2861 files changed, 451393 insertions, 0 deletions

diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..9760566
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2003
+# Pavel Bartusek, Sysgo Real-Time Solutions AG, pba@sysgo.de
+#
+
+ARCH := x86
+CROSS_COMPILE := 
+CC = $(CROSS_COMPILE)gcc
+AR = $(CROSS_COMPILE)ar
+NOSTDINC_FLAGS = -nostdinc -isystem $(shell $(CC) -print-file-name=include)
+CFLAGS += $(NOSTDINC_FLAGS) -I include -I arch/$(ARCH)/include -include include/linux/kconfig.h -D__KERNEL__ -D__UBOOT__ -Wall -fno-builtin
+
+obj := ext4fs.o ext4_common.o dev.o
+ifeq ($(CONFIG_EXT4_WRITE), y)
+	CFLAGS += -DCONFIG_EXT4_WRITE=1
+	obj += ext4_write.o ext4_journal.o crc16.o
+endif
+
+ext4.a: $(obj)
+	$(AR) r ext4.a $^
+
+clean:
+	bash -c 'rm -f *.o *.a'
diff --git a/arch/arc/include/asm/arc-bcr.h b/arch/arc/include/asm/arc-bcr.h
new file mode 100644
index 0000000..823906d
--- /dev/null
+++ b/arch/arc/include/asm/arc-bcr.h
@@ -0,0 +1,77 @@
+/*
+ * ARC Build Configuration Registers, with encoded hardware config
+ *
+ * Copyright (C) 2018 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARC_BCR_H
+#define __ARC_BCR_H
+#ifndef __ASSEMBLY__
+
+#include <config.h>
+
+union bcr_di_cache {
+	struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+		unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
+#else
+		unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
+#endif
+	} fields;
+	unsigned int word;
+};
+
+union bcr_slc_cfg {
+	struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+		unsigned int pad:24, way:2, lsz:2, sz:4;
+#else
+		unsigned int sz:4, lsz:2, way:2, pad:24;
+#endif
+	} fields;
+	unsigned int word;
+};
+
+union bcr_generic {
+	struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+		unsigned int pad:24, ver:8;
+#else
+		unsigned int ver:8, pad:24;
+#endif
+	} fields;
+	unsigned int word;
+};
+
+union bcr_clust_cfg {
+	struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+		unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
+#else
+		unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
+#endif
+	} fields;
+	unsigned int word;
+};
+
+union bcr_mmu_4 {
+	struct {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+	unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
+		     n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
+#else
+	/*           DTLB      ITLB      JES        JE         JA      */
+	unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
+		     pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
+#endif
+	} fields;
+	unsigned int word;
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARC_BCR_H */
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
new file mode 100644
index 0000000..fff6591
--- /dev/null
+++ b/arch/arc/include/asm/arcregs.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_ARC_ARCREGS_H
+#define _ASM_ARC_ARCREGS_H
+
+#include <asm/cache.h>
+#include <config.h>
+
+/*
+ * ARC architecture has additional address space - auxiliary registers.
+ * These registers are mostly used for configuration purposes.
+ * These registers are not memory mapped and special commands are used for
+ * access: "lr"/"sr".
+ */
+
+/*
+ * Typically 8 least significant bits of Build Configuration Register (BCR)
+ * describe version of the HW block in question. Moreover if decoded version
+ * is 0 this means given HW block is absent - this is especially useful because
+ * we may safely read BRC regardless HW block existence while an attempt to
+ * access any other AUX regs associated with this HW block lead to imediate
+ * "instruction error" exception.
+ *
+ * I.e. before using any cofigurable HW block it's required to make sure it
+ * exists at all, and for that we introduce a special macro below.
+ */
+#define ARC_BCR_VERSION_MASK	GENMASK(7, 0)
+#define ARC_FEATURE_EXISTS(bcr)	!!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK)
+
+#define ARC_AUX_IDENTITY	0x04
+#define ARC_AUX_STATUS32	0x0a
+
+/* STATUS32 Bits Positions */
+#define STATUS_AD_BIT		19	/* Enable unaligned access */
+
+/* Instruction cache related auxiliary registers */
+#define ARC_AUX_IC_IVIC		0x10
+#define ARC_AUX_IC_CTRL		0x11
+#define ARC_AUX_IC_IVIL		0x19
+#if (CONFIG_ARC_MMU_VER == 3)
+#define ARC_AUX_IC_PTAG		0x1E
+#endif
+#define ARC_BCR_IC_BUILD	0x77
+#define AUX_AUX_CACHE_LIMIT		0x5D
+#define ARC_AUX_NON_VOLATILE_LIMIT	0x5E
+
+/* ICCM and DCCM auxiliary registers */
+#define ARC_AUX_DCCM_BASE	0x18	/* DCCM Base Addr ARCv2 */
+#define ARC_AUX_ICCM_BASE	0x208	/* ICCM Base Addr ARCv2 */
+
+/* Timer related auxiliary registers */
+#define ARC_AUX_TIMER0_CNT	0x21	/* Timer 0 count */
+#define ARC_AUX_TIMER0_CTRL	0x22	/* Timer 0 control */
+#define ARC_AUX_TIMER0_LIMIT	0x23	/* Timer 0 limit */
+
+#define ARC_AUX_TIMER1_CNT	0x100	/* Timer 1 count */
+#define ARC_AUX_TIMER1_CTRL	0x101	/* Timer 1 control */
+#define ARC_AUX_TIMER1_LIMIT	0x102	/* Timer 1 limit */
+
+#define ARC_AUX_INTR_VEC_BASE	0x25
+
+/* Data cache related auxiliary registers */
+#define ARC_AUX_DC_IVDC		0x47
+#define ARC_AUX_DC_CTRL		0x48
+
+#define ARC_AUX_DC_IVDL		0x4A
+#define ARC_AUX_DC_FLSH		0x4B
+#define ARC_AUX_DC_FLDL		0x4C
+#if (CONFIG_ARC_MMU_VER == 3)
+#define ARC_AUX_DC_PTAG		0x5C
+#endif
+#define ARC_BCR_DC_BUILD	0x72
+#define ARC_BCR_SLC		0xce
+#define ARC_AUX_SLC_CONFIG	0x901
+#define ARC_AUX_SLC_CTRL	0x903
+#define ARC_AUX_SLC_FLUSH	0x904
+#define ARC_AUX_SLC_INVALIDATE	0x905
+#define ARC_AUX_SLC_IVDL	0x910
+#define ARC_AUX_SLC_FLDL	0x912
+#define ARC_AUX_SLC_RGN_START	0x914
+#define ARC_AUX_SLC_RGN_START1	0x915
+#define ARC_AUX_SLC_RGN_END	0x916
+#define ARC_AUX_SLC_RGN_END1	0x917
+#define ARC_BCR_CLUSTER		0xcf
+
+/* MMU Management regs */
+#define ARC_AUX_MMU_BCR		0x6f
+
+/* IO coherency related auxiliary registers */
+#define ARC_AUX_IO_COH_ENABLE	0x500
+#define ARC_AUX_IO_COH_PARTIAL	0x501
+#define ARC_AUX_IO_COH_AP0_BASE	0x508
+#define ARC_AUX_IO_COH_AP0_SIZE	0x509
+
+/* XY-memory related */
+#define ARC_AUX_XY_BUILD	0x79
+
+/* DSP-extensions related auxiliary registers */
+#define ARC_AUX_DSP_BUILD	0x7A
+
+/* ARC Subsystems related auxiliary registers */
+#define ARC_AUX_SUBSYS_BUILD	0xF0
+
+#ifndef __ASSEMBLY__
+/* Accessors for auxiliary registers */
+#define read_aux_reg(reg)	__builtin_arc_lr(reg)
+
+/* gcc builtin sr needs reg param to be long immediate */
+#define write_aux_reg(reg_immed, val)		\
+		__builtin_arc_sr((unsigned int)val, reg_immed)
+
+/* ARCNUM [15:8] - field to identify each core in a multi-core system */
+#define CPU_ID_GET()	((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
+
+static const inline int is_isa_arcv2(void)
+{
+	return IS_ENABLED(CONFIG_ISA_ARCV2);
+}
+
+static const inline int is_isa_arcompact(void)
+{
+	return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARC_ARCREGS_H */
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
new file mode 100644
index 0000000..c6dd28e
--- /dev/null
+++ b/arch/arc/include/asm/bitops.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_BITOPS_H
+#define __ASM_ARC_BITOPS_H
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+#endif /* __ASM_ARC_BITOPS_H */
diff --git a/arch/arc/include/asm/byteorder.h b/arch/arc/include/asm/byteorder.h
new file mode 100644
index 0000000..8c171bb
--- /dev/null
+++ b/arch/arc/include/asm/byteorder.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_BYTEORDER_H
+#define __ASM_ARC_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+	#define __BYTEORDER_HAS_U64__
+	#define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __LITTLE_ENDIAN__
+	#include <linux/byteorder/little_endian.h>
+#else
+	#include <linux/byteorder/big_endian.h>
+#endif	/* CONFIG_SYS_BIG_ENDIAN */
+
+#endif	/* ASM_ARC_BYTEORDER_H */
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
new file mode 100644
index 0000000..0fdcf2d
--- /dev/null
+++ b/arch/arc/include/asm/cache.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_CACHE_H
+#define __ASM_ARC_CACHE_H
+
+#include <config.h>
+
+/*
+ * As of today we may handle any L1 cache line length right in software.
+ * For that essentially cache line length is a variable not constant.
+ * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length
+ * that may exist in either L1 or L2 (AKA SLC) caches on ARC.
+ */
+#define ARCH_DMA_MINALIGN	128
+
+/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
+#define CONFIG_SYS_CACHELINE_SIZE	ARCH_DMA_MINALIGN
+
+#if defined(ARC_MMU_ABSENT)
+#define CONFIG_ARC_MMU_VER 0
+#elif defined(CONFIG_ARC_MMU_V2)
+#define CONFIG_ARC_MMU_VER 2
+#elif defined(CONFIG_ARC_MMU_V3)
+#define CONFIG_ARC_MMU_VER 3
+#elif defined(CONFIG_ARC_MMU_V4)
+#define CONFIG_ARC_MMU_VER 4
+#endif
+
+#ifndef __ASSEMBLY__
+
+void cache_init(void);
+void flush_n_invalidate_dcache_all(void);
+void sync_n_cleanup_cache_all(void);
+
+static const inline int is_ioc_enabled(void)
+{
+	return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARC_CACHE_H */
diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h
new file mode 100644
index 0000000..d88c361
--- /dev/null
+++ b/arch/arc/include/asm/config.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_CONFIG_H_
+#define __ASM_ARC_CONFIG_H_
+
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#define CONFIG_LMB
+
+#endif /*__ASM_ARC_CONFIG_H_ */
diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h
new file mode 100644
index 0000000..8f9c83d
--- /dev/null
+++ b/arch/arc/include/asm/global_data.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef	__ASM_ARC_GLOBAL_DATA_H
+#define __ASM_ARC_GLOBAL_DATA_H
+
+#include <config.h>
+
+#ifndef __ASSEMBLY__
+/* Architecture-specific global data */
+struct arch_global_data {
+	int l1_line_sz;
+#if defined(CONFIG_ISA_ARCV2)
+	int slc_line_sz;
+#endif
+};
+#endif /* __ASSEMBLY__ */
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("r25")
+
+#endif /* __ASM_ARC_GLOBAL_DATA_H */
diff --git a/arch/arc/include/asm/gpio.h b/arch/arc/include/asm/gpio.h
new file mode 100644
index 0000000..306ab4c
--- /dev/null
+++ b/arch/arc/include/asm/gpio.h
@@ -0,0 +1 @@
+#include <asm-generic/gpio.h>
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
new file mode 100644
index 0000000..fa844b5
--- /dev/null
+++ b/arch/arc/include/asm/io.h
@@ -0,0 +1,282 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_IO_H
+#define __ASM_ARC_IO_H
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+#ifdef __ARCHS__
+
+/*
+ * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
+ * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
+ *
+ * Explicit barrier provided by DMB instruction
+ *  - Operand supports fine grained load/store/load+store semantics
+ *  - Ensures that selected memory operation issued before it will complete
+ *    before any subsequent memory operation of same type
+ *  - DMB guarantees SMP as well as local barrier semantics
+ *    (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
+ *    UP: barrier(), SMP: smp_*mb == *mb)
+ *  - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
+ *    in the general case. Plus it only provides full barrier.
+ */
+
+#define mb()	asm volatile("dmb 3\n" : : : "memory")
+#define rmb()	asm volatile("dmb 1\n" : : : "memory")
+#define wmb()	asm volatile("dmb 2\n" : : : "memory")
+
+#else
+
+/*
+ * ARCompact based cores (ARC700) only have SYNC instruction which is super
+ * heavy weight as it flushes the pipeline as well.
+ * There are no real SMP implementations of such cores.
+ */
+
+#define mb()	asm volatile("sync\n" : : : "memory")
+#endif
+
+#ifdef __ARCHS__
+#define __iormb()		rmb()
+#define __iowmb()		wmb()
+#else
+#define __iormb()		asm volatile("" : : : "memory")
+#define __iowmb()		asm volatile("" : : : "memory")
+#endif
+
+static inline void sync(void)
+{
+	/* Not yet implemented */
+}
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+	u8 b;
+
+	__asm__ __volatile__("ldb%U1	%0, %1\n"
+			     : "=r" (b)
+			     : "m" (*(volatile u8 __force *)addr)
+			     : "memory");
+	return b;
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+	u16 s;
+
+	__asm__ __volatile__("ldw%U1	%0, %1\n"
+			     : "=r" (s)
+			     : "m" (*(volatile u16 __force *)addr)
+			     : "memory");
+	return s;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+	u32 w;
+
+	__asm__ __volatile__("ld%U1	%0, %1\n"
+			     : "=r" (w)
+			     : "m" (*(volatile u32 __force *)addr)
+			     : "memory");
+	return w;
+}
+
+static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
+{
+	__asm__ __volatile__("stb%U1	%0, %1\n"
+			     :
+			     : "r" (b), "m" (*(volatile u8 __force *)addr)
+			     : "memory");
+}
+
+static inline void __raw_writew(u16 s, volatile void __iomem *addr)
+{
+	__asm__ __volatile__("stw%U1	%0, %1\n"
+			     :
+			     : "r" (s), "m" (*(volatile u16 __force *)addr)
+			     : "memory");
+}
+
+static inline void __raw_writel(u32 w, volatile void __iomem *addr)
+{
+	__asm__ __volatile__("st%U1	%0, %1\n"
+			     :
+			     : "r" (w), "m" (*(volatile u32 __force *)addr)
+			     : "memory");
+}
+
+static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "stb.ab	r8, [r1, 1]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (bytelen)
+			      : "r8");
+	return bytelen;
+}
+
+static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "stw.ab	r8, [r1, 2]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (wordlen)
+			      : "r8");
+	return wordlen;
+}
+
+static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
+{
+	__asm__ __volatile__ ("1:ld.di	r8, [r0]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab	r8, [r1, 4]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (longlen)
+			      : "r8");
+	return longlen;
+}
+
+static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
+{
+	__asm__ __volatile__ ("1:ldb.ab	r8, [r1, 1]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (bytelen)
+			      : "r8");
+	return bytelen;
+}
+
+static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
+{
+	__asm__ __volatile__ ("1:ldw.ab	r8, [r1, 2]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (wordlen)
+			      : "r8");
+	return wordlen;
+}
+
+static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
+{
+	__asm__ __volatile__ ("1:ld.ab	r8, [r1, 4]\n"
+			      "sub.f	r2, r2, 1\n"
+			      "bnz.d	1b\n"
+			      "st.ab.di	r8, [r0, 0]\n"
+			      :
+			      : "r" (addr), "r" (data), "r" (longlen)
+			      : "r8");
+	return longlen;
+}
+
+/*
+ * MMIO can also get buffered/optimized in micro-arch, so barriers needed
+ * Based on ARM model for the typical use case
+ *
+ *	<ST [DMA buffer]>
+ *	<writel MMIO "go" reg>
+ *  or:
+ *	<readl MMIO "status" reg>
+ *	<LD [DMA buffer]>
+ *
+ * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
+ */
+#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(); __v; })
+#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(); __v; })
+#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; })
+
+#define writeb(v,c)		({ __iowmb(); writeb_relaxed(v,c); })
+#define writew(v,c)		({ __iowmb(); writew_relaxed(v,c); })
+#define writel(v,c)		({ __iowmb(); writel_relaxed(v,c); })
+
+/*
+ * Relaxed API for drivers which can handle barrier ordering themselves
+ *
+ * Also these are defined to perform little endian accesses.
+ * To provide the typical device register semantics of fixed endian,
+ * swap the byte order for Big Endian
+ *
+ * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
+ */
+#define readb_relaxed(c)	__raw_readb(c)
+#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
+					__raw_readw(c)); __r; })
+#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
+					__raw_readl(c)); __r; })
+
+#define writeb_relaxed(v,c)	__raw_writeb(v,c)
+#define writew_relaxed(v,c)	__raw_writew((__force u16) cpu_to_le16(v),c)
+#define writel_relaxed(v,c)	__raw_writel((__force u32) cpu_to_le32(v),c)
+
+#define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v)	out_arch(l, le32, a, v)
+#define out_le16(a, v)	out_arch(w, le16, a, v)
+
+#define in_le32(a)	in_arch(l, le32, a)
+#define in_le16(a)	in_arch(w, le16, a)
+
+#define out_be32(a, v)	out_arch(l, be32, a, v)
+#define out_be16(a, v)	out_arch(w, be16, a, v)
+
+#define in_be32(a)	in_arch(l, be32, a)
+#define in_be16(a)	in_arch(w, be16, a)
+
+#define out_8(a, v)	__raw_writeb(v, a)
+#define in_8(a)		__raw_readb(a)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+#include <asm-generic/io.h>
+
+#endif	/* __ASM_ARC_IO_H */
diff --git a/arch/arc/include/asm/linkage.h b/arch/arc/include/asm/linkage.h
new file mode 100644
index 0000000..2d42ed4
--- /dev/null
+++ b/arch/arc/include/asm/linkage.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2015 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_LINKAGE_H
+#define __ASM_ARC_LINKAGE_H
+
+#define ASM_NL		 `	/* use '`' to mark new line in macro */
+
+#endif /* __ASM_ARC_LINKAGE_H */
diff --git a/arch/arc/include/asm/posix_types.h b/arch/arc/include/asm/posix_types.h
new file mode 100644
index 0000000..13838cb
--- /dev/null
+++ b/arch/arc/include/asm/posix_types.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_POSIX_TYPES_H
+#define __ASM_ARC_POSIX_TYPES_H
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+#ifdef __GNUC__
+typedef __SIZE_TYPE__		__kernel_size_t;
+#else
+typedef unsigned int		__kernel_size_t;
+#endif
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+#endif	/* __ASM_ARC_POSIX_TYPES_H */
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
new file mode 100644
index 0000000..03e31fb
--- /dev/null
+++ b/arch/arc/include/asm/processor.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_ARC_PROCESSOR_H
+#define _ASM_ARC_PROCESSOR_H
+
+/* This file is required by some generic code like USB etc */
+
+#endif /* _ASM_ARC_PROCESSOR_H */
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
new file mode 100644
index 0000000..6965e89
--- /dev/null
+++ b/arch/arc/include/asm/ptrace.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_PTRACE_H
+#define __ASM_ARC_PTRACE_H
+
+struct pt_regs {
+	long bta;
+	long lp_start;
+	long lp_end;
+	long lp_count;
+	long status32;
+	long ret;
+	long blink;
+	long fp;
+	long r26;	/* gp */
+	long r25;
+	long r24;
+	long r23;
+	long r22;
+	long r21;
+	long r20;
+	long r19;
+	long r18;
+	long r17;
+	long r16;
+	long r15;
+	long r14;
+	long r13;
+	long r12;
+	long r11;
+	long r10;
+	long r9;
+	long r8;
+	long r7;
+	long r6;
+	long r5;
+	long r4;
+	long r3;
+	long r2;
+	long r1;
+	long r0;
+	long sp;
+	long ecr;
+};
+
+#endif /* __ASM_ARC_PTRACE_H */
diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h
new file mode 100644
index 0000000..1c9c9db
--- /dev/null
+++ b/arch/arc/include/asm/sections.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_SECTIONS_H
+#define __ASM_ARC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern ulong __ivt_start;
+extern ulong __ivt_end;
+
+#endif /* __ASM_ARC_SECTIONS_H */
diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/arch/arc/include/asm/string.h
@@ -0,0 +1 @@
+
diff --git a/arch/arc/include/asm/types.h b/arch/arc/include/asm/types.h
new file mode 100644
index 0000000..f31dcdf
--- /dev/null
+++ b/arch/arc/include/asm/types.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_TYPES_H
+#define __ASM_ARC_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+typedef unsigned short umode_t;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __ASM_ARC_TYPES_H */
diff --git a/arch/arc/include/asm/u-boot-arc.h b/arch/arc/include/asm/u-boot-arc.h
new file mode 100644
index 0000000..dd2c094
--- /dev/null
+++ b/arch/arc/include/asm/u-boot-arc.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_U_BOOT_ARC_H__
+#define __ASM_ARC_U_BOOT_ARC_H__
+
+int arch_early_init_r(void);
+
+void	board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
+void	board_init_f_r(void) __attribute__ ((noreturn));
+
+#endif	/* __ASM_ARC_U_BOOT_ARC_H__ */
diff --git a/arch/arc/include/asm/u-boot.h b/arch/arc/include/asm/u-boot.h
new file mode 100644
index 0000000..36c2207
--- /dev/null
+++ b/arch/arc/include/asm/u-boot.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARC_U_BOOT_H__
+#define __ASM_ARC_U_BOOT_H__
+
+#include <asm-generic/u-boot.h>
+#include <asm/u-boot-arc.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_ARC
+
+#endif	/* __ASM_ARC_U_BOOT_H__ */
diff --git a/arch/arc/include/asm/unaligned.h b/arch/arc/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/arc/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
diff --git a/arch/arm/include/asm/arch-am33xx/chilisom.h b/arch/arm/include/asm/arch-am33xx/chilisom.h
new file mode 100644
index 0000000..493be64
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/chilisom.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Grinn
+ */
+
+#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__
+#define __ARCH_ARM_MACH_CHILISOM_SOM_H__
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+void chilisom_enable_pin_mux(void);
+void chilisom_spl_board_init(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
new file mode 100644
index 0000000..6579cc0
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * clk-synthesizer.h
+ *
+ * Clock synthesizer header
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef __CLK_SYNTHESIZER_H
+#define __CLK_SYNTHESIZER_H
+
+#include <common.h>
+
+#define CLK_SYNTHESIZER_ID_REG		0x0
+#define CLK_SYNTHESIZER_XCSEL		0x05
+#define CLK_SYNTHESIZER_MUX_REG		0x14
+#define CLK_SYNTHESIZER_PDIV2_REG	0x16
+#define CLK_SYNTHESIZER_PDIV3_REG	0x17
+
+#define CLK_SYNTHESIZER_BYTE_MODE	0x80
+
+/**
+ * struct clk_synth: This structure holds data neeed for configuring
+ *		     for clock synthesizer.
+ * @id: The id of synthesizer
+ * @capacitor: value of the capacitor attached
+ * @mux: mux settings.
+ * @pdiv2: Div to be applied to second output
+ * @pdiv3: Div to be applied to third output
+ */
+struct clk_synth {
+	u32 id;
+	u32 capacitor;
+	u32 mux;
+	u32 pdiv2;
+	u32 pdiv3;
+};
+
+int setup_clock_synthesizer(struct clk_synth *data);
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
new file mode 100644
index 0000000..dc7a9b1
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * clock.h
+ *
+ * clock header
+ *
+ * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef _CLOCKS_H_
+#define _CLOCKS_H_
+
+#include <asm/arch/clocks_am33xx.h>
+#include <asm/arch/hardware.h>
+
+#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
+#include <asm/arch/clock_ti81xx.h>
+#endif
+
+#define LDELAY 1000000
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_SSC_EN_SHIFT		12
+#define CM_CLKMODE_DPLL_SSC_EN_MASK		(1 << 12)
+#define CM_CLKMODE_DPLL_SSC_ACK_MASK		(1 << 13)
+#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK	(1 << 14)
+#define CM_CLKMODE_DPLL_SSC_TYPE_MASK		(1 << 15)
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+
+struct dpll_params {
+	u32 m;
+	u32 n;
+	s8 m2;
+	s8 m3;
+	s8 m4;
+	s8 m5;
+	s8 m6;
+};
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_dpll;
+	u32 cm_div_m5_dpll;
+	u32 cm_div_m6_dpll;
+};
+
+extern const struct dpll_regs dpll_mpu_regs;
+extern const struct dpll_regs dpll_core_regs;
+extern const struct dpll_regs dpll_per_regs;
+extern const struct dpll_regs dpll_ddr_regs;
+extern const struct dpll_regs dpll_disp_regs;
+extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];
+extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ];
+extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ];
+
+extern struct cm_wkuppll *const cmwkup;
+
+const struct dpll_params *get_dpll_mpu_params(void);
+const struct dpll_params *get_dpll_core_params(void);
+const struct dpll_params *get_dpll_per_params(void);
+const struct dpll_params *get_dpll_ddr_params(void);
+void scale_vcores(void);
+void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
+void prcm_init(void);
+void enable_basic_clocks(void);
+
+void rtc_only_update_board_type(u32 btype);
+u32 rtc_only_get_board_type(void);
+void rtc_only_prcm_init(void);
+void rtc_only_enable_basic_clocks(void);
+
+void do_enable_clocks(u32 *const *, u32 *const *, u8);
+void do_disable_clocks(u32 *const *, u32 *const *, u8);
+
+void set_mpu_spreadspectrum(int permille);
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
new file mode 100644
index 0000000..f069922
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h
@@ -0,0 +1,142 @@
+/*
+ * ti81xx.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ */
+
+#ifndef _CLOCK_TI81XX_H_
+#define _CLOCK_TI81XX_H_
+
+#define PRCM_MOD_EN     0x2
+
+#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
+#define CM_ALWON_BASE   (PRCM_BASE + 0x1400)
+
+struct cm_def {
+	unsigned int resv0[2];
+	unsigned int l3fastclkstctrl;
+	unsigned int resv1[1];
+	unsigned int pciclkstctrl;
+	unsigned int resv2[1];
+	unsigned int ducaticlkstctrl;
+	unsigned int resv3[1];
+	unsigned int emif0clkctrl;
+	unsigned int emif1clkctrl;
+	unsigned int dmmclkctrl;
+	unsigned int fwclkctrl;
+	unsigned int resv4[10];
+	unsigned int usbclkctrl;
+	unsigned int resv5[1];
+	unsigned int sataclkctrl;
+	unsigned int resv6[4];
+	unsigned int ducaticlkctrl;
+	unsigned int pciclkctrl;
+};
+
+struct cm_alwon {
+	unsigned int l3slowclkstctrl;
+	unsigned int ethclkstctrl;
+	unsigned int l3medclkstctrl;
+	unsigned int mmu_clkstctrl;
+	unsigned int mmucfg_clkstctrl;
+	unsigned int ocmc0clkstctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int vcpclkstctrl;
+#elif defined(CONFIG_TI816X)
+	unsigned int ocmc1clkstctrl;
+#endif
+	unsigned int mpuclkstctrl;
+	unsigned int sysclk4clkstctrl;
+	unsigned int sysclk5clkstctrl;
+	unsigned int sysclk6clkstctrl;
+	unsigned int rtcclkstctrl;
+	unsigned int l3fastclkstctrl;
+	unsigned int resv0[67];
+	unsigned int mcasp0clkctrl;
+	unsigned int mcasp1clkctrl;
+	unsigned int mcasp2clkctrl;
+	unsigned int mcbspclkctrl;
+	unsigned int uart0clkctrl;
+	unsigned int uart1clkctrl;
+	unsigned int uart2clkctrl;
+	unsigned int gpio0clkctrl;
+	unsigned int gpio1clkctrl;
+	unsigned int i2c0clkctrl;
+	unsigned int i2c1clkctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int mcasp345clkctrl;
+	unsigned int atlclkctrl;
+	unsigned int mlbclkctrl;
+	unsigned int pataclkctrl;
+	unsigned int resv1[1];
+	unsigned int uart3clkctrl;
+	unsigned int uart4clkctrl;
+	unsigned int uart5clkctrl;
+#elif defined(CONFIG_TI816X)
+	unsigned int resv1[1];
+	unsigned int timer1clkctrl;
+	unsigned int timer2clkctrl;
+	unsigned int timer3clkctrl;
+	unsigned int timer4clkctrl;
+	unsigned int timer5clkctrl;
+	unsigned int timer6clkctrl;
+	unsigned int timer7clkctrl;
+#endif
+	unsigned int wdtimerclkctrl;
+	unsigned int spiclkctrl;
+	unsigned int mailboxclkctrl;
+	unsigned int spinboxclkctrl;
+	unsigned int mmudataclkctrl;
+	unsigned int resv2[2];
+	unsigned int mmucfgclkctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int resv3[2];
+#elif defined(CONFIG_TI816X)
+	unsigned int resv3[1];
+	unsigned int sdioclkctrl;
+#endif
+	unsigned int ocmc0clkctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int vcpclkctrl;
+#elif defined(CONFIG_TI816X)
+	unsigned int ocmc1clkctrl;
+#endif
+	unsigned int resv4[2];
+	unsigned int controlclkctrl;
+	unsigned int resv5[2];
+	unsigned int gpmcclkctrl;
+	unsigned int ethernet0clkctrl;
+	unsigned int ethernet1clkctrl;
+	unsigned int mpuclkctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int debugssclkctrl;
+#elif defined(CONFIG_TI816X)
+	unsigned int resv6[1];
+#endif
+	unsigned int l3clkctrl;
+	unsigned int l4hsclkctrl;
+	unsigned int l4lsclkctrl;
+	unsigned int rtcclkctrl;
+	unsigned int tpccclkctrl;
+	unsigned int tptc0clkctrl;
+	unsigned int tptc1clkctrl;
+	unsigned int tptc2clkctrl;
+	unsigned int tptc3clkctrl;
+#if defined(CONFIG_TI814X)
+	unsigned int resv6[4];
+	unsigned int dcan01clkctrl;
+	unsigned int mmchs0clkctrl;
+	unsigned int mmchs1clkctrl;
+	unsigned int mmchs2clkctrl;
+	unsigned int custefuseclkctrl;
+#elif defined(CONFIG_TI816X)
+	unsigned int sr0clkctrl;
+	unsigned int sr1clkctrl;
+#endif
+};
+
+#endif /* _CLOCK_TI81XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
new file mode 100644
index 0000000..e5ad507
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * clocks_am33xx.h
+ *
+ * AM33xx clock define
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef _CLOCKS_AM33XX_H_
+#define _CLOCKS_AM33XX_H_
+
+/* MAIN PLL Fdll supported frequencies */
+#define MPUPLL_M_1000	1000
+#define MPUPLL_M_800	800
+#define MPUPLL_M_720	720
+#define MPUPLL_M_600	600
+#define MPUPLL_M_500	500
+#define MPUPLL_M_300	300
+
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
+#define CM_DLL_CTRL_NO_OVERRIDE	0x0
+#define CM_DLL_READYST		0x4
+
+#define NUM_OPPS	6
+
+extern void enable_dmm_clocks(void);
+extern void enable_emif_clocks(void);
+extern const struct dpll_params dpll_core_opp100;
+extern struct dpll_params dpll_mpu_opp100;
+
+#endif	/* endif _CLOCKS_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
new file mode 100644
index 0000000..9b819b0
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -0,0 +1,611 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * cpu.h
+ *
+ * AM33xx specific header file
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _AM33XX_CPU_H
+#define _AM33XX_CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#include <asm/arch/hardware.h>
+
+#define CL_BIT(x)			(0 << x)
+
+/* Timer register bits */
+#define TCLR_ST				BIT(0)	/* Start=1 Stop=0 */
+#define TCLR_AR				BIT(1)	/* Auto reload */
+#define TCLR_PRE			BIT(5)	/* Pre-scaler enable */
+#define TCLR_PTV_SHIFT			(2)	/* Pre-scaler shift value */
+#define TCLR_PRE_DISABLE		CL_BIT(5) /* Pre-scalar disable */
+#define TCLR_CE				BIT(6)	/* compare mode enable */
+#define TCLR_SCPWM			BIT(7)	/* pwm outpin behaviour */
+#define TCLR_TCM			BIT(8)	/* edge detection of input pin*/
+#define TCLR_TRG_SHIFT			(10)	/* trigmode on pwm outpin */
+#define TCLR_PT				BIT(12)	/* pulse/toggle mode of outpin*/
+#define TCLR_CAPTMODE			BIT(13) /* capture mode */
+#define TCLR_GPOCFG			BIT(14)	/* 0=output,1=input */
+
+#define TCFG_RESET			BIT(0)	/* software reset */
+#define TCFG_EMUFREE			BIT(1)	/* behaviour of tmr on debug */
+#define TCFG_IDLEMOD_SHIFT		(2)	/* power management */
+
+/* cpu-id for AM43XX AM33XX and TI81XX family */
+#define AM437X				0xB98C
+#define AM335X				0xB944
+#define TI81XX				0xB81E
+#define DEVICE_ID			(CTRL_BASE + 0x0600)
+#define DEVICE_ID_MASK			0x1FFF
+#define PACKAGE_TYPE_SHIFT		16
+#define PACKAGE_TYPE_MASK		(3 << 16)
+
+/* Package Type */
+#define PACKAGE_TYPE_UNDEFINED		0x0
+#define PACKAGE_TYPE_ZCZ		0x1
+#define PACKAGE_TYPE_ZCE		0x2
+#define PACKAGE_TYPE_RESERVED		0x3
+
+/* MPU max frequencies */
+#define AM335X_ZCZ_300			0x1FEF
+#define AM335X_ZCZ_600			0x1FAF
+#define AM335X_ZCZ_720			0x1F2F
+#define AM335X_ZCZ_800			0x1E2F
+#define AM335X_ZCZ_1000			0x1C2F
+#define AM335X_ZCE_300			0x1FDF
+#define AM335X_ZCE_600			0x1F9F
+
+/* This gives the status of the boot mode pins on the evm */
+#define SYSBOOT_MASK			(BIT(0) | BIT(1) | BIT(2)\
+					| BIT(3) | BIT(4))
+
+#define PRM_RSTCTRL_RESET		0x01
+#define PRM_RSTST_WARM_RESET_MASK	0x232
+
+/* EMIF Control register bits */
+#define EMIF_CTRL_DEVOFF	BIT(0)
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+#include <asm/ti-common/omap_wdt.h>
+
+#ifndef CONFIG_AM43XX
+/* Encapsulating core pll registers */
+struct cm_wkuppll {
+	unsigned int wkclkstctrl;	/* offset 0x00 */
+	unsigned int wkctrlclkctrl;	/* offset 0x04 */
+	unsigned int wkgpio0clkctrl;	/* offset 0x08 */
+	unsigned int wkl4wkclkctrl;	/* offset 0x0c */
+	unsigned int timer0clkctrl;	/* offset 0x10 */
+	unsigned int resv2[3];
+	unsigned int idlestdpllmpu;	/* offset 0x20 */
+	unsigned int sscdeltamstepdllmpu; /* off  0x24 */
+	unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
+	unsigned int clkseldpllmpu;	/* offset 0x2c */
+	unsigned int resv4[1];
+	unsigned int idlestdpllddr;	/* offset 0x34 */
+	unsigned int resv5[2];
+	unsigned int clkseldpllddr;	/* offset 0x40 */
+	unsigned int resv6[4];
+	unsigned int clkseldplldisp;	/* offset 0x54 */
+	unsigned int resv7[1];
+	unsigned int idlestdpllcore;	/* offset 0x5c */
+	unsigned int resv8[2];
+	unsigned int clkseldpllcore;	/* offset 0x68 */
+	unsigned int resv9[1];
+	unsigned int idlestdpllper;	/* offset 0x70 */
+	unsigned int resv10[2];
+	unsigned int clkdcoldodpllper;	/* offset 0x7c */
+	unsigned int divm4dpllcore;	/* offset 0x80 */
+	unsigned int divm5dpllcore;	/* offset 0x84 */
+	unsigned int clkmoddpllmpu;	/* offset 0x88 */
+	unsigned int clkmoddpllper;	/* offset 0x8c */
+	unsigned int clkmoddpllcore;	/* offset 0x90 */
+	unsigned int clkmoddpllddr;	/* offset 0x94 */
+	unsigned int clkmoddplldisp;	/* offset 0x98 */
+	unsigned int clkseldpllper;	/* offset 0x9c */
+	unsigned int divm2dpllddr;	/* offset 0xA0 */
+	unsigned int divm2dplldisp;	/* offset 0xA4 */
+	unsigned int divm2dpllmpu;	/* offset 0xA8 */
+	unsigned int divm2dpllper;	/* offset 0xAC */
+	unsigned int resv11[1];
+	unsigned int wkup_uart0ctrl;	/* offset 0xB4 */
+	unsigned int wkup_i2c0ctrl;	/* offset 0xB8 */
+	unsigned int wkup_adctscctrl;	/* offset 0xBC */
+	unsigned int resv12;
+	unsigned int timer1clkctrl;	/* offset 0xC4 */
+	unsigned int resv13[4];
+	unsigned int divm6dpllcore;	/* offset 0xD8 */
+};
+
+/**
+ * Encapsulating peripheral functional clocks
+ * pll registers
+ */
+struct cm_perpll {
+	unsigned int l4lsclkstctrl;	/* offset 0x00 */
+	unsigned int l3sclkstctrl;	/* offset 0x04 */
+	unsigned int l4fwclkstctrl;	/* offset 0x08 */
+	unsigned int l3clkstctrl;	/* offset 0x0c */
+	unsigned int resv1;
+	unsigned int cpgmac0clkctrl;	/* offset 0x14 */
+	unsigned int lcdclkctrl;	/* offset 0x18 */
+	unsigned int usb0clkctrl;	/* offset 0x1C */
+	unsigned int resv2;
+	unsigned int tptc0clkctrl;	/* offset 0x24 */
+	unsigned int emifclkctrl;	/* offset 0x28 */
+	unsigned int ocmcramclkctrl;	/* offset 0x2c */
+	unsigned int gpmcclkctrl;	/* offset 0x30 */
+	unsigned int mcasp0clkctrl;	/* offset 0x34 */
+	unsigned int uart5clkctrl;	/* offset 0x38 */
+	unsigned int mmc0clkctrl;	/* offset 0x3C */
+	unsigned int elmclkctrl;	/* offset 0x40 */
+	unsigned int i2c2clkctrl;	/* offset 0x44 */
+	unsigned int i2c1clkctrl;	/* offset 0x48 */
+	unsigned int spi0clkctrl;	/* offset 0x4C */
+	unsigned int spi1clkctrl;	/* offset 0x50 */
+	unsigned int resv3[3];
+	unsigned int l4lsclkctrl;	/* offset 0x60 */
+	unsigned int l4fwclkctrl;	/* offset 0x64 */
+	unsigned int mcasp1clkctrl;	/* offset 0x68 */
+	unsigned int uart1clkctrl;	/* offset 0x6C */
+	unsigned int uart2clkctrl;	/* offset 0x70 */
+	unsigned int uart3clkctrl;	/* offset 0x74 */
+	unsigned int uart4clkctrl;	/* offset 0x78 */
+	unsigned int timer7clkctrl;	/* offset 0x7C */
+	unsigned int timer2clkctrl;	/* offset 0x80 */
+	unsigned int timer3clkctrl;	/* offset 0x84 */
+	unsigned int timer4clkctrl;	/* offset 0x88 */
+	unsigned int resv4[8];
+	unsigned int gpio1clkctrl;	/* offset 0xAC */
+	unsigned int gpio2clkctrl;	/* offset 0xB0 */
+	unsigned int gpio3clkctrl;	/* offset 0xB4 */
+	unsigned int resv5;
+	unsigned int tpccclkctrl;	/* offset 0xBC */
+	unsigned int dcan0clkctrl;	/* offset 0xC0 */
+	unsigned int dcan1clkctrl;	/* offset 0xC4 */
+	unsigned int resv6;
+	unsigned int epwmss1clkctrl;	/* offset 0xCC */
+	unsigned int emiffwclkctrl;	/* offset 0xD0 */
+	unsigned int epwmss0clkctrl;	/* offset 0xD4 */
+	unsigned int epwmss2clkctrl;	/* offset 0xD8 */
+	unsigned int l3instrclkctrl;	/* offset 0xDC */
+	unsigned int l3clkctrl;		/* Offset 0xE0 */
+	unsigned int resv8[2];
+	unsigned int timer5clkctrl;	/* offset 0xEC */
+	unsigned int timer6clkctrl;	/* offset 0xF0 */
+	unsigned int mmc1clkctrl;	/* offset 0xF4 */
+	unsigned int mmc2clkctrl;	/* offset 0xF8 */
+	unsigned int resv9[8];
+	unsigned int l4hsclkstctrl;	/* offset 0x11C */
+	unsigned int l4hsclkctrl;	/* offset 0x120 */
+	unsigned int resv10[8];
+	unsigned int cpswclkstctrl;	/* offset 0x144 */
+	unsigned int lcdcclkstctrl;	/* offset 0x148 */
+};
+
+/* Encapsulating Display pll registers */
+struct cm_dpll {
+	unsigned int resv1;
+	unsigned int clktimer7clk;	/* offset 0x04 */
+	unsigned int clktimer2clk;	/* offset 0x08 */
+	unsigned int clktimer3clk;	/* offset 0x0C */
+	unsigned int clktimer4clk;	/* offset 0x10 */
+	unsigned int resv2;
+	unsigned int clktimer5clk;	/* offset 0x18 */
+	unsigned int clktimer6clk;	/* offset 0x1C */
+	unsigned int resv3[2];
+	unsigned int clktimer1clk;	/* offset 0x28 */
+	unsigned int resv4[2];
+	unsigned int clklcdcpixelclk;	/* offset 0x34 */
+};
+
+struct prm_device_inst {
+	unsigned int prm_rstctrl;
+	unsigned int prm_rsttime;
+	unsigned int prm_rstst;
+};
+#else
+/* Encapsulating core pll registers */
+struct cm_wkuppll {
+	unsigned int resv0[136];
+	unsigned int wkl4wkclkctrl;	/* offset 0x220 */
+	unsigned int resv1[7];
+	unsigned int usbphy0clkctrl;	/* offset 0x240 */
+	unsigned int resv112;
+	unsigned int usbphy1clkctrl;	/* offset 0x248 */
+	unsigned int resv113[45];
+	unsigned int wkclkstctrl;	/* offset 0x300 */
+	unsigned int resv2[15];
+	unsigned int wkup_i2c0ctrl;	/* offset 0x340 */
+	unsigned int resv3;
+	unsigned int wkup_uart0ctrl;	/* offset 0x348 */
+	unsigned int resv4[5];
+	unsigned int wkctrlclkctrl;	/* offset 0x360 */
+	unsigned int resv5;
+	unsigned int wkgpio0clkctrl;	/* offset 0x368 */
+
+	unsigned int resv6[109];
+	unsigned int clkmoddpllcore;	/* offset 0x520 */
+	unsigned int idlestdpllcore;	/* offset 0x524 */
+	unsigned int resv61;
+	unsigned int clkseldpllcore;	/* offset 0x52C */
+	unsigned int resv7[2];
+	unsigned int divm4dpllcore;	/* offset 0x538 */
+	unsigned int divm5dpllcore;	/* offset 0x53C */
+	unsigned int divm6dpllcore;	/* offset 0x540 */
+
+	unsigned int resv8[7];
+	unsigned int clkmoddpllmpu;	/* offset 0x560 */
+	unsigned int idlestdpllmpu;	/* offset 0x564 */
+	unsigned int resv9;
+	unsigned int clkseldpllmpu;	/* offset 0x56c */
+	unsigned int divm2dpllmpu;	/* offset 0x570 */
+
+	unsigned int resv10[11];
+	unsigned int clkmoddpllddr;	/* offset 0x5A0 */
+	unsigned int idlestdpllddr;	/* offset 0x5A4 */
+	unsigned int resv11;
+	unsigned int clkseldpllddr;	/* offset 0x5AC */
+	unsigned int divm2dpllddr;	/* offset 0x5B0 */
+
+	unsigned int resv12[11];
+	unsigned int clkmoddpllper;	/* offset 0x5E0 */
+	unsigned int idlestdpllper;	/* offset 0x5E4 */
+	unsigned int resv13;
+	unsigned int clkseldpllper;	/* offset 0x5EC */
+	unsigned int divm2dpllper;	/* offset 0x5F0 */
+	unsigned int resv14[8];
+	unsigned int clkdcoldodpllper;	/* offset 0x614 */
+
+	unsigned int resv15[2];
+	unsigned int clkmoddplldisp;	/* offset 0x620 */
+	unsigned int resv16[2];
+	unsigned int clkseldplldisp;	/* offset 0x62C */
+	unsigned int divm2dplldisp;	/* offset 0x630 */
+};
+
+/*
+ * Encapsulating peripheral functional clocks
+ * pll registers
+ */
+struct cm_perpll {
+	unsigned int l3clkstctrl;	/* offset 0x00 */
+	unsigned int resv0[7];
+	unsigned int l3clkctrl;		/* Offset 0x20 */
+	unsigned int resv112[7];
+	unsigned int l3instrclkctrl;	/* offset 0x40 */
+	unsigned int resv2[3];
+	unsigned int ocmcramclkctrl;	/* offset 0x50 */
+	unsigned int resv3[9];
+	unsigned int tpccclkctrl;	/* offset 0x78 */
+	unsigned int resv4;
+	unsigned int tptc0clkctrl;	/* offset 0x80 */
+
+	unsigned int resv5[7];
+	unsigned int l4hsclkctrl;	/* offset 0x0A0 */
+	unsigned int resv6;
+	unsigned int l4fwclkctrl;	/* offset 0x0A8 */
+	unsigned int resv7[85];
+	unsigned int l3sclkstctrl;	/* offset 0x200 */
+	unsigned int resv8[7];
+	unsigned int gpmcclkctrl;	/* offset 0x220 */
+	unsigned int resv9[5];
+	unsigned int mcasp0clkctrl;	/* offset 0x238 */
+	unsigned int resv10;
+	unsigned int mcasp1clkctrl;	/* offset 0x240 */
+	unsigned int resv11;
+	unsigned int mmc2clkctrl;	/* offset 0x248 */
+	unsigned int resv12[3];
+	unsigned int qspiclkctrl;       /* offset 0x258 */
+	unsigned int resv121;
+	unsigned int usb0clkctrl;	/* offset 0x260 */
+	unsigned int resv122;
+	unsigned int usb1clkctrl;	/* offset 0x268 */
+	unsigned int resv13[101];
+	unsigned int l4lsclkstctrl;	/* offset 0x400 */
+	unsigned int resv14[7];
+	unsigned int l4lsclkctrl;	/* offset 0x420 */
+	unsigned int resv15;
+	unsigned int dcan0clkctrl;	/* offset 0x428 */
+	unsigned int resv16;
+	unsigned int dcan1clkctrl;	/* offset 0x430 */
+	unsigned int resv17[13];
+	unsigned int elmclkctrl;	/* offset 0x468 */
+
+	unsigned int resv18[3];
+	unsigned int gpio1clkctrl;	/* offset 0x478 */
+	unsigned int resv19;
+	unsigned int gpio2clkctrl;	/* offset 0x480 */
+	unsigned int resv20;
+	unsigned int gpio3clkctrl;	/* offset 0x488 */
+	unsigned int resv41;
+	unsigned int gpio4clkctrl;	/* offset 0x490 */
+	unsigned int resv42;
+	unsigned int gpio5clkctrl;	/* offset 0x498 */
+	unsigned int resv21[3];
+
+	unsigned int i2c1clkctrl;	/* offset 0x4A8 */
+	unsigned int resv22;
+	unsigned int i2c2clkctrl;	/* offset 0x4B0 */
+	unsigned int resv23[3];
+	unsigned int mmc0clkctrl;	/* offset 0x4C0 */
+	unsigned int resv24;
+	unsigned int mmc1clkctrl;	/* offset 0x4C8 */
+
+	unsigned int resv25[13];
+	unsigned int spi0clkctrl;	/* offset 0x500 */
+	unsigned int resv26;
+	unsigned int spi1clkctrl;	/* offset 0x508 */
+	unsigned int resv27[9];
+	unsigned int timer2clkctrl;	/* offset 0x530 */
+	unsigned int resv28;
+	unsigned int timer3clkctrl;	/* offset 0x538 */
+	unsigned int resv29;
+	unsigned int timer4clkctrl;	/* offset 0x540 */
+	unsigned int resv30[5];
+	unsigned int timer7clkctrl;	/* offset 0x558 */
+
+	unsigned int resv31[9];
+	unsigned int uart1clkctrl;	/* offset 0x580 */
+	unsigned int resv32;
+	unsigned int uart2clkctrl;	/* offset 0x588 */
+	unsigned int resv33;
+	unsigned int uart3clkctrl;	/* offset 0x590 */
+	unsigned int resv34;
+	unsigned int uart4clkctrl;	/* offset 0x598 */
+	unsigned int resv35;
+	unsigned int uart5clkctrl;	/* offset 0x5A0 */
+	unsigned int resv36[5];
+	unsigned int usbphyocp2scp0clkctrl;	/* offset 0x5B8 */
+	unsigned int resv361;
+	unsigned int usbphyocp2scp1clkctrl;	/* offset 0x5C0 */
+	unsigned int resv3611[79];
+
+	unsigned int emifclkstctrl;	/* offset 0x700 */
+	unsigned int resv362[7];
+	unsigned int emifclkctrl;	/* offset 0x720 */
+	unsigned int resv37[3];
+	unsigned int emiffwclkctrl;	/* offset 0x730 */
+	unsigned int resv371;
+	unsigned int otfaemifclkctrl;	/* offset 0x738 */
+	unsigned int resv38[57];
+	unsigned int lcdclkctrl;	/* offset 0x820 */
+	unsigned int resv39[183];
+	unsigned int cpswclkstctrl;	/* offset 0xB00 */
+	unsigned int resv40[7];
+	unsigned int cpgmac0clkctrl;	/* offset 0xB20 */
+};
+
+struct cm_device_inst {
+	unsigned int cm_clkout1_ctrl;
+	unsigned int cm_dll_ctrl;
+};
+
+struct prm_device_inst {
+	unsigned int rstctrl;
+	unsigned int rstst;
+	unsigned int rsttime;
+	unsigned int sram_count;
+	unsigned int ldo_sram_core_set;	/* offset 0x10 */
+	unsigned int ldo_sram_core_ctr;
+	unsigned int ldo_sram_mpu_setu;
+	unsigned int ldo_sram_mpu_ctrl;
+	unsigned int io_count;		/* offset 0x20 */
+	unsigned int io_pmctrl;
+	unsigned int vc_val_bypass;
+	unsigned int resv1;
+	unsigned int emif_ctrl;		/* offset 0x30 */
+};
+
+struct cm_dpll {
+	unsigned int resv1;
+	unsigned int clktimer2clk;	/* offset 0x04 */
+	unsigned int resv2[11];
+	unsigned int clkselmacclk;	/* offset 0x34 */ 
+};
+#endif /* CONFIG_AM43XX */
+
+/* Control Module RTC registers */
+struct cm_rtc {
+	unsigned int rtcclkctrl;	/* offset 0x0 */
+	unsigned int clkstctrl;		/* offset 0x4 */
+};
+
+/* Timer 32 bit registers */
+struct gptimer {
+	unsigned int tidr;		/* offset 0x00 */
+	unsigned char res1[12];
+	unsigned int tiocp_cfg;		/* offset 0x10 */
+	unsigned char res2[12];
+	unsigned int tier;		/* offset 0x20 */
+	unsigned int tistatr;		/* offset 0x24 */
+	unsigned int tistat;		/* offset 0x28 */
+	unsigned int tisr;		/* offset 0x2c */
+	unsigned int tcicr;		/* offset 0x30 */
+	unsigned int twer;		/* offset 0x34 */
+	unsigned int tclr;		/* offset 0x38 */
+	unsigned int tcrr;		/* offset 0x3c */
+	unsigned int tldr;		/* offset 0x40 */
+	unsigned int ttgr;		/* offset 0x44 */
+	unsigned int twpc;		/* offset 0x48 */
+	unsigned int tmar;		/* offset 0x4c */
+	unsigned int tcar1;		/* offset 0x50 */
+	unsigned int tscir;		/* offset 0x54 */
+	unsigned int tcar2;		/* offset 0x58 */
+};
+
+/* UART Registers */
+struct uart_sys {
+	unsigned int resv1[21];
+	unsigned int uartsyscfg;	/* offset 0x54 */
+	unsigned int uartsyssts;	/* offset 0x58 */
+};
+
+/* VTP Registers */
+struct vtp_reg {
+	unsigned int vtp0ctrlreg;
+};
+
+/* Control Status Register */
+struct ctrl_stat {
+	unsigned int resv1[16];
+	unsigned int statusreg;		/* ofset 0x40 */
+	unsigned int resv2[51];
+	unsigned int secure_emif_sdram_config;	/* offset 0x0110 */
+	unsigned int resv3[319];
+	unsigned int dev_attr;
+};
+
+/* AM33XX GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0114
+#define OMAP_GPIO_IRQSTATUS1		0x002c
+#define OMAP_GPIO_IRQSTATUS2		0x0030
+#define OMAP_GPIO_IRQSTATUS_SET_0	0x0034
+#define OMAP_GPIO_IRQSTATUS_SET_1	0x0038
+#define OMAP_GPIO_CTRL			0x0130
+#define OMAP_GPIO_OE			0x0134
+#define OMAP_GPIO_DATAIN		0x0138
+#define OMAP_GPIO_DATAOUT		0x013c
+#define OMAP_GPIO_LEVELDETECT0		0x0140
+#define OMAP_GPIO_LEVELDETECT1		0x0144
+#define OMAP_GPIO_RISINGDETECT		0x0148
+#define OMAP_GPIO_FALLINGDETECT		0x014c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+#define OMAP_GPIO_CLEARDATAOUT		0x0190
+#define OMAP_GPIO_SETDATAOUT		0x0194
+
+/* Control Device Register */
+
+ /* Control Device Register */
+#define MREQPRIO_0_SAB_INIT1_MASK	0xFFFFFF8F
+#define MREQPRIO_0_SAB_INIT0_MASK	0xFFFFFFF8
+#define MREQPRIO_1_DSS_MASK		0xFFFFFF8F
+
+struct ctrl_dev {
+	unsigned int deviceid;		/* offset 0x00 */
+	unsigned int resv1[7];
+	unsigned int usb_ctrl0;		/* offset 0x20 */
+	unsigned int resv2;
+	unsigned int usb_ctrl1;		/* offset 0x28 */
+	unsigned int resv3;
+	unsigned int macid0l;		/* offset 0x30 */
+	unsigned int macid0h;		/* offset 0x34 */
+	unsigned int macid1l;		/* offset 0x38 */
+	unsigned int macid1h;		/* offset 0x3c */
+	unsigned int resv4[4];
+	unsigned int miisel;		/* offset 0x50 */
+	unsigned int resv5[7];
+	unsigned int mreqprio_0;	/* offset 0x70 */
+	unsigned int mreqprio_1;	/* offset 0x74 */
+	unsigned int resv6[97];
+	unsigned int efuse_sma;		/* offset 0x1FC */
+};
+
+/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
+#define BW_LIMITER_BW_FRAC_MASK         0xFFFFFFE0
+#define BW_LIMITER_BW_INT_MASK          0xFFFFFFF0
+#define BW_LIMITER_BW_WATERMARK_MASK    0xFFFFF800
+
+struct l3f_cfg_bwlimiter {
+	u32 padding0[2];
+	u32 modena_init0_bw_fractional;
+	u32 modena_init0_bw_integer;
+	u32 modena_init0_watermark_0;
+};
+
+/* gmii_sel register defines */
+#define GMII1_SEL_MII		0x0
+#define GMII1_SEL_RMII		0x1
+#define GMII1_SEL_RGMII		0x2
+#define GMII2_SEL_MII		0x0
+#define GMII2_SEL_RMII		0x4
+#define GMII2_SEL_RGMII		0x8
+#define RGMII1_IDMODE		BIT(4)
+#define RGMII2_IDMODE		BIT(5)
+#define RMII1_IO_CLK_EN		BIT(6)
+#define RMII2_IO_CLK_EN		BIT(7)
+
+#define MII_MODE_ENABLE		(GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE	(GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+#define RGMII_INT_DELAY		(RGMII1_IDMODE | RGMII2_IDMODE)
+#define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
+
+/* PWMSS */
+struct pwmss_regs {
+	unsigned int idver;
+	unsigned int sysconfig;
+	unsigned int clkconfig;
+	unsigned int clkstatus;
+};
+#define ECAP_CLK_EN		BIT(0)
+#define ECAP_CLK_STOP_REQ	BIT(1)
+#define EPWM_CLK_EN		BIT(8)
+#define EPWM_CLK_STOP_REQ	BIT(9)
+
+struct pwmss_ecap_regs {
+	unsigned int tsctr;
+	unsigned int ctrphs;
+	unsigned int cap1;
+	unsigned int cap2;
+	unsigned int cap3;
+	unsigned int cap4;
+	unsigned int resv1[4];
+	unsigned short ecctl1;
+	unsigned short ecctl2;
+};
+
+struct pwmss_epwm_regs {
+	unsigned short tbctl;
+	unsigned short tbsts;
+	unsigned short tbphshr;
+	unsigned short tbphs;
+	unsigned short tbcnt;
+	unsigned short tbprd;
+	unsigned short res1;
+	unsigned short cmpctl;
+	unsigned short cmpahr;
+	unsigned short cmpa;
+	unsigned short cmpb;
+	unsigned short aqctla;
+	unsigned short aqctlb;
+	unsigned short aqsfrc;
+	unsigned short aqcsfrc;
+	unsigned short dbctl;
+	unsigned short dbred;
+	unsigned short dbfed;
+	unsigned short tzsel;
+	unsigned short tzctl;
+	unsigned short tzflg;
+	unsigned short tzclr;
+	unsigned short tzfrc;
+	unsigned short etsel;
+	unsigned short etps;
+	unsigned short etflg;
+	unsigned short etclr;
+	unsigned short etfrc;
+	unsigned short pcctl;
+	unsigned int res2[66];
+	unsigned short hrcnfg;
+};
+
+/* Capture Control register 2 */
+#define ECTRL2_SYNCOSEL_MASK	(0x03 << 6)
+#define ECTRL2_MDSL_ECAP	BIT(9)
+#define ECTRL2_CTRSTP_FREERUN	BIT(4)
+#define ECTRL2_PLSL_LOW		BIT(10)
+#define ECTRL2_SYNC_EN		BIT(5)
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#endif /* _AM33XX_CPU_H */
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
new file mode 100644
index 0000000..15a5b64
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -0,0 +1,383 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ddr_defs.h
+ *
+ * ddr specific header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _DDR_DEFS_H
+#define _DDR_DEFS_H
+
+#include <asm/arch/hardware.h>
+#include <asm/emif.h>
+
+/* AM335X EMIF Register values */
+#define VTP_CTRL_READY		(0x1 << 5)
+#define VTP_CTRL_ENABLE		(0x1 << 6)
+#define VTP_CTRL_START_EN	(0x1)
+#ifdef CONFIG_AM43XX
+#define DDR_CKE_CTRL_NORMAL	0x3
+#else
+#define DDR_CKE_CTRL_NORMAL	0x1
+#endif
+#define PHY_EN_DYN_PWRDN	(0x1 << 20)
+
+/* Micron MT47H128M16RT-25E */
+#define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005
+#define MT47H128M16RT25E_EMIF_TIM1		0x0666B3C9
+#define MT47H128M16RT25E_EMIF_TIM2		0x243631CA
+#define MT47H128M16RT25E_EMIF_TIM3		0x0000033F
+#define MT47H128M16RT25E_EMIF_SDCFG		0x41805332
+#define MT47H128M16RT25E_EMIF_SDREF		0x0000081a
+#define MT47H128M16RT25E_RATIO			0x80
+#define MT47H128M16RT25E_RD_DQS			0x12
+#define MT47H128M16RT25E_PHY_WR_DATA		0x40
+#define MT47H128M16RT25E_PHY_FIFO_WE		0x80
+#define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
+
+/* Micron MT41J128M16JT-125 */
+#define MT41J128MJT125_EMIF_READ_LATENCY	0x100006
+#define MT41J128MJT125_EMIF_TIM1		0x0888A39B
+#define MT41J128MJT125_EMIF_TIM2		0x26337FDA
+#define MT41J128MJT125_EMIF_TIM3		0x501F830F
+#define MT41J128MJT125_EMIF_SDCFG		0x61C04AB2
+#define MT41J128MJT125_EMIF_SDREF		0x0000093B
+#define MT41J128MJT125_ZQ_CFG			0x50074BE4
+#define MT41J128MJT125_RATIO			0x40
+#define MT41J128MJT125_INVERT_CLKOUT		0x1
+#define MT41J128MJT125_RD_DQS			0x3B
+#define MT41J128MJT125_WR_DQS			0x85
+#define MT41J128MJT125_PHY_WR_DATA		0xC1
+#define MT41J128MJT125_PHY_FIFO_WE		0x100
+#define MT41J128MJT125_IOCTRL_VALUE		0x18B
+
+/* Micron MT41J128M16JT-125 at 400MHz*/
+#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz	0x100007
+#define MT41J128MJT125_EMIF_TIM1_400MHz		0x0AAAD4DB
+#define MT41J128MJT125_EMIF_TIM2_400MHz		0x26437FDA
+#define MT41J128MJT125_EMIF_TIM3_400MHz		0x501F83FF
+#define MT41J128MJT125_EMIF_SDCFG_400MHz	0x61C052B2
+#define MT41J128MJT125_EMIF_SDREF_400MHz	0x00000C30
+#define MT41J128MJT125_ZQ_CFG_400MHz		0x50074BE4
+#define MT41J128MJT125_RATIO_400MHz		0x80
+#define MT41J128MJT125_INVERT_CLKOUT_400MHz	0x0
+#define MT41J128MJT125_RD_DQS_400MHz		0x3A
+#define MT41J128MJT125_WR_DQS_400MHz		0x3B
+#define MT41J128MJT125_PHY_WR_DATA_400MHz	0x76
+#define MT41J128MJT125_PHY_FIFO_WE_400MHz	0x96
+
+/* Micron MT41K128M16JT-187E */
+#define MT41K128MJT187E_EMIF_READ_LATENCY	0x06
+#define MT41K128MJT187E_EMIF_TIM1		0x0888B3DB
+#define MT41K128MJT187E_EMIF_TIM2		0x36337FDA
+#define MT41K128MJT187E_EMIF_TIM3		0x501F830F
+#define MT41K128MJT187E_EMIF_SDCFG		0x61C04AB2
+#define MT41K128MJT187E_EMIF_SDREF		0x0000093B
+#define MT41K128MJT187E_ZQ_CFG			0x50074BE4
+#define MT41K128MJT187E_RATIO			0x40
+#define MT41K128MJT187E_INVERT_CLKOUT		0x1
+#define MT41K128MJT187E_RD_DQS			0x3B
+#define MT41K128MJT187E_WR_DQS			0x85
+#define MT41K128MJT187E_PHY_WR_DATA		0xC1
+#define MT41K128MJT187E_PHY_FIFO_WE		0x100
+#define MT41K128MJT187E_IOCTRL_VALUE		0x18B
+
+/* Micron MT41K128M16JT-125 IT:K (256 MB) at 400MHz */
+#define MT41K128M16JT125K_EMIF_READ_LATENCY     0x07
+#define MT41K128M16JT125K_EMIF_TIM1             0x0AAAD4DB
+#define MT41K128M16JT125K_EMIF_TIM2             0x2A437FDA
+#define MT41K128M16JT125K_EMIF_TIM3             0x501F83FF
+#define MT41K128M16JT125K_EMIF_SDCFG            0x61A052B2
+#define MT41K128M16JT125K_EMIF_SDREF            0x00000C30
+#define MT41K128M16JT125K_ZQ_CFG                0x50074BE4
+#define MT41K128M16JT125K_RATIO                 0x80
+#define MT41K128M16JT125K_INVERT_CLKOUT         0x0
+#define MT41K128M16JT125K_RD_DQS                0x38
+#define MT41K128M16JT125K_WR_DQS                0x46
+#define MT41K128M16JT125K_PHY_WR_DATA           0x7D
+#define MT41K128M16JT125K_PHY_FIFO_WE           0x9B
+#define MT41K128M16JT125K_IOCTRL_VALUE          0x18B
+
+/* Micron MT41J64M16JT-125 */
+#define MT41J64MJT125_EMIF_SDCFG		0x61C04A32
+
+/* Micron MT41J256M16JT-125 */
+#define MT41J256MJT125_EMIF_SDCFG		0x61C04B32
+
+/* Micron MT41J256M8HX-15E */
+#define MT41J256M8HX15E_EMIF_READ_LATENCY	0x100006
+#define MT41J256M8HX15E_EMIF_TIM1		0x0888A39B
+#define MT41J256M8HX15E_EMIF_TIM2		0x26337FDA
+#define MT41J256M8HX15E_EMIF_TIM3		0x501F830F
+#define MT41J256M8HX15E_EMIF_SDCFG		0x61C04B32
+#define MT41J256M8HX15E_EMIF_SDREF		0x0000093B
+#define MT41J256M8HX15E_ZQ_CFG			0x50074BE4
+#define MT41J256M8HX15E_RATIO			0x40
+#define MT41J256M8HX15E_INVERT_CLKOUT		0x1
+#define MT41J256M8HX15E_RD_DQS			0x3B
+#define MT41J256M8HX15E_WR_DQS			0x85
+#define MT41J256M8HX15E_PHY_WR_DATA		0xC1
+#define MT41J256M8HX15E_PHY_FIFO_WE		0x100
+#define MT41J256M8HX15E_IOCTRL_VALUE		0x18B
+
+/* Micron MT41K256M16HA-125E */
+#define MT41K256M16HA125E_EMIF_READ_LATENCY	0x100007
+#define MT41K256M16HA125E_EMIF_TIM1		0x0AAAD4DB
+#define MT41K256M16HA125E_EMIF_TIM2		0x266B7FDA
+#define MT41K256M16HA125E_EMIF_TIM3		0x501F867F
+#define MT41K256M16HA125E_EMIF_SDCFG		0x61C05332
+#define MT41K256M16HA125E_EMIF_SDREF		0xC30
+#define MT41K256M16HA125E_ZQ_CFG		0x50074BE4
+#define MT41K256M16HA125E_RATIO			0x80
+#define MT41K256M16HA125E_INVERT_CLKOUT		0x0
+#define MT41K256M16HA125E_RD_DQS		0x38
+#define MT41K256M16HA125E_WR_DQS		0x44
+#define MT41K256M16HA125E_PHY_WR_DATA		0x7D
+#define MT41K256M16HA125E_PHY_FIFO_WE		0x94
+#define MT41K256M16HA125E_IOCTRL_VALUE		0x18B
+
+/* Micron MT41J512M8RH-125 on EVM v1.5 */
+#define MT41J512M8RH125_EMIF_READ_LATENCY	0x100006
+#define MT41J512M8RH125_EMIF_TIM1		0x0888A39B
+#define MT41J512M8RH125_EMIF_TIM2		0x26517FDA
+#define MT41J512M8RH125_EMIF_TIM3		0x501F84EF
+#define MT41J512M8RH125_EMIF_SDCFG		0x61C04BB2
+#define MT41J512M8RH125_EMIF_SDREF		0x0000093B
+#define MT41J512M8RH125_ZQ_CFG			0x50074BE4
+#define MT41J512M8RH125_RATIO			0x80
+#define MT41J512M8RH125_INVERT_CLKOUT		0x0
+#define MT41J512M8RH125_RD_DQS			0x3B
+#define MT41J512M8RH125_WR_DQS			0x3C
+#define MT41J512M8RH125_PHY_FIFO_WE		0xA5
+#define MT41J512M8RH125_PHY_WR_DATA		0x74
+#define MT41J512M8RH125_IOCTRL_VALUE		0x18B
+
+/* Samsung K4B2G1646E-BIH9 */
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x100007
+#define K4B2G1646EBIH9_EMIF_TIM1		0x0AAAE51B
+#define K4B2G1646EBIH9_EMIF_TIM2		0x2A1D7FDA
+#define K4B2G1646EBIH9_EMIF_TIM3		0x501F83FF
+#define K4B2G1646EBIH9_EMIF_SDCFG		0x61C052B2
+#define K4B2G1646EBIH9_EMIF_SDREF		0x00000C30
+#define K4B2G1646EBIH9_ZQ_CFG			0x50074BE4
+#define K4B2G1646EBIH9_RATIO			0x80
+#define K4B2G1646EBIH9_INVERT_CLKOUT		0x0
+#define K4B2G1646EBIH9_RD_DQS			0x35
+#define K4B2G1646EBIH9_WR_DQS			0x3A
+#define K4B2G1646EBIH9_PHY_FIFO_WE		0x97
+#define K4B2G1646EBIH9_PHY_WR_DATA		0x76
+#define K4B2G1646EBIH9_IOCTRL_VALUE		0x18B
+
+#define  LPDDR2_ADDRCTRL_IOCTRL_VALUE   0x294
+#define  LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  LPDDR2_DATA0_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA1_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
+
+#define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
+#define  DDR3_DATA0_IOCTRL_VALUE   0x84
+#define  DDR3_DATA1_IOCTRL_VALUE   0x84
+#define  DDR3_DATA2_IOCTRL_VALUE   0x84
+#define  DDR3_DATA3_IOCTRL_VALUE   0x84
+
+/**
+ * Configure DMM
+ */
+void config_dmm(const struct dmm_lisa_map_regs *regs);
+
+/**
+ * Configure SDRAM
+ */
+void config_sdram(const struct emif_regs *regs, int nr);
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
+
+/**
+ * Set SDRAM timings
+ */
+void set_sdram_timings(const struct emif_regs *regs, int nr);
+
+/**
+ * Configure DDR PHY
+ */
+void config_ddr_phy(const struct emif_regs *regs, int nr);
+
+struct ddr_cmd_regs {
+	unsigned int resv0[7];
+	unsigned int cm0csratio;	/* offset 0x01C */
+	unsigned int resv1[3];
+	unsigned int cm0iclkout;	/* offset 0x02C */
+	unsigned int resv2[8];
+	unsigned int cm1csratio;	/* offset 0x050 */
+	unsigned int resv3[3];
+	unsigned int cm1iclkout;	/* offset 0x060 */
+	unsigned int resv4[8];
+	unsigned int cm2csratio;	/* offset 0x084 */
+	unsigned int resv5[3];
+	unsigned int cm2iclkout;	/* offset 0x094 */
+	unsigned int resv6[3];
+};
+
+struct ddr_data_regs {
+	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
+	unsigned int resv1[4];
+	unsigned int dt0wdsratio0;	/* offset 0x0DC */
+	unsigned int resv2[4];
+	unsigned int dt0wiratio0;	/* offset 0x0F0 */
+	unsigned int resv3;
+	unsigned int dt0wimode0;	/* offset 0x0F8 */
+	unsigned int dt0giratio0;	/* offset 0x0FC */
+	unsigned int resv4;
+	unsigned int dt0gimode0;	/* offset 0x104 */
+	unsigned int dt0fwsratio0;	/* offset 0x108 */
+	unsigned int resv5[4];
+	unsigned int dt0dqoffset;	/* offset 0x11C */
+	unsigned int dt0wrsratio0;	/* offset 0x120 */
+	unsigned int resv6[4];
+	unsigned int dt0rdelays0;	/* offset 0x134 */
+	unsigned int dt0dldiff0;	/* offset 0x138 */
+	unsigned int resv7[12];
+};
+
+/**
+ * This structure represents the DDR registers on AM33XX devices.
+ * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
+ * correspond to DATA1 registers defined here.
+ */
+struct ddr_regs {
+	unsigned int resv0[3];
+	unsigned int cm0config;		/* offset 0x00C */
+	unsigned int cm0configclk;	/* offset 0x010 */
+	unsigned int resv1[2];
+	unsigned int cm0csratio;	/* offset 0x01C */
+	unsigned int resv2[3];
+	unsigned int cm0iclkout;	/* offset 0x02C */
+	unsigned int resv3[4];
+	unsigned int cm1config;		/* offset 0x040 */
+	unsigned int cm1configclk;	/* offset 0x044 */
+	unsigned int resv4[2];
+	unsigned int cm1csratio;	/* offset 0x050 */
+	unsigned int resv5[3];
+	unsigned int cm1iclkout;	/* offset 0x060 */
+	unsigned int resv6[4];
+	unsigned int cm2config;		/* offset 0x074 */
+	unsigned int cm2configclk;	/* offset 0x078 */
+	unsigned int resv7[2];
+	unsigned int cm2csratio;	/* offset 0x084 */
+	unsigned int resv8[3];
+	unsigned int cm2iclkout;	/* offset 0x094 */
+	unsigned int resv9[12];
+	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
+	unsigned int resv10[4];
+	unsigned int dt0wdsratio0;	/* offset 0x0DC */
+	unsigned int resv11[4];
+	unsigned int dt0wiratio0;	/* offset 0x0F0 */
+	unsigned int resv12;
+	unsigned int dt0wimode0;	/* offset 0x0F8 */
+	unsigned int dt0giratio0;	/* offset 0x0FC */
+	unsigned int resv13;
+	unsigned int dt0gimode0;	/* offset 0x104 */
+	unsigned int dt0fwsratio0;	/* offset 0x108 */
+	unsigned int resv14[4];
+	unsigned int dt0dqoffset;	/* offset 0x11C */
+	unsigned int dt0wrsratio0;	/* offset 0x120 */
+	unsigned int resv15[4];
+	unsigned int dt0rdelays0;	/* offset 0x134 */
+	unsigned int dt0dldiff0;	/* offset 0x138 */
+};
+
+/**
+ * Encapsulates DDR CMD control registers.
+ */
+struct cmd_control {
+	unsigned long cmd0csratio;
+	unsigned long cmd0csforce;
+	unsigned long cmd0csdelay;
+	unsigned long cmd0iclkout;
+	unsigned long cmd1csratio;
+	unsigned long cmd1csforce;
+	unsigned long cmd1csdelay;
+	unsigned long cmd1iclkout;
+	unsigned long cmd2csratio;
+	unsigned long cmd2csforce;
+	unsigned long cmd2csdelay;
+	unsigned long cmd2iclkout;
+};
+
+/**
+ * Encapsulates DDR DATA registers.
+ */
+struct ddr_data {
+	unsigned long datardsratio0;
+	unsigned long datawdsratio0;
+	unsigned long datawiratio0;
+	unsigned long datagiratio0;
+	unsigned long datafwsratio0;
+	unsigned long datawrsratio0;
+};
+
+/**
+ * Configure DDR CMD control registers
+ */
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
+
+/**
+ * Configure DDR DATA registers
+ */
+void config_ddr_data(const struct ddr_data *data, int nr);
+
+/**
+ * This structure represents the DDR io control on AM33XX devices.
+ */
+struct ddr_cmdtctrl {
+	unsigned int cm0ioctl;
+	unsigned int cm1ioctl;
+	unsigned int cm2ioctl;
+	unsigned int resv2[12];
+	unsigned int dt0ioctl;
+	unsigned int dt1ioctl;
+	unsigned int dt2ioctrl;
+	unsigned int dt3ioctrl;
+	unsigned int resv3[4];
+	unsigned int emif_sdram_config_ext;
+};
+
+struct ctrl_ioregs {
+	unsigned int cm0ioctl;
+	unsigned int cm1ioctl;
+	unsigned int cm2ioctl;
+	unsigned int dt0ioctl;
+	unsigned int dt1ioctl;
+	unsigned int dt2ioctrl;
+	unsigned int dt3ioctrl;
+	unsigned int emif_sdram_config_ext;
+};
+
+/**
+ * Configure DDR io control registers
+ */
+void config_io_ctrl(const struct ctrl_ioregs *ioregs);
+
+struct ddr_ctrl {
+	unsigned int ddrioctrl;
+	unsigned int resv1[325];
+	unsigned int ddrckectrl;
+};
+
+#ifdef CONFIG_TI816X
+void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
+		const struct emif_regs *regs,
+		const struct dmm_lisa_map_regs *lisa_regs, int nrs);
+#else
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
+		const struct ddr_data *data, const struct cmd_control *ctrl,
+		const struct emif_regs *regs, int nr);
+#endif
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
+
+#endif  /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/emac_defs.h b/arch/arm/include/asm/arch-am33xx/emac_defs.h
new file mode 100644
index 0000000..eb6516d
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/emac_defs.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * Based on:
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * dm644x_emac.h
+ *
+ * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
+ *
+ * Copyright (C) 2005 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ */
+
+#ifndef _EMAC_DEFS_H_
+#define _EMAC_DEFS_H_
+
+#ifdef CONFIG_TI816X
+#define EMAC_BASE_ADDR			(0x4A100000)
+#define EMAC_WRAPPER_BASE_ADDR		(0x4A100900)
+#define EMAC_WRAPPER_RAM_ADDR		(0x4A102000)
+#define EMAC_MDIO_BASE_ADDR		(0x4A100800)
+#define EMAC_MDIO_BUS_FREQ		(250000000UL)
+#define EMAC_MDIO_CLOCK_FREQ		(2000000UL)
+
+typedef volatile unsigned int	dv_reg;
+typedef volatile unsigned int	*dv_reg_p;
+
+#define DAVINCI_EMAC_VERSION2
+#define DAVINCI_EMAC_GIG_ENABLE
+#endif
+
+#endif  /* _EMAC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h
new file mode 100644
index 0000000..24dc4bb
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/gpio.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _GPIO_AM33xx_H
+#define _GPIO_AM33xx_H
+
+#include <asm/omap_gpio.h>
+
+#ifdef CONFIG_AM43XX
+#define OMAP_MAX_GPIO		192
+#else
+#define OMAP_MAX_GPIO		128
+#endif
+
+#define AM33XX_GPIO0_BASE       0x44E07000
+#define AM33XX_GPIO1_BASE       0x4804C000
+#define AM33XX_GPIO2_BASE       0x481AC000
+#define AM33XX_GPIO3_BASE       0x481AE000
+#define AM33XX_GPIO4_BASE	0x48320000
+#define AM33XX_GPIO5_BASE	0x48322000
+
+/* GPIO CTRL register */
+#define GPIO_CTRL_DISABLEMODULE_SHIFT	0
+#define GPIO_CTRL_DISABLEMODULE_MASK	(1 << 0)
+#define GPIO_CTRL_ENABLEMODULE		GPIO_CTRL_DISABLEMODULE_MASK
+
+/* GPIO OUTPUT ENABLE register */
+#define GPIO_OE_ENABLE(x)		(1 << x)
+
+/* GPIO SETDATAOUT register */
+#define GPIO_SETDATAOUT(x)		(1 << x)
+#endif /* _GPIO_AM33xx_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
new file mode 100644
index 0000000..0508b8c
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * hardware.h
+ *
+ * hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef __AM33XX_HARDWARE_H
+#define __AM33XX_HARDWARE_H
+
+#include <config.h>
+#include <asm/arch/omap.h>
+#ifdef CONFIG_AM33XX
+#include <asm/arch/hardware_am33xx.h>
+#elif defined(CONFIG_TI816X)
+#include <asm/arch/hardware_ti816x.h>
+#elif defined(CONFIG_TI814X)
+#include <asm/arch/hardware_ti814x.h>
+#elif defined(CONFIG_AM43XX)
+#include <asm/arch/hardware_am43xx.h>
+#endif
+
+/*
+ * Common hardware definitions
+ */
+
+/* DM Timer base addresses */
+#define DM_TIMER0_BASE			0x4802C000
+#define DM_TIMER1_BASE			0x4802E000
+#define DM_TIMER2_BASE			0x48040000
+#define DM_TIMER3_BASE			0x48042000
+#define DM_TIMER4_BASE			0x48044000
+#define DM_TIMER5_BASE			0x48046000
+#define DM_TIMER6_BASE			0x48048000
+#define DM_TIMER7_BASE			0x4804A000
+
+/* GPIO Base address */
+#define GPIO0_BASE			0x48032000
+#define GPIO1_BASE			0x4804C000
+
+/* BCH Error Location Module */
+#define ELM_BASE			0x48080000
+
+/* EMIF Base address */
+#define EMIF4_0_CFG_BASE		0x4C000000
+#define EMIF4_1_CFG_BASE		0x4D000000
+
+/* DDR Base address */
+#define DDR_CTRL_ADDR			0x44E10E04
+#define DDR_CONTROL_BASE_ADDR		0x44E11404
+
+/* UART */
+#if CONFIG_CONS_INDEX == 1
+#	define DEFAULT_UART_BASE UART0_BASE
+#elif CONFIG_CONS_INDEX == 2
+#	define DEFAULT_UART_BASE UART1_BASE
+#elif CONFIG_CONS_INDEX == 3
+#	define DEFAULT_UART_BASE UART2_BASE
+#elif CONFIG_CONS_INDEX == 4
+#	define DEFAULT_UART_BASE UART3_BASE
+#elif CONFIG_CONS_INDEX == 5
+#	define DEFAULT_UART_BASE UART4_BASE
+#elif CONFIG_CONS_INDEX == 6
+#	define DEFAULT_UART_BASE UART5_BASE
+#endif
+
+/* GPMC Base address */
+#define GPMC_BASE			0x50000000
+
+/* CPSW Config space */
+#define CPSW_BASE			0x4A100000
+
+/* Control status register */
+#define CTRL_CRYSTAL_FREQ_SRC_MASK		(1 << 31)
+#define CTRL_CRYSTAL_FREQ_SRC_SHIFT		31
+#define CTRL_CRYSTAL_FREQ_SELECTION_MASK	(0x3 << 29)
+#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT	29
+#define CTRL_SYSBOOT_15_14_MASK			(0x3 << 22)
+#define CTRL_SYSBOOT_15_14_SHIFT		22
+
+#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT		0x0
+#define CTRL_CRYSTAL_FREQ_SRC_EFUSE		0x1
+
+#define NUM_CRYSTAL_FREQ			0x4
+
+int clk_get(int clk);
+#endif /* __AM33XX_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
new file mode 100644
index 0000000..878ef3e
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * hardware_am33xx.h
+ *
+ * AM33xx hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef __AM33XX_HARDWARE_AM33XX_H
+#define __AM33XX_HARDWARE_AM33XX_H
+
+/* Module base addresses */
+
+/* UART Base Address */
+#define UART0_BASE			0x44E09000
+#define UART1_BASE			0x48022000
+#define UART2_BASE			0x48024000
+#define UART3_BASE			0x481A6000
+#define UART4_BASE			0x481A8000
+#define UART5_BASE			0x481AA000
+
+/* GPIO Base address */
+#define GPIO2_BASE			0x481AC000
+
+/* Watchdog Timer */
+#define WDT_BASE			0x44E35000
+
+/* Control Module Base Address */
+#define CTRL_BASE			0x44E10000
+#define CTRL_DEVICE_BASE		0x44E10600
+
+/* PRCM Base Address */
+#define PRCM_BASE			0x44E00000
+#define CM_PER				0x44E00000
+#define CM_WKUP				0x44E00400
+#define CM_DPLL				0x44E00500
+#define CM_RTC				0x44E00800
+
+#define PRM_RSTCTRL			(PRCM_BASE + 0x0F00)
+#define PRM_RSTST			(PRM_RSTCTRL + 8)
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x44E10E0C
+#define VTP1_CTRL_ADDR			0x48140E10
+#define PRM_DEVICE_INST			0x44E00F00
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x44E12000
+#define DDR_PHY_DATA_ADDR		0x44E120C8
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
+#define DDR_DATA_REGS_NR		2
+
+#define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
+
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A101000
+
+/* RTC base address */
+#define RTC_BASE			0x44E3E000
+
+/* OTG */
+#define USB0_OTG_BASE			0x47401000
+#define USB1_OTG_BASE			0x47401800
+
+/* LCD Controller */
+#define LCD_CNTL_BASE			0x4830E000
+
+/* PWMSS */
+#define PWMSS0_BASE			0x48300000
+#define AM33XX_ECAP0_BASE		0x48300100
+#define AM33XX_EPWM_BASE		0x48300200
+
+#endif /* __AM33XX_HARDWARE_AM33XX_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
new file mode 100644
index 0000000..64809d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * hardware_am43xx.h
+ *
+ * AM43xx hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef __AM43XX_HARDWARE_AM43XX_H
+#define __AM43XX_HARDWARE_AM43XX_H
+
+/* Module base addresses */
+
+/* L3 Fast Configuration Bandwidth Limiter Base Address */
+#define L3F_CFG_BWLIMITER		0x44005200
+
+/* UART Base Address */
+#define UART0_BASE			0x44E09000
+
+/* GPIO Base address */
+#define GPIO2_BASE			0x481AC000
+
+/* Watchdog Timer */
+#define WDT_BASE			0x44E35000
+
+/* Control Module Base Address */
+#define CTRL_BASE			0x44E10000
+#define CTRL_DEVICE_BASE		0x44E10600
+
+/* PRCM Base Address */
+#define PRCM_BASE			0x44DF0000
+#define	CM_WKUP				0x44DF2800
+#define	CM_PER				0x44DF8800
+#define CM_DPLL				0x44DF4200
+#define CM_RTC				0x44DF8500
+
+#define PRM_RSTCTRL			(PRCM_BASE + 0x4000)
+#define PRM_RSTST			(PRM_RSTCTRL + 4)
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x44E10E0C
+#define VTP1_CTRL_ADDR			0x48140E10
+
+/* USB CTRL Base Address */
+#define USB1_CTRL			0x44e10628
+#define USB1_CTRL_CM_PWRDN		BIT(0)
+#define USB1_CTRL_OTG_PWRDN		BIT(1)
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x44E12000
+#define DDR_PHY_DATA_ADDR		0x44E120C8
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
+#define DDR_DATA_REGS_NR		2
+
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A101000
+
+/* RTC base address */
+#define RTC_BASE			0x44E3E000
+
+/* USB OTG */
+#define USB_OTG_SS1_BASE		0x48390000
+#define USB_OTG_SS1_GLUE_BASE		0x48380000
+#define USB2_PHY1_POWER			0x44E10620
+
+#define USB_OTG_SS2_BASE		0x483D0000
+#define USB_OTG_SS2_GLUE_BASE		0x483C0000
+#define USB2_PHY2_POWER			0x44E10628
+
+/* USB Clock Control */
+#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
+#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
+#define USBOTGSSX_CLKCTRL_MODULE_EN	(1 << 1)
+#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
+
+#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
+#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
+#define USBPHYOCPSCP_MODULE_EN	(1 << 1)
+#define CM_DEVICE_INST			0x44df4100
+#define PRM_DEVICE_INST			0x44df4000
+
+#define	USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960	(1 << 8)
+#define	USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K	(1 << 8)
+
+/* EDMA3 Base Address */
+#define EDMA3_BASE				0x49000000
+
+#endif /* __AM43XX_HARDWARE_AM43XX_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
new file mode 100644
index 0000000..b00d592
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * hardware_ti814x.h
+ *
+ * TI814x hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef __AM33XX_HARDWARE_TI814X_H
+#define __AM33XX_HARDWARE_TI814X_H
+
+/* Module base addresses */
+
+/* UART Base Address */
+#define UART0_BASE			0x48020000
+
+/* Watchdog Timer */
+#define WDT_BASE			0x481C7000
+
+/* Control Module Base Address */
+#define CTRL_BASE			0x48140000
+#define CTRL_DEVICE_BASE		0x48140600
+
+/* PRCM Base Address */
+#define PRCM_BASE			0x48180000
+#define CM_PER				0x44E00000
+#define CM_WKUP				0x44E00400
+
+#define PRM_RSTCTRL			(PRCM_BASE + 0x00A0)
+#define PRM_RSTST			(PRM_RSTCTRL + 8)
+
+/* PLL Subsystem Base Address */
+#define PLL_SUBSYS_BASE			0x481C5000
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR			0x48140E0C
+#define VTP1_CTRL_ADDR			0x48140E10
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR		0x47C0C400
+#define DDR_PHY_DATA_ADDR		0x47C0C4C8
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
+#define DDR_DATA_REGS_NR		4
+
+#define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
+
+/* CPSW Config space */
+#define CPSW_MDIO_BASE			0x4A100800
+
+/* RTC base address */
+#define RTC_BASE			0x480C0000
+
+/* OTG */
+#define USB0_OTG_BASE			0x47401000
+#define USB1_OTG_BASE			0x47401800
+
+#endif /* __AM33XX_HARDWARE_TI814X_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
new file mode 100644
index 0000000..78b7948
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h
@@ -0,0 +1,62 @@
+/*
+ * hardware_ti816x.h
+ *
+ * TI816x hardware specific header
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ * Based on TI-PSP-04.00.02.14
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AM33XX_HARDWARE_TI816X_H
+#define __AM33XX_HARDWARE_TI816X_H
+
+/* UART */
+#define UART0_BASE		0x48020000
+#define UART1_BASE		0x48022000
+#define UART2_BASE		0x48024000
+
+/* Watchdog Timer */
+#define WDT_BASE		0x480C2000
+
+/* Control Module Base Address */
+#define CTRL_BASE		0x48140000
+#define CTRL_DEVICE_BASE	0x48140600
+
+/* PRCM Base Address */
+#define PRCM_BASE		0x48180000
+
+#define PRM_RSTCTRL		(PRCM_BASE + 0x00A0)
+#define PRM_RSTST		(PRM_RSTCTRL + 8)
+
+/* VTP Base address */
+#define VTP0_CTRL_ADDR		0x48198358
+#define VTP1_CTRL_ADDR		0x4819A358
+
+/* DDR Base address */
+#define DDR_PHY_CMD_ADDR	0x48198000
+#define DDR_PHY_DATA_ADDR	0x481980C8
+#define DDR_PHY_CMD_ADDR2	0x4819A000
+#define DDR_PHY_DATA_ADDR2	0x4819A0C8
+#define DDR_DATA_REGS_NR	4
+
+
+#define DDRPHY_0_CONFIG_BASE	0x48198000
+#define DDRPHY_1_CONFIG_BASE	0x4819A000
+#define DDRPHY_CONFIG_BASE	((emif == 0) ? \
+	DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE)
+
+/* RTC base address */
+#define RTC_BASE		0x480C0000
+
+#endif /* __AM33XX_HARDWARE_TI816X_H */
diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h
new file mode 100644
index 0000000..c2a9850
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/i2c.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef _I2C_AM33XX_H_
+#define _I2C_AM33XX_H_
+
+#include <asm/omap_i2c.h>
+
+#define  I2C_BASE1		0x44E0B000
+#define  I2C_BASE2		0x4802A000
+#define  I2C_BASE3		0x4819C000
+
+#define I2C_DEFAULT_BASE		I2C_BASE1
+
+#define I2C_IP_CLK			48000000
+#define I2C_INTERNAL_SAMPLING_CLK	12000000
+
+#endif /* _I2C_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
new file mode 100644
index 0000000..0fd52f8
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ *		Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *		Richard Woodruff <r-woodruff2@ti.com>
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * M_NAND - Micron NAND
+ * STNOR - STMicrolelctronics M29W128GL
+ */
+#define GPMC_SIZE_256M		0x0
+#define GPMC_SIZE_128M		0x8
+#define GPMC_SIZE_64M		0xC
+#define GPMC_SIZE_32M		0xE
+#define GPMC_SIZE_16M		0xF
+
+#define M_NAND_GPMC_CONFIG1	0x00000800
+#define M_NAND_GPMC_CONFIG2	0x001e1e00
+#define M_NAND_GPMC_CONFIG3	0x001e1e00
+#define M_NAND_GPMC_CONFIG4	0x16051807
+#define M_NAND_GPMC_CONFIG5	0x00151e1e
+#define M_NAND_GPMC_CONFIG6	0x16000f80
+#define M_NAND_GPMC_CONFIG7	0x00000008
+
+#define STNOR_GPMC_CONFIG1	0x00001200
+#define STNOR_GPMC_CONFIG2	0x00101000
+#define STNOR_GPMC_CONFIG3	0x00030301
+#define STNOR_GPMC_CONFIG4	0x10041004
+#define STNOR_GPMC_CONFIG5	0x000C1010
+#define STNOR_GPMC_CONFIG6	0x08070280
+#define STNOR_GPMC_CONFIG7	0x00000F48
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS		8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG		7
+
+#define DBG_MPDB		6
+
+#endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
new file mode 100644
index 0000000..5a2ea8f
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h
@@ -0,0 +1,35 @@
+/*
+ * mmc_host_def.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+#include <asm/omap_mmc.h>
+
+/*
+ * OMAP HSMMC register definitions
+ */
+#define OMAP_HSMMC1_BASE		0x48060000
+#define OMAP_HSMMC2_BASE		0x481D8000
+
+#if defined(CONFIG_TI814X)
+#undef MMC_CLOCK_REFERENCE
+#define MMC_CLOCK_REFERENCE	192 /* MHz */
+#elif defined(CONFIG_TI816X)
+#undef MMC_CLOCK_REFERENCE
+#define MMC_CLOCK_REFERENCE	48 /* MHz */
+#endif
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
new file mode 100644
index 0000000..d8bf872
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -0,0 +1,47 @@
+/*
+ * mux.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_H_
+#define _MUX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_AM33XX
+#include <asm/arch/mux_am33xx.h>
+#elif defined(CONFIG_TI814X)
+#include <asm/arch/mux_ti814x.h>
+#elif defined(CONFIG_TI816X)
+#include <asm/arch/mux_ti816x.h>
+#elif defined(CONFIG_AM43XX)
+#include <asm/arch/mux_am43xx.h>
+#endif
+
+struct module_pin_mux {
+	short reg_offset;
+	unsigned int val;
+};
+
+/* Pad control register offset */
+#define PAD_CTRL_BASE	0x800
+#define OFFSET(x)	(unsigned int) (&((struct pad_signals *)\
+				(PAD_CTRL_BASE))->x)
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
+
+#endif /* endif _MUX_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
new file mode 100644
index 0000000..d5cab3e
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h
@@ -0,0 +1,247 @@
+/*
+ * mux_am33xx.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_AM33XX_H_
+#define _MUX_AM33XX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset)	\
+	__raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL	(0x1 << 6)
+#define RXACTIVE	(0x1 << 5)
+#define PULLDOWN_EN	(0x0 << 4) /* Pull Down Selection */
+#define PULLUP_EN	(0x1 << 4) /* Pull Up Selection */
+#define PULLUDEN	(0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
+#define MODE(val)	val	/* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int gpmc_ad0;
+	int gpmc_ad1;
+	int gpmc_ad2;
+	int gpmc_ad3;
+	int gpmc_ad4;
+	int gpmc_ad5;
+	int gpmc_ad6;
+	int gpmc_ad7;
+	int gpmc_ad8;
+	int gpmc_ad9;
+	int gpmc_ad10;
+	int gpmc_ad11;
+	int gpmc_ad12;
+	int gpmc_ad13;
+	int gpmc_ad14;
+	int gpmc_ad15;
+	int gpmc_a0;
+	int gpmc_a1;
+	int gpmc_a2;
+	int gpmc_a3;
+	int gpmc_a4;
+	int gpmc_a5;
+	int gpmc_a6;
+	int gpmc_a7;
+	int gpmc_a8;
+	int gpmc_a9;
+	int gpmc_a10;
+	int gpmc_a11;
+	int gpmc_wait0;
+	int gpmc_wpn;
+	int gpmc_be1n;
+	int gpmc_csn0;
+	int gpmc_csn1;
+	int gpmc_csn2;
+	int gpmc_csn3;
+	int gpmc_clk;
+	int gpmc_advn_ale;
+	int gpmc_oen_ren;
+	int gpmc_wen;
+	int gpmc_be0n_cle;
+	int lcd_data0;
+	int lcd_data1;
+	int lcd_data2;
+	int lcd_data3;
+	int lcd_data4;
+	int lcd_data5;
+	int lcd_data6;
+	int lcd_data7;
+	int lcd_data8;
+	int lcd_data9;
+	int lcd_data10;
+	int lcd_data11;
+	int lcd_data12;
+	int lcd_data13;
+	int lcd_data14;
+	int lcd_data15;
+	int lcd_vsync;
+	int lcd_hsync;
+	int lcd_pclk;
+	int lcd_ac_bias_en;
+	int mmc0_dat3;
+	int mmc0_dat2;
+	int mmc0_dat1;
+	int mmc0_dat0;
+	int mmc0_clk;
+	int mmc0_cmd;
+	int mii1_col;
+	int mii1_crs;
+	int mii1_rxerr;
+	int mii1_txen;
+	int mii1_rxdv;
+	int mii1_txd3;
+	int mii1_txd2;
+	int mii1_txd1;
+	int mii1_txd0;
+	int mii1_txclk;
+	int mii1_rxclk;
+	int mii1_rxd3;
+	int mii1_rxd2;
+	int mii1_rxd1;
+	int mii1_rxd0;
+	int rmii1_refclk;
+	int mdio_data;
+	int mdio_clk;
+	int spi0_sclk;
+	int spi0_d0;
+	int spi0_d1;
+	int spi0_cs0;
+	int spi0_cs1;
+	int ecap0_in_pwm0_out;
+	int uart0_ctsn;
+	int uart0_rtsn;
+	int uart0_rxd;
+	int uart0_txd;
+	int uart1_ctsn;
+	int uart1_rtsn;
+	int uart1_rxd;
+	int uart1_txd;
+	int i2c0_sda;
+	int i2c0_scl;
+	int mcasp0_aclkx;
+	int mcasp0_fsx;
+	int mcasp0_axr0;
+	int mcasp0_ahclkr;
+	int mcasp0_aclkr;
+	int mcasp0_fsr;
+	int mcasp0_axr1;
+	int mcasp0_ahclkx;
+	int xdma_event_intr0;
+	int xdma_event_intr1;
+	int nresetin_out;
+	int porz;
+	int nnmi;
+	int osc0_in;
+	int osc0_out;
+	int rsvd1;
+	int tms;
+	int tdi;
+	int tdo;
+	int tck;
+	int ntrst;
+	int emu0;
+	int emu1;
+	int osc1_in;
+	int osc1_out;
+	int pmic_power_en;
+	int rtc_porz;
+	int rsvd2;
+	int ext_wakeup;
+	int enz_kaldo_1p8v;
+	int usb0_dm;
+	int usb0_dp;
+	int usb0_ce;
+	int usb0_id;
+	int usb0_vbus;
+	int usb0_drvvbus;
+	int usb1_dm;
+	int usb1_dp;
+	int usb1_ce;
+	int usb1_id;
+	int usb1_vbus;
+	int usb1_drvvbus;
+	int ddr_resetn;
+	int ddr_csn0;
+	int ddr_cke;
+	int ddr_ck;
+	int ddr_nck;
+	int ddr_casn;
+	int ddr_rasn;
+	int ddr_wen;
+	int ddr_ba0;
+	int ddr_ba1;
+	int ddr_ba2;
+	int ddr_a0;
+	int ddr_a1;
+	int ddr_a2;
+	int ddr_a3;
+	int ddr_a4;
+	int ddr_a5;
+	int ddr_a6;
+	int ddr_a7;
+	int ddr_a8;
+	int ddr_a9;
+	int ddr_a10;
+	int ddr_a11;
+	int ddr_a12;
+	int ddr_a13;
+	int ddr_a14;
+	int ddr_a15;
+	int ddr_odt;
+	int ddr_d0;
+	int ddr_d1;
+	int ddr_d2;
+	int ddr_d3;
+	int ddr_d4;
+	int ddr_d5;
+	int ddr_d6;
+	int ddr_d7;
+	int ddr_d8;
+	int ddr_d9;
+	int ddr_d10;
+	int ddr_d11;
+	int ddr_d12;
+	int ddr_d13;
+	int ddr_d14;
+	int ddr_d15;
+	int ddr_dqm0;
+	int ddr_dqm1;
+	int ddr_dqs0;
+	int ddr_dqsn0;
+	int ddr_dqs1;
+	int ddr_dqsn1;
+	int ddr_vref;
+	int ddr_vtp;
+	int ddr_strben0;
+	int ddr_strben1;
+	int ain7;
+	int ain6;
+	int ain5;
+	int ain4;
+	int ain3;
+	int ain2;
+	int ain1;
+	int ain0;
+	int vrefp;
+	int vrefn;
+};
+
+#endif /* endif _MUX_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
new file mode 100644
index 0000000..256c5e2
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * mux_am43xx.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef _MUX_AM43XX_H_
+#define _MUX_AM43XX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset)	\
+	__raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL	(0x1 << 19)
+#define RXACTIVE	(0x1 << 18)
+#define PULLDOWN_EN	(0x0 << 17) /* Pull Down Selection */
+#define PULLUP_EN	(0x1 << 17) /* Pull Up Selection */
+#define PULLUDEN	(0x0 << 16) /* Pull up/down enable */
+#define PULLUDDIS	(0x1 << 16) /* Pull up/down disable */
+#define MODE(val)	val	/* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int gpmc_ad0;
+	int gpmc_ad1;
+	int gpmc_ad2;
+	int gpmc_ad3;
+	int gpmc_ad4;
+	int gpmc_ad5;
+	int gpmc_ad6;
+	int gpmc_ad7;
+	int gpmc_ad8;
+	int gpmc_ad9;
+	int gpmc_ad10;
+	int gpmc_ad11;
+	int gpmc_ad12;
+	int gpmc_ad13;
+	int gpmc_ad14;
+	int gpmc_ad15;
+	int gpmc_a0;
+	int gpmc_a1;
+	int gpmc_a2;
+	int gpmc_a3;
+	int gpmc_a4;
+	int gpmc_a5;
+	int gpmc_a6;
+	int gpmc_a7;
+	int gpmc_a8;
+	int gpmc_a9;
+	int gpmc_a10;
+	int gpmc_a11;
+	int gpmc_wait0;
+	int gpmc_wpn;
+	int gpmc_be1n;
+	int gpmc_csn0;
+	int gpmc_csn1;
+	int gpmc_csn2;
+	int gpmc_csn3;
+	int gpmc_clk;
+	int gpmc_advn_ale;
+	int gpmc_oen_ren;
+	int gpmc_wen;
+	int gpmc_be0n_cle;
+	int lcd_data0;
+	int lcd_data1;
+	int lcd_data2;
+	int lcd_data3;
+	int lcd_data4;
+	int lcd_data5;
+	int lcd_data6;
+	int lcd_data7;
+	int lcd_data8;
+	int lcd_data9;
+	int lcd_data10;
+	int lcd_data11;
+	int lcd_data12;
+	int lcd_data13;
+	int lcd_data14;
+	int lcd_data15;
+	int lcd_vsync;
+	int lcd_hsync;
+	int lcd_pclk;
+	int lcd_ac_bias_en;
+	int mmc0_dat3;
+	int mmc0_dat2;
+	int mmc0_dat1;
+	int mmc0_dat0;
+	int mmc0_clk;
+	int mmc0_cmd;
+	int mii1_col;
+	int mii1_crs;
+	int mii1_rxerr;
+	int mii1_txen;
+	int mii1_rxdv;
+	int mii1_txd3;
+	int mii1_txd2;
+	int mii1_txd1;
+	int mii1_txd0;
+	int mii1_txclk;
+	int mii1_rxclk;
+	int mii1_rxd3;
+	int mii1_rxd2;
+	int mii1_rxd1;
+	int mii1_rxd0;
+	int rmii1_refclk;
+	int mdio_data;
+	int mdio_clk;
+	int spi0_sclk;
+	int spi0_d0;
+	int spi0_d1;
+	int spi0_cs0;
+	int spi0_cs1;
+	int ecap0_in_pwm0_out;
+	int uart0_ctsn;
+	int uart0_rtsn;
+	int uart0_rxd;
+	int uart0_txd;
+	int uart1_ctsn;
+	int uart1_rtsn;
+	int uart1_rxd;
+	int uart1_txd;
+	int i2c0_sda;
+	int i2c0_scl;
+	int mcasp0_aclkx;
+	int mcasp0_fsx;
+	int mcasp0_axr0;
+	int mcasp0_ahclkr;
+	int mcasp0_aclkr;
+	int mcasp0_fsr;
+	int mcasp0_axr1;
+	int mcasp0_ahclkx;
+	int cam0_hd;
+	int cam0_vd;
+	int cam0_field;
+	int cam0_wen;
+	int cam0_pclk;
+	int cam0_data8;
+	int cam0_data9;
+	int cam1_data9;
+	int cam1_data8;
+	int cam1_hd;
+	int cam1_vd;
+	int cam1_pclk;
+	int cam1_field;
+	int cam1_wen;
+	int cam1_data0;
+	int cam1_data1;
+	int cam1_data2;
+	int cam1_data3;
+	int cam1_data4;
+	int cam1_data5;
+	int cam1_data6;
+	int cam1_data7;
+	int cam0_data0;
+	int cam0_data1;
+	int cam0_data2;
+	int cam0_data3;
+	int cam0_data4;
+	int cam0_data5;
+	int cam0_data6;
+	int cam0_data7;
+	int uart3_rxd;
+	int uart3_txd;
+	int uart3_ctsn;
+	int uart3_rtsn;
+	int gpio5_8;
+	int gpio5_9;
+	int gpio5_10;
+	int gpio5_11;
+	int gpio5_12;
+	int gpio5_13;
+	int spi4_sclk;
+	int spi4_d0;
+	int spi4_d1;
+	int spi4_cs0;
+	int spi2_sclk;
+	int spi2_d0;
+	int spi2_d1;
+	int spi2_cs0;
+	int xdma_evt_intr0;
+	int xdma_evt_intr1;
+	int clkreq;
+	int nresetin_out;
+	int rsvd1;
+	int nnmi;
+	int rsvd2;
+	int rsvd3;
+	int tms;
+	int tdi;
+	int tdo;
+	int tck;
+	int ntrst;
+	int emu0;
+	int emu1;
+	int osc1_in;
+	int osc1_out;
+	int rtc_porz;
+	int ext_wakeup0;
+	int pmic_power_en0;
+	int usb0_drvvbus;
+	int usb1_drvvbus;
+};
+
+#endif /* _MUX_AM43XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h
new file mode 100644
index 0000000..a26e503
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h
@@ -0,0 +1,311 @@
+/*
+ * mux_ti814x.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_TI814X_H_
+#define _MUX_TI814X_H_
+
+/* PAD Control Fields */
+#define PINCNTL_RSV_MSK	(0x3 << 18) /* Reserved bitmask */
+#define PULLUP_EN	(0x1 << 17) /* Pull UP Selection */
+#define PULLUDEN	(0x0 << 16) /* Pull up enabled */
+#define PULLUDDIS	(0x1 << 16) /* Pull up disabled */
+#define MODE(val)	val	/* used for Readability */
+
+#define MUX_CFG(value, offset)				\
+{							\
+	int tmp;					\
+	tmp = __raw_readl(CTRL_BASE + offset);		\
+	tmp &= PINCNTL_RSV_MSK;				\
+	__raw_writel(tmp | value, (CTRL_BASE + offset));\
+}
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int pincntl1;
+	int pincntl2;
+	int pincntl3;
+	int pincntl4;
+	int pincntl5;
+	int pincntl6;
+	int pincntl7;
+	int pincntl8;
+	int pincntl9;
+	int pincntl10;
+	int pincntl11;
+	int pincntl12;
+	int pincntl13;
+	int pincntl14;
+	int pincntl15;
+	int pincntl16;
+	int pincntl17;
+	int pincntl18;
+	int pincntl19;
+	int pincntl20;
+	int pincntl21;
+	int pincntl22;
+	int pincntl23;
+	int pincntl24;
+	int pincntl25;
+	int pincntl26;
+	int pincntl27;
+	int pincntl28;
+	int pincntl29;
+	int pincntl30;
+	int pincntl31;
+	int pincntl32;
+	int pincntl33;
+	int pincntl34;
+	int pincntl35;
+	int pincntl36;
+	int pincntl37;
+	int pincntl38;
+	int pincntl39;
+	int pincntl40;
+	int pincntl41;
+	int pincntl42;
+	int pincntl43;
+	int pincntl44;
+	int pincntl45;
+	int pincntl46;
+	int pincntl47;
+	int pincntl48;
+	int pincntl49;
+	int pincntl50;
+	int pincntl51;
+	int pincntl52;
+	int pincntl53;
+	int pincntl54;
+	int pincntl55;
+	int pincntl56;
+	int pincntl57;
+	int pincntl58;
+	int pincntl59;
+	int pincntl60;
+	int pincntl61;
+	int pincntl62;
+	int pincntl63;
+	int pincntl64;
+	int pincntl65;
+	int pincntl66;
+	int pincntl67;
+	int pincntl68;
+	int pincntl69;
+	int pincntl70;
+	int pincntl71;
+	int pincntl72;
+	int pincntl73;
+	int pincntl74;
+	int pincntl75;
+	int pincntl76;
+	int pincntl77;
+	int pincntl78;
+	int pincntl79;
+	int pincntl80;
+	int pincntl81;
+	int pincntl82;
+	int pincntl83;
+	int pincntl84;
+	int pincntl85;
+	int pincntl86;
+	int pincntl87;
+	int pincntl88;
+	int pincntl89;
+	int pincntl90;
+	int pincntl91;
+	int pincntl92;
+	int pincntl93;
+	int pincntl94;
+	int pincntl95;
+	int pincntl96;
+	int pincntl97;
+	int pincntl98;
+	int pincntl99;
+	int pincntl100;
+	int pincntl101;
+	int pincntl102;
+	int pincntl103;
+	int pincntl104;
+	int pincntl105;
+	int pincntl106;
+	int pincntl107;
+	int pincntl108;
+	int pincntl109;
+	int pincntl110;
+	int pincntl111;
+	int pincntl112;
+	int pincntl113;
+	int pincntl114;
+	int pincntl115;
+	int pincntl116;
+	int pincntl117;
+	int pincntl118;
+	int pincntl119;
+	int pincntl120;
+	int pincntl121;
+	int pincntl122;
+	int pincntl123;
+	int pincntl124;
+	int pincntl125;
+	int pincntl126;
+	int pincntl127;
+	int pincntl128;
+	int pincntl129;
+	int pincntl130;
+	int pincntl131;
+	int pincntl132;
+	int pincntl133;
+	int pincntl134;
+	int pincntl135;
+	int pincntl136;
+	int pincntl137;
+	int pincntl138;
+	int pincntl139;
+	int pincntl140;
+	int pincntl141;
+	int pincntl142;
+	int pincntl143;
+	int pincntl144;
+	int pincntl145;
+	int pincntl146;
+	int pincntl147;
+	int pincntl148;
+	int pincntl149;
+	int pincntl150;
+	int pincntl151;
+	int pincntl152;
+	int pincntl153;
+	int pincntl154;
+	int pincntl155;
+	int pincntl156;
+	int pincntl157;
+	int pincntl158;
+	int pincntl159;
+	int pincntl160;
+	int pincntl161;
+	int pincntl162;
+	int pincntl163;
+	int pincntl164;
+	int pincntl165;
+	int pincntl166;
+	int pincntl167;
+	int pincntl168;
+	int pincntl169;
+	int pincntl170;
+	int pincntl171;
+	int pincntl172;
+	int pincntl173;
+	int pincntl174;
+	int pincntl175;
+	int pincntl176;
+	int pincntl177;
+	int pincntl178;
+	int pincntl179;
+	int pincntl180;
+	int pincntl181;
+	int pincntl182;
+	int pincntl183;
+	int pincntl184;
+	int pincntl185;
+	int pincntl186;
+	int pincntl187;
+	int pincntl188;
+	int pincntl189;
+	int pincntl190;
+	int pincntl191;
+	int pincntl192;
+	int pincntl193;
+	int pincntl194;
+	int pincntl195;
+	int pincntl196;
+	int pincntl197;
+	int pincntl198;
+	int pincntl199;
+	int pincntl200;
+	int pincntl201;
+	int pincntl202;
+	int pincntl203;
+	int pincntl204;
+	int pincntl205;
+	int pincntl206;
+	int pincntl207;
+	int pincntl208;
+	int pincntl209;
+	int pincntl210;
+	int pincntl211;
+	int pincntl212;
+	int pincntl213;
+	int pincntl214;
+	int pincntl215;
+	int pincntl216;
+	int pincntl217;
+	int pincntl218;
+	int pincntl219;
+	int pincntl220;
+	int pincntl221;
+	int pincntl222;
+	int pincntl223;
+	int pincntl224;
+	int pincntl225;
+	int pincntl226;
+	int pincntl227;
+	int pincntl228;
+	int pincntl229;
+	int pincntl230;
+	int pincntl231;
+	int pincntl232;
+	int pincntl233;
+	int pincntl234;
+	int pincntl235;
+	int pincntl236;
+	int pincntl237;
+	int pincntl238;
+	int pincntl239;
+	int pincntl240;
+	int pincntl241;
+	int pincntl242;
+	int pincntl243;
+	int pincntl244;
+	int pincntl245;
+	int pincntl246;
+	int pincntl247;
+	int pincntl248;
+	int pincntl249;
+	int pincntl250;
+	int pincntl251;
+	int pincntl252;
+	int pincntl253;
+	int pincntl254;
+	int pincntl255;
+	int pincntl256;
+	int pincntl257;
+	int pincntl258;
+	int pincntl259;
+	int pincntl260;
+	int pincntl261;
+	int pincntl262;
+	int pincntl263;
+	int pincntl264;
+	int pincntl265;
+	int pincntl266;
+	int pincntl267;
+	int pincntl268;
+	int pincntl269;
+	int pincntl270;
+};
+
+#endif /* endif _MUX_TI814X_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
new file mode 100644
index 0000000..e4e5a48
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h
@@ -0,0 +1,363 @@
+/*
+ * mux_ti816x.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_TI816X_H_
+#define _MUX_TI816X_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset)  \
+	__raw_writel(value, (CTRL_BASE + offset));
+
+#define PULLDOWN_EN	(0x0 << 4)	/* Pull Down Selection */
+#define PULLUP_EN	(0x1 << 4)	/* Pull Up Selection */
+#define PULLUDEN	(0x0 << 3)	/* Pull up enabled */
+#define PULLUDDIS	(0x1 << 3)	/* Pull up disabled */
+#define MODE(val)	(val)		/* used for Readability */
+
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int pincntl1;
+	int pincntl2;
+	int pincntl3;
+	int pincntl4;
+	int pincntl5;
+	int pincntl6;
+	int pincntl7;
+	int pincntl8;
+	int pincntl9;
+	int pincntl10;
+	int pincntl11;
+	int pincntl12;
+	int pincntl13;
+	int pincntl14;
+	int pincntl15;
+	int pincntl16;
+	int pincntl17;
+	int pincntl18;
+	int pincntl19;
+	int pincntl20;
+	int pincntl21;
+	int pincntl22;
+	int pincntl23;
+	int pincntl24;
+	int pincntl25;
+	int pincntl26;
+	int pincntl27;
+	int pincntl28;
+	int pincntl29;
+	int pincntl30;
+	int pincntl31;
+	int pincntl32;
+	int pincntl33;
+	int pincntl34;
+	int pincntl35;
+	int pincntl36;
+	int pincntl37;
+	int pincntl38;
+	int pincntl39;
+	int pincntl40;
+	int pincntl41;
+	int pincntl42;
+	int pincntl43;
+	int pincntl44;
+	int pincntl45;
+	int pincntl46;
+	int pincntl47;
+	int pincntl48;
+	int pincntl49;
+	int pincntl50;
+	int pincntl51;
+	int pincntl52;
+	int pincntl53;
+	int pincntl54;
+	int pincntl55;
+	int pincntl56;
+	int pincntl57;
+	int pincntl58;
+	int pincntl59;
+	int pincntl60;
+	int pincntl61;
+	int pincntl62;
+	int pincntl63;
+	int pincntl64;
+	int pincntl65;
+	int pincntl66;
+	int pincntl67;
+	int pincntl68;
+	int pincntl69;
+	int pincntl70;
+	int pincntl71;
+	int pincntl72;
+	int pincntl73;
+	int pincntl74;
+	int pincntl75;
+	int pincntl76;
+	int pincntl77;
+	int pincntl78;
+	int pincntl79;
+	int pincntl80;
+	int pincntl81;
+	int pincntl82;
+	int pincntl83;
+	int pincntl84;
+	int pincntl85;
+	int pincntl86;
+	int pincntl87;
+	int pincntl88;
+	int pincntl89;
+	int pincntl90;
+	int pincntl91;
+	int pincntl92;
+	int pincntl93;
+	int pincntl94;
+	int pincntl95;
+	int pincntl96;
+	int pincntl97;
+	int pincntl98;
+	int pincntl99;
+	int pincntl100;
+	int pincntl101;
+	int pincntl102;
+	int pincntl103;
+	int pincntl104;
+	int pincntl105;
+	int pincntl106;
+	int pincntl107;
+	int pincntl108;
+	int pincntl109;
+	int pincntl110;
+	int pincntl111;
+	int pincntl112;
+	int pincntl113;
+	int pincntl114;
+	int pincntl115;
+	int pincntl116;
+	int pincntl117;
+	int pincntl118;
+	int pincntl119;
+	int pincntl120;
+	int pincntl121;
+	int pincntl122;
+	int pincntl123;
+	int pincntl124;
+	int pincntl125;
+	int pincntl126;
+	int pincntl127;
+	int pincntl128;
+	int pincntl129;
+	int pincntl130;
+	int pincntl131;
+	int pincntl132;
+	int pincntl133;
+	int pincntl134;
+	int pincntl135;
+	int pincntl136;
+	int pincntl137;
+	int pincntl138;
+	int pincntl139;
+	int pincntl140;
+	int pincntl141;
+	int pincntl142;
+	int pincntl143;
+	int pincntl144;
+	int pincntl145;
+	int pincntl146;
+	int pincntl147;
+	int pincntl148;
+	int pincntl149;
+	int pincntl150;
+	int pincntl151;
+	int pincntl152;
+	int pincntl153;
+	int pincntl154;
+	int pincntl155;
+	int pincntl156;
+	int pincntl157;
+	int pincntl158;
+	int pincntl159;
+	int pincntl160;
+	int pincntl161;
+	int pincntl162;
+	int pincntl163;
+	int pincntl164;
+	int pincntl165;
+	int pincntl166;
+	int pincntl167;
+	int pincntl168;
+	int pincntl169;
+	int pincntl170;
+	int pincntl171;
+	int pincntl172;
+	int pincntl173;
+	int pincntl174;
+	int pincntl175;
+	int pincntl176;
+	int pincntl177;
+	int pincntl178;
+	int pincntl179;
+	int pincntl180;
+	int pincntl181;
+	int pincntl182;
+	int pincntl183;
+	int pincntl184;
+	int pincntl185;
+	int pincntl186;
+	int pincntl187;
+	int pincntl188;
+	int pincntl189;
+	int pincntl190;
+	int pincntl191;
+	int pincntl192;
+	int pincntl193;
+	int pincntl194;
+	int pincntl195;
+	int pincntl196;
+	int pincntl197;
+	int pincntl198;
+	int pincntl199;
+	int pincntl200;
+	int pincntl201;
+	int pincntl202;
+	int pincntl203;
+	int pincntl204;
+	int pincntl205;
+	int pincntl206;
+	int pincntl207;
+	int pincntl208;
+	int pincntl209;
+	int pincntl210;
+	int pincntl211;
+	int pincntl212;
+	int pincntl213;
+	int pincntl214;
+	int pincntl215;
+	int pincntl216;
+	int pincntl217;
+	int pincntl218;
+	int pincntl219;
+	int pincntl220;
+	int pincntl221;
+	int pincntl222;
+	int pincntl223;
+	int pincntl224;
+	int pincntl225;
+	int pincntl226;
+	int pincntl227;
+	int pincntl228;
+	int pincntl229;
+	int pincntl230;
+	int pincntl231;
+	int pincntl232;
+	int pincntl233;
+	int pincntl234;
+	int pincntl235;
+	int pincntl236;
+	int pincntl237;
+	int pincntl238;
+	int pincntl239;
+	int pincntl240;
+	int pincntl241;
+	int pincntl242;
+	int pincntl243;
+	int pincntl244;
+	int pincntl245;
+	int pincntl246;
+	int pincntl247;
+	int pincntl248;
+	int pincntl249;
+	int pincntl250;
+	int pincntl251;
+	int pincntl252;
+	int pincntl253;
+	int pincntl254;
+	int pincntl255;
+	int pincntl256;
+	int pincntl257;
+	int pincntl258;
+	int pincntl259;
+	int pincntl260;
+	int pincntl261;
+	int pincntl262;
+	int pincntl263;
+	int pincntl264;
+	int pincntl265;
+	int pincntl266;
+	int pincntl267;
+	int pincntl268;
+	int pincntl269;
+	int pincntl270;
+	int pincntl271;
+	int pincntl272;
+	int pincntl273;
+	int pincntl274;
+	int pincntl275;
+	int pincntl276;
+	int pincntl277;
+	int pincntl278;
+	int pincntl279;
+	int pincntl280;
+	int pincntl281;
+	int pincntl282;
+	int pincntl283;
+	int pincntl284;
+	int pincntl285;
+	int pincntl286;
+	int pincntl287;
+	int pincntl288;
+	int pincntl289;
+	int pincntl290;
+	int pincntl291;
+	int pincntl292;
+	int pincntl293;
+	int pincntl294;
+	int pincntl295;
+	int pincntl296;
+	int pincntl297;
+	int pincntl298;
+	int pincntl299;
+	int pincntl300;
+	int pincntl301;
+	int pincntl302;
+	int pincntl303;
+	int pincntl304;
+	int pincntl305;
+	int pincntl306;
+	int pincntl307;
+	int pincntl308;
+	int pincntl309;
+	int pincntl310;
+	int pincntl311;
+	int pincntl312;
+	int pincntl313;
+	int pincntl314;
+	int pincntl315;
+	int pincntl316;
+	int pincntl317;
+	int pincntl318;
+	int pincntl319;
+	int pincntl320;
+	int pincntl321;
+	int pincntl322;
+	int pincntl323;
+};
+
+#endif /* endif _MUX_TI816X_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
new file mode 100644
index 0000000..bc9f0a1
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * omap.h
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * Author:
+ *	Chandan Nath <chandan.nath@ti.com>
+ *
+ * Derived from OMAP4 work by
+ *	Aneesh V <aneesh@ti.com>
+ */
+
+#ifndef _OMAP_H_
+#define _OMAP_H_
+
+#include <linux/sizes.h>
+
+#ifdef CONFIG_AM33XX
+#define NON_SECURE_SRAM_START	0x402F0400
+#define NON_SECURE_SRAM_END	0x40310000
+#define NON_SECURE_SRAM_IMG_END	0x4030B800
+#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
+#define NON_SECURE_SRAM_START	0x40300000
+#define NON_SECURE_SRAM_END	0x40320000
+#define NON_SECURE_SRAM_IMG_END	0x4031B800
+#elif defined(CONFIG_AM43XX)
+#define NON_SECURE_SRAM_START	0x402F0400
+#define NON_SECURE_SRAM_END	0x40340000
+#define NON_SECURE_SRAM_IMG_END	0x40337DE0
+#define QSPI_BASE              0x47900000
+#endif
+#define SRAM_SCRATCH_SPACE_ADDR	(NON_SECURE_SRAM_IMG_END - SZ_1K)
+
+/* Boot parameters */
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+	unsigned int reserved;
+	unsigned int boot_device_descriptor;
+	unsigned char boot_device;
+	unsigned char reset_reason;
+};
+
+#define DEVICE_TYPE_SHIFT		0x8
+#define DEVICE_TYPE_MASK		(0x7 << DEVICE_TYPE_SHIFT)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
new file mode 100644
index 0000000..f3910c2
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NONE	0x00
+#define BOOT_DEVICE_MMC2_2	0xFF
+
+#if defined(CONFIG_TI814X)
+#define BOOT_DEVICE_XIP		0x01
+#define BOOT_DEVICE_XIPWAIT	0x02
+#define BOOT_DEVICE_NAND	0x05
+#define BOOT_DEVICE_NAND_I2C	0x06
+#define BOOT_DEVICE_MMC2	0x08 /* ROM only supports 2nd instance. */
+#define BOOT_DEVICE_MMC1	0x09
+#define BOOT_DEVICE_SPI		0x15
+#define BOOT_DEVICE_UART	0x41
+#define BOOT_DEVICE_USBETH	0x44
+#define BOOT_DEVICE_CPGMAC	0x46
+
+#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC2
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC1
+#elif defined(CONFIG_TI816X)
+#define BOOT_DEVICE_XIP		0x01
+#define BOOT_DEVICE_XIPWAIT	0x02
+#define BOOT_DEVICE_NAND	0x03
+#define BOOT_DEVICE_ONENAND	0x04
+#define BOOT_DEVICE_MMC2	0x05 /* ROM only supports 2nd instance. */
+#define BOOT_DEVICE_MMC1	0x06
+#define BOOT_DEVICE_UART	0x43
+#define BOOT_DEVICE_USB		0x45
+
+#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC2
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC1
+#elif defined(CONFIG_AM33XX)
+#define BOOT_DEVICE_XIP		0x01
+#define BOOT_DEVICE_XIPWAIT	0x02
+#define BOOT_DEVICE_NAND	0x05
+#define BOOT_DEVICE_NAND_I2C	0x06
+#define BOOT_DEVICE_MMC1	0x08
+#define BOOT_DEVICE_MMC2	0x09
+#define BOOT_DEVICE_SPI		0x0B
+#define BOOT_DEVICE_UART	0x41
+#define BOOT_DEVICE_USBETH	0x44
+#define BOOT_DEVICE_CPGMAC	0x46
+#define BOOT_DEVICE_ONENAND	0xFF /* ROM does not support OneNAND. */
+
+#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2
+#elif defined(CONFIG_AM43XX)
+#define BOOT_DEVICE_NOR		0x01
+#define BOOT_DEVICE_NAND	0x05
+#define BOOT_DEVICE_MMC1	0x07
+#define BOOT_DEVICE_MMC2	0x08
+#define BOOT_DEVICE_SPI		0x0A
+#define BOOT_DEVICE_USB		0x0D
+#define BOOT_DEVICE_UART	0x41
+#define BOOT_DEVICE_USBETH	0x45
+#define BOOT_DEVICE_CPGMAC	0x47
+
+#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
+#ifdef CONFIG_SPL_USB_STORAGE
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_USB
+#else
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2
+#endif
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
new file mode 100644
index 0000000..be17aad
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * sys_proto.h
+ *
+ * System information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+#include <linux/mtd/omap_gpmc.h>
+#include <asm/arch/cpu.h>
+
+u32 get_cpu_rev(void);
+u32 get_sysboot_value(void);
+
+extern struct ctrl_stat *cstat;
+u32 get_device_type(void);
+void save_omap_boot_params(void);
+void setup_early_clocks(void);
+void setup_clocks_for_console(void);
+void mpu_pll_config_val(int mpull_m);
+void ddr_pll_config(unsigned int ddrpll_M);
+
+void sdelay(unsigned long);
+
+void gpmc_init(void);
+void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base,
+			u32 size);
+int omap_nand_switch_ecc(uint32_t, uint32_t);
+
+void set_uart_mux_conf(void);
+void set_mux_conf_regs(void);
+void sdram_init(void);
+u32 wait_on_value(u32, u32, void *, u32);
+#ifdef CONFIG_NOR_BOOT
+void enable_norboot_pin_mux(void);
+#endif
+void am33xx_spl_board_init(void);
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
+int am335x_get_mpu_vdd(int sil_rev, int frequency);
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
+#endif
+
+void enable_usb_clocks(int index);
+void disable_usb_clocks(int index);
+void do_board_detect(void);
+u32 get_sys_clk_index(void);
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
new file mode 100644
index 0000000..dd21ad3
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#ifndef _ASM_ARCH_ARMADA100_H
+#define _ASM_ARCH_ARMADA100_H
+
+#if defined (CONFIG_ARMADA100)
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
+#define APBC_RST        (1<<2)  /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
+
+/* Fast Ethernet Controller Clock register definition */
+#define FE_CLK_RST		0x1
+#define FE_CLK_ENA		0x8
+
+/* SSP2 Clock Control */
+#define SSP2_APBCLK		0x01
+#define SSP2_FNCLK		0x02
+
+/* USB Clock/reset control bits */
+#define USB_SPH_AXICLK_EN	0x10
+#define USB_SPH_AXI_RST		0x02
+
+/* MPMU Clocks */
+#define APB2_26M_EN		(1 << 20)
+#define AP_26M			(1 << 4)
+
+/* Register Base Addresses */
+#define ARMD1_DRAM_BASE		0xB0000000
+#define ARMD1_FEC_BASE		0xC0800000
+#define ARMD1_TIMER_BASE	0xD4014000
+#define ARMD1_APBC1_BASE	0xD4015000
+#define ARMD1_APBC2_BASE	0xD4015800
+#define ARMD1_UART1_BASE	0xD4017000
+#define ARMD1_UART2_BASE	0xD4018000
+#define ARMD1_GPIO_BASE		0xD4019000
+#define ARMD1_SSP1_BASE		0xD401B000
+#define ARMD1_SSP2_BASE		0xD401C000
+#define ARMD1_MFPR_BASE		0xD401E000
+#define ARMD1_SSP3_BASE		0xD401F000
+#define ARMD1_SSP4_BASE		0xD4020000
+#define ARMD1_SSP5_BASE		0xD4021000
+#define ARMD1_UART3_BASE	0xD4026000
+#define ARMD1_MPMU_BASE		0xD4050000
+#define ARMD1_USB_HOST_BASE	0xD4209000
+#define ARMD1_APMU_BASE		0xD4282800
+#define ARMD1_CPU_BASE		0xD4282C00
+
+#endif /* CONFIG_ARMADA100 */
+#endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
new file mode 100644
index 0000000..2862dd0
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/config.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for Armada100 platform
+ */
+
+#ifndef _ARMD1_CONFIG_H
+#define _ARMD1_CONFIG_H
+
+#include <asm/arch/armada100.h>
+
+#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
+#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
+#define MV_MFPR_BASE		ARMD1_MFPR_BASE
+#define MV_UART_CONSOLE_BASE	ARMD1_UART1_BASE
+#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
+						represents UART Unit Enable */
+
+#endif /* _ARMD1_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h
new file mode 100644
index 0000000..cd5e505
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/cpu.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#ifndef _ARMADA100CPU_H
+#define _ARMADA100CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Datasheet Appendix A.8
+ */
+struct armd1mpmu_registers {
+	u8 pad0[0x08 - 0x00];
+	u32 fccr;	/*0x0008*/
+	u32 pocr;	/*0x000c*/
+	u32 posr;	/*0x0010*/
+	u32 succr;	/*0x0014*/
+	u8 pad1[0x030 - 0x014 - 4];
+	u32 gpcr;	/*0x0030*/
+	u8 pad2[0x200 - 0x030 - 4];
+	u32 wdtpcr;	/*0x0200*/
+	u8 pad3[0x1000 - 0x200 - 4];
+	u32 apcr;	/*0x1000*/
+	u32 apsr;	/*0x1004*/
+	u8 pad4[0x1020 - 0x1004 - 4];
+	u32 aprr;	/*0x1020*/
+	u32 acgr;	/*0x1024*/
+	u32 arsr;	/*0x1028*/
+};
+
+/*
+ * Application Subsystem Power Management
+ * Refer Datasheet Appendix A.9
+ */
+struct armd1apmu_registers {
+	u32 pcr;		/* 0x000 */
+	u32 ccr;		/* 0x004 */
+	u32 pad1;
+	u32 ccsr;		/* 0x00C */
+	u32 fc_timer;		/* 0x010 */
+	u32 pad2;
+	u32 ideal_cfg;		/* 0x018 */
+	u8 pad3[0x04C - 0x018 - 4];
+	u32 lcdcrc;		/* 0x04C */
+	u32 cciccrc;		/* 0x050 */
+	u32 sd1crc;		/* 0x054 */
+	u32 sd2crc;		/* 0x058 */
+	u32 usbcrc;		/* 0x05C */
+	u32 nfccrc;		/* 0x060 */
+	u32 dmacrc;		/* 0x064 */
+	u32 pad4;
+	u32 buscrc;		/* 0x06C */
+	u8 pad5[0x07C - 0x06C - 4];
+	u32 wake_clr;		/* 0x07C */
+	u8 pad6[0x090 - 0x07C - 4];
+	u32 core_status;	/* 0x090 */
+	u32 rfsc;		/* 0x094 */
+	u32 imr;		/* 0x098 */
+	u32 irwc;		/* 0x09C */
+	u32 isr;		/* 0x0A0 */
+	u8 pad7[0x0B0 - 0x0A0 - 4];
+	u32 mhst;		/* 0x0B0 */
+	u32 msr;		/* 0x0B4 */
+	u8 pad8[0x0C0 - 0x0B4 - 4];
+	u32 msst;		/* 0x0C0 */
+	u32 pllss;		/* 0x0C4 */
+	u32 smb;		/* 0x0C8 */
+	u32 gccrc;		/* 0x0CC */
+	u8 pad9[0x0D4 - 0x0CC - 4];
+	u32 smccrc;		/* 0x0D4 */
+	u32 pad10;
+	u32 xdcrc;		/* 0x0DC */
+	u32 sd3crc;		/* 0x0E0 */
+	u32 sd4crc;		/* 0x0E4 */
+	u8 pad11[0x0F0 - 0x0E4 - 4];
+	u32 cfcrc;		/* 0x0F0 */
+	u32 mspcrc;		/* 0x0F4 */
+	u32 cmucrc;		/* 0x0F8 */
+	u32 fecrc;		/* 0x0FC */
+	u32 pciecrc;		/* 0x100 */
+	u32 epdcrc;		/* 0x104 */
+};
+
+/*
+ * APB1 Clock Reset/Control Registers
+ * Refer Datasheet Appendix A.10
+ */
+struct armd1apb1_registers {
+	u32 uart1;	/*0x000*/
+	u32 uart2;	/*0x004*/
+	u32 gpio;	/*0x008*/
+	u32 pwm1;	/*0x00c*/
+	u32 pwm2;	/*0x010*/
+	u32 pwm3;	/*0x014*/
+	u32 pwm4;	/*0x018*/
+	u8 pad0[0x028 - 0x018 - 4];
+	u32 rtc;	/*0x028*/
+	u32 twsi0;	/*0x02c*/
+	u32 kpc;	/*0x030*/
+	u32 timers;	/*0x034*/
+	u8 pad1[0x03c - 0x034 - 4];
+	u32 aib;	/*0x03c*/
+	u32 sw_jtag;	/*0x040*/
+	u32 timer1;	/*0x044*/
+	u32 onewire;	/*0x048*/
+	u8 pad2[0x050 - 0x048 - 4];
+	u32 asfar;	/*0x050 AIB Secure First Access Reg*/
+	u32 assar;	/*0x054 AIB Secure Second Access Reg*/
+	u8 pad3[0x06c - 0x054 - 4];
+	u32 twsi1;	/*0x06c*/
+	u32 uart3;	/*0x070*/
+	u8 pad4[0x07c - 0x070 - 4];
+	u32 timer2;	/*0x07C*/
+	u8 pad5[0x084 - 0x07c - 4];
+	u32 ac97;	/*0x084*/
+};
+
+/*
+* APB2 Clock Reset/Control Registers
+* Refer Datasheet Appendix A.11
+*/
+struct armd1apb2_registers {
+	u32 pad1[0x01C - 0x000];
+	u32 ssp1_clkrst;		/* 0x01C */
+	u32 ssp2_clkrst;		/* 0x020 */
+	u32 pad2[0x04C - 0x020 - 4];
+	u32 ssp3_clkrst;		/* 0x04C */
+	u32 pad3[0x058 - 0x04C - 4];
+	u32 ssp4_clkrst;		/* 0x058 */
+	u32 ssp5_clkrst;		/* 0x05C */
+};
+
+/*
+ * CPU Interface Registers
+ * Refer Datasheet Appendix A.2
+ */
+struct armd1cpu_registers {
+	u32 chip_id;		/* Chip Id Reg */
+	u32 pad;
+	u32 cpu_conf;		/* CPU Conf Reg */
+	u32 pad1;
+	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
+	u32 pad2;
+	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
+	u32 mcb_conf;		/* MCB Conf Reg */
+	u32 sys_boot_ctl;	/* Sytem Boot Control */
+};
+
+/*
+ * Functions
+ */
+u32 armd1_sdram_base(int);
+u32 armd1_sdram_size(int);
+
+#endif /* _ARMADA100CPU_H */
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h
new file mode 100644
index 0000000..b85f6a5
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/gpio.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include <asm/types.h>
+#include <asm/arch/armada100.h>
+
+#define GPIO_HIGH		1
+#define GPIO_LOW		0
+
+#define GPIO_TO_REG(gp)		(gp >> 5)
+#define GPIO_TO_BIT(gp)		(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val)	((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+	const unsigned int offset[4] = {0, 4, 8, 0x100};
+	/* gpio register bank offset - refer Appendix A.36 */
+	return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
new file mode 100644
index 0000000..a808ee8
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
+ * (C) Copyright 2007
+ * Marvell Semiconductor <www.marvell.com>
+ * 2007-08-21: eric miao <eric.miao@marvell.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#ifndef __ARMADA100_MFP_H
+#define __ARMADA100_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
+ *
+ * 				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+/* UART1 */
+#define MFP107_UART1_TXD	(MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
+#define MFP107_UART1_RXD	(MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
+#define MFP108_UART1_RXD	(MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
+#define MFP108_UART1_TXD	(MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
+#define MFP109_UART1_CTS	(MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP109_UART1_RTS	(MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP110_UART1_RTS	(MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP110_UART1_CTS	(MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP111_UART1_RI		(MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP111_UART1_DSR	(MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP112_UART1_DTR	(MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP112_UART1_DCD	(MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+
+/* UART2 */
+#define MFP47_UART2_RXD		(MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM)
+#define MFP48_UART2_TXD		(MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
+#define MFP88_UART2_RXD		(MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFP89_UART2_TXD		(MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+
+/* UART3 */
+#define MFPO8_UART3_TXD		(MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFPO9_UART3_RXD		(MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+
+/* I2c */
+#define MFP105_CI2C_SDA		(MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MFP106_CI2C_SCL		(MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+
+/* Fast Ethernet */
+#define MFP086_ETH_TXCLK	(MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP087_ETH_TXEN		(MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP088_ETH_TXDQ3	(MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP089_ETH_TXDQ2	(MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP090_ETH_TXDQ1	(MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP091_ETH_TXDQ0	(MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP092_ETH_CRS		(MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP093_ETH_COL		(MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP094_ETH_RXCLK	(MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP095_ETH_RXER		(MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP096_ETH_RXDQ3	(MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP097_ETH_RXDQ2	(MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP098_ETH_RXDQ1	(MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP099_ETH_RXDQ0	(MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP100_ETH_MDC		(MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP101_ETH_MDIO		(MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP103_ETH_RXDV		(MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+
+/* SPI */
+#define MFP107_SSP2_RXD		(MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
+#define MFP108_SSP2_TXD		(MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM)
+#define MFP110_SSP2_CS		(MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP111_SSP2_CLK		(MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
+
+/* More macros can be defined here... */
+
+#define MFP_PIN_MAX	117
+
+#endif /* __ARMADA100_MFP_H */
diff --git a/arch/arm/include/asm/arch-armada100/spi.h b/arch/arm/include/asm/arch-armada100/spi.h
new file mode 100644
index 0000000..873ba6e
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/spi.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#ifndef __ARMADA100_SPI_H_
+#define __ARMADA100_SPI_H_
+
+#include <asm/arch/armada100.h>
+
+#define CAT_BASE_ADDR(x)	ARMD1_SSP ## x ## _BASE
+#define SSP_REG_BASE(x)		CAT_BASE_ADDR(x)
+
+/*
+ * SSP Serial Port Registers
+ * refer Appendix A.26
+ */
+struct ssp_reg {
+	u32 sscr0;	/* SSP Control Register 0 - 0x000 */
+	u32 sscr1;	/* SSP Control Register 1 - 0x004 */
+	u32 sssr;	/* SSP Status Register - 0x008 */
+	u32 ssitr;	/* SSP Interrupt Test Register - 0x00C */
+	u32 ssdr;	/* SSP Data Register - 0x010 */
+	u32 pad1[5];
+	u32 ssto;	/* SSP Timeout Register - 0x028 */
+	u32 sspsp;	/* SSP Programmable Serial Protocol Register - 0x02C */
+	u32 sstsa;	/* SSP TX Timeslot Active Register - 0x030 */
+	u32 ssrsa;	/* SSP RX Timeslot Active Register - 0x034 */
+	u32 sstss;	/* SSP Timeslot Status Register - 0x038 */
+};
+
+#define DEFAULT_WORD_LEN	8
+#define SSP_FLUSH_NUM		0x2000
+#define RX_THRESH_DEF		8
+#define TX_THRESH_DEF		8
+#define TIMEOUT_DEF		1000
+
+#define SSCR1_RIE	(1 << 0)	/* Receive FIFO Interrupt Enable */
+#define SSCR1_TIE	(1 << 1)	/* Transmit FIFO Interrupt Enable */
+#define SSCR1_LBM	(1 << 2)	/* Loop-Back Mode */
+#define SSCR1_SPO	(1 << 3)	/* Motorola SPI SSPSCLK polarity
+					   setting */
+#define SSCR1_SPH	(1 << 4)	/* Motorola SPI SSPSCLK phase setting */
+#define SSCR1_MWDS	(1 << 5)	/* Microwire Transmit Data Size */
+#define SSCR1_TFT	0x03c0		/* Transmit FIFO Threshold (mask) */
+#define SSCR1_RFT	0x3c00		/* Receive FIFO Threshold (mask) */
+
+#define SSCR1_TXTRESH(x)	((x - 1) << 6)	/* level [1..16] */
+#define SSCR1_RXTRESH(x)	((x - 1) << 10)	/* level [1..16] */
+#define SSCR1_TINTE		(1 << 19)	/* Receiver Time-out
+						   Interrupt enable */
+
+#define SSCR0_DSS		0x0f		/* Data Size Select (mask) */
+#define SSCR0_DATASIZE(x)	(x - 1)		/* Data Size Select [4..16] */
+#define SSCR0_FRF		0x30		/* FRame Format (mask) */
+#define SSCR0_MOTO		(0x0 << 4)	/* Motorola's Serial
+						   Peripheral Interface */
+#define SSCR0_TI		(0x1 << 4)	/* TI's Synchronous
+						   Serial Protocol (SSP) */
+#define SSCR0_NATIONAL		(0x2 << 4)	/* National Microwire */
+#define SSCR0_ECS		(1 << 6)	/* External clock select */
+#define SSCR0_SSE		(1 << 7)	/* Synchronous Serial Port
+						   Enable */
+
+#define SSSR_TNF	(1 << 2)	/* Transmit FIFO Not Full */
+#define SSSR_RNE	(1 << 3)	/* Receive FIFO Not Empty */
+#define SSSR_BSY	(1 << 4)	/* SSP Busy */
+#define SSSR_TFS	(1 << 5)	/* Transmit FIFO Service Request */
+#define SSSR_RFS	(1 << 6)	/* Receive FIFO Service Request */
+#define SSSR_ROR	(1 << 7)	/* Receive FIFO Overrun */
+#define SSSR_TINT	(1 << 19)	/* Receiver Time-out Interrupt */
+
+#endif /* __ARMADA100_SPI_H_ */
diff --git a/arch/arm/include/asm/arch-armada100/utmi-armada100.h b/arch/arm/include/asm/arch-armada100/utmi-armada100.h
new file mode 100644
index 0000000..28147f4
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/utmi-armada100.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#ifndef __UTMI_ARMADA100__
+#define __UTMI_ARMADA100__
+
+#define UTMI_PHY_BASE		0xD4206000
+
+/* utmi_ctrl - bits */
+#define INPKT_DELAY_SOF		(1 << 28)
+#define PLL_PWR_UP		2
+#define PHY_PWR_UP		1
+
+/* utmi_pll - bits */
+#define PLL_FBDIV_MASK		0x00000FF0
+#define PLL_FBDIV		4
+#define PLL_REFDIV_MASK		0x0000000F
+#define PLL_REFDIV		0
+#define PLL_READY		0x800000
+#define VCOCAL_START		(1 << 21)
+
+#define N_DIVIDER		0xEE
+#define M_DIVIDER		0x0B
+
+/* utmi_tx - bits */
+#define CK60_PHSEL		17
+#define PHSEL_VAL		0x4
+#define RCAL_START		(1 << 12)
+
+/*
+ * USB PHY registers
+ * Refer Datasheet Appendix A.21
+ */
+struct armd1usb_phy_reg {
+	u32 utmi_rev;	/* USB PHY Revision */
+	u32 utmi_ctrl;	/* USB PHY Control register */
+	u32 utmi_pll;	/* PLL register */
+	u32 utmi_tx;	/* Tx register */
+	u32 utmi_rx;	/* Rx register */
+	u32 utmi_ivref;	/* IVREF register */
+	u32 utmi_tst_g0;	/* Test group 0 register */
+	u32 utmi_tst_g1;	/* Test group 1 register */
+	u32 utmi_tst_g2;	/* Test group 2 register */
+	u32 utmi_tst_g3;	/* Test group 3 register */
+	u32 utmi_tst_g4;	/* Test group 4 register */
+	u32 utmi_tst_g5;	/* Test group 5 register */
+	u32 utmi_reserve;	/* Reserve Register */
+	u32 utmi_usb_int;	/* USB interuppt register */
+	u32 utmi_dbg_ctl;	/* Debug control register */
+	u32 utmi_otg_addon;	/* OTG addon register */
+};
+
+int utmi_init(void);
+
+#endif /* __UTMI_ARMADA100__ */
diff --git a/arch/arm/include/asm/arch-armada8k/cache_llc.h b/arch/arm/include/asm/arch-armada8k/cache_llc.h
new file mode 100644
index 0000000..8cb1144
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada8k/cache_llc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ * https://spdx.org/licenses
+ */
+
+#ifndef _CACHE_LLC_H_
+#define _CACHE_LLC_H_
+
+/* Armada-7K/8K last level cache */
+
+#define MVEBU_A8K_REGS_BASE_MSB		0xf000
+#define LLC_BASE_ADDR			0x8000
+#define LLC_CACHE_SYNC			0x700
+#define LLC_CACHE_SYNC_COMPLETE		0x730
+#define LLC_FLUSH_BY_WAY		0x7fc
+#define LLC_WAY_MASK			0xffffffff
+#define LLC_CACHE_SYNC_MASK		0x1
+
+#endif	/* _CACHE_LLC_H_ */
diff --git a/arch/arm/include/asm/arch-armada8k/soc-info.h b/arch/arm/include/asm/arch-armada8k/soc-info.h
new file mode 100644
index 0000000..64606ef
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada8k/soc-info.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Marvell International Ltd.
+ * https://spdx.org/licenses
+ */
+
+#ifndef _SOC_INFO_H_
+#define _SOC_INFO_H_
+
+/* Pin Ctrl driver definitions */
+#define BITS_PER_PIN		4
+#define PIN_FUNC_MASK		((1 << BITS_PER_PIN) - 1)
+#define PIN_REG_SHIFT		3
+#define PIN_FIELD_MASK		((1 << PIN_REG_SHIFT) - 1)
+
+#endif	/* _SOC_INFO_H_ */
diff --git a/arch/arm/include/asm/arch-armv7/generictimer.h b/arch/arm/include/asm/arch-armv7/generictimer.h
new file mode 100644
index 0000000..f402686
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv7/generictimer.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Based on code by Carl van Schaik <carl@ok-labs.com>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _GENERICTIMER_H_
+#define _GENERICTIMER_H_
+
+#ifdef __ASSEMBLY__
+
+/*
+ * This macro provide a physical timer that can be used for delay in the code.
+ * The macro is moved from sunxi/psci_sun7i.S
+ *
+ * reg: is used in this macro.
+ * ticks: The freq is based on generic timer.
+ */
+.macro	timer_wait	reg, ticks
+	movw	\reg, #(\ticks & 0xffff)
+	movt	\reg, #(\ticks >> 16)
+	mcr	p15, 0, \reg, c14, c2, 0
+	isb
+	mov	\reg, #3
+	mcr	p15, 0, \reg, c14, c2, 1
+1 :	isb
+	mrc	p15, 0, \reg, c14, c2, 1
+	ands	\reg, \reg, #4
+	bne	1b
+	mov	\reg, #0
+	mcr	p15, 0, \reg, c14, c2, 1
+	isb
+.endm
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _GENERICTIMER_H_ */
diff --git a/arch/arm/include/asm/arch-armv7/globaltimer.h b/arch/arm/include/asm/arch-armv7/globaltimer.h
new file mode 100644
index 0000000..2d9cf77
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv7/globaltimer.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ */
+#ifndef _GLOBALTIMER_H_
+#define _GLOBALTIMER_H_
+
+struct globaltimer {
+	u32 cnt_l; /* 0x00 */
+	u32 cnt_h;
+	u32 ctl;
+	u32 stat;
+	u32 cmp_l; /* 0x10 */
+	u32 cmp_h;
+	u32 inc;
+};
+
+#endif /* _GLOBALTIMER_H_ */
diff --git a/arch/arm/include/asm/arch-armv7/sysctrl.h b/arch/arm/include/asm/arch-armv7/sysctrl.h
new file mode 100644
index 0000000..fc72fac
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv7/sysctrl.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ */
+#ifndef _SYSCTRL_H_
+#define _SYSCTRL_H_
+
+/* System controller (SP810) register definitions */
+#define SP810_TIMER0_ENSEL	(1 << 15)
+#define SP810_TIMER1_ENSEL	(1 << 17)
+#define SP810_TIMER2_ENSEL	(1 << 19)
+#define SP810_TIMER3_ENSEL	(1 << 21)
+
+struct sysctrl {
+	u32 scctrl;		/* 0x000 */
+	u32 scsysstat;
+	u32 scimctrl;
+	u32 scimstat;
+	u32 scxtalctrl;
+	u32 scpllctrl;
+	u32 scpllfctrl;
+	u32 scperctrl0;
+	u32 scperctrl1;
+	u32 scperen;
+	u32 scperdis;
+	u32 scperclken;
+	u32 scperstat;
+	u32 res1[0x006];
+	u32 scflashctrl;	/* 0x04c */
+	u32 res2[0x3a4];
+	u32 scsysid0;		/* 0xee0 */
+	u32 scsysid1;
+	u32 scsysid2;
+	u32 scsysid3;
+	u32 scitcr;
+	u32 scitir0;
+	u32 scitir1;
+	u32 scitor;
+	u32 sccntctrl;
+	u32 sccntdata;
+	u32 sccntstep;
+	u32 res3[0x32];
+	u32 scperiphid0;	/* 0xfe0 */
+	u32 scperiphid1;
+	u32 scperiphid2;
+	u32 scperiphid3;
+	u32 scpcellid0;
+	u32 scpcellid1;
+	u32 scpcellid2;
+	u32 scpcellid3;
+};
+#endif /* _SYSCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-armv7/systimer.h b/arch/arm/include/asm/arch-armv7/systimer.h
new file mode 100644
index 0000000..04c4130
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv7/systimer.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ */
+#ifndef _SYSTIMER_H_
+#define _SYSTIMER_H_
+
+/* AMBA timer register base address */
+#define SYSTIMER_BASE		0x10011000
+
+#define SYSHZ_CLOCK		1000000		/* Timers -> 1Mhz */
+#define SYSTIMER_RELOAD		0xFFFFFFFF
+#define SYSTIMER_EN		(1 << 7)
+#define SYSTIMER_32BIT		(1 << 1)
+#define SYSTIMER_PRESC_16	(1 << 2)
+#define SYSTIMER_PRESC_256	(1 << 3)
+
+struct systimer {
+	u32 timer0load;		/* 0x00 */
+	u32 timer0value;
+	u32 timer0control;
+	u32 timer0intclr;
+	u32 timer0ris;
+	u32 timer0mis;
+	u32 timer0bgload;
+	u32 timer1load;		/* 0x20 */
+	u32 timer1value;
+	u32 timer1control;
+	u32 timer1intclr;
+	u32 timer1ris;
+	u32 timer1mis;
+	u32 timer1bgload;
+};
+#endif /* _SYSTIMER_H_ */
diff --git a/arch/arm/include/asm/arch-armv7/wdt.h b/arch/arm/include/asm/arch-armv7/wdt.h
new file mode 100644
index 0000000..e3fa16f
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv7/wdt.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Matt Waddel, <matt.waddel@linaro.org>
+ */
+#ifndef _WDT_H_
+#define _WDT_H_
+
+/* Watchdog timer (SP805) register base address */
+#define WDT_BASE	0x100E5000
+
+#define WDT_EN		0x2
+#define WDT_RESET_LOAD	0x0
+
+struct wdt {
+	u32 wdogload;		/* 0x000 */
+	u32 wdogvalue;
+	u32 wdogcontrol;
+	u32 wdogintclr;
+	u32 wdogris;
+	u32 wdogmis;
+	u32 res1[0x2F9];
+	u32 wdoglock;		/* 0xC00 */
+	u32 res2[0xBE];
+	u32 wdogitcr;		/* 0xF00 */
+	u32 wdogitop;
+	u32 res3[0x35];
+	u32 wdogperiphid0;	/* 0xFE0 */
+	u32 wdogperiphid1;
+	u32 wdogperiphid2;
+	u32 wdogperiphid3;
+	u32 wdogpcellid0;
+	u32 wdogpcellid1;
+	u32 wdogpcellid2;
+	u32 wdogpcellid3;
+};
+
+#endif /* _WDT_H_ */
diff --git a/arch/arm/include/asm/arch-aspeed/pinctrl.h b/arch/arm/include/asm/arch-aspeed/pinctrl.h
new file mode 100644
index 0000000..dd85464
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/pinctrl.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Google, Inc
+ */
+#ifndef _ASM_ARCH_PERIPH_H
+#define _ASM_ARCH_PERIPH_H
+
+/*
+ * Peripherals supported by the hardware.
+ * These are used to specify pinctrl settings.
+ */
+
+enum periph_id {
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+	PERIPH_ID_UART3,
+	PERIPH_ID_UART4,
+	PERIPH_ID_LPC,
+	PERIPH_ID_PWM0,
+	PERIPH_ID_PWM1,
+	PERIPH_ID_PWM2,
+	PERIPH_ID_PWM3,
+	PERIPH_ID_PWM4,
+	PERIPH_ID_PWM5,
+	PERIPH_ID_PWM6,
+	PERIPH_ID_PWM7,
+	PERIPH_ID_PWM8,
+	PERIPH_ID_MAC1,
+	PERIPH_ID_MAC2,
+	PERIPH_ID_VIDEO,
+	PERIPH_ID_SPI1,
+	PERIPH_ID_SPI2,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_I2C4,
+	PERIPH_ID_I2C5,
+	PERIPH_ID_I2C6,
+	PERIPH_ID_I2C7,
+	PERIPH_ID_I2C8,
+	PERIPH_ID_I2C9,
+	PERIPH_ID_I2C10,
+	PERIPH_ID_I2C11,
+	PERIPH_ID_I2C12,
+	PERIPH_ID_I2C13,
+	PERIPH_ID_I2C14,
+	PERIPH_ID_SD1,
+	PERIPH_ID_SD2,
+};
+
+#endif  /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
new file mode 100644
index 0000000..8db4901
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+#ifndef _ASM_ARCH_SCU_AST2500_H
+#define _ASM_ARCH_SCU_AST2500_H
+
+#define SCU_UNLOCK_VALUE		0x1688a8a8
+
+#define SCU_HWSTRAP_VGAMEM_SHIFT	2
+#define SCU_HWSTRAP_VGAMEM_MASK		(3 << SCU_HWSTRAP_VGAMEM_SHIFT)
+#define SCU_HWSTRAP_MAC1_RGMII		(1 << 6)
+#define SCU_HWSTRAP_MAC2_RGMII		(1 << 7)
+#define SCU_HWSTRAP_DDR4		(1 << 24)
+#define SCU_HWSTRAP_CLKIN_25MHZ		(1 << 23)
+
+#define SCU_MPLL_DENUM_SHIFT		0
+#define SCU_MPLL_DENUM_MASK		0x1f
+#define SCU_MPLL_NUM_SHIFT		5
+#define SCU_MPLL_NUM_MASK		(0xff << SCU_MPLL_NUM_SHIFT)
+#define SCU_MPLL_POST_SHIFT		13
+#define SCU_MPLL_POST_MASK		(0x3f << SCU_MPLL_POST_SHIFT)
+#define SCU_PCLK_DIV_SHIFT		23
+#define SCU_PCLK_DIV_MASK		(7 << SCU_PCLK_DIV_SHIFT)
+#define SCU_SDCLK_DIV_SHIFT		12
+#define SCU_SDCLK_DIV_MASK		(7 << SCU_SDCLK_DIV_SHIFT)
+#define SCU_HPLL_DENUM_SHIFT		0
+#define SCU_HPLL_DENUM_MASK		0x1f
+#define SCU_HPLL_NUM_SHIFT		5
+#define SCU_HPLL_NUM_MASK		(0xff << SCU_HPLL_NUM_SHIFT)
+#define SCU_HPLL_POST_SHIFT		13
+#define SCU_HPLL_POST_MASK		(0x3f << SCU_HPLL_POST_SHIFT)
+
+#define SCU_MACCLK_SHIFT		16
+#define SCU_MACCLK_MASK			(7 << SCU_MACCLK_SHIFT)
+
+#define SCU_MISC2_RGMII_HPLL		(1 << 23)
+#define SCU_MISC2_RGMII_CLKDIV_SHIFT	20
+#define SCU_MISC2_RGMII_CLKDIV_MASK	(3 << SCU_MISC2_RGMII_CLKDIV_SHIFT)
+#define SCU_MISC2_RMII_MPLL		(1 << 19)
+#define SCU_MISC2_RMII_CLKDIV_SHIFT	16
+#define SCU_MISC2_RMII_CLKDIV_MASK	(3 << SCU_MISC2_RMII_CLKDIV_SHIFT)
+#define SCU_MISC2_UARTCLK_SHIFT		24
+
+#define SCU_MISC_D2PLL_OFF		(1 << 4)
+#define SCU_MISC_UARTCLK_DIV13		(1 << 12)
+#define SCU_MISC_GCRT_USB20CLK		(1 << 21)
+
+#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT	0
+#define SCU_MICDS_MAC1RGMII_TXDLY_MASK	(0x3f\
+					 << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT	6
+#define SCU_MICDS_MAC2RGMII_TXDLY_MASK	(0x3f\
+					 << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_RDLY_SHIFT	12
+#define SCU_MICDS_MAC1RMII_RDLY_MASK	(0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC2RMII_RDLY_SHIFT	18
+#define SCU_MICDS_MAC2RMII_RDLY_MASK	(0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_TXFALL	(1 << 24)
+#define SCU_MICDS_MAC2RMII_TXFALL	(1 << 25)
+#define SCU_MICDS_RMII1_RCLKEN		(1 << 29)
+#define SCU_MICDS_RMII2_RCLKEN		(1 << 30)
+#define SCU_MICDS_RGMIIPLL		(1 << 31)
+
+/*
+ * SYSRESET is actually more like a Power register,
+ * except that corresponding bit set to 1 means that
+ * the peripheral is off.
+ */
+#define SCU_SYSRESET_XDMA		(1 << 25)
+#define SCU_SYSRESET_MCTP		(1 << 24)
+#define SCU_SYSRESET_ADC		(1 << 23)
+#define SCU_SYSRESET_JTAG		(1 << 22)
+#define SCU_SYSRESET_MIC		(1 << 18)
+#define SCU_SYSRESET_SDIO		(1 << 16)
+#define SCU_SYSRESET_USB11HOST		(1 << 15)
+#define SCU_SYSRESET_USBHUB		(1 << 14)
+#define SCU_SYSRESET_CRT		(1 << 13)
+#define SCU_SYSRESET_MAC2		(1 << 12)
+#define SCU_SYSRESET_MAC1		(1 << 11)
+#define SCU_SYSRESET_PECI		(1 << 10)
+#define SCU_SYSRESET_PWM		(1 << 9)
+#define SCU_SYSRESET_PCI_VGA		(1 << 8)
+#define SCU_SYSRESET_2D			(1 << 7)
+#define SCU_SYSRESET_VIDEO		(1 << 6)
+#define SCU_SYSRESET_LPC		(1 << 5)
+#define SCU_SYSRESET_HAC		(1 << 4)
+#define SCU_SYSRESET_USBHID		(1 << 3)
+#define SCU_SYSRESET_I2C		(1 << 2)
+#define SCU_SYSRESET_AHB		(1 << 1)
+#define SCU_SYSRESET_SDRAM_WDT		(1 << 0)
+
+/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
+#define SCU_PINMUX_CTRL5_I2C		(1 << 16)
+
+/*
+ * The values are grouped by function, not by register.
+ * They are actually scattered across multiple loosely related registers.
+ */
+#define SCU_PIN_FUN_MAC1_MDC		(1 << 30)
+#define SCU_PIN_FUN_MAC1_MDIO		(1 << 31)
+#define SCU_PIN_FUN_MAC1_PHY_LINK	(1 << 0)
+#define SCU_PIN_FUN_MAC2_MDIO		(1 << 2)
+#define SCU_PIN_FUN_MAC2_PHY_LINK	(1 << 1)
+#define SCU_PIN_FUN_SCL1		(1 << 12)
+#define SCU_PIN_FUN_SCL2		(1 << 14)
+#define SCU_PIN_FUN_SDA1		(1 << 13)
+#define SCU_PIN_FUN_SDA2		(1 << 15)
+
+#define SCU_CLKSTOP_MAC1		(1 << 20)
+#define SCU_CLKSTOP_MAC2		(1 << 21)
+#define SCU_CLKSTOP_SDCLK		(1 << 27)
+
+#define SCU_D2PLL_EXT1_OFF		(1 << 0)
+#define SCU_D2PLL_EXT1_BYPASS		(1 << 1)
+#define SCU_D2PLL_EXT1_RESET		(1 << 2)
+#define SCU_D2PLL_EXT1_MODE_SHIFT	3
+#define SCU_D2PLL_EXT1_MODE_MASK	(3 << SCU_D2PLL_EXT1_MODE_SHIFT)
+#define SCU_D2PLL_EXT1_PARAM_SHIFT	5
+#define SCU_D2PLL_EXT1_PARAM_MASK	(0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT)
+
+#define SCU_D2PLL_NUM_SHIFT		0
+#define SCU_D2PLL_NUM_MASK		(0xff << SCU_D2PLL_NUM_SHIFT)
+#define SCU_D2PLL_DENUM_SHIFT		8
+#define SCU_D2PLL_DENUM_MASK		(0x1f << SCU_D2PLL_DENUM_SHIFT)
+#define SCU_D2PLL_POST_SHIFT		13
+#define SCU_D2PLL_POST_MASK		(0x3f << SCU_D2PLL_POST_SHIFT)
+#define SCU_D2PLL_ODIV_SHIFT		19
+#define SCU_D2PLL_ODIV_MASK		(7 << SCU_D2PLL_ODIV_SHIFT)
+#define SCU_D2PLL_SIC_SHIFT		22
+#define SCU_D2PLL_SIC_MASK		(0x1f << SCU_D2PLL_SIC_SHIFT)
+#define SCU_D2PLL_SIP_SHIFT		27
+#define SCU_D2PLL_SIP_MASK		(0x1f << SCU_D2PLL_SIP_SHIFT)
+
+#define SCU_CLKDUTY_DCLK_SHIFT		0
+#define SCU_CLKDUTY_DCLK_MASK		(0x3f << SCU_CLKDUTY_DCLK_SHIFT)
+#define SCU_CLKDUTY_RGMII1TXCK_SHIFT	8
+#define SCU_CLKDUTY_RGMII1TXCK_MASK	(0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT)
+#define SCU_CLKDUTY_RGMII2TXCK_SHIFT	16
+#define SCU_CLKDUTY_RGMII2TXCK_MASK	(0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
+
+#ifndef __ASSEMBLY__
+
+struct ast2500_clk_priv {
+	struct ast2500_scu *scu;
+};
+
+struct ast2500_scu {
+	u32 protection_key;
+	u32 sysreset_ctrl1;
+	u32 clk_sel1;
+	u32 clk_stop_ctrl1;
+	u32 freq_counter_ctrl;
+	u32 freq_counter_cmp;
+	u32 intr_ctrl;
+	u32 d2_pll_param;
+	u32 m_pll_param;
+	u32 h_pll_param;
+	u32 d_pll_param;
+	u32 misc_ctrl1;
+	u32 pci_config[3];
+	u32 sysreset_status;
+	u32 vga_handshake[2];
+	u32 mac_clk_delay;
+	u32 misc_ctrl2;
+	u32 vga_scratch[8];
+	u32 hwstrap;
+	u32 rng_ctrl;
+	u32 rng_data;
+	u32 rev_id;
+	u32 pinmux_ctrl[6];
+	u32 reserved0;
+	u32 extrst_sel;
+	u32 pinmux_ctrl1[4];
+	u32 reserved1[2];
+	u32 mac_clk_delay_100M;
+	u32 mac_clk_delay_10M;
+	u32 wakeup_enable;
+	u32 wakeup_control;
+	u32 reserved2[3];
+	u32 sysreset_ctrl2;
+	u32 clk_sel2;
+	u32 clk_stop_ctrl2;
+	u32 freerun_counter;
+	u32 freerun_counter_ext;
+	u32 clk_duty_meas_ctrl;
+	u32 clk_duty_meas_res;
+	u32 reserved3[4];
+	/* The next registers are not key-protected */
+	struct ast2500_cpu2 {
+		u32 ctrl;
+		u32 base_addr[9];
+		u32 cache_ctrl;
+	} cpu2;
+	u32 reserved4;
+	u32 d_pll_ext_param[3];
+	u32 d2_pll_ext_param[3];
+	u32 mh_pll_ext_param;
+	u32 reserved5;
+	u32 chip_id[2];
+	u32 reserved6[2];
+	u32 uart_clk_ctrl;
+	u32 reserved7[7];
+	u32 pcie_config;
+	u32 mmio_decode;
+	u32 reloc_ctrl_decode[2];
+	u32 mailbox_addr;
+	u32 shared_sram_decode[2];
+	u32 bmc_rev_id;
+	u32 reserved8;
+	u32 bmc_device_id;
+	u32 reserved9[13];
+	u32 clk_duty_sel;
+};
+
+/**
+ * ast_get_clk() - get a pointer to Clock Driver
+ *
+ * @devp, OUT - pointer to Clock Driver
+ * @return zero on success, error code (< 0) otherwise.
+ */
+int ast_get_clk(struct udevice **devp);
+
+/**
+ * ast_get_scu() - get a pointer to SCU registers
+ *
+ * @return pointer to struct ast2500_scu on success, ERR_PTR otherwise
+ */
+void *ast_get_scu(void);
+
+/**
+ * ast_scu_unlock() - unlock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_unlock(struct ast2500_scu *scu);
+
+/**
+ * ast_scu_lock() - lock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_lock(struct ast2500_scu *scu);
+
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h b/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h
new file mode 100644
index 0000000..0bc551f
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/sdram_ast2500.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+#ifndef _ASM_ARCH_SDRAM_AST2500_H
+#define _ASM_ARCH_SDRAM_AST2500_H
+
+#define SDRAM_UNLOCK_KEY		0xfc600309
+#define SDRAM_VIDEO_UNLOCK_KEY		0x2003000f
+
+#define SDRAM_PCR_CKE_EN		(1 << 0)
+#define SDRAM_PCR_AUTOPWRDN_EN		(1 << 1)
+#define SDRAM_PCR_CKE_DELAY_SHIFT	4
+#define SDRAM_PCR_CKE_DELAY_MASK	7
+#define SDRAM_PCR_RESETN_DIS		(1 << 7)
+#define SDRAM_PCR_ODT_EN		(1 << 8)
+#define SDRAM_PCR_ODT_AUTO_ON		(1 << 10)
+#define SDRAM_PCR_ODT_EXT_EN		(1 << 11)
+#define SDRAM_PCR_TCKE_PW_SHIFT		12
+#define SDRAM_PCR_TCKE_PW_MASK		7
+#define SDRAM_PCR_RGAP_CTRL_EN		(1 << 15)
+#define SDRAM_PCR_MREQI_DIS		(1 << 17)
+
+/* Fixed priority DRAM Requests mask */
+#define SDRAM_REQ_VGA_HW_CURSOR		(1 << 0)
+#define SDRAM_REQ_VGA_TEXT_CG_FONT	(1 << 1)
+#define SDRAM_REQ_VGA_TEXT_ASCII	(1 << 2)
+#define SDRAM_REQ_VGA_CRT		(1 << 3)
+#define SDRAM_REQ_SOC_DC_CURSOR		(1 << 4)
+#define SDRAM_REQ_SOC_DC_OCD		(1 << 5)
+#define SDRAM_REQ_SOC_DC_CRT		(1 << 6)
+#define SDRAM_REQ_VIDEO_HIPRI_WRITE	(1 << 7)
+#define SDRAM_REQ_USB20_EHCI1		(1 << 8)
+#define SDRAM_REQ_USB20_EHCI2		(1 << 9)
+#define SDRAM_REQ_CPU			(1 << 10)
+#define SDRAM_REQ_AHB2			(1 << 11)
+#define SDRAM_REQ_AHB			(1 << 12)
+#define SDRAM_REQ_MAC0			(1 << 13)
+#define SDRAM_REQ_MAC1			(1 << 14)
+#define SDRAM_REQ_PCIE			(1 << 16)
+#define SDRAM_REQ_XDMA			(1 << 17)
+#define SDRAM_REQ_ENCRYPTION		(1 << 18)
+#define SDRAM_REQ_VIDEO_FLAG		(1 << 21)
+#define SDRAM_REQ_VIDEO_LOW_PRI_WRITE	(1 << 28)
+#define SDRAM_REQ_2D_RW			(1 << 29)
+#define SDRAM_REQ_MEMCHECK		(1 << 30)
+
+#define SDRAM_ICR_RESET_ALL		(1 << 31)
+
+#define SDRAM_CONF_CAP_SHIFT		0
+#define SDRAM_CONF_CAP_MASK		3
+#define SDRAM_CONF_DDR4			(1 << 4)
+#define SDRAM_CONF_SCRAMBLE		(1 << 8)
+#define SDRAM_CONF_SCRAMBLE_PAT2	(1 << 9)
+#define SDRAM_CONF_CACHE_EN		(1 << 10)
+#define SDRAM_CONF_CACHE_INIT_EN	(1 << 12)
+#define SDRAM_CONF_DUALX8		(1 << 13)
+#define SDRAM_CONF_CACHE_INIT_DONE	(1 << 19)
+
+#define SDRAM_CONF_CAP_128M		0
+#define SDRAM_CONF_CAP_256M		1
+#define SDRAM_CONF_CAP_512M		2
+#define SDRAM_CONF_CAP_1024M		3
+
+#define SDRAM_MISC_DDR4_TREFRESH	(1 << 3)
+
+#define SDRAM_PHYCTRL0_INIT		(1 << 0)
+#define SDRAM_PHYCTRL0_AUTO_UPDATE	(1 << 1)
+#define SDRAM_PHYCTRL0_NRST		(1 << 2)
+
+#define SDRAM_REFRESH_CYCLES_SHIFT	0
+#define SDRAM_REFRESH_CYCLES_MASK	0xf
+#define SDRAM_REFRESH_ZQCS_EN		(1 << 7)
+#define SDRAM_REFRESH_PERIOD_SHIFT	8
+#define SDRAM_REFRESH_PERIOD_MASK	0xf
+
+#define SDRAM_TEST_LEN_SHIFT		4
+#define SDRAM_TEST_LEN_MASK		0xfffff
+#define SDRAM_TEST_START_ADDR_SHIFT	24
+#define SDRAM_TEST_START_ADDR_MASK	0x3f
+
+#define SDRAM_TEST_EN			(1 << 0)
+#define SDRAM_TEST_MODE_SHIFT		1
+#define SDRAM_TEST_MODE_MASK		3
+#define SDRAM_TEST_MODE_WO		0
+#define SDRAM_TEST_MODE_RB		1
+#define SDRAM_TEST_MODE_RW		2
+#define SDRAM_TEST_GEN_MODE_SHIFT	3
+#define SDRAM_TEST_GEN_MODE_MASK	7
+#define SDRAM_TEST_TWO_MODES		(1 << 6)
+#define SDRAM_TEST_ERRSTOP		(1 << 7)
+#define SDRAM_TEST_DONE			(1 << 12)
+#define SDRAM_TEST_FAIL			(1 << 13)
+
+#define SDRAM_AC_TRFC_SHIFT		0
+#define SDRAM_AC_TRFC_MASK		0xff
+
+#ifndef __ASSEMBLY__
+
+struct ast2500_sdrammc_regs {
+	u32 protection_key;
+	u32 config;
+	u32 gm_protection_key;
+	u32 refresh_timing;
+	u32 ac_timing[3];
+	u32 misc_control;
+	u32 mr46_mode_setting;
+	u32 mr5_mode_setting;
+	u32 mode_setting_control;
+	u32 mr02_mode_setting;
+	u32 mr13_mode_setting;
+	u32 power_control;
+	u32 req_limit_mask;
+	u32 pri_group_setting;
+	u32 max_grant_len[4];
+	u32 intr_ctrl;
+	u32 ecc_range_ctrl;
+	u32 first_ecc_err_addr;
+	u32 last_ecc_err_addr;
+	u32 phy_ctrl[4];
+	u32 ecc_test_ctrl;
+	u32 test_addr;
+	u32 test_fail_dq_bit;
+	u32 test_init_val;
+	u32 phy_debug_ctrl;
+	u32 phy_debug_data;
+	u32 reserved1[30];
+	u32 scu_passwd;
+	u32 reserved2[7];
+	u32 scu_mpll;
+	u32 reserved3[19];
+	u32 scu_hwstrap;
+};
+
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* _ASM_ARCH_SDRAM_AST2500_H */
diff --git a/arch/arm/include/asm/arch-aspeed/timer.h b/arch/arm/include/asm/arch-aspeed/timer.h
new file mode 100644
index 0000000..ff24e2f
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/timer.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+#ifndef _ASM_ARCH_TIMER_H
+#define _ASM_ARCH_TIMER_H
+
+/* Each timer has 4 control bits in ctrl1 register.
+ * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on,
+ * such that timer X uses bits (4 * X - 4):(4 * X - 1)
+ * If the timer does not support PWM, bit 4 is reserved.
+ */
+#define AST_TMC_EN			(1 << 0)
+#define AST_TMC_1MHZ			(1 << 1)
+#define AST_TMC_OVFINTR			(1 << 2)
+#define AST_TMC_PWM			(1 << 3)
+
+/* Timers are counted from 1 in the datasheet. */
+#define AST_TMC_CTRL1_SHIFT(n)			(4 * ((n) - 1))
+
+#define AST_TMC_RATE  (1000*1000)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * All timers share control registers, which makes it harder to make them
+ * separate devices. Since only one timer is needed at the moment, making
+ * it this just one device.
+ */
+
+struct ast_timer_counter {
+	u32 status;
+	u32 reload_val;
+	u32 match1;
+	u32 match2;
+};
+
+struct ast_timer {
+	struct ast_timer_counter timers1[3];
+	u32 ctrl1;
+	u32 ctrl2;
+#ifdef CONFIG_ASPEED_AST2500
+	u32 ctrl3;
+	u32 ctrl1_clr;
+#else
+	u32 reserved[2];
+#endif
+	struct ast_timer_counter timers2[5];
+};
+
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* _ASM_ARCH_TIMER_H */
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h b/arch/arm/include/asm/arch-aspeed/wdt.h
new file mode 100644
index 0000000..fb04d41
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_WDT_H
+#define _ASM_ARCH_WDT_H
+
+#define WDT_BASE			0x1e785000
+
+/*
+ * Special value that needs to be written to counter_restart register to
+ * (re)start the timer
+ */
+#define WDT_COUNTER_RESTART_VAL		0x4755
+
+/* Control register */
+#define WDT_CTRL_RESET_MODE_SHIFT	5
+#define WDT_CTRL_RESET_MODE_MASK	3
+
+#define WDT_CTRL_EN			(1 << 0)
+#define WDT_CTRL_RESET			(1 << 1)
+#define WDT_CTRL_CLK1MHZ		(1 << 4)
+#define WDT_CTRL_2ND_BOOT		(1 << 7)
+
+/* Values for Reset Mode */
+#define WDT_CTRL_RESET_SOC		0
+#define WDT_CTRL_RESET_CHIP		1
+#define WDT_CTRL_RESET_CPU		2
+#define WDT_CTRL_RESET_MASK		3
+
+/* Reset Mask register */
+#define WDT_RESET_ARM			(1 << 0)
+#define WDT_RESET_COPROC		(1 << 1)
+#define WDT_RESET_SDRAM			(1 << 2)
+#define WDT_RESET_AHB			(1 << 3)
+#define WDT_RESET_I2C			(1 << 4)
+#define WDT_RESET_MAC1			(1 << 5)
+#define WDT_RESET_MAC2			(1 << 6)
+#define WDT_RESET_GCRT			(1 << 7)
+#define WDT_RESET_USB20			(1 << 8)
+#define WDT_RESET_USB11_HOST		(1 << 9)
+#define WDT_RESET_USB11_EHCI2		(1 << 10)
+#define WDT_RESET_VIDEO			(1 << 11)
+#define WDT_RESET_HAC			(1 << 12)
+#define WDT_RESET_LPC			(1 << 13)
+#define WDT_RESET_SDSDIO		(1 << 14)
+#define WDT_RESET_MIC			(1 << 15)
+#define WDT_RESET_CRT2C			(1 << 16)
+#define WDT_RESET_PWM			(1 << 17)
+#define WDT_RESET_PECI			(1 << 18)
+#define WDT_RESET_JTAG			(1 << 19)
+#define WDT_RESET_ADC			(1 << 20)
+#define WDT_RESET_GPIO			(1 << 21)
+#define WDT_RESET_MCTP			(1 << 22)
+#define WDT_RESET_XDMA			(1 << 23)
+#define WDT_RESET_SPI			(1 << 24)
+#define WDT_RESET_MISC			(1 << 25)
+
+#define WDT_RESET_DEFAULT						\
+	(WDT_RESET_ARM | WDT_RESET_COPROC | WDT_RESET_I2C |		\
+	 WDT_RESET_MAC1 | WDT_RESET_MAC2 | WDT_RESET_GCRT |		\
+	 WDT_RESET_USB20 | WDT_RESET_USB11_HOST | WDT_RESET_USB11_EHCI2 | \
+	 WDT_RESET_VIDEO | WDT_RESET_HAC | WDT_RESET_LPC |		\
+	 WDT_RESET_SDSDIO | WDT_RESET_MIC | WDT_RESET_CRT2C |		\
+	 WDT_RESET_PWM | WDT_RESET_PECI | WDT_RESET_JTAG |		\
+	 WDT_RESET_ADC | WDT_RESET_GPIO | WDT_RESET_MISC)
+
+#ifndef __ASSEMBLY__
+struct ast_wdt {
+	u32 counter_status;
+	u32 counter_reload_val;
+	u32 counter_restart;
+	u32 ctrl;
+	u32 timeout_status;
+	u32 clr_timeout_status;
+	u32 reset_width;
+	/* On pre-ast2500 SoCs this register is reserved. */
+	u32 reset_mask;
+};
+
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mode value from it.
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mode value
+ */
+u32 ast_reset_mode_from_flags(ulong flags);
+
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mask value from it. Reset Mask is only supported on ast2500
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mask value
+ */
+u32 ast_reset_mask_from_flags(ulong flags);
+
+/**
+ * Given Reset Mask and Reset Mode values, converts them to flags,
+ * suitable for passing into wdt_start or wdt_reset uclass functions.
+ *
+ * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
+ * can both be packed into single 32 bits wide value.
+ *
+ * @reset_mode: Reset Mode
+ * @reset_mask: Reset Mask
+ */
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
+#endif  /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARCH_WDT_H */
diff --git a/arch/arm/include/asm/arch-bcm235xx/boot0.h b/arch/arm/include/asm/arch-bcm235xx/boot0.h
new file mode 100644
index 0000000..8cde42b
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm235xx/boot0.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Broadcom Corporation.
+ */
+
+/* BOOT0 header information */
+_start:
+	ARM_VECTORS
+	.word	0xbabeface
+	.word	_end - _start
diff --git a/arch/arm/include/asm/arch-bcm235xx/gpio.h b/arch/arm/include/asm/arch-bcm235xx/gpio.h
new file mode 100644
index 0000000..82c12bb
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm235xx/gpio.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#ifndef __ARCH_BCM235XX_GPIO_H
+#define __ARCH_BCM235XX_GPIO_H
+
+/*
+ * Empty file - cmd_gpio.c requires this. The implementation
+ * is in drivers/gpio/kona_gpio.c instead of inlined here.
+ */
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm235xx/sysmap.h b/arch/arm/include/asm/arch-bcm235xx/sysmap.h
new file mode 100644
index 0000000..ff6debc
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm235xx/sysmap.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#ifndef __ARCH_BCM235XX_SYSMAP_H
+
+#define BSC1_BASE_ADDR		0x3e016000
+#define BSC2_BASE_ADDR		0x3e017000
+#define BSC3_BASE_ADDR		0x3e018000
+#define GPIO2_BASE_ADDR		0x35003000
+#define HSOTG_BASE_ADDR		0x3f120000
+#define HSOTG_CTRL_BASE_ADDR	0x3f130000
+#define KONA_MST_CLK_BASE_ADDR	0x3f001000
+#define KONA_SLV_CLK_BASE_ADDR	0x3e011000
+#define PMU_BSC_BASE_ADDR	0x3500d000
+#define SDIO1_BASE_ADDR		0x3f180000
+#define SDIO2_BASE_ADDR		0x3f190000
+#define SDIO3_BASE_ADDR		0x3f1a0000
+#define SDIO4_BASE_ADDR		0x3f1b0000
+#define TIMER_BASE_ADDR		0x3e00d000
+
+#define HSOTG_DCTL_OFFSET					0x00000804
+#define    HSOTG_DCTL_SFTDISCON_MASK				0x00000002
+
+#define HSOTG_CTRL_PHY_P1CTL_OFFSET				0x00000008
+#define    HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK			0x00000002
+#define    HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK		0x00000001
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm281xx/boot0.h b/arch/arm/include/asm/arch-bcm281xx/boot0.h
new file mode 100644
index 0000000..8cde42b
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm281xx/boot0.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Broadcom Corporation.
+ */
+
+/* BOOT0 header information */
+_start:
+	ARM_VECTORS
+	.word	0xbabeface
+	.word	_end - _start
diff --git a/arch/arm/include/asm/arch-bcm281xx/gpio.h b/arch/arm/include/asm/arch-bcm281xx/gpio.h
new file mode 100644
index 0000000..6716e1a
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm281xx/gpio.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#ifndef __ARCH_BCM281XX_GPIO_H
+#define __ARCH_BCM281XX_GPIO_H
+
+/*
+ * Empty file - cmd_gpio.c requires this. The implementation
+ * is in drivers/gpio/kona_gpio.c instead of inlined here.
+ */
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
new file mode 100644
index 0000000..477b693
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#ifndef __ARCH_BCM281XX_SYSMAP_H
+
+#define BSC1_BASE_ADDR		0x3e016000
+#define BSC2_BASE_ADDR		0x3e017000
+#define BSC3_BASE_ADDR		0x3e018000
+#define DWDMA_AHB_BASE_ADDR	0x38100000
+#define ESUB_CLK_BASE_ADDR	0x38000000
+#define ESW_CONTRL_BASE_ADDR	0x38200000
+#define GPIO2_BASE_ADDR		0x35003000
+#define HSOTG_BASE_ADDR		0x3f120000
+#define HSOTG_CTRL_BASE_ADDR	0x3f130000
+#define KONA_MST_CLK_BASE_ADDR	0x3f001000
+#define KONA_SLV_CLK_BASE_ADDR	0x3e011000
+#define PMU_BSC_BASE_ADDR	0x3500d000
+#define PWRMGR_BASE_ADDR	0x35010000
+#define SDIO1_BASE_ADDR		0x3f180000
+#define SDIO2_BASE_ADDR		0x3f190000
+#define SDIO3_BASE_ADDR		0x3f1a0000
+#define SDIO4_BASE_ADDR		0x3f1b0000
+#define SECWD_BASE_ADDR		0x3500c000
+#define SECWD2_BASE_ADDR	0x35002f40
+#define TIMER_BASE_ADDR		0x3e00d000
+
+#define HSOTG_DCTL_OFFSET					0x00000804
+#define    HSOTG_DCTL_SFTDISCON_MASK				0x00000002
+
+#define HSOTG_CTRL_PHY_P1CTL_OFFSET				0x00000008
+#define    HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK			0x00000002
+#define    HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK		0x00000001
+
+#endif
diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h
new file mode 100644
index 0000000..9eafe43
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014-2017 Broadcom.
+ */
+
+#ifndef __ARCH_CONFIGS_H
+#define __ARCH_CONFIGS_H
+
+#include <asm/iproc-common/configs.h>
+
+/* uArchitecture specifics */
+
+/* Serial Info */
+/* Post pad 3 bytes after each reg addr */
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_NS16550_CLK		100000000
+#define CONFIG_SYS_NS16550_CLK_DIV	54
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_NS16550_COM3		0x18023000
+
+/* Ethernet */
+#define CONFIG_PHY_BROADCOM
+#define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/
+
+#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h
new file mode 100644
index 0000000..05fa9b9
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcmnsp/configs.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#ifndef __ARCH_CONFIGS_H
+#define __ARCH_CONFIGS_H
+
+#include <asm/iproc-common/configs.h>
+
+/* uArchitecture specifics */
+
+/* Serial Info */
+/* no padding */
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#define CONFIG_SYS_NS16550_CLK		0x03b9aca0
+#define CONFIG_SYS_NS16550_COM1		0x18000300
+
+#endif /* __ARCH_CONFIGS_H */
diff --git a/arch/arm/include/asm/arch-ep93xx/ep93xx.h b/arch/arm/include/asm/arch-ep93xx/ep93xx.h
new file mode 100644
index 0000000..272b644
--- /dev/null
+++ b/arch/arm/include/asm/arch-ep93xx/ep93xx.h
@@ -0,0 +1,666 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Cirrus Logic EP93xx register definitions.
+ *
+ * Copyright (C) 2013
+ * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+ *
+ * Copyright (C) 2009
+ * Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * Copyright (C) 2006
+ * Dominic Rath <Dominic.Rath@gmx.de>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
+ *
+ * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
+ *
+ * Copyright (C) 2004 Ray Lehtiniemi
+ * Copyright (C) 2003 Cirrus Logic, Inc
+ * Copyright (C) 1999 ARM Limited.
+ */
+
+#define EP93XX_AHB_BASE			0x80000000
+#define EP93XX_APB_BASE			0x80800000
+
+/*
+ * 0x80000000 - 0x8000FFFF: DMA
+ */
+#define DMA_OFFSET			0x000000
+#define DMA_BASE			(EP93XX_AHB_BASE | DMA_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct dma_channel {
+	uint32_t control;
+	uint32_t interrupt;
+	uint32_t ppalloc;
+	uint32_t status;
+	uint32_t reserved0;
+	uint32_t remain;
+	uint32_t reserved1[2];
+	uint32_t maxcnt0;
+	uint32_t base0;
+	uint32_t current0;
+	uint32_t reserved2;
+	uint32_t maxcnt1;
+	uint32_t base1;
+	uint32_t current1;
+	uint32_t reserved3;
+};
+
+struct dma_regs {
+	struct dma_channel m2p_channel_0;
+	struct dma_channel m2p_channel_1;
+	struct dma_channel m2p_channel_2;
+	struct dma_channel m2p_channel_3;
+	struct dma_channel m2m_channel_0;
+	struct dma_channel m2m_channel_1;
+	struct dma_channel reserved0[2];
+	struct dma_channel m2p_channel_5;
+	struct dma_channel m2p_channel_4;
+	struct dma_channel m2p_channel_7;
+	struct dma_channel m2p_channel_6;
+	struct dma_channel m2p_channel_9;
+	struct dma_channel m2p_channel_8;
+	uint32_t channel_arbitration;
+	uint32_t reserved[15];
+	uint32_t global_interrupt;
+};
+#endif
+
+/*
+ * 0x80010000 - 0x8001FFFF: Ethernet MAC
+ */
+#define MAC_OFFSET			0x010000
+#define MAC_BASE			(EP93XX_AHB_BASE | MAC_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct mac_queue {
+	uint32_t badd;
+	union { /* deal with half-word aligned registers */
+		uint32_t blen;
+		union {
+			uint16_t filler;
+			uint16_t curlen;
+		};
+	};
+	uint32_t curadd;
+};
+
+struct mac_regs {
+	uint32_t rxctl;
+	uint32_t txctl;
+	uint32_t testctl;
+	uint32_t reserved0;
+	uint32_t miicmd;
+	uint32_t miidata;
+	uint32_t miists;
+	uint32_t reserved1;
+	uint32_t selfctl;
+	uint32_t inten;
+	uint32_t intstsp;
+	uint32_t intstsc;
+	uint32_t reserved2[2];
+	uint32_t diagad;
+	uint32_t diagdata;
+	uint32_t gt;
+	uint32_t fct;
+	uint32_t fcf;
+	uint32_t afp;
+	union {
+		struct {
+			uint32_t indad;
+			uint32_t indad_upper;
+		};
+		uint32_t hashtbl;
+	};
+	uint32_t reserved3[2];
+	uint32_t giintsts;
+	uint32_t giintmsk;
+	uint32_t giintrosts;
+	uint32_t giintfrc;
+	uint32_t txcollcnt;
+	uint32_t rxmissnct;
+	uint32_t rxruntcnt;
+	uint32_t reserved4;
+	uint32_t bmctl;
+	uint32_t bmsts;
+	uint32_t rxbca;
+	uint32_t reserved5;
+	struct mac_queue rxdq;
+	uint32_t rxdqenq;
+	struct mac_queue rxstsq;
+	uint32_t rxstsqenq;
+	struct mac_queue txdq;
+	uint32_t txdqenq;
+	struct mac_queue txstsq;
+	uint32_t reserved6;
+	uint32_t rxbufthrshld;
+	uint32_t txbufthrshld;
+	uint32_t rxststhrshld;
+	uint32_t txststhrshld;
+	uint32_t rxdthrshld;
+	uint32_t txdthrshld;
+	uint32_t maxfrmlen;
+	uint32_t maxhdrlen;
+};
+#endif
+
+#define SELFCTL_RWP		(1 << 7)
+#define SELFCTL_GPO0		(1 << 5)
+#define SELFCTL_PUWE		(1 << 4)
+#define SELFCTL_PDWE		(1 << 3)
+#define SELFCTL_MIIL		(1 << 2)
+#define SELFCTL_RESET		(1 << 0)
+
+#define INTSTS_RWI		(1 << 30)
+#define INTSTS_RXMI		(1 << 29)
+#define INTSTS_RXBI		(1 << 28)
+#define INTSTS_RXSQI		(1 << 27)
+#define INTSTS_TXLEI		(1 << 26)
+#define INTSTS_ECIE		(1 << 25)
+#define INTSTS_TXUHI		(1 << 24)
+#define INTSTS_MOI		(1 << 18)
+#define INTSTS_TXCOI		(1 << 17)
+#define INTSTS_RXROI		(1 << 16)
+#define INTSTS_MIII		(1 << 12)
+#define INTSTS_PHYI		(1 << 11)
+#define INTSTS_TI		(1 << 10)
+#define INTSTS_AHBE		(1 << 8)
+#define INTSTS_OTHER		(1 << 4)
+#define INTSTS_TXSQ		(1 << 3)
+#define INTSTS_RXSQ		(1 << 2)
+
+#define BMCTL_MT		(1 << 13)
+#define BMCTL_TT		(1 << 12)
+#define BMCTL_UNH		(1 << 11)
+#define BMCTL_TXCHR		(1 << 10)
+#define BMCTL_TXDIS		(1 << 9)
+#define BMCTL_TXEN		(1 << 8)
+#define BMCTL_EH2		(1 << 6)
+#define BMCTL_EH1		(1 << 5)
+#define BMCTL_EEOB		(1 << 4)
+#define BMCTL_RXCHR		(1 << 2)
+#define BMCTL_RXDIS		(1 << 1)
+#define BMCTL_RXEN		(1 << 0)
+
+#define BMSTS_TXACT		(1 << 7)
+#define BMSTS_TP		(1 << 4)
+#define BMSTS_RXACT		(1 << 3)
+#define BMSTS_QID_MASK		0x07
+#define BMSTS_QID_RXDATA	0x00
+#define BMSTS_QID_TXDATA	0x01
+#define BMSTS_QID_RXSTS		0x02
+#define BMSTS_QID_TXSTS		0x03
+#define BMSTS_QID_RXDESC	0x04
+#define BMSTS_QID_TXDESC	0x05
+
+#define AFP_MASK		0x07
+#define AFP_IAPRIMARY		0x00
+#define AFP_IASECONDARY1	0x01
+#define AFP_IASECONDARY2	0x02
+#define AFP_IASECONDARY3	0x03
+#define AFP_TX			0x06
+#define AFP_HASH		0x07
+
+#define RXCTL_PAUSEA		(1 << 20)
+#define RXCTL_RXFCE1		(1 << 19)
+#define RXCTL_RXFCE0		(1 << 18)
+#define RXCTL_BCRC		(1 << 17)
+#define RXCTL_SRXON		(1 << 16)
+#define RXCTL_RCRCA		(1 << 13)
+#define RXCTL_RA		(1 << 12)
+#define RXCTL_PA		(1 << 11)
+#define RXCTL_BA		(1 << 10)
+#define RXCTL_MA		(1 << 9)
+#define RXCTL_IAHA		(1 << 8)
+#define RXCTL_IA3		(1 << 3)
+#define RXCTL_IA2		(1 << 2)
+#define RXCTL_IA1		(1 << 1)
+#define RXCTL_IA0		(1 << 0)
+
+#define TXCTL_DEFDIS		(1 << 7)
+#define TXCTL_MBE		(1 << 6)
+#define TXCTL_ICRC		(1 << 5)
+#define TXCTL_TPD		(1 << 4)
+#define TXCTL_OCOLL		(1 << 3)
+#define TXCTL_SP		(1 << 2)
+#define TXCTL_PB		(1 << 1)
+#define TXCTL_STXON		(1 << 0)
+
+#define MIICMD_REGAD_MASK	(0x001F)
+#define MIICMD_PHYAD_MASK	(0x03E0)
+#define MIICMD_OPCODE_MASK	(0xC000)
+#define MIICMD_PHYAD_8950	(0x0000)
+#define MIICMD_OPCODE_READ	(0x8000)
+#define MIICMD_OPCODE_WRITE	(0x4000)
+
+#define MIISTS_BUSY		(1 << 0)
+
+/*
+ * 0x80020000 - 0x8002FFFF: USB OHCI
+ */
+#define USB_OFFSET			0x020000
+#define USB_BASE			(EP93XX_AHB_BASE | USB_OFFSET)
+
+/*
+ * 0x80030000 - 0x8003FFFF: Raster engine
+ */
+#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
+#define RASTER_OFFSET			0x030000
+#define RASTER_BASE			(EP93XX_AHB_BASE | RASTER_OFFSET)
+#endif
+
+/*
+ * 0x80040000 - 0x8004FFFF: Graphics accelerator
+ */
+#if defined(CONFIG_EP9315)
+#define GFX_OFFSET			0x040000
+#define GFX_BASE			(EP93XX_AHB_BASE | GFX_OFFSET)
+#endif
+
+/*
+ * 0x80050000 - 0x8005FFFF: Reserved
+ */
+
+/*
+ * 0x80060000 - 0x8006FFFF: SDRAM controller
+ */
+#define SDRAM_OFFSET			0x060000
+#define SDRAM_BASE			(EP93XX_AHB_BASE | SDRAM_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct sdram_regs {
+	uint32_t reserved;
+	uint32_t glconfig;
+	uint32_t refrshtimr;
+	uint32_t bootsts;
+	uint32_t devcfg0;
+	uint32_t devcfg1;
+	uint32_t devcfg2;
+	uint32_t devcfg3;
+};
+#endif
+
+#define SDRAM_DEVCFG_EXTBUSWIDTH	(1 << 2)
+#define SDRAM_DEVCFG_BANKCOUNT		(1 << 3)
+#define SDRAM_DEVCFG_SROMLL		(1 << 5)
+#define SDRAM_DEVCFG_CASLAT_2		0x00010000
+#define SDRAM_DEVCFG_RASTOCAS_2		0x00200000
+
+#define SDRAM_OFF_GLCONFIG		0x0004
+#define SDRAM_OFF_REFRSHTIMR		0x0008
+
+#define SDRAM_OFF_DEVCFG0		0x0010
+#define SDRAM_OFF_DEVCFG1		0x0014
+#define SDRAM_OFF_DEVCFG2		0x0018
+#define SDRAM_OFF_DEVCFG3		0x001C
+
+#define SDRAM_DEVCFG0_BASE		0xC0000000
+#define SDRAM_DEVCFG1_BASE		0xD0000000
+#define SDRAM_DEVCFG2_BASE		0xE0000000
+#define SDRAM_DEVCFG3_ASD0_BASE		0xF0000000
+#define SDRAM_DEVCFG3_ASD1_BASE		0x00000000
+
+#define GLCONFIG_INIT			(1 << 0)
+#define GLCONFIG_MRS			(1 << 1)
+#define GLCONFIG_SMEMBUSY		(1 << 5)
+#define GLCONFIG_LCR			(1 << 6)
+#define GLCONFIG_REARBEN		(1 << 7)
+#define GLCONFIG_CLKSHUTDOWN		(1 << 30)
+#define GLCONFIG_CKE			(1 << 31)
+
+#define EP93XX_SDRAMCTRL			0x80060000
+#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT		0x00000001
+#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS		0x00000002
+#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY	0x00000020
+#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR		0x00000040
+#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN	0x00000080
+#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN	0x40000000
+#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE		0x80000000
+
+#define EP93XX_SDRAMCTRL_REFRESH_MASK		0x0000FFFF
+
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32	0x00000002
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16	0x00000001
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8	0x00000000
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK	0x00000003
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA	0x00000004
+
+#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH	0x00000004
+#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT	0x00000008
+#define EP93XX_SDRAMCTRL_DEVCFG_SROM512		0x00000010
+#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL		0x00000020
+#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE		0x00000040
+#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR	0x00000080
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK	0x00070000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2	0x00010000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3	0x00020000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4	0x00030000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5	0x00040000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6	0x00050000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7	0x00060000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8	0x00070000
+#define EP93XX_SDRAMCTRL_DEVCFG_WBL		0x00080000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK	0x00300000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2	0x00200000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3	0x00300000
+#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE	0x01000000
+
+/*
+ * 0x80070000 - 0x8007FFFF: Reserved
+ */
+
+/*
+ * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
+ */
+#define SMC_OFFSET			0x080000
+#define SMC_BASE			(EP93XX_AHB_BASE | SMC_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct smc_regs {
+	uint32_t bcr0;
+	uint32_t bcr1;
+	uint32_t bcr2;
+	uint32_t bcr3;
+	uint32_t reserved0[2];
+	uint32_t bcr6;
+	uint32_t bcr7;
+#if defined(CONFIG_EP9315)
+	uint32_t pcattribute;
+	uint32_t pccommon;
+	uint32_t pcio;
+	uint32_t reserved1[5];
+	uint32_t pcmciactrl;
+#endif
+};
+#endif
+
+#define EP93XX_OFF_SMCBCR0		0x00
+#define EP93XX_OFF_SMCBCR1		0x04
+#define EP93XX_OFF_SMCBCR2		0x08
+#define EP93XX_OFF_SMCBCR3		0x0C
+#define EP93XX_OFF_SMCBCR6		0x18
+#define EP93XX_OFF_SMCBCR7		0x1C
+
+#define SMC_BCR_IDCY_SHIFT	0
+#define SMC_BCR_WST1_SHIFT	5
+#define SMC_BCR_BLE		(1 << 10)
+#define SMC_BCR_WST2_SHIFT	11
+#define SMC_BCR_MW_SHIFT	28
+
+/*
+ * 0x80090000 - 0x8009FFFF: Boot ROM
+ */
+
+/*
+ * 0x800A0000 - 0x800AFFFF: IDE interface
+ */
+
+/*
+ * 0x800B0000 - 0x800BFFFF: VIC1
+ */
+
+/*
+ * 0x800C0000 - 0x800CFFFF: VIC2
+ */
+
+/*
+ * 0x800D0000 - 0x800FFFFF: Reserved
+ */
+
+/*
+ * 0x80800000 - 0x8080FFFF: Reserved
+ */
+
+/*
+ * 0x80810000 - 0x8081FFFF: Timers
+ */
+#define TIMER_OFFSET		0x010000
+#define TIMER_BASE		(EP93XX_APB_BASE | TIMER_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct timer {
+	uint32_t load;
+	uint32_t value;
+	uint32_t control;
+	uint32_t clear;
+};
+
+struct timer4 {
+	uint32_t value_low;
+	uint32_t value_high;
+};
+
+struct timer_regs {
+	struct timer timer1;
+	uint32_t reserved0[4];
+	struct timer timer2;
+	uint32_t reserved1[12];
+	struct timer4 timer4;
+	uint32_t reserved2[6];
+	struct timer timer3;
+};
+#endif
+
+/*
+ * 0x80820000 - 0x8082FFFF: I2S
+ */
+#define I2S_OFFSET		0x020000
+#define I2S_BASE		(EP93XX_APB_BASE | I2S_OFFSET)
+
+/*
+ * 0x80830000 - 0x8083FFFF: Security
+ */
+#define SECURITY_OFFSET		0x030000
+#define SECURITY_BASE		(EP93XX_APB_BASE | SECURITY_OFFSET)
+
+#define EXTENSIONID		(SECURITY_BASE + 0x2714)
+
+/*
+ * 0x80840000 - 0x8084FFFF: GPIO
+ */
+#define GPIO_OFFSET		0x040000
+#define GPIO_BASE		(EP93XX_APB_BASE | GPIO_OFFSET)
+
+#ifndef __ASSEMBLY__
+struct gpio_int {
+	uint32_t inttype1;
+	uint32_t inttype2;
+	uint32_t eoi;
+	uint32_t inten;
+	uint32_t intsts;
+	uint32_t rawintsts;
+	uint32_t db;
+};
+
+struct gpio_regs {
+	uint32_t padr;
+	uint32_t pbdr;
+	uint32_t pcdr;
+	uint32_t pddr;
+	uint32_t paddr;
+	uint32_t pbddr;
+	uint32_t pcddr;
+	uint32_t pdddr;
+	uint32_t pedr;
+	uint32_t peddr;
+	uint32_t reserved0[2];
+	uint32_t pfdr;
+	uint32_t pfddr;
+	uint32_t pgdr;
+	uint32_t pgddr;
+	uint32_t phdr;
+	uint32_t phddr;
+	uint32_t reserved1;
+	uint32_t finttype1;
+	uint32_t finttype2;
+	uint32_t reserved2;
+	struct gpio_int pfint;
+	uint32_t reserved3[10];
+	struct gpio_int paint;
+	struct gpio_int pbint;
+	uint32_t eedrive;
+};
+#endif
+
+#define EP93XX_LED_DATA		0x80840020
+#define EP93XX_LED_GREEN_ON	0x0001
+#define EP93XX_LED_RED_ON	0x0002
+
+#define EP93XX_LED_DDR		0x80840024
+#define EP93XX_LED_GREEN_ENABLE	0x0001
+#define EP93XX_LED_RED_ENABLE	0x00020000
+
+/*
+ * 0x80850000 - 0x8087FFFF: Reserved
+ */
+
+/*
+ * 0x80880000 - 0x8088FFFF: AAC
+ */
+#define AAC_OFFSET		0x080000
+#define AAC_BASE		(EP93XX_APB_BASE | AAC_OFFSET)
+
+/*
+ * 0x80890000 - 0x8089FFFF: Reserved
+ */
+
+/*
+ * 0x808A0000 - 0x808AFFFF: SPI
+ */
+#define SPI_OFFSET		0x0A0000
+#define SPI_BASE		(EP93XX_APB_BASE | SPI_OFFSET)
+
+/*
+ * 0x808B0000 - 0x808BFFFF: IrDA
+ */
+#define IRDA_OFFSET		0x0B0000
+#define IRDA_BASE		(EP93XX_APB_BASE | IRDA_OFFSET)
+
+/*
+ * 0x808C0000 - 0x808CFFFF: UART1
+ */
+#define UART1_OFFSET		0x0C0000
+#define UART1_BASE		(EP93XX_APB_BASE | UART1_OFFSET)
+
+/*
+ * 0x808D0000 - 0x808DFFFF: UART2
+ */
+#define UART2_OFFSET		0x0D0000
+#define UART2_BASE		(EP93XX_APB_BASE | UART2_OFFSET)
+
+/*
+ * 0x808E0000 - 0x808EFFFF: UART3
+ */
+#define UART3_OFFSET		0x0E0000
+#define UART3_BASE		(EP93XX_APB_BASE | UART3_OFFSET)
+
+/*
+ * 0x808F0000 - 0x808FFFFF: Key Matrix
+ */
+#define KEY_OFFSET		0x0F0000
+#define KEY_BASE		(EP93XX_APB_BASE | KEY_OFFSET)
+
+/*
+ * 0x80900000 - 0x8090FFFF: Touchscreen
+ */
+#define TOUCH_OFFSET		0x900000
+#define TOUCH_BASE		(EP93XX_APB_BASE | TOUCH_OFFSET)
+
+/*
+ * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
+ */
+#define PWM_OFFSET		0x910000
+#define PWM_BASE		(EP93XX_APB_BASE | PWM_OFFSET)
+
+/*
+ * 0x80920000 - 0x8092FFFF: Real time clock
+ */
+#define RTC_OFFSET		0x920000
+#define RTC_BASE		(EP93XX_APB_BASE | RTC_OFFSET)
+
+/*
+ * 0x80930000 - 0x8093FFFF: Syscon
+ */
+#define SYSCON_OFFSET		0x930000
+#define SYSCON_BASE		(EP93XX_APB_BASE | SYSCON_OFFSET)
+
+/* Security */
+#define SECURITY_EXTENSIONID	0x80832714
+
+#ifndef __ASSEMBLY__
+struct syscon_regs {
+	uint32_t pwrsts;
+	uint32_t pwrcnt;
+	uint32_t halt;
+	uint32_t stby;
+	uint32_t reserved0[2];
+	uint32_t teoi;
+	uint32_t stfclr;
+	uint32_t clkset1;
+	uint32_t clkset2;
+	uint32_t reserved1[6];
+	uint32_t scratch0;
+	uint32_t scratch1;
+	uint32_t reserved2[2];
+	uint32_t apbwait;
+	uint32_t bustmstrarb;
+	uint32_t bootmodeclr;
+	uint32_t reserved3[9];
+	uint32_t devicecfg;
+	uint32_t vidclkdiv;
+	uint32_t mirclkdiv;
+	uint32_t i2sclkdiv;
+	uint32_t keytchclkdiv;
+	uint32_t chipid;
+	uint32_t reserved4;
+	uint32_t syscfg;
+	uint32_t reserved5[8];
+	uint32_t sysswlock;
+};
+#else
+#define SYSCON_SCRATCH0		(SYSCON_BASE + 0x0040)
+#endif
+
+#define SYSCON_OFF_CLKSET1			0x0020
+#define SYSCON_OFF_SYSCFG			0x009c
+
+#define SYSCON_PWRCNT_UART_BAUD			(1 << 29)
+#define SYSCON_PWRCNT_USH_EN			(1 << 28)
+
+#define SYSCON_CLKSET_PLL_X2IPD_SHIFT		0
+#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT		5
+#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT		11
+#define SYSCON_CLKSET_PLL_PS_SHIFT		16
+#define SYSCON_CLKSET1_PCLK_DIV_SHIFT		18
+#define SYSCON_CLKSET1_HCLK_DIV_SHIFT		20
+#define SYSCON_CLKSET1_NBYP1			(1 << 23)
+#define SYSCON_CLKSET1_FCLK_DIV_SHIFT		25
+
+#define SYSCON_CLKSET2_PLL2_EN			(1 << 18)
+#define SYSCON_CLKSET2_NBYP2			(1 << 19)
+#define SYSCON_CLKSET2_USB_DIV_SHIFT		28
+
+#define SYSCON_CHIPID_REV_MASK			0xF0000000
+#define SYSCON_DEVICECFG_SWRST			(1 << 31)
+
+#define SYSCON_SYSCFG_LASDO			0x00000020
+
+/*
+ * 0x80930000 - 0x8093FFFF: Watchdog Timer
+ */
+#define WATCHDOG_OFFSET		0x940000
+#define WATCHDOG_BASE		(EP93XX_APB_BASE | WATCHDOG_OFFSET)
+
+/*
+ * 0x80950000 - 0x9000FFFF: Reserved
+ */
+
+/*
+ * During low_level init we store memory layout in memory at specific location
+ */
+#define UBOOT_MEMORYCNF_BANK_SIZE		0x2000
+#define UBOOT_MEMORYCNF_BANK_MASK		0x2004
+#define UBOOT_MEMORYCNF_BANK_COUNT		0x2008
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
new file mode 100644
index 0000000..b37a08d
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP Semiconductors
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
+#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
+
+#include <common.h>
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_BUS_CLK,
+	MXC_UART_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_I2C_CLK,
+	MXC_DSPI_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+ulong get_ddr_freq(ulong);
+uint get_svr(void);
+
+#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
new file mode 100644
index 0000000..a83c70e
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -0,0 +1,404 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016-2018 NXP
+ * Copyright 2015, Freescale Semiconductor
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+
+#include <linux/kconfig.h>
+#include <fsl_ddrc_version.h>
+
+#define CONFIG_STANDALONE_LOAD_ADDR	0x80300000
+
+/*
+ * Reserve secure memory
+ * To be aligned with MMU block size
+ */
+#define CONFIG_SYS_MEM_RESERVE_SECURE	(66 * 1024 * 1024)	/* 66MB */
+#define SPL_TLB_SETBACK	0x1000000	/* 16MB under effective memory top */
+
+#ifdef CONFIG_ARCH_LS2080A
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
+#define	SRDS_MAX_LANES	8
+#define CONFIG_SYS_PAGE_SIZE		0x10000
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT		6
+#define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
+#endif
+
+#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0x06000000
+#define GICR_BASE			0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE			0x05000000 /* GR0 Base */
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+
+/* Cache Coherent Interconnect */
+#define CCI_MN_BASE			0x04000000
+#define CCI_MN_RNF_NODEID_LIST		0x180
+#define CCI_MN_DVM_DOMAIN_CTL		0x200
+#define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
+
+#define CCI_HN_F_0_BASE			(CCI_MN_BASE + 0x200000)
+#define CCI_HN_F_1_BASE			(CCI_MN_BASE + 0x210000)
+#define CCN_HN_F_SAM_CTL		0x8	/* offset on base HN_F base */
+#define CCN_HN_F_SAM_NODEID_MASK	0x7f
+#define CCN_HN_F_SAM_NODEID_DDR0	0x4
+#define CCN_HN_F_SAM_NODEID_DDR1	0xe
+
+#define CCI_RN_I_0_BASE			(CCI_MN_BASE + 0x800000)
+#define CCI_RN_I_2_BASE			(CCI_MN_BASE + 0x820000)
+#define CCI_RN_I_6_BASE			(CCI_MN_BASE + 0x860000)
+#define CCI_RN_I_12_BASE		(CCI_MN_BASE + 0x8C0000)
+#define CCI_RN_I_16_BASE		(CCI_MN_BASE + 0x900000)
+#define CCI_RN_I_20_BASE		(CCI_MN_BASE + 0x940000)
+
+#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
+#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
+#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
+
+#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE				0x02200000
+#define TZPCR0SIZE_BASE				(TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
+
+#define DCSR_CGACRE5		0x700070914ULL
+#define EPU_EPCMPR5		0x700060914ULL
+#define EPU_EPCCR5		0x700060814ULL
+#define EPU_EPSMCR5		0x700060228ULL
+#define EPU_EPECR5		0x700060314ULL
+#define EPU_EPCTR5		0x700060a14ULL
+#define EPU_EPGCR		0x700060000ULL
+
+#define CONFIG_SYS_FSL_ERRATUM_A008751
+
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+
+#elif defined(CONFIG_ARCH_LS1088A)
+#define CONFIG_SYS_FSL_NUM_CC_PLLS		3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
+#define CONFIG_GICV3
+#define CONFIG_SYS_PAGE_SIZE		0x10000
+
+#define	SRDS_MAX_LANES	4
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE				0x02200000
+#define TZPCR0SIZE_BASE				(TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0x06000000
+#define GICR_BASE			0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE			0x05000000 /* GR0 Base */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
+#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
+
+/* LX2160A Soc Support */
+#elif defined(CONFIG_ARCH_LX2160A)
+#define TZPC_BASE				0x02200000
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#if !defined(CONFIG_DM_I2C)
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_EARLY_INIT
+#endif
+#define SRDS_MAX_LANES  8
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT		6
+#define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
+#endif
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER	2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 1, 1, 4, 4, 4, 4 }
+#define CONFIG_SYS_FSL_NUM_CC_PLLS		4
+
+#define CONFIG_SYS_PAGE_SIZE			0x10000
+
+#define CONFIG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE				0x06000000
+#define GICR_BASE				0x06200000
+
+/* SMMU Definitions */
+#define SMMU_BASE				0x05000000 /* GR0 Base */
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+
+#elif defined(CONFIG_ARCH_LS1028A)
+#define CONFIG_SYS_FSL_NUM_CC_PLLS		3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_TZASC_400
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE				0x02200000
+#define TZPCR0SIZE_BASE				(TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
+
+#define	SRDS_MAX_LANES	4
+
+#define CONFIG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE				0x06000000
+#define GICR_BASE				0x06040000
+
+/* SMMU Definitions */
+#define SMMU_BASE				0x05000000 /* GR0 Base */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* SEC */
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+
+#elif defined(CONFIG_FSL_LSCH2)
+#define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00020000 /* Real size 128K */
+
+#define DCSR_DCFG_SBEESR2			0x20140534
+#define DCSR_DCFG_MBEESR2			0x20140544
+
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
+
+/* SoC related */
+#ifdef CONFIG_ARCH_LS1043A
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FSL_QMAN_V3
+#define CONFIG_SYS_NUM_FMAN			1
+#define CONFIG_SYS_NUM_FM1_DTSEC		7
+#define CONFIG_SYS_NUM_FM1_10GEC		1
+#define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define QE_MURAM_SIZE		0x6000UL
+#define MAX_QE_RISC		1
+#define QE_NUM_OF_SNUM		28
+
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SEC_MON_BE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+
+/* SMMU Defintions */
+#define SMMU_BASE		0x09000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE		0x01401000
+#define GICC_BASE		0x01402000
+#define GICH_BASE		0x01404000
+#define GICV_BASE		0x01406000
+#define GICD_SIZE		0x1000
+#define GICC_SIZE		0x2000
+#define GICH_SIZE		0x2000
+#define GICV_SIZE		0x2000
+#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
+#define GICD_BASE_64K		0x01410000
+#define GICC_BASE_64K		0x01420000
+#define GICH_BASE_64K		0x01440000
+#define GICV_BASE_64K		0x01460000
+#define GICD_SIZE_64K		0x10000
+#define GICC_SIZE_64K		0x20000
+#define GICH_SIZE_64K		0x20000
+#define GICV_SIZE_64K		0x20000
+#endif
+
+#define DCFG_CCSR_SVR		0x1ee00a4
+#define REV1_0			0x10
+#define REV1_1			0x11
+#define GIC_ADDR_BIT		31
+#define SCFG_GIC400_ALIGN	0x1570188
+
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+
+#elif defined(CONFIG_ARCH_LS1012A)
+#define GICD_BASE		0x01401000
+#define GICC_BASE		0x01402000
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SEC_MON_BE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC           1
+#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#elif defined(CONFIG_ARCH_LS1046A)
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FSL_QMAN_V3
+#define CONFIG_SYS_NUM_FMAN			1
+#define CONFIG_SYS_NUM_FM1_DTSEC		8
+#define CONFIG_SYS_NUM_FM1_10GEC		2
+#define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SEC_MON_BE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+
+/* SMMU Defintions */
+#define SMMU_BASE		0x09000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE		0x01410000
+#define GICC_BASE		0x01420000
+
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+#else
+#error SoC not defined
+#endif
+#endif
+
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
new file mode 100644
index 0000000..7759acd
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2014-2015, Freescale Semiconductor
+ */
+
+#ifndef _FSL_LAYERSCAPE_CPU_H
+#define _FSL_LAYERSCAPE_CPU_H
+
+#ifdef CONFIG_FSL_LSCH3
+#define CONFIG_SYS_FSL_CCSR_BASE	0x00000000
+#define CONFIG_SYS_FSL_CCSR_SIZE	0x10000000
+#define CONFIG_SYS_FSL_QSPI_BASE1	0x20000000
+#define CONFIG_SYS_FSL_QSPI_SIZE1	0x10000000
+#ifndef CONFIG_NXP_LSCH3_2
+#define CONFIG_SYS_FSL_IFC_BASE1	0x30000000
+#define CONFIG_SYS_FSL_IFC_SIZE1	0x10000000
+#define CONFIG_SYS_FSL_IFC_SIZE1_1	0x400000
+#endif
+#define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
+#define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
+#define CONFIG_SYS_FSL_QSPI_BASE2	0x400000000
+#define CONFIG_SYS_FSL_QSPI_SIZE2	0x100000000
+#ifndef CONFIG_NXP_LSCH3_2
+#define CONFIG_SYS_FSL_IFC_BASE2	0x500000000
+#define CONFIG_SYS_FSL_IFC_SIZE2	0x100000000
+#endif
+#define CONFIG_SYS_FSL_DCSR_BASE	0x700000000
+#define CONFIG_SYS_FSL_DCSR_SIZE	0x40000000
+#define CONFIG_SYS_FSL_MC_BASE		0x80c000000
+#define CONFIG_SYS_FSL_MC_SIZE		0x4000000
+#define CONFIG_SYS_FSL_NI_BASE		0x810000000
+#define CONFIG_SYS_FSL_NI_SIZE		0x8000000
+#define CONFIG_SYS_FSL_QBMAN_BASE	0x818000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE	0x8000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE_1	0x4000000
+#ifdef CONFIG_ARCH_LS2080A
+#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x200000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x200000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x200000000
+#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x200000000
+#else
+#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
+#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE
+#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
+#endif
+#define CONFIG_SYS_PCIE4_PHYS_SIZE	0x800000000
+#define SYS_PCIE5_PHYS_SIZE		0x800000000
+#define SYS_PCIE6_PHYS_SIZE		0x800000000
+#endif
+#define CONFIG_SYS_FSL_WRIOP1_BASE	0x4300000000
+#define CONFIG_SYS_FSL_WRIOP1_SIZE	0x100000000
+#define CONFIG_SYS_FSL_AIOP1_BASE	0x4b00000000
+#define CONFIG_SYS_FSL_AIOP1_SIZE	0x100000000
+#ifndef CONFIG_ARCH_LX2160A
+#define CONFIG_SYS_FSL_PEBUF_BASE	0x4c00000000
+#else
+#define CONFIG_SYS_FSL_PEBUF_BASE	0x1c00000000
+#endif
+#define CONFIG_SYS_FSL_PEBUF_SIZE	0x400000000
+#ifdef CONFIG_NXP_LSCH3_2
+#define CONFIG_SYS_FSL_DRAM_BASE2	0x2080000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2	0x1F80000000
+#define CONFIG_SYS_FSL_DRAM_BASE3	0x6000000000
+#define CONFIG_SYS_FSL_DRAM_SIZE3	0x2000000000
+#else
+#define CONFIG_SYS_FSL_DRAM_BASE2	0x8080000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2	0x7F80000000
+#endif
+#elif defined(CONFIG_FSL_LSCH2)
+#define CONFIG_SYS_FSL_BOOTROM_BASE	0x0
+#define CONFIG_SYS_FSL_BOOTROM_SIZE	0x1000000
+#define CONFIG_SYS_FSL_CCSR_BASE	0x1000000
+#define CONFIG_SYS_FSL_CCSR_SIZE	0xf000000
+#define CONFIG_SYS_FSL_DCSR_BASE	0x20000000
+#define CONFIG_SYS_FSL_DCSR_SIZE	0x4000000
+#define CONFIG_SYS_FSL_QSPI_BASE	0x40000000
+#define CONFIG_SYS_FSL_QSPI_SIZE	0x20000000
+#define CONFIG_SYS_FSL_IFC_BASE		0x60000000
+#define CONFIG_SYS_FSL_IFC_SIZE		0x20000000
+#define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
+#define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
+#define CONFIG_SYS_FSL_QBMAN_BASE	0x500000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE	0x10000000
+#define CONFIG_SYS_FSL_DRAM_BASE2	0x880000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2	0x780000000	/* 30GB */
+#define CONFIG_SYS_PCIE1_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE	0x800000000
+#define CONFIG_SYS_FSL_DRAM_BASE3	0x8800000000
+#define CONFIG_SYS_FSL_DRAM_SIZE3	0x7800000000	/* 480GB */
+#endif
+
+int fsl_qoriq_core_to_cluster(unsigned int core);
+u32 cpu_mask(void);
+
+#endif /* _FSL_LAYERSCAPE_CPU_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
new file mode 100644
index 0000000..ebc999c
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+
+void fdt_fixup_board_enet(void *fdt);
+#endif	/* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
new file mode 100644
index 0000000..37e2fe4
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef _FSL_ICID_H_
+#define _FSL_ICID_H_
+
+#include <asm/types.h>
+#include <fsl_qbman.h>
+#include <fsl_sec.h>
+#include <asm/armv8/sec_firmware.h>
+
+struct icid_id_table {
+	const char *compat;
+	u32 id;
+	u32 reg;
+	phys_addr_t compat_addr;
+	phys_addr_t reg_addr;
+	bool le;
+};
+
+struct fman_icid_id_table {
+	u32 port_id;
+	u32 icid;
+};
+
+u32 get_ppid_icid(int ppid_tbl_idx, int ppid);
+int fdt_get_smmu_phandle(void *blob);
+int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
+void set_icids(void);
+void fdt_fixup_icid(void *blob);
+
+#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
+	{ .compat = name, \
+	  .id = idA, \
+	  .reg = regA, \
+	  .compat_addr = compataddr, \
+	  .reg_addr = addr, \
+	  .le = _le \
+	}
+
+#ifdef CONFIG_SYS_FSL_SEC_LE
+#define SEC_IS_LE true
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+#define SEC_IS_LE false
+#endif
+
+#ifdef CONFIG_FSL_LSCH2
+
+#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define SCFG_IS_LE true
+#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
+#define SCFG_IS_LE false
+#endif
+
+#define QDMA_IS_LE false
+
+#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
+	SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
+		offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
+		compataddr, SCFG_IS_LE)
+
+#define SET_USB_ICID(usb_num, compat, streamid) \
+	SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\
+		CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+
+#define SET_SATA_ICID(compat, streamid) \
+	SET_SCFG_ICID(compat, streamid, sata_icid,\
+		AHCI_BASE_ADDR)
+
+#define SET_SDHC_ICID(streamid) \
+	SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
+		CONFIG_SYS_FSL_ESDHC_ADDR)
+
+#define SET_EDMA_ICID(streamid) \
+	SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
+		EDMA_BASE_ADDR)
+
+#define SET_ETR_ICID(streamid) \
+	SET_SCFG_ICID(NULL, streamid, etr_icid, 0)
+
+#define SET_DEBUG_ICID(streamid) \
+	SET_SCFG_ICID(NULL, streamid, debug_icid, 0)
+
+#define SET_QE_ICID(streamid) \
+	SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\
+		QE_BASE_ADDR)
+
+#define SET_QMAN_ICID(streamid) \
+	SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
+		offsetof(struct ccsr_qman, liodnr) + \
+		CONFIG_SYS_FSL_QMAN_ADDR, \
+		CONFIG_SYS_FSL_QMAN_ADDR, false)
+
+#define SET_BMAN_ICID(streamid) \
+	SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
+		offsetof(struct ccsr_bman, liodnr) + \
+		CONFIG_SYS_FSL_BMAN_ADDR, \
+		CONFIG_SYS_FSL_BMAN_ADDR, false)
+
+#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
+	{ .port_id = (_port_id), .icid = (streamid) }
+
+#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))
+
+#define SET_SEC_QI_ICID(streamid) \
+	SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
+		0, offsetof(ccsr_sec_t, qilcr_ls) + \
+		CONFIG_SYS_FSL_SEC_ADDR, \
+		CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
+
+extern struct fman_icid_id_table fman_icid_tbl[];
+extern int fman_icid_tbl_sz;
+
+#else /* CONFIG_FSL_LSCH2 */
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define GUR_IS_LE true
+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
+#define GUR_IS_LE false
+#endif
+
+#define QDMA_IS_LE true
+
+#define SET_GUR_ICID(compat, streamid, name, compataddr) \
+	SET_ICID_ENTRY(compat, streamid, streamid, \
+		offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
+		compataddr, GUR_IS_LE)
+
+#define SET_USB_ICID(usb_num, compat, streamid) \
+	SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\
+		CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+
+#define SET_SATA_ICID(sata_num, compat, streamid) \
+	SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \
+		AHCI_BASE_ADDR##sata_num)
+
+#define SET_SDHC_ICID(sdhc_num, streamid) \
+	SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\
+		FSL_ESDHC##sdhc_num##_BASE_ADDR)
+
+#define SET_EDMA_ICID(streamid) \
+	SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\
+		EDMA_BASE_ADDR)
+
+#define SET_GPU_ICID(compat, streamid) \
+	SET_GUR_ICID(compat, streamid, misc1_amqr,\
+		GPU_BASE_ADDR)
+
+#define SET_DISPLAY_ICID(streamid) \
+	SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\
+		DISPLAY_BASE_ADDR)
+
+#define SEC_ICID_REG_VAL(streamid) (streamid)
+
+#endif /* CONFIG_FSL_LSCH2 */
+
+#define SET_QDMA_ICID(compat, streamid) \
+	SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
+		QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
+		QDMA_BASE_ADDR, QDMA_IS_LE), \
+	SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
+		QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
+		QDMA_BASE_ADDR, QDMA_IS_LE)
+
+#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
+	SET_ICID_ENTRY( \
+		(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \
+		(FSL_SEC_JR##jr_num##_OFFSET ==  \
+			SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
+			? NULL \
+			: "fsl,sec-v4.0-job-ring"), \
+		streamid, \
+		SEC_ICID_REG_VAL(streamid), \
+		offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
+		CONFIG_SYS_FSL_SEC_ADDR, \
+		FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
+
+#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
+	SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
+		offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
+		CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+
+#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
+	SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
+		offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
+		CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+
+extern struct icid_id_table icid_tbl[];
+extern int icid_tbl_sz;
+
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
new file mode 100644
index 0000000..1577e93
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef _FSL_PORTALS_H_
+#define _FSL_PORTALS_H_
+
+struct qportal_info {
+	u16	dicid;	/* DQRR ICID */
+	u16	ficid;	/* frame data ICID */
+	u16	icid;
+	u8	sdest;
+};
+
+#define SET_QP_INFO(streamid, dest) \
+	{ .dicid = (streamid), .ficid = (streamid), .icid = (streamid), \
+	.sdest = (dest) }
+
+extern struct qportal_info qp_info[];
+void fdt_portal(void *blob, const char *compat, const char *container,
+		u64 addr, u32 size);
+
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
new file mode 100644
index 0000000..8f43651
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_SERDES_H__
+#define __FSL_SERDES_H__
+
+#include <config.h>
+
+#ifdef CONFIG_FSL_LSCH3
+enum srds_prtcl {
+	/*
+	 * Nobody will check whether the device 'NONE' has been configured,
+	 * So use it to indicate if the serdes_prtcl_map has been initialized.
+	 */
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	PCIE3,
+	PCIE4,
+	PCIE5,
+	PCIE6,
+	SATA1,
+	SATA2,
+	SATA3,
+	SATA4,
+	XAUI1,
+	XAUI2,
+	XFI1,
+	XFI2,
+	XFI3,
+	XFI4,
+	XFI5,
+	XFI6,
+	XFI7,
+	XFI8,
+	XFI9,
+	XFI10,
+	XFI11,
+	XFI12,
+	XFI13,
+	XFI14,
+	SGMII1,
+	SGMII2,
+	SGMII3,
+	SGMII4,
+	SGMII5,
+	SGMII6,
+	SGMII7,
+	SGMII8,
+	SGMII9,
+	SGMII10,
+	SGMII11,
+	SGMII12,
+	SGMII13,
+	SGMII14,
+	SGMII15,
+	SGMII16,
+	SGMII17,
+	SGMII18,
+	QSGMII_A,
+	QSGMII_B,
+	QSGMII_C,
+	QSGMII_D,
+	SGMII_T1,
+	SGMII_T2,
+	SGMII_T3,
+	SGMII_T4,
+	SXGMII1,
+	SXGMII2,
+	SXGMII3,
+	SXGMII4,
+	QXGMII1,
+	QXGMII2,
+	QXGMII3,
+	QXGMII4,
+	_25GE1,
+	_25GE2,
+	_25GE3,
+	_25GE4,
+	_25GE5,
+	_25GE6,
+	_25GE7,
+	_25GE8,
+	_25GE9,
+	_25GE10,
+	_40GE1,
+	_40GE2,
+	_50GE1,
+	_50GE2,
+	_100GE1,
+	_100GE2,
+	SERDES_PRCTL_COUNT
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+	NXP_SRDS_3  = 2,
+};
+#elif defined(CONFIG_FSL_LSCH2)
+enum srds_prtcl {
+	/*
+	 * Nobody will check whether the device 'NONE' has been configured,
+	 * So use it to indicate if the serdes_prtcl_map has been initialized.
+	 */
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	PCIE3,
+	PCIE4,
+	SATA1,
+	SATA2,
+	SRIO1,
+	SRIO2,
+	SGMII_FM1_DTSEC1,
+	SGMII_FM1_DTSEC2,
+	SGMII_FM1_DTSEC3,
+	SGMII_FM1_DTSEC4,
+	SGMII_FM1_DTSEC5,
+	SGMII_FM1_DTSEC6,
+	SGMII_FM1_DTSEC9,
+	SGMII_FM1_DTSEC10,
+	SGMII_FM2_DTSEC1,
+	SGMII_FM2_DTSEC2,
+	SGMII_FM2_DTSEC3,
+	SGMII_FM2_DTSEC4,
+	SGMII_FM2_DTSEC5,
+	SGMII_FM2_DTSEC6,
+	SGMII_FM2_DTSEC9,
+	SGMII_FM2_DTSEC10,
+	SGMII_TSEC1,
+	SGMII_TSEC2,
+	SGMII_TSEC3,
+	SGMII_TSEC4,
+	XAUI_FM1,
+	XAUI_FM2,
+	AURORA,
+	CPRI1,
+	CPRI2,
+	CPRI3,
+	CPRI4,
+	CPRI5,
+	CPRI6,
+	CPRI7,
+	CPRI8,
+	XAUI_FM1_MAC9,
+	XAUI_FM1_MAC10,
+	XAUI_FM2_MAC9,
+	XAUI_FM2_MAC10,
+	HIGIG_FM1_MAC9,
+	HIGIG_FM1_MAC10,
+	HIGIG_FM2_MAC9,
+	HIGIG_FM2_MAC10,
+	QSGMII_FM1_A,		/* A indicates MACs 1,2,5,6 */
+	QSGMII_FM1_B,		/* B indicates MACs 5,6,9,10 */
+	QSGMII_FM2_A,
+	QSGMII_FM2_B,
+	XFI_FM1_MAC1,
+	XFI_FM1_MAC2,
+	XFI_FM1_MAC9,
+	XFI_FM1_MAC10,
+	XFI_FM2_MAC9,
+	XFI_FM2_MAC10,
+	INTERLAKEN,
+	QSGMII_SW1_A,		/* Indicates ports on L2 Switch */
+	QSGMII_SW1_B,
+	SGMII_2500_FM1_DTSEC1,
+	SGMII_2500_FM1_DTSEC2,
+	SGMII_2500_FM1_DTSEC3,
+	SGMII_2500_FM1_DTSEC4,
+	SGMII_2500_FM1_DTSEC5,
+	SGMII_2500_FM1_DTSEC6,
+	SGMII_2500_FM1_DTSEC9,
+	SGMII_2500_FM1_DTSEC10,
+	SGMII_2500_FM2_DTSEC1,
+	SGMII_2500_FM2_DTSEC2,
+	SGMII_2500_FM2_DTSEC3,
+	SGMII_2500_FM2_DTSEC4,
+	SGMII_2500_FM2_DTSEC5,
+	SGMII_2500_FM2_DTSEC6,
+	SGMII_2500_FM2_DTSEC9,
+	SGMII_2500_FM2_DTSEC10,
+	TX_CLK,
+	SERDES_PRCTL_COUNT
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+};
+
+#endif
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_get_number(int serdes, int cfg);
+void fsl_rgmii_init(void);
+
+#ifdef CONFIG_FSL_LSCH2
+const char *serdes_clock_to_string(u32 clock);
+int get_serdes_protocol(void);
+#endif
+#ifdef CONFIG_SYS_HAS_SERDES
+/* Get the volt of SVDD in unit mV */
+int get_serdes_volt(void);
+/* Set the volt of SVDD in unit mV */
+int set_serdes_volt(int svdd);
+/* The target volt of SVDD in unit mV */
+int setup_serdes_volt(u32 svdd);
+#endif
+
+#endif /* __FSL_SERDES_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
new file mode 100644
index 0000000..862ec2e
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -0,0 +1,709 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_FSL_LSCH2_IMMAP_H__
+#define __ARCH_FSL_LSCH2_IMMAP_H__
+
+#include <fsl_immap.h>
+
+#define CONFIG_SYS_IMMR				0x01000000
+#define CONFIG_SYS_DCSRBAR			0x20000000
+#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00140000)
+#define CONFIG_SYS_DCSR_COP_CCP_ADDR	(CONFIG_SYS_DCSRBAR + 0x02008040)
+
+#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_GIC400_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
+#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
+#define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x00550000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
+#define CONFIG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
+#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00ee00b0)
+#define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_BMAN_ADDR		(CONFIG_SYS_IMMR + 0x00890000)
+#define CONFIG_SYS_FSL_QMAN_ADDR		(CONFIG_SYS_IMMR + 0x00880000)
+#define CONFIG_SYS_FSL_FMAN_ADDR		(CONFIG_SYS_IMMR + 0x00a00000)
+#define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
+#define CONFIG_SYS_FSL_DCFG_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_CLK_ADDR			(CONFIG_SYS_IMMR + 0x00ee1000)
+#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
+#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
+#define CONFIG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
+#define CONFIG_SYS_NS16550_COM4			(CONFIG_SYS_IMMR + 0x011d0600)
+#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_EHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x07600000)
+#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
+#define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
+
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0x508000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	(0xf00000000ull + \
+						CONFIG_SYS_BMAN_MEM_BASE)
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x08000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x10000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x10000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0x3E80
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0x500000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x08000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x10000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x10000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0x3680
+
+#define CONFIG_SYS_FSL_TIMER_ADDR		0x02b00000
+
+#define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
+#define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01190000)
+#define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011a0000)
+#define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011b0000)
+
+#define WDOG1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01ad0000)
+
+#define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
+#define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
+
+#define GPIO1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1300000)
+#define GPIO2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1310000)
+#define GPIO3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1320000)
+#define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1330000)
+
+#define QE_BASE_ADDR				(CONFIG_SYS_IMMR + 0x1400000)
+
+#define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
+
+#define EDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01c00000)
+
+#define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
+
+#define QDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x07380000)
+#define QMAN_CQSIDR_REG				0x20a80
+
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
+/* LUT registers */
+#ifdef CONFIG_ARCH_LS1012A
+#define PCIE_LUT_BASE				0xC0000
+#else
+#define PCIE_LUT_BASE				0x10000
+#endif
+#define PCIE_LUT_LCTRL0				0x7F8
+#define PCIE_LUT_DBG				0x7FC
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE			0x01100000	/* as per CCSR map. */
+#define TZASC2_BASE			0x01110000	/* as per CCSR map. */
+#define TZASC3_BASE			0x01120000	/* as per CCSR map. */
+#define TZASC4_BASE			0x01130000	/* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x)	((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x)		((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x)		((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
+#define TP_ITYP_AV              0x00000001      /* Initiator available */
+#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
+#define TP_ITYP_TYPE_ARM        0x0
+#define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
+#define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
+#define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
+#define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
+#define TY_ITYP_VER_A7          0x1
+#define TY_ITYP_VER_A53         0x2
+#define TY_ITYP_VER_A57         0x3
+#define TY_ITYP_VER_A72		0x4
+
+#define TP_CLUSTER_EOC		0xc0000000      /* end of clusters */
+#define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
+#define TP_INIT_PER_CLUSTER     4
+
+/*
+ * Define default values for some CCSR macros to make header files cleaner*
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
+CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR		0x01000000
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	0x01000000
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
+struct sys_info {
+	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	/* frequency of platform PLL */
+	unsigned long freq_systembus;
+	unsigned long freq_ddrbus;
+	unsigned long freq_localbus;
+	unsigned long freq_cga_m2;
+#ifdef CONFIG_SYS_DPAA_FMAN
+	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+#endif
+	unsigned long freq_qman;
+};
+
+#define CONFIG_SYS_FSL_FM1_OFFSET		0xa00000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0xa88000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0xa89000
+#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0xa8a000
+#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0xa8b000
+#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0xa8c000
+#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET	0xa8d000
+
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0xae0000
+#define CONFIG_SYS_FSL_FM1_ADDR			\
+		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
+#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR		\
+		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x700000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x710000ull
+#define FSL_SEC_JR0_OFFSET			CONFIG_SYS_FSL_JR0_OFFSET
+#define FSL_SEC_JR1_OFFSET			0x720000ull
+#define FSL_SEC_JR2_OFFSET			0x730000ull
+#define FSL_SEC_JR3_OFFSET			0x740000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
+#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
+#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
+#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
+
+/* Device Configuration and Pin Control */
+#define DCFG_DCSR_PORCR1		0x0
+#define DCFG_DCSR_ECCCR2		0x524
+#define DISABLE_PFE_ECC			BIT(13)
+
+struct ccsr_gur {
+	u32     porsr1;         /* POR status 1 */
+#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK	0xFF800000
+	u32     porsr2;         /* POR status 2 */
+	u8      res_008[0x20-0x8];
+	u32     gpporcr1;       /* General-purpose POR configuration */
+	u32	gpporcr2;
+#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT	25
+#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK	0x1F
+#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT	20
+#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK	0x1F
+	u32     dcfg_fusesr;    /* Fuse status register */
+	u8      res_02c[0x70-0x2c];
+	u32     devdisr;        /* Device disable control */
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1	0x80000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2	0x40000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3	0x20000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4	0x10000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5	0x08000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6	0x04000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9	0x00800000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10	0x00400000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_1	0x00800000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
+	u32     devdisr2;       /* Device disable control 2 */
+	u32     devdisr3;       /* Device disable control 3 */
+	u32     devdisr4;       /* Device disable control 4 */
+	u32     devdisr5;       /* Device disable control 5 */
+	u32     devdisr6;       /* Device disable control 6 */
+	u32     devdisr7;       /* Device disable control 7 */
+	u8      res_08c[0x94-0x8c];
+	u32     coredisru;      /* uppper portion for support of 64 cores */
+	u32     coredisrl;      /* lower portion for support of 64 cores */
+	u8      res_09c[0xa0-0x9c];
+	u32     pvr;            /* Processor version */
+	u32     svr;            /* System version */
+	u32     mvr;            /* Manufacturing version */
+	u8	res_0ac[0xb0-0xac];
+	u32	rstcr;		/* Reset control */
+	u32	rstrqpblsr;	/* Reset request preboot loader status */
+	u8	res_0b8[0xc0-0xb8];
+	u32	rstrqmr1;	/* Reset request mask */
+	u8	res_0c4[0xc8-0xc4];
+	u32	rstrqsr1;	/* Reset request status */
+	u8	res_0cc[0xd4-0xcc];
+	u32	rstrqwdtmrl;	/* Reset request WDT mask */
+	u8	res_0d8[0xdc-0xd8];
+	u32	rstrqwdtsrl;	/* Reset request WDT status */
+	u8	res_0e0[0xe4-0xe0];
+	u32	brrl;		/* Boot release */
+	u8      res_0e8[0x100-0xe8];
+	u32     rcwsr[16];      /* Reset control word status */
+#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT	25
+#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK	0x1f
+#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT	16
+#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK	0x3f
+#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK	0xffff0000
+#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT	16
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK	0x0000ffff
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT	0
+#define RCW_SB_EN_REG_INDEX	7
+#define RCW_SB_EN_MASK		0x00200000
+
+	u8      res_140[0x200-0x140];
+	u32     scratchrw[4];  /* Scratch Read/Write */
+	u8      res_210[0x300-0x210];
+	u32     scratchw1r[4];  /* Scratch Read (Write once) */
+	u8      res_310[0x400-0x310];
+	u32	crstsr[12];
+	u8	res_430[0x500-0x430];
+
+	/* PCI Express n Logical I/O Device Number register */
+	u32 dcfg_ccsr_pex1liodnr;
+	u32 dcfg_ccsr_pex2liodnr;
+	u32 dcfg_ccsr_pex3liodnr;
+	u32 dcfg_ccsr_pex4liodnr;
+	/* RIO n Logical I/O Device Number register */
+	u32 dcfg_ccsr_rio1liodnr;
+	u32 dcfg_ccsr_rio2liodnr;
+	u32 dcfg_ccsr_rio3liodnr;
+	u32 dcfg_ccsr_rio4liodnr;
+	/* USB Logical I/O Device Number register */
+	u32 dcfg_ccsr_usb1liodnr;
+	u32 dcfg_ccsr_usb2liodnr;
+	u32 dcfg_ccsr_usb3liodnr;
+	u32 dcfg_ccsr_usb4liodnr;
+	/* SD/MMC Logical I/O Device Number register */
+	u32 dcfg_ccsr_sdmmc1liodnr;
+	u32 dcfg_ccsr_sdmmc2liodnr;
+	u32 dcfg_ccsr_sdmmc3liodnr;
+	u32 dcfg_ccsr_sdmmc4liodnr;
+	/* RIO Message Unit Logical I/O Device Number register */
+	u32 dcfg_ccsr_riomaintliodnr;
+
+	u8      res_544[0x550-0x544];
+	u32	sataliodnr[4];
+	u8	res_560[0x570-0x560];
+
+	u32 dcfg_ccsr_misc1liodnr;
+	u32 dcfg_ccsr_misc2liodnr;
+	u32 dcfg_ccsr_misc3liodnr;
+	u32 dcfg_ccsr_misc4liodnr;
+	u32 dcfg_ccsr_dma1liodnr;
+	u32 dcfg_ccsr_dma2liodnr;
+	u32 dcfg_ccsr_dma3liodnr;
+	u32 dcfg_ccsr_dma4liodnr;
+	u32 dcfg_ccsr_spare1liodnr;
+	u32 dcfg_ccsr_spare2liodnr;
+	u32 dcfg_ccsr_spare3liodnr;
+	u32 dcfg_ccsr_spare4liodnr;
+	u8	res_5a0[0x600-0x5a0];
+	u32 dcfg_ccsr_pblsr;
+
+	u32	pamubypenr;
+	u32	dmacr1;
+
+	u8	res_60c[0x610-0x60c];
+	u32 dcfg_ccsr_gensr1;
+	u32 dcfg_ccsr_gensr2;
+	u32 dcfg_ccsr_gensr3;
+	u32 dcfg_ccsr_gensr4;
+	u32 dcfg_ccsr_gencr1;
+	u32 dcfg_ccsr_gencr2;
+	u32 dcfg_ccsr_gencr3;
+	u32 dcfg_ccsr_gencr4;
+	u32 dcfg_ccsr_gencr5;
+	u32 dcfg_ccsr_gencr6;
+	u32 dcfg_ccsr_gencr7;
+	u8	res_63c[0x658-0x63c];
+	u32 dcfg_ccsr_cgensr1;
+	u32 dcfg_ccsr_cgensr0;
+	u8	res_660[0x678-0x660];
+	u32 dcfg_ccsr_cgencr1;
+
+	u32 dcfg_ccsr_cgencr0;
+	u8	res_680[0x700-0x680];
+	u32 dcfg_ccsr_sriopstecr;
+	u32 dcfg_ccsr_dcsrcr;
+
+	u8      res_708[0x740-0x708];   /* add more registers when needed */
+	u32     tp_ityp[64];    /* Topology Initiator Type Register */
+	struct {
+		u32     upper;
+		u32     lower;
+	} tp_cluster[16];
+	u8      res_8c0[0xa00-0x8c0];   /* add more registers when needed */
+	u32 dcfg_ccsr_qmbm_warmrst;
+	u8      res_a04[0xa20-0xa04];   /* add more registers when needed */
+	u32 dcfg_ccsr_reserved0;
+	u32 dcfg_ccsr_reserved1;
+};
+
+#define SCFG_QSPI_CLKSEL		0x40100000
+#define SCFG_USBDRVVBUS_SELCR_USB1	0x00000000
+#define SCFG_USBDRVVBUS_SELCR_USB2	0x00000001
+#define SCFG_USBDRVVBUS_SELCR_USB3	0x00000002
+#define SCFG_USBPWRFAULT_INACTIVE	0x00000000
+#define SCFG_USBPWRFAULT_SHARED		0x00000001
+#define SCFG_USBPWRFAULT_DEDICATED	0x00000002
+#define SCFG_USBPWRFAULT_USB3_SHIFT	4
+#define SCFG_USBPWRFAULT_USB2_SHIFT	2
+#define SCFG_USBPWRFAULT_USB1_SHIFT	0
+
+#define SCFG_BASE			0x01570000
+#define SCFG_USB3PRM1CR_USB1		0x070
+#define SCFG_USB3PRM2CR_USB1		0x074
+#define SCFG_USB3PRM1CR_USB2		0x07C
+#define SCFG_USB3PRM2CR_USB2		0x080
+#define SCFG_USB3PRM1CR_USB3		0x088
+#define SCFG_USB3PRM2CR_USB3		0x08c
+#define SCFG_USB_TXVREFTUNE			0x9
+#define SCFG_USB_SQRXTUNE_MASK		0x7
+#define SCFG_USB_PCSTXSWINGFULL		0x47
+#define SCFG_USB_PHY1			0x084F0000
+#define SCFG_USB_PHY2			0x08500000
+#define SCFG_USB_PHY3			0x08510000
+#define SCFG_USB_PHY_RX_OVRD_IN_HI		0x200c
+#define USB_PHY_RX_EQ_VAL_1		0x0000
+#define USB_PHY_RX_EQ_VAL_2		0x0080
+#define USB_PHY_RX_EQ_VAL_3		0x0380
+#define USB_PHY_RX_EQ_VAL_4		0x0b80
+
+#define SCFG_SNPCNFGCR_SECRDSNP		0x80000000
+#define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
+#define SCFG_SNPCNFGCR_SATARDSNP	0x00800000
+#define SCFG_SNPCNFGCR_SATAWRSNP	0x00400000
+#define SCFG_SNPCNFGCR_USB1RDSNP	0x00200000
+#define SCFG_SNPCNFGCR_USB1WRSNP	0x00100000
+#define SCFG_SNPCNFGCR_USB2RDSNP	0x00008000
+#define SCFG_SNPCNFGCR_USB2WRSNP	0x00010000
+#define SCFG_SNPCNFGCR_USB3RDSNP	0x00002000
+#define SCFG_SNPCNFGCR_USB3WRSNP	0x00004000
+
+/* RGMIIPCR bit definitions*/
+#define SCFG_RGMIIPCR_EN_AUTO		BIT(3)
+#define SCFG_RGMIIPCR_SETSP_1000M	BIT(2)
+#define SCFG_RGMIIPCR_SETSP_100M	0
+#define SCFG_RGMIIPCR_SETSP_10M		BIT(1)
+#define SCFG_RGMIIPCR_SETFD		BIT(0)
+
+/* PFEASBCR bit definitions */
+#define SCFG_PFEASBCR_ARCACHE0		BIT(31)
+#define SCFG_PFEASBCR_AWCACHE0		BIT(30)
+#define SCFG_PFEASBCR_ARCACHE1		BIT(29)
+#define SCFG_PFEASBCR_AWCACHE1		BIT(28)
+#define SCFG_PFEASBCR_ARSNP		BIT(27)
+#define SCFG_PFEASBCR_AWSNP		BIT(26)
+
+/* WR_QoS1 PFE bit definitions */
+#define SCFG_WR_QOS1_PFE1_QOS		GENMASK(27, 24)
+#define SCFG_WR_QOS1_PFE2_QOS		GENMASK(23, 20)
+
+/* RD_QoS1 PFE bit definitions */
+#define SCFG_RD_QOS1_PFE1_QOS		GENMASK(27, 24)
+#define SCFG_RD_QOS1_PFE2_QOS		GENMASK(23, 20)
+
+/* Supplemental Configuration Unit */
+struct ccsr_scfg {
+	u8 res_000[0x100-0x000];
+	u32 usb2_icid;
+	u32 usb3_icid;
+	u8 res_108[0x114-0x108];
+	u32 dma_icid;
+	u32 sata_icid;
+	u32 usb1_icid;
+	u32 qe_icid;
+	u32 sdhc_icid;
+	u32 edma_icid;
+	u32 etr_icid;
+	u32 core_sft_rst[4];
+	u8 res_140[0x158-0x140];
+	u32 altcbar;
+	u32 qspi_cfg;
+	u8 res_160[0x164 - 0x160];
+	u32 wr_qos1;
+	u32 wr_qos2;
+	u32 rd_qos1;
+	u32 rd_qos2;
+	u8 res_174[0x180 - 0x174];
+	u32 dmamcr;
+	u8 res_184[0x188-0x184];
+	u32 gic_align;
+	u32 debug_icid;
+	u8 res_190[0x1a4-0x190];
+	u32 snpcnfgcr;
+	u8 res_1a8[0x1ac-0x1a8];
+	u32 intpcr;
+	u8 res_1b0[0x204-0x1b0];
+	u32 coresrencr;
+	u8 res_208[0x220-0x208];
+	u32 rvbar0_0;
+	u32 rvbar0_1;
+	u32 rvbar1_0;
+	u32 rvbar1_1;
+	u32 rvbar2_0;
+	u32 rvbar2_1;
+	u32 rvbar3_0;
+	u32 rvbar3_1;
+	u32 lpmcsr;
+	u8 res_244[0x400-0x244];
+	u32 qspidqscr;
+	u32 ecgtxcmcr;
+	u32 sdhciovselcr;
+	u32 rcwpmuxcr0;
+	u32 usbdrvvbus_selcr;
+	u32 usbpwrfault_selcr;
+	u32 usb_refclk_selcr1;
+	u32 usb_refclk_selcr2;
+	u32 usb_refclk_selcr3;
+	u8 res_424[0x434 - 0x424];
+	u32 rgmiipcr;
+	u32 res_438;
+	u32 rgmiipsr;
+	u32 pfepfcssr1;
+	u32 pfeintencr1;
+	u32 pfepfcssr2;
+	u32 pfeintencr2;
+	u32 pfeerrcr;
+	u32 pfeeerrintencr;
+	u32 pfeasbcr;
+	u32 pfebsbcr;
+	u8 res_460[0x484 - 0x460];
+	u32 mdioselcr;
+	u8 res_468[0x600 - 0x488];
+	u32 scratchrw[4];
+	u8 res_610[0x680-0x610];
+	u32 corebcr;
+	u8 res_684[0x1000-0x684];
+	u32 pex1msiir;
+	u32 pex1msir;
+	u8 res_1008[0x2000-0x1008];
+	u32 pex2;
+	u32 pex2msir;
+	u8 res_2008[0x3000-0x2008];
+	u32 pex3msiir;
+	u32 pex3msir;
+};
+
+/* Clocking */
+struct ccsr_clk {
+	struct {
+		u32 clkcncsr;	/* core cluster n clock control status */
+		u8  res_004[0x0c];
+		u32 clkcghwacsr; /* Clock generator n hardware accelerator */
+		u8  res_014[0x0c];
+	} clkcsr[4];
+	u8	res_040[0x780]; /* 0x100 */
+	struct {
+		u32 pllcngsr;
+		u8 res_804[0x1c];
+	} pllcgsr[2];
+	u8	res_840[0x1c0];
+	u32	clkpcsr;	/* 0xa00 Platform clock domain control/status */
+	u8	res_a04[0x1fc];
+	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
+	u8	res_c04[0x1c];
+	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
+	u8	res_c24[0x3dc];
+};
+
+/* System Counter */
+struct sctr_regs {
+	u32 cntcr;
+	u32 cntsr;
+	u32 cntcv1;
+	u32 cntcv2;
+	u32 resv1[4];
+	u32 cntfid0;
+	u32 cntfid1;
+	u32 resv2[1002];
+	u32 counterid[12];
+};
+
+#define SRDS_MAX_LANES		4
+struct ccsr_serdes {
+	struct {
+		u32	rstctl;	/* Reset Control Register */
+#define SRDS_RSTCTL_RST		0x80000000
+#define SRDS_RSTCTL_RSTDONE	0x40000000
+#define SRDS_RSTCTL_RSTERR	0x20000000
+#define SRDS_RSTCTL_SWRST	0x10000000
+#define SRDS_RSTCTL_SDEN	0x00000020
+#define SRDS_RSTCTL_SDRST_B	0x00000040
+#define SRDS_RSTCTL_PLLRST_B	0x00000080
+		u32	pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF		0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_PLL_LCK		0x00800000
+#define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
+		u32	pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL	0x08000000
+		u32	res_0c;	/* 0x00c */
+		u32	pllcr3;
+		u32	pllcr4;
+		u32	pllcr5; /* 0x018 SerDes PLL1 Control 5 */
+		u8	res_1c[0x20-0x1c];
+	} bank[2];
+	u8	res_40[0x90-0x40];
+	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
+	u8	res_94[0xa0-0x94];
+	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
+	u8	res_a4[0xb0-0xa4];
+	u32	srdsgr0;	/* 0xb0 General Register 0 */
+	u8	res_b4[0x100-0xb4];
+	struct {
+		u32	lnpssr0;	/* 0x100, 0x120, 0x140, 0x160 */
+		u8	res_104[0x120-0x104];
+	} lnpssr[4];	/* Lane A, B, C, D */
+	u8	res_180[0x200-0x180];
+	u32	srdspccr0;	/* 0x200 Protocol Configuration 0 */
+	u32	srdspccr1;	/* 0x204 Protocol Configuration 1 */
+	u32	srdspccr2;	/* 0x208 Protocol Configuration 2 */
+	u32	srdspccr3;	/* 0x20c Protocol Configuration 3 */
+	u32	srdspccr4;	/* 0x210 Protocol Configuration 4 */
+	u32	srdspccr5;	/* 0x214 Protocol Configuration 5 */
+	u32	srdspccr6;	/* 0x218 Protocol Configuration 6 */
+	u32	srdspccr7;	/* 0x21c Protocol Configuration 7 */
+	u32	srdspccr8;	/* 0x220 Protocol Configuration 8 */
+	u32	srdspccr9;	/* 0x224 Protocol Configuration 9 */
+	u32	srdspccra;	/* 0x228 Protocol Configuration A */
+	u32	srdspccrb;	/* 0x22c Protocol Configuration B */
+	u8	res_230[0x800-0x230];
+	struct {
+		u32	gcr0;	/* 0x800 General Control Register 0 */
+		u32	gcr1;	/* 0x804 General Control Register 1 */
+		u32	gcr2;	/* 0x808 General Control Register 2 */
+		u32	sscr0;
+		u32	recr0;	/* 0x810 Receive Equalization Control */
+		u32	recr1;
+		u32	tecr0;	/* 0x818 Transmit Equalization Control */
+		u32	sscr1;
+		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
+		u8	res_824[0x83c-0x824];
+		u32	tcsr3;
+	} lane[4];	/* Lane A, B, C, D */
+	u8	res_900[0x1000-0x900];	/* from 0x900 to 0xfff */
+	struct {
+		u32	srdspexcr0;	/* 0x1000, 0x1040, 0x1080 */
+		u8	res_1004[0x1040-0x1004];
+	} pcie[3];
+	u8	res_10c0[0x1800-0x10c0];
+	struct {
+		u8	res_1800[0x1804-0x1800];
+		u32	srdssgmiicr1;	/* 0x1804 SGMII Protocol Control 1 */
+		u8	res_1808[0x180c-0x1808];
+		u32	srdssgmiicr3;	/* 0x180c SGMII Protocol Control 3 */
+	} sgmii[4];	/* Lane A, B, C, D */
+	u8	res_1840[0x1880-0x1840];
+	struct {
+		u8	res_1880[0x1884-0x1880];
+		u32	srdsqsgmiicr1;	/* 0x1884 QSGMII Protocol Control 1 */
+		u8	res_1888[0x188c-0x1888];
+		u32	srdsqsgmiicr3;	/* 0x188c QSGMII Protocol Control 3 */
+	} qsgmii[2];	/* Lane A, B */
+	u8	res_18a0[0x1980-0x18a0];
+	struct {
+		u8	res_1980[0x1984-0x1980];
+		u32	srdsxficr1;	/* 0x1984 XFI Protocol Control 1 */
+		u8	res_1988[0x198c-0x1988];
+		u32	srdsxficr3;	/* 0x198c XFI Protocol Control 3 */
+	} xfi[2];	/* Lane A, B */
+	u8	res_19a0[0x2000-0x19a0];	/* from 0x19a0 to 0x1fff */
+};
+
+struct ccsr_gpio {
+	u32	gpdir;
+	u32	gpodr;
+	u32	gpdat;
+	u32	gpier;
+	u32	gpimr;
+	u32	gpicr;
+	u32	gpibe;
+};
+
+/* MMU 500 */
+#define SMMU_SCR0			(SMMU_BASE + 0x0)
+#define SMMU_SCR1			(SMMU_BASE + 0x4)
+#define SMMU_SCR2			(SMMU_BASE + 0x8)
+#define SMMU_SACR			(SMMU_BASE + 0x10)
+#define SMMU_IDR0			(SMMU_BASE + 0x20)
+#define SMMU_IDR1			(SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0			(SMMU_BASE + 0x400)
+#define SMMU_NSCR2			(SMMU_BASE + 0x408)
+#define SMMU_NSACR			(SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK		0x00000001
+#define SCR0_USFCFG_MASK		0x00000400
+
+#ifdef CONFIG_TFABOOT
+#define RCW_SRC_MASK			(0xFF800000)
+#define RCW_SRC_BIT			23
+
+/* RCW SRC NAND */
+#define RCW_SRC_NAND_MASK		(0x100)
+#define RCW_SRC_NAND_VAL		(0x100)
+#define NAND_RESERVED_MASK		(0xFC)
+#define NAND_RESERVED_1			(0x0)
+#define NAND_RESERVED_2			(0x80)
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_MASK		(0x1F0)
+#define NOR_8B_VAL			(0x10)
+#define NOR_16B_VAL			(0x20)
+#define SD_VAL				(0x40)
+#define QSPI_VAL1			(0x44)
+#define QSPI_VAL2			(0x45)
+#endif
+
+uint get_svr(void);
+
+#endif	/* __ARCH_FSL_LSCH2_IMMAP_H__*/
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
new file mode 100644
index 0000000..4f05047
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -0,0 +1,572 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * LayerScape Internal Memory Map
+ *
+ * Copyright 2017-2019 NXP
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
+#define __ARCH_FSL_LSCH3_IMMAP_H_
+
+#define CONFIG_SYS_IMMR				0x01000000
+#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
+#define CONFIG_SYS_FSL_DDR3_ADDR		0x08210000
+#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
+#define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
+#ifdef CONFIG_ARCH_LX2160A
+#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00e88180)
+#else
+#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
+#endif
+#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
+#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
+#define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x010c0000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
+#define FSL_ESDHC1_BASE_ADDR			CONFIG_SYS_FSL_ESDHC_ADDR
+#define FSL_ESDHC2_BASE_ADDR			(CONFIG_SYS_IMMR + 0x01150000)
+#ifndef CONFIG_NXP_LSCH3_2
+#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
+#endif
+#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
+#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
+#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR	0x023d0000
+#define CONFIG_SYS_FSL_TIMER_ADDR		0x023e0000
+#define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
+						 0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
+#define FSL_LSCH3_SVR		(CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
+
+#define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
+
+#define CONFIG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR		0x700133000ULL
+
+#define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01000000)
+#define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
+#define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
+#define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
+#ifdef CONFIG_NXP_LSCH3_2
+#define I2C5_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01040000)
+#define I2C6_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01050000)
+#define I2C7_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01060000)
+#define I2C8_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01070000)
+#endif
+#define GPIO4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01330000)
+#define GPIO4_GPDIR_ADDR			(GPIO4_BASE_ADDR + 0x0)
+#define GPIO4_GPDAT_ADDR			(GPIO4_BASE_ADDR + 0x8)
+
+#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02110000)
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE			0x01100000	/* as per CCSR map. */
+#define TZASC2_BASE			0x01110000	/* as per CCSR map. */
+#define TZASC3_BASE			0x01120000	/* as per CCSR map. */
+#define TZASC4_BASE			0x01130000	/* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x)	((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x)		((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x)		((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
+/* EDMA */
+#define EDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x012c0000)
+
+/* SATA */
+#define AHCI_BASE_ADDR1				(CONFIG_SYS_IMMR + 0x02200000)
+#define AHCI_BASE_ADDR2				(CONFIG_SYS_IMMR + 0x02210000)
+
+/* QDMA */
+#define QDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x07380000)
+#define QMAN_CQSIDR_REG				0x20a80
+
+/* DISPLAY */
+#define DISPLAY_BASE_ADDR			(CONFIG_SYS_IMMR + 0x0e080000)
+
+/* GPU */
+#define GPU_BASE_ADDR				(CONFIG_SYS_IMMR + 0x0e0c0000)
+
+/* SFP */
+#define CONFIG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
+
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x07000000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x07010000ull
+#define FSL_SEC_JR0_OFFSET			CONFIG_SYS_FSL_JR0_OFFSET
+#define FSL_SEC_JR1_OFFSET			0x07020000ull
+#define FSL_SEC_JR2_OFFSET			0x07030000ull
+#define FSL_SEC_JR3_OFFSET			0x07040000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
+#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
+#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
+#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET)
+
+#ifdef CONFIG_TFABOOT
+#ifdef CONFIG_NXP_LSCH3_2
+/* RCW_SRC field in Power-On Reset Control Register 1 */
+#define RCW_SRC_MASK			0x07800000
+#define RCW_SRC_BIT			23
+
+/* CFG_RCW_SRC[3:0] */
+#define RCW_SRC_TYPE_MASK		0x8
+#define RCW_SRC_ADDR_OFFSET_8MB		0x800000
+
+/* RCW SRC HARDCODED */
+#define RCW_SRC_HARDCODED_VAL		0x0	/* 0x00 - 0x07 */
+
+#define RCW_SRC_SDHC1_VAL		0x8	/* 0x8 */
+#define RCW_SRC_SDHC2_VAL		0x9	/* 0x9 */
+#define RCW_SRC_I2C1_VAL		0xa	/* 0xa */
+#define RCW_SRC_RESERVED_UART_VAL	0xb	/* 0xb */
+#define RCW_SRC_FLEXSPI_NAND2K_VAL	0xc	/* 0xc */
+#define RCW_SRC_FLEXSPI_NAND4K_VAL	0xd	/* 0xd */
+#define RCW_SRC_RESERVED_1_VAL		0xe	/* 0xe */
+#define RCW_SRC_FLEXSPI_NOR_24B		0xf	/* 0xf */
+#else
+#define RCW_SRC_MASK			(0xFF800000)
+#define RCW_SRC_BIT			23
+/* CFG_RCW_SRC[6:0] */
+#define RCW_SRC_TYPE_MASK               (0x70)
+
+/* RCW SRC HARDCODED */
+#define RCW_SRC_HARDCODED_VAL           (0x10)     /* 0x10 - 0x1f */
+/* Hardcoded will also have CFG_RCW_SRC[7] as 1.   0x90 - 0x9f */
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_VAL                 (0x20)
+#define NOR_TYPE_MASK                   (0x10)
+#define NOR_16B_VAL                     (0x0)       /* 0x20 - 0x2f */
+#define NOR_32B_VAL                     (0x10)       /* 0x30 - 0x3f */
+
+/* RCW SRC Serial Flash
+ * 1. SERIAL NOR (QSPI)
+ * 2. OTHERS (SD/MMC, SPI, I2C1
+ */
+#define RCW_SRC_SERIAL_MASK             (0x7F)
+#define RCW_SRC_QSPI_VAL                (0x62)     /* 0x62 */
+#define RCW_SRC_SD_CARD_VAL             (0x40)     /* 0x40 */
+#define RCW_SRC_EMMC_VAL                (0x41)     /* 0x41 */
+#define RCW_SRC_I2C1_VAL                (0x49)     /* 0x49 */
+#endif
+#endif
+
+/* Security Monitor */
+#define CONFIG_SYS_SEC_MON_ADDR		(CONFIG_SYS_IMMR + 0x00e90000)
+
+/* MMU 500 */
+#define SMMU_SCR0			(SMMU_BASE + 0x0)
+#define SMMU_SCR1			(SMMU_BASE + 0x4)
+#define SMMU_SCR2			(SMMU_BASE + 0x8)
+#define SMMU_SACR			(SMMU_BASE + 0x10)
+#define SMMU_IDR0			(SMMU_BASE + 0x20)
+#define SMMU_IDR1			(SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0			(SMMU_BASE + 0x400)
+#define SMMU_NSCR2			(SMMU_BASE + 0x408)
+#define SMMU_NSACR			(SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK		0x00000001
+#define SCR0_USFCFG_MASK		0x00000400
+
+
+/* PCIe */
+#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_PCIE4_ADDR			(CONFIG_SYS_IMMR + 0x2700000)
+#ifdef CONFIG_ARCH_LX2160A
+#define SYS_PCIE5_ADDR				(CONFIG_SYS_IMMR + 0x2800000)
+#define SYS_PCIE6_ADDR				(CONFIG_SYS_IMMR + 0x2900000)
+#endif
+
+#ifdef CONFIG_ARCH_LX2160A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x9000000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR		0x9800000000ULL
+#define SYS_PCIE5_PHYS_ADDR			0xa000000000ULL
+#define SYS_PCIE6_PHYS_ADDR			0xa800000000ULL
+#elif CONFIG_ARCH_LS1088A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x2000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x2800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x3000000000ULL
+#elif CONFIG_ARCH_LS1028A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x8000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x8800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x01f0000000ULL
+/* this is used by integrated PCI on LS1028, includes ECAM and register space */
+#define CONFIG_SYS_PCIE3_PHYS_SIZE		0x0010000000ULL
+#else
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
+#endif
+
+/* Device Configuration */
+#define DCFG_BASE		0x01e00000
+#define DCFG_PORSR1			0x000
+#define DCFG_PORSR1_RCW_SRC		0xff800000
+#define DCFG_PORSR1_RCW_SRC_NOR		0x12f00000
+#define DCFG_RCWSR13			0x130
+#define DCFG_RCWSR13_DSPI		(0 << 8)
+#define DCFG_RCWSR15			0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI	0x3
+
+#define DCFG_DCSR_BASE		0X700100000ULL
+#define DCFG_DCSR_PORCR1		0x000
+
+/* Interrupt Sampling Control */
+#define ISC_BASE		0x01F70000
+#define IRQCR_OFFSET		0x14
+
+/* Supplemental Configuration */
+#define SCFG_BASE		0x01fc0000
+#define SCFG_USB3PRM1CR			0x000
+#define SCFG_USB3PRM1CR_INIT		0x27672b2a
+#define SCFG_USB_TXVREFTUNE		0x9
+#define SCFG_USB_SQRXTUNE_MASK	0x7
+#define SCFG_QSPICLKCTLR	0x10
+
+#define DCSR_BASE		0x700000000ULL
+#define DCSR_USB_PHY1			0x4600000
+#define DCSR_USB_PHY2			0x4610000
+#define DCSR_USB_PHY_RX_OVRD_IN_HI	0x200C
+#define USB_PHY_RX_EQ_VAL_1		0x0000
+#define USB_PHY_RX_EQ_VAL_2		0x0080
+#define USB_PHY_RX_EQ_VAL_3		0x0380
+#define USB_PHY_RX_EQ_VAL_4		0x0b80
+#define DCSR_USB_IOCR1			0x108004
+#define DCSR_USB_PCSTXSWINGFULL	0x71
+
+#define TP_ITYP_AV		0x00000001	/* Initiator available */
+#define TP_ITYP_TYPE(x)	(((x) & 0x6) >> 1)	/* Initiator Type */
+#define TP_ITYP_TYPE_ARM	0x0
+#define TP_ITYP_TYPE_PPC	0x1		/* PowerPC */
+#define TP_ITYP_TYPE_OTHER	0x2		/* StarCore DSP */
+#define TP_ITYP_TYPE_HA		0x3		/* HW Accelerator */
+#define TP_ITYP_THDS(x)	(((x) & 0x18) >> 3)	/* # threads */
+#define TP_ITYP_VER(x)	(((x) & 0xe0) >> 5)	/* Initiator Version */
+#define TY_ITYP_VER_A7		0x1
+#define TY_ITYP_VER_A53		0x2
+#define TY_ITYP_VER_A57		0x3
+#define TY_ITYP_VER_A72		0x4
+
+#define TP_CLUSTER_EOC		0x80000000	/* end of clusters */
+#define TP_CLUSTER_INIT_MASK	0x0000003f	/* initiator mask */
+#define TP_INIT_PER_CLUSTER     4
+/* This is chassis generation 3 */
+#ifndef __ASSEMBLY__
+struct sys_info {
+	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	/* frequency of platform PLL */
+	unsigned long freq_systembus;
+	unsigned long freq_ddrbus;
+	unsigned long freq_cga_m2;
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+	unsigned long freq_ddrbus2;
+#endif
+	unsigned long freq_localbus;
+	unsigned long freq_qe;
+#ifdef CONFIG_SYS_DPAA_FMAN
+	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	unsigned long freq_qman;
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	unsigned long freq_pme;
+#endif
+};
+
+/* Global Utilities Block */
+struct ccsr_gur {
+	u32	porsr1;		/* POR status 1 */
+	u32	porsr2;		/* POR status 2 */
+	u8	res_008[0x20-0x8];
+	u32	gpporcr1;	/* General-purpose POR configuration */
+	u32	gpporcr2;	/* General-purpose POR configuration 2 */
+	u32	gpporcr3;
+	u32	gpporcr4;
+	u8	res_030[0x60-0x30];
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK	0x1F
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK	0x1F
+#if defined(CONFIG_ARCH_LS1088A)
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT	25
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT	20
+#else
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT	2
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT	7
+#endif
+	u32	dcfg_fusesr;	/* Fuse status register */
+	u8	res_064[0x70-0x64];
+	u32	devdisr;	/* Device disable control 1 */
+	u32	devdisr2;	/* Device disable control 2 */
+	u32	devdisr3;	/* Device disable control 3 */
+	u32	devdisr4;	/* Device disable control 4 */
+	u32	devdisr5;	/* Device disable control 5 */
+	u32	devdisr6;	/* Device disable control 6 */
+	u8	res_088[0x94-0x88];
+	u32	coredisr;	/* Device disable control 7 */
+#define FSL_CHASSIS3_DEVDISR2_DPMAC1	0x00000001
+#define FSL_CHASSIS3_DEVDISR2_DPMAC2	0x00000002
+#define FSL_CHASSIS3_DEVDISR2_DPMAC3	0x00000004
+#define FSL_CHASSIS3_DEVDISR2_DPMAC4	0x00000008
+#define FSL_CHASSIS3_DEVDISR2_DPMAC5	0x00000010
+#define FSL_CHASSIS3_DEVDISR2_DPMAC6	0x00000020
+#define FSL_CHASSIS3_DEVDISR2_DPMAC7	0x00000040
+#define FSL_CHASSIS3_DEVDISR2_DPMAC8	0x00000080
+#define FSL_CHASSIS3_DEVDISR2_DPMAC9	0x00000100
+#define FSL_CHASSIS3_DEVDISR2_DPMAC10	0x00000200
+#define FSL_CHASSIS3_DEVDISR2_DPMAC11	0x00000400
+#define FSL_CHASSIS3_DEVDISR2_DPMAC12	0x00000800
+#define FSL_CHASSIS3_DEVDISR2_DPMAC13	0x00001000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC14	0x00002000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC15	0x00004000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC16	0x00008000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC17	0x00010000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC18	0x00020000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC19	0x00040000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC20	0x00080000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC21	0x00100000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC22	0x00200000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC23	0x00400000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC24	0x00800000
+	u8	res_098[0xa0-0x98];
+	u32	pvr;		/* Processor version */
+	u32	svr;		/* System version */
+	u8	res_0a8[0x100-0xa8];
+	u32	rcwsr[30];	/* Reset control word status */
+
+#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT	2
+#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK	0x1f
+#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT	10
+#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK	0x3f
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT	18
+#define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK	0x3f
+
+#if defined(CONFIG_ARCH_LS2080A)
+#define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK	0x00FF0000
+#define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT	16
+#define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK	0xFF000000
+#define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT	24
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR	29
+#define FSL_CHASSIS3_SRDS2_REGSR	29
+#elif defined(CONFIG_ARCH_LX2160A)
+#define FSL_CHASSIS3_EC1_REGSR  27
+#define FSL_CHASSIS3_EC2_REGSR  27
+#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK	0x00000003
+#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT	0
+#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK	0x00000007
+#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT	2
+#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x001F0000
+#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
+#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0x03E00000
+#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  21
+#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK   0x7C000000
+#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT  26
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS3_PRTCL_MASK	FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR	29
+#define FSL_CHASSIS3_SRDS2_REGSR	29
+#define FSL_CHASSIS3_SRDS3_REGSR	29
+#define FSL_CHASSIS3_RCWSR12_REGSR         12
+#define FSL_CHASSIS3_RCWSR13_REGSR         13
+#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK  0x07000000
+#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
+#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK  0x00000038
+#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
+#define FSL_CHASSIS3_IIC5_PMUX_MASK        0x00000E00
+#define FSL_CHASSIS3_IIC5_PMUX_SHIFT       9
+#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_CHASSIS3_EC1_REGSR  26
+#define FSL_CHASSIS3_EC2_REGSR  26
+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK     0x00000007
+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT    0
+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK     0x00000038
+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT    3
+#define	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK	0xFFFF0000
+#define	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT	16
+#define	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK	0x0000FFFF
+#define	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT	0
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR	29
+#define FSL_CHASSIS3_SRDS2_REGSR	30
+#elif defined(CONFIG_ARCH_LS1028A)
+#define	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK	0xFFFF0000
+#define	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT	16
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR	29
+#endif
+#define RCW_SB_EN_REG_INDEX	9
+#define RCW_SB_EN_MASK		0x00000400
+
+	u8	res_178[0x200-0x178];
+	u32	scratchrw[16];	/* Scratch Read/Write */
+	u8	res_240[0x300-0x240];
+	u32	scratchw1r[4];	/* Scratch Read (Write once) */
+	u8	res_310[0x400-0x310];
+	u32	bootlocptrl;	/* Boot location pointer low-order addr */
+	u32	bootlocptrh;	/* Boot location pointer high-order addr */
+	u8	res_408[0x520-0x408];
+	u32	usb1_amqr;
+	u32	usb2_amqr;
+	u8	res_528[0x530-0x528];	/* add more registers when needed */
+	u32	sdmm1_amqr;
+	u32	sdmm2_amqr;
+	u8	res_538[0x550 - 0x538];	/* add more registers when needed */
+	u32	sata1_amqr;
+	u32	sata2_amqr;
+	u8	res_558[0x570-0x558];	/* add more registers when needed */
+	u32	misc1_amqr;
+	u8	res_574[0x590-0x574];	/* add more registers when needed */
+	u32	spare1_amqr;
+	u32	spare2_amqr;
+	u32	spare3_amqr;
+	u8	res_59c[0x620 - 0x59c];	/* add more registers when needed */
+	u32	gencr[7];	/* General Control Registers */
+	u8	res_63c[0x640-0x63c];	/* add more registers when needed */
+	u32	cgensr1;	/* Core General Status Register */
+	u8	res_644[0x660-0x644];	/* add more registers when needed */
+	u32	cgencr1;	/* Core General Control Register */
+	u8	res_664[0x740-0x664];	/* add more registers when needed */
+	u32	tp_ityp[64];	/* Topology Initiator Type Register */
+	struct {
+		u32	upper;
+		u32	lower;
+	} tp_cluster[4];	/* Core cluster n Topology Register */
+	u8	res_864[0x920-0x864];	/* add more registers when needed */
+	u32 ioqoscr[8];	/*I/O Quality of Services Register */
+	u32 uccr;
+	u8	res_944[0x960-0x944];	/* add more registers when needed */
+	u32 ftmcr;
+	u8	res_964[0x990-0x964];	/* add more registers when needed */
+	u32 coredisablesr;
+	u8	res_994[0xa00-0x994];	/* add more registers when needed */
+	u32 sdbgcr; /*Secure Debug Confifuration Register */
+	u8	res_a04[0xbf8-0xa04];	/* add more registers when needed */
+	u32 ipbrr1;
+	u32 ipbrr2;
+	u8	res_858[0x1000-0xc00];
+};
+
+struct ccsr_clk_cluster_group {
+	struct {
+		u8	res_00[0x10];
+		u32	csr;
+		u8	res_14[0x20-0x14];
+	} hwncsr[3];
+	u8	res_60[0x80-0x60];
+	struct {
+		u32	gsr;
+		u8	res_84[0xa0-0x84];
+	} pllngsr[3];
+	u8	res_e0[0x100-0xe0];
+};
+
+struct ccsr_clk_ctrl {
+	struct {
+		u32 csr;	/* core cluster n clock control status */
+		u8  res_04[0x20-0x04];
+	} clkcncsr[8];
+};
+
+struct ccsr_reset {
+	u32 rstcr;			/* 0x000 */
+	u32 rstcrsp;			/* 0x004 */
+	u8 res_008[0x10-0x08];		/* 0x008 */
+	u32 rstrqmr1;			/* 0x010 */
+	u32 rstrqmr2;			/* 0x014 */
+	u32 rstrqsr1;			/* 0x018 */
+	u32 rstrqsr2;			/* 0x01c */
+	u32 rstrqwdtmrl;		/* 0x020 */
+	u32 rstrqwdtmru;		/* 0x024 */
+	u8 res_028[0x30-0x28];		/* 0x028 */
+	u32 rstrqwdtsrl;		/* 0x030 */
+	u32 rstrqwdtsru;		/* 0x034 */
+	u8 res_038[0x60-0x38];		/* 0x038 */
+	u32 brrl;			/* 0x060 */
+	u32 brru;			/* 0x064 */
+	u8 res_068[0x80-0x68];		/* 0x068 */
+	u32 pirset;			/* 0x080 */
+	u32 pirclr;			/* 0x084 */
+	u8 res_088[0x90-0x88];		/* 0x088 */
+	u32 brcorenbr;			/* 0x090 */
+	u8 res_094[0x100-0x94];		/* 0x094 */
+	u32 rcw_reqr;			/* 0x100 */
+	u32 rcw_completion;		/* 0x104 */
+	u8 res_108[0x110-0x108];	/* 0x108 */
+	u32 pbi_reqr;			/* 0x110 */
+	u32 pbi_completion;		/* 0x114 */
+	u8 res_118[0xa00-0x118];	/* 0x118 */
+	u32 qmbm_warmrst;		/* 0xa00 */
+	u32 soc_warmrst;		/* 0xa04 */
+	u8 res_a08[0xbf8-0xa08];	/* 0xa08 */
+	u32 ip_rev1;			/* 0xbf8 */
+	u32 ip_rev2;			/* 0xbfc */
+};
+
+struct ccsr_serdes {
+	struct {
+		u32     rstctl; /* Reset Control Register */
+		u32     pllcr0; /* PLL Control Register 0 */
+		u32     pllcr1; /* PLL Control Register 1 */
+		u32     pllcr2; /* PLL Control Register 2 */
+		u32     pllcr3; /* PLL Control Register 3 */
+		u32     pllcr4; /* PLL Control Register 4 */
+		u32     pllcr5; /* PLL Control Register 5 */
+		u8      res[0x20 - 0x1c];
+	} bank[2];
+	u8      res1[0x90 - 0x40];
+	u32     srdstcalcr;     /* TX Calibration Control */
+	u32     srdstcalcr1;    /* TX Calibration Control1 */
+	u8      res2[0xa0 - 0x98];
+	u32     srdsrcalcr;     /* RX Calibration Control */
+	u32     srdsrcalcr1;    /* RX Calibration Control1 */
+	u8      res3[0xb0 - 0xa8];
+	u32     srdsgr0;        /* General Register 0 */
+	u8      res4[0x800 - 0xb4];
+	struct serdes_lane {
+		u32     gcr0;   /* General Control Register 0 */
+		u32     gcr1;   /* General Control Register 1 */
+		u32     gcr2;   /* General Control Register 2 */
+		u32     ssc0;   /* Speed Switch Control 0 */
+		u32     rec0;   /* Receive Equalization Control 0 */
+		u32     rec1;   /* Receive Equalization Control 1 */
+		u32     tec0;   /* Transmit Equalization Control 0 */
+		u32     ssc1;   /* Speed Switch Control 1 */
+		u8      res1[0x840 - 0x820];
+	} lane[8];
+	u8 res5[0x19fc - 0xa00];
+};
+
+#endif /*__ASSEMBLY__*/
+#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
new file mode 100644
index 0000000..d709af8
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
+#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
+
+#define I2C_QUIRK_REG	/* enable 8-bit driver */
+
+#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
new file mode 100644
index 0000000..661cdea
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015, Freescale Semiconductor
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+void update_early_mmu_table(void);
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
new file mode 100644
index 0000000..00aa91b
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014-2015, Freescale Semiconductor
+ */
+
+#ifndef _FSL_LAYERSCAPE_MP_H
+#define _FSL_LAYERSCAPE_MP_H
+
+/*
+* Each spin table element is defined as
+* struct {
+*      uint64_t entry_addr;
+*      uint64_t status;
+*      uint64_t lpid;
+*      uint64_t arch_comp;
+* };
+* we pad this struct to 64 bytes so each entry is in its own cacheline
+* the actual spin table is an array of these structures
+*/
+#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX	0
+#define SPIN_TABLE_ELEM_STATUS_IDX	1
+#define SPIN_TABLE_ELEM_LPID_IDX	2
+/* compare os arch and cpu arch */
+#define SPIN_TABLE_ELEM_ARCH_COMP_IDX	3
+#define WORDS_PER_SPIN_TABLE_ENTRY	8	/* pad to 64 bytes */
+#define SPIN_TABLE_ELEM_SIZE		64
+
+/* os arch is same as cpu arch */
+#define OS_ARCH_SAME			0
+/* os arch is different from cpu arch */
+#define OS_ARCH_DIFF			1
+
+#define id_to_core(x)	((x & 3) | (x >> 6))
+#ifndef __ASSEMBLY__
+extern u64 __spin_table[];
+extern u64 __real_cntfrq;
+extern u64 *secondary_boot_code;
+extern size_t __secondary_boot_code_size;
+#ifdef CONFIG_MP
+int fsl_layerscape_wake_seconday_cores(void);
+#else
+static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
+#endif
+void *get_spin_tbl_addr(void);
+phys_addr_t determine_mp_bootpg(void);
+void secondary_boot_func(void);
+int is_core_online(u64 cpu_id);
+u32 cpu_pos_mask(void);
+#endif
+
+#endif /* _FSL_LAYERSCAPE_MP_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
new file mode 100644
index 0000000..a265106
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+#include <fsl_csu.h>
+
+enum csu_cslx_ind {
+	CSU_CSLX_PCIE2_IO = 0,
+	CSU_CSLX_PCIE1_IO,
+	CSU_CSLX_MG2TPR_IP,
+	CSU_CSLX_IFC_MEM,
+	CSU_CSLX_OCRAM,
+	CSU_CSLX_GIC,
+	CSU_CSLX_PCIE1,
+	CSU_CSLX_OCRAM2,
+	CSU_CSLX_QSPI_MEM,
+	CSU_CSLX_PCIE2,
+	CSU_CSLX_SATA,
+	CSU_CSLX_USB1,
+	CSU_CSLX_QM_BM_SWPORTAL,
+	CSU_CSLX_PCIE3 = 16,
+	CSU_CSLX_PCIE3_IO,
+	CSU_CSLX_USB3 = 20,
+	CSU_CSLX_USB2,
+	CSU_CSLX_PFE = 23,
+	CSU_CSLX_SERDES = 32,
+	CSU_CSLX_QDMA,
+	CSU_CSLX_LPUART2,
+	CSU_CSLX_LPUART1,
+	CSU_CSLX_LPUART4,
+	CSU_CSLX_LPUART3,
+	CSU_CSLX_LPUART6,
+	CSU_CSLX_LPUART5,
+	CSU_CSLX_DSPI1 = 41,
+	CSU_CSLX_QSPI,
+	CSU_CSLX_ESDHC,
+	CSU_CSLX_IFC = 45,
+	CSU_CSLX_I2C1,
+	CSU_CSLX_USB_2,
+	CSU_CSLX_I2C3 = 48,
+	CSU_CSLX_I2C2,
+	CSU_CSLX_DUART2 = 50,
+	CSU_CSLX_DUART1,
+	CSU_CSLX_WDT2,
+	CSU_CSLX_WDT1,
+	CSU_CSLX_EDMA,
+	CSU_CSLX_SYS_CNT,
+	CSU_CSLX_DMA_MUX2,
+	CSU_CSLX_DMA_MUX1,
+	CSU_CSLX_DDR,
+	CSU_CSLX_QUICC,
+	CSU_CSLX_DCFG_CCU_RCPM = 60,
+	CSU_CSLX_SECURE_BOOTROM,
+	CSU_CSLX_SFP,
+	CSU_CSLX_TMU,
+	CSU_CSLX_SECURE_MONITOR,
+	CSU_CSLX_SCFG,
+	CSU_CSLX_FM = 66,
+	CSU_CSLX_SEC5_5,
+	CSU_CSLX_BM,
+	CSU_CSLX_QM,
+	CSU_CSLX_GPIO2 = 70,
+	CSU_CSLX_GPIO1,
+	CSU_CSLX_GPIO4,
+	CSU_CSLX_GPIO3,
+	CSU_CSLX_PLATFORM_CONT,
+	CSU_CSLX_CSU,
+	CSU_CSLX_IIC4 = 77,
+	CSU_CSLX_WDT4,
+	CSU_CSLX_WDT3,
+	CSU_CSLX_ESDHC2 = 80,
+	CSU_CSLX_WDT5 = 81,
+	CSU_CSLX_SAI2,
+	CSU_CSLX_SAI1,
+	CSU_CSLX_SAI4,
+	CSU_CSLX_SAI3,
+	CSU_CSLX_FTM2 = 86,
+	CSU_CSLX_FTM1,
+	CSU_CSLX_FTM4,
+	CSU_CSLX_FTM3,
+	CSU_CSLX_FTM6 = 90,
+	CSU_CSLX_FTM5,
+	CSU_CSLX_FTM8,
+	CSU_CSLX_FTM7,
+	CSU_CSLX_DSCR = 121,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h
new file mode 100644
index 0000000..f0c4a84
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 NXP Semiconductor, Inc.
+ */
+
+#ifndef __FSL_PPA_H_
+#define __FSL_PPA_H_
+
+#ifdef CONFIG_FSL_LS_PPA
+int ppa_init(void);
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
new file mode 100644
index 0000000..35719d7
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2019 NXP
+ * Copyright 2015 Freescale Semiconductor
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#endif
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/immap_lsch3.h>
+#endif
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a)       in_le32(a)
+#define gur_out32(a, v)   out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
+#define gur_in32(a)       in_be32(a)
+#define gur_out32(a, v)   out_be32(a, v)
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define scfg_in32(a)       in_le32(a)
+#define scfg_out32(a, v)   out_le32(a, v)
+#define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
+#define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
+#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
+#define scfg_in32(a)       in_be32(a)
+#define scfg_out32(a, v)   out_be32(a, v)
+#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
+#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
+#endif
+
+#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
+#define pex_lut_in32(a)       in_le32(a)
+#define pex_lut_out32(a, v)   out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
+#define pex_lut_in32(a)       in_be32(a)
+#define pex_lut_out32(a, v)   out_be32(a, v)
+#endif
+#ifndef __ASSEMBLY__
+struct cpu_type {
+	char name[15];
+	u32 soc_ver;
+	u32 num_cores;
+};
+
+#define CPU_TYPE_ENTRY(n, v, nc) \
+	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#ifdef CONFIG_TFABOOT
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+#define SIP_SVC_RCW	0xC200FF18
+
+phys_size_t tfa_get_dram_size(void);
+
+enum boot_src {
+	BOOT_SOURCE_RESERVED = 0,
+	BOOT_SOURCE_IFC_NOR,
+	BOOT_SOURCE_IFC_NAND,
+	BOOT_SOURCE_QSPI_NOR,
+	BOOT_SOURCE_QSPI_NAND,
+	BOOT_SOURCE_XSPI_NOR,
+	BOOT_SOURCE_XSPI_NAND,
+	BOOT_SOURCE_SD_MMC,
+	BOOT_SOURCE_SD_MMC2,
+	BOOT_SOURCE_I2C1_EXTENDED,
+};
+
+enum boot_src get_boot_src(void);
+#endif
+#endif
+#define SVR_WO_E		0xFFFFFE
+#define SVR_LS1012A		0x870400
+#define SVR_LS1043A		0x879200
+#define SVR_LS1023A		0x879208
+/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
+#define SVR_LS1043A_P23		0x879202
+#define SVR_LS1023A_P23		0x87920A
+#define SVR_LS1017A		0x870B24
+#define SVR_LS1018A		0x870B20
+#define SVR_LS1027A		0x870B04
+#define SVR_LS1028A		0x870B00
+#define SVR_LS1046A		0x870700
+#define SVR_LS1026A		0x870708
+#define SVR_LS1048A		0x870320
+#define SVR_LS1084A		0x870302
+#define SVR_LS1088A		0x870300
+#define SVR_LS1044A		0x870322
+#define SVR_LS2045A		0x870120
+#define SVR_LS2080A		0x870110
+#define SVR_LS2085A		0x870100
+#define SVR_LS2040A		0x870130
+#define SVR_LS2088A		0x870900
+#define SVR_LS2084A		0x870910
+#define SVR_LS2048A		0x870920
+#define SVR_LS2044A		0x870930
+#define SVR_LS2081A		0x870918
+#define SVR_LS2041A		0x870914
+#define SVR_LX2160A		0x873600
+#define SVR_LX2120A		0x873620
+#define SVR_LX2080A		0x873602
+
+#define SVR_MAJ(svr)		(((svr) >> 4) & 0xf)
+#define SVR_MIN(svr)		(((svr) >> 0) & 0xf)
+#define SVR_REV(svr)		(((svr) >> 0) & 0xff)
+#define SVR_SOC_VER(svr)	(((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr)	(!((svr >> 8) & 0x1))
+#ifdef CONFIG_ARCH_LX2160A
+#define IS_C_PROCESSOR(svr)	(!((svr >> 12) & 0x1))
+#endif
+#ifdef CONFIG_ARCH_LS1028A
+#define IS_MULTIMEDIA_EN(svr)	(!((svr >> 10) & 0x1))
+#endif
+#define IS_SVR_REV(svr, maj, min) \
+		((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+#define SVR_DEV(svr)		((svr) >> 8)
+#define IS_SVR_DEV(svr, dev)	(((svr) >> 16) == (dev))
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_FSL_LSCH3
+void fsl_lsch3_early_init_f(void);
+int get_core_volt_from_fuse(void);
+#elif defined(CONFIG_FSL_LSCH2)
+void fsl_lsch2_early_init_f(void);
+int setup_chip_volt(void);
+/* Setup core vdd in unit mV */
+int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
+#endif
+#ifdef CONFIG_QSPI_AHB_INIT
+int qspi_ahb_init(void);
+#endif
+
+void cpu_name(char *name);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+void erratum_a009635(void);
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void);
+#endif
+
+bool soc_has_dp_ddr(void);
+bool soc_has_aiop(void);
+#endif
+
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
new file mode 100644
index 0000000..2672169
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014-2015, Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_LAYERSCAPE_SPEED_H
+#define _FSL_LAYERSCAPE_SPEED_H
+void get_sys_info(struct sys_info *sys_info);
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void);
+#endif
+#endif /* _FSL_LAYERSCAPE_SPEED_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
new file mode 100644
index 0000000..1b02d48
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP Semiconductor, Inc.
+ *
+ */
+#ifndef __FSL_STREAM_ID_H
+#define __FSL_STREAM_ID_H
+
+/*
+ * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
+ * are not hardwired and are programmed by sw.  There are a limited number
+ * of stream IDs available, and the partitioning of them is scenario
+ * dependent. This header defines the partitioning between legacy, PCI,
+ * and DPAA1 devices.
+ *
+ * This partitioning can be customized in this file depending
+ * on the specific hardware config:
+ *
+ *  -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc)
+ *     -all legacy devices get a unique stream ID assigned and programmed in
+ *      their AMQR registers by u-boot
+ *
+ *  -PCIe
+ *     -there is a range of stream IDs set aside for PCI in this
+ *      file.  U-boot will scan the PCI bus and for each device discovered:
+ *         -allocate a streamID
+ *         -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
+ *         -set a msi-map entry in the PEXn controller node in the
+ *          device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
+ *          for more info on the msi-map definition)
+ *         -set a iommu-map entry in the PEXn controller node in the
+ *          device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
+ *          for more info on the iommu-map definition)
+ *
+ *  -DPAA1
+ *     - Stream ids for DPAA1 use are reserved for future usecase.
+ *
+ */
+
+
+#define FSL_INVALID_STREAM_ID		0
+
+/* legacy devices */
+#define FSL_USB1_STREAM_ID		1
+#define FSL_USB2_STREAM_ID		2
+#define FSL_USB3_STREAM_ID		3
+#define FSL_SDHC_STREAM_ID		4
+#define FSL_SATA_STREAM_ID		5
+#define FSL_QE_STREAM_ID		6
+#define FSL_QDMA_STREAM_ID		7
+#define FSL_EDMA_STREAM_ID		8
+#define FSL_ETR_STREAM_ID		9
+#define FSL_DEBUG_STREAM_ID		10
+
+/* PCI - programmed in PEXn_LUT */
+#define FSL_PEX_STREAM_ID_START		11
+#define FSL_PEX_STREAM_ID_END		26
+
+/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */
+#define FSL_DPAA1_STREAM_ID_START	27
+#define FSL_DPAA1_STREAM_ID_END		63
+
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
new file mode 100644
index 0000000..93bdcc4
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2018 NXP
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ */
+#ifndef __FSL_STREAM_ID_H
+#define __FSL_STREAM_ID_H
+
+/*
+ * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a)
+ * devices are not hardwired and are programmed by sw. There are a limited
+ * number of stream IDs available, and the partitioning of them is scenario
+ * dependent. This header defines the partitioning between legacy,
+ * PCI, and DPAA2 devices.
+ *
+ * This partitioning can be customized in this file depending
+ * on the specific hardware config:
+ *
+ *  -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
+ *     -all legacy devices get a unique stream ID assigned and programmed in
+ *      their AMQR registers by u-boot
+ *
+ *  -PCIe
+ *     -there is a range of stream IDs set aside for PCI in this
+ *      file.  U-boot will scan the PCI bus and for each device discovered:
+ *         -allocate a streamID
+ *         -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
+ *         -set a msi-map entry in the PEXn controller node in the
+ *          device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
+ *          for more info on the msi-map definition)
+ *         -set a iommu-map entry in the PEXn controller node in the
+ *          device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
+ *          for more info on the iommu-map definition)
+ *
+ *  -DPAA2
+ *     -u-boot will allocate a range of stream IDs to be used by the Management
+ *      Complex for containers and will set these values in the MC DPC image.
+ *     -u-boot will fixup the iommu-map property in the fsl-mc node in the
+ *      device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
+ *      for more info on the msi-map definition)
+ *     -the MC is responsible for allocating and setting up 'isolation context
+ *      IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices.
+ *
+ * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for
+ * each of the different bus masters.  The relationship between
+ * the AMQ registers and stream IDs is defined in the table below:
+ *          AMQ bit    streamID bit
+ *      ---------------------------
+ *           PL[18]         9        // privilege bit
+ *          BMT[17]         8        // bypass translation
+ *           VA[16]         7        // reserved
+ *             [15]         -        // unused
+ *         ICID[14:7]       -        // unused
+ *         ICID[6:0]        6-0      // isolation context id
+ *     ----------------------------
+ *
+ */
+
+#define AMQ_PL_MASK			(0x1 << 18)   /* priviledge bit */
+#define AMQ_BMT_MASK			(0x1 << 17)   /* bypass bit */
+
+#define FSL_INVALID_STREAM_ID		0
+
+#define FSL_BYPASS_AMQ			(AMQ_PL_MASK | AMQ_BMT_MASK)
+
+/* legacy devices */
+#define FSL_USB1_STREAM_ID		1
+#define FSL_USB2_STREAM_ID		2
+#define FSL_SDMMC_STREAM_ID		3
+#define FSL_SATA1_STREAM_ID		4
+
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+#define FSL_SATA2_STREAM_ID		5
+#endif
+
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
+#define FSL_DMA_STREAM_ID		6
+#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
+#define FSL_DMA_STREAM_ID		5
+#endif
+
+/* PCI - programmed in PEXn_LUT */
+#define FSL_PEX_STREAM_ID_START		7
+
+#ifdef CONFIG_ARCH_LX2160A
+#define FSL_PEX_STREAM_ID_NUM		(0x100)
+#endif
+
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1028A)
+#define FSL_PEX_STREAM_ID_END		22
+#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_PEX_STREAM_ID_END		18
+#endif
+
+
+/* DPAA2 - set in MC DPC and alloced by MC */
+#define FSL_DPAA2_STREAM_ID_START	23
+#define FSL_DPAA2_STREAM_ID_END		63
+
+#define FSL_SEC_STREAM_ID		64
+#define FSL_SEC_JR1_STREAM_ID		65
+#define FSL_SEC_JR2_STREAM_ID		66
+#define FSL_SEC_JR3_STREAM_ID		67
+#define FSL_SEC_JR4_STREAM_ID		68
+
+#define FSL_SDMMC2_STREAM_ID		69
+#define FSL_EDMA_STREAM_ID		70
+#define FSL_GPU_STREAM_ID		71
+#define FSL_DISPLAY_STREAM_ID		72
+
+#endif
diff --git a/arch/arm/include/asm/arch-hi3660/hi3660.h b/arch/arm/include/asm/arch-hi3660/hi3660.h
new file mode 100644
index 0000000..3ca0951
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi3660/hi3660.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Linaro
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#ifndef __HI3660_H__
+#define __HI3660_H__
+
+#define HI3660_UART6_BASE			0xfff32000
+
+#define PMU_REG_BASE                            0xfff34000
+#define PMIC_HARDWARE_CTRL0                     (PMU_REG_BASE + (0x0C5 << 2))
+
+#define SCTRL_REG_BASE                          0xfff0a000
+#define SCTRL_SCFPLLCTRL0                       (SCTRL_REG_BASE + 0x120)
+#define SCTRL_SCFPLLCTRL0_FPLL0_EN              BIT(0)
+
+#define CRG_REG_BASE                            0xfff35000
+#define CRG_PEREN2                              (CRG_REG_BASE + 0x020)
+#define CRG_PERDIS2                             (CRG_REG_BASE + 0x024)
+#define CRG_PERCLKEN2                           (CRG_REG_BASE + 0x028)
+#define CRG_PERSTAT2                            (CRG_REG_BASE + 0x02C)
+#define CRG_PEREN4                              (CRG_REG_BASE + 0x040)
+#define CRG_PERDIS4                             (CRG_REG_BASE + 0x044)
+#define CRG_PERCLKEN4                           (CRG_REG_BASE + 0x048)
+#define CRG_PERSTAT4                            (CRG_REG_BASE + 0x04C)
+#define CRG_PERRSTEN2                           (CRG_REG_BASE + 0x078)
+#define CRG_PERRSTDIS2                          (CRG_REG_BASE + 0x07C)
+#define CRG_PERRSTSTAT2                         (CRG_REG_BASE + 0x080)
+#define CRG_PERRSTEN3                           (CRG_REG_BASE + 0x084)
+#define CRG_PERRSTDIS3                          (CRG_REG_BASE + 0x088)
+#define CRG_PERRSTSTAT3                         (CRG_REG_BASE + 0x08C)
+#define CRG_PERRSTEN4                           (CRG_REG_BASE + 0x090)
+#define CRG_PERRSTDIS4                          (CRG_REG_BASE + 0x094)
+#define CRG_PERRSTSTAT4                         (CRG_REG_BASE + 0x098)
+#define CRG_ISOEN                               (CRG_REG_BASE + 0x144)
+#define CRG_ISODIS                              (CRG_REG_BASE + 0x148)
+#define CRG_ISOSTAT                             (CRG_REG_BASE + 0x14C)
+
+#define PINMUX4_BASE				0xfff11000
+#define PINMUX4_SDDET				(PINMUX4_BASE + 0x60)
+
+#define PINCONF3_BASE				0xff37e800
+#define PINCONF3_SDCLK				(PINCONF3_BASE + 0x00)
+#define PINCONF3_SDCMD				(PINCONF3_BASE + 0x04)
+#define PINCONF3_SDDATA0			(PINCONF3_BASE + 0x08)
+#define PINCONF3_SDDATA1			(PINCONF3_BASE + 0x0c)
+#define PINCONF3_SDDATA2			(PINCONF3_BASE + 0x10)
+#define PINCONF3_SDDATA3			(PINCONF3_BASE + 0x14)
+
+#endif /*__HI3660_H__*/
diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h
new file mode 100644
index 0000000..b98b45c
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Linaro
+ * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ */
+
+#ifndef __HI3798cv200_H__
+#define __HI3798cv200_H__
+
+#define REG_BASE_PERI_CTRL		0xF8A20000
+#define REG_BASE_CRG			0xF8A22000
+
+/* DEVICES */
+#define REG_BASE_UART0			0xF8B00000
+#define HIOTG_BASE_ADDR			0xF98C0000
+
+/* PERI control registers (4KB) */
+	/* USB2 PHY01 configuration register */
+#define PERI_CTRL_USB0			(REG_BASE_PERI_CTRL + 0x120)
+
+	/* USB2 controller configuration register */
+#define PERI_CTRL_USB3			(REG_BASE_PERI_CTRL + 0x12c)
+#define USB2_2P_CHIPID			(1 << 28)
+
+/* PERI CRG registers (4KB) */
+	/* USB2 CTRL0 clock and soft reset */
+#define PERI_CRG46			(REG_BASE_CRG + 0xb8)
+#define USB2_BUS_CKEN			(1<<0)
+#define USB2_OHCI48M_CKEN		(1<<1)
+#define USB2_OHCI12M_CKEN		(1<<2)
+#define USB2_OTG_UTMI_CKEN		(1<<3)
+#define USB2_HST_PHY_CKEN		(1<<4)
+#define USB2_UTMI0_CKEN			(1<<5)
+#define USB2_BUS_SRST_REQ		(1<<12)
+#define USB2_UTMI0_SRST_REQ		(1<<13)
+#define USB2_HST_PHY_SYST_REQ		(1<<16)
+#define USB2_OTG_PHY_SYST_REQ		(1<<17)
+#define USB2_CLK48_SEL			(1<<20)
+
+	/* USB2 PHY clock and soft reset */
+#define PERI_CRG47			(REG_BASE_CRG + 0xbc)
+#define USB2_PHY01_REF_CKEN		(1 << 0)
+#define USB2_PHY2_REF_CKEN		(1 << 2)
+#define USB2_PHY01_SRST_REQ		(1 << 4)
+#define USB2_PHY2_SRST_REQ		(1 << 6)
+#define USB2_PHY01_SRST_TREQ0		(1 << 8)
+#define USB2_PHY01_SRST_TREQ1		(1 << 9)
+#define USB2_PHY2_SRST_TREQ		(1 << 10)
+#define USB2_PHY01_REFCLK_SEL		(1 << 12)
+#define USB2_PHY2_REFCLK_SEL		(1 << 14)
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-hi6220/dwmmc.h b/arch/arm/include/asm/arch-hi6220/dwmmc.h
new file mode 100644
index 0000000..cf51c17
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/dwmmc.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ */
+
+int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
diff --git a/arch/arm/include/asm/arch-hi6220/gpio.h b/arch/arm/include/asm/arch-hi6220/gpio.h
new file mode 100644
index 0000000..c5ee359
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/gpio.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ */
+
+#ifndef _HI6220_GPIO_H_
+#define _HI6220_GPIO_H_
+
+#define HI6220_GPIO_BASE(bank)	(((bank < 4) ? 0xf8011000 : \
+				0xf7020000 - 0x4000) + (0x1000 * bank))
+
+#define HI6220_GPIO_PER_BANK	8
+#define HI6220_GPIO_DIR		0x400
+
+struct gpio_bank {
+	u8 *base;	/* address of registers in physical memory */
+};
+
+/* Information about a GPIO bank */
+struct hikey_gpio_platdata {
+	int bank_index;
+	ulong base;     /* address of registers in physical memory */
+};
+
+#endif /* _HI6220_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-hi6220/hi6220.h b/arch/arm/include/asm/arch-hi6220/hi6220.h
new file mode 100644
index 0000000..55729e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/hi6220.h
@@ -0,0 +1,389 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ */
+
+#ifndef __HI6220_H__
+#define __HI6220_H__
+
+#include "hi6220_regs_alwayson.h"
+
+#define HI6220_MMC0_BASE			0xF723D000
+#define HI6220_MMC1_BASE			0xF723E000
+
+#define HI6220_UART0_BASE			0xF8015000
+#define HI6220_UART3_BASE			0xF7113000
+
+#define HI6220_PMUSSI_BASE			0xF8000000
+
+#define HI6220_PERI_BASE			0xF7030000
+
+struct peri_sc_periph_regs {
+	u32 ctrl1;		/*0x0*/
+	u32 ctrl2;
+	u32 ctrl3;
+	u32 ctrl4;
+	u32 ctrl5;
+	u32 ctrl6;
+	u32 ctrl8;
+	u32 ctrl9;
+	u32 ctrl10;
+	u32 ctrl12;
+	u32 ctrl13;
+	u32 ctrl14;
+
+	u32 unknown_1[8];
+
+	u32 ddr_ctrl0;		/*0x50*/
+
+	u32 unknown_2[16];
+
+	u32 stat1;		/*0x94*/
+
+	u32 unknown_3[90];
+
+	u32 clk0_en;		/*0x200*/
+	u32 clk0_dis;
+	u32 clk0_stat;
+
+	u32 unknown_4;
+
+	u32 clk1_en;		/*0x210*/
+	u32 clk1_dis;
+	u32 clk1_stat;
+
+	u32 unknown_5;
+
+	u32 clk2_en;		/*0x220*/
+	u32 clk2_dis;
+	u32 clk2_stat;
+
+	u32 unknown_6;
+
+	u32 clk3_en;		/*0x230*/
+	u32 clk3_dis;
+	u32 clk3_stat;
+
+	u32 unknown_7;
+
+	u32 clk8_en;		/*0x240*/
+	u32 clk8_dis;
+	u32 clk8_stat;
+
+	u32 unknown_8;
+
+	u32 clk9_en;		/*0x250*/
+	u32 clk9_dis;
+	u32 clk9_stat;
+
+	u32 unknown_9;
+
+	u32 clk10_en;		/*0x260*/
+	u32 clk10_dis;
+	u32 clk10_stat;
+
+	u32 unknown_10;
+
+	u32 clk12_en;		/*0x270*/
+	u32 clk12_dis;
+	u32 clk12_stat;
+
+	u32 unknown_11[33];
+
+	u32 rst0_en;		/*0x300*/
+	u32 rst0_dis;
+	u32 rst0_stat;
+
+	u32 unknown_12;
+
+	u32 rst1_en;		/*0x310*/
+	u32 rst1_dis;
+	u32 rst1_stat;
+
+	u32 unknown_13;
+
+	u32 rst2_en;		/*0x320*/
+	u32 rst2_dis;
+	u32 rst2_stat;
+
+	u32 unknown_14;
+
+	u32 rst3_en;		/*0x330*/
+	u32 rst3_dis;
+	u32 rst3_stat;
+
+	u32 unknown_15;
+
+	u32 rst8_en;		/*0x340*/
+	u32 rst8_dis;
+	u32 rst8_stat;
+
+	u32 unknown_16[45];
+
+	u32 clk0_sel;		/*0x400*/
+
+	u32 unknown_17[36];
+
+	u32 clkcfg8bit1;	/*0x494*/
+	u32 clkcfg8bit2;
+
+	u32 unknown_18[538];
+
+	u32 reserved8_addr;	/*0xd04*/
+};
+
+
+/* CTRL1 bit definitions */
+
+#define PERI_CTRL1_ETR_AXI_CSYSREQ_N			(1 << 0)
+#define PERI_CTRL1_HIFI_INT_MASK			(1 << 1)
+#define PERI_CTRL1_HIFI_ALL_INT_MASK			(1 << 2)
+#define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK		(1 << 16)
+#define PERI_CTRL1_HIFI_INT_MASK_MSK			(1 << 17)
+#define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK		(1 << 18)
+
+
+/* CTRL2 bit definitions */
+
+#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0		(1 << 0)
+#define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1		(1 << 2)
+#define PERI_CTRL2_NAND_SYS_MEM_SEL			(1 << 6)
+#define PERI_CTRL2_G3D_DDRT_AXI_SEL			(1 << 7)
+#define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL		(1 << 8)
+#define PERI_CTRL2_CODEC_SSI_MASTER_CHECK		(1 << 9)
+#define PERI_CTRL2_FUNC_TEST_SOFT			(1 << 12)
+#define PERI_CTRL2_CSSYS_TS_ENABLE			(1 << 15)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMA			(1 << 16)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW			(1 << 20)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS			(1 << 22)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N			(1 << 26)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N			(1 << 27)
+#define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN			(1 << 28)
+
+/* CTRL3 bit definitions */
+
+#define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR		(1 << 0)
+#define PERI_CTRL3_HIFI_HARQMEMRMP_EN			(1 << 12)
+#define PERI_CTRL3_HARQMEM_SYS_MED_SEL			(1 << 13)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP1			(1 << 14)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP2			(1 << 16)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP3			(1 << 18)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP4			(1 << 20)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP5			(1 << 22)
+#define PERI_CTRL3_SOC_AP_OCCUPY_GRP6			(1 << 24)
+
+/* CTRL4 bit definitions */
+
+#define PERI_CTRL4_PICO_FSELV				(1 << 0)
+#define PERI_CTRL4_FPGA_EXT_PHY_SEL			(1 << 3)
+#define PERI_CTRL4_PICO_REFCLKSEL			(1 << 4)
+#define PERI_CTRL4_PICO_SIDDQ				(1 << 6)
+#define PERI_CTRL4_PICO_SUSPENDM_SLEEPM			(1 << 7)
+#define PERI_CTRL4_PICO_OGDISABLE			(1 << 8)
+#define PERI_CTRL4_PICO_COMMONONN			(1 << 9)
+#define PERI_CTRL4_PICO_VBUSVLDEXT			(1 << 10)
+#define PERI_CTRL4_PICO_VBUSVLDEXTSEL			(1 << 11)
+#define PERI_CTRL4_PICO_VATESTENB			(1 << 12)
+#define PERI_CTRL4_PICO_SUSPENDM			(1 << 14)
+#define PERI_CTRL4_PICO_SLEEPM				(1 << 15)
+#define PERI_CTRL4_BC11_C				(1 << 16)
+#define PERI_CTRL4_BC11_B				(1 << 17)
+#define PERI_CTRL4_BC11_A				(1 << 18)
+#define PERI_CTRL4_BC11_GND				(1 << 19)
+#define PERI_CTRL4_BC11_FLOAT				(1 << 20)
+#define PERI_CTRL4_OTG_PHY_SEL				(1 << 21)
+#define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE		(1 << 22)
+#define PERI_CTRL4_OTG_DM_PULLDOWN			(1 << 24)
+#define PERI_CTRL4_OTG_DP_PULLDOWN			(1 << 25)
+#define PERI_CTRL4_OTG_IDPULLUP				(1 << 26)
+#define PERI_CTRL4_OTG_DRVBUS				(1 << 27)
+#define PERI_CTRL4_OTG_SESSEND				(1 << 28)
+#define PERI_CTRL4_OTG_BVALID				(1 << 29)
+#define PERI_CTRL4_OTG_AVALID				(1 << 30)
+#define PERI_CTRL4_OTG_VBUSVALID			(1 << 31)
+
+/* CTRL5 bit definitions */
+
+#define PERI_CTRL5_USBOTG_RES_SEL			(1 << 3)
+#define PERI_CTRL5_PICOPHY_ACAENB			(1 << 4)
+#define PERI_CTRL5_PICOPHY_BC_MODE			(1 << 5)
+#define PERI_CTRL5_PICOPHY_CHRGSEL			(1 << 6)
+#define PERI_CTRL5_PICOPHY_VDATSRCEND			(1 << 7)
+#define PERI_CTRL5_PICOPHY_VDATDETENB			(1 << 8)
+#define PERI_CTRL5_PICOPHY_DCDENB			(1 << 9)
+#define PERI_CTRL5_PICOPHY_IDDIG			(1 << 10)
+#define PERI_CTRL5_DBG_MUX				(1 << 11)
+
+/* CTRL6 bit definitions */
+
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA		(1 << 0)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW		(1 << 4)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS		(1 << 6)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N		(1 << 10)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N		(1 << 11)
+#define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN		(1 << 12)
+
+/* CTRL8 bit definitions */
+
+#define PERI_CTRL8_PICOPHY_TXRISETUNE0			(1 << 0)
+#define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0		(1 << 2)
+#define PERI_CTRL8_PICOPHY_TXRESTUNE0			(1 << 4)
+#define PERI_CTRL8_PICOPHY_TXHSSVTUNE0			(1 << 6)
+#define PERI_CTRL8_PICOPHY_COMPDISTUNE0			(1 << 8)
+#define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0		(1 << 11)
+#define PERI_CTRL8_PICOPHY_OTGTUNE0			(1 << 12)
+#define PERI_CTRL8_PICOPHY_SQRXTUNE0			(1 << 16)
+#define PERI_CTRL8_PICOPHY_TXVREFTUNE0			(1 << 20)
+#define PERI_CTRL8_PICOPHY_TXFSLSTUNE0			(1 << 28)
+
+/* CTRL9 bit definitions */
+
+#define PERI_CTRL9_PICOPLY_TESTCLKEN			(1 << 0)
+#define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL		(1 << 1)
+#define PERI_CTRL9_PICOPLY_TESTADDR			(1 << 4)
+#define PERI_CTRL9_PICOPLY_TESTDATAIN			(1 << 8)
+
+/* CLK0 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK0_MMC0					(1 << 0)
+#define PERI_CLK0_MMC1					(1 << 1)
+#define PERI_CLK0_MMC2					(1 << 2)
+#define PERI_CLK0_NANDC					(1 << 3)
+#define PERI_CLK0_USBOTG				(1 << 4)
+#define PERI_CLK0_PICOPHY				(1 << 5)
+#define PERI_CLK0_PLL					(1 << 6)
+
+/* CLK1 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK1_HIFI					(1 << 0)
+#define PERI_CLK1_DIGACODEC				(1 << 5)
+
+/* CLK2 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK2_IPF					(1 << 0)
+#define PERI_CLK2_SOCP					(1 << 1)
+#define PERI_CLK2_DMAC					(1 << 2)
+#define PERI_CLK2_SECENG				(1 << 3)
+#define PERI_CLK2_HPM0					(1 << 5)
+#define PERI_CLK2_HPM1					(1 << 6)
+#define PERI_CLK2_HPM2					(1 << 7)
+#define PERI_CLK2_HPM3					(1 << 8)
+
+/* CLK8 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK8_RS0					(1 << 0)
+#define PERI_CLK8_RS2					(1 << 1)
+#define PERI_CLK8_RS3					(1 << 2)
+#define PERI_CLK8_MS0					(1 << 3)
+#define PERI_CLK8_MS2					(1 << 5)
+#define PERI_CLK8_XG2RAM0				(1 << 6)
+#define PERI_CLK8_X2SRAM				(1 << 7)
+#define PERI_CLK8_SRAM					(1 << 8)
+#define PERI_CLK8_ROM					(1 << 9)
+#define PERI_CLK8_HARQ					(1 << 10)
+#define PERI_CLK8_MMU					(1 << 11)
+#define PERI_CLK8_DDRC					(1 << 12)
+#define PERI_CLK8_DDRPHY				(1 << 13)
+#define PERI_CLK8_DDRPHY_REF				(1 << 14)
+#define PERI_CLK8_X2X_SYSNOC				(1 << 15)
+#define PERI_CLK8_X2X_CCPU				(1 << 16)
+#define PERI_CLK8_DDRT					(1 << 17)
+#define PERI_CLK8_DDRPACK_RS				(1 << 18)
+
+/* CLK9 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK9_CARM_DAP				(1 << 0)
+#define PERI_CLK9_CARM_ATB				(1 << 1)
+#define PERI_CLK9_CARM_LBUS				(1 << 2)
+#define PERI_CLK9_CARM_KERNEL				(1 << 3)
+
+/* CLK10 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK10_IPF_CCPU				(1 << 0)
+#define PERI_CLK10_SOCP_CCPU				(1 << 1)
+#define PERI_CLK10_SECENG_CCPU				(1 << 2)
+#define PERI_CLK10_HARQ_CCPU				(1 << 3)
+#define PERI_CLK10_IPF_MCU				(1 << 16)
+#define PERI_CLK10_SOCP_MCU				(1 << 17)
+#define PERI_CLK10_SECENG_MCU				(1 << 18)
+#define PERI_CLK10_HARQ_MCU				(1 << 19)
+
+/* CLK12 EN/DIS/STAT bit definitions */
+
+#define PERI_CLK12_HIFI_SRC				(1 << 0)
+#define PERI_CLK12_MMC0_SRC				(1 << 1)
+#define PERI_CLK12_MMC1_SRC				(1 << 2)
+#define PERI_CLK12_MMC2_SRC				(1 << 3)
+#define PERI_CLK12_SYSPLL_DIV				(1 << 4)
+#define PERI_CLK12_TPIU_SRC				(1 << 5)
+#define PERI_CLK12_MMC0_HF				(1 << 6)
+#define PERI_CLK12_MMC1_HF				(1 << 7)
+#define PERI_CLK12_PLL_TEST_SRC				(1 << 8)
+#define PERI_CLK12_CODEC_SOC				(1 << 9)
+#define PERI_CLK12_MEDIA				(1 << 10)
+
+/* RST0 EN/DIS/STAT bit definitions */
+
+#define PERI_RST0_MMC0					(1 << 0)
+#define PERI_RST0_MMC1					(1 << 1)
+#define PERI_RST0_MMC2					(1 << 2)
+#define PERI_RST0_NANDC					(1 << 3)
+#define PERI_RST0_USBOTG_BUS				(1 << 4)
+#define PERI_RST0_POR_PICOPHY				(1 << 5)
+#define PERI_RST0_USBOTG				(1 << 6)
+#define PERI_RST0_USBOTG_32K				(1 << 7)
+
+/* RST1 EN/DIS/STAT bit definitions */
+
+#define PERI_RST1_HIFI					(1 << 0)
+#define PERI_RST1_DIGACODEC				(1 << 5)
+
+/* RST2 EN/DIS/STAT bit definitions */
+
+#define PERI_RST2_IPF					(1 << 0)
+#define PERI_RST2_SOCP					(1 << 1)
+#define PERI_RST2_DMAC					(1 << 2)
+#define PERI_RST2_SECENG				(1 << 3)
+#define PERI_RST2_ABB					(1 << 4)
+#define PERI_RST2_HPM0					(1 << 5)
+#define PERI_RST2_HPM1					(1 << 6)
+#define PERI_RST2_HPM2					(1 << 7)
+#define PERI_RST2_HPM3					(1 << 8)
+
+/* RST3 EN/DIS/STAT bit definitions */
+
+#define PERI_RST3_CSSYS					(1 << 0)
+#define PERI_RST3_I2C0					(1 << 1)
+#define PERI_RST3_I2C1					(1 << 2)
+#define PERI_RST3_I2C2					(1 << 3)
+#define PERI_RST3_I2C3					(1 << 4)
+#define PERI_RST3_UART1					(1 << 5)
+#define PERI_RST3_UART2					(1 << 6)
+#define PERI_RST3_UART3					(1 << 7)
+#define PERI_RST3_UART4					(1 << 8)
+#define PERI_RST3_SSP					(1 << 9)
+#define PERI_RST3_PWM					(1 << 10)
+#define PERI_RST3_BLPWM					(1 << 11)
+#define PERI_RST3_TSENSOR				(1 << 12)
+#define PERI_RST3_DAPB					(1 << 18)
+#define PERI_RST3_HKADC					(1 << 19)
+#define PERI_RST3_CODEC					(1 << 20)
+
+/* RST8 EN/DIS/STAT bit definitions */
+
+#define PERI_RST8_RS0					(1 << 0)
+#define PERI_RST8_RS2					(1 << 1)
+#define PERI_RST8_RS3					(1 << 2)
+#define PERI_RST8_MS0					(1 << 3)
+#define PERI_RST8_MS2					(1 << 5)
+#define PERI_RST8_XG2RAM0				(1 << 6)
+#define PERI_RST8_X2SRAM_TZMA				(1 << 7)
+#define PERI_RST8_SRAM					(1 << 8)
+#define PERI_RST8_HARQ					(1 << 10)
+#define PERI_RST8_DDRC					(1 << 12)
+#define PERI_RST8_DDRC_APB				(1 << 13)
+#define PERI_RST8_DDRPACK_APB				(1 << 14)
+#define PERI_RST8_DDRT					(1 << 17)
+
+#endif /*__HI62220_H__*/
diff --git a/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h b/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h
new file mode 100644
index 0000000..4b9a0d4
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/hi6220_regs_alwayson.h
@@ -0,0 +1,419 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ */
+
+#ifndef __HI6220_ALWAYSON_H__
+#define __HI6220_ALWAYSON_H__
+
+#define ALWAYSON_CTRL_BASE			0xF7800000
+
+struct alwayson_sc_regs {
+	u32 ctrl0;		/*0x0*/
+	u32 ctrl1;
+	u32 ctrl2;
+
+	u32 unknown;
+
+	u32 stat0;		/*0x10*/
+	u32 stat1;
+	u32 mcu_imctrl;
+	u32 mcu_imstat;
+
+	u32 unknown_1[9];
+
+	u32 secondary_int_en0;	/*0x44*/
+	u32 secondary_int_statr0;
+	u32 secondary_int_statm0;
+
+	u32 unknown_2;
+
+	u32 mcu_wkup_int_en6;	/*0x54*/
+	u32 mcu_wkup_int_statr6;
+	u32 mcu_wkup_int_statm6;
+
+	u32 unknown_3;
+
+	u32 mcu_wkup_int_en5;	/*0x64*/
+	u32 mcu_wkup_int_statr5;
+	u32 mcu_wkup_int_statm5;
+
+	u32 unknown_4[9];
+
+	u32 mcu_wkup_int_en4;	/*0x94*/
+	u32 mcu_wkup_int_statr4;
+	u32 mcu_wkup_int_statm4;
+
+	u32 unknown_5[2];
+
+	u32 mcu_wkup_int_en0;	/*0xa8*/
+	u32 mcu_wkup_int_statr0;
+	u32 mcu_wkup_int_statm0;
+
+	u32 mcu_wkup_int_en1;	/*0xb4*/
+	u32 mcu_wkup_int_statr1;
+	u32 mcu_wkup_int_statm1;
+
+	u32 unknown_6;
+
+	u32 int_statr;		/*0xc4*/
+	u32 int_statm;
+	u32 int_clear;
+
+	u32 int_en_set;		/*0xd0*/
+	u32 int_en_dis;
+	u32 int_en_stat;
+
+	u32 unknown_7[2];
+
+	u32 int_statr1;		/*0xc4*/
+	u32 int_statm1;
+	u32 int_clear1;
+
+	u32 int_en_set1;	/*0xf0*/
+	u32 int_en_dis1;
+	u32 int_en_stat1;
+
+	u32 unknown_8[53];
+
+	u32 timer_en0;		/*0x1d0*/
+	u32 timer_en1;
+
+	u32 unknown_9[6];
+
+	u32 timer_en4;		/*0x1f0*/
+	u32 timer_en5;
+
+	u32 unknown_10[130];
+
+	u32 mcu_subsys_ctrl0;	/*0x400*/
+	u32 mcu_subsys_ctrl1;
+	u32 mcu_subsys_ctrl2;
+	u32 mcu_subsys_ctrl3;
+	u32 mcu_subsys_ctrl4;
+	u32 mcu_subsys_ctrl5;
+	u32 mcu_subsys_ctrl6;
+	u32 mcu_subsys_ctrl7;
+
+	u32 unknown_10_1[8];
+
+	u32 mcu_subsys_stat0;	/*0x440*/
+	u32 mcu_subsys_stat1;
+	u32 mcu_subsys_stat2;
+	u32 mcu_subsys_stat3;
+	u32 mcu_subsys_stat4;
+	u32 mcu_subsys_stat5;
+	u32 mcu_subsys_stat6;
+	u32 mcu_subsys_stat7;
+
+	u32 unknown_11[116];
+
+	u32 clk4_en;		/*0x630*/
+	u32 clk4_dis;
+	u32 clk4_stat;
+
+	u32 clk5_en;		/*0x63c*/
+	u32 clk5_dis;
+	u32 clk5_stat;
+
+	u32 unknown_12[42];
+
+	u32 rst4_en;		/*0x6f0*/
+	u32 rst4_dis;
+	u32 rst4_stat;
+
+	u32 rst5_en;		/*0x6fc*/
+	u32 rst5_dis;
+	u32 rst5_stat;
+
+	u32 unknown_13[62];
+
+	u32 pw_clk0_en;		/*0x800*/
+	u32 pw_clk0_dis;
+	u32 pw_clk0_stat;
+
+	u32 unknown_13_1;
+
+	u32 pw_rst0_en;		/*0x810*/
+	u32 pw_rst0_dis;
+	u32 pw_rst0_stat;
+
+	u32 unknown_14;
+
+	u32 pw_isoen0;		/*0x820*/
+	u32 pw_isodis0;
+	u32 pw_iso_stat0;
+
+	u32 unknown_14_1;
+
+	u32 pw_mtcmos_en0;	/*0x830*/
+	u32 pw_mtcmos_dis0;
+	u32 pw_mtcmos_stat0;
+	u32 pw_mtcmos_ack_stat0;
+	u32 pw_mtcmos_timeout_stat0;
+
+	u32 unknown_14_2[3];
+
+	u32 pw_stat0;		/*0x850*/
+	u32 pw_stat1;
+
+	u32 unknown_15[10];
+
+	u32 systest_stat;	/*0x880*/
+
+	u32 unknown_16[3];
+
+	u32 systest_slicer_cnt0;/*0x890*/
+	u32 systest_slicer_cnt1;
+
+	u32 unknown_17[12];
+
+	u32 pw_ctrl1;		/*0x8C8*/
+	u32 pw_ctrl;
+
+	u32 mcpu_voteen;
+	u32 mcpu_votedis;
+	u32 mcpu_votestat;
+
+	u32 unknown_17_1;
+
+	u32 mcpu_vote_msk0;	/*0x8E0*/
+	u32 mcpu_vote_msk1;
+	u32 mcpu_votestat0_msk;
+	u32 mcpu_votestat1_msk;
+
+	u32 peri_voteen;	/*0x8F0*/
+	u32 peri_votedis;
+	u32 peri_votestat;
+
+	u32 unknown_17_2;
+
+	u32 peri_vote_msk0;	/*0x900*/
+	u32 peri_vote_msk1;
+	u32 peri_votestat0_msk;
+	u32 erpi_votestat1_msk;
+	u32 acpu_voteen;
+	u32 acpu_votedis;
+	u32 acpu_votestat;
+
+	u32 unknown_18;
+
+	u32 acpu_vote_msk0;	/*0x920*/
+	u32 acpu_vote_msk1;
+	u32 acpu_votestat0_msk;
+	u32 acpu_votestat1_msk;
+	u32 mcu_voteen;
+	u32 mcu_votedis;
+	u32 mcu_votestat;
+
+	u32 unknown_18_1;
+
+	u32 mcu_vote_msk0;	/*0x940*/
+	u32 mcu_vote_msk1;
+	u32 mcu_vote_votestat0_msk;
+	u32 mcu_vote_votestat1_msk;
+
+	u32 unknown_18_1_2[4];
+
+	u32 mcu_vote_vote1en;	/*0x960*/
+	u32 mcu_vote_vote1dis;
+	u32 mcu_vote_vote1stat;
+
+	u32 unknown_18_2;
+
+	u32 mcu_vote_vote1_msk0;/*0x970*/
+	u32 mcu_vote_vote1_msk1;
+	u32 mcu_vote_vote1stat0_msk;
+	u32 mcu_vote_vote1stat1_msk;
+	u32 mcu_vote_vote2en;
+	u32 mcu_vote_vote2dis;
+	u32 mcu_vote_vote2stat;
+
+	u32 unknown_18_3;
+
+	u32 mcu_vote2_msk0;	/*0x990*/
+	u32 mcu_vote2_msk1;
+	u32 mcu_vote2stat0_msk;
+	u32 mcu_vote2stat1_msk;
+	u32 vote_ctrl;
+	u32 vote_stat;		/*0x9a4*/
+
+	u32 unknown_19[342];
+
+	u32 econum;		/*0xf00*/
+
+	u32 unknown_20_1[3];
+
+	u32 scchipid;		/*0xf10*/
+
+	u32 unknown_20_2[2];
+
+	u32 scsocid;		/*0xf1c*/
+
+	u32 unknown_20[48];
+
+	u32 soc_fpga_rtl_def;	/*0xfe0*/
+	u32 soc_fpga_pr_def;
+	u32 soc_fpga_res_def0;
+	u32 soc_fpga_res_def1;	/*0xfec*/
+};
+
+/* ctrl0 bit definitions */
+
+#define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL			0x004
+#define ALWAYSON_SC_SYS_CTRL0_MODE_MASK				0x007
+
+/* ctrl1 bit definitions */
+
+#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG			(1 << 0)
+#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM			(1 << 1)
+#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP			(1 << 2)
+#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL			(1 << 3)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG		(1 << 4)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG		(1 << 6)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG			(1 << 7)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG		(1 << 8)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG			(1 << 9)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG		(1 << 10)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1		(1 << 11)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT			(1 << 12)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT			(1 << 13)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG			(1 << 15)
+#define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK		(1 << 16)
+#define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK		(1 << 17)
+#define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK			(1 << 18)
+#define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK			(1 << 19)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK		(1 << 20)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK	(1 << 22)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK		(1 << 23)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK	(1 << 24)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK		(1 << 25)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK		(1 << 26)
+#define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK		(1 << 27)
+#define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK		(1 << 28)
+#define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK		(1 << 29)
+#define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK		(1 << 31)
+
+/* ctrl2 bit definitions */
+
+#define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR		(1 << 26)
+#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR		(1 << 27)
+#define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR		(1 << 28)
+#define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR		(1 << 29)
+#define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR		(1 << 30)
+#define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR		(1 << 31)
+
+/* stat0 bit definitions */
+
+#define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT			(1 << 25)
+#define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT			(1 << 26)
+#define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT			(1 << 27)
+#define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT		(1 << 28)
+#define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT		(1 << 29)
+#define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT			(1 << 30)
+#define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT			(1 << 31)
+
+/* stat1 bit definitions */
+
+#define ALWAYSON_SC_SYS_STAT1_MODE_STATUS			(1 << 0)
+#define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK			(1 << 16)
+#define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK			(1 << 17)
+#define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK			(1 << 19)
+#define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT			(1 << 20)
+#define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG			(1 << 27)
+#define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK		(1 << 28)
+#define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE		(1 << 29)
+
+/* ctrl3 bit definitions */
+
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3			0x003
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK			0x007
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT		(1 << 3)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG		(1 << 4)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1		(1 << 8)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0		(1 << 9)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD		(1 << 10)
+#define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED	(1 << 11)
+
+/* clk4_en bit definitions */
+
+#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU			(1 << 0)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP			(1 << 3)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0		(1 << 4)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1		(1 << 5)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0		(1 << 6)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1		(1 << 7)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S			(1 << 8)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS			(1 << 9)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC			(1 << 10)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC			(1 << 11)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0			(1 << 12)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1			(1 << 13)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2			(1 << 14)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0			(1 << 15)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1			(1 << 16)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2			(1 << 17)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3			(1 << 18)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4			(1 << 19)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5			(1 << 20)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6			(1 << 21)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7			(1 << 22)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8			(1 << 23)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0			(1 << 24)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0			(1 << 25)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1			(1 << 26)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI			(1 << 27)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH		(1 << 28)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON		(1 << 29)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM			(1 << 30)
+#define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD			(1 << 31)
+
+/* clk5_en bit definitions */
+
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU		(1 << 0)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU		(1 << 1)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU		(1 << 2)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU		(1 << 3)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU		(1 << 16)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU		(1 << 17)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU			(1 << 18)
+#define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU		(1 << 19)
+
+/* rst4_dis bit definitions */
+
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N		(1 << 0)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N		(1 << 1)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N		(1 << 2)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N		(1 << 3)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N		(1 << 4)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N		(1 << 5)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N		(1 << 6)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N		(1 << 7)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N		(1 << 8)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N		(1 << 9)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N		(1 << 10)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N		(1 << 12)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N		(1 << 13)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N		(1 << 14)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N		(1 << 15)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N		(1 << 16)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N		(1 << 17)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N		(1 << 18)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N		(1 << 19)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N		(1 << 20)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N		(1 << 21)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N		(1 << 22)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N		(1 << 23)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N		(1 << 24)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N		(1 << 25)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N		(1 << 26)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N		(1 << 27)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N		(1 << 28)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N		(1 << 29)
+#define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB		(1 << 30)
+
+#define PCLK_TIMER1						(1 << 16)
+#define PCLK_TIMER0						(1 << 15)
+
+#endif /* __HI6220_ALWAYSON_H__ */
diff --git a/arch/arm/include/asm/arch-hi6220/periph.h b/arch/arm/include/asm/arch-hi6220/periph.h
new file mode 100644
index 0000000..edec213
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/periph.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals required for pinmux configuration. List will
+ * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
+ *
+ */
+enum periph_id {
+	PERIPH_ID_UART0 = 36,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+	PERIPH_ID_UART3,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_SDMMC0 = 72,
+	PERIPH_ID_SDMMC1,
+
+	PERIPH_ID_NONE = -1,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/include/asm/arch-hi6220/pinmux.h b/arch/arm/include/asm/arch-hi6220/pinmux.h
new file mode 100644
index 0000000..b4a9957
--- /dev/null
+++ b/arch/arm/include/asm/arch-hi6220/pinmux.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ */
+
+#ifndef __ASM_ARM_ARCH_PINMUX_H
+#define __ASM_ARM_ARCH_PINMUX_H
+
+#include "periph.h"
+
+
+/* iomg bit definition */
+#define MUX_M0          0
+#define MUX_M1          1
+#define MUX_M2          2
+#define MUX_M3          3
+#define MUX_M4          4
+#define MUX_M5          5
+#define MUX_M6          6
+#define MUX_M7          7
+
+/* iocg bit definition */
+#define PULL_MASK       (3)
+#define PULL_DIS        (0)
+#define PULL_UP         (1 << 0)
+#define PULL_DOWN       (1 << 1)
+
+/* drive strength definition */
+#define DRIVE_MASK      (7 << 4)
+#define DRIVE1_02MA     (0 << 4)
+#define DRIVE1_04MA     (1 << 4)
+#define DRIVE1_08MA     (2 << 4)
+#define DRIVE1_10MA     (3 << 4)
+#define DRIVE2_02MA     (0 << 4)
+#define DRIVE2_04MA     (1 << 4)
+#define DRIVE2_08MA     (2 << 4)
+#define DRIVE2_10MA     (3 << 4)
+#define DRIVE3_04MA     (0 << 4)
+#define DRIVE3_08MA     (1 << 4)
+#define DRIVE3_12MA     (2 << 4)
+#define DRIVE3_16MA     (3 << 4)
+#define DRIVE3_20MA     (4 << 4)
+#define DRIVE3_24MA     (5 << 4)
+#define DRIVE3_32MA     (6 << 4)
+#define DRIVE3_40MA     (7 << 4)
+#define DRIVE4_02MA     (0 << 4)
+#define DRIVE4_04MA     (2 << 4)
+#define DRIVE4_08MA     (4 << 4)
+#define DRIVE4_10MA     (6 << 4)
+
+#define HI6220_PINMUX0_BASE 0xf7010000
+#define HI6220_PINMUX1_BASE 0xf7010800
+
+#ifndef	__ASSEMBLY__
+
+/* maybe more registers, but highest used is 123 */
+#define REG_NUM 123
+
+struct hi6220_pinmux0_regs {
+	uint32_t	iomg[REG_NUM];
+};
+
+struct hi6220_pinmux1_regs {
+	uint32_t	iocfg[REG_NUM];
+};
+
+#endif
+
+/**
+ * Configures the pinmux for a particular peripheral.
+ *
+ * This function will configure the peripheral pinmux along with
+ * pull-up/down and drive strength.
+ *
+ * @param peripheral	peripheral to be configured
+ * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
+ */
+int hi6220_pinmux_config(int peripheral);
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
new file mode 100644
index 0000000..3a85492
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#define MXC_CPU_MX23		0x23
+#define MXC_CPU_MX25		0x25
+#define MXC_CPU_MX27		0x27
+#define MXC_CPU_MX28		0x28
+#define MXC_CPU_MX31		0x31
+#define MXC_CPU_MX35		0x35
+#define MXC_CPU_MX51		0x51
+#define MXC_CPU_MX53		0x53
+#define MXC_CPU_MX6SL		0x60
+#define MXC_CPU_MX6DL		0x61
+#define MXC_CPU_MX6SX		0x62
+#define MXC_CPU_MX6Q		0x63
+#define MXC_CPU_MX6UL		0x64
+#define MXC_CPU_MX6ULL		0x65
+#define MXC_CPU_MX6ULZ		0x6B
+#define MXC_CPU_MX6SOLO		0x66 /* dummy */
+#define MXC_CPU_MX6SLL		0x67
+#define MXC_CPU_MX6D		0x6A
+#define MXC_CPU_MX6DP		0x68
+#define MXC_CPU_MX6QP		0x69
+#define MXC_CPU_MX7S		0x71 /* dummy ID */
+#define MXC_CPU_MX7D		0x72
+#define MXC_CPU_IMX8MQ		0x82
+#define MXC_CPU_IMX8MM		0x85 /* dummy ID */
+#define MXC_CPU_IMX8MML		0x86 /* dummy ID */
+#define MXC_CPU_IMX8MMD		0x87 /* dummy ID */
+#define MXC_CPU_IMX8MMDL	0x88 /* dummy ID */
+#define MXC_CPU_IMX8MMS		0x89 /* dummy ID */
+#define MXC_CPU_IMX8MMSL	0x8a /* dummy ID */
+#define MXC_CPU_IMX8QXP_A0	0x90 /* dummy ID */
+#define MXC_CPU_IMX8QM		0x91 /* dummy ID */
+#define MXC_CPU_IMX8QXP		0x92 /* dummy ID */
+#define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
+#define MXC_CPU_VF610		0xF6 /* dummy ID */
+
+#define MXC_SOC_MX6		0x60
+#define MXC_SOC_MX7		0x70
+#define MXC_SOC_IMX8M		0x80
+#define MXC_SOC_IMX8		0x90 /* dummy */
+#define MXC_SOC_MX7ULP		0xE0 /* dummy */
+
+#define CHIP_REV_1_0            0x10
+#define CHIP_REV_1_1            0x11
+#define CHIP_REV_1_2            0x12
+#define CHIP_REV_1_5            0x15
+#define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_1            0x21
+#define CHIP_REV_2_5            0x25
+#define CHIP_REV_3_0            0x30
+
+#define CHIP_REV_A		0x0
+#define CHIP_REV_B		0x1
+
+#define BOARD_REV_1_0           0x0
+#define BOARD_REV_2_0           0x1
+#define BOARD_VER_OFFSET        0x8
+
+#define CS0_128					0
+#define CS0_64M_CS1_64M				1
+#define CS0_64M_CS1_32M_CS2_32M			2
+#define CS0_32M_CS1_32M_CS2_32M_CS3_32M		3
+
+u32 get_imx_reset_cause(void);
+ulong get_systemPLLCLK(void);
+ulong get_FCLK(void);
+ulong get_HCLK(void);
+ulong get_BCLK(void);
+ulong get_PERCLK1(void);
+ulong get_PERCLK2(void);
+ulong get_PERCLK3(void);
diff --git a/arch/arm/include/asm/arch-imx8/boot0.h b/arch/arm/include/asm/arch-imx8/boot0.h
new file mode 100644
index 0000000..5ce781a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/boot0.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#if defined(CONFIG_SPL_BUILD)
+	/*
+	 * We use absolute address not PC relative address to jump.
+	 * When running SPL on iMX8, the A core starts at address 0, a alias to OCRAM 0x100000,
+	 * our linker address for SPL is from 0x100000. So using absolute address can jump to
+	 * the OCRAM address from the alias.
+	 * The alias only map first 96KB of OCRAM, so this require the SPL size can't beyond 96KB.
+	 * But when using SPL DM, the size increase significantly and may exceed 96KB.
+	 * That's why we have to jump to OCRAM.
+	 */
+
+	ldr	x0, =reset
+	br	x0
+#else
+	b	reset
+#endif
diff --git a/arch/arm/include/asm/arch-imx8/clock.h b/arch/arm/include/asm/arch-imx8/clock.h
new file mode 100644
index 0000000..bea1571
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/clock.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8_CLOCK_H__
+#define __ASM_ARCH_IMX8_CLOCK_H__
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_UART_CLK,
+	MXC_CSPI_CLK,
+	MXC_AXI_CLK,
+	MXC_DDR_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_I2C_CLK,
+	MXC_FEC_CLK,
+};
+
+u32 mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_IMX8_CLOCK_H__ */
diff --git a/arch/arm/include/asm/arch-imx8/gpio.h b/arch/arm/include/asm/arch-imx8/gpio.h
new file mode 100644
index 0000000..24cfde3
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/gpio.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8_GPIO_H
+#define __ASM_ARCH_IMX8_GPIO_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/* GPIO registers */
+struct gpio_regs {
+	u32 gpio_dr;	/* data */
+	u32 gpio_dir;	/* direction */
+	u32 gpio_psr;	/* pad satus */
+};
+#endif
+
+/* IMX8 the GPIO index is from 0 not 1 */
+#define IMX_GPIO_NR(port, index)		(((port) * 32) + ((index) & 31))
+
+#endif /* __ASM_ARCH_IMX8_GPIO_H */
diff --git a/arch/arm/include/asm/arch-imx8/image.h b/arch/arm/include/asm/arch-imx8/image.h
new file mode 100644
index 0000000..c1e5700
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/image.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __CONTAINER_HEADER_H_
+#define __CONTAINER_HEADER_H_
+
+#include <linux/sizes.h>
+#include <linux/types.h>
+
+#define IV_MAX_LEN			32
+#define HASH_MAX_LEN			64
+
+#define CONTAINER_HDR_ALIGNMENT 0x400
+#define CONTAINER_HDR_EMMC_OFFSET 0
+#define CONTAINER_HDR_MMCSD_OFFSET SZ_32K
+#define CONTAINER_HDR_QSPI_OFFSET SZ_4K
+#define CONTAINER_HDR_NAND_OFFSET SZ_128M
+
+struct container_hdr {
+	u8 version;
+	u8 length_lsb;
+	u8 length_msb;
+	u8 tag;
+	u32 flags;
+	u16 sw_version;
+	u8 fuse_version;
+	u8 num_images;
+	u16 sig_blk_offset;
+	u16 reserved;
+} __packed;
+
+struct boot_img_t {
+	u32 offset;
+	u32 size;
+	u64 dst;
+	u64 entry;
+	u32 hab_flags;
+	u32 meta;
+	u8 hash[HASH_MAX_LEN];
+	u8 iv[IV_MAX_LEN];
+} __packed;
+
+struct signature_block_hdr {
+	u8 version;
+	u8 length_lsb;
+	u8 length_msb;
+	u8 tag;
+	u16 srk_table_offset;
+	u16 cert_offset;
+	u16 blob_offset;
+	u16 signature_offset;
+	u32 reserved;
+} __packed;
+#endif
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
new file mode 100644
index 0000000..6333ff4
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8_REGS_H__
+#define __ASM_ARCH_IMX8_REGS_H__
+
+#define ARCH_MXC
+
+#define LPUART_BASE		0x5A060000
+
+#define GPT1_BASE_ADDR		0x5D140000
+#define SCU_LPUART_BASE		0x33220000
+#define GPIO1_BASE_ADDR		0x5D080000
+#define GPIO2_BASE_ADDR		0x5D090000
+#define GPIO3_BASE_ADDR		0x5D0A0000
+#define GPIO4_BASE_ADDR		0x5D0B0000
+#define GPIO5_BASE_ADDR		0x5D0C0000
+#define GPIO6_BASE_ADDR		0x5D0D0000
+#define GPIO7_BASE_ADDR		0x5D0E0000
+#define GPIO8_BASE_ADDR		0x5D0F0000
+#define LPI2C1_BASE_ADDR	0x5A800000
+#define LPI2C2_BASE_ADDR	0x5A810000
+#define LPI2C3_BASE_ADDR	0x5A820000
+#define LPI2C4_BASE_ADDR	0x5A830000
+#define LPI2C5_BASE_ADDR	0x5A840000
+
+#ifdef CONFIG_IMX8QXP
+#define LVDS0_PHYCTRL_BASE	0x56221000
+#define LVDS1_PHYCTRL_BASE	0x56241000
+#define MIPI0_SS_BASE		0x56220000
+#define MIPI1_SS_BASE		0x56240000
+#endif
+
+#define APBH_DMA_ARB_BASE_ADDR	0x5B810000
+#define APBH_DMA_ARB_END_ADDR	0x5B81FFFF
+#define MXS_APBH_BASE		APBH_DMA_ARB_BASE_ADDR
+
+#define MXS_GPMI_BASE		(APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE		(APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
+#define PASS_OVER_INFO_ADDR	0x0010fe00
+
+#define USB_BASE_ADDR		0x5b0d0000
+#define USB_PHY0_BASE_ADDR	0x5b100000
+
+#endif /* __ASM_ARCH_IMX8_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-imx8/imx8-pins.h b/arch/arm/include/asm/arch-imx8/imx8-pins.h
new file mode 100644
index 0000000..2130298
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/imx8-pins.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8_PINS_H__
+#define __ASM_ARCH_IMX8_PINS_H__
+
+#if defined(CONFIG_IMX8QXP)
+#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+#elif defined(CONFIG_IMX8QM)
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+#else
+#error "No pin header"
+#endif
+
+#endif	/* __ASM_ARCH_IMX8_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-imx8/iomux.h b/arch/arm/include/asm/arch-imx8/iomux.h
new file mode 100644
index 0000000..bedd01b
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/iomux.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8_IOMUX_H__
+#define __ASM_ARCH_IMX8_IOMUX_H__
+
+/*
+ * We use 64bits value for iomux settings.
+ * High 32bits are used for padring register value,
+ * low 16bits are used for pin index.
+ */
+typedef u64 iomux_cfg_t;
+
+#define PADRING_IFMUX_EN_SHIFT		31
+#define PADRING_IFMUX_EN_MASK		BIT(31)
+#define PADRING_GP_EN_SHIFT		30
+#define PADRING_GP_EN_MASK		BIT(30)
+#define PADRING_IFMUX_SHIFT		27
+#define PADRING_IFMUX_MASK		GENMASK(29, 27)
+#define PADRING_CONFIG_SHIFT		25
+#define PADRING_LPCONFIG_SHIFT		23
+#define PADRING_PULL_SHIFT		5
+#define PADRING_DSE_SHIFT		0
+
+#define MUX_PAD_CTRL_SHIFT	32
+#define MUX_PAD_CTRL_MASK	((iomux_cfg_t)0xFFFFFFFF << MUX_PAD_CTRL_SHIFT)
+#define MUX_PAD_CTRL(x)		((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+#define MUX_MODE_SHIFT		(PADRING_IFMUX_SHIFT + MUX_PAD_CTRL_SHIFT)
+#define MUX_MODE_MASK		((iomux_cfg_t)0x7 << MUX_MODE_SHIFT)
+#define PIN_ID_MASK		((iomux_cfg_t)0xFFFF)
+
+/* Valid mux alt0 to alt7 */
+#define MUX_MODE_ALT(x)		(((iomux_cfg_t)(x) << MUX_MODE_SHIFT) & \
+				 MUX_MODE_MASK)
+
+void imx8_iomux_setup_pad(iomux_cfg_t pad);
+void imx8_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list, u32 count);
+#endif	/* __ASM_ARCH_IMX8_IOMUX_H__ */
diff --git a/arch/arm/include/asm/arch-imx8/power-domain.h b/arch/arm/include/asm/arch-imx8/power-domain.h
new file mode 100644
index 0000000..1396008
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/power-domain.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef _ASM_ARCH_IMX8_POWER_DOMAIN_H
+#define _ASM_ARCH_IMX8_POWER_DOMAIN_H
+
+#include <asm/arch/sci/types.h>
+
+struct imx8_power_domain_platdata {
+	sc_rsrc_t resource_id;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h
new file mode 100644
index 0000000..8e1e9bb
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2017-2018 NXP
+ *
+ */
+
+#ifndef SC_RPC_H
+#define SC_RPC_H
+
+/* Note: Check SCFW API Released DOC before you want to modify something */
+#define SC_RPC_VERSION          1U
+
+#define SC_RPC_MAX_MSG          8U
+
+#define RPC_VER(MSG)            ((MSG)->version)
+#define RPC_SIZE(MSG)           ((MSG)->size)
+#define RPC_SVC(MSG)            ((MSG)->svc)
+#define RPC_FUNC(MSG)           ((MSG)->func)
+#define RPC_R8(MSG)             ((MSG)->func)
+#define RPC_I32(MSG, IDX)       ((MSG)->DATA.i32[(IDX) / 4U])
+#define RPC_I16(MSG, IDX)       ((MSG)->DATA.i16[(IDX) / 2U])
+#define RPC_I8(MSG, IDX)        ((MSG)->DATA.i8[(IDX)])
+#define RPC_U32(MSG, IDX)       ((MSG)->DATA.u32[(IDX) / 4U])
+#define RPC_U16(MSG, IDX)       ((MSG)->DATA.u16[(IDX) / 2U])
+#define RPC_U8(MSG, IDX)        ((MSG)->DATA.u8[(IDX)])
+
+#define SC_RPC_SVC_UNKNOWN      0U
+#define SC_RPC_SVC_RETURN       1U
+#define SC_RPC_SVC_PM           2U
+#define SC_RPC_SVC_RM           3U
+#define SC_RPC_SVC_TIMER        5U
+#define SC_RPC_SVC_PAD          6U
+#define SC_RPC_SVC_MISC         7U
+#define SC_RPC_SVC_IRQ          8U
+#define SC_RPC_SVC_SECO         9U
+#define SC_RPC_SVC_ABORT        10U
+
+
+/* Types */
+
+struct sc_rpc_msg_s {
+	u8 version;
+	u8 size;
+	u8 svc;
+	u8 func;
+	union {
+		s32 i32[(SC_RPC_MAX_MSG - 1U)];
+		s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U];
+		s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U];
+		u32 u32[(SC_RPC_MAX_MSG - 1U)];
+		u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U];
+		u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U];
+	} DATA;
+};
+
+/* PM RPC */
+#define PM_FUNC_UNKNOWN				0
+#define PM_FUNC_SET_SYS_POWER_MODE		19U
+#define PM_FUNC_SET_PARTITION_POWER_MODE	1U
+#define PM_FUNC_GET_SYS_POWER_MODE		2U
+#define PM_FUNC_SET_RESOURCE_POWER_MODE		3U
+#define PM_FUNC_GET_RESOURCE_POWER_MODE		4U
+#define PM_FUNC_REQ_LOW_POWER_MODE		16U
+#define PM_FUNC_REQ_CPU_LOW_POWER_MODE		20U
+#define PM_FUNC_SET_CPU_RESUME_ADDR		17U
+#define PM_FUNC_SET_CPU_RESUME			21U
+#define PM_FUNC_REQ_SYS_IF_POWER_MODE		18U
+#define PM_FUNC_SET_CLOCK_RATE			5U
+#define PM_FUNC_GET_CLOCK_RATE			6U
+#define PM_FUNC_CLOCK_ENABLE			7U
+#define PM_FUNC_SET_CLOCK_PARENT		14U
+#define PM_FUNC_GET_CLOCK_PARENT		15U
+#define PM_FUNC_RESET				13U
+#define PM_FUNC_RESET_REASON			10U
+#define PM_FUNC_BOOT				8U
+#define PM_FUNC_REBOOT				9U
+#define PM_FUNC_REBOOT_PARTITION		12U
+#define PM_FUNC_CPU_START			11U
+#define PM_FUNC_IS_PARTITION_STARTED 24U
+
+/* MISC RPC */
+#define MISC_FUNC_UNKNOWN			0
+#define MISC_FUNC_SET_CONTROL			1U
+#define MISC_FUNC_GET_CONTROL			2U
+#define MISC_FUNC_SET_MAX_DMA_GROUP		4U
+#define MISC_FUNC_SET_DMA_GROUP			5U
+#define MISC_FUNC_SECO_IMAGE_LOAD		8U
+#define MISC_FUNC_SECO_AUTHENTICATE		9U
+#define MISC_FUNC_SECO_FUSE_WRITE		20U
+#define MISC_FUNC_SECO_ENABLE_DEBUG		21U
+#define MISC_FUNC_SECO_FORWARD_LIFECYCLE	22U
+#define MISC_FUNC_SECO_RETURN_LIFECYCLE		23U
+#define MISC_FUNC_SECO_BUILD_INFO		24U
+#define MISC_FUNC_DEBUG_OUT			10U
+#define MISC_FUNC_WAVEFORM_CAPTURE		6U
+#define MISC_FUNC_BUILD_INFO			15U
+#define MISC_FUNC_UNIQUE_ID			19U
+#define MISC_FUNC_SET_ARI			3U
+#define MISC_FUNC_BOOT_STATUS			7U
+#define MISC_FUNC_BOOT_DONE			14U
+#define MISC_FUNC_OTP_FUSE_READ			11U
+#define MISC_FUNC_OTP_FUSE_WRITE		17U
+#define MISC_FUNC_SET_TEMP			12U
+#define MISC_FUNC_GET_TEMP			13U
+#define MISC_FUNC_GET_BOOT_DEV			16U
+#define MISC_FUNC_GET_BUTTON_STATUS		18U
+
+/* PAD RPC */
+#define PAD_FUNC_UNKNOWN			0
+#define PAD_FUNC_SET_MUX			1U
+#define PAD_FUNC_GET_MUX			6U
+#define PAD_FUNC_SET_GP				2U
+#define PAD_FUNC_GET_GP				7U
+#define PAD_FUNC_SET_WAKEUP			4U
+#define PAD_FUNC_GET_WAKEUP			9U
+#define PAD_FUNC_SET_ALL			5U
+#define PAD_FUNC_GET_ALL			10U
+#define PAD_FUNC_SET				15U
+#define PAD_FUNC_GET				16U
+#define PAD_FUNC_SET_GP_28FDSOI			11U
+#define PAD_FUNC_GET_GP_28FDSOI			12U
+#define PAD_FUNC_SET_GP_28FDSOI_HSIC		3U
+#define PAD_FUNC_GET_GP_28FDSOI_HSIC		8U
+#define PAD_FUNC_SET_GP_28FDSOI_COMP		13U
+#define PAD_FUNC_GET_GP_28FDSOI_COMP		14U
+
+/* RM RPC */
+#define RM_FUNC_UNKNOWN				0
+#define RM_FUNC_PARTITION_ALLOC			1U
+#define RM_FUNC_SET_CONFIDENTIAL		31U
+#define RM_FUNC_PARTITION_FREE			2U
+#define RM_FUNC_GET_DID				26U
+#define RM_FUNC_PARTITION_STATIC		3U
+#define RM_FUNC_PARTITION_LOCK			4U
+#define RM_FUNC_GET_PARTITION			5U
+#define RM_FUNC_SET_PARENT			6U
+#define RM_FUNC_MOVE_ALL			7U
+#define RM_FUNC_ASSIGN_RESOURCE			8U
+#define RM_FUNC_SET_RESOURCE_MOVABLE		9U
+#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE		28U
+#define RM_FUNC_SET_MASTER_ATTRIBUTES		10U
+#define RM_FUNC_SET_MASTER_SID			11U
+#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS	12U
+#define RM_FUNC_IS_RESOURCE_OWNED		13U
+#define RM_FUNC_GET_RESOURCE_OWNER 33U
+#define RM_FUNC_IS_RESOURCE_MASTER		14U
+#define RM_FUNC_IS_RESOURCE_PERIPHERAL		15U
+#define RM_FUNC_GET_RESOURCE_INFO		16U
+#define RM_FUNC_MEMREG_ALLOC			17U
+#define RM_FUNC_MEMREG_SPLIT			29U
+#define RM_FUNC_MEMREG_FREE			18U
+#define RM_FUNC_FIND_MEMREG			30U
+#define RM_FUNC_ASSIGN_MEMREG			19U
+#define RM_FUNC_SET_MEMREG_PERMISSIONS		20U
+#define RM_FUNC_IS_MEMREG_OWNED			21U
+#define RM_FUNC_GET_MEMREG_INFO			22U
+#define RM_FUNC_ASSIGN_PAD			23U
+#define RM_FUNC_SET_PAD_MOVABLE			24U
+#define RM_FUNC_IS_PAD_OWNED			25U
+#define RM_FUNC_DUMP				27U
+
+/* SECO RPC */
+#define SECO_FUNC_UNKNOWN			0
+#define SECO_FUNC_IMAGE_LOAD			1U
+#define SECO_FUNC_AUTHENTICATE			2U
+#define SECO_FUNC_FORWARD_LIFECYCLE		3U
+#define SECO_FUNC_RETURN_LIFECYCLE		4U
+#define SECO_FUNC_COMMIT			5U
+#define SECO_FUNC_ATTEST_MODE			6U
+#define SECO_FUNC_ATTEST			7U
+#define SECO_FUNC_GET_ATTEST_PKEY		8U
+#define SECO_FUNC_GET_ATTEST_SIGN		9U
+#define SECO_FUNC_ATTEST_VERIFY			10U
+#define SECO_FUNC_GEN_KEY_BLOB			11U
+#define SECO_FUNC_LOAD_KEY			12U
+#define SECO_FUNC_GET_MP_KEY			13U
+#define SECO_FUNC_UPDATE_MPMR			14U
+#define SECO_FUNC_GET_MP_SIGN			15U
+#define SECO_FUNC_BUILD_INFO			16U
+#define SECO_FUNC_CHIP_INFO			17U
+#define SECO_FUNC_ENABLE_DEBUG			18U
+#define SECO_FUNC_GET_EVENT			19U
+#define SECO_FUNC_FUSE_WRITE			20U
+
+#endif /* SC_RPC_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h
new file mode 100644
index 0000000..14ee6f9
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef _SC_SCI_H
+#define _SC_SCI_H
+
+#include <asm/arch/sci/types.h>
+#include <asm/arch/sci/svc/misc/api.h>
+#include <asm/arch/sci/svc/pad/api.h>
+#include <asm/arch/sci/svc/pm/api.h>
+#include <asm/arch/sci/svc/rm/api.h>
+#include <asm/arch/sci/svc/seco/api.h>
+#include <asm/arch/sci/rpc.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <linux/errno.h>
+
+static inline int sc_err_to_linux(sc_err_t err)
+{
+	int ret;
+
+	switch (err) {
+	case SC_ERR_NONE:
+		return 0;
+	case SC_ERR_VERSION:
+	case SC_ERR_CONFIG:
+	case SC_ERR_PARM:
+		ret = -EINVAL;
+		break;
+	case SC_ERR_NOACCESS:
+	case SC_ERR_LOCKED:
+	case SC_ERR_UNAVAILABLE:
+		ret = -EACCES;
+		break;
+	case SC_ERR_NOTFOUND:
+	case SC_ERR_NOPOWER:
+		ret = -ENODEV;
+		break;
+	case SC_ERR_IPC:
+		ret = -EIO;
+		break;
+	case SC_ERR_BUSY:
+		ret = -EBUSY;
+		break;
+	case SC_ERR_FAIL:
+		ret = -EIO;
+		break;
+	default:
+		ret = 0;
+		break;
+	}
+
+	debug("%s %d %d\n", __func__, err, ret);
+
+	return ret;
+}
+
+/* PM API*/
+int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+				  sc_pm_power_mode_t mode);
+int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+				  sc_pm_power_mode_t *mode);
+int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+			 sc_pm_clock_rate_t *rate);
+int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+			 sc_pm_clock_rate_t *rate);
+int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+		       sc_bool_t enable, sc_bool_t autog);
+int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
+			   sc_pm_clk_parent_t parent);
+int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
+		    sc_faddr_t address);
+sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
+
+/* MISC API */
+int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
+			sc_ctrl_t ctrl, u32 val);
+int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
+			u32 *val);
+void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
+void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
+void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
+int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
+int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
+		     s16 *celsius, s8 *tenths);
+
+/* RM API */
+sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
+int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start,
+		      sc_faddr_t addr_end);
+int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
+				 sc_rm_pt_t pt, sc_rm_perm_t perm);
+int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
+			  sc_faddr_t *addr_end);
+sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
+int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
+			  sc_bool_t isolated, sc_bool_t restricted,
+			  sc_bool_t grant, sc_bool_t coherent);
+int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
+int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
+int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
+int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
+int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
+sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
+int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
+			     sc_rm_pt_t *pt);
+
+/* PAD API */
+int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
+
+/* SMMU API */
+int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
+
+/* SECO API */
+int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
+			 sc_faddr_t addr);
+int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change);
+int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l,
+		      u32 *uid_h);
+void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
+int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
+int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
+			 sc_faddr_t export_addr, u16 max_size);
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
new file mode 100644
index 0000000..3629eb6
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef SC_MISC_API_H
+#define SC_MISC_API_H
+
+/* Defines for sc_misc_boot_status_t */
+#define SC_MISC_BOOT_STATUS_SUCCESS	0U	/* Success */
+#define SC_MISC_BOOT_STATUS_SECURITY	1U	/* Security violation */
+
+/* Defines for sc_misc_seco_auth_cmd_t */
+#define SC_MISC_SECO_AUTH_SECO_FW	0U   /* SECO Firmware */
+#define SC_MISC_SECO_AUTH_HDMI_TX_FW	1U   /* HDMI TX Firmware */
+#define SC_MISC_SECO_AUTH_HDMI_RX_FW	2U   /* HDMI RX Firmware */
+
+/* Defines for sc_misc_temp_t */
+#define SC_MISC_TEMP			0U	/* Temp sensor */
+#define SC_MISC_TEMP_HIGH		1U	/* Temp high alarm */
+#define SC_MISC_TEMP_LOW		2U	/* Temp low alarm */
+
+/* Defines for sc_misc_seco_auth_cmd_t */
+#define SC_MISC_AUTH_CONTAINER	0U	/* Authenticate container */
+#define SC_MISC_VERIFY_IMAGE	1U	/* Verify image */
+#define SC_MISC_REL_CONTAINER	2U	/* Release container */
+
+typedef u8 sc_misc_boot_status_t;
+typedef u8 sc_misc_temp_t;
+
+#endif /* SC_MISC_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
new file mode 100644
index 0000000..905c568
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef SC_PAD_API_H
+#define SC_PAD_API_H
+
+/* Defines for sc_pad_config_t */
+#define SC_PAD_CONFIG_NORMAL	0U	/* Normal */
+#define SC_PAD_CONFIG_OD	1U	/* Open Drain */
+#define SC_PAD_CONFIG_OD_IN	2U	/* Open Drain and input */
+#define SC_PAD_CONFIG_OUT_IN	3U	/* Output and input */
+
+/* Defines for sc_pad_iso_t */
+#define SC_PAD_ISO_OFF		0U	/* ISO latch is transparent */
+#define SC_PAD_ISO_EARLY	1U	/* Follow EARLY_ISO */
+#define SC_PAD_ISO_LATE		2U	/* Follow LATE_ISO */
+#define SC_PAD_ISO_ON		3U	/* ISO latched data is held */
+
+/* Defines for sc_pad_28fdsoi_dse_t */
+#define SC_PAD_28FDSOI_DSE_18V_1MA	0U /* Drive strength of 1mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_2MA	1U /* Drive strength of 2mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_4MA	2U /* Drive strength of 4mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_6MA	3U /* Drive strength of 6mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_8MA	4U /* Drive strength of 8mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_10MA	5U /* Drive strength of 10mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_12MA	6U /* Drive strength of 12mA for 1.8v */
+#define SC_PAD_28FDSOI_DSE_18V_HS	7U /* High-speed for 1.8v */
+#define SC_PAD_28FDSOI_DSE_33V_2MA	0U /* Drive strength of 2mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_4MA	1U /* Drive strength of 4mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_8MA	2U /* Drive strength of 8mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_33V_12MA	3U /* Drive strength of 12mA for 3.3v */
+#define SC_PAD_28FDSOI_DSE_DV_HIGH	0U /* High drive strength dual volt */
+#define SC_PAD_28FDSOI_DSE_DV_LOW	1U /* Low drive strength  dual volt */
+
+/* Defines for sc_pad_28fdsoi_ps_t */
+#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */
+#define SC_PAD_28FDSOI_PS_PU	1U /* Pull-up */
+#define SC_PAD_28FDSOI_PS_PD	2U /* Pull-down */
+#define SC_PAD_28FDSOI_PS_NONE	3U /* No pull (disabled) */
+
+/* Defines for sc_pad_28fdsoi_pus_t */
+#define SC_PAD_28FDSOI_PUS_30K_PD	0U /* 30K pull-down */
+#define SC_PAD_28FDSOI_PUS_100K_PU	1U /* 100K pull-up */
+#define SC_PAD_28FDSOI_PUS_3K_PU	2U /* 3K pull-up */
+#define SC_PAD_28FDSOI_PUS_30K_PU	3U /* 30K pull-up */
+
+/* Defines for sc_pad_wakeup_t */
+#define SC_PAD_WAKEUP_OFF	0U /* Off */
+#define SC_PAD_WAKEUP_CLEAR	1U /* Clears pending flag */
+#define SC_PAD_WAKEUP_LOW_LVL	4U /* Low level */
+#define SC_PAD_WAKEUP_FALL_EDGE	5U /* Falling edge */
+#define SC_PAD_WAKEUP_RISE_EDGE	6U /* Rising edge */
+#define SC_PAD_WAKEUP_HIGH_LVL	7U /* High-level */
+
+#endif /* SC_PAD_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
new file mode 100644
index 0000000..9008b85
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef SC_PM_API_H
+#define SC_PM_API_H
+
+/* Defines for sc_pm_power_mode_t */
+#define SC_PM_PW_MODE_OFF	0U /* Power off */
+#define SC_PM_PW_MODE_STBY	1U /* Power in standby */
+#define SC_PM_PW_MODE_LP	2U /* Power in low-power */
+#define SC_PM_PW_MODE_ON	3U /* Power on */
+
+/* Defines for sc_pm_clk_t */
+#define SC_PM_CLK_SLV_BUS	0U /* Slave bus clock */
+#define SC_PM_CLK_MST_BUS	1U /* Master bus clock */
+#define SC_PM_CLK_PER		2U /* Peripheral clock */
+#define SC_PM_CLK_PHY		3U /* Phy clock */
+#define SC_PM_CLK_MISC		4U /* Misc clock */
+#define SC_PM_CLK_MISC0		0U /* Misc 0 clock */
+#define SC_PM_CLK_MISC1		1U /* Misc 1 clock */
+#define SC_PM_CLK_MISC2		2U /* Misc 2 clock */
+#define SC_PM_CLK_MISC3		3U /* Misc 3 clock */
+#define SC_PM_CLK_MISC4		4U /* Misc 4 clock */
+#define SC_PM_CLK_CPU		2U /* CPU clock */
+#define SC_PM_CLK_PLL		4U /* PLL */
+#define SC_PM_CLK_BYPASS	4U /* Bypass clock */
+
+/* Defines for sc_pm_clk_mode_t */
+#define SC_PM_CLK_MODE_ROM_INIT		0U /* Clock is initialized by ROM. */
+#define SC_PM_CLK_MODE_OFF		1U /* Clock is disabled */
+#define SC_PM_CLK_MODE_ON		2U /* Clock is enabled. */
+#define SC_PM_CLK_MODE_AUTOGATE_SW	3U /* Clock is in SW autogate mode */
+#define SC_PM_CLK_MODE_AUTOGATE_HW	4U /* Clock is in HW autogate mode */
+#define SC_PM_CLK_MODE_AUTOGATE_SW_HW	5U /* Clock is in SW-HW autogate mode */
+
+typedef u8 sc_pm_power_mode_t;
+typedef u8 sc_pm_clk_t;
+typedef u8 sc_pm_clk_mode_t;
+typedef u8 sc_pm_clk_parent_t;
+typedef u32 sc_pm_clock_rate_t;
+
+#endif /* SC_PM_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
new file mode 100644
index 0000000..ed30388
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef SC_RM_API_H
+#define SC_RM_API_H
+
+#include <asm/arch/sci/types.h>
+
+/* Defines for type widths */
+#define SC_RM_PARTITION_W   5U      /* Width of sc_rm_pt_t */
+#define SC_RM_MEMREG_W      6U      /* Width of sc_rm_mr_t */
+#define SC_RM_DID_W         4U      /* Width of sc_rm_did_t */
+#define SC_RM_SID_W         6U      /* Width of sc_rm_sid_t */
+#define SC_RM_SPA_W         2U      /* Width of sc_rm_spa_t */
+#define SC_RM_PERM_W        3U      /* Width of sc_rm_perm_t */
+
+/* Defines for ALL parameters */
+#define SC_RM_PT_ALL        ((sc_rm_pt_t)UINT8_MAX)   /* All partitions */
+#define SC_RM_MR_ALL        ((sc_rm_mr_t)UINT8_MAX)   /* All memory regions */
+
+/* Defines for sc_rm_spa_t */
+#define SC_RM_SPA_PASSTHRU  0U   /* Pass through (attribute driven by master) */
+#define SC_RM_SPA_PASSSID   1U   /* Pass through and output on SID */
+#define SC_RM_SPA_ASSERT    2U   /* Assert (force to be secure/privileged) */
+#define SC_RM_SPA_NEGATE    3U   /* Negate (force to be non-secure/user) */
+
+/* Defines for sc_rm_perm_t */
+#define SC_RM_PERM_NONE         0U /* No access */
+#define SC_RM_PERM_SEC_R        1U /* Secure RO */
+#define SC_RM_PERM_SECPRIV_RW   2U /* Secure privilege R/W */
+#define SC_RM_PERM_SEC_RW       3U /* Secure R/W */
+#define SC_RM_PERM_NSPRIV_R     4U /* Secure R/W, non-secure privilege RO */
+#define SC_RM_PERM_NS_R         5U /* Secure R/W, non-secure RO */
+#define SC_RM_PERM_NSPRIV_RW    6U /* Secure R/W, non-secure privilege R/W */
+#define SC_RM_PERM_FULL         7U /* Full access */
+
+/* Types */
+
+/*!
+ * This type is used to declare a resource partition.
+ */
+typedef u8 sc_rm_pt_t;
+
+/*!
+ * This type is used to declare a memory region.
+ */
+typedef u8 sc_rm_mr_t;
+
+/*!
+ * This type is used to declare a resource domain ID used by the
+ * isolation HW.
+ */
+typedef u8 sc_rm_did_t;
+
+/*!
+ * This type is used to declare an SMMU StreamID.
+ */
+typedef u16 sc_rm_sid_t;
+
+/*!
+ * This type is a used to declare master transaction attributes.
+ */
+typedef u8 sc_rm_spa_t;
+
+typedef u8 sc_rm_perm_t;
+
+#endif /* SC_RM_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h
new file mode 100644
index 0000000..3ed0584
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef SC_SECO_API_H
+#define SC_SECO_API_H
+
+/* Includes */
+
+#include <asm/arch/sci/types.h>
+
+/* Defines */
+#define SC_SECO_AUTH_CONTAINER          0U   /* Authenticate container */
+#define SC_SECO_VERIFY_IMAGE            1U   /* Verify image */
+#define SC_SECO_REL_CONTAINER           2U   /* Release container */
+#define SC_SECO_AUTH_SECO_FW            3U   /* SECO Firmware */
+#define SC_SECO_AUTH_HDMI_TX_FW         4U   /* HDMI TX Firmware */
+#define SC_SECO_AUTH_HDMI_RX_FW         5U   /* HDMI RX Firmware */
+
+#define SC_SECO_RNG_STAT_UNAVAILABLE    0U  /* Unable to initialize the RNG */
+#define SC_SECO_RNG_STAT_INPROGRESS     1U  /* Initialization is on-going */
+#define SC_SECO_RNG_STAT_READY          2U  /* Initialized */
+
+/* Types */
+
+/*!
+ * This type is used to issue SECO authenticate commands.
+ */
+typedef u8 sc_seco_auth_cmd_t;
+
+/*!
+ * This type is used to return the RNG initialization status.
+ */
+typedef u32 sc_seco_rng_stat_t;
+
+#endif /* SC_SECO_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h
new file mode 100644
index 0000000..9eadc88
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/types.h
@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef SC_TYPES_H
+#define SC_TYPES_H
+
+/* Includes */
+#include <linux/types.h>
+
+/* Defines */
+/*
+ * This type is used to declare a handle for an IPC communication
+ * channel. Its meaning is specific to the IPC implementation.
+ */
+typedef u64 sc_ipc_t;
+
+/* Defines for common frequencies */
+#define SC_32KHZ            32768U   /* 32KHz */
+#define SC_10MHZ         10000000U   /* 10MHz */
+#define SC_20MHZ         20000000U   /* 20MHz */
+#define SC_25MHZ         25000000U   /* 25MHz */
+#define SC_27MHZ         27000000U   /* 27MHz */
+#define SC_40MHZ         40000000U   /* 40MHz */
+#define SC_45MHZ         45000000U   /* 45MHz */
+#define SC_50MHZ         50000000U   /* 50MHz */
+#define SC_60MHZ         60000000U   /* 60MHz */
+#define SC_66MHZ         66666666U   /* 66MHz */
+#define SC_74MHZ         74250000U   /* 74.25MHz */
+#define SC_80MHZ         80000000U   /* 80MHz */
+#define SC_83MHZ         83333333U   /* 83MHz */
+#define SC_84MHZ         84375000U   /* 84.37MHz */
+#define SC_100MHZ       100000000U   /* 100MHz */
+#define SC_125MHZ       125000000U   /* 125MHz */
+#define SC_133MHZ       133333333U   /* 133MHz */
+#define SC_135MHZ       135000000U   /* 135MHz */
+#define SC_150MHZ       150000000U   /* 150MHz */
+#define SC_160MHZ       160000000U   /* 160MHz */
+#define SC_166MHZ       166666666U   /* 166MHz */
+#define SC_175MHZ       175000000U   /* 175MHz */
+#define SC_180MHZ       180000000U   /* 180MHz */
+#define SC_200MHZ       200000000U   /* 200MHz */
+#define SC_250MHZ       250000000U   /* 250MHz */
+#define SC_266MHZ       266666666U   /* 266MHz */
+#define SC_300MHZ       300000000U   /* 300MHz */
+#define SC_312MHZ       312500000U   /* 312.5MHZ */
+#define SC_320MHZ       320000000U   /* 320MHz */
+#define SC_325MHZ       325000000U   /* 325MHz */
+#define SC_333MHZ       333333333U   /* 333MHz */
+#define SC_350MHZ       350000000U   /* 350MHz */
+#define SC_372MHZ       372000000U   /* 372MHz */
+#define SC_375MHZ       375000000U   /* 375MHz */
+#define SC_400MHZ       400000000U   /* 400MHz */
+#define SC_500MHZ       500000000U   /* 500MHz */
+#define SC_594MHZ       594000000U   /* 594MHz */
+#define SC_625MHZ       625000000U   /* 625MHz */
+#define SC_640MHZ       640000000U   /* 640MHz */
+#define SC_650MHZ       650000000U   /* 650MHz */
+#define SC_667MHZ       666666667U   /* 667MHz */
+#define SC_675MHZ       675000000U   /* 675MHz */
+#define SC_700MHZ       700000000U   /* 700MHz */
+#define SC_720MHZ       720000000U   /* 720MHz */
+#define SC_750MHZ       750000000U   /* 750MHz */
+#define SC_800MHZ       800000000U   /* 800MHz */
+#define SC_850MHZ       850000000U   /* 850MHz */
+#define SC_900MHZ       900000000U   /* 900MHz */
+#define SC_1000MHZ     1000000000U   /* 1GHz */
+#define SC_1060MHZ     1060000000U   /* 1.06GHz */
+#define SC_1188MHZ     1188000000U   /* 1.188GHz */
+#define SC_1260MHZ     1260000000U   /* 1.26GHz */
+#define SC_1280MHZ     1280000000U   /* 1.28GHz */
+#define SC_1300MHZ     1300000000U   /* 1.3GHz */
+#define SC_1400MHZ     1400000000U   /* 1.4GHz */
+#define SC_1500MHZ     1500000000U   /* 1.5GHz */
+#define SC_1600MHZ     1600000000U   /* 1.6GHz */
+#define SC_1800MHZ     1800000000U   /* 1.8GHz */
+#define SC_2000MHZ     2000000000U   /* 2.0GHz */
+#define SC_2112MHZ     2112000000U   /* 2.12GHz */
+
+/* Defines for 24M related frequencies */
+#define SC_8MHZ           8000000U   /* 8MHz */
+#define SC_12MHZ         12000000U   /* 12MHz */
+#define SC_19MHZ         19800000U   /* 19.8MHz */
+#define SC_24MHZ         24000000U   /* 24MHz */
+#define SC_48MHZ         48000000U   /* 48MHz */
+#define SC_120MHZ       120000000U   /* 120MHz */
+#define SC_132MHZ       132000000U   /* 132MHz */
+#define SC_144MHZ       144000000U   /* 144MHz */
+#define SC_192MHZ       192000000U   /* 192MHz */
+#define SC_211MHZ       211200000U   /* 211.2MHz */
+#define SC_240MHZ       240000000U   /* 240MHz */
+#define SC_264MHZ       264000000U   /* 264MHz */
+#define SC_352MHZ       352000000U   /* 352MHz */
+#define SC_360MHZ       360000000U   /* 360MHz */
+#define SC_384MHZ       384000000U   /* 384MHz */
+#define SC_396MHZ       396000000U   /* 396MHz */
+#define SC_432MHZ       432000000U   /* 432MHz */
+#define SC_480MHZ       480000000U   /* 480MHz */
+#define SC_600MHZ       600000000U   /* 600MHz */
+#define SC_744MHZ       744000000U   /* 744MHz */
+#define SC_792MHZ       792000000U   /* 792MHz */
+#define SC_864MHZ       864000000U   /* 864MHz */
+#define SC_960MHZ       960000000U   /* 960MHz */
+#define SC_1056MHZ     1056000000U   /* 1056MHz */
+#define SC_1104MHZ     1104000000U   /* 1104MHz */
+#define SC_1200MHZ     1200000000U   /* 1.2GHz */
+#define SC_1464MHZ     1464000000U   /* 1.464GHz */
+#define SC_2400MHZ     2400000000U   /* 2.4GHz */
+
+/* Defines for A/V related frequencies */
+#define SC_62MHZ         62937500U   /* 62.9375MHz */
+#define SC_755MHZ       755250000U   /* 755.25MHz */
+
+/* Defines for type widths */
+#define SC_FADDR_W      36U          /* Width of sc_faddr_t */
+#define SC_BOOL_W       1U           /* Width of sc_bool_t */
+#define SC_ERR_W        4U           /* Width of sc_err_t */
+#define SC_RSRC_W       10U          /* Width of sc_rsrc_t */
+#define SC_CTRL_W       6U           /* Width of sc_ctrl_t */
+
+/* Defines for sc_bool_t */
+#define SC_FALSE        ((sc_bool_t)0U)
+#define SC_TRUE         ((sc_bool_t)1U)
+
+/* Defines for sc_err_t */
+#define SC_ERR_NONE         0U      /* Success */
+#define SC_ERR_VERSION      1U      /* Incompatible API version */
+#define SC_ERR_CONFIG       2U      /* Configuration error */
+#define SC_ERR_PARM         3U      /* Bad parameter */
+#define SC_ERR_NOACCESS     4U      /* Permission error (no access) */
+#define SC_ERR_LOCKED       5U      /* Permission error (locked) */
+#define SC_ERR_UNAVAILABLE  6U      /* Unavailable (out of resources) */
+#define SC_ERR_NOTFOUND     7U      /* Not found */
+#define SC_ERR_NOPOWER      8U      /* No power */
+#define SC_ERR_IPC          9U      /* Generic IPC error */
+#define SC_ERR_BUSY         10U     /* Resource is currently busy/active */
+#define SC_ERR_FAIL         11U     /* General I/O failure */
+#define SC_ERR_LAST         12U
+
+/* Defines for sc_ctrl_t. */
+#define SC_C_TEMP                       0U
+#define SC_C_TEMP_HI                    1U
+#define SC_C_TEMP_LOW                   2U
+#define SC_C_PXL_LINK_MST1_ADDR         3U
+#define SC_C_PXL_LINK_MST2_ADDR         4U
+#define SC_C_PXL_LINK_MST_ENB           5U
+#define SC_C_PXL_LINK_MST1_ENB          6U
+#define SC_C_PXL_LINK_MST2_ENB          7U
+#define SC_C_PXL_LINK_SLV1_ADDR         8U
+#define SC_C_PXL_LINK_SLV2_ADDR         9U
+#define SC_C_PXL_LINK_MST_VLD           10U
+#define SC_C_PXL_LINK_MST1_VLD          11U
+#define SC_C_PXL_LINK_MST2_VLD          12U
+#define SC_C_SINGLE_MODE                13U
+#define SC_C_ID                         14U
+#define SC_C_PXL_CLK_POLARITY           15U
+#define SC_C_LINESTATE                  16U
+#define SC_C_PCIE_G_RST                 17U
+#define SC_C_PCIE_BUTTON_RST            18U
+#define SC_C_PCIE_PERST                 19U
+#define SC_C_PHY_RESET                  20U
+#define SC_C_PXL_LINK_RATE_CORRECTION   21U
+#define SC_C_PANIC                      22U
+#define SC_C_PRIORITY_GROUP             23U
+#define SC_C_TXCLK                      24U
+#define SC_C_CLKDIV                     25U
+#define SC_C_DISABLE_50                 26U
+#define SC_C_DISABLE_125                27U
+#define SC_C_SEL_125                    28U
+#define SC_C_MODE                       29U
+#define SC_C_SYNC_CTRL0                 30U
+#define SC_C_KACHUNK_CNT                31U
+#define SC_C_KACHUNK_SEL                32U
+#define SC_C_SYNC_CTRL1                 33U
+#define SC_C_DPI_RESET                  34U
+#define SC_C_MIPI_RESET                 35U
+#define SC_C_DUAL_MODE                  36U
+#define SC_C_VOLTAGE                    37U
+#define SC_C_PXL_LINK_SEL               38U
+#define SC_C_OFS_SEL                    39U
+#define SC_C_OFS_AUDIO                  40U
+#define SC_C_OFS_PERIPH                 41U
+#define SC_C_OFS_IRQ                    42U
+#define SC_C_RST0                       43U
+#define SC_C_RST1                       44U
+#define SC_C_SEL0                       45U
+#define SC_C_LAST                       46U
+
+#define SC_P_ALL        ((sc_pad_t)UINT16_MAX)   /* All pads */
+
+/* Types */
+
+/* This type is used to store a boolean */
+typedef u8 sc_bool_t;
+
+/* This type is used to store a system (full-size) address.  */
+typedef u64 sc_faddr_t;
+
+/* This type is used to indicate error response for most functions.  */
+typedef u8 sc_err_t;
+
+/*
+ * This type is used to indicate a resource. Resources include peripherals
+ * and bus masters (but not memory regions). Note items from list should
+ * never be changed or removed (only added to at the end of the list).
+ */
+typedef u16 sc_rsrc_t;
+
+/* This type is used to indicate a control.  */
+typedef u8 sc_ctrl_t;
+
+/*
+ * This type is used to indicate a pad. Valid values are SoC specific.
+ *
+ * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
+ */
+typedef u16 sc_pad_t;
+
+#endif /* SC_TYPES_H */
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h
new file mode 100644
index 0000000..0e981ae
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <asm/arch/sci/sci.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <linux/types.h>
+
+struct pass_over_info_t {
+	u16 barker;
+	u16 len;
+	u32 g_bt_cfg_shadow;
+	u32 card_address_mode;
+	u32 bad_block_count_met;
+	u32 g_ap_mu;
+};
+
+extern unsigned long boot_pointer[];
+void build_info(void);
+enum boot_device get_boot_device(void);
+int print_bootinfo(void);
+int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate);
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
new file mode 100644
index 0000000..dded6e0
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -0,0 +1,275 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan at nxp.com>
+ */
+
+#include <linux/bitops.h>
+
+#ifdef CONFIG_IMX8MQ
+#include <asm/arch/clock_imx8mq.h>
+#elif defined(CONFIG_IMX8MM)
+#include <asm/arch/clock_imx8mm.h>
+#else
+#error "Error no clock.h"
+#endif
+
+#define MHZ(X)	((X) * 1000000UL)
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_IPG_CLK,
+	MXC_CSPI_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_I2C_CLK,
+	MXC_UART_CLK,
+	MXC_QSPI_CLK,
+};
+
+enum clk_slice_type {
+	CORE_CLOCK_SLICE,
+	BUS_CLOCK_SLICE,
+	IP_CLOCK_SLICE,
+	AHB_CLOCK_SLICE,
+	IPG_CLOCK_SLICE,
+	CORE_SEL_CLOCK_SLICE,
+	DRAM_SEL_CLOCK_SLICE,
+};
+
+enum root_pre_div {
+	CLK_ROOT_PRE_DIV1 = 0,
+	CLK_ROOT_PRE_DIV2,
+	CLK_ROOT_PRE_DIV3,
+	CLK_ROOT_PRE_DIV4,
+	CLK_ROOT_PRE_DIV5,
+	CLK_ROOT_PRE_DIV6,
+	CLK_ROOT_PRE_DIV7,
+	CLK_ROOT_PRE_DIV8,
+};
+
+enum root_post_div {
+	CLK_ROOT_POST_DIV1 = 0,
+	CLK_ROOT_POST_DIV2,
+	CLK_ROOT_POST_DIV3,
+	CLK_ROOT_POST_DIV4,
+	CLK_ROOT_POST_DIV5,
+	CLK_ROOT_POST_DIV6,
+	CLK_ROOT_POST_DIV7,
+	CLK_ROOT_POST_DIV8,
+	CLK_ROOT_POST_DIV9,
+	CLK_ROOT_POST_DIV10,
+	CLK_ROOT_POST_DIV11,
+	CLK_ROOT_POST_DIV12,
+	CLK_ROOT_POST_DIV13,
+	CLK_ROOT_POST_DIV14,
+	CLK_ROOT_POST_DIV15,
+	CLK_ROOT_POST_DIV16,
+	CLK_ROOT_POST_DIV17,
+	CLK_ROOT_POST_DIV18,
+	CLK_ROOT_POST_DIV19,
+	CLK_ROOT_POST_DIV20,
+	CLK_ROOT_POST_DIV21,
+	CLK_ROOT_POST_DIV22,
+	CLK_ROOT_POST_DIV23,
+	CLK_ROOT_POST_DIV24,
+	CLK_ROOT_POST_DIV25,
+	CLK_ROOT_POST_DIV26,
+	CLK_ROOT_POST_DIV27,
+	CLK_ROOT_POST_DIV28,
+	CLK_ROOT_POST_DIV29,
+	CLK_ROOT_POST_DIV30,
+	CLK_ROOT_POST_DIV31,
+	CLK_ROOT_POST_DIV32,
+	CLK_ROOT_POST_DIV33,
+	CLK_ROOT_POST_DIV34,
+	CLK_ROOT_POST_DIV35,
+	CLK_ROOT_POST_DIV36,
+	CLK_ROOT_POST_DIV37,
+	CLK_ROOT_POST_DIV38,
+	CLK_ROOT_POST_DIV39,
+	CLK_ROOT_POST_DIV40,
+	CLK_ROOT_POST_DIV41,
+	CLK_ROOT_POST_DIV42,
+	CLK_ROOT_POST_DIV43,
+	CLK_ROOT_POST_DIV44,
+	CLK_ROOT_POST_DIV45,
+	CLK_ROOT_POST_DIV46,
+	CLK_ROOT_POST_DIV47,
+	CLK_ROOT_POST_DIV48,
+	CLK_ROOT_POST_DIV49,
+	CLK_ROOT_POST_DIV50,
+	CLK_ROOT_POST_DIV51,
+	CLK_ROOT_POST_DIV52,
+	CLK_ROOT_POST_DIV53,
+	CLK_ROOT_POST_DIV54,
+	CLK_ROOT_POST_DIV55,
+	CLK_ROOT_POST_DIV56,
+	CLK_ROOT_POST_DIV57,
+	CLK_ROOT_POST_DIV58,
+	CLK_ROOT_POST_DIV59,
+	CLK_ROOT_POST_DIV60,
+	CLK_ROOT_POST_DIV61,
+	CLK_ROOT_POST_DIV62,
+	CLK_ROOT_POST_DIV63,
+	CLK_ROOT_POST_DIV64,
+};
+
+struct clk_root_map {
+	enum clk_root_index entry;
+	enum clk_slice_type slice_type;
+	u32 slice_index;
+	u8 src_mux[8];
+};
+
+struct ccm_ccgr {
+	u32 ccgr;
+	u32 ccgr_set;
+	u32 ccgr_clr;
+	u32 ccgr_tog;
+};
+
+struct ccm_root {
+	u32 target_root;
+	u32 target_root_set;
+	u32 target_root_clr;
+	u32 target_root_tog;
+	u32 misc;
+	u32 misc_set;
+	u32 misc_clr;
+	u32 misc_tog;
+	u32 nm_post;
+	u32 nm_post_root_set;
+	u32 nm_post_root_clr;
+	u32 nm_post_root_tog;
+	u32 nm_pre;
+	u32 nm_pre_root_set;
+	u32 nm_pre_root_clr;
+	u32 nm_pre_root_tog;
+	u32 db_post;
+	u32 db_post_root_set;
+	u32 db_post_root_clr;
+	u32 db_post_root_tog;
+	u32 db_pre;
+	u32 db_pre_root_set;
+	u32 db_pre_root_clr;
+	u32 db_pre_root_tog;
+	u32 reserved[4];
+	u32 access_ctrl;
+	u32 access_ctrl_root_set;
+	u32 access_ctrl_root_clr;
+	u32 access_ctrl_root_tog;
+};
+
+struct ccm_reg {
+	u32 reserved_0[4096];
+	struct ccm_ccgr ccgr_array[192];
+	u32 reserved_1[3328];
+	struct ccm_root core_root[5];
+	u32 reserved_2[352];
+	struct ccm_root bus_root[12];
+	u32 reserved_3[128];
+	struct ccm_root ahb_ipg_root[4];
+	u32 reserved_4[384];
+	struct ccm_root dram_sel;
+	struct ccm_root core_sel;
+	u32 reserved_5[448];
+	struct ccm_root ip_root[78];
+};
+
+enum enet_freq {
+	ENET_25MHZ = 0,
+	ENET_50MHZ,
+	ENET_125MHZ,
+};
+
+#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k)			\
+	{								\
+		.clk		=	(_rate),			\
+		.alt_root_sel	=	(_m),				\
+		.alt_pre_div	=	(_p),				\
+		.apb_root_sel	=	(_s),				\
+		.apb_pre_div	=	(_k),				\
+	}
+
+struct dram_bypass_clk_setting {
+	ulong clk;
+	int alt_root_sel;
+	enum root_pre_div alt_pre_div;
+	int apb_root_sel;
+	enum root_pre_div apb_pre_div;
+};
+
+#define CCGR_CLK_ON_MASK	0x03
+#define CLK_SRC_ON_MASK		0x03
+
+#define CLK_ROOT_ON		BIT(28)
+#define CLK_ROOT_OFF		(0 << 28)
+#define CLK_ROOT_ENABLE_MASK	BIT(28)
+#define CLK_ROOT_ENABLE_SHIFT	28
+#define CLK_ROOT_SOURCE_SEL(n)	(((n) & 0x7) << 24)
+
+/* For SEL, only use 1 bit */
+#define CLK_ROOT_SRC_MUX_MASK	0x07000000
+#define CLK_ROOT_SRC_MUX_SHIFT	24
+#define CLK_ROOT_SRC_0		0x00000000
+#define CLK_ROOT_SRC_1		0x01000000
+#define CLK_ROOT_SRC_2		0x02000000
+#define CLK_ROOT_SRC_3		0x03000000
+#define CLK_ROOT_SRC_4		0x04000000
+#define CLK_ROOT_SRC_5		0x05000000
+#define CLK_ROOT_SRC_6		0x06000000
+#define CLK_ROOT_SRC_7		0x07000000
+
+#define CLK_ROOT_PRE_DIV_MASK	(0x00070000)
+#define CLK_ROOT_PRE_DIV_SHIFT	16
+#define CLK_ROOT_PRE_DIV(n)	(((n) << 16) & 0x00070000)
+
+#define CLK_ROOT_AUDO_SLOW_EN	0x1000
+
+#define CLK_ROOT_AUDO_DIV_MASK	0x700
+#define CLK_ROOT_AUDO_DIV_SHIFT	0x8
+#define CLK_ROOT_AUDO_DIV(n)	(((n) << 8) & 0x700)
+
+/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
+#define CLK_ROOT_POST_DIV_MASK		0x3f
+#define CLK_ROOT_CORE_POST_DIV_MASK	0x7
+#define CLK_ROOT_IPG_POST_DIV_MASK	0x3
+#define CLK_ROOT_POST_DIV_SHIFT		0
+#define CLK_ROOT_POST_DIV(n)		((n) & 0x3f)
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x01000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK		0x03000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x07000000
+#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M			0x01000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK	0x01000000
+
+void dram_pll_init(ulong pll_val);
+void dram_enable_bypass(ulong clk_val);
+void dram_disable_bypass(void);
+u32 imx_get_fecclk(void);
+u32 imx_get_uartclk(void);
+int clock_init(void);
+void init_clk_usdhc(u32 index);
+void init_uart_clk(u32 index);
+void init_wdog_clk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+int clock_enable(enum clk_ccgr_index index, bool enable);
+int clock_root_enabled(enum clk_root_index clock_id);
+int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
+		   enum root_post_div post_div, enum clk_root_src clock_src);
+int clock_set_target_val(enum clk_root_index clock_id, u32 val);
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
+int clock_get_postdiv(enum clk_root_index clock_id,
+		      enum root_post_div *post_div);
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
+void mxs_set_lcdclk(u32 base_addr, u32 freq);
+int set_clk_qspi(void);
+void enable_ocotp_clk(unsigned char enable);
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
+int set_clk_enet(enum enet_freq type);
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
new file mode 100644
index 0000000..305514a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -0,0 +1,387 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
+#define _ASM_ARCH_IMX8MM_CLOCK_H
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)			\
+	{							\
+		.rate	=	(_rate),			\
+		.mdiv	=	(_m),				\
+		.pdiv	=	(_p),				\
+		.sdiv	=	(_s),				\
+		.kdiv	=	(_k),				\
+	}
+
+#define LOCK_STATUS	BIT(31)
+#define LOCK_SEL_MASK	BIT(29)
+#define CLKE_MASK	BIT(11)
+#define RST_MASK	BIT(9)
+#define BYPASS_MASK	BIT(4)
+#define	MDIV_SHIFT	12
+#define	MDIV_MASK	GENMASK(21, 12)
+#define PDIV_SHIFT	4
+#define PDIV_MASK	GENMASK(9, 4)
+#define SDIV_SHIFT	0
+#define SDIV_MASK	GENMASK(2, 0)
+#define KDIV_SHIFT	0
+#define KDIV_MASK	GENMASK(15, 0)
+
+struct imx_int_pll_rate_table {
+	u32 rate;
+	int mdiv;
+	int pdiv;
+	int sdiv;
+	int kdiv;
+};
+
+enum pll_clocks {
+	ANATOP_ARM_PLL,
+	ANATOP_VPU_PLL,
+	ANATOP_GPU_PLL,
+	ANATOP_SYSTEM_PLL1,
+	ANATOP_SYSTEM_PLL2,
+	ANATOP_SYSTEM_PLL3,
+	ANATOP_AUDIO_PLL1,
+	ANATOP_AUDIO_PLL2,
+	ANATOP_VIDEO_PLL,
+	ANATOP_DRAM_PLL,
+};
+
+enum clk_root_index {
+	ARM_A53_CLK_ROOT		= 0,
+	ARM_M4_CLK_ROOT			= 1,
+	VPU_A53_CLK_ROOT		= 2,
+	GPU3D_CLK_ROOT			= 3,
+	GPU2D_CLK_ROOT			= 4,
+	MAIN_AXI_CLK_ROOT		= 16,
+	ENET_AXI_CLK_ROOT		= 17,
+	NAND_USDHC_BUS_CLK_ROOT		= 18,
+	VPU_BUS_CLK_ROOT		= 19,
+	DISPLAY_AXI_CLK_ROOT		= 20,
+	DISPLAY_APB_CLK_ROOT		= 21,
+	DISPLAY_RTRM_CLK_ROOT		= 22,
+	USB_BUS_CLK_ROOT		= 23,
+	GPU_AXI_CLK_ROOT		= 24,
+	GPU_AHB_CLK_ROOT		= 25,
+	NOC_CLK_ROOT			= 26,
+	NOC_APB_CLK_ROOT		= 27,
+	AHB_CLK_ROOT			= 32,
+	IPG_CLK_ROOT			= 33,
+	AUDIO_AHB_CLK_ROOT		= 34,
+	MIPI_DSI_ESC_RX_CLK_ROOT	= 36,
+	DRAM_SEL_CFG			= 48,
+	CORE_SEL_CFG			= 49,
+	DRAM_ALT_CLK_ROOT		= 64,
+	DRAM_APB_CLK_ROOT		= 65,
+	VPU_G1_CLK_ROOT			= 66,
+	VPU_G2_CLK_ROOT			= 67,
+	DISPLAY_DTRC_CLK_ROOT		= 68,
+	DISPLAY_DC8000_CLK_ROOT		= 69,
+	PCIE_CTRL_CLK_ROOT		= 70,
+	PCIE_PHY_CLK_ROOT		= 71,
+	PCIE_AUX_CLK_ROOT		= 72,
+	DC_PIXEL_CLK_ROOT		= 73,
+	LCDIF_PIXEL_CLK_ROOT		= 74,
+	SAI1_CLK_ROOT			= 75,
+	SAI2_CLK_ROOT			= 76,
+	SAI3_CLK_ROOT			= 77,
+	SAI4_CLK_ROOT			= 78,
+	SAI5_CLK_ROOT			= 79,
+	SAI6_CLK_ROOT			= 80,
+	SPDIF1_CLK_ROOT			= 81,
+	SPDIF2_CLK_ROOT			= 82,
+	ENET_REF_CLK_ROOT		= 83,
+	ENET_TIMER_CLK_ROOT		= 84,
+	ENET_PHY_REF_CLK_ROOT		= 85,
+	NAND_CLK_ROOT			= 86,
+	QSPI_CLK_ROOT			= 87,
+	USDHC1_CLK_ROOT			= 88,
+	USDHC2_CLK_ROOT			= 89,
+	I2C1_CLK_ROOT			= 90,
+	I2C2_CLK_ROOT			= 91,
+	I2C3_CLK_ROOT			= 92,
+	I2C4_CLK_ROOT			= 93,
+	UART1_CLK_ROOT			= 94,
+	UART2_CLK_ROOT			= 95,
+	UART3_CLK_ROOT			= 96,
+	UART4_CLK_ROOT			= 97,
+	USB_CORE_REF_CLK_ROOT		= 98,
+	USB_PHY_REF_CLK_ROOT		= 99,
+	GIC_CLK_ROOT			= 100,
+	ECSPI1_CLK_ROOT			= 101,
+	ECSPI2_CLK_ROOT			= 102,
+	PWM1_CLK_ROOT			= 103,
+	PWM2_CLK_ROOT			= 104,
+	PWM3_CLK_ROOT			= 105,
+	PWM4_CLK_ROOT			= 106,
+	GPT1_CLK_ROOT			= 107,
+	GPT2_CLK_ROOT			= 108,
+	GPT3_CLK_ROOT			= 109,
+	GPT4_CLK_ROOT			= 110,
+	GPT5_CLK_ROOT			= 111,
+	GPT6_CLK_ROOT			= 112,
+	TRACE_CLK_ROOT			= 113,
+	WDOG_CLK_ROOT			= 114,
+	WRCLK_CLK_ROOT			= 115,
+	IPP_DO_CLKO1			= 116,
+	IPP_DO_CLKO2			= 117,
+	MIPI_DSI_CORE_CLK_ROOT		= 118,
+	MIPI_DSI_PHY_REF_CLK_ROOT	= 119,
+	MIPI_DSI_DBI_CLK_ROOT		= 120,
+	USDHC3_CLK_ROOT			= 121,
+	MIPI_CSI1_CORE_CLK_ROOT		= 122,
+	MIPI_CSI1_PHY_REF_CLK_ROOT	= 123,
+	MIPI_CSI1_ESC_CLK_ROOT		= 124,
+	MIPI_CSI2_CORE_CLK_ROOT		= 125,
+	MIPI_CSI2_PHY_REF_CLK_ROOT	= 126,
+	MIPI_CSI2_ESC_CLK_ROOT		= 127,
+	PCIE2_CTRL_CLK_ROOT		= 128,
+	PCIE2_PHY_CLK_ROOT		= 129,
+	PCIE2_AUX_CLK_ROOT		= 130,
+	ECSPI3_CLK_ROOT			= 131,
+	PDM_CLK_ROOT			= 132,
+	VPU_H1_CLK_ROOT			= 133,
+	CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+	OSC_24M_CLK,
+	ARM_PLL_CLK,
+	DRAM_PLL1_CLK,
+	VIDEO_PLL2_CLK,
+	VPU_PLL_CLK,
+	GPU_PLL_CLK,
+	SYSTEM_PLL1_800M_CLK,
+	SYSTEM_PLL1_400M_CLK,
+	SYSTEM_PLL1_266M_CLK,
+	SYSTEM_PLL1_200M_CLK,
+	SYSTEM_PLL1_160M_CLK,
+	SYSTEM_PLL1_133M_CLK,
+	SYSTEM_PLL1_100M_CLK,
+	SYSTEM_PLL1_80M_CLK,
+	SYSTEM_PLL1_40M_CLK,
+	SYSTEM_PLL2_1000M_CLK,
+	SYSTEM_PLL2_500M_CLK,
+	SYSTEM_PLL2_333M_CLK,
+	SYSTEM_PLL2_250M_CLK,
+	SYSTEM_PLL2_200M_CLK,
+	SYSTEM_PLL2_166M_CLK,
+	SYSTEM_PLL2_125M_CLK,
+	SYSTEM_PLL2_100M_CLK,
+	SYSTEM_PLL2_50M_CLK,
+	SYSTEM_PLL3_CLK,
+	AUDIO_PLL1_CLK,
+	AUDIO_PLL2_CLK,
+	VIDEO_PLL_CLK,
+	OSC_32K_CLK,
+	EXT_CLK_1,
+	EXT_CLK_2,
+	EXT_CLK_3,
+	EXT_CLK_4,
+	OSC_HDMI_CLK
+};
+
+enum clk_ccgr_index {
+	CCGR_DVFS = 0,
+	CCGR_ANAMIX = 1,
+	CCGR_CPU = 2,
+	CCGR_CSU = 3,
+	CCGR_DEBUG = 4,
+	CCGR_DDR1 = 5,
+	CCGR_ECSPI1 = 7,
+	CCGR_ECSPI2 = 8,
+	CCGR_ECSPI3 = 9,
+	CCGR_ENET1 = 10,
+	CCGR_GPIO1 = 11,
+	CCGR_GPIO2 = 12,
+	CCGR_GPIO3 = 13,
+	CCGR_GPIO4 = 14,
+	CCGR_GPIO5 = 15,
+	CCGR_GPT1 = 16,
+	CCGR_GPT2 = 17,
+	CCGR_GPT3 = 18,
+	CCGR_GPT4 = 19,
+	CCGR_GPT5 = 20,
+	CCGR_GPT6 = 21,
+	CCGR_HS = 22,
+	CCGR_I2C1 = 23,
+	CCGR_I2C2 = 24,
+	CCGR_I2C3 = 25,
+	CCGR_I2C4 = 26,
+	CCGR_IOMUX = 27,
+	CCGR_IOMUX1 = 28,
+	CCGR_IOMUX2 = 29,
+	CCGR_IOMUX3 = 30,
+	CCGR_IOMUX4 = 31,
+	CCGR_SNVSMIX_IPG_CLK = 32,
+	CCGR_MU = 33,
+	CCGR_OCOTP = 34,
+	CCGR_OCRAM = 35,
+	CCGR_OCRAM_S = 36,
+	CCGR_PCIE = 37,
+	CCGR_PERFMON1 = 38,
+	CCGR_PERFMON2 = 39,
+	CCGR_PWM1 = 40,
+	CCGR_PWM2 = 41,
+	CCGR_PWM3 = 42,
+	CCGR_PWM4 = 43,
+	CCGR_QOS = 44,
+	CCGR_QOS_DISPMIX = 45,
+	CCGR_QOS_ETHENET = 46,
+	CCGR_QSPI = 47,
+	CCGR_RAWNAND = 48,
+	CCGR_RDC = 49,
+	CCGR_ROM = 50,
+	CCGR_SAI1 = 51,
+	CCGR_SAI2 = 52,
+	CCGR_SAI3 = 53,
+	CCGR_SAI4 = 54,
+	CCGR_SAI5 = 55,
+	CCGR_SAI6 = 56,
+	CCGR_SCTR = 57,
+	CCGR_SDMA1 = 58,
+	CCGR_SDMA2 = 59,
+	CCGR_SEC_DEBUG = 60,
+	CCGR_SEMA1 = 61,
+	CCGR_SEMA2 = 62,
+	CCGR_SIM_DISPLAY = 63,
+	CCGR_SIM_ENET = 64,
+	CCGR_SIM_M = 65,
+	CCGR_SIM_MAIN = 66,
+	CCGR_SIM_S = 67,
+	CCGR_SIM_WAKEUP = 68,
+	CCGR_SIM_HSIO = 69,
+	CCGR_SIM_VPU = 70,
+	CCGR_SNVS = 71,
+	CCGR_TRACE = 72,
+	CCGR_UART1 = 73,
+	CCGR_UART2 = 74,
+	CCGR_UART3 = 75,
+	CCGR_UART4 = 76,
+	CCGR_USB_MSCALE_PL301 = 77,
+	CCGR_GPU3D = 79,
+	CCGR_USDHC1 = 81,
+	CCGR_USDHC2 = 82,
+	CCGR_WDOG1 = 83,
+	CCGR_WDOG2 = 84,
+	CCGR_WDOG3 = 85,
+	CCGR_VPUG1 = 86,
+	CCGR_GPU_BUS = 87,
+	CCGR_VPUH1 = 89,
+	CCGR_VPUG2 = 90,
+	CCGR_PDM = 91,
+	CCGR_GIC = 92,
+	CCGR_DISPMIX = 93,
+	CCGR_USDHC3 = 94,
+	CCGR_SDMA3 = 95,
+	CCGR_XTAL = 96,
+	CCGR_PLL = 97,
+	CCGR_TEMP_SENSOR = 98,
+	CCGR_VPUMIX_BUS = 99,
+	CCGR_GPU2D = 102,
+	CCGR_MAX
+};
+
+enum clk_src_index {
+	CLK_SRC_CKIL_SYNC_REQ = 0,
+	CLK_SRC_ARM_PLL_EN = 1,
+	CLK_SRC_GPU_PLL_EN = 2,
+	CLK_SRC_VPU_PLL_EN = 3,
+	CLK_SRC_DRAM_PLL_EN = 4,
+	CLK_SRC_SYSTEM_PLL1_EN = 5,
+	CLK_SRC_SYSTEM_PLL2_EN = 6,
+	CLK_SRC_SYSTEM_PLL3_EN = 7,
+	CLK_SRC_AUDIO_PLL1_EN = 8,
+	CLK_SRC_AUDIO_PLL2_EN = 9,
+	CLK_SRC_VIDEO_PLL1_EN = 10,
+	CLK_SRC_RESERVED = 11,
+	CLK_SRC_ARM_PLL = 12,
+	CLK_SRC_GPU_PLL = 13,
+	CLK_SRC_VPU_PLL = 14,
+	CLK_SRC_DRAM_PLL = 15,
+	CLK_SRC_SYSTEM_PLL1_800M = 16,
+	CLK_SRC_SYSTEM_PLL1_400M = 17,
+	CLK_SRC_SYSTEM_PLL1_266M = 18,
+	CLK_SRC_SYSTEM_PLL1_200M = 19,
+	CLK_SRC_SYSTEM_PLL1_160M = 20,
+	CLK_SRC_SYSTEM_PLL1_133M = 21,
+	CLK_SRC_SYSTEM_PLL1_100M = 22,
+	CLK_SRC_SYSTEM_PLL1_80M = 23,
+	CLK_SRC_SYSTEM_PLL1_40M = 24,
+	CLK_SRC_SYSTEM_PLL2_1000M = 25,
+	CLK_SRC_SYSTEM_PLL2_500M = 26,
+	CLK_SRC_SYSTEM_PLL2_333M = 27,
+	CLK_SRC_SYSTEM_PLL2_250M = 28,
+	CLK_SRC_SYSTEM_PLL2_200M = 29,
+	CLK_SRC_SYSTEM_PLL2_166M = 30,
+	CLK_SRC_SYSTEM_PLL2_125M = 31,
+	CLK_SRC_SYSTEM_PLL2_100M = 32,
+	CLK_SRC_SYSTEM_PLL2_50M = 33,
+	CLK_SRC_SYSTEM_PLL3 = 34,
+	CLK_SRC_AUDIO_PLL1 = 35,
+	CLK_SRC_AUDIO_PLL2 = 36,
+	CLK_SRC_VIDEO_PLL1 = 37,
+};
+
+#define INTPLL_LOCK_MASK			BIT(31)
+#define INTPLL_LOCK_SEL_MASK			BIT(29)
+#define INTPLL_EXT_BYPASS_MASK			BIT(28)
+#define INTPLL_DIV20_CLKE_MASK			BIT(27)
+#define INTPLL_DIV20_CLKE_OVERRIDE_MASK		BIT(26)
+#define INTPLL_DIV10_CLKE_MASK			BIT(25)
+#define INTPLL_DIV10_CLKE_OVERRIDE_MASK		BIT(24)
+#define INTPLL_DIV8_CLKE_MASK			BIT(23)
+#define INTPLL_DIV8_CLKE_OVERRIDE_MASK		BIT(22)
+#define INTPLL_DIV6_CLKE_MASK			BIT(21)
+#define INTPLL_DIV6_CLKE_OVERRIDE_MASK		BIT(20)
+#define INTPLL_DIV5_CLKE_MASK			BIT(19)
+#define INTPLL_DIV5_CLKE_OVERRIDE_MASK		BIT(18)
+#define INTPLL_DIV4_CLKE_MASK			BIT(17)
+#define INTPLL_DIV4_CLKE_OVERRIDE_MASK		BIT(16)
+#define INTPLL_DIV3_CLKE_MASK			BIT(15)
+#define INTPLL_DIV3_CLKE_OVERRIDE_MASK		BIT(14)
+#define INTPLL_DIV2_CLKE_MASK			BIT(13)
+#define INTPLL_DIV2_CLKE_OVERRIDE_MASK		BIT(12)
+#define INTPLL_CLKE_MASK			BIT(11)
+#define INTPLL_CLKE_OVERRIDE_MASK		BIT(10)
+#define INTPLL_RST_MASK				BIT(9)
+#define INTPLL_RST_OVERRIDE_MASK		BIT(8)
+#define INTPLL_BYPASS_MASK			BIT(4)
+#define INTPLL_PAD_CLK_SEL_MASK			GENMASK(3, 2)
+#define INTPLL_REF_CLK_SEL_MASK			GENMASK(1, 0)
+
+#define INTPLL_MAIN_DIV_MASK		GENMASK(21, 12)
+#define INTPLL_MAIN_DIV_VAL(n)		((n << 12) & GENMASK(21, 12))
+#define INTPLL_MAIN_DIV_SHIFT		12
+#define INTPLL_PRE_DIV_MASK		GENMASK(9, 4)
+#define INTPLL_PRE_DIV_VAL(n)		((n << 4) & GENMASK(9, 4))
+#define INTPLL_PRE_DIV_SHIFT		4
+#define INTPLL_POST_DIV_MASK		GENMASK(2, 0)
+#define INTPLL_POST_DIV_VAL(n)		((n << 0) & GENMASK(2, 0))
+#define INTPLL_POST_DIV_SHIFT		0
+
+#define INTPLL_LOCK_CON_DLY_MASK	GENMASK(5, 4)
+#define INTPLL_LOCK_CON_DLY_SHIFT	4
+#define INTPLL_LOCK_CON_OUT_MASK	GENMASK(3, 2)
+#define INTPLL_LOCK_CON_OUT_SHIFT	2
+#define INTPLL_LOCK_CON_IN_MASK		GENMASK(1, 0)
+#define INTPLL_LOCK_CON_IN_SHIFT	0
+
+#define INTPLL_LRD_EN_MASK		BIT(21)
+#define INTPLL_FOUT_MASK		BIT(20)
+#define INTPLL_AFC_SEL_MASK		BIT(19)
+#define INTPLL_PBIAS_CTRL_MASK		BIT(18)
+#define INTPLL_PBIAS_CTRL_EN_MASK	BIT(17)
+#define INTPLL_AFCINIT_SEL_MASK		BIT(16)
+#define INTPLL_FSEL_MASK		BIT(14)
+#define INTPLL_FEED_EN_MASK		BIT(13)
+#define INTPLL_EXTAFC_MASK		GENMASK(7, 3)
+#define INTPLL_AFC_EN_MASK		BIT(2)
+#define INTPLL_ICP_MASK			GENMASK(1, 0)
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
new file mode 100644
index 0000000..9fa9eb2
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
@@ -0,0 +1,424 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CLOCK_H
+#define _ASM_ARCH_IMX8M_CLOCK_H
+
+enum pll_clocks {
+	ANATOP_ARM_PLL,
+	ANATOP_GPU_PLL,
+	ANATOP_SYSTEM_PLL1,
+	ANATOP_SYSTEM_PLL2,
+	ANATOP_SYSTEM_PLL3,
+	ANATOP_AUDIO_PLL1,
+	ANATOP_AUDIO_PLL2,
+	ANATOP_VIDEO_PLL1,
+	ANATOP_VIDEO_PLL2,
+	ANATOP_DRAM_PLL,
+};
+
+enum clk_root_index {
+	ARM_A53_CLK_ROOT		= 0,
+	ARM_M4_CLK_ROOT			= 1,
+	VPU_A53_CLK_ROOT		= 2,
+	GPU_CORE_CLK_ROOT		= 3,
+	GPU_SHADER_CLK_ROOT		= 4,
+	MAIN_AXI_CLK_ROOT		= 16,
+	ENET_AXI_CLK_ROOT		= 17,
+	NAND_USDHC_BUS_CLK_ROOT		= 18,
+	VPU_BUS_CLK_ROOT		= 19,
+	DISPLAY_AXI_CLK_ROOT		= 20,
+	DISPLAY_APB_CLK_ROOT		= 21,
+	DISPLAY_RTRM_CLK_ROOT		= 22,
+	USB_BUS_CLK_ROOT		= 23,
+	GPU_AXI_CLK_ROOT		= 24,
+	GPU_AHB_CLK_ROOT		= 25,
+	NOC_CLK_ROOT			= 26,
+	NOC_APB_CLK_ROOT		= 27,
+	AHB_CLK_ROOT			= 32,
+	IPG_CLK_ROOT			= 33,
+	AUDIO_AHB_CLK_ROOT		= 34,
+	MIPI_DSI_ESC_RX_CLK_ROOT	= 36,
+	DRAM_SEL_CFG			= 48,
+	CORE_SEL_CFG			= 49,
+	DRAM_ALT_CLK_ROOT		= 64,
+	DRAM_APB_CLK_ROOT		= 65,
+	VPU_G1_CLK_ROOT			= 66,
+	VPU_G2_CLK_ROOT			= 67,
+	DISPLAY_DTRC_CLK_ROOT		= 68,
+	DISPLAY_DC8000_CLK_ROOT		= 69,
+	PCIE1_CTRL_CLK_ROOT		= 70,
+	PCIE1_PHY_CLK_ROOT		= 71,
+	PCIE1_AUX_CLK_ROOT		= 72,
+	DC_PIXEL_CLK_ROOT		= 73,
+	LCDIF_PIXEL_CLK_ROOT		= 74,
+	SAI1_CLK_ROOT			= 75,
+	SAI2_CLK_ROOT			= 76,
+	SAI3_CLK_ROOT			= 77,
+	SAI4_CLK_ROOT			= 78,
+	SAI5_CLK_ROOT			= 79,
+	SAI6_CLK_ROOT			= 80,
+	SPDIF1_CLK_ROOT			= 81,
+	SPDIF2_CLK_ROOT			= 82,
+	ENET_REF_CLK_ROOT		= 83,
+	ENET_TIMER_CLK_ROOT		= 84,
+	ENET_PHY_REF_CLK_ROOT		= 85,
+	NAND_CLK_ROOT			= 86,
+	QSPI_CLK_ROOT			= 87,
+	USDHC1_CLK_ROOT			= 88,
+	USDHC2_CLK_ROOT			= 89,
+	I2C1_CLK_ROOT			= 90,
+	I2C2_CLK_ROOT			= 91,
+	I2C3_CLK_ROOT			= 92,
+	I2C4_CLK_ROOT			= 93,
+	UART1_CLK_ROOT			= 94,
+	UART2_CLK_ROOT			= 95,
+	UART3_CLK_ROOT			= 96,
+	UART4_CLK_ROOT			= 97,
+	USB_CORE_REF_CLK_ROOT		= 98,
+	USB_PHY_REF_CLK_ROOT		= 99,
+	GIC_CLK_ROOT			= 100,
+	ECSPI1_CLK_ROOT			= 101,
+	ECSPI2_CLK_ROOT			= 102,
+	PWM1_CLK_ROOT			= 103,
+	PWM2_CLK_ROOT			= 104,
+	PWM3_CLK_ROOT			= 105,
+	PWM4_CLK_ROOT			= 106,
+	GPT1_CLK_ROOT			= 107,
+	GPT2_CLK_ROOT			= 108,
+	GPT3_CLK_ROOT			= 109,
+	GPT4_CLK_ROOT			= 110,
+	GPT5_CLK_ROOT			= 111,
+	GPT6_CLK_ROOT			= 112,
+	TRACE_CLK_ROOT			= 113,
+	WDOG_CLK_ROOT			= 114,
+	WRCLK_CLK_ROOT			= 115,
+	IPP_DO_CLKO1			= 116,
+	IPP_DO_CLKO2			= 117,
+	MIPI_DSI_CORE_CLK_ROOT		= 118,
+	MIPI_DSI_PHY_REF_CLK_ROOT	= 119,
+	MIPI_DSI_DBI_CLK_ROOT		= 120,
+	OLD_MIPI_DSI_ESC_CLK_ROOT	= 121,
+	MIPI_CSI1_CORE_CLK_ROOT		= 122,
+	MIPI_CSI1_PHY_REF_CLK_ROOT	= 123,
+	MIPI_CSI1_ESC_CLK_ROOT		= 124,
+	MIPI_CSI2_CORE_CLK_ROOT		= 125,
+	MIPI_CSI2_PHY_REF_CLK_ROOT	= 126,
+	MIPI_CSI2_ESC_CLK_ROOT		= 127,
+	PCIE2_CTRL_CLK_ROOT		= 128,
+	PCIE2_PHY_CLK_ROOT		= 129,
+	PCIE2_AUX_CLK_ROOT		= 130,
+	ECSPI3_CLK_ROOT			= 131,
+	OLD_MIPI_DSI_ESC_RX_ROOT	= 132,
+	DISPLAY_HDMI_CLK_ROOT		= 133,
+	CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+	OSC_25M_CLK,
+	ARM_PLL_CLK,
+	DRAM_PLL1_CLK,
+	VIDEO_PLL2_CLK,
+	VPU_PLL_CLK,
+	GPU_PLL_CLK,
+	SYSTEM_PLL1_800M_CLK,
+	SYSTEM_PLL1_400M_CLK,
+	SYSTEM_PLL1_266M_CLK,
+	SYSTEM_PLL1_200M_CLK,
+	SYSTEM_PLL1_160M_CLK,
+	SYSTEM_PLL1_133M_CLK,
+	SYSTEM_PLL1_100M_CLK,
+	SYSTEM_PLL1_80M_CLK,
+	SYSTEM_PLL1_40M_CLK,
+	SYSTEM_PLL2_1000M_CLK,
+	SYSTEM_PLL2_500M_CLK,
+	SYSTEM_PLL2_333M_CLK,
+	SYSTEM_PLL2_250M_CLK,
+	SYSTEM_PLL2_200M_CLK,
+	SYSTEM_PLL2_166M_CLK,
+	SYSTEM_PLL2_125M_CLK,
+	SYSTEM_PLL2_100M_CLK,
+	SYSTEM_PLL2_50M_CLK,
+	SYSTEM_PLL3_CLK,
+	AUDIO_PLL1_CLK,
+	AUDIO_PLL2_CLK,
+	VIDEO_PLL_CLK,
+	OSC_32K_CLK,
+	EXT_CLK_1,
+	EXT_CLK_2,
+	EXT_CLK_3,
+	EXT_CLK_4,
+	OSC_27M_CLK,
+};
+
+/* CCGR index */
+enum clk_ccgr_index {
+	CCGR_DVFS = 0,
+	CCGR_ANAMIX = 1,
+	CCGR_CPU = 2,
+	CCGR_CSU = 4,
+	CCGR_DRAM1 = 5,
+	CCGR_DRAM2_OBSOLETE = 6,
+	CCGR_ECSPI1 = 7,
+	CCGR_ECSPI2 = 8,
+	CCGR_ECSPI3 = 9,
+	CCGR_ENET1 = 10,
+	CCGR_GPIO1 = 11,
+	CCGR_GPIO2 = 12,
+	CCGR_GPIO3 = 13,
+	CCGR_GPIO4 = 14,
+	CCGR_GPIO5 = 15,
+	CCGR_GPT1 = 16,
+	CCGR_GPT2 = 17,
+	CCGR_GPT3 = 18,
+	CCGR_GPT4 = 19,
+	CCGR_GPT5 = 20,
+	CCGR_GPT6 = 21,
+	CCGR_HS = 22,
+	CCGR_I2C1 = 23,
+	CCGR_I2C2 = 24,
+	CCGR_I2C3 = 25,
+	CCGR_I2C4 = 26,
+	CCGR_IOMUX = 27,
+	CCGR_IOMUX1 = 28,
+	CCGR_IOMUX2 = 29,
+	CCGR_IOMUX3 = 30,
+	CCGR_IOMUX4 = 31,
+	CCGR_M4 = 32,
+	CCGR_MU = 33,
+	CCGR_OCOTP = 34,
+	CCGR_OCRAM = 35,
+	CCGR_OCRAM_S = 36,
+	CCGR_PCIE = 37,
+	CCGR_PERFMON1 = 38,
+	CCGR_PERFMON2 = 39,
+	CCGR_PWM1 = 40,
+	CCGR_PWM2 = 41,
+	CCGR_PWM3 = 42,
+	CCGR_PWM4 = 43,
+	CCGR_QOS = 44,
+	CCGR_DISMIX = 45,
+	CCGR_MEGAMIX = 46,
+	CCGR_QSPI = 47,
+	CCGR_RAWNAND = 48,
+	CCGR_RDC = 49,
+	CCGR_ROM = 50,
+	CCGR_SAI1 = 51,
+	CCGR_SAI2 = 52,
+	CCGR_SAI3 = 53,
+	CCGR_SAI4 = 54,
+	CCGR_SAI5 = 55,
+	CCGR_SAI6 = 56,
+	CCGR_SCTR = 57,
+	CCGR_SDMA1 = 58,
+	CCGR_SDMA2 = 59,
+	CCGR_SEC_DEBUG = 60,
+	CCGR_SEMA1 = 61,
+	CCGR_SEMA2 = 62,
+	CCGR_SIM_DISPLAY = 63,
+	CCGR_SIM_ENET = 64,
+	CCGR_SIM_M = 65,
+	CCGR_SIM_MAIN = 66,
+	CCGR_SIM_S = 67,
+	CCGR_SIM_WAKEUP = 68,
+	CCGR_SIM_USB = 69,
+	CCGR_SIM_VPU = 70,
+	CCGR_SNVS = 71,
+	CCGR_TRACE = 72,
+	CCGR_UART1 = 73,
+	CCGR_UART2 = 74,
+	CCGR_UART3 = 75,
+	CCGR_UART4 = 76,
+	CCGR_USB_CTRL1 = 77,
+	CCGR_USB_CTRL2 = 78,
+	CCGR_USB_PHY1 = 79,
+	CCGR_USB_PHY2 = 80,
+	CCGR_USDHC1 = 81,
+	CCGR_USDHC2 = 82,
+	CCGR_WDOG1 = 83,
+	CCGR_WDOG2 = 84,
+	CCGR_WDOG3 = 85,
+	CCGR_VA53 = 86,
+	CCGR_GPU = 87,
+	CCGR_HEVC = 88,
+	CCGR_AVC = 89,
+	CCGR_VP9 = 90,
+	CCGR_HEVC_INTER = 91,
+	CCGR_GIC = 92,
+	CCGR_DISPLAY = 93,
+	CCGR_HDMI = 94,
+	CCGR_HDMI_PHY = 95,
+	CCGR_XTAL = 96,
+	CCGR_PLL = 97,
+	CCGR_TSENSOR = 98,
+	CCGR_VPU_DEC = 99,
+	CCGR_PCIE2 = 100,
+	CCGR_MIPI_CSI1 = 101,
+	CCGR_MIPI_CSI2 = 102,
+	CCGR_MAX,
+};
+
+/* src index */
+enum clk_src_index {
+	CLK_SRC_CKIL_SYNC_REQ = 0,
+	CLK_SRC_ARM_PLL_EN = 1,
+	CLK_SRC_GPU_PLL_EN = 2,
+	CLK_SRC_VPU_PLL_EN = 3,
+	CLK_SRC_DRAM_PLL_EN = 4,
+	CLK_SRC_SYSTEM_PLL1_EN = 5,
+	CLK_SRC_SYSTEM_PLL2_EN = 6,
+	CLK_SRC_SYSTEM_PLL3_EN = 7,
+	CLK_SRC_AUDIO_PLL1_EN = 8,
+	CLK_SRC_AUDIO_PLL2_EN = 9,
+	CLK_SRC_VIDEO_PLL1_EN = 10,
+	CLK_SRC_VIDEO_PLL2_EN = 11,
+	CLK_SRC_ARM_PLL = 12,
+	CLK_SRC_GPU_PLL = 13,
+	CLK_SRC_VPU_PLL = 14,
+	CLK_SRC_DRAM_PLL = 15,
+	CLK_SRC_SYSTEM_PLL1_800M = 16,
+	CLK_SRC_SYSTEM_PLL1_400M = 17,
+	CLK_SRC_SYSTEM_PLL1_266M = 18,
+	CLK_SRC_SYSTEM_PLL1_200M = 19,
+	CLK_SRC_SYSTEM_PLL1_160M = 20,
+	CLK_SRC_SYSTEM_PLL1_133M = 21,
+	CLK_SRC_SYSTEM_PLL1_100M = 22,
+	CLK_SRC_SYSTEM_PLL1_80M = 23,
+	CLK_SRC_SYSTEM_PLL1_40M = 24,
+	CLK_SRC_SYSTEM_PLL2_1000M = 25,
+	CLK_SRC_SYSTEM_PLL2_500M = 26,
+	CLK_SRC_SYSTEM_PLL2_333M = 27,
+	CLK_SRC_SYSTEM_PLL2_250M = 28,
+	CLK_SRC_SYSTEM_PLL2_200M = 29,
+	CLK_SRC_SYSTEM_PLL2_166M = 30,
+	CLK_SRC_SYSTEM_PLL2_125M = 31,
+	CLK_SRC_SYSTEM_PLL2_100M = 32,
+	CLK_SRC_SYSTEM_PLL2_50M = 33,
+	CLK_SRC_SYSTEM_PLL3 = 34,
+	CLK_SRC_AUDIO_PLL1 = 35,
+	CLK_SRC_AUDIO_PLL2 = 36,
+	CLK_SRC_VIDEO_PLL1 = 37,
+	CLK_SRC_VIDEO_PLL2 = 38,
+	CLK_SRC_OSC_25M = 39,
+	CLK_SRC_OSC_27M = 40,
+};
+
+/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
+#define FRAC_PLL_LOCK_MASK		BIT(31)
+#define FRAC_PLL_CLKE_MASK		BIT(21)
+#define FRAC_PLL_PD_MASK		BIT(19)
+#define FRAC_PLL_REFCLK_SEL_MASK	BIT(16)
+#define FRAC_PLL_LOCK_SEL_MASK		BIT(15)
+#define FRAC_PLL_BYPASS_MASK		BIT(14)
+#define FRAC_PLL_COUNTCLK_SEL_MASK	BIT(13)
+#define FRAC_PLL_NEWDIV_VAL_MASK	BIT(12)
+#define FRAC_PLL_NEWDIV_ACK_MASK	BIT(11)
+#define FRAC_PLL_REFCLK_DIV_VAL(n)	(((n) << 5) & (0x3f << 5))
+#define FRAC_PLL_REFCLK_DIV_VAL_MASK	(0x3f << 5)
+#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT	5
+#define FRAC_PLL_OUTPUT_DIV_VAL_MASK	0x1f
+#define FRAC_PLL_OUTPUT_DIV_VAL(n)	((n) & 0x1f)
+
+#define FRAC_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
+#define FRAC_PLL_REFCLK_SEL_OSC_27M	BIT(16)
+#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define FRAC_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
+
+#define FRAC_PLL_FRAC_DIV_CTL_MASK	(0x1ffffff << 7)
+#define FRAC_PLL_FRAC_DIV_CTL_SHIFT	7
+#define FRAC_PLL_INT_DIV_CTL_MASK	0x7f
+#define FRAC_PLL_INT_DIV_CTL_VAL(n)	((n) & 0x7f)
+
+/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
+#define SSCG_PLL_LOCK_MASK		BIT(31)
+#define SSCG_PLL_CLKE_MASK		BIT(25)
+#define SSCG_PLL_DIV2_CLKE_MASK		BIT(23)
+#define SSCG_PLL_DIV3_CLKE_MASK		BIT(21)
+#define SSCG_PLL_DIV4_CLKE_MASK		BIT(19)
+#define SSCG_PLL_DIV5_CLKE_MASK		BIT(17)
+#define SSCG_PLL_DIV6_CLKE_MASK		BIT(15)
+#define SSCG_PLL_DIV8_CLKE_MASK		BIT(13)
+#define SSCG_PLL_DIV10_CLKE_MASK	BIT(11)
+#define SSCG_PLL_DIV20_CLKE_MASK	BIT(9)
+#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK	BIT(9)
+#define SSCG_PLL_DRAM_PLL_CLKE_MASK	BIT(9)
+#define SSCG_PLL_PLL3_CLKE_MASK		BIT(9)
+#define SSCG_PLL_PD_MASK		BIT(7)
+#define SSCG_PLL_BYPASS1_MASK		BIT(5)
+#define SSCG_PLL_BYPASS2_MASK		BIT(4)
+#define SSCG_PLL_LOCK_SEL_MASK		BIT(3)
+#define SSCG_PLL_COUNTCLK_SEL_MASK	BIT(2)
+#define SSCG_PLL_REFCLK_SEL_MASK	0x3
+#define SSCG_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
+#define SSCG_PLL_REFCLK_SEL_OSC_27M	BIT(16)
+#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define SSCG_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
+
+#define SSCG_PLL_SSDS_MASK		BIT(8)
+#define SSCG_PLL_SSMD_MASK		(0x7 << 5)
+#define SSCG_PLL_SSMF_MASK		(0xf << 1)
+#define SSCG_PLL_SSE_MASK		0x1
+
+#define SSCG_PLL_REF_DIVR1_MASK		(0x7 << 25)
+#define SSCG_PLL_REF_DIVR1_SHIFT	25
+#define SSCG_PLL_REF_DIVR1_VAL(n)	(((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
+#define SSCG_PLL_REF_DIVR2_MASK		(0x3f << 19)
+#define SSCG_PLL_REF_DIVR2_SHIFT	19
+#define SSCG_PLL_REF_DIVR2_VAL(n)	(((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F1_MASK	(0x3f << 13)
+#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT	13
+#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n)	(((n) << 13) & \
+					 SSCG_PLL_FEEDBACK_DIV_F1_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F2_MASK	(0x3f << 7)
+#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT	7
+#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n)	(((n) << 7) & \
+					 SSCG_PLL_FEEDBACK_DIV_F2_MASK)
+#define SSCG_PLL_OUTPUT_DIV_VAL_MASK	(0x3f << 1)
+#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT	1
+#define SSCG_PLL_OUTPUT_DIV_VAL(n)	(((n) << 1) & \
+					 SSCG_PLL_OUTPUT_DIV_VAL_MASK)
+#define SSCG_PLL_FILTER_RANGE_MASK	0x1
+
+#define HW_DIGPROG_MAJOR_UPPER_MASK	(0xff << 16)
+#define HW_DIGPROG_MAJOR_LOWER_MASK	(0xff << 8)
+#define HW_DIGPROG_MINOR_MASK		0xff
+
+#define HW_OSC_27M_CLKE_MASK		BIT(4)
+#define HW_OSC_25M_CLKE_MASK		BIT(2)
+#define HW_OSC_32K_SEL_MASK		0x1
+#define HW_OSC_32K_SEL_RTC		0x1
+#define HW_OSC_32K_SEL_25M_DIV800	0x0
+
+#define HW_FRAC_ARM_PLL_DIV_MASK	(0x7 << 20)
+#define HW_FRAC_ARM_PLL_DIV_SHIFT	20
+#define HW_FRAC_VPU_PLL_DIV_MASK	(0x7 << 16)
+#define HW_FRAC_VPU_PLL_DIV_SHIFT	16
+#define HW_FRAC_GPU_PLL_DIV_MASK	(0x7 << 12)
+#define HW_FRAC_GPU_PLL_DIV_SHIFT	12
+#define HW_FRAC_VIDEO_PLL1_DIV_MASK	(0x7 << 10)
+#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT	10
+#define HW_FRAC_AUDIO_PLL2_DIV_MASK	(0x7 << 4)
+#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT	4
+#define HW_FRAC_AUDIO_PLL1_DIV_MASK	0x7
+#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT	0
+
+#define HW_SSCG_VIDEO_PLL2_DIV_MASK	(0x7 << 16)
+#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT	16
+#define HW_SSCG_DRAM_PLL_DIV_MASK	(0x7 << 14)
+#define HW_SSCG_DRAM_PLL_DIV_SHIFT	14
+#define HW_SSCG_SYSTEM_PLL3_DIV_MASK	(0x7 << 8)
+#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT	8
+#define HW_SSCG_SYSTEM_PLL2_DIV_MASK	(0x7 << 4)
+#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT	4
+#define HW_SSCG_SYSTEM_PLL1_DIV_MASK	0x7
+#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT	0
+
+enum frac_pll_out_val {
+	FRAC_PLL_OUT_1000M,
+	FRAC_PLL_OUT_1600M,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/crm_regs.h b/arch/arm/include/asm/arch-imx8m/crm_regs.h
new file mode 100644
index 0000000..c42e668
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/crm_regs.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H
+#define _ASM_ARCH_IMX8M_CRM_REGS_H
+/* Dummy header, some imx-common code needs this file */
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
new file mode 100644
index 0000000..53d4625
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -0,0 +1,740 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8M_DDR_H
+#define __ASM_ARCH_IMX8M_DDR_H
+
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/arch/ddr.h>
+
+#define DDRC_DDR_SS_GPR0		0x3d000000
+#define DDRC_IPS_BASE_ADDR_0		0x3f400000
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X)	(0x3c000000 + (X * 0x2000000))
+#define DDRPHY_MEM(X)			(0x3c000000 + (X * 0x2000000) + 0x50000)
+
+struct ddrc_freq {
+	u32 res0[8];
+	u32 derateen;
+	u32 derateint;
+	u32 res1[10];
+	u32 rfshctl0;
+	u32 res2[4];
+	u32 rfshtmg;
+	u32 rfshtmg1;
+	u32 res3[28];
+	u32 init3;
+	u32 init4;
+	u32 res;
+	u32 init6;
+	u32 init7;
+	u32 res4[4];
+	u32 dramtmg0;
+	u32 dramtmg1;
+	u32 dramtmg2;
+	u32 dramtmg3;
+	u32 dramtmg4;
+	u32 dramtmg5;
+	u32 dramtmg6;
+	u32 dramtmg7;
+	u32 dramtmg8;
+	u32 dramtmg9;
+	u32 dramtmg10;
+	u32 dramtmg11;
+	u32 dramtmg12;
+	u32 dramtmg13;
+	u32 dramtmg14;
+	u32 dramtmg15;
+	u32 dramtmg16;
+	u32 dramtmg17;
+	u32 res5[10];
+	u32 mramtmg0;
+	u32 mramtmg1;
+	u32 mramtmg4;
+	u32 mramtmg9;
+	u32 zqctl0;
+	u32 res6[3];
+	u32 dfitmg0;
+	u32 dfitmg1;
+	u32 res7[7];
+	u32 dfitmg2;
+	u32 dfitmg3;
+	u32 res8[33];
+	u32 odtcfg;
+};
+
+struct imx8m_ddrc_regs {
+	u32 mstr;
+	u32 stat;
+	u32 mstr1;
+	u32 res1;
+	u32 mrctrl0;
+	u32 mrctrl1;
+	u32 mrstat;
+	u32 mrctrl2;
+	u32 derateen;
+	u32 derateint;
+	u32 mstr2;
+	u32 res2;
+	u32 pwrctl;
+	u32 pwrtmg;
+	u32 hwlpctl;
+	u32 hwffcctl;
+	u32 hwffcstat;
+	u32 res3[3];
+	u32 rfshctl0;
+	u32 rfshctl1;
+	u32 rfshctl2;
+	u32 rfshctl4;
+	u32 rfshctl3;
+	u32 rfshtmg;
+	u32 rfshtmg1;
+	u32 res4;
+	u32 ecccfg0;
+	u32 ecccfg1;
+	u32 eccstat;
+	u32 eccclr;
+	u32 eccerrcnt;
+	u32 ecccaddr0;
+	u32 ecccaddr1;
+	u32 ecccsyn0;
+	u32 ecccsyn1;
+	u32 ecccsyn2;
+	u32 eccbitmask0;
+	u32 eccbitmask1;
+	u32 eccbitmask2;
+	u32 eccuaddr0;
+	u32 eccuaddr1;
+	u32 eccusyn0;
+	u32 eccusyn1;
+	u32 eccusyn2;
+	u32 eccpoisonaddr0;
+	u32 eccpoisonaddr1;
+	u32 crcparctl0;
+	u32 crcparctl1;
+	u32 crcparctl2;
+	u32 crcparstat;
+	u32 init0;
+	u32 init1;
+	u32 init2;
+	u32 init3;
+	u32 init4;
+	u32 init5;
+	u32 init6;
+	u32 init7;
+	u32 dimmctl;
+	u32 rankctl;
+	u32 res5;
+	u32 chctl;
+	u32 dramtmg0;
+	u32 dramtmg1;
+	u32 dramtmg2;
+	u32 dramtmg3;
+	u32 dramtmg4;
+	u32 dramtmg5;
+	u32 dramtmg6;
+	u32 dramtmg7;
+	u32 dramtmg8;
+	u32 dramtmg9;
+	u32 dramtmg10;
+	u32 dramtmg11;
+	u32 dramtmg12;
+	u32 dramtmg13;
+	u32 dramtmg14;
+	u32 dramtmg15;
+	u32 dramtmg16;
+	u32 dramtmg17;
+	u32 res6[10];
+	u32 mramtmg0;
+	u32 mramtmg1;
+	u32 mramtmg4;
+	u32 mramtmg9;
+	u32 zqctl0;
+	u32 zqctl1;
+	u32 zqctl2;
+	u32 zqstat;
+	u32 dfitmg0;
+	u32 dfitmg1;
+	u32 dfilpcfg0;
+	u32 dfilpcfg1;
+	u32 dfiupd0;
+	u32 dfiupd1;
+	u32 dfiupd2;
+	u32 res7;
+	u32 dfimisc;
+	u32 dfitmg2;
+	u32 dfitmg3;
+	u32 dfistat;
+	u32 dbictl;
+	u32 dfiphymstr;
+	u32 res8[14];
+	u32 addrmap0;
+	u32 addrmap1;
+	u32 addrmap2;
+	u32 addrmap3;
+	u32 addrmap4;
+	u32 addrmap5;
+	u32 addrmap6;
+	u32 addrmap7;
+	u32 addrmap8;
+	u32 addrmap9;
+	u32 addrmap10;
+	u32 addrmap11;
+	u32 res9[4];
+	u32 odtcfg;
+	u32 odtmap;
+	u32 res10[2];
+	u32 sched;
+	u32 sched1;
+	u32 sched2;
+	u32 perfhpr1;
+	u32 res11;
+	u32 perflpr1;
+	u32 res12;
+	u32 perfwr1;
+	u32 res13[4];
+	u32 dqmap0;
+	u32 dqmap1;
+	u32 dqmap2;
+	u32 dqmap3;
+	u32 dqmap4;
+	u32 dqmap5;
+	u32 res14[26];
+	u32 dbg0;
+	u32 dbg1;
+	u32 dbgcam;
+	u32 dbgcmd;
+	u32 dbgstat;
+	u32 res15[3];
+	u32 swctl;
+	u32 swstat;
+	u32 res16[2];
+	u32 ocparcfg0;
+	u32 ocparcfg1;
+	u32 ocparcfg2;
+	u32 ocparcfg3;
+	u32 ocparstat0;
+	u32 ocparstat1;
+	u32 ocparwlog0;
+	u32 ocparwlog1;
+	u32 ocparwlog2;
+	u32 ocparawlog0;
+	u32 ocparawlog1;
+	u32 ocparrlog0;
+	u32 ocparrlog1;
+	u32 ocpararlog0;
+	u32 ocpararlog1;
+	u32 poisoncfg;
+	u32 poisonstat;
+	u32 adveccindex;
+	union  {
+		u32 adveccstat;
+		u32 eccapstat;
+	};
+	u32 eccpoisonpat0;
+	u32 eccpoisonpat1;
+	u32 eccpoisonpat2;
+	u32 res17[6];
+	u32 caparpoisonctl;
+	u32 caparpoisonstat;
+	u32 res18[2];
+	u32 dynbsmstat;
+	u32 res19[18];
+	u32 pstat;
+	u32 pccfg;
+	struct {
+		u32 pcfgr;
+		u32 pcfgw;
+		u32 pcfgc;
+		struct {
+			u32 pcfgidmaskch0;
+			u32 pcfidvaluech0;
+		} pcfgid[16];
+		u32 pctrl;
+		u32 pcfgqos0;
+		u32 pcfgqos1;
+		u32 pcfgwqos0;
+		u32 pcfgwqos1;
+		u32 res[4];
+	} pcfg[16];
+	struct {
+		u32 sarbase;
+		u32 sarsize;
+	} sar[4];
+	u32 sbrctl;
+	u32 sbrstat;
+	u32 sbrwdata0;
+	u32 sbrwdata1;
+	u32 pdch;
+	u32 res20[755];
+	/* umctl2_regs_dch1 */
+	u32 ch1_stat;
+	u32 res21[2];
+	u32 ch1_mrctrl0;
+	u32 ch1_mrctrl1;
+	u32 ch1_mrstat;
+	u32 ch1_mrctrl2;
+	u32 res22[4];
+	u32 ch1_pwrctl;
+	u32 ch1_pwrtmg;
+	u32 ch1_hwlpctl;
+	u32 res23[15];
+	u32 ch1_eccstat;
+	u32 ch1_eccclr;
+	u32 ch1_eccerrcnt;
+	u32 ch1_ecccaddr0;
+	u32 ch1_ecccaddr1;
+	u32 ch1_ecccsyn0;
+	u32 ch1_ecccsyn1;
+	u32 ch1_ecccsyn2;
+	u32 ch1_eccbitmask0;
+	u32 ch1_eccbitmask1;
+	u32 ch1_eccbitmask2;
+	u32 ch1_eccuaddr0;
+	u32 ch1_eccuaddr1;
+	u32 ch1_eccusyn0;
+	u32 ch1_eccusyn1;
+	u32 ch1_eccusyn2;
+	u32 res24[2];
+	u32 ch1_crcparctl0;
+	u32 res25[2];
+	u32 ch1_crcparstat;
+	u32 res26[46];
+	u32 ch1_zqctl2;
+	u32 ch1_zqstat;
+	u32 res27[11];
+	u32 ch1_dfistat;
+	u32 res28[33];
+	u32 ch1_odtmap;
+	u32 res29[47];
+	u32 ch1_dbg1;
+	u32 ch1_dbgcam;
+	u32 ch1_dbgcmd;
+	u32 ch1_dbgstat;
+	u32 res30[123];
+	/* umctl2_regs_freq1 */
+	struct ddrc_freq freq1;
+	u32 res31[109];
+	/* umctl2_regs_addrmap_alt */
+	u32 addrmap0_alt;
+	u32 addrmap1_alt;
+	u32 addrmap2_alt;
+	u32 addrmap3_alt;
+	u32 addrmap4_alt;
+	u32 addrmap5_alt;
+	u32 addrmap6_alt;
+	u32 addrmap7_alt;
+	u32 addrmap8_alt;
+	u32 addrmap9_alt;
+	u32 addrmap10_alt;
+	u32 addrmap11_alt;
+	u32 res32[758];
+	/* umctl2_regs_freq2 */
+	struct ddrc_freq freq2;
+	u32 res33[879];
+	/* umctl2_regs_freq3 */
+	struct ddrc_freq freq3;
+};
+
+struct imx8m_ddrphy_regs {
+	u32 reg[0xf0000];
+};
+
+/* PHY State */
+enum pstate {
+	PS0,
+	PS1,
+	PS2,
+	PS3,
+};
+
+enum msg_response {
+	TRAIN_SUCCESS = 0x7,
+	TRAIN_STREAM_START = 0x8,
+	TRAIN_FAIL = 0xff,
+};
+
+#define DDRC_MSTR(X)             (DDRC_IPS_BASE_ADDR(X) + 0x00)
+#define DDRC_STAT(X)             (DDRC_IPS_BASE_ADDR(X) + 0x04)
+#define DDRC_MSTR1(X)            (DDRC_IPS_BASE_ADDR(X) + 0x08)
+#define DDRC_MRCTRL0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x10)
+#define DDRC_MRCTRL1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x14)
+#define DDRC_MRSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x18)
+#define DDRC_MRCTRL2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1c)
+#define DDRC_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x20)
+#define DDRC_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x24)
+#define DDRC_MSTR2(X)            (DDRC_IPS_BASE_ADDR(X) + 0x28)
+#define DDRC_PWRCTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0x30)
+#define DDRC_PWRTMG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x34)
+#define DDRC_HWLPCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0x38)
+#define DDRC_HWFFCCTL(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3c)
+#define DDRC_HWFFCSTAT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x40)
+#define DDRC_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x50)
+#define DDRC_RFSHCTL1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x54)
+#define DDRC_RFSHCTL2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x58)
+#define DDRC_RFSHCTL3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x60)
+#define DDRC_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x64)
+#define DDRC_ECCCFG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x70)
+#define DDRC_ECCCFG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x74)
+#define DDRC_ECCSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x78)
+#define DDRC_ECCCLR(X)           (DDRC_IPS_BASE_ADDR(X) + 0x7c)
+#define DDRC_ECCERRCNT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x80)
+#define DDRC_ECCCADDR0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x84)
+#define DDRC_ECCCADDR1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x88)
+#define DDRC_ECCCSYN0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x8c)
+#define DDRC_ECCCSYN1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x90)
+#define DDRC_ECCCSYN2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x94)
+#define DDRC_ECCBITMASK0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x98)
+#define DDRC_ECCBITMASK1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x9c)
+#define DDRC_ECCBITMASK2(X)      (DDRC_IPS_BASE_ADDR(X) + 0xa0)
+#define DDRC_ECCUADDR0(X)        (DDRC_IPS_BASE_ADDR(X) + 0xa4)
+#define DDRC_ECCUADDR1(X)        (DDRC_IPS_BASE_ADDR(X) + 0xa8)
+#define DDRC_ECCUSYN0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xac)
+#define DDRC_ECCUSYN1(X)         (DDRC_IPS_BASE_ADDR(X) + 0xb0)
+#define DDRC_ECCUSYN2(X)         (DDRC_IPS_BASE_ADDR(X) + 0xb4)
+#define DDRC_ECCPOISONADDR0(X)   (DDRC_IPS_BASE_ADDR(X) + 0xb8)
+#define DDRC_ECCPOISONADDR1(X)   (DDRC_IPS_BASE_ADDR(X) + 0xbc)
+#define DDRC_CRCPARCTL0(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc0)
+#define DDRC_CRCPARCTL1(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc4)
+#define DDRC_CRCPARCTL2(X)       (DDRC_IPS_BASE_ADDR(X) + 0xc8)
+#define DDRC_CRCPARSTAT(X)       (DDRC_IPS_BASE_ADDR(X) + 0xcc)
+#define DDRC_INIT0(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd0)
+#define DDRC_INIT1(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd4)
+#define DDRC_INIT2(X)            (DDRC_IPS_BASE_ADDR(X) + 0xd8)
+#define DDRC_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0xdc)
+#define DDRC_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe0)
+#define DDRC_INIT5(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe4)
+#define DDRC_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0xe8)
+#define DDRC_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0xec)
+#define DDRC_DIMMCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf0)
+#define DDRC_RANKCTL(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf4)
+#define DDRC_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x100)
+#define DDRC_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x104)
+#define DDRC_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x108)
+#define DDRC_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x10c)
+#define DDRC_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x110)
+#define DDRC_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x114)
+#define DDRC_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x118)
+#define DDRC_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x11c)
+#define DDRC_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x120)
+#define DDRC_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x124)
+#define DDRC_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x128)
+#define DDRC_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x12c)
+#define DDRC_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x130)
+#define DDRC_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x134)
+#define DDRC_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x138)
+#define DDRC_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x13C)
+#define DDRC_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x140)
+#define DDRC_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x144)
+#define DDRC_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x180)
+#define DDRC_ZQCTL1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x184)
+#define DDRC_ZQCTL2(X)           (DDRC_IPS_BASE_ADDR(X) + 0x188)
+#define DDRC_ZQSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x18c)
+#define DDRC_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x190)
+#define DDRC_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x194)
+#define DDRC_DFILPCFG0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x198)
+#define DDRC_DFILPCFG1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x19c)
+#define DDRC_DFIUPD0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
+#define DDRC_DFIUPD1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
+#define DDRC_DFIUPD2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
+#define DDRC_DFIMISC(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
+#define DDRC_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
+#define DDRC_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
+#define DDRC_DFISTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
+#define DDRC_DBICTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
+#define DDRC_DFIPHYMSTR(X)       (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
+#define DDRC_TRAINCTL0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
+#define DDRC_TRAINCTL1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
+#define DDRC_TRAINCTL2(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
+#define DDRC_TRAINSTAT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
+#define DDRC_ADDRMAP0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x200)
+#define DDRC_ADDRMAP1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x204)
+#define DDRC_ADDRMAP2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x208)
+#define DDRC_ADDRMAP3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x20c)
+#define DDRC_ADDRMAP4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x210)
+#define DDRC_ADDRMAP5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x214)
+#define DDRC_ADDRMAP6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x218)
+#define DDRC_ADDRMAP7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21c)
+#define DDRC_ADDRMAP8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x220)
+#define DDRC_ADDRMAP9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x224)
+#define DDRC_ADDRMAP10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x228)
+#define DDRC_ADDRMAP11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x22c)
+#define DDRC_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x240)
+#define DDRC_ODTMAP(X)           (DDRC_IPS_BASE_ADDR(X) + 0x244)
+#define DDRC_SCHED(X)            (DDRC_IPS_BASE_ADDR(X) + 0x250)
+#define DDRC_SCHED1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x254)
+#define DDRC_PERFHPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x25c)
+#define DDRC_PERFLPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x264)
+#define DDRC_PERFWR1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x26c)
+#define DDRC_PERFVPR1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x274)
+#define DDRC_PERFVPW1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x278)
+#define DDRC_DQMAP0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x280)
+#define DDRC_DQMAP1(X)           (DDRC_IPS_BASE_ADDR(X) + 0x284)
+#define DDRC_DQMAP2(X)           (DDRC_IPS_BASE_ADDR(X) + 0x288)
+#define DDRC_DQMAP3(X)           (DDRC_IPS_BASE_ADDR(X) + 0x28c)
+#define DDRC_DQMAP4(X)           (DDRC_IPS_BASE_ADDR(X) + 0x290)
+#define DDRC_DQMAP5(X)           (DDRC_IPS_BASE_ADDR(X) + 0x294)
+#define DDRC_DBG0(X)             (DDRC_IPS_BASE_ADDR(X) + 0x300)
+#define DDRC_DBG1(X)             (DDRC_IPS_BASE_ADDR(X) + 0x304)
+#define DDRC_DBGCAM(X)           (DDRC_IPS_BASE_ADDR(X) + 0x308)
+#define DDRC_DBGCMD(X)           (DDRC_IPS_BASE_ADDR(X) + 0x30c)
+#define DDRC_DBGSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0x310)
+#define DDRC_SWCTL(X)            (DDRC_IPS_BASE_ADDR(X) + 0x320)
+#define DDRC_SWSTAT(X)           (DDRC_IPS_BASE_ADDR(X) + 0x324)
+#define DDRC_OCPARCFG0(X)        (DDRC_IPS_BASE_ADDR(X) + 0x330)
+#define DDRC_OCPARCFG1(X)        (DDRC_IPS_BASE_ADDR(X) + 0x334)
+#define DDRC_OCPARCFG2(X)        (DDRC_IPS_BASE_ADDR(X) + 0x338)
+#define DDRC_OCPARCFG3(X)        (DDRC_IPS_BASE_ADDR(X) + 0x33c)
+#define DDRC_OCPARSTAT0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x340)
+#define DDRC_OCPARSTAT1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x344)
+#define DDRC_OCPARWLOG0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x348)
+#define DDRC_OCPARWLOG1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x34c)
+#define DDRC_OCPARWLOG2(X)       (DDRC_IPS_BASE_ADDR(X) + 0x350)
+#define DDRC_OCPARAWLOG0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x354)
+#define DDRC_OCPARAWLOG1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x358)
+#define DDRC_OCPARRLOG0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x35c)
+#define DDRC_OCPARRLOG1(X)       (DDRC_IPS_BASE_ADDR(X) + 0x360)
+#define DDRC_OCPARARLOG0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x364)
+#define DDRC_OCPARARLOG1(X)      (DDRC_IPS_BASE_ADDR(X) + 0x368)
+#define DDRC_POISONCFG(X)        (DDRC_IPS_BASE_ADDR(X) + 0x36C)
+#define DDRC_POISONSTAT(X)       (DDRC_IPS_BASE_ADDR(X) + 0x370)
+
+#define DDRC_PSTAT(X)            (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
+#define DDRC_PCCFG(X)            (DDRC_IPS_BASE_ADDR(X) + 0x400)
+#define DDRC_PCFGR_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x404)
+#define DDRC_PCFGR_1(X)          (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404)
+#define DDRC_PCFGR_2(X)          (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404)
+#define DDRC_PCFGR_3(X)          (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404)
+#define DDRC_PCFGW_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x408)
+#define DDRC_PCFGW_1(X)          (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408)
+#define DDRC_PCFGW_2(X)          (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408)
+#define DDRC_PCFGW_3(X)          (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408)
+#define DDRC_PCFGC_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x40c)
+#define DDRC_PCFGIDMASKCH(X)     (DDRC_IPS_BASE_ADDR(X) + 0x410)
+#define DDRC_PCFGIDVALUECH(X)    (DDRC_IPS_BASE_ADDR(X) + 0x414)
+#define DDRC_PCTRL_0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490)
+#define DDRC_PCTRL_1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0)
+#define DDRC_PCTRL_2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0)
+#define DDRC_PCTRL_3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0)
+#define DDRC_PCFGQOS0_0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x494)
+#define DDRC_PCFGQOS1_0(X)       (DDRC_IPS_BASE_ADDR(X) + 0x498)
+#define DDRC_PCFGWQOS0_0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x49c)
+#define DDRC_PCFGWQOS1_0(X)      (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
+#define DDRC_SARBASE0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xf04)
+#define DDRC_SARSIZE0(X)         (DDRC_IPS_BASE_ADDR(X) + 0xf08)
+#define DDRC_SBRCTL(X)           (DDRC_IPS_BASE_ADDR(X) + 0xf24)
+#define DDRC_SBRSTAT(X)          (DDRC_IPS_BASE_ADDR(X) + 0xf28)
+#define DDRC_SBRWDATA0(X)        (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
+#define DDRC_SBRWDATA1(X)        (DDRC_IPS_BASE_ADDR(X) + 0xf30)
+#define DDRC_PDCH(X)             (DDRC_IPS_BASE_ADDR(X) + 0xf34)
+
+#define DDRC_FREQ1_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2020)
+#define DDRC_FREQ1_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2024)
+#define DDRC_FREQ1_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2050)
+#define DDRC_FREQ1_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2064)
+#define DDRC_FREQ1_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
+#define DDRC_FREQ1_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
+#define DDRC_FREQ1_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
+#define DDRC_FREQ1_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
+#define DDRC_FREQ1_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2100)
+#define DDRC_FREQ1_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2104)
+#define DDRC_FREQ1_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2108)
+#define DDRC_FREQ1_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x210c)
+#define DDRC_FREQ1_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2110)
+#define DDRC_FREQ1_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2114)
+#define DDRC_FREQ1_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2118)
+#define DDRC_FREQ1_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x211c)
+#define DDRC_FREQ1_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2120)
+#define DDRC_FREQ1_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2124)
+#define DDRC_FREQ1_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2128)
+#define DDRC_FREQ1_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x212c)
+#define DDRC_FREQ1_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2130)
+#define DDRC_FREQ1_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2134)
+#define DDRC_FREQ1_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2138)
+#define DDRC_FREQ1_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x213C)
+#define DDRC_FREQ1_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2140)
+#define DDRC_FREQ1_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x2144)
+#define DDRC_FREQ1_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x2180)
+#define DDRC_FREQ1_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_FREQ1_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_FREQ1_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_FREQ1_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_FREQ1_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+#define DDRC_FREQ2_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3020)
+#define DDRC_FREQ2_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3024)
+#define DDRC_FREQ2_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3050)
+#define DDRC_FREQ2_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3064)
+#define DDRC_FREQ2_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
+#define DDRC_FREQ2_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
+#define DDRC_FREQ2_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
+#define DDRC_FREQ2_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
+#define DDRC_FREQ2_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3100)
+#define DDRC_FREQ2_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3104)
+#define DDRC_FREQ2_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3108)
+#define DDRC_FREQ2_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x310c)
+#define DDRC_FREQ2_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3110)
+#define DDRC_FREQ2_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3114)
+#define DDRC_FREQ2_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3118)
+#define DDRC_FREQ2_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x311c)
+#define DDRC_FREQ2_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3120)
+#define DDRC_FREQ2_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x3124)
+#define DDRC_FREQ2_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3128)
+#define DDRC_FREQ2_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x312c)
+#define DDRC_FREQ2_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3130)
+#define DDRC_FREQ2_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3134)
+#define DDRC_FREQ2_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3138)
+#define DDRC_FREQ2_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x313C)
+#define DDRC_FREQ2_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3140)
+#define DDRC_FREQ2_DRAMTMG17(X)        (DDRC_IPS_BASE_ADDR(X) + 0x3144)
+#define DDRC_FREQ2_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x3180)
+#define DDRC_FREQ2_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3190)
+#define DDRC_FREQ2_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x3194)
+#define DDRC_FREQ2_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
+#define DDRC_FREQ2_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
+#define DDRC_FREQ2_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x3240)
+
+#define DDRC_FREQ3_DERATEEN(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4020)
+#define DDRC_FREQ3_DERATEINT(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4024)
+#define DDRC_FREQ3_RFSHCTL0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4050)
+#define DDRC_FREQ3_RFSHTMG(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4064)
+#define DDRC_FREQ3_INIT3(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
+#define DDRC_FREQ3_INIT4(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
+#define DDRC_FREQ3_INIT6(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
+#define DDRC_FREQ3_INIT7(X)            (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
+#define DDRC_FREQ3_DRAMTMG0(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4100)
+#define DDRC_FREQ3_DRAMTMG1(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4104)
+#define DDRC_FREQ3_DRAMTMG2(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4108)
+#define DDRC_FREQ3_DRAMTMG3(X)         (DDRC_IPS_BASE_ADDR(X) + 0x410c)
+#define DDRC_FREQ3_DRAMTMG4(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4110)
+#define DDRC_FREQ3_DRAMTMG5(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4114)
+#define DDRC_FREQ3_DRAMTMG6(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4118)
+#define DDRC_FREQ3_DRAMTMG7(X)         (DDRC_IPS_BASE_ADDR(X) + 0x411c)
+#define DDRC_FREQ3_DRAMTMG8(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4120)
+#define DDRC_FREQ3_DRAMTMG9(X)         (DDRC_IPS_BASE_ADDR(X) + 0x4124)
+#define DDRC_FREQ3_DRAMTMG10(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4128)
+#define DDRC_FREQ3_DRAMTMG11(X)        (DDRC_IPS_BASE_ADDR(X) + 0x412c)
+#define DDRC_FREQ3_DRAMTMG12(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4130)
+#define DDRC_FREQ3_DRAMTMG13(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4134)
+#define DDRC_FREQ3_DRAMTMG14(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4138)
+#define DDRC_FREQ3_DRAMTMG15(X)        (DDRC_IPS_BASE_ADDR(X) + 0x413C)
+#define DDRC_FREQ3_DRAMTMG16(X)        (DDRC_IPS_BASE_ADDR(X) + 0x4140)
+
+#define DDRC_FREQ3_ZQCTL0(X)           (DDRC_IPS_BASE_ADDR(X) + 0x4180)
+#define DDRC_FREQ3_DFITMG0(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4190)
+#define DDRC_FREQ3_DFITMG1(X)          (DDRC_IPS_BASE_ADDR(X) + 0x4194)
+#define DDRC_FREQ3_DFITMG2(X)          (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
+#define DDRC_FREQ3_DFITMG3(X)          (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
+#define DDRC_FREQ3_ODTCFG(X)           (DDRC_IPS_BASE_ADDR(X) + 0x4240)
+#define DDRC_DFITMG0_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_DFITMG1_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_DFITMG2_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_DFITMG3_SHADOW(X)         (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_ODTCFG_SHADOW(X)          (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097)
+
+#define DRC_PERF_MON_BASE_ADDR(X)            (0x3d800000 + ((X) * 0x2000000))
+#define DRC_PERF_MON_CNT0_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x0)
+#define DRC_PERF_MON_CNT1_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x4)
+#define DRC_PERF_MON_CNT2_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x8)
+#define DRC_PERF_MON_CNT3_CTL(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0xC)
+#define DRC_PERF_MON_CNT0_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x20)
+#define DRC_PERF_MON_CNT1_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x24)
+#define DRC_PERF_MON_CNT2_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x28)
+#define DRC_PERF_MON_CNT3_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x2C)
+#define DRC_PERF_MON_MRR0_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x40)
+#define DRC_PERF_MON_MRR1_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x44)
+#define DRC_PERF_MON_MRR2_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x48)
+#define DRC_PERF_MON_MRR3_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x4C)
+#define DRC_PERF_MON_MRR4_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x50)
+#define DRC_PERF_MON_MRR5_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x54)
+#define DRC_PERF_MON_MRR6_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x58)
+#define DRC_PERF_MON_MRR7_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x5C)
+#define DRC_PERF_MON_MRR8_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x60)
+#define DRC_PERF_MON_MRR9_DAT(X)             (DRC_PERF_MON_BASE_ADDR(X) + 0x64)
+#define DRC_PERF_MON_MRR10_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x68)
+#define DRC_PERF_MON_MRR11_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x6C)
+#define DRC_PERF_MON_MRR12_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x70)
+#define DRC_PERF_MON_MRR13_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x74)
+#define DRC_PERF_MON_MRR14_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x78)
+#define DRC_PERF_MON_MRR15_DAT(X)            (DRC_PERF_MON_BASE_ADDR(X) + 0x7C)
+
+/* user data type */
+enum fw_type {
+	FW_1D_IMAGE,
+	FW_2D_IMAGE,
+};
+
+struct dram_cfg_param {
+	unsigned int reg;
+	unsigned int val;
+};
+
+struct dram_fsp_msg {
+	unsigned int drate;
+	enum fw_type fw_type;
+	struct dram_cfg_param *fsp_cfg;
+	unsigned int fsp_cfg_num;
+};
+
+struct dram_timing_info {
+	/* umctl2 config */
+	struct dram_cfg_param *ddrc_cfg;
+	unsigned int ddrc_cfg_num;
+	/* ddrphy config */
+	struct dram_cfg_param *ddrphy_cfg;
+	unsigned int ddrphy_cfg_num;
+	/* ddr fsp train info */
+	struct dram_fsp_msg *fsp_msg;
+	unsigned int fsp_msg_num;
+	/* ddr phy trained CSR */
+	struct dram_cfg_param *ddrphy_trained_csr;
+	unsigned int ddrphy_trained_csr_num;
+	/* ddr phy PIE */
+	struct dram_cfg_param *ddrphy_pie;
+	unsigned int ddrphy_pie_num;
+	/* initialized drate table */
+	unsigned int fsp_table[4];
+};
+
+extern struct dram_timing_info dram_timing;
+
+void ddr_load_train_firmware(enum fw_type type);
+void ddr_init(struct dram_timing_info *timing_info);
+void ddr_cfg_phy(struct dram_timing_info *timing_info);
+void load_lpddr4_phy_pie(void);
+void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
+void dram_config_save(struct dram_timing_info *info, unsigned long base);
+
+/* utils function for ddr phy training */
+void wait_ddrphy_training_complete(void);
+void ddrphy_init_set_dfi_clk(unsigned int drate);
+void ddrphy_init_read_msg_block(enum fw_type type);
+
+static inline void reg32_write(unsigned long addr, u32 val)
+{
+	writel(val, addr);
+}
+
+static inline u32 reg32_read(unsigned long addr)
+{
+	return readl(addr);
+}
+
+static inline void reg32setbit(unsigned long addr, u32 bit)
+{
+	setbits_le32(addr, (1 << bit));
+}
+
+#define dwc_ddrphy_apb_wr(addr, data) \
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
+#define dwc_ddrphy_apb_rd(addr) \
+	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
+
+extern struct dram_cfg_param ddrphy_trained_csr[];
+extern uint32_t ddrphy_trained_csr_num;
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/gpio.h b/arch/arm/include/asm/arch-imx8m/gpio.h
new file mode 100644
index 0000000..2d9fbcb
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8M_GPIO_H
+#define __ASM_ARCH_IMX8M_GPIO_H
+
+#include <asm/mach-imx/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
new file mode 100644
index 0000000..62640d9
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8M_REGS_H__
+#define __ASM_ARCH_IMX8M_REGS_H__
+
+#define ARCH_MXC
+
+#include <asm/mach-imx/regs-lcdif.h>
+
+#define ROM_VERSION_A0		IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
+#define ROM_VERSION_B0		IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
+
+#define M4_BOOTROM_BASE_ADDR   0x007E0000
+
+#define GPIO1_BASE_ADDR		0X30200000
+#define GPIO2_BASE_ADDR		0x30210000
+#define GPIO3_BASE_ADDR		0x30220000
+#define GPIO4_BASE_ADDR		0x30230000
+#define GPIO5_BASE_ADDR		0x30240000
+#define WDOG1_BASE_ADDR		0x30280000
+#define WDOG2_BASE_ADDR		0x30290000
+#define WDOG3_BASE_ADDR		0x302A0000
+#define IOMUXC_BASE_ADDR	0x30330000
+#define IOMUXC_GPR_BASE_ADDR	0x30340000
+#define OCOTP_BASE_ADDR		0x30350000
+#define ANATOP_BASE_ADDR	0x30360000
+#define CCM_BASE_ADDR		0x30380000
+#define SRC_BASE_ADDR		0x30390000
+#define GPC_BASE_ADDR		0x303A0000
+
+#define SYSCNT_RD_BASE_ADDR	0x306A0000
+#define SYSCNT_CMP_BASE_ADDR	0x306B0000
+#define SYSCNT_CTRL_BASE_ADDR	0x306C0000
+
+#define UART1_BASE_ADDR		0x30860000
+#define UART3_BASE_ADDR		0x30880000
+#define UART2_BASE_ADDR		0x30890000
+#define I2C1_BASE_ADDR		0x30A20000
+#define I2C2_BASE_ADDR		0x30A30000
+#define I2C3_BASE_ADDR		0x30A40000
+#define I2C4_BASE_ADDR		0x30A50000
+#define UART4_BASE_ADDR		0x30A60000
+#define USDHC1_BASE_ADDR	0x30B40000
+#define USDHC2_BASE_ADDR	0x30B50000
+#ifdef CONFIG_IMX8MM
+#define USDHC3_BASE_ADDR	0x30B60000
+#endif
+
+#define TZASC_BASE_ADDR		0x32F80000
+
+#define MXS_LCDIF_BASE		IS_ENABLED(CONFIG_IMX8MQ) ? \
+					0x30320000 : 0x32e00000
+
+#define SRC_IPS_BASE_ADDR	0x30390000
+#define SRC_DDRC_RCR_ADDR	0x30391000
+#define SRC_DDRC2_RCR_ADDR	0x30391004
+
+#define DDRC_DDR_SS_GPR0	0x3d000000
+#define DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
+#define DDR_CSD1_BASE_ADDR	0x40000000
+
+#if !defined(__ASSEMBLY__)
+#include <asm/types.h>
+#include <linux/bitops.h>
+#include <stdbool.h>
+
+#define GPR_TZASC_EN		BIT(0)
+#define GPR_TZASC_EN_LOCK	BIT(16)
+
+#define SRC_SCR_M4_ENABLE_OFFSET	3
+#define SRC_SCR_M4_ENABLE_MASK		BIT(3)
+#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET	0
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK	BIT(0)
+#define SRC_DDR1_ENABLE_MASK		0x8F000000UL
+#define SRC_DDR2_ENABLE_MASK		0x8F000000UL
+#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK	BIT(3)
+#define SRC_DDR1_RCR_PHY_RESET_MASK	BIT(2)
+#define SRC_DDR1_RCR_CORE_RESET_N_MASK	BIT(1)
+#define SRC_DDR1_RCR_PRESET_N_MASK	BIT(0)
+
+struct iomuxc_gpr_base_regs {
+	u32 gpr[47];
+};
+
+struct ocotp_regs {
+	u32	ctrl;
+	u32	ctrl_set;
+	u32     ctrl_clr;
+	u32	ctrl_tog;
+	u32	timing;
+	u32     rsvd0[3];
+	u32     data;
+	u32     rsvd1[3];
+	u32     read_ctrl;
+	u32     rsvd2[3];
+	u32	read_fuse_data;
+	u32     rsvd3[3];
+	u32	sw_sticky;
+	u32     rsvd4[3];
+	u32     scs;
+	u32     scs_set;
+	u32     scs_clr;
+	u32     scs_tog;
+	u32     crc_addr;
+	u32     rsvd5[3];
+	u32     crc_value;
+	u32     rsvd6[3];
+	u32     version;
+	u32     rsvd7[0xdb];
+
+	/* fuse banks */
+	struct fuse_bank {
+		u32	fuse_regs[0x10];
+	} bank[0];
+};
+
+struct fuse_bank0_regs {
+	u32 lock;
+	u32 rsvd0[3];
+	u32 uid_low;
+	u32 rsvd1[3];
+	u32 uid_high;
+	u32 rsvd2[7];
+};
+
+struct fuse_bank1_regs {
+	u32 tester3;
+	u32 rsvd0[3];
+	u32 tester4;
+	u32 rsvd1[3];
+	u32 tester5;
+	u32 rsvd2[3];
+	u32 cfg0;
+	u32 rsvd3[3];
+};
+
+#ifdef CONFIG_IMX8MQ
+struct anamix_pll {
+	u32 audio_pll1_cfg0;
+	u32 audio_pll1_cfg1;
+	u32 audio_pll2_cfg0;
+	u32 audio_pll2_cfg1;
+	u32 video_pll_cfg0;
+	u32 video_pll_cfg1;
+	u32 gpu_pll_cfg0;
+	u32 gpu_pll_cfg1;
+	u32 vpu_pll_cfg0;
+	u32 vpu_pll_cfg1;
+	u32 arm_pll_cfg0;
+	u32 arm_pll_cfg1;
+	u32 sys_pll1_cfg0;
+	u32 sys_pll1_cfg1;
+	u32 sys_pll1_cfg2;
+	u32 sys_pll2_cfg0;
+	u32 sys_pll2_cfg1;
+	u32 sys_pll2_cfg2;
+	u32 sys_pll3_cfg0;
+	u32 sys_pll3_cfg1;
+	u32 sys_pll3_cfg2;
+	u32 video_pll2_cfg0;
+	u32 video_pll2_cfg1;
+	u32 video_pll2_cfg2;
+	u32 dram_pll_cfg0;
+	u32 dram_pll_cfg1;
+	u32 dram_pll_cfg2;
+	u32 digprog;
+	u32 osc_misc_cfg;
+	u32 pllout_monitor_cfg;
+	u32 frac_pllout_div_cfg;
+	u32 sscg_pllout_div_cfg;
+};
+#else
+struct anamix_pll {
+	u32 audio_pll1_gnrl_ctl;
+	u32 audio_pll1_fdiv_ctl0;
+	u32 audio_pll1_fdiv_ctl1;
+	u32 audio_pll1_sscg_ctl;
+	u32 audio_pll1_mnit_ctl;
+	u32 audio_pll2_gnrl_ctl;
+	u32 audio_pll2_fdiv_ctl0;
+	u32 audio_pll2_fdiv_ctl1;
+	u32 audio_pll2_sscg_ctl;
+	u32 audio_pll2_mnit_ctl;
+	u32 video_pll1_gnrl_ctl;
+	u32 video_pll1_fdiv_ctl0;
+	u32 video_pll1_fdiv_ctl1;
+	u32 video_pll1_sscg_ctl;
+	u32 video_pll1_mnit_ctl;
+	u32 reserved[5];
+	u32 dram_pll_gnrl_ctl;
+	u32 dram_pll_fdiv_ctl0;
+	u32 dram_pll_fdiv_ctl1;
+	u32 dram_pll_sscg_ctl;
+	u32 dram_pll_mnit_ctl;
+	u32 gpu_pll_gnrl_ctl;
+	u32 gpu_pll_div_ctl;
+	u32 gpu_pll_locked_ctl1;
+	u32 gpu_pll_mnit_ctl;
+	u32 vpu_pll_gnrl_ctl;
+	u32 vpu_pll_div_ctl;
+	u32 vpu_pll_locked_ctl1;
+	u32 vpu_pll_mnit_ctl;
+	u32 arm_pll_gnrl_ctl;
+	u32 arm_pll_div_ctl;
+	u32 arm_pll_locked_ctl1;
+	u32 arm_pll_mnit_ctl;
+	u32 sys_pll1_gnrl_ctl;
+	u32 sys_pll1_div_ctl;
+	u32 sys_pll1_locked_ctl1;
+	u32 reserved2[24];
+	u32 sys_pll1_mnit_ctl;
+	u32 sys_pll2_gnrl_ctl;
+	u32 sys_pll2_div_ctl;
+	u32 sys_pll2_locked_ctl1;
+	u32 sys_pll2_mnit_ctl;
+	u32 sys_pll3_gnrl_ctl;
+	u32 sys_pll3_div_ctl;
+	u32 sys_pll3_locked_ctl1;
+	u32 sys_pll3_mnit_ctl;
+	u32 anamix_misc_ctl;
+	u32 anamix_clk_mnit_ctl;
+	u32 reserved3[437];
+	u32 digprog;
+};
+#endif
+
+struct fuse_bank9_regs {
+	u32 mac_addr0;
+	u32 rsvd0[3];
+	u32 mac_addr1;
+	u32 rsvd1[11];
+};
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32 scr;
+	u32 a53rcr;
+	u32 a53rcr1;
+	u32 m4rcr;
+	u32 reserved1[4];
+	u32 usbophy1_rcr;
+	u32 usbophy2_rcr;
+	u32 mipiphy_rcr;
+	u32 pciephy_rcr;
+	u32 hdmi_rcr;
+	u32 disp_rcr;
+	u32 reserved2[2];
+	u32 gpu_rcr;
+	u32 vpu_rcr;
+	u32 pcie2_rcr;
+	u32 mipiphy1_rcr;
+	u32 mipiphy2_rcr;
+	u32 reserved3;
+	u32 sbmr1;
+	u32 srsr;
+	u32 reserved4[2];
+	u32 sisr;
+	u32 simr;
+	u32 sbmr2;
+	u32 gpr1;
+	u32 gpr2;
+	u32 gpr3;
+	u32 gpr4;
+	u32 gpr5;
+	u32 gpr6;
+	u32 gpr7;
+	u32 gpr8;
+	u32 gpr9;
+	u32 gpr10;
+	u32 reserved5[985];
+	u32 ddr1_rcr;
+	u32 ddr2_rcr;
+};
+
+#define WDOG_WDT_MASK	BIT(3)
+#define WDOG_WDZST_MASK	BIT(0)
+struct wdog_regs {
+	u16	wcr;	/* Control */
+	u16	wsr;	/* Service */
+	u16	wrsr;	/* Reset Status */
+	u16	wicr;	/* Interrupt Control */
+	u16	wmcr;	/* Miscellaneous Control */
+};
+
+struct bootrom_sw_info {
+	u8 reserved_1;
+	u8 boot_dev_instance;
+	u8 boot_dev_type;
+	u8 reserved_2;
+	u32 core_freq;
+	u32 axi_freq;
+	u32 ddr_freq;
+	u32 tick_freq;
+	u32 reserved_3[3];
+};
+
+#define ROM_SW_INFO_ADDR_B0	(IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
+				 0x000009e8)
+#define ROM_SW_INFO_ADDR_A0	0x000009e8
+
+#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
+		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
+		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
new file mode 100644
index 0000000..210e96e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
@@ -0,0 +1,691 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8MM_PINS_H__
+#define __ASM_ARCH_IMX8MM_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+	IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0                               =  IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT               =  IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K                     =  IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1                            =  IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1                               =  IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO01_PWM1_OUT                                =  IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M                     =  IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2                            =  IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2                               =  IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B                            =  IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY                          =  IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3                               =  IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT                          =  IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0                        =  IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4                               =  IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT                          =  IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1                        =  IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5                               =  IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI                     =  IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY                          =  IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+	IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT                            =  IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6                               =  IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO06_ENET1_MDC                               =  IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B                             =  IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3                            =  IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7                               =  IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO                              =  IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+	IMX8MM_PAD_GPIO1_IO07_USDHC1_WP                               =  IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4                            =  IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8                               =  IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN                    =  IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B                          =  IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO08_CCM_WAIT                                =  IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9                               =  IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT                   =  IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B                          =  IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0                        =  IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO09_CCM_STOP                                =  IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10                              =  IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID                             =  IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11                              =  IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID                             =  IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT                          =  IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY                          =  IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
+	IMX8MM_PAD_GPIO1_IO11_CCM_OUT0                                =  IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12                              =  IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR                            =  IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1                        =  IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO12_CCM_OUT1                                =  IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13                              =  IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC                             =  IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO13_PWM2_OUT                                =  IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO13_CCM_OUT2                                =  IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14                              =  IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR                            =  IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B                             =  IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0),
+	IMX8MM_PAD_GPIO1_IO14_PWM3_OUT                                =  IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1                               =  IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15                              =  IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC                             =  IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO15_USDHC3_WP                               =  IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0),
+	IMX8MM_PAD_GPIO1_IO15_PWM4_OUT                                =  IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2                               =  IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_MDC_ENET1_MDC                                 =  IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_MDC_GPIO1_IO16                                =  IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_MDIO_ENET1_MDIO                               =  IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
+	IMX8MM_PAD_ENET_MDIO_GPIO1_IO17                               =  IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3                           =  IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD3_GPIO1_IO18                                =  IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2                           =  IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK                              =  IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT                     =  IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD2_GPIO1_IO19                                =  IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1                           =  IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD1_GPIO1_IO20                                =  IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0                           =  IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD0_GPIO1_IO21                                =  IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL                     =  IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22                             =  IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC                           =  IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TXC_ENET1_TX_ER                               =  IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TXC_GPIO1_IO23                                =  IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL                     =  IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24                             =  IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC                           =  IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RXC_ENET1_RX_ER                               =  IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RXC_GPIO1_IO25                                =  IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0                           =  IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RD0_GPIO1_IO26                                =  IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1                           =  IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RD1_GPIO1_IO27                                =  IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2                           =  IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RD2_GPIO1_IO28                                =  IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3                           =  IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RD3_GPIO1_IO29                                =  IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_CLK_USDHC1_CLK                                 =  IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_CLK_GPIO2_IO0                                  =  IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_CMD_USDHC1_CMD                                 =  IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_CMD_GPIO2_IO1                                  =  IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0                             =  IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA0_GPIO2_IO2                                =  IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1                             =  IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA1_GPIO2_IO3                                =  IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2                             =  IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA2_GPIO2_IO4                                =  IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3                             =  IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA3_GPIO2_IO5                                =  IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4                             =  IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA4_GPIO2_IO6                                =  IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5                             =  IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA5_GPIO2_IO7                                =  IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6                             =  IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA6_GPIO2_IO8                                =  IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7                             =  IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA7_GPIO2_IO9                                =  IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B                         =  IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10                             =  IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE                           =  IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_STROBE_GPIO2_IO11                              =  IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B                               =  IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_CD_B_GPIO2_IO12                                =  IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_CLK_USDHC2_CLK                                 =  IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_CLK_GPIO2_IO13                                 =  IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0                               =  IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_CMD_USDHC2_CMD                                 =  IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_CMD_GPIO2_IO14                                 =  IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1                               =  IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0                             =  IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA0_GPIO2_IO15                               =  IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2                             =  IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1                             =  IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA1_GPIO2_IO16                               =  IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA1_CCM_WAIT                                 =  IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2                             =  IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA2_GPIO2_IO17                               =  IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA2_CCM_STOP                                 =  IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3                             =  IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA3_GPIO2_IO18                               =  IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET                          =  IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B                         =  IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19                             =  IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET                       =  IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_WP_USDHC2_WP                                   =  IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_WP_GPIO2_IO20                                  =  IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_ALE_RAWNAND_ALE                               =  IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK                               =  IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_ALE_GPIO3_IO0                                 =  IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B                           =  IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B                            =  IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1                               =  IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B                           =  IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B                            =  IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE                           =  IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2                               =  IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B                           =  IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B                            =  IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5                            =  IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3                               =  IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B                           =  IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B                            =  IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6                            =  IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4                               =  IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_CLE_RAWNAND_CLE                               =  IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK                               =  IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CLE_USDHC3_DATA7                              =  IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CLE_GPIO3_IO5                                 =  IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00                         =  IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0                           =  IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA00_GPIO3_IO6                              =  IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01                         =  IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1                           =  IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA01_GPIO3_IO7                              =  IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02                         =  IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2                           =  IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B                            =  IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0),
+	IMX8MM_PAD_NAND_DATA02_GPIO3_IO8                              =  IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03                         =  IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3                           =  IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA03_USDHC3_WP                              =  IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0),
+	IMX8MM_PAD_NAND_DATA03_GPIO3_IO9                              =  IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04                         =  IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0                           =  IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0                           =  IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA04_GPIO3_IO10                             =  IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05                         =  IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1                           =  IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1                           =  IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA05_GPIO3_IO11                             =  IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06                         =  IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2                           =  IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2                           =  IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA06_GPIO3_IO12                             =  IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07                         =  IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3                           =  IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3                           =  IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA07_GPIO3_IO13                             =  IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DQS_RAWNAND_DQS                               =  IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DQS_QSPI_A_DQS                                =  IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DQS_GPIO3_IO14                                =  IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B                             =  IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS                               =  IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4                             =  IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_RE_B_GPIO3_IO15                               =  IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B                       =  IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B                        =  IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_READY_B_GPIO3_IO16                            =  IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B                             =  IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_WE_B_USDHC3_CLK                               =  IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_WE_B_GPIO3_IO17                               =  IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B                             =  IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_WP_B_USDHC3_CMD                               =  IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_WP_B_GPIO3_IO18                               =  IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
+	IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0                            =  IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19                               =  IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
+	IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1                             =  IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXC_PDM_CLK                                   =  IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXC_GPIO3_IO20                                =  IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0                            =  IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
+	IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2                            =  IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0                          =  IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0),
+	IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21                               =  IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1                            =  IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
+	IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3                            =  IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
+	IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC                             =  IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
+	IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1                          =  IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0),
+	IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22                               =  IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2                            =  IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
+	IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4                            =  IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
+	IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK                             =  IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
+	IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2                          =  IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0),
+	IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23                               =  IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3                            =  IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
+	IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5                            =  IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
+	IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0                            =  IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3                          =  IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0),
+	IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24                               =  IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
+	IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK                             =  IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
+	IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25                               =  IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK                           =  IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC                             =  IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
+	IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
+	IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK                   =  IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0                                =  IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK                              =  IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
+	IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL                    =  IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXC_GPIO4_IO1                                 =  IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0                            =  IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0                            =  IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
+	IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1                            =  IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0                          =  IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0),
+	IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0                      =  IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2                                =  IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0                            =  IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1                            =  IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1                            =  IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
+	IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1                          =  IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0),
+	IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1                      =  IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3                                =  IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1                            =  IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2                            =  IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2                            =  IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
+	IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2                          =  IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0),
+	IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2                      =  IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4                                =  IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2                            =  IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3                            =  IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3                            =  IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0),
+	IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3                          =  IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0),
+	IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3                      =  IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5                                =  IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3                            =  IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4                            =  IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK                             =  IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
+	IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK                             =  IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
+	IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4                      =  IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6                                =  IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4                            =  IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5                            =  IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0                            =  IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0                            =  IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
+	IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC                             =  IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
+	IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5                      =  IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7                                =  IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5                            =  IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6                            =  IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC                             =  IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
+	IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC                             =  IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
+	IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6                      =  IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8                                =  IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6                            =  IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7                            =  IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK                                =  IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
+	IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
+	IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4                            =  IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7                      =  IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9                                =  IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7                            =  IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
+	IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC                             =  IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
+	IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO                      =  IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10                               =  IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK                              =  IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
+	IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK                              =  IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
+	IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI                       =  IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXC_GPIO4_IO11                                =  IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0                            =  IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0                            =  IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8                      =  IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12                               =  IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8                            =  IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1                            =  IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1                            =  IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9                      =  IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13                               =  IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9                            =  IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2                            =  IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2                            =  IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10                     =  IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14                               =  IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10                           =  IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3                            =  IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3                            =  IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11                     =  IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15                               =  IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11                           =  IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4                            =  IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK                             =  IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
+	IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK                             =  IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
+	IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12                     =  IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16                               =  IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12                           =  IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5                            =  IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0                            =  IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
+	IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0                            =  IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13                     =  IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17                               =  IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13                           =  IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6                            =  IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC                             =  IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
+	IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC                             =  IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
+	IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14                     =  IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18                               =  IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14                           =  IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7                            =  IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK                                =  IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
+	IMX8MM_PAD_SAI1_TXD7_PDM_CLK                                  =  IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15                     =  IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19                               =  IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15                           =  IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK                                =  IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
+	IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK                             =  IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
+	IMX8MM_PAD_SAI1_MCLK_PDM_CLK                                  =  IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20                               =  IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC                             =  IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC                             =  IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
+	IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1                            =  IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1                            =  IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXFS_UART1_TX                                 =  IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXFS_UART1_RX                                 =  IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0),
+	IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21                               =  IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK                              =  IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK                              =  IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
+	IMX8MM_PAD_SAI2_RXC_UART1_RX                                  =  IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0),
+	IMX8MM_PAD_SAI2_RXC_UART1_TX                                  =  IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXC_GPIO4_IO22                                =  IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0                            =  IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0                            =  IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B                              =  IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0),
+	IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B                              =  IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23                               =  IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC                             =  IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1                            =  IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1                            =  IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B                              =  IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B                              =  IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0),
+	IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24                               =  IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK                              =  IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2                             =  IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXC_GPIO4_IO25                                =  IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0                            =  IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3                            =  IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26                               =  IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK                                =  IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
+	IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27                               =  IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC                             =  IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1                            =  IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
+	IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1                            =  IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28                               =  IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK                              =  IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXC_GPT1_CLK                                  =  IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
+	IMX8MM_PAD_SAI3_RXC_UART2_CTS_B                               =  IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXC_UART2_RTS_B                               =  IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0),
+	IMX8MM_PAD_SAI3_RXC_GPIO4_IO29                                =  IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0                             =  IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1                             =  IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0                             =  IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
+	IMX8MM_PAD_SAI3_RXD_UART2_RTS_B                               =  IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0),
+	IMX8MM_PAD_SAI3_RXD_UART2_CTS_B                               =  IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXD_GPIO4_IO30                                =  IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC                             =  IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2                            =  IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1                            =  IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
+	IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1                            =  IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXFS_UART2_RX                                 =  IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0),
+	IMX8MM_PAD_SAI3_TXFS_UART2_TX                                 =  IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31                               =  IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK                              =  IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2                             =  IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2                             =  IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
+	IMX8MM_PAD_SAI3_TXC_UART2_TX                                  =  IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXC_UART2_RX                                  =  IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0),
+	IMX8MM_PAD_SAI3_TXC_GPIO5_IO0                                 =  IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0                             =  IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3                             =  IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3                             =  IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
+	IMX8MM_PAD_SAI3_TXD_GPIO5_IO1                                 =  IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK                                =  IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_MCLK_PWM4_OUT                                 =  IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
+	IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2                                =  IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT                                =  IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_TX_PWM3_OUT                                  =  IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_TX_GPIO5_IO3                                 =  IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SPDIF_RX_SPDIF1_IN                                 =  IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_RX_PWM2_OUT                                  =  IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_RX_GPIO5_IO4                                 =  IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK                       =  IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT                             =  IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5                            =  IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK                            =  IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_SCLK_UART3_RX                               =  IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
+	IMX8MM_PAD_ECSPI1_SCLK_UART3_TX                               =  IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6                              =  IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI                            =  IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_MOSI_UART3_TX                               =  IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_MOSI_UART3_RX                               =  IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
+	IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7                              =  IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO                            =  IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B                            =  IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B                            =  IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
+	IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8                              =  IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0                              =  IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B                             =  IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
+	IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B                             =  IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9                               =  IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK                            =  IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_SCLK_UART4_RX                               =  IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
+	IMX8MM_PAD_ECSPI2_SCLK_UART4_TX                               =  IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10                             =  IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI                            =  IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_MOSI_UART4_TX                               =  IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_MOSI_UART4_RX                               =  IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
+	IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11                             =  IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO                            =  IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B                            =  IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B                            =  IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
+	IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12                             =  IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0                              =  IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B                             =  IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
+	IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B                             =  IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13                              =  IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C1_SCL_I2C1_SCL                                  =  IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C1_SCL_ENET1_MDC                                 =  IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C1_SCL_GPIO5_IO14                                =  IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C1_SDA_I2C1_SDA                                  =  IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C1_SDA_ENET1_MDIO                                =  IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
+	IMX8MM_PAD_I2C1_SDA_GPIO5_IO15                                =  IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C2_SCL_I2C2_SCL                                  =  IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN                      =  IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B                               =  IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0),
+	IMX8MM_PAD_I2C2_SCL_GPIO5_IO16                                =  IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C2_SDA_I2C2_SDA                                  =  IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT                     =  IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C2_SDA_USDHC3_WP                                 =  IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0),
+	IMX8MM_PAD_I2C2_SDA_GPIO5_IO17                                =  IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C3_SCL_I2C3_SCL                                  =  IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SCL_PWM4_OUT                                  =  IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SCL_GPT2_CLK                                  =  IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SCL_GPIO5_IO18                                =  IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C3_SDA_I2C3_SDA                                  =  IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SDA_PWM3_OUT                                  =  IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SDA_GPT3_CLK                                  =  IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SDA_GPIO5_IO19                                =  IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C4_SCL_I2C4_SCL                                  =  IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C4_SCL_PWM2_OUT                                  =  IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B                            =  IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
+	IMX8MM_PAD_I2C4_SCL_GPIO5_IO20                                =  IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C4_SDA_I2C4_SDA                                  =  IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C4_SDA_PWM1_OUT                                  =  IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C4_SDA_GPIO5_IO21                                =  IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART1_RXD_UART1_RX                                 =  IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
+	IMX8MM_PAD_UART1_RXD_UART1_TX                                 =  IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK                              =  IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART1_RXD_GPIO5_IO22                               =  IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART1_TXD_UART1_TX                                 =  IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART1_TXD_UART1_RX                                 =  IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0),
+	IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI                              =  IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART1_TXD_GPIO5_IO23                               =  IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART2_RXD_UART2_RX                                 =  IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
+	IMX8MM_PAD_UART2_RXD_UART2_TX                                 =  IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART2_RXD_ECSPI3_MISO                              =  IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART2_RXD_GPIO5_IO24                               =  IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART2_TXD_UART2_TX                                 =  IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART2_TXD_UART2_RX                                 =  IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0),
+	IMX8MM_PAD_UART2_TXD_ECSPI3_SS0                               =  IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART2_TXD_GPIO5_IO25                               =  IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART3_RXD_UART3_RX                                 =  IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
+	IMX8MM_PAD_UART3_RXD_UART3_TX                                 =  IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_RXD_UART1_CTS_B                              =  IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_RXD_UART1_RTS_B                              =  IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
+	IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B                           =  IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_RXD_GPIO5_IO26                               =  IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART3_TXD_UART3_TX                                 =  IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_TXD_UART3_RX                                 =  IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0),
+	IMX8MM_PAD_UART3_TXD_UART1_RTS_B                              =  IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
+	IMX8MM_PAD_UART3_TXD_UART1_CTS_B                              =  IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT                           =  IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_TXD_GPIO5_IO27                               =  IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART4_RXD_UART4_RX                                 =  IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
+	IMX8MM_PAD_UART4_RXD_UART4_TX                                 =  IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART4_RXD_UART2_CTS_B                              =  IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART4_RXD_UART2_RTS_B                              =  IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
+	IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B                           =  IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
+	IMX8MM_PAD_UART4_RXD_GPIO5_IO28                               =  IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART4_TXD_UART4_TX                                 =  IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART4_TXD_UART4_RX                                 =  IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0),
+	IMX8MM_PAD_UART4_TXD_UART2_RTS_B                              =  IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
+	IMX8MM_PAD_UART4_TXD_UART2_CTS_B                              =  IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART4_TXD_GPIO5_IO29                               =  IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
+};
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h
new file mode 100644
index 0000000..c71913f
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx8mq_pins.h
@@ -0,0 +1,622 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8MQ_PINS_H__
+#define __ASM_ARCH_IMX8MQ_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+		IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0                    = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT    = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__XTALOSC_REF_CLK_32K          = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__CCM_EXT_CLK1                 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO00__JTAG_FAIL                    = IOMUX_PAD(0x0290, 0x0028, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1                    = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__PWM1_OUT                     = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__XTALOSC_REF_CLK_24M          = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__CCM_EXT_CLK2                 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO01__JTAG_ACTIVE                  = IOMUX_PAD(0x0294, 0x002C, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2                    = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B                 = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_ANY               = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO02__JTAG_DE_B                    = IOMUX_PAD(0x0298, 0x0030, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3                    = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__USDHC1_VSELECT               = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__SDMA1_EXT_EVENT0             = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__XTALOSC_XTAL_OK              = IOMUX_PAD(0x029C, 0x0034, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO03__JTAG_DONE                    = IOMUX_PAD(0x029C, 0x0034, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4                    = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT               = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO04__SDMA1_EXT_EVENT1             = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO04__XTALOSC_XTAL_OK_1V           = IOMUX_PAD(0x02A0, 0x0038, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO05__GPIO1_IO5                    = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO05__ARM_PLATFORM_CM4_NMI         = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO05__CCM_PMIC_READY               = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO05__SRC_INT_BOOT                 = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO06__GPIO1_IO6                    = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO06__ENET_MDC                     = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO06__USDHC1_CD_B                  = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO06__CCM_EXT_CLK3                 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7                    = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO07__ENET_MDIO                    = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO07__USDHC1_WP                    = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO07__CCM_EXT_CLK4                 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8                    = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO08__ENET_1588_EVENT0_IN          = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO08__USDHC2_RESET_B               = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO08__CCM_WAIT                     = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9                    = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO09__ENET_1588_EVENT0_OUT         = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO09__SDMA2_EXT_EVENT0             = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO09__CCM_STOP                     = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO10__GPIO1_IO10                   = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO10__USB1_OTG_ID                  = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11                   = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO11__USB2_OTG_ID                  = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO11__CCM_PMIC_READY               = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
+
+		IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12                   = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO12__USB1_OTG_PWR                 = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO12__SDMA2_EXT_EVENT1             = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT0           = IOMUX_PAD(0x02C0, 0x0058, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13                   = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO13__USB1_OTG_OC                  = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO13__PWM2_OUT                     = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT1           = IOMUX_PAD(0x02C4, 0x005C, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14                   = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__USB2_OTG_PWR                 = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__PWM3_OUT                     = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__CCM_CLKO1                    = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT2           = IOMUX_PAD(0x02C8, 0x0060, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_GPIO1_IO15__GPIO1_IO15                   = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__USB2_OTG_OC                  = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__PWM4_OUT                     = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__CCM_CLKO2                    = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
+		IMX8MQ_PAD_GPIO1_IO15__CSU_CSU_INT_DEB              = IOMUX_PAD(0x02CC, 0x0064, 7, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_MDC__ENET_MDC                       = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_MDC__GPIO1_IO16                     = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_MDIO__ENET_MDIO                     = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
+		IMX8MQ_PAD_ENET_MDIO__GPIO1_IO17                    = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD3__ENET_RGMII_TD3                 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD3__GPIO1_IO18                     = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD2__ENET_RGMII_TD2                 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD2__ENET_TX_CLK                    = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD2__GPIO1_IO19                     = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD1__ENET_RGMII_TD1                 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD1__GPIO1_IO20                     = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TD0__ENET_RGMII_TD0                 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TD0__GPIO1_IO21                     = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TX_CTL__ENET_RGMII_TX_CTL           = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TX_CTL__GPIO1_IO22                  = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_TXC__ENET_RGMII_TXC                 = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TXC__ENET_TX_ER                     = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_TXC__GPIO1_IO23                     = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL           = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24                  = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC                 = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RXC__ENET_RX_ER                     = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RXC__GPIO1_IO25                     = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0                 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD0__GPIO1_IO26                     = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1                 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD1__GPIO1_IO27                     = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2                 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD2__GPIO1_IO28                     = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3                 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ENET_RD3__GPIO1_IO29                     = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_CLK__USDHC1_CLK                      = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_CLK__GPIO2_IO0                       = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_CMD__USDHC1_CMD                      = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_CMD__GPIO2_IO1                       = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0                  = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA0__GPIO2_IO2                     = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1                  = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA1__GPIO2_IO3                     = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2                  = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA2__GPIO2_IO4                     = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3                  = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA3__GPIO2_IO5                     = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4                  = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA4__GPIO2_IO6                     = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5                  = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA5__GPIO2_IO7                     = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6                  = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA6__GPIO2_IO8                     = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7                  = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_DATA7__GPIO2_IO9                     = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_RESET_B__USDHC1_RESET_B              = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10                  = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD1_STROBE__USDHC1_STROBE                = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11                   = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_CD_B__USDHC2_CD_B                    = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12                     = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_CLK__USDHC2_CLK                      = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_CLK__GPIO2_IO13                      = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_CMD__USDHC2_CMD                      = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_CMD__GPIO2_IO14                      = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0                  = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA0__GPIO2_IO15                    = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1                  = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA1__GPIO2_IO16                    = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA1__CCM_WAIT                      = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2                  = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA2__GPIO2_IO17                    = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA2__CCM_STOP                      = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3                  = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA3__GPIO2_IO18                    = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_DATA3__SRC_EARLY_RESET               = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_RESET_B__USDHC2_RESET_B              = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19                  = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_RESET_B__SRC_SYSTEM_RESET            = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SD2_WP__USDHC2_WP                        = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SD2_WP__GPIO2_IO20                       = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE                    = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK                    = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_ALE__GPIO3_IO0                      = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B                = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B                 = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE0_B__GPIO3_IO1                    = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE1_B__RAWNAND_CE1_B                = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE1_B__QSPI_A_SS1_B                 = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2                    = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE2_B__RAWNAND_CE2_B                = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE2_B__QSPI_B_SS0_B                 = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3                    = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CE3_B__RAWNAND_CE3_B                = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE3_B__QSPI_B_SS1_B                 = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CE3_B__GPIO3_IO4                    = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE                    = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CLE__QSPI_B_SCLK                    = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_CLE__GPIO3_IO5                      = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00              = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0                = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA00__GPIO3_IO6                   = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01              = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1                = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA01__GPIO3_IO7                   = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02              = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2                = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA02__GPIO3_IO8                   = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03              = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3                = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA03__GPIO3_IO9                   = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04              = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA04__QSPI_B_DATA0                = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10                  = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05              = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA05__QSPI_B_DATA1                = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA05__GPIO3_IO11                  = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06              = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA06__QSPI_B_DATA2                = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12                  = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07              = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA07__QSPI_B_DATA3                = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13                  = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_DQS__RAWNAND_DQS                    = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DQS__QSPI_A_DQS                     = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_DQS__GPIO3_IO14                     = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B                  = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_RE_B__QSPI_B_DQS                    = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15                    = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B            = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16                 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B                  = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17                    = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B                  = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18                    = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
+		IMX8MQ_PAD_SAI5_RXFS__SAI1_TX_DATA0                 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19                    = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
+		IMX8MQ_PAD_SAI5_RXC__SAI1_TX_DATA1                  = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20                     = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD0__SAI5_RX_DATA0                 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD0__SAI1_TX_DATA2                 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21                    = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD1__SAI5_RX_DATA1                 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_DATA3                 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__SAI1_TX_SYNC                  = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__SAI5_TX_SYNC                  = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22                    = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD2__SAI5_RX_DATA2                 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_DATA4                 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD2__SAI1_TX_SYNC                  = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
+		IMX8MQ_PAD_SAI5_RXD2__SAI5_TX_BCLK                  = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23                    = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_RXD3__SAI5_RX_DATA3                 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_DATA5                 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD3__SAI1_TX_SYNC                  = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
+		IMX8MQ_PAD_SAI5_RXD3__SAI5_TX_DATA0                 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24                    = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI5_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__SAI1_TX_BCLK                  = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__SAI4_MCLK                     = IOMUX_PAD(0x03C0, 0x0158, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25                    = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI5_MCLK__SRC_TESTER_ACK                = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXFS__SAI1_RX_SYNC                  = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
+		IMX8MQ_PAD_SAI1_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
+		IMX8MQ_PAD_SAI1_RXFS__ARM_PLATFORM_TRACE_CLK        = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXFS__GPIO4_IO0                     = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXC__SAI1_RX_BCLK                   = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
+		IMX8MQ_PAD_SAI1_RXC__ARM_PLATFORM_TRACE_CTL         = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXC__GPIO4_IO1                      = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD0__SAI1_RX_DATA0                 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD0__SAI5_RX_DATA0                 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD0__ARM_PLATFORM_TRACE0           = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD0__GPIO4_IO2                     = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD0__SRC_BOOT_CFG0                 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD1__SAI1_RX_DATA1                 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD1__SAI5_RX_DATA1                 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD1__ARM_PLATFORM_TRACE1           = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD1__GPIO4_IO3                     = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD1__SRC_BOOT_CFG1                 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD2__SAI1_RX_DATA2                 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD2__SAI5_RX_DATA2                 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD2__ARM_PLATFORM_TRACE2           = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD2__GPIO4_IO4                     = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD2__SRC_BOOT_CFG2                 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD3__SAI1_RX_DATA3                 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x04E0, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD3__SAI5_RX_DATA3                 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD3__ARM_PLATFORM_TRACE3           = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD3__GPIO4_IO5                     = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD3__SRC_BOOT_CFG3                 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD4__SAI1_RX_DATA4                 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__SAI6_TX_BCLK                  = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__SAI6_RX_BCLK                  = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__ARM_PLATFORM_TRACE4           = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__GPIO4_IO6                     = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD4__SRC_BOOT_CFG4                 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_DATA5                 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SAI6_TX_DATA0                 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SAI6_RX_DATA0                 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SAI1_RX_SYNC                  = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
+		IMX8MQ_PAD_SAI1_RXD5__ARM_PLATFORM_TRACE5           = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__GPIO4_IO7                     = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD5__SRC_BOOT_CFG5                 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD6__SAI1_RX_DATA6                 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__SAI6_TX_SYNC                  = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__SAI6_RX_SYNC                  = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__ARM_PLATFORM_TRACE6           = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__GPIO4_IO8                     = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD6__SRC_BOOT_CFG6                 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_RXD7__SAI1_RX_DATA7                 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SAI6_MCLK                     = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_SYNC                  = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SAI1_TX_DATA4                 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__ARM_PLATFORM_TRACE7           = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__GPIO4_IO9                     = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_RXD7__SRC_BOOT_CFG7                 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXFS__SAI1_TX_SYNC                  = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
+		IMX8MQ_PAD_SAI1_TXFS__SAI5_TX_SYNC                  = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
+		IMX8MQ_PAD_SAI1_TXFS__ARM_PLATFORM_EVENTO           = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10                    = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXC__SAI1_TX_BCLK                   = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
+		IMX8MQ_PAD_SAI1_TXC__SAI5_TX_BCLK                   = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
+		IMX8MQ_PAD_SAI1_TXC__ARM_PLATFORM_EVENTI            = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11                     = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD0__SAI1_TX_DATA0                 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__SAI5_TX_DATA0                 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__ARM_PLATFORM_TRACE8           = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__GPIO4_IO12                    = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD0__SRC_BOOT_CFG8                 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD1__SAI1_TX_DATA1                 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__SAI5_TX_DATA1                 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__ARM_PLATFORM_TRACE9           = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__GPIO4_IO13                    = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD1__SRC_BOOT_CFG9                 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD2__SAI1_TX_DATA2                 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__SAI5_TX_DATA2                 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__ARM_PLATFORM_TRACE10          = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__GPIO4_IO14                    = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD2__SRC_BOOT_CFG10                = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD3__SAI1_TX_DATA3                 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__SAI5_TX_DATA3                 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__ARM_PLATFORM_TRACE11          = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__GPIO4_IO15                    = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD3__SRC_BOOT_CFG11                = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD4__SAI1_TX_DATA4                 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD4__SAI6_RX_BCLK                  = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD4__SAI6_TX_BCLK                  = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD4__ARM_PLATFORM_TRACE12          = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD4__GPIO4_IO16                    = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD4__SRC_BOOT_CFG12                = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD5__SAI1_TX_DATA5                 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__SAI6_RX_DATA0                 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD5__SAI6_TX_DATA0                 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__ARM_PLATFORM_TRACE13          = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__GPIO4_IO17                    = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD5__SRC_BOOT_CFG13                = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD6__SAI1_TX_DATA6                 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD6__SAI6_RX_SYNC                  = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD6__SAI6_TX_SYNC                  = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD6__ARM_PLATFORM_TRACE14          = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD6__GPIO4_IO18                    = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD6__SRC_BOOT_CFG14                = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_TXD7__SAI1_TX_DATA7                 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD7__SAI6_MCLK                     = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
+		IMX8MQ_PAD_SAI1_TXD7__ARM_PLATFORM_TRACE15          = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD7__GPIO4_IO19                    = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_TXD7__SRC_BOOT_CFG15                = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI1_MCLK__SAI1_MCLK                     = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI1_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
+		IMX8MQ_PAD_SAI1_MCLK__SAI1_TX_BCLK                  = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
+		IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20                    = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_RXFS__SAI2_RX_SYNC                  = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXFS__SAI5_TX_SYNC                  = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
+		IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21                    = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_RXC__SAI2_RX_BCLK                   = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXC__SAI5_TX_BCLK                   = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
+		IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22                     = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_RXD0__SAI2_RX_DATA0                 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXD0__SAI5_TX_DATA0                 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_RXD0__GPIO4_IO23                    = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_TXFS__SAI2_TX_SYNC                  = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXFS__SAI5_TX_DATA1                 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXFS__GPIO4_IO24                    = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_TXC__SAI2_TX_BCLK                   = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXC__SAI5_TX_DATA2                  = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXC__GPIO4_IO25                     = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_TXD0__SAI2_TX_DATA0                 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXD0__SAI5_TX_DATA3                 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_TXD0__GPIO4_IO26                    = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI2_MCLK__SAI2_MCLK                     = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI2_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
+		IMX8MQ_PAD_SAI2_MCLK__GPIO4_IO27                    = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_RXFS__SAI3_RX_SYNC                  = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXFS__GPT1_CAPTURE1                 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXFS__SAI5_RX_SYNC                  = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
+		IMX8MQ_PAD_SAI3_RXFS__GPIO4_IO28                    = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_RXC__SAI3_RX_BCLK                   = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXC__GPT1_CAPTURE2                  = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXC__SAI5_RX_BCLK                   = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
+		IMX8MQ_PAD_SAI3_RXC__GPIO4_IO29                     = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_RXD__SAI3_RX_DATA0                  = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXD__GPT1_COMPARE1                  = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_RXD__SAI5_RX_DATA0                  = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
+		IMX8MQ_PAD_SAI3_RXD__GPIO4_IO30                     = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_TXFS__SAI3_TX_SYNC                  = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXFS__GPT1_CLK                      = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXFS__SAI5_RX_DATA1                 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
+		IMX8MQ_PAD_SAI3_TXFS__GPIO4_IO31                    = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_TXC__SAI3_TX_BCLK                   = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXC__GPT1_COMPARE2                  = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXC__SAI5_RX_DATA2                  = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
+		IMX8MQ_PAD_SAI3_TXC__GPIO5_IO0                      = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_TXD__SAI3_TX_DATA0                  = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXD__GPT1_COMPARE3                  = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_TXD__SAI5_RX_DATA3                  = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
+		IMX8MQ_PAD_SAI3_TXD__GPIO5_IO1                      = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SAI3_MCLK__SAI3_MCLK                     = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_MCLK__PWM4_OUT                      = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SAI3_MCLK__SAI5_MCLK                     = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
+		IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2                     = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SPDIF_TX__SPDIF1_OUT                     = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_TX__PWM3_OUT                       = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3                      = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SPDIF_RX__SPDIF1_IN                      = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_RX__PWM2_OUT                       = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4                      = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_SPDIF_EXT_CLK__SPDIF1_EXT_CLK            = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_EXT_CLK__PWM1_OUT                  = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_SPDIF_EXT_CLK__GPIO5_IO5                 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK                 = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_SCLK__UART3_RX                    = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
+		IMX8MQ_PAD_ECSPI1_SCLK__GPIO5_IO6                   = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI                 = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_MOSI__UART3_TX                    = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
+		IMX8MQ_PAD_ECSPI1_MOSI__GPIO5_IO7                   = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO                 = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_MISO__UART3_CTS_B                 = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
+		IMX8MQ_PAD_ECSPI1_MISO__GPIO5_IO8                   = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI1_SS0__ECSPI1_SS0                   = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI1_SS0__UART3_RTS_B                  = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
+		IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9                    = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_SCLK__ECSPI2_SCLK                 = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX                    = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
+		IMX8MQ_PAD_ECSPI2_SCLK__GPIO5_IO10                  = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_MOSI__ECSPI2_MOSI                 = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX                    = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
+		IMX8MQ_PAD_ECSPI2_MOSI__GPIO5_IO11                  = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_MISO__ECSPI2_MISO                 = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B                 = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
+		IMX8MQ_PAD_ECSPI2_MISO__GPIO5_IO12                  = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_ECSPI2_SS0__ECSPI2_SS0                   = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B                  = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
+		IMX8MQ_PAD_ECSPI2_SS0__GPIO5_IO13                   = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C1_SCL__I2C1_SCL                       = IOMUX_PAD(0x047C, 0x0214, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C1_SCL__ENET_MDC                       = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14                     = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C1_SDA__I2C1_SDA                       = IOMUX_PAD(0x0480, 0x0218, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C1_SDA__ENET_MDIO                      = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
+		IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15                     = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C2_SCL__I2C2_SCL                       = IOMUX_PAD(0x0484, 0x021C, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SCL__ENET_1588_EVENT1_IN            = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16                     = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C2_SDA__I2C2_SDA                       = IOMUX_PAD(0x0488, 0x0220, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SDA__ENET_1588_EVENT1_OUT           = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17                     = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C3_SCL__I2C3_SCL                       = IOMUX_PAD(0x048C, 0x0224, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SCL__PWM4_OUT                       = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SCL__GPT2_CLK                       = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18                     = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C3_SDA__I2C3_SDA                       = IOMUX_PAD(0x0490, 0x0228, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SDA__PWM3_OUT                       = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SDA__GPT3_CLK                       = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19                     = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C4_SCL__I2C4_SCL                       = IOMUX_PAD(0x0494, 0x022C, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SCL__PWM2_OUT                       = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SCL__PCIE1_CLKREQ_B                 = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
+		IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20                     = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_I2C4_SDA__I2C4_SDA                       = IOMUX_PAD(0x0498, 0x0230, 0x10 | 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SDA__PWM1_OUT                       = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_I2C4_SDA__PCIE2_CLKREQ_B                 = IOMUX_PAD(0x0498, 0x0230, 2, 0x0528, 0, 0),
+		IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21                     = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART1_RXD__UART1_RX                      = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
+		IMX8MQ_PAD_UART1_RXD__ECSPI3_SCLK                   = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART1_RXD__GPIO5_IO22                    = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART1_TXD__UART1_TX                      = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART1_TXD__ECSPI3_MOSI                   = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART1_TXD__GPIO5_IO23                    = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART2_RXD__UART2_RX                      = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
+		IMX8MQ_PAD_UART2_RXD__ECSPI3_MISO                   = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART2_RXD__GPIO5_IO24                    = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART2_TXD__UART2_TX                      = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART2_TXD__ECSPI3_SS0                    = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART2_TXD__GPIO5_IO25                    = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART3_RXD__UART3_RX                      = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
+		IMX8MQ_PAD_UART3_RXD__UART1_CTS_B                   = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
+		IMX8MQ_PAD_UART3_RXD__GPIO5_IO26                    = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART3_TXD__UART3_TX                      = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART3_TXD__UART1_RTS_B                   = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
+		IMX8MQ_PAD_UART3_TXD__GPIO5_IO27                    = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART4_RXD__UART4_RX                      = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
+		IMX8MQ_PAD_UART4_RXD__UART2_CTS_B                   = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
+		IMX8MQ_PAD_UART4_RXD__PCIE1_CLKREQ_B                = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
+		IMX8MQ_PAD_UART4_RXD__GPIO5_IO28                    = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
+
+		IMX8MQ_PAD_UART4_TXD__UART4_TX                      = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
+		IMX8MQ_PAD_UART4_TXD__UART2_RTS_B                   = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
+		IMX8MQ_PAD_UART4_TXD__PCIE2_CLKREQ_B                = IOMUX_PAD(0x04B8, 0x0250, 2, 0x0528, 1, 0),
+		IMX8MQ_PAD_UART4_TXD__GPIO5_IO29                    = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
+};
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/lpddr4_define.h b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h
new file mode 100644
index 0000000..caf5baf
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/lpddr4_define.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __LPDDR4_DEFINE_H_
+#define __LPDDR4_DEFINE_H_
+
+#define LPDDR4_DVFS_DBI
+#define DDR_ONE_RANK
+/* #define LPDDR4_DBI_ON */
+#define DFI_BUG_WR
+#define M845S_4GBx2
+#define PRETRAIN
+
+/* DRAM MR setting */
+#ifdef LPDDR4_DBI_ON
+#define LPDDR4_MR3			0xf1
+#define LPDDR4_PHY_DMIPinPresent	0x1
+#else
+#define LPDDR4_MR3			0x31
+#define LPDDR4_PHY_DMIPinPresent	0x0
+#endif
+
+#ifdef DDR_ONE_RANK
+#define LPDDR4_CS			0x1
+#else
+#define LPDDR4_CS			0x3
+#endif
+
+/* PHY training feature */
+#define LPDDR4_HDT_CTL_2D		0xC8
+#define LPDDR4_HDT_CTL_3200_1D		0xC8
+#define LPDDR4_HDT_CTL_400_1D		0xC8
+#define LPDDR4_HDT_CTL_100_1D		0xC8
+
+/* 400/100 training seq */
+#define LPDDR4_TRAIN_SEQ_P2		0x121f
+#define LPDDR4_TRAIN_SEQ_P1		0x121f
+#define LPDDR4_TRAIN_SEQ_P0		0x121f
+#define LPDDR4_TRAIN_SEQ_100		0x121f
+#define LPDDR4_TRAIN_SEQ_400		0x121f
+
+/* 2D share & weight */
+#define LPDDR4_2D_WEIGHT		0x1f7f
+#define LPDDR4_2D_SHARE			1
+#define LPDDR4_CATRAIN_3200_1d		0
+#define LPDDR4_CATRAIN_400		0
+#define LPDDR4_CATRAIN_100		0
+#define LPDDR4_CATRAIN_3200_2d		0
+
+/* MRS parameter */
+/* for LPDDR4 Rtt */
+#define LPDDR4_RTT40			6
+#define LPDDR4_RTT48			5
+#define LPDDR4_RTT60			4
+#define LPDDR4_RTT80			3
+#define LPDDR4_RTT120			2
+#define LPDDR4_RTT240			1
+#define LPDDR4_RTT_DIS			0
+
+/* for LPDDR4 Ron */
+#define LPDDR4_RON34			7
+#define LPDDR4_RON40			6
+#define LPDDR4_RON48			5
+#define LPDDR4_RON60			4
+#define LPDDR4_RON80			3
+
+#define LPDDR4_PHY_ADDR_RON60		0x1
+#define LPDDR4_PHY_ADDR_RON40		0x3
+#define LPDDR4_PHY_ADDR_RON30		0x7
+#define LPDDR4_PHY_ADDR_RON24		0xf
+#define LPDDR4_PHY_ADDR_RON20		0x1f
+
+/* for read channel */
+#define LPDDR4_RON			LPDDR4_RON40
+#define LPDDR4_PHY_RTT			30
+#define LPDDR4_PHY_VREF_VALUE		17
+
+/* for write channel */
+#define LPDDR4_PHY_RON			30
+#define LPDDR4_PHY_ADDR_RON		LPDDR4_PHY_ADDR_RON40
+#define LPDDR4_RTT_DQ			LPDDR4_RTT40
+#define LPDDR4_RTT_CA			LPDDR4_RTT40
+#define LPDDR4_RTT_CA_BANK0		LPDDR4_RTT40
+#define LPDDR4_RTT_CA_BANK1		LPDDR4_RTT40
+#define LPDDR4_VREF_VALUE_CA		((1 << 6) | (0xd))
+#define LPDDR4_VREF_VALUE_DQ_RANK0	((1 << 6) | (0xd))
+#define LPDDR4_VREF_VALUE_DQ_RANK1	((1 << 6) | (0xd))
+#define LPDDR4_MR22_RANK0		((0 << 5) | (1 << 4) | (0 << 3) | \
+					(LPDDR4_RTT40))
+#define LPDDR4_MR22_RANK1		((1 << 5) | (1 << 4) | (1 << 3) | \
+					(LPDDR4_RTT40))
+
+#define LPDDR4_MR3_PU_CAL		1
+
+#endif /* __LPDDR4_DEFINE_H__ */
diff --git a/arch/arm/include/asm/arch-imx8m/power-domain.h b/arch/arm/include/asm/arch-imx8m/power-domain.h
new file mode 100644
index 0000000..0f94945
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/power-domain.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H
+#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H
+
+struct imx8m_power_domain_platdata {
+	int resource_id;
+	int has_pd;
+	struct power_domain pd;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h
new file mode 100644
index 0000000..d328542
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef __ARCH_IMX8M_SYS_PROTO_H
+#define __ARCH_NMX8M_SYS_PROTO_H
+
+#include <asm/mach-imx/sys_proto.h>
+
+void set_wdog_reset(struct wdog_regs *wdog);
+void enable_tzc380(void);
+void restore_boot_params(void);
+extern unsigned long rom_pointer[];
+enum boot_device get_boot_device(void);
+bool is_usb_boot(void);
+#endif
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
new file mode 100644
index 0000000..5ab48a9
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#ifndef _LPC32XX_CLK_H
+#define _LPC32XX_CLK_H
+
+#include <asm/types.h>
+
+#define OSC_CLK_FREQUENCY	13000000
+#define RTC_CLK_FREQUENCY	32768
+
+/* Clocking and Power Control Registers */
+struct clk_pm_regs {
+	u32 reserved0[5];
+	u32 boot_map;		/* Boot Map Control Register		*/
+	u32 p0_intr_er;		/* Port 0/1 Start and Interrupt Enable	*/
+	u32 usbdiv_ctrl;	/* USB Clock Pre-Divide Register	*/
+	/* Internal Start Signal Sources Registers	*/
+	u32 start_er_int;	/* Start Enable Register		*/
+	u32 start_rsr_int;	/* Start Raw Status Register		*/
+	u32 start_sr_int;	/* Start Status Register		*/
+	u32 start_apr_int;	/* Start Activation Polarity Register	*/
+	/* Device Pin Start Signal Sources Registers	*/
+	u32 start_er_pin;	/* Start Enable Register		*/
+	u32 start_rsr_pin;	/* Start Raw Status Register		*/
+	u32 start_sr_pin;	/* Start Status Register		*/
+	u32 start_apr_pin;	/* Start Activation Polarity Register	*/
+	/* Clock Control Registers			*/
+	u32 hclkdiv_ctrl;	/* HCLK Divider Control Register	*/
+	u32 pwr_ctrl;		/* Power Control Register		*/
+	u32 pll397_ctrl;	/* PLL397 Control Register		*/
+	u32 osc_ctrl;		/* Main Oscillator Control Register	*/
+	u32 sysclk_ctrl;	/* SYSCLK Control Register		*/
+	u32 lcdclk_ctrl;	/* LCD Clock Control Register		*/
+	u32 hclkpll_ctrl;	/* HCLK PLL Control Register		*/
+	u32 reserved1;
+	u32 adclk_ctrl1;	/* ADC Clock Control1 Register		*/
+	u32 usb_ctrl;		/* USB Control Register			*/
+	u32 sdramclk_ctrl;	/* SDRAM Clock Control Register		*/
+	u32 ddr_lap_nom;	/* DDR Calibration Nominal Value	*/
+	u32 ddr_lap_count;	/* DDR Calibration Measured Value	*/
+	u32 ddr_cal_delay;	/* DDR Calibration Delay Value		*/
+	u32 ssp_ctrl;		/* SSP Control Register			*/
+	u32 i2s_ctrl;		/* I2S Clock Control Register		*/
+	u32 ms_ctrl;		/* Memory Card Control Register		*/
+	u32 reserved2[3];
+	u32 macclk_ctrl;	/* Ethernet MAC Clock Control Register	*/
+	u32 reserved3[4];
+	u32 test_clk;		/* Test Clock Selection Register	*/
+	u32 sw_int;		/* Software Interrupt Register		*/
+	u32 i2cclk_ctrl;	/* I2C Clock Control Register		*/
+	u32 keyclk_ctrl;	/* Keyboard Scan Clock Control Register	*/
+	u32 adclk_ctrl;		/* ADC Clock Control Register		*/
+	u32 pwmclk_ctrl;	/* PWM Clock Control Register		*/
+	u32 timclk_ctrl;	/* Watchdog and Highspeed Timer Control */
+	u32 timclk_ctrl1;	/* Motor and Timer Clock Control	*/
+	u32 spi_ctrl;		/* SPI Control Register			*/
+	u32 flashclk_ctrl;	/* NAND Flash Clock Control Register	*/
+	u32 reserved4;
+	u32 u3clk;		/* UART 3 Clock Control Register	*/
+	u32 u4clk;		/* UART 4 Clock Control Register	*/
+	u32 u5clk;		/* UART 5 Clock Control Register	*/
+	u32 u6clk;		/* UART 6 Clock Control Register	*/
+	u32 irdaclk;		/* IrDA Clock Control Register		*/
+	u32 uartclk_ctrl;	/* UART Clock Control Register		*/
+	u32 dmaclk_ctrl;	/* DMA Clock Control Register		*/
+	u32 autoclk_ctrl;	/* Autoclock Control Register		*/
+};
+
+/* HCLK Divider Control Register bits */
+#define CLK_HCLK_DDRAM_MASK		(0x3 << 7)
+#define CLK_HCLK_DDRAM_HALF		(0x2 << 7)
+#define CLK_HCLK_DDRAM_NOMINAL		(0x1 << 7)
+#define CLK_HCLK_DDRAM_STOPPED		(0x0 << 7)
+#define CLK_HCLK_PERIPH_DIV_MASK	(0x1F << 2)
+#define CLK_HCLK_PERIPH_DIV(n)		((((n) - 1) & 0x1F) << 2)
+#define CLK_HCLK_ARM_PLL_DIV_MASK	(0x3 << 0)
+#define CLK_HCLK_ARM_PLL_DIV_4		(0x2 << 0)
+#define CLK_HCLK_ARM_PLL_DIV_2		(0x1 << 0)
+#define CLK_HCLK_ARM_PLL_DIV_1		(0x0 << 0)
+
+/* Power Control Register bits */
+#define CLK_PWR_HCLK_RUN_PERIPH		(1 << 10)
+#define CLK_PWR_EMC_SREFREQ		(1 << 9)
+#define CLK_PWR_EMC_SREFREQ_UPDATE	(1 << 8)
+#define CLK_PWR_SDRAM_SREFREQ		(1 << 7)
+#define CLK_PWR_HIGHCORE_LEVEL		(1 << 5)
+#define CLK_PWR_SYSCLKEN_LEVEL		(1 << 4)
+#define CLK_PWR_SYSCLKEN_CTRL		(1 << 3)
+#define CLK_PWR_NORMAL_RUN		(1 << 2)
+#define CLK_PWR_HIGHCORE_CTRL		(1 << 1)
+#define CLK_PWR_STOP_MODE		(1 << 0)
+
+/* SYSCLK Control Register bits */
+#define CLK_SYSCLK_PLL397		(1 << 1)
+#define CLK_SYSCLK_MUX			(1 << 0)
+
+/* HCLK PLL Control Register bits */
+#define CLK_HCLK_PLL_OPERATING		(1 << 16)
+#define CLK_HCLK_PLL_BYPASS		(1 << 15)
+#define CLK_HCLK_PLL_DIRECT		(1 << 14)
+#define CLK_HCLK_PLL_FEEDBACK		(1 << 13)
+#define CLK_HCLK_PLL_POSTDIV_MASK	(0x3 << 11)
+#define CLK_HCLK_PLL_POSTDIV_16		(0x3 << 11)
+#define CLK_HCLK_PLL_POSTDIV_8		(0x2 << 11)
+#define CLK_HCLK_PLL_POSTDIV_4		(0x1 << 11)
+#define CLK_HCLK_PLL_POSTDIV_2		(0x0 << 11)
+#define CLK_HCLK_PLL_PREDIV_MASK	(0x3 << 9)
+#define CLK_HCLK_PLL_PREDIV_4		(0x3 << 9)
+#define CLK_HCLK_PLL_PREDIV_3		(0x2 << 9)
+#define CLK_HCLK_PLL_PREDIV_2		(0x1 << 9)
+#define CLK_HCLK_PLL_PREDIV_1		(0x0 << 9)
+#define CLK_HCLK_PLL_FEEDBACK_DIV_MASK	(0xFF << 1)
+#define CLK_HCLK_PLL_FEEDBACK_DIV(n)	((((n) - 1) & 0xFF) << 1)
+#define CLK_HCLK_PLL_LOCKED		(1 << 0)
+
+/* Ethernet MAC Clock Control Register bits	*/
+#define CLK_MAC_RMII			(0x3 << 3)
+#define CLK_MAC_MII			(0x1 << 3)
+#define CLK_MAC_MASTER			(1 << 2)
+#define CLK_MAC_SLAVE			(1 << 1)
+#define CLK_MAC_REG			(1 << 0)
+
+/* I2C Clock Control Register bits	*/
+#define CLK_I2C2_ENABLE			(1 << 1)
+#define CLK_I2C1_ENABLE			(1 << 0)
+
+/* Timer Clock Control1 Register bits */
+#define CLK_TIMCLK_MOTOR		(1 << 6)
+#define CLK_TIMCLK_TIMER3		(1 << 5)
+#define CLK_TIMCLK_TIMER2		(1 << 4)
+#define CLK_TIMCLK_TIMER1		(1 << 3)
+#define CLK_TIMCLK_TIMER0		(1 << 2)
+#define CLK_TIMCLK_TIMER5		(1 << 1)
+#define CLK_TIMCLK_TIMER4		(1 << 0)
+
+/* Timer Clock Control Register bits */
+#define CLK_TIMCLK_HSTIMER		(1 << 1)
+#define CLK_TIMCLK_WATCHDOG		(1 << 0)
+
+/* UART Clock Control Register bits */
+#define CLK_UART(n)			(1 << ((n) - 3))
+
+/* UARTn Clock Select Registers bits */
+#define CLK_UART_HCLK			(1 << 16)
+#define CLK_UART_X_DIV(n)		(((n) & 0xFF) << 8)
+#define CLK_UART_Y_DIV(n)		(((n) & 0xFF) << 0)
+
+/* DMA Clock Control Register bits */
+#define CLK_DMA_ENABLE			(1 << 0)
+
+/* NAND Clock Control Register bits */
+#define CLK_NAND_SLC			(1 << 0)
+#define CLK_NAND_MLC			(1 << 1)
+#define CLK_NAND_SLC_SELECT		(1 << 2)
+#define CLK_NAND_MLC_INT		(1 << 5)
+
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK		(1 << 0)
+
+/* SDRAMCLK register bits */
+#define CLK_SDRAM_DDR_SEL		(1 << 1)
+
+/* USB control register definitions */
+#define CLK_USBCTRL_PLL_STS		(1 << 0)
+#define CLK_USBCTRL_FDBK_PLUS1(n)	(((n) & 0xFF) << 1)
+#define CLK_USBCTRL_POSTDIV_2POW(n)	(((n) & 0x3) << 11)
+#define CLK_USBCTRL_PLL_PWRUP		(1 << 16)
+#define CLK_USBCTRL_CLK_EN1		(1 << 17)
+#define CLK_USBCTRL_CLK_EN2		(1 << 18)
+#define CLK_USBCTRL_BUS_KEEPER		(0x1 << 19)
+#define CLK_USBCTRL_USBHSTND_EN		(1 << 21)
+#define CLK_USBCTRL_USBDVND_EN		(1 << 22)
+#define CLK_USBCTRL_HCLK_EN		(1 << 24)
+
+unsigned int get_sys_clk_rate(void);
+unsigned int get_hclk_pll_rate(void);
+unsigned int get_hclk_clk_div(void);
+unsigned int get_hclk_clk_rate(void);
+unsigned int get_periph_clk_div(void);
+unsigned int get_periph_clk_rate(void);
+unsigned int get_sdram_clk_rate(void);
+
+#endif /* _LPC32XX_CLK_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
new file mode 100644
index 0000000..0836091
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common definitions for LPC32XX board configurations
+ *
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#ifndef _LPC32XX_CONFIG_H
+#define _LPC32XX_CONFIG_H
+
+
+/* Basic CPU architecture */
+
+/* UART configuration */
+#if	(CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
+	(CONFIG_SYS_LPC32XX_UART == 7)
+#if !defined(CONFIG_LPC32XX_HSUART)
+#define CONFIG_LPC32XX_HSUART
+#endif
+#endif
+
+#if !defined(CONFIG_SYS_NS16550_CLK)
+#define CONFIG_SYS_NS16550_CLK		13000000
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+		{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
+
+/* NAND */
+#if defined(CONFIG_NAND_LPC32XX_SLC)
+#define NAND_LARGE_BLOCK_PAGE_SIZE	0x800
+#define NAND_SMALL_BLOCK_PAGE_SIZE	0x200
+
+#if !defined(CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	NAND_LARGE_BLOCK_PAGE_SIZE
+#endif
+
+#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE		16
+#define CONFIG_SYS_NAND_ECCPOS		{ 10, 11, 12, 13, 14, 15, }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#else
+#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
+#endif
+
+#define CONFIG_SYS_NAND_ECCSIZE		0x100
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+						CONFIG_SYS_NAND_PAGE_SIZE)
+#endif	/* CONFIG_NAND_LPC32XX_SLC */
+
+/* NOR Flash */
+
+/* USB OHCI */
+#if defined(CONFIG_USB_OHCI_LPC32XX)
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		USB_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"lpc32xx-ohci"
+#endif
+
+#endif /* _LPC32XX_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h
new file mode 100644
index 0000000..7e0b781
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#ifndef _LPC32XX_CPU_H
+#define _LPC32XX_CPU_H
+
+/* LPC32XX Memory map */
+
+/* AHB physical base addresses */
+#define SLC_NAND_BASE	0x20020000	/* SLC NAND Flash registers base    */
+#define SSP0_BASE	0x20084000	/* SSP0 registers base              */
+#define SD_CARD_BASE	0x20098000	/* SD card interface registers base */
+#define MLC_NAND_BASE	0x200A8000	/* MLC NAND Flash registers base    */
+#define DMA_BASE	0x31000000	/* DMA controller registers base    */
+#define USB_BASE	0x31020000	/* USB registers base               */
+#define LCD_BASE	0x31040000	/* LCD registers base               */
+#define ETHERNET_BASE	0x31060000	/* Ethernet registers base          */
+#define EMC_BASE	0x31080000	/* EMC configuration registers base */
+
+/* FAB peripherals base addresses */
+#define CLK_PM_BASE	0x40004000	/* System control registers base    */
+#define HS_UART1_BASE	0x40014000	/* High speed UART 1 registers base */
+#define HS_UART2_BASE	0x40018000	/* High speed UART 2 registers base */
+#define HS_UART7_BASE	0x4001C000	/* High speed UART 7 registers base */
+#define RTC_BASE	0x40024000	/* RTC registers base               */
+#define GPIO_BASE	0x40028000	/* GPIO registers base              */
+#define MUX_BASE	0x40028000	/* MUX registers base               */
+#define WDT_BASE	0x4003C000	/* Watchdog timer registers base    */
+#define TIMER0_BASE	0x40044000	/* Timer0 registers base            */
+#define TIMER1_BASE	0x4004C000	/* Timer1 registers base            */
+#define UART_CTRL_BASE	0x40054000	/* UART control regsisters base     */
+
+/* APB peripherals base addresses */
+#define UART3_BASE	0x40080000	/* UART 3 registers base            */
+#define UART4_BASE	0x40088000	/* UART 4 registers base            */
+#define UART5_BASE	0x40090000	/* UART 5 registers base            */
+#define UART6_BASE	0x40098000	/* UART 6 registers base            */
+#define I2C1_BASE	0x400A0000	/* I2C  1 registers base            */
+#define I2C2_BASE	0x400A8000	/* I2C  2 registers base            */
+
+/* External SDRAM Memory Bank base addresses */
+#define EMC_DYCS0_BASE	0x80000000	/* SDRAM DYCS0 base address         */
+#define EMC_DYCS1_BASE	0xA0000000	/* SDRAM DYCS1 base address         */
+
+/* External Static Memory Bank base addresses */
+#define EMC_CS0_BASE	0xE0000000
+#define EMC_CS1_BASE	0xE1000000
+#define EMC_CS2_BASE	0xE2000000
+#define EMC_CS3_BASE	0xE3000000
+
+#endif /* _LPC32XX_CPU_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/dma.h b/arch/arm/include/asm/arch-lpc32xx/dma.h
new file mode 100644
index 0000000..8775491
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/dma.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * LPC32xx DMA Controller Interface
+ *
+ * Copyright (C) 2008 by NXP Semiconductors
+ * @Author: Kevin Wells
+ * @Descr: Definitions for LPC3250 chip
+ * @References: NXP LPC3250 User's Guide
+ */
+
+#ifndef _LPC32XX_DMA_H
+#define _LPC32XX_DMA_H
+
+#include <common.h>
+
+/*
+ * DMA linked list structure used with a channel's LLI register;
+ * refer to UM10326, "LPC32x0 and LPC32x0/01 User manual" - Rev. 3
+ * tables 84, 85, 86 & 87 for details.
+ */
+struct lpc32xx_dmac_ll {
+	u32 dma_src;
+	u32 dma_dest;
+	u32 next_lli;
+	u32 next_ctrl;
+};
+
+/* control register definitions */
+#define DMAC_CHAN_INT_TC_EN	(1 << 31) /* channel terminal count interrupt */
+#define DMAC_CHAN_DEST_AUTOINC	(1 << 27) /* automatic destination increment */
+#define DMAC_CHAN_SRC_AUTOINC	(1 << 26) /* automatic source increment */
+#define DMAC_CHAN_DEST_AHB1	(1 << 25) /* AHB1 master for dest. transfer */
+#define DMAC_CHAN_DEST_WIDTH_32	(1 << 22) /* Destination data width selection */
+#define DMAC_CHAN_SRC_WIDTH_32	(1 << 19) /* Source data width selection */
+#define DMAC_CHAN_DEST_BURST_1	0
+#define DMAC_CHAN_DEST_BURST_4	(1 << 15) /* Destination data burst size */
+#define DMAC_CHAN_SRC_BURST_1	0
+#define DMAC_CHAN_SRC_BURST_4	(1 << 12) /* Source data burst size */
+
+/*
+ * config_ch register definitions
+ * DMAC_CHAN_FLOW_D_xxx: flow control with DMA as the controller
+ * DMAC_DEST_PERIP: Macro for loading destination peripheral
+ * DMAC_SRC_PERIP: Macro for loading source peripheral
+ */
+#define DMAC_CHAN_FLOW_D_M2P	(0x1 << 11)
+#define DMAC_CHAN_FLOW_D_P2M	(0x2 << 11)
+#define DMAC_DEST_PERIP(n)	(((n) & 0x1F) << 6)
+#define DMAC_SRC_PERIP(n)	(((n) & 0x1F) << 1)
+
+/*
+ * config_ch register definitions
+ * (source and destination peripheral ID numbers).
+ * These can be used with the DMAC_DEST_PERIP and DMAC_SRC_PERIP macros.
+ */
+#define DMA_PERID_NAND1		1
+
+/* Channel enable bit */
+#define DMAC_CHAN_ENABLE	(1 << 0)
+
+int lpc32xx_dma_get_channel(void);
+int lpc32xx_dma_start_xfer(unsigned int channel,
+			   const struct lpc32xx_dmac_ll *desc, u32 config);
+int lpc32xx_dma_wait_status(unsigned int channel);
+
+#endif /* _LPC32XX_DMA_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h
new file mode 100644
index 0000000..20698a3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/emc.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#ifndef _LPC32XX_EMC_H
+#define _LPC32XX_EMC_H
+
+#include <asm/types.h>
+
+/* EMC Registers */
+struct emc_regs {
+	u32 ctrl;		/* Controls operation of the EMC             */
+	u32 status;		/* Provides EMC status information           */
+	u32 config;		/* Configures operation of the EMC           */
+	u32 reserved0[5];
+	u32 control;		/* Controls dyn memory operation             */
+	u32 refresh;		/* Configures dyn memory refresh operation   */
+	u32 read_config;	/* Configures the dyn memory read strategy   */
+	u32 reserved1;
+	u32 t_rp;		/* Precharge command period                  */
+	u32 t_ras;		/* Active to precharge command period        */
+	u32 t_srex;		/* Self-refresh exit time                    */
+	u32 reserved2[2];
+	u32 t_wr;		/* Write recovery time                       */
+	u32 t_rc;		/* Active to active command period           */
+	u32 t_rfc;		/* Auto-refresh period                       */
+	u32 t_xsr;		/* Exit self-refresh to active command time  */
+	u32 t_rrd;		/* Active bank A to active bank B latency    */
+	u32 t_mrd;		/* Load mode register to active command time */
+	u32 t_cdlr;		/* Last data in to read command time         */
+	u32 reserved3[8];
+	u32 extended_wait;	/* time for static memory rd/wr transfers    */
+	u32 reserved4[31];
+	u32 config0;		/* Configuration information for the SDRAM   */
+	u32 rascas0;		/* RAS and CAS latencies for the SDRAM       */
+	u32 reserved5[6];
+	u32 config1;		/* Configuration information for the SDRAM   */
+	u32 rascas1;		/* RAS and CAS latencies for the SDRAM       */
+	u32 reserved6[54];
+	struct emc_stat_t {
+		u32 config;	/* Static memory configuration               */
+		u32 waitwen;	/* Delay from chip select to write enable    */
+		u32 waitoen;	/* Delay to output enable                    */
+		u32 waitrd;	/* Delay to a read access                    */
+		u32 waitpage;	/* Delay for async page mode read            */
+		u32 waitwr;	/* Delay to a write access                   */
+		u32 waitturn;	/* Number of bus turnaround cycles           */
+		u32 reserved;
+	} stat[4];
+	u32 reserved7[96];
+	struct emc_ahb_t {
+		u32 control;	/* Control register for AHB                  */
+		u32 status;	/* Status register for AHB                   */
+		u32 timeout;	/* Timeout register for AHB                  */
+		u32 reserved[5];
+	} ahb[5];
+};
+
+/* Static Memory Configuration Register bits */
+#define EMC_STAT_CONFIG_WP		(1 << 20)
+#define EMC_STAT_CONFIG_EW		(1 << 8)
+#define EMC_STAT_CONFIG_PB		(1 << 7)
+#define EMC_STAT_CONFIG_PC		(1 << 6)
+#define EMC_STAT_CONFIG_PM		(1 << 3)
+#define EMC_STAT_CONFIG_32BIT		(2 << 0)
+#define EMC_STAT_CONFIG_16BIT		(1 << 0)
+#define EMC_STAT_CONFIG_8BIT		(0 << 0)
+
+/* Static Memory Delay Registers */
+#define EMC_STAT_WAITWEN(n)		(((n) - 1) & 0x0F)
+#define EMC_STAT_WAITOEN(n)		((n) & 0x0F)
+#define EMC_STAT_WAITRD(n)		(((n) - 1) & 0x1F)
+#define EMC_STAT_WAITPAGE(n)		(((n) - 1) & 0x1F)
+#define EMC_STAT_WAITWR(n)		(((n) - 2) & 0x1F)
+#define EMC_STAT_WAITTURN(n)		(((n) - 1) & 0x0F)
+
+/* EMC settings for DRAM */
+struct emc_dram_settings {
+	u32	cmddelay;
+	u32	config0;
+	u32	rascas0;
+	u32	rdconfig;
+	u32	trp;
+	u32	tras;
+	u32	tsrex;
+	u32	twr;
+	u32	trc;
+	u32	trfc;
+	u32	txsr;
+	u32	trrd;
+	u32	tmrd;
+	u32	tcdlr;
+	u32	refresh;
+	u32	mode;
+	u32	emode;
+};
+
+#endif /* _LPC32XX_EMC_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 0000000..93e7a88
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+	u32 p3_inp_state;
+	u32 p3_outp_set;
+	u32 p3_outp_clr;
+	u32 p3_outp_state;
+	/* Watch out! the following are shared between p2 and p3 */
+	u32 p2_p3_dir_set;
+	u32 p2_p3_dir_clr;
+	u32 p2_p3_dir_state;
+	/* Now back to 'one register for one port' */
+	u32 p2_inp_state;
+	u32 p2_outp_set;
+	u32 p2_outp_clr;
+	u32 reserved1[6];
+	u32 p0_inp_state;
+	u32 p0_outp_set;
+	u32 p0_outp_clr;
+	u32 p0_outp_state;
+	u32 p0_dir_set;
+	u32 p0_dir_clr;
+	u32 p0_dir_state;
+	u32 reserved2;
+	u32 p1_inp_state;
+	u32 p1_outp_set;
+	u32 p1_outp_clr;
+	u32 p1_outp_state;
+	u32 p1_dir_set;
+	u32 p1_dir_clr;
+	u32 p1_dir_state;
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
new file mode 100644
index 0000000..762bbee
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * LPC32xx GPIO interface macro for pin mapping.
+ *
+ * (C) Copyright 2015  DENX Software Engineering GmbH
+ * Written-by: Sylvain Lemieux <slemieux@@tycoint.com>
+ */
+
+#ifndef _LPC32XX_GPIO_GRP_H
+#define _LPC32XX_GPIO_GRP_H
+
+/*
+ * Macro to map the pin for the lpc32xx_gpio driver.
+ * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
+ *         mapping is done per register, as group of 32.
+ *         (see drivers/gpio/lpc32xx_gpio.c for details).
+ *       - macros can be use with the following pins:
+ *         P0.0 - P0.7
+ *         P1.0 - P1.23
+ *         P2.0 - P2.12
+ *         P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28
+ *         P3 GPO_0 - GPO_23
+ *         P3 GPIO_0 - GPIO_5 (output register only)
+ */
+#define LPC32XX_GPIO_P0_GRP 0
+#define LPC32XX_GPIO_P1_GRP 32
+#define LPC32XX_GPIO_P2_GRP 64
+#define LPC32XX_GPO_P3_GRP  96
+#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
+#define LPC32XX_GPI_P3_GRP  128
+
+/*
+ * A specific GPIO can be selected with this macro
+ * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1)
+ * See the LPC32x0 User's guide for GPIO group numbers
+ */
+#define LPC32XX_GPIO(x, y) ((x) + (y))
+
+#endif /* _LPC32XX_GPIO_GRP_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/i2c.h b/arch/arm/include/asm/arch-lpc32xx/i2c.h
new file mode 100644
index 0000000..5301d4c
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/i2c.h
@@ -0,0 +1,37 @@
+#ifndef _LPC32XX_I2C_H
+#define _LPC32XX_I2C_H
+
+#include <common.h>
+#include <asm/types.h>
+
+/* i2c register set */
+struct lpc32xx_i2c_base {
+	union {
+		u32 rx;
+		u32 tx;
+	};
+	u32 stat;
+	u32 ctrl;
+	u32 clk_hi;
+	u32 clk_lo;
+	u32 adr;
+	u32 rxfl;
+	u32 txfl;
+	u32 rxb;
+	u32 txb;
+	u32 stx;
+	u32 stxfl;
+};
+
+#ifdef CONFIG_DM_I2C
+enum {
+	I2C_0, I2C_1, I2C_2,
+};
+
+struct lpc32xx_i2c_dev {
+	struct lpc32xx_i2c_base *base;
+	int index;
+	uint speed;
+};
+#endif /* CONFIG_DM_I2C */
+#endif /* _LPC32XX_I2C_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h
new file mode 100644
index 0000000..d661e82
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/mux.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * LPC32xx MUX interface
+ *
+ * (C) Copyright 2015  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ */
+
+/**
+ * MUX register map for LPC32xx
+ */
+
+struct mux_regs {
+	u32 reserved1[10];
+	u32 p2_mux_set;
+	u32 p2_mux_clr;
+	u32 p2_mux_state;
+	u32 reserved2[51];
+	u32 p_mux_set;
+	u32 p_mux_clr;
+	u32 p_mux_state;
+	u32 reserved3;
+	u32 p3_mux_set;
+	u32 p3_mux_clr;
+	u32 p3_mux_state;
+	u32 reserved4;
+	u32 p0_mux_set;
+	u32 p0_mux_clr;
+	u32 p0_mux_state;
+	u32 reserved5;
+	u32 p1_mux_set;
+	u32 p1_mux_clr;
+	u32 p1_mux_state;
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
new file mode 100644
index 0000000..4675dc3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#ifndef _LPC32XX_SYS_PROTO_H
+#define _LPC32XX_SYS_PROTO_H
+
+#include <asm/arch/emc.h>
+
+void lpc32xx_uart_init(unsigned int uart_id);
+void lpc32xx_dma_init(void);
+void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
+void lpc32xx_slc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
+void lpc32xx_usb_init(void);
+#if defined(CONFIG_SPL_BUILD)
+void ddr_init(const struct emc_dram_settings *dram);
+#endif
+#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/timer.h b/arch/arm/include/asm/arch-lpc32xx/timer.h
new file mode 100644
index 0000000..302bd6b
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/timer.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#ifndef _LPC32XX_TIMER_H
+#define _LPC32XX_TIMER_H
+
+#include <asm/types.h>
+
+/* Timer/Counter Registers */
+struct timer_regs {
+	u32 ir;			/* Interrupt Register		*/
+	u32 tcr;		/* Timer Control Register	*/
+	u32 tc;			/* Timer Counter		*/
+	u32 pr;			/* Prescale Register		*/
+	u32 pc;			/* Prescale Counter		*/
+	u32 mcr;		/* Match Control Register	*/
+	u32 mr[4];		/* Match Registers		*/
+	u32 ccr;		/* Capture Control Register	*/
+	u32 cr[4];		/* Capture Registers		*/
+	u32 emr;		/* External Match Register	*/
+	u32 reserved[12];
+	u32 ctcr;		/* Count Control Register	*/
+};
+
+/* Timer/Counter Interrupt Register bits */
+#define TIMER_IR_CR(n)			(1 << ((n) + 4))
+#define TIMER_IR_MR(n)			(1 << (n))
+
+/* Timer/Counter Timer Control Register bits */
+#define TIMER_TCR_COUNTER_RESET		(1 << 1)
+#define TIMER_TCR_COUNTER_ENABLE	(1 << 0)
+#define TIMER_TCR_COUNTER_DISABLE	(0 << 0)
+
+/* Timer/Counter Match Control Register bits */
+#define TIMER_MCR_STOP(n)		(1 << (3 * (n) + 2))
+#define TIMER_MCR_RESET(n)		(1 << (3 * (n) + 1))
+#define TIMER_MCR_INTERRUPT(n)		(1 << (3 * (n)))
+
+/* Timer/Counter Capture Control Register bits */
+#define TIMER_CCR_INTERRUPT(n)		(1 << (3 * (n) + 2))
+#define TIMER_CCR_FALLING_EDGE(n)	(1 << (3 * (n) + 1))
+#define TIMER_CCR_RISING_EDGE(n)	(1 << (3 * (n)))
+
+/* Timer/Counter External Match Register bits */
+#define TIMER_EMR_EMC_TOGGLE(n)		(0x3 << (2 * (n) + 4))
+#define TIMER_EMR_EMC_SET(n)		(0x2 << (2 * (n) + 4))
+#define TIMER_EMR_EMC_CLEAR(n)		(0x1 << (2 * (n) + 4))
+#define TIMER_EMR_EMC_NOTHING(n)	(0x0 << (2 * (n) + 4))
+#define TIMER_EMR_EM(n)			(1 << (n))
+
+/* Timer/Counter Count Control Register bits */
+#define TIMER_CTCR_INPUT(n)		((n) << 2)
+#define TIMER_CTCR_MODE_COUNTER_BOTH	(0x3 << 0)
+#define TIMER_CTCR_MODE_COUNTER_FALLING	(0x2 << 0)
+#define TIMER_CTCR_MODE_COUNTER_RISING	(0x1 << 0)
+#define TIMER_CTCR_MODE_TIMER		(0x0 << 0)
+
+#endif /* _LPC32XX_TIMER_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h b/arch/arm/include/asm/arch-lpc32xx/uart.h
new file mode 100644
index 0000000..8ffd867
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/uart.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#ifndef _LPC32XX_UART_H
+#define _LPC32XX_UART_H
+
+#include <asm/types.h>
+
+/* 14-clock UART Registers */
+struct hsuart_regs {
+	union {
+		u32 rx;		/* Receiver FIFO		*/
+		u32 tx;		/* Transmitter FIFO		*/
+	};
+	u32 level;		/* FIFO Level Register		*/
+	u32 iir;		/* Interrupt ID Register	*/
+	u32 ctrl;		/* Control Register		*/
+	u32 rate;		/* Rate Control Register	*/
+};
+
+/* 14-clock UART Receiver FIFO Register bits */
+#define HSUART_RX_BREAK			(1 << 10)
+#define HSUART_RX_ERROR			(1 << 9)
+#define HSUART_RX_EMPTY			(1 << 8)
+#define HSUART_RX_DATA			(0xff << 0)
+
+/* 14-clock UART Level Register bits */
+#define HSUART_LEVEL_TX			(0xff << 8)
+#define HSUART_LEVEL_RX			(0xff << 0)
+
+/* 14-clock UART Interrupt Identification Register bits */
+#define HSUART_IIR_TX_INT_SET		(1 << 6)
+#define HSUART_IIR_RX_OE		(1 << 5)
+#define HSUART_IIR_BRK			(1 << 4)
+#define HSUART_IIR_FE			(1 << 3)
+#define HSUART_IIR_RX_TIMEOUT		(1 << 2)
+#define HSUART_IIR_RX_TRIG		(1 << 1)
+#define HSUART_IIR_TX			(1 << 0)
+
+/* 14-clock UART Control Register bits */
+#define HSUART_CTRL_HRTS_INV		(1 << 21)
+#define HSUART_CTRL_HRTS_TRIG_48	(0x3 << 19)
+#define HSUART_CTRL_HRTS_TRIG_32	(0x2 << 19)
+#define HSUART_CTRL_HRTS_TRIG_16	(0x1 << 19)
+#define HSUART_CTRL_HRTS_TRIG_8		(0x0 << 19)
+#define HSUART_CTRL_HRTS_EN		(1 << 18)
+#define HSUART_CTRL_TMO_16		(0x3 << 16)
+#define HSUART_CTRL_TMO_8		(0x2 << 16)
+#define HSUART_CTRL_TMO_4		(0x1 << 16)
+#define HSUART_CTRL_TMO_DISABLED	(0x0 << 16)
+#define HSUART_CTRL_HCTS_INV		(1 << 15)
+#define HSUART_CTRL_HCTS_EN		(1 << 14)
+#define HSUART_CTRL_HSU_OFFSET(n)	((n) << 9)
+#define HSUART_CTRL_HSU_BREAK		(1 << 8)
+#define HSUART_CTRL_HSU_ERR_INT_EN	(1 << 7)
+#define HSUART_CTRL_HSU_RX_INT_EN	(1 << 6)
+#define HSUART_CTRL_HSU_TX_INT_EN	(1 << 5)
+#define HSUART_CTRL_HSU_RX_TRIG_48	(0x5 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_32	(0x4 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_16	(0x3 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_8	(0x2 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_4	(0x1 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_1	(0x0 << 2)
+#define HSUART_CTRL_HSU_TX_TRIG_16	(0x3 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_8	(0x2 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_4	(0x1 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_0	(0x0 << 0)
+
+/* UART Control Registers */
+struct uart_ctrl_regs {
+	u32 ctrl;		/* Control Register		*/
+	u32 clkmode;		/* Clock Mode Register		*/
+	u32 loop;		/* Loopback Control Register	*/
+};
+
+/* UART Control Register bits */
+#define UART_CTRL_UART3_MD_CTRL		(1 << 11)
+#define UART_CTRL_HDPX_INV		(1 << 10)
+#define UART_CTRL_HDPX_EN		(1 << 9)
+#define UART_CTRL_UART6_IRDA		(1 << 5)
+#define UART_CTRL_IR_TX6_INV		(1 << 4)
+#define UART_CTRL_IR_RX6_INV		(1 << 3)
+#define UART_CTRL_IR_RX_LENGTH		(1 << 2)
+#define UART_CTRL_IR_TX_LENGTH		(1 << 1)
+#define UART_CTRL_UART5_USB_MODE	(1 << 0)
+
+/* UART Clock Mode Register bits */
+#define UART_CLKMODE_STATX(n)		(1 << ((n) + 16))
+#define UART_CLKMODE_STAT		(1 << 14)
+#define UART_CLKMODE_MASK(n)		(0x3 << (2 * (n) - 2))
+#define UART_CLKMODE_AUTO(n)		(0x2 << (2 * (n) - 2))
+#define UART_CLKMODE_ON(n)		(0x1 << (2 * (n) - 2))
+#define UART_CLKMODE_OFF(n)		(0x0 << (2 * (n) - 2))
+
+/* UART Loopback Control Register bits */
+#define UART_LOOPBACK(n)		(1 << ((n) - 1))
+
+#endif /* _LPC32XX_UART_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/wdt.h b/arch/arm/include/asm/arch-lpc32xx/wdt.h
new file mode 100644
index 0000000..dd0fc16
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/wdt.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#ifndef _LPC32XX_WDT_H
+#define _LPC32XX_WDT_H
+
+#include <asm/types.h>
+
+/* Watchdog Timer Registers */
+struct wdt_regs {
+	u32 isr;		/* Interrupt Status Register		*/
+	u32 ctrl;		/* Control Register			*/
+	u32 counter;		/* Counter Value Register		*/
+	u32 mctrl;		/* Match Control Register		*/
+	u32 match0;		/* Match 0 Register			*/
+	u32 emr;		/* External Match Control Register	*/
+	u32 pulse;		/* Reset Pulse Length Register		*/
+	u32 res;		/* Reset Source Register		*/
+};
+
+/* Watchdog Timer Control Register bits */
+#define WDTIM_CTRL_PAUSE_EN		(1 << 2)
+#define WDTIM_CTRL_RESET_COUNT		(1 << 1)
+#define WDTIM_CTRL_COUNT_ENAB		(1 << 0)
+
+/* Watchdog Timer Match Control Register bits */
+#define WDTIM_MCTRL_RESFRC2		(1 << 6)
+#define WDTIM_MCTRL_RESFRC1		(1 << 5)
+#define WDTIM_MCTRL_M_RES2		(1 << 4)
+#define WDTIM_MCTRL_M_RES1		(1 << 3)
+#define WDTIM_MCTRL_STOP_COUNT0		(1 << 2)
+#define WDTIM_MCTRL_RESET_COUNT0	(1 << 1)
+#define WDTIM_MCTRL_MR0_INT		(1 << 0)
+
+#endif /* _LPC32XX_WDT_H */
diff --git a/arch/arm/include/asm/arch-ls102xa/clock.h b/arch/arm/include/asm/arch-ls102xa/clock.h
new file mode 100644
index 0000000..bf67df5
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/clock.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ */
+
+#ifndef __ASM_ARCH_LS102XA_CLOCK_H_
+#define __ASM_ARCH_LS102XA_CLOCK_H_
+
+#include <common.h>
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_UART_CLK,
+	MXC_ESDHC_CLK,
+	MXC_I2C_CLK,
+	MXC_DSPI_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+ulong get_ddr_freq(ulong);
+uint get_svr(void);
+
+#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
new file mode 100644
index 0000000..9705378
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014, Freescale Semiconductor
+ */
+
+#ifndef _ASM_ARMV7_LS102XA_CONFIG_
+#define _ASM_ARMV7_LS102XA_CONFIG_
+
+#define OCRAM_BASE_ADDR				0x10000000
+#define OCRAM_SIZE				0x00010000
+#define OCRAM_BASE_S_ADDR			0x10010000
+#define OCRAM_S_SIZE				0x00010000
+
+#define CONFIG_SYS_IMMR				0x01000000
+#define CONFIG_SYS_DCSRBAR			0x20000000
+
+#define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00220000)
+#define SYS_FSL_DCSR_RCPM_ADDR	(CONFIG_SYS_DCSRBAR + 0x00222000)
+
+#define SYS_FSL_GIC_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
+#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
+#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
+#define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
+#define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
+#define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0x00e90000)
+#define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0x00e80200)
+#define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
+#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
+#define CONFIG_SYS_FSL_RCPM_ADDR		(CONFIG_SYS_IMMR + 0x00ee2000)
+#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
+#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
+#define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
+#define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_EHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x07600000)
+
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x00700000
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x00710000
+#define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
+#define CONFIG_SYS_TSEC2_OFFSET			0x01d50000
+#define CONFIG_SYS_TSEC3_OFFSET			0x01d90000
+#define CONFIG_SYS_MDIO1_OFFSET			0x01d24000
+
+#define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+
+#define SCTR_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01b00000)
+
+#define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
+#define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01190000)
+#define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011a0000)
+
+#define WDOG1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01ad0000)
+
+#define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
+#define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
+
+#define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
+
+#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+
+#define CONFIG_SYS_PCIE1_PHYS_BASE		0x4000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_BASE		0x4800000000ULL
+#define CONFIG_SYS_PCIE1_VIRT_ADDR		0x24000000UL
+#define CONFIG_SYS_PCIE2_VIRT_ADDR		0x34000000UL
+#define CONFIG_SYS_PCIE_MMAP_SIZE		(192 * 1024 * 1024) /* 192M */
+/*
+ * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
+ * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
+ */
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		(CONFIG_SYS_PCIE1_PHYS_BASE + \
+						 CONFIG_SYS_PCIE1_VIRT_ADDR)
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		(CONFIG_SYS_PCIE2_PHYS_BASE + \
+						 CONFIG_SYS_PCIE2_VIRT_ADDR)
+
+/* SATA */
+#define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#ifdef CONFIG_DDR_SPD
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED			CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+#endif
+
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_DCU_BE
+#define CONFIG_SYS_FSL_SEC_MON_LE
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+
+#define DCU_LAYER_MAX_NUM			16
+
+#ifdef CONFIG_ARCH_LS1021A
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		1
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+#else
+#error SoC not defined
+#endif
+
+#define FSL_IFC_COMPAT		"fsl,ifc"
+#define FSL_QSPI_COMPAT		"fsl,ls1021a-qspi"
+#define FSL_DSPI_COMPAT		"fsl,ls1021a-v1.0-dspi"
+
+#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
new file mode 100644
index 0000000..d99a6f3
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_SERDES_H
+#define __FSL_SERDES_H
+
+#include <config.h>
+
+enum srds_prtcl {
+	/*
+	 * Nobody will check whether the device 'NONE' has been configured,
+	 * So use it to indicate if the serdes_prtcl_map has been initialized.
+	 */
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	SATA1,
+	SGMII_TSEC1,
+	SGMII_TSEC2,
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+};
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+const char *serdes_clock_to_string(u32 clock);
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+
+#endif /* __FSL_SERDES_H */
diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h
new file mode 100644
index 0000000..dad181e
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/gpio.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_LS102XA_GPIO_H_
+#define __ASM_ARCH_LS102XA_GPIO_H_
+
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
new file mode 100644
index 0000000..f2ba182
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -0,0 +1,432 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
+#define __ASM_ARCH_LS102XA_IMMAP_H_
+#include <fsl_immap.h>
+
+#define SVR_MAJ(svr)		(((svr) >>  4) & 0xf)
+#define SVR_MIN(svr)		(((svr) >>  0) & 0xf)
+#define SVR_SOC_VER(svr)	(((svr) >> 8) & 0x7ff)
+#define IS_E_PROCESSOR(svr)	(svr & 0x80000)
+#define IS_SVR_REV(svr, maj, min) \
+		((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
+
+#define SOC_VER_SLS1020		0x00
+#define SOC_VER_LS1020		0x10
+#define SOC_VER_LS1021		0x11
+#define SOC_VER_LS1022		0x12
+
+#define SOC_MAJOR_VER_1_0	0x1
+#define SOC_MAJOR_VER_2_0	0x2
+
+#define CCSR_BRR_OFFSET		0xe4
+#define CCSR_SCRATCHRW1_OFFSET	0x200
+
+#define RCWSR0_SYS_PLL_RAT_SHIFT	25
+#define RCWSR0_SYS_PLL_RAT_MASK		0x1f
+#define RCWSR0_MEM_PLL_RAT_SHIFT	16
+#define RCWSR0_MEM_PLL_RAT_MASK		0x3f
+
+#define RCWSR4_SRDS1_PRTCL_SHIFT	24
+#define RCWSR4_SRDS1_PRTCL_MASK		0xff000000
+
+#define TIMER_COMP_VAL			0xffffffffffffffffull
+#define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
+#define SYS_COUNTER_CTRL_ENABLE		(1 << 24)
+
+#define DCFG_CCSR_PORSR1_RCW_MASK	0xff800000
+#define DCFG_CCSR_PORSR1_RCW_SRC_I2C	0x24800000
+
+#define DCFG_DCSR_PORCR1		0
+
+/*
+ * Define default values for some CCSR macros to make header files cleaner
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_IMMR
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_IMMR
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
+struct sys_info {
+	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	unsigned long freq_systembus;
+	unsigned long freq_ddrbus;
+	unsigned long freq_localbus;
+};
+
+#define CCSR_DEVDISR1_QE	0x00000001
+
+/* Device Configuration and Pin Control */
+struct ccsr_gur {
+	u32     porsr1;         /* POR status 1 */
+	u32     porsr2;         /* POR status 2 */
+	u8      res_008[0x20-0x8];
+	u32     gpporcr1;       /* General-purpose POR configuration */
+	u32	gpporcr2;
+	u32     dcfg_fusesr;    /* Fuse status register */
+	u8      res_02c[0x70-0x2c];
+	u32     devdisr;        /* Device disable control */
+	u32     devdisr2;       /* Device disable control 2 */
+	u32     devdisr3;       /* Device disable control 3 */
+	u32     devdisr4;       /* Device disable control 4 */
+	u32     devdisr5;       /* Device disable control 5 */
+	u8      res_084[0x94-0x84];
+	u32     coredisru;      /* uppper portion for support of 64 cores */
+	u32     coredisrl;      /* lower portion for support of 64 cores */
+	u8      res_09c[0xa4-0x9c];
+	u32     svr;            /* System version */
+	u8	res_0a8[0xb0-0xa8];
+	u32	rstcr;		/* Reset control */
+	u32	rstrqpblsr;	/* Reset request preboot loader status */
+	u8	res_0b8[0xc0-0xb8];
+	u32	rstrqmr1;	/* Reset request mask */
+	u8	res_0c4[0xc8-0xc4];
+	u32	rstrqsr1;	/* Reset request status */
+	u8	res_0cc[0xd4-0xcc];
+	u32	rstrqwdtmrl;	/* Reset request WDT mask */
+	u8	res_0d8[0xdc-0xd8];
+	u32	rstrqwdtsrl;	/* Reset request WDT status */
+	u8	res_0e0[0xe4-0xe0];
+	u32	brrl;		/* Boot release */
+	u8      res_0e8[0x100-0xe8];
+	u32     rcwsr[16];      /* Reset control word status */
+#define RCW_SB_EN_REG_INDEX	7
+#define RCW_SB_EN_MASK		0x00200000
+	u8      res_140[0x200-0x140];
+	u32     scratchrw[4];  /* Scratch Read/Write */
+	u8      res_210[0x300-0x210];
+	u32     scratchw1r[4];  /* Scratch Read (Write once) */
+	u8      res_310[0x400-0x310];
+	u32	crstsr;
+	u8      res_404[0x550-0x404];
+	u32	sataliodnr;
+	u8	res_554[0x604-0x554];
+	u32	pamubypenr;
+	u32	dmacr1;
+	u8      res_60c[0x740-0x60c];   /* add more registers when needed */
+	u32     tp_ityp[64];    /* Topology Initiator Type Register */
+	struct {
+		u32     upper;
+		u32     lower;
+	} tp_cluster[1];        /* Core Cluster n Topology Register */
+	u8	res_848[0xe60-0x848];
+	u32	ddrclkdr;
+	u8	res_e60[0xe68-0xe64];
+	u32	ifcclkdr;
+	u8	res_e68[0xe80-0xe6c];
+	u32	sdhcpcr;
+};
+
+#define SCFG_ETSECDMAMCR_LE_BD_FR	0x00000c00
+#define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
+#define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
+#define SCFG_ETSECCMCR_GE0_CLK125	0x00000000
+#define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
+#define SCFG_PIXCLKCR_PXCKEN		0x80000000
+#define SCFG_QSPI_CLKSEL		0x50100000
+#define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
+#define SCFG_SNPCNFGCR_DCU_RD_WR	0x03000000
+#define SCFG_SNPCNFGCR_SATA_RD_WR	0x00c00000
+#define SCFG_SNPCNFGCR_USB3_RD_WR	0x00300000
+#define SCFG_SNPCNFGCR_DBG_RD_WR	0x000c0000
+#define SCFG_SNPCNFGCR_EDMA_SNP		0x00020000
+#define SCFG_ENDIANCR_LE		0x80000000
+#define SCFG_DPSLPCR_WDRR_EN		0x00000001
+#define SCFG_PMCINTECR_LPUART		0x40000000
+#define SCFG_PMCINTECR_FTM		0x20000000
+#define SCFG_PMCINTECR_GPIO		0x10000000
+#define SCFG_PMCINTECR_IRQ0		0x08000000
+#define SCFG_PMCINTECR_IRQ1		0x04000000
+#define SCFG_PMCINTECR_ETSECRXG0	0x00800000
+#define SCFG_PMCINTECR_ETSECRXG1	0x00400000
+#define SCFG_PMCINTECR_ETSECERRG0	0x00080000
+#define SCFG_PMCINTECR_ETSECERRG1	0x00040000
+#define SCFG_CLUSTERPMCR_WFIL2EN	0x80000000
+
+#define SCFG_BASE			0x01570000
+#define SCFG_USB3PRM1CR			0x070
+#define SCFG_USB_TXVREFTUNE		0x9
+#define SCFG_USB_SQRXTUNE_MASK		0x7
+#define SCFG_USB3PRM2CR			0x074
+#define SCFG_USB_PCSTXSWINGFULL_MASK	0x0000FE00
+#define SCFG_USB_PCSTXSWINGFULL_VAL		0x00008E00
+
+#define USB_PHY_BASE			0x08510000
+#define USB_PHY_RX_OVRD_IN_HI	0x200c
+#define USB_PHY_RX_EQ_VAL_1		0x0000
+#define USB_PHY_RX_EQ_VAL_2		0x8000
+#define USB_PHY_RX_EQ_VAL_3		0x8004
+#define USB_PHY_RX_EQ_VAL_4		0x800C
+
+/* Supplemental Configuration Unit */
+struct ccsr_scfg {
+	u32 dpslpcr;
+	u32 resv0[2];
+	u32 etsecclkdpslpcr;
+	u32 resv1[5];
+	u32 fuseovrdcr;
+	u32 pixclkcr;
+	u32 resv2[5];
+	u32 spimsicr;
+	u32 resv3[6];
+	u32 pex1pmwrcr;
+	u32 pex1pmrdsr;
+	u32 resv4[3];
+	u32 usb3prm1cr;
+	u32 usb4prm2cr;
+	u32 pex1rdmsgpldlsbsr;
+	u32 pex1rdmsgpldmsbsr;
+	u32 pex2rdmsgpldlsbsr;
+	u32 pex2rdmsgpldmsbsr;
+	u32 pex1rdmmsgrqsr;
+	u32 pex2rdmmsgrqsr;
+	u32 spimsiclrcr;
+	u32 pexmscportsr[2];
+	u32 pex2pmwrcr;
+	u32 resv5[24];
+	u32 mac1_streamid;
+	u32 mac2_streamid;
+	u32 mac3_streamid;
+	u32 pex1_streamid;
+	u32 pex2_streamid;
+	u32 dma_streamid;
+	u32 sata_streamid;
+	u32 usb3_streamid;
+	u32 qe_streamid;
+	u32 sdhc_streamid;
+	u32 adma_streamid;
+	u32 letechsftrstcr;
+	u32 core0_sft_rst;
+	u32 core1_sft_rst;
+	u32 resv6[1];
+	u32 usb_hi_addr;
+	u32 etsecclkadjcr;
+	u32 sai_clk;
+	u32 resv7[1];
+	u32 dcu_streamid;
+	u32 usb2_streamid;
+	u32 ftm_reset;
+	u32 altcbar;
+	u32 qspi_cfg;
+	u32 pmcintecr;
+	u32 pmcintlecr;
+	u32 pmcintsr;
+	u32 qos1;
+	u32 qos2;
+	u32 qos3;
+	u32 cci_cfg;
+	u32 endiancr;
+	u32 etsecdmamcr;
+	u32 usb3prm3cr;
+	u32 resv9[1];
+	u32 debug_streamid;
+	u32 resv10[5];
+	u32 snpcnfgcr;
+	u32 hrstcr;
+	u32 intpcr;
+	u32 resv12[20];
+	u32 scfgrevcr;
+	u32 coresrencr;
+	u32 pex2pmrdsr;
+	u32 eddrtqcfg;
+	u32 ddrc2cr;
+	u32 ddrc3cr;
+	u32 ddrc4cr;
+	u32 ddrgcr;
+	u32 resv13[120];
+	u32 qeioclkcr;
+	u32 etsecmcr;
+	u32 sdhciovserlcr;
+	u32 resv14[61];
+	u32 sparecr[8];
+	u32 resv15[248];
+	u32 core0sftrstsr;
+	u32 clusterpmcr;
+};
+
+/* Clocking */
+struct ccsr_clk {
+	struct {
+		u32 clkcncsr;	/* core cluster n clock control status */
+		u8  res_004[0x1c];
+	} clkcsr[2];
+	u8	res_040[0x7c0]; /* 0x100 */
+	struct {
+		u32 pllcngsr;
+		u8 res_804[0x1c];
+	} pllcgsr[2];
+	u8	res_840[0x1c0];
+	u32	clkpcsr;	/* 0xa00 Platform clock domain control/status */
+	u8	res_a04[0x1fc];
+	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
+	u8	res_c04[0x1c];
+	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
+	u8	res_c24[0x3dc];
+};
+
+/* System Counter */
+struct sctr_regs {
+	u32 cntcr;
+	u32 cntsr;
+	u32 cntcv1;
+	u32 cntcv2;
+	u32 resv1[4];
+	u32 cntfid0;
+	u32 cntfid1;
+	u32 resv2[1002];
+	u32 counterid[12];
+};
+
+#define MAX_SERDES			1
+#define SRDS_MAX_LANES			4
+#define SRDS_MAX_BANK			2
+
+#define SRDS_RSTCTL_RST			0x80000000
+#define SRDS_RSTCTL_RSTDONE		0x40000000
+#define SRDS_RSTCTL_RSTERR		0x20000000
+#define SRDS_RSTCTL_SWRST		0x10000000
+#define SRDS_RSTCTL_SDEN		0x00000020
+#define SRDS_RSTCTL_SDRST_B		0x00000040
+#define SRDS_RSTCTL_PLLRST_B		0x00000080
+#define SRDS_PLLCR0_POFF		0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_PLL_LCK		0x00800000
+#define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
+#define SRDS_PLLCR1_PLL_BWSEL		0x08000000
+
+struct ccsr_serdes {
+	struct {
+		u32	rstctl;	/* Reset Control Register */
+
+		u32	pllcr0; /* PLL Control Register 0 */
+
+		u32	pllcr1; /* PLL Control Register 1 */
+		u32	res_0c;	/* 0x00c */
+		u32	pllcr3;
+		u32	pllcr4;
+		u8	res_18[0x20-0x18];
+	} bank[2];
+	u8	res_40[0x90-0x40];
+	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
+	u8	res_94[0xa0-0x94];
+	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
+	u8	res_a4[0xb0-0xa4];
+	u32	srdsgr0;	/* 0xb0 General Register 0 */
+	u8	res_b4[0xe0-0xb4];
+	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
+	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
+	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
+	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
+	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
+	u8	res_f4[0x100-0xf4];
+	struct {
+		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
+		u8	res_104[0x120-0x104];
+	} srdslnpssr[4];
+	u8	res_180[0x300-0x180];
+	u32	srdspexeqcr;
+	u32	srdspexeqpcr[11];
+	u8	res_330[0x400-0x330];
+	u32	srdspexapcr;
+	u8	res_404[0x440-0x404];
+	u32	srdspexbpcr;
+	u8	res_444[0x800-0x444];
+	struct {
+		u32	gcr0;	/* 0x800 General Control Register 0 */
+		u32	gcr1;	/* 0x804 General Control Register 1 */
+		u32	gcr2;	/* 0x808 General Control Register 2 */
+		u32	sscr0;
+		u32	recr0;	/* 0x810 Receive Equalization Control */
+		u32	recr1;
+		u32	tecr0;	/* 0x818 Transmit Equalization Control */
+		u32	sscr1;
+		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
+		u8	res_824[0x83c-0x824];
+		u32	tcsr3;
+	} lane[4];	/* Lane A, B, C, D, E, F, G, H */
+	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
+};
+
+#define RCPM_POWMGTCSR			0x130
+#define RCPM_POWMGTCSR_SERDES_PW	0x80000000
+#define RCPM_POWMGTCSR_LPM20_REQ	0x00100000
+#define RCPM_POWMGTCSR_LPM20_ST		0x00000200
+#define RCPM_POWMGTCSR_P_LPM20_ST	0x00000100
+#define RCPM_IPPDEXPCR0			0x140
+#define RCPM_IPPDEXPCR0_ETSEC		0x80000000
+#define RCPM_IPPDEXPCR0_GPIO		0x00000040
+#define RCPM_IPPDEXPCR1			0x144
+#define RCPM_IPPDEXPCR1_LPUART		0x40000000
+#define RCPM_IPPDEXPCR1_FLEXTIMER	0x20000000
+#define RCPM_IPPDEXPCR1_OCRAM1		0x10000000
+#define RCPM_NFIQOUTR			0x15c
+#define RCPM_NIRQOUTR			0x16c
+#define RCPM_DSIMSKR			0x18c
+#define RCPM_CLPCL10SETR		0x1c4
+#define RCPM_CLPCL10SETR_C0		0x00000001
+
+struct ccsr_rcpm {
+	u8 rev1[0x4c];
+	u32 twaitsr;
+	u8 rev2[0xe0];
+	u32 powmgtcsr;
+	u8 rev3[0xc];
+	u32 ippdexpcr0;
+	u32 ippdexpcr1;
+	u8 rev4[0x14];
+	u32 nfiqoutr;
+	u8 rev5[0xc];
+	u32 nirqoutr;
+	u8 rev6[0x1c];
+	u32 dsimskr;
+	u8 rev7[0x34];
+	u32 clpcl10setr;
+};
+
+uint get_svr(void);
+
+#endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/imx-regs.h b/arch/arm/include/asm/arch-ls102xa/imx-regs.h
new file mode 100644
index 0000000..64853d8
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/imx-regs.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define I2C_QUIRK_REG	/* enable 8-bit driver */
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h
new file mode 100644
index 0000000..5d6a4e7
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_devdis.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_LS102XA_DEVDIS_H_
+#define __FSL_LS102XA_DEVDIS_H_
+
+#include <fsl_devdis.h>
+
+const struct devdis_table devdis_tbl[] = {
+	{ "pbl", 0x0, 0x80000000 },	/* PBL	*/
+	{ "esdhc", 0x0, 0x20000000 },	/* eSDHC	*/
+	{ "qdma", 0x0, 0x800000 },	/* qDMA		*/
+	{ "edma", 0x0, 0x400000 },	/* eDMA		*/
+	{ "usb3", 0x0, 0x84000 },	/* USB3.0 controller and PHY*/
+	{ "usb2", 0x0, 0x40000 },	/* USB2.0 controller	*/
+	{ "sata", 0x0, 0x8000 },	/* SATA		*/
+	{ "sec", 0x0, 0x200 },		/* SEC		*/
+	{ "dcu", 0x0, 0x2 },		/* Display controller Unit	*/
+	{ "qe", 0x0, 0x1 },		/* QUICC Engine	*/
+	{ "etsec1", 0x1, 0x80000000 },	/* eTSEC1 controller	*/
+	{ "etesc2", 0x1, 0x40000000 },	/* eTSEC2 controller	*/
+	{ "etsec3", 0x1, 0x20000000 },	/* eTSEC3 controller	*/
+	{ "pex1", 0x2, 0x80000000 },	/* PCIE controller 1	*/
+	{ "pex2", 0x2, 0x40000000 },	/* PCIE controller 2	*/
+	{ "duart1", 0x3, 0x20000000 },	/* DUART1	*/
+	{ "duart2", 0x3, 0x10000000 },	/* DUART2	*/
+	{ "qspi", 0x3, 0x8000000 },	/* QSPI		*/
+	{ "ddr", 0x4, 0x80000000 },	/* DDR		*/
+	{ "ocram1", 0x4, 0x8000000 },	/* OCRAM1	*/
+	{ "ifc", 0x4, 0x800000 },	/* IFC		*/
+	{ "gpio", 0x4, 0x400000 },	/* GPIO		*/
+	{ "dbg", 0x4, 0x200000 },	/* DBG		*/
+	{ "can1", 0x4, 0x80000 },	/* FlexCAN1	*/
+	{ "can2_4", 0x4, 0x40000 },	/* FlexCAN2_3_4	*/
+	{ "ftm2_8", 0x4, 0x20000 },	/* FlexTimer2_3_4_5_6_7_8	*/
+	{ "secmon", 0x4, 0x4000 },	/* Security Monitor	*/
+	{ "wdog1_2", 0x4, 0x400 },	/* WatchDog1_2	*/
+	{ "i2c2_3", 0x4, 0x200 },	/* I2C2_3	*/
+	{ "sai1_4", 0x4, 0x100 },	/* SAI1_2_3_4	*/
+	{ "lpuart2_6", 0x4, 0x80 },	/* LPUART2_3_4_5_6	*/
+	{ "dspi1_2", 0x4, 0x40 },	/* DSPI1_2	*/
+	{ "asrc", 0x4, 0x20 },		/* ASRC		*/
+	{ "spdif", 0x4, 0x10 },		/* SPDIF	*/
+	{ "i2c1", 0x4, 0x4 },		/* I2C1		*/
+	{ "lpuart1", 0x4, 0x2 },	/* LPUART1	*/
+	{ "ftm1", 0x4, 0x1 },		/* FlexTimer1	*/
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
new file mode 100644
index 0000000..1fde8bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_LS102XA_SOC_H
+#define __FSL_LS102XA_SOC_H
+
+unsigned int get_soc_major_rev(void);
+int arch_soc_init(void);
+int ls102xa_smmu_stream_id_init(void);
+
+void erratum_a008850_post(void);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+void erratum_a010315(void);
+#endif
+
+#endif /* __FSL_LS102XA_SOC_H */
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
new file mode 100644
index 0000000..93b0a26
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_LS102XA_STREAM_ID_H_
+#define __FSL_LS102XA_STREAM_ID_H_
+
+#include <fsl_sec.h>
+
+#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
+	{ .compat = name, \
+	  .id = { idA }, .num_ids = 1, \
+	  .reg_offset = off + CONFIG_SYS_IMMR, \
+	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	}
+
+#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
+	{ .compat = name, \
+	  .id = { idA, idB }, .num_ids = 2, \
+	  .reg_offset = off + CONFIG_SYS_IMMR, \
+	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	}
+
+/*
+ * handle both old and new versioned SEC properties:
+ * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
+ */
+#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
+	SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
+		offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
+	SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
+		offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
+
+/* This is a bit evil since we treat rtic param as both a string & hex value */
+#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
+	SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
+		liodnA,	\
+		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+	SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
+		liodnA,	\
+		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+
+#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
+	SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
+		offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, 0)
+
+struct liodn_id_table {
+	const char *compat;
+	u32 id[2];
+	u8 num_ids;
+	phys_addr_t compat_offset;
+	unsigned long reg_offset;
+};
+
+struct smmu_stream_id {
+	uint16_t offset;
+	uint16_t stream_id;
+	char dev_name[32];
+};
+
+void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size);
+void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h
new file mode 100644
index 0000000..b6daf32
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+
+enum csu_cslx_ind {
+	CSU_CSLX_PCIE2_IO = 0,
+	CSU_CSLX_PCIE1_IO,
+	CSU_CSLX_MG2TPR_IP,
+	CSU_CSLX_IFC_MEM,
+	CSU_CSLX_OCRAM,
+	CSU_CSLX_GIC,
+	CSU_CSLX_PCIE1,
+	CSU_CSLX_OCRAM2,
+	CSU_CSLX_QSPI_MEM,
+	CSU_CSLX_PCIE2,
+	CSU_CSLX_SATA,
+	CSU_CSLX_USB3,
+	CSU_CSLX_SERDES = 32,
+	CSU_CSLX_QDMA,
+	CSU_CSLX_LPUART2,
+	CSU_CSLX_LPUART1,
+	CSU_CSLX_LPUART4,
+	CSU_CSLX_LPUART3,
+	CSU_CSLX_LPUART6,
+	CSU_CSLX_LPUART5,
+	CSU_CSLX_DSPI2 = 40,
+	CSU_CSLX_DSPI1,
+	CSU_CSLX_QSPI,
+	CSU_CSLX_ESDHC,
+	CSU_CSLX_2D_ACE,
+	CSU_CSLX_IFC,
+	CSU_CSLX_I2C1,
+	CSU_CSLX_USB2,
+	CSU_CSLX_I2C3,
+	CSU_CSLX_I2C2,
+	CSU_CSLX_DUART2 = 50,
+	CSU_CSLX_DUART1,
+	CSU_CSLX_WDT2,
+	CSU_CSLX_WDT1,
+	CSU_CSLX_EDMA,
+	CSU_CSLX_SYS_CNT,
+	CSU_CSLX_DMA_MUX2,
+	CSU_CSLX_DMA_MUX1,
+	CSU_CSLX_DDR,
+	CSU_CSLX_QUICC,
+	CSU_CSLX_DCFG_CCU_RCPM = 60,
+	CSU_CSLX_SECURE_BOOTROM,
+	CSU_CSLX_SFP,
+	CSU_CSLX_TMU,
+	CSU_CSLX_SECURE_MONITOR,
+	CSU_CSLX_RESERVED0,
+	CSU_CSLX_ETSEC1,
+	CSU_CSLX_SEC5_5,
+	CSU_CSLX_ETSEC3,
+	CSU_CSLX_ETSEC2,
+	CSU_CSLX_GPIO2 = 70,
+	CSU_CSLX_GPIO1,
+	CSU_CSLX_GPIO4,
+	CSU_CSLX_GPIO3,
+	CSU_CSLX_PLATFORM_CONT,
+	CSU_CSLX_CSU,
+	CSU_CSLX_ASRC,
+	CSU_CSLX_SPDIF,
+	CSU_CSLX_FLEXCAN2,
+	CSU_CSLX_FLEXCAN1,
+	CSU_CSLX_FLEXCAN4 = 80,
+	CSU_CSLX_FLEXCAN3,
+	CSU_CSLX_SAI2,
+	CSU_CSLX_SAI1,
+	CSU_CSLX_SAI4,
+	CSU_CSLX_SAI3,
+	CSU_CSLX_FTM2,
+	CSU_CSLX_FTM1,
+	CSU_CSLX_FTM4,
+	CSU_CSLX_FTM3,
+	CSU_CSLX_FTM6 = 90,
+	CSU_CSLX_FTM5,
+	CSU_CSLX_FTM8,
+	CSU_CSLX_FTM7,
+	CSU_CSLX_EPU,
+	CSU_CSLX_COP_DCSR,
+	CSU_CSLX_DDI,
+	CSU_CSLX_GDI,
+	CSU_CSLX_RESERVED1,
+	CSU_CSLX_USB3_PHY = 116,
+	CSU_CSLX_RESERVED2,
+	CSU_CSLX_MAX,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/soc.h b/arch/arm/include/asm/arch-ls102xa/soc.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/soc.h
diff --git a/arch/arm/include/asm/arch-ls102xa/spl.h b/arch/arm/include/asm/arch-ls102xa/spl.h
new file mode 100644
index 0000000..990c74d
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/spl.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_SPL_H__
+#define __ASM_ARCH_SPL_H__
+
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONENAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+#define BOOT_DEVICE_MMC2_2	7
+#define BOOT_DEVICE_SPI		10
+
+#endif	/* __ASM_ARCH_SPL_H__ */
diff --git a/arch/arm/include/asm/arch-mediatek/gpio.h b/arch/arm/include/asm/arch-mediatek/gpio.h
new file mode 100644
index 0000000..4ea1020
--- /dev/null
+++ b/arch/arm/include/asm/arch-mediatek/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_GPIO_H
+#define __MEDIATEK_GPIO_H
+
+#endif	/* __MEDIATEK_GPIO_H */
diff --git a/arch/arm/include/asm/arch-mediatek/misc.h b/arch/arm/include/asm/arch-mediatek/misc.h
new file mode 100644
index 0000000..2530e78
--- /dev/null
+++ b/arch/arm/include/asm/arch-mediatek/misc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_MISC_H_
+#define __MEDIATEK_MISC_H_
+
+#define VER_BASE		0x08000000
+#define VER_SIZE		0x10
+
+#define APHW_CODE		0x00
+#define APHW_SUBCODE		0x04
+#define APHW_VER		0x08
+#define APSW_VER		0x0c
+
+#endif /* __MEDIATEK_MISC_H_ */
diff --git a/arch/arm/include/asm/arch-mediatek/reset.h b/arch/arm/include/asm/arch-mediatek/reset.h
new file mode 100644
index 0000000..9704666
--- /dev/null
+++ b/arch/arm/include/asm/arch-mediatek/reset.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_RESET_H
+#define __MEDIATEK_RESET_H
+
+#include <dm.h>
+
+int mediatek_reset_bind(struct udevice *pdev, u32 regofs, u32 num_regs);
+
+#endif	/* __MEDIATEK_RESET_H */
diff --git a/arch/arm/include/asm/arch-meson/axg.h b/arch/arm/include/asm/arch-meson/axg.h
new file mode 100644
index 0000000..d293f2a
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/axg.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __AXG_H__
+#define __AXG_H__
+
+#define AXG_AOBUS_BASE		0xff800000
+#define AXG_PERIPHS_BASE	0xff634400
+#define AXG_HIU_BASE		0xff63c000
+#define AXG_ETH_BASE		0xff3f0000
+
+/* Always-On Peripherals registers */
+#define AXG_AO_ADDR(off)	(AXG_AOBUS_BASE + ((off) << 2))
+
+#define AXG_AO_SEC_GP_CFG0	AXG_AO_ADDR(0x90)
+#define AXG_AO_SEC_GP_CFG3	AXG_AO_ADDR(0x93)
+#define AXG_AO_SEC_GP_CFG4	AXG_AO_ADDR(0x94)
+#define AXG_AO_SEC_GP_CFG5	AXG_AO_ADDR(0x95)
+
+#define AXG_AO_BOOT_DEVICE	0xF
+#define AXG_AO_MEM_SIZE_MASK	0xFFFF0000
+#define AXG_AO_MEM_SIZE_SHIFT	16
+#define AXG_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
+#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT	16
+#define AXG_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
+
+/* Peripherals registers */
+#define AXG_PERIPHS_ADDR(off)	(AXG_PERIPHS_BASE + ((off) << 2))
+
+#define AXG_ETH_REG_0		AXG_PERIPHS_ADDR(0x50)
+#define AXG_ETH_REG_1		AXG_PERIPHS_ADDR(0x51)
+
+#define AXG_ETH_REG_0_PHY_INTF_RGMII	BIT(0)
+#define AXG_ETH_REG_0_PHY_INTF_RMII	BIT(2)
+#define AXG_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
+#define AXG_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
+#define AXG_ETH_REG_0_PHY_CLK_EN	BIT(10)
+#define AXG_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
+#define AXG_ETH_REG_0_CLK_EN		BIT(12)
+
+/* HIU registers */
+#define AXG_HIU_ADDR(off)	(AXG_HIU_BASE + ((off) << 2))
+
+#define AXG_MEM_PD_REG_0	AXG_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define AXG_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
+
+#endif /* __AXG_H__ */
diff --git a/arch/arm/include/asm/arch-meson/boot.h b/arch/arm/include/asm/arch-meson/boot.h
new file mode 100644
index 0000000..a90fe55
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/boot.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __MESON_BOOT_H__
+#define __MESON_BOOT_H__
+
+/* Boot device */
+#define BOOT_DEVICE_RESERVED    0
+#define BOOT_DEVICE_EMMC        1
+#define BOOT_DEVICE_NAND        2
+#define BOOT_DEVICE_SPI         3
+#define BOOT_DEVICE_SD          4
+#define BOOT_DEVICE_USB         5
+
+int meson_get_boot_device(void);
+
+#endif /* __MESON_BOOT_H__ */
diff --git a/arch/arm/include/asm/arch-meson/clock-axg.h b/arch/arm/include/asm/arch-meson/clock-axg.h
new file mode 100644
index 0000000..1ef88e4
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/clock-axg.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - AmLogic, Inc.
+ * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
+ * Copyright 2018 - BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+#ifndef _ARCH_MESON_CLOCK_AXG_H_
+#define _ARCH_MESON_CLOCK_AXG_H_
+
+/*
+ * Clock controller register offsets
+ *
+ * Register offsets from the data sheet are listed in comment blocks below.
+ * Those offsets must be multiplied by 4 before adding them to the base address
+ * to get the right value
+ */
+#define HHI_GP0_PLL_CNTL		0x40
+#define HHI_GP0_PLL_CNTL2		0x44
+#define HHI_GP0_PLL_CNTL3		0x48
+#define HHI_GP0_PLL_CNTL4		0x4c
+#define HHI_GP0_PLL_CNTL5		0x50
+#define HHI_GP0_PLL_STS			0x54
+#define HHI_GP0_PLL_CNTL1		0x58
+#define HHI_HIFI_PLL_CNTL		0x80
+#define HHI_HIFI_PLL_CNTL2		0x84
+#define HHI_HIFI_PLL_CNTL3		0x88
+#define HHI_HIFI_PLL_CNTL4		0x8C
+#define HHI_HIFI_PLL_CNTL5		0x90
+#define HHI_HIFI_PLL_STS		0x94
+#define HHI_HIFI_PLL_CNTL1		0x98
+
+#define HHI_XTAL_DIVN_CNTL		0xbc
+#define HHI_GCLK2_MPEG0			0xc0
+#define HHI_GCLK2_MPEG1			0xc4
+#define HHI_GCLK2_MPEG2			0xc8
+#define HHI_GCLK2_OTHER			0xd0
+#define HHI_GCLK2_AO			0xd4
+#define HHI_PCIE_PLL_CNTL		0xd8
+#define HHI_PCIE_PLL_CNTL1		0xdC
+#define HHI_PCIE_PLL_CNTL2		0xe0
+#define HHI_PCIE_PLL_CNTL3		0xe4
+#define HHI_PCIE_PLL_CNTL4		0xe8
+#define HHI_PCIE_PLL_CNTL5		0xec
+#define HHI_PCIE_PLL_CNTL6		0xf0
+#define HHI_PCIE_PLL_STS		0xf4
+
+#define HHI_MEM_PD_REG0			0x100
+#define HHI_VPU_MEM_PD_REG0		0x104
+#define HHI_VIID_CLK_DIV		0x128
+#define HHI_VIID_CLK_CNTL		0x12c
+
+#define HHI_GCLK_MPEG0			0x140
+#define HHI_GCLK_MPEG1			0x144
+#define HHI_GCLK_MPEG2			0x148
+#define HHI_GCLK_OTHER			0x150
+#define HHI_GCLK_AO			0x154
+#define HHI_SYS_CPU_CLK_CNTL1		0x15c
+#define HHI_SYS_CPU_RESET_CNTL		0x160
+#define HHI_VID_CLK_DIV			0x164
+#define HHI_SPICC_HCLK_CNTL		0x168
+
+#define HHI_MPEG_CLK_CNTL		0x174
+#define HHI_VID_CLK_CNTL		0x17c
+#define HHI_TS_CLK_CNTL			0x190
+#define HHI_VID_CLK_CNTL2		0x194
+#define HHI_SYS_CPU_CLK_CNTL0		0x19c
+#define HHI_VID_PLL_CLK_DIV		0x1a0
+#define HHI_VPU_CLK_CNTL		0x1bC
+
+#define HHI_VAPBCLK_CNTL		0x1F4
+
+#define HHI_GEN_CLK_CNTL		0x228
+
+#define HHI_VDIN_MEAS_CLK_CNTL		0x250
+#define HHI_NAND_CLK_CNTL		0x25C
+#define HHI_SD_EMMC_CLK_CNTL		0x264
+
+#define HHI_MPLL_CNTL			0x280
+#define HHI_MPLL_CNTL2			0x284
+#define HHI_MPLL_CNTL3			0x288
+#define HHI_MPLL_CNTL4			0x28C
+#define HHI_MPLL_CNTL5			0x290
+#define HHI_MPLL_CNTL6			0x294
+#define HHI_MPLL_CNTL7			0x298
+#define HHI_MPLL_CNTL8			0x29C
+#define HHI_MPLL_CNTL9			0x2A0
+#define HHI_MPLL_CNTL10			0x2A4
+
+#define HHI_MPLL3_CNTL0			0x2E0
+#define HHI_MPLL3_CNTL1			0x2E4
+#define HHI_PLL_TOP_MISC		0x2E8
+
+#define HHI_SYS_PLL_CNTL1		0x2FC
+#define HHI_SYS_PLL_CNTL		0x300
+#define HHI_SYS_PLL_CNTL2		0x304
+#define HHI_SYS_PLL_CNTL3		0x308
+#define HHI_SYS_PLL_CNTL4		0x30c
+#define HHI_SYS_PLL_CNTL5		0x310
+#define HHI_SYS_PLL_STS			0x314
+#define HHI_DPLL_TOP_I			0x318
+#define HHI_DPLL_TOP2_I			0x31C
+
+#endif
diff --git a/arch/arm/include/asm/arch-meson/clock-g12a.h b/arch/arm/include/asm/arch-meson/clock-g12a.h
new file mode 100644
index 0000000..d52e27e
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/clock-g12a.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - AmLogic, Inc.
+ * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
+ * Copyright 2018 - BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+#ifndef _ARCH_MESON_CLOCK_G12A_H_
+#define _ARCH_MESON_CLOCK_G12A_H_
+
+/*
+ * Clock controller register offsets
+ *
+ * Register offsets from the data sheet are listed in comment blocks below.
+ * Those offsets must be multiplied by 4 before adding them to the base address
+ * to get the right value
+ */
+
+#define HHI_MIPI_CNTL0			0x000
+#define HHI_MIPI_CNTL1			0x004
+#define HHI_MIPI_CNTL2			0x008
+#define HHI_MIPI_STS			0x00C
+#define HHI_GP0_PLL_CNTL0		0x040
+#define HHI_GP0_PLL_CNTL1		0x044
+#define HHI_GP0_PLL_CNTL2		0x048
+#define HHI_GP0_PLL_CNTL3		0x04C
+#define HHI_GP0_PLL_CNTL4		0x050
+#define HHI_GP0_PLL_CNTL5		0x054
+#define HHI_GP0_PLL_CNTL6		0x058
+#define HHI_GP0_PLL_STS			0x05C
+#define HHI_PCIE_PLL_CNTL0		0x098
+#define HHI_PCIE_PLL_CNTL1		0x09C
+#define HHI_PCIE_PLL_CNTL2		0x0A0
+#define HHI_PCIE_PLL_CNTL3		0x0A4
+#define HHI_PCIE_PLL_CNTL4		0x0A8
+#define HHI_PCIE_PLL_CNTL5		0x0AC
+#define HHI_PCIE_PLL_STS		0x0B8
+#define HHI_HIFI_PLL_CNTL0		0x0D8
+#define HHI_HIFI_PLL_CNTL1		0x0DC
+#define HHI_HIFI_PLL_CNTL2		0x0E0
+#define HHI_HIFI_PLL_CNTL3		0x0E4
+#define HHI_HIFI_PLL_CNTL4		0x0E8
+#define HHI_HIFI_PLL_CNTL5		0x0EC
+#define HHI_HIFI_PLL_CNTL6		0x0F0
+#define HHI_VIID_CLK_DIV		0x128
+#define HHI_VIID_CLK_CNTL		0x12C
+#define HHI_GCLK_MPEG0			0x140
+#define HHI_GCLK_MPEG1			0x144
+#define HHI_GCLK_MPEG2			0x148
+#define HHI_GCLK_OTHER			0x150
+#define HHI_GCLK_OTHER2			0x154
+#define HHI_VID_CLK_DIV			0x164
+#define HHI_MPEG_CLK_CNTL		0x174
+#define HHI_AUD_CLK_CNTL		0x178
+#define HHI_VID_CLK_CNTL		0x17c
+#define HHI_TS_CLK_CNTL			0x190
+#define HHI_VID_CLK_CNTL2		0x194
+#define HHI_SYS_CPU_CLK_CNTL0		0x19c
+#define HHI_VID_PLL_CLK_DIV		0x1A0
+#define HHI_MALI_CLK_CNTL		0x1b0
+#define HHI_VPU_CLKC_CNTL		0x1b4
+#define HHI_VPU_CLK_CNTL		0x1bC
+#define HHI_HDMI_CLK_CNTL		0x1CC
+#define HHI_VDEC_CLK_CNTL		0x1E0
+#define HHI_VDEC2_CLK_CNTL		0x1E4
+#define HHI_VDEC3_CLK_CNTL		0x1E8
+#define HHI_VDEC4_CLK_CNTL		0x1EC
+#define HHI_HDCP22_CLK_CNTL		0x1F0
+#define HHI_VAPBCLK_CNTL		0x1F4
+#define HHI_VPU_CLKB_CNTL		0x20C
+#define HHI_GEN_CLK_CNTL		0x228
+#define HHI_VDIN_MEAS_CLK_CNTL		0x250
+#define HHI_MIPIDSI_PHY_CLK_CNTL	0x254
+#define HHI_NAND_CLK_CNTL		0x25C
+#define HHI_SD_EMMC_CLK_CNTL		0x264
+#define HHI_MPLL_CNTL0			0x278
+#define HHI_MPLL_CNTL1			0x27C
+#define HHI_MPLL_CNTL2			0x280
+#define HHI_MPLL_CNTL3			0x284
+#define HHI_MPLL_CNTL4			0x288
+#define HHI_MPLL_CNTL5			0x28c
+#define HHI_MPLL_CNTL6			0x290
+#define HHI_MPLL_CNTL7			0x294
+#define HHI_MPLL_CNTL8			0x298
+#define HHI_FIX_PLL_CNTL0		0x2A0
+#define HHI_FIX_PLL_CNTL1		0x2A4
+#define HHI_FIX_PLL_CNTL3		0x2AC
+#define HHI_SYS_PLL_CNTL0		0x2f4
+#define HHI_SYS_PLL_CNTL1		0x2f8
+#define HHI_SYS_PLL_CNTL2		0x2fc
+#define HHI_SYS_PLL_CNTL3		0x300
+#define HHI_SYS_PLL_CNTL4		0x304
+#define HHI_SYS_PLL_CNTL5		0x308
+#define HHI_SYS_PLL_CNTL6		0x30c
+#define HHI_HDMI_PLL_CNTL0		0x320
+#define HHI_HDMI_PLL_CNTL1		0x324
+#define HHI_HDMI_PLL_CNTL2		0x328
+#define HHI_HDMI_PLL_CNTL3		0x32c
+#define HHI_HDMI_PLL_CNTL4		0x330
+#define HHI_HDMI_PLL_CNTL5		0x334
+#define HHI_HDMI_PLL_CNTL6		0x338
+#define HHI_SPICC_CLK_CNTL		0x3dc
+
+#endif
diff --git a/arch/arm/include/asm/arch-meson/clock-gx.h b/arch/arm/include/asm/arch-meson/clock-gx.h
new file mode 100644
index 0000000..13a2e76
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/clock-gx.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - AmLogic, Inc.
+ * Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
+ */
+#ifndef _ARCH_MESON_CLOCK_GX_H_
+#define _ARCH_MESON_CLOCK_GX_H_
+
+/*
+ * Clock controller register offsets
+ *
+ * Register offsets from the data sheet are listed in comment blocks below.
+ * Those offsets must be multiplied by 4 before adding them to the base address
+ * to get the right value
+ */
+#define SCR				0x2C /* 0x0b offset in data sheet */
+#define TIMEOUT_VALUE			0x3c /* 0x0f offset in data sheet */
+
+#define HHI_GP0_PLL_CNTL		0x40 /* 0x10 offset in data sheet */
+#define HHI_GP0_PLL_CNTL2		0x44 /* 0x11 offset in data sheet */
+#define HHI_GP0_PLL_CNTL3		0x48 /* 0x12 offset in data sheet */
+#define HHI_GP0_PLL_CNTL4		0x4c /* 0x13 offset in data sheet */
+#define	HHI_GP0_PLL_CNTL5		0x50 /* 0x14 offset in data sheet */
+#define	HHI_GP0_PLL_CNTL1		0x58 /* 0x16 offset in data sheet */
+
+#define	HHI_XTAL_DIVN_CNTL		0xbc /* 0x2f offset in data sheet */
+#define	HHI_TIMER90K			0xec /* 0x3b offset in data sheet */
+
+#define	HHI_MEM_PD_REG0			0x100 /* 0x40 offset in data sheet */
+#define	HHI_MEM_PD_REG1			0x104 /* 0x41 offset in data sheet */
+#define	HHI_VPU_MEM_PD_REG1		0x108 /* 0x42 offset in data sheet */
+#define	HHI_VIID_CLK_DIV		0x128 /* 0x4a offset in data sheet */
+#define	HHI_VIID_CLK_CNTL		0x12c /* 0x4b offset in data sheet */
+
+#define HHI_GCLK_MPEG0			0x140 /* 0x50 offset in data sheet */
+#define HHI_GCLK_MPEG1			0x144 /* 0x51 offset in data sheet */
+#define HHI_GCLK_MPEG2			0x148 /* 0x52 offset in data sheet */
+#define HHI_GCLK_OTHER			0x150 /* 0x54 offset in data sheet */
+#define HHI_GCLK_AO			0x154 /* 0x55 offset in data sheet */
+#define HHI_SYS_OSCIN_CNTL		0x158 /* 0x56 offset in data sheet */
+#define HHI_SYS_CPU_CLK_CNTL1		0x15c /* 0x57 offset in data sheet */
+#define HHI_SYS_CPU_RESET_CNTL		0x160 /* 0x58 offset in data sheet */
+#define HHI_VID_CLK_DIV			0x164 /* 0x59 offset in data sheet */
+
+#define HHI_MPEG_CLK_CNTL		0x174 /* 0x5d offset in data sheet */
+#define HHI_AUD_CLK_CNTL		0x178 /* 0x5e offset in data sheet */
+#define HHI_VID_CLK_CNTL		0x17c /* 0x5f offset in data sheet */
+#define HHI_AUD_CLK_CNTL2		0x190 /* 0x64 offset in data sheet */
+#define HHI_VID_CLK_CNTL2		0x194 /* 0x65 offset in data sheet */
+#define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
+#define HHI_VID_PLL_CLK_DIV		0x1a0 /* 0x68 offset in data sheet */
+#define HHI_AUD_CLK_CNTL3		0x1a4 /* 0x69 offset in data sheet */
+#define HHI_MALI_CLK_CNTL		0x1b0 /* 0x6c offset in data sheet */
+#define HHI_VPU_CLK_CNTL		0x1bC /* 0x6f offset in data sheet */
+
+#define HHI_HDMI_CLK_CNTL		0x1CC /* 0x73 offset in data sheet */
+#define HHI_VDEC_CLK_CNTL		0x1E0 /* 0x78 offset in data sheet */
+#define HHI_VDEC2_CLK_CNTL		0x1E4 /* 0x79 offset in data sheet */
+#define HHI_VDEC3_CLK_CNTL		0x1E8 /* 0x7a offset in data sheet */
+#define HHI_VDEC4_CLK_CNTL		0x1EC /* 0x7b offset in data sheet */
+#define HHI_HDCP22_CLK_CNTL		0x1F0 /* 0x7c offset in data sheet */
+#define HHI_VAPBCLK_CNTL		0x1F4 /* 0x7d offset in data sheet */
+
+#define HHI_VPU_CLKB_CNTL		0x20C /* 0x83 offset in data sheet */
+#define HHI_USB_CLK_CNTL		0x220 /* 0x88 offset in data sheet */
+#define HHI_32K_CLK_CNTL		0x224 /* 0x89 offset in data sheet */
+#define HHI_GEN_CLK_CNTL		0x228 /* 0x8a offset in data sheet */
+#define HHI_GEN_CLK_CNTL		0x228 /* 0x8a offset in data sheet */
+
+#define HHI_PCM_CLK_CNTL		0x258 /* 0x96 offset in data sheet */
+#define HHI_NAND_CLK_CNTL		0x25C /* 0x97 offset in data sheet */
+#define HHI_SD_EMMC_CLK_CNTL		0x264 /* 0x99 offset in data sheet */
+
+#define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
+#define HHI_MPLL_CNTL2			0x284 /* 0xa1 offset in data sheet */
+#define HHI_MPLL_CNTL3			0x288 /* 0xa2 offset in data sheet */
+#define HHI_MPLL_CNTL4			0x28C /* 0xa3 offset in data sheet */
+#define HHI_MPLL_CNTL5			0x290 /* 0xa4 offset in data sheet */
+#define HHI_MPLL_CNTL6			0x294 /* 0xa5 offset in data sheet */
+#define HHI_MPLL_CNTL7			0x298 /* 0xa6 offset in data sheet */
+#define HHI_MPLL_CNTL8			0x29C /* 0xa7 offset in data sheet */
+#define HHI_MPLL_CNTL9			0x2A0 /* 0xa8 offset in data sheet */
+#define HHI_MPLL_CNTL10			0x2A4 /* 0xa9 offset in data sheet */
+
+#define HHI_MPLL3_CNTL0			0x2E0 /* 0xb8 offset in data sheet */
+#define HHI_MPLL3_CNTL1			0x2E4 /* 0xb9 offset in data sheet */
+#define HHI_VDAC_CNTL0			0x2F4 /* 0xbd offset in data sheet */
+#define HHI_VDAC_CNTL1			0x2F8 /* 0xbe offset in data sheet */
+
+#define HHI_SYS_PLL_CNTL		0x300 /* 0xc0 offset in data sheet */
+#define HHI_SYS_PLL_CNTL2		0x304 /* 0xc1 offset in data sheet */
+#define HHI_SYS_PLL_CNTL3		0x308 /* 0xc2 offset in data sheet */
+#define HHI_SYS_PLL_CNTL4		0x30c /* 0xc3 offset in data sheet */
+#define HHI_SYS_PLL_CNTL5		0x310 /* 0xc4 offset in data sheet */
+#define HHI_DPLL_TOP_I			0x318 /* 0xc6 offset in data sheet */
+#define HHI_DPLL_TOP2_I			0x31C /* 0xc7 offset in data sheet */
+#define HHI_HDMI_PLL_CNTL		0x320 /* 0xc8 offset in data sheet */
+#define HHI_HDMI_PLL_CNTL2		0x324 /* 0xc9 offset in data sheet */
+#define HHI_HDMI_PLL_CNTL3		0x328 /* 0xca offset in data sheet */
+#define HHI_HDMI_PLL_CNTL4		0x32C /* 0xcb offset in data sheet */
+#define HHI_HDMI_PLL_CNTL5		0x330 /* 0xcc offset in data sheet */
+#define HHI_HDMI_PLL_CNTL6		0x334 /* 0xcd offset in data sheet */
+#define HHI_HDMI_PLL_CNTL_I		0x338 /* 0xce offset in data sheet */
+#define HHI_HDMI_PLL_CNTL7		0x33C /* 0xcf offset in data sheet */
+
+#define HHI_HDMI_PHY_CNTL0		0x3A0 /* 0xe8 offset in data sheet */
+#define HHI_HDMI_PHY_CNTL1		0x3A4 /* 0xe9 offset in data sheet */
+#define HHI_HDMI_PHY_CNTL2		0x3A8 /* 0xea offset in data sheet */
+#define HHI_HDMI_PHY_CNTL3		0x3AC /* 0xeb offset in data sheet */
+
+#define HHI_VID_LOCK_CLK_CNTL		0x3C8 /* 0xf2 offset in data sheet */
+#define HHI_BT656_CLK_CNTL		0x3D4 /* 0xf5 offset in data sheet */
+#define HHI_SAR_CLK_CNTL		0x3D8 /* 0xf6 offset in data sheet */
+
+ulong meson_measure_clk_rate(unsigned int clk);
+
+#endif
diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h
new file mode 100644
index 0000000..f765cd7
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/eth.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __MESON_ETH_H__
+#define __MESON_ETH_H__
+
+#include <phy.h>
+
+enum {
+	/* Use Internal RMII PHY */
+	MESON_USE_INTERNAL_RMII_PHY = 1,
+};
+
+/* Configure the Ethernet MAC with the requested interface mode
+ * with some optional flags.
+ */
+void meson_eth_init(phy_interface_t mode, unsigned int flags);
+
+/* Generate an unique MAC address based on the HW serial */
+int meson_generate_serial_ethaddr(void);
+
+#endif /* __MESON_ETH_H__ */
diff --git a/arch/arm/include/asm/arch-meson/g12a.h b/arch/arm/include/asm/arch-meson/g12a.h
new file mode 100644
index 0000000..b806667
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/g12a.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __G12A_H__
+#define __G12A_H__
+
+#define G12A_AOBUS_BASE			0xff800000
+#define G12A_PERIPHS_BASE		0xff634400
+#define G12A_HIU_BASE			0xff63c000
+#define G12A_ETH_PHY_BASE		0xff64c000
+#define G12A_ETH_BASE			0xff3f0000
+
+/* Always-On Peripherals registers */
+#define G12A_AO_ADDR(off)	(G12A_AOBUS_BASE + ((off) << 2))
+
+#define G12A_AO_SEC_GP_CFG0		G12A_AO_ADDR(0x90)
+#define G12A_AO_SEC_GP_CFG3		G12A_AO_ADDR(0x93)
+#define G12A_AO_SEC_GP_CFG4		G12A_AO_ADDR(0x94)
+#define G12A_AO_SEC_GP_CFG5		G12A_AO_ADDR(0x95)
+
+#define G12A_AO_BOOT_DEVICE		0xF
+#define G12A_AO_MEM_SIZE_MASK		0xFFFF0000
+#define G12A_AO_MEM_SIZE_SHIFT		16
+#define G12A_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
+#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT	16
+#define G12A_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
+
+/* Peripherals registers */
+#define G12A_PERIPHS_ADDR(off)	(G12A_PERIPHS_BASE + ((off) << 2))
+
+#define G12A_ETH_REG_0			G12A_PERIPHS_ADDR(0x50)
+#define G12A_ETH_REG_1			G12A_PERIPHS_ADDR(0x51)
+
+#define G12A_ETH_REG_0_PHY_INTF_RGMII	BIT(0)
+#define G12A_ETH_REG_0_PHY_INTF_RMII	BIT(2)
+#define G12A_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
+#define G12A_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
+#define G12A_ETH_REG_0_PHY_CLK_EN	BIT(10)
+#define G12A_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
+#define G12A_ETH_REG_0_CLK_EN		BIT(12)
+
+#define G12A_ETH_PHY_ADDR(off)	(G12A_ETH_PHY_BASE + ((off) << 2))
+#define ETH_PLL_CNTL0			G12A_ETH_PHY_ADDR(0x11)
+#define ETH_PLL_CNTL1			G12A_ETH_PHY_ADDR(0x12)
+#define ETH_PLL_CNTL2			G12A_ETH_PHY_ADDR(0x13)
+#define ETH_PLL_CNTL3			G12A_ETH_PHY_ADDR(0x14)
+#define ETH_PLL_CNTL4			G12A_ETH_PHY_ADDR(0x15)
+#define ETH_PLL_CNTL5			G12A_ETH_PHY_ADDR(0x16)
+#define ETH_PLL_CNTL6			G12A_ETH_PHY_ADDR(0x17)
+#define ETH_PLL_CNTL7			G12A_ETH_PHY_ADDR(0x18)
+#define ETH_PHY_CNTL0			G12A_ETH_PHY_ADDR(0x20)
+#define ETH_PHY_CNTL1			G12A_ETH_PHY_ADDR(0x21)
+#define ETH_PHY_CNTL2			G12A_ETH_PHY_ADDR(0x22)
+
+/* HIU registers */
+#define G12A_HIU_ADDR(off)	(G12A_HIU_BASE + ((off) << 2))
+
+#define G12A_MEM_PD_REG_0		G12A_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define G12A_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
+
+#endif /* __G12A_H__ */
diff --git a/arch/arm/include/asm/arch-meson/gpio.h b/arch/arm/include/asm/arch-meson/gpio.h
new file mode 100644
index 0000000..d0142f1
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#ifndef __ASM_ARCH_MESON_GPIO_H
+#define __ASM_ARCH_MESON_GPIO_H
+
+
+#endif	/* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-meson/gx.h b/arch/arm/include/asm/arch-meson/gx.h
new file mode 100644
index 0000000..b781ba9
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/gx.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#ifndef __GX_H__
+#define __GX_H__
+
+#define GX_FIRMWARE_MEM_SIZE	0x1000000
+
+#define GX_AOBUS_BASE		0xc8100000
+#define GX_PERIPHS_BASE	0xc8834400
+#define GX_HIU_BASE		0xc883c000
+#define GX_ETH_BASE		0xc9410000
+
+/* Always-On Peripherals registers */
+#define GX_AO_ADDR(off)	(GX_AOBUS_BASE + ((off) << 2))
+
+#define GX_AO_SEC_GP_CFG0	GX_AO_ADDR(0x90)
+#define GX_AO_SEC_GP_CFG3	GX_AO_ADDR(0x93)
+#define GX_AO_SEC_GP_CFG4	GX_AO_ADDR(0x94)
+#define GX_AO_SEC_GP_CFG5	GX_AO_ADDR(0x95)
+
+#define GX_AO_BOOT_DEVICE	0xF
+#define GX_AO_MEM_SIZE_MASK	0xFFFF0000
+#define GX_AO_MEM_SIZE_SHIFT	16
+#define GX_AO_BL31_RSVMEM_SIZE_MASK	0xFFFF0000
+#define GX_AO_BL31_RSVMEM_SIZE_SHIFT	16
+#define GX_AO_BL32_RSVMEM_SIZE_MASK	0xFFFF
+
+/* Peripherals registers */
+#define GX_PERIPHS_ADDR(off)	(GX_PERIPHS_BASE + ((off) << 2))
+
+/* GPIO registers 0 to 6 */
+#define _GX_GPIO_OFF(n)	((n) == 6 ? 0x08 : 0x0c + 3 * (n))
+#define GX_GPIO_EN(n)		GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0)
+#define GX_GPIO_IN(n)		GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
+#define GX_GPIO_OUT(n)	GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
+
+#define GX_ETH_REG_0		GX_PERIPHS_ADDR(0x50)
+#define GX_ETH_REG_1		GX_PERIPHS_ADDR(0x51)
+#define GX_ETH_REG_2		GX_PERIPHS_ADDR(0x56)
+#define GX_ETH_REG_3		GX_PERIPHS_ADDR(0x57)
+
+#define GX_ETH_REG_0_PHY_INTF		BIT(0)
+#define GX_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
+#define GX_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
+#define GX_ETH_REG_0_PHY_CLK_EN	BIT(10)
+#define GX_ETH_REG_0_INVERT_RMII_CLK	BIT(11)
+#define GX_ETH_REG_0_CLK_EN		BIT(12)
+
+/* HIU registers */
+#define GX_HIU_ADDR(off)	(GX_HIU_BASE + ((off) << 2))
+
+#define GX_MEM_PD_REG_0	GX_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define GX_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
+
+#endif /* __GX_H__ */
diff --git a/arch/arm/include/asm/arch-meson/i2c.h b/arch/arm/include/asm/arch-meson/i2c.h
new file mode 100644
index 0000000..aa474a0
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/i2c.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com>
+ */
+#ifndef _MESON_I2C_H_
+#define _MESON_I2C_H_
+
+#define MESON_I2C_CLK_RATE	167000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-meson/mem.h b/arch/arm/include/asm/arch-meson/mem.h
new file mode 100644
index 0000000..a65100a
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/mem.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __MESON_MEM_H__
+#define __MESON_MEM_H__
+
+/* Configure the reserved memory zones exported by the secure registers
+ * into EFI and DTB reserved memory entries.
+ */
+void meson_board_add_reserved_memory(void *fdt, u64 start, u64 size);
+void meson_init_reserved_memory(void *fdt);
+
+#endif /* __MESON_MEM_H__ */
diff --git a/arch/arm/include/asm/arch-meson/meson-vpu.h b/arch/arm/include/asm/arch-meson/meson-vpu.h
new file mode 100644
index 0000000..f31dfa6
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/meson-vpu.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Maxime Jourdan <mjourdan@baylibre.com>
+ */
+
+#ifndef __MESON_VPU_H__
+#define __MESON_VPU_H__
+
+/* Allow reserving the framebuffer memory region */
+void meson_vpu_rsv_fb(void *fdt);
+
+#endif /* __MESON_VPU_H__ */
diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h b/arch/arm/include/asm/arch-meson/sd_emmc.h
new file mode 100644
index 0000000..e3a72c8
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
+ */
+
+#ifndef __SD_EMMC_H__
+#define __SD_EMMC_H__
+
+#include <mmc.h>
+
+#define SDIO_PORT_A			0
+#define SDIO_PORT_B			1
+#define SDIO_PORT_C			2
+
+#define SD_EMMC_CLKSRC_24M		24000000	/* 24 MHz */
+#define SD_EMMC_CLKSRC_DIV2		1000000000	/* 1 GHz */
+
+#define MESON_SD_EMMC_CLOCK		0x00
+#define   CLK_MAX_DIV			63
+#define   CLK_SRC_24M			(0 << 6)
+#define   CLK_SRC_DIV2			(1 << 6)
+#define   CLK_CO_PHASE_000		(0 << 8)
+#define   CLK_CO_PHASE_090		(1 << 8)
+#define   CLK_CO_PHASE_180		(2 << 8)
+#define   CLK_CO_PHASE_270		(3 << 8)
+#define   CLK_TX_PHASE_000		(0 << 10)
+#define   CLK_TX_PHASE_090		(1 << 10)
+#define   CLK_TX_PHASE_180		(2 << 10)
+#define   CLK_TX_PHASE_270		(3 << 10)
+#define   CLK_ALWAYS_ON			BIT(24)
+
+#define MESON_SD_EMMC_CFG		0x44
+#define   CFG_BUS_WIDTH_MASK		GENMASK(1, 0)
+#define   CFG_BUS_WIDTH_1		0
+#define   CFG_BUS_WIDTH_4		1
+#define   CFG_BUS_WIDTH_8		2
+#define   CFG_BL_LEN_MASK		GENMASK(7, 4)
+#define   CFG_BL_LEN_SHIFT		4
+#define   CFG_BL_LEN_512		(9 << 4)
+#define   CFG_RESP_TIMEOUT_MASK		GENMASK(11, 8)
+#define   CFG_RESP_TIMEOUT_256		(8 << 8)
+#define   CFG_RC_CC_MASK		GENMASK(15, 12)
+#define   CFG_RC_CC_16			(4 << 12)
+#define   CFG_SDCLK_ALWAYS_ON		BIT(18)
+#define   CFG_AUTO_CLK			BIT(23)
+
+#define MESON_SD_EMMC_STATUS		0x48
+#define   STATUS_MASK			GENMASK(15, 0)
+#define   STATUS_ERR_MASK		GENMASK(12, 0)
+#define   STATUS_RXD_ERR_MASK		GENMASK(7, 0)
+#define   STATUS_TXD_ERR		BIT(8)
+#define   STATUS_DESC_ERR		BIT(9)
+#define   STATUS_RESP_ERR		BIT(10)
+#define   STATUS_RESP_TIMEOUT		BIT(11)
+#define   STATUS_DESC_TIMEOUT		BIT(12)
+#define   STATUS_END_OF_CHAIN		BIT(13)
+
+#define MESON_SD_EMMC_IRQ_EN		0x4c
+
+#define MESON_SD_EMMC_CMD_CFG		0x50
+#define   CMD_CFG_LENGTH_MASK		GENMASK(8, 0)
+#define   CMD_CFG_BLOCK_MODE		BIT(9)
+#define   CMD_CFG_R1B			BIT(10)
+#define   CMD_CFG_END_OF_CHAIN		BIT(11)
+#define   CMD_CFG_TIMEOUT_4S		(12 << 12)
+#define   CMD_CFG_NO_RESP		BIT(16)
+#define   CMD_CFG_DATA_IO		BIT(18)
+#define   CMD_CFG_DATA_WR		BIT(19)
+#define   CMD_CFG_RESP_NOCRC		BIT(20)
+#define   CMD_CFG_RESP_128		BIT(21)
+#define   CMD_CFG_CMD_INDEX_SHIFT	24
+#define   CMD_CFG_OWNER			BIT(31)
+
+#define MESON_SD_EMMC_CMD_ARG		0x54
+#define MESON_SD_EMMC_CMD_DAT		0x58
+#define MESON_SD_EMMC_CMD_RSP		0x5c
+#define MESON_SD_EMMC_CMD_RSP1		0x60
+#define MESON_SD_EMMC_CMD_RSP2		0x64
+#define MESON_SD_EMMC_CMD_RSP3		0x68
+
+struct meson_mmc_platdata {
+	struct mmc_config cfg;
+	struct mmc mmc;
+	void *regbase;
+	void *w_buf;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
new file mode 100644
index 0000000..f3ae46a
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#ifndef __MESON_SM_H__
+#define __MESON_SM_H__
+
+ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
+
+#define SM_SERIAL_SIZE	12
+
+int meson_sm_get_serial(void *buffer, size_t size);
+
+enum {
+	REBOOT_REASON_COLD = 0,
+	REBOOT_REASON_NORMAL = 1,
+	REBOOT_REASON_RECOVERY = 2,
+	REBOOT_REASON_UPDATE = 3,
+	REBOOT_REASON_FASTBOOT = 4,
+	REBOOT_REASON_SUSPEND_OFF = 5,
+	REBOOT_REASON_HIBERNATE = 6,
+	REBOOT_REASON_BOOTLOADER = 7,
+	REBOOT_REASON_SHUTDOWN_REBOOT = 8,
+	REBOOT_REASON_RPMBP = 9,
+	REBOOT_REASON_CRASH_DUMP = 11,
+	REBOOT_REASON_KERNEL_PANIC = 12,
+	REBOOT_REASON_WATCHDOG_REBOOT = 13,
+};
+
+int meson_sm_get_reboot_reason(void);
+
+#endif /* __MESON_SM_H__ */
diff --git a/arch/arm/include/asm/arch-meson/usb.h b/arch/arm/include/asm/arch-meson/usb.h
new file mode 100644
index 0000000..b794b5c
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/usb.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __MESON_USB_H__
+#define __MESON_USB_H__
+
+int dwc3_meson_g12a_force_mode(struct udevice *dev, enum usb_dr_mode mode);
+
+#endif /* __MESON_USB_H__ */
diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h
new file mode 100644
index 0000000..58b6c32
--- /dev/null
+++ b/arch/arm/include/asm/arch-mvebu/spi.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Derived from drivers/spi/mpc8xxx_spi.c
+ */
+
+#ifndef __KW_SPI_H__
+#define __KW_SPI_H__
+
+/* SPI Registers on kirkwood SOC */
+struct kwspi_registers {
+	u32 ctrl;	/* 0x10600 */
+	u32 cfg;	/* 0x10604 */
+	u32 dout;	/* 0x10608 */
+	u32 din;	/* 0x1060c */
+	u32 irq_cause;	/* 0x10610 */
+	u32 irq_mask;	/* 0x10614 */
+	u32 timing1;	/* 0x10618 */
+	u32 timing2;	/* 0x1061c */
+	u32 dw_cfg;	/* 0x10620 - Direct Write Configuration */
+};
+
+/* Control Register */
+#define KWSPI_CSN_ACT		(1 << 0) /* Activates serial memory interface */
+#define KWSPI_SMEMRDY		(1 << 1) /* SerMem Data xfer ready */
+#define KWSPI_CS_SHIFT		2	/* chip select shift */
+#define KWSPI_CS_MASK		0x7	/* chip select mask */
+
+/* Configuration Register */
+#define KWSPI_CLKPRESCL_MASK	0x1f
+#define KWSPI_CLKPRESCL_MIN	0x12
+#define KWSPI_XFERLEN_1BYTE	0
+#define KWSPI_XFERLEN_2BYTE	(1 << 5)
+#define KWSPI_XFERLEN_MASK	(1 << 5)
+#define KWSPI_ADRLEN_1BYTE	0
+#define KWSPI_ADRLEN_2BYTE	(1 << 8)
+#define KWSPI_ADRLEN_3BYTE	(2 << 8)
+#define KWSPI_ADRLEN_4BYTE	(3 << 8)
+#define KWSPI_ADRLEN_MASK	(3 << 8)
+#define KWSPI_CPOL		(1 << 11)
+#define KWSPI_CPHA		(1 << 12)
+#define KWSPI_TXLSBF		(1 << 13)
+#define KWSPI_RXLSBF		(1 << 14)
+
+/* Timing Parameters 1 Register */
+#define KW_SPI_TMISO_SAMPLE_OFFSET	6
+#define KW_SPI_TMISO_SAMPLE_MASK	(0x3 << KW_SPI_TMISO_SAMPLE_OFFSET)
+#define KW_SPI_TMISO_SAMPLE_1		(1 << KW_SPI_TMISO_SAMPLE_OFFSET)
+#define KW_SPI_TMISO_SAMPLE_2		(2 << KW_SPI_TMISO_SAMPLE_OFFSET)
+
+#define KWSPI_IRQUNMASK		1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK		0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ		1 /* SerMem data xfer ready irq */
+
+#define KWSPI_TIMEOUT		10000
+
+#endif /* __KW_SPI_H__ */
diff --git a/arch/arm/include/asm/arch-mx25/clock.h b/arch/arm/include/asm/arch-mx25/clock.h
new file mode 100644
index 0000000..7eec731
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx25/clock.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *
+ * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
+ *
+ * Modified for mx25 by John Rigby <jrigby@gmail.com>
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+#ifdef CONFIG_MX25_HCLK_FREQ
+#define MXC_HCLK	CONFIG_MX25_HCLK_FREQ
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_MX25_CLK32
+#define MXC_CLK32	CONFIG_MX25_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
+enum mxc_clock {
+	/* PER clocks (do not change order) */
+	MXC_CSI_CLK,
+	MXC_EPIT_CLK,
+	MXC_ESAI_CLK,
+	MXC_ESDHC1_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_GPT_CLK,
+	MXC_I2C_CLK,
+	MXC_LCDC_CLK,
+	MXC_NFC_CLK,
+	MXC_OWIRE_CLK,
+	MXC_PWM_CLK,
+	MXC_SIM1_CLK,
+	MXC_SIM2_CLK,
+	MXC_SSI1_CLK,
+	MXC_SSI2_CLK,
+	MXC_UART_CLK,
+	/* Other clocks */
+	MXC_ARM_CLK,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_CSPI_CLK,
+	MXC_FEC_CLK,
+	MXC_CLK_NUM
+};
+
+int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#define imx_get_uartclk()	mxc_get_clock(MXC_UART_CLK)
+#define imx_get_fecclk()	mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx25/gpio.h b/arch/arm/include/asm/arch-mx25/gpio.h
new file mode 100644
index 0000000..1205695
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx25/gpio.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ */
+
+
+#ifndef __ASM_ARCH_MX25_GPIO_H
+#define __ASM_ARCH_MX25_GPIO_H
+
+#include <asm/mach-imx/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
new file mode 100644
index 0000000..5d0974f
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -0,0 +1,534 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009, DENX Software Engineering
+ * Author: John Rigby <jcrigby@gmail.com
+ *
+ *   Based on arch-mx31/imx-regs.h
+ *	Copyright (C) 2009 Ilya Yanok,
+ *		Emcraft Systems <yanok@emcraft.com>
+ *   and arch-mx27/imx-regs.h
+ *	Copyright (C) 2007 Pengutronix,
+ *		Sascha Hauer <s.hauer@pengutronix.de>
+ *	Copyright (C) 2009 Ilya Yanok,
+ *		Emcraft Systems <yanok@emcraft.com>
+ */
+
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* Clock Control Module (CCM) registers */
+struct ccm_regs {
+	u32 mpctl;	/* Core PLL Control */
+	u32 upctl;	/* USB PLL Control */
+	u32 cctl;	/* Clock Control */
+	u32 cgr0;	/* Clock Gating Control 0 */
+	u32 cgr1;	/* Clock Gating Control 1 */
+	u32 cgr2;	/* Clock Gating Control 2 */
+	u32 pcdr[4];	/* PER Clock Dividers */
+	u32 rcsr;	/* CCM Status */
+	u32 crdr;	/* CCM Reset and Debug */
+	u32 dcvr0;	/* DPTC Comparator Value 0 */
+	u32 dcvr1;	/* DPTC Comparator Value 1 */
+	u32 dcvr2;	/* DPTC Comparator Value 2 */
+	u32 dcvr3;	/* DPTC Comparator Value 3 */
+	u32 ltr0;	/* Load Tracking 0 */
+	u32 ltr1;	/* Load Tracking 1 */
+	u32 ltr2;	/* Load Tracking 2 */
+	u32 ltr3;	/* Load Tracking 3 */
+	u32 ltbr0;	/* Load Tracking Buffer 0 */
+	u32 ltbr1;	/* Load Tracking Buffer 1 */
+	u32 pcmr0;	/* Power Management Control 0 */
+	u32 pcmr1;	/* Power Management Control 1 */
+	u32 pcmr2;	/* Power Management Control 2 */
+	u32 mcr;	/* Miscellaneous Control */
+	u32 lpimr0;	/* Low Power Interrupt Mask 0 */
+	u32 lpimr1;	/* Low Power Interrupt Mask 1 */
+};
+
+/* Enhanced SDRAM Controller (ESDRAMC) registers */
+struct esdramc_regs {
+	u32 ctl0; 	/* control 0 */
+	u32 cfg0; 	/* configuration 0 */
+	u32 ctl1; 	/* control 1 */
+	u32 cfg1; 	/* configuration 1 */
+	u32 misc; 	/* miscellaneous */
+	u32 pad[3];
+	u32 cdly1;	/* Delay Line 1 configuration debug */
+	u32 cdly2;	/* delay line 2 configuration debug */
+	u32 cdly3;	/* delay line 3 configuration debug */
+	u32 cdly4;	/* delay line 4 configuration debug */
+	u32 cdly5;	/* delay line 5 configuration debug */
+	u32 cdlyl;	/* delay line cycle length debug */
+};
+
+/* General Purpose Timer (GPT) registers */
+struct gpt_regs {
+	u32 ctrl;   	/* control */
+	u32 pre;    	/* prescaler */
+	u32 stat;   	/* status */
+	u32 intr;   	/* interrupt */
+	u32 cmp[3]; 	/* output compare 1-3 */
+	u32 capt[2];	/* input capture 1-2 */
+	u32 counter;	/* counter */
+};
+
+/* Watchdog Timer (WDOG) registers */
+struct wdog_regs {
+	u16 wcr;	/* Control */
+	u16 wsr;	/* Service */
+	u16 wrsr;	/* Reset Status */
+	u16 wicr;	/* Interrupt Control */
+	u16 wmcr;	/* Misc Control */
+};
+
+/* IIM control registers */
+struct iim_regs {
+	u32 iim_stat;
+	u32 iim_statm;
+	u32 iim_err;
+	u32 iim_emask;
+	u32 iim_fctl;
+	u32 iim_ua;
+	u32 iim_la;
+	u32 iim_sdat;
+	u32 iim_prev;
+	u32 iim_srev;
+	u32 iim_prg_p;
+	u32 iim_scs0;
+	u32 iim_scs1;
+	u32 iim_scs2;
+	u32 iim_scs3;
+	u32 res1[0x1f1];
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+		u32 fuse_rsvd[0xe0];
+	} bank[3];
+};
+
+struct fuse_bank0_regs {
+	u32 fuse0_7[8];
+	u32 uid[8];
+	u32 fuse16_25[0xa];
+	u32 mac_addr[6];
+};
+
+struct fuse_bank1_regs {
+	u32 fuse0_21[0x16];
+	u32 usr5;
+	u32 fuse23_29[7];
+	u32 usr6[2];
+};
+
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+	u32 mpr0;
+	u32 pad00[3];
+	u32 sgpcr0;
+	u32 pad01[59];
+	u32 mpr1;
+	u32 pad02[3];
+	u32 sgpcr1;
+	u32 pad03[59];
+	u32 mpr2;
+	u32 pad04[3];
+	u32 sgpcr2;
+	u32 pad05[59];
+	u32 mpr3;
+	u32 pad06[3];
+	u32 sgpcr3;
+	u32 pad07[59];
+	u32 mpr4;
+	u32 pad08[3];
+	u32 sgpcr4;
+	u32 pad09[251];
+	u32 mgpcr0;
+	u32 pad10[63];
+	u32 mgpcr1;
+	u32 pad11[63];
+	u32 mgpcr2;
+	u32 pad12[63];
+	u32 mgpcr3;
+	u32 pad13[63];
+	u32 mgpcr4;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+	u32 mpr_0_7;
+	u32 mpr_8_15;
+};
+/* LCD controller registers */
+struct lcdc_regs {
+	u32 lssar;	/* Screen Start Address */
+	u32 lsr;	/* Size */
+	u32 lvpwr;	/* Virtual Page Width */
+	u32 lcpr;	/* Cursor Position */
+	u32 lcwhb;	/* Cursor Width Height and Blink */
+	u32 lccmr;	/* Color Cursor Mapping */
+	u32 lpcr;	/* Panel Configuration */
+	u32 lhcr;	/* Horizontal Configuration */
+	u32 lvcr;	/* Vertical Configuration */
+	u32 lpor;	/* Panning Offset */
+	u32 lscr;	/* Sharp Configuration */
+	u32 lpccr;	/* PWM Contrast Control */
+	u32 ldcr;	/* DMA Control */
+	u32 lrmcr;	/* Refresh Mode Control */
+	u32 licr;	/* Interrupt Configuration */
+	u32 lier;	/* Interrupt Enable */
+	u32 lisr;	/* Interrupt Status */
+	u32 res0[3];
+	u32 lgwsar;	/* Graphic Window Start Address */
+	u32 lgwsr;	/* Graphic Window Size */
+	u32 lgwvpwr;	/* Graphic Window Virtual Page Width Regist */
+	u32 lgwpor;	/* Graphic Window Panning Offset */
+	u32 lgwpr;	/* Graphic Window Position */
+	u32 lgwcr;	/* Graphic Window Control */
+	u32 lgwdcr;	/* Graphic Window DMA Control */
+	u32 res1[5];
+	u32 lauscr;	/* AUS Mode Control */
+	u32 lausccr;	/* AUS mode Cursor Control */
+	u32 res2[31 + 64*7];
+	u32 bglut;	/* Background Lookup Table */
+	u32 gwlut;	/* Graphic Window Lookup Table */
+};
+
+/* Wireless External Interface Module Registers */
+struct weim_regs {
+	u32 cscr0u;	/* Chip Select 0 Upper Register */
+	u32 cscr0l;	/* Chip Select 0 Lower Register */
+	u32 cscr0a;	/* Chip Select 0 Addition Register */
+	u32 pad0;
+	u32 cscr1u;	/* Chip Select 1 Upper Register */
+	u32 cscr1l;	/* Chip Select 1 Lower Register */
+	u32 cscr1a;	/* Chip Select 1 Addition Register */
+	u32 pad1;
+	u32 cscr2u;	/* Chip Select 2 Upper Register */
+	u32 cscr2l;	/* Chip Select 2 Lower Register */
+	u32 cscr2a;	/* Chip Select 2 Addition Register */
+	u32 pad2;
+	u32 cscr3u;	/* Chip Select 3 Upper Register */
+	u32 cscr3l;	/* Chip Select 3 Lower Register */
+	u32 cscr3a;	/* Chip Select 3 Addition Register */
+	u32 pad3;
+	u32 cscr4u;	/* Chip Select 4 Upper Register */
+	u32 cscr4l;	/* Chip Select 4 Lower Register */
+	u32 cscr4a;	/* Chip Select 4 Addition Register */
+	u32 pad4;
+	u32 cscr5u;	/* Chip Select 5 Upper Register */
+	u32 cscr5l;	/* Chip Select 5 Lower Register */
+	u32 cscr5a;	/* Chip Select 5 Addition Register */
+	u32 pad5;
+	u32 wcr;	/* WEIM Configuration Register */
+};
+
+/* Multi-Master Memory Interface */
+struct m3if_regs {
+	u32 ctl;	/* Control Register */
+	u32 wcfg0;	/* Watermark Configuration Register 0 */
+	u32 wcfg1;	/* Watermark Configuration Register1 */
+	u32 wcfg2;	/* Watermark Configuration Register2 */
+	u32 wcfg3;	/* Watermark Configuration Register 3 */
+	u32 wcfg4;	/* Watermark Configuration Register 4 */
+	u32 wcfg5;	/* Watermark Configuration Register 5 */
+	u32 wcfg6;	/* Watermark Configuration Register 6 */
+	u32 wcfg7;	/* Watermark Configuration Register 7 */
+	u32 wcsr;	/* Watermark Control and Status Register */
+	u32 scfg0;	/* Snooping Configuration Register 0 */
+	u32 scfg1;	/* Snooping Configuration Register 1 */
+	u32 scfg2;	/* Snooping Configuration Register 2 */
+	u32 ssr0;	/* Snooping Status Register 0 */
+	u32 ssr1;	/* Snooping Status Register 1 */
+	u32 res0;
+	u32 mlwe0;	/* Master Lock WEIM CS0 Register */
+	u32 mlwe1;	/* Master Lock WEIM CS1 Register */
+	u32 mlwe2;	/* Master Lock WEIM CS2 Register */
+	u32 mlwe3;	/* Master Lock WEIM CS3 Register */
+	u32 mlwe4;	/* Master Lock WEIM CS4 Register */
+	u32 mlwe5;	/* Master Lock WEIM CS5 Register */
+};
+
+/* Pulse width modulation */
+struct pwm_regs {
+	u32 cr;	/* Control Register */
+	u32 sr;	/* Status Register */
+	u32 ir;	/* Interrupt Register */
+	u32 sar;	/* Sample Register */
+	u32 pr;	/* Period Register */
+	u32 cnr;	/* Counter Register */
+};
+
+/* Enhanced Periodic Interrupt Timer */
+struct epit_regs {
+	u32 cr;	/* Control register */
+	u32 sr;	/* Status register */
+	u32 lr;	/* Load register */
+	u32 cmpr;	/* Compare register */
+	u32 cnr;	/* Counter register */
+};
+
+/* CSPI registers */
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+	u32 test;
+};
+
+#endif
+
+#define ARCH_MXC
+
+/* AIPS 1 */
+#define IMX_AIPS1_BASE		(0x43F00000)
+#define IMX_MAX_BASE		(0x43F04000)
+#define IMX_CLKCTL_BASE		(0x43F08000)
+#define IMX_ETB_SLOT4_BASE	(0x43F0C000)
+#define IMX_ETB_SLOT5_BASE	(0x43F10000)
+#define IMX_ECT_CTIO_BASE	(0x43F18000)
+#define I2C1_BASE_ADDR		(0x43F80000)
+#define I2C3_BASE_ADDR		(0x43F84000)
+#define IMX_CAN1_BASE		(0x43F88000)
+#define IMX_CAN2_BASE		(0x43F8C000)
+#define UART1_BASE		(0x43F90000)
+#define UART2_BASE		(0x43F94000)
+#define I2C2_BASE_ADDR		(0x43F98000)
+#define IMX_OWIRE_BASE		(0x43F9C000)
+#define IMX_CSPI1_BASE		(0x43FA4000)
+#define IMX_KPP_BASE		(0x43FA8000)
+#define IMX_IOPADMUX_BASE	(0x43FAC000)
+#define IOMUXC_BASE_ADDR	IMX_IOPADMUX_BASE
+#define IMX_IOPADCTL_BASE	(0x43FAC22C)
+#define IMX_IOPADGRPCTL_BASE	(0x43FAC418)
+#define IMX_IOPADINPUTSEL_BASE	(0x43FAC460)
+#define IMX_AUDMUX_BASE		(0x43FB0000)
+#define IMX_ECT_IP1_BASE	(0x43FB8000)
+#define IMX_ECT_IP2_BASE	(0x43FBC000)
+
+/* SPBA */
+#define IMX_SPBA_BASE		(0x50000000)
+#define IMX_CSPI3_BASE		(0x50004000)
+#define UART4_BASE		(0x50008000)
+#define UART3_BASE		(0x5000C000)
+#define IMX_CSPI2_BASE		(0x50010000)
+#define IMX_SSI2_BASE		(0x50014000)
+#define IMX_ESAI_BASE		(0x50018000)
+#define IMX_ATA_DMA_BASE	(0x50020000)
+#define IMX_SIM1_BASE		(0x50024000)
+#define IMX_SIM2_BASE		(0x50028000)
+#define UART5_BASE		(0x5002C000)
+#define IMX_TSC_BASE		(0x50030000)
+#define IMX_SSI1_BASE		(0x50034000)
+#define IMX_FEC_BASE		(0x50038000)
+#define IMX_SPBA_CTRL_BASE	(0x5003C000)
+
+/* AIPS 2 */
+#define IMX_AIPS2_BASE		(0x53F00000)
+#define IMX_CCM_BASE		(0x53F80000)
+#define IMX_GPT4_BASE		(0x53F84000)
+#define IMX_GPT3_BASE		(0x53F88000)
+#define IMX_GPT2_BASE		(0x53F8C000)
+#define IMX_GPT1_BASE		(0x53F90000)
+#define IMX_EPIT1_BASE		(0x53F94000)
+#define IMX_EPIT2_BASE		(0x53F98000)
+#define IMX_GPIO4_BASE		(0x53F9C000)
+#define IMX_PWM2_BASE		(0x53FA0000)
+#define IMX_GPIO3_BASE		(0x53FA4000)
+#define IMX_PWM3_BASE		(0x53FA8000)
+#define IMX_SCC_BASE		(0x53FAC000)
+#define IMX_SCM_BASE		(0x53FAE000)
+#define IMX_SMN_BASE		(0x53FAF000)
+#define IMX_RNGD_BASE		(0x53FB0000)
+#define IMX_MMC_SDHC1_BASE	(0x53FB4000)
+#define IMX_MMC_SDHC2_BASE	(0x53FB8000)
+#define IMX_LCDC_BASE		(0x53FBC000)
+#define IMX_SLCDC_BASE		(0x53FC0000)
+#define IMX_PWM4_BASE		(0x53FC8000)
+#define IMX_GPIO1_BASE		(0x53FCC000)
+#define IMX_GPIO2_BASE		(0x53FD0000)
+#define IMX_SDMA_BASE		(0x53FD4000)
+#define IMX_WDT_BASE		(0x53FDC000)
+#define WDOG1_BASE_ADDR	IMX_WDT_BASE
+#define IMX_PWM1_BASE		(0x53FE0000)
+#define IMX_RTIC_BASE		(0x53FEC000)
+#define IMX_IIM_BASE		(0x53FF0000)
+#define IIM_BASE_ADDR		IMX_IIM_BASE
+#define IMX_USB_BASE		(0x53FF4000)
+/*
+ * This is in contradiction to the imx25 reference manual, which says that
+ * port 1's registers start at 0x53FF4200. The correct base address for
+ * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well.
+ */
+#define IMX_USB_PORT_OFFSET	0x400
+#define IMX_CSI_BASE		(0x53FF8000)
+#define IMX_DRYICE_BASE		(0x53FFC000)
+
+#define IMX_ARM926_ROMPATCH	(0x60000000)
+#define IMX_ARM926_ASIC		(0x68000000)
+
+/* 128K Internal Static RAM */
+#define IMX_RAM_BASE		(0x78000000)
+#define IMX_RAM_SIZE		(128 * 1024)
+
+/* SDRAM BANKS */
+#define IMX_SDRAM_BANK0_BASE	(0x80000000)
+#define IMX_SDRAM_BANK1_BASE	(0x90000000)
+
+#define IMX_WEIM_CS0		(0xA0000000)
+#define IMX_WEIM_CS1		(0xA8000000)
+#define IMX_WEIM_CS2		(0xB0000000)
+#define IMX_WEIM_CS3		(0xB2000000)
+#define IMX_WEIM_CS4		(0xB4000000)
+#define IMX_ESDRAMC_BASE	(0xB8001000)
+#define IMX_WEIM_CTRL_BASE	(0xB8002000)
+#define IMX_M3IF_CTRL_BASE	(0xB8003000)
+#define IMX_EMI_CTRL_BASE	(0xB8004000)
+
+/* NAND Flash Controller */
+#define IMX_NFC_BASE		(0xBB000000)
+#define NFC_BASE_ADDR		IMX_NFC_BASE
+
+/* CCM bitfields */
+#define CCM_PLL_MFI_SHIFT	10
+#define CCM_PLL_MFI_MASK	0xf
+#define CCM_PLL_MFN_SHIFT	0
+#define CCM_PLL_MFN_MASK	0x3ff
+#define CCM_PLL_MFD_SHIFT	16
+#define CCM_PLL_MFD_MASK	0x3ff
+#define CCM_PLL_PD_SHIFT	26
+#define CCM_PLL_PD_MASK		0xf
+#define CCM_CCTL_ARM_DIV_SHIFT	30
+#define CCM_CCTL_ARM_DIV_MASK	3
+#define CCM_CCTL_AHB_DIV_SHIFT	28
+#define CCM_CCTL_AHB_DIV_MASK	3
+#define CCM_CCTL_ARM_SRC	(1 << 14)
+#define CCM_CGR1_GPT1		(1 << 19)
+#define CCM_PERCLK_REG(clk)	(clk / 4)
+#define CCM_PERCLK_SHIFT(clk)	(8 * (clk % 4))
+#define CCM_PERCLK_MASK		0x3f
+#define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
+#define CCM_RCSR_NF_PS(v)	((v >> 26) & 3)
+#define CCM_CRDR_BT_UART_SRC_SHIFT	29
+#define CCM_CRDR_BT_UART_SRC_MASK	7
+
+/* ESDRAM Controller register bitfields */
+#define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
+#define ESDCTL_BL		(1 << 7)
+#define ESDCTL_FP		(1 << 8)
+#define ESDCTL_PWDT(x)		(((x) & 3) << 10)
+#define ESDCTL_SREFR(x)		(((x) & 7) << 13)
+#define ESDCTL_DSIZ_16_UPPER	(0 << 16)
+#define ESDCTL_DSIZ_16_LOWER	(1 << 16)
+#define ESDCTL_DSIZ_32		(2 << 16)
+#define ESDCTL_COL8		(0 << 20)
+#define ESDCTL_COL9		(1 << 20)
+#define ESDCTL_COL10		(2 << 20)
+#define ESDCTL_ROW11		(0 << 24)
+#define ESDCTL_ROW12		(1 << 24)
+#define ESDCTL_ROW13		(2 << 24)
+#define ESDCTL_ROW14		(3 << 24)
+#define ESDCTL_ROW15		(4 << 24)
+#define ESDCTL_SP		(1 << 27)
+#define ESDCTL_SMODE_NORMAL	(0 << 28)
+#define ESDCTL_SMODE_PRECHARGE	(1 << 28)
+#define ESDCTL_SMODE_AUTO_REF	(2 << 28)
+#define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
+#define ESDCTL_SMODE_MAN_REF	(4 << 28)
+#define ESDCTL_SDE		(1 << 31)
+
+#define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
+#define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
+#define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
+#define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
+#define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
+#define ESDCFG_TWR		(1 << 15)
+#define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
+#define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
+#define ESDCFG_TWTR		(1 << 20)
+#define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
+
+#define ESDMISC_RST		(1 << 1)
+#define ESDMISC_MDDREN		(1 << 2)
+#define ESDMISC_MDDR_DL_RST	(1 << 3)
+#define ESDMISC_MDDR_MDIS	(1 << 4)
+#define ESDMISC_LHD		(1 << 5)
+#define ESDMISC_MA10_SHARE	(1 << 6)
+#define ESDMISC_SDRAM_RDY	(1 << 31)
+
+/* GPT bits */
+#define GPT_CTRL_SWR		(1 << 15)	/* Software reset */
+#define GPT_CTRL_FRR		(1 << 9)	/* Freerun / restart */
+#define GPT_CTRL_CLKSOURCE_32	(4 << 6)	/* Clock source	*/
+#define GPT_CTRL_TEN		1		/* Timer enable	*/
+
+/* WDOG enable */
+#define WCR_WDE 		0x04
+#define WSR_UNLOCK1		0x5555
+#define WSR_UNLOCK2		0xAAAA
+
+/* MAX bits */
+#define MAX_MGPCR_AULB(x)	(((x) & 0x7) << 0)
+
+/* M3IF bits */
+#define M3IF_CTL_MRRP(x)	(((x) & 0xff) << 0)
+
+/* WEIM bits */
+/* 13 fields of the upper CS control register */
+#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
+		cnc, wsc, ew, wws, edc) \
+		((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
+		(psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
+		(cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
+/* 12 fields of the lower CS control register */
+#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
+		csa, ebc, dsz, csn, psr, cre, wrap, csen) \
+		((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
+		(csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
+		(psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
+/* 14 fields of the additional CS control register */
+#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
+		wwu, age, cnc2, fce) \
+		((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
+		(mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
+		(dww) << 6 | (dct) << 4 | (wwu) << 3 |\
+		(age) << 2 | (cnc2) << 1 | (fce) << 0)
+
+/* Names used in GPIO driver */
+#define GPIO1_BASE_ADDR		IMX_GPIO1_BASE
+#define GPIO2_BASE_ADDR		IMX_GPIO2_BASE
+#define GPIO3_BASE_ADDR		IMX_GPIO3_BASE
+#define GPIO4_BASE_ADDR		IMX_GPIO4_BASE
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_SMC	(1 << 3)
+#define MXC_CSPICTRL_POL	(1 << 4)
+#define MXC_CSPICTRL_PHA	(1 << 5)
+#define MXC_CSPICTRL_SSCTL	(1 << 6)
+#define MXC_CSPICTRL_SSPOL	(1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	4
+
+#define MXC_SPI_BASE_ADDRESSES \
+	IMX_CSPI1_BASE, \
+	IMX_CSPI2_BASE, \
+	IMX_CSPI3_BASE
+
+#endif				/* _IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx25/iomux-mx25.h b/arch/arm/include/asm/arch-mx25/iomux-mx25.h
new file mode 100644
index 0000000..1ce7a85
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx25/iomux-mx25.h
@@ -0,0 +1,537 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on mainline Linux i.MX iomux-mx25.h file:
+ * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
+ *
+ * Based on Linux arch/arm/mach-mx25/mx25_pins.h:
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ */
+
+#ifndef __IOMUX_MX25_H__
+#define __IOMUX_MX25_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX25_KPP_ROW_PAD_CTRL	PAD_CTL_PUS_100K_UP
+#define MX25_KPP_COL_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+/*
+ * The naming convention for the pad modes is MX25_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*							    PAD    MUX    ALT INPSE PATH PADCTRL */
+enum {
+	MX25_PAD_A10__A10			= IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A10__GPIO_4_0			= IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A13__A13			= IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A13__GPIO_4_1			= IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A14__A14			= IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A14__GPIO_2_0			= IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A15__A15			= IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A15__GPIO_2_1			= IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A16__A16			= IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A16__GPIO_2_2			= IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A17__A17			= IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A17__GPIO_2_3			= IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A18__A18			= IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A18__GPIO_2_4			= IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A18__FEC_COL			= IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A19__A19			= IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A19__FEC_RX_ER			= IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL),
+	MX25_PAD_A19__GPIO_2_5			= IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A20__A20			= IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A20__GPIO_2_6			= IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A20__FEC_RDATA2		= IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A21__A21			= IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A21__GPIO_2_7			= IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A21__FEC_RDATA3		= IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A22__A22			= IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A22__GPIO_2_8			= IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A23__A23			= IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A23__GPIO_2_9			= IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A24__A24			= IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A24__GPIO_2_10			= IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A24__FEC_RX_CLK		= IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL),
+
+	MX25_PAD_A25__A25			= IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A25__GPIO_2_11			= IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_A25__FEC_CRS			= IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL),
+
+	MX25_PAD_EB0__EB0			= IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EB0__AUD4_TXD			= IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL),
+	MX25_PAD_EB0__GPIO_2_12			= IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_EB1__EB1			= IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EB1__AUD4_RXD			= IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL),
+	MX25_PAD_EB1__GPIO_2_13			= IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_OE__OE				= IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE__AUD4_TXC			= IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE__GPIO_2_14			= IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS0__CS0			= IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS0__GPIO_4_2			= IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS1__CS1			= IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS1__NF_CE3			= IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS1__GPIO_4_3			= IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS4__CS4			= IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__NF_CE1			= IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__UART5_CTS			= IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS4__GPIO_3_20			= IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CS5__CS5			= IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__NF_CE2			= IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__UART5_RTS			= IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL),
+	MX25_PAD_CS5__GPIO_3_21			= IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NF_CE0__NF_CE0			= IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NF_CE0__GPIO_3_22		= IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_ECB__ECB			= IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_ECB__UART5_TXD_MUX		= IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_ECB__GPIO_3_23			= IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LBA__LBA			= IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LBA__UART5_RXD_MUX		= IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL),
+	MX25_PAD_LBA__GPIO_3_24			= IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_BCLK__BCLK			= IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BCLK__GPIO_4_4			= IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_RW__RW				= IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RW__AUD4_TXFS			= IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL),
+	MX25_PAD_RW__GPIO_3_25			= IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFWE_B__NFWE_B			= IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFWE_B__GPIO_3_26		= IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFRE_B__NFRE_B			= IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFRE_B__GPIO_3_27		= IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFALE__NFALE			= IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFALE__GPIO_3_28		= IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFCLE__NFCLE			= IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFCLE__GPIO_3_29		= IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFWP_B__NFWP_B			= IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_NFWP_B__GPIO_3_30		= IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_NFRB__NFRB			= IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE),
+	MX25_PAD_NFRB__GPIO_3_31		= IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D15__D15			= IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D15__LD16			= IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_D15__GPIO_4_5			= IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D14__D14			= IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D14__LD17			= IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_D14__GPIO_4_6			= IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D13__D13			= IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D13__LD18			= IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_D13__GPIO_4_7			= IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D12__D12			= IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D12__GPIO_4_8			= IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D11__D11			= IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D11__GPIO_4_9			= IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D10__D10			= IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D10__GPIO_4_10			= IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D10__USBOTG_OC			= IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_D9__D9				= IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D9__GPIO_4_11			= IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D9__USBH2_PWR			= IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE),
+
+	MX25_PAD_D8__D8				= IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D8__GPIO_4_12			= IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D8__USBH2_OC			= IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_D7__D7				= IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D7__GPIO_4_13			= IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D6__D6				= IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D6__GPIO_4_14			= IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D5__D5				= IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D5__GPIO_4_15			= IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D4__D4				= IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D4__GPIO_4_16			= IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D3__D3				= IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D3__GPIO_4_17			= IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D2__D2				= IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D2__GPIO_4_18			= IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D1__D1				= IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D1__GPIO_4_19			= IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_D0__D0				= IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_D0__GPIO_4_20			= IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD0__LD0			= IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD0__CSI_D0			= IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL),
+	MX25_PAD_LD0__GPIO_2_15			= IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD1__LD1			= IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD1__CSI_D1			= IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL),
+	MX25_PAD_LD1__GPIO_2_16			= IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD2__LD2			= IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD2__GPIO_2_17			= IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD3__LD3			= IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD3__GPIO_2_18			= IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD4__LD4			= IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD4__GPIO_2_19			= IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD5__LD5			= IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD5__GPIO_1_19			= IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD6__LD6			= IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD6__GPIO_1_20			= IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD7__LD7			= IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD7__GPIO_1_21			= IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD8__LD8			= IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD8__FEC_TX_ERR		= IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD9__LD9			= IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD9__FEC_COL			= IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD10__LD10			= IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD10__FEC_RX_ER		= IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD11__LD11			= IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD11__FEC_RDATA2		= IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD12__LD12			= IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD12__FEC_RDATA3		= IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL),
+
+	MX25_PAD_LD13__LD13			= IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD13__FEC_TDATA2		= IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD14__LD14			= IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD14__FEC_TDATA3		= IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LD15__LD15			= IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_LD15__FEC_RX_CLK		= IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL),
+
+	MX25_PAD_HSYNC__HSYNC			= IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_HSYNC__GPIO_1_22		= IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_VSYNC__VSYNC			= IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSYNC__GPIO_1_23		= IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_LSCLK__LSCLK			= IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_LSCLK__GPIO_1_24		= IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_OE_ACD__OE_ACD			= IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_OE_ACD__GPIO_1_25		= IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CONTRAST__CONTRAST		= IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CONTRAST__PWM4_PWMO		= IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CONTRAST__FEC_CRS		= IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL),
+
+	MX25_PAD_PWM__PWM			= IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_PWM__GPIO_1_26			= IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_PWM__USBH2_OC			= IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_CSI_D2__CSI_D2			= IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__UART5_RXD_MUX		= IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__GPIO_1_27		= IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D2__CSPI3_MOSI		= IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D3__CSI_D3			= IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D3__GPIO_1_28		= IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D3__CSPI3_MISO		= IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D4__CSI_D4			= IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__UART5_RTS		= IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__GPIO_1_29		= IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D4__CSPI3_SCLK		= IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D5__CSI_D5			= IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D5__GPIO_1_30		= IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D5__CSPI3_RDY		= IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D6__CSI_D6			= IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D6__GPIO_1_31		= IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D7__CSI_D7			= IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D7__GPIO_1_6		= IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D8__CSI_D8			= IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D8__GPIO_1_7		= IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_D9__CSI_D9			= IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_D9__GPIO_4_21		= IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_MCLK__CSI_MCLK		= IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_MCLK__GPIO_1_8		= IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_VSYNC__CSI_VSYNC		= IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_VSYNC__GPIO_1_9		= IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_HSYNC__CSI_HSYNC		= IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_HSYNC__GPIO_1_10		= IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSI_PIXCLK__CSI_PIXCLK		= IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSI_PIXCLK__GPIO_1_11		= IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_I2C1_CLK__I2C1_CLK		= IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_I2C1_CLK__GPIO_1_12		= IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_I2C1_DAT__I2C1_DAT		= IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_I2C1_DAT__GPIO_1_13		= IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_MOSI__CSPI1_MOSI		= IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_MOSI__GPIO_1_14		= IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_MISO__CSPI1_MISO		= IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_MISO__GPIO_1_15		= IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_SS0__CSPI1_SS0		= IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS0__GPIO_1_16		= IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_SS1__CSPI1_SS1		= IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS1__I2C3_DAT		= IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SS1__GPIO_1_17		= IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_SCLK__CSPI1_SCLK		= IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CSPI1_SCLK__GPIO_1_18		= IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CSPI1_RDY__CSPI1_RDY		= IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE),
+	MX25_PAD_CSPI1_RDY__GPIO_2_22		= IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_RXD__UART1_RXD		= IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_UART1_RXD__GPIO_4_22		= IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_TXD__UART1_TXD		= IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART1_TXD__GPIO_4_23		= IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_RTS__UART1_RTS		= IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_UART1_RTS__CSI_D0		= IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL),
+	MX25_PAD_UART1_RTS__GPIO_4_24		= IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART1_CTS__UART1_CTS		= IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_UART1_CTS__CSI_D1		= IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL),
+	MX25_PAD_UART1_CTS__GPIO_4_25		= IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_RXD__UART2_RXD		= IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_RXD__GPIO_4_26		= IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_TXD__UART2_TXD		= IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_TXD__GPIO_4_27		= IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_RTS__UART2_RTS		= IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_RTS__FEC_COL		= IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL),
+	MX25_PAD_UART2_RTS__GPIO_4_28		= IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UART2_CTS__FEC_RX_ER		= IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL),
+	MX25_PAD_UART2_CTS__UART2_CTS		= IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UART2_CTS__GPIO_4_29		= IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	/*
+	 * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
+	 * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
+	 * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
+	 * bug that configuring the SD1_CMD function doesn't enable the input path for
+	 * this pin.
+	 * This might have side effects for other hardware units that are connected to
+	 * that pin and use the respective function as input.
+	 */
+	MX25_PAD_SD1_CMD__SD1_CMD		= IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_CMD__FEC_RDATA2		= IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_CMD__GPIO_2_23		= IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_CLK__SD1_CLK		= IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_CLK__FEC_RDATA3		= IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_CLK__GPIO_2_24		= IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA0__SD1_DATA0		= IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA0__GPIO_2_25		= IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA1__SD1_DATA1		= IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA1__AUD7_RXD		= IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA1__GPIO_2_26		= IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA2__SD1_DATA2		= IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA2__FEC_RX_CLK		= IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA2__GPIO_2_27		= IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_SD1_DATA3__SD1_DATA3		= IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
+	MX25_PAD_SD1_DATA3__FEC_CRS		= IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL),
+	MX25_PAD_SD1_DATA3__GPIO_2_28		= IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW0__KPP_ROW0		= IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW0__GPIO_2_29		= IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW1__KPP_ROW1		= IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW1__GPIO_2_30		= IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW2__KPP_ROW2		= IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW2__CSI_D0		= IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW2__GPIO_2_31		= IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_ROW3__KPP_ROW3		= IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+	MX25_PAD_KPP_ROW3__CSI_LD1		= IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL),
+	MX25_PAD_KPP_ROW3__GPIO_3_0		= IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL0__KPP_COL0		= IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL0__UART4_RXD_MUX	= IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL0__AUD5_TXD		= IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL0__GPIO_3_1		= IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL1__KPP_COL1		= IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL1__UART4_TXD_MUX	= IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL1__AUD5_RXD		= IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL1__GPIO_3_2		= IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL2__KPP_COL2		= IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL2__UART4_RTS		= IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL2__AUD5_TXC		= IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL2__GPIO_3_3		= IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_KPP_COL3__KPP_COL3		= IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
+	MX25_PAD_KPP_COL3__UART4_CTS		= IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_KPP_COL3__AUD5_TXFS		= IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
+	MX25_PAD_KPP_COL3__GPIO_3_4		= IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_MDC__FEC_MDC		= IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDC__AUD4_TXD		= IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDC__GPIO_3_5		= IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_MDIO__FEC_MDIO		= IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
+	MX25_PAD_FEC_MDIO__AUD4_RXD		= IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_MDIO__GPIO_3_6		= IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TDATA0__FEC_TDATA0		= IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA0__GPIO_3_7		= IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TDATA1__FEC_TDATA1		= IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA1__AUD4_TXFS		= IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL),
+	MX25_PAD_FEC_TDATA1__GPIO_3_8		= IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TX_EN__FEC_TX_EN		= IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_FEC_TX_EN__GPIO_3_9		= IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_RDATA0__FEC_RDATA0		= IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RDATA0__GPIO_3_10		= IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_RDATA1__FEC_RDATA1		= IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RDATA1__GPIO_3_11		= IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_RX_DV__FEC_RX_DV		= IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_RX_DV__CAN2_RX		= IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_FEC_RX_DV__GPIO_3_12		= IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		= IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+	MX25_PAD_FEC_TX_CLK__GPIO_3_13		= IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_RTCK__RTCK			= IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RTCK__OWIRE			= IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_RTCK__GPIO_3_14		= IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_DE_B__DE_B			= IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_DE_B__GPIO_2_20		= IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_TDO__TDO			= IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_GPIO_A__GPIO_A			= IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_A__CAN1_TX		= IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_GPIO_A__USBOTG_PWR		= IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE),
+
+	MX25_PAD_GPIO_B__GPIO_B			= IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_B__CAN1_RX		= IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP),
+	MX25_PAD_GPIO_B__USBOTG_OC		= IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP),
+
+	MX25_PAD_GPIO_C__GPIO_C			= IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_C__CAN2_TX		= IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
+
+	MX25_PAD_GPIO_D__GPIO_D			= IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_E__LD16			= IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_GPIO_D__CAN2_RX		= IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP),
+
+	MX25_PAD_GPIO_E__GPIO_E			= IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_F__LD17			= IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
+	MX25_PAD_GPIO_E__I2C3_CLK		= IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL),
+	MX25_PAD_GPIO_E__AUD7_TXD		= IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_GPIO_F__GPIO_F			= IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_GPIO_F__AUD7_TXC		= IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_EXT_ARMCLK__EXT_ARMCLK		= IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_EXT_ARMCLK__GPIO_3_15		= IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK	= IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_UPLL_BYPCLK__GPIO_3_16		= IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_VSTBY_REQ__VSTBY_REQ		= IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_REQ__AUD7_TXFS		= IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_REQ__GPIO_3_17		= IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_ACK__VSTBY_ACK		= IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_VSTBY_ACK__GPIO_3_18		= IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_POWER_FAIL__POWER_FAIL		= IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_POWER_FAIL__AUD7_RXD		= IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL),
+	MX25_PAD_POWER_FAIL__GPIO_3_19		= IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CLKO__CLKO			= IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CLKO__GPIO_2_21		= IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_BOOT_MODE0__BOOT_MODE0		= IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BOOT_MODE0__GPIO_4_30		= IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BOOT_MODE1__BOOT_MODE1		= IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_BOOT_MODE1__GPIO_4_31		= IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL),
+
+	MX25_PAD_CTL_GRP_DVS_MISC		= IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_FEC		= IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_JTAG		= IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_NFC		= IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_CSI		= IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_WEIM		= IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_DDR		= IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_CRM		= IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_KPP		= IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_SDHC1		= IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_LCD		= IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_UART		= IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_NFC		= IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_CSI		= IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DSE_CSPI1		= IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DDRTYPE		= IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_SDHC1		= IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL),
+	MX25_PAD_CTL_GRP_DVS_LCD		= IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX25_H__ */
diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h
new file mode 100644
index 0000000..68bddf4
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx25/macro.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * Common asm macros for imx25
+ */
+
+#ifndef __ASM_ARM_ARCH_MACRO_H__
+#define __ASM_ARM_ARCH_MACRO_H__
+#ifdef __ASSEMBLY__
+
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+#include <asm/macro.h>
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ *
+ * Default argument values:
+ *  - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
+ *    user-mode.
+ */
+.macro init_aips mpr=0x77777777
+	ldr	r0, =IMX_AIPS1_BASE
+	ldr	r1, =\mpr
+	str	r1, [r0, #AIPS_MPR_0_7]
+	str	r1, [r0, #AIPS_MPR_8_15]
+	ldr	r2, =IMX_AIPS2_BASE
+	str	r1, [r2, #AIPS_MPR_0_7]
+	str	r1, [r2, #AIPS_MPR_8_15]
+.endm
+
+/*
+ * MAX (Multi-Layer AHB Crossbar Switch) setup
+ *
+ * Default argument values:
+ *  - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
+ *  - SGPCR: always park on last master
+ *  - MGPCR: restore default values
+ */
+.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000
+	ldr	r0, =IMX_MAX_BASE
+	ldr	r1, =\mpr
+	str	r1, [r0, #MAX_MPR0]	/* for S0 */
+	str	r1, [r0, #MAX_MPR1]	/* for S1 */
+	str	r1, [r0, #MAX_MPR2]	/* for S2 */
+	str	r1, [r0, #MAX_MPR3]	/* for S3 */
+	str	r1, [r0, #MAX_MPR4]	/* for S4 */
+	ldr	r1, =\sgpcr
+	str	r1, [r0, #MAX_SGPCR0]	/* for S0 */
+	str	r1, [r0, #MAX_SGPCR1]	/* for S1 */
+	str	r1, [r0, #MAX_SGPCR2]	/* for S2 */
+	str	r1, [r0, #MAX_SGPCR3]	/* for S3 */
+	str	r1, [r0, #MAX_SGPCR4]	/* for S4 */
+	ldr	r1, =\mgpcr
+	str	r1, [r0, #MAX_MGPCR0]	/* for M0 */
+	str	r1, [r0, #MAX_MGPCR1]	/* for M1 */
+	str	r1, [r0, #MAX_MGPCR2]	/* for M2 */
+	str	r1, [r0, #MAX_MGPCR3]	/* for M3 */
+	str	r1, [r0, #MAX_MGPCR4]	/* for M4 */
+.endm
+
+/*
+ * M3IF setup
+ *
+ * Default argument values:
+ *  - CTL:
+ * MRRP[0] = LCDC on priority list (1 << 0)			= 0x00000001
+ * MRRP[1] = MAX1 not on priority list (0 << 1)			= 0x00000000
+ * MRRP[2] = MAX0 not on priority list (0 << 2)			= 0x00000000
+ * MRRP[3] = USBH not on priority list (0 << 3)			= 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 4)			= 0x00000000
+ * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5)	= 0x00000000
+ * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6)	= 0x00000000
+ * MRRP[7] = CSI not on priority list (0 << 7)			= 0x00000000
+ *								------------
+ *								  0x00000001
+ */
+.macro init_m3if ctl=0x00000001
+	/* M3IF Control Register (M3IFCTL) */
+	write32	IMX_M3IF_CTRL_BASE, \ctl
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_ARCH_MACRO_H__ */
diff --git a/arch/arm/include/asm/arch-mx27/clock.h b/arch/arm/include/asm/arch-mx27/clock.h
new file mode 100644
index 0000000..ab96431
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx27/clock.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *
+ * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+enum mxc_clock {
+	MXC_ARM_CLK,
+	MXC_I2C_CLK,
+	MXC_UART_CLK,
+	MXC_ESDHC_CLK,
+	MXC_FEC_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK)
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx27/gpio.h b/arch/arm/include/asm/arch-mx27/gpio.h
new file mode 100644
index 0000000..9f342eb
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx27/gpio.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012
+ * Philippe Reynes <tremyfr@yahoo.fr>
+ */
+
+
+#ifndef __ASM_ARCH_MX27_GPIO_H
+#define __ASM_ARCH_MX27_GPIO_H
+
+/* GPIO registers */
+struct gpio_regs {
+	u32 gpio_dir; /* DDIR */
+	u32 ocr1;
+	u32 ocr2;
+	u32 iconfa1;
+	u32 iconfa2;
+	u32 iconfb1;
+	u32 iconfb2;
+	u32 gpio_dr; /* DR */
+	u32 gius;
+	u32 gpio_psr; /* SSR */
+	u32 icr1;
+	u32 icr2;
+	u32 imr;
+	u32 isr;
+	u32 gpr;
+	u32 swr;
+	u32 puen;
+	u32 res[0x2f];
+};
+
+/* This structure is used by the function imx_gpio_mode */
+struct gpio_port_regs {
+	struct gpio_regs port[6];
+};
+
+/*
+ *  GPIO Module and I/O Multiplexer
+ */
+#define PORTA 0
+#define PORTB 1
+#define PORTC 2
+#define PORTD 3
+#define PORTE 4
+#define PORTF 5
+
+#define GPIO_PIN_MASK		0x1f
+#define GPIO_PORT_SHIFT		5
+#define GPIO_PORT_MASK		(0x7 << GPIO_PORT_SHIFT)
+#define GPIO_PORTA		(PORTA << GPIO_PORT_SHIFT)
+#define GPIO_PORTB		(PORTB << GPIO_PORT_SHIFT)
+#define GPIO_PORTC		(PORTC << GPIO_PORT_SHIFT)
+#define GPIO_PORTD		(PORTD << GPIO_PORT_SHIFT)
+#define GPIO_PORTE		(PORTE << GPIO_PORT_SHIFT)
+#define GPIO_PORTF		(PORTF << GPIO_PORT_SHIFT)
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
new file mode 100644
index 0000000..d39f6b0
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -0,0 +1,480 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
+ */
+
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+
+#include <asm/arch/regs-rtc.h>
+
+#ifndef __ASSEMBLY__
+
+extern void imx_gpio_mode (int gpio_mode);
+
+#ifdef CONFIG_MXC_UART
+extern void mx27_uart1_init_pins(void);
+#endif /* CONFIG_MXC_UART */
+
+#ifdef CONFIG_FEC_MXC
+extern void mx27_fec_init_pins(void);
+#endif /* CONFIG_FEC_MXC */
+
+#ifdef CONFIG_MMC_MXC
+extern void mx27_sd1_init_pins(void);
+extern void mx27_sd2_init_pins(void);
+#endif /* CONFIG_MMC_MXC */
+
+/* AIPI */
+struct aipi_regs {
+	u32 psr0;
+	u32 psr1;
+};
+
+/* System Control */
+struct system_control_regs {
+	u32 res[5];
+	u32 fmcr;
+	u32 gpcr;
+	u32 wbcr;
+	u32 dscr1;
+	u32 dscr2;
+	u32 dscr3;
+	u32 dscr4;
+	u32 dscr5;
+	u32 dscr6;
+	u32 dscr7;
+	u32 dscr8;
+	u32 dscr9;
+	u32 dscr10;
+	u32 dscr11;
+	u32 dscr12;
+	u32 dscr13;
+	u32 pscr;
+	u32 pmcr;
+	u32 res1;
+	u32 dcvr0;
+	u32 dcvr1;
+	u32 dcvr2;
+	u32 dcvr3;
+};
+
+/* Chip Select Registers */
+struct weim_regs {
+	u32 cs0u;	/* Chip Select 0 Upper Register */
+	u32 cs0l;	/* Chip Select 0 Lower Register */
+	u32 cs0a;	/* Chip Select 0 Addition Register */
+	u32 pad0;
+	u32 cs1u;	/* Chip Select 1 Upper Register */
+	u32 cs1l;	/* Chip Select 1 Lower Register */
+	u32 cs1a;	/* Chip Select 1 Addition Register */
+	u32 pad1;
+	u32 cs2u;	/* Chip Select 2 Upper Register */
+	u32 cs2l;	/* Chip Select 2 Lower Register */
+	u32 cs2a;	/* Chip Select 2 Addition Register */
+	u32 pad2;
+	u32 cs3u;	/* Chip Select 3 Upper Register */
+	u32 cs3l;	/* Chip Select 3 Lower Register */
+	u32 cs3a;	/* Chip Select 3 Addition Register */
+	u32 pad3;
+	u32 cs4u;	/* Chip Select 4 Upper Register */
+	u32 cs4l;	/* Chip Select 4 Lower Register */
+	u32 cs4a;	/* Chip Select 4 Addition Register */
+	u32 pad4;
+	u32 cs5u;	/* Chip Select 5 Upper Register */
+	u32 cs5l;	/* Chip Select 5 Lower Register */
+	u32 cs5a;	/* Chip Select 5 Addition Register */
+	u32 pad5;
+	u32 eim;	/* WEIM Configuration Register */
+};
+
+/* SDRAM Controller registers */
+struct esdramc_regs {
+/* Enhanced SDRAM Control Register 0 */
+	u32 esdctl0;
+/* Enhanced SDRAM Configuration Register 0 */
+	u32 esdcfg0;
+/* Enhanced SDRAM Control Register 1 */
+	u32 esdctl1;
+/* Enhanced SDRAM Configuration Register 1 */
+	u32 esdcfg1;
+/* Enhanced SDRAM Miscellanious Register */
+	u32 esdmisc;
+};
+
+/* Watchdog Registers*/
+struct wdog_regs {
+	u16 wcr;
+	u16 wsr;
+	u16 wstr;
+};
+
+/* PLL registers */
+struct pll_regs {
+	u32 cscr;	/* Clock Source Control Register */
+	u32 mpctl0;	/* MCU PLL Control Register 0 */
+	u32 mpctl1;	/* MCU PLL Control Register 1 */
+	u32 spctl0;	/* System PLL Control Register 0 */
+	u32 spctl1;	/* System PLL Control Register 1 */
+	u32 osc26mctl;	/* Oscillator 26M Register */
+	u32 pcdr0;	/* Peripheral Clock Divider Register 0 */
+	u32 pcdr1;	/* Peripheral Clock Divider Register 1 */
+	u32 pccr0;	/* Peripheral Clock Control Register 0 */
+	u32 pccr1;	/* Peripheral Clock Control Register 1 */
+	u32 ccsr;	/* Clock Control Status Register */
+};
+
+/*
+ * Definitions for the clocksource registers
+ */
+struct gpt_regs {
+	u32 gpt_tctl;
+	u32 gpt_tprer;
+	u32 gpt_tcmp;
+	u32 gpt_tcr;
+	u32 gpt_tcn;
+	u32 gpt_tstat;
+};
+
+/* IIM Control Registers */
+struct iim_regs {
+	u32 iim_stat;
+	u32 iim_statm;
+	u32 iim_err;
+	u32 iim_emask;
+	u32 iim_fctl;
+	u32 iim_ua;
+	u32 iim_la;
+	u32 iim_sdat;
+	u32 iim_prev;
+	u32 iim_srev;
+	u32 iim_prg_p;
+	u32 iim_scs0;
+	u32 iim_scs1;
+	u32 iim_scs2;
+	u32 iim_scs3;
+	u32 res[0x1f1];
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+		u32 fuse_rsvd[0xe0];
+	} bank[2];
+};
+
+struct fuse_bank0_regs {
+	u32 fuse0_3[5];
+	u32 mac_addr[6];
+	u32 fuse10_31[0x16];
+};
+
+#endif
+
+#define ARCH_MXC
+
+#define IMX_IO_BASE		0x10000000
+
+#define IMX_AIPI1_BASE		(0x00000 + IMX_IO_BASE)
+#define IMX_WDT_BASE		(0x02000 + IMX_IO_BASE)
+#define IMX_TIM1_BASE		(0x03000 + IMX_IO_BASE)
+#define IMX_TIM2_BASE		(0x04000 + IMX_IO_BASE)
+#define IMX_TIM3_BASE		(0x05000 + IMX_IO_BASE)
+#define IMX_RTC_BASE		(0x07000 + IMX_IO_BASE)
+#define UART1_BASE		(0x0a000 + IMX_IO_BASE)
+#define UART2_BASE		(0x0b000 + IMX_IO_BASE)
+#define UART3_BASE		(0x0c000 + IMX_IO_BASE)
+#define UART4_BASE		(0x0d000 + IMX_IO_BASE)
+#define I2C1_BASE_ADDR		(0x12000 + IMX_IO_BASE)
+#define IMX_GPIO_BASE		(0x15000 + IMX_IO_BASE)
+#define IMX_TIM4_BASE		(0x19000 + IMX_IO_BASE)
+#define IMX_TIM5_BASE		(0x1a000 + IMX_IO_BASE)
+#define IMX_UART5_BASE		(0x1b000 + IMX_IO_BASE)
+#define IMX_UART6_BASE		(0x1c000 + IMX_IO_BASE)
+#define I2C2_BASE_ADDR		(0x1D000 + IMX_IO_BASE)
+#define IMX_TIM6_BASE		(0x1f000 + IMX_IO_BASE)
+#define IMX_AIPI2_BASE		(0x20000 + IMX_IO_BASE)
+#define IMX_PLL_BASE		(0x27000 + IMX_IO_BASE)
+#define IMX_SYSTEM_CTL_BASE	(0x27800 + IMX_IO_BASE)
+#define IMX_IIM_BASE		(0x28000 + IMX_IO_BASE)
+#define IIM_BASE_ADDR		IMX_IIM_BASE
+#define IMX_FEC_BASE		(0x2b000 + IMX_IO_BASE)
+
+#define IMX_NFC_BASE		(0xD8000000)
+#define IMX_ESD_BASE		(0xD8001000)
+#define IMX_WEIM_BASE		(0xD8002000)
+
+#define NFC_BASE_ADDR		IMX_NFC_BASE
+
+
+/* FMCR System Control bit definition*/
+#define UART4_RXD_CTL	(1 << 25)
+#define UART4_RTS_CTL	(1 << 24)
+#define KP_COL6_CTL	(1 << 18)
+#define KP_ROW7_CTL	(1 << 17)
+#define KP_ROW6_CTL	(1 << 16)
+#define PC_WAIT_B_CTL	(1 << 14)
+#define PC_READY_CTL	(1 << 13)
+#define PC_VS1_CTL	(1 << 12)
+#define PC_VS2_CTL	(1 << 11)
+#define PC_BVD1_CTL	(1 << 10)
+#define PC_BVD2_CTL	(1 << 9)
+#define IOS16_CTL	(1 << 8)
+#define NF_FMS		(1 << 5)
+#define NF_16BIT_SEL	(1 << 4)
+#define SLCDC_SEL	(1 << 2)
+#define SDCS1_SEL	(1 << 1)
+#define SDCS0_SEL	(1 << 0)
+
+
+/* important definition of some bits of WCR */
+#define WCR_WDE 0x04
+
+#define CSCR_MPEN		(1 << 0)
+#define CSCR_SPEN		(1 << 1)
+#define CSCR_FPM_EN		(1 << 2)
+#define CSCR_OSC26M_DIS		(1 << 3)
+#define CSCR_OSC26M_DIV1P5	(1 << 4)
+#define CSCR_AHB_DIV
+#define CSCR_ARM_DIV
+#define CSCR_ARM_SRC_MPLL	(1 << 15)
+#define CSCR_MCU_SEL		(1 << 16)
+#define CSCR_SP_SEL		(1 << 17)
+#define CSCR_MPLL_RESTART	(1 << 18)
+#define CSCR_SPLL_RESTART	(1 << 19)
+#define CSCR_MSHC_SEL		(1 << 20)
+#define CSCR_H264_SEL		(1 << 21)
+#define CSCR_SSI1_SEL		(1 << 22)
+#define CSCR_SSI2_SEL		(1 << 23)
+#define CSCR_SD_CNT
+#define CSCR_USB_DIV
+#define CSCR_UPDATE_DIS		(1 << 31)
+
+#define MPCTL1_BRMO		(1 << 6)
+#define MPCTL1_LF		(1 << 15)
+
+#define PCCR0_SSI2_EN	(1 << 0)
+#define PCCR0_SSI1_EN	(1 << 1)
+#define PCCR0_SLCDC_EN	(1 << 2)
+#define PCCR0_SDHC3_EN	(1 << 3)
+#define PCCR0_SDHC2_EN	(1 << 4)
+#define PCCR0_SDHC1_EN	(1 << 5)
+#define PCCR0_SDC_EN	(1 << 6)
+#define PCCR0_SAHARA_EN	(1 << 7)
+#define PCCR0_RTIC_EN	(1 << 8)
+#define PCCR0_RTC_EN	(1 << 9)
+#define PCCR0_PWM_EN	(1 << 11)
+#define PCCR0_OWIRE_EN	(1 << 12)
+#define PCCR0_MSHC_EN	(1 << 13)
+#define PCCR0_LCDC_EN	(1 << 14)
+#define PCCR0_KPP_EN	(1 << 15)
+#define PCCR0_IIM_EN	(1 << 16)
+#define PCCR0_I2C2_EN	(1 << 17)
+#define PCCR0_I2C1_EN	(1 << 18)
+#define PCCR0_GPT6_EN	(1 << 19)
+#define PCCR0_GPT5_EN	(1 << 20)
+#define PCCR0_GPT4_EN	(1 << 21)
+#define PCCR0_GPT3_EN	(1 << 22)
+#define PCCR0_GPT2_EN	(1 << 23)
+#define PCCR0_GPT1_EN	(1 << 24)
+#define PCCR0_GPIO_EN	(1 << 25)
+#define PCCR0_FEC_EN	(1 << 26)
+#define PCCR0_EMMA_EN	(1 << 27)
+#define PCCR0_DMA_EN	(1 << 28)
+#define PCCR0_CSPI3_EN	(1 << 29)
+#define PCCR0_CSPI2_EN	(1 << 30)
+#define PCCR0_CSPI1_EN	(1 << 31)
+
+#define PCCR1_MSHC_BAUDEN	(1 << 2)
+#define PCCR1_NFC_BAUDEN	(1 << 3)
+#define PCCR1_SSI2_BAUDEN	(1 << 4)
+#define PCCR1_SSI1_BAUDEN	(1 << 5)
+#define PCCR1_H264_BAUDEN	(1 << 6)
+#define PCCR1_PERCLK4_EN	(1 << 7)
+#define PCCR1_PERCLK3_EN	(1 << 8)
+#define PCCR1_PERCLK2_EN	(1 << 9)
+#define PCCR1_PERCLK1_EN	(1 << 10)
+#define PCCR1_HCLK_USB		(1 << 11)
+#define PCCR1_HCLK_SLCDC	(1 << 12)
+#define PCCR1_HCLK_SAHARA	(1 << 13)
+#define PCCR1_HCLK_RTIC		(1 << 14)
+#define PCCR1_HCLK_LCDC		(1 << 15)
+#define PCCR1_HCLK_H264		(1 << 16)
+#define PCCR1_HCLK_FEC		(1 << 17)
+#define PCCR1_HCLK_EMMA		(1 << 18)
+#define PCCR1_HCLK_EMI		(1 << 19)
+#define PCCR1_HCLK_DMA		(1 << 20)
+#define PCCR1_HCLK_CSI		(1 << 21)
+#define PCCR1_HCLK_BROM		(1 << 22)
+#define PCCR1_HCLK_ATA		(1 << 23)
+#define PCCR1_WDT_EN		(1 << 24)
+#define PCCR1_USB_EN		(1 << 25)
+#define PCCR1_UART6_EN		(1 << 26)
+#define PCCR1_UART5_EN		(1 << 27)
+#define PCCR1_UART4_EN		(1 << 28)
+#define PCCR1_UART3_EN		(1 << 29)
+#define PCCR1_UART2_EN		(1 << 30)
+#define PCCR1_UART1_EN		(1 << 31)
+
+/* SDRAM Controller registers bitfields */
+#define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
+#define ESDCTL_BL		(1 << 7)
+#define ESDCTL_FP		(1 << 8)
+#define ESDCTL_PWDT(x)		(((x) & 3) << 10)
+#define ESDCTL_SREFR(x)		(((x) & 7) << 13)
+#define ESDCTL_DSIZ_16_UPPER	(0 << 16)
+#define ESDCTL_DSIZ_16_LOWER	(1 << 16)
+#define ESDCTL_DSIZ_32		(2 << 16)
+#define ESDCTL_COL8		(0 << 20)
+#define ESDCTL_COL9		(1 << 20)
+#define ESDCTL_COL10		(2 << 20)
+#define ESDCTL_ROW11		(0 << 24)
+#define ESDCTL_ROW12		(1 << 24)
+#define ESDCTL_ROW13		(2 << 24)
+#define ESDCTL_ROW14		(3 << 24)
+#define ESDCTL_ROW15		(4 << 24)
+#define ESDCTL_SP		(1 << 27)
+#define ESDCTL_SMODE_NORMAL	(0 << 28)
+#define ESDCTL_SMODE_PRECHARGE	(1 << 28)
+#define ESDCTL_SMODE_AUTO_REF	(2 << 28)
+#define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
+#define ESDCTL_SMODE_MAN_REF	(4 << 28)
+#define ESDCTL_SDE		(1 << 31)
+
+#define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
+#define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
+#define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
+#define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
+#define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
+#define ESDCFG_TWR		(1 << 15)
+#define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
+#define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
+#define ESDCFG_TWTR		(1 << 20)
+#define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
+
+#define ESDMISC_RST		(1 << 1)
+#define ESDMISC_MDDREN		(1 << 2)
+#define ESDMISC_MDDR_DL_RST	(1 << 3)
+#define ESDMISC_MDDR_MDIS	(1 << 4)
+#define ESDMISC_LHD		(1 << 5)
+#define ESDMISC_MA10_SHARE	(1 << 6)
+#define ESDMISC_SDRAM_RDY	(1 << 31)
+
+#define PC5_PF_I2C2_DATA	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
+#define PC6_PF_I2C2_CLK		(GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
+#define PC7_PF_USBOTG_DATA5	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
+#define PC8_PF_USBOTG_DATA6	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
+#define PC9_PF_USBOTG_DATA0	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
+#define PC10_PF_USBOTG_DATA2	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
+#define PC11_PF_USBOTG_DATA1	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
+#define PC12_PF_USBOTG_DATA4	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
+#define PC13_PF_USBOTG_DATA3	(GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
+
+#define PD0_AIN_FEC_TXD0	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
+#define PD1_AIN_FEC_TXD1	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
+#define PD2_AIN_FEC_TXD2	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
+#define PD3_AIN_FEC_TXD3	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
+#define PD4_AOUT_FEC_RX_ER	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
+#define PD5_AOUT_FEC_RXD1	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
+#define PD6_AOUT_FEC_RXD2	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
+#define PD7_AOUT_FEC_RXD3	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
+#define PD8_AF_FEC_MDIO		(GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
+#define PD9_AIN_FEC_MDC		(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
+#define PD10_AOUT_FEC_CRS	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
+#define PD11_AOUT_FEC_TX_CLK	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
+#define PD12_AOUT_FEC_RXD0	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
+#define PD13_AOUT_FEC_RX_DV	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
+#define PD14_AOUT_FEC_CLR	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
+#define PD15_AOUT_FEC_COL	(GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
+#define PD16_AIN_FEC_TX_ER	(GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
+#define PF23_AIN_FEC_TX_EN	(GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
+
+#define PE0_PF_USBOTG_NXT	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
+#define PE1_PF_USBOTG_STP	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
+#define PE2_PF_USBOTG_DIR	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
+#define PE3_PF_UART2_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
+#define PE4_PF_UART2_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 4)
+#define PE6_PF_UART2_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
+#define PE7_PF_UART2_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 7)
+#define PE8_PF_UART3_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
+#define PE9_PF_UART3_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 9)
+#define PE10_PF_UART3_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
+#define PE11_PF_UART3_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 11)
+#define PE12_PF_UART1_TXD	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
+#define PE13_PF_UART1_RXD	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 13)
+#define PE14_PF_UART1_CTS	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
+#define PE15_PF_UART1_RTS	(GPIO_PORTE | GPIO_IN  | GPIO_PF | 15)
+#define PE18_PF_SD1_D0		(GPIO_PORTE | GPIO_PF | 18)
+#define PE19_PF_SD1_D1		(GPIO_PORTE | GPIO_PF | 19)
+#define PE20_PF_SD1_D2		(GPIO_PORTE | GPIO_PF | 20)
+#define PE21_PF_SD1_D3		(GPIO_PORTE | GPIO_PF | 21)
+#define PE22_PF_SD1_CMD		(GPIO_PORTE | GPIO_PF | 22)
+#define PE23_PF_SD1_CLK		(GPIO_PORTE | GPIO_PF | 23)
+#define PB4_PF_SD2_D0		(GPIO_PORTB | GPIO_PF | 4)
+#define PB5_PF_SD2_D1		(GPIO_PORTB | GPIO_PF | 5)
+#define PB6_PF_SD2_D2		(GPIO_PORTB | GPIO_PF | 6)
+#define PB7_PF_SD2_D3		(GPIO_PORTB | GPIO_PF | 7)
+#define PB8_PF_SD2_CMD		(GPIO_PORTB | GPIO_PF | 8)
+#define PB9_PF_SD2_CLK		(GPIO_PORTB | GPIO_PF | 9)
+#define PD17_PF_I2C_DATA	(GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
+#define PD18_PF_I2C_CLK		(GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
+#define PE24_PF_USBOTG_CLK	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
+#define PE25_PF_USBOTG_DATA7	(GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
+
+/* Clocksource Bitfields */
+#define TCTL_SWR	(1 << 15)	/* Software reset */
+#define TCTL_FRR	(1 << 8)	/* Freerun / restart */
+#define TCTL_CAP	(3 << 6)	/* Capture Edge */
+#define TCTL_OM		(1 << 5)	/* output mode */
+#define TCTL_IRQEN	(1 << 4)	/* interrupt enable */
+#define TCTL_CLKSOURCE	1		/* Clock source bit position */
+#define TCTL_TEN	1		/* Timer enable */
+#define TPRER_PRES	0xff		/* Prescale */
+#define TSTAT_CAPT	(1 << 1)	/* Capture event */
+#define TSTAT_COMP	1		/* Compare event */
+
+#define GPIO1_BASE_ADDR 0x10015000
+#define GPIO2_BASE_ADDR 0x10015100
+#define GPIO3_BASE_ADDR 0x10015200
+#define GPIO4_BASE_ADDR 0x10015300
+#define GPIO5_BASE_ADDR 0x10015400
+#define GPIO6_BASE_ADDR 0x10015500
+
+#define GPIO_OUT	(1 << 8)
+#define GPIO_IN		(0 << 8)
+#define GPIO_PUEN	(1 << 9)
+
+#define GPIO_PF		(1 << 10)
+#define GPIO_AF		(1 << 11)
+
+#define GPIO_OCR_SHIFT	12
+#define GPIO_OCR_MASK	(3 << GPIO_OCR_SHIFT)
+#define GPIO_AIN	(0 << GPIO_OCR_SHIFT)
+#define GPIO_BIN	(1 << GPIO_OCR_SHIFT)
+#define GPIO_CIN	(2 << GPIO_OCR_SHIFT)
+#define GPIO_GPIO	(3 << GPIO_OCR_SHIFT)
+
+#define GPIO_AOUT_SHIFT	14
+#define GPIO_AOUT_MASK	(3 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT	(0 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_ISR	(1 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_0	(2 << GPIO_AOUT_SHIFT)
+#define GPIO_AOUT_1	(3 << GPIO_AOUT_SHIFT)
+
+#define GPIO_BOUT_SHIFT	16
+#define GPIO_BOUT_MASK	(3 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT	(0 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_ISR	(1 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_0	(2 << GPIO_BOUT_SHIFT)
+#define GPIO_BOUT_1	(3 << GPIO_BOUT_SHIFT)
+
+#define IIM_STAT_BUSY	(1 << 7)
+#define IIM_STAT_PRGD	(1 << 1)
+#define IIM_STAT_SNSD	(1 << 0)
+#define IIM_ERR_PRGE	(1 << 7)
+#define IIM_ERR_WPE	(1 << 6)
+#define IIM_ERR_OPE	(1 << 5)
+#define IIM_ERR_RPE	(1 << 4)
+#define IIM_ERR_WLRE	(1 << 3)
+#define IIM_ERR_SNSE	(1 << 2)
+#define IIM_ERR_PARITYE	(1 << 1)
+
+#endif				/* _IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx27/mxcmmc.h b/arch/arm/include/asm/arch-mx27/mxcmmc.h
new file mode 100644
index 0000000..d7b5ca2
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx27/mxcmmc.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
+ */
+
+#ifndef ASM_ARCH_MXCMMC_H
+#define ASM_ARCH_MXCMMC_H
+
+int mxc_mmc_init(bd_t *bis);
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx27/regs-rtc.h b/arch/arm/include/asm/arch-mx27/regs-rtc.h
new file mode 100644
index 0000000..d373ab1
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx27/regs-rtc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX27 RTC Register Definitions
+ *
+ * Copyright (C) 2012 Philippe Reynes <tremyfr@yahoo.fr>
+ */
+
+#ifndef __MX27_REGS_RTC_H__
+#define __MX27_REGS_RTC_H__
+
+#ifndef	__ASSEMBLY__
+struct rtc_regs {
+	u32 hourmin;
+	u32 seconds;
+	u32 alrm_hm;
+	u32 alrm_sec;
+	u32 rtcctl;
+	u32 rtcisr;
+	u32 rtcienr;
+	u32 stpwch;
+	u32 dayr;
+	u32 dayalarm;
+};
+#endif /* __ASSEMBLY__*/
+
+#endif	/* __MX28_REGS_RTC_H__ */
diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h
new file mode 100644
index 0000000..aafc2d6
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx31/clock.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+#define MXC_HCLK	CONFIG_MX31_HCLK_FREQ
+
+#define MXC_CLK32	CONFIG_MX31_CLK32
+
+enum mxc_clock {
+	MXC_ARM_CLK,
+	MXC_IPG_CLK,
+	MXC_IPG_PERCLK,
+	MXC_CSPI_CLK,
+	MXC_UART_CLK,
+	MXC_IPU_CLK,
+	MXC_ESDHC_CLK,
+	MXC_I2C_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+extern u32 imx_get_uartclk(void);
+extern void mx31_gpio_mux(unsigned long mode);
+extern void mx31_set_pad(enum iomux_pins pin, u32 config);
+extern void mx31_set_gpr(enum iomux_gp_func gp, char en);
+
+void mx31_uart1_hw_init(void);
+void mx31_uart2_hw_init(void);
+void mx31_spi2_hw_init(void);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx31/gpio.h b/arch/arm/include/asm/arch-mx31/gpio.h
new file mode 100644
index 0000000..45e9fc6
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx31/gpio.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ */
+
+
+#ifndef __ASM_ARCH_MX31_GPIO_H
+#define __ASM_ARCH_MX31_GPIO_H
+
+#include <asm/mach-imx/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
new file mode 100644
index 0000000..9e271d6
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -0,0 +1,926 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ */
+
+#ifndef __ASM_ARCH_MX31_IMX_REGS_H
+#define __ASM_ARCH_MX31_IMX_REGS_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* Clock control module registers */
+struct clock_control_regs {
+	u32 ccmr;
+	u32 pdr0;
+	u32 pdr1;
+	u32 rcsr;
+	u32 mpctl;
+	u32 upctl;
+	u32 spctl;
+	u32 cosr;
+	u32 cgr0;
+	u32 cgr1;
+	u32 cgr2;
+	u32 wimr0;
+	u32 ldc;
+	u32 dcvr0;
+	u32 dcvr1;
+	u32 dcvr2;
+	u32 dcvr3;
+	u32 ltr0;
+	u32 ltr1;
+	u32 ltr2;
+	u32 ltr3;
+	u32 ltbr0;
+	u32 ltbr1;
+	u32 pmcr0;
+	u32 pmcr1;
+	u32 pdr2;
+};
+
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+	u32 test;
+};
+
+/* IIM control registers */
+struct iim_regs {
+	u32 iim_stat;
+	u32 iim_statm;
+	u32 iim_err;
+	u32 iim_emask;
+	u32 iim_fctl;
+	u32 iim_ua;
+	u32 iim_la;
+	u32 iim_sdat;
+	u32 iim_prev;
+	u32 iim_srev;
+	u32 iim_prg_p;
+	u32 iim_scs0;
+	u32 iim_scs1;
+	u32 iim_scs2;
+	u32 iim_scs3;
+	u32 res[0x1f1];
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+		u32 fuse_rsvd[0xe0];
+	} bank[3];
+};
+
+struct fuse_bank0_regs {
+	u32 fuse0_5[6];
+	u32 usr;
+	u32 fuse7_15[9];
+};
+
+struct fuse_bank2_regs {
+	u32 fuse0;
+	u32 uid[8];
+	u32 fuse9_15[7];
+};
+
+struct iomuxc_regs {
+	u32 unused1;
+	u32 unused2;
+	u32 gpr;
+};
+
+struct mx3_cpu_type {
+	u8 srev;
+	u32 v;
+};
+
+#define IOMUX_PADNUM_MASK	0x1ff
+#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
+
+/*
+ * various IOMUX pad functions
+ */
+enum iomux_pad_config {
+	PAD_CTL_NOLOOPBACK	= 0x0 << 9,
+	PAD_CTL_LOOPBACK	= 0x1 << 9,
+	PAD_CTL_PKE_NONE	= 0x0 << 8,
+	PAD_CTL_PKE_ENABLE	= 0x1 << 8,
+	PAD_CTL_PUE_KEEPER	= 0x0 << 7,
+	PAD_CTL_PUE_PUD		= 0x1 << 7,
+	PAD_CTL_100K_PD		= 0x0 << 5,
+	PAD_CTL_100K_PU		= 0x1 << 5,
+	PAD_CTL_47K_PU		= 0x2 << 5,
+	PAD_CTL_22K_PU		= 0x3 << 5,
+	PAD_CTL_HYS_CMOS	= 0x0 << 4,
+	PAD_CTL_HYS_SCHMITZ	= 0x1 << 4,
+	PAD_CTL_ODE_CMOS	= 0x0 << 3,
+	PAD_CTL_ODE_OpenDrain	= 0x1 << 3,
+	PAD_CTL_DRV_NORMAL	= 0x0 << 1,
+	PAD_CTL_DRV_HIGH	= 0x1 << 1,
+	PAD_CTL_DRV_MAX		= 0x2 << 1,
+	PAD_CTL_SRE_SLOW	= 0x0 << 0,
+	PAD_CTL_SRE_FAST	= 0x1 << 0
+};
+
+/*
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+
+enum iomux_pins {
+	MX31_PIN_TTM_PAD	= IOMUX_PIN(0xff,   0),
+	MX31_PIN_CSPI3_SPI_RDY	= IOMUX_PIN(0xff,   1),
+	MX31_PIN_CSPI3_SCLK	= IOMUX_PIN(0xff,   2),
+	MX31_PIN_CSPI3_MISO	= IOMUX_PIN(0xff,   3),
+	MX31_PIN_CSPI3_MOSI	= IOMUX_PIN(0xff,   4),
+	MX31_PIN_CLKSS		= IOMUX_PIN(0xff,   5),
+	MX31_PIN_CE_CONTROL	= IOMUX_PIN(0xff,   6),
+	MX31_PIN_ATA_RESET_B	= IOMUX_PIN(95,     7),
+	MX31_PIN_ATA_DMACK	= IOMUX_PIN(94,     8),
+	MX31_PIN_ATA_DIOW	= IOMUX_PIN(93,     9),
+	MX31_PIN_ATA_DIOR	= IOMUX_PIN(92,    10),
+	MX31_PIN_ATA_CS1	= IOMUX_PIN(91,    11),
+	MX31_PIN_ATA_CS0	= IOMUX_PIN(90,    12),
+	MX31_PIN_SD1_DATA3	= IOMUX_PIN(63,    13),
+	MX31_PIN_SD1_DATA2	= IOMUX_PIN(62,    14),
+	MX31_PIN_SD1_DATA1	= IOMUX_PIN(61,    15),
+	MX31_PIN_SD1_DATA0	= IOMUX_PIN(60,    16),
+	MX31_PIN_SD1_CLK	= IOMUX_PIN(59,    17),
+	MX31_PIN_SD1_CMD	= IOMUX_PIN(58,    18),
+	MX31_PIN_D3_SPL		= IOMUX_PIN(0xff,  19),
+	MX31_PIN_D3_CLS		= IOMUX_PIN(0xff,  20),
+	MX31_PIN_D3_REV		= IOMUX_PIN(0xff,  21),
+	MX31_PIN_CONTRAST	= IOMUX_PIN(0xff,  22),
+	MX31_PIN_VSYNC3		= IOMUX_PIN(0xff,  23),
+	MX31_PIN_READ		= IOMUX_PIN(0xff,  24),
+	MX31_PIN_WRITE		= IOMUX_PIN(0xff,  25),
+	MX31_PIN_PAR_RS		= IOMUX_PIN(0xff,  26),
+	MX31_PIN_SER_RS		= IOMUX_PIN(89,    27),
+	MX31_PIN_LCS1		= IOMUX_PIN(88,    28),
+	MX31_PIN_LCS0		= IOMUX_PIN(87,    29),
+	MX31_PIN_SD_D_CLK	= IOMUX_PIN(86,    30),
+	MX31_PIN_SD_D_IO	= IOMUX_PIN(85,    31),
+	MX31_PIN_SD_D_I		= IOMUX_PIN(84,    32),
+	MX31_PIN_DRDY0		= IOMUX_PIN(0xff,  33),
+	MX31_PIN_FPSHIFT	= IOMUX_PIN(0xff,  34),
+	MX31_PIN_HSYNC		= IOMUX_PIN(0xff,  35),
+	MX31_PIN_VSYNC0		= IOMUX_PIN(0xff,  36),
+	MX31_PIN_LD17		= IOMUX_PIN(0xff,  37),
+	MX31_PIN_LD16		= IOMUX_PIN(0xff,  38),
+	MX31_PIN_LD15		= IOMUX_PIN(0xff,  39),
+	MX31_PIN_LD14		= IOMUX_PIN(0xff,  40),
+	MX31_PIN_LD13		= IOMUX_PIN(0xff,  41),
+	MX31_PIN_LD12		= IOMUX_PIN(0xff,  42),
+	MX31_PIN_LD11		= IOMUX_PIN(0xff,  43),
+	MX31_PIN_LD10		= IOMUX_PIN(0xff,  44),
+	MX31_PIN_LD9		= IOMUX_PIN(0xff,  45),
+	MX31_PIN_LD8		= IOMUX_PIN(0xff,  46),
+	MX31_PIN_LD7		= IOMUX_PIN(0xff,  47),
+	MX31_PIN_LD6		= IOMUX_PIN(0xff,  48),
+	MX31_PIN_LD5		= IOMUX_PIN(0xff,  49),
+	MX31_PIN_LD4		= IOMUX_PIN(0xff,  50),
+	MX31_PIN_LD3		= IOMUX_PIN(0xff,  51),
+	MX31_PIN_LD2		= IOMUX_PIN(0xff,  52),
+	MX31_PIN_LD1		= IOMUX_PIN(0xff,  53),
+	MX31_PIN_LD0		= IOMUX_PIN(0xff,  54),
+	MX31_PIN_USBH2_DATA1	= IOMUX_PIN(0xff,  55),
+	MX31_PIN_USBH2_DATA0	= IOMUX_PIN(0xff,  56),
+	MX31_PIN_USBH2_NXT	= IOMUX_PIN(0xff,  57),
+	MX31_PIN_USBH2_STP	= IOMUX_PIN(0xff,  58),
+	MX31_PIN_USBH2_DIR	= IOMUX_PIN(0xff,  59),
+	MX31_PIN_USBH2_CLK	= IOMUX_PIN(0xff,  60),
+	MX31_PIN_USBOTG_DATA7	= IOMUX_PIN(0xff,  61),
+	MX31_PIN_USBOTG_DATA6	= IOMUX_PIN(0xff,  62),
+	MX31_PIN_USBOTG_DATA5	= IOMUX_PIN(0xff,  63),
+	MX31_PIN_USBOTG_DATA4	= IOMUX_PIN(0xff,  64),
+	MX31_PIN_USBOTG_DATA3	= IOMUX_PIN(0xff,  65),
+	MX31_PIN_USBOTG_DATA2	= IOMUX_PIN(0xff,  66),
+	MX31_PIN_USBOTG_DATA1	= IOMUX_PIN(0xff,  67),
+	MX31_PIN_USBOTG_DATA0	= IOMUX_PIN(0xff,  68),
+	MX31_PIN_USBOTG_NXT	= IOMUX_PIN(0xff,  69),
+	MX31_PIN_USBOTG_STP	= IOMUX_PIN(0xff,  70),
+	MX31_PIN_USBOTG_DIR	= IOMUX_PIN(0xff,  71),
+	MX31_PIN_USBOTG_CLK	= IOMUX_PIN(0xff,  72),
+	MX31_PIN_USB_BYP	= IOMUX_PIN(31,    73),
+	MX31_PIN_USB_OC		= IOMUX_PIN(30,    74),
+	MX31_PIN_USB_PWR	= IOMUX_PIN(29,    75),
+	MX31_PIN_SJC_MOD	= IOMUX_PIN(0xff,  76),
+	MX31_PIN_DE_B		= IOMUX_PIN(0xff,  77),
+	MX31_PIN_TRSTB		= IOMUX_PIN(0xff,  78),
+	MX31_PIN_TDO		= IOMUX_PIN(0xff,  79),
+	MX31_PIN_TDI		= IOMUX_PIN(0xff,  80),
+	MX31_PIN_TMS		= IOMUX_PIN(0xff,  81),
+	MX31_PIN_TCK		= IOMUX_PIN(0xff,  82),
+	MX31_PIN_RTCK		= IOMUX_PIN(0xff,  83),
+	MX31_PIN_KEY_COL7	= IOMUX_PIN(57,    84),
+	MX31_PIN_KEY_COL6	= IOMUX_PIN(56,    85),
+	MX31_PIN_KEY_COL5	= IOMUX_PIN(55,    86),
+	MX31_PIN_KEY_COL4	= IOMUX_PIN(54,    87),
+	MX31_PIN_KEY_COL3	= IOMUX_PIN(0xff,  88),
+	MX31_PIN_KEY_COL2	= IOMUX_PIN(0xff,  89),
+	MX31_PIN_KEY_COL1	= IOMUX_PIN(0xff,  90),
+	MX31_PIN_KEY_COL0	= IOMUX_PIN(0xff,  91),
+	MX31_PIN_KEY_ROW7	= IOMUX_PIN(53,    92),
+	MX31_PIN_KEY_ROW6	= IOMUX_PIN(52,    93),
+	MX31_PIN_KEY_ROW5	= IOMUX_PIN(51,    94),
+	MX31_PIN_KEY_ROW4	= IOMUX_PIN(50,    95),
+	MX31_PIN_KEY_ROW3	= IOMUX_PIN(0xff,  96),
+	MX31_PIN_KEY_ROW2	= IOMUX_PIN(0xff,  97),
+	MX31_PIN_KEY_ROW1	= IOMUX_PIN(0xff,  98),
+	MX31_PIN_KEY_ROW0	= IOMUX_PIN(0xff,  99),
+	MX31_PIN_BATT_LINE	= IOMUX_PIN(49,   100),
+	MX31_PIN_CTS2		= IOMUX_PIN(0xff, 101),
+	MX31_PIN_RTS2		= IOMUX_PIN(0xff, 102),
+	MX31_PIN_TXD2		= IOMUX_PIN(28,   103),
+	MX31_PIN_RXD2		= IOMUX_PIN(27,   104),
+	MX31_PIN_DTR_DCE2	= IOMUX_PIN(48,   105),
+	MX31_PIN_DCD_DTE1	= IOMUX_PIN(47,   106),
+	MX31_PIN_RI_DTE1	= IOMUX_PIN(46,   107),
+	MX31_PIN_DSR_DTE1	= IOMUX_PIN(45,   108),
+	MX31_PIN_DTR_DTE1	= IOMUX_PIN(44,   109),
+	MX31_PIN_DCD_DCE1	= IOMUX_PIN(43,   110),
+	MX31_PIN_RI_DCE1	= IOMUX_PIN(42,   111),
+	MX31_PIN_DSR_DCE1	= IOMUX_PIN(41,   112),
+	MX31_PIN_DTR_DCE1	= IOMUX_PIN(40,   113),
+	MX31_PIN_CTS1		= IOMUX_PIN(39,   114),
+	MX31_PIN_RTS1		= IOMUX_PIN(38,   115),
+	MX31_PIN_TXD1		= IOMUX_PIN(37,   116),
+	MX31_PIN_RXD1		= IOMUX_PIN(36,   117),
+	MX31_PIN_CSPI2_SPI_RDY	= IOMUX_PIN(0xff, 118),
+	MX31_PIN_CSPI2_SCLK	= IOMUX_PIN(0xff, 119),
+	MX31_PIN_CSPI2_SS2	= IOMUX_PIN(0xff, 120),
+	MX31_PIN_CSPI2_SS1	= IOMUX_PIN(0xff, 121),
+	MX31_PIN_CSPI2_SS0	= IOMUX_PIN(0xff, 122),
+	MX31_PIN_CSPI2_MISO	= IOMUX_PIN(0xff, 123),
+	MX31_PIN_CSPI2_MOSI	= IOMUX_PIN(0xff, 124),
+	MX31_PIN_CSPI1_SPI_RDY	= IOMUX_PIN(0xff, 125),
+	MX31_PIN_CSPI1_SCLK	= IOMUX_PIN(0xff, 126),
+	MX31_PIN_CSPI1_SS2	= IOMUX_PIN(0xff, 127),
+	MX31_PIN_CSPI1_SS1	= IOMUX_PIN(0xff, 128),
+	MX31_PIN_CSPI1_SS0	= IOMUX_PIN(0xff, 129),
+	MX31_PIN_CSPI1_MISO	= IOMUX_PIN(0xff, 130),
+	MX31_PIN_CSPI1_MOSI	= IOMUX_PIN(0xff, 131),
+	MX31_PIN_SFS6		= IOMUX_PIN(26,   132),
+	MX31_PIN_SCK6		= IOMUX_PIN(25,   133),
+	MX31_PIN_SRXD6		= IOMUX_PIN(24,   134),
+	MX31_PIN_STXD6		= IOMUX_PIN(23,   135),
+	MX31_PIN_SFS5		= IOMUX_PIN(0xff, 136),
+	MX31_PIN_SCK5		= IOMUX_PIN(0xff, 137),
+	MX31_PIN_SRXD5		= IOMUX_PIN(22,   138),
+	MX31_PIN_STXD5		= IOMUX_PIN(21,   139),
+	MX31_PIN_SFS4		= IOMUX_PIN(0xff, 140),
+	MX31_PIN_SCK4		= IOMUX_PIN(0xff, 141),
+	MX31_PIN_SRXD4		= IOMUX_PIN(20,   142),
+	MX31_PIN_STXD4		= IOMUX_PIN(19,   143),
+	MX31_PIN_SFS3		= IOMUX_PIN(0xff, 144),
+	MX31_PIN_SCK3		= IOMUX_PIN(0xff, 145),
+	MX31_PIN_SRXD3		= IOMUX_PIN(18,   146),
+	MX31_PIN_STXD3		= IOMUX_PIN(17,   147),
+	MX31_PIN_I2C_DAT	= IOMUX_PIN(0xff, 148),
+	MX31_PIN_I2C_CLK	= IOMUX_PIN(0xff, 149),
+	MX31_PIN_CSI_PIXCLK	= IOMUX_PIN(83,   150),
+	MX31_PIN_CSI_HSYNC	= IOMUX_PIN(82,   151),
+	MX31_PIN_CSI_VSYNC	= IOMUX_PIN(81,   152),
+	MX31_PIN_CSI_MCLK	= IOMUX_PIN(80,   153),
+	MX31_PIN_CSI_D15	= IOMUX_PIN(79,   154),
+	MX31_PIN_CSI_D14	= IOMUX_PIN(78,   155),
+	MX31_PIN_CSI_D13	= IOMUX_PIN(77,   156),
+	MX31_PIN_CSI_D12	= IOMUX_PIN(76,   157),
+	MX31_PIN_CSI_D11	= IOMUX_PIN(75,   158),
+	MX31_PIN_CSI_D10	= IOMUX_PIN(74,   159),
+	MX31_PIN_CSI_D9		= IOMUX_PIN(73,   160),
+	MX31_PIN_CSI_D8		= IOMUX_PIN(72,   161),
+	MX31_PIN_CSI_D7		= IOMUX_PIN(71,   162),
+	MX31_PIN_CSI_D6		= IOMUX_PIN(70,   163),
+	MX31_PIN_CSI_D5		= IOMUX_PIN(69,   164),
+	MX31_PIN_CSI_D4		= IOMUX_PIN(68,   165),
+	MX31_PIN_M_GRANT	= IOMUX_PIN(0xff, 166),
+	MX31_PIN_M_REQUEST	= IOMUX_PIN(0xff, 167),
+	MX31_PIN_PC_POE		= IOMUX_PIN(0xff, 168),
+	MX31_PIN_PC_RW_B	= IOMUX_PIN(0xff, 169),
+	MX31_PIN_IOIS16		= IOMUX_PIN(0xff, 170),
+	MX31_PIN_PC_RST		= IOMUX_PIN(0xff, 171),
+	MX31_PIN_PC_BVD2	= IOMUX_PIN(0xff, 172),
+	MX31_PIN_PC_BVD1	= IOMUX_PIN(0xff, 173),
+	MX31_PIN_PC_VS2		= IOMUX_PIN(0xff, 174),
+	MX31_PIN_PC_VS1		= IOMUX_PIN(0xff, 175),
+	MX31_PIN_PC_PWRON	= IOMUX_PIN(0xff, 176),
+	MX31_PIN_PC_READY	= IOMUX_PIN(0xff, 177),
+	MX31_PIN_PC_WAIT_B	= IOMUX_PIN(0xff, 178),
+	MX31_PIN_PC_CD2_B	= IOMUX_PIN(0xff, 179),
+	MX31_PIN_PC_CD1_B	= IOMUX_PIN(0xff, 180),
+	MX31_PIN_D0		= IOMUX_PIN(0xff, 181),
+	MX31_PIN_D1		= IOMUX_PIN(0xff, 182),
+	MX31_PIN_D2		= IOMUX_PIN(0xff, 183),
+	MX31_PIN_D3		= IOMUX_PIN(0xff, 184),
+	MX31_PIN_D4		= IOMUX_PIN(0xff, 185),
+	MX31_PIN_D5		= IOMUX_PIN(0xff, 186),
+	MX31_PIN_D6		= IOMUX_PIN(0xff, 187),
+	MX31_PIN_D7		= IOMUX_PIN(0xff, 188),
+	MX31_PIN_D8		= IOMUX_PIN(0xff, 189),
+	MX31_PIN_D9		= IOMUX_PIN(0xff, 190),
+	MX31_PIN_D10		= IOMUX_PIN(0xff, 191),
+	MX31_PIN_D11		= IOMUX_PIN(0xff, 192),
+	MX31_PIN_D12		= IOMUX_PIN(0xff, 193),
+	MX31_PIN_D13		= IOMUX_PIN(0xff, 194),
+	MX31_PIN_D14		= IOMUX_PIN(0xff, 195),
+	MX31_PIN_D15		= IOMUX_PIN(0xff, 196),
+	MX31_PIN_NFRB		= IOMUX_PIN(16,   197),
+	MX31_PIN_NFCE_B		= IOMUX_PIN(15,   198),
+	MX31_PIN_NFWP_B		= IOMUX_PIN(14,   199),
+	MX31_PIN_NFCLE		= IOMUX_PIN(13,   200),
+	MX31_PIN_NFALE		= IOMUX_PIN(12,   201),
+	MX31_PIN_NFRE_B		= IOMUX_PIN(11,   202),
+	MX31_PIN_NFWE_B		= IOMUX_PIN(10,   203),
+	MX31_PIN_SDQS3		= IOMUX_PIN(0xff, 204),
+	MX31_PIN_SDQS2		= IOMUX_PIN(0xff, 205),
+	MX31_PIN_SDQS1		= IOMUX_PIN(0xff, 206),
+	MX31_PIN_SDQS0		= IOMUX_PIN(0xff, 207),
+	MX31_PIN_SDCLK_B	= IOMUX_PIN(0xff, 208),
+	MX31_PIN_SDCLK		= IOMUX_PIN(0xff, 209),
+	MX31_PIN_SDCKE1		= IOMUX_PIN(0xff, 210),
+	MX31_PIN_SDCKE0		= IOMUX_PIN(0xff, 211),
+	MX31_PIN_SDWE		= IOMUX_PIN(0xff, 212),
+	MX31_PIN_CAS		= IOMUX_PIN(0xff, 213),
+	MX31_PIN_RAS		= IOMUX_PIN(0xff, 214),
+	MX31_PIN_RW		= IOMUX_PIN(0xff, 215),
+	MX31_PIN_BCLK		= IOMUX_PIN(0xff, 216),
+	MX31_PIN_LBA		= IOMUX_PIN(0xff, 217),
+	MX31_PIN_ECB		= IOMUX_PIN(0xff, 218),
+	MX31_PIN_CS5		= IOMUX_PIN(0xff, 219),
+	MX31_PIN_CS4		= IOMUX_PIN(0xff, 220),
+	MX31_PIN_CS3		= IOMUX_PIN(0xff, 221),
+	MX31_PIN_CS2		= IOMUX_PIN(0xff, 222),
+	MX31_PIN_CS1		= IOMUX_PIN(0xff, 223),
+	MX31_PIN_CS0		= IOMUX_PIN(0xff, 224),
+	MX31_PIN_OE		= IOMUX_PIN(0xff, 225),
+	MX31_PIN_EB1		= IOMUX_PIN(0xff, 226),
+	MX31_PIN_EB0		= IOMUX_PIN(0xff, 227),
+	MX31_PIN_DQM3		= IOMUX_PIN(0xff, 228),
+	MX31_PIN_DQM2		= IOMUX_PIN(0xff, 229),
+	MX31_PIN_DQM1		= IOMUX_PIN(0xff, 230),
+	MX31_PIN_DQM0		= IOMUX_PIN(0xff, 231),
+	MX31_PIN_SD31		= IOMUX_PIN(0xff, 232),
+	MX31_PIN_SD30		= IOMUX_PIN(0xff, 233),
+	MX31_PIN_SD29		= IOMUX_PIN(0xff, 234),
+	MX31_PIN_SD28		= IOMUX_PIN(0xff, 235),
+	MX31_PIN_SD27		= IOMUX_PIN(0xff, 236),
+	MX31_PIN_SD26		= IOMUX_PIN(0xff, 237),
+	MX31_PIN_SD25		= IOMUX_PIN(0xff, 238),
+	MX31_PIN_SD24		= IOMUX_PIN(0xff, 239),
+	MX31_PIN_SD23		= IOMUX_PIN(0xff, 240),
+	MX31_PIN_SD22		= IOMUX_PIN(0xff, 241),
+	MX31_PIN_SD21		= IOMUX_PIN(0xff, 242),
+	MX31_PIN_SD20		= IOMUX_PIN(0xff, 243),
+	MX31_PIN_SD19		= IOMUX_PIN(0xff, 244),
+	MX31_PIN_SD18		= IOMUX_PIN(0xff, 245),
+	MX31_PIN_SD17		= IOMUX_PIN(0xff, 246),
+	MX31_PIN_SD16		= IOMUX_PIN(0xff, 247),
+	MX31_PIN_SD15		= IOMUX_PIN(0xff, 248),
+	MX31_PIN_SD14		= IOMUX_PIN(0xff, 249),
+	MX31_PIN_SD13		= IOMUX_PIN(0xff, 250),
+	MX31_PIN_SD12		= IOMUX_PIN(0xff, 251),
+	MX31_PIN_SD11		= IOMUX_PIN(0xff, 252),
+	MX31_PIN_SD10		= IOMUX_PIN(0xff, 253),
+	MX31_PIN_SD9		= IOMUX_PIN(0xff, 254),
+	MX31_PIN_SD8		= IOMUX_PIN(0xff, 255),
+	MX31_PIN_SD7		= IOMUX_PIN(0xff, 256),
+	MX31_PIN_SD6		= IOMUX_PIN(0xff, 257),
+	MX31_PIN_SD5		= IOMUX_PIN(0xff, 258),
+	MX31_PIN_SD4		= IOMUX_PIN(0xff, 259),
+	MX31_PIN_SD3		= IOMUX_PIN(0xff, 260),
+	MX31_PIN_SD2		= IOMUX_PIN(0xff, 261),
+	MX31_PIN_SD1		= IOMUX_PIN(0xff, 262),
+	MX31_PIN_SD0		= IOMUX_PIN(0xff, 263),
+	MX31_PIN_SDBA0		= IOMUX_PIN(0xff, 264),
+	MX31_PIN_SDBA1		= IOMUX_PIN(0xff, 265),
+	MX31_PIN_A25		= IOMUX_PIN(0xff, 266),
+	MX31_PIN_A24		= IOMUX_PIN(0xff, 267),
+	MX31_PIN_A23		= IOMUX_PIN(0xff, 268),
+	MX31_PIN_A22		= IOMUX_PIN(0xff, 269),
+	MX31_PIN_A21		= IOMUX_PIN(0xff, 270),
+	MX31_PIN_A20		= IOMUX_PIN(0xff, 271),
+	MX31_PIN_A19		= IOMUX_PIN(0xff, 272),
+	MX31_PIN_A18		= IOMUX_PIN(0xff, 273),
+	MX31_PIN_A17		= IOMUX_PIN(0xff, 274),
+	MX31_PIN_A16		= IOMUX_PIN(0xff, 275),
+	MX31_PIN_A14		= IOMUX_PIN(0xff, 276),
+	MX31_PIN_A15		= IOMUX_PIN(0xff, 277),
+	MX31_PIN_A13		= IOMUX_PIN(0xff, 278),
+	MX31_PIN_A12		= IOMUX_PIN(0xff, 279),
+	MX31_PIN_A11		= IOMUX_PIN(0xff, 280),
+	MX31_PIN_MA10		= IOMUX_PIN(0xff, 281),
+	MX31_PIN_A10		= IOMUX_PIN(0xff, 282),
+	MX31_PIN_A9		= IOMUX_PIN(0xff, 283),
+	MX31_PIN_A8		= IOMUX_PIN(0xff, 284),
+	MX31_PIN_A7		= IOMUX_PIN(0xff, 285),
+	MX31_PIN_A6		= IOMUX_PIN(0xff, 286),
+	MX31_PIN_A5		= IOMUX_PIN(0xff, 287),
+	MX31_PIN_A4		= IOMUX_PIN(0xff, 288),
+	MX31_PIN_A3		= IOMUX_PIN(0xff, 289),
+	MX31_PIN_A2		= IOMUX_PIN(0xff, 290),
+	MX31_PIN_A1		= IOMUX_PIN(0xff, 291),
+	MX31_PIN_A0		= IOMUX_PIN(0xff, 292),
+	MX31_PIN_VPG1		= IOMUX_PIN(0xff, 293),
+	MX31_PIN_VPG0		= IOMUX_PIN(0xff, 294),
+	MX31_PIN_DVFS1		= IOMUX_PIN(0xff, 295),
+	MX31_PIN_DVFS0		= IOMUX_PIN(0xff, 296),
+	MX31_PIN_VSTBY		= IOMUX_PIN(0xff, 297),
+	MX31_PIN_POWER_FAIL	= IOMUX_PIN(0xff, 298),
+	MX31_PIN_CKIL		= IOMUX_PIN(0xff, 299),
+	MX31_PIN_BOOT_MODE4	= IOMUX_PIN(0xff, 300),
+	MX31_PIN_BOOT_MODE3	= IOMUX_PIN(0xff, 301),
+	MX31_PIN_BOOT_MODE2	= IOMUX_PIN(0xff, 302),
+	MX31_PIN_BOOT_MODE1	= IOMUX_PIN(0xff, 303),
+	MX31_PIN_BOOT_MODE0	= IOMUX_PIN(0xff, 304),
+	MX31_PIN_CLKO		= IOMUX_PIN(0xff, 305),
+	MX31_PIN_POR_B		= IOMUX_PIN(0xff, 306),
+	MX31_PIN_RESET_IN_B	= IOMUX_PIN(0xff, 307),
+	MX31_PIN_CKIH		= IOMUX_PIN(0xff, 308),
+	MX31_PIN_SIMPD0		= IOMUX_PIN(35,   309),
+	MX31_PIN_SRX0		= IOMUX_PIN(34,   310),
+	MX31_PIN_STX0		= IOMUX_PIN(33,   311),
+	MX31_PIN_SVEN0		= IOMUX_PIN(32,   312),
+	MX31_PIN_SRST0		= IOMUX_PIN(67,   313),
+	MX31_PIN_SCLK0		= IOMUX_PIN(66,   314),
+	MX31_PIN_GPIO3_1	= IOMUX_PIN(65,   315),
+	MX31_PIN_GPIO3_0	= IOMUX_PIN(64,   316),
+	MX31_PIN_GPIO1_6	= IOMUX_PIN(6,    317),
+	MX31_PIN_GPIO1_5	= IOMUX_PIN(5,    318),
+	MX31_PIN_GPIO1_4	= IOMUX_PIN(4,    319),
+	MX31_PIN_GPIO1_3	= IOMUX_PIN(3,    320),
+	MX31_PIN_GPIO1_2	= IOMUX_PIN(2,    321),
+	MX31_PIN_GPIO1_1	= IOMUX_PIN(1,    322),
+	MX31_PIN_GPIO1_0	= IOMUX_PIN(0,    323),
+	MX31_PIN_PWMO		= IOMUX_PIN(9,    324),
+	MX31_PIN_WATCHDOG_RST	= IOMUX_PIN(0xff, 325),
+	MX31_PIN_COMPARE	= IOMUX_PIN(8,    326),
+	MX31_PIN_CAPTURE	= IOMUX_PIN(7,    327),
+};
+
+/*
+ * various IOMUX general purpose functions
+ */
+enum iomux_gp_func {
+	MUX_PGP_FIRI			= 1 << 0,
+	MUX_DDR_MODE			= 1 << 1,
+	MUX_PGP_CSPI_BB			= 1 << 2,
+	MUX_PGP_ATA_1			= 1 << 3,
+	MUX_PGP_ATA_2			= 1 << 4,
+	MUX_PGP_ATA_3			= 1 << 5,
+	MUX_PGP_ATA_4			= 1 << 6,
+	MUX_PGP_ATA_5			= 1 << 7,
+	MUX_PGP_ATA_6			= 1 << 8,
+	MUX_PGP_ATA_7			= 1 << 9,
+	MUX_PGP_ATA_8			= 1 << 10,
+	MUX_PGP_UH2			= 1 << 11,
+	MUX_SDCTL_CSD0_SEL		= 1 << 12,
+	MUX_SDCTL_CSD1_SEL		= 1 << 13,
+	MUX_CSPI1_UART3			= 1 << 14,
+	MUX_EXTDMAREQ2_MBX_SEL		= 1 << 15,
+	MUX_TAMPER_DETECT_EN		= 1 << 16,
+	MUX_PGP_USB_4WIRE		= 1 << 17,
+	MUX_PGP_USB_COMMON		= 1 << 18,
+	MUX_SDHC_MEMSTICK1		= 1 << 19,
+	MUX_SDHC_MEMSTICK2		= 1 << 20,
+	MUX_PGP_SPLL_BYP		= 1 << 21,
+	MUX_PGP_UPLL_BYP		= 1 << 22,
+	MUX_PGP_MSHC1_CLK_SEL		= 1 << 23,
+	MUX_PGP_MSHC2_CLK_SEL		= 1 << 24,
+	MUX_CSPI3_UART5_SEL		= 1 << 25,
+	MUX_PGP_ATA_9			= 1 << 26,
+	MUX_PGP_USB_SUSPEND		= 1 << 27,
+	MUX_PGP_USB_OTG_LOOPBACK	= 1 << 28,
+	MUX_PGP_USB_HS1_LOOPBACK	= 1 << 29,
+	MUX_PGP_USB_HS2_LOOPBACK	= 1 << 30,
+	MUX_CLKO_DDR_MODE		= 1 << 31,
+};
+
+/* Bit definitions for RCSR register in CCM */
+#define CCM_RCSR_NF16B	(1 << 31)
+#define CCM_RCSR_NFMS	(1 << 30)
+
+/* WEIM CS control registers */
+struct mx31_weim_cscr {
+	u32 upper;
+	u32 lower;
+	u32 additional;
+	u32 reserved;
+};
+
+struct mx31_weim {
+	struct mx31_weim_cscr cscr[6];
+};
+
+/* ESD control registers */
+struct esdc_regs {
+	u32 ctl0;
+	u32 cfg0;
+	u32 ctl1;
+	u32 cfg1;
+	u32 misc;
+	u32 dly[5];
+	u32 dlyl;
+};
+
+#endif
+
+#define ARCH_MXC
+
+#define __REG(x)     (*((volatile u32 *)(x)))
+#define __REG16(x)   (*((volatile u16 *)(x)))
+#define __REG8(x)    (*((volatile u8 *)(x)))
+
+#define CCM_BASE	0x53f80000
+#define CCM_CCMR	(CCM_BASE + 0x00)
+#define CCM_PDR0	(CCM_BASE + 0x04)
+#define CCM_PDR1	(CCM_BASE + 0x08)
+#define CCM_RCSR	(CCM_BASE + 0x0c)
+#define CCM_MPCTL	(CCM_BASE + 0x10)
+#define CCM_UPCTL	(CCM_BASE + 0x14)
+#define CCM_SPCTL	(CCM_BASE + 0x18)
+#define CCM_COSR	(CCM_BASE + 0x1C)
+#define CCM_CGR0	(CCM_BASE + 0x20)
+#define CCM_CGR1	(CCM_BASE + 0x24)
+#define CCM_CGR2	(CCM_BASE + 0x28)
+
+#define CCMR_MDS	(1 << 7)
+#define CCMR_SBYCS	(1 << 4)
+#define CCMR_MPE	(1 << 3)
+#define CCMR_PRCS_MASK	(3 << 1)
+#define CCMR_FPM	(1 << 1)
+#define CCMR_CKIH	(2 << 1)
+
+#define MX31_IIM_BASE_ADDR	0x5001C000
+#define IIM_BASE_ADDR		MX31_IIM_BASE_ADDR
+
+#define PDR0_CSI_PODF(x)	(((x) & 0x3f) << 26)
+#define PDR0_CSI_PRDF(x)	(((x) & 0x7) << 23)
+#define PDR0_PER_PODF(x)	(((x) & 0x1f) << 16)
+#define PDR0_HSP_PODF(x)	(((x) & 0x7) << 11)
+#define PDR0_NFC_PODF(x)	(((x) & 0x7) << 8)
+#define PDR0_IPG_PODF(x)	(((x) & 0x3) << 6)
+#define PDR0_MAX_PODF(x)	(((x) & 0x7) << 3)
+#define PDR0_MCU_PODF(x)	((x) & 0x7)
+
+#define PDR1_USB_PRDF(x)	(((x) & 0x3) << 30)
+#define PDR1_USB_PODF(x)	(((x) & 0x7) << 27)
+#define PDR1_FIRI_PRDF(x)	(((x) & 0x7) << 24)
+#define PDR1_FIRI_PODF(x)	(((x) & 0x3f) << 18)
+#define PDR1_SSI2_PRDF(x)	(((x) & 0x7) << 15)
+#define PDR1_SSI2_PODF(x)	(((x) & 0x3f) << 9)
+#define PDR1_SSI1_PRDF(x)	(((x) & 0x7) << 6)
+#define PDR1_SSI1_PODF(x)	((x) & 0x3f)
+
+#define PLL_BRMO(x)		(((x) & 0x1) << 31)
+#define PLL_PD(x)		(((x) & 0xf) << 26)
+#define PLL_MFD(x)		(((x) & 0x3ff) << 16)
+#define PLL_MFI(x)		(((x) & 0xf) << 10)
+#define PLL_MFN(x)		(((x) & 0x3ff) << 0)
+
+#define GET_PDR0_CSI_PODF(x)	(((x) >> 26) & 0x3f)
+#define GET_PDR0_CSI_PRDF(x)	(((x) >> 23) & 0x7)
+#define GET_PDR0_PER_PODF(x)	(((x) >> 16) & 0x1f)
+#define GET_PDR0_HSP_PODF(x)	(((x) >> 11) & 0x7)
+#define GET_PDR0_NFC_PODF(x)	(((x) >> 8) & 0x7)
+#define GET_PDR0_IPG_PODF(x)	(((x) >> 6) & 0x3)
+#define GET_PDR0_MAX_PODF(x)	(((x) >> 3) & 0x7)
+#define GET_PDR0_MCU_PODF(x)	((x) & 0x7)
+
+#define GET_PLL_PD(x)		(((x) >> 26) & 0xf)
+#define GET_PLL_MFD(x)		(((x) >> 16) & 0x3ff)
+#define GET_PLL_MFI(x)		(((x) >> 10) & 0xf)
+#define GET_PLL_MFN(x)		(((x) >> 0) & 0x3ff)
+
+
+#define WEIM_ESDCTL0	0xB8001000
+#define WEIM_ESDCFG0	0xB8001004
+#define WEIM_ESDCTL1	0xB8001008
+#define WEIM_ESDCFG1	0xB800100C
+#define WEIM_ESDMISC	0xB8001010
+
+#define UART1_BASE	0x43F90000
+#define UART2_BASE	0x43F94000
+#define UART3_BASE	0x5000C000
+#define UART4_BASE	0x43FB0000
+#define UART5_BASE	0x43FB4000
+
+#define I2C1_BASE_ADDR          0x43f80000
+#define I2C1_CLK_OFFSET		26
+#define I2C2_BASE_ADDR          0x43F98000
+#define I2C2_CLK_OFFSET		28
+#define I2C3_BASE_ADDR          0x43f84000
+#define I2C3_CLK_OFFSET		30
+
+#define ESDCTL_SDE			(1 << 31)
+#define ESDCTL_CMD_RW			(0 << 28)
+#define ESDCTL_CMD_PRECHARGE		(1 << 28)
+#define ESDCTL_CMD_AUTOREFRESH		(2 << 28)
+#define ESDCTL_CMD_LOADMODEREG		(3 << 28)
+#define ESDCTL_CMD_MANUALREFRESH	(4 << 28)
+#define ESDCTL_ROW_13			(2 << 24)
+#define ESDCTL_ROW(x)			((x) << 24)
+#define ESDCTL_COL_9			(1 << 20)
+#define ESDCTL_COL(x)			((x) << 20)
+#define ESDCTL_DSIZ(x)			((x) << 16)
+#define ESDCTL_SREFR(x)			((x) << 13)
+#define ESDCTL_PWDT(x)			((x) << 10)
+#define ESDCTL_FP(x)			((x) << 8)
+#define ESDCTL_BL(x)			((x) << 7)
+#define ESDCTL_PRCT(x)			((x) << 0)
+
+#define ESDCTL_BASE_ADDR	0xB8001000
+
+/* 13 fields of the upper CS control register */
+#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
+		cnc, wsc, ew, wws, edc) \
+	((sp) << 31 | (wp) << 30 | (bcd) << 28 | (psz) << 22 | (pme) << 21 |\
+	 (sync) << 20 | (dol) << 16 | (cnc) << 14 | (wsc) << 8 | (ew) << 7 |\
+	 (wws) << 4 | (edc) << 0)
+/* 12 fields of the lower CS control register */
+#define CSCR_L(oea, oen, ebwa, ebwn, \
+		csa, ebc, dsz, csn, psr, cre, wrap, csen) \
+	((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
+	 (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
+	 (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
+/* 14 fields of the additional CS control register */
+#define CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
+		wwu, age, cnc2, fce) \
+	((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
+	 (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
+	 (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
+	 (age) << 2 | (cnc2) << 1 | (fce) << 0)
+
+#define WEIM_BASE	0xb8002000
+
+#define IOMUXC_BASE	0x43FAC000
+#define IOMUXC_SW_MUX_CTL(x)	(IOMUXC_BASE + 0xc + (x) * 4)
+#define IOMUXC_SW_PAD_CTL(x)	(IOMUXC_BASE + 0x154 + (x) * 4)
+
+#define IPU_BASE		0x53fc0000
+#define IPU_CONF		IPU_BASE
+
+#define IPU_CONF_PXL_ENDIAN	(1<<8)
+#define IPU_CONF_DU_EN		(1<<7)
+#define IPU_CONF_DI_EN		(1<<6)
+#define IPU_CONF_ADC_EN		(1<<5)
+#define IPU_CONF_SDC_EN		(1<<4)
+#define IPU_CONF_PF_EN		(1<<3)
+#define IPU_CONF_ROT_EN		(1<<2)
+#define IPU_CONF_IC_EN		(1<<1)
+#define IPU_CONF_CSI_EN		(1<<0)
+
+#define ARM_PPMRR		0x40000015
+
+#define WDOG1_BASE_ADDR		0x53FDC000
+
+/*
+ * GPIO
+ */
+#define GPIO1_BASE_ADDR	0x53FCC000
+#define GPIO2_BASE_ADDR	0x53FD0000
+#define GPIO3_BASE_ADDR	0x53FA4000
+#define GPIO_DR		0x00000000	/* data register */
+#define GPIO_GDIR	0x00000004	/* direction register */
+#define GPIO_PSR	0x00000008	/* pad status register */
+
+/*
+ * Signal Multiplexing (IOMUX)
+ */
+
+/* bits in the SW_MUX_CTL registers */
+#define MUX_CTL_OUT_GPIO_DR	(0 << 4)
+#define MUX_CTL_OUT_FUNC	(1 << 4)
+#define MUX_CTL_OUT_ALT1	(2 << 4)
+#define MUX_CTL_OUT_ALT2	(3 << 4)
+#define MUX_CTL_OUT_ALT3	(4 << 4)
+#define MUX_CTL_OUT_ALT4	(5 << 4)
+#define MUX_CTL_OUT_ALT5	(6 << 4)
+#define MUX_CTL_OUT_ALT6	(7 << 4)
+#define MUX_CTL_IN_NONE		(0 << 0)
+#define MUX_CTL_IN_GPIO		(1 << 0)
+#define MUX_CTL_IN_FUNC		(2 << 0)
+#define MUX_CTL_IN_ALT1		(4 << 0)
+#define MUX_CTL_IN_ALT2		(8 << 0)
+
+#define MUX_CTL_FUNC		(MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
+#define MUX_CTL_ALT1		(MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
+#define MUX_CTL_ALT2		(MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
+#define MUX_CTL_GPIO		(MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
+
+/* Register offsets based on IOMUXC_BASE */
+/* 0x00 .. 0x7b */
+#define MUX_CTL_CSPI3_MISO		0x0c
+#define MUX_CTL_CSPI3_SCLK		0x0d
+#define MUX_CTL_CSPI3_SPI_RDY	0x0e
+#define MUX_CTL_CSPI3_MOSI		0x13
+
+#define MUX_CTL_SD1_DATA1	0x18
+#define MUX_CTL_SD1_DATA2	0x19
+#define MUX_CTL_SD1_DATA3	0x1a
+#define MUX_CTL_SD1_CMD		0x1d
+#define MUX_CTL_SD1_CLK		0x1e
+#define MUX_CTL_SD1_DATA0	0x1f
+
+#define MUX_CTL_USBH2_DATA1	0x40
+#define MUX_CTL_USBH2_DIR	0x44
+#define MUX_CTL_USBH2_STP	0x45
+#define MUX_CTL_USBH2_NXT	0x46
+#define MUX_CTL_USBH2_DATA0	0x47
+#define MUX_CTL_USBH2_CLK	0x4B
+
+#define MUX_CTL_TXD2		0x70
+#define MUX_CTL_RTS2		0x71
+#define MUX_CTL_CTS2		0x72
+#define MUX_CTL_RXD2		0x77
+
+#define MUX_CTL_RTS1		0x7c
+#define MUX_CTL_CTS1		0x7d
+#define MUX_CTL_DTR_DCE1	0x7e
+#define MUX_CTL_DSR_DCE1	0x7f
+#define MUX_CTL_CSPI2_SCLK	0x80
+#define MUX_CTL_CSPI2_SPI_RDY	0x81
+#define MUX_CTL_RXD1		0x82
+#define MUX_CTL_TXD1		0x83
+#define MUX_CTL_CSPI2_MISO	0x84
+#define MUX_CTL_CSPI2_SS0	0x85
+#define MUX_CTL_CSPI2_SS1	0x86
+#define MUX_CTL_CSPI2_SS2	0x87
+#define MUX_CTL_CSPI1_SS2	0x88
+#define MUX_CTL_CSPI1_SCLK	0x89
+#define MUX_CTL_CSPI1_SPI_RDY	0x8a
+#define MUX_CTL_CSPI2_MOSI	0x8b
+#define MUX_CTL_CSPI1_MOSI	0x8c
+#define MUX_CTL_CSPI1_MISO	0x8d
+#define MUX_CTL_CSPI1_SS0	0x8e
+#define MUX_CTL_CSPI1_SS1	0x8f
+#define MUX_CTL_STXD6		0x90
+#define MUX_CTL_SRXD6		0x91
+#define MUX_CTL_SCK6		0x92
+#define MUX_CTL_SFS6		0x93
+
+#define MUX_CTL_STXD3		0x9C
+#define MUX_CTL_SRXD3		0x9D
+#define MUX_CTL_SCK3		0x9E
+#define MUX_CTL_SFS3		0x9F
+
+#define MUX_CTL_NFC_WP		0xD0
+#define MUX_CTL_NFC_CE		0xD1
+#define MUX_CTL_NFC_RB		0xD2
+#define MUX_CTL_NFC_WE		0xD4
+#define MUX_CTL_NFC_RE		0xD5
+#define MUX_CTL_NFC_ALE		0xD6
+#define MUX_CTL_NFC_CLE		0xD7
+
+
+#define MUX_CTL_CAPTURE		0x150
+#define MUX_CTL_COMPARE		0x151
+
+/*
+ * Helper macros for the MUX_[contact name]__[pin function] macros
+ */
+#define IOMUX_MODE_POS 9
+#define IOMUX_MODE(contact, mode) (((mode) << IOMUX_MODE_POS) | (contact))
+
+/*
+ * These macros can be used in mx31_gpio_mux() and have the form
+ * MUX_[contact name]__[pin function]
+ */
+#define MUX_RXD1__UART1_RXD_MUX	IOMUX_MODE(MUX_CTL_RXD1, MUX_CTL_FUNC)
+#define MUX_TXD1__UART1_TXD_MUX	IOMUX_MODE(MUX_CTL_TXD1, MUX_CTL_FUNC)
+#define MUX_RTS1__UART1_RTS_B	IOMUX_MODE(MUX_CTL_RTS1, MUX_CTL_FUNC)
+#define MUX_CTS1__UART1_CTS_B	IOMUX_MODE(MUX_CTL_CTS1, MUX_CTL_FUNC)
+
+#define MUX_RXD2__UART2_RXD_MUX	IOMUX_MODE(MUX_CTL_RXD2, MUX_CTL_FUNC)
+#define MUX_TXD2__UART2_TXD_MUX	IOMUX_MODE(MUX_CTL_TXD2, MUX_CTL_FUNC)
+#define MUX_RTS2__UART2_RTS_B	IOMUX_MODE(MUX_CTL_RTS2, MUX_CTL_FUNC)
+#define MUX_CTS2__UART2_CTS_B	IOMUX_MODE(MUX_CTL_CTS2, MUX_CTL_FUNC)
+
+#define MUX_CSPI2_SS0__CSPI2_SS0_B IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_FUNC)
+#define MUX_CSPI2_SS1__CSPI2_SS1_B IOMUX_MODE(MUX_CTL_CSPI2_SS1, MUX_CTL_FUNC)
+#define MUX_CSPI2_SS2__CSPI2_SS2_B IOMUX_MODE(MUX_CTL_CSPI2_SS2, MUX_CTL_FUNC)
+#define MUX_CSPI2_MOSI__CSPI2_MOSI IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_FUNC)
+#define MUX_CSPI2_MISO__CSPI2_MISO IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_FUNC)
+#define MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B \
+	IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
+#define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
+
+#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
+#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
+#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
+#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
+	IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
+#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
+
+#define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
+#define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
+
+/* PAD control registers for SDR/DDR */
+#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B	(IOMUXC_BASE + 0x26C)
+#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0	(IOMUXC_BASE + 0x270)
+#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS		(IOMUXC_BASE + 0x274)
+#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA		(IOMUXC_BASE + 0x278)
+#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4		(IOMUXC_BASE + 0x27C)
+#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1		(IOMUXC_BASE + 0x280)
+#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1		(IOMUXC_BASE + 0x284)
+#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2	(IOMUXC_BASE + 0x288)
+#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31	(IOMUXC_BASE + 0x28C)
+#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28	(IOMUXC_BASE + 0x290)
+#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25	(IOMUXC_BASE + 0x294)
+#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22	(IOMUXC_BASE + 0x298)
+#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19	(IOMUXC_BASE + 0x29C)
+#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16	(IOMUXC_BASE + 0x2A0)
+#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13	(IOMUXC_BASE + 0x2A4)
+#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10		(IOMUXC_BASE + 0x2A8)
+#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7		(IOMUXC_BASE + 0x2AC)
+#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4		(IOMUXC_BASE + 0x2B0)
+#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1		(IOMUXC_BASE + 0x2B4)
+#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1		(IOMUXC_BASE + 0x2B8)
+#define IOMUXC_SW_PAD_CTL_A21_A22_A23		(IOMUXC_BASE + 0x2BC)
+#define IOMUXC_SW_PAD_CTL_A18_A19_A20		(IOMUXC_BASE + 0x2C0)
+#define IOMUXC_SW_PAD_CTL_A15_A16_A17		(IOMUXC_BASE + 0x2C4)
+#define IOMUXC_SW_PAD_CTL_A12_A13_A14		(IOMUXC_BASE + 0x2C8)
+#define IOMUXC_SW_PAD_CTL_A10_MA10_A11		(IOMUXC_BASE + 0x2CC)
+#define IOMUXC_SW_PAD_CTL_A7_A8_A9		(IOMUXC_BASE + 0x2D0)
+#define IOMUXC_SW_PAD_CTL_A4_A5_A6		(IOMUXC_BASE + 0x2D4)
+#define IOMUXC_SW_PAD_CTL_A1_A2_A3		(IOMUXC_BASE + 0x2D8)
+#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0		(IOMUXC_BASE + 0x2DC)
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE	0x70000000
+#define CSD0_BASE	0x80000000
+#define CSD1_BASE	0x90000000
+#define CS0_BASE	0xA0000000
+#define CS1_BASE	0xA8000000
+#define CS2_BASE	0xB0000000
+#define CS3_BASE	0xB2000000
+#define CS4_BASE	0xB4000000
+#define CS4_PSRAM_BASE	0xB5000000
+#define CS5_BASE	0xB6000000
+#define PCMCIA_MEM_BASE	0xC0000000
+
+/*
+ * NAND controller
+ */
+#define NFC_BASE_ADDR	0xB8000000
+
+/* SD card controller */
+#define SDHC1_BASE_ADDR	0x50004000
+#define SDHC2_BASE_ADDR	0x50008000
+
+/*
+ * Internal RAM (16KB)
+ */
+#define	IRAM_BASE_ADDR	0x1FFFC000
+#define IRAM_SIZE	(16 * 1024)
+
+#define MX31_AIPS1_BASE_ADDR	0x43f00000
+#define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_PORT_OFFSET	0x200
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_SMC	(1 << 3)
+#define MXC_CSPICTRL_POL	(1 << 4)
+#define MXC_CSPICTRL_PHA	(1 << 5)
+#define MXC_CSPICTRL_SSCTL	(1 << 6)
+#define MXC_CSPICTRL_SSPOL	(1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC		(1 << 8)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPICTRL_MAXBITS	0x1f
+
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	4
+
+
+#define MXC_SPI_BASE_ADDRESSES \
+	0x43fa4000, \
+	0x50010000, \
+	0x53f84000,
+
+/*
+ * Generic timer support
+ */
+#ifdef CONFIG_MX31_CLK32
+#define	CONFIG_SYS_TIMER_RATE	CONFIG_MX31_CLK32
+#else
+#define	CONFIG_SYS_TIMER_RATE	32768
+#endif
+
+#endif /* __ASM_ARCH_MX31_IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx31/sys_proto.h b/arch/arm/include/asm/arch-mx31/sys_proto.h
new file mode 100644
index 0000000..e408788
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx31/sys_proto.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at
+ */
+
+#ifndef _MX31_SYS_PROTO_H_
+#define _MX31_SYS_PROTO_H_
+
+#include <asm/mach-imx/sys_proto.h>
+
+struct mxc_weimcs {
+	u32 upper;
+	u32 lower;
+	u32 additional;
+};
+
+void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs);
+int mxc_mmc_init(bd_t *bis);
+#endif
diff --git a/arch/arm/include/asm/arch-mx35/clock.h b/arch/arm/include/asm/arch-mx35/clock.h
new file mode 100644
index 0000000..7885340
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/clock.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+#ifdef CONFIG_MX35_HCLK_FREQ
+#define MXC_HCLK	CONFIG_MX35_HCLK_FREQ
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_MX35_CLK32
+#define MXC_CLK32	CONFIG_MX35_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
+enum mxc_clock {
+	MXC_ARM_CLK,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_IPG_PERCLK,
+	MXC_UART_CLK,
+	MXC_ESDHC1_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_USB_CLK,
+	MXC_CSPI_CLK,
+	MXC_FEC_CLK,
+	MXC_I2C_CLK,
+};
+
+enum mxc_main_clock {
+	CPU_CLK,
+	AHB_CLK,
+	IPG_CLK,
+	IPG_PER_CLK,
+	NFC_CLK,
+	USB_CLK,
+	HSP_CLK,
+};
+
+enum mxc_peri_clock {
+	UART1_BAUD,
+	UART2_BAUD,
+	UART3_BAUD,
+	SSI1_BAUD,
+	SSI2_BAUD,
+	CSI_BAUD,
+	MSHC_CLK,
+	ESDHC1_CLK,
+	ESDHC2_CLK,
+	ESDHC3_CLK,
+	SPDIF_CLK,
+	SPI1_CLK,
+	SPI2_CLK,
+};
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h
new file mode 100644
index 0000000..fc65a3a
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/crm_regs.h
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__
+#define __CPU_ARM1136_MX35_CRM_REGS_H__
+
+/* Register bit definitions */
+#define MXC_CCM_CCMR_WFI                        (1 << 30)
+#define MXC_CCM_CCMR_STBY_EXIT_SRC              (1 << 29)
+#define MXC_CCM_CCMR_VSTBY                      (1 << 28)
+#define MXC_CCM_CCMR_WBEN                       (1 << 27)
+#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET        20
+#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK          (0xF << 20)
+#define MXC_CCM_CCMR_ROMW_OFFSET               18
+#define MXC_CCM_CCMR_ROMW_MASK                 (0x3 << 18)
+#define MXC_CCM_CCMR_RAMW_OFFSET               16
+#define MXC_CCM_CCMR_RAMW_MASK                 (0x3 << 16)
+#define MXC_CCM_CCMR_LPM_OFFSET                 14
+#define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
+#define MXC_CCM_CCMR_UPE                        (1 << 9)
+#define MXC_CCM_CCMR_MPE                        (1 << 3)
+
+#define MXC_CCM_PDR0_PER_SEL			(1 << 26)
+#define MXC_CCM_PDR0_IPU_HND_BYP                (1 << 23)
+#define MXC_CCM_PDR0_HSP_PODF_OFFSET            20
+#define MXC_CCM_PDR0_HSP_PODF_MASK              (0x3 << 20)
+#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET		16
+#define MXC_CCM_PDR0_CON_MUX_DIV_MASK           (0xF << 16)
+#define MXC_CCM_PDR0_CKIL_SEL			(1 << 15)
+#define MXC_CCM_PDR0_PER_PODF_OFFSET            12
+#define MXC_CCM_PDR0_PER_PODF_MASK              (0x7 << 12)
+#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET        9
+#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK          (0x7 << 9)
+#define MXC_CCM_PDR0_AUTO_CON	                0x1
+
+#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET           28
+#define MXC_CCM_PDR1_MSHC_PRDF_MASK             (0x7 << 28)
+#define MXC_CCM_PDR1_MSHC_PODF_OFFSET           22
+#define MXC_CCM_PDR1_MSHC_PODF_MASK             (0x3F << 22)
+#define MXC_CCM_PDR1_MSHC_M_U			(1 << 7)
+
+#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET           27
+#define MXC_CCM_PDR2_SSI2_PRDF_MASK             (0x7 << 27)
+#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET           24
+#define MXC_CCM_PDR2_SSI1_PRDF_MASK             (0x7 << 24)
+#define MXC_CCM_PDR2_CSI_PODF_OFFSET            16
+#define MXC_CCM_PDR2_CSI_PODF_MASK              (0x3F << 16)
+#define MXC_CCM_PDR2_SSI2_PODF_OFFSET           8
+#define MXC_CCM_PDR2_SSI2_PODF_MASK             (0x3F << 8)
+#define MXC_CCM_PDR2_CSI_M_U			(1 << 7)
+#define MXC_CCM_PDR2_SSI_M_U			(1 << 6)
+#define MXC_CCM_PDR2_SSI1_PODF_OFFSET           0
+#define MXC_CCM_PDR2_SSI1_PODF_MASK             (0x3F)
+
+#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET          29
+#define MXC_CCM_PDR3_SPDIF_PRDF_MASK            (0x7 << 29)
+#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET          23
+#define MXC_CCM_PDR3_SPDIF_PODF_MASK            (0x3F << 23)
+#define MXC_CCM_PDR3_SPDIF_M_U			(1 << 22)
+#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET         16
+#define MXC_CCM_PDR3_ESDHC3_PODF_MASK           (0x3F << 16)
+#define MXC_CCM_PDR3_UART_M_U			(1 << 14)
+#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET         8
+#define MXC_CCM_PDR3_ESDHC2_PODF_MASK           (0x3F << 8)
+#define MXC_CCM_PDR3_ESDHC_M_U			(1 << 6)
+#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET         0
+#define MXC_CCM_PDR3_ESDHC1_PODF_MASK           (0x3F)
+
+#define MXC_CCM_PDR4_NFC_PODF_OFFSET		28
+#define MXC_CCM_PDR4_NFC_PODF_MASK		(0xF << 28)
+#define MXC_CCM_PDR4_USB_PODF_OFFSET		22
+#define MXC_CCM_PDR4_USB_PODF_MASK		(0x3F << 22)
+#define MXC_CCM_PDR4_PER0_PODF_OFFSET		16
+#define MXC_CCM_PDR4_PER0_PODF_MASK		(0x3F << 16)
+#define MXC_CCM_PDR4_UART_PODF_OFFSET		10
+#define MXC_CCM_PDR4_UART_PODF_MASK		(0x3F << 10)
+#define MXC_CCM_PDR4_USB_M_U			(1 << 9)
+
+/* Bit definitions for RCSR */
+#define MXC_CCM_RCSR_BUS_WIDTH			(1 << 29)
+#define MXC_CCM_RCSR_BUS_16BIT			(1 << 29)
+#define MXC_CCM_RCSR_PAGE_SIZE			(3 << 27)
+#define MXC_CCM_RCSR_PAGE_512			(0 << 27)
+#define MXC_CCM_RCSR_PAGE_2K			(1 << 27)
+#define MXC_CCM_RCSR_PAGE_4K1			(2 << 27)
+#define MXC_CCM_RCSR_PAGE_4K2			(3 << 27)
+#define MXC_CCM_RCSR_SOFT_RESET			(1 << 15)
+#define MXC_CCM_RCSR_NF16B			(1 << 14)
+#define MXC_CCM_RCSR_NFC_4K			(1 << 9)
+#define MXC_CCM_RCSR_NFC_FMS			(1 << 8)
+
+/* Bit definitions for both MCU, PERIPHERAL PLL control registers */
+#define MXC_CCM_PCTL_BRM                        0x80000000
+#define MXC_CCM_PCTL_PD_OFFSET                  26
+#define MXC_CCM_PCTL_PD_MASK                    (0xF << 26)
+#define MXC_CCM_PCTL_MFD_OFFSET                 16
+#define MXC_CCM_PCTL_MFD_MASK                   (0x3FF << 16)
+#define MXC_CCM_PCTL_MFI_OFFSET                 10
+#define MXC_CCM_PCTL_MFI_MASK                   (0xF << 10)
+#define MXC_CCM_PCTL_MFN_OFFSET                 0
+#define MXC_CCM_PCTL_MFN_MASK                   0x3FF
+
+/* Bit definitions for Audio clock mux register*/
+#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET	12
+#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK		(0xF << 12)
+#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET	8
+#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK		(0xF << 8)
+#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET	4
+#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK		(0xF << 4)
+#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET	0
+#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK		(0xF << 0)
+
+/* Bit definitions for Clock gating Register*/
+#define MXC_CCM_CGR_CG_MASK			0x3
+#define MXC_CCM_CGR_CG_OFF			0x0
+#define MXC_CCM_CGR_CG_RUN_ON			0x1
+#define MXC_CCM_CGR_CG_RUN_WAIT_ON		0x2
+#define MXC_CCM_CGR_CG_ON			0x3
+
+#define MXC_CCM_CGR0_ASRC_OFFSET		0
+#define MXC_CCM_CGR0_ASRC_MASK			(0x3 << 0)
+#define MXC_CCM_CGR0_ATA_OFFSET			2
+#define MXC_CCM_CGR0_ATA_MASK			(0x3 << 2)
+#define MXC_CCM_CGR0_CAN1_OFFSET		6
+#define MXC_CCM_CGR0_CAN1_MASK			(0x3 << 6)
+#define MXC_CCM_CGR0_CAN2_OFFSET		8
+#define MXC_CCM_CGR0_CAN2_MASK			(0x3 << 8)
+#define MXC_CCM_CGR0_CSPI1_OFFSET		10
+#define MXC_CCM_CGR0_CSPI1_MASK			(0x3 << 10)
+#define MXC_CCM_CGR0_CSPI2_OFFSET		12
+#define MXC_CCM_CGR0_CSPI2_MASK			(0x3 << 12)
+#define MXC_CCM_CGR0_ECT_OFFSET			14
+#define MXC_CCM_CGR0_ECT_MASK			(0x3 << 14)
+#define MXC_CCM_CGR0_EDIO_OFFSET		16
+#define MXC_CCM_CGR0_EDIO_MASK			(0x3 << 16)
+#define MXC_CCM_CGR0_EMI_OFFSET			18
+#define MXC_CCM_CGR0_EMI_MASK			(0x3 << 18)
+#define MXC_CCM_CGR0_EPIT1_OFFSET		20
+#define MXC_CCM_CGR0_EPIT1_MASK			(0x3 << 20)
+#define MXC_CCM_CGR0_EPIT2_OFFSET		22
+#define MXC_CCM_CGR0_EPIT2_MASK			(0x3 << 22)
+#define MXC_CCM_CGR0_ESAI_OFFSET		24
+#define MXC_CCM_CGR0_ESAI_MASK			(0x3 << 24)
+#define MXC_CCM_CGR0_ESDHC1_OFFSET		26
+#define MXC_CCM_CGR0_ESDHC1_MASK		(0x3 << 26)
+#define MXC_CCM_CGR0_ESDHC2_OFFSET		28
+#define MXC_CCM_CGR0_ESDHC2_MASK		(0x3 << 28)
+#define MXC_CCM_CGR0_ESDHC3_OFFSET		30
+#define MXC_CCM_CGR0_ESDHC3_MASK		(0x3 << 30)
+
+#define MXC_CCM_CGR1_FEC_OFFSET			0
+#define MXC_CCM_CGR1_FEC_MASK			(0x3 << 0)
+#define MXC_CCM_CGR1_GPIO1_OFFSET		2
+#define MXC_CCM_CGR1_GPIO1_MASK			(0x3 << 2)
+#define MXC_CCM_CGR1_GPIO2_OFFSET		4
+#define MXC_CCM_CGR1_GPIO2_MASK			(0x3 << 4)
+#define MXC_CCM_CGR1_GPIO3_OFFSET		6
+#define MXC_CCM_CGR1_GPIO3_MASK			(0x3 << 6)
+#define MXC_CCM_CGR1_GPT_OFFSET			8
+#define MXC_CCM_CGR1_GPT_MASK			(0x3 << 8)
+#define MXC_CCM_CGR1_I2C1_OFFSET		10
+#define MXC_CCM_CGR1_I2C1_MASK			(0x3 << 10)
+#define MXC_CCM_CGR1_I2C2_OFFSET		12
+#define MXC_CCM_CGR1_I2C2_MASK			(0x3 << 12)
+#define MXC_CCM_CGR1_I2C3_OFFSET		14
+#define MXC_CCM_CGR1_I2C3_MASK			(0x3 << 14)
+#define MXC_CCM_CGR1_IOMUXC_OFFSET		16
+#define MXC_CCM_CGR1_IOMUXC_MASK		(0x3 << 16)
+#define MXC_CCM_CGR1_IPU_OFFSET			18
+#define MXC_CCM_CGR1_IPU_MASK			(0x3 << 18)
+#define MXC_CCM_CGR1_KPP_OFFSET			20
+#define MXC_CCM_CGR1_KPP_MASK			(0x3 << 20)
+#define MXC_CCM_CGR1_MLB_OFFSET			22
+#define MXC_CCM_CGR1_MLB_MASK			(0x3 << 22)
+#define MXC_CCM_CGR1_MSHC_OFFSET		24
+#define MXC_CCM_CGR1_MSHC_MASK			(0x3 << 24)
+#define MXC_CCM_CGR1_OWIRE_OFFSET		26
+#define MXC_CCM_CGR1_OWIRE_MASK			(0x3 << 26)
+#define MXC_CCM_CGR1_PWM_OFFSET			28
+#define MXC_CCM_CGR1_PWM_MASK			(0x3 << 28)
+#define MXC_CCM_CGR1_RNGC_OFFSET		30
+#define MXC_CCM_CGR1_RNGC_MASK			(0x3 << 30)
+
+#define MXC_CCM_CGR2_RTC_OFFSET			0
+#define MXC_CCM_CGR2_RTC_MASK			(0x3 << 0)
+#define MXC_CCM_CGR2_RTIC_OFFSET		2
+#define MXC_CCM_CGR2_RTIC_MASK			(0x3 << 2)
+#define MXC_CCM_CGR2_SCC_OFFSET			4
+#define MXC_CCM_CGR2_SCC_MASK			(0x3 << 4)
+#define MXC_CCM_CGR2_SDMA_OFFSET		6
+#define MXC_CCM_CGR2_SDMA_MASK			(0x3 << 6)
+#define MXC_CCM_CGR2_SPBA_OFFSET		8
+#define MXC_CCM_CGR2_SPBA_MASK			(0x3 << 8)
+#define MXC_CCM_CGR2_SPDIF_OFFSET		10
+#define MXC_CCM_CGR2_SPDIF_MASK			(0x3 << 10)
+#define MXC_CCM_CGR2_SSI1_OFFSET		12
+#define MXC_CCM_CGR2_SSI1_MASK			(0x3 << 12)
+#define MXC_CCM_CGR2_SSI2_OFFSET		14
+#define MXC_CCM_CGR2_SSI2_MASK			(0x3 << 14)
+#define MXC_CCM_CGR2_UART1_OFFSET		16
+#define MXC_CCM_CGR2_UART1_MASK			(0x3 << 16)
+#define MXC_CCM_CGR2_UART2_OFFSET		18
+#define MXC_CCM_CGR2_UART2_MASK			(0x3 << 18)
+#define MXC_CCM_CGR2_UART3_OFFSET		20
+#define MXC_CCM_CGR2_UART3_MASK			(0x3 << 20)
+#define MXC_CCM_CGR2_USBOTG_OFFSET		22
+#define MXC_CCM_CGR2_USBOTG_MASK		(0x3 << 22)
+#define MXC_CCM_CGR2_WDOG_OFFSET		24
+#define MXC_CCM_CGR2_WDOG_MASK			(0x3 << 24)
+#define MXC_CCM_CGR2_MAX_OFFSET			26
+#define MXC_CCM_CGR2_MAX_MASK			(0x3 << 26)
+#define MXC_CCM_CGR2_MAX_ENABLE			(0x2 << 26)
+#define MXC_CCM_CGR2_AUDMUX_OFFSET		30
+#define MXC_CCM_CGR2_AUDMUX_MASK		(0x3 << 30)
+
+#define MXC_CCM_CGR3_CSI_OFFSET			0
+#define MXC_CCM_CGR3_CSI_MASK			(0x3 << 0)
+#define MXC_CCM_CGR3_IIM_OFFSET			2
+#define MXC_CCM_CGR3_IIM_MASK			(0x3 << 2)
+#define MXC_CCM_CGR3_GPU2D_OFFSET		4
+#define MXC_CCM_CGR3_GPU2D_MASK			(0x3 << 4)
+
+#define MXC_CCM_COSR_CLKOSEL_MASK		0x1F
+#define MXC_CCM_COSR_CLKOSEL_OFFSET		0
+#define MXC_CCM_COSR_CLKOEN			(1 << 5)
+#define MXC_CCM_COSR_CLKOUTDIV_1		(1 << 6)
+#define MXC_CCM_COSR_CLKOUT_DIV_MASK		(0x3F << 10)
+#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET		10
+#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK	(0x3 << 16)
+#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET	16
+#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK	(0x3 << 18)
+#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET	18
+#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK	(0x3 << 20)
+#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET	20
+#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK	(0x3 << 22)
+#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET	22
+#define MXC_CCM_COSR_ASRC_AUDIO_EN		(1 << 24)
+#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK	(0x3F << 26)
+#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET	26
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx35/gpio.h b/arch/arm/include/asm/arch-mx35/gpio.h
new file mode 100644
index 0000000..b3d3639
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/gpio.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ */
+
+
+#ifndef __ASM_ARCH_MX35_GPIO_H
+#define __ASM_ARCH_MX35_GPIO_H
+
+#include <asm/mach-imx/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
new file mode 100644
index 0000000..8ee0754
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -0,0 +1,386 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_MX35_H
+#define __ASM_ARCH_MX35_H
+
+#define ARCH_MXC
+
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR		0x10000000	/* internal ram */
+#define IRAM_SIZE		0x00020000	/* 128 KB */
+
+#define LOW_LEVEL_SRAM_STACK	0x1001E000
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR         0x43F00000
+#define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
+#define MAX_BASE_ADDR           0x43F04000
+#define EVTMON_BASE_ADDR        0x43F08000
+#define CLKCTL_BASE_ADDR        0x43F0C000
+#define I2C1_BASE_ADDR		0x43F80000
+#define I2C3_BASE_ADDR          0x43F84000
+#define ATA_BASE_ADDR           0x43F8C000
+#define UART1_BASE		0x43F90000
+#define UART2_BASE		0x43F94000
+#define I2C2_BASE_ADDR          0x43F98000
+#define CSPI1_BASE_ADDR         0x43FA4000
+#define IOMUXC_BASE_ADDR        0x43FAC000
+
+/*
+ * SPBA
+ */
+#define SPBA_BASE_ADDR          0x50000000
+#define UART3_BASE		0x5000C000
+#define CSPI2_BASE_ADDR         0x50010000
+#define ATA_DMA_BASE_ADDR       0x50020000
+#define FEC_BASE_ADDR           0x50038000
+#define SPBA_CTRL_BASE_ADDR     0x5003C000
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR         0x53F00000
+#define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
+#define CCM_BASE_ADDR           0x53F80000
+#define GPT1_BASE_ADDR          0x53F90000
+#define EPIT1_BASE_ADDR         0x53F94000
+#define EPIT2_BASE_ADDR         0x53F98000
+#define GPIO3_BASE_ADDR         0x53FA4000
+#define MMC_SDHC1_BASE_ADDR	0x53FB4000
+#define MMC_SDHC2_BASE_ADDR	0x53FB8000
+#define MMC_SDHC3_BASE_ADDR	0x53FBC000
+#define IPU_CTRL_BASE_ADDR	0x53FC0000
+#define GPIO1_BASE_ADDR		0x53FCC000
+#define GPIO2_BASE_ADDR		0x53FD0000
+#define SDMA_BASE_ADDR		0x53FD4000
+#define RTC_BASE_ADDR		0x53FD8000
+#define WDOG1_BASE_ADDR		0x53FDC000
+#define PWM_BASE_ADDR		0x53FE0000
+#define RTIC_BASE_ADDR		0x53FEC000
+#define IIM_BASE_ADDR		0x53FF0000
+#define IMX_USB_BASE		0x53FF4000
+#define IMX_USB_PORT_OFFSET	0x400
+
+#define IMX_CCM_BASE		CCM_BASE_ADDR
+
+/*
+ * ROMPATCH and AVIC
+ */
+#define ROMPATCH_BASE_ADDR	0x60000000
+#define AVIC_BASE_ADDR		0x68000000
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define EXT_MEM_CTRL_BASE	0xB8000000
+#define ESDCTL_BASE_ADDR	0xB8001000
+#define WEIM_BASE_ADDR		0xB8002000
+#define WEIM_CTRL_CS0		WEIM_BASE_ADDR
+#define WEIM_CTRL_CS1		(WEIM_BASE_ADDR + 0x10)
+#define WEIM_CTRL_CS2		(WEIM_BASE_ADDR + 0x20)
+#define WEIM_CTRL_CS3		(WEIM_BASE_ADDR + 0x30)
+#define WEIM_CTRL_CS4		(WEIM_BASE_ADDR + 0x40)
+#define WEIM_CTRL_CS5		(WEIM_BASE_ADDR + 0x50)
+#define M3IF_BASE_ADDR		0xB8003000
+#define EMI_BASE_ADDR		0xB8004000
+
+#define NFC_BASE_ADDR		0xBB000000
+
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR	0x70000000
+#define CSD0_BASE_ADDR		0x80000000
+#define CSD1_BASE_ADDR		0x90000000
+#define CS0_BASE_ADDR		0xA0000000
+#define CS1_BASE_ADDR		0xA8000000
+#define CS2_BASE_ADDR		0xB0000000
+#define CS3_BASE_ADDR		0xB2000000
+#define CS4_BASE_ADDR		0xB4000000
+#define CS5_BASE_ADDR		0xB6000000
+
+/*
+ * IRQ Controller Register Definitions.
+ */
+#define AVIC_NIMASK		0x04
+#define AVIC_INTTYPEH		0x18
+#define AVIC_INTTYPEL		0x1C
+
+/* L210 */
+#define L2CC_BASE_ADDR		0x30000000
+#define L2_CACHE_LINE_SIZE		32
+#define L2_CACHE_CTL_REG		0x100
+#define L2_CACHE_AUX_CTL_REG		0x104
+#define L2_CACHE_SYNC_REG		0x730
+#define L2_CACHE_INV_LINE_REG		0x770
+#define L2_CACHE_INV_WAY_REG		0x77C
+#define L2_CACHE_CLEAN_LINE_REG		0x7B0
+#define L2_CACHE_CLEAN_INV_LINE_REG	0x7F0
+#define L2_CACHE_DBG_CTL_REG		0xF40
+
+#define CLKMODE_AUTO		0
+#define CLKMODE_CONSUMER	1
+
+#define PLL_PD(x)		(((x) & 0xf) << 26)
+#define PLL_MFD(x)		(((x) & 0x3ff) << 16)
+#define PLL_MFI(x)		(((x) & 0xf) << 10)
+#define PLL_MFN(x)		(((x) & 0x3ff) << 0)
+
+#define _PLL_BRM(x)	((x) << 31)
+#define _PLL_PD(x)	(((x) - 1) << 26)
+#define _PLL_MFD(x)	(((x) - 1) << 16)
+#define _PLL_MFI(x)	((x) << 10)
+#define _PLL_MFN(x)	(x)
+#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
+	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
+	 _PLL_MFN(mfn))
+
+#define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
+#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
+#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
+
+#define CSCR_U(x)	(WEIM_CTRL_CS#x + 0)
+#define CSCR_L(x)	(WEIM_CTRL_CS#x + 4)
+#define CSCR_A(x)	(WEIM_CTRL_CS#x + 8)
+
+#define IIM_SREV	0x24
+#define ROMPATCH_REV	0x40
+
+#define IPU_CONF	IPU_CTRL_BASE_ADDR
+
+#define IPU_CONF_PXL_ENDIAN	(1<<8)
+#define IPU_CONF_DU_EN		(1<<7)
+#define IPU_CONF_DI_EN		(1<<6)
+#define IPU_CONF_ADC_EN		(1<<5)
+#define IPU_CONF_SDC_EN		(1<<4)
+#define IPU_CONF_PF_EN		(1<<3)
+#define IPU_CONF_ROT_EN		(1<<2)
+#define IPU_CONF_IC_EN		(1<<1)
+#define IPU_CONF_CSI_EN		(1<<0)
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_SMC	(1 << 3)
+#define MXC_CSPICTRL_POL	(1 << 4)
+#define MXC_CSPICTRL_PHA	(1 << 5)
+#define MXC_CSPICTRL_SSCTL	(1 << 6)
+#define MXC_CSPICTRL_SSPOL	(1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	4
+
+#define MXC_SPI_BASE_ADDRESSES \
+	0x43fa4000, \
+	0x50010000,
+
+#define GPIO_PORT_NUM		3
+#define GPIO_NUM_PIN		32
+
+#define CHIP_REV_1_0		0x10
+#define CHIP_REV_2_0		0x20
+
+#define BOARD_REV_1_0		0x0
+#define BOARD_REV_2_0		0x1
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* Clock Control Module (CCM) registers */
+struct ccm_regs {
+	u32 ccmr;	/* Control */
+	u32 pdr0;	/* Post divider 0 */
+	u32 pdr1;	/* Post divider 1 */
+	u32 pdr2;	/* Post divider 2 */
+	u32 pdr3;	/* Post divider 3 */
+	u32 pdr4;	/* Post divider 4 */
+	u32 rcsr;	/* CCM Status */
+	u32 mpctl;	/* Core PLL Control */
+	u32 ppctl;	/* Peripheral PLL Control */
+	u32 acmr;	/* Audio clock mux */
+	u32 cosr;	/* Clock out source */
+	u32 cgr0;	/* Clock Gating Control 0 */
+	u32 cgr1;	/* Clock Gating Control 1 */
+	u32 cgr2;	/* Clock Gating Control 2 */
+	u32 cgr3;	/* Clock Gating Control 3 */
+	u32 reserved;
+	u32 dcvr0;	/* DPTC Comparator 0 */
+	u32 dcvr1;	/* DPTC Comparator 0 */
+	u32 dcvr2;	/* DPTC Comparator 0 */
+	u32 dcvr3;	/* DPTC Comparator 0 */
+	u32 ltr0;	/* Load Tracking 0 */
+	u32 ltr1;	/* Load Tracking 1 */
+	u32 ltr2;	/* Load Tracking 2 */
+	u32 ltr3;	/* Load Tracking 3 */
+	u32 ltbr0;	/* Load Tracking Buffer 0 */
+};
+
+/* IIM control registers */
+struct iim_regs {
+	u32 iim_stat;
+	u32 iim_statm;
+	u32 iim_err;
+	u32 iim_emask;
+	u32 iim_fctl;
+	u32 iim_ua;
+	u32 iim_la;
+	u32 iim_sdat;
+	u32 iim_prev;
+	u32 iim_srev;
+	u32 iim_prg_p;
+	u32 iim_scs0;
+	u32 iim_scs1;
+	u32 iim_scs2;
+	u32 iim_scs3;
+	u32 res1[0x1f1];
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+		u32 fuse_rsvd[0xe0];
+	} bank[3];
+};
+
+struct fuse_bank0_regs {
+	u32 fuse0_7[8];
+	u32 uid[8];
+	u32 fuse16_31[0x10];
+};
+
+struct fuse_bank1_regs {
+	u32 fuse0_21[0x16];
+	u32 usr;
+	u32 fuse23_31[9];
+};
+
+/* General Purpose Timer (GPT) registers */
+struct gpt_regs {
+	u32 ctrl;	/* control */
+	u32 pre;	/* prescaler */
+	u32 stat;	/* status */
+	u32 intr;	/* interrupt */
+	u32 cmp[3];	/* output compare 1-3 */
+	u32 capt[2];	/* input capture 1-2 */
+	u32 counter;	/* counter */
+};
+
+/* CSPI registers */
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+	u32 test;
+};
+
+struct esdc_regs {
+	u32	esdctl0;
+	u32	esdcfg0;
+	u32	esdctl1;
+	u32	esdcfg1;
+	u32	esdmisc;
+	u32	reserved[4];
+	u32	esdcdly[5];
+	u32	esdcdlyl;
+};
+
+#define ESDC_MISC_RST		(1 << 1)
+#define ESDC_MISC_MDDR_EN	(1 << 2)
+#define ESDC_MISC_MDDR_DL_RST	(1 << 3)
+#define ESDC_MISC_DDR_EN	(1 << 8)
+#define ESDC_MISC_DDR2_EN	(1 << 9)
+
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+	u32 mpr0;
+	u32 pad00[3];
+	u32 sgpcr0;
+	u32 pad01[59];
+	u32 mpr1;
+	u32 pad02[3];
+	u32 sgpcr1;
+	u32 pad03[59];
+	u32 mpr2;
+	u32 pad04[3];
+	u32 sgpcr2;
+	u32 pad05[59];
+	u32 mpr3;
+	u32 pad06[3];
+	u32 sgpcr3;
+	u32 pad07[59];
+	u32 mpr4;
+	u32 pad08[3];
+	u32 sgpcr4;
+	u32 pad09[251];
+	u32 mgpcr0;
+	u32 pad10[63];
+	u32 mgpcr1;
+	u32 pad11[63];
+	u32 mgpcr2;
+	u32 pad12[63];
+	u32 mgpcr3;
+	u32 pad13[63];
+	u32 mgpcr4;
+	u32 pad14[63];
+	u32 mgpcr5;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+	u32 mpr_0_7;
+	u32 mpr_8_15;
+	u32 pad0[6];
+	u32 pacr_0_7;
+	u32 pacr_8_15;
+	u32 pacr_16_23;
+	u32 pacr_24_31;
+	u32 pad1[4];
+	u32 opacr_0_7;
+	u32 opacr_8_15;
+	u32 opacr_16_23;
+	u32 opacr_24_31;
+	u32 opacr_32_39;
+};
+
+/*
+ * NFMS bit in RCSR register for pagesize of nandflash
+ */
+#define NFMS_BIT		8
+#define NFMS_NF_DWIDTH		14
+#define NFMS_NF_PG_SZ		8
+
+#define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
+
+#endif
+
+/*
+ * Generic timer support
+ */
+#ifdef CONFIG_MX35_CLK32
+#define	CONFIG_SYS_TIMER_RATE	CONFIG_MX35_CLK32
+#else
+#define	CONFIG_SYS_TIMER_RATE	32768
+#endif
+
+#define CONFIG_SYS_TIMER_COUNTER	(GPT1_BASE_ADDR+36)
+
+#endif /* __ASM_ARCH_MX35_H */
diff --git a/arch/arm/include/asm/arch-mx35/iomux-mx35.h b/arch/arm/include/asm/arch-mx35/iomux-mx35.h
new file mode 100644
index 0000000..f519c69
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/iomux-mx35.h
@@ -0,0 +1,1259 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on mainline Linux i.MX iomux-mx35.h file:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ */
+
+#ifndef __IOMUX_MX35_H__
+#define __IOMUX_MX35_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+/*
+ * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*									    PAD    MUX   ALT INPSE PATH PADCTRL */
+enum {
+	MX35_PAD_CAPTURE__GPT_CAPIN1				= IOMUX_PAD(0x328, 0x004, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__GPT_CMPOUT2				= IOMUX_PAD(0x328, 0x004, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__CSPI2_SS1				= IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__EPIT1_EPITO				= IOMUX_PAD(0x328, 0x004, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__CCM_CLK32K				= IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL),
+	MX35_PAD_CAPTURE__GPIO1_4				= IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL),
+
+	MX35_PAD_COMPARE__GPT_CMPOUT1				= IOMUX_PAD(0x32c, 0x008, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__GPT_CAPIN2				= IOMUX_PAD(0x32c, 0x008, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__GPT_CMPOUT3				= IOMUX_PAD(0x32c, 0x008, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__EPIT2_EPITO				= IOMUX_PAD(0x32c, 0x008, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__GPIO1_5				= IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL),
+	MX35_PAD_COMPARE__SDMA_EXTDMA_2				= IOMUX_PAD(0x32c, 0x008, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_WDOG_RST__WDOG_WDOG_B				= IOMUX_PAD(0x330, 0x00c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_WDOG_RST__IPU_FLASH_STROBE			= IOMUX_PAD(0x330, 0x00c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_WDOG_RST__GPIO1_6				= IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO1_0__GPIO1_0				= IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_0__CCM_PMIC_RDY				= IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_0__OWIRE_LINE				= IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_0__SDMA_EXTDMA_0				= IOMUX_PAD(0x334, 0x010, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO1_1__GPIO1_1				= IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__PWM_PWMO				= IOMUX_PAD(0x338, 0x014, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__CSPI1_SS2				= IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT			= IOMUX_PAD(0x338, 0x014, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_GPIO1_1__SDMA_EXTDMA_1				= IOMUX_PAD(0x338, 0x014, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO2_0__GPIO2_0				= IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK			= IOMUX_PAD(0x33c, 0x018, 1, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_GPIO3_0__GPIO3_0				= IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL),
+	MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK			= IOMUX_PAD(0x340, 0x01c, 1, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RESET_IN_B__CCM_RESET_IN_B			= IOMUX_PAD(0x344, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_POR_B__CCM_POR_B				= IOMUX_PAD(0x348, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CLKO__CCM_CLKO					= IOMUX_PAD(0x34c, 0x020, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CLKO__GPIO1_8					= IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL),
+
+	MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0			= IOMUX_PAD(0x350, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1			= IOMUX_PAD(0x354, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0			= IOMUX_PAD(0x358, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1			= IOMUX_PAD(0x35c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26		= IOMUX_PAD(0x360, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_VSTBY__CCM_VSTBY				= IOMUX_PAD(0x364, 0x024, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_VSTBY__GPIO1_7					= IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL),
+
+	MX35_PAD_A0__EMI_EIM_DA_L_0				= IOMUX_PAD(0x368, 0x028, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A1__EMI_EIM_DA_L_1				= IOMUX_PAD(0x36c, 0x02c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A2__EMI_EIM_DA_L_2				= IOMUX_PAD(0x370, 0x030, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A3__EMI_EIM_DA_L_3				= IOMUX_PAD(0x374, 0x034, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A4__EMI_EIM_DA_L_4				= IOMUX_PAD(0x378, 0x038, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A5__EMI_EIM_DA_L_5				= IOMUX_PAD(0x37c, 0x03c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A6__EMI_EIM_DA_L_6				= IOMUX_PAD(0x380, 0x040, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A7__EMI_EIM_DA_L_7				= IOMUX_PAD(0x384, 0x044, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A8__EMI_EIM_DA_H_8				= IOMUX_PAD(0x388, 0x048, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A9__EMI_EIM_DA_H_9				= IOMUX_PAD(0x38c, 0x04c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A10__EMI_EIM_DA_H_10				= IOMUX_PAD(0x390, 0x050, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_MA10__EMI_MA10					= IOMUX_PAD(0x394, 0x054, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A11__EMI_EIM_DA_H_11				= IOMUX_PAD(0x398, 0x058, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A12__EMI_EIM_DA_H_12				= IOMUX_PAD(0x39c, 0x05c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A13__EMI_EIM_DA_H_13				= IOMUX_PAD(0x3a0, 0x060, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A14__EMI_EIM_DA_H2_14				= IOMUX_PAD(0x3a4, 0x064, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A15__EMI_EIM_DA_H2_15				= IOMUX_PAD(0x3a8, 0x068, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A16__EMI_EIM_A_16				= IOMUX_PAD(0x3ac, 0x06c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A17__EMI_EIM_A_17				= IOMUX_PAD(0x3b0, 0x070, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A18__EMI_EIM_A_18				= IOMUX_PAD(0x3b4, 0x074, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A19__EMI_EIM_A_19				= IOMUX_PAD(0x3b8, 0x078, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A20__EMI_EIM_A_20				= IOMUX_PAD(0x3bc, 0x07c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A21__EMI_EIM_A_21				= IOMUX_PAD(0x3c0, 0x080, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A22__EMI_EIM_A_22				= IOMUX_PAD(0x3c4, 0x084, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A23__EMI_EIM_A_23				= IOMUX_PAD(0x3c8, 0x088, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A24__EMI_EIM_A_24				= IOMUX_PAD(0x3cc, 0x08c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_A25__EMI_EIM_A_25				= IOMUX_PAD(0x3d0, 0x090, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDBA1__EMI_EIM_SDBA1				= IOMUX_PAD(0x3d4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDBA0__EMI_EIM_SDBA0				= IOMUX_PAD(0x3d8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD0__EMI_DRAM_D_0				= IOMUX_PAD(0x3dc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1__EMI_DRAM_D_1				= IOMUX_PAD(0x3e0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD2__EMI_DRAM_D_2				= IOMUX_PAD(0x3e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD3__EMI_DRAM_D_3				= IOMUX_PAD(0x3e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD4__EMI_DRAM_D_4				= IOMUX_PAD(0x3ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD5__EMI_DRAM_D_5				= IOMUX_PAD(0x3f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD6__EMI_DRAM_D_6				= IOMUX_PAD(0x3f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD7__EMI_DRAM_D_7				= IOMUX_PAD(0x3f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD8__EMI_DRAM_D_8				= IOMUX_PAD(0x3fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD9__EMI_DRAM_D_9				= IOMUX_PAD(0x400, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD10__EMI_DRAM_D_10				= IOMUX_PAD(0x404, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD11__EMI_DRAM_D_11				= IOMUX_PAD(0x408, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD12__EMI_DRAM_D_12				= IOMUX_PAD(0x40c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD13__EMI_DRAM_D_13				= IOMUX_PAD(0x410, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD14__EMI_DRAM_D_14				= IOMUX_PAD(0x414, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD15__EMI_DRAM_D_15				= IOMUX_PAD(0x418, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD16__EMI_DRAM_D_16				= IOMUX_PAD(0x41c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD17__EMI_DRAM_D_17				= IOMUX_PAD(0x420, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD18__EMI_DRAM_D_18				= IOMUX_PAD(0x424, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD19__EMI_DRAM_D_19				= IOMUX_PAD(0x428, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD20__EMI_DRAM_D_20				= IOMUX_PAD(0x42c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD21__EMI_DRAM_D_21				= IOMUX_PAD(0x430, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD22__EMI_DRAM_D_22				= IOMUX_PAD(0x434, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD23__EMI_DRAM_D_23				= IOMUX_PAD(0x438, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD24__EMI_DRAM_D_24				= IOMUX_PAD(0x43c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD25__EMI_DRAM_D_25				= IOMUX_PAD(0x440, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD26__EMI_DRAM_D_26				= IOMUX_PAD(0x444, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD27__EMI_DRAM_D_27				= IOMUX_PAD(0x448, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD28__EMI_DRAM_D_28				= IOMUX_PAD(0x44c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD29__EMI_DRAM_D_29				= IOMUX_PAD(0x450, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD30__EMI_DRAM_D_30				= IOMUX_PAD(0x454, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD31__EMI_DRAM_D_31				= IOMUX_PAD(0x458, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM0__EMI_DRAM_DQM_0				= IOMUX_PAD(0x45c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM1__EMI_DRAM_DQM_1				= IOMUX_PAD(0x460, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM2__EMI_DRAM_DQM_2				= IOMUX_PAD(0x464, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DQM3__EMI_DRAM_DQM_3				= IOMUX_PAD(0x468, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_EB0__EMI_EIM_EB0_B				= IOMUX_PAD(0x46c, 0x094, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_EB1__EMI_EIM_EB1_B				= IOMUX_PAD(0x470, 0x098, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_OE__EMI_EIM_OE					= IOMUX_PAD(0x474, 0x09c, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS0__EMI_EIM_CS0				= IOMUX_PAD(0x478, 0x0a0, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS1__EMI_EIM_CS1				= IOMUX_PAD(0x47c, 0x0a4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS1__EMI_NANDF_CE3				= IOMUX_PAD(0x47c, 0x0a4, 3, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS2__EMI_EIM_CS2				= IOMUX_PAD(0x480, 0x0a8, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS3__EMI_EIM_CS3				= IOMUX_PAD(0x484, 0x0ac, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CS4__EMI_EIM_CS4				= IOMUX_PAD(0x488, 0x0b0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS4__EMI_DTACK_B				= IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL),
+	MX35_PAD_CS4__EMI_NANDF_CE1				= IOMUX_PAD(0x488, 0x0b0, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS4__GPIO1_20					= IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL),
+
+	MX35_PAD_CS5__EMI_EIM_CS5				= IOMUX_PAD(0x48c, 0x0b4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS5__CSPI2_SS2					= IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL),
+	MX35_PAD_CS5__CSPI1_SS2					= IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL),
+	MX35_PAD_CS5__EMI_NANDF_CE2				= IOMUX_PAD(0x48c, 0x0b4, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CS5__GPIO1_21					= IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL),
+
+	MX35_PAD_NF_CE0__EMI_NANDF_CE0				= IOMUX_PAD(0x490, 0x0b8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NF_CE0__GPIO1_22				= IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL),
+
+	MX35_PAD_ECB__EMI_EIM_ECB				= IOMUX_PAD(0x494, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LBA__EMI_EIM_LBA				= IOMUX_PAD(0x498, 0x0bc, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_BCLK__EMI_EIM_BCLK				= IOMUX_PAD(0x49c, 0x0c0, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RW__EMI_EIM_RW					= IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RAS__EMI_DRAM_RAS				= IOMUX_PAD(0x4a4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CAS__EMI_DRAM_CAS				= IOMUX_PAD(0x4a8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDWE__EMI_DRAM_SDWE				= IOMUX_PAD(0x4ac, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0			= IOMUX_PAD(0x4b0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1			= IOMUX_PAD(0x4b4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDCLK__EMI_DRAM_SDCLK				= IOMUX_PAD(0x4b8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS0__EMI_DRAM_SDQS_0				= IOMUX_PAD(0x4bc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS1__EMI_DRAM_SDQS_1				= IOMUX_PAD(0x4c0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS2__EMI_DRAM_SDQS_2				= IOMUX_PAD(0x4c4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SDQS3__EMI_DRAM_SDQS_3				= IOMUX_PAD(0x4c8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFWE_B__EMI_NANDF_WE_B				= IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3			= IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__GPIO2_18				= IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0			= IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFRE_B__EMI_NANDF_RE_B				= IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR			= IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__IPU_DISPB_BCLK				= IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__GPIO2_19				= IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL),
+	MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1			= IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFALE__EMI_NANDF_ALE				= IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__USB_TOP_USBH2_STP			= IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__IPU_DISPB_CS0				= IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__GPIO2_20				= IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL),
+	MX35_PAD_NFALE__ARM11P_TOP_TRACE_2			= IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFCLE__EMI_NANDF_CLE				= IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__USB_TOP_USBH2_NXT			= IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__IPU_DISPB_PAR_RS			= IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__GPIO2_21				= IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL),
+	MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3			= IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFWP_B__EMI_NANDF_WP_B				= IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7			= IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__IPU_DISPB_WR				= IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__GPIO2_22				= IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL),
+	MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL			= IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_NFRB__EMI_NANDF_RB				= IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRB__IPU_DISPB_RD				= IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_NFRB__GPIO2_23					= IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL),
+	MX35_PAD_NFRB__ARM11P_TOP_TRCLK				= IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D15__EMI_EIM_D_15				= IOMUX_PAD(0x4e4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D14__EMI_EIM_D_14				= IOMUX_PAD(0x4e8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D13__EMI_EIM_D_13				= IOMUX_PAD(0x4ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D12__EMI_EIM_D_12				= IOMUX_PAD(0x4f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D11__EMI_EIM_D_11				= IOMUX_PAD(0x4f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D10__EMI_EIM_D_10				= IOMUX_PAD(0x4f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D9__EMI_EIM_D_9				= IOMUX_PAD(0x4fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D8__EMI_EIM_D_8				= IOMUX_PAD(0x500, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D7__EMI_EIM_D_7				= IOMUX_PAD(0x504, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D6__EMI_EIM_D_6				= IOMUX_PAD(0x508, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D5__EMI_EIM_D_5				= IOMUX_PAD(0x50c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D4__EMI_EIM_D_4				= IOMUX_PAD(0x510, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3__EMI_EIM_D_3				= IOMUX_PAD(0x514, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D2__EMI_EIM_D_2				= IOMUX_PAD(0x518, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D1__EMI_EIM_D_1				= IOMUX_PAD(0x51c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D0__EMI_EIM_D_0				= IOMUX_PAD(0x520, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D8__IPU_CSI_D_8				= IOMUX_PAD(0x524, 0x0e0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D8__KPP_COL_0				= IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D8__GPIO1_20				= IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL),
+	MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13			= IOMUX_PAD(0x524, 0x0e0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D9__IPU_CSI_D_9				= IOMUX_PAD(0x528, 0x0e4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D9__KPP_COL_1				= IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D9__GPIO1_21				= IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL),
+	MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14			= IOMUX_PAD(0x528, 0x0e4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D10__IPU_CSI_D_10				= IOMUX_PAD(0x52c, 0x0e8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D10__KPP_COL_2				= IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D10__GPIO1_22				= IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL),
+	MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15			= IOMUX_PAD(0x52c, 0x0e8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D11__IPU_CSI_D_11				= IOMUX_PAD(0x530, 0x0ec, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D11__KPP_COL_3				= IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D11__GPIO1_23				= IOMUX_PAD(0x530, 0x0ec, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D12__IPU_CSI_D_12				= IOMUX_PAD(0x534, 0x0f0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D12__KPP_ROW_0				= IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D12__GPIO1_24				= IOMUX_PAD(0x534, 0x0f0, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D13__IPU_CSI_D_13				= IOMUX_PAD(0x538, 0x0f4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D13__KPP_ROW_1				= IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D13__GPIO1_25				= IOMUX_PAD(0x538, 0x0f4, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D14__IPU_CSI_D_14				= IOMUX_PAD(0x53c, 0x0f8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D14__KPP_ROW_2				= IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D14__GPIO1_26				= IOMUX_PAD(0x53c, 0x0f8, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_D15__IPU_CSI_D_15				= IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D15__KPP_ROW_3				= IOMUX_PAD(0x540, 0x0fc, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_D15__GPIO1_27				= IOMUX_PAD(0x540, 0x0fc, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_MCLK__IPU_CSI_MCLK				= IOMUX_PAD(0x544, 0x100, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_MCLK__GPIO1_28				= IOMUX_PAD(0x544, 0x100, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC			= IOMUX_PAD(0x548, 0x104, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_VSYNC__GPIO1_29				= IOMUX_PAD(0x548, 0x104, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC			= IOMUX_PAD(0x54c, 0x108, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_HSYNC__GPIO1_30				= IOMUX_PAD(0x54c, 0x108, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK			= IOMUX_PAD(0x550, 0x10c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSI_PIXCLK__GPIO1_31				= IOMUX_PAD(0x550, 0x10c, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C1_CLK__I2C1_SCL				= IOMUX_PAD(0x554, 0x110, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C1_CLK__GPIO2_24				= IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK			= IOMUX_PAD(0x554, 0x110, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C1_DAT__I2C1_SDA				= IOMUX_PAD(0x558, 0x114, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C1_DAT__GPIO2_25				= IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C2_CLK__I2C2_SCL				= IOMUX_PAD(0x55c, 0x118, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__CAN1_TXCAN				= IOMUX_PAD(0x55c, 0x118, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR			= IOMUX_PAD(0x55c, 0x118, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__GPIO2_26				= IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2		= IOMUX_PAD(0x55c, 0x118, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_I2C2_DAT__I2C2_SDA				= IOMUX_PAD(0x560, 0x11c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__CAN1_RXCAN				= IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC			= IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__GPIO2_27				= IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL),
+	MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3		= IOMUX_PAD(0x560, 0x11c, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXD4__AUDMUX_AUD4_TXD				= IOMUX_PAD(0x564, 0x120, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXD4__GPIO2_28				= IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL),
+	MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0		= IOMUX_PAD(0x564, 0x120, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SRXD4__AUDMUX_AUD4_RXD				= IOMUX_PAD(0x568, 0x124, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SRXD4__GPIO2_29				= IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL),
+	MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1		= IOMUX_PAD(0x568, 0x124, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCK4__AUDMUX_AUD4_TXC				= IOMUX_PAD(0x56c, 0x128, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCK4__GPIO2_30					= IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2			= IOMUX_PAD(0x56c, 0x128, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS			= IOMUX_PAD(0x570, 0x12c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXFS4__GPIO2_31				= IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL),
+	MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3		= IOMUX_PAD(0x570, 0x12c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXD5__AUDMUX_AUD5_TXD				= IOMUX_PAD(0x574, 0x130, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXD5__SPDIF_SPDIF_OUT1			= IOMUX_PAD(0x574, 0x130, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXD5__CSPI2_MOSI				= IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL),
+	MX35_PAD_STXD5__GPIO1_0					= IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL),
+	MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4		= IOMUX_PAD(0x574, 0x130, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SRXD5__AUDMUX_AUD5_RXD				= IOMUX_PAD(0x578, 0x134, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__SPDIF_SPDIF_IN1				= IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__CSPI2_MISO				= IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__GPIO1_1					= IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL),
+	MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5		= IOMUX_PAD(0x578, 0x134, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCK5__AUDMUX_AUD5_TXC				= IOMUX_PAD(0x57c, 0x138, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__CSPI2_SCLK				= IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__GPIO1_2					= IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL),
+	MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6			= IOMUX_PAD(0x57c, 0x138, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS			= IOMUX_PAD(0x580, 0x13c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_STXFS5__CSPI2_RDY				= IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL),
+	MX35_PAD_STXFS5__GPIO1_3				= IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL),
+	MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7		= IOMUX_PAD(0x580, 0x13c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCKR__ESAI_SCKR				= IOMUX_PAD(0x584, 0x140, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCKR__GPIO1_4					= IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL),
+	MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10			= IOMUX_PAD(0x584, 0x140, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FSR__ESAI_FSR					= IOMUX_PAD(0x588, 0x144, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FSR__GPIO1_5					= IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL),
+	MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11			= IOMUX_PAD(0x588, 0x144, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_HCKR__ESAI_HCKR				= IOMUX_PAD(0x58c, 0x148, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__AUDMUX_AUD5_RXFS				= IOMUX_PAD(0x58c, 0x148, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__CSPI2_SS0				= IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__IPU_FLASH_STROBE				= IOMUX_PAD(0x58c, 0x148, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKR__GPIO1_6					= IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL),
+	MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12			= IOMUX_PAD(0x58c, 0x148, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SCKT__ESAI_SCKT				= IOMUX_PAD(0x590, 0x14c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SCKT__GPIO1_7					= IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL),
+	MX35_PAD_SCKT__IPU_CSI_D_0				= IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL),
+	MX35_PAD_SCKT__KPP_ROW_2				= IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL),
+
+	MX35_PAD_FST__ESAI_FST					= IOMUX_PAD(0x594, 0x150, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FST__GPIO1_8					= IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL),
+	MX35_PAD_FST__IPU_CSI_D_1				= IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL),
+	MX35_PAD_FST__KPP_ROW_3					= IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL),
+
+	MX35_PAD_HCKT__ESAI_HCKT				= IOMUX_PAD(0x598, 0x154, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__AUDMUX_AUD5_RXC				= IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__GPIO1_9					= IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__IPU_CSI_D_2				= IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL),
+	MX35_PAD_HCKT__KPP_COL_3				= IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX5_RX0__ESAI_TX5_RX0				= IOMUX_PAD(0x59c, 0x158, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC			= IOMUX_PAD(0x59c, 0x158, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__CSPI2_SS2				= IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__CAN2_TXCAN				= IOMUX_PAD(0x59c, 0x158, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__UART2_DTR				= IOMUX_PAD(0x59c, 0x158, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__GPIO1_10				= IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL),
+	MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0		= IOMUX_PAD(0x59c, 0x158, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TX4_RX1__ESAI_TX4_RX1				= IOMUX_PAD(0x5a0, 0x15c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS			= IOMUX_PAD(0x5a0, 0x15c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__CSPI2_SS3				= IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__CAN2_RXCAN				= IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__UART2_DSR				= IOMUX_PAD(0x5a0, 0x15c, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__GPIO1_11				= IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__IPU_CSI_D_3				= IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL),
+	MX35_PAD_TX4_RX1__KPP_ROW_0				= IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX3_RX2__ESAI_TX3_RX2				= IOMUX_PAD(0x5a4, 0x160, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__I2C3_SCL				= IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__EMI_NANDF_CE1				= IOMUX_PAD(0x5a4, 0x160, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__GPIO1_12				= IOMUX_PAD(0x5a4, 0x160, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__IPU_CSI_D_4				= IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL),
+	MX35_PAD_TX3_RX2__KPP_ROW_1				= IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX2_RX3__ESAI_TX2_RX3				= IOMUX_PAD(0x5a8, 0x164, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__I2C3_SDA				= IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__EMI_NANDF_CE2				= IOMUX_PAD(0x5a8, 0x164, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__GPIO1_13				= IOMUX_PAD(0x5a8, 0x164, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__IPU_CSI_D_5				= IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL),
+	MX35_PAD_TX2_RX3__KPP_COL_0				= IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX1__ESAI_TX1					= IOMUX_PAD(0x5ac, 0x168, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__CCM_PMIC_RDY				= IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL),
+	MX35_PAD_TX1__CSPI1_SS2					= IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL),
+	MX35_PAD_TX1__EMI_NANDF_CE3				= IOMUX_PAD(0x5ac, 0x168, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__UART2_RI					= IOMUX_PAD(0x5ac, 0x168, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__GPIO1_14					= IOMUX_PAD(0x5ac, 0x168, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX1__IPU_CSI_D_6				= IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL),
+	MX35_PAD_TX1__KPP_COL_1					= IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL),
+
+	MX35_PAD_TX0__ESAI_TX0					= IOMUX_PAD(0x5b0, 0x16c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL),
+	MX35_PAD_TX0__CSPI1_SS3					= IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL),
+	MX35_PAD_TX0__EMI_DTACK_B				= IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL),
+	MX35_PAD_TX0__UART2_DCD					= IOMUX_PAD(0x5b0, 0x16c, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX0__GPIO1_15					= IOMUX_PAD(0x5b0, 0x16c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TX0__IPU_CSI_D_7				= IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL),
+	MX35_PAD_TX0__KPP_COL_2					= IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_MOSI__CSPI1_MOSI				= IOMUX_PAD(0x5b4, 0x170, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MOSI__GPIO1_16				= IOMUX_PAD(0x5b4, 0x170, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2		= IOMUX_PAD(0x5b4, 0x170, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_MISO__CSPI1_MISO				= IOMUX_PAD(0x5b8, 0x174, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MISO__GPIO1_17				= IOMUX_PAD(0x5b8, 0x174, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3		= IOMUX_PAD(0x5b8, 0x174, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SS0__CSPI1_SS0				= IOMUX_PAD(0x5bc, 0x178, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__OWIRE_LINE				= IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__CSPI2_SS3				= IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__GPIO1_18				= IOMUX_PAD(0x5bc, 0x178, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4			= IOMUX_PAD(0x5bc, 0x178, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SS1__CSPI1_SS1				= IOMUX_PAD(0x5c0, 0x17c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__PWM_PWMO				= IOMUX_PAD(0x5c0, 0x17c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__CCM_CLK32K				= IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__GPIO1_19				= IOMUX_PAD(0x5c0, 0x17c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__IPU_DIAGB_29			= IOMUX_PAD(0x5c0, 0x17c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5			= IOMUX_PAD(0x5c0, 0x17c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SCLK__CSPI1_SCLK				= IOMUX_PAD(0x5c4, 0x180, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SCLK__GPIO3_4				= IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30			= IOMUX_PAD(0x5c4, 0x180, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1		= IOMUX_PAD(0x5c4, 0x180, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY			= IOMUX_PAD(0x5c8, 0x184, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SPI_RDY__GPIO3_5				= IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31			= IOMUX_PAD(0x5c8, 0x184, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2	= IOMUX_PAD(0x5c8, 0x184, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RXD1__UART1_RXD_MUX				= IOMUX_PAD(0x5cc, 0x188, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RXD1__CSPI2_MOSI				= IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL),
+	MX35_PAD_RXD1__KPP_COL_4				= IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL),
+	MX35_PAD_RXD1__GPIO3_6					= IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL),
+	MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16			= IOMUX_PAD(0x5cc, 0x188, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TXD1__UART1_TXD_MUX				= IOMUX_PAD(0x5d0, 0x18c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TXD1__CSPI2_MISO				= IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL),
+	MX35_PAD_TXD1__KPP_COL_5				= IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL),
+	MX35_PAD_TXD1__GPIO3_7					= IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL),
+	MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17			= IOMUX_PAD(0x5d0, 0x18c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RTS1__UART1_RTS				= IOMUX_PAD(0x5d4, 0x190, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__CSPI2_SCLK				= IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS1__I2C3_SCL					= IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS1__IPU_CSI_D_0				= IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS1__KPP_COL_6				= IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__GPIO3_8					= IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__EMI_NANDF_CE1				= IOMUX_PAD(0x5d4, 0x190, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18			= IOMUX_PAD(0x5d4, 0x190, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CTS1__UART1_CTS				= IOMUX_PAD(0x5d8, 0x194, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__CSPI2_RDY				= IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS1__I2C3_SDA					= IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS1__IPU_CSI_D_1				= IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS1__KPP_COL_7				= IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__GPIO3_9					= IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__EMI_NANDF_CE2				= IOMUX_PAD(0x5d8, 0x194, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19			= IOMUX_PAD(0x5d8, 0x194, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RXD2__UART2_RXD_MUX				= IOMUX_PAD(0x5dc, 0x198, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RXD2__KPP_ROW_4				= IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL),
+	MX35_PAD_RXD2__GPIO3_10					= IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL),
+
+	MX35_PAD_TXD2__UART2_TXD_MUX				= IOMUX_PAD(0x5e0, 0x19c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL),
+	MX35_PAD_TXD2__KPP_ROW_5				= IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL),
+	MX35_PAD_TXD2__GPIO3_11					= IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL),
+
+	MX35_PAD_RTS2__UART2_RTS				= IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__SPDIF_SPDIF_IN1				= IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS2__CAN2_RXCAN				= IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS2__IPU_CSI_D_2				= IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL),
+	MX35_PAD_RTS2__KPP_ROW_6				= IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__GPIO3_12					= IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__AUDMUX_AUD5_RXC				= IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_RTS2__UART3_RXD_MUX				= IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL),
+
+	MX35_PAD_CTS2__UART2_CTS				= IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__SPDIF_SPDIF_OUT1				= IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__CAN2_TXCAN				= IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__IPU_CSI_D_3				= IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL),
+	MX35_PAD_CTS2__KPP_ROW_7				= IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__GPIO3_13					= IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__AUDMUX_AUD5_RXFS				= IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CTS2__UART3_TXD_MUX				= IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_RTCK__ARM11P_TOP_RTCK				= IOMUX_PAD(0x5ec, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TCK__SJC_TCK					= IOMUX_PAD(0x5f0, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TMS__SJC_TMS					= IOMUX_PAD(0x5f4, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TDI__SJC_TDI					= IOMUX_PAD(0x5f8, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TDO__SJC_TDO					= IOMUX_PAD(0x5fc, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TRSTB__SJC_TRSTB				= IOMUX_PAD(0x600, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_DE_B__SJC_DE_B					= IOMUX_PAD(0x604, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SJC_MOD__SJC_MOD				= IOMUX_PAD(0x608, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR			= IOMUX_PAD(0x60c, 0x1a8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR			= IOMUX_PAD(0x60c, 0x1a8, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_PWR__GPIO3_14				= IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL),
+
+	MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC			= IOMUX_PAD(0x610, 0x1ac, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC			= IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL),
+	MX35_PAD_USBOTG_OC__GPIO3_15				= IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL),
+
+	MX35_PAD_LD0__IPU_DISPB_DAT_0				= IOMUX_PAD(0x614, 0x1b0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD0__GPIO2_0					= IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL),
+	MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0			= IOMUX_PAD(0x614, 0x1b0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD1__IPU_DISPB_DAT_1				= IOMUX_PAD(0x618, 0x1b4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD1__GPIO2_1					= IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL),
+	MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1			= IOMUX_PAD(0x618, 0x1b4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD2__IPU_DISPB_DAT_2				= IOMUX_PAD(0x61c, 0x1b8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD2__GPIO2_2					= IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2			= IOMUX_PAD(0x61c, 0x1b8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD3__IPU_DISPB_DAT_3				= IOMUX_PAD(0x620, 0x1bc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD3__GPIO2_3					= IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL),
+	MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3			= IOMUX_PAD(0x620, 0x1bc, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD4__IPU_DISPB_DAT_4				= IOMUX_PAD(0x624, 0x1c0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD4__GPIO2_4					= IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4			= IOMUX_PAD(0x624, 0x1c0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD5__IPU_DISPB_DAT_5				= IOMUX_PAD(0x628, 0x1c4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD5__GPIO2_5					= IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL),
+	MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5			= IOMUX_PAD(0x628, 0x1c4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD6__IPU_DISPB_DAT_6				= IOMUX_PAD(0x62c, 0x1c8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD6__GPIO2_6					= IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL),
+	MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6			= IOMUX_PAD(0x62c, 0x1c8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD7__IPU_DISPB_DAT_7				= IOMUX_PAD(0x630, 0x1cc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD7__GPIO2_7					= IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL),
+	MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7			= IOMUX_PAD(0x630, 0x1cc, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD8__IPU_DISPB_DAT_8				= IOMUX_PAD(0x634, 0x1d0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD8__GPIO2_8					= IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8			= IOMUX_PAD(0x634, 0x1d0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD9__IPU_DISPB_DAT_9				= IOMUX_PAD(0x638, 0x1d4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD9__GPIO2_9					= IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL),
+	MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9			= IOMUX_PAD(0x638, 0x1d4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD10__IPU_DISPB_DAT_10				= IOMUX_PAD(0x63c, 0x1d8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD10__GPIO2_10					= IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10			= IOMUX_PAD(0x63c, 0x1d8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD11__IPU_DISPB_DAT_11				= IOMUX_PAD(0x640, 0x1dc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD11__GPIO2_11					= IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL),
+	MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11			= IOMUX_PAD(0x640, 0x1dc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD11__ARM11P_TOP_TRACE_4			= IOMUX_PAD(0x640, 0x1dc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD12__IPU_DISPB_DAT_12				= IOMUX_PAD(0x644, 0x1e0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD12__GPIO2_12					= IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL),
+	MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12			= IOMUX_PAD(0x644, 0x1e0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD12__ARM11P_TOP_TRACE_5			= IOMUX_PAD(0x644, 0x1e0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD13__IPU_DISPB_DAT_13				= IOMUX_PAD(0x648, 0x1e4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD13__GPIO2_13					= IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL),
+	MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13			= IOMUX_PAD(0x648, 0x1e4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD13__ARM11P_TOP_TRACE_6			= IOMUX_PAD(0x648, 0x1e4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD14__IPU_DISPB_DAT_14				= IOMUX_PAD(0x64c, 0x1e8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD14__GPIO2_14					= IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0		= IOMUX_PAD(0x64c, 0x1e8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD14__ARM11P_TOP_TRACE_7			= IOMUX_PAD(0x64c, 0x1e8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD15__IPU_DISPB_DAT_15				= IOMUX_PAD(0x650, 0x1ec, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD15__GPIO2_15					= IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL),
+	MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1		= IOMUX_PAD(0x650, 0x1ec, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD15__ARM11P_TOP_TRACE_8			= IOMUX_PAD(0x650, 0x1ec, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD16__IPU_DISPB_DAT_16				= IOMUX_PAD(0x654, 0x1f0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD16__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL),
+	MX35_PAD_LD16__GPIO2_16					= IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL),
+	MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2		= IOMUX_PAD(0x654, 0x1f0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD16__ARM11P_TOP_TRACE_9			= IOMUX_PAD(0x654, 0x1f0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD17__IPU_DISPB_DAT_17				= IOMUX_PAD(0x658, 0x1f4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD17__IPU_DISPB_CS2				= IOMUX_PAD(0x658, 0x1f4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD17__GPIO2_17					= IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL),
+	MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3		= IOMUX_PAD(0x658, 0x1f4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD17__ARM11P_TOP_TRACE_10			= IOMUX_PAD(0x658, 0x1f4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD18__IPU_DISPB_DAT_18				= IOMUX_PAD(0x65c, 0x1f8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD18__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL),
+	MX35_PAD_LD18__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL),
+	MX35_PAD_LD18__ESDHC3_CMD				= IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL),
+	MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3			= IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD18__GPIO3_24					= IOMUX_PAD(0x65c, 0x1f8, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4		= IOMUX_PAD(0x65c, 0x1f8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD18__ARM11P_TOP_TRACE_11			= IOMUX_PAD(0x65c, 0x1f8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD19__IPU_DISPB_DAT_19				= IOMUX_PAD(0x660, 0x1fc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__IPU_DISPB_BCLK				= IOMUX_PAD(0x660, 0x1fc, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__IPU_DISPB_CS1				= IOMUX_PAD(0x660, 0x1fc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__ESDHC3_CLK				= IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL),
+	MX35_PAD_LD19__USB_TOP_USBOTG_DIR			= IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL),
+	MX35_PAD_LD19__GPIO3_25					= IOMUX_PAD(0x660, 0x1fc, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5		= IOMUX_PAD(0x660, 0x1fc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD19__ARM11P_TOP_TRACE_12			= IOMUX_PAD(0x660, 0x1fc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD20__IPU_DISPB_DAT_20				= IOMUX_PAD(0x664, 0x200, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__IPU_DISPB_CS0				= IOMUX_PAD(0x664, 0x200, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__IPU_DISPB_SD_CLK				= IOMUX_PAD(0x664, 0x200, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__ESDHC3_DAT0				= IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD20__GPIO3_26					= IOMUX_PAD(0x664, 0x200, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3		= IOMUX_PAD(0x664, 0x200, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD20__ARM11P_TOP_TRACE_13			= IOMUX_PAD(0x664, 0x200, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD21__IPU_DISPB_DAT_21				= IOMUX_PAD(0x668, 0x204, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__IPU_DISPB_PAR_RS				= IOMUX_PAD(0x668, 0x204, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__IPU_DISPB_SER_RS				= IOMUX_PAD(0x668, 0x204, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__ESDHC3_DAT1				= IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL),
+	MX35_PAD_LD21__USB_TOP_USBOTG_STP			= IOMUX_PAD(0x668, 0x204, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__GPIO3_27					= IOMUX_PAD(0x668, 0x204, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL		= IOMUX_PAD(0x668, 0x204, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD21__ARM11P_TOP_TRACE_14			= IOMUX_PAD(0x668, 0x204, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD22__IPU_DISPB_DAT_22				= IOMUX_PAD(0x66c, 0x208, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__IPU_DISPB_WR				= IOMUX_PAD(0x66c, 0x208, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__IPU_DISPB_SD_D_I				= IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL),
+	MX35_PAD_LD22__ESDHC3_DAT2				= IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL),
+	MX35_PAD_LD22__USB_TOP_USBOTG_NXT			= IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL),
+	MX35_PAD_LD22__GPIO3_28					= IOMUX_PAD(0x66c, 0x208, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR			= IOMUX_PAD(0x66c, 0x208, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD22__ARM11P_TOP_TRCTL				= IOMUX_PAD(0x66c, 0x208, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_LD23__IPU_DISPB_DAT_23				= IOMUX_PAD(0x670, 0x20c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__IPU_DISPB_RD				= IOMUX_PAD(0x670, 0x20c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL),
+	MX35_PAD_LD23__ESDHC3_DAT3				= IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL),
+	MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7			= IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL),
+	MX35_PAD_LD23__GPIO3_29					= IOMUX_PAD(0x670, 0x20c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS			= IOMUX_PAD(0x670, 0x20c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_LD23__ARM11P_TOP_TRCLK				= IOMUX_PAD(0x670, 0x20c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC			= IOMUX_PAD(0x674, 0x210, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__GPIO3_30				= IOMUX_PAD(0x674, 0x210, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE		= IOMUX_PAD(0x674, 0x210, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15			= IOMUX_PAD(0x674, 0x210, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK			= IOMUX_PAD(0x678, 0x214, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK			= IOMUX_PAD(0x678, 0x214, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__GPIO3_31				= IOMUX_PAD(0x678, 0x214, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0	= IOMUX_PAD(0x678, 0x214, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16		= IOMUX_PAD(0x678, 0x214, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY			= IOMUX_PAD(0x67c, 0x218, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O			= IOMUX_PAD(0x67c, 0x218, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__GPIO1_0				= IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1		= IOMUX_PAD(0x67c, 0x218, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17			= IOMUX_PAD(0x67c, 0x218, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_CONTRAST__IPU_DISPB_CONTR			= IOMUX_PAD(0x680, 0x21c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CONTRAST__GPIO1_1				= IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL),
+	MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2	= IOMUX_PAD(0x680, 0x21c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18			= IOMUX_PAD(0x680, 0x21c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC			= IOMUX_PAD(0x684, 0x220, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__IPU_DISPB_CS1			= IOMUX_PAD(0x684, 0x220, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__GPIO1_2				= IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD			= IOMUX_PAD(0x684, 0x220, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19			= IOMUX_PAD(0x684, 0x220, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_REV__IPU_DISPB_D3_REV			= IOMUX_PAD(0x688, 0x224, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__IPU_DISPB_SER_RS			= IOMUX_PAD(0x688, 0x224, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__GPIO1_3				= IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB			= IOMUX_PAD(0x688, 0x224, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20			= IOMUX_PAD(0x688, 0x224, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS			= IOMUX_PAD(0x68c, 0x228, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__IPU_DISPB_CS2				= IOMUX_PAD(0x68c, 0x228, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__GPIO1_4				= IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0		= IOMUX_PAD(0x68c, 0x228, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21			= IOMUX_PAD(0x68c, 0x228, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL			= IOMUX_PAD(0x690, 0x22c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__GPIO1_5				= IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1		= IOMUX_PAD(0x690, 0x22c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22			= IOMUX_PAD(0x690, 0x22c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_CMD__ESDHC1_CMD				= IOMUX_PAD(0x694, 0x230, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__MSHC_SCLK				= IOMUX_PAD(0x694, 0x230, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4			= IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__GPIO1_6				= IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL			= IOMUX_PAD(0x694, 0x230, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_CLK__ESDHC1_CLK				= IOMUX_PAD(0x698, 0x234, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__MSHC_BS				= IOMUX_PAD(0x698, 0x234, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__IPU_DISPB_BCLK			= IOMUX_PAD(0x698, 0x234, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5			= IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__GPIO1_7				= IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK			= IOMUX_PAD(0x698, 0x234, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA0__ESDHC1_DAT0				= IOMUX_PAD(0x69c, 0x238, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__MSHC_DATA_0				= IOMUX_PAD(0x69c, 0x238, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__IPU_DISPB_CS0			= IOMUX_PAD(0x69c, 0x238, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6		= IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__GPIO1_8				= IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23			= IOMUX_PAD(0x69c, 0x238, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA1__ESDHC1_DAT1				= IOMUX_PAD(0x6a0, 0x23c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__MSHC_DATA_1				= IOMUX_PAD(0x6a0, 0x23c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS			= IOMUX_PAD(0x6a0, 0x23c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0		= IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__GPIO1_9				= IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24			= IOMUX_PAD(0x6a0, 0x23c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA2__ESDHC1_DAT2				= IOMUX_PAD(0x6a4, 0x240, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__MSHC_DATA_2				= IOMUX_PAD(0x6a4, 0x240, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__IPU_DISPB_WR			= IOMUX_PAD(0x6a4, 0x240, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1		= IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__GPIO1_10				= IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25			= IOMUX_PAD(0x6a4, 0x240, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD1_DATA3__ESDHC1_DAT3				= IOMUX_PAD(0x6a8, 0x244, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__MSHC_DATA_3				= IOMUX_PAD(0x6a8, 0x244, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__IPU_DISPB_RD			= IOMUX_PAD(0x6a8, 0x244, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2		= IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__GPIO1_11				= IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL),
+	MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26			= IOMUX_PAD(0x6a8, 0x244, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_CMD__ESDHC2_CMD				= IOMUX_PAD(0x6ac, 0x248, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__I2C3_SCL				= IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__ESDHC1_DAT4				= IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__IPU_CSI_D_2				= IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4			= IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__GPIO2_0				= IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1			= IOMUX_PAD(0x6ac, 0x248, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_CLK__ESDHC2_CLK				= IOMUX_PAD(0x6b0, 0x24c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__I2C3_SDA				= IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__ESDHC1_DAT5				= IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__IPU_CSI_D_3				= IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5			= IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__GPIO2_1				= IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1			= IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL),
+	MX35_PAD_SD2_CLK__IPU_DISPB_CS2				= IOMUX_PAD(0x6b0, 0x24c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA0__ESDHC2_DAT0				= IOMUX_PAD(0x6b4, 0x250, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__UART3_RXD_MUX			= IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__ESDHC1_DAT6				= IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__IPU_CSI_D_4				= IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6		= IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__GPIO2_2				= IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA1__ESDHC2_DAT1				= IOMUX_PAD(0x6b8, 0x254, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__UART3_TXD_MUX			= IOMUX_PAD(0x6b8, 0x254, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__ESDHC1_DAT7				= IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__IPU_CSI_D_5				= IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0		= IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA1__GPIO2_3				= IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA2__ESDHC2_DAT2				= IOMUX_PAD(0x6bc, 0x258, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__UART3_RTS				= IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__CAN1_RXCAN				= IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__IPU_CSI_D_6				= IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1		= IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA2__GPIO2_4				= IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL),
+
+	MX35_PAD_SD2_DATA3__ESDHC2_DAT3				= IOMUX_PAD(0x6c0, 0x25c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__UART3_CTS				= IOMUX_PAD(0x6c0, 0x25c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__CAN1_TXCAN				= IOMUX_PAD(0x6c0, 0x25c, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__IPU_CSI_D_7				= IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2		= IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL),
+	MX35_PAD_SD2_DATA3__GPIO2_5				= IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_CS0__ATA_CS0				= IOMUX_PAD(0x6c4, 0x260, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__CSPI1_SS3				= IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__IPU_DISPB_CS1				= IOMUX_PAD(0x6c4, 0x260, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__GPIO2_6				= IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__IPU_DIAGB_0				= IOMUX_PAD(0x6c4, 0x260, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0		= IOMUX_PAD(0x6c4, 0x260, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_CS1__ATA_CS1				= IOMUX_PAD(0x6c8, 0x264, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__IPU_DISPB_CS2				= IOMUX_PAD(0x6c8, 0x264, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__CSPI2_SS0				= IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__GPIO2_7				= IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__IPU_DIAGB_1				= IOMUX_PAD(0x6c8, 0x264, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1		= IOMUX_PAD(0x6c8, 0x264, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DIOR__ATA_DIOR				= IOMUX_PAD(0x6cc, 0x268, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__ESDHC3_DAT0				= IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR			= IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__IPU_DISPB_BE0			= IOMUX_PAD(0x6cc, 0x268, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__CSPI2_SS1				= IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__GPIO2_8				= IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__IPU_DIAGB_2				= IOMUX_PAD(0x6cc, 0x268, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2		= IOMUX_PAD(0x6cc, 0x268, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DIOW__ATA_DIOW				= IOMUX_PAD(0x6d0, 0x26c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__ESDHC3_DAT1				= IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP			= IOMUX_PAD(0x6d0, 0x26c, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__IPU_DISPB_BE1			= IOMUX_PAD(0x6d0, 0x26c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__CSPI2_MOSI				= IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__GPIO2_9				= IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__IPU_DIAGB_3				= IOMUX_PAD(0x6d0, 0x26c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3		= IOMUX_PAD(0x6d0, 0x26c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DMACK__ATA_DMACK				= IOMUX_PAD(0x6d4, 0x270, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__ESDHC3_DAT2				= IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT			= IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__CSPI2_MISO				= IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__GPIO2_10				= IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__IPU_DIAGB_4				= IOMUX_PAD(0x6d4, 0x270, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0		= IOMUX_PAD(0x6d4, 0x270, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_RESET_B__ATA_RESET_B			= IOMUX_PAD(0x6d8, 0x274, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__ESDHC3_DAT3			= IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0		= IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O			= IOMUX_PAD(0x6d8, 0x274, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__CSPI2_RDY				= IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__GPIO2_11				= IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__IPU_DIAGB_5			= IOMUX_PAD(0x6d8, 0x274, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1		= IOMUX_PAD(0x6d8, 0x274, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_IORDY__ATA_IORDY				= IOMUX_PAD(0x6dc, 0x278, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__ESDHC3_DAT4				= IOMUX_PAD(0x6dc, 0x278, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1		= IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__ESDHC2_DAT4				= IOMUX_PAD(0x6dc, 0x278, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__GPIO2_12				= IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__IPU_DIAGB_6				= IOMUX_PAD(0x6dc, 0x278, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2		= IOMUX_PAD(0x6dc, 0x278, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA0__ATA_DATA_0				= IOMUX_PAD(0x6e0, 0x27c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__ESDHC3_DAT5				= IOMUX_PAD(0x6e0, 0x27c, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2		= IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC			= IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__ESDHC2_DAT5				= IOMUX_PAD(0x6e0, 0x27c, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__GPIO2_13				= IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__IPU_DIAGB_7				= IOMUX_PAD(0x6e0, 0x27c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3		= IOMUX_PAD(0x6e0, 0x27c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA1__ATA_DATA_1				= IOMUX_PAD(0x6e4, 0x280, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__ESDHC3_DAT6				= IOMUX_PAD(0x6e4, 0x280, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3		= IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK			= IOMUX_PAD(0x6e4, 0x280, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__ESDHC2_DAT6				= IOMUX_PAD(0x6e4, 0x280, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__GPIO2_14				= IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__IPU_DIAGB_8				= IOMUX_PAD(0x6e4, 0x280, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27			= IOMUX_PAD(0x6e4, 0x280, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA2__ATA_DATA_2				= IOMUX_PAD(0x6e8, 0x284, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__ESDHC3_DAT7				= IOMUX_PAD(0x6e8, 0x284, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4		= IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS			= IOMUX_PAD(0x6e8, 0x284, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__ESDHC2_DAT7				= IOMUX_PAD(0x6e8, 0x284, 4, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__GPIO2_15				= IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__IPU_DIAGB_9				= IOMUX_PAD(0x6e8, 0x284, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28			= IOMUX_PAD(0x6e8, 0x284, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA3__ATA_DATA_3				= IOMUX_PAD(0x6ec, 0x288, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__ESDHC3_CLK				= IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5		= IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__CSPI2_SCLK				= IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__GPIO2_16				= IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__IPU_DIAGB_10			= IOMUX_PAD(0x6ec, 0x288, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29			= IOMUX_PAD(0x6ec, 0x288, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA4__ATA_DATA_4				= IOMUX_PAD(0x6f0, 0x28c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__ESDHC3_CMD				= IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6		= IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__GPIO2_17				= IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__IPU_DIAGB_11			= IOMUX_PAD(0x6f0, 0x28c, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30			= IOMUX_PAD(0x6f0, 0x28c, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA5__ATA_DATA_5				= IOMUX_PAD(0x6f4, 0x290, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7		= IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__GPIO2_18				= IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__IPU_DIAGB_12			= IOMUX_PAD(0x6f4, 0x290, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31			= IOMUX_PAD(0x6f4, 0x290, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA6__ATA_DATA_6				= IOMUX_PAD(0x6f8, 0x294, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__CAN1_TXCAN				= IOMUX_PAD(0x6f8, 0x294, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__UART1_DTR				= IOMUX_PAD(0x6f8, 0x294, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD			= IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__GPIO2_19				= IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA6__IPU_DIAGB_13			= IOMUX_PAD(0x6f8, 0x294, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA7__ATA_DATA_7				= IOMUX_PAD(0x6fc, 0x298, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__CAN1_RXCAN				= IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__UART1_DSR				= IOMUX_PAD(0x6fc, 0x298, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD			= IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__GPIO2_20				= IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA7__IPU_DIAGB_14			= IOMUX_PAD(0x6fc, 0x298, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA8__ATA_DATA_8				= IOMUX_PAD(0x700, 0x29c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__UART3_RTS				= IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__UART1_RI				= IOMUX_PAD(0x700, 0x29c, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC			= IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__GPIO2_21				= IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA8__IPU_DIAGB_15			= IOMUX_PAD(0x700, 0x29c, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA9__ATA_DATA_9				= IOMUX_PAD(0x704, 0x2a0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__UART3_CTS				= IOMUX_PAD(0x704, 0x2a0, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__UART1_DCD				= IOMUX_PAD(0x704, 0x2a0, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS			= IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__GPIO2_22				= IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA9__IPU_DIAGB_16			= IOMUX_PAD(0x704, 0x2a0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA10__ATA_DATA_10			= IOMUX_PAD(0x708, 0x2a4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__UART3_RXD_MUX			= IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC			= IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__GPIO2_23				= IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA10__IPU_DIAGB_17			= IOMUX_PAD(0x708, 0x2a4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA11__ATA_DATA_11			= IOMUX_PAD(0x70c, 0x2a8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__UART3_TXD_MUX			= IOMUX_PAD(0x70c, 0x2a8, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS			= IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__GPIO2_24				= IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA11__IPU_DIAGB_18			= IOMUX_PAD(0x70c, 0x2a8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA12__ATA_DATA_12			= IOMUX_PAD(0x710, 0x2ac, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA12__I2C3_SCL				= IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA12__GPIO2_25				= IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA12__IPU_DIAGB_19			= IOMUX_PAD(0x710, 0x2ac, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA13__ATA_DATA_13			= IOMUX_PAD(0x714, 0x2b0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA13__I2C3_SDA				= IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA13__GPIO2_26				= IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA13__IPU_DIAGB_20			= IOMUX_PAD(0x714, 0x2b0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA14__ATA_DATA_14			= IOMUX_PAD(0x718, 0x2b4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__IPU_CSI_D_0			= IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__KPP_ROW_0				= IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__GPIO2_27				= IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA14__IPU_DIAGB_21			= IOMUX_PAD(0x718, 0x2b4, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DATA15__ATA_DATA_15			= IOMUX_PAD(0x71c, 0x2b8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__IPU_CSI_D_1			= IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__KPP_ROW_1				= IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__GPIO2_28				= IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DATA15__IPU_DIAGB_22			= IOMUX_PAD(0x71c, 0x2b8, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_INTRQ__ATA_INTRQ				= IOMUX_PAD(0x720, 0x2bc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__IPU_CSI_D_2				= IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__KPP_ROW_2				= IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__GPIO2_29				= IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_INTRQ__IPU_DIAGB_23			= IOMUX_PAD(0x720, 0x2bc, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN			= IOMUX_PAD(0x724, 0x2c0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3			= IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__KPP_ROW_3				= IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__GPIO2_30				= IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24			= IOMUX_PAD(0x724, 0x2c0, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DMARQ__ATA_DMARQ				= IOMUX_PAD(0x728, 0x2c4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__IPU_CSI_D_4				= IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__KPP_COL_0				= IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__GPIO2_31				= IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__IPU_DIAGB_25			= IOMUX_PAD(0x728, 0x2c4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4			= IOMUX_PAD(0x728, 0x2c4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DA0__ATA_DA_0				= IOMUX_PAD(0x72c, 0x2c8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__IPU_CSI_D_5				= IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__KPP_COL_1				= IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__GPIO3_0				= IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__IPU_DIAGB_26				= IOMUX_PAD(0x72c, 0x2c8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5			= IOMUX_PAD(0x72c, 0x2c8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DA1__ATA_DA_1				= IOMUX_PAD(0x730, 0x2cc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__IPU_CSI_D_6				= IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__KPP_COL_2				= IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__GPIO3_1				= IOMUX_PAD(0x730, 0x2cc, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__IPU_DIAGB_27				= IOMUX_PAD(0x730, 0x2cc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6			= IOMUX_PAD(0x730, 0x2cc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_ATA_DA2__ATA_DA_2				= IOMUX_PAD(0x734, 0x2d0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__IPU_CSI_D_7				= IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__KPP_COL_3				= IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__GPIO3_2				= IOMUX_PAD(0x734, 0x2d0, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__IPU_DIAGB_28				= IOMUX_PAD(0x734, 0x2d0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7			= IOMUX_PAD(0x734, 0x2d0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_MLB_CLK__MLB_MLBCLK				= IOMUX_PAD(0x738, 0x2d4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_MLB_CLK__GPIO3_3				= IOMUX_PAD(0x738, 0x2d4, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_MLB_DAT__MLB_MLBDAT				= IOMUX_PAD(0x73c, 0x2d8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_MLB_DAT__GPIO3_4				= IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL),
+
+	MX35_PAD_MLB_SIG__MLB_MLBSIG				= IOMUX_PAD(0x740, 0x2dc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_MLB_SIG__GPIO3_5				= IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK				= IOMUX_PAD(0x744, 0x2e0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4			= IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX			= IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR			= IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__CSPI2_MOSI				= IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__GPIO3_6				= IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC		= IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0		= IOMUX_PAD(0x744, 0x2e0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK				= IOMUX_PAD(0x748, 0x2e4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5			= IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX			= IOMUX_PAD(0x748, 0x2e4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP			= IOMUX_PAD(0x748, 0x2e4, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__CSPI2_MISO				= IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__GPIO3_7				= IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I			= IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1		= IOMUX_PAD(0x748, 0x2e4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RX_DV__FEC_RX_DV				= IOMUX_PAD(0x74c, 0x2e8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__ESDHC1_DAT6				= IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__UART3_RTS				= IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT			= IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__CSPI2_SCLK				= IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__GPIO3_8				= IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK			= IOMUX_PAD(0x74c, 0x2e8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2		= IOMUX_PAD(0x74c, 0x2e8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_COL__FEC_COL				= IOMUX_PAD(0x750, 0x2ec, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__ESDHC1_DAT7				= IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__UART3_CTS				= IOMUX_PAD(0x750, 0x2ec, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0			= IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__CSPI2_RDY				= IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__GPIO3_9				= IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__IPU_DISPB_SER_RS			= IOMUX_PAD(0x750, 0x2ec, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3			= IOMUX_PAD(0x750, 0x2ec, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA0__FEC_RDATA_0			= IOMUX_PAD(0x754, 0x2f0, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__PWM_PWMO				= IOMUX_PAD(0x754, 0x2f0, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__UART3_DTR				= IOMUX_PAD(0x754, 0x2f0, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1		= IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__CSPI2_SS0				= IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__GPIO3_10				= IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1			= IOMUX_PAD(0x754, 0x2f0, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4		= IOMUX_PAD(0x754, 0x2f0, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA0__FEC_TDATA_0			= IOMUX_PAD(0x758, 0x2f4, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1			= IOMUX_PAD(0x758, 0x2f4, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__UART3_DSR				= IOMUX_PAD(0x758, 0x2f4, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2		= IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__CSPI2_SS1				= IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__GPIO3_11				= IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0			= IOMUX_PAD(0x758, 0x2f4, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5		= IOMUX_PAD(0x758, 0x2f4, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TX_EN__FEC_TX_EN				= IOMUX_PAD(0x75c, 0x2f8, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1			= IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__UART3_RI				= IOMUX_PAD(0x75c, 0x2f8, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3		= IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__GPIO3_12				= IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS			= IOMUX_PAD(0x75c, 0x2f8, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6		= IOMUX_PAD(0x75c, 0x2f8, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_MDC__FEC_MDC				= IOMUX_PAD(0x760, 0x2fc, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__CAN2_TXCAN				= IOMUX_PAD(0x760, 0x2fc, 1, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__UART3_DCD				= IOMUX_PAD(0x760, 0x2fc, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4			= IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__GPIO3_13				= IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__IPU_DISPB_WR				= IOMUX_PAD(0x760, 0x2fc, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7			= IOMUX_PAD(0x760, 0x2fc, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_MDIO__FEC_MDIO				= IOMUX_PAD(0x764, 0x300, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__CAN2_RXCAN				= IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5			= IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__GPIO3_14				= IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__IPU_DISPB_RD				= IOMUX_PAD(0x764, 0x300, 6, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8			= IOMUX_PAD(0x764, 0x300, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR				= IOMUX_PAD(0x768, 0x304, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__OWIRE_LINE				= IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK			= IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6		= IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__GPIO3_15				= IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC			= IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9		= IOMUX_PAD(0x768, 0x304, 7, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR				= IOMUX_PAD(0x76c, 0x308, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0			= IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7		= IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__KPP_COL_4				= IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__GPIO3_16				= IOMUX_PAD(0x76c, 0x308, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO			= IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_CRS__FEC_CRS				= IOMUX_PAD(0x770, 0x30c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__IPU_CSI_D_1				= IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR			= IOMUX_PAD(0x770, 0x30c, 3, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__KPP_COL_5				= IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__GPIO3_17				= IOMUX_PAD(0x770, 0x30c, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_CRS__IPU_FLASH_STROBE			= IOMUX_PAD(0x770, 0x30c, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA1__FEC_RDATA_1			= IOMUX_PAD(0x774, 0x310, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__IPU_CSI_D_2			= IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC			= IOMUX_PAD(0x774, 0x310, 2, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC			= IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__KPP_COL_6				= IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__GPIO3_18				= IOMUX_PAD(0x774, 0x310, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0			= IOMUX_PAD(0x774, 0x310, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA1__FEC_TDATA_1			= IOMUX_PAD(0x778, 0x314, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__IPU_CSI_D_3			= IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS			= IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__KPP_COL_7				= IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__GPIO3_19				= IOMUX_PAD(0x778, 0x314, 5, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1			= IOMUX_PAD(0x778, 0x314, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA2__FEC_RDATA_2			= IOMUX_PAD(0x77c, 0x318, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__IPU_CSI_D_4			= IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD			= IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__KPP_ROW_4				= IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA2__GPIO3_20				= IOMUX_PAD(0x77c, 0x318, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA2__FEC_TDATA_2			= IOMUX_PAD(0x780, 0x31c, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__IPU_CSI_D_5			= IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD			= IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__KPP_ROW_5				= IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA2__GPIO3_21				= IOMUX_PAD(0x780, 0x31c, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_RDATA3__FEC_RDATA_3			= IOMUX_PAD(0x784, 0x320, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__IPU_CSI_D_6			= IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC			= IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__KPP_ROW_6				= IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_RDATA3__GPIO3_22				= IOMUX_PAD(0x784, 0x320, 6, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_FEC_TDATA3__FEC_TDATA_3			= IOMUX_PAD(0x788, 0x324, 0, 0x0,   0, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__IPU_CSI_D_7			= IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS			= IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__KPP_ROW_7				= IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL),
+	MX35_PAD_FEC_TDATA3__GPIO3_23				= IOMUX_PAD(0x788, 0x324, 5, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK			= IOMUX_PAD(0x78c, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+
+	MX35_PAD_TEST_MODE__TCU_TEST_MODE			= IOMUX_PAD(0x790, 0x0,   0, 0x0,   0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX35_H__ */
diff --git a/arch/arm/include/asm/arch-mx35/lowlevel_macro.S b/arch/arm/include/asm/arch-mx35/lowlevel_macro.S
new file mode 100644
index 0000000..4b1c9f8
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/lowlevel_macro.S
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+#include <asm/macro.h>
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ *
+ * Default argument values:
+ *  - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
+ *    user-mode.
+ *  - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
+ *    SDMA to access them.
+ */
+.macro init_aips mpr=0x77777777, opacr=0x00000000
+	ldr	r0, =AIPS1_BASE_ADDR
+	ldr	r1, =\mpr
+	str	r1, [r0, #AIPS_MPR_0_7]
+	str	r1, [r0, #AIPS_MPR_8_15]
+	ldr	r2, =AIPS2_BASE_ADDR
+	str	r1, [r2, #AIPS_MPR_0_7]
+	str	r1, [r2, #AIPS_MPR_8_15]
+
+	/* Did not change the AIPS control registers access type. */
+	ldr	r1, =\opacr
+	str	r1, [r0, #AIPS_OPACR_0_7]
+	str	r1, [r0, #AIPS_OPACR_8_15]
+	str	r1, [r0, #AIPS_OPACR_16_23]
+	str	r1, [r0, #AIPS_OPACR_24_31]
+	str	r1, [r0, #AIPS_OPACR_32_39]
+	str	r1, [r2, #AIPS_OPACR_0_7]
+	str	r1, [r2, #AIPS_OPACR_8_15]
+	str	r1, [r2, #AIPS_OPACR_16_23]
+	str	r1, [r2, #AIPS_OPACR_24_31]
+	str	r1, [r2, #AIPS_OPACR_32_39]
+.endm
+
+/*
+ * MAX (Multi-Layer AHB Crossbar Switch) setup
+ *
+ * Default argument values:
+ *  - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
+ *  - SGPCR: always park on last master
+ *  - MGPCR: restore default values
+ */
+.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
+	ldr	r0, =MAX_BASE_ADDR
+	ldr	r1, =\mpr
+	str	r1, [r0, #MAX_MPR0]	/* for S0 */
+	str	r1, [r0, #MAX_MPR1]	/* for S1 */
+	str	r1, [r0, #MAX_MPR2]	/* for S2 */
+	str	r1, [r0, #MAX_MPR3]	/* for S3 */
+	str	r1, [r0, #MAX_MPR4]	/* for S4 */
+	ldr	r1, =\sgpcr
+	str	r1, [r0, #MAX_SGPCR0]	/* for S0 */
+	str	r1, [r0, #MAX_SGPCR1]	/* for S1 */
+	str	r1, [r0, #MAX_SGPCR2]	/* for S2 */
+	str	r1, [r0, #MAX_SGPCR3]	/* for S3 */
+	str	r1, [r0, #MAX_SGPCR4]	/* for S4 */
+	ldr	r1, =\mgpcr
+	str	r1, [r0, #MAX_MGPCR0]	/* for M0 */
+	str	r1, [r0, #MAX_MGPCR1]	/* for M1 */
+	str	r1, [r0, #MAX_MGPCR2]	/* for M2 */
+	str	r1, [r0, #MAX_MGPCR3]	/* for M3 */
+	str	r1, [r0, #MAX_MGPCR4]	/* for M4 */
+	str	r1, [r0, #MAX_MGPCR5]	/* for M5 */
+.endm
+
+/*
+ * M3IF setup
+ *
+ * Default argument values:
+ *  - CTL:
+ * MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 1)	= 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 2)		= 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 3)		= 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 4)		= 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 5)	= 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6)		= 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 7)		= 0x00000000
+ *							------------
+ *							  0x00000040
+ */
+.macro init_m3if ctl=0x00000040
+	/* M3IF Control Register (M3IFCTL) */
+	write32	M3IF_BASE_ADDR, \ctl
+.endm
+
+.macro core_init
+	mrc	p15, 0, r1, c1, c0, 0
+
+	/* Set branch prediction enable */
+	mrc	p15, 0, r0, c1, c0, 1
+	orr	r0, r0, #7
+	mcr	p15, 0, r0, c1, c0, 1
+	orr	r1, r1, #1 << 11
+
+	/* Set unaligned access enable */
+	orr	r1, r1, #1 << 22
+
+	/* Set low int latency enable */
+	orr	r1, r1, #1 << 21
+
+	mcr	p15, 0, r1, c1, c0, 0
+
+	mov	r0, #0
+
+	mcr	p15, 0, r0, c15, c2, 4
+
+	mcr	p15, 0, r0, c7, c7, 0	/* Invalidate I cache and D cache */
+	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate TLBs */
+	mcr	p15, 0, r0, c7, c10, 4	/* Drain the write buffer */
+
+	/* Setup the Peripheral Port Memory Remap Register */
+	ldr	r0, =0x40000015		/* Start from AIPS 2-GB region */
+	mcr	p15, 0, r0, c15, c2, 4
+.endm
diff --git a/arch/arm/include/asm/arch-mx35/mmc_host_def.h b/arch/arm/include/asm/arch-mx35/mmc_host_def.h
new file mode 100644
index 0000000..81c19bb
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/mmc_host_def.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE		512
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-mx35/sys_proto.h b/arch/arm/include/asm/arch-mx35/sys_proto.h
new file mode 100644
index 0000000..6e8b841
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/sys_proto.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ */
+
+#ifndef _MX35_SYS_PROTO_H_
+#define _MX35_SYS_PROTO_H_
+
+#include <asm/mach-imx/sys_proto.h>
+
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row,
+			  u32 col, u32 dsize, u32 refresh);
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
new file mode 100644
index 0000000..6f5ca58
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+#ifdef CONFIG_SYS_MX5_HCLK
+#define MXC_HCLK	CONFIG_SYS_MX5_HCLK
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_SYS_MX5_CLK32
+#define MXC_CLK32	CONFIG_SYS_MX5_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_IPG_PERCLK,
+	MXC_UART_CLK,
+	MXC_CSPI_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_ESDHC4_CLK,
+	MXC_FEC_CLK,
+	MXC_SATA_CLK,
+	MXC_DDR_CLK,
+	MXC_NFC_CLK,
+	MXC_PERIPH_CLK,
+	MXC_I2C_CLK,
+	MXC_LDB_CLK,
+};
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
+void set_usb_phy_clk(void);
+void enable_usb_phy1_clk(bool enable);
+void enable_usb_phy2_clk(bool enable);
+void set_usboh3_clk(void);
+void enable_usboh3_clk(bool enable);
+void mxc_set_sata_internal_clock(void);
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+void enable_nfc_clk(unsigned char enable);
+void enable_efuse_prog_supply(bool enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
new file mode 100644
index 0000000..9d54ab7
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -0,0 +1,616 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+#define MXC_CCM_BASE	CCM_BASE_ADDR
+
+/* DPLL register mapping structure */
+struct mxc_pll_reg {
+	u32 ctrl;
+	u32 config;
+	u32 op;
+	u32 mfd;
+	u32 mfn;
+	u32 mfn_minus;
+	u32 mfn_plus;
+	u32 hfs_op;
+	u32 hfs_mfd;
+	u32 hfs_mfn;
+	u32 mfn_togc;
+	u32 destat;
+};
+
+/* Register maping of CCM*/
+struct mxc_ccm_reg {
+	u32 ccr;	/* 0x0000 */
+	u32 ccdr;
+	u32 csr;
+	u32 ccsr;
+	u32 cacrr;	/* 0x0010*/
+	u32 cbcdr;
+	u32 cbcmr;
+	u32 cscmr1;
+	u32 cscmr2;	/* 0x0020 */
+	u32 cscdr1;
+	u32 cs1cdr;
+	u32 cs2cdr;
+	u32 cdcdr;	/* 0x0030 */
+	u32 chsccdr;
+	u32 cscdr2;
+	u32 cscdr3;
+	u32 cscdr4;	/* 0x0040 */
+	u32 cwdr;
+	u32 cdhipr;
+	u32 cdcr;
+	u32 ctor;	/* 0x0050 */
+	u32 clpcr;
+	u32 cisr;
+	u32 cimr;
+	u32 ccosr;	/* 0x0060 */
+	u32 cgpr;
+	u32 CCGR0;
+	u32 CCGR1;
+	u32 CCGR2;	/* 0x0070 */
+	u32 CCGR3;
+	u32 CCGR4;
+	u32 CCGR5;
+	u32 CCGR6;	/* 0x0080 */
+#ifdef CONFIG_MX53
+	u32 CCGR7;      /* 0x0084 */
+#endif
+	u32 cmeor;
+};
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN			(0x1 << 12)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_MULT			(0x1 << 11)
+#endif
+#define MXC_CCM_CCR_CAMP2_EN			(0x1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN			(0x1 << 9)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_EN			(0x1 << 8)
+#endif
+#define MXC_CCM_CCR_OSCNT_OFFSET		0
+#define MXC_CCM_CCR_OSCNT_MASK			0xFF
+#define MXC_CCM_CCR_OSCNT(v)			((v) & 0xFF)
+#define MXC_CCM_CCR_OSCNT_RD(r)			((r) & 0xFF)
+
+/* Define the bits in register CCSR */
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCSR_LP_APM			(0x1 << 9)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCSR_LP_APM			(0x1 << 10)
+#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL		(0x1 << 9)
+#endif
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET		7
+#define MXC_CCM_CCSR_STEP_SEL_MASK		(0x3 << 7)
+#define MXC_CCM_CCSR_STEP_SEL(v)		(((v) & 0x3) << 7)
+#define MXC_CCM_CCSR_STEP_SEL_RD(r)		(((r) >> 7) & 0x3)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET	5
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK		(0x3 << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF(v)		(((v) & 0x3) << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r)	(((r) >> 5) & 0x3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET	3
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK		(0x3 << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF(v)		(((v) & 0x3) << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r)	(((r) >> 3) & 0x3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL		(0x1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL		(0x1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL		0x1
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
+#define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
+#define MXC_CCM_CACRR_ARM_PODF(v)		((v) & 0x7)
+#define MXC_CCM_CACRR_ARM_PODF_RD(r)		((r) & 0x7)
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL		(0x1 << 30)
+#define MXC_CCM_CBCDR_DDR_PODF_OFFSET		27
+#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF(v)		(((v) & 0x7) << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_RD(r)		(((r) >> 27) & 0x7)
+#define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
+#define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
+#define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
+#define MXC_CCM_CBCDR_EMI_PODF(v)		(((v) & 0x7) << 22)
+#define MXC_CCM_CBCDR_EMI_PODF_RD(r)		(((r) >> 22) & 0x7)
+#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		19
+#define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF(v)		(((v) & 0x7) << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r)		(((r) >> 19) & 0x7)
+#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		16
+#define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF(v)		(((v) & 0x7) << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r)		(((r) >> 16) & 0x7)
+#define MXC_CCM_CBCDR_NFC_PODF_OFFSET		13
+#define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
+#define MXC_CCM_CBCDR_NFC_PODF(v)		(((v) & 0x7) << 13)
+#define MXC_CCM_CBCDR_NFC_PODF_RD(r)		(((r) >> 13) & 0x7)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET		10
+#define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF(v)		(((v) & 0x7) << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_RD(r)		(((r) >> 10) & 0x7)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET		8
+#define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_RD(r)		(((r) >> 8) & 0x3)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	6
+#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r)	(((r) >> 6) & 0x3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	3
+#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2(v)		(((v) & 0x7) << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r)	(((r) >> 3) & 0x7)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	0
+#define MXC_CCM_CBCDR_PERCLK_PODF_MASK		0x7
+#define MXC_CCM_CBCDR_PERCLK_PODF(v)		((v) & 0x7)
+#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r)		((r) & 0x7)
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		30
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v)		(((v) & 0x3) << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r)		(((r) >> 30) & 0x3)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		28
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v)		(((v) & 0x3) << 28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r)		(((r) >> 28) & 0x3)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		24
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r)		(((r) >> 24) & 0x3)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		22
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v)		(((v) & 0x3) << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r)		(((r) >> 22) & 0x3)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	20
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v)		(((v) & 0x3) << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r)	(((r) >> 20) & 0x3)
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	16
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v)		(((v) & 0x3) << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r)	(((r) >> 16) & 0x3)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		14
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		8
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
+#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		4
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r)		(((r) >> 4) & 0x3)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		2
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r)		(((r) >> 2) & 0x3)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		0x1
+
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_OFFSET		26
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_MASK		(0x7 << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL(v)		(((v) & 0x7) << 26)
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_RD(r)	(((r) >> 26) & 0x7)
+
+#define MXC_CCM_CSCMR2_DI0_CLK_SEL_LDB_DI0_CLK 5
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		25
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v)			(((v) & 0x7) << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r)		(((r) >> 25) & 0x7)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		19
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v)			(((v) & 0x3F) << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r)		(((r) >> 19) & 0x3F)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		16
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v)			(((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r)		(((r) >> 16) & 0x7)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		9
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v)			(((v) & 0x3F) << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r)		(((r) >> 9) & 0x3F)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		6
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v)		(((v) & 0x7) << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r)		(((r) >> 6) & 0x7)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET		0
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK		0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v)		((v) & 0x3F)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r)		((r) & 0x3F)
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v)		(((v) & 0x3) << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		12
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET		10
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK			(0x3 << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r)			(((r) >> 10) & 0x3)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET		8
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET		6
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r)		(((r) >> 6) & 0x3)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		4
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK			(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r)			(((r) >> 4) & 0x3)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	22
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v)		(((v) & 0x7) << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r)	(((r) >> 22) & 0x7)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	19
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v)		(((v) & 0x7) << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r)	(((r) >> 19) & 0x7)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	16
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v)		(((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r)	(((r) >> 16) & 0x7)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		14
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r)		(((r) >> 14) & 0x3)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	11
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v)		(((v) & 0x7) << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r)	(((r) >> 11) & 0x7)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v)		(((v) & 0x7) << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r)		(((r) >> 8) & 0x7)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r)		(((r) >> 6) & 0x3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		3
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED(v)			(((v) & 0x7) << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r)		(((r) >> 3) & 0x7)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
+#define MXC_CCM_CSCDR1_UART_CLK_PODF(v)			((v) & 0x7)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r)		((r) & 0x7)
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_IPU_HS_MASK			(0x1 << 17)
+
+/* Define the bits in register CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(1 << 4)
+
+/* Define the bits in register CCGRx */
+#define MXC_CCM_CCGR_CG_MASK				0x3
+#define MXC_CCM_CCGR_CG_OFF				0x0
+#define MXC_CCM_CCGR_CG_RUN_ON				0x1
+#define MXC_CCM_CCGR_CG_ON				0x3
+
+#define MXC_CCM_CCGR0_ARM_BUS_OFFSET			0
+#define MXC_CCM_CCGR0_ARM_BUS(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR0_ARM_AXI_OFFSET			2
+#define MXC_CCM_CCGR0_ARM_AXI(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET			4
+#define MXC_CCM_CCGR0_ARM_DEBUG(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR0_TZIC_OFFSET			6
+#define MXC_CCM_CCGR0_TZIC(v)				(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR0_DAP_OFFSET			8
+#define MXC_CCM_CCGR0_DAP(v)				(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR0_TPIU_OFFSET			10
+#define MXC_CCM_CCGR0_TPIU(v)				(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR0_CTI2_OFFSET			12
+#define MXC_CCM_CCGR0_CTI2(v)				(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR0_CTI3_OFFSET			14
+#define MXC_CCM_CCGR0_CTI3(v)				(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR0_AHBMUX1_OFFSET			16
+#define MXC_CCM_CCGR0_AHBMUX1(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR0_AHBMUX2_OFFSET			18
+#define MXC_CCM_CCGR0_AHBMUX2(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR0_ROMCP_OFFSET			20
+#define MXC_CCM_CCGR0_ROMCP(v)				(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR0_ROM_OFFSET			22
+#define MXC_CCM_CCGR0_ROM(v)				(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			24
+#define MXC_CCM_CCGR0_AIPS_TZ1(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			26
+#define MXC_CCM_CCGR0_AIPS_TZ2(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR0_AHB_MAX_OFFSET			28
+#define MXC_CCM_CCGR0_AHB_MAX(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR0_IIM_OFFSET			30
+#define MXC_CCM_CCGR0_IIM(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR1_TMAX1_OFFSET			0
+#define MXC_CCM_CCGR1_TMAX1(v)				(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR1_TMAX2_OFFSET			2
+#define MXC_CCM_CCGR1_TMAX2(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR1_TMAX3_OFFSET			4
+#define MXC_CCM_CCGR1_TMAX3(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR1_UART1_IPG_OFFSET			6
+#define MXC_CCM_CCGR1_UART1_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR1_UART1_PER_OFFSET			8
+#define MXC_CCM_CCGR1_UART1_PER(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR1_UART2_IPG_OFFSET			10
+#define MXC_CCM_CCGR1_UART2_IPG(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR1_UART2_PER_OFFSET			12
+#define MXC_CCM_CCGR1_UART2_PER(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR1_UART3_IPG_OFFSET			14
+#define MXC_CCM_CCGR1_UART3_IPG(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR1_UART3_PER_OFFSET			16
+#define MXC_CCM_CCGR1_UART3_PER(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR1_I2C1_OFFSET			18
+#define MXC_CCM_CCGR1_I2C1(v)				(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR1_I2C2_OFFSET			20
+#define MXC_CCM_CCGR1_I2C2(v)				(((v) & 0x3) << 20)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET			22
+#define MXC_CCM_CCGR1_HSI2C_IPG(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET		24
+#define MXC_CCM_CCGR1_HSI2C_SERIAL(v)			(((v) & 0x3) << 24)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR1_I2C3_OFFSET			22
+#define MXC_CCM_CCGR1_I2C3(v)				(((v) & 0x3) << 22)
+#endif
+#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET			26
+#define MXC_CCM_CCGR1_FIRI_IPG(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET		28
+#define MXC_CCM_CCGR1_FIRI_SERIAL(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR1_SCC_OFFSET			30
+#define MXC_CCM_CCGR1_SCC(v)				(((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR2_USB_PHY_OFFSET			0
+#define MXC_CCM_CCGR2_USB_PHY(v)			(((v) & 0x3) << 0)
+#endif
+#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET			2
+#define MXC_CCM_CCGR2_EPIT1_IPG(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET			4
+#define MXC_CCM_CCGR2_EPIT1_HF(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET			6
+#define MXC_CCM_CCGR2_EPIT2_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET			8
+#define MXC_CCM_CCGR2_EPIT2_HF(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET			10
+#define MXC_CCM_CCGR2_PWM1_IPG(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR2_PWM1_HF_OFFSET			12
+#define MXC_CCM_CCGR2_PWM1_HF(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET			14
+#define MXC_CCM_CCGR2_PWM2_IPG(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR2_PWM2_HF_OFFSET			16
+#define MXC_CCM_CCGR2_PWM2_HF(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR2_GPT_IPG_OFFSET			18
+#define MXC_CCM_CCGR2_GPT_IPG(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR2_GPT_HF_OFFSET			20
+#define MXC_CCM_CCGR2_GPT_HF(v)				(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR2_OWIRE_OFFSET			22
+#define MXC_CCM_CCGR2_OWIRE(v)				(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR2_FEC_OFFSET			24
+#define MXC_CCM_CCGR2_FEC(v)				(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET		26
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET			28
+#define MXC_CCM_CCGR2_USBOH3_60M(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR2_TVE_OFFSET			30
+#define MXC_CCM_CCGR2_TVE(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET			0
+#define MXC_CCM_CCGR3_ESDHC1_IPG(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET			2
+#define MXC_CCM_CCGR3_ESDHC1_PER(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET			4
+#define MXC_CCM_CCGR3_ESDHC2_IPG(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET			6
+#define MXC_CCM_CCGR3_ESDHC2_PER(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET			8
+#define MXC_CCM_CCGR3_ESDHC3_IPG(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET			10
+#define MXC_CCM_CCGR3_ESDHC3_PER(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET			12
+#define MXC_CCM_CCGR3_ESDHC4_IPG(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET			14
+#define MXC_CCM_CCGR3_ESDHC4_PER(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET			16
+#define MXC_CCM_CCGR3_SSI1_IPG(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET			18
+#define MXC_CCM_CCGR3_SSI1_SSI(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET			20
+#define MXC_CCM_CCGR3_SSI2_IPG(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET			22
+#define MXC_CCM_CCGR3_SSI2_SSI(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET			24
+#define MXC_CCM_CCGR3_SSI3_IPG(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET			26
+#define MXC_CCM_CCGR3_SSI3_SSI(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET			28
+#define MXC_CCM_CCGR3_SSI_EXT1(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET			30
+#define MXC_CCM_CCGR3_SSI_EXT2(v)			(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR4_PATA_OFFSET			0
+#define MXC_CCM_CCGR4_PATA(v)				(((v) & 0x3) << 0)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR4_SIM_IPG_OFFSET			2
+#define MXC_CCM_CCGR4_SIM_IPG(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET			4
+#define MXC_CCM_CCGR4_SIM_SERIAL(v)			(((v) & 0x3) << 4)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR4_SATA_OFFSET			2
+#define MXC_CCM_CCGR4_SATA(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET			6
+#define MXC_CCM_CCGR4_CAN2_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET		8
+#define MXC_CCM_CCGR4_CAN2_SERIAL(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR4_USB_PHY1_OFFSET			10
+#define MXC_CCM_CCGR4_USB_PHY1(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR4_USB_PHY2_OFFSET			12
+#define MXC_CCM_CCGR4_USB_PHY2(v)			(((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR4_SAHARA_OFFSET			14
+#define MXC_CCM_CCGR4_SAHARA(v)				(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR4_RTIC_OFFSET			16
+#define MXC_CCM_CCGR4_RTIC(v)				(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET			18
+#define MXC_CCM_CCGR4_ECSPI1_IPG(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET			20
+#define MXC_CCM_CCGR4_ECSPI1_PER(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET			22
+#define MXC_CCM_CCGR4_ECSPI2_IPG(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET			24
+#define MXC_CCM_CCGR4_ECSPI2_PER(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET			26
+#define MXC_CCM_CCGR4_CSPI_IPG(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR4_SRTC_OFFSET			28
+#define MXC_CCM_CCGR4_SRTC(v)				(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR4_SDMA_OFFSET			30
+#define MXC_CCM_CCGR4_SDMA(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR5_SPBA_OFFSET			0
+#define MXC_CCM_CCGR5_SPBA(v)				(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR5_GPU_OFFSET			2
+#define MXC_CCM_CCGR5_GPU(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR5_GARB_OFFSET			4
+#define MXC_CCM_CCGR5_GARB(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR5_VPU_OFFSET			6
+#define MXC_CCM_CCGR5_VPU(v)				(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR5_VPU_REF_OFFSET			8
+#define MXC_CCM_CCGR5_VPU_REF(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR5_IPU_OFFSET			10
+#define MXC_CCM_CCGR5_IPU(v)				(((v) & 0x3) << 10)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_IPUMUX12_OFFSET			12
+#define MXC_CCM_CCGR5_IPUMUX12(v)			(((v) & 0x3) << 12)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR5_IPUMUX1_OFFSET			12
+#define MXC_CCM_CCGR5_IPUMUX1(v)			(((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR5_EMI_FAST_OFFSET			14
+#define MXC_CCM_CCGR5_EMI_FAST(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET			16
+#define MXC_CCM_CCGR5_EMI_SLOW(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR5_EMI_INT1_OFFSET			18
+#define MXC_CCM_CCGR5_EMI_INT1(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET			20
+#define MXC_CCM_CCGR5_EMI_ENFC(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET			22
+#define MXC_CCM_CCGR5_EMI_WRCK(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR5_GPC_IPG_OFFSET			24
+#define MXC_CCM_CCGR5_GPC_IPG(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR5_SPDIF0_OFFSET			26
+#define MXC_CCM_CCGR5_SPDIF0(v)				(((v) & 0x3) << 26)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_SPDIF1_OFFSET			28
+#define MXC_CCM_CCGR5_SPDIF1(v)				(((v) & 0x3) << 28)
+#endif
+#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET			30
+#define MXC_CCM_CCGR5_SPDIF_IPG(v)			(((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_IPUMUX2_OFFSET			0
+#define MXC_CCM_CCGR6_IPUMUX2(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR6_OCRAM_OFFSET			2
+#define MXC_CCM_CCGR6_OCRAM(v)				(((v) & 0x3) << 2)
+#endif
+#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET			4
+#define MXC_CCM_CCGR6_CSI_MCLK1(v)			(((v) & 0x3) << 4)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET			6
+#define MXC_CCM_CCGR6_CSI_MCLK2(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR6_EMI_GARB_OFFSET			8
+#define MXC_CCM_CCGR6_EMI_GARB(v)			(((v) & 0x3) << 8)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_EMI_INT2_OFFSET			8
+#define MXC_CCM_CCGR6_EMI_INT2(v)			(((v) & 0x3) << 8)
+#endif
+#define MXC_CCM_CCGR6_IPU_DI0_OFFSET			10
+#define MXC_CCM_CCGR6_IPU_DI0(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR6_IPU_DI1_OFFSET			12
+#define MXC_CCM_CCGR6_IPU_DI1(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR6_GPU2D_OFFSET			14
+#define MXC_CCM_CCGR6_GPU2D(v)				(((v) & 0x3) << 14)
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET			16
+#define MXC_CCM_CCGR6_ESAI_IPG(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET			18
+#define MXC_CCM_CCGR6_ESAI_ROOT(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET			20
+#define MXC_CCM_CCGR6_CAN1_IPG(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET		22
+#define MXC_CCM_CCGR6_CAN1_SERIAL(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR6_PL301_4X1_OFFSET			24
+#define MXC_CCM_CCGR6_PL301_4X1(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR6_PL301_2X2_OFFSET			26
+#define MXC_CCM_CCGR6_PL301_2X2(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR6_LDB_DI0_OFFSET			28
+#define MXC_CCM_CCGR6_LDB_DI0(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR6_LDB_DI1_OFFSET			30
+#define MXC_CCM_CCGR6_LDB_DI1(v)			(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET			0
+#define MXC_CCM_CCGR7_ASRC_IPG(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET			2
+#define MXC_CCM_CCGR7_ASRC_ASRCK(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR7_MLB_OFFSET			4
+#define MXC_CCM_CCGR7_MLB(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR7_IEEE1588_OFFSET			6
+#define MXC_CCM_CCGR7_IEEE1588(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR7_UART4_IPG_OFFSET			8
+#define MXC_CCM_CCGR7_UART4_IPG(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR7_UART4_PER_OFFSET			10
+#define MXC_CCM_CCGR7_UART4_PER(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR7_UART5_IPG_OFFSET			12
+#define MXC_CCM_CCGR7_UART5_IPG(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR7_UART5_PER_OFFSET			14
+#define MXC_CCM_CCGR7_UART5_PER(v)			(((v) & 0x3) << 14)
+#endif
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)
+
+#define	MXC_DPLLC_CTL_HFSM				(1 << 7)
+#define	MXC_DPLLC_CTL_DPDCK0_2_EN			(1 << 12)
+
+#define	MXC_DPLLC_OP_PDF_MASK				0xf
+#define	MXC_DPLLC_OP_MFI_OFFSET				4
+#define	MXC_DPLLC_OP_MFI_MASK				(0xf << 4)
+#define	MXC_DPLLC_OP_MFI(v)				(((v) & 0xf) << 4)
+#define	MXC_DPLLC_OP_MFI_RD(r)				(((r) >> 4) & 0xf)
+
+#define	MXC_DPLLC_MFD_MFD_MASK				0x7ffffff
+
+#define	MXC_DPLLC_MFN_MFN_MASK				0x7ffffff
+
+#endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/gpio.h b/arch/arm/include/asm/arch-mx5/gpio.h
new file mode 100644
index 0000000..dad40bd
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/gpio.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ */
+
+
+#ifndef __ASM_ARCH_MX5_GPIO_H
+#define __ASM_ARCH_MX5_GPIO_H
+
+#include <asm/mach-imx/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
new file mode 100644
index 0000000..fbb6e59
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -0,0 +1,562 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
+#define __ASM_ARCH_MX5_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#if defined(CONFIG_MX51)
+#define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
+#define IPU_SOC_BASE_ADDR	0x40000000
+#define IPU_SOC_OFFSET		0x1E000000
+#define SPBA0_BASE_ADDR         0x70000000
+#define AIPS1_BASE_ADDR         0x73F00000
+#define AIPS2_BASE_ADDR         0x83F00000
+#define CSD0_BASE_ADDR          0x90000000
+#define CSD1_BASE_ADDR          0xA0000000
+#define NFC_BASE_ADDR_AXI       0xCFFF0000
+#define CS1_BASE_ADDR           0xB8000000
+#elif defined(CONFIG_MX53)
+#define IPU_SOC_BASE_ADDR	0x18000000
+#define IPU_SOC_OFFSET		0x06000000
+#define SPBA0_BASE_ADDR         0x50000000
+#define AIPS1_BASE_ADDR         0x53F00000
+#define AIPS2_BASE_ADDR         0x63F00000
+#define CSD0_BASE_ADDR          0x70000000
+#define CSD1_BASE_ADDR          0xB0000000
+#define NFC_BASE_ADDR_AXI       0xF7FF0000
+#define IRAM_BASE_ADDR          0xF8000000
+#define CS1_BASE_ADDR           0xF4000000
+#define SATA_BASE_ADDR		0x10000000
+#else
+#error "CPU_TYPE not defined"
+#endif
+
+#define IRAM_SIZE		0x00020000	/* 128 KB */
+
+/*
+ * SPBA global module enabled #0
+ */
+#define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE		(SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
+#define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
+#define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
+#define SPDIF_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00028000)
+#define ATA_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00030000)
+#define SLIM_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00034000)
+#define HSI2C_DMA_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00038000)
+#define SPBA_CTRL_BASE_ADDR	(SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 1
+ */
+#define OTG_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00080000)
+#define GPIO1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00084000)
+#define GPIO2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00088000)
+#define GPIO3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0008C000)
+#define GPIO4_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00090000)
+#define KPP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00094000)
+#define WDOG1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00098000)
+#define WDOG2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0009C000)
+#define GPT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A0000)
+#define SRTC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000A4000)
+#define IOMUXC_BASE_ADDR	(AIPS1_BASE_ADDR + 0x000A8000)
+#define EPIT1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000AC000)
+#define EPIT2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B0000)
+#define PWM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B4000)
+#define PWM2_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000B8000)
+#define UART1_BASE		(AIPS1_BASE_ADDR + 0x000BC000)
+#define UART2_BASE		(AIPS1_BASE_ADDR + 0x000C0000)
+#define SRC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D0000)
+#define CCM_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D4000)
+#define GPC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000D8000)
+
+#if defined(CONFIG_MX53)
+#define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
+#define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
+#define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
+#define I2C3_BASE_ADDR		(AIPS1_BASE_ADDR + 0x000EC000)
+#define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000F0000)
+#endif
+/*
+ * AIPS 2
+ */
+#define PLL1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00080000)
+#define PLL2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00084000)
+#define PLL3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00088000)
+#ifdef	CONFIG_MX53
+#define PLL4_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0008c000)
+#endif
+#define AHBMAX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x00094000)
+#define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
+#define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
+#define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
+#define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
+#define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
+#define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
+#define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)
+#define SCC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B4000)
+#define ROMCP_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B8000)
+#define RTIC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000BC000)
+#define CSPI3_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C0000)
+#define I2C2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C4000)
+#define I2C1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000C8000)
+#define SSI1_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000CC000)
+#define AUDMUX_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D0000)
+#define M4IF_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000D8000)
+#define ESDCTL_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000D9000)
+#define WEIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DA000)
+#define NFC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DB000)
+#define EMI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000DBF00)
+#define MIPI_HSC_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000DC000)
+#define ATA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E0000)
+#define SIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E4000)
+#define SSI3BASE_ADDR		(AIPS2_BASE_ADDR + 0x000E8000)
+#define FEC_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000EC000)
+#define TVE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F0000)
+#define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
+#define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
+
+#if defined(CONFIG_MX53)
+#define UART5_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00090000)
+#endif
+
+/*
+ * WEIM CSnGCR1
+ */
+#define CSEN		1
+#define SWR		(1 << 1)
+#define SRD		(1 << 2)
+#define MUM		(1 << 3)
+#define WFL		(1 << 4)
+#define RFL		(1 << 5)
+#define CRE		(1 << 6)
+#define CREP		(1 << 7)
+#define BL(x)		(((x) & 0x7) << 8)
+#define WC		(1 << 11)
+#define BCD(x)		(((x) & 0x3) << 12)
+#define BCS(x)		(((x) & 0x3) << 14)
+#define DSZ(x)		(((x) & 0x7) << 16)
+#define SP		(1 << 19)
+#define CSREC(x)	(((x) & 0x7) << 20)
+#define AUS		(1 << 23)
+#define GBC(x)		(((x) & 0x7) << 24)
+#define WP		(1 << 27)
+#define PSZ(x)		(((x) & 0x0f << 28)
+
+/*
+ * WEIM CSnGCR2
+ */
+#define ADH(x)		(((x) & 0x3))
+#define DAPS(x)		(((x) & 0x0f << 4)
+#define DAE		(1 << 8)
+#define DAP		(1 << 9)
+#define MUX16_BYP	(1 << 12)
+
+/*
+ * WEIM CSnRCR1
+ */
+#define RCSN(x)		(((x) & 0x7))
+#define RCSA(x)		(((x) & 0x7) << 4)
+#define OEN(x)		(((x) & 0x7) << 8)
+#define OEA(x)		(((x) & 0x7) << 12)
+#define RADVN(x)	(((x) & 0x7) << 16)
+#define RAL		(1 << 19)
+#define RADVA(x)	(((x) & 0x7) << 20)
+#define RWSC(x)		(((x) & 0x3f) << 24)
+
+/*
+ * WEIM CSnRCR2
+ */
+#define RBEN(x)		(((x) & 0x7))
+#define RBE		(1 << 3)
+#define RBEA(x)		(((x) & 0x7) << 4)
+#define RL(x)		(((x) & 0x3) << 8)
+#define PAT(x)		(((x) & 0x7) << 12)
+#define APR		(1 << 15)
+
+/*
+ * WEIM CSnWCR1
+ */
+#define WCSN(x)		(((x) & 0x7))
+#define WCSA(x)		(((x) & 0x7) << 3)
+#define WEN(x)		(((x) & 0x7) << 6)
+#define WEA(x)		(((x) & 0x7) << 9)
+#define WBEN(x)		(((x) & 0x7) << 12)
+#define WBEA(x)		(((x) & 0x7) << 15)
+#define WADVN(x)	(((x) & 0x7) << 18)
+#define WADVA(x)	(((x) & 0x7) << 21)
+#define WWSC(x)		(((x) & 0x3f) << 24)
+#define WBED1		(1 << 30)
+#define WAL		(1 << 31)
+
+/*
+ * WEIM CSnWCR2
+ */
+#define WBED		1
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_MODE_MASK	(0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN	18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA		0  /* SCLK phase control */
+#define MXC_CSPICON_POL		4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL	12 /* SS polarity */
+#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
+#define MXC_SPI_BASE_ADDRESSES \
+	CSPI1_BASE_ADDR, \
+	CSPI2_BASE_ADDR, \
+	CSPI3_BASE_ADDR,
+
+/*
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN            32
+
+#define IIM_SREV	0x24
+#define ROM_SI_REV	0x48
+
+#define NFC_BUF_SIZE	0x1000
+
+/* M4IF */
+#define M4IF_FBPM0	0x40
+#define M4IF_FIDBP	0x48
+#define M4IF_GENP_WEIM_MM_MASK		0x00000001
+#define WEIM_GCR2_MUX16_BYP_GRANT_MASK	0x00001000
+
+/* Assuming 24MHz input clock with doubler ON */
+/*                            MFI         PDF */
+#define DP_OP_864	((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_864	(180 - 1) /* PL Dither mode */
+#define DP_MFN_864	180
+#define DP_MFN_800_DIT	60 /* PL Dither mode */
+
+#define DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_850	(48 - 1)
+#define DP_MFN_850	41
+
+#define DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_800	(3 - 1)
+#define DP_MFN_800	1
+
+#define DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_700	(24 - 1)
+#define DP_MFN_700	7
+
+#define DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_665	(96 - 1)
+#define DP_MFN_665	89
+
+#define DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_532	(24 - 1)
+#define DP_MFN_532	13
+
+#define DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_400	(3 - 1)
+#define DP_MFN_400	1
+
+#define DP_OP_455	((9 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_455	(48 - 1)
+#define DP_MFN_455	23
+
+#define DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
+#define DP_MFD_216	(4 - 1)
+#define DP_MFN_216	3
+
+#define IMX_IIM_BASE            (IIM_BASE_ADDR)
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+#define __REG(x)	(*((volatile u32 *)(x)))
+#define __REG16(x)	(*((volatile u16 *)(x)))
+#define __REG8(x)	(*((volatile u8 *)(x)))
+
+struct clkctl {
+	u32	ccr;
+	u32	ccdr;
+	u32	csr;
+	u32	ccsr;
+	u32	cacrr;
+	u32	cbcdr;
+	u32	cbcmr;
+	u32	cscmr1;
+	u32	cscmr2;
+	u32	cscdr1;
+	u32	cs1cdr;
+	u32	cs2cdr;
+	u32	cdcdr;
+	u32	chsccdr;
+	u32	cscdr2;
+	u32	cscdr3;
+	u32	cscdr4;
+	u32	cwdr;
+	u32	cdhipr;
+	u32	cdcr;
+	u32	ctor;
+	u32	clpcr;
+	u32	cisr;
+	u32	cimr;
+	u32	ccosr;
+	u32	cgpr;
+	u32	ccgr0;
+	u32	ccgr1;
+	u32	ccgr2;
+	u32	ccgr3;
+	u32	ccgr4;
+	u32	ccgr5;
+	u32	ccgr6;
+#if defined(CONFIG_MX53)
+	u32	ccgr7;
+#endif
+	u32	cmeor;
+};
+
+/* DPLL registers */
+struct dpll {
+	u32	dp_ctl;
+	u32	dp_config;
+	u32	dp_op;
+	u32	dp_mfd;
+	u32	dp_mfn;
+	u32	dp_mfn_minus;
+	u32	dp_mfn_plus;
+	u32	dp_hfs_op;
+	u32	dp_hfs_mfd;
+	u32	dp_hfs_mfn;
+	u32	dp_mfn_togc;
+	u32	dp_destat;
+};
+/* WEIM registers */
+struct weim {
+	u32	cs0gcr1;
+	u32	cs0gcr2;
+	u32	cs0rcr1;
+	u32	cs0rcr2;
+	u32	cs0wcr1;
+	u32	cs0wcr2;
+	u32	cs1gcr1;
+	u32	cs1gcr2;
+	u32	cs1rcr1;
+	u32	cs1rcr2;
+	u32	cs1wcr1;
+	u32	cs1wcr2;
+	u32	cs2gcr1;
+	u32	cs2gcr2;
+	u32	cs2rcr1;
+	u32	cs2rcr2;
+	u32	cs2wcr1;
+	u32	cs2wcr2;
+	u32	cs3gcr1;
+	u32	cs3gcr2;
+	u32	cs3rcr1;
+	u32	cs3rcr2;
+	u32	cs3wcr1;
+	u32	cs3wcr2;
+	u32	cs4gcr1;
+	u32	cs4gcr2;
+	u32	cs4rcr1;
+	u32	cs4rcr2;
+	u32	cs4wcr1;
+	u32	cs4wcr2;
+	u32	cs5gcr1;
+	u32	cs5gcr2;
+	u32	cs5rcr1;
+	u32	cs5rcr2;
+	u32	cs5wcr1;
+	u32	cs5wcr2;
+	u32	wcr;
+	u32	wiar;
+	u32	ear;
+};
+
+#if defined(CONFIG_MX51)
+struct iomuxc {
+	u32	gpr[2];
+	u32	omux0;
+	u32	omux1;
+	u32	omux2;
+	u32	omux3;
+	u32	omux4;
+};
+#elif defined(CONFIG_MX53)
+struct iomuxc {
+	u32	gpr[3];
+	u32	omux0;
+	u32	omux1;
+	u32	omux2;
+	u32	omux3;
+	u32	omux4;
+};
+#endif
+
+#define IOMUXC_GPR2_BITMAP_SPWG	0
+#define IOMUXC_GPR2_BITMAP_JEIDA	1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET	6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK	(1 << IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA	(IOMUXC_GPR2_BITMAP_JEIDA << \
+						 IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG	(IOMUXC_GPR2_BITMAP_SPWG << \
+						 IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18	0
+#define IOMUXC_GPR2_DATA_WIDTH_24	1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET	5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK		(1 << IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT	(IOMUXC_GPR2_DATA_WIDTH_18 << \
+						 IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT	(IOMUXC_GPR2_DATA_WIDTH_24 << \
+						 IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED	0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0	1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1	3
+
+#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET	0
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK		(3 << IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED	(IOMUXC_GPR2_MODE_DISABLED << \
+						 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0	(IOMUXC_GPR2_MODE_ENABLED_DI0 << \
+						 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1	(IOMUXC_GPR2_MODE_ENABLED_DI1 << \
+						 IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32	scr;
+	u32	sbmr;
+	u32	srsr;
+	u32	reserved1[2];
+	u32	sisr;
+	u32	simr;
+};
+
+struct srtc_regs {
+	u32	lpscmr;		/* 0x00 */
+	u32	lpsclr;		/* 0x04 */
+	u32	lpsar;		/* 0x08 */
+	u32	lpsmcr;		/* 0x0c */
+	u32	lpcr;		/* 0x10 */
+	u32	lpsr;		/* 0x14 */
+	u32	lppdr;		/* 0x18 */
+	u32	lpgr;		/* 0x1c */
+	u32	hpcmr;		/* 0x20 */
+	u32	hpclr;		/* 0x24 */
+	u32	hpamr;		/* 0x28 */
+	u32	hpalr;		/* 0x2c */
+	u32	hpcr;		/* 0x30 */
+	u32	hpisr;		/* 0x34 */
+	u32	hpienr;		/* 0x38 */
+};
+
+/* CSPI registers */
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 cfg;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+};
+
+struct iim_regs {
+	u32	stat;
+	u32	statm;
+	u32     err;
+	u32	emask;
+	u32	fctl;
+	u32	ua;
+	u32	la;
+	u32	sdat;
+	u32	prev;
+	u32	srev;
+	u32	prg_p;
+	u32	scs0;
+	u32	scs1;
+	u32	scs2;
+	u32	scs3;
+	u32	res0[0x1f1];
+	struct fuse_bank {
+		u32	fuse_regs[0x20];
+		u32	fuse_rsvd[0xe0];
+#if defined(CONFIG_MX51)
+	} bank[4];
+#elif defined(CONFIG_MX53)
+	} bank[5];
+#endif
+};
+
+struct fuse_bank0_regs {
+	u32	fuse0_7[8];
+	u32	uid[8];
+	u32	fuse16_23[8];
+#if defined(CONFIG_MX51)
+	u32	imei[8];
+#elif defined(CONFIG_MX53)
+	u32	gp[8];
+#endif
+};
+
+struct fuse_bank1_regs {
+	u32	fuse0_8[9];
+	u32	mac_addr[6];
+	u32	fuse15_31[0x11];
+};
+
+#if defined(CONFIG_MX53)
+struct fuse_bank4_regs {
+	u32	fuse0_4[5];
+	u32	gp[3];
+	u32	fuse8_31[0x18];
+};
+#endif
+
+#define PWMCR_PRESCALER(x)	(((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN		(1 << 24)
+#define PWMCR_WAITEN		(1 << 23)
+#define PWMCR_DBGEN		(1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
+#define PWMCR_CLKSRC_IPG	(1 << 16)
+#define PWMCR_EN		(1 << 0)
+
+struct pwm_regs {
+	u32	cr;
+	u32	sr;
+	u32	ir;
+	u32	sar;
+	u32	pr;
+	u32	cnr;
+};
+
+#endif /* __ASSEMBLER__*/
+
+#endif				/* __ASM_ARCH_MX5_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
new file mode 100644
index 0000000..7f8a238
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2009-2012 Genesi USA, Inc.
+ */
+
+/*
+ * The vast majority of this file is taken from the Linux kernel at
+ * commit 5d23b39
+ */
+
+#ifndef __IOMUX_MX51_H__
+#define __IOMUX_MX51_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX51_UART_PAD_CTRL	(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
+				PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+#define MX51_I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+				PAD_CTL_HYS)
+#define MX51_ESDHC_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+				PAD_CTL_HYS)
+#define MX51_USBH_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+				PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
+#define MX51_ECSPI_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_HYS | \
+				PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+#define MX51_SDHCI_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
+				PAD_CTL_SRE_FAST | PAD_CTL_DVS)
+#define MX51_GPIO_PAD_CTRL	(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
+
+#define MX51_PAD_CTRL_2		(PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_4		(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_5		(PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+
+/*
+ * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*							    PAD    MUX   ALT INPSE PATH PADCTRL */
+enum {
+	MX51_PAD_EIM_D16__USBH2_DATA0		= IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D17__GPIO2_1		= IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_D17__USBH2_DATA1		= IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D18__USBH2_DATA2		= IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D19__USBH2_DATA3		= IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D20__USBH2_DATA4		= IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D21__GPIO2_5		= IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_D21__USBH2_DATA5		= IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D22__USBH2_DATA6		= IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D23__USBH2_DATA7		= IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_D25__UART3_RXD		= IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_EIM_D26__UART3_TXD		= IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_EIM_D27__GPIO2_9		= IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A16__GPIO2_10		= IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A17__GPIO2_11		= IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A20__GPIO2_14		= IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A22__GPIO2_16		= IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A24__USBH2_CLK		= IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_A25__USBH2_DIR		= IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_A26__GPIO2_20		= IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_A26__USBH2_STP		= IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_A27__USBH2_NXT		= IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_EIM_EB2__FEC_MDIO		= IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS),
+	MX51_PAD_EIM_EB3__FEC_RDATA1		= IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_EB3__GPIO2_23		= IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS0__GPIO2_25		= IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS2__FEC_RDATA2		= IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_CS2__GPIO2_27		= IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS3__FEC_RDATA3		= IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
+	MX51_PAD_EIM_CS3__GPIO2_28		= IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS4__FEC_RX_ER		= IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_EIM_CS4__GPIO2_29		= IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_EIM_CS5__FEC_CRS		= IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_DRAM_RAS__DRAM_RAS		= IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CAS__DRAM_CAS		= IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDWE__DRAM_SDWE		= IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0	= IOMUX_PAD(0x4b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1	= IOMUX_PAD(0x4b4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDCLK__DRAM_SDCLK		= IOMUX_PAD(0x4b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS0__DRAM_SDQS0		= IOMUX_PAD(0x4bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS1__DRAM_SDQS1		= IOMUX_PAD(0x4c0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS2__DRAM_SDQS2		= IOMUX_PAD(0x4c4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_SDQS3__DRAM_SDQS3		= IOMUX_PAD(0x4c8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CS0__DRAM_CS0		= IOMUX_PAD(0x4cc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_CS1__DRAM_CS1		= IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM0__DRAM_DQM0		= IOMUX_PAD(0x4d4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM1__DRAM_DQM1		= IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM2__DRAM_DQM2		= IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DRAM_DQM3__DRAM_DQM3		= IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_WE_B__PATA_DIOW		= IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_RE_B__PATA_DIOR		= IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_ALE__PATA_BUFFER_EN	= IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CLE__PATA_RESET_B	= IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_WP_B__PATA_DMACK		= IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_RB0__PATA_DMARQ		= IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_RB1__PATA_IORDY		= IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_RB2__FEC_COL		= IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_NANDF_RB2__GPIO3_10		= IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_RB3__FEC_RX_CLK		= IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
+	MX51_PAD_NANDF_RB3__GPIO3_11		= IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO_NAND__PATA_INTRQ		= IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS2__FEC_TX_ER		= IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_CS2__PATA_CS_0		= IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS3__FEC_MDC		= IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_CS3__PATA_CS_1		= IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS4__FEC_TDATA1		= IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_CS4__PATA_DA_0		= IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS5__FEC_TDATA2		= IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_CS5__PATA_DA_1		= IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS6__FEC_TDATA3		= IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_CS6__PATA_DA_2		= IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_CS7__FEC_TX_EN		= IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	= IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4),
+	MX51_PAD_NANDF_D15__GPIO3_25		= IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_D15__PATA_DATA15		= IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D14__GPIO3_26		= IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_D14__PATA_DATA14		= IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D13__GPIO3_27		= IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_D13__PATA_DATA13		= IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D12__PATA_DATA12		= IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D11__FEC_RX_DV		= IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D11__PATA_DATA11		= IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D10__GPIO3_30		= IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_D10__PATA_DATA10		= IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D9__FEC_RDATA0		= IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4),
+	MX51_PAD_NANDF_D9__GPIO3_31		= IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_NANDF_D9__PATA_DATA9		= IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D8__FEC_TDATA0		= IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_NANDF_D8__PATA_DATA8		= IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D7__PATA_DATA7		= IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D6__PATA_DATA6		= IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D5__PATA_DATA5		= IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D4__PATA_DATA4		= IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D3__PATA_DATA3		= IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D2__PATA_DATA2		= IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D1__PATA_DATA1		= IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_NANDF_D0__PATA_DATA0		= IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_CSI2_D12__GPIO4_9		= IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSI2_D13__GPIO4_10		= IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	= IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_MISO__ECSPI1_MISO	= IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_SS0__ECSPI1_SS0		= IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_SS0__GPIO4_24		= IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_SS1__ECSPI1_SS1		= IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_SS1__GPIO4_25		= IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_RDY__ECSPI1_RDY		= IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_CSPI1_RDY__GPIO4_26		= IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	= IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_UART1_RXD__UART1_RXD		= IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_UART1_TXD__UART1_TXD		= IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_UART1_RTS__UART1_RTS		= IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_UART1_CTS__UART1_CTS		= IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
+	MX51_PAD_USBH1_CLK__USBH1_CLK		= IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DIR__USBH1_DIR		= IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_STP__GPIO1_27		= IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_USBH1_STP__USBH1_STP		= IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_NXT__USBH1_NXT		= IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA0__USBH1_DATA0	= IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA1__USBH1_DATA1	= IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA2__USBH1_DATA2	= IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA3__USBH1_DATA3	= IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA4__USBH1_DATA4	= IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA5__USBH1_DATA5	= IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA6__USBH1_DATA6	= IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_USBH1_DATA7__USBH1_DATA7	= IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+	MX51_PAD_DI1_PIN11__ECSPI1_SS2		= IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+	MX51_PAD_DI1_PIN12__GPIO3_1		= IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_PIN13__GPIO3_2		= IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_D0_CS__GPIO3_3		= IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_D1_CS__GPIO3_4		= IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DISPB2_SER_DIN__GPIO3_5	= IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DISPB2_SER_DIO__GPIO3_6	= IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_DI1_PIN3__DI1_PIN3		= IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI1_PIN2__DI1_PIN2		= IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI2_PIN2__FEC_MDC		= IOMUX_PAD(0x74C, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	= IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DI_GP4__DI2_PIN15		= IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_DISP2_DAT6__FEC_TDAT1		= IOMUX_PAD(0x774, 0x36C, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_DISP2_DAT7__FEC_TDAT2		= IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_DISP2_DAT8__FEC_TDAT3		= IOMUX_PAD(0x77C, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_DISP2_DAT9__FEC_TX_EN		= IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_DISP2_DAT10__FEC_COL		= IOMUX_PAD(0x784, 0x37C, 2, 0x94c, 0x1, MX51_PAD_CTRL_2),
+	MX51_PAD_DISP2_DAT11__FEC_RXCLK		= IOMUX_PAD(0x788, 0x380, 2, 0x968, 0x1, MX51_PAD_CTRL_2),
+	MX51_PAD_DISP2_DAT12__FEC_RX_DV		= IOMUX_PAD(0x78C, 0x384, 2, 0x96c, 0x1, MX51_PAD_CTRL_4),
+	MX51_PAD_DISP2_DAT13__FEC_TX_CLK	= IOMUX_PAD(0x790, 0x388, 2, 0x974, 0x1, MX51_PAD_CTRL_4),
+	MX51_PAD_DISP2_DAT14__FEC_RDAT0		= IOMUX_PAD(0x794, 0x38C, 2, 0x958, 0x1, MX51_PAD_CTRL_4),
+	MX51_PAD_DISP2_DAT15__FEC_TDAT0		= IOMUX_PAD(0x798, 0x390, 2, 0x0, 0, MX51_PAD_CTRL_5),
+	MX51_PAD_SD1_CMD__SD1_CMD		= IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD1_CLK__SD1_CLK		= IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
+	MX51_PAD_SD1_DATA0__SD1_DATA0		= IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD1_DATA1__SD1_DATA1		= IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD1_DATA2__SD1_DATA2		= IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD1_DATA3__SD1_DATA3		= IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_GPIO1_0__GPIO1_0		= IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_0__SD1_CD		= IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_PAD_GPIO1_1__SD1_WP		= IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_PAD_SD2_CMD__SD2_CMD		= IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD2_CLK__SD2_CLK		= IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
+	MX51_PAD_SD2_DATA0__SD2_DATA0		= IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD2_DATA1__SD2_DATA1		= IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD2_DATA2__SD2_DATA2		= IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_SD2_DATA3__SD2_DATA3		= IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+	MX51_PAD_GPIO1_2__GPIO1_2		= IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_2__PWM1_PWMO		= IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL),
+	MX51_PAD_GPIO1_3__GPIO1_3		= IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_5__GPIO1_5		= IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_6__GPIO1_6		= IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_7__GPIO1_7		= IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+	MX51_PAD_GPIO1_7__SD2_WP		= IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_PAD_GPIO1_8__SD2_CD		= IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+	MX51_GRP_DDRPKS				= IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B4			= IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_PKEDDR				= IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_A0				= IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_A1				= IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRAPUS			= IOMUX_PAD(0x84c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR0			= IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR1			= IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR2			= IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_HYSDDR3			= IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B0			= IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRAPKS			= IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B1			= IOMUX_PAD(0x880, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDRPUS				= IOMUX_PAD(0x884, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B2			= IOMUX_PAD(0x88c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_PKEADDR			= IOMUX_PAD(0x890, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_SR_B4			= IOMUX_PAD(0x89c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_INMODE1			= IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B0			= IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B1			= IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DRAM_B2			= IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+	MX51_GRP_DDR_SR_A1			= IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX51_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx53.h b/arch/arm/include/asm/arch-mx5/iomux-mx53.h
new file mode 100644
index 0000000..cbc08b0
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx53.h
@@ -0,0 +1,1215 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on Freescale's Linux i.MX iomux-mx53.h file:
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __IOMUX_MX53_H__
+#define __IOMUX_MX53_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX53_UART_PAD_CTRL	(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define MX53_SDHC_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+
+/*
+ * The naming convention for the pad modes is MX53_PAD_<padname>__<padmode>
+ * If <padname> refers to a GPIO, it is named GPIO_<unit>
+ * If <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/*								    PAD    MUX   ALT INPSE PATH PADCTRL */
+enum {
+	MX53_PAD_GPIO_19__KPP_COL_5			= IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__GPIO4_5			= IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__CCM_CLKO			= IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__SPDIF_OUT1			= IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2		= IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__ECSPI1_RDY			= IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__FEC_TDATA_3			= IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_19__SRC_INT_BOOT			= IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__KPP_COL_0			= IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__GPIO4_6			= IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC		= IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__UART4_TXD_MUX		= IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL0__ECSPI1_SCLK			= IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__FEC_RDATA_3			= IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL0__SRC_ANY_PU_RST		= IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__KPP_ROW_0			= IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__GPIO4_7			= IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD		= IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__UART4_RXD_MUX		= IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__ECSPI1_MOSI			= IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW0__FEC_TX_ER			= IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__KPP_COL_1			= IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__GPIO4_8			= IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS		= IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__UART5_TXD_MUX		= IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL1__ECSPI1_MISO			= IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__FEC_RX_CLK			= IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL1__USBPHY1_TXREADY		= IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__KPP_ROW_1			= IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__GPIO4_9			= IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD		= IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__UART5_RXD_MUX		= IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__ECSPI1_SS0			= IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__FEC_COL			= IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW1__USBPHY1_RXVALID		= IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__KPP_COL_2			= IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__GPIO4_10			= IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__CAN1_TXCAN			= IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__FEC_MDIO			= IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__ECSPI1_SS1			= IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__FEC_RDATA_2			= IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE		= IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__KPP_ROW_2			= IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__GPIO4_11			= IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__CAN1_RXCAN			= IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__FEC_MDC			= IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__ECSPI1_SS2			= IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__FEC_TDATA_2			= IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW2__USBPHY1_RXERROR		= IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__KPP_COL_3			= IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__GPIO4_12			= IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__USBOH3_H2_DP			= IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__SPDIF_IN1			= IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__I2C2_SCL			= IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__ECSPI1_SS3			= IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__FEC_CRS			= IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK		= IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__KPP_ROW_3			= IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__GPIO4_13			= IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__USBOH3_H2_DM			= IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK		= IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__I2C2_SDA			= IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__OSC32K_32K_OUT		= IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__CCM_PLL4_BYP			= IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0		= IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__KPP_COL_4			= IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__GPIO4_14			= IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__CAN2_TXCAN			= IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__IPU_SISG_4			= IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__UART5_RTS			= IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC		= IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1		= IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__KPP_ROW_4			= IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__GPIO4_15			= IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__CAN2_RXCAN			= IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__IPU_SISG_5			= IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__UART5_CTS			= IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR		= IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID		= IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK		= IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__GPIO4_16			= IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR		= IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0	= IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0		= IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID		= IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__IPU_DI0_PIN15		= IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__GPIO4_17			= IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC		= IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1	= IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1		= IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN15__USBPHY1_BVALID		= IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__IPU_DI0_PIN2			= IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__GPIO4_18			= IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD		= IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2	= IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2		= IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION		= IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__IPU_DI0_PIN3			= IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__GPIO4_19			= IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS		= IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3	= IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3		= IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN3__USBPHY1_IDDIG		= IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__IPU_DI0_PIN4			= IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__GPIO4_20			= IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD		= IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__ESDHC1_WP			= IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD		= IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4		= IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT	= IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0		= IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__GPIO4_21			= IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__CSPI_SCLK			= IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0	= IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN	= IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5		= IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY		= IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1		= IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__GPIO4_22			= IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__CSPI_MOSI			= IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1	= IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL
+							= IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6		= IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID		= IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2		= IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__GPIO4_23			= IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__CSPI_MISO			= IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2	= IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE		= IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7		= IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE		= IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3		= IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__GPIO4_24			= IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__CSPI_SS0			= IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3	= IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR	= IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8		= IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR		= IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4		= IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__GPIO4_25			= IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__CSPI_SS1			= IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4	= IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB		= IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9		= IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK		= IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5		= IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__GPIO4_26			= IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__CSPI_SS2			= IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5	= IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS	= IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10		= IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0	= IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6		= IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__GPIO4_27			= IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__CSPI_SS3			= IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6	= IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE	= IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11		= IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1	= IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7		= IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__GPIO4_28			= IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__CSPI_RDY			= IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7	= IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0	= IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12		= IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID		= IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8		= IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__GPIO4_29			= IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__PWM1_PWMO			= IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B		= IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1	= IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13		= IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT8__USBPHY2_AVALID		= IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9		= IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__GPIO4_30			= IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__PWM2_PWMO			= IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B		= IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2	= IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14		= IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0		= IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10		= IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__GPIO4_31			= IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP		= IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3
+							= IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15		= IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1		= IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11		= IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__GPIO5_5			= IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT		= IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4
+							= IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16		= IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2		= IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12		= IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__GPIO5_6			= IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK		= IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5
+							= IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17		= IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3		= IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13		= IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__GPIO5_7			= IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS		= IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0
+							= IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18		= IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4		= IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14		= IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__GPIO5_8			= IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC		= IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1
+							= IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19		= IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5		= IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15		= IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__GPIO5_9			= IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__ECSPI1_SS1		= IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__ECSPI2_SS1		= IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2
+							= IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20		= IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6		= IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16		= IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__GPIO5_10			= IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__ECSPI2_MOSI		= IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC		= IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0		= IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3
+							= IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21		= IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7		= IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17		= IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__GPIO5_11			= IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__ECSPI2_MISO		= IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD		= IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1		= IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4
+							= IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22		= IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18		= IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__GPIO5_12			= IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__ECSPI2_SS0		= IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS		= IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS		= IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5
+							= IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23		= IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2		= IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19		= IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__GPIO5_13			= IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__ECSPI2_SCLK		= IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD		= IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC		= IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6
+							= IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24		= IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3		= IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20		= IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__GPIO5_14			= IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__ECSPI1_SCLK		= IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC		= IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7
+							= IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25		= IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT20__SATA_PHY_TDI		= IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21		= IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__GPIO5_15			= IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__ECSPI1_MOSI		= IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD		= IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0	= IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26		= IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT21__SATA_PHY_TDO		= IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22		= IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__GPIO5_16			= IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__ECSPI1_MISO		= IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS		= IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1	= IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27		= IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT22__SATA_PHY_TCK		= IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23		= IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__GPIO5_17			= IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__ECSPI1_SS0		= IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD		= IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2	= IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28		= IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_DISP0_DAT23__SATA_PHY_TMS		= IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK		= IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__GPIO5_18			= IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0		= IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29		= IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC		= IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__GPIO5_19			= IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK		= IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1		= IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30		= IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_MCLK__TPIU_TRCTL			= IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN		= IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__GPIO5_20			= IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2		= IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31		= IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK		= IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC		= IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__GPIO5_21			= IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3		= IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32		= IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0		= IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4		= IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__GPIO5_22			= IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__KPP_COL_5			= IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__ECSPI1_SCLK			= IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP		= IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC		= IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33		= IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT4__TPIU_TRACE_1		= IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5		= IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__GPIO5_23			= IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__KPP_ROW_5			= IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__ECSPI1_MOSI			= IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT		= IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD		= IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34		= IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT5__TPIU_TRACE_2		= IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6		= IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__GPIO5_24			= IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__KPP_COL_6			= IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__ECSPI1_MISO			= IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK		= IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS		= IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35		= IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT6__TPIU_TRACE_3		= IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7		= IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__GPIO5_25			= IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__KPP_ROW_6			= IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__ECSPI1_SS0			= IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR		= IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD		= IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36		= IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT7__TPIU_TRACE_4		= IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8		= IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__GPIO5_26			= IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__KPP_COL_7			= IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__ECSPI2_SCLK			= IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC		= IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__I2C1_SDA			= IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37		= IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT8__TPIU_TRACE_5		= IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9		= IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__GPIO5_27			= IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__KPP_ROW_7			= IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__ECSPI2_MOSI			= IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR		= IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__I2C1_SCL			= IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38		= IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT9__TPIU_TRACE_6		= IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10		= IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__GPIO5_28			= IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX		= IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__ECSPI2_MISO		= IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC		= IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4		= IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39		= IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT10__TPIU_TRACE_7		= IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11		= IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__GPIO5_29			= IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX		= IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__ECSPI2_SS0			= IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS		= IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5		= IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40		= IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT11__TPIU_TRACE_8		= IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12		= IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__GPIO5_30			= IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__UART4_TXD_MUX		= IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0	= IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6		= IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41		= IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT12__TPIU_TRACE_9		= IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13		= IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__GPIO5_31			= IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__UART4_RXD_MUX		= IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1	= IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7		= IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42		= IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT13__TPIU_TRACE_10		= IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14		= IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__GPIO6_0			= IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__UART5_TXD_MUX		= IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2	= IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8		= IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43		= IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT14__TPIU_TRACE_11		= IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15		= IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__GPIO6_1			= IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__UART5_RXD_MUX		= IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3	= IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9		= IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44		= IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT15__TPIU_TRACE_12		= IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16		= IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__GPIO6_2			= IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__UART4_RTS			= IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4	= IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10		= IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45		= IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT16__TPIU_TRACE_13		= IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17		= IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__GPIO6_3			= IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__UART4_CTS			= IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5	= IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11		= IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46		= IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT17__TPIU_TRACE_14		= IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18		= IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__GPIO6_4			= IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__UART5_RTS			= IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6	= IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12		= IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47		= IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT18__TPIU_TRACE_15		= IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19		= IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__GPIO6_5			= IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__UART5_CTS			= IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7	= IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13		= IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48		= IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK		= IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__EMI_WEIM_A_25			= IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__GPIO5_2			= IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__ECSPI2_RDY			= IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__IPU_DI1_PIN12			= IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__CSPI_SS1			= IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__IPU_DI0_D1_CS			= IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A25__USBPHY1_BISTOK		= IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__EMI_WEIM_EB_2			= IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__GPIO2_30			= IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK		= IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS		= IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__ECSPI1_SS0			= IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB2__I2C2_SCL			= IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__EMI_WEIM_D_16			= IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__GPIO3_16			= IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__IPU_DI0_PIN5			= IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK		= IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__ECSPI1_SCLK			= IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D16__I2C2_SDA			= IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__EMI_WEIM_D_17			= IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__GPIO3_17			= IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__IPU_DI0_PIN6			= IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN		= IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__ECSPI1_MISO			= IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D17__I2C3_SCL			= IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__EMI_WEIM_D_18			= IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__GPIO3_18			= IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DI0_PIN7			= IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO		= IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__ECSPI1_MOSI			= IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__I2C3_SDA			= IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D18__IPU_DI1_D0_CS			= IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__EMI_WEIM_D_19			= IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__GPIO3_19			= IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__IPU_DI0_PIN8			= IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS		= IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__ECSPI1_SS1			= IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__EPIT1_EPITO			= IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D19__UART1_CTS			= IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D19__USBOH3_USBH2_OC		= IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__EMI_WEIM_D_20			= IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__GPIO3_20			= IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__IPU_DI0_PIN16			= IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__IPU_SER_DISP0_CS		= IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__CSPI_SS0			= IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__EPIT2_EPITO			= IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D20__UART1_RTS			= IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D20__USBOH3_USBH2_PWR		= IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__EMI_WEIM_D_21			= IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__GPIO3_21			= IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__IPU_DI0_PIN17			= IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK		= IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__CSPI_SCLK			= IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__I2C1_SCL			= IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D21__USBOH3_USBOTG_OC		= IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__EMI_WEIM_D_22			= IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__GPIO3_22			= IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__IPU_DI0_PIN1			= IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN		= IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__CSPI_MISO			= IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR		= IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__EMI_WEIM_D_23			= IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__GPIO3_23			= IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__UART3_CTS			= IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D23__UART1_DCD			= IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI0_D0_CS			= IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI1_PIN2			= IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN		= IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D23__IPU_DI1_PIN14			= IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__EMI_WEIM_EB_3			= IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__GPIO2_31			= IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__UART3_RTS			= IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_EB3__UART1_RI			= IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_DI1_PIN3			= IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC		= IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB3__IPU_DI1_PIN16			= IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__EMI_WEIM_D_24			= IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__GPIO3_24			= IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__UART3_TXD_MUX			= IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D24__ECSPI1_SS2			= IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__CSPI_SS2			= IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS		= IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__ECSPI2_SS2			= IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D24__UART1_DTR			= IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__EMI_WEIM_D_25			= IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__GPIO3_25			= IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__UART3_RXD_MUX			= IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D25__ECSPI1_SS3			= IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__CSPI_SS3			= IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC		= IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__ECSPI2_SS3			= IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D25__UART1_DSR			= IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__EMI_WEIM_D_26			= IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__GPIO3_26			= IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__UART2_TXD_MUX			= IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D26__FIRI_RXD			= IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_CSI0_D_1			= IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_DI1_PIN11			= IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_SISG_2			= IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D26__IPU_DISP1_DAT_22		= IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__EMI_WEIM_D_27			= IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__GPIO3_27			= IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__UART2_RXD_MUX			= IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D27__FIRI_TXD			= IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_CSI0_D_0			= IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_DI1_PIN13			= IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_SISG_3			= IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D27__IPU_DISP1_DAT_23		= IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__EMI_WEIM_D_28			= IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__GPIO3_28			= IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__UART2_CTS			= IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO		= IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__CSPI_MOSI			= IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__I2C1_SDA			= IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_EXT_TRIG			= IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D28__IPU_DI0_PIN13			= IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__EMI_WEIM_D_29			= IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__GPIO3_29			= IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__UART2_RTS			= IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS		= IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__CSPI_SS0			= IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DI1_PIN15			= IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_CSI1_VSYNC		= IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D29__IPU_DI0_PIN14			= IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__EMI_WEIM_D_30			= IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__GPIO3_30			= IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__UART3_CTS			= IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_CSI0_D_3			= IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_DI0_PIN11			= IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__IPU_DISP1_DAT_21		= IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__USBOH3_USBH1_OC		= IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D30__USBOH3_USBH2_OC		= IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__EMI_WEIM_D_31			= IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__GPIO3_31			= IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__UART3_RTS			= IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_CSI0_D_2			= IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_DI0_PIN12			= IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__IPU_DISP1_DAT_20		= IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__USBOH3_USBH1_PWR		= IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_D31__USBOH3_USBH2_PWR		= IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__EMI_WEIM_A_24			= IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__GPIO5_4			= IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_DISP1_DAT_19		= IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_CSI1_D_19			= IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__IPU_SISG_2			= IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A24__USBPHY2_BVALID		= IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__EMI_WEIM_A_23			= IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__GPIO6_6			= IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_DISP1_DAT_18		= IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_CSI1_D_18			= IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__IPU_SISG_3			= IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A23__USBPHY2_ENDSESSION		= IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__EMI_WEIM_A_22			= IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__GPIO2_16			= IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__IPU_DISP1_DAT_17		= IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__IPU_CSI1_D_17			= IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A22__SRC_BT_CFG1_7			= IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__EMI_WEIM_A_21			= IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__GPIO2_17			= IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__IPU_DISP1_DAT_16		= IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__IPU_CSI1_D_16			= IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A21__SRC_BT_CFG1_6			= IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__EMI_WEIM_A_20			= IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__GPIO2_18			= IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__IPU_DISP1_DAT_15		= IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__IPU_CSI1_D_15			= IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A20__SRC_BT_CFG1_5			= IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__EMI_WEIM_A_19			= IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__GPIO2_19			= IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__IPU_DISP1_DAT_14		= IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__IPU_CSI1_D_14			= IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A19__SRC_BT_CFG1_4			= IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__EMI_WEIM_A_18			= IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__GPIO2_20			= IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__IPU_DISP1_DAT_13		= IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__IPU_CSI1_D_13			= IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A18__SRC_BT_CFG1_3			= IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__EMI_WEIM_A_17			= IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__GPIO2_21			= IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__IPU_DISP1_DAT_12		= IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__IPU_CSI1_D_12			= IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A17__SRC_BT_CFG1_2			= IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__EMI_WEIM_A_16			= IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__GPIO2_22			= IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK		= IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK		= IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_A16__SRC_BT_CFG1_1			= IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__EMI_WEIM_CS_0			= IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__GPIO2_23			= IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__ECSPI2_SCLK			= IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS0__IPU_DI1_PIN5			= IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__EMI_WEIM_CS_1			= IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__GPIO2_24			= IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__ECSPI2_MOSI			= IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_CS1__IPU_DI1_PIN6			= IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__EMI_WEIM_OE			= IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__GPIO2_25			= IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__ECSPI2_MISO			= IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__IPU_DI1_PIN7			= IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_OE__USBPHY2_IDDIG			= IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__EMI_WEIM_RW			= IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__GPIO2_26			= IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__ECSPI2_SS0			= IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__IPU_DI1_PIN8			= IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT		= IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__EMI_WEIM_LBA			= IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__GPIO2_27			= IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__ECSPI2_SS1			= IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__IPU_DI1_PIN17			= IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_LBA__SRC_BT_CFG1_0			= IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__EMI_WEIM_EB_0			= IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__GPIO2_28			= IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11		= IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__IPU_CSI1_D_11			= IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__GPC_PMIC_RDY			= IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB0__SRC_BT_CFG2_7			= IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__EMI_WEIM_EB_1			= IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__GPIO2_29			= IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10		= IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__IPU_CSI1_D_10			= IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_EB1__SRC_BT_CFG2_6			= IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0		= IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__GPIO3_0			= IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9		= IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__IPU_CSI1_D_9			= IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA0__SRC_BT_CFG2_5			= IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1		= IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__GPIO3_1			= IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8		= IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__IPU_CSI1_D_8			= IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA1__SRC_BT_CFG2_4			= IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2		= IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__GPIO3_2			= IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7		= IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__IPU_CSI1_D_7			= IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA2__SRC_BT_CFG2_3			= IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3		= IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__GPIO3_3			= IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6		= IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__IPU_CSI1_D_6			= IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA3__SRC_BT_CFG2_2			= IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4		= IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__GPIO3_4			= IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5		= IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__IPU_CSI1_D_5			= IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA4__SRC_BT_CFG3_7			= IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5		= IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__GPIO3_5			= IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4		= IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__IPU_CSI1_D_4			= IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA5__SRC_BT_CFG3_6			= IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6		= IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__GPIO3_6			= IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3		= IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__IPU_CSI1_D_3			= IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA6__SRC_BT_CFG3_5			= IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7		= IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__GPIO3_7			= IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2		= IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__IPU_CSI1_D_2			= IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA7__SRC_BT_CFG3_4			= IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8		= IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__GPIO3_8			= IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1		= IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__IPU_CSI1_D_1			= IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA8__SRC_BT_CFG3_3			= IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9		= IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__GPIO3_9			= IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0		= IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__IPU_CSI1_D_0			= IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA9__SRC_BT_CFG3_2			= IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10		= IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__GPIO3_10			= IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__IPU_DI1_PIN15		= IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN		= IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA10__SRC_BT_CFG3_1		= IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11		= IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__GPIO3_11			= IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__IPU_DI1_PIN2			= IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC		= IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12		= IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__GPIO3_12			= IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__IPU_DI1_PIN3			= IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC		= IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13		= IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__GPIO3_13			= IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__IPU_DI1_D0_CS		= IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK		= IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14		= IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__GPIO3_14			= IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__IPU_DI1_D1_CS		= IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK		= IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15		= IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__GPIO3_15			= IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__IPU_DI1_PIN1			= IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_DA15__IPU_DI1_PIN4			= IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B		= IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WE_B__GPIO6_12			= IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B		= IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RE_B__GPIO6_13			= IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT		= IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__GPIO5_0			= IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B		= IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX3_P__GPIO6_22			= IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3		= IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX2_P__GPIO6_24			= IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2		= IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_CLK_P__GPIO6_26			= IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK		= IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX1_P__GPIO6_28			= IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1		= IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX0_P__GPIO6_30			= IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0		= IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX3_P__GPIO7_22			= IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3		= IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_CLK_P__GPIO7_24			= IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK		= IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX2_P__GPIO7_26			= IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2		= IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX1_P__GPIO7_28			= IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1		= IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX0_P__GPIO7_30			= IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0		= IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_10__GPIO4_0			= IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_10__OSC32k_32K_OUT		= IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_11__GPIO4_1			= IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_12__GPIO4_2			= IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_13__GPIO4_3			= IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_14__GPIO4_4			= IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__EMI_NANDF_CLE		= IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__GPIO6_7			= IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0		= IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__EMI_NANDF_ALE		= IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__GPIO6_8			= IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1		= IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B		= IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__GPIO6_9			= IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2		= IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0		= IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__GPIO6_10			= IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3		= IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0		= IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__GPIO6_11			= IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4		= IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1		= IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__GPIO6_14			= IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__MLB_MLBCLK			= IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5		= IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2		= IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__GPIO6_15			= IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__IPU_SISG_0			= IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__ESAI1_TX0			= IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__EMI_WEIM_CRE		= IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK		= IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__MLB_MLBSIG			= IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6		= IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3		= IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__GPIO6_16			= IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__IPU_SISG_1			= IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__ESAI1_TX1			= IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__EMI_WEIM_A_26		= IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__MLB_MLBDAT			= IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL),
+	MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7		= IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__FEC_MDIO			= IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__GPIO1_22			= IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__ESAI1_SCKR			= IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__FEC_COL			= IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2		= IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3	= IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49		= IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__FEC_TX_CLK		= IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__GPIO1_23			= IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__ESAI1_FSR			= IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4	= IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50		= IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__FEC_RX_ER			= IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__GPIO1_24			= IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__ESAI1_HCKR			= IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__FEC_RX_CLK			= IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3		= IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__FEC_RX_DV			= IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__GPIO1_25			= IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_CRS_DV__ESAI1_SCKT			= IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__FEC_RDATA_1			= IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__GPIO1_26			= IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__ESAI1_FST			= IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__MLB_MLBSIG			= IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1		= IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__FEC_RDATA_0			= IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__GPIO1_27			= IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__ESAI1_HCKT			= IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_RXD0__OSC32k_32K_OUT		= IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__FEC_TX_EN			= IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__GPIO1_28			= IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2		= IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__FEC_TDATA_1			= IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__GPIO1_29			= IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3		= IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__MLB_MLBCLK			= IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK		= IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__FEC_TDATA_0			= IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__GPIO1_30			= IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1		= IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0		= IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__FEC_MDC			= IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__GPIO1_31			= IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__ESAI1_TX5_RX0			= IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__MLB_MLBDAT			= IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG	= IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1		= IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__PATA_DIOW			= IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__GPIO6_17			= IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__UART1_TXD_MUX		= IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2		= IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__PATA_DMACK			= IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__GPIO6_18			= IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__UART1_RXD_MUX		= IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3		= IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__PATA_DMARQ			= IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__GPIO7_0			= IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__UART2_TXD_MUX		= IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0		= IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4		= IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN		= IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__GPIO7_1		= IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX		= IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1		= IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5	= IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__PATA_INTRQ			= IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__GPIO7_2			= IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__UART2_CTS			= IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__CAN1_TXCAN			= IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2		= IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6		= IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__PATA_DIOR			= IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__GPIO7_3			= IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__UART2_RTS			= IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__CAN1_RXCAN			= IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL),
+	MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7		= IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B	= IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__GPIO7_4			= IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__ESDHC3_CMD		= IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__UART1_CTS		= IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__CAN2_TXCAN		= IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0	= IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__PATA_IORDY			= IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__GPIO7_5			= IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__ESDHC3_CLK			= IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__UART1_RTS			= IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__CAN2_RXCAN			= IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL),
+	MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1		= IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__PATA_DA_0			= IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__GPIO7_6			= IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__ESDHC3_RST			= IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__OWIRE_LINE			= IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2		= IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__PATA_DA_1			= IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__GPIO7_7			= IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__ESDHC4_CMD			= IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__UART3_CTS			= IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3		= IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__PATA_DA_2			= IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__GPIO7_8			= IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__ESDHC4_CLK			= IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__UART3_RTS			= IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4		= IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__PATA_CS_0			= IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__GPIO7_9			= IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__UART3_TXD_MUX		= IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5		= IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__PATA_CS_1			= IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__GPIO7_10			= IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__UART3_RXD_MUX		= IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL),
+	MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6		= IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__PATA_DATA_0		= IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__GPIO2_0			= IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__EMI_NANDF_D_0		= IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__ESDHC3_DAT4		= IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0	= IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0		= IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7		= IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__PATA_DATA_1		= IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__GPIO2_1			= IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__EMI_NANDF_D_1		= IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__ESDHC3_DAT5		= IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1	= IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1		= IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__PATA_DATA_2		= IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__GPIO2_2			= IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__EMI_NANDF_D_2		= IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__ESDHC3_DAT6		= IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2	= IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2		= IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__PATA_DATA_3		= IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__GPIO2_3			= IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__EMI_NANDF_D_3		= IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__ESDHC3_DAT7		= IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3	= IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3		= IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__PATA_DATA_4		= IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__GPIO2_4			= IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__EMI_NANDF_D_4		= IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__ESDHC4_DAT4		= IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4	= IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4		= IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__PATA_DATA_5		= IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__GPIO2_5			= IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__EMI_NANDF_D_5		= IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__ESDHC4_DAT5		= IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5	= IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5		= IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__PATA_DATA_6		= IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__GPIO2_6			= IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__EMI_NANDF_D_6		= IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__ESDHC4_DAT6		= IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6	= IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6		= IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__PATA_DATA_7		= IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__GPIO2_7			= IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__EMI_NANDF_D_7		= IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__ESDHC4_DAT7		= IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7	= IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7		= IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__PATA_DATA_8		= IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__GPIO2_8			= IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__ESDHC1_DAT4		= IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__EMI_NANDF_D_8		= IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__ESDHC3_DAT0		= IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8	= IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8		= IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__PATA_DATA_9		= IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__GPIO2_9			= IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__ESDHC1_DAT5		= IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__EMI_NANDF_D_9		= IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__ESDHC3_DAT1		= IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9	= IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9		= IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__PATA_DATA_10		= IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__GPIO2_10			= IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__ESDHC1_DAT6		= IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__EMI_NANDF_D_10		= IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__ESDHC3_DAT2		= IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10	= IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10		= IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__PATA_DATA_11		= IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__GPIO2_11			= IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__ESDHC1_DAT7		= IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__EMI_NANDF_D_11		= IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__ESDHC3_DAT3		= IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11	= IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11		= IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__PATA_DATA_12		= IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__GPIO2_12			= IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__ESDHC2_DAT4		= IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__EMI_NANDF_D_12		= IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__ESDHC4_DAT0		= IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12	= IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12		= IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__PATA_DATA_13		= IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__GPIO2_13			= IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__ESDHC2_DAT5		= IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__EMI_NANDF_D_13		= IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__ESDHC4_DAT1		= IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13	= IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13		= IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__PATA_DATA_14		= IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__GPIO2_14			= IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__ESDHC2_DAT6		= IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__EMI_NANDF_D_14		= IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__ESDHC4_DAT2		= IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14	= IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14		= IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__PATA_DATA_15		= IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__GPIO2_15			= IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__ESDHC2_DAT7		= IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__EMI_NANDF_D_15		= IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__ESDHC4_DAT3		= IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15	= IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15		= IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__ESDHC1_DAT0			= IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__GPIO1_16			= IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__GPT_CAPIN1			= IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__CSPI_MISO			= IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA0__CCM_PLL3_BYP		= IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__ESDHC1_DAT1			= IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__GPIO1_17			= IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__GPT_CAPIN2			= IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__CSPI_SS0			= IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA1__CCM_PLL4_BYP		= IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__ESDHC1_CMD			= IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_CMD__GPIO1_18			= IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__GPT_CMPOUT1			= IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__CSPI_MOSI			= IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_CMD__CCM_PLL1_BYP			= IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__ESDHC1_DAT2			= IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__GPIO1_19			= IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__GPT_CMPOUT2			= IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__PWM2_PWMO			= IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__WDOG1_WDOG_B		= IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__CSPI_SS1			= IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB	= IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA2__CCM_PLL2_BYP		= IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__ESDHC1_CLK			= IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_CLK__GPIO1_20			= IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__OSC32k_32K_OUT		= IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__GPT_CLKIN			= IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__CSPI_SCLK			= IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_CLK__SATA_PHY_DTB_0		= IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__ESDHC1_DAT3			= IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__GPIO1_21			= IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__GPT_CMPOUT3			= IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__PWM1_PWMO			= IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__WDOG2_WDOG_B		= IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__CSPI_SS2			= IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB	= IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1		= IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__ESDHC2_CLK			= IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_CLK__GPIO1_10			= IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__KPP_COL_5			= IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS		= IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__CSPI_SCLK			= IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_CLK__SCC_RANDOM_V			= IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__ESDHC2_CMD			= IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_CMD__GPIO1_11			= IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__KPP_ROW_5			= IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC		= IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__CSPI_MOSI			= IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_CMD__SCC_RANDOM			= IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__ESDHC2_DAT3			= IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__GPIO1_12			= IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__KPP_COL_6			= IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC		= IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__CSPI_SS2			= IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA3__SJC_DONE			= IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__ESDHC2_DAT2			= IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__GPIO1_13			= IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__KPP_ROW_6			= IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD		= IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__CSPI_SS1			= IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA2__SJC_FAIL			= IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__ESDHC2_DAT1			= IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__GPIO1_14			= IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__KPP_COL_7			= IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS		= IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__CSPI_SS0			= IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA1__RTIC_SEC_VIO		= IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__ESDHC2_DAT0			= IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__GPIO1_15			= IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__KPP_ROW_7			= IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD		= IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__CSPI_MISO			= IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL),
+	MX53_PAD_SD2_DATA0__RTIC_DONE_INT		= IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CCM_CLKO			= IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__GPIO1_0			= IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__KPP_COL_5			= IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK		= IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__EPIT1_EPITO			= IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__SRTC_ALARM_DEB			= IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__USBOH3_USBH1_PWR		= IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_0__CSU_TD				= IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__ESAI1_SCKR			= IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__GPIO1_1			= IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__KPP_ROW_5			= IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK		= IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__PWM2_PWMO			= IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__WDOG2_WDOG_B			= IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__ESDHC1_CD			= IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_1__SRC_TESTER_ACK			= IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__ESAI1_FSR			= IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__GPIO1_9			= IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__KPP_COL_6			= IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__CCM_REF_EN_B			= IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__PWM1_PWMO			= IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__WDOG1_WDOG_B			= IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__ESDHC1_WP			= IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_9__SCC_FAIL_STATE			= IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__ESAI1_HCKR			= IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__GPIO1_3			= IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__I2C3_SCL			= IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__DPLLIP1_TOG_EN			= IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__CCM_CLKO2			= IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0	= IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__USBOH3_USBH1_OC		= IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_3__MLB_MLBCLK			= IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__ESAI1_SCKT			= IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__GPIO1_6			= IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__I2C3_SDA			= IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__CCM_CCM_OUT_0			= IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__CSU_CSU_INT_DEB		= IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1	= IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__ESDHC2_LCTL			= IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_6__MLB_MLBSIG			= IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__ESAI1_FST			= IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__GPIO1_2			= IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__KPP_ROW_6			= IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__CCM_CCM_OUT_1			= IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0		= IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2	= IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__ESDHC2_WP			= IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_2__MLB_MLBDAT			= IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__ESAI1_HCKT			= IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__GPIO1_4			= IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__KPP_COL_7			= IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__CCM_CCM_OUT_2			= IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1		= IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3	= IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__ESDHC2_CD			= IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_4__SCC_SEC_STATE			= IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__ESAI1_TX2_RX3			= IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__GPIO1_5			= IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__KPP_ROW_7			= IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CCM_CLKO			= IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2		= IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4	= IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__I2C3_SCL			= IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_5__CCM_PLL1_BYP			= IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__ESAI1_TX4_RX1			= IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__GPIO1_7			= IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__EPIT1_EPITO			= IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__CAN1_TXCAN			= IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__UART2_TXD_MUX			= IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+	MX53_PAD_GPIO_7__FIRI_RXD			= IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__SPDIF_PLOCK			= IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_7__CCM_PLL2_BYP			= IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__ESAI1_TX5_RX0			= IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__GPIO1_8			= IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__EPIT2_EPITO			= IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__CAN1_RXCAN			= IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__UART2_RXD_MUX			= IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL),
+	MX53_PAD_GPIO_8__FIRI_TXD			= IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__SPDIF_SRCLK			= IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_8__CCM_PLL3_BYP			= IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__ESAI1_TX3_RX2			= IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__GPIO7_11			= IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT		= IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1		= IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__SPDIF_IN1			= IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__I2C3_SDA			= IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL),
+	MX53_PAD_GPIO_16__SJC_DE_B			= IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__ESAI1_TX0			= IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__GPIO7_12			= IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0		= IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__GPC_PMIC_RDY			= IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG		= IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SPDIF_OUT1			= IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__IPU_SNOOP2			= IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_17__SJC_JTAG_ACT			= IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__ESAI1_TX1			= IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__GPIO7_13			= IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1		= IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__OWIRE_LINE			= IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG	= IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK		= IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__ESDHC1_LCTL			= IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL),
+	MX53_PAD_GPIO_18__SRC_SYSTEM_RST		= IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX53_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h
new file mode 100644
index 0000000..c8aff2b
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/sys_proto.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ */
+#ifndef __SYS_PROTO_IMX5_
+#define __SYS_PROTO_IMX5_
+
+#include <asm/mach-imx/sys_proto.h>
+
+#endif /* __SYS_PROTO_IMX5_ */
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
new file mode 100644
index 0000000..a9481a5
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+#ifdef CONFIG_SYS_MX6_HCLK
+#define MXC_HCLK	CONFIG_SYS_MX6_HCLK
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_SYS_MX6_CLK32
+#define MXC_CLK32	CONFIG_SYS_MX6_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_PER_CLK,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_IPG_PERCLK,
+	MXC_UART_CLK,
+	MXC_CSPI_CLK,
+	MXC_AXI_CLK,
+	MXC_EMI_SLOW_CLK,
+	MXC_DDR_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_ESDHC4_CLK,
+	MXC_SATA_CLK,
+	MXC_NFC_CLK,
+	MXC_I2C_CLK,
+};
+
+enum ldb_di_clock {
+	MXC_PLL5_CLK = 0,
+	MXC_PLL2_PFD0_CLK,
+	MXC_PLL2_PFD2_CLK,
+	MXC_MMDC_CH1_CLK,
+	MXC_PLL3_SW_CLK,
+};
+
+enum enet_freq {
+	ENET_25MHZ,
+	ENET_50MHZ,
+	ENET_100MHZ,
+	ENET_125MHZ,
+};
+
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+void setup_gpmi_io_clk(u32 cfg);
+void hab_caam_clock_enable(unsigned char enable);
+void enable_ocotp_clk(unsigned char enable);
+void enable_usboh3_clk(unsigned char enable);
+void enable_uart_clk(unsigned char enable);
+int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
+int enable_sata_clock(void);
+void disable_sata_clock(void);
+int enable_pcie_clock(void);
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+int enable_spi_clk(unsigned char enable, unsigned spi_num);
+void enable_ipu_clock(void);
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
+void enable_enet_clk(unsigned char enable);
+int enable_lcdif_clock(u32 base_addr, bool enable);
+void enable_qspi_clk(int qspi_num);
+void enable_thermal_clk(void);
+void mxs_set_lcdclk(u32 base_addr, u32 freq);
+void select_ldb_di_clock_source(enum ldb_di_clock clk);
+void enable_eim_clk(unsigned char enable);
+int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
new file mode 100644
index 0000000..4174f24
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -0,0 +1,1309 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+
+#define CCM_CCOSR		0x020c4060
+#define CCM_CCGR0		0x020C4068
+#define CCM_CCGR1		0x020C406c
+#define CCM_CCGR2		0x020C4070
+#define CCM_CCGR3		0x020C4074
+#define CCM_CCGR4		0x020C4078
+#define CCM_CCGR5		0x020C407c
+#define CCM_CCGR6		0x020C4080
+
+#define PMU_MISC2		0x020C8170
+
+#ifndef __ASSEMBLY__
+struct mxc_ccm_reg {
+	u32 ccr;	/* 0x0000 */
+	u32 ccdr;
+	u32 csr;
+	u32 ccsr;
+	u32 cacrr;	/* 0x0010*/
+	u32 cbcdr;
+	u32 cbcmr;
+	u32 cscmr1;
+	u32 cscmr2;	/* 0x0020 */
+	u32 cscdr1;
+	u32 cs1cdr;
+	u32 cs2cdr;
+	u32 cdcdr;	/* 0x0030 */
+	u32 chsccdr;
+	u32 cscdr2;
+	u32 cscdr3;
+	u32 cscdr4;	/* 0x0040 */
+	u32 resv0;
+	u32 cdhipr;
+	u32 cdcr;
+	u32 ctor;	/* 0x0050 */
+	u32 clpcr;
+	u32 cisr;
+	u32 cimr;
+	u32 ccosr;	/* 0x0060 */
+	u32 cgpr;
+	u32 CCGR0;
+	u32 CCGR1;
+	u32 CCGR2;	/* 0x0070 */
+	u32 CCGR3;
+	u32 CCGR4;
+	u32 CCGR5;
+	u32 CCGR6;	/* 0x0080 */
+	u32 CCGR7;
+	u32 cmeor;
+	u32 resv[0xfdd];
+	u32 analog_pll_sys;			/* 0x4000 */
+	u32 analog_pll_sys_set;
+	u32 analog_pll_sys_clr;
+	u32 analog_pll_sys_tog;
+	u32 analog_usb1_pll_480_ctrl;		/* 0x4010 */
+	u32 analog_usb1_pll_480_ctrl_set;
+	u32 analog_usb1_pll_480_ctrl_clr;
+	u32 analog_usb1_pll_480_ctrl_tog;
+	u32 analog_reserved0[4];
+	u32 analog_pll_528;			/* 0x4030 */
+	u32 analog_pll_528_set;
+	u32 analog_pll_528_clr;
+	u32 analog_pll_528_tog;
+	u32 analog_pll_528_ss;			/* 0x4040 */
+	u32 analog_reserved1[3];
+	u32 analog_pll_528_num;			/* 0x4050 */
+	u32 analog_reserved2[3];
+	u32 analog_pll_528_denom;		/* 0x4060 */
+	u32 analog_reserved3[3];
+	u32 analog_pll_audio;			/* 0x4070 */
+	u32 analog_pll_audio_set;
+	u32 analog_pll_audio_clr;
+	u32 analog_pll_audio_tog;
+	u32 analog_pll_audio_num;		/* 0x4080*/
+	u32 analog_reserved4[3];
+	u32 analog_pll_audio_denom;		/* 0x4090 */
+	u32 analog_reserved5[3];
+	u32 analog_pll_video;			/* 0x40a0 */
+	u32 analog_pll_video_set;
+	u32 analog_pll_video_clr;
+	u32 analog_pll_video_tog;
+	u32 analog_pll_video_num;		/* 0x40b0 */
+	u32 analog_reserved6[3];
+	u32 analog_pll_video_denom;		/* 0x40c0 */
+	u32 analog_reserved7[7];
+	u32 analog_pll_enet;			/* 0x40e0 */
+	u32 analog_pll_enet_set;
+	u32 analog_pll_enet_clr;
+	u32 analog_pll_enet_tog;
+	u32 analog_pfd_480;			/* 0x40f0 */
+	u32 analog_pfd_480_set;
+	u32 analog_pfd_480_clr;
+	u32 analog_pfd_480_tog;
+	u32 analog_pfd_528;			/* 0x4100 */
+	u32 analog_pfd_528_set;
+	u32 analog_pfd_528_clr;
+	u32 analog_pfd_528_tog;
+	/* PMU Memory Map/Register Definition */
+	u32 pmu_reg_1p1;
+	u32 pmu_reg_1p1_set;
+	u32 pmu_reg_1p1_clr;
+	u32 pmu_reg_1p1_tog;
+	u32 pmu_reg_3p0;
+	u32 pmu_reg_3p0_set;
+	u32 pmu_reg_3p0_clr;
+	u32 pmu_reg_3p0_tog;
+	u32 pmu_reg_2p5;
+	u32 pmu_reg_2p5_set;
+	u32 pmu_reg_2p5_clr;
+	u32 pmu_reg_2p5_tog;
+	u32 pmu_reg_core;
+	u32 pmu_reg_core_set;
+	u32 pmu_reg_core_clr;
+	u32 pmu_reg_core_tog;
+	u32 pmu_misc0;
+	u32 pmu_misc0_set;
+	u32 pmu_misc0_clr;
+	u32 pmu_misc0_tog;
+	u32 pmu_misc1;
+	u32 pmu_misc1_set;
+	u32 pmu_misc1_clr;
+	u32 pmu_misc1_tog;
+	u32 pmu_misc2;
+	u32 pmu_misc2_set;
+	u32 pmu_misc2_clr;
+	u32 pmu_misc2_tog;
+	/* TEMPMON Memory Map/Register Definition */
+	u32 tempsense0;
+	u32 tempsense0_set;
+	u32 tempsense0_clr;
+	u32 tempsense0_tog;
+	u32 tempsense1;
+	u32 tempsense1_set;
+	u32 tempsense1_clr;
+	u32 tempsense1_tog;
+	/* USB Analog Memory Map/Register Definition */
+	u32 usb1_vbus_detect;
+	u32 usb1_vbus_detect_set;
+	u32 usb1_vbus_detect_clr;
+	u32 usb1_vbus_detect_tog;
+	u32 usb1_chrg_detect;
+	u32 usb1_chrg_detect_set;
+	u32 usb1_chrg_detect_clr;
+	u32 usb1_chrg_detect_tog;
+	u32 usb1_vbus_det_stat;
+	u32 usb1_vbus_det_stat_set;
+	u32 usb1_vbus_det_stat_clr;
+	u32 usb1_vbus_det_stat_tog;
+	u32 usb1_chrg_det_stat;
+	u32 usb1_chrg_det_stat_set;
+	u32 usb1_chrg_det_stat_clr;
+	u32 usb1_chrg_det_stat_tog;
+	u32 usb1_loopback;
+	u32 usb1_loopback_set;
+	u32 usb1_loopback_clr;
+	u32 usb1_loopback_tog;
+	u32 usb1_misc;
+	u32 usb1_misc_set;
+	u32 usb1_misc_clr;
+	u32 usb1_misc_tog;
+	u32 usb2_vbus_detect;
+	u32 usb2_vbus_detect_set;
+	u32 usb2_vbus_detect_clr;
+	u32 usb2_vbus_detect_tog;
+	u32 usb2_chrg_detect;
+	u32 usb2_chrg_detect_set;
+	u32 usb2_chrg_detect_clr;
+	u32 usb2_chrg_detect_tog;
+	u32 usb2_vbus_det_stat;
+	u32 usb2_vbus_det_stat_set;
+	u32 usb2_vbus_det_stat_clr;
+	u32 usb2_vbus_det_stat_tog;
+	u32 usb2_chrg_det_stat;
+	u32 usb2_chrg_det_stat_set;
+	u32 usb2_chrg_det_stat_clr;
+	u32 usb2_chrg_det_stat_tog;
+	u32 usb2_loopback;
+	u32 usb2_loopback_set;
+	u32 usb2_loopback_clr;
+	u32 usb2_loopback_tog;
+	u32 usb2_misc;
+	u32 usb2_misc_set;
+	u32 usb2_misc_clr;
+	u32 usb2_misc_tog;
+	u32 digprog;
+	u32 reserved1[7];
+	/* For i.MX 6SoloLite */
+	u32 digprog_sololite;
+};
+#endif
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_RBC_EN				(1 << 27)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK			(0x3F << 21)
+#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET		21
+/* CCR_WB does not exist on i.MX6SX/UL */
+#define MXC_CCM_CCR_WB_COUNT_MASK			0x7
+#define MXC_CCM_CCR_WB_COUNT_OFFSET			(1 << 16)
+#define MXC_CCM_CCR_COSC_EN				(1 << 12)
+#ifdef CONFIG_MX6SX
+#define MXC_CCM_CCR_OSCNT_MASK				0x7F
+#else
+#define MXC_CCM_CCR_OSCNT_MASK				0xFF
+#endif
+#define MXC_CCM_CCR_OSCNT_OFFSET			0
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK			(1 << 16)
+#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK			(1 << 17)
+/* Exists on i.MX6QP */
+#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG		(1 << 18)
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSC_READY				(1 << 5)
+#define MXC_CCM_CSR_REF_EN_B				(1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS			(1 << 15)
+#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS			(1 << 14)
+#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS			(1 << 13)
+#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS			(1 << 12)
+#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS			(1 << 11)
+#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS			(1 << 10)
+#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS			(1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL				(1 << 8)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL			(1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL			(1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL			(1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET			0
+#define MXC_CCM_CACRR_ARM_PODF_MASK			0x7
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK		(0x7 << 27)
+#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET		27
+#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL			(1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL			(1 << 25)
+/* MMDC_CH0 not exists on i.MX6SX */
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET		19
+#define MXC_CCM_CBCDR_AXI_PODF_MASK			(0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_PODF_OFFSET			16
+#define MXC_CCM_CBCDR_AHB_PODF_MASK			(0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET			10
+#define MXC_CCM_CBCDR_IPG_PODF_MASK			(0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET			8
+#define MXC_CCM_CBCDR_AXI_ALT_SEL			(1 << 7)
+#define MXC_CCM_CBCDR_AXI_SEL				(1 << 6)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET		3
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK		(0x7 << 0)
+#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET		0
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK		(0x7 << 29)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET		29
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK		(0x7 << 26)
+#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET		26
+/* LCDIF on i.MX6SX/UL */
+#define MXC_CCM_CBCMR_LCDIF1_PODF_MASK                  (0x7 << 23)
+#define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET                23
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		23
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
+#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET	21
+#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL			(1 << 20)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK		(0x3 << 18)
+#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET		18
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK		(0x3 << 16)
+#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET		16
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
+#endif
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET		12
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL			(1 << 11)
+#endif
+#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL			(1 << 10)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET	8
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		4
+/* Exists on i.MX6QP */
+#define MXC_CCM_CBCMR_PRE_CLK_SEL			(1 << 1)
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK		(0x3 << 29)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET		29
+/* QSPI1 exist on i.MX6SX/UL */
+#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK			(0x7 << 26)
+#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET		26
+#define MXC_CCM_CSCMR1_ACLK_EMI_MASK			(0x3 << 27)
+#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET			27
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET	23
+/* LCFIF2_PODF on i.MX6SX */
+#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK			(0x7 << 20)
+#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET               20
+/* LCDIF_PIX_PODF on i.MX6SL */
+#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK		(0x7 << 20)
+#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET		20
+/* ACLK_EMI on i.MX6DQ/SDL/DQP */
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK		(0x7 << 20)
+#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET		20
+/* CSCMR1_GPMI/BCH exist on i.MX6UL */
+#define MXC_CCM_CSCMR1_GPMI_CLK_SEL			(1 << 19)
+#define MXC_CCM_CSCMR1_BCH_CLK_SEL			(1 << 18)
+#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL			(1 << 19)
+#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL			(1 << 18)
+#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL			(1 << 17)
+#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL			(1 << 16)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET		14
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 10)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		10
+/* QSPI1 exist on i.MX6SX/UL */
+#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK		(0x7 << 7)
+#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET		7
+/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
+#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET		6
+
+#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK			0x3F
+
+/* Define the bits in register CSCMR2 */
+#ifdef CONFIG_MX6SX
+#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK			(0x7 << 21)
+#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET		21
+#endif
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK		(0x3 << 19)
+#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET		19
+#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(1 << 11)
+#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(1 << 10)
+/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3 << 8)
+#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		8
+
+#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK		(0x3F << 2)
+#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET		2
+
+/* Define the bits in register CSCDR1 */
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK		(0x7 << 25)
+#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET		25
+#endif
+/* CSCDR1_GPMI/BCH exist on i.MX6UL */
+#define MXC_CCM_CSCDR1_GPMI_PODF_MASK			(0x7 << 22)
+#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET			22
+#define MXC_CCM_CSCDR1_BCH_PODF_MASK			(0x7 << 19)
+#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET			19
+
+#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK			(0x7 << 22)
+#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET		22
+#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK			(0x7 << 19)
+#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET		19
+#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK			(0x7 << 16)
+#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET		16
+#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK			(0x7 << 11)
+#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET		11
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
+#endif
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x3F
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
+/* UART_CLK_SEL exists on i.MX6SL/SX/QP */
+#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
+
+/* Define the bits in register CS1CDR */
+/* MX6UL, !MX6ULL */
+#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK		(0x7 << 22)
+#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET		22
+#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK		(0x3F << 16)
+#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET		16
+#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET		6
+#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK		0x3F
+#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET		0
+
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK		(0x3F << 25)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET		25
+#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK		(0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET		22
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK		(0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET		16
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK		(0x3 << 9)
+#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET		9
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET		6
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK		0x3F
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		0
+
+/* Define the bits in register CS2CDR */
+/* QSPI2 on i.MX6SX */
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK             (0x3F << 21)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET           21
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)                       (((v) & 0x3f) << 21)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK             (0x7 << 18)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET           18
+#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v)                       (((v) & 0x7) << 18)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK              (0x7 << 15)
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET            15
+#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v)                        (((v) & 0x7) << 15)
+
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK		(0x3F << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET		21
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v)			(((v) & 0x3f) << 21)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK		(0x7 << 18)
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET		18
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v)			(((v) & 0x7) << 18)
+
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP		(0x7 << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP		15
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v)		(((v) & 0x7) << 15)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ		(0x3 << 16)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ		16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)		(((v) & 0x3) << 16)
+
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		\
+	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP :		\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		\
+	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP :	\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			\
+	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) :		\
+	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
+
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK		(0x7 << 12)
+#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET		12
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET		9
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET		6
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK		0x3F
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET		0
+
+/* Define the bits in register CDCDR */
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK			(0x7 << 29)
+#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET		29
+#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL			(1 << 28)
+#endif
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK		(0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET		25
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(0x7 << 22)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET		22
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK		(0x3 << 20)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET		20
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK		(0x7 << 12)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET		12
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK		(0x7 << 9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET		9
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK		(0x3 << 7)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET		7
+
+/* Define the bits in register CHSCCDR */
+/* i.MX6SX */
+#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK		(0x7 << 15)
+#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET		15
+#define MXC_CCM_CHSCCDR_ENET_PODF_MASK			(0x7 << 12)
+#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET		12
+#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET		9
+#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK		(0x7 << 6)
+#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET		6
+#define MXC_CCM_CHSCCDR_M4_PODF_MASK			(0x7 << 3)
+#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET			3
+#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK			(0x7)
+#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET		0
+
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET	15
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK		(0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET		12
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET		9
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET	6
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET		3
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK		(0x7)
+#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET		0
+
+/* i.MX6ULL */
+#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK		(0x7 << 15)
+#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET		15
+#define MXC_CCM_CHSCCDR_EPDC_PODF_MASK			(0x7 << 12)
+#define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET		12
+#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET		9
+
+#define CHSCCDR_CLK_SEL_LDB_DI0				3
+#define CHSCCDR_PODF_DIVIDE_BY_3			2
+#define CHSCCDR_IPU_PRE_CLK_540M_PFD			5
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
+#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
+/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
+/* LCDIF1 on i.MX6SX/UL */
+#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK             (0x7 << 15)
+#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET           15
+#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK              (0x7 << 12)
+#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET            12
+#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK              (0x7 << 9)
+#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET            9
+/* LCDIF2 on i.MX6SX */
+#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK             (0x7 << 6)
+#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET           6
+#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK              (0x7 << 3)
+#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET            3
+#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK              (0x7 << 0)
+#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET             0
+
+/*LCD on i.MX6SL */
+#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK		(0x7 << 6)
+#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET		6
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK		(0x7 << 3)
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET		3
+
+/* All IPU2_DI1 are LCDIF1 on MX6SX */
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	15
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK		(0x7 << 12)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET		12
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET		9
+/* All IPU2_DI0 are LCDIF2 on MX6SX */
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK	(0x7 << 6)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET	6
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET		3
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK		0x7
+#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET		0
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET		16
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET		14
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK		(0x7 << 11)
+#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET		11
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK		(0x3 << 9)
+#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET		9
+
+/* For i.MX6SL */
+#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET		16
+#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET		14
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		(1 << 5)
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY		(1 << 4)
+#endif
+#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY		(1 << 3)
+#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY		(1 << 2)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY			(1 << 1)
+#define MXC_CCM_CDHIPR_AXI_PODF_BUSY			1
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_MASK_L2CC_IDLE			(1 << 27)
+#define MXC_CCM_CLPCR_MASK_SCU_IDLE			(1 << 26)
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CLPCR_MASK_CORE3_WFI			(1 << 25)
+#define MXC_CCM_CLPCR_MASK_CORE2_WFI			(1 << 24)
+#define MXC_CCM_CLPCR_MASK_CORE1_WFI			(1 << 23)
+#endif
+#define MXC_CCM_CLPCR_MASK_CORE0_WFI			(1 << 22)
+#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS		(1 << 21)
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS		(1 << 19)
+#define MXC_CCM_CLPCR_WB_CORE_AT_LPM			(1 << 17)
+#endif
+#define MXC_CCM_CLPCR_WB_PER_AT_LPM			(1 << 16)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN			(1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK			(0x3 << 9)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET			9
+#define MXC_CCM_CLPCR_VSTBY				(1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC			(1 << 7)
+#define MXC_CCM_CLPCR_SBYOS				(1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM		(1 << 5)
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK			(0x3 << 3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET		3
+#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY		(1 << 2)
+#endif
+#define MXC_CCM_CLPCR_LPM_MASK				0x3
+#define MXC_CCM_CLPCR_LPM_OFFSET			0
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED			(1 << 26)
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED		(1 << 23)
+#endif
+#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED		(1 << 22)
+#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED		(1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED			(1 << 20)
+#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED		(1 << 19)
+#define MXC_CCM_CISR_AXI_PODF_LOADED			(1 << 17)
+#define MXC_CCM_CISR_COSC_READY				(1 << 6)
+#define MXC_CCM_CISR_LRF_PLL				1
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED		(1 << 26)
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED		(1 << 23)
+#endif
+#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED		(1 << 22)
+#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED		(1 << 21)
+#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED		(1 << 20)
+#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED	(1 << 19)
+#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED		(1 << 17)
+#define MXC_CCM_CIMR_MASK_COSC_READY			(1 << 6)
+#define MXC_CCM_CIMR_MASK_LRF_PLL			1
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET			(1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK			(0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET			21
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET			16
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK			(0x1F << 16)
+#define MXC_CCM_CCOSR_CLK_OUT_SEL			(0x1 << 8)
+#define MXC_CCM_CCOSR_CKOL_EN				(0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK			(0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET			4
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK			0xF
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET			0
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_FAST_PLL_EN			(1 << 16)
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(1 << 4)
+#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS			(1 << 2)
+#define MXC_CCM_CGPR_PMIC_DELAY_SCALER			1
+
+/* Define the bits in registers CCGRx */
+#define MXC_CCM_CCGR_CG_MASK				3
+
+/* i.MX 6ULL */
+#define MXC_CCM_CCGR0_DCP_CLK_OFFSET		10
+#define MXC_CCM_CCGR0_DCP_CLK_MASK		(3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET)
+#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET	12
+#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK	(3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET)
+
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			0
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK			(3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			2
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK			(3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA_OFFSET			4
+#define MXC_CCM_CCGR0_APBHDMA_MASK			(3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
+#define MXC_CCM_CCGR0_ASRC_OFFSET			6
+#define MXC_CCM_CCGR0_ASRC_MASK				(3 << MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET		8
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK		(3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET		10
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK		(3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET		12
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK		(3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_OFFSET			14
+#define MXC_CCM_CCGR0_CAN1_MASK				(3 << MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET		16
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK			(3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_OFFSET			18
+#define MXC_CCM_CCGR0_CAN2_MASK				(3 << MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET		20
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK			(3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET		22
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK		(3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_OFFSET			24
+#define MXC_CCM_CCGR0_DCIC1_MASK			(3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_OFFSET			26
+#define MXC_CCM_CCGR0_DCIC2_MASK			(3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
+#ifdef CONFIG_MX6SX
+#define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET			30
+#define MXC_CCM_CCGR0_AIPS_TZ3_MASK			(3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
+#else
+#define MXC_CCM_CCGR0_DTCP_OFFSET			28
+#define MXC_CCM_CCGR0_DTCP_MASK				(3 << MXC_CCM_CCGR0_DTCP_OFFSET)
+#endif
+
+#define MXC_CCM_CCGR1_ECSPI1S_OFFSET			0
+#define MXC_CCM_CCGR1_ECSPI1S_MASK			(3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_OFFSET			2
+#define MXC_CCM_CCGR1_ECSPI2S_MASK			(3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_OFFSET			4
+#define MXC_CCM_CCGR1_ECSPI3S_MASK			(3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_OFFSET			6
+#define MXC_CCM_CCGR1_ECSPI4S_MASK			(3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_OFFSET			8
+#define MXC_CCM_CCGR1_ECSPI5S_MASK			(3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+/* CCGR1_ENET does not exist on i.MX6SX/UL */
+#define MXC_CCM_CCGR1_ENET_OFFSET			10
+#define MXC_CCM_CCGR1_ENET_MASK				(3 << MXC_CCM_CCGR1_ENET_OFFSET)
+#define MXC_CCM_CCGR1_EPIT1S_OFFSET			12
+#define MXC_CCM_CCGR1_EPIT1S_MASK			(3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_OFFSET			14
+#define MXC_CCM_CCGR1_EPIT2S_MASK			(3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_OFFSET			16
+#define MXC_CCM_CCGR1_ESAIS_MASK			(3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
+#ifdef CONFIG_MX6SX
+#define MXC_CCM_CCGR1_WAKEUP_OFFSET			18
+#define MXC_CCM_CCGR1_WAKEUP_MASK			(3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
+#endif
+#define MXC_CCM_CCGR1_GPT_BUS_OFFSET			20
+#define MXC_CCM_CCGR1_GPT_BUS_MASK			(3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET			22
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK			(3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CCGR1_GPU2D_OFFSET			24
+#define MXC_CCM_CCGR1_GPU2D_MASK			(3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
+#endif
+#define MXC_CCM_CCGR1_GPU3D_OFFSET			26
+#define MXC_CCM_CCGR1_GPU3D_MASK			(3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
+#ifdef CONFIG_MX6SX
+#define MXC_CCM_CCGR1_OCRAM_S_OFFSET			28
+#define MXC_CCM_CCGR1_OCRAM_S_MASK			(3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
+#define MXC_CCM_CCGR1_CANFD_OFFSET			30
+#define MXC_CCM_CCGR1_CANFD_MASK			(3 << MXC_CCM_CCGR1_CANFD_OFFSET)
+#endif
+
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET		0
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK		(3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+/* i.MX6SX/UL */
+#define MXC_CCM_CCGR2_CSI_OFFSET			2
+#define MXC_CCM_CCGR2_CSI_MASK				(3 << MXC_CCM_CCGR2_CSI_OFFSET)
+
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET		4
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK		(3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#endif
+#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET		6
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET		8
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET		10
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK			(3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET		8
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK			(3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET			12
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK			(3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET		14
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK		(3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_OFFSET			16
+#define MXC_CCM_CCGR2_IPMUX1_MASK			(3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_OFFSET			18
+#define MXC_CCM_CCGR2_IPMUX2_MASK			(3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_OFFSET			20
+#define MXC_CCM_CCGR2_IPMUX3_MASK			(3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET	22
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+/* i.MX6SX/UL LCD and PXP */
+#define MXC_CCM_CCGR2_LCD_OFFSET			28
+#define MXC_CCM_CCGR2_LCD_MASK				(3 << MXC_CCM_CCGR2_LCD_OFFSET)
+#define MXC_CCM_CCGR2_PXP_OFFSET			30
+#define MXC_CCM_CCGR2_PXP_MASK				(3 << MXC_CCM_CCGR2_PXP_OFFSET)
+
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET	24
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET	26
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+
+/* i.MX6ULL */
+#define MXC_CCM_CCGR2_ESAI_CLK_OFFSET		0
+#define MXC_CCM_CCGR2_ESAI_CLK_MASK		(3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET)
+#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET	4
+#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK	(3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET)
+
+/* Exist on i.MX6SX */
+#define MXC_CCM_CCGR3_M4_OFFSET					2
+#define MXC_CCM_CCGR3_M4_MASK					(3 << MXC_CCM_CCGR3_M4_OFFSET)
+/* i.MX6ULL */
+#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET			4
+#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK			(3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR3_ENET_OFFSET				4
+#define MXC_CCM_CCGR3_ENET_MASK					(3 << MXC_CCM_CCGR3_ENET_OFFSET)
+#define MXC_CCM_CCGR3_QSPI_OFFSET				14
+#define MXC_CCM_CCGR3_QSPI_MASK					(3 << MXC_CCM_CCGR3_QSPI_OFFSET)
+
+/* i.MX6SL */
+#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET				6
+#define MXC_CCM_CCGR3_LCDIF_AXI_MASK				(3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET				8
+#define MXC_CCM_CCGR3_LCDIF_PIX_MASK				(3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET)
+
+#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET				0
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET			2
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET			4
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+
+#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET				6
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET			8
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET			10
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK				(3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_OFFSET				12
+#define MXC_CCM_CCGR3_LDB_DI0_MASK				(3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+
+/* QSPI1 exists on i.MX6SX/UL */
+#define MXC_CCM_CCGR3_QSPI1_OFFSET				14
+#define MXC_CCM_CCGR3_QSPI1_MASK				(3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
+
+#define MXC_CCM_CCGR3_LDB_DI1_OFFSET				14
+#define MXC_CCM_CCGR3_LDB_DI1_MASK				(3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET			16
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK			(3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+
+/* A7_CLKDIV/WDOG1 on i.MX6UL */
+#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET			16
+#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK			(3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET			18
+#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK			(3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET)
+
+#define MXC_CCM_CCGR3_MLB_OFFSET				18
+#define MXC_CCM_CCGR3_MLB_MASK					(3 << MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET	20
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK		(3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET	22
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK		(3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#endif
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET		24
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET		26
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK			(3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+
+#define MXC_CCM_CCGR3_DISP_AXI_OFFSET                           6
+#define MXC_CCM_CCGR3_DISP_AXI_MASK                             (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET                         8
+#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK                           (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET                         10
+#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK                           (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET)
+/* AXI on i.MX6UL */
+#define MXC_CCM_CCGR3_AXI_CLK_OFFSET				28
+#define MXC_CCM_CCGR3_AXI_CLK_MASK				(3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_OFFSET				28
+#define MXC_CCM_CCGR3_OCRAM_MASK				(3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
+
+/* GPIO4 on i.MX6UL/ULL */
+#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET				30
+#define MXC_CCM_CCGR3_GPIO4_CLK_MASK				(3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
+
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET			30
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK				(3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+#endif
+
+/* i.MX6ULL */
+#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET		30
+#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK			(3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET)
+
+#define MXC_CCM_CCGR4_PCIE_OFFSET				0
+#define MXC_CCM_CCGR4_PCIE_MASK					(3 << MXC_CCM_CCGR4_PCIE_OFFSET)
+/* QSPI2 on i.MX6SX */
+#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET				10
+#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK				(3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET		8
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK			(3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET			12
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK			(3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET	14
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK	(3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_OFFSET				16
+#define MXC_CCM_CCGR4_PWM1_MASK					(3 << MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_OFFSET				18
+#define MXC_CCM_CCGR4_PWM2_MASK					(3 << MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_OFFSET				20
+#define MXC_CCM_CCGR4_PWM3_MASK					(3 << MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_OFFSET				22
+#define MXC_CCM_CCGR4_PWM4_MASK					(3 << MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET		24
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET	26
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET	28
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK	(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET		30
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK		(3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+
+#define MXC_CCM_CCGR5_ROM_OFFSET			0
+#define MXC_CCM_CCGR5_ROM_MASK				(3 << MXC_CCM_CCGR5_ROM_OFFSET)
+#ifndef CONFIG_MX6SX
+#define MXC_CCM_CCGR5_SATA_OFFSET			4
+#define MXC_CCM_CCGR5_SATA_MASK				(3 << MXC_CCM_CCGR5_SATA_OFFSET)
+#endif
+#define MXC_CCM_CCGR5_SDMA_OFFSET			6
+#define MXC_CCM_CCGR5_SDMA_MASK				(3 << MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_OFFSET			12
+#define MXC_CCM_CCGR5_SPBA_MASK				(3 << MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_OFFSET			14
+#define MXC_CCM_CCGR5_SPDIF_MASK			(3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_OFFSET			18
+#define MXC_CCM_CCGR5_SSI1_MASK				(3 << MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_OFFSET			20
+#define MXC_CCM_CCGR5_SSI2_MASK				(3 << MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_OFFSET			22
+#define MXC_CCM_CCGR5_SSI3_MASK				(3 << MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_UART_OFFSET			24
+#define MXC_CCM_CCGR5_UART_MASK				(3 << MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET		26
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK			(3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+#ifdef CONFIG_MX6SX
+#define MXC_CCM_CCGR5_SAI1_OFFSET			20
+#define MXC_CCM_CCGR5_SAI1_MASK				(3 << MXC_CCM_CCGR5_SAI1_OFFSET)
+#define MXC_CCM_CCGR5_SAI2_OFFSET			30
+#define MXC_CCM_CCGR5_SAI2_MASK				(3 << MXC_CCM_CCGR5_SAI2_OFFSET)
+#endif
+
+/* PRG_CLK0 exists on i.MX6QP */
+#define MXC_CCM_CCGR6_PRG_CLK0_MASK		(3 << 24)
+
+#define MXC_CCM_CCGR6_USBOH3_OFFSET		0
+#define MXC_CCM_CCGR6_USBOH3_MASK		(3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_OFFSET		2
+#define MXC_CCM_CCGR6_USDHC1_MASK		(3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_OFFSET		4
+#define MXC_CCM_CCGR6_USDHC2_MASK		(3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_SIM1_CLK_OFFSET		6
+#define MXC_CCM_CCGR6_SIM1_CLK_MASK		(3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET)
+#define MXC_CCM_CCGR6_SIM2_CLK_OFFSET		8
+#define MXC_CCM_CCGR6_SIM2_CLK_MASK		(3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET)
+/* i.MX6ULL */
+#define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET		8
+#define MXC_CCM_CCGR6_IPMUX4_CLK_MASK		(3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET)
+/* GPMI/BCH on i.MX6UL */
+#define MXC_CCM_CCGR6_BCH_OFFSET		6
+#define MXC_CCM_CCGR6_BCH_MASK			(3 << MXC_CCM_CCGR6_BCH_OFFSET)
+#define MXC_CCM_CCGR6_GPMI_OFFSET		8
+#define MXC_CCM_CCGR6_GPMI_MASK		(3 << MXC_CCM_CCGR6_GPMI_OFFSET)
+
+#define MXC_CCM_CCGR6_USDHC3_OFFSET		6
+#define MXC_CCM_CCGR6_USDHC3_MASK		(3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_OFFSET		8
+#define MXC_CCM_CCGR6_USDHC4_MASK		(3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET		10
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK		(3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+/* i.MX6ULL */
+#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET	18
+#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK		(3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET)
+/* The following *CCGR6* exist only i.MX6SX */
+#define MXC_CCM_CCGR6_PWM8_OFFSET		16
+#define MXC_CCM_CCGR6_PWM8_MASK			(3 << MXC_CCM_CCGR6_PWM8_OFFSET)
+#define MXC_CCM_CCGR6_VADC_OFFSET		20
+#define MXC_CCM_CCGR6_VADC_MASK			(3 << MXC_CCM_CCGR6_VADC_OFFSET)
+#define MXC_CCM_CCGR6_GIS_OFFSET		22
+#define MXC_CCM_CCGR6_GIS_MASK			(3 << MXC_CCM_CCGR6_GIS_OFFSET)
+#define MXC_CCM_CCGR6_I2C4_OFFSET		24
+#define MXC_CCM_CCGR6_I2C4_MASK			(3 << MXC_CCM_CCGR6_I2C4_OFFSET)
+#define MXC_CCM_CCGR6_PWM5_OFFSET		26
+#define MXC_CCM_CCGR6_PWM5_MASK			(3 << MXC_CCM_CCGR6_PWM5_OFFSET)
+#define MXC_CCM_CCGR6_PWM6_OFFSET		28
+#define MXC_CCM_CCGR6_PWM6_MASK			(3 << MXC_CCM_CCGR6_PWM6_OFFSET)
+#define MXC_CCM_CCGR6_PWM7_OFFSET		30
+#define MXC_CCM_CCGR6_PWM7_MASK			(3 << MXC_CCM_CCGR6_PWM7_OFFSET)
+/* The two does not exist on i.MX6SX */
+#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET		12
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK		(3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+
+#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
+#define BP_ANADIG_PLL_SYS_RSVD0      20
+#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
+#define BF_ANADIG_PLL_SYS_RSVD0(v)  \
+	(((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
+#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
+#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
+#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
+#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
+#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
+#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_SYS_DIV_SELECT      0
+#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_SYS_DIV_SELECT(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
+
+#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
+#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1      17
+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
+#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v)  \
+	(((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
+#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC      14
+#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
+#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
+#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
+#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
+#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
+#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
+#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
+#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0      2
+#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
+#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v)  \
+	(((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
+#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT      0
+#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
+#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v)  \
+	(((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
+
+#define BM_ANADIG_PLL_528_LOCK 0x80000000
+#define BP_ANADIG_PLL_528_RSVD1      19
+#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
+#define BF_ANADIG_PLL_528_RSVD1(v)  \
+	(((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
+#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_528_BYPASS 0x00010000
+#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_528_ENABLE 0x00002000
+#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_528_RSVD0      1
+#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
+#define BF_ANADIG_PLL_528_RSVD0(v)  \
+	(((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
+#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
+
+#define BP_ANADIG_PLL_528_SS_STOP      16
+#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
+#define BF_ANADIG_PLL_528_SS_STOP(v) \
+	(((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
+#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
+#define BP_ANADIG_PLL_528_SS_STEP      0
+#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
+#define BF_ANADIG_PLL_528_SS_STEP(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
+
+#define BP_ANADIG_PLL_528_NUM_RSVD0      30
+#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
+#define BP_ANADIG_PLL_528_NUM_A      0
+#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_NUM_A(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
+
+#define BP_ANADIG_PLL_528_DENOM_RSVD0      30
+#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
+#define BP_ANADIG_PLL_528_DENOM_B      0
+#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_528_DENOM_B(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
+
+#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
+#define BP_ANADIG_PLL_AUDIO_RSVD0      22
+#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
+#define BF_ANADIG_PLL_AUDIO_RSVD0(v)  \
+	(((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
+#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT      19
+#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v)  \
+	(((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
+#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_AUDIO_DIV_SELECT      0
+#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0      30
+#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
+#define BP_ANADIG_PLL_AUDIO_NUM_A      0
+#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_NUM_A(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
+
+#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0      30
+#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
+#define BP_ANADIG_PLL_AUDIO_DENOM_B      0
+#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_AUDIO_DENOM_B(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
+
+#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
+#define BP_ANADIG_PLL_VIDEO_RSVD0      22
+#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
+#define BF_ANADIG_PLL_VIDEO_RSVD0(v)  \
+	(((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
+#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT      19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v)  \
+	(((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
+#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
+#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
+#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_VIDEO_DIV_SELECT      0
+#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
+#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
+
+#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0      30
+#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
+#define BP_ANADIG_PLL_VIDEO_NUM_A      0
+#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_NUM_A(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
+
+#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0      30
+#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
+#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
+	(((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
+#define BP_ANADIG_PLL_VIDEO_DENOM_B      0
+#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
+#define BF_ANADIG_PLL_VIDEO_DENOM_B(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
+
+#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
+#define BP_ANADIG_PLL_ENET_RSVD1      21
+#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
+#define BF_ANADIG_PLL_ENET_RSVD1(v)  \
+	(((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
+#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
+#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
+#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
+#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
+#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
+#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
+#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC      14
+#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
+#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v)  \
+	(((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M  0x0
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
+#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR      0x3
+#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
+#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
+#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
+#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
+#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
+#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
+#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
+#define BP_ANADIG_PLL_ENET_RSVD0      2
+#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
+#define BF_ANADIG_PLL_ENET_RSVD0(v)  \
+	(((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
+#define BP_ANADIG_PLL_ENET_DIV_SELECT      0
+#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
+#define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  \
+	(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
+
+/* ENET2 for i.MX6SX/UL */
+#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
+#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
+#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v)  \
+	(((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
+
+#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_480_PFD3_FRAC      24
+#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_480_PFD3_FRAC(v)  \
+	(((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
+#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_480_PFD2_FRAC      16
+#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_480_PFD2_FRAC(v)  \
+	(((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
+#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_480_PFD1_FRAC      8
+#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_480_PFD1_FRAC(v)  \
+	(((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
+#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_480_PFD0_FRAC      0
+#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_480_PFD0_FRAC(v)  \
+	(((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
+
+#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
+#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
+#define BP_ANADIG_PFD_528_PFD3_FRAC      24
+#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
+#define BF_ANADIG_PFD_528_PFD3_FRAC(v)  \
+	(((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
+#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
+#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
+#define BP_ANADIG_PFD_528_PFD2_FRAC      16
+#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
+#define BF_ANADIG_PFD_528_PFD2_FRAC(v)  \
+	(((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
+#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
+#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
+#define BP_ANADIG_PFD_528_PFD1_FRAC      8
+#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
+#define BF_ANADIG_PFD_528_PFD1_FRAC(v)  \
+	(((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
+#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
+#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
+#define BP_ANADIG_PFD_528_PFD0_FRAC      0
+#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
+#define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
+	(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
+
+#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4
+
+#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
+#define BP_PMU_MISC2_AUDIO_DIV_MSB 23
+
+#define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15)
+#define BP_PMU_MISC2_AUDIO_DIV_LSB 15
+
+#define PMU_MISC2_AUDIO_DIV(v) \
+	(((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \
+	(BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \
+	((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \
+	 BP_PMU_MISC2_AUDIO_DIV_LSB))
+
+#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/gpio.h b/arch/arm/include/asm/arch-mx6/gpio.h
new file mode 100644
index 0000000..b391319
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/gpio.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ */
+
+
+#ifndef __ASM_ARCH_MX6_GPIO_H
+#define __ASM_ARCH_MX6_GPIO_H
+
+#include <asm/mach-imx/gpio.h>
+
+#endif	/* __ASM_ARCH_MX6_GPIO_H */
diff --git a/arch/arm/include/asm/arch-mx6/imx-rdc.h b/arch/arm/include/asm/arch-mx6/imx-rdc.h
new file mode 100644
index 0000000..ecdd64d
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/imx-rdc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __IMX_RDC_H__
+#define __IMX_RDC_H__
+
+#if defined(CONFIG_MX6SX)
+#include "mx6sx_rdc.h"
+#else
+#error "Please select cpu"
+#endif /* CONFIG_MX6SX */
+
+#endif	/* __IMX_RDC_H__*/
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
new file mode 100644
index 0000000..4f01b20
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -0,0 +1,1007 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
+#define __ASM_ARCH_MX6_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define ROMCP_ARB_BASE_ADDR             0x00000000
+#define ROMCP_ARB_END_ADDR              0x000FFFFF
+
+#ifdef CONFIG_MX6SL
+#define GPU_2D_ARB_BASE_ADDR            0x02200000
+#define GPU_2D_ARB_END_ADDR             0x02203FFF
+#define OPENVG_ARB_BASE_ADDR            0x02204000
+#define OPENVG_ARB_END_ADDR             0x02207FFF
+#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define CAAM_ARB_BASE_ADDR              0x00100000
+#define CAAM_ARB_END_ADDR               0x00107FFF
+#define GPU_ARB_BASE_ADDR               0x01800000
+#define GPU_ARB_END_ADDR                0x01803FFF
+#define APBH_DMA_ARB_BASE_ADDR          0x01804000
+#define APBH_DMA_ARB_END_ADDR           0x0180BFFF
+#define M4_BOOTROM_BASE_ADDR			0x007F8000
+
+#elif !defined(CONFIG_MX6SLL)
+#define CAAM_ARB_BASE_ADDR              0x00100000
+#define CAAM_ARB_END_ADDR               0x00103FFF
+#define APBH_DMA_ARB_BASE_ADDR          0x00110000
+#define APBH_DMA_ARB_END_ADDR           0x00117FFF
+#define HDMI_ARB_BASE_ADDR              0x00120000
+#define HDMI_ARB_END_ADDR               0x00128FFF
+#define GPU_3D_ARB_BASE_ADDR            0x00130000
+#define GPU_3D_ARB_END_ADDR             0x00133FFF
+#define GPU_2D_ARB_BASE_ADDR            0x00134000
+#define GPU_2D_ARB_END_ADDR             0x00137FFF
+#define DTCP_ARB_BASE_ADDR              0x00138000
+#define DTCP_ARB_END_ADDR               0x0013BFFF
+#endif	/* CONFIG_MX6SL */
+
+#define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
+/* GPV - PL301 configuration ports */
+#if (defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
+#define GPV2_BASE_ADDR                  0x00D00000
+#define GPV3_BASE_ADDR			0x00E00000
+#define GPV4_BASE_ADDR			0x00F00000
+#define GPV5_BASE_ADDR			0x01000000
+#define GPV6_BASE_ADDR			0x01100000
+#define PCIE_ARB_BASE_ADDR              0x08000000
+#define PCIE_ARB_END_ADDR               0x08FFFFFF
+
+#else
+#define GPV2_BASE_ADDR			0x00200000
+#define GPV3_BASE_ADDR			0x00300000
+#define GPV4_BASE_ADDR			0x00800000
+#define PCIE_ARB_BASE_ADDR              0x01000000
+#define PCIE_ARB_END_ADDR               0x01FFFFFF
+#endif
+
+#define IRAM_BASE_ADDR			0x00900000
+#define SCU_BASE_ADDR                   0x00A00000
+#define IC_INTERFACES_BASE_ADDR         0x00A00100
+#define GLOBAL_TIMER_BASE_ADDR          0x00A00200
+#define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
+#define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
+#define L2_PL310_BASE			0x00A02000
+#define GPV0_BASE_ADDR                  0x00B00000
+#define GPV1_BASE_ADDR                  0x00C00000
+
+#define AIPS1_ARB_BASE_ADDR             0x02000000
+#define AIPS1_ARB_END_ADDR              0x020FFFFF
+#define AIPS2_ARB_BASE_ADDR             0x02100000
+#define AIPS2_ARB_END_ADDR              0x021FFFFF
+/* AIPS3 only on i.MX6SX */
+#define AIPS3_ARB_BASE_ADDR             0x02200000
+#define AIPS3_ARB_END_ADDR              0x022FFFFF
+#ifdef CONFIG_MX6SX
+#define WEIM_ARB_BASE_ADDR              0x50000000
+#define WEIM_ARB_END_ADDR               0x57FFFFFF
+#define QSPI0_AMBA_BASE                0x60000000
+#define QSPI0_AMBA_END                 0x6FFFFFFF
+#define QSPI1_AMBA_BASE                0x70000000
+#define QSPI1_AMBA_END                 0x7FFFFFFF
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define WEIM_ARB_BASE_ADDR              0x50000000
+#define WEIM_ARB_END_ADDR               0x57FFFFFF
+#define QSPI0_AMBA_BASE                 0x60000000
+#define QSPI0_AMBA_END                  0x6FFFFFFF
+#elif !defined(CONFIG_MX6SLL)
+#define SATA_ARB_BASE_ADDR              0x02200000
+#define SATA_ARB_END_ADDR               0x02203FFF
+#define OPENVG_ARB_BASE_ADDR            0x02204000
+#define OPENVG_ARB_END_ADDR             0x02207FFF
+#define HSI_ARB_BASE_ADDR               0x02208000
+#define HSI_ARB_END_ADDR                0x0220BFFF
+#define IPU1_ARB_BASE_ADDR              0x02400000
+#define IPU1_ARB_END_ADDR               0x027FFFFF
+#define IPU2_ARB_BASE_ADDR              0x02800000
+#define IPU2_ARB_END_ADDR               0x02BFFFFF
+#define WEIM_ARB_BASE_ADDR              0x08000000
+#define WEIM_ARB_END_ADDR               0x0FFFFFFF
+#endif
+
+#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
+	defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define MMDC0_ARB_BASE_ADDR             0x80000000
+#define MMDC0_ARB_END_ADDR              0xFFFFFFFF
+#define MMDC1_ARB_BASE_ADDR             0xC0000000
+#define MMDC1_ARB_END_ADDR              0xFFFFFFFF
+#else
+#define MMDC0_ARB_BASE_ADDR             0x10000000
+#define MMDC0_ARB_END_ADDR              0x7FFFFFFF
+#define MMDC1_ARB_BASE_ADDR             0x80000000
+#define MMDC1_ARB_END_ADDR              0xFFFFFFFF
+#endif
+
+#ifndef CONFIG_MX6SX
+#define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
+#define IPU_SOC_OFFSET			0x00200000
+#endif
+
+/* Defines for Blocks connected via AIPS (SkyBlue) */
+#define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
+#define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
+#define ATZ3_BASE_ADDR              AIPS3_ARB_BASE_ADDR
+#define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
+#define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
+#define AIPS3_BASE_ADDR             AIPS3_ON_BASE_ADDR
+
+#define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
+#define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
+#define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
+#define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
+#define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
+
+#define MX6SL_UART5_BASE_ADDR       (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SLL_UART4_BASE_ADDR      (ATZ1_BASE_ADDR + 0x18000)
+#define MX6UL_UART7_BASE_ADDR       (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SL_UART2_BASE_ADDR       (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SLL_UART2_BASE_ADDR      (ATZ1_BASE_ADDR + 0x24000)
+#define MX6UL_UART8_BASE_ADDR       (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SL_UART3_BASE_ADDR       (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SLL_UART3_BASE_ADDR      (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SL_UART4_BASE_ADDR       (ATZ1_BASE_ADDR + 0x38000)
+
+#ifndef CONFIG_MX6SX
+#define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
+#endif
+#define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)
+#define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
+#define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
+#define UART8_BASE                  (ATZ1_BASE_ADDR + 0x24000)
+#define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
+#define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
+#define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
+#define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
+
+#ifndef CONFIG_MX6SX
+#define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
+#define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
+#endif
+#define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
+
+#define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
+#define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
+#define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
+#define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
+#define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
+#define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
+#define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
+/* QOSC on i.MX6SLL */
+#define QOSC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
+#define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
+#define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
+#define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
+#define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
+#define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
+#define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
+#define MX6UL_SNVS_LP_BASE_ADDR     (AIPS1_OFF_BASE_ADDR + 0x30000)
+#define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
+#define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
+#define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
+#define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
+#define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
+#define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
+#define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
+#define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
+#define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
+#define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
+#define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
+#define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
+#define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
+#define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
+#define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
+#define IOMUXC_GPR_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x64000)
+#ifdef CONFIG_MX6SLL
+#define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define PXP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x70000)
+#define EPDC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x74000)
+#define DCP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
+#elif defined(CONFIG_MX6SL)
+#define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#elif defined(CONFIG_MX6SX)
+#define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define CANFD2_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x70000)
+#define SEMAPHORE1_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x74000)
+#define SEMAPHORE2_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x78000)
+#define RDC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
+#else
+#define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#endif
+
+#define MX6SL_LCDIF_BASE_ADDR      (AIPS1_OFF_BASE_ADDR + 0x78000)
+#define MX6SLL_LCDIF_BASE_ADDR      (AIPS1_OFF_BASE_ADDR + 0x78000)
+
+#define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
+#define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
+#define AIPS3_ON_BASE_ADDR          (ATZ3_BASE_ADDR + 0x7C000)
+#define AIPS3_OFF_BASE_ADDR         (ATZ3_BASE_ADDR + 0x80000)
+#if defined(CONFIG_MX6UL)
+#define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR + 0x40000)
+#else
+#define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
+#endif
+#define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
+
+#define CONFIG_SYS_FSL_SEC_OFFSET   0
+#define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
+				     CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET   0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
+				     CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
+
+#define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
+
+#define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
+#ifdef CONFIG_MX6SL
+#define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
+#else
+#define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
+#endif
+
+#define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
+#define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
+#define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
+#define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
+#define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
+#define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
+#define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
+#define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
+#define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
+/* i.MX6SL/SLL */
+#define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
+#else
+/* i.MX6SX */
+#define ENET2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x34000)
+#endif
+/* i.MX6DQ/SDL */
+#define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
+
+#define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
+#define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
+#define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
+#ifdef CONFIG_MX6SLL
+#define IOMUXC_GPR_SNVS_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x44000)
+#define IOMUXC_SNVS_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x48000)
+#endif
+#define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
+#define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
+#define MX6UL_LCDIF1_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x48000)
+#define MX6ULL_LCDIF1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x48000)
+#ifdef CONFIG_MX6SX
+#define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
+#else
+#define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
+#endif
+#define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define SCTR_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
+#elif defined(CONFIG_MX6SX)
+#define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
+#define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
+#define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
+#else
+#define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
+#define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
+#endif
+#define MX6UL_WDOG3_BASE_ADDR       (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
+#define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
+#define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
+#define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
+#define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
+/* i.MX6SLL */
+#define MTR_MASTER_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x7C000)
+
+#ifdef CONFIG_MX6SX
+#define GIS_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x04000)
+#define DCIC1_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x0C000)
+#define DCIC2_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x10000)
+#define CSI1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x14000)
+#define PXP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x18000)
+#define CSI2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x1C000)
+#define VADC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x28000)
+#define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
+#define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
+#define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
+#define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
+#define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
+#define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
+#define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
+#define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
+#define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
+#define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
+#define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
+#define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
+#define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
+#define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
+#define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
+#define DCP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x80000)
+#define RNGB_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
+#define UART8_IPS_BASE_ADDR         (AIPS3_ARB_BASE_ADDR + 0x88000)
+#define EPDC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x8C000)
+#define IOMUXC_SNVS_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x90000)
+#define SNVS_GPR_BASE_ADDR          (AIPS3_ARB_BASE_ADDR + 0x94000)
+#endif
+
+#define NOC_DDR_BASE_ADDR           (GPV0_BASE_ADDR + 0xB0000)
+
+/* Only for i.MX6SX */
+#define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
+#define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)
+#define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
+
+#if !(defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+	defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
+#define IRAM_SIZE                    0x00040000
+#else
+#define IRAM_SIZE                    0x00020000
+#endif
+#define FEC_QUIRK_ENET_MAC
+
+#include <asm/mach-imx/regs-lcdif.h>
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* only for i.MX6SX/UL */
+#define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ?	\
+			 MX6UL_WDOG3_BASE_ADDR :  MX6SX_WDOG3_BASE_ADDR))
+#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ?	\
+			  MX6SLL_LCDIF_BASE_ADDR :		\
+			  (is_cpu_type(MXC_CPU_MX6SL)) ?	\
+			  MX6SL_LCDIF_BASE_ADDR :		\
+			  ((is_cpu_type(MXC_CPU_MX6UL)) ?	\
+			  MX6UL_LCDIF1_BASE_ADDR :		\
+			  ((is_mx6ull()) ?	\
+			  MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
+
+
+extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
+#define SRC_SCR_CORE_1_RESET_OFFSET     14
+#define SRC_SCR_CORE_1_RESET_MASK       (1<<SRC_SCR_CORE_1_RESET_OFFSET)
+#define SRC_SCR_CORE_2_RESET_OFFSET     15
+#define SRC_SCR_CORE_2_RESET_MASK       (1<<SRC_SCR_CORE_2_RESET_OFFSET)
+#define SRC_SCR_CORE_3_RESET_OFFSET     16
+#define SRC_SCR_CORE_3_RESET_MASK       (1<<SRC_SCR_CORE_3_RESET_OFFSET)
+#define SRC_SCR_CORE_1_ENABLE_OFFSET    22
+#define SRC_SCR_CORE_1_ENABLE_MASK      (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
+#define SRC_SCR_CORE_2_ENABLE_OFFSET    23
+#define SRC_SCR_CORE_2_ENABLE_MASK      (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
+#define SRC_SCR_CORE_3_ENABLE_OFFSET    24
+#define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
+
+struct rdc_regs {
+	u32	vir;		/* Version information */
+	u32	reserved1[8];
+	u32	stat;		/* Status */
+	u32	intctrl;	/* Interrupt and Control */
+	u32	intstat;	/* Interrupt Status */
+	u32	reserved2[116];
+	u32	mda[32];	/* Master Domain Assignment */
+	u32	reserved3[96];
+	u32	pdap[104];	/* Peripheral Domain Access Permissions */
+	u32	reserved4[88];
+	struct {
+		u32 mrsa;	/* Memory Region Start Address */
+		u32 mrea;	/* Memory Region End Address */
+		u32 mrc;	/* Memory Region Control */
+		u32 mrvs;	/* Memory Region Violation Status */
+	} mem_region[55];
+};
+
+struct rdc_sema_regs {
+	u8	gate[64];	/* Gate */
+	u16	rstgt;		/* Reset Gate */
+};
+
+/* WEIM registers */
+struct weim {
+	u32 cs0gcr1;
+	u32 cs0gcr2;
+	u32 cs0rcr1;
+	u32 cs0rcr2;
+	u32 cs0wcr1;
+	u32 cs0wcr2;
+
+	u32 cs1gcr1;
+	u32 cs1gcr2;
+	u32 cs1rcr1;
+	u32 cs1rcr2;
+	u32 cs1wcr1;
+	u32 cs1wcr2;
+
+	u32 cs2gcr1;
+	u32 cs2gcr2;
+	u32 cs2rcr1;
+	u32 cs2rcr2;
+	u32 cs2wcr1;
+	u32 cs2wcr2;
+
+	u32 cs3gcr1;
+	u32 cs3gcr2;
+	u32 cs3rcr1;
+	u32 cs3rcr2;
+	u32 cs3wcr1;
+	u32 cs3wcr2;
+
+	u32 unused[12];
+
+	u32 wcr;
+	u32 wiar;
+	u32 ear;
+};
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32	scr;
+	u32	sbmr1;
+	u32	srsr;
+	u32	reserved1[2];
+	u32	sisr;
+	u32	simr;
+	u32     sbmr2;
+	u32     gpr1;
+	u32     gpr2;
+	u32     gpr3;
+	u32     gpr4;
+	u32     gpr5;
+	u32     gpr6;
+	u32     gpr7;
+	u32     gpr8;
+	u32     gpr9;
+	u32     gpr10;
+};
+
+#define src_base ((struct src *)SRC_BASE_ADDR)
+
+#define SRC_M4_REG_OFFSET		0
+#define SRC_M4_ENABLE_OFFSET		22
+#define SRC_M4_ENABLE_MASK		BIT(22)
+#define SRC_M4C_NON_SCLR_RST_OFFSET	4
+#define SRC_M4C_NON_SCLR_RST_MASK	BIT(4)
+
+/* GPR1 bitfields */
+#define IOMUXC_GPR1_APP_CLK_REQ_N		BIT(30)
+#define IOMUXC_GPR1_PCIE_EXIT_L1		BIT(28)
+#define IOMUXC_GPR1_PCIE_RDY_L23		BIT(27)
+#define IOMUXC_GPR1_PCIE_ENTER_L1		BIT(26)
+#define IOMUXC_GPR1_MIPI_COLOR_SW		BIT(25)
+#define IOMUXC_GPR1_DPI_OFF			BIT(24)
+#define IOMUXC_GPR1_EXC_MON_SLVE		BIT(22)
+#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET		21
+#define IOMUXC_GPR1_ENET_CLK_SEL_MASK		(1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX		BIT(20)
+#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX		BIT(19)
+#define IOMUXC_GPR1_PCIE_TEST_PD			BIT(18)
+#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2		BIT(17)
+#define IOMUXC_GPR1_PCIE_REF_CLK_EN		BIT(16)
+#define IOMUXC_GPR1_USB_EXP_MODE			BIT(15)
+#define IOMUXC_GPR1_PCIE_INT			BIT(14)
+#define IOMUXC_GPR1_USB_OTG_ID_OFFSET		13
+#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK		(1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
+#define IOMUXC_GPR1_GINT				BIT(12)
+#define IOMUXC_GPR1_ADDRS3_MASK			(0x3 << 10)
+#define IOMUXC_GPR1_ADDRS3_32MB			(0x0 << 10)
+#define IOMUXC_GPR1_ADDRS3_64MB			(0x1 << 10)
+#define IOMUXC_GPR1_ADDRS3_128MB			(0x2 << 10)
+#define IOMUXC_GPR1_ACT_CS3			BIT(9)
+#define IOMUXC_GPR1_ADDRS2_MASK			(0x3 << 7)
+#define IOMUXC_GPR1_ACT_CS2			BIT(6)
+#define IOMUXC_GPR1_ADDRS1_MASK			(0x3 << 4)
+#define IOMUXC_GPR1_ACT_CS1			BIT(3)
+#define IOMUXC_GPR1_ADDRS0_OFFSET		(1)
+#define IOMUXC_GPR1_ADDRS0_MASK			(0x3 << 1)
+#define IOMUXC_GPR1_ACT_CS0			BIT(0)
+
+/* GPR3 bitfields */
+#define IOMUXC_GPR3_GPU_DBG_OFFSET		29
+#define IOMUXC_GPR3_GPU_DBG_MASK		(3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET	28
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET	27
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET	26
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET	25
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK	(1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_CTL_OFFSET		21
+#define IOMUXC_GPR3_OCRAM_CTL_MASK		(0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET		17
+#define IOMUXC_GPR3_OCRAM_STATUS_MASK		(0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET	16
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET	15
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET	14
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET	13
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK	(1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET	12
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET	11
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK	(1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_IPU_DIAG_OFFSET		10
+#define IOMUXC_GPR3_IPU_DIAG_MASK		(1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
+
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0	0
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1	1
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0	2
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1	3
+
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET	8
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET	6
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK		(3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET		4
+#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET		2
+#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK		(3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+
+/* gpr12 bitfields */
+#define IOMUXC_GPR12_ARMP_IPG_CLK_EN		BIT(27)
+#define IOMUXC_GPR12_ARMP_AHB_CLK_EN		BIT(26)
+#define IOMUXC_GPR12_ARMP_ATB_CLK_EN		BIT(25)
+#define IOMUXC_GPR12_ARMP_APB_CLK_EN		BIT(24)
+#define IOMUXC_GPR12_DEVICE_TYPE		(0xf << 12)
+#define IOMUXC_GPR12_PCIE_CTL_2			BIT(10)
+#define IOMUXC_GPR12_LOS_LEVEL			(0x1f << 4)
+
+struct iomuxc {
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+	u8 reserved[0x4000];
+#endif
+	u32 gpr[14];
+};
+
+struct gpc {
+	u32	cntr;
+	u32	pgr;
+	u32	imr1;
+	u32	imr2;
+	u32	imr3;
+	u32	imr4;
+	u32	isr1;
+	u32	isr2;
+	u32	isr3;
+	u32	isr4;
+};
+
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET		20
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK		(3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET		16
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK			(7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
+
+#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET			15
+#define IOMUXC_GPR2_BGREF_RRMODE_MASK			(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES		(1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES		(0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH	0
+#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW	1
+
+#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET		10
+#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET		9
+#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK		(1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH		(IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW		(IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_BITMAP_SPWG	0
+#define IOMUXC_GPR2_BITMAP_JEIDA	1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET		8
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18	0
+#define IOMUXC_GPR2_DATA_WIDTH_24	1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET		7
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET		6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK		(1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA		(IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG		(IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET		5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK			(1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT		(IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT		(IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET		4
+#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK			(1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED	0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0	1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1	3
+
+#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET		2
+#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+
+#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET		0
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK			(3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED		(IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+
+/* ECSPI registers */
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 cfg;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	32
+#define SPI_MAX_NUM	4
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN	18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA		0  /* SCLK phase control */
+#define MXC_CSPICON_POL		4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL	12 /* SS polarity */
+#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
+#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
+	defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#define MXC_SPI_BASE_ADDRESSES \
+	ECSPI1_BASE_ADDR, \
+	ECSPI2_BASE_ADDR, \
+	ECSPI3_BASE_ADDR, \
+	ECSPI4_BASE_ADDR
+#else
+#define MXC_SPI_BASE_ADDRESSES \
+	ECSPI1_BASE_ADDR, \
+	ECSPI2_BASE_ADDR, \
+	ECSPI3_BASE_ADDR, \
+	ECSPI4_BASE_ADDR, \
+	ECSPI5_BASE_ADDR
+#endif
+
+struct ocotp_regs {
+	u32	ctrl;
+	u32	ctrl_set;
+	u32     ctrl_clr;
+	u32	ctrl_tog;
+	u32	timing;
+	u32     rsvd0[3];
+	u32     data;
+	u32     rsvd1[3];
+	u32     read_ctrl;
+	u32     rsvd2[3];
+	u32	read_fuse_data;
+	u32     rsvd3[3];
+	u32	sw_sticky;
+	u32     rsvd4[3];
+	u32     scs;
+	u32     scs_set;
+	u32     scs_clr;
+	u32     scs_tog;
+	u32     crc_addr;
+	u32     rsvd5[3];
+	u32     crc_value;
+	u32     rsvd6[3];
+	u32     version;
+	u32     rsvd7[0xdb];
+
+	/* fuse banks */
+	struct fuse_bank {
+		u32	fuse_regs[0x20];
+	} bank[0];
+};
+
+struct fuse_bank0_regs {
+	u32	lock;
+	u32	rsvd0[3];
+	u32	uid_low;
+	u32	rsvd1[3];
+	u32	uid_high;
+	u32	rsvd2[3];
+	u32	cfg2;
+	u32	rsvd3[3];
+	u32	cfg3;
+	u32	rsvd4[3];
+	u32	cfg4;
+	u32	rsvd5[3];
+	u32	cfg5;
+	u32	rsvd6[3];
+	u32	cfg6;
+	u32	rsvd7[3];
+};
+
+struct fuse_bank1_regs {
+	u32	mem0;
+	u32	rsvd0[3];
+	u32	mem1;
+	u32	rsvd1[3];
+	u32	mem2;
+	u32	rsvd2[3];
+	u32	mem3;
+	u32	rsvd3[3];
+	u32	mem4;
+	u32	rsvd4[3];
+	u32	ana0;
+	u32	rsvd5[3];
+	u32	ana1;
+	u32	rsvd6[3];
+	u32	ana2;
+	u32	rsvd7[3];
+};
+
+struct fuse_bank4_regs {
+	u32 sjc_resp_low;
+	u32 rsvd0[3];
+	u32 sjc_resp_high;
+	u32 rsvd1[3];
+	u32 mac_addr0;
+	u32 rsvd2[3];
+	u32 mac_addr1;
+	u32 rsvd3[3];
+	u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
+	u32 rsvd4[7];
+	u32 gp1;
+	u32 rsvd5[3];
+	u32 gp2;
+	u32 rsvd6[3];
+};
+
+struct aipstz_regs {
+	u32	mprot0;
+	u32	mprot1;
+	u32	rsvd[0xe];
+	u32	opacr0;
+	u32	opacr1;
+	u32	opacr2;
+	u32	opacr3;
+	u32	opacr4;
+};
+
+struct anatop_regs {
+	u32	pll_sys;		/* 0x000 */
+	u32	pll_sys_set;		/* 0x004 */
+	u32	pll_sys_clr;		/* 0x008 */
+	u32	pll_sys_tog;		/* 0x00c */
+	u32	usb1_pll_480_ctrl;	/* 0x010 */
+	u32	usb1_pll_480_ctrl_set;	/* 0x014 */
+	u32	usb1_pll_480_ctrl_clr;	/* 0x018 */
+	u32	usb1_pll_480_ctrl_tog;	/* 0x01c */
+	u32	usb2_pll_480_ctrl;	/* 0x020 */
+	u32	usb2_pll_480_ctrl_set;	/* 0x024 */
+	u32	usb2_pll_480_ctrl_clr;	/* 0x028 */
+	u32	usb2_pll_480_ctrl_tog;	/* 0x02c */
+	u32	pll_528;		/* 0x030 */
+	u32	pll_528_set;		/* 0x034 */
+	u32	pll_528_clr;		/* 0x038 */
+	u32	pll_528_tog;		/* 0x03c */
+	u32	pll_528_ss;		/* 0x040 */
+	u32	rsvd0[3];
+	u32	pll_528_num;		/* 0x050 */
+	u32	rsvd1[3];
+	u32	pll_528_denom;		/* 0x060 */
+	u32	rsvd2[3];
+	u32	pll_audio;		/* 0x070 */
+	u32	pll_audio_set;		/* 0x074 */
+	u32	pll_audio_clr;		/* 0x078 */
+	u32	pll_audio_tog;		/* 0x07c */
+	u32	pll_audio_num;		/* 0x080 */
+	u32	rsvd3[3];
+	u32	pll_audio_denom;	/* 0x090 */
+	u32	rsvd4[3];
+	u32	pll_video;		/* 0x0a0 */
+	u32	pll_video_set;		/* 0x0a4 */
+	u32	pll_video_clr;		/* 0x0a8 */
+	u32	pll_video_tog;		/* 0x0ac */
+	u32	pll_video_num;		/* 0x0b0 */
+	u32	rsvd5[3];
+	u32	pll_video_denom;	/* 0x0c0 */
+	u32	rsvd6[3];
+	u32	pll_mlb;		/* 0x0d0 */
+	u32	pll_mlb_set;		/* 0x0d4 */
+	u32	pll_mlb_clr;		/* 0x0d8 */
+	u32	pll_mlb_tog;		/* 0x0dc */
+	u32	pll_enet;		/* 0x0e0 */
+	u32	pll_enet_set;		/* 0x0e4 */
+	u32	pll_enet_clr;		/* 0x0e8 */
+	u32	pll_enet_tog;		/* 0x0ec */
+	u32	pfd_480;		/* 0x0f0 */
+	u32	pfd_480_set;		/* 0x0f4 */
+	u32	pfd_480_clr;		/* 0x0f8 */
+	u32	pfd_480_tog;		/* 0x0fc */
+	u32	pfd_528;		/* 0x100 */
+	u32	pfd_528_set;		/* 0x104 */
+	u32	pfd_528_clr;		/* 0x108 */
+	u32	pfd_528_tog;		/* 0x10c */
+	u32	reg_1p1;		/* 0x110 */
+	u32	reg_1p1_set;		/* 0x114 */
+	u32	reg_1p1_clr;		/* 0x118 */
+	u32	reg_1p1_tog;		/* 0x11c */
+	u32	reg_3p0;		/* 0x120 */
+	u32	reg_3p0_set;		/* 0x124 */
+	u32	reg_3p0_clr;		/* 0x128 */
+	u32	reg_3p0_tog;		/* 0x12c */
+	u32	reg_2p5;		/* 0x130 */
+	u32	reg_2p5_set;		/* 0x134 */
+	u32	reg_2p5_clr;		/* 0x138 */
+	u32	reg_2p5_tog;		/* 0x13c */
+	u32	reg_core;		/* 0x140 */
+	u32	reg_core_set;		/* 0x144 */
+	u32	reg_core_clr;		/* 0x148 */
+	u32	reg_core_tog;		/* 0x14c */
+	u32	ana_misc0;		/* 0x150 */
+	u32	ana_misc0_set;		/* 0x154 */
+	u32	ana_misc0_clr;		/* 0x158 */
+	u32	ana_misc0_tog;		/* 0x15c */
+	u32	ana_misc1;		/* 0x160 */
+	u32	ana_misc1_set;		/* 0x164 */
+	u32	ana_misc1_clr;		/* 0x168 */
+	u32	ana_misc1_tog;		/* 0x16c */
+	u32	ana_misc2;		/* 0x170 */
+	u32	ana_misc2_set;		/* 0x174 */
+	u32	ana_misc2_clr;		/* 0x178 */
+	u32	ana_misc2_tog;		/* 0x17c */
+	u32	tempsense0;		/* 0x180 */
+	u32	tempsense0_set;		/* 0x184 */
+	u32	tempsense0_clr;		/* 0x188 */
+	u32	tempsense0_tog;		/* 0x18c */
+	u32	tempsense1;		/* 0x190 */
+	u32	tempsense1_set;		/* 0x194 */
+	u32	tempsense1_clr;		/* 0x198 */
+	u32	tempsense1_tog;		/* 0x19c */
+	u32	usb1_vbus_detect;	/* 0x1a0 */
+	u32	usb1_vbus_detect_set;	/* 0x1a4 */
+	u32	usb1_vbus_detect_clr;	/* 0x1a8 */
+	u32	usb1_vbus_detect_tog;	/* 0x1ac */
+	u32	usb1_chrg_detect;	/* 0x1b0 */
+	u32	usb1_chrg_detect_set;	/* 0x1b4 */
+	u32	usb1_chrg_detect_clr;	/* 0x1b8 */
+	u32	usb1_chrg_detect_tog;	/* 0x1bc */
+	u32	usb1_vbus_det_stat;	/* 0x1c0 */
+	u32	usb1_vbus_det_stat_set;	/* 0x1c4 */
+	u32	usb1_vbus_det_stat_clr;	/* 0x1c8 */
+	u32	usb1_vbus_det_stat_tog;	/* 0x1cc */
+	u32	usb1_chrg_det_stat;	/* 0x1d0 */
+	u32	usb1_chrg_det_stat_set;	/* 0x1d4 */
+	u32	usb1_chrg_det_stat_clr;	/* 0x1d8 */
+	u32	usb1_chrg_det_stat_tog;	/* 0x1dc */
+	u32	usb1_loopback;		/* 0x1e0 */
+	u32	usb1_loopback_set;	/* 0x1e4 */
+	u32	usb1_loopback_clr;	/* 0x1e8 */
+	u32	usb1_loopback_tog;	/* 0x1ec */
+	u32	usb1_misc;		/* 0x1f0 */
+	u32	usb1_misc_set;		/* 0x1f4 */
+	u32	usb1_misc_clr;		/* 0x1f8 */
+	u32	usb1_misc_tog;		/* 0x1fc */
+	u32	usb2_vbus_detect;	/* 0x200 */
+	u32	usb2_vbus_detect_set;	/* 0x204 */
+	u32	usb2_vbus_detect_clr;	/* 0x208 */
+	u32	usb2_vbus_detect_tog;	/* 0x20c */
+	u32	usb2_chrg_detect;	/* 0x210 */
+	u32	usb2_chrg_detect_set;	/* 0x214 */
+	u32	usb2_chrg_detect_clr;	/* 0x218 */
+	u32	usb2_chrg_detect_tog;	/* 0x21c */
+	u32	usb2_vbus_det_stat;	/* 0x220 */
+	u32	usb2_vbus_det_stat_set;	/* 0x224 */
+	u32	usb2_vbus_det_stat_clr;	/* 0x228 */
+	u32	usb2_vbus_det_stat_tog;	/* 0x22c */
+	u32	usb2_chrg_det_stat;	/* 0x230 */
+	u32	usb2_chrg_det_stat_set;	/* 0x234 */
+	u32	usb2_chrg_det_stat_clr;	/* 0x238 */
+	u32	usb2_chrg_det_stat_tog;	/* 0x23c */
+	u32	usb2_loopback;		/* 0x240 */
+	u32	usb2_loopback_set;	/* 0x244 */
+	u32	usb2_loopback_clr;	/* 0x248 */
+	u32	usb2_loopback_tog;	/* 0x24c */
+	u32	usb2_misc;		/* 0x250 */
+	u32	usb2_misc_set;		/* 0x254 */
+	u32	usb2_misc_clr;		/* 0x258 */
+	u32	usb2_misc_tog;		/* 0x25c */
+	u32	digprog;		/* 0x260 */
+	u32	reserved1[7];
+	u32	digprog_sololite;	/* 0x280 */
+};
+
+#define ANATOP_PFD_FRAC_SHIFT(n)	((n)*8)
+#define ANATOP_PFD_FRAC_MASK(n)	(0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
+#define ANATOP_PFD_STABLE_SHIFT(n)	(6+((n)*8))
+#define ANATOP_PFD_STABLE_MASK(n)	(1<<ANATOP_PFD_STABLE_SHIFT(n))
+#define ANATOP_PFD_CLKGATE_SHIFT(n)	(7+((n)*8))
+#define ANATOP_PFD_CLKGATE_MASK(n)	(1<<ANATOP_PFD_CLKGATE_SHIFT(n))
+
+struct wdog_regs {
+	u16	wcr;	/* Control */
+	u16	wsr;	/* Service */
+	u16	wrsr;	/* Reset Status */
+	u16	wicr;	/* Interrupt Control */
+	u16	wmcr;	/* Miscellaneous Control */
+};
+
+#define PWMCR_PRESCALER(x)	(((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN		(1 << 24)
+#define PWMCR_WAITEN		(1 << 23)
+#define PWMCR_DBGEN		(1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
+#define PWMCR_CLKSRC_IPG	(1 << 16)
+#define PWMCR_EN		(1 << 0)
+
+struct pwm_regs {
+	u32	cr;
+	u32	sr;
+	u32	ir;
+	u32	sar;
+	u32	pr;
+	u32	cnr;
+};
+
+/*
+ * If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
+ * If boot from the other mode, USB0_PWD will keep reset value
+ */
+#define	is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
+
+#endif /* __ASSEMBLER__*/
+#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
new file mode 100644
index 0000000..bea0bbb
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASM_ARCH_IOMUX_H__
+#define __ASM_ARCH_IOMUX_H__
+
+#define MX6_IOMUXC_GPR4		0x020e0010
+#define MX6_IOMUXC_GPR6		0x020e0018
+#define MX6_IOMUXC_GPR7		0x020e001c
+
+/*
+ * IOMUXC_GPR1 bit fields
+ */
+#define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR	(0<<13)
+#define IOMUXC_GPR1_OTG_ID_GPIO1	(1<<13)
+#define IOMUXC_GPR1_OTG_ID_MASK		(1<<13)
+#define IOMUXC_GPR1_REF_SSP_EN			(1 << 16)
+#define IOMUXC_GPR1_TEST_POWERDOWN		(1 << 18)
+
+#define IOMUXC_GPR1_PCIE_SW_RST		(1 << 29)
+
+/*
+ * IOMUXC_GPR5 bit fields
+ */
+#define IOMUXC_GPR5_PCIE_BTNRST			(1 << 19)
+#define IOMUXC_GPR5_PCIE_PERST			(1 << 18)
+
+/*
+ * IOMUXC_GPR8 bit fields
+ */
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK		(0x3f << 0)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET		0
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK	(0x3f << 6)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET	6
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK		(0x3f << 12)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET	12
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK		(0x7f << 18)
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET		18
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK		(0x7f << 25)
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET		25
+
+/*
+ * IOMUXC_GPR12 bit fields
+ */
+#define IOMUXC_GPR12_RX_EQ_2			(0x2 << 0)
+#define IOMUXC_GPR12_RX_EQ_MASK			(0x7 << 0)
+#define IOMUXC_GPR12_LOS_LEVEL_9		(0x9 << 4)
+#define IOMUXC_GPR12_LOS_LEVEL_MASK		(0x1f << 4)
+#define IOMUXC_GPR12_APPS_LTSSM_ENABLE		(1 << 10)
+#define IOMUXC_GPR12_DEVICE_TYPE_EP		(0x0 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC		(0x4 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_MASK		(0xf << 12)
+#define IOMUXC_GPR12_TEST_POWERDOWN		(1 << 30)
+
+/*
+ * IOMUXC_GPR13 bit fields
+ */
+#define IOMUXC_GPR13_SDMA_STOP_REQ	(1<<30)
+#define IOMUXC_GPR13_CAN2_STOP_REQ	(1<<29)
+#define IOMUXC_GPR13_CAN1_STOP_REQ	(1<<28)
+#define IOMUXC_GPR13_ENET_STOP_REQ	(1<<27)
+#define IOMUXC_GPR13_SATA_PHY_8_MASK	(7<<24)
+#define IOMUXC_GPR13_SATA_PHY_7_MASK	(0x1f<<19)
+#define IOMUXC_GPR13_SATA_PHY_6_SHIFT	16
+#define IOMUXC_GPR13_SATA_PHY_6_MASK	(7<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+#define IOMUXC_GPR13_SATA_SPEED_MASK	(1<<15)
+#define IOMUXC_GPR13_SATA_PHY_5_MASK	(1<<14)
+#define IOMUXC_GPR13_SATA_PHY_4_MASK	(7<<11)
+#define IOMUXC_GPR13_SATA_PHY_3_MASK	(0x1f<<7)
+#define IOMUXC_GPR13_SATA_PHY_2_MASK	(0x1f<<2)
+#define IOMUXC_GPR13_SATA_PHY_1_MASK	(3<<0)
+
+#define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
+#define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+#define IOMUX_GPR1_FEC_MASK    (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \
+				| IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK)
+
+#define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17)
+#define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13)
+#define IOMUX_GPR1_FEC1_MASK	(IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \
+				| IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK)
+
+#define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18)
+#define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+#define IOMUX_GPR1_FEC2_MASK	(IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \
+				| IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK)
+
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB	(0<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB	(1<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB	(2<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB	(3<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB	(4<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB	(5<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB	(6<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB	(7<<24)
+
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1I	(0x10<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1M	(0x10<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1X	(0x1A<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2I	(0x12<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2M	(0x12<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2X	(0x1A<<19)
+
+#define IOMUXC_GPR13_SATA_SPEED_1P5G	(0<<15)
+#define IOMUXC_GPR13_SATA_SPEED_3G	(1<<15)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED	(0<<14)
+#define IOMUXC_GPR13_SATA_SATA_PHY_5_SS_ENABLED		(1<<14)
+
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_16_16	(0<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_14_16	(1<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16	(2<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_10_16	(3<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16		(4<<11)
+#define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16		(5<<11)
+
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB	(0<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB	(1<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB	(2<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB	(3<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB	(4<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB	(5<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB	(6<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB	(7<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB	(8<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB	(9<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB	(0xA<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB	(0xB<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB	(0xC<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB	(0xD<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB	(0xE<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB	(0xF<<7)
+
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V	(0<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V	(1<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V	(2<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V	(3<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V	(4<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V	(5<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V	(6<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V	(7<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V	(8<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V	(9<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V	(0xA<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V	(0xB<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V	(0xC<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V	(0xD<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V	(0xE<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V	(0xF<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V	(0x10<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V	(0x11<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V	(0x12<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V	(0x13<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V	(0x14<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V	(0x15<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V	(0x16<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V	(0x17<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V	(0x18<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V	(0x19<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V	(0x1A<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V	(0x1B<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V	(0x1C<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V	(0x1D<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V	(0x1E<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V	(0x1F<<2)
+
+#define IOMUXC_GPR13_SATA_PHY_1_FAST	0
+#define IOMUXC_GPR13_SATA_PHY_1_MEDIUM	1
+#define IOMUXC_GPR13_SATA_PHY_1_SLOW	2
+
+#define IOMUXC_GPR13_SATA_MASK (IOMUXC_GPR13_SATA_PHY_8_MASK \
+				|IOMUXC_GPR13_SATA_PHY_7_MASK \
+				|IOMUXC_GPR13_SATA_PHY_6_MASK \
+				|IOMUXC_GPR13_SATA_SPEED_MASK \
+				|IOMUXC_GPR13_SATA_PHY_5_MASK \
+				|IOMUXC_GPR13_SATA_PHY_4_MASK \
+				|IOMUXC_GPR13_SATA_PHY_3_MASK \
+				|IOMUXC_GPR13_SATA_PHY_2_MASK \
+				|IOMUXC_GPR13_SATA_PHY_1_MASK)
+
+/*
+ * Setup RGMII voltage levels on iMX6 SoC - the
+ *
+ * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - register
+ *
+ * 1P2V_IO - USB_HSIC, MIPI_HSI
+ * 1P5V_IO - ENET pins
+ */
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII	0x020e0790
+#define DDR_SEL_1P2V_IO (0x2 << 18)
+#define DDR_SEL_1P5V_IO (0x3 << 18)
+
+#endif	/* __ASM_ARCH_IOMUX_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/litesom.h b/arch/arm/include/asm/arch-mx6/litesom.h
new file mode 100644
index 0000000..fcdfcab
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/litesom.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Grinn
+ */
+
+#ifndef __ARCH_ARM_MX6UL_LITESOM_H__
+#define __ARCH_ARM_MX6UL_LITESOM_H__
+
+int litesom_mmc_init(bd_t *bis);
+
+#ifdef CONFIG_SPL_BUILD
+void litesom_init_f(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
new file mode 100644
index 0000000..e0fadb9
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -0,0 +1,530 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ */
+#ifndef __ASM_ARCH_MX6_DDR_H__
+#define __ASM_ARCH_MX6_DDR_H__
+
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_MX6Q
+#include "mx6q-ddr.h"
+#else
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#include "mx6dl-ddr.h"
+#else
+#ifdef CONFIG_MX6SX
+#include "mx6sx-ddr.h"
+#else
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#include "mx6ul-ddr.h"
+#else
+#ifdef CONFIG_MX6SL
+#include "mx6sl-ddr.h"
+#else
+#error "Please select cpu"
+#endif	/* CONFIG_MX6SL */
+#endif	/* CONFIG_MX6UL */
+#endif	/* CONFIG_MX6SX */
+#endif	/* CONFIG_MX6DL or CONFIG_MX6S */
+#endif	/* CONFIG_MX6Q */
+#else
+
+enum {
+	DDR_TYPE_DDR3,
+	DDR_TYPE_LPDDR2,
+};
+
+/* MMDC P0/P1 Registers */
+struct mmdc_p_regs {
+	u32 mdctl;
+	u32 mdpdc;
+	u32 mdotc;
+	u32 mdcfg0;
+	u32 mdcfg1;
+	u32 mdcfg2;
+	u32 mdmisc;
+	u32 mdscr;
+	u32 mdref;
+	u32 res1[2];
+	u32 mdrwd;
+	u32 mdor;
+	u32 mdmrr;
+	u32 mdcfg3lp;
+	u32 mdmr4;
+	u32 mdasp;
+	u32 res2[239];
+	u32 maarcr;
+	u32 mapsr;
+	u32 maexidr0;
+	u32 maexidr1;
+	u32 madpcr0;
+	u32 madpcr1;
+	u32 madpsr0;
+	u32 madpsr1;
+	u32 madpsr2;
+	u32 madpsr3;
+	u32 madpsr4;
+	u32 madpsr5;
+	u32 masbs0;
+	u32 masbs1;
+	u32 res3[2];
+	u32 magenp;
+	u32 res4[239];
+	u32 mpzqhwctrl;
+	u32 mpzqswctrl;
+	u32 mpwlgcr;
+	u32 mpwldectrl0;
+	u32 mpwldectrl1;
+	u32 mpwldlst;
+	u32 mpodtctrl;
+	u32 mprddqby0dl;
+	u32 mprddqby1dl;
+	u32 mprddqby2dl;
+	u32 mprddqby3dl;
+	u32 mpwrdqby0dl;
+	u32 mpwrdqby1dl;
+	u32 mpwrdqby2dl;
+	u32 mpwrdqby3dl;
+	u32 mpdgctrl0;
+	u32 mpdgctrl1;
+	u32 mpdgdlst0;
+	u32 mprddlctl;
+	u32 mprddlst;
+	u32 mpwrdlctl;
+	u32 mpwrdlst;
+	u32 mpsdctrl;
+	u32 mpzqlp2ctl;
+	u32 mprddlhwctl;
+	u32 mpwrdlhwctl;
+	u32 mprddlhwst0;
+	u32 mprddlhwst1;
+	u32 mpwrdlhwst0;
+	u32 mpwrdlhwst1;
+	u32 mpwlhwerr;
+	u32 mpdghwst0;
+	u32 mpdghwst1;
+	u32 mpdghwst2;
+	u32 mpdghwst3;
+	u32 mppdcmpr1;
+	u32 mppdcmpr2;
+	u32 mpswdar0;
+	u32 mpswdrdr0;
+	u32 mpswdrdr1;
+	u32 mpswdrdr2;
+	u32 mpswdrdr3;
+	u32 mpswdrdr4;
+	u32 mpswdrdr5;
+	u32 mpswdrdr6;
+	u32 mpswdrdr7;
+	u32 mpmur0;
+	u32 mpwrcadl;
+	u32 mpdccr;
+};
+
+#define MX6SL_IOM_DDR_BASE     0x020e0300
+struct mx6sl_iomux_ddr_regs {
+	u32 dram_cas;
+	u32 dram_cs0_b;
+	u32 dram_cs1_b;
+	u32 dram_dqm0;
+	u32 dram_dqm1;
+	u32 dram_dqm2;
+	u32 dram_dqm3;
+	u32 dram_ras;
+	u32 dram_reset;
+	u32 dram_sdba0;
+	u32 dram_sdba1;
+	u32 dram_sdba2;
+	u32 dram_sdcke0;
+	u32 dram_sdcke1;
+	u32 dram_sdclk_0;
+	u32 dram_odt0;
+	u32 dram_odt1;
+	u32 dram_sdqs0;
+	u32 dram_sdqs1;
+	u32 dram_sdqs2;
+	u32 dram_sdqs3;
+	u32 dram_sdwe_b;
+};
+
+#define MX6SL_IOM_GRP_BASE     0x020e0500
+struct mx6sl_iomux_grp_regs {
+	u32 res1[43];
+	u32 grp_addds;
+	u32 grp_ddrmode_ctl;
+	u32 grp_ddrpke;
+	u32 grp_ddrpk;
+	u32 grp_ddrhys;
+	u32 grp_ddrmode;
+	u32 grp_b0ds;
+	u32 grp_ctlds;
+	u32 grp_b1ds;
+	u32 grp_ddr_type;
+	u32 grp_b2ds;
+	u32 grp_b3ds;
+};
+
+#define MX6UL_IOM_DDR_BASE	0x020e0200
+struct mx6ul_iomux_ddr_regs {
+	u32 res1[17];
+	u32 dram_dqm0;
+	u32 dram_dqm1;
+	u32 dram_ras;
+	u32 dram_cas;
+	u32 dram_cs0;
+	u32 dram_cs1;
+	u32 dram_sdwe_b;
+	u32 dram_odt0;
+	u32 dram_odt1;
+	u32 dram_sdba0;
+	u32 dram_sdba1;
+	u32 dram_sdba2;
+	u32 dram_sdcke0;
+	u32 dram_sdcke1;
+	u32 dram_sdclk_0;
+	u32 dram_sdqs0;
+	u32 dram_sdqs1;
+	u32 dram_reset;
+};
+
+#define MX6UL_IOM_GRP_BASE	0x020e0400
+struct mx6ul_iomux_grp_regs {
+	u32 res1[36];
+	u32 grp_addds;
+	u32 grp_ddrmode_ctl;
+	u32 grp_b0ds;
+	u32 grp_ddrpk;
+	u32 grp_ctlds;
+	u32 grp_b1ds;
+	u32 grp_ddrhys;
+	u32 grp_ddrpke;
+	u32 grp_ddrmode;
+	u32 grp_ddr_type;
+};
+
+#define MX6SX_IOM_DDR_BASE	0x020e0200
+struct mx6sx_iomux_ddr_regs {
+	u32 res1[59];
+	u32 dram_dqm0;
+	u32 dram_dqm1;
+	u32 dram_dqm2;
+	u32 dram_dqm3;
+	u32 dram_ras;
+	u32 dram_cas;
+	u32 res2[2];
+	u32 dram_sdwe_b;
+	u32 dram_odt0;
+	u32 dram_odt1;
+	u32 dram_sdba0;
+	u32 dram_sdba1;
+	u32 dram_sdba2;
+	u32 dram_sdcke0;
+	u32 dram_sdcke1;
+	u32 dram_sdclk_0;
+	u32 dram_sdqs0;
+	u32 dram_sdqs1;
+	u32 dram_sdqs2;
+	u32 dram_sdqs3;
+	u32 dram_reset;
+};
+
+#define MX6SX_IOM_GRP_BASE	0x020e0500
+struct mx6sx_iomux_grp_regs {
+	u32 res1[61];
+	u32 grp_addds;
+	u32 grp_ddrmode_ctl;
+	u32 grp_ddrpke;
+	u32 grp_ddrpk;
+	u32 grp_ddrhys;
+	u32 grp_ddrmode;
+	u32 grp_b0ds;
+	u32 grp_b1ds;
+	u32 grp_ctlds;
+	u32 grp_ddr_type;
+	u32 grp_b2ds;
+	u32 grp_b3ds;
+};
+
+/*
+ * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
+ */
+#define MX6DQ_IOM_DDR_BASE      0x020e0500
+struct mx6dq_iomux_ddr_regs {
+	u32 res1[3];
+	u32 dram_sdqs5;
+	u32 dram_dqm5;
+	u32 dram_dqm4;
+	u32 dram_sdqs4;
+	u32 dram_sdqs3;
+	u32 dram_dqm3;
+	u32 dram_sdqs2;
+	u32 dram_dqm2;
+	u32 res2[16];
+	u32 dram_cas;
+	u32 res3[2];
+	u32 dram_ras;
+	u32 dram_reset;
+	u32 res4[2];
+	u32 dram_sdclk_0;
+	u32 dram_sdba2;
+	u32 dram_sdcke0;
+	u32 dram_sdclk_1;
+	u32 dram_sdcke1;
+	u32 dram_sdodt0;
+	u32 dram_sdodt1;
+	u32 res5;
+	u32 dram_sdqs0;
+	u32 dram_dqm0;
+	u32 dram_sdqs1;
+	u32 dram_dqm1;
+	u32 dram_sdqs6;
+	u32 dram_dqm6;
+	u32 dram_sdqs7;
+	u32 dram_dqm7;
+};
+
+#define MX6DQ_IOM_GRP_BASE      0x020e0700
+struct mx6dq_iomux_grp_regs {
+	u32 res1[18];
+	u32 grp_b7ds;
+	u32 grp_addds;
+	u32 grp_ddrmode_ctl;
+	u32 res2;
+	u32 grp_ddrpke;
+	u32 res3[6];
+	u32 grp_ddrmode;
+	u32 res4[3];
+	u32 grp_b0ds;
+	u32 grp_b1ds;
+	u32 grp_ctlds;
+	u32 res5;
+	u32 grp_b2ds;
+	u32 grp_ddr_type;
+	u32 grp_b3ds;
+	u32 grp_b4ds;
+	u32 grp_b5ds;
+	u32 grp_b6ds;
+};
+
+#define MX6SDL_IOM_DDR_BASE     0x020e0400
+struct mx6sdl_iomux_ddr_regs {
+	u32 res1[25];
+	u32 dram_cas;
+	u32 res2[2];
+	u32 dram_dqm0;
+	u32 dram_dqm1;
+	u32 dram_dqm2;
+	u32 dram_dqm3;
+	u32 dram_dqm4;
+	u32 dram_dqm5;
+	u32 dram_dqm6;
+	u32 dram_dqm7;
+	u32 dram_ras;
+	u32 dram_reset;
+	u32 res3[2];
+	u32 dram_sdba2;
+	u32 dram_sdcke0;
+	u32 dram_sdcke1;
+	u32 dram_sdclk_0;
+	u32 dram_sdclk_1;
+	u32 dram_sdodt0;
+	u32 dram_sdodt1;
+	u32 dram_sdqs0;
+	u32 dram_sdqs1;
+	u32 dram_sdqs2;
+	u32 dram_sdqs3;
+	u32 dram_sdqs4;
+	u32 dram_sdqs5;
+	u32 dram_sdqs6;
+	u32 dram_sdqs7;
+};
+
+#define MX6SDL_IOM_GRP_BASE     0x020e0700
+struct mx6sdl_iomux_grp_regs {
+	u32 res1[18];
+	u32 grp_b7ds;
+	u32 grp_addds;
+	u32 grp_ddrmode_ctl;
+	u32 grp_ddrpke;
+	u32 res2[2];
+	u32 grp_ddrmode;
+	u32 grp_b0ds;
+	u32 res3;
+	u32 grp_ctlds;
+	u32 grp_b1ds;
+	u32 grp_ddr_type;
+	u32 grp_b2ds;
+	u32 grp_b3ds;
+	u32 grp_b4ds;
+	u32 grp_b5ds;
+	u32 res4;
+	u32 grp_b6ds;
+};
+
+/* Device Information: Varies per DDR3 part number and speed grade */
+struct mx6_ddr3_cfg {
+	u16 mem_speed;	/* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
+	u8 density;	/* chip density (Gb) (1,2,4,8) */
+	u8 width;	/* bus width (bits) (4,8,16) */
+	u8 banks;	/* number of banks */
+	u8 rowaddr;	/* row address bits (11-16)*/
+	u8 coladdr;	/* col address bits (9-12) */
+	u8 pagesz;	/* page size (K) (1-2) */
+	u16 trcd;	/* tRCD=tRP=CL (ns*100) */
+	u16 trcmin;	/* tRC min (ns*100) */
+	u16 trasmin;	/* tRAS min (ns*100) */
+	u8 SRT;		/* self-refresh temperature: 0=normal, 1=extended */
+};
+
+/* Device Information: Varies per LPDDR2 part number and speed grade */
+struct mx6_lpddr2_cfg {
+	u16 mem_speed;	/* ie 800 for LPDDR2-800 */
+	u8 density;	/* chip density (Gb) (1,2,4,8) */
+	u8 width;	/* bus width (bits) (4,8,16) */
+	u8 banks;	/* number of banks */
+	u8 rowaddr;	/* row address bits (11-16)*/
+	u8 coladdr;	/* col address bits (9-12) */
+	u16 trcd_lp;
+	u16 trppb_lp;
+	u16 trpab_lp;
+	u16 trcmin;	/* tRC min (ns*100) */
+	u16 trasmin;	/* tRAS min (ns*100) */
+};
+
+/* System Information: Varies per board design, layout, and term choices */
+struct mx6_ddr_sysinfo {
+	u8 dsize;	/* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
+	u8 cs_density;	/* density per chip select (Gb) */
+	u8 ncs;		/* number chip selects used (1|2) */
+	char cs1_mirror;/* enable address mirror (0|1) */
+	char bi_on;	/* Bank interleaving enable */
+	u8 rtt_nom;	/* Rtt_Nom (DDR3_RTT_*) */
+	u8 rtt_wr;	/* Rtt_Wr (DDR3_RTT_*) */
+	u8 ralat;	/* Read Additional Latency (0-7) */
+	u8 walat;	/* Write Additional Latency (0-3) */
+	u8 mif3_mode;	/* Command prediction working mode */
+	u8 rst_to_cke;	/* Time from SDE enable to CKE rise */
+	u8 sde_to_rst;	/* Time from SDE enable until DDR reset# is high */
+	u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
+	u8 ddr_type;	/* DDR type: DDR3(0) or LPDDR2(1) */
+	u8 refsel;	/* REF_SEL field of register MDREF */
+	u8 refr;	/* REFR field of register MDREF */
+};
+
+/*
+ * Board specific calibration:
+ *   This includes write leveling calibration values as well as DQS gating
+ *   and read/write delays. These values are board/layout/device specific.
+ *   Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
+ *   (DOC-96412) to determine these values over a range of boards and
+ *   temperatures.
+ */
+struct mx6_mmdc_calibration {
+	/* write leveling calibration */
+	u32 p0_mpwldectrl0;
+	u32 p0_mpwldectrl1;
+	u32 p1_mpwldectrl0;
+	u32 p1_mpwldectrl1;
+	/* read DQS gating */
+	u32 p0_mpdgctrl0;
+	u32 p0_mpdgctrl1;
+	u32 p1_mpdgctrl0;
+	u32 p1_mpdgctrl1;
+	/* read delay */
+	u32 p0_mprddlctl;
+	u32 p1_mprddlctl;
+	/* write delay */
+	u32 p0_mpwrdlctl;
+	u32 p1_mpwrdlctl;
+	/* lpddr2 zq hw calibration */
+	u32 mpzqlp2ctl;
+};
+
+/* configure iomux (pinctl/padctl) */
+void mx6dq_dram_iocfg(unsigned width,
+		      const struct mx6dq_iomux_ddr_regs *,
+		      const struct mx6dq_iomux_grp_regs *);
+void mx6sdl_dram_iocfg(unsigned width,
+		       const struct mx6sdl_iomux_ddr_regs *,
+		       const struct mx6sdl_iomux_grp_regs *);
+void mx6sx_dram_iocfg(unsigned width,
+		      const struct mx6sx_iomux_ddr_regs *,
+		      const struct mx6sx_iomux_grp_regs *);
+void mx6ul_dram_iocfg(unsigned width,
+		      const struct mx6ul_iomux_ddr_regs *,
+		      const struct mx6ul_iomux_grp_regs *);
+void mx6sl_dram_iocfg(unsigned width,
+		      const struct mx6sl_iomux_ddr_regs *,
+		      const struct mx6sl_iomux_grp_regs *);
+
+#if defined(CONFIG_MX6_DDRCAL)
+int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+                           struct mx6_mmdc_calibration *calib);
+#endif
+
+/* configure mx6 mmdc registers */
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
+		  const struct mx6_mmdc_calibration *,
+		  const void *);
+
+#endif /* CONFIG_SPL_BUILD */
+
+#define MX6_MMDC_P0_MDCTL	0x021b0000
+#define MX6_MMDC_P0_MDPDC	0x021b0004
+#define MX6_MMDC_P0_MDOTC	0x021b0008
+#define MX6_MMDC_P0_MDCFG0	0x021b000c
+#define MX6_MMDC_P0_MDCFG1	0x021b0010
+#define MX6_MMDC_P0_MDCFG2	0x021b0014
+#define MX6_MMDC_P0_MDMISC	0x021b0018
+#define MX6_MMDC_P0_MDSCR	0x021b001c
+#define MX6_MMDC_P0_MDREF	0x021b0020
+#define MX6_MMDC_P0_MDRWD	0x021b002c
+#define MX6_MMDC_P0_MDOR	0x021b0030
+#define MX6_MMDC_P0_MDASP	0x021b0040
+#define MX6_MMDC_P0_MAPSR	0x021b0404
+#define MX6_MMDC_P0_MPZQHWCTRL	0x021b0800
+#define MX6_MMDC_P0_MPWLDECTRL0	0x021b080c
+#define MX6_MMDC_P0_MPWLDECTRL1	0x021b0810
+#define MX6_MMDC_P0_MPODTCTRL	0x021b0818
+#define MX6_MMDC_P0_MPRDDQBY0DL	0x021b081c
+#define MX6_MMDC_P0_MPRDDQBY1DL	0x021b0820
+#define MX6_MMDC_P0_MPRDDQBY2DL	0x021b0824
+#define MX6_MMDC_P0_MPRDDQBY3DL	0x021b0828
+#define MX6_MMDC_P0_MPDGCTRL0	0x021b083c
+#define MX6_MMDC_P0_MPDGCTRL1	0x021b0840
+#define MX6_MMDC_P0_MPRDDLCTL	0x021b0848
+#define MX6_MMDC_P0_MPWRDLCTL	0x021b0850
+#define MX6_MMDC_P0_MPZQLP2CTL	0x021b085C
+#define MX6_MMDC_P0_MPMUR0	0x021b08b8
+
+#define MX6_MMDC_P1_MDCTL	0x021b4000
+#define MX6_MMDC_P1_MDPDC	0x021b4004
+#define MX6_MMDC_P1_MDOTC	0x021b4008
+#define MX6_MMDC_P1_MDCFG0	0x021b400c
+#define MX6_MMDC_P1_MDCFG1	0x021b4010
+#define MX6_MMDC_P1_MDCFG2	0x021b4014
+#define MX6_MMDC_P1_MDMISC	0x021b4018
+#define MX6_MMDC_P1_MDSCR	0x021b401c
+#define MX6_MMDC_P1_MDREF	0x021b4020
+#define MX6_MMDC_P1_MDRWD	0x021b402c
+#define MX6_MMDC_P1_MDOR	0x021b4030
+#define MX6_MMDC_P1_MDASP	0x021b4040
+#define MX6_MMDC_P1_MAPSR	0x021b4404
+#define MX6_MMDC_P1_MPZQHWCTRL	0x021b4800
+#define MX6_MMDC_P1_MPWLDECTRL0	0x021b480c
+#define MX6_MMDC_P1_MPWLDECTRL1	0x021b4810
+#define MX6_MMDC_P1_MPODTCTRL	0x021b4818
+#define MX6_MMDC_P1_MPRDDQBY0DL	0x021b481c
+#define MX6_MMDC_P1_MPRDDQBY1DL	0x021b4820
+#define MX6_MMDC_P1_MPRDDQBY2DL	0x021b4824
+#define MX6_MMDC_P1_MPRDDQBY3DL	0x021b4828
+#define MX6_MMDC_P1_MPDGCTRL0	0x021b483c
+#define MX6_MMDC_P1_MPDGCTRL1	0x021b4840
+#define MX6_MMDC_P1_MPRDDLCTL	0x021b4848
+#define MX6_MMDC_P1_MPWRDLCTL	0x021b4850
+#define MX6_MMDC_P1_MPZQLP2CTL	0x021b485C
+#define MX6_MMDC_P1_MPMUR0	0x021b48b8
+
+#endif	/*__ASM_ARCH_MX6_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
new file mode 100644
index 0000000..9a99a6b
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ */
+#ifndef __ASM_ARCH_MX6_PINS_H__
+#define __ASM_ARCH_MX6_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
+	prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
+
+#ifdef CONFIG_MX6QDL
+enum {
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc),
+#include "mx6q_pins.h"
+#undef MX6_PAD_DECL
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
+#include "mx6dl_pins.h"
+};
+#elif defined(CONFIG_MX6Q)
+enum {
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
+#include "mx6q_pins.h"
+};
+#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+enum {
+#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
+	MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
+#include "mx6dl_pins.h"
+};
+#elif defined(CONFIG_MX6SLL)
+#include "mx6sll_pins.h"
+#elif defined(CONFIG_MX6SL)
+#include "mx6sl_pins.h"
+#elif defined(CONFIG_MX6SX)
+#include "mx6sx_pins.h"
+#elif defined(CONFIG_MX6ULL)
+#include "mx6ull_pins.h"
+#elif defined(CONFIG_MX6UL)
+#include "mx6ul_pins.h"
+#else
+#error "Please select cpu"
+#endif	/* CONFIG_MX6Q */
+
+#endif	/*__ASM_ARCH_MX6_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6_plugin.S b/arch/arm/include/asm/arch-mx6/mx6_plugin.S
new file mode 100644
index 0000000..7e61d22
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6_plugin.S
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_ROM_UNIFIED_SECTIONS
+#define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
+#define ROM_VERSION_OFFSET               	0x80
+#else
+#define ROM_API_TABLE_BASE_ADDR_LEGACY		0xC0
+#define ROM_VERSION_OFFSET               	0x48
+#endif
+#define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15	0xC4
+#define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12	0xC4
+#define ROM_API_HWCNFG_SETUP_OFFSET		0x08
+#define ROM_VERSION_TO10			0x10
+#define ROM_VERSION_TO12			0x12
+#define ROM_VERSION_TO15			0x15
+
+plugin_start:
+
+	push    {r0-r4, lr}
+
+	imx6_ddr_setting
+	imx6_clock_gating
+	imx6_qos_setting
+
+/*
+ * The following is to fill in those arguments for this ROM function
+ * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+ * This function is used to copy data from the storage media into DDR.
+ * start - Initial (possibly partial) image load address on entry.
+ *         Final image load address on exit.
+ * bytes - Initial (possibly partial) image size on entry.
+ *         Final image size on exit.
+ * boot_data - Initial @ref ivt Boot Data load address.
+ */
+	adr r0, boot_data2
+	adr r1, image_len2
+	adr r2, boot_data2
+
+#ifdef CONFIG_NOR_BOOT
+#ifdef CONFIG_MX6SX
+	ldr r3, =ROM_VERSION_OFFSET
+	ldr r4, [r3]
+	cmp r4, #ROM_VERSION_TO10
+	bgt before_calling_rom___pu_irom_hwcnfg_setup
+	ldr r3, =0x00900b00
+	ldr r4, =0x50000000
+	str r4, [r3, #0x5c]
+#else
+	ldr r3, =0x00900800
+	ldr r4, =0x08000000
+	str r4, [r3, #0xc0]
+#endif
+#endif
+
+/*
+ * check the _pu_irom_api_table for the address
+ */
+before_calling_rom___pu_irom_hwcnfg_setup:
+	ldr r3, =ROM_VERSION_OFFSET
+	ldr r4, [r3]
+#if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL)
+	ldr r3, =ROM_VERSION_TO12
+	cmp r4, r3
+	ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12
+	ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
+#elif defined(CONFIG_MX6Q)
+	ldr r3, =ROM_VERSION_TO15
+	cmp r4, r3
+	ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15
+	ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
+#else
+	ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
+#endif
+	ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
+	blx r4
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+/*
+ * ROM_API_HWCNFG_SETUP function enables MMU & Caches.
+ * Thus disable MMU & Caches.
+ */
+
+	mrc     p15, 0, r0, c1, c0, 0   /* read CP15 register 1 into r0*/
+	ands    r0, r0, #0x1            /* check if MMU is enabled */
+	beq     mmu_disable_notreq      /* exit if MMU is already disabled */
+
+	/* Disable caches, MMU */
+	mrc     p15, 0, r0, c1, c0, 0	/* read CP15 register 1 into r0 */
+	bic     r0, r0, #(1 << 2)	/* disable D Cache */
+	bic     r0, r0, #0x1		/* clear bit 0 ; MMU off */
+
+	bic     r0, r0, #(0x1 << 11)	/* disable Z, branch prediction */
+	bic     r0, r0, #(0x1 << 1)	/* disable A, Strict alignment */
+					/* check enabled. */
+	mcr     p15, 0, r0, c1, c0, 0	/* write CP15 register 1 */
+	mov     r0, r0
+	mov     r0, r0
+	mov     r0, r0
+	mov     r0, r0
+
+mmu_disable_notreq:
+    NOP
+
+/* To return to ROM from plugin, we need to fill in these argument.
+ * Here is what need to do:
+ * Need to construct the paramters for this function before return to ROM:
+ * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+	pop {r0-r4, lr}
+	push {r5}
+	ldr r5, boot_data2
+	str r5, [r0]
+	ldr r5, image_len2
+	str r5, [r1]
+	ldr r5, second_ivt_offset
+	str r5, [r2]
+	mov r0, #1
+	pop {r5}
+
+	/* return back to ROM code */
+	bx lr
+
+/* make the following data right in the end of the output*/
+.ltorg
+
+#if (defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT))
+#define FLASH_OFFSET 0x1000
+#else
+#define FLASH_OFFSET 0x400
+#endif
+
+/*
+ * second_ivt_offset is the offset from the "second_ivt_header" to
+ * "image_copy_start", which involves FLASH_OFFSET, plus the first
+ * ivt_header, the plugin code size itself recorded by "ivt2_header"
+ */
+
+second_ivt_offset:      .long (ivt2_header + 0x2C + FLASH_OFFSET)
+
+/*
+ * The following is the second IVT header plus the second boot data
+ */
+ivt2_header:            .long 0x0
+app2_code_jump_v:       .long 0x0
+reserv3:                .long 0x0
+dcd2_ptr:               .long 0x0
+boot_data2_ptr:         .long 0x0
+self_ptr2:              .long 0x0
+app_code_csf2:          .long 0x0
+reserv4:                .long 0x0
+boot_data2:             .long 0x0
+image_len2:             .long 0x0
+plugin2:                .long 0x0
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
new file mode 100644
index 0000000..2b2821d
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ */
+#ifndef __ASM_ARCH_MX6DLS_DDR_H__
+#define __ASM_ARCH_MX6DLS_DDR_H__
+
+#ifndef CONFIG_MX6DL
+#ifndef CONFIG_MX6S
+#error "wrong CPU"
+#endif
+#endif
+
+#define MX6_IOM_DRAM_DQM0	0x020e0470
+#define MX6_IOM_DRAM_DQM1	0x020e0474
+#define MX6_IOM_DRAM_DQM2	0x020e0478
+#define MX6_IOM_DRAM_DQM3	0x020e047c
+#define MX6_IOM_DRAM_DQM4	0x020e0480
+#define MX6_IOM_DRAM_DQM5	0x020e0484
+#define MX6_IOM_DRAM_DQM6	0x020e0488
+#define MX6_IOM_DRAM_DQM7	0x020e048c
+
+#define MX6_IOM_DRAM_CAS	0x020e0464
+#define MX6_IOM_DRAM_RAS	0x020e0490
+#define MX6_IOM_DRAM_RESET	0x020e0494
+#define MX6_IOM_DRAM_SDCLK_0	0x020e04ac
+#define MX6_IOM_DRAM_SDCLK_1	0x020e04b0
+#define MX6_IOM_DRAM_SDBA2	0x020e04a0
+#define MX6_IOM_DRAM_SDCKE0	0x020e04a4
+#define MX6_IOM_DRAM_SDCKE1	0x020e04a8
+#define MX6_IOM_DRAM_SDODT0	0x020e04b4
+#define MX6_IOM_DRAM_SDODT1	0x020e04b8
+
+#define MX6_IOM_DRAM_SDQS0	0x020e04bc
+#define MX6_IOM_DRAM_SDQS1	0x020e04c0
+#define MX6_IOM_DRAM_SDQS2	0x020e04c4
+#define MX6_IOM_DRAM_SDQS3	0x020e04c8
+#define MX6_IOM_DRAM_SDQS4	0x020e04cc
+#define MX6_IOM_DRAM_SDQS5	0x020e04d0
+#define MX6_IOM_DRAM_SDQS6	0x020e04d4
+#define MX6_IOM_DRAM_SDQS7	0x020e04d8
+
+#define MX6_IOM_GRP_B0DS	0x020e0764
+#define MX6_IOM_GRP_B1DS	0x020e0770
+#define MX6_IOM_GRP_B2DS	0x020e0778
+#define MX6_IOM_GRP_B3DS	0x020e077c
+#define MX6_IOM_GRP_B4DS	0x020e0780
+#define MX6_IOM_GRP_B5DS	0x020e0784
+#define MX6_IOM_GRP_B6DS	0x020e078c
+#define MX6_IOM_GRP_B7DS	0x020e0748
+#define MX6_IOM_GRP_ADDDS	0x020e074c
+#define MX6_IOM_DDRMODE_CTL	0x020e0750
+#define MX6_IOM_GRP_DDRPKE	0x020e0754
+#define MX6_IOM_GRP_DDRMODE	0x020e0760
+#define MX6_IOM_GRP_CTLDS	0x020e076c
+#define MX6_IOM_GRP_DDR_TYPE	0x020e0774
+
+#endif	/*__ASM_ARCH_MX6S_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
new file mode 100644
index 0000000..c207a75
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -0,0 +1,1079 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__
+#define __ASM_ARCH_MX6_MX6DL_PINS_H__
+
+MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10,	0x0360, 0x004C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC,	0x0360, 0x004C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO,	0x0360, 0x004C, 2, 0x07F8, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA,	0x0360, 0x004C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA,	0x0360, 0x004C, 3, 0x08FC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28,	0x0360, 0x004C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07,	0x0360, 0x004C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11,	0x0364, 0x0050, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS,	0x0364, 0x0050, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0,	0x0364, 0x0050, 2, 0x0800, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA,	0x0364, 0x0050, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA,	0x0364, 0x0050, 3, 0x08FC, 1, 0)
+MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29,	0x0364, 0x0050, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08,	0x0364, 0x0050, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12,	0x0368, 0x0054, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08,	0x0368, 0x0054, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA,	0x0368, 0x0054, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA,	0x0368, 0x0054, 3, 0x0914, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30,	0x0368, 0x0054, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09,	0x0368, 0x0054, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13,	0x036C, 0x0058, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09,	0x036C, 0x0058, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA,	0x036C, 0x0058, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA,	0x036C, 0x0058, 3, 0x0914, 1, 0)
+MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31,	0x036C, 0x0058, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10,	0x036C, 0x0058, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14,	0x0370, 0x005C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10,	0x0370, 0x005C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA,	0x0370, 0x005C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA,	0x0370, 0x005C, 3, 0x091C, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00,	0x0370, 0x005C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11,	0x0370, 0x005C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15,	0x0374, 0x0060, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11,	0x0374, 0x0060, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA,	0x0374, 0x0060, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA,	0x0374, 0x0060, 3, 0x091C, 1, 0)
+MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01,	0x0374, 0x0060, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12,	0x0374, 0x0060, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16,	0x0378, 0x0064, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12,	0x0378, 0x0064, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B,	0x0378, 0x0064, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B,	0x0378, 0x0064, 3, 0x0910, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02,	0x0378, 0x0064, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13,	0x0378, 0x0064, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17,	0x037C, 0x0068, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13,	0x037C, 0x0068, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B,	0x037C, 0x0068, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B,	0x037C, 0x0068, 3, 0x0910, 1, 0)
+MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03,	0x037C, 0x0068, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14,	0x037C, 0x0068, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18,	0x0380, 0x006C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14,	0x0380, 0x006C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B,	0x0380, 0x006C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B,	0x0380, 0x006C, 3, 0x0918, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04,	0x0380, 0x006C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15,	0x0380, 0x006C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19,	0x0384, 0x0070, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15,	0x0384, 0x0070, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B,	0x0384, 0x0070, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B,	0x0384, 0x0070, 3, 0x0918, 1, 0)
+MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05,	0x0384, 0x0070, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04,	0x0388, 0x0074, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02,	0x0388, 0x0074, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK,	0x0388, 0x0074, 2, 0x07D8, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__KEY_COL5,	0x0388, 0x0074, 3, 0x08C0, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC,	0x0388, 0x0074, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22,	0x0388, 0x0074, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01,	0x0388, 0x0074, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05,	0x038C, 0x0078, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03,	0x038C, 0x0078, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI,	0x038C, 0x0078, 2, 0x07E0, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5,	0x038C, 0x0078, 3, 0x08CC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD,	0x038C, 0x0078, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23,	0x038C, 0x0078, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02,	0x038C, 0x0078, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06,	0x0390, 0x007C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04,	0x0390, 0x007C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO,	0x0390, 0x007C, 2, 0x07DC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__KEY_COL6,	0x0390, 0x007C, 3, 0x08C4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS,	0x0390, 0x007C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24,	0x0390, 0x007C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03,	0x0390, 0x007C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07,	0x0394, 0x0080, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05,	0x0394, 0x0080, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0,	0x0394, 0x0080, 2, 0x07E4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6,	0x0394, 0x0080, 3, 0x08D0, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD,	0x0394, 0x0080, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25,	0x0394, 0x0080, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04,	0x0394, 0x0080, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08,	0x0398, 0x0084, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06,	0x0398, 0x0084, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK,	0x0398, 0x0084, 2, 0x07F4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__KEY_COL7,	0x0398, 0x0084, 3, 0x08C8, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA,	0x0398, 0x0084, 4 | IOMUX_CONFIG_SION, 0x086C, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26,	0x0398, 0x0084, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05,	0x0398, 0x0084, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09,	0x039C, 0x0088, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07,	0x039C, 0x0088, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI,	0x039C, 0x0088, 2, 0x07FC, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7,	0x039C, 0x0088, 3, 0x08D4, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL,	0x039C, 0x0088, 4 | IOMUX_CONFIG_SION, 0x0868, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27,	0x039C, 0x0088, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06,	0x039C, 0x0088, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN,	0x03A0, 0x008C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00,	0x03A0, 0x008C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20,	0x03A0, 0x008C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK,	0x03A0, 0x008C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC,	0x03A4, 0x0090, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1,	0x03A4, 0x0090, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19,	0x03A4, 0x0090, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL,	0x03A4, 0x0090, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK,	0x03A8, 0x0094, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18,	0x03A8, 0x0094, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO,	0x03A8, 0x0094, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC,	0x03AC, 0x0098, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01,	0x03AC, 0x0098, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21,	0x03AC, 0x0098, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00,	0x03AC, 0x0098, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_DISP_CLK__LCD_CLK,	0x03B0, 0x009C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16,	0x03B0, 0x009C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__LCD_WR_RWN,	0x03B0, 0x009C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15,	0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN15__LCD_ENABLE,	0x03B4, 0x00A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__AUD6_TXC,	0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17,	0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__LCD_RD_E,	0x03B4, 0x00A0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02,	0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN2__LCD_HSYNC,	0x03B8, 0x00A4, 1, 0x08D8, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__AUD6_TXD,	0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18,	0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__LCD_RS,	0x03B8, 0x00A4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03,	0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN3__LCD_VSYNC,	0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS,	0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19,	0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__LCD_CS,	0x03BC, 0x00A8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04,	0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN4__LCD_BUSY,	0x03C0, 0x00AC, 1, 0x08D8, 1, 0)
+MX6_PAD_DECL(DI0_PIN4__AUD6_RXD,	0x03C0, 0x00AC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__SD1_WP,	0x03C0, 0x00AC, 3, 0x092C, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20,	0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__LCD_RESET,	0x03C0, 0x00AC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00,	0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT0__LCD_DATA00,	0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK,	0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21,	0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01,	0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01,	0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI,	0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22,	0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10,	0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10,	0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31,	0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11,	0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT11__LCD_DATA11,	0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05,	0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12,	0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT12__LCD_DATA12,	0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06,	0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13,	0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT13__LCD_DATA13,	0x03D8, 0x00C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS,	0x03D8, 0x00C4, 3, 0x07BC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07,	0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14,	0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT14__LCD_DATA14,	0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC,	0x03DC, 0x00C8, 3, 0x07B8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08,	0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15,	0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT15__LCD_DATA15,	0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1,	0x03E0, 0x00CC, 2, 0x07E8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1,	0x03E0, 0x00CC, 3, 0x0804, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09,	0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16,	0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT16__LCD_DATA16,	0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI,	0x03E4, 0x00D0, 2, 0x07FC, 1, 0)
+MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC,	0x03E4, 0x00D0, 3, 0x07C0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0,	0x03E4, 0x00D0, 4, 0x08E8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10,	0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17,	0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT17__LCD_DATA17,	0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO,	0x03E8, 0x00D4, 2, 0x07F8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD,	0x03E8, 0x00D4, 3, 0x07B4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1,	0x03E8, 0x00D4, 4, 0x08EC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11,	0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18,	0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT18__LCD_DATA18,	0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0,	0x03EC, 0x00D8, 2, 0x0800, 1, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS,	0x03EC, 0x00D8, 3, 0x07C4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS,	0x03EC, 0x00D8, 4, 0x07A4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12,	0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B,	0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19,	0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT19__LCD_DATA19,	0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK,	0x03F0, 0x00DC, 2, 0x07F4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD,	0x03F0, 0x00DC, 3, 0x07B0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC,	0x03F0, 0x00DC, 4, 0x07A0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13,	0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B,	0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02,	0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02,	0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO,	0x03F4, 0x00E0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23,	0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20,	0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT20__LCD_DATA20,	0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK,	0x03F8, 0x00E4, 2, 0x07D8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC,	0x03F8, 0x00E4, 3, 0x07A8, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14,	0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21,	0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT21__LCD_DATA21,	0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI,	0x03FC, 0x00E8, 2, 0x07E0, 1, 0)
+MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD,	0x03FC, 0x00E8, 3, 0x079C, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15,	0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22,	0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT22__LCD_DATA22,	0x0400, 0x00EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO,	0x0400, 0x00EC, 2, 0x07DC, 1, 0)
+MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS,	0x0400, 0x00EC, 3, 0x07AC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16,	0x0400, 0x00EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23,	0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT23__LCD_DATA23,	0x0404, 0x00F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0,	0x0404, 0x00F0, 2, 0x07E4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD,	0x0404, 0x00F0, 3, 0x0798, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17,	0x0404, 0x00F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03,	0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT3__LCD_DATA03,	0x0408, 0x00F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0,	0x0408, 0x00F4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24,	0x0408, 0x00F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04,	0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT4__LCD_DATA04,	0x040C, 0x00F8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1,	0x040C, 0x00F8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25,	0x040C, 0x00F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05,	0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT5__LCD_DATA05,	0x0410, 0x00FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2,	0x0410, 0x00FC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS,	0x0410, 0x00FC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26,	0x0410, 0x00FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06,	0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT6__LCD_DATA06,	0x0414, 0x0100, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3,	0x0414, 0x0100, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC,	0x0414, 0x0100, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27,	0x0414, 0x0100, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07,	0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT7__LCD_DATA07,	0x0418, 0x0104, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY,	0x0418, 0x0104, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28,	0x0418, 0x0104, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08,	0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT8__LCD_DATA08,	0x041C, 0x0108, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT,	0x041C, 0x0108, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__WDOG1_B,	0x041C, 0x0108, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29,	0x041C, 0x0108, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09,	0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT9__LCD_DATA09,	0x0420, 0x010C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT,	0x0420, 0x010C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__WDOG2_B,	0x0420, 0x010C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30,	0x0420, 0x010C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__EIM_ADDR16,	0x04E0, 0x0110, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK,	0x04E0, 0x0110, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU1_CSI1_PIXCLK,	0x04E0, 0x0110, 2, 0x08B8, 0, 0)
+MX6_PAD_DECL(EIM_A16__GPIO2_IO22,	0x04E0, 0x0110, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16,	0x04E0, 0x0110, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__EPDC_DATA00,	0x04E0, 0x0110, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__EIM_ADDR17,	0x04E4, 0x0114, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12,	0x04E4, 0x0114, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU1_CSI1_DATA12,	0x04E4, 0x0114, 2, 0x0890, 0, 0)
+MX6_PAD_DECL(EIM_A17__GPIO2_IO21,	0x04E4, 0x0114, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17,	0x04E4, 0x0114, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__EPDC_PWR_STAT,	0x04E4, 0x0114, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__EIM_ADDR18,	0x04E8, 0x0118, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13,	0x04E8, 0x0118, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU1_CSI1_DATA13,	0x04E8, 0x0118, 2, 0x0894, 0, 0)
+MX6_PAD_DECL(EIM_A18__GPIO2_IO20,	0x04E8, 0x0118, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18,	0x04E8, 0x0118, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__EPDC_PWR_CTRL0,	0x04E8, 0x0118, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__EIM_ADDR19,	0x04EC, 0x011C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14,	0x04EC, 0x011C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU1_CSI1_DATA14,	0x04EC, 0x011C, 2, 0x0898, 0, 0)
+MX6_PAD_DECL(EIM_A19__GPIO2_IO19,	0x04EC, 0x011C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19,	0x04EC, 0x011C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__EPDC_PWR_CTRL1,	0x04EC, 0x011C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__EIM_ADDR20,	0x04F0, 0x0120, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15,	0x04F0, 0x0120, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU1_CSI1_DATA15,	0x04F0, 0x0120, 2, 0x089C, 0, 0)
+MX6_PAD_DECL(EIM_A20__GPIO2_IO18,	0x04F0, 0x0120, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20,	0x04F0, 0x0120, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__EPDC_PWR_CTRL2,	0x04F0, 0x0120, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__EIM_ADDR21,	0x04F4, 0x0124, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16,	0x04F4, 0x0124, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU1_CSI1_DATA16,	0x04F4, 0x0124, 2, 0x08A0, 0, 0)
+MX6_PAD_DECL(EIM_A21__GPIO2_IO17,	0x04F4, 0x0124, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21,	0x04F4, 0x0124, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__EPDC_GDCLK,	0x04F4, 0x0124, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__EIM_ADDR22,	0x04F8, 0x0128, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17,	0x04F8, 0x0128, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU1_CSI1_DATA17,	0x04F8, 0x0128, 2, 0x08A4, 0, 0)
+MX6_PAD_DECL(EIM_A22__GPIO2_IO16,	0x04F8, 0x0128, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22,	0x04F8, 0x0128, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__EPDC_GDSP,	0x04F8, 0x0128, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__EIM_ADDR23,	0x04FC, 0x012C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18,	0x04FC, 0x012C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_CSI1_DATA18,	0x04FC, 0x012C, 2, 0x08A8, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_SISG3,	0x04FC, 0x012C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__GPIO6_IO06,	0x04FC, 0x012C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23,	0x04FC, 0x012C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__EPDC_GDOE,	0x04FC, 0x012C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__EIM_ADDR24,	0x0500, 0x0130, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19,	0x0500, 0x0130, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_CSI1_DATA19,	0x0500, 0x0130, 2, 0x08AC, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_SISG2,	0x0500, 0x0130, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__GPIO5_IO04,	0x0500, 0x0130, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24,	0x0500, 0x0130, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__EPDC_GDRL,	0x0500, 0x0130, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__EIM_ADDR25,	0x0504, 0x0134, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI4_SS1,	0x0504, 0x0134, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI2_RDY,	0x0504, 0x0134, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12,	0x0504, 0x0134, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS,	0x0504, 0x0134, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__GPIO5_IO02,	0x0504, 0x0134, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE,	0x0504, 0x0134, 6, 0x085C, 0, 0)
+MX6_PAD_DECL(EIM_A25__EPDC_DATA15,	0x0504, 0x0134, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__EIM_ACLK_FREERUN,	0x0504, 0x0134, 9, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__EIM_BCLK,	0x0508, 0x0138, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16,	0x0508, 0x0138, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31,	0x0508, 0x0138, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__EPDC_SDCE9,	0x0508, 0x0138, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__EIM_CS0_B,	0x050C, 0x013C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05,	0x050C, 0x013C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK,	0x050C, 0x013C, 2, 0x07F4, 2, 0)
+MX6_PAD_DECL(EIM_CS0__GPIO2_IO23,	0x050C, 0x013C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__EPDC_DATA06,	0x050C, 0x013C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__EIM_CS1_B,	0x0510, 0x0140, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06,	0x0510, 0x0140, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI,	0x0510, 0x0140, 2, 0x07FC, 2, 0)
+MX6_PAD_DECL(EIM_CS1__GPIO2_IO24,	0x0510, 0x0140, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__EPDC_DATA08,	0x0510, 0x0140, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__EIM_DATA16,	0x0514, 0x0144, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK,	0x0514, 0x0144, 1, 0x07D8, 2, 0)
+MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05,	0x0514, 0x0144, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__IPU1_CSI1_DATA18,	0x0514, 0x0144, 3, 0x08A8, 1, 0)
+MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA,	0x0514, 0x0144, 4, 0x0864, 0, 0)
+MX6_PAD_DECL(EIM_D16__GPIO3_IO16,	0x0514, 0x0144, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__I2C2_SDA,	0x0514, 0x0144, 6 | IOMUX_CONFIG_SION, 0x0874, 0, 0)
+MX6_PAD_DECL(EIM_D16__EPDC_DATA10,	0x0514, 0x0144, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__EIM_DATA17,	0x0518, 0x0148, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__ECSPI1_MISO,	0x0518, 0x0148, 1, 0x07DC, 2, 0)
+MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06,	0x0518, 0x0148, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__IPU1_CSI1_PIXCLK,	0x0518, 0x0148, 3, 0x08B8, 1, 0)
+MX6_PAD_DECL(EIM_D17__DCIC1_OUT,	0x0518, 0x0148, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__GPIO3_IO17,	0x0518, 0x0148, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__I2C3_SCL,	0x0518, 0x0148, 6 | IOMUX_CONFIG_SION, 0x0878, 0, 0)
+MX6_PAD_DECL(EIM_D17__EPDC_VCOM0,	0x0518, 0x0148, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__EIM_DATA18,	0x051C, 0x014C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI,	0x051C, 0x014C, 1, 0x07E0, 2, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07,	0x051C, 0x014C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_CSI1_DATA17,	0x051C, 0x014C, 3, 0x08A4, 1, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS,	0x051C, 0x014C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__GPIO3_IO18,	0x051C, 0x014C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__I2C3_SDA,	0x051C, 0x014C, 6 | IOMUX_CONFIG_SION, 0x087C, 0, 0)
+MX6_PAD_DECL(EIM_D18__EPDC_VCOM1,	0x051C, 0x014C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EIM_DATA19,	0x0520, 0x0150, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__ECSPI1_SS1,	0x0520, 0x0150, 1, 0x07E8, 1, 0)
+MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08,	0x0520, 0x0150, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__IPU1_CSI1_DATA16,	0x0520, 0x0150, 3, 0x08A0, 1, 0)
+MX6_PAD_DECL(EIM_D19__UART1_CTS_B,	0x0520, 0x0150, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__UART1_RTS_B,	0x0520, 0x0150, 4, 0x08F8, 0, 0)
+MX6_PAD_DECL(EIM_D19__GPIO3_IO19,	0x0520, 0x0150, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EPIT1_OUT,	0x0520, 0x0150, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EPDC_DATA12,	0x0520, 0x0150, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EIM_DATA20,	0x0524, 0x0154, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__ECSPI4_SS0,	0x0524, 0x0154, 1, 0x0808, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16,	0x0524, 0x0154, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU1_CSI1_DATA15,	0x0524, 0x0154, 3, 0x089C, 1, 0)
+MX6_PAD_DECL(EIM_D20__UART1_CTS_B,	0x0524, 0x0154, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__UART1_RTS_B,	0x0524, 0x0154, 4, 0x08F8, 1, 0)
+MX6_PAD_DECL(EIM_D20__GPIO3_IO20,	0x0524, 0x0154, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EPIT2_OUT,	0x0524, 0x0154, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__EIM_DATA21,	0x0528, 0x0158, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK,	0x0528, 0x0158, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17,	0x0528, 0x0158, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU1_CSI1_DATA11,	0x0528, 0x0158, 3, 0x088C, 0, 0)
+MX6_PAD_DECL(EIM_D21__USB_OTG_OC,	0x0528, 0x0158, 4, 0x0920, 0, 0)
+MX6_PAD_DECL(EIM_D21__GPIO3_IO21,	0x0528, 0x0158, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__I2C1_SCL,	0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0)
+MX6_PAD_DECL(EIM_D21__SPDIF_IN,	0x0528, 0x0158, 7, 0x08F0, 0, 0)
+MX6_PAD_DECL(EIM_D22__EIM_DATA22,	0x052C, 0x015C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__ECSPI4_MISO,	0x052C, 0x015C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01,	0x052C, 0x015C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU1_CSI1_DATA10,	0x052C, 0x015C, 3, 0x0888, 0, 0)
+MX6_PAD_DECL(EIM_D22__USB_OTG_PWR,	0x052C, 0x015C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__GPIO3_IO22,	0x052C, 0x015C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__SPDIF_OUT,	0x052C, 0x015C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__EPDC_SDCE6,	0x052C, 0x015C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__EIM_DATA23,	0x0530, 0x0160, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS,	0x0530, 0x0160, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_CTS_B,	0x0530, 0x0160, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_RTS_B,	0x0530, 0x0160, 2, 0x0908, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART1_DCD_B,	0x0530, 0x0160, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_CSI1_DATA_EN,	0x0530, 0x0160, 4, 0x08B0, 0, 0)
+MX6_PAD_DECL(EIM_D23__GPIO3_IO23,	0x0530, 0x0160, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02,	0x0530, 0x0160, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14,	0x0530, 0x0160, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__EPDC_DATA11,	0x0530, 0x0160, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__EIM_DATA24,	0x0534, 0x0164, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI4_SS2,	0x0534, 0x0164, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_TX_DATA,	0x0534, 0x0164, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_RX_DATA,	0x0534, 0x0164, 2, 0x090C, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI1_SS2,	0x0534, 0x0164, 3, 0x07EC, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI2_SS2,	0x0534, 0x0164, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__GPIO3_IO24,	0x0534, 0x0164, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__AUD5_RXFS,	0x0534, 0x0164, 6, 0x07BC, 1, 0)
+MX6_PAD_DECL(EIM_D24__UART1_DTR_B,	0x0534, 0x0164, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__EPDC_SDCE7,	0x0534, 0x0164, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__EIM_DATA25,	0x0538, 0x0168, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI4_SS3,	0x0538, 0x0168, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_TX_DATA,	0x0538, 0x0168, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_RX_DATA,	0x0538, 0x0168, 2, 0x090C, 1, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI1_SS3,	0x0538, 0x0168, 3, 0x07F0, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI2_SS3,	0x0538, 0x0168, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__GPIO3_IO25,	0x0538, 0x0168, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__AUD5_RXC,	0x0538, 0x0168, 6, 0x07B8, 1, 0)
+MX6_PAD_DECL(EIM_D25__UART1_DSR_B,	0x0538, 0x0168, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__EPDC_SDCE8,	0x0538, 0x0168, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__EIM_DATA26,	0x053C, 0x016C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11,	0x053C, 0x016C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01,	0x053C, 0x016C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_CSI1_DATA14,	0x053C, 0x016C, 3, 0x0898, 1, 0)
+MX6_PAD_DECL(EIM_D26__UART2_TX_DATA,	0x053C, 0x016C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__UART2_RX_DATA,	0x053C, 0x016C, 4, 0x0904, 0, 0)
+MX6_PAD_DECL(EIM_D26__GPIO3_IO26,	0x053C, 0x016C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_SISG2,	0x053C, 0x016C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22,	0x053C, 0x016C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__EPDC_SDOED,	0x053C, 0x016C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__EIM_DATA27,	0x0540, 0x0170, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13,	0x0540, 0x0170, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00,	0x0540, 0x0170, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_CSI1_DATA13,	0x0540, 0x0170, 3, 0x0894, 1, 0)
+MX6_PAD_DECL(EIM_D27__UART2_TX_DATA,	0x0540, 0x0170, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__UART2_RX_DATA,	0x0540, 0x0170, 4, 0x0904, 1, 0)
+MX6_PAD_DECL(EIM_D27__GPIO3_IO27,	0x0540, 0x0170, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_SISG3,	0x0540, 0x0170, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23,	0x0540, 0x0170, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__EPDC_SDOE,	0x0540, 0x0170, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__EIM_DATA28,	0x0544, 0x0174, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__I2C1_SDA,	0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0)
+MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI,	0x0544, 0x0174, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_CSI1_DATA12,	0x0544, 0x0174, 3, 0x0890, 1, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B,	0x0544, 0x0174, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B,	0x0544, 0x0174, 4, 0x0900, 0, 0)
+MX6_PAD_DECL(EIM_D28__GPIO3_IO28,	0x0544, 0x0174, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG,	0x0544, 0x0174, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13,	0x0544, 0x0174, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__EPDC_PWR_CTRL3,	0x0544, 0x0174, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__EIM_DATA29,	0x0548, 0x0178, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15,	0x0548, 0x0178, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__ECSPI4_SS0,	0x0548, 0x0178, 2, 0x0808, 1, 0)
+MX6_PAD_DECL(EIM_D29__UART2_CTS_B,	0x0548, 0x0178, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__UART2_RTS_B,	0x0548, 0x0178, 4, 0x0900, 1, 0)
+MX6_PAD_DECL(EIM_D29__GPIO3_IO29,	0x0548, 0x0178, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_CSI1_VSYNC,	0x0548, 0x0178, 6, 0x08BC, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14,	0x0548, 0x0178, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__EPDC_PWR_WAKE,	0x0548, 0x0178, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__EIM_DATA30,	0x054C, 0x017C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21,	0x054C, 0x017C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11,	0x054C, 0x017C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03,	0x054C, 0x017C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_CTS_B,	0x054C, 0x017C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_RTS_B,	0x054C, 0x017C, 4, 0x0908, 1, 0)
+MX6_PAD_DECL(EIM_D30__GPIO3_IO30,	0x054C, 0x017C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__USB_H1_OC,	0x054C, 0x017C, 6, 0x0924, 0, 0)
+MX6_PAD_DECL(EIM_D30__EPDC_SDOEZ,	0x054C, 0x017C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__EIM_DATA31,	0x0550, 0x0180, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20,	0x0550, 0x0180, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12,	0x0550, 0x0180, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02,	0x0550, 0x0180, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_CTS_B,	0x0550, 0x0180, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_RTS_B,	0x0550, 0x0180, 4, 0x0908, 2, 0)
+MX6_PAD_DECL(EIM_D31__GPIO3_IO31,	0x0550, 0x0180, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__USB_H1_PWR,	0x0550, 0x0180, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__EPDC_SDCLK_P,	0x0550, 0x0180, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__EIM_ACLK_FREERUN,	0x0550, 0x0180, 9, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__EIM_AD00,	0x0554, 0x0184, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09,	0x0554, 0x0184, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU1_CSI1_DATA09,	0x0554, 0x0184, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__GPIO3_IO00,	0x0554, 0x0184, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00,	0x0554, 0x0184, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__EPDC_SDCLK_N,	0x0554, 0x0184, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__EIM_AD01,	0x0558, 0x0188, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08,	0x0558, 0x0188, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU1_CSI1_DATA08,	0x0558, 0x0188, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__GPIO3_IO01,	0x0558, 0x0188, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01,	0x0558, 0x0188, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__EPDC_SDLE,	0x0558, 0x0188, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__EIM_AD10,	0x055C, 0x018C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15,	0x055C, 0x018C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU1_CSI1_DATA_EN,	0x055C, 0x018C, 2, 0x08B0, 1, 0)
+MX6_PAD_DECL(EIM_DA10__GPIO3_IO10,	0x055C, 0x018C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10,	0x055C, 0x018C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__EPDC_DATA01,	0x055C, 0x018C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__EIM_AD11,	0x0560, 0x0190, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02,	0x0560, 0x0190, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU1_CSI1_HSYNC,	0x0560, 0x0190, 2, 0x08B4, 0, 0)
+MX6_PAD_DECL(EIM_DA11__GPIO3_IO11,	0x0560, 0x0190, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11,	0x0560, 0x0190, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__EPDC_DATA03,	0x0560, 0x0190, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__EIM_AD12,	0x0564, 0x0194, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03,	0x0564, 0x0194, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU1_CSI1_VSYNC,	0x0564, 0x0194, 2, 0x08BC, 1, 0)
+MX6_PAD_DECL(EIM_DA12__GPIO3_IO12,	0x0564, 0x0194, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12,	0x0564, 0x0194, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__EPDC_DATA02,	0x0564, 0x0194, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__EIM_AD13,	0x0568, 0x0198, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS,	0x0568, 0x0198, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__GPIO3_IO13,	0x0568, 0x0198, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13,	0x0568, 0x0198, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__EPDC_DATA13,	0x0568, 0x0198, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__EIM_AD14,	0x056C, 0x019C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS,	0x056C, 0x019C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__GPIO3_IO14,	0x056C, 0x019C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14,	0x056C, 0x019C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__EPDC_DATA14,	0x056C, 0x019C, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__EIM_AD15,	0x0570, 0x01A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01,	0x0570, 0x01A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04,	0x0570, 0x01A0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__GPIO3_IO15,	0x0570, 0x01A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15,	0x0570, 0x01A0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__EPDC_DATA09,	0x0570, 0x01A0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__EIM_AD02,	0x0574, 0x01A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07,	0x0574, 0x01A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU1_CSI1_DATA07,	0x0574, 0x01A4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__GPIO3_IO02,	0x0574, 0x01A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02,	0x0574, 0x01A4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__EPDC_BDR0,	0x0574, 0x01A4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__EIM_AD03,	0x0578, 0x01A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06,	0x0578, 0x01A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU1_CSI1_DATA06,	0x0578, 0x01A8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__GPIO3_IO03,	0x0578, 0x01A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03,	0x0578, 0x01A8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__EPDC_BDR1,	0x0578, 0x01A8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__EIM_AD04,	0x057C, 0x01AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05,	0x057C, 0x01AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU1_CSI1_DATA05,	0x057C, 0x01AC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__GPIO3_IO04,	0x057C, 0x01AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04,	0x057C, 0x01AC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__EPDC_SDCE0,	0x057C, 0x01AC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__EIM_AD05,	0x0580, 0x01B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04,	0x0580, 0x01B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU1_CSI1_DATA04,	0x0580, 0x01B0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__GPIO3_IO05,	0x0580, 0x01B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05,	0x0580, 0x01B0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__EPDC_SDCE1,	0x0580, 0x01B0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__EIM_AD06,	0x0584, 0x01B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03,	0x0584, 0x01B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU1_CSI1_DATA03,	0x0584, 0x01B4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__GPIO3_IO06,	0x0584, 0x01B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06,	0x0584, 0x01B4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__EPDC_SDCE2,	0x0584, 0x01B4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__EIM_AD07,	0x0588, 0x01B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02,	0x0588, 0x01B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU1_CSI1_DATA02,	0x0588, 0x01B8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__GPIO3_IO07,	0x0588, 0x01B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07,	0x0588, 0x01B8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__EPDC_SDCE3,	0x0588, 0x01B8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__EIM_AD08,	0x058C, 0x01BC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01,	0x058C, 0x01BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU1_CSI1_DATA01,	0x058C, 0x01BC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__GPIO3_IO08,	0x058C, 0x01BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08,	0x058C, 0x01BC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__EPDC_SDCE4,	0x058C, 0x01BC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__EIM_AD09,	0x0590, 0x01C0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00,	0x0590, 0x01C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU1_CSI1_DATA00,	0x0590, 0x01C0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__GPIO3_IO09,	0x0590, 0x01C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09,	0x0590, 0x01C0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__EPDC_SDCE5,	0x0590, 0x01C0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__EIM_EB0_B,	0x0594, 0x01C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11,	0x0594, 0x01C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU1_CSI1_DATA11,	0x0594, 0x01C4, 2, 0x088C, 1, 0)
+MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY,	0x0594, 0x01C4, 4, 0x07D4, 0, 0)
+MX6_PAD_DECL(EIM_EB0__GPIO2_IO28,	0x0594, 0x01C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27,	0x0594, 0x01C4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__EPDC_PWR_COM,	0x0594, 0x01C4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__EIM_EB1_B,	0x0598, 0x01C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10,	0x0598, 0x01C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU1_CSI1_DATA10,	0x0598, 0x01C8, 2, 0x0888, 1, 0)
+MX6_PAD_DECL(EIM_EB1__GPIO2_IO29,	0x0598, 0x01C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28,	0x0598, 0x01C8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__EPDC_SDSHR,	0x0598, 0x01C8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__EIM_EB2_B,	0x059C, 0x01CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0,	0x059C, 0x01CC, 1, 0x07E4, 2, 0)
+MX6_PAD_DECL(EIM_EB2__IPU1_CSI1_DATA19,	0x059C, 0x01CC, 3, 0x08AC, 1, 0)
+MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL,	0x059C, 0x01CC, 4, 0x0860, 0, 0)
+MX6_PAD_DECL(EIM_EB2__GPIO2_IO30,	0x059C, 0x01CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__I2C2_SCL,	0x059C, 0x01CC, 6 | IOMUX_CONFIG_SION, 0x0870, 0, 0)
+MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30,	0x059C, 0x01CC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__EPDC_DATA05,	0x059C, 0x01CC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EIM_EB3_B,	0x05A0, 0x01D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY,	0x05A0, 0x01D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_CTS_B,	0x05A0, 0x01D0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_RTS_B,	0x05A0, 0x01D0, 2, 0x0908, 3, 0)
+MX6_PAD_DECL(EIM_EB3__UART1_RI_B,	0x05A0, 0x01D0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU1_CSI1_HSYNC,	0x05A0, 0x01D0, 4, 0x08B4, 1, 0)
+MX6_PAD_DECL(EIM_EB3__GPIO2_IO31,	0x05A0, 0x01D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03,	0x05A0, 0x01D0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31,	0x05A0, 0x01D0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EPDC_SDCE0,	0x05A0, 0x01D0, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EIM_ACLK_FREERUN,	0x05A0, 0x01D0, 9, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__EIM_LBA_B,	0x05A4, 0x01D4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17,	0x05A4, 0x01D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1,	0x05A4, 0x01D4, 2, 0x0804, 1, 0)
+MX6_PAD_DECL(EIM_LBA__GPIO2_IO27,	0x05A4, 0x01D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26,	0x05A4, 0x01D4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__EPDC_DATA04,	0x05A4, 0x01D4, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__EIM_OE_B,	0x05A8, 0x01D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07,	0x05A8, 0x01D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__ECSPI2_MISO,	0x05A8, 0x01D8, 2, 0x07F8, 2, 0)
+MX6_PAD_DECL(EIM_OE__GPIO2_IO25,	0x05A8, 0x01D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__EPDC_PWR_IRQ,	0x05A8, 0x01D8, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__EIM_RW,	0x05AC, 0x01DC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08,	0x05AC, 0x01DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__ECSPI2_SS0,	0x05AC, 0x01DC, 2, 0x0800, 2, 0)
+MX6_PAD_DECL(EIM_RW__GPIO2_IO26,	0x05AC, 0x01DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29,	0x05AC, 0x01DC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__EPDC_DATA07,	0x05AC, 0x01DC, 8, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B,	0x05B0, 0x01E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B,	0x05B0, 0x01E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00,	0x05B0, 0x01E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25,	0x05B0, 0x01E0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN,	0x05B4, 0x01E4, 1, 0x0828, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK,	0x05B4, 0x01E4, 2, 0x0840, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK,	0x05B4, 0x01E4, 3, 0x08F4, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25,	0x05B4, 0x01E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__MLB_DATA,	0x05B8, 0x01E8, 0, 0x08E0, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_MDC,	0x05B8, 0x01E8, 1, 0x0000, 0,  0)
+MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0,	0x05B8, 0x01E8, 2, 0x0858, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN,	0x05B8, 0x01E8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__GPIO1_IO31,	0x05B8, 0x01E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_MDIO,	0x05BC, 0x01EC, 1, 0x0810, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK,	0x05BC, 0x01EC, 2, 0x083C, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT,	0x05BC, 0x01EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22,	0x05BC, 0x01EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK,	0x05BC, 0x01EC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK,	0x05C0, 0x01F0, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS,	0x05C0, 0x01F0, 2, 0x082C, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23,	0x05C0, 0x01F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK,	0x05C0, 0x01F0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID,	0x05C4, 0x01F4, 0, 0x0790, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER,	0x05C4, 0x01F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK,	0x05C4, 0x01F4, 2, 0x0834, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN,	0x05C4, 0x01F4, 3, 0x08F0, 1, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT,	0x05C4, 0x01F4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24,	0x05C4, 0x01F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0,	0x05C8, 0x01F8, 1, 0x0818, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK,	0x05C8, 0x01F8, 2, 0x0838, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT,	0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27,	0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__MLB_SIG,	0x05CC, 0x01FC, 0, 0x08E4, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1,	0x05CC, 0x01FC, 1, 0x081C, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS,	0x05CC, 0x01FC, 2, 0x0830, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT,	0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26,	0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN,	0x05D0, 0x0200, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2,	0x05D0, 0x0200, 2, 0x0850, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28,	0x05D0, 0x0200, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__I2C4_SCL,	0x05D0, 0x0200, 9 | IOMUX_CONFIG_SION, 0x0880, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0,	0x05D4, 0x0204, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1,	0x05D4, 0x0204, 2, 0x0854, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30,	0x05D4, 0x0204, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__MLB_CLK,	0x05D8, 0x0208, 0, 0x08DC, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1,	0x05D8, 0x0208, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3,	0x05D8, 0x0208, 2, 0x084C, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN,	0x05D8, 0x0208, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29,	0x05D8, 0x0208, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__I2C4_SDA,	0x05D8, 0x0208, 9 | IOMUX_CONFIG_SION, 0x0884, 0, 0)
+MX6_PAD_DECL(GPIO_0__CCM_CLKO1,	0x05DC, 0x020C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__KEY_COL5,	0x05DC, 0x020C, 2, 0x08C0, 1, 0)
+MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK,	0x05DC, 0x020C, 3, 0x0794, 0, 0)
+MX6_PAD_DECL(GPIO_0__EPIT1_OUT,	0x05DC, 0x020C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__GPIO1_IO00,	0x05DC, 0x020C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__USB_H1_PWR,	0x05DC, 0x020C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__SNVS_VIO_5,	0x05DC, 0x020C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK,	0x05E0, 0x0210, 0, 0x083C, 1, 0)
+MX6_PAD_DECL(GPIO_1__WDOG2_B,	0x05E0, 0x0210, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__KEY_ROW5,	0x05E0, 0x0210, 2, 0x08CC, 1, 0)
+MX6_PAD_DECL(GPIO_1__USB_OTG_ID,	0x05E0, 0x0210, 3, 0x0790, 1, 0)
+MX6_PAD_DECL(GPIO_1__PWM2_OUT,	0x05E0, 0x0210, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__GPIO1_IO01,	0x05E0, 0x0210, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__SD1_CD_B,	0x05E0, 0x0210, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,	0x05E4, 0x0214, 0, 0x0850, 1, 0)
+MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN,	0x05E4, 0x0214, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,	0x05E4, 0x0214, 2 | IOMUX_CONFIG_SION, 0x080C, 0, 0)
+MX6_PAD_DECL(GPIO_16__SD1_LCTL,	0x05E4, 0x0214, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__SPDIF_IN,	0x05E4, 0x0214, 4, 0x08F0, 2, 0)
+MX6_PAD_DECL(GPIO_16__GPIO7_IO11,	0x05E4, 0x0214, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__I2C3_SDA,	0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0)
+MX6_PAD_DECL(GPIO_16__JTAG_DE_B,	0x05E4, 0x0214, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__ESAI_TX0,	0x05E8, 0x0218, 0, 0x0844, 0, 0)
+MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN,	0x05E8, 0x0218, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY,	0x05E8, 0x0218, 2, 0x07D4, 1, 0)
+MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0,	0x05E8, 0x0218, 3, 0x08E8, 1, 0)
+MX6_PAD_DECL(GPIO_17__SPDIF_OUT,	0x05E8, 0x0218, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__GPIO7_IO12,	0x05E8, 0x0218, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__ESAI_TX1,	0x05EC, 0x021C, 0, 0x0848, 0, 0)
+MX6_PAD_DECL(GPIO_18__ENET_RX_CLK,	0x05EC, 0x021C, 1, 0x0814, 0, 0)
+MX6_PAD_DECL(GPIO_18__SD3_VSELECT,	0x05EC, 0x021C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1,	0x05EC, 0x021C, 3, 0x08EC, 1, 0)
+MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK,	0x05EC, 0x021C, 4, 0x0794, 1, 0)
+MX6_PAD_DECL(GPIO_18__GPIO7_IO13,	0x05EC, 0x021C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL,	0x05EC, 0x021C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__KEY_COL5,	0x05F0, 0x0220, 0, 0x08C0, 2, 0)
+MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT,	0x05F0, 0x0220, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__SPDIF_OUT,	0x05F0, 0x0220, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__CCM_CLKO1,	0x05F0, 0x0220, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ECSPI1_RDY,	0x05F0, 0x0220, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__GPIO4_IO05,	0x05F0, 0x0220, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ENET_TX_ER,	0x05F0, 0x0220, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__ESAI_TX_FS,	0x05F4, 0x0224, 0, 0x0830, 1, 0)
+MX6_PAD_DECL(GPIO_2__KEY_ROW6,	0x05F4, 0x0224, 2, 0x08D0, 1, 0)
+MX6_PAD_DECL(GPIO_2__GPIO1_IO02,	0x05F4, 0x0224, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__SD2_WP,	0x05F4, 0x0224, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__MLB_DATA,	0x05F4, 0x0224, 7, 0x08E0, 1, 0)
+MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK,	0x05F8, 0x0228, 0, 0x0834, 1, 0)
+MX6_PAD_DECL(GPIO_3__I2C3_SCL,	0x05F8, 0x0228, 2 | IOMUX_CONFIG_SION, 0x0878, 1, 0)
+MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M,	0x05F8, 0x0228, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__CCM_CLKO2,	0x05F8, 0x0228, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__GPIO1_IO03,	0x05F8, 0x0228, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__USB_H1_OC,	0x05F8, 0x0228, 6, 0x0924, 1, 0)
+MX6_PAD_DECL(GPIO_3__MLB_CLK,	0x05F8, 0x0228, 7, 0x08DC, 1, 0)
+MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK,	0x05FC, 0x022C, 0, 0x0838, 1, 0)
+MX6_PAD_DECL(GPIO_4__KEY_COL7,	0x05FC, 0x022C, 2, 0x08C8, 1, 0)
+MX6_PAD_DECL(GPIO_4__GPIO1_IO04,	0x05FC, 0x022C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_4__SD2_CD_B,	0x05FC, 0x022C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3,	0x0600, 0x0230, 0, 0x084C, 1, 0)
+MX6_PAD_DECL(GPIO_5__KEY_ROW7,	0x0600, 0x0230, 2, 0x08D4, 1, 0)
+MX6_PAD_DECL(GPIO_5__CCM_CLKO1,	0x0600, 0x0230, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__GPIO1_IO05,	0x0600, 0x0230, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__I2C3_SCL,	0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0)
+MX6_PAD_DECL(GPIO_5__ARM_EVENTI,	0x0600, 0x0230, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK,	0x0604, 0x0234, 0, 0x0840, 1, 0)
+MX6_PAD_DECL(GPIO_6__I2C3_SDA,	0x0604, 0x0234, 2 | IOMUX_CONFIG_SION, 0x087C, 2, 0)
+MX6_PAD_DECL(GPIO_6__GPIO1_IO06,	0x0604, 0x0234, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__SD2_LCTL,	0x0604, 0x0234, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__MLB_SIG,	0x0604, 0x0234, 7, 0x08E4, 1, 0)
+MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1,	0x0608, 0x0238, 0, 0x0854, 1, 0)
+MX6_PAD_DECL(GPIO_7__EPIT1_OUT,	0x0608, 0x0238, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX,	0x0608, 0x0238, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_TX_DATA,	0x0608, 0x0238, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_RX_DATA,	0x0608, 0x0238, 4, 0x0904, 2, 0)
+MX6_PAD_DECL(GPIO_7__GPIO1_IO07,	0x0608, 0x0238, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__SPDIF_LOCK,	0x0608, 0x0238, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE,	0x0608, 0x0238, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__I2C4_SCL,	0x0608, 0x0238, 8 | IOMUX_CONFIG_SION, 0x0880, 1, 0)
+MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0,	0x060C, 0x023C, 0, 0x0858, 1, 0)
+MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K,	0x060C, 0x023C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__EPIT2_OUT,	0x060C, 0x023C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX,	0x060C, 0x023C, 3, 0x07C8, 0, 0)
+MX6_PAD_DECL(GPIO_8__UART2_TX_DATA,	0x060C, 0x023C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__UART2_RX_DATA,	0x060C, 0x023C, 4, 0x0904, 3, 0)
+MX6_PAD_DECL(GPIO_8__GPIO1_IO08,	0x060C, 0x023C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK,	0x060C, 0x023C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE,	0x060C, 0x023C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__I2C4_SDA,	0x060C, 0x023C, 8 | IOMUX_CONFIG_SION, 0x0884, 1, 0)
+MX6_PAD_DECL(GPIO_9__ESAI_RX_FS,	0x0610, 0x0240, 0, 0x082C, 1, 0)
+MX6_PAD_DECL(GPIO_9__WDOG1_B,	0x0610, 0x0240, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__KEY_COL6,	0x0610, 0x0240, 2, 0x08C4, 1, 0)
+MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B,	0x0610, 0x0240, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__PWM1_OUT,	0x0610, 0x0240, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__GPIO1_IO09,	0x0610, 0x0240, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__SD1_WP,	0x0610, 0x0240, 6, 0x092C, 1, 0)
+MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK,	0x062C, 0x0244, 0, 0x07D8, 3, 0)
+MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3,	0x062C, 0x0244, 1, 0x0824, 0, 0)
+MX6_PAD_DECL(KEY_COL0__AUD5_TXC,	0x062C, 0x0244, 2, 0x07C0, 1, 0)
+MX6_PAD_DECL(KEY_COL0__KEY_COL0,	0x062C, 0x0244, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA,	0x062C, 0x0244, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA,	0x062C, 0x0244, 4, 0x0914, 2, 0)
+MX6_PAD_DECL(KEY_COL0__GPIO4_IO06,	0x062C, 0x0244, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__DCIC1_OUT,	0x062C, 0x0244, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO,	0x0630, 0x0248, 0, 0x07DC, 3, 0)
+MX6_PAD_DECL(KEY_COL1__ENET_MDIO,	0x0630, 0x0248, 1, 0x0810, 1, 0)
+MX6_PAD_DECL(KEY_COL1__AUD5_TXFS,	0x0630, 0x0248, 2, 0x07C4, 1, 0)
+MX6_PAD_DECL(KEY_COL1__KEY_COL1,	0x0630, 0x0248, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA,	0x0630, 0x0248, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA,	0x0630, 0x0248, 4, 0x091C, 2, 0)
+MX6_PAD_DECL(KEY_COL1__GPIO4_IO08,	0x0630, 0x0248, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__SD1_VSELECT,	0x0630, 0x0248, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1,	0x0634, 0x024C, 0, 0x07E8, 2, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2,	0x0634, 0x024C, 1, 0x0820, 0, 0)
+MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX,	0x0634, 0x024C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__KEY_COL2,	0x0634, 0x024C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_MDC,	0x0634, 0x024C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__GPIO4_IO10,	0x0634, 0x024C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE,	0x0634, 0x024C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3,	0x0638, 0x0250, 0, 0x07F0, 1, 0)
+MX6_PAD_DECL(KEY_COL3__ENET_CRS,	0x0638, 0x0250, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL,	0x0638, 0x0250, 2, 0x0860, 1, 0)
+MX6_PAD_DECL(KEY_COL3__KEY_COL3,	0x0638, 0x0250, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__I2C2_SCL,	0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0)
+MX6_PAD_DECL(KEY_COL3__GPIO4_IO12,	0x0638, 0x0250, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__SPDIF_IN,	0x0638, 0x0250, 6, 0x08F0, 3, 0)
+MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX,	0x063C, 0x0254, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__IPU1_SISG4,	0x063C, 0x0254, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__USB_OTG_OC,	0x063C, 0x0254, 2, 0x0920, 1, 0)
+MX6_PAD_DECL(KEY_COL4__KEY_COL4,	0x063C, 0x0254, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_CTS_B,	0x063C, 0x0254, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_RTS_B,	0x063C, 0x0254, 4, 0x0918, 2, 0)
+MX6_PAD_DECL(KEY_COL4__GPIO4_IO14,	0x063C, 0x0254, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI,	0x0640, 0x0258, 0, 0x07E0, 3, 0)
+MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3,	0x0640, 0x0258, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__AUD5_TXD,	0x0640, 0x0258, 2, 0x07B4, 1, 0)
+MX6_PAD_DECL(KEY_ROW0__KEY_ROW0,	0x0640, 0x0258, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA,	0x0640, 0x0258, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA,	0x0640, 0x0258, 4, 0x0914, 3, 0)
+MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07,	0x0640, 0x0258, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT,	0x0640, 0x0258, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0,	0x0644, 0x025C, 0, 0x07E4, 3, 0)
+MX6_PAD_DECL(KEY_ROW1__ENET_COL,	0x0644, 0x025C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__AUD5_RXD,	0x0644, 0x025C, 2, 0x07B0, 1, 0)
+MX6_PAD_DECL(KEY_ROW1__KEY_ROW1,	0x0644, 0x025C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA,	0x0644, 0x025C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA,	0x0644, 0x025C, 4, 0x091C, 3, 0)
+MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09,	0x0644, 0x025C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT,	0x0644, 0x025C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2,	0x0648, 0x0260, 0, 0x07EC, 1, 0)
+MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2,	0x0648, 0x0260, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX,	0x0648, 0x0260, 2, 0x07C8, 1, 0)
+MX6_PAD_DECL(KEY_ROW2__KEY_ROW2,	0x0648, 0x0260, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT,	0x0648, 0x0260, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11,	0x0648, 0x0260, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE,	0x0648, 0x0260, 6, 0x085C, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK,	0x064C, 0x0264, 1, 0x0794, 2, 0)
+MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA,	0x064C, 0x0264, 2, 0x0864, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__KEY_ROW3,	0x064C, 0x0264, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__I2C2_SDA,	0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13,	0x064C, 0x0264, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT,	0x064C, 0x0264, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX,	0x0650, 0x0268, 0, 0x07CC, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5,	0x0650, 0x0268, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR,	0x0650, 0x0268, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__KEY_ROW4,	0x0650, 0x0268, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B,	0x0650, 0x0268, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B,	0x0650, 0x0268, 4, 0x0918, 3, 0)
+MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15,	0x0650, 0x0268, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__NAND_ALE,	0x0654, 0x026C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__SD4_RESET,	0x0654, 0x026C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08,	0x0654, 0x026C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__NAND_CLE,	0x0658, 0x0270, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07,	0x0658, 0x0270, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B,	0x065C, 0x0274, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11,	0x065C, 0x0274, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B,	0x0660, 0x0278, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT,	0x0660, 0x0278, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT,	0x0660, 0x0278, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14,	0x0660, 0x0278, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B,	0x0664, 0x027C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0,	0x0664, 0x027C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__ESAI_TX0,	0x0664, 0x027C, 2, 0x0844, 1, 0)
+MX6_PAD_DECL(NANDF_CS2__EIM_CRE,	0x0664, 0x027C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2,	0x0664, 0x027C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15,	0x0664, 0x027C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B,	0x0668, 0x0280, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1,	0x0668, 0x0280, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__ESAI_TX1,	0x0668, 0x0280, 2, 0x0848, 1, 0)
+MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26,	0x0668, 0x0280, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16,	0x0668, 0x0280, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__I2C4_SDA,	0x0668, 0x0280, 9 | IOMUX_CONFIG_SION, 0x0884, 2, 0)
+MX6_PAD_DECL(NANDF_D0__NAND_DATA00,	0x066C, 0x0284, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__SD1_DATA4,	0x066C, 0x0284, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__GPIO2_IO00,	0x066C, 0x0284, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__NAND_DATA01,	0x0670, 0x0288, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__SD1_DATA5,	0x0670, 0x0288, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__GPIO2_IO01,	0x0670, 0x0288, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__NAND_DATA02,	0x0674, 0x028C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__SD1_DATA6,	0x0674, 0x028C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__GPIO2_IO02,	0x0674, 0x028C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__NAND_DATA03,	0x0678, 0x0290, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__SD1_DATA7,	0x0678, 0x0290, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__GPIO2_IO03,	0x0678, 0x0290, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__NAND_DATA04,	0x067C, 0x0294, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__SD2_DATA4,	0x067C, 0x0294, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__GPIO2_IO04,	0x067C, 0x0294, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__NAND_DATA05,	0x0680, 0x0298, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__SD2_DATA5,	0x0680, 0x0298, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__GPIO2_IO05,	0x0680, 0x0298, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__NAND_DATA06,	0x0684, 0x029C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__SD2_DATA6,	0x0684, 0x029C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__GPIO2_IO06,	0x0684, 0x029C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__NAND_DATA07,	0x0688, 0x02A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__SD2_DATA7,	0x0688, 0x02A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__GPIO2_IO07,	0x0688, 0x02A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__NAND_READY_B,	0x068C, 0x02A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10,	0x068C, 0x02A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B,	0x0690, 0x02A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09,	0x0690, 0x02A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__I2C4_SCL,	0x0690, 0x02A8, 9 | IOMUX_CONFIG_SION, 0x0880, 2, 0)
+MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY,	0x0694, 0x02AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__RGMII_RD0,	0x0694, 0x02AC, 1, 0x0818, 1, 0)
+MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25,	0x0694, 0x02AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG,	0x0698, 0x02B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__RGMII_RD1,	0x0698, 0x02B0, 1, 0x081C, 1, 0)
+MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27,	0x0698, 0x02B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA,	0x069C, 0x02B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__RGMII_RD2,	0x069C, 0x02B4, 1, 0x0820, 1, 0)
+MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28,	0x069C, 0x02B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE,	0x06A0, 0x02B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__RGMII_RD3,	0x06A0, 0x02B8, 1, 0x0824, 1, 0)
+MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29,	0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA,	0x06A4, 0x02BC, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL,	0x06A4, 0x02BC, 1, 0x0828, 1, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24,	0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__USBOH3_H3_STROBE,	0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE,	0x06A8, 0x02C0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP)
+MX6_PAD_DECL(RGMII_RXC__RGMII_RXC,	0x06A8, 0x02C0, 1, 0x0814, 1, 0)
+MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30,	0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY,	0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__RGMII_TD0,	0x06AC, 0x02C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20,	0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG,	0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__RGMII_TD1,	0x06B0, 0x02C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21,	0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA,	0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__RGMII_TD2,	0x06B4, 0x02CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22,	0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE,	0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__RGMII_TD3,	0x06B8, 0x02D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23,	0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__USBOH3_H2_STROBE,	0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE,	0x06BC, 0x02D4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, PAD_CTL_PUS_47K_UP)
+MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL,	0x06BC, 0x02D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26,	0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK,	0x06BC, 0x02D4, 7 | IOMUX_CONFIG_SION, 0x080C, 1, 0)
+MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA,	0x06C0, 0x02D8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__RGMII_TXC,	0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK,	0x06C0, 0x02D8, 2, 0x08F4, 1, 0)
+MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19,	0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M,	0x06C0, 0x02D8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__SD1_CLK,	0x06C4, 0x02DC, 0, 0x0928, 1, 0)
+MX6_PAD_DECL(SD1_CLK__GPT_CLKIN,	0x06C4, 0x02DC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__GPIO1_IO20,	0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__SD1_CMD,	0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__PWM4_OUT,	0x06C8, 0x02E0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1,	0x06C8, 0x02E0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPIO1_IO18,	0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__SD1_DATA0,	0x06CC, 0x02E4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1,	0x06CC, 0x02E4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16,	0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__SD1_DATA1,	0x06D0, 0x02E8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__PWM3_OUT,	0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2,	0x06D0, 0x02E8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17,	0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__SD1_DATA2,	0x06D4, 0x02EC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2,	0x06D4, 0x02EC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__PWM2_OUT,	0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_B,	0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19,	0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB,	0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__SD1_DATA3,	0x06D8, 0x02F0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3,	0x06D8, 0x02F0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__PWM1_OUT,	0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_B,	0x06D8, 0x02F0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21,	0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB,	0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CLK__SD2_CLK,	0x06DC, 0x02F4, 0, 0x0930, 1, 0)
+MX6_PAD_DECL(SD2_CLK__KEY_COL5,	0x06DC, 0x02F4, 2, 0x08C0, 3, 0)
+MX6_PAD_DECL(SD2_CLK__AUD4_RXFS,	0x06DC, 0x02F4, 3, 0x07A4, 1, 0)
+MX6_PAD_DECL(SD2_CLK__GPIO1_IO10,	0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__SD2_CMD,	0x06E0, 0x02F8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__KEY_ROW5,	0x06E0, 0x02F8, 2, 0x08CC, 2, 0)
+MX6_PAD_DECL(SD2_CMD__AUD4_RXC,	0x06E0, 0x02F8, 3, 0x07A0, 1, 0)
+MX6_PAD_DECL(SD2_CMD__GPIO1_IO11,	0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__SD2_DATA0,	0x06E4, 0x02FC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__AUD4_RXD,	0x06E4, 0x02FC, 3, 0x0798, 1, 0)
+MX6_PAD_DECL(SD2_DAT0__KEY_ROW7,	0x06E4, 0x02FC, 4, 0x08D4, 2, 0)
+MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15,	0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT,	0x06E4, 0x02FC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__SD2_DATA1,	0x06E8, 0x0300, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B,	0x06E8, 0x0300, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS,	0x06E8, 0x0300, 3, 0x07AC, 1, 0)
+MX6_PAD_DECL(SD2_DAT1__KEY_COL7,	0x06E8, 0x0300, 4, 0x08C8, 2, 0)
+MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14,	0x06E8, 0x0300, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__SD2_DATA2,	0x06EC, 0x0304, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B,	0x06EC, 0x0304, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__AUD4_TXD,	0x06EC, 0x0304, 3, 0x079C, 1, 0)
+MX6_PAD_DECL(SD2_DAT2__KEY_ROW6,	0x06EC, 0x0304, 4, 0x08D0, 2, 0)
+MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13,	0x06EC, 0x0304, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__SD2_DATA3,	0x06F0, 0x0308, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__KEY_COL6,	0x06F0, 0x0308, 2, 0x08C4, 2, 0)
+MX6_PAD_DECL(SD2_DAT3__AUD4_TXC,	0x06F0, 0x0308, 3, 0x07A8, 1, 0)
+MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12,	0x06F0, 0x0308, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__SD3_CLK,	0x06F4, 0x030C, 0, 0x0934, 1, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_CTS_B,	0x06F4, 0x030C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_RTS_B,	0x06F4, 0x030C, 1, 0x0900, 2, 0)
+MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX,	0x06F4, 0x030C, 2, 0x07C8, 2, 0)
+MX6_PAD_DECL(SD3_CLK__GPIO7_IO03,	0x06F4, 0x030C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__SD3_CMD,	0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_CTS_B,	0x06F8, 0x0310, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_RTS_B,	0x06F8, 0x0310, 1, 0x0900, 3, 0)
+MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX,	0x06F8, 0x0310, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__GPIO7_IO02,	0x06F8, 0x0310, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__SD3_DATA0,	0x06FC, 0x0314, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B,	0x06FC, 0x0314, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B,	0x06FC, 0x0314, 1, 0x08F8, 2, 0)
+MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX,	0x06FC, 0x0314, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04,	0x06FC, 0x0314, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__SD3_DATA1,	0x0700, 0x0318, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B,	0x0700, 0x0318, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B,	0x0700, 0x0318, 1, 0x08F8, 3, 0)
+MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX,	0x0700, 0x0318, 2, 0x07CC, 1, 0)
+MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05,	0x0700, 0x0318, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__SD3_DATA2,	0x0704, 0x031C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06,	0x0704, 0x031C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__SD3_DATA3,	0x0708, 0x0320, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B,	0x0708, 0x0320, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B,	0x0708, 0x0320, 1, 0x0908, 4, 0)
+MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07,	0x0708, 0x0320, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__SD3_DATA4,	0x070C, 0x0324, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA,	0x070C, 0x0324, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA,	0x070C, 0x0324, 1, 0x0904, 4, 0)
+MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01,	0x070C, 0x0324, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__SD3_DATA5,	0x0710, 0x0328, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA,	0x0710, 0x0328, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA,	0x0710, 0x0328, 1, 0x0904, 5, 0)
+MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00,	0x0710, 0x0328, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__SD3_DATA6,	0x0714, 0x032C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA,	0x0714, 0x032C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA,	0x0714, 0x032C, 1, 0x08FC, 2, 0)
+MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18,	0x0714, 0x032C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__SD3_DATA7,	0x0718, 0x0330, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA,	0x0718, 0x0330, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA,	0x0718, 0x0330, 1, 0x08FC, 3, 0)
+MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17,	0x0718, 0x0330, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__SD3_RESET,	0x071C, 0x0334, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_CTS_B,	0x071C, 0x0334, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_RTS_B,	0x071C, 0x0334, 1, 0x0908, 5, 0)
+MX6_PAD_DECL(SD3_RST__GPIO7_IO08,	0x071C, 0x0334, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__SD4_CLK,	0x0720, 0x0338, 0, 0x0938, 1, 0)
+MX6_PAD_DECL(SD4_CLK__NAND_WE_B,	0x0720, 0x0338, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA,	0x0720, 0x0338, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA,	0x0720, 0x0338, 2, 0x090C, 2, 0)
+MX6_PAD_DECL(SD4_CLK__GPIO7_IO10,	0x0720, 0x0338, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__SD4_CMD,	0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__NAND_RE_B,	0x0724, 0x033C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA,	0x0724, 0x033C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA,	0x0724, 0x033C, 2, 0x090C, 3, 0)
+MX6_PAD_DECL(SD4_CMD__GPIO7_IO09,	0x0724, 0x033C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__SD4_DATA0,	0x0728, 0x0340, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__NAND_DQS,	0x0728, 0x0340, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08,	0x0728, 0x0340, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__SD4_DATA1,	0x072C, 0x0344, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__PWM3_OUT,	0x072C, 0x0344, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09,	0x072C, 0x0344, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__SD4_DATA2,	0x0730, 0x0348, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__PWM4_OUT,	0x0730, 0x0348, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10,	0x0730, 0x0348, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__SD4_DATA3,	0x0734, 0x034C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11,	0x0734, 0x034C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__SD4_DATA4,	0x0738, 0x0350, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA,	0x0738, 0x0350, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA,	0x0738, 0x0350, 2, 0x0904, 6, 0)
+MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12,	0x0738, 0x0350, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__SD4_DATA5,	0x073C, 0x0354, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B,	0x073C, 0x0354, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B,	0x073C, 0x0354, 2, 0x0900, 4, 0)
+MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13,	0x073C, 0x0354, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__SD4_DATA6,	0x0740, 0x0358, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B,	0x0740, 0x0358, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B,	0x0740, 0x0358, 2, 0x0900, 5, 0)
+MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14,	0x0740, 0x0358, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__SD4_DATA7,	0x0744, 0x035C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA,	0x0744, 0x035C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA,	0x0744, 0x035C, 2, 0x0904, 7, 0)
+MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15,	0x0744, 0x035C, 5, 0x0000, 0, 0)
+
+#endif	/* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
new file mode 100644
index 0000000..c76a920
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Boundary Devices Inc.
+ */
+#ifndef __ASM_ARCH_MX6Q_DDR_H__
+#define __ASM_ARCH_MX6Q_DDR_H__
+
+#ifndef CONFIG_MX6Q
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_DQM0	0x020e05ac
+#define MX6_IOM_DRAM_DQM1	0x020e05b4
+#define MX6_IOM_DRAM_DQM2	0x020e0528
+#define MX6_IOM_DRAM_DQM3	0x020e0520
+#define MX6_IOM_DRAM_DQM4	0x020e0514
+#define MX6_IOM_DRAM_DQM5	0x020e0510
+#define MX6_IOM_DRAM_DQM6	0x020e05bc
+#define MX6_IOM_DRAM_DQM7	0x020e05c4
+
+#define MX6_IOM_DRAM_CAS	0x020e056c
+#define MX6_IOM_DRAM_RAS	0x020e0578
+#define MX6_IOM_DRAM_RESET	0x020e057c
+#define MX6_IOM_DRAM_SDCLK_0	0x020e0588
+#define MX6_IOM_DRAM_SDCLK_1	0x020e0594
+#define MX6_IOM_DRAM_SDBA2	0x020e058c
+#define MX6_IOM_DRAM_SDCKE0	0x020e0590
+#define MX6_IOM_DRAM_SDCKE1	0x020e0598
+#define MX6_IOM_DRAM_SDODT0	0x020e059c
+#define MX6_IOM_DRAM_SDODT1	0x020e05a0
+
+#define MX6_IOM_DRAM_SDQS0	0x020e05a8
+#define MX6_IOM_DRAM_SDQS1	0x020e05b0
+#define MX6_IOM_DRAM_SDQS2	0x020e0524
+#define MX6_IOM_DRAM_SDQS3	0x020e051c
+#define MX6_IOM_DRAM_SDQS4	0x020e0518
+#define MX6_IOM_DRAM_SDQS5	0x020e050c
+#define MX6_IOM_DRAM_SDQS6	0x020e05b8
+#define MX6_IOM_DRAM_SDQS7	0x020e05c0
+
+#define MX6_IOM_GRP_B0DS	0x020e0784
+#define MX6_IOM_GRP_B1DS	0x020e0788
+#define MX6_IOM_GRP_B2DS	0x020e0794
+#define MX6_IOM_GRP_B3DS	0x020e079c
+#define MX6_IOM_GRP_B4DS	0x020e07a0
+#define MX6_IOM_GRP_B5DS	0x020e07a4
+#define MX6_IOM_GRP_B6DS	0x020e07a8
+#define MX6_IOM_GRP_B7DS	0x020e0748
+#define MX6_IOM_GRP_ADDDS	0x020e074c
+#define MX6_IOM_DDRMODE_CTL	0x020e0750
+#define MX6_IOM_GRP_DDRPKE	0x020e0758
+#define MX6_IOM_GRP_DDRMODE	0x020e0774
+#define MX6_IOM_GRP_CTLDS	0x020e078c
+#define MX6_IOM_GRP_DDR_TYPE	0x020e0798
+
+#endif	/*__ASM_ARCH_MX6Q_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
new file mode 100644
index 0000000..dce13d0
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -0,0 +1,1035 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Auto Generate file, please don't edit it
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6Q_PINS_H__
+#define __ASM_ARCH_MX6_MX6Q_PINS_H__
+
+MX6_PAD_DECL(SD2_DAT1__SD2_DATA1,	0x0360, 0x004C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__ECSPI5_SS0,	0x0360, 0x004C, 1, 0x0834, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__EIM_CS2_B,	0x0360, 0x004C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__AUD4_TXFS,	0x0360, 0x004C, 3, 0x07C8, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__KEY_COL7,	0x0360, 0x004C, 4, 0x08F0, 0, 0)
+MX6_PAD_DECL(SD2_DAT1__GPIO1_IO14,	0x0360, 0x004C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__SD2_DATA2,	0x0364, 0x0050, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__ECSPI5_SS1,	0x0364, 0x0050, 1, 0x0838, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__EIM_CS3_B,	0x0364, 0x0050, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__AUD4_TXD,	0x0364, 0x0050, 3, 0x07B8, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__KEY_ROW6,	0x0364, 0x0050, 4, 0x08F8, 0, 0)
+MX6_PAD_DECL(SD2_DAT2__GPIO1_IO13,	0x0364, 0x0050, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__SD2_DATA0,	0x0368, 0x0054, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__ECSPI5_MISO,	0x0368, 0x0054, 1, 0x082C, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__AUD4_RXD,	0x0368, 0x0054, 3, 0x07B4, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__KEY_ROW7,	0x0368, 0x0054, 4, 0x08FC, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__GPIO1_IO15,	0x0368, 0x0054, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT0__DCIC2_OUT,	0x0368, 0x0054, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__USB_H2_DATA,	0x036C, 0x0058, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__RGMII_TXC,	0x036C, 0x0058, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__SPDIF_EXT_CLK,	0x036C, 0x0058, 2, 0x0918, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__GPIO6_IO19,	0x036C, 0x0058, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TXC__XTALOSC_REF_CLK_24M,	0x036C, 0x0058, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__HSI_TX_READY,	0x0370, 0x005C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__RGMII_TD0,	0x0370, 0x005C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD0__GPIO6_IO20,	0x0370, 0x005C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__HSI_RX_FLAG,	0x0374, 0x0060, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__RGMII_TD1,	0x0374, 0x0060, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD1__GPIO6_IO21,	0x0374, 0x0060, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__HSI_RX_DATA,	0x0378, 0x0064, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__RGMII_TD2,	0x0378, 0x0064, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD2__GPIO6_IO22,	0x0378, 0x0064, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__HSI_RX_WAKE,	0x037C, 0x0068, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__RGMII_TD3,	0x037C, 0x0068, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TD3__GPIO6_IO23,	0x037C, 0x0068, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__USB_H3_DATA,	0x0380, 0x006C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__RGMII_RX_CTL,	0x0380, 0x006C, 1, 0x0858, 0, 0)
+MX6_PAD_DECL(RGMII_RX_CTL__GPIO6_IO24,	0x0380, 0x006C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__HSI_RX_READY,	0x0384, 0x0070, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__RGMII_RD0,	0x0384, 0x0070, 1, 0x0848, 0, 0)
+MX6_PAD_DECL(RGMII_RD0__GPIO6_IO25,	0x0384, 0x0070, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__USB_H2_STROBE,	0x0388, 0x0074, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__RGMII_TX_CTL,	0x0388, 0x0074, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__GPIO6_IO26,	0x0388, 0x0074, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_TX_CTL__ENET_REF_CLK,	0x0388, 0x0074, 7 | IOMUX_CONFIG_SION, 0x083C, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__HSI_TX_FLAG,	0x038C, 0x0078, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__RGMII_RD1,	0x038C, 0x0078, 1, 0x084C, 0, 0)
+MX6_PAD_DECL(RGMII_RD1__GPIO6_IO27,	0x038C, 0x0078, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__HSI_TX_DATA,	0x0390, 0x007C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__RGMII_RD2,	0x0390, 0x007C, 1, 0x0850, 0, 0)
+MX6_PAD_DECL(RGMII_RD2__GPIO6_IO28,	0x0390, 0x007C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__HSI_TX_WAKE,	0x0394, 0x0080, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__RGMII_RD3,	0x0394, 0x0080, 1, 0x0854, 0, 0)
+MX6_PAD_DECL(RGMII_RD3__GPIO6_IO29,	0x0394, 0x0080, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__USB_H3_STROBE,	0x0398, 0x0084, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__RGMII_RXC,	0x0398, 0x0084, 1, 0x0844, 0, 0)
+MX6_PAD_DECL(RGMII_RXC__GPIO6_IO30,	0x0398, 0x0084, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__EIM_ADDR25,	0x039C, 0x0088, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI4_SS1,	0x039C, 0x0088, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__ECSPI2_RDY,	0x039C, 0x0088, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI1_PIN12,	0x039C, 0x0088, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__IPU1_DI0_D1_CS,	0x039C, 0x0088, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__GPIO5_IO02,	0x039C, 0x0088, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A25__HDMI_TX_CEC_LINE,	0x039C, 0x0088, 6, 0x088C, 0, 0)
+MX6_PAD_DECL(EIM_EB2__EIM_EB2_B,	0x03A0, 0x008C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__ECSPI1_SS0,	0x03A0, 0x008C, 1, 0x0800, 0, 0)
+MX6_PAD_DECL(EIM_EB2__IPU2_CSI1_DATA19,	0x03A0, 0x008C, 3, 0x08D4, 0, 0)
+MX6_PAD_DECL(EIM_EB2__HDMI_TX_DDC_SCL,	0x03A0, 0x008C, 4, 0x0890, 0, 0)
+MX6_PAD_DECL(EIM_EB2__GPIO2_IO30,	0x03A0, 0x008C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB2__I2C2_SCL,	0x03A0, 0x008C, 22, 0x08A0, 0, 0)
+MX6_PAD_DECL(EIM_EB2__SRC_BOOT_CFG30,	0x03A0, 0x008C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__EIM_DATA16,	0x03A4, 0x0090, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__ECSPI1_SCLK,	0x03A4, 0x0090, 1, 0x07F4, 0, 0)
+MX6_PAD_DECL(EIM_D16__IPU1_DI0_PIN05,	0x03A4, 0x0090, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__IPU2_CSI1_DATA18,	0x03A4, 0x0090, 3, 0x08D0, 0, 0)
+MX6_PAD_DECL(EIM_D16__HDMI_TX_DDC_SDA,	0x03A4, 0x0090, 4, 0x0894, 0, 0)
+MX6_PAD_DECL(EIM_D16__GPIO3_IO16,	0x03A4, 0x0090, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D16__I2C2_SDA,	0x03A4, 0x0090, 22, 0x08A4, 0, 0)
+MX6_PAD_DECL(EIM_D17__EIM_DATA17,	0x03A8, 0x0094, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__ECSPI1_MISO,	0x03A8, 0x0094, 1, 0x07F8, 0, 0)
+MX6_PAD_DECL(EIM_D17__IPU1_DI0_PIN06,	0x03A8, 0x0094, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__IPU2_CSI1_PIXCLK,	0x03A8, 0x0094, 3, 0x08E0, 0, 0)
+MX6_PAD_DECL(EIM_D17__DCIC1_OUT,	0x03A8, 0x0094, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__GPIO3_IO17,	0x03A8, 0x0094, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D17__I2C3_SCL,	0x03A8, 0x0094, 22, 0x08A8, 0, 0)
+MX6_PAD_DECL(EIM_D18__EIM_DATA18,	0x03AC, 0x0098, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__ECSPI1_MOSI,	0x03AC, 0x0098, 1, 0x07FC, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI0_PIN07,	0x03AC, 0x0098, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU2_CSI1_DATA17,	0x03AC, 0x0098, 3, 0x08CC, 0, 0)
+MX6_PAD_DECL(EIM_D18__IPU1_DI1_D0_CS,	0x03AC, 0x0098, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__GPIO3_IO18,	0x03AC, 0x0098, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D18__I2C3_SDA,	0x03AC, 0x0098, 22, 0x08AC, 0, 0)
+MX6_PAD_DECL(EIM_D19__EIM_DATA19,	0x03B0, 0x009C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__ECSPI1_SS1,	0x03B0, 0x009C, 1, 0x0804, 0, 0)
+MX6_PAD_DECL(EIM_D19__IPU1_DI0_PIN08,	0x03B0, 0x009C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__IPU2_CSI1_DATA16,	0x03B0, 0x009C, 3, 0x08C8, 0, 0)
+MX6_PAD_DECL(EIM_D19__UART1_CTS_B,	0x03B0, 0x009C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__UART1_RTS_B,	0x03B0, 0x009C, 4, 0x091C, 0, 0)
+MX6_PAD_DECL(EIM_D19__GPIO3_IO19,	0x03B0, 0x009C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D19__EPIT1_OUT,	0x03B0, 0x009C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EIM_DATA20,	0x03B4, 0x00A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__ECSPI4_SS0,	0x03B4, 0x00A0, 1, 0x0824, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU1_DI0_PIN16,	0x03B4, 0x00A0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__IPU2_CSI1_DATA15,	0x03B4, 0x00A0, 3, 0x08C4, 0, 0)
+MX6_PAD_DECL(EIM_D20__UART1_CTS_B,	0x03B4, 0x00A0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__UART1_RTS_B,	0x03B4, 0x00A0, 4, 0x091C, 1, 0)
+MX6_PAD_DECL(EIM_D20__GPIO3_IO20,	0x03B4, 0x00A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D20__EPIT2_OUT,	0x03B4, 0x00A0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__EIM_DATA21,	0x03B8, 0x00A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__ECSPI4_SCLK,	0x03B8, 0x00A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU1_DI0_PIN17,	0x03B8, 0x00A4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__IPU2_CSI1_DATA11,	0x03B8, 0x00A4, 3, 0x08B4, 0, 0)
+MX6_PAD_DECL(EIM_D21__USB_OTG_OC,	0x03B8, 0x00A4, 4, 0x0944, 0, 0)
+MX6_PAD_DECL(EIM_D21__GPIO3_IO21,	0x03B8, 0x00A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D21__I2C1_SCL,	0x03B8, 0x00A4, 22, 0x0898, 0, 0)
+MX6_PAD_DECL(EIM_D21__SPDIF_IN,	0x03B8, 0x00A4, 7, 0x0914, 0, 0)
+MX6_PAD_DECL(EIM_D22__EIM_DATA22,	0x03BC, 0x00A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__ECSPI4_MISO,	0x03BC, 0x00A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU1_DI0_PIN01,	0x03BC, 0x00A8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__IPU2_CSI1_DATA10,	0x03BC, 0x00A8, 3, 0x08B0, 0, 0)
+MX6_PAD_DECL(EIM_D22__USB_OTG_PWR,	0x03BC, 0x00A8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__GPIO3_IO22,	0x03BC, 0x00A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D22__SPDIF_OUT,	0x03BC, 0x00A8, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__EIM_DATA23,	0x03C0, 0x00AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI0_D0_CS,	0x03C0, 0x00AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_CTS_B,	0x03C0, 0x00AC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART3_RTS_B,	0x03C0, 0x00AC, 2, 0x092C, 0, 0)
+MX6_PAD_DECL(EIM_D23__UART1_DCD_B,	0x03C0, 0x00AC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU2_CSI1_DATA_EN,	0x03C0, 0x00AC, 4, 0x08D8, 0, 0)
+MX6_PAD_DECL(EIM_D23__GPIO3_IO23,	0x03C0, 0x00AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN02,	0x03C0, 0x00AC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D23__IPU1_DI1_PIN14,	0x03C0, 0x00AC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__EIM_EB3_B,	0x03C4, 0x00B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__ECSPI4_RDY,	0x03C4, 0x00B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_CTS_B,	0x03C4, 0x00B0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__UART3_RTS_B,	0x03C4, 0x00B0, 2, 0x092C, 1, 0)
+MX6_PAD_DECL(EIM_EB3__UART1_RI_B,	0x03C4, 0x00B0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU2_CSI1_HSYNC,	0x03C4, 0x00B0, 4, 0x08DC, 0, 0)
+MX6_PAD_DECL(EIM_EB3__GPIO2_IO31,	0x03C4, 0x00B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__IPU1_DI1_PIN03,	0x03C4, 0x00B0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB3__SRC_BOOT_CFG31,	0x03C4, 0x00B0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__EIM_DATA24,	0x03C8, 0x00B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI4_SS2,	0x03C8, 0x00B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_TX_DATA,	0x03C8, 0x00B4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART3_RX_DATA,	0x03C8, 0x00B4, 2, 0x0930, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI1_SS2,	0x03C8, 0x00B4, 3, 0x0808, 0, 0)
+MX6_PAD_DECL(EIM_D24__ECSPI2_SS2,	0x03C8, 0x00B4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__GPIO3_IO24,	0x03C8, 0x00B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D24__AUD5_RXFS,	0x03C8, 0x00B4, 6, 0x07D8, 0, 0)
+MX6_PAD_DECL(EIM_D24__UART1_DTR_B,	0x03C8, 0x00B4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__EIM_DATA25,	0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI4_SS3,	0x03CC, 0x00B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_TX_DATA,	0x03CC, 0x00B8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART3_RX_DATA,	0x03CC, 0x00B8, 2, 0x0930, 1, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI1_SS3,	0x03CC, 0x00B8, 3, 0x080C, 0, 0)
+MX6_PAD_DECL(EIM_D25__ECSPI2_SS3,	0x03CC, 0x00B8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__GPIO3_IO25,	0x03CC, 0x00B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D25__AUD5_RXC,	0x03CC, 0x00B8, 6, 0x07D4, 0, 0)
+MX6_PAD_DECL(EIM_D25__UART1_DSR_B,	0x03CC, 0x00B8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__EIM_DATA26,	0x03D0, 0x00BC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DI1_PIN11,	0x03D0, 0x00BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_CSI0_DATA01,	0x03D0, 0x00BC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU2_CSI1_DATA14,	0x03D0, 0x00BC, 3, 0x08C0, 0, 0)
+MX6_PAD_DECL(EIM_D26__UART2_TX_DATA,	0x03D0, 0x00BC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__UART2_RX_DATA,	0x03D0, 0x00BC, 4, 0x0928, 0, 0)
+MX6_PAD_DECL(EIM_D26__GPIO3_IO26,	0x03D0, 0x00BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_SISG2,	0x03D0, 0x00BC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D26__IPU1_DISP1_DATA22,	0x03D0, 0x00BC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__EIM_DATA27,	0x03D4, 0x00C0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DI1_PIN13,	0x03D4, 0x00C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_CSI0_DATA00,	0x03D4, 0x00C0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU2_CSI1_DATA13,	0x03D4, 0x00C0, 3, 0x08BC, 0, 0)
+MX6_PAD_DECL(EIM_D27__UART2_TX_DATA,	0x03D4, 0x00C0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__UART2_RX_DATA,	0x03D4, 0x00C0, 4, 0x0928, 1, 0)
+MX6_PAD_DECL(EIM_D27__GPIO3_IO27,	0x03D4, 0x00C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_SISG3,	0x03D4, 0x00C0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D27__IPU1_DISP1_DATA23,	0x03D4, 0x00C0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__EIM_DATA28,	0x03D8, 0x00C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__I2C1_SDA,	0x03D8, 0x00C4, 17, 0x089C, 0, 0)
+MX6_PAD_DECL(EIM_D28__ECSPI4_MOSI,	0x03D8, 0x00C4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU2_CSI1_DATA12,	0x03D8, 0x00C4, 3, 0x08B8, 0, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_CTS_B,	0x03D8, 0x00C4, 4, 0x0924, 0, 0)
+MX6_PAD_DECL(EIM_D28__UART2_DTE_RTS_B,	0x03D8, 0x00C4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__GPIO3_IO28,	0x03D8, 0x00C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_EXT_TRIG,	0x03D8, 0x00C4, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D28__IPU1_DI0_PIN13,	0x03D8, 0x00C4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__EIM_DATA29,	0x03DC, 0x00C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI1_PIN15,	0x03DC, 0x00C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__ECSPI4_SS0,	0x03DC, 0x00C8, 2, 0x0824, 1, 0)
+MX6_PAD_DECL(EIM_D29__UART2_CTS_B,	0x03DC, 0x00C8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__UART2_RTS_B,	0x03DC, 0x00C8, 4, 0x0924, 1, 0)
+MX6_PAD_DECL(EIM_D29__GPIO3_IO29,	0x03DC, 0x00C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU2_CSI1_VSYNC,	0x03DC, 0x00C8, 6, 0x08E4, 0, 0)
+MX6_PAD_DECL(EIM_D29__IPU1_DI0_PIN14,	0x03DC, 0x00C8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__EIM_DATA30,	0x03E0, 0x00CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DISP1_DATA21,	0x03E0, 0x00CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_DI0_PIN11,	0x03E0, 0x00CC, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__IPU1_CSI0_DATA03,	0x03E0, 0x00CC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_CTS_B,	0x03E0, 0x00CC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__UART3_RTS_B,	0x03E0, 0x00CC, 4, 0x092C, 2, 0)
+MX6_PAD_DECL(EIM_D30__GPIO3_IO30,	0x03E0, 0x00CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D30__USB_H1_OC,	0x03E0, 0x00CC, 6, 0x0948, 0, 0)
+MX6_PAD_DECL(EIM_D31__EIM_DATA31,	0x03E4, 0x00D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DISP1_DATA20,	0x03E4, 0x00D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_DI0_PIN12,	0x03E4, 0x00D0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__IPU1_CSI0_DATA02,	0x03E4, 0x00D0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_CTS_B,	0x03E4, 0x00D0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__UART3_RTS_B,	0x03E4, 0x00D0, 4, 0x092C, 3, 0)
+MX6_PAD_DECL(EIM_D31__GPIO3_IO31,	0x03E4, 0x00D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_D31__USB_H1_PWR,	0x03E4, 0x00D0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__EIM_ADDR24,	0x03E8, 0x00D4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_DISP1_DATA19,	0x03E8, 0x00D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU2_CSI1_DATA19,	0x03E8, 0x00D4, 2, 0x08D4, 1, 0)
+MX6_PAD_DECL(EIM_A24__IPU2_SISG2,	0x03E8, 0x00D4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__IPU1_SISG2,	0x03E8, 0x00D4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__GPIO5_IO04,	0x03E8, 0x00D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A24__SRC_BOOT_CFG24,	0x03E8, 0x00D4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__EIM_ADDR23,	0x03EC, 0x00D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_DISP1_DATA18,	0x03EC, 0x00D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU2_CSI1_DATA18,	0x03EC, 0x00D8, 2, 0x08D0, 1, 0)
+MX6_PAD_DECL(EIM_A23__IPU2_SISG3,	0x03EC, 0x00D8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__IPU1_SISG3,	0x03EC, 0x00D8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__GPIO6_IO06,	0x03EC, 0x00D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A23__SRC_BOOT_CFG23,	0x03EC, 0x00D8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__EIM_ADDR22,	0x03F0, 0x00DC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU1_DISP1_DATA17,	0x03F0, 0x00DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__IPU2_CSI1_DATA17,	0x03F0, 0x00DC, 2, 0x08CC, 1, 0)
+MX6_PAD_DECL(EIM_A22__GPIO2_IO16,	0x03F0, 0x00DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A22__SRC_BOOT_CFG22,	0x03F0, 0x00DC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__EIM_ADDR21,	0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU1_DISP1_DATA16,	0x03F4, 0x00E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__IPU2_CSI1_DATA16,	0x03F4, 0x00E0, 2, 0x08C8, 1, 0)
+MX6_PAD_DECL(EIM_A21__GPIO2_IO17,	0x03F4, 0x00E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A21__SRC_BOOT_CFG21,	0x03F4, 0x00E0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__EIM_ADDR20,	0x03F8, 0x00E4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU1_DISP1_DATA15,	0x03F8, 0x00E4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__IPU2_CSI1_DATA15,	0x03F8, 0x00E4, 2, 0x08C4, 1, 0)
+MX6_PAD_DECL(EIM_A20__GPIO2_IO18,	0x03F8, 0x00E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A20__SRC_BOOT_CFG20,	0x03F8, 0x00E4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__EIM_ADDR19,	0x03FC, 0x00E8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU1_DISP1_DATA14,	0x03FC, 0x00E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__IPU2_CSI1_DATA14,	0x03FC, 0x00E8, 2, 0x08C0, 1, 0)
+MX6_PAD_DECL(EIM_A19__GPIO2_IO19,	0x03FC, 0x00E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A19__SRC_BOOT_CFG19,	0x03FC, 0x00E8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__EIM_ADDR18,	0x0400, 0x00EC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU1_DISP1_DATA13,	0x0400, 0x00EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__IPU2_CSI1_DATA13,	0x0400, 0x00EC, 2, 0x08BC, 1, 0)
+MX6_PAD_DECL(EIM_A18__GPIO2_IO20,	0x0400, 0x00EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A18__SRC_BOOT_CFG18,	0x0400, 0x00EC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__EIM_ADDR17,	0x0404, 0x00F0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU1_DISP1_DATA12,	0x0404, 0x00F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__IPU2_CSI1_DATA12,	0x0404, 0x00F0, 2, 0x08B8, 1, 0)
+MX6_PAD_DECL(EIM_A17__GPIO2_IO21,	0x0404, 0x00F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A17__SRC_BOOT_CFG17,	0x0404, 0x00F0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__EIM_ADDR16,	0x0408, 0x00F4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU1_DI1_DISP_CLK,	0x0408, 0x00F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__IPU2_CSI1_PIXCLK,	0x0408, 0x00F4, 2, 0x08E0, 1, 0)
+MX6_PAD_DECL(EIM_A16__GPIO2_IO22,	0x0408, 0x00F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_A16__SRC_BOOT_CFG16,	0x0408, 0x00F4, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__EIM_CS0_B,	0x040C, 0x00F8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__IPU1_DI1_PIN05,	0x040C, 0x00F8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS0__ECSPI2_SCLK,	0x040C, 0x00F8, 2, 0x0810, 0, 0)
+MX6_PAD_DECL(EIM_CS0__GPIO2_IO23,	0x040C, 0x00F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__EIM_CS1_B,	0x0410, 0x00FC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__IPU1_DI1_PIN06,	0x0410, 0x00FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_CS1__ECSPI2_MOSI,	0x0410, 0x00FC, 2, 0x0818, 0, 0)
+MX6_PAD_DECL(EIM_CS1__GPIO2_IO24,	0x0410, 0x00FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__EIM_OE_B,	0x0414, 0x0100, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__IPU1_DI1_PIN07,	0x0414, 0x0100, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_OE__ECSPI2_MISO,	0x0414, 0x0100, 2, 0x0814, 0, 0)
+MX6_PAD_DECL(EIM_OE__GPIO2_IO25,	0x0414, 0x0100, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__EIM_RW,	0x0418, 0x0104, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__IPU1_DI1_PIN08,	0x0418, 0x0104, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__ECSPI2_SS0,	0x0418, 0x0104, 2, 0x081C, 0, 0)
+MX6_PAD_DECL(EIM_RW__GPIO2_IO26,	0x0418, 0x0104, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_RW__SRC_BOOT_CFG29,	0x0418, 0x0104, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__EIM_LBA_B,	0x041C, 0x0108, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__IPU1_DI1_PIN17,	0x041C, 0x0108, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__ECSPI2_SS1,	0x041C, 0x0108, 2, 0x0820, 0, 0)
+MX6_PAD_DECL(EIM_LBA__GPIO2_IO27,	0x041C, 0x0108, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_LBA__SRC_BOOT_CFG26,	0x041C, 0x0108, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__EIM_EB0_B,	0x0420, 0x010C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU1_DISP1_DATA11,	0x0420, 0x010C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__IPU2_CSI1_DATA11,	0x0420, 0x010C, 2, 0x08B4, 1, 0)
+MX6_PAD_DECL(EIM_EB0__CCM_PMIC_READY,	0x0420, 0x010C, 4, 0x07F0, 0, 0)
+MX6_PAD_DECL(EIM_EB0__GPIO2_IO28,	0x0420, 0x010C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB0__SRC_BOOT_CFG27,	0x0420, 0x010C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__EIM_EB1_B,	0x0424, 0x0110, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU1_DISP1_DATA10,	0x0424, 0x0110, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__IPU2_CSI1_DATA10,	0x0424, 0x0110, 2, 0x08B0, 1, 0)
+MX6_PAD_DECL(EIM_EB1__GPIO2_IO29,	0x0424, 0x0110, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_EB1__SRC_BOOT_CFG28,	0x0424, 0x0110, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__EIM_AD00,	0x0428, 0x0114, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU1_DISP1_DATA09,	0x0428, 0x0114, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__IPU2_CSI1_DATA09,	0x0428, 0x0114, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__GPIO3_IO00,	0x0428, 0x0114, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA0__SRC_BOOT_CFG00,	0x0428, 0x0114, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__EIM_AD01,	0x042C, 0x0118, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU1_DISP1_DATA08,	0x042C, 0x0118, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__IPU2_CSI1_DATA08,	0x042C, 0x0118, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__GPIO3_IO01,	0x042C, 0x0118, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA1__SRC_BOOT_CFG01,	0x042C, 0x0118, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__EIM_AD02,	0x0430, 0x011C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU1_DISP1_DATA07,	0x0430, 0x011C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__IPU2_CSI1_DATA07,	0x0430, 0x011C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__GPIO3_IO02,	0x0430, 0x011C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA2__SRC_BOOT_CFG02,	0x0430, 0x011C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__EIM_AD03,	0x0434, 0x0120, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU1_DISP1_DATA06,	0x0434, 0x0120, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__IPU2_CSI1_DATA06,	0x0434, 0x0120, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__GPIO3_IO03,	0x0434, 0x0120, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA3__SRC_BOOT_CFG03,	0x0434, 0x0120, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__EIM_AD04,	0x0438, 0x0124, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU1_DISP1_DATA05,	0x0438, 0x0124, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__IPU2_CSI1_DATA05,	0x0438, 0x0124, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__GPIO3_IO04,	0x0438, 0x0124, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA4__SRC_BOOT_CFG04,	0x0438, 0x0124, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__EIM_AD05,	0x043C, 0x0128, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU1_DISP1_DATA04,	0x043C, 0x0128, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__IPU2_CSI1_DATA04,	0x043C, 0x0128, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__GPIO3_IO05,	0x043C, 0x0128, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA5__SRC_BOOT_CFG05,	0x043C, 0x0128, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__EIM_AD06,	0x0440, 0x012C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU1_DISP1_DATA03,	0x0440, 0x012C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__IPU2_CSI1_DATA03,	0x0440, 0x012C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__GPIO3_IO06,	0x0440, 0x012C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA6__SRC_BOOT_CFG06,	0x0440, 0x012C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__EIM_AD07,	0x0444, 0x0130, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU1_DISP1_DATA02,	0x0444, 0x0130, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__IPU2_CSI1_DATA02,	0x0444, 0x0130, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__GPIO3_IO07,	0x0444, 0x0130, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA7__SRC_BOOT_CFG07,	0x0444, 0x0130, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__EIM_AD08,	0x0448, 0x0134, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU1_DISP1_DATA01,	0x0448, 0x0134, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__IPU2_CSI1_DATA01,	0x0448, 0x0134, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__GPIO3_IO08,	0x0448, 0x0134, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA8__SRC_BOOT_CFG08,	0x0448, 0x0134, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__EIM_AD09,	0x044C, 0x0138, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU1_DISP1_DATA00,	0x044C, 0x0138, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__IPU2_CSI1_DATA00,	0x044C, 0x0138, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__GPIO3_IO09,	0x044C, 0x0138, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA9__SRC_BOOT_CFG09,	0x044C, 0x0138, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__EIM_AD10,	0x0450, 0x013C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU1_DI1_PIN15,	0x0450, 0x013C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__IPU2_CSI1_DATA_EN,	0x0450, 0x013C, 2, 0x08D8, 1, 0)
+MX6_PAD_DECL(EIM_DA10__GPIO3_IO10,	0x0450, 0x013C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA10__SRC_BOOT_CFG10,	0x0450, 0x013C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__EIM_AD11,	0x0454, 0x0140, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU1_DI1_PIN02,	0x0454, 0x0140, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__IPU2_CSI1_HSYNC,	0x0454, 0x0140, 2, 0x08DC, 1, 0)
+MX6_PAD_DECL(EIM_DA11__GPIO3_IO11,	0x0454, 0x0140, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA11__SRC_BOOT_CFG11,	0x0454, 0x0140, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__EIM_AD12,	0x0458, 0x0144, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU1_DI1_PIN03,	0x0458, 0x0144, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__IPU2_CSI1_VSYNC,	0x0458, 0x0144, 2, 0x08E4, 1, 0)
+MX6_PAD_DECL(EIM_DA12__GPIO3_IO12,	0x0458, 0x0144, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA12__SRC_BOOT_CFG12,	0x0458, 0x0144, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__EIM_AD13,	0x045C, 0x0148, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__IPU1_DI1_D0_CS,	0x045C, 0x0148, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__GPIO3_IO13,	0x045C, 0x0148, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA13__SRC_BOOT_CFG13,	0x045C, 0x0148, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__EIM_AD14,	0x0460, 0x014C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__IPU1_DI1_D1_CS,	0x0460, 0x014C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__GPIO3_IO14,	0x0460, 0x014C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA14__SRC_BOOT_CFG14,	0x0460, 0x014C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__EIM_AD15,	0x0464, 0x0150, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN01,	0x0464, 0x0150, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__IPU1_DI1_PIN04,	0x0464, 0x0150, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__GPIO3_IO15,	0x0464, 0x0150, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_DA15__SRC_BOOT_CFG15,	0x0464, 0x0150, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_WAIT_B,	0x0468, 0x0154, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__EIM_DTACK_B,	0x0468, 0x0154, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__GPIO5_IO00,	0x0468, 0x0154, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_WAIT__SRC_BOOT_CFG25,	0x0468, 0x0154, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__EIM_BCLK,	0x046C, 0x0158, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__IPU1_DI1_PIN16,	0x046C, 0x0158, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(EIM_BCLK__GPIO6_IO31,	0x046C, 0x0158, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK,	0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_DISP_CLK__IPU2_DI0_DISP_CLK,	0x0470, 0x015C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_DISP_CLK__GPIO4_IO16,	0x0470, 0x015C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__IPU1_DI0_PIN15,	0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN15__IPU2_DI0_PIN15,	0x0474, 0x0160, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__AUD6_TXC,	0x0474, 0x0160, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN15__GPIO4_IO17,	0x0474, 0x0160, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__IPU1_DI0_PIN02,	0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN2__IPU2_DI0_PIN02,	0x0478, 0x0164, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__AUD6_TXD,	0x0478, 0x0164, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN2__GPIO4_IO18,	0x0478, 0x0164, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__IPU1_DI0_PIN03,	0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DI0_PIN3__IPU2_DI0_PIN03,	0x047C, 0x0168, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__AUD6_TXFS,	0x047C, 0x0168, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN3__GPIO4_IO19,	0x047C, 0x0168, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__IPU1_DI0_PIN04,	0x0480, 0x016C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__IPU2_DI0_PIN04,	0x0480, 0x016C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__AUD6_RXD,	0x0480, 0x016C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__SD1_WP,	0x0480, 0x016C, 3, 0x094C, 0, 0)
+MX6_PAD_DECL(DI0_PIN4__GPIO4_IO20,	0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT0__IPU1_DISP0_DATA00,	0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT0__IPU2_DISP0_DATA00,	0x0484, 0x0170, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__ECSPI3_SCLK,	0x0484, 0x0170, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT0__GPIO4_IO21,	0x0484, 0x0170, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01,	0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT1__IPU2_DISP0_DATA01,	0x0488, 0x0174, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI,	0x0488, 0x0174, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22,	0x0488, 0x0174, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02,	0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT2__IPU2_DISP0_DATA02,	0x048C, 0x0178, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO,	0x048C, 0x0178, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23,	0x048C, 0x0178, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__IPU1_DISP0_DATA03,	0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT3__IPU2_DISP0_DATA03,	0x0490, 0x017C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__ECSPI3_SS0,	0x0490, 0x017C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT3__GPIO4_IO24,	0x0490, 0x017C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__IPU1_DISP0_DATA04,	0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT4__IPU2_DISP0_DATA04,	0x0494, 0x0180, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__ECSPI3_SS1,	0x0494, 0x0180, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT4__GPIO4_IO25,	0x0494, 0x0180, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__IPU1_DISP0_DATA05,	0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT5__IPU2_DISP0_DATA05,	0x0498, 0x0184, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__ECSPI3_SS2,	0x0498, 0x0184, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__AUD6_RXFS,	0x0498, 0x0184, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT5__GPIO4_IO26,	0x0498, 0x0184, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__IPU1_DISP0_DATA06,	0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT6__IPU2_DISP0_DATA06,	0x049C, 0x0188, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__ECSPI3_SS3,	0x049C, 0x0188, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__AUD6_RXC,	0x049C, 0x0188, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT6__GPIO4_IO27,	0x049C, 0x0188, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__IPU1_DISP0_DATA07,	0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT7__IPU2_DISP0_DATA07,	0x04A0, 0x018C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__ECSPI3_RDY,	0x04A0, 0x018C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT7__GPIO4_IO28,	0x04A0, 0x018C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__IPU1_DISP0_DATA08,	0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT8__IPU2_DISP0_DATA08,	0x04A4, 0x0190, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__PWM1_OUT,	0x04A4, 0x0190, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__WDOG1_B,	0x04A4, 0x0190, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT8__GPIO4_IO29,	0x04A4, 0x0190, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__IPU1_DISP0_DATA09,	0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT9__IPU2_DISP0_DATA09,	0x04A8, 0x0194, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__PWM2_OUT,	0x04A8, 0x0194, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__WDOG2_B,	0x04A8, 0x0194, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT9__GPIO4_IO30,	0x04A8, 0x0194, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10,	0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT10__IPU2_DISP0_DATA10,	0x04AC, 0x0198, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31,	0x04AC, 0x0198, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11,	0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT11__IPU2_DISP0_DATA11,	0x04B0, 0x019C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT11__GPIO5_IO05,	0x04B0, 0x019C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__IPU1_DISP0_DATA12,	0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT12__IPU2_DISP0_DATA12,	0x04B4, 0x01A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT12__GPIO5_IO06,	0x04B4, 0x01A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__IPU1_DISP0_DATA13,	0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT13__IPU2_DISP0_DATA13,	0x04B8, 0x01A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT13__AUD5_RXFS,	0x04B8, 0x01A4, 3, 0x07D8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT13__GPIO5_IO07,	0x04B8, 0x01A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__IPU1_DISP0_DATA14,	0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT14__IPU2_DISP0_DATA14,	0x04BC, 0x01A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT14__AUD5_RXC,	0x04BC, 0x01A8, 3, 0x07D4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT14__GPIO5_IO08,	0x04BC, 0x01A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__IPU1_DISP0_DATA15,	0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT15__IPU2_DISP0_DATA15,	0x04C0, 0x01AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI1_SS1,	0x04C0, 0x01AC, 2, 0x0804, 1, 0)
+MX6_PAD_DECL(DISP0_DAT15__ECSPI2_SS1,	0x04C0, 0x01AC, 3, 0x0820, 1, 0)
+MX6_PAD_DECL(DISP0_DAT15__GPIO5_IO09,	0x04C0, 0x01AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__IPU1_DISP0_DATA16,	0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT16__IPU2_DISP0_DATA16,	0x04C4, 0x01B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__ECSPI2_MOSI,	0x04C4, 0x01B0, 2, 0x0818, 1, 0)
+MX6_PAD_DECL(DISP0_DAT16__AUD5_TXC,	0x04C4, 0x01B0, 3, 0x07DC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__SDMA_EXT_EVENT0,	0x04C4, 0x01B0, 4, 0x090C, 0, 0)
+MX6_PAD_DECL(DISP0_DAT16__GPIO5_IO10,	0x04C4, 0x01B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__IPU1_DISP0_DATA17,	0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT17__IPU2_DISP0_DATA17,	0x04C8, 0x01B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__ECSPI2_MISO,	0x04C8, 0x01B4, 2, 0x0814, 1, 0)
+MX6_PAD_DECL(DISP0_DAT17__AUD5_TXD,	0x04C8, 0x01B4, 3, 0x07D0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__SDMA_EXT_EVENT1,	0x04C8, 0x01B4, 4, 0x0910, 0, 0)
+MX6_PAD_DECL(DISP0_DAT17__GPIO5_IO11,	0x04C8, 0x01B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__IPU1_DISP0_DATA18,	0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT18__IPU2_DISP0_DATA18,	0x04CC, 0x01B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__ECSPI2_SS0,	0x04CC, 0x01B8, 2, 0x081C, 1, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD5_TXFS,	0x04CC, 0x01B8, 3, 0x07E0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__AUD4_RXFS,	0x04CC, 0x01B8, 4, 0x07C0, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__GPIO5_IO12,	0x04CC, 0x01B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT18__EIM_CS2_B,	0x04CC, 0x01B8, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__IPU1_DISP0_DATA19,	0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT19__IPU2_DISP0_DATA19,	0x04D0, 0x01BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__ECSPI2_SCLK,	0x04D0, 0x01BC, 2, 0x0810, 1, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD,	0x04D0, 0x01BC, 3, 0x07CC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC,	0x04D0, 0x01BC, 4, 0x07BC, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13,	0x04D0, 0x01BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B,	0x04D0, 0x01BC, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__IPU1_DISP0_DATA20,	0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT20__IPU2_DISP0_DATA20,	0x04D4, 0x01C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__ECSPI1_SCLK,	0x04D4, 0x01C0, 2, 0x07F4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT20__AUD4_TXC,	0x04D4, 0x01C0, 3, 0x07C4, 0, 0)
+MX6_PAD_DECL(DISP0_DAT20__GPIO5_IO14,	0x04D4, 0x01C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__IPU1_DISP0_DATA21,	0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT21__IPU2_DISP0_DATA21,	0x04D8, 0x01C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT21__ECSPI1_MOSI,	0x04D8, 0x01C4, 2, 0x07FC, 1, 0)
+MX6_PAD_DECL(DISP0_DAT21__AUD4_TXD,	0x04D8, 0x01C4, 3, 0x07B8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT21__GPIO5_IO15,	0x04D8, 0x01C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__IPU1_DISP0_DATA22,	0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT22__IPU2_DISP0_DATA22,	0x04DC, 0x01C8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT22__ECSPI1_MISO,	0x04DC, 0x01C8, 2, 0x07F8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT22__AUD4_TXFS,	0x04DC, 0x01C8, 3, 0x07C8, 1, 0)
+MX6_PAD_DECL(DISP0_DAT22__GPIO5_IO16,	0x04DC, 0x01C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__IPU1_DISP0_DATA23,	0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
+MX6_PAD_DECL(DISP0_DAT23__IPU2_DISP0_DATA23,	0x04E0, 0x01CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT23__ECSPI1_SS0,	0x04E0, 0x01CC, 2, 0x0800, 1, 0)
+MX6_PAD_DECL(DISP0_DAT23__AUD4_RXD,	0x04E0, 0x01CC, 3, 0x07B4, 1, 0)
+MX6_PAD_DECL(DISP0_DAT23__GPIO5_IO17,	0x04E0, 0x01CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_MDIO,	0x04E4, 0x01D0, 1, 0x0840, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ESAI_RX_CLK,	0x04E4, 0x01D0, 2, 0x086C, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__ENET_1588_EVENT1_OUT,	0x04E4, 0x01D0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__GPIO1_IO22,	0x04E4, 0x01D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDIO__SPDIF_LOCK,	0x04E4, 0x01D0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ENET_TX_CLK,	0x04E8, 0x01D4, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__ESAI_RX_FS,	0x04E8, 0x01D4, 2, 0x085C, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__GPIO1_IO23,	0x04E8, 0x01D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_REF_CLK__SPDIF_SR_CLK,	0x04E8, 0x01D4, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__USB_OTG_ID,	0x04EC, 0x01D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_RX_ER,	0x04EC, 0x01D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__ESAI_RX_HF_CLK,	0x04EC, 0x01D8, 2, 0x0864, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__SPDIF_IN,	0x04EC, 0x01D8, 3, 0x0914, 1, 0)
+MX6_PAD_DECL(ENET_RX_ER__ENET_1588_EVENT2_OUT,	0x04EC, 0x01D8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RX_ER__GPIO1_IO24,	0x04EC, 0x01D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ENET_RX_EN,	0x04F0, 0x01DC, 1, 0x0858, 1, 0)
+MX6_PAD_DECL(ENET_CRS_DV__ESAI_TX_CLK,	0x04F0, 0x01DC, 2, 0x0870, 0, 0)
+MX6_PAD_DECL(ENET_CRS_DV__SPDIF_EXT_CLK,	0x04F0, 0x01DC, 3, 0x0918, 1, 0)
+MX6_PAD_DECL(ENET_CRS_DV__GPIO1_IO25,	0x04F0, 0x01DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__MLB_SIG,	0x04F4, 0x01E0, 0, 0x0908, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_RX_DATA1,	0x04F4, 0x01E0, 1, 0x084C, 1, 0)
+MX6_PAD_DECL(ENET_RXD1__ESAI_TX_FS,	0x04F4, 0x01E0, 2, 0x0860, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__ENET_1588_EVENT3_OUT,	0x04F4, 0x01E0, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD1__GPIO1_IO26,	0x04F4, 0x01E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__ENET_RX_DATA0,	0x04F8, 0x01E4, 1, 0x0848, 1, 0)
+MX6_PAD_DECL(ENET_RXD0__ESAI_TX_HF_CLK,	0x04F8, 0x01E4, 2, 0x0868, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__SPDIF_OUT,	0x04F8, 0x01E4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_RXD0__GPIO1_IO27,	0x04F8, 0x01E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ENET_TX_EN,	0x04FC, 0x01E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__ESAI_TX3_RX2,	0x04FC, 0x01E8, 2, 0x0880, 0, 0)
+MX6_PAD_DECL(ENET_TX_EN__GPIO1_IO28,	0x04FC, 0x01E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__MLB_CLK,	0x0500, 0x01EC, 0, 0x0900, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_TX_DATA1,	0x0500, 0x01EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ESAI_TX2_RX3,	0x0500, 0x01EC, 2, 0x087C, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__ENET_1588_EVENT0_IN,	0x0500, 0x01EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD1__GPIO1_IO29,	0x0500, 0x01EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ENET_TX_DATA0,	0x0504, 0x01F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__ESAI_TX4_RX1,	0x0504, 0x01F0, 2, 0x0884, 0, 0)
+MX6_PAD_DECL(ENET_TXD0__GPIO1_IO30,	0x0504, 0x01F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__MLB_DATA,	0x0508, 0x01F4, 0, 0x0904, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_MDC,	0x0508, 0x01F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ESAI_TX5_RX0,	0x0508, 0x01F4, 2, 0x0888, 0, 0)
+MX6_PAD_DECL(ENET_MDC__ENET_1588_EVENT1_IN,	0x0508, 0x01F4, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(ENET_MDC__GPIO1_IO31,	0x0508, 0x01F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__ECSPI1_SCLK,	0x05C8, 0x01F8, 0, 0x07F4, 2, 0)
+MX6_PAD_DECL(KEY_COL0__ENET_RX_DATA3,	0x05C8, 0x01F8, 1, 0x0854, 1, 0)
+MX6_PAD_DECL(KEY_COL0__AUD5_TXC,	0x05C8, 0x01F8, 2, 0x07DC, 1, 0)
+MX6_PAD_DECL(KEY_COL0__KEY_COL0,	0x05C8, 0x01F8, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_TX_DATA,	0x05C8, 0x01F8, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__UART4_RX_DATA,	0x05C8, 0x01F8, 4, 0x0938, 0, 0)
+MX6_PAD_DECL(KEY_COL0__GPIO4_IO06,	0x05C8, 0x01F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL0__DCIC1_OUT,	0x05C8, 0x01F8, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__ECSPI1_MOSI,	0x05CC, 0x01FC, 0, 0x07FC, 2, 0)
+MX6_PAD_DECL(KEY_ROW0__ENET_TX_DATA3,	0x05CC, 0x01FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__AUD5_TXD,	0x05CC, 0x01FC, 2, 0x07D0, 1, 0)
+MX6_PAD_DECL(KEY_ROW0__KEY_ROW0,	0x05CC, 0x01FC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_TX_DATA,	0x05CC, 0x01FC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__UART4_RX_DATA,	0x05CC, 0x01FC, 4, 0x0938, 1, 0)
+MX6_PAD_DECL(KEY_ROW0__GPIO4_IO07,	0x05CC, 0x01FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW0__DCIC2_OUT,	0x05CC, 0x01FC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__ECSPI1_MISO,	0x05D0, 0x0200, 0, 0x07F8, 2, 0)
+MX6_PAD_DECL(KEY_COL1__ENET_MDIO,	0x05D0, 0x0200, 1, 0x0840, 1, 0)
+MX6_PAD_DECL(KEY_COL1__AUD5_TXFS,	0x05D0, 0x0200, 2, 0x07E0, 1, 0)
+MX6_PAD_DECL(KEY_COL1__KEY_COL1,	0x05D0, 0x0200, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_TX_DATA,	0x05D0, 0x0200, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__UART5_RX_DATA,	0x05D0, 0x0200, 4, 0x0940, 0, 0)
+MX6_PAD_DECL(KEY_COL1__GPIO4_IO08,	0x05D0, 0x0200, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL1__SD1_VSELECT,	0x05D0, 0x0200, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__ECSPI1_SS0,	0x05D4, 0x0204, 0, 0x0800, 2, 0)
+MX6_PAD_DECL(KEY_ROW1__ENET_COL,	0x05D4, 0x0204, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__AUD5_RXD,	0x05D4, 0x0204, 2, 0x07CC, 1, 0)
+MX6_PAD_DECL(KEY_ROW1__KEY_ROW1,	0x05D4, 0x0204, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_TX_DATA,	0x05D4, 0x0204, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__UART5_RX_DATA,	0x05D4, 0x0204, 4, 0x0940, 1, 0)
+MX6_PAD_DECL(KEY_ROW1__GPIO4_IO09,	0x05D4, 0x0204, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW1__SD2_VSELECT,	0x05D4, 0x0204, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ECSPI1_SS1,	0x05D8, 0x0208, 0, 0x0804, 2, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_RX_DATA2,	0x05D8, 0x0208, 1, 0x0850, 1, 0)
+MX6_PAD_DECL(KEY_COL2__FLEXCAN1_TX,	0x05D8, 0x0208, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__KEY_COL2,	0x05D8, 0x0208, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__ENET_MDC,	0x05D8, 0x0208, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__GPIO4_IO10,	0x05D8, 0x0208, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL2__USB_H1_PWR_CTL_WAKE,	0x05D8, 0x0208, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__ECSPI1_SS2,	0x05DC, 0x020C, 0, 0x0808, 1, 0)
+MX6_PAD_DECL(KEY_ROW2__ENET_TX_DATA2,	0x05DC, 0x020C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__FLEXCAN1_RX,	0x05DC, 0x020C, 2, 0x07E4, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__KEY_ROW2,	0x05DC, 0x020C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__SD2_VSELECT,	0x05DC, 0x020C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__GPIO4_IO11,	0x05DC, 0x020C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW2__HDMI_TX_CEC_LINE,	0x05DC, 0x020C, 6, 0x088C, 1, 0)
+MX6_PAD_DECL(KEY_COL3__ECSPI1_SS3,	0x05E0, 0x0210, 0, 0x080C, 1, 0)
+MX6_PAD_DECL(KEY_COL3__ENET_CRS,	0x05E0, 0x0210, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__HDMI_TX_DDC_SCL,	0x05E0, 0x0210, 2, 0x0890, 1, 0)
+MX6_PAD_DECL(KEY_COL3__KEY_COL3,	0x05E0, 0x0210, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__I2C2_SCL,	0x05E0, 0x0210, 20, 0x08A0, 1, 0)
+MX6_PAD_DECL(KEY_COL3__GPIO4_IO12,	0x05E0, 0x0210, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL3__SPDIF_IN,	0x05E0, 0x0210, 6, 0x0914, 2, 0)
+MX6_PAD_DECL(KEY_ROW3__ASRC_EXT_CLK,	0x05E4, 0x0214, 1, 0x07B0, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__HDMI_TX_DDC_SDA,	0x05E4, 0x0214, 2, 0x0894, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__KEY_ROW3,	0x05E4, 0x0214, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__I2C2_SDA,	0x05E4, 0x0214, 20, 0x08A4, 1, 0)
+MX6_PAD_DECL(KEY_ROW3__GPIO4_IO13,	0x05E4, 0x0214, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW3__SD1_VSELECT,	0x05E4, 0x0214, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__FLEXCAN2_TX,	0x05E8, 0x0218, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__IPU1_SISG4,	0x05E8, 0x0218, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__USB_OTG_OC,	0x05E8, 0x0218, 2, 0x0944, 1, 0)
+MX6_PAD_DECL(KEY_COL4__KEY_COL4,	0x05E8, 0x0218, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_CTS_B,	0x05E8, 0x0218, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_COL4__UART5_RTS_B,	0x05E8, 0x0218, 4, 0x093C, 0, 0)
+MX6_PAD_DECL(KEY_COL4__GPIO4_IO14,	0x05E8, 0x0218, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__FLEXCAN2_RX,	0x05EC, 0x021C, 0, 0x07E8, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__IPU1_SISG5,	0x05EC, 0x021C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__USB_OTG_PWR,	0x05EC, 0x021C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__KEY_ROW4,	0x05EC, 0x021C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_CTS_B,	0x05EC, 0x021C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(KEY_ROW4__UART5_RTS_B,	0x05EC, 0x021C, 4, 0x093C, 1, 0)
+MX6_PAD_DECL(KEY_ROW4__GPIO4_IO15,	0x05EC, 0x021C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__CCM_CLKO1,	0x05F0, 0x0220, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__KEY_COL5,	0x05F0, 0x0220, 2, 0x08E8, 0, 0)
+MX6_PAD_DECL(GPIO_0__ASRC_EXT_CLK,	0x05F0, 0x0220, 3, 0x07B0, 1, 0)
+MX6_PAD_DECL(GPIO_0__EPIT1_OUT,	0x05F0, 0x0220, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__GPIO1_IO00,	0x05F0, 0x0220, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__USB_H1_PWR,	0x05F0, 0x0220, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_0__SNVS_VIO_5,	0x05F0, 0x0220, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__ESAI_RX_CLK,	0x05F4, 0x0224, 0, 0x086C, 1, 0)
+MX6_PAD_DECL(GPIO_1__WDOG2_B,	0x05F4, 0x0224, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__KEY_ROW5,	0x05F4, 0x0224, 2, 0x08F4, 0, 0)
+MX6_PAD_DECL(GPIO_1__USB_OTG_ID,	0x05F4, 0x0224, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__PWM2_OUT,	0x05F4, 0x0224, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__GPIO1_IO01,	0x05F4, 0x0224, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_1__SD1_CD_B,	0x05F4, 0x0224, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__ESAI_RX_FS,	0x05F8, 0x0228, 0, 0x085C, 1, 0)
+MX6_PAD_DECL(GPIO_9__WDOG1_B,	0x05F8, 0x0228, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__KEY_COL6,	0x05F8, 0x0228, 2, 0x08EC, 0, 0)
+MX6_PAD_DECL(GPIO_9__CCM_REF_EN_B,	0x05F8, 0x0228, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__PWM1_OUT,	0x05F8, 0x0228, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__GPIO1_IO09,	0x05F8, 0x0228, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_9__SD1_WP,	0x05F8, 0x0228, 6, 0x094C, 1, 0)
+MX6_PAD_DECL(GPIO_3__ESAI_RX_HF_CLK,	0x05FC, 0x022C, 0, 0x0864, 1, 0)
+MX6_PAD_DECL(GPIO_3__I2C3_SCL,	0x05FC, 0x022C, 18, 0x08A8, 1, 0)
+MX6_PAD_DECL(GPIO_3__XTALOSC_REF_CLK_24M,	0x05FC, 0x022C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__CCM_CLKO2,	0x05FC, 0x022C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__GPIO1_IO03,	0x05FC, 0x022C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_3__USB_H1_OC,	0x05FC, 0x022C, 6, 0x0948, 1, 0)
+MX6_PAD_DECL(GPIO_3__MLB_CLK,	0x05FC, 0x022C, 7, 0x0900, 1, 0)
+MX6_PAD_DECL(GPIO_6__ESAI_TX_CLK,	0x0600, 0x0230, 0, 0x0870, 1, 0)
+MX6_PAD_DECL(GPIO_6__I2C3_SDA,	0x0600, 0x0230, 18, 0x08AC, 1, 0)
+MX6_PAD_DECL(GPIO_6__GPIO1_IO06,	0x0600, 0x0230, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__SD2_LCTL,	0x0600, 0x0230, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_6__MLB_SIG,	0x0600, 0x0230, 7, 0x0908, 1, 0)
+MX6_PAD_DECL(GPIO_2__ESAI_TX_FS,	0x0604, 0x0234, 0, 0x0860, 1, 0)
+MX6_PAD_DECL(GPIO_2__KEY_ROW6,	0x0604, 0x0234, 2, 0x08F8, 1, 0)
+MX6_PAD_DECL(GPIO_2__GPIO1_IO02,	0x0604, 0x0234, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__SD2_WP,	0x0604, 0x0234, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_2__MLB_DATA,	0x0604, 0x0234, 7, 0x0904, 1, 0)
+MX6_PAD_DECL(GPIO_4__ESAI_TX_HF_CLK,	0x0608, 0x0238, 0, 0x0868, 1, 0)
+MX6_PAD_DECL(GPIO_4__KEY_COL7,	0x0608, 0x0238, 2, 0x08F0, 1, 0)
+MX6_PAD_DECL(GPIO_4__GPIO1_IO04,	0x0608, 0x0238, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_4__SD2_CD_B,	0x0608, 0x0238, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__ESAI_TX2_RX3,	0x060C, 0x023C, 0, 0x087C, 1, 0)
+MX6_PAD_DECL(GPIO_5__KEY_ROW7,	0x060C, 0x023C, 2, 0x08FC, 1, 0)
+MX6_PAD_DECL(GPIO_5__CCM_CLKO1,	0x060C, 0x023C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__GPIO1_IO05,	0x060C, 0x023C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_5__I2C3_SCL,	0x060C, 0x023C, 22, 0x08A8, 2, 0)
+MX6_PAD_DECL(GPIO_5__ARM_EVENTI,	0x060C, 0x023C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__ESAI_TX4_RX1,	0x0610, 0x0240, 0, 0x0884, 1, 0)
+MX6_PAD_DECL(GPIO_7__ECSPI5_RDY,	0x0610, 0x0240, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__EPIT1_OUT,	0x0610, 0x0240, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__FLEXCAN1_TX,	0x0610, 0x0240, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_TX_DATA,	0x0610, 0x0240, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__UART2_RX_DATA,	0x0610, 0x0240, 4, 0x0928, 2, 0)
+MX6_PAD_DECL(GPIO_7__GPIO1_IO07,	0x0610, 0x0240, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__SPDIF_LOCK,	0x0610, 0x0240, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_7__USB_OTG_HOST_MODE,	0x0610, 0x0240, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__ESAI_TX5_RX0,	0x0614, 0x0244, 0, 0x0888, 1, 0)
+MX6_PAD_DECL(GPIO_8__XTALOSC_REF_CLK_32K,	0x0614, 0x0244, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__EPIT2_OUT,	0x0614, 0x0244, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__FLEXCAN1_RX,	0x0614, 0x0244, 3, 0x07E4, 1, 0)
+MX6_PAD_DECL(GPIO_8__UART2_TX_DATA,	0x0614, 0x0244, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__UART2_RX_DATA,	0x0614, 0x0244, 4, 0x0928, 3, 0)
+MX6_PAD_DECL(GPIO_8__GPIO1_IO08,	0x0614, 0x0244, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__SPDIF_SR_CLK,	0x0614, 0x0244, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_8__USB_OTG_PWR_CTL_WAKE,	0x0614, 0x0244, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ESAI_TX3_RX2,	0x0618, 0x0248, 0, 0x0880, 1, 0)
+MX6_PAD_DECL(GPIO_16__ENET_1588_EVENT2_IN,	0x0618, 0x0248, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__ENET_REF_CLK,	0x0618, 0x0248, 2 | IOMUX_CONFIG_SION, 0x083C, 1, 0)
+MX6_PAD_DECL(GPIO_16__SD1_LCTL,	0x0618, 0x0248, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__SPDIF_IN,	0x0618, 0x0248, 4, 0x0914, 3, 0)
+MX6_PAD_DECL(GPIO_16__GPIO7_IO11,	0x0618, 0x0248, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_16__I2C3_SDA,	0x0618, 0x0248, 22, 0x08AC, 2, 0)
+MX6_PAD_DECL(GPIO_16__JTAG_DE_B,	0x0618, 0x0248, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__ESAI_TX0,	0x061C, 0x024C, 0, 0x0874, 0, 0)
+MX6_PAD_DECL(GPIO_17__ENET_1588_EVENT3_IN,	0x061C, 0x024C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__CCM_PMIC_READY,	0x061C, 0x024C, 2, 0x07F0, 1, 0)
+MX6_PAD_DECL(GPIO_17__SDMA_EXT_EVENT0,	0x061C, 0x024C, 3, 0x090C, 1, 0)
+MX6_PAD_DECL(GPIO_17__SPDIF_OUT,	0x061C, 0x024C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_17__GPIO7_IO12,	0x061C, 0x024C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__ESAI_TX1,	0x0620, 0x0250, 0, 0x0878, 0, 0)
+MX6_PAD_DECL(GPIO_18__ENET_RX_CLK,	0x0620, 0x0250, 1, 0x0844, 1, 0)
+MX6_PAD_DECL(GPIO_18__SD3_VSELECT,	0x0620, 0x0250, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SDMA_EXT_EVENT1,	0x0620, 0x0250, 3, 0x0910, 1, 0)
+MX6_PAD_DECL(GPIO_18__ASRC_EXT_CLK,	0x0620, 0x0250, 4, 0x07B0, 2, 0)
+MX6_PAD_DECL(GPIO_18__GPIO7_IO13,	0x0620, 0x0250, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_18__SNVS_VIO_5_CTL,	0x0620, 0x0250, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__KEY_COL5,	0x0624, 0x0254, 0, 0x08E8, 1, 0)
+MX6_PAD_DECL(GPIO_19__ENET_1588_EVENT0_OUT,	0x0624, 0x0254, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__SPDIF_OUT,	0x0624, 0x0254, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__CCM_CLKO1,	0x0624, 0x0254, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ECSPI1_RDY,	0x0624, 0x0254, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__GPIO4_IO05,	0x0624, 0x0254, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(GPIO_19__ENET_TX_ER,	0x0624, 0x0254, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK,	0x0628, 0x0258, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__GPIO5_IO18,	0x0628, 0x0258, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_PIXCLK__ARM_EVENTO,	0x0628, 0x0258, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__IPU1_CSI0_HSYNC,	0x062C, 0x025C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__CCM_CLKO1,	0x062C, 0x025C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__GPIO5_IO19,	0x062C, 0x025C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_MCLK__ARM_TRACE_CTL,	0x062C, 0x025C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN,	0x0630, 0x0260, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__EIM_DATA00,	0x0630, 0x0260, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__GPIO5_IO20,	0x0630, 0x0260, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DATA_EN__ARM_TRACE_CLK,	0x0630, 0x0260, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__IPU1_CSI0_VSYNC,	0x0634, 0x0264, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__EIM_DATA01,	0x0634, 0x0264, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__GPIO5_IO21,	0x0634, 0x0264, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_VSYNC__ARM_TRACE00,	0x0634, 0x0264, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__IPU1_CSI0_DATA04,	0x0638, 0x0268, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__EIM_DATA02,	0x0638, 0x0268, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ECSPI1_SCLK,	0x0638, 0x0268, 2, 0x07F4, 3, 0)
+MX6_PAD_DECL(CSI0_DAT4__KEY_COL5,	0x0638, 0x0268, 3, 0x08E8, 2, 0)
+MX6_PAD_DECL(CSI0_DAT4__AUD3_TXC,	0x0638, 0x0268, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__GPIO5_IO22,	0x0638, 0x0268, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT4__ARM_TRACE01,	0x0638, 0x0268, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__IPU1_CSI0_DATA05,	0x063C, 0x026C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__EIM_DATA03,	0x063C, 0x026C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ECSPI1_MOSI,	0x063C, 0x026C, 2, 0x07FC, 3, 0)
+MX6_PAD_DECL(CSI0_DAT5__KEY_ROW5,	0x063C, 0x026C, 3, 0x08F4, 1, 0)
+MX6_PAD_DECL(CSI0_DAT5__AUD3_TXD,	0x063C, 0x026C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__GPIO5_IO23,	0x063C, 0x026C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT5__ARM_TRACE02,	0x063C, 0x026C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__IPU1_CSI0_DATA06,	0x0640, 0x0270, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__EIM_DATA04,	0x0640, 0x0270, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ECSPI1_MISO,	0x0640, 0x0270, 2, 0x07F8, 3, 0)
+MX6_PAD_DECL(CSI0_DAT6__KEY_COL6,	0x0640, 0x0270, 3, 0x08EC, 1, 0)
+MX6_PAD_DECL(CSI0_DAT6__AUD3_TXFS,	0x0640, 0x0270, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__GPIO5_IO24,	0x0640, 0x0270, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT6__ARM_TRACE03,	0x0640, 0x0270, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__IPU1_CSI0_DATA07,	0x0644, 0x0274, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__EIM_DATA05,	0x0644, 0x0274, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ECSPI1_SS0,	0x0644, 0x0274, 2, 0x0800, 3, 0)
+MX6_PAD_DECL(CSI0_DAT7__KEY_ROW6,	0x0644, 0x0274, 3, 0x08F8, 2, 0)
+MX6_PAD_DECL(CSI0_DAT7__AUD3_RXD,	0x0644, 0x0274, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__GPIO5_IO25,	0x0644, 0x0274, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT7__ARM_TRACE04,	0x0644, 0x0274, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__IPU1_CSI0_DATA08,	0x0648, 0x0278, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__EIM_DATA06,	0x0648, 0x0278, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ECSPI2_SCLK,	0x0648, 0x0278, 2, 0x0810, 2, 0)
+MX6_PAD_DECL(CSI0_DAT8__KEY_COL7,	0x0648, 0x0278, 3, 0x08F0, 2, 0)
+MX6_PAD_DECL(CSI0_DAT8__I2C1_SDA,	0x0648, 0x0278, 20, 0x089C, 1, 0)
+MX6_PAD_DECL(CSI0_DAT8__GPIO5_IO26,	0x0648, 0x0278, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT8__ARM_TRACE05,	0x0648, 0x0278, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__IPU1_CSI0_DATA09,	0x064C, 0x027C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__EIM_DATA07,	0x064C, 0x027C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ECSPI2_MOSI,	0x064C, 0x027C, 2, 0x0818, 2, 0)
+MX6_PAD_DECL(CSI0_DAT9__KEY_ROW7,	0x064C, 0x027C, 3, 0x08FC, 2, 0)
+MX6_PAD_DECL(CSI0_DAT9__I2C1_SCL,	0x064C, 0x027C, 20, 0x0898, 1, 0)
+MX6_PAD_DECL(CSI0_DAT9__GPIO5_IO27,	0x064C, 0x027C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT9__ARM_TRACE06,	0x064C, 0x027C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__IPU1_CSI0_DATA10,	0x0650, 0x0280, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__AUD3_RXC,	0x0650, 0x0280, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ECSPI2_MISO,	0x0650, 0x0280, 2, 0x0814, 2, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_TX_DATA,	0x0650, 0x0280, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__UART1_RX_DATA,	0x0650, 0x0280, 3, 0x0920, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__GPIO5_IO28,	0x0650, 0x0280, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT10__ARM_TRACE07,	0x0650, 0x0280, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__IPU1_CSI0_DATA11,	0x0654, 0x0284, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__AUD3_RXFS,	0x0654, 0x0284, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ECSPI2_SS0,	0x0654, 0x0284, 2, 0x081C, 2, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_TX_DATA,	0x0654, 0x0284, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__UART1_RX_DATA,	0x0654, 0x0284, 3, 0x0920, 1, 0)
+MX6_PAD_DECL(CSI0_DAT11__GPIO5_IO29,	0x0654, 0x0284, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT11__ARM_TRACE08,	0x0654, 0x0284, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__IPU1_CSI0_DATA12,	0x0658, 0x0288, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__EIM_DATA08,	0x0658, 0x0288, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_TX_DATA,	0x0658, 0x0288, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__UART4_RX_DATA,	0x0658, 0x0288, 3, 0x0938, 2, 0)
+MX6_PAD_DECL(CSI0_DAT12__GPIO5_IO30,	0x0658, 0x0288, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT12__ARM_TRACE09,	0x0658, 0x0288, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__IPU1_CSI0_DATA13,	0x065C, 0x028C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__EIM_DATA09,	0x065C, 0x028C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_TX_DATA,	0x065C, 0x028C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__UART4_RX_DATA,	0x065C, 0x028C, 3, 0x0938, 3, 0)
+MX6_PAD_DECL(CSI0_DAT13__GPIO5_IO31,	0x065C, 0x028C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT13__ARM_TRACE10,	0x065C, 0x028C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__IPU1_CSI0_DATA14,	0x0660, 0x0290, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__EIM_DATA10,	0x0660, 0x0290, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_TX_DATA,	0x0660, 0x0290, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__UART5_RX_DATA,	0x0660, 0x0290, 3, 0x0940, 2, 0)
+MX6_PAD_DECL(CSI0_DAT14__GPIO6_IO00,	0x0660, 0x0290, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT14__ARM_TRACE11,	0x0660, 0x0290, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__IPU1_CSI0_DATA15,	0x0664, 0x0294, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__EIM_DATA11,	0x0664, 0x0294, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_TX_DATA,	0x0664, 0x0294, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__UART5_RX_DATA,	0x0664, 0x0294, 3, 0x0940, 3, 0)
+MX6_PAD_DECL(CSI0_DAT15__GPIO6_IO01,	0x0664, 0x0294, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT15__ARM_TRACE12,	0x0664, 0x0294, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__IPU1_CSI0_DATA16,	0x0668, 0x0298, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__EIM_DATA12,	0x0668, 0x0298, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_CTS_B,	0x0668, 0x0298, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__UART4_RTS_B,	0x0668, 0x0298, 3, 0x0934, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__GPIO6_IO02,	0x0668, 0x0298, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT16__ARM_TRACE13,	0x0668, 0x0298, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__IPU1_CSI0_DATA17,	0x066C, 0x029C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__EIM_DATA13,	0x066C, 0x029C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_CTS_B,	0x066C, 0x029C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__UART4_RTS_B,	0x066C, 0x029C, 3, 0x0934, 1, 0)
+MX6_PAD_DECL(CSI0_DAT17__GPIO6_IO03,	0x066C, 0x029C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT17__ARM_TRACE14,	0x066C, 0x029C, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__IPU1_CSI0_DATA18,	0x0670, 0x02A0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__EIM_DATA14,	0x0670, 0x02A0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_CTS_B,	0x0670, 0x02A0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__UART5_RTS_B,	0x0670, 0x02A0, 3, 0x093C, 2, 0)
+MX6_PAD_DECL(CSI0_DAT18__GPIO6_IO04,	0x0670, 0x02A0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT18__ARM_TRACE15,	0x0670, 0x02A0, 7, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__IPU1_CSI0_DATA19,	0x0674, 0x02A4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__EIM_DATA15,	0x0674, 0x02A4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_CTS_B,	0x0674, 0x02A4, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(CSI0_DAT19__UART5_RTS_B,	0x0674, 0x02A4, 3, 0x093C, 3, 0)
+MX6_PAD_DECL(CSI0_DAT19__GPIO6_IO05,	0x0674, 0x02A4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__SD3_DATA7,	0x0690, 0x02A8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_TX_DATA,	0x0690, 0x02A8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT7__UART1_RX_DATA,	0x0690, 0x02A8, 1, 0x0920, 2, 0)
+MX6_PAD_DECL(SD3_DAT7__GPIO6_IO17,	0x0690, 0x02A8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__SD3_DATA6,	0x0694, 0x02AC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_TX_DATA,	0x0694, 0x02AC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT6__UART1_RX_DATA,	0x0694, 0x02AC, 1, 0x0920, 3, 0)
+MX6_PAD_DECL(SD3_DAT6__GPIO6_IO18,	0x0694, 0x02AC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__SD3_DATA5,	0x0698, 0x02B0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_TX_DATA,	0x0698, 0x02B0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT5__UART2_RX_DATA,	0x0698, 0x02B0, 1, 0x0928, 4, 0)
+MX6_PAD_DECL(SD3_DAT5__GPIO7_IO00,	0x0698, 0x02B0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__SD3_DATA4,	0x069C, 0x02B4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_TX_DATA,	0x069C, 0x02B4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT4__UART2_RX_DATA,	0x069C, 0x02B4, 1, 0x0928, 5, 0)
+MX6_PAD_DECL(SD3_DAT4__GPIO7_IO01,	0x069C, 0x02B4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__SD3_CMD,		0x06A0, 0x02B8, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_CTS_B,	0x06A0, 0x02B8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__UART2_RTS_B,	0x06A0, 0x02B8, 1, 0x0924, 2, 0)
+MX6_PAD_DECL(SD3_CMD__FLEXCAN1_TX,	0x06A0, 0x02B8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CMD__GPIO7_IO02,	0x06A0, 0x02B8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__SD3_CLK,	0x06A4, 0x02BC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_CTS_B,	0x06A4, 0x02BC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_CLK__UART2_RTS_B,	0x06A4, 0x02BC, 1, 0x0924, 3, 0)
+MX6_PAD_DECL(SD3_CLK__FLEXCAN1_RX,	0x06A4, 0x02BC, 2, 0x07E4, 2, 0)
+MX6_PAD_DECL(SD3_CLK__GPIO7_IO03,	0x06A4, 0x02BC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__SD3_DATA0,	0x06A8, 0x02C0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_CTS_B,	0x06A8, 0x02C0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__UART1_RTS_B,	0x06A8, 0x02C0, 1, 0x091C, 2, 0)
+MX6_PAD_DECL(SD3_DAT0__FLEXCAN2_TX,	0x06A8, 0x02C0, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT0__GPIO7_IO04,	0x06A8, 0x02C0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__SD3_DATA1,	0x06AC, 0x02C4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_CTS_B,	0x06AC, 0x02C4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT1__UART1_RTS_B,	0x06AC, 0x02C4, 1, 0x091C, 3, 0)
+MX6_PAD_DECL(SD3_DAT1__FLEXCAN2_RX,	0x06AC, 0x02C4, 2, 0x07E8, 1, 0)
+MX6_PAD_DECL(SD3_DAT1__GPIO7_IO05,	0x06AC, 0x02C4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__SD3_DATA2,	0x06B0, 0x02C8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT2__GPIO7_IO06,	0x06B0, 0x02C8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__SD3_DATA3,	0x06B4, 0x02CC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_CTS_B,	0x06B4, 0x02CC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_DAT3__UART3_RTS_B,	0x06B4, 0x02CC, 1, 0x092C, 4, 0)
+MX6_PAD_DECL(SD3_DAT3__GPIO7_IO07,	0x06B4, 0x02CC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__SD3_RESET,	0x06B8, 0x02D0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_CTS_B,	0x06B8, 0x02D0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD3_RST__UART3_RTS_B,	0x06B8, 0x02D0, 1, 0x092C, 5, 0)
+MX6_PAD_DECL(SD3_RST__GPIO7_IO08,	0x06B8, 0x02D0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__NAND_CLE,	0x06BC, 0x02D4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__IPU2_SISG4,	0x06BC, 0x02D4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CLE__GPIO6_IO07,	0x06BC, 0x02D4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__NAND_ALE,	0x06C0, 0x02D8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__SD4_RESET,	0x06C0, 0x02D8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_ALE__GPIO6_IO08,	0x06C0, 0x02D8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__NAND_WP_B,	0x06C4, 0x02DC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__IPU2_SISG5,	0x06C4, 0x02DC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_WP_B__GPIO6_IO09,	0x06C4, 0x02DC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__NAND_READY_B,	0x06C8, 0x02E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__IPU2_DI0_PIN01,	0x06C8, 0x02E0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_RB0__GPIO6_IO10,	0x06C8, 0x02E0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__NAND_CE0_B,	0x06CC, 0x02E4, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS0__GPIO6_IO11,	0x06CC, 0x02E4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__NAND_CE1_B,	0x06D0, 0x02E8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD4_VSELECT,	0x06D0, 0x02E8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__SD3_VSELECT,	0x06D0, 0x02E8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS1__GPIO6_IO14,	0x06D0, 0x02E8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__NAND_CE2_B,	0x06D4, 0x02EC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__IPU1_SISG0,	0x06D4, 0x02EC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__ESAI_TX0,	0x06D4, 0x02EC, 2, 0x0874, 1, 0)
+MX6_PAD_DECL(NANDF_CS2__EIM_CRE,	0x06D4, 0x02EC, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__CCM_CLKO2,	0x06D4, 0x02EC, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__GPIO6_IO15,	0x06D4, 0x02EC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS2__IPU2_SISG0,	0x06D4, 0x02EC, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__NAND_CE3_B,	0x06D8, 0x02F0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__IPU1_SISG1,	0x06D8, 0x02F0, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__ESAI_TX1,	0x06D8, 0x02F0, 2, 0x0878, 1, 0)
+MX6_PAD_DECL(NANDF_CS3__EIM_ADDR26,	0x06D8, 0x02F0, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__GPIO6_IO16,	0x06D8, 0x02F0, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_CS3__IPU2_SISG1,	0x06D8, 0x02F0, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__SD4_CMD,		0x06DC, 0x02F4, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__NAND_RE_B,	0x06DC, 0x02F4, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_TX_DATA,	0x06DC, 0x02F4, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CMD__UART3_RX_DATA,	0x06DC, 0x02F4, 2, 0x0930, 2, 0)
+MX6_PAD_DECL(SD4_CMD__GPIO7_IO09,	0x06DC, 0x02F4, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__SD4_CLK,	0x06E0, 0x02F8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__NAND_WE_B,	0x06E0, 0x02F8, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_TX_DATA,	0x06E0, 0x02F8, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_CLK__UART3_RX_DATA,	0x06E0, 0x02F8, 2, 0x0930, 3, 0)
+MX6_PAD_DECL(SD4_CLK__GPIO7_IO10,	0x06E0, 0x02F8, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__NAND_DATA00,	0x06E4, 0x02FC, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__SD1_DATA4,	0x06E4, 0x02FC, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D0__GPIO2_IO00,	0x06E4, 0x02FC, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__NAND_DATA01,	0x06E8, 0x0300, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__SD1_DATA5,	0x06E8, 0x0300, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D1__GPIO2_IO01,	0x06E8, 0x0300, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__NAND_DATA02,	0x06EC, 0x0304, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__SD1_DATA6,	0x06EC, 0x0304, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D2__GPIO2_IO02,	0x06EC, 0x0304, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__NAND_DATA03,	0x06F0, 0x0308, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__SD1_DATA7,	0x06F0, 0x0308, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D3__GPIO2_IO03,	0x06F0, 0x0308, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__NAND_DATA04,	0x06F4, 0x030C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__SD2_DATA4,	0x06F4, 0x030C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D4__GPIO2_IO04,	0x06F4, 0x030C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__NAND_DATA05,	0x06F8, 0x0310, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__SD2_DATA5,	0x06F8, 0x0310, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D5__GPIO2_IO05,	0x06F8, 0x0310, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__NAND_DATA06,	0x06FC, 0x0314, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__SD2_DATA6,	0x06FC, 0x0314, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D6__GPIO2_IO06,	0x06FC, 0x0314, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__NAND_DATA07,	0x0700, 0x0318, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__SD2_DATA7,	0x0700, 0x0318, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(NANDF_D7__GPIO2_IO07,	0x0700, 0x0318, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__SD4_DATA0,	0x0704, 0x031C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__NAND_DQS,	0x0704, 0x031C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT0__GPIO2_IO08,	0x0704, 0x031C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__SD4_DATA1,	0x0708, 0x0320, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__PWM3_OUT,	0x0708, 0x0320, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT1__GPIO2_IO09,	0x0708, 0x0320, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__SD4_DATA2,	0x070C, 0x0324, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__PWM4_OUT,	0x070C, 0x0324, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT2__GPIO2_IO10,	0x070C, 0x0324, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__SD4_DATA3,	0x0710, 0x0328, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT3__GPIO2_IO11,	0x0710, 0x0328, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__SD4_DATA4,	0x0714, 0x032C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_TX_DATA,	0x0714, 0x032C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT4__UART2_RX_DATA,	0x0714, 0x032C, 2, 0x0928, 6, 0)
+MX6_PAD_DECL(SD4_DAT4__GPIO2_IO12,	0x0714, 0x032C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__SD4_DATA5,	0x0718, 0x0330, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_CTS_B,	0x0718, 0x0330, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT5__UART2_RTS_B,	0x0718, 0x0330, 2, 0x0924, 4, 0)
+MX6_PAD_DECL(SD4_DAT5__GPIO2_IO13,	0x0718, 0x0330, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__SD4_DATA6,	0x071C, 0x0334, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_CTS_B,	0x071C, 0x0334, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT6__UART2_RTS_B,	0x071C, 0x0334, 2, 0x0924, 5, 0)
+MX6_PAD_DECL(SD4_DAT6__GPIO2_IO14,	0x071C, 0x0334, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__SD4_DATA7,	0x0720, 0x0338, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_TX_DATA,	0x0720, 0x0338, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD4_DAT7__UART2_RX_DATA,	0x0720, 0x0338, 2, 0x0928, 7, 0)
+MX6_PAD_DECL(SD4_DAT7__GPIO2_IO15,	0x0720, 0x0338, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__SD1_DATA1,	0x0724, 0x033C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__ECSPI5_SS0,	0x0724, 0x033C, 1, 0x0834, 1, 0)
+MX6_PAD_DECL(SD1_DAT1__PWM3_OUT,	0x0724, 0x033C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPT_CAPTURE2,	0x0724, 0x033C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT1__GPIO1_IO17,	0x0724, 0x033C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__SD1_DATA0,	0x0728, 0x0340, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__ECSPI5_MISO,	0x0728, 0x0340, 1, 0x082C, 1, 0)
+MX6_PAD_DECL(SD1_DAT0__GPT_CAPTURE1,	0x0728, 0x0340, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT0__GPIO1_IO16,	0x0728, 0x0340, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__SD1_DATA3,	0x072C, 0x0344, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__ECSPI5_SS2,	0x072C, 0x0344, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPT_COMPARE3,	0x072C, 0x0344, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__PWM1_OUT,	0x072C, 0x0344, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_B,	0x072C, 0x0344, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__GPIO1_IO21,	0x072C, 0x0344, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT3__WDOG2_RESET_B_DEB,	0x072C, 0x0344, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__SD1_CMD,		0x0730, 0x0348, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__ECSPI5_MOSI,	0x0730, 0x0348, 1, 0x0830, 0, 0)
+MX6_PAD_DECL(SD1_CMD__PWM4_OUT,	0x0730, 0x0348, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPT_COMPARE1,	0x0730, 0x0348, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CMD__GPIO1_IO18,	0x0730, 0x0348, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__SD1_DATA2,	0x0734, 0x034C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__ECSPI5_SS1,	0x0734, 0x034C, 1, 0x0838, 1, 0)
+MX6_PAD_DECL(SD1_DAT2__GPT_COMPARE2,	0x0734, 0x034C, 2, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__PWM2_OUT,	0x0734, 0x034C, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_B,	0x0734, 0x034C, 4, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__GPIO1_IO19,	0x0734, 0x034C, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_DAT2__WDOG1_RESET_B_DEB,	0x0734, 0x034C, 6, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__SD1_CLK,	0x0738, 0x0350, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__ECSPI5_SCLK,	0x0738, 0x0350, 1, 0x0828, 0, 0)
+MX6_PAD_DECL(SD1_CLK__GPT_CLKIN,	0x0738, 0x0350, 3, 0x0000, 0, 0)
+MX6_PAD_DECL(SD1_CLK__GPIO1_IO20,	0x0738, 0x0350, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CLK__SD2_CLK,	0x073C, 0x0354, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CLK__ECSPI5_SCLK,	0x073C, 0x0354, 1, 0x0828, 1, 0)
+MX6_PAD_DECL(SD2_CLK__KEY_COL5,	0x073C, 0x0354, 2, 0x08E8, 3, 0)
+MX6_PAD_DECL(SD2_CLK__AUD4_RXFS,	0x073C, 0x0354, 3, 0x07C0, 1, 0)
+MX6_PAD_DECL(SD2_CLK__GPIO1_IO10,	0x073C, 0x0354, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__SD2_CMD,		0x0740, 0x0358, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_CMD__ECSPI5_MOSI,	0x0740, 0x0358, 1, 0x0830, 1, 0)
+MX6_PAD_DECL(SD2_CMD__KEY_ROW5,	0x0740, 0x0358, 2, 0x08F4, 2, 0)
+MX6_PAD_DECL(SD2_CMD__AUD4_RXC,	0x0740, 0x0358, 3, 0x07BC, 1, 0)
+MX6_PAD_DECL(SD2_CMD__GPIO1_IO11,	0x0740, 0x0358, 5, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__SD2_DATA3,	0x0744, 0x035C, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__ECSPI5_SS3,	0x0744, 0x035C, 1, 0x0000, 0, 0)
+MX6_PAD_DECL(SD2_DAT3__KEY_COL6,	0x0744, 0x035C, 2, 0x08EC, 2, 0)
+MX6_PAD_DECL(SD2_DAT3__AUD4_TXC,	0x0744, 0x035C, 3, 0x07C4, 1, 0)
+MX6_PAD_DECL(SD2_DAT3__GPIO1_IO12,	0x0744, 0x035C, 5, 0x0000, 0, 0)
+
+#endif	/* __ASM_ARCH_MX6_MX6Q_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h
new file mode 100644
index 0000000..d397c8a
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sl-ddr.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_MX6SL_DDR_H__
+#define __ASM_ARCH_MX6SL_DDR_H__
+
+#ifndef CONFIG_MX6SL
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_CAS_B	0x020e0300
+#define MX6_IOM_DRAM_CS0_B	0x020e0304
+#define MX6_IOM_DRAM_CS1_B	0x020e0308
+
+#define MX6_IOM_DRAM_DQM0	0x020e030c
+#define MX6_IOM_DRAM_DQM1	0x020e0310
+#define MX6_IOM_DRAM_DQM2	0x020e0314
+#define MX6_IOM_DRAM_DQM3	0x020e0318
+
+#define MX6_IOM_DRAM_RAS_B	0x020e031c
+#define MX6_IOM_DRAM_RESET	0x020e0320
+
+#define MX6_IOM_DRAM_SDBA0	0x020e0324
+#define MX6_IOM_DRAM_SDBA1	0x020e0328
+#define MX6_IOM_DRAM_SDBA2	0x020e032c
+
+#define MX6_IOM_DRAM_SDCKE0	0x020e0330
+#define MX6_IOM_DRAM_SDCKE1	0x020e0334
+
+#define MX6_IOM_DRAM_SDCLK0_P	0x020e0338
+
+#define MX6_IOM_DRAM_ODT0	0x020e033c
+#define MX6_IOM_DRAM_ODT1	0x020e0340
+
+#define MX6_IOM_DRAM_SDQS0_P	0x020e0344
+#define MX6_IOM_DRAM_SDQS1_P	0x020e0348
+#define MX6_IOM_DRAM_SDQS2_P	0x020e034c
+#define MX6_IOM_DRAM_SDQS3_P	0x020e0350
+
+#define MX6_IOM_DRAM_SDWE_B	0x020e0354
+
+#endif /*__ASM_ARCH_MX6SL_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
new file mode 100644
index 0000000..01b14d7
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__
+#define __ASM_ARCH_MX6_MX6SL_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+	MX6_PAD_ECSPI1_MISO__ECSPI_MISO				= IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0),
+	MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI				= IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
+	MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK				= IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
+	MX6_PAD_ECSPI1_SS0__GPIO4_IO11				= IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__USDHC1_CLK					= IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__USDHC1_CMD					= IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT0__USDHC1_DAT0				= IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT1__USDHC1_DAT1				= IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT2__USDHC1_DAT2				= IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT3__USDHC1_DAT3				= IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT4__USDHC1_DAT4				= IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT5__USDHC1_DAT5				= IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT5__GPIO_5_9				= IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT6__USDHC1_DAT6				= IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DAT7__USDHC1_DAT7				= IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW7__GPIO_4_7					= IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
+	MX6_PAD_SD2_CLK__USDHC2_CLK				= IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_CMD__USDHC2_CMD				= IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT0__USDHC2_DAT0				= IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT1__USDHC2_DAT1				= IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT2__USDHC2_DAT2				= IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT3__USDHC2_DAT3				= IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DAT4__USDHC2_DAT4				= IOMUX_PAD(0X0574, 0X026C, 0, 0X0000, 0, 0),
+	MX6_PAD_SD2_DAT5__USDHC2_DAT5				= IOMUX_PAD(0X0578, 0X0270, 0, 0X0000, 0, 0),
+	MX6_PAD_SD2_DAT6__USDHC2_DAT6				= IOMUX_PAD(0X057C, 0X0274, 0, 0X0000, 0, 0),
+	MX6_PAD_SD2_DAT7__USDHC2_DAT7				= IOMUX_PAD(0X0580, 0X0278, 0, 0X0000, 0, 0),
+	MX6_PAD_SD2_DAT7__GPIO_5_0					= IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
+	MX6_PAD_SD2_RST__USDHC2_RST				= IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_CLK__USDHC3_CLK					= IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_CMD__USDHC3_CMD					= IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT0__USDHC3_DAT0				= IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT1__USDHC3_DAT1				= IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT2__USDHC3_DAT2				= IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DAT3__USDHC3_DAT3				= IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0),
+	MX6_PAD_REF_CLK_32K__GPIO_3_22				= IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0),
+	MX6_PAD_UART1_RXD__UART1_RXD				= IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
+	MX6_PAD_UART1_TXD__UART1_TXD				= IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
+
+	MX6_PAD_FEC_MDC__FEC_MDC				= IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_MDIO__FEC_MDIO				= IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0),
+	MX6_PAD_FEC_CRS_DV__FEC_RX_DV				= IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0),
+	MX6_PAD_FEC_RXD0__FEC_RX_DATA0				= IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0),
+	MX6_PAD_FEC_RXD1__FEC_RX_DATA1				= IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0),
+	MX6_PAD_FEC_TX_EN__FEC_TX_EN				= IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_TXD0__FEC_TX_DATA0				= IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_TXD1__FEC_TX_DATA1				= IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT			= IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
+	MX6_PAD_FEC_RX_ER__GPIO_4_19				= IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
+	MX6_PAD_FEC_TX_CLK__GPIO_4_21				= IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID			= IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
+
+	MX6_PAD_KEY_COL4__USB_USBOTG1_PWR			= IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL5__USB_USBOTG2_PWR			= IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
+
+	MX6_PAD_I2C1_SDA__I2C1_SDA				= IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
+	MX6_PAD_I2C1_SDA__GPIO_3_13				= IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
+	MX6_PAD_I2C1_SCL__I2C1_SCL				= IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
+	MX6_PAD_I2C1_SCL__GPIO_3_12				= IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
+};
+#endif	/* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6sll_pins.h b/arch/arm/include/asm/arch-mx6/mx6sll_pins.h
new file mode 100644
index 0000000..e4bd4ef
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sll_pins.h
@@ -0,0 +1,1018 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 - 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_IMX6SLL_PINS_H__
+#define __ASM_ARCH_IMX6SLL_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+	MX6_PAD_WDOG_B__WDOG1_B                               = IOMUX_PAD(0x02DC, 0x0014, 0, 0x0000, 0, 0),
+	MX6_PAD_WDOG_B__WDOG1_RESET_B_DEB                     = IOMUX_PAD(0x02DC, 0x0014, 1, 0x0000, 0, 0),
+	MX6_PAD_WDOG_B__UART5_RI_B                            = IOMUX_PAD(0x02DC, 0x0014, 2, 0x0000, 0, 0),
+	MX6_PAD_WDOG_B__GPIO3_IO18                            = IOMUX_PAD(0x02DC, 0x0014, 5, 0x0000, 0, 0),
+
+	MX6_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M              = IOMUX_PAD(0x02E0, 0x0018, 0, 0x0000, 0, 0),
+	MX6_PAD_REF_CLK_24M__I2C3_SCL                         = IOMUX_PAD(0x02E0, 0x0018, IOMUX_CONFIG_SION | 1, 0x068C, 0, 0),
+	MX6_PAD_REF_CLK_24M__PWM3_OUT                         = IOMUX_PAD(0x02E0, 0x0018, 2, 0x0000, 0, 0),
+	MX6_PAD_REF_CLK_24M__USB_OTG2_ID                      = IOMUX_PAD(0x02E0, 0x0018, 3, 0x0560, 0, 0),
+	MX6_PAD_REF_CLK_24M__CCM_PMIC_READY                   = IOMUX_PAD(0x02E0, 0x0018, 4, 0x05AC, 0, 0),
+	MX6_PAD_REF_CLK_24M__GPIO3_IO21                       = IOMUX_PAD(0x02E0, 0x0018, 5, 0x0000, 0, 0),
+	MX6_PAD_REF_CLK_24M__SD3_WP                           = IOMUX_PAD(0x02E0, 0x0018, 6, 0x0794, 0, 0),
+
+	MX6_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K              = IOMUX_PAD(0x02E4, 0x001C, 0, 0x0000, 0, 0),
+	MX6_PAD_REF_CLK_32K__I2C3_SDA                         = IOMUX_PAD(0x02E4, 0x001C, IOMUX_CONFIG_SION | 1, 0x0690, 0, 0),
+	MX6_PAD_REF_CLK_32K__PWM4_OUT                         = IOMUX_PAD(0x02E4, 0x001C, 2, 0x0000, 0, 0),
+	MX6_PAD_REF_CLK_32K__USB_OTG1_ID                      = IOMUX_PAD(0x02E4, 0x001C, 3, 0x055C, 0, 0),
+	MX6_PAD_REF_CLK_32K__SD1_LCTL                         = IOMUX_PAD(0x02E4, 0x001C, 4, 0x0000, 0, 0),
+	MX6_PAD_REF_CLK_32K__GPIO3_IO22                       = IOMUX_PAD(0x02E4, 0x001C, 5, 0x0000, 0, 0),
+	MX6_PAD_REF_CLK_32K__SD3_CD_B                         = IOMUX_PAD(0x02E4, 0x001C, 6, 0x0780, 0, 0),
+
+	MX6_PAD_PWM1__PWM1_OUT                                = IOMUX_PAD(0x02E8, 0x0020, 0, 0x0000, 0, 0),
+	MX6_PAD_PWM1__CCM_CLKO                                = IOMUX_PAD(0x02E8, 0x0020, 1, 0x0000, 0, 0),
+	MX6_PAD_PWM1__AUDIO_CLK_OUT                           = IOMUX_PAD(0x02E8, 0x0020, 2, 0x0000, 0, 0),
+	MX6_PAD_PWM1__CSI_MCLK                                = IOMUX_PAD(0x02E8, 0x0020, 4, 0x0000, 0, 0),
+	MX6_PAD_PWM1__GPIO3_IO23                              = IOMUX_PAD(0x02E8, 0x0020, 5, 0x0000, 0, 0),
+	MX6_PAD_PWM1__EPIT1_OUT                               = IOMUX_PAD(0x02E8, 0x0020, 6, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_COL0__KEY_COL0                            = IOMUX_PAD(0x02EC, 0x0024, 0, 0x06A0, 0, 0),
+	MX6_PAD_KEY_COL0__I2C2_SCL                            = IOMUX_PAD(0x02EC, 0x0024, IOMUX_CONFIG_SION | 1, 0x0684, 0, 0),
+	MX6_PAD_KEY_COL0__LCD_DATA00                          = IOMUX_PAD(0x02EC, 0x0024, 2, 0x06D8, 0, 0),
+	MX6_PAD_KEY_COL0__SD1_CD_B                            = IOMUX_PAD(0x02EC, 0x0024, 4, 0x0770, 1, 0),
+	MX6_PAD_KEY_COL0__GPIO3_IO24                          = IOMUX_PAD(0x02EC, 0x0024, 5, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_ROW0__KEY_ROW0                            = IOMUX_PAD(0x02F0, 0x0028, 0, 0x06C0, 0, 0),
+	MX6_PAD_KEY_ROW0__I2C2_SDA                            = IOMUX_PAD(0x02F0, 0x0028, IOMUX_CONFIG_SION | 1, 0x0688, 0, 0),
+	MX6_PAD_KEY_ROW0__LCD_DATA01                          = IOMUX_PAD(0x02F0, 0x0028, 2, 0x06DC, 0, 0),
+	MX6_PAD_KEY_ROW0__SD1_WP                              = IOMUX_PAD(0x02F0, 0x0028, 4, 0x0774, 1, 0),
+	MX6_PAD_KEY_ROW0__GPIO3_IO25                          = IOMUX_PAD(0x02F0, 0x0028, 5, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_COL1__KEY_COL1                            = IOMUX_PAD(0x02F4, 0x002C, 0, 0x06A4, 0, 0),
+	MX6_PAD_KEY_COL1__ECSPI4_MOSI                         = IOMUX_PAD(0x02F4, 0x002C, 1, 0x0658, 1, 0),
+	MX6_PAD_KEY_COL1__LCD_DATA02                          = IOMUX_PAD(0x02F4, 0x002C, 2, 0x06E0, 0, 0),
+	MX6_PAD_KEY_COL1__SD3_DATA4                           = IOMUX_PAD(0x02F4, 0x002C, 4, 0x0784, 0, 0),
+	MX6_PAD_KEY_COL1__GPIO3_IO26                          = IOMUX_PAD(0x02F4, 0x002C, 5, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_ROW1__KEY_ROW1                            = IOMUX_PAD(0x02F8, 0x0030, 0, 0x06C4, 0, 0),
+	MX6_PAD_KEY_ROW1__ECSPI4_MISO                         = IOMUX_PAD(0x02F8, 0x0030, 1, 0x0654, 1, 0),
+	MX6_PAD_KEY_ROW1__LCD_DATA03                          = IOMUX_PAD(0x02F8, 0x0030, 2, 0x06E4, 0, 0),
+	MX6_PAD_KEY_ROW1__CSI_FIELD                           = IOMUX_PAD(0x02F8, 0x0030, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW1__SD3_DATA5                           = IOMUX_PAD(0x02F8, 0x0030, 4, 0x0788, 0, 0),
+	MX6_PAD_KEY_ROW1__GPIO3_IO27                          = IOMUX_PAD(0x02F8, 0x0030, 5, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_COL2__KEY_COL2                            = IOMUX_PAD(0x02FC, 0x0034, 0, 0x06A8, 0, 0),
+	MX6_PAD_KEY_COL2__ECSPI4_SS0                          = IOMUX_PAD(0x02FC, 0x0034, 1, 0x065C, 1, 0),
+	MX6_PAD_KEY_COL2__LCD_DATA04                          = IOMUX_PAD(0x02FC, 0x0034, 2, 0x06E8, 0, 0),
+	MX6_PAD_KEY_COL2__CSI_DATA12                          = IOMUX_PAD(0x02FC, 0x0034, 3, 0x05B8, 1, 0),
+	MX6_PAD_KEY_COL2__SD3_DATA6                           = IOMUX_PAD(0x02FC, 0x0034, 4, 0x078C, 0, 0),
+	MX6_PAD_KEY_COL2__GPIO3_IO28                          = IOMUX_PAD(0x02FC, 0x0034, 5, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_ROW2__KEY_ROW2                            = IOMUX_PAD(0x0300, 0x0038, 0, 0x06C8, 0, 0),
+	MX6_PAD_KEY_ROW2__ECSPI4_SCLK                         = IOMUX_PAD(0x0300, 0x0038, 1, 0x0650, 1, 0),
+	MX6_PAD_KEY_ROW2__LCD_DATA05                          = IOMUX_PAD(0x0300, 0x0038, 2, 0x06EC, 0, 0),
+	MX6_PAD_KEY_ROW2__CSI_DATA13                          = IOMUX_PAD(0x0300, 0x0038, 3, 0x05BC, 1, 0),
+	MX6_PAD_KEY_ROW2__SD3_DATA7                           = IOMUX_PAD(0x0300, 0x0038, 4, 0x0790, 0, 0),
+	MX6_PAD_KEY_ROW2__GPIO3_IO29                          = IOMUX_PAD(0x0300, 0x0038, 5, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_COL3__KEY_COL3                            = IOMUX_PAD(0x0304, 0x003C, 0, 0x06AC, 0, 0),
+	MX6_PAD_KEY_COL3__AUD6_RXFS                           = IOMUX_PAD(0x0304, 0x003C, 1, 0x05A0, 1, 0),
+	MX6_PAD_KEY_COL3__LCD_DATA06                          = IOMUX_PAD(0x0304, 0x003C, 2, 0x06F0, 0, 0),
+	MX6_PAD_KEY_COL3__CSI_DATA14                          = IOMUX_PAD(0x0304, 0x003C, 3, 0x05C0, 1, 0),
+	MX6_PAD_KEY_COL3__GPIO3_IO30                          = IOMUX_PAD(0x0304, 0x003C, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL3__SD1_RESET                           = IOMUX_PAD(0x0304, 0x003C, 6, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_ROW3__KEY_ROW3                            = IOMUX_PAD(0x0308, 0x0040, 0, 0x06CC, 1, 0),
+	MX6_PAD_KEY_ROW3__AUD6_RXC                            = IOMUX_PAD(0x0308, 0x0040, 1, 0x059C, 1, 0),
+	MX6_PAD_KEY_ROW3__LCD_DATA07                          = IOMUX_PAD(0x0308, 0x0040, 2, 0x06F4, 1, 0),
+	MX6_PAD_KEY_ROW3__CSI_DATA15                          = IOMUX_PAD(0x0308, 0x0040, 3, 0x05C4, 2, 0),
+	MX6_PAD_KEY_ROW3__GPIO3_IO31                          = IOMUX_PAD(0x0308, 0x0040, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW3__SD1_VSELECT                         = IOMUX_PAD(0x0308, 0x0040, 6, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_COL4__KEY_COL4                            = IOMUX_PAD(0x030C, 0x0044, 0, 0x06B0, 1, 0),
+	MX6_PAD_KEY_COL4__AUD6_RXD                            = IOMUX_PAD(0x030C, 0x0044, 1, 0x0594, 1, 0),
+	MX6_PAD_KEY_COL4__LCD_DATA08                          = IOMUX_PAD(0x030C, 0x0044, 2, 0x06F8, 1, 0),
+	MX6_PAD_KEY_COL4__CSI_DATA16                          = IOMUX_PAD(0x030C, 0x0044, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL4__GPIO4_IO00                          = IOMUX_PAD(0x030C, 0x0044, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL4__USB_OTG1_PWR                        = IOMUX_PAD(0x030C, 0x0044, 6, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_ROW4__KEY_ROW4                            = IOMUX_PAD(0x0310, 0x0048, 0, 0x06D0, 1, 0),
+	MX6_PAD_KEY_ROW4__AUD6_TXC                            = IOMUX_PAD(0x0310, 0x0048, 1, 0x05A4, 1, 0),
+	MX6_PAD_KEY_ROW4__LCD_DATA09                          = IOMUX_PAD(0x0310, 0x0048, 2, 0x06FC, 1, 0),
+	MX6_PAD_KEY_ROW4__CSI_DATA17                          = IOMUX_PAD(0x0310, 0x0048, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW4__GPIO4_IO01                          = IOMUX_PAD(0x0310, 0x0048, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW4__USB_OTG1_OC                         = IOMUX_PAD(0x0310, 0x0048, 6, 0x076C, 2, 0),
+
+	MX6_PAD_KEY_COL5__KEY_COL5                            = IOMUX_PAD(0x0314, 0x004C, 0, 0x0694, 1, 0),
+	MX6_PAD_KEY_COL5__AUD6_TXFS                           = IOMUX_PAD(0x0314, 0x004C, 1, 0x05A8, 1, 0),
+	MX6_PAD_KEY_COL5__LCD_DATA10                          = IOMUX_PAD(0x0314, 0x004C, 2, 0x0700, 0, 0),
+	MX6_PAD_KEY_COL5__CSI_DATA18                          = IOMUX_PAD(0x0314, 0x004C, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL5__GPIO4_IO02                          = IOMUX_PAD(0x0314, 0x004C, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL5__USB_OTG2_PWR                        = IOMUX_PAD(0x0314, 0x004C, 6, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_ROW5__KEY_ROW5                            = IOMUX_PAD(0x0318, 0x0050, 0, 0x06B4, 2, 0),
+	MX6_PAD_KEY_ROW5__AUD6_TXD                            = IOMUX_PAD(0x0318, 0x0050, 1, 0x0598, 1, 0),
+	MX6_PAD_KEY_ROW5__LCD_DATA11                          = IOMUX_PAD(0x0318, 0x0050, 2, 0x0704, 1, 0),
+	MX6_PAD_KEY_ROW5__CSI_DATA19                          = IOMUX_PAD(0x0318, 0x0050, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW5__GPIO4_IO03                          = IOMUX_PAD(0x0318, 0x0050, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW5__USB_OTG2_OC                         = IOMUX_PAD(0x0318, 0x0050, 6, 0x0768, 3, 0),
+
+	MX6_PAD_KEY_COL6__KEY_COL6                            = IOMUX_PAD(0x031C, 0x0054, 0, 0x0698, 2, 0),
+	MX6_PAD_KEY_COL6__UART4_DCE_RX                        = IOMUX_PAD(0x031C, 0x0054, 1, 0x075C, 2, 0),
+	MX6_PAD_KEY_COL6__UART4_DTE_TX                        = IOMUX_PAD(0x031C, 0x0054, 1, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL6__LCD_DATA12                          = IOMUX_PAD(0x031C, 0x0054, 2, 0x0708, 1, 0),
+	MX6_PAD_KEY_COL6__CSI_DATA20                          = IOMUX_PAD(0x031C, 0x0054, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL6__GPIO4_IO04                          = IOMUX_PAD(0x031C, 0x0054, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL6__SD3_RESET                           = IOMUX_PAD(0x031C, 0x0054, 6, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_ROW6__KEY_ROW6                            = IOMUX_PAD(0x0320, 0x0058, 0, 0x06B8, 2, 0),
+	MX6_PAD_KEY_ROW6__UART4_DCE_TX                        = IOMUX_PAD(0x0320, 0x0058, 1, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW6__UART4_DTE_RX                        = IOMUX_PAD(0x0320, 0x0058, 1, 0x075C, 3, 0),
+	MX6_PAD_KEY_ROW6__LCD_DATA13                          = IOMUX_PAD(0x0320, 0x0058, 2, 0x070C, 1, 0),
+	MX6_PAD_KEY_ROW6__CSI_DATA21                          = IOMUX_PAD(0x0320, 0x0058, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW6__GPIO4_IO05                          = IOMUX_PAD(0x0320, 0x0058, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW6__SD3_VSELECT                         = IOMUX_PAD(0x0320, 0x0058, 6, 0x0000, 0, 0),
+
+	MX6_PAD_KEY_COL7__KEY_COL7                            = IOMUX_PAD(0x0324, 0x005C, 0, 0x069C, 2, 0),
+	MX6_PAD_KEY_COL7__UART4_DCE_RTS                       = IOMUX_PAD(0x0324, 0x005C, 1, 0x0758, 2, 0),
+	MX6_PAD_KEY_COL7__UART4_DTE_CTS                       = IOMUX_PAD(0x0324, 0x005C, 1, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL7__LCD_DATA14                          = IOMUX_PAD(0x0324, 0x005C, 2, 0x0710, 1, 0),
+	MX6_PAD_KEY_COL7__CSI_DATA22                          = IOMUX_PAD(0x0324, 0x005C, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL7__GPIO4_IO06                          = IOMUX_PAD(0x0324, 0x005C, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL7__SD1_WP                              = IOMUX_PAD(0x0324, 0x005C, 6, 0x0774, 3, 0),
+
+	MX6_PAD_KEY_ROW7__KEY_ROW7                            = IOMUX_PAD(0x0328, 0x0060, 0, 0x06BC, 2, 0),
+	MX6_PAD_KEY_ROW7__UART4_DCE_CTS                       = IOMUX_PAD(0x0328, 0x0060, 1, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW7__UART4_DTE_RTS                       = IOMUX_PAD(0x0328, 0x0060, 1, 0x0758, 3, 0),
+	MX6_PAD_KEY_ROW7__LCD_DATA15                          = IOMUX_PAD(0x0328, 0x0060, 2, 0x0714, 1, 0),
+	MX6_PAD_KEY_ROW7__CSI_DATA23                          = IOMUX_PAD(0x0328, 0x0060, 3, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW7__GPIO4_IO07                          = IOMUX_PAD(0x0328, 0x0060, 5, 0x0000, 0, 0),
+	MX6_PAD_KEY_ROW7__SD1_CD_B                            = IOMUX_PAD(0x0328, 0x0060, 6, 0x0770, 3, 0),
+
+	MX6_PAD_EPDC_DATA00__EPDC_DATA00                      = IOMUX_PAD(0x032C, 0x0064, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA00__ECSPI4_MOSI                      = IOMUX_PAD(0x032C, 0x0064, 1, 0x0658, 2, 0),
+	MX6_PAD_EPDC_DATA00__LCD_DATA24                       = IOMUX_PAD(0x032C, 0x0064, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA00__CSI_DATA00                       = IOMUX_PAD(0x032C, 0x0064, 3, 0x05C8, 2, 0),
+	MX6_PAD_EPDC_DATA00__GPIO1_IO07                       = IOMUX_PAD(0x032C, 0x0064, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA01__EPDC_DATA01                      = IOMUX_PAD(0x0330, 0x0068, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA01__ECSPI4_MISO                      = IOMUX_PAD(0x0330, 0x0068, 1, 0x0654, 2, 0),
+	MX6_PAD_EPDC_DATA01__LCD_DATA25                       = IOMUX_PAD(0x0330, 0x0068, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA01__CSI_DATA01                       = IOMUX_PAD(0x0330, 0x0068, 3, 0x05CC, 2, 0),
+	MX6_PAD_EPDC_DATA01__GPIO1_IO08                       = IOMUX_PAD(0x0330, 0x0068, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA02__EPDC_DATA02                      = IOMUX_PAD(0x0334, 0x006C, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA02__ECSPI4_SS0                       = IOMUX_PAD(0x0334, 0x006C, 1, 0x065C, 2, 0),
+	MX6_PAD_EPDC_DATA02__LCD_DATA26                       = IOMUX_PAD(0x0334, 0x006C, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA02__CSI_DATA02                       = IOMUX_PAD(0x0334, 0x006C, 3, 0x05D0, 2, 0),
+	MX6_PAD_EPDC_DATA02__GPIO1_IO09                       = IOMUX_PAD(0x0334, 0x006C, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA03__EPDC_DATA03                      = IOMUX_PAD(0x0338, 0x0070, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA03__ECSPI4_SCLK                      = IOMUX_PAD(0x0338, 0x0070, 1, 0x0650, 2, 0),
+	MX6_PAD_EPDC_DATA03__LCD_DATA27                       = IOMUX_PAD(0x0338, 0x0070, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA03__CSI_DATA03                       = IOMUX_PAD(0x0338, 0x0070, 3, 0x05D4, 2, 0),
+	MX6_PAD_EPDC_DATA03__GPIO1_IO10                       = IOMUX_PAD(0x0338, 0x0070, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA04__EPDC_DATA04                      = IOMUX_PAD(0x033C, 0x0074, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA04__ECSPI4_SS1                       = IOMUX_PAD(0x033C, 0x0074, 1, 0x0660, 1, 0),
+	MX6_PAD_EPDC_DATA04__LCD_DATA28                       = IOMUX_PAD(0x033C, 0x0074, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA04__CSI_DATA04                       = IOMUX_PAD(0x033C, 0x0074, 3, 0x05D8, 2, 0),
+	MX6_PAD_EPDC_DATA04__GPIO1_IO11                       = IOMUX_PAD(0x033C, 0x0074, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA05__EPDC_DATA05                      = IOMUX_PAD(0x0340, 0x0078, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA05__ECSPI4_SS2                       = IOMUX_PAD(0x0340, 0x0078, 1, 0x0664, 1, 0),
+	MX6_PAD_EPDC_DATA05__LCD_DATA29                       = IOMUX_PAD(0x0340, 0x0078, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA05__CSI_DATA05                       = IOMUX_PAD(0x0340, 0x0078, 3, 0x05DC, 2, 0),
+	MX6_PAD_EPDC_DATA05__GPIO1_IO12                       = IOMUX_PAD(0x0340, 0x0078, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA06__EPDC_DATA06                      = IOMUX_PAD(0x0344, 0x007C, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA06__ECSPI4_SS3                       = IOMUX_PAD(0x0344, 0x007C, 1, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA06__LCD_DATA30                       = IOMUX_PAD(0x0344, 0x007C, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA06__CSI_DATA06                       = IOMUX_PAD(0x0344, 0x007C, 3, 0x05E0, 2, 0),
+	MX6_PAD_EPDC_DATA06__GPIO1_IO13                       = IOMUX_PAD(0x0344, 0x007C, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA07__EPDC_DATA07                      = IOMUX_PAD(0x0348, 0x0080, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA07__ECSPI4_RDY                       = IOMUX_PAD(0x0348, 0x0080, 1, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA07__LCD_DATA31                       = IOMUX_PAD(0x0348, 0x0080, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA07__CSI_DATA07                       = IOMUX_PAD(0x0348, 0x0080, 3, 0x05E4, 2, 0),
+	MX6_PAD_EPDC_DATA07__GPIO1_IO14                       = IOMUX_PAD(0x0348, 0x0080, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA08__EPDC_DATA08                      = IOMUX_PAD(0x034C, 0x0084, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA08__ECSPI3_MOSI                      = IOMUX_PAD(0x034C, 0x0084, 1, 0x063C, 2, 0),
+	MX6_PAD_EPDC_DATA08__EPDC_PWR_CTRL0                   = IOMUX_PAD(0x034C, 0x0084, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA08__GPIO1_IO15                       = IOMUX_PAD(0x034C, 0x0084, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA09__EPDC_DATA09                      = IOMUX_PAD(0x0350, 0x0088, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA09__ECSPI3_MISO                      = IOMUX_PAD(0x0350, 0x0088, 1, 0x0638, 2, 0),
+	MX6_PAD_EPDC_DATA09__EPDC_PWR_CTRL1                   = IOMUX_PAD(0x0350, 0x0088, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA09__GPIO1_IO16                       = IOMUX_PAD(0x0350, 0x0088, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA10__EPDC_DATA10                      = IOMUX_PAD(0x0354, 0x008C, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA10__ECSPI3_SS0                       = IOMUX_PAD(0x0354, 0x008C, 1, 0x0648, 2, 0),
+	MX6_PAD_EPDC_DATA10__EPDC_PWR_CTRL2                   = IOMUX_PAD(0x0354, 0x008C, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA10__GPIO1_IO17                       = IOMUX_PAD(0x0354, 0x008C, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA11__EPDC_DATA11                      = IOMUX_PAD(0x0358, 0x0090, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA11__ECSPI3_SCLK                      = IOMUX_PAD(0x0358, 0x0090, 1, 0x0630, 2, 0),
+	MX6_PAD_EPDC_DATA11__EPDC_PWR_CTRL3                   = IOMUX_PAD(0x0358, 0x0090, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA11__GPIO1_IO18                       = IOMUX_PAD(0x0358, 0x0090, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_DATA12__EPDC_DATA12                      = IOMUX_PAD(0x035C, 0x0094, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA12__UART2_DCE_RX                     = IOMUX_PAD(0x035C, 0x0094, 1, 0x074C, 4, 0),
+	MX6_PAD_EPDC_DATA12__UART2_DTE_TX                     = IOMUX_PAD(0x035C, 0x0094, 1, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA12__EPDC_PWR_COM                     = IOMUX_PAD(0x035C, 0x0094, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA12__GPIO1_IO19                       = IOMUX_PAD(0x035C, 0x0094, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA12__ECSPI3_SS1                       = IOMUX_PAD(0x035C, 0x0094, 6, 0x064C, 1, 0),
+
+	MX6_PAD_EPDC_DATA13__EPDC_DATA13                      = IOMUX_PAD(0x0360, 0x0098, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA13__UART2_DCE_TX                     = IOMUX_PAD(0x0360, 0x0098, 1, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA13__UART2_DTE_RX                     = IOMUX_PAD(0x0360, 0x0098, 1, 0x074C, 5, 0),
+	MX6_PAD_EPDC_DATA13__EPDC_PWR_IRQ                     = IOMUX_PAD(0x0360, 0x0098, 2, 0x0668, 0, 0),
+	MX6_PAD_EPDC_DATA13__GPIO1_IO20                       = IOMUX_PAD(0x0360, 0x0098, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA13__ECSPI3_SS2                       = IOMUX_PAD(0x0360, 0x0098, 6, 0x0640, 1, 0),
+
+	MX6_PAD_EPDC_DATA14__EPDC_DATA14                      = IOMUX_PAD(0x0364, 0x009C, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA14__UART2_DCE_RTS                    = IOMUX_PAD(0x0364, 0x009C, 1, 0x0748, 4, 0),
+	MX6_PAD_EPDC_DATA14__UART2_DTE_CTS                    = IOMUX_PAD(0x0364, 0x009C, 1, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA14__EPDC_PWR_STAT                    = IOMUX_PAD(0x0364, 0x009C, 2, 0x066C, 0, 0),
+	MX6_PAD_EPDC_DATA14__GPIO1_IO21                       = IOMUX_PAD(0x0364, 0x009C, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA14__ECSPI3_SS3                       = IOMUX_PAD(0x0364, 0x009C, 6, 0x0644, 1, 0),
+
+	MX6_PAD_EPDC_DATA15__EPDC_DATA15                      = IOMUX_PAD(0x0368, 0x00A0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA15__UART2_DCE_CTS                    = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA15__UART2_DTE_RTS                    = IOMUX_PAD(0x0368, 0x00A0, 1, 0x0748, 5, 0),
+	MX6_PAD_EPDC_DATA15__EPDC_PWR_WAKE                    = IOMUX_PAD(0x0368, 0x00A0, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA15__GPIO1_IO22                       = IOMUX_PAD(0x0368, 0x00A0, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_DATA15__ECSPI3_RDY                       = IOMUX_PAD(0x0368, 0x00A0, 6, 0x0634, 1, 0),
+
+	MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P                      = IOMUX_PAD(0x036C, 0x00A4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCLK__ECSPI2_MOSI                       = IOMUX_PAD(0x036C, 0x00A4, 1, 0x0624, 2, 0),
+	MX6_PAD_EPDC_SDCLK__I2C2_SCL                          = IOMUX_PAD(0x036C, 0x00A4, IOMUX_CONFIG_SION | 2, 0x0684, 2, 0),
+	MX6_PAD_EPDC_SDCLK__CSI_DATA08                        = IOMUX_PAD(0x036C, 0x00A4, 3, 0x05E8, 2, 0),
+	MX6_PAD_EPDC_SDCLK__GPIO1_IO23                        = IOMUX_PAD(0x036C, 0x00A4, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_SDLE__EPDC_SDLE                          = IOMUX_PAD(0x0370, 0x00A8, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDLE__ECSPI2_MISO                        = IOMUX_PAD(0x0370, 0x00A8, 1, 0x0620, 2, 0),
+	MX6_PAD_EPDC_SDLE__I2C2_SDA                           = IOMUX_PAD(0x0370, 0x00A8, IOMUX_CONFIG_SION | 2, 0x0688, 2, 0),
+	MX6_PAD_EPDC_SDLE__CSI_DATA09                         = IOMUX_PAD(0x0370, 0x00A8, 3, 0x05EC, 2, 0),
+	MX6_PAD_EPDC_SDLE__GPIO1_IO24                         = IOMUX_PAD(0x0370, 0x00A8, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_SDOE__EPDC_SDOE                          = IOMUX_PAD(0x0374, 0x00AC, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDOE__ECSPI2_SS0                         = IOMUX_PAD(0x0374, 0x00AC, 1, 0x0628, 1, 0),
+	MX6_PAD_EPDC_SDOE__CSI_DATA10                         = IOMUX_PAD(0x0374, 0x00AC, 3, 0x05B0, 2, 0),
+	MX6_PAD_EPDC_SDOE__GPIO1_IO25                         = IOMUX_PAD(0x0374, 0x00AC, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_SDSHR__EPDC_SDSHR                        = IOMUX_PAD(0x0378, 0x00B0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDSHR__ECSPI2_SCLK                       = IOMUX_PAD(0x0378, 0x00B0, 1, 0x061C, 2, 0),
+	MX6_PAD_EPDC_SDSHR__EPDC_SDCE4                        = IOMUX_PAD(0x0378, 0x00B0, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDSHR__CSI_DATA11                        = IOMUX_PAD(0x0378, 0x00B0, 3, 0x05B4, 2, 0),
+	MX6_PAD_EPDC_SDSHR__GPIO1_IO26                        = IOMUX_PAD(0x0378, 0x00B0, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_SDCE0__EPDC_SDCE0                        = IOMUX_PAD(0x037C, 0x00B4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE0__ECSPI2_SS1                        = IOMUX_PAD(0x037C, 0x00B4, 1, 0x062C, 1, 0),
+	MX6_PAD_EPDC_SDCE0__PWM3_OUT                          = IOMUX_PAD(0x037C, 0x00B4, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE0__GPIO1_IO27                        = IOMUX_PAD(0x037C, 0x00B4, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_SDCE1__EPDC_SDCE1                        = IOMUX_PAD(0x0380, 0x00B8, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE1__WDOG2_B                           = IOMUX_PAD(0x0380, 0x00B8, 1, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE1__PWM4_OUT                          = IOMUX_PAD(0x0380, 0x00B8, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE1__GPIO1_IO28                        = IOMUX_PAD(0x0380, 0x00B8, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_SDCE2__EPDC_SDCE2                        = IOMUX_PAD(0x0384, 0x00BC, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE2__I2C3_SCL                          = IOMUX_PAD(0x0384, 0x00BC, IOMUX_CONFIG_SION | 1, 0x068C, 2, 0),
+	MX6_PAD_EPDC_SDCE2__PWM1_OUT                          = IOMUX_PAD(0x0384, 0x00BC, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE2__GPIO1_IO29                        = IOMUX_PAD(0x0384, 0x00BC, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_SDCE3__EPDC_SDCE3                        = IOMUX_PAD(0x0388, 0x00C0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE3__I2C3_SDA                          = IOMUX_PAD(0x0388, 0x00C0, IOMUX_CONFIG_SION | 1, 0x0690, 2, 0),
+	MX6_PAD_EPDC_SDCE3__PWM2_OUT                          = IOMUX_PAD(0x0388, 0x00C0, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE3__GPIO1_IO30                        = IOMUX_PAD(0x0388, 0x00C0, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_GDCLK__EPDC_GDCLK                        = IOMUX_PAD(0x038C, 0x00C4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDCLK__ECSPI2_SS2                        = IOMUX_PAD(0x038C, 0x00C4, 1, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDCLK__CSI_PIXCLK                        = IOMUX_PAD(0x038C, 0x00C4, 3, 0x05F4, 2, 0),
+	MX6_PAD_EPDC_GDCLK__GPIO1_IO31                        = IOMUX_PAD(0x038C, 0x00C4, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDCLK__SD2_RESET                         = IOMUX_PAD(0x038C, 0x00C4, 6, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_GDOE__EPDC_GDOE                          = IOMUX_PAD(0x0390, 0x00C8, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDOE__ECSPI2_SS3                         = IOMUX_PAD(0x0390, 0x00C8, 1, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDOE__CSI_HSYNC                          = IOMUX_PAD(0x0390, 0x00C8, 3, 0x05F0, 2, 0),
+	MX6_PAD_EPDC_GDOE__GPIO2_IO00                         = IOMUX_PAD(0x0390, 0x00C8, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDOE__SD2_VSELECT                        = IOMUX_PAD(0x0390, 0x00C8, 6, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_GDRL__EPDC_GDRL                          = IOMUX_PAD(0x0394, 0x00CC, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDRL__ECSPI2_RDY                         = IOMUX_PAD(0x0394, 0x00CC, 1, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDRL__CSI_MCLK                           = IOMUX_PAD(0x0394, 0x00CC, 3, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDRL__GPIO2_IO01                         = IOMUX_PAD(0x0394, 0x00CC, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDRL__SD2_WP                             = IOMUX_PAD(0x0394, 0x00CC, 6, 0x077C, 2, 0),
+
+	MX6_PAD_EPDC_GDSP__EPDC_GDSP                          = IOMUX_PAD(0x0398, 0x00D0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDSP__PWM4_OUT                           = IOMUX_PAD(0x0398, 0x00D0, 1, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDSP__CSI_VSYNC                          = IOMUX_PAD(0x0398, 0x00D0, 3, 0x05F8, 2, 0),
+	MX6_PAD_EPDC_GDSP__GPIO2_IO02                         = IOMUX_PAD(0x0398, 0x00D0, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDSP__SD2_CD_B                           = IOMUX_PAD(0x0398, 0x00D0, 6, 0x0778, 2, 0),
+
+	MX6_PAD_EPDC_VCOM0__EPDC_VCOM0                        = IOMUX_PAD(0x039C, 0x00D4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_VCOM0__AUD5_RXFS                         = IOMUX_PAD(0x039C, 0x00D4, 1, 0x0588, 1, 0),
+	MX6_PAD_EPDC_VCOM0__UART3_DCE_RX                      = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0754, 4, 0),
+	MX6_PAD_EPDC_VCOM0__UART3_DTE_TX                      = IOMUX_PAD(0x039C, 0x00D4, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_VCOM0__GPIO2_IO03                        = IOMUX_PAD(0x039C, 0x00D4, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_VCOM0__EPDC_SDCE5                        = IOMUX_PAD(0x039C, 0x00D4, 6, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_VCOM1__EPDC_VCOM1                        = IOMUX_PAD(0x03A0, 0x00D8, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_VCOM1__AUD5_RXD                          = IOMUX_PAD(0x03A0, 0x00D8, 1, 0x057C, 1, 0),
+	MX6_PAD_EPDC_VCOM1__UART3_DCE_TX                      = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_VCOM1__UART3_DTE_RX                      = IOMUX_PAD(0x03A0, 0x00D8, 2, 0x0754, 5, 0),
+	MX6_PAD_EPDC_VCOM1__GPIO2_IO04                        = IOMUX_PAD(0x03A0, 0x00D8, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_VCOM1__EPDC_SDCE6                        = IOMUX_PAD(0x03A0, 0x00D8, 6, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_BDR0__EPDC_BDR0                          = IOMUX_PAD(0x03A4, 0x00DC, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_BDR0__UART3_DCE_RTS                      = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0750, 2, 0),
+	MX6_PAD_EPDC_BDR0__UART3_DTE_CTS                      = IOMUX_PAD(0x03A4, 0x00DC, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_BDR0__GPIO2_IO05                         = IOMUX_PAD(0x03A4, 0x00DC, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_BDR0__EPDC_SDCE7                         = IOMUX_PAD(0x03A4, 0x00DC, 6, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_BDR1__EPDC_BDR1                          = IOMUX_PAD(0x03A8, 0x00E0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_BDR1__UART3_DCE_CTS                      = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0000, 0, 0),
+	MX6_PAD_EPDC_BDR1__UART3_DTE_RTS                      = IOMUX_PAD(0x03A8, 0x00E0, 2, 0x0750, 3, 0),
+	MX6_PAD_EPDC_BDR1__GPIO2_IO06                         = IOMUX_PAD(0x03A8, 0x00E0, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_BDR1__EPDC_SDCE8                         = IOMUX_PAD(0x03A8, 0x00E0, 6, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0                = IOMUX_PAD(0x03AC, 0x00E4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_CTRL0__AUD5_RXC                      = IOMUX_PAD(0x03AC, 0x00E4, 1, 0x0584, 1, 0),
+	MX6_PAD_EPDC_PWR_CTRL0__LCD_DATA16                    = IOMUX_PAD(0x03AC, 0x00E4, 2, 0x0718, 1, 0),
+	MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07                    = IOMUX_PAD(0x03AC, 0x00E4, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1                = IOMUX_PAD(0x03B0, 0x00E8, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_CTRL1__AUD5_TXFS                     = IOMUX_PAD(0x03B0, 0x00E8, 1, 0x0590, 1, 0),
+	MX6_PAD_EPDC_PWR_CTRL1__LCD_DATA17                    = IOMUX_PAD(0x03B0, 0x00E8, 2, 0x071C, 1, 0),
+	MX6_PAD_EPDC_PWR_CTRL1__GPIO2_IO08                    = IOMUX_PAD(0x03B0, 0x00E8, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2                = IOMUX_PAD(0x03B4, 0x00EC, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_CTRL2__AUD5_TXD                      = IOMUX_PAD(0x03B4, 0x00EC, 1, 0x0580, 1, 0),
+	MX6_PAD_EPDC_PWR_CTRL2__LCD_DATA18                    = IOMUX_PAD(0x03B4, 0x00EC, 2, 0x0720, 1, 0),
+	MX6_PAD_EPDC_PWR_CTRL2__GPIO2_IO09                    = IOMUX_PAD(0x03B4, 0x00EC, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3                = IOMUX_PAD(0x03B8, 0x00F0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_CTRL3__AUD5_TXC                      = IOMUX_PAD(0x03B8, 0x00F0, 1, 0x058C, 1, 0),
+	MX6_PAD_EPDC_PWR_CTRL3__LCD_DATA19                    = IOMUX_PAD(0x03B8, 0x00F0, 2, 0x0724, 1, 0),
+	MX6_PAD_EPDC_PWR_CTRL3__GPIO2_IO10                    = IOMUX_PAD(0x03B8, 0x00F0, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_PWR_COM__EPDC_PWR_COM                    = IOMUX_PAD(0x03BC, 0x00F4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_COM__LCD_DATA20                      = IOMUX_PAD(0x03BC, 0x00F4, 2, 0x0728, 1, 0),
+	MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID                     = IOMUX_PAD(0x03BC, 0x00F4, 4, 0x055C, 4, 0),
+	MX6_PAD_EPDC_PWR_COM__GPIO2_IO11                      = IOMUX_PAD(0x03BC, 0x00F4, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_COM__SD3_RESET                       = IOMUX_PAD(0x03BC, 0x00F4, 6, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ                    = IOMUX_PAD(0x03C0, 0x00F8, 0, 0x0668, 1, 0),
+	MX6_PAD_EPDC_PWR_IRQ__LCD_DATA21                      = IOMUX_PAD(0x03C0, 0x00F8, 2, 0x072C, 1, 0),
+	MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID                     = IOMUX_PAD(0x03C0, 0x00F8, 4, 0x0560, 3, 0),
+	MX6_PAD_EPDC_PWR_IRQ__GPIO2_IO12                      = IOMUX_PAD(0x03C0, 0x00F8, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_IRQ__SD3_VSELECT                     = IOMUX_PAD(0x03C0, 0x00F8, 6, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT                  = IOMUX_PAD(0x03C4, 0x00FC, 0, 0x066C, 1, 0),
+	MX6_PAD_EPDC_PWR_STAT__LCD_DATA22                     = IOMUX_PAD(0x03C4, 0x00FC, 2, 0x0730, 1, 0),
+	MX6_PAD_EPDC_PWR_STAT__ARM_EVENTI                     = IOMUX_PAD(0x03C4, 0x00FC, 4, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13                     = IOMUX_PAD(0x03C4, 0x00FC, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_STAT__SD3_WP                         = IOMUX_PAD(0x03C4, 0x00FC, 6, 0x0794, 2, 0),
+
+	MX6_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE                  = IOMUX_PAD(0x03C8, 0x0100, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_WAKE__LCD_DATA23                     = IOMUX_PAD(0x03C8, 0x0100, 2, 0x0734, 1, 0),
+	MX6_PAD_EPDC_PWR_WAKE__ARM_EVENTO                     = IOMUX_PAD(0x03C8, 0x0100, 4, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14                     = IOMUX_PAD(0x03C8, 0x0100, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWR_WAKE__SD3_CD_B                       = IOMUX_PAD(0x03C8, 0x0100, 6, 0x0780, 2, 0),
+
+	MX6_PAD_LCD_CLK__LCD_CLK                              = IOMUX_PAD(0x03CC, 0x0104, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__LCD_WR_RWN                           = IOMUX_PAD(0x03CC, 0x0104, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__PWM4_OUT                             = IOMUX_PAD(0x03CC, 0x0104, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__GPIO2_IO15                           = IOMUX_PAD(0x03CC, 0x0104, 5, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_ENABLE__LCD_ENABLE                        = IOMUX_PAD(0x03D0, 0x0108, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__LCD_RD_E                          = IOMUX_PAD(0x03D0, 0x0108, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__UART2_DCE_RX                      = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__UART2_DTE_TX                      = IOMUX_PAD(0x03D0, 0x0108, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__GPIO2_IO16                        = IOMUX_PAD(0x03D0, 0x0108, 5, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_HSYNC__LCD_HSYNC                          = IOMUX_PAD(0x03D4, 0x010C, 0, 0x06D4, 0, 0),
+	MX6_PAD_LCD_HSYNC__LCD_CS                             = IOMUX_PAD(0x03D4, 0x010C, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__UART2_DCE_TX                       = IOMUX_PAD(0x03D4, 0x010C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__UART2_DTE_RX                       = IOMUX_PAD(0x03D4, 0x010C, 4, 0x074C, 1, 0),
+	MX6_PAD_LCD_HSYNC__GPIO2_IO17                         = IOMUX_PAD(0x03D4, 0x010C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__ARM_TRACE_CLK                      = IOMUX_PAD(0x03D4, 0x010C, 6, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_VSYNC__LCD_VSYNC                          = IOMUX_PAD(0x03D8, 0x0110, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__LCD_RS                             = IOMUX_PAD(0x03D8, 0x0110, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__UART2_DCE_RTS                      = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0748, 0, 0),
+	MX6_PAD_LCD_VSYNC__UART2_DTE_CTS                      = IOMUX_PAD(0x03D8, 0x0110, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__GPIO2_IO18                         = IOMUX_PAD(0x03D8, 0x0110, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__ARM_TRACE_CTL                      = IOMUX_PAD(0x03D8, 0x0110, 6, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_RESET__LCD_RESET                          = IOMUX_PAD(0x03DC, 0x0114, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__LCD_BUSY                           = IOMUX_PAD(0x03DC, 0x0114, 2, 0x06D4, 1, 0),
+	MX6_PAD_LCD_RESET__UART2_DCE_CTS                      = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__UART2_DTE_RTS                      = IOMUX_PAD(0x03DC, 0x0114, 4, 0x0748, 1, 0),
+	MX6_PAD_LCD_RESET__GPIO2_IO19                         = IOMUX_PAD(0x03DC, 0x0114, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__CCM_PMIC_READY                     = IOMUX_PAD(0x03DC, 0x0114, 6, 0x05AC, 2, 0),
+
+	MX6_PAD_LCD_DATA00__LCD_DATA00                        = IOMUX_PAD(0x03E0, 0x0118, 0, 0x06D8, 1, 0),
+	MX6_PAD_LCD_DATA00__ECSPI1_MOSI                       = IOMUX_PAD(0x03E0, 0x0118, 1, 0x0608, 0, 0),
+	MX6_PAD_LCD_DATA00__USB_OTG2_ID                       = IOMUX_PAD(0x03E0, 0x0118, 2, 0x0560, 2, 0),
+	MX6_PAD_LCD_DATA00__PWM1_OUT                          = IOMUX_PAD(0x03E0, 0x0118, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__UART5_DTR_B                       = IOMUX_PAD(0x03E0, 0x0118, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__GPIO2_IO20                        = IOMUX_PAD(0x03E0, 0x0118, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__ARM_TRACE00                       = IOMUX_PAD(0x03E0, 0x0118, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__SRC_BOOT_CFG00                    = IOMUX_PAD(0x03E0, 0x0118, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA01__LCD_DATA01                        = IOMUX_PAD(0x03E4, 0x011C, 0, 0x06DC, 1, 0),
+	MX6_PAD_LCD_DATA01__ECSPI1_MISO                       = IOMUX_PAD(0x03E4, 0x011C, 1, 0x0604, 0, 0),
+	MX6_PAD_LCD_DATA01__USB_OTG1_ID                       = IOMUX_PAD(0x03E4, 0x011C, 2, 0x055C, 3, 0),
+	MX6_PAD_LCD_DATA01__PWM2_OUT                          = IOMUX_PAD(0x03E4, 0x011C, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__AUD4_RXFS                         = IOMUX_PAD(0x03E4, 0x011C, 4, 0x0570, 0, 0),
+	MX6_PAD_LCD_DATA01__GPIO2_IO21                        = IOMUX_PAD(0x03E4, 0x011C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__ARM_TRACE01                       = IOMUX_PAD(0x03E4, 0x011C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__SRC_BOOT_CFG01                    = IOMUX_PAD(0x03E4, 0x011C, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA02__LCD_DATA02                        = IOMUX_PAD(0x03E8, 0x0120, 0, 0x06E0, 1, 0),
+	MX6_PAD_LCD_DATA02__ECSPI1_SS0                        = IOMUX_PAD(0x03E8, 0x0120, 1, 0x0614, 0, 0),
+	MX6_PAD_LCD_DATA02__EPIT2_OUT                         = IOMUX_PAD(0x03E8, 0x0120, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__PWM3_OUT                          = IOMUX_PAD(0x03E8, 0x0120, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__AUD4_RXC                          = IOMUX_PAD(0x03E8, 0x0120, 4, 0x056C, 0, 0),
+	MX6_PAD_LCD_DATA02__GPIO2_IO22                        = IOMUX_PAD(0x03E8, 0x0120, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__ARM_TRACE02                       = IOMUX_PAD(0x03E8, 0x0120, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__SRC_BOOT_CFG02                    = IOMUX_PAD(0x03E8, 0x0120, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA03__LCD_DATA03                        = IOMUX_PAD(0x03EC, 0x0124, 0, 0x06E4, 1, 0),
+	MX6_PAD_LCD_DATA03__ECSPI1_SCLK                       = IOMUX_PAD(0x03EC, 0x0124, 1, 0x05FC, 0, 0),
+	MX6_PAD_LCD_DATA03__UART5_DSR_B                       = IOMUX_PAD(0x03EC, 0x0124, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__PWM4_OUT                          = IOMUX_PAD(0x03EC, 0x0124, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__AUD4_RXD                          = IOMUX_PAD(0x03EC, 0x0124, 4, 0x0564, 0, 0),
+	MX6_PAD_LCD_DATA03__GPIO2_IO23                        = IOMUX_PAD(0x03EC, 0x0124, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__ARM_TRACE03                       = IOMUX_PAD(0x03EC, 0x0124, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__SRC_BOOT_CFG03                    = IOMUX_PAD(0x03EC, 0x0124, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA04__LCD_DATA04                        = IOMUX_PAD(0x03F0, 0x0128, 0, 0x06E8, 1, 0),
+	MX6_PAD_LCD_DATA04__ECSPI1_SS1                        = IOMUX_PAD(0x03F0, 0x0128, 1, 0x060C, 1, 0),
+	MX6_PAD_LCD_DATA04__CSI_VSYNC                         = IOMUX_PAD(0x03F0, 0x0128, 2, 0x05F8, 0, 0),
+	MX6_PAD_LCD_DATA04__WDOG2_RESET_B_DEB                 = IOMUX_PAD(0x03F0, 0x0128, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__AUD4_TXC                          = IOMUX_PAD(0x03F0, 0x0128, 4, 0x0574, 0, 0),
+	MX6_PAD_LCD_DATA04__GPIO2_IO24                        = IOMUX_PAD(0x03F0, 0x0128, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__ARM_TRACE04                       = IOMUX_PAD(0x03F0, 0x0128, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__SRC_BOOT_CFG04                    = IOMUX_PAD(0x03F0, 0x0128, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA05__LCD_DATA05                        = IOMUX_PAD(0x03F4, 0x012C, 0, 0x06EC, 1, 0),
+	MX6_PAD_LCD_DATA05__ECSPI1_SS2                        = IOMUX_PAD(0x03F4, 0x012C, 1, 0x0610, 1, 0),
+	MX6_PAD_LCD_DATA05__CSI_HSYNC                         = IOMUX_PAD(0x03F4, 0x012C, 2, 0x05F0, 0, 0),
+	MX6_PAD_LCD_DATA05__AUD4_TXFS                         = IOMUX_PAD(0x03F4, 0x012C, 4, 0x0578, 0, 0),
+	MX6_PAD_LCD_DATA05__GPIO2_IO25                        = IOMUX_PAD(0x03F4, 0x012C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__ARM_TRACE05                       = IOMUX_PAD(0x03F4, 0x012C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__SRC_BOOT_CFG05                    = IOMUX_PAD(0x03F4, 0x012C, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA06__LCD_DATA06                        = IOMUX_PAD(0x03F8, 0x0130, 0, 0x06F0, 1, 0),
+	MX6_PAD_LCD_DATA06__ECSPI1_SS3                        = IOMUX_PAD(0x03F8, 0x0130, 1, 0x0618, 0, 0),
+	MX6_PAD_LCD_DATA06__CSI_PIXCLK                        = IOMUX_PAD(0x03F8, 0x0130, 2, 0x05F4, 0, 0),
+	MX6_PAD_LCD_DATA06__AUD4_TXD                          = IOMUX_PAD(0x03F8, 0x0130, 4, 0x0568, 0, 0),
+	MX6_PAD_LCD_DATA06__GPIO2_IO26                        = IOMUX_PAD(0x03F8, 0x0130, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__ARM_TRACE06                       = IOMUX_PAD(0x03F8, 0x0130, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__SRC_BOOT_CFG06                    = IOMUX_PAD(0x03F8, 0x0130, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA07__LCD_DATA07                        = IOMUX_PAD(0x03FC, 0x0134, 0, 0x06F4, 0, 0),
+	MX6_PAD_LCD_DATA07__ECSPI1_RDY                        = IOMUX_PAD(0x03FC, 0x0134, 1, 0x0600, 0, 0),
+	MX6_PAD_LCD_DATA07__CSI_MCLK                          = IOMUX_PAD(0x03FC, 0x0134, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__AUDIO_CLK_OUT                     = IOMUX_PAD(0x03FC, 0x0134, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__GPIO2_IO27                        = IOMUX_PAD(0x03FC, 0x0134, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__ARM_TRACE07                       = IOMUX_PAD(0x03FC, 0x0134, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__SRC_BOOT_CFG07                    = IOMUX_PAD(0x03FC, 0x0134, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA08__LCD_DATA08                        = IOMUX_PAD(0x0400, 0x0138, 0, 0x06F8, 0, 0),
+	MX6_PAD_LCD_DATA08__KEY_COL0                          = IOMUX_PAD(0x0400, 0x0138, 1, 0x06A0, 1, 0),
+	MX6_PAD_LCD_DATA08__CSI_DATA09                        = IOMUX_PAD(0x0400, 0x0138, 2, 0x05EC, 0, 0),
+	MX6_PAD_LCD_DATA08__ECSPI2_SCLK                       = IOMUX_PAD(0x0400, 0x0138, 4, 0x061C, 0, 0),
+	MX6_PAD_LCD_DATA08__GPIO2_IO28                        = IOMUX_PAD(0x0400, 0x0138, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA08__ARM_TRACE08                       = IOMUX_PAD(0x0400, 0x0138, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA08__SRC_BOOT_CFG08                    = IOMUX_PAD(0x0400, 0x0138, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA09__LCD_DATA09                        = IOMUX_PAD(0x0404, 0x013C, 0, 0x06FC, 0, 0),
+	MX6_PAD_LCD_DATA09__KEY_ROW0                          = IOMUX_PAD(0x0404, 0x013C, 1, 0x06C0, 1, 0),
+	MX6_PAD_LCD_DATA09__CSI_DATA08                        = IOMUX_PAD(0x0404, 0x013C, 2, 0x05E8, 0, 0),
+	MX6_PAD_LCD_DATA09__ECSPI2_MOSI                       = IOMUX_PAD(0x0404, 0x013C, 4, 0x0624, 0, 0),
+	MX6_PAD_LCD_DATA09__GPIO2_IO29                        = IOMUX_PAD(0x0404, 0x013C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA09__ARM_TRACE09                       = IOMUX_PAD(0x0404, 0x013C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA09__SRC_BOOT_CFG09                    = IOMUX_PAD(0x0404, 0x013C, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA10__LCD_DATA10                        = IOMUX_PAD(0x0408, 0x0140, 0, 0x0700, 1, 0),
+	MX6_PAD_LCD_DATA10__KEY_COL1                          = IOMUX_PAD(0x0408, 0x0140, 1, 0x06A4, 1, 0),
+	MX6_PAD_LCD_DATA10__CSI_DATA07                        = IOMUX_PAD(0x0408, 0x0140, 2, 0x05E4, 0, 0),
+	MX6_PAD_LCD_DATA10__ECSPI2_MISO                       = IOMUX_PAD(0x0408, 0x0140, 4, 0x0620, 0, 0),
+	MX6_PAD_LCD_DATA10__GPIO2_IO30                        = IOMUX_PAD(0x0408, 0x0140, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__ARM_TRACE10                       = IOMUX_PAD(0x0408, 0x0140, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__SRC_BOOT_CFG10                    = IOMUX_PAD(0x0408, 0x0140, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA11__LCD_DATA11                        = IOMUX_PAD(0x040C, 0x0144, 0, 0x0704, 0, 0),
+	MX6_PAD_LCD_DATA11__KEY_ROW1                          = IOMUX_PAD(0x040C, 0x0144, 1, 0x06C4, 1, 0),
+	MX6_PAD_LCD_DATA11__CSI_DATA06                        = IOMUX_PAD(0x040C, 0x0144, 2, 0x05E0, 0, 0),
+	MX6_PAD_LCD_DATA11__ECSPI2_SS1                        = IOMUX_PAD(0x040C, 0x0144, 4, 0x062C, 0, 0),
+	MX6_PAD_LCD_DATA11__GPIO2_IO31                        = IOMUX_PAD(0x040C, 0x0144, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__ARM_TRACE11                       = IOMUX_PAD(0x040C, 0x0144, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__SRC_BOOT_CFG11                    = IOMUX_PAD(0x040C, 0x0144, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA12__LCD_DATA12                        = IOMUX_PAD(0x0410, 0x0148, 0, 0x0708, 0, 0),
+	MX6_PAD_LCD_DATA12__KEY_COL2                          = IOMUX_PAD(0x0410, 0x0148, 1, 0x06A8, 1, 0),
+	MX6_PAD_LCD_DATA12__CSI_DATA05                        = IOMUX_PAD(0x0410, 0x0148, 2, 0x05DC, 0, 0),
+	MX6_PAD_LCD_DATA12__UART5_DCE_RTS                     = IOMUX_PAD(0x0410, 0x0148, 4, 0x0760, 0, 0),
+	MX6_PAD_LCD_DATA12__UART5_DTE_CTS                     = IOMUX_PAD(0x0410, 0x0148, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA12__GPIO3_IO00                        = IOMUX_PAD(0x0410, 0x0148, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA12__ARM_TRACE12                       = IOMUX_PAD(0x0410, 0x0148, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA12__SRC_BOOT_CFG12                    = IOMUX_PAD(0x0410, 0x0148, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA13__LCD_DATA13                        = IOMUX_PAD(0x0414, 0x014C, 0, 0x070C, 0, 0),
+	MX6_PAD_LCD_DATA13__KEY_ROW2                          = IOMUX_PAD(0x0414, 0x014C, 1, 0x06C8, 1, 0),
+	MX6_PAD_LCD_DATA13__CSI_DATA04                        = IOMUX_PAD(0x0414, 0x014C, 2, 0x05D8, 0, 0),
+	MX6_PAD_LCD_DATA13__UART5_DCE_CTS                     = IOMUX_PAD(0x0414, 0x014C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA13__UART5_DTE_RTS                     = IOMUX_PAD(0x0414, 0x014C, 4, 0x0760, 1, 0),
+	MX6_PAD_LCD_DATA13__GPIO3_IO01                        = IOMUX_PAD(0x0414, 0x014C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA13__ARM_TRACE13                       = IOMUX_PAD(0x0414, 0x014C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA13__SRC_BOOT_CFG13                    = IOMUX_PAD(0x0414, 0x014C, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA14__LCD_DATA14                        = IOMUX_PAD(0x0418, 0x0150, 0, 0x0710, 0, 0),
+	MX6_PAD_LCD_DATA14__KEY_COL3                          = IOMUX_PAD(0x0418, 0x0150, 1, 0x06AC, 1, 0),
+	MX6_PAD_LCD_DATA14__CSI_DATA03                        = IOMUX_PAD(0x0418, 0x0150, 2, 0x05D4, 0, 0),
+	MX6_PAD_LCD_DATA14__UART5_DCE_RX                      = IOMUX_PAD(0x0418, 0x0150, 4, 0x0764, 0, 0),
+	MX6_PAD_LCD_DATA14__UART5_DTE_TX                      = IOMUX_PAD(0x0418, 0x0150, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA14__GPIO3_IO02                        = IOMUX_PAD(0x0418, 0x0150, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA14__ARM_TRACE14                       = IOMUX_PAD(0x0418, 0x0150, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA14__SRC_BOOT_CFG14                    = IOMUX_PAD(0x0418, 0x0150, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA15__LCD_DATA15                        = IOMUX_PAD(0x041C, 0x0154, 0, 0x0714, 0, 0),
+	MX6_PAD_LCD_DATA15__KEY_ROW3                          = IOMUX_PAD(0x041C, 0x0154, 1, 0x06CC, 0, 0),
+	MX6_PAD_LCD_DATA15__CSI_DATA02                        = IOMUX_PAD(0x041C, 0x0154, 2, 0x05D0, 0, 0),
+	MX6_PAD_LCD_DATA15__UART5_DCE_TX                      = IOMUX_PAD(0x041C, 0x0154, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__UART5_DTE_RX                      = IOMUX_PAD(0x041C, 0x0154, 4, 0x0764, 1, 0),
+	MX6_PAD_LCD_DATA15__GPIO3_IO03                        = IOMUX_PAD(0x041C, 0x0154, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__ARM_TRACE15                       = IOMUX_PAD(0x041C, 0x0154, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__SRC_BOOT_CFG15                    = IOMUX_PAD(0x041C, 0x0154, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA16__LCD_DATA16                        = IOMUX_PAD(0x0420, 0x0158, 0, 0x0718, 0, 0),
+	MX6_PAD_LCD_DATA16__KEY_COL4                          = IOMUX_PAD(0x0420, 0x0158, 1, 0x06B0, 0, 0),
+	MX6_PAD_LCD_DATA16__CSI_DATA01                        = IOMUX_PAD(0x0420, 0x0158, 2, 0x05CC, 0, 0),
+	MX6_PAD_LCD_DATA16__I2C2_SCL                          = IOMUX_PAD(0x0420, 0x0158, IOMUX_CONFIG_SION | 4, 0x0684, 1, 0),
+	MX6_PAD_LCD_DATA16__GPIO3_IO04                        = IOMUX_PAD(0x0420, 0x0158, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA16__SRC_BOOT_CFG24                    = IOMUX_PAD(0x0420, 0x0158, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA17__LCD_DATA17                        = IOMUX_PAD(0x0424, 0x015C, 0, 0x071C, 0, 0),
+	MX6_PAD_LCD_DATA17__KEY_ROW4                          = IOMUX_PAD(0x0424, 0x015C, 1, 0x06D0, 0, 0),
+	MX6_PAD_LCD_DATA17__CSI_DATA00                        = IOMUX_PAD(0x0424, 0x015C, 2, 0x05C8, 0, 0),
+	MX6_PAD_LCD_DATA17__I2C2_SDA                          = IOMUX_PAD(0x0424, 0x015C, IOMUX_CONFIG_SION | 4, 0x0688, 1, 0),
+	MX6_PAD_LCD_DATA17__GPIO3_IO05                        = IOMUX_PAD(0x0424, 0x015C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__SRC_BOOT_CFG25                    = IOMUX_PAD(0x0424, 0x015C, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA18__LCD_DATA18                        = IOMUX_PAD(0x0428, 0x0160, 0, 0x0720, 0, 0),
+	MX6_PAD_LCD_DATA18__KEY_COL5                          = IOMUX_PAD(0x0428, 0x0160, 1, 0x0694, 2, 0),
+	MX6_PAD_LCD_DATA18__CSI_DATA15                        = IOMUX_PAD(0x0428, 0x0160, 2, 0x05C4, 1, 0),
+	MX6_PAD_LCD_DATA18__GPT_CAPTURE1                      = IOMUX_PAD(0x0428, 0x0160, 4, 0x0670, 1, 0),
+	MX6_PAD_LCD_DATA18__GPIO3_IO06                        = IOMUX_PAD(0x0428, 0x0160, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__SRC_BOOT_CFG26                    = IOMUX_PAD(0x0428, 0x0160, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA19__LCD_DATA19                        = IOMUX_PAD(0x042C, 0x0164, 0, 0x0724, 0, 0),
+	MX6_PAD_LCD_DATA19__KEY_ROW5                          = IOMUX_PAD(0x042C, 0x0164, 1, 0x06B4, 1, 0),
+	MX6_PAD_LCD_DATA19__CSI_DATA14                        = IOMUX_PAD(0x042C, 0x0164, 2, 0x05C0, 2, 0),
+	MX6_PAD_LCD_DATA19__GPT_CAPTURE2                      = IOMUX_PAD(0x042C, 0x0164, 4, 0x0674, 1, 0),
+	MX6_PAD_LCD_DATA19__GPIO3_IO07                        = IOMUX_PAD(0x042C, 0x0164, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__SRC_BOOT_CFG27                    = IOMUX_PAD(0x042C, 0x0164, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA20__LCD_DATA20                        = IOMUX_PAD(0x0430, 0x0168, 0, 0x0728, 0, 0),
+	MX6_PAD_LCD_DATA20__KEY_COL6                          = IOMUX_PAD(0x0430, 0x0168, 1, 0x0698, 1, 0),
+	MX6_PAD_LCD_DATA20__CSI_DATA13                        = IOMUX_PAD(0x0430, 0x0168, 2, 0x05BC, 2, 0),
+	MX6_PAD_LCD_DATA20__GPT_COMPARE1                      = IOMUX_PAD(0x0430, 0x0168, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__GPIO3_IO08                        = IOMUX_PAD(0x0430, 0x0168, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__SRC_BOOT_CFG28                    = IOMUX_PAD(0x0430, 0x0168, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA21__LCD_DATA21                        = IOMUX_PAD(0x0434, 0x016C, 0, 0x072C, 0, 0),
+	MX6_PAD_LCD_DATA21__KEY_ROW6                          = IOMUX_PAD(0x0434, 0x016C, 1, 0x06B8, 1, 0),
+	MX6_PAD_LCD_DATA21__CSI_DATA12                        = IOMUX_PAD(0x0434, 0x016C, 2, 0x05B8, 2, 0),
+	MX6_PAD_LCD_DATA21__GPT_COMPARE2                      = IOMUX_PAD(0x0434, 0x016C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__GPIO3_IO09                        = IOMUX_PAD(0x0434, 0x016C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__SRC_BOOT_CFG29                    = IOMUX_PAD(0x0434, 0x016C, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA22__LCD_DATA22                        = IOMUX_PAD(0x0438, 0x0170, 0, 0x0730, 0, 0),
+	MX6_PAD_LCD_DATA22__KEY_COL7                          = IOMUX_PAD(0x0438, 0x0170, 1, 0x069C, 1, 0),
+	MX6_PAD_LCD_DATA22__CSI_DATA11                        = IOMUX_PAD(0x0438, 0x0170, 2, 0x05B4, 1, 0),
+	MX6_PAD_LCD_DATA22__GPT_COMPARE3                      = IOMUX_PAD(0x0438, 0x0170, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__GPIO3_IO10                        = IOMUX_PAD(0x0438, 0x0170, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__SRC_BOOT_CFG30                    = IOMUX_PAD(0x0438, 0x0170, 7, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA23__LCD_DATA23                        = IOMUX_PAD(0x043C, 0x0174, 0, 0x0734, 0, 0),
+	MX6_PAD_LCD_DATA23__KEY_ROW7                          = IOMUX_PAD(0x043C, 0x0174, 1, 0x06BC, 1, 0),
+	MX6_PAD_LCD_DATA23__CSI_DATA10                        = IOMUX_PAD(0x043C, 0x0174, 2, 0x05B0, 1, 0),
+	MX6_PAD_LCD_DATA23__GPT_CLKIN                         = IOMUX_PAD(0x043C, 0x0174, 4, 0x0678, 1, 0),
+	MX6_PAD_LCD_DATA23__GPIO3_IO11                        = IOMUX_PAD(0x043C, 0x0174, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA23__SRC_BOOT_CFG31                    = IOMUX_PAD(0x043C, 0x0174, 7, 0x0000, 0, 0),
+
+	MX6_PAD_AUD_RXFS__AUD3_RXFS                           = IOMUX_PAD(0x0440, 0x0178, 0, 0x0000, 0, 0),
+	MX6_PAD_AUD_RXFS__I2C1_SCL                            = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 1, 0x067C, 1, 0),
+	MX6_PAD_AUD_RXFS__UART3_DCE_RX                        = IOMUX_PAD(0x0440, 0x0178, 2, 0x0754, 0, 0),
+	MX6_PAD_AUD_RXFS__UART3_DTE_TX                        = IOMUX_PAD(0x0440, 0x0178, 2, 0x0000, 0, 0),
+	MX6_PAD_AUD_RXFS__I2C3_SCL                            = IOMUX_PAD(0x0440, 0x0178, IOMUX_CONFIG_SION | 4, 0x068C, 1, 0),
+	MX6_PAD_AUD_RXFS__GPIO1_IO00                          = IOMUX_PAD(0x0440, 0x0178, 5, 0x0000, 0, 0),
+	MX6_PAD_AUD_RXFS__ECSPI3_SS0                          = IOMUX_PAD(0x0440, 0x0178, 6, 0x0648, 0, 0),
+	MX6_PAD_AUD_RXFS__MBIST_BEND                          = IOMUX_PAD(0x0440, 0x0178, 7, 0x0000, 0, 0),
+
+	MX6_PAD_AUD_RXC__AUD3_RXC                             = IOMUX_PAD(0x0444, 0x017C, 0, 0x0000, 0, 0),
+	MX6_PAD_AUD_RXC__I2C1_SDA                             = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 1, 0x0680, 1, 0),
+	MX6_PAD_AUD_RXC__UART3_DCE_TX                         = IOMUX_PAD(0x0444, 0x017C, 2, 0x0000, 0, 0),
+	MX6_PAD_AUD_RXC__UART3_DTE_RX                         = IOMUX_PAD(0x0444, 0x017C, 2, 0x0754, 1, 0),
+	MX6_PAD_AUD_RXC__I2C3_SDA                             = IOMUX_PAD(0x0444, 0x017C, IOMUX_CONFIG_SION | 4, 0x0690, 1, 0),
+	MX6_PAD_AUD_RXC__GPIO1_IO01                           = IOMUX_PAD(0x0444, 0x017C, 5, 0x0000, 0, 0),
+	MX6_PAD_AUD_RXC__ECSPI3_SS1                           = IOMUX_PAD(0x0444, 0x017C, 6, 0x064C, 0, 0),
+
+	MX6_PAD_AUD_RXD__AUD3_RXD                             = IOMUX_PAD(0x0448, 0x0180, 0, 0x0000, 0, 0),
+	MX6_PAD_AUD_RXD__ECSPI3_MOSI                          = IOMUX_PAD(0x0448, 0x0180, 1, 0x063C, 0, 0),
+	MX6_PAD_AUD_RXD__UART4_DCE_RX                         = IOMUX_PAD(0x0448, 0x0180, 2, 0x075C, 0, 0),
+	MX6_PAD_AUD_RXD__UART4_DTE_TX                         = IOMUX_PAD(0x0448, 0x0180, 2, 0x0000, 0, 0),
+	MX6_PAD_AUD_RXD__SD1_LCTL                             = IOMUX_PAD(0x0448, 0x0180, 4, 0x0000, 0, 0),
+	MX6_PAD_AUD_RXD__GPIO1_IO02                           = IOMUX_PAD(0x0448, 0x0180, 5, 0x0000, 0, 0),
+
+	MX6_PAD_AUD_TXC__AUD3_TXC                             = IOMUX_PAD(0x044C, 0x0184, 0, 0x0000, 0, 0),
+	MX6_PAD_AUD_TXC__ECSPI3_MISO                          = IOMUX_PAD(0x044C, 0x0184, 1, 0x0638, 0, 0),
+	MX6_PAD_AUD_TXC__UART4_DCE_TX                         = IOMUX_PAD(0x044C, 0x0184, 2, 0x0000, 0, 0),
+	MX6_PAD_AUD_TXC__UART4_DTE_RX                         = IOMUX_PAD(0x044C, 0x0184, 2, 0x075C, 1, 0),
+	MX6_PAD_AUD_TXC__SD2_LCTL                             = IOMUX_PAD(0x044C, 0x0184, 4, 0x0000, 0, 0),
+	MX6_PAD_AUD_TXC__GPIO1_IO03                           = IOMUX_PAD(0x044C, 0x0184, 5, 0x0000, 0, 0),
+
+	MX6_PAD_AUD_TXFS__AUD3_TXFS                           = IOMUX_PAD(0x0450, 0x0188, 0, 0x0000, 0, 0),
+	MX6_PAD_AUD_TXFS__PWM3_OUT                            = IOMUX_PAD(0x0450, 0x0188, 1, 0x0000, 0, 0),
+	MX6_PAD_AUD_TXFS__UART4_DCE_RTS                       = IOMUX_PAD(0x0450, 0x0188, 2, 0x0758, 0, 0),
+	MX6_PAD_AUD_TXFS__UART4_DTE_CTS                       = IOMUX_PAD(0x0450, 0x0188, 2, 0x0000, 0, 0),
+	MX6_PAD_AUD_TXFS__SD3_LCTL                            = IOMUX_PAD(0x0450, 0x0188, 4, 0x0000, 0, 0),
+	MX6_PAD_AUD_TXFS__GPIO1_IO04                          = IOMUX_PAD(0x0450, 0x0188, 5, 0x0000, 0, 0),
+
+	MX6_PAD_AUD_TXD__AUD3_TXD                             = IOMUX_PAD(0x0454, 0x018C, 0, 0x0000, 0, 0),
+	MX6_PAD_AUD_TXD__ECSPI3_SCLK                          = IOMUX_PAD(0x0454, 0x018C, 1, 0x0630, 0, 0),
+	MX6_PAD_AUD_TXD__UART4_DCE_CTS                        = IOMUX_PAD(0x0454, 0x018C, 2, 0x0000, 0, 0),
+	MX6_PAD_AUD_TXD__UART4_DTE_RTS                        = IOMUX_PAD(0x0454, 0x018C, 2, 0x0758, 1, 0),
+	MX6_PAD_AUD_TXD__GPIO1_IO05                           = IOMUX_PAD(0x0454, 0x018C, 5, 0x0000, 0, 0),
+
+	MX6_PAD_AUD_MCLK__AUDIO_CLK_OUT                       = IOMUX_PAD(0x0458, 0x0190, 0, 0x0000, 0, 0),
+	MX6_PAD_AUD_MCLK__PWM4_OUT                            = IOMUX_PAD(0x0458, 0x0190, 1, 0x0000, 0, 0),
+	MX6_PAD_AUD_MCLK__ECSPI3_RDY                          = IOMUX_PAD(0x0458, 0x0190, 2, 0x0634, 0, 0),
+	MX6_PAD_AUD_MCLK__WDOG2_RESET_B_DEB                   = IOMUX_PAD(0x0458, 0x0190, 4, 0x0000, 0, 0),
+	MX6_PAD_AUD_MCLK__GPIO1_IO06                          = IOMUX_PAD(0x0458, 0x0190, 5, 0x0000, 0, 0),
+	MX6_PAD_AUD_MCLK__SPDIF_EXT_CLK                       = IOMUX_PAD(0x0458, 0x0190, 6, 0x073C, 1, 0),
+
+	MX6_PAD_UART1_RXD__UART1_DCE_RX                       = IOMUX_PAD(0x045C, 0x0194, 0, 0x0744, 0, 0),
+
+	MX6_PAD_UART1_RXD__UART1_DTE_TX                       = IOMUX_PAD(0x045C, 0x0194, 0, 0x0000, 0, 0),
+	MX6_PAD_UART1_RXD__PWM1_OUT                           = IOMUX_PAD(0x045C, 0x0194, 1, 0x0000, 0, 0),
+	MX6_PAD_UART1_RXD__UART4_DCE_RX                       = IOMUX_PAD(0x045C, 0x0194, 2, 0x075C, 4, 0),
+	MX6_PAD_UART1_RXD__UART4_DTE_TX                       = IOMUX_PAD(0x045C, 0x0194, 2, 0x0000, 0, 0),
+	MX6_PAD_UART1_RXD__UART5_DCE_RX                       = IOMUX_PAD(0x045C, 0x0194, 4, 0x0764, 6, 0),
+	MX6_PAD_UART1_RXD__UART5_DTE_TX                       = IOMUX_PAD(0x045C, 0x0194, 4, 0x0000, 0, 0),
+	MX6_PAD_UART1_RXD__GPIO3_IO16                         = IOMUX_PAD(0x045C, 0x0194, 5, 0x0000, 0, 0),
+
+	MX6_PAD_UART1_TXD__UART1_DCE_TX                       = IOMUX_PAD(0x0460, 0x0198, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART1_TXD__UART1_DTE_RX                       = IOMUX_PAD(0x0460, 0x0198, 0, 0x0744, 1, 0),
+	MX6_PAD_UART1_TXD__PWM2_OUT                           = IOMUX_PAD(0x0460, 0x0198, 1, 0x0000, 0, 0),
+	MX6_PAD_UART1_TXD__UART4_DCE_TX                       = IOMUX_PAD(0x0460, 0x0198, 2, 0x0000, 0, 0),
+	MX6_PAD_UART1_TXD__UART4_DTE_RX                       = IOMUX_PAD(0x0460, 0x0198, 2, 0x075C, 5, 0),
+	MX6_PAD_UART1_TXD__UART5_DCE_TX                       = IOMUX_PAD(0x0460, 0x0198, 4, 0x0000, 0, 0),
+	MX6_PAD_UART1_TXD__UART5_DTE_RX                       = IOMUX_PAD(0x0460, 0x0198, 4, 0x0764, 7, 0),
+	MX6_PAD_UART1_TXD__GPIO3_IO17                         = IOMUX_PAD(0x0460, 0x0198, 5, 0x0000, 0, 0),
+	MX6_PAD_UART1_TXD__UART5_DCD_B                        = IOMUX_PAD(0x0460, 0x0198, 7, 0x0000, 0, 0),
+
+	MX6_PAD_I2C1_SCL__I2C1_SCL                            = IOMUX_PAD(0x0464, 0x019C, IOMUX_CONFIG_SION | 0, 0x067C, 0, 0),
+	MX6_PAD_I2C1_SCL__UART1_DCE_RTS                       = IOMUX_PAD(0x0464, 0x019C, 1, 0x0740, 0, 0),
+	MX6_PAD_I2C1_SCL__UART1_DTE_CTS                       = IOMUX_PAD(0x0464, 0x019C, 1, 0x0000, 0, 0),
+	MX6_PAD_I2C1_SCL__ECSPI3_SS2                          = IOMUX_PAD(0x0464, 0x019C, 2, 0x0640, 0, 0),
+	MX6_PAD_I2C1_SCL__SD3_RESET                           = IOMUX_PAD(0x0464, 0x019C, 4, 0x0000, 0, 0),
+	MX6_PAD_I2C1_SCL__GPIO3_IO12                          = IOMUX_PAD(0x0464, 0x019C, 5, 0x0000, 0, 0),
+	MX6_PAD_I2C1_SCL__ECSPI1_SS1                          = IOMUX_PAD(0x0464, 0x019C, 6, 0x060C, 0, 0),
+
+	MX6_PAD_I2C1_SDA__I2C1_SDA                            = IOMUX_PAD(0x0468, 0x01A0, IOMUX_CONFIG_SION | 0, 0x0680, 0, 0),
+	MX6_PAD_I2C1_SDA__UART1_DCE_CTS                       = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0000, 0, 0),
+	MX6_PAD_I2C1_SDA__UART1_DTE_RTS                       = IOMUX_PAD(0x0468, 0x01A0, 1, 0x0740, 1, 0),
+	MX6_PAD_I2C1_SDA__ECSPI3_SS3                          = IOMUX_PAD(0x0468, 0x01A0, 2, 0x0644, 0, 0),
+	MX6_PAD_I2C1_SDA__SD3_VSELECT                         = IOMUX_PAD(0x0468, 0x01A0, 4, 0x0000, 0, 0),
+	MX6_PAD_I2C1_SDA__GPIO3_IO13                          = IOMUX_PAD(0x0468, 0x01A0, 5, 0x0000, 0, 0),
+	MX6_PAD_I2C1_SDA__ECSPI1_SS2                          = IOMUX_PAD(0x0468, 0x01A0, 6, 0x0610, 0, 0),
+
+	MX6_PAD_I2C2_SCL__I2C2_SCL                            = IOMUX_PAD(0x046C, 0x01A4, IOMUX_CONFIG_SION | 0, 0x0684, 3, 0),
+	MX6_PAD_I2C2_SCL__AUD4_RXFS                           = IOMUX_PAD(0x046C, 0x01A4, 1, 0x0570, 2, 0),
+	MX6_PAD_I2C2_SCL__SPDIF_IN                            = IOMUX_PAD(0x046C, 0x01A4, 2, 0x0738, 2, 0),
+	MX6_PAD_I2C2_SCL__SD3_WP                              = IOMUX_PAD(0x046C, 0x01A4, 4, 0x0794, 3, 0),
+	MX6_PAD_I2C2_SCL__GPIO3_IO14                          = IOMUX_PAD(0x046C, 0x01A4, 5, 0x0000, 0, 0),
+	MX6_PAD_I2C2_SCL__ECSPI1_RDY                          = IOMUX_PAD(0x046C, 0x01A4, 6, 0x0600, 1, 0),
+
+	MX6_PAD_I2C2_SDA__I2C2_SDA                            = IOMUX_PAD(0x0470, 0x01A8, IOMUX_CONFIG_SION | 0, 0x0688, 3, 0),
+	MX6_PAD_I2C2_SDA__AUD4_RXC                            = IOMUX_PAD(0x0470, 0x01A8, 1, 0x056C, 2, 0),
+	MX6_PAD_I2C2_SDA__SPDIF_OUT                           = IOMUX_PAD(0x0470, 0x01A8, 2, 0x0000, 0, 0),
+	MX6_PAD_I2C2_SDA__SD3_CD_B                            = IOMUX_PAD(0x0470, 0x01A8, 4, 0x0780, 3, 0),
+	MX6_PAD_I2C2_SDA__GPIO3_IO15                          = IOMUX_PAD(0x0470, 0x01A8, 5, 0x0000, 0, 0),
+
+	MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK                      = IOMUX_PAD(0x0474, 0x01AC, 0, 0x05FC, 1, 0),
+	MX6_PAD_ECSPI1_SCLK__AUD4_TXD                         = IOMUX_PAD(0x0474, 0x01AC, 1, 0x0568, 1, 0),
+	MX6_PAD_ECSPI1_SCLK__UART5_DCE_RX                     = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0764, 2, 0),
+	MX6_PAD_ECSPI1_SCLK__UART5_DTE_TX                     = IOMUX_PAD(0x0474, 0x01AC, 2, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_SCLK__EPDC_VCOM0                       = IOMUX_PAD(0x0474, 0x01AC, 3, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_SCLK__SD2_RESET                        = IOMUX_PAD(0x0474, 0x01AC, 4, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_SCLK__GPIO4_IO08                       = IOMUX_PAD(0x0474, 0x01AC, 5, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_SCLK__USB_OTG2_OC                      = IOMUX_PAD(0x0474, 0x01AC, 6, 0x0768, 1, 0),
+
+	MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI                      = IOMUX_PAD(0x0478, 0x01B0, 0, 0x0608, 1, 0),
+	MX6_PAD_ECSPI1_MOSI__AUD4_TXC                         = IOMUX_PAD(0x0478, 0x01B0, 1, 0x0574, 1, 0),
+	MX6_PAD_ECSPI1_MOSI__UART5_DCE_TX                     = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_MOSI__UART5_DTE_RX                     = IOMUX_PAD(0x0478, 0x01B0, 2, 0x0764, 3, 0),
+	MX6_PAD_ECSPI1_MOSI__EPDC_VCOM1                       = IOMUX_PAD(0x0478, 0x01B0, 3, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_MOSI__SD2_VSELECT                      = IOMUX_PAD(0x0478, 0x01B0, 4, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_MOSI__GPIO4_IO09                       = IOMUX_PAD(0x0478, 0x01B0, 5, 0x0000, 0, 0),
+
+	MX6_PAD_ECSPI1_MISO__ECSPI1_MISO                      = IOMUX_PAD(0x047C, 0x01B4, 0, 0x0604, 1, 0),
+	MX6_PAD_ECSPI1_MISO__AUD4_TXFS                        = IOMUX_PAD(0x047C, 0x01B4, 1, 0x0578, 1, 0),
+	MX6_PAD_ECSPI1_MISO__UART5_DCE_RTS                    = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0760, 2, 0),
+	MX6_PAD_ECSPI1_MISO__UART5_DTE_CTS                    = IOMUX_PAD(0x047C, 0x01B4, 2, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_MISO__EPDC_BDR0                        = IOMUX_PAD(0x047C, 0x01B4, 3, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_MISO__SD2_WP                           = IOMUX_PAD(0x047C, 0x01B4, 4, 0x077C, 0, 0),
+	MX6_PAD_ECSPI1_MISO__GPIO4_IO10                       = IOMUX_PAD(0x047C, 0x01B4, 5, 0x0000, 0, 0),
+
+	MX6_PAD_ECSPI1_SS0__ECSPI1_SS0                        = IOMUX_PAD(0x0480, 0x01B8, 0, 0x0614, 1, 0),
+	MX6_PAD_ECSPI1_SS0__AUD4_RXD                          = IOMUX_PAD(0x0480, 0x01B8, 1, 0x0564, 1, 0),
+	MX6_PAD_ECSPI1_SS0__UART5_DCE_CTS                     = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_SS0__UART5_DTE_RTS                     = IOMUX_PAD(0x0480, 0x01B8, 2, 0x0760, 3, 0),
+	MX6_PAD_ECSPI1_SS0__EPDC_BDR1                         = IOMUX_PAD(0x0480, 0x01B8, 3, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_SS0__SD2_CD_B                          = IOMUX_PAD(0x0480, 0x01B8, 4, 0x0778, 0, 0),
+	MX6_PAD_ECSPI1_SS0__GPIO4_IO11                        = IOMUX_PAD(0x0480, 0x01B8, 5, 0x0000, 0, 0),
+	MX6_PAD_ECSPI1_SS0__USB_OTG2_PWR                      = IOMUX_PAD(0x0480, 0x01B8, 6, 0x0000, 0, 0),
+
+	MX6_PAD_ECSPI2_SCLK__ECSPI2_SCLK                      = IOMUX_PAD(0x0484, 0x01BC, 0, 0x061C, 1, 0),
+	MX6_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK                    = IOMUX_PAD(0x0484, 0x01BC, 1, 0x073C, 2, 0),
+	MX6_PAD_ECSPI2_SCLK__UART3_DCE_RX                     = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0754, 2, 0),
+	MX6_PAD_ECSPI2_SCLK__UART3_DTE_TX                     = IOMUX_PAD(0x0484, 0x01BC, 2, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_SCLK__CSI_PIXCLK                       = IOMUX_PAD(0x0484, 0x01BC, 3, 0x05F4, 1, 0),
+	MX6_PAD_ECSPI2_SCLK__SD1_RESET                        = IOMUX_PAD(0x0484, 0x01BC, 4, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_SCLK__GPIO4_IO12                       = IOMUX_PAD(0x0484, 0x01BC, 5, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC                      = IOMUX_PAD(0x0484, 0x01BC, 6, 0x0768, 2, 0),
+
+	MX6_PAD_ECSPI2_MOSI__ECSPI2_MOSI                      = IOMUX_PAD(0x0488, 0x01C0, 0, 0x0624, 1, 0),
+	MX6_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1                  = IOMUX_PAD(0x0488, 0x01C0, 1, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_MOSI__UART3_DCE_TX                     = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_MOSI__UART3_DTE_RX                     = IOMUX_PAD(0x0488, 0x01C0, 2, 0x0754, 3, 0),
+	MX6_PAD_ECSPI2_MOSI__CSI_HSYNC                        = IOMUX_PAD(0x0488, 0x01C0, 3, 0x05F0, 1, 0),
+	MX6_PAD_ECSPI2_MOSI__SD1_VSELECT                      = IOMUX_PAD(0x0488, 0x01C0, 4, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_MOSI__GPIO4_IO13                       = IOMUX_PAD(0x0488, 0x01C0, 5, 0x0000, 0, 0),
+
+	MX6_PAD_ECSPI2_MISO__ECSPI2_MISO                      = IOMUX_PAD(0x048C, 0x01C4, 0, 0x0620, 1, 0),
+	MX6_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0                  = IOMUX_PAD(0x048C, 0x01C4, 1, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_MISO__UART3_DCE_RTS                    = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0750, 0, 0),
+	MX6_PAD_ECSPI2_MISO__UART3_DTE_CTS                    = IOMUX_PAD(0x048C, 0x01C4, 2, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_MISO__CSI_MCLK                         = IOMUX_PAD(0x048C, 0x01C4, 3, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_MISO__SD1_WP                           = IOMUX_PAD(0x048C, 0x01C4, 4, 0x0774, 2, 0),
+	MX6_PAD_ECSPI2_MISO__GPIO4_IO14                       = IOMUX_PAD(0x048C, 0x01C4, 5, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_MISO__USB_OTG1_OC                      = IOMUX_PAD(0x048C, 0x01C4, 6, 0x076C, 1, 0),
+
+	MX6_PAD_ECSPI2_SS0__ECSPI2_SS0                        = IOMUX_PAD(0x0490, 0x01C8, 0, 0x0628, 0, 0),
+	MX6_PAD_ECSPI2_SS0__ECSPI1_SS3                        = IOMUX_PAD(0x0490, 0x01C8, 1, 0x0618, 1, 0),
+	MX6_PAD_ECSPI2_SS0__UART3_DCE_CTS                     = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_SS0__UART3_DTE_RTS                     = IOMUX_PAD(0x0490, 0x01C8, 2, 0x0750, 1, 0),
+	MX6_PAD_ECSPI2_SS0__CSI_VSYNC                         = IOMUX_PAD(0x0490, 0x01C8, 3, 0x05F8, 1, 0),
+	MX6_PAD_ECSPI2_SS0__SD1_CD_B                          = IOMUX_PAD(0x0490, 0x01C8, 4, 0x0770, 2, 0),
+	MX6_PAD_ECSPI2_SS0__GPIO4_IO15                        = IOMUX_PAD(0x0490, 0x01C8, 5, 0x0000, 0, 0),
+	MX6_PAD_ECSPI2_SS0__USB_OTG1_PWR                      = IOMUX_PAD(0x0490, 0x01C8, 6, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_CLK__SD1_CLK                              = IOMUX_PAD(0x0494, 0x01CC, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__KEY_COL0                             = IOMUX_PAD(0x0494, 0x01CC, 2, 0x06A0, 2, 0),
+	MX6_PAD_SD1_CLK__EPDC_SDCE4                           = IOMUX_PAD(0x0494, 0x01CC, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__GPIO5_IO15                           = IOMUX_PAD(0x0494, 0x01CC, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_CMD__SD1_CMD                              = IOMUX_PAD(0x0498, 0x01D0, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__KEY_ROW0                             = IOMUX_PAD(0x0498, 0x01D0, 2, 0x06C0, 2, 0),
+	MX6_PAD_SD1_CMD__EPDC_SDCE5                           = IOMUX_PAD(0x0498, 0x01D0, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__GPIO5_IO14                           = IOMUX_PAD(0x0498, 0x01D0, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_DATA0__SD1_DATA0                          = IOMUX_PAD(0x049C, 0x01D4, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__KEY_COL1                           = IOMUX_PAD(0x049C, 0x01D4, 2, 0x06A4, 2, 0),
+	MX6_PAD_SD1_DATA0__EPDC_SDCE6                         = IOMUX_PAD(0x049C, 0x01D4, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__GPIO5_IO11                         = IOMUX_PAD(0x049C, 0x01D4, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_DATA1__SD1_DATA1                          = IOMUX_PAD(0x04A0, 0x01D8, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA1__KEY_ROW1                           = IOMUX_PAD(0x04A0, 0x01D8, 2, 0x06C4, 2, 0),
+	MX6_PAD_SD1_DATA1__EPDC_SDCE7                         = IOMUX_PAD(0x04A0, 0x01D8, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA1__GPIO5_IO08                         = IOMUX_PAD(0x04A0, 0x01D8, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_DATA2__SD1_DATA2                          = IOMUX_PAD(0x04A4, 0x01DC, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__KEY_COL2                           = IOMUX_PAD(0x04A4, 0x01DC, 2, 0x06A8, 2, 0),
+	MX6_PAD_SD1_DATA2__EPDC_SDCE8                         = IOMUX_PAD(0x04A4, 0x01DC, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__GPIO5_IO13                         = IOMUX_PAD(0x04A4, 0x01DC, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_DATA3__SD1_DATA3                          = IOMUX_PAD(0x04A8, 0x01E0, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__KEY_ROW2                           = IOMUX_PAD(0x04A8, 0x01E0, 2, 0x06C8, 2, 0),
+	MX6_PAD_SD1_DATA3__EPDC_SDCE9                         = IOMUX_PAD(0x04A8, 0x01E0, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__GPIO5_IO06                         = IOMUX_PAD(0x04A8, 0x01E0, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_DATA4__SD1_DATA4                          = IOMUX_PAD(0x04AC, 0x01E4, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA4__KEY_COL3                           = IOMUX_PAD(0x04AC, 0x01E4, 2, 0x06AC, 2, 0),
+	MX6_PAD_SD1_DATA4__EPDC_SDCLK_N                       = IOMUX_PAD(0x04AC, 0x01E4, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA4__UART4_DCE_RX                       = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x075C, 6, 0),
+	MX6_PAD_SD1_DATA4__UART4_DTE_TX                       = IOMUX_PAD(0x04AC, 0x01E4, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA4__GPIO5_IO12                         = IOMUX_PAD(0x04AC, 0x01E4, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_DATA5__SD1_DATA5                          = IOMUX_PAD(0x04B0, 0x01E8, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA5__KEY_ROW3                           = IOMUX_PAD(0x04B0, 0x01E8, 2, 0x06CC, 2, 0),
+	MX6_PAD_SD1_DATA5__EPDC_SDOED                         = IOMUX_PAD(0x04B0, 0x01E8, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA5__UART4_DCE_TX                       = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA5__UART4_DTE_RX                       = IOMUX_PAD(0x04B0, 0x01E8, 4, 0x075C, 7, 0),
+	MX6_PAD_SD1_DATA5__GPIO5_IO09                         = IOMUX_PAD(0x04B0, 0x01E8, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_DATA6__SD1_DATA6                          = IOMUX_PAD(0x04B4, 0x01EC, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA6__KEY_COL4                           = IOMUX_PAD(0x04B4, 0x01EC, 2, 0x06B0, 2, 0),
+	MX6_PAD_SD1_DATA6__EPDC_SDOEZ                         = IOMUX_PAD(0x04B4, 0x01EC, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA6__UART4_DCE_RTS                      = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0758, 4, 0),
+	MX6_PAD_SD1_DATA6__UART4_DTE_CTS                      = IOMUX_PAD(0x04B4, 0x01EC, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA6__GPIO5_IO07                         = IOMUX_PAD(0x04B4, 0x01EC, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_DATA7__SD1_DATA7                          = IOMUX_PAD(0x04B8, 0x01F0, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA7__KEY_ROW4                           = IOMUX_PAD(0x04B8, 0x01F0, 2, 0x06D0, 2, 0),
+	MX6_PAD_SD1_DATA7__CCM_PMIC_READY                     = IOMUX_PAD(0x04B8, 0x01F0, 3, 0x05AC, 3, 0),
+	MX6_PAD_SD1_DATA7__UART4_DCE_CTS                      = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA7__UART4_DTE_RTS                      = IOMUX_PAD(0x04B8, 0x01F0, 4, 0x0758, 5, 0),
+	MX6_PAD_SD1_DATA7__GPIO5_IO10                         = IOMUX_PAD(0x04B8, 0x01F0, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD2_RESET__SD2_RESET                          = IOMUX_PAD(0x04BC, 0x01F4, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_RESET__WDOG2_B                            = IOMUX_PAD(0x04BC, 0x01F4, 2, 0x0000, 0, 0),
+	MX6_PAD_SD2_RESET__SPDIF_OUT                          = IOMUX_PAD(0x04BC, 0x01F4, 3, 0x0000, 0, 0),
+	MX6_PAD_SD2_RESET__CSI_MCLK                           = IOMUX_PAD(0x04BC, 0x01F4, 4, 0x0000, 0, 0),
+	MX6_PAD_SD2_RESET__GPIO4_IO27                         = IOMUX_PAD(0x04BC, 0x01F4, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD2_CLK__SD2_CLK                              = IOMUX_PAD(0x04C0, 0x01F8, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_CLK__AUD4_RXFS                            = IOMUX_PAD(0x04C0, 0x01F8, 1, 0x0570, 1, 0),
+	MX6_PAD_SD2_CLK__ECSPI3_SCLK                          = IOMUX_PAD(0x04C0, 0x01F8, 2, 0x0630, 1, 0),
+	MX6_PAD_SD2_CLK__CSI_DATA00                           = IOMUX_PAD(0x04C0, 0x01F8, 3, 0x05C8, 1, 0),
+	MX6_PAD_SD2_CLK__GPIO5_IO05                           = IOMUX_PAD(0x04C0, 0x01F8, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD2_CMD__SD2_CMD                              = IOMUX_PAD(0x04C4, 0x01FC, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_CMD__AUD4_RXC                             = IOMUX_PAD(0x04C4, 0x01FC, 1, 0x056C, 1, 0),
+	MX6_PAD_SD2_CMD__ECSPI3_SS0                           = IOMUX_PAD(0x04C4, 0x01FC, 2, 0x0648, 1, 0),
+	MX6_PAD_SD2_CMD__CSI_DATA01                           = IOMUX_PAD(0x04C4, 0x01FC, 3, 0x05CC, 1, 0),
+	MX6_PAD_SD2_CMD__EPIT1_OUT                            = IOMUX_PAD(0x04C4, 0x01FC, 4, 0x0000, 0, 0),
+	MX6_PAD_SD2_CMD__GPIO5_IO04                           = IOMUX_PAD(0x04C4, 0x01FC, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD2_DATA0__SD2_DATA0                          = IOMUX_PAD(0x04C8, 0x0200, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA0__AUD4_RXD                           = IOMUX_PAD(0x04C8, 0x0200, 1, 0x0564, 2, 0),
+	MX6_PAD_SD2_DATA0__ECSPI3_MOSI                        = IOMUX_PAD(0x04C8, 0x0200, 2, 0x063C, 1, 0),
+	MX6_PAD_SD2_DATA0__CSI_DATA02                         = IOMUX_PAD(0x04C8, 0x0200, 3, 0x05D0, 1, 0),
+	MX6_PAD_SD2_DATA0__UART5_DCE_RTS                      = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0760, 4, 0),
+	MX6_PAD_SD2_DATA0__UART5_DTE_CTS                      = IOMUX_PAD(0x04C8, 0x0200, 4, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA0__GPIO5_IO01                         = IOMUX_PAD(0x04C8, 0x0200, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD2_DATA1__SD2_DATA1                          = IOMUX_PAD(0x04CC, 0x0204, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA1__AUD4_TXC                           = IOMUX_PAD(0x04CC, 0x0204, 1, 0x0574, 2, 0),
+	MX6_PAD_SD2_DATA1__ECSPI3_MISO                        = IOMUX_PAD(0x04CC, 0x0204, 2, 0x0638, 1, 0),
+	MX6_PAD_SD2_DATA1__CSI_DATA03                         = IOMUX_PAD(0x04CC, 0x0204, 3, 0x05D4, 1, 0),
+	MX6_PAD_SD2_DATA1__UART5_DCE_CTS                      = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA1__UART5_DTE_RTS                      = IOMUX_PAD(0x04CC, 0x0204, 4, 0x0760, 5, 0),
+	MX6_PAD_SD2_DATA1__GPIO4_IO30                         = IOMUX_PAD(0x04CC, 0x0204, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD2_DATA2__SD2_DATA2                          = IOMUX_PAD(0x04D0, 0x0208, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA2__AUD4_TXFS                          = IOMUX_PAD(0x04D0, 0x0208, 1, 0x0578, 2, 0),
+	MX6_PAD_SD2_DATA2__CSI_DATA04                         = IOMUX_PAD(0x04D0, 0x0208, 3, 0x05D8, 1, 0),
+	MX6_PAD_SD2_DATA2__UART5_DCE_RX                       = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0764, 4, 0),
+	MX6_PAD_SD2_DATA2__UART5_DTE_TX                       = IOMUX_PAD(0x04D0, 0x0208, 4, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA2__GPIO5_IO03                         = IOMUX_PAD(0x04D0, 0x0208, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD2_DATA3__SD2_DATA3                          = IOMUX_PAD(0x04D4, 0x020C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA3__AUD4_TXD                           = IOMUX_PAD(0x04D4, 0x020C, 1, 0x0568, 2, 0),
+	MX6_PAD_SD2_DATA3__CSI_DATA05                         = IOMUX_PAD(0x04D4, 0x020C, 3, 0x05DC, 1, 0),
+	MX6_PAD_SD2_DATA3__UART5_DCE_TX                       = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA3__UART5_DTE_RX                       = IOMUX_PAD(0x04D4, 0x020C, 4, 0x0764, 5, 0),
+	MX6_PAD_SD2_DATA3__GPIO4_IO28                         = IOMUX_PAD(0x04D4, 0x020C, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD2_DATA4__SD2_DATA4                          = IOMUX_PAD(0x04D8, 0x0210, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA4__SD3_DATA4                          = IOMUX_PAD(0x04D8, 0x0210, 1, 0x0784, 1, 0),
+	MX6_PAD_SD2_DATA4__UART2_DCE_RX                       = IOMUX_PAD(0x04D8, 0x0210, 2, 0x074C, 2, 0),
+	MX6_PAD_SD2_DATA4__UART2_DTE_TX                       = IOMUX_PAD(0x04D8, 0x0210, 2, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA4__CSI_DATA06                         = IOMUX_PAD(0x04D8, 0x0210, 3, 0x05E0, 1, 0),
+	MX6_PAD_SD2_DATA4__SPDIF_OUT                          = IOMUX_PAD(0x04D8, 0x0210, 4, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA4__GPIO5_IO02                         = IOMUX_PAD(0x04D8, 0x0210, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD2_DATA5__SD2_DATA5                          = IOMUX_PAD(0x04DC, 0x0214, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA5__SD3_DATA5                          = IOMUX_PAD(0x04DC, 0x0214, 1, 0x0788, 1, 0),
+	MX6_PAD_SD2_DATA5__UART2_DCE_TX                       = IOMUX_PAD(0x04DC, 0x0214, 2, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA5__UART2_DTE_RX                       = IOMUX_PAD(0x04DC, 0x0214, 2, 0x074C, 3, 0),
+	MX6_PAD_SD2_DATA5__CSI_DATA07                         = IOMUX_PAD(0x04DC, 0x0214, 3, 0x05E4, 1, 0),
+	MX6_PAD_SD2_DATA5__SPDIF_IN                           = IOMUX_PAD(0x04DC, 0x0214, 4, 0x0738, 1, 0),
+	MX6_PAD_SD2_DATA5__GPIO4_IO31                         = IOMUX_PAD(0x04DC, 0x0214, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD2_DATA6__SD2_DATA6                          = IOMUX_PAD(0x04E0, 0x0218, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA6__SD3_DATA6                          = IOMUX_PAD(0x04E0, 0x0218, 1, 0x078C, 1, 0),
+	MX6_PAD_SD2_DATA6__UART2_DCE_RTS                      = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0748, 2, 0),
+	MX6_PAD_SD2_DATA6__UART2_DTE_CTS                      = IOMUX_PAD(0x04E0, 0x0218, 2, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA6__CSI_DATA08                         = IOMUX_PAD(0x04E0, 0x0218, 3, 0x05E8, 1, 0),
+	MX6_PAD_SD2_DATA6__SD2_WP                             = IOMUX_PAD(0x04E0, 0x0218, 4, 0x077C, 1, 0),
+	MX6_PAD_SD2_DATA6__GPIO4_IO29                         = IOMUX_PAD(0x04E0, 0x0218, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD2_DATA7__SD2_DATA7                          = IOMUX_PAD(0x04E4, 0x021C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA7__SD3_DATA7                          = IOMUX_PAD(0x04E4, 0x021C, 1, 0x0790, 1, 0),
+	MX6_PAD_SD2_DATA7__UART2_DCE_CTS                      = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0000, 0, 0),
+	MX6_PAD_SD2_DATA7__UART2_DTE_RTS                      = IOMUX_PAD(0x04E4, 0x021C, 2, 0x0748, 3, 0),
+	MX6_PAD_SD2_DATA7__CSI_DATA09                         = IOMUX_PAD(0x04E4, 0x021C, 3, 0x05EC, 1, 0),
+	MX6_PAD_SD2_DATA7__SD2_CD_B                           = IOMUX_PAD(0x04E4, 0x021C, 4, 0x0778, 1, 0),
+	MX6_PAD_SD2_DATA7__GPIO5_IO00                         = IOMUX_PAD(0x04E4, 0x021C, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD3_CLK__SD3_CLK                              = IOMUX_PAD(0x04E8, 0x0220, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_CLK__AUD5_RXFS                            = IOMUX_PAD(0x04E8, 0x0220, 1, 0x0588, 0, 0),
+	MX6_PAD_SD3_CLK__KEY_COL5                             = IOMUX_PAD(0x04E8, 0x0220, 2, 0x0694, 0, 0),
+	MX6_PAD_SD3_CLK__CSI_DATA10                           = IOMUX_PAD(0x04E8, 0x0220, 3, 0x05B0, 0, 0),
+	MX6_PAD_SD3_CLK__WDOG1_RESET_B_DEB                    = IOMUX_PAD(0x04E8, 0x0220, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_CLK__GPIO5_IO18                           = IOMUX_PAD(0x04E8, 0x0220, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_CLK__USB_OTG1_PWR                         = IOMUX_PAD(0x04E8, 0x0220, 6, 0x0000, 0, 0),
+
+	MX6_PAD_SD3_CMD__SD3_CMD                              = IOMUX_PAD(0x04EC, 0x0224, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_CMD__AUD5_RXC                             = IOMUX_PAD(0x04EC, 0x0224, 1, 0x0584, 0, 0),
+	MX6_PAD_SD3_CMD__KEY_ROW5                             = IOMUX_PAD(0x04EC, 0x0224, 2, 0x06B4, 0, 0),
+	MX6_PAD_SD3_CMD__CSI_DATA11                           = IOMUX_PAD(0x04EC, 0x0224, 3, 0x05B4, 0, 0),
+	MX6_PAD_SD3_CMD__USB_OTG2_ID                          = IOMUX_PAD(0x04EC, 0x0224, 4, 0x0560, 1, 0),
+	MX6_PAD_SD3_CMD__GPIO5_IO21                           = IOMUX_PAD(0x04EC, 0x0224, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_CMD__USB_OTG2_PWR                         = IOMUX_PAD(0x04EC, 0x0224, 6, 0x0000, 0, 0),
+
+	MX6_PAD_SD3_DATA0__SD3_DATA0                          = IOMUX_PAD(0x04F0, 0x0228, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DATA0__AUD5_RXD                           = IOMUX_PAD(0x04F0, 0x0228, 1, 0x057C, 0, 0),
+	MX6_PAD_SD3_DATA0__KEY_COL6                           = IOMUX_PAD(0x04F0, 0x0228, 2, 0x0698, 0, 0),
+	MX6_PAD_SD3_DATA0__CSI_DATA12                         = IOMUX_PAD(0x04F0, 0x0228, 3, 0x05B8, 0, 0),
+	MX6_PAD_SD3_DATA0__USB_OTG1_ID                        = IOMUX_PAD(0x04F0, 0x0228, 4, 0x055C, 1, 0),
+	MX6_PAD_SD3_DATA0__GPIO5_IO19                         = IOMUX_PAD(0x04F0, 0x0228, 5, 0x0000, 0, 0),
+
+	MX6_PAD_SD3_DATA1__SD3_DATA1                          = IOMUX_PAD(0x04F4, 0x022C, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DATA1__AUD5_TXC                           = IOMUX_PAD(0x04F4, 0x022C, 1, 0x058C, 0, 0),
+	MX6_PAD_SD3_DATA1__KEY_ROW6                           = IOMUX_PAD(0x04F4, 0x022C, 2, 0x06B8, 0, 0),
+	MX6_PAD_SD3_DATA1__CSI_DATA13                         = IOMUX_PAD(0x04F4, 0x022C, 3, 0x05BC, 0, 0),
+	MX6_PAD_SD3_DATA1__SD1_VSELECT                        = IOMUX_PAD(0x04F4, 0x022C, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_DATA1__GPIO5_IO20                         = IOMUX_PAD(0x04F4, 0x022C, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_DATA1__JTAG_DE_B                          = IOMUX_PAD(0x04F4, 0x022C, 6, 0x0000, 0, 0),
+
+	MX6_PAD_SD3_DATA2__SD3_DATA2                          = IOMUX_PAD(0x04F8, 0x0230, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DATA2__AUD5_TXFS                          = IOMUX_PAD(0x04F8, 0x0230, 1, 0x0590, 0, 0),
+	MX6_PAD_SD3_DATA2__KEY_COL7                           = IOMUX_PAD(0x04F8, 0x0230, 2, 0x069C, 0, 0),
+	MX6_PAD_SD3_DATA2__CSI_DATA14                         = IOMUX_PAD(0x04F8, 0x0230, 3, 0x05C0, 0, 0),
+	MX6_PAD_SD3_DATA2__EPIT1_OUT                          = IOMUX_PAD(0x04F8, 0x0230, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_DATA2__GPIO5_IO16                         = IOMUX_PAD(0x04F8, 0x0230, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_DATA2__USB_OTG2_OC                        = IOMUX_PAD(0x04F8, 0x0230, 6, 0x0768, 0, 0),
+
+	MX6_PAD_SD3_DATA3__SD3_DATA3                          = IOMUX_PAD(0x04FC, 0x0234, 0, 0x0000, 0, 0),
+	MX6_PAD_SD3_DATA3__AUD5_TXD                           = IOMUX_PAD(0x04FC, 0x0234, 1, 0x0580, 0, 0),
+	MX6_PAD_SD3_DATA3__KEY_ROW7                           = IOMUX_PAD(0x04FC, 0x0234, 2, 0x06BC, 0, 0),
+	MX6_PAD_SD3_DATA3__CSI_DATA15                         = IOMUX_PAD(0x04FC, 0x0234, 3, 0x05C4, 0, 0),
+	MX6_PAD_SD3_DATA3__EPIT2_OUT                          = IOMUX_PAD(0x04FC, 0x0234, 4, 0x0000, 0, 0),
+	MX6_PAD_SD3_DATA3__GPIO5_IO17                         = IOMUX_PAD(0x04FC, 0x0234, 5, 0x0000, 0, 0),
+	MX6_PAD_SD3_DATA3__USB_OTG1_OC                        = IOMUX_PAD(0x04FC, 0x0234, 6, 0x076C, 0, 0),
+
+	MX6_PAD_GPIO4_IO20__SD1_STROBE                        = IOMUX_PAD(0x0500, 0x0238, 0, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO20__AUD6_RXFS                         = IOMUX_PAD(0x0500, 0x0238, 2, 0x05A0, 0, 0),
+	MX6_PAD_GPIO4_IO20__ECSPI4_SS0                        = IOMUX_PAD(0x0500, 0x0238, 3, 0x065C, 0, 0),
+	MX6_PAD_GPIO4_IO20__GPT_CAPTURE1                      = IOMUX_PAD(0x0500, 0x0238, 4, 0x0670, 0, 0),
+	MX6_PAD_GPIO4_IO20__GPIO4_IO20                        = IOMUX_PAD(0x0500, 0x0238, 5, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO4_IO21__SD2_STROBE                        = IOMUX_PAD(0x0504, 0x023C, 0, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO21__AUD6_RXC                          = IOMUX_PAD(0x0504, 0x023C, 2, 0x059C, 0, 0),
+	MX6_PAD_GPIO4_IO21__ECSPI4_SCLK                       = IOMUX_PAD(0x0504, 0x023C, 3, 0x0650, 0, 0),
+	MX6_PAD_GPIO4_IO21__GPT_CAPTURE2                      = IOMUX_PAD(0x0504, 0x023C, 4, 0x0674, 0, 0),
+	MX6_PAD_GPIO4_IO21__GPIO4_IO21                        = IOMUX_PAD(0x0504, 0x023C, 5, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO4_IO19__SD3_STROBE                        = IOMUX_PAD(0x0508, 0x0240, 0, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO19__AUD6_RXD                          = IOMUX_PAD(0x0508, 0x0240, 2, 0x0594, 0, 0),
+	MX6_PAD_GPIO4_IO19__ECSPI4_MOSI                       = IOMUX_PAD(0x0508, 0x0240, 3, 0x0658, 0, 0),
+	MX6_PAD_GPIO4_IO19__GPT_COMPARE1                      = IOMUX_PAD(0x0508, 0x0240, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO19__GPIO4_IO19                        = IOMUX_PAD(0x0508, 0x0240, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO25__AUD6_TXC                          = IOMUX_PAD(0x050C, 0x0244, 2, 0x05A4, 0, 0),
+	MX6_PAD_GPIO4_IO25__ECSPI4_MISO                       = IOMUX_PAD(0x050C, 0x0244, 3, 0x0654, 0, 0),
+	MX6_PAD_GPIO4_IO25__GPT_COMPARE2                      = IOMUX_PAD(0x050C, 0x0244, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO25__GPIO4_IO25                        = IOMUX_PAD(0x050C, 0x0244, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO18__AUD6_TXFS                         = IOMUX_PAD(0x0510, 0x0248, 2, 0x05A8, 0, 0),
+	MX6_PAD_GPIO4_IO18__ECSPI4_SS1                        = IOMUX_PAD(0x0510, 0x0248, 3, 0x0660, 0, 0),
+	MX6_PAD_GPIO4_IO18__GPT_COMPARE3                      = IOMUX_PAD(0x0510, 0x0248, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO18__GPIO4_IO18                        = IOMUX_PAD(0x0510, 0x0248, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO24__AUD6_TXD                          = IOMUX_PAD(0x0514, 0x024C, 2, 0x0598, 0, 0),
+	MX6_PAD_GPIO4_IO24__ECSPI4_SS2                        = IOMUX_PAD(0x0514, 0x024C, 3, 0x0664, 0, 0),
+	MX6_PAD_GPIO4_IO24__GPT_CLKIN                         = IOMUX_PAD(0x0514, 0x024C, 4, 0x0678, 0, 0),
+	MX6_PAD_GPIO4_IO24__GPIO4_IO24                        = IOMUX_PAD(0x0514, 0x024C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO23__AUDIO_CLK_OUT                     = IOMUX_PAD(0x0518, 0x0250, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO23__SD1_RESET                         = IOMUX_PAD(0x0518, 0x0250, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO23__SD3_RESET                         = IOMUX_PAD(0x0518, 0x0250, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO23__GPIO4_IO23                        = IOMUX_PAD(0x0518, 0x0250, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO17__USB_OTG1_ID                       = IOMUX_PAD(0x051C, 0x0254, 2, 0x055C, 2, 0),
+	MX6_PAD_GPIO4_IO17__SD1_VSELECT                       = IOMUX_PAD(0x051C, 0x0254, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO17__SD3_VSELECT                       = IOMUX_PAD(0x051C, 0x0254, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO17__GPIO4_IO17                        = IOMUX_PAD(0x051C, 0x0254, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO22__SPDIF_IN                          = IOMUX_PAD(0x0520, 0x0258, 2, 0x0738, 0, 0),
+	MX6_PAD_GPIO4_IO22__SD1_WP                            = IOMUX_PAD(0x0520, 0x0258, 3, 0x0774, 0, 0),
+	MX6_PAD_GPIO4_IO22__SD3_WP                            = IOMUX_PAD(0x0520, 0x0258, 4, 0x0794, 1, 0),
+	MX6_PAD_GPIO4_IO22__GPIO4_IO22                        = IOMUX_PAD(0x0520, 0x0258, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO16__SPDIF_OUT                         = IOMUX_PAD(0x0524, 0x025C, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO16__SD1_CD_B                          = IOMUX_PAD(0x0524, 0x025C, 3, 0x0770, 0, 0),
+	MX6_PAD_GPIO4_IO16__SD3_CD_B                          = IOMUX_PAD(0x0524, 0x025C, 4, 0x0780, 1, 0),
+	MX6_PAD_GPIO4_IO16__GPIO4_IO16                        = IOMUX_PAD(0x0524, 0x025C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO26__WDOG1_B                           = IOMUX_PAD(0x0528, 0x0260, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO26__PWM4_OUT                          = IOMUX_PAD(0x0528, 0x0260, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO26__CCM_PMIC_READY                    = IOMUX_PAD(0x0528, 0x0260, 4, 0x05AC, 1, 0),
+	MX6_PAD_GPIO4_IO26__GPIO4_IO26                        = IOMUX_PAD(0x0528, 0x0260, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO4_IO26__SPDIF_EXT_CLK                     = IOMUX_PAD(0x0528, 0x0260, 6, 0x073C, 0, 0),
+};
+#endif  /* __ASM_ARCH_IMX6SLL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h b/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h
new file mode 100644
index 0000000..5ad93ed
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_MX6SX_DDR_H__
+#define __ASM_ARCH_MX6SX_DDR_H__
+
+#ifndef CONFIG_MX6SX
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_DQM0	0x020e02ec
+#define MX6_IOM_DRAM_DQM1	0x020e02f0
+#define MX6_IOM_DRAM_DQM2	0x020e02f4
+#define MX6_IOM_DRAM_DQM3	0x020e02f8
+
+#define MX6_IOM_DRAM_RAS	0x020e02fc
+#define MX6_IOM_DRAM_CAS	0x020e0300
+#define MX6_IOM_DRAM_SDODT0	0x020e0310
+#define MX6_IOM_DRAM_SDODT1	0x020e0314
+#define MX6_IOM_DRAM_SDBA2	0x020e0320
+#define MX6_IOM_DRAM_SDCKE0	0x020e0324
+#define MX6_IOM_DRAM_SDCKE1	0x020e0328
+#define MX6_IOM_DRAM_SDCLK_0	0x020e032c
+#define MX6_IOM_DRAM_RESET	0x020e0340
+
+#define MX6_IOM_DRAM_SDQS0	0x020e0330
+#define MX6_IOM_DRAM_SDQS1	0x020e0334
+#define MX6_IOM_DRAM_SDQS2	0x020e0338
+#define MX6_IOM_DRAM_SDQS3	0x020e033c
+
+#define MX6_IOM_GRP_ADDDS	0x020e05f4
+#define MX6_IOM_DDRMODE_CTL	0x020e05f8
+#define MX6_IOM_GRP_DDRPKE	0x020e05fc
+#define MX6_IOM_GRP_DDRMODE	0x020e0608
+#define MX6_IOM_GRP_B0DS	0x020e060c
+#define MX6_IOM_GRP_B1DS	0x020e0610
+#define MX6_IOM_GRP_CTLDS	0x020e0614
+#define MX6_IOM_GRP_DDR_TYPE	0x020e0618
+#define MX6_IOM_GRP_B2DS	0x020e061c
+#define MX6_IOM_GRP_B3DS	0x020e0620
+
+#endif	/*__ASM_ARCH_MX6SX_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
new file mode 100644
index 0000000..a18e08f
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
@@ -0,0 +1,1674 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6_PINS_H__
+#define __ASM_ARCH_MX6_MX6_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+	 MX6_PAD_GPIO1_IO00__I2C1_SCL                           = IOMUX_PAD(0x035C, 0x0014, IOMUX_CONFIG_SION | 0, 0x07A8, 1, 0),
+	 MX6_PAD_GPIO1_IO00__USDHC1_VSELECT                     = IOMUX_PAD(0x035C, 0x0014, 1, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO00__SPDIF_LOCK                         = IOMUX_PAD(0x035C, 0x0014, 2, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO00__CCM_WAIT                           = IOMUX_PAD(0x035C, 0x0014, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO00__WDOG1_WDOG_ANY                     = IOMUX_PAD(0x035C, 0x0014, 4, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO00__GPIO1_IO_0                         = IOMUX_PAD(0x035C, 0x0014, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5              = IOMUX_PAD(0x035C, 0x0014, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO00__PHY_DTB_1                          = IOMUX_PAD(0x035C, 0x0014, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO01__I2C1_SDA                           = IOMUX_PAD(0x0360, 0x0018, IOMUX_CONFIG_SION | 0, 0x07AC, 1, 0),
+	 MX6_PAD_GPIO1_IO01__USDHC1_RESET_B                     = IOMUX_PAD(0x0360, 0x0018, 1, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO01__SPDIF_SR_CLK                       = IOMUX_PAD(0x0360, 0x0018, 2, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO01__CCM_STOP                           = IOMUX_PAD(0x0360, 0x0018, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO01__WDOG3_WDOG_B                       = IOMUX_PAD(0x0360, 0x0018, 4, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO01__GPIO1_IO_1                         = IOMUX_PAD(0x0360, 0x0018, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL          = IOMUX_PAD(0x0360, 0x0018, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO01__PHY_DTB_0                          = IOMUX_PAD(0x0360, 0x0018, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO02__I2C2_SCL                           = IOMUX_PAD(0x0364, 0x001C, IOMUX_CONFIG_SION | 0, 0x07B0, 1, 0),
+	 MX6_PAD_GPIO1_IO02__USDHC1_CD_B                        = IOMUX_PAD(0x0364, 0x001C, 1, 0x0864, 1, 0),
+	 MX6_PAD_GPIO1_IO02__CSI2_MCLK                          = IOMUX_PAD(0x0364, 0x001C, 2, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK                    = IOMUX_PAD(0x0364, 0x001C, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO02__WDOG1_WDOG_B                       = IOMUX_PAD(0x0364, 0x001C, 4, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO02__GPIO1_IO_2                         = IOMUX_PAD(0x0364, 0x001C, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO02__CCM_REF_EN_B                       = IOMUX_PAD(0x0364, 0x001C, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO02__PHY_TDI                            = IOMUX_PAD(0x0364, 0x001C, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO03__I2C2_SDA                           = IOMUX_PAD(0x0368, 0x0020, IOMUX_CONFIG_SION | 0, 0x07B4, 1, 0),
+	 MX6_PAD_GPIO1_IO03__USDHC1_WP                          = IOMUX_PAD(0x0368, 0x0020, 1, 0x0868, 1, 0),
+	 MX6_PAD_GPIO1_IO03__ENET1_REF_CLK_25M                  = IOMUX_PAD(0x0368, 0x0020, 2, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK                    = IOMUX_PAD(0x0368, 0x0020, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO03__WDOG2_WDOG_B                       = IOMUX_PAD(0x0368, 0x0020, 4, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO03__GPIO1_IO_3                         = IOMUX_PAD(0x0368, 0x0020, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO03__CCM_PLL3_BYP                       = IOMUX_PAD(0x0368, 0x0020, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO03__PHY_TCK                            = IOMUX_PAD(0x0368, 0x0020, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO04__UART1_TX                           = IOMUX_PAD(0x036C, 0x0024, 0, 0x0830, 0, 0),
+	 MX6_PAD_GPIO1_IO04__USDHC2_RESET_B                     = IOMUX_PAD(0x036C, 0x0024, 1, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO04__ENET1_MDC                          = IOMUX_PAD(0x036C, 0x0024, 2, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO04__OSC32K_32K_OUT                     = IOMUX_PAD(0x036C, 0x0024, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO04__ENET2_REF_CLK2                     = IOMUX_PAD(0x036C, 0x0024, 4, 0x076C, 0, 0),
+	 MX6_PAD_GPIO1_IO04__GPIO1_IO_4                         = IOMUX_PAD(0x036C, 0x0024, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO04__CCM_PLL2_BYP                       = IOMUX_PAD(0x036C, 0x0024, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO04__PHY_TMS                            = IOMUX_PAD(0x036C, 0x0024, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO05__UART1_RX                           = IOMUX_PAD(0x0370, 0x0028, 0, 0x0830, 1, 0),
+	 MX6_PAD_GPIO1_IO05__USDHC2_VSELECT                     = IOMUX_PAD(0x0370, 0x0028, 1, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO05__ENET1_MDIO                         = IOMUX_PAD(0x0370, 0x0028, 2, 0x0764, 0, 0),
+	 MX6_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK                  = IOMUX_PAD(0x0370, 0x0028, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO05__ENET1_REF_CLK1                     = IOMUX_PAD(0x0370, 0x0028, 4, 0x0760, 0, 0),
+	 MX6_PAD_GPIO1_IO05__GPIO1_IO_5                         = IOMUX_PAD(0x0370, 0x0028, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO05__SRC_TESTER_ACK                     = IOMUX_PAD(0x0370, 0x0028, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO05__PHY_TDO                            = IOMUX_PAD(0x0370, 0x0028, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO06__UART2_TX                           = IOMUX_PAD(0x0374, 0x002C, 0, 0x0838, 0, 0),
+	 MX6_PAD_GPIO1_IO06__USDHC2_CD_B                        = IOMUX_PAD(0x0374, 0x002C, 1, 0x086C, 1, 0),
+	 MX6_PAD_GPIO1_IO06__ENET2_MDC                          = IOMUX_PAD(0x0374, 0x002C, 2, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO06__CSI1_MCLK                          = IOMUX_PAD(0x0374, 0x002C, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO06__UART1_RTS_B                        = IOMUX_PAD(0x0374, 0x002C, 4, 0x082C, 0, 0),
+	 MX6_PAD_GPIO1_IO06__GPIO1_IO_6                         = IOMUX_PAD(0x0374, 0x002C, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO06__SRC_ANY_PU_RESET                   = IOMUX_PAD(0x0374, 0x002C, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED    = IOMUX_PAD(0x0374, 0x002C, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO07__UART2_RX                           = IOMUX_PAD(0x0378, 0x0030, 0, 0x0838, 1, 0),
+	 MX6_PAD_GPIO1_IO07__USDHC2_WP                          = IOMUX_PAD(0x0378, 0x0030, 1, 0x0870, 1, 0),
+	 MX6_PAD_GPIO1_IO07__ENET2_MDIO                         = IOMUX_PAD(0x0378, 0x0030, 2, 0x0770, 0, 0),
+	 MX6_PAD_GPIO1_IO07__AUDMUX_MCLK                        = IOMUX_PAD(0x0378, 0x0030, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO07__UART1_CTS_B                        = IOMUX_PAD(0x0378, 0x0030, 4, 0x082C, 1, 0),
+	 MX6_PAD_GPIO1_IO07__GPIO1_IO_7                         = IOMUX_PAD(0x0378, 0x0030, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO07__SRC_EARLY_RESET                    = IOMUX_PAD(0x0378, 0x0030, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO07__DCIC2_OUT                          = IOMUX_PAD(0x0378, 0x0030, 7, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO07__VDEC_DEBUG_44                      = IOMUX_PAD(0x0378, 0x0030, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO08__USB_OTG1_OC                        = IOMUX_PAD(0x037C, 0x0034, 0, 0x0860, 0, 0),
+	 MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B                       = IOMUX_PAD(0x037C, 0x0034, 1, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0                   = IOMUX_PAD(0x037C, 0x0034, 2, 0x081C, 0, 0),
+	 MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY                       = IOMUX_PAD(0x037C, 0x0034, 3, 0x069C, 1, 0),
+	 MX6_PAD_GPIO1_IO08__UART2_RTS_B                        = IOMUX_PAD(0x037C, 0x0034, 4, 0x0834, 0, 0),
+	 MX6_PAD_GPIO1_IO08__GPIO1_IO_8                         = IOMUX_PAD(0x037C, 0x0034, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO08__SRC_SYSTEM_RESET                   = IOMUX_PAD(0x037C, 0x0034, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO08__DCIC1_OUT                          = IOMUX_PAD(0x037C, 0x0034, 7, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO08__VDEC_DEBUG_43                      = IOMUX_PAD(0x037C, 0x0034, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR                       = IOMUX_PAD(0x0380, 0x0038, 0, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO09__WDOG2_WDOG_B                       = IOMUX_PAD(0x0380, 0x0038, 1, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1                   = IOMUX_PAD(0x0380, 0x0038, 2, 0x0820, 0, 0),
+	 MX6_PAD_GPIO1_IO09__CCM_OUT0                           = IOMUX_PAD(0x0380, 0x0038, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO09__UART2_CTS_B                        = IOMUX_PAD(0x0380, 0x0038, 4, 0x0834, 1, 0),
+	 MX6_PAD_GPIO1_IO09__GPIO1_IO_9                         = IOMUX_PAD(0x0380, 0x0038, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO09__SRC_INT_BOOT                       = IOMUX_PAD(0x0380, 0x0038, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4                  = IOMUX_PAD(0x0380, 0x0038, 7, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO09__VDEC_DEBUG_42                      = IOMUX_PAD(0x0380, 0x0038, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID                     = IOMUX_PAD(0x0384, 0x003C, 0, 0x0624, 0, 0),
+	 MX6_PAD_GPIO1_IO10__SPDIF_EXT_CLK                      = IOMUX_PAD(0x0384, 0x003C, 1, 0x0828, 0, 0),
+	 MX6_PAD_GPIO1_IO10__PWM1_OUT                           = IOMUX_PAD(0x0384, 0x003C, 2, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO10__CCM_OUT1                           = IOMUX_PAD(0x0384, 0x003C, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO10__CSI1_FIELD                         = IOMUX_PAD(0x0384, 0x003C, 4, 0x070C, 1, 0),
+	 MX6_PAD_GPIO1_IO10__GPIO1_IO_10                        = IOMUX_PAD(0x0384, 0x003C, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO10__CSU_CSU_INT_DEB                    = IOMUX_PAD(0x0384, 0x003C, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3                  = IOMUX_PAD(0x0384, 0x003C, 7, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO10__VDEC_DEBUG_41                      = IOMUX_PAD(0x0384, 0x003C, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO11__USB_OTG2_OC                        = IOMUX_PAD(0x0388, 0x0040, 0, 0x085C, 0, 0),
+	 MX6_PAD_GPIO1_IO11__SPDIF_IN                           = IOMUX_PAD(0x0388, 0x0040, 1, 0x0824, 2, 0),
+	 MX6_PAD_GPIO1_IO11__PWM2_OUT                           = IOMUX_PAD(0x0388, 0x0040, 2, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO11__CCM_CLKO1                          = IOMUX_PAD(0x0388, 0x0040, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO11__MLB_DATA                           = IOMUX_PAD(0x0388, 0x0040, 4, 0x07EC, 0, 0),
+	 MX6_PAD_GPIO1_IO11__GPIO1_IO_11                        = IOMUX_PAD(0x0388, 0x0040, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0                = IOMUX_PAD(0x0388, 0x0040, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2                  = IOMUX_PAD(0x0388, 0x0040, 7, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO11__VDEC_DEBUG_40                      = IOMUX_PAD(0x0388, 0x0040, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR                       = IOMUX_PAD(0x038C, 0x0044, 0, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO12__SPDIF_OUT                          = IOMUX_PAD(0x038C, 0x0044, 1, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO12__PWM3_OUT                           = IOMUX_PAD(0x038C, 0x0044, 2, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO12__CCM_CLKO2                          = IOMUX_PAD(0x038C, 0x0044, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO12__MLB_CLK                            = IOMUX_PAD(0x038C, 0x0044, 4, 0x07E8, 0, 0),
+	 MX6_PAD_GPIO1_IO12__GPIO1_IO_12                        = IOMUX_PAD(0x038C, 0x0044, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1                = IOMUX_PAD(0x038C, 0x0044, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1                  = IOMUX_PAD(0x038C, 0x0044, 7, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO12__VDEC_DEBUG_39                      = IOMUX_PAD(0x038C, 0x0044, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_GPIO1_IO13__WDOG1_WDOG_ANY                     = IOMUX_PAD(0x0390, 0x0048, 0, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO13__ANATOP_OTG2_ID                     = IOMUX_PAD(0x0390, 0x0048, 1, 0x0628, 0, 0),
+	 MX6_PAD_GPIO1_IO13__PWM4_OUT                           = IOMUX_PAD(0x0390, 0x0048, 2, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO13__CCM_OUT2                           = IOMUX_PAD(0x0390, 0x0048, 3, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO13__MLB_SIG                            = IOMUX_PAD(0x0390, 0x0048, 4, 0x07F0, 0, 0),
+	 MX6_PAD_GPIO1_IO13__GPIO1_IO_13                        = IOMUX_PAD(0x0390, 0x0048, 5, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2                = IOMUX_PAD(0x0390, 0x0048, 6, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0                  = IOMUX_PAD(0x0390, 0x0048, 7, 0x0000, 0, 0),
+	 MX6_PAD_GPIO1_IO13__VDEC_DEBUG_38                      = IOMUX_PAD(0x0390, 0x0048, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_DATA00__CSI1_DATA_2                        = IOMUX_PAD(0x0394, 0x004C, 0, 0x06A8, 0, 0),
+	 MX6_PAD_CSI_DATA00__ESAI_TX_CLK                        = IOMUX_PAD(0x0394, 0x004C, 1, 0x078C, 1, 0),
+	 MX6_PAD_CSI_DATA00__AUDMUX_AUD6_TXC                    = IOMUX_PAD(0x0394, 0x004C, 2, 0x0684, 1, 0),
+	 MX6_PAD_CSI_DATA00__I2C1_SCL                           = IOMUX_PAD(0x0394, 0x004C, IOMUX_CONFIG_SION | 3, 0x07A8, 0, 0),
+	 MX6_PAD_CSI_DATA00__UART6_RI_B                         = IOMUX_PAD(0x0394, 0x004C, 4, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA00__GPIO1_IO_14                        = IOMUX_PAD(0x0394, 0x004C, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA00__WEIM_DATA_23                       = IOMUX_PAD(0x0394, 0x004C, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA00__SAI1_TX_BCLK                       = IOMUX_PAD(0x0394, 0x004C, 7, 0x0800, 0, 0),
+	 MX6_PAD_CSI_DATA00__VADC_DATA_4                        = IOMUX_PAD(0x0394, 0x004C, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA00__MMDC_DEBUG_37                      = IOMUX_PAD(0x0394, 0x004C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_DATA01__CSI1_DATA_3                        = IOMUX_PAD(0x0398, 0x0050, 0, 0x06AC, 0, 0),
+	 MX6_PAD_CSI_DATA01__ESAI_TX_FS                         = IOMUX_PAD(0x0398, 0x0050, 1, 0x077C, 1, 0),
+	 MX6_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS                   = IOMUX_PAD(0x0398, 0x0050, 2, 0x0688, 1, 0),
+	 MX6_PAD_CSI_DATA01__I2C1_SDA                           = IOMUX_PAD(0x0398, 0x0050, IOMUX_CONFIG_SION | 3, 0x07AC, 0, 0),
+	 MX6_PAD_CSI_DATA01__UART6_DSR_B                        = IOMUX_PAD(0x0398, 0x0050, 4, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA01__GPIO1_IO_15                        = IOMUX_PAD(0x0398, 0x0050, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA01__WEIM_DATA_22                       = IOMUX_PAD(0x0398, 0x0050, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA01__SAI1_TX_SYNC                       = IOMUX_PAD(0x0398, 0x0050, 7, 0x0804, 0, 0),
+	 MX6_PAD_CSI_DATA01__VADC_DATA_5                        = IOMUX_PAD(0x0398, 0x0050, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA01__MMDC_DEBUG_38                      = IOMUX_PAD(0x0398, 0x0050, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_DATA02__CSI1_DATA_4                        = IOMUX_PAD(0x039C, 0x0054, 0, 0x06B0, 0, 0),
+	 MX6_PAD_CSI_DATA02__ESAI_RX_CLK                        = IOMUX_PAD(0x039C, 0x0054, 1, 0x0788, 1, 0),
+	 MX6_PAD_CSI_DATA02__AUDMUX_AUD6_RXC                    = IOMUX_PAD(0x039C, 0x0054, 2, 0x067C, 1, 0),
+	 MX6_PAD_CSI_DATA02__KPP_COL_5                          = IOMUX_PAD(0x039C, 0x0054, 3, 0x07C8, 0, 0),
+	 MX6_PAD_CSI_DATA02__UART6_DTR_B                        = IOMUX_PAD(0x039C, 0x0054, 4, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA02__GPIO1_IO_16                        = IOMUX_PAD(0x039C, 0x0054, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA02__WEIM_DATA_21                       = IOMUX_PAD(0x039C, 0x0054, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA02__SAI1_RX_BCLK                       = IOMUX_PAD(0x039C, 0x0054, 7, 0x07F4, 0, 0),
+	 MX6_PAD_CSI_DATA02__VADC_DATA_6                        = IOMUX_PAD(0x039C, 0x0054, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA02__MMDC_DEBUG_39                      = IOMUX_PAD(0x039C, 0x0054, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_DATA03__CSI1_DATA_5                        = IOMUX_PAD(0x03A0, 0x0058, 0, 0x06B4, 0, 0),
+	 MX6_PAD_CSI_DATA03__ESAI_RX_FS                         = IOMUX_PAD(0x03A0, 0x0058, 1, 0x0778, 1, 0),
+	 MX6_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS                   = IOMUX_PAD(0x03A0, 0x0058, 2, 0x0680, 1, 0),
+	 MX6_PAD_CSI_DATA03__KPP_ROW_5                          = IOMUX_PAD(0x03A0, 0x0058, 3, 0x07D4, 0, 0),
+	 MX6_PAD_CSI_DATA03__UART6_DCD_B                        = IOMUX_PAD(0x03A0, 0x0058, 4, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA03__GPIO1_IO_17                        = IOMUX_PAD(0x03A0, 0x0058, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA03__WEIM_DATA_20                       = IOMUX_PAD(0x03A0, 0x0058, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA03__SAI1_RX_SYNC                       = IOMUX_PAD(0x03A0, 0x0058, 7, 0x07FC, 0, 0),
+	 MX6_PAD_CSI_DATA03__VADC_DATA_7                        = IOMUX_PAD(0x03A0, 0x0058, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA03__MMDC_DEBUG_40                      = IOMUX_PAD(0x03A0, 0x0058, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_DATA04__CSI1_DATA_6                        = IOMUX_PAD(0x03A4, 0x005C, 0, 0x06B8, 0, 0),
+	 MX6_PAD_CSI_DATA04__ESAI_TX1                           = IOMUX_PAD(0x03A4, 0x005C, 1, 0x0794, 1, 0),
+	 MX6_PAD_CSI_DATA04__SPDIF_OUT                          = IOMUX_PAD(0x03A4, 0x005C, 2, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA04__KPP_COL_6                          = IOMUX_PAD(0x03A4, 0x005C, 3, 0x07CC, 0, 0),
+	 MX6_PAD_CSI_DATA04__UART6_RX                           = IOMUX_PAD(0x03A4, 0x005C, 4, 0x0858, 0, 0),
+	 MX6_PAD_CSI_DATA04__GPIO1_IO_18                        = IOMUX_PAD(0x03A4, 0x005C, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA04__WEIM_DATA_19                       = IOMUX_PAD(0x03A4, 0x005C, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA04__PWM5_OUT                           = IOMUX_PAD(0x03A4, 0x005C, 7, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA04__VADC_DATA_8                        = IOMUX_PAD(0x03A4, 0x005C, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA04__MMDC_DEBUG_41                      = IOMUX_PAD(0x03A4, 0x005C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_DATA05__CSI1_DATA_7                        = IOMUX_PAD(0x03A8, 0x0060, 0, 0x06BC, 0, 0),
+	 MX6_PAD_CSI_DATA05__ESAI_TX4_RX1                       = IOMUX_PAD(0x03A8, 0x0060, 1, 0x07A0, 1, 0),
+	 MX6_PAD_CSI_DATA05__SPDIF_IN                           = IOMUX_PAD(0x03A8, 0x0060, 2, 0x0824, 1, 0),
+	 MX6_PAD_CSI_DATA05__KPP_ROW_6                          = IOMUX_PAD(0x03A8, 0x0060, 3, 0x07D8, 0, 0),
+	 MX6_PAD_CSI_DATA05__UART6_TX                           = IOMUX_PAD(0x03A8, 0x0060, 4, 0x0858, 1, 0),
+	 MX6_PAD_CSI_DATA05__GPIO1_IO_19                        = IOMUX_PAD(0x03A8, 0x0060, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA05__WEIM_DATA_18                       = IOMUX_PAD(0x03A8, 0x0060, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA05__PWM6_OUT                           = IOMUX_PAD(0x03A8, 0x0060, 7, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA05__VADC_DATA_9                        = IOMUX_PAD(0x03A8, 0x0060, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA05__MMDC_DEBUG_42                      = IOMUX_PAD(0x03A8, 0x0060, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_DATA06__CSI1_DATA_8                        = IOMUX_PAD(0x03AC, 0x0064, 0, 0x06C0, 0, 0),
+	 MX6_PAD_CSI_DATA06__ESAI_TX2_RX3                       = IOMUX_PAD(0x03AC, 0x0064, 1, 0x0798, 1, 0),
+	 MX6_PAD_CSI_DATA06__I2C4_SCL                           = IOMUX_PAD(0x03AC, 0x0064, IOMUX_CONFIG_SION | 2, 0x07C0, 2, 0),
+	 MX6_PAD_CSI_DATA06__KPP_COL_7                          = IOMUX_PAD(0x03AC, 0x0064, 3, 0x07D0, 0, 0),
+	 MX6_PAD_CSI_DATA06__UART6_RTS_B                        = IOMUX_PAD(0x03AC, 0x0064, 4, 0x0854, 0, 0),
+	 MX6_PAD_CSI_DATA06__GPIO1_IO_20                        = IOMUX_PAD(0x03AC, 0x0064, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA06__WEIM_DATA_17                       = IOMUX_PAD(0x03AC, 0x0064, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA06__DCIC2_OUT                          = IOMUX_PAD(0x03AC, 0x0064, 7, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA06__VADC_DATA_10                       = IOMUX_PAD(0x03AC, 0x0064, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA06__MMDC_DEBUG_43                      = IOMUX_PAD(0x03AC, 0x0064, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_DATA07__CSI1_DATA_9                        = IOMUX_PAD(0x03B0, 0x0068, 0, 0x06C4, 0, 0),
+	 MX6_PAD_CSI_DATA07__ESAI_TX3_RX2                       = IOMUX_PAD(0x03B0, 0x0068, 1, 0x079C, 1, 0),
+	 MX6_PAD_CSI_DATA07__I2C4_SDA                           = IOMUX_PAD(0x03B0, 0x0068, IOMUX_CONFIG_SION | 2, 0x07C4, 2, 0),
+	 MX6_PAD_CSI_DATA07__KPP_ROW_7                          = IOMUX_PAD(0x03B0, 0x0068, 3, 0x07DC, 0, 0),
+	 MX6_PAD_CSI_DATA07__UART6_CTS_B                        = IOMUX_PAD(0x03B0, 0x0068, 4, 0x0854, 1, 0),
+	 MX6_PAD_CSI_DATA07__GPIO1_IO_21                        = IOMUX_PAD(0x03B0, 0x0068, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA07__WEIM_DATA_16                       = IOMUX_PAD(0x03B0, 0x0068, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA07__DCIC1_OUT                          = IOMUX_PAD(0x03B0, 0x0068, 7, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA07__VADC_DATA_11                       = IOMUX_PAD(0x03B0, 0x0068, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_DATA07__MMDC_DEBUG_44                      = IOMUX_PAD(0x03B0, 0x0068, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_HSYNC__CSI1_HSYNC                          = IOMUX_PAD(0x03B4, 0x006C, 0, 0x0700, 0, 0),
+	 MX6_PAD_CSI_HSYNC__ESAI_TX0                            = IOMUX_PAD(0x03B4, 0x006C, 1, 0x0790, 1, 0),
+	 MX6_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD                     = IOMUX_PAD(0x03B4, 0x006C, 2, 0x0678, 1, 0),
+	 MX6_PAD_CSI_HSYNC__UART4_RTS_B                         = IOMUX_PAD(0x03B4, 0x006C, 3, 0x0844, 2, 0),
+	 MX6_PAD_CSI_HSYNC__MQS_LEFT                            = IOMUX_PAD(0x03B4, 0x006C, 4, 0x0000, 0, 0),
+	 MX6_PAD_CSI_HSYNC__GPIO1_IO_22                         = IOMUX_PAD(0x03B4, 0x006C, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_HSYNC__WEIM_DATA_25                        = IOMUX_PAD(0x03B4, 0x006C, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_HSYNC__SAI1_TX_DATA_0                      = IOMUX_PAD(0x03B4, 0x006C, 7, 0x0000, 0, 0),
+	 MX6_PAD_CSI_HSYNC__VADC_DATA_2                         = IOMUX_PAD(0x03B4, 0x006C, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_HSYNC__MMDC_DEBUG_35                       = IOMUX_PAD(0x03B4, 0x006C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_MCLK__CSI1_MCLK                            = IOMUX_PAD(0x03B8, 0x0070, 0, 0x0000, 0, 0),
+	 MX6_PAD_CSI_MCLK__ESAI_TX_HF_CLK                       = IOMUX_PAD(0x03B8, 0x0070, 1, 0x0784, 1, 0),
+	 MX6_PAD_CSI_MCLK__OSC32K_32K_OUT                       = IOMUX_PAD(0x03B8, 0x0070, 2, 0x0000, 0, 0),
+	 MX6_PAD_CSI_MCLK__UART4_RX                             = IOMUX_PAD(0x03B8, 0x0070, 3, 0x0848, 2, 0),
+	 MX6_PAD_CSI_MCLK__ANATOP_32K_OUT                       = IOMUX_PAD(0x03B8, 0x0070, 4, 0x0000, 0, 0),
+	 MX6_PAD_CSI_MCLK__GPIO1_IO_23                          = IOMUX_PAD(0x03B8, 0x0070, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_MCLK__WEIM_DATA_26                         = IOMUX_PAD(0x03B8, 0x0070, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_MCLK__CSI1_FIELD                           = IOMUX_PAD(0x03B8, 0x0070, 7, 0x070C, 0, 0),
+	 MX6_PAD_CSI_MCLK__VADC_DATA_1                          = IOMUX_PAD(0x03B8, 0x0070, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_MCLK__MMDC_DEBUG_34                        = IOMUX_PAD(0x03B8, 0x0070, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_PIXCLK__CSI1_PIXCLK                        = IOMUX_PAD(0x03BC, 0x0074, 0, 0x0704, 0, 0),
+	 MX6_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK                     = IOMUX_PAD(0x03BC, 0x0074, 1, 0x0780, 1, 0),
+	 MX6_PAD_CSI_PIXCLK__AUDMUX_MCLK                        = IOMUX_PAD(0x03BC, 0x0074, 2, 0x0000, 0, 0),
+	 MX6_PAD_CSI_PIXCLK__UART4_TX                           = IOMUX_PAD(0x03BC, 0x0074, 3, 0x0848, 3, 0),
+	 MX6_PAD_CSI_PIXCLK__ANATOP_24M_OUT                     = IOMUX_PAD(0x03BC, 0x0074, 4, 0x0000, 0, 0),
+	 MX6_PAD_CSI_PIXCLK__GPIO1_IO_24                        = IOMUX_PAD(0x03BC, 0x0074, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_PIXCLK__WEIM_DATA_27                       = IOMUX_PAD(0x03BC, 0x0074, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK                     = IOMUX_PAD(0x03BC, 0x0074, 7, 0x0784, 2, 0),
+	 MX6_PAD_CSI_PIXCLK__VADC_CLK                           = IOMUX_PAD(0x03BC, 0x0074, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_PIXCLK__MMDC_DEBUG_33                      = IOMUX_PAD(0x03BC, 0x0074, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_CSI_VSYNC__CSI1_VSYNC                          = IOMUX_PAD(0x03C0, 0x0078, 0, 0x0708, 0, 0),
+	 MX6_PAD_CSI_VSYNC__ESAI_TX5_RX0                        = IOMUX_PAD(0x03C0, 0x0078, 1, 0x07A4, 1, 0),
+	 MX6_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD                     = IOMUX_PAD(0x03C0, 0x0078, 2, 0x0674, 1, 0),
+	 MX6_PAD_CSI_VSYNC__UART4_CTS_B                         = IOMUX_PAD(0x03C0, 0x0078, 3, 0x0844, 3, 0),
+	 MX6_PAD_CSI_VSYNC__MQS_RIGHT                           = IOMUX_PAD(0x03C0, 0x0078, 4, 0x0000, 0, 0),
+	 MX6_PAD_CSI_VSYNC__GPIO1_IO_25                         = IOMUX_PAD(0x03C0, 0x0078, 5, 0x0000, 0, 0),
+	 MX6_PAD_CSI_VSYNC__WEIM_DATA_24                        = IOMUX_PAD(0x03C0, 0x0078, 6, 0x0000, 0, 0),
+	 MX6_PAD_CSI_VSYNC__SAI1_RX_DATA_0                      = IOMUX_PAD(0x03C0, 0x0078, 7, 0x07F8, 0, 0),
+	 MX6_PAD_CSI_VSYNC__VADC_DATA_3                         = IOMUX_PAD(0x03C0, 0x0078, 8, 0x0000, 0, 0),
+	 MX6_PAD_CSI_VSYNC__MMDC_DEBUG_36                       = IOMUX_PAD(0x03C0, 0x0078, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_ENET1_COL__ENET1_COL                           = IOMUX_PAD(0x03C4, 0x007C, 0, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_COL__ENET2_MDC                           = IOMUX_PAD(0x03C4, 0x007C, 1, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_COL__AUDMUX_AUD4_TXC                     = IOMUX_PAD(0x03C4, 0x007C, 2, 0x0654, 1, 0),
+	 MX6_PAD_ENET1_COL__UART1_RI_B                          = IOMUX_PAD(0x03C4, 0x007C, 3, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_COL__SPDIF_EXT_CLK                       = IOMUX_PAD(0x03C4, 0x007C, 4, 0x0828, 1, 0),
+	 MX6_PAD_ENET1_COL__GPIO2_IO_0                          = IOMUX_PAD(0x03C4, 0x007C, 5, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_COL__CSI2_DATA_23                        = IOMUX_PAD(0x03C4, 0x007C, 6, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_COL__LCDIF2_DATA_16                      = IOMUX_PAD(0x03C4, 0x007C, 7, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_COL__VDEC_DEBUG_37                       = IOMUX_PAD(0x03C4, 0x007C, 8, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31                  = IOMUX_PAD(0x03C4, 0x007C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_ENET1_CRS__ENET1_CRS                           = IOMUX_PAD(0x03C8, 0x0080, 0, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_CRS__ENET2_MDIO                          = IOMUX_PAD(0x03C8, 0x0080, 1, 0x0770, 1, 0),
+	 MX6_PAD_ENET1_CRS__AUDMUX_AUD4_TXD                     = IOMUX_PAD(0x03C8, 0x0080, 2, 0x0648, 1, 0),
+	 MX6_PAD_ENET1_CRS__UART1_DCD_B                         = IOMUX_PAD(0x03C8, 0x0080, 3, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_CRS__SPDIF_LOCK                          = IOMUX_PAD(0x03C8, 0x0080, 4, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_CRS__GPIO2_IO_1                          = IOMUX_PAD(0x03C8, 0x0080, 5, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_CRS__CSI2_DATA_22                        = IOMUX_PAD(0x03C8, 0x0080, 6, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_CRS__LCDIF2_DATA_17                      = IOMUX_PAD(0x03C8, 0x0080, 7, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_CRS__VDEC_DEBUG_36                       = IOMUX_PAD(0x03C8, 0x0080, 8, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30                  = IOMUX_PAD(0x03C8, 0x0080, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_ENET1_MDC__ENET1_MDC                           = IOMUX_PAD(0x03CC, 0x0084, 0, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_MDC__ENET2_MDC                           = IOMUX_PAD(0x03CC, 0x0084, 1, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS                    = IOMUX_PAD(0x03CC, 0x0084, 2, 0x0638, 1, 0),
+	 MX6_PAD_ENET1_MDC__ANATOP_24M_OUT                      = IOMUX_PAD(0x03CC, 0x0084, 3, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_MDC__EPIT2_OUT                           = IOMUX_PAD(0x03CC, 0x0084, 4, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_MDC__GPIO2_IO_2                          = IOMUX_PAD(0x03CC, 0x0084, 5, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_MDC__USB_OTG1_PWR                        = IOMUX_PAD(0x03CC, 0x0084, 6, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_MDC__PWM7_OUT                            = IOMUX_PAD(0x03CC, 0x0084, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_ENET1_MDIO__ENET1_MDIO                         = IOMUX_PAD(0x03D0, 0x0088, 0, 0x0764, 1, 0),
+	 MX6_PAD_ENET1_MDIO__ENET2_MDIO                         = IOMUX_PAD(0x03D0, 0x0088, 1, 0x0770, 2, 0),
+	 MX6_PAD_ENET1_MDIO__AUDMUX_MCLK                        = IOMUX_PAD(0x03D0, 0x0088, 2, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_MDIO__OSC32K_32K_OUT                     = IOMUX_PAD(0x03D0, 0x0088, 3, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_MDIO__EPIT1_OUT                          = IOMUX_PAD(0x03D0, 0x0088, 4, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_MDIO__GPIO2_IO_3                         = IOMUX_PAD(0x03D0, 0x0088, 5, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_MDIO__USB_OTG1_OC                        = IOMUX_PAD(0x03D0, 0x0088, 6, 0x0860, 1, 0),
+	 MX6_PAD_ENET1_MDIO__PWM8_OUT                           = IOMUX_PAD(0x03D0, 0x0088, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_ENET1_RX_CLK__ENET1_RX_CLK                     = IOMUX_PAD(0x03D4, 0x008C, 0, 0x0768, 0, 0),
+	 MX6_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M                = IOMUX_PAD(0x03D4, 0x008C, 1, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS                 = IOMUX_PAD(0x03D4, 0x008C, 2, 0x0658, 1, 0),
+	 MX6_PAD_ENET1_RX_CLK__UART1_DSR_B                      = IOMUX_PAD(0x03D4, 0x008C, 3, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_RX_CLK__SPDIF_OUT                        = IOMUX_PAD(0x03D4, 0x008C, 4, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_RX_CLK__GPIO2_IO_4                       = IOMUX_PAD(0x03D4, 0x008C, 5, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_RX_CLK__CSI2_DATA_21                     = IOMUX_PAD(0x03D4, 0x008C, 6, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_RX_CLK__LCDIF2_DATA_18                   = IOMUX_PAD(0x03D4, 0x008C, 7, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_RX_CLK__VDEC_DEBUG_35                    = IOMUX_PAD(0x03D4, 0x008C, 8, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29               = IOMUX_PAD(0x03D4, 0x008C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK                     = IOMUX_PAD(0x03D8, 0x0090, 0, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1                   = IOMUX_PAD(0x03D8, 0x0090, 1, 0x0760, 1, 0),
+	 MX6_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD                  = IOMUX_PAD(0x03D8, 0x0090, 2, 0x0644, 1, 0),
+	 MX6_PAD_ENET1_TX_CLK__UART1_DTR_B                      = IOMUX_PAD(0x03D8, 0x0090, 3, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_TX_CLK__SPDIF_SR_CLK                     = IOMUX_PAD(0x03D8, 0x0090, 4, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_TX_CLK__GPIO2_IO_5                       = IOMUX_PAD(0x03D8, 0x0090, 5, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_TX_CLK__CSI2_DATA_20                     = IOMUX_PAD(0x03D8, 0x0090, 6, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_TX_CLK__LCDIF2_DATA_19                   = IOMUX_PAD(0x03D8, 0x0090, 7, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_TX_CLK__VDEC_DEBUG_34                    = IOMUX_PAD(0x03D8, 0x0090, 8, 0x0000, 0, 0),
+	 MX6_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28               = IOMUX_PAD(0x03D8, 0x0090, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_ENET2_COL__ENET2_COL                           = IOMUX_PAD(0x03DC, 0x0094, 0, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_COL__ENET1_MDC                           = IOMUX_PAD(0x03DC, 0x0094, 1, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_COL__AUDMUX_AUD4_RXC                     = IOMUX_PAD(0x03DC, 0x0094, 2, 0x064C, 1, 0),
+	 MX6_PAD_ENET2_COL__UART1_RX                            = IOMUX_PAD(0x03DC, 0x0094, 3, 0x0830, 2, 0),
+	 MX6_PAD_ENET2_COL__SPDIF_IN                            = IOMUX_PAD(0x03DC, 0x0094, 4, 0x0824, 3, 0),
+	 MX6_PAD_ENET2_COL__GPIO2_IO_6                          = IOMUX_PAD(0x03DC, 0x0094, 5, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_COL__ANATOP_OTG1_ID                      = IOMUX_PAD(0x03DC, 0x0094, 6, 0x0624, 1, 0),
+	 MX6_PAD_ENET2_COL__LCDIF2_DATA_20                      = IOMUX_PAD(0x03DC, 0x0094, 7, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_COL__VDEC_DEBUG_33                       = IOMUX_PAD(0x03DC, 0x0094, 8, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27                  = IOMUX_PAD(0x03DC, 0x0094, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_ENET2_CRS__ENET2_CRS                           = IOMUX_PAD(0x03E0, 0x0098, 0, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_CRS__ENET1_MDIO                          = IOMUX_PAD(0x03E0, 0x0098, 1, 0x0764, 2, 0),
+	 MX6_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS                    = IOMUX_PAD(0x03E0, 0x0098, 2, 0x0650, 1, 0),
+	 MX6_PAD_ENET2_CRS__UART1_TX                            = IOMUX_PAD(0x03E0, 0x0098, 3, 0x0830, 3, 0),
+	 MX6_PAD_ENET2_CRS__MLB_SIG                             = IOMUX_PAD(0x03E0, 0x0098, 4, 0x07F0, 1, 0),
+	 MX6_PAD_ENET2_CRS__GPIO2_IO_7                          = IOMUX_PAD(0x03E0, 0x0098, 5, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_CRS__ANATOP_OTG2_ID                      = IOMUX_PAD(0x03E0, 0x0098, 6, 0x0628, 1, 0),
+	 MX6_PAD_ENET2_CRS__LCDIF2_DATA_21                      = IOMUX_PAD(0x03E0, 0x0098, 7, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_CRS__VDEC_DEBUG_32                       = IOMUX_PAD(0x03E0, 0x0098, 8, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26                  = IOMUX_PAD(0x03E0, 0x0098, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_ENET2_RX_CLK__ENET2_RX_CLK                     = IOMUX_PAD(0x03E4, 0x009C, 0, 0x0774, 0, 0),
+	 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M                = IOMUX_PAD(0x03E4, 0x009C, 1, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_RX_CLK__I2C3_SCL                         = IOMUX_PAD(0x03E4, 0x009C, IOMUX_CONFIG_SION | 2, 0x07B8, 1, 0),
+	 MX6_PAD_ENET2_RX_CLK__UART1_RTS_B                      = IOMUX_PAD(0x03E4, 0x009C, 3, 0x082C, 2, 0),
+	 MX6_PAD_ENET2_RX_CLK__MLB_DATA                         = IOMUX_PAD(0x03E4, 0x009C, 4, 0x07EC, 1, 0),
+	 MX6_PAD_ENET2_RX_CLK__GPIO2_IO_8                       = IOMUX_PAD(0x03E4, 0x009C, 5, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_RX_CLK__USB_OTG2_OC                      = IOMUX_PAD(0x03E4, 0x009C, 6, 0x085C, 1, 0),
+	 MX6_PAD_ENET2_RX_CLK__LCDIF2_DATA_22                   = IOMUX_PAD(0x03E4, 0x009C, 7, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_RX_CLK__VDEC_DEBUG_31                    = IOMUX_PAD(0x03E4, 0x009C, 8, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25               = IOMUX_PAD(0x03E4, 0x009C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK                     = IOMUX_PAD(0x03E8, 0x00A0, 0, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2                   = IOMUX_PAD(0x03E8, 0x00A0, 1, 0x076C, 1, 0),
+	 MX6_PAD_ENET2_TX_CLK__I2C3_SDA                         = IOMUX_PAD(0x03E8, 0x00A0, IOMUX_CONFIG_SION | 2, 0x07BC, 1, 0),
+	 MX6_PAD_ENET2_TX_CLK__UART1_CTS_B                      = IOMUX_PAD(0x03E8, 0x00A0, 3, 0x082C, 3, 0),
+	 MX6_PAD_ENET2_TX_CLK__MLB_CLK                          = IOMUX_PAD(0x03E8, 0x00A0, 4, 0x07E8, 1, 0),
+	 MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9                       = IOMUX_PAD(0x03E8, 0x00A0, 5, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_TX_CLK__USB_OTG2_PWR                     = IOMUX_PAD(0x03E8, 0x00A0, 6, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_TX_CLK__LCDIF2_DATA_23                   = IOMUX_PAD(0x03E8, 0x00A0, 7, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_TX_CLK__VDEC_DEBUG_30                    = IOMUX_PAD(0x03E8, 0x00A0, 8, 0x0000, 0, 0),
+	 MX6_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24               = IOMUX_PAD(0x03E8, 0x00A0, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_KEY_COL0__KPP_COL_0                            = IOMUX_PAD(0x03EC, 0x00A4, 0, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL0__USDHC3_CD_B                          = IOMUX_PAD(0x03EC, 0x00A4, 1, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL0__UART6_RTS_B                          = IOMUX_PAD(0x03EC, 0x00A4, 2, 0x0854, 2, 0),
+	 MX6_PAD_KEY_COL0__ECSPI1_SCLK                          = IOMUX_PAD(0x03EC, 0x00A4, 3, 0x0710, 0, 0),
+	 MX6_PAD_KEY_COL0__AUDMUX_AUD5_TXC                      = IOMUX_PAD(0x03EC, 0x00A4, 4, 0x066C, 0, 0),
+	 MX6_PAD_KEY_COL0__GPIO2_IO_10                          = IOMUX_PAD(0x03EC, 0x00A4, 5, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL0__SDMA_EXT_EVENT_1                     = IOMUX_PAD(0x03EC, 0x00A4, 6, 0x0820, 1, 0),
+	 MX6_PAD_KEY_COL0__SAI2_TX_BCLK                         = IOMUX_PAD(0x03EC, 0x00A4, 7, 0x0814, 0, 0),
+	 MX6_PAD_KEY_COL0__VADC_DATA_0                          = IOMUX_PAD(0x03EC, 0x00A4, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_KEY_COL1__KPP_COL_1                            = IOMUX_PAD(0x03F0, 0x00A8, 0, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL1__USDHC3_RESET_B                       = IOMUX_PAD(0x03F0, 0x00A8, 1, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL1__UART6_TX                             = IOMUX_PAD(0x03F0, 0x00A8, 2, 0x0858, 2, 0),
+	 MX6_PAD_KEY_COL1__ECSPI1_MISO                          = IOMUX_PAD(0x03F0, 0x00A8, 3, 0x0714, 0, 0),
+	 MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS                     = IOMUX_PAD(0x03F0, 0x00A8, 4, 0x0670, 0, 0),
+	 MX6_PAD_KEY_COL1__GPIO2_IO_11                          = IOMUX_PAD(0x03F0, 0x00A8, 5, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL1__USDHC3_RESET                         = IOMUX_PAD(0x03F0, 0x00A8, 6, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL1__SAI2_TX_SYNC                         = IOMUX_PAD(0x03F0, 0x00A8, 7, 0x0818, 0, 0),
+
+	 MX6_PAD_KEY_COL2__KPP_COL_2                            = IOMUX_PAD(0x03F4, 0x00AC, 0, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL2__USDHC4_CD_B                          = IOMUX_PAD(0x03F4, 0x00AC, 1, 0x0874, 1, 0),
+	 MX6_PAD_KEY_COL2__UART5_RTS_B                          = IOMUX_PAD(0x03F4, 0x00AC, 2, 0x084C, 2, 0),
+	 MX6_PAD_KEY_COL2__CAN1_TX                              = IOMUX_PAD(0x03F4, 0x00AC, 3, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL2__CANFD_TX1                            = IOMUX_PAD(0x03F4, 0x00AC, 4, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL2__GPIO2_IO_12                          = IOMUX_PAD(0x03F4, 0x00AC, 5, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL2__WEIM_DATA_30                         = IOMUX_PAD(0x03F4, 0x00AC, 6, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL2__ECSPI1_RDY                           = IOMUX_PAD(0x03F4, 0x00AC, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_KEY_COL3__KPP_COL_3                            = IOMUX_PAD(0x03F8, 0x00B0, 0, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL3__USDHC4_LCTL                          = IOMUX_PAD(0x03F8, 0x00B0, 1, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL3__UART5_TX                             = IOMUX_PAD(0x03F8, 0x00B0, 2, 0x0850, 2, 0),
+	 MX6_PAD_KEY_COL3__CAN2_TX                              = IOMUX_PAD(0x03F8, 0x00B0, 3, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL3__CANFD_TX2                            = IOMUX_PAD(0x03F8, 0x00B0, 4, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL3__GPIO2_IO_13                          = IOMUX_PAD(0x03F8, 0x00B0, 5, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL3__WEIM_DATA_28                         = IOMUX_PAD(0x03F8, 0x00B0, 6, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL3__ECSPI1_SS2                           = IOMUX_PAD(0x03F8, 0x00B0, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_KEY_COL4__KPP_COL_4                            = IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL4__ENET2_MDC                            = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL4__I2C3_SCL                             = IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0),
+	 MX6_PAD_KEY_COL4__USDHC2_LCTL                          = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC                      = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0),
+	 MX6_PAD_KEY_COL4__GPIO2_IO_14                          = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL4__WEIM_CRE                             = IOMUX_PAD(0x03FC, 0x00B4, 6, 0x0000, 0, 0),
+	 MX6_PAD_KEY_COL4__SAI2_RX_BCLK                         = IOMUX_PAD(0x03FC, 0x00B4, 7, 0x0808, 0, 0),
+
+	 MX6_PAD_KEY_ROW0__KPP_ROW_0                            = IOMUX_PAD(0x0400, 0x00B8, 0, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW0__USDHC3_WP                            = IOMUX_PAD(0x0400, 0x00B8, 1, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW0__UART6_CTS_B                          = IOMUX_PAD(0x0400, 0x00B8, 2, 0x0854, 3, 0),
+	 MX6_PAD_KEY_ROW0__ECSPI1_MOSI                          = IOMUX_PAD(0x0400, 0x00B8, 3, 0x0718, 0, 0),
+	 MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD                      = IOMUX_PAD(0x0400, 0x00B8, 4, 0x0660, 0, 0),
+	 MX6_PAD_KEY_ROW0__GPIO2_IO_15                          = IOMUX_PAD(0x0400, 0x00B8, 5, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW0__SDMA_EXT_EVENT_0                     = IOMUX_PAD(0x0400, 0x00B8, 6, 0x081C, 1, 0),
+	 MX6_PAD_KEY_ROW0__SAI2_TX_DATA_0                       = IOMUX_PAD(0x0400, 0x00B8, 7, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW0__GPU_IDLE                             = IOMUX_PAD(0x0400, 0x00B8, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_KEY_ROW1__KPP_ROW_1                            = IOMUX_PAD(0x0404, 0x00BC, 0, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW1__USDHC4_VSELECT                       = IOMUX_PAD(0x0404, 0x00BC, 1, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW1__UART6_RX                             = IOMUX_PAD(0x0404, 0x00BC, 2, 0x0858, 3, 0),
+	 MX6_PAD_KEY_ROW1__ECSPI1_SS0                           = IOMUX_PAD(0x0404, 0x00BC, 3, 0x071C, 0, 0),
+	 MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD                      = IOMUX_PAD(0x0404, 0x00BC, 4, 0x065C, 0, 0),
+	 MX6_PAD_KEY_ROW1__GPIO2_IO_16                          = IOMUX_PAD(0x0404, 0x00BC, 5, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW1__WEIM_DATA_31                         = IOMUX_PAD(0x0404, 0x00BC, 6, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW1__SAI2_RX_DATA_0                       = IOMUX_PAD(0x0404, 0x00BC, 7, 0x080C, 0, 0),
+	 MX6_PAD_KEY_ROW1__M4_NMI                               = IOMUX_PAD(0x0404, 0x00BC, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_KEY_ROW2__KPP_ROW_2                            = IOMUX_PAD(0x0408, 0x00C0, 0, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW2__USDHC4_WP                            = IOMUX_PAD(0x0408, 0x00C0, 1, 0x0878, 1, 0),
+	 MX6_PAD_KEY_ROW2__UART5_CTS_B                          = IOMUX_PAD(0x0408, 0x00C0, 2, 0x084C, 3, 0),
+	 MX6_PAD_KEY_ROW2__CAN1_RX                              = IOMUX_PAD(0x0408, 0x00C0, 3, 0x068C, 1, 0),
+	 MX6_PAD_KEY_ROW2__CANFD_RX1                            = IOMUX_PAD(0x0408, 0x00C0, 4, 0x0694, 1, 0),
+	 MX6_PAD_KEY_ROW2__GPIO2_IO_17                          = IOMUX_PAD(0x0408, 0x00C0, 5, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW2__WEIM_DATA_29                         = IOMUX_PAD(0x0408, 0x00C0, 6, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW2__ECSPI1_SS3                           = IOMUX_PAD(0x0408, 0x00C0, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_KEY_ROW3__KPP_ROW_3                            = IOMUX_PAD(0x040C, 0x00C4, 0, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW3__USDHC3_LCTL                          = IOMUX_PAD(0x040C, 0x00C4, 1, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW3__UART5_RX                             = IOMUX_PAD(0x040C, 0x00C4, 2, 0x0850, 3, 0),
+	 MX6_PAD_KEY_ROW3__CAN2_RX                              = IOMUX_PAD(0x040C, 0x00C4, 3, 0x0690, 1, 0),
+	 MX6_PAD_KEY_ROW3__CANFD_RX2                            = IOMUX_PAD(0x040C, 0x00C4, 4, 0x0698, 1, 0),
+	 MX6_PAD_KEY_ROW3__GPIO2_IO_18                          = IOMUX_PAD(0x040C, 0x00C4, 5, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW3__WEIM_DTACK_B                         = IOMUX_PAD(0x040C, 0x00C4, 6, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW3__ECSPI1_SS1                           = IOMUX_PAD(0x040C, 0x00C4, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_KEY_ROW4__KPP_ROW_4                            = IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW4__ENET2_MDIO                           = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0),
+	 MX6_PAD_KEY_ROW4__I2C3_SDA                             = IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0),
+	 MX6_PAD_KEY_ROW4__USDHC1_LCTL                          = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS                     = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0),
+	 MX6_PAD_KEY_ROW4__GPIO2_IO_19                          = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW4__WEIM_ACLK_FREERUN                    = IOMUX_PAD(0x0410, 0x00C8, 6, 0x0000, 0, 0),
+	 MX6_PAD_KEY_ROW4__SAI2_RX_SYNC                         = IOMUX_PAD(0x0410, 0x00C8, 7, 0x0810, 0, 0),
+
+	 MX6_PAD_LCD1_CLK__LCDIF1_CLK                           = IOMUX_PAD(0x0414, 0x00CC, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_CLK__LCDIF1_WR_RWN                        = IOMUX_PAD(0x0414, 0x00CC, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_CLK__AUDMUX_AUD3_RXC                      = IOMUX_PAD(0x0414, 0x00CC, 2, 0x0634, 1, 0),
+	 MX6_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN                 = IOMUX_PAD(0x0414, 0x00CC, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_CLK__CSI1_DATA_16                         = IOMUX_PAD(0x0414, 0x00CC, 4, 0x06DC, 0, 0),
+	 MX6_PAD_LCD1_CLK__GPIO3_IO_0                           = IOMUX_PAD(0x0414, 0x00CC, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_CLK__USDHC1_WP                            = IOMUX_PAD(0x0414, 0x00CC, 6, 0x0868, 0, 0),
+	 MX6_PAD_LCD1_CLK__SIM_M_HADDR_16                       = IOMUX_PAD(0x0414, 0x00CC, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_CLK__VADC_TEST_0                          = IOMUX_PAD(0x0414, 0x00CC, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_CLK__MMDC_DEBUG_0                         = IOMUX_PAD(0x0414, 0x00CC, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0                     = IOMUX_PAD(0x0418, 0x00D0, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA00__WEIM_CS1_B                        = IOMUX_PAD(0x0418, 0x00D0, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA00__M4_TRACE_0                        = IOMUX_PAD(0x0418, 0x00D0, 2, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA00__KITTEN_TRACE_0                    = IOMUX_PAD(0x0418, 0x00D0, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA00__CSI1_DATA_20                      = IOMUX_PAD(0x0418, 0x00D0, 4, 0x06EC, 0, 0),
+	 MX6_PAD_LCD1_DATA00__GPIO3_IO_1                        = IOMUX_PAD(0x0418, 0x00D0, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA00__SRC_BT_CFG_0                      = IOMUX_PAD(0x0418, 0x00D0, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA00__SIM_M_HADDR_21                    = IOMUX_PAD(0x0418, 0x00D0, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA00__VADC_TEST_5                       = IOMUX_PAD(0x0418, 0x00D0, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA00__MMDC_DEBUG_5                      = IOMUX_PAD(0x0418, 0x00D0, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1                     = IOMUX_PAD(0x041C, 0x00D4, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA01__WEIM_CS2_B                        = IOMUX_PAD(0x041C, 0x00D4, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA01__M4_TRACE_1                        = IOMUX_PAD(0x041C, 0x00D4, 2, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA01__KITTEN_TRACE_1                    = IOMUX_PAD(0x041C, 0x00D4, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA01__CSI1_DATA_21                      = IOMUX_PAD(0x041C, 0x00D4, 4, 0x06F0, 0, 0),
+	 MX6_PAD_LCD1_DATA01__GPIO3_IO_2                        = IOMUX_PAD(0x041C, 0x00D4, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA01__SRC_BT_CFG_1                      = IOMUX_PAD(0x041C, 0x00D4, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA01__SIM_M_HADDR_22                    = IOMUX_PAD(0x041C, 0x00D4, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA01__VADC_TEST_6                       = IOMUX_PAD(0x041C, 0x00D4, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA01__MMDC_DEBUG_6                      = IOMUX_PAD(0x041C, 0x00D4, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2                     = IOMUX_PAD(0x0420, 0x00D8, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA02__WEIM_CS3_B                        = IOMUX_PAD(0x0420, 0x00D8, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA02__M4_TRACE_2                        = IOMUX_PAD(0x0420, 0x00D8, 2, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA02__KITTEN_TRACE_2                    = IOMUX_PAD(0x0420, 0x00D8, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA02__CSI1_DATA_22                      = IOMUX_PAD(0x0420, 0x00D8, 4, 0x06F4, 0, 0),
+	 MX6_PAD_LCD1_DATA02__GPIO3_IO_3                        = IOMUX_PAD(0x0420, 0x00D8, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA02__SRC_BT_CFG_2                      = IOMUX_PAD(0x0420, 0x00D8, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA02__SIM_M_HADDR_23                    = IOMUX_PAD(0x0420, 0x00D8, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA02__VADC_TEST_7                       = IOMUX_PAD(0x0420, 0x00D8, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA02__MMDC_DEBUG_7                      = IOMUX_PAD(0x0420, 0x00D8, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3                     = IOMUX_PAD(0x0424, 0x00DC, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA03__WEIM_ADDR_24                      = IOMUX_PAD(0x0424, 0x00DC, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA03__M4_TRACE_3                        = IOMUX_PAD(0x0424, 0x00DC, 2, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA03__KITTEN_TRACE_3                    = IOMUX_PAD(0x0424, 0x00DC, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA03__CSI1_DATA_23                      = IOMUX_PAD(0x0424, 0x00DC, 4, 0x06F8, 0, 0),
+	 MX6_PAD_LCD1_DATA03__GPIO3_IO_4                        = IOMUX_PAD(0x0424, 0x00DC, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA03__SRC_BT_CFG_3                      = IOMUX_PAD(0x0424, 0x00DC, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA03__SIM_M_HADDR_24                    = IOMUX_PAD(0x0424, 0x00DC, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA03__VADC_TEST_8                       = IOMUX_PAD(0x0424, 0x00DC, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA03__MMDC_DEBUG_8                      = IOMUX_PAD(0x0424, 0x00DC, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4                     = IOMUX_PAD(0x0428, 0x00E0, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA04__WEIM_ADDR_25                      = IOMUX_PAD(0x0428, 0x00E0, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA04__KITTEN_TRACE_4                    = IOMUX_PAD(0x0428, 0x00E0, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA04__CSI1_VSYNC                        = IOMUX_PAD(0x0428, 0x00E0, 4, 0x0708, 1, 0),
+	 MX6_PAD_LCD1_DATA04__GPIO3_IO_5                        = IOMUX_PAD(0x0428, 0x00E0, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA04__SRC_BT_CFG_4                      = IOMUX_PAD(0x0428, 0x00E0, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA04__SIM_M_HADDR_25                    = IOMUX_PAD(0x0428, 0x00E0, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA04__VADC_TEST_9                       = IOMUX_PAD(0x0428, 0x00E0, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA04__MMDC_DEBUG_9                      = IOMUX_PAD(0x0428, 0x00E0, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5                     = IOMUX_PAD(0x042C, 0x00E4, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA05__WEIM_ADDR_26                      = IOMUX_PAD(0x042C, 0x00E4, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA05__KITTEN_TRACE_5                    = IOMUX_PAD(0x042C, 0x00E4, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA05__CSI1_HSYNC                        = IOMUX_PAD(0x042C, 0x00E4, 4, 0x0700, 1, 0),
+	 MX6_PAD_LCD1_DATA05__GPIO3_IO_6                        = IOMUX_PAD(0x042C, 0x00E4, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA05__SRC_BT_CFG_5                      = IOMUX_PAD(0x042C, 0x00E4, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA05__SIM_M_HADDR_26                    = IOMUX_PAD(0x042C, 0x00E4, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA05__VADC_TEST_10                      = IOMUX_PAD(0x042C, 0x00E4, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA05__MMDC_DEBUG_10                     = IOMUX_PAD(0x042C, 0x00E4, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6                     = IOMUX_PAD(0x0430, 0x00E8, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA06__WEIM_EB_B_2                       = IOMUX_PAD(0x0430, 0x00E8, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA06__KITTEN_TRACE_6                    = IOMUX_PAD(0x0430, 0x00E8, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA06__CSI1_PIXCLK                       = IOMUX_PAD(0x0430, 0x00E8, 4, 0x0704, 1, 0),
+	 MX6_PAD_LCD1_DATA06__GPIO3_IO_7                        = IOMUX_PAD(0x0430, 0x00E8, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA06__SRC_BT_CFG_6                      = IOMUX_PAD(0x0430, 0x00E8, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA06__SIM_M_HADDR_27                    = IOMUX_PAD(0x0430, 0x00E8, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA06__VADC_TEST_11                      = IOMUX_PAD(0x0430, 0x00E8, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA06__MMDC_DEBUG_11                     = IOMUX_PAD(0x0430, 0x00E8, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7                     = IOMUX_PAD(0x0434, 0x00EC, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA07__WEIM_EB_B_3                       = IOMUX_PAD(0x0434, 0x00EC, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA07__KITTEN_TRACE_7                    = IOMUX_PAD(0x0434, 0x00EC, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA07__CSI1_MCLK                         = IOMUX_PAD(0x0434, 0x00EC, 4, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA07__GPIO3_IO_8                        = IOMUX_PAD(0x0434, 0x00EC, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA07__SRC_BT_CFG_7                      = IOMUX_PAD(0x0434, 0x00EC, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA07__SIM_M_HADDR_28                    = IOMUX_PAD(0x0434, 0x00EC, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA07__VADC_TEST_12                      = IOMUX_PAD(0x0434, 0x00EC, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA07__MMDC_DEBUG_12                     = IOMUX_PAD(0x0434, 0x00EC, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8                     = IOMUX_PAD(0x0438, 0x00F0, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA08__WEIM_AD_8                         = IOMUX_PAD(0x0438, 0x00F0, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA08__KITTEN_TRACE_8                    = IOMUX_PAD(0x0438, 0x00F0, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA08__CSI1_DATA_9                       = IOMUX_PAD(0x0438, 0x00F0, 4, 0x06C4, 1, 0),
+	 MX6_PAD_LCD1_DATA08__GPIO3_IO_9                        = IOMUX_PAD(0x0438, 0x00F0, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA08__SRC_BT_CFG_8                      = IOMUX_PAD(0x0438, 0x00F0, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA08__SIM_M_HADDR_29                    = IOMUX_PAD(0x0438, 0x00F0, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA08__VADC_TEST_13                      = IOMUX_PAD(0x0438, 0x00F0, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA08__MMDC_DEBUG_13                     = IOMUX_PAD(0x0438, 0x00F0, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9                     = IOMUX_PAD(0x043C, 0x00F4, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA09__WEIM_AD_9                         = IOMUX_PAD(0x043C, 0x00F4, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA09__KITTEN_TRACE_9                    = IOMUX_PAD(0x043C, 0x00F4, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA09__CSI1_DATA_8                       = IOMUX_PAD(0x043C, 0x00F4, 4, 0x06C0, 1, 0),
+	 MX6_PAD_LCD1_DATA09__GPIO3_IO_10                       = IOMUX_PAD(0x043C, 0x00F4, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA09__SRC_BT_CFG_9                      = IOMUX_PAD(0x043C, 0x00F4, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA09__SIM_M_HADDR_30                    = IOMUX_PAD(0x043C, 0x00F4, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA09__VADC_TEST_14                      = IOMUX_PAD(0x043C, 0x00F4, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA09__MMDC_DEBUG_14                     = IOMUX_PAD(0x043C, 0x00F4, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10                    = IOMUX_PAD(0x0440, 0x00F8, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA10__WEIM_AD_10                        = IOMUX_PAD(0x0440, 0x00F8, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA10__KITTEN_TRACE_10                   = IOMUX_PAD(0x0440, 0x00F8, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA10__CSI1_DATA_7                       = IOMUX_PAD(0x0440, 0x00F8, 4, 0x06BC, 1, 0),
+	 MX6_PAD_LCD1_DATA10__GPIO3_IO_11                       = IOMUX_PAD(0x0440, 0x00F8, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA10__SRC_BT_CFG_10                     = IOMUX_PAD(0x0440, 0x00F8, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA10__SIM_M_HADDR_31                    = IOMUX_PAD(0x0440, 0x00F8, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA10__VADC_TEST_15                      = IOMUX_PAD(0x0440, 0x00F8, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA10__MMDC_DEBUG_15                     = IOMUX_PAD(0x0440, 0x00F8, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11                    = IOMUX_PAD(0x0444, 0x00FC, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA11__WEIM_AD_11                        = IOMUX_PAD(0x0444, 0x00FC, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA11__KITTEN_TRACE_11                   = IOMUX_PAD(0x0444, 0x00FC, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA11__CSI1_DATA_6                       = IOMUX_PAD(0x0444, 0x00FC, 4, 0x06B8, 1, 0),
+	 MX6_PAD_LCD1_DATA11__GPIO3_IO_12                       = IOMUX_PAD(0x0444, 0x00FC, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA11__SRC_BT_CFG_11                     = IOMUX_PAD(0x0444, 0x00FC, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA11__SIM_M_HBURST_0                    = IOMUX_PAD(0x0444, 0x00FC, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA11__VADC_TEST_16                      = IOMUX_PAD(0x0444, 0x00FC, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA11__MMDC_DEBUG_16                     = IOMUX_PAD(0x0444, 0x00FC, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12                    = IOMUX_PAD(0x0448, 0x0100, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA12__WEIM_AD_12                        = IOMUX_PAD(0x0448, 0x0100, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA12__KITTEN_TRACE_12                   = IOMUX_PAD(0x0448, 0x0100, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA12__CSI1_DATA_5                       = IOMUX_PAD(0x0448, 0x0100, 4, 0x06B4, 1, 0),
+	 MX6_PAD_LCD1_DATA12__GPIO3_IO_13                       = IOMUX_PAD(0x0448, 0x0100, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA12__SRC_BT_CFG_12                     = IOMUX_PAD(0x0448, 0x0100, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA12__SIM_M_HBURST_1                    = IOMUX_PAD(0x0448, 0x0100, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA12__VADC_TEST_17                      = IOMUX_PAD(0x0448, 0x0100, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA12__MMDC_DEBUG_17                     = IOMUX_PAD(0x0448, 0x0100, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13                    = IOMUX_PAD(0x044C, 0x0104, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA13__WEIM_AD_13                        = IOMUX_PAD(0x044C, 0x0104, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA13__KITTEN_TRACE_13                   = IOMUX_PAD(0x044C, 0x0104, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA13__CSI1_DATA_4                       = IOMUX_PAD(0x044C, 0x0104, 4, 0x06B0, 1, 0),
+	 MX6_PAD_LCD1_DATA13__GPIO3_IO_14                       = IOMUX_PAD(0x044C, 0x0104, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA13__SRC_BT_CFG_13                     = IOMUX_PAD(0x044C, 0x0104, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA13__SIM_M_HBURST_2                    = IOMUX_PAD(0x044C, 0x0104, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA13__VADC_TEST_18                      = IOMUX_PAD(0x044C, 0x0104, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA13__MMDC_DEBUG_18                     = IOMUX_PAD(0x044C, 0x0104, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14                    = IOMUX_PAD(0x0450, 0x0108, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA14__WEIM_AD_14                        = IOMUX_PAD(0x0450, 0x0108, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA14__KITTEN_TRACE_14                   = IOMUX_PAD(0x0450, 0x0108, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA14__CSI1_DATA_3                       = IOMUX_PAD(0x0450, 0x0108, 4, 0x06AC, 1, 0),
+	 MX6_PAD_LCD1_DATA14__GPIO3_IO_15                       = IOMUX_PAD(0x0450, 0x0108, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA14__SRC_BT_CFG_14                     = IOMUX_PAD(0x0450, 0x0108, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA14__SIM_M_HMASTLOCK                   = IOMUX_PAD(0x0450, 0x0108, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA14__VADC_TEST_19                      = IOMUX_PAD(0x0450, 0x0108, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA14__MMDC_DEBUG_19                     = IOMUX_PAD(0x0450, 0x0108, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15                    = IOMUX_PAD(0x0454, 0x010C, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA15__WEIM_AD_15                        = IOMUX_PAD(0x0454, 0x010C, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA15__KITTEN_TRACE_15                   = IOMUX_PAD(0x0454, 0x010C, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA15__CSI1_DATA_2                       = IOMUX_PAD(0x0454, 0x010C, 4, 0x06A8, 1, 0),
+	 MX6_PAD_LCD1_DATA15__GPIO3_IO_16                       = IOMUX_PAD(0x0454, 0x010C, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA15__SRC_BT_CFG_15                     = IOMUX_PAD(0x0454, 0x010C, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA15__SIM_M_HPROT_0                     = IOMUX_PAD(0x0454, 0x010C, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA15__VDEC_DEBUG_0                      = IOMUX_PAD(0x0454, 0x010C, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA15__MMDC_DEBUG_20                     = IOMUX_PAD(0x0454, 0x010C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16                    = IOMUX_PAD(0x0458, 0x0110, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA16__WEIM_ADDR_16                      = IOMUX_PAD(0x0458, 0x0110, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA16__M4_TRACE_CLK                      = IOMUX_PAD(0x0458, 0x0110, 2, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA16__KITTEN_TRACE_CLK                  = IOMUX_PAD(0x0458, 0x0110, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA16__CSI1_DATA_1                       = IOMUX_PAD(0x0458, 0x0110, 4, 0x06A4, 0, 0),
+	 MX6_PAD_LCD1_DATA16__GPIO3_IO_17                       = IOMUX_PAD(0x0458, 0x0110, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA16__SRC_BT_CFG_24                     = IOMUX_PAD(0x0458, 0x0110, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA16__SIM_M_HPROT_1                     = IOMUX_PAD(0x0458, 0x0110, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA16__VDEC_DEBUG_1                      = IOMUX_PAD(0x0458, 0x0110, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA16__MMDC_DEBUG_21                     = IOMUX_PAD(0x0458, 0x0110, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17                    = IOMUX_PAD(0x045C, 0x0114, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA17__WEIM_ADDR_17                      = IOMUX_PAD(0x045C, 0x0114, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA17__KITTEN_TRACE_CTL                  = IOMUX_PAD(0x045C, 0x0114, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA17__CSI1_DATA_0                       = IOMUX_PAD(0x045C, 0x0114, 4, 0x06A0, 0, 0),
+	 MX6_PAD_LCD1_DATA17__GPIO3_IO_18                       = IOMUX_PAD(0x045C, 0x0114, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA17__SRC_BT_CFG_25                     = IOMUX_PAD(0x045C, 0x0114, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA17__SIM_M_HPROT_2                     = IOMUX_PAD(0x045C, 0x0114, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA17__VDEC_DEBUG_2                      = IOMUX_PAD(0x045C, 0x0114, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA17__MMDC_DEBUG_22                     = IOMUX_PAD(0x045C, 0x0114, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18                    = IOMUX_PAD(0x0460, 0x0118, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA18__WEIM_ADDR_18                      = IOMUX_PAD(0x0460, 0x0118, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA18__M4_EVENTO                         = IOMUX_PAD(0x0460, 0x0118, 2, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA18__KITTEN_EVENTO                     = IOMUX_PAD(0x0460, 0x0118, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA18__CSI1_DATA_15                      = IOMUX_PAD(0x0460, 0x0118, 4, 0x06D8, 0, 0),
+	 MX6_PAD_LCD1_DATA18__GPIO3_IO_19                       = IOMUX_PAD(0x0460, 0x0118, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA18__SRC_BT_CFG_26                     = IOMUX_PAD(0x0460, 0x0118, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA18__SIM_M_HPROT_3                     = IOMUX_PAD(0x0460, 0x0118, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA18__VDEC_DEBUG_3                      = IOMUX_PAD(0x0460, 0x0118, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA18__MMDC_DEBUG_23                     = IOMUX_PAD(0x0460, 0x0118, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19                    = IOMUX_PAD(0x0464, 0x011C, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA19__WEIM_ADDR_19                      = IOMUX_PAD(0x0464, 0x011C, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA19__M4_TRACE_SWO                      = IOMUX_PAD(0x0464, 0x011C, 2, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA19__CSI1_DATA_14                      = IOMUX_PAD(0x0464, 0x011C, 4, 0x06D4, 0, 0),
+	 MX6_PAD_LCD1_DATA19__GPIO3_IO_20                       = IOMUX_PAD(0x0464, 0x011C, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA19__SRC_BT_CFG_27                     = IOMUX_PAD(0x0464, 0x011C, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA19__SIM_M_HREADYOUT                   = IOMUX_PAD(0x0464, 0x011C, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA19__VDEC_DEBUG_4                      = IOMUX_PAD(0x0464, 0x011C, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA19__MMDC_DEBUG_24                     = IOMUX_PAD(0x0464, 0x011C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20                    = IOMUX_PAD(0x0468, 0x0120, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA20__WEIM_ADDR_20                      = IOMUX_PAD(0x0468, 0x0120, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA20__PWM8_OUT                          = IOMUX_PAD(0x0468, 0x0120, 2, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT             = IOMUX_PAD(0x0468, 0x0120, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA20__CSI1_DATA_13                      = IOMUX_PAD(0x0468, 0x0120, 4, 0x06D0, 0, 0),
+	 MX6_PAD_LCD1_DATA20__GPIO3_IO_21                       = IOMUX_PAD(0x0468, 0x0120, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA20__SRC_BT_CFG_28                     = IOMUX_PAD(0x0468, 0x0120, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA20__SIM_M_HRESP                       = IOMUX_PAD(0x0468, 0x0120, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA20__VDEC_DEBUG_5                      = IOMUX_PAD(0x0468, 0x0120, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA20__MMDC_DEBUG_25                     = IOMUX_PAD(0x0468, 0x0120, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21                    = IOMUX_PAD(0x046C, 0x0124, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA21__WEIM_ADDR_21                      = IOMUX_PAD(0x046C, 0x0124, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA21__PWM7_OUT                          = IOMUX_PAD(0x046C, 0x0124, 2, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT             = IOMUX_PAD(0x046C, 0x0124, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA21__CSI1_DATA_12                      = IOMUX_PAD(0x046C, 0x0124, 4, 0x06CC, 0, 0),
+	 MX6_PAD_LCD1_DATA21__GPIO3_IO_22                       = IOMUX_PAD(0x046C, 0x0124, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA21__SRC_BT_CFG_29                     = IOMUX_PAD(0x046C, 0x0124, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA21__SIM_M_HSIZE_0                     = IOMUX_PAD(0x046C, 0x0124, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA21__VDEC_DEBUG_6                      = IOMUX_PAD(0x046C, 0x0124, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA21__MMDC_DEBUG_26                     = IOMUX_PAD(0x046C, 0x0124, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22                    = IOMUX_PAD(0x0470, 0x0128, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA22__WEIM_ADDR_22                      = IOMUX_PAD(0x0470, 0x0128, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA22__PWM6_OUT                          = IOMUX_PAD(0x0470, 0x0128, 2, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT             = IOMUX_PAD(0x0470, 0x0128, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA22__CSI1_DATA_11                      = IOMUX_PAD(0x0470, 0x0128, 4, 0x06C8, 0, 0),
+	 MX6_PAD_LCD1_DATA22__GPIO3_IO_23                       = IOMUX_PAD(0x0470, 0x0128, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA22__SRC_BT_CFG_30                     = IOMUX_PAD(0x0470, 0x0128, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA22__SIM_M_HSIZE_1                     = IOMUX_PAD(0x0470, 0x0128, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA22__VDEC_DEBUG_7                      = IOMUX_PAD(0x0470, 0x0128, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA22__MMDC_DEBUG_27                     = IOMUX_PAD(0x0470, 0x0128, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23                    = IOMUX_PAD(0x0474, 0x012C, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA23__WEIM_ADDR_23                      = IOMUX_PAD(0x0474, 0x012C, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA23__PWM5_OUT                          = IOMUX_PAD(0x0474, 0x012C, 2, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT             = IOMUX_PAD(0x0474, 0x012C, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA23__CSI1_DATA_10                      = IOMUX_PAD(0x0474, 0x012C, 4, 0x06FC, 0, 0),
+	 MX6_PAD_LCD1_DATA23__GPIO3_IO_24                       = IOMUX_PAD(0x0474, 0x012C, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA23__SRC_BT_CFG_31                     = IOMUX_PAD(0x0474, 0x012C, 6, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA23__SIM_M_HSIZE_2                     = IOMUX_PAD(0x0474, 0x012C, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA23__VDEC_DEBUG_8                      = IOMUX_PAD(0x0474, 0x012C, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_DATA23__MMDC_DEBUG_28                     = IOMUX_PAD(0x0474, 0x012C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE                     = IOMUX_PAD(0x0478, 0x0130, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_ENABLE__LCDIF1_RD_E                       = IOMUX_PAD(0x0478, 0x0130, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC                   = IOMUX_PAD(0x0478, 0x0130, 2, 0x063C, 1, 0),
+	 MX6_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN              = IOMUX_PAD(0x0478, 0x0130, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_ENABLE__CSI1_DATA_17                      = IOMUX_PAD(0x0478, 0x0130, 4, 0x06E0, 0, 0),
+	 MX6_PAD_LCD1_ENABLE__GPIO3_IO_25                       = IOMUX_PAD(0x0478, 0x0130, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_ENABLE__USDHC1_CD_B                       = IOMUX_PAD(0x0478, 0x0130, 6, 0x0864, 0, 0),
+	 MX6_PAD_LCD1_ENABLE__SIM_M_HADDR_17                    = IOMUX_PAD(0x0478, 0x0130, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_ENABLE__VADC_TEST_1                       = IOMUX_PAD(0x0478, 0x0130, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_ENABLE__MMDC_DEBUG_1                      = IOMUX_PAD(0x0478, 0x0130, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC                       = IOMUX_PAD(0x047C, 0x0134, 0, 0x07E0, 0, 0),
+	 MX6_PAD_LCD1_HSYNC__LCDIF1_RS                          = IOMUX_PAD(0x047C, 0x0134, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD                    = IOMUX_PAD(0x047C, 0x0134, 2, 0x0630, 1, 0),
+	 MX6_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN               = IOMUX_PAD(0x047C, 0x0134, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_HSYNC__CSI1_DATA_18                       = IOMUX_PAD(0x047C, 0x0134, 4, 0x06E4, 0, 0),
+	 MX6_PAD_LCD1_HSYNC__GPIO3_IO_26                        = IOMUX_PAD(0x047C, 0x0134, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_HSYNC__USDHC2_WP                          = IOMUX_PAD(0x047C, 0x0134, 6, 0x0870, 0, 0),
+	 MX6_PAD_LCD1_HSYNC__SIM_M_HADDR_18                     = IOMUX_PAD(0x047C, 0x0134, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_HSYNC__VADC_TEST_2                        = IOMUX_PAD(0x047C, 0x0134, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_HSYNC__MMDC_DEBUG_2                       = IOMUX_PAD(0x047C, 0x0134, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_RESET__LCDIF1_RESET                       = IOMUX_PAD(0x0480, 0x0138, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_RESET__LCDIF1_CS                          = IOMUX_PAD(0x0480, 0x0138, 1, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_RESET__AUDMUX_AUD3_RXD                    = IOMUX_PAD(0x0480, 0x0138, 2, 0x062C, 1, 0),
+	 MX6_PAD_LCD1_RESET__KITTEN_EVENTI                      = IOMUX_PAD(0x0480, 0x0138, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_RESET__M4_EVENTI                          = IOMUX_PAD(0x0480, 0x0138, 4, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_RESET__GPIO3_IO_27                        = IOMUX_PAD(0x0480, 0x0138, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_RESET__CCM_PMIC_RDY                       = IOMUX_PAD(0x0480, 0x0138, 6, 0x069C, 0, 0),
+	 MX6_PAD_LCD1_RESET__SIM_M_HADDR_20                     = IOMUX_PAD(0x0480, 0x0138, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_RESET__VADC_TEST_4                        = IOMUX_PAD(0x0480, 0x0138, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_RESET__MMDC_DEBUG_4                       = IOMUX_PAD(0x0480, 0x0138, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC                       = IOMUX_PAD(0x0484, 0x013C, 0, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_VSYNC__LCDIF1_BUSY                        = IOMUX_PAD(0x0484, 0x013C, 1, 0x07E0, 1, 0),
+	 MX6_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS                   = IOMUX_PAD(0x0484, 0x013C, 2, 0x0640, 1, 0),
+	 MX6_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN               = IOMUX_PAD(0x0484, 0x013C, 3, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_VSYNC__CSI1_DATA_19                       = IOMUX_PAD(0x0484, 0x013C, 4, 0x06E8, 0, 0),
+	 MX6_PAD_LCD1_VSYNC__GPIO3_IO_28                        = IOMUX_PAD(0x0484, 0x013C, 5, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_VSYNC__USDHC2_CD_B                        = IOMUX_PAD(0x0484, 0x013C, 6, 0x086C, 0, 0),
+	 MX6_PAD_LCD1_VSYNC__SIM_M_HADDR_19                     = IOMUX_PAD(0x0484, 0x013C, 7, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_VSYNC__VADC_TEST_3                        = IOMUX_PAD(0x0484, 0x013C, 8, 0x0000, 0, 0),
+	 MX6_PAD_LCD1_VSYNC__MMDC_DEBUG_3                       = IOMUX_PAD(0x0484, 0x013C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_ALE__RAWNAND_ALE                          = IOMUX_PAD(0x0488, 0x0140, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_ALE__I2C3_SDA                             = IOMUX_PAD(0x0488, 0x0140, IOMUX_CONFIG_SION | 1, 0x07BC, 0, 0),
+	 MX6_PAD_NAND_ALE__QSPI2_A_SS0_B                        = IOMUX_PAD(0x0488, 0x0140, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_ALE__ECSPI2_SS0                           = IOMUX_PAD(0x0488, 0x0140, 3, 0x072C, 0, 0),
+	 MX6_PAD_NAND_ALE__ESAI_TX3_RX2                         = IOMUX_PAD(0x0488, 0x0140, 4, 0x079C, 0, 0),
+	 MX6_PAD_NAND_ALE__GPIO4_IO_0                           = IOMUX_PAD(0x0488, 0x0140, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_ALE__WEIM_CS0_B                           = IOMUX_PAD(0x0488, 0x0140, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_ALE__TPSMP_HDATA_0                        = IOMUX_PAD(0x0488, 0x0140, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN            = IOMUX_PAD(0x0488, 0x0140, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_ALE__SDMA_DEBUG_PC_12                     = IOMUX_PAD(0x0488, 0x0140, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B                      = IOMUX_PAD(0x048C, 0x0144, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE0_B__USDHC2_VSELECT                     = IOMUX_PAD(0x048C, 0x0144, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2                     = IOMUX_PAD(0x048C, 0x0144, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC                    = IOMUX_PAD(0x048C, 0x0144, 3, 0x0654, 0, 0),
+	 MX6_PAD_NAND_CE0_B__ESAI_TX_CLK                        = IOMUX_PAD(0x048C, 0x0144, 4, 0x078C, 0, 0),
+	 MX6_PAD_NAND_CE0_B__GPIO4_IO_1                         = IOMUX_PAD(0x048C, 0x0144, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE0_B__WEIM_LBA_B                         = IOMUX_PAD(0x048C, 0x0144, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE0_B__TPSMP_HDATA_3                      = IOMUX_PAD(0x048C, 0x0144, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ         = IOMUX_PAD(0x048C, 0x0144, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9                    = IOMUX_PAD(0x048C, 0x0144, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B                      = IOMUX_PAD(0x0490, 0x0148, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE1_B__USDHC3_RESET_B                     = IOMUX_PAD(0x0490, 0x0148, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3                     = IOMUX_PAD(0x0490, 0x0148, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD                    = IOMUX_PAD(0x0490, 0x0148, 3, 0x0648, 0, 0),
+	 MX6_PAD_NAND_CE1_B__ESAI_TX0                           = IOMUX_PAD(0x0490, 0x0148, 4, 0x0790, 0, 0),
+	 MX6_PAD_NAND_CE1_B__GPIO4_IO_2                         = IOMUX_PAD(0x0490, 0x0148, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE1_B__WEIM_OE                            = IOMUX_PAD(0x0490, 0x0148, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE1_B__TPSMP_HDATA_4                      = IOMUX_PAD(0x0490, 0x0148, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE     = IOMUX_PAD(0x0490, 0x0148, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8                    = IOMUX_PAD(0x0490, 0x0148, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_CLE__RAWNAND_CLE                          = IOMUX_PAD(0x0494, 0x014C, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CLE__I2C3_SCL                             = IOMUX_PAD(0x0494, 0x014C, IOMUX_CONFIG_SION | 1, 0x07B8, 0, 0),
+	 MX6_PAD_NAND_CLE__QSPI2_A_SCLK                         = IOMUX_PAD(0x0494, 0x014C, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CLE__ECSPI2_SCLK                          = IOMUX_PAD(0x0494, 0x014C, 3, 0x0720, 0, 0),
+	 MX6_PAD_NAND_CLE__ESAI_TX2_RX3                         = IOMUX_PAD(0x0494, 0x014C, 4, 0x0798, 0, 0),
+	 MX6_PAD_NAND_CLE__GPIO4_IO_3                           = IOMUX_PAD(0x0494, 0x014C, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CLE__WEIM_BCLK                            = IOMUX_PAD(0x0494, 0x014C, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CLE__TPSMP_CLK                            = IOMUX_PAD(0x0494, 0x014C, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP            = IOMUX_PAD(0x0494, 0x014C, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_CLE__SDMA_DEBUG_PC_13                     = IOMUX_PAD(0x0494, 0x014C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_DATA00__RAWNAND_DATA00                    = IOMUX_PAD(0x0498, 0x0150, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA00__USDHC1_DATA4                      = IOMUX_PAD(0x0498, 0x0150, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1                    = IOMUX_PAD(0x0498, 0x0150, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA00__ECSPI5_MISO                       = IOMUX_PAD(0x0498, 0x0150, 3, 0x0754, 0, 0),
+	 MX6_PAD_NAND_DATA00__ESAI_RX_CLK                       = IOMUX_PAD(0x0498, 0x0150, 4, 0x0788, 0, 0),
+	 MX6_PAD_NAND_DATA00__GPIO4_IO_4                        = IOMUX_PAD(0x0498, 0x0150, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA00__WEIM_AD_0                         = IOMUX_PAD(0x0498, 0x0150, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA00__TPSMP_HDATA_7                     = IOMUX_PAD(0x0498, 0x0150, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET = IOMUX_PAD(0x0498, 0x0150, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5        = IOMUX_PAD(0x0498, 0x0150, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_DATA01__RAWNAND_DATA01                    = IOMUX_PAD(0x049C, 0x0154, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA01__USDHC1_DATA5                      = IOMUX_PAD(0x049C, 0x0154, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0                    = IOMUX_PAD(0x049C, 0x0154, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA01__ECSPI5_MOSI                       = IOMUX_PAD(0x049C, 0x0154, 3, 0x0758, 0, 0),
+	 MX6_PAD_NAND_DATA01__ESAI_RX_FS                        = IOMUX_PAD(0x049C, 0x0154, 4, 0x0778, 0, 0),
+	 MX6_PAD_NAND_DATA01__GPIO4_IO_5                        = IOMUX_PAD(0x049C, 0x0154, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA01__WEIM_AD_1                         = IOMUX_PAD(0x049C, 0x0154, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA01__TPSMP_HDATA_8                     = IOMUX_PAD(0x049C, 0x0154, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD     = IOMUX_PAD(0x049C, 0x0154, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4        = IOMUX_PAD(0x049C, 0x0154, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_DATA02__RAWNAND_DATA02                    = IOMUX_PAD(0x04A0, 0x0158, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA02__USDHC1_DATA6                      = IOMUX_PAD(0x04A0, 0x0158, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA02__QSPI2_B_SCLK                      = IOMUX_PAD(0x04A0, 0x0158, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA02__ECSPI5_SCLK                       = IOMUX_PAD(0x04A0, 0x0158, 3, 0x0750, 0, 0),
+	 MX6_PAD_NAND_DATA02__ESAI_TX_HF_CLK                    = IOMUX_PAD(0x04A0, 0x0158, 4, 0x0784, 0, 0),
+	 MX6_PAD_NAND_DATA02__GPIO4_IO_6                        = IOMUX_PAD(0x04A0, 0x0158, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA02__WEIM_AD_2                         = IOMUX_PAD(0x04A0, 0x0158, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA02__TPSMP_HDATA_9                     = IOMUX_PAD(0x04A0, 0x0158, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV  = IOMUX_PAD(0x04A0, 0x0158, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3        = IOMUX_PAD(0x04A0, 0x0158, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_DATA03__RAWNAND_DATA03                    = IOMUX_PAD(0x04A4, 0x015C, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA03__USDHC1_DATA7                      = IOMUX_PAD(0x04A4, 0x015C, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B                     = IOMUX_PAD(0x04A4, 0x015C, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA03__ECSPI5_SS0                        = IOMUX_PAD(0x04A4, 0x015C, 3, 0x075C, 0, 0),
+	 MX6_PAD_NAND_DATA03__ESAI_RX_HF_CLK                    = IOMUX_PAD(0x04A4, 0x015C, 4, 0x0780, 0, 0),
+	 MX6_PAD_NAND_DATA03__GPIO4_IO_7                        = IOMUX_PAD(0x04A4, 0x015C, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA03__WEIM_AD_3                         = IOMUX_PAD(0x04A4, 0x015C, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA03__TPSMP_HDATA_10                    = IOMUX_PAD(0x04A4, 0x015C, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH    = IOMUX_PAD(0x04A4, 0x015C, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6        = IOMUX_PAD(0x04A4, 0x015C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_DATA04__RAWNAND_DATA04                    = IOMUX_PAD(0x04A8, 0x0160, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA04__USDHC2_DATA4                      = IOMUX_PAD(0x04A8, 0x0160, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA04__QSPI2_B_SS1_B                     = IOMUX_PAD(0x04A8, 0x0160, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA04__UART3_RTS_B                       = IOMUX_PAD(0x04A8, 0x0160, 3, 0x083C, 0, 0),
+	 MX6_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS                  = IOMUX_PAD(0x04A8, 0x0160, 4, 0x0650, 0, 0),
+	 MX6_PAD_NAND_DATA04__GPIO4_IO_8                        = IOMUX_PAD(0x04A8, 0x0160, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA04__WEIM_AD_4                         = IOMUX_PAD(0x04A8, 0x0160, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA04__TPSMP_HDATA_11                    = IOMUX_PAD(0x04A8, 0x0160, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH    = IOMUX_PAD(0x04A8, 0x0160, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0           = IOMUX_PAD(0x04A8, 0x0160, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_DATA05__RAWNAND_DATA05                    = IOMUX_PAD(0x04AC, 0x0164, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA05__USDHC2_DATA5                      = IOMUX_PAD(0x04AC, 0x0164, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA05__QSPI2_B_DQS                       = IOMUX_PAD(0x04AC, 0x0164, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA05__UART3_CTS_B                       = IOMUX_PAD(0x04AC, 0x0164, 3, 0x083C, 1, 0),
+	 MX6_PAD_NAND_DATA05__AUDMUX_AUD4_RXC                   = IOMUX_PAD(0x04AC, 0x0164, 4, 0x064C, 0, 0),
+	 MX6_PAD_NAND_DATA05__GPIO4_IO_9                        = IOMUX_PAD(0x04AC, 0x0164, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA05__WEIM_AD_5                         = IOMUX_PAD(0x04AC, 0x0164, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA05__TPSMP_HDATA_12                    = IOMUX_PAD(0x04AC, 0x0164, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET = IOMUX_PAD(0x04AC, 0x0164, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1           = IOMUX_PAD(0x04AC, 0x0164, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_DATA06__RAWNAND_DATA06                    = IOMUX_PAD(0x04B0, 0x0168, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA06__USDHC2_DATA6                      = IOMUX_PAD(0x04B0, 0x0168, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA06__QSPI2_A_SS1_B                     = IOMUX_PAD(0x04B0, 0x0168, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA06__UART3_RX                          = IOMUX_PAD(0x04B0, 0x0168, 3, 0x0840, 0, 0),
+	 MX6_PAD_NAND_DATA06__PWM3_OUT                          = IOMUX_PAD(0x04B0, 0x0168, 4, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA06__GPIO4_IO_10                       = IOMUX_PAD(0x04B0, 0x0168, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA06__WEIM_AD_6                         = IOMUX_PAD(0x04B0, 0x0168, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA06__TPSMP_HDATA_13                    = IOMUX_PAD(0x04B0, 0x0168, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD     = IOMUX_PAD(0x04B0, 0x0168, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2           = IOMUX_PAD(0x04B0, 0x0168, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_DATA07__RAWNAND_DATA07                    = IOMUX_PAD(0x04B4, 0x016C, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA07__USDHC2_DATA7                      = IOMUX_PAD(0x04B4, 0x016C, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA07__QSPI2_A_DQS                       = IOMUX_PAD(0x04B4, 0x016C, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA07__UART3_TX                          = IOMUX_PAD(0x04B4, 0x016C, 3, 0x0840, 1, 0),
+	 MX6_PAD_NAND_DATA07__PWM4_OUT                          = IOMUX_PAD(0x04B4, 0x016C, 4, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA07__GPIO4_IO_11                       = IOMUX_PAD(0x04B4, 0x016C, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA07__WEIM_AD_7                         = IOMUX_PAD(0x04B4, 0x016C, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA07__TPSMP_HDATA_14                    = IOMUX_PAD(0x04B4, 0x016C, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD     = IOMUX_PAD(0x04B4, 0x016C, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3           = IOMUX_PAD(0x04B4, 0x016C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_RE_B__RAWNAND_RE_B                        = IOMUX_PAD(0x04B8, 0x0170, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_RE_B__USDHC2_RESET_B                      = IOMUX_PAD(0x04B8, 0x0170, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3                      = IOMUX_PAD(0x04B8, 0x0170, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS                    = IOMUX_PAD(0x04B8, 0x0170, 3, 0x0658, 0, 0),
+	 MX6_PAD_NAND_RE_B__ESAI_TX_FS                          = IOMUX_PAD(0x04B8, 0x0170, 4, 0x077C, 0, 0),
+	 MX6_PAD_NAND_RE_B__GPIO4_IO_12                         = IOMUX_PAD(0x04B8, 0x0170, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_RE_B__WEIM_RW                             = IOMUX_PAD(0x04B8, 0x0170, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_RE_B__TPSMP_HDATA_5                       = IOMUX_PAD(0x04B8, 0x0170, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD       = IOMUX_PAD(0x04B8, 0x0170, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_RE_B__SDMA_DEBUG_PC_7                     = IOMUX_PAD(0x04B8, 0x0170, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_READY_B__RAWNAND_READY_B                  = IOMUX_PAD(0x04BC, 0x0174, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_READY_B__USDHC1_VSELECT                   = IOMUX_PAD(0x04BC, 0x0174, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1                   = IOMUX_PAD(0x04BC, 0x0174, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_READY_B__ECSPI2_MISO                      = IOMUX_PAD(0x04BC, 0x0174, 3, 0x0724, 0, 0),
+	 MX6_PAD_NAND_READY_B__ESAI_TX1                         = IOMUX_PAD(0x04BC, 0x0174, 4, 0x0794, 0, 0),
+	 MX6_PAD_NAND_READY_B__GPIO4_IO_13                      = IOMUX_PAD(0x04BC, 0x0174, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_READY_B__WEIM_EB_B_1                      = IOMUX_PAD(0x04BC, 0x0174, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_READY_B__TPSMP_HDATA_2                    = IOMUX_PAD(0x04BC, 0x0174, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN        = IOMUX_PAD(0x04BC, 0x0174, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_READY_B__SDMA_DEBUG_PC_10                 = IOMUX_PAD(0x04BC, 0x0174, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_WE_B__RAWNAND_WE_B                        = IOMUX_PAD(0x04C0, 0x0178, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WE_B__USDHC4_VSELECT                      = IOMUX_PAD(0x04C0, 0x0178, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2                      = IOMUX_PAD(0x04C0, 0x0178, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WE_B__AUDMUX_AUD4_RXD                     = IOMUX_PAD(0x04C0, 0x0178, 3, 0x0644, 0, 0),
+	 MX6_PAD_NAND_WE_B__ESAI_TX5_RX0                        = IOMUX_PAD(0x04C0, 0x0178, 4, 0x07A4, 0, 0),
+	 MX6_PAD_NAND_WE_B__GPIO4_IO_14                         = IOMUX_PAD(0x04C0, 0x0178, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WE_B__WEIM_WAIT                           = IOMUX_PAD(0x04C0, 0x0178, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WE_B__TPSMP_HDATA_6                       = IOMUX_PAD(0x04C0, 0x0178, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV    = IOMUX_PAD(0x04C0, 0x0178, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WE_B__SDMA_DEBUG_PC_6                     = IOMUX_PAD(0x04C0, 0x0178, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_NAND_WP_B__RAWNAND_WP_B                        = IOMUX_PAD(0x04C4, 0x017C, 0, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WP_B__USDHC1_RESET_B                      = IOMUX_PAD(0x04C4, 0x017C, 1, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0                      = IOMUX_PAD(0x04C4, 0x017C, 2, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WP_B__ECSPI2_MOSI                         = IOMUX_PAD(0x04C4, 0x017C, 3, 0x0728, 0, 0),
+	 MX6_PAD_NAND_WP_B__ESAI_TX4_RX1                        = IOMUX_PAD(0x04C4, 0x017C, 4, 0x07A0, 0, 0),
+	 MX6_PAD_NAND_WP_B__GPIO4_IO_15                         = IOMUX_PAD(0x04C4, 0x017C, 5, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WP_B__WEIM_EB_B_0                         = IOMUX_PAD(0x04C4, 0x017C, 6, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WP_B__TPSMP_HDATA_1                       = IOMUX_PAD(0x04C4, 0x017C, 7, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE      = IOMUX_PAD(0x04C4, 0x017C, 8, 0x0000, 0, 0),
+	 MX6_PAD_NAND_WP_B__SDMA_DEBUG_PC_11                    = IOMUX_PAD(0x04C4, 0x017C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0                   = IOMUX_PAD(0x04C8, 0x0180, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA0__USB_OTG2_OC                      = IOMUX_PAD(0x04C8, 0x0180, 1, 0x085C, 2, 0),
+	 MX6_PAD_QSPI1A_DATA0__ECSPI1_MOSI                      = IOMUX_PAD(0x04C8, 0x0180, 2, 0x0718, 1, 0),
+	 MX6_PAD_QSPI1A_DATA0__ESAI_TX4_RX1                     = IOMUX_PAD(0x04C8, 0x0180, 3, 0x07A0, 2, 0),
+	 MX6_PAD_QSPI1A_DATA0__CSI1_DATA_14                     = IOMUX_PAD(0x04C8, 0x0180, 4, 0x06D4, 1, 0),
+	 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16                      = IOMUX_PAD(0x04C8, 0x0180, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA0__WEIM_DATA_6                      = IOMUX_PAD(0x04C8, 0x0180, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA0__SIM_M_HADDR_3                    = IOMUX_PAD(0x04C8, 0x0180, 7, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3          = IOMUX_PAD(0x04C8, 0x0180, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1                   = IOMUX_PAD(0x04CC, 0x0184, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID                   = IOMUX_PAD(0x04CC, 0x0184, 1, 0x0624, 2, 0),
+	 MX6_PAD_QSPI1A_DATA1__ECSPI1_MISO                      = IOMUX_PAD(0x04CC, 0x0184, 2, 0x0714, 1, 0),
+	 MX6_PAD_QSPI1A_DATA1__ESAI_TX1                         = IOMUX_PAD(0x04CC, 0x0184, 3, 0x0794, 2, 0),
+	 MX6_PAD_QSPI1A_DATA1__CSI1_DATA_13                     = IOMUX_PAD(0x04CC, 0x0184, 4, 0x06D0, 1, 0),
+	 MX6_PAD_QSPI1A_DATA1__GPIO4_IO_17                      = IOMUX_PAD(0x04CC, 0x0184, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA1__WEIM_DATA_5                      = IOMUX_PAD(0x04CC, 0x0184, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA1__SIM_M_HADDR_4                    = IOMUX_PAD(0x04CC, 0x0184, 7, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0                  = IOMUX_PAD(0x04CC, 0x0184, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2                   = IOMUX_PAD(0x04D0, 0x0188, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA2__USB_OTG1_PWR                     = IOMUX_PAD(0x04D0, 0x0188, 1, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA2__ECSPI5_SS1                       = IOMUX_PAD(0x04D0, 0x0188, 2, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA2__ESAI_TX_CLK                      = IOMUX_PAD(0x04D0, 0x0188, 3, 0x078C, 2, 0),
+	 MX6_PAD_QSPI1A_DATA2__CSI1_DATA_12                     = IOMUX_PAD(0x04D0, 0x0188, 4, 0x06CC, 1, 0),
+	 MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18                      = IOMUX_PAD(0x04D0, 0x0188, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA2__WEIM_DATA_4                      = IOMUX_PAD(0x04D0, 0x0188, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA2__SIM_M_HADDR_6                    = IOMUX_PAD(0x04D0, 0x0188, 7, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1                  = IOMUX_PAD(0x04D0, 0x0188, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3                   = IOMUX_PAD(0x04D4, 0x018C, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA3__USB_OTG1_OC                      = IOMUX_PAD(0x04D4, 0x018C, 1, 0x0860, 2, 0),
+	 MX6_PAD_QSPI1A_DATA3__ECSPI5_SS2                       = IOMUX_PAD(0x04D4, 0x018C, 2, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA3__ESAI_TX0                         = IOMUX_PAD(0x04D4, 0x018C, 3, 0x0790, 2, 0),
+	 MX6_PAD_QSPI1A_DATA3__CSI1_DATA_11                     = IOMUX_PAD(0x04D4, 0x018C, 4, 0x06C8, 1, 0),
+	 MX6_PAD_QSPI1A_DATA3__GPIO4_IO_19                      = IOMUX_PAD(0x04D4, 0x018C, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA3__WEIM_DATA_3                      = IOMUX_PAD(0x04D4, 0x018C, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA3__SIM_M_HADDR_7                    = IOMUX_PAD(0x04D4, 0x018C, 7, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2                  = IOMUX_PAD(0x04D4, 0x018C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1A_DQS__QSPI1_A_DQS                        = IOMUX_PAD(0x04D8, 0x0190, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DQS__CAN2_TX                            = IOMUX_PAD(0x04D8, 0x0190, 1, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DQS__CANFD_TX2                          = IOMUX_PAD(0x04D8, 0x0190, 2, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DQS__ECSPI5_MOSI                        = IOMUX_PAD(0x04D8, 0x0190, 3, 0x0758, 1, 0),
+	 MX6_PAD_QSPI1A_DQS__CSI1_DATA_15                       = IOMUX_PAD(0x04D8, 0x0190, 4, 0x06D8, 1, 0),
+	 MX6_PAD_QSPI1A_DQS__GPIO4_IO_20                        = IOMUX_PAD(0x04D8, 0x0190, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DQS__WEIM_DATA_7                        = IOMUX_PAD(0x04D8, 0x0190, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DQS__SIM_M_HADDR_13                     = IOMUX_PAD(0x04D8, 0x0190, 7, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4            = IOMUX_PAD(0x04D8, 0x0190, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK                      = IOMUX_PAD(0x04DC, 0x0194, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID                    = IOMUX_PAD(0x04DC, 0x0194, 1, 0x0628, 2, 0),
+	 MX6_PAD_QSPI1A_SCLK__ECSPI1_SCLK                       = IOMUX_PAD(0x04DC, 0x0194, 2, 0x0710, 1, 0),
+	 MX6_PAD_QSPI1A_SCLK__ESAI_TX2_RX3                      = IOMUX_PAD(0x04DC, 0x0194, 3, 0x0798, 2, 0),
+	 MX6_PAD_QSPI1A_SCLK__CSI1_DATA_1                       = IOMUX_PAD(0x04DC, 0x0194, 4, 0x06A4, 1, 0),
+	 MX6_PAD_QSPI1A_SCLK__GPIO4_IO_21                       = IOMUX_PAD(0x04DC, 0x0194, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SCLK__WEIM_DATA_0                       = IOMUX_PAD(0x04DC, 0x0194, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SCLK__SIM_M_HADDR_0                     = IOMUX_PAD(0x04DC, 0x0194, 7, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5                   = IOMUX_PAD(0x04DC, 0x0194, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B                    = IOMUX_PAD(0x04E0, 0x0198, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SS0_B__USB_OTG2_PWR                     = IOMUX_PAD(0x04E0, 0x0198, 1, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SS0_B__ECSPI1_SS0                       = IOMUX_PAD(0x04E0, 0x0198, 2, 0x071C, 1, 0),
+	 MX6_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2                     = IOMUX_PAD(0x04E0, 0x0198, 3, 0x079C, 2, 0),
+	 MX6_PAD_QSPI1A_SS0_B__CSI1_DATA_0                      = IOMUX_PAD(0x04E0, 0x0198, 4, 0x06A0, 1, 0),
+	 MX6_PAD_QSPI1A_SS0_B__GPIO4_IO_22                      = IOMUX_PAD(0x04E0, 0x0198, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SS0_B__WEIM_DATA_1                      = IOMUX_PAD(0x04E0, 0x0198, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1                    = IOMUX_PAD(0x04E0, 0x0198, 7, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4                  = IOMUX_PAD(0x04E0, 0x0198, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B                    = IOMUX_PAD(0x04E4, 0x019C, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SS1_B__CAN1_RX                          = IOMUX_PAD(0x04E4, 0x019C, 1, 0x068C, 2, 0),
+	 MX6_PAD_QSPI1A_SS1_B__CANFD_RX1                        = IOMUX_PAD(0x04E4, 0x019C, 2, 0x0694, 2, 0),
+	 MX6_PAD_QSPI1A_SS1_B__ECSPI5_MISO                      = IOMUX_PAD(0x04E4, 0x019C, 3, 0x0754, 1, 0),
+	 MX6_PAD_QSPI1A_SS1_B__CSI1_DATA_10                     = IOMUX_PAD(0x04E4, 0x019C, 4, 0x06FC, 1, 0),
+	 MX6_PAD_QSPI1A_SS1_B__GPIO4_IO_23                      = IOMUX_PAD(0x04E4, 0x019C, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SS1_B__WEIM_DATA_2                      = IOMUX_PAD(0x04E4, 0x019C, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12                   = IOMUX_PAD(0x04E4, 0x019C, 7, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3                  = IOMUX_PAD(0x04E4, 0x019C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0                   = IOMUX_PAD(0x04E8, 0x01A0, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA0__UART3_CTS_B                      = IOMUX_PAD(0x04E8, 0x01A0, 1, 0x083C, 4, 0),
+	 MX6_PAD_QSPI1B_DATA0__ECSPI3_MOSI                      = IOMUX_PAD(0x04E8, 0x01A0, 2, 0x0738, 1, 0),
+	 MX6_PAD_QSPI1B_DATA0__ESAI_RX_FS                       = IOMUX_PAD(0x04E8, 0x01A0, 3, 0x0778, 2, 0),
+	 MX6_PAD_QSPI1B_DATA0__CSI1_DATA_22                     = IOMUX_PAD(0x04E8, 0x01A0, 4, 0x06F4, 1, 0),
+	 MX6_PAD_QSPI1B_DATA0__GPIO4_IO_24                      = IOMUX_PAD(0x04E8, 0x01A0, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA0__WEIM_DATA_14                     = IOMUX_PAD(0x04E8, 0x01A0, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA0__SIM_M_HADDR_9                    = IOMUX_PAD(0x04E8, 0x01A0, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1                   = IOMUX_PAD(0x04EC, 0x01A4, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA1__UART3_RTS_B                      = IOMUX_PAD(0x04EC, 0x01A4, 1, 0x083C, 5, 0),
+	 MX6_PAD_QSPI1B_DATA1__ECSPI3_MISO                      = IOMUX_PAD(0x04EC, 0x01A4, 2, 0x0734, 1, 0),
+	 MX6_PAD_QSPI1B_DATA1__ESAI_RX_CLK                      = IOMUX_PAD(0x04EC, 0x01A4, 3, 0x0788, 2, 0),
+	 MX6_PAD_QSPI1B_DATA1__CSI1_DATA_21                     = IOMUX_PAD(0x04EC, 0x01A4, 4, 0x06F0, 1, 0),
+	 MX6_PAD_QSPI1B_DATA1__GPIO4_IO_25                      = IOMUX_PAD(0x04EC, 0x01A4, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA1__WEIM_DATA_13                     = IOMUX_PAD(0x04EC, 0x01A4, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA1__SIM_M_HADDR_8                    = IOMUX_PAD(0x04EC, 0x01A4, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2                   = IOMUX_PAD(0x04F0, 0x01A8, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA2__I2C2_SDA                         = IOMUX_PAD(0x04F0, 0x01A8, IOMUX_CONFIG_SION | 1, 0x07B4, 2, 0),
+	 MX6_PAD_QSPI1B_DATA2__ECSPI5_RDY                       = IOMUX_PAD(0x04F0, 0x01A8, 2, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA2__ESAI_TX5_RX0                     = IOMUX_PAD(0x04F0, 0x01A8, 3, 0x07A4, 2, 0),
+	 MX6_PAD_QSPI1B_DATA2__CSI1_DATA_20                     = IOMUX_PAD(0x04F0, 0x01A8, 4, 0x06EC, 1, 0),
+	 MX6_PAD_QSPI1B_DATA2__GPIO4_IO_26                      = IOMUX_PAD(0x04F0, 0x01A8, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA2__WEIM_DATA_12                     = IOMUX_PAD(0x04F0, 0x01A8, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA2__SIM_M_HADDR_5                    = IOMUX_PAD(0x04F0, 0x01A8, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3                   = IOMUX_PAD(0x04F4, 0x01AC, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA3__I2C2_SCL                         = IOMUX_PAD(0x04F4, 0x01AC, IOMUX_CONFIG_SION | 1, 0x07B0, 2, 0),
+	 MX6_PAD_QSPI1B_DATA3__ECSPI5_SS3                       = IOMUX_PAD(0x04F4, 0x01AC, 2, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA3__ESAI_TX_FS                       = IOMUX_PAD(0x04F4, 0x01AC, 3, 0x077C, 2, 0),
+	 MX6_PAD_QSPI1B_DATA3__CSI1_DATA_19                     = IOMUX_PAD(0x04F4, 0x01AC, 4, 0x06E8, 1, 0),
+	 MX6_PAD_QSPI1B_DATA3__GPIO4_IO_27                      = IOMUX_PAD(0x04F4, 0x01AC, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA3__WEIM_DATA_11                     = IOMUX_PAD(0x04F4, 0x01AC, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DATA3__SIM_M_HADDR_2                    = IOMUX_PAD(0x04F4, 0x01AC, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1B_DQS__QSPI1_B_DQS                        = IOMUX_PAD(0x04F8, 0x01B0, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DQS__CAN1_TX                            = IOMUX_PAD(0x04F8, 0x01B0, 1, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DQS__CANFD_TX1                          = IOMUX_PAD(0x04F8, 0x01B0, 2, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DQS__ECSPI5_SS0                         = IOMUX_PAD(0x04F8, 0x01B0, 3, 0x075C, 1, 0),
+	 MX6_PAD_QSPI1B_DQS__CSI1_DATA_23                       = IOMUX_PAD(0x04F8, 0x01B0, 4, 0x06F8, 1, 0),
+	 MX6_PAD_QSPI1B_DQS__GPIO4_IO_28                        = IOMUX_PAD(0x04F8, 0x01B0, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DQS__WEIM_DATA_15                       = IOMUX_PAD(0x04F8, 0x01B0, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_DQS__SIM_M_HADDR_15                     = IOMUX_PAD(0x04F8, 0x01B0, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK                      = IOMUX_PAD(0x04FC, 0x01B4, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_SCLK__UART3_RX                          = IOMUX_PAD(0x04FC, 0x01B4, 1, 0x0840, 4, 0),
+	 MX6_PAD_QSPI1B_SCLK__ECSPI3_SCLK                       = IOMUX_PAD(0x04FC, 0x01B4, 2, 0x0730, 1, 0),
+	 MX6_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK                    = IOMUX_PAD(0x04FC, 0x01B4, 3, 0x0780, 2, 0),
+	 MX6_PAD_QSPI1B_SCLK__CSI1_DATA_16                      = IOMUX_PAD(0x04FC, 0x01B4, 4, 0x06DC, 1, 0),
+	 MX6_PAD_QSPI1B_SCLK__GPIO4_IO_29                       = IOMUX_PAD(0x04FC, 0x01B4, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_SCLK__WEIM_DATA_8                       = IOMUX_PAD(0x04FC, 0x01B4, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_SCLK__SIM_M_HADDR_11                    = IOMUX_PAD(0x04FC, 0x01B4, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B                    = IOMUX_PAD(0x0500, 0x01B8, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_SS0_B__UART3_TX                         = IOMUX_PAD(0x0500, 0x01B8, 1, 0x0840, 5, 0),
+	 MX6_PAD_QSPI1B_SS0_B__ECSPI3_SS0                       = IOMUX_PAD(0x0500, 0x01B8, 2, 0x073C, 1, 0),
+	 MX6_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK                   = IOMUX_PAD(0x0500, 0x01B8, 3, 0x0784, 3, 0),
+	 MX6_PAD_QSPI1B_SS0_B__CSI1_DATA_17                     = IOMUX_PAD(0x0500, 0x01B8, 4, 0x06E0, 1, 0),
+	 MX6_PAD_QSPI1B_SS0_B__GPIO4_IO_30                      = IOMUX_PAD(0x0500, 0x01B8, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_SS0_B__WEIM_DATA_9                      = IOMUX_PAD(0x0500, 0x01B8, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10                   = IOMUX_PAD(0x0500, 0x01B8, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B                    = IOMUX_PAD(0x0504, 0x01BC, 0, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_SS1_B__CAN2_RX                          = IOMUX_PAD(0x0504, 0x01BC, 1, 0x0690, 2, 0),
+	 MX6_PAD_QSPI1B_SS1_B__CANFD_RX2                        = IOMUX_PAD(0x0504, 0x01BC, 2, 0x0698, 2, 0),
+	 MX6_PAD_QSPI1B_SS1_B__ECSPI5_SCLK                      = IOMUX_PAD(0x0504, 0x01BC, 3, 0x0750, 1, 0),
+	 MX6_PAD_QSPI1B_SS1_B__CSI1_DATA_18                     = IOMUX_PAD(0x0504, 0x01BC, 4, 0x06E4, 1, 0),
+	 MX6_PAD_QSPI1B_SS1_B__GPIO4_IO_31                      = IOMUX_PAD(0x0504, 0x01BC, 5, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_SS1_B__WEIM_DATA_10                     = IOMUX_PAD(0x0504, 0x01BC, 6, 0x0000, 0, 0),
+	 MX6_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14                   = IOMUX_PAD(0x0504, 0x01BC, 7, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0                    = IOMUX_PAD(0x0508, 0x01C0, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD0__GPIO5_IO_0                         = IOMUX_PAD(0x0508, 0x01C0, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD0__CSI2_DATA_10                       = IOMUX_PAD(0x0508, 0x01C0, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD0__ANATOP_TESTI_0                     = IOMUX_PAD(0x0508, 0x01C0, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER             = IOMUX_PAD(0x0508, 0x01C0, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0                  = IOMUX_PAD(0x0508, 0x01C0, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1                    = IOMUX_PAD(0x050C, 0x01C4, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD1__GPIO5_IO_1                         = IOMUX_PAD(0x050C, 0x01C4, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD1__CSI2_DATA_11                       = IOMUX_PAD(0x050C, 0x01C4, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD1__ANATOP_TESTI_1                     = IOMUX_PAD(0x050C, 0x01C4, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER              = IOMUX_PAD(0x050C, 0x01C4, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1                  = IOMUX_PAD(0x050C, 0x01C4, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2                    = IOMUX_PAD(0x0510, 0x01C8, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD2__GPIO5_IO_2                         = IOMUX_PAD(0x0510, 0x01C8, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD2__CSI2_DATA_12                       = IOMUX_PAD(0x0510, 0x01C8, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD2__ANATOP_TESTI_2                     = IOMUX_PAD(0x0510, 0x01C8, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER              = IOMUX_PAD(0x0510, 0x01C8, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2                  = IOMUX_PAD(0x0510, 0x01C8, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3                    = IOMUX_PAD(0x0514, 0x01CC, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD3__GPIO5_IO_3                         = IOMUX_PAD(0x0514, 0x01CC, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD3__CSI2_DATA_13                       = IOMUX_PAD(0x0514, 0x01CC, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD3__ANATOP_TESTI_3                     = IOMUX_PAD(0x0514, 0x01CC, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER              = IOMUX_PAD(0x0514, 0x01CC, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3                  = IOMUX_PAD(0x0514, 0x01CC, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN                     = IOMUX_PAD(0x0518, 0x01D0, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RX_CTL__GPIO5_IO_4                      = IOMUX_PAD(0x0518, 0x01D0, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RX_CTL__CSI2_DATA_14                    = IOMUX_PAD(0x0518, 0x01D0, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0                  = IOMUX_PAD(0x0518, 0x01D0, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER           = IOMUX_PAD(0x0518, 0x01D0, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4               = IOMUX_PAD(0x0518, 0x01D0, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_RXC__ENET1_RX_CLK                       = IOMUX_PAD(0x051C, 0x01D4, 0, 0x0768, 1, 0),
+	 MX6_PAD_RGMII1_RXC__ENET1_RX_ER                        = IOMUX_PAD(0x051C, 0x01D4, 1, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RXC__GPIO5_IO_5                         = IOMUX_PAD(0x051C, 0x01D4, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RXC__CSI2_DATA_15                       = IOMUX_PAD(0x051C, 0x01D4, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RXC__ANATOP_TESTO_1                     = IOMUX_PAD(0x051C, 0x01D4, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER              = IOMUX_PAD(0x051C, 0x01D4, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5                  = IOMUX_PAD(0x051C, 0x01D4, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0                    = IOMUX_PAD(0x0520, 0x01D8, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD0__SAI2_RX_SYNC                       = IOMUX_PAD(0x0520, 0x01D8, 2, 0x0810, 1, 0),
+	 MX6_PAD_RGMII1_TD0__GPIO5_IO_6                         = IOMUX_PAD(0x0520, 0x01D8, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD0__CSI2_DATA_16                       = IOMUX_PAD(0x0520, 0x01D8, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD0__ANATOP_TESTO_2                     = IOMUX_PAD(0x0520, 0x01D8, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER              = IOMUX_PAD(0x0520, 0x01D8, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6                  = IOMUX_PAD(0x0520, 0x01D8, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1                    = IOMUX_PAD(0x0524, 0x01DC, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD1__SAI2_RX_BCLK                       = IOMUX_PAD(0x0524, 0x01DC, 2, 0x0808, 1, 0),
+	 MX6_PAD_RGMII1_TD1__GPIO5_IO_7                         = IOMUX_PAD(0x0524, 0x01DC, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD1__CSI2_DATA_17                       = IOMUX_PAD(0x0524, 0x01DC, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD1__ANATOP_TESTO_3                     = IOMUX_PAD(0x0524, 0x01DC, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER              = IOMUX_PAD(0x0524, 0x01DC, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7                  = IOMUX_PAD(0x0524, 0x01DC, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2                    = IOMUX_PAD(0x0528, 0x01E0, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD2__SAI2_TX_SYNC                       = IOMUX_PAD(0x0528, 0x01E0, 2, 0x0818, 1, 0),
+	 MX6_PAD_RGMII1_TD2__GPIO5_IO_8                         = IOMUX_PAD(0x0528, 0x01E0, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD2__CSI2_DATA_18                       = IOMUX_PAD(0x0528, 0x01E0, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD2__ANATOP_TESTO_4                     = IOMUX_PAD(0x0528, 0x01E0, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER              = IOMUX_PAD(0x0528, 0x01E0, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8                  = IOMUX_PAD(0x0528, 0x01E0, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3                    = IOMUX_PAD(0x052C, 0x01E4, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD3__SAI2_TX_BCLK                       = IOMUX_PAD(0x052C, 0x01E4, 2, 0x0814, 1, 0),
+	 MX6_PAD_RGMII1_TD3__GPIO5_IO_9                         = IOMUX_PAD(0x052C, 0x01E4, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD3__CSI2_DATA_19                       = IOMUX_PAD(0x052C, 0x01E4, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD3__ANATOP_TESTO_5                     = IOMUX_PAD(0x052C, 0x01E4, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER              = IOMUX_PAD(0x052C, 0x01E4, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9                  = IOMUX_PAD(0x052C, 0x01E4, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN                     = IOMUX_PAD(0x0530, 0x01E8, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0                  = IOMUX_PAD(0x0530, 0x01E8, 2, 0x080C, 1, 0),
+	 MX6_PAD_RGMII1_TX_CTL__GPIO5_IO_10                     = IOMUX_PAD(0x0530, 0x01E8, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TX_CTL__CSI2_DATA_0                     = IOMUX_PAD(0x0530, 0x01E8, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6                  = IOMUX_PAD(0x0530, 0x01E8, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER            = IOMUX_PAD(0x0530, 0x01E8, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10              = IOMUX_PAD(0x0530, 0x01E8, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC                    = IOMUX_PAD(0x0534, 0x01EC, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TXC__ENET1_TX_ER                        = IOMUX_PAD(0x0534, 0x01EC, 1, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TXC__SAI2_TX_DATA_0                     = IOMUX_PAD(0x0534, 0x01EC, 2, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TXC__GPIO5_IO_11                        = IOMUX_PAD(0x0534, 0x01EC, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TXC__CSI2_DATA_1                        = IOMUX_PAD(0x0534, 0x01EC, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TXC__ANATOP_TESTO_7                     = IOMUX_PAD(0x0534, 0x01EC, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER               = IOMUX_PAD(0x0534, 0x01EC, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11                 = IOMUX_PAD(0x0534, 0x01EC, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0                    = IOMUX_PAD(0x0538, 0x01F0, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD0__PWM4_OUT                           = IOMUX_PAD(0x0538, 0x01F0, 2, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD0__GPIO5_IO_12                        = IOMUX_PAD(0x0538, 0x01F0, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD0__CSI2_DATA_2                        = IOMUX_PAD(0x0538, 0x01F0, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD0__ANATOP_TESTO_8                     = IOMUX_PAD(0x0538, 0x01F0, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD0__VDEC_DEBUG_18                      = IOMUX_PAD(0x0538, 0x01F0, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12                 = IOMUX_PAD(0x0538, 0x01F0, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1                    = IOMUX_PAD(0x053C, 0x01F4, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD1__PWM3_OUT                           = IOMUX_PAD(0x053C, 0x01F4, 2, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD1__GPIO5_IO_13                        = IOMUX_PAD(0x053C, 0x01F4, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD1__CSI2_DATA_3                        = IOMUX_PAD(0x053C, 0x01F4, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD1__ANATOP_TESTO_9                     = IOMUX_PAD(0x053C, 0x01F4, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD1__VDEC_DEBUG_19                      = IOMUX_PAD(0x053C, 0x01F4, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13                 = IOMUX_PAD(0x053C, 0x01F4, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2                    = IOMUX_PAD(0x0540, 0x01F8, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD2__PWM2_OUT                           = IOMUX_PAD(0x0540, 0x01F8, 2, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD2__GPIO5_IO_14                        = IOMUX_PAD(0x0540, 0x01F8, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD2__CSI2_DATA_4                        = IOMUX_PAD(0x0540, 0x01F8, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD2__ANATOP_TESTO_10                    = IOMUX_PAD(0x0540, 0x01F8, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD2__VDEC_DEBUG_20                      = IOMUX_PAD(0x0540, 0x01F8, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14                 = IOMUX_PAD(0x0540, 0x01F8, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3                    = IOMUX_PAD(0x0544, 0x01FC, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD3__PWM1_OUT                           = IOMUX_PAD(0x0544, 0x01FC, 2, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD3__GPIO5_IO_15                        = IOMUX_PAD(0x0544, 0x01FC, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD3__CSI2_DATA_5                        = IOMUX_PAD(0x0544, 0x01FC, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD3__ANATOP_TESTO_11                    = IOMUX_PAD(0x0544, 0x01FC, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD3__VDEC_DEBUG_21                      = IOMUX_PAD(0x0544, 0x01FC, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15                 = IOMUX_PAD(0x0544, 0x01FC, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN                     = IOMUX_PAD(0x0548, 0x0200, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RX_CTL__GPIO5_IO_16                     = IOMUX_PAD(0x0548, 0x0200, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RX_CTL__CSI2_DATA_6                     = IOMUX_PAD(0x0548, 0x0200, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12                 = IOMUX_PAD(0x0548, 0x0200, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22                   = IOMUX_PAD(0x0548, 0x0200, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16              = IOMUX_PAD(0x0548, 0x0200, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_RXC__ENET2_RX_CLK                       = IOMUX_PAD(0x054C, 0x0204, 0, 0x0774, 1, 0),
+	 MX6_PAD_RGMII2_RXC__ENET2_RX_ER                        = IOMUX_PAD(0x054C, 0x0204, 1, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RXC__GPIO5_IO_17                        = IOMUX_PAD(0x054C, 0x0204, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RXC__CSI2_DATA_7                        = IOMUX_PAD(0x054C, 0x0204, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RXC__ANATOP_TESTO_13                    = IOMUX_PAD(0x054C, 0x0204, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RXC__VDEC_DEBUG_23                      = IOMUX_PAD(0x054C, 0x0204, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17                 = IOMUX_PAD(0x054C, 0x0204, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0                    = IOMUX_PAD(0x0550, 0x0208, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD0__SAI1_RX_SYNC                       = IOMUX_PAD(0x0550, 0x0208, 2, 0x07FC, 1, 0),
+	 MX6_PAD_RGMII2_TD0__PWM8_OUT                           = IOMUX_PAD(0x0550, 0x0208, 3, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD0__GPIO5_IO_18                        = IOMUX_PAD(0x0550, 0x0208, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD0__CSI2_DATA_8                        = IOMUX_PAD(0x0550, 0x0208, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD0__ANATOP_TESTO_14                    = IOMUX_PAD(0x0550, 0x0208, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD0__VDEC_DEBUG_24                      = IOMUX_PAD(0x0550, 0x0208, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18                 = IOMUX_PAD(0x0550, 0x0208, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1                    = IOMUX_PAD(0x0554, 0x020C, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD1__SAI1_RX_BCLK                       = IOMUX_PAD(0x0554, 0x020C, 2, 0x07F4, 1, 0),
+	 MX6_PAD_RGMII2_TD1__PWM7_OUT                           = IOMUX_PAD(0x0554, 0x020C, 3, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD1__GPIO5_IO_19                        = IOMUX_PAD(0x0554, 0x020C, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD1__CSI2_DATA_9                        = IOMUX_PAD(0x0554, 0x020C, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD1__ANATOP_TESTO_15                    = IOMUX_PAD(0x0554, 0x020C, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD1__VDEC_DEBUG_25                      = IOMUX_PAD(0x0554, 0x020C, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19                 = IOMUX_PAD(0x0554, 0x020C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2                    = IOMUX_PAD(0x0558, 0x0210, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD2__SAI1_TX_SYNC                       = IOMUX_PAD(0x0558, 0x0210, 2, 0x0804, 1, 0),
+	 MX6_PAD_RGMII2_TD2__PWM6_OUT                           = IOMUX_PAD(0x0558, 0x0210, 3, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD2__GPIO5_IO_20                        = IOMUX_PAD(0x0558, 0x0210, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD2__CSI2_VSYNC                         = IOMUX_PAD(0x0558, 0x0210, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD2__SJC_FAIL                           = IOMUX_PAD(0x0558, 0x0210, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD2__VDEC_DEBUG_26                      = IOMUX_PAD(0x0558, 0x0210, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20                 = IOMUX_PAD(0x0558, 0x0210, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3                    = IOMUX_PAD(0x055C, 0x0214, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD3__SAI1_TX_BCLK                       = IOMUX_PAD(0x055C, 0x0214, 2, 0x0800, 1, 0),
+	 MX6_PAD_RGMII2_TD3__PWM5_OUT                           = IOMUX_PAD(0x055C, 0x0214, 3, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD3__GPIO5_IO_21                        = IOMUX_PAD(0x055C, 0x0214, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD3__CSI2_HSYNC                         = IOMUX_PAD(0x055C, 0x0214, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD3__SJC_JTAG_ACT                       = IOMUX_PAD(0x055C, 0x0214, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD3__VDEC_DEBUG_27                      = IOMUX_PAD(0x055C, 0x0214, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21                 = IOMUX_PAD(0x055C, 0x0214, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN                     = IOMUX_PAD(0x0560, 0x0218, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0                  = IOMUX_PAD(0x0560, 0x0218, 2, 0x07F8, 1, 0),
+	 MX6_PAD_RGMII2_TX_CTL__GPIO5_IO_22                     = IOMUX_PAD(0x0560, 0x0218, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TX_CTL__CSI2_FIELD                      = IOMUX_PAD(0x0560, 0x0218, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TX_CTL__SJC_DE_B                        = IOMUX_PAD(0x0560, 0x0218, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28                   = IOMUX_PAD(0x0560, 0x0218, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22              = IOMUX_PAD(0x0560, 0x0218, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC                    = IOMUX_PAD(0x0564, 0x021C, 0, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TXC__ENET2_TX_ER                        = IOMUX_PAD(0x0564, 0x021C, 1, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TXC__SAI1_TX_DATA_0                     = IOMUX_PAD(0x0564, 0x021C, 2, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TXC__GPIO5_IO_23                        = IOMUX_PAD(0x0564, 0x021C, 5, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TXC__CSI2_PIXCLK                        = IOMUX_PAD(0x0564, 0x021C, 6, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TXC__SJC_DONE                           = IOMUX_PAD(0x0564, 0x021C, 7, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TXC__VDEC_DEBUG_29                      = IOMUX_PAD(0x0564, 0x021C, 8, 0x0000, 0, 0),
+	 MX6_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23                 = IOMUX_PAD(0x0564, 0x021C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD1_CLK__USDHC1_CLK                            = IOMUX_PAD(0x0568, 0x0220, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CLK__AUDMUX_AUD5_RXFS                      = IOMUX_PAD(0x0568, 0x0220, 1, 0x0668, 1, 0),
+	 MX6_PAD_SD1_CLK__WDOG2_WDOG_B                          = IOMUX_PAD(0x0568, 0x0220, 2, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CLK__GPT_CLK                               = IOMUX_PAD(0x0568, 0x0220, 3, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB                  = IOMUX_PAD(0x0568, 0x0220, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CLK__GPIO6_IO_0                            = IOMUX_PAD(0x0568, 0x0220, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT                 = IOMUX_PAD(0x0568, 0x0220, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CLK__CCM_OUT1                              = IOMUX_PAD(0x0568, 0x0220, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CLK__VADC_ADC_PROC_CLK                     = IOMUX_PAD(0x0568, 0x0220, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CLK__MMDC_DEBUG_45                         = IOMUX_PAD(0x0568, 0x0220, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD1_CMD__USDHC1_CMD                            = IOMUX_PAD(0x056C, 0x0224, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CMD__AUDMUX_AUD5_RXC                       = IOMUX_PAD(0x056C, 0x0224, 1, 0x0664, 1, 0),
+	 MX6_PAD_SD1_CMD__WDOG1_WDOG_B                          = IOMUX_PAD(0x056C, 0x0224, 2, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CMD__GPT_COMPARE1                          = IOMUX_PAD(0x056C, 0x0224, 3, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB                  = IOMUX_PAD(0x056C, 0x0224, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CMD__GPIO6_IO_1                            = IOMUX_PAD(0x056C, 0x0224, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CMD__ENET2_1588_EVENT1_IN                  = IOMUX_PAD(0x056C, 0x0224, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CMD__CCM_CLKO1                             = IOMUX_PAD(0x056C, 0x0224, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CMD__VADC_EXT_SYSCLK                       = IOMUX_PAD(0x056C, 0x0224, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD1_CMD__MMDC_DEBUG_46                         = IOMUX_PAD(0x056C, 0x0224, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD1_DATA0__USDHC1_DATA0                        = IOMUX_PAD(0x0570, 0x0228, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA0__AUDMUX_AUD5_RXD                     = IOMUX_PAD(0x0570, 0x0228, 1, 0x065C, 1, 0),
+	 MX6_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS            = IOMUX_PAD(0x0570, 0x0228, 2, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA0__GPT_CAPTURE1                        = IOMUX_PAD(0x0570, 0x0228, 3, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA0__UART2_RX                            = IOMUX_PAD(0x0570, 0x0228, 4, 0x0838, 2, 0),
+	 MX6_PAD_SD1_DATA0__GPIO6_IO_2                          = IOMUX_PAD(0x0570, 0x0228, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN                = IOMUX_PAD(0x0570, 0x0228, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA0__CCM_OUT2                            = IOMUX_PAD(0x0570, 0x0228, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA0__VADC_CLAMP_UP                       = IOMUX_PAD(0x0570, 0x0228, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA0__MMDC_DEBUG_48                       = IOMUX_PAD(0x0570, 0x0228, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD1_DATA1__USDHC1_DATA1                        = IOMUX_PAD(0x0574, 0x022C, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA1__AUDMUX_AUD5_TXC                     = IOMUX_PAD(0x0574, 0x022C, 1, 0x066C, 1, 0),
+	 MX6_PAD_SD1_DATA1__PWM4_OUT                            = IOMUX_PAD(0x0574, 0x022C, 2, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA1__GPT_CAPTURE2                        = IOMUX_PAD(0x0574, 0x022C, 3, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA1__UART2_TX                            = IOMUX_PAD(0x0574, 0x022C, 4, 0x0838, 3, 0),
+	 MX6_PAD_SD1_DATA1__GPIO6_IO_3                          = IOMUX_PAD(0x0574, 0x022C, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT               = IOMUX_PAD(0x0574, 0x022C, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA1__CCM_CLKO2                           = IOMUX_PAD(0x0574, 0x022C, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA1__VADC_CLAMP_DOWN                     = IOMUX_PAD(0x0574, 0x022C, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA1__MMDC_DEBUG_47                       = IOMUX_PAD(0x0574, 0x022C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD1_DATA2__USDHC1_DATA2                        = IOMUX_PAD(0x0578, 0x0230, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS                    = IOMUX_PAD(0x0578, 0x0230, 1, 0x0670, 1, 0),
+	 MX6_PAD_SD1_DATA2__PWM3_OUT                            = IOMUX_PAD(0x0578, 0x0230, 2, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA2__GPT_COMPARE2                        = IOMUX_PAD(0x0578, 0x0230, 3, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA2__UART2_CTS_B                         = IOMUX_PAD(0x0578, 0x0230, 4, 0x0834, 2, 0),
+	 MX6_PAD_SD1_DATA2__GPIO6_IO_4                          = IOMUX_PAD(0x0578, 0x0230, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA2__ECSPI4_RDY                          = IOMUX_PAD(0x0578, 0x0230, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA2__CCM_OUT0                            = IOMUX_PAD(0x0578, 0x0230, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA2__VADC_EXT_PD_N                       = IOMUX_PAD(0x0578, 0x0230, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_SD1_DATA3__USDHC1_DATA3                        = IOMUX_PAD(0x057C, 0x0234, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA3__AUDMUX_AUD5_TXD                     = IOMUX_PAD(0x057C, 0x0234, 1, 0x0660, 1, 0),
+	 MX6_PAD_SD1_DATA3__AUDMUX_AUD5_RXD                     = IOMUX_PAD(0x057C, 0x0234, 2, 0x065C, 2, 0),
+	 MX6_PAD_SD1_DATA3__GPT_COMPARE3                        = IOMUX_PAD(0x057C, 0x0234, 3, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA3__UART2_RTS_B                         = IOMUX_PAD(0x057C, 0x0234, 4, 0x0834, 3, 0),
+	 MX6_PAD_SD1_DATA3__GPIO6_IO_5                          = IOMUX_PAD(0x057C, 0x0234, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA3__ECSPI4_SS1                          = IOMUX_PAD(0x057C, 0x0234, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD1_DATA3__CCM_PMIC_RDY                        = IOMUX_PAD(0x057C, 0x0234, 7, 0x069C, 2, 0),
+	 MX6_PAD_SD1_DATA3__VADC_RST_N                          = IOMUX_PAD(0x057C, 0x0234, 8, 0x0000, 0, 0),
+
+	 MX6_PAD_SD2_CLK__USDHC2_CLK                            = IOMUX_PAD(0x0580, 0x0238, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD2_CLK__AUDMUX_AUD6_RXFS                      = IOMUX_PAD(0x0580, 0x0238, 1, 0x0680, 2, 0),
+	 MX6_PAD_SD2_CLK__KPP_COL_5                             = IOMUX_PAD(0x0580, 0x0238, 2, 0x07C8, 1, 0),
+	 MX6_PAD_SD2_CLK__ECSPI4_SCLK                           = IOMUX_PAD(0x0580, 0x0238, 3, 0x0740, 1, 0),
+	 MX6_PAD_SD2_CLK__MLB_SIG                               = IOMUX_PAD(0x0580, 0x0238, 4, 0x07F0, 2, 0),
+	 MX6_PAD_SD2_CLK__GPIO6_IO_6                            = IOMUX_PAD(0x0580, 0x0238, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD2_CLK__MQS_RIGHT                             = IOMUX_PAD(0x0580, 0x0238, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD2_CLK__WDOG1_WDOG_ANY                        = IOMUX_PAD(0x0580, 0x0238, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5                  = IOMUX_PAD(0x0580, 0x0238, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD2_CLK__MMDC_DEBUG_29                         = IOMUX_PAD(0x0580, 0x0238, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD2_CMD__USDHC2_CMD                            = IOMUX_PAD(0x0584, 0x023C, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD2_CMD__AUDMUX_AUD6_RXC                       = IOMUX_PAD(0x0584, 0x023C, 1, 0x067C, 2, 0),
+	 MX6_PAD_SD2_CMD__KPP_ROW_5                             = IOMUX_PAD(0x0584, 0x023C, 2, 0x07D4, 1, 0),
+	 MX6_PAD_SD2_CMD__ECSPI4_MOSI                           = IOMUX_PAD(0x0584, 0x023C, 3, 0x0748, 1, 0),
+	 MX6_PAD_SD2_CMD__MLB_CLK                               = IOMUX_PAD(0x0584, 0x023C, 4, 0x07E8, 2, 0),
+	 MX6_PAD_SD2_CMD__GPIO6_IO_7                            = IOMUX_PAD(0x0584, 0x023C, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD2_CMD__MQS_LEFT                              = IOMUX_PAD(0x0584, 0x023C, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD2_CMD__WDOG3_WDOG_B                          = IOMUX_PAD(0x0584, 0x023C, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4                  = IOMUX_PAD(0x0584, 0x023C, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD2_CMD__MMDC_DEBUG_30                         = IOMUX_PAD(0x0584, 0x023C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD2_DATA0__USDHC2_DATA0                        = IOMUX_PAD(0x0588, 0x0240, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA0__AUDMUX_AUD6_RXD                     = IOMUX_PAD(0x0588, 0x0240, 1, 0x0674, 2, 0),
+	 MX6_PAD_SD2_DATA0__KPP_ROW_7                           = IOMUX_PAD(0x0588, 0x0240, 2, 0x07DC, 1, 0),
+	 MX6_PAD_SD2_DATA0__PWM1_OUT                            = IOMUX_PAD(0x0588, 0x0240, 3, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA0__I2C4_SDA                            = IOMUX_PAD(0x0588, 0x0240, IOMUX_CONFIG_SION | 4, 0x07C4, 3, 0),
+	 MX6_PAD_SD2_DATA0__GPIO6_IO_8                          = IOMUX_PAD(0x0588, 0x0240, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA0__ECSPI4_SS3                          = IOMUX_PAD(0x0588, 0x0240, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA0__UART4_RX                            = IOMUX_PAD(0x0588, 0x0240, 7, 0x0848, 4, 0),
+	 MX6_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0                = IOMUX_PAD(0x0588, 0x0240, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA0__MMDC_DEBUG_50                       = IOMUX_PAD(0x0588, 0x0240, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD2_DATA1__USDHC2_DATA1                        = IOMUX_PAD(0x058C, 0x0244, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA1__AUDMUX_AUD6_TXC                     = IOMUX_PAD(0x058C, 0x0244, 1, 0x0684, 2, 0),
+	 MX6_PAD_SD2_DATA1__KPP_COL_7                           = IOMUX_PAD(0x058C, 0x0244, 2, 0x07D0, 1, 0),
+	 MX6_PAD_SD2_DATA1__PWM2_OUT                            = IOMUX_PAD(0x058C, 0x0244, 3, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA1__I2C4_SCL                            = IOMUX_PAD(0x058C, 0x0244, IOMUX_CONFIG_SION | 4, 0x07C0, 3, 0),
+	 MX6_PAD_SD2_DATA1__GPIO6_IO_9                          = IOMUX_PAD(0x058C, 0x0244, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA1__ECSPI4_SS2                          = IOMUX_PAD(0x058C, 0x0244, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA1__UART4_TX                            = IOMUX_PAD(0x058C, 0x0244, 7, 0x0848, 5, 0),
+	 MX6_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1                = IOMUX_PAD(0x058C, 0x0244, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA1__MMDC_DEBUG_49                       = IOMUX_PAD(0x058C, 0x0244, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD2_DATA2__USDHC2_DATA2                        = IOMUX_PAD(0x0590, 0x0248, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS                    = IOMUX_PAD(0x0590, 0x0248, 1, 0x0688, 2, 0),
+	 MX6_PAD_SD2_DATA2__KPP_ROW_6                           = IOMUX_PAD(0x0590, 0x0248, 2, 0x07D8, 1, 0),
+	 MX6_PAD_SD2_DATA2__ECSPI4_SS0                          = IOMUX_PAD(0x0590, 0x0248, 3, 0x074C, 1, 0),
+	 MX6_PAD_SD2_DATA2__SDMA_EXT_EVENT_0                    = IOMUX_PAD(0x0590, 0x0248, 4, 0x081C, 2, 0),
+	 MX6_PAD_SD2_DATA2__GPIO6_IO_10                         = IOMUX_PAD(0x0590, 0x0248, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA2__SPDIF_OUT                           = IOMUX_PAD(0x0590, 0x0248, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA2__UART6_RX                            = IOMUX_PAD(0x0590, 0x0248, 7, 0x0858, 4, 0),
+	 MX6_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2                = IOMUX_PAD(0x0590, 0x0248, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA2__MMDC_DEBUG_32                       = IOMUX_PAD(0x0590, 0x0248, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD2_DATA3__USDHC2_DATA3                        = IOMUX_PAD(0x0594, 0x024C, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA3__AUDMUX_AUD6_TXD                     = IOMUX_PAD(0x0594, 0x024C, 1, 0x0678, 2, 0),
+	 MX6_PAD_SD2_DATA3__KPP_COL_6                           = IOMUX_PAD(0x0594, 0x024C, 2, 0x07CC, 1, 0),
+	 MX6_PAD_SD2_DATA3__ECSPI4_MISO                         = IOMUX_PAD(0x0594, 0x024C, 3, 0x0744, 1, 0),
+	 MX6_PAD_SD2_DATA3__MLB_DATA                            = IOMUX_PAD(0x0594, 0x024C, 4, 0x07EC, 2, 0),
+	 MX6_PAD_SD2_DATA3__GPIO6_IO_11                         = IOMUX_PAD(0x0594, 0x024C, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA3__SPDIF_IN                            = IOMUX_PAD(0x0594, 0x024C, 6, 0x0824, 4, 0),
+	 MX6_PAD_SD2_DATA3__UART6_TX                            = IOMUX_PAD(0x0594, 0x024C, 7, 0x0858, 5, 0),
+	 MX6_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3                = IOMUX_PAD(0x0594, 0x024C, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD2_DATA3__MMDC_DEBUG_31                       = IOMUX_PAD(0x0594, 0x024C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD3_CLK__USDHC3_CLK                            = IOMUX_PAD(0x0598, 0x0250, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD3_CLK__UART4_CTS_B                           = IOMUX_PAD(0x0598, 0x0250, 1, 0x0844, 0, 0),
+	 MX6_PAD_SD3_CLK__ECSPI4_SCLK                           = IOMUX_PAD(0x0598, 0x0250, 2, 0x0740, 0, 0),
+	 MX6_PAD_SD3_CLK__AUDMUX_AUD6_RXFS                      = IOMUX_PAD(0x0598, 0x0250, 3, 0x0680, 0, 0),
+	 MX6_PAD_SD3_CLK__LCDIF2_VSYNC                          = IOMUX_PAD(0x0598, 0x0250, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD3_CLK__GPIO7_IO_0                            = IOMUX_PAD(0x0598, 0x0250, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD3_CLK__LCDIF2_BUSY                           = IOMUX_PAD(0x0598, 0x0250, 6, 0x07E4, 0, 0),
+	 MX6_PAD_SD3_CLK__TPSMP_HDATA_29                        = IOMUX_PAD(0x0598, 0x0250, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5            = IOMUX_PAD(0x0598, 0x0250, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD3_CMD__USDHC3_CMD                            = IOMUX_PAD(0x059C, 0x0254, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD3_CMD__UART4_TX                              = IOMUX_PAD(0x059C, 0x0254, 1, 0x0848, 0, 0),
+	 MX6_PAD_SD3_CMD__ECSPI4_MOSI                           = IOMUX_PAD(0x059C, 0x0254, 2, 0x0748, 0, 0),
+	 MX6_PAD_SD3_CMD__AUDMUX_AUD6_RXC                       = IOMUX_PAD(0x059C, 0x0254, 3, 0x067C, 0, 0),
+	 MX6_PAD_SD3_CMD__LCDIF2_HSYNC                          = IOMUX_PAD(0x059C, 0x0254, 4, 0x07E4, 1, 0),
+	 MX6_PAD_SD3_CMD__GPIO7_IO_1                            = IOMUX_PAD(0x059C, 0x0254, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD3_CMD__LCDIF2_RS                             = IOMUX_PAD(0x059C, 0x0254, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD3_CMD__TPSMP_HDATA_28                        = IOMUX_PAD(0x059C, 0x0254, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4            = IOMUX_PAD(0x059C, 0x0254, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD3_DATA0__USDHC3_DATA0                        = IOMUX_PAD(0x05A0, 0x0258, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA0__I2C4_SCL                            = IOMUX_PAD(0x05A0, 0x0258, IOMUX_CONFIG_SION | 1, 0x07C0, 0, 0),
+	 MX6_PAD_SD3_DATA0__ECSPI2_SS1                          = IOMUX_PAD(0x05A0, 0x0258, 2, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA0__AUDMUX_AUD6_RXD                     = IOMUX_PAD(0x05A0, 0x0258, 3, 0x0674, 0, 0),
+	 MX6_PAD_SD3_DATA0__LCDIF2_DATA_1                       = IOMUX_PAD(0x05A0, 0x0258, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA0__GPIO7_IO_2                          = IOMUX_PAD(0x05A0, 0x0258, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA0__DCIC1_OUT                           = IOMUX_PAD(0x05A0, 0x0258, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA0__TPSMP_HDATA_30                      = IOMUX_PAD(0x05A0, 0x0258, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA0__GPU_DEBUG_0                         = IOMUX_PAD(0x05A0, 0x0258, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0          = IOMUX_PAD(0x05A0, 0x0258, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD3_DATA1__USDHC3_DATA1                        = IOMUX_PAD(0x05A4, 0x025C, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA1__I2C4_SDA                            = IOMUX_PAD(0x05A4, 0x025C, IOMUX_CONFIG_SION | 1, 0x07C4, 0, 0),
+	 MX6_PAD_SD3_DATA1__ECSPI2_SS2                          = IOMUX_PAD(0x05A4, 0x025C, 2, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA1__AUDMUX_AUD6_TXC                     = IOMUX_PAD(0x05A4, 0x025C, 3, 0x0684, 0, 0),
+	 MX6_PAD_SD3_DATA1__LCDIF2_DATA_0                       = IOMUX_PAD(0x05A4, 0x025C, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA1__GPIO7_IO_3                          = IOMUX_PAD(0x05A4, 0x025C, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA1__DCIC2_OUT                           = IOMUX_PAD(0x05A4, 0x025C, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA1__TPSMP_HDATA_31                      = IOMUX_PAD(0x05A4, 0x025C, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA1__GPU_DEBUG_1                         = IOMUX_PAD(0x05A4, 0x025C, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1          = IOMUX_PAD(0x05A4, 0x025C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD3_DATA2__USDHC3_DATA2                        = IOMUX_PAD(0x05A8, 0x0260, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA2__UART4_RTS_B                         = IOMUX_PAD(0x05A8, 0x0260, 1, 0x0844, 1, 0),
+	 MX6_PAD_SD3_DATA2__ECSPI4_SS0                          = IOMUX_PAD(0x05A8, 0x0260, 2, 0x074C, 0, 0),
+	 MX6_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS                    = IOMUX_PAD(0x05A8, 0x0260, 3, 0x0688, 0, 0),
+	 MX6_PAD_SD3_DATA2__LCDIF2_CLK                          = IOMUX_PAD(0x05A8, 0x0260, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA2__GPIO7_IO_4                          = IOMUX_PAD(0x05A8, 0x0260, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA2__LCDIF2_WR_RWN                       = IOMUX_PAD(0x05A8, 0x0260, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA2__TPSMP_HDATA_26                      = IOMUX_PAD(0x05A8, 0x0260, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA2__GPU_DEBUG_2                         = IOMUX_PAD(0x05A8, 0x0260, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2          = IOMUX_PAD(0x05A8, 0x0260, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD3_DATA3__USDHC3_DATA3                        = IOMUX_PAD(0x05AC, 0x0264, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA3__UART4_RX                            = IOMUX_PAD(0x05AC, 0x0264, 1, 0x0848, 1, 0),
+	 MX6_PAD_SD3_DATA3__ECSPI4_MISO                         = IOMUX_PAD(0x05AC, 0x0264, 2, 0x0744, 0, 0),
+	 MX6_PAD_SD3_DATA3__AUDMUX_AUD6_TXD                     = IOMUX_PAD(0x05AC, 0x0264, 3, 0x0678, 0, 0),
+	 MX6_PAD_SD3_DATA3__LCDIF2_ENABLE                       = IOMUX_PAD(0x05AC, 0x0264, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA3__GPIO7_IO_5                          = IOMUX_PAD(0x05AC, 0x0264, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA3__LCDIF2_RD_E                         = IOMUX_PAD(0x05AC, 0x0264, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA3__TPSMP_HDATA_27                      = IOMUX_PAD(0x05AC, 0x0264, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA3__GPU_DEBUG_3                         = IOMUX_PAD(0x05AC, 0x0264, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3          = IOMUX_PAD(0x05AC, 0x0264, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD3_DATA4__USDHC3_DATA4                        = IOMUX_PAD(0x05B0, 0x0268, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA4__CAN2_RX                             = IOMUX_PAD(0x05B0, 0x0268, 1, 0x0690, 0, 0),
+	 MX6_PAD_SD3_DATA4__CANFD_RX2                           = IOMUX_PAD(0x05B0, 0x0268, 2, 0x0698, 0, 0),
+	 MX6_PAD_SD3_DATA4__UART3_RX                            = IOMUX_PAD(0x05B0, 0x0268, 3, 0x0840, 2, 0),
+	 MX6_PAD_SD3_DATA4__LCDIF2_DATA_3                       = IOMUX_PAD(0x05B0, 0x0268, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA4__GPIO7_IO_6                          = IOMUX_PAD(0x05B0, 0x0268, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN                = IOMUX_PAD(0x05B0, 0x0268, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA4__TPSMP_HTRANS_1                      = IOMUX_PAD(0x05B0, 0x0268, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA4__GPU_DEBUG_4                         = IOMUX_PAD(0x05B0, 0x0268, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0             = IOMUX_PAD(0x05B0, 0x0268, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD3_DATA5__USDHC3_DATA5                        = IOMUX_PAD(0x05B4, 0x026C, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA5__CAN1_TX                             = IOMUX_PAD(0x05B4, 0x026C, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA5__CANFD_TX1                           = IOMUX_PAD(0x05B4, 0x026C, 2, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA5__UART3_TX                            = IOMUX_PAD(0x05B4, 0x026C, 3, 0x0840, 3, 0),
+	 MX6_PAD_SD3_DATA5__LCDIF2_DATA_2                       = IOMUX_PAD(0x05B4, 0x026C, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA5__GPIO7_IO_7                          = IOMUX_PAD(0x05B4, 0x026C, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT               = IOMUX_PAD(0x05B4, 0x026C, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA5__SIM_M_HWRITE                        = IOMUX_PAD(0x05B4, 0x026C, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA5__GPU_DEBUG_5                         = IOMUX_PAD(0x05B4, 0x026C, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1             = IOMUX_PAD(0x05B4, 0x026C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD3_DATA6__USDHC3_DATA6                        = IOMUX_PAD(0x05B8, 0x0270, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA6__CAN2_TX                             = IOMUX_PAD(0x05B8, 0x0270, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA6__CANFD_TX2                           = IOMUX_PAD(0x05B8, 0x0270, 2, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA6__UART3_RTS_B                         = IOMUX_PAD(0x05B8, 0x0270, 3, 0x083C, 2, 0),
+	 MX6_PAD_SD3_DATA6__LCDIF2_DATA_4                       = IOMUX_PAD(0x05B8, 0x0270, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA6__GPIO7_IO_8                          = IOMUX_PAD(0x05B8, 0x0270, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT               = IOMUX_PAD(0x05B8, 0x0270, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA6__TPSMP_HTRANS_0                      = IOMUX_PAD(0x05B8, 0x0270, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA6__GPU_DEBUG_7                         = IOMUX_PAD(0x05B8, 0x0270, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7          = IOMUX_PAD(0x05B8, 0x0270, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD3_DATA7__USDHC3_DATA7                        = IOMUX_PAD(0x05BC, 0x0274, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA7__CAN1_RX                             = IOMUX_PAD(0x05BC, 0x0274, 1, 0x068C, 0, 0),
+	 MX6_PAD_SD3_DATA7__CANFD_RX1                           = IOMUX_PAD(0x05BC, 0x0274, 2, 0x0694, 0, 0),
+	 MX6_PAD_SD3_DATA7__UART3_CTS_B                         = IOMUX_PAD(0x05BC, 0x0274, 3, 0x083C, 3, 0),
+	 MX6_PAD_SD3_DATA7__LCDIF2_DATA_5                       = IOMUX_PAD(0x05BC, 0x0274, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA7__GPIO7_IO_9                          = IOMUX_PAD(0x05BC, 0x0274, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN                = IOMUX_PAD(0x05BC, 0x0274, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA7__TPSMP_HDATA_DIR                     = IOMUX_PAD(0x05BC, 0x0274, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA7__GPU_DEBUG_6                         = IOMUX_PAD(0x05BC, 0x0274, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2          = IOMUX_PAD(0x05BC, 0x0274, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD4_CLK__USDHC4_CLK                            = IOMUX_PAD(0x05C0, 0x0278, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CLK__RAWNAND_DATA15                        = IOMUX_PAD(0x05C0, 0x0278, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CLK__ECSPI2_MISO                           = IOMUX_PAD(0x05C0, 0x0278, 2, 0x0724, 1, 0),
+	 MX6_PAD_SD4_CLK__AUDMUX_AUD3_RXFS                      = IOMUX_PAD(0x05C0, 0x0278, 3, 0x0638, 0, 0),
+	 MX6_PAD_SD4_CLK__LCDIF2_DATA_13                        = IOMUX_PAD(0x05C0, 0x0278, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CLK__GPIO6_IO_12                           = IOMUX_PAD(0x05C0, 0x0278, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CLK__ECSPI3_SS2                            = IOMUX_PAD(0x05C0, 0x0278, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CLK__TPSMP_HDATA_20                        = IOMUX_PAD(0x05C0, 0x0278, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CLK__VDEC_DEBUG_12                         = IOMUX_PAD(0x05C0, 0x0278, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL          = IOMUX_PAD(0x05C0, 0x0278, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD4_CMD__USDHC4_CMD                            = IOMUX_PAD(0x05C4, 0x027C, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CMD__RAWNAND_DATA14                        = IOMUX_PAD(0x05C4, 0x027C, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CMD__ECSPI2_MOSI                           = IOMUX_PAD(0x05C4, 0x027C, 2, 0x0728, 1, 0),
+	 MX6_PAD_SD4_CMD__AUDMUX_AUD3_RXC                       = IOMUX_PAD(0x05C4, 0x027C, 3, 0x0634, 0, 0),
+	 MX6_PAD_SD4_CMD__LCDIF2_DATA_14                        = IOMUX_PAD(0x05C4, 0x027C, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CMD__GPIO6_IO_13                           = IOMUX_PAD(0x05C4, 0x027C, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CMD__ECSPI3_SS1                            = IOMUX_PAD(0x05C4, 0x027C, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CMD__TPSMP_HDATA_19                        = IOMUX_PAD(0x05C4, 0x027C, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CMD__VDEC_DEBUG_11                         = IOMUX_PAD(0x05C4, 0x027C, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN                   = IOMUX_PAD(0x05C4, 0x027C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD4_DATA0__USDHC4_DATA0                        = IOMUX_PAD(0x05C8, 0x0280, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA0__RAWNAND_DATA10                      = IOMUX_PAD(0x05C8, 0x0280, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA0__ECSPI2_SS0                          = IOMUX_PAD(0x05C8, 0x0280, 2, 0x072C, 1, 0),
+	 MX6_PAD_SD4_DATA0__AUDMUX_AUD3_RXD                     = IOMUX_PAD(0x05C8, 0x0280, 3, 0x062C, 0, 0),
+	 MX6_PAD_SD4_DATA0__LCDIF2_DATA_12                      = IOMUX_PAD(0x05C8, 0x0280, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA0__GPIO6_IO_14                         = IOMUX_PAD(0x05C8, 0x0280, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA0__ECSPI3_SS3                          = IOMUX_PAD(0x05C8, 0x0280, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA0__TPSMP_HDATA_21                      = IOMUX_PAD(0x05C8, 0x0280, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA0__VDEC_DEBUG_13                       = IOMUX_PAD(0x05C8, 0x0280, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA0__SDMA_DEBUG_MODE                     = IOMUX_PAD(0x05C8, 0x0280, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD4_DATA1__USDHC4_DATA1                        = IOMUX_PAD(0x05CC, 0x0284, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA1__RAWNAND_DATA11                      = IOMUX_PAD(0x05CC, 0x0284, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA1__ECSPI2_SCLK                         = IOMUX_PAD(0x05CC, 0x0284, 2, 0x0720, 1, 0),
+	 MX6_PAD_SD4_DATA1__AUDMUX_AUD3_TXC                     = IOMUX_PAD(0x05CC, 0x0284, 3, 0x063C, 0, 0),
+	 MX6_PAD_SD4_DATA1__LCDIF2_DATA_11                      = IOMUX_PAD(0x05CC, 0x0284, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA1__GPIO6_IO_15                         = IOMUX_PAD(0x05CC, 0x0284, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA1__ECSPI3_RDY                          = IOMUX_PAD(0x05CC, 0x0284, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA1__TPSMP_HDATA_22                      = IOMUX_PAD(0x05CC, 0x0284, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA1__VDEC_DEBUG_14                       = IOMUX_PAD(0x05CC, 0x0284, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR                = IOMUX_PAD(0x05CC, 0x0284, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD4_DATA2__USDHC4_DATA2                        = IOMUX_PAD(0x05D0, 0x0288, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA2__RAWNAND_DATA12                      = IOMUX_PAD(0x05D0, 0x0288, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA2__I2C2_SDA                            = IOMUX_PAD(0x05D0, 0x0288, IOMUX_CONFIG_SION | 2, 0x07B4, 0, 0),
+	 MX6_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS                    = IOMUX_PAD(0x05D0, 0x0288, 3, 0x0640, 0, 0),
+	 MX6_PAD_SD4_DATA2__LCDIF2_DATA_10                      = IOMUX_PAD(0x05D0, 0x0288, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA2__GPIO6_IO_16                         = IOMUX_PAD(0x05D0, 0x0288, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA2__ECSPI2_SS3                          = IOMUX_PAD(0x05D0, 0x0288, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA2__TPSMP_HDATA_23                      = IOMUX_PAD(0x05D0, 0x0288, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA2__VDEC_DEBUG_15                       = IOMUX_PAD(0x05D0, 0x0288, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB                  = IOMUX_PAD(0x05D0, 0x0288, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD4_DATA3__USDHC4_DATA3                        = IOMUX_PAD(0x05D4, 0x028C, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA3__RAWNAND_DATA13                      = IOMUX_PAD(0x05D4, 0x028C, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA3__I2C2_SCL                            = IOMUX_PAD(0x05D4, 0x028C, IOMUX_CONFIG_SION | 2, 0x07B0, 0, 0),
+	 MX6_PAD_SD4_DATA3__AUDMUX_AUD3_TXD                     = IOMUX_PAD(0x05D4, 0x028C, 3, 0x0630, 0, 0),
+	 MX6_PAD_SD4_DATA3__LCDIF2_DATA_9                       = IOMUX_PAD(0x05D4, 0x028C, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA3__GPIO6_IO_17                         = IOMUX_PAD(0x05D4, 0x028C, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA3__ECSPI2_RDY                          = IOMUX_PAD(0x05D4, 0x028C, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA3__TPSMP_HDATA_24                      = IOMUX_PAD(0x05D4, 0x028C, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA3__VDEC_DEBUG_16                       = IOMUX_PAD(0x05D4, 0x028C, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS            = IOMUX_PAD(0x05D4, 0x028C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD4_DATA4__USDHC4_DATA4                        = IOMUX_PAD(0x05D8, 0x0290, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA4__RAWNAND_DATA09                      = IOMUX_PAD(0x05D8, 0x0290, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA4__UART5_RX                            = IOMUX_PAD(0x05D8, 0x0290, 2, 0x0850, 0, 0),
+	 MX6_PAD_SD4_DATA4__ECSPI3_SCLK                         = IOMUX_PAD(0x05D8, 0x0290, 3, 0x0730, 0, 0),
+	 MX6_PAD_SD4_DATA4__LCDIF2_DATA_8                       = IOMUX_PAD(0x05D8, 0x0290, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA4__GPIO6_IO_18                         = IOMUX_PAD(0x05D8, 0x0290, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA4__SPDIF_OUT                           = IOMUX_PAD(0x05D8, 0x0290, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA4__TPSMP_HDATA_16                      = IOMUX_PAD(0x05D8, 0x0290, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA4__USB_OTG_HOST_MODE                   = IOMUX_PAD(0x05D8, 0x0290, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE           = IOMUX_PAD(0x05D8, 0x0290, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD4_DATA5__USDHC4_DATA5                        = IOMUX_PAD(0x05DC, 0x0294, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA5__RAWNAND_CE2_B                       = IOMUX_PAD(0x05DC, 0x0294, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA5__UART5_TX                            = IOMUX_PAD(0x05DC, 0x0294, 2, 0x0850, 1, 0),
+	 MX6_PAD_SD4_DATA5__ECSPI3_MOSI                         = IOMUX_PAD(0x05DC, 0x0294, 3, 0x0738, 0, 0),
+	 MX6_PAD_SD4_DATA5__LCDIF2_DATA_7                       = IOMUX_PAD(0x05DC, 0x0294, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA5__GPIO6_IO_19                         = IOMUX_PAD(0x05DC, 0x0294, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA5__SPDIF_IN                            = IOMUX_PAD(0x05DC, 0x0294, 6, 0x0824, 0, 0),
+	 MX6_PAD_SD4_DATA5__TPSMP_HDATA_17                      = IOMUX_PAD(0x05DC, 0x0294, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA5__VDEC_DEBUG_9                        = IOMUX_PAD(0x05DC, 0x0294, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0          = IOMUX_PAD(0x05DC, 0x0294, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD4_DATA6__USDHC4_DATA6                        = IOMUX_PAD(0x05E0, 0x0298, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA6__RAWNAND_CE3_B                       = IOMUX_PAD(0x05E0, 0x0298, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA6__UART5_RTS_B                         = IOMUX_PAD(0x05E0, 0x0298, 2, 0x084C, 0, 0),
+	 MX6_PAD_SD4_DATA6__ECSPI3_MISO                         = IOMUX_PAD(0x05E0, 0x0298, 3, 0x0734, 0, 0),
+	 MX6_PAD_SD4_DATA6__LCDIF2_DATA_6                       = IOMUX_PAD(0x05E0, 0x0298, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA6__GPIO6_IO_20                         = IOMUX_PAD(0x05E0, 0x0298, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA6__USDHC4_WP                           = IOMUX_PAD(0x05E0, 0x0298, 6, 0x0878, 0, 0),
+	 MX6_PAD_SD4_DATA6__TPSMP_HDATA_18                      = IOMUX_PAD(0x05E0, 0x0298, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA6__VDEC_DEBUG_10                       = IOMUX_PAD(0x05E0, 0x0298, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1          = IOMUX_PAD(0x05E0, 0x0298, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD4_DATA7__USDHC4_DATA7                        = IOMUX_PAD(0x05E4, 0x029C, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA7__RAWNAND_DATA08                      = IOMUX_PAD(0x05E4, 0x029C, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA7__UART5_CTS_B                         = IOMUX_PAD(0x05E4, 0x029C, 2, 0x084C, 1, 0),
+	 MX6_PAD_SD4_DATA7__ECSPI3_SS0                          = IOMUX_PAD(0x05E4, 0x029C, 3, 0x073C, 0, 0),
+	 MX6_PAD_SD4_DATA7__LCDIF2_DATA_15                      = IOMUX_PAD(0x05E4, 0x029C, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA7__GPIO6_IO_21                         = IOMUX_PAD(0x05E4, 0x029C, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA7__USDHC4_CD_B                         = IOMUX_PAD(0x05E4, 0x029C, 6, 0x0874, 0, 0),
+	 MX6_PAD_SD4_DATA7__TPSMP_HDATA_15                      = IOMUX_PAD(0x05E4, 0x029C, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA7__USB_OTG_PWR_WAKE                    = IOMUX_PAD(0x05E4, 0x029C, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD4_DATA7__SDMA_DEBUG_YIELD                    = IOMUX_PAD(0x05E4, 0x029C, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_SD4_RESET_B__USDHC4_RESET_B                    = IOMUX_PAD(0x05E8, 0x02A0, 0, 0x0000, 0, 0),
+	 MX6_PAD_SD4_RESET_B__RAWNAND_DQS                       = IOMUX_PAD(0x05E8, 0x02A0, 1, 0x0000, 0, 0),
+	 MX6_PAD_SD4_RESET_B__USDHC4_RESET                      = IOMUX_PAD(0x05E8, 0x02A0, 2, 0x0000, 0, 0),
+	 MX6_PAD_SD4_RESET_B__AUDMUX_MCLK                       = IOMUX_PAD(0x05E8, 0x02A0, 3, 0x0000, 0, 0),
+	 MX6_PAD_SD4_RESET_B__LCDIF2_RESET                      = IOMUX_PAD(0x05E8, 0x02A0, 4, 0x0000, 0, 0),
+	 MX6_PAD_SD4_RESET_B__GPIO6_IO_22                       = IOMUX_PAD(0x05E8, 0x02A0, 5, 0x0000, 0, 0),
+	 MX6_PAD_SD4_RESET_B__LCDIF2_CS                         = IOMUX_PAD(0x05E8, 0x02A0, 6, 0x0000, 0, 0),
+	 MX6_PAD_SD4_RESET_B__TPSMP_HDATA_25                    = IOMUX_PAD(0x05E8, 0x02A0, 7, 0x0000, 0, 0),
+	 MX6_PAD_SD4_RESET_B__VDEC_DEBUG_17                     = IOMUX_PAD(0x05E8, 0x02A0, 8, 0x0000, 0, 0),
+	 MX6_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2           = IOMUX_PAD(0x05E8, 0x02A0, 9, 0x0000, 0, 0),
+
+	 MX6_PAD_USB_H_DATA__USB_H_DATA                         = IOMUX_PAD(0x05EC, 0x02A4, 0, 0x0000, 0, 0),
+	 MX6_PAD_USB_H_DATA__PWM2_OUT                           = IOMUX_PAD(0x05EC, 0x02A4, 1, 0x0000, 0, 0),
+	 MX6_PAD_USB_H_DATA__ANATOP_24M_OUT                     = IOMUX_PAD(0x05EC, 0x02A4, 2, 0x0000, 0, 0),
+	 MX6_PAD_USB_H_DATA__I2C4_SDA                           = IOMUX_PAD(0x05EC, 0x02A4, IOMUX_CONFIG_SION | 3, 0x07C4, 1, 0),
+	 MX6_PAD_USB_H_DATA__WDOG3_WDOG_B                       = IOMUX_PAD(0x05EC, 0x02A4, 4, 0x0000, 0, 0),
+	 MX6_PAD_USB_H_DATA__GPIO7_IO_10                        = IOMUX_PAD(0x05EC, 0x02A4, 5, 0x0000, 0, 0),
+
+	 MX6_PAD_USB_H_STROBE__USB_H_STROBE                     = IOMUX_PAD(0x05F0, 0x02A8, 0, 0x0000, 0, 0),
+	 MX6_PAD_USB_H_STROBE__PWM1_OUT                         = IOMUX_PAD(0x05F0, 0x02A8, 1, 0x0000, 0, 0),
+	 MX6_PAD_USB_H_STROBE__ANATOP_32K_OUT                   = IOMUX_PAD(0x05F0, 0x02A8, 2, 0x0000, 0, 0),
+	 MX6_PAD_USB_H_STROBE__I2C4_SCL                         = IOMUX_PAD(0x05F0, 0x02A8, IOMUX_CONFIG_SION | 3, 0x07C0, 1, 0),
+	 MX6_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB             = IOMUX_PAD(0x05F0, 0x02A8, 4, 0x0000, 0, 0),
+	 MX6_PAD_USB_H_STROBE__GPIO7_IO_11                      = IOMUX_PAD(0x05F0, 0x02A8, 5, 0x0000, 0, 0),
+};
+#endif  /* __ASM_ARCH_MX6_ MX6_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h b/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h
new file mode 100644
index 0000000..7ff2016
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __MX6SX_RDC_H__
+#define __MX6SX_RDC_H__
+
+#define RDC_SEMA_PROC_ID 2  /* The processor ID for main CPU */
+
+enum {
+	RDC_PER_PWM1 = 0,
+	RDC_PER_PWM2,
+	RDC_PER_PWM3,
+	RDC_PER_PWM4,
+	RDC_PER_CAN1,
+	RDC_PER_CAN2,
+	RDC_PER_GPT,
+	RDC_PER_GPIO1,
+	RDC_PER_GPIO2,
+	RDC_PER_GPIO3,
+	RDC_PER_GPIO4,
+	RDC_PER_GPIO5,
+	RDC_PER_GPIO6,
+	RDC_PER_GPIO7,
+	RDC_PER_KPP,
+	RDC_PER_WDOG1,
+	RDC_PER_WODG2,
+	RDC_PER_CCM,
+	RDC_PER_ANATOPDIG,
+	RDC_PER_SNVSHP,
+	RDC_PER_EPIT1,
+	RDC_PER_EPIT2,
+	RDC_PER_SRC,
+	RDC_PER_GPC,
+	RDC_PER_IOMUXC,
+	RDC_PER_IOMUXCGPR,
+	RDC_PER_CANFD1,
+	RDC_PER_SDMA,
+	RDC_PER_CANFD2,
+	RDC_PER_SEMA1,
+	RDC_PER_SEMA2,
+	RDC_PER_RDC,
+	RDC_PER_AIPSTZ1_GE1,
+	RDC_PER_AIPSTZ2_GE2,
+	RDC_PER_USBO2H_PL301,
+	RDC_PER_USBO2H_USB,
+	RDC_PER_ENET1,
+	RDC_PER_MLB25,
+	RDC_PER_USDHC1,
+	RDC_PER_USDHC2,
+	RDC_PER_USDHC3,
+	RDC_PER_USDHC4,
+	RDC_PER_I2C1,
+	RDC_PER_I2C2,
+	RDC_PER_I2C3,
+	RDC_PER_ROMCP,
+	RDC_PER_MMDC,
+	RDC_PER_ENET2,
+	RDC_PER_EIM,
+	RDC_PER_OCOTP,
+	RDC_PER_CSU,
+	RDC_PER_PERFMON1,
+	RDC_PER_PERFMON2,
+	RDC_PER_AXIMON,
+	RDC_PER_TZASC1,
+	RDC_PER_SAI1,
+	RDC_PER_AUDMUX,
+	RDC_PER_SAI2,
+	RDC_PER_QSPI1,
+	RDC_PER_QSPI2,
+	RDC_PER_UART2,
+	RDC_PER_UART3,
+	RDC_PER_UART4,
+	RDC_PER_UART5,
+	RDC_PER_I2C4,
+	RDC_PER_QOSC,
+	RDC_PER_CAAM,
+	RDC_PER_DAP,
+	RDC_PER_ADC1,
+	RDC_PER_ADC2,
+	RDC_PER_WDOG3,
+	RDC_PER_ECSPI5,
+	RDC_PER_SEMA4,
+	RDC_PER_MUPORT1,
+	RDC_PER_CANFD_CPU,
+	RDC_PER_MUPORT2,
+	RDC_PER_UART6,
+	RDC_PER_PWM5,
+	RDC_PER_PWM6,
+	RDC_PER_PWM7,
+	RDC_PER_PWM8,
+	RDC_PER_AIPSTZ3_GE0,
+	RDC_PER_AIPSTZ3_GE1,
+	RDC_PER_RESERVED1,
+	RDC_PER_SPDIF,
+	RDC_PER_ECSPI1,
+	RDC_PER_ECSPI2,
+	RDC_PER_ECSPI3,
+	RDC_PER_ECSPI4,
+	RDC_PER_RESERVED2,
+	RDC_PER_RESERVED3,
+	RDC_PER_UART1,
+	RDC_PER_ESAI,
+	RDC_PER_SSI1,
+	RDC_PER_SSI2,
+	RDC_PER_SSI3,
+	RDC_PER_ASRC,
+	RDC_PER_RESERVED4,
+	RDC_PER_SPBA_MA,
+	RDC_PER_GIS,
+	RDC_PER_DCIC1,
+	RDC_PER_DCIC2,
+	RDC_PER_CSI1,
+	RDC_PER_PXP,
+	RDC_PER_CSI2,
+	RDC_PER_LCDIF1,
+	RDC_PER_LCDIF2,
+	RDC_PER_VADC,
+	RDC_PER_VDEC,
+	RDC_PER_SPBA_DISPLAYMIX,
+};
+
+enum {
+	RDC_MA_A9_L2CACHE = 0,
+	RDC_MA_M4,
+	RDC_MA_GPU,
+	RDC_MA_CSI1,
+	RDC_MA_CSI2,
+	RDC_MA_LCDIF1,
+	RDC_MA_LCDIF2,
+	RDC_MA_PXP,
+	RDC_MA_PCIE_CTRL,
+	RDC_MA_DAP,
+	RDC_MA_CAAM,
+	RDC_MA_SDMA_PERI,
+	RDC_MA_SDMA_BURST,
+	RDC_MA_APBHDMA,
+	RDC_MA_RAWNAND,
+	RDC_MA_USDHC1,
+	RDC_MA_USDHC2,
+	RDC_MA_USDHC3,
+	RDC_MA_USDHC4,
+	RDC_MA_USB,
+	RDC_MA_MLB,
+	RDC_MA_TEST,
+	RDC_MA_ENET1_TX,
+	RDC_MA_ENET1_RX,
+	RDC_MA_ENET2_TX,
+	RDC_MA_ENET2_RX,
+	RDC_MA_SDMA,
+};
+
+#endif	/* __MX6SX_RDC_H__*/
diff --git a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
new file mode 100644
index 0000000..9977958
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_MX6UL_DDR_H__
+#define __ASM_ARCH_MX6UL_DDR_H__
+
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#error "wrong CPU"
+#endif
+
+#define MX6_IOM_DRAM_DQM0	0x020e0244
+#define MX6_IOM_DRAM_DQM1	0x020e0248
+
+#define MX6_IOM_DRAM_RAS	0x020e024c
+#define MX6_IOM_DRAM_CAS	0x020e0250
+#define MX6_IOM_DRAM_CS0	0x020e0254
+#define MX6_IOM_DRAM_CS1	0x020e0258
+#define MX6_IOM_DRAM_SDWE_B	0x020e025c
+#define MX6_IOM_DRAM_SDODT0	0x020e0260
+#define MX6_IOM_DRAM_SDODT1	0x020e0264
+#define MX6_IOM_DRAM_SDBA0	0x020e0268
+#define MX6_IOM_DRAM_SDBA1	0x020e026c
+#define MX6_IOM_DRAM_SDBA2	0x020e0270
+#define MX6_IOM_DRAM_SDCKE0	0x020e0274
+#define MX6_IOM_DRAM_SDCKE1	0x020e0278
+#define MX6_IOM_DRAM_SDCLK_0	0x020e027c
+#define MX6_IOM_DRAM_SDQS0	0x020e0280
+#define MX6_IOM_DRAM_SDQS1	0x020e0284
+#define MX6_IOM_DRAM_RESET	0x020e0288
+
+#define MX6_IOM_GRP_ADDDS	0x020e0490
+#define MX6_IOM_DDRMODE_CTL	0x020e0494
+#define MX6_IOM_GRP_B0DS	0x020e0498
+#define MX6_IOM_GRP_DDRPK	0x020e049c
+#define MX6_IOM_GRP_CTLDS	0x020e04a0
+#define MX6_IOM_GRP_B1DS	0x020e04a4
+#define MX6_IOM_GRP_DDRHYS	0x020e04a8
+#define MX6_IOM_GRP_DDRPKE	0x020e04ac
+#define MX6_IOM_GRP_DDRMODE	0x020e04b0
+#define MX6_IOM_GRP_DDR_TYPE	0x020e04b4
+
+#endif	/*__ASM_ARCH_MX6SX_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6ul_pins.h b/arch/arm/include/asm/arch-mx6/mx6ul_pins.h
new file mode 100644
index 0000000..031b4a0
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6ul_pins.h
@@ -0,0 +1,1064 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_IMX6UL_PINS_H__
+#define __ASM_ARCH_IMX6UL_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+
+	MX6_PAD_BOOT_MODE0__GPIO5_IO10	                        = IOMUX_PAD(0x02A0, 0x0014, 5, 0x0000, 0, 0),
+	MX6_PAD_BOOT_MODE1__GPIO5_IO11	                        = IOMUX_PAD(0x02A4, 0x0018, 5, 0x0000, 0, 0),
+	/*
+	 * The TAMPER Pin can be used for GPIO, which depends on
+	 * fusemap TAMPER_PIN_DISABLE[1:0] settings.
+	 */
+	MX6_PAD_SNVS_TAMPER0__GPIO5_IO00                       = IOMUX_PAD(0x02A8, 0x001C, 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER1__GPIO5_IO01                       = IOMUX_PAD(0x02AC, 0x0020, 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER2__GPIO5_IO02                       = IOMUX_PAD(0x02B0, 0x0024, 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER3__GPIO5_IO03                       = IOMUX_PAD(0x02B4, 0x0028, 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER4__GPIO5_IO04                       = IOMUX_PAD(0x02B8, 0x002C, 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER5__GPIO5_IO05                       = IOMUX_PAD(0x02BC, 0x0030, 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER6__GPIO5_IO06                       = IOMUX_PAD(0x02C0, 0x0034, 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER7__GPIO5_IO07                       = IOMUX_PAD(0x02C4, 0x0038, 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER8__GPIO5_IO08                       = IOMUX_PAD(0x02C8, 0x003C, 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER9__GPIO5_IO09                       = IOMUX_PAD(0x02CC, 0x0040, 5, 0x0000, 0, 0),
+
+	MX6_PAD_JTAG_MOD__SJC_MOD                              = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_MOD__GPT2_CLK                             = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0),
+	MX6_PAD_JTAG_MOD__SPDIF_OUT                            = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0),
+	MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M                    = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0),
+	MX6_PAD_JTAG_MOD__CCM_PMIC_RDY                         = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0),
+	MX6_PAD_JTAG_MOD__GPIO1_IO10                           = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00                     = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0),
+
+	MX6_PAD_JTAG_TMS__SJC_TMS                              = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TMS__GPT2_CAPTURE1                        = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0),
+	MX6_PAD_JTAG_TMS__SAI2_MCLK                            = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0),
+	MX6_PAD_JTAG_TMS__CCM_CLKO1                            = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TMS__CCM_WAIT                             = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TMS__GPIO1_IO11                           = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01                     = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0),
+	MX6_PAD_JTAG_TMS__EPIT1_OUT                            = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0),
+
+	MX6_PAD_JTAG_TDO__SJC_TDO                              = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDO__GPT2_CAPTURE2                        = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0),
+	MX6_PAD_JTAG_TDO__SAI2_TX_SYNC                         = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0),
+	MX6_PAD_JTAG_TDO__CCM_CLKO2                            = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDO__CCM_STOP                             = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDO__GPIO1_IO12                           = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDO__MQS_RIGHT                            = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDO__EPIT2_OUT                            = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_JTAG_TDI__SJC_TDI                              = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDI__GPT2_COMPARE1                        = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDI__SAI2_TX_BCLK                         = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0),
+	MX6_PAD_JTAG_TDI__PWM6_OUT                             = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDI__GPIO1_IO13                           = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDI__MQS_LEFT                             = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL                      = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0),
+
+	MX6_PAD_JTAG_TCK__SJC_TCK                              = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TCK__GPT2_COMPARE2                        = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TCK__SAI2_RX_DATA                         = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0),
+	MX6_PAD_JTAG_TCK__PWM7_OUT                             = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TCK__GPIO1_IO14                           = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL                      = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0),
+
+	MX6_PAD_JTAG_TRST_B__SJC_TRSTB                         = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3                     = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA                      = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRST_B__PWM8_OUT                          = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRST_B__GPIO1_IO15                        = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS                  = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO00__I2C2_SCL                           = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0),
+	MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1                      = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0),
+	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID                     = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0),
+	MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1                     = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0),
+	MX6_PAD_GPIO1_IO00__MQS_RIGHT                          = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO00__GPIO1_IO00                         = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN               = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET                   = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B                       = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO01__I2C2_SDA                           = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0),
+	MX6_PAD_GPIO1_IO01__GPT1_COMPARE1                      = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO01__USB_OTG1_OC                        = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0),
+	MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2                     = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0),
+	MX6_PAD_GPIO1_IO01__MQS_LEFT                           = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO01__GPIO1_IO01                         = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT              = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET                    = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B                       = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO02__I2C1_SCL                           = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0),
+	MX6_PAD_GPIO1_IO02__GPT1_COMPARE2                      = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__USB_OTG2_PWR                       = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M                  = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__USDHC1_WP                          = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0),
+	MX6_PAD_GPIO1_IO02__GPIO1_IO02                         = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00                   = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0),
+	MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET                   = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__UART1_DCE_TX                       = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__UART1_DTE_RX                       = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0),
+
+	MX6_PAD_GPIO1_IO03__I2C1_SDA                           = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0),
+	MX6_PAD_GPIO1_IO03__GPT1_COMPARE3                      = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO03__USB_OTG2_OC                        = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0),
+	MX6_PAD_GPIO1_IO03__USDHC1_CD_B                        = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0),
+	MX6_PAD_GPIO1_IO03__GPIO1_IO03                         = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK                    = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK                     = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO03__UART1_DCE_RX                       = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0),
+	MX6_PAD_GPIO1_IO03__UART1_DTE_TX                       = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1                     = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0),
+	MX6_PAD_GPIO1_IO04__PWM3_OUT                           = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__USB_OTG1_PWR                       = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__USDHC1_RESET_B                     = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__GPIO1_IO04                         = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN               = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__UART5_DCE_TX                       = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__UART5_DTE_RX                       = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0),
+
+	MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2                     = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0),
+	MX6_PAD_GPIO1_IO05__PWM4_OUT                           = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID                     = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0),
+	MX6_PAD_GPIO1_IO05__CSI_FIELD                          = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0),
+	MX6_PAD_GPIO1_IO05__USDHC1_VSELECT                     = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO05__GPIO1_IO05                         = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT              = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO05__UART5_DCE_RX                       = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0),
+	MX6_PAD_GPIO1_IO05__UART5_DTE_TX                       = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO                         = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0),
+	MX6_PAD_GPIO1_IO06__ENET2_MDIO                         = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0),
+	MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE                   = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__CSI_MCLK                           = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__USDHC2_WP                          = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0),
+	MX6_PAD_GPIO1_IO06__GPIO1_IO06                         = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__CCM_WAIT                           = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__CCM_REF_EN_B                       = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__UART1_DCE_CTS                      = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__UART1_DTE_RTS                      = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0),
+
+	MX6_PAD_GPIO1_IO07__ENET1_MDC                          = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO07__ENET2_MDC                          = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE                  = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO07__CSI_PIXCLK                         = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0),
+	MX6_PAD_GPIO1_IO07__USDHC2_CD_B                        = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0),
+	MX6_PAD_GPIO1_IO07__GPIO1_IO07                         = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO07__CCM_STOP                           = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO07__UART1_DCE_RTS                      = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0),
+	MX6_PAD_GPIO1_IO07__UART1_DTE_CTS                      = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO08__PWM1_OUT                           = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B                       = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO08__SPDIF_OUT                          = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO08__CSI_VSYNC                          = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0),
+	MX6_PAD_GPIO1_IO08__USDHC2_VSELECT                     = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO08__GPIO1_IO08                         = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY                       = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0),
+	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS                      = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0),
+	MX6_PAD_GPIO1_IO08__UART5_DTE_CTS                      = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO09__PWM2_OUT                           = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY                     = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__SPDIF_IN                           = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0),
+	MX6_PAD_GPIO1_IO09__CSI_HSYNC                          = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0),
+	MX6_PAD_GPIO1_IO09__USDHC2_RESET_B                     = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__GPIO1_IO09                         = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__USDHC1_RESET_B                     = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS                      = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__UART5_DTE_RTS                      = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0),
+
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX                    = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART1_TX_DATA__UART1_DTE_RX                    = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0),
+	MX6_PAD_UART1_TX_DATA__ENET1_RDATA02                   = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0),
+	MX6_PAD_UART1_TX_DATA__I2C3_SCL                        = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0),
+	MX6_PAD_UART1_TX_DATA__CSI_DATA02                      = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0),
+	MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1                   = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0),
+	MX6_PAD_UART1_TX_DATA__GPIO1_IO16                      = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0),
+	MX6_PAD_UART1_TX_DATA__SPDIF_OUT                       = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0),
+
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX                    = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0),
+
+	MX6_PAD_UART1_RX_DATA__UART1_DTE_TX                    = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0),
+	MX6_PAD_UART1_RX_DATA__ENET1_RDATA03                   = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0),
+	MX6_PAD_UART1_RX_DATA__I2C3_SDA                        = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0),
+	MX6_PAD_UART1_RX_DATA__CSI_DATA03                      = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0),
+	MX6_PAD_UART1_RX_DATA__GPT1_CLK                        = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0),
+	MX6_PAD_UART1_RX_DATA__GPIO1_IO17                      = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0),
+	MX6_PAD_UART1_RX_DATA__SPDIF_IN                        = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0),
+
+	MX6_PAD_UART1_CTS_B__UART1_DCE_CTS                     = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART1_CTS_B__UART1_DTE_RTS                     = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0),
+	MX6_PAD_UART1_CTS_B__ENET1_RX_CLK                      = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0),
+	MX6_PAD_UART1_CTS_B__USDHC1_WP                         = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0),
+	MX6_PAD_UART1_CTS_B__CSI_DATA04                        = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0),
+	MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN              = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0),
+	MX6_PAD_UART1_CTS_B__GPIO1_IO18                        = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0),
+	MX6_PAD_UART1_CTS_B__USDHC2_WP                         = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0),
+
+	MX6_PAD_UART1_RTS_B__UART1_DCE_RTS                     = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0),
+
+	MX6_PAD_UART1_RTS_B__UART1_DTE_CTS                     = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0),
+	MX6_PAD_UART1_RTS_B__ENET1_TX_ER                       = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0),
+	MX6_PAD_UART1_RTS_B__USDHC1_CD_B                       = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0),
+	MX6_PAD_UART1_RTS_B__CSI_DATA05                        = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0),
+	MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT             = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0),
+	MX6_PAD_UART1_RTS_B__GPIO1_IO19                        = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0),
+	MX6_PAD_UART1_RTS_B__USDHC2_CD_B                       = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0),
+
+	MX6_PAD_UART2_TX_DATA__UART2_DCE_TX                    = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART2_TX_DATA__UART2_DTE_RX                    = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0),
+	MX6_PAD_UART2_TX_DATA__ENET1_TDATA02                   = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0),
+	MX6_PAD_UART2_TX_DATA__I2C4_SCL                        = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0),
+	MX6_PAD_UART2_TX_DATA__CSI_DATA06                      = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0),
+	MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1                   = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0),
+	MX6_PAD_UART2_TX_DATA__GPIO1_IO20                      = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0),
+	MX6_PAD_UART2_TX_DATA__ECSPI3_SS0                      = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0),
+
+	MX6_PAD_UART2_RX_DATA__UART2_DCE_RX                    = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0),
+
+	MX6_PAD_UART2_RX_DATA__UART2_DTE_TX                    = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0),
+	MX6_PAD_UART2_RX_DATA__ENET1_TDATA03                   = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0),
+	MX6_PAD_UART2_RX_DATA__I2C4_SDA                        = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0),
+	MX6_PAD_UART2_RX_DATA__CSI_DATA07                      = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0),
+	MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2                   = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0),
+	MX6_PAD_UART2_RX_DATA__GPIO1_IO21                      = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0),
+	MX6_PAD_UART2_RX_DATA__SJC_DONE                        = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0),
+	MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK                     = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0),
+
+	MX6_PAD_UART2_CTS_B__UART2_DCE_CTS                     = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART2_CTS_B__UART2_DTE_RTS                     = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0),
+	MX6_PAD_UART2_CTS_B__ENET1_CRS                         = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0),
+	MX6_PAD_UART2_CTS_B__FLEXCAN2_TX                       = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0),
+	MX6_PAD_UART2_CTS_B__CSI_DATA08                        = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0),
+	MX6_PAD_UART2_CTS_B__GPT1_COMPARE2                     = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0),
+	MX6_PAD_UART2_CTS_B__GPIO1_IO22                        = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0),
+	MX6_PAD_UART2_CTS_B__SJC_DE_B                          = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0),
+	MX6_PAD_UART2_CTS_B__ECSPI3_MOSI                       = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0),
+
+	MX6_PAD_UART2_RTS_B__UART2_DCE_RTS                     = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0),
+
+	MX6_PAD_UART2_RTS_B__UART2_DTE_CTS                     = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0),
+	MX6_PAD_UART2_RTS_B__ENET1_COL                         = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0),
+	MX6_PAD_UART2_RTS_B__FLEXCAN2_RX                       = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0),
+	MX6_PAD_UART2_RTS_B__CSI_DATA09                        = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0),
+	MX6_PAD_UART2_RTS_B__GPT1_COMPARE3                     = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0),
+	MX6_PAD_UART2_RTS_B__GPIO1_IO23                        = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0),
+	MX6_PAD_UART2_RTS_B__SJC_FAIL                          = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0),
+	MX6_PAD_UART2_RTS_B__ECSPI3_MISO                       = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0),
+
+	MX6_PAD_UART3_TX_DATA__UART3_DCE_TX                    = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART3_TX_DATA__UART3_DTE_RX                    = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0),
+	MX6_PAD_UART3_TX_DATA__ENET2_RDATA02                   = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0),
+	MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD                   = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0),
+	MX6_PAD_UART3_TX_DATA__CSI_DATA01                      = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0),
+	MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS                   = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0),
+	MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS                   = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0),
+	MX6_PAD_UART3_TX_DATA__GPIO1_IO24                      = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0),
+	MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT                    = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0),
+	MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID                  = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0),
+
+	MX6_PAD_UART3_RX_DATA__UART3_DCE_RX                    = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0),
+
+	MX6_PAD_UART3_RX_DATA__UART3_DTE_TX                    = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0),
+	MX6_PAD_UART3_RX_DATA__ENET2_RDATA03                   = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0),
+	MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD                   = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0),
+	MX6_PAD_UART3_RX_DATA__CSI_DATA00                      = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0),
+	MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS                   = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0),
+	MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS                   = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0),
+	MX6_PAD_UART3_RX_DATA__GPIO1_IO25                      = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0),
+	MX6_PAD_UART3_RX_DATA__EPIT1_OUT                       = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_UART3_CTS_B__UART3_DCE_CTS                     = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART3_CTS_B__UART3_DTE_RTS                     = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0),
+	MX6_PAD_UART3_CTS_B__ENET2_RX_CLK                      = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
+	MX6_PAD_UART3_CTS_B__FLEXCAN1_TX                       = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0),
+	MX6_PAD_UART3_CTS_B__CSI_DATA10                        = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0),
+	MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN              = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0),
+	MX6_PAD_UART3_CTS_B__GPIO1_IO26                        = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0),
+	MX6_PAD_UART3_CTS_B__EPIT2_OUT                         = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_UART3_RTS_B__UART3_DCE_RTS                     = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0),
+
+	MX6_PAD_UART3_RTS_B__UART3_DTE_CTS                     = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0),
+	MX6_PAD_UART3_RTS_B__ENET2_TX_ER                       = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0),
+	MX6_PAD_UART3_RTS_B__FLEXCAN1_RX                       = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0),
+	MX6_PAD_UART3_RTS_B__CSI_DATA11                        = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0),
+	MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT             = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0),
+	MX6_PAD_UART3_RTS_B__GPIO1_IO27                        = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0),
+	MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B                      = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0),
+
+	MX6_PAD_UART4_TX_DATA__UART4_DCE_TX                    = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART4_TX_DATA__UART4_DTE_RX                    = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0),
+	MX6_PAD_UART4_TX_DATA__ENET2_TDATA02                   = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0),
+	MX6_PAD_UART4_TX_DATA__I2C1_SCL                        = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0),
+	MX6_PAD_UART4_TX_DATA__CSI_DATA12                      = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0),
+	MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02             = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0),
+	MX6_PAD_UART4_TX_DATA__GPIO1_IO28                      = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0),
+	MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK                     = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0),
+
+	MX6_PAD_UART4_RX_DATA__UART4_DCE_RX                    = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0),
+
+	MX6_PAD_UART4_RX_DATA__UART4_DTE_TX                    = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0),
+	MX6_PAD_UART4_RX_DATA__ENET2_TDATA03                   = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0),
+	MX6_PAD_UART4_RX_DATA__I2C1_SDA                        = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0),
+	MX6_PAD_UART4_RX_DATA__CSI_DATA13                      = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0),
+	MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01             = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0),
+	MX6_PAD_UART4_RX_DATA__GPIO1_IO29                      = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0),
+	MX6_PAD_UART4_RX_DATA__ECSPI2_SS0                      = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0),
+	MX6_PAD_UART5_TX_DATA__GPIO1_IO30                      = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0),
+	MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI                     = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0),
+
+	MX6_PAD_UART5_TX_DATA__UART5_DCE_TX                    = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART5_TX_DATA__UART5_DTE_RX                    = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0),
+	MX6_PAD_UART5_TX_DATA__ENET2_CRS                       = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0),
+	MX6_PAD_UART5_TX_DATA__I2C2_SCL                        = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0),
+	MX6_PAD_UART5_TX_DATA__CSI_DATA14                      = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0),
+	MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00             = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0),
+
+	MX6_PAD_UART5_RX_DATA__UART5_DCE_RX                    = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 5, 0),
+
+	MX6_PAD_UART5_RX_DATA__UART5_DTE_TX                    = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0),
+	MX6_PAD_UART5_RX_DATA__ENET2_COL                       = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0),
+	MX6_PAD_UART5_RX_DATA__I2C2_SDA                        = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0),
+	MX6_PAD_UART5_RX_DATA__CSI_DATA15                      = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0),
+	MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB                 = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0),
+	MX6_PAD_UART5_RX_DATA__GPIO1_IO31                      = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0),
+	MX6_PAD_UART5_RX_DATA__ECSPI2_MISO                     = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0),
+
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00                  = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS                  = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS                  = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__PWM1_OUT                       = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__CSI_DATA16                     = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX                    = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00                     = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__KPP_ROW00                      = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL                    = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01                  = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS                  = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS                  = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0),
+	MX6_PAD_ENET1_RX_DATA1__PWM2_OUT                       = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__CSI_DATA17                     = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX                    = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0),
+	MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01                     = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__KPP_COL00                      = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL                    = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN                       = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS                     = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0),
+	MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS                     = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_EN__CSI_DATA18                        = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0),
+	MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX                       = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_EN__GPIO2_IO02                        = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_EN__KPP_ROW01                         = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0),
+	MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT                    = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00                  = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS                  = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                  = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0),
+	MX6_PAD_ENET1_TX_DATA0__CSI_DATA19                     = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0),
+	MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX                    = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0),
+	MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03                     = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA0__KPP_COL01                      = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0),
+	MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT                 = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01                  = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS                  = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS                  = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0),
+	MX6_PAD_ENET1_TX_DATA1__PWM5_OUT                       = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__CSI_DATA20                     = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO                     = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0),
+	MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04                     = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__KPP_ROW02                      = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB           = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN                       = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS                     = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0),
+	MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS                     = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_EN__PWM6_OUT                          = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_EN__CSI_DATA21                        = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0),
+	MX6_PAD_ENET1_TX_EN__ENET2_MDC                         = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_EN__GPIO2_IO05                        = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_EN__KPP_COL02                         = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0),
+	MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB              = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK                     = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS                    = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS                    = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__PWM7_OUT                         = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__CSI_DATA22                       = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1                   = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0),
+	MX6_PAD_ENET1_TX_CLK__GPIO2_IO06                       = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__KPP_ROW03                        = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__GPT1_CLK                         = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0),
+
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER                       = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS                     = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0),
+	MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS                     = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__PWM8_OUT                          = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__CSI_DATA23                        = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0),
+	MX6_PAD_ENET1_RX_ER__EIM_CRE                           = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__GPIO2_IO07                        = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__KPP_COL03                         = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2                     = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0),
+
+	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00                  = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX                   = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX                   = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0),
+	MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD                = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__I2C3_SCL                       = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0),
+	MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO                     = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0),
+	MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08                     = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__KPP_ROW04                      = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR                   = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01                  = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX                   = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0),
+	MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX                   = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK                 = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__I2C3_SDA                       = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0),
+	MX6_PAD_ENET2_RX_DATA1__ENET1_MDC                      = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09                     = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__KPP_COL04                      = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC                    = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0),
+
+	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN                       = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__UART7_DCE_TX                      = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__UART7_DTE_RX                      = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0),
+	MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B                  = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__I2C4_SCL                          = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0),
+	MX6_PAD_ENET2_RX_EN__EIM_ADDR26                        = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__GPIO2_IO10                        = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__KPP_ROW05                         = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M                 = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00                  = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX                   = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0),
+	MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX                   = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN                = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__I2C4_SDA                       = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0),
+	MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02                     = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11                     = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__KPP_COL05                      = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0),
+
+	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01                  = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX                   = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX                   = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD                = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK                    = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03                     = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12                     = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__KPP_ROW06                      = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR                   = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN                       = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__UART8_DCE_RX                      = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0),
+	MX6_PAD_ENET2_TX_EN__UART8_DTE_TX                      = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK                    = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI                       = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0),
+	MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN                  = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__GPIO2_IO13                        = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__KPP_COL06                         = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__USB_OTG2_OC                       = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0),
+
+	MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK                     = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS                    = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS                    = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B                 = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO                      = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2                   = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0),
+	MX6_PAD_ENET2_TX_CLK__GPIO2_IO14                       = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__KPP_ROW07                        = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID                   = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0),
+
+	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER                       = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS                     = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0),
+	MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS                     = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN                   = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__ECSPI4_SS0                        = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0),
+	MX6_PAD_ENET2_RX_ER__EIM_ADDR25                        = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__GPIO2_IO15                        = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__KPP_COL07                         = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY                    = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_CLK__LCDIF_CLK                             = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__LCDIF_WR_RWN                          = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__UART4_DCE_TX                          = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__UART4_DTE_RX                          = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0),
+	MX6_PAD_LCD_CLK__SAI3_MCLK                             = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0),
+	MX6_PAD_LCD_CLK__EIM_CS2_B                             = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__GPIO3_IO00                            = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB                  = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE                       = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__LCDIF_RD_E                         = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__UART4_DCE_RX                       = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0),
+	MX6_PAD_LCD_ENABLE__UART4_DTE_TX                       = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC                       = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0),
+	MX6_PAD_LCD_ENABLE__EIM_CS3_B                          = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__GPIO3_IO01                         = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__ECSPI2_RDY                         = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC                         = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0),
+	MX6_PAD_LCD_HSYNC__LCDIF_RS                            = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__UART4_DCE_CTS                       = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__UART4_DTE_RTS                       = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0),
+	MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK                        = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0),
+	MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB                = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__GPIO3_IO02                          = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__ECSPI2_SS1                          = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC                         = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__LCDIF_BUSY                          = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0),
+	MX6_PAD_LCD_VSYNC__UART4_DCE_RTS                       = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0),
+	MX6_PAD_LCD_VSYNC__UART4_DTE_CTS                       = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__SAI3_RX_DATA                        = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0),
+	MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B                        = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__GPIO3_IO03                          = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__ECSPI2_SS2                          = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_RESET__LCDIF_RESET                         = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__LCDIF_CS                            = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__CA7_MX6UL_EVENTI                    = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__SAI3_TX_DATA                        = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY                      = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__GPIO3_IO04                          = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__ECSPI2_SS3                          = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA00__LCDIF_DATA00                       = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__PWM1_OUT                           = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN               = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__I2C3_SDA                           = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0),
+	MX6_PAD_LCD_DATA00__GPIO3_IO05                         = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__SRC_BT_CFG00                       = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__SAI1_MCLK                          = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0),
+
+	MX6_PAD_LCD_DATA01__LCDIF_DATA01                       = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__PWM2_OUT                           = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT              = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__I2C3_SCL                           = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0),
+	MX6_PAD_LCD_DATA01__GPIO3_IO06                         = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__SRC_BT_CFG01                       = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__SAI1_TX_SYNC                       = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0),
+
+	MX6_PAD_LCD_DATA02__LCDIF_DATA02                       = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__PWM3_OUT                           = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN               = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__I2C4_SDA                           = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0),
+	MX6_PAD_LCD_DATA02__GPIO3_IO07                         = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__SRC_BT_CFG02                       = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__SAI1_TX_BCLK                       = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0),
+
+	MX6_PAD_LCD_DATA03__LCDIF_DATA03                       = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__PWM4_OUT                           = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT              = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__I2C4_SCL                           = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0),
+	MX6_PAD_LCD_DATA03__GPIO3_IO08                         = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__SRC_BT_CFG03                       = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__SAI1_RX_DATA                       = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0),
+
+	MX6_PAD_LCD_DATA04__LCDIF_DATA04                       = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__UART8_DCE_CTS                      = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__UART8_DTE_RTS                      = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0),
+	MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN               = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__SPDIF_SR_CLK                       = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__GPIO3_IO09                         = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__SRC_BT_CFG04                       = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__SAI1_TX_DATA                       = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA05__LCDIF_DATA05                       = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__UART8_DCE_RTS                      = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0),
+	MX6_PAD_LCD_DATA05__UART8_DTE_CTS                      = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT              = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__SPDIF_OUT                          = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__GPIO3_IO10                         = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__SRC_BT_CFG05                       = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__ECSPI1_SS1                         = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA06__LCDIF_DATA06                       = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__UART7_DCE_CTS                      = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__UART7_DTE_RTS                      = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0),
+	MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN               = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__SPDIF_LOCK                         = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__GPIO3_IO11                         = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__SRC_BT_CFG06                       = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__ECSPI1_SS2                         = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA07__LCDIF_DATA07                       = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__UART7_DCE_RTS                      = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0),
+	MX6_PAD_LCD_DATA07__UART7_DTE_CTS                      = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT              = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK                      = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0),
+	MX6_PAD_LCD_DATA07__GPIO3_IO12                         = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__SRC_BT_CFG07                       = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__ECSPI1_SS3                         = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA08__LCDIF_DATA08                       = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA08__SPDIF_IN                           = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0),
+	MX6_PAD_LCD_DATA08__CSI_DATA16                         = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0),
+	MX6_PAD_LCD_DATA08__EIM_DATA00                         = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA08__GPIO3_IO13                         = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA08__SRC_BT_CFG08                       = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA08__FLEXCAN1_TX                        = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA09__LCDIF_DATA09                       = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA09__SAI3_MCLK                          = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0),
+	MX6_PAD_LCD_DATA09__CSI_DATA17                         = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0),
+	MX6_PAD_LCD_DATA09__EIM_DATA01                         = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA09__GPIO3_IO14                         = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA09__SRC_BT_CFG09                       = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA09__FLEXCAN1_RX                        = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0),
+
+	MX6_PAD_LCD_DATA10__LCDIF_DATA10                       = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__SAI3_RX_SYNC                       = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__CSI_DATA18                         = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0),
+	MX6_PAD_LCD_DATA10__EIM_DATA02                         = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__GPIO3_IO15                         = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__SRC_BT_CFG10                       = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__FLEXCAN2_TX                        = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA11__LCDIF_DATA11                       = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__SAI3_RX_BCLK                       = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__CSI_DATA19                         = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0),
+	MX6_PAD_LCD_DATA11__EIM_DATA03                         = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__GPIO3_IO16                         = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__SRC_BT_CFG11                       = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__FLEXCAN2_RX                        = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0),
+
+	MX6_PAD_LCD_DATA12__LCDIF_DATA12                       = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA12__SAI3_TX_SYNC                       = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0),
+	MX6_PAD_LCD_DATA12__CSI_DATA20                         = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0),
+	MX6_PAD_LCD_DATA12__EIM_DATA04                         = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA12__GPIO3_IO17                         = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA12__SRC_BT_CFG12                       = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA12__ECSPI1_RDY                         = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA13__LCDIF_DATA13                       = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA13__SAI3_TX_BCLK                       = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0),
+	MX6_PAD_LCD_DATA13__CSI_DATA21                         = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0),
+	MX6_PAD_LCD_DATA13__EIM_DATA05                         = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA13__GPIO3_IO18                         = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA13__SRC_BT_CFG13                       = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA13__USDHC2_RESET_B                     = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA14__LCDIF_DATA14                       = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA14__SAI3_RX_DATA                       = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0),
+	MX6_PAD_LCD_DATA14__CSI_DATA22                         = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0),
+	MX6_PAD_LCD_DATA14__EIM_DATA06                         = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA14__GPIO3_IO19                         = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA14__SRC_BT_CFG14                       = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA14__USDHC2_DATA4                       = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0),
+
+	MX6_PAD_LCD_DATA15__LCDIF_DATA15                       = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__SAI3_TX_DATA                       = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__CSI_DATA23                         = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0),
+	MX6_PAD_LCD_DATA15__EIM_DATA07                         = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__GPIO3_IO20                         = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__SRC_BT_CFG15                       = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__USDHC2_DATA5                       = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0),
+
+	MX6_PAD_LCD_DATA16__LCDIF_DATA16                       = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA16__UART7_DCE_TX                       = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA16__UART7_DTE_RX                       = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0),
+	MX6_PAD_LCD_DATA16__CSI_DATA01                         = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0),
+	MX6_PAD_LCD_DATA16__EIM_DATA08                         = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA16__GPIO3_IO21                         = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA16__SRC_BT_CFG24                       = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA16__USDHC2_DATA6                       = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0),
+
+	MX6_PAD_LCD_DATA17__LCDIF_DATA17                       = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__UART7_DCE_RX                       = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0),
+	MX6_PAD_LCD_DATA17__UART7_DTE_TX                       = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__CSI_DATA00                         = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0),
+	MX6_PAD_LCD_DATA17__EIM_DATA09                         = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__GPIO3_IO22                         = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__SRC_BT_CFG25                       = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__USDHC2_DATA7                       = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0),
+
+	MX6_PAD_LCD_DATA18__LCDIF_DATA18                       = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__PWM5_OUT                           = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__CA7_MX6UL_EVENTO                   = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__CSI_DATA10                         = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0),
+	MX6_PAD_LCD_DATA18__EIM_DATA10                         = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__GPIO3_IO23                         = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__SRC_BT_CFG26                       = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__USDHC2_CMD                         = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0),
+	MX6_PAD_LCD_DATA19__EIM_DATA11                         = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__GPIO3_IO24                         = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__SRC_BT_CFG27                       = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__USDHC2_CLK                         = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0),
+
+	MX6_PAD_LCD_DATA19__LCDIF_DATA19                       = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__PWM6_OUT                           = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY                     = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__CSI_DATA11                         = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0),
+	MX6_PAD_LCD_DATA20__EIM_DATA12                         = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__GPIO3_IO25                         = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__SRC_BT_CFG28                       = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__USDHC2_DATA0                       = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0),
+
+	MX6_PAD_LCD_DATA20__LCDIF_DATA20                       = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__UART8_DCE_TX                       = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__UART8_DTE_RX                       = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0),
+	MX6_PAD_LCD_DATA20__ECSPI1_SCLK                        = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0),
+	MX6_PAD_LCD_DATA20__CSI_DATA12                         = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0),
+
+	MX6_PAD_LCD_DATA21__LCDIF_DATA21                       = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__UART8_DCE_RX                       = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0),
+	MX6_PAD_LCD_DATA21__UART8_DTE_TX                       = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__ECSPI1_SS0                         = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0),
+	MX6_PAD_LCD_DATA21__CSI_DATA13                         = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0),
+	MX6_PAD_LCD_DATA21__EIM_DATA13                         = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__GPIO3_IO26                         = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__SRC_BT_CFG29                       = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__USDHC2_DATA1                       = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0),
+
+	MX6_PAD_LCD_DATA22__LCDIF_DATA22                       = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__MQS_RIGHT                          = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__ECSPI1_MOSI                        = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0),
+	MX6_PAD_LCD_DATA22__CSI_DATA14                         = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0),
+	MX6_PAD_LCD_DATA22__EIM_DATA14                         = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__GPIO3_IO27                         = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__SRC_BT_CFG30                       = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__USDHC2_DATA2                       = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0),
+
+	MX6_PAD_LCD_DATA23__LCDIF_DATA23                       = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA23__MQS_LEFT                           = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA23__ECSPI1_MISO                        = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0),
+	MX6_PAD_LCD_DATA23__CSI_DATA15                         = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0),
+	MX6_PAD_LCD_DATA23__EIM_DATA15                         = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA23__GPIO3_IO28                         = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA23__SRC_BT_CFG31                       = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA23__USDHC2_DATA3                       = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0),
+
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B                        = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_RE_B__USDHC2_CLK                          = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0),
+	MX6_PAD_NAND_RE_B__QSPI_B_SCLK                         = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_RE_B__KPP_ROW00                           = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0),
+	MX6_PAD_NAND_RE_B__EIM_EB_B00                          = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_RE_B__GPIO4_IO00                          = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_RE_B__ECSPI3_SS2                          = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B                        = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD                          = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0),
+	MX6_PAD_NAND_WE_B__QSPI_B_SS0_B                        = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_WE_B__KPP_COL00                           = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0),
+	MX6_PAD_NAND_WE_B__EIM_EB_B01                          = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_WE_B__GPIO4_IO01                          = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_WE_B__ECSPI3_SS3                          = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00                    = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0                      = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0),
+	MX6_PAD_NAND_DATA00__QSPI_B_SS1_B                      = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA00__KPP_ROW01                         = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0),
+	MX6_PAD_NAND_DATA00__EIM_AD08                          = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA00__GPIO4_IO02                        = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA00__ECSPI4_RDY                        = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01                    = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1                      = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0),
+	MX6_PAD_NAND_DATA01__QSPI_B_DQS                        = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA01__KPP_COL01                         = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0),
+	MX6_PAD_NAND_DATA01__EIM_AD09                          = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA01__GPIO4_IO03                        = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA01__ECSPI4_SS1                        = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02                    = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2                      = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0),
+	MX6_PAD_NAND_DATA02__QSPI_B_DATA00                     = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA02__KPP_ROW02                         = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0),
+	MX6_PAD_NAND_DATA02__EIM_AD10                          = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA02__GPIO4_IO04                        = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA02__ECSPI4_SS2                        = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03                    = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3                      = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0),
+	MX6_PAD_NAND_DATA03__QSPI_B_DATA01                     = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA03__KPP_COL02                         = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0),
+	MX6_PAD_NAND_DATA03__EIM_AD11                          = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA03__GPIO4_IO05                        = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA03__ECSPI4_SS3                        = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04                    = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4                      = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0),
+	MX6_PAD_NAND_DATA04__QSPI_B_DATA02                     = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA04__ECSPI4_SCLK                       = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0),
+	MX6_PAD_NAND_DATA04__EIM_AD12                          = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA04__GPIO4_IO06                        = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA04__UART2_DCE_TX                      = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA04__UART2_DTE_RX                      = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0),
+
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05                    = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5                      = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0),
+	MX6_PAD_NAND_DATA05__QSPI_B_DATA03                     = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA05__ECSPI4_MOSI                       = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0),
+	MX6_PAD_NAND_DATA05__EIM_AD13                          = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA05__GPIO4_IO07                        = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA05__UART2_DCE_RX                      = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0),
+	MX6_PAD_NAND_DATA05__UART2_DTE_TX                      = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06                    = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6                      = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0),
+	MX6_PAD_NAND_DATA06__SAI2_RX_BCLK                      = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA06__ECSPI4_MISO                       = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0),
+	MX6_PAD_NAND_DATA06__EIM_AD14                          = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA06__GPIO4_IO08                        = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA06__UART2_DCE_CTS                     = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA06__UART2_DTE_RTS                     = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0),
+
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07                    = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7                      = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0),
+	MX6_PAD_NAND_DATA07__QSPI_A_SS1_B                      = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA07__ECSPI4_SS0                        = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0),
+	MX6_PAD_NAND_DATA07__EIM_AD15                          = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA07__GPIO4_IO09                        = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA07__UART2_DCE_RTS                     = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0),
+	MX6_PAD_NAND_DATA07__UART2_DTE_CTS                     = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_ALE__RAWNAND_ALE                          = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__USDHC2_RESET_B                       = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__QSPI_A_DQS                           = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__PWM3_OUT                             = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__EIM_ADDR17                           = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__GPIO4_IO10                           = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__ECSPI3_SS1                           = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B                        = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__USDHC1_RESET_B                      = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__QSPI_A_SCLK                         = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__PWM4_OUT                            = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__EIM_BCLK                            = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__GPIO4_IO11                          = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__ECSPI3_RDY                          = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B                  = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__USDHC1_DATA4                     = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__QSPI_A_DATA00                    = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__ECSPI3_SS0                       = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0),
+	MX6_PAD_NAND_READY_B__EIM_CS1_B                        = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__GPIO4_IO12                       = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__UART3_DCE_TX                     = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__UART3_DTE_RX                     = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0),
+
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B                      = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE0_B__USDHC1_DATA5                       = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE0_B__QSPI_A_DATA01                      = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE0_B__ECSPI3_SCLK                        = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0),
+	MX6_PAD_NAND_CE0_B__EIM_DTACK_B                        = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE0_B__GPIO4_IO13                         = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE0_B__UART3_DCE_RX                       = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0),
+	MX6_PAD_NAND_CE0_B__UART3_DTE_TX                       = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B                      = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__USDHC1_DATA6                       = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__QSPI_A_DATA02                      = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__ECSPI3_MOSI                        = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0),
+	MX6_PAD_NAND_CE1_B__EIM_ADDR18                         = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__GPIO4_IO14                         = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__UART3_DCE_CTS                      = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__UART3_DTE_RTS                      = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0),
+
+	MX6_PAD_NAND_CLE__RAWNAND_CLE                          = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_CLE__USDHC1_DATA7                         = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_CLE__QSPI_A_DATA03                        = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_CLE__ECSPI3_MISO                          = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0),
+	MX6_PAD_NAND_CLE__EIM_ADDR16                           = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_CLE__GPIO4_IO15                           = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_CLE__UART3_DCE_RTS                        = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0),
+	MX6_PAD_NAND_CLE__UART3_DTE_CTS                        = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DQS__RAWNAND_DQS                          = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DQS__CSI_FIELD                            = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0),
+	MX6_PAD_NAND_DQS__QSPI_A_SS0_B                         = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DQS__PWM5_OUT                             = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0),
+	MX6_PAD_NAND_DQS__EIM_WAIT                             = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DQS__GPIO4_IO16                           = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01                     = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0),
+	MX6_PAD_NAND_DQS__SPDIF_EXT_CLK                        = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0),
+
+	MX6_PAD_SD1_CMD__USDHC1_CMD                            = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__GPT2_COMPARE1                         = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__SAI2_RX_SYNC                          = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__SPDIF_OUT                             = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__EIM_ADDR19                            = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__GPIO2_IO16                            = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00                      = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0),
+	MX6_PAD_SD1_CMD__USB_OTG1_PWR                          = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_CLK__USDHC1_CLK                            = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__GPT2_COMPARE2                         = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__SAI2_MCLK                             = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0),
+	MX6_PAD_SD1_CLK__SPDIF_IN                              = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0),
+	MX6_PAD_SD1_CLK__EIM_ADDR20                            = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__GPIO2_IO17                            = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__USB_OTG1_OC                           = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0),
+
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0                        = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__GPT2_COMPARE3                       = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__SAI2_TX_SYNC                        = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0),
+	MX6_PAD_SD1_DATA0__FLEXCAN1_TX                         = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__EIM_ADDR21                          = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__GPIO2_IO18                          = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID                      = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0),
+
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1                        = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA1__GPT2_CLK                            = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0),
+	MX6_PAD_SD1_DATA1__SAI2_TX_BCLK                        = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0),
+	MX6_PAD_SD1_DATA1__FLEXCAN1_RX                         = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0),
+	MX6_PAD_SD1_DATA1__EIM_ADDR22                          = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA1__GPIO2_IO19                          = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA1__USB_OTG2_PWR                        = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2                        = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__GPT2_CAPTURE1                       = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0),
+	MX6_PAD_SD1_DATA2__SAI2_RX_DATA                        = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0),
+	MX6_PAD_SD1_DATA2__FLEXCAN2_TX                         = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__EIM_ADDR23                          = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__GPIO2_IO20                          = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__CCM_CLKO1                           = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__USB_OTG2_OC                         = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0),
+
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3                        = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__GPT2_CAPTURE2                       = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0),
+	MX6_PAD_SD1_DATA3__SAI2_TX_DATA                        = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__FLEXCAN2_RX                         = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0),
+	MX6_PAD_SD1_DATA3__EIM_ADDR24                          = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__GPIO2_IO21                          = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__CCM_CLKO2                           = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID                      = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0),
+
+	MX6_PAD_CSI_MCLK__CSI_MCLK                             = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__USDHC2_CD_B                          = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0),
+	MX6_PAD_CSI_MCLK__RAWNAND_CE2_B                        = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__I2C1_SDA                             = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0),
+	MX6_PAD_CSI_MCLK__EIM_CS0_B                            = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__GPIO4_IO17                           = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL                    = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__UART6_DCE_TX                         = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__UART6_DTE_RX                         = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0),
+
+	MX6_PAD_CSI_PIXCLK__CSI_PIXCLK                         = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0),
+	MX6_PAD_CSI_PIXCLK__USDHC2_WP                          = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0),
+	MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B                      = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_PIXCLK__I2C1_SCL                           = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0),
+	MX6_PAD_CSI_PIXCLK__EIM_OE                             = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_PIXCLK__GPIO4_IO18                         = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5                      = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_PIXCLK__UART6_DCE_RX                       = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0),
+	MX6_PAD_CSI_PIXCLK__UART6_DTE_TX                       = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_CSI_VSYNC__CSI_VSYNC                           = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0),
+	MX6_PAD_CSI_VSYNC__USDHC2_CLK                          = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0),
+	MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK                      = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_VSYNC__I2C2_SDA                            = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0),
+	MX6_PAD_CSI_VSYNC__EIM_RW                              = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_VSYNC__GPIO4_IO19                          = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_VSYNC__PWM7_OUT                            = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_VSYNC__UART6_DCE_RTS                       = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0),
+	MX6_PAD_CSI_VSYNC__UART6_DTE_CTS                       = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_CSI_HSYNC__CSI_HSYNC                           = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0),
+	MX6_PAD_CSI_HSYNC__USDHC2_CMD                          = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0),
+	MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD                       = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_HSYNC__I2C2_SCL                            = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0),
+	MX6_PAD_CSI_HSYNC__EIM_LBA_B                           = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_HSYNC__GPIO4_IO20                          = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_HSYNC__PWM8_OUT                            = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_HSYNC__UART6_DCE_CTS                       = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0),
+	MX6_PAD_CSI_HSYNC__UART6_DTE_RTS                       = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0),
+
+	MX6_PAD_CSI_DATA00__CSI_DATA02                         = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0),
+	MX6_PAD_CSI_DATA00__USDHC2_DATA0                       = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0),
+	MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B                   = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA00__ECSPI2_SCLK                        = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0),
+	MX6_PAD_CSI_DATA00__EIM_AD00                           = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA00__GPIO4_IO21                         = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA00__SRC_INT_BOOT                       = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA00__UART5_DCE_TX                       = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA00__UART5_DTE_RX                       = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0),
+
+	MX6_PAD_CSI_DATA01__CSI_DATA03                         = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0),
+	MX6_PAD_CSI_DATA01__USDHC2_DATA1                       = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0),
+	MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN                    = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA01__ECSPI2_SS0                         = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0),
+	MX6_PAD_CSI_DATA01__EIM_AD01                           = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA01__GPIO4_IO22                         = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA01__SAI1_MCLK                          = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0),
+	MX6_PAD_CSI_DATA01__UART5_DCE_RX                       = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0),
+	MX6_PAD_CSI_DATA01__UART5_DTE_TX                       = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_CSI_DATA02__CSI_DATA04                         = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0),
+	MX6_PAD_CSI_DATA02__USDHC2_DATA2                       = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0),
+	MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD                    = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA02__ECSPI2_MOSI                        = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0),
+	MX6_PAD_CSI_DATA02__EIM_AD02                           = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA02__GPIO4_IO23                         = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA02__SAI1_RX_SYNC                       = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA02__UART5_DCE_RTS                      = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0),
+	MX6_PAD_CSI_DATA02__UART5_DTE_CTS                      = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_CSI_DATA03__CSI_DATA05                         = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0),
+	MX6_PAD_CSI_DATA03__USDHC2_DATA3                       = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0),
+	MX6_PAD_CSI_DATA03__SIM2_PORT1_PD                      = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA03__ECSPI2_MISO                        = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0),
+	MX6_PAD_CSI_DATA03__EIM_AD03                           = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA03__GPIO4_IO24                         = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA03__SAI1_RX_BCLK                       = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA03__UART5_DCE_CTS                      = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA03__UART5_DTE_RTS                      = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0),
+
+	MX6_PAD_CSI_DATA04__CSI_DATA06                         = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0),
+	MX6_PAD_CSI_DATA04__USDHC2_DATA4                       = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0),
+	MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK                     = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA04__ECSPI1_SCLK                        = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0),
+	MX6_PAD_CSI_DATA04__EIM_AD04                           = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA04__GPIO4_IO25                         = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA04__SAI1_TX_SYNC                       = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0),
+	MX6_PAD_CSI_DATA04__USDHC1_WP                          = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0),
+
+	MX6_PAD_CSI_DATA05__CSI_DATA07                         = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0),
+	MX6_PAD_CSI_DATA05__USDHC2_DATA5                       = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0),
+	MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B                   = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA05__ECSPI1_SS0                         = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0),
+	MX6_PAD_CSI_DATA05__EIM_AD05                           = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA05__GPIO4_IO26                         = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA05__SAI1_TX_BCLK                       = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0),
+	MX6_PAD_CSI_DATA05__USDHC1_CD_B                        = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0),
+
+	MX6_PAD_CSI_DATA06__CSI_DATA08                         = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0),
+	MX6_PAD_CSI_DATA06__USDHC2_DATA6                       = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0),
+	MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN                    = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA06__ECSPI1_MOSI                        = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0),
+	MX6_PAD_CSI_DATA06__EIM_AD06                           = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA06__GPIO4_IO27                         = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA06__SAI1_RX_DATA                       = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0),
+	MX6_PAD_CSI_DATA06__USDHC1_RESET_B                     = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_CSI_DATA07__CSI_DATA09                         = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0),
+	MX6_PAD_CSI_DATA07__USDHC2_DATA7                       = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0),
+	MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD                    = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA07__ECSPI1_MISO                        = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0),
+	MX6_PAD_CSI_DATA07__EIM_AD07                           = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA07__GPIO4_IO28                         = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA07__SAI1_TX_DATA                       = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA07__USDHC1_VSELECT                     = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0),
+};
+#endif  /* __ASM_ARCH_IMX6UL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
new file mode 100644
index 0000000..de4a1ab
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
@@ -0,0 +1,1064 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_IMX6ULL_PINS_H__
+#define __ASM_ARCH_IMX6ULL_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+	MX6_PAD_BOOT_MODE0__GPIO5_IO10	                       = IOMUX_PAD(0x0044, 0x0000, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX6_PAD_BOOT_MODE1__GPIO5_IO11	                       = IOMUX_PAD(0x0048, 0x0004, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+
+	/*
+	 * The TAMPER Pin can be used for GPIO, which depends on
+	 * TAMPER_PIN_DISABLE[1:0] settings.
+	 */
+	MX6_PAD_SNVS_TAMPER0__GPIO5_IO00                       = IOMUX_PAD(0x004C, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER1__GPIO5_IO01                       = IOMUX_PAD(0x0050, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER2__GPIO5_IO02                       = IOMUX_PAD(0x0054, 0x0010, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER3__GPIO5_IO03                       = IOMUX_PAD(0x0058, 0x0014, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER4__GPIO5_IO04                       = IOMUX_PAD(0x005C, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER5__GPIO5_IO05                       = IOMUX_PAD(0x0060, 0x001C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER6__GPIO5_IO06                       = IOMUX_PAD(0x0064, 0x0020, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER7__GPIO5_IO07                       = IOMUX_PAD(0x0068, 0x0024, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER8__GPIO5_IO08                       = IOMUX_PAD(0x006C, 0x0028, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX6_PAD_SNVS_TAMPER9__GPIO5_IO09                       = IOMUX_PAD(0x0070, 0x002C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+
+	MX6_PAD_JTAG_MOD__SJC_MOD                             = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_MOD__GPT2_CLK                            = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0),
+	MX6_PAD_JTAG_MOD__SPDIF_OUT                           = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0),
+	MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M                   = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0),
+	MX6_PAD_JTAG_MOD__CCM_PMIC_RDY                        = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0),
+	MX6_PAD_JTAG_MOD__GPIO1_IO10                          = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00                    = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0),
+
+	MX6_PAD_JTAG_TMS__SJC_TMS                             = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TMS__GPT2_CAPTURE1                       = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0),
+	MX6_PAD_JTAG_TMS__SAI2_MCLK                           = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0),
+	MX6_PAD_JTAG_TMS__CCM_CLKO1                           = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TMS__CCM_WAIT                            = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TMS__GPIO1_IO11                          = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01                    = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0),
+	MX6_PAD_JTAG_TMS__EPIT1_OUT                           = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0),
+
+	MX6_PAD_JTAG_TDO__SJC_TDO                             = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDO__GPT2_CAPTURE2                       = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0),
+	MX6_PAD_JTAG_TDO__SAI2_TX_SYNC                        = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0),
+	MX6_PAD_JTAG_TDO__CCM_CLKO2                           = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDO__CCM_STOP                            = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDO__GPIO1_IO12                          = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDO__MQS_RIGHT                           = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDO__EPIT2_OUT                           = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_JTAG_TDI__SJC_TDI                             = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDI__GPT2_COMPARE1                       = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDI__SAI2_TX_BCLK                        = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0),
+	MX6_PAD_JTAG_TDI__PWM6_OUT                            = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDI__GPIO1_IO13                          = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDI__MQS_LEFT                            = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL                     = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0),
+
+	MX6_PAD_JTAG_TCK__SJC_TCK                             = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TCK__GPT2_COMPARE2                       = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TCK__SAI2_RX_DATA                        = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0),
+	MX6_PAD_JTAG_TCK__PWM7_OUT                            = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TCK__GPIO1_IO14                          = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL                     = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0),
+
+	MX6_PAD_JTAG_TRST_B__SJC_TRSTB                        = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3                    = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA                     = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRST_B__PWM8_OUT                         = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRST_B__GPIO1_IO15                       = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS                 = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO00__I2C2_SCL                          = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0),
+	MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1                     = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0),
+	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID                    = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0),
+	MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1                    = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0),
+	MX6_PAD_GPIO1_IO00__MQS_RIGHT                         = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO00__GPIO1_IO00                        = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN              = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET                  = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B                      = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO01__I2C2_SDA                          = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0),
+	MX6_PAD_GPIO1_IO01__GPT1_COMPARE1                     = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO01__USB_OTG1_OC                       = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0),
+	MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2                    = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0),
+	MX6_PAD_GPIO1_IO01__MQS_LEFT                          = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO01__GPIO1_IO01                        = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT             = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET                   = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B                      = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO02__I2C1_SCL                          = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0),
+	MX6_PAD_GPIO1_IO02__GPT1_COMPARE2                     = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__USB_OTG2_PWR                      = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M                 = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__USDHC1_WP                         = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0),
+	MX6_PAD_GPIO1_IO02__GPIO1_IO02                        = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00                  = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0),
+	MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET                  = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__UART1_DCE_TX                      = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO02__UART1_DTE_RX                      = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0),
+
+	MX6_PAD_GPIO1_IO03__I2C1_SDA                          = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0),
+	MX6_PAD_GPIO1_IO03__GPT1_COMPARE3                     = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO03__USB_OTG2_OC                       = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0),
+	MX6_PAD_GPIO1_IO03__USDHC1_CD_B                       = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0),
+	MX6_PAD_GPIO1_IO03__GPIO1_IO03                        = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK                   = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK                    = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO03__UART1_DCE_RX                      = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0),
+	MX6_PAD_GPIO1_IO03__UART1_DTE_TX                      = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1                    = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0),
+	MX6_PAD_GPIO1_IO04__PWM3_OUT                          = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__USB_OTG1_PWR                      = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__USDHC1_RESET_B                    = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__GPIO1_IO04                        = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN              = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__UART5_DCE_TX                      = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__UART5_DTE_RX                      = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0),
+
+	MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2                    = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0),
+	MX6_PAD_GPIO1_IO05__PWM4_OUT                          = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID                    = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0),
+	MX6_PAD_GPIO1_IO05__CSI_FIELD                         = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0),
+	MX6_PAD_GPIO1_IO05__USDHC1_VSELECT                    = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO05__GPIO1_IO05                        = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT             = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO05__UART5_DCE_RX                      = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0),
+	MX6_PAD_GPIO1_IO05__UART5_DTE_TX                      = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO                        = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0),
+	MX6_PAD_GPIO1_IO06__ENET2_MDIO                        = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0),
+	MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE                  = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__CSI_MCLK                          = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__USDHC2_WP                         = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0),
+	MX6_PAD_GPIO1_IO06__GPIO1_IO06                        = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__CCM_WAIT                          = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__CCM_REF_EN_B                      = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__UART1_DCE_CTS                     = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO06__UART1_DTE_RTS                     = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0),
+
+	MX6_PAD_GPIO1_IO07__ENET1_MDC                         = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO07__ENET2_MDC                         = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE                 = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO07__CSI_PIXCLK                        = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0),
+	MX6_PAD_GPIO1_IO07__USDHC2_CD_B                       = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0),
+	MX6_PAD_GPIO1_IO07__GPIO1_IO07                        = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO07__CCM_STOP                          = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO07__UART1_DCE_RTS                     = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0),
+	MX6_PAD_GPIO1_IO07__UART1_DTE_CTS                     = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO08__PWM1_OUT                          = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B                      = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO08__SPDIF_OUT                         = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO08__CSI_VSYNC                         = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0),
+	MX6_PAD_GPIO1_IO08__USDHC2_VSELECT                    = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO08__GPIO1_IO08                        = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY                      = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0),
+	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS                     = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0),
+	MX6_PAD_GPIO1_IO08__UART5_DTE_CTS                     = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_GPIO1_IO09__PWM2_OUT                          = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY                    = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__SPDIF_IN                          = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0),
+	MX6_PAD_GPIO1_IO09__CSI_HSYNC                         = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0),
+	MX6_PAD_GPIO1_IO09__USDHC2_RESET_B                    = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__GPIO1_IO09                        = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__USDHC1_RESET_B                    = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS                     = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO09__UART5_DTE_RTS                     = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0),
+
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX                   = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART1_TX_DATA__UART1_DTE_RX                   = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0),
+	MX6_PAD_UART1_TX_DATA__ENET1_RDATA02                  = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0),
+	MX6_PAD_UART1_TX_DATA__I2C3_SCL                       = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0),
+	MX6_PAD_UART1_TX_DATA__CSI_DATA02                     = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0),
+	MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1                  = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0),
+	MX6_PAD_UART1_TX_DATA__GPIO1_IO16                     = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0),
+	MX6_PAD_UART1_TX_DATA__SPDIF_OUT                      = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0),
+
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX                   = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0),
+
+	MX6_PAD_UART1_RX_DATA__UART1_DTE_TX                   = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0),
+	MX6_PAD_UART1_RX_DATA__ENET1_RDATA03                  = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0),
+	MX6_PAD_UART1_RX_DATA__I2C3_SDA                       = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0),
+	MX6_PAD_UART1_RX_DATA__CSI_DATA03                     = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0),
+	MX6_PAD_UART1_RX_DATA__GPT1_CLK                       = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0),
+	MX6_PAD_UART1_RX_DATA__GPIO1_IO17                     = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0),
+	MX6_PAD_UART1_RX_DATA__SPDIF_IN                       = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0),
+
+	MX6_PAD_UART1_CTS_B__UART1_DCE_CTS                    = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART1_CTS_B__UART1_DTE_RTS                    = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0),
+	MX6_PAD_UART1_CTS_B__ENET1_RX_CLK                     = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0),
+	MX6_PAD_UART1_CTS_B__USDHC1_WP                        = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0),
+	MX6_PAD_UART1_CTS_B__CSI_DATA04                       = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0),
+	MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN             = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0),
+	MX6_PAD_UART1_CTS_B__GPIO1_IO18                       = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0),
+	MX6_PAD_UART1_CTS_B__USDHC2_WP                        = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0),
+
+	MX6_PAD_UART1_RTS_B__UART1_DCE_RTS                    = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0),
+
+	MX6_PAD_UART1_RTS_B__UART1_DTE_CTS                    = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0),
+	MX6_PAD_UART1_RTS_B__ENET1_TX_ER                      = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0),
+	MX6_PAD_UART1_RTS_B__USDHC1_CD_B                      = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0),
+	MX6_PAD_UART1_RTS_B__CSI_DATA05                       = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0),
+	MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT            = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0),
+	MX6_PAD_UART1_RTS_B__GPIO1_IO19                       = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0),
+	MX6_PAD_UART1_RTS_B__USDHC2_CD_B                      = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0),
+
+	MX6_PAD_UART2_TX_DATA__UART2_DCE_TX                   = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART2_TX_DATA__UART2_DTE_RX                   = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0),
+	MX6_PAD_UART2_TX_DATA__ENET1_TDATA02                  = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0),
+	MX6_PAD_UART2_TX_DATA__I2C4_SCL                       = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0),
+	MX6_PAD_UART2_TX_DATA__CSI_DATA06                     = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0),
+	MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1                  = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0),
+	MX6_PAD_UART2_TX_DATA__GPIO1_IO20                     = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0),
+	MX6_PAD_UART2_TX_DATA__ECSPI3_SS0                     = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0),
+
+	MX6_PAD_UART2_RX_DATA__UART2_DCE_RX                   = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0),
+
+	MX6_PAD_UART2_RX_DATA__UART2_DTE_TX                   = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0),
+	MX6_PAD_UART2_RX_DATA__ENET1_TDATA03                  = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0),
+	MX6_PAD_UART2_RX_DATA__I2C4_SDA                       = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0),
+	MX6_PAD_UART2_RX_DATA__CSI_DATA07                     = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0),
+	MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2                  = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0),
+	MX6_PAD_UART2_RX_DATA__GPIO1_IO21                     = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0),
+	MX6_PAD_UART2_RX_DATA__SJC_DONE                       = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0),
+	MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK                    = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0),
+
+	MX6_PAD_UART2_CTS_B__UART2_DCE_CTS                    = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART2_CTS_B__UART2_DTE_RTS                    = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0),
+	MX6_PAD_UART2_CTS_B__ENET1_CRS                        = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0),
+	MX6_PAD_UART2_CTS_B__FLEXCAN2_TX                      = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0),
+	MX6_PAD_UART2_CTS_B__CSI_DATA08                       = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0),
+	MX6_PAD_UART2_CTS_B__GPT1_COMPARE2                    = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0),
+	MX6_PAD_UART2_CTS_B__GPIO1_IO22                       = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0),
+	MX6_PAD_UART2_CTS_B__SJC_DE_B                         = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0),
+	MX6_PAD_UART2_CTS_B__ECSPI3_MOSI                      = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0),
+
+	MX6_PAD_UART2_RTS_B__UART2_DCE_RTS                    = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0),
+
+	MX6_PAD_UART2_RTS_B__UART2_DTE_CTS                    = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0),
+	MX6_PAD_UART2_RTS_B__ENET1_COL                        = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0),
+	MX6_PAD_UART2_RTS_B__FLEXCAN2_RX                      = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0),
+	MX6_PAD_UART2_RTS_B__CSI_DATA09                       = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0),
+	MX6_PAD_UART2_RTS_B__GPT1_COMPARE3                    = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0),
+	MX6_PAD_UART2_RTS_B__GPIO1_IO23                       = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0),
+	MX6_PAD_UART2_RTS_B__SJC_FAIL                         = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0),
+	MX6_PAD_UART2_RTS_B__ECSPI3_MISO                      = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0),
+
+	MX6_PAD_UART3_TX_DATA__UART3_DCE_TX                   = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART3_TX_DATA__UART3_DTE_RX                   = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0),
+	MX6_PAD_UART3_TX_DATA__ENET2_RDATA02                  = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0),
+	MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD                  = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0),
+	MX6_PAD_UART3_TX_DATA__CSI_DATA01                     = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0),
+	MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS                  = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0),
+	MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS                  = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0),
+	MX6_PAD_UART3_TX_DATA__GPIO1_IO24                     = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0),
+	MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT                   = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0),
+	MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID                 = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0),
+
+	MX6_PAD_UART3_RX_DATA__UART3_DCE_RX                   = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0),
+
+	MX6_PAD_UART3_RX_DATA__UART3_DTE_TX                   = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0),
+	MX6_PAD_UART3_RX_DATA__ENET2_RDATA03                  = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0),
+	MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD                  = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0),
+	MX6_PAD_UART3_RX_DATA__CSI_DATA00                     = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0),
+	MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS                  = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0),
+	MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS                  = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0),
+	MX6_PAD_UART3_RX_DATA__GPIO1_IO25                     = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0),
+	MX6_PAD_UART3_RX_DATA__EPIT1_OUT                      = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_UART3_CTS_B__UART3_DCE_CTS                    = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART3_CTS_B__UART3_DTE_RTS                    = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0),
+	MX6_PAD_UART3_CTS_B__ENET2_RX_CLK                     = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
+	MX6_PAD_UART3_CTS_B__FLEXCAN1_TX                      = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0),
+	MX6_PAD_UART3_CTS_B__CSI_DATA10                       = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0),
+	MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN             = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0),
+	MX6_PAD_UART3_CTS_B__GPIO1_IO26                       = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0),
+	MX6_PAD_UART3_CTS_B__EPIT2_OUT                        = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_UART3_RTS_B__UART3_DCE_RTS                    = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0),
+
+	MX6_PAD_UART3_RTS_B__UART3_DTE_CTS                    = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0),
+	MX6_PAD_UART3_RTS_B__ENET2_TX_ER                      = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0),
+	MX6_PAD_UART3_RTS_B__FLEXCAN1_RX                      = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0),
+	MX6_PAD_UART3_RTS_B__CSI_DATA11                       = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0),
+	MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT            = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0),
+	MX6_PAD_UART3_RTS_B__GPIO1_IO27                       = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0),
+	MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B                     = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0),
+
+	MX6_PAD_UART4_TX_DATA__UART4_DCE_TX                   = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART4_TX_DATA__UART4_DTE_RX                   = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0),
+	MX6_PAD_UART4_TX_DATA__ENET2_TDATA02                  = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0),
+	MX6_PAD_UART4_TX_DATA__I2C1_SCL                       = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0),
+	MX6_PAD_UART4_TX_DATA__CSI_DATA12                     = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0),
+	MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02            = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0),
+	MX6_PAD_UART4_TX_DATA__GPIO1_IO28                     = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0),
+	MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK                    = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0),
+
+	MX6_PAD_UART4_RX_DATA__UART4_DCE_RX                   = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0),
+
+	MX6_PAD_UART4_RX_DATA__UART4_DTE_TX                   = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0),
+	MX6_PAD_UART4_RX_DATA__ENET2_TDATA03                  = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0),
+	MX6_PAD_UART4_RX_DATA__I2C1_SDA                       = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0),
+	MX6_PAD_UART4_RX_DATA__CSI_DATA13                     = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0),
+	MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01            = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0),
+	MX6_PAD_UART4_RX_DATA__GPIO1_IO29                     = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0),
+	MX6_PAD_UART4_RX_DATA__ECSPI2_SS0                     = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0),
+	MX6_PAD_UART5_TX_DATA__GPIO1_IO30                     = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0),
+	MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI                    = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0),
+
+	MX6_PAD_UART5_TX_DATA__UART5_DCE_TX                   = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0),
+
+	MX6_PAD_UART5_TX_DATA__UART5_DTE_RX                   = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0),
+	MX6_PAD_UART5_TX_DATA__ENET2_CRS                      = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0),
+	MX6_PAD_UART5_TX_DATA__I2C2_SCL                       = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0),
+	MX6_PAD_UART5_TX_DATA__CSI_DATA14                     = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0),
+	MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00            = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0),
+
+	MX6_PAD_UART5_RX_DATA__UART5_DCE_RX                   = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 7, 0),
+
+	MX6_PAD_UART5_RX_DATA__UART5_DTE_TX                   = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0),
+	MX6_PAD_UART5_RX_DATA__ENET2_COL                      = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0),
+	MX6_PAD_UART5_RX_DATA__I2C2_SDA                       = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0),
+	MX6_PAD_UART5_RX_DATA__CSI_DATA15                     = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0),
+	MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB                = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0),
+	MX6_PAD_UART5_RX_DATA__GPIO1_IO31                     = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0),
+	MX6_PAD_UART5_RX_DATA__ECSPI2_MISO                    = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0),
+
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00                 = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS                 = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS                 = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__PWM1_OUT                      = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__CSI_DATA16                    = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX                   = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00                    = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__KPP_ROW00                     = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0),
+	MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL                   = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01                 = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS                 = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS                 = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0),
+	MX6_PAD_ENET1_RX_DATA1__PWM2_OUT                      = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__CSI_DATA17                    = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX                   = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0),
+	MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01                    = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__KPP_COL00                     = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0),
+	MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL                   = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN                      = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS                    = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0),
+	MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS                    = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_EN__CSI_DATA18                       = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0),
+	MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX                      = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_EN__GPIO2_IO02                       = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_EN__KPP_ROW01                        = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0),
+	MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT                   = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00                 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS                 = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                 = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0),
+	MX6_PAD_ENET1_TX_DATA0__CSI_DATA19                    = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0),
+	MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX                   = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0),
+	MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03                    = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA0__KPP_COL01                     = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0),
+	MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT                = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01                 = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS                 = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS                 = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0),
+	MX6_PAD_ENET1_TX_DATA1__PWM5_OUT                      = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__CSI_DATA20                    = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO                    = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0),
+	MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04                    = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__KPP_ROW02                     = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0),
+	MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB          = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN                      = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS                    = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0),
+	MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS                    = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_EN__PWM6_OUT                         = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_EN__CSI_DATA21                       = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0),
+	MX6_PAD_ENET1_TX_EN__ENET2_MDC                        = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_EN__GPIO2_IO05                       = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_EN__KPP_COL02                        = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0),
+	MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB             = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK                    = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS                   = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS                   = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__PWM7_OUT                        = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__CSI_DATA22                      = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1                  = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0),
+	MX6_PAD_ENET1_TX_CLK__GPIO2_IO06                      = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__KPP_ROW03                       = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET1_TX_CLK__GPT1_CLK                        = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0),
+
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER                      = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS                    = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0),
+	MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS                    = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__PWM8_OUT                         = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__CSI_DATA23                       = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0),
+	MX6_PAD_ENET1_RX_ER__EIM_CRE                          = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__GPIO2_IO07                       = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__KPP_COL03                        = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2                    = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0),
+
+	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00                 = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX                  = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX                  = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0),
+	MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD               = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__I2C3_SCL                      = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0),
+	MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO                    = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0),
+	MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08                    = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__KPP_ROW04                     = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR                  = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01                 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX                  = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0),
+	MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX                  = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK                = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__I2C3_SDA                      = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0),
+	MX6_PAD_ENET2_RX_DATA1__ENET1_MDC                     = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09                    = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__KPP_COL04                     = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC                   = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0),
+
+	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN                      = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__UART7_DCE_TX                     = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__UART7_DTE_RX                     = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0),
+	MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B                 = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__I2C4_SCL                         = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0),
+	MX6_PAD_ENET2_RX_EN__EIM_ADDR26                       = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__GPIO2_IO10                       = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__KPP_ROW05                        = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M                = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00                 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX                  = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0),
+	MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX                  = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN               = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__I2C4_SDA                      = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0),
+	MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02                    = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11                    = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__KPP_COL05                     = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0),
+
+	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01                 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX                  = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX                  = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD               = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK                   = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03                    = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12                    = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__KPP_ROW06                     = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR                  = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN                      = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__UART8_DCE_RX                     = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0),
+	MX6_PAD_ENET2_TX_EN__UART8_DTE_TX                     = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK                   = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI                      = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0),
+	MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN                 = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__GPIO2_IO13                       = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__KPP_COL06                        = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_EN__USB_OTG2_OC                      = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0),
+
+	MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK                    = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS                   = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS                   = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B                = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO                     = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2                  = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0),
+	MX6_PAD_ENET2_TX_CLK__GPIO2_IO14                      = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__KPP_ROW07                       = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID                  = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0),
+
+	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER                      = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS                    = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0),
+	MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS                    = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN                  = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__ECSPI4_SS0                       = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0),
+	MX6_PAD_ENET2_RX_ER__EIM_ADDR25                       = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__GPIO2_IO15                       = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__KPP_COL07                        = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY                   = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_CLK__LCDIF_CLK                            = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__LCDIF_WR_RWN                         = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__UART4_DCE_TX                         = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__UART4_DTE_RX                         = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0),
+	MX6_PAD_LCD_CLK__SAI3_MCLK                            = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0),
+	MX6_PAD_LCD_CLK__EIM_CS2_B                            = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__GPIO3_IO00                           = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB                 = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE                      = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__LCDIF_RD_E                        = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__UART4_DCE_RX                      = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0),
+	MX6_PAD_LCD_ENABLE__UART4_DTE_TX                      = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC                      = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0),
+	MX6_PAD_LCD_ENABLE__EIM_CS3_B                         = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__GPIO3_IO01                        = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__ECSPI2_RDY                        = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC                        = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0),
+	MX6_PAD_LCD_HSYNC__LCDIF_RS                           = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__UART4_DCE_CTS                      = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__UART4_DTE_RTS                      = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0),
+	MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK                       = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0),
+	MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB               = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__GPIO3_IO02                         = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__ECSPI2_SS1                         = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC                        = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__LCDIF_BUSY                         = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0),
+	MX6_PAD_LCD_VSYNC__UART4_DCE_RTS                      = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0),
+	MX6_PAD_LCD_VSYNC__UART4_DTE_CTS                      = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__SAI3_RX_DATA                       = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0),
+	MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B                       = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__GPIO3_IO03                         = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__ECSPI2_SS2                         = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_RESET__LCDIF_RESET                        = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__LCDIF_CS                           = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__CA7_MX6ULL_EVENTI                  = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__SAI3_TX_DATA                       = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY                     = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__GPIO3_IO04                         = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__ECSPI2_SS3                         = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA00__LCDIF_DATA00                      = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__PWM1_OUT                          = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN              = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__I2C3_SDA                          = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0),
+	MX6_PAD_LCD_DATA00__GPIO3_IO05                        = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__SRC_BT_CFG00                      = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__SAI1_MCLK                         = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0),
+
+	MX6_PAD_LCD_DATA01__LCDIF_DATA01                      = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__PWM2_OUT                          = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT             = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__I2C3_SCL                          = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0),
+	MX6_PAD_LCD_DATA01__GPIO3_IO06                        = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__SRC_BT_CFG01                      = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__SAI1_TX_SYNC                      = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0),
+
+	MX6_PAD_LCD_DATA02__LCDIF_DATA02                      = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__PWM3_OUT                          = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN              = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__I2C4_SDA                          = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0),
+	MX6_PAD_LCD_DATA02__GPIO3_IO07                        = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__SRC_BT_CFG02                      = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__SAI1_TX_BCLK                      = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0),
+
+	MX6_PAD_LCD_DATA03__LCDIF_DATA03                      = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__PWM4_OUT                          = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT             = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__I2C4_SCL                          = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0),
+	MX6_PAD_LCD_DATA03__GPIO3_IO08                        = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__SRC_BT_CFG03                      = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__SAI1_RX_DATA                      = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0),
+
+	MX6_PAD_LCD_DATA04__LCDIF_DATA04                      = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__UART8_DCE_CTS                     = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__UART8_DTE_RTS                     = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0),
+	MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN              = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__SPDIF_SR_CLK                      = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__GPIO3_IO09                        = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__SRC_BT_CFG04                      = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__SAI1_TX_DATA                      = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA05__LCDIF_DATA05                      = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__UART8_DCE_RTS                     = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0),
+	MX6_PAD_LCD_DATA05__UART8_DTE_CTS                     = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT             = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__SPDIF_OUT                         = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__GPIO3_IO10                        = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__SRC_BT_CFG05                      = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__ECSPI1_SS1                        = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA06__LCDIF_DATA06                      = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__UART7_DCE_CTS                     = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__UART7_DTE_RTS                     = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0),
+	MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN              = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__SPDIF_LOCK                        = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__GPIO3_IO11                        = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__SRC_BT_CFG06                      = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__ECSPI1_SS2                        = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA07__LCDIF_DATA07                      = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__UART7_DCE_RTS                     = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0),
+	MX6_PAD_LCD_DATA07__UART7_DTE_CTS                     = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT             = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK                     = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0),
+	MX6_PAD_LCD_DATA07__GPIO3_IO12                        = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__SRC_BT_CFG07                      = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__ECSPI1_SS3                        = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA08__LCDIF_DATA08                      = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA08__SPDIF_IN                          = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0),
+	MX6_PAD_LCD_DATA08__CSI_DATA16                        = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0),
+	MX6_PAD_LCD_DATA08__EIM_DATA00                        = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA08__GPIO3_IO13                        = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA08__SRC_BT_CFG08                      = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA08__FLEXCAN1_TX                       = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA09__LCDIF_DATA09                      = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA09__SAI3_MCLK                         = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0),
+	MX6_PAD_LCD_DATA09__CSI_DATA17                        = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0),
+	MX6_PAD_LCD_DATA09__EIM_DATA01                        = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA09__GPIO3_IO14                        = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA09__SRC_BT_CFG09                      = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA09__FLEXCAN1_RX                       = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0),
+
+	MX6_PAD_LCD_DATA10__LCDIF_DATA10                      = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__SAI3_RX_SYNC                      = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__CSI_DATA18                        = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0),
+	MX6_PAD_LCD_DATA10__EIM_DATA02                        = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__GPIO3_IO15                        = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__SRC_BT_CFG10                      = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__FLEXCAN2_TX                       = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA11__LCDIF_DATA11                      = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__SAI3_RX_BCLK                      = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__CSI_DATA19                        = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0),
+	MX6_PAD_LCD_DATA11__EIM_DATA03                        = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__GPIO3_IO16                        = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__SRC_BT_CFG11                      = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__FLEXCAN2_RX                       = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0),
+
+	MX6_PAD_LCD_DATA12__LCDIF_DATA12                      = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA12__SAI3_TX_SYNC                      = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0),
+	MX6_PAD_LCD_DATA12__CSI_DATA20                        = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0),
+	MX6_PAD_LCD_DATA12__EIM_DATA04                        = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA12__GPIO3_IO17                        = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA12__SRC_BT_CFG12                      = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA12__ECSPI1_RDY                        = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA13__LCDIF_DATA13                      = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA13__SAI3_TX_BCLK                      = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0),
+	MX6_PAD_LCD_DATA13__CSI_DATA21                        = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0),
+	MX6_PAD_LCD_DATA13__EIM_DATA05                        = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA13__GPIO3_IO18                        = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA13__SRC_BT_CFG13                      = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA13__USDHC2_RESET_B                    = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_LCD_DATA14__LCDIF_DATA14                      = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA14__SAI3_RX_DATA                      = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0),
+	MX6_PAD_LCD_DATA14__CSI_DATA22                        = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0),
+	MX6_PAD_LCD_DATA14__EIM_DATA06                        = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA14__GPIO3_IO19                        = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA14__SRC_BT_CFG14                      = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA14__USDHC2_DATA4                      = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0),
+
+	MX6_PAD_LCD_DATA15__LCDIF_DATA15                      = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__SAI3_TX_DATA                      = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__CSI_DATA23                        = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0),
+	MX6_PAD_LCD_DATA15__EIM_DATA07                        = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__GPIO3_IO20                        = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__SRC_BT_CFG15                      = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__USDHC2_DATA5                      = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0),
+
+	MX6_PAD_LCD_DATA16__LCDIF_DATA16                      = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA16__UART7_DCE_TX                      = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA16__UART7_DTE_RX                      = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0),
+	MX6_PAD_LCD_DATA16__CSI_DATA01                        = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0),
+	MX6_PAD_LCD_DATA16__EIM_DATA08                        = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA16__GPIO3_IO21                        = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA16__SRC_BT_CFG24                      = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA16__USDHC2_DATA6                      = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0),
+
+	MX6_PAD_LCD_DATA17__LCDIF_DATA17                      = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__UART7_DCE_RX                      = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0),
+	MX6_PAD_LCD_DATA17__UART7_DTE_TX                      = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__CSI_DATA00                        = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0),
+	MX6_PAD_LCD_DATA17__EIM_DATA09                        = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__GPIO3_IO22                        = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__SRC_BT_CFG25                      = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__USDHC2_DATA7                      = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0),
+
+	MX6_PAD_LCD_DATA18__LCDIF_DATA18                      = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__PWM5_OUT                          = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__CA7_MX6ULL_EVENTO                 = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__CSI_DATA10                        = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0),
+	MX6_PAD_LCD_DATA18__EIM_DATA10                        = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__GPIO3_IO23                        = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__SRC_BT_CFG26                      = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA18__USDHC2_CMD                        = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0),
+	MX6_PAD_LCD_DATA19__EIM_DATA11                        = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__GPIO3_IO24                        = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__SRC_BT_CFG27                      = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__USDHC2_CLK                        = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0),
+
+	MX6_PAD_LCD_DATA19__LCDIF_DATA19                      = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__PWM6_OUT                          = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY                    = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA19__CSI_DATA11                        = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0),
+	MX6_PAD_LCD_DATA20__EIM_DATA12                        = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__GPIO3_IO25                        = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__SRC_BT_CFG28                      = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__USDHC2_DATA0                      = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0),
+
+	MX6_PAD_LCD_DATA20__LCDIF_DATA20                      = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__UART8_DCE_TX                      = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA20__UART8_DTE_RX                      = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0),
+	MX6_PAD_LCD_DATA20__ECSPI1_SCLK                       = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0),
+	MX6_PAD_LCD_DATA20__CSI_DATA12                        = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0),
+
+	MX6_PAD_LCD_DATA21__LCDIF_DATA21                      = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__UART8_DCE_RX                      = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0),
+	MX6_PAD_LCD_DATA21__UART8_DTE_TX                      = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__ECSPI1_SS0                        = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0),
+	MX6_PAD_LCD_DATA21__CSI_DATA13                        = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0),
+	MX6_PAD_LCD_DATA21__EIM_DATA13                        = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__GPIO3_IO26                        = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__SRC_BT_CFG29                      = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA21__USDHC2_DATA1                      = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0),
+
+	MX6_PAD_LCD_DATA22__LCDIF_DATA22                      = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__MQS_RIGHT                         = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__ECSPI1_MOSI                       = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0),
+	MX6_PAD_LCD_DATA22__CSI_DATA14                        = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0),
+	MX6_PAD_LCD_DATA22__EIM_DATA14                        = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__GPIO3_IO27                        = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__SRC_BT_CFG30                      = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA22__USDHC2_DATA2                      = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0),
+
+	MX6_PAD_LCD_DATA23__LCDIF_DATA23                      = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA23__MQS_LEFT                          = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA23__ECSPI1_MISO                       = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0),
+	MX6_PAD_LCD_DATA23__CSI_DATA15                        = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0),
+	MX6_PAD_LCD_DATA23__EIM_DATA15                        = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA23__GPIO3_IO28                        = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA23__SRC_BT_CFG31                      = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA23__USDHC2_DATA3                      = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0),
+
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B                       = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_RE_B__USDHC2_CLK                         = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0),
+	MX6_PAD_NAND_RE_B__QSPI_B_SCLK                        = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_RE_B__KPP_ROW00                          = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0),
+	MX6_PAD_NAND_RE_B__EIM_EB_B00                         = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_RE_B__GPIO4_IO00                         = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_RE_B__ECSPI3_SS2                         = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B                       = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD                         = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0),
+	MX6_PAD_NAND_WE_B__QSPI_B_SS0_B                       = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_WE_B__KPP_COL00                          = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0),
+	MX6_PAD_NAND_WE_B__EIM_EB_B01                         = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_WE_B__GPIO4_IO01                         = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_WE_B__ECSPI3_SS3                         = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00                   = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0                     = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0),
+	MX6_PAD_NAND_DATA00__QSPI_B_SS1_B                     = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA00__KPP_ROW01                        = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0),
+	MX6_PAD_NAND_DATA00__EIM_AD08                         = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA00__GPIO4_IO02                       = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA00__ECSPI4_RDY                       = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01                   = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1                     = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0),
+	MX6_PAD_NAND_DATA01__QSPI_B_DQS                       = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA01__KPP_COL01                        = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0),
+	MX6_PAD_NAND_DATA01__EIM_AD09                         = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA01__GPIO4_IO03                       = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA01__ECSPI4_SS1                       = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02                   = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2                     = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0),
+	MX6_PAD_NAND_DATA02__QSPI_B_DATA00                    = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA02__KPP_ROW02                        = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0),
+	MX6_PAD_NAND_DATA02__EIM_AD10                         = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA02__GPIO4_IO04                       = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA02__ECSPI4_SS2                       = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03                   = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3                     = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0),
+	MX6_PAD_NAND_DATA03__QSPI_B_DATA01                    = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA03__KPP_COL02                        = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0),
+	MX6_PAD_NAND_DATA03__EIM_AD11                         = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA03__GPIO4_IO05                       = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA03__ECSPI4_SS3                       = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04                   = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4                     = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0),
+	MX6_PAD_NAND_DATA04__QSPI_B_DATA02                    = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA04__ECSPI4_SCLK                      = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0),
+	MX6_PAD_NAND_DATA04__EIM_AD12                         = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA04__GPIO4_IO06                       = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA04__UART2_DCE_TX                     = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA04__UART2_DTE_RX                     = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0),
+
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05                   = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5                     = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0),
+	MX6_PAD_NAND_DATA05__QSPI_B_DATA03                    = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA05__ECSPI4_MOSI                      = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0),
+	MX6_PAD_NAND_DATA05__EIM_AD13                         = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA05__GPIO4_IO07                       = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA05__UART2_DCE_RX                     = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0),
+	MX6_PAD_NAND_DATA05__UART2_DTE_TX                     = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06                   = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6                     = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0),
+	MX6_PAD_NAND_DATA06__SAI2_RX_BCLK                     = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA06__ECSPI4_MISO                      = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0),
+	MX6_PAD_NAND_DATA06__EIM_AD14                         = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA06__GPIO4_IO08                       = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA06__UART2_DCE_CTS                    = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA06__UART2_DTE_RTS                    = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0),
+
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07                   = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7                     = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0),
+	MX6_PAD_NAND_DATA07__QSPI_A_SS1_B                     = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA07__ECSPI4_SS0                       = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0),
+	MX6_PAD_NAND_DATA07__EIM_AD15                         = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA07__GPIO4_IO09                       = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DATA07__UART2_DCE_RTS                    = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0),
+	MX6_PAD_NAND_DATA07__UART2_DTE_CTS                    = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_ALE__RAWNAND_ALE                         = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__USDHC2_RESET_B                      = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__QSPI_A_DQS                          = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__PWM3_OUT                            = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__EIM_ADDR17                          = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__GPIO4_IO10                          = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_ALE__ECSPI3_SS1                          = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B                       = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__USDHC1_RESET_B                     = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__QSPI_A_SCLK                        = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__PWM4_OUT                           = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__EIM_BCLK                           = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__GPIO4_IO11                         = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_WP_B__ECSPI3_RDY                         = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B                 = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__USDHC1_DATA4                    = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__QSPI_A_DATA00                   = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__ECSPI3_SS0                      = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0),
+	MX6_PAD_NAND_READY_B__EIM_CS1_B                       = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__GPIO4_IO12                      = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__UART3_DCE_TX                    = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0),
+	MX6_PAD_NAND_READY_B__UART3_DTE_RX                    = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0),
+
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B                     = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE0_B__USDHC1_DATA5                      = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE0_B__QSPI_A_DATA01                     = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE0_B__ECSPI3_SCLK                       = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0),
+	MX6_PAD_NAND_CE0_B__EIM_DTACK_B                       = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE0_B__GPIO4_IO13                        = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE0_B__UART3_DCE_RX                      = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0),
+	MX6_PAD_NAND_CE0_B__UART3_DTE_TX                      = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B                     = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__USDHC1_DATA6                      = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__QSPI_A_DATA02                     = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__ECSPI3_MOSI                       = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0),
+	MX6_PAD_NAND_CE1_B__EIM_ADDR18                        = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__GPIO4_IO14                        = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__UART3_DCE_CTS                     = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0),
+	MX6_PAD_NAND_CE1_B__UART3_DTE_RTS                     = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0),
+
+	MX6_PAD_NAND_CLE__RAWNAND_CLE                         = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_CLE__USDHC1_DATA7                        = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0),
+	MX6_PAD_NAND_CLE__QSPI_A_DATA03                       = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_CLE__ECSPI3_MISO                         = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0),
+	MX6_PAD_NAND_CLE__EIM_ADDR16                          = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_CLE__GPIO4_IO15                          = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_CLE__UART3_DCE_RTS                       = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0),
+	MX6_PAD_NAND_CLE__UART3_DTE_CTS                       = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0),
+
+	MX6_PAD_NAND_DQS__RAWNAND_DQS                         = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0),
+	MX6_PAD_NAND_DQS__CSI_FIELD                           = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0),
+	MX6_PAD_NAND_DQS__QSPI_A_SS0_B                        = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0),
+	MX6_PAD_NAND_DQS__PWM5_OUT                            = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0),
+	MX6_PAD_NAND_DQS__EIM_WAIT                            = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0),
+	MX6_PAD_NAND_DQS__GPIO4_IO16                          = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0),
+	MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01                    = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0),
+	MX6_PAD_NAND_DQS__SPDIF_EXT_CLK                       = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0),
+
+	MX6_PAD_SD1_CMD__USDHC1_CMD                           = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__GPT2_COMPARE1                        = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__SAI2_RX_SYNC                         = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__SPDIF_OUT                            = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__EIM_ADDR19                           = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__GPIO2_IO16                           = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00                     = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0),
+	MX6_PAD_SD1_CMD__USB_OTG1_PWR                         = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_CLK__USDHC1_CLK                           = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__GPT2_COMPARE2                        = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__SAI2_MCLK                            = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0),
+	MX6_PAD_SD1_CLK__SPDIF_IN                             = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0),
+	MX6_PAD_SD1_CLK__EIM_ADDR20                           = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__GPIO2_IO17                           = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_CLK__USB_OTG1_OC                          = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0),
+
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0                       = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__GPT2_COMPARE3                      = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__SAI2_TX_SYNC                       = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0),
+	MX6_PAD_SD1_DATA0__FLEXCAN1_TX                        = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__EIM_ADDR21                         = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__GPIO2_IO18                         = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID                     = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0),
+
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1                       = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA1__GPT2_CLK                           = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0),
+	MX6_PAD_SD1_DATA1__SAI2_TX_BCLK                       = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0),
+	MX6_PAD_SD1_DATA1__FLEXCAN1_RX                        = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0),
+	MX6_PAD_SD1_DATA1__EIM_ADDR22                         = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA1__GPIO2_IO19                         = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA1__USB_OTG2_PWR                       = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2                       = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__GPT2_CAPTURE1                      = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0),
+	MX6_PAD_SD1_DATA2__SAI2_RX_DATA                       = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0),
+	MX6_PAD_SD1_DATA2__FLEXCAN2_TX                        = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__EIM_ADDR23                         = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__GPIO2_IO20                         = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__CCM_CLKO1                          = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA2__USB_OTG2_OC                        = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0),
+
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3                       = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__GPT2_CAPTURE2                      = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0),
+	MX6_PAD_SD1_DATA3__SAI2_TX_DATA                       = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__FLEXCAN2_RX                        = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0),
+	MX6_PAD_SD1_DATA3__EIM_ADDR24                         = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__GPIO2_IO21                         = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__CCM_CLKO2                          = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0),
+	MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID                     = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0),
+
+	MX6_PAD_CSI_MCLK__CSI_MCLK                            = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__USDHC2_CD_B                         = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0),
+	MX6_PAD_CSI_MCLK__RAWNAND_CE2_B                       = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__I2C1_SDA                            = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0),
+	MX6_PAD_CSI_MCLK__EIM_CS0_B                           = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__GPIO4_IO17                          = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL                   = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__UART6_DCE_TX                        = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0),
+	MX6_PAD_CSI_MCLK__UART6_DTE_RX                        = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0),
+
+	MX6_PAD_CSI_PIXCLK__CSI_PIXCLK                        = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0),
+	MX6_PAD_CSI_PIXCLK__USDHC2_WP                         = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0),
+	MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B                     = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_PIXCLK__I2C1_SCL                          = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0),
+	MX6_PAD_CSI_PIXCLK__EIM_OE                            = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_PIXCLK__GPIO4_IO18                        = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5                     = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_PIXCLK__UART6_DCE_RX                      = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0),
+	MX6_PAD_CSI_PIXCLK__UART6_DTE_TX                      = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_CSI_VSYNC__CSI_VSYNC                          = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0),
+	MX6_PAD_CSI_VSYNC__USDHC2_CLK                         = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0),
+	MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK                     = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_VSYNC__I2C2_SDA                           = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0),
+	MX6_PAD_CSI_VSYNC__EIM_RW                             = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_VSYNC__GPIO4_IO19                         = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_VSYNC__PWM7_OUT                           = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_VSYNC__UART6_DCE_RTS                      = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0),
+	MX6_PAD_CSI_VSYNC__UART6_DTE_CTS                      = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_CSI_HSYNC__CSI_HSYNC                          = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0),
+	MX6_PAD_CSI_HSYNC__USDHC2_CMD                         = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0),
+	MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD                      = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_HSYNC__I2C2_SCL                           = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0),
+	MX6_PAD_CSI_HSYNC__EIM_LBA_B                          = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_HSYNC__GPIO4_IO20                         = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_HSYNC__PWM8_OUT                           = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_HSYNC__UART6_DCE_CTS                      = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0),
+	MX6_PAD_CSI_HSYNC__UART6_DTE_RTS                      = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0),
+
+	MX6_PAD_CSI_DATA00__CSI_DATA02                        = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0),
+	MX6_PAD_CSI_DATA00__USDHC2_DATA0                      = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0),
+	MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B                  = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA00__ECSPI2_SCLK                       = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0),
+	MX6_PAD_CSI_DATA00__EIM_AD00                          = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA00__GPIO4_IO21                        = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA00__SRC_INT_BOOT                      = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA00__UART5_DCE_TX                      = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA00__UART5_DTE_RX                      = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0),
+
+	MX6_PAD_CSI_DATA01__CSI_DATA03                        = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0),
+	MX6_PAD_CSI_DATA01__USDHC2_DATA1                      = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0),
+	MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN                   = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA01__ECSPI2_SS0                        = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0),
+	MX6_PAD_CSI_DATA01__EIM_AD01                          = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA01__GPIO4_IO22                        = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA01__SAI1_MCLK                         = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0),
+	MX6_PAD_CSI_DATA01__UART5_DCE_RX                      = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0),
+	MX6_PAD_CSI_DATA01__UART5_DTE_TX                      = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0),
+
+	MX6_PAD_CSI_DATA02__CSI_DATA04                        = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0),
+	MX6_PAD_CSI_DATA02__USDHC2_DATA2                      = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0),
+	MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD                   = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA02__ECSPI2_MOSI                       = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0),
+	MX6_PAD_CSI_DATA02__EIM_AD02                          = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA02__GPIO4_IO23                        = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA02__SAI1_RX_SYNC                      = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA02__UART5_DCE_RTS                     = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0),
+	MX6_PAD_CSI_DATA02__UART5_DTE_CTS                     = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_CSI_DATA03__CSI_DATA05                        = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0),
+	MX6_PAD_CSI_DATA03__USDHC2_DATA3                      = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0),
+	MX6_PAD_CSI_DATA03__SIM2_PORT1_PD                     = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA03__ECSPI2_MISO                       = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0),
+	MX6_PAD_CSI_DATA03__EIM_AD03                          = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA03__GPIO4_IO24                        = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA03__SAI1_RX_BCLK                      = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA03__UART5_DCE_CTS                     = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA03__UART5_DTE_RTS                     = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0),
+
+	MX6_PAD_CSI_DATA04__CSI_DATA06                        = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0),
+	MX6_PAD_CSI_DATA04__USDHC2_DATA4                      = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0),
+	MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK                    = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA04__ECSPI1_SCLK                       = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0),
+	MX6_PAD_CSI_DATA04__EIM_AD04                          = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA04__GPIO4_IO25                        = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA04__SAI1_TX_SYNC                      = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0),
+	MX6_PAD_CSI_DATA04__USDHC1_WP                         = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0),
+
+	MX6_PAD_CSI_DATA05__CSI_DATA07                        = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0),
+	MX6_PAD_CSI_DATA05__USDHC2_DATA5                      = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0),
+	MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B                  = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA05__ECSPI1_SS0                        = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0),
+	MX6_PAD_CSI_DATA05__EIM_AD05                          = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA05__GPIO4_IO26                        = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA05__SAI1_TX_BCLK                      = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0),
+	MX6_PAD_CSI_DATA05__USDHC1_CD_B                       = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0),
+
+	MX6_PAD_CSI_DATA06__CSI_DATA08                        = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0),
+	MX6_PAD_CSI_DATA06__USDHC2_DATA6                      = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0),
+	MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN                   = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA06__ECSPI1_MOSI                       = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0),
+	MX6_PAD_CSI_DATA06__EIM_AD06                          = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA06__GPIO4_IO27                        = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA06__SAI1_RX_DATA                      = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0),
+	MX6_PAD_CSI_DATA06__USDHC1_RESET_B                    = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0),
+
+	MX6_PAD_CSI_DATA07__CSI_DATA09                        = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0),
+	MX6_PAD_CSI_DATA07__USDHC2_DATA7                      = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0),
+	MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD                   = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA07__ECSPI1_MISO                       = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0),
+	MX6_PAD_CSI_DATA07__EIM_AD07                          = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA07__GPIO4_IO28                        = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA07__SAI1_TX_DATA                      = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0),
+	MX6_PAD_CSI_DATA07__USDHC1_VSELECT                    = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0),
+};
+#endif  /* __ASM_ARCH_IMX6ULL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
new file mode 100644
index 0000000..71ad0e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
@@ -0,0 +1,1057 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __MXC_HDMI_H__
+#define __MXC_HDMI_H__
+
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void);
+void imx_setup_hdmi(void);
+#endif
+
+/*
+ * Hdmi controller registers
+ */
+struct hdmi_regs {
+	/*Identification Registers */
+	u8 design_id;			/* 0x000 */
+	u8 revision_id;			/* 0x001 */
+	u8 product_id0;			/* 0x002 */
+	u8 product_id1;			/* 0x003 */
+	u8 config0_id;			/* 0x004 */
+	u8 config1_id;			/* 0x005 */
+	u8 config2_id;			/* 0x006 */
+	u8 config3_id;			/* 0x007 */
+	u8 reserved1[0xf8];
+	/* Interrupt Registers */
+	u8 ih_fc_stat0;			/* 0x100 */
+	u8 ih_fc_stat1;			/* 0x101 */
+	u8 ih_fc_stat2;			/* 0x102 */
+	u8 ih_as_stat0;			/* 0x103 */
+	u8 ih_phy_stat0;		/* 0x104 */
+	u8 ih_i2cm_stat0;		/* 0x105 */
+	u8 ih_cec_stat0;		/* 0x106 */
+	u8 ih_vp_stat0;			/* 0x107 */
+	u8 ih_i2cmphy_stat0;		/* 0x108 */
+	u8 ih_ahbdmaaud_stat0;		/* 0x109 */
+	u8 reserved2[0x76];
+	u8 ih_mute_fc_stat0;		/* 0x180 */
+	u8 ih_mute_fc_stat1;		/* 0x181 */
+	u8 ih_mute_fc_stat2;		/* 0x182 */
+	u8 ih_mute_as_stat0;		/* 0x183 */
+	u8 ih_mute_phy_stat0;		/* 0x184 */
+	u8 ih_mute_i2cm_stat0;		/* 0x185 */
+	u8 ih_mute_cec_stat0;		/* 0x186 */
+	u8 ih_mute_vp_stat0;		/* 0x187 */
+	u8 ih_mute_i2cmphy_stat0;	/* 0x188 */
+	u8 ih_mute_ahbdmaaud_stat0;	/* 0x189 */
+	u8 reserved3[0x75];
+	u8 ih_mute;			/* 0x1ff */
+	/* Video Sample Registers */
+	u8 tx_invid0;			/* 0x200 */
+	u8 tx_instuffing;		/* 0x201 */
+	u8 tx_gydata0;			/* 0x202 */
+	u8 tx_gydata1;			/* 0x203 */
+	u8 tx_rcrdata0;			/* 0x204 */
+	u8 tx_rcrdata1;			/* 0x205 */
+	u8 tx_bcbdata0;			/* 0x206 */
+	u8 tx_bcbdata1;			/* 0x207 */
+	u8 reserved4[0x5f8];
+	/* Video Packetizer Registers */
+	u8 vp_status;			/* 0x800 */
+	u8 vp_pr_cd;			/* 0x801 */
+	u8 vp_stuff;			/* 0x802 */
+	u8 vp_remap;			/* 0x803 */
+	u8 vp_conf;			/* 0x804 */
+	u8 vp_stat;			/* 0x805 */
+	u8 vp_int;			/* 0x806 */
+	u8 vp_mask;			/* 0x807 */
+	u8 vp_pol;			/* 0x808 */
+	u8 reserved5[0x7f7];
+	/* Frame Composer Registers */
+	u8 fc_invidconf;		/* 0x1000 */
+	u8 fc_inhactv0;			/* 0x1001 */
+	u8 fc_inhactv1;			/* 0x1002 */
+	u8 fc_inhblank0;		/* 0x1003 */
+	u8 fc_inhblank1;		/* 0x1004 */
+	u8 fc_invactv0;			/* 0x1005 */
+	u8 fc_invactv1;			/* 0x1006 */
+	u8 fc_invblank;			/* 0x1007 */
+	u8 fc_hsyncindelay0;		/* 0x1008 */
+	u8 fc_hsyncindelay1;		/* 0x1009 */
+	u8 fc_hsyncinwidth0;		/* 0x100a */
+	u8 fc_hsyncinwidth1;		/* 0x100b */
+	u8 fc_vsyncindelay;		/* 0x100c */
+	u8 fc_vsyncinwidth;		/* 0x100d */
+	u8 fc_infreq0;			/* 0x100e */
+	u8 fc_infreq1;			/* 0x100f */
+	u8 fc_infreq2;			/* 0x1010 */
+	u8 fc_ctrldur;			/* 0x1011 */
+	u8 fc_exctrldur;		/* 0x1012 */
+	u8 fc_exctrlspac;		/* 0x1013 */
+	u8 fc_ch0pream;			/* 0x1014 */
+	u8 fc_ch1pream;			/* 0x1015 */
+	u8 fc_ch2pream;			/* 0x1016 */
+	u8 fc_aviconf3;			/* 0x1017 */
+	u8 fc_gcp;			/* 0x1018 */
+	u8 fc_aviconf0;			/* 0x1019 */
+	u8 fc_aviconf1;			/* 0x101a */
+	u8 fc_aviconf2;			/* 0x101b */
+	u8 fc_avivid;			/* 0x101c */
+	u8 fc_avietb0;			/* 0x101d */
+	u8 fc_avietb1;			/* 0x101e */
+	u8 fc_avisbb0;			/* 0x101f */
+	u8 fc_avisbb1;			/* 0x1020 */
+	u8 fc_avielb0;			/* 0x1021 */
+	u8 fc_avielb1;			/* 0x1022 */
+	u8 fc_avisrb0;			/* 0x1023 */
+	u8 fc_avisrb1;			/* 0x1024 */
+	u8 fc_audiconf0;		/* 0x1025 */
+	u8 fc_audiconf1;		/* 0x1026 */
+	u8 fc_audiconf2;		/* 0x1027 */
+	u8 fc_audiconf3;		/* 0x1028 */
+	u8 fc_vsdieeeid0;		/* 0x1029 */
+	u8 fc_vsdsize;			/* 0x102a */
+	u8 reserved6[5];
+	u8 fc_vsdieeeid1;		/* 0x1030 */
+	u8 fc_vsdieeeid2;		/* 0x1031 */
+	u8 fc_vsdpayload0;		/* 0x1032 */
+	u8 fc_vsdpayload1;		/* 0x1033 */
+	u8 fc_vsdpayload2;		/* 0x1034 */
+	u8 fc_vsdpayload3;		/* 0x1035 */
+	u8 fc_vsdpayload4;		/* 0x1036 */
+	u8 fc_vsdpayload5;		/* 0x1037 */
+	u8 fc_vsdpayload6;		/* 0x1038 */
+	u8 fc_vsdpayload7;		/* 0x1039 */
+	u8 fc_vsdpayload8;		/* 0x103a */
+	u8 fc_vsdpayload9;		/* 0x103b */
+	u8 fc_vsdpayload10;		/* 0x103c */
+	u8 fc_vsdpayload11;		/* 0x103d */
+	u8 fc_vsdpayload12;		/* 0x103e */
+	u8 fc_vsdpayload13;		/* 0x103f */
+	u8 fc_vsdpayload14;		/* 0x1040 */
+	u8 fc_vsdpayload15;		/* 0x1041 */
+	u8 fc_vsdpayload16;		/* 0x1042 */
+	u8 fc_vsdpayload17;		/* 0x1043 */
+	u8 fc_vsdpayload18;		/* 0x1044 */
+	u8 fc_vsdpayload19;		/* 0x1045 */
+	u8 fc_vsdpayload20;		/* 0x1046 */
+	u8 fc_vsdpayload21;		/* 0x1047 */
+	u8 fc_vsdpayload22;		/* 0x1048 */
+	u8 fc_vsdpayload23;		/* 0x1049 */
+	u8 fc_spdvendorname0;		/* 0x104a */
+	u8 fc_spdvendorname1;		/* 0x104b */
+	u8 fc_spdvendorname2;		/* 0x104c */
+	u8 fc_spdvendorname3;		/* 0x104d */
+	u8 fc_spdvendorname4;		/* 0x104e */
+	u8 fc_spdvendorname5;		/* 0x104f */
+	u8 fc_spdvendorname6;		/* 0x1050 */
+	u8 fc_spdvendorname7;		/* 0x1051 */
+	u8 fc_sdpproductname0;		/* 0x1052 */
+	u8 fc_sdpproductname1;		/* 0x1053 */
+	u8 fc_sdpproductname2;		/* 0x1054 */
+	u8 fc_sdpproductname3;		/* 0x1055 */
+	u8 fc_sdpproductname4;		/* 0x1056 */
+	u8 fc_sdpproductname5;		/* 0x1057 */
+	u8 fc_sdpproductname6;		/* 0x1058 */
+	u8 fc_sdpproductname7;		/* 0x1059 */
+	u8 fc_sdpproductname8;		/* 0x105a */
+	u8 fc_sdpproductname9;		/* 0x105b */
+	u8 fc_sdpproductname10;		/* 0x105c */
+	u8 fc_sdpproductname11;		/* 0x105d */
+	u8 fc_sdpproductname12;		/* 0x105e */
+	u8 fc_sdpproductname13;		/* 0x105f */
+	u8 fc_sdpproductname14;		/* 0x1060 */
+	u8 fc_spdproductname15;		/* 0x1061 */
+	u8 fc_spddeviceinf;		/* 0x1062 */
+	u8 fc_audsconf;			/* 0x1063 */
+	u8 fc_audsstat;			/* 0x1064 */
+	u8 reserved7[0xb];
+	u8 fc_datach0fill;		/* 0x1070 */
+	u8 fc_datach1fill;		/* 0x1071 */
+	u8 fc_datach2fill;		/* 0x1072 */
+	u8 fc_ctrlqhigh;		/* 0x1073 */
+	u8 fc_ctrlqlow;			/* 0x1074 */
+	u8 fc_acp0;			/* 0x1075 */
+	u8 fc_acp28;			/* 0x1076 */
+	u8 fc_acp27;			/* 0x1077 */
+	u8 fc_acp26;			/* 0x1078 */
+	u8 fc_acp25;			/* 0x1079 */
+	u8 fc_acp24;			/* 0x107a */
+	u8 fc_acp23;			/* 0x107b */
+	u8 fc_acp22;			/* 0x107c */
+	u8 fc_acp21;			/* 0x107d */
+	u8 fc_acp20;			/* 0x107e */
+	u8 fc_acp19;			/* 0x107f */
+	u8 fc_acp18;			/* 0x1080 */
+	u8 fc_acp17;			/* 0x1081 */
+	u8 fc_acp16;			/* 0x1082 */
+	u8 fc_acp15;			/* 0x1083 */
+	u8 fc_acp14;			/* 0x1084 */
+	u8 fc_acp13;			/* 0x1085 */
+	u8 fc_acp12;			/* 0x1086 */
+	u8 fc_acp11;			/* 0x1087 */
+	u8 fc_acp10;			/* 0x1088 */
+	u8 fc_acp9;			/* 0x1089 */
+	u8 fc_acp8;			/* 0x108a */
+	u8 fc_acp7;			/* 0x108b */
+	u8 fc_acp6;			/* 0x108c */
+	u8 fc_acp5;			/* 0x108d */
+	u8 fc_acp4;			/* 0x108e */
+	u8 fc_acp3;			/* 0x108f */
+	u8 fc_acp2;			/* 0x1090 */
+	u8 fc_acp1;			/* 0x1091 */
+	u8 fc_iscr1_0;			/* 0x1092 */
+	u8 fc_iscr1_16;			/* 0x1093 */
+	u8 fc_iscr1_15;			/* 0x1094 */
+	u8 fc_iscr1_14;			/* 0x1095 */
+	u8 fc_iscr1_13;			/* 0x1096 */
+	u8 fc_iscr1_12;			/* 0x1097 */
+	u8 fc_iscr1_11;			/* 0x1098 */
+	u8 fc_iscr1_10;			/* 0x1099 */
+	u8 fc_iscr1_9;			/* 0x109a */
+	u8 fc_iscr1_8;			/* 0x109b */
+	u8 fc_iscr1_7;			/* 0x109c */
+	u8 fc_iscr1_6;			/* 0x109d */
+	u8 fc_iscr1_5;			/* 0x109e */
+	u8 fc_iscr1_4;			/* 0x109f */
+	u8 fc_iscr1_3;			/* 0x10a0 */
+	u8 fc_iscr1_2;			/* 0x10a1 */
+	u8 fc_iscr1_1;			/* 0x10a2 */
+	u8 fc_iscr2_15;			/* 0x10a3 */
+	u8 fc_iscr2_14;			/* 0x10a4 */
+	u8 fc_iscr2_13;			/* 0x10a5 */
+	u8 fc_iscr2_12;			/* 0x10a6 */
+	u8 fc_iscr2_11;			/* 0x10a7 */
+	u8 fc_iscr2_10;			/* 0x10a8 */
+	u8 fc_iscr2_9;			/* 0x10a9 */
+	u8 fc_iscr2_8;			/* 0x10aa */
+	u8 fc_iscr2_7;			/* 0x10ab */
+	u8 fc_iscr2_6;			/* 0x10ac */
+	u8 fc_iscr2_5;			/* 0x10ad */
+	u8 fc_iscr2_4;			/* 0x10ae */
+	u8 fc_iscr2_3;			/* 0x10af */
+	u8 fc_iscr2_2;			/* 0x10b0 */
+	u8 fc_iscr2_1;			/* 0x10b1 */
+	u8 fc_iscr2_0;			/* 0x10b2 */
+	u8 fc_datauto0;			/* 0x10b3 */
+	u8 fc_datauto1;			/* 0x10b4 */
+	u8 fc_datauto2;			/* 0x10b5 */
+	u8 fc_datman;			/* 0x10b6 */
+	u8 fc_datauto3;			/* 0x10b7 */
+	u8 fc_rdrb0;			/* 0x10b8 */
+	u8 fc_rdrb1;			/* 0x10b9 */
+	u8 fc_rdrb2;			/* 0x10ba */
+	u8 fc_rdrb3;			/* 0x10bb */
+	u8 fc_rdrb4;			/* 0x10bc */
+	u8 fc_rdrb5;			/* 0x10bd */
+	u8 fc_rdrb6;			/* 0x10be */
+	u8 fc_rdrb7;			/* 0x10bf */
+	u8 reserved8[0x10];
+	u8 fc_stat0;			/* 0x10d0 */
+	u8 fc_int0;			/* 0x10d1 */
+	u8 fc_mask0;			/* 0x10d2 */
+	u8 fc_pol0;			/* 0x10d3 */
+	u8 fc_stat1;			/* 0x10d4 */
+	u8 fc_int1;			/* 0x10d5 */
+	u8 fc_mask1;			/* 0x10d6 */
+	u8 fc_pol1;			/* 0x10d7 */
+	u8 fc_stat2;			/* 0x10d8 */
+	u8 fc_int2;			/* 0x10d9 */
+	u8 fc_mask2;			/* 0x10da */
+	u8 fc_pol2;			/* 0x10db */
+	u8 reserved9[0x4];
+	u8 fc_prconf;			/* 0x10e0 */
+	u8 reserved10[0x1f];
+	u8 fc_gmd_stat;			/* 0x1100 */
+	u8 fc_gmd_en;			/* 0x1101 */
+	u8 fc_gmd_up;			/* 0x1102 */
+	u8 fc_gmd_conf;			/* 0x1103 */
+	u8 fc_gmd_hb;			/* 0x1104 */
+	u8 fc_gmd_pb0;			/* 0x1105 */
+	u8 fc_gmd_pb1;			/* 0x1106 */
+	u8 fc_gmd_pb2;			/* 0x1107 */
+	u8 fc_gmd_pb3;			/* 0x1108 */
+	u8 fc_gmd_pb4;			/* 0x1109 */
+	u8 fc_gmd_pb5;			/* 0x110a */
+	u8 fc_gmd_pb6;			/* 0x110b */
+	u8 fc_gmd_pb7;			/* 0x110c */
+	u8 fc_gmd_pb8;			/* 0x110d */
+	u8 fc_gmd_pb9;			/* 0x110e */
+	u8 fc_gmd_pb10;			/* 0x110f */
+	u8 fc_gmd_pb11;			/* 0x1110 */
+	u8 fc_gmd_pb12;			/* 0x1111 */
+	u8 fc_gmd_pb13;			/* 0x1112 */
+	u8 fc_gmd_pb14;			/* 0x1113 */
+	u8 fc_gmd_pb15;			/* 0x1114 */
+	u8 fc_gmd_pb16;			/* 0x1115 */
+	u8 fc_gmd_pb17;			/* 0x1116 */
+	u8 fc_gmd_pb18;			/* 0x1117 */
+	u8 fc_gmd_pb19;			/* 0x1118 */
+	u8 fc_gmd_pb20;			/* 0x1119 */
+	u8 fc_gmd_pb21;			/* 0x111a */
+	u8 fc_gmd_pb22;			/* 0x111b */
+	u8 fc_gmd_pb23;			/* 0x111c */
+	u8 fc_gmd_pb24;			/* 0x111d */
+	u8 fc_gmd_pb25;			/* 0x111e */
+	u8 fc_gmd_pb26;			/* 0x111f */
+	u8 fc_gmd_pb27;			/* 0x1120 */
+	u8 reserved11[0xdf];
+	u8 fc_dbgforce;			/* 0x1200 */
+	u8 fc_dbgaud0ch0;		/* 0x1201 */
+	u8 fc_dbgaud1ch0;		/* 0x1202 */
+	u8 fc_dbgaud2ch0;		/* 0x1203 */
+	u8 fc_dbgaud0ch1;		/* 0x1204 */
+	u8 fc_dbgaud1ch1;		/* 0x1205 */
+	u8 fc_dbgaud2ch1;		/* 0x1206 */
+	u8 fc_dbgaud0ch2;		/* 0x1207 */
+	u8 fc_dbgaud1ch2;		/* 0x1208 */
+	u8 fc_dbgaud2ch2;		/* 0x1209 */
+	u8 fc_dbgaud0ch3;		/* 0x120a */
+	u8 fc_dbgaud1ch3;		/* 0x120b */
+	u8 fc_dbgaud2ch3;		/* 0x120c */
+	u8 fc_dbgaud0ch4;		/* 0x120d */
+	u8 fc_dbgaud1ch4;		/* 0x120e */
+	u8 fc_dbgaud2ch4;		/* 0x120f */
+	u8 fc_dbgaud0ch5;		/* 0x1210 */
+	u8 fc_dbgaud1ch5;		/* 0x1211 */
+	u8 fc_dbgaud2ch5;		/* 0x1212 */
+	u8 fc_dbgaud0ch6;		/* 0x1213 */
+	u8 fc_dbgaud1ch6;		/* 0x1214 */
+	u8 fc_dbgaud2ch6;		/* 0x1215 */
+	u8 fc_dbgaud0ch7;		/* 0x1216 */
+	u8 fc_dbgaud1ch7;		/* 0x1217 */
+	u8 fc_dbgaud2ch7;		/* 0x1218 */
+	u8 fc_dbgtmds0;			/* 0x1219 */
+	u8 fc_dbgtmds1;			/* 0x121a */
+	u8 fc_dbgtmds2;			/* 0x121b */
+	u8 reserved12[0x1de4];
+	/* Hdmi Source Phy Registers */
+	u8 phy_conf0;			/* 0x3000 */
+	u8 phy_tst0;			/* 0x3001 */
+	u8 phy_tst1;			/* 0x3002 */
+	u8 phy_tst2;			/* 0x3003 */
+	u8 phy_stat0;			/* 0x3004 */
+	u8 phy_int0;			/* 0x3005 */
+	u8 phy_mask0;			/* 0x3006 */
+	u8 phy_pol0;			/* 0x3007 */
+	u8 reserved13[0x18];
+	/* Hdmi Master Phy Registers */
+	u8 phy_i2cm_slave_addr;		/* 0x3020 */
+	u8 phy_i2cm_address_addr;	/* 0x3021 */
+	u8 phy_i2cm_datao_1_addr;	/* 0x3022 */
+	u8 phy_i2cm_datao_0_addr;	/* 0x3023 */
+	u8 phy_i2cm_datai_1_addr;	/* 0x3024 */
+	u8 phy_i2cm_datai_0_addr;	/* 0x3025 */
+	u8 phy_i2cm_operation_addr;	/* 0x3026 */
+	u8 phy_i2cm_int_addr;		/* 0x3027 */
+	u8 phy_i2cm_ctlint_addr;	/* 0x3028 */
+	u8 phy_i2cm_div_addr;		/* 0x3029 */
+	u8 phy_i2cm_softrstz_addr;	/* 0x302a */
+	u8 phy_i2cm_ss_scl_hcnt_1_addr;	/* 0x302b */
+	u8 phy_i2cm_ss_scl_hcnt_0_addr;	/* 0x302c */
+	u8 phy_i2cm_ss_scl_lcnt_1_addr;	/* 0x302d */
+	u8 phy_i2cm_ss_scl_lcnt_0_addr;	/* 0x302e */
+	u8 phy_i2cm_fs_scl_hcnt_1_addr;	/* 0x302f */
+	u8 phy_i2cm_fs_scl_hcnt_0_addr;	/* 0x3030 */
+	u8 phy_i2cm_fs_scl_lcnt_1_addr;	/* 0x3031 */
+	u8 phy_i2cm_fs_scl_lcnt_0_addr;	/* 0x3032 */
+	u8 reserved14[0xcd];
+	/* Audio Sampler Registers */
+	u8 aud_conf0;			/* 0x3100 */
+	u8 aud_conf1;			/* 0x3101 */
+	u8 aud_int;			/* 0x3102 */
+	u8 aud_conf2;			/* 0x3103 */
+	u8 reserved15[0xfc];
+	u8 aud_n1;			/* 0x3200 */
+	u8 aud_n2;			/* 0x3201 */
+	u8 aud_n3;			/* 0x3202 */
+	u8 aud_cts1;			/* 0x3203 */
+	u8 aud_cts2;			/* 0x3204 */
+	u8 aud_cts3;			/* 0x3205 */
+	u8 aud_inputclkfs;		/* 0x3206 */
+	u8 reserved16[0xfb];
+	u8 aud_spdifint;		/* 0x3302 */
+	u8 reserved17[0xfd];
+	u8 aud_conf0_hbr;		/* 0x3400 */
+	u8 aud_hbr_status;		/* 0x3401 */
+	u8 aud_hbr_int;			/* 0x3402 */
+	u8 aud_hbr_pol;			/* 0x3403 */
+	u8 aud_hbr_mask;		/* 0x3404 */
+	u8 reserved18[0xfb];
+	/*
+	 * Generic Parallel Audio Interface Registers
+	 * Not used as GPAUD interface is not enabled in hw
+	 */
+	u8 gp_conf0;			/* 0x3500 */
+	u8 gp_conf1;			/* 0x3501 */
+	u8 gp_conf2;			/* 0x3502 */
+	u8 gp_stat;			/* 0x3503 */
+	u8 gp_int;			/* 0x3504 */
+	u8 gp_mask;			/* 0x3505 */
+	u8 gp_pol;			/* 0x3506 */
+	u8 reserved19[0xf9];
+	/* Audio DMA Registers */
+	u8 ahb_dma_conf0;		/* 0x3600 */
+	u8 ahb_dma_start;		/* 0x3601 */
+	u8 ahb_dma_stop;		/* 0x3602 */
+	u8 ahb_dma_thrsld;		/* 0x3603 */
+	u8 ahb_dma_straddr0;		/* 0x3604 */
+	u8 ahb_dma_straddr1;		/* 0x3605 */
+	u8 ahb_dma_straddr2;		/* 0x3606 */
+	u8 ahb_dma_straddr3;		/* 0x3607 */
+	u8 ahb_dma_stpaddr0;		/* 0x3608 */
+	u8 ahb_dma_stpaddr1;		/* 0x3609 */
+	u8 ahb_dma_stpaddr2;		/* 0x360a */
+	u8 ahb_dma_stpaddr3;		/* 0x360b */
+	u8 ahb_dma_bstaddr0;		/* 0x360c */
+	u8 ahb_dma_bstaddr1;		/* 0x360d */
+	u8 ahb_dma_bstaddr2;		/* 0x360e */
+	u8 ahb_dma_bstaddr3;		/* 0x360f */
+	u8 ahb_dma_mblength0;		/* 0x3610 */
+	u8 ahb_dma_mblength1;		/* 0x3611 */
+	u8 ahb_dma_stat;		/* 0x3612 */
+	u8 ahb_dma_int;			/* 0x3613 */
+	u8 ahb_dma_mask;		/* 0x3614 */
+	u8 ahb_dma_pol;			/* 0x3615 */
+	u8 ahb_dma_conf1;		/* 0x3616 */
+	u8 ahb_dma_buffstat;		/* 0x3617 */
+	u8 ahb_dma_buffint;		/* 0x3618 */
+	u8 ahb_dma_buffmask;		/* 0x3619 */
+	u8 ahb_dma_buffpol;		/* 0x361a */
+	u8 reserved20[0x9e5];
+	/* Main Controller Registers */
+	u8 mc_sfrdiv;			/* 0x4000 */
+	u8 mc_clkdis;			/* 0x4001 */
+	u8 mc_swrstz;			/* 0x4002 */
+	u8 mc_opctrl;			/* 0x4003 */
+	u8 mc_flowctrl;			/* 0x4004 */
+	u8 mc_phyrstz;			/* 0x4005 */
+	u8 mc_lockonclock;		/* 0x4006 */
+	u8 mc_heacphy_rst;		/* 0x4007 */
+	u8 reserved21[0xf8];
+	/* Colorspace Converter Registers */
+	u8 csc_cfg;			/* 0x4100 */
+	u8 csc_scale;			/* 0x4101 */
+	u8 csc_coef_a1_msb;		/* 0x4102 */
+	u8 csc_coef_a1_lsb;		/* 0x4103 */
+	u8 csc_coef_a2_msb;		/* 0x4104 */
+	u8 csc_coef_a2_lsb;		/* 0x4105 */
+	u8 csc_coef_a3_msb;		/* 0x4106 */
+	u8 csc_coef_a3_lsb;		/* 0x4107 */
+	u8 csc_coef_a4_msb;		/* 0x4108 */
+	u8 csc_coef_a4_lsb;		/* 0x4109 */
+	u8 csc_coef_b1_msb;		/* 0x410a */
+	u8 csc_coef_b1_lsb;		/* 0x410b */
+	u8 csc_coef_b2_msb;		/* 0x410c */
+	u8 csc_coef_b2_lsb;		/* 0x410d */
+	u8 csc_coef_b3_msb;		/* 0x410e */
+	u8 csc_coef_b3_lsb;		/* 0x410f */
+	u8 csc_coef_b4_msb;		/* 0x4110 */
+	u8 csc_coef_b4_lsb;		/* 0x4111 */
+	u8 csc_coef_c1_msb;		/* 0x4112 */
+	u8 csc_coef_c1_lsb;		/* 0x4113 */
+	u8 csc_coef_c2_msb;		/* 0x4114 */
+	u8 csc_coef_c2_lsb;		/* 0x4115 */
+	u8 csc_coef_c3_msb;		/* 0x4116 */
+	u8 csc_coef_c3_lsb;		/* 0x4117 */
+	u8 csc_coef_c4_msb;		/* 0x4118 */
+	u8 csc_coef_c4_lsb;		/* 0x4119 */
+	u8 reserved22[0xee6];
+	/* HDCP Encryption Engine Registers */
+	u8 a_hdcpcfg0;			/* 0x5000 */
+	u8 a_hdcpcfg1;			/* 0x5001 */
+	u8 a_hdcpobs0;			/* 0x5002 */
+	u8 a_hdcpobs1;			/* 0x5003 */
+	u8 a_hdcpobs2;			/* 0x5004 */
+	u8 a_hdcpobs3;			/* 0x5005 */
+	u8 a_apiintclr;			/* 0x5006 */
+	u8 a_apiintstat;		/* 0x5007 */
+	u8 a_apiintmsk;			/* 0x5008 */
+	u8 a_vidpolcfg;			/* 0x5009 */
+	u8 a_oesswcfg;			/* 0x500a */
+	u8 a_timer1setup0;		/* 0x500b */
+	u8 a_timer1setup1;		/* 0x500c */
+	u8 a_timer2setup0;		/* 0x500d */
+	u8 a_timer2setup1;		/* 0x500e */
+	u8 a_100mscfg;			/* 0x500f */
+	u8 a_2scfg0;			/* 0x5010 */
+	u8 a_2scfg1;			/* 0x5011 */
+	u8 a_5scfg0;			/* 0x5012 */
+	u8 a_5scfg1;			/* 0x5013 */
+	u8 a_srmverlsb;			/* 0x5014 */
+	u8 a_srmvermsb;			/* 0x5015 */
+	u8 a_srmctrl;			/* 0x5016 */
+	u8 a_sfrsetup;			/* 0x5017 */
+	u8 a_i2chsetup;			/* 0x5018 */
+	u8 a_intsetup;			/* 0x5019 */
+	u8 a_presetup;			/* 0x501a */
+	u8 reserved23[0x5];
+	u8 a_srm_base;			/* 0x5020 */
+	u8 reserved24[0x2cdf];
+	/* CEC Engine Registers */
+	u8 cec_ctrl;			/* 0x7d00 */
+	u8 cec_stat;			/* 0x7d01 */
+	u8 cec_mask;			/* 0x7d02 */
+	u8 cec_polarity;		/* 0x7d03 */
+	u8 cec_int;			/* 0x7d04 */
+	u8 cec_addr_l;			/* 0x7d05 */
+	u8 cec_addr_h;			/* 0x7d06 */
+	u8 cec_tx_cnt;			/* 0x7d07 */
+	u8 cec_rx_cnt;			/* 0x7d08 */
+	u8 reserved25[0x7];
+	u8 cec_tx_data0;		/* 0x7d10 */
+	u8 cec_tx_data1;		/* 0x7d11 */
+	u8 cec_tx_data2;		/* 0x7d12 */
+	u8 cec_tx_data3;		/* 0x7d13 */
+	u8 cec_tx_data4;		/* 0x7d14 */
+	u8 cec_tx_data5;		/* 0x7d15 */
+	u8 cec_tx_data6;		/* 0x7d16 */
+	u8 cec_tx_data7;		/* 0x7d17 */
+	u8 cec_tx_data8;		/* 0x7d18 */
+	u8 cec_tx_data9;		/* 0x7d19 */
+	u8 cec_tx_data10;		/* 0x7d1a */
+	u8 cec_tx_data11;		/* 0x7d1b */
+	u8 cec_tx_data12;		/* 0x7d1c */
+	u8 cec_tx_data13;		/* 0x7d1d */
+	u8 cec_tx_data14;		/* 0x7d1e */
+	u8 cec_tx_data15;		/* 0x7d1f */
+	u8 cec_rx_data0;		/* 0x7d20 */
+	u8 cec_rx_data1;		/* 0x7d21 */
+	u8 cec_rx_data2;		/* 0x7d22 */
+	u8 cec_rx_data3;		/* 0x7d23 */
+	u8 cec_rx_data4;		/* 0x7d24 */
+	u8 cec_rx_data5;		/* 0x7d25 */
+	u8 cec_rx_data6;		/* 0x7d26 */
+	u8 cec_rx_data7;		/* 0x7d27 */
+	u8 cec_rx_data8;		/* 0x7d28 */
+	u8 cec_rx_data9;		/* 0x7d29 */
+	u8 cec_rx_data10;		/* 0x7d2a */
+	u8 cec_rx_data11;		/* 0x7d2b */
+	u8 cec_rx_data12;		/* 0x7d2c */
+	u8 cec_rx_data13;		/* 0x7d2d */
+	u8 cec_rx_data14;		/* 0x7d2e */
+	u8 cec_rx_data15;		/* 0x7d2f */
+	u8 cec_lock;			/* 0x7d30 */
+	u8 cec_wkupctrl;		/* 0x7d31 */
+	u8 reserved26[0xce];
+	/* I2C Master Registers (E-DDC) */
+	u8 i2cm_slave;			/* 0x7e00 */
+	u8 i2cmess;			/* 0x7e01 */
+	u8 i2cm_datao;			/* 0x7e02 */
+	u8 i2cm_datai;			/* 0x7e03 */
+	u8 i2cm_operation;		/* 0x7e04 */
+	u8 i2cm_int;			/* 0x7e05 */
+	u8 i2cm_ctlint;			/* 0x7e06 */
+	u8 i2cm_div;			/* 0x7e07 */
+	u8 i2cm_segaddr;		/* 0x7e08 */
+	u8 i2cm_softrstz;		/* 0x7e09 */
+	u8 i2cm_segptr;			/* 0x7e0a */
+	u8 i2cm_ss_scl_hcnt_1_addr;	/* 0x7e0b */
+	u8 i2cm_ss_scl_hcnt_0_addr;	/* 0x7e0c */
+	u8 i2cm_ss_scl_lcnt_1_addr;	/* 0x7e0d */
+	u8 i2cm_ss_scl_lcnt_0_addr;	/* 0x7e0e */
+	u8 i2cm_fs_scl_hcnt_1_addr;	/* 0x7e0f */
+	u8 i2cm_fs_scl_hcnt_0_addr;	/* 0x7e10 */
+	u8 i2cm_fs_scl_lcnt_1_addr;	/* 0x7e11 */
+	u8 i2cm_fs_scl_lcnt_0_addr;	/* 0x7e12 */
+	u8 reserved27[0x1ed];
+	/* Random Number Generator Registers (RNG) */
+	u8 rng_base;			/* 0x8000 */
+};
+
+/*
+ * Register field definitions
+ */
+enum {
+/* IH_FC_INT2 field values */
+	HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
+	HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_FC_STAT2 field values */
+	HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
+	HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_PHY_STAT0 field values */
+	HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
+	HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
+	HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
+	HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
+	HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
+	HDMI_IH_PHY_STAT0_HPD = 0x1,
+
+/* IH_MUTE_I2CMPHY_STAT0 field values */
+	HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
+	HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
+
+/* IH_AHBDMAAUD_STAT0 field values */
+	HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
+	HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
+	HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
+	HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
+	HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
+	HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
+
+/* IH_MUTE_FC_STAT2 field values */
+	HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
+	HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_MUTE_AHBDMAAUD_STAT0 field values */
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
+	HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
+
+/* IH_MUTE field values */
+	HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
+	HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
+
+/* TX_INVID0 field values */
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
+	HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
+	HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
+
+/* TX_INSTUFFING field values */
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
+
+/* VP_PR_CD field values */
+	HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
+	HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
+
+/* VP_STUFF field values */
+	HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
+	HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
+	HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
+	HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
+	HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
+	HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
+	HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
+	HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
+	HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
+	HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
+	HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
+	HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
+	HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
+	HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
+	HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
+
+/* VP_CONF field values */
+	HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
+	HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
+	HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
+	HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
+	HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_PR_EN_MASK = 0x10,
+	HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
+	HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
+	HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
+	HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
+	HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
+	HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
+	HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
+
+/* VP_REMAP field values */
+	HDMI_VP_REMAP_MASK = 0x3,
+	HDMI_VP_REMAP_YCC422_24bit = 0x2,
+	HDMI_VP_REMAP_YCC422_20bit = 0x1,
+	HDMI_VP_REMAP_YCC422_16bit = 0x0,
+
+/* FC_INVIDCONF field values */
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
+	HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
+
+/* FC_AUDICONF0 field values */
+	HDMI_FC_AUDICONF0_CC_OFFSET = 4,
+	HDMI_FC_AUDICONF0_CC_MASK = 0x70,
+	HDMI_FC_AUDICONF0_CT_OFFSET = 0,
+	HDMI_FC_AUDICONF0_CT_MASK = 0xF,
+
+/* FC_AUDICONF1 field values */
+	HDMI_FC_AUDICONF1_SS_OFFSET = 3,
+	HDMI_FC_AUDICONF1_SS_MASK = 0x18,
+	HDMI_FC_AUDICONF1_SF_OFFSET = 0,
+	HDMI_FC_AUDICONF1_SF_MASK = 0x7,
+
+/* FC_AUDICONF3 field values */
+	HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
+	HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
+	HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
+	HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
+	HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
+	HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
+
+/* FC_AUDSCHNLS0 field values */
+	HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
+	HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
+
+/* FC_AUDSCHNLS3-6 field values */
+	HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
+
+	HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
+
+/* HDMI_FC_AUDSCHNLS7 field values */
+	HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
+
+/* HDMI_FC_AUDSCHNLS8 field values */
+	HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
+	HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
+	HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
+	HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
+
+/* FC_AUDSCONF field values */
+	HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
+	HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
+	HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
+
+/* FC_STAT2 field values */
+	HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
+	HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_INT2 field values */
+	HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
+	HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_MASK2 field values */
+	HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
+	HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
+	HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_PRCONF field values */
+	HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
+	HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
+	HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
+	HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
+
+/* FC_AVICONF0-FC_AVICONF3 field values */
+	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
+	HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
+	HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
+	HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
+	HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
+	HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
+	HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
+	HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
+
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
+	HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
+	HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
+	HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
+	HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
+
+	HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
+	HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
+	HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
+	HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
+	HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
+	HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
+	HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
+	HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
+	HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
+	HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
+	HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
+	HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
+
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
+	HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
+	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
+	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
+
+/* FC_DBGFORCE field values */
+	HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
+	HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
+
+/* PHY_CONF0 field values */
+	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
+	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
+	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
+	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
+	HDMI_PHY_CONF0_SPARECTRL = 0x20,
+	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
+	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
+	HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
+	HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
+	HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
+	HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
+	HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
+	HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
+
+/* PHY_TST0 field values */
+	HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
+	HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
+	HDMI_PHY_TST0_TSTEN_MASK = 0x10,
+	HDMI_PHY_TST0_TSTEN_OFFSET = 4,
+	HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
+	HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
+
+/* PHY_STAT0 field values */
+	HDMI_PHY_RX_SENSE3 = 0x80,
+	HDMI_PHY_RX_SENSE2 = 0x40,
+	HDMI_PHY_RX_SENSE1 = 0x20,
+	HDMI_PHY_RX_SENSE0 = 0x10,
+	HDMI_PHY_HPD = 0x02,
+	HDMI_PHY_TX_PHY_LOCK = 0x01,
+
+/* Convenience macro RX_SENSE | HPD */
+	HDMI_DVI_STAT = 0xF2,
+
+/* PHY_I2CM_SLAVE_ADDR field values */
+	HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
+	HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
+
+/* PHY_I2CM_OPERATION_ADDR field values */
+	HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
+	HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
+
+/* HDMI_PHY_I2CM_INT_ADDR */
+	HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
+	HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
+
+/* HDMI_PHY_I2CM_CTLINT_ADDR */
+	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
+	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
+	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
+	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
+
+/* AUD_CTS3 field values */
+	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
+	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
+	HDMI_AUD_CTS3_N_SHIFT_1 = 0,
+	HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
+	HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
+	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
+	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
+	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
+	/* note that the CTS3 MANUAL bit has been removed
+	   from our part. Can't set it, will read as 0. */
+	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
+	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
+
+/* AHB_DMA_CONF0 field values */
+	HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
+	HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
+	HDMI_AHB_DMA_CONF0_HBR = 0x10,
+	HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
+	HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
+	HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
+	HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
+	HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
+	HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
+	HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
+	HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
+
+/* HDMI_AHB_DMA_START field values */
+	HDMI_AHB_DMA_START_START_OFFSET = 0,
+	HDMI_AHB_DMA_START_START_MASK = 0x01,
+
+/* HDMI_AHB_DMA_STOP field values */
+	HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
+	HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
+
+/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
+	HDMI_AHB_DMA_DONE = 0x80,
+	HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
+	HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
+	HDMI_AHB_DMA_ERROR = 0x10,
+	HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
+	HDMI_AHB_DMA_FIFO_FULL = 0x02,
+	HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
+
+/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */
+	HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
+	HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
+
+/* MC_CLKDIS field values */
+	HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
+	HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
+	HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
+	HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
+	HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
+	HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
+	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
+
+/* MC_SWRSTZ field values */
+	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
+
+/* MC_FLOWCTRL field values */
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
+
+/* MC_PHYRSTZ field values */
+	HDMI_MC_PHYRSTZ_ASSERT = 0x0,
+	HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
+
+/* MC_HEACPHY_RST field values */
+	HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
+	HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
+
+/* CSC_CFG field values */
+	HDMI_CSC_CFG_INTMODE_MASK = 0x30,
+	HDMI_CSC_CFG_INTMODE_OFFSET = 4,
+	HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
+	HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
+	HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
+	HDMI_CSC_CFG_DECMODE_MASK = 0x3,
+	HDMI_CSC_CFG_DECMODE_OFFSET = 0,
+	HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
+
+/* CSC_SCALE field values */
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
+	HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
+
+/* A_HDCPCFG0 field values */
+	HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
+	HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
+	HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
+	HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
+	HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
+	HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
+	HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
+	HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
+	HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
+	HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
+	HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
+	HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
+	HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
+	HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
+	HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
+	HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
+	HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
+	HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
+	HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
+	HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
+	HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
+
+/* A_HDCPCFG1 field values */
+	HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
+	HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
+	HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
+	HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
+	HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
+	HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
+	HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
+	HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
+	HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
+	HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
+	HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
+
+/* A_VIDPOLCFG field values */
+	HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
+	HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
+	HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
+	HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
+	HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
+	HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
+	HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
+	HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
+	HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
+	HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
+	HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
+};
+
+#endif /* __MXC_HDMI_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/opos6ul.h b/arch/arm/include/asm/arch-mx6/opos6ul.h
new file mode 100644
index 0000000..b55a54c
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/opos6ul.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Armadeus Systems
+ */
+
+#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__
+#define __ARCH_ARM_MX6UL_OPOS6UL_H__
+
+int opos6ul_board_late_init(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
new file mode 100644
index 0000000..4bf7dff
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ */
+
+#ifndef __SYS_PROTO_IMX6_
+#define __SYS_PROTO_IMX6_
+
+#include <asm/mach-imx/sys_proto.h>
+#include <asm/arch/iomux.h>
+
+#define USBPHY_PWD		0x00000000
+
+#define USBPHY_PWD_RXPWDRX	(1 << 20) /* receiver block power down */
+
+#define is_usbotg_phy_active(void) (!(readl(USB_PHY0_BASE_ADDR + USBPHY_PWD) & \
+				   USBPHY_PWD_RXPWDRX))
+
+int imx6_pcie_toggle_power(void);
+int imx6_pcie_toggle_reset(void);
+
+/**
+ * iomuxc_set_rgmii_io_voltage - set voltage level of RGMII/USB pins
+ *
+ * @param io_vol - the voltage IO level of pins
+ */
+static inline void iomuxc_set_rgmii_io_voltage(int io_vol)
+{
+	__raw_writel(io_vol, IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII);
+}
+
+#endif /* __SYS_PROTO_IMX6_ */
diff --git a/arch/arm/include/asm/arch-mx7/clock.h b/arch/arm/include/asm/arch-mx7/clock.h
new file mode 100644
index 0000000..984bd3f
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/clock.h
@@ -0,0 +1,365 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ *	Peng Fan <Peng.Fan@freescale.com>
+ */
+
+#ifndef _ASM_ARCH_CLOCK_H
+#define _ASM_ARCH_CLOCK_H
+
+#include <common.h>
+#include <asm/arch/crm_regs.h>
+
+#ifdef CONFIG_SYS_MX7_HCLK
+#define MXC_HCLK	CONFIG_SYS_MX7_HCLK
+#else
+#define MXC_HCLK	24000000
+#endif
+
+#ifdef CONFIG_SYS_MX7_CLK32
+#define MXC_CLK32	CONFIG_SYS_MX7_CLK32
+#else
+#define MXC_CLK32	32768
+#endif
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_UART_CLK,
+	MXC_CSPI_CLK,
+	MXC_AXI_CLK,
+	MXC_DDR_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_I2C_CLK,
+};
+
+/* PLL supported by i.mx7d */
+enum pll_clocks {
+	PLL_CORE,	/* Core PLL */
+	PLL_SYS,	/* System PLL*/
+	PLL_ENET,	/* Enet PLL */
+	PLL_AUDIO,	/* Audio PLL */
+	PLL_VIDEO,	/* Video PLL*/
+	PLL_DDR,	/* Dram PLL */
+	PLL_USB,	/* USB PLL, fixed at 480MHZ */
+};
+
+/* clk src for clock root gen */
+enum clk_root_src {
+	OSC_24M_CLK,
+
+	PLL_ARM_MAIN_800M_CLK,
+
+	PLL_SYS_MAIN_480M_CLK,
+	PLL_SYS_MAIN_240M_CLK,
+	PLL_SYS_MAIN_120M_CLK,
+	PLL_SYS_PFD0_392M_CLK,
+	PLL_SYS_PFD0_196M_CLK,
+	PLL_SYS_PFD1_332M_CLK,
+	PLL_SYS_PFD1_166M_CLK,
+	PLL_SYS_PFD2_270M_CLK,
+	PLL_SYS_PFD2_135M_CLK,
+	PLL_SYS_PFD3_CLK,
+	PLL_SYS_PFD4_CLK,
+	PLL_SYS_PFD5_CLK,
+	PLL_SYS_PFD6_CLK,
+	PLL_SYS_PFD7_CLK,
+
+	PLL_ENET_MAIN_500M_CLK,
+	PLL_ENET_MAIN_250M_CLK,
+	PLL_ENET_MAIN_125M_CLK,
+	PLL_ENET_MAIN_100M_CLK,
+	PLL_ENET_MAIN_50M_CLK,
+	PLL_ENET_MAIN_40M_CLK,
+	PLL_ENET_MAIN_25M_CLK,
+
+	PLL_DRAM_MAIN_1066M_CLK,
+	PLL_DRAM_MAIN_533M_CLK,
+
+	PLL_AUDIO_MAIN_CLK,
+	PLL_VIDEO_MAIN_CLK,
+
+	PLL_USB_MAIN_480M_CLK,		/* fixed at 480MHZ */
+
+	EXT_CLK_1,
+	EXT_CLK_2,
+	EXT_CLK_3,
+	EXT_CLK_4,
+
+	REF_1M_CLK,
+	OSC_32K_CLK,
+};
+
+/*
+ * Clock root index
+ */
+enum clk_root_index {
+	ARM_A7_CLK_ROOT = 0,
+	ARM_M4_CLK_ROOT = 1,
+	ARM_M0_CLK_ROOT = 2,
+	MAIN_AXI_CLK_ROOT = 16,
+	DISP_AXI_CLK_ROOT = 17,
+	ENET_AXI_CLK_ROOT = 18,
+	NAND_USDHC_BUS_CLK_ROOT = 19,
+	AHB_CLK_ROOT = 32,
+	DRAM_PHYM_CLK_ROOT = 48,
+	DRAM_CLK_ROOT = 49,
+	DRAM_PHYM_ALT_CLK_ROOT = 64,
+	DRAM_ALT_CLK_ROOT = 65,
+	USB_HSIC_CLK_ROOT = 66,
+	PCIE_CTRL_CLK_ROOT = 67,
+	PCIE_PHY_CLK_ROOT = 68,
+	EPDC_PIXEL_CLK_ROOT = 69,
+	LCDIF_PIXEL_CLK_ROOT = 70,
+	MIPI_DSI_EXTSER_CLK_ROOT = 71,
+	MIPI_CSI_WARP_CLK_ROOT = 72,
+	MIPI_DPHY_REF_CLK_ROOT = 73,
+	SAI1_CLK_ROOT = 74,
+	SAI2_CLK_ROOT = 75,
+	SAI3_CLK_ROOT = 76,
+	SPDIF_CLK_ROOT = 77,
+	ENET1_REF_CLK_ROOT = 78,
+	ENET1_TIME_CLK_ROOT = 79,
+	ENET2_REF_CLK_ROOT = 80,
+	ENET2_TIME_CLK_ROOT = 81,
+	ENET_PHY_REF_CLK_ROOT = 82,
+	EIM_CLK_ROOT = 83,
+	NAND_CLK_ROOT = 84,
+	QSPI_CLK_ROOT = 85,
+	USDHC1_CLK_ROOT = 86,
+	USDHC2_CLK_ROOT = 87,
+	USDHC3_CLK_ROOT = 88,
+	CAN1_CLK_ROOT = 89,
+	CAN2_CLK_ROOT = 90,
+	I2C1_CLK_ROOT = 91,
+	I2C2_CLK_ROOT = 92,
+	I2C3_CLK_ROOT = 93,
+	I2C4_CLK_ROOT = 94,
+	UART1_CLK_ROOT = 95,
+	UART2_CLK_ROOT = 96,
+	UART3_CLK_ROOT = 97,
+	UART4_CLK_ROOT = 98,
+	UART5_CLK_ROOT = 99,
+	UART6_CLK_ROOT = 100,
+	UART7_CLK_ROOT = 101,
+	ECSPI1_CLK_ROOT = 102,
+	ECSPI2_CLK_ROOT = 103,
+	ECSPI3_CLK_ROOT = 104,
+	ECSPI4_CLK_ROOT = 105,
+	PWM1_CLK_ROOT = 106,
+	PWM2_CLK_ROOT = 107,
+	PWM3_CLK_ROOT = 108,
+	PWM4_CLK_ROOT = 109,
+	FLEXTIMER1_CLK_ROOT = 110,
+	FLEXTIMER2_CLK_ROOT = 111,
+	SIM1_CLK_ROOT = 112,
+	SIM2_CLK_ROOT = 113,
+	GPT1_CLK_ROOT = 114,
+	GPT2_CLK_ROOT = 115,
+	GPT3_CLK_ROOT = 116,
+	GPT4_CLK_ROOT = 117,
+	TRACE_CLK_ROOT = 118,
+	WDOG_CLK_ROOT = 119,
+	CSI_MCLK_CLK_ROOT = 120,
+	AUDIO_MCLK_CLK_ROOT = 121,
+	WRCLK_CLK_ROOT = 122,
+	IPP_DO_CLKO1 = 123,
+	IPP_DO_CLKO2 = 124,
+
+	CLK_ROOT_MAX,
+};
+
+#if (CONFIG_CONS_INDEX == 0)
+#define UART_CLK_ROOT UART1_CLK_ROOT
+#elif (CONFIG_CONS_INDEX == 1)
+#define UART_CLK_ROOT UART2_CLK_ROOT
+#elif (CONFIG_CONS_INDEX == 2)
+#define UART_CLK_ROOT UART3_CLK_ROOT
+#elif (CONFIG_CONS_INDEX == 3)
+#define UART_CLK_ROOT UART4_CLK_ROOT
+#elif (CONFIG_CONS_INDEX == 4)
+#define UART_CLK_ROOT UART5_CLK_ROOT
+#elif (CONFIG_CONS_INDEX == 5)
+#define UART_CLK_ROOT UART6_CLK_ROOT
+#elif (CONFIG_CONS_INDEX == 6)
+#define UART_CLK_ROOT UART7_CLK_ROOT
+#else
+#error "Invalid IMX UART ID for serial console is defined"
+#endif
+
+struct clk_root_setting {
+	enum clk_root_index root;
+	u32 setting;
+};
+
+/*
+ * CCGR mapping
+ */
+enum clk_ccgr_index {
+	CCGR_CPU = 0,
+	CCGR_M4 = 1,
+	CCGR_SIM_MAIN = 4,
+	CCGR_SIM_DISPLAY = 5,
+	CCGR_SIM_ENET = 6,
+	CCGR_SIM_M = 7,
+	CCGR_SIM_S = 8,
+	CCGR_SIM_WAKEUP = 9,
+	CCGR_IPMUX1 = 10,
+	CCGR_IPMUX2 = 11,
+	CCGR_IPMUX3 = 12,
+	CCGR_ROM = 16,
+	CCGR_OCRAM = 17,
+	CCGR_OCRAM_S = 18,
+	CCGR_DRAM = 19,
+	CCGR_RAWNAND = 20,
+	CCGR_QSPI = 21,
+	CCGR_WEIM = 22,
+	CCGR_ADC = 32,
+	CCGR_ANATOP = 33,
+	CCGR_SCTR = 34,
+	CCGR_OCOTP = 35,
+	CCGR_CAAM = 36,
+	CCGR_SNVS = 37,
+	CCGR_RDC = 38,
+	CCGR_MU = 39,
+	CCGR_HS = 40,
+	CCGR_DVFS = 41,
+	CCGR_QOS = 42,
+	CCGR_QOS_DISPMIX = 43,
+	CCGR_QOS_MEGAMIX = 44,
+	CCGR_CSU = 45,
+	CCGR_DBGMON = 46,
+	CCGR_DEBUG = 47,
+	CCGR_TRACE = 48,
+	CCGR_SEC_DEBUG = 49,
+	CCGR_SEMA1 = 64,
+	CCGR_SEMA2 = 65,
+	CCGR_PERFMON1 = 68,
+	CCGR_PERFMON2 = 69,
+	CCGR_SDMA = 72,
+	CCGR_CSI = 73,
+	CCGR_EPDC = 74,
+	CCGR_LCDIF = 75,
+	CCGR_PXP = 76,
+	CCGR_PCIE = 96,
+	CCGR_MIPI_CSI = 100,
+	CCGR_MIPI_DSI = 101,
+	CCGR_MIPI_MEM_PHY = 102,
+	CCGR_USB_CTRL = 104,
+	CCGR_USB_HSIC = 105,
+	CCGR_USB_PHY1 = 106,
+	CCGR_USB_PHY2 = 107,
+	CCGR_USDHC1 = 108,
+	CCGR_USDHC2 = 109,
+	CCGR_USDHC3 = 110,
+	CCGR_ENET1 = 112,
+	CCGR_ENET2 = 113,
+	CCGR_CAN1 = 116,
+	CCGR_CAN2 = 117,
+	CCGR_ECSPI1 = 120,
+	CCGR_ECSPI2 = 121,
+	CCGR_ECSPI3 = 122,
+	CCGR_ECSPI4 = 123,
+	CCGR_GPT1 = 124,
+	CCGR_GPT2 = 125,
+	CCGR_GPT3 = 126,
+	CCGR_GPT4 = 127,
+	CCGR_FTM1 = 128,
+	CCGR_FTM2 = 129,
+	CCGR_PWM1 = 132,
+	CCGR_PWM2 = 133,
+	CCGR_PWM3 = 134,
+	CCGR_PWM4 = 135,
+	CCGR_I2C1 = 136,
+	CCGR_I2C2 = 137,
+	CCGR_I2C3 = 138,
+	CCGR_I2C4 = 139,
+	CCGR_SAI1 = 140,
+	CCGR_SAI2 = 141,
+	CCGR_SAI3 = 142,
+	CCGR_SIM1 = 144,
+	CCGR_SIM2 = 145,
+	CCGR_UART1 = 148,
+	CCGR_UART2 = 149,
+	CCGR_UART3 = 150,
+	CCGR_UART4 = 151,
+	CCGR_UART5 = 152,
+	CCGR_UART6 = 153,
+	CCGR_UART7 = 154,
+	CCGR_WDOG1 = 156,
+	CCGR_WDOG2 = 157,
+	CCGR_WDOG3 = 158,
+	CCGR_WDOG4 = 159,
+	CCGR_GPIO1 = 160,
+	CCGR_GPIO2 = 161,
+	CCGR_GPIO3 = 162,
+	CCGR_GPIO4 = 163,
+	CCGR_GPIO5 = 164,
+	CCGR_GPIO6 = 165,
+	CCGR_GPIO7 = 166,
+	CCGR_IOMUX = 168,
+	CCGR_IOMUX_LPSR = 169,
+	CCGR_KPP = 170,
+
+	CCGR_SKIP,
+	CCGR_MAX,
+};
+
+/* Clock root channel */
+enum clk_root_type {
+	CCM_CORE_CHANNEL,
+	CCM_BUS_CHANNEL,
+	CCM_AHB_CHANNEL,
+	CCM_DRAM_PHYM_CHANNEL,
+	CCM_DRAM_CHANNEL,
+	CCM_IP_CHANNEL,
+};
+
+#include <asm/arch/clock_slice.h>
+
+/*
+ * entry: the clock root index
+ * type: ccm channel
+ * src_mux: each entry corresponding to the clock src, detailed info in CCM RM
+ */
+struct clk_root_map {
+	enum clk_root_index entry;
+	enum clk_root_type type;
+	uint8_t src_mux[8];
+};
+
+enum enet_freq {
+	ENET_25MHZ,
+	ENET_50MHZ,
+	ENET_125MHZ,
+};
+
+u32 get_root_clk(enum clk_root_index clock_id);
+u32 mxc_get_clock(enum mxc_clock clk);
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+void clock_init(void);
+#ifdef CONFIG_SYS_I2C_MXC
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+#endif
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type);
+#endif
+int set_clk_qspi(void);
+int set_clk_nand(void);
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable);
+#endif
+void enable_usboh3_clk(unsigned char enable);
+#ifdef CONFIG_IMX_HAB
+void hab_caam_clock_enable(unsigned char enable);
+#endif
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
+void enable_thermal_clk(void);
+#endif
diff --git a/arch/arm/include/asm/arch-mx7/clock_slice.h b/arch/arm/include/asm/arch-mx7/clock_slice.h
new file mode 100644
index 0000000..9a7c1f8
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/clock_slice.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ *	Peng Fan <Peng.Fan@freescale.com>
+ */
+
+#ifndef _ASM_ARCH_CLOCK_SLICE_H
+#define _ASM_ARCH_CLOCK_SLICE_H
+
+enum root_pre_div {
+	CLK_ROOT_PRE_DIV1 = 0,
+	CLK_ROOT_PRE_DIV2,
+	CLK_ROOT_PRE_DIV3,
+	CLK_ROOT_PRE_DIV4,
+	CLK_ROOT_PRE_DIV5,
+	CLK_ROOT_PRE_DIV6,
+	CLK_ROOT_PRE_DIV7,
+	CLK_ROOT_PRE_DIV8,
+};
+
+enum root_post_div {
+	CLK_ROOT_POST_DIV1 = 0,
+	CLK_ROOT_POST_DIV2,
+	CLK_ROOT_POST_DIV3,
+	CLK_ROOT_POST_DIV4,
+	CLK_ROOT_POST_DIV5,
+	CLK_ROOT_POST_DIV6,
+	CLK_ROOT_POST_DIV7,
+	CLK_ROOT_POST_DIV8,
+	CLK_ROOT_POST_DIV9,
+	CLK_ROOT_POST_DIV10,
+	CLK_ROOT_POST_DIV11,
+	CLK_ROOT_POST_DIV12,
+	CLK_ROOT_POST_DIV13,
+	CLK_ROOT_POST_DIV14,
+	CLK_ROOT_POST_DIV15,
+	CLK_ROOT_POST_DIV16,
+	CLK_ROOT_POST_DIV17,
+	CLK_ROOT_POST_DIV18,
+	CLK_ROOT_POST_DIV19,
+	CLK_ROOT_POST_DIV20,
+	CLK_ROOT_POST_DIV21,
+	CLK_ROOT_POST_DIV22,
+	CLK_ROOT_POST_DIV23,
+	CLK_ROOT_POST_DIV24,
+	CLK_ROOT_POST_DIV25,
+	CLK_ROOT_POST_DIV26,
+	CLK_ROOT_POST_DIV27,
+	CLK_ROOT_POST_DIV28,
+	CLK_ROOT_POST_DIV29,
+	CLK_ROOT_POST_DIV30,
+	CLK_ROOT_POST_DIV31,
+	CLK_ROOT_POST_DIV32,
+	CLK_ROOT_POST_DIV33,
+	CLK_ROOT_POST_DIV34,
+	CLK_ROOT_POST_DIV35,
+	CLK_ROOT_POST_DIV36,
+	CLK_ROOT_POST_DIV37,
+	CLK_ROOT_POST_DIV38,
+	CLK_ROOT_POST_DIV39,
+	CLK_ROOT_POST_DIV40,
+	CLK_ROOT_POST_DIV41,
+	CLK_ROOT_POST_DIV42,
+	CLK_ROOT_POST_DIV43,
+	CLK_ROOT_POST_DIV44,
+	CLK_ROOT_POST_DIV45,
+	CLK_ROOT_POST_DIV46,
+	CLK_ROOT_POST_DIV47,
+	CLK_ROOT_POST_DIV48,
+	CLK_ROOT_POST_DIV49,
+	CLK_ROOT_POST_DIV50,
+	CLK_ROOT_POST_DIV51,
+	CLK_ROOT_POST_DIV52,
+	CLK_ROOT_POST_DIV53,
+	CLK_ROOT_POST_DIV54,
+	CLK_ROOT_POST_DIV55,
+	CLK_ROOT_POST_DIV56,
+	CLK_ROOT_POST_DIV57,
+	CLK_ROOT_POST_DIV58,
+	CLK_ROOT_POST_DIV59,
+	CLK_ROOT_POST_DIV60,
+	CLK_ROOT_POST_DIV61,
+	CLK_ROOT_POST_DIV62,
+	CLK_ROOT_POST_DIV63,
+	CLK_ROOT_POST_DIV64,
+};
+
+enum root_auto_div {
+	CLK_ROOT_AUTO_DIV1 = 0,
+	CLK_ROOT_AUTO_DIV2,
+	CLK_ROOT_AUTO_DIV4,
+	CLK_ROOT_AUTO_DIV8,
+	CLK_ROOT_AUTO_DIV16,
+};
+
+int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src);
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
+int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div);
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
+int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div);
+int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div);
+int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
+			  int auto_en);
+int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
+			  int *auto_en);
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
+int clock_set_target_val(enum clk_root_index clock_id, u32 val);
+int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
+		   enum root_post_div post_div, enum clk_root_src clock_src);
+int clock_root_enabled(enum clk_root_index clock_id);
+
+int clock_enable(enum clk_ccgr_index index, bool enable);
+#endif
diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h
new file mode 100644
index 0000000..f3515fa
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/crm_regs.h
@@ -0,0 +1,2817 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ *	Peng Fan <Peng.Fan@freescale.com>
+ */
+
+#ifndef __ARCH_ARM_MACH_MX7_CCM_REGS_H__
+#define __ARCH_ARM_MACH_MX7_CCM_REGS_H__
+
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+
+#define	CCM_GPR0_OFFSET			0x0
+#define	CCM_OBSERVE0_OFFSET		0x0400
+#define	CCM_SCTRL0_OFFSET		0x0800
+#define	CCM_CCGR0_OFFSET		0x4000
+#define	CCM_ROOT0_TARGET_OFFSET		0x8000
+
+#ifndef __ASSEMBLY__
+
+struct mxc_ccm_ccgr {
+	uint32_t ccgr;
+	uint32_t ccgr_set;
+	uint32_t ccgr_clr;
+	uint32_t ccgr_tog;
+};
+
+struct mxc_ccm_root_slice {
+	uint32_t target_root;
+	uint32_t target_root_set;
+	uint32_t target_root_clr;
+	uint32_t target_root_tog;
+	uint32_t reserved_0[4];
+	uint32_t post;
+	uint32_t post_root_set;
+	uint32_t post_root_clr;
+	uint32_t post_root_tog;
+	uint32_t pre;
+	uint32_t pre_root_set;
+	uint32_t pre_root_clr;
+	uint32_t pre_root_tog;
+	uint32_t reserved_1[12];
+	uint32_t access_ctrl;
+	uint32_t access_ctrl_root_set;
+	uint32_t access_ctrl_root_clr;
+	uint32_t access_ctrl_root_tog;
+};
+
+/** CCM - Peripheral register structure */
+struct mxc_ccm_reg {
+	uint32_t gpr0;
+	uint32_t gpr0_set;
+	uint32_t gpr0_clr;
+	uint32_t gpr0_tog;
+	uint32_t reserved_0[4092];
+	struct mxc_ccm_ccgr ccgr_array[191];	/* offset 0x4000 */
+	uint32_t reserved_1[3332];
+	struct mxc_ccm_root_slice root[121];	/* offset 0x8000 */
+
+};
+
+struct mxc_ccm_anatop_reg {
+	uint32_t ctrl_24m;			/* offset 0x0000 */
+	uint32_t ctrl_24m_set;
+	uint32_t ctrl_24m_clr;
+	uint32_t ctrl_24m_tog;
+	uint32_t rcosc_config0;			/* offset 0x0010 */
+	uint32_t rcosc_config0_set;
+	uint32_t rcosc_config0_clr;
+	uint32_t rcosc_config0_tog;
+	uint32_t rcosc_config1;			/* offset 0x0020 */
+	uint32_t rcosc_config1_set;
+	uint32_t rcosc_config1_clr;
+	uint32_t rcosc_config1_tog;
+	uint32_t rcosc_config2;			/* offset 0x0030 */
+	uint32_t rcosc_config2_set;
+	uint32_t rcosc_config2_clr;
+	uint32_t rcosc_config2_tog;
+	uint8_t reserved_0[16];
+	uint32_t osc_32k;			/* offset 0x0050 */
+	uint32_t osc_32k_set;
+	uint32_t osc_32k_clr;
+	uint32_t osc_32k_tog;
+	uint32_t pll_arm;			/* offset 0x0060 */
+	uint32_t pll_arm_set;
+	uint32_t pll_arm_clr;
+	uint32_t pll_arm_tog;
+	uint32_t pll_ddr;			/* offset 0x0070 */
+	uint32_t pll_ddr_set;
+	uint32_t pll_ddr_clr;
+	uint32_t pll_ddr_tog;
+	uint32_t pll_ddr_ss;			/* offset 0x0080 */
+	uint8_t reserved_1[12];
+	uint32_t pll_ddr_num;			/* offset 0x0090 */
+	uint8_t reserved_2[12];
+	uint32_t pll_ddr_denom;			/* offset 0x00a0 */
+	uint8_t reserved_3[12];
+	uint32_t pll_480;			/* offset 0x00b0 */
+	uint32_t pll_480_set;
+	uint32_t pll_480_clr;
+	uint32_t pll_480_tog;
+	uint32_t pfd_480a;			/* offset 0x00c0 */
+	uint32_t pfd_480a_set;
+	uint32_t pfd_480a_clr;
+	uint32_t pfd_480a_tog;
+	uint32_t pfd_480b;			/* offset 0x00d0 */
+	uint32_t pfd_480b_set;
+	uint32_t pfd_480b_clr;
+	uint32_t pfd_480b_tog;
+	uint32_t pll_enet;			/* offset 0x00e0 */
+	uint32_t pll_enet_set;
+	uint32_t pll_enet_clr;
+	uint32_t pll_enet_tog;
+	uint32_t pll_audio;			/* offset 0x00f0 */
+	uint32_t pll_audio_set;
+	uint32_t pll_audio_clr;
+	uint32_t pll_audio_tog;
+	uint32_t pll_audio_ss;			/* offset 0x0100 */
+	uint8_t reserved_4[12];
+	uint32_t pll_audio_num;			/* offset 0x0110 */
+	uint8_t reserved_5[12];
+	uint32_t pll_audio_denom;		/* offset 0x0120 */
+	uint8_t reserved_6[12];
+	uint32_t pll_video;			/* offset 0x0130 */
+	uint32_t pll_video_set;
+	uint32_t pll_video_clr;
+	uint32_t pll_video_tog;
+	uint32_t pll_video_ss;			/* offset 0x0140 */
+	uint8_t reserved_7[12];
+	uint32_t pll_video_num;			/* offset 0x0150 */
+	uint8_t reserved_8[12];
+	uint32_t pll_video_denom;		/* offset 0x0160 */
+	uint8_t reserved_9[12];
+	uint32_t clk_misc0;			/* offset 0x0170 */
+	uint32_t clk_misc0_set;
+	uint32_t clk_misc0_clr;
+	uint32_t clk_misc0_tog;
+	uint32_t clk_rsvd;			/* offset 0x0180 */
+	uint8_t reserved_10[124];
+	uint32_t reg_1p0a;			/* offset 0x0200 */
+	uint32_t reg_1p0a_set;
+	uint32_t reg_1p0a_clr;
+	uint32_t reg_1p0a_tog;
+	uint32_t reg_1p0d;			/* offsest 0x0210 */
+	uint32_t reg_1p0d_set;
+	uint32_t reg_1p0d_clr;
+	uint32_t reg_1p0d_tog;
+	uint32_t reg_hsic_1p2;			/* offset 0x0220 */
+	uint32_t reg_hsic_1p2_set;
+	uint32_t reg_hsic_1p2_clr;
+	uint32_t reg_hsic_1p2_tog;
+	uint32_t reg_lpsr_1p0;			/* offset 0x0230 */
+	uint32_t reg_lpsr_1p0_set;
+	uint32_t reg_lpsr_1p0_clr;
+	uint32_t reg_lpsr_1p0_tog;
+	uint32_t reg_3p0;			/* offset 0x0240 */
+	uint32_t reg_3p0_set;
+	uint32_t reg_3p0_clr;
+	uint32_t reg_3p0_tog;
+	uint32_t reg_snvs;			/* offset 0x0250 */
+	uint32_t reg_snvs_set;
+	uint32_t reg_snvs_clr;
+	uint32_t reg_snvs_tog;
+	uint32_t analog_debug_misc0;		/* offset 0x0260 */
+	uint32_t analog_debug_misc0_set;
+	uint32_t analog_debug_misc0_clr;
+	uint32_t analog_debug_misc0_tog;
+	uint32_t ref;				/* offset 0x0270 */
+	uint32_t ref_set;
+	uint32_t ref_clr;
+	uint32_t ref_tog;
+	uint8_t reserved_11[128];
+	uint32_t tempsense0;			/* offset 0x0300 */
+	uint32_t tempsense0_set;
+	uint32_t tempsense0_clr;
+	uint32_t tempsense0_tog;
+	uint32_t tempsense1;			/* offset 0x0310 */
+	uint32_t tempsense1_set;
+	uint32_t tempsense1_clr;
+	uint32_t tempsense1_tog;
+	uint32_t tempsense_trim;		/* offset 0x0320 */
+	uint32_t tempsense_trim_set;
+	uint32_t tempsense_trim_clr;
+	uint32_t tempsense_trim_tog;
+	uint32_t lowpwr_ctrl;			/* offset 0x0330 */
+	uint32_t lowpwr_ctrl_set;
+	uint32_t lowpwr_ctrl_clr;
+	uint32_t lowpwr_ctrl_tog;
+	uint32_t snvs_tamper_offset_ctrl;	/* offset 0x0340 */
+	uint32_t snvs_tamper_offset_ctrl_set;
+	uint32_t snvs_tamper_offset_ctrl_clr;
+	uint32_t snvs_tamper_offset_ctrl_tog;
+	uint32_t snvs_tamper_pull_ctrl;		/* offset 0x0350 */
+	uint32_t snvs_tamper_pull_ctrl_set;
+	uint32_t snvs_tamper_pull_ctrl_clr;
+	uint32_t snvs_tamper_pull_ctrl_tog;
+	uint32_t snvs_test;			/* offset 0x0360 */
+	uint32_t snvs_test_set;
+	uint32_t snvs_test_clr;
+	uint32_t snvs_test_tog;
+	uint32_t snvs_tamper_trim_ctrl;		/* offset 0x0370 */
+	uint32_t snvs_tamper_trim_ctrl_set;
+	uint32_t snvs_tamper_trim_ctrl_ctrl;
+	uint32_t snvs_tamper_trim_ctrl_tog;
+	uint32_t snvs_misc_ctrl;		/* offset 0x0380 */
+	uint32_t snvs_misc_ctrl_set;
+	uint32_t snvs_misc_ctrl_clr;
+	uint32_t snvs_misc_ctrl_tog;
+	uint8_t reserved_12[112];
+	uint32_t misc;				/* offset 0x0400 */
+	uint8_t reserved_13[252];
+	uint32_t adc0;				/* offset 0x0500 */
+	uint8_t reserved_14[12];
+	uint32_t adc1;				/* offset 0x0510 */
+	uint8_t reserved_15[748];
+	uint32_t digprog;			/* offset 0x0800 */
+};
+#endif
+
+#define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK	(0x01 << 17)
+
+#define ANADIG_PLL_LOCK					0x80000000
+
+#define ANADIG_PLL_ARM_PWDN_MASK			(0x01 << 12)
+#define ANADIG_PLL_480_PWDN_MASK			(0x01 << 12)
+#define ANADIG_PLL_DDR_PWDN_MASK			(0x01 << 20)
+#define ANADIG_PLL_ENET_PWDN_MASK			(0x01 << 5)
+#define ANADIG_PLL_VIDEO_PWDN_MASK			(0x01 << 12)
+
+
+#define ANATOP_PFD480B_PFD4_FRAC_MASK			0x0000003f
+#define ANATOP_PFD480B_PFD4_FRAC_320M_VAL		0x0000001B
+#define ANATOP_PFD480B_PFD4_FRAC_392M_VAL		0x00000016
+#define ANATOP_PFD480B_PFD4_FRAC_432M_VAL		0x00000014
+
+/* PLL_ARM Bit Fields */
+#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK		0x7F
+#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT		0
+#define CCM_ANALOG_PLL_ARM_HALF_LF_MASK			0x80
+#define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT		7
+#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK		0x100
+#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT		8
+#define CCM_ANALOG_PLL_ARM_HALF_CP_MASK			0x200
+#define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT		9
+#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK		0x400
+#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT		10
+#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK		0x800
+#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT		11
+#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK		0x1000
+#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT		12
+#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK		0x2000
+#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT		13
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK		0xC000
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT		14
+#define CCM_ANALOG_PLL_ARM_BYPASS_MASK			0x10000
+#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT			16
+#define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK		0x20000
+#define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT		17
+#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK		0x40000
+#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT		18
+#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK			0x80000
+#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT		19
+#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK	0x100000
+#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT	20
+#define CCM_ANALOG_PLL_ARM_RSVD0_MASK			0x7FE00000
+#define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT			21
+#define CCM_ANALOG_PLL_ARM_LOCK_MASK			0x80000000
+#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT			31
+
+/* PLL_DDR Bit Fields */
+#define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK		0x7F
+#define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT		0
+#define CCM_ANALOG_PLL_DDR_HALF_LF_MASK			0x80
+#define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT		7
+#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK		0x100
+#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT		8
+#define CCM_ANALOG_PLL_DDR_HALF_CP_MASK			0x200
+#define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT		9
+#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK		0x400
+#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT		10
+#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK		0x800
+#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT		11
+#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK		0x1000
+#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT	12
+#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK		0x2000
+#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT		13
+#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK		0xC000
+#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT		14
+#define CCM_ANALOG_PLL_DDR_BYPASS_MASK			0x10000
+#define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT			16
+#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK		0x20000
+#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT		17
+#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK		0x40000
+#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT		18
+#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK	0x80000
+#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT	19
+#define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK		0x100000
+#define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT		20
+#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK		0x600000
+#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT	21
+#define CCM_ANALOG_PLL_DDR_RSVD1_MASK			0x7F800000
+#define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT			23
+#define CCM_ANALOG_PLL_DDR_LOCK_MASK			0x80000000
+#define CCM_ANALOG_PLL_DDR_LOCK_SHIFT			31
+
+/* PLL_480 Bit Fields */
+#define CCM_ANALOG_PLL_480_DIV_SELECT_MASK		0x1
+#define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT		0
+#define CCM_ANALOG_PLL_480_RSVD0_MASK			0xE
+#define CCM_ANALOG_PLL_480_RSVD0_SHIFT			1
+#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK	0x10
+#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT	4
+#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK	0x20
+#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT	5
+#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK	0x40
+#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT	6
+#define CCM_ANALOG_PLL_480_HALF_LF_MASK			0x80
+#define CCM_ANALOG_PLL_480_HALF_LF_SHIFT		7
+#define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK		0x100
+#define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT		8
+#define CCM_ANALOG_PLL_480_HALF_CP_MASK			0x200
+#define CCM_ANALOG_PLL_480_HALF_CP_SHIFT		9
+#define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK		0x400
+#define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT		10
+#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK		0x800
+#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT		11
+#define CCM_ANALOG_PLL_480_POWERDOWN_MASK		0x1000
+#define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT		12
+#define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK		0x2000
+#define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT		13
+#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK		0xC000
+#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT		14
+#define CCM_ANALOG_PLL_480_BYPASS_MASK			0x10000
+#define CCM_ANALOG_PLL_480_BYPASS_SHIFT			16
+#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK	0x20000
+#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT	17
+#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK		0x40000
+#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT		18
+#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK		0x80000
+#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT		19
+#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK		0x100000
+#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT		20
+#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK		0x200000
+#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT		21
+#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK		0x400000
+#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT		22
+#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK		0x800000
+#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT		23
+#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK		0x1000000
+#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT		24
+#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK		0x2000000
+#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT		25
+#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK	0x4000000
+#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT	26
+#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK	0x8000000
+#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT	27
+#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK	0x10000000
+#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT	28
+#define CCM_ANALOG_PLL_480_RSVD1_MASK			0x60000000
+#define CCM_ANALOG_PLL_480_RSVD1_SHIFT			29
+#define CCM_ANALOG_PLL_480_LOCK_MASK			0x80000000
+#define CCM_ANALOG_PLL_480_LOCK_SHIFT			31
+
+/* PFD_480A Bit Fields */
+#define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK		0x3F
+#define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT		0
+#define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK		0x40
+#define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT		6
+#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK	0x80
+#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT	7
+#define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK		0x3F00
+#define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT		8
+#define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK		0x4000
+#define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT		14
+#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK	0x8000
+#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT	15
+#define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK		0x3F0000
+#define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT		16
+#define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK		0x400000
+#define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT		22
+#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK	0x800000
+#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT	23
+#define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK		0x3F000000
+#define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT		24
+#define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK		0x40000000
+#define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT		30
+#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK	0x80000000
+#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT	31
+/* PFD_480B Bit Fields */
+#define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK		0x3F
+#define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT		0
+#define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK		0x40
+#define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT		6
+#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK	0x80
+#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT	7
+#define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK		0x3F00
+#define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT		8
+#define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK		0x4000
+#define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT		14
+#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK	0x8000
+#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT	15
+#define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK		0x3F0000
+#define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT		16
+#define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK		0x400000
+#define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT		22
+#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK	0x800000
+#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT	23
+#define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK		0x3F000000
+#define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT		24
+#define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK		0x40000000
+#define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT		30
+#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK	0x80000000
+#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT	31
+
+/* PLL_ENET Bit Fields */
+#define CCM_ANALOG_PLL_ENET_HALF_LF_MASK		0x1
+#define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT		0
+#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK		0x2
+#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT		1
+#define CCM_ANALOG_PLL_ENET_HALF_CP_MASK		0x4
+#define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT		2
+#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK		0x8
+#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT		3
+#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK		0x10
+#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT		4
+#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK		0x20
+#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT		5
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK	0x40
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT	6
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK	0x80
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT	7
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK	0x100
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT	8
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK	0x200
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT	9
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK	0x400
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT	10
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK	0x800
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT	11
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK	0x1000
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT	12
+#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK	0x2000
+#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT	13
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK		0xC000
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT	14
+#define CCM_ANALOG_PLL_ENET_BYPASS_MASK			0x10000
+#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT		16
+#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK		0x20000
+#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT		17
+#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK		0x40000
+#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT		18
+#define CCM_ANALOG_PLL_ENET_RSVD1_MASK			0x7FF80000
+#define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT			19
+#define CCM_ANALOG_PLL_ENET_LOCK_MASK			0x80000000
+#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT			31
+
+/* PLL_AUDIO Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK     0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT    0
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK        0x80u
+#define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT       7
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK      0x100u
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT     8
+#define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK        0x200u
+#define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT       9
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK      0x400u
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT     10
+#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK  0x800u
+#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK      0x1000u
+#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT     12
+#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK     0x2000u
+#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT    13
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK         0x10000u
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT        16
+#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK  0x20000u
+#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK  0x40000u
+#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK          0x200000u
+#define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT         21
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK   0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT  22
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK          0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT         25
+#define CCM_ANALOG_PLL_AUDIO_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK           0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT          31
+/* PLL_AUDIO_SET Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK    0x80u
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT   7
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK  0x100u
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK    0x200u
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT   9
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK  0x400u
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK  0x1000u
+#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK     0x10000u
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT    16
+#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK      0x200000u
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT     21
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK      0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT     25
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK       0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT      31
+/* PLL_AUDIO_CLR Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK    0x80u
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT   7
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK  0x100u
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK    0x200u
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT   9
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK  0x400u
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK  0x1000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK     0x10000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT    16
+#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK      0x200000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT     21
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK      0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT     25
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK       0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT      31
+/* PLL_AUDIO_TOG Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK    0x80u
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT   7
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK  0x100u
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK    0x200u
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT   9
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK  0x400u
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK  0x1000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK     0x10000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT    16
+#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK      0x200000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT     21
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK      0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT     25
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK       0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT      31
+/* PLL_AUDIO_SS Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK        0x7FFFu
+#define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT       0
+#define CCM_ANALOG_PLL_AUDIO_SS_STEP(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK      0x8000u
+#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT     15
+#define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK        0xFFFF0000u
+#define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT       16
+#define CCM_ANALOG_PLL_AUDIO_SS_STOP(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK)
+/* PLL_AUDIO_NUM Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK          0x3FFFFFFFu
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT         0
+#define CCM_ANALOG_PLL_AUDIO_NUM_A(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
+#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK      0xC0000000u
+#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT     30
+#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK)
+/* PLL_AUDIO_DENOM Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK        0x3FFFFFFFu
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT       0
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
+#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK    0xC0000000u
+#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT   30
+#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK)
+/* PLL_VIDEO Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK     0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT    0
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x)       (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK        0x80u
+#define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT       7
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK      0x100u
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT     8
+#define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK        0x200u
+#define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT       9
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK      0x400u
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT     10
+#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK  0x800u
+#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK      0x1000u
+#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT     12
+#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK     0x2000u
+#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT    13
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK         0x10000u
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT        16
+#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK  0x20000u
+#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK  0x40000u
+#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT(x)  (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK          0x200000u
+#define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT         21
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK   0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT  22
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL(x)     (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK          0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT         25
+#define CCM_ANALOG_PLL_VIDEO_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK           0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT          31
+/* PLL_VIDEO_SET Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK    0x80u
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT   7
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK  0x100u
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK    0x200u
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT   9
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK  0x400u
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK  0x1000u
+#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK     0x10000u
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT    16
+#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK      0x200000u
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT     21
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK      0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT     25
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK       0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT      31
+/* PLL_VIDEO_CLR Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK    0x80u
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT   7
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK  0x100u
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK    0x200u
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT   9
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK  0x400u
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK  0x1000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK     0x10000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT    16
+#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK      0x200000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT     21
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK      0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT     25
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK       0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT      31
+/* PLL_VIDEO_TOG Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x)   (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK    0x80u
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT   7
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK  0x100u
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK    0x200u
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT   9
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK  0x400u
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK  0x1000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK     0x10000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT    16
+#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK      0x200000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT     21
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK      0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT     25
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK       0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT      31
+/* PLL_VIDEO_SS Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK        0x7FFFu
+#define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT       0
+#define CCM_ANALOG_PLL_VIDEO_SS_STEP(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK      0x8000u
+#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT     15
+#define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK        0xFFFF0000u
+#define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT       16
+#define CCM_ANALOG_PLL_VIDEO_SS_STOP(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK)
+/* PLL_VIDEO_NUM Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK          0x3FFFFFFFu
+#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT         0
+#define CCM_ANALOG_PLL_VIDEO_NUM_A(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
+#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK      0xC0000000u
+#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT     30
+#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK)
+/* PLL_VIDEO_DENOM Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK        0x3FFFFFFFu
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT       0
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x)          (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
+#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK    0xC0000000u
+#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT   30
+#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0(x)      (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK)
+/* CLK_MISC0 Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK  0x1Fu
+#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL(x)    (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK  0x20u
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK  0x40u
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK   0x80u
+#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT  7
+#define CCM_ANALOG_CLK_MISC0_RSVD0_MASK          0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT         8
+#define CCM_ANALOG_CLK_MISC0_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_RSVD0_MASK)
+/* CLK_MISC0_SET Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu
+#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u
+#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7
+#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK      0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT     8
+#define CCM_ANALOG_CLK_MISC0_SET_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK)
+/* CLK_MISC0_CLR Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u
+#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7
+#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK      0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT     8
+#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK)
+/* CLK_MISC0_TOG Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u
+#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7
+#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK      0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT     8
+#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0(x)        (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK)
+
+/* REG_1P0A Bit Fields */
+#define PMU_REG_1P0A_ENABLE_LINREG_MASK          0x1u
+#define PMU_REG_1P0A_ENABLE_LINREG_SHIFT         0
+#define PMU_REG_1P0A_ENABLE_BO_MASK              0x2u
+#define PMU_REG_1P0A_ENABLE_BO_SHIFT             1
+#define PMU_REG_1P0A_ENABLE_ILIMIT_MASK          0x4u
+#define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT         2
+#define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK        0x8u
+#define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT       3
+#define PMU_REG_1P0A_BO_OFFSET_MASK              0x70u
+#define PMU_REG_1P0A_BO_OFFSET_SHIFT             4
+#define PMU_REG_1P0A_BO_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_BO_OFFSET_SHIFT))&PMU_REG_1P0A_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK       0x80u
+#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT      7
+#define PMU_REG_1P0A_OUTPUT_TRG_MASK             0x1F00u
+#define PMU_REG_1P0A_OUTPUT_TRG_SHIFT            8
+#define PMU_REG_1P0A_OUTPUT_TRG(x)               (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_RSVD0_MASK                  0xE000u
+#define PMU_REG_1P0A_RSVD0_SHIFT                 13
+#define PMU_REG_1P0A_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD0_SHIFT))&PMU_REG_1P0A_RSVD0_MASK)
+#define PMU_REG_1P0A_BO_MASK                     0x10000u
+#define PMU_REG_1P0A_BO_SHIFT                    16
+#define PMU_REG_1P0A_OK_MASK                     0x20000u
+#define PMU_REG_1P0A_OK_SHIFT                    17
+#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK     0x40000u
+#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT    18
+#define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK     0x80000u
+#define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT    19
+#define PMU_REG_1P0A_REG_TEST_MASK               0xF00000u
+#define PMU_REG_1P0A_REG_TEST_SHIFT              20
+#define PMU_REG_1P0A_REG_TEST(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_REG_TEST_SHIFT))&PMU_REG_1P0A_REG_TEST_MASK)
+#define PMU_REG_1P0A_RSVD1_MASK                  0xFF000000u
+#define PMU_REG_1P0A_RSVD1_SHIFT                 24
+#define PMU_REG_1P0A_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD1_SHIFT))&PMU_REG_1P0A_RSVD1_MASK)
+/* REG_1P0A_SET Bit Fields */
+#define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK      0x1u
+#define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT     0
+#define PMU_REG_1P0A_SET_ENABLE_BO_MASK          0x2u
+#define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT         1
+#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK      0x4u
+#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT     2
+#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK    0x8u
+#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT   3
+#define PMU_REG_1P0A_SET_BO_OFFSET_MASK          0x70u
+#define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT         4
+#define PMU_REG_1P0A_SET_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0A_SET_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK   0x80u
+#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT  7
+#define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK         0x1F00u
+#define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT        8
+#define PMU_REG_1P0A_SET_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_SET_RSVD0_MASK              0xE000u
+#define PMU_REG_1P0A_SET_RSVD0_SHIFT             13
+#define PMU_REG_1P0A_SET_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD0_SHIFT))&PMU_REG_1P0A_SET_RSVD0_MASK)
+#define PMU_REG_1P0A_SET_BO_MASK                 0x10000u
+#define PMU_REG_1P0A_SET_BO_SHIFT                16
+#define PMU_REG_1P0A_SET_OK_MASK                 0x20000u
+#define PMU_REG_1P0A_SET_OK_SHIFT                17
+#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0A_SET_REG_TEST_MASK           0xF00000u
+#define PMU_REG_1P0A_SET_REG_TEST_SHIFT          20
+#define PMU_REG_1P0A_SET_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_REG_TEST_SHIFT))&PMU_REG_1P0A_SET_REG_TEST_MASK)
+#define PMU_REG_1P0A_SET_RSVD1_MASK              0xFF000000u
+#define PMU_REG_1P0A_SET_RSVD1_SHIFT             24
+#define PMU_REG_1P0A_SET_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD1_SHIFT))&PMU_REG_1P0A_SET_RSVD1_MASK)
+/* REG_1P0A_CLR Bit Fields */
+#define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK      0x1u
+#define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT     0
+#define PMU_REG_1P0A_CLR_ENABLE_BO_MASK          0x2u
+#define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT         1
+#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK      0x4u
+#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT     2
+#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK    0x8u
+#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT   3
+#define PMU_REG_1P0A_CLR_BO_OFFSET_MASK          0x70u
+#define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT         4
+#define PMU_REG_1P0A_CLR_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0A_CLR_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK   0x80u
+#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT  7
+#define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK         0x1F00u
+#define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT        8
+#define PMU_REG_1P0A_CLR_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_CLR_RSVD0_MASK              0xE000u
+#define PMU_REG_1P0A_CLR_RSVD0_SHIFT             13
+#define PMU_REG_1P0A_CLR_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD0_SHIFT))&PMU_REG_1P0A_CLR_RSVD0_MASK)
+#define PMU_REG_1P0A_CLR_BO_MASK                 0x10000u
+#define PMU_REG_1P0A_CLR_BO_SHIFT                16
+#define PMU_REG_1P0A_CLR_OK_MASK                 0x20000u
+#define PMU_REG_1P0A_CLR_OK_SHIFT                17
+#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0A_CLR_REG_TEST_MASK           0xF00000u
+#define PMU_REG_1P0A_CLR_REG_TEST_SHIFT          20
+#define PMU_REG_1P0A_CLR_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_REG_TEST_SHIFT))&PMU_REG_1P0A_CLR_REG_TEST_MASK)
+#define PMU_REG_1P0A_CLR_RSVD1_MASK              0xFF000000u
+#define PMU_REG_1P0A_CLR_RSVD1_SHIFT             24
+#define PMU_REG_1P0A_CLR_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD1_SHIFT))&PMU_REG_1P0A_CLR_RSVD1_MASK)
+/* REG_1P0A_TOG Bit Fields */
+#define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK      0x1u
+#define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT     0
+#define PMU_REG_1P0A_TOG_ENABLE_BO_MASK          0x2u
+#define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT         1
+#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK      0x4u
+#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT     2
+#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK    0x8u
+#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT   3
+#define PMU_REG_1P0A_TOG_BO_OFFSET_MASK          0x70u
+#define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT         4
+#define PMU_REG_1P0A_TOG_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0A_TOG_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK   0x80u
+#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT  7
+#define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK         0x1F00u
+#define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT        8
+#define PMU_REG_1P0A_TOG_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_TOG_RSVD0_MASK              0xE000u
+#define PMU_REG_1P0A_TOG_RSVD0_SHIFT             13
+#define PMU_REG_1P0A_TOG_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD0_SHIFT))&PMU_REG_1P0A_TOG_RSVD0_MASK)
+#define PMU_REG_1P0A_TOG_BO_MASK                 0x10000u
+#define PMU_REG_1P0A_TOG_BO_SHIFT                16
+#define PMU_REG_1P0A_TOG_OK_MASK                 0x20000u
+#define PMU_REG_1P0A_TOG_OK_SHIFT                17
+#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0A_TOG_REG_TEST_MASK           0xF00000u
+#define PMU_REG_1P0A_TOG_REG_TEST_SHIFT          20
+#define PMU_REG_1P0A_TOG_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_REG_TEST_SHIFT))&PMU_REG_1P0A_TOG_REG_TEST_MASK)
+#define PMU_REG_1P0A_TOG_RSVD1_MASK              0xFF000000u
+#define PMU_REG_1P0A_TOG_RSVD1_SHIFT             24
+#define PMU_REG_1P0A_TOG_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD1_SHIFT))&PMU_REG_1P0A_TOG_RSVD1_MASK)
+/* REG_1P0D Bit Fields */
+#define PMU_REG_1P0D_ENABLE_LINREG_MASK          0x1u
+#define PMU_REG_1P0D_ENABLE_LINREG_SHIFT         0
+#define PMU_REG_1P0D_ENABLE_BO_MASK              0x2u
+#define PMU_REG_1P0D_ENABLE_BO_SHIFT             1
+#define PMU_REG_1P0D_ENABLE_ILIMIT_MASK          0x4u
+#define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT         2
+#define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK        0x8u
+#define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT       3
+#define PMU_REG_1P0D_BO_OFFSET_MASK              0x70u
+#define PMU_REG_1P0D_BO_OFFSET_SHIFT             4
+#define PMU_REG_1P0D_BO_OFFSET(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_BO_OFFSET_SHIFT))&PMU_REG_1P0D_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK       0x80u
+#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT      7
+#define PMU_REG_1P0D_OUTPUT_TRG_MASK             0x1F00u
+#define PMU_REG_1P0D_OUTPUT_TRG_SHIFT            8
+#define PMU_REG_1P0D_OUTPUT_TRG(x)               (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_RSVD0_MASK                  0xE000u
+#define PMU_REG_1P0D_RSVD0_SHIFT                 13
+#define PMU_REG_1P0D_RSVD0(x)                    (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD0_SHIFT))&PMU_REG_1P0D_RSVD0_MASK)
+#define PMU_REG_1P0D_BO_MASK                     0x10000u
+#define PMU_REG_1P0D_BO_SHIFT                    16
+#define PMU_REG_1P0D_OK_MASK                     0x20000u
+#define PMU_REG_1P0D_OK_SHIFT                    17
+#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK     0x40000u
+#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT    18
+#define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK     0x80000u
+#define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT    19
+#define PMU_REG_1P0D_REG_TEST_MASK               0xF00000u
+#define PMU_REG_1P0D_REG_TEST_SHIFT              20
+#define PMU_REG_1P0D_REG_TEST(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_REG_TEST_SHIFT))&PMU_REG_1P0D_REG_TEST_MASK)
+#define PMU_REG_1P0D_RSVD1_MASK                  0x7F000000u
+#define PMU_REG_1P0D_RSVD1_SHIFT                 24
+#define PMU_REG_1P0D_RSVD1(x)                    (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD1_SHIFT))&PMU_REG_1P0D_RSVD1_MASK)
+#define PMU_REG_1P0D_OVERRIDE_MASK               0x80000000u
+#define PMU_REG_1P0D_OVERRIDE_SHIFT              31
+/* REG_1P0D_SET Bit Fields */
+#define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK      0x1u
+#define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT     0
+#define PMU_REG_1P0D_SET_ENABLE_BO_MASK          0x2u
+#define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT         1
+#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK      0x4u
+#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT     2
+#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK    0x8u
+#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT   3
+#define PMU_REG_1P0D_SET_BO_OFFSET_MASK          0x70u
+#define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT         4
+#define PMU_REG_1P0D_SET_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0D_SET_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK   0x80u
+#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT  7
+#define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK         0x1F00u
+#define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT        8
+#define PMU_REG_1P0D_SET_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_SET_RSVD0_MASK              0xE000u
+#define PMU_REG_1P0D_SET_RSVD0_SHIFT             13
+#define PMU_REG_1P0D_SET_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD0_SHIFT))&PMU_REG_1P0D_SET_RSVD0_MASK)
+#define PMU_REG_1P0D_SET_BO_MASK                 0x10000u
+#define PMU_REG_1P0D_SET_BO_SHIFT                16
+#define PMU_REG_1P0D_SET_OK_MASK                 0x20000u
+#define PMU_REG_1P0D_SET_OK_SHIFT                17
+#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0D_SET_REG_TEST_MASK           0xF00000u
+#define PMU_REG_1P0D_SET_REG_TEST_SHIFT          20
+#define PMU_REG_1P0D_SET_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_REG_TEST_SHIFT))&PMU_REG_1P0D_SET_REG_TEST_MASK)
+#define PMU_REG_1P0D_SET_RSVD1_MASK              0x7F000000u
+#define PMU_REG_1P0D_SET_RSVD1_SHIFT             24
+#define PMU_REG_1P0D_SET_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD1_SHIFT))&PMU_REG_1P0D_SET_RSVD1_MASK)
+#define PMU_REG_1P0D_SET_OVERRIDE_MASK           0x80000000u
+#define PMU_REG_1P0D_SET_OVERRIDE_SHIFT          31
+/* REG_1P0D_CLR Bit Fields */
+#define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK      0x1u
+#define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT     0
+#define PMU_REG_1P0D_CLR_ENABLE_BO_MASK          0x2u
+#define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT         1
+#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK      0x4u
+#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT     2
+#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK    0x8u
+#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT   3
+#define PMU_REG_1P0D_CLR_BO_OFFSET_MASK          0x70u
+#define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT         4
+#define PMU_REG_1P0D_CLR_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0D_CLR_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK   0x80u
+#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT  7
+#define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK         0x1F00u
+#define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT        8
+#define PMU_REG_1P0D_CLR_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_CLR_RSVD0_MASK              0xE000u
+#define PMU_REG_1P0D_CLR_RSVD0_SHIFT             13
+#define PMU_REG_1P0D_CLR_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD0_SHIFT))&PMU_REG_1P0D_CLR_RSVD0_MASK)
+#define PMU_REG_1P0D_CLR_BO_MASK                 0x10000u
+#define PMU_REG_1P0D_CLR_BO_SHIFT                16
+#define PMU_REG_1P0D_CLR_OK_MASK                 0x20000u
+#define PMU_REG_1P0D_CLR_OK_SHIFT                17
+#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0D_CLR_REG_TEST_MASK           0xF00000u
+#define PMU_REG_1P0D_CLR_REG_TEST_SHIFT          20
+#define PMU_REG_1P0D_CLR_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_REG_TEST_SHIFT))&PMU_REG_1P0D_CLR_REG_TEST_MASK)
+#define PMU_REG_1P0D_CLR_RSVD1_MASK              0x7F000000u
+#define PMU_REG_1P0D_CLR_RSVD1_SHIFT             24
+#define PMU_REG_1P0D_CLR_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD1_SHIFT))&PMU_REG_1P0D_CLR_RSVD1_MASK)
+#define PMU_REG_1P0D_CLR_OVERRIDE_MASK           0x80000000u
+#define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT          31
+/* REG_1P0D_TOG Bit Fields */
+#define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK      0x1u
+#define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT     0
+#define PMU_REG_1P0D_TOG_ENABLE_BO_MASK          0x2u
+#define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT         1
+#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK      0x4u
+#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT     2
+#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK    0x8u
+#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT   3
+#define PMU_REG_1P0D_TOG_BO_OFFSET_MASK          0x70u
+#define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT         4
+#define PMU_REG_1P0D_TOG_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0D_TOG_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK   0x80u
+#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT  7
+#define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK         0x1F00u
+#define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT        8
+#define PMU_REG_1P0D_TOG_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_TOG_RSVD0_MASK              0xE000u
+#define PMU_REG_1P0D_TOG_RSVD0_SHIFT             13
+#define PMU_REG_1P0D_TOG_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD0_SHIFT))&PMU_REG_1P0D_TOG_RSVD0_MASK)
+#define PMU_REG_1P0D_TOG_BO_MASK                 0x10000u
+#define PMU_REG_1P0D_TOG_BO_SHIFT                16
+#define PMU_REG_1P0D_TOG_OK_MASK                 0x20000u
+#define PMU_REG_1P0D_TOG_OK_SHIFT                17
+#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0D_TOG_REG_TEST_MASK           0xF00000u
+#define PMU_REG_1P0D_TOG_REG_TEST_SHIFT          20
+#define PMU_REG_1P0D_TOG_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_REG_TEST_SHIFT))&PMU_REG_1P0D_TOG_REG_TEST_MASK)
+#define PMU_REG_1P0D_TOG_RSVD1_MASK              0x7F000000u
+#define PMU_REG_1P0D_TOG_RSVD1_SHIFT             24
+#define PMU_REG_1P0D_TOG_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD1_SHIFT))&PMU_REG_1P0D_TOG_RSVD1_MASK)
+#define PMU_REG_1P0D_TOG_OVERRIDE_MASK           0x80000000u
+#define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT          31
+/* REG_HSIC_1P2 Bit Fields */
+#define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK      0x1u
+#define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT     0
+#define PMU_REG_HSIC_1P2_ENABLE_BO_MASK          0x2u
+#define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT         1
+#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK      0x4u
+#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT     2
+#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK    0x8u
+#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT   3
+#define PMU_REG_HSIC_1P2_BO_OFFSET_MASK          0x70u
+#define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT         4
+#define PMU_REG_HSIC_1P2_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK   0x80u
+#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT  7
+#define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK         0x1F00u
+#define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT        8
+#define PMU_REG_HSIC_1P2_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_RSVD0_MASK              0xE000u
+#define PMU_REG_HSIC_1P2_RSVD0_SHIFT             13
+#define PMU_REG_HSIC_1P2_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_BO_MASK                 0x10000u
+#define PMU_REG_HSIC_1P2_BO_SHIFT                16
+#define PMU_REG_HSIC_1P2_OK_MASK                 0x20000u
+#define PMU_REG_HSIC_1P2_OK_SHIFT                17
+#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_REG_TEST_MASK           0xF00000u
+#define PMU_REG_HSIC_1P2_REG_TEST_SHIFT          20
+#define PMU_REG_HSIC_1P2_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_RSVD1_MASK              0x7F000000u
+#define PMU_REG_HSIC_1P2_RSVD1_SHIFT             24
+#define PMU_REG_HSIC_1P2_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_OVERRIDE_MASK           0x80000000u
+#define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT          31
+/* REG_HSIC_1P2_SET Bit Fields */
+#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK  0x1u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK      0x2u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT     1
+#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK  0x4u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK      0x70u
+#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT     4
+#define PMU_REG_HSIC_1P2_SET_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK     0x1F00u
+#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT    8
+#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_SET_RSVD0_MASK          0xE000u
+#define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT         13
+#define PMU_REG_HSIC_1P2_SET_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_SET_BO_MASK             0x10000u
+#define PMU_REG_HSIC_1P2_SET_BO_SHIFT            16
+#define PMU_REG_HSIC_1P2_SET_OK_MASK             0x20000u
+#define PMU_REG_HSIC_1P2_SET_OK_SHIFT            17
+#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK       0xF00000u
+#define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT      20
+#define PMU_REG_HSIC_1P2_SET_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_SET_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_SET_RSVD1_MASK          0x7F000000u
+#define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT         24
+#define PMU_REG_HSIC_1P2_SET_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK       0x80000000u
+#define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT      31
+/* REG_HSIC_1P2_CLR Bit Fields */
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK  0x1u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK      0x2u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT     1
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK  0x4u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK      0x70u
+#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT     4
+#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK     0x1F00u
+#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT    8
+#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK          0xE000u
+#define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT         13
+#define PMU_REG_HSIC_1P2_CLR_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_CLR_BO_MASK             0x10000u
+#define PMU_REG_HSIC_1P2_CLR_BO_SHIFT            16
+#define PMU_REG_HSIC_1P2_CLR_OK_MASK             0x20000u
+#define PMU_REG_HSIC_1P2_CLR_OK_SHIFT            17
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK       0xF00000u
+#define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT      20
+#define PMU_REG_HSIC_1P2_CLR_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK          0x7F000000u
+#define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT         24
+#define PMU_REG_HSIC_1P2_CLR_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK       0x80000000u
+#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT      31
+/* REG_HSIC_1P2_TOG Bit Fields */
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK  0x1u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK      0x2u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT     1
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK  0x4u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK      0x70u
+#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT     4
+#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK     0x1F00u
+#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT    8
+#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK          0xE000u
+#define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT         13
+#define PMU_REG_HSIC_1P2_TOG_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_TOG_BO_MASK             0x10000u
+#define PMU_REG_HSIC_1P2_TOG_BO_SHIFT            16
+#define PMU_REG_HSIC_1P2_TOG_OK_MASK             0x20000u
+#define PMU_REG_HSIC_1P2_TOG_OK_SHIFT            17
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK       0xF00000u
+#define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT      20
+#define PMU_REG_HSIC_1P2_TOG_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK          0x7F000000u
+#define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT         24
+#define PMU_REG_HSIC_1P2_TOG_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK       0x80000000u
+#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT      31
+/* REG_LPSR_1P0 Bit Fields */
+#define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK      0x1u
+#define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT     0
+#define PMU_REG_LPSR_1P0_ENABLE_BO_MASK          0x2u
+#define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT         1
+#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK      0x4u
+#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT     2
+#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK    0x8u
+#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT   3
+#define PMU_REG_LPSR_1P0_BO_OFFSET_MASK          0x70u
+#define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT         4
+#define PMU_REG_LPSR_1P0_BO_OFFSET(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK   0x80u
+#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT  7
+#define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK         0x1F00u
+#define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT        8
+#define PMU_REG_LPSR_1P0_OUTPUT_TRG(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_RSVD0_MASK              0xE000u
+#define PMU_REG_LPSR_1P0_RSVD0_SHIFT             13
+#define PMU_REG_LPSR_1P0_RSVD0(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_BO_MASK                 0x10000u
+#define PMU_REG_LPSR_1P0_BO_SHIFT                16
+#define PMU_REG_LPSR_1P0_OK_MASK                 0x20000u
+#define PMU_REG_LPSR_1P0_OK_SHIFT                17
+#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_REG_TEST_MASK           0xF00000u
+#define PMU_REG_LPSR_1P0_REG_TEST_SHIFT          20
+#define PMU_REG_LPSR_1P0_REG_TEST(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_RSVD1_MASK              0xFF000000u
+#define PMU_REG_LPSR_1P0_RSVD1_SHIFT             24
+#define PMU_REG_LPSR_1P0_RSVD1(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_RSVD1_MASK)
+/* REG_LPSR_1P0_SET Bit Fields */
+#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK  0x1u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK      0x2u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT     1
+#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK  0x4u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK      0x70u
+#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT     4
+#define PMU_REG_LPSR_1P0_SET_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK     0x1F00u
+#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT    8
+#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_SET_RSVD0_MASK          0xE000u
+#define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT         13
+#define PMU_REG_LPSR_1P0_SET_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_SET_BO_MASK             0x10000u
+#define PMU_REG_LPSR_1P0_SET_BO_SHIFT            16
+#define PMU_REG_LPSR_1P0_SET_OK_MASK             0x20000u
+#define PMU_REG_LPSR_1P0_SET_OK_SHIFT            17
+#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK       0xF00000u
+#define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT      20
+#define PMU_REG_LPSR_1P0_SET_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_SET_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_SET_RSVD1_MASK          0xFF000000u
+#define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT         24
+#define PMU_REG_LPSR_1P0_SET_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD1_MASK)
+/* REG_LPSR_1P0_CLR Bit Fields */
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK  0x1u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK      0x2u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT     1
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK  0x4u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK      0x70u
+#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT     4
+#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK     0x1F00u
+#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT    8
+#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK          0xE000u
+#define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT         13
+#define PMU_REG_LPSR_1P0_CLR_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_CLR_BO_MASK             0x10000u
+#define PMU_REG_LPSR_1P0_CLR_BO_SHIFT            16
+#define PMU_REG_LPSR_1P0_CLR_OK_MASK             0x20000u
+#define PMU_REG_LPSR_1P0_CLR_OK_SHIFT            17
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK       0xF00000u
+#define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT      20
+#define PMU_REG_LPSR_1P0_CLR_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK          0xFF000000u
+#define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT         24
+#define PMU_REG_LPSR_1P0_CLR_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD1_MASK)
+/* REG_LPSR_1P0_TOG Bit Fields */
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK  0x1u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK      0x2u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT     1
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK  0x4u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK      0x70u
+#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT     4
+#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET(x)        (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK     0x1F00u
+#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT    8
+#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK          0xE000u
+#define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT         13
+#define PMU_REG_LPSR_1P0_TOG_RSVD0(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_TOG_BO_MASK             0x10000u
+#define PMU_REG_LPSR_1P0_TOG_BO_SHIFT            16
+#define PMU_REG_LPSR_1P0_TOG_OK_MASK             0x20000u
+#define PMU_REG_LPSR_1P0_TOG_OK_SHIFT            17
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK       0xF00000u
+#define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT      20
+#define PMU_REG_LPSR_1P0_TOG_REG_TEST(x)         (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK          0xFF000000u
+#define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT         24
+#define PMU_REG_LPSR_1P0_TOG_RSVD1(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK)
+/* REG_3P0 Bit Fields */
+#define PMU_REG_3P0_ENABLE_LINREG_MASK           0x1u
+#define PMU_REG_3P0_ENABLE_LINREG_SHIFT          0
+#define PMU_REG_3P0_ENABLE_BO_MASK               0x2u
+#define PMU_REG_3P0_ENABLE_BO_SHIFT              1
+#define PMU_REG_3P0_ENABLE_ILIMIT_MASK           0x4u
+#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT          2
+#define PMU_REG_3P0_RSVD0_MASK                   0x8u
+#define PMU_REG_3P0_RSVD0_SHIFT                  3
+#define PMU_REG_3P0_BO_OFFSET_MASK               0x70u
+#define PMU_REG_3P0_BO_OFFSET_SHIFT              4
+#define PMU_REG_3P0_BO_OFFSET(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK)
+#define PMU_REG_3P0_VBUS_SEL_MASK                0x80u
+#define PMU_REG_3P0_VBUS_SEL_SHIFT               7
+#define PMU_REG_3P0_OUTPUT_TRG_MASK              0x1F00u
+#define PMU_REG_3P0_OUTPUT_TRG_SHIFT             8
+#define PMU_REG_3P0_OUTPUT_TRG(x)                (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_RSVD1_MASK                   0xE000u
+#define PMU_REG_3P0_RSVD1_SHIFT                  13
+#define PMU_REG_3P0_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD1_SHIFT))&PMU_REG_3P0_RSVD1_MASK)
+#define PMU_REG_3P0_BO_VDD3P0_MASK               0x10000u
+#define PMU_REG_3P0_BO_VDD3P0_SHIFT              16
+#define PMU_REG_3P0_OK_VDD3P0_MASK               0x20000u
+#define PMU_REG_3P0_OK_VDD3P0_SHIFT              17
+#define PMU_REG_3P0_REG_TEST_MASK                0x3C0000u
+#define PMU_REG_3P0_REG_TEST_SHIFT               18
+#define PMU_REG_3P0_REG_TEST(x)                  (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_REG_TEST_SHIFT))&PMU_REG_3P0_REG_TEST_MASK)
+#define PMU_REG_3P0_RSVD2_MASK                   0xFFC00000u
+#define PMU_REG_3P0_RSVD2_SHIFT                  22
+#define PMU_REG_3P0_RSVD2(x)                     (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD2_SHIFT))&PMU_REG_3P0_RSVD2_MASK)
+/* REG_3P0_SET Bit Fields */
+#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK       0x1u
+#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT      0
+#define PMU_REG_3P0_SET_ENABLE_BO_MASK           0x2u
+#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT          1
+#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK       0x4u
+#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT      2
+#define PMU_REG_3P0_SET_RSVD0_MASK               0x8u
+#define PMU_REG_3P0_SET_RSVD0_SHIFT              3
+#define PMU_REG_3P0_SET_BO_OFFSET_MASK           0x70u
+#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT          4
+#define PMU_REG_3P0_SET_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_BO_OFFSET_SHIFT))&PMU_REG_3P0_SET_BO_OFFSET_MASK)
+#define PMU_REG_3P0_SET_VBUS_SEL_MASK            0x80u
+#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT           7
+#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK          0x1F00u
+#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT         8
+#define PMU_REG_3P0_SET_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_SET_RSVD1_MASK               0xE000u
+#define PMU_REG_3P0_SET_RSVD1_SHIFT              13
+#define PMU_REG_3P0_SET_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD1_SHIFT))&PMU_REG_3P0_SET_RSVD1_MASK)
+#define PMU_REG_3P0_SET_BO_VDD3P0_MASK           0x10000u
+#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT          16
+#define PMU_REG_3P0_SET_OK_VDD3P0_MASK           0x20000u
+#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT          17
+#define PMU_REG_3P0_SET_REG_TEST_MASK            0x3C0000u
+#define PMU_REG_3P0_SET_REG_TEST_SHIFT           18
+#define PMU_REG_3P0_SET_REG_TEST(x)              (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_REG_TEST_SHIFT))&PMU_REG_3P0_SET_REG_TEST_MASK)
+#define PMU_REG_3P0_SET_RSVD2_MASK               0xFFC00000u
+#define PMU_REG_3P0_SET_RSVD2_SHIFT              22
+#define PMU_REG_3P0_SET_RSVD2(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD2_SHIFT))&PMU_REG_3P0_SET_RSVD2_MASK)
+/* REG_3P0_CLR Bit Fields */
+#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK       0x1u
+#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT      0
+#define PMU_REG_3P0_CLR_ENABLE_BO_MASK           0x2u
+#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT          1
+#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK       0x4u
+#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT      2
+#define PMU_REG_3P0_CLR_RSVD0_MASK               0x8u
+#define PMU_REG_3P0_CLR_RSVD0_SHIFT              3
+#define PMU_REG_3P0_CLR_BO_OFFSET_MASK           0x70u
+#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT          4
+#define PMU_REG_3P0_CLR_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_3P0_CLR_BO_OFFSET_MASK)
+#define PMU_REG_3P0_CLR_VBUS_SEL_MASK            0x80u
+#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT           7
+#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK          0x1F00u
+#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT         8
+#define PMU_REG_3P0_CLR_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_CLR_RSVD1_MASK               0xE000u
+#define PMU_REG_3P0_CLR_RSVD1_SHIFT              13
+#define PMU_REG_3P0_CLR_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD1_SHIFT))&PMU_REG_3P0_CLR_RSVD1_MASK)
+#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK           0x10000u
+#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT          16
+#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK           0x20000u
+#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT          17
+#define PMU_REG_3P0_CLR_REG_TEST_MASK            0x3C0000u
+#define PMU_REG_3P0_CLR_REG_TEST_SHIFT           18
+#define PMU_REG_3P0_CLR_REG_TEST(x)              (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_REG_TEST_SHIFT))&PMU_REG_3P0_CLR_REG_TEST_MASK)
+#define PMU_REG_3P0_CLR_RSVD2_MASK               0xFFC00000u
+#define PMU_REG_3P0_CLR_RSVD2_SHIFT              22
+#define PMU_REG_3P0_CLR_RSVD2(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD2_SHIFT))&PMU_REG_3P0_CLR_RSVD2_MASK)
+/* REG_3P0_TOG Bit Fields */
+#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK       0x1u
+#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT      0
+#define PMU_REG_3P0_TOG_ENABLE_BO_MASK           0x2u
+#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT          1
+#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK       0x4u
+#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT      2
+#define PMU_REG_3P0_TOG_RSVD0_MASK               0x8u
+#define PMU_REG_3P0_TOG_RSVD0_SHIFT              3
+#define PMU_REG_3P0_TOG_BO_OFFSET_MASK           0x70u
+#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT          4
+#define PMU_REG_3P0_TOG_BO_OFFSET(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_3P0_TOG_BO_OFFSET_MASK)
+#define PMU_REG_3P0_TOG_VBUS_SEL_MASK            0x80u
+#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT           7
+#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK          0x1F00u
+#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT         8
+#define PMU_REG_3P0_TOG_OUTPUT_TRG(x)            (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_TOG_RSVD1_MASK               0xE000u
+#define PMU_REG_3P0_TOG_RSVD1_SHIFT              13
+#define PMU_REG_3P0_TOG_RSVD1(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD1_SHIFT))&PMU_REG_3P0_TOG_RSVD1_MASK)
+#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK           0x10000u
+#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT          16
+#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK           0x20000u
+#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT          17
+#define PMU_REG_3P0_TOG_REG_TEST_MASK            0x3C0000u
+#define PMU_REG_3P0_TOG_REG_TEST_SHIFT           18
+#define PMU_REG_3P0_TOG_REG_TEST(x)              (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_REG_TEST_SHIFT))&PMU_REG_3P0_TOG_REG_TEST_MASK)
+#define PMU_REG_3P0_TOG_RSVD2_MASK               0xFFC00000u
+#define PMU_REG_3P0_TOG_RSVD2_SHIFT              22
+#define PMU_REG_3P0_TOG_RSVD2(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD2_SHIFT))&PMU_REG_3P0_TOG_RSVD2_MASK)
+/* REF Bit Fields */
+#define PMU_REF_REFTOP_PWD_MASK                  0x1u
+#define PMU_REF_REFTOP_PWD_SHIFT                 0
+#define PMU_REF_REFTOP_PWDVBGUP_MASK             0x2u
+#define PMU_REF_REFTOP_PWDVBGUP_SHIFT            1
+#define PMU_REF_REFTOP_LOWPOWER_MASK             0x4u
+#define PMU_REF_REFTOP_LOWPOWER_SHIFT            2
+#define PMU_REF_REFTOP_SELFBIASOFF_MASK          0x8u
+#define PMU_REF_REFTOP_SELFBIASOFF_SHIFT         3
+#define PMU_REF_REFTOP_VBGADJ_MASK               0x70u
+#define PMU_REF_REFTOP_VBGADJ_SHIFT              4
+#define PMU_REF_REFTOP_VBGADJ(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_VBGADJ_SHIFT))&PMU_REF_REFTOP_VBGADJ_MASK)
+#define PMU_REF_REFTOP_VBGUP_MASK                0x80u
+#define PMU_REF_REFTOP_VBGUP_SHIFT               7
+#define PMU_REF_REFTOP_BIAS_TST_MASK             0x300u
+#define PMU_REF_REFTOP_BIAS_TST_SHIFT            8
+#define PMU_REF_REFTOP_BIAS_TST(x)               (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_BIAS_TST_SHIFT))&PMU_REF_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_LPBG_SEL_MASK                    0x400u
+#define PMU_REF_LPBG_SEL_SHIFT                   10
+#define PMU_REF_LPBG_TEST_MASK                   0x800u
+#define PMU_REF_LPBG_TEST_SHIFT                  11
+#define PMU_REF_REFTOP_IBIAS_OFF_MASK            0x1000u
+#define PMU_REF_REFTOP_IBIAS_OFF_SHIFT           12
+#define PMU_REF_REFTOP_LINREGREF_EN_MASK         0x2000u
+#define PMU_REF_REFTOP_LINREGREF_EN_SHIFT        13
+#define PMU_REF_RSVD1_MASK                       0xFFFFC000u
+#define PMU_REF_RSVD1_SHIFT                      14
+#define PMU_REF_RSVD1(x)                         (((uint32_t)(((uint32_t)(x))<<PMU_REF_RSVD1_SHIFT))&PMU_REF_RSVD1_MASK)
+/* REF_SET Bit Fields */
+#define PMU_REF_SET_REFTOP_PWD_MASK              0x1u
+#define PMU_REF_SET_REFTOP_PWD_SHIFT             0
+#define PMU_REF_SET_REFTOP_PWDVBGUP_MASK         0x2u
+#define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT        1
+#define PMU_REF_SET_REFTOP_LOWPOWER_MASK         0x4u
+#define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT        2
+#define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK      0x8u
+#define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT     3
+#define PMU_REF_SET_REFTOP_VBGADJ_MASK           0x70u
+#define PMU_REF_SET_REFTOP_VBGADJ_SHIFT          4
+#define PMU_REF_SET_REFTOP_VBGADJ(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_VBGADJ_SHIFT))&PMU_REF_SET_REFTOP_VBGADJ_MASK)
+#define PMU_REF_SET_REFTOP_VBGUP_MASK            0x80u
+#define PMU_REF_SET_REFTOP_VBGUP_SHIFT           7
+#define PMU_REF_SET_REFTOP_BIAS_TST_MASK         0x300u
+#define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT        8
+#define PMU_REF_SET_REFTOP_BIAS_TST(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_BIAS_TST_SHIFT))&PMU_REF_SET_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_SET_LPBG_SEL_MASK                0x400u
+#define PMU_REF_SET_LPBG_SEL_SHIFT               10
+#define PMU_REF_SET_LPBG_TEST_MASK               0x800u
+#define PMU_REF_SET_LPBG_TEST_SHIFT              11
+#define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK        0x1000u
+#define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT       12
+#define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK     0x2000u
+#define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT    13
+#define PMU_REF_SET_RSVD1_MASK                   0xFFFFC000u
+#define PMU_REF_SET_RSVD1_SHIFT                  14
+#define PMU_REF_SET_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_RSVD1_SHIFT))&PMU_REF_SET_RSVD1_MASK)
+/* REF_CLR Bit Fields */
+#define PMU_REF_CLR_REFTOP_PWD_MASK              0x1u
+#define PMU_REF_CLR_REFTOP_PWD_SHIFT             0
+#define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK         0x2u
+#define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT        1
+#define PMU_REF_CLR_REFTOP_LOWPOWER_MASK         0x4u
+#define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT        2
+#define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK      0x8u
+#define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT     3
+#define PMU_REF_CLR_REFTOP_VBGADJ_MASK           0x70u
+#define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT          4
+#define PMU_REF_CLR_REFTOP_VBGADJ(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_VBGADJ_SHIFT))&PMU_REF_CLR_REFTOP_VBGADJ_MASK)
+#define PMU_REF_CLR_REFTOP_VBGUP_MASK            0x80u
+#define PMU_REF_CLR_REFTOP_VBGUP_SHIFT           7
+#define PMU_REF_CLR_REFTOP_BIAS_TST_MASK         0x300u
+#define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT        8
+#define PMU_REF_CLR_REFTOP_BIAS_TST(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT))&PMU_REF_CLR_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_CLR_LPBG_SEL_MASK                0x400u
+#define PMU_REF_CLR_LPBG_SEL_SHIFT               10
+#define PMU_REF_CLR_LPBG_TEST_MASK               0x800u
+#define PMU_REF_CLR_LPBG_TEST_SHIFT              11
+#define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK        0x1000u
+#define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT       12
+#define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK     0x2000u
+#define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT    13
+#define PMU_REF_CLR_RSVD1_MASK                   0xFFFFC000u
+#define PMU_REF_CLR_RSVD1_SHIFT                  14
+#define PMU_REF_CLR_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_RSVD1_SHIFT))&PMU_REF_CLR_RSVD1_MASK)
+/* REF_TOG Bit Fields */
+#define PMU_REF_TOG_REFTOP_PWD_MASK              0x1u
+#define PMU_REF_TOG_REFTOP_PWD_SHIFT             0
+#define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK         0x2u
+#define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT        1
+#define PMU_REF_TOG_REFTOP_LOWPOWER_MASK         0x4u
+#define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT        2
+#define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK      0x8u
+#define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT     3
+#define PMU_REF_TOG_REFTOP_VBGADJ_MASK           0x70u
+#define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT          4
+#define PMU_REF_TOG_REFTOP_VBGADJ(x)             (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_VBGADJ_SHIFT))&PMU_REF_TOG_REFTOP_VBGADJ_MASK)
+#define PMU_REF_TOG_REFTOP_VBGUP_MASK            0x80u
+#define PMU_REF_TOG_REFTOP_VBGUP_SHIFT           7
+#define PMU_REF_TOG_REFTOP_BIAS_TST_MASK         0x300u
+#define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT        8
+#define PMU_REF_TOG_REFTOP_BIAS_TST(x)           (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT))&PMU_REF_TOG_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_TOG_LPBG_SEL_MASK                0x400u
+#define PMU_REF_TOG_LPBG_SEL_SHIFT               10
+#define PMU_REF_TOG_LPBG_TEST_MASK               0x800u
+#define PMU_REF_TOG_LPBG_TEST_SHIFT              11
+#define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK        0x1000u
+#define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT       12
+#define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK     0x2000u
+#define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT    13
+#define PMU_REF_TOG_RSVD1_MASK                   0xFFFFC000u
+#define PMU_REF_TOG_RSVD1_SHIFT                  14
+#define PMU_REF_TOG_RSVD1(x)                     (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_RSVD1_SHIFT))&PMU_REF_TOG_RSVD1_MASK)
+/* LOWPWR_CTRL Bit Fields */
+#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK    0x3u
+#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT   0
+#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG(x)      (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_RSVD0_MASK               0xFCu
+#define PMU_LOWPWR_CTRL_RSVD0_SHIFT              2
+#define PMU_LOWPWR_CTRL_RSVD0(x)                 (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK          0x100u
+#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT         8
+#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK          0x200u
+#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT         9
+#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK         0x400u
+#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT        10
+#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK     0x800u
+#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT    11
+#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK         0x1000u
+#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT        12
+#define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK         0x2000u
+#define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT        13
+#define PMU_LOWPWR_CTRL_CONTROL0_MASK            0xFFC000u
+#define PMU_LOWPWR_CTRL_CONTROL0_SHIFT           14
+#define PMU_LOWPWR_CTRL_CONTROL0(x)              (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_CONTROL1_MASK            0xFF000000u
+#define PMU_LOWPWR_CTRL_CONTROL1_SHIFT           24
+#define PMU_LOWPWR_CTRL_CONTROL1(x)              (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CONTROL1_MASK)
+/* LOWPWR_CTRL_SET Bit Fields */
+#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u
+#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0
+#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG(x)  (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_SET_RSVD0_MASK           0xFCu
+#define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT          2
+#define PMU_LOWPWR_CTRL_SET_RSVD0(x)             (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_SET_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK      0x100u
+#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT     8
+#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK      0x200u
+#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT     9
+#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK     0x400u
+#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT    10
+#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u
+#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11
+#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK     0x1000u
+#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT    12
+#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK     0x2000u
+#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT    13
+#define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK        0xFFC000u
+#define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT       14
+#define PMU_LOWPWR_CTRL_SET_CONTROL0(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK        0xFF000000u
+#define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT       24
+#define PMU_LOWPWR_CTRL_SET_CONTROL1(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL1_MASK)
+/* LOWPWR_CTRL_CLR Bit Fields */
+#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u
+#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0
+#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG(x)  (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK           0xFCu
+#define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT          2
+#define PMU_LOWPWR_CTRL_CLR_RSVD0(x)             (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_CLR_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK      0x100u
+#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT     8
+#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK      0x200u
+#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT     9
+#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK     0x400u
+#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT    10
+#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u
+#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11
+#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK     0x1000u
+#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT    12
+#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK     0x2000u
+#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT    13
+#define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK        0xFFC000u
+#define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT       14
+#define PMU_LOWPWR_CTRL_CLR_CONTROL0(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK        0xFF000000u
+#define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT       24
+#define PMU_LOWPWR_CTRL_CLR_CONTROL1(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK)
+/* LOWPWR_CTRL_TOG Bit Fields */
+#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u
+#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0
+#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG(x)  (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK           0xFCu
+#define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT          2
+#define PMU_LOWPWR_CTRL_TOG_RSVD0(x)             (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_TOG_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK      0x100u
+#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT     8
+#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK      0x200u
+#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT     9
+#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK     0x400u
+#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT    10
+#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u
+#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11
+#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK     0x1000u
+#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT    12
+#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK     0x2000u
+#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT    13
+#define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK        0xFFC000u
+#define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT       14
+#define PMU_LOWPWR_CTRL_TOG_CONTROL0(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK        0xFF000000u
+#define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT       24
+#define PMU_LOWPWR_CTRL_TOG_CONTROL1(x)          (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK)
+
+
+/* HW_ANADIG_TEMPSENSE0 Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK  0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1(x)    (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE0_SET Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE1 Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK  0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0(x)    (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE1_SET Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)
+
+
+#define CCM_GPR(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i))
+#define CCM_OBSERVE(i)		(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i))
+#define CCM_SCTRL(i)		(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i))
+#define CCM_CCGR(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i))
+#define CCM_ROOT_TARGET(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
+
+#define CCM_GPR_SET(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
+#define CCM_OBSERVE_SET(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
+#define CCM_SCTRL_SET(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
+#define CCM_CCGR_SET(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
+#define CCM_ROOT_TARGET_SET(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
+
+#define CCM_GPR_CLR(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
+#define CCM_OBSERVE_CLR(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
+#define CCM_SCTRL_CLR(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
+#define CCM_CCGR_CLR(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
+#define CCM_ROOT_TARGET_CLR(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
+
+#define CCM_GPR_TOGGLE(i)	(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
+#define CCM_OBSERVE_TOGGLE(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
+#define CCM_SCTRL_TOGGLE(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
+#define CCM_CCGR_TOGGLE(i)	(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
+#define CCM_ROOT_TARGET_TOGGLE(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
+
+#define HW_CCM_GPR_WR(i, v)		writel((v), CCM_GPR(i))
+#define HW_CCM_CCM_OBSERVE_WR(i, v)	writel((v), CCM_OBSERVE(i))
+#define HW_CCM_SCTRL_WR(i, v)		writel((v), CCM_SCTRL(i))
+#define HW_CCM_CCGR_WR(i, v)		writel((v), CCM_CCGR(i))
+#define HW_CCM_ROOT_TARGET_WR(i, v)	writel((v), CCM_ROOT_TARGET(i))
+
+#define HW_CCM_GPR_RD(i)		readl(CCM_GPR(i))
+#define HW_CCM_CCM_OBSERVE_RD(i)	readl(CCM_OBSERVE(i))
+#define HW_CCM_SCTRL_RD(i)		readl(CCM_SCTRL(i))
+#define HW_CCM_CCGR_RD(i)		readl(CCM_CCGR(i))
+#define HW_CCM_ROOT_TARGET_RD(i)	readl(CCM_ROOT_TARGET(i))
+
+#define HW_CCM_GPR_SET(i, v)		writel((v), CCM_GPR_SET(i))
+#define HW_CCM_CCM_OBSERVE_SET(i, v)	writel((v), CCM_CCM_OBSERVE_SET(i))
+#define HW_CCM_SCTRL_SET(i, v)		writel((v), CCM_SCTRL_SET(i))
+#define HW_CCM_CCGR_SET(i, v)		writel((v), CCM_CCGR_SET(i))
+#define HW_CCM_ROOT_TARGET_SET(i, v)	writel((v), CCM_ROOT_TARGET_SET(i))
+
+#define HW_CCM_GPR_CLR(i, v)		writel((v), CCM_GPR_CLR(i))
+#define HW_CCM_CCM_OBSERVE_CLR(i, v)	writel((v), CCM_CCM_OBSERVE_CLR(i))
+#define HW_CCM_SCTRL_CLR(i, v)		writel((v), CCM_SCTRL_CLR(i))
+#define HW_CCM_CCGR_CLR(i, v)		writel((v), CCM_CCGR_CLR(i))
+#define HW_CCM_ROOT_TARGET_CLR(i, v)	writel((v), CCM_ROOT_TARGET_CLR(i))
+
+#define HW_CCM_GPR_TOGGLE(i, v)		writel((v), CCM_GPR_TOGGLE(i))
+#define HW_CCM_CCM_OBSERVE_TOGGLE(i, v)	writel((v), CCM_CCM_OBSERVE_TOGGLE(i))
+#define HW_CCM_SCTRL_TOGGLE(i, v)	writel((v), CCM_SCTRL_TOGGLE(i))
+#define HW_CCM_CCGR_TOGGLE(i, v)	writel((v), CCM_CCGR_TOGGLE(i))
+#define HW_CCM_ROOT_TARGET_TOGGLE(i, v)	writel((v), CCM_ROOT_TARGET_TOGGLE(i))
+
+#define CCM_CLK_ON_MSK	0x03
+#define CCM_CLK_ON_N_N	0x00 /* Domain clocks not needed */
+#define CCM_CLK_ON_R_W	0x02 /* Domain clocks needed when in RUN and WAIT */
+
+/* CCGR Mapping */
+#define CCGR_IDX_DDR 19 /* CCM_CCGR19 */
+
+#define CCM_ROOT_TGT_POST_DIV_SHIFT	0
+#define CCM_ROOT_TGT_PRE_DIV_SHIFT	15
+#define CCM_ROOT_TGT_MUX_SHIFT		24
+#define CCM_ROOT_TGT_ENABLE_SHIFT	28
+#define CCM_ROOT_TGT_POST_DIV_MSK	0x3F
+#define CCM_ROOT_TGT_PRE_DIV_MSK	(0x07 << CCM_ROOT_TGT_PRE_DIV_SHIFT)
+#define CCM_ROOT_TGT_MUX_MSK		(0x07 << CCM_ROOT_TGT_MUX_SHIFT)
+#define CCM_ROOT_TGT_ENABLE_MSK		(0x01 << CCM_ROOT_TGT_ENABLE_SHIFT)
+
+#define CCM_ROOT_TGT_POST_DIV(x)	((((x) - 1) << CCM_ROOT_TGT_POST_DIV_SHIFT) & CCM_ROOT_TGT_POST_DIV_MSK)
+#define CCM_ROOT_TGT_PRE_DIV(x)		((((x) - 1) << CCM_ROOT_TGT_PRE_DIV_SHIFT) & CCM_ROOT_TGT_PRE_DIV_MSK)
+#define CCM_ROOT_TGT_MUX_TO(x)		((((x) - 1) << CCM_ROOT_TGT_MUX_SHIFT) & CCM_ROOT_TGT_MUX_MSK)
+
+/*
+ * Field values definition for clock slice TARGET register
+ */
+
+#define CLK_ROOT_ON		0x10000000
+#define CLK_ROOT_OFF		0x0
+#define CLK_ROOT_ENABLE_MASK	0x10000000
+#define CLK_ROOT_ENABLE_SHIFT	28
+
+#define CLK_ROOT_ALT0		0x00000000
+#define CLK_ROOT_ALT1		0x01000000
+#define CLK_ROOT_ALT2		0x02000000
+#define CLK_ROOT_ALT3		0x03000000
+#define CLK_ROOT_ALT4		0x04000000
+#define CLK_ROOT_ALT5		0x05000000
+#define CLK_ROOT_ALT6		0x06000000
+#define CLK_ROOT_ALT7		0x07000000
+
+
+#define DRAM_CLK_ROOT_POST_DIV_MASK	0x00000007
+#define CLK_ROOT_POST_DIV_MASK	0x0000003f
+#define CLK_ROOT_POST_DIV_SHIFT	0
+#define CLK_ROOT_POST_DIV(n) ((n << CLK_ROOT_POST_DIV_SHIFT) & CLK_ROOT_POST_DIV_MASK)
+
+#define CLK_ROOT_AUTO_DIV_MASK	0x00000700
+#define CLK_ROOT_AUTO_DIV_SHIFT	8
+#define CLK_ROOT_AUTO_DIV(n) ((n << CLK_ROOT_AUTO_DIV_SHIFT) & CLK_ROOT_AUTO_DIV_MASK)
+
+#define CLK_ROOT_AUTO_EN_MASK	0x00001000
+#define CLK_ROOT_AUTO_EN	0x00001000
+
+#define CLK_ROOT_PRE_DIV_MASK	0x00070000
+#define CLK_ROOT_PRE_DIV_SHIFT	16
+#define CLK_ROOT_PRE_DIV(n) ((n << CLK_ROOT_PRE_DIV_SHIFT) & CLK_ROOT_PRE_DIV_MASK)
+
+#define CLK_ROOT_MUX_MASK	0x07000000
+#define CLK_ROOT_MUX_SHIFT	24
+
+#define CLK_ROOT_EN_MASK	0x10000000
+
+#define CLK_ROOT_AUTO_ON	0x00001000
+#define CLK_ROOT_AUTO_OFF	0x0
+
+/* ARM_A7_CLK_ROOT */
+#define ARM_A7_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_ARM_MAIN_800M_CLK		0x01000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK		0x03000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x05000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x02000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+
+/* ARM_M4_CLK_ROOT */
+#define ARM_M4_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x04000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x03000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x02000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x05000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x06000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+
+/* ARM_M0_CLK_ROOT */
+#define ARM_M0_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x04000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x03000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x02000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x05000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x06000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+
+/* MAIN_AXI_CLK_ROOT */
+#define MAIN_AXI_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK		0x01000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK			0x04000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x03000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
+
+/* DISP_AXI_CLK_ROOT */
+#define DISP_AXI_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK		0x01000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x04000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x05000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x03000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x06000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
+
+/* ENET_AXI_CLK_ROOT */
+#define ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x04000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x01000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x07000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x03000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
+
+/* NAND_USDHC_BUS_CLK_ROOT */
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_OSC_24M_CLK		0x00000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x02000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK	0x03000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK	0x01000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK	0x04000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK		0x05000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK	0x06000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x07000000
+
+/* AHB_CLK_ROOT */
+#define AHB_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define AHB_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK			0x03000000
+#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK			0x01000000
+#define AHB_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x04000000
+#define AHB_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
+#define AHB_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
+#define AHB_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK			0x05000000
+
+/* DRAM_PHYM_CLK_ROOT */
+#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK		0x00000000
+#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_PHYM_ALT_CLK_ROOT	0x01000000
+
+/* DRAM_CLK_ROOT */
+#define DRAM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK		0x00000000
+#define DRAM_CLK_ROOT_FROM_PLL_DRAM_ALT_CLK_ROOT		0x01000000
+
+/* DRAM_PHYM_ALT_CLK_ROOT */
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x01000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK	0x02000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK		0x05000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK	0x03000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x06000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK	0x04000000
+
+/* DRAM_ALT_CLK_ROOT */
+#define DRAM_ALT_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x01000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x02000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x05000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x07000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x03000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x04000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x06000000
+
+/* USB_HSIC_CLK_ROOT */
+#define USB_HSIC_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x01000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK			0x03000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x04000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK			0x05000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x06000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x02000000
+
+/* PCIE_CTRL_CLK_ROOT */
+#define PCIE_CTRL_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x04000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x02000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK		0x06000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x03000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK		0x07000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x05000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x01000000
+
+/* PCIE_PHY_CLK_ROOT */
+#define PCIE_PHY_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define PCIE_PHY_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x07000000
+#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x02000000
+#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_1			0x03000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_2			0x04000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_3			0x05000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_4			0x06000000
+
+/* EPDC_PIXEL_CLK_ROOT */
+#define EPDC_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x03000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK		0x01000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK		0x04000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK		0x05000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK		0x06000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
+
+/* LCDIF_PIXEL_CLK_ROOT */
+#define LCDIF_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x02000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK		0x04000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK		0x01000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_EXT_CLK_3			0x03000000
+
+/* MIPI_DSI_EXTSER_CLK_ROOT */
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_OSC_24M_CLK		0x00000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x05000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK	0x03000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK	0x04000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK		0x02000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK		0x01000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK	0x07000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK	0x06000000
+
+/* MIPI_CSI_WARP_CLK_ROOT */
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x05000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK	0x03000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK	0x04000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK		0x02000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK		0x01000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x07000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
+
+/* MIPI_DPHY_REF_CLK_ROOT */
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x02000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK	0x01000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK		0x03000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_REF_1M_CLK			0x04000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_2			0x05000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_3			0x07000000
+
+/* SAI1_CLK_ROOT */
+#define SAI1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define SAI1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
+#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
+#define SAI1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
+#define SAI1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x02000000
+#define SAI1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
+#define SAI1_CLK_ROOT_FROM_EXT_CLK_2				0x07000000
+
+/* SAI2_CLK_ROOT */
+#define SAI2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define SAI2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
+#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
+#define SAI2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
+#define SAI2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x02000000
+#define SAI2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
+#define SAI2_CLK_ROOT_FROM_EXT_CLK_2				0x07000000
+
+/* SAI3_CLK_ROOT */
+#define SAI3_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define SAI3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
+#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
+#define SAI3_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
+#define SAI3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x02000000
+#define SAI3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
+#define SAI3_CLK_ROOT_FROM_EXT_CLK_3				0x07000000
+
+/* SPDIF_CLK_ROOT */
+#define SPDIF_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define SPDIF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
+#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
+#define SPDIF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
+#define SPDIF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x02000000
+#define SPDIF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
+#define SPDIF_CLK_ROOT_FROM_EXT_CLK_3				0x07000000
+
+/* ENET1_REF_CLK_ROOT */
+#define ENET1_REF_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x04000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x01000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK		0x03000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
+#define ENET1_REF_CLK_ROOT_FROM_EXT_CLK_4			0x07000000
+
+/* ENET1_TIME_CLK_ROOT */
+#define ENET1_TIME_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x02000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_1			0x03000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_2			0x04000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_3			0x05000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_4			0x06000000
+
+/* ENET2_REF_CLK_ROOT */
+#define ENET2_REF_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x04000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x01000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK		0x03000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
+#define ENET2_REF_CLK_ROOT_FROM_EXT_CLK_4			0x07000000
+
+/* ENET2_TIME_CLK_ROOT */
+#define ENET2_TIME_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define ENET2_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x02000000
+#define ENET2_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_1			0x03000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_2			0x04000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_3			0x05000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_4			0x06000000
+
+/* ENET_PHY_REF_CLK_ROOT */
+#define ENET_PHY_REF_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK	0x04000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK		0x07000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK	0x03000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK	0x02000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK	0x01000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
+
+/* EIM_CLK_ROOT */
+#define EIM_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define EIM_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK			0x02000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK			0x04000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK			0x01000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK			0x05000000
+#define EIM_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
+#define EIM_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK			0x07000000
+
+/* NAND_CLK_ROOT */
+#define NAND_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define NAND_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define NAND_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x01000000
+#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x03000000
+#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK			0x04000000
+#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x05000000
+#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x06000000
+#define NAND_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
+
+/* QSPI_CLK_ROOT */
+#define QSPI_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define QSPI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK			0x04000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x01000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x06000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
+#define QSPI_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x03000000
+
+/* USDHC1_CLK_ROOT */
+#define USDHC1_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define USDHC1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x01000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x04000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x06000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
+#define USDHC1_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x03000000
+
+/* USDHC2_CLK_ROOT */
+#define USDHC2_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define USDHC2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x01000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x04000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x06000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
+#define USDHC2_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x03000000
+
+/* USDHC3_CLK_ROOT */
+#define USDHC3_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define USDHC3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x01000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x04000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK			0x06000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
+#define USDHC3_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x03000000
+
+/* CAN1_CLK_ROOT */
+#define CAN1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define CAN1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x03000000
+#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
+#define CAN1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x04000000
+#define CAN1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x05000000
+#define CAN1_CLK_ROOT_FROM_EXT_CLK_1				0x06000000
+#define CAN1_CLK_ROOT_FROM_EXT_CLK_4				0x07000000
+
+/* CAN2_CLK_ROOT */
+#define CAN2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define CAN2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x03000000
+#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
+#define CAN2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x04000000
+#define CAN2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x05000000
+#define CAN2_CLK_ROOT_FROM_EXT_CLK_1				0x06000000
+#define CAN2_CLK_ROOT_FROM_EXT_CLK_3				0x07000000
+
+/* I2C1_CLK_ROOT */
+#define I2C1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define I2C1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
+#define I2C1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x07000000
+#define I2C1_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
+#define I2C1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
+#define I2C1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x05000000
+#define I2C1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x06000000
+
+/* I2C2_CLK_ROOT */
+#define I2C2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define I2C2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define I2C2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
+#define I2C2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x07000000
+#define I2C2_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
+#define I2C2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
+#define I2C2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x05000000
+#define I2C2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x06000000
+
+/* I2C3_CLK_ROOT */
+#define I2C3_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define I2C3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define I2C3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
+#define I2C3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x07000000
+#define I2C3_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
+#define I2C3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
+#define I2C3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x05000000
+#define I2C3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x06000000
+
+/* I2C4_CLK_ROOT */
+#define I2C4_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define I2C4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define I2C4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x01000000
+#define I2C4_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x07000000
+#define I2C4_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
+#define I2C4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
+#define I2C4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x05000000
+#define I2C4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x06000000
+
+/* UART1_CLK_ROOT */
+#define UART1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
+#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
+#define UART1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+#define UART1_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
+#define UART1_CLK_ROOT_FROM_EXT_CLK_4				0x06000000
+
+/* UART2_CLK_ROOT */
+#define UART2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
+#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
+#define UART2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+#define UART2_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
+#define UART2_CLK_ROOT_FROM_EXT_CLK_3				0x06000000
+
+/* UART3_CLK_ROOT */
+#define UART3_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
+#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
+#define UART3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+#define UART3_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
+#define UART3_CLK_ROOT_FROM_EXT_CLK_4				0x06000000
+
+/* UART4_CLK_ROOT */
+#define UART4_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
+#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
+#define UART4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+#define UART4_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
+#define UART4_CLK_ROOT_FROM_EXT_CLK_3				0x06000000
+
+/* UART5_CLK_ROOT */
+#define UART5_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
+#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
+#define UART5_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+#define UART5_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
+#define UART5_CLK_ROOT_FROM_EXT_CLK_4				0x06000000
+
+/* UART6_CLK_ROOT */
+#define UART6_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
+#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
+#define UART6_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+#define UART6_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
+#define UART6_CLK_ROOT_FROM_EXT_CLK_3				0x06000000
+
+/* UART7_CLK_ROOT */
+#define UART7_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x03000000
+#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
+#define UART7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+#define UART7_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
+#define UART7_CLK_ROOT_FROM_EXT_CLK_4				0x06000000
+
+/* ECSPI1_CLK_ROOT */
+#define ECSPI1_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x03000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x06000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+
+/* ECSPI2_CLK_ROOT */
+#define ECSPI2_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x03000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x06000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+
+/* ECSPI3_CLK_ROOT */
+#define ECSPI3_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x03000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x06000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+
+/* ECSPI4_CLK_ROOT */
+#define ECSPI4_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK		0x04000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x01000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x03000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK			0x05000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK		0x06000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x02000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+
+/* PWM1_CLK_ROOT */
+#define PWM1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define PWM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
+#define PWM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
+#define PWM1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
+#define PWM1_CLK_ROOT_FROM_REF_1M_CLK				0x06000000
+#define PWM1_CLK_ROOT_FROM_EXT_CLK_1				0x05000000
+
+/* PWM2_CLK_ROOT */
+#define PWM2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define PWM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
+#define PWM2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
+#define PWM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
+#define PWM2_CLK_ROOT_FROM_REF_1M_CLK				0x06000000
+#define PWM2_CLK_ROOT_FROM_EXT_CLK_1				0x05000000
+
+/* PWM3_CLK_ROOT */
+#define PWM3_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define PWM3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
+#define PWM3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
+#define PWM3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
+#define PWM3_CLK_ROOT_FROM_REF_1M_CLK				0x06000000
+#define PWM3_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
+
+/* PWM4_CLK_ROOT */
+#define PWM4_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define PWM4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
+#define PWM4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x04000000
+#define PWM4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x07000000
+#define PWM4_CLK_ROOT_FROM_REF_1M_CLK				0x06000000
+#define PWM4_CLK_ROOT_FROM_EXT_CLK_2				0x05000000
+
+/* FLEXTIMER1_CLK_ROOT */
+#define FLEXTIMER1_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x04000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
+#define FLEXTIMER1_CLK_ROOT_FROM_REF_1M_CLK			0x06000000
+#define FLEXTIMER1_CLK_ROOT_FROM_EXT_CLK_3			0x05000000
+
+/* FLEXTIMER2_CLK_ROOT */
+#define FLEXTIMER2_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x04000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x07000000
+#define FLEXTIMER2_CLK_ROOT_FROM_REF_1M_CLK			0x06000000
+#define FLEXTIMER2_CLK_ROOT_FROM_EXT_CLK_3			0x05000000
+
+/* SIM1_CLK_ROOT */
+#define SIM1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define SIM1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define SIM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
+#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
+#define SIM1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
+#define SIM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x05000000
+#define SIM1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x04000000
+
+/* SIM2_CLK_ROOT */
+#define SIM2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define SIM2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define SIM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
+#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
+#define SIM2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x06000000
+#define SIM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x05000000
+#define SIM2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x04000000
+
+/* GPT1_CLK_ROOT */
+#define GPT1_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define GPT1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x02000000
+#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
+#define GPT1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
+#define GPT1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
+#define GPT1_CLK_ROOT_FROM_REF_1M_CLK				0x05000000
+#define GPT1_CLK_ROOT_FROM_EXT_CLK_1				0x07000000
+
+/* GPT2_CLK_ROOT */
+#define GPT2_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define GPT2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x02000000
+#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
+#define GPT2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
+#define GPT2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
+#define GPT2_CLK_ROOT_FROM_REF_1M_CLK				0x05000000
+#define GPT2_CLK_ROOT_FROM_EXT_CLK_2				0x07000000
+
+/* GPT3_CLK_ROOT */
+#define GPT3_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define GPT3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x02000000
+#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
+#define GPT3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
+#define GPT3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
+#define GPT3_CLK_ROOT_FROM_REF_1M_CLK				0x05000000
+#define GPT3_CLK_ROOT_FROM_EXT_CLK_3				0x07000000
+
+/* GPT4_CLK_ROOT */
+#define GPT4_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define GPT4_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK		0x02000000
+#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
+#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x03000000
+#define GPT4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK			0x06000000
+#define GPT4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK			0x04000000
+#define GPT4_CLK_ROOT_FROM_REF_1M_CLK				0x05000000
+#define GPT4_CLK_ROOT_FROM_EXT_CLK_4				0x07000000
+
+/* TRACE_CLK_ROOT */
+#define TRACE_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define TRACE_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define TRACE_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define TRACE_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
+#define TRACE_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x04000000
+#define TRACE_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x05000000
+#define TRACE_CLK_ROOT_FROM_EXT_CLK_1				0x06000000
+#define TRACE_CLK_ROOT_FROM_EXT_CLK_3				0x07000000
+
+/* WDOG_CLK_ROOT */
+#define WDOG_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define WDOG_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define WDOG_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD1_166M_CLK		0x07000000
+#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
+#define WDOG_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x04000000
+#define WDOG_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x05000000
+#define WDOG_CLK_ROOT_FROM_REF_1M_CLK				0x06000000
+
+/* CSI_MCLK_CLK_ROOT */
+#define CSI_MCLK_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x04000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+
+/* AUDIO_MCLK_CLK_ROOT */
+#define AUDIO_MCLK_CLK_ROOT_FROM_OSC_24M_CLK			0x00000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x03000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK		0x02000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK		0x01000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x04000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK		0x05000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK		0x06000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x07000000
+
+/* WRCLK_CLK_ROOT */
+#define WRCLK_CLK_ROOT_FROM_OSC_24M_CLK				0x00000000
+#define WRCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK		0x02000000
+#define WRCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK		0x04000000
+#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK		0x05000000
+#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK			0x07000000
+#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK		0x06000000
+#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK		0x01000000
+#define WRCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK		0x03000000
+
+/* IPP_DO_CLKO1 */
+#define IPP_DO_CLKO1_FROM_OSC_24M_CLK				0x00000000
+#define IPP_DO_CLKO1_FROM_PLL_DRAM_MAIN_533M_CLK		0x06000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_480M_CLK			0x01000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_240M_CLK			0x02000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD0_196M_CLK			0x03000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD3_CLK			0x04000000
+#define IPP_DO_CLKO1_FROM_PLL_ENET_MAIN_500M_CLK		0x05000000
+#define IPP_DO_CLKO1_FROM_REF_1M_CLK				0x07000000
+
+/* IPP_DO_CLKO2 */
+#define IPP_DO_CLKO2_FROM_OSC_24M_CLK				0x00000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_MAIN_240M_CLK			0x01000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD0_392M_CLK			0x02000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD1_166M_CLK			0x03000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD4_CLK			0x04000000
+#define IPP_DO_CLKO2_FROM_PLL_AUDIO_MAIN_CLK			0x05000000
+#define IPP_DO_CLKO2_FROM_PLL_VIDEO_MAIN_CLK			0x06000000
+#define IPP_DO_CLKO2_FROM_OSC_32K_CLK				0x07000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx7/gpio.h b/arch/arm/include/asm/arch-mx7/gpio.h
new file mode 100644
index 0000000..1da66a4
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_MX7_GPIO_H
+#define __ASM_ARCH_MX7_GPIO_H
+
+#include <asm/mach-imx/gpio.h>
+
+#endif /* __ASM_ARCH_MX7_GPIO_H */
diff --git a/arch/arm/include/asm/arch-mx7/imx-rdc.h b/arch/arm/include/asm/arch-mx7/imx-rdc.h
new file mode 100644
index 0000000..3512ddb
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/imx-rdc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __IMX_RDC_H__
+#define __IMX_RDC_H__
+
+#if defined(CONFIG_MX7D)
+#include "mx7d_rdc.h"
+#else
+#error "Please select cpu"
+#endif	/* CONFIG_MX7D */
+
+#endif	/* __IMX_RDC_H__*/
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
new file mode 100644
index 0000000..6336514
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -0,0 +1,1227 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __ASM_ARCH_MX7_IMX_REGS_H__
+#define __ASM_ARCH_MX7_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define ROM_SW_INFO_ADDR                0x000001E8
+#define ROMCP_ARB_BASE_ADDR             0x00000000
+#define ROMCP_ARB_END_ADDR              0x00017FFF
+#define BOOT_ROM_BASE_ADDR              ROMCP_ARB_BASE_ADDR
+#define CAAM_ARB_BASE_ADDR              0x00100000
+#define CAAM_ARB_END_ADDR               0x00107FFF
+#define GIC400_ARB_BASE_ADDR            0x31000000
+#define GIC400_ARB_END_ADDR             0x31007FFF
+#define APBH_DMA_ARB_BASE_ADDR          0x33000000
+#define APBH_DMA_ARB_END_ADDR           0x33007FFF
+#define M4_BOOTROM_BASE_ADDR            0x00180000
+
+#define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
+/* GPV - PL301 configuration ports */
+#define GPV0_BASE_ADDR                  0x32000000
+#define GPV1_BASE_ADDR                  0x32100000
+#define GPV2_BASE_ADDR                  0x32200000
+#define GPV3_BASE_ADDR                  0x32300000
+#define GPV4_BASE_ADDR                  0x32400000
+#define GPV5_BASE_ADDR                  0x32500000
+#define GPV6_BASE_ADDR                  0x32600000
+#define GPV7_BASE_ADDR                  0x32700000
+
+#define OCRAM_ARB_BASE_ADDR             0x00900000
+#define OCRAM_ARB_END_ADDR              0x0091FFFF
+#define OCRAM_EPDC_BASE_ADDR            0x00920000
+#define OCRAM_EPDC_END_ADDR             0x0093FFFF
+#define OCRAM_PXP_BASE_ADDR             0x00940000
+#define OCRAM_PXP_END_ADDR              0x00947FFF
+#define IRAM_BASE_ADDR                  OCRAM_ARB_BASE_ADDR
+#define IRAM_SIZE			0x00020000
+
+#define AIPS1_ARB_BASE_ADDR             0x30000000
+#define AIPS1_ARB_END_ADDR              0x303FFFFF
+#define AIPS2_ARB_BASE_ADDR             0x30400000
+#define AIPS2_ARB_END_ADDR              0x307FFFFF
+#define AIPS3_ARB_BASE_ADDR             0x30800000
+#define AIPS3_ARB_END_ADDR              0x30BFFFFF
+
+#define WEIM_ARB_BASE_ADDR              0x28000000
+#define WEIM_ARB_END_ADDR               0x2FFFFFFF
+
+#define QSPI0_ARB_BASE_ADDR             0x60000000
+#define QSPI0_ARB_END_ADDR              0x6FFFFFFF
+#define PCIE_ARB_BASE_ADDR              0x40000000
+#define PCIE_ARB_END_ADDR               0x4FFFFFFF
+#define PCIE_REG_BASE_ADDR              0x33800000
+#define PCIE_REG_END_ADDR               0x33803FFF
+
+#define MMDC0_ARB_BASE_ADDR             0x80000000
+#define MMDC0_ARB_END_ADDR              0xBFFFFFFF
+#define MMDC1_ARB_BASE_ADDR             0xC0000000
+#define MMDC1_ARB_END_ADDR              0xFFFFFFFF
+
+/* Cortex-A9 MPCore private memory region */
+#define ARM_PERIPHBASE                  0x31000000
+#define SCU_BASE_ADDR                   ARM_PERIPHBASE
+#define GLOBAL_TIMER_BASE_ADDR          (ARM_PERIPHBASE + 0x0200)
+#define PRIVATE_TIMERS_WD_BASE_ADDR     (ARM_PERIPHBASE + 0x0600)
+
+
+/* Defines for Blocks connected via AIPS (SkyBlue) */
+#define AIPS_TZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
+#define AIPS_TZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
+#define AIPS_TZ3_BASE_ADDR              AIPS3_ARB_BASE_ADDR
+
+/* DAP base-address */
+#define ARM_IPS_BASE_ADDR               AIPS1_ARB_BASE_ADDR
+
+/* AIPS_TZ#1- On Platform */
+#define AIPS1_ON_BASE_ADDR              (AIPS_TZ1_BASE_ADDR+0x1F0000)
+/* AIPS_TZ#1- Off Platform */
+#define AIPS1_OFF_BASE_ADDR             (AIPS_TZ1_BASE_ADDR+0x200000)
+
+#define GPIO1_BASE_ADDR                 AIPS1_OFF_BASE_ADDR
+#define GPIO2_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x10000)
+#define GPIO3_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x20000)
+#define GPIO4_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x30000)
+#define GPIO5_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x40000)
+#define GPIO6_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x50000)
+#define GPIO7_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x60000)
+#define IOMUXC_LPSR_GPR_BASE_ADDR      (AIPS1_OFF_BASE_ADDR+0x70000)
+#define WDOG1_BASE_ADDR                (AIPS1_OFF_BASE_ADDR+0x80000)
+#define WDOG2_BASE_ADDR                (AIPS1_OFF_BASE_ADDR+0x90000)
+#define WDOG3_BASE_ADDR                (AIPS1_OFF_BASE_ADDR+0xA0000)
+#define WDOG4_BASE_ADDR                (AIPS1_OFF_BASE_ADDR+0xB0000)
+#define IOMUXC_LPSR_BASE_ADDR          (AIPS1_OFF_BASE_ADDR+0xC0000)
+#define GPT_IPS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR+0xD0000)
+#define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR
+#define GPT2_IPS_BASE_ADDR             (AIPS1_OFF_BASE_ADDR+0xE0000)
+#define GPT3_IPS_BASE_ADDR             (AIPS1_OFF_BASE_ADDR+0xF0000)
+#define GPT4_IPS_BASE_ADDR             (AIPS1_OFF_BASE_ADDR+0x100000)
+#define ROMCP_IPS_BASE_ADDR            (AIPS1_OFF_BASE_ADDR+0x110000)
+#define KPP_IPS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR+0x120000)
+#define IOMUXC_IPS_BASE_ADDR           (AIPS1_OFF_BASE_ADDR+0x130000)
+#define IOMUXC_BASE_ADDR               IOMUXC_IPS_BASE_ADDR
+#define IOMUXC_GPR_BASE_ADDR           (AIPS1_OFF_BASE_ADDR+0x140000)
+#define OCOTP_BASE_ADDR                (AIPS1_OFF_BASE_ADDR+0x150000)
+#define ANATOP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR+0x160000)
+#define SNVS_BASE_ADDR                 (AIPS1_OFF_BASE_ADDR+0x170000)
+#define CCM_BASE_ADDR                  (AIPS1_OFF_BASE_ADDR+0x180000)
+#define SRC_BASE_ADDR                  (AIPS1_OFF_BASE_ADDR+0x190000)
+#define GPC_IPS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR+0x1A0000)
+#define SEMA41_IPS_BASE_ADDR           (AIPS1_OFF_BASE_ADDR+0x1B0000)
+#define SEMA42_IPS_BASE_ADDR           (AIPS1_OFF_BASE_ADDR+0x1C0000)
+#define RDC_IPS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR+0x1D0000)
+#define CSU_IPS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR+0x1E0000)
+
+/* AIPS_TZ#2- On Platform */
+#define AIPS2_ON_BASE_ADDR              (AIPS_TZ2_BASE_ADDR+0x1F0000)
+/* AIPS_TZ#2- Off Platform */
+#define AIPS2_OFF_BASE_ADDR             (AIPS_TZ2_BASE_ADDR+0x200000)
+#define ADC1_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x10000)
+#define ADC2_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x20000)
+#define ECSPI4_BASE_ADDR                (AIPS2_OFF_BASE_ADDR+0x30000)
+#define FTM1_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x40000)
+#define FTM2_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x50000)
+#define PWM1_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x60000)
+#define PWM2_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x70000)
+#define PWM3_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x80000)
+#define PWM4_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x90000)
+#define SYSCNT_RD_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR+0xA0000)
+#define SYSCNT_CMP_IPS_BASE_ADDR        (AIPS2_OFF_BASE_ADDR+0xB0000)
+#define SYSCNT_CTRL_IPS_BASE_ADDR       (AIPS2_OFF_BASE_ADDR+0xC0000)
+#define PCIE_PHY_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR+0xD0000)
+#define EPDC_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0xF0000)
+#define EPDC_BASE_ADDR                  EPDC_IPS_BASE_ADDR
+#define EPXP_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x100000)
+#define CSI1_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x110000)
+#define ELCDIF1_IPS_BASE_ADDR           (AIPS2_OFF_BASE_ADDR+0x130000)
+#define MIPI_CSI2_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR+0x150000)
+#define MIPI_DSI_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR+0x160000)
+#define IP2APB_TZASC1_IPS_BASE_ADDR     (AIPS2_OFF_BASE_ADDR+0x180000)
+#define DDRPHY_IPS_BASE_ADDR            (AIPS2_OFF_BASE_ADDR+0x190000)
+#define DDRC_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x1A0000)
+#define IP2APB_PERFMON1_IPS_BASE_ADDR   (AIPS2_OFF_BASE_ADDR+0x1C0000)
+#define IP2APB_PERFMON2_IPS_BASE_ADDR   (AIPS2_OFF_BASE_ADDR+0x1D0000)
+#define IP2APB_AXIMON_IPS_BASE_ADDR     (AIPS2_OFF_BASE_ADDR+0x1E0000)
+#define QOSC_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x1F0000)
+
+/* AIPS_TZ#3  - Global enable (0) */
+#define ECSPI1_BASE_ADDR                (AIPS_TZ3_BASE_ADDR+0x20000)
+#define ECSPI2_BASE_ADDR                (AIPS_TZ3_BASE_ADDR+0x30000)
+#define ECSPI3_BASE_ADDR                (AIPS_TZ3_BASE_ADDR+0x40000)
+#define UART1_IPS_BASE_ADDR             (AIPS_TZ3_BASE_ADDR+0x60000)
+#define UART3_IPS_BASE_ADDR             (AIPS_TZ3_BASE_ADDR+0x80000)
+#define UART2_IPS_BASE_ADDR             (AIPS_TZ3_BASE_ADDR+0x90000)
+#define SAI1_IPS_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0xA0000)
+#define SAI2_IPS_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0xB0000)
+#define SAI3_IPS_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0xC0000)
+#define SPBA_IPS_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0xF0000)
+#define CAAM_IPS_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0x100000)
+
+/* AIPS_TZ#3- On Platform */
+#define AIPS3_ON_BASE_ADDR              (AIPS_TZ3_BASE_ADDR+0x1F0000)
+/* AIPS_TZ#3- Off Platform */
+#define AIPS3_OFF_BASE_ADDR             (AIPS_TZ3_BASE_ADDR+0x200000)
+#define CAN1_IPS_BASE_ADDR              AIPS3_OFF_BASE_ADDR
+#define CAN2_IPS_BASE_ADDR              (AIPS3_OFF_BASE_ADDR+0x10000)
+#define I2C1_BASE_ADDR                  (AIPS3_OFF_BASE_ADDR+0x20000)
+#define I2C2_BASE_ADDR                  (AIPS3_OFF_BASE_ADDR+0x30000)
+#define I2C3_BASE_ADDR                  (AIPS3_OFF_BASE_ADDR+0x40000)
+#define I2C4_BASE_ADDR                  (AIPS3_OFF_BASE_ADDR+0x50000)
+#define UART4_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x60000)
+#define UART5_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x70000)
+#define UART6_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x80000)
+#define UART7_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x90000)
+#define MUCPU_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0xA0000)
+#define MUDSP_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0xB0000)
+#define HS_IPS_BASE_ADDR                (AIPS3_OFF_BASE_ADDR+0xC0000)
+#define USBOH2_PL301_IPS_BASE_ADDR      (AIPS3_OFF_BASE_ADDR+0xD0000)
+#define USBOTG1_IPS_BASE_ADDR		(AIPS3_OFF_BASE_ADDR+0x110000)
+#define USBOTG2_IPS_BASE_ADDR		(AIPS3_OFF_BASE_ADDR+0x120000)
+#define USBHSIC_IPS_BASE_ADDR		(AIPS3_OFF_BASE_ADDR+0x130000)
+#define USDHC1_BASE_ADDR                (AIPS3_OFF_BASE_ADDR+0x140000)
+#define USDHC2_BASE_ADDR                (AIPS3_OFF_BASE_ADDR+0x150000)
+#define USDHC3_BASE_ADDR                (AIPS3_OFF_BASE_ADDR+0x160000)
+#define EMVSIM1_IPS_BASE_ADDR           (AIPS3_OFF_BASE_ADDR+0x190000)
+#define EMVSIM2_IPS_BASE_ADDR           (AIPS3_OFF_BASE_ADDR+0x1A0000)
+#define SIM1_IPS_BASE_ADDR              (AIPS3_OFF_BASE_ADDR+0x190000)
+#define SIM2_IPS_BASE_ADDR              (AIPS3_OFF_BASE_ADDR+0x1A0000)
+#define QSPI1_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x1B0000)
+#define WEIM_IPS_BASE_ADDR              (AIPS3_OFF_BASE_ADDR+0x1C0000)
+#define SDMA_PORT_IPS_HOST_BASE_ADDR    (AIPS3_OFF_BASE_ADDR+0x1D0000)
+#define ENET_IPS_BASE_ADDR              (AIPS3_OFF_BASE_ADDR+0x1E0000)
+#define ENET2_IPS_BASE_ADDR             (AIPS3_OFF_BASE_ADDR+0x1F0000)
+
+#define AIPS1_BASE_ADDR			AIPS1_ON_BASE_ADDR
+#define AIPS2_BASE_ADDR			AIPS2_ON_BASE_ADDR
+#define AIPS3_BASE_ADDR			AIPS3_ON_BASE_ADDR
+
+#define SDMA_IPS_HOST_BASE_ADDR         SDMA_PORT_IPS_HOST_BASE_ADDR
+#define SDMA_IPS_HOST_IPS_BASE_ADDR     SDMA_PORT_IPS_HOST_BASE_ADDR
+
+#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR
+#define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR
+
+#define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR
+#define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR
+#define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR
+#define RDC_BASE_ADDR RDC_IPS_BASE_ADDR
+
+#define FEC_QUIRK_ENET_MAC
+#define SNVS_LPGPR	0x68
+#define CONFIG_SYS_FSL_SEC_OFFSET       0
+#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
+					 CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET       0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
+					 CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/mach-imx/regs-lcdif.h>
+#include <asm/types.h>
+
+extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32	scr;
+	u32 a7rcr0;
+	u32 a7rcr1;
+	u32 m4rcr;
+	u32 reserved1;
+	u32 ercr;
+	u32 reserved2;
+	u32 hsicphy_rcr;
+	u32 usbophy1_rcr;
+	u32 usbophy2_rcr;
+	u32 mipiphy_rcr;
+	u32 pciephy_rcr;
+	u32 reserved3[10];
+	u32	sbmr1;
+	u32	srsr;
+	u32	reserved4[2];
+	u32	sisr;
+	u32	simr;
+	u32 sbmr2;
+	u32 gpr1;
+	u32 gpr2;
+	u32 gpr3;
+	u32 gpr4;
+	u32 gpr5;
+	u32 gpr6;
+	u32 gpr7;
+	u32 gpr8;
+	u32 gpr9;
+	u32 gpr10;
+	u32 reserved5[985];
+	u32 ddrc_rcr;
+};
+
+#define src_base ((struct src *)SRC_BASE_ADDR)
+
+#define SRC_M4_REG_OFFSET		0xC
+#define SRC_M4C_NON_SCLR_RST_OFFSET	0
+#define SRC_M4C_NON_SCLR_RST_MASK	BIT(0)
+#define SRC_M4_ENABLE_OFFSET		3
+#define SRC_M4_ENABLE_MASK		BIT(3)
+
+#define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET	1
+#define SRC_DDRC_RCR_DDRC_CORE_RST_MASK		(1 << 1)
+
+/* GPR0 Bit Fields */
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK     0x1u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT    0
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK     0x2u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT    1
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK     0x4u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT    2
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK     0x8u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT    3
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK     0x10u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT    4
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK     0x20u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT    5
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK     0x40u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT    6
+#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7)
+#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7
+/* GPR1 Bit Fields */
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK    0x1u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT   0
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK     0x6u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT    1
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK)
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK    0x8u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT   3
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK     0x30u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT    4
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK)
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK    0x40u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT   6
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK     0x180u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT    7
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK)
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK    0x200u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT   9
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK     0xC00u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT    10
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK)
+#define IOMUXC_GPR_GPR1_GPR_IRQ_MASK             0x1000u
+#define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT            12
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13
+#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u
+#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14
+#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u
+#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15
+#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK      0x10000u
+#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT     16
+#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK   0x20000u
+#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT  17
+#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK   0x40000u
+#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT  18
+#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u
+#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22
+#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u
+#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23
+#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK         0x30000000u
+#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT        28
+#define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK)
+#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u
+#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30
+/* GPR2 Bit Fields */
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK      0x2u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT     1
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK      0x4u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT     2
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK      0x8u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT     3
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK    0x20u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT   5
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK    0x40u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT   6
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK    0x80u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT   7
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK     0x200u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT    9
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK     0x400u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT    10
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK     0x800u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT    11
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK      0x2000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT     13
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK      0x4000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT     14
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK      0x8000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT     15
+#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK     0xFF0000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT    16
+#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK)
+#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK      0x1000000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT     24
+#define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK          0x2000000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT         25
+#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK  0x4000000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK      0x10000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT     28
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK       0x20000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT      29
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK       0x40000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT      30
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31
+/* GPR3 Bit Fields */
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31
+/* GPR4 Bit Fields */
+#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK   0x1u
+#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT  0
+#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK   0x2u
+#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT  1
+#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK   0x4u
+#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT  2
+#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK  0x8u
+#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3
+#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK  0x10u
+#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4
+#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK   0x20u
+#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT  5
+#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK   0x40u
+#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT  6
+#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK   0x80u
+#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT  7
+#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK   0x10000u
+#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT  16
+#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK   0x20000u
+#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT  17
+#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK   0x40000u
+#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT  18
+#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK  0x80000u
+#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19
+#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK  0x100000u
+#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20
+#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK   0x200000u
+#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT  21
+#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK   0x400000u
+#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT  22
+#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK   0x800000u
+#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT  23
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK      0x6000000u
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT     25
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK)
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK      0x18000000u
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT     27
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK)
+/* GPR5 Bit Fields */
+#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u
+#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4
+#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u
+#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5
+#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK      0x40u
+#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT     6
+#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK      0x80u
+#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT     7
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12
+#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK     0x80000u
+#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT    19
+#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK      0x100000u
+#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT     20
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21
+#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK      0x400000u
+#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT     22
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25
+#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u
+#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26
+#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u
+#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31
+/* GPR6 Bit Fields */
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK    0x1u
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT   0
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK    0x2u
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT   1
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3
+/* GPR7 Bit Fields */
+#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u
+#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0
+#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u
+#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3
+#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u
+#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4
+#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK)
+#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u
+#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6
+#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u
+#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9
+#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u
+#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10
+#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK)
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13
+/* GPR8 Bit Fields */
+#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u
+#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3
+#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x)  (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK)
+#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u
+#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8
+/* GPR9 Bit Fields */
+#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u
+#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0
+#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK     0x3Eu
+#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT    1
+#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK)
+/* GPR10 Bit Fields */
+#define IOMUXC_GPR_GPR10_GPR0_BF0_MASK           0x1u
+#define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT          0
+#define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK         0x2u
+#define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT        1
+#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u
+#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK)
+/* GPR11 Bit Fields */
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK)
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK)
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK)
+/* GPR12 Bit Fields */
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK)
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK)
+/* GPR13 Bit Fields */
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK  0x1u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK  0x2u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK    0x4u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT   2
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK    0x8u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT   3
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK   0x10u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT  4
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK   0x20u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT  5
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK  0x40u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK   0x80u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT  7
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK   0x4000u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT  14
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK)
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK)
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31
+/* GPR14 Bit Fields */
+#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u
+#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0
+#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u
+#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1
+/* GPR15 Bit Fields */
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK)
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK)
+/* GPR16 Bit Fields */
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK   0x20u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT  5
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK   0x3C0u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT  6
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10
+#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK  0x800u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11
+#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK    0x1000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT   12
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK   0xE000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT  13
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x)     (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK   0x10000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT  16
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK   0x400000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT  22
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23
+/* GPR17 Bit Fields */
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK)
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x)   (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK)
+/* GPR18 Bit Fields */
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27
+#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK  0x10000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28
+#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29
+/* GPR19 Bit Fields */
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK)
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16
+#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17
+/* GPR20 Bit Fields */
+#define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK         0x3Fu
+#define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT        0
+#define IOMUXC_GPR_GPR20_GPR_LVDS_P(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK)
+#define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK         0x3F00u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT        8
+#define IOMUXC_GPR_GPR20_GPR_LVDS_M(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK)
+#define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK         0x30000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT        16
+#define IOMUXC_GPR_GPR20_GPR_LVDS_S(x)           (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK)
+#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK      0x1000000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT     24
+#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25
+#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27
+#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK)
+/* GPR21 Bit Fields */
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK      0x7u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT     0
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK      0x38u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT     3
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK      0x1C0u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT     6
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK     0xE00u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT    9
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x)       (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK      0x7000u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT     12
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK      0x38000u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT     15
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x)        (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK)
+#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK  0x40000u
+#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18
+#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK  0x80000u
+#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19
+/* GPR22 Bit Fields */
+#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK  0xFF0000u
+#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16
+#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x)    (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK)
+#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u
+#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24
+#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u
+#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25
+#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u
+#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26
+#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u
+#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27
+#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u
+#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28
+#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u
+#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29
+#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u
+#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31
+
+#define IMX7D_GPR5_CSI1_MUX_CTRL_MASK			(0x1 << 4)
+#define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI		(0x0 << 4)
+#define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI		(0x1 << 4)
+
+struct iomuxc {
+	u32 gpr[23];
+	/* mux and pad registers */
+};
+
+struct iomuxc_gpr_base_regs {
+	u32 gpr[23];        /* 0x000 */
+};
+
+/* ECSPI registers */
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 cfg;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x)	(((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)	(((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)	(((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN	18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA		0  /* SCLK phase control */
+#define MXC_CSPICON_POL		4  /* SCLK polarity */
+#define MXC_CSPICON_SSPOL	12 /* SS polarity */
+#define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
+
+#define MXC_SPI_BASE_ADDRESSES \
+	ECSPI1_BASE_ADDR, \
+	ECSPI2_BASE_ADDR, \
+	ECSPI3_BASE_ADDR, \
+	ECSPI4_BASE_ADDR
+
+#define CSU_INIT_SEC_LEVEL0	0x00FF00FF
+#define CSU_NUM_REGS		64
+
+struct ocotp_regs {
+	u32 ctrl;
+	u32 ctrl_set;
+	u32 ctrl_clr;
+	u32 ctrl_tog;
+	u32 timing;
+	u32 rsvd0[3];
+	u32 data0;
+	u32 rsvd1[3];
+	u32 data1;
+	u32 rsvd2[3];
+	u32 data2;
+	u32 rsvd3[3];
+	u32 data3;
+	u32 rsvd4[3];
+	u32 read_ctrl;
+	u32 rsvd5[3];
+	u32 read_fuse_data0;
+	u32 rsvd6[3];
+	u32 read_fuse_data1;
+	u32 rsvd7[3];
+	u32 read_fuse_data2;
+	u32 rsvd8[3];
+	u32 read_fuse_data3;
+	u32 rsvd9[3];
+	u32 sw_sticky;
+	u32 rsvd10[3];
+	u32 scs;
+	u32 scs_set;
+	u32 scs_clr;
+	u32 scs_tog;
+	u32 crc_addr;
+	u32 rsvd11[3];
+	u32 crc_value;
+	u32 rsvd12[3];
+	u32 version;
+	u32 rsvd13[0xc3];
+
+	struct fuse_bank {	/* offset 0x400 */
+		u32 fuse_regs[0x10];
+	} bank[16];
+};
+
+struct fuse_bank0_regs {
+	u32 lock;
+	u32 rsvd0[3];
+	u32 tester0;
+	u32 rsvd1[3];
+	u32 tester1;
+	u32 rsvd2[3];
+	u32 tester2;
+	u32 rsvd3[3];
+};
+
+struct fuse_bank1_regs {
+	u32 tester3;
+	u32 rsvd0[3];
+	u32 tester4;
+	u32 rsvd1[3];
+	u32 tester5;
+	u32 rsvd2[3];
+	u32 cfg0;
+	u32 rsvd3[3];
+};
+
+struct fuse_bank2_regs {
+	u32 cfg1;
+	u32 rsvd0[3];
+	u32 cfg2;
+	u32 rsvd1[3];
+	u32 cfg3;
+	u32 rsvd2[3];
+	u32 cfg4;
+	u32 rsvd3[3];
+};
+
+struct fuse_bank3_regs {
+	u32 mem_trim0;
+	u32 rsvd0[3];
+	u32 mem_trim1;
+	u32 rsvd1[3];
+	u32 ana0;
+	u32 rsvd2[3];
+	u32 ana1;
+	u32 rsvd3[3];
+};
+
+struct fuse_bank8_regs {
+	u32 sjc_resp_low;
+	u32 rsvd0[3];
+	u32 sjc_resp_high;
+	u32 rsvd1[3];
+	u32 usb_id;
+	u32 rsvd2[3];
+	u32 field_return;
+	u32 rsvd3[3];
+};
+
+struct fuse_bank9_regs {
+	u32 mac_addr0;
+	u32 rsvd0[3];
+	u32 mac_addr1;
+	u32 rsvd1[3];
+	u32 mac_addr2;
+	u32 rsvd2[7];
+};
+
+struct aipstz_regs {
+	u32	mprot0;
+	u32	mprot1;
+	u32	rsvd[0xe];
+	u32	opacr0;
+	u32	opacr1;
+	u32	opacr2;
+	u32	opacr3;
+	u32	opacr4;
+};
+
+struct wdog_regs {
+	u16	wcr;	/* Control */
+	u16	wsr;	/* Service */
+	u16	wrsr;	/* Reset Status */
+	u16	wicr;	/* Interrupt Control */
+	u16	wmcr;	/* Miscellaneous Control */
+};
+
+struct dbg_monitor_regs {
+	u32	ctrl[4];		/* Control */
+	u32	master_en[4];		/* Master enable */
+	u32	irq[4];			/* IRQ */
+	u32	trap_addr_low[4];	/* Trap address low */
+	u32	trap_addr_high[4];	/* Trap address high */
+	u32	trap_id[4];		/* Trap ID */
+	u32	snvs_addr[4];		/* SNVS address */
+	u32	snvs_data[4];		/* SNVS data */
+	u32	snvs_info[4];		/* SNVS info */
+	u32	version[4];		/* Version */
+};
+
+struct rdc_regs {
+	u32	vir;		/* Version information */
+	u32	reserved1[8];
+	u32	stat;		/* Status */
+	u32	intctrl;	/* Interrupt and Control */
+	u32	intstat;	/* Interrupt Status */
+	u32	reserved2[116];
+	u32	mda[27];		/* Master Domain Assignment */
+	u32	reserved3[101];
+	u32	pdap[118];		/* Peripheral Domain Access Permissions */
+	u32	reserved4[138];
+	struct {
+		u32 mrsa;		/* Memory Region Start Address */
+		u32 mrea;		/* Memory Region End Address */
+		u32 mrc;		/* Memory Region Control */
+		u32 mrvs;		/* Memory Region Violation Status */
+	} mem_region[52];
+};
+
+struct rdc_sema_regs {
+	u8	gate[64];	/* Gate */
+	u16	rstgt;		/* Reset Gate */
+};
+
+#define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR
+
+#define	LCDIF_CTRL_SFTRST					(1 << 31)
+#define	LCDIF_CTRL_CLKGATE					(1 << 30)
+#define	LCDIF_CTRL_YCBCR422_INPUT				(1 << 29)
+#define	LCDIF_CTRL_READ_WRITEB					(1 << 28)
+#define	LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE				(1 << 27)
+#define	LCDIF_CTRL_DATA_SHIFT_DIR				(1 << 26)
+#define	LCDIF_CTRL_SHIFT_NUM_BITS_MASK				(0x1f << 21)
+#define	LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET			21
+#define	LCDIF_CTRL_DVI_MODE					(1 << 20)
+#define	LCDIF_CTRL_BYPASS_COUNT					(1 << 19)
+#define	LCDIF_CTRL_VSYNC_MODE					(1 << 18)
+#define	LCDIF_CTRL_DOTCLK_MODE					(1 << 17)
+#define	LCDIF_CTRL_DATA_SELECT					(1 << 16)
+#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK			(0x3 << 14)
+#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET			14
+#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK			(0x3 << 12)
+#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET			12
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK			(0x3 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET			10
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT			(0 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT			(1 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT			(2 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT			(3 << 10)
+#define	LCDIF_CTRL_WORD_LENGTH_MASK				(0x3 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_OFFSET				8
+#define	LCDIF_CTRL_WORD_LENGTH_16BIT				(0 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_8BIT				(1 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_18BIT				(2 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_24BIT				(3 << 8)
+#define	LCDIF_CTRL_RGB_TO_YCBCR422_CSC				(1 << 7)
+#define	LCDIF_CTRL_LCDIF_MASTER					(1 << 5)
+#define	LCDIF_CTRL_DATA_FORMAT_16_BIT				(1 << 3)
+#define	LCDIF_CTRL_DATA_FORMAT_18_BIT				(1 << 2)
+#define	LCDIF_CTRL_DATA_FORMAT_24_BIT				(1 << 1)
+#define	LCDIF_CTRL_RUN						(1 << 0)
+
+#define	LCDIF_CTRL1_COMBINE_MPU_WR_STRB				(1 << 27)
+#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN				(1 << 26)
+#define	LCDIF_CTRL1_BM_ERROR_IRQ				(1 << 25)
+#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW			(1 << 24)
+#define	LCDIF_CTRL1_INTERLACE_FIELDS				(1 << 23)
+#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD		(1 << 22)
+#define	LCDIF_CTRL1_FIFO_CLEAR					(1 << 21)
+#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS			(1 << 20)
+#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK			(0xf << 16)
+#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET			16
+#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN				(1 << 15)
+#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN				(1 << 14)
+#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN			(1 << 13)
+#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN				(1 << 12)
+#define	LCDIF_CTRL1_OVERFLOW_IRQ				(1 << 11)
+#define	LCDIF_CTRL1_UNDERFLOW_IRQ				(1 << 10)
+#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ				(1 << 9)
+#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ				(1 << 8)
+#define	LCDIF_CTRL1_BUSY_ENABLE					(1 << 2)
+#define	LCDIF_CTRL1_MODE86					(1 << 1)
+#define	LCDIF_CTRL1_RESET					(1 << 0)
+
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_MASK			(0x7 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET			21
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1			(0x0 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2			(0x1 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4			(0x2 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8			(0x3 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16			(0x4 << 21)
+#define	LCDIF_CTRL2_BURST_LEN_8					(1 << 20)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_MASK			(0x7 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET			16
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_RGB			(0x0 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_RBG			(0x1 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_GBR			(0x2 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_GRB			(0x3 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_BRG			(0x4 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_BGR			(0x5 << 16)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK			(0x7 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET			12
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB			(0x0 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG			(0x1 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR			(0x2 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB			(0x3 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG			(0x4 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR			(0x5 << 12)
+#define	LCDIF_CTRL2_READ_PACK_DIR				(1 << 10)
+#define	LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT		(1 << 9)
+#define	LCDIF_CTRL2_READ_MODE_6_BIT_INPUT			(1 << 8)
+#define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK		(0x7 << 4)
+#define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET	4
+#define	LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK			(0x7 << 1)
+#define	LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET			1
+
+#define	LCDIF_TRANSFER_COUNT_V_COUNT_MASK			(0xffff << 16)
+#define	LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET			16
+#define	LCDIF_TRANSFER_COUNT_H_COUNT_MASK			(0xffff << 0)
+#define	LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET			0
+
+#define	LCDIF_CUR_BUF_ADDR_MASK					0xffffffff
+#define	LCDIF_CUR_BUF_ADDR_OFFSET				0
+
+#define	LCDIF_NEXT_BUF_ADDR_MASK				0xffffffff
+#define	LCDIF_NEXT_BUF_ADDR_OFFSET				0
+
+#define	LCDIF_TIMING_CMD_HOLD_MASK				(0xff << 24)
+#define	LCDIF_TIMING_CMD_HOLD_OFFSET				24
+#define	LCDIF_TIMING_CMD_SETUP_MASK				(0xff << 16)
+#define	LCDIF_TIMING_CMD_SETUP_OFFSET				16
+#define	LCDIF_TIMING_DATA_HOLD_MASK				(0xff << 8)
+#define	LCDIF_TIMING_DATA_HOLD_OFFSET				8
+#define	LCDIF_TIMING_DATA_SETUP_MASK				(0xff << 0)
+#define	LCDIF_TIMING_DATA_SETUP_OFFSET				0
+
+#define	LCDIF_VDCTRL0_VSYNC_OEB					(1 << 29)
+#define	LCDIF_VDCTRL0_ENABLE_PRESENT				(1 << 28)
+#define	LCDIF_VDCTRL0_VSYNC_POL					(1 << 27)
+#define	LCDIF_VDCTRL0_HSYNC_POL					(1 << 26)
+#define	LCDIF_VDCTRL0_DOTCLK_POL				(1 << 25)
+#define	LCDIF_VDCTRL0_ENABLE_POL				(1 << 24)
+#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT				(1 << 21)
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT			(1 << 20)
+#define	LCDIF_VDCTRL0_HALF_LINE					(1 << 19)
+#define	LCDIF_VDCTRL0_HALF_LINE_MODE				(1 << 18)
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK			0x3ffff
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET			0
+
+#define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK				0xffffffff
+#define	LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET			0
+
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0x3fff << 18)
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			18
+#define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK				0x3ffff
+#define	LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET			0
+
+#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS				(1 << 29)
+#define	LCDIF_VDCTRL3_VSYNC_ONLY				(1 << 28)
+#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK			(0xfff << 16)
+#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET		16
+#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK			(0xffff << 0)
+#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET			0
+
+#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK			(0x7 << 29)
+#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET			29
+#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON				(1 << 18)
+#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK		0x3ffff
+#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET		0
+
+
+extern void check_cpu_temperature(void);
+
+extern void pcie_power_up(void);
+extern void pcie_power_off(void);
+
+/* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
+ * If boot from the other mode, USB0_PWD will keep reset value
+ */
+#define	is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \
+	readl(USBOTG2_IPS_BASE_ADDR + 0x158))
+#define	disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)
+
+struct bootrom_sw_info {
+	u8 reserved_1;
+	u8 boot_dev_instance;
+	u8 boot_dev_type;
+	u8 reserved_2;
+	u32 arm_core_freq;
+	u32 axi_freq;
+	u32 ddr_freq;
+	u32 gpt1_freq;
+	u32 reserved_3[3];
+};
+
+#endif /* __ASSEMBLER__*/
+#endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx7/mx7-ddr.h b/arch/arm/include/asm/arch-mx7/mx7-ddr.h
new file mode 100644
index 0000000..3c07904
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/mx7-ddr.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * DDR controller registers of the i.MX7 architecture
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ */
+
+#ifndef __ASM_ARCH_MX7_DDR_H__
+#define __ASM_ARCH_MX7_DDR_H__
+
+/* DDRC Registers (DDRC_IPS_BASE_ADDR) */
+struct ddrc {
+	u32 mstr;		/* 0x0000 */
+	u32 reserved1[0x18];
+	u32 rfshtmg;		/* 0x0064 */
+	u32 reserved2[0x1a];
+	u32 init0;		/* 0x00d0 */
+	u32 init1;		/* 0x00d4 */
+	u32 reserved3;
+	u32 init3;		/* 0x00dc */
+	u32 init4;		/* 0x00e0 */
+	u32 init5;		/* 0x00e4 */
+	u32 reserved4[0x03];
+	u32 rankctl;		/* 0x00f4 */
+	u32 reserved5[0x02];
+	u32 dramtmg0;		/* 0x0100 */
+	u32 dramtmg1;		/* 0x0104 */
+	u32 dramtmg2;		/* 0x0108 */
+	u32 dramtmg3;		/* 0x010c */
+	u32 dramtmg4;		/* 0x0110 */
+	u32 dramtmg5;		/* 0x0114 */
+	u32 reserved6[0x02];
+	u32 dramtmg8;		/* 0x0120 */
+	u32 reserved7[0x17];
+	u32 zqctl0;		/* 0x0180 */
+	u32 reserved8[0x03];
+	u32 dfitmg0;		/* 0x0190 */
+	u32 dfitmg1;		/* 0x0194 */
+	u32 reserved9[0x02];
+	u32 dfiupd0;		/* 0x01a0 */
+	u32 dfiupd1;		/* 0x01a4 */
+	u32 dfiupd2;		/* 0x01a8 */
+	u32 reserved10[0x15];
+	u32 addrmap0;		/* 0x0200 */
+	u32 addrmap1;		/* 0x0204 */
+	u32 addrmap2;		/* 0x0208 */
+	u32 addrmap3;		/* 0x020c */
+	u32 addrmap4;		/* 0x0210 */
+	u32 addrmap5;		/* 0x0214 */
+	u32 addrmap6;		/* 0x0218 */
+	u32 reserved12[0x09];
+	u32 odtcfg;		/* 0x0240 */
+	u32 odtmap;		/* 0x0244 */
+};
+
+/* DDRC_MSTR fields */
+#define MSTR_DATA_BUS_WIDTH_MASK	0x3 << 12
+#define MSTR_DATA_BUS_WIDTH_SHIFT	12
+#define MSTR_DATA_ACTIVE_RANKS_MASK	0xf << 24
+#define MSTR_DATA_ACTIVE_RANKS_SHIFT	24
+/* DDRC_ADDRMAP1 fields */
+#define ADDRMAP1_BANK_B0_MASK		0x1f << 0
+#define ADDRMAP1_BANK_B0_SHIFT		0
+#define ADDRMAP1_BANK_B1_MASK		0x1f << 8
+#define ADDRMAP1_BANK_B1_SHIFT		8
+#define ADDRMAP1_BANK_B2_MASK		0x1f << 16
+#define ADDRMAP1_BANK_B2_SHIFT		16
+/* DDRC_ADDRMAP2 fields */
+#define ADDRMAP2_COL_B2_MASK		0xF << 0
+#define ADDRMAP2_COL_B2_SHIFT		0
+#define ADDRMAP2_COL_B3_MASK		0xF << 8
+#define ADDRMAP2_COL_B3_SHIFT		8
+#define ADDRMAP2_COL_B4_MASK		0xF << 16
+#define ADDRMAP2_COL_B4_SHIFT		16
+#define ADDRMAP2_COL_B5_MASK		0xF << 24
+#define ADDRMAP2_COL_B5_SHIFT		24
+/* DDRC_ADDRMAP3 fields */
+#define ADDRMAP3_COL_B6_MASK		0xF << 0
+#define ADDRMAP3_COL_B6_SHIFT		0
+#define ADDRMAP3_COL_B7_MASK		0xF << 8
+#define ADDRMAP3_COL_B7_SHIFT		8
+#define ADDRMAP3_COL_B8_MASK		0xF << 16
+#define ADDRMAP3_COL_B8_SHIFT		16
+#define ADDRMAP3_COL_B9_MASK		0xF << 24
+#define ADDRMAP3_COL_B9_SHIFT		24
+/* DDRC_ADDRMAP4 fields */
+#define ADDRMAP4_COL_B10_MASK		0xF << 0
+#define ADDRMAP4_COL_B10_SHIFT		0
+#define ADDRMAP4_COL_B11_MASK		0xF << 8
+#define ADDRMAP4_COL_B11_SHIFT		8
+/* DDRC_ADDRMAP5 fields */
+#define ADDRMAP5_ROW_B0_MASK		0xF << 0
+#define ADDRMAP5_ROW_B0_SHIFT		0
+#define ADDRMAP5_ROW_B1_MASK		0xF << 8
+#define ADDRMAP5_ROW_B1_SHIFT		8
+#define ADDRMAP5_ROW_B2_10_MASK		0xF << 16
+#define ADDRMAP5_ROW_B2_10_SHIFT	16
+#define ADDRMAP5_ROW_B11_MASK		0xF << 24
+#define ADDRMAP5_ROW_B11_SHIFT		24
+/* DDRC_ADDRMAP6 fields */
+#define ADDRMAP6_ROW_B12_MASK		0xF << 0
+#define ADDRMAP6_ROW_B12_SHIFT		0
+#define ADDRMAP6_ROW_B13_MASK		0xF << 8
+#define ADDRMAP6_ROW_B13_SHIFT		8
+#define ADDRMAP6_ROW_B14_MASK		0xF << 16
+#define ADDRMAP6_ROW_B14_SHIFT		16
+#define ADDRMAP6_ROW_B15_MASK		0xF << 24
+#define ADDRMAP6_ROW_B15_SHIFT		24
+
+/* DDRC_MP Registers */
+#define DDRC_MP_BASE_ADDR (DDRC_IPS_BASE_ADDR + 0x03fc)
+struct ddrc_mp {
+	u32 reserved1[0x25];
+	u32 pctrl_0;		/* 0x0094 */
+};
+
+/* DDR_PHY registers */
+struct ddr_phy {
+	u32 phy_con0;		/* 0x0000 */
+	u32 phy_con1;		/* 0x0004 */
+	u32 reserved1[0x02];
+	u32 phy_con4;		/* 0x0010 */
+	u32 reserved2;
+	u32 offset_lp_con0;	/* 0x0018 */
+	u32 reserved3;
+	u32 offset_rd_con0;	/* 0x0020 */
+	u32 reserved4[0x03];
+	u32 offset_wr_con0;	/* 0x0030 */
+	u32 reserved5[0x07];
+	u32 cmd_sdll_con0;	/* 0x0050 */
+	u32 reserved6[0x12];
+	u32 drvds_con0;		/* 0x009c */
+	u32 reserved7[0x04];
+	u32 mdll_con0;		/* 0x00b0 */
+	u32 reserved8[0x03];
+	u32 zq_con0;		/* 0x00c0 */
+};
+
+#define DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK BIT(24)
+
+#define MX7_CAL_VAL_MAX 5
+/* Calibration parameters */
+struct mx7_calibration {
+	int num_val;			/* Number of calibration values */
+	u32 values[MX7_CAL_VAL_MAX];	/* calibration values */
+};
+
+void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
+		  struct ddr_phy *ddr_phy_regs_val,
+		  struct mx7_calibration *calib_param);
+
+#endif	/*__ASM_ARCH_MX7_DDR_H__ */
diff --git a/arch/arm/include/asm/arch-mx7/mx7-pins.h b/arch/arm/include/asm/arch-mx7/mx7-pins.h
new file mode 100644
index 0000000..bc99a86
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/mx7-pins.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+#ifndef __ASM_ARCH_MX7_PINS_H__
+#define __ASM_ARCH_MX7_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+#if defined(CONFIG_MX7D)
+#include "mx7d_pins.h"
+#elif defined(CONFIG_MX7S)
+#include "mx7s_pins.h"
+#else
+#error "Please select cpu"
+#endif	/* CONFIG_MX7D */
+
+#endif	/*__ASM_ARCH_MX7_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx7/mx7_plugin.S b/arch/arm/include/asm/arch-mx7/mx7_plugin.S
new file mode 100644
index 0000000..c7a84e8
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/mx7_plugin.S
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <config.h>
+
+#define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
+#define ROM_VERSION_OFFSET               	0x80
+#define ROM_API_HWCNFG_SETUP_OFFSET		0x08
+
+plugin_start:
+
+	push    {r0-r4, lr}
+
+	imx7_ddr_setting
+	imx7_clock_gating
+	imx7_qos_setting
+
+/*
+ * Check if we are in USB serial download mode and immediately return to ROM
+ * Need to check USB CTRL clock firstly, then check the USBx_nASYNCLISTADDR
+ */
+	ldr r0, =0x30384680
+	ldr r1, [r0]
+	cmp r1, #0
+	beq normal_boot
+
+	ldr r0, =0x30B10158
+	ldr r1, [r0]
+	cmp r1, #0
+	beq normal_boot
+
+	pop {r0-r4, lr}
+	bx lr
+
+normal_boot:
+
+/*
+ * The following is to fill in those arguments for this ROM function
+ * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+ * This function is used to copy data from the storage media into DDR.
+ * start - Initial (possibly partial) image load address on entry.
+ *         Final image load address on exit.
+ * bytes - Initial (possibly partial) image size on entry.
+ *         Final image size on exit.
+ * boot_data - Initial @ref ivt Boot Data load address.
+ */
+	adr r0, boot_data2
+	adr r1, image_len2
+	adr r2, boot_data2
+
+/*
+ * check the _pu_irom_api_table for the address
+ */
+before_calling_rom___pu_irom_hwcnfg_setup:
+	ldr r3, =ROM_VERSION_OFFSET
+	ldr r4, [r3]
+	ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
+	ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
+	blx r4
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+
+/* To return to ROM from plugin, we need to fill in these argument.
+ * Here is what need to do:
+ * Need to construct the paramters for this function before return to ROM:
+ * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+	pop {r0-r4, lr}
+	push {r5}
+	ldr r5, boot_data2
+	str r5, [r0]
+	ldr r5, image_len2
+	str r5, [r1]
+	ldr r5, second_ivt_offset
+	str r5, [r2]
+	mov r0, #1
+	pop {r5}
+
+	/* return back to ROM code */
+	bx lr
+
+/* make the following data right in the end of the output*/
+.ltorg
+
+#define FLASH_OFFSET 0x400
+
+/*
+ * second_ivt_offset is the offset from the "second_ivt_header" to
+ * "image_copy_start", which involves FLASH_OFFSET, plus the first
+ * ivt_header, the plugin code size itself recorded by "ivt2_header"
+ */
+
+second_ivt_offset:      .long (ivt2_header + 0x2C + FLASH_OFFSET)
+
+/*
+ * The following is the second IVT header plus the second boot data
+ */
+ivt2_header:            .long 0x0
+app2_code_jump_v:       .long 0x0
+reserv3:                .long 0x0
+dcd2_ptr:               .long 0x0
+boot_data2_ptr:         .long 0x0
+self_ptr2:              .long 0x0
+app_code_csf2:          .long 0x0
+reserv4:                .long 0x0
+boot_data2:             .long 0x0
+image_len2:             .long 0x0
+plugin2:                .long 0x0
diff --git a/arch/arm/include/asm/arch-mx7/mx7d_pins.h b/arch/arm/include/asm/arch-mx7/mx7d_pins.h
new file mode 100644
index 0000000..d54680f
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/mx7d_pins.h
@@ -0,0 +1,1307 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_IMX7D_PINS_H__
+#define __ASM_ARCH_IMX7D_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+	MX7D_PAD_GPIO1_IO00__GPIO1_IO0                           = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO00__PWM4_OUT				 = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B                        = IOMUX_PAD(0x0030, 0x0000, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
+
+	MX7D_PAD_GPIO1_IO01__GPIO1_IO1                           = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO01__PWM1_OUT                            = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3                   = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 2, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO01__SAI1_MCLK				 = IOMUX_PAD(0x0034, 0x0004, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
+
+	MX7D_PAD_GPIO1_IO02__GPIO1_IO2                           = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO02__PWM2_OUT                            = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1                   = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 2, 0x0564, 3, 0),
+	MX7D_PAD_GPIO1_IO02__SAI2_MCLK                           = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO02__CCM_CLKO1                           = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO02__USB_OTG1_ID                         = IOMUX_PAD(0x0038, 0x0008, IOMUX_CONFIG_LPSR | 7, 0x0734, 3, 0),
+
+	MX7D_PAD_GPIO1_IO03__GPIO1_IO3                           = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO03__PWM3_OUT                            = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2                   = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 2, 0x0570, 3, 0),
+	MX7D_PAD_GPIO1_IO03__SAI3_MCLK                           = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 3, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO03__CCM_CLKO2                           = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO03__USB_OTG2_ID                         = IOMUX_PAD(0x003c, 0x000C, IOMUX_CONFIG_LPSR | 7, 0x0730, 3, 0),
+
+	MX7D_PAD_GPIO1_IO04__GPIO1_IO4                           = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO04__USB_OTG1_OC                         = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 1, 0x072C, 1, 0),
+	MX7D_PAD_GPIO1_IO04__FLEXTIMER_CH4                       = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 2, 0x0594, 1, 0),
+	MX7D_PAD_GPIO1_IO04__UART5_CTS_B                         = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | 3, 0x0710, 4, 0),
+	MX7D_PAD_GPIO1_IO04__I2C1_SCL                            = IOMUX_PAD(0x0040, 0x0010, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D4, 2, 0),
+
+	MX7D_PAD_GPIO1_IO05__GPIO1_IO5                           = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR                        = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5                      = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 2, 0x0598, 1, 0),
+	MX7D_PAD_GPIO1_IO05__UART5_RTS_B                         = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | 3, 0x0710, 5, 0),
+	MX7D_PAD_GPIO1_IO05__I2C1_SDA                            = IOMUX_PAD(0x0044, 0x0014, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05D8, 2, 0),
+
+	MX7D_PAD_GPIO1_IO06__GPIO1_IO6                           = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO06__USB_OTG2_OC                         = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 1, 0x0728, 1, 0),
+	MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6                      = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 2, 0x059C, 1, 0),
+	MX7D_PAD_GPIO1_IO06__UART5_RX_DATA                       = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 3, 0x0714, 4, 0),
+	MX7D_PAD_GPIO1_IO06__I2C2_SCL                            = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05DC, 2, 0),
+	MX7D_PAD_GPIO1_IO06__CCM_WAIT				 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO06__KPP_ROW4				 = IOMUX_PAD(0x0048, 0x0018, IOMUX_CONFIG_LPSR | 6, 0x0624, 1, 0),
+
+	MX7D_PAD_GPIO1_IO07__GPIO1_IO7                           = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR                        = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7                      = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 2, 0x05A0, 1, 0),
+	MX7D_PAD_GPIO1_IO07__UART5_TX_DATA                       = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 3, 0x0714, 5, 0),
+	MX7D_PAD_GPIO1_IO07__I2C2_SDA                            = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | IOMUX_CONFIG_SION | 4, 0x05E0, 2, 0),
+	MX7D_PAD_GPIO1_IO07__CCM_STOP				 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO07__KPP_COL4				 = IOMUX_PAD(0x004c, 0x001c, IOMUX_CONFIG_LPSR | 6, 0x0604, 1, 0),
+};
+
+enum {
+	MX7D_PAD_GPIO1_IO08__GPIO1_IO8                           = IOMUX_PAD(0x026C, 0x0014, 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO08__SD1_VSELECT                         = IOMUX_PAD(0x026C, 0x0014, 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B                        = IOMUX_PAD(0x026C, 0x0014, 2, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO08__UART3_DCE_RX                        = IOMUX_PAD(0x026C, 0x0014, 3, 0x0704, 0, 0),
+	MX7D_PAD_GPIO1_IO08__UART3_DTE_TX                        = IOMUX_PAD(0x026C, 0x0014, 3, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO08__I2C3_SCL                            = IOMUX_PAD(0x026C, 0x0014, IOMUX_CONFIG_SION | 4, 0x05E4, 0, 0),
+	MX7D_PAD_GPIO1_IO08__KPP_COL5                            = IOMUX_PAD(0x026C, 0x0014, 6, 0x0608, 0, 0),
+	MX7D_PAD_GPIO1_IO08__PWM1_OUT                            = IOMUX_PAD(0x026C, 0x0014, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_GPIO1_IO09__GPIO1_IO9                           = IOMUX_PAD(0x0270, 0x0018, 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO09__SD1_LCTL                            = IOMUX_PAD(0x0270, 0x0018, 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3                   = IOMUX_PAD(0x0270, 0x0018, 2, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO09__UART3_DCE_TX                        = IOMUX_PAD(0x0270, 0x0018, 3, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO09__UART3_DTE_RX                        = IOMUX_PAD(0x0270, 0x0018, 3, 0x0704, 1, 0),
+	MX7D_PAD_GPIO1_IO09__I2C3_SDA                            = IOMUX_PAD(0x0270, 0x0018, IOMUX_CONFIG_SION | 4, 0x05E8, 0, 0),
+	MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY                      = IOMUX_PAD(0x0270, 0x0018, 5, 0x04F4, 0, 0),
+	MX7D_PAD_GPIO1_IO09__KPP_ROW5                            = IOMUX_PAD(0x0270, 0x0018, 6, 0x0628, 0, 0),
+	MX7D_PAD_GPIO1_IO09__PWM2_OUT                            = IOMUX_PAD(0x0270, 0x0018, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_GPIO1_IO10__GPIO1_IO10                          = IOMUX_PAD(0x0274, 0x001C, 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO10__SD2_LCTL                            = IOMUX_PAD(0x0274, 0x001C, 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO10__ENET1_MDIO                          = IOMUX_PAD(0x0274, 0x001C, 2, 0x0568, 0, 0),
+	MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS                       = IOMUX_PAD(0x0274, 0x001C, 3, 0x0700, 0, 0),
+	MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS                       = IOMUX_PAD(0x0274, 0x001C, 3, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO10__I2C4_SCL                            = IOMUX_PAD(0x0274, 0x001C, IOMUX_CONFIG_SION | 4, 0x05EC, 0, 0),
+	MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA                      = IOMUX_PAD(0x0274, 0x001C, 5, 0x05A4, 0, 0),
+	MX7D_PAD_GPIO1_IO10__KPP_COL6                            = IOMUX_PAD(0x0274, 0x001C, 6, 0x060C, 0, 0),
+	MX7D_PAD_GPIO1_IO10__PWM3_OUT                            = IOMUX_PAD(0x0274, 0x001C, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_GPIO1_IO11__GPIO1_IO11                          = IOMUX_PAD(0x0278, 0x0020, 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO11__SD3_LCTL                            = IOMUX_PAD(0x0278, 0x0020, 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO11__ENET1_MDC                           = IOMUX_PAD(0x0278, 0x0020, 2, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS                       = IOMUX_PAD(0x0278, 0x0020, 3, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS                       = IOMUX_PAD(0x0278, 0x0020, 3, 0x0700, 1, 0),
+	MX7D_PAD_GPIO1_IO11__I2C4_SDA                            = IOMUX_PAD(0x0278, 0x0020, IOMUX_CONFIG_SION | 4, 0x05F0, 0, 0),
+	MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB                      = IOMUX_PAD(0x0278, 0x0020, 5, 0x05A8, 0, 0),
+	MX7D_PAD_GPIO1_IO11__KPP_ROW6                            = IOMUX_PAD(0x0278, 0x0020, 6, 0x062C, 0, 0),
+	MX7D_PAD_GPIO1_IO11__PWM4_OUT                            = IOMUX_PAD(0x0278, 0x0020, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_GPIO1_IO12__GPIO1_IO12                          = IOMUX_PAD(0x027C, 0x0024, 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO12__SD2_VSELECT                         = IOMUX_PAD(0x027C, 0x0024, 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1                   = IOMUX_PAD(0x027C, 0x0024, 2, 0x0564, 0, 0),
+	MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX                         = IOMUX_PAD(0x027C, 0x0024, 3, 0x04DC, 0, 0),
+	MX7D_PAD_GPIO1_IO12__CM4_NMI                             = IOMUX_PAD(0x027C, 0x0024, 4, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1                        = IOMUX_PAD(0x027C, 0x0024, 5, 0x04E4, 0, 0),
+	MX7D_PAD_GPIO1_IO12__SNVS_VIO_5                          = IOMUX_PAD(0x027C, 0x0024, 6, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO12__USB_OTG1_ID                         = IOMUX_PAD(0x027C, 0x0024, 7, 0x0734, 0, 0),
+
+	MX7D_PAD_GPIO1_IO13__GPIO1_IO13                          = IOMUX_PAD(0x0280, 0x0028, 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO13__SD3_VSELECT                         = IOMUX_PAD(0x0280, 0x0028, 1, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2                   = IOMUX_PAD(0x0280, 0x0028, 2, 0x0570, 0, 0),
+	MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX                         = IOMUX_PAD(0x0280, 0x0028, 3, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY                      = IOMUX_PAD(0x0280, 0x0028, 4, 0x04F4, 1, 0),
+	MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2                        = IOMUX_PAD(0x0280, 0x0028, 5, 0x04E8, 0, 0),
+	MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL                      = IOMUX_PAD(0x0280, 0x0028, 6, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO13__USB_OTG2_ID                         = IOMUX_PAD(0x0280, 0x0028, 7, 0x0730, 0, 0),
+
+	MX7D_PAD_GPIO1_IO14__GPIO1_IO14                          = IOMUX_PAD(0x0284, 0x002C, 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO14__SD3_CD_B                            = IOMUX_PAD(0x0284, 0x002C, 1, 0x0738, 0, 0),
+	MX7D_PAD_GPIO1_IO14__ENET2_MDIO                          = IOMUX_PAD(0x0284, 0x002C, 2, 0x0574, 0, 0),
+	MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX                         = IOMUX_PAD(0x0284, 0x002C, 3, 0x04E0, 0, 0),
+	MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B                        = IOMUX_PAD(0x0284, 0x002C, 4, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3                        = IOMUX_PAD(0x0284, 0x002C, 5, 0x04EC, 0, 0),
+	MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0                     = IOMUX_PAD(0x0284, 0x002C, 6, 0x06D8, 0, 0),
+
+	MX7D_PAD_GPIO1_IO15__GPIO1_IO15                          = IOMUX_PAD(0x0288, 0x0030, 0, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO15__SD3_WP                              = IOMUX_PAD(0x0288, 0x0030, 1, 0x073C, 0, 0),
+	MX7D_PAD_GPIO1_IO15__ENET2_MDC                           = IOMUX_PAD(0x0288, 0x0030, 2, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX                         = IOMUX_PAD(0x0288, 0x0030, 3, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B                        = IOMUX_PAD(0x0288, 0x0030, 4, 0x0000, 0, 0),
+	MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4                        = IOMUX_PAD(0x0288, 0x0030, 5, 0x04F0, 0, 0),
+	MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1                     = IOMUX_PAD(0x0288, 0x0030, 6, 0x06DC, 0, 0),
+
+	MX7D_PAD_EPDC_DATA00__EPDC_DATA0                         = IOMUX_PAD(0x02A4, 0x0034, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD                    = IOMUX_PAD(0x02A4, 0x0034, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0                       = IOMUX_PAD(0x02A4, 0x0034, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA00__KPP_ROW3                           = IOMUX_PAD(0x02A4, 0x0034, 3, 0x0620, 0, 0),
+	MX7D_PAD_EPDC_DATA00__EIM_AD0                            = IOMUX_PAD(0x02A4, 0x0034, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA00__GPIO2_IO0                          = IOMUX_PAD(0x02A4, 0x0034, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA00__LCD_DATA0                          = IOMUX_PAD(0x02A4, 0x0034, 6, 0x0638, 0, 0),
+	MX7D_PAD_EPDC_DATA00__LCD_CLK                            = IOMUX_PAD(0x02A4, 0x0034, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA01__EPDC_DATA1                         = IOMUX_PAD(0x02A8, 0x0038, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK                     = IOMUX_PAD(0x02A8, 0x0038, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1                       = IOMUX_PAD(0x02A8, 0x0038, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA01__KPP_COL3                           = IOMUX_PAD(0x02A8, 0x0038, 3, 0x0600, 0, 0),
+	MX7D_PAD_EPDC_DATA01__EIM_AD1                            = IOMUX_PAD(0x02A8, 0x0038, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA01__GPIO2_IO1                          = IOMUX_PAD(0x02A8, 0x0038, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA01__LCD_DATA1                          = IOMUX_PAD(0x02A8, 0x0038, 6, 0x063C, 0, 0),
+	MX7D_PAD_EPDC_DATA01__LCD_ENABLE                         = IOMUX_PAD(0x02A8, 0x0038, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA02__EPDC_DATA2                         = IOMUX_PAD(0x02AC, 0x003C, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B                   = IOMUX_PAD(0x02AC, 0x003C, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2                       = IOMUX_PAD(0x02AC, 0x003C, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA02__KPP_ROW2                           = IOMUX_PAD(0x02AC, 0x003C, 3, 0x061C, 0, 0),
+	MX7D_PAD_EPDC_DATA02__EIM_AD2                            = IOMUX_PAD(0x02AC, 0x003C, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA02__GPIO2_IO2                          = IOMUX_PAD(0x02AC, 0x003C, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA02__LCD_DATA2                          = IOMUX_PAD(0x02AC, 0x003C, 6, 0x0640, 0, 0),
+	MX7D_PAD_EPDC_DATA02__LCD_VSYNC                          = IOMUX_PAD(0x02AC, 0x003C, 7, 0x0698, 0, 0),
+
+	MX7D_PAD_EPDC_DATA03__EPDC_DATA3                         = IOMUX_PAD(0x02B0, 0x0040, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN                    = IOMUX_PAD(0x02B0, 0x0040, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3                       = IOMUX_PAD(0x02B0, 0x0040, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA03__KPP_COL2                           = IOMUX_PAD(0x02B0, 0x0040, 3, 0x05FC, 0, 0),
+	MX7D_PAD_EPDC_DATA03__EIM_AD3                            = IOMUX_PAD(0x02B0, 0x0040, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA03__GPIO2_IO3                          = IOMUX_PAD(0x02B0, 0x0040, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA03__LCD_DATA3                          = IOMUX_PAD(0x02B0, 0x0040, 6, 0x0644, 0, 0),
+	MX7D_PAD_EPDC_DATA03__LCD_HSYNC                          = IOMUX_PAD(0x02B0, 0x0040, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA04__EPDC_DATA4                         = IOMUX_PAD(0x02B4, 0x0044, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD                      = IOMUX_PAD(0x02B4, 0x0044, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA04__QSPI_A_DQS                         = IOMUX_PAD(0x02B4, 0x0044, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA04__KPP_ROW1                           = IOMUX_PAD(0x02B4, 0x0044, 3, 0x0618, 0, 0),
+	MX7D_PAD_EPDC_DATA04__EIM_AD4                            = IOMUX_PAD(0x02B4, 0x0044, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA04__GPIO2_IO4                          = IOMUX_PAD(0x02B4, 0x0044, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA04__LCD_DATA4                          = IOMUX_PAD(0x02B4, 0x0044, 6, 0x0648, 0, 0),
+	MX7D_PAD_EPDC_DATA04__JTAG_FAIL                          = IOMUX_PAD(0x02B4, 0x0044, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA05__EPDC_DATA5                         = IOMUX_PAD(0x02B8, 0x0048, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD                    = IOMUX_PAD(0x02B8, 0x0048, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK                        = IOMUX_PAD(0x02B8, 0x0048, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA05__KPP_COL1                           = IOMUX_PAD(0x02B8, 0x0048, 3, 0x05F8, 0, 0),
+	MX7D_PAD_EPDC_DATA05__EIM_AD5                            = IOMUX_PAD(0x02B8, 0x0048, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA05__GPIO2_IO5                          = IOMUX_PAD(0x02B8, 0x0048, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA05__LCD_DATA5                          = IOMUX_PAD(0x02B8, 0x0048, 6, 0x064C, 0, 0),
+	MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE                        = IOMUX_PAD(0x02B8, 0x0048, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA06__EPDC_DATA6                         = IOMUX_PAD(0x02BC, 0x004C, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK                     = IOMUX_PAD(0x02BC, 0x004C, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B                       = IOMUX_PAD(0x02BC, 0x004C, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA06__KPP_ROW0                           = IOMUX_PAD(0x02BC, 0x004C, 3, 0x0614, 0, 0),
+	MX7D_PAD_EPDC_DATA06__EIM_AD6                            = IOMUX_PAD(0x02BC, 0x004C, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA06__GPIO2_IO6                          = IOMUX_PAD(0x02BC, 0x004C, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA06__LCD_DATA6                          = IOMUX_PAD(0x02BC, 0x004C, 6, 0x0650, 0, 0),
+	MX7D_PAD_EPDC_DATA06__JTAG_DE_B                          = IOMUX_PAD(0x02BC, 0x004C, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA07__EPDC_DATA7                         = IOMUX_PAD(0x02C0, 0x0050, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B                   = IOMUX_PAD(0x02C0, 0x0050, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B                       = IOMUX_PAD(0x02C0, 0x0050, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA07__KPP_COL0                           = IOMUX_PAD(0x02C0, 0x0050, 3, 0x05F4, 0, 0),
+	MX7D_PAD_EPDC_DATA07__EIM_AD7                            = IOMUX_PAD(0x02C0, 0x0050, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA07__GPIO2_IO7                          = IOMUX_PAD(0x02C0, 0x0050, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA07__LCD_DATA7                          = IOMUX_PAD(0x02C0, 0x0050, 6, 0x0654, 0, 0),
+	MX7D_PAD_EPDC_DATA07__JTAG_DONE                          = IOMUX_PAD(0x02C0, 0x0050, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA08__EPDC_DATA8                         = IOMUX_PAD(0x02C4, 0x0054, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD                    = IOMUX_PAD(0x02C4, 0x0054, 1, 0x06E4, 0, 0),
+	MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0                       = IOMUX_PAD(0x02C4, 0x0054, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA08__UART6_DCE_RX                       = IOMUX_PAD(0x02C4, 0x0054, 3, 0x071C, 0, 0),
+	MX7D_PAD_EPDC_DATA08__UART6_DTE_TX                       = IOMUX_PAD(0x02C4, 0x0054, 3, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA08__EIM_OE                             = IOMUX_PAD(0x02C4, 0x0054, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA08__GPIO2_IO8                          = IOMUX_PAD(0x02C4, 0x0054, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA08__LCD_DATA8                          = IOMUX_PAD(0x02C4, 0x0054, 6, 0x0658, 0, 0),
+	MX7D_PAD_EPDC_DATA08__LCD_BUSY                           = IOMUX_PAD(0x02C4, 0x0054, 7, 0x0634, 0, 0),
+	MX7D_PAD_EPDC_DATA08__EPDC_SDCLK                         = IOMUX_PAD(0x02C4, 0x0054, 8, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA09__EPDC_DATA9                         = IOMUX_PAD(0x02C8, 0x0058, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK                     = IOMUX_PAD(0x02C8, 0x0058, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1                       = IOMUX_PAD(0x02C8, 0x0058, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA09__UART6_DCE_TX                       = IOMUX_PAD(0x02C8, 0x0058, 3, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA09__UART6_DTE_RX                       = IOMUX_PAD(0x02C8, 0x0058, 3, 0x071C, 1, 0),
+	MX7D_PAD_EPDC_DATA09__EIM_RW                             = IOMUX_PAD(0x02C8, 0x0058, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA09__GPIO2_IO9                          = IOMUX_PAD(0x02C8, 0x0058, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA09__LCD_DATA9                          = IOMUX_PAD(0x02C8, 0x0058, 6, 0x065C, 0, 0),
+	MX7D_PAD_EPDC_DATA09__LCD_DATA0                          = IOMUX_PAD(0x02C8, 0x0058, 7, 0x0638, 1, 0),
+	MX7D_PAD_EPDC_DATA09__EPDC_SDLE                          = IOMUX_PAD(0x02C8, 0x0058, 8, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA10__EPDC_DATA10                        = IOMUX_PAD(0x02CC, 0x005C, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B                   = IOMUX_PAD(0x02CC, 0x005C, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2                       = IOMUX_PAD(0x02CC, 0x005C, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS                      = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0718, 0, 0),
+	MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS                      = IOMUX_PAD(0x02CC, 0x005C, 3, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA10__EIM_CS0_B                          = IOMUX_PAD(0x02CC, 0x005C, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA10__GPIO2_IO10                         = IOMUX_PAD(0x02CC, 0x005C, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA10__LCD_DATA10                         = IOMUX_PAD(0x02CC, 0x005C, 6, 0x0660, 0, 0),
+	MX7D_PAD_EPDC_DATA10__LCD_DATA9                          = IOMUX_PAD(0x02CC, 0x005C, 7, 0x065C, 1, 0),
+	MX7D_PAD_EPDC_DATA10__EPDC_SDOE                          = IOMUX_PAD(0x02CC, 0x005C, 8, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA11__EPDC_DATA11                        = IOMUX_PAD(0x02D0, 0x0060, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN                    = IOMUX_PAD(0x02D0, 0x0060, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3                       = IOMUX_PAD(0x02D0, 0x0060, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS                      = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS                      = IOMUX_PAD(0x02D0, 0x0060, 3, 0x0718, 1, 0),
+	MX7D_PAD_EPDC_DATA11__EIM_BCLK                           = IOMUX_PAD(0x02D0, 0x0060, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA11__GPIO2_IO11                         = IOMUX_PAD(0x02D0, 0x0060, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA11__LCD_DATA11                         = IOMUX_PAD(0x02D0, 0x0060, 6, 0x0664, 0, 0),
+	MX7D_PAD_EPDC_DATA11__LCD_DATA1                          = IOMUX_PAD(0x02D0, 0x0060, 7, 0x063C, 1, 0),
+	MX7D_PAD_EPDC_DATA11__EPDC_SDCE0                         = IOMUX_PAD(0x02D0, 0x0060, 8, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA12__EPDC_DATA12                        = IOMUX_PAD(0x02D4, 0x0064, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD                      = IOMUX_PAD(0x02D4, 0x0064, 1, 0x06E0, 0, 0),
+	MX7D_PAD_EPDC_DATA12__QSPI_B_DQS                         = IOMUX_PAD(0x02D4, 0x0064, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA12__UART7_DCE_RX                       = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0724, 0, 0),
+	MX7D_PAD_EPDC_DATA12__UART7_DTE_TX                       = IOMUX_PAD(0x02D4, 0x0064, 3, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA12__EIM_LBA_B                          = IOMUX_PAD(0x02D4, 0x0064, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA12__GPIO2_IO12                         = IOMUX_PAD(0x02D4, 0x0064, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA12__LCD_DATA12                         = IOMUX_PAD(0x02D4, 0x0064, 6, 0x0668, 0, 0),
+	MX7D_PAD_EPDC_DATA12__LCD_DATA21                         = IOMUX_PAD(0x02D4, 0x0064, 7, 0x068C, 0, 0),
+	MX7D_PAD_EPDC_DATA12__EPDC_GDCLK                         = IOMUX_PAD(0x02D4, 0x0064, 8, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA13__EPDC_DATA13                        = IOMUX_PAD(0x02D8, 0x0068, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD                    = IOMUX_PAD(0x02D8, 0x0068, 1, 0x06EC, 0, 0),
+	MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK                        = IOMUX_PAD(0x02D8, 0x0068, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA13__UART7_DCE_TX                       = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA13__UART7_DTE_RX                       = IOMUX_PAD(0x02D8, 0x0068, 3, 0x0724, 1, 0),
+	MX7D_PAD_EPDC_DATA13__EIM_WAIT                           = IOMUX_PAD(0x02D8, 0x0068, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA13__GPIO2_IO13                         = IOMUX_PAD(0x02D8, 0x0068, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA13__LCD_DATA13                         = IOMUX_PAD(0x02D8, 0x0068, 6, 0x066C, 0, 0),
+	MX7D_PAD_EPDC_DATA13__LCD_CS                             = IOMUX_PAD(0x02D8, 0x0068, 7, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA13__EPDC_GDOE                          = IOMUX_PAD(0x02D8, 0x0068, 8, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA14__EPDC_DATA14                        = IOMUX_PAD(0x02DC, 0x006C, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK                     = IOMUX_PAD(0x02DC, 0x006C, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B                       = IOMUX_PAD(0x02DC, 0x006C, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS                      = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0720, 0, 0),
+	MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS                      = IOMUX_PAD(0x02DC, 0x006C, 3, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA14__EIM_EB_B0                          = IOMUX_PAD(0x02DC, 0x006C, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA14__GPIO2_IO14                         = IOMUX_PAD(0x02DC, 0x006C, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA14__LCD_DATA14                         = IOMUX_PAD(0x02DC, 0x006C, 6, 0x0670, 0, 0),
+	MX7D_PAD_EPDC_DATA14__LCD_DATA22                         = IOMUX_PAD(0x02DC, 0x006C, 7, 0x0690, 0, 0),
+	MX7D_PAD_EPDC_DATA14__EPDC_GDSP                          = IOMUX_PAD(0x02DC, 0x006C, 8, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_DATA15__EPDC_DATA15                        = IOMUX_PAD(0x02E0, 0x0070, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B                   = IOMUX_PAD(0x02E0, 0x0070, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B                       = IOMUX_PAD(0x02E0, 0x0070, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS                      = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS                      = IOMUX_PAD(0x02E0, 0x0070, 3, 0x0720, 1, 0),
+	MX7D_PAD_EPDC_DATA15__EIM_CS1_B                          = IOMUX_PAD(0x02E0, 0x0070, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA15__GPIO2_IO15                         = IOMUX_PAD(0x02E0, 0x0070, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA15__LCD_DATA15                         = IOMUX_PAD(0x02E0, 0x0070, 6, 0x0674, 0, 0),
+	MX7D_PAD_EPDC_DATA15__LCD_WR_RWN                         = IOMUX_PAD(0x02E0, 0x0070, 7, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM                       = IOMUX_PAD(0x02E0, 0x0070, 8, 0x0000, 0, 0),
+
+	MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK                          = IOMUX_PAD(0x02E4, 0x0074, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN                     = IOMUX_PAD(0x02E4, 0x0074, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0                     = IOMUX_PAD(0x02E4, 0x0074, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCLK__KPP_ROW4                            = IOMUX_PAD(0x02E4, 0x0074, 3, 0x0624, 0, 0),
+	MX7D_PAD_EPDC_SDCLK__EIM_AD10                            = IOMUX_PAD(0x02E4, 0x0074, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCLK__GPIO2_IO16                          = IOMUX_PAD(0x02E4, 0x0074, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCLK__LCD_CLK                             = IOMUX_PAD(0x02E4, 0x0074, 6, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCLK__LCD_DATA20                          = IOMUX_PAD(0x02E4, 0x0074, 7, 0x0688, 0, 0),
+
+	MX7D_PAD_EPDC_SDLE__EPDC_SDLE                            = IOMUX_PAD(0x02E8, 0x0078, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD                        = IOMUX_PAD(0x02E8, 0x0078, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1                      = IOMUX_PAD(0x02E8, 0x0078, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDLE__KPP_COL4                             = IOMUX_PAD(0x02E8, 0x0078, 3, 0x0604, 0, 0),
+	MX7D_PAD_EPDC_SDLE__EIM_AD11                             = IOMUX_PAD(0x02E8, 0x0078, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDLE__GPIO2_IO17                           = IOMUX_PAD(0x02E8, 0x0078, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDLE__LCD_DATA16                           = IOMUX_PAD(0x02E8, 0x0078, 6, 0x0678, 0, 0),
+	MX7D_PAD_EPDC_SDLE__LCD_DATA8                            = IOMUX_PAD(0x02E8, 0x0078, 7, 0x0658, 1, 0),
+
+	MX7D_PAD_EPDC_SDOE__EPDC_SDOE                            = IOMUX_PAD(0x02EC, 0x007C, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0                       = IOMUX_PAD(0x02EC, 0x007C, 1, 0x0584, 0, 0),
+	MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2                      = IOMUX_PAD(0x02EC, 0x007C, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDOE__KPP_COL5                             = IOMUX_PAD(0x02EC, 0x007C, 3, 0x0608, 1, 0),
+	MX7D_PAD_EPDC_SDOE__EIM_AD12                             = IOMUX_PAD(0x02EC, 0x007C, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDOE__GPIO2_IO18                           = IOMUX_PAD(0x02EC, 0x007C, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDOE__LCD_DATA17                           = IOMUX_PAD(0x02EC, 0x007C, 6, 0x067C, 0, 0),
+	MX7D_PAD_EPDC_SDOE__LCD_DATA23                           = IOMUX_PAD(0x02EC, 0x007C, 7, 0x0694, 0, 0),
+
+	MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR                          = IOMUX_PAD(0x02F0, 0x0080, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1                      = IOMUX_PAD(0x02F0, 0x0080, 1, 0x0588, 0, 0),
+	MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3                     = IOMUX_PAD(0x02F0, 0x0080, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDSHR__KPP_ROW5                            = IOMUX_PAD(0x02F0, 0x0080, 3, 0x0628, 1, 0),
+	MX7D_PAD_EPDC_SDSHR__EIM_AD13                            = IOMUX_PAD(0x02F0, 0x0080, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDSHR__GPIO2_IO19                          = IOMUX_PAD(0x02F0, 0x0080, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDSHR__LCD_DATA18                          = IOMUX_PAD(0x02F0, 0x0080, 6, 0x0680, 0, 0),
+	MX7D_PAD_EPDC_SDSHR__LCD_DATA10                          = IOMUX_PAD(0x02F0, 0x0080, 7, 0x0660, 1, 0),
+
+	MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0                          = IOMUX_PAD(0x02F4, 0x0084, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2                      = IOMUX_PAD(0x02F4, 0x0084, 1, 0x058C, 0, 0),
+	MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL                  = IOMUX_PAD(0x02F4, 0x0084, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE0__EIM_AD14                            = IOMUX_PAD(0x02F4, 0x0084, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE0__GPIO2_IO20                          = IOMUX_PAD(0x02F4, 0x0084, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE0__LCD_DATA19                          = IOMUX_PAD(0x02F4, 0x0084, 6, 0x0684, 0, 0),
+	MX7D_PAD_EPDC_SDCE0__LCD_DATA5                           = IOMUX_PAD(0x02F4, 0x0084, 7, 0x064C, 1, 0),
+
+	MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1                          = IOMUX_PAD(0x02F8, 0x0088, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3                      = IOMUX_PAD(0x02F8, 0x0088, 1, 0x0590, 0, 0),
+	MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC                     = IOMUX_PAD(0x02F8, 0x0088, 2, 0x0578, 0, 0),
+	MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER                         = IOMUX_PAD(0x02F8, 0x0088, 3, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE1__EIM_AD15                            = IOMUX_PAD(0x02F8, 0x0088, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE1__GPIO2_IO21                          = IOMUX_PAD(0x02F8, 0x0088, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE1__LCD_DATA20                          = IOMUX_PAD(0x02F8, 0x0088, 6, 0x0688, 1, 0),
+	MX7D_PAD_EPDC_SDCE1__LCD_DATA4                           = IOMUX_PAD(0x02F8, 0x0088, 7, 0x0648, 1, 0),
+
+	MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2                          = IOMUX_PAD(0x02FC, 0x008C, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN                     = IOMUX_PAD(0x02FC, 0x008C, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0                     = IOMUX_PAD(0x02FC, 0x008C, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE2__KPP_COL6                            = IOMUX_PAD(0x02FC, 0x008C, 3, 0x060C, 1, 0),
+	MX7D_PAD_EPDC_SDCE2__EIM_ADDR16                          = IOMUX_PAD(0x02FC, 0x008C, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE2__GPIO2_IO22                          = IOMUX_PAD(0x02FC, 0x008C, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE2__LCD_DATA21                          = IOMUX_PAD(0x02FC, 0x008C, 6, 0x068C, 1, 0),
+	MX7D_PAD_EPDC_SDCE2__LCD_DATA3                           = IOMUX_PAD(0x02FC, 0x008C, 7, 0x0644, 1, 0),
+
+	MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3                          = IOMUX_PAD(0x0300, 0x0090, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD                       = IOMUX_PAD(0x0300, 0x0090, 1, 0x06E8, 0, 0),
+	MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1                     = IOMUX_PAD(0x0300, 0x0090, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE3__KPP_ROW6                            = IOMUX_PAD(0x0300, 0x0090, 3, 0x062C, 1, 0),
+	MX7D_PAD_EPDC_SDCE3__EIM_ADDR17                          = IOMUX_PAD(0x0300, 0x0090, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE3__GPIO2_IO23                          = IOMUX_PAD(0x0300, 0x0090, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_SDCE3__LCD_DATA22                          = IOMUX_PAD(0x0300, 0x0090, 6, 0x0690, 1, 0),
+	MX7D_PAD_EPDC_SDCE3__LCD_DATA2                           = IOMUX_PAD(0x0300, 0x0090, 7, 0x0640, 1, 0),
+
+	MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK                          = IOMUX_PAD(0x0304, 0x0094, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0                      = IOMUX_PAD(0x0304, 0x0094, 1, 0x05AC, 0, 0),
+	MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2                     = IOMUX_PAD(0x0304, 0x0094, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDCLK__KPP_COL7                            = IOMUX_PAD(0x0304, 0x0094, 3, 0x0610, 0, 0),
+	MX7D_PAD_EPDC_GDCLK__EIM_ADDR18                          = IOMUX_PAD(0x0304, 0x0094, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDCLK__GPIO2_IO24                          = IOMUX_PAD(0x0304, 0x0094, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDCLK__LCD_DATA23                          = IOMUX_PAD(0x0304, 0x0094, 6, 0x0694, 1, 0),
+	MX7D_PAD_EPDC_GDCLK__LCD_DATA16                          = IOMUX_PAD(0x0304, 0x0094, 7, 0x0678, 1, 0),
+
+	MX7D_PAD_EPDC_GDOE__EPDC_GDOE                            = IOMUX_PAD(0x0308, 0x0098, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1                       = IOMUX_PAD(0x0308, 0x0098, 1, 0x05B0, 0, 0),
+	MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3                      = IOMUX_PAD(0x0308, 0x0098, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDOE__KPP_ROW7                             = IOMUX_PAD(0x0308, 0x0098, 3, 0x0630, 0, 0),
+	MX7D_PAD_EPDC_GDOE__EIM_ADDR19                           = IOMUX_PAD(0x0308, 0x0098, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDOE__GPIO2_IO25                           = IOMUX_PAD(0x0308, 0x0098, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDOE__LCD_WR_RWN                           = IOMUX_PAD(0x0308, 0x0098, 6, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDOE__LCD_DATA18                           = IOMUX_PAD(0x0308, 0x0098, 7, 0x0680, 1, 0),
+
+	MX7D_PAD_EPDC_GDRL__EPDC_GDRL                            = IOMUX_PAD(0x030C, 0x009C, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2                       = IOMUX_PAD(0x030C, 0x009C, 1, 0x05B4, 0, 0),
+	MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL                   = IOMUX_PAD(0x030C, 0x009C, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDRL__EIM_ADDR20                           = IOMUX_PAD(0x030C, 0x009C, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDRL__GPIO2_IO26                           = IOMUX_PAD(0x030C, 0x009C, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDRL__LCD_RD_E                             = IOMUX_PAD(0x030C, 0x009C, 6, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDRL__LCD_DATA19                           = IOMUX_PAD(0x030C, 0x009C, 7, 0x0684, 1, 0),
+
+	MX7D_PAD_EPDC_GDSP__EPDC_GDSP                            = IOMUX_PAD(0x0310, 0x00A0, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3                       = IOMUX_PAD(0x0310, 0x00A0, 1, 0x05B8, 0, 0),
+	MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC                      = IOMUX_PAD(0x0310, 0x00A0, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDSP__ENET2_TX_ER                          = IOMUX_PAD(0x0310, 0x00A0, 3, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDSP__EIM_ADDR21                           = IOMUX_PAD(0x0310, 0x00A0, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDSP__GPIO2_IO27                           = IOMUX_PAD(0x0310, 0x00A0, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_GDSP__LCD_BUSY                             = IOMUX_PAD(0x0310, 0x00A0, 6, 0x0634, 1, 0),
+	MX7D_PAD_EPDC_GDSP__LCD_DATA17                           = IOMUX_PAD(0x0310, 0x00A0, 7, 0x067C, 1, 0),
+
+	MX7D_PAD_EPDC_BDR0__EPDC_BDR0                            = IOMUX_PAD(0x0314, 0x00A4, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK                         = IOMUX_PAD(0x0314, 0x00A4, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2                    = IOMUX_PAD(0x0314, 0x00A4, 3, 0x0570, 1, 0),
+	MX7D_PAD_EPDC_BDR0__EIM_ADDR22                           = IOMUX_PAD(0x0314, 0x00A4, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_BDR0__GPIO2_IO28                           = IOMUX_PAD(0x0314, 0x00A4, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_BDR0__LCD_CS                               = IOMUX_PAD(0x0314, 0x00A4, 6, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_BDR0__LCD_DATA7                            = IOMUX_PAD(0x0314, 0x00A4, 7, 0x0654, 1, 0),
+
+	MX7D_PAD_EPDC_BDR1__EPDC_BDR1                            = IOMUX_PAD(0x0318, 0x00A8, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN                          = IOMUX_PAD(0x0318, 0x00A8, 1, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK                         = IOMUX_PAD(0x0318, 0x00A8, 2, 0x0578, 1, 0),
+	MX7D_PAD_EPDC_BDR1__EIM_AD8                              = IOMUX_PAD(0x0318, 0x00A8, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_BDR1__GPIO2_IO29                           = IOMUX_PAD(0x0318, 0x00A8, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_BDR1__LCD_ENABLE                           = IOMUX_PAD(0x0318, 0x00A8, 6, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_BDR1__LCD_DATA6                            = IOMUX_PAD(0x0318, 0x00A8, 7, 0x0650, 1, 0),
+
+	MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM                      = IOMUX_PAD(0x031C, 0x00AC, 0, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA                    = IOMUX_PAD(0x031C, 0x00AC, 1, 0x05CC, 0, 0),
+	MX7D_PAD_EPDC_PWR_COM__ENET2_CRS                         = IOMUX_PAD(0x031C, 0x00AC, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_PWR_COM__EIM_AD9                           = IOMUX_PAD(0x031C, 0x00AC, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30                        = IOMUX_PAD(0x031C, 0x00AC, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC                         = IOMUX_PAD(0x031C, 0x00AC, 6, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_PWR_COM__LCD_DATA11                        = IOMUX_PAD(0x031C, 0x00AC, 7, 0x0664, 1, 0),
+
+	MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT                    = IOMUX_PAD(0x0320, 0x00B0, 0, 0x0580, 0, 0),
+	MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB                   = IOMUX_PAD(0x0320, 0x00B0, 1, 0x05D0, 0, 0),
+	MX7D_PAD_EPDC_PWR_STAT__ENET2_COL                        = IOMUX_PAD(0x0320, 0x00B0, 2, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1                        = IOMUX_PAD(0x0320, 0x00B0, 4, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31                       = IOMUX_PAD(0x0320, 0x00B0, 5, 0x0000, 0, 0),
+	MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC                        = IOMUX_PAD(0x0320, 0x00B0, 6, 0x0698, 1, 0),
+	MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12                       = IOMUX_PAD(0x0320, 0x00B0, 7, 0x0668, 1, 0),
+
+	MX7D_PAD_LCD_CLK__LCD_CLK                                = IOMUX_PAD(0x0324, 0x00B4, 0, 0x0000, 0, 0),
+	MX7D_PAD_LCD_CLK__ECSPI4_MISO                            = IOMUX_PAD(0x0324, 0x00B4, 1, 0x0558, 0, 0),
+	MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN                   = IOMUX_PAD(0x0324, 0x00B4, 2, 0x0000, 0, 0),
+	MX7D_PAD_LCD_CLK__CSI_DATA16                             = IOMUX_PAD(0x0324, 0x00B4, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_CLK__UART2_DCE_RX                           = IOMUX_PAD(0x0324, 0x00B4, 4, 0x06FC, 0, 0),
+	MX7D_PAD_LCD_CLK__UART2_DTE_TX                           = IOMUX_PAD(0x0324, 0x00B4, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_CLK__GPIO3_IO0                              = IOMUX_PAD(0x0324, 0x00B4, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_ENABLE__LCD_ENABLE                          = IOMUX_PAD(0x0328, 0x00B8, 0, 0x0000, 0, 0),
+	MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI                         = IOMUX_PAD(0x0328, 0x00B8, 1, 0x055C, 0, 0),
+	MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN                = IOMUX_PAD(0x0328, 0x00B8, 2, 0x0000, 0, 0),
+	MX7D_PAD_LCD_ENABLE__CSI_DATA17                          = IOMUX_PAD(0x0328, 0x00B8, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_ENABLE__UART2_DCE_TX                        = IOMUX_PAD(0x0328, 0x00B8, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_ENABLE__UART2_DTE_RX                        = IOMUX_PAD(0x0328, 0x00B8, 4, 0x06FC, 1, 0),
+	MX7D_PAD_LCD_ENABLE__GPIO3_IO1                           = IOMUX_PAD(0x0328, 0x00B8, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_HSYNC__LCD_HSYNC                            = IOMUX_PAD(0x032C, 0x00BC, 0, 0x0000, 0, 0),
+	MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK                          = IOMUX_PAD(0x032C, 0x00BC, 1, 0x0554, 0, 0),
+	MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN                 = IOMUX_PAD(0x032C, 0x00BC, 2, 0x0000, 0, 0),
+	MX7D_PAD_LCD_HSYNC__CSI_DATA18                           = IOMUX_PAD(0x032C, 0x00BC, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS                        = IOMUX_PAD(0x032C, 0x00BC, 4, 0x06F8, 0, 0),
+	MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS                        = IOMUX_PAD(0x032C, 0x00BC, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_HSYNC__GPIO3_IO2                            = IOMUX_PAD(0x032C, 0x00BC, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_VSYNC__LCD_VSYNC                            = IOMUX_PAD(0x0330, 0x00C0, 0, 0x0698, 2, 0),
+	MX7D_PAD_LCD_VSYNC__ECSPI4_SS0                           = IOMUX_PAD(0x0330, 0x00C0, 1, 0x0560, 0, 0),
+	MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN                 = IOMUX_PAD(0x0330, 0x00C0, 2, 0x0000, 0, 0),
+	MX7D_PAD_LCD_VSYNC__CSI_DATA19                           = IOMUX_PAD(0x0330, 0x00C0, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS                        = IOMUX_PAD(0x0330, 0x00C0, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS                        = IOMUX_PAD(0x0330, 0x00C0, 4, 0x06F8, 1, 0),
+	MX7D_PAD_LCD_VSYNC__GPIO3_IO3                            = IOMUX_PAD(0x0330, 0x00C0, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_RESET__LCD_RESET                            = IOMUX_PAD(0x0334, 0x00C4, 0, 0x0000, 0, 0),
+	MX7D_PAD_LCD_RESET__GPT1_COMPARE1                        = IOMUX_PAD(0x0334, 0x00C4, 1, 0x0000, 0, 0),
+	MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI                  = IOMUX_PAD(0x0334, 0x00C4, 2, 0x0000, 0, 0),
+	MX7D_PAD_LCD_RESET__CSI_FIELD                            = IOMUX_PAD(0x0334, 0x00C4, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_RESET__EIM_DTACK_B                          = IOMUX_PAD(0x0334, 0x00C4, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_RESET__GPIO3_IO4                            = IOMUX_PAD(0x0334, 0x00C4, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA00__LCD_DATA0                           = IOMUX_PAD(0x0338, 0x00C8, 0, 0x0638, 2, 0),
+	MX7D_PAD_LCD_DATA00__GPT1_COMPARE2                       = IOMUX_PAD(0x0338, 0x00C8, 1, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA00__CSI_DATA20                          = IOMUX_PAD(0x0338, 0x00C8, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA00__EIM_DATA0                           = IOMUX_PAD(0x0338, 0x00C8, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA00__GPIO3_IO5                           = IOMUX_PAD(0x0338, 0x00C8, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0                       = IOMUX_PAD(0x0338, 0x00C8, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA01__LCD_DATA1                           = IOMUX_PAD(0x033C, 0x00CC, 0, 0x063C, 2, 0),
+	MX7D_PAD_LCD_DATA01__GPT1_COMPARE3                       = IOMUX_PAD(0x033C, 0x00CC, 1, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA01__CSI_DATA21                          = IOMUX_PAD(0x033C, 0x00CC, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA01__EIM_DATA1                           = IOMUX_PAD(0x033C, 0x00CC, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA01__GPIO3_IO6                           = IOMUX_PAD(0x033C, 0x00CC, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1                       = IOMUX_PAD(0x033C, 0x00CC, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA02__LCD_DATA2                           = IOMUX_PAD(0x0340, 0x00D0, 0, 0x0640, 2, 0),
+	MX7D_PAD_LCD_DATA02__GPT1_CLK                            = IOMUX_PAD(0x0340, 0x00D0, 1, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA02__CSI_DATA22                          = IOMUX_PAD(0x0340, 0x00D0, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA02__EIM_DATA2                           = IOMUX_PAD(0x0340, 0x00D0, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA02__GPIO3_IO7                           = IOMUX_PAD(0x0340, 0x00D0, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2                       = IOMUX_PAD(0x0340, 0x00D0, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA03__LCD_DATA3                           = IOMUX_PAD(0x0344, 0x00D4, 0, 0x0644, 2, 0),
+	MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1                       = IOMUX_PAD(0x0344, 0x00D4, 1, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA03__CSI_DATA23                          = IOMUX_PAD(0x0344, 0x00D4, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA03__EIM_DATA3                           = IOMUX_PAD(0x0344, 0x00D4, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA03__GPIO3_IO8                           = IOMUX_PAD(0x0344, 0x00D4, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3                       = IOMUX_PAD(0x0344, 0x00D4, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA04__LCD_DATA4                           = IOMUX_PAD(0x0348, 0x00D8, 0, 0x0648, 2, 0),
+	MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2                       = IOMUX_PAD(0x0348, 0x00D8, 1, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA04__CSI_VSYNC                           = IOMUX_PAD(0x0348, 0x00D8, 3, 0x0520, 0, 0),
+	MX7D_PAD_LCD_DATA04__EIM_DATA4                           = IOMUX_PAD(0x0348, 0x00D8, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA04__GPIO3_IO9                           = IOMUX_PAD(0x0348, 0x00D8, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4                       = IOMUX_PAD(0x0348, 0x00D8, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA05__LCD_DATA5                           = IOMUX_PAD(0x034C, 0x00DC, 0, 0x064C, 2, 0),
+	MX7D_PAD_LCD_DATA05__CSI_HSYNC                           = IOMUX_PAD(0x034C, 0x00DC, 3, 0x0518, 0, 0),
+	MX7D_PAD_LCD_DATA05__EIM_DATA5                           = IOMUX_PAD(0x034C, 0x00DC, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA05__GPIO3_IO10                          = IOMUX_PAD(0x034C, 0x00DC, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5                       = IOMUX_PAD(0x034C, 0x00DC, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA06__LCD_DATA6                           = IOMUX_PAD(0x0350, 0x00E0, 0, 0x0650, 2, 0),
+	MX7D_PAD_LCD_DATA06__CSI_PIXCLK                          = IOMUX_PAD(0x0350, 0x00E0, 3, 0x051C, 0, 0),
+	MX7D_PAD_LCD_DATA06__EIM_DATA6                           = IOMUX_PAD(0x0350, 0x00E0, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA06__GPIO3_IO11                          = IOMUX_PAD(0x0350, 0x00E0, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6                       = IOMUX_PAD(0x0350, 0x00E0, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA07__LCD_DATA7                           = IOMUX_PAD(0x0354, 0x00E4, 0, 0x0654, 2, 0),
+	MX7D_PAD_LCD_DATA07__CSI_MCLK                            = IOMUX_PAD(0x0354, 0x00E4, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA07__EIM_DATA7                           = IOMUX_PAD(0x0354, 0x00E4, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA07__GPIO3_IO12                          = IOMUX_PAD(0x0354, 0x00E4, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7                       = IOMUX_PAD(0x0354, 0x00E4, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA08__LCD_DATA8                           = IOMUX_PAD(0x0358, 0x00E8, 0, 0x0658, 2, 0),
+	MX7D_PAD_LCD_DATA08__CSI_DATA9                           = IOMUX_PAD(0x0358, 0x00E8, 3, 0x0514, 0, 0),
+	MX7D_PAD_LCD_DATA08__EIM_DATA8                           = IOMUX_PAD(0x0358, 0x00E8, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA08__GPIO3_IO13                          = IOMUX_PAD(0x0358, 0x00E8, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8                       = IOMUX_PAD(0x0358, 0x00E8, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA09__LCD_DATA9                           = IOMUX_PAD(0x035C, 0x00EC, 0, 0x065C, 2, 0),
+	MX7D_PAD_LCD_DATA09__CSI_DATA8                           = IOMUX_PAD(0x035C, 0x00EC, 3, 0x0510, 0, 0),
+	MX7D_PAD_LCD_DATA09__EIM_DATA9                           = IOMUX_PAD(0x035C, 0x00EC, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA09__GPIO3_IO14                          = IOMUX_PAD(0x035C, 0x00EC, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9                       = IOMUX_PAD(0x035C, 0x00EC, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA10__LCD_DATA10                          = IOMUX_PAD(0x0360, 0x00F0, 0, 0x0660, 2, 0),
+	MX7D_PAD_LCD_DATA10__CSI_DATA7                           = IOMUX_PAD(0x0360, 0x00F0, 3, 0x050C, 0, 0),
+	MX7D_PAD_LCD_DATA10__EIM_DATA10                          = IOMUX_PAD(0x0360, 0x00F0, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA10__GPIO3_IO15                          = IOMUX_PAD(0x0360, 0x00F0, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10                      = IOMUX_PAD(0x0360, 0x00F0, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA11__LCD_DATA11                          = IOMUX_PAD(0x0364, 0x00F4, 0, 0x0664, 2, 0),
+	MX7D_PAD_LCD_DATA11__CSI_DATA6                           = IOMUX_PAD(0x0364, 0x00F4, 3, 0x0508, 0, 0),
+	MX7D_PAD_LCD_DATA11__EIM_DATA11                          = IOMUX_PAD(0x0364, 0x00F4, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA11__GPIO3_IO16                          = IOMUX_PAD(0x0364, 0x00F4, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11                      = IOMUX_PAD(0x0364, 0x00F4, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA12__LCD_DATA12                          = IOMUX_PAD(0x0368, 0x00F8, 0, 0x0668, 2, 0),
+	MX7D_PAD_LCD_DATA12__CSI_DATA5                           = IOMUX_PAD(0x0368, 0x00F8, 3, 0x0504, 0, 0),
+	MX7D_PAD_LCD_DATA12__EIM_DATA12                          = IOMUX_PAD(0x0368, 0x00F8, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA12__GPIO3_IO17                          = IOMUX_PAD(0x0368, 0x00F8, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12                      = IOMUX_PAD(0x0368, 0x00F8, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA13__LCD_DATA13                          = IOMUX_PAD(0x036C, 0x00FC, 0, 0x066C, 1, 0),
+	MX7D_PAD_LCD_DATA13__CSI_DATA4                           = IOMUX_PAD(0x036C, 0x00FC, 3, 0x0500, 0, 0),
+	MX7D_PAD_LCD_DATA13__EIM_DATA13                          = IOMUX_PAD(0x036C, 0x00FC, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA13__GPIO3_IO18                          = IOMUX_PAD(0x036C, 0x00FC, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13                      = IOMUX_PAD(0x036C, 0x00FC, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA14__LCD_DATA14                          = IOMUX_PAD(0x0370, 0x0100, 0, 0x0670, 1, 0),
+	MX7D_PAD_LCD_DATA14__CSI_DATA3                           = IOMUX_PAD(0x0370, 0x0100, 3, 0x04FC, 0, 0),
+	MX7D_PAD_LCD_DATA14__EIM_DATA14                          = IOMUX_PAD(0x0370, 0x0100, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA14__GPIO3_IO19                          = IOMUX_PAD(0x0370, 0x0100, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14                      = IOMUX_PAD(0x0370, 0x0100, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA15__LCD_DATA15                          = IOMUX_PAD(0x0374, 0x0104, 0, 0x0674, 1, 0),
+	MX7D_PAD_LCD_DATA15__CSI_DATA2                           = IOMUX_PAD(0x0374, 0x0104, 3, 0x04F8, 0, 0),
+	MX7D_PAD_LCD_DATA15__EIM_DATA15                          = IOMUX_PAD(0x0374, 0x0104, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA15__GPIO3_IO20                          = IOMUX_PAD(0x0374, 0x0104, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15                      = IOMUX_PAD(0x0374, 0x0104, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA16__LCD_DATA16                          = IOMUX_PAD(0x0378, 0x0108, 0, 0x0678, 2, 0),
+	MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4                      = IOMUX_PAD(0x0378, 0x0108, 1, 0x0594, 0, 0),
+	MX7D_PAD_LCD_DATA16__CSI_DATA1                           = IOMUX_PAD(0x0378, 0x0108, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA16__EIM_CRE                             = IOMUX_PAD(0x0378, 0x0108, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA16__GPIO3_IO21                          = IOMUX_PAD(0x0378, 0x0108, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16                      = IOMUX_PAD(0x0378, 0x0108, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA17__LCD_DATA17                          = IOMUX_PAD(0x037C, 0x010C, 0, 0x067C, 2, 0),
+	MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5                      = IOMUX_PAD(0x037C, 0x010C, 1, 0x0598, 0, 0),
+	MX7D_PAD_LCD_DATA17__CSI_DATA0                           = IOMUX_PAD(0x037C, 0x010C, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN                    = IOMUX_PAD(0x037C, 0x010C, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA17__GPIO3_IO22                          = IOMUX_PAD(0x037C, 0x010C, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17                      = IOMUX_PAD(0x037C, 0x010C, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA18__LCD_DATA18                          = IOMUX_PAD(0x0380, 0x0110, 0, 0x0680, 2, 0),
+	MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6                      = IOMUX_PAD(0x0380, 0x0110, 1, 0x059C, 0, 0),
+	MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO                 = IOMUX_PAD(0x0380, 0x0110, 2, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA18__CSI_DATA15                          = IOMUX_PAD(0x0380, 0x0110, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA18__EIM_CS2_B                           = IOMUX_PAD(0x0380, 0x0110, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA18__GPIO3_IO23                          = IOMUX_PAD(0x0380, 0x0110, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18                      = IOMUX_PAD(0x0380, 0x0110, 6, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA19__EIM_CS3_B                           = IOMUX_PAD(0x0384, 0x0114, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA19__GPIO3_IO24                          = IOMUX_PAD(0x0384, 0x0114, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19                      = IOMUX_PAD(0x0384, 0x0114, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA19__LCD_DATA19                          = IOMUX_PAD(0x0384, 0x0114, 0, 0x0684, 2, 0),
+	MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7                      = IOMUX_PAD(0x0384, 0x0114, 1, 0x05A0, 0, 0),
+	MX7D_PAD_LCD_DATA19__CSI_DATA14                          = IOMUX_PAD(0x0384, 0x0114, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA20__EIM_ADDR23                          = IOMUX_PAD(0x0388, 0x0118, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA20__GPIO3_IO25                          = IOMUX_PAD(0x0388, 0x0118, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA20__I2C3_SCL                            = IOMUX_PAD(0x0388, 0x0118, IOMUX_CONFIG_SION | 6, 0x05E4, 1, 0),
+
+	MX7D_PAD_LCD_DATA20__LCD_DATA20                          = IOMUX_PAD(0x0388, 0x0118, 0, 0x0688, 2, 0),
+	MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4                      = IOMUX_PAD(0x0388, 0x0118, 1, 0x05BC, 0, 0),
+	MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT               = IOMUX_PAD(0x0388, 0x0118, 2, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA20__CSI_DATA13                          = IOMUX_PAD(0x0388, 0x0118, 3, 0x0000, 0, 0),
+
+	MX7D_PAD_LCD_DATA21__LCD_DATA21                          = IOMUX_PAD(0x038C, 0x011C, 0, 0x068C, 2, 0),
+	MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5                      = IOMUX_PAD(0x038C, 0x011C, 1, 0x05C0, 0, 0),
+	MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT               = IOMUX_PAD(0x038C, 0x011C, 2, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA21__CSI_DATA12                          = IOMUX_PAD(0x038C, 0x011C, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA21__EIM_ADDR24                          = IOMUX_PAD(0x038C, 0x011C, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA21__GPIO3_IO26                          = IOMUX_PAD(0x038C, 0x011C, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA21__I2C3_SDA                            = IOMUX_PAD(0x038C, 0x011C, IOMUX_CONFIG_SION | 6, 0x05E8, 1, 0),
+
+	MX7D_PAD_LCD_DATA22__LCD_DATA22                          = IOMUX_PAD(0x0390, 0x0120, 0, 0x0690, 2, 0),
+	MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6                      = IOMUX_PAD(0x0390, 0x0120, 1, 0x05C4, 0, 0),
+	MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT               = IOMUX_PAD(0x0390, 0x0120, 2, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA22__CSI_DATA11                          = IOMUX_PAD(0x0390, 0x0120, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA22__EIM_ADDR25                          = IOMUX_PAD(0x0390, 0x0120, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA22__GPIO3_IO27                          = IOMUX_PAD(0x0390, 0x0120, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA22__I2C4_SCL                            = IOMUX_PAD(0x0390, 0x0120, IOMUX_CONFIG_SION | 6, 0x05EC, 1, 0),
+
+	MX7D_PAD_LCD_DATA23__LCD_DATA23                          = IOMUX_PAD(0x0394, 0x0124, 0, 0x0694, 2, 0),
+	MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7                      = IOMUX_PAD(0x0394, 0x0124, 1, 0x05C8, 0, 0),
+	MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT               = IOMUX_PAD(0x0394, 0x0124, 2, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA23__CSI_DATA10                          = IOMUX_PAD(0x0394, 0x0124, 3, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA23__EIM_ADDR26                          = IOMUX_PAD(0x0394, 0x0124, 4, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA23__GPIO3_IO28                          = IOMUX_PAD(0x0394, 0x0124, 5, 0x0000, 0, 0),
+	MX7D_PAD_LCD_DATA23__I2C4_SDA                            = IOMUX_PAD(0x0394, 0x0124, IOMUX_CONFIG_SION | 6, 0x05F0, 1, 0),
+
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX                     = IOMUX_PAD(0x0398, 0x0128, 0, 0x06F4, 0, 0),
+
+	MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX                     = IOMUX_PAD(0x0398, 0x0128, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART1_RX_DATA__I2C1_SCL                         = IOMUX_PAD(0x0398, 0x0128, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
+	MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY                   = IOMUX_PAD(0x0398, 0x0128, 2, 0x0000, 0, 0),
+	MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1                       = IOMUX_PAD(0x0398, 0x0128, 3, 0x0000, 0, 0),
+	MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN             = IOMUX_PAD(0x0398, 0x0128, 4, 0x0000, 0, 0),
+	MX7D_PAD_UART1_RX_DATA__GPIO4_IO0                        = IOMUX_PAD(0x0398, 0x0128, 5, 0x0000, 0, 0),
+	MX7D_PAD_UART1_RX_DATA__ENET1_MDIO                       = IOMUX_PAD(0x0398, 0x0128, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX                     = IOMUX_PAD(0x039C, 0x012C, 0, 0x0000, 0, 0),
+
+	MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX                     = IOMUX_PAD(0x039C, 0x012C, 0, 0x06F4, 1, 0),
+	MX7D_PAD_UART1_TX_DATA__I2C1_SDA                         = IOMUX_PAD(0x039C, 0x012C, IOMUX_CONFIG_SION | 1, 0x05D8, 0, 0),
+	MX7D_PAD_UART1_TX_DATA__SAI3_MCLK                        = IOMUX_PAD(0x039C, 0x012C, 2, 0x0000, 0, 0),
+	MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2                       = IOMUX_PAD(0x039C, 0x012C, 3, 0x0000, 0, 0),
+	MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT            = IOMUX_PAD(0x039C, 0x012C, 4, 0x0000, 0, 0),
+	MX7D_PAD_UART1_TX_DATA__GPIO4_IO1                        = IOMUX_PAD(0x039C, 0x012C, 5, 0x0000, 0, 0),
+	MX7D_PAD_UART1_TX_DATA__ENET1_MDC                        = IOMUX_PAD(0x039C, 0x012C, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX                     = IOMUX_PAD(0x03A0, 0x0130, 0, 0x06FC, 2, 0),
+
+	MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX                     = IOMUX_PAD(0x03A0, 0x0130, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART2_RX_DATA__I2C2_SCL                         = IOMUX_PAD(0x03A0, 0x0130, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0),
+	MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK                     = IOMUX_PAD(0x03A0, 0x0130, 2, 0x0000, 0, 0),
+	MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3                       = IOMUX_PAD(0x03A0, 0x0130, 3, 0x0000, 0, 0),
+	MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN             = IOMUX_PAD(0x03A0, 0x0130, 4, 0x0000, 0, 0),
+	MX7D_PAD_UART2_RX_DATA__GPIO4_IO2                        = IOMUX_PAD(0x03A0, 0x0130, 5, 0x0000, 0, 0),
+	MX7D_PAD_UART2_RX_DATA__ENET2_MDIO                       = IOMUX_PAD(0x03A0, 0x0130, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX                     = IOMUX_PAD(0x03A4, 0x0134, 0, 0x0000, 0, 0),
+
+	MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX                     = IOMUX_PAD(0x03A4, 0x0134, 0, 0x06FC, 3, 0),
+	MX7D_PAD_UART2_TX_DATA__I2C2_SDA                         = IOMUX_PAD(0x03A4, 0x0134, IOMUX_CONFIG_SION | 1, 0x05E0, 0, 0),
+	MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0                    = IOMUX_PAD(0x03A4, 0x0134, 2, 0x06C8, 0, 0),
+	MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY                       = IOMUX_PAD(0x03A4, 0x0134, 3, 0x0000, 0, 0),
+	MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT            = IOMUX_PAD(0x03A4, 0x0134, 4, 0x0000, 0, 0),
+	MX7D_PAD_UART2_TX_DATA__GPIO4_IO3                        = IOMUX_PAD(0x03A4, 0x0134, 5, 0x0000, 0, 0),
+	MX7D_PAD_UART2_TX_DATA__ENET2_MDC                        = IOMUX_PAD(0x03A4, 0x0134, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX                     = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0704, 2, 0),
+
+	MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX                     = IOMUX_PAD(0x03A8, 0x0138, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC                      = IOMUX_PAD(0x03A8, 0x0138, 1, 0x072C, 0, 0),
+	MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC                     = IOMUX_PAD(0x03A8, 0x0138, 2, 0x06CC, 0, 0),
+	MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO                      = IOMUX_PAD(0x03A8, 0x0138, 3, 0x0528, 0, 0),
+	MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN             = IOMUX_PAD(0x03A8, 0x0138, 4, 0x0000, 0, 0),
+	MX7D_PAD_UART3_RX_DATA__GPIO4_IO4                        = IOMUX_PAD(0x03A8, 0x0138, 5, 0x0000, 0, 0),
+	MX7D_PAD_UART3_RX_DATA__SD1_LCTL                         = IOMUX_PAD(0x03A8, 0x0138, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX                     = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0000, 0, 0),
+
+	MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX                     = IOMUX_PAD(0x03AC, 0x013C, 0, 0x0704, 3, 0),
+	MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR                     = IOMUX_PAD(0x03AC, 0x013C, 1, 0x0000, 0, 0),
+	MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK                     = IOMUX_PAD(0x03AC, 0x013C, 2, 0x06D0, 0, 0),
+	MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI                      = IOMUX_PAD(0x03AC, 0x013C, 3, 0x052C, 0, 0),
+	MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT            = IOMUX_PAD(0x03AC, 0x013C, 4, 0x0000, 0, 0),
+	MX7D_PAD_UART3_TX_DATA__GPIO4_IO5                        = IOMUX_PAD(0x03AC, 0x013C, 5, 0x0000, 0, 0),
+	MX7D_PAD_UART3_TX_DATA__SD2_LCTL                         = IOMUX_PAD(0x03AC, 0x013C, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS                      = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0700, 2, 0),
+
+	MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS                      = IOMUX_PAD(0x03B0, 0x0140, 0, 0x0000, 0, 0),
+	MX7D_PAD_UART3_RTS_B__USB_OTG2_OC                        = IOMUX_PAD(0x03B0, 0x0140, 1, 0x0000, 0, 0),
+	MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0                      = IOMUX_PAD(0x03B0, 0x0140, 2, 0x0000, 0, 0),
+	MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK                        = IOMUX_PAD(0x03B0, 0x0140, 3, 0x0000, 0, 0),
+	MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN               = IOMUX_PAD(0x03B0, 0x0140, 4, 0x0000, 0, 0),
+	MX7D_PAD_UART3_RTS_B__GPIO4_IO6                          = IOMUX_PAD(0x03B0, 0x0140, 5, 0x0000, 0, 0),
+	MX7D_PAD_UART3_RTS_B__SD3_LCTL                           = IOMUX_PAD(0x03B0, 0x0140, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS                      = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0000, 0, 0),
+
+	MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS                      = IOMUX_PAD(0x03B4, 0x0144, 0, 0x0700, 3, 0),
+	MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR                       = IOMUX_PAD(0x03B4, 0x0144, 1, 0x0000, 0, 0),
+	MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC                       = IOMUX_PAD(0x03B4, 0x0144, 2, 0x06D4, 0, 0),
+	MX7D_PAD_UART3_CTS_B__ECSPI1_SS0                         = IOMUX_PAD(0x03B4, 0x0144, 3, 0x0530, 0, 0),
+	MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT              = IOMUX_PAD(0x03B4, 0x0144, 4, 0x0000, 0, 0),
+	MX7D_PAD_UART3_CTS_B__GPIO4_IO7                          = IOMUX_PAD(0x03B4, 0x0144, 5, 0x0000, 0, 0),
+	MX7D_PAD_UART3_CTS_B__SD1_VSELECT                        = IOMUX_PAD(0x03B4, 0x0144, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_I2C1_SCL__I2C1_SCL                              = IOMUX_PAD(0x03B8, 0x0148, IOMUX_CONFIG_SION | 0, 0x05D4, 1, 0),
+	MX7D_PAD_I2C1_SCL__UART4_DCE_CTS                         = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0000, 0, 0),
+	MX7D_PAD_I2C1_SCL__UART4_DTE_RTS                         = IOMUX_PAD(0x03B8, 0x0148, 1, 0x0708, 0, 0),
+	MX7D_PAD_I2C1_SCL__FLEXCAN1_RX                           = IOMUX_PAD(0x03B8, 0x0148, 2, 0x04DC, 1, 0),
+	MX7D_PAD_I2C1_SCL__ECSPI3_MISO                           = IOMUX_PAD(0x03B8, 0x0148, 3, 0x0548, 0, 0),
+	MX7D_PAD_I2C1_SCL__GPIO4_IO8                             = IOMUX_PAD(0x03B8, 0x0148, 5, 0x0000, 0, 0),
+	MX7D_PAD_I2C1_SCL__SD2_VSELECT                           = IOMUX_PAD(0x03B8, 0x0148, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_I2C1_SDA__I2C1_SDA                              = IOMUX_PAD(0x03BC, 0x014C, IOMUX_CONFIG_SION | 0, 0x05D8, 1, 0),
+	MX7D_PAD_I2C1_SDA__UART4_DCE_RTS                         = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0708, 1, 0),
+	MX7D_PAD_I2C1_SDA__UART4_DTE_CTS                         = IOMUX_PAD(0x03BC, 0x014C, 1, 0x0000, 0, 0),
+	MX7D_PAD_I2C1_SDA__FLEXCAN1_TX                           = IOMUX_PAD(0x03BC, 0x014C, 2, 0x0000, 0, 0),
+	MX7D_PAD_I2C1_SDA__ECSPI3_MOSI                           = IOMUX_PAD(0x03BC, 0x014C, 3, 0x054C, 0, 0),
+	MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1                     = IOMUX_PAD(0x03BC, 0x014C, 4, 0x0564, 1, 0),
+	MX7D_PAD_I2C1_SDA__GPIO4_IO9                             = IOMUX_PAD(0x03BC, 0x014C, 5, 0x0000, 0, 0),
+	MX7D_PAD_I2C1_SDA__SD3_VSELECT                           = IOMUX_PAD(0x03BC, 0x014C, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_I2C2_SCL__I2C2_SCL                              = IOMUX_PAD(0x03C0, 0x0150, IOMUX_CONFIG_SION | 0, 0x05DC, 1, 0),
+	MX7D_PAD_I2C2_SCL__UART4_DCE_RX                          = IOMUX_PAD(0x03C0, 0x0150, 1, 0x070C, 0, 0),
+	MX7D_PAD_I2C2_SCL__UART4_DTE_TX                          = IOMUX_PAD(0x03C0, 0x0150, 1, 0x0000, 0, 0),
+	MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B                          = IOMUX_PAD(0x03C0, 0x0150, 2, 0x0000, 0, 0),
+	MX7D_PAD_I2C2_SCL__ECSPI3_SCLK                           = IOMUX_PAD(0x03C0, 0x0150, 3, 0x0544, 0, 0),
+	MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2                     = IOMUX_PAD(0x03C0, 0x0150, 4, 0x0570, 2, 0),
+	MX7D_PAD_I2C2_SCL__GPIO4_IO10                            = IOMUX_PAD(0x03C0, 0x0150, 5, 0x0000, 0, 0),
+	MX7D_PAD_I2C2_SCL__SD3_CD_B                              = IOMUX_PAD(0x03C0, 0x0150, 6, 0x0738, 1, 0),
+
+	MX7D_PAD_I2C2_SDA__I2C2_SDA                              = IOMUX_PAD(0x03C4, 0x0154, IOMUX_CONFIG_SION | 0, 0x05E0, 1, 0),
+	MX7D_PAD_I2C2_SDA__UART4_DCE_TX                          = IOMUX_PAD(0x03C4, 0x0154, 1, 0x0000, 0, 0),
+	MX7D_PAD_I2C2_SDA__UART4_DTE_RX                          = IOMUX_PAD(0x03C4, 0x0154, 1, 0x070C, 1, 0),
+	MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB                  = IOMUX_PAD(0x03C4, 0x0154, 2, 0x0000, 0, 0),
+	MX7D_PAD_I2C2_SDA__ECSPI3_SS0                            = IOMUX_PAD(0x03C4, 0x0154, 3, 0x0550, 0, 0),
+	MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3                     = IOMUX_PAD(0x03C4, 0x0154, 4, 0x0000, 0, 0),
+	MX7D_PAD_I2C2_SDA__GPIO4_IO11                            = IOMUX_PAD(0x03C4, 0x0154, 5, 0x0000, 0, 0),
+	MX7D_PAD_I2C2_SDA__SD3_WP                                = IOMUX_PAD(0x03C4, 0x0154, 6, 0x073C, 1, 0),
+
+	MX7D_PAD_I2C3_SCL__I2C3_SCL                              = IOMUX_PAD(0x03C8, 0x0158, IOMUX_CONFIG_SION | 0, 0x05E4, 2, 0),
+	MX7D_PAD_I2C3_SCL__UART5_DCE_CTS                         = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0000, 0, 0),
+	MX7D_PAD_I2C3_SCL__UART5_DTE_RTS                         = IOMUX_PAD(0x03C8, 0x0158, 1, 0x0710, 0, 0),
+	MX7D_PAD_I2C3_SCL__FLEXCAN2_RX                           = IOMUX_PAD(0x03C8, 0x0158, 2, 0x04E0, 1, 0),
+	MX7D_PAD_I2C3_SCL__CSI_VSYNC                             = IOMUX_PAD(0x03C8, 0x0158, 3, 0x0520, 1, 0),
+	MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0                       = IOMUX_PAD(0x03C8, 0x0158, 4, 0x06D8, 1, 0),
+	MX7D_PAD_I2C3_SCL__GPIO4_IO12                            = IOMUX_PAD(0x03C8, 0x0158, 5, 0x0000, 0, 0),
+	MX7D_PAD_I2C3_SCL__EPDC_BDR0                             = IOMUX_PAD(0x03C8, 0x0158, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_I2C3_SDA__I2C3_SDA                              = IOMUX_PAD(0x03CC, 0x015C, IOMUX_CONFIG_SION | 0, 0x05E8, 2, 0),
+	MX7D_PAD_I2C3_SDA__UART5_DCE_RTS                         = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0710, 1, 0),
+	MX7D_PAD_I2C3_SDA__UART5_DTE_CTS                         = IOMUX_PAD(0x03CC, 0x015C, 1, 0x0000, 0, 0),
+	MX7D_PAD_I2C3_SDA__FLEXCAN2_TX                           = IOMUX_PAD(0x03CC, 0x015C, 2, 0x0000, 0, 0),
+	MX7D_PAD_I2C3_SDA__CSI_HSYNC                             = IOMUX_PAD(0x03CC, 0x015C, 3, 0x0518, 1, 0),
+	MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1                       = IOMUX_PAD(0x03CC, 0x015C, 4, 0x06DC, 1, 0),
+	MX7D_PAD_I2C3_SDA__GPIO4_IO13                            = IOMUX_PAD(0x03CC, 0x015C, 5, 0x0000, 0, 0),
+	MX7D_PAD_I2C3_SDA__EPDC_BDR1                             = IOMUX_PAD(0x03CC, 0x015C, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_I2C4_SCL__I2C4_SCL                              = IOMUX_PAD(0x03D0, 0x0160, IOMUX_CONFIG_SION | 0, 0x05EC, 2, 0),
+	MX7D_PAD_I2C4_SCL__UART5_DCE_RX                          = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0714, 0, 0),
+	MX7D_PAD_I2C4_SCL__UART5_DTE_TX                          = IOMUX_PAD(0x03D0, 0x0160, 1, 0x0000, 0, 0),
+	MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B                          = IOMUX_PAD(0x03D0, 0x0160, 2, 0x0000, 0, 0),
+	MX7D_PAD_I2C4_SCL__CSI_PIXCLK                            = IOMUX_PAD(0x03D0, 0x0160, 3, 0x051C, 1, 0),
+	MX7D_PAD_I2C4_SCL__USB_OTG1_ID                           = IOMUX_PAD(0x03D0, 0x0160, 4, 0x0734, 1, 0),
+	MX7D_PAD_I2C4_SCL__GPIO4_IO14                            = IOMUX_PAD(0x03D0, 0x0160, 5, 0x0000, 0, 0),
+	MX7D_PAD_I2C4_SCL__EPDC_VCOM0                            = IOMUX_PAD(0x03D0, 0x0160, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_I2C4_SDA__I2C4_SDA                              = IOMUX_PAD(0x03D4, 0x0164, IOMUX_CONFIG_SION | 0, 0x05F0, 2, 0),
+	MX7D_PAD_I2C4_SDA__UART5_DCE_TX                          = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0000, 0, 0),
+	MX7D_PAD_I2C4_SDA__UART5_DTE_RX                          = IOMUX_PAD(0x03D4, 0x0164, 1, 0x0714, 1, 0),
+	MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB                  = IOMUX_PAD(0x03D4, 0x0164, 2, 0x0000, 0, 0),
+	MX7D_PAD_I2C4_SDA__CSI_MCLK                              = IOMUX_PAD(0x03D4, 0x0164, 3, 0x0000, 0, 0),
+	MX7D_PAD_I2C4_SDA__USB_OTG2_ID                           = IOMUX_PAD(0x03D4, 0x0164, 4, 0x0730, 1, 0),
+	MX7D_PAD_I2C4_SDA__GPIO4_IO15                            = IOMUX_PAD(0x03D4, 0x0164, 5, 0x0000, 0, 0),
+	MX7D_PAD_I2C4_SDA__EPDC_VCOM1                            = IOMUX_PAD(0x03D4, 0x0164, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK                        = IOMUX_PAD(0x03D8, 0x0168, 0, 0x0524, 1, 0),
+	MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX                       = IOMUX_PAD(0x03D8, 0x0168, 1, 0x071C, 2, 0),
+	MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX                       = IOMUX_PAD(0x03D8, 0x0168, 1, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_SCLK__SD2_DATA4                          = IOMUX_PAD(0x03D8, 0x0168, 2, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_SCLK__CSI_DATA2                          = IOMUX_PAD(0x03D8, 0x0168, 3, 0x04F8, 1, 0),
+	MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16                         = IOMUX_PAD(0x03D8, 0x0168, 5, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM                       = IOMUX_PAD(0x03D8, 0x0168, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI                        = IOMUX_PAD(0x03DC, 0x016C, 0, 0x052C, 1, 0),
+	MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX                       = IOMUX_PAD(0x03DC, 0x016C, 1, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX                       = IOMUX_PAD(0x03DC, 0x016C, 1, 0x071C, 3, 0),
+	MX7D_PAD_ECSPI1_MOSI__SD2_DATA5                          = IOMUX_PAD(0x03DC, 0x016C, 2, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_MOSI__CSI_DATA3                          = IOMUX_PAD(0x03DC, 0x016C, 3, 0x04FC, 1, 0),
+	MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17                         = IOMUX_PAD(0x03DC, 0x016C, 5, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT                      = IOMUX_PAD(0x03DC, 0x016C, 6, 0x0580, 1, 0),
+
+	MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO                        = IOMUX_PAD(0x03E0, 0x0170, 0, 0x0528, 1, 0),
+	MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS                      = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0718, 2, 0),
+	MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS                      = IOMUX_PAD(0x03E0, 0x0170, 1, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_MISO__SD2_DATA6                          = IOMUX_PAD(0x03E0, 0x0170, 2, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_MISO__CSI_DATA4                          = IOMUX_PAD(0x03E0, 0x0170, 3, 0x0500, 1, 0),
+	MX7D_PAD_ECSPI1_MISO__GPIO4_IO18                         = IOMUX_PAD(0x03E0, 0x0170, 5, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ                       = IOMUX_PAD(0x03E0, 0x0170, 6, 0x057C, 0, 0),
+
+	MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0                          = IOMUX_PAD(0x03E4, 0x0174, 0, 0x0530, 1, 0),
+	MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS                       = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS                       = IOMUX_PAD(0x03E4, 0x0174, 1, 0x0718, 3, 0),
+	MX7D_PAD_ECSPI1_SS0__SD2_DATA7                           = IOMUX_PAD(0x03E4, 0x0174, 2, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_SS0__CSI_DATA5                           = IOMUX_PAD(0x03E4, 0x0174, 3, 0x0504, 1, 0),
+	MX7D_PAD_ECSPI1_SS0__GPIO4_IO19                          = IOMUX_PAD(0x03E4, 0x0174, 5, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3                      = IOMUX_PAD(0x03E4, 0x0174, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK                        = IOMUX_PAD(0x03E8, 0x0178, 0, 0x0534, 0, 0),
+	MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX                       = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0724, 2, 0),
+	MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX                       = IOMUX_PAD(0x03E8, 0x0178, 1, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_SCLK__SD1_DATA4                          = IOMUX_PAD(0x03E8, 0x0178, 2, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_SCLK__CSI_DATA6                          = IOMUX_PAD(0x03E8, 0x0178, 3, 0x0508, 1, 0),
+	MX7D_PAD_ECSPI2_SCLK__LCD_DATA13                         = IOMUX_PAD(0x03E8, 0x0178, 4, 0x066C, 2, 0),
+	MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20                         = IOMUX_PAD(0x03E8, 0x0178, 5, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0                     = IOMUX_PAD(0x03E8, 0x0178, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI                        = IOMUX_PAD(0x03EC, 0x017C, 0, 0x053C, 0, 0),
+	MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX                       = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX                       = IOMUX_PAD(0x03EC, 0x017C, 1, 0x0724, 3, 0),
+	MX7D_PAD_ECSPI2_MOSI__SD1_DATA5                          = IOMUX_PAD(0x03EC, 0x017C, 2, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_MOSI__CSI_DATA7                          = IOMUX_PAD(0x03EC, 0x017C, 3, 0x050C, 1, 0),
+	MX7D_PAD_ECSPI2_MOSI__LCD_DATA14                         = IOMUX_PAD(0x03EC, 0x017C, 4, 0x0670, 2, 0),
+	MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21                         = IOMUX_PAD(0x03EC, 0x017C, 5, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1                     = IOMUX_PAD(0x03EC, 0x017C, 6, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_MISO__GPIO4_IO22                         = IOMUX_PAD(0x03F0, 0x0180, 5, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2                     = IOMUX_PAD(0x03F0, 0x0180, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO                        = IOMUX_PAD(0x03F0, 0x0180, 0, 0x0538, 0, 0),
+	MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS                      = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0720, 2, 0),
+	MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS                      = IOMUX_PAD(0x03F0, 0x0180, 1, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_MISO__SD1_DATA6                          = IOMUX_PAD(0x03F0, 0x0180, 2, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_MISO__CSI_DATA8                          = IOMUX_PAD(0x03F0, 0x0180, 3, 0x0510, 1, 0),
+	MX7D_PAD_ECSPI2_MISO__LCD_DATA15                         = IOMUX_PAD(0x03F0, 0x0180, 4, 0x0674, 2, 0),
+
+	MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0                          = IOMUX_PAD(0x03F4, 0x0184, 0, 0x0540, 0, 0),
+	MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS                       = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS                       = IOMUX_PAD(0x03F4, 0x0184, 1, 0x0720, 3, 0),
+	MX7D_PAD_ECSPI2_SS0__SD1_DATA7                           = IOMUX_PAD(0x03F4, 0x0184, 2, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_SS0__CSI_DATA9                           = IOMUX_PAD(0x03F4, 0x0184, 3, 0x0514, 1, 0),
+	MX7D_PAD_ECSPI2_SS0__LCD_RESET                           = IOMUX_PAD(0x03F4, 0x0184, 4, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_SS0__GPIO4_IO23                          = IOMUX_PAD(0x03F4, 0x0184, 5, 0x0000, 0, 0),
+	MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE                       = IOMUX_PAD(0x03F4, 0x0184, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_SD1_CD_B__SD1_CD_B                              = IOMUX_PAD(0x03F8, 0x0188, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD1_CD_B__UART6_DCE_RX                          = IOMUX_PAD(0x03F8, 0x0188, 2, 0x071C, 4, 0),
+	MX7D_PAD_SD1_CD_B__UART6_DTE_TX                          = IOMUX_PAD(0x03F8, 0x0188, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD1_CD_B__ECSPI4_MISO                           = IOMUX_PAD(0x03F8, 0x0188, 3, 0x0558, 1, 0),
+	MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0                        = IOMUX_PAD(0x03F8, 0x0188, 4, 0x0584, 1, 0),
+	MX7D_PAD_SD1_CD_B__GPIO5_IO0                             = IOMUX_PAD(0x03F8, 0x0188, 5, 0x0000, 0, 0),
+	MX7D_PAD_SD1_CD_B__CCM_CLKO1                             = IOMUX_PAD(0x03F8, 0x0188, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_SD1_WP__SD1_WP                                  = IOMUX_PAD(0x03FC, 0x018C, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD1_WP__UART6_DCE_TX                            = IOMUX_PAD(0x03FC, 0x018C, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD1_WP__UART6_DTE_RX                            = IOMUX_PAD(0x03FC, 0x018C, 2, 0x071C, 5, 0),
+	MX7D_PAD_SD1_WP__ECSPI4_MOSI                             = IOMUX_PAD(0x03FC, 0x018C, 3, 0x055C, 1, 0),
+	MX7D_PAD_SD1_WP__FLEXTIMER1_CH1                          = IOMUX_PAD(0x03FC, 0x018C, 4, 0x0588, 1, 0),
+	MX7D_PAD_SD1_WP__GPIO5_IO1                               = IOMUX_PAD(0x03FC, 0x018C, 5, 0x0000, 0, 0),
+	MX7D_PAD_SD1_WP__CCM_CLKO2                               = IOMUX_PAD(0x03FC, 0x018C, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_SD1_RESET_B__SD1_RESET_B                        = IOMUX_PAD(0x0400, 0x0190, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD1_RESET_B__SAI3_MCLK                          = IOMUX_PAD(0x0400, 0x0190, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS                      = IOMUX_PAD(0x0400, 0x0190, 2, 0x0718, 4, 0),
+	MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS                      = IOMUX_PAD(0x0400, 0x0190, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK                        = IOMUX_PAD(0x0400, 0x0190, 3, 0x0554, 1, 0),
+	MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2                     = IOMUX_PAD(0x0400, 0x0190, 4, 0x058C, 1, 0),
+	MX7D_PAD_SD1_RESET_B__GPIO5_IO2                          = IOMUX_PAD(0x0400, 0x0190, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD1_CLK__SD1_CLK                                = IOMUX_PAD(0x0404, 0x0194, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD1_CLK__SAI3_RX_SYNC                           = IOMUX_PAD(0x0404, 0x0194, 1, 0x06CC, 1, 0),
+	MX7D_PAD_SD1_CLK__UART6_DCE_CTS                          = IOMUX_PAD(0x0404, 0x0194, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD1_CLK__UART6_DTE_RTS                          = IOMUX_PAD(0x0404, 0x0194, 2, 0x0718, 5, 0),
+	MX7D_PAD_SD1_CLK__ECSPI4_SS0                             = IOMUX_PAD(0x0404, 0x0194, 3, 0x0560, 1, 0),
+	MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3                         = IOMUX_PAD(0x0404, 0x0194, 4, 0x0590, 1, 0),
+	MX7D_PAD_SD1_CLK__GPIO5_IO3                              = IOMUX_PAD(0x0404, 0x0194, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD1_CMD__SD1_CMD                                = IOMUX_PAD(0x0408, 0x0198, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD1_CMD__SAI3_RX_BCLK                           = IOMUX_PAD(0x0408, 0x0198, 1, 0x06C4, 1, 0),
+	MX7D_PAD_SD1_CMD__ECSPI4_SS1                             = IOMUX_PAD(0x0408, 0x0198, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0                         = IOMUX_PAD(0x0408, 0x0198, 4, 0x05AC, 1, 0),
+	MX7D_PAD_SD1_CMD__GPIO5_IO4                              = IOMUX_PAD(0x0408, 0x0198, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD1_DATA0__SD1_DATA0                            = IOMUX_PAD(0x040C, 0x019C, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0                        = IOMUX_PAD(0x040C, 0x019C, 1, 0x06C8, 1, 0),
+	MX7D_PAD_SD1_DATA0__UART7_DCE_RX                         = IOMUX_PAD(0x040C, 0x019C, 2, 0x0724, 4, 0),
+	MX7D_PAD_SD1_DATA0__UART7_DTE_TX                         = IOMUX_PAD(0x040C, 0x019C, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA0__ECSPI4_SS2                           = IOMUX_PAD(0x040C, 0x019C, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1                       = IOMUX_PAD(0x040C, 0x019C, 4, 0x05B0, 1, 0),
+	MX7D_PAD_SD1_DATA0__GPIO5_IO5                            = IOMUX_PAD(0x040C, 0x019C, 5, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1                         = IOMUX_PAD(0x040C, 0x019C, 6, 0x04E4, 1, 0),
+
+	MX7D_PAD_SD1_DATA1__SD1_DATA1                            = IOMUX_PAD(0x0410, 0x01A0, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK                         = IOMUX_PAD(0x0410, 0x01A0, 1, 0x06D0, 1, 0),
+	MX7D_PAD_SD1_DATA1__UART7_DCE_TX                         = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA1__UART7_DTE_RX                         = IOMUX_PAD(0x0410, 0x01A0, 2, 0x0724, 5, 0),
+	MX7D_PAD_SD1_DATA1__ECSPI4_SS3                           = IOMUX_PAD(0x0410, 0x01A0, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2                       = IOMUX_PAD(0x0410, 0x01A0, 4, 0x05B4, 1, 0),
+	MX7D_PAD_SD1_DATA1__GPIO5_IO6                            = IOMUX_PAD(0x0410, 0x01A0, 5, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2                         = IOMUX_PAD(0x0410, 0x01A0, 6, 0x04E8, 1, 0),
+
+	MX7D_PAD_SD1_DATA2__SD1_DATA2                            = IOMUX_PAD(0x0414, 0x01A4, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC                         = IOMUX_PAD(0x0414, 0x01A4, 1, 0x06D4, 1, 0),
+	MX7D_PAD_SD1_DATA2__UART7_DCE_CTS                        = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA2__UART7_DTE_RTS                        = IOMUX_PAD(0x0414, 0x01A4, 2, 0x0720, 4, 0),
+	MX7D_PAD_SD1_DATA2__ECSPI4_RDY                           = IOMUX_PAD(0x0414, 0x01A4, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3                       = IOMUX_PAD(0x0414, 0x01A4, 4, 0x05B8, 1, 0),
+	MX7D_PAD_SD1_DATA2__GPIO5_IO7                            = IOMUX_PAD(0x0414, 0x01A4, 5, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3                         = IOMUX_PAD(0x0414, 0x01A4, 6, 0x04EC, 1, 0),
+
+	MX7D_PAD_SD1_DATA3__SD1_DATA3                            = IOMUX_PAD(0x0418, 0x01A8, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0                        = IOMUX_PAD(0x0418, 0x01A8, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA3__UART7_DCE_RTS                        = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0720, 5, 0),
+	MX7D_PAD_SD1_DATA3__UART7_DTE_CTS                        = IOMUX_PAD(0x0418, 0x01A8, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA3__ECSPI3_SS1                           = IOMUX_PAD(0x0418, 0x01A8, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA                       = IOMUX_PAD(0x0418, 0x01A8, 4, 0x05A4, 1, 0),
+	MX7D_PAD_SD1_DATA3__GPIO5_IO8                            = IOMUX_PAD(0x0418, 0x01A8, 5, 0x0000, 0, 0),
+	MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4                         = IOMUX_PAD(0x0418, 0x01A8, 6, 0x04F0, 1, 0),
+
+	MX7D_PAD_SD2_CD_B__SD2_CD_B                              = IOMUX_PAD(0x041C, 0x01AC, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD2_CD_B__ENET1_MDIO                            = IOMUX_PAD(0x041C, 0x01AC, 1, 0x0568, 2, 0),
+	MX7D_PAD_SD2_CD_B__ENET2_MDIO                            = IOMUX_PAD(0x041C, 0x01AC, 2, 0x0574, 2, 0),
+	MX7D_PAD_SD2_CD_B__ECSPI3_SS2                            = IOMUX_PAD(0x041C, 0x01AC, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB                        = IOMUX_PAD(0x041C, 0x01AC, 4, 0x05A8, 1, 0),
+	MX7D_PAD_SD2_CD_B__GPIO5_IO9                             = IOMUX_PAD(0x041C, 0x01AC, 5, 0x0000, 0, 0),
+	MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0                       = IOMUX_PAD(0x041C, 0x01AC, 6, 0x06D8, 2, 0),
+
+	MX7D_PAD_SD2_WP__SD2_WP                                  = IOMUX_PAD(0x0420, 0x01B0, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD2_WP__ENET1_MDC                               = IOMUX_PAD(0x0420, 0x01B0, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD2_WP__ENET2_MDC                               = IOMUX_PAD(0x0420, 0x01B0, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD2_WP__ECSPI3_SS3                              = IOMUX_PAD(0x0420, 0x01B0, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD2_WP__USB_OTG1_ID                             = IOMUX_PAD(0x0420, 0x01B0, 4, 0x0734, 2, 0),
+	MX7D_PAD_SD2_WP__GPIO5_IO10                              = IOMUX_PAD(0x0420, 0x01B0, 5, 0x0000, 0, 0),
+	MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1                         = IOMUX_PAD(0x0420, 0x01B0, 6, 0x06DC, 2, 0),
+
+	MX7D_PAD_SD2_RESET_B__SD2_RESET_B                        = IOMUX_PAD(0x0424, 0x01B4, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD2_RESET_B__SAI2_MCLK                          = IOMUX_PAD(0x0424, 0x01B4, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD2_RESET_B__SD2_RESET                          = IOMUX_PAD(0x0424, 0x01B4, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD2_RESET_B__ECSPI3_RDY                         = IOMUX_PAD(0x0424, 0x01B4, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD2_RESET_B__USB_OTG2_ID                        = IOMUX_PAD(0x0424, 0x01B4, 4, 0x0730, 2, 0),
+	MX7D_PAD_SD2_RESET_B__GPIO5_IO11                         = IOMUX_PAD(0x0424, 0x01B4, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD2_CLK__SD2_CLK                                = IOMUX_PAD(0x0428, 0x01B8, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD2_CLK__SAI2_RX_SYNC                           = IOMUX_PAD(0x0428, 0x01B8, 1, 0x06B8, 0, 0),
+	MX7D_PAD_SD2_CLK__MQS_RIGHT                              = IOMUX_PAD(0x0428, 0x01B8, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD2_CLK__GPT4_CLK                               = IOMUX_PAD(0x0428, 0x01B8, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD2_CLK__GPIO5_IO12                             = IOMUX_PAD(0x0428, 0x01B8, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD2_CMD__SD2_CMD                                = IOMUX_PAD(0x042C, 0x01BC, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD2_CMD__SAI2_RX_BCLK                           = IOMUX_PAD(0x042C, 0x01BC, 1, 0x06B0, 0, 0),
+	MX7D_PAD_SD2_CMD__MQS_LEFT                               = IOMUX_PAD(0x042C, 0x01BC, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD2_CMD__GPT4_CAPTURE1                          = IOMUX_PAD(0x042C, 0x01BC, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD                        = IOMUX_PAD(0x042C, 0x01BC, 4, 0x06EC, 1, 0),
+	MX7D_PAD_SD2_CMD__GPIO5_IO13                             = IOMUX_PAD(0x042C, 0x01BC, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD2_DATA0__SD2_DATA0                            = IOMUX_PAD(0x0430, 0x01C0, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0                        = IOMUX_PAD(0x0430, 0x01C0, 1, 0x06B4, 0, 0),
+	MX7D_PAD_SD2_DATA0__UART4_DCE_RX                         = IOMUX_PAD(0x0430, 0x01C0, 2, 0x070C, 2, 0),
+	MX7D_PAD_SD2_DATA0__UART4_DTE_TX                         = IOMUX_PAD(0x0430, 0x01C0, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2                        = IOMUX_PAD(0x0430, 0x01C0, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK                       = IOMUX_PAD(0x0430, 0x01C0, 4, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA0__GPIO5_IO14                           = IOMUX_PAD(0x0430, 0x01C0, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD2_DATA1__SD2_DATA1                            = IOMUX_PAD(0x0434, 0x01C4, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK                         = IOMUX_PAD(0x0434, 0x01C4, 1, 0x06BC, 0, 0),
+	MX7D_PAD_SD2_DATA1__UART4_DCE_TX                         = IOMUX_PAD(0x0434, 0x01C4, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA1__UART4_DTE_RX                         = IOMUX_PAD(0x0434, 0x01C4, 2, 0x070C, 3, 0),
+	MX7D_PAD_SD2_DATA1__GPT4_COMPARE1                        = IOMUX_PAD(0x0434, 0x01C4, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B                     = IOMUX_PAD(0x0434, 0x01C4, 4, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA1__GPIO5_IO15                           = IOMUX_PAD(0x0434, 0x01C4, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD2_DATA2__SD2_DATA2                            = IOMUX_PAD(0x0438, 0x01C8, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC                         = IOMUX_PAD(0x0438, 0x01C8, 1, 0x06C0, 0, 0),
+	MX7D_PAD_SD2_DATA2__UART4_DCE_CTS                        = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA2__UART4_DTE_RTS                        = IOMUX_PAD(0x0438, 0x01C8, 2, 0x0708, 2, 0),
+	MX7D_PAD_SD2_DATA2__GPT4_COMPARE2                        = IOMUX_PAD(0x0438, 0x01C8, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN                      = IOMUX_PAD(0x0438, 0x01C8, 4, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA2__GPIO5_IO16                           = IOMUX_PAD(0x0438, 0x01C8, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD2_DATA3__SD2_DATA3                            = IOMUX_PAD(0x043C, 0x01CC, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0                        = IOMUX_PAD(0x043C, 0x01CC, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA3__UART4_DCE_RTS                        = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0708, 3, 0),
+	MX7D_PAD_SD2_DATA3__UART4_DTE_CTS                        = IOMUX_PAD(0x043C, 0x01CC, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA3__GPT4_COMPARE3                        = IOMUX_PAD(0x043C, 0x01CC, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD                        = IOMUX_PAD(0x043C, 0x01CC, 4, 0x06E8, 1, 0),
+	MX7D_PAD_SD2_DATA3__GPIO5_IO17                           = IOMUX_PAD(0x043C, 0x01CC, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_CLK__SD3_CLK                                = IOMUX_PAD(0x0440, 0x01D0, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_CLK__NAND_CLE                               = IOMUX_PAD(0x0440, 0x01D0, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_CLK__ECSPI4_MISO                            = IOMUX_PAD(0x0440, 0x01D0, 2, 0x0558, 2, 0),
+	MX7D_PAD_SD3_CLK__SAI3_RX_SYNC                           = IOMUX_PAD(0x0440, 0x01D0, 3, 0x06CC, 2, 0),
+	MX7D_PAD_SD3_CLK__GPT3_CLK                               = IOMUX_PAD(0x0440, 0x01D0, 4, 0x0000, 0, 0),
+	MX7D_PAD_SD3_CLK__GPIO6_IO0                              = IOMUX_PAD(0x0440, 0x01D0, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_CMD__SD3_CMD                                = IOMUX_PAD(0x0444, 0x01D4, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_CMD__NAND_ALE                               = IOMUX_PAD(0x0444, 0x01D4, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_CMD__ECSPI4_MOSI                            = IOMUX_PAD(0x0444, 0x01D4, 2, 0x055C, 2, 0),
+	MX7D_PAD_SD3_CMD__SAI3_RX_BCLK                           = IOMUX_PAD(0x0444, 0x01D4, 3, 0x06C4, 2, 0),
+	MX7D_PAD_SD3_CMD__GPT3_CAPTURE1                          = IOMUX_PAD(0x0444, 0x01D4, 4, 0x0000, 0, 0),
+	MX7D_PAD_SD3_CMD__GPIO6_IO1                              = IOMUX_PAD(0x0444, 0x01D4, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_DATA0__SD3_DATA0                            = IOMUX_PAD(0x0448, 0x01D8, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA0__NAND_DATA00                          = IOMUX_PAD(0x0448, 0x01D8, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA0__ECSPI4_SS0                           = IOMUX_PAD(0x0448, 0x01D8, 2, 0x0560, 2, 0),
+	MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0                        = IOMUX_PAD(0x0448, 0x01D8, 3, 0x06C8, 2, 0),
+	MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2                        = IOMUX_PAD(0x0448, 0x01D8, 4, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA0__GPIO6_IO2                            = IOMUX_PAD(0x0448, 0x01D8, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_DATA1__SD3_DATA1                            = IOMUX_PAD(0x044C, 0x01DC, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA1__NAND_DATA01                          = IOMUX_PAD(0x044C, 0x01DC, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA1__ECSPI4_SCLK                          = IOMUX_PAD(0x044C, 0x01DC, 2, 0x0554, 2, 0),
+	MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK                         = IOMUX_PAD(0x044C, 0x01DC, 3, 0x06D0, 2, 0),
+	MX7D_PAD_SD3_DATA1__GPT3_COMPARE1                        = IOMUX_PAD(0x044C, 0x01DC, 4, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA1__GPIO6_IO3                            = IOMUX_PAD(0x044C, 0x01DC, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_DATA2__SD3_DATA2                            = IOMUX_PAD(0x0450, 0x01E0, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA2__NAND_DATA02                          = IOMUX_PAD(0x0450, 0x01E0, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA2__I2C3_SDA                             = IOMUX_PAD(0x0450, 0x01E0, IOMUX_CONFIG_SION | 2, 0x05E8, 3, 0),
+	MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC                         = IOMUX_PAD(0x0450, 0x01E0, 3, 0x06D4, 2, 0),
+	MX7D_PAD_SD3_DATA2__GPT3_COMPARE2                        = IOMUX_PAD(0x0450, 0x01E0, 4, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA2__GPIO6_IO4                            = IOMUX_PAD(0x0450, 0x01E0, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_DATA3__SD3_DATA3                            = IOMUX_PAD(0x0454, 0x01E4, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA3__NAND_DATA03                          = IOMUX_PAD(0x0454, 0x01E4, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA3__I2C3_SCL                             = IOMUX_PAD(0x0454, 0x01E4, IOMUX_CONFIG_SION | 2, 0x05E4, 3, 0),
+	MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0                        = IOMUX_PAD(0x0454, 0x01E4, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA3__GPT3_COMPARE3                        = IOMUX_PAD(0x0454, 0x01E4, 4, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA3__GPIO6_IO5                            = IOMUX_PAD(0x0454, 0x01E4, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_DATA4__SD3_DATA4                            = IOMUX_PAD(0x0458, 0x01E8, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA4__NAND_DATA04                          = IOMUX_PAD(0x0458, 0x01E8, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA4__UART3_DCE_RX                         = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0704, 4, 0),
+	MX7D_PAD_SD3_DATA4__UART3_DTE_TX                         = IOMUX_PAD(0x0458, 0x01E8, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA4__FLEXCAN2_RX                          = IOMUX_PAD(0x0458, 0x01E8, 4, 0x04E0, 2, 0),
+	MX7D_PAD_SD3_DATA4__GPIO6_IO6                            = IOMUX_PAD(0x0458, 0x01E8, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_DATA5__SD3_DATA5                            = IOMUX_PAD(0x045C, 0x01EC, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA5__NAND_DATA05                          = IOMUX_PAD(0x045C, 0x01EC, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA5__UART3_DCE_TX                         = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA5__UART3_DTE_RX                         = IOMUX_PAD(0x045C, 0x01EC, 3, 0x0704, 5, 0),
+	MX7D_PAD_SD3_DATA5__FLEXCAN1_TX                          = IOMUX_PAD(0x045C, 0x01EC, 4, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA5__GPIO6_IO7                            = IOMUX_PAD(0x045C, 0x01EC, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_DATA6__SD3_DATA6                            = IOMUX_PAD(0x0460, 0x01F0, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA6__NAND_DATA06                          = IOMUX_PAD(0x0460, 0x01F0, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA6__SD3_WP                               = IOMUX_PAD(0x0460, 0x01F0, 2, 0x073C, 2, 0),
+	MX7D_PAD_SD3_DATA6__UART3_DCE_RTS                        = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0700, 4, 0),
+	MX7D_PAD_SD3_DATA6__UART3_DTE_CTS                        = IOMUX_PAD(0x0460, 0x01F0, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA6__FLEXCAN2_TX                          = IOMUX_PAD(0x0460, 0x01F0, 4, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA6__GPIO6_IO8                            = IOMUX_PAD(0x0460, 0x01F0, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_DATA7__SD3_DATA7                            = IOMUX_PAD(0x0464, 0x01F4, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA7__NAND_DATA07                          = IOMUX_PAD(0x0464, 0x01F4, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA7__SD3_CD_B                             = IOMUX_PAD(0x0464, 0x01F4, 2, 0x0738, 2, 0),
+	MX7D_PAD_SD3_DATA7__UART3_DCE_CTS                        = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD3_DATA7__UART3_DTE_RTS                        = IOMUX_PAD(0x0464, 0x01F4, 3, 0x0700, 5, 0),
+	MX7D_PAD_SD3_DATA7__FLEXCAN1_RX                          = IOMUX_PAD(0x0464, 0x01F4, 4, 0x04DC, 2, 0),
+	MX7D_PAD_SD3_DATA7__GPIO6_IO9                            = IOMUX_PAD(0x0464, 0x01F4, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_STROBE__SD3_STROBE                          = IOMUX_PAD(0x0468, 0x01F8, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_STROBE__NAND_RE_B                           = IOMUX_PAD(0x0468, 0x01F8, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_STROBE__GPIO6_IO10                          = IOMUX_PAD(0x0468, 0x01F8, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SD3_RESET_B__SD3_RESET_B                        = IOMUX_PAD(0x046C, 0x01FC, 0, 0x0000, 0, 0),
+	MX7D_PAD_SD3_RESET_B__NAND_WE_B                          = IOMUX_PAD(0x046C, 0x01FC, 1, 0x0000, 0, 0),
+	MX7D_PAD_SD3_RESET_B__SD3_RESET                          = IOMUX_PAD(0x046C, 0x01FC, 2, 0x0000, 0, 0),
+	MX7D_PAD_SD3_RESET_B__SAI3_MCLK                          = IOMUX_PAD(0x046C, 0x01FC, 3, 0x0000, 0, 0),
+	MX7D_PAD_SD3_RESET_B__GPIO6_IO11                         = IOMUX_PAD(0x046C, 0x01FC, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0                     = IOMUX_PAD(0x0470, 0x0200, 0, 0x06A0, 0, 0),
+	MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B                        = IOMUX_PAD(0x0470, 0x0200, 1, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX                      = IOMUX_PAD(0x0470, 0x0200, 2, 0x0714, 2, 0),
+	MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX                      = IOMUX_PAD(0x0470, 0x0200, 2, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX                       = IOMUX_PAD(0x0470, 0x0200, 3, 0x04DC, 3, 0),
+	MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD                   = IOMUX_PAD(0x0470, 0x0200, 4, 0x06E4, 1, 0),
+	MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12                        = IOMUX_PAD(0x0470, 0x0200, 5, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET                  = IOMUX_PAD(0x0470, 0x0200, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK                      = IOMUX_PAD(0x0474, 0x0204, 0, 0x06A8, 0, 0),
+	MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B                        = IOMUX_PAD(0x0474, 0x0204, 1, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX                      = IOMUX_PAD(0x0474, 0x0204, 2, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX                      = IOMUX_PAD(0x0474, 0x0204, 2, 0x0714, 3, 0),
+	MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX                       = IOMUX_PAD(0x0474, 0x0204, 3, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK                    = IOMUX_PAD(0x0474, 0x0204, 4, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13                        = IOMUX_PAD(0x0474, 0x0204, 5, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET                   = IOMUX_PAD(0x0474, 0x0204, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC                      = IOMUX_PAD(0x0478, 0x0208, 0, 0x06AC, 0, 0),
+	MX7D_PAD_SAI1_TX_SYNC__NAND_DQS                          = IOMUX_PAD(0x0478, 0x0208, 1, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS                     = IOMUX_PAD(0x0478, 0x0208, 2, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS                     = IOMUX_PAD(0x0478, 0x0208, 2, 0x0710, 2, 0),
+	MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX                       = IOMUX_PAD(0x0478, 0x0208, 3, 0x04E0, 3, 0),
+	MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B                  = IOMUX_PAD(0x0478, 0x0208, 4, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14                        = IOMUX_PAD(0x0478, 0x0208, 5, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT                      = IOMUX_PAD(0x0478, 0x0208, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0                     = IOMUX_PAD(0x047C, 0x020C, 0, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_DATA__NAND_READY_B                      = IOMUX_PAD(0x047C, 0x020C, 1, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS                     = IOMUX_PAD(0x047C, 0x020C, 2, 0x0710, 3, 0),
+	MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS                     = IOMUX_PAD(0x047C, 0x020C, 2, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX                       = IOMUX_PAD(0x047C, 0x020C, 3, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN                   = IOMUX_PAD(0x047C, 0x020C, 4, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15                        = IOMUX_PAD(0x047C, 0x020C, 5, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET                  = IOMUX_PAD(0x047C, 0x020C, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC                      = IOMUX_PAD(0x0480, 0x0210, 0, 0x06A4, 0, 0),
+	MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B                        = IOMUX_PAD(0x0480, 0x0210, 1, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC                      = IOMUX_PAD(0x0480, 0x0210, 2, 0x06B8, 1, 0),
+	MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL                          = IOMUX_PAD(0x0480, 0x0210, IOMUX_CONFIG_SION | 3, 0x05EC, 3, 0),
+	MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD                     = IOMUX_PAD(0x0480, 0x0210, 4, 0x06E0, 1, 0),
+	MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16                        = IOMUX_PAD(0x0480, 0x0210, 5, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT                         = IOMUX_PAD(0x0480, 0x0210, 6, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0                  = IOMUX_PAD(0x0480, 0x0210, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK                      = IOMUX_PAD(0x0484, 0x0214, 0, 0x069C, 0, 0),
+	MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B                        = IOMUX_PAD(0x0484, 0x0214, 1, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK                      = IOMUX_PAD(0x0484, 0x0214, 2, 0x06B0, 1, 0),
+	MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA                          = IOMUX_PAD(0x0484, 0x0214, IOMUX_CONFIG_SION | 3, 0x05F0, 3, 0),
+	MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA                    = IOMUX_PAD(0x0484, 0x0214, 4, 0x05CC, 1, 0),
+	MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17                        = IOMUX_PAD(0x0484, 0x0214, 5, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT                          = IOMUX_PAD(0x0484, 0x0214, 6, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1                  = IOMUX_PAD(0x0484, 0x0214, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_SAI1_MCLK__SAI1_MCLK                            = IOMUX_PAD(0x0488, 0x0218, 0, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_MCLK__NAND_WP_B                            = IOMUX_PAD(0x0488, 0x0218, 1, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_MCLK__SAI2_MCLK                            = IOMUX_PAD(0x0488, 0x0218, 2, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY                       = IOMUX_PAD(0x0488, 0x0218, 3, 0x04F4, 3, 0),
+	MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB                       = IOMUX_PAD(0x0488, 0x0218, 4, 0x05D0, 1, 0),
+	MX7D_PAD_SAI1_MCLK__GPIO6_IO18                           = IOMUX_PAD(0x0488, 0x0218, 5, 0x0000, 0, 0),
+	MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK                       = IOMUX_PAD(0x0488, 0x0218, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC                      = IOMUX_PAD(0x048C, 0x021C, 0, 0x06C0, 1, 0),
+	MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO                       = IOMUX_PAD(0x048C, 0x021C, 1, 0x0548, 1, 0),
+	MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX                      = IOMUX_PAD(0x048C, 0x021C, 2, 0x070C, 4, 0),
+	MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX                      = IOMUX_PAD(0x048C, 0x021C, 2, 0x0000, 0, 0),
+	MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS                     = IOMUX_PAD(0x048C, 0x021C, 3, 0x0000, 0, 0),
+	MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS                     = IOMUX_PAD(0x048C, 0x021C, 3, 0x06F0, 0, 0),
+	MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4                    = IOMUX_PAD(0x048C, 0x021C, 4, 0x05BC, 1, 0),
+	MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19                        = IOMUX_PAD(0x048C, 0x021C, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK                      = IOMUX_PAD(0x0490, 0x0220, 0, 0x06BC, 1, 0),
+	MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI                       = IOMUX_PAD(0x0490, 0x0220, 1, 0x054C, 1, 0),
+	MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX                      = IOMUX_PAD(0x0490, 0x0220, 2, 0x0000, 0, 0),
+	MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX                      = IOMUX_PAD(0x0490, 0x0220, 2, 0x070C, 5, 0),
+	MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS                     = IOMUX_PAD(0x0490, 0x0220, 3, 0x06F0, 1, 0),
+	MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS                     = IOMUX_PAD(0x0490, 0x0220, 3, 0x0000, 0, 0),
+	MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5                    = IOMUX_PAD(0x0490, 0x0220, 4, 0x05C0, 1, 0),
+	MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20                        = IOMUX_PAD(0x0490, 0x0220, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0                     = IOMUX_PAD(0x0494, 0x0224, 0, 0x06B4, 1, 0),
+	MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK                       = IOMUX_PAD(0x0494, 0x0224, 1, 0x0544, 1, 0),
+	MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS                     = IOMUX_PAD(0x0494, 0x0224, 2, 0x0000, 0, 0),
+	MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS                     = IOMUX_PAD(0x0494, 0x0224, 2, 0x0708, 4, 0),
+	MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS                     = IOMUX_PAD(0x0494, 0x0224, 3, 0x0000, 0, 0),
+	MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS                     = IOMUX_PAD(0x0494, 0x0224, 3, 0x06F8, 2, 0),
+	MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6                    = IOMUX_PAD(0x0494, 0x0224, 4, 0x05C4, 1, 0),
+	MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21                        = IOMUX_PAD(0x0494, 0x0224, 5, 0x0000, 0, 0),
+	MX7D_PAD_SAI2_RX_DATA__KPP_COL7                          = IOMUX_PAD(0x0494, 0x0224, 6, 0x0610, 1, 0),
+
+	MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0                     = IOMUX_PAD(0x0498, 0x0228, 0, 0x0000, 0, 0),
+	MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0                        = IOMUX_PAD(0x0498, 0x0228, 1, 0x0550, 1, 0),
+	MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS                     = IOMUX_PAD(0x0498, 0x0228, 2, 0x0708, 5, 0),
+	MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS                     = IOMUX_PAD(0x0498, 0x0228, 2, 0x0000, 0, 0),
+	MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS                     = IOMUX_PAD(0x0498, 0x0228, 3, 0x06F8, 3, 0),
+	MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS                     = IOMUX_PAD(0x0498, 0x0228, 3, 0x0000, 0, 0),
+	MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7                    = IOMUX_PAD(0x0498, 0x0228, 4, 0x05C8, 1, 0),
+	MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22                        = IOMUX_PAD(0x0498, 0x0228, 5, 0x0000, 0, 0),
+	MX7D_PAD_SAI2_TX_DATA__KPP_ROW7                          = IOMUX_PAD(0x0498, 0x0228, 6, 0x0630, 1, 0),
+
+	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0                = IOMUX_PAD(0x049C, 0x022C, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT                       = IOMUX_PAD(0x049C, 0x022C, 1, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL                       = IOMUX_PAD(0x049C, 0x022C, IOMUX_CONFIG_SION | 2, 0x05E4, 4, 0),
+	MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS                  = IOMUX_PAD(0x049C, 0x022C, 3, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS                  = IOMUX_PAD(0x049C, 0x022C, 3, 0x06F0, 2, 0),
+	MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0                     = IOMUX_PAD(0x049C, 0x022C, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0                      = IOMUX_PAD(0x049C, 0x022C, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3                       = IOMUX_PAD(0x049C, 0x022C, 6, 0x0620, 1, 0),
+
+	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1                = IOMUX_PAD(0x04A0, 0x0230, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT                       = IOMUX_PAD(0x04A0, 0x0230, 1, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA                       = IOMUX_PAD(0x04A0, 0x0230, IOMUX_CONFIG_SION | 2, 0x05E8, 4, 0),
+	MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS                  = IOMUX_PAD(0x04A0, 0x0230, 3, 0x06F0, 3, 0),
+	MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS                  = IOMUX_PAD(0x04A0, 0x0230, 3, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1                     = IOMUX_PAD(0x04A0, 0x0230, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1                      = IOMUX_PAD(0x04A0, 0x0230, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3                       = IOMUX_PAD(0x04A0, 0x0230, 6, 0x0600, 1, 0),
+
+	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2                = IOMUX_PAD(0x04A4, 0x0234, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX                    = IOMUX_PAD(0x04A4, 0x0234, 1, 0x04DC, 4, 0),
+	MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK                    = IOMUX_PAD(0x04A4, 0x0234, 2, 0x0534, 1, 0),
+	MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX                   = IOMUX_PAD(0x04A4, 0x0234, 3, 0x06F4, 2, 0),
+	MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX                   = IOMUX_PAD(0x04A4, 0x0234, 3, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4                     = IOMUX_PAD(0x04A4, 0x0234, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2                      = IOMUX_PAD(0x04A4, 0x0234, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2                       = IOMUX_PAD(0x04A4, 0x0234, 6, 0x061C, 1, 0),
+
+	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3                = IOMUX_PAD(0x04A8, 0x0238, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX                    = IOMUX_PAD(0x04A8, 0x0238, 1, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI                    = IOMUX_PAD(0x04A8, 0x0238, 2, 0x053C, 1, 0),
+	MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX                   = IOMUX_PAD(0x04A8, 0x0238, 3, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX                   = IOMUX_PAD(0x04A8, 0x0238, 3, 0x06F4, 3, 0),
+	MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5                     = IOMUX_PAD(0x04A8, 0x0238, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3                      = IOMUX_PAD(0x04A8, 0x0238, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2                       = IOMUX_PAD(0x04A8, 0x0238, 6, 0x05FC, 1, 0),
+
+	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL          = IOMUX_PAD(0x04AC, 0x023C, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1                  = IOMUX_PAD(0x04AC, 0x023C, 2, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6                  = IOMUX_PAD(0x04AC, 0x023C, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4                   = IOMUX_PAD(0x04AC, 0x023C, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1                    = IOMUX_PAD(0x04AC, 0x023C, 6, 0x0618, 1, 0),
+
+	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC                = IOMUX_PAD(0x04B0, 0x0240, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER                    = IOMUX_PAD(0x04B0, 0x0240, 1, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2                     = IOMUX_PAD(0x04B0, 0x0240, 2, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7                     = IOMUX_PAD(0x04B0, 0x0240, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5                      = IOMUX_PAD(0x04B0, 0x0240, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1                       = IOMUX_PAD(0x04B0, 0x0240, 6, 0x0000, 0, 0),
+
+	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0                = IOMUX_PAD(0x04B4, 0x0244, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT                       = IOMUX_PAD(0x04B4, 0x0244, 1, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3                     = IOMUX_PAD(0x04B4, 0x0244, 2, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8                     = IOMUX_PAD(0x04B4, 0x0244, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6                      = IOMUX_PAD(0x04B4, 0x0244, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0                       = IOMUX_PAD(0x04B4, 0x0244, 6, 0x0614, 1, 0),
+
+	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1                = IOMUX_PAD(0x04B8, 0x0248, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT                       = IOMUX_PAD(0x04B8, 0x0248, 1, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY                     = IOMUX_PAD(0x04B8, 0x0248, 2, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9                     = IOMUX_PAD(0x04B8, 0x0248, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7                      = IOMUX_PAD(0x04B8, 0x0248, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0                       = IOMUX_PAD(0x04B8, 0x0248, 6, 0x05F4, 1, 0),
+
+	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2                = IOMUX_PAD(0x04BC, 0x024C, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX                    = IOMUX_PAD(0x04BC, 0x024C, 1, 0x04E0, 4, 0),
+	MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO                    = IOMUX_PAD(0x04BC, 0x024C, 2, 0x0538, 1, 0),
+	MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL                       = IOMUX_PAD(0x04BC, 0x024C, IOMUX_CONFIG_SION | 3, 0x05EC, 4, 0),
+	MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED                     = IOMUX_PAD(0x04BC, 0x024C, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8                      = IOMUX_PAD(0x04BC, 0x024C, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3                = IOMUX_PAD(0x04C0, 0x0250, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX                    = IOMUX_PAD(0x04C0, 0x0250, 1, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0                     = IOMUX_PAD(0x04C0, 0x0250, 2, 0x0540, 1, 0),
+	MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA                       = IOMUX_PAD(0x04C0, 0x0250, IOMUX_CONFIG_SION | 3, 0x05F0, 4, 0),
+	MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ                     = IOMUX_PAD(0x04C0, 0x0250, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9                      = IOMUX_PAD(0x04C0, 0x0250, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS               = IOMUX_PAD(0x04C0, 0x0250, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL          = IOMUX_PAD(0x04C4, 0x0254, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC                = IOMUX_PAD(0x04C4, 0x0254, 2, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1               = IOMUX_PAD(0x04C4, 0x0254, 3, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2              = IOMUX_PAD(0x04C4, 0x0254, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10                  = IOMUX_PAD(0x04C4, 0x0254, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC                = IOMUX_PAD(0x04C8, 0x0258, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER                    = IOMUX_PAD(0x04C8, 0x0258, 1, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK                   = IOMUX_PAD(0x04C8, 0x0258, 2, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2                  = IOMUX_PAD(0x04C8, 0x0258, 3, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3                 = IOMUX_PAD(0x04C8, 0x0258, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11                     = IOMUX_PAD(0x04C8, 0x0258, 5, 0x0000, 0, 0),
+
+	MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK                      = IOMUX_PAD(0x04CC, 0x025C, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1                 = IOMUX_PAD(0x04CC, 0x025C, 1, 0x0564, 2, 0),
+	MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0                     = IOMUX_PAD(0x04CC, 0x025C, 2, 0x06A0, 1, 0),
+	MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3                     = IOMUX_PAD(0x04CC, 0x025C, 3, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ                      = IOMUX_PAD(0x04CC, 0x025C, 4, 0x057C, 1, 0),
+	MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12                        = IOMUX_PAD(0x04CC, 0x025C, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1                      = IOMUX_PAD(0x04CC, 0x025C, 6, 0x04E4, 2, 0),
+	MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0                    = IOMUX_PAD(0x04CC, 0x025C, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK                      = IOMUX_PAD(0x04D0, 0x0260, 0, 0x056C, 0, 0),
+	MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B                      = IOMUX_PAD(0x04D0, 0x0260, 1, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK                      = IOMUX_PAD(0x04D0, 0x0260, 2, 0x06A8, 1, 0),
+	MX7D_PAD_ENET1_RX_CLK__GPT2_CLK                          = IOMUX_PAD(0x04D0, 0x0260, 3, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE                     = IOMUX_PAD(0x04D0, 0x0260, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13                        = IOMUX_PAD(0x04D0, 0x0260, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2                      = IOMUX_PAD(0x04D0, 0x0260, 6, 0x04E8, 2, 0),
+	MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1                    = IOMUX_PAD(0x04D0, 0x0260, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_ENET1_CRS__ENET1_CRS                            = IOMUX_PAD(0x04D4, 0x0264, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB                 = IOMUX_PAD(0x04D4, 0x0264, 1, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC                         = IOMUX_PAD(0x04D4, 0x0264, 2, 0x06AC, 1, 0),
+	MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1                        = IOMUX_PAD(0x04D4, 0x0264, 3, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0                       = IOMUX_PAD(0x04D4, 0x0264, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_CRS__GPIO7_IO14                           = IOMUX_PAD(0x04D4, 0x0264, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3                         = IOMUX_PAD(0x04D4, 0x0264, 6, 0x04EC, 2, 0),
+	MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2                       = IOMUX_PAD(0x04D4, 0x0264, 7, 0x0000, 0, 0),
+
+	MX7D_PAD_ENET1_COL__ENET1_COL                            = IOMUX_PAD(0x04D8, 0x0268, 0, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY                       = IOMUX_PAD(0x04D8, 0x0268, 1, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_COL__SAI1_TX_DATA0                        = IOMUX_PAD(0x04D8, 0x0268, 2, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_COL__GPT2_CAPTURE2                        = IOMUX_PAD(0x04D8, 0x0268, 3, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1                       = IOMUX_PAD(0x04D8, 0x0268, 4, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_COL__GPIO7_IO15                           = IOMUX_PAD(0x04D8, 0x0268, 5, 0x0000, 0, 0),
+	MX7D_PAD_ENET1_COL__CCM_EXT_CLK4                         = IOMUX_PAD(0x04D8, 0x0268, 6, 0x04F0, 2, 0),
+	MX7D_PAD_ENET1_COL__CSU_INT_DEB                          = IOMUX_PAD(0x04D8, 0x0268, 7, 0x0000, 0, 0),
+};
+#endif  /* __ASM_ARCH_IMX7D_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx7/mx7d_rdc.h b/arch/arm/include/asm/arch-mx7/mx7d_rdc.h
new file mode 100644
index 0000000..2ea175c
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/mx7d_rdc.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __MX7D_RDC_H__
+#define __MX7D_RDC_H__
+
+#define RDC_SEMA_PROC_ID 2  /* The processor ID for main CPU */
+
+enum {
+	RDC_PER_GPIO1 = 0,
+	RDC_PER_GPIO2,
+	RDC_PER_GPIO3,
+	RDC_PER_GPIO4,
+	RDC_PER_GPIO5,
+	RDC_PER_GPIO6,
+	RDC_PER_GPIO7,
+	RDC_PER_IOMUXC_LPSR_GPR,
+	RDC_PER_WDOG1,
+	RDC_PER_WDOG2,
+	RDC_PER_WDOG3,
+	RDC_PER_WDOG4,
+	RDC_PER_IOMUXC_LPSR,
+	RDC_PER_GPT1,
+	RDC_PER_GPT2,
+	RDC_PER_GPT3,
+	RDC_PER_GPT4,
+	RDC_PER_ROMCP,
+	RDC_PER_KPP,
+	RDC_PER_IOMUXC,
+	RDC_PER_IOMUXCGPR,
+	RDC_PER_OCOTP,
+	RDC_PER_ANATOP_DIG,
+	RDC_PER_SNVS_HP,
+	RDC_PER_CCM,
+	RDC_PER_SRC,
+	RDC_PER_GPC,
+	RDC_PER_SEMA1,
+	RDC_PER_SEMA2,
+	RDC_PER_RDC,
+	RDC_PER_CSU,
+	RDC_PER_RESERVED1,
+	RDC_PER_RESERVED2,
+	RDC_PER_ADC1,
+	RDC_PER_ADC2,
+	RDC_PER_ECSPI4,
+	RDC_PER_FLEX_TIMER1,
+	RDC_PER_FLEX_TIMER2,
+	RDC_PER_PWM1,
+	RDC_PER_PWM2,
+	RDC_PER_PWM3,
+	RDC_PER_PWM4,
+	RDC_PER_SYSTEM_COUNTER_READ,
+	RDC_PER_SYSTEM_COUNTER_COMPARE,
+	RDC_PER_SYSTEM_COUNTER_CONTROL,
+	RDC_PER_PCIE_PHY,
+	RDC_PER_RESERVED3,
+	RDC_PER_EPDC,
+	RDC_PER_PXP,
+	RDC_PER_CSI,
+	RDC_PER_RESERVED4,
+	RDC_PER_LCDIF,
+	RDC_PER_RESERVED5,
+	RDC_PER_MIPI_CSI,
+	RDC_PER_MIPI_DSI,
+	RDC_PER_RESERVED6,
+	RDC_PER_TZASC,
+	RDC_PER_DDR_PHY,
+	RDC_PER_DDRC,
+	RDC_PER_RESERVED7,
+	RDC_PER_PERFMON1,
+	RDC_PER_PERFMON2,
+	RDC_PER_AXI_DEBUG_MON,
+	RDC_PER_QOSC,
+	RDC_PER_FLEXCAN1,
+	RDC_PER_FLEXCAN2,
+	RDC_PER_I2C1,
+	RDC_PER_I2C2,
+	RDC_PER_I2C3,
+	RDC_PER_I2C4,
+	RDC_PER_UART4,
+	RDC_PER_UART5,
+	RDC_PER_UART6,
+	RDC_PER_UART7,
+	RDC_PER_MU_A,
+	RDC_PER_MU_B,
+	RDC_PER_SEMAPHORE_HS,
+	RDC_PER_USB_PL301,
+	RDC_PER_RESERVED8,
+	RDC_PER_RESERVED9,
+	RDC_PER_RESERVED10,
+	RDC_PER_USB1,
+	RDC_PER_USB2,
+	RDC_PER_USB3,
+	RDC_PER_USDHC1,
+	RDC_PER_USDHC2,
+	RDC_PER_USDHC3,
+	RDC_PER_RESERVED11,
+	RDC_PER_RESERVED12,
+	RDC_PER_SIM1,
+	RDC_PER_SIM2,
+	RDC_PER_QSPI,
+	RDC_PER_WEIM,
+	RDC_PER_SDMA,
+	RDC_PER_ENET1,
+	RDC_PER_ENET2,
+	RDC_PER_RESERVED13,
+	RDC_PER_RESERVED14,
+	RDC_PER_ECSPI1,
+	RDC_PER_ECSPI2,
+	RDC_PER_ECSPI3,
+	RDC_PER_RESERVED15,
+	RDC_PER_UART1,
+	RDC_PER_UART2,
+	RDC_PER_UART3,
+	RDC_PER_RESERVED16,
+	RDC_PER_SAI1,
+	RDC_PER_SAI2,
+	RDC_PER_SAI3,
+	RDC_PER_RESERVED17,
+	RDC_PER_RESERVED18,
+	RDC_PER_SPBA,
+	RDC_PER_DAP,
+	RDC_PER_RESERVED19,
+	RDC_PER_RESERVED20,
+	RDC_PER_RESERVED21,
+	RDC_PER_CAAM,
+	RDC_PER_RESERVED22,
+};
+
+enum {
+	RDC_MA_A7 = 0,
+	RDC_MA_M4,
+	RDC_MA_PCIE,
+	RDC_MA_CSI,
+	RDC_MA_EPDC,
+	RDC_MA_LCDIF,
+	RDC_MA_DISPLAY_PORT,
+	RDC_MA_PXP,
+	RDC_MA_CORESIGHT,
+	RDC_MA_DAP,
+	RDC_MA_CAAM,
+	RDC_MA_SDMA_PERI,
+	RDC_MA_SDMA_BURST,
+	RDC_MA_APBHDMA,
+	RDC_MA_RAWNAND,
+	RDC_MA_USDHC1,
+	RDC_MA_USDHC2,
+	RDC_MA_USDHC3,
+	RDC_MA_NC1,
+	RDC_MA_USB,
+	RDC_MA_NC2,
+	RDC_MA_TEST,
+	RDC_MA_ENET1_TX,
+	RDC_MA_ENET1_RX,
+	RDC_MA_ENET2_TX,
+	RDC_MA_ENET2_RX,
+	RDC_MA_SDMA,
+};
+
+#endif	/* __MX7D_RDC_H__*/
diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h
new file mode 100644
index 0000000..e46a021
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/sys_proto.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+#ifndef __SYS_PROTO_IMX7_
+#define __SYS_PROTO_IMX7_
+
+#include <asm/mach-imx/sys_proto.h>
+
+void set_wdog_reset(struct wdog_regs *wdog);
+enum boot_device get_boot_device(void);
+
+#endif /* __SYS_PROTO_IMX7_ */
diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h
new file mode 100644
index 0000000..eb02a20
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/clock.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_ARCH_CLOCK_H
+#define _ASM_ARCH_CLOCK_H
+
+#include <common.h>
+#include <asm/arch/pcc.h>
+#include <asm/arch/scg.h>
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_UART_CLK,
+	MXC_CSPI_CLK,
+	MXC_AXI_CLK,
+	MXC_DDR_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_I2C_CLK,
+};
+
+u32 mxc_get_clock(enum mxc_clock clk);
+u32 get_lpuart_clk(void);
+#ifdef CONFIG_SYS_I2C_IMX_LPI2C
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+u32 imx_get_i2cclk(unsigned i2c_num);
+#endif
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable);
+#endif
+#ifdef CONFIG_USB_EHCI_HCD
+void enable_usboh3_clk(unsigned char enable);
+#endif
+void init_clk_usdhc(u32 index);
+void clock_init(void);
+void hab_caam_clock_enable(unsigned char enable);
+#endif
diff --git a/arch/arm/include/asm/arch-mx7ulp/gpio.h b/arch/arm/include/asm/arch-mx7ulp/gpio.h
new file mode 100644
index 0000000..7c62560
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/gpio.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_MX7ULP_GPIO_H
+#define __ASM_ARCH_MX7ULP_GPIO_H
+
+struct gpio_regs {
+	u32 gpio_pdor;
+	u32 gpio_psor;
+	u32 gpio_pcor;
+	u32 gpio_ptor;
+	u32 gpio_pdir;
+	u32 gpio_pddr;
+	u32 gpio_gacr;
+};
+
+#define IMX_GPIO_NR(port, index)		((((port)-1)*32)+((index)&31))
+
+#endif /* __ASM_ARCH_MX7ULP_GPIO_H */
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
new file mode 100644
index 0000000..3c82e99
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -0,0 +1,1141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _MX7ULP_REGS_H_
+#define _MX7ULP_REGS_H_
+
+#include <linux/sizes.h>
+
+#define ARCH_MXC
+
+#define ROM_SW_INFO_ADDR        0x000001E8
+
+#define CAAM_SEC_SRAM_BASE      (0x26000000)
+#define CAAM_SEC_SRAM_SIZE      (SZ_32K)
+#define CAAM_SEC_SRAM_END       (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1)
+
+#define OCRAM_0_BASE            (0x2F000000)
+#define OCRAM_0_SIZE            (SZ_128K)
+#define OCRAM_0_END             (OCRAM_0_BASE + OCRAM_0_SIZE - 1)
+
+#define OCRAM_1_BASE            (0x2F020000)
+#define OCRAM_1_SIZE            (SZ_128K)
+#define OCRAM_1_END             (OCRAM_1_BASE + OCRAM_1_SIZE - 1)
+
+#define TCML_BASE               (0x1FFD0000)
+#define TCMU_BASE               (0x20000000)
+
+#define AIPS3_BASE			(0x40800000UL)
+#define AIPS3_SLOT_SIZE			(SZ_64K)
+#define AIPS2_BASE			(0x40000000UL)
+#define AIPS2_SLOT_SIZE			(SZ_64K)
+#define AIPS1_BASE			(0x41080000UL)
+#define AIPS1_SLOT_SIZE			(SZ_4K)
+#define AIPS0_BASE			(0x41000000UL)
+#define AIPS0_SLOT_SIZE			(SZ_4K)
+#define IOMUXC0_AIPS0_SLOT		(61)
+#define WDG0_AIPS0_SLOT			(37)
+#define WDG1_AIPS2_SLOT			(61)
+#define WDG2_AIPS2_SLOT			(67)
+#define WDG0_PCC0_SLOT			(37)
+#define IOMUXC1_AIPS3_SLOT		(44)
+#define CMC0_AIPS1_SLOT			(36)
+#define CMC1_AIPS2_SLOT			(65)
+#define SCG0_AIPS0_SLOT			(39)
+#define PCC0_AIPS0_SLOT			(38)
+#define PCC1_AIPS1_SLOT			(50)
+#define PCC2_AIPS2_SLOT			(63)
+#define PCC3_AIPS3_SLOT			(51)
+#define SCG1_AIPS2_SLOT			(62)
+#define SIM0_AIPS1_SLOT			(35)
+#define SIM1_AIPS1_SLOT			(48)
+#define USBOTG0_AIPS2_SLOT		(51)
+#define USBOTG1_AIPS2_SLOT		(52)
+#define USBPHY_AIPS2_SLOT		(53)
+#define USDHC0_AIPS2_SLOT		(55)
+#define USDHC1_AIPS2_SLOT		(56)
+#define RGPIO2P0_AIPS0_SLOT		(15)
+#define RGPIO2P1_AIPS2_SLOT		(15)
+#define SNVS_AIPS2_SLOT			(35)
+#define IOMUXC0_AIPS0_SLOT		(61)
+#define OCOTP_CTRL_AIPS1_SLOT		(38)
+#define OCOTP_CTRL_PCC1_SLOT		(38)
+#define SIM1_PCC1_SLOT			(48)
+#define MMDC0_AIPS3_SLOT		(43)
+#define IOMUXC_DDR_AIPS3_SLOT		(45)
+
+#define LPI2C0_AIPS0_SLOT		(51)
+#define LPI2C1_AIPS0_SLOT		(52)
+#define LPI2C2_AIPS0_SLOT		(53)
+#define LPI2C3_AIPS0_SLOT		(54)
+#define LPI2C4_AIPS2_SLOT		(43)
+#define LPI2C5_AIPS2_SLOT		(44)
+#define LPI2C6_AIPS3_SLOT		(36)
+#define LPI2C7_AIPS3_SLOT		(37)
+
+#define LPUART0_PCC0_SLOT		(58)
+#define LPUART1_PCC0_SLOT		(59)
+#define LPUART2_PCC1_SLOT		(43)
+#define LPUART3_PCC1_SLOT		(44)
+#define LPUART0_AIPS0_SLOT		(58)
+#define LPUART1_AIPS0_SLOT		(59)
+#define LPUART2_AIPS1_SLOT		(43)
+#define LPUART3_AIPS1_SLOT		(44)
+#define LPUART4_AIPS2_SLOT		(45)
+#define LPUART5_AIPS2_SLOT		(46)
+#define LPUART6_AIPS3_SLOT		(38)
+#define LPUART7_AIPS3_SLOT		(39)
+
+#define CORE_B_ROM_SIZE			(SZ_32K + SZ_64K)
+#define CORE_B_ROM_BASE			(0x00000000)
+
+#define ROMCP_ARB_BASE_ADDR		CORE_B_ROM_BASE
+#define ROMCP_ARB_END_ADDR		CORE_B_ROM_SIZE
+#define IRAM_BASE_ADDR			OCRAM_0_BASE
+#define IRAM_SIZE			(SZ_128K + SZ_128K)
+
+#define IOMUXC_PCR_MUX_ALT0		(0<<8)
+#define IOMUXC_PCR_MUX_ALT1		(1<<8)
+#define IOMUXC_PCR_MUX_ALT2		(2<<8)
+#define IOMUXC_PCR_MUX_ALT3		(3<<8)
+#define IOMUXC_PCR_MUX_ALT4		(4<<8)
+#define IOMUXC_PCR_MUX_ALT5		(5<<8)
+#define IOMUXC_PCR_MUX_ALT6		(6<<8)
+#define IOMUXC_PCR_MUX_ALT7		(7<<8)
+#define IOMUXC_PCR_MUX_ALT8		(8<<8)
+#define IOMUXC_PCR_MUX_ALT9		(9<<8)
+#define IOMUXC_PCR_MUX_ALT10		(10<<8)
+#define IOMUXC_PCR_MUX_ALT11		(11<<8)
+#define IOMUXC_PCR_MUX_ALT12		(12<<8)
+#define IOMUXC_PCR_MUX_ALT13		(13<<8)
+#define IOMUXC_PCR_MUX_ALT14		(14<<8)
+#define IOMUXC_PCR_MUX_ALT15		(15<<8)
+
+#define IOMUXC_PSMI_IMUX_ALT0		(0x0)
+#define IOMUXC_PSMI_IMUX_ALT1		(0x1)
+#define IOMUXC_PSMI_IMUX_ALT2		(0x2)
+#define IOMUXC_PSMI_IMUX_ALT3		(0x3)
+#define IOMUXC_PSMI_IMUX_ALT4		(0x4)
+#define IOMUXC_PSMI_IMUX_ALT5		(0x5)
+#define IOMUXC_PSMI_IMUX_ALT6		(0x6)
+#define IOMUXC_PSMI_IMUX_ALT7		(0x7)
+
+
+#define SIM_SOPT1_EN_SNVS_HARD_RST	(1<<8)
+#define SIM_SOPT1_PMIC_STBY_REQ		(1<<2)
+#define SIM_SOPT1_A7_SW_RESET		(1<<0)
+
+#define IOMUXC_PCR_MUX_ALT_SHIFT	(8)
+#define IOMUXC_PCR_MUX_ALT_MASK		(0xF00)
+#define IOMUXC_PSMI_IMUX_ALT_SHIFT	(0)
+
+#define IOMUXC0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT)))
+#define IOMUXC1_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC1_AIPS3_SLOT)))
+#define WDG0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * WDG0_AIPS0_SLOT)))
+#define WDG1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG1_AIPS2_SLOT)))
+#define WDG2_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * WDG2_AIPS2_SLOT)))
+#define SCG0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * SCG0_AIPS0_SLOT)))
+#define SCG1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * SCG1_AIPS2_SLOT)))
+#define PCC0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * PCC0_AIPS0_SLOT)))
+#define PCC1_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * PCC1_AIPS1_SLOT)))
+#define PCC2_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * PCC2_AIPS2_SLOT)))
+#define PCC3_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * PCC3_AIPS3_SLOT)))
+#define IOMUXC0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * IOMUXC0_AIPS0_SLOT)))
+#define PSMI0_RBASE	((IOMUXC0_RBASE + 0x100)) /* in iomuxc0 after pta and ptb */
+#define CMC0_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * CMC0_AIPS1_SLOT)))
+#define CMC1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * CMC1_AIPS2_SLOT)))
+#define OCOTP_BASE_ADDR	((AIPS1_BASE + (AIPS1_SLOT_SIZE * OCOTP_CTRL_AIPS1_SLOT)))
+#define SIM0_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM0_AIPS1_SLOT)))
+#define SIM1_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * SIM1_AIPS1_SLOT)))
+#define MMDC0_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * MMDC0_AIPS3_SLOT)))
+
+#define USBOTG0_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG0_AIPS2_SLOT)))
+#define USBOTG1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBOTG1_AIPS2_SLOT)))
+#define USBPHY_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USBPHY_AIPS2_SLOT)))
+#define USB_PHY0_BASE_ADDR	USBPHY_RBASE
+#define USB_BASE_ADDR		USBOTG0_RBASE
+
+#define LPI2C1_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C0_AIPS0_SLOT)))
+#define LPI2C2_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C1_AIPS0_SLOT)))
+#define LPI2C3_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C2_AIPS0_SLOT)))
+#define LPI2C4_BASE_ADDR	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPI2C3_AIPS0_SLOT)))
+#define LPI2C5_BASE_ADDR	((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C4_AIPS2_SLOT)))
+#define LPI2C6_BASE_ADDR	((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPI2C5_AIPS2_SLOT)))
+#define LPI2C7_BASE_ADDR	((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C6_AIPS3_SLOT)))
+#define LPI2C8_BASE_ADDR	((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPI2C7_AIPS3_SLOT)))
+
+#define LPUART0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART0_AIPS0_SLOT)))
+#define LPUART1_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * LPUART1_AIPS0_SLOT)))
+#define LPUART2_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART2_AIPS1_SLOT)))
+#define LPUART3_RBASE	((AIPS1_BASE + (AIPS1_SLOT_SIZE * LPUART3_AIPS1_SLOT)))
+#define LPUART4_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART4_AIPS2_SLOT)))
+#define LPUART5_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * LPUART5_AIPS2_SLOT)))
+#define LPUART6_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART6_AIPS3_SLOT)))
+#define LPUART7_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * LPUART7_AIPS3_SLOT)))
+
+#define USDHC0_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT)))
+#define USDHC1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT)))
+
+#define SNVS_BASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT)))
+#define SNVS_LP_LPCR	(SNVS_BASE + 0x38)
+
+#define RGPIO2P0_RBASE	((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT)))
+#define RGPIO2P1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT)))
+
+#define WDG0_PCC_REG	(PCC0_RBASE + (4 * WDG0_PCC0_SLOT))
+#define WDG1_PCC_REG	(PCC2_RBASE + (4 * WDG1_PCC2_SLOT))
+#define CMC0_SRS	(CMC0_RBASE  + 0x20)
+#define CMC0_SSRS	(CMC0_RBASE  + 0x28)
+#define CMC1_SRS	(CMC1_RBASE  + 0x20)
+#define CMC1_SSRS	(CMC1_RBASE  + 0x28)
+
+#define IOMUXC0_PCR0	(IOMUXC0_RBASE + (4 * 0))
+#define IOMUXC0_PCR1	(IOMUXC0_RBASE + (4 * 1))
+#define IOMUXC0_PCR2	(IOMUXC0_RBASE + (4 * 2))
+#define IOMUXC0_PCR3	(IOMUXC0_RBASE + (4 * 3))
+#define IOMUXC0_PSMI62	(PSMI0_RBASE + (4 * 62))
+#define IOMUXC0_PSMI63	(PSMI0_RBASE + (4 * 63))
+#define IOMUXC0_PSMI64	(PSMI0_RBASE + (4 * 64))
+
+#define SCG_CSR		(SCG0_RBASE + 0x010)
+#define SCG_RCCR	(SCG0_RBASE + 0x014)
+#define SCG_VCCR	(SCG0_RBASE + 0x018)
+#define SCG_HCCR	(SCG0_RBASE + 0x01c)
+
+#define LPUART0_PCC_REG	(PCC0_RBASE + (4 * LPUART0_PCC0_SLOT))
+#define LPUART1_PCC_REG	(PCC0_RBASE + (4 * LPUART1_PCC0_SLOT))
+#define LPUART2_PCC_REG	(PCC1_RBASE + (4 * LPUART2_PCC1_SLOT))
+#define LPUART3_PCC_REG	(PCC1_RBASE + (4 * LPUART3_PCC1_SLOT))
+#define LPUART4_PCC_REG	(PCC2_RBASE + (4 * LPUART4_PCC2_SLOT))
+#define LPUART5_PCC_REG	(PCC2_RBASE + (4 * LPUART5_PCC2_SLOT))
+#define LPUART6_PCC_REG	(PCC3_RBASE + (4 * LPUART6_PCC3_SLOT))
+#define LPUART7_PCC_REG	(PCC3_RBASE + (4 * LPUART7_PCC3_SLOT))
+
+#define USDHC0_PCC_REG	(PCC2_RBASE + (4 * USDHC0_PCC2_SLOT))
+#define USDHC1_PCC_REG	(PCC2_RBASE + (4 * USDHC1_PCC2_SLOT))
+
+#define SIM1_PCC_REG	(PCC1_RBASE + (4 * SIM1_PCC1_SLOT))
+#define SCG1_PCC_REG	(PCC2_RBASE + (4 * SCG1_PCC2_SLOT))
+
+#define OCOTP_CTRL_PCC_REG	(PCC1_RBASE + (4 * OCOTP_CTRL_PCC1_SLOT))
+
+#define IOMUXC_DDR_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT)))
+#define MMDC0_PCC_REG		(PCC3_RBASE + (4 * MMDC0_PCC3_SLOT))
+
+#define IOMUXC_DPCR_DDR_DQS0	((IOMUXC_DDR_RBASE + (4 * 32)))
+#define IOMUXC_DPCR_DDR_DQS1	((IOMUXC_DDR_RBASE + (4 * 33)))
+#define IOMUXC_DPCR_DDR_DQS2	((IOMUXC_DDR_RBASE + (4 * 34)))
+#define IOMUXC_DPCR_DDR_DQS3	((IOMUXC_DDR_RBASE + (4 * 35)))
+
+
+#define IOMUXC_DPCR_DDR_DQ0	((IOMUXC_DDR_RBASE + (4 * 0)))
+#define IOMUXC_DPCR_DDR_DQ1	((IOMUXC_DDR_RBASE + (4 * 1)))
+#define IOMUXC_DPCR_DDR_DQ2	((IOMUXC_DDR_RBASE + (4 * 2)))
+#define IOMUXC_DPCR_DDR_DQ3	((IOMUXC_DDR_RBASE + (4 * 3)))
+#define IOMUXC_DPCR_DDR_DQ4	((IOMUXC_DDR_RBASE + (4 * 4)))
+#define IOMUXC_DPCR_DDR_DQ5	((IOMUXC_DDR_RBASE + (4 * 5)))
+#define IOMUXC_DPCR_DDR_DQ6	((IOMUXC_DDR_RBASE + (4 * 6)))
+#define IOMUXC_DPCR_DDR_DQ7	((IOMUXC_DDR_RBASE + (4 * 7)))
+#define IOMUXC_DPCR_DDR_DQ8	((IOMUXC_DDR_RBASE + (4 * 8)))
+#define IOMUXC_DPCR_DDR_DQ9	((IOMUXC_DDR_RBASE + (4 * 9)))
+#define IOMUXC_DPCR_DDR_DQ10	((IOMUXC_DDR_RBASE + (4 * 10)))
+#define IOMUXC_DPCR_DDR_DQ11	((IOMUXC_DDR_RBASE + (4 * 11)))
+#define IOMUXC_DPCR_DDR_DQ12	((IOMUXC_DDR_RBASE + (4 * 12)))
+#define IOMUXC_DPCR_DDR_DQ13	((IOMUXC_DDR_RBASE + (4 * 13)))
+#define IOMUXC_DPCR_DDR_DQ14	((IOMUXC_DDR_RBASE + (4 * 14)))
+#define IOMUXC_DPCR_DDR_DQ15	((IOMUXC_DDR_RBASE + (4 * 15)))
+#define IOMUXC_DPCR_DDR_DQ16	((IOMUXC_DDR_RBASE + (4 * 16)))
+#define IOMUXC_DPCR_DDR_DQ17	((IOMUXC_DDR_RBASE + (4 * 17)))
+#define IOMUXC_DPCR_DDR_DQ18	((IOMUXC_DDR_RBASE + (4 * 18)))
+#define IOMUXC_DPCR_DDR_DQ19	((IOMUXC_DDR_RBASE + (4 * 19)))
+#define IOMUXC_DPCR_DDR_DQ20	((IOMUXC_DDR_RBASE + (4 * 20)))
+#define IOMUXC_DPCR_DDR_DQ21	((IOMUXC_DDR_RBASE + (4 * 21)))
+#define IOMUXC_DPCR_DDR_DQ22	((IOMUXC_DDR_RBASE + (4 * 22)))
+#define IOMUXC_DPCR_DDR_DQ23	((IOMUXC_DDR_RBASE + (4 * 23)))
+#define IOMUXC_DPCR_DDR_DQ24	((IOMUXC_DDR_RBASE + (4 * 24)))
+#define IOMUXC_DPCR_DDR_DQ25	((IOMUXC_DDR_RBASE + (4 * 25)))
+#define IOMUXC_DPCR_DDR_DQ26	((IOMUXC_DDR_RBASE + (4 * 26)))
+#define IOMUXC_DPCR_DDR_DQ27	((IOMUXC_DDR_RBASE + (4 * 27)))
+#define IOMUXC_DPCR_DDR_DQ28	((IOMUXC_DDR_RBASE + (4 * 28)))
+#define IOMUXC_DPCR_DDR_DQ29	((IOMUXC_DDR_RBASE + (4 * 29)))
+#define IOMUXC_DPCR_DDR_DQ30	((IOMUXC_DDR_RBASE + (4 * 30)))
+#define IOMUXC_DPCR_DDR_DQ31	((IOMUXC_DDR_RBASE + (4 * 31)))
+
+/* Remap the rgpio2p registers addr to driver's addr */
+#define RGPIO2P_GPIO1_BASE_ADDR	RGPIO2P0_RBASE
+#define RGPIO2P_GPIO2_BASE_ADDR	(RGPIO2P0_RBASE + 0x40)
+#define RGPIO2P_GPIO3_BASE_ADDR	(RGPIO2P1_RBASE)
+#define RGPIO2P_GPIO4_BASE_ADDR	(RGPIO2P1_RBASE + 0x40)
+#define RGPIO2P_GPIO5_BASE_ADDR	(RGPIO2P1_RBASE + 0x80)
+#define RGPIO2P_GPIO6_BASE_ADDR	(RGPIO2P1_RBASE + 0xc0)
+
+/* MMDC registers addresses */
+#define MMDC_MDCTL_OFFSET	(0x000)
+#define MMDC_MDPDC_OFFSET	(0x004)
+#define MMDC_MDOTC_OFFSET	(0x008)
+#define MMDC_MDCFG0_OFFSET	(0x00C)
+#define MMDC_MDCFG1_OFFSET	(0x010)
+#define MMDC_MDCFG2_OFFSET	(0x014)
+#define MMDC_MDMISC_OFFSET	(0x018)
+#define MMDC_MDSCR_OFFSET	(0x01C)
+#define MMDC_MDREF_OFFSET	(0x020)
+#define MMDC_MDRWD_OFFSET	(0x02C)
+#define MMDC_MDOR_OFFSET	(0x030)
+#define MMDC_MDMRR_OFFSET	(0x034)
+#define MMDC_MDCFG3LP_OFFSET	(0x038)
+#define MMDC_MDMR4_OFFSET	(0x03C)
+#define MMDC_MDASP_OFFSET	(0x040)
+
+#define MMDC_MAARCR_OFFSET	(0x400)
+#define MMDC_MAPSR_OFFSET	(0x404)
+#define MMDC_MAEXIDR0_OFFSET	(0x408)
+#define MMDC_MAEXIDR1_OFFSET	(0x40C)
+#define MMDC_MADPCR0_OFFSET	(0x410)
+#define MMDC_MADPCR1_OFFSET	(0x414)
+#define MMDC_MADPSR0_OFFSET	(0x418)
+#define MMDC_MADPSR1_OFFSET	(0x41C)
+#define MMDC_MADPSR2_OFFSET	(0x420)
+#define MMDC_MADPSR3_OFFSET	(0x424)
+#define MMDC_MADPSR4_OFFSET	(0x428)
+#define MMDC_MADPSR5_OFFSET	(0x42C)
+#define MMDC_MASBS0_OFFSET	(0x430)
+#define MMDC_MASBS1_OFFSET	(0x434)
+#define MMDC_MAGENP_OFFSET	(0x440)
+
+#define MMDC_MPZQHWCTRL_OFFSET	(0x800)
+#define MMDC_MPZQSWCTRL_OFFSET	(0x804)
+#define MMDC_MPWLGCR_OFFSET	(0x808)
+#define MMDC_MPWLDECTRL0_OFFSET	(0x80C)
+#define MMDC_MPWLDECTRL1_OFFSET	(0x810)
+#define MMDC_MPWLDLST_OFFSET	(0x814)
+#define MMDC_MPODTCTRL_OFFSET	(0x818)
+#define MMDC_MPREDQBY0DL_OFFSET	(0x81C)
+#define MMDC_MPREDQBY1DL_OFFSET	(0x820)
+#define MMDC_MPREDQBY2DL_OFFSET	(0x824)
+#define MMDC_MPREDQBY3DL_OFFSET	(0x828)
+#define MMDC_MPWRDQBY0DL_OFFSET	(0x82C)
+#define MMDC_MPWRDQBY1DL_OFFSET	(0x830)
+#define MMDC_MPWRDQBY2DL_OFFSET	(0x834)
+#define MMDC_MPWRDQBY3DL_OFFSET	(0x838)
+#define MMDC_MPDGCTRL0_OFFSET	(0x83C)
+#define MMDC_MPDGCTRL1_OFFSET	(0x840)
+#define MMDC_MPDGDLST_OFFSET	(0x844)
+#define MMDC_MPRDDLCTL_OFFSET	(0x848)
+#define MMDC_MPRDDLST_OFFSET	(0x84C)
+#define MMDC_MPWRDLCTL_OFFSET	(0x850)
+#define MMDC_MPWRDLST_OFFSET	(0x854)
+#define MMDC_MPSDCTRL_OFFSET	(0x858)
+#define MMDC_MPZQLP2CTL_OFFSET	(0x85C)
+#define MMDC_MPRDDLHWCTL_OFFSET	(0x860)
+#define MMDC_MPWRDLHWCTL_OFFSET	(0x864)
+#define MMDC_MPRDDLHWST0_OFFSET	(0x868)
+#define MMDC_MPRDDLHWST1_OFFSET	(0x86C)
+#define MMDC_MPWRDLHWST0_OFFSET	(0x870)
+#define MMDC_MPWRDLHWST1_OFFSET	(0x874)
+#define MMDC_MPWLHWERR_OFFSET	(0x878)
+#define MMDC_MPDGHWST0_OFFSET	(0x87C)
+#define MMDC_MPDGHWST1_OFFSET	(0x880)
+#define MMDC_MPDGHWST2_OFFSET	(0x884)
+#define MMDC_MPDGHWST3_OFFSET	(0x888)
+#define MMDC_MPPDCMPR1_OFFSET	(0x88C)
+#define MMDC_MPPDCMPR2_OFFSET	(0x890)
+#define MMDC_MPSWDAR_OFFSET	(0x894)
+#define MMDC_MPSWDRDR0_OFFSET	(0x898)
+#define MMDC_MPSWDRDR1_OFFSET	(0x89C)
+#define MMDC_MPSWDRDR2_OFFSET	(0x8A0)
+#define MMDC_MPSWDRDR3_OFFSET	(0x8A4)
+#define MMDC_MPSWDRDR4_OFFSET	(0x8A8)
+#define MMDC_MPSWDRDR5_OFFSET	(0x8AC)
+#define MMDC_MPSWDRDR6_OFFSET	(0x8B0)
+#define MMDC_MPSWDRDR7_OFFSET	(0x8B4)
+#define MMDC_MPMUR_OFFSET	(0x8B8)
+#define MMDC_MPWRCADL_OFFSET	(0x8BC)
+#define MMDC_MPDCCR_OFFSET	(0x8C0)
+#define MMDC_MPBC_OFFSET	(0x8C4)
+#define MMDC_MPSWDRAR_OFFSET	(0x8C8)
+
+/* First MMDC invalid IPS address */
+#define MMDC_IPS_ILL_ADDR_START_OFFSET	(0x8CC)
+#define MMDC_REGS_BASE			MMDC0_RBASE
+
+#define MMDC_MDCTL	((MMDC_REGS_BASE + MMDC_MDCTL_OFFSET))
+#define MMDC_MDPDC	((MMDC_REGS_BASE + MMDC_MDPDC_OFFSET))
+#define MMDC_MDOTC	((MMDC_REGS_BASE + MMDC_MDOTC_OFFSET))
+#define MMDC_MDCFG0	((MMDC_REGS_BASE + MMDC_MDCFG0_OFFSET))
+#define MMDC_MDCFG1	((MMDC_REGS_BASE + MMDC_MDCFG1_OFFSET))
+#define MMDC_MDCFG2	((MMDC_REGS_BASE + MMDC_MDCFG2_OFFSET))
+#define MMDC_MDMISC	((MMDC_REGS_BASE + MMDC_MDMISC_OFFSET))
+#define MMDC_MDSCR	((MMDC_REGS_BASE + MMDC_MDSCR_OFFSET))
+#define MMDC_MDREF	((MMDC_REGS_BASE + MMDC_MDREF_OFFSET))
+#define MMDC_MDRWD	((MMDC_REGS_BASE + MMDC_MDRWD_OFFSET))
+#define MMDC_MDOR	((MMDC_REGS_BASE + MMDC_MDOR_OFFSET))
+#define MMDC_MDMRR	((MMDC_REGS_BASE + MMDC_MDMRR_OFFSET))
+#define MMDC_MDCFG3LP	((MMDC_REGS_BASE + MMDC_MDCFG3LP_OFFSET))
+#define MMDC_MDMR4	((MMDC_REGS_BASE + MMDC_MDMR4_OFFSET))
+#define MMDC_MDASP	((MMDC_REGS_BASE + MMDC_MDASP_OFFSET))
+
+#define MMDC_MAARCR	((MMDC_REGS_BASE + MMDC_MAARCR_OFFSET))
+#define MMDC_MAPSR	((MMDC_REGS_BASE + MMDC_MAPSR_OFFSET))
+#define MMDC_MAEXIDR0	((MMDC_REGS_BASE + MMDC_MAEXIDR0_OFFSET))
+#define MMDC_MAEXIDR1	((MMDC_REGS_BASE + MMDC_MAEXIDR1_OFFSET))
+#define MMDC_MADPCR0	((MMDC_REGS_BASE + MMDC_MADPCR0_OFFSET))
+#define MMDC_MADPCR1	((MMDC_REGS_BASE + MMDC_MADPCR1_OFFSET))
+#define MMDC_MADPSR0	((MMDC_REGS_BASE + MMDC_MADPSR0_OFFSET))
+#define MMDC_MADPSR1	((MMDC_REGS_BASE + MMDC_MADPSR1_OFFSET))
+#define MMDC_MADPSR2	((MMDC_REGS_BASE + MMDC_MADPSR2_OFFSET))
+#define MMDC_MADPSR3	((MMDC_REGS_BASE + MMDC_MADPSR3_OFFSET))
+#define MMDC_MADPSR4	((MMDC_REGS_BASE + MMDC_MADPSR4_OFFSET))
+#define MMDC_MADPSR5	((MMDC_REGS_BASE + MMDC_MADPSR5_OFFSET))
+#define MMDC_MASBS0	((MMDC_REGS_BASE + MMDC_MASBS0_OFFSET))
+#define MMDC_MASBS1	((MMDC_REGS_BASE + MMDC_MASBS1_OFFSET))
+#define MMDC_MAGENP	((MMDC_REGS_BASE + MMDC_MAGENP_OFFSET))
+
+#define MMDC_MPZQHWCTRL		((MMDC_REGS_BASE + MMDC_MPZQHWCTRL_OFFSET))
+#define MMDC_MPZQSWCTRL		((MMDC_REGS_BASE + MMDC_MPZQSWCTRL_OFFSET))
+#define MMDC_MPWLGCR		((MMDC_REGS_BASE + MMDC_MPWLGCR_OFFSET))
+#define MMDC_MPWLDECTRL0	((MMDC_REGS_BASE + MMDC_MPWLDECTRL0_OFFSET))
+#define MMDC_MPWLDECTRL1	((MMDC_REGS_BASE + MMDC_MPWLDECTRL1_OFFSET))
+#define MMDC_MPWLDLST		((MMDC_REGS_BASE + MMDC_MPWLDLST_OFFSET))
+#define MMDC_MPODTCTRL		((MMDC_REGS_BASE + MMDC_MPODTCTRL_OFFSET))
+#define MMDC_MPREDQBY0DL	((MMDC_REGS_BASE + MMDC_MPREDQBY0DL_OFFSET))
+#define MMDC_MPREDQBY1DL	((MMDC_REGS_BASE + MMDC_MPREDQBY1DL_OFFSET))
+#define MMDC_MPREDQBY2DL	((MMDC_REGS_BASE + MMDC_MPREDQBY2DL_OFFSET))
+#define MMDC_MPREDQBY3DL	((MMDC_REGS_BASE + MMDC_MPREDQBY3DL_OFFSET))
+#define MMDC_MPWRDQBY0DL	((MMDC_REGS_BASE + MMDC_MPWRDQBY0DL_OFFSET))
+#define MMDC_MPWRDQBY1DL	((MMDC_REGS_BASE + MMDC_MPWRDQBY1DL_OFFSET))
+#define MMDC_MPWRDQBY2DL	((MMDC_REGS_BASE + MMDC_MPWRDQBY2DL_OFFSET))
+#define MMDC_MPWRDQBY3DL	((MMDC_REGS_BASE + MMDC_MPWRDQBY3DL_OFFSET))
+#define MMDC_MPDGCTRL0		((MMDC_REGS_BASE + MMDC_MPDGCTRL0_OFFSET))
+#define MMDC_MPDGCTRL1		((MMDC_REGS_BASE + MMDC_MPDGCTRL1_OFFSET))
+#define MMDC_MPDGDLST		((MMDC_REGS_BASE + MMDC_MPDGDLST_OFFSET))
+#define MMDC_MPRDDLCTL		((MMDC_REGS_BASE + MMDC_MPRDDLCTL_OFFSET))
+#define MMDC_MPRDDLST		((MMDC_REGS_BASE + MMDC_MPRDDLST_OFFSET))
+#define MMDC_MPWRDLCTL		((MMDC_REGS_BASE + MMDC_MPWRDLCTL_OFFSET))
+#define MMDC_MPWRDLST		((MMDC_REGS_BASE + MMDC_MPWRDLST_OFFSET))
+#define MMDC_MPSDCTRL		((MMDC_REGS_BASE + MMDC_MPSDCTRL_OFFSET))
+#define MMDC_MPZQLP2CTL		((MMDC_REGS_BASE + MMDC_MPZQLP2CTL_OFFSET))
+#define MMDC_MPRDDLHWCTL	((MMDC_REGS_BASE + MMDC_MPRDDLHWCTL_OFFSET))
+#define MMDC_MPWRDLHWCTL	((MMDC_REGS_BASE + MMDC_MPWRDLHWCTL_OFFSET))
+#define MMDC_MPRDDLHWST0	((MMDC_REGS_BASE + MMDC_MPRDDLHWST0_OFFSET))
+#define MMDC_MPRDDLHWST1	((MMDC_REGS_BASE + MMDC_MPRDDLHWST1_OFFSET))
+#define MMDC_MPWRDLHWST0	((MMDC_REGS_BASE + MMDC_MPWRDLHWST0_OFFSET))
+#define MMDC_MPWRDLHWST1	((MMDC_REGS_BASE + MMDC_MPWRDLHWST1_OFFSET))
+#define MMDC_MPWLHWERR		((MMDC_REGS_BASE + MMDC_MPWLHWERR_OFFSET))
+#define MMDC_MPDGHWST0		((MMDC_REGS_BASE + MMDC_MPDGHWST0_OFFSET))
+#define MMDC_MPDGHWST1		((MMDC_REGS_BASE + MMDC_MPDGHWST1_OFFSET))
+#define MMDC_MPDGHWST2		((MMDC_REGS_BASE + MMDC_MPDGHWST2_OFFSET))
+#define MMDC_MPDGHWST3		((MMDC_REGS_BASE + MMDC_MPDGHWST3_OFFSET))
+#define MMDC_MPPDCMPR1		((MMDC_REGS_BASE + MMDC_MPPDCMPR1_OFFSET))
+#define MMDC_MPPDCMPR2		((MMDC_REGS_BASE + MMDC_MPPDCMPR2_OFFSET))
+#define MMDC_MPSWDAR		((MMDC_REGS_BASE + MMDC_MPSWDAR_OFFSET))
+#define MMDC_MPSWDRDR0		((MMDC_REGS_BASE + MMDC_MPSWDRDR0_OFFSET))
+#define MMDC_MPSWDRDR1		((MMDC_REGS_BASE + MMDC_MPSWDRDR1_OFFSET))
+#define MMDC_MPSWDRDR2		((MMDC_REGS_BASE + MMDC_MPSWDRDR2_OFFSET))
+#define MMDC_MPSWDRDR3		((MMDC_REGS_BASE + MMDC_MPSWDRDR3_OFFSET))
+#define MMDC_MPSWDRDR4		((MMDC_REGS_BASE + MMDC_MPSWDRDR4_OFFSET))
+#define MMDC_MPSWDRDR5		((MMDC_REGS_BASE + MMDC_MPSWDRDR5_OFFSET))
+#define MMDC_MPSWDRDR6		((MMDC_REGS_BASE + MMDC_MPSWDRDR6_OFFSET))
+#define MMDC_MPSWDRDR7		((MMDC_REGS_BASE + MMDC_MPSWDRDR7_OFFSET))
+#define MMDC_MPMUR		((MMDC_REGS_BASE + MMDC_MPMUR_OFFSET))
+#define MMDC_MPWRCADL		((MMDC_REGS_BASE + MMDC_MPWRCADL_OFFSET))
+#define MMDC_MPDCCR		((MMDC_REGS_BASE + MMDC_MPDCCR_OFFSET))
+#define MMDC_MPBC		((MMDC_REGS_BASE + MMDC_MPBC_OFFSET))
+#define MMDC_MPSWDRAR		((MMDC_REGS_BASE + MMDC_MPSWDRAR_OFFSET))
+
+/* MMDC registers bit defines */
+#define MMDC_MDCTL_SDE_0		(31)
+#define MMDC_MDCTL_SDE_1		(30)
+#define MMDC_MDCTL_ROW			(24)
+#define MMDC_MDCTL_COL			(20)
+#define MMDC_MDCTL_BL			(19)
+#define MMDC_MDCTL_DSIZ			(16)
+
+/* MDMISC */
+#define MMDC_MDMISC_CS0_RDY		(31)
+#define MMDC_MDMISC_CS1_RDY		(30)
+#define MMDC_MDMISC_CK1_DEL		(22)
+#define MMDC_MDMISC_CK1_GATING		(21)
+#define MMDC_MDMISC_CALIB_PER_CS	(20)
+#define MMDC_MDMISC_ADDR_MIRROR		(19)
+#define MMDC_MDMISC_LHD			(18)
+#define MMDC_MDMISC_WALAT		(16)
+#define MMDC_MDMISC_BI			(12)
+#define MMDC_MDMISC_LPDDR2_S		(11)
+#define MMDC_MDMISC_MIF3_MODE		(9)
+#define MMDC_MDMISC_RALAT		(6)
+#define MMDC_MDMISC_DDR_4_BANK		(5)
+#define MMDC_MDMISC_DDR_TYPE		(3)
+#define MMDC_MDMISC_RST			(1)
+
+/* MPWLGCR */
+#define MMDC_MPWLGCR_WL_HW_ERR		(8)
+
+/* MDSCR */
+#define MMDC_MDSCR_CMD_ADDR_MSB		(24)
+#define MMDC_MDSCR_MR_OP		(24)
+#define MMDC_MDSCR_CMD_ADDR_LSB		(16)
+#define MMDC_MDSCR_MR_ADDR		(16)
+#define MMDC_MDSCR_CON_REQ		(15)
+#define MMDC_MDSCR_CON_ACK		(14)
+#define MMDC_MDSCR_MRR_READ_DATA_VALID	(10)
+#define MMDC_MDSCR_WL_EN		(9)
+#define MMDC_MDSCR_CMD			(4)
+#define MMDC_MDSCR_CMD_CS		(3)
+#define MMDC_MDSCR_CMD_BA		(0)
+
+/* MPZQHWCTRL */
+#define MMDC_MPZQHWCTRL_ZQ_HW_FOR	(16)
+#define MMDC_MPZQHWCTRL_ZQ_MODE		(0)
+
+/* MPZQSWCTRL */
+#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP	(16)
+#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL	(13)
+#define MMDC_MPZQSWCTRL_ZQ_SW_PD	(12)
+#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL	(7)
+#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL	(2)
+#define MMDC_MPZQSWCTRL_ZQ_SW_RES	(1)
+#define MMDC_MPZQSWCTRL_ZQ_SW_FOR	(0)
+
+/* MPDGCTRL0 */
+#define MMDC_MPDGCTRL0_RST_RD_FIFO	(31)
+#define MMDC_MPDGCTRL0_DG_CMP_CYC	(30)
+#define MMDC_MPDGCTRL0_DG_DIS		(29)
+#define MMDC_MPDGCTRL0_HW_DG_EN		(28)
+#define MMDC_MPDGCTRL0_HW_DG_ERR	(12)
+
+/* MPRDDLHWCTL */
+#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC	(5)
+#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN		(4)
+#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR		(0)
+
+/* MPWRDLHWCTL */
+#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC	(5)
+#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN		(4)
+#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR		(0)
+
+/* MPSWDAR */
+#define MMDC_MPSWDAR_TEST_DUMMY_EN	(6)
+#define MMDC_MPSWDAR_SW_DUM_CMP3	(5)
+#define MMDC_MPSWDAR_SW_DUM_CMP2	(4)
+#define MMDC_MPSWDAR_SW_DUM_CMP1	(3)
+#define MMDC_MPSWDAR_SW_DUM_CMP0	(2)
+#define MMDC_MPSWDAR_SW_DUMMY_RD	(1)
+#define MMDC_MPSWDAR_SW_DUMMY_WR	(0)
+
+/* MADPCR0 */
+#define MMDC_MADPCR0_SBS		(9)
+#define MMDC_MADPCR0_SBS_EN		(8)
+
+/* MASBS1 */
+#define MMDC_MASBS1_SBS_VLD		(0)
+#define MMDC_MASBS1_SBS_TYPE		(1)
+
+/* MDREF */
+#define MMDC_MDREF_REF_CNT		(16)
+#define MMDC_MDREF_REF_SEL		(14)
+#define MMDC_MDREF_REFR			(11)
+#define MMDC_MDREF_START_REF		(0)
+
+/* MPWLGCR */
+#define MMDC_MPWLGCR_HW_WL_EN		(0)
+
+/* MPBC */
+#define MMDC_MPBC_BIST_DM_LP_EN		(0)
+#define MMDC_MPBC_BIST_CA0_LP_EN	(1)
+#define MMDC_MPBC_BIST_DQ0_LP_EN	(3)
+#define MMDC_MPBC_BIST_DQ1_LP_EN	(4)
+#define MMDC_MPBC_BIST_DQ2_LP_EN	(5)
+#define MMDC_MPBC_BIST_DQ3_LP_EN	(6)
+
+/* MPMUR */
+#define MMDC_MPMUR_FRC_MSR		(11)
+
+/* MPODTCTRL */
+#define MMDC_MPODTCTRL_ODT_RD_ACT_EN	(3)
+#define MMDC_MPODTCTRL_ODT_RD_PAS_EN	(2)
+#define MMDC_MPODTCTRL_ODT_WR_ACT_EN	(1)
+#define MMDC_MPODTCTRL_ODT_WR_PAS_EN	(0)
+
+/* MAPSR */
+#define MMDC_MAPSR_DVACK		(25)
+#define MMDC_MAPSR_LPACK		(24)
+#define MMDC_MAPSR_DVFS			(21)
+#define MMDC_MAPSR_LPMD			(20)
+
+/* MAARCR */
+#define MMDC_MAARCR_ARCR_EXC_ERR_EN	(28)
+
+/* MPZQLP2CTL */
+#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS	(24)
+#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL	(16)
+#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT	(0)
+
+/* MDCFG3LP */
+#define MMDC_MDCFG3LP_tRC_LP		(16)
+#define MMDC_MDCFG3LP_tRCD_LP		(8)
+#define MMDC_MDCFG3LP_tRPpb_LP		(4)
+#define MMDC_MDCFG3LP_tRPab_LP		(0)
+
+/* MDOR */
+#define MMDC_MDOR_tXPR			(16)
+#define MMDC_MDOR_SDE_to_RST		(8)
+#define MMDC_MDOR_RST_to_CKE		(0)
+
+/* MDCFG0 */
+#define MMDC_MDCFG0_tRFC		(24)
+#define MMDC_MDCFG0_tXS			(16)
+#define MMDC_MDCFG0_tXP			(13)
+#define MMDC_MDCFG0_tXPDLL		(9)
+#define MMDC_MDCFG0_tFAW		(4)
+#define MMDC_MDCFG0_tCL			(0)
+
+/* MDCFG1 */
+#define MMDC_MDCFG1_tRCD		(29)
+#define MMDC_MDCFG1_tRP			(26)
+#define MMDC_MDCFG1_tRC			(21)
+#define MMDC_MDCFG1_tRAS		(16)
+#define MMDC_MDCFG1_tRPA		(15)
+#define MMDC_MDCFG1_tWR			(9)
+#define MMDC_MDCFG1_tMRD		(5)
+#define MMDC_MDCFG1_tCWL		(0)
+
+/* MDCFG2 */
+#define MMDC_MDCFG2_tDLLK		(16)
+#define MMDC_MDCFG2_tRTP		(6)
+#define MMDC_MDCFG2_tWTR		(3)
+#define MMDC_MDCFG2_tRRD		(0)
+
+/* MDRWD */
+#define MMDC_MDRWD_tDAI			(16)
+#define MMDC_MDRWD_RTW_SAME		(12)
+#define MMDC_MDRWD_WTR_DIFF		(9)
+#define MMDC_MDRWD_WTW_DIFF		(6)
+#define MMDC_MDRWD_RTW_DIFF		(3)
+#define MMDC_MDRWD_RTR_DIFF		(0)
+
+/* MDPDC */
+#define MMDC_MDPDC_PRCT_1		(28)
+#define MMDC_MDPDC_PRCT_0		(24)
+#define MMDC_MDPDC_tCKE			(16)
+#define MMDC_MDPDC_PWDT_1		(12)
+#define MMDC_MDPDC_PWDT_0		(8)
+#define MMDC_MDPDC_SLOW_PD		(7)
+#define MMDC_MDPDC_BOTH_CS_PD		(6)
+#define MMDC_MDPDC_tCKSRX		(3)
+#define MMDC_MDPDC_tCKSRE		(0)
+
+/* MDASP */
+#define MMDC_MDASP_CS0_END		(0)
+
+/* MAEXIDR0 */
+#define MMDC_MAEXIDR0_EXC_ID_MONITOR1	(16)
+#define MMDC_MAEXIDR0_EXC_ID_MONITOR0	(0)
+
+/* MAEXIDR1 */
+#define MMDC_MAEXIDR1_EXC_ID_MONITOR3	(16)
+#define MMDC_MAEXIDR1_EXC_ID_MONITOR2	(0)
+
+/* MPWRDLCTL */
+#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3	(24)
+#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2	(16)
+#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1	(8)
+#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0	(0)
+
+/* MPRDDLCTL */
+#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3	(24)
+#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2	(16)
+#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1	(8)
+#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0	(0)
+
+/* MPWRDQBY0DL */
+#define MMDC_MPWRDQBY0DL_WR_DM0_DEL	(30)
+#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL	(28)
+#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL	(24)
+#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL	(20)
+#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL	(16)
+#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL	(12)
+#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL	(8)
+#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL	(4)
+#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL	(0)
+
+/* MPWRDQBY1DL */
+#define MMDC_MPWRDQBY1DL_WR_DM1_DEL	(30)
+#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL	(28)
+#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL	(24)
+#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL	(20)
+#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL	(16)
+#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL	(12)
+#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL	(8)
+#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL	(4)
+#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL	(0)
+
+/* MPWRDQBY2DL */
+#define MMDC_MPWRDQBY2DL_WR_DM2_DEL	(30)
+#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL	(28)
+#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL	(24)
+#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL	(20)
+#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL	(16)
+#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL	(12)
+#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL	(8)
+#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL	(4)
+#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL	(0)
+
+/* MPWRDQBY3DL */
+#define MMDC_MPWRDQBY3DL_WR_DM3_DEL	(30)
+#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL	(28)
+#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL	(24)
+#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL	(20)
+#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL	(16)
+#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL	(12)
+#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL	(8)
+#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL	(4)
+#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL	(0)
+
+/* Fields masks */
+#define MMDC_MDCTL_SDE_0_MASK	((0x1 << MMDC_MDCTL_SDE_0))
+#define MMDC_MDCTL_SDE_1_MASK	((0x1 << MMDC_MDCTL_SDE_1))
+#define MMDC_MDCTL_BL_MASK	((0x1 << MMDC_MDCTL_BL))
+#define MMDC_MDCTL_ROW_MASK	((0x7 << MMDC_MDCTL_ROW))
+#define MMDC_MDCTL_COL_MASK	((0x7 << MMDC_MDCTL_COL))
+#define MMDC_MDCTL_DSIZ_MASK	((0x3 << MMDC_MDCTL_DSIZ))
+
+/* MDMISC */
+#define MMDC_MDMISC_CS0_RDY_MASK	((0x1 << MMDC_MDMISC_CS0_RDY))
+#define MMDC_MDMISC_CS1_RDY_MASK	((0x1 << MMDC_MDMISC_CS1_RDY))
+#define MMDC_MDMISC_CK1_DEL_MASK	((0x3 << MMDC_MDMISC_CK1_DEL))
+#define MMDC_MDMISC_CK1_GATING_MASK	((0x1 << MMDC_MDMISC_CK1_GATING))
+#define MMDC_MDMISC_CALIB_PER_CS_MASK	((0x1 << MMDC_MDMISC_CALIB_PER_CS))
+#define MMDC_MDMISC_ADDR_MIRROR_MASK	((0x1 << MMDC_MDMISC_ADDR_MIRROR))
+#define MMDC_MDMISC_LHD_MASK		((0x1 << MMDC_MDMISC_LHD))
+#define MMDC_MDMISC_WALAT_MASK		((0x3 << MMDC_MDMISC_WALAT))
+#define MMDC_MDMISC_BI_MASK		((0x1 << MMDC_MDMISC_BI))
+#define MMDC_MDMISC_LPDDR2_S_MASK	((0x1 << MMDC_MDMISC_LPDDR2_S))
+#define MMDC_MDMISC_MIF3_MODE_MASK	((0x3 << MMDC_MDMISC_MIF3_MODE))
+#define MMDC_MDMISC_RALAT_MASK		((0x7 << MMDC_MDMISC_RALAT))
+#define MMDC_MDMISC_DDR_4_BANK_MASK	((0x1 << MMDC_MDMISC_DDR_4_BANK))
+#define MMDC_MDMISC_DDR_TYPE_MASK	((0x3 << MMDC_MDMISC_DDR_TYPE))
+#define MMDC_MDMISC_RST_MASK		((0x1 << MMDC_MDMISC_RST))
+
+/* MPWLGCR */
+#define MMDC_MPWLGCR_WL_HW_ERR_MASK	((0xf << MMDC_MPWLGCR_WL_HW_ERR))
+
+/* MDSCR */
+#define MMDC_MDSCR_CMD_ADDR_MSB_MASK	((0xff << MMDC_MDSCR_CMD_ADDR_MSB))
+#define MMDC_MDSCR_MR_OP_MASK		((0xff << MMDC_MDSCR_MR_OP))
+#define MMDC_MDSCR_CMD_ADDR_LSB_MASK	((0xff << MMDC_MDSCR_CMD_ADDR_LSB))
+#define MMDC_MDSCR_MR_ADDR_MASK		((0xff << MMDC_MDSCR_MR_ADDR))
+#define MMDC_MDSCR_CON_REQ_MASK		((0x1  << MMDC_MDSCR_CON_REQ))
+#define MMDC_MDSCR_CON_ACK_MASK		((0x1  << MMDC_MDSCR_CON_ACK))
+#define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK	((0x1  << MMDC_MDSCR_MRR_READ_DATA_VALID))
+#define MMDC_MDSCR_WL_EN_MASK		((0x1  << MMDC_MDSCR_WL_EN))
+#define MMDC_MDSCR_CMD_MASK		((0x7  << MMDC_MDSCR_CMD))
+#define MMDC_MDSCR_CMD_CS_MASK		((0x1  << MMDC_MDSCR_CMD_CS))
+#define MMDC_MDSCR_CMD_BA_MASK		((0x7  << MMDC_MDSCR_CMD_BA))
+
+/* MPZQHWCTRL */
+#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK	((0x1 << MMDC_MPZQHWCTRL_ZQ_HW_FOR))
+#define MMDC_MPZQHWCTRL_ZQ_MODE_MASK	((0x3 << MMDC_MPZQHWCTRL_ZQ_MODE))
+
+/* MPZQSWCTRL */
+#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK	((0x3  << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP))
+#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK	((0x1  << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL))
+#define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK		((0x1  << MMDC_MPZQSWCTRL_ZQ_SW_PD))
+#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK	((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL))
+#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK	((0x1f << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL))
+#define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK		((0x1  << MMDC_MPZQSWCTRL_ZQ_SW_RES))
+#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK		((0x1  << MMDC_MPZQSWCTRL_ZQ_SW_FOR))
+
+/* MPDGCTRL0 */
+#define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK		((0x1 << MMDC_MPDGCTRL0_RST_RD_FIFO))
+#define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK		((0x1 << MMDC_MPDGCTRL0_DG_CMP_CYC))
+#define MMDC_MPDGCTRL0_DG_DIS_MASK		((0x1 << MMDC_MPDGCTRL0_DG_DIS))
+#define MMDC_MPDGCTRL0_HW_DG_EN_MASK		((0x1 << MMDC_MPDGCTRL0_HW_DG_EN))
+#define MMDC_MPDGCTRL0_HW_DG_ERR_MASK		((0x1 << MMDC_MPDGCTRL0_HW_DG_ERR))
+
+/* MPRDDLHWCTL */
+#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK	((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC))
+#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK	((0x1 << MMDC_MPRDDLHWCTL_HW_RD_DL_EN))
+#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR_MASK	((0xf << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR))
+
+/* MPWRDLHWCTL */
+#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK	((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC))
+#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK	((0x1 << MMDC_MPWRDLHWCTL_HW_WR_DL_EN))
+#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR_MASK	((0xf << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR))
+
+/* MPSWDAR */
+#define MMDC_MPSWDAR_TEST_DUMMY_EN_MASK	((0x1 << MMDC_MPSWDAR_TEST_DUMMY_EN))
+#define MMDC_MPSWDAR_SW_DUM_CMP3_MASK	((0x1 << MMDC_MPSWDAR_SW_DUM_CMP3))
+#define MMDC_MPSWDAR_SW_DUM_CMP2_MASK	((0x1 << MMDC_MPSWDAR_SW_DUM_CMP2))
+#define MMDC_MPSWDAR_SW_DUM_CMP1_MASK	((0x1 << MMDC_MPSWDAR_SW_DUM_CMP1))
+#define MMDC_MPSWDAR_SW_DUM_CMP0_MASK	((0x1 << MMDC_MPSWDAR_SW_DUM_CMP0))
+#define MMDC_MPSWDAR_SW_DUMMY_RD_MASK	((0x1 << MMDC_MPSWDAR_SW_DUMMY_RD))
+#define MMDC_MPSWDAR_SW_DUMMY_WR_MASK	((0x1 << MMDC_MPSWDAR_SW_DUMMY_WR))
+
+/* MADPCR0 */
+#define MMDC_MADPCR0_SBS_MASK		((0x1 << MMDC_MADPCR0_SBS))
+#define MMDC_MADPCR0_SBS_EN_MASK	((0x1 << MMDC_MADPCR0_SBS_EN))
+
+/* MASBS1 */
+#define MMDC_MASBS1_SBS_VLD_MASK	((0x1 << MMDC_MASBS1_SBS_VLD))
+#define MMDC_MASBS1_SBS_TYPE_MASK	((0x1 << MMDC_MASBS1_SBS_TYPE))
+
+/* MDREF */
+#define MMDC_MDREF_REF_CNT_MASK		((0xffff << MMDC_MDREF_REF_CNT))
+#define MMDC_MDREF_REF_SEL_MASK		((0x3    << MMDC_MDREF_REF_SEL))
+#define MMDC_MDREF_REFR_MASK		((0x7    << MMDC_MDREF_REFR))
+#define MMDC_MDREF_START_REF_MASK	((0x1    << MMDC_MDREF_START_REF))
+
+/* MPWLGCR */
+#define MMDC_MPWLGCR_HW_WL_EN_MASK	((0x1 << MMDC_MPWLGCR_HW_WL_EN))
+
+/* MPBC */
+#define MMDC_MPBC_BIST_DM_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_DM_LP_EN))
+#define MMDC_MPBC_BIST_CA0_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_CA0_LP_EN))
+#define MMDC_MPBC_BIST_DQ0_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_DQ0_LP_EN))
+#define MMDC_MPBC_BIST_DQ1_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_DQ1_LP_EN))
+#define MMDC_MPBC_BIST_DQ2_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_DQ2_LP_EN))
+#define MMDC_MPBC_BIST_DQ3_LP_EN_MASK	((0x1 << MMDC_MPBC_BIST_DQ3_LP_EN))
+#define MMDC_MPBC_BIST_DQ_LP_EN_MASK	((0xf << MMDC_MPBC_BIST_DQ0_LP_EN))
+
+/* MPMUR */
+#define MMDC_MPMUR_FRC_MSR_MASK		((0x1 << MMDC_MPMUR_FRC_MSR))
+
+/* MPODTCTRL */
+#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK	((0x1 << MMDC_MPODTCTRL_ODT_RD_ACT_EN))
+#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK	((0x1 << MMDC_MPODTCTRL_ODT_RD_PAS_EN))
+#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK	((0x1 << MMDC_MPODTCTRL_ODT_WR_ACT_EN))
+#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK	((0x1 << MMDC_MPODTCTRL_ODT_WR_PAS_EN))
+
+/* MAPSR */
+#define MMDC_MAPSR_DVACK_MASK		((0x1 << MMDC_MAPSR_DVACK))
+#define MMDC_MAPSR_LPACK_MASK		((0x1 << MMDC_MAPSR_LPACK))
+#define MMDC_MAPSR_DVFS_MASK		((0x1 << MMDC_MAPSR_DVFS))
+#define MMDC_MAPSR_LPMD_MASK		((0x1 << MMDC_MAPSR_LPMD))
+
+/* MAARCR */
+#define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK	((0x1 << MMDC_MAARCR_ARCR_EXC_ERR_EN))
+
+/* MPZQLP2CTL */
+#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK	((0x7f  << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS))
+#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK	((0xff  << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL))
+#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK	((0x1ff << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT))
+
+/* MDCFG3LP */
+#define MMDC_MDCFG3LP_tRC_LP_MASK	((0x3f  << MMDC_MDCFG3LP_tRC_LP))
+#define MMDC_MDCFG3LP_tRCD_LP_MASK	((0xf   << MMDC_MDCFG3LP_tRCD_LP))
+#define MMDC_MDCFG3LP_tRPpb_LP_MASK	((0xf   << MMDC_MDCFG3LP_tRPpb_LP))
+#define MMDC_MDCFG3LP_tRPab_LP_MASK	((0xf   << MMDC_MDCFG3LP_tRPab_LP))
+
+/* MDOR */
+#define MMDC_MDOR_tXPR_MASK		((0xff  << MMDC_MDOR_tXPR))
+#define MMDC_MDOR_SDE_to_RST_MASK	((0x3f  << MMDC_MDOR_SDE_to_RST))
+#define MMDC_MDOR_RST_to_CKE_MASK	((0x3f  << MMDC_MDOR_RST_to_CKE))
+
+/* MDCFG0 */
+#define MMDC_MDCFG0_tRFC_MASK		((0xff  << MMDC_MDCFG0_tRFC))
+#define MMDC_MDCFG0_tXS_MASK		((0xff  << MMDC_MDCFG0_tXS))
+#define MMDC_MDCFG0_tXP_MASK		((0x7   << MMDC_MDCFG0_tXP))
+#define MMDC_MDCFG0_tXPDLL_MASK		((0xf   << MMDC_MDCFG0_tXPDLL))
+#define MMDC_MDCFG0_tFAW_MASK		((0x1f  << MMDC_MDCFG0_tFAW))
+#define MMDC_MDCFG0_tCL_MASK		((0xf   << MMDC_MDCFG0_tCL))
+
+/* MDCFG1 */
+#define MMDC_MDCFG1_tRCD_MASK		((0x7   << MMDC_MDCFG1_tRCD))
+#define MMDC_MDCFG1_tRP_MASK		((0x7   << MMDC_MDCFG1_tRP))
+#define MMDC_MDCFG1_tRC_MASK		((0x1f  << MMDC_MDCFG1_tRC))
+#define MMDC_MDCFG1_tRAS_MASK		((0x1f  << MMDC_MDCFG1_tRAS))
+#define MMDC_MDCFG1_tRPA_MASK		((0x1   << MMDC_MDCFG1_tRPA))
+#define MMDC_MDCFG1_tWR_MASK		((0x7   << MMDC_MDCFG1_tWR))
+#define MMDC_MDCFG1_tMRD_MASK		((0xf   << MMDC_MDCFG1_tMRD))
+#define MMDC_MDCFG1_tCWL_MASK		((0x7   << MMDC_MDCFG1_tCWL))
+
+/* MDCFG2 */
+#define MMDC_MDCFG2_tDLLK_MASK		((0x1ff << MMDC_MDCFG2_tDLLK))
+#define MMDC_MDCFG2_tRTP_MASK		((0x7   << MMDC_MDCFG2_tRTP))
+#define MMDC_MDCFG2_tWTR_MASK		((0x7   << MMDC_MDCFG2_tWTR))
+#define MMDC_MDCFG2_tRRD_MASK		((0x7   << MMDC_MDCFG2_tRRD))
+
+/* MDRWD */
+#define MMDC_MDRWD_tDAI_MASK		((0x1fff << MMDC_MDRWD_tDAI))
+#define MMDC_MDRWD_RTW_SAME_MASK	((0x7    << MMDC_MDRWD_RTW_SAME))
+#define MMDC_MDRWD_WTR_DIFF_MASK	((0x7    << MMDC_MDRWD_WTR_DIFF))
+#define MMDC_MDRWD_WTW_DIFF_MASK	((0x7    << MMDC_MDRWD_WTW_DIFF))
+#define MMDC_MDRWD_RTW_DIFF_MASK	((0x7    << MMDC_MDRWD_RTW_DIFF))
+#define MMDC_MDRWD_RTR_DIFF_MASK	((0x7    << MMDC_MDRWD_RTR_DIFF))
+
+/* MDPDC */
+#define MMDC_MDPDC_PRCT_1_MASK		((0x7    << MMDC_MDPDC_PRCT_1))
+#define MMDC_MDPDC_PRCT_0_MASK		((0x7    << MMDC_MDPDC_PRCT_0))
+#define MMDC_MDPDC_tCKE_MASK		((0x7    << MMDC_MDPDC_tCKE))
+#define MMDC_MDPDC_PWDT_1_MASK		((0xf    << MMDC_MDPDC_PWDT_1))
+#define MMDC_MDPDC_PWDT_0_MASK		((0xf    << MMDC_MDPDC_PWDT_0))
+#define MMDC_MDPDC_SLOW_PD_MASK		((0x1    << MMDC_MDPDC_SLOW_PD))
+#define MMDC_MDPDC_BOTH_CS_PD_MASK	((0x1    << MMDC_MDPDC_BOTH_CS_PD))
+#define MMDC_MDPDC_tCKSRX_MASK		((0x7    << MMDC_MDPDC_tCKSRX))
+#define MMDC_MDPDC_tCKSRE_MASK		((0x7    << MMDC_MDPDC_tCKSRE))
+
+/* MDASP */
+#define MMDC_MDASP_CS0_END_MASK		((0x7f << MMDC_MDASP_CS0_END))
+
+/* MAEXIDR0 */
+#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK	((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR1))
+#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK	((0xffff << MMDC_MAEXIDR0_EXC_ID_MONITOR0))
+
+/* MAEXIDR1 */
+#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK	((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR3))
+#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK	((0xffff << MMDC_MAEXIDR1_EXC_ID_MONITOR2))
+
+/* MPWRDLCTL */
+#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3_MASK	((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET3))
+#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2_MASK	((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET2))
+#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK	((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1))
+#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK	((0x7f << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0))
+
+/* MPRDDLCTL */
+#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3_MASK	((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET3))
+#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2_MASK	((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET2))
+#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK	((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1))
+#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK	((0x7f << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0))
+
+/* MPWRDQBY0DL */
+#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DM0_DEL))
+#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ7_DEL))
+#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ6_DEL))
+#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ5_DEL))
+#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ4_DEL))
+#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ3_DEL))
+#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ2_DEL))
+#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ1_DEL))
+#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK	((0x3f  << MMDC_MPWRDQBY0DL_WR_DQ0_DEL))
+
+/* MPWRDQBY1DL */
+#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DM1_DEL))
+#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ15_DEL))
+#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ14_DEL))
+#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ13_DEL))
+#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ12_DEL))
+#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ11_DEL))
+#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ10_DEL))
+#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ9_DEL))
+#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK	((0x3f  << MMDC_MPWRDQBY1DL_WR_DQ8_DEL))
+
+/* MPWRDQBY2DL */
+#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DM2_DEL))
+#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ23_DEL))
+#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ22_DEL))
+#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ21_DEL))
+#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ20_DEL))
+#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ19_DEL))
+#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ18_DEL))
+#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ17_DEL))
+#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK	((0x3f  << MMDC_MPWRDQBY2DL_WR_DQ16_DEL))
+
+/* MPWRDQBY3DL */
+#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DM3_DEL))
+#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ31_DEL))
+#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ30_DEL))
+#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ29_DEL))
+#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ28_DEL))
+#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ27_DEL))
+#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ26_DEL))
+#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ25_DEL))
+#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK	((0x3f  << MMDC_MPWRDQBY3DL_WR_DQ24_DEL))
+
+#define SNVS_LPCR_DPEN				(0x20)
+#define SNVS_LPCR_SRTC_ENV			(0x1)
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+
+#include <asm/types.h>
+
+struct fuse_word {
+	u32	fuse;
+	u32	rsvd[3];
+};
+
+struct ocotp_regs {
+	u32	ctrl;
+	u32	ctrl_set;
+	u32	ctrl_clr;
+	u32	ctrl_tog;
+	u32	pdn;
+	u32	rsvd0[3];
+	u32	data;
+	u32	rsvd1[3];
+	u32	read_ctrl;
+	u32	rsvd2[3];
+	u32	read_fuse_data;
+	u32	rsvd3[3];
+	u32	sw_sticky;
+	u32	rsvd4[3];
+	u32	scs;
+	u32	scs_set;
+	u32	scs_clr;
+	u32	scs_tog;
+	u32	out_status;
+	u32	out_status_set;
+	u32	out_status_clr;
+	u32	out_status_tog;
+	u32	startword;
+	u32	rsvd5[3];
+	u32	version;
+	u32	rsvd6[19];
+	struct	fuse_word mem_repair[8];
+	u32	rsvd7[0xa8];
+
+	/* fuse banks */
+	struct fuse_bank {
+		u32	fuse_regs[0x20];
+	} bank[0];
+};
+
+struct fuse_bank1_regs {
+	u32	lock0;
+	u32	rsvd0[3];
+	u32	lock1;
+	u32	rsvd1[3];
+	u32	lock2;
+	u32	rsvd2[3];
+	u32	cfg0;
+	u32	rsvd3[3];
+	u32	cfg1;
+	u32	rsvd4[3];
+	u32	cfg2;
+	u32	rsvd5[3];
+	u32	cfg3;
+	u32	rsvd6[3];
+	u32	cfg4;
+	u32	rsvd7[3];
+};
+
+struct fuse_bank2_regs {
+	struct fuse_word boot[8];
+};
+
+struct fuse_bank3_regs {
+	u32	mem0;
+	u32	rsvd0[3];
+	u32	mem1;
+	u32	rsvd1[3];
+	u32	mem2;
+	u32	rsvd2[3];
+	u32	mem3;
+	u32	rsvd3[3];
+	u32	ana0;
+	u32	rsvd4[3];
+	u32	ana1;
+	u32	rsvd5[3];
+	u32	ana2;
+	u32	rsvd6[3];
+	u32	ana3;
+	u32	rsvd7[3];
+};
+
+struct fuse_bank7_regs {
+	u32	sjc_resp0;
+	u32	rsvd0[3];
+	u32	sjc_resp1;
+	u32	rsvd1[3];
+	u32	gp0;
+	u32	rsvd2[3];
+	u32	gp1;
+	u32	rsvd3[3];
+	u32	gp2;
+	u32	rsvd4[3];
+	u32	gp3;
+	u32	rsvd5[3];
+	u32	gp4;
+	u32	rsvd6[3];
+	u32	gp5;
+	u32	rsvd7[3];
+};
+
+struct usbphy_regs {
+	u32	usbphy_pwd;			/* 0x000 */
+	u32	usbphy_pwd_set;			/* 0x004 */
+	u32	usbphy_pwd_clr;			/* 0x008 */
+	u32	usbphy_pwd_tog;			/* 0x00c */
+	u32	usbphy_tx;			/* 0x010 */
+	u32	usbphy_tx_set;			/* 0x014 */
+	u32	usbphy_tx_clr;			/* 0x018 */
+	u32	usbphy_tx_tog;			/* 0x01c */
+	u32	usbphy_rx;			/* 0x020 */
+	u32	usbphy_rx_set;			/* 0x024 */
+	u32	usbphy_rx_clr;			/* 0x028 */
+	u32	usbphy_rx_tog;			/* 0x02c */
+	u32	usbphy_ctrl;			/* 0x030 */
+	u32	usbphy_ctrl_set;		/* 0x034 */
+	u32	usbphy_ctrl_clr;		/* 0x038 */
+	u32	usbphy_ctrl_tog;		/* 0x03c */
+	u32	usbphy_status;			/* 0x040 */
+	u32	reserved0[3];
+	u32	usbphy_debug0;			/* 0x050 */
+	u32	usbphy_debug0_set;		/* 0x054 */
+	u32	usbphy_debug0_clr;		/* 0x058 */
+	u32	usbphy_debug0_tog;		/* 0x05c */
+	u32	reserved1[4];
+	u32	usbphy_debug1;			/* 0x070 */
+	u32	usbphy_debug1_set;		/* 0x074 */
+	u32	usbphy_debug1_clr;		/* 0x078 */
+	u32	usbphy_debug1_tog;		/* 0x07c */
+	u32	usbphy_version;			/* 0x080 */
+	u32	reserved2[7];
+	u32	usb1_pll_480_ctrl;		/* 0x0a0 */
+	u32	usb1_pll_480_ctrl_set;		/* 0x0a4 */
+	u32	usb1_pll_480_ctrl_clr;		/* 0x0a8 */
+	u32	usb1_pll_480_ctrl_tog;		/* 0x0ac */
+	u32	reserved3[4];
+	u32	usb1_vbus_detect;		/* 0xc0 */
+	u32	usb1_vbus_detect_set;		/* 0xc4 */
+	u32	usb1_vbus_detect_clr;		/* 0xc8 */
+	u32	usb1_vbus_detect_tog;		/* 0xcc */
+	u32	usb1_vbus_det_stat;		/* 0xd0 */
+	u32	reserved4[3];
+	u32	usb1_chrg_detect;		/* 0xe0 */
+	u32	usb1_chrg_detect_set;		/* 0xe4 */
+	u32	usb1_chrg_detect_clr;		/* 0xe8 */
+	u32	usb1_chrg_detect_tog;		/* 0xec */
+	u32	usb1_chrg_det_stat;		/* 0xf0 */
+	u32	reserved5[3];
+	u32	usbphy_anactrl;			/* 0x100 */
+	u32	usbphy_anactrl_set;		/* 0x104 */
+	u32	usbphy_anactrl_clr;		/* 0x108 */
+	u32	usbphy_anactrl_tog;		/* 0x10c */
+	u32	usb1_loopback;			/* 0x110 */
+	u32	usb1_loopback_set;		/* 0x114 */
+	u32	usb1_loopback_clr;		/* 0x118 */
+	u32	usb1_loopback_tog;		/* 0x11c */
+	u32	usb1_loopback_hsfscnt;		/* 0x120 */
+	u32	usb1_loopback_hsfscnt_set;	/* 0x124 */
+	u32	usb1_loopback_hsfscnt_clr;	/* 0x128 */
+	u32	usb1_loopback_hsfscnt_tog;	/* 0x12c */
+	u32	usphy_trim_override_en;		/* 0x130 */
+	u32	usphy_trim_override_en_set;	/* 0x134 */
+	u32	usphy_trim_override_en_clr;	/* 0x138 */
+	u32	usphy_trim_override_en_tog;	/* 0x13c */
+	u32	usb1_pfda_ctrl1;		/* 0x140 */
+	u32	usb1_pfda_ctrl1_set;		/* 0x144 */
+	u32	usb1_pfda_ctrl1_clr;		/* 0x148 */
+	u32	usb1_pfda_ctrl1_tog;		/* 0x14c */
+};
+
+struct bootrom_sw_info {
+	u8 reserved_1;
+	u8 boot_dev_instance;
+	u8 boot_dev_type;
+	u8 reserved_2;
+	u32 core_freq;
+	u32 axi_freq;
+	u32 ddr_freq;
+	u32 rom_tick_freq;
+	u32 reserved_3[3];
+};
+
+#define	is_boot_from_usb(void)		(!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
+#define	disconnect_from_pc(void)	writel(0x0, USBOTG0_RBASE + 0x140)
+
+#endif
+
+#endif /* _MX7ULP_REGS_H_*/
diff --git a/arch/arm/include/asm/arch-mx7ulp/iomux.h b/arch/arm/include/asm/arch-mx7ulp/iomux.h
new file mode 100644
index 0000000..f067c02
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/iomux.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on Linux i.MX iomux-v3.h file:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *			<armlinux@phytec.de>
+ *
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __MACH_IOMUX_H__
+#define __MACH_IOMUX_H__
+
+/*
+ *	build IOMUX_PAD structure
+ *
+ * This iomux scheme is based around pads, which are the physical balls
+ * on the processor.
+ *
+ * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
+ *   things like driving strength and pullup/pulldown.
+ * - Each pad can have but not necessarily does have an output routing register
+ *   (IOMUXC_SW_MUX_CTL_PAD_x).
+ * - Each pad can have but not necessarily does have an input routing register
+ *   (IOMUXC_x_SELECT_INPUT)
+ *
+ * The three register sets do not have a fixed offset to each other,
+ * hence we order this table by pad control registers (which all pads
+ * have) and put the optional i/o routing registers into additional
+ * fields.
+ *
+ * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ *
+ * IOMUX/PAD Bit field definitions
+ *
+ * MUX_CTRL_OFS:	                0..15 (16)
+ * SEL_INPUT_OFS:	               16..31 (16)
+ * MUX_MODE:	                   32..37  (6)
+ * SEL_INP:		                   38..41  (4)
+ * PAD_CTRL + NO_PAD_CTRL:         42..60 (19)
+ * reserved:		               61-63      (3)
+*/
+
+typedef u64 iomux_cfg_t;
+
+#define MUX_CTRL_OFS_SHIFT	     0
+#define MUX_CTRL_OFS_MASK	((iomux_cfg_t)0xffff << MUX_CTRL_OFS_SHIFT)
+#define MUX_SEL_INPUT_OFS_SHIFT	16
+#define MUX_SEL_INPUT_OFS_MASK	((iomux_cfg_t)0xffff << \
+	MUX_SEL_INPUT_OFS_SHIFT)
+
+#define MUX_MODE_SHIFT		32
+#define MUX_MODE_MASK		((iomux_cfg_t)0x3f << MUX_MODE_SHIFT)
+#define MUX_SEL_INPUT_SHIFT	38
+#define MUX_SEL_INPUT_MASK	((iomux_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
+#define MUX_PAD_CTRL_SHIFT	42
+#define MUX_PAD_CTRL_MASK	((iomux_cfg_t)0x7ffff << MUX_PAD_CTRL_SHIFT)
+
+#define MUX_PAD_CTRL(x)		((iomux_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+
+#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,	\
+		sel_input, pad_ctrl)					\
+	(((iomux_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT)     |	\
+	((iomux_cfg_t)(mux_mode)      << MUX_MODE_SHIFT)         |	\
+	((iomux_cfg_t)(pad_ctrl)      << MUX_PAD_CTRL_SHIFT)     |	\
+	((iomux_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)|	\
+	((iomux_cfg_t)(sel_input)     << MUX_SEL_INPUT_SHIFT))
+
+#define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | \
+					MUX_PAD_CTRL(pad))
+
+
+#define IOMUX_CONFIG_MPORTS       0x20
+#define MUX_MODE_MPORTS           ((iomux_v3_cfg_t)IOMUX_CONFIG_MPORTS << \
+				MUX_MODE_SHIFT)
+
+/* Bit definition below needs to be fixed acccording to ulp rm */
+
+#define NO_PAD_CTRL		     (1 << 18)
+#define PAD_CTL_OBE_ENABLE	 (1 << 17)
+#define PAD_CTL_IBE_ENABLE	 (1 << 16)
+#define PAD_CTL_DSE          (1 << 6)
+#define PAD_CTL_ODE          (1 << 5)
+#define PAD_CTL_SRE_FAST     (0 << 2)
+#define PAD_CTL_SRE_SLOW     (1 << 2)
+#define PAD_CTL_PUE          (1 << 1)
+#define PAD_CTL_PUS_UP       ((1 << 0) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_DOWN     ((0 << 0) | PAD_CTL_PUE)
+
+
+void mx7ulp_iomux_setup_pad(iomux_cfg_t pad);
+void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
+				      unsigned count);
+#endif	/* __MACH_IOMUX_H__*/
diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h
new file mode 100644
index 0000000..139b766
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h
@@ -0,0 +1,909 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_IMX7ULP_PINS_H__
+#define __ASM_ARCH_IMX7ULP_PINS_H__
+
+#include <asm/arch/iomux.h>
+
+enum {
+	MX7ULP_PAD_PTA0__CMP0_IN1_3V                                 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA0__PTA0                                        = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA0__LPSPI0_PCS1                                 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x2, 0),
+	MX7ULP_PAD_PTA0__LPUART0_CTS_b                               = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0),
+	MX7ULP_PAD_PTA0__LPI2C0_SCL                                  = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x2, 0),
+	MX7ULP_PAD_PTA0__TPM0_CLKIN                                  = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x2, 0),
+	MX7ULP_PAD_PTA0__I2S0_RX_BCLK                                = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x2, 0),
+	MX7ULP_PAD_PTA0__LLWU0_P0                                    = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA1__CMP0_IN2_3V                                 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA1__PTA1                                        = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA1__LPSPI0_PCS2                                 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x1, 0),
+	MX7ULP_PAD_PTA1__LPUART0_RTS_b                               = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA1__LPI2C0_SDA                                  = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x1, 0),
+	MX7ULP_PAD_PTA1__TPM0_CH0                                    = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x1, 0),
+	MX7ULP_PAD_PTA1__I2S0_RX_FS                                  = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x1, 0),
+	MX7ULP_PAD_PTA2__CMP1_IN2_3V                                 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA2__PTA2                                        = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA2__LPSPI0_PCS3                                 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x1, 0),
+	MX7ULP_PAD_PTA2__LPUART0_TX                                  = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x1, 0),
+	MX7ULP_PAD_PTA2__LPI2C0_HREQ                                 = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x1, 0),
+	MX7ULP_PAD_PTA2__TPM0_CH1                                    = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x1, 0),
+	MX7ULP_PAD_PTA2__I2S0_RXD0                                   = IOMUX_PAD(0xD008, 0xD008, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x1, 0),
+	MX7ULP_PAD_PTA3__CMP1_IN4_3V                                 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA3__PTA3                                        = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA3__LPSPI0_PCS0                                 = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x1, 0),
+	MX7ULP_PAD_PTA3__LPUART0_RX                                  = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x1, 0),
+	MX7ULP_PAD_PTA3__TPM0_CH2                                    = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x1, 0),
+	MX7ULP_PAD_PTA3__I2S0_RXD1                                   = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x1, 0),
+	MX7ULP_PAD_PTA3__CMP0_OUT                                    = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA3__LLWU0_P1                                    = IOMUX_PAD(0xD00C, 0xD00C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA4__ADC1_CH3A                                   = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA4__PTA4                                        = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA4__LPSPI0_SIN                                  = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x1, 0),
+	MX7ULP_PAD_PTA4__LPUART1_CTS_b                               = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0),
+	MX7ULP_PAD_PTA4__LPI2C1_SCL                                  = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x1, 0),
+	MX7ULP_PAD_PTA4__TPM0_CH3                                    = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x1, 0),
+	MX7ULP_PAD_PTA4__I2S0_MCLK                                   = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x1, 0),
+	MX7ULP_PAD_PTA5__ADC1_CH3B                                   = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA5__PTA5                                        = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA5__LPSPI0_SOUT                                 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x1, 0),
+	MX7ULP_PAD_PTA5__LPUART1_RTS_b                               = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA5__LPI2C1_SDA                                  = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x1, 0),
+	MX7ULP_PAD_PTA5__TPM0_CH4                                    = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x1, 0),
+	MX7ULP_PAD_PTA5__I2S0_TX_BCLK                                = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x1, 0),
+	MX7ULP_PAD_PTA6__ADC1_CH4A_5A_6A_7A_8A                       = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA6__PTA6                                        = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA6__LPSPI0_SCK                                  = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x1, 0),
+	MX7ULP_PAD_PTA6__LPUART1_TX                                  = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x1, 0),
+	MX7ULP_PAD_PTA6__LPI2C1_HREQ                                 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x1, 0),
+	MX7ULP_PAD_PTA6__TPM0_CH5                                    = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x1, 0),
+	MX7ULP_PAD_PTA6__I2S0_TX_FS                                  = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x1, 0),
+	MX7ULP_PAD_PTA7__ADC1_CH4B_5B_6B_7B_8B                       = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA7__PTA7                                        = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA7__LPUART1_RX                                  = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x1, 0),
+	MX7ULP_PAD_PTA7__TPM1_CH1                                    = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x1, 0),
+	MX7ULP_PAD_PTA7__I2S0_TXD0                                   = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA8__ADC1_CH4A_5A_6A_7A_8A                       = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA8__PTA8                                        = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA8__LPSPI1_PCS1                                 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x1, 0),
+	MX7ULP_PAD_PTA8__LPUART2_CTS_b                               = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0),
+	MX7ULP_PAD_PTA8__LPI2C2_SCL                                  = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x1, 0),
+	MX7ULP_PAD_PTA8__TPM1_CLKIN                                  = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x1, 0),
+	MX7ULP_PAD_PTA8__I2S0_TXD1                                   = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA9__ADC1_CH4B_5B_6B_7B_8B                       = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA9__PTA9                                        = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA9__LPSPI1_PCS2                                 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x1, 0),
+	MX7ULP_PAD_PTA9__LPUART2_RTS_b                               = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA9__LPI2C2_SDA                                  = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x1, 0),
+	MX7ULP_PAD_PTA9__TPM1_CH0                                    = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x1, 0),
+	MX7ULP_PAD_PTA9__NMI0_b                                      = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA10__ADC1_CH4A_5A_6A_7A_8A                      = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA10__PTA10                                      = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA10__LPSPI1_PCS3                                = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x1, 0),
+	MX7ULP_PAD_PTA10__LPUART2_TX                                 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x1, 0),
+	MX7ULP_PAD_PTA10__LPI2C2_HREQ                                = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x1, 0),
+	MX7ULP_PAD_PTA10__TPM2_CLKIN                                 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x1, 0),
+	MX7ULP_PAD_PTA10__I2S0_RX_BCLK                               = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x1, 0),
+	MX7ULP_PAD_PTA11__ADC1_CH4B_5B_6B_7B_8B                      = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA11__PTA11                                      = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA11__LPUART2_RX                                 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x1, 0),
+	MX7ULP_PAD_PTA11__TPM2_CH0                                   = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x1, 0),
+	MX7ULP_PAD_PTA11__I2S0_RX_FS                                 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x2, 0),
+	MX7ULP_PAD_PTA12__ADC1_CH4A_5A_6A_7A_8A                      = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA12__PTA12                                      = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA12__LPSPI1_SIN                                 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x1, 0),
+	MX7ULP_PAD_PTA12__LPUART3_CTS_b                              = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0),
+	MX7ULP_PAD_PTA12__LPI2C3_SCL                                 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x1, 0),
+	MX7ULP_PAD_PTA12__TPM2_CH1                                   = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x1, 0),
+	MX7ULP_PAD_PTA12__I2S0_RXD0                                  = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x2, 0),
+	MX7ULP_PAD_PTA13__ADC1_CH4B_5B_6B_7B_8B                      = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA13__PTA13                                      = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA13__LPSPI1_SOUT                                = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x2, 0),
+	MX7ULP_PAD_PTA13__LPUART3_RTS_b                              = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA13__LPI2C3_SDA                                 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x2, 0),
+	MX7ULP_PAD_PTA13__TPM3_CLKIN                                 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x1, 0),
+	MX7ULP_PAD_PTA13__I2S0_RXD1                                  = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x2, 0),
+	MX7ULP_PAD_PTA13__CMP0_OUT                                   = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA13__LLWU0_P2                                   = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA14__ADC1_CH4A_5A_6A_7A_8A                      = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA14__PTA14                                      = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA14__LPSPI1_SCK                                 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x2, 0),
+	MX7ULP_PAD_PTA14__LPUART3_TX                                 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x2, 0),
+	MX7ULP_PAD_PTA14__LPI2C3_HREQ                                = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x2, 0),
+	MX7ULP_PAD_PTA14__TPM3_CH0                                   = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x1, 0),
+	MX7ULP_PAD_PTA14__I2S0_MCLK                                  = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x2, 0),
+	MX7ULP_PAD_PTA14__LLWU0_P3                                   = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA15__ADC1_CH4B_5B_6B_7B_8B                      = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA15__PTA15                                      = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA15__LPSPI1_PCS0                                = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x1, 0),
+	MX7ULP_PAD_PTA15__LPUART3_RX                                 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x1, 0),
+	MX7ULP_PAD_PTA15__TPM3_CH1                                   = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x1, 0),
+	MX7ULP_PAD_PTA15__I2S0_TX_BCLK                               = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x2, 0),
+	MX7ULP_PAD_PTA16__CMP1_IN5_3V                                = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA16__PTA16                                      = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA16__FXIO0_D0                                   = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA16__LPSPI0_SOUT                                = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x2, 0),
+	MX7ULP_PAD_PTA16__LPUART0_CTS_b                              = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0),
+	MX7ULP_PAD_PTA16__LPI2C0_SCL                                 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x1, 0),
+	MX7ULP_PAD_PTA16__TPM3_CH2                                   = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x1, 0),
+	MX7ULP_PAD_PTA16__I2S0_TX_FS                                 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x2, 0),
+	MX7ULP_PAD_PTA17__CMP1_IN6_3V                                = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA17__PTA17                                      = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA17__FXIO0_D1                                   = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA17__LPSPI0_SCK                                 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x2, 0),
+	MX7ULP_PAD_PTA17__LPUART0_RTS_b                              = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA17__LPI2C0_SDA                                 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x2, 0),
+	MX7ULP_PAD_PTA17__TPM3_CH3                                   = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x1, 0),
+	MX7ULP_PAD_PTA17__I2S0_TXD0                                  = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA18__CMP1_IN1_3V                                = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA18__PTA18                                      = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA18__FXIO0_D2                                   = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA18__LPSPI0_PCS0                                = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x2, 0),
+	MX7ULP_PAD_PTA18__LPUART0_TX                                 = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x2, 0),
+	MX7ULP_PAD_PTA18__LPI2C0_HREQ                                = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x2, 0),
+	MX7ULP_PAD_PTA18__TPM3_CH4                                   = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x1, 0),
+	MX7ULP_PAD_PTA18__I2S0_TXD1                                  = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA18__LLWU0_P4                                   = IOMUX_PAD(0xD048, 0xD048, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA19__CMP1_IN3_3V                                = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA19__PTA19                                      = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA19__FXIO0_D3                                   = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA19__LPUART0_RX                                 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x2, 0),
+	MX7ULP_PAD_PTA19__TPM3_CH5                                   = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x1, 0),
+	MX7ULP_PAD_PTA19__I2S1_RX_BCLK                               = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x1, 0),
+	MX7ULP_PAD_PTA19__LPTMR0_ALT3                                = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA19__LLWU0_P5                                   = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA20__ADC0_CH8A_9A_10A                           = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA20__PTA20                                      = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA20__FXIO0_D4                                   = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA20__LPSPI0_SIN                                 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x2, 0),
+	MX7ULP_PAD_PTA20__LPUART1_CTS_b                              = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0),
+	MX7ULP_PAD_PTA20__LPI2C1_SCL                                 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x2, 0),
+	MX7ULP_PAD_PTA20__TPM0_CLKIN                                 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x1, 0),
+	MX7ULP_PAD_PTA20__I2S1_RX_FS                                 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x1, 0),
+	MX7ULP_PAD_PTA21__ADC0_CH8B_9B_10B                           = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA21__PTA21                                      = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA21__FXIO0_D5                                   = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA21__LPSPI0_PCS1                                = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x1, 0),
+	MX7ULP_PAD_PTA21__LPUART1_RTS_b                              = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA21__LPI2C1_SDA                                 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x2, 0),
+	MX7ULP_PAD_PTA21__TPM0_CH0                                   = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x2, 0),
+	MX7ULP_PAD_PTA21__I2S1_RXD0                                  = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x1, 0),
+	MX7ULP_PAD_PTA22__ADC0_CH8A_9A_10A                           = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA22__PTA22                                      = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA22__FXIO0_D6                                   = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA22__LPSPI0_PCS2                                = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x2, 0),
+	MX7ULP_PAD_PTA22__LPUART1_TX                                 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x2, 0),
+	MX7ULP_PAD_PTA22__LPI2C1_HREQ                                = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x2, 0),
+	MX7ULP_PAD_PTA22__TPM0_CH1                                   = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x2, 0),
+	MX7ULP_PAD_PTA22__I2S1_RXD1                                  = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x1, 0),
+	MX7ULP_PAD_PTA22__LPTMR0_ALT2                                = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA22__EWM_OUT_b                                  = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA23__ADC0_CH8B_9B_10B                           = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA23__PTA23                                      = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA23__FXIO0_D7                                   = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA23__LPSPI0_PCS3                                = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x2, 0),
+	MX7ULP_PAD_PTA23__LPUART1_RX                                 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x2, 0),
+	MX7ULP_PAD_PTA23__TPM0_CH2                                   = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x2, 0),
+	MX7ULP_PAD_PTA23__I2S1_MCLK                                  = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x1, 0),
+	MX7ULP_PAD_PTA23__LLWU0_P6                                   = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA24__ADC0_CH8A_9A_10A                           = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA24__PTA24                                      = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA24__FXIO0_D8                                   = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA24__LPSPI1_PCS1                                = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x2, 0),
+	MX7ULP_PAD_PTA24__LPUART2_CTS_b                              = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0),
+	MX7ULP_PAD_PTA24__LPI2C2_SCL                                 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x2, 0),
+	MX7ULP_PAD_PTA24__TPM0_CH3                                   = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x2, 0),
+	MX7ULP_PAD_PTA24__I2S1_TX_BCLK                               = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x1, 0),
+	MX7ULP_PAD_PTA25__ADC0_CH8B_9B_10B                           = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA25__PTA25                                      = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA25__FXIO0_D9                                   = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA25__LPSPI1_PCS2                                = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x2, 0),
+	MX7ULP_PAD_PTA25__LPUART2_RTS_b                              = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA25__LPI2C2_SDA                                 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x2, 0),
+	MX7ULP_PAD_PTA25__TPM0_CH4                                   = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x2, 0),
+	MX7ULP_PAD_PTA25__I2S1_TX_FS                                 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x1, 0),
+	MX7ULP_PAD_PTA26__PTA26                                      = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO                           = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA26__FXIO0_D10                                  = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA26__LPSPI1_PCS3                                = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x2, 0),
+	MX7ULP_PAD_PTA26__LPUART2_TX                                 = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x2, 0),
+	MX7ULP_PAD_PTA26__LPI2C2_HREQ                                = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x2, 0),
+	MX7ULP_PAD_PTA26__TPM0_CH5                                   = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x2, 0),
+	MX7ULP_PAD_PTA26__I2S1_RXD2                                  = IOMUX_PAD(0xD068, 0xD068, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x1, 0),
+	MX7ULP_PAD_PTA27__PTA27                                      = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA27__JTAG_TDO                                   = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA27__FXIO0_D11                                  = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA27__LPUART2_RX                                 = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x2, 0),
+	MX7ULP_PAD_PTA27__TPM1_CH1                                   = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x2, 0),
+	MX7ULP_PAD_PTA27__I2S1_RXD3                                  = IOMUX_PAD(0xD06C, 0xD06C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x1, 0),
+	MX7ULP_PAD_PTA28__PTA28                                      = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA28__JTAG_TDI                                   = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA28__FXIO0_D12                                  = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA28__LPSPI1_SIN                                 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x2, 0),
+	MX7ULP_PAD_PTA28__LPUART3_CTS_b                              = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0),
+	MX7ULP_PAD_PTA28__LPI2C3_SCL                                 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x2, 0),
+	MX7ULP_PAD_PTA28__TPM1_CLKIN                                 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x2, 0),
+	MX7ULP_PAD_PTA28__I2S1_TXD2                                  = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA29__PTA29                                      = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK                          = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA29__FXIO0_D13                                  = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA29__LPSPI1_SOUT                                = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x1, 0),
+	MX7ULP_PAD_PTA29__LPUART3_RTS_b                              = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA29__LPI2C3_SDA                                 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x1, 0),
+	MX7ULP_PAD_PTA29__TPM1_CH0                                   = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x2, 0),
+	MX7ULP_PAD_PTA29__I2S1_TXD3                                  = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA30__ADC0_CH1A                                  = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA30__PTA30                                      = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA30__FXIO0_D14                                  = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA30__LPSPI1_SCK                                 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x1, 0),
+	MX7ULP_PAD_PTA30__LPUART3_TX                                 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x1, 0),
+	MX7ULP_PAD_PTA30__LPI2C3_HREQ                                = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x1, 0),
+	MX7ULP_PAD_PTA30__TPM2_CLKIN                                 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x2, 0),
+	MX7ULP_PAD_PTA30__I2S1_TXD0                                  = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA30__JTAG_TRST_b                                = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA31__ADC0_CH1B                                  = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA31__PTA31                                      = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA31__FXIO0_D15                                  = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA31__LPSPI1_PCS0                                = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x2, 0),
+	MX7ULP_PAD_PTA31__LPUART3_RX                                 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x2, 0),
+	MX7ULP_PAD_PTA31__TPM2_CH0                                   = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x2, 0),
+	MX7ULP_PAD_PTA31__I2S1_TXD1                                  = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA31__LPTMR0_ALT1                                = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA31__EWM_IN                                     = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x1, 0),
+	MX7ULP_PAD_PTA31__LLWU0_P7                                   = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB0__ADC0_CH0A                                   = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB0__PTB0                                        = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB0__FXIO0_D16                                   = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB0__LPSPI0_SIN                                  = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x3, 0),
+	MX7ULP_PAD_PTB0__LPUART0_TX                                  = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x4, 0xD200, 0x3, 0),
+	MX7ULP_PAD_PTB0__TPM2_CH1                                    = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x2, 0),
+	MX7ULP_PAD_PTB0__CLKOUT0                                     = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB0__CMP1_OUT                                    = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB0__EWM_OUT_b                                   = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB1__ADC0_CH0B                                   = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB1__PTB1                                        = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB1__FXIO0_D17                                   = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB1__LPSPI0_SOUT                                 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x3, 0),
+	MX7ULP_PAD_PTB1__LPUART0_RX                                  = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x4, 0xD1FC, 0x3, 0),
+	MX7ULP_PAD_PTB1__TPM3_CLKIN                                  = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x3, 0),
+	MX7ULP_PAD_PTB1__I2S1_TX_BCLK                                = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x2, 0),
+	MX7ULP_PAD_PTB1__RTC_CLKOUT                                  = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB1__EWM_IN                                      = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x2, 0),
+	MX7ULP_PAD_PTB1__LLWU0_P8                                    = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB2__ADC0_CH4A_5A_6A                             = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB2__PTB2                                        = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB2__FXIO0_D18                                   = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB2__LPSPI0_SCK                                  = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x3, 0),
+	MX7ULP_PAD_PTB2__LPUART1_TX                                  = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x3, 0),
+	MX7ULP_PAD_PTB2__TPM3_CH0                                    = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x2, 0),
+	MX7ULP_PAD_PTB2__I2S1_TX_FS                                  = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x2, 0),
+	MX7ULP_PAD_PTB2__TRACE_CLKOUT                                = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB3__ADC0_CH4B_5B_6B                             = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB3__PTB3                                        = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB3__FXIO0_D19                                   = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB3__LPSPI0_PCS0                                 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x3, 0),
+	MX7ULP_PAD_PTB3__LPUART1_RX                                  = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x3, 0),
+	MX7ULP_PAD_PTB3__TPM3_CH1                                    = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x2, 0),
+	MX7ULP_PAD_PTB3__I2S1_TXD0                                   = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB3__TRACE_D0                                    = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB3__LPTMR1_ALT2                                 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB3__LLWU0_P9                                    = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB4__PTB4                                        = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB4__FXIO0_D20                                   = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB4__LPSPI0_PCS1                                 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x3, 0),
+	MX7ULP_PAD_PTB4__LPUART2_TX                                  = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x3, 0),
+	MX7ULP_PAD_PTB4__LPI2C0_HREQ                                 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x5, 0xD178, 0x3, 0),
+	MX7ULP_PAD_PTB4__TPM3_CH2                                    = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x2, 0),
+	MX7ULP_PAD_PTB4__I2S1_TXD1                                   = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB4__QSPIA_DATA7                                 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB4__TRACE_D1                                    = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB5__PTB5                                        = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB5__FXIO0_D21                                   = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB5__LPSPI0_PCS2                                 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x3, 0),
+	MX7ULP_PAD_PTB5__LPUART2_RX                                  = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x3, 0),
+	MX7ULP_PAD_PTB5__LPI2C1_HREQ                                 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x3, 0),
+	MX7ULP_PAD_PTB5__TPM3_CH3                                    = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x2, 0),
+	MX7ULP_PAD_PTB5__I2S1_TXD2                                   = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB5__QSPIA_DATA6                                 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB5__TRACE_D2                                    = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB6__ADC1_CH1A                                   = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB6__PTB6                                        = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB6__FXIO0_D22                                   = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB6__LPSPI0_PCS3                                 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x3, 0),
+	MX7ULP_PAD_PTB6__LPUART3_TX                                  = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x3, 0),
+	MX7ULP_PAD_PTB6__LPI2C0_SCL                                  = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x3, 0),
+	MX7ULP_PAD_PTB6__TPM3_CH4                                    = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x6, 0xD170, 0x2, 0),
+	MX7ULP_PAD_PTB6__I2S1_TXD3                                   = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB6__QSPIA_DATA5                                 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB6__TRACE_D3                                    = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB6__LPTMR1_ALT3                                 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB6__LLWU0_P10                                   = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB7__ADC1_CH1B                                   = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB7__PTB7                                        = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB7__FXIO0_D23                                   = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB7__LPSPI1_SIN                                  = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x3, 0),
+	MX7ULP_PAD_PTB7__LPUART3_RX                                  = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x3, 0),
+	MX7ULP_PAD_PTB7__LPI2C0_SDA                                  = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x3, 0),
+	MX7ULP_PAD_PTB7__TPM3_CH5                                    = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x6, 0xD174, 0x2, 0),
+	MX7ULP_PAD_PTB7__I2S1_MCLK                                   = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x2, 0),
+	MX7ULP_PAD_PTB7__QSPIA_SS1_B                                 = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB7__CMP1_OUT                                    = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB7__LLWU0_P11                                   = IOMUX_PAD(0xD09C, 0xD09C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0                         = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB8__PTB8                                        = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB8__FXIO0_D24                                   = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB8__LPSPI1_SOUT                                 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x3, 0),
+	MX7ULP_PAD_PTB8__LPI2C1_SCL                                  = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x3, 0),
+	MX7ULP_PAD_PTB8__TPM0_CLKIN                                  = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x3, 0),
+	MX7ULP_PAD_PTB8__I2S1_RX_BCLK                                = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x2, 0),
+	MX7ULP_PAD_PTB8__QSPIA_SS0_B                                 = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB8__RTC_CLKOUT                                  = IOMUX_PAD(0xD0A0, 0xD0A0, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2                         = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB9__PTB9                                        = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB9__FXIO0_D25                                   = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB9__LPSPI1_SCK                                  = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x3, 0),
+	MX7ULP_PAD_PTB9__LPI2C1_SDA                                  = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x3, 0),
+	MX7ULP_PAD_PTB9__TPM0_CH0                                    = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x3, 0),
+	MX7ULP_PAD_PTB9__I2S1_RX_FS                                  = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x2, 0),
+	MX7ULP_PAD_PTB9__QSPIA_DQS                                   = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB9__LLWU0_P12                                   = IOMUX_PAD(0xD0A4, 0xD0A4, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB10__CMP0_IN1                                   = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB10__PTB10                                      = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB10__FXIO0_D26                                  = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB10__LPSPI1_PCS0                                = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x3, 0),
+	MX7ULP_PAD_PTB10__LPI2C2_SCL                                 = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x3, 0),
+	MX7ULP_PAD_PTB10__TPM0_CH1                                   = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x3, 0),
+	MX7ULP_PAD_PTB10__I2S1_RXD0                                  = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x2, 0),
+	MX7ULP_PAD_PTB10__TRACE_D4                                   = IOMUX_PAD(0xD0A8, 0xD0A8, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB11__CMP0_IN3                                   = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB11__PTB11                                      = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB11__FXIO0_D27                                  = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB11__LPSPI1_PCS1                                = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x3, 0),
+	MX7ULP_PAD_PTB11__LPI2C2_SDA                                 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x3, 0),
+	MX7ULP_PAD_PTB11__TPM1_CLKIN                                 = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x3, 0),
+	MX7ULP_PAD_PTB11__I2S1_RXD1                                  = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x2, 0),
+	MX7ULP_PAD_PTB11__TRACE_D5                                   = IOMUX_PAD(0xD0AC, 0xD0AC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0                        = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB12__PTB12                                      = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB12__FXIO0_D28                                  = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB12__LPSPI1_PCS2                                = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x3, 0),
+	MX7ULP_PAD_PTB12__LPI2C3_SCL                                 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x3, 0),
+	MX7ULP_PAD_PTB12__TPM1_CH0                                   = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x3, 0),
+	MX7ULP_PAD_PTB12__I2S1_RXD2                                  = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x2, 0),
+	MX7ULP_PAD_PTB12__TRACE_D6                                   = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1                        = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB13__PTB13                                      = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB13__FXIO0_D29                                  = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB13__LPSPI1_PCS3                                = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x3, 0),
+	MX7ULP_PAD_PTB13__LPI2C3_SDA                                 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x3, 0),
+	MX7ULP_PAD_PTB13__TPM1_CH1                                   = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x3, 0),
+	MX7ULP_PAD_PTB13__I2S1_RXD3                                  = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x2, 0),
+	MX7ULP_PAD_PTB13__QSPIA_DATA4                                = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB13__TRACE_D7                                   = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB14__ADC1_CH2A                                  = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB14__PTB14                                      = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB14__FXIO0_D30                                  = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB14__LPI2C2_HREQ                                = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x3, 0),
+	MX7ULP_PAD_PTB14__TPM2_CLKIN                                 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x3, 0),
+	MX7ULP_PAD_PTB14__QSPIA_SS1_B                                = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB14__QSPIA_SCLK_b                               = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB14__LLWU0_P13                                  = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB15__ADC1_CH2B                                  = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB15__PTB15                                      = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB15__FXIO0_D31                                  = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB15__LPI2C3_HREQ                                = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x3, 0),
+	MX7ULP_PAD_PTB15__TPM2_CH0                                   = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x3, 0),
+	MX7ULP_PAD_PTB15__QSPIA_SCLK                                 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB16__ADC0_CH4A_5A_6A                            = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB16__PTB16                                      = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB16__TPM2_CH1                                   = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x3, 0),
+	MX7ULP_PAD_PTB16__QSPIA_DATA3                                = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB16__LLWU0_P14                                  = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB17__ADC0_CH4B_5B_6B                            = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB17__PTB17                                      = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB17__TPM3_CLKIN                                 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x2, 0),
+	MX7ULP_PAD_PTB17__QSPIA_DATA2                                = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB18__ADC0_CH4A_5A_6A                            = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB18__PTB18                                      = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB18__TPM3_CH0                                   = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x3, 0),
+	MX7ULP_PAD_PTB18__QSPIA_DATA1                                = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB19__ADC0_CH4B_5B_6B                            = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB19__PTB19                                      = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB19__TPM3_CH1                                   = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x3, 0),
+	MX7ULP_PAD_PTB19__QSPIA_DATA0                                = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB19__USB0_ID                                    = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB19__LLWU0_P15                                  = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC0__PTC0                                        = IOMUX_PAD(0x0000, 0x0000, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC0__LPUART4_CTS_b                               = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0),
+	MX7ULP_PAD_PTC0__LPI2C4_SCL                                  = IOMUX_PAD(0x0000, 0x0000, 0x5, 0x0278, 0x1, 0),
+	MX7ULP_PAD_PTC0__TPM4_CLKIN                                  = IOMUX_PAD(0x0000, 0x0000, 0x6, 0x0298, 0x1, 0),
+	MX7ULP_PAD_PTC0__FB_AD0                                      = IOMUX_PAD(0x0000, 0x0000, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC0__TRACE_D15                                   = IOMUX_PAD(0x0000, 0x0000, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC0__DEBUG_MUX0                                  = IOMUX_PAD(0x0000, 0x0000, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC1__PTC1                                        = IOMUX_PAD(0x0004, 0x0004, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC1__LPUART4_RTS_b                               = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC1__LPI2C4_SDA                                  = IOMUX_PAD(0x0004, 0x0004, 0x5, 0x027C, 0x1, 0),
+	MX7ULP_PAD_PTC1__TPM4_CH0                                    = IOMUX_PAD(0x0004, 0x0004, 0x6, 0x0280, 0x1, 0),
+	MX7ULP_PAD_PTC1__FB_AD1                                      = IOMUX_PAD(0x0004, 0x0004, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC1__TRACE_D14                                   = IOMUX_PAD(0x0004, 0x0004, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC1__DEBUG_MUX1                                  = IOMUX_PAD(0x0004, 0x0004, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC2__PTC2                                        = IOMUX_PAD(0x0008, 0x0008, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC2__LPUART4_TX                                  = IOMUX_PAD(0x0008, 0x0008, 0x4, 0x024C, 0x1, 0),
+	MX7ULP_PAD_PTC2__LPI2C4_HREQ                                 = IOMUX_PAD(0x0008, 0x0008, 0x5, 0x0274, 0x1, 0),
+	MX7ULP_PAD_PTC2__TPM4_CH1                                    = IOMUX_PAD(0x0008, 0x0008, 0x6, 0x0284, 0x1, 0),
+	MX7ULP_PAD_PTC2__FB_AD2                                      = IOMUX_PAD(0x0008, 0x0008, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC2__TRACE_D13                                   = IOMUX_PAD(0x0008, 0x0008, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC2__DEBUG_MUX2                                  = IOMUX_PAD(0x0008, 0x0008, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC3__PTC3                                        = IOMUX_PAD(0x000C, 0x000C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC3__LPUART4_RX                                  = IOMUX_PAD(0x000C, 0x000C, 0x4, 0x0248, 0x1, 0),
+	MX7ULP_PAD_PTC3__TPM4_CH2                                    = IOMUX_PAD(0x000C, 0x000C, 0x6, 0x0288, 0x1, 0),
+	MX7ULP_PAD_PTC3__FB_AD3                                      = IOMUX_PAD(0x000C, 0x000C, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC3__TRACE_D12                                   = IOMUX_PAD(0x000C, 0x000C, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC3__DEBUG_MUX3                                  = IOMUX_PAD(0x000C, 0x000C, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC4__PTC4                                        = IOMUX_PAD(0x0010, 0x0010, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC4__FXIO1_D0                                    = IOMUX_PAD(0x0010, 0x0010, 0x2, 0x0204, 0x1, 0),
+	MX7ULP_PAD_PTC4__LPSPI2_PCS1                                 = IOMUX_PAD(0x0010, 0x0010, 0x3, 0x02A0, 0x1, 0),
+	MX7ULP_PAD_PTC4__LPUART5_CTS_b                               = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0),
+	MX7ULP_PAD_PTC4__LPI2C5_SCL                                  = IOMUX_PAD(0x0010, 0x0010, 0x5, 0x02BC, 0x1, 0),
+	MX7ULP_PAD_PTC4__TPM4_CH3                                    = IOMUX_PAD(0x0010, 0x0010, 0x6, 0x028C, 0x1, 0),
+	MX7ULP_PAD_PTC4__FB_AD4                                      = IOMUX_PAD(0x0010, 0x0010, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC4__TRACE_D11                                   = IOMUX_PAD(0x0010, 0x0010, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC4__DEBUG_MUX4                                  = IOMUX_PAD(0x0010, 0x0010, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC5__PTC5                                        = IOMUX_PAD(0x0014, 0x0014, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC5__FXIO1_D1                                    = IOMUX_PAD(0x0014, 0x0014, 0x2, 0x0208, 0x1, 0),
+	MX7ULP_PAD_PTC5__LPSPI2_PCS2                                 = IOMUX_PAD(0x0014, 0x0014, 0x3, 0x02A4, 0x1, 0),
+	MX7ULP_PAD_PTC5__LPUART5_RTS_b                               = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC5__LPI2C5_SDA                                  = IOMUX_PAD(0x0014, 0x0014, 0x5, 0x02C0, 0x1, 0),
+	MX7ULP_PAD_PTC5__TPM4_CH4                                    = IOMUX_PAD(0x0014, 0x0014, 0x6, 0x0290, 0x1, 0),
+	MX7ULP_PAD_PTC5__FB_AD5                                      = IOMUX_PAD(0x0014, 0x0014, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC5__TRACE_D10                                   = IOMUX_PAD(0x0014, 0x0014, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC5__DEBUG_MUX5                                  = IOMUX_PAD(0x0014, 0x0014, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC6__PTC6                                        = IOMUX_PAD(0x0018, 0x0018, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC6__FXIO1_D2                                    = IOMUX_PAD(0x0018, 0x0018, 0x2, 0x020C, 0x1, 0),
+	MX7ULP_PAD_PTC6__LPSPI2_PCS3                                 = IOMUX_PAD(0x0018, 0x0018, 0x3, 0x02A8, 0x1, 0),
+	MX7ULP_PAD_PTC6__LPUART5_TX                                  = IOMUX_PAD(0x0018, 0x0018, 0x4, 0x0258, 0x1, 0),
+	MX7ULP_PAD_PTC6__LPI2C5_HREQ                                 = IOMUX_PAD(0x0018, 0x0018, 0x5, 0x02B8, 0x1, 0),
+	MX7ULP_PAD_PTC6__TPM4_CH5                                    = IOMUX_PAD(0x0018, 0x0018, 0x6, 0x0294, 0x1, 0),
+	MX7ULP_PAD_PTC6__FB_AD6                                      = IOMUX_PAD(0x0018, 0x0018, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC6__TRACE_D9                                    = IOMUX_PAD(0x0018, 0x0018, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC6__DEBUG_MUX6                                  = IOMUX_PAD(0x0018, 0x0018, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC7__PTC7                                        = IOMUX_PAD(0x001C, 0x001C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC7__FXIO1_D3                                    = IOMUX_PAD(0x001C, 0x001C, 0x2, 0x0210, 0x1, 0),
+	MX7ULP_PAD_PTC7__LPUART5_RX                                  = IOMUX_PAD(0x001C, 0x001C, 0x4, 0x0254, 0x1, 0),
+	MX7ULP_PAD_PTC7__TPM5_CH1                                    = IOMUX_PAD(0x001C, 0x001C, 0x6, 0x02C8, 0x1, 0),
+	MX7ULP_PAD_PTC7__FB_AD7                                      = IOMUX_PAD(0x001C, 0x001C, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC7__TRACE_D8                                    = IOMUX_PAD(0x001C, 0x001C, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC7__DEBUG_MUX7                                  = IOMUX_PAD(0x001C, 0x001C, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC8__PTC8                                        = IOMUX_PAD(0x0020, 0x0020, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC8__FXIO1_D4                                    = IOMUX_PAD(0x0020, 0x0020, 0x2, 0x0214, 0x1, 0),
+	MX7ULP_PAD_PTC8__LPSPI2_SIN                                  = IOMUX_PAD(0x0020, 0x0020, 0x3, 0x02B0, 0x1, 0),
+	MX7ULP_PAD_PTC8__LPUART6_CTS_b                               = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0),
+	MX7ULP_PAD_PTC8__LPI2C6_SCL                                  = IOMUX_PAD(0x0020, 0x0020, 0x5, 0x02FC, 0x1, 0),
+	MX7ULP_PAD_PTC8__TPM5_CLKIN                                  = IOMUX_PAD(0x0020, 0x0020, 0x6, 0x02CC, 0x1, 0),
+	MX7ULP_PAD_PTC8__FB_AD8                                      = IOMUX_PAD(0x0020, 0x0020, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC8__TRACE_D7                                    = IOMUX_PAD(0x0020, 0x0020, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC8__DEBUG_MUX8                                  = IOMUX_PAD(0x0020, 0x0020, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC9__PTC9                                        = IOMUX_PAD(0x0024, 0x0024, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC9__FXIO1_D5                                    = IOMUX_PAD(0x0024, 0x0024, 0x2, 0x0218, 0x1, 0),
+	MX7ULP_PAD_PTC9__LPSPI2_SOUT                                 = IOMUX_PAD(0x0024, 0x0024, 0x3, 0x02B4, 0x1, 0),
+	MX7ULP_PAD_PTC9__LPUART6_RTS_b                               = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC9__LPI2C6_SDA                                  = IOMUX_PAD(0x0024, 0x0024, 0x5, 0x0300, 0x1, 0),
+	MX7ULP_PAD_PTC9__TPM5_CH0                                    = IOMUX_PAD(0x0024, 0x0024, 0x6, 0x02C4, 0x1, 0),
+	MX7ULP_PAD_PTC9__FB_AD9                                      = IOMUX_PAD(0x0024, 0x0024, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC9__TRACE_D6                                    = IOMUX_PAD(0x0024, 0x0024, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC9__DEBUG_MUX9                                  = IOMUX_PAD(0x0024, 0x0024, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC10__PTC10                                      = IOMUX_PAD(0x0028, 0x0028, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC10__FXIO1_D6                                   = IOMUX_PAD(0x0028, 0x0028, 0x2, 0x021C, 0x1, 0),
+	MX7ULP_PAD_PTC10__LPSPI2_SCK                                 = IOMUX_PAD(0x0028, 0x0028, 0x3, 0x02AC, 0x1, 0),
+	MX7ULP_PAD_PTC10__LPUART6_TX                                 = IOMUX_PAD(0x0028, 0x0028, 0x4, 0x0264, 0x1, 0),
+	MX7ULP_PAD_PTC10__LPI2C6_HREQ                                = IOMUX_PAD(0x0028, 0x0028, 0x5, 0x02F8, 0x1, 0),
+	MX7ULP_PAD_PTC10__TPM7_CH3                                   = IOMUX_PAD(0x0028, 0x0028, 0x6, 0x02E8, 0x1, 0),
+	MX7ULP_PAD_PTC10__FB_AD10                                    = IOMUX_PAD(0x0028, 0x0028, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC10__TRACE_D5                                   = IOMUX_PAD(0x0028, 0x0028, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC10__DEBUG_MUX10                                = IOMUX_PAD(0x0028, 0x0028, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC11__PTC11                                      = IOMUX_PAD(0x002C, 0x002C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC11__FXIO1_D7                                   = IOMUX_PAD(0x002C, 0x002C, 0x2, 0x0220, 0x1, 0),
+	MX7ULP_PAD_PTC11__LPSPI2_PCS0                                = IOMUX_PAD(0x002C, 0x002C, 0x3, 0x029C, 0x1, 0),
+	MX7ULP_PAD_PTC11__LPUART6_RX                                 = IOMUX_PAD(0x002C, 0x002C, 0x4, 0x0260, 0x1, 0),
+	MX7ULP_PAD_PTC11__TPM7_CH4                                   = IOMUX_PAD(0x002C, 0x002C, 0x6, 0x02EC, 0x1, 0),
+	MX7ULP_PAD_PTC11__FB_AD11                                    = IOMUX_PAD(0x002C, 0x002C, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC11__TRACE_D4                                   = IOMUX_PAD(0x002C, 0x002C, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC11__DEBUG_MUX11                                = IOMUX_PAD(0x002C, 0x002C, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC12__PTC12                                      = IOMUX_PAD(0x0030, 0x0030, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC12__FXIO1_D8                                   = IOMUX_PAD(0x0030, 0x0030, 0x2, 0x0224, 0x1, 0),
+	MX7ULP_PAD_PTC12__LPSPI3_PCS1                                = IOMUX_PAD(0x0030, 0x0030, 0x3, 0x0314, 0x1, 0),
+	MX7ULP_PAD_PTC12__LPUART7_CTS_b                              = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0),
+	MX7ULP_PAD_PTC12__LPI2C7_SCL                                 = IOMUX_PAD(0x0030, 0x0030, 0x5, 0x0308, 0x1, 0),
+	MX7ULP_PAD_PTC12__TPM7_CH5                                   = IOMUX_PAD(0x0030, 0x0030, 0x6, 0x02F0, 0x1, 0),
+	MX7ULP_PAD_PTC12__FB_AD12                                    = IOMUX_PAD(0x0030, 0x0030, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC12__TRACE_D3                                   = IOMUX_PAD(0x0030, 0x0030, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC12__DEBUG_MUX12                                = IOMUX_PAD(0x0030, 0x0030, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC13__PTC13                                      = IOMUX_PAD(0x0034, 0x0034, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC13__FXIO1_D9                                   = IOMUX_PAD(0x0034, 0x0034, 0x2, 0x0228, 0x1, 0),
+	MX7ULP_PAD_PTC13__LPSPI3_PCS2                                = IOMUX_PAD(0x0034, 0x0034, 0x3, 0x0318, 0x1, 0),
+	MX7ULP_PAD_PTC13__LPUART7_RTS_b                              = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC13__LPI2C7_SDA                                 = IOMUX_PAD(0x0034, 0x0034, 0x5, 0x030C, 0x1, 0),
+	MX7ULP_PAD_PTC13__TPM7_CLKIN                                 = IOMUX_PAD(0x0034, 0x0034, 0x6, 0x02F4, 0x1, 0),
+	MX7ULP_PAD_PTC13__FB_AD13                                    = IOMUX_PAD(0x0034, 0x0034, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC13__TRACE_D2                                   = IOMUX_PAD(0x0034, 0x0034, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC13__DEBUG_MUX13                                = IOMUX_PAD(0x0034, 0x0034, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC14__PTC14                                      = IOMUX_PAD(0x0038, 0x0038, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC14__FXIO1_D10                                  = IOMUX_PAD(0x0038, 0x0038, 0x2, 0x022C, 0x1, 0),
+	MX7ULP_PAD_PTC14__LPSPI3_PCS3                                = IOMUX_PAD(0x0038, 0x0038, 0x3, 0x031C, 0x1, 0),
+	MX7ULP_PAD_PTC14__LPUART7_TX                                 = IOMUX_PAD(0x0038, 0x0038, 0x4, 0x0270, 0x1, 0),
+	MX7ULP_PAD_PTC14__LPI2C7_HREQ                                = IOMUX_PAD(0x0038, 0x0038, 0x5, 0x0304, 0x1, 0),
+	MX7ULP_PAD_PTC14__TPM7_CH0                                   = IOMUX_PAD(0x0038, 0x0038, 0x6, 0x02DC, 0x1, 0),
+	MX7ULP_PAD_PTC14__FB_AD14                                    = IOMUX_PAD(0x0038, 0x0038, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC14__TRACE_D1                                   = IOMUX_PAD(0x0038, 0x0038, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC14__DEBUG_MUX14                                = IOMUX_PAD(0x0038, 0x0038, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC15__PTC15                                      = IOMUX_PAD(0x003C, 0x003C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC15__FXIO1_D11                                  = IOMUX_PAD(0x003C, 0x003C, 0x2, 0x0230, 0x1, 0),
+	MX7ULP_PAD_PTC15__LPUART7_RX                                 = IOMUX_PAD(0x003C, 0x003C, 0x4, 0x026C, 0x1, 0),
+	MX7ULP_PAD_PTC15__TPM7_CH1                                   = IOMUX_PAD(0x003C, 0x003C, 0x6, 0x02E0, 0x1, 0),
+	MX7ULP_PAD_PTC15__FB_AD15                                    = IOMUX_PAD(0x003C, 0x003C, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC15__TRACE_D0                                   = IOMUX_PAD(0x003C, 0x003C, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC15__DEBUG_MUX15                                = IOMUX_PAD(0x003C, 0x003C, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC16__PTC16                                      = IOMUX_PAD(0x0040, 0x0040, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC16__FXIO1_D12                                  = IOMUX_PAD(0x0040, 0x0040, 0x2, 0x0234, 0x1, 0),
+	MX7ULP_PAD_PTC16__LPSPI3_SIN                                 = IOMUX_PAD(0x0040, 0x0040, 0x3, 0x0324, 0x1, 0),
+	MX7ULP_PAD_PTC16__TPM7_CH2                                   = IOMUX_PAD(0x0040, 0x0040, 0x6, 0x02E4, 0x1, 0),
+	MX7ULP_PAD_PTC16__FB_ALE_FB_CS1_b_FB_TS_b                    = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC16__TRACE_CLKOUT                               = IOMUX_PAD(0x0040, 0x0040, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC16__USB1_ULPI_OC2                              = IOMUX_PAD(0x0040, 0x0040, 0xb, 0x0334, 0x1, 0),
+	MX7ULP_PAD_PTC17__PTC17                                      = IOMUX_PAD(0x0044, 0x0044, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC17__FXIO1_D13                                  = IOMUX_PAD(0x0044, 0x0044, 0x2, 0x0238, 0x1, 0),
+	MX7ULP_PAD_PTC17__LPSPI3_SOUT                                = IOMUX_PAD(0x0044, 0x0044, 0x3, 0x0328, 0x1, 0),
+	MX7ULP_PAD_PTC17__TPM6_CLKIN                                 = IOMUX_PAD(0x0044, 0x0044, 0x6, 0x02D8, 0x1, 0),
+	MX7ULP_PAD_PTC17__FB_CS0_b                                   = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC17__DEBUG_MUX16                                = IOMUX_PAD(0x0044, 0x0044, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC18__PTC18                                      = IOMUX_PAD(0x0048, 0x0048, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC18__FXIO1_D14                                  = IOMUX_PAD(0x0048, 0x0048, 0x2, 0x023C, 0x1, 0),
+	MX7ULP_PAD_PTC18__LPSPI3_SCK                                 = IOMUX_PAD(0x0048, 0x0048, 0x3, 0x0320, 0x1, 0),
+	MX7ULP_PAD_PTC18__TPM6_CH0                                   = IOMUX_PAD(0x0048, 0x0048, 0x6, 0x02D0, 0x1, 0),
+	MX7ULP_PAD_PTC18__FB_OE_b                                    = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC18__DEBUG_MUX17                                = IOMUX_PAD(0x0048, 0x0048, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC19__PTC19                                      = IOMUX_PAD(0x004C, 0x004C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC19__FXIO1_D15                                  = IOMUX_PAD(0x004C, 0x004C, 0x2, 0x0240, 0x1, 0),
+	MX7ULP_PAD_PTC19__LPSPI3_PCS0                                = IOMUX_PAD(0x004C, 0x004C, 0x3, 0x0310, 0x1, 0),
+	MX7ULP_PAD_PTC19__TPM6_CH1                                   = IOMUX_PAD(0x004C, 0x004C, 0x6, 0x02D4, 0x1, 0),
+	MX7ULP_PAD_PTC19__FB_A16                                     = IOMUX_PAD(0x004C, 0x004C, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC19__USB1_ULPI_PWR2                             = IOMUX_PAD(0x004C, 0x004C, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD0__PTD0                                        = IOMUX_PAD(0x0080, 0x0080, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD0__SDHC0_RESET_b                               = IOMUX_PAD(0x0080, 0x0080, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD0__DEBUG_MUX18                                 = IOMUX_PAD(0x0080, 0x0080, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD1__PTD1                                        = IOMUX_PAD(0x0084, 0x0084, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD1__SDHC0_CMD                                   = IOMUX_PAD(0x0084, 0x0084, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD1__DEBUG_MUX19                                 = IOMUX_PAD(0x0084, 0x0084, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD2__PTD2                                        = IOMUX_PAD(0x0088, 0x0088, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD2__SDHC0_CLK                                   = IOMUX_PAD(0x0088, 0x0088, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD2__DEBUG_MUX20                                 = IOMUX_PAD(0x0088, 0x0088, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD3__PTD3                                        = IOMUX_PAD(0x008C, 0x008C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD3__SDHC0_D7                                    = IOMUX_PAD(0x008C, 0x008C, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD3__DEBUG_MUX21                                 = IOMUX_PAD(0x008C, 0x008C, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD4__PTD4                                        = IOMUX_PAD(0x0090, 0x0090, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD4__SDHC0_D6                                    = IOMUX_PAD(0x0090, 0x0090, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD4__DEBUG_MUX22                                 = IOMUX_PAD(0x0090, 0x0090, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD5__PTD5                                        = IOMUX_PAD(0x0094, 0x0094, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD5__SDHC0_D5                                    = IOMUX_PAD(0x0094, 0x0094, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD5__DEBUG_MUX23                                 = IOMUX_PAD(0x0094, 0x0094, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD6__PTD6                                        = IOMUX_PAD(0x0098, 0x0098, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD6__SDHC0_D4                                    = IOMUX_PAD(0x0098, 0x0098, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD6__DEBUG_MUX24                                 = IOMUX_PAD(0x0098, 0x0098, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD7__PTD7                                        = IOMUX_PAD(0x009C, 0x009C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD7__SDHC0_D3                                    = IOMUX_PAD(0x009C, 0x009C, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD7__DEBUG_MUX25                                 = IOMUX_PAD(0x009C, 0x009C, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD8__PTD8                                        = IOMUX_PAD(0x00A0, 0x00A0, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD8__TPM4_CLKIN                                  = IOMUX_PAD(0x00A0, 0x00A0, 0x6, 0x0298, 0x2, 0),
+	MX7ULP_PAD_PTD8__SDHC0_D2                                    = IOMUX_PAD(0x00A0, 0x00A0, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD8__DEBUG_MUX26                                 = IOMUX_PAD(0x00A0, 0x00A0, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD9__PTD9                                        = IOMUX_PAD(0x00A4, 0x00A4, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD9__TPM4_CH0                                    = IOMUX_PAD(0x00A4, 0x00A4, 0x6, 0x0280, 0x2, 0),
+	MX7ULP_PAD_PTD9__SDHC0_D1                                    = IOMUX_PAD(0x00A4, 0x00A4, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD9__DEBUG_MUX27                                 = IOMUX_PAD(0x00A4, 0x00A4, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD10__PTD10                                      = IOMUX_PAD(0x00A8, 0x00A8, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD10__TPM4_CH1                                   = IOMUX_PAD(0x00A8, 0x00A8, 0x6, 0x0284, 0x2, 0),
+	MX7ULP_PAD_PTD10__SDHC0_D0                                   = IOMUX_PAD(0x00A8, 0x00A8, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD10__DEBUG_MUX28                                = IOMUX_PAD(0x00A8, 0x00A8, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD11__PTD11                                      = IOMUX_PAD(0x00AC, 0x00AC, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD11__TPM4_CH2                                   = IOMUX_PAD(0x00AC, 0x00AC, 0x6, 0x0288, 0x2, 0),
+	MX7ULP_PAD_PTD11__SDHC0_DQS                                  = IOMUX_PAD(0x00AC, 0x00AC, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD11__DEBUG_MUX29                                = IOMUX_PAD(0x00AC, 0x00AC, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE0__PTE0                                        = IOMUX_PAD(0x0100, 0x0100, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE0__FXIO1_D31                                   = IOMUX_PAD(0x0100, 0x0100, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE0__LPSPI2_PCS1                                 = IOMUX_PAD(0x0100, 0x0100, 0x3, 0x02A0, 0x2, 0),
+	MX7ULP_PAD_PTE0__LPUART4_CTS_b                               = IOMUX_PAD(0x0100, 0x0100, 0x4, 0x0244, 0x2, 0),
+	MX7ULP_PAD_PTE0__LPI2C4_SCL                                  = IOMUX_PAD(0x0100, 0x0100, 0x5, 0x0278, 0x2, 0),
+	MX7ULP_PAD_PTE0__SDHC1_D1                                    = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE0__FB_A25                                      = IOMUX_PAD(0x0100, 0x0100, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE0__DEBUG_MUX30                                 = IOMUX_PAD(0x0100, 0x0100, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE1__PTE1                                        = IOMUX_PAD(0x0104, 0x0104, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE1__FXIO1_D30                                   = IOMUX_PAD(0x0104, 0x0104, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE1__LPSPI2_PCS2                                 = IOMUX_PAD(0x0104, 0x0104, 0x3, 0x02A4, 0x2, 0),
+	MX7ULP_PAD_PTE1__LPUART4_RTS_b                               = IOMUX_PAD(0x0104, 0x0104, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE1__LPI2C4_SDA                                  = IOMUX_PAD(0x0104, 0x0104, 0x5, 0x027C, 0x2, 0),
+	MX7ULP_PAD_PTE1__SDHC1_D0                                    = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE1__FB_A26                                      = IOMUX_PAD(0x0104, 0x0104, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE1__DEBUG_MUX31                                 = IOMUX_PAD(0x0104, 0x0104, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE2__PTE2                                        = IOMUX_PAD(0x0108, 0x0108, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE2__FXIO1_D29                                   = IOMUX_PAD(0x0108, 0x0108, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE2__LPSPI2_PCS3                                 = IOMUX_PAD(0x0108, 0x0108, 0x3, 0x02A8, 0x2, 0),
+	MX7ULP_PAD_PTE2__LPUART4_TX                                  = IOMUX_PAD(0x0108, 0x0108, 0x4, 0x024C, 0x2, 0),
+	MX7ULP_PAD_PTE2__LPI2C4_HREQ                                 = IOMUX_PAD(0x0108, 0x0108, 0x5, 0x0274, 0x2, 0),
+	MX7ULP_PAD_PTE2__SDHC1_CLK                                   = IOMUX_PAD(0x0108, 0x0108, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE2__DEBUG_MUX32                                 = IOMUX_PAD(0x0108, 0x0108, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE3__PTE3                                        = IOMUX_PAD(0x010C, 0x010C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE3__FXIO1_D28                                   = IOMUX_PAD(0x010C, 0x010C, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE3__LPUART4_RX                                  = IOMUX_PAD(0x010C, 0x010C, 0x4, 0x0248, 0x2, 0),
+	MX7ULP_PAD_PTE3__TPM5_CH1                                    = IOMUX_PAD(0x010C, 0x010C, 0x6, 0x02C8, 0x2, 0),
+	MX7ULP_PAD_PTE3__SDHC1_CMD                                   = IOMUX_PAD(0x010C, 0x010C, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE3__DEBUG_MUX33                                 = IOMUX_PAD(0x010C, 0x010C, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE4__PTE4                                        = IOMUX_PAD(0x0110, 0x0110, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE4__FXIO1_D27                                   = IOMUX_PAD(0x0110, 0x0110, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE4__LPSPI2_SIN                                  = IOMUX_PAD(0x0110, 0x0110, 0x3, 0x02B0, 0x2, 0),
+	MX7ULP_PAD_PTE4__LPUART5_CTS_b                               = IOMUX_PAD(0x0110, 0x0110, 0x4, 0x0250, 0x2, 0),
+	MX7ULP_PAD_PTE4__LPI2C5_SCL                                  = IOMUX_PAD(0x0110, 0x0110, 0x5, 0x02BC, 0x2, 0),
+	MX7ULP_PAD_PTE4__TPM5_CLKIN                                  = IOMUX_PAD(0x0110, 0x0110, 0x6, 0x02CC, 0x2, 0),
+	MX7ULP_PAD_PTE4__SDHC1_D3                                    = IOMUX_PAD(0x0110, 0x0110, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE5__PTE5                                        = IOMUX_PAD(0x0114, 0x0114, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE5__FXIO1_D26                                   = IOMUX_PAD(0x0114, 0x0114, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE5__LPSPI2_SOUT                                 = IOMUX_PAD(0x0114, 0x0114, 0x3, 0x02B4, 0x2, 0),
+	MX7ULP_PAD_PTE5__LPUART5_RTS_b                               = IOMUX_PAD(0x0114, 0x0114, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE5__LPI2C5_SDA                                  = IOMUX_PAD(0x0114, 0x0114, 0x5, 0x02C0, 0x2, 0),
+	MX7ULP_PAD_PTE5__TPM5_CH0                                    = IOMUX_PAD(0x0114, 0x0114, 0x6, 0x02C4, 0x2, 0),
+	MX7ULP_PAD_PTE5__SDHC1_D2                                    = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE6__PTE6                                        = IOMUX_PAD(0x0118, 0x0118, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE6__FXIO1_D25                                   = IOMUX_PAD(0x0118, 0x0118, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE6__LPSPI2_SCK                                  = IOMUX_PAD(0x0118, 0x0118, 0x3, 0x02AC, 0x2, 0),
+	MX7ULP_PAD_PTE6__LPUART5_TX                                  = IOMUX_PAD(0x0118, 0x0118, 0x4, 0x0258, 0x2, 0),
+	MX7ULP_PAD_PTE6__LPI2C5_HREQ                                 = IOMUX_PAD(0x0118, 0x0118, 0x5, 0x02B8, 0x2, 0),
+	MX7ULP_PAD_PTE6__TPM7_CH3                                    = IOMUX_PAD(0x0118, 0x0118, 0x6, 0x02E8, 0x2, 0),
+	MX7ULP_PAD_PTE6__SDHC1_D4                                    = IOMUX_PAD(0x0118, 0x0118, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE6__FB_A17                                      = IOMUX_PAD(0x0118, 0x0118, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE6__USB0_OC                                     = IOMUX_PAD(0x0118, 0x0118, 0xb, 0x0330, 0x1, 0),
+	MX7ULP_PAD_PTE7__PTE7                                        = IOMUX_PAD(0x011C, 0x011C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE7__FXIO1_D24                                   = IOMUX_PAD(0x011C, 0x011C, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE7__LPSPI2_PCS0                                 = IOMUX_PAD(0x011C, 0x011C, 0x3, 0x029C, 0x2, 0),
+	MX7ULP_PAD_PTE7__LPUART5_RX                                  = IOMUX_PAD(0x011C, 0x011C, 0x4, 0x0254, 0x2, 0),
+	MX7ULP_PAD_PTE7__TPM7_CH4                                    = IOMUX_PAD(0x011C, 0x011C, 0x6, 0x02EC, 0x2, 0),
+	MX7ULP_PAD_PTE7__SDHC1_D5                                    = IOMUX_PAD(0x011C, 0x011C, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE7__FB_A18                                      = IOMUX_PAD(0x011C, 0x011C, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE7__TRACE_D7                                    = IOMUX_PAD(0x011C, 0x011C, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE7__USB0_PWR                                    = IOMUX_PAD(0x011C, 0x011C, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE7__VIU_FID                                     = IOMUX_PAD(0x011C, 0x011C, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE8__PTE8                                        = IOMUX_PAD(0x0120, 0x0120, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE8__TRACE_D6                                    = IOMUX_PAD(0x0120, 0x0120, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE8__VIU_D16                                     = IOMUX_PAD(0x0120, 0x0120, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE8__FXIO1_D23                                   = IOMUX_PAD(0x0120, 0x0120, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE8__LPSPI3_PCS1                                 = IOMUX_PAD(0x0120, 0x0120, 0x3, 0x0314, 0x2, 0),
+	MX7ULP_PAD_PTE8__LPUART6_CTS_b                               = IOMUX_PAD(0x0120, 0x0120, 0x4, 0x025C, 0x2, 0),
+	MX7ULP_PAD_PTE8__LPI2C6_SCL                                  = IOMUX_PAD(0x0120, 0x0120, 0x5, 0x02FC, 0x2, 0),
+	MX7ULP_PAD_PTE8__TPM7_CH5                                    = IOMUX_PAD(0x0120, 0x0120, 0x6, 0x02F0, 0x2, 0),
+	MX7ULP_PAD_PTE8__SDHC1_WP                                    = IOMUX_PAD(0x0120, 0x0120, 0x7, 0x0200, 0x1, 0),
+	MX7ULP_PAD_PTE8__SDHC1_D6                                    = IOMUX_PAD(0x0120, 0x0120, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE8__FB_CS3_b_FB_BE7_0_BLS31_24_b                = IOMUX_PAD(0x0120, 0x0120, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE9__PTE9                                        = IOMUX_PAD(0x0124, 0x0124, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE9__TRACE_D5                                    = IOMUX_PAD(0x0124, 0x0124, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE9__VIU_D17                                     = IOMUX_PAD(0x0124, 0x0124, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE9__FXIO1_D22                                   = IOMUX_PAD(0x0124, 0x0124, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE9__LPSPI3_PCS2                                 = IOMUX_PAD(0x0124, 0x0124, 0x3, 0x0318, 0x2, 0),
+	MX7ULP_PAD_PTE9__LPUART6_RTS_b                               = IOMUX_PAD(0x0124, 0x0124, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE9__LPI2C6_SDA                                  = IOMUX_PAD(0x0124, 0x0124, 0x5, 0x0300, 0x2, 0),
+	MX7ULP_PAD_PTE9__TPM7_CLKIN                                  = IOMUX_PAD(0x0124, 0x0124, 0x6, 0x02F4, 0x2, 0),
+	MX7ULP_PAD_PTE9__SDHC1_CD                                    = IOMUX_PAD(0x0124, 0x0124, 0x7, 0x032C, 0x1, 0),
+	MX7ULP_PAD_PTE9__SDHC1_D7                                    = IOMUX_PAD(0x0124, 0x0124, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE9__FB_TBST_b_FB_CS2_b_FB_BE15_8_BLS23_16_b     = IOMUX_PAD(0x0124, 0x0124, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE10__PTE10                                      = IOMUX_PAD(0x0128, 0x0128, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE10__TRACE_D4                                   = IOMUX_PAD(0x0128, 0x0128, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE10__VIU_D18                                    = IOMUX_PAD(0x0128, 0x0128, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE10__FXIO1_D21                                  = IOMUX_PAD(0x0128, 0x0128, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE10__LPSPI3_PCS3                                = IOMUX_PAD(0x0128, 0x0128, 0x3, 0x031C, 0x2, 0),
+	MX7ULP_PAD_PTE10__LPUART6_TX                                 = IOMUX_PAD(0x0128, 0x0128, 0x4, 0x0264, 0x2, 0),
+	MX7ULP_PAD_PTE10__LPI2C6_HREQ                                = IOMUX_PAD(0x0128, 0x0128, 0x5, 0x02F8, 0x2, 0),
+	MX7ULP_PAD_PTE10__TPM7_CH0                                   = IOMUX_PAD(0x0128, 0x0128, 0x6, 0x02DC, 0x2, 0),
+	MX7ULP_PAD_PTE10__SDHC1_VS                                   = IOMUX_PAD(0x0128, 0x0128, 0x7, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE10__SDHC1_DQS                                  = IOMUX_PAD(0x0128, 0x0128, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE10__FB_A19                                     = IOMUX_PAD(0x0128, 0x0128, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE11__PTE11                                      = IOMUX_PAD(0x012C, 0x012C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE11__TRACE_D3                                   = IOMUX_PAD(0x012C, 0x012C, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE11__VIU_D19                                    = IOMUX_PAD(0x012C, 0x012C, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE11__FXIO1_D20                                  = IOMUX_PAD(0x012C, 0x012C, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE11__LPUART6_RX                                 = IOMUX_PAD(0x012C, 0x012C, 0x4, 0x0260, 0x2, 0),
+	MX7ULP_PAD_PTE11__TPM7_CH1                                   = IOMUX_PAD(0x012C, 0x012C, 0x6, 0x02E0, 0x2, 0),
+	MX7ULP_PAD_PTE11__SDHC1_RESET_b                              = IOMUX_PAD(0x012C, 0x012C, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE11__FB_A20                                     = IOMUX_PAD(0x012C, 0x012C, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE12__PTE12                                      = IOMUX_PAD(0x0130, 0x0130, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE12__FXIO1_D19                                  = IOMUX_PAD(0x0130, 0x0130, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE12__LPSPI3_SIN                                 = IOMUX_PAD(0x0130, 0x0130, 0x3, 0x0324, 0x2, 0),
+	MX7ULP_PAD_PTE12__LPUART7_CTS_b                              = IOMUX_PAD(0x0130, 0x0130, 0x4, 0x0268, 0x2, 0),
+	MX7ULP_PAD_PTE12__LPI2C7_SCL                                 = IOMUX_PAD(0x0130, 0x0130, 0x5, 0x0308, 0x2, 0),
+	MX7ULP_PAD_PTE12__TPM7_CH2                                   = IOMUX_PAD(0x0130, 0x0130, 0x6, 0x02E4, 0x2, 0),
+	MX7ULP_PAD_PTE12__SDHC1_WP                                   = IOMUX_PAD(0x0130, 0x0130, 0x8, 0x0200, 0x2, 0),
+	MX7ULP_PAD_PTE12__FB_A21                                     = IOMUX_PAD(0x0130, 0x0130, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE12__TRACE_D2                                   = IOMUX_PAD(0x0130, 0x0130, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE12__USB1_ULPI_OC2                              = IOMUX_PAD(0x0130, 0x0130, 0xb, 0x0334, 0x2, 0),
+	MX7ULP_PAD_PTE12__VIU_D20                                    = IOMUX_PAD(0x0130, 0x0130, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE13__PTE13                                      = IOMUX_PAD(0x0134, 0x0134, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE13__FXIO1_D18                                  = IOMUX_PAD(0x0134, 0x0134, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE13__LPSPI3_SOUT                                = IOMUX_PAD(0x0134, 0x0134, 0x3, 0x0328, 0x2, 0),
+	MX7ULP_PAD_PTE13__LPUART7_RTS_b                              = IOMUX_PAD(0x0134, 0x0134, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE13__LPI2C7_SDA                                 = IOMUX_PAD(0x0134, 0x0134, 0x5, 0x030C, 0x2, 0),
+	MX7ULP_PAD_PTE13__TPM6_CLKIN                                 = IOMUX_PAD(0x0134, 0x0134, 0x6, 0x02D8, 0x2, 0),
+	MX7ULP_PAD_PTE13__SDHC1_CD                                   = IOMUX_PAD(0x0134, 0x0134, 0x8, 0x032C, 0x2, 0),
+	MX7ULP_PAD_PTE13__FB_A22                                     = IOMUX_PAD(0x0134, 0x0134, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE13__TRACE_D1                                   = IOMUX_PAD(0x0134, 0x0134, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE13__USB1_ULPI_PWR2                             = IOMUX_PAD(0x0134, 0x0134, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE13__VIU_D21                                    = IOMUX_PAD(0x0134, 0x0134, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE14__PTE14                                      = IOMUX_PAD(0x0138, 0x0138, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE14__FXIO1_D17                                  = IOMUX_PAD(0x0138, 0x0138, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE14__LPSPI3_SCK                                 = IOMUX_PAD(0x0138, 0x0138, 0x3, 0x0320, 0x2, 0),
+	MX7ULP_PAD_PTE14__LPUART7_TX                                 = IOMUX_PAD(0x0138, 0x0138, 0x4, 0x0270, 0x2, 0),
+	MX7ULP_PAD_PTE14__LPI2C7_HREQ                                = IOMUX_PAD(0x0138, 0x0138, 0x5, 0x0304, 0x2, 0),
+	MX7ULP_PAD_PTE14__TPM6_CH0                                   = IOMUX_PAD(0x0138, 0x0138, 0x6, 0x02D0, 0x2, 0),
+	MX7ULP_PAD_PTE14__SDHC1_VS                                   = IOMUX_PAD(0x0138, 0x0138, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE14__FB_A23                                     = IOMUX_PAD(0x0138, 0x0138, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE14__TRACE_D0                                   = IOMUX_PAD(0x0138, 0x0138, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE14__USB0_OC                                    = IOMUX_PAD(0x0138, 0x0138, 0xb, 0x0330, 0x2, 0),
+	MX7ULP_PAD_PTE14__VIU_D22                                    = IOMUX_PAD(0x0138, 0x0138, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE15__PTE15                                      = IOMUX_PAD(0x013C, 0x013C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE15__FXIO1_D16                                  = IOMUX_PAD(0x013C, 0x013C, 0x2, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE15__LPSPI3_PCS0                                = IOMUX_PAD(0x013C, 0x013C, 0x3, 0x0310, 0x2, 0),
+	MX7ULP_PAD_PTE15__LPUART7_RX                                 = IOMUX_PAD(0x013C, 0x013C, 0x4, 0x026C, 0x2, 0),
+	MX7ULP_PAD_PTE15__TPM6_CH1                                   = IOMUX_PAD(0x013C, 0x013C, 0x6, 0x02D4, 0x2, 0),
+	MX7ULP_PAD_PTE15__FB_A24                                     = IOMUX_PAD(0x013C, 0x013C, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE15__TRACE_CLKOUT                               = IOMUX_PAD(0x013C, 0x013C, 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE15__USB0_PWR                                   = IOMUX_PAD(0x013C, 0x013C, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE15__VIU_D23                                    = IOMUX_PAD(0x013C, 0x013C, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF0__PTF0                                        = IOMUX_PAD(0x0180, 0x0180, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF0__LPUART4_CTS_b                               = IOMUX_PAD(0x0180, 0x0180, 0x4, 0x0244, 0x3, 0),
+	MX7ULP_PAD_PTF0__LPI2C4_SCL                                  = IOMUX_PAD(0x0180, 0x0180, 0x5, 0x0278, 0x3, 0),
+	MX7ULP_PAD_PTF0__TPM4_CLKIN                                  = IOMUX_PAD(0x0180, 0x0180, 0x6, 0x0298, 0x3, 0),
+	MX7ULP_PAD_PTF0__FB_RW_b                                     = IOMUX_PAD(0x0180, 0x0180, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF0__VIU_DE                                      = IOMUX_PAD(0x0180, 0x0180, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF1__PTF1                                        = IOMUX_PAD(0x0184, 0x0184, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF1__LPUART4_RTS_b                               = IOMUX_PAD(0x0184, 0x0184, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF1__LPI2C4_SDA                                  = IOMUX_PAD(0x0184, 0x0184, 0x5, 0x027C, 0x3, 0),
+	MX7ULP_PAD_PTF1__TPM4_CH0                                    = IOMUX_PAD(0x0184, 0x0184, 0x6, 0x0280, 0x3, 0),
+	MX7ULP_PAD_PTF1__CLKOUT                                      = IOMUX_PAD(0x0184, 0x0184, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF1__VIU_HSYNC                                   = IOMUX_PAD(0x0184, 0x0184, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF2__PTF2                                        = IOMUX_PAD(0x0188, 0x0188, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF2__LPUART4_TX                                  = IOMUX_PAD(0x0188, 0x0188, 0x4, 0x024C, 0x3, 0),
+	MX7ULP_PAD_PTF2__LPI2C4_HREQ                                 = IOMUX_PAD(0x0188, 0x0188, 0x5, 0x0274, 0x3, 0),
+	MX7ULP_PAD_PTF2__TPM4_CH1                                    = IOMUX_PAD(0x0188, 0x0188, 0x6, 0x0284, 0x3, 0),
+	MX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_b_FB_BE23_16_BLS15_8_b      = IOMUX_PAD(0x0188, 0x0188, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF2__VIU_VSYNC                                   = IOMUX_PAD(0x0188, 0x0188, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF3__PTF3                                        = IOMUX_PAD(0x018C, 0x018C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF3__LPUART4_RX                                  = IOMUX_PAD(0x018C, 0x018C, 0x4, 0x0248, 0x3, 0),
+	MX7ULP_PAD_PTF3__TPM4_CH2                                    = IOMUX_PAD(0x018C, 0x018C, 0x6, 0x0288, 0x3, 0),
+	MX7ULP_PAD_PTF3__FB_AD16                                     = IOMUX_PAD(0x018C, 0x018C, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF3__VIU_PCLK                                    = IOMUX_PAD(0x018C, 0x018C, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF4__PTF4                                        = IOMUX_PAD(0x0190, 0x0190, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF4__FXIO1_D0                                    = IOMUX_PAD(0x0190, 0x0190, 0x2, 0x0204, 0x2, 0),
+	MX7ULP_PAD_PTF4__LPSPI2_PCS1                                 = IOMUX_PAD(0x0190, 0x0190, 0x3, 0x02A0, 0x3, 0),
+	MX7ULP_PAD_PTF4__LPUART5_CTS_b                               = IOMUX_PAD(0x0190, 0x0190, 0x4, 0x0250, 0x3, 0),
+	MX7ULP_PAD_PTF4__LPI2C5_SCL                                  = IOMUX_PAD(0x0190, 0x0190, 0x5, 0x02BC, 0x3, 0),
+	MX7ULP_PAD_PTF4__TPM4_CH3                                    = IOMUX_PAD(0x0190, 0x0190, 0x6, 0x028C, 0x2, 0),
+	MX7ULP_PAD_PTF4__FB_AD17                                     = IOMUX_PAD(0x0190, 0x0190, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF4__VIU_D0                                      = IOMUX_PAD(0x0190, 0x0190, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF5__PTF5                                        = IOMUX_PAD(0x0194, 0x0194, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF5__FXIO1_D1                                    = IOMUX_PAD(0x0194, 0x0194, 0x2, 0x0208, 0x2, 0),
+	MX7ULP_PAD_PTF5__LPSPI2_PCS2                                 = IOMUX_PAD(0x0194, 0x0194, 0x3, 0x02A4, 0x3, 0),
+	MX7ULP_PAD_PTF5__LPUART5_RTS_b                               = IOMUX_PAD(0x0194, 0x0194, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF5__LPI2C5_SDA                                  = IOMUX_PAD(0x0194, 0x0194, 0x5, 0x02C0, 0x3, 0),
+	MX7ULP_PAD_PTF5__TPM4_CH4                                    = IOMUX_PAD(0x0194, 0x0194, 0x6, 0x0290, 0x2, 0),
+	MX7ULP_PAD_PTF5__FB_AD18                                     = IOMUX_PAD(0x0194, 0x0194, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF5__VIU_D1                                      = IOMUX_PAD(0x0194, 0x0194, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF6__PTF6                                        = IOMUX_PAD(0x0198, 0x0198, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF6__FXIO1_D2                                    = IOMUX_PAD(0x0198, 0x0198, 0x2, 0x020C, 0x2, 0),
+	MX7ULP_PAD_PTF6__LPSPI2_PCS3                                 = IOMUX_PAD(0x0198, 0x0198, 0x3, 0x02A8, 0x3, 0),
+	MX7ULP_PAD_PTF6__LPUART5_TX                                  = IOMUX_PAD(0x0198, 0x0198, 0x4, 0x0258, 0x3, 0),
+	MX7ULP_PAD_PTF6__LPI2C5_HREQ                                 = IOMUX_PAD(0x0198, 0x0198, 0x5, 0x02B8, 0x3, 0),
+	MX7ULP_PAD_PTF6__TPM4_CH5                                    = IOMUX_PAD(0x0198, 0x0198, 0x6, 0x0294, 0x2, 0),
+	MX7ULP_PAD_PTF6__FB_AD19                                     = IOMUX_PAD(0x0198, 0x0198, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF6__VIU_D2                                      = IOMUX_PAD(0x0198, 0x0198, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF7__PTF7                                        = IOMUX_PAD(0x019C, 0x019C, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF7__FXIO1_D3                                    = IOMUX_PAD(0x019C, 0x019C, 0x2, 0x0210, 0x2, 0),
+	MX7ULP_PAD_PTF7__LPUART5_RX                                  = IOMUX_PAD(0x019C, 0x019C, 0x4, 0x0254, 0x3, 0),
+	MX7ULP_PAD_PTF7__TPM5_CH1                                    = IOMUX_PAD(0x019C, 0x019C, 0x6, 0x02C8, 0x3, 0),
+	MX7ULP_PAD_PTF7__FB_AD20                                     = IOMUX_PAD(0x019C, 0x019C, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF7__VIU_D3                                      = IOMUX_PAD(0x019C, 0x019C, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF8__PTF8                                        = IOMUX_PAD(0x01A0, 0x01A0, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF8__FXIO1_D4                                    = IOMUX_PAD(0x01A0, 0x01A0, 0x2, 0x0214, 0x2, 0),
+	MX7ULP_PAD_PTF8__LPSPI2_SIN                                  = IOMUX_PAD(0x01A0, 0x01A0, 0x3, 0x02B0, 0x3, 0),
+	MX7ULP_PAD_PTF8__LPUART6_CTS_b                               = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0),
+	MX7ULP_PAD_PTF8__LPI2C6_SCL                                  = IOMUX_PAD(0x01A0, 0x01A0, 0x5, 0x02FC, 0x3, 0),
+	MX7ULP_PAD_PTF8__TPM5_CLKIN                                  = IOMUX_PAD(0x01A0, 0x01A0, 0x6, 0x02CC, 0x3, 0),
+	MX7ULP_PAD_PTF8__FB_AD21                                     = IOMUX_PAD(0x01A0, 0x01A0, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF8__USB1_ULPI_CLK                               = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF8__VIU_D4                                      = IOMUX_PAD(0x01A0, 0x01A0, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF9__PTF9                                        = IOMUX_PAD(0x01A4, 0x01A4, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF9__FXIO1_D5                                    = IOMUX_PAD(0x01A4, 0x01A4, 0x2, 0x0218, 0x2, 0),
+	MX7ULP_PAD_PTF9__LPSPI2_SOUT                                 = IOMUX_PAD(0x01A4, 0x01A4, 0x3, 0x02B4, 0x3, 0),
+	MX7ULP_PAD_PTF9__LPUART6_RTS_b                               = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF9__LPI2C6_SDA                                  = IOMUX_PAD(0x01A4, 0x01A4, 0x5, 0x0300, 0x3, 0),
+	MX7ULP_PAD_PTF9__TPM5_CH0                                    = IOMUX_PAD(0x01A4, 0x01A4, 0x6, 0x02C4, 0x3, 0),
+	MX7ULP_PAD_PTF9__FB_AD22                                     = IOMUX_PAD(0x01A4, 0x01A4, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF9__USB1_ULPI_NXT                               = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF9__VIU_D5                                      = IOMUX_PAD(0x01A4, 0x01A4, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF10__PTF10                                      = IOMUX_PAD(0x01A8, 0x01A8, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF10__FXIO1_D6                                   = IOMUX_PAD(0x01A8, 0x01A8, 0x2, 0x021C, 0x2, 0),
+	MX7ULP_PAD_PTF10__LPSPI2_SCK                                 = IOMUX_PAD(0x01A8, 0x01A8, 0x3, 0x02AC, 0x3, 0),
+	MX7ULP_PAD_PTF10__LPUART6_TX                                 = IOMUX_PAD(0x01A8, 0x01A8, 0x4, 0x0264, 0x3, 0),
+	MX7ULP_PAD_PTF10__LPI2C6_HREQ                                = IOMUX_PAD(0x01A8, 0x01A8, 0x5, 0x02F8, 0x3, 0),
+	MX7ULP_PAD_PTF10__TPM7_CH3                                   = IOMUX_PAD(0x01A8, 0x01A8, 0x6, 0x02E8, 0x3, 0),
+	MX7ULP_PAD_PTF10__FB_AD23                                    = IOMUX_PAD(0x01A8, 0x01A8, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF10__USB1_ULPI_STP                              = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF10__VIU_D6                                     = IOMUX_PAD(0x01A8, 0x01A8, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF11__PTF11                                      = IOMUX_PAD(0x01AC, 0x01AC, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF11__FXIO1_D7                                   = IOMUX_PAD(0x01AC, 0x01AC, 0x2, 0x0220, 0x2, 0),
+	MX7ULP_PAD_PTF11__LPSPI2_PCS0                                = IOMUX_PAD(0x01AC, 0x01AC, 0x3, 0x029C, 0x3, 0),
+	MX7ULP_PAD_PTF11__LPUART6_RX                                 = IOMUX_PAD(0x01AC, 0x01AC, 0x4, 0x0260, 0x3, 0),
+	MX7ULP_PAD_PTF11__TPM7_CH4                                   = IOMUX_PAD(0x01AC, 0x01AC, 0x6, 0x02EC, 0x3, 0),
+	MX7ULP_PAD_PTF11__FB_CS4_b_FB_TSIZ0_FB_BE31_24_BLS7_0_b      = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF11__USB1_ULPI_DIR                              = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF11__VIU_D7                                     = IOMUX_PAD(0x01AC, 0x01AC, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF12__PTF12                                      = IOMUX_PAD(0x01B0, 0x01B0, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF12__FXIO1_D8                                   = IOMUX_PAD(0x01B0, 0x01B0, 0x2, 0x0224, 0x2, 0),
+	MX7ULP_PAD_PTF12__LPSPI3_PCS1                                = IOMUX_PAD(0x01B0, 0x01B0, 0x3, 0x0314, 0x3, 0),
+	MX7ULP_PAD_PTF12__LPUART7_CTS_b                              = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0),
+	MX7ULP_PAD_PTF12__LPI2C7_SCL                                 = IOMUX_PAD(0x01B0, 0x01B0, 0x5, 0x0308, 0x3, 0),
+	MX7ULP_PAD_PTF12__TPM7_CH5                                   = IOMUX_PAD(0x01B0, 0x01B0, 0x6, 0x02F0, 0x3, 0),
+	MX7ULP_PAD_PTF12__FB_AD24                                    = IOMUX_PAD(0x01B0, 0x01B0, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF12__USB1_ULPI_DATA0                            = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF12__VIU_D8                                     = IOMUX_PAD(0x01B0, 0x01B0, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF13__PTF13                                      = IOMUX_PAD(0x01B4, 0x01B4, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF13__FXIO1_D9                                   = IOMUX_PAD(0x01B4, 0x01B4, 0x2, 0x0228, 0x2, 0),
+	MX7ULP_PAD_PTF13__LPSPI3_PCS2                                = IOMUX_PAD(0x01B4, 0x01B4, 0x3, 0x0318, 0x3, 0),
+	MX7ULP_PAD_PTF13__LPUART7_RTS_b                              = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF13__LPI2C7_SDA                                 = IOMUX_PAD(0x01B4, 0x01B4, 0x5, 0x030C, 0x3, 0),
+	MX7ULP_PAD_PTF13__TPM7_CLKIN                                 = IOMUX_PAD(0x01B4, 0x01B4, 0x6, 0x02F4, 0x3, 0),
+	MX7ULP_PAD_PTF13__FB_AD25                                    = IOMUX_PAD(0x01B4, 0x01B4, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF13__USB1_ULPI_DATA1                            = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF13__VIU_D9                                     = IOMUX_PAD(0x01B4, 0x01B4, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF14__PTF14                                      = IOMUX_PAD(0x01B8, 0x01B8, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF14__FXIO1_D10                                  = IOMUX_PAD(0x01B8, 0x01B8, 0x2, 0x022C, 0x2, 0),
+	MX7ULP_PAD_PTF14__LPSPI3_PCS3                                = IOMUX_PAD(0x01B8, 0x01B8, 0x3, 0x031C, 0x3, 0),
+	MX7ULP_PAD_PTF14__LPUART7_TX                                 = IOMUX_PAD(0x01B8, 0x01B8, 0x4, 0x0270, 0x3, 0),
+	MX7ULP_PAD_PTF14__LPI2C7_HREQ                                = IOMUX_PAD(0x01B8, 0x01B8, 0x5, 0x0304, 0x3, 0),
+	MX7ULP_PAD_PTF14__TPM7_CH0                                   = IOMUX_PAD(0x01B8, 0x01B8, 0x6, 0x02DC, 0x3, 0),
+	MX7ULP_PAD_PTF14__FB_AD26                                    = IOMUX_PAD(0x01B8, 0x01B8, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF14__USB1_ULPI_DATA2                            = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF14__VIU_D10                                    = IOMUX_PAD(0x01B8, 0x01B8, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF15__PTF15                                      = IOMUX_PAD(0x01BC, 0x01BC, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF15__FXIO1_D11                                  = IOMUX_PAD(0x01BC, 0x01BC, 0x2, 0x0230, 0x2, 0),
+	MX7ULP_PAD_PTF15__LPUART7_RX                                 = IOMUX_PAD(0x01BC, 0x01BC, 0x4, 0x026C, 0x3, 0),
+	MX7ULP_PAD_PTF15__TPM7_CH1                                   = IOMUX_PAD(0x01BC, 0x01BC, 0x6, 0x02E0, 0x3, 0),
+	MX7ULP_PAD_PTF15__FB_AD27                                    = IOMUX_PAD(0x01BC, 0x01BC, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF15__USB1_ULPI_DATA3                            = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF15__VIU_D11                                    = IOMUX_PAD(0x01BC, 0x01BC, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF16__PTF16                                      = IOMUX_PAD(0x01C0, 0x01C0, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF16__USB1_ULPI_DATA4                            = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF16__VIU_D12                                    = IOMUX_PAD(0x01C0, 0x01C0, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF16__FXIO1_D12                                  = IOMUX_PAD(0x01C0, 0x01C0, 0x2, 0x0234, 0x2, 0),
+	MX7ULP_PAD_PTF16__LPSPI3_SIN                                 = IOMUX_PAD(0x01C0, 0x01C0, 0x3, 0x0324, 0x3, 0),
+	MX7ULP_PAD_PTF16__TPM7_CH2                                   = IOMUX_PAD(0x01C0, 0x01C0, 0x6, 0x02E4, 0x3, 0),
+	MX7ULP_PAD_PTF16__FB_AD28                                    = IOMUX_PAD(0x01C0, 0x01C0, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF17__PTF17                                      = IOMUX_PAD(0x01C4, 0x01C4, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF17__USB1_ULPI_DATA5                            = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF17__VIU_D13                                    = IOMUX_PAD(0x01C4, 0x01C4, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF17__FXIO1_D13                                  = IOMUX_PAD(0x01C4, 0x01C4, 0x2, 0x0238, 0x2, 0),
+	MX7ULP_PAD_PTF17__LPSPI3_SOUT                                = IOMUX_PAD(0x01C4, 0x01C4, 0x3, 0x0328, 0x3, 0),
+	MX7ULP_PAD_PTF17__TPM6_CLKIN                                 = IOMUX_PAD(0x01C4, 0x01C4, 0x6, 0x02D8, 0x3, 0),
+	MX7ULP_PAD_PTF17__FB_AD29                                    = IOMUX_PAD(0x01C4, 0x01C4, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF18__PTF18                                      = IOMUX_PAD(0x01C8, 0x01C8, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF18__USB1_ULPI_DATA6                            = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF18__VIU_D14                                    = IOMUX_PAD(0x01C8, 0x01C8, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF18__FXIO1_D14                                  = IOMUX_PAD(0x01C8, 0x01C8, 0x2, 0x023C, 0x2, 0),
+	MX7ULP_PAD_PTF18__LPSPI3_SCK                                 = IOMUX_PAD(0x01C8, 0x01C8, 0x3, 0x0320, 0x3, 0),
+	MX7ULP_PAD_PTF18__TPM6_CH0                                   = IOMUX_PAD(0x01C8, 0x01C8, 0x6, 0x02D0, 0x3, 0),
+	MX7ULP_PAD_PTF18__FB_AD30                                    = IOMUX_PAD(0x01C8, 0x01C8, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF19__PTF19                                      = IOMUX_PAD(0x01CC, 0x01CC, 0x1, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF19__USB1_ULPI_DATA7                            = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF19__VIU_D15                                    = IOMUX_PAD(0x01CC, 0x01CC, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF19__FXIO1_D15                                  = IOMUX_PAD(0x01CC, 0x01CC, 0x2, 0x0240, 0x2, 0),
+	MX7ULP_PAD_PTF19__LPSPI3_PCS0                                = IOMUX_PAD(0x01CC, 0x01CC, 0x3, 0x0310, 0x3, 0),
+	MX7ULP_PAD_PTF19__TPM6_CH1                                   = IOMUX_PAD(0x01CC, 0x01CC, 0x6, 0x02D4, 0x3, 0),
+	MX7ULP_PAD_PTF19__FB_AD31                                    = IOMUX_PAD(0x01CC, 0x01CC, 0x9, 0x0000, 0x0, 0),
+};
+#endif  /* __ASM_ARCH_IMX7ULP_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S
new file mode 100644
index 0000000..bcc804b
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <config.h>
+
+#define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
+#define ROM_VERSION_OFFSET               	0x80
+#define ROM_API_HWCNFG_SETUP_OFFSET		0x08
+
+plugin_start:
+
+	push    {r0-r4, lr}
+
+	imx7ulp_ddr_setting
+	imx7ulp_clock_gating
+	imx7ulp_qos_setting
+
+normal_boot:
+
+/*
+ * The following is to fill in those arguments for this ROM function
+ * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
+ * This function is used to copy data from the storage media into DDR.
+ * start - Initial (possibly partial) image load address on entry.
+ *         Final image load address on exit.
+ * bytes - Initial (possibly partial) image size on entry.
+ *         Final image size on exit.
+ * boot_data - Initial @ref ivt Boot Data load address.
+ */
+	adr r0, boot_data2
+	adr r1, image_len2
+	adr r2, boot_data2
+
+/*
+ * check the _pu_irom_api_table for the address
+ */
+before_calling_rom___pu_irom_hwcnfg_setup:
+	ldr r3, =ROM_VERSION_OFFSET
+	ldr r4, [r3]
+	ldr r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
+	ldr r4, [r3, #ROM_API_HWCNFG_SETUP_OFFSET]
+	blx r4
+after_calling_rom___pu_irom_hwcnfg_setup:
+
+/*
+ * To return to ROM from plugin, we need to fill in these argument.
+ * Here is what need to do:
+ * Need to construct the parameters for this function before return to ROM:
+ * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset)
+ */
+	pop {r0-r4, lr}
+	push {r5}
+	ldr r5, boot_data2
+	str r5, [r0]
+	ldr r5, image_len2
+	str r5, [r1]
+	ldr r5, second_ivt_offset
+	str r5, [r2]
+	mov r0, #1
+	pop {r5}
+
+	/* return back to ROM code */
+	bx lr
+
+/* make the following data right in the end of the output*/
+.ltorg
+
+#define FLASH_OFFSET 0x400
+
+/*
+ * second_ivt_offset is the offset from the "second_ivt_header" to
+ * "image_copy_start", which involves FLASH_OFFSET, plus the first
+ * ivt_header, the plugin code size itself recorded by "ivt2_header"
+ */
+
+second_ivt_offset:      .long (ivt2_header + 0x2C + FLASH_OFFSET)
+
+/*
+ * The following is the second IVT header plus the second boot data
+ */
+ivt2_header:            .long 0x0
+app2_code_jump_v:       .long 0x0
+reserv3:                .long 0x0
+dcd2_ptr:               .long 0x0
+boot_data2_ptr:         .long 0x0
+self_ptr2:              .long 0x0
+app_code_csf2:          .long 0x0
+reserv4:                .long 0x0
+boot_data2:             .long 0x0
+image_len2:             .long 0x0
+plugin2:                .long 0x0
diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h
new file mode 100644
index 0000000..dee3cfc
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/pcc.h
@@ -0,0 +1,372 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_ARCH_PCC_H
+#define _ASM_ARCH_PCC_H
+
+#include <common.h>
+#include <asm/arch/scg.h>
+
+/* PCC2 */
+
+enum pcc2_entry {
+	/* On-Platform (32 entries) */
+	RSVD0_PCC2_SLOT			= 0,
+	RSVD1_PCC2_SLOT			= 1,
+	CA7_GIC_PCC2_SLOT		= 2,
+	RSVD3_PCC2_SLOT			= 3,
+	RSVD4_PCC2_SLOT			= 4,
+	RSVD5_PCC2_SLOT			= 5,
+	RSVD6_PCC2_SLOT			= 6,
+	RSVD7_PCC2_SLOT			= 7,
+	DMA1_PCC2_SLOT			= 8,
+	RSVD9_PCC2_SLOT			= 9,
+	RSVD10_PCC2_SLOT		= 10,
+	RSVD11_PCC2_SLOT		= 11,
+	RSVD12_PCC2_SLOT		= 12,
+	RSVD13_PCC2_SLOT		= 13,
+	RSVD14_PCC2_SLOT		= 14,
+	RGPIO1_PCC2_SLOT		= 15,
+	FLEXBUS0_PCC2_SLOT		= 16,
+	RSVD17_PCC2_SLOT		= 17,
+	RSVD18_PCC2_SLOT		= 18,
+	RSVD19_PCC2_SLOT		= 19,
+	RSVD20_PCC2_SLOT		= 20,
+	RSVD21_PCC2_SLOT		= 21,
+	RSVD22_PCC2_SLOT		= 22,
+	RSVD23_PCC2_SLOT		= 23,
+	RSVD24_PCC2_SLOT		= 24,
+	RSVD25_PCC2_SLOT		= 25,
+	RSVD26_PCC2_SLOT		= 26,
+	SEMA42_1_PCC2_SLOT		= 27,
+	RSVD28_PCC2_SLOT		= 28,
+	RSVD29_PCC2_SLOT		= 29,
+	RSVD30_PCC2_SLOT		= 30,
+	RSVD31_PCC2_SLOT		= 31,
+
+	/* Off-Platform (96 entries) */
+	RSVD32_PCC2_SLOT		= 32,
+	DMA1_CH_MUX0_PCC2_SLOT		= 33,
+	MU_B_PCC2_SLOT			= 34,
+	SNVS_PCC2_SLOT			= 35,
+	CAAM_PCC2_SLOT			= 36,
+	LPTPM4_PCC2_SLOT		= 37,
+	LPTPM5_PCC2_SLOT		= 38,
+	LPIT1_PCC2_SLOT			= 39,
+	RSVD40_PCC2_SLOT		= 40,
+	LPSPI2_PCC2_SLOT		= 41,
+	LPSPI3_PCC2_SLOT		= 42,
+	LPI2C4_PCC2_SLOT		= 43,
+	LPI2C5_PCC2_SLOT		= 44,
+	LPUART4_PCC2_SLOT		= 45,
+	LPUART5_PCC2_SLOT		= 46,
+	RSVD47_PCC2_SLOT		= 47,
+	RSVD48_PCC2_SLOT		= 48,
+	FLEXIO1_PCC2_SLOT		= 49,
+	RSVD50_PCC2_SLOT		= 50,
+	USBOTG0_PCC2_SLOT		= 51,
+	USBOTG1_PCC2_SLOT		= 52,
+	USBPHY_PCC2_SLOT		= 53,
+	USB_PL301_PCC2_SLOT		= 54,
+	USDHC0_PCC2_SLOT		= 55,
+	USDHC1_PCC2_SLOT		= 56,
+	RSVD57_PCC2_SLOT		= 57,
+	TRGMUX1_PCC2_SLOT		= 58,
+	RSVD59_PCC2_SLOT		= 59,
+	RSVD60_PCC2_SLOT		= 60,
+	WDG1_PCC2_SLOT			= 61,
+	SCG1_PCC2_SLOT			= 62,
+	PCC2_PCC2_SLOT			= 63,
+	PMC1_PCC2_SLOT			= 64,
+	SMC1_PCC2_SLOT			= 65,
+	RCM1_PCC2_SLOT			= 66,
+	WDG2_PCC2_SLOT			= 67,
+	RSVD68_PCC2_SLOT		= 68,
+	TEST_SPACE1_PCC2_SLOT		= 69,
+	TEST_SPACE2_PCC2_SLOT		= 70,
+	TEST_SPACE3_PCC2_SLOT		= 71,
+	RSVD72_PCC2_SLOT		= 72,
+	RSVD73_PCC2_SLOT		= 73,
+	RSVD74_PCC2_SLOT		= 74,
+	RSVD75_PCC2_SLOT		= 75,
+	RSVD76_PCC2_SLOT		= 76,
+	RSVD77_PCC2_SLOT		= 77,
+	RSVD78_PCC2_SLOT		= 78,
+	RSVD79_PCC2_SLOT		= 79,
+	RSVD80_PCC2_SLOT		= 80,
+	RSVD81_PCC2_SLOT		= 81,
+	RSVD82_PCC2_SLOT		= 82,
+	RSVD83_PCC2_SLOT		= 83,
+	RSVD84_PCC2_SLOT		= 84,
+	RSVD85_PCC2_SLOT		= 85,
+	RSVD86_PCC2_SLOT		= 86,
+	RSVD87_PCC2_SLOT		= 87,
+	RSVD88_PCC2_SLOT		= 88,
+	RSVD89_PCC2_SLOT		= 89,
+	RSVD90_PCC2_SLOT		= 90,
+	RSVD91_PCC2_SLOT		= 91,
+	RSVD92_PCC2_SLOT		= 92,
+	RSVD93_PCC2_SLOT		= 93,
+	RSVD94_PCC2_SLOT		= 94,
+	RSVD95_PCC2_SLOT		= 95,
+	RSVD96_PCC2_SLOT		= 96,
+	RSVD97_PCC2_SLOT		= 97,
+	RSVD98_PCC2_SLOT		= 98,
+	RSVD99_PCC2_SLOT		= 99,
+	RSVD100_PCC2_SLOT		= 100,
+	RSVD101_PCC2_SLOT		= 101,
+	RSVD102_PCC2_SLOT		= 102,
+	RSVD103_PCC2_SLOT		= 103,
+	RSVD104_PCC2_SLOT		= 104,
+	RSVD105_PCC2_SLOT		= 105,
+	RSVD106_PCC2_SLOT		= 106,
+	RSVD107_PCC2_SLOT		= 107,
+	RSVD108_PCC2_SLOT		= 108,
+	RSVD109_PCC2_SLOT		= 109,
+	RSVD110_PCC2_SLOT		= 110,
+	RSVD111_PCC2_SLOT		= 111,
+	RSVD112_PCC2_SLOT		= 112,
+	RSVD113_PCC2_SLOT		= 113,
+	RSVD114_PCC2_SLOT		= 114,
+	RSVD115_PCC2_SLOT		= 115,
+	RSVD116_PCC2_SLOT		= 116,
+	RSVD117_PCC2_SLOT		= 117,
+	RSVD118_PCC2_SLOT		= 118,
+	RSVD119_PCC2_SLOT		= 119,
+	RSVD120_PCC2_SLOT		= 120,
+	RSVD121_PCC2_SLOT		= 121,
+	RSVD122_PCC2_SLOT		= 122,
+	RSVD123_PCC2_SLOT		= 123,
+	RSVD124_PCC2_SLOT		= 124,
+	RSVD125_PCC2_SLOT		= 125,
+	RSVD126_PCC2_SLOT		= 126,
+	RSVD127_PCC2_SLOT		= 127,
+};
+
+enum pcc3_entry {
+	/* On-Platform (32 entries) */
+	RSVD0_PCC3_SLOT			= 0,
+	RSVD1_PCC3_SLOT			= 1,
+	RSVD2_PCC3_SLOT			= 2,
+	RSVD3_PCC3_SLOT			= 3,
+	RSVD4_PCC3_SLOT			= 4,
+	RSVD5_PCC3_SLOT			= 5,
+	RSVD6_PCC3_SLOT			= 6,
+	RSVD7_PCC3_SLOT			= 7,
+	RSVD8_PCC3_SLOT			= 8,
+	RSVD9_PCC3_SLOT			= 9,
+	RSVD10_PCC3_SLOT		= 10,
+	RSVD11_PCC3_SLOT		= 11,
+	RSVD12_PCC3_SLOT		= 12,
+	RSVD13_PCC3_SLOT		= 13,
+	RSVD14_PCC3_SLOT		= 14,
+	RSVD15_PCC3_SLOT		= 15,
+	ROMCP1_PCC3_SLOT		= 16,
+	RSVD17_PCC3_SLOT		= 17,
+	RSVD18_PCC3_SLOT		= 18,
+	RSVD19_PCC3_SLOT		= 19,
+	RSVD20_PCC3_SLOT		= 20,
+	RSVD21_PCC3_SLOT		= 21,
+	RSVD22_PCC3_SLOT		= 22,
+	RSVD23_PCC3_SLOT		= 23,
+	RSVD24_PCC3_SLOT		= 24,
+	RSVD25_PCC3_SLOT		= 25,
+	RSVD26_PCC3_SLOT		= 26,
+	RSVD27_PCC3_SLOT		= 27,
+	RSVD28_PCC3_SLOT		= 28,
+	RSVD29_PCC3_SLOT		= 29,
+	RSVD30_PCC3_SLOT		= 30,
+	RSVD31_PCC3_SLOT		= 31,
+
+	/* Off-Platform (96 entries) */
+	RSVD32_PCC3_SLOT		= 32,
+	LPTPM6_PCC3_SLOT		= 33,
+	LPTPM7_PCC3_SLOT		= 34,
+	RSVD35_PCC3_SLOT		= 35,
+	LPI2C6_PCC3_SLOT		= 36,
+	LPI2C7_PCC3_SLOT		= 37,
+	LPUART6_PCC3_SLOT		= 38,
+	LPUART7_PCC3_SLOT		= 39,
+	VIU0_PCC3_SLOT			= 40,
+	DSI0_PCC3_SLOT			= 41,
+	LCDIF0_PCC3_SLOT		= 42,
+	MMDC0_PCC3_SLOT			= 43,
+	IOMUXC1_PCC3_SLOT		= 44,
+	IOMUXC_DDR_PCC3_SLOT		= 45,
+	PORTC_PCC3_SLOT			= 46,
+	PORTD_PCC3_SLOT			= 47,
+	PORTE_PCC3_SLOT			= 48,
+	PORTF_PCC3_SLOT			= 49,
+	RSVD50_PCC3_SLOT		= 50,
+	PCC3_PCC3_SLOT			= 51,
+	RSVD52_PCC3_SLOT		= 52,
+	WKPU_PCC3_SLOT			= 53,
+	RSVD54_PCC3_SLOT		= 54,
+	RSVD55_PCC3_SLOT		= 55,
+	RSVD56_PCC3_SLOT		= 56,
+	RSVD57_PCC3_SLOT		= 57,
+	RSVD58_PCC3_SLOT		= 58,
+	RSVD59_PCC3_SLOT		= 59,
+	RSVD60_PCC3_SLOT		= 60,
+	RSVD61_PCC3_SLOT		= 61,
+	RSVD62_PCC3_SLOT		= 62,
+	RSVD63_PCC3_SLOT		= 63,
+	RSVD64_PCC3_SLOT		= 64,
+	RSVD65_PCC3_SLOT		= 65,
+	RSVD66_PCC3_SLOT		= 66,
+	RSVD67_PCC3_SLOT		= 67,
+	RSVD68_PCC3_SLOT		= 68,
+	RSVD69_PCC3_SLOT		= 69,
+	RSVD70_PCC3_SLOT		= 70,
+	RSVD71_PCC3_SLOT		= 71,
+	RSVD72_PCC3_SLOT		= 72,
+	RSVD73_PCC3_SLOT		= 73,
+	RSVD74_PCC3_SLOT		= 74,
+	RSVD75_PCC3_SLOT		= 75,
+	RSVD76_PCC3_SLOT		= 76,
+	RSVD77_PCC3_SLOT		= 77,
+	RSVD78_PCC3_SLOT		= 78,
+	RSVD79_PCC3_SLOT		= 79,
+	RSVD80_PCC3_SLOT		= 80,
+	GPU3D_PCC3_SLOT			= 81,
+	GPU2D_PCC3_SLOT			= 82,
+	RSVD83_PCC3_SLOT		= 83,
+	RSVD84_PCC3_SLOT		= 84,
+	RSVD85_PCC3_SLOT		= 85,
+	RSVD86_PCC3_SLOT		= 86,
+	RSVD87_PCC3_SLOT		= 87,
+	RSVD88_PCC3_SLOT		= 88,
+	RSVD89_PCC3_SLOT		= 89,
+	RSVD90_PCC3_SLOT		= 90,
+	RSVD91_PCC3_SLOT		= 91,
+	RSVD92_PCC3_SLOT		= 92,
+	RSVD93_PCC3_SLOT		= 93,
+	RSVD94_PCC3_SLOT		= 94,
+	RSVD95_PCC3_SLOT		= 95,
+	RSVD96_PCC3_SLOT		= 96,
+	RSVD97_PCC3_SLOT		= 97,
+	RSVD98_PCC3_SLOT		= 98,
+	RSVD99_PCC3_SLOT		= 99,
+	RSVD100_PCC3_SLOT		= 100,
+	RSVD101_PCC3_SLOT		= 101,
+	RSVD102_PCC3_SLOT		= 102,
+	RSVD103_PCC3_SLOT		= 103,
+	RSVD104_PCC3_SLOT		= 104,
+	RSVD105_PCC3_SLOT		= 105,
+	RSVD106_PCC3_SLOT		= 106,
+	RSVD107_PCC3_SLOT		= 107,
+	RSVD108_PCC3_SLOT		= 108,
+	RSVD109_PCC3_SLOT		= 109,
+	RSVD110_PCC3_SLOT		= 110,
+	RSVD111_PCC3_SLOT		= 111,
+	RSVD112_PCC3_SLOT		= 112,
+	RSVD113_PCC3_SLOT		= 113,
+	RSVD114_PCC3_SLOT		= 114,
+	RSVD115_PCC3_SLOT		= 115,
+	RSVD116_PCC3_SLOT		= 116,
+	RSVD117_PCC3_SLOT		= 117,
+	RSVD118_PCC3_SLOT		= 118,
+	RSVD119_PCC3_SLOT		= 119,
+	RSVD120_PCC3_SLOT		= 120,
+	RSVD121_PCC3_SLOT		= 121,
+	RSVD122_PCC3_SLOT		= 122,
+	RSVD123_PCC3_SLOT		= 123,
+	RSVD124_PCC3_SLOT		= 124,
+	RSVD125_PCC3_SLOT		= 125,
+	RSVD126_PCC3_SLOT		= 126,
+	RSVD127_PCC3_SLOT		= 127,
+};
+
+
+/* PCC registers */
+#define PCC_PR_OFFSET	31
+#define PCC_PR_MASK		(0x1 << PCC_PR_OFFSET)
+#define PCC_CGC_OFFSET	30
+#define PCC_CGC_MASK	(0x1 << PCC_CGC_OFFSET)
+#define PCC_INUSE_OFFSET	29
+#define PCC_INUSE_MASK		(0x1 << PCC_INUSE_OFFSET)
+#define PCC_PCS_OFFSET	24
+#define PCC_PCS_MASK	(0x7 << PCC_PCS_OFFSET)
+#define PCC_FRAC_OFFSET	3
+#define PCC_FRAC_MASK	(0x1 << PCC_FRAC_OFFSET)
+#define PCC_PCD_OFFSET	0
+#define PCC_PCD_MASK	(0x7 << PCC_PCD_OFFSET)
+
+
+enum pcc_clksrc_type {
+	CLKSRC_PER_PLAT = 0,
+	CLKSRC_PER_BUS = 1,
+	CLKSRC_NO_PCS = 2,
+};
+
+enum pcc_div_type {
+	PCC_HAS_DIV,
+	PCC_NO_DIV,
+};
+
+/* All peripheral clocks on A7 PCCs */
+enum pcc_clk {
+	/*PCC2 clocks*/
+	PER_CLK_DMA1 = 0,
+	PER_CLK_RGPIO2P1,
+	PER_CLK_FLEXBUS,
+	PER_CLK_SEMA42_1,
+	PER_CLK_DMA_MUX1,
+	PER_CLK_SNVS,
+	PER_CLK_CAAM,
+	PER_CLK_LPTPM4,
+	PER_CLK_LPTPM5,
+	PER_CLK_LPIT1,
+	PER_CLK_LPSPI2,
+	PER_CLK_LPSPI3,
+	PER_CLK_LPI2C4,
+	PER_CLK_LPI2C5,
+	PER_CLK_LPUART4,
+	PER_CLK_LPUART5,
+	PER_CLK_FLEXIO1,
+	PER_CLK_USB0,
+	PER_CLK_USB1,
+	PER_CLK_USB_PHY,
+	PER_CLK_USB_PL301,
+	PER_CLK_USDHC0,
+	PER_CLK_USDHC1,
+	PER_CLK_WDG1,
+	PER_CLK_WDG2,
+
+	/*PCC3 clocks*/
+	PER_CLK_LPTPM6,
+	PER_CLK_LPTPM7,
+	PER_CLK_LPI2C6,
+	PER_CLK_LPI2C7,
+	PER_CLK_LPUART6,
+	PER_CLK_LPUART7,
+	PER_CLK_VIU,
+	PER_CLK_DSI,
+	PER_CLK_LCDIF,
+	PER_CLK_MMDC,
+	PER_CLK_PCTLC,
+	PER_CLK_PCTLD,
+	PER_CLK_PCTLE,
+	PER_CLK_PCTLF,
+	PER_CLK_GPU3D,
+	PER_CLK_GPU2D,
+};
+
+
+/* This structure keeps info for each pcc slot */
+struct pcc_entry {
+	u32 pcc_base;
+	u32 pcc_slot;
+	enum pcc_clksrc_type clksrc;
+	enum pcc_div_type div;
+};
+
+int pcc_clock_enable(enum pcc_clk clk, bool enable);
+int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src);
+int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div);
+bool pcc_clock_is_enable(enum pcc_clk clk);
+int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src);
+u32 pcc_clock_get_rate(enum pcc_clk clk);
+#endif
diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h
new file mode 100644
index 0000000..531d8f3
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/scg.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_ARCH_SCG_H
+#define _ASM_ARCH_SCG_H
+
+#include <common.h>
+
+#ifdef CONFIG_CLK_DEBUG
+#define clk_debug(fmt, args...)	printf(fmt, ##args)
+#else
+#define clk_debug(fmt, args...)
+#endif
+
+#define SCG_CCR_SCS_SHIFT		(24)
+#define SCG_CCR_SCS_MASK		((0xFUL) << SCG_CCR_SCS_SHIFT)
+#define SCG_CCR_DIVCORE_SHIFT		(16)
+#define SCG_CCR_DIVCORE_MASK		((0xFUL) << SCG_CCR_DIVCORE_SHIFT)
+#define SCG_CCR_DIVPLAT_SHIFT		(12)
+#define SCG_CCR_DIVPLAT_MASK		((0xFUL) << SCG_CCR_DIVPLAT_SHIFT)
+#define SCG_CCR_DIVEXT_SHIFT		(8)
+#define SCG_CCR_DIVEXT_MASK		((0xFUL) << SCG_CCR_DIVEXT_SHIFT)
+#define SCG_CCR_DIVBUS_SHIFT		(4)
+#define SCG_CCR_DIVBUS_MASK		((0xFUL) << SCG_CCR_DIVBUS_SHIFT)
+#define SCG_CCR_DIVSLOW_SHIFT		(0)
+#define SCG_CCR_DIVSLOW_MASK		((0xFUL) << SCG_CCR_DIVSLOW_SHIFT)
+
+/* SCG DDR Clock Control Register */
+#define SCG_DDRCCR_DDRCS_SHIFT		(24)
+#define SCG_DDRCCR_DDRCS_MASK		((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT)
+
+#define SCG_DDRCCR_DDRDIV_SHIFT		(0)
+#define SCG_DDRCCR_DDRDIV_MASK		((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT)
+
+/* SCG NIC Clock Control Register */
+#define SCG_NICCCR_NICCS_SHIFT		(28)
+#define SCG_NICCCR_NICCS_MASK		((0x1UL) << SCG_NICCCR_NICCS_SHIFT)
+
+#define SCG_NICCCR_NIC0_DIV_SHIFT       (24)
+#define SCG_NICCCR_NIC0_DIV_MASK        ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT)
+
+#define SCG_NICCCR_GPU_DIV_SHIFT        (20)
+#define SCG_NICCCR_GPU_DIV_MASK         ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT)
+
+#define SCG_NICCCR_NIC1_DIV_SHIFT       (16)
+#define SCG_NICCCR_NIC1_DIV_MASK        ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT)
+
+#define SCG_NICCCR_NIC1_DIVEXT_SHIFT    (8)
+#define SCG_NICCCR_NIC1_DIVEXT_MASK   ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT)
+
+#define SCG_NICCCR_NIC1_DIVBUS_SHIFT    (4)
+#define SCG_NICCCR_NIC1_DIVBUS_MASK   ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
+
+/* SCG NIC clock status register */
+#define SCG_NICCSR_NICCS_SHIFT          (28)
+#define SCG_NICCSR_NICCS_MASK           ((0x1UL) << SCG_NICCSR_NICCS_SHIFT)
+
+#define SCG_NICCSR_NIC0DIV_SHIFT        (24)
+#define SCG_NICCSR_NIC0DIV_MASK         ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT)
+#define SCG_NICCSR_GPUDIV_SHIFT         (20)
+#define SCG_NICCSR_GPUDIV_MASK          ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT)
+#define SCG_NICCSR_NIC1DIV_SHIFT        (16)
+#define SCG_NICCSR_NIC1DIV_MASK         ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT)
+#define SCG_NICCSR_NIC1EXTDIV_SHIFT     (8)
+#define SCG_NICCSR_NIC1EXTDIV_MASK      ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT)
+#define SCG_NICCSR_NIC1BUSDIV_SHIFT     (4)
+#define SCG_NICCSR_NIC1BUSDIV_MASK      ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT)
+
+/* SCG Slow IRC Control Status Register */
+#define SCG_SIRC_CSR_SIRCVLD_SHIFT      (24)
+#define SCG_SIRC_CSR_SIRCVLD_MASK       ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT)
+
+#define SCG_SIRC_CSR_SIRCEN_SHIFT       (0)
+#define SCG_SIRC_CSR_SIRCEN_MASK        ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT)
+
+/* SCG Slow IRC Configuration Register */
+#define SCG_SIRCCFG_RANGE_SHIFT         (0)
+#define SCG_SIRCCFG_RANGE_MASK          ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
+#define SCG_SIRCCFG_RANGE_4M            ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT)
+#define SCG_SIRCCFG_RANGE_16M           ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
+
+/* SCG Slow IRC Divide Register */
+#define SCG_SIRCDIV_DIV3_SHIFT          (16)
+#define SCG_SIRCDIV_DIV3_MASK           ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT)
+
+#define SCG_SIRCDIV_DIV2_SHIFT          (8)
+#define SCG_SIRCDIV_DIV2_MASK           ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT)
+
+#define SCG_SIRCDIV_DIV1_SHIFT          (0)
+#define SCG_SIRCDIV_DIV1_MASK           ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT)
+/*
+ * FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK
+ * FIRC/SIRC DIV2 ==> xIRC_BUS_CLK
+ * FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK
+ */
+
+/* SCG Fast IRC Control Status Register */
+#define SCG_FIRC_CSR_FIRCVLD_SHIFT      (24)
+#define SCG_FIRC_CSR_FIRCVLD_MASK       ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT)
+
+#define SCG_FIRC_CSR_FIRCEN_SHIFT       (0)
+#define SCG_FIRC_CSR_FIRCEN_MASK        ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT)
+
+/* SCG Fast IRC Divide Register */
+#define SCG_FIRCDIV_DIV3_SHIFT          (16)
+#define SCG_FIRCDIV_DIV3_MASK           ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT)
+
+#define SCG_FIRCDIV_DIV2_SHIFT          (8)
+#define SCG_FIRCDIV_DIV2_MASK           ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT)
+
+#define SCG_FIRCDIV_DIV1_SHIFT          (0)
+#define SCG_FIRCDIV_DIV1_MASK           ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT)
+
+#define SCG_FIRCCFG_RANGE_SHIFT         (0)
+#define SCG_FIRCCFG_RANGE_MASK          ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT)
+
+#define SCG_FIRCCFG_RANGE_SHIFT         (0)
+#define SCG_FIRCCFG_RANGE_48M           ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT)
+
+/* SCG System OSC Control Status Register */
+#define SCG_SOSC_CSR_SOSCVLD_SHIFT      (24)
+#define SCG_SOSC_CSR_SOSCVLD_MASK       ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT)
+
+/* SCG Fast IRC Divide Register */
+#define SCG_SOSCDIV_DIV3_SHIFT          (16)
+#define SCG_SOSCDIV_DIV3_MASK           ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT)
+
+#define SCG_SOSCDIV_DIV2_SHIFT          (8)
+#define SCG_SOSCDIV_DIV2_MASK           ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT)
+
+#define SCG_SOSCDIV_DIV1_SHIFT          (0)
+#define SCG_SOSCDIV_DIV1_MASK           ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT)
+
+/* SCG RTC OSC Control Status Register */
+#define SCG_ROSC_CSR_ROSCVLD_SHIFT      (24)
+#define SCG_ROSC_CSR_ROSCVLD_MASK       ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT)
+
+#define SCG_SPLL_CSR_SPLLVLD_SHIFT      (24)
+#define SCG_SPLL_CSR_SPLLVLD_MASK       ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT)
+#define SCG_SPLL_CSR_SPLLEN_SHIFT       (0)
+#define SCG_SPLL_CSR_SPLLEN_MASK        ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT)
+#define SCG_APLL_CSR_APLLEN_SHIFT       (0)
+#define SCG_APLL_CSR_APLLEN_MASK        (0x1UL)
+#define SCG_APLL_CSR_APLLVLD_MASK       (0x01000000)
+
+#define SCG_UPLL_CSR_UPLLVLD_MASK       (0x01000000)
+
+
+#define SCG_PLL_PFD3_GATE_MASK          (0x80000000)
+#define SCG_PLL_PFD2_GATE_MASK          (0x00800000)
+#define SCG_PLL_PFD1_GATE_MASK          (0x00008000)
+#define SCG_PLL_PFD0_GATE_MASK          (0x00000080)
+#define SCG_PLL_PFD3_VALID_MASK         (0x40000000)
+#define SCG_PLL_PFD2_VALID_MASK         (0x00400000)
+#define SCG_PLL_PFD1_VALID_MASK         (0x00004000)
+#define SCG_PLL_PFD0_VALID_MASK         (0x00000040)
+
+#define SCG_PLL_PFD0_FRAC_SHIFT         (0)
+#define SCG_PLL_PFD0_FRAC_MASK          ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT)
+#define SCG_PLL_PFD1_FRAC_SHIFT         (8)
+#define SCG_PLL_PFD1_FRAC_MASK          ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT)
+#define SCG_PLL_PFD2_FRAC_SHIFT         (16)
+#define SCG_PLL_PFD2_FRAC_MASK          ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT)
+#define SCG_PLL_PFD3_FRAC_SHIFT         (24)
+#define SCG_PLL_PFD3_FRAC_MASK          ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT)
+
+#define SCG_PLL_CFG_POSTDIV2_SHIFT      (28)
+#define SCG_PLL_CFG_POSTDIV2_MASK       ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT)
+#define SCG_PLL_CFG_POSTDIV1_SHIFT      (24)
+#define SCG_PLL_CFG_POSTDIV1_MASK       ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT)
+#define SCG_PLL_CFG_MULT_SHIFT          (16)
+#define SCG1_SPLL_CFG_MULT_MASK         ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
+#define SCG_APLL_CFG_MULT_MASK          ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
+#define SCG_PLL_CFG_PFDSEL_SHIFT        (14)
+#define SCG_PLL_CFG_PFDSEL_MASK         ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT)
+#define SCG_PLL_CFG_PREDIV_SHIFT        (8)
+#define SCG_PLL_CFG_PREDIV_MASK         ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT)
+#define SCG_PLL_CFG_BYPASS_SHIFT        (2)
+/* 0: SPLL, 1: bypass */
+#define SCG_PLL_CFG_BYPASS_MASK         ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT)
+#define SCG_PLL_CFG_PLLSEL_SHIFT        (1)
+/* 0: pll, 1: pfd */
+#define SCG_PLL_CFG_PLLSEL_MASK         ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT)
+#define SCG_PLL_CFG_CLKSRC_SHIFT        (0)
+/* 0: Sys-OSC, 1: FIRC */
+#define SCG_PLL_CFG_CLKSRC_MASK         ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT)
+#define SCG0_SPLL_CFG_MULT_SHIFT        (17)
+/* 0: Multiplier = 20, 1: Multiplier = 22 */
+#define SCG0_SPLL_CFG_MULT_MASK         ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT)
+
+#define PLL_USB_EN_USB_CLKS_MASK	(0x01 << 6)
+#define PLL_USB_PWR_MASK		(0x01 << 12)
+#define PLL_USB_ENABLE_MASK		(0x01 << 13)
+#define PLL_USB_BYPASS_MASK		(0x01 << 16)
+#define PLL_USB_REG_ENABLE_MASK		(0x01 << 21)
+#define PLL_USB_DIV_SEL_MASK		(0x07 << 22)
+#define PLL_USB_LOCK_MASK		(0x01 << 31)
+
+enum scg_clk {
+	SCG_SOSC_CLK,
+	SCG_FIRC_CLK,
+	SCG_SIRC_CLK,
+	SCG_ROSC_CLK,
+	SCG_SIRC_DIV1_CLK,
+	SCG_SIRC_DIV2_CLK,
+	SCG_SIRC_DIV3_CLK,
+	SCG_FIRC_DIV1_CLK,
+	SCG_FIRC_DIV2_CLK,
+	SCG_FIRC_DIV3_CLK,
+	SCG_SOSC_DIV1_CLK,
+	SCG_SOSC_DIV2_CLK,
+	SCG_SOSC_DIV3_CLK,
+	SCG_CORE_CLK,
+	SCG_BUS_CLK,
+	SCG_SPLL_PFD0_CLK,
+	SCG_SPLL_PFD1_CLK,
+	SCG_SPLL_PFD2_CLK,
+	SCG_SPLL_PFD3_CLK,
+	SCG_DDR_CLK,
+	SCG_NIC0_CLK,
+	SCG_GPU_CLK,
+	SCG_NIC1_CLK,
+	SCG_NIC1_BUS_CLK,
+	SCG_NIC1_EXT_CLK,
+	SCG_APLL_PFD0_CLK,
+	SCG_APLL_PFD1_CLK,
+	SCG_APLL_PFD2_CLK,
+	SCG_APLL_PFD3_CLK,
+	USB_PLL_OUT,
+	MIPI_PLL_OUT
+};
+
+enum scg_sys_src {
+	SCG_SCS_SYS_OSC = 1,
+	SCG_SCS_SLOW_IRC,
+	SCG_SCS_FAST_IRC,
+	SCG_SCS_RTC_OSC,
+	SCG_SCS_AUX_PLL,
+	SCG_SCS_SYS_PLL,
+	SCG_SCS_USBPHY_PLL,
+};
+
+/* PLL supported by i.mx7ulp */
+enum pll_clocks {
+	PLL_M4_SPLL,	/* M4 SPLL */
+	PLL_M4_APLL,	/* M4 APLL*/
+	PLL_A7_SPLL,	/* A7 SPLL */
+	PLL_A7_APLL,	/* A7 APLL */
+	PLL_USB,	/* USB PLL*/
+	PLL_MIPI,	/* MIPI PLL */
+};
+
+typedef struct scg_regs {
+	u32 verid;	/* VERSION_ID */
+	u32 param;	/*  PARAMETER */
+	u32 rsvd11[2];
+
+	u32 csr;	/*  Clock Status Register */
+	u32 rccr;	/*  Run Clock Control Register */
+	u32 vccr;	/*  VLPR Clock Control Register */
+	u32 hccr;	/*  HSRUN Clock Control Register */
+	u32 clkoutcnfg;	/*  SCG CLKOUT Configuration Register */
+	u32 rsvd12[3];
+	u32 ddrccr;	/*  SCG DDR Clock Control Register */
+	u32 rsvd13[3];
+	u32 nicccr;	/*  NIC Clock Control Register */
+	u32 niccsr;	/*  NIC Clock Status Register */
+	u32 rsvd10[46];
+
+	u32 sosccsr;	/*  System OSC Control Status Register, offset 0x100 */
+	u32 soscdiv;	/*  System OSC Divide Register */
+	u32 sosccfg;	/*  System Oscillator Configuration Register */
+	u32 sosctest;	/*  System Oscillator Test Register */
+	u32 rsvd20[60];
+
+	u32 sirccsr;	/*  Slow IRC Control Status Register, offset 0x200 */
+	u32 sircdiv;	/*  Slow IRC Divide Register */
+	u32 sirccfg;	/*  Slow IRC Configuration Register */
+	u32 sirctrim;	/*  Slow IRC Trim Register */
+	u32 loptrim;	/*  Low Power Oscillator Trim Register */
+	u32 sirctest;	/*  Slow IRC Test Register */
+	u32 rsvd30[58];
+
+	u32 firccsr;	/*  Fast IRC Control Status Register, offset 0x300 */
+	u32 fircdiv;
+	u32 firccfg;
+	u32 firctcfg;	/*  Fast IRC Trim Configuration Register */
+	u32 firctriml;	/*  Fast IRC Trim Low Register */
+	u32 firctrimh;
+	u32 fircstat;	/*  Fast IRC Status Register */
+	u32 firctest;	/*  Fast IRC Test Register */
+	u32 rsvd40[56];
+
+	u32 rtccsr;	/*  RTC OSC Control Status Register, offset 0x400 */
+	u32 rsvd50[63];
+
+	u32 apllcsr; /*  Auxiliary PLL Control Status Register, offset 0x500 */
+	u32 aplldiv;	/*  Auxiliary PLL Divider Register */
+	u32 apllcfg;	/*  Auxiliary PLL Configuration Register */
+	u32 apllpfd;	/*  Auxiliary PLL PFD Register */
+	u32 apllnum;	/*  Auxiliary PLL Numerator Register */
+	u32 aplldenom;	/*  Auxiliary PLL Denominator Register */
+	u32 apllss;	/*  Auxiliary PLL Spread Spectrum Register */
+	u32 rsvd60[55];
+	u32 apllock_cnfg; /*  Auxiliary PLL LOCK Configuration Register */
+	u32 rsvd61[1];
+
+	u32 spllcsr;	/*  System PLL Control Status Register, offset 0x600 */
+	u32 splldiv;	/*  System PLL Divide Register */
+	u32 spllcfg;	/*  System PLL Configuration Register */
+	u32 spllpfd;	/*  System PLL Test Register */
+	u32 spllnum;	/*  System PLL Numerator Register */
+	u32 splldenom;	/*  System PLL Denominator Register */
+	u32 spllss;	/*  System PLL Spread Spectrum Register */
+	u32 rsvd70[55];
+	u32 spllock_cnfg;	/*  System PLL LOCK Configuration Register */
+	u32 rsvd71[1];
+
+	u32 upllcsr;	/*  USB PLL Control Status Register, offset 0x700 */
+	u32 uplldiv;	/*  USB PLL Divide Register */
+	u32 upllcfg;	/*  USB PLL Configuration Register */
+} scg_t, *scg_p;
+
+u32 scg_clk_get_rate(enum scg_clk clk);
+int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
+int scg_enable_usb_pll(bool usb_control);
+u32 decode_pll(enum pll_clocks pll);
+
+void scg_a7_rccr_init(void);
+void scg_a7_spll_init(void);
+void scg_a7_ddrclk_init(void);
+void scg_a7_apll_init(void);
+void scg_a7_firc_init(void);
+void scg_a7_nicclk_init(void);
+void scg_a7_sys_clk_sel(enum scg_sys_src clk);
+void scg_a7_info(void);
+void scg_a7_soscdiv_init(void);
+void scg_a7_init_core_clk(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
new file mode 100644
index 0000000..0e4c8ad
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _SYS_PROTO_MX7ULP_H_
+#define _SYS_PROTO_MX7ULP_H_
+
+#include <asm/mach-imx/sys_proto.h>
+
+#define BT0CFG_LPBOOT_MASK 0x1
+#define BT0CFG_DUALBOOT_MASK 0x2
+
+enum bt_mode {
+	LOW_POWER_BOOT,		/* LP_BT = 1 */
+	DUAL_BOOT,		/* LP_BT = 0, DUAL_BT = 1 */
+	SINGLE_BOOT		/* LP_BT = 0, DUAL_BT = 0 */
+};
+
+enum boot_device get_boot_device(void);
+#endif
diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h
new file mode 100644
index 0000000..ee56d10
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/clock.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX23/i.MX28 Clock
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#ifndef __CLOCK_H__
+#define __CLOCK_H__
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_AHB_CLK,
+	MXC_IPG_CLK,
+	MXC_EMI_CLK,
+	MXC_GPMI_CLK,
+	MXC_IO0_CLK,
+	MXC_IO1_CLK,
+	MXC_XTAL_CLK,
+	MXC_SSP0_CLK,
+#ifdef CONFIG_MX28
+	MXC_SSP1_CLK,
+	MXC_SSP2_CLK,
+	MXC_SSP3_CLK,
+#endif
+};
+
+enum mxs_ioclock {
+	MXC_IOCLK0 = 0,
+	MXC_IOCLK1,
+};
+
+enum mxs_sspclock {
+	MXC_SSPCLK0 = 0,
+#ifdef CONFIG_MX28
+	MXC_SSPCLK1,
+	MXC_SSPCLK2,
+	MXC_SSPCLK3,
+#endif
+};
+
+uint32_t mxc_get_clock(enum mxc_clock clk);
+
+void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
+void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
+void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
+void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq);
+
+/* Compatibility with the FEC Ethernet driver */
+#define	imx_get_fecclk()	mxc_get_clock(MXC_AHB_CLK)
+
+#endif	/* __CLOCK_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/gpio.h b/arch/arm/include/asm/arch-mxs/gpio.h
new file mode 100644
index 0000000..34fa421
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/gpio.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 GPIO
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#ifndef	__MX28_GPIO_H__
+#define	__MX28_GPIO_H__
+
+#ifdef	CONFIG_MXS_GPIO
+void mxs_gpio_init(void);
+#else
+inline void mxs_gpio_init(void) {}
+#endif
+
+#endif	/* __MX28_GPIO_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h
new file mode 100644
index 0000000..f853c48
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/imx-regs.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX23/i.MX28 Registers
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#ifndef __IMX_REGS_H__
+#define __IMX_REGS_H__
+
+#include <asm/mach-imx/regs-apbh.h>
+#include <asm/arch/regs-base.h>
+#include <asm/mach-imx/regs-bch.h>
+#include <asm/arch/regs-digctl.h>
+#include <asm/mach-imx/regs-gpmi.h>
+#include <asm/mach-imx/regs-lcdif.h>
+#include <asm/arch/regs-i2c.h>
+#include <asm/arch/regs-lradc.h>
+#include <asm/arch/regs-ocotp.h>
+#include <asm/arch/regs-pinctrl.h>
+#include <asm/arch/regs-rtc.h>
+#include <asm/arch/regs-ssp.h>
+#include <asm/arch/regs-timrot.h>
+#include <asm/arch/regs-usb.h>
+#include <asm/arch/regs-usbphy.h>
+
+#ifdef CONFIG_MX23
+#include <asm/arch/regs-clkctrl-mx23.h>
+#include <asm/arch/regs-power-mx23.h>
+#endif
+
+#ifdef CONFIG_MX28
+#include <asm/arch/regs-clkctrl-mx28.h>
+#include <asm/arch/regs-power-mx28.h>
+#endif
+
+#endif	/* __IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/iomux-mx23.h b/arch/arm/include/asm/arch-mxs/iomux-mx23.h
new file mode 100644
index 0000000..2706efa
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/iomux-mx23.h
@@ -0,0 +1,349 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __MACH_IOMUX_MX23_H__
+#define __MACH_IOMUX_MX23_H__
+
+#include <asm/arch/iomux.h>
+
+/*
+ * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux.h
+ *
+ *									BANK	PIN	MUX
+ */
+/* MUXSEL_0 */
+#define MX23_PAD_GPMI_D00__GPMI_D00		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D01__GPMI_D01		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D02__GPMI_D02		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D03__GPMI_D03		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D04__GPMI_D04		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D05__GPMI_D05		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D06__GPMI_D06		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D07__GPMI_D07		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D08__GPMI_D08		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D09__GPMI_D09		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D10__GPMI_D10		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D11__GPMI_D11		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D12__GPMI_D12		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D13__GPMI_D13		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D14__GPMI_D14		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D15__GPMI_D15		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CLE__GPMI_CLE		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_ALE__GPMI_ALE		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE2N__GPMI_CE2N		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY0__GPMI_RDY0		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY1__GPMI_RDY1		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY2__GPMI_RDY2		MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY3__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_WPN__GPMI_WPN		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_WRN__GPMI_WRN		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDN__GPMI_RDN		MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_CTS__AUART1_CTS		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_RTS__AUART1_RTS		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_RX__AUART1_RX		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_TX__AUART1_TX		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
+#define MX23_PAD_I2C_SCL__I2C_SCL		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
+#define MX23_PAD_I2C_SDA__I2C_SDA		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
+
+#define MX23_PAD_LCD_D00__LCD_D00		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D01__LCD_D01		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D02__LCD_D02		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D03__LCD_D03		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D04__LCD_D04		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D05__LCD_D05		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D06__LCD_D06		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D07__LCD_D07		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D08__LCD_D08		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D09__LCD_D09		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D10__LCD_D10		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D11__LCD_D11		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D12__LCD_D12		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D13__LCD_D13		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D14__LCD_D14		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D15__LCD_D15		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D16__LCD_D16		MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D17__LCD_D17		MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_RESET__LCD_RESET		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_RS__LCD_RS			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_WR__LCD_WR			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_CS__LCD_CS			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_DOTCK__LCD_DOTCK		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_ENABLE__LCD_ENABLE		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_HSYNC__LCD_HSYNC		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_VSYNC__LCD_VSYNC		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
+#define MX23_PAD_PWM0__PWM0			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
+#define MX23_PAD_PWM1__PWM1			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
+#define MX23_PAD_PWM2__PWM2			MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
+#define MX23_PAD_PWM3__PWM3			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
+#define MX23_PAD_PWM4__PWM4			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
+
+#define MX23_PAD_SSP1_CMD__SSP1_CMD		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DETECT__SSP1_DETECT	MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA0__SSP1_DATA0		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA1__SSP1_DATA1		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA2__SSP1_DATA2		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA3__SSP1_DATA3		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_SCK__SSP1_SCK		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
+#define MX23_PAD_ROTARYA__ROTARYA		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
+#define MX23_PAD_ROTARYB__ROTARYB		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A00__EMI_A00		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A01__EMI_A01		MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A02__EMI_A02		MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A03__EMI_A03		MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A04__EMI_A04		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A05__EMI_A05		MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A06__EMI_A06		MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A07__EMI_A07		MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A08__EMI_A08		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A09__EMI_A09		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A10__EMI_A10		MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A11__EMI_A11		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A12__EMI_A12		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_BA0__EMI_BA0		MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_BA1__EMI_BA1		MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CASN__EMI_CASN		MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CE0N__EMI_CE0N		MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CE1N__EMI_CE1N		MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE1N__GPMI_CE1N		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE0N__GPMI_CE0N		MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CKE__EMI_CKE		MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_RASN__EMI_RASN		MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_WEN__EMI_WEN		MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
+
+#define MX23_PAD_EMI_D00__EMI_D00		MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D01__EMI_D01		MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D02__EMI_D02		MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D03__EMI_D03		MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D04__EMI_D04		MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D05__EMI_D05		MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D06__EMI_D06		MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D07__EMI_D07		MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D08__EMI_D08		MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D09__EMI_D09		MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D10__EMI_D10		MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D11__EMI_D11		MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D12__EMI_D12		MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D13__EMI_D13		MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D14__EMI_D14		MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D15__EMI_D15		MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQM0__EMI_DQM0		MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQM1__EMI_DQM1		MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQS0__EMI_DQS0		MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQS1__EMI_DQS1		MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CLK__EMI_CLK		MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CLKN__EMI_CLKN		MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
+
+/* MUXSEL_1 */
+#define MX23_PAD_GPMI_D00__LCD_D8		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D01__LCD_D9		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D02__LCD_D10		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D03__LCD_D11		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D04__LCD_D12		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D05__LCD_D13		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D06__LCD_D14		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D07__LCD_D15		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D08__LCD_D18		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D09__LCD_D19		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D10__LCD_D20		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D11__LCD_D21		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D12__LCD_D22		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D13__LCD_D23		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D14__AUART2_RX		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D15__AUART2_TX		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_CLE__LCD_D16		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_ALE__LCD_D17		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_CE2N__ATA_A2		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_RTS__IR_CLK		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_RX__IR_RX		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_TX__IR_TX		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
+#define MX23_PAD_I2C_SCL__GPMI_RDY2		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
+#define MX23_PAD_I2C_SDA__GPMI_CE2N		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
+
+#define MX23_PAD_LCD_D00__ETM_DA8		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D01__ETM_DA9		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D02__ETM_DA10		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D03__ETM_DA11		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D04__ETM_DA12		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D05__ETM_DA13		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D06__ETM_DA14		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D07__ETM_DA15		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D08__ETM_DA0		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D09__ETM_DA1		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D10__ETM_DA2		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D11__ETM_DA3		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D12__ETM_DA4		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D13__ETM_DA5		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D14__ETM_DA6		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D15__ETM_DA7		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_RESET__ETM_TCTL		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_RS__ETM_TCLK		MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_DOTCK__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_ENABLE__I2C_SCL		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_HSYNC__I2C_SDA		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_VSYNC__LCD_BUSY		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
+#define MX23_PAD_PWM0__ROTARYA			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
+#define MX23_PAD_PWM1__ROTARYB			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
+#define MX23_PAD_PWM2__GPMI_RDY3		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
+#define MX23_PAD_PWM3__ETM_TCTL			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
+#define MX23_PAD_PWM4__ETM_TCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
+
+#define MX23_PAD_SSP1_DETECT__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_1)
+#define MX23_PAD_SSP1_DATA1__I2C_SCL		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_1)
+#define MX23_PAD_SSP1_DATA2__I2C_SDA		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
+#define MX23_PAD_ROTARYA__AUART2_RTS		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
+#define MX23_PAD_ROTARYB__AUART2_CTS		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_1)
+
+/* MUXSEL_2 */
+#define MX23_PAD_GPMI_D00__SSP2_DATA0		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D01__SSP2_DATA1		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D02__SSP2_DATA2		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D03__SSP2_DATA3		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D04__SSP2_DATA4		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D05__SSP2_DATA5		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D06__SSP2_DATA6		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D07__SSP2_DATA7		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D08__SSP1_DATA4		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D09__SSP1_DATA5		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D10__SSP1_DATA6		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D11__SSP1_DATA7		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D15__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_RDY0__SSP2_DETECT		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_RDY1__SSP2_CMD		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_WRN__SSP2_SCK		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_CTS__SSP1_DATA4		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_RTS__SSP1_DATA5		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_RX__SSP1_DATA6		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_TX__SSP1_DATA7		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
+#define MX23_PAD_I2C_SCL__AUART1_TX		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
+#define MX23_PAD_I2C_SDA__AUART1_RX		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
+
+#define MX23_PAD_LCD_D08__SAIF2_SDATA0		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D09__SAIF1_SDATA0		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK	MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D11__SAIF_LRCLK		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D12__SAIF2_SDATA1		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D13__SAIF2_SDATA2		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D14__SAIF1_SDATA2		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D15__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK	MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_RESET__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
+#define MX23_PAD_PWM0__DUART_RX			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
+#define MX23_PAD_PWM1__DUART_TX			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
+#define MX23_PAD_PWM3__AUART1_CTS		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
+#define MX23_PAD_PWM4__AUART1_RTS		MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
+
+#define MX23_PAD_SSP1_CMD__JTAG_TDO		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DETECT__USB_OTG_ID	MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA0__JTAG_TDI		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA1__JTAG_TCLK		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA2__JTAG_RTCK		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA3__JTAG_TMS		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_SCK__JTAG_TRST		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_2)
+#define MX23_PAD_ROTARYA__SPDIF			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_2)
+#define MX23_PAD_ROTARYB__GPMI_CE3N		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
+
+/* MUXSEL_GPIO */
+#define MX23_PAD_GPMI_D00__GPIO_0_0		MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D01__GPIO_0_1		MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D02__GPIO_0_2		MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D03__GPIO_0_3		MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D04__GPIO_0_4		MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D05__GPIO_0_5		MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D06__GPIO_0_6		MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D07__GPIO_0_7		MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D08__GPIO_0_8		MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D09__GPIO_0_9		MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D10__GPIO_0_10		MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D11__GPIO_0_11		MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D12__GPIO_0_12		MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D13__GPIO_0_13		MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D14__GPIO_0_14		MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D15__GPIO_0_15		MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CLE__GPIO_0_16		MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_ALE__GPIO_0_17		MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE2N__GPIO_0_18		MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY0__GPIO_0_19		MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY1__GPIO_0_20		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY2__GPIO_0_21		MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY3__GPIO_0_22		MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WPN__GPIO_0_23		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WRN__GPIO_0_24		MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDN__GPIO_0_25		MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_CTS__GPIO_0_26		MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RTS__GPIO_0_27		MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RX__GPIO_0_28		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_TX__GPIO_0_29		MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SCL__GPIO_0_30		MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SDA__GPIO_0_31		MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
+
+#define MX23_PAD_LCD_D00__GPIO_1_0		MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D01__GPIO_1_1		MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D02__GPIO_1_2		MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D03__GPIO_1_3		MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D04__GPIO_1_4		MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D05__GPIO_1_5		MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D06__GPIO_1_6		MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D07__GPIO_1_7		MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D08__GPIO_1_8		MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D09__GPIO_1_9		MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D10__GPIO_1_10		MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D11__GPIO_1_11		MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D12__GPIO_1_12		MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D13__GPIO_1_13		MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D14__GPIO_1_14		MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D15__GPIO_1_15		MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D16__GPIO_1_16		MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D17__GPIO_1_17		MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RESET__GPIO_1_18		MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RS__GPIO_1_19		MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_WR__GPIO_1_20		MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_CS__GPIO_1_21		MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_DOTCK__GPIO_1_22		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_ENABLE__GPIO_1_23		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_HSYNC__GPIO_1_24		MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_VSYNC__GPIO_1_25		MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM0__GPIO_1_26		MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM1__GPIO_1_27		MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM2__GPIO_1_28		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM3__GPIO_1_29		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM4__GPIO_1_30		MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+
+#define MX23_PAD_SSP1_CMD__GPIO_2_0		MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DETECT__GPIO_2_1		MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA0__GPIO_2_2		MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA1__GPIO_2_3		MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA2__GPIO_2_4		MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA3__GPIO_2_5		MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_SCK__GPIO_2_6		MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYA__GPIO_2_7		MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYB__GPIO_2_8		MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A00__GPIO_2_9		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A01__GPIO_2_10		MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A02__GPIO_2_11		MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A03__GPIO_2_12		MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A04__GPIO_2_13		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A05__GPIO_2_14		MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A06__GPIO_2_15		MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A07__GPIO_2_16		MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A08__GPIO_2_17		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A09__GPIO_2_18		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A10__GPIO_2_19		MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A11__GPIO_2_20		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A12__GPIO_2_21		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA0__GPIO_2_22		MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA1__GPIO_2_23		MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CASN__GPIO_2_24		MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE0N__GPIO_2_25		MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE1N__GPIO_2_26		MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE1N__GPIO_2_27		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE0N__GPIO_2_28		MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CKE__GPIO_2_29		MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_RASN__GPIO_2_30		MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_WEN__GPIO_2_31		MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
+
+#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/iomux-mx28.h b/arch/arm/include/asm/arch-mxs/iomux-mx28.h
new file mode 100644
index 0000000..00356f0
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/iomux-mx28.h
@@ -0,0 +1,531 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __MACH_IOMUX_MX28_H__
+#define __MACH_IOMUX_MX28_H__
+
+#include <asm/arch/iomux.h>
+
+/*
+ * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux.h
+ *
+ *									BANK	PIN	MUX
+ */
+/* MUXSEL_0 */
+#define MX28_PAD_GPMI_D00__GPMI_D0			MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D01__GPMI_D1			MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D02__GPMI_D2			MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D03__GPMI_D3			MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D04__GPMI_D4			MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D05__GPMI_D5			MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D06__GPMI_D6			MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D07__GPMI_D7			MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE0N__GPMI_CE0N			MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE1N__GPMI_CE1N			MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE2N__GPMI_CE2N			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE3N__GPMI_CE3N			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY0__GPMI_READY0			MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY1__GPMI_READY1			MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY2__GPMI_READY2			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY3__GPMI_READY3			MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDN__GPMI_RDN			MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_WRN__GPMI_WRN			MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_ALE__GPMI_ALE			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CLE__GPMI_CLE			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RESETN__GPMI_RESETN		MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
+
+#define MX28_PAD_LCD_D00__LCD_D0			MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D01__LCD_D1			MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D02__LCD_D2			MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D03__LCD_D3			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D04__LCD_D4			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D05__LCD_D5			MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D06__LCD_D6			MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D07__LCD_D7			MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D08__LCD_D8			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D09__LCD_D9			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D10__LCD_D10			MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D11__LCD_D11			MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D12__LCD_D12			MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D13__LCD_D13			MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D14__LCD_D14			MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D15__LCD_D15			MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D16__LCD_D16			MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D17__LCD_D17			MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D18__LCD_D18			MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D19__LCD_D19			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D20__LCD_D20			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D21__LCD_D21			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D22__LCD_D22			MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D23__LCD_D23			MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RD_E__LCD_RD_E			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RS__LCD_RS				MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_CS__LCD_CS				MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_VSYNC__LCD_VSYNC			MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_HSYNC__LCD_HSYNC			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_ENABLE__LCD_ENABLE			MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)
+
+#define MX28_PAD_SSP0_DATA0__SSP0_D0			MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA1__SSP0_D1			MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA2__SSP0_D2			MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA3__SSP0_D3			MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA4__SSP0_D4			MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA5__SSP0_D5			MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA6__SSP0_D6			MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA7__SSP0_D7			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_CMD__SSP0_CMD			MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT		MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_SCK__SSP0_SCK			MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_SCK__SSP1_SCK			MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_CMD__SSP1_CMD			MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_DATA0__SSP1_D0			MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_DATA3__SSP1_D3			MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SCK__SSP2_SCK			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_MOSI__SSP2_CMD			MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_MISO__SSP2_D0			MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS0__SSP2_D3			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS1__SSP2_D4			MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS2__SSP2_D5			MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_SCK__SSP3_SCK			MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_MOSI__SSP3_CMD			MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_MISO__SSP3_D0			MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_SS0__SSP3_D3			MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
+
+#define MX28_PAD_AUART0_RX__AUART0_RX			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_TX__AUART0_TX			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_CTS__AUART0_CTS			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_RTS__AUART0_RTS			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_RX__AUART1_RX			MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_TX__AUART1_TX			MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_CTS__AUART1_CTS			MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_RTS__AUART1_RTS			MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_RX__AUART2_RX			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_TX__AUART2_TX			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_CTS__AUART2_CTS			MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_RTS__AUART2_RTS			MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_RX__AUART3_RX			MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_TX__AUART3_TX			MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_CTS__AUART3_CTS			MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_RTS__AUART3_RTS			MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
+#define MX28_PAD_PWM0__PWM_0				MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
+#define MX28_PAD_PWM1__PWM_1				MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
+#define MX28_PAD_PWM2__PWM_2				MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK		MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK		MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0		MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
+#define MX28_PAD_I2C0_SCL__I2C0_SCL			MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
+#define MX28_PAD_I2C0_SDA__I2C0_SDA			MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0		MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
+#define MX28_PAD_SPDIF__SPDIF_TX			MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
+#define MX28_PAD_PWM3__PWM_3				MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
+#define MX28_PAD_PWM4__PWM_4				MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RESET__LCD_RESET			MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)
+
+#define MX28_PAD_ENET0_MDC__ENET0_MDC			MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_MDIO__ENET0_MDIO			MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN		MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD0__ENET0_RXD0			MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD1__ENET0_RXD1			MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK		MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN		MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD0__ENET0_TXD0			MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD1__ENET0_TXD1			MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD2__ENET0_RXD2			MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD3__ENET0_RXD3			MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD2__ENET0_TXD2			MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD3__ENET0_TXD3			MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK		MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_COL__ENET0_COL			MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_CRS__ENET0_CRS			MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
+#define MX28_PAD_ENET_CLK__CLKCTRL_ENET			MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
+#define MX28_PAD_JTAG_RTCK__JTAG_RTCK			MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)
+
+#define MX28_PAD_EMI_D00__EMI_DATA0			MXS_IOMUX_PAD_NAKED(5,  0, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D01__EMI_DATA1			MXS_IOMUX_PAD_NAKED(5,  1, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D02__EMI_DATA2			MXS_IOMUX_PAD_NAKED(5,  2, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D03__EMI_DATA3			MXS_IOMUX_PAD_NAKED(5,  3, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D04__EMI_DATA4			MXS_IOMUX_PAD_NAKED(5,  4, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D05__EMI_DATA5			MXS_IOMUX_PAD_NAKED(5,  5, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D06__EMI_DATA6			MXS_IOMUX_PAD_NAKED(5,  6, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D07__EMI_DATA7			MXS_IOMUX_PAD_NAKED(5,  7, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D08__EMI_DATA8			MXS_IOMUX_PAD_NAKED(5,  8, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D09__EMI_DATA9			MXS_IOMUX_PAD_NAKED(5,  9, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D10__EMI_DATA10			MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D11__EMI_DATA11			MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D12__EMI_DATA12			MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D13__EMI_DATA13			MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D14__EMI_DATA14			MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D15__EMI_DATA15			MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_ODT0__EMI_ODT0			MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQM0__EMI_DQM0			MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_ODT1__EMI_ODT1			MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQM1__EMI_DQM1			MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK	MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CLK__EMI_CLK			MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQS0__EMI_DQS0			MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQS1__EMI_DQS1			MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN		MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)
+
+#define MX28_PAD_EMI_A00__EMI_ADDR0			MXS_IOMUX_PAD_NAKED(6,  0, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A01__EMI_ADDR1			MXS_IOMUX_PAD_NAKED(6,  1, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A02__EMI_ADDR2			MXS_IOMUX_PAD_NAKED(6,  2, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A03__EMI_ADDR3			MXS_IOMUX_PAD_NAKED(6,  3, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A04__EMI_ADDR4			MXS_IOMUX_PAD_NAKED(6,  4, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A05__EMI_ADDR5			MXS_IOMUX_PAD_NAKED(6,  5, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A06__EMI_ADDR6			MXS_IOMUX_PAD_NAKED(6,  6, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A07__EMI_ADDR7			MXS_IOMUX_PAD_NAKED(6,  7, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A08__EMI_ADDR8			MXS_IOMUX_PAD_NAKED(6,  8, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A09__EMI_ADDR9			MXS_IOMUX_PAD_NAKED(6,  9, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A10__EMI_ADDR10			MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A11__EMI_ADDR11			MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A12__EMI_ADDR12			MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A13__EMI_ADDR13			MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A14__EMI_ADDR14			MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA0__EMI_BA0			MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA1__EMI_BA1			MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA2__EMI_BA2			MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CASN__EMI_CASN			MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_RASN__EMI_RASN			MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_WEN__EMI_WEN			MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CE0N__EMI_CE0N			MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CE1N__EMI_CE1N			MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CKE__EMI_CKE			MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)
+
+/* MUXSEL_1 */
+#define MX28_PAD_GPMI_D00__SSP1_D0			MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D01__SSP1_D1			MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D02__SSP1_D2			MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D03__SSP1_D3			MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D04__SSP1_D4			MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D05__SSP1_D5			MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D06__SSP1_D6			MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D07__SSP1_D7			MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE0N__SSP3_D0			MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE1N__SSP3_D3			MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE2N__CAN1_TX			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE3N__CAN1_RX			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT		MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY1__SSP1_CMD			MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY2__CAN0_TX			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY3__CAN0_RX			MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDN__SSP3_SCK			MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_WRN__SSP1_SCK			MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_ALE__SSP3_D1			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CLE__SSP3_D2			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RESETN__SSP3_CMD			MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
+
+#define MX28_PAD_LCD_D03__ETM_DA8			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D04__ETM_DA9			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D08__ETM_DA3			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D09__ETM_DA4			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT		MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN		MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT		MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN		MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RD_E__LCD_VSYNC			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RS__LCD_DOTCLK			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_CS__LCD_ENABLE			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0		MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
+
+#define MX28_PAD_SSP0_DATA4__SSP2_D0			MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA5__SSP2_D3			MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA6__SSP2_CMD			MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA7__SSP2_SCK			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_SCK__SSP2_D1			MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_CMD__SSP2_D2			MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_DATA0__SSP2_D6			MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_DATA3__SSP2_D7			MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SCK__AUART2_RX			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_MOSI__AUART2_TX			MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_MISO__AUART3_RX			MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS0__AUART3_TX			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS1__SSP2_D1			MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS2__SSP2_D2			MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_SCK__AUART4_TX			MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_MOSI__AUART4_RX			MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_MISO__AUART4_RTS			MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_SS0__AUART4_CTS			MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)
+
+#define MX28_PAD_AUART0_RX__I2C0_SCL			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_TX__I2C0_SDA			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_CTS__AUART4_RX			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_RTS__AUART4_TX			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT		MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT		MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT		MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_RTS__USB0_ID			MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_RX__SSP3_D1			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_TX__SSP3_D2			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_CTS__I2C1_SCL			MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_RTS__I2C1_SDA			MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_RX__CAN0_TX			MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_TX__CAN0_RX			MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_CTS__CAN1_TX			MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_RTS__CAN1_RX			MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
+#define MX28_PAD_PWM0__I2C1_SCL				MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
+#define MX28_PAD_PWM1__I2C1_SDA				MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
+#define MX28_PAD_PWM2__USB0_ID				MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_MCLK__PWM_3			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_LRCLK__PWM_4			MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_BITCLK__PWM_5			MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_SDATA0__PWM_6			MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
+#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA		MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
+#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB		MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF1_SDATA0__PWM_7			MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RESET__LCD_VSYNC			MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)
+
+#define MX28_PAD_ENET0_MDC__GPMI_CE4N			MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_MDIO__GPMI_CE5N			MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N			MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD0__GPMI_CE7N			MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD1__GPMI_READY4		MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER		MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TX_EN__GPMI_READY5		MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD0__GPMI_READY6		MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD1__GPMI_READY7		MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD2__ENET1_RXD0			MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD3__ENET1_RXD1			MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD2__ENET1_TXD0			MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD3__ENET1_TXD1			MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER		MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_COL__ENET1_TX_EN			MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_CRS__ENET1_RX_EN			MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)
+
+/* MUXSEL_2 */
+#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY0__USB0_ID			MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER		MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_ALE__SSP3_D4			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_CLE__SSP3_D5			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_LCD_D00__ETM_DA0			MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D01__ETM_DA1			MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D02__ETM_DA2			MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D03__ETM_DA3			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D04__ETM_DA4			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D05__ETM_DA5			MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D06__ETM_DA6			MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D07__ETM_DA7			MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D08__ETM_DA8			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D09__ETM_DA9			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D10__ETM_DA10			MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D11__ETM_DA11			MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D12__ETM_DA12			MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D13__ETM_DA13			MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D14__ETM_DA14			MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D15__ETM_DA15			MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D16__ETM_DA7			MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D17__ETM_DA6			MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D18__ETM_DA5			MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D19__ETM_DA4			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D20__ETM_DA3			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D21__ETM_DA2			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D22__ETM_DA1			MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D23__ETM_DA0			MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_RD_E__ETM_TCTL			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_WR_RWN__ETM_TCLK			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_HSYNC__ETM_TCTL			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_DOTCLK__ETM_TCLK			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
+
+#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT	MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN		MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT	MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN	MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2		MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT		MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT		MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT	MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN	MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT	MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN		MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_AUART0_RX__DUART_CTS			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_TX__DUART_RTS			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_CTS__DUART_RX			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_RTS__DUART_TX			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_RX__PWM_0			MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_TX__PWM_1			MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA		MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB		MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_RX__SSP3_D4			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_TX__SSP3_D5			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK		MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK		MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT	MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN	MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT	MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN	MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
+#define MX28_PAD_PWM0__DUART_RX				MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
+#define MX28_PAD_PWM1__DUART_TX				MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
+#define MX28_PAD_PWM2__USB1_OVERCURRENT			MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_MCLK__AUART4_CTS			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS		MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_BITCLK__AUART4_RX		MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_SDATA0__AUART4_TX		MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
+#define MX28_PAD_I2C0_SCL__DUART_RX			MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
+#define MX28_PAD_I2C0_SDA__DUART_TX			MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1		MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
+#define MX28_PAD_SPDIF__ENET1_RX_ER			MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1		MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2		MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1		MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2		MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT	MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT	MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN	MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT	MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN	MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN	MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT	MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN	MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)
+
+/* MUXSEL_GPIO */
+#define MX28_PAD_GPMI_D00__GPIO_0_0			MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D01__GPIO_0_1			MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D02__GPIO_0_2			MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D03__GPIO_0_3			MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D04__GPIO_0_4			MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D05__GPIO_0_5			MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D06__GPIO_0_6			MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D07__GPIO_0_7			MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE0N__GPIO_0_16			MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE1N__GPIO_0_17			MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE2N__GPIO_0_18			MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE3N__GPIO_0_19			MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY0__GPIO_0_20			MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY1__GPIO_0_21			MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY2__GPIO_0_22			MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY3__GPIO_0_23			MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDN__GPIO_0_24			MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_WRN__GPIO_0_25			MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_ALE__GPIO_0_26			MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CLE__GPIO_0_27			MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RESETN__GPIO_0_28			MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_LCD_D00__GPIO_1_0			MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D01__GPIO_1_1			MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D02__GPIO_1_2			MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D03__GPIO_1_3			MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D04__GPIO_1_4			MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D05__GPIO_1_5			MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D06__GPIO_1_6			MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D07__GPIO_1_7			MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D08__GPIO_1_8			MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D09__GPIO_1_9			MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D10__GPIO_1_10			MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D11__GPIO_1_11			MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D12__GPIO_1_12			MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D13__GPIO_1_13			MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D14__GPIO_1_14			MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D15__GPIO_1_15			MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D16__GPIO_1_16			MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D17__GPIO_1_17			MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D18__GPIO_1_18			MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D19__GPIO_1_19			MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D20__GPIO_1_20			MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D21__GPIO_1_21			MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D22__GPIO_1_22			MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D23__GPIO_1_23			MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RD_E__GPIO_1_24			MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_WR_RWN__GPIO_1_25			MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RS__GPIO_1_26			MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_CS__GPIO_1_27			MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_VSYNC__GPIO_1_28			MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_HSYNC__GPIO_1_29			MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_DOTCLK__GPIO_1_30			MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_ENABLE__GPIO_1_31			MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_SSP0_DATA0__GPIO_2_0			MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA1__GPIO_2_1			MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA2__GPIO_2_2			MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA3__GPIO_2_3			MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA4__GPIO_2_4			MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA5__GPIO_2_5			MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA6__GPIO_2_6			MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA7__GPIO_2_7			MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_CMD__GPIO_2_8			MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DETECT__GPIO_2_9			MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_SCK__GPIO_2_10			MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_SCK__GPIO_2_12			MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_CMD__GPIO_2_13			MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_DATA0__GPIO_2_14			MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_DATA3__GPIO_2_15			MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SCK__GPIO_2_16			MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_MOSI__GPIO_2_17			MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_MISO__GPIO_2_18			MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS0__GPIO_2_19			MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS1__GPIO_2_20			MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS2__GPIO_2_21			MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_SCK__GPIO_2_24			MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_MOSI__GPIO_2_25			MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_MISO__GPIO_2_26			MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_SS0__GPIO_2_27			MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_AUART0_RX__GPIO_3_0			MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_TX__GPIO_3_1			MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_CTS__GPIO_3_2			MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_RTS__GPIO_3_3			MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_RX__GPIO_3_4			MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_TX__GPIO_3_5			MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_CTS__GPIO_3_6			MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_RTS__GPIO_3_7			MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_RX__GPIO_3_8			MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_TX__GPIO_3_9			MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_CTS__GPIO_3_10			MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_RTS__GPIO_3_11			MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_RX__GPIO_3_12			MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_TX__GPIO_3_13			MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_CTS__GPIO_3_14			MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_RTS__GPIO_3_15			MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM0__GPIO_3_16			MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM1__GPIO_3_17			MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM2__GPIO_3_18			MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_MCLK__GPIO_3_20			MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21			MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22		MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23		MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_I2C0_SCL__GPIO_3_24			MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_I2C0_SDA__GPIO_3_25			MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26		MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SPDIF__GPIO_3_27			MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM3__GPIO_3_28			MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM4__GPIO_3_29			MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RESET__GPIO_3_30			MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_ENET0_MDC__GPIO_4_0			MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_MDIO__GPIO_4_1			MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RX_EN__GPIO_4_2			MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD0__GPIO_4_3			MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD1__GPIO_4_4			MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5			MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TX_EN__GPIO_4_6			MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD0__GPIO_4_7			MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD1__GPIO_4_8			MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD2__GPIO_4_9			MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD3__GPIO_4_10			MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD2__GPIO_4_11			MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD3__GPIO_4_12			MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13		MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_COL__GPIO_4_14			MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_CRS__GPIO_4_15			MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET_CLK__GPIO_4_16			MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_JTAG_RTCK__GPIO_4_20			MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)
+
+#endif /* __MACH_IOMUX_MX28_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h
new file mode 100644
index 0000000..a9896e1
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/iomux.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *			<armlinux@phytec.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __MACH_MXS_IOMUX_H__
+#define __MACH_MXS_IOMUX_H__
+
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
+/*
+ * IOMUX/PAD Bit field definitions
+ *
+ * PAD_BANK:		 0..2	(3)
+ * PAD_PIN:		 3..7	(5)
+ * PAD_MUXSEL:		 8..9	(2)
+ * PAD_MA:		10..11	(2)
+ * PAD_MA_VALID:	12	(1)
+ * PAD_VOL:		13	(1)
+ * PAD_VOL_VALID:	14	(1)
+ * PAD_PULL:		15	(1)
+ * PAD_PULL_VALID:	16	(1)
+ * RESERVED:		17..31	(15)
+ */
+typedef u32 iomux_cfg_t;
+
+#define MXS_PAD_BANK_SHIFT	0
+#define MXS_PAD_BANK_MASK	((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
+#define MXS_PAD_PIN_SHIFT	3
+#define MXS_PAD_PIN_MASK	((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
+#define MXS_PAD_MUXSEL_SHIFT	8
+#define MXS_PAD_MUXSEL_MASK	((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
+#define MXS_PAD_MA_SHIFT	10
+#define MXS_PAD_MA_MASK		((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
+#define MXS_PAD_MA_VALID_SHIFT	12
+#define MXS_PAD_MA_VALID_MASK	((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
+#define MXS_PAD_VOL_SHIFT	13
+#define MXS_PAD_VOL_MASK	((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
+#define MXS_PAD_VOL_VALID_SHIFT	14
+#define MXS_PAD_VOL_VALID_MASK	((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
+#define MXS_PAD_PULL_SHIFT	15
+#define MXS_PAD_PULL_MASK	((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
+#define MXS_PAD_PULL_VALID_SHIFT 16
+#define MXS_PAD_PULL_VALID_MASK	((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
+
+#define PAD_MUXSEL_0		0
+#define PAD_MUXSEL_1		1
+#define PAD_MUXSEL_2		2
+#define PAD_MUXSEL_GPIO		3
+
+#define PAD_4MA			0
+#define PAD_8MA			1
+#define PAD_12MA		2
+#define PAD_16MA		3
+
+#define PAD_1V8			0
+#if defined(CONFIG_MX28)
+#define PAD_3V3			1
+#else
+#define PAD_3V3			0
+#endif
+
+#define PAD_NOPULL		0
+#define PAD_PULLUP		1
+
+#define MXS_PAD_4MA	((PAD_4MA << MXS_PAD_MA_SHIFT) | \
+					MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_8MA	((PAD_8MA << MXS_PAD_MA_SHIFT) | \
+					MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_12MA	((PAD_12MA << MXS_PAD_MA_SHIFT) | \
+					MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_16MA	((PAD_16MA << MXS_PAD_MA_SHIFT) | \
+					MXS_PAD_MA_VALID_MASK)
+
+#define MXS_PAD_1V8	((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
+					MXS_PAD_VOL_VALID_MASK)
+#define MXS_PAD_3V3	((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
+					MXS_PAD_VOL_VALID_MASK)
+
+#define MXS_PAD_NOPULL	((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \
+					MXS_PAD_PULL_VALID_MASK)
+#define MXS_PAD_PULLUP	((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
+					MXS_PAD_PULL_VALID_MASK)
+
+/* generic pad control used in most cases */
+#define MXS_PAD_CTRL	(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
+
+#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull)		\
+		(((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) |		\
+		((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) |		\
+		((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) |	\
+		((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) |		\
+		((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) |		\
+		((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
+
+/*
+ * A pad becomes naked, when none of mA, vol or pull
+ * validity bits is set.
+ */
+#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \
+		MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0)
+
+static inline unsigned int PAD_BANK(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT;
+}
+
+static inline unsigned int PAD_PIN(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT;
+}
+
+static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT;
+}
+
+static inline unsigned int PAD_MA(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT;
+}
+
+static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT;
+}
+
+static inline unsigned int PAD_VOL(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT;
+}
+
+static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT;
+}
+
+static inline unsigned int PAD_PULL(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT;
+}
+
+static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad)
+{
+	return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT;
+}
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int mxs_iomux_setup_pad(iomux_cfg_t pad);
+
+/*
+ * configures multiple pads
+ * convenient way to call the above function with tables
+ */
+int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h
new file mode 100644
index 0000000..44d40ca
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-base.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX23/i.MX28 Peripheral Base Addresses
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2008 Embedded Alley Solutions Inc.
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __MXS_REGS_BASE_H__
+#define __MXS_REGS_BASE_H__
+
+/*
+ * Register base addresses for i.MX23
+ */
+#if defined(CONFIG_MX23)
+#define	MXS_ICOLL_BASE		0x80000000
+#define	MXS_APBH_BASE		0x80004000
+#define	MXS_ECC8_BASE		0x80008000
+#define	MXS_BCH_BASE		0x8000A000
+#define	MXS_GPMI_BASE		0x8000C000
+#define	MXS_SSP0_BASE		0x80010000
+#define	MXS_SSP1_BASE		0x80034000
+#define	MXS_ETM_BASE		0x80014000
+#define	MXS_PINCTRL_BASE	0x80018000
+#define	MXS_DIGCTL_BASE		0x8001C000
+#define	MXS_EMI_BASE		0x80020000
+#define	MXS_APBX_BASE		0x80024000
+#define	MXS_DCP_BASE		0x80028000
+#define	MXS_PXP_BASE		0x8002A000
+#define	MXS_OCOTP_BASE		0x8002C000
+#define	MXS_AXI_BASE		0x8002E000
+#define	MXS_LCDIF_BASE		0x80030000
+#define	MXS_SSP1_BASE		0x80034000
+#define	MXS_TVENC_BASE		0x80038000
+#define	MXS_CLKCTRL_BASE	0x80040000
+#define	MXS_SAIF0_BASE		0x80042000
+#define	MXS_POWER_BASE		0x80044000
+#define	MXS_SAIF1_BASE		0x80046000
+#define	MXS_AUDIOOUT_BASE	0x80048000
+#define	MXS_AUDIOIN_BASE	0x8004C000
+#define	MXS_LRADC_BASE		0x80050000
+#define	MXS_SPDIF_BASE		0x80054000
+#define	MXS_I2C0_BASE		0x80058000
+#define	MXS_RTC_BASE		0x8005C000
+#define	MXS_PWM_BASE		0x80064000
+#define	MXS_TIMROT_BASE		0x80068000
+#define	MXS_UARTAPP0_BASE	0x8006C000
+#define	MXS_UARTAPP1_BASE	0x8006E000
+#define	MXS_UARTDBG_BASE	0x80070000
+#define	MXS_USBPHY0_BASE	0x8007C000
+#define	MXS_USBCTRL0_BASE	0x80080000
+#define	MXS_DRAM_BASE		0x800E0000
+
+/*
+ * Register base addresses for i.MX28
+ */
+#elif defined(CONFIG_MX28)
+#define	MXS_ICOL_BASE		0x80000000
+#define	MXS_HSADC_BASE		0x80002000
+#define	MXS_APBH_BASE		0x80004000
+#define	MXS_PERFMON_BASE	0x80006000
+#define	MXS_BCH_BASE		0x8000A000
+#define	MXS_GPMI_BASE		0x8000C000
+#define	MXS_SSP0_BASE		0x80010000
+#define	MXS_SSP1_BASE		0x80012000
+#define	MXS_SSP2_BASE		0x80014000
+#define	MXS_SSP3_BASE		0x80016000
+#define	MXS_PINCTRL_BASE	0x80018000
+#define	MXS_DIGCTL_BASE		0x8001C000
+#define	MXS_ETM_BASE		0x80022000
+#define	MXS_APBX_BASE		0x80024000
+#define	MXS_DCP_BASE		0x80028000
+#define	MXS_PXP_BASE		0x8002A000
+#define	MXS_OCOTP_BASE		0x8002C000
+#define	MXS_AXI_AHB0_BASE	0x8002E000
+#define	MXS_LCDIF_BASE		0x80030000
+#define	MXS_CAN0_BASE		0x80032000
+#define	MXS_CAN1_BASE		0x80034000
+#define	MXS_SIMDBG_BASE		0x8003C000
+#define	MXS_SIMGPMISEL_BASE	0x8003C200
+#define	MXS_SIMSSPSEL_BASE	0x8003C300
+#define	MXS_SIMMEMSEL_BASE	0x8003C400
+#define	MXS_GPIOMON_BASE	0x8003C500
+#define	MXS_SIMENET_BASE	0x8003C700
+#define	MXS_ARMJTAG_BASE	0x8003C800
+#define	MXS_CLKCTRL_BASE	0x80040000
+#define	MXS_SAIF0_BASE		0x80042000
+#define	MXS_POWER_BASE		0x80044000
+#define	MXS_SAIF1_BASE		0x80046000
+#define	MXS_LRADC_BASE		0x80050000
+#define	MXS_SPDIF_BASE		0x80054000
+#define	MXS_RTC_BASE		0x80056000
+#define	MXS_I2C0_BASE		0x80058000
+#define	MXS_I2C1_BASE		0x8005A000
+#define	MXS_PWM_BASE		0x80064000
+#define	MXS_TIMROT_BASE		0x80068000
+#define	MXS_UARTAPP0_BASE	0x8006A000
+#define	MXS_UARTAPP1_BASE	0x8006C000
+#define	MXS_UARTAPP2_BASE	0x8006E000
+#define	MXS_UARTAPP3_BASE	0x80070000
+#define	MXS_UARTAPP4_BASE	0x80072000
+#define	MXS_UARTDBG_BASE	0x80074000
+#define	MXS_USBPHY0_BASE	0x8007C000
+#define	MXS_USBPHY1_BASE	0x8007E000
+#define	MXS_USBCTRL0_BASE	0x80080000
+#define	MXS_USBCTRL1_BASE	0x80090000
+#define	MXS_DFLPT_BASE		0x800C0000
+#define	MXS_DRAM_BASE		0x800E0000
+#define	MXS_ENET0_BASE		0x800F0000
+#define	MXS_ENET1_BASE		0x800F4000
+#else
+#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28
+#endif
+
+#endif /* __MXS_REGS_BASE_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
new file mode 100644
index 0000000..6e9ffeb
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX23 CLKCTRL Register Definitions
+ *
+ * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __MX23_REGS_CLKCTRL_H__
+#define __MX23_REGS_CLKCTRL_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_clkctrl_regs {
+	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
+	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
+	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
+	mxs_reg_32(hw_clkctrl_cpu)		/* 0x20 */
+	mxs_reg_32(hw_clkctrl_hbus)		/* 0x30 */
+	mxs_reg_32(hw_clkctrl_xbus)		/* 0x40 */
+	mxs_reg_32(hw_clkctrl_xtal)		/* 0x50 */
+	mxs_reg_32(hw_clkctrl_pix)		/* 0x60 */
+	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x70 */
+	mxs_reg_32(hw_clkctrl_gpmi)		/* 0x80 */
+	mxs_reg_32(hw_clkctrl_spdif)		/* 0x90 */
+	mxs_reg_32(hw_clkctrl_emi)		/* 0xa0 */
+
+	uint32_t	reserved1[4];
+
+	mxs_reg_32(hw_clkctrl_saif0)		/* 0xc0 */
+	mxs_reg_32(hw_clkctrl_tv)		/* 0xd0 */
+	mxs_reg_32(hw_clkctrl_etm)		/* 0xe0 */
+	mxs_reg_8(hw_clkctrl_frac0)		/* 0xf0 */
+	mxs_reg_8(hw_clkctrl_frac1)		/* 0x100 */
+	mxs_reg_32(hw_clkctrl_clkseq)		/* 0x110 */
+	mxs_reg_32(hw_clkctrl_reset)		/* 0x120 */
+	mxs_reg_32(hw_clkctrl_status)		/* 0x130 */
+	mxs_reg_32(hw_clkctrl_version)		/* 0x140 */
+};
+#endif
+
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET	28
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_MASK		(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET		24
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_MASK		(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET	20
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER		(0x1 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_EN_USB_CLKS		(1 << 18)
+#define	CLKCTRL_PLL0CTRL0_POWER			(1 << 16)
+
+#define	CLKCTRL_PLL0CTRL1_LOCK			(1 << 31)
+#define	CLKCTRL_PLL0CTRL1_FORCE_LOCK		(1 << 30)
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK	0xffff
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET	0
+
+#define	CLKCTRL_CPU_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_CPU_BUSY_REF_CPU		(1 << 28)
+#define	CLKCTRL_CPU_DIV_XTAL_FRAC_EN		(1 << 26)
+#define	CLKCTRL_CPU_DIV_XTAL_MASK		(0x3ff << 16)
+#define	CLKCTRL_CPU_DIV_XTAL_OFFSET		16
+#define	CLKCTRL_CPU_INTERRUPT_WAIT		(1 << 12)
+#define	CLKCTRL_CPU_DIV_CPU_FRAC_EN		(1 << 10)
+#define	CLKCTRL_CPU_DIV_CPU_MASK		0x3f
+#define	CLKCTRL_CPU_DIV_CPU_OFFSET		0
+
+#define	CLKCTRL_HBUS_BUSY			(1 << 29)
+#define	CLKCTRL_HBUS_DCP_AS_ENABLE		(1 << 28)
+#define	CLKCTRL_HBUS_PXP_AS_ENABLE		(1 << 27)
+#define	CLKCTRL_HBUS_APBHDMA_AS_ENABLE		(1 << 26)
+#define	CLKCTRL_HBUS_APBXDMA_AS_ENABLE		(1 << 25)
+#define	CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	(1 << 24)
+#define	CLKCTRL_HBUS_TRAFFIC_AS_ENABLE		(1 << 23)
+#define	CLKCTRL_HBUS_CPU_DATA_AS_ENABLE		(1 << 22)
+#define	CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	(1 << 21)
+#define	CLKCTRL_HBUS_AUTO_SLOW_MODE		(1 << 20)
+#define	CLKCTRL_HBUS_SLOW_DIV_MASK		(0x7 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_OFFSET		16
+#define	CLKCTRL_HBUS_SLOW_DIV_BY1		(0x0 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY2		(0x1 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY4		(0x2 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY8		(0x3 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY16		(0x4 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY32		(0x5 << 16)
+#define	CLKCTRL_HBUS_DIV_FRAC_EN		(1 << 5)
+#define	CLKCTRL_HBUS_DIV_MASK			0x1f
+#define	CLKCTRL_HBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XBUS_BUSY			(1 << 31)
+#define	CLKCTRL_XBUS_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_XBUS_DIV_MASK			0x3ff
+#define	CLKCTRL_XBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XTAL_UART_CLK_GATE		(1 << 31)
+#define	CLKCTRL_XTAL_FILT_CLK24M_GATE		(1 << 30)
+#define	CLKCTRL_XTAL_PWM_CLK24M_GATE		(1 << 29)
+#define	CLKCTRL_XTAL_DRI_CLK24M_GATE		(1 << 28)
+#define	CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE		(1 << 27)
+#define	CLKCTRL_XTAL_TIMROT_CLK32K_GATE		(1 << 26)
+#define	CLKCTRL_XTAL_DIV_UART_MASK		0x3
+#define	CLKCTRL_XTAL_DIV_UART_OFFSET		0
+
+#define	CLKCTRL_PIX_CLKGATE			(1 << 31)
+#define	CLKCTRL_PIX_BUSY			(1 << 29)
+#define	CLKCTRL_PIX_DIV_FRAC_EN			(1 << 12)
+#define	CLKCTRL_PIX_DIV_MASK			0xfff
+#define	CLKCTRL_PIX_DIV_OFFSET			0
+
+#define	CLKCTRL_SSP_CLKGATE			(1 << 31)
+#define	CLKCTRL_SSP_BUSY			(1 << 29)
+#define	CLKCTRL_SSP_DIV_FRAC_EN			(1 << 9)
+#define	CLKCTRL_SSP_DIV_MASK			0x1ff
+#define	CLKCTRL_SSP_DIV_OFFSET			0
+
+#define	CLKCTRL_GPMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_GPMI_BUSY			(1 << 29)
+#define	CLKCTRL_GPMI_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_GPMI_DIV_MASK			0x3ff
+#define	CLKCTRL_GPMI_DIV_OFFSET			0
+
+#define	CLKCTRL_SPDIF_CLKGATE			(1 << 31)
+
+#define	CLKCTRL_EMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_EMI_SYNC_MODE_EN		(1 << 30)
+#define	CLKCTRL_EMI_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_EMI_BUSY_REF_EMI		(1 << 28)
+#define	CLKCTRL_EMI_BUSY_REF_CPU		(1 << 27)
+#define	CLKCTRL_EMI_BUSY_SYNC_MODE		(1 << 26)
+#define	CLKCTRL_EMI_BUSY_DCC_RESYNC		(1 << 17)
+#define	CLKCTRL_EMI_DCC_RESYNC_ENABLE		(1 << 16)
+#define	CLKCTRL_EMI_DIV_XTAL_MASK		(0xf << 8)
+#define	CLKCTRL_EMI_DIV_XTAL_OFFSET		8
+#define	CLKCTRL_EMI_DIV_EMI_MASK		0x3f
+#define	CLKCTRL_EMI_DIV_EMI_OFFSET		0
+
+#define	CLKCTRL_IR_CLKGATE			(1 << 31)
+#define	CLKCTRL_IR_AUTO_DIV			(1 << 29)
+#define	CLKCTRL_IR_IR_BUSY			(1 << 28)
+#define	CLKCTRL_IR_IROV_BUSY			(1 << 27)
+#define	CLKCTRL_IR_IROV_DIV_MASK		(0x1ff << 16)
+#define	CLKCTRL_IR_IROV_DIV_OFFSET		16
+#define	CLKCTRL_IR_IR_DIV_MASK			0x3ff
+#define	CLKCTRL_IR_IR_DIV_OFFSET		0
+
+#define	CLKCTRL_SAIF0_CLKGATE			(1 << 31)
+#define	CLKCTRL_SAIF0_BUSY			(1 << 29)
+#define	CLKCTRL_SAIF0_DIV_FRAC_EN		(1 << 16)
+#define	CLKCTRL_SAIF0_DIV_MASK			0xffff
+#define	CLKCTRL_SAIF0_DIV_OFFSET		0
+
+#define	CLKCTRL_TV_CLK_TV108M_GATE		(1 << 31)
+#define	CLKCTRL_TV_CLK_TV_GATE			(1 << 30)
+
+#define	CLKCTRL_ETM_CLKGATE			(1 << 31)
+#define	CLKCTRL_ETM_BUSY			(1 << 29)
+#define	CLKCTRL_ETM_DIV_FRAC_EN			(1 << 6)
+#define	CLKCTRL_ETM_DIV_MASK			0x3f
+#define	CLKCTRL_ETM_DIV_OFFSET			0
+
+#define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
+#define	CLKCTRL_FRAC_STABLE			(1 << 6)
+#define	CLKCTRL_FRAC_FRAC_MASK			0x3f
+#define	CLKCTRL_FRAC_FRAC_OFFSET		0
+#define	CLKCTRL_FRAC0_CPU			0
+#define	CLKCTRL_FRAC0_EMI			1
+#define	CLKCTRL_FRAC0_PIX			2
+#define	CLKCTRL_FRAC0_IO0			3
+#define	CLKCTRL_FRAC1_VID			3
+
+#define	CLKCTRL_CLKSEQ_BYPASS_ETM		(1 << 8)
+#define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 7)
+#define	CLKCTRL_CLKSEQ_BYPASS_EMI		(1 << 6)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP0		(1 << 5)
+#define	CLKCTRL_CLKSEQ_BYPASS_GPMI		(1 << 4)
+#define	CLKCTRL_CLKSEQ_BYPASS_IR		(1 << 3)
+#define	CLKCTRL_CLKSEQ_BYPASS_PIX		(1 << 1)
+#define	CLKCTRL_CLKSEQ_BYPASS_SAIF		(1 << 0)
+
+#define	CLKCTRL_RESET_CHIP			(1 << 1)
+#define	CLKCTRL_RESET_DIG			(1 << 0)
+
+#define	CLKCTRL_STATUS_CPU_LIMIT_MASK		(0x3 << 30)
+#define	CLKCTRL_STATUS_CPU_LIMIT_OFFSET		30
+
+#define	CLKCTRL_VERSION_MAJOR_MASK		(0xff << 24)
+#define	CLKCTRL_VERSION_MAJOR_OFFSET		24
+#define	CLKCTRL_VERSION_MINOR_MASK		(0xff << 16)
+#define	CLKCTRL_VERSION_MINOR_OFFSET		16
+#define	CLKCTRL_VERSION_STEP_MASK		0xffff
+#define	CLKCTRL_VERSION_STEP_OFFSET		0
+
+#endif /* __MX23_REGS_CLKCTRL_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
new file mode 100644
index 0000000..01e0a7a
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
@@ -0,0 +1,282 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 CLKCTRL Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __MX28_REGS_CLKCTRL_H__
+#define __MX28_REGS_CLKCTRL_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_clkctrl_regs {
+	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
+	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
+	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
+	mxs_reg_32(hw_clkctrl_pll1ctrl0)	/* 0x20 */
+	uint32_t	hw_clkctrl_pll1ctrl1;	/* 0x30 */
+	uint32_t	reserved_pll1ctrl1[3];	/* 0x34-0x3c */
+	mxs_reg_32(hw_clkctrl_pll2ctrl0)	/* 0x40 */
+	mxs_reg_32(hw_clkctrl_cpu)		/* 0x50 */
+	mxs_reg_32(hw_clkctrl_hbus)		/* 0x60 */
+	mxs_reg_32(hw_clkctrl_xbus)		/* 0x70 */
+	mxs_reg_32(hw_clkctrl_xtal)		/* 0x80 */
+	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x90 */
+	mxs_reg_32(hw_clkctrl_ssp1)		/* 0xa0 */
+	mxs_reg_32(hw_clkctrl_ssp2)		/* 0xb0 */
+	mxs_reg_32(hw_clkctrl_ssp3)		/* 0xc0 */
+	mxs_reg_32(hw_clkctrl_gpmi)		/* 0xd0 */
+	mxs_reg_32(hw_clkctrl_spdif)		/* 0xe0 */
+	mxs_reg_32(hw_clkctrl_emi)		/* 0xf0 */
+	mxs_reg_32(hw_clkctrl_saif0)		/* 0x100 */
+	mxs_reg_32(hw_clkctrl_saif1)		/* 0x110 */
+	mxs_reg_32(hw_clkctrl_lcdif)		/* 0x120 */
+	mxs_reg_32(hw_clkctrl_etm)		/* 0x130 */
+	mxs_reg_32(hw_clkctrl_enet)		/* 0x140 */
+	mxs_reg_32(hw_clkctrl_hsadc)		/* 0x150 */
+	mxs_reg_32(hw_clkctrl_flexcan)		/* 0x160 */
+
+	uint32_t	reserved[16];
+
+	mxs_reg_8(hw_clkctrl_frac0)		/* 0x1b0 */
+	mxs_reg_8(hw_clkctrl_frac1)		/* 0x1c0 */
+	mxs_reg_32(hw_clkctrl_clkseq)		/* 0x1d0 */
+	mxs_reg_32(hw_clkctrl_reset)		/* 0x1e0 */
+	mxs_reg_32(hw_clkctrl_status)		/* 0x1f0 */
+	mxs_reg_32(hw_clkctrl_version)		/* 0x200 */
+};
+#endif
+
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET	28
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_MASK		(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET		24
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
+#define	CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_MASK		(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET	20
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER		(0x1 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
+#define	CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
+#define	CLKCTRL_PLL0CTRL0_EN_USB_CLKS		(1 << 18)
+#define	CLKCTRL_PLL0CTRL0_POWER			(1 << 17)
+
+#define	CLKCTRL_PLL0CTRL1_LOCK			(1 << 31)
+#define	CLKCTRL_PLL0CTRL1_FORCE_LOCK		(1 << 30)
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK	0xffff
+#define	CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET	0
+
+#define	CLKCTRL_PLL1CTRL0_CLKGATEEMI		(1 << 31)
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_MASK		(0x3 << 28)
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET	28
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT	(0x0 << 28)
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2	(0x1 << 28)
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05	(0x2 << 28)
+#define	CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED	(0x3 << 28)
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_MASK		(0x3 << 24)
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET		24
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT	(0x0 << 24)
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2	(0x1 << 24)
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05	(0x2 << 24)
+#define	CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED	(0x3 << 24)
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_MASK		(0x3 << 20)
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET	20
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT	(0x0 << 20)
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER		(0x1 << 20)
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST	(0x2 << 20)
+#define	CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED	(0x3 << 20)
+#define	CLKCTRL_PLL1CTRL0_EN_USB_CLKS		(1 << 18)
+#define	CLKCTRL_PLL1CTRL0_POWER			(1 << 17)
+
+#define	CLKCTRL_PLL1CTRL1_LOCK			(1 << 31)
+#define	CLKCTRL_PLL1CTRL1_FORCE_LOCK		(1 << 30)
+#define	CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK	0xffff
+#define	CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET	0
+
+#define	CLKCTRL_PLL2CTRL0_CLKGATE		(1 << 31)
+#define	CLKCTRL_PLL2CTRL0_LFR_SEL_MASK		(0x3 << 28)
+#define	CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET	28
+#define	CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B	(1 << 26)
+#define	CLKCTRL_PLL2CTRL0_CP_SEL_MASK		(0x3 << 24)
+#define	CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET		24
+#define	CLKCTRL_PLL2CTRL0_POWER			(1 << 23)
+
+#define	CLKCTRL_CPU_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_CPU_BUSY_REF_CPU		(1 << 28)
+#define	CLKCTRL_CPU_DIV_XTAL_FRAC_EN		(1 << 26)
+#define	CLKCTRL_CPU_DIV_XTAL_MASK		(0x3ff << 16)
+#define	CLKCTRL_CPU_DIV_XTAL_OFFSET		16
+#define	CLKCTRL_CPU_INTERRUPT_WAIT		(1 << 12)
+#define	CLKCTRL_CPU_DIV_CPU_FRAC_EN		(1 << 10)
+#define	CLKCTRL_CPU_DIV_CPU_MASK		0x3f
+#define	CLKCTRL_CPU_DIV_CPU_OFFSET		0
+
+#define	CLKCTRL_HBUS_ASM_BUSY			(1 << 31)
+#define	CLKCTRL_HBUS_DCP_AS_ENABLE		(1 << 30)
+#define	CLKCTRL_HBUS_PXP_AS_ENABLE		(1 << 29)
+#define	CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE	(1 << 27)
+#define	CLKCTRL_HBUS_APBHDMA_AS_ENABLE		(1 << 26)
+#define	CLKCTRL_HBUS_APBXDMA_AS_ENABLE		(1 << 25)
+#define	CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE	(1 << 24)
+#define	CLKCTRL_HBUS_TRAFFIC_AS_ENABLE		(1 << 23)
+#define	CLKCTRL_HBUS_CPU_DATA_AS_ENABLE		(1 << 22)
+#define	CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE	(1 << 21)
+#define	CLKCTRL_HBUS_ASM_ENABLE			(1 << 20)
+#define	CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE	(1 << 19)
+#define	CLKCTRL_HBUS_SLOW_DIV_MASK		(0x7 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_OFFSET		16
+#define	CLKCTRL_HBUS_SLOW_DIV_BY1		(0x0 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY2		(0x1 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY4		(0x2 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY8		(0x3 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY16		(0x4 << 16)
+#define	CLKCTRL_HBUS_SLOW_DIV_BY32		(0x5 << 16)
+#define	CLKCTRL_HBUS_DIV_FRAC_EN		(1 << 5)
+#define	CLKCTRL_HBUS_DIV_MASK			0x1f
+#define	CLKCTRL_HBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XBUS_BUSY			(1 << 31)
+#define	CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE	(1 << 11)
+#define	CLKCTRL_XBUS_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_XBUS_DIV_MASK			0x3ff
+#define	CLKCTRL_XBUS_DIV_OFFSET			0
+
+#define	CLKCTRL_XTAL_UART_CLK_GATE		(1 << 31)
+#define	CLKCTRL_XTAL_PWM_CLK24M_GATE		(1 << 29)
+#define	CLKCTRL_XTAL_TIMROT_CLK32K_GATE		(1 << 26)
+#define	CLKCTRL_XTAL_DIV_UART_MASK		0x3
+#define	CLKCTRL_XTAL_DIV_UART_OFFSET		0
+
+#define	CLKCTRL_SSP_CLKGATE			(1 << 31)
+#define	CLKCTRL_SSP_BUSY			(1 << 29)
+#define	CLKCTRL_SSP_DIV_FRAC_EN			(1 << 9)
+#define	CLKCTRL_SSP_DIV_MASK			0x1ff
+#define	CLKCTRL_SSP_DIV_OFFSET			0
+
+#define	CLKCTRL_GPMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_GPMI_BUSY			(1 << 29)
+#define	CLKCTRL_GPMI_DIV_FRAC_EN		(1 << 10)
+#define	CLKCTRL_GPMI_DIV_MASK			0x3ff
+#define	CLKCTRL_GPMI_DIV_OFFSET			0
+
+#define	CLKCTRL_SPDIF_CLKGATE			(1 << 31)
+
+#define	CLKCTRL_EMI_CLKGATE			(1 << 31)
+#define	CLKCTRL_EMI_SYNC_MODE_EN		(1 << 30)
+#define	CLKCTRL_EMI_BUSY_REF_XTAL		(1 << 29)
+#define	CLKCTRL_EMI_BUSY_REF_EMI		(1 << 28)
+#define	CLKCTRL_EMI_BUSY_REF_CPU		(1 << 27)
+#define	CLKCTRL_EMI_BUSY_SYNC_MODE		(1 << 26)
+#define	CLKCTRL_EMI_BUSY_DCC_RESYNC		(1 << 17)
+#define	CLKCTRL_EMI_DCC_RESYNC_ENABLE		(1 << 16)
+#define	CLKCTRL_EMI_DIV_XTAL_MASK		(0xf << 8)
+#define	CLKCTRL_EMI_DIV_XTAL_OFFSET		8
+#define	CLKCTRL_EMI_DIV_EMI_MASK		0x3f
+#define	CLKCTRL_EMI_DIV_EMI_OFFSET		0
+
+#define	CLKCTRL_SAIF0_CLKGATE			(1 << 31)
+#define	CLKCTRL_SAIF0_BUSY			(1 << 29)
+#define	CLKCTRL_SAIF0_DIV_FRAC_EN		(1 << 16)
+#define	CLKCTRL_SAIF0_DIV_MASK			0xffff
+#define	CLKCTRL_SAIF0_DIV_OFFSET		0
+
+#define	CLKCTRL_SAIF1_CLKGATE			(1 << 31)
+#define	CLKCTRL_SAIF1_BUSY			(1 << 29)
+#define	CLKCTRL_SAIF1_DIV_FRAC_EN		(1 << 16)
+#define	CLKCTRL_SAIF1_DIV_MASK			0xffff
+#define	CLKCTRL_SAIF1_DIV_OFFSET		0
+
+#define	CLKCTRL_DIS_LCDIF_CLKGATE		(1 << 31)
+#define	CLKCTRL_DIS_LCDIF_BUSY			(1 << 29)
+#define	CLKCTRL_DIS_LCDIF_DIV_FRAC_EN		(1 << 13)
+#define	CLKCTRL_DIS_LCDIF_DIV_MASK		0x1fff
+#define	CLKCTRL_DIS_LCDIF_DIV_OFFSET		0
+
+#define	CLKCTRL_ETM_CLKGATE			(1 << 31)
+#define	CLKCTRL_ETM_BUSY			(1 << 29)
+#define	CLKCTRL_ETM_DIV_FRAC_EN			(1 << 7)
+#define	CLKCTRL_ETM_DIV_MASK			0x7f
+#define	CLKCTRL_ETM_DIV_OFFSET			0
+
+#define	CLKCTRL_ENET_SLEEP			(1 << 31)
+#define	CLKCTRL_ENET_DISABLE			(1 << 30)
+#define	CLKCTRL_ENET_STATUS			(1 << 29)
+#define	CLKCTRL_ENET_BUSY_TIME			(1 << 27)
+#define	CLKCTRL_ENET_DIV_TIME_MASK		(0x3f << 21)
+#define	CLKCTRL_ENET_DIV_TIME_OFFSET		21
+#define	CLKCTRL_ENET_TIME_SEL_MASK		(0x3 << 19)
+#define	CLKCTRL_ENET_TIME_SEL_OFFSET		19
+#define	CLKCTRL_ENET_TIME_SEL_XTAL		(0x0 << 19)
+#define	CLKCTRL_ENET_TIME_SEL_PLL		(0x1 << 19)
+#define	CLKCTRL_ENET_TIME_SEL_RMII_CLK		(0x2 << 19)
+#define	CLKCTRL_ENET_TIME_SEL_UNDEFINED		(0x3 << 19)
+#define	CLKCTRL_ENET_CLK_OUT_EN			(1 << 18)
+#define	CLKCTRL_ENET_RESET_BY_SW_CHIP		(1 << 17)
+#define	CLKCTRL_ENET_RESET_BY_SW		(1 << 16)
+
+#define	CLKCTRL_HSADC_RESETB			(1 << 30)
+#define	CLKCTRL_HSADC_FREQDIV_MASK		(0x3 << 28)
+#define	CLKCTRL_HSADC_FREQDIV_OFFSET		28
+
+#define	CLKCTRL_FLEXCAN_STOP_CAN0		(1 << 30)
+#define	CLKCTRL_FLEXCAN_CAN0_STATUS		(1 << 29)
+#define	CLKCTRL_FLEXCAN_STOP_CAN1		(1 << 28)
+#define	CLKCTRL_FLEXCAN_CAN1_STATUS		(1 << 27)
+
+#define	CLKCTRL_FRAC_CLKGATE			(1 << 7)
+#define	CLKCTRL_FRAC_STABLE			(1 << 6)
+#define	CLKCTRL_FRAC_FRAC_MASK			0x3f
+#define	CLKCTRL_FRAC_FRAC_OFFSET		0
+#define	CLKCTRL_FRAC0_CPU			0
+#define	CLKCTRL_FRAC0_EMI			1
+#define	CLKCTRL_FRAC0_IO1			2
+#define	CLKCTRL_FRAC0_IO0			3
+#define	CLKCTRL_FRAC1_PIX			0
+#define	CLKCTRL_FRAC1_HSADC			1
+#define	CLKCTRL_FRAC1_GPMI			2
+
+#define	CLKCTRL_CLKSEQ_BYPASS_CPU		(1 << 18)
+#define	CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF		(1 << 14)
+#define	CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS	(0x1 << 14)
+#define	CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD	(0x0 << 14)
+#define	CLKCTRL_CLKSEQ_BYPASS_ETM		(1 << 8)
+#define	CLKCTRL_CLKSEQ_BYPASS_EMI		(1 << 7)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP3		(1 << 6)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP2		(1 << 5)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP1		(1 << 4)
+#define	CLKCTRL_CLKSEQ_BYPASS_SSP0		(1 << 3)
+#define	CLKCTRL_CLKSEQ_BYPASS_GPMI		(1 << 2)
+#define	CLKCTRL_CLKSEQ_BYPASS_SAIF1		(1 << 1)
+#define	CLKCTRL_CLKSEQ_BYPASS_SAIF0		(1 << 0)
+
+#define	CLKCTRL_RESET_WDOG_POR_DISABLE		(1 << 5)
+#define	CLKCTRL_RESET_EXTERNAL_RESET_ENABLE	(1 << 4)
+#define	CLKCTRL_RESET_THERMAL_RESET_ENABLE	(1 << 3)
+#define	CLKCTRL_RESET_THERMAL_RESET_DEFAULT	(1 << 2)
+#define	CLKCTRL_RESET_CHIP			(1 << 1)
+#define	CLKCTRL_RESET_DIG			(1 << 0)
+
+#define	CLKCTRL_STATUS_CPU_LIMIT_MASK		(0x3 << 30)
+#define	CLKCTRL_STATUS_CPU_LIMIT_OFFSET		30
+
+#define	CLKCTRL_VERSION_MAJOR_MASK		(0xff << 24)
+#define	CLKCTRL_VERSION_MAJOR_OFFSET		24
+#define	CLKCTRL_VERSION_MINOR_MASK		(0xff << 16)
+#define	CLKCTRL_VERSION_MINOR_OFFSET		16
+#define	CLKCTRL_VERSION_STEP_MASK		0xffff
+#define	CLKCTRL_VERSION_STEP_OFFSET		0
+
+#endif /* __MX28_REGS_CLKCTRL_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-digctl.h b/arch/arm/include/asm/arch-mxs/regs-digctl.h
new file mode 100644
index 0000000..219f58b
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-digctl.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 DIGCTL Register Definitions
+ *
+ * Copyright (C) 2012 Robert Delien <robert@delien.nl>
+ */
+
+#ifndef __MX28_REGS_DIGCTL_H__
+#define __MX28_REGS_DIGCTL_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_digctl_regs {
+	mxs_reg_32(hw_digctl_ctrl)				/* 0x000 */
+	mxs_reg_32(hw_digctl_status)				/* 0x010 */
+	mxs_reg_32(hw_digctl_hclkcount)			/* 0x020 */
+	mxs_reg_32(hw_digctl_ramctrl)				/* 0x030 */
+	mxs_reg_32(hw_digctl_emi_status)			/* 0x040 */
+	mxs_reg_32(hw_digctl_read_margin)			/* 0x050 */
+	uint32_t	hw_digctl_writeonce;			/* 0x060 */
+	uint32_t	reserved_writeonce[3];
+	mxs_reg_32(hw_digctl_bist_ctl)				/* 0x070 */
+	mxs_reg_32(hw_digctl_bist_status)			/* 0x080 */
+	uint32_t	hw_digctl_entropy;			/* 0x090 */
+	uint32_t	reserved_entropy[3];
+	uint32_t	hw_digctl_entropy_latched;		/* 0x0a0 */
+	uint32_t	reserved_entropy_latched[3];
+
+	uint32_t	reserved1[4];
+
+	mxs_reg_32(hw_digctl_microseconds)			/* 0x0c0 */
+	uint32_t	hw_digctl_dbgrd;			/* 0x0d0 */
+	uint32_t	reserved_hw_digctl_dbgrd[3];
+	uint32_t	hw_digctl_dbg;				/* 0x0e0 */
+	uint32_t	reserved_hw_digctl_dbg[3];
+
+	uint32_t	reserved2[4];
+
+	mxs_reg_32(hw_digctl_usb_loopback)			/* 0x100 */
+	mxs_reg_32(hw_digctl_ocram_status0)			/* 0x110 */
+	mxs_reg_32(hw_digctl_ocram_status1)			/* 0x120 */
+	mxs_reg_32(hw_digctl_ocram_status2)			/* 0x130 */
+	mxs_reg_32(hw_digctl_ocram_status3)			/* 0x140 */
+	mxs_reg_32(hw_digctl_ocram_status4)			/* 0x150 */
+	mxs_reg_32(hw_digctl_ocram_status5)			/* 0x160 */
+	mxs_reg_32(hw_digctl_ocram_status6)			/* 0x170 */
+	mxs_reg_32(hw_digctl_ocram_status7)			/* 0x180 */
+	mxs_reg_32(hw_digctl_ocram_status8)			/* 0x190 */
+	mxs_reg_32(hw_digctl_ocram_status9)			/* 0x1a0 */
+	mxs_reg_32(hw_digctl_ocram_status10)			/* 0x1b0 */
+	mxs_reg_32(hw_digctl_ocram_status11)			/* 0x1c0 */
+	mxs_reg_32(hw_digctl_ocram_status12)			/* 0x1d0 */
+	mxs_reg_32(hw_digctl_ocram_status13)			/* 0x1e0 */
+
+	uint32_t	reserved3[36];
+
+	uint32_t	hw_digctl_scratch0;			/* 0x280 */
+	uint32_t	reserved_hw_digctl_scratch0[3];
+	uint32_t	hw_digctl_scratch1;			/* 0x290 */
+	uint32_t	reserved_hw_digctl_scratch1[3];
+	uint32_t	hw_digctl_armcache;			/* 0x2a0 */
+	uint32_t	reserved_hw_digctl_armcache[3];
+	mxs_reg_32(hw_digctl_debug_trap)			/* 0x2b0 */
+	uint32_t	hw_digctl_debug_trap_l0_addr_low;	/* 0x2c0 */
+	uint32_t	reserved_hw_digctl_debug_trap_l0_addr_low[3];
+	uint32_t	hw_digctl_debug_trap_l0_addr_high;	/* 0x2d0 */
+	uint32_t	reserved_hw_digctl_debug_trap_l0_addr_high[3];
+	uint32_t	hw_digctl_debug_trap_l3_addr_low;	/* 0x2e0 */
+	uint32_t	reserved_hw_digctl_debug_trap_l3_addr_low[3];
+	uint32_t	hw_digctl_debug_trap_l3_addr_high;	/* 0x2f0 */
+	uint32_t	reserved_hw_digctl_debug_trap_l3_addr_high[3];
+	uint32_t	hw_digctl_fsl;				/* 0x300 */
+	uint32_t	reserved_hw_digctl_fsl[3];
+	uint32_t	hw_digctl_chipid;			/* 0x310 */
+	uint32_t	reserved_hw_digctl_chipid[3];
+
+	uint32_t	reserved4[4];
+
+	uint32_t	hw_digctl_ahb_stats_select;		/* 0x330 */
+	uint32_t	reserved_hw_digctl_ahb_stats_select[3];
+
+	uint32_t	reserved5[12];
+
+	uint32_t	hw_digctl_l1_ahb_active_cycles;		/* 0x370 */
+	uint32_t	reserved_hw_digctl_l1_ahb_active_cycles[3];
+	uint32_t	hw_digctl_l1_ahb_data_stalled;		/* 0x380 */
+	uint32_t	reserved_hw_digctl_l1_ahb_data_stalled[3];
+	uint32_t	hw_digctl_l1_ahb_data_cycles;		/* 0x390 */
+	uint32_t	reserved_hw_digctl_l1_ahb_data_cycles[3];
+	uint32_t	hw_digctl_l2_ahb_active_cycles;		/* 0x3a0 */
+	uint32_t	reserved_hw_digctl_l2_ahb_active_cycles[3];
+	uint32_t	hw_digctl_l2_ahb_data_stalled;		/* 0x3b0 */
+	uint32_t	reserved_hw_digctl_l2_ahb_data_stalled[3];
+	uint32_t	hw_digctl_l2_ahb_data_cycles;		/* 0x3c0 */
+	uint32_t	reserved_hw_digctl_l2_ahb_data_cycles[3];
+	uint32_t	hw_digctl_l3_ahb_active_cycles;		/* 0x3d0 */
+	uint32_t	reserved_hw_digctl_l3_ahb_active_cycles[3];
+	uint32_t	hw_digctl_l3_ahb_data_stalled;		/* 0x3e0 */
+	uint32_t	reserved_hw_digctl_l3_ahb_data_stalled[3];
+	uint32_t	hw_digctl_l3_ahb_data_cycles;		/* 0x3f0 */
+	uint32_t	reserved_hw_digctl_l3_ahb_data_cycles[3];
+
+	uint32_t	reserved6[64];
+
+	uint32_t	hw_digctl_mpte0_loc;			/* 0x500 */
+	uint32_t	reserved_hw_digctl_mpte0_loc[3];
+	uint32_t	hw_digctl_mpte1_loc;			/* 0x510 */
+	uint32_t	reserved_hw_digctl_mpte1_loc[3];
+	uint32_t	hw_digctl_mpte2_loc;			/* 0x520 */
+	uint32_t	reserved_hw_digctl_mpte2_loc[3];
+	uint32_t	hw_digctl_mpte3_loc;			/* 0x530 */
+	uint32_t	reserved_hw_digctl_mpte3_loc[3];
+	uint32_t	hw_digctl_mpte4_loc;			/* 0x540 */
+	uint32_t	reserved_hw_digctl_mpte4_loc[3];
+	uint32_t	hw_digctl_mpte5_loc;			/* 0x550 */
+	uint32_t	reserved_hw_digctl_mpte5_loc[3];
+	uint32_t	hw_digctl_mpte6_loc;			/* 0x560 */
+	uint32_t	reserved_hw_digctl_mpte6_loc[3];
+	uint32_t	hw_digctl_mpte7_loc;			/* 0x570 */
+	uint32_t	reserved_hw_digctl_mpte7_loc[3];
+	uint32_t	hw_digctl_mpte8_loc;			/* 0x580 */
+	uint32_t	reserved_hw_digctl_mpte8_loc[3];
+	uint32_t	hw_digctl_mpte9_loc;			/* 0x590 */
+	uint32_t	reserved_hw_digctl_mpte9_loc[3];
+	uint32_t	hw_digctl_mpte10_loc;			/* 0x5a0 */
+	uint32_t	reserved_hw_digctl_mpte10_loc[3];
+	uint32_t	hw_digctl_mpte11_loc;			/* 0x5b0 */
+	uint32_t	reserved_hw_digctl_mpte11_loc[3];
+	uint32_t	hw_digctl_mpte12_loc;			/* 0x5c0 */
+	uint32_t	reserved_hw_digctl_mpte12_loc[3];
+	uint32_t	hw_digctl_mpte13_loc;			/* 0x5d0 */
+	uint32_t	reserved_hw_digctl_mpte13_loc[3];
+	uint32_t	hw_digctl_mpte14_loc;			/* 0x5e0 */
+	uint32_t	reserved_hw_digctl_mpte14_loc[3];
+	uint32_t	hw_digctl_mpte15_loc;			/* 0x5f0 */
+	uint32_t	reserved_hw_digctl_mpte15_loc[3];
+};
+#endif
+
+/* Product code identification */
+#define HW_DIGCTL_CHIPID_MASK	(0xffff << 16)
+#define HW_DIGCTL_CHIPID_MX23	(0x3780 << 16)
+#define HW_DIGCTL_CHIPID_MX28	(0x2800 << 16)
+
+#endif /* __MX28_REGS_DIGCTL_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-i2c.h b/arch/arm/include/asm/arch-mxs/regs-i2c.h
new file mode 100644
index 0000000..4cc2e0b
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-i2c.h
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 I2C Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#ifndef __MX28_REGS_I2C_H__
+#define __MX28_REGS_I2C_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_i2c_regs {
+	mxs_reg_32(hw_i2c_ctrl0)
+	mxs_reg_32(hw_i2c_timing0)
+	mxs_reg_32(hw_i2c_timing1)
+	mxs_reg_32(hw_i2c_timing2)
+	mxs_reg_32(hw_i2c_ctrl1)
+	mxs_reg_32(hw_i2c_stat)
+	mxs_reg_32(hw_i2c_queuectrl)
+	mxs_reg_32(hw_i2c_queuestat)
+	mxs_reg_32(hw_i2c_queuecmd)
+	mxs_reg_32(hw_i2c_queuedata)
+	mxs_reg_32(hw_i2c_data)
+	mxs_reg_32(hw_i2c_debug0)
+	mxs_reg_32(hw_i2c_debug1)
+	mxs_reg_32(hw_i2c_version)
+};
+#endif
+
+#define	I2C_CTRL_SFTRST				(1 << 31)
+#define	I2C_CTRL_CLKGATE			(1 << 30)
+#define	I2C_CTRL_RUN				(1 << 29)
+#define	I2C_CTRL_PREACK				(1 << 27)
+#define	I2C_CTRL_ACKNOWLEDGE			(1 << 26)
+#define	I2C_CTRL_SEND_NAK_ON_LAST		(1 << 25)
+#define	I2C_CTRL_MULTI_MASTER			(1 << 23)
+#define	I2C_CTRL_CLOCK_HELD			(1 << 22)
+#define	I2C_CTRL_RETAIN_CLOCK			(1 << 21)
+#define	I2C_CTRL_POST_SEND_STOP			(1 << 20)
+#define	I2C_CTRL_PRE_SEND_START			(1 << 19)
+#define	I2C_CTRL_SLAVE_ADDRESS_ENABLE		(1 << 18)
+#define	I2C_CTRL_MASTER_MODE			(1 << 17)
+#define	I2C_CTRL_DIRECTION			(1 << 16)
+#define	I2C_CTRL_XFER_COUNT_MASK		0xffff
+#define	I2C_CTRL_XFER_COUNT_OFFSET		0
+
+#define	I2C_TIMING0_HIGH_COUNT_MASK		(0x3ff << 16)
+#define	I2C_TIMING0_HIGH_COUNT_OFFSET		16
+#define	I2C_TIMING0_RCV_COUNT_MASK		0x3ff
+#define	I2C_TIMING0_RCV_COUNT_OFFSET		0
+
+#define	I2C_TIMING1_LOW_COUNT_MASK		(0x3ff << 16)
+#define	I2C_TIMING1_LOW_COUNT_OFFSET		16
+#define	I2C_TIMING1_XMIT_COUNT_MASK		0x3ff
+#define	I2C_TIMING1_XMIT_COUNT_OFFSET		0
+
+#define	I2C_TIMING2_BUS_FREE_MASK		(0x3ff << 16)
+#define	I2C_TIMING2_BUS_FREE_OFFSET		16
+#define	I2C_TIMING2_LEADIN_COUNT_MASK		0x3ff
+#define	I2C_TIMING2_LEADIN_COUNT_OFFSET		0
+
+#define	I2C_CTRL1_RD_QUEUE_IRQ			(1 << 30)
+#define	I2C_CTRL1_WR_QUEUE_IRQ			(1 << 29)
+#define	I2C_CTRL1_CLR_GOT_A_NAK			(1 << 28)
+#define	I2C_CTRL1_ACK_MODE			(1 << 27)
+#define	I2C_CTRL1_FORCE_DATA_IDLE		(1 << 26)
+#define	I2C_CTRL1_FORCE_CLK_IDLE		(1 << 25)
+#define	I2C_CTRL1_BCAST_SLAVE_EN		(1 << 24)
+#define	I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK	(0xff << 16)
+#define	I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET	16
+#define	I2C_CTRL1_BUS_FREE_IRQ_EN		(1 << 15)
+#define	I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN	(1 << 14)
+#define	I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN		(1 << 13)
+#define	I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN	(1 << 12)
+#define	I2C_CTRL1_EARLY_TERM_IRQ_EN		(1 << 11)
+#define	I2C_CTRL1_MASTER_LOSS_IRQ_EN		(1 << 10)
+#define	I2C_CTRL1_SLAVE_STOP_IRQ_EN		(1 << 9)
+#define	I2C_CTRL1_SLAVE_IRQ_EN			(1 << 8)
+#define	I2C_CTRL1_BUS_FREE_IRQ			(1 << 7)
+#define	I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ		(1 << 6)
+#define	I2C_CTRL1_NO_SLAVE_ACK_IRQ		(1 << 5)
+#define	I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ	(1 << 4)
+#define	I2C_CTRL1_EARLY_TERM_IRQ		(1 << 3)
+#define	I2C_CTRL1_MASTER_LOSS_IRQ		(1 << 2)
+#define	I2C_CTRL1_SLAVE_STOP_IRQ		(1 << 1)
+#define	I2C_CTRL1_SLAVE_IRQ			(1 << 0)
+
+#define	I2C_STAT_MASTER_PRESENT			(1 << 31)
+#define	I2C_STAT_SLAVE_PRESENT			(1 << 30)
+#define	I2C_STAT_ANY_ENABLED_IRQ		(1 << 29)
+#define	I2C_STAT_GOT_A_NAK			(1 << 28)
+#define	I2C_STAT_RCVD_SLAVE_ADDR_MASK		(0xff << 16)
+#define	I2C_STAT_RCVD_SLAVE_ADDR_OFFSET		16
+#define	I2C_STAT_SLAVE_ADDR_EQ_ZERO		(1 << 15)
+#define	I2C_STAT_SLAVE_FOUND			(1 << 14)
+#define	I2C_STAT_SLAVE_SEARCHING		(1 << 13)
+#define	I2C_STAT_DATA_ENGING_DMA_WAIT		(1 << 12)
+#define	I2C_STAT_BUS_BUSY			(1 << 11)
+#define	I2C_STAT_CLK_GEN_BUSY			(1 << 10)
+#define	I2C_STAT_DATA_ENGINE_BUSY		(1 << 9)
+#define	I2C_STAT_SLAVE_BUSY			(1 << 8)
+#define	I2C_STAT_BUS_FREE_IRQ_SUMMARY		(1 << 7)
+#define	I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY	(1 << 6)
+#define	I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY	(1 << 5)
+#define	I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY	(1 << 4)
+#define	I2C_STAT_EARLY_TERM_IRQ_SUMMARY		(1 << 3)
+#define	I2C_STAT_MASTER_LOSS_IRQ_SUMMARY	(1 << 2)
+#define	I2C_STAT_SLAVE_STOP_IRQ_SUMMARY		(1 << 1)
+#define	I2C_STAT_SLAVE_IRQ_SUMMARY		(1 << 0)
+
+#define	I2C_QUEUECTRL_RD_THRESH_MASK		(0x1f << 16)
+#define	I2C_QUEUECTRL_RD_THRESH_OFFSET		16
+#define	I2C_QUEUECTRL_WR_THRESH_MASK		(0x1f << 8)
+#define	I2C_QUEUECTRL_WR_THRESH_OFFSET		8
+#define	I2C_QUEUECTRL_QUEUE_RUN			(1 << 5)
+#define	I2C_QUEUECTRL_RD_CLEAR			(1 << 4)
+#define	I2C_QUEUECTRL_WR_CLEAR			(1 << 3)
+#define	I2C_QUEUECTRL_PIO_QUEUE_MODE		(1 << 2)
+#define	I2C_QUEUECTRL_RD_QUEUE_IRQ_EN		(1 << 1)
+#define	I2C_QUEUECTRL_WR_QUEUE_IRQ_EN		(1 << 0)
+
+#define	I2C_QUEUESTAT_RD_QUEUE_FULL		(1 << 14)
+#define	I2C_QUEUESTAT_RD_QUEUE_EMPTY		(1 << 13)
+#define	I2C_QUEUESTAT_RD_QUEUE_CNT_MASK		(0x1f << 8)
+#define	I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET	8
+#define	I2C_QUEUESTAT_WR_QUEUE_FULL		(1 << 6)
+#define	I2C_QUEUESTAT_WR_QUEUE_EMPTY		(1 << 5)
+#define	I2C_QUEUESTAT_WR_QUEUE_CNT_MASK		0x1f
+#define	I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET	0
+
+#define	I2C_QUEUECMD_PREACK			(1 << 27)
+#define	I2C_QUEUECMD_ACKNOWLEDGE		(1 << 26)
+#define	I2C_QUEUECMD_SEND_NAK_ON_LAST		(1 << 25)
+#define	I2C_QUEUECMD_MULTI_MASTER		(1 << 23)
+#define	I2C_QUEUECMD_CLOCK_HELD			(1 << 22)
+#define	I2C_QUEUECMD_RETAIN_CLOCK		(1 << 21)
+#define	I2C_QUEUECMD_POST_SEND_STOP		(1 << 20)
+#define	I2C_QUEUECMD_PRE_SEND_START		(1 << 19)
+#define	I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE	(1 << 18)
+#define	I2C_QUEUECMD_MASTER_MODE		(1 << 17)
+#define	I2C_QUEUECMD_DIRECTION			(1 << 16)
+#define	I2C_QUEUECMD_XFER_COUNT_MASK		0xffff
+#define	I2C_QUEUECMD_XFER_COUNT_OFFSET		0
+
+#define	I2C_QUEUEDATA_DATA_MASK			0xffffffff
+#define	I2C_QUEUEDATA_DATA_OFFSET		0
+
+#define	I2C_DATA_DATA_MASK			0xffffffff
+#define	I2C_DATA_DATA_OFFSET			0
+
+#define	I2C_DEBUG0_DMAREQ			(1 << 31)
+#define	I2C_DEBUG0_DMAENDCMD			(1 << 30)
+#define	I2C_DEBUG0_DMAKICK			(1 << 29)
+#define	I2C_DEBUG0_DMATERMINATE			(1 << 28)
+#define	I2C_DEBUG0_STATE_VALUE_MASK		(0x3 << 26)
+#define	I2C_DEBUG0_STATE_VALUE_OFFSET		26
+#define	I2C_DEBUG0_DMA_STATE_MASK		(0x3ff << 16)
+#define	I2C_DEBUG0_DMA_STATE_OFFSET		16
+#define	I2C_DEBUG0_START_TOGGLE			(1 << 15)
+#define	I2C_DEBUG0_STOP_TOGGLE			(1 << 14)
+#define	I2C_DEBUG0_GRAB_TOGGLE			(1 << 13)
+#define	I2C_DEBUG0_CHANGE_TOGGLE		(1 << 12)
+#define	I2C_DEBUG0_STATE_LATCH			(1 << 11)
+#define	I2C_DEBUG0_SLAVE_HOLD_CLK		(1 << 10)
+#define	I2C_DEBUG0_STATE_STATE_MASK		0x3ff
+#define	I2C_DEBUG0_STATE_STATE_OFFSET		0
+
+#define	I2C_DEBUG1_I2C_CLK_IN			(1 << 31)
+#define	I2C_DEBUG1_I2C_DATA_IN			(1 << 30)
+#define	I2C_DEBUG1_DMA_BYTE_ENABLES_MASK	(0xf << 24)
+#define	I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET	24
+#define	I2C_DEBUG1_CLK_GEN_STATE_MASK		(0xff << 16)
+#define	I2C_DEBUG1_CLK_GEN_STATE_OFFSET		16
+#define	I2C_DEBUG1_LST_MODE_MASK		(0x3 << 9)
+#define	I2C_DEBUG1_LST_MODE_OFFSET		9
+#define	I2C_DEBUG1_LOCAL_SLAVE_TEST		(1 << 8)
+#define	I2C_DEBUG1_FORCE_CLK_ON			(1 << 4)
+#define	I2C_DEBUG1_FORCE_ABR_LOSS		(1 << 3)
+#define	I2C_DEBUG1_FORCE_RCV_ACK		(1 << 2)
+#define	I2C_DEBUG1_FORCE_I2C_DATA_OE		(1 << 1)
+#define	I2C_DEBUG1_FORCE_I2C_CLK_OE		(1 << 0)
+
+#define	I2C_VERSION_MAJOR_MASK			(0xff << 24)
+#define	I2C_VERSION_MAJOR_OFFSET		24
+#define	I2C_VERSION_MINOR_MASK			(0xff << 16)
+#define	I2C_VERSION_MINOR_OFFSET		16
+#define	I2C_VERSION_STEP_MASK			0xffff
+#define	I2C_VERSION_STEP_OFFSET			0
+
+#endif	/* __MX28_REGS_I2C_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-lradc.h b/arch/arm/include/asm/arch-mxs/regs-lradc.h
new file mode 100644
index 0000000..a48f7a4
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-lradc.h
@@ -0,0 +1,386 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 LRADC Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __MX28_REGS_LRADC_H__
+#define __MX28_REGS_LRADC_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_lradc_regs {
+	mxs_reg_32(hw_lradc_ctrl0);
+	mxs_reg_32(hw_lradc_ctrl1);
+	mxs_reg_32(hw_lradc_ctrl2);
+	mxs_reg_32(hw_lradc_ctrl3);
+	mxs_reg_32(hw_lradc_status);
+	mxs_reg_32(hw_lradc_ch0);
+	mxs_reg_32(hw_lradc_ch1);
+	mxs_reg_32(hw_lradc_ch2);
+	mxs_reg_32(hw_lradc_ch3);
+	mxs_reg_32(hw_lradc_ch4);
+	mxs_reg_32(hw_lradc_ch5);
+	mxs_reg_32(hw_lradc_ch6);
+	mxs_reg_32(hw_lradc_ch7);
+	mxs_reg_32(hw_lradc_delay0);
+	mxs_reg_32(hw_lradc_delay1);
+	mxs_reg_32(hw_lradc_delay2);
+	mxs_reg_32(hw_lradc_delay3);
+	mxs_reg_32(hw_lradc_debug0);
+	mxs_reg_32(hw_lradc_debug1);
+	mxs_reg_32(hw_lradc_conversion);
+	mxs_reg_32(hw_lradc_ctrl4);
+	mxs_reg_32(hw_lradc_treshold0);
+	mxs_reg_32(hw_lradc_treshold1);
+	mxs_reg_32(hw_lradc_version);
+};
+#endif
+
+#define	LRADC_CTRL0_SFTRST					(1 << 31)
+#define	LRADC_CTRL0_CLKGATE					(1 << 30)
+#define	LRADC_CTRL0_ONCHIP_GROUNDREF				(1 << 26)
+#define	LRADC_CTRL0_BUTTON1_DETECT_ENABLE			(1 << 25)
+#define	LRADC_CTRL0_BUTTON0_DETECT_ENABLE			(1 << 24)
+#define	LRADC_CTRL0_TOUCH_DETECT_ENABLE				(1 << 23)
+#define	LRADC_CTRL0_TOUCH_SCREEN_TYPE				(1 << 22)
+#define	LRADC_CTRL0_YNLRSW					(1 << 21)
+#define	LRADC_CTRL0_YPLLSW_MASK					(0x3 << 19)
+#define	LRADC_CTRL0_YPLLSW_OFFSET				19
+#define	LRADC_CTRL0_XNURSW_MASK					(0x3 << 17)
+#define	LRADC_CTRL0_XNURSW_OFFSET				17
+#define	LRADC_CTRL0_XPULSW					(1 << 16)
+#define	LRADC_CTRL0_SCHEDULE_MASK				0xff
+#define	LRADC_CTRL0_SCHEDULE_OFFSET				0
+
+#define	LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN			(1 << 28)
+#define	LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN			(1 << 27)
+#define	LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN			(1 << 26)
+#define	LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN			(1 << 25)
+#define	LRADC_CTRL1_TOUCH_DETECT_IRQ_EN				(1 << 24)
+#define	LRADC_CTRL1_LRADC7_IRQ_EN				(1 << 23)
+#define	LRADC_CTRL1_LRADC6_IRQ_EN				(1 << 22)
+#define	LRADC_CTRL1_LRADC5_IRQ_EN				(1 << 21)
+#define	LRADC_CTRL1_LRADC4_IRQ_EN				(1 << 20)
+#define	LRADC_CTRL1_LRADC3_IRQ_EN				(1 << 19)
+#define	LRADC_CTRL1_LRADC2_IRQ_EN				(1 << 18)
+#define	LRADC_CTRL1_LRADC1_IRQ_EN				(1 << 17)
+#define	LRADC_CTRL1_LRADC0_IRQ_EN				(1 << 16)
+#define	LRADC_CTRL1_BUTTON1_DETECT_IRQ				(1 << 12)
+#define	LRADC_CTRL1_BUTTON0_DETECT_IRQ				(1 << 11)
+#define	LRADC_CTRL1_THRESHOLD1_DETECT_IRQ			(1 << 10)
+#define	LRADC_CTRL1_THRESHOLD0_DETECT_IRQ			(1 << 9)
+#define	LRADC_CTRL1_TOUCH_DETECT_IRQ				(1 << 8)
+#define	LRADC_CTRL1_LRADC7_IRQ					(1 << 7)
+#define	LRADC_CTRL1_LRADC6_IRQ					(1 << 6)
+#define	LRADC_CTRL1_LRADC5_IRQ					(1 << 5)
+#define	LRADC_CTRL1_LRADC4_IRQ					(1 << 4)
+#define	LRADC_CTRL1_LRADC3_IRQ					(1 << 3)
+#define	LRADC_CTRL1_LRADC2_IRQ					(1 << 2)
+#define	LRADC_CTRL1_LRADC1_IRQ					(1 << 1)
+#define	LRADC_CTRL1_LRADC0_IRQ					(1 << 0)
+
+#define	LRADC_CTRL2_DIVIDE_BY_TWO_MASK				(0xff << 24)
+#define	LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET			24
+#define	LRADC_CTRL2_TEMPSENSE_PWD				(1 << 15)
+#define	LRADC_CTRL2_VTHSENSE_MASK				(0x3 << 13)
+#define	LRADC_CTRL2_VTHSENSE_OFFSET				13
+#define	LRADC_CTRL2_DISABLE_MUXAMP_BYPASS			(1 << 12)
+#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE1			(1 << 9)
+#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE0			(1 << 8)
+#define	LRADC_CTRL2_TEMP_ISRC1_MASK				(0xf << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_OFFSET				4
+#define	LRADC_CTRL2_TEMP_ISRC1_300				(0xf << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_280				(0xe << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_260				(0xd << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_240				(0xc << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_220				(0xb << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_200				(0xa << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_180				(0x9 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_160				(0x8 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_140				(0x7 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_120				(0x6 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_100				(0x5 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_80				(0x4 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_60				(0x3 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_40				(0x2 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_20				(0x1 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC1_ZERO				(0x0 << 4)
+#define	LRADC_CTRL2_TEMP_ISRC0_MASK				(0xf << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_OFFSET				0
+#define	LRADC_CTRL2_TEMP_ISRC0_300				(0xf << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_280				(0xe << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_260				(0xd << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_240				(0xc << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_220				(0xb << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_200				(0xa << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_180				(0x9 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_160				(0x8 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_140				(0x7 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_120				(0x6 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_100				(0x5 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_80				(0x4 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_60				(0x3 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_40				(0x2 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_20				(0x1 << 0)
+#define	LRADC_CTRL2_TEMP_ISRC0_ZERO				(0x0 << 0)
+
+#define	LRADC_CTRL3_DISCARD_MASK				(0x3 << 24)
+#define	LRADC_CTRL3_DISCARD_OFFSET				24
+#define	LRADC_CTRL3_DISCARD_1_SAMPLE				(0x1 << 24)
+#define	LRADC_CTRL3_DISCARD_2_SAMPLES				(0x2 << 24)
+#define	LRADC_CTRL3_DISCARD_3_SAMPLES				(0x3 << 24)
+#define	LRADC_CTRL3_FORCE_ANALOG_PWUP				(1 << 23)
+#define	LRADC_CTRL3_FORCE_ANALOG_PWDN				(1 << 22)
+#define	LRADC_CTRL3_CYCLE_TIME_MASK				(0x3 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_OFFSET				8
+#define	LRADC_CTRL3_CYCLE_TIME_6MHZ				(0x0 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_4MHZ				(0x1 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_3MHZ				(0x2 << 8)
+#define	LRADC_CTRL3_CYCLE_TIME_2MHZ				(0x3 << 8)
+#define	LRADC_CTRL3_HIGH_TIME_MASK				(0x3 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_OFFSET				4
+#define	LRADC_CTRL3_HIGH_TIME_42NS				(0x0 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_83NS				(0x1 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_125NS				(0x2 << 4)
+#define	LRADC_CTRL3_HIGH_TIME_250NS				(0x3 << 4)
+#define	LRADC_CTRL3_DELAY_CLOCK					(1 << 1)
+#define	LRADC_CTRL3_INVERT_CLOCK				(1 << 0)
+
+#define	LRADC_STATUS_BUTTON1_PRESENT				(1 << 28)
+#define	LRADC_STATUS_BUTTON0_PRESENT				(1 << 27)
+#define	LRADC_STATUS_TEMP1_PRESENT				(1 << 26)
+#define	LRADC_STATUS_TEMP0_PRESENT				(1 << 25)
+#define	LRADC_STATUS_TOUCH_PANEL_PRESENT			(1 << 24)
+#define	LRADC_STATUS_CHANNEL7_PRESENT				(1 << 23)
+#define	LRADC_STATUS_CHANNEL6_PRESENT				(1 << 22)
+#define	LRADC_STATUS_CHANNEL5_PRESENT				(1 << 21)
+#define	LRADC_STATUS_CHANNEL4_PRESENT				(1 << 20)
+#define	LRADC_STATUS_CHANNEL3_PRESENT				(1 << 19)
+#define	LRADC_STATUS_CHANNEL2_PRESENT				(1 << 18)
+#define	LRADC_STATUS_CHANNEL1_PRESENT				(1 << 17)
+#define	LRADC_STATUS_CHANNEL0_PRESENT				(1 << 16)
+#define	LRADC_STATUS_BUTTON1_DETECT_RAW				(1 << 2)
+#define	LRADC_STATUS_BUTTON0_DETECT_RAW				(1 << 1)
+#define	LRADC_STATUS_TOUCH_DETECT_RAW				(1 << 0)
+
+#define	LRADC_CH_TOGGLE						(1 << 31)
+#define	LRADC_CH7_TESTMODE_TOGGLE				(1 << 30)
+#define	LRADC_CH_ACCUMULATE					(1 << 29)
+#define	LRADC_CH_NUM_SAMPLES_MASK				(0x1f << 24)
+#define	LRADC_CH_NUM_SAMPLES_OFFSET				24
+#define	LRADC_CH_VALUE_MASK					0x3ffff
+#define	LRADC_CH_VALUE_OFFSET					0
+
+#define	LRADC_DELAY_TRIGGER_LRADCS_MASK				(0xff << 24)
+#define	LRADC_DELAY_TRIGGER_LRADCS_OFFSET			24
+#define	LRADC_DELAY_KICK					(1 << 20)
+#define	LRADC_DELAY_TRIGGER_DELAYS_MASK				(0xf << 16)
+#define	LRADC_DELAY_TRIGGER_DELAYS_OFFSET			16
+#define	LRADC_DELAY_LOOP_COUNT_MASK				(0x1f << 11)
+#define	LRADC_DELAY_LOOP_COUNT_OFFSET				11
+#define	LRADC_DELAY_DELAY_MASK					0x7ff
+#define	LRADC_DELAY_DELAY_OFFSET				0
+
+#define	LRADC_DEBUG0_READONLY_MASK				(0xffff << 16)
+#define	LRADC_DEBUG0_READONLY_OFFSET				16
+#define	LRADC_DEBUG0_STATE_MASK					(0xfff << 0)
+#define	LRADC_DEBUG0_STATE_OFFSET				0
+
+#define	LRADC_DEBUG1_REQUEST_MASK				(0xff << 16)
+#define	LRADC_DEBUG1_REQUEST_OFFSET				16
+#define	LRADC_DEBUG1_TESTMODE_COUNT_MASK			(0x1f << 8)
+#define	LRADC_DEBUG1_TESTMODE_COUNT_OFFSET			8
+#define	LRADC_DEBUG1_TESTMODE6					(1 << 2)
+#define	LRADC_DEBUG1_TESTMODE5					(1 << 1)
+#define	LRADC_DEBUG1_TESTMODE					(1 << 0)
+
+#define	LRADC_CONVERSION_AUTOMATIC				(1 << 20)
+#define	LRADC_CONVERSION_SCALE_FACTOR_MASK			(0x3 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_OFFSET			16
+#define	LRADC_CONVERSION_SCALE_FACTOR_NIMH			(0x0 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH			(0x1 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_LI_ION			(0x2 << 16)
+#define	LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION		(0x3 << 16)
+#define	LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK		0x3ff
+#define	LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET		0
+
+#define	LRADC_CTRL4_LRADC7SELECT_MASK				(0xf << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_OFFSET				28
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL0			(0x0 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL1			(0x1 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL2			(0x2 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL3			(0x3 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL4			(0x4 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL5			(0x5 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL6			(0x6 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL7			(0x7 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL8			(0x8 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL9			(0x9 << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL10			(0xa << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL11			(0xb << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL12			(0xc << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL13			(0xd << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL14			(0xe << 28)
+#define	LRADC_CTRL4_LRADC7SELECT_CHANNEL15			(0xf << 28)
+#define	LRADC_CTRL4_LRADC6SELECT_MASK				(0xf << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_OFFSET				24
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL0			(0x0 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL1			(0x1 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL2			(0x2 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL3			(0x3 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL4			(0x4 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL5			(0x5 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL6			(0x6 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL7			(0x7 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL8			(0x8 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL9			(0x9 << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL10			(0xa << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL11			(0xb << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL12			(0xc << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL13			(0xd << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL14			(0xe << 24)
+#define	LRADC_CTRL4_LRADC6SELECT_CHANNEL15			(0xf << 24)
+#define	LRADC_CTRL4_LRADC5SELECT_MASK				(0xf << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_OFFSET				20
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL0			(0x0 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL1			(0x1 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL2			(0x2 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL3			(0x3 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL4			(0x4 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL5			(0x5 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL6			(0x6 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL7			(0x7 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL8			(0x8 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL9			(0x9 << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL10			(0xa << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL11			(0xb << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL12			(0xc << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL13			(0xd << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL14			(0xe << 20)
+#define	LRADC_CTRL4_LRADC5SELECT_CHANNEL15			(0xf << 20)
+#define	LRADC_CTRL4_LRADC4SELECT_MASK				(0xf << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_OFFSET				16
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL0			(0x0 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL1			(0x1 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL2			(0x2 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL3			(0x3 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL4			(0x4 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL5			(0x5 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL6			(0x6 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL7			(0x7 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL8			(0x8 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL9			(0x9 << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL10			(0xa << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL11			(0xb << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL12			(0xc << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL13			(0xd << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL14			(0xe << 16)
+#define	LRADC_CTRL4_LRADC4SELECT_CHANNEL15			(0xf << 16)
+#define	LRADC_CTRL4_LRADC3SELECT_MASK				(0xf << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_OFFSET				12
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL0			(0x0 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL1			(0x1 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL2			(0x2 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL3			(0x3 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL4			(0x4 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL5			(0x5 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL6			(0x6 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL7			(0x7 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL8			(0x8 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL9			(0x9 << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL10			(0xa << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL11			(0xb << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL12			(0xc << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL13			(0xd << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL14			(0xe << 12)
+#define	LRADC_CTRL4_LRADC3SELECT_CHANNEL15			(0xf << 12)
+#define	LRADC_CTRL4_LRADC2SELECT_MASK				(0xf << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_OFFSET				8
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL0			(0x0 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL1			(0x1 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL2			(0x2 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL3			(0x3 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL4			(0x4 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL5			(0x5 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL6			(0x6 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL7			(0x7 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL8			(0x8 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL9			(0x9 << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL10			(0xa << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL11			(0xb << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL12			(0xc << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL13			(0xd << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL14			(0xe << 8)
+#define	LRADC_CTRL4_LRADC2SELECT_CHANNEL15			(0xf << 8)
+#define	LRADC_CTRL4_LRADC1SELECT_MASK				(0xf << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_OFFSET				4
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL0			(0x0 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL1			(0x1 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL2			(0x2 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL3			(0x3 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL4			(0x4 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL5			(0x5 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL6			(0x6 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL7			(0x7 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL8			(0x8 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL9			(0x9 << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL10			(0xa << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL11			(0xb << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL12			(0xc << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL13			(0xd << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL14			(0xe << 4)
+#define	LRADC_CTRL4_LRADC1SELECT_CHANNEL15			(0xf << 4)
+#define	LRADC_CTRL4_LRADC0SELECT_MASK				0xf
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL0			(0x0 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL1			(0x1 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL2			(0x2 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL3			(0x3 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL4			(0x4 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL5			(0x5 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL6			(0x6 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL7			(0x7 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL8			(0x8 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL9			(0x9 << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL10			(0xa << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL11			(0xb << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL12			(0xc << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL13			(0xd << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL14			(0xe << 0)
+#define	LRADC_CTRL4_LRADC0SELECT_CHANNEL15			(0xf << 0)
+
+#define	LRADC_THRESHOLD_ENABLE					(1 << 24)
+#define	LRADC_THRESHOLD_BATTCHRG_DISABLE			(1 << 23)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_MASK			(0x7 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_OFFSET			20
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0			(0x0 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1			(0x1 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2			(0x2 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3			(0x3 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4			(0x4 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5			(0x5 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6			(0x6 << 20)
+#define	LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7			(0x7 << 20)
+#define	LRADC_THRESHOLD_SETTING_MASK				(0x3 << 18)
+#define	LRADC_THRESHOLD_SETTING_OFFSET				18
+#define	LRADC_THRESHOLD_SETTING_NO_COMPARE			(0x0 << 18)
+#define	LRADC_THRESHOLD_SETTING_DETECT_LOW			(0x1 << 18)
+#define	LRADC_THRESHOLD_SETTING_DETECT_HIGH			(0x2 << 18)
+#define	LRADC_THRESHOLD_SETTING_RESERVED			(0x3 << 18)
+#define	LRADC_THRESHOLD_VALUE_MASK				0x3ffff
+#define	LRADC_THRESHOLD_VALUE_OFFSET				0
+
+#define	LRADC_VERSION_MAJOR_MASK				(0xff << 24)
+#define	LRADC_VERSION_MAJOR_OFFSET				24
+#define	LRADC_VERSION_MINOR_MASK				(0xff << 16)
+#define	LRADC_VERSION_MINOR_OFFSET				16
+#define	LRADC_VERSION_STEP_MASK					0xffff
+#define	LRADC_VERSION_STEP_OFFSET				0
+
+#endif	/* __MX28_REGS_LRADC_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/arch/arm/include/asm/arch-mxs/regs-ocotp.h
new file mode 100644
index 0000000..8bfbd19
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-ocotp.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 OCOTP Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __MX28_REGS_OCOTP_H__
+#define __MX28_REGS_OCOTP_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_ocotp_regs {
+	mxs_reg_32(hw_ocotp_ctrl)	/* 0x0 */
+	mxs_reg_32(hw_ocotp_data)	/* 0x10 */
+	mxs_reg_32(hw_ocotp_cust0)	/* 0x20 */
+	mxs_reg_32(hw_ocotp_cust1)	/* 0x30 */
+	mxs_reg_32(hw_ocotp_cust2)	/* 0x40 */
+	mxs_reg_32(hw_ocotp_cust3)	/* 0x50 */
+	mxs_reg_32(hw_ocotp_crypto0)	/* 0x60 */
+	mxs_reg_32(hw_ocotp_crypto1)	/* 0x70 */
+	mxs_reg_32(hw_ocotp_crypto2)	/* 0x80 */
+	mxs_reg_32(hw_ocotp_crypto3)	/* 0x90 */
+	mxs_reg_32(hw_ocotp_hwcap0)	/* 0xa0 */
+	mxs_reg_32(hw_ocotp_hwcap1)	/* 0xb0 */
+	mxs_reg_32(hw_ocotp_hwcap2)	/* 0xc0 */
+	mxs_reg_32(hw_ocotp_hwcap3)	/* 0xd0 */
+	mxs_reg_32(hw_ocotp_hwcap4)	/* 0xe0 */
+	mxs_reg_32(hw_ocotp_hwcap5)	/* 0xf0 */
+	mxs_reg_32(hw_ocotp_swcap)	/* 0x100 */
+	mxs_reg_32(hw_ocotp_custcap)	/* 0x110 */
+	mxs_reg_32(hw_ocotp_lock)	/* 0x120 */
+	mxs_reg_32(hw_ocotp_ops0)	/* 0x130 */
+	mxs_reg_32(hw_ocotp_ops1)	/* 0x140 */
+	mxs_reg_32(hw_ocotp_ops2)	/* 0x150 */
+	mxs_reg_32(hw_ocotp_ops3)	/* 0x160 */
+	mxs_reg_32(hw_ocotp_un0)	/* 0x170 */
+	mxs_reg_32(hw_ocotp_un1)	/* 0x180 */
+	mxs_reg_32(hw_ocotp_un2)	/* 0x190 */
+	mxs_reg_32(hw_ocotp_rom0)	/* 0x1a0 */
+	mxs_reg_32(hw_ocotp_rom1)	/* 0x1b0 */
+	mxs_reg_32(hw_ocotp_rom2)	/* 0x1c0 */
+	mxs_reg_32(hw_ocotp_rom3)	/* 0x1d0 */
+	mxs_reg_32(hw_ocotp_rom4)	/* 0x1e0 */
+	mxs_reg_32(hw_ocotp_rom5)	/* 0x1f0 */
+	mxs_reg_32(hw_ocotp_rom6)	/* 0x200 */
+	mxs_reg_32(hw_ocotp_rom7)	/* 0x210 */
+	mxs_reg_32(hw_ocotp_srk0)	/* 0x220 */
+	mxs_reg_32(hw_ocotp_srk1)	/* 0x230 */
+	mxs_reg_32(hw_ocotp_srk2)	/* 0x240 */
+	mxs_reg_32(hw_ocotp_srk3)	/* 0x250 */
+	mxs_reg_32(hw_ocotp_srk4)	/* 0x260 */
+	mxs_reg_32(hw_ocotp_srk5)	/* 0x270 */
+	mxs_reg_32(hw_ocotp_srk6)	/* 0x280 */
+	mxs_reg_32(hw_ocotp_srk7)	/* 0x290 */
+	mxs_reg_32(hw_ocotp_version)	/* 0x2a0 */
+};
+#endif
+
+#define	OCOTP_CTRL_WR_UNLOCK_MASK		(0xffff << 16)
+#define	OCOTP_CTRL_WR_UNLOCK_OFFSET		16
+#define	OCOTP_CTRL_WR_UNLOCK_KEY		(0x3e77 << 16)
+#define	OCOTP_CTRL_RELOAD_SHADOWS		(1 << 13)
+#define	OCOTP_CTRL_RD_BANK_OPEN			(1 << 12)
+#define	OCOTP_CTRL_ERROR			(1 << 9)
+#define	OCOTP_CTRL_BUSY				(1 << 8)
+#define	OCOTP_CTRL_ADDR_MASK			0x3f
+#define	OCOTP_CTRL_ADDR_OFFSET			0
+
+#define	OCOTP_DATA_DATA_MASK			0xffffffff
+#define	OCOTP_DATA_DATA_OFFSET			0
+
+#define	OCOTP_CUST_BITS_MASK			0xffffffff
+#define	OCOTP_CUST_BITS_OFFSET			0
+
+#define	OCOTP_CRYPTO_BITS_MASK			0xffffffff
+#define	OCOTP_CRYPTO_BITS_OFFSET		0
+
+#define	OCOTP_HWCAP_BITS_MASK			0xffffffff
+#define	OCOTP_HWCAP_BITS_OFFSET			0
+
+#define	OCOTP_SWCAP_BITS_MASK			0xffffffff
+#define	OCOTP_SWCAP_BITS_OFFSET			0
+
+#define	OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT	(1 << 2)
+#define	OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT	(1 << 1)
+
+#define	OCOTP_LOCK_ROM7				(1 << 31)
+#define	OCOTP_LOCK_ROM6				(1 << 30)
+#define	OCOTP_LOCK_ROM5				(1 << 29)
+#define	OCOTP_LOCK_ROM4				(1 << 28)
+#define	OCOTP_LOCK_ROM3				(1 << 27)
+#define	OCOTP_LOCK_ROM2				(1 << 26)
+#define	OCOTP_LOCK_ROM1				(1 << 25)
+#define	OCOTP_LOCK_ROM0				(1 << 24)
+#define	OCOTP_LOCK_HWSW_SHADOW_ALT		(1 << 23)
+#define	OCOTP_LOCK_CRYPTODCP_ALT		(1 << 22)
+#define	OCOTP_LOCK_CRYPTOKEY_ALT		(1 << 21)
+#define	OCOTP_LOCK_PIN				(1 << 20)
+#define	OCOTP_LOCK_OPS				(1 << 19)
+#define	OCOTP_LOCK_UN2				(1 << 18)
+#define	OCOTP_LOCK_UN1				(1 << 17)
+#define	OCOTP_LOCK_UN0				(1 << 16)
+#define	OCOTP_LOCK_SRK				(1 << 15)
+#define	OCOTP_LOCK_UNALLOCATED_MASK		(0x7 << 12)
+#define	OCOTP_LOCK_UNALLOCATED_OFFSET		12
+#define	OCOTP_LOCK_SRK_SHADOW			(1 << 11)
+#define	OCOTP_LOCK_ROM_SHADOW			(1 << 10)
+#define	OCOTP_LOCK_CUSTCAP			(1 << 9)
+#define	OCOTP_LOCK_HWSW				(1 << 8)
+#define	OCOTP_LOCK_CUSTCAP_SHADOW		(1 << 7)
+#define	OCOTP_LOCK_HWSW_SHADOW			(1 << 6)
+#define	OCOTP_LOCK_CRYPTODCP			(1 << 5)
+#define	OCOTP_LOCK_CRYPTOKEY			(1 << 4)
+#define	OCOTP_LOCK_CUST3			(1 << 3)
+#define	OCOTP_LOCK_CUST2			(1 << 2)
+#define	OCOTP_LOCK_CUST1			(1 << 1)
+#define	OCOTP_LOCK_CUST0			(1 << 0)
+
+#define	OCOTP_OPS_BITS_MASK			0xffffffff
+#define	OCOTP_OPS_BITS_OFFSET			0
+
+#define	OCOTP_UN_BITS_MASK			0xffffffff
+#define	OCOTP_UN_BITS_OFFSET			0
+
+#define	OCOTP_ROM_BOOT_MODE_MASK		(0xff << 24)
+#define	OCOTP_ROM_BOOT_MODE_OFFSET		24
+#define	OCOTP_ROM_SD_MMC_MODE_MASK		(0x3 << 22)
+#define	OCOTP_ROM_SD_MMC_MODE_OFFSET		22
+#define	OCOTP_ROM_SD_POWER_GATE_GPIO_MASK	(0x3 << 20)
+#define	OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET	20
+#define	OCOTP_ROM_SD_POWER_UP_DELAY_MASK	(0x3f << 14)
+#define	OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET	14
+#define	OCOTP_ROM_SD_BUS_WIDTH_MASK		(0x3 << 12)
+#define	OCOTP_ROM_SD_BUS_WIDTH_OFFSET		12
+#define	OCOTP_ROM_SSP_SCK_INDEX_MASK		(0xf << 8)
+#define	OCOTP_ROM_SSP_SCK_INDEX_OFFSET		8
+#define	OCOTP_ROM_EMMC_USE_DDR			(1 << 7)
+#define	OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ	(1 << 6)
+#define	OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM	(1 << 5)
+#define	OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT	(1 << 4)
+#define	OCOTP_ROM_SD_MBR_BOOT			(1 << 3)
+
+#define	OCOTP_SRK_BITS_MASK			0xffffffff
+#define	OCOTP_SRK_BITS_OFFSET			0
+
+#define	OCOTP_VERSION_MAJOR_MASK		(0xff << 24)
+#define	OCOTP_VERSION_MAJOR_OFFSET		24
+#define	OCOTP_VERSION_MINOR_MASK		(0xff << 16)
+#define	OCOTP_VERSION_MINOR_OFFSET		16
+#define	OCOTP_VERSION_STEP_MASK			0xffff
+#define	OCOTP_VERSION_STEP_OFFSET		0
+
+#endif /* __MX28_REGS_OCOTP_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
new file mode 100644
index 0000000..134d436
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
@@ -0,0 +1,1270 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 PINCTRL Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __MX28_REGS_PINCTRL_H__
+#define __MX28_REGS_PINCTRL_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_pinctrl_regs {
+	mxs_reg_32(hw_pinctrl_ctrl)		/* 0x0 */
+
+	uint32_t	reserved1[60];
+
+	mxs_reg_32(hw_pinctrl_muxsel0)		/* 0x100 */
+	mxs_reg_32(hw_pinctrl_muxsel1)		/* 0x110 */
+	mxs_reg_32(hw_pinctrl_muxsel2)		/* 0x120 */
+	mxs_reg_32(hw_pinctrl_muxsel3)		/* 0x130 */
+	mxs_reg_32(hw_pinctrl_muxsel4)		/* 0x140 */
+	mxs_reg_32(hw_pinctrl_muxsel5)		/* 0x150 */
+	mxs_reg_32(hw_pinctrl_muxsel6)		/* 0x160 */
+	mxs_reg_32(hw_pinctrl_muxsel7)		/* 0x170 */
+	mxs_reg_32(hw_pinctrl_muxsel8)		/* 0x180 */
+	mxs_reg_32(hw_pinctrl_muxsel9)		/* 0x190 */
+	mxs_reg_32(hw_pinctrl_muxsel10)	/* 0x1a0 */
+	mxs_reg_32(hw_pinctrl_muxsel11)	/* 0x1b0 */
+	mxs_reg_32(hw_pinctrl_muxsel12)	/* 0x1c0 */
+	mxs_reg_32(hw_pinctrl_muxsel13)	/* 0x1d0 */
+
+	uint32_t	reserved2[72];
+
+	mxs_reg_32(hw_pinctrl_drive0)		/* 0x300 */
+	mxs_reg_32(hw_pinctrl_drive1)		/* 0x310 */
+	mxs_reg_32(hw_pinctrl_drive2)		/* 0x320 */
+	mxs_reg_32(hw_pinctrl_drive3)		/* 0x330 */
+	mxs_reg_32(hw_pinctrl_drive4)		/* 0x340 */
+	mxs_reg_32(hw_pinctrl_drive5)		/* 0x350 */
+	mxs_reg_32(hw_pinctrl_drive6)		/* 0x360 */
+	mxs_reg_32(hw_pinctrl_drive7)		/* 0x370 */
+	mxs_reg_32(hw_pinctrl_drive8)		/* 0x380 */
+	mxs_reg_32(hw_pinctrl_drive9)		/* 0x390 */
+	mxs_reg_32(hw_pinctrl_drive10)		/* 0x3a0 */
+	mxs_reg_32(hw_pinctrl_drive11)		/* 0x3b0 */
+	mxs_reg_32(hw_pinctrl_drive12)		/* 0x3c0 */
+	mxs_reg_32(hw_pinctrl_drive13)		/* 0x3d0 */
+	mxs_reg_32(hw_pinctrl_drive14)		/* 0x3e0 */
+	mxs_reg_32(hw_pinctrl_drive15)		/* 0x3f0 */
+	mxs_reg_32(hw_pinctrl_drive16)		/* 0x400 */
+	mxs_reg_32(hw_pinctrl_drive17)		/* 0x410 */
+	mxs_reg_32(hw_pinctrl_drive18)		/* 0x420 */
+	mxs_reg_32(hw_pinctrl_drive19)		/* 0x430 */
+
+	uint32_t	reserved3[112];
+
+	mxs_reg_32(hw_pinctrl_pull0)		/* 0x600 */
+	mxs_reg_32(hw_pinctrl_pull1)		/* 0x610 */
+	mxs_reg_32(hw_pinctrl_pull2)		/* 0x620 */
+	mxs_reg_32(hw_pinctrl_pull3)		/* 0x630 */
+	mxs_reg_32(hw_pinctrl_pull4)		/* 0x640 */
+	mxs_reg_32(hw_pinctrl_pull5)		/* 0x650 */
+	mxs_reg_32(hw_pinctrl_pull6)		/* 0x660 */
+
+	uint32_t	reserved4[36];
+
+	mxs_reg_32(hw_pinctrl_dout0)		/* 0x700 */
+	mxs_reg_32(hw_pinctrl_dout1)		/* 0x710 */
+	mxs_reg_32(hw_pinctrl_dout2)		/* 0x720 */
+	mxs_reg_32(hw_pinctrl_dout3)		/* 0x730 */
+	mxs_reg_32(hw_pinctrl_dout4)		/* 0x740 */
+
+	uint32_t	reserved5[108];
+
+	mxs_reg_32(hw_pinctrl_din0)		/* 0x900 */
+	mxs_reg_32(hw_pinctrl_din1)		/* 0x910 */
+	mxs_reg_32(hw_pinctrl_din2)		/* 0x920 */
+	mxs_reg_32(hw_pinctrl_din3)		/* 0x930 */
+	mxs_reg_32(hw_pinctrl_din4)		/* 0x940 */
+
+	uint32_t	reserved6[108];
+
+	mxs_reg_32(hw_pinctrl_doe0)		/* 0xb00 */
+	mxs_reg_32(hw_pinctrl_doe1)		/* 0xb10 */
+	mxs_reg_32(hw_pinctrl_doe2)		/* 0xb20 */
+	mxs_reg_32(hw_pinctrl_doe3)		/* 0xb30 */
+	mxs_reg_32(hw_pinctrl_doe4)		/* 0xb40 */
+
+	uint32_t	reserved7[300];
+
+	mxs_reg_32(hw_pinctrl_pin2irq0)	/* 0x1000 */
+	mxs_reg_32(hw_pinctrl_pin2irq1)	/* 0x1010 */
+	mxs_reg_32(hw_pinctrl_pin2irq2)	/* 0x1020 */
+	mxs_reg_32(hw_pinctrl_pin2irq3)	/* 0x1030 */
+	mxs_reg_32(hw_pinctrl_pin2irq4)	/* 0x1040 */
+
+	uint32_t	reserved8[44];
+
+	mxs_reg_32(hw_pinctrl_irqen0)		/* 0x1100 */
+	mxs_reg_32(hw_pinctrl_irqen1)		/* 0x1110 */
+	mxs_reg_32(hw_pinctrl_irqen2)		/* 0x1120 */
+	mxs_reg_32(hw_pinctrl_irqen3)		/* 0x1130 */
+	mxs_reg_32(hw_pinctrl_irqen4)		/* 0x1140 */
+
+	uint32_t	reserved9[44];
+
+	mxs_reg_32(hw_pinctrl_irqlevel0)	/* 0x1200 */
+	mxs_reg_32(hw_pinctrl_irqlevel1)	/* 0x1210 */
+	mxs_reg_32(hw_pinctrl_irqlevel2)	/* 0x1220 */
+	mxs_reg_32(hw_pinctrl_irqlevel3)	/* 0x1230 */
+	mxs_reg_32(hw_pinctrl_irqlevel4)	/* 0x1240 */
+
+	uint32_t	reserved10[44];
+
+	mxs_reg_32(hw_pinctrl_irqpol0)		/* 0x1300 */
+	mxs_reg_32(hw_pinctrl_irqpol1)		/* 0x1310 */
+	mxs_reg_32(hw_pinctrl_irqpol2)		/* 0x1320 */
+	mxs_reg_32(hw_pinctrl_irqpol3)		/* 0x1330 */
+	mxs_reg_32(hw_pinctrl_irqpol4)		/* 0x1340 */
+
+	uint32_t	reserved11[44];
+
+	mxs_reg_32(hw_pinctrl_irqstat0)	/* 0x1400 */
+	mxs_reg_32(hw_pinctrl_irqstat1)	/* 0x1410 */
+	mxs_reg_32(hw_pinctrl_irqstat2)	/* 0x1420 */
+	mxs_reg_32(hw_pinctrl_irqstat3)	/* 0x1430 */
+	mxs_reg_32(hw_pinctrl_irqstat4)	/* 0x1440 */
+
+	uint32_t	reserved12[380];
+
+	mxs_reg_32(hw_pinctrl_emi_odt_ctrl)	/* 0x1a40 */
+
+	uint32_t	reserved13[76];
+
+	mxs_reg_32(hw_pinctrl_emi_ds_ctrl)	/* 0x1b80 */
+};
+#endif
+
+#define	PINCTRL_CTRL_SFTRST				(1 << 31)
+#define	PINCTRL_CTRL_CLKGATE				(1 << 30)
+#define	PINCTRL_CTRL_PRESENT4				(1 << 24)
+#define	PINCTRL_CTRL_PRESENT3				(1 << 23)
+#define	PINCTRL_CTRL_PRESENT2				(1 << 22)
+#define	PINCTRL_CTRL_PRESENT1				(1 << 21)
+#define	PINCTRL_CTRL_PRESENT0				(1 << 20)
+#define	PINCTRL_CTRL_IRQOUT4				(1 << 4)
+#define	PINCTRL_CTRL_IRQOUT3				(1 << 3)
+#define	PINCTRL_CTRL_IRQOUT2				(1 << 2)
+#define	PINCTRL_CTRL_IRQOUT1				(1 << 1)
+#define	PINCTRL_CTRL_IRQOUT0				(1 << 0)
+
+#define	PINCTRL_MUXSEL0_BANK0_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL0_BANK0_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL0_BANK0_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL0_BANK0_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL0_BANK0_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL0_BANK0_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL0_BANK0_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL0_BANK0_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL1_BANK0_PIN28_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET		24
+#define	PINCTRL_MUXSEL1_BANK0_PIN27_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET		22
+#define	PINCTRL_MUXSEL1_BANK0_PIN26_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET		20
+#define	PINCTRL_MUXSEL1_BANK0_PIN25_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET		18
+#define	PINCTRL_MUXSEL1_BANK0_PIN24_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET		16
+#define	PINCTRL_MUXSEL1_BANK0_PIN23_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET		14
+#define	PINCTRL_MUXSEL1_BANK0_PIN22_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET		12
+#define	PINCTRL_MUXSEL1_BANK0_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL1_BANK0_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL1_BANK0_PIN19_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET		6
+#define	PINCTRL_MUXSEL1_BANK0_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL1_BANK0_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL1_BANK0_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL2_BANK1_PIN15_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET		30
+#define	PINCTRL_MUXSEL2_BANK1_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL2_BANK1_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL2_BANK1_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL2_BANK1_PIN11_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET		22
+#define	PINCTRL_MUXSEL2_BANK1_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL2_BANK1_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL2_BANK1_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL2_BANK1_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL2_BANK1_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL2_BANK1_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL2_BANK1_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL2_BANK1_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL2_BANK1_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL2_BANK1_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL2_BANK1_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL3_BANK1_PIN31_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET		30
+#define	PINCTRL_MUXSEL3_BANK1_PIN30_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET		28
+#define	PINCTRL_MUXSEL3_BANK1_PIN29_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET		26
+#define	PINCTRL_MUXSEL3_BANK1_PIN28_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET		24
+#define	PINCTRL_MUXSEL3_BANK1_PIN27_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET		22
+#define	PINCTRL_MUXSEL3_BANK1_PIN26_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET		20
+#define	PINCTRL_MUXSEL3_BANK1_PIN25_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET		18
+#define	PINCTRL_MUXSEL3_BANK1_PIN24_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET		16
+#define	PINCTRL_MUXSEL3_BANK1_PIN23_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET		14
+#define	PINCTRL_MUXSEL3_BANK1_PIN22_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET		12
+#define	PINCTRL_MUXSEL3_BANK1_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL3_BANK1_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL3_BANK1_PIN19_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET		6
+#define	PINCTRL_MUXSEL3_BANK1_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL3_BANK1_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL3_BANK1_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL4_BANK2_PIN15_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET		30
+#define	PINCTRL_MUXSEL4_BANK2_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL4_BANK2_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL4_BANK2_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL4_BANK2_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL4_BANK2_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL4_BANK2_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL4_BANK2_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL4_BANK2_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL4_BANK2_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL4_BANK2_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL4_BANK2_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL4_BANK2_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL4_BANK2_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL4_BANK2_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL5_BANK2_PIN27_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET		22
+#define	PINCTRL_MUXSEL5_BANK2_PIN26_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET		20
+#define	PINCTRL_MUXSEL5_BANK2_PIN25_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET		18
+#define	PINCTRL_MUXSEL5_BANK2_PIN24_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET		16
+#define	PINCTRL_MUXSEL5_BANK2_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL5_BANK2_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL5_BANK2_PIN19_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET		6
+#define	PINCTRL_MUXSEL5_BANK2_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL5_BANK2_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL5_BANK2_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL6_BANK3_PIN15_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET		30
+#define	PINCTRL_MUXSEL6_BANK3_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL6_BANK3_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL6_BANK3_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL6_BANK3_PIN11_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET		22
+#define	PINCTRL_MUXSEL6_BANK3_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL6_BANK3_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL6_BANK3_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL6_BANK3_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL6_BANK3_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL6_BANK3_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL6_BANK3_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL6_BANK3_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL6_BANK3_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL6_BANK3_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL6_BANK3_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL7_BANK3_PIN30_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET		28
+#define	PINCTRL_MUXSEL7_BANK3_PIN29_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET		26
+#define	PINCTRL_MUXSEL7_BANK3_PIN28_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET		24
+#define	PINCTRL_MUXSEL7_BANK3_PIN27_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET		22
+#define	PINCTRL_MUXSEL7_BANK3_PIN26_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET		20
+#define	PINCTRL_MUXSEL7_BANK3_PIN25_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET		18
+#define	PINCTRL_MUXSEL7_BANK3_PIN24_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET		16
+#define	PINCTRL_MUXSEL7_BANK3_PIN23_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET		14
+#define	PINCTRL_MUXSEL7_BANK3_PIN22_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET		12
+#define	PINCTRL_MUXSEL7_BANK3_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL7_BANK3_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL7_BANK3_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL7_BANK3_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL7_BANK3_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL8_BANK4_PIN15_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET		30
+#define	PINCTRL_MUXSEL8_BANK4_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL8_BANK4_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL8_BANK4_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL8_BANK4_PIN11_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET		22
+#define	PINCTRL_MUXSEL8_BANK4_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL8_BANK4_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL8_BANK4_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL8_BANK4_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL8_BANK4_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL8_BANK4_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL8_BANK4_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL8_BANK4_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL8_BANK4_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL8_BANK4_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL8_BANK4_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL9_BANK4_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL9_BANK4_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL10_BANK5_PIN15_MASK		(0x3 << 30)
+#define	PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET		30
+#define	PINCTRL_MUXSEL10_BANK5_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL10_BANK5_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL10_BANK5_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL10_BANK5_PIN11_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET		22
+#define	PINCTRL_MUXSEL10_BANK5_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL10_BANK5_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL10_BANK5_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL10_BANK5_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL10_BANK5_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL10_BANK5_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL10_BANK5_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL10_BANK5_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL10_BANK5_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL10_BANK5_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL10_BANK5_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL11_BANK5_PIN26_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET		20
+#define	PINCTRL_MUXSEL11_BANK5_PIN23_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET		14
+#define	PINCTRL_MUXSEL11_BANK5_PIN22_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET		12
+#define	PINCTRL_MUXSEL11_BANK5_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL11_BANK5_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL11_BANK5_PIN19_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET		6
+#define	PINCTRL_MUXSEL11_BANK5_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL11_BANK5_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL11_BANK5_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET		0
+
+#define	PINCTRL_MUXSEL12_BANK6_PIN14_MASK		(0x3 << 28)
+#define	PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET		28
+#define	PINCTRL_MUXSEL12_BANK6_PIN13_MASK		(0x3 << 26)
+#define	PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET		26
+#define	PINCTRL_MUXSEL12_BANK6_PIN12_MASK		(0x3 << 24)
+#define	PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET		24
+#define	PINCTRL_MUXSEL12_BANK6_PIN11_MASK		(0x3 << 22)
+#define	PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET		22
+#define	PINCTRL_MUXSEL12_BANK6_PIN10_MASK		(0x3 << 20)
+#define	PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET		20
+#define	PINCTRL_MUXSEL12_BANK6_PIN09_MASK		(0x3 << 18)
+#define	PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET		18
+#define	PINCTRL_MUXSEL12_BANK6_PIN08_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET		16
+#define	PINCTRL_MUXSEL12_BANK6_PIN07_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET		14
+#define	PINCTRL_MUXSEL12_BANK6_PIN06_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET		12
+#define	PINCTRL_MUXSEL12_BANK6_PIN05_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET		10
+#define	PINCTRL_MUXSEL12_BANK6_PIN04_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET		8
+#define	PINCTRL_MUXSEL12_BANK6_PIN03_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET		6
+#define	PINCTRL_MUXSEL12_BANK6_PIN02_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET		4
+#define	PINCTRL_MUXSEL12_BANK6_PIN01_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET		2
+#define	PINCTRL_MUXSEL12_BANK6_PIN00_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET		0
+
+#define	PINCTRL_MUXSEL13_BANK6_PIN24_MASK		(0x3 << 16)
+#define	PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET		16
+#define	PINCTRL_MUXSEL13_BANK6_PIN23_MASK		(0x3 << 14)
+#define	PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET		14
+#define	PINCTRL_MUXSEL13_BANK6_PIN22_MASK		(0x3 << 12)
+#define	PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET		12
+#define	PINCTRL_MUXSEL13_BANK6_PIN21_MASK		(0x3 << 10)
+#define	PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET		10
+#define	PINCTRL_MUXSEL13_BANK6_PIN20_MASK		(0x3 << 8)
+#define	PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET		8
+#define	PINCTRL_MUXSEL13_BANK6_PIN19_MASK		(0x3 << 6)
+#define	PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET		6
+#define	PINCTRL_MUXSEL13_BANK6_PIN18_MASK		(0x3 << 4)
+#define	PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET		4
+#define	PINCTRL_MUXSEL13_BANK6_PIN17_MASK		(0x3 << 2)
+#define	PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET		2
+#define	PINCTRL_MUXSEL13_BANK6_PIN16_MASK		(0x3 << 0)
+#define	PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET		0
+
+#define	PINCTRL_DRIVE0_BANK0_PIN07_V			(1 << 30)
+#define	PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET		28
+#define	PINCTRL_DRIVE0_BANK0_PIN06_V			(1 << 26)
+#define	PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET		24
+#define	PINCTRL_DRIVE0_BANK0_PIN05_V			(1 << 22)
+#define	PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET		20
+#define	PINCTRL_DRIVE0_BANK0_PIN04_V			(1 << 18)
+#define	PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET		16
+#define	PINCTRL_DRIVE0_BANK0_PIN03_V			(1 << 14)
+#define	PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET		12
+#define	PINCTRL_DRIVE0_BANK0_PIN02_V			(1 << 10)
+#define	PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET		8
+#define	PINCTRL_DRIVE0_BANK0_PIN01_V			(1 << 6)
+#define	PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET		4
+#define	PINCTRL_DRIVE0_BANK0_PIN00_V			(1 << 2)
+#define	PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE2_BANK0_PIN23_V			(1 << 30)
+#define	PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET		28
+#define	PINCTRL_DRIVE2_BANK0_PIN22_V			(1 << 26)
+#define	PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET		24
+#define	PINCTRL_DRIVE2_BANK0_PIN21_V			(1 << 22)
+#define	PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET		20
+#define	PINCTRL_DRIVE2_BANK0_PIN20_V			(1 << 18)
+#define	PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET		16
+#define	PINCTRL_DRIVE2_BANK0_PIN19_V			(1 << 14)
+#define	PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET		12
+#define	PINCTRL_DRIVE2_BANK0_PIN18_V			(1 << 10)
+#define	PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET		8
+#define	PINCTRL_DRIVE2_BANK0_PIN17_V			(1 << 6)
+#define	PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET		4
+#define	PINCTRL_DRIVE2_BANK0_PIN16_V			(1 << 2)
+#define	PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE3_BANK0_PIN28_V			(1 << 18)
+#define	PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET		16
+#define	PINCTRL_DRIVE3_BANK0_PIN27_V			(1 << 14)
+#define	PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET		12
+#define	PINCTRL_DRIVE3_BANK0_PIN26_V			(1 << 10)
+#define	PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET		8
+#define	PINCTRL_DRIVE3_BANK0_PIN25_V			(1 << 6)
+#define	PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET		4
+#define	PINCTRL_DRIVE3_BANK0_PIN24_V			(1 << 2)
+#define	PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE4_BANK1_PIN07_V			(1 << 30)
+#define	PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET		28
+#define	PINCTRL_DRIVE4_BANK1_PIN06_V			(1 << 26)
+#define	PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET		24
+#define	PINCTRL_DRIVE4_BANK1_PIN05_V			(1 << 22)
+#define	PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET		20
+#define	PINCTRL_DRIVE4_BANK1_PIN04_V			(1 << 18)
+#define	PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET		16
+#define	PINCTRL_DRIVE4_BANK1_PIN03_V			(1 << 14)
+#define	PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET		12
+#define	PINCTRL_DRIVE4_BANK1_PIN02_V			(1 << 10)
+#define	PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET		8
+#define	PINCTRL_DRIVE4_BANK1_PIN01_V			(1 << 6)
+#define	PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET		4
+#define	PINCTRL_DRIVE4_BANK1_PIN00_V			(1 << 2)
+#define	PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE5_BANK1_PIN15_V			(1 << 30)
+#define	PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET		28
+#define	PINCTRL_DRIVE5_BANK1_PIN14_V			(1 << 26)
+#define	PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET		24
+#define	PINCTRL_DRIVE5_BANK1_PIN13_V			(1 << 22)
+#define	PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET		20
+#define	PINCTRL_DRIVE5_BANK1_PIN12_V			(1 << 18)
+#define	PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET		16
+#define	PINCTRL_DRIVE5_BANK1_PIN11_V			(1 << 14)
+#define	PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET		12
+#define	PINCTRL_DRIVE5_BANK1_PIN10_V			(1 << 10)
+#define	PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET		8
+#define	PINCTRL_DRIVE5_BANK1_PIN09_V			(1 << 6)
+#define	PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET		4
+#define	PINCTRL_DRIVE5_BANK1_PIN08_V			(1 << 2)
+#define	PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE6_BANK1_PIN23_V			(1 << 30)
+#define	PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET		28
+#define	PINCTRL_DRIVE6_BANK1_PIN22_V			(1 << 26)
+#define	PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET		24
+#define	PINCTRL_DRIVE6_BANK1_PIN21_V			(1 << 22)
+#define	PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET		20
+#define	PINCTRL_DRIVE6_BANK1_PIN20_V			(1 << 18)
+#define	PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET		16
+#define	PINCTRL_DRIVE6_BANK1_PIN19_V			(1 << 14)
+#define	PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET		12
+#define	PINCTRL_DRIVE6_BANK1_PIN18_V			(1 << 10)
+#define	PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET		8
+#define	PINCTRL_DRIVE6_BANK1_PIN17_V			(1 << 6)
+#define	PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET		4
+#define	PINCTRL_DRIVE6_BANK1_PIN16_V			(1 << 2)
+#define	PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE7_BANK1_PIN31_V			(1 << 30)
+#define	PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET		28
+#define	PINCTRL_DRIVE7_BANK1_PIN30_V			(1 << 26)
+#define	PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET		24
+#define	PINCTRL_DRIVE7_BANK1_PIN29_V			(1 << 22)
+#define	PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET		20
+#define	PINCTRL_DRIVE7_BANK1_PIN28_V			(1 << 18)
+#define	PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET		16
+#define	PINCTRL_DRIVE7_BANK1_PIN27_V			(1 << 14)
+#define	PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET		12
+#define	PINCTRL_DRIVE7_BANK1_PIN26_V			(1 << 10)
+#define	PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET		8
+#define	PINCTRL_DRIVE7_BANK1_PIN25_V			(1 << 6)
+#define	PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET		4
+#define	PINCTRL_DRIVE7_BANK1_PIN24_V			(1 << 2)
+#define	PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE8_BANK2_PIN07_V			(1 << 30)
+#define	PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET		28
+#define	PINCTRL_DRIVE8_BANK2_PIN06_V			(1 << 26)
+#define	PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET		24
+#define	PINCTRL_DRIVE8_BANK2_PIN05_V			(1 << 22)
+#define	PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET		20
+#define	PINCTRL_DRIVE8_BANK2_PIN04_V			(1 << 18)
+#define	PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET		16
+#define	PINCTRL_DRIVE8_BANK2_PIN03_V			(1 << 14)
+#define	PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET		12
+#define	PINCTRL_DRIVE8_BANK2_PIN02_V			(1 << 10)
+#define	PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET		8
+#define	PINCTRL_DRIVE8_BANK2_PIN01_V			(1 << 6)
+#define	PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET		4
+#define	PINCTRL_DRIVE8_BANK2_PIN00_V			(1 << 2)
+#define	PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE9_BANK2_PIN15_V			(1 << 30)
+#define	PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET		28
+#define	PINCTRL_DRIVE9_BANK2_PIN14_V			(1 << 26)
+#define	PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET		24
+#define	PINCTRL_DRIVE9_BANK2_PIN13_V			(1 << 22)
+#define	PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET		20
+#define	PINCTRL_DRIVE9_BANK2_PIN12_V			(1 << 18)
+#define	PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET		16
+#define	PINCTRL_DRIVE9_BANK2_PIN10_V			(1 << 10)
+#define	PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET		8
+#define	PINCTRL_DRIVE9_BANK2_PIN09_V			(1 << 6)
+#define	PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET		4
+#define	PINCTRL_DRIVE9_BANK2_PIN08_V			(1 << 2)
+#define	PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE10_BANK2_PIN21_V			(1 << 22)
+#define	PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET		20
+#define	PINCTRL_DRIVE10_BANK2_PIN20_V			(1 << 18)
+#define	PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET		16
+#define	PINCTRL_DRIVE10_BANK2_PIN19_V			(1 << 14)
+#define	PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET		12
+#define	PINCTRL_DRIVE10_BANK2_PIN18_V			(1 << 10)
+#define	PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET		8
+#define	PINCTRL_DRIVE10_BANK2_PIN17_V			(1 << 6)
+#define	PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET		4
+#define	PINCTRL_DRIVE10_BANK2_PIN16_V			(1 << 2)
+#define	PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE11_BANK2_PIN27_V			(1 << 14)
+#define	PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET		12
+#define	PINCTRL_DRIVE11_BANK2_PIN26_V			(1 << 10)
+#define	PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET		8
+#define	PINCTRL_DRIVE11_BANK2_PIN25_V			(1 << 6)
+#define	PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET		4
+#define	PINCTRL_DRIVE11_BANK2_PIN24_V			(1 << 2)
+#define	PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE12_BANK3_PIN07_V			(1 << 30)
+#define	PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET		28
+#define	PINCTRL_DRIVE12_BANK3_PIN06_V			(1 << 26)
+#define	PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET		24
+#define	PINCTRL_DRIVE12_BANK3_PIN05_V			(1 << 22)
+#define	PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET		20
+#define	PINCTRL_DRIVE12_BANK3_PIN04_V			(1 << 18)
+#define	PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET		16
+#define	PINCTRL_DRIVE12_BANK3_PIN03_V			(1 << 14)
+#define	PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET		12
+#define	PINCTRL_DRIVE12_BANK3_PIN02_V			(1 << 10)
+#define	PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET		8
+#define	PINCTRL_DRIVE12_BANK3_PIN01_V			(1 << 6)
+#define	PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET		4
+#define	PINCTRL_DRIVE12_BANK3_PIN00_V			(1 << 2)
+#define	PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE13_BANK3_PIN15_V			(1 << 30)
+#define	PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET		28
+#define	PINCTRL_DRIVE13_BANK3_PIN14_V			(1 << 26)
+#define	PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET		24
+#define	PINCTRL_DRIVE13_BANK3_PIN13_V			(1 << 22)
+#define	PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET		20
+#define	PINCTRL_DRIVE13_BANK3_PIN12_V			(1 << 18)
+#define	PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET		16
+#define	PINCTRL_DRIVE13_BANK3_PIN11_V			(1 << 14)
+#define	PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET		12
+#define	PINCTRL_DRIVE13_BANK3_PIN10_V			(1 << 10)
+#define	PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET		8
+#define	PINCTRL_DRIVE13_BANK3_PIN09_V			(1 << 6)
+#define	PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET		4
+#define	PINCTRL_DRIVE13_BANK3_PIN08_V			(1 << 2)
+#define	PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE14_BANK3_PIN23_V			(1 << 30)
+#define	PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET		28
+#define	PINCTRL_DRIVE14_BANK3_PIN22_V			(1 << 26)
+#define	PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET		24
+#define	PINCTRL_DRIVE14_BANK3_PIN21_V			(1 << 22)
+#define	PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET		20
+#define	PINCTRL_DRIVE14_BANK3_PIN20_V			(1 << 18)
+#define	PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET		16
+#define	PINCTRL_DRIVE14_BANK3_PIN18_V			(1 << 10)
+#define	PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET		8
+#define	PINCTRL_DRIVE14_BANK3_PIN17_V			(1 << 6)
+#define	PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET		4
+#define	PINCTRL_DRIVE14_BANK3_PIN16_V			(1 << 2)
+#define	PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE15_BANK3_PIN30_V			(1 << 26)
+#define	PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET		24
+#define	PINCTRL_DRIVE15_BANK3_PIN29_V			(1 << 22)
+#define	PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET		20
+#define	PINCTRL_DRIVE15_BANK3_PIN28_V			(1 << 18)
+#define	PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET		16
+#define	PINCTRL_DRIVE15_BANK3_PIN27_V			(1 << 14)
+#define	PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET		12
+#define	PINCTRL_DRIVE15_BANK3_PIN26_V			(1 << 10)
+#define	PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET		8
+#define	PINCTRL_DRIVE15_BANK3_PIN25_V			(1 << 6)
+#define	PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET		4
+#define	PINCTRL_DRIVE15_BANK3_PIN24_V			(1 << 2)
+#define	PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE16_BANK4_PIN07_V			(1 << 30)
+#define	PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET		28
+#define	PINCTRL_DRIVE16_BANK4_PIN06_V			(1 << 26)
+#define	PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET		24
+#define	PINCTRL_DRIVE16_BANK4_PIN05_V			(1 << 22)
+#define	PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET		20
+#define	PINCTRL_DRIVE16_BANK4_PIN04_V			(1 << 18)
+#define	PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET		16
+#define	PINCTRL_DRIVE16_BANK4_PIN03_V			(1 << 14)
+#define	PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET		12
+#define	PINCTRL_DRIVE16_BANK4_PIN02_V			(1 << 10)
+#define	PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET		8
+#define	PINCTRL_DRIVE16_BANK4_PIN01_V			(1 << 6)
+#define	PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET		4
+#define	PINCTRL_DRIVE16_BANK4_PIN00_V			(1 << 2)
+#define	PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE17_BANK4_PIN15_V			(1 << 30)
+#define	PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK		(0x3 << 28)
+#define	PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET		28
+#define	PINCTRL_DRIVE17_BANK4_PIN14_V			(1 << 26)
+#define	PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK		(0x3 << 24)
+#define	PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET		24
+#define	PINCTRL_DRIVE17_BANK4_PIN13_V			(1 << 22)
+#define	PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK		(0x3 << 20)
+#define	PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET		20
+#define	PINCTRL_DRIVE17_BANK4_PIN12_V			(1 << 18)
+#define	PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET		16
+#define	PINCTRL_DRIVE17_BANK4_PIN11_V			(1 << 14)
+#define	PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK		(0x3 << 12)
+#define	PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET		12
+#define	PINCTRL_DRIVE17_BANK4_PIN10_V			(1 << 10)
+#define	PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK		(0x3 << 8)
+#define	PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET		8
+#define	PINCTRL_DRIVE17_BANK4_PIN09_V			(1 << 6)
+#define	PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK		(0x3 << 4)
+#define	PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET		4
+#define	PINCTRL_DRIVE17_BANK4_PIN08_V			(1 << 2)
+#define	PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET		0
+
+#define	PINCTRL_DRIVE18_BANK4_PIN20_V			(1 << 18)
+#define	PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK		(0x3 << 16)
+#define	PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET		16
+#define	PINCTRL_DRIVE18_BANK4_PIN16_V			(1 << 2)
+#define	PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK		(0x3 << 0)
+#define	PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET		0
+
+#define	PINCTRL_PULL0_BANK0_PIN28			(1 << 28)
+#define	PINCTRL_PULL0_BANK0_PIN27			(1 << 27)
+#define	PINCTRL_PULL0_BANK0_PIN26			(1 << 26)
+#define	PINCTRL_PULL0_BANK0_PIN25			(1 << 25)
+#define	PINCTRL_PULL0_BANK0_PIN24			(1 << 24)
+#define	PINCTRL_PULL0_BANK0_PIN23			(1 << 23)
+#define	PINCTRL_PULL0_BANK0_PIN22			(1 << 22)
+#define	PINCTRL_PULL0_BANK0_PIN21			(1 << 21)
+#define	PINCTRL_PULL0_BANK0_PIN20			(1 << 20)
+#define	PINCTRL_PULL0_BANK0_PIN19			(1 << 19)
+#define	PINCTRL_PULL0_BANK0_PIN18			(1 << 18)
+#define	PINCTRL_PULL0_BANK0_PIN17			(1 << 17)
+#define	PINCTRL_PULL0_BANK0_PIN16			(1 << 16)
+#define	PINCTRL_PULL0_BANK0_PIN07			(1 << 7)
+#define	PINCTRL_PULL0_BANK0_PIN06			(1 << 6)
+#define	PINCTRL_PULL0_BANK0_PIN05			(1 << 5)
+#define	PINCTRL_PULL0_BANK0_PIN04			(1 << 4)
+#define	PINCTRL_PULL0_BANK0_PIN03			(1 << 3)
+#define	PINCTRL_PULL0_BANK0_PIN02			(1 << 2)
+#define	PINCTRL_PULL0_BANK0_PIN01			(1 << 1)
+#define	PINCTRL_PULL0_BANK0_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL1_BANK1_PIN31			(1 << 31)
+#define	PINCTRL_PULL1_BANK1_PIN30			(1 << 30)
+#define	PINCTRL_PULL1_BANK1_PIN29			(1 << 29)
+#define	PINCTRL_PULL1_BANK1_PIN28			(1 << 28)
+#define	PINCTRL_PULL1_BANK1_PIN27			(1 << 27)
+#define	PINCTRL_PULL1_BANK1_PIN26			(1 << 26)
+#define	PINCTRL_PULL1_BANK1_PIN25			(1 << 25)
+#define	PINCTRL_PULL1_BANK1_PIN24			(1 << 24)
+#define	PINCTRL_PULL1_BANK1_PIN23			(1 << 23)
+#define	PINCTRL_PULL1_BANK1_PIN22			(1 << 22)
+#define	PINCTRL_PULL1_BANK1_PIN21			(1 << 21)
+#define	PINCTRL_PULL1_BANK1_PIN20			(1 << 20)
+#define	PINCTRL_PULL1_BANK1_PIN19			(1 << 19)
+#define	PINCTRL_PULL1_BANK1_PIN18			(1 << 18)
+#define	PINCTRL_PULL1_BANK1_PIN17			(1 << 17)
+#define	PINCTRL_PULL1_BANK1_PIN16			(1 << 16)
+#define	PINCTRL_PULL1_BANK1_PIN15			(1 << 15)
+#define	PINCTRL_PULL1_BANK1_PIN14			(1 << 14)
+#define	PINCTRL_PULL1_BANK1_PIN13			(1 << 13)
+#define	PINCTRL_PULL1_BANK1_PIN12			(1 << 12)
+#define	PINCTRL_PULL1_BANK1_PIN11			(1 << 11)
+#define	PINCTRL_PULL1_BANK1_PIN10			(1 << 10)
+#define	PINCTRL_PULL1_BANK1_PIN09			(1 << 9)
+#define	PINCTRL_PULL1_BANK1_PIN08			(1 << 8)
+#define	PINCTRL_PULL1_BANK1_PIN07			(1 << 7)
+#define	PINCTRL_PULL1_BANK1_PIN06			(1 << 6)
+#define	PINCTRL_PULL1_BANK1_PIN05			(1 << 5)
+#define	PINCTRL_PULL1_BANK1_PIN04			(1 << 4)
+#define	PINCTRL_PULL1_BANK1_PIN03			(1 << 3)
+#define	PINCTRL_PULL1_BANK1_PIN02			(1 << 2)
+#define	PINCTRL_PULL1_BANK1_PIN01			(1 << 1)
+#define	PINCTRL_PULL1_BANK1_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL2_BANK2_PIN27			(1 << 27)
+#define	PINCTRL_PULL2_BANK2_PIN26			(1 << 26)
+#define	PINCTRL_PULL2_BANK2_PIN25			(1 << 25)
+#define	PINCTRL_PULL2_BANK2_PIN24			(1 << 24)
+#define	PINCTRL_PULL2_BANK2_PIN21			(1 << 21)
+#define	PINCTRL_PULL2_BANK2_PIN20			(1 << 20)
+#define	PINCTRL_PULL2_BANK2_PIN19			(1 << 19)
+#define	PINCTRL_PULL2_BANK2_PIN18			(1 << 18)
+#define	PINCTRL_PULL2_BANK2_PIN17			(1 << 17)
+#define	PINCTRL_PULL2_BANK2_PIN16			(1 << 16)
+#define	PINCTRL_PULL2_BANK2_PIN15			(1 << 15)
+#define	PINCTRL_PULL2_BANK2_PIN14			(1 << 14)
+#define	PINCTRL_PULL2_BANK2_PIN13			(1 << 13)
+#define	PINCTRL_PULL2_BANK2_PIN12			(1 << 12)
+#define	PINCTRL_PULL2_BANK2_PIN10			(1 << 10)
+#define	PINCTRL_PULL2_BANK2_PIN09			(1 << 9)
+#define	PINCTRL_PULL2_BANK2_PIN08			(1 << 8)
+#define	PINCTRL_PULL2_BANK2_PIN07			(1 << 7)
+#define	PINCTRL_PULL2_BANK2_PIN06			(1 << 6)
+#define	PINCTRL_PULL2_BANK2_PIN05			(1 << 5)
+#define	PINCTRL_PULL2_BANK2_PIN04			(1 << 4)
+#define	PINCTRL_PULL2_BANK2_PIN03			(1 << 3)
+#define	PINCTRL_PULL2_BANK2_PIN02			(1 << 2)
+#define	PINCTRL_PULL2_BANK2_PIN01			(1 << 1)
+#define	PINCTRL_PULL2_BANK2_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL3_BANK3_PIN30			(1 << 30)
+#define	PINCTRL_PULL3_BANK3_PIN29			(1 << 29)
+#define	PINCTRL_PULL3_BANK3_PIN28			(1 << 28)
+#define	PINCTRL_PULL3_BANK3_PIN27			(1 << 27)
+#define	PINCTRL_PULL3_BANK3_PIN26			(1 << 26)
+#define	PINCTRL_PULL3_BANK3_PIN25			(1 << 25)
+#define	PINCTRL_PULL3_BANK3_PIN24			(1 << 24)
+#define	PINCTRL_PULL3_BANK3_PIN23			(1 << 23)
+#define	PINCTRL_PULL3_BANK3_PIN22			(1 << 22)
+#define	PINCTRL_PULL3_BANK3_PIN21			(1 << 21)
+#define	PINCTRL_PULL3_BANK3_PIN20			(1 << 20)
+#define	PINCTRL_PULL3_BANK3_PIN18			(1 << 18)
+#define	PINCTRL_PULL3_BANK3_PIN17			(1 << 17)
+#define	PINCTRL_PULL3_BANK3_PIN16			(1 << 16)
+#define	PINCTRL_PULL3_BANK3_PIN15			(1 << 15)
+#define	PINCTRL_PULL3_BANK3_PIN14			(1 << 14)
+#define	PINCTRL_PULL3_BANK3_PIN13			(1 << 13)
+#define	PINCTRL_PULL3_BANK3_PIN12			(1 << 12)
+#define	PINCTRL_PULL3_BANK3_PIN11			(1 << 11)
+#define	PINCTRL_PULL3_BANK3_PIN10			(1 << 10)
+#define	PINCTRL_PULL3_BANK3_PIN09			(1 << 9)
+#define	PINCTRL_PULL3_BANK3_PIN08			(1 << 8)
+#define	PINCTRL_PULL3_BANK3_PIN07			(1 << 7)
+#define	PINCTRL_PULL3_BANK3_PIN06			(1 << 6)
+#define	PINCTRL_PULL3_BANK3_PIN05			(1 << 5)
+#define	PINCTRL_PULL3_BANK3_PIN04			(1 << 4)
+#define	PINCTRL_PULL3_BANK3_PIN03			(1 << 3)
+#define	PINCTRL_PULL3_BANK3_PIN02			(1 << 2)
+#define	PINCTRL_PULL3_BANK3_PIN01			(1 << 1)
+#define	PINCTRL_PULL3_BANK3_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL4_BANK4_PIN20			(1 << 20)
+#define	PINCTRL_PULL4_BANK4_PIN16			(1 << 16)
+#define	PINCTRL_PULL4_BANK4_PIN15			(1 << 15)
+#define	PINCTRL_PULL4_BANK4_PIN14			(1 << 14)
+#define	PINCTRL_PULL4_BANK4_PIN13			(1 << 13)
+#define	PINCTRL_PULL4_BANK4_PIN12			(1 << 12)
+#define	PINCTRL_PULL4_BANK4_PIN11			(1 << 11)
+#define	PINCTRL_PULL4_BANK4_PIN10			(1 << 10)
+#define	PINCTRL_PULL4_BANK4_PIN09			(1 << 9)
+#define	PINCTRL_PULL4_BANK4_PIN08			(1 << 8)
+#define	PINCTRL_PULL4_BANK4_PIN07			(1 << 7)
+#define	PINCTRL_PULL4_BANK4_PIN06			(1 << 6)
+#define	PINCTRL_PULL4_BANK4_PIN05			(1 << 5)
+#define	PINCTRL_PULL4_BANK4_PIN04			(1 << 4)
+#define	PINCTRL_PULL4_BANK4_PIN03			(1 << 3)
+#define	PINCTRL_PULL4_BANK4_PIN02			(1 << 2)
+#define	PINCTRL_PULL4_BANK4_PIN01			(1 << 1)
+#define	PINCTRL_PULL4_BANK4_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL5_BANK5_PIN26			(1 << 26)
+#define	PINCTRL_PULL5_BANK5_PIN23			(1 << 23)
+#define	PINCTRL_PULL5_BANK5_PIN22			(1 << 22)
+#define	PINCTRL_PULL5_BANK5_PIN21			(1 << 21)
+#define	PINCTRL_PULL5_BANK5_PIN20			(1 << 20)
+#define	PINCTRL_PULL5_BANK5_PIN19			(1 << 19)
+#define	PINCTRL_PULL5_BANK5_PIN18			(1 << 18)
+#define	PINCTRL_PULL5_BANK5_PIN17			(1 << 17)
+#define	PINCTRL_PULL5_BANK5_PIN16			(1 << 16)
+#define	PINCTRL_PULL5_BANK5_PIN15			(1 << 15)
+#define	PINCTRL_PULL5_BANK5_PIN14			(1 << 14)
+#define	PINCTRL_PULL5_BANK5_PIN13			(1 << 13)
+#define	PINCTRL_PULL5_BANK5_PIN12			(1 << 12)
+#define	PINCTRL_PULL5_BANK5_PIN11			(1 << 11)
+#define	PINCTRL_PULL5_BANK5_PIN10			(1 << 10)
+#define	PINCTRL_PULL5_BANK5_PIN09			(1 << 9)
+#define	PINCTRL_PULL5_BANK5_PIN08			(1 << 8)
+#define	PINCTRL_PULL5_BANK5_PIN07			(1 << 7)
+#define	PINCTRL_PULL5_BANK5_PIN06			(1 << 6)
+#define	PINCTRL_PULL5_BANK5_PIN05			(1 << 5)
+#define	PINCTRL_PULL5_BANK5_PIN04			(1 << 4)
+#define	PINCTRL_PULL5_BANK5_PIN03			(1 << 3)
+#define	PINCTRL_PULL5_BANK5_PIN02			(1 << 2)
+#define	PINCTRL_PULL5_BANK5_PIN01			(1 << 1)
+#define	PINCTRL_PULL5_BANK5_PIN00			(1 << 0)
+
+#define	PINCTRL_PULL6_BANK6_PIN24			(1 << 24)
+#define	PINCTRL_PULL6_BANK6_PIN23			(1 << 23)
+#define	PINCTRL_PULL6_BANK6_PIN22			(1 << 22)
+#define	PINCTRL_PULL6_BANK6_PIN21			(1 << 21)
+#define	PINCTRL_PULL6_BANK6_PIN20			(1 << 20)
+#define	PINCTRL_PULL6_BANK6_PIN19			(1 << 19)
+#define	PINCTRL_PULL6_BANK6_PIN18			(1 << 18)
+#define	PINCTRL_PULL6_BANK6_PIN17			(1 << 17)
+#define	PINCTRL_PULL6_BANK6_PIN16			(1 << 16)
+#define	PINCTRL_PULL6_BANK6_PIN14			(1 << 14)
+#define	PINCTRL_PULL6_BANK6_PIN13			(1 << 13)
+#define	PINCTRL_PULL6_BANK6_PIN12			(1 << 12)
+#define	PINCTRL_PULL6_BANK6_PIN11			(1 << 11)
+#define	PINCTRL_PULL6_BANK6_PIN10			(1 << 10)
+#define	PINCTRL_PULL6_BANK6_PIN09			(1 << 9)
+#define	PINCTRL_PULL6_BANK6_PIN08			(1 << 8)
+#define	PINCTRL_PULL6_BANK6_PIN07			(1 << 7)
+#define	PINCTRL_PULL6_BANK6_PIN06			(1 << 6)
+#define	PINCTRL_PULL6_BANK6_PIN05			(1 << 5)
+#define	PINCTRL_PULL6_BANK6_PIN04			(1 << 4)
+#define	PINCTRL_PULL6_BANK6_PIN03			(1 << 3)
+#define	PINCTRL_PULL6_BANK6_PIN02			(1 << 2)
+#define	PINCTRL_PULL6_BANK6_PIN01			(1 << 1)
+#define	PINCTRL_PULL6_BANK6_PIN00			(1 << 0)
+
+#define	PINCTRL_DOUT0_DOUT_MASK				0x1fffffff
+#define	PINCTRL_DOUT0_DOUT_OFFSET			0
+
+#define	PINCTRL_DOUT1_DOUT_MASK				0xffffffff
+#define	PINCTRL_DOUT1_DOUT_OFFSET			0
+
+#define	PINCTRL_DOUT2_DOUT_MASK				0xfffffff
+#define	PINCTRL_DOUT2_DOUT_OFFSET			0
+
+#define	PINCTRL_DOUT3_DOUT_MASK				0x7fffffff
+#define	PINCTRL_DOUT3_DOUT_OFFSET			0
+
+#define	PINCTRL_DOUT4_DOUT_MASK				0x1fffff
+#define	PINCTRL_DOUT4_DOUT_OFFSET			0
+
+#define	PINCTRL_DIN0_DIN_MASK				0x1fffffff
+#define	PINCTRL_DIN0_DIN_OFFSET				0
+
+#define	PINCTRL_DIN1_DIN_MASK				0xffffffff
+#define	PINCTRL_DIN1_DIN_OFFSET				0
+
+#define	PINCTRL_DIN2_DIN_MASK				0xfffffff
+#define	PINCTRL_DIN2_DIN_OFFSET				0
+
+#define	PINCTRL_DIN3_DIN_MASK				0x7fffffff
+#define	PINCTRL_DIN3_DIN_OFFSET				0
+
+#define	PINCTRL_DIN4_DIN_MASK				0x1fffff
+#define	PINCTRL_DIN4_DIN_OFFSET				0
+
+#define	PINCTRL_DOE0_DOE_MASK				0x1fffffff
+#define	PINCTRL_DOE0_DOE_OFFSET				0
+
+#define	PINCTRL_DOE1_DOE_MASK				0xffffffff
+#define	PINCTRL_DOE1_DOE_OFFSET				0
+
+#define	PINCTRL_DOE2_DOE_MASK				0xfffffff
+#define	PINCTRL_DOE2_DOE_OFFSET				0
+
+#define	PINCTRL_DOE3_DOE_MASK				0x7fffffff
+#define	PINCTRL_DOE3_DOE_OFFSET				0
+
+#define	PINCTRL_DOE4_DOE_MASK				0x1fffff
+#define	PINCTRL_DOE4_DOE_OFFSET				0
+
+#define	PINCTRL_PIN2IRQ0_PIN2IRQ_MASK			0x1fffffff
+#define	PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET			0
+
+#define	PINCTRL_PIN2IRQ1_PIN2IRQ_MASK			0xffffffff
+#define	PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET			0
+
+#define	PINCTRL_PIN2IRQ2_PIN2IRQ_MASK			0xfffffff
+#define	PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET			0
+
+#define	PINCTRL_PIN2IRQ3_PIN2IRQ_MASK			0x7fffffff
+#define	PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET			0
+
+#define	PINCTRL_PIN2IRQ4_PIN2IRQ_MASK			0x1fffff
+#define	PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET			0
+
+#define	PINCTRL_IRQEN0_IRQEN_MASK			0x1fffffff
+#define	PINCTRL_IRQEN0_IRQEN_OFFSET			0
+
+#define	PINCTRL_IRQEN1_IRQEN_MASK			0xffffffff
+#define	PINCTRL_IRQEN1_IRQEN_OFFSET			0
+
+#define	PINCTRL_IRQEN2_IRQEN_MASK			0xfffffff
+#define	PINCTRL_IRQEN2_IRQEN_OFFSET			0
+
+#define	PINCTRL_IRQEN3_IRQEN_MASK			0x7fffffff
+#define	PINCTRL_IRQEN3_IRQEN_OFFSET			0
+
+#define	PINCTRL_IRQEN4_IRQEN_MASK			0x1fffff
+#define	PINCTRL_IRQEN4_IRQEN_OFFSET			0
+
+#define	PINCTRL_IRQLEVEL0_IRQLEVEL_MASK			0x1fffffff
+#define	PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET		0
+
+#define	PINCTRL_IRQLEVEL1_IRQLEVEL_MASK			0xffffffff
+#define	PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET		0
+
+#define	PINCTRL_IRQLEVEL2_IRQLEVEL_MASK			0xfffffff
+#define	PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET		0
+
+#define	PINCTRL_IRQLEVEL3_IRQLEVEL_MASK			0x7fffffff
+#define	PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET		0
+
+#define	PINCTRL_IRQLEVEL4_IRQLEVEL_MASK			0x1fffff
+#define	PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET		0
+
+#define	PINCTRL_IRQPOL0_IRQPOL_MASK			0x1fffffff
+#define	PINCTRL_IRQPOL0_IRQPOL_OFFSET			0
+
+#define	PINCTRL_IRQPOL1_IRQPOL_MASK			0xffffffff
+#define	PINCTRL_IRQPOL1_IRQPOL_OFFSET			0
+
+#define	PINCTRL_IRQPOL2_IRQPOL_MASK			0xfffffff
+#define	PINCTRL_IRQPOL2_IRQPOL_OFFSET			0
+
+#define	PINCTRL_IRQPOL3_IRQPOL_MASK			0x7fffffff
+#define	PINCTRL_IRQPOL3_IRQPOL_OFFSET			0
+
+#define	PINCTRL_IRQPOL4_IRQPOL_MASK			0x1fffff
+#define	PINCTRL_IRQPOL4_IRQPOL_OFFSET			0
+
+#define	PINCTRL_IRQSTAT0_IRQSTAT_MASK			0x1fffffff
+#define	PINCTRL_IRQSTAT0_IRQSTAT_OFFSET			0
+
+#define	PINCTRL_IRQSTAT1_IRQSTAT_MASK			0xffffffff
+#define	PINCTRL_IRQSTAT1_IRQSTAT_OFFSET			0
+
+#define	PINCTRL_IRQSTAT2_IRQSTAT_MASK			0xfffffff
+#define	PINCTRL_IRQSTAT2_IRQSTAT_OFFSET			0
+
+#define	PINCTRL_IRQSTAT3_IRQSTAT_MASK			0x7fffffff
+#define	PINCTRL_IRQSTAT3_IRQSTAT_OFFSET			0
+
+#define	PINCTRL_IRQSTAT4_IRQSTAT_MASK			0x1fffff
+#define	PINCTRL_IRQSTAT4_IRQSTAT_OFFSET			0
+
+#define	PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK		(0x3 << 26)
+#define	PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET	26
+#define	PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK		(0x3 << 24)
+#define	PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET	24
+#define	PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK		(0x3 << 22)
+#define	PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET	22
+#define	PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK		(0x3 << 20)
+#define	PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET	20
+#define	PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK		(0x3 << 18)
+#define	PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET	18
+#define	PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK		(0x3 << 16)
+#define	PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET	16
+#define	PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK		(0x3 << 14)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET	14
+#define	PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK		(0x3 << 12)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET	12
+#define	PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK		(0x3 << 10)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET	10
+#define	PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK		(0x3 << 8)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET	8
+#define	PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK		(0x3 << 6)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET	6
+#define	PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK		(0x3 << 4)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET	4
+#define	PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK		(0x3 << 2)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET	2
+#define	PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK		(0x3 << 0)
+#define	PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET	0
+
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK		(0x3 << 16)
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET		16
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR		(0x0 << 16)
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO		(0x1 << 16)
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2		(0x2 << 16)
+#define	PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2		(0x3 << 16)
+#define	PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK		(0x3 << 12)
+#define	PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET		12
+#define	PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK		(0x3 << 10)
+#define	PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET		10
+#define	PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK		(0x3 << 8)
+#define	PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET		8
+#define	PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK		(0x3 << 6)
+#define	PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET		6
+#define	PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK		(0x3 << 4)
+#define	PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET		4
+#define	PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK		(0x3 << 2)
+#define	PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET		2
+#define	PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK		(0x3 << 0)
+#define	PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET		0
+
+#endif /* __MX28_REGS_PINCTRL_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
new file mode 100644
index 0000000..a0dc781
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
@@ -0,0 +1,344 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX23 Power Controller Register Definitions
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __MX23_REGS_POWER_H__
+#define __MX23_REGS_POWER_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_power_regs {
+	mxs_reg_32(hw_power_ctrl)
+	mxs_reg_32(hw_power_5vctrl)
+	mxs_reg_32(hw_power_minpwr)
+	mxs_reg_32(hw_power_charge)
+	uint32_t	hw_power_vdddctrl;
+	uint32_t	reserved_vddd[3];
+	uint32_t	hw_power_vddactrl;
+	uint32_t	reserved_vdda[3];
+	uint32_t	hw_power_vddioctrl;
+	uint32_t	reserved_vddio[3];
+	uint32_t	hw_power_vddmemctrl;
+	uint32_t	reserved_vddmem[3];
+	uint32_t	hw_power_dcdc4p2;
+	uint32_t	reserved_dcdc4p2[3];
+	uint32_t	hw_power_misc;
+	uint32_t	reserved_misc[3];
+	uint32_t	hw_power_dclimits;
+	uint32_t	reserved_dclimits[3];
+	mxs_reg_32(hw_power_loopctrl)
+	uint32_t	hw_power_sts;
+	uint32_t	reserved_sts[3];
+	mxs_reg_32(hw_power_speed)
+	uint32_t	hw_power_battmonitor;
+	uint32_t	reserved_battmonitor[3];
+
+	uint32_t	reserved1[4];
+
+	mxs_reg_32(hw_power_reset)
+
+	uint32_t	reserved2[4];
+
+	mxs_reg_32(hw_power_special)
+	mxs_reg_32(hw_power_version)
+};
+#endif
+
+#define	POWER_CTRL_CLKGATE				(1 << 30)
+#define	POWER_CTRL_PSWITCH_MID_TRAN			(1 << 27)
+#define	POWER_CTRL_DCDC4P2_BO_IRQ			(1 << 24)
+#define	POWER_CTRL_ENIRQ_DCDC4P2_BO			(1 << 23)
+#define	POWER_CTRL_VDD5V_DROOP_IRQ			(1 << 22)
+#define	POWER_CTRL_ENIRQ_VDD5V_DROOP			(1 << 21)
+#define	POWER_CTRL_PSWITCH_IRQ				(1 << 20)
+#define	POWER_CTRL_PSWITCH_IRQ_SRC			(1 << 19)
+#define	POWER_CTRL_POLARITY_PSWITCH			(1 << 18)
+#define	POWER_CTRL_ENIRQ_PSWITCH			(1 << 17)
+#define	POWER_CTRL_POLARITY_DC_OK			(1 << 16)
+#define	POWER_CTRL_DC_OK_IRQ				(1 << 15)
+#define	POWER_CTRL_ENIRQ_DC_OK				(1 << 14)
+#define	POWER_CTRL_BATT_BO_IRQ				(1 << 13)
+#define	POWER_CTRL_ENIRQ_BATT_BO			(1 << 12)
+#define	POWER_CTRL_VDDIO_BO_IRQ				(1 << 11)
+#define	POWER_CTRL_ENIRQ_VDDIO_BO			(1 << 10)
+#define	POWER_CTRL_VDDA_BO_IRQ				(1 << 9)
+#define	POWER_CTRL_ENIRQ_VDDA_BO			(1 << 8)
+#define	POWER_CTRL_VDDD_BO_IRQ				(1 << 7)
+#define	POWER_CTRL_ENIRQ_VDDD_BO			(1 << 6)
+#define	POWER_CTRL_POLARITY_VBUSVALID			(1 << 5)
+#define	POWER_CTRL_VBUS_VALID_IRQ			(1 << 4)
+#define	POWER_CTRL_ENIRQ_VBUS_VALID			(1 << 3)
+#define	POWER_CTRL_POLARITY_VDD5V_GT_VDDIO		(1 << 2)
+#define	POWER_CTRL_VDD5V_GT_VDDIO_IRQ			(1 << 1)
+#define	POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO			(1 << 0)
+
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_MASK		(0x3 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET		28
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V3			(0x0 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V4			(0x1 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V5			(0x2 << 28)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V7			(0x3 << 28)
+#define	POWER_5VCTRL_HEADROOM_ADJ_MASK			(0x7 << 24)
+#define	POWER_5VCTRL_HEADROOM_ADJ_OFFSET		24
+#define	POWER_5VCTRL_PWD_CHARGE_4P2_MASK		(0x1 << 20)
+#define	POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET		20
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK		(0x3f << 12)
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET		12
+#define	POWER_5VCTRL_VBUSVALID_TRSH_MASK		(0x7 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_OFFSET		8
+#define	POWER_5VCTRL_VBUSVALID_TRSH_2V9			(0x0 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V0			(0x1 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V1			(0x2 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V2			(0x3 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V3			(0x4 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V4			(0x5 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V5			(0x6 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V6			(0x7 << 8)
+#define	POWER_5VCTRL_PWDN_5VBRNOUT			(1 << 7)
+#define	POWER_5VCTRL_ENABLE_LINREG_ILIMIT		(1 << 6)
+#define	POWER_5VCTRL_DCDC_XFER				(1 << 5)
+#define	POWER_5VCTRL_VBUSVALID_5VDETECT			(1 << 4)
+#define	POWER_5VCTRL_VBUSVALID_TO_B			(1 << 3)
+#define	POWER_5VCTRL_ILIMIT_EQ_ZERO			(1 << 2)
+#define	POWER_5VCTRL_PWRUP_VBUS_CMPS			(1 << 1)
+#define	POWER_5VCTRL_ENABLE_DCDC			(1 << 0)
+
+#define	POWER_MINPWR_LOWPWR_4P2				(1 << 14)
+#define	POWER_MINPWR_VDAC_DUMP_CTRL			(1 << 13)
+#define	POWER_MINPWR_PWD_BO				(1 << 12)
+#define	POWER_MINPWR_USE_VDDXTAL_VBG			(1 << 11)
+#define	POWER_MINPWR_PWD_ANA_CMPS			(1 << 10)
+#define	POWER_MINPWR_ENABLE_OSC				(1 << 9)
+#define	POWER_MINPWR_SELECT_OSC				(1 << 8)
+#define	POWER_MINPWR_VBG_OFF				(1 << 7)
+#define	POWER_MINPWR_DOUBLE_FETS			(1 << 6)
+#define	POWER_MINPWR_HALFFETS				(1 << 5)
+#define	POWER_MINPWR_LESSANA_I				(1 << 4)
+#define	POWER_MINPWR_PWD_XTAL24				(1 << 3)
+#define	POWER_MINPWR_DC_STOPCLK				(1 << 2)
+#define	POWER_MINPWR_EN_DC_PFM				(1 << 1)
+#define	POWER_MINPWR_DC_HALFCLK				(1 << 0)
+
+#define	POWER_CHARGE_ADJ_VOLT_MASK			(0x7 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_OFFSET			24
+#define	POWER_CHARGE_ADJ_VOLT_M025P			(0x1 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P050P			(0x2 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M075P			(0x3 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P025P			(0x4 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M050P			(0x5 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P075P			(0x6 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M100P			(0x7 << 24)
+#define	POWER_CHARGE_ENABLE_LOAD			(1 << 22)
+#define	POWER_CHARGE_ENABLE_CHARGER_RESISTORS		(1 << 21)
+#define	POWER_CHARGE_ENABLE_FAULT_DETECT		(1 << 20)
+#define	POWER_CHARGE_CHRG_STS_OFF			(1 << 19)
+#define	POWER_CHARGE_USE_EXTERN_R			(1 << 17)
+#define	POWER_CHARGE_PWD_BATTCHRG			(1 << 16)
+#define	POWER_CHARGE_STOP_ILIMIT_MASK			(0xf << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_OFFSET			8
+#define	POWER_CHARGE_STOP_ILIMIT_10MA			(0x1 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_20MA			(0x2 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_50MA			(0x4 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_100MA			(0x8 << 8)
+#define	POWER_CHARGE_BATTCHRG_I_MASK			0x3f
+#define	POWER_CHARGE_BATTCHRG_I_OFFSET			0
+#define	POWER_CHARGE_BATTCHRG_I_10MA			0x01
+#define	POWER_CHARGE_BATTCHRG_I_20MA			0x02
+#define	POWER_CHARGE_BATTCHRG_I_50MA			0x04
+#define	POWER_CHARGE_BATTCHRG_I_100MA			0x08
+#define	POWER_CHARGE_BATTCHRG_I_200MA			0x10
+#define	POWER_CHARGE_BATTCHRG_I_400MA			0x20
+
+#define	POWER_VDDDCTRL_ADJTN_MASK			(0xf << 28)
+#define	POWER_VDDDCTRL_ADJTN_OFFSET			28
+#define	POWER_VDDDCTRL_PWDN_BRNOUT			(1 << 23)
+#define	POWER_VDDDCTRL_DISABLE_STEPPING			(1 << 22)
+#define	POWER_VDDDCTRL_ENABLE_LINREG			(1 << 21)
+#define	POWER_VDDDCTRL_DISABLE_FET			(1 << 20)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_MASK		(0x3 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_OFFSET		16
+#define	POWER_VDDDCTRL_LINREG_OFFSET_0STEPS		(0x0 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 16)
+#define	POWER_VDDDCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDDCTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDDCTRL_TRG_MASK				0x1f
+#define	POWER_VDDDCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDACTRL_PWDN_BRNOUT			(1 << 19)
+#define	POWER_VDDACTRL_DISABLE_STEPPING			(1 << 18)
+#define	POWER_VDDACTRL_ENABLE_LINREG			(1 << 17)
+#define	POWER_VDDACTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDACTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDACTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDACTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDACTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDACTRL_TRG_MASK				0x1f
+#define	POWER_VDDACTRL_TRG_OFFSET			0
+
+#define	POWER_VDDIOCTRL_ADJTN_MASK			(0xf << 20)
+#define	POWER_VDDIOCTRL_ADJTN_OFFSET			20
+#define	POWER_VDDIOCTRL_PWDN_BRNOUT			(1 << 18)
+#define	POWER_VDDIOCTRL_DISABLE_STEPPING		(1 << 17)
+#define	POWER_VDDIOCTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDIOCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDIOCTRL_BO_OFFSET_OFFSET		8
+#define	POWER_VDDIOCTRL_TRG_MASK			0x1f
+#define	POWER_VDDIOCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDMEMCTRL_PULLDOWN_ACTIVE		(1 << 10)
+#define	POWER_VDDMEMCTRL_ENABLE_ILIMIT			(1 << 9)
+#define	POWER_VDDMEMCTRL_ENABLE_LINREG			(1 << 8)
+#define	POWER_VDDMEMCTRL_TRG_MASK			0x1f
+#define	POWER_VDDMEMCTRL_TRG_OFFSET			0
+
+#define	POWER_DCDC4P2_DROPOUT_CTRL_MASK			(0xf << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_OFFSET		28
+#define	POWER_DCDC4P2_DROPOUT_CTRL_200MV		(0x3 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_100MV		(0x2 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_50MV			(0x1 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_25MV			(0x0 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2		(0x0 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT	(0x1 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL		(0x2 << 28)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_MASK		(0x3 << 24)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_OFFSET		24
+#define	POWER_DCDC4P2_ENABLE_4P2			(1 << 23)
+#define	POWER_DCDC4P2_ENABLE_DCDC			(1 << 22)
+#define	POWER_DCDC4P2_HYST_DIR				(1 << 21)
+#define	POWER_DCDC4P2_HYST_THRESH			(1 << 20)
+#define	POWER_DCDC4P2_TRG_MASK				(0x7 << 16)
+#define	POWER_DCDC4P2_TRG_OFFSET			16
+#define	POWER_DCDC4P2_TRG_4V2				(0x0 << 16)
+#define	POWER_DCDC4P2_TRG_4V1				(0x1 << 16)
+#define	POWER_DCDC4P2_TRG_4V0				(0x2 << 16)
+#define	POWER_DCDC4P2_TRG_3V9				(0x3 << 16)
+#define	POWER_DCDC4P2_TRG_BATT				(0x4 << 16)
+#define	POWER_DCDC4P2_BO_MASK				(0x1f << 8)
+#define	POWER_DCDC4P2_BO_OFFSET				8
+#define	POWER_DCDC4P2_CMPTRIP_MASK			0x1f
+#define	POWER_DCDC4P2_CMPTRIP_OFFSET			0
+
+#define	POWER_MISC_FREQSEL_MASK				(0x7 << 4)
+#define	POWER_MISC_FREQSEL_OFFSET			4
+#define	POWER_MISC_FREQSEL_20MHZ			(0x1 << 4)
+#define	POWER_MISC_FREQSEL_24MHZ			(0x2 << 4)
+#define	POWER_MISC_FREQSEL_19MHZ			(0x3 << 4)
+#define	POWER_MISC_FREQSEL_14MHZ			(0x4 << 4)
+#define	POWER_MISC_FREQSEL_18MHZ			(0x5 << 4)
+#define	POWER_MISC_FREQSEL_21MHZ			(0x6 << 4)
+#define	POWER_MISC_FREQSEL_17MHZ			(0x7 << 4)
+#define	POWER_MISC_DISABLE_FET_BO_LOGIC			(1 << 3)
+#define	POWER_MISC_DELAY_TIMING				(1 << 2)
+#define	POWER_MISC_TEST					(1 << 1)
+#define	POWER_MISC_SEL_PLLCLK				(1 << 0)
+
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_MASK		(0x7f << 8)
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET		8
+#define	POWER_DCLIMITS_NEGLIMIT_MASK			0x7f
+#define	POWER_DCLIMITS_NEGLIMIT_OFFSET			0
+
+#define	POWER_LOOPCTRL_TOGGLE_DIF			(1 << 20)
+#define	POWER_LOOPCTRL_HYST_SIGN			(1 << 19)
+#define	POWER_LOOPCTRL_EN_CM_HYST			(1 << 18)
+#define	POWER_LOOPCTRL_EN_DF_HYST			(1 << 17)
+#define	POWER_LOOPCTRL_CM_HYST_THRESH			(1 << 16)
+#define	POWER_LOOPCTRL_DF_HYST_THRESH			(1 << 15)
+#define	POWER_LOOPCTRL_RCSCALE_THRESH			(1 << 14)
+#define	POWER_LOOPCTRL_EN_RCSCALE_MASK			(0x3 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_OFFSET		12
+#define	POWER_LOOPCTRL_EN_RCSCALE_DIS			(0x0 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_2X			(0x1 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_4X			(0x2 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_8X			(0x3 << 12)
+#define	POWER_LOOPCTRL_DC_FF_MASK			(0x7 << 8)
+#define	POWER_LOOPCTRL_DC_FF_OFFSET			8
+#define	POWER_LOOPCTRL_DC_R_MASK			(0xf << 4)
+#define	POWER_LOOPCTRL_DC_R_OFFSET			4
+#define	POWER_LOOPCTRL_DC_C_MASK			0x3
+#define	POWER_LOOPCTRL_DC_C_OFFSET			0
+#define	POWER_LOOPCTRL_DC_C_MAX				0x0
+#define	POWER_LOOPCTRL_DC_C_2X				0x1
+#define	POWER_LOOPCTRL_DC_C_4X				0x2
+#define	POWER_LOOPCTRL_DC_C_MIN				0x3
+
+#define	POWER_STS_PWRUP_SOURCE_MASK			(0x3f << 24)
+#define	POWER_STS_PWRUP_SOURCE_OFFSET			24
+#define	POWER_STS_PWRUP_SOURCE_5V			(0x20 << 24)
+#define	POWER_STS_PWRUP_SOURCE_RTC			(0x10 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH		(0x02 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_MID		(0x01 << 24)
+#define	POWER_STS_PSWITCH_MASK				(0x3 << 20)
+#define	POWER_STS_PSWITCH_OFFSET			20
+#define	POWER_STS_AVALID0_STATUS			(1 << 17)
+#define	POWER_STS_BVALID0_STATUS			(1 << 16)
+#define	POWER_STS_VBUSVALID0_STATUS			(1 << 15)
+#define	POWER_STS_SESSEND0_STATUS			(1 << 14)
+#define	POWER_STS_BATT_BO				(1 << 13)
+#define	POWER_STS_VDD5V_FAULT				(1 << 12)
+#define	POWER_STS_CHRGSTS				(1 << 11)
+#define	POWER_STS_DCDC_4P2_BO				(1 << 10)
+#define	POWER_STS_DC_OK					(1 << 9)
+#define	POWER_STS_VDDIO_BO				(1 << 8)
+#define	POWER_STS_VDDA_BO				(1 << 7)
+#define	POWER_STS_VDDD_BO				(1 << 6)
+#define	POWER_STS_VDD5V_GT_VDDIO			(1 << 5)
+#define	POWER_STS_VDD5V_DROOP				(1 << 4)
+#define	POWER_STS_AVALID0				(1 << 3)
+#define	POWER_STS_BVALID0				(1 << 2)
+#define	POWER_STS_VBUSVALID0				(1 << 1)
+#define	POWER_STS_SESSEND0				(1 << 0)
+
+#define	POWER_SPEED_STATUS_MASK				(0xff << 16)
+#define	POWER_SPEED_STATUS_OFFSET			16
+#define	POWER_SPEED_CTRL_MASK				0x3
+#define	POWER_SPEED_CTRL_OFFSET				0
+#define	POWER_SPEED_CTRL_SS_OFF				0x0
+#define	POWER_SPEED_CTRL_SS_ON				0x1
+#define	POWER_SPEED_CTRL_SS_ENABLE			0x3
+
+#define	POWER_BATTMONITOR_BATT_VAL_MASK			(0x3ff << 16)
+#define	POWER_BATTMONITOR_BATT_VAL_OFFSET		16
+#define	POWER_BATTMONITOR_EN_BATADJ			(1 << 10)
+#define	POWER_BATTMONITOR_PWDN_BATTBRNOUT		(1 << 9)
+#define	POWER_BATTMONITOR_BRWNOUT_PWD			(1 << 8)
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_MASK		0x1f
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET		0
+
+#define	POWER_RESET_UNLOCK_MASK				(0xffff << 16)
+#define	POWER_RESET_UNLOCK_OFFSET			16
+#define	POWER_RESET_UNLOCK_KEY				(0x3e77 << 16)
+#define	POWER_RESET_PWD_OFF				(1 << 1)
+#define	POWER_RESET_PWD					(1 << 0)
+
+#define	POWER_DEBUG_VBUSVALIDPIOLOCK			(1 << 3)
+#define	POWER_DEBUG_AVALIDPIOLOCK			(1 << 2)
+#define	POWER_DEBUG_BVALIDPIOLOCK			(1 << 1)
+#define	POWER_DEBUG_SESSENDPIOLOCK			(1 << 0)
+
+#define	POWER_SPECIAL_TEST_MASK				0xffffffff
+#define	POWER_SPECIAL_TEST_OFFSET			0
+
+#define	POWER_VERSION_MAJOR_MASK			(0xff << 24)
+#define	POWER_VERSION_MAJOR_OFFSET			24
+#define	POWER_VERSION_MINOR_MASK			(0xff << 16)
+#define	POWER_VERSION_MINOR_OFFSET			16
+#define	POWER_VERSION_STEP_MASK				0xffff
+#define	POWER_VERSION_STEP_OFFSET			0
+
+#endif	/* __MX23_REGS_POWER_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h
new file mode 100644
index 0000000..39250c5
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h
@@ -0,0 +1,399 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 Power Controller Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#ifndef __MX28_REGS_POWER_H__
+#define __MX28_REGS_POWER_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_power_regs {
+	mxs_reg_32(hw_power_ctrl)
+	mxs_reg_32(hw_power_5vctrl)
+	mxs_reg_32(hw_power_minpwr)
+	mxs_reg_32(hw_power_charge)
+	uint32_t	hw_power_vdddctrl;
+	uint32_t	reserved_vddd[3];
+	uint32_t	hw_power_vddactrl;
+	uint32_t	reserved_vdda[3];
+	uint32_t	hw_power_vddioctrl;
+	uint32_t	reserved_vddio[3];
+	uint32_t	hw_power_vddmemctrl;
+	uint32_t	reserved_vddmem[3];
+	uint32_t	hw_power_dcdc4p2;
+	uint32_t	reserved_dcdc4p2[3];
+	uint32_t	hw_power_misc;
+	uint32_t	reserved_misc[3];
+	uint32_t	hw_power_dclimits;
+	uint32_t	reserved_dclimits[3];
+	mxs_reg_32(hw_power_loopctrl)
+	uint32_t	hw_power_sts;
+	uint32_t	reserved_sts[3];
+	mxs_reg_32(hw_power_speed)
+	uint32_t	hw_power_battmonitor;
+	uint32_t	reserved_battmonitor[3];
+
+	uint32_t	reserved[4];
+
+	mxs_reg_32(hw_power_reset)
+	mxs_reg_32(hw_power_debug)
+	mxs_reg_32(hw_power_thermal)
+	mxs_reg_32(hw_power_usb1ctrl)
+	mxs_reg_32(hw_power_special)
+	mxs_reg_32(hw_power_version)
+	mxs_reg_32(hw_power_anaclkctrl)
+	mxs_reg_32(hw_power_refctrl)
+};
+#endif
+
+#define	POWER_CTRL_PSWITCH_MID_TRAN			(1 << 27)
+#define	POWER_CTRL_DCDC4P2_BO_IRQ			(1 << 24)
+#define	POWER_CTRL_ENIRQ_DCDC4P2_BO			(1 << 23)
+#define	POWER_CTRL_VDD5V_DROOP_IRQ			(1 << 22)
+#define	POWER_CTRL_ENIRQ_VDD5V_DROOP			(1 << 21)
+#define	POWER_CTRL_PSWITCH_IRQ				(1 << 20)
+#define	POWER_CTRL_PSWITCH_IRQ_SRC			(1 << 19)
+#define	POWER_CTRL_POLARITY_PSWITCH			(1 << 18)
+#define	POWER_CTRL_ENIRQ_PSWITCH			(1 << 17)
+#define	POWER_CTRL_POLARITY_DC_OK			(1 << 16)
+#define	POWER_CTRL_DC_OK_IRQ				(1 << 15)
+#define	POWER_CTRL_ENIRQ_DC_OK				(1 << 14)
+#define	POWER_CTRL_BATT_BO_IRQ				(1 << 13)
+#define	POWER_CTRL_ENIRQ_BATT_BO			(1 << 12)
+#define	POWER_CTRL_VDDIO_BO_IRQ				(1 << 11)
+#define	POWER_CTRL_ENIRQ_VDDIO_BO			(1 << 10)
+#define	POWER_CTRL_VDDA_BO_IRQ				(1 << 9)
+#define	POWER_CTRL_ENIRQ_VDDA_BO			(1 << 8)
+#define	POWER_CTRL_VDDD_BO_IRQ				(1 << 7)
+#define	POWER_CTRL_ENIRQ_VDDD_BO			(1 << 6)
+#define	POWER_CTRL_POLARITY_VBUSVALID			(1 << 5)
+#define	POWER_CTRL_VBUS_VALID_IRQ			(1 << 4)
+#define	POWER_CTRL_ENIRQ_VBUS_VALID			(1 << 3)
+#define	POWER_CTRL_POLARITY_VDD5V_GT_VDDIO		(1 << 2)
+#define	POWER_CTRL_VDD5V_GT_VDDIO_IRQ			(1 << 1)
+#define	POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO			(1 << 0)
+
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_MASK		(0x3 << 30)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET		30
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V3			(0x0 << 30)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V4			(0x1 << 30)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V5			(0x2 << 30)
+#define	POWER_5VCTRL_VBUSDROOP_TRSH_4V7			(0x3 << 30)
+#define	POWER_5VCTRL_HEADROOM_ADJ_MASK			(0x7 << 24)
+#define	POWER_5VCTRL_HEADROOM_ADJ_OFFSET		24
+#define	POWER_5VCTRL_PWD_CHARGE_4P2_MASK		(0x3 << 20)
+#define	POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET		20
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK		(0x3f << 12)
+#define	POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET		12
+#define	POWER_5VCTRL_VBUSVALID_TRSH_MASK		(0x7 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_OFFSET		8
+#define	POWER_5VCTRL_VBUSVALID_TRSH_2V9			(0x0 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V0			(0x1 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V1			(0x2 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V2			(0x3 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V3			(0x4 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V4			(0x5 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V5			(0x6 << 8)
+#define	POWER_5VCTRL_VBUSVALID_TRSH_4V6			(0x7 << 8)
+#define	POWER_5VCTRL_PWDN_5VBRNOUT			(1 << 7)
+#define	POWER_5VCTRL_ENABLE_LINREG_ILIMIT		(1 << 6)
+#define	POWER_5VCTRL_DCDC_XFER				(1 << 5)
+#define	POWER_5VCTRL_VBUSVALID_5VDETECT			(1 << 4)
+#define	POWER_5VCTRL_VBUSVALID_TO_B			(1 << 3)
+#define	POWER_5VCTRL_ILIMIT_EQ_ZERO			(1 << 2)
+#define	POWER_5VCTRL_PWRUP_VBUS_CMPS			(1 << 1)
+#define	POWER_5VCTRL_ENABLE_DCDC			(1 << 0)
+
+#define	POWER_MINPWR_LOWPWR_4P2				(1 << 14)
+#define	POWER_MINPWR_PWD_BO				(1 << 12)
+#define	POWER_MINPWR_USE_VDDXTAL_VBG			(1 << 11)
+#define	POWER_MINPWR_PWD_ANA_CMPS			(1 << 10)
+#define	POWER_MINPWR_ENABLE_OSC				(1 << 9)
+#define	POWER_MINPWR_SELECT_OSC				(1 << 8)
+#define	POWER_MINPWR_VBG_OFF				(1 << 7)
+#define	POWER_MINPWR_DOUBLE_FETS			(1 << 6)
+#define	POWER_MINPWR_HALFFETS				(1 << 5)
+#define	POWER_MINPWR_LESSANA_I				(1 << 4)
+#define	POWER_MINPWR_PWD_XTAL24				(1 << 3)
+#define	POWER_MINPWR_DC_STOPCLK				(1 << 2)
+#define	POWER_MINPWR_EN_DC_PFM				(1 << 1)
+#define	POWER_MINPWR_DC_HALFCLK				(1 << 0)
+
+#define	POWER_CHARGE_ADJ_VOLT_MASK			(0x7 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_OFFSET			24
+#define	POWER_CHARGE_ADJ_VOLT_M025P			(0x1 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P050P			(0x2 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M075P			(0x3 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P025P			(0x4 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M050P			(0x5 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_P075P			(0x6 << 24)
+#define	POWER_CHARGE_ADJ_VOLT_M100P			(0x7 << 24)
+#define	POWER_CHARGE_ENABLE_LOAD			(1 << 22)
+#define	POWER_CHARGE_ENABLE_FAULT_DETECT		(1 << 20)
+#define	POWER_CHARGE_CHRG_STS_OFF			(1 << 19)
+#define	POWER_CHARGE_LIION_4P1				(1 << 18)
+#define	POWER_CHARGE_PWD_BATTCHRG			(1 << 16)
+#define	POWER_CHARGE_ENABLE_CHARGER_USB1		(1 << 13)
+#define	POWER_CHARGE_ENABLE_CHARGER_USB0		(1 << 12)
+#define	POWER_CHARGE_STOP_ILIMIT_MASK			(0xf << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_OFFSET			8
+#define	POWER_CHARGE_STOP_ILIMIT_10MA			(0x1 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_20MA			(0x2 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_50MA			(0x4 << 8)
+#define	POWER_CHARGE_STOP_ILIMIT_100MA			(0x8 << 8)
+#define	POWER_CHARGE_BATTCHRG_I_MASK			0x3f
+#define	POWER_CHARGE_BATTCHRG_I_OFFSET			0
+#define	POWER_CHARGE_BATTCHRG_I_10MA			0x01
+#define	POWER_CHARGE_BATTCHRG_I_20MA			0x02
+#define	POWER_CHARGE_BATTCHRG_I_50MA			0x04
+#define	POWER_CHARGE_BATTCHRG_I_100MA			0x08
+#define	POWER_CHARGE_BATTCHRG_I_200MA			0x10
+#define	POWER_CHARGE_BATTCHRG_I_400MA			0x20
+
+#define	POWER_VDDDCTRL_ADJTN_MASK			(0xf << 28)
+#define	POWER_VDDDCTRL_ADJTN_OFFSET			28
+#define	POWER_VDDDCTRL_PWDN_BRNOUT			(1 << 23)
+#define	POWER_VDDDCTRL_DISABLE_STEPPING			(1 << 22)
+#define	POWER_VDDDCTRL_ENABLE_LINREG			(1 << 21)
+#define	POWER_VDDDCTRL_DISABLE_FET			(1 << 20)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_MASK		(0x3 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_OFFSET		16
+#define	POWER_VDDDCTRL_LINREG_OFFSET_0STEPS		(0x0 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 16)
+#define	POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 16)
+#define	POWER_VDDDCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDDCTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDDCTRL_TRG_MASK				0x1f
+#define	POWER_VDDDCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDACTRL_PWDN_BRNOUT			(1 << 19)
+#define	POWER_VDDACTRL_DISABLE_STEPPING			(1 << 18)
+#define	POWER_VDDACTRL_ENABLE_LINREG			(1 << 17)
+#define	POWER_VDDACTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDACTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDACTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDACTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDACTRL_BO_OFFSET_OFFSET			8
+#define	POWER_VDDACTRL_TRG_MASK				0x1f
+#define	POWER_VDDACTRL_TRG_OFFSET			0
+
+#define	POWER_VDDIOCTRL_ADJTN_MASK			(0xf << 20)
+#define	POWER_VDDIOCTRL_ADJTN_OFFSET			20
+#define	POWER_VDDIOCTRL_PWDN_BRNOUT			(1 << 18)
+#define	POWER_VDDIOCTRL_DISABLE_STEPPING		(1 << 17)
+#define	POWER_VDDIOCTRL_DISABLE_FET			(1 << 16)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_MASK		(0x3 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET		12
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS		(0x0 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE	(0x1 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW	(0x2 << 12)
+#define	POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW	(0x3 << 12)
+#define	POWER_VDDIOCTRL_BO_OFFSET_MASK			(0x7 << 8)
+#define	POWER_VDDIOCTRL_BO_OFFSET_OFFSET		8
+#define	POWER_VDDIOCTRL_TRG_MASK			0x1f
+#define	POWER_VDDIOCTRL_TRG_OFFSET			0
+
+#define	POWER_VDDMEMCTRL_PULLDOWN_ACTIVE		(1 << 10)
+#define	POWER_VDDMEMCTRL_ENABLE_ILIMIT			(1 << 9)
+#define	POWER_VDDMEMCTRL_ENABLE_LINREG			(1 << 8)
+#define	POWER_VDDMEMCTRL_BO_OFFSET_MASK			(0x7 << 5)
+#define	POWER_VDDMEMCTRL_BO_OFFSET_OFFSET		5
+#define	POWER_VDDMEMCTRL_TRG_MASK			0x1f
+#define	POWER_VDDMEMCTRL_TRG_OFFSET			0
+
+#define	POWER_DCDC4P2_DROPOUT_CTRL_MASK			(0xf << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_OFFSET		28
+#define	POWER_DCDC4P2_DROPOUT_CTRL_200MV		(0x3 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_100MV		(0x2 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_50MV			(0x1 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_25MV			(0x0 << 30)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2		(0x0 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT	(0x1 << 28)
+#define	POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL		(0x2 << 28)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_MASK		(0x3 << 24)
+#define	POWER_DCDC4P2_ISTEAL_THRESH_OFFSET		24
+#define	POWER_DCDC4P2_ENABLE_4P2			(1 << 23)
+#define	POWER_DCDC4P2_ENABLE_DCDC			(1 << 22)
+#define	POWER_DCDC4P2_HYST_DIR				(1 << 21)
+#define	POWER_DCDC4P2_HYST_THRESH			(1 << 20)
+#define	POWER_DCDC4P2_TRG_MASK				(0x7 << 16)
+#define	POWER_DCDC4P2_TRG_OFFSET			16
+#define	POWER_DCDC4P2_TRG_4V2				(0x0 << 16)
+#define	POWER_DCDC4P2_TRG_4V1				(0x1 << 16)
+#define	POWER_DCDC4P2_TRG_4V0				(0x2 << 16)
+#define	POWER_DCDC4P2_TRG_3V9				(0x3 << 16)
+#define	POWER_DCDC4P2_TRG_BATT				(0x4 << 16)
+#define	POWER_DCDC4P2_BO_MASK				(0x1f << 8)
+#define	POWER_DCDC4P2_BO_OFFSET				8
+#define	POWER_DCDC4P2_CMPTRIP_MASK			0x1f
+#define	POWER_DCDC4P2_CMPTRIP_OFFSET			0
+
+#define	POWER_MISC_FREQSEL_MASK				(0x7 << 4)
+#define	POWER_MISC_FREQSEL_OFFSET			4
+#define	POWER_MISC_FREQSEL_20MHZ			(0x1 << 4)
+#define	POWER_MISC_FREQSEL_24MHZ			(0x2 << 4)
+#define	POWER_MISC_FREQSEL_19MHZ			(0x3 << 4)
+#define	POWER_MISC_FREQSEL_14MHZ			(0x4 << 4)
+#define	POWER_MISC_FREQSEL_18MHZ			(0x5 << 4)
+#define	POWER_MISC_FREQSEL_21MHZ			(0x6 << 4)
+#define	POWER_MISC_FREQSEL_17MHZ			(0x7 << 4)
+#define	POWER_MISC_DISABLE_FET_BO_LOGIC			(1 << 3)
+#define	POWER_MISC_DELAY_TIMING				(1 << 2)
+#define	POWER_MISC_TEST					(1 << 1)
+#define	POWER_MISC_SEL_PLLCLK				(1 << 0)
+
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_MASK		(0x7f << 8)
+#define	POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET		8
+#define	POWER_DCLIMITS_NEGLIMIT_MASK			0x7f
+#define	POWER_DCLIMITS_NEGLIMIT_OFFSET			0
+
+#define	POWER_LOOPCTRL_TOGGLE_DIF			(1 << 20)
+#define	POWER_LOOPCTRL_HYST_SIGN			(1 << 19)
+#define	POWER_LOOPCTRL_EN_CM_HYST			(1 << 18)
+#define	POWER_LOOPCTRL_EN_DF_HYST			(1 << 17)
+#define	POWER_LOOPCTRL_CM_HYST_THRESH			(1 << 16)
+#define	POWER_LOOPCTRL_DF_HYST_THRESH			(1 << 15)
+#define	POWER_LOOPCTRL_RCSCALE_THRESH			(1 << 14)
+#define	POWER_LOOPCTRL_EN_RCSCALE_MASK			(0x3 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_OFFSET		12
+#define	POWER_LOOPCTRL_EN_RCSCALE_DIS			(0x0 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_2X			(0x1 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_4X			(0x2 << 12)
+#define	POWER_LOOPCTRL_EN_RCSCALE_8X			(0x3 << 12)
+#define	POWER_LOOPCTRL_DC_FF_MASK			(0x7 << 8)
+#define	POWER_LOOPCTRL_DC_FF_OFFSET			8
+#define	POWER_LOOPCTRL_DC_R_MASK			(0xf << 4)
+#define	POWER_LOOPCTRL_DC_R_OFFSET			4
+#define	POWER_LOOPCTRL_DC_C_MASK			0x3
+#define	POWER_LOOPCTRL_DC_C_OFFSET			0
+#define	POWER_LOOPCTRL_DC_C_MAX				0x0
+#define	POWER_LOOPCTRL_DC_C_2X				0x1
+#define	POWER_LOOPCTRL_DC_C_4X				0x2
+#define	POWER_LOOPCTRL_DC_C_MIN				0x3
+
+#define	POWER_STS_PWRUP_SOURCE_MASK			(0x3f << 24)
+#define	POWER_STS_PWRUP_SOURCE_OFFSET			24
+#define	POWER_STS_PWRUP_SOURCE_5V			(0x20 << 24)
+#define	POWER_STS_PWRUP_SOURCE_RTC			(0x10 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH		(0x02 << 24)
+#define	POWER_STS_PWRUP_SOURCE_PSWITCH_MID		(0x01 << 24)
+#define	POWER_STS_PSWITCH_MASK				(0x3 << 20)
+#define	POWER_STS_PSWITCH_OFFSET			20
+#define	POWER_STS_THERMAL_WARNING			(1 << 19)
+#define	POWER_STS_VDDMEM_BO				(1 << 18)
+#define	POWER_STS_AVALID0_STATUS			(1 << 17)
+#define	POWER_STS_BVALID0_STATUS			(1 << 16)
+#define	POWER_STS_VBUSVALID0_STATUS			(1 << 15)
+#define	POWER_STS_SESSEND0_STATUS			(1 << 14)
+#define	POWER_STS_BATT_BO				(1 << 13)
+#define	POWER_STS_VDD5V_FAULT				(1 << 12)
+#define	POWER_STS_CHRGSTS				(1 << 11)
+#define	POWER_STS_DCDC_4P2_BO				(1 << 10)
+#define	POWER_STS_DC_OK					(1 << 9)
+#define	POWER_STS_VDDIO_BO				(1 << 8)
+#define	POWER_STS_VDDA_BO				(1 << 7)
+#define	POWER_STS_VDDD_BO				(1 << 6)
+#define	POWER_STS_VDD5V_GT_VDDIO			(1 << 5)
+#define	POWER_STS_VDD5V_DROOP				(1 << 4)
+#define	POWER_STS_AVALID0				(1 << 3)
+#define	POWER_STS_BVALID0				(1 << 2)
+#define	POWER_STS_VBUSVALID0				(1 << 1)
+#define	POWER_STS_SESSEND0				(1 << 0)
+
+#define	POWER_SPEED_STATUS_MASK				(0xffff << 8)
+#define	POWER_SPEED_STATUS_OFFSET			8
+#define	POWER_SPEED_STATUS_SEL_MASK			(0x3 << 6)
+#define	POWER_SPEED_STATUS_SEL_OFFSET			6
+#define	POWER_SPEED_STATUS_SEL_DCDC_STAT		(0x0 << 6)
+#define	POWER_SPEED_STATUS_SEL_CORE_STAT		(0x1 << 6)
+#define	POWER_SPEED_STATUS_SEL_ARM_STAT			(0x2 << 6)
+#define	POWER_SPEED_CTRL_MASK				0x3
+#define	POWER_SPEED_CTRL_OFFSET				0
+#define	POWER_SPEED_CTRL_SS_OFF				0x0
+#define	POWER_SPEED_CTRL_SS_ON				0x1
+#define	POWER_SPEED_CTRL_SS_ENABLE			0x3
+
+#define	POWER_BATTMONITOR_BATT_VAL_MASK			(0x3ff << 16)
+#define	POWER_BATTMONITOR_BATT_VAL_OFFSET		16
+#define	POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN	(1 << 11)
+#define	POWER_BATTMONITOR_EN_BATADJ			(1 << 10)
+#define	POWER_BATTMONITOR_PWDN_BATTBRNOUT		(1 << 9)
+#define	POWER_BATTMONITOR_BRWNOUT_PWD			(1 << 8)
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_MASK		0x1f
+#define	POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET		0
+
+#define	POWER_RESET_UNLOCK_MASK				(0xffff << 16)
+#define	POWER_RESET_UNLOCK_OFFSET			16
+#define	POWER_RESET_UNLOCK_KEY				(0x3e77 << 16)
+#define	POWER_RESET_FASTFALL_PSWITCH_OFF		(1 << 2)
+#define	POWER_RESET_PWD_OFF				(1 << 1)
+#define	POWER_RESET_PWD					(1 << 0)
+
+#define	POWER_DEBUG_VBUSVALIDPIOLOCK			(1 << 3)
+#define	POWER_DEBUG_AVALIDPIOLOCK			(1 << 2)
+#define	POWER_DEBUG_BVALIDPIOLOCK			(1 << 1)
+#define	POWER_DEBUG_SESSENDPIOLOCK			(1 << 0)
+
+#define	POWER_THERMAL_TEST				(1 << 8)
+#define	POWER_THERMAL_PWD				(1 << 7)
+#define	POWER_THERMAL_LOW_POWER				(1 << 6)
+#define	POWER_THERMAL_OFFSET_ADJ_MASK			(0x3 << 4)
+#define	POWER_THERMAL_OFFSET_ADJ_OFFSET			4
+#define	POWER_THERMAL_OFFSET_ADJ_ENABLE			(1 << 3)
+#define	POWER_THERMAL_TEMP_THRESHOLD_MASK		0x7
+#define	POWER_THERMAL_TEMP_THRESHOLD_OFFSET		0
+
+#define	POWER_USB1CTRL_AVALID1				(1 << 3)
+#define	POWER_USB1CTRL_BVALID1				(1 << 2)
+#define	POWER_USB1CTRL_VBUSVALID1			(1 << 1)
+#define	POWER_USB1CTRL_SESSEND1				(1 << 0)
+
+#define	POWER_SPECIAL_TEST_MASK				0xffffffff
+#define	POWER_SPECIAL_TEST_OFFSET			0
+
+#define	POWER_VERSION_MAJOR_MASK			(0xff << 24)
+#define	POWER_VERSION_MAJOR_OFFSET			24
+#define	POWER_VERSION_MINOR_MASK			(0xff << 16)
+#define	POWER_VERSION_MINOR_OFFSET			16
+#define	POWER_VERSION_STEP_MASK				0xffff
+#define	POWER_VERSION_STEP_OFFSET			0
+
+#define	POWER_ANACLKCTRL_CLKGATE_0			(1 << 31)
+#define	POWER_ANACLKCTRL_OUTDIV_MASK			(0x7 << 28)
+#define	POWER_ANACLKCTRL_OUTDIV_OFFSET			28
+#define	POWER_ANACLKCTRL_INVERT_OUTCLK			(1 << 27)
+#define	POWER_ANACLKCTRL_CLKGATE_I			(1 << 26)
+#define	POWER_ANACLKCTRL_DITHER_OFF			(1 << 10)
+#define	POWER_ANACLKCTRL_SLOW_DITHER			(1 << 9)
+#define	POWER_ANACLKCTRL_INVERT_INCLK			(1 << 8)
+#define	POWER_ANACLKCTRL_INCLK_SHIFT_MASK		(0x3 << 4)
+#define	POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET		4
+#define	POWER_ANACLKCTRL_INDIV_MASK			0x7
+#define	POWER_ANACLKCTRL_INDIV_OFFSET			0
+
+#define	POWER_REFCTRL_FASTSETTLING			(1 << 26)
+#define	POWER_REFCTRL_RAISE_REF				(1 << 25)
+#define	POWER_REFCTRL_XTAL_BGR_BIAS			(1 << 24)
+#define	POWER_REFCTRL_VBG_ADJ_MASK			(0x7 << 20)
+#define	POWER_REFCTRL_VBG_ADJ_OFFSET			20
+#define	POWER_REFCTRL_LOW_PWR				(1 << 19)
+#define	POWER_REFCTRL_BIAS_CTRL_MASK			(0x3 << 16)
+#define	POWER_REFCTRL_BIAS_CTRL_OFFSET			16
+#define	POWER_REFCTRL_VDDXTAL_TO_VDDD			(1 << 14)
+#define	POWER_REFCTRL_ADJ_ANA				(1 << 13)
+#define	POWER_REFCTRL_ADJ_VAG				(1 << 12)
+#define	POWER_REFCTRL_ANA_REFVAL_MASK			(0xf << 8)
+#define	POWER_REFCTRL_ANA_REFVAL_OFFSET			8
+#define	POWER_REFCTRL_VAG_VAL_MASK			(0xf << 4)
+#define	POWER_REFCTRL_VAG_VAL_OFFSET			4
+
+#endif	/* __MX28_REGS_POWER_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-rtc.h b/arch/arm/include/asm/arch-mxs/regs-rtc.h
new file mode 100644
index 0000000..8d6ba57
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-rtc.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 RTC Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#ifndef __MX28_REGS_RTC_H__
+#define __MX28_REGS_RTC_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_rtc_regs {
+	mxs_reg_32(hw_rtc_ctrl)
+	mxs_reg_32(hw_rtc_stat)
+	mxs_reg_32(hw_rtc_milliseconds)
+	mxs_reg_32(hw_rtc_seconds)
+	mxs_reg_32(hw_rtc_rtc_alarm)
+	mxs_reg_32(hw_rtc_watchdog)
+	mxs_reg_32(hw_rtc_persistent0)
+	mxs_reg_32(hw_rtc_persistent1)
+	mxs_reg_32(hw_rtc_persistent2)
+	mxs_reg_32(hw_rtc_persistent3)
+	mxs_reg_32(hw_rtc_persistent4)
+	mxs_reg_32(hw_rtc_persistent5)
+	mxs_reg_32(hw_rtc_debug)
+	mxs_reg_32(hw_rtc_version)
+};
+#endif
+
+#define	RTC_CTRL_SFTRST				(1 << 31)
+#define	RTC_CTRL_CLKGATE			(1 << 30)
+#define	RTC_CTRL_SUPPRESS_COPY2ANALOG		(1 << 6)
+#define	RTC_CTRL_FORCE_UPDATE			(1 << 5)
+#define	RTC_CTRL_WATCHDOGEN			(1 << 4)
+#define	RTC_CTRL_ONEMSEC_IRQ			(1 << 3)
+#define	RTC_CTRL_ALARM_IRQ			(1 << 2)
+#define	RTC_CTRL_ONEMSEC_IRQ_EN			(1 << 1)
+#define	RTC_CTRL_ALARM_IRQ_EN			(1 << 0)
+
+#define	RTC_STAT_RTC_PRESENT			(1 << 31)
+#define	RTC_STAT_ALARM_PRESENT			(1 << 30)
+#define	RTC_STAT_WATCHDOG_PRESENT		(1 << 29)
+#define	RTC_STAT_XTAL32000_PRESENT		(1 << 28)
+#define	RTC_STAT_XTAL32768_PRESENT		(1 << 27)
+#define	RTC_STAT_STALE_REGS_MASK		(0xff << 16)
+#define	RTC_STAT_STALE_REGS_OFFSET		16
+#define	RTC_STAT_NEW_REGS_MASK			(0xff << 8)
+#define	RTC_STAT_NEW_REGS_OFFSET		8
+
+#define	RTC_MILLISECONDS_COUNT_MASK		0xffffffff
+#define	RTC_MILLISECONDS_COUNT_OFFSET		0
+
+#define	RTC_SECONDS_COUNT_MASK			0xffffffff
+#define	RTC_SECONDS_COUNT_OFFSET		0
+
+#define	RTC_ALARM_VALUE_MASK			0xffffffff
+#define	RTC_ALARM_VALUE_OFFSET			0
+
+#define	RTC_WATCHDOG_COUNT_MASK			0xffffffff
+#define	RTC_WATCHDOG_COUNT_OFFSET		0
+
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK	(0xf << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET	28
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83	(0x0 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78	(0x1 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73	(0x2 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68	(0x3 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62	(0x4 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57	(0x5 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52	(0x6 << 28)
+#define	RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48	(0x7 << 28)
+#define	RTC_PERSISTENT0_EXTERNAL_RESET		(1 << 21)
+#define	RTC_PERSISTENT0_THERMAL_RESET		(1 << 20)
+#define	RTC_PERSISTENT0_ENABLE_LRADC_PWRUP	(1 << 18)
+#define	RTC_PERSISTENT0_AUTO_RESTART		(1 << 17)
+#define	RTC_PERSISTENT0_DISABLE_PSWITCH		(1 << 16)
+#define	RTC_PERSISTENT0_LOWERBIAS_MASK		(0xf << 14)
+#define	RTC_PERSISTENT0_LOWERBIAS_OFFSET	14
+#define	RTC_PERSISTENT0_LOWERBIAS_NOMINAL	(0x0 << 14)
+#define	RTC_PERSISTENT0_LOWERBIAS_M25P		(0x1 << 14)
+#define	RTC_PERSISTENT0_LOWERBIAS_M50P		(0x3 << 14)
+#define	RTC_PERSISTENT0_DISABLE_XTALOK		(1 << 13)
+#define	RTC_PERSISTENT0_MSEC_RES_MASK		(0x1f << 8)
+#define	RTC_PERSISTENT0_MSEC_RES_OFFSET		8
+#define	RTC_PERSISTENT0_MSEC_RES_1MS		(0x01 << 8)
+#define	RTC_PERSISTENT0_MSEC_RES_2MS		(0x02 << 8)
+#define	RTC_PERSISTENT0_MSEC_RES_4MS		(0x04 << 8)
+#define	RTC_PERSISTENT0_MSEC_RES_8MS		(0x08 << 8)
+#define	RTC_PERSISTENT0_MSEC_RES_16MS		(0x10 << 8)
+#define	RTC_PERSISTENT0_ALARM_WAKE		(1 << 7)
+#define	RTC_PERSISTENT0_XTAL32_FREQ		(1 << 6)
+#define	RTC_PERSISTENT0_XTAL32KHZ_PWRUP		(1 << 5)
+#define	RTC_PERSISTENT0_XTAL24KHZ_PWRUP		(1 << 4)
+#define	RTC_PERSISTENT0_LCK_SECS		(1 << 3)
+#define	RTC_PERSISTENT0_ALARM_EN		(1 << 2)
+#define	RTC_PERSISTENT0_ALARM_WAKE_EN		(1 << 1)
+#define	RTC_PERSISTENT0_CLOCKSOURCE		(1 << 0)
+
+#define	RTC_PERSISTENT1_GENERAL_MASK		0xffffffff
+#define	RTC_PERSISTENT1_GENERAL_OFFSET		0
+#define	RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE	0x0080
+#define	RTC_PERSISTENT1_GENERAL_OTG_HNP		0x0100
+#define	RTC_PERSISTENT1_GENERAL_USB_LPM		0x0200
+#define	RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK	0x0400
+#define	RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER	0x0800
+#define	RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X	0x1000
+
+#define	RTC_PERSISTENT2_GENERAL_MASK		0xffffffff
+#define	RTC_PERSISTENT2_GENERAL_OFFSET		0
+
+#define	RTC_PERSISTENT3_GENERAL_MASK		0xffffffff
+#define	RTC_PERSISTENT3_GENERAL_OFFSET		0
+
+#define	RTC_PERSISTENT4_GENERAL_MASK		0xffffffff
+#define	RTC_PERSISTENT4_GENERAL_OFFSET		0
+
+#define	RTC_PERSISTENT5_GENERAL_MASK		0xffffffff
+#define	RTC_PERSISTENT5_GENERAL_OFFSET		0
+
+#define	RTC_DEBUG_WATCHDOG_RESET_MASK		(1 << 1)
+#define	RTC_DEBUG_WATCHDOG_RESET		(1 << 0)
+
+#define	RTC_VERSION_MAJOR_MASK			(0xff << 24)
+#define	RTC_VERSION_MAJOR_OFFSET		24
+#define	RTC_VERSION_MINOR_MASK			(0xff << 16)
+#define	RTC_VERSION_MINOR_OFFSET		16
+#define	RTC_VERSION_STEP_MASK			0xffff
+#define	RTC_VERSION_STEP_OFFSET			0
+
+#endif	/* __MX28_REGS_RTC_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h
new file mode 100644
index 0000000..eeb7e7f
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h
@@ -0,0 +1,415 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 SSP Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __MX28_REGS_SSP_H__
+#define __MX28_REGS_SSP_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+#if defined(CONFIG_MX23)
+struct mxs_ssp_regs {
+	mxs_reg_32(hw_ssp_ctrl0)
+	mxs_reg_32(hw_ssp_cmd0)
+	mxs_reg_32(hw_ssp_cmd1)
+	mxs_reg_32(hw_ssp_compref)
+	mxs_reg_32(hw_ssp_compmask)
+	mxs_reg_32(hw_ssp_timing)
+	mxs_reg_32(hw_ssp_ctrl1)
+	mxs_reg_32(hw_ssp_data)
+	mxs_reg_32(hw_ssp_sdresp0)
+	mxs_reg_32(hw_ssp_sdresp1)
+	mxs_reg_32(hw_ssp_sdresp2)
+	mxs_reg_32(hw_ssp_sdresp3)
+	mxs_reg_32(hw_ssp_status)
+
+	uint32_t	reserved1[12];
+
+	mxs_reg_32(hw_ssp_debug)
+	mxs_reg_32(hw_ssp_version)
+};
+#elif defined(CONFIG_MX28)
+struct mxs_ssp_regs {
+	mxs_reg_32(hw_ssp_ctrl0)
+	mxs_reg_32(hw_ssp_cmd0)
+	mxs_reg_32(hw_ssp_cmd1)
+	mxs_reg_32(hw_ssp_xfer_size)
+	mxs_reg_32(hw_ssp_block_size)
+	mxs_reg_32(hw_ssp_compref)
+	mxs_reg_32(hw_ssp_compmask)
+	mxs_reg_32(hw_ssp_timing)
+	mxs_reg_32(hw_ssp_ctrl1)
+	mxs_reg_32(hw_ssp_data)
+	mxs_reg_32(hw_ssp_sdresp0)
+	mxs_reg_32(hw_ssp_sdresp1)
+	mxs_reg_32(hw_ssp_sdresp2)
+	mxs_reg_32(hw_ssp_sdresp3)
+	mxs_reg_32(hw_ssp_ddr_ctrl)
+	mxs_reg_32(hw_ssp_dll_ctrl)
+	mxs_reg_32(hw_ssp_status)
+	mxs_reg_32(hw_ssp_dll_sts)
+	mxs_reg_32(hw_ssp_debug)
+	mxs_reg_32(hw_ssp_version)
+};
+#endif
+
+static inline int mxs_ssp_bus_id_valid(int bus)
+{
+#if defined(CONFIG_MX23)
+	const unsigned int mxs_ssp_chan_count = 2;
+#elif defined(CONFIG_MX28)
+	const unsigned int mxs_ssp_chan_count = 4;
+#endif
+
+	if (bus >= mxs_ssp_chan_count)
+		return 0;
+
+	if (bus < 0)
+		return 0;
+
+	return 1;
+}
+
+static inline int mxs_ssp_clock_by_bus(unsigned int clock)
+{
+#if defined(CONFIG_MX23)
+	return 0;
+#elif defined(CONFIG_MX28)
+	return clock;
+#endif
+}
+
+static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
+{
+	switch (port) {
+	case 0:
+		return (struct mxs_ssp_regs *)MXS_SSP0_BASE;
+	case 1:
+		return (struct mxs_ssp_regs *)MXS_SSP1_BASE;
+#ifdef CONFIG_MX28
+	case 2:
+		return (struct mxs_ssp_regs *)MXS_SSP2_BASE;
+	case 3:
+		return (struct mxs_ssp_regs *)MXS_SSP3_BASE;
+#endif
+	default:
+		return NULL;
+	}
+}
+#endif
+
+#define	SSP_CTRL0_SFTRST			(1 << 31)
+#define	SSP_CTRL0_CLKGATE			(1 << 30)
+#define	SSP_CTRL0_RUN				(1 << 29)
+#define	SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)
+#define	SSP_CTRL0_LOCK_CS			(1 << 27)
+#define	SSP_CTRL0_IGNORE_CRC			(1 << 26)
+#define	SSP_CTRL0_READ				(1 << 25)
+#define	SSP_CTRL0_DATA_XFER			(1 << 24)
+#define	SSP_CTRL0_BUS_WIDTH_MASK		(0x3 << 22)
+#define	SSP_CTRL0_BUS_WIDTH_OFFSET		22
+#define	SSP_CTRL0_BUS_WIDTH_ONE_BIT		(0x0 << 22)
+#define	SSP_CTRL0_BUS_WIDTH_FOUR_BIT		(0x1 << 22)
+#define	SSP_CTRL0_BUS_WIDTH_EIGHT_BIT		(0x2 << 22)
+#define	SSP_CTRL0_WAIT_FOR_IRQ			(1 << 21)
+#define	SSP_CTRL0_WAIT_FOR_CMD			(1 << 20)
+#define	SSP_CTRL0_LONG_RESP			(1 << 19)
+#define	SSP_CTRL0_CHECK_RESP			(1 << 18)
+#define	SSP_CTRL0_GET_RESP			(1 << 17)
+#define	SSP_CTRL0_ENABLE			(1 << 16)
+
+#ifdef CONFIG_MX23
+#define	SSP_CTRL0_XFER_COUNT_OFFSET		0
+#define	SSP_CTRL0_XFER_COUNT_MASK		0xffff
+#endif
+
+#define	SSP_CMD0_SOFT_TERMINATE			(1 << 26)
+#define	SSP_CMD0_DBL_DATA_RATE_EN		(1 << 25)
+#define	SSP_CMD0_PRIM_BOOT_OP_EN		(1 << 24)
+#define	SSP_CMD0_BOOT_ACK_EN			(1 << 23)
+#define	SSP_CMD0_SLOW_CLKING_EN			(1 << 22)
+#define	SSP_CMD0_CONT_CLKING_EN			(1 << 21)
+#define	SSP_CMD0_APPEND_8CYC			(1 << 20)
+#if defined(CONFIG_MX23)
+#define	SSP_CMD0_BLOCK_SIZE_MASK		(0xf << 16)
+#define	SSP_CMD0_BLOCK_SIZE_OFFSET		16
+#define	SSP_CMD0_BLOCK_COUNT_MASK		(0xff << 8)
+#define	SSP_CMD0_BLOCK_COUNT_OFFSET		8
+#endif
+#define	SSP_CMD0_CMD_MASK			0xff
+#define	SSP_CMD0_CMD_OFFSET			0
+#define	SSP_CMD0_CMD_MMC_GO_IDLE_STATE		0x00
+#define	SSP_CMD0_CMD_MMC_SEND_OP_COND		0x01
+#define	SSP_CMD0_CMD_MMC_ALL_SEND_CID		0x02
+#define	SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR	0x03
+#define	SSP_CMD0_CMD_MMC_SET_DSR		0x04
+#define	SSP_CMD0_CMD_MMC_RESERVED_5		0x05
+#define	SSP_CMD0_CMD_MMC_SWITCH			0x06
+#define	SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD	0x07
+#define	SSP_CMD0_CMD_MMC_SEND_EXT_CSD		0x08
+#define	SSP_CMD0_CMD_MMC_SEND_CSD		0x09
+#define	SSP_CMD0_CMD_MMC_SEND_CID		0x0a
+#define	SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP	0x0b
+#define	SSP_CMD0_CMD_MMC_STOP_TRANSMISSION	0x0c
+#define	SSP_CMD0_CMD_MMC_SEND_STATUS		0x0d
+#define	SSP_CMD0_CMD_MMC_BUSTEST_R		0x0e
+#define	SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE	0x0f
+#define	SSP_CMD0_CMD_MMC_SET_BLOCKLEN		0x10
+#define	SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK	0x11
+#define	SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK	0x12
+#define	SSP_CMD0_CMD_MMC_BUSTEST_W		0x13
+#define	SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP	0x14
+#define	SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT	0x17
+#define	SSP_CMD0_CMD_MMC_WRITE_BLOCK		0x18
+#define	SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK	0x19
+#define	SSP_CMD0_CMD_MMC_PROGRAM_CID		0x1a
+#define	SSP_CMD0_CMD_MMC_PROGRAM_CSD		0x1b
+#define	SSP_CMD0_CMD_MMC_SET_WRITE_PROT		0x1c
+#define	SSP_CMD0_CMD_MMC_CLR_WRITE_PROT		0x1d
+#define	SSP_CMD0_CMD_MMC_SEND_WRITE_PROT	0x1e
+#define	SSP_CMD0_CMD_MMC_ERASE_GROUP_START	0x23
+#define	SSP_CMD0_CMD_MMC_ERASE_GROUP_END	0x24
+#define	SSP_CMD0_CMD_MMC_ERASE			0x26
+#define	SSP_CMD0_CMD_MMC_FAST_IO		0x27
+#define	SSP_CMD0_CMD_MMC_GO_IRQ_STATE		0x28
+#define	SSP_CMD0_CMD_MMC_LOCK_UNLOCK		0x2a
+#define	SSP_CMD0_CMD_MMC_APP_CMD		0x37
+#define	SSP_CMD0_CMD_MMC_GEN_CMD		0x38
+#define	SSP_CMD0_CMD_SD_GO_IDLE_STATE		0x00
+#define	SSP_CMD0_CMD_SD_ALL_SEND_CID		0x02
+#define	SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR	0x03
+#define	SSP_CMD0_CMD_SD_SET_DSR			0x04
+#define	SSP_CMD0_CMD_SD_IO_SEND_OP_COND		0x05
+#define	SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD	0x07
+#define	SSP_CMD0_CMD_SD_SEND_CSD		0x09
+#define	SSP_CMD0_CMD_SD_SEND_CID		0x0a
+#define	SSP_CMD0_CMD_SD_STOP_TRANSMISSION	0x0c
+#define	SSP_CMD0_CMD_SD_SEND_STATUS		0x0d
+#define	SSP_CMD0_CMD_SD_GO_INACTIVE_STATE	0x0f
+#define	SSP_CMD0_CMD_SD_SET_BLOCKLEN		0x10
+#define	SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK	0x11
+#define	SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK	0x12
+#define	SSP_CMD0_CMD_SD_WRITE_BLOCK		0x18
+#define	SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK	0x19
+#define	SSP_CMD0_CMD_SD_PROGRAM_CSD		0x1b
+#define	SSP_CMD0_CMD_SD_SET_WRITE_PROT		0x1c
+#define	SSP_CMD0_CMD_SD_CLR_WRITE_PROT		0x1d
+#define	SSP_CMD0_CMD_SD_SEND_WRITE_PROT		0x1e
+#define	SSP_CMD0_CMD_SD_ERASE_WR_BLK_START	0x20
+#define	SSP_CMD0_CMD_SD_ERASE_WR_BLK_END	0x21
+#define	SSP_CMD0_CMD_SD_ERASE_GROUP_START	0x23
+#define	SSP_CMD0_CMD_SD_ERASE_GROUP_END		0x24
+#define	SSP_CMD0_CMD_SD_ERASE			0x26
+#define	SSP_CMD0_CMD_SD_LOCK_UNLOCK		0x2a
+#define	SSP_CMD0_CMD_SD_IO_RW_DIRECT		0x34
+#define	SSP_CMD0_CMD_SD_IO_RW_EXTENDED		0x35
+#define	SSP_CMD0_CMD_SD_APP_CMD			0x37
+#define	SSP_CMD0_CMD_SD_GEN_CMD			0x38
+
+#define	SSP_CMD1_CMD_ARG_MASK			0xffffffff
+#define	SSP_CMD1_CMD_ARG_OFFSET			0
+
+#if defined(CONFIG_MX28)
+#define	SSP_XFER_SIZE_XFER_COUNT_MASK		0xffffffff
+#define	SSP_XFER_SIZE_XFER_COUNT_OFFSET		0
+
+#define	SSP_BLOCK_SIZE_BLOCK_COUNT_MASK		(0xffffff << 4)
+#define	SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET	4
+#define	SSP_BLOCK_SIZE_BLOCK_SIZE_MASK		0xf
+#define	SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET	0
+#endif
+
+#define	SSP_COMPREF_REFERENCE_MASK		0xffffffff
+#define	SSP_COMPREF_REFERENCE_OFFSET		0
+
+#define	SSP_COMPMASK_MASK_MASK			0xffffffff
+#define	SSP_COMPMASK_MASK_OFFSET		0
+
+#define	SSP_TIMING_TIMEOUT_MASK			(0xffff << 16)
+#define	SSP_TIMING_TIMEOUT_OFFSET		16
+#define	SSP_TIMING_CLOCK_DIVIDE_MASK		(0xff << 8)
+#define	SSP_TIMING_CLOCK_DIVIDE_OFFSET		8
+#define	SSP_TIMING_CLOCK_RATE_MASK		0xff
+#define	SSP_TIMING_CLOCK_RATE_OFFSET		0
+
+#define	SSP_CTRL1_SDIO_IRQ			(1 << 31)
+#define	SSP_CTRL1_SDIO_IRQ_EN			(1 << 30)
+#define	SSP_CTRL1_RESP_ERR_IRQ			(1 << 29)
+#define	SSP_CTRL1_RESP_ERR_IRQ_EN		(1 << 28)
+#define	SSP_CTRL1_RESP_TIMEOUT_IRQ		(1 << 27)
+#define	SSP_CTRL1_RESP_TIMEOUT_IRQ_EN		(1 << 26)
+#define	SSP_CTRL1_DATA_TIMEOUT_IRQ		(1 << 25)
+#define	SSP_CTRL1_DATA_TIMEOUT_IRQ_EN		(1 << 24)
+#define	SSP_CTRL1_DATA_CRC_IRQ			(1 << 23)
+#define	SSP_CTRL1_DATA_CRC_IRQ_EN		(1 << 22)
+#define	SSP_CTRL1_FIFO_UNDERRUN_IRQ		(1 << 21)
+#define	SSP_CTRL1_FIFO_UNDERRUN_EN		(1 << 20)
+#define	SSP_CTRL1_CEATA_CCS_ERR_IRQ		(1 << 19)
+#define	SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN		(1 << 18)
+#define	SSP_CTRL1_RECV_TIMEOUT_IRQ		(1 << 17)
+#define	SSP_CTRL1_RECV_TIMEOUT_IRQ_EN		(1 << 16)
+#define	SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)
+#define	SSP_CTRL1_FIFO_OVERRUN_IRQ_EN		(1 << 14)
+#define	SSP_CTRL1_DMA_ENABLE			(1 << 13)
+#define	SSP_CTRL1_CEATA_CCS_ERR_EN		(1 << 12)
+#define	SSP_CTRL1_SLAVE_OUT_DISABLE		(1 << 11)
+#define	SSP_CTRL1_PHASE				(1 << 10)
+#define	SSP_CTRL1_POLARITY			(1 << 9)
+#define	SSP_CTRL1_SLAVE_MODE			(1 << 8)
+#define	SSP_CTRL1_WORD_LENGTH_MASK		(0xf << 4)
+#define	SSP_CTRL1_WORD_LENGTH_OFFSET		4
+#define	SSP_CTRL1_WORD_LENGTH_RESERVED0		(0x0 << 4)
+#define	SSP_CTRL1_WORD_LENGTH_RESERVED1		(0x1 << 4)
+#define	SSP_CTRL1_WORD_LENGTH_RESERVED2		(0x2 << 4)
+#define	SSP_CTRL1_WORD_LENGTH_FOUR_BITS		(0x3 << 4)
+#define	SSP_CTRL1_WORD_LENGTH_EIGHT_BITS	(0x7 << 4)
+#define	SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS	(0xf << 4)
+#define	SSP_CTRL1_SSP_MODE_MASK			0xf
+#define	SSP_CTRL1_SSP_MODE_OFFSET		0
+#define	SSP_CTRL1_SSP_MODE_SPI			0x0
+#define	SSP_CTRL1_SSP_MODE_SSI			0x1
+#define	SSP_CTRL1_SSP_MODE_SD_MMC		0x3
+#define	SSP_CTRL1_SSP_MODE_MS			0x4
+
+#define	SSP_DATA_DATA_MASK			0xffffffff
+#define	SSP_DATA_DATA_OFFSET			0
+
+#define	SSP_SDRESP0_RESP0_MASK			0xffffffff
+#define	SSP_SDRESP0_RESP0_OFFSET		0
+
+#define	SSP_SDRESP1_RESP1_MASK			0xffffffff
+#define	SSP_SDRESP1_RESP1_OFFSET		0
+
+#define	SSP_SDRESP2_RESP2_MASK			0xffffffff
+#define	SSP_SDRESP2_RESP2_OFFSET		0
+
+#define	SSP_SDRESP3_RESP3_MASK			0xffffffff
+#define	SSP_SDRESP3_RESP3_OFFSET		0
+
+#define	SSP_DDR_CTRL_DMA_BURST_TYPE_MASK	(0x3 << 30)
+#define	SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET	30
+#define	SSP_DDR_CTRL_NIBBLE_POS			(1 << 1)
+#define	SSP_DDR_CTRL_TXCLK_DELAY_TYPE		(1 << 0)
+
+#define	SSP_DLL_CTRL_REF_UPDATE_INT_MASK	(0xf << 28)
+#define	SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET	28
+#define	SSP_DLL_CTRL_SLV_UPDATE_INT_MASK	(0xff << 20)
+#define	SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET	20
+#define	SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK	(0x3f << 10)
+#define	SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET	10
+#define	SSP_DLL_CTRL_SLV_OVERRIDE		(1 << 9)
+#define	SSP_DLL_CTRL_GATE_UPDATE		(1 << 7)
+#define	SSP_DLL_CTRL_SLV_DLY_TARGET_MASK	(0xf << 3)
+#define	SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET	3
+#define	SSP_DLL_CTRL_SLV_FORCE_UPD		(1 << 2)
+#define	SSP_DLL_CTRL_RESET			(1 << 1)
+#define	SSP_DLL_CTRL_ENABLE			(1 << 0)
+
+#define	SSP_STATUS_PRESENT			(1 << 31)
+#define	SSP_STATUS_MS_PRESENT			(1 << 30)
+#define	SSP_STATUS_SD_PRESENT			(1 << 29)
+#define	SSP_STATUS_CARD_DETECT			(1 << 28)
+#define	SSP_STATUS_DMABURST			(1 << 22)
+#define	SSP_STATUS_DMASENSE			(1 << 21)
+#define	SSP_STATUS_DMATERM			(1 << 20)
+#define	SSP_STATUS_DMAREQ			(1 << 19)
+#define	SSP_STATUS_DMAEND			(1 << 18)
+#define	SSP_STATUS_SDIO_IRQ			(1 << 17)
+#define	SSP_STATUS_RESP_CRC_ERR			(1 << 16)
+#define	SSP_STATUS_RESP_ERR			(1 << 15)
+#define	SSP_STATUS_RESP_TIMEOUT			(1 << 14)
+#define	SSP_STATUS_DATA_CRC_ERR			(1 << 13)
+#define	SSP_STATUS_TIMEOUT			(1 << 12)
+#define	SSP_STATUS_RECV_TIMEOUT_STAT		(1 << 11)
+#define	SSP_STATUS_CEATA_CCS_ERR		(1 << 10)
+#define	SSP_STATUS_FIFO_OVRFLW			(1 << 9)
+#define	SSP_STATUS_FIFO_FULL			(1 << 8)
+#define	SSP_STATUS_FIFO_EMPTY			(1 << 5)
+#define	SSP_STATUS_FIFO_UNDRFLW			(1 << 4)
+#define	SSP_STATUS_CMD_BUSY			(1 << 3)
+#define	SSP_STATUS_DATA_BUSY			(1 << 2)
+#define	SSP_STATUS_BUSY				(1 << 0)
+
+#define	SSP_DLL_STS_REF_SEL_MASK		(0x3f << 8)
+#define	SSP_DLL_STS_REF_SEL_OFFSET		8
+#define	SSP_DLL_STS_SLV_SEL_MASK		(0x3f << 2)
+#define	SSP_DLL_STS_SLV_SEL_OFFSET		2
+#define	SSP_DLL_STS_REF_LOCK			(1 << 1)
+#define	SSP_DLL_STS_SLV_LOCK			(1 << 0)
+
+#define	SSP_DEBUG_DATACRC_ERR_MASK		(0xf << 28)
+#define	SSP_DEBUG_DATACRC_ERR_OFFSET		28
+#define	SSP_DEBUG_DATA_STALL			(1 << 27)
+#define	SSP_DEBUG_DAT_SM_MASK			(0x7 << 24)
+#define	SSP_DEBUG_DAT_SM_OFFSET			24
+#define	SSP_DEBUG_DAT_SM_DSM_IDLE		(0x0 << 24)
+#define	SSP_DEBUG_DAT_SM_DSM_WORD		(0x2 << 24)
+#define	SSP_DEBUG_DAT_SM_DSM_CRC1		(0x3 << 24)
+#define	SSP_DEBUG_DAT_SM_DSM_CRC2		(0x4 << 24)
+#define	SSP_DEBUG_DAT_SM_DSM_END		(0x5 << 24)
+#define	SSP_DEBUG_MSTK_SM_MASK			(0xf << 20)
+#define	SSP_DEBUG_MSTK_SM_OFFSET		20
+#define	SSP_DEBUG_MSTK_SM_MSTK_IDLE		(0x0 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_CKON		(0x1 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_BS1		(0x2 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_TPC		(0x3 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_BS2		(0x4 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_HDSHK		(0x5 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_BS3		(0x6 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_RW		(0x7 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_CRC1		(0x8 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_CRC2		(0x9 << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_BS0		(0xa << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_END1		(0xb << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_END2W		(0xc << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_END2R		(0xd << 20)
+#define	SSP_DEBUG_MSTK_SM_MSTK_DONE		(0xe << 20)
+#define	SSP_DEBUG_CMD_OE			(1 << 19)
+#define	SSP_DEBUG_DMA_SM_MASK			(0x7 << 16)
+#define	SSP_DEBUG_DMA_SM_OFFSET			16
+#define	SSP_DEBUG_DMA_SM_DMA_IDLE		(0x0 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_DMAREQ		(0x1 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_DMAACK		(0x2 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_STALL		(0x3 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_BUSY		(0x4 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_DONE		(0x5 << 16)
+#define	SSP_DEBUG_DMA_SM_DMA_COUNT		(0x6 << 16)
+#define	SSP_DEBUG_MMC_SM_MASK			(0xf << 12)
+#define	SSP_DEBUG_MMC_SM_OFFSET			12
+#define	SSP_DEBUG_MMC_SM_MMC_IDLE		(0x0 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_CMD		(0x1 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_TRC		(0x2 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_RESP		(0x3 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_RPRX		(0x4 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_TX			(0x5 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_CTOK		(0x6 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_RX			(0x7 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_CCS		(0x8 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_PUP		(0x9 << 12)
+#define	SSP_DEBUG_MMC_SM_MMC_WAIT		(0xa << 12)
+#define	SSP_DEBUG_CMD_SM_MASK			(0x3 << 10)
+#define	SSP_DEBUG_CMD_SM_OFFSET			10
+#define	SSP_DEBUG_CMD_SM_CSM_IDLE		(0x0 << 10)
+#define	SSP_DEBUG_CMD_SM_CSM_INDEX		(0x1 << 10)
+#define	SSP_DEBUG_CMD_SM_CSM_ARG		(0x2 << 10)
+#define	SSP_DEBUG_CMD_SM_CSM_CRC		(0x3 << 10)
+#define	SSP_DEBUG_SSP_CMD			(1 << 9)
+#define	SSP_DEBUG_SSP_RESP			(1 << 8)
+#define	SSP_DEBUG_SSP_RXD_MASK			0xff
+#define	SSP_DEBUG_SSP_RXD_OFFSET		0
+
+#define	SSP_VERSION_MAJOR_MASK			(0xff << 24)
+#define	SSP_VERSION_MAJOR_OFFSET		24
+#define	SSP_VERSION_MINOR_MASK			(0xff << 16)
+#define	SSP_VERSION_MINOR_OFFSET		16
+#define	SSP_VERSION_STEP_MASK			0xffff
+#define	SSP_VERSION_STEP_OFFSET			0
+
+#endif /* __MX28_REGS_SSP_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h
new file mode 100644
index 0000000..9e19aab
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h
@@ -0,0 +1,258 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 TIMROT Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __MX28_REGS_TIMROT_H__
+#define __MX28_REGS_TIMROT_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_timrot_regs {
+	mxs_reg_32(hw_timrot_rotctrl)
+	mxs_reg_32(hw_timrot_rotcount)
+#if defined(CONFIG_MX23)
+	mxs_reg_32(hw_timrot_timctrl0)
+	mxs_reg_32(hw_timrot_timcount0)
+	mxs_reg_32(hw_timrot_timctrl1)
+	mxs_reg_32(hw_timrot_timcount1)
+	mxs_reg_32(hw_timrot_timctrl2)
+	mxs_reg_32(hw_timrot_timcount2)
+	mxs_reg_32(hw_timrot_timctrl3)
+	mxs_reg_32(hw_timrot_timcount3)
+#elif defined(CONFIG_MX28)
+	mxs_reg_32(hw_timrot_timctrl0)
+	mxs_reg_32(hw_timrot_running_count0)
+	mxs_reg_32(hw_timrot_fixed_count0)
+	mxs_reg_32(hw_timrot_match_count0)
+	mxs_reg_32(hw_timrot_timctrl1)
+	mxs_reg_32(hw_timrot_running_count1)
+	mxs_reg_32(hw_timrot_fixed_count1)
+	mxs_reg_32(hw_timrot_match_count1)
+	mxs_reg_32(hw_timrot_timctrl2)
+	mxs_reg_32(hw_timrot_running_count2)
+	mxs_reg_32(hw_timrot_fixed_count2)
+	mxs_reg_32(hw_timrot_match_count2)
+	mxs_reg_32(hw_timrot_timctrl3)
+	mxs_reg_32(hw_timrot_running_count3)
+	mxs_reg_32(hw_timrot_fixed_count3)
+	mxs_reg_32(hw_timrot_match_count3)
+#endif
+	mxs_reg_32(hw_timrot_version)
+};
+#endif
+
+#define	TIMROT_ROTCTRL_SFTRST				(1 << 31)
+#define	TIMROT_ROTCTRL_CLKGATE				(1 << 30)
+#define	TIMROT_ROTCTRL_ROTARY_PRESENT			(1 << 29)
+#define	TIMROT_ROTCTRL_TIM3_PRESENT			(1 << 28)
+#define	TIMROT_ROTCTRL_TIM2_PRESENT			(1 << 27)
+#define	TIMROT_ROTCTRL_TIM1_PRESENT			(1 << 26)
+#define	TIMROT_ROTCTRL_TIM0_PRESENT			(1 << 25)
+#define	TIMROT_ROTCTRL_STATE_MASK			(0x7 << 22)
+#define	TIMROT_ROTCTRL_STATE_OFFSET			22
+#define	TIMROT_ROTCTRL_DIVIDER_MASK			(0x3f << 16)
+#define	TIMROT_ROTCTRL_DIVIDER_OFFSET			16
+#define	TIMROT_ROTCTRL_RELATIVE				(1 << 12)
+#define	TIMROT_ROTCTRL_OVERSAMPLE_MASK			(0x3 << 10)
+#define	TIMROT_ROTCTRL_OVERSAMPLE_OFFSET		10
+#define	TIMROT_ROTCTRL_OVERSAMPLE_8X			(0x0 << 10)
+#define	TIMROT_ROTCTRL_OVERSAMPLE_4X			(0x1 << 10)
+#define	TIMROT_ROTCTRL_OVERSAMPLE_2X			(0x2 << 10)
+#define	TIMROT_ROTCTRL_OVERSAMPLE_1X			(0x3 << 10)
+#define	TIMROT_ROTCTRL_POLARITY_B			(1 << 9)
+#define	TIMROT_ROTCTRL_POLARITY_A			(1 << 8)
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_B_MASK			(0x7 << 4)
+#elif defined(CONFIG_MX28)
+#define	TIMROT_ROTCTRL_SELECT_B_MASK			(0xf << 4)
+#endif
+#define	TIMROT_ROTCTRL_SELECT_B_OFFSET			4
+#define	TIMROT_ROTCTRL_SELECT_B_NEVER_TICK		(0x0 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM0			(0x1 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM1			(0x2 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM2			(0x3 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM3			(0x4 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM4			(0x5 << 4)
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_B_ROTARYA		(0x6 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_ROTARYB		(0x7 << 4)
+#elif defined(CONFIG_MX28)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM5			(0x6 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM6			(0x7 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_PWM7			(0x8 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_ROTARYA			(0x9 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_ROTARYB			(0xa << 4)
+#endif
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_A_MASK			0x7
+#elif defined(CONFIG_MX28)
+#define	TIMROT_ROTCTRL_SELECT_A_MASK			0xf
+#endif
+#define	TIMROT_ROTCTRL_SELECT_A_OFFSET			0
+#define	TIMROT_ROTCTRL_SELECT_A_NEVER_TICK		0x0
+#define	TIMROT_ROTCTRL_SELECT_A_PWM0			0x1
+#define	TIMROT_ROTCTRL_SELECT_A_PWM1			0x2
+#define	TIMROT_ROTCTRL_SELECT_A_PWM2			0x3
+#define	TIMROT_ROTCTRL_SELECT_A_PWM3			0x4
+#define	TIMROT_ROTCTRL_SELECT_A_PWM4			0x5
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_A_ROTARYA		0x6
+#define	TIMROT_ROTCTRL_SELECT_A_ROTARYB		0x7
+#elif defined(CONFIG_MX28)
+#define	TIMROT_ROTCTRL_SELECT_A_PWM5			0x6
+#define	TIMROT_ROTCTRL_SELECT_A_PWM6			0x7
+#define	TIMROT_ROTCTRL_SELECT_A_PWM7			0x8
+#define	TIMROT_ROTCTRL_SELECT_A_ROTARYA			0x9
+#define	TIMROT_ROTCTRL_SELECT_A_ROTARYB			0xa
+#endif
+
+#define	TIMROT_ROTCOUNT_UPDOWN_MASK			0xffff
+#define	TIMROT_ROTCOUNT_UPDOWN_OFFSET			0
+
+#define	TIMROT_TIMCTRLn_IRQ				(1 << 15)
+#define	TIMROT_TIMCTRLn_IRQ_EN				(1 << 14)
+#if defined(CONFIG_MX28)
+#define	TIMROT_TIMCTRLn_MATCH_MODE			(1 << 11)
+#endif
+#define	TIMROT_TIMCTRLn_POLARITY			(1 << 8)
+#define	TIMROT_TIMCTRLn_UPDATE				(1 << 7)
+#define	TIMROT_TIMCTRLn_RELOAD				(1 << 6)
+#define	TIMROT_TIMCTRLn_PRESCALE_MASK			(0x3 << 4)
+#define	TIMROT_TIMCTRLn_PRESCALE_OFFSET			4
+#define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1		(0x0 << 4)
+#define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2		(0x1 << 4)
+#define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4		(0x2 << 4)
+#define	TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8		(0x3 << 4)
+#define	TIMROT_TIMCTRLn_SELECT_MASK			0xf
+#define	TIMROT_TIMCTRLn_SELECT_OFFSET			0
+#define	TIMROT_TIMCTRLn_SELECT_NEVER_TICK		0x0
+#define	TIMROT_TIMCTRLn_SELECT_PWM0			0x1
+#define	TIMROT_TIMCTRLn_SELECT_PWM1			0x2
+#define	TIMROT_TIMCTRLn_SELECT_PWM2			0x3
+#define	TIMROT_TIMCTRLn_SELECT_PWM3			0x4
+#define	TIMROT_TIMCTRLn_SELECT_PWM4			0x5
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRLn_SELECT_ROTARYA		0x6
+#define	TIMROT_TIMCTRLn_SELECT_ROTARYB		0x7
+#define	TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL		0x8
+#define	TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL		0x9
+#define	TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL		0xa
+#define	TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL		0xb
+#define	TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS		0xc
+#elif defined(CONFIG_MX28)
+#define	TIMROT_TIMCTRLn_SELECT_PWM5			0x6
+#define	TIMROT_TIMCTRLn_SELECT_PWM6			0x7
+#define	TIMROT_TIMCTRLn_SELECT_PWM7			0x8
+#define	TIMROT_TIMCTRLn_SELECT_ROTARYA			0x9
+#define	TIMROT_TIMCTRLn_SELECT_ROTARYB			0xa
+#define	TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL		0xb
+#define	TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL		0xc
+#define	TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL		0xd
+#define	TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL		0xe
+#define	TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS		0xf
+#endif
+
+#if defined(CONFIG_MX23)
+#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK	(0xffff << 16)
+#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET	16
+#elif defined(CONFIG_MX28)
+#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK	0xffffffff
+#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET	0
+#endif
+
+#if defined(CONFIG_MX23)
+#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK		0xffff
+#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET		0
+#elif defined(CONFIG_MX28)
+#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK		0xffffffff
+#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET		0
+#endif
+
+#if defined(CONFIG_MX28)
+#define	TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK		0xffffffff
+#define	TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET		0
+#endif
+
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_MASK		(0xf << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET		16
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK		(0x0 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0		(0x1 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1		(0x2 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2		(0x3 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3		(0x4 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4		(0x5 << 16)
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA		(0x6 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB		(0x7 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL		(0x8 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL		(0x9 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL		(0xa << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL		(0xb << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS		(0xc << 16)
+#elif defined(CONFIG_MX28)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5		(0x6 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6		(0x7 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7		(0x8 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA		(0x9 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB		(0xa << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL		(0xb << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL		(0xc << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL		(0xd << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL		(0xe << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS		(0xf << 16)
+#endif
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRL3_IRQ				(1 << 15)
+#define	TIMROT_TIMCTRL3_IRQ_EN				(1 << 14)
+#define	TIMROT_TIMCTRL3_DUTU_VALID			(1 << 10)
+#endif
+#define	TIMROT_TIMCTRL3_DUTY_CYCLE			(1 << 9)
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRL3_POLARITY_MASK			(0x1 << 8)
+#define	TIMROT_TIMCTRL3_POLARITY_OFFSET		8
+#define	TIMROT_TIMCTRL3_POLARITY_POSITIVE		(0x0 << 8)
+#define	TIMROT_TIMCTRL3_POLARITY_NEGATIVE		(0x1 << 8)
+#define	TIMROT_TIMCTRL3_UPDATE				(1 << 7)
+#define	TIMROT_TIMCTRL3_RELOAD				(1 << 6)
+#define	TIMROT_TIMCTRL3_PRESCALE_MASK			(0x3 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_OFFSET		4
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1		(0x0 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2		(0x1 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4		(0x2 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8		(0x3 << 4)
+#define	TIMROT_TIMCTRL3_SELECT_MASK			0xf
+#define	TIMROT_TIMCTRL3_SELECT_OFFSET			0
+#define	TIMROT_TIMCTRL3_SELECT_NEVER_TICK		0x0
+#define	TIMROT_TIMCTRL3_SELECT_PWM0			0x1
+#define	TIMROT_TIMCTRL3_SELECT_PWM1			0x2
+#define	TIMROT_TIMCTRL3_SELECT_PWM2			0x3
+#define	TIMROT_TIMCTRL3_SELECT_PWM3			0x4
+#define	TIMROT_TIMCTRL3_SELECT_PWM4			0x5
+#define	TIMROT_TIMCTRL3_SELECT_ROTARYA		0x6
+#define	TIMROT_TIMCTRL3_SELECT_ROTARYB		0x7
+#define	TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL		0x8
+#define	TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL		0x9
+#define	TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL		0xa
+#define	TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL		0xb
+#define	TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS		0xc
+#define	TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK	(0xffff << 16)
+#define	TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET	16
+#define	TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK	0xffff
+#define	TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET	0
+#endif
+
+#define	TIMROT_VERSION_MAJOR_MASK			(0xff << 24)
+#define	TIMROT_VERSION_MAJOR_OFFSET			24
+#define	TIMROT_VERSION_MINOR_MASK			(0xff << 16)
+#define	TIMROT_VERSION_MINOR_OFFSET			16
+#define	TIMROT_VERSION_STEP_MASK			0xffff
+#define	TIMROT_VERSION_STEP_OFFSET			0
+
+#endif /* __MX28_REGS_TIMROT_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
new file mode 100644
index 0000000..d89cf27
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-uartapp.h
@@ -0,0 +1,219 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale MXS UARTAPP Register Definitions
+ *
+ * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __ARCH_ARM___MXS_UARTAPP_H
+#define __ARCH_ARM___MXS_UARTAPP_H
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef __ASSEMBLY__
+struct mxs_uartapp_regs {
+	mxs_reg_32(hw_uartapp_ctrl0)
+	mxs_reg_32(hw_uartapp_ctrl1)
+	mxs_reg_32(hw_uartapp_ctrl2)
+	mxs_reg_32(hw_uartapp_linectrl)
+	mxs_reg_32(hw_uartapp_linectrl2)
+	mxs_reg_32(hw_uartapp_intr)
+	mxs_reg_32(hw_uartapp_data)
+	mxs_reg_32(hw_uartapp_stat)
+	mxs_reg_32(hw_uartapp_debug)
+	mxs_reg_32(hw_uartapp_version)
+	mxs_reg_32(hw_uartapp_autobaud)
+};
+#endif
+
+#define UARTAPP_CTRL0_SFTRST_MASK				(1 << 31)
+#define UARTAPP_CTRL0_CLKGATE_MASK			(1 << 30)
+#define UARTAPP_CTRL0_RUN_MASK				(1 << 29)
+#define UARTAPP_CTRL0_RX_SOURCE_MASK			(1 << 28)
+#define UARTAPP_CTRL0_RXTO_ENABLE_MASK			(1 << 27)
+#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET			16
+#define UARTAPP_CTRL0_RXTIMEOUT_MASK			(0x7FF << 16)
+#define UARTAPP_CTRL0_XFER_COUNT_OFFSET			0
+#define UARTAPP_CTRL0_XFER_COUNT_MASK			0xFFFF
+
+#define UARTAPP_CTRL1_RUN_MASK				(1 << 28)
+
+#define UARTAPP_CTRL1_XFER_COUNT_OFFSET			0
+#define UARTAPP_CTRL1_XFER_COUNT_MASK			0xFFFF
+
+#define UARTAPP_CTRL2_INVERT_RTS_MASK			(1 << 31)
+#define UARTAPP_CTRL2_INVERT_CTS_MASK			(1 << 30)
+#define UARTAPP_CTRL2_INVERT_TX_MASK			(1 << 29)
+#define UARTAPP_CTRL2_INVERT_RX_MASK			(1 << 28)
+#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK			(1 << 27)
+#define UARTAPP_CTRL2_DMAONERR_MASK			(1 << 26)
+#define UARTAPP_CTRL2_TXDMAE_MASK				(1 << 25)
+#define UARTAPP_CTRL2_RXDMAE_MASK				(1 << 24)
+#define UARTAPP_CTRL2_RXIFLSEL_OFFSET			20
+#define UARTAPP_CTRL2_RXIFLSEL_MASK			(0x7 << 20)
+
+#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY		(0x0 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER		(0x1 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF		(0x2 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS		(0x3 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS		(0x4 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID5		(0x5 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID6		(0x6 << 20)
+#define UARTAPP_CTRL2_RXIFLSEL_INVALID7		(0x7 << 20)
+#define UARTAPP_CTRL2_TXIFLSEL_OFFSET			16
+#define UARTAPP_CTRL2_TXIFLSEL_MASK			(0x7 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_EMPTY			(0x0 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER		(0x1 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF		(0x2 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS		(0x3 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS		(0x4 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_INVALID5		(0x5 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_INVALID6		(0x6 << 16)
+#define UARTAPP_CTRL2_TXIFLSEL_INVALID7		(0x7 << 16)
+#define UARTAPP_CTRL2_CTSEN_MASK				(1 << 15)
+#define UARTAPP_CTRL2_RTSEN_MASK				(1 << 14)
+#define UARTAPP_CTRL2_OUT2_MASK				(1 << 13)
+#define UARTAPP_CTRL2_OUT1_MASK				(1 << 12)
+#define UARTAPP_CTRL2_RTS_MASK				(1 << 11)
+#define UARTAPP_CTRL2_DTR_MASK				(1 << 10)
+#define UARTAPP_CTRL2_RXE_MASK				(1 << 9)
+#define UARTAPP_CTRL2_TXE_MASK				(1 << 8)
+#define UARTAPP_CTRL2_LBE_MASK				(1 << 7)
+#define UARTAPP_CTRL2_USE_LCR2_MASK			(1 << 6)
+
+#define UARTAPP_CTRL2_SIRLP_MASK				(1 << 2)
+#define UARTAPP_CTRL2_SIREN_MASK				(1 << 1)
+#define UARTAPP_CTRL2_UARTEN_MASK				0x01
+
+#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET			16
+#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK			(0xFFFF << 16)
+#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET		6
+
+#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET		8
+#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK		(0x3F << 8)
+#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK	0x3F
+
+#define UARTAPP_LINECTRL_SPS_MASK				(1 << 7)
+#define UARTAPP_LINECTRL_WLEN_OFFSET			5
+#define UARTAPP_LINECTRL_WLEN_MASK			(0x03 << 5)
+#define UARTAPP_LINECTRL_WLEN_5BITS			(0x00 << 5)
+#define UARTAPP_LINECTRL_WLEN_6BITS			(0x01 << 5)
+#define UARTAPP_LINECTRL_WLEN_7BITS			(0x02 << 5)
+#define UARTAPP_LINECTRL_WLEN_8BITS			(0x03 << 5)
+
+#define UARTAPP_LINECTRL_FEN_MASK				(1 << 4)
+#define UARTAPP_LINECTRL_STP2_MASK			(1 << 3)
+#define UARTAPP_LINECTRL_EPS_MASK				(1 << 2)
+#define UARTAPP_LINECTRL_PEN_MASK				(1 << 1)
+#define UARTAPP_LINECTRL_BRK_MASK				1
+
+#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET		16
+#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK		(0xFFFF << 16)
+#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET	6
+
+#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET		8
+#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK		(0x3F << 8)
+#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK	0x3F
+
+#define UARTAPP_LINECTRL2_SPS_MASK			(1 << 7)
+#define UARTAPP_LINECTRL2_WLEN_OFFSET			5
+#define UARTAPP_LINECTRL2_WLEN_MASK			(0x03 << 5)
+#define UARTAPP_LINECTRL2_WLEN_5BITS			(0x00 << 5)
+#define UARTAPP_LINECTRL2_WLEN_6BITS			(0x01 << 5)
+#define UARTAPP_LINECTRL2_WLEN_7BITS			(0x02 << 5)
+#define UARTAPP_LINECTRL2_WLEN_8BITS			(0x03 << 5)
+
+#define UARTAPP_LINECTRL2_FEN_MASK			(1 << 4)
+#define UARTAPP_LINECTRL2_STP2_MASK			(1 << 3)
+#define UARTAPP_LINECTRL2_EPS_MASK			(1 << 2)
+#define UARTAPP_LINECTRL2_PEN_MASK			(1 << 1)
+
+#define UARTAPP_INTR_ABDIEN_MASK				(1 << 27)
+#define UARTAPP_INTR_OEIEN_MASK				(1 << 26)
+#define UARTAPP_INTR_BEIEN_MASK				(1 << 25)
+#define UARTAPP_INTR_PEIEN_MASK				(1 << 24)
+#define UARTAPP_INTR_FEIEN_MASK				(1 << 23)
+#define UARTAPP_INTR_RTIEN_MASK				(1 << 22)
+#define UARTAPP_INTR_TXIEN_MASK				(1 << 21)
+#define UARTAPP_INTR_RXIEN_MASK				(1 << 20)
+#define UARTAPP_INTR_DSRMIEN_MASK				(1 << 19)
+#define UARTAPP_INTR_DCDMIEN_MASK				(1 << 18)
+#define UARTAPP_INTR_CTSMIEN_MASK				(1 << 17)
+#define UARTAPP_INTR_RIMIEN_MASK				(1 << 16)
+
+#define UARTAPP_INTR_ABDIS_MASK				(1 << 11)
+#define UARTAPP_INTR_OEIS_MASK				(1 << 10)
+#define UARTAPP_INTR_BEIS_MASK				(1 << 9)
+#define UARTAPP_INTR_PEIS_MASK				(1 << 8)
+#define UARTAPP_INTR_FEIS_MASK				(1 << 7)
+#define UARTAPP_INTR_RTIS_MASK				(1 << 6)
+#define UARTAPP_INTR_TXIS_MASK				(1 << 5)
+#define UARTAPP_INTR_RXIS_MASK				(1 << 4)
+#define UARTAPP_INTR_DSRMIS_MASK				(1 << 3)
+#define UARTAPP_INTR_DCDMIS_MASK				(1 << 2)
+#define UARTAPP_INTR_CTSMIS_MASK				(1 << 1)
+#define UARTAPP_INTR_RIMIS_MASK				0x1
+
+#define UARTAPP_DATA_DATA_OFFSET				0
+#define UARTAPP_DATA_DATA_MASK				0xFFFFFFFF
+#define UARTAPP_STAT_PRESENT_MASK				(1 << 31)
+#define UARTAPP_STAT_PRESENT_UNAVAILABLE		(0x0 << 31)
+#define UARTAPP_STAT_PRESENT_AVAILABLE			(0x1 << 31)
+
+#define UARTAPP_STAT_HISPEED_MASK				(1 << 30)
+#define UARTAPP_STAT_HISPEED_UNAVAILABLE		(0x0 << 30)
+#define UARTAPP_STAT_HISPEED_AVAILABLE			(0x1 << 30)
+
+#define UARTAPP_STAT_BUSY_MASK				(1 << 29)
+#define UARTAPP_STAT_CTS_MASK				(1 << 28)
+#define UARTAPP_STAT_TXFE_MASK				(1 << 27)
+#define UARTAPP_STAT_RXFF_MASK				(1 << 26)
+#define UARTAPP_STAT_TXFF_MASK				(1 << 25)
+#define UARTAPP_STAT_RXFE_MASK				(1 << 24)
+#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET			20
+#define UARTAPP_STAT_RXBYTE_INVALID_MASK		(0xF << 20)
+
+#define UARTAPP_STAT_OERR_MASK				(1 << 19)
+#define UARTAPP_STAT_BERR_MASK				(1 << 18)
+#define UARTAPP_STAT_PERR_MASK				(1 << 17)
+#define UARTAPP_STAT_FERR_MASK				(1 << 16)
+#define UARTAPP_STAT_RXCOUNT_OFFSET				0
+#define UARTAPP_STAT_RXCOUNT_MASK				0xFFFF
+
+#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET			16
+#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK				(0xFFFF << 16)
+
+#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET			10
+#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK				(0x3F << 10)
+
+#define UARTAPP_DEBUG_TXDMARUN_MASK			(1 << 5)
+#define UARTAPP_DEBUG_RXDMARUN_MASK			(1 << 4)
+#define UARTAPP_DEBUG_TXCMDEND_MASK			(1 << 3)
+#define UARTAPP_DEBUG_RXCMDEND_MASK			(1 << 2)
+#define UARTAPP_DEBUG_TXDMARQ_MASK			(1 << 1)
+#define UARTAPP_DEBUG_RXDMARQ_MASK			0x01
+
+#define UARTAPP_VERSION_MAJOR_OFFSET			24
+#define UARTAPP_VERSION_MAJOR_MASK			(0xFF << 24)
+
+#define UARTAPP_VERSION_MINOR_OFFSET			16
+#define UARTAPP_VERSION_MINOR_MASK			(0xFF << 16)
+
+#define UARTAPP_VERSION_STEP_OFFSET				0
+#define UARTAPP_VERSION_STEP_MASK				0xFFFF
+
+#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET			24
+#define UARTAPP_AUTOBAUD_REFCHAR1_MASK				(0xFF << 24)
+
+#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET			16
+#define UARTAPP_AUTOBAUD_REFCHAR0_MASK				(0xFF << 16)
+
+#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK			(1 << 4)
+#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK		(1 << 3)
+#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK		(1 << 2)
+#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK		(1 << 1)
+#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK		0x01
+#endif /* __ARCH_ARM___UARTAPP_H */
diff --git a/arch/arm/include/asm/arch-mxs/regs-usb.h b/arch/arm/include/asm/arch-mxs/regs-usb.h
new file mode 100644
index 0000000..8d5168d
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-usb.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 USB OTG Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#ifndef __REGS_USB_H__
+#define __REGS_USB_H__
+
+struct mxs_usb_regs {
+	uint32_t		hw_usbctrl_id;			/* 0x000 */
+	uint32_t		hw_usbctrl_hwgeneral;		/* 0x004 */
+	uint32_t		hw_usbctrl_hwhost;		/* 0x008 */
+	uint32_t		hw_usbctrl_hwdevice;		/* 0x00c */
+	uint32_t		hw_usbctrl_hwtxbuf;		/* 0x010 */
+	uint32_t		hw_usbctrl_hwrxbuf;		/* 0x014 */
+
+	uint32_t		reserved1[26];
+
+	uint32_t		hw_usbctrl_gptimer0ld;		/* 0x080 */
+	uint32_t		hw_usbctrl_gptimer0ctrl;	/* 0x084 */
+	uint32_t		hw_usbctrl_gptimer1ld;		/* 0x088 */
+	uint32_t		hw_usbctrl_gptimer1ctrl;	/* 0x08c */
+	uint32_t		hw_usbctrl_sbuscfg;		/* 0x090 */
+
+	uint32_t		reserved2[27];
+
+	uint32_t		hw_usbctrl_caplength;		/* 0x100 */
+	uint32_t		hw_usbctrl_hcsparams;		/* 0x104 */
+	uint32_t		hw_usbctrl_hccparams;		/* 0x108 */
+
+	uint32_t		reserved3[5];
+
+	uint32_t		hw_usbctrl_dciversion;		/* 0x120 */
+	uint32_t		hw_usbctrl_dccparams;		/* 0x124 */
+
+	uint32_t		reserved4[6];
+
+	uint32_t		hw_usbctrl_usbcmd;		/* 0x140 */
+	uint32_t		hw_usbctrl_usbsts;		/* 0x144 */
+	uint32_t		hw_usbctrl_usbintr;		/* 0x148 */
+	uint32_t		hw_usbctrl_frindex;		/* 0x14c */
+
+	uint32_t		reserved5;
+
+	union {
+		uint32_t	hw_usbctrl_periodiclistbase;	/* 0x154 */
+		uint32_t	hw_usbctrl_deviceaddr;		/* 0x154 */
+	};
+	union {
+		uint32_t	hw_usbctrl_asynclistaddr;	/* 0x158 */
+		uint32_t	hw_usbctrl_endpointlistaddr;	/* 0x158 */
+	};
+
+	uint32_t		hw_usbctrl_ttctrl;		/* 0x15c */
+	uint32_t		hw_usbctrl_burstsize;		/* 0x160 */
+	uint32_t		hw_usbctrl_txfilltuning;	/* 0x164 */
+
+	uint32_t		reserved6;
+
+	uint32_t		hw_usbctrl_ic_usb;		/* 0x16c */
+	uint32_t		hw_usbctrl_ulpi;		/* 0x170 */
+
+	uint32_t		reserved7;
+
+	uint32_t		hw_usbctrl_endptnak;		/* 0x178 */
+	uint32_t		hw_usbctrl_endptnaken;		/* 0x17c */
+
+	uint32_t		reserved8;
+
+	uint32_t		hw_usbctrl_portsc1;		/* 0x184 */
+
+	uint32_t		reserved9[7];
+
+	uint32_t		hw_usbctrl_otgsc;		/* 0x1a4 */
+	uint32_t		hw_usbctrl_usbmode;		/* 0x1a8 */
+	uint32_t		hw_usbctrl_endptsetupstat;	/* 0x1ac */
+	uint32_t		hw_usbctrl_endptprime;		/* 0x1b0 */
+	uint32_t		hw_usbctrl_endptflush;		/* 0x1b4 */
+	uint32_t		hw_usbctrl_endptstat;		/* 0x1b8 */
+	uint32_t		hw_usbctrl_endptcomplete;	/* 0x1bc */
+	uint32_t		hw_usbctrl_endptctrl0;		/* 0x1c0 */
+	uint32_t		hw_usbctrl_endptctrl1;		/* 0x1c4 */
+	uint32_t		hw_usbctrl_endptctrl2;		/* 0x1c8 */
+	uint32_t		hw_usbctrl_endptctrl3;		/* 0x1cc */
+	uint32_t		hw_usbctrl_endptctrl4;		/* 0x1d0 */
+	uint32_t		hw_usbctrl_endptctrl5;		/* 0x1d4 */
+	uint32_t		hw_usbctrl_endptctrl6;		/* 0x1d8 */
+	uint32_t		hw_usbctrl_endptctrl7;		/* 0x1dc */
+};
+
+#define	CLKCTRL_PLL0CTRL0_LFR_SEL_MASK		(0x3 << 28)
+
+#define	HW_USBCTRL_ID_CIVERSION_OFFSET		29
+#define	HW_USBCTRL_ID_CIVERSION_MASK		(0x7 << 29)
+#define	HW_USBCTRL_ID_VERSION_OFFSET		25
+#define	HW_USBCTRL_ID_VERSION_MASK		(0xf << 25)
+#define	HW_USBCTRL_ID_REVISION_OFFSET		21
+#define	HW_USBCTRL_ID_REVISION_MASK		(0xf << 21)
+#define	HW_USBCTRL_ID_TAG_OFFSET		16
+#define	HW_USBCTRL_ID_TAG_MASK			(0x1f << 16)
+#define	HW_USBCTRL_ID_NID_OFFSET		8
+#define	HW_USBCTRL_ID_NID_MASK			(0x3f << 8)
+#define	HW_USBCTRL_ID_ID_OFFSET			0
+#define	HW_USBCTRL_ID_ID_MASK			(0x3f << 0)
+
+#define	HW_USBCTRL_HWGENERAL_SM_OFFSET		9
+#define	HW_USBCTRL_HWGENERAL_SM_MASK		(0x3 << 9)
+#define	HW_USBCTRL_HWGENERAL_PHYM_OFFSET	6
+#define	HW_USBCTRL_HWGENERAL_PHYM_MASK		(0x7 << 6)
+#define	HW_USBCTRL_HWGENERAL_PHYW_OFFSET	4
+#define	HW_USBCTRL_HWGENERAL_PHYW_MASK		(0x3 << 4)
+#define	HW_USBCTRL_HWGENERAL_BWT		(1 << 3)
+#define	HW_USBCTRL_HWGENERAL_CLKC_OFFSET	1
+#define	HW_USBCTRL_HWGENERAL_CLKC_MASK		(0x3 << 1)
+#define	HW_USBCTRL_HWGENERAL_RT			(1 << 0)
+
+#define	HW_USBCTRL_HWHOST_TTPER_OFFSET		24
+#define	HW_USBCTRL_HWHOST_TTPER_MASK		(0xff << 24)
+#define	HW_USBCTRL_HWHOST_TTASY_OFFSET		16
+#define	HW_USBCTRL_HWHOST_TTASY_MASK		(0xff << 19)
+#define	HW_USBCTRL_HWHOST_NPORT_OFFSET		1
+#define	HW_USBCTRL_HWHOST_NPORT_MASK		(0x7 << 1)
+#define	HW_USBCTRL_HWHOST_HC			(1 << 0)
+
+#define	HW_USBCTRL_HWDEVICE_DEVEP_OFFSET	1
+#define	HW_USBCTRL_HWDEVICE_DEVEP_MASK		(0x1f << 1)
+#define	HW_USBCTRL_HWDEVICE_DC			(1 << 0)
+
+#define	HW_USBCTRL_HWTXBUF_TXLCR		(1 << 31)
+#define	HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET	16
+#define	HW_USBCTRL_HWTXBUF_TXCHANADD_MASK	(0xff << 16)
+#define	HW_USBCTRL_HWTXBUF_TXADD_OFFSET		8
+#define	HW_USBCTRL_HWTXBUF_TXADD_MASK		(0xff << 8)
+#define	HW_USBCTRL_HWTXBUF_TXBURST_OFFSET	0
+#define	HW_USBCTRL_HWTXBUF_TXBURST_MASK		0xff
+
+#define	HW_USBCTRL_HWRXBUF_RXADD_OFFSET		8
+#define	HW_USBCTRL_HWRXBUF_RXADD_MASK		(0xff << 8)
+#define	HW_USBCTRL_HWRXBUF_RXBURST_OFFSET	0
+#define	HW_USBCTRL_HWRXBUF_RXBURST_MASK		0xff
+
+#define	HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET	0
+#define	HW_USBCTRL_GPTIMERLD_GPTLD_MASK		0xffffff
+
+#define	HW_USBCTRL_GPTIMERCTRL_GPTRUN		(1 << 31)
+#define	HW_USBCTRL_GPTIMERCTRL_GPTRST		(1 << 30)
+#define	HW_USBCTRL_GPTIMERCTRL_GPTMODE		(1 << 24)
+#define	HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET	0
+#define	HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK	0xffffff
+
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET	0
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_MASK	0x7
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR	0x0
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4	0x1
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8	0x2
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16	0x3
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4	0x5
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8	0x6
+#define	HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16	0x7
+
+#endif	/* __REGS_USB_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/regs-usbphy.h b/arch/arm/include/asm/arch-mxs/regs-usbphy.h
new file mode 100644
index 0000000..643feab
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/regs-usbphy.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 USB PHY Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#ifndef __REGS_USBPHY_H__
+#define __REGS_USBPHY_H__
+
+struct mxs_usbphy_regs {
+	mxs_reg_32(hw_usbphy_pwd)
+	mxs_reg_32(hw_usbphy_tx)
+	mxs_reg_32(hw_usbphy_rx)
+	mxs_reg_32(hw_usbphy_ctrl)
+	mxs_reg_32(hw_usbphy_status)
+	mxs_reg_32(hw_usbphy_debug)
+	mxs_reg_32(hw_usbphy_debug0_status)
+	mxs_reg_32(hw_usbphy_debug1)
+	mxs_reg_32(hw_usbphy_version)
+	mxs_reg_32(hw_usbphy_ip)
+};
+
+#define	USBPHY_PWD_RXPWDRX				(1 << 20)
+#define	USBPHY_PWD_RXPWDDIFF				(1 << 19)
+#define	USBPHY_PWD_RXPWD1PT1				(1 << 18)
+#define	USBPHY_PWD_RXPWDENV				(1 << 17)
+#define	USBPHY_PWD_TXPWDV2I				(1 << 12)
+#define	USBPHY_PWD_TXPWDIBIAS				(1 << 11)
+#define	USBPHY_PWD_TXPWDFS				(1 << 10)
+
+#define	USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET		26
+#define	USBPHY_TX_USBPHY_TX_EDGECTRL_MASK		(0x7 << 26)
+#define	USBPHY_TX_USBPHY_TX_SYNC_INVERT			(1 << 25)
+#define	USBPHY_TX_USBPHY_TX_SYNC_MUX			(1 << 24)
+#define	USBPHY_TX_TXENCAL45DP				(1 << 21)
+#define	USBPHY_TX_TXCAL45DP_OFFSET			16
+#define	USBPHY_TX_TXCAL45DP_MASK			(0xf << 16)
+#define	USBPHY_TX_TXENCAL45DM				(1 << 13)
+#define	USBPHY_TX_TXCAL45DM_OFFSET			8
+#define	USBPHY_TX_TXCAL45DM_MASK			(0xf << 8)
+#define	USBPHY_TX_D_CAL_OFFSET				0
+#define	USBPHY_TX_D_CAL_MASK				0xf
+
+#define	USBPHY_RX_RXDBYPASS				(1 << 22)
+#define	USBPHY_RX_DISCONADJ_OFFSET			4
+#define	USBPHY_RX_DISCONADJ_MASK			(0x7 << 4)
+#define	USBPHY_RX_ENVADJ_OFFSET				0
+#define	USBPHY_RX_ENVADJ_MASK				0x7
+
+#define	USBPHY_CTRL_SFTRST				(1 << 31)
+#define	USBPHY_CTRL_CLKGATE				(1 << 30)
+#define	USBPHY_CTRL_UTMI_SUSPENDM			(1 << 29)
+#define	USBPHY_CTRL_HOST_FORCE_LS_SE0			(1 << 28)
+#define	USBPHY_CTRL_ENAUTOSET_USBCLKS			(1 << 26)
+#define	USBPHY_CTRL_ENAUTOCLR_USBCLKGATE		(1 << 25)
+#define	USBPHY_CTRL_FSDLL_RST_EN			(1 << 24)
+#define	USBPHY_CTRL_ENVBUSCHG_WKUP			(1 << 23)
+#define	USBPHY_CTRL_ENIDCHG_WKUP			(1 << 22)
+#define	USBPHY_CTRL_ENDPDMCHG_WKUP			(1 << 21)
+#define	USBPHY_CTRL_ENAUTOCLR_PHY_PWD			(1 << 20)
+#define	USBPHY_CTRL_ENAUTOCLR_CLKGATE			(1 << 19)
+#define	USBPHY_CTRL_ENAUTO_PWRON_PLL			(1 << 18)
+#define	USBPHY_CTRL_WAKEUP_IRQ				(1 << 17)
+#define	USBPHY_CTRL_ENIRQWAKEUP				(1 << 16)
+#define	USBPHY_CTRL_ENUTMILEVEL3			(1 << 15)
+#define	USBPHY_CTRL_ENUTMILEVEL2			(1 << 14)
+#define	USBPHY_CTRL_DATA_ON_LRADC			(1 << 13)
+#define	USBPHY_CTRL_DEVPLUGIN_IRQ			(1 << 12)
+#define	USBPHY_CTRL_ENIRQDEVPLUGIN			(1 << 11)
+#define	USBPHY_CTRL_RESUME_IRQ				(1 << 10)
+#define	USBPHY_CTRL_ENIRQRESUMEDETECT			(1 << 9)
+#define	USBPHY_CTRL_RESUMEIRQSTICKY			(1 << 8)
+#define	USBPHY_CTRL_ENOTGIDDETECT			(1 << 7)
+#define	USBPHY_CTRL_DEVPLUGIN_POLARITY			(1 << 5)
+#define	USBPHY_CTRL_ENDEVPLUGINDETECT			(1 << 4)
+#define	USBPHY_CTRL_HOSTDISCONDETECT_IRQ		(1 << 3)
+#define	USBPHY_CTRL_ENIRQHOSTDISCON			(1 << 2)
+#define	USBPHY_CTRL_ENHOSTDISCONDETECT			(1 << 1)
+
+#define	USBPHY_STATUS_RESUME_STATUS			(1 << 10)
+#define	USBPHY_STATUS_OTGID_STATUS			(1 << 8)
+#define	USBPHY_STATUS_DEVPLUGIN_STATUS			(1 << 6)
+#define	USBPHY_STATUS_HOSTDISCONDETECT_STATUS		(1 << 3)
+
+#define	USBPHY_DEBUG_CLKGATE				(1 << 30)
+#define	USBPHY_DEBUG_HOST_RESUME_DEBUG			(1 << 29)
+#define	USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET		25
+#define	USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK		(0xf << 25)
+#define	USBPHY_DEBUG_ENSQUELCHRESET			(1 << 24)
+#define	USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET		16
+#define	USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK		(0x1f << 16)
+#define	USBPHY_DEBUG_ENTX2RXCOUNT			(1 << 12)
+#define	USBPHY_DEBUG_TX2RXCOUNT_OFFSET			8
+#define	USBPHY_DEBUG_TX2RXCOUNT_MASK			(0xf << 8)
+#define	USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET		4
+#define	USBPHY_DEBUG_ENHSTPULLDOWN_MASK			(0x3 << 4)
+#define	USBPHY_DEBUG_HSTPULLDOWN_OFFSET			2
+#define	USBPHY_DEBUG_HSTPULLDOWN_MASK			(0x3 << 2)
+#define	USBPHY_DEBUG_DEBUG_INTERFACE_HOLD		(1 << 1)
+#define	USBPHY_DEBUG_OTGIDPIDLOCK			(1 << 0)
+
+#define	USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET	26
+#define	USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK		(0x3f << 26)
+#define	USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET	16
+#define	USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK		(0x3ff << 16)
+#define	USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET		0
+#define	USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK		0xffff
+
+#define	USBPHY_DEBUG1_ENTAILADJVD_OFFSET		13
+#define	USBPHY_DEBUG1_ENTAILADJVD_MASK			(0x3 << 13)
+#define	USBPHY_DEBUG1_ENTX2TX				(1 << 12)
+#define	USBPHY_DEBUG1_DBG_ADDRESS_OFFSET		0
+#define	USBPHY_DEBUG1_DBG_ADDRESS_MASK			0xf
+
+#define	USBPHY_VERSION_MAJOR_MASK			(0xff << 24)
+#define	USBPHY_VERSION_MAJOR_OFFSET			24
+#define	USBPHY_VERSION_MINOR_MASK			(0xff << 16)
+#define	USBPHY_VERSION_MINOR_OFFSET			16
+#define	USBPHY_VERSION_STEP_MASK			0xffff
+#define	USBPHY_VERSION_STEP_OFFSET			0
+
+#define	USBPHY_IP_DIV_SEL_OFFSET			23
+#define	USBPHY_IP_DIV_SEL_MASK				(0x3 << 23)
+#define	USBPHY_IP_LFR_SEL_OFFSET			21
+#define	USBPHY_IP_LFR_SEL_MASK				(0x3 << 21)
+#define	USBPHY_IP_CP_SEL_OFFSET				19
+#define	USBPHY_IP_CP_SEL_MASK				(0x3 << 19)
+#define	USBPHY_IP_TSTI_TX_DP				(1 << 18)
+#define	USBPHY_IP_TSTI_TX_DM				(1 << 17)
+#define	USBPHY_IP_ANALOG_TESTMODE			(1 << 16)
+#define	USBPHY_IP_EN_USB_CLKS				(1 << 2)
+#define	USBPHY_IP_PLL_LOCKED				(1 << 1)
+#define	USBPHY_IP_PLL_POWER				(1 << 0)
+
+#endif	/* __REGS_USBPHY_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
new file mode 100644
index 0000000..6478692
--- /dev/null
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX23/i.MX28 specific functions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#ifndef __MXS_SYS_PROTO_H__
+#define __MXS_SYS_PROTO_H__
+
+#include <asm/mach-imx/sys_proto.h>
+
+int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
+
+#ifdef CONFIG_SPL_BUILD
+
+#if defined(CONFIG_MX23)
+#include <asm/arch/iomux-mx23.h>
+#elif defined(CONFIG_MX28)
+#include <asm/arch/iomux-mx28.h>
+#endif
+
+void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
+			 const iomux_cfg_t *iomux_setup,
+			 const unsigned int iomux_size);
+
+void mxs_power_switch_dcdc_clocksource(uint32_t freqsel);
+#endif
+
+struct mxs_pair {
+	uint8_t	boot_pads;
+	uint8_t boot_mask;
+	const char *mode;
+};
+
+static const struct mxs_pair mxs_boot_modes[] = {
+#if defined(CONFIG_MX23)
+	{ 0x00, 0x0f, "USB" },
+	{ 0x01, 0x1f, "I2C, master" },
+	{ 0x02, 0x1f, "SSP SPI #1, master, NOR" },
+	{ 0x03, 0x1f, "SSP SPI #2, master, NOR" },
+	{ 0x04, 0x1f, "NAND" },
+	{ 0x06, 0x1f, "JTAG" },
+	{ 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
+	{ 0x09, 0x1f, "SSP SD/MMC #0" },
+	{ 0x0a, 0x1f, "SSP SD/MMC #1" },
+	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
+#elif defined(CONFIG_MX28)
+	{ 0x00, 0x0f, "USB #0" },
+	{ 0x01, 0x1f, "I2C #0, master, 3V3" },
+	{ 0x11, 0x1f, "I2C #0, master, 1V8" },
+	{ 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
+	{ 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
+	{ 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
+	{ 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
+	{ 0x04, 0x1f, "NAND, 3V3" },
+	{ 0x14, 0x1f, "NAND, 1V8" },
+	{ 0x06, 0x1f, "JTAG" },
+	{ 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
+	{ 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
+	{ 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
+	{ 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
+	{ 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
+	{ 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
+	{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
+#endif
+};
+
+#define MXS_BM_USB			0x00
+#define MXS_BM_I2C_MASTER_3V3		0x01
+#define MXS_BM_I2C_MASTER_1V8		0x11
+#define MXS_BM_SPI2_MASTER_3V3_NOR	0x02
+#define MXS_BM_SPI2_MASTER_1V8_NOR	0x12
+#define MXS_BM_SPI3_MASTER_3V3_NOR	0x03
+#define MXS_BM_SPI3_MASTER_1V8_NOR	0x13
+#define MXS_BM_NAND_3V3			0x04
+#define MXS_BM_NAND_1V8			0x14
+#define MXS_BM_JTAG			0x06
+#define MXS_BM_SPI3_MASTER_3V3_EEPROM	0x08
+#define MXS_BM_SPI3_MASTER_1V8_EEPROM	0x18
+#define MXS_BM_SDMMC0_3V3		0x09
+#define MXS_BM_SDMMC0_1V8		0x19
+#define MXS_BM_SDMMC1_3V3		0x0a
+#define MXS_BM_SDMMC1_1V8		0x1a
+
+#define MXS_SPL_DATA ((struct mxs_spl_data *)(CONFIG_SYS_TEXT_BASE - 0x200))
+
+struct mxs_spl_data {
+	uint8_t		boot_mode_idx;
+	uint32_t	mem_dram_size;
+};
+
+int mxs_dram_init(void);
+
+#endif	/* __SYS_PROTO_H__ */
diff --git a/arch/arm/include/asm/arch-omap3/am35x_def.h b/arch/arm/include/asm/arch-omap3/am35x_def.h
new file mode 100644
index 0000000..33f6db1
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/am35x_def.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * am35x_def.h - TI's AM35x specific definitions.
+ *
+ * Based on arch/arm/include/asm/arch-omap3/cpu.h
+ *
+ * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
+ *
+ * Copyright (c) 2010 Texas Instruments Incorporated
+ */
+
+#ifndef _AM35X_DEF_H_
+#define _AM35X_DEF_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+
+/* LVL_INTR_CLEAR bits */
+#define USBOTGSS_INT_CLR	(1 << 4)
+
+/* IP_SW_RESET bits */
+#define USBOTGSS_SW_RST		(1 << 0)	/* reset USBOTG */
+#define CPGMACSS_SW_RST		(1 << 1)	/* reset CPGMAC */
+
+/* DEVCONF2 bits */
+#define CONF2_PHY_GPIOMODE	(1 << 23)
+#define CONF2_OTGMODE		(3 << 14)
+#define CONF2_NO_OVERRIDE	(0 << 14)
+#define CONF2_FORCE_HOST	(1 << 14)
+#define CONF2_FORCE_DEVICE	(2 << 14)
+#define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
+#define CONF2_SESENDEN		(1 << 13)
+#define CONF2_VBDTCTEN		(1 << 12)
+#define CONF2_REFFREQ_24MHZ	(2 << 8)
+#define CONF2_REFFREQ_26MHZ	(7 << 8)
+#define CONF2_REFFREQ_13MHZ	(6 << 8)
+#define CONF2_REFFREQ		(0xf << 8)
+#define CONF2_PHYCLKGD		(1 << 7)
+#define CONF2_VBUSSENSE		(1 << 6)
+#define CONF2_PHY_PLLON		(1 << 5)
+#define CONF2_RESET		(1 << 4)
+#define CONF2_PHYPWRDN		(1 << 3)
+#define CONF2_OTGPWRDN		(1 << 2)
+#define CONF2_DATPOL		(1 << 1)
+
+/* General register mappings of system control module */
+#define AM35X_SCM_GEN_BASE	0x48002270
+struct am35x_scm_general {
+	u32 res1[0xC4];		/* 0x000 - 0x30C */
+	u32 devconf2;		/* 0x310 */
+	u32 devconf3;		/* 0x314 */
+	u32 res2[0x2];		/* 0x318 - 0x31C */
+	u32 cba_priority;	/* 0x320 */
+	u32 lvl_intr_clr;	/* 0x324 */
+	u32 ip_sw_reset;	/* 0x328 */
+	u32 ipss_clk_ctrl;	/* 0x32C */
+};
+#define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE)
+
+#define AM35XX_IPSS_USBOTGSS_BASE	0x5C040000
+
+#endif /*__ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#endif /* _AM35X_DEF_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h
new file mode 100644
index 0000000..ac537fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/clock.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ */
+#ifndef _CLOCKS_H_
+#define _CLOCKS_H_
+
+#define LDELAY		12000000
+
+#define S12M		12000000
+#define S13M		13000000
+#define S19_2M		19200000
+#define S24M		24000000
+#define S26M		26000000
+#define S38_4M		38400000
+
+#define FCK_IVA2_ON	0x00000001
+#define FCK_CORE1_ON	0x03fffe29
+#define ICK_CORE1_ON	0x3ffffffb
+#define ICK_CORE2_ON	0x0000001f
+#define FCK_WKUP_ON	0x000000e9
+#define ICK_WKUP_ON	0x0000003f
+#define FCK_DSS_ON	0x00000005
+#define ICK_DSS_ON	0x00000001
+#define FCK_CAM_ON	0x00000001
+#define ICK_CAM_ON	0x00000001
+
+/* Used to index into DPLL parameter tables */
+typedef struct {
+	unsigned int m;
+	unsigned int n;
+	unsigned int fsel;
+	unsigned int m2;
+} dpll_param;
+
+struct dpll_per_36x_param {
+	unsigned int sys_clk;
+	unsigned int m;
+	unsigned int n;
+	unsigned int m2;
+	unsigned int m3;
+	unsigned int m4;
+	unsigned int m5;
+	unsigned int m6;
+	unsigned int m2div;
+};
+
+/* Following functions are exported from lowlevel_init.S */
+extern dpll_param *get_mpu_dpll_param(void);
+extern dpll_param *get_iva_dpll_param(void);
+extern dpll_param *get_core_dpll_param(void);
+extern dpll_param *get_per_dpll_param(void);
+extern dpll_param *get_per2_dpll_param(void);
+
+extern dpll_param *get_36x_mpu_dpll_param(void);
+extern dpll_param *get_36x_iva_dpll_param(void);
+extern dpll_param *get_36x_core_dpll_param(void);
+extern dpll_param *get_36x_per_dpll_param(void);
+extern dpll_param *get_36x_per2_dpll_param(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
new file mode 100644
index 0000000..48bb391
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
@@ -0,0 +1,347 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ */
+#ifndef _CLOCKS_OMAP3_H_
+#define _CLOCKS_OMAP3_H_
+
+#define PLL_STOP		1	/* PER & IVA */
+#define PLL_LOW_POWER_BYPASS	5	/* MPU, IVA & CORE */
+#define PLL_FAST_RELOCK_BYPASS	6	/* CORE */
+#define PLL_LOCK		7	/* MPU, IVA, CORE & PER */
+
+/*
+ * The following configurations are OPP and SysClk value independant
+ * and hence are defined here. All the other DPLL related values are
+ * tabulated in lowlevel_init.S.
+ */
+
+/* CORE DPLL */
+#define CORE_M3X2	2	/* 332MHz : CM_CLKSEL1_EMU */
+#define CORE_SSI_DIV	3	/* 221MHz : CM_CLKSEL_CORE */
+#define CORE_FUSB_DIV	2	/* 41.5MHz: */
+#define CORE_L4_DIV	2	/* 83MHz  : L4 */
+#define CORE_L3_DIV	2	/* 166MHz : L3 {DDR} */
+#define GFX_DIV		2	/* 83MHz  : CM_CLKSEL_GFX */
+#define GFX_DIV_36X	5	/* 200MHz : CM_CLKSEL_GFX */
+#define WKUP_RSM	2	/* 41.5MHz: CM_CLKSEL_WKUP */
+
+/* PER DPLL */
+#define PER_M6X2	3	/* 288MHz: CM_CLKSEL1_EMU */
+#define PER_M5X2	4	/* 216MHz: CM_CLKSEL_CAM */
+#define PER_M4X2	2	/* 432MHz: CM_CLKSEL_DSS-dss1 */
+#define PER_M3X2	16	/* 54MHz : CM_CLKSEL_DSS-tv */
+
+#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50))
+
+/* MPU DPLL */
+
+#define MPU_M_12_ES1		0x0FE
+#define MPU_N_12_ES1		0x07
+#define MPU_FSEL_12_ES1		0x05
+#define MPU_M2_12_ES1		0x01
+
+#define MPU_M_12_ES2		0x0FA
+#define MPU_N_12_ES2		0x05
+#define MPU_FSEL_12_ES2		0x07
+#define MPU_M2_ES2		0x01
+
+#define MPU_M_12		0x085
+#define MPU_N_12		0x05
+#define MPU_FSEL_12		0x07
+#define MPU_M2_12		0x01
+
+#define MPU_M_13_ES1		0x17D
+#define MPU_N_13_ES1		0x0C
+#define MPU_FSEL_13_ES1		0x03
+#define MPU_M2_13_ES1		0x01
+
+#define MPU_M_13_ES2		0x258
+#define MPU_N_13_ES2		0x0C
+#define MPU_FSEL_13_ES2		0x03
+#define MPU_M2_13_ES2		0x01
+
+#define MPU_M_13		0x10A
+#define MPU_N_13		0x0C
+#define MPU_FSEL_13		0x03
+#define MPU_M2_13		0x01
+
+#define MPU_M_19P2_ES1		0x179
+#define MPU_N_19P2_ES1		0x12
+#define MPU_FSEL_19P2_ES1	0x04
+#define MPU_M2_19P2_ES1		0x01
+
+#define MPU_M_19P2_ES2		0x271
+#define MPU_N_19P2_ES2		0x17
+#define MPU_FSEL_19P2_ES2	0x03
+#define MPU_M2_19P2_ES2		0x01
+
+#define MPU_M_19P2		0x14C
+#define MPU_N_19P2		0x17
+#define MPU_FSEL_19P2		0x03
+#define MPU_M2_19P2		0x01
+
+#define MPU_M_26_ES1		0x17D
+#define MPU_N_26_ES1		0x19
+#define MPU_FSEL_26_ES1		0x03
+#define MPU_M2_26_ES1		0x01
+
+#define MPU_M_26_ES2		0x0FA
+#define MPU_N_26_ES2		0x0C
+#define MPU_FSEL_26_ES2		0x07
+#define MPU_M2_26_ES2		0x01
+
+#define MPU_M_26		0x085
+#define MPU_N_26		0x0C
+#define MPU_FSEL_26		0x07
+#define MPU_M2_26		0x01
+
+#define MPU_M_38P4_ES1		0x1FA
+#define MPU_N_38P4_ES1		0x32
+#define MPU_FSEL_38P4_ES1	0x03
+#define MPU_M2_38P4_ES1		0x01
+
+#define MPU_M_38P4_ES2		0x271
+#define MPU_N_38P4_ES2		0x2F
+#define MPU_FSEL_38P4_ES2	0x03
+#define MPU_M2_38P4_ES2		0x01
+
+#define MPU_M_38P4		0x14C
+#define MPU_N_38P4		0x2F
+#define MPU_FSEL_38P4		0x03
+#define MPU_M2_38P4		0x01
+
+/* IVA DPLL */
+
+#define IVA_M_12_ES1		0x07D
+#define IVA_N_12_ES1		0x05
+#define IVA_FSEL_12_ES1		0x07
+#define IVA_M2_12_ES1		0x01
+
+#define IVA_M_12_ES2		0x0B4
+#define IVA_N_12_ES2		0x05
+#define IVA_FSEL_12_ES2		0x07
+#define IVA_M2_12_ES2		0x01
+
+#define IVA_M_12		0x085
+#define IVA_N_12		0x05
+#define IVA_FSEL_12		0x07
+#define IVA_M2_12		0x01
+
+#define IVA_M_13_ES1		0x0FA
+#define IVA_N_13_ES1		0x0C
+#define IVA_FSEL_13_ES1		0x03
+#define IVA_M2_13_ES1		0x01
+
+#define IVA_M_13_ES2		0x168
+#define IVA_N_13_ES2		0x0C
+#define IVA_FSEL_13_ES2		0x03
+#define IVA_M2_13_ES2		0x01
+
+#define IVA_M_13		0x10A
+#define IVA_N_13		0x0C
+#define IVA_FSEL_13		0x03
+#define IVA_M2_13		0x01
+
+#define IVA_M_19P2_ES1		0x082
+#define IVA_N_19P2_ES1		0x09
+#define IVA_FSEL_19P2_ES1	0x07
+#define IVA_M2_19P2_ES1		0x01
+
+#define IVA_M_19P2_ES2		0x0E1
+#define IVA_N_19P2_ES2		0x0B
+#define IVA_FSEL_19P2_ES2	0x06
+#define IVA_M2_19P2_ES2		0x01
+
+#define IVA_M_19P2		0x14C
+#define IVA_N_19P2		0x17
+#define IVA_FSEL_19P2		0x03
+#define IVA_M2_19P2		0x01
+
+#define IVA_M_26_ES1		0x07D
+#define IVA_N_26_ES1		0x0C
+#define IVA_FSEL_26_ES1		0x07
+#define IVA_M2_26_ES1		0x01
+
+#define IVA_M_26_ES2		0x0B4
+#define IVA_N_26_ES2		0x0C
+#define IVA_FSEL_26_ES2		0x07
+#define IVA_M2_26_ES2		0x01
+
+#define IVA_M_26		0x085
+#define IVA_N_26		0x0C
+#define IVA_FSEL_26		0x07
+#define IVA_M2_26		0x01
+
+#define IVA_M_38P4_ES1		0x13F
+#define IVA_N_38P4_ES1		0x30
+#define IVA_FSEL_38P4_ES1	0x03
+#define IVA_M2_38P4_ES1		0x01
+
+#define IVA_M_38P4_ES2		0x0E1
+#define IVA_N_38P4_ES2		0x17
+#define IVA_FSEL_38P4_ES2	0x06
+#define IVA_M2_38P4_ES2		0x01
+
+#define IVA_M_38P4		0x14C
+#define IVA_N_38P4		0x2F
+#define IVA_FSEL_38P4		0x03
+#define IVA_M2_38P4		0x01
+
+/* CORE DPLL */
+
+#define CORE_M_12		0xA6
+#define CORE_N_12		0x05
+#define CORE_FSEL_12		0x07
+#define CORE_M2_12		0x01	/* M3 of 2 */
+
+#define CORE_M_12_ES1		0x19F
+#define CORE_N_12_ES1		0x0E
+#define CORE_FSL_12_ES1		0x03
+#define CORE_M2_12_ES1		0x1	/* M3 of 2 */
+
+#define CORE_M_13		0x14C
+#define CORE_N_13		0x0C
+#define CORE_FSEL_13		0x03
+#define CORE_M2_13		0x01	/* M3 of 2 */
+
+#define CORE_M_13_ES1		0x1B2
+#define CORE_N_13_ES1		0x10
+#define CORE_FSL_13_ES1		0x03
+#define CORE_M2_13_ES1		0x01	/* M3 of 2 */
+
+#define CORE_M_19P2		0x19F
+#define CORE_N_19P2		0x17
+#define CORE_FSEL_19P2		0x03
+#define CORE_M2_19P2		0x01	/* M3 of 2 */
+
+#define CORE_M_19P2_ES1		0x19F
+#define CORE_N_19P2_ES1		0x17
+#define CORE_FSL_19P2_ES1	0x03
+#define CORE_M2_19P2_ES1	0x01	/* M3 of 2 */
+
+#define CORE_M_26		0xA6
+#define CORE_N_26		0x0C
+#define CORE_FSEL_26		0x07
+#define CORE_M2_26		0x01	/* M3 of 2 */
+
+#define CORE_M_26_ES1		0x1B2
+#define CORE_N_26_ES1		0x21
+#define CORE_FSL_26_ES1		0x03
+#define CORE_M2_26_ES1		0x01	/* M3 of 2 */
+
+#define CORE_M_38P4		0x19F
+#define CORE_N_38P4		0x2F
+#define CORE_FSEL_38P4		0x03
+#define CORE_M2_38P4		0x01	/* M3 of 2 */
+
+#define CORE_M_38P4_ES1		0x19F
+#define CORE_N_38P4_ES1		0x2F
+#define CORE_FSL_38P4_ES1	0x03
+#define CORE_M2_38P4_ES1	0x01	/* M3 of 2 */
+
+/* PER DPLL */
+
+#define PER_M_12		0xD8
+#define PER_N_12		0x05
+#define PER_FSEL_12		0x07
+#define PER_M2_12		0x09
+
+#define PER_M_13		0x1B0
+#define PER_N_13		0x0C
+#define PER_FSEL_13		0x03
+#define PER_M2_13		0x09
+
+#define PER_M_19P2		0xE1
+#define PER_N_19P2		0x09
+#define PER_FSEL_19P2		0x07
+#define PER_M2_19P2		0x09
+
+#define PER_M_26		0xD8
+#define PER_N_26		0x0C
+#define PER_FSEL_26		0x07
+#define PER_M2_26		0x09
+
+#define PER_M_38P4		0xE1
+#define PER_N_38P4		0x13
+#define PER_FSEL_38P4		0x07
+#define PER_M2_38P4		0x09
+
+/* PER2 DPLL */
+#define PER2_M_12		0x78
+#define PER2_N_12		0x0B
+#define PER2_FSEL_12		0x03
+#define PER2_M2_12		0x01
+
+#define PER2_M_13		0x78
+#define PER2_N_13		0x0C
+#define PER2_FSEL_13		0x03
+#define PER2_M2_13		0x01
+
+#define PER2_M_19P2		0x2EE
+#define PER2_N_19P2		0x0B
+#define PER2_FSEL_19P2		0x06
+#define PER2_M2_19P2		0x0A
+
+#define PER2_M_26		0x78
+#define PER2_N_26		0x0C
+#define PER2_FSEL_26		0x03
+#define PER2_M2_26		0x01
+
+#define PER2_M_38P4		0x2EE
+#define PER2_N_38P4		0x0B
+#define PER2_FSEL_38P4		0x06
+#define PER2_M2_38P4		0x0A
+
+/* 36XX PER DPLL */
+
+#define PER_36XX_M_12		0x1B0
+#define PER_36XX_N_12		0x05
+#define PER_36XX_FSEL_12	0x07
+#define PER_36XX_M2_12		0x09
+
+#define PER_36XX_M_13		0x360
+#define PER_36XX_N_13		0x0C
+#define PER_36XX_FSEL_13	0x03
+#define PER_36XX_M2_13		0x09
+
+#define PER_36XX_M_19P2		0x1C2
+#define PER_36XX_N_19P2		0x09
+#define PER_36XX_FSEL_19P2	0x07
+#define PER_36XX_M2_19P2	0x09
+
+#define PER_36XX_M_26		0x1B0
+#define PER_36XX_N_26		0x0C
+#define PER_36XX_FSEL_26	0x07
+#define PER_36XX_M2_26		0x09
+
+#define PER_36XX_M_38P4		0x1C2
+#define PER_36XX_N_38P4		0x13
+#define PER_36XX_FSEL_38P4	0x07
+#define PER_36XX_M2_38P4	0x09
+
+/* 36XX PER2 DPLL */
+
+#define PER2_36XX_M_12		0x50
+#define PER2_36XX_N_12		0x00
+#define PER2_36XX_M2_12		0x08
+
+#define PER2_36XX_M_13		0x1BB
+#define PER2_36XX_N_13		0x05
+#define PER2_36XX_M2_13		0x08
+
+#define PER2_36XX_M_19P2		0x32
+#define PER2_36XX_N_19P2		0x00
+#define PER2_36XX_M2_19P2		0x08
+
+#define PER2_36XX_M_26		0x1BB
+#define PER2_36XX_N_26		0x0B
+#define PER2_36XX_M2_26		0x08
+
+#define PER2_36XX_M_38P4		0x19
+#define PER2_36XX_N_38P4		0x00
+#define PER2_36XX_M2_38P4		0x08
+
+#endif	/* endif _CLOCKS_OMAP3_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
new file mode 100644
index 0000000..3f0182e
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -0,0 +1,504 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/* Register offsets of common modules */
+/* Control */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct ctrl {
+	u8 res1[0xC0];
+	u16 gpmc_nadv_ale;	/* 0xC0 */
+	u16 gpmc_noe;		/* 0xC2 */
+	u16 gpmc_nwe;		/* 0xC4 */
+	u8 res2[0x22A];
+	u32 status;		/* 0x2F0 */
+	u32 gpstatus;		/* 0x2F4 */
+	u8 res3[0x08];
+	u32 rpubkey_0;		/* 0x300 */
+	u32 rpubkey_1;		/* 0x304 */
+	u32 rpubkey_2;		/* 0x308 */
+	u32 rpubkey_3;		/* 0x30C */
+	u32 rpubkey_4;		/* 0x310 */
+	u8 res4[0x04];
+	u32 randkey_0;		/* 0x318 */
+	u32 randkey_1;		/* 0x31C */
+	u32 randkey_2;		/* 0x320 */
+	u32 randkey_3;		/* 0x324 */
+	u8 res5[0x124];
+	u32 ctrl_omap_stat;	/* 0x44C */
+};
+#else /* __ASSEMBLY__ */
+#define CONTROL_STATUS		0x2F0
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct ctrl_id {
+	u8 res1[0x4];
+	u32 idcode;		/* 0x04 */
+	u32 prod_id;		/* 0x08 */
+	u32 sku_id;		/* 0x0c */
+	u8 res2[0x08];
+	u32 die_id_0;		/* 0x18 */
+	u32 die_id_1;		/* 0x1C */
+	u32 die_id_2;		/* 0x20 */
+	u32 die_id_3;		/* 0x24 */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* boot pin mask */
+#define SYSBOOT_MASK		0x1F
+
+/* device speed */
+#define SKUID_CLK_MASK		0xf
+#define SKUID_CLK_600MHZ	0x0
+#define SKUID_CLK_720MHZ	0x8
+
+#define GPMC_BASE		(OMAP34XX_GPMC_BASE)
+#define GPMC_CONFIG_CS0		0x60
+#define GPMC_CONFIG_CS0_BASE	(GPMC_BASE + GPMC_CONFIG_CS0)
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifdef __ASSEMBLY__
+#define GPMC_CONFIG1		0x00
+#define GPMC_CONFIG2		0x04
+#define GPMC_CONFIG3		0x08
+#define GPMC_CONFIG4		0x0C
+#define GPMC_CONFIG5		0x10
+#define GPMC_CONFIG6		0x14
+#define GPMC_CONFIG7		0x18
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* GPMC Mapping */
+#define FLASH_BASE		0x10000000	/* NOR flash, */
+						/* aligned to 256 Meg */
+#define FLASH_BASE_SDPV1	0x04000000	/* NOR flash, */
+						/* aligned to 64 Meg */
+#define FLASH_BASE_SDPV2	0x10000000	/* NOR flash, */
+						/* aligned to 256 Meg */
+#define DEBUG_BASE		0x08000000	/* debug board */
+#define NAND_BASE		0x30000000	/* NAND addr */
+						/* (actual size small port) */
+#define ONENAND_MAP		0x20000000	/* OneNand addr */
+						/* (actual size small port) */
+/* SMS */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct sms {
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u8 res2[0x34];
+	u32 rg_att0;		/* 0x48 */
+	u8 res3[0x84];
+	u32 class_arb0;		/* 0xD0 */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define BURSTCOMPLETE_GROUP7	(0x1 << 31)
+
+/* SDRC */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct sdrc_cs {
+	u32 mcfg;		/* 0x80 || 0xB0 */
+	u32 mr;			/* 0x84 || 0xB4 */
+	u8 res1[0x4];
+	u32 emr2;		/* 0x8C || 0xBC */
+	u8 res2[0x14];
+	u32 rfr_ctrl;		/* 0x84 || 0xD4 */
+	u32 manual;		/* 0xA8 || 0xD8 */
+	u8 res3[0x4];
+};
+
+struct sdrc_actim {
+	u32 ctrla;		/* 0x9C || 0xC4 */
+	u32 ctrlb;		/* 0xA0 || 0xC8 */
+};
+
+struct sdrc {
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u32 status;		/* 0x14 */
+	u8 res2[0x28];
+	u32 cs_cfg;		/* 0x40 */
+	u32 sharing;		/* 0x44 */
+	u8 res3[0x18];
+	u32 dlla_ctrl;		/* 0x60 */
+	u32 dlla_status;	/* 0x64 */
+	u32 dllb_ctrl;		/* 0x68 */
+	u32 dllb_status;	/* 0x6C */
+	u32 power;		/* 0x70 */
+	u8 res4[0xC];
+	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
+};
+
+/* EMIF4 */
+typedef struct emif4 {
+	unsigned int emif_mod_id_rev;
+	unsigned int sdram_sts;
+	unsigned int sdram_config;
+	unsigned int res1;
+	unsigned int sdram_refresh_ctrl;
+	unsigned int sdram_refresh_ctrl_shdw;
+	unsigned int sdram_time1;
+	unsigned int sdram_time1_shdw;
+	unsigned int sdram_time2;
+	unsigned int sdram_time2_shdw;
+	unsigned int sdram_time3;
+	unsigned int sdram_time3_shdw;
+	unsigned char res2[8];
+	unsigned int sdram_pwr_mgmt;
+	unsigned int sdram_pwr_mgmt_shdw;
+	unsigned char res3[32];
+	unsigned int sdram_iodft_tlgc;
+	unsigned char res4[128];
+	unsigned int ddr_phyctrl1;
+	unsigned int ddr_phyctrl1_shdw;
+	unsigned int ddr_phyctrl2;
+} emif4_t;
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define DLLPHASE_90		(0x1 << 1)
+#define LOADDLL			(0x1 << 2)
+#define ENADLL			(0x1 << 3)
+#define DLL_DELAY_MASK		0xFF00
+#define DLL_NO_FILTER_MASK	((0x1 << 9) | (0x1 << 8))
+
+#define PAGEPOLICY_HIGH		(0x1 << 0)
+#define SRFRONRESET		(0x1 << 7)
+#define PWDNEN			(0x1 << 2)
+#define WAKEUPPROC		(0x1 << 26)
+
+#define DDR_SDRAM		(0x1 << 0)
+#define DEEPPD			(0x1 << 3)
+#define B32NOT16		(0x1 << 4)
+#define BANKALLOCATION		(0x2 << 6)
+#define RAMSIZE_128		(0x40 << 8) /* RAM size in 2MB chunks */
+#define ADDRMUXLEGACY		(0x1 << 19)
+#define CASWIDTH_10BITS		(0x5 << 20)
+#define RASWIDTH_13BITS		(0x2 << 24)
+#define BURSTLENGTH4		(0x2 << 0)
+#define CASL3			(0x3 << 4)
+#define SDRC_ACTIM_CTRL0_BASE	(OMAP34XX_SDRC_BASE + 0x9C)
+#define SDRC_ACTIM_CTRL1_BASE	(OMAP34XX_SDRC_BASE + 0xC4)
+#define ARE_ARCV_1		(0x1 << 0)
+#define ARCV			(0x4e2 << 8) /* Autorefresh count */
+#define OMAP34XX_SDRC_CS0	0x80000000
+#define OMAP34XX_SDRC_CS1	0xA0000000
+#define CMD_NOP			0x0
+#define CMD_PRECHARGE		0x1
+#define CMD_AUTOREFRESH		0x2
+#define CMD_ENTR_PWRDOWN	0x3
+#define CMD_EXIT_PWRDOWN	0x4
+#define CMD_ENTR_SRFRSH		0x5
+#define CMD_CKE_HIGH		0x6
+#define CMD_CKE_LOW		0x7
+#define SOFTRESET		(0x1 << 1)
+#define SMART_IDLE		(0x2 << 3)
+#define REF_ON_IDLE		(0x1 << 6)
+
+/* DMA */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct dma4_chan {
+	u32 ccr;
+	u32 clnk_ctrl;
+	u32 cicr;
+	u32 csr;
+	u32 csdp;
+	u32 cen;
+	u32 cfn;
+	u32 cssa;
+	u32 cdsa;
+	u32 csel;
+	u32 csfl;
+	u32 cdel;
+	u32 cdfl;
+	u32 csac;
+	u32 cdac;
+	u32 ccen;
+	u32 ccfn;
+	u32 color;
+};
+
+struct dma4 {
+	u32 revision;
+	u8 res1[0x4];
+	u32 irqstatus_l[0x4];
+	u32 irqenable_l[0x4];
+	u32 sysstatus;
+	u32 ocp_sysconfig;
+	u8 res2[0x34];
+	u32 caps_0;
+	u8 res3[0x4];
+	u32 caps_2;
+	u32 caps_3;
+	u32 caps_4;
+	u32 gcr;
+	u8 res4[0x4];
+	struct dma4_chan chan[32];
+};
+
+#endif /*__ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* timer regs offsets (32 bit regs) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gptimer {
+	u32 tidr;	/* 0x00 r */
+	u8 res[0xc];
+	u32 tiocp_cfg;	/* 0x10 rw */
+	u32 tistat;	/* 0x14 r */
+	u32 tisr;	/* 0x18 rw */
+	u32 tier;	/* 0x1c rw */
+	u32 twer;	/* 0x20 rw */
+	u32 tclr;	/* 0x24 rw */
+	u32 tcrr;	/* 0x28 rw */
+	u32 tldr;	/* 0x2c rw */
+	u32 ttgr;	/* 0x30 rw */
+	u32 twpc;	/* 0x34 r*/
+	u32 tmar;	/* 0x38 rw*/
+	u32 tcar1;	/* 0x3c r */
+	u32 tcicr;	/* 0x40 rw */
+	u32 tcar2;	/* 0x44 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+	u8 res1[0x34];
+	u32 wwps;	/* 0x34 r */
+	u8 res2[0x10];
+	u32 wspr;	/* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1		0xAAAA
+#define WD_UNLOCK2		0x5555
+
+/* PRCM */
+#define PRCM_BASE		0x48004000
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct prcm {
+	u32 fclken_iva2;	/* 0x00 */
+	u32 clken_pll_iva2;	/* 0x04 */
+	u8 res1[0x1c];
+	u32 idlest_pll_iva2;	/* 0x24 */
+	u8 res2[0x18];
+	u32 clksel1_pll_iva2 ;	/* 0x40 */
+	u32 clksel2_pll_iva2;	/* 0x44 */
+	u8 res3[0x8bc];
+	u32 clken_pll_mpu;	/* 0x904 */
+	u8 res4[0x1c];
+	u32 idlest_pll_mpu;	/* 0x924 */
+	u8 res5[0x18];
+	u32 clksel1_pll_mpu;	/* 0x940 */
+	u32 clksel2_pll_mpu;	/* 0x944 */
+	u8 res6[0xb8];
+	u32 fclken1_core;	/* 0xa00 */
+	u32 res_fclken2_core;
+	u32 fclken3_core;	/* 0xa08 */
+	u8 res7[0x4];
+	u32 iclken1_core;	/* 0xa10 */
+	u32 iclken2_core;	/* 0xa14 */
+	u32 iclken3_core;	/* 0xa18 */
+	u8 res8[0x24];
+	u32 clksel_core;	/* 0xa40 */
+	u8 res9[0xbc];
+	u32 fclken_gfx;		/* 0xb00 */
+	u8 res10[0xc];
+	u32 iclken_gfx;		/* 0xb10 */
+	u8 res11[0x2c];
+	u32 clksel_gfx;		/* 0xb40 */
+	u8 res12[0xbc];
+	u32 fclken_wkup;	/* 0xc00 */
+	u8 res13[0xc];
+	u32 iclken_wkup;	/* 0xc10 */
+	u8 res14[0xc];
+	u32 idlest_wkup;	/* 0xc20 */
+	u8 res15[0x1c];
+	u32 clksel_wkup;	/* 0xc40 */
+	u8 res16[0xbc];
+	u32 clken_pll;		/* 0xd00 */
+	u32 clken2_pll;	        /* 0xd04 */
+	u8 res17[0x18];
+	u32 idlest_ckgen;	/* 0xd20 */
+	u32 idlest2_ckgen;	/* 0xd24 */
+	u8 res18[0x18];
+	u32 clksel1_pll;	/* 0xd40 */
+	u32 clksel2_pll;	/* 0xd44 */
+	u32 clksel3_pll;	/* 0xd48 */
+	u32 clksel4_pll;	/* 0xd4c */
+	u32 clksel5_pll;	/* 0xd50 */
+	u8 res19[0xac];
+	u32 fclken_dss;		/* 0xe00 */
+	u8 res20[0xc];
+	u32 iclken_dss;		/* 0xe10 */
+	u8 res21[0x2c];
+	u32 clksel_dss;		/* 0xe40 */
+	u8 res22[0xbc];
+	u32 fclken_cam;		/* 0xf00 */
+	u8 res23[0xc];
+	u32 iclken_cam;		/* 0xf10 */
+	u8 res24[0x2c];
+	u32 clksel_cam;		/* 0xf40 */
+	u8 res25[0xbc];
+	u32 fclken_per;		/* 0x1000 */
+	u8 res26[0xc];
+	u32 iclken_per;		/* 0x1010 */
+	u8 res27[0x2c];
+	u32 clksel_per;		/* 0x1040 */
+	u8 res28[0xfc];
+	u32 clksel1_emu;	/* 0x1140 */
+	u8 res29[0x2bc];
+	u32 fclken_usbhost;	/* 0x1400 */
+	u8 res30[0xc];
+	u32 iclken_usbhost;	/* 0x1410 */
+};
+#else /* __ASSEMBLY__ */
+#define CM_CLKSEL_CORE		0x48004a40
+#define CM_CLKSEL_GFX		0x48004b40
+#define CM_CLKSEL_WKUP		0x48004c40
+#define CM_CLKEN_PLL		0x48004d00
+#define CM_CLKSEL1_PLL		0x48004d40
+#define CM_CLKSEL1_EMU		0x48005140
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define PRM_BASE		0x48306000
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct prm {
+	u8 res1[0xd40];
+	u32 clksel;		/* 0xd40 */
+	u8 res2[0x50c];
+	u32 rstctrl;		/* 0x1250 */
+	u8 res3[0x1c];
+	u32 clksrc_ctrl;	/* 0x1270 */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define PRM_RSTCTRL		0x48307250
+#define PRM_RSTCTRL_RESET	0x04
+#define PRM_RSTST			0x48307258
+#define PRM_RSTST_WARM_RESET_MASK	0x7D2
+#define SYSCLKDIV_1		(0x1 << 6)
+#define SYSCLKDIV_2		(0x1 << 7)
+
+#define CLKSEL_GPT1		(0x1 << 0)
+
+#define EN_GPT1			(0x1 << 0)
+#define EN_32KSYNC		(0x1 << 2)
+
+#define ST_WDT2			(0x1 << 5)
+
+#define ST_MPU_CLK		(0x1 << 0)
+
+#define ST_CORE_CLK		(0x1 << 0)
+
+#define ST_PERIPH_CLK		(0x1 << 1)
+
+#define ST_IVA2_CLK		(0x1 << 0)
+
+#define RESETDONE		(0x1 << 0)
+
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
+
+/* SMX-APE */
+#define PM_RT_APE_BASE_ADDR_ARM		(SMX_APE_BASE + 0x10000)
+#define PM_GPMC_BASE_ADDR_ARM		(SMX_APE_BASE + 0x12400)
+#define PM_OCM_RAM_BASE_ADDR_ARM	(SMX_APE_BASE + 0x12800)
+#define PM_IVA2_BASE_ADDR_ARM		(SMX_APE_BASE + 0x14000)
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct pm {
+	u8 res1[0x48];
+	u32 req_info_permission_0;	/* 0x48 */
+	u8 res2[0x4];
+	u32 read_permission_0;		/* 0x50 */
+	u8 res3[0x4];
+	u32 wirte_permission_0;		/* 0x58 */
+	u8 res4[0x4];
+	u32 addr_match_1;		/* 0x58 */
+	u8 res5[0x4];
+	u32 req_info_permission_1;	/* 0x68 */
+	u8 res6[0x14];
+	u32 addr_match_2;		/* 0x80 */
+};
+#endif /*__ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* Permission values for registers -Full fledged permissions to all */
+#define UNLOCK_1			0xFFFFFFFF
+#define UNLOCK_2			0x00000000
+#define UNLOCK_3			0x0000FFFF
+
+#define NOT_EARLY			0
+
+/* I2C base */
+#define I2C_BASE1		(OMAP34XX_CORE_L4_IO_BASE + 0x70000)
+#define I2C_BASE2		(OMAP34XX_CORE_L4_IO_BASE + 0x72000)
+#define I2C_BASE3		(OMAP34XX_CORE_L4_IO_BASE + 0x60000)
+
+/* MUSB base */
+#define MUSB_BASE		(OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
+
+/* OMAP3 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0014
+#define OMAP_GPIO_IRQSTATUS1		0x0018
+#define OMAP_GPIO_IRQSTATUS2		0x0028
+#define OMAP_GPIO_IRQENABLE2		0x002c
+#define OMAP_GPIO_IRQENABLE1		0x001c
+#define OMAP_GPIO_WAKE_EN		0x0020
+#define OMAP_GPIO_CTRL			0x0030
+#define OMAP_GPIO_OE			0x0034
+#define OMAP_GPIO_DATAIN		0x0038
+#define OMAP_GPIO_DATAOUT		0x003c
+#define OMAP_GPIO_LEVELDETECT0		0x0040
+#define OMAP_GPIO_LEVELDETECT1		0x0044
+#define OMAP_GPIO_RISINGDETECT		0x0048
+#define OMAP_GPIO_FALLINGDETECT		0x004c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0050
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0054
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0060
+#define OMAP_GPIO_SETIRQENABLE1		0x0064
+#define OMAP_GPIO_CLEARWKUENA		0x0080
+#define OMAP_GPIO_SETWKUENA		0x0084
+#define OMAP_GPIO_CLEARDATAOUT		0x0090
+#define OMAP_GPIO_SETDATAOUT		0x0094
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap3/dma.h b/arch/arm/include/asm/arch-omap3/dma.h
new file mode 100644
index 0000000..d26e490
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/dma.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __SDMA_H
+#define __SDMA_H
+
+/* Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ */
+
+/* Functions */
+void omap3_dma_init(void);
+int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
+		uint32_t sze);
+int omap3_dma_start_transfer(uint32_t chan);
+int omap3_dma_wait_for_transfer(uint32_t chan);
+int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
+int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
+
+/* Register settings */
+#define CSDP_DATA_TYPE_8BIT             0x0
+#define CSDP_DATA_TYPE_16BIT            0x1
+#define CSDP_DATA_TYPE_32BIT            0x2
+#define CSDP_SRC_BURST_SINGLE           (0x0 << 7)
+#define CSDP_SRC_BURST_EN_16BYTES       (0x1 << 7)
+#define CSDP_SRC_BURST_EN_32BYTES       (0x2 << 7)
+#define CSDP_SRC_BURST_EN_64BYTES       (0x3 << 7)
+#define CSDP_DST_BURST_SINGLE           (0x0 << 14)
+#define CSDP_DST_BURST_EN_16BYTES       (0x1 << 14)
+#define CSDP_DST_BURST_EN_32BYTES       (0x2 << 14)
+#define CSDP_DST_BURST_EN_64BYTES       (0x3 << 14)
+#define CSDP_DST_ENDIAN_LOCK_ADAPT      (0x0 << 18)
+#define CSDP_DST_ENDIAN_LOCK_LOCK       (0x1 << 18)
+#define CSDP_DST_ENDIAN_LITTLE          (0x0 << 19)
+#define CSDP_DST_ENDIAN_BIG             (0x1 << 19)
+#define CSDP_SRC_ENDIAN_LOCK_ADAPT      (0x0 << 20)
+#define CSDP_SRC_ENDIAN_LOCK_LOCK       (0x1 << 20)
+#define CSDP_SRC_ENDIAN_LITTLE          (0x0 << 21)
+#define CSDP_SRC_ENDIAN_BIG             (0x1 << 21)
+
+#define CCR_READ_PRIORITY_LOW           (0x0 << 6)
+#define CCR_READ_PRIORITY_HIGH          (0x1 << 6)
+#define CCR_ENABLE_DISABLED             (0x0 << 7)
+#define CCR_ENABLE_ENABLE               (0x1 << 7)
+#define CCR_SRC_AMODE_CONSTANT          (0x0 << 12)
+#define CCR_SRC_AMODE_POST_INC          (0x1 << 12)
+#define CCR_SRC_AMODE_SINGLE_IDX        (0x2 << 12)
+#define CCR_SRC_AMODE_DOUBLE_IDX        (0x3 << 12)
+#define CCR_DST_AMODE_CONSTANT          (0x0 << 14)
+#define CCR_DST_AMODE_POST_INC          (0x1 << 14)
+#define CCR_DST_AMODE_SINGLE_IDX        (0x2 << 14)
+#define CCR_DST_AMODE_SOUBLE_IDX        (0x3 << 14)
+
+#define CCR_RD_ACTIVE_MASK              (1 << 9)
+#define CCR_WR_ACTIVE_MASK              (1 << 10)
+
+#define CSR_TRANS_ERR			(1 << 8)
+#define CSR_SUPERVISOR_ERR		(1 << 10)
+#define CSR_MISALIGNED_ADRS_ERR		(1 << 11)
+
+/* others */
+#define CHAN_NR_MIN			0
+#define CHAN_NR_MAX			31
+
+#endif /* __SDMA_H */
diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h
new file mode 100644
index 0000000..8bf6b48
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -0,0 +1,233 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Referred to Linux Kernel DSS driver files for OMAP3 by
+ * Tomi Valkeinen from drivers/video/omap2/dss/
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 and any
+ * later version the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef DSS_H
+#define DSS_H
+
+/* DSS Base Registers */
+#define OMAP3_DSS_BASE		0x48050000
+#define OMAP3_DISPC_BASE	0x48050400
+#define OMAP3_VENC_BASE		0x48050C00
+
+/* DSS Registers */
+struct dss_regs {
+	u32 revision;				/* 0x00 */
+	u8 res1[12];				/* 0x04 */
+	u32 sysconfig;				/* 0x10 */
+	u32 sysstatus;				/* 0x14 */
+	u32 irqstatus;				/* 0x18 */
+	u8 res2[36];				/* 0x1C */
+	u32 control;				/* 0x40 */
+	u32 sdi_control;			/* 0x44 */
+	u32 pll_control;			/* 0x48 */
+};
+
+/* DISPC Registers */
+struct dispc_regs {
+	u32 revision;				/* 0x00 */
+	u8 res1[12];				/* 0x04 */
+	u32 sysconfig;				/* 0x10 */
+	u32 sysstatus;				/* 0x14 */
+	u32 irqstatus;				/* 0x18 */
+	u32 irqenable;				/* 0x1C */
+	u8 res2[32];				/* 0x20 */
+	u32 control;				/* 0x40 */
+	u32 config;				/* 0x44 */
+	u32 reserve_2;				/* 0x48 */
+	u32 default_color0;			/* 0x4C */
+	u32 default_color1;			/* 0x50 */
+	u32 trans_color0;			/* 0x54 */
+	u32 trans_color1;			/* 0x58 */
+	u32 line_status;			/* 0x5C */
+	u32 line_number;			/* 0x60 */
+	u32 timing_h;				/* 0x64 */
+	u32 timing_v;				/* 0x68 */
+	u32 pol_freq;				/* 0x6C */
+	u32 divisor;				/* 0x70 */
+	u32 global_alpha;			/* 0x74 */
+	u32 size_dig;				/* 0x78 */
+	u32 size_lcd;				/* 0x7C */
+	u32 gfx_ba0;				/* 0x80 */
+	u32 gfx_ba1;				/* 0x84 */
+	u32 gfx_position;			/* 0x88 */
+	u32 gfx_size;				/* 0x8C */
+	u8 unused[16];				/* 0x90 */
+	u32 gfx_attributes;			/* 0xA0 */
+	u32 gfx_fifo_threshold;			/* 0xA4 */
+	u32 gfx_fifo_size_status;		/* 0xA8 */
+	u32 gfx_row_inc;			/* 0xAC */
+	u32 gfx_pixel_inc;			/* 0xB0 */
+	u32 gfx_window_skip;			/* 0xB4 */
+	u32 gfx_table_ba;			/* 0xB8 */
+};
+
+/* VENC Registers */
+struct venc_regs {
+	u32 rev_id;				/* 0x00 */
+	u32 status;				/* 0x04 */
+	u32 f_control;				/* 0x08 */
+	u32 reserve_1;				/* 0x0C */
+	u32 vidout_ctrl;			/* 0x10 */
+	u32 sync_ctrl;				/* 0x14 */
+	u32 reserve_2;				/* 0x18 */
+	u32 llen;				/* 0x1C */
+	u32 flens;				/* 0x20 */
+	u32 hfltr_ctrl;				/* 0x24 */
+	u32 cc_carr_wss_carr;			/* 0x28 */
+	u32 c_phase;				/* 0x2C */
+	u32 gain_u;				/* 0x30 */
+	u32 gain_v;				/* 0x34 */
+	u32 gain_y;				/* 0x38 */
+	u32 black_level;			/* 0x3C */
+	u32 blank_level;			/* 0x40 */
+	u32 x_color;				/* 0x44 */
+	u32 m_control;				/* 0x48 */
+	u32 bstamp_wss_data;			/* 0x4C */
+	u32 s_carr;				/* 0x50 */
+	u32 line21;				/* 0x54 */
+	u32 ln_sel;				/* 0x58 */
+	u32 l21__wc_ctl;			/* 0x5C */
+	u32 htrigger_vtrigger;			/* 0x60 */
+	u32 savid__eavid;			/* 0x64 */
+	u32 flen__fal;				/* 0x68 */
+	u32 lal__phase_reset;			/* 0x6C */
+	u32 hs_int_start_stop_x;		/* 0x70 */
+	u32 hs_ext_start_stop_x;		/* 0x74 */
+	u32 vs_int_start_x;			/* 0x78 */
+	u32 vs_int_stop_x__vs_int_start_y;	/* 0x7C */
+	u32 vs_int_stop_y__vs_ext_start_x;	/* 0x80 */
+	u32 vs_ext_stop_x__vs_ext_start_y;	/* 0x84 */
+	u32 vs_ext_stop_y;			/* 0x88 */
+	u32 reserve_3;				/* 0x8C */
+	u32 avid_start_stop_x;			/* 0x90 */
+	u32 avid_start_stop_y;			/* 0x94 */
+	u32 reserve_4;				/* 0x98 */
+	u32 reserve_5;				/* 0x9C */
+	u32 fid_int_start_x__fid_int_start_y;	/* 0xA0 */
+	u32 fid_int_offset_y__fid_ext_start_x;	/* 0xA4 */
+	u32 fid_ext_start_y__fid_ext_offset_y;	/* 0xA8 */
+	u32 reserve_6;				/* 0xAC */
+	u32 tvdetgp_int_start_stop_x;		/* 0xB0 */
+	u32 tvdetgp_int_start_stop_y;		/* 0xB4 */
+	u32 gen_ctrl;				/* 0xB8 */
+	u32 reserve_7;				/* 0xBC */
+	u32 reserve_8;				/* 0xC0 */
+	u32 output_control;			/* 0xC4 */
+	u32 dac_b__dac_c;			/* 0xC8 */
+	u32 height_width;			/* 0xCC */
+};
+
+/* Few Register Offsets */
+#define TFTSTN_SHIFT				3
+#define DATALINES_SHIFT				8
+
+#define GFX_ENABLE				1
+#define GFX_FORMAT_SHIFT			1
+#define LOADMODE_SHIFT				1
+
+#define DSS_SOFTRESET				(1 << 1)
+#define DSS_RESETDONE				1
+
+/* Enabling Display controller */
+#define LCD_ENABLE				1
+#define DIG_ENABLE				(1 << 1)
+#define GO_LCD					(1 << 5)
+#define GO_DIG					(1 << 6)
+#define GP_OUT0					(1 << 15)
+#define GP_OUT1					(1 << 16)
+
+/* Configure VENC DSS Params */
+#define VENC_CLK_ENABLE				(1 << 3)
+#define DAC_DEMEN				(1 << 4)
+#define DAC_POWERDN				(1 << 5)
+#define VENC_OUT_SEL				(1 << 6)
+#define DIG_LPP_SHIFT				16
+
+/* LCD display type */
+#define PASSIVE_DISPLAY			0
+#define ACTIVE_DISPLAY			1
+
+/* TFTDATALINES */
+#define LCD_INTERFACE_12_BIT	0
+#define LCD_INTERFACE_16_BIT	1
+#define LCD_INTERFACE_18_BIT	2
+#define LCD_INTERFACE_24_BIT	3
+
+/* Polarity */
+#define DSS_IVS		(1 << 12)
+#define DSS_IHS		(1 << 13)
+#define DSS_IPC		(1 << 14)
+#define DSS_IEO		(1 << 15)
+#define DSS_ONOFF	(1 << 17)
+
+/* GFX format */
+#define GFXFORMAT_BITMAP1		(0x0 << 1)
+#define GFXFORMAT_BITMAP2		(0x1 << 1)
+#define GFXFORMAT_BITMAP4		(0x2 << 1)
+#define GFXFORMAT_BITMAP8		(0x3 << 1)
+#define GFXFORMAT_RGB12			(0x4 << 1)
+#define GFXFORMAT_ARGB16		(0x5 << 1)
+#define GFXFORMAT_RGB16			(0x6 << 1)
+#define GFXFORMAT_RGB24_UNPACKED	(0x8 << 1)
+#define GFXFORMAT_RGB24_PACKED		(0x9 << 1)
+#define GFXFORMAT_ARGB32		(0xC << 1)
+#define GFXFORMAT_RGBA32		(0xD << 1)
+#define GFXFORMAT_RGBx32		(0xE << 1)
+
+/* Panel Configuration */
+struct panel_config {
+	u32 timing_h;
+	u32 timing_v;
+	u32 pol_freq;
+	u32 divisor;
+	u32 lcd_size;
+	u32 panel_type;
+	u32 data_lines;
+	u32 load_mode;
+	u32 panel_color;
+	u32 gfx_format;
+	void *frame_buffer;
+};
+
+#define DSS_HBP(bp)    (((bp) - 1) << 20)
+#define DSS_HFP(fp)    (((fp) - 1) << 8)
+#define DSS_HSW(sw)    ((sw) - 1)
+#define DSS_VBP(bp)    ((bp) << 20)
+#define DSS_VFP(fp)    ((fp) << 8)
+#define DSS_VSW(sw)    ((sw) - 1)
+
+#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
+#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
+#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1))
+
+/* Generic DSS Functions */
+void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
+			u32 height, u32 width);
+void omap3_dss_panel_config(const struct panel_config *panel_cfg);
+void omap3_dss_enable(void);
+
+#endif /* DSS_H */
diff --git a/arch/arm/include/asm/arch-omap3/ehci.h b/arch/arm/include/asm/arch-omap3/ehci.h
new file mode 100644
index 0000000..fa839ef
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/ehci.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Alexander Holler <holler@ahsoftware.de>
+ *
+ * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37
+ *
+ * See there for additional Copyrights.
+ */
+#ifndef _OMAP3_EHCI_H_
+#define _OMAP3_EHCI_H_
+
+/* USB/EHCI registers */
+#define OMAP_USBTLL_BASE				0x48062000UL
+#define OMAP_UHH_BASE					0x48064000UL
+#define OMAP_EHCI_BASE					0x48064800UL
+
+/* TLL Register Set */
+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET			(1 << 1)
+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP			(1 << 2)
+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE			(1 << 3)
+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY			(1 << 8)
+#define OMAP_USBTLL_SYSSTATUS_RESETDONE			1
+
+/* UHH Register Set */
+#define OMAP_UHH_SYSCONFIG_SOFTRESET			(1 << 1)
+#define OMAP_UHH_SYSCONFIG_CACTIVITY			(1 << 8)
+#define OMAP_UHH_SYSCONFIG_SIDLEMODE			(1 << 3)
+#define OMAP_UHH_SYSCONFIG_ENAWAKEUP			(1 << 2)
+#define OMAP_UHH_SYSCONFIG_MIDLEMODE			(1 << 12)
+#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE		(1 << 2)
+
+#define OMAP_UHH_SYSCONFIG_VAL		(OMAP_UHH_SYSCONFIG_CACTIVITY | \
+					OMAP_UHH_SYSCONFIG_SIDLEMODE | \
+					OMAP_UHH_SYSCONFIG_ENAWAKEUP | \
+					OMAP_UHH_SYSCONFIG_MIDLEMODE)
+
+#endif /* _OMAP3_EHCI_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/emac_defs.h b/arch/arm/include/asm/arch-omap3/emac_defs.h
new file mode 100644
index 0000000..0f4b934
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/emac_defs.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * dm644x_emac.h
+ *
+ * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
+ *
+ * Copyright (C) 2005 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * Modifications:
+ * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
+ */
+
+#ifndef _AM3517_EMAC_H_
+#define _AM3517_EMAC_H_
+
+#define EMAC_BASE_ADDR                 0x5C010000
+#define EMAC_WRAPPER_BASE_ADDR         0x5C000000
+#define EMAC_WRAPPER_RAM_ADDR          0x5C020000
+#define EMAC_MDIO_BASE_ADDR            0x5C030000
+#define EMAC_HW_RAM_ADDR               0x01E20000
+
+#define EMAC_MDIO_BUS_FREQ             166000000       /* 166 MHZ check */
+#define EMAC_MDIO_CLOCK_FREQ           1000000         /* 2.0 MHz */
+
+/* SOFTRESET macro definition interferes with emac_regs structure definition */
+#undef SOFTRESET
+
+typedef volatile unsigned int	dv_reg;
+typedef volatile unsigned int	*dv_reg_p;
+
+#define DAVINCI_EMAC_VERSION2
+
+#endif  /* _AM3517_EMAC_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/emif4.h b/arch/arm/include/asm/arch-omap3/emif4.h
new file mode 100644
index 0000000..bac43b2
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/emif4.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Auther:
+ *       Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+
+/*
+ * Configuration values
+ */
+#define EMIF4_TIM1_T_RP		(0x3 << 25)
+#define EMIF4_TIM1_T_RCD	(0x3 << 21)
+#define EMIF4_TIM1_T_WR		(0x3 << 17)
+#define EMIF4_TIM1_T_RAS	(0x8 << 12)
+#define EMIF4_TIM1_T_RC		(0xA << 6)
+#define EMIF4_TIM1_T_RRD	(0x2 << 3)
+#define EMIF4_TIM1_T_WTR	(0x2)
+
+#define EMIF4_TIM2_T_XP		(0x2 << 28)
+#define EMIF4_TIM2_T_ODT	(0x0 << 25)
+#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
+#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
+#define EMIF4_TIM2_T_RTP	(0x1 << 3)
+#define EMIF4_TIM2_T_CKE	(0x2)
+
+#define EMIF4_TIM3_T_RFC	(0x25 << 4)
+#define EMIF4_TIM3_T_RAS_MAX	(0x7)
+
+#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
+#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
+#define EMIF4_PWR_DPD_EN	(0x1 << 10)
+#define EMIF4_PWR_LP_MODE	(0x0 << 8)
+#define EMIF4_PWR_PM_TIM	(0x0)
+
+#define EMIF4_INITREF_DIS	(0x0 << 31)
+#define EMIF4_REFRESH_RATE	(0x50F)
+
+#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
+#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
+#define EMIF4_CFG_DDR_TERM	(0x0 << 24)
+#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
+#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
+#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
+#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
+#define EMIF4_CFG_CL		(0x5 << 10)
+#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
+#define EMIF4_CFG_IBANK		(0x3 << 4)
+#define EMIF4_CFG_EBANK		(0x0 << 3)
+#define EMIF4_CFG_PGSIZE	(0x2)
+
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
+#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
+#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
+#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
+#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
+
+#endif /* endif _EMIF_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/gpio.h b/arch/arm/include/asm/arch-omap3/gpio.h
new file mode 100644
index 0000000..ee092f9
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/gpio.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+#ifndef _GPIO_OMAP3_H
+#define _GPIO_OMAP3_H
+
+#include <asm/omap_gpio.h>
+
+#define OMAP_MAX_GPIO			192
+
+#define OMAP34XX_GPIO1_BASE		0x48310000
+#define OMAP34XX_GPIO2_BASE		0x49050000
+#define OMAP34XX_GPIO3_BASE		0x49052000
+#define OMAP34XX_GPIO4_BASE		0x49054000
+#define OMAP34XX_GPIO5_BASE		0x49056000
+#define OMAP34XX_GPIO6_BASE		0x49058000
+
+#endif /* _GPIO_OMAP3_H */
diff --git a/arch/arm/include/asm/arch-omap3/i2c.h b/arch/arm/include/asm/arch-omap3/i2c.h
new file mode 100644
index 0000000..b04c012
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/i2c.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef _OMAP3_I2C_H_
+#define _OMAP3_I2C_H_
+
+#define I2C_DEFAULT_BASE	I2C_BASE1
+
+#endif /* _OMAP3_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
new file mode 100644
index 0000000..7adc134
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -0,0 +1,488 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+#define CS0		0x0
+#define CS1		0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
+
+#ifndef __ASSEMBLY__
+enum {
+	STACKED = 0,
+	IP_DDR = 1,
+	COMBO_DDR = 2,
+	IP_SDR = 3,
+};
+#endif /* __ASSEMBLY__ */
+
+#define EARLY_INIT	1
+
+/*
+ * For a full explanation of these registers and values please see
+ * the Technical Reference Manual (TRM) for any of the processors in
+ * this family.
+ */
+
+/* Slower full frequency range default timings for x32 operation*/
+#define SDRC_SHARING	0x00000100
+#define SDRC_MR_0_SDR	0x00000031
+
+/*
+ * SDRC autorefresh control values.  This register consists of autorefresh
+ * enable at bits 0:1 and an autorefresh counter value in bits 8:23.  The
+ * counter is a result of ( tREFI / tCK ) - 50.
+ */
+#define SDP_3430_SDRC_RFR_CTRL_100MHz	0x0002da01
+#define SDP_3430_SDRC_RFR_CTRL_133MHz	0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
+#define SDP_3430_SDRC_RFR_CTRL_165MHz	0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
+#define SDP_3430_SDRC_RFR_CTRL_200MHz	0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
+
+#define DLL_OFFSET		0
+#define DLL_WRITEDDRCLKX2DIS	1
+#define DLL_ENADLL		1
+#define DLL_LOCKDLL		0
+#define DLL_DLLPHASE_72		0
+#define DLL_DLLPHASE_90		1
+
+/* rkw - need to find of 90/72 degree recommendation for speed like before */
+#define SDP_SDRC_DLLAB_CTRL	((DLL_ENADLL << 3) | \
+				(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
+
+/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
+#define ACTIM_CTRLA_TRFC(v)	(((v) & 0x1F) << 27)	/* 31:27 */
+#define ACTIM_CTRLA_TRC(v)	(((v) & 0x1F) << 22)	/* 26:22 */
+#define ACTIM_CTRLA_TRAS(v)	(((v) & 0x0F) << 18)	/* 21:18 */
+#define ACTIM_CTRLA_TRP(v)	(((v) & 0x07) << 15)	/* 17:15 */
+#define ACTIM_CTRLA_TRCD(v)	(((v) & 0x07) << 12)	/* 14:12 */
+#define ACTIM_CTRLA_TRRD(v)	(((v) & 0x07) << 9)	/* 11:9  */
+#define ACTIM_CTRLA_TDPL(v)	(((v) & 0x07) << 6)	/*  8:6  */
+#define ACTIM_CTRLA_TDAL(v)	(v & 0x1F)		/*  4:0  */
+
+#define ACTIM_CTRLA(trfc, trc, tras, trp, trcd, trrd, tdpl, tdal)	\
+		ACTIM_CTRLA_TRFC(trfc)	|	\
+		ACTIM_CTRLA_TRC(trc)	|	\
+		ACTIM_CTRLA_TRAS(tras)	|	\
+		ACTIM_CTRLA_TRP(trp)	|	\
+		ACTIM_CTRLA_TRCD(trcd)	|	\
+		ACTIM_CTRLA_TRRD(trrd)	|	\
+		ACTIM_CTRLA_TDPL(tdpl)	|	\
+		ACTIM_CTRLA_TDAL(tdal)
+
+/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
+#define ACTIM_CTRLB_TWTR(v)	(((v) & 0x03) << 16)	/* 17:16 */
+#define ACTIM_CTRLB_TCKE(v)	(((v) & 0x07) << 12)	/* 14:12 */
+#define ACTIM_CTRLB_TXP(v)	(((v) & 0x07) << 8)	/* 10:8  */
+#define ACTIM_CTRLB_TXSR(v)	(v & 0xFF)		/*  7:0  */
+
+#define ACTIM_CTRLB(twtr, tcke, txp, txsr)		\
+		ACTIM_CTRLB_TWTR(twtr)	|	\
+		ACTIM_CTRLB_TCKE(tcke)	|	\
+		ACTIM_CTRLB_TXP(txp)	|	\
+		ACTIM_CTRLB_TXSR(txsr)
+
+/*
+ * Values used in the MCFG register.  Only values we use today
+ * are defined and the rest can be found in the TRM.  Unless otherwise
+ * noted all fields are one bit.
+ */
+#define V_MCFG_RAMTYPE_DDR		(0x1)
+#define V_MCFG_DEEPPD_EN		(0x1 << 3)
+#define V_MCFG_B32NOT16_32		(0x1 << 4)
+#define V_MCFG_BANKALLOCATION_RBC	(0x2 << 6)		/* 6:7 */
+#define V_MCFG_RAMSIZE(ramsize)		((((ramsize) >> 20)/2) << 8) /* 8:17 */
+#define V_MCFG_ADDRMUXLEGACY_FLEX	(0x1 << 19)
+#define V_MCFG_CASWIDTH(caswidth)	(((caswidth)-5) << 20)	/* 20:22 */
+#define V_MCFG_CASWIDTH_10B		V_MCFG_CASWIDTH(10)
+#define V_MCFG_RASWIDTH(raswidth)	(((raswidth)-11) << 24)	/* 24:26 */
+
+/* Macro to construct MCFG */
+#define MCFG(ramsize, raswidth)						\
+		V_MCFG_RASWIDTH(raswidth) | V_MCFG_CASWIDTH_10B |	\
+		V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(ramsize) |	\
+		V_MCFG_BANKALLOCATION_RBC | V_MCFG_B32NOT16_32 |	\
+		V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
+
+/* Hynix part of Overo (165MHz optimized) 6.06ns */
+#define HYNIX_TDAL_165   6
+#define HYNIX_TDPL_165   3
+#define HYNIX_TRRD_165   2
+#define HYNIX_TRCD_165   3
+#define HYNIX_TRP_165    3
+#define HYNIX_TRAS_165   7
+#define HYNIX_TRC_165   10
+#define HYNIX_TRFC_165  21
+#define HYNIX_V_ACTIMA_165	\
+		ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165,	\
+				HYNIX_TRAS_165, HYNIX_TRP_165,	\
+				HYNIX_TRCD_165, HYNIX_TRRD_165,	\
+				HYNIX_TDPL_165, HYNIX_TDAL_165)
+
+#define HYNIX_TWTR_165   1
+#define HYNIX_TCKE_165   1
+#define HYNIX_TXP_165    2
+#define HYNIX_XSR_165    24
+#define HYNIX_V_ACTIMB_165	\
+		ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165,	\
+				HYNIX_TXP_165, HYNIX_XSR_165)
+
+#define HYNIX_RASWIDTH_165	13
+#define HYNIX_V_MCFG_165(size)	MCFG((size), HYNIX_RASWIDTH_165)
+
+/* Hynix part of AM/DM37xEVM (200MHz optimized) */
+#define HYNIX_TDAL_200		6
+#define HYNIX_TDPL_200		3
+#define HYNIX_TRRD_200		2
+#define HYNIX_TRCD_200		4
+#define HYNIX_TRP_200		3
+#define HYNIX_TRAS_200		8
+#define HYNIX_TRC_200		11
+#define HYNIX_TRFC_200		18
+#define HYNIX_V_ACTIMA_200	\
+		ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200,	\
+				HYNIX_TRAS_200, HYNIX_TRP_200,	\
+				HYNIX_TRCD_200, HYNIX_TRRD_200,	\
+				HYNIX_TDPL_200, HYNIX_TDAL_200)
+
+#define HYNIX_TWTR_200		2
+#define HYNIX_TCKE_200		1
+#define HYNIX_TXP_200		1
+#define HYNIX_XSR_200		28
+#define HYNIX_V_ACTIMB_200	\
+		ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200,	\
+				HYNIX_TXP_200, HYNIX_XSR_200)
+
+#define HYNIX_RASWIDTH_200	14
+#define HYNIX_V_MCFG_200(size)	MCFG((size), HYNIX_RASWIDTH_200)
+
+/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
+#define INFINEON_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
+					/* 15/6 + 18/6 = 5.5 -> 6	*/
+#define INFINEON_TDPL_165	3	/* 15/6 = 2.5 -> 3 (Twr)	*/
+#define INFINEON_TRRD_165	2	/* 12/6 = 2			*/
+#define INFINEON_TRCD_165	3	/* 18/6 = 3			*/
+#define INFINEON_TRP_165	3	/* 18/6 = 3			*/
+#define INFINEON_TRAS_165	7	/* 42/6 = 7			*/
+#define INFINEON_TRC_165	10	/* 60/6 = 10			*/
+#define INFINEON_TRFC_165	12	/* 72/6 = 12			*/
+
+#define INFINEON_V_ACTIMA_165	\
+		ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165,	\
+				INFINEON_TRAS_165, INFINEON_TRP_165,	\
+				INFINEON_TRCD_165, INFINEON_TRRD_165,	\
+				INFINEON_TDPL_165, INFINEON_TDAL_165)
+
+#define INFINEON_TWTR_165	1
+#define INFINEON_TCKE_165	2
+#define INFINEON_TXP_165	2
+#define INFINEON_XSR_165	20	/* 120/6 = 20	*/
+
+#define INFINEON_V_ACTIMB_165	\
+		ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165,	\
+				INFINEON_TXP_165, INFINEON_XSR_165)
+
+/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
+#define MICRON_TDAL_165		6	/* Twr/Tck + Trp/tck		*/
+					/* 15/6 + 18/6 = 5.5 -> 6	*/
+#define MICRON_TDPL_165		3	/* 15/6 = 2.5 -> 3 (Twr)	*/
+#define MICRON_TRRD_165		2	/* 12/6 = 2			*/
+#define MICRON_TRCD_165		3	/* 18/6 = 3			*/
+#define MICRON_TRP_165		3	/* 18/6 = 3			*/
+#define MICRON_TRAS_165		7	/* 42/6 = 7			*/
+#define MICRON_TRC_165		10	/* 60/6 = 10			*/
+#define MICRON_TRFC_165		21	/* 125/6 = 21			*/
+
+#define MICRON_V_ACTIMA_165	\
+		ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165,		\
+				MICRON_TRAS_165, MICRON_TRP_165,	\
+				MICRON_TRCD_165, MICRON_TRRD_165,	\
+				MICRON_TDPL_165, MICRON_TDAL_165)
+
+#define MICRON_TWTR_165		1
+#define MICRON_TCKE_165		1
+#define MICRON_XSR_165		23	/* 138/6 = 23		*/
+#define MICRON_TXP_165		5	/* 25/6 = 4.1 => ~5	*/
+
+#define MICRON_V_ACTIMB_165	\
+		ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165,	\
+				MICRON_TXP_165,	MICRON_XSR_165)
+
+#define MICRON_RASWIDTH_165	13
+#define MICRON_V_MCFG_165(size)	MCFG((size), MICRON_RASWIDTH_165)
+
+#define MICRON_BL_165			0x2
+#define MICRON_SIL_165			0x0
+#define MICRON_CASL_165			0x3
+#define MICRON_WBST_165			0x0
+#define MICRON_V_MR_165			((MICRON_WBST_165 << 9) | \
+		(MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
+		(MICRON_BL_165))
+
+/* Micron part (200MHz optimized) 5 ns */
+#define MICRON_TDAL_200		6
+#define MICRON_TDPL_200		3
+#define MICRON_TRRD_200		2
+#define MICRON_TRCD_200		3
+#define MICRON_TRP_200		3
+#define MICRON_TRAS_200		8
+#define MICRON_TRC_200		11
+#define MICRON_TRFC_200		15
+#define MICRON_V_ACTIMA_200	\
+		ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200,		\
+				MICRON_TRAS_200, MICRON_TRP_200,	\
+				MICRON_TRCD_200, MICRON_TRRD_200,	\
+				MICRON_TDPL_200, MICRON_TDAL_200)
+
+#define MICRON_TWTR_200		2
+#define MICRON_TCKE_200		4
+#define MICRON_TXP_200		2
+#define MICRON_XSR_200		23
+#define MICRON_V_ACTIMB_200	\
+		ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200,	\
+				MICRON_TXP_200,	MICRON_XSR_200)
+
+#define MICRON_RASWIDTH_200	14
+#define MICRON_V_MCFG_200(size)	MCFG((size), MICRON_RASWIDTH_200)
+
+/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
+#define SAMSUNG_TDAL_165	5
+#define SAMSUNG_TDPL_165	2
+#define SAMSUNG_TRRD_165	2
+#define SAMSUNG_TRCD_165	3
+#define SAMSUNG_TRP_165		3
+#define SAMSUNG_TRAS_165	7
+#define SAMSUNG_TRC_165		10
+#define SAMSUNG_TRFC_165	12
+
+#define SAMSUNG_V_ACTIMA_165	\
+		ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165,		\
+				SAMSUNG_TRAS_165, SAMSUNG_TRP_165,	\
+				SAMSUNG_TRCD_165, SAMSUNG_TRRD_165,	\
+				SAMSUNG_TDPL_165, SAMSUNG_TDAL_165)
+
+#define SAMSUNG_TWTR_165	1
+#define SAMSUNG_TCKE_165	2
+#define SAMSUNG_XSR_165		20
+#define SAMSUNG_TXP_165		5
+
+#define SAMSUNG_V_ACTIMB_165	\
+		ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165,	\
+				SAMSUNG_TXP_165, SAMSUNG_XSR_165)
+
+#define SAMSUNG_RASWIDTH_165	14
+#define SAMSUNG_V_MCFG_165(size) \
+	V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \
+	V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \
+	V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR
+
+/* TODO: find which register these were taken from */
+
+#define SAMSUNG_BL_165				0x2
+#define SAMSUNG_SIL_165				0x0
+#define SAMSUNG_CASL_165			0x3
+#define SAMSUNG_WBST_165			0x0
+#define SAMSUNG_V_MR_165			((SAMSUNG_WBST_165 << 9) | \
+		(SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \
+		(SAMSUNG_BL_165))
+
+#define SAMSUNG_SHARING 0x00003700
+
+/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
+#define NUMONYX_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
+					/* 15/6 + 18/6 = 5.5 -> 6	*/
+#define NUMONYX_TDPL_165	3	/* 15/6 = 2.5 -> 3 (Twr)	*/
+#define NUMONYX_TRRD_165	2	/* 12/6 = 2			*/
+#define NUMONYX_TRCD_165	4	/* 22.5/6 = 3.75 -> 4		*/
+#define NUMONYX_TRP_165		3	/* 18/6 = 3			*/
+#define NUMONYX_TRAS_165	7	/* 42/6 = 7			*/
+#define NUMONYX_TRC_165		10	/* 60/6 = 10			*/
+#define NUMONYX_TRFC_165	24	/* 140/6 = 23.3 -> 24		*/
+
+#define NUMONYX_V_ACTIMA_165	\
+		ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165,		\
+				NUMONYX_TRAS_165, NUMONYX_TRP_165,	\
+				NUMONYX_TRCD_165, NUMONYX_TRRD_165,	\
+				NUMONYX_TDPL_165, NUMONYX_TDAL_165)
+
+#define NUMONYX_TWTR_165	2
+#define NUMONYX_TCKE_165	2
+#define NUMONYX_TXP_165		3	/* 200/6 =  33.3 -> 34	*/
+#define NUMONYX_XSR_165		34	/* 1.0 + 1.1 = 2.1 -> 3	*/
+
+#define NUMONYX_V_ACTIMB_165	\
+		ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165,	\
+				NUMONYX_TXP_165, NUMONYX_XSR_165)
+
+#define NUMONYX_RASWIDTH_165		15
+#define NUMONYX_V_MCFG_165(size)	MCFG((size), NUMONYX_RASWIDTH_165)
+
+/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
+#define NUMONYX_TDAL_200	6	/* Twr/Tck + Trp/tck		*/
+					/* 15/5 + 15/5 = 3 + 3 -> 6	*/
+#define NUMONYX_TDPL_200	3	/* 15/5 = 3 -> 3 (Twr)	        */
+#define NUMONYX_TRRD_200	2	/* 10/5 = 2			*/
+#define NUMONYX_TRCD_200	4	/* 16.2/5 = 3.24 -> 4		*/
+#define NUMONYX_TRP_200		3	/* 15/5 = 3			*/
+#define NUMONYX_TRAS_200	8	/* 40/5 = 8			*/
+#define NUMONYX_TRC_200		11	/* 55/5 = 11			*/
+#define NUMONYX_TRFC_200        28      /* 140/5 = 28                   */
+
+#define NUMONYX_V_ACTIMA_200	\
+		ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200,		\
+				NUMONYX_TRAS_200, NUMONYX_TRP_200,	\
+				NUMONYX_TRCD_200, NUMONYX_TRRD_200,	\
+				NUMONYX_TDPL_200, NUMONYX_TDAL_200)
+
+#define NUMONYX_TWTR_200	2
+#define NUMONYX_TCKE_200	2
+#define NUMONYX_TXP_200		3
+#define NUMONYX_XSR_200		40
+
+#define NUMONYX_V_ACTIMB_200	\
+		ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200,	\
+				NUMONYX_TXP_200, NUMONYX_XSR_200)
+
+#define NUMONYX_RASWIDTH_200		15
+#define NUMONYX_V_MCFG_200(size)	MCFG((size), NUMONYX_RASWIDTH_200)
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * STNOR - Intel Strata Flash
+ * SMNAND - Samsung NAND
+ * MPDB - H4 MPDB board
+ * SBNOR - Sibley NOR
+ * MNAND - Micron Large page x16 NAND
+ * ONNAND - Samsung One NAND
+ *
+ * include/configs/file.h contains the defn - for all CS we are interested
+ * #define OMAP34XX_GPMC_CSx PART
+ * #define OMAP34XX_GPMC_CSx_SIZE Size
+ * #define OMAP34XX_GPMC_CSx_MAP Map
+ * Where:
+ * x - CS number
+ * PART - Part Name as defined above
+ * SIZE - how big is the mapping to be
+ *   GPMC_SIZE_128M - 0x8
+ *   GPMC_SIZE_64M  - 0xC
+ *   GPMC_SIZE_32M  - 0xE
+ *   GPMC_SIZE_16M  - 0xF
+ * MAP  - Map this CS to which address(GPMC address space)- Absolute address
+ *   >>24 before being used.
+ */
+#define GPMC_SIZE_256M	0x0
+#define GPMC_SIZE_128M	0x8
+#define GPMC_SIZE_64M	0xC
+#define GPMC_SIZE_32M	0xE
+#define GPMC_SIZE_16M	0xF
+
+#define GPMC_BASEADDR_MASK	0x3F
+
+#define GPMC_CS_ENABLE		0x1
+
+#define M_NAND_GPMC_CONFIG1	0x00001800
+#define M_NAND_GPMC_CONFIG2	0x00141400
+#define M_NAND_GPMC_CONFIG3	0x00141400
+#define M_NAND_GPMC_CONFIG4	0x0F010F01
+#define M_NAND_GPMC_CONFIG5	0x010C1414
+#define M_NAND_GPMC_CONFIG6	0x1f0f0A80
+#define M_NAND_GPMC_CONFIG7	0x00000C44
+
+#define STNOR_GPMC_CONFIG1	0x3
+#define STNOR_GPMC_CONFIG2	0x00151501
+#define STNOR_GPMC_CONFIG3	0x00060602
+#define STNOR_GPMC_CONFIG4	0x11091109
+#define STNOR_GPMC_CONFIG5	0x01141F1F
+#define STNOR_GPMC_CONFIG6	0x000004c4
+
+#define SIBNOR_GPMC_CONFIG1	0x1200
+#define SIBNOR_GPMC_CONFIG2	0x001f1f00
+#define SIBNOR_GPMC_CONFIG3	0x00080802
+#define SIBNOR_GPMC_CONFIG4	0x1C091C09
+#define SIBNOR_GPMC_CONFIG5	0x01131F1F
+#define SIBNOR_GPMC_CONFIG6	0x1F0F03C2
+
+#define SDPV2_MPDB_GPMC_CONFIG1	0x00611200
+#define SDPV2_MPDB_GPMC_CONFIG2	0x001F1F01
+#define SDPV2_MPDB_GPMC_CONFIG3	0x00080803
+#define SDPV2_MPDB_GPMC_CONFIG4	0x1D091D09
+#define SDPV2_MPDB_GPMC_CONFIG5	0x041D1F1F
+#define SDPV2_MPDB_GPMC_CONFIG6	0x1D0904C4
+
+#define MPDB_GPMC_CONFIG1	0x00011000
+#define MPDB_GPMC_CONFIG2	0x001f1f01
+#define MPDB_GPMC_CONFIG3	0x00080803
+#define MPDB_GPMC_CONFIG4	0x1c0b1c0a
+#define MPDB_GPMC_CONFIG5	0x041f1F1F
+#define MPDB_GPMC_CONFIG6	0x1F0F04C4
+
+#define P2_GPMC_CONFIG1	0x0
+#define P2_GPMC_CONFIG2	0x0
+#define P2_GPMC_CONFIG3	0x0
+#define P2_GPMC_CONFIG4	0x0
+#define P2_GPMC_CONFIG5	0x0
+#define P2_GPMC_CONFIG6	0x0
+
+#define ONENAND_GPMC_CONFIG1	0x00001200
+#define ONENAND_GPMC_CONFIG2	0x000F0F01
+#define ONENAND_GPMC_CONFIG3	0x00030301
+#define ONENAND_GPMC_CONFIG4	0x0F040F04
+#define ONENAND_GPMC_CONFIG5	0x010F1010
+#define ONENAND_GPMC_CONFIG6	0x1F060000
+
+#define NET_GPMC_CONFIG1	0x00001000
+#define NET_GPMC_CONFIG2	0x001e1e01
+#define NET_GPMC_CONFIG3	0x00080300
+#define NET_GPMC_CONFIG4	0x1c091c09
+#define NET_GPMC_CONFIG5	0x04181f1f
+#define NET_GPMC_CONFIG6	0x00000FCF
+#define NET_GPMC_CONFIG7	0x00000f6c
+
+/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1    0x00001000
+#define NET_LAN9221_GPMC_CONFIG2    0x00060700
+#define NET_LAN9221_GPMC_CONFIG3    0x00020201
+#define NET_LAN9221_GPMC_CONFIG4    0x06000700
+#define NET_LAN9221_GPMC_CONFIG5    0x0006090A
+#define NET_LAN9221_GPMC_CONFIG6    0x87030000
+#define NET_LAN9221_GPMC_CONFIG7    0x00000f6c
+
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS	8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG	7
+
+#define DBG_MPDB	6
+#define DBG_MPDB_BASE		DEBUG_BASE
+
+#ifndef __ASSEMBLY__
+
+/* Function prototypes */
+void mem_init(void);
+
+u32 is_mem_sdr(void);
+u32 mem_ok(u32 cs);
+
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
new file mode 100644
index 0000000..39a7cba
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+#include <asm/omap_mmc.h>
+
+/* T2 Register definitions */
+#define T2_BASE			0x48002000
+
+typedef struct t2 {
+	unsigned char res1[0x274];	/* 0x000 */
+	unsigned int devconf0;		/* 0x274 */
+	unsigned char res2[0x060];	/* 0x278 */
+	unsigned int devconf1;		/* 0x2D8 */
+	unsigned char res3[0x16C];	/* 0x2DC */
+	unsigned int ctl_prog_io1;	/* 0x448 */
+	unsigned char res4[0x0D4];	/* 0x44C */
+	unsigned int pbias_lite;	/* 0x520 */
+} t2_t;
+
+#define MMCSDIO1ADPCLKISEL		(1 << 24)
+#define MMCSDIO2ADPCLKISEL		(1 << 6)
+
+#define EN_MMC1				(1 << 24)
+#define EN_MMC2				(1 << 25)
+#define EN_MMC3				(1 << 30)
+
+#define PBIASLITEPWRDNZ0		(1 << 1)
+#define PBIASSPEEDCTRL0			(1 << 2)
+#define PBIASLITEPWRDNZ1		(1 << 9)
+#define PBIASLITEVMODE1			(1 << 8)
+#define PBIASLITEVMODE0			(1 << 0)
+
+#define CTLPROGIO1SPEEDCTRL		(1 << 20)
+
+/*
+ * OMAP HSMMC register definitions
+ */
+#define OMAP_HSMMC1_BASE	0x4809C000
+#define OMAP_HSMMC2_BASE	0x480B4000
+#define OMAP_HSMMC3_BASE	0x480AD000
+
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap3/musb.h b/arch/arm/include/asm/arch-omap3/musb.h
new file mode 100644
index 0000000..cb3f5d8
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/musb.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Ilya Yanok, <ilya.yanok@gmail.com>
+ */
+
+#ifndef __ASM_ARCH_OMAP3_MUSB_H
+#define __ASM_ARCH_OMAP3_MUSB_H
+void am35x_musb_reset(struct udevice *dev);
+void am35x_musb_phy_power(struct udevice *dev, u8 on);
+void am35x_musb_clear_irq(struct udevice *dev);
+#endif
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
new file mode 100644
index 0000000..2ed520d
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -0,0 +1,497 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ */
+#ifndef _MUX_H_
+#define _MUX_H_
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * SB_LOW - Standby mode configuration: Output low-level
+ * SB_HI - Standby mode configuration: Output high-level
+ * SB_HIZ - Standby mode configuration: Output hi-impedence
+ * SB_PD - Standby mode pull-down enabled
+ * SB_PU - Standby mode pull-up enabled
+ * WKEN - Wakeup input enabled
+ * M0   - Mode 0
+ */
+
+#define IEN	(1 << 8)
+
+#define IDIS	(0 << 8)
+#define PTU	(1 << 4)
+#define PTD	(0 << 4)
+#define EN	(1 << 3)
+#define DIS	(0 << 3)
+
+#define SB_LOW (1 << 9)
+#define SB_HI (5 << 9)
+#define SB_HIZ (2 << 9)
+#define SB_PD (1 << 12)
+#define SB_PU (3 << 12)
+#define WKEN (1 << 14)
+
+#define M0	0
+#define M1	1
+#define M2	2
+#define M3	3
+#define M4	4
+#define M5	5
+#define M6	6
+#define M7	7
+
+/*
+ * To get the actual address the offset has to be added
+ * to OMAP34XX_CTRL_BASE
+ */
+
+/*SDRC*/
+#define CONTROL_PADCONF_SDRC_D0		0x0030
+#define CONTROL_PADCONF_SDRC_D1		0x0032
+#define CONTROL_PADCONF_SDRC_D2		0x0034
+#define CONTROL_PADCONF_SDRC_D3		0x0036
+#define CONTROL_PADCONF_SDRC_D4		0x0038
+#define CONTROL_PADCONF_SDRC_D5		0x003A
+#define CONTROL_PADCONF_SDRC_D6		0x003C
+#define CONTROL_PADCONF_SDRC_D7		0x003E
+#define CONTROL_PADCONF_SDRC_D8		0x0040
+#define CONTROL_PADCONF_SDRC_D9		0x0042
+#define CONTROL_PADCONF_SDRC_D10	0x0044
+#define CONTROL_PADCONF_SDRC_D11	0x0046
+#define CONTROL_PADCONF_SDRC_D12	0x0048
+#define CONTROL_PADCONF_SDRC_D13	0x004A
+#define CONTROL_PADCONF_SDRC_D14	0x004C
+#define CONTROL_PADCONF_SDRC_D15	0x004E
+#define CONTROL_PADCONF_SDRC_D16	0x0050
+#define CONTROL_PADCONF_SDRC_D17	0x0052
+#define CONTROL_PADCONF_SDRC_D18	0x0054
+#define CONTROL_PADCONF_SDRC_D19	0x0056
+#define CONTROL_PADCONF_SDRC_D20	0x0058
+#define CONTROL_PADCONF_SDRC_D21	0x005A
+#define CONTROL_PADCONF_SDRC_D22	0x005C
+#define CONTROL_PADCONF_SDRC_D23	0x005E
+#define CONTROL_PADCONF_SDRC_D24	0x0060
+#define CONTROL_PADCONF_SDRC_D25	0x0062
+#define CONTROL_PADCONF_SDRC_D26	0x0064
+#define CONTROL_PADCONF_SDRC_D27	0x0066
+#define CONTROL_PADCONF_SDRC_D28	0x0068
+#define CONTROL_PADCONF_SDRC_D29	0x006A
+#define CONTROL_PADCONF_SDRC_D30	0x006C
+#define CONTROL_PADCONF_SDRC_D31	0x006E
+#define CONTROL_PADCONF_SDRC_CLK	0x0070
+#define CONTROL_PADCONF_SDRC_DQS0	0x0072
+#define CONTROL_PADCONF_SDRC_DQS1	0x0074
+#define CONTROL_PADCONF_SDRC_DQS2	0x0076
+#define CONTROL_PADCONF_SDRC_DQS3	0x0078
+#define CONTROL_PADCONF_SDRC_BA0	0x05A0
+#define CONTROL_PADCONF_SDRC_BA1	0x05A2
+#define CONTROL_PADCONF_SDRC_A0		0x05A4
+#define CONTROL_PADCONF_SDRC_A1		0x05A6
+#define CONTROL_PADCONF_SDRC_A2		0x05A8
+#define CONTROL_PADCONF_SDRC_A3		0x05AA
+#define CONTROL_PADCONF_SDRC_A4		0x05AC
+#define CONTROL_PADCONF_SDRC_A5		0x05AE
+#define CONTROL_PADCONF_SDRC_A6		0x05B0
+#define CONTROL_PADCONF_SDRC_A7		0x05B2
+#define CONTROL_PADCONF_SDRC_A8		0x05B4
+#define CONTROL_PADCONF_SDRC_A9		0x05B6
+#define CONTROL_PADCONF_SDRC_A10	0x05B8
+#define CONTROL_PADCONF_SDRC_A11	0x05BA
+#define CONTROL_PADCONF_SDRC_A12	0x05BC
+#define CONTROL_PADCONF_SDRC_A13	0x05BE
+#define CONTROL_PADCONF_SDRC_A14	0x05C0
+#define CONTROL_PADCONF_SDRC_NCS0	0x05C2
+#define CONTROL_PADCONF_SDRC_NCS1	0x05C4
+#define CONTROL_PADCONF_SDRC_NCLK	0x05C6
+#define CONTROL_PADCONF_SDRC_NRAS	0x05C8
+#define CONTROL_PADCONF_SDRC_NCAS	0x05CA
+#define CONTROL_PADCONF_SDRC_NWE	0x05CC
+#define CONTROL_PADCONF_SDRC_DM0	0x05CE
+#define CONTROL_PADCONF_SDRC_DM1	0x05D0
+#define CONTROL_PADCONF_SDRC_DM2	0x05D2
+#define CONTROL_PADCONF_SDRC_DM3	0x05D4
+/*GPMC*/
+#define CONTROL_PADCONF_GPMC_A1		0x007A
+#define CONTROL_PADCONF_GPMC_A2		0x007C
+#define CONTROL_PADCONF_GPMC_A3		0x007E
+#define CONTROL_PADCONF_GPMC_A4		0x0080
+#define CONTROL_PADCONF_GPMC_A5		0x0082
+#define CONTROL_PADCONF_GPMC_A6		0x0084
+#define CONTROL_PADCONF_GPMC_A7		0x0086
+#define CONTROL_PADCONF_GPMC_A8		0x0088
+#define CONTROL_PADCONF_GPMC_A9		0x008A
+#define CONTROL_PADCONF_GPMC_A10	0x008C
+#define CONTROL_PADCONF_GPMC_A11	0x0264
+#define CONTROL_PADCONF_GPMC_D0		0x008E
+#define CONTROL_PADCONF_GPMC_D1		0x0090
+#define CONTROL_PADCONF_GPMC_D2		0x0092
+#define CONTROL_PADCONF_GPMC_D3		0x0094
+#define CONTROL_PADCONF_GPMC_D4		0x0096
+#define CONTROL_PADCONF_GPMC_D5		0x0098
+#define CONTROL_PADCONF_GPMC_D6		0x009A
+#define CONTROL_PADCONF_GPMC_D7		0x009C
+#define CONTROL_PADCONF_GPMC_D8		0x009E
+#define CONTROL_PADCONF_GPMC_D9		0x00A0
+#define CONTROL_PADCONF_GPMC_D10	0x00A2
+#define CONTROL_PADCONF_GPMC_D11	0x00A4
+#define CONTROL_PADCONF_GPMC_D12	0x00A6
+#define CONTROL_PADCONF_GPMC_D13	0x00A8
+#define CONTROL_PADCONF_GPMC_D14	0x00AA
+#define CONTROL_PADCONF_GPMC_D15	0x00AC
+#define CONTROL_PADCONF_GPMC_NCS0	0x00AE
+#define CONTROL_PADCONF_GPMC_NCS1	0x00B0
+#define CONTROL_PADCONF_GPMC_NCS2	0x00B2
+#define CONTROL_PADCONF_GPMC_NCS3	0x00B4
+#define CONTROL_PADCONF_GPMC_NCS4	0x00B6
+#define CONTROL_PADCONF_GPMC_NCS5	0x00B8
+#define CONTROL_PADCONF_GPMC_NCS6	0x00BA
+#define CONTROL_PADCONF_GPMC_NCS7	0x00BC
+#define CONTROL_PADCONF_GPMC_CLK	0x00BE
+#define CONTROL_PADCONF_GPMC_NADV_ALE	0x00C0
+#define CONTROL_PADCONF_GPMC_NOE	0x00C2
+#define CONTROL_PADCONF_GPMC_NWE	0x00C4
+#define CONTROL_PADCONF_GPMC_NBE0_CLE	0x00C6
+#define CONTROL_PADCONF_GPMC_NBE1	0x00C8
+#define CONTROL_PADCONF_GPMC_NWP	0x00CA
+#define CONTROL_PADCONF_GPMC_WAIT0	0x00CC
+#define CONTROL_PADCONF_GPMC_WAIT1	0x00CE
+#define CONTROL_PADCONF_GPMC_WAIT2	0x00D0
+#define CONTROL_PADCONF_GPMC_WAIT3	0x00D2
+/*DSS*/
+#define CONTROL_PADCONF_DSS_PCLK	0x00D4
+#define CONTROL_PADCONF_DSS_HSYNC	0x00D6
+#define CONTROL_PADCONF_DSS_VSYNC	0x00D8
+#define CONTROL_PADCONF_DSS_ACBIAS	0x00DA
+#define CONTROL_PADCONF_DSS_DATA0	0x00DC
+#define CONTROL_PADCONF_DSS_DATA1	0x00DE
+#define CONTROL_PADCONF_DSS_DATA2	0x00E0
+#define CONTROL_PADCONF_DSS_DATA3	0x00E2
+#define CONTROL_PADCONF_DSS_DATA4	0x00E4
+#define CONTROL_PADCONF_DSS_DATA5	0x00E6
+#define CONTROL_PADCONF_DSS_DATA6	0x00E8
+#define CONTROL_PADCONF_DSS_DATA7	0x00EA
+#define CONTROL_PADCONF_DSS_DATA8	0x00EC
+#define CONTROL_PADCONF_DSS_DATA9	0x00EE
+#define CONTROL_PADCONF_DSS_DATA10	0x00F0
+#define CONTROL_PADCONF_DSS_DATA11	0x00F2
+#define CONTROL_PADCONF_DSS_DATA12	0x00F4
+#define CONTROL_PADCONF_DSS_DATA13	0x00F6
+#define CONTROL_PADCONF_DSS_DATA14	0x00F8
+#define CONTROL_PADCONF_DSS_DATA15	0x00FA
+#define CONTROL_PADCONF_DSS_DATA16	0x00FC
+#define CONTROL_PADCONF_DSS_DATA17	0x00FE
+#define CONTROL_PADCONF_DSS_DATA18	0x0100
+#define CONTROL_PADCONF_DSS_DATA19	0x0102
+#define CONTROL_PADCONF_DSS_DATA20	0x0104
+#define CONTROL_PADCONF_DSS_DATA21	0x0106
+#define CONTROL_PADCONF_DSS_DATA22	0x0108
+#define CONTROL_PADCONF_DSS_DATA23	0x010A
+/*CAMERA*/
+#define CONTROL_PADCONF_CAM_HS		0x010C
+#define CONTROL_PADCONF_CAM_VS		0x010E
+#define CONTROL_PADCONF_CAM_XCLKA	0x0110
+#define CONTROL_PADCONF_CAM_PCLK	0x0112
+#define CONTROL_PADCONF_CAM_FLD		0x0114
+#define CONTROL_PADCONF_CAM_D0		0x0116
+#define CONTROL_PADCONF_CAM_D1		0x0118
+#define CONTROL_PADCONF_CAM_D2		0x011A
+#define CONTROL_PADCONF_CAM_D3		0x011C
+#define CONTROL_PADCONF_CAM_D4		0x011E
+#define CONTROL_PADCONF_CAM_D5		0x0120
+#define CONTROL_PADCONF_CAM_D6		0x0122
+#define CONTROL_PADCONF_CAM_D7		0x0124
+#define CONTROL_PADCONF_CAM_D8		0x0126
+#define CONTROL_PADCONF_CAM_D9		0x0128
+#define CONTROL_PADCONF_CAM_D10		0x012A
+#define CONTROL_PADCONF_CAM_D11		0x012C
+#define CONTROL_PADCONF_CAM_XCLKB	0x012E
+#define CONTROL_PADCONF_CAM_WEN		0x0130
+#define CONTROL_PADCONF_CAM_STROBE	0x0132
+#define CONTROL_PADCONF_CSI2_DX0	0x0134
+#define CONTROL_PADCONF_CSI2_DY0	0x0136
+#define CONTROL_PADCONF_CSI2_DX1	0x0138
+#define CONTROL_PADCONF_CSI2_DY1	0x013A
+/*Audio Interface */
+#define CONTROL_PADCONF_MCBSP2_FSX	0x013C
+#define CONTROL_PADCONF_MCBSP2_CLKX	0x013E
+#define CONTROL_PADCONF_MCBSP2_DR	0x0140
+#define CONTROL_PADCONF_MCBSP2_DX	0x0142
+#define CONTROL_PADCONF_MMC1_CLK	0x0144
+#define CONTROL_PADCONF_MMC1_CMD	0x0146
+#define CONTROL_PADCONF_MMC1_DAT0	0x0148
+#define CONTROL_PADCONF_MMC1_DAT1	0x014A
+#define CONTROL_PADCONF_MMC1_DAT2	0x014C
+#define CONTROL_PADCONF_MMC1_DAT3	0x014E
+#define CONTROL_PADCONF_MMC1_DAT4	0x0150
+#define CONTROL_PADCONF_MMC1_DAT5	0x0152
+#define CONTROL_PADCONF_MMC1_DAT6	0x0154
+#define CONTROL_PADCONF_MMC1_DAT7	0x0156
+/*Wireless LAN */
+#define CONTROL_PADCONF_MMC2_CLK	0x0158
+#define CONTROL_PADCONF_MMC2_CMD	0x015A
+#define CONTROL_PADCONF_MMC2_DAT0	0x015C
+#define CONTROL_PADCONF_MMC2_DAT1	0x015E
+#define CONTROL_PADCONF_MMC2_DAT2	0x0160
+#define CONTROL_PADCONF_MMC2_DAT3	0x0162
+#define CONTROL_PADCONF_MMC2_DAT4	0x0164
+#define CONTROL_PADCONF_MMC2_DAT5	0x0166
+#define CONTROL_PADCONF_MMC2_DAT6	0x0168
+#define CONTROL_PADCONF_MMC2_DAT7	0x016A
+/*Bluetooth*/
+#define CONTROL_PADCONF_MCBSP3_DX	0x016C
+#define CONTROL_PADCONF_MCBSP3_DR	0x016E
+#define CONTROL_PADCONF_MCBSP3_CLKX	0x0170
+#define CONTROL_PADCONF_MCBSP3_FSX	0x0172
+#define CONTROL_PADCONF_UART2_CTS	0x0174
+#define CONTROL_PADCONF_UART2_RTS	0x0176
+#define CONTROL_PADCONF_UART2_TX	0x0178
+#define CONTROL_PADCONF_UART2_RX	0x017A
+/*Modem Interface */
+#define CONTROL_PADCONF_UART1_TX	0x017C
+#define CONTROL_PADCONF_UART1_RTS	0x017E
+#define CONTROL_PADCONF_UART1_CTS	0x0180
+#define CONTROL_PADCONF_UART1_RX	0x0182
+#define CONTROL_PADCONF_MCBSP4_CLKX	0x0184
+#define CONTROL_PADCONF_MCBSP4_DR	0x0186
+#define CONTROL_PADCONF_MCBSP4_DX	0x0188
+#define CONTROL_PADCONF_MCBSP4_FSX	0x018A
+#define CONTROL_PADCONF_MCBSP1_CLKR	0x018C
+#define CONTROL_PADCONF_MCBSP1_FSR	0x018E
+#define CONTROL_PADCONF_MCBSP1_DX	0x0190
+#define CONTROL_PADCONF_MCBSP1_DR	0x0192
+#define CONTROL_PADCONF_MCBSP_CLKS	0x0194
+#define CONTROL_PADCONF_MCBSP1_FSX	0x0196
+#define CONTROL_PADCONF_MCBSP1_CLKX	0x0198
+/*Serial Interface*/
+#define CONTROL_PADCONF_UART3_CTS_RCTX	0x019A
+#define CONTROL_PADCONF_UART3_RTS_SD	0x019C
+#define CONTROL_PADCONF_UART3_RX_IRRX	0x019E
+#define CONTROL_PADCONF_UART3_TX_IRTX	0x01A0
+#define CONTROL_PADCONF_HSUSB0_CLK	0x01A2
+#define CONTROL_PADCONF_HSUSB0_STP	0x01A4
+#define CONTROL_PADCONF_HSUSB0_DIR	0x01A6
+#define CONTROL_PADCONF_HSUSB0_NXT	0x01A8
+#define CONTROL_PADCONF_HSUSB0_DATA0	0x01AA
+#define CONTROL_PADCONF_HSUSB0_DATA1	0x01AC
+#define CONTROL_PADCONF_HSUSB0_DATA2	0x01AE
+#define CONTROL_PADCONF_HSUSB0_DATA3	0x01B0
+#define CONTROL_PADCONF_HSUSB0_DATA4	0x01B2
+#define CONTROL_PADCONF_HSUSB0_DATA5	0x01B4
+#define CONTROL_PADCONF_HSUSB0_DATA6	0x01B6
+#define CONTROL_PADCONF_HSUSB0_DATA7	0x01B8
+#define CONTROL_PADCONF_I2C1_SCL	0x01BA
+#define CONTROL_PADCONF_I2C1_SDA	0x01BC
+#define CONTROL_PADCONF_I2C2_SCL	0x01BE
+#define CONTROL_PADCONF_I2C2_SDA	0x01C0
+#define CONTROL_PADCONF_I2C3_SCL	0x01C2
+#define CONTROL_PADCONF_I2C3_SDA	0x01C4
+#define CONTROL_PADCONF_I2C4_SCL	0x0A00
+#define CONTROL_PADCONF_I2C4_SDA	0x0A02
+#define CONTROL_PADCONF_HDQ_SIO		0x01C6
+#define CONTROL_PADCONF_MCSPI1_CLK	0x01C8
+#define CONTROL_PADCONF_MCSPI1_SIMO	0x01CA
+#define CONTROL_PADCONF_MCSPI1_SOMI	0x01CC
+#define CONTROL_PADCONF_MCSPI1_CS0	0x01CE
+#define CONTROL_PADCONF_MCSPI1_CS1	0x01D0
+#define CONTROL_PADCONF_MCSPI1_CS2	0x01D2
+#define CONTROL_PADCONF_MCSPI1_CS3	0x01D4
+#define CONTROL_PADCONF_MCSPI2_CLK	0x01D6
+#define CONTROL_PADCONF_MCSPI2_SIMO	0x01D8
+#define CONTROL_PADCONF_MCSPI2_SOMI	0x01DA
+#define CONTROL_PADCONF_MCSPI2_CS0	0x01DC
+#define CONTROL_PADCONF_MCSPI2_CS1	0x01DE
+/*Control and debug */
+#define CONTROL_PADCONF_SYS_32K		0x0A04
+#define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
+#define CONTROL_PADCONF_SYS_NIRQ	0x01E0
+#define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
+#define CONTROL_PADCONF_SYS_BOOT1	0x0A0C
+#define CONTROL_PADCONF_SYS_BOOT2	0x0A0E
+#define CONTROL_PADCONF_SYS_BOOT3	0x0A10
+#define CONTROL_PADCONF_SYS_BOOT4	0x0A12
+#define CONTROL_PADCONF_SYS_BOOT5	0x0A14
+#define CONTROL_PADCONF_SYS_BOOT6	0x0A16
+#define CONTROL_PADCONF_SYS_OFF_MODE	0x0A18
+#define CONTROL_PADCONF_SYS_CLKOUT1	0x0A1A
+#define CONTROL_PADCONF_SYS_CLKOUT2	0x01E2
+#define CONTROL_PADCONF_JTAG_NTRST	0x0A1C
+#define CONTROL_PADCONF_JTAG_TCK	0x0A1E
+#define CONTROL_PADCONF_JTAG_TMS	0x0A20
+#define CONTROL_PADCONF_JTAG_TDI	0x0A22
+#define CONTROL_PADCONF_JTAG_EMU0	0x0A24
+#define CONTROL_PADCONF_JTAG_EMU1	0x0A26
+#define CONTROL_PADCONF_ETK_CLK		0x0A28
+#define CONTROL_PADCONF_ETK_CTL		0x0A2A
+#define CONTROL_PADCONF_ETK_D0		0x0A2C
+#define CONTROL_PADCONF_ETK_D1		0x0A2E
+#define CONTROL_PADCONF_ETK_D2		0x0A30
+#define CONTROL_PADCONF_ETK_D3		0x0A32
+#define CONTROL_PADCONF_ETK_D4		0x0A34
+#define CONTROL_PADCONF_ETK_D5		0x0A36
+#define CONTROL_PADCONF_ETK_D6		0x0A38
+#define CONTROL_PADCONF_ETK_D7		0x0A3A
+#define CONTROL_PADCONF_ETK_D8		0x0A3C
+#define CONTROL_PADCONF_ETK_D9		0x0A3E
+#define CONTROL_PADCONF_ETK_D10		0x0A40
+#define CONTROL_PADCONF_ETK_D11		0x0A42
+#define CONTROL_PADCONF_ETK_D12		0x0A44
+#define CONTROL_PADCONF_ETK_D13		0x0A46
+#define CONTROL_PADCONF_ETK_D14		0x0A48
+#define CONTROL_PADCONF_ETK_D15		0x0A4A
+#define CONTROL_PADCONF_ETK_CLK_ES2	0x05D8
+#define CONTROL_PADCONF_ETK_CTL_ES2	0x05DA
+#define CONTROL_PADCONF_ETK_D0_ES2	0x05DC
+#define CONTROL_PADCONF_ETK_D1_ES2	0x05DE
+#define CONTROL_PADCONF_ETK_D2_ES2	0x05E0
+#define CONTROL_PADCONF_ETK_D3_ES2	0x05E2
+#define CONTROL_PADCONF_ETK_D4_ES2	0x05E4
+#define CONTROL_PADCONF_ETK_D5_ES2	0x05E6
+#define CONTROL_PADCONF_ETK_D6_ES2	0x05E8
+#define CONTROL_PADCONF_ETK_D7_ES2	0x05EA
+#define CONTROL_PADCONF_ETK_D8_ES2	0x05EC
+#define CONTROL_PADCONF_ETK_D9_ES2	0x05EE
+#define CONTROL_PADCONF_ETK_D10_ES2	0x05F0
+#define CONTROL_PADCONF_ETK_D11_ES2	0x05F2
+#define CONTROL_PADCONF_ETK_D12_ES2	0x05F4
+#define CONTROL_PADCONF_ETK_D13_ES2	0x05F6
+#define CONTROL_PADCONF_ETK_D14_ES2	0x05F8
+#define CONTROL_PADCONF_ETK_D15_ES2	0x05FA
+#define CONTROL_PADCONF_JTAG_RTCK	0x0A4E
+#define CONTROL_PADCONF_JTAG_TDO	0x0A50
+/*Die to Die */
+#define CONTROL_PADCONF_D2D_MCAD0	0x01E4
+#define CONTROL_PADCONF_D2D_MCAD1	0x01E6
+#define CONTROL_PADCONF_D2D_MCAD2	0x01E8
+#define CONTROL_PADCONF_D2D_MCAD3	0x01EA
+#define CONTROL_PADCONF_D2D_MCAD4	0x01EC
+#define CONTROL_PADCONF_D2D_MCAD5	0x01EE
+#define CONTROL_PADCONF_D2D_MCAD6	0x01F0
+#define CONTROL_PADCONF_D2D_MCAD7	0x01F2
+#define CONTROL_PADCONF_D2D_MCAD8	0x01F4
+#define CONTROL_PADCONF_D2D_MCAD9	0x01F6
+#define CONTROL_PADCONF_D2D_MCAD10	0x01F8
+#define CONTROL_PADCONF_D2D_MCAD11	0x01FA
+#define CONTROL_PADCONF_D2D_MCAD12	0x01FC
+#define CONTROL_PADCONF_D2D_MCAD13	0x01FE
+#define CONTROL_PADCONF_D2D_MCAD14	0x0200
+#define CONTROL_PADCONF_D2D_MCAD15	0x0202
+#define CONTROL_PADCONF_D2D_MCAD16	0x0204
+#define CONTROL_PADCONF_D2D_MCAD17	0x0206
+#define CONTROL_PADCONF_D2D_MCAD18	0x0208
+#define CONTROL_PADCONF_D2D_MCAD19	0x020A
+#define CONTROL_PADCONF_D2D_MCAD20	0x020C
+#define CONTROL_PADCONF_D2D_MCAD21	0x020E
+#define CONTROL_PADCONF_D2D_MCAD22	0x0210
+#define CONTROL_PADCONF_D2D_MCAD23	0x0212
+#define CONTROL_PADCONF_D2D_MCAD24	0x0214
+#define CONTROL_PADCONF_D2D_MCAD25	0x0216
+#define CONTROL_PADCONF_D2D_MCAD26	0x0218
+#define CONTROL_PADCONF_D2D_MCAD27	0x021A
+#define CONTROL_PADCONF_D2D_MCAD28	0x021C
+#define CONTROL_PADCONF_D2D_MCAD29	0x021E
+#define CONTROL_PADCONF_D2D_MCAD30	0x0220
+#define CONTROL_PADCONF_D2D_MCAD31	0x0222
+#define CONTROL_PADCONF_D2D_MCAD32	0x0224
+#define CONTROL_PADCONF_D2D_MCAD33	0x0226
+#define CONTROL_PADCONF_D2D_MCAD34	0x0228
+#define CONTROL_PADCONF_D2D_MCAD35	0x022A
+#define CONTROL_PADCONF_D2D_MCAD36	0x022C
+#define CONTROL_PADCONF_D2D_CLK26MI	0x022E
+#define CONTROL_PADCONF_D2D_NRESPWRON	0x0230
+#define CONTROL_PADCONF_D2D_NRESWARM	0x0232
+#define CONTROL_PADCONF_D2D_ARM9NIRQ	0x0234
+#define CONTROL_PADCONF_D2D_UMA2P6FIQ	0x0236
+#define CONTROL_PADCONF_D2D_SPINT	0x0238
+#define CONTROL_PADCONF_D2D_FRINT	0x023A
+#define CONTROL_PADCONF_D2D_DMAREQ0	0x023C
+#define CONTROL_PADCONF_D2D_DMAREQ1	0x023E
+#define CONTROL_PADCONF_D2D_DMAREQ2	0x0240
+#define CONTROL_PADCONF_D2D_DMAREQ3	0x0242
+#define CONTROL_PADCONF_D2D_N3GTRST	0x0244
+#define CONTROL_PADCONF_D2D_N3GTDI	0x0246
+#define CONTROL_PADCONF_D2D_N3GTDO	0x0248
+#define CONTROL_PADCONF_D2D_N3GTMS	0x024A
+#define CONTROL_PADCONF_D2D_N3GTCK	0x024C
+#define CONTROL_PADCONF_D2D_N3GRTCK	0x024E
+#define CONTROL_PADCONF_D2D_MSTDBY	0x0250
+#define CONTROL_PADCONF_D2D_SWAKEUP	0x0A4C
+#define CONTROL_PADCONF_D2D_IDLEREQ	0x0252
+#define CONTROL_PADCONF_D2D_IDLEACK	0x0254
+#define CONTROL_PADCONF_D2D_MWRITE	0x0256
+#define CONTROL_PADCONF_D2D_SWRITE	0x0258
+#define CONTROL_PADCONF_D2D_MREAD	0x025A
+#define CONTROL_PADCONF_D2D_SREAD	0x025C
+#define CONTROL_PADCONF_D2D_MBUSFLAG	0x025E
+#define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
+#define CONTROL_PADCONF_SDRC_CKE0	0x0262
+#define CONTROL_PADCONF_SDRC_CKE1	0x0264
+
+/* AM3517 specific mux configuration */
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
+/* CCDC */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
+#define CONTROL_PADCONF_CCDC_HD		0x01E8
+#define CONTROL_PADCONF_CCDC_VD		0x01EA
+#define CONTROL_PADCONF_CCDC_WEN	0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0	0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1	0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2	0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3	0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4	0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5	0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6	0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7	0x01FC
+/* RMII */
+#define CONTROL_PADCONF_RMII_MDIO_DATA	0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK	0x0200
+#define CONTROL_PADCONF_RMII_RXD0	0x0202
+#define CONTROL_PADCONF_RMII_RXD1	0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV	0x0206
+#define CONTROL_PADCONF_RMII_RXER	0x0208
+#define CONTROL_PADCONF_RMII_TXD0	0x020A
+#define CONTROL_PADCONF_RMII_TXD1	0x020C
+#define CONTROL_PADCONF_RMII_TXEN	0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK	0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS	0x0212
+/* CAN */
+#define CONTROL_PADCONF_HECC1_TXD	0x0214
+#define CONTROL_PADCONF_HECC1_RXD	0x0216
+
+#define CONTROL_PADCONF_SYS_BOOT7	0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N	0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N	0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N	0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N	0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0	0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1	0x0224
+#define CONTROL_PADCONF_SYS_BOOT8	0x0226
+
+/* AM/DM37xx specific */
+#define CONTROL_PADCONF_GPIO112		0x0134
+#define CONTROL_PADCONF_GPIO113		0x0136
+#define CONTROL_PADCONF_GPIO114		0x0138
+#define CONTROL_PADCONF_GPIO115		0x013A
+#define CONTROL_PADCONF_GPIO127		0x0A54
+#define CONTROL_PADCONF_GPIO126		0x0A56
+#define CONTROL_PADCONF_GPIO128		0x0A58
+#define CONTROL_PADCONF_GPIO129		0x0A5A
+
+/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration
+ * of the extended drain cells */
+#define OMAP34XX_CTRL_WKUP_CTRL		(OMAP34XX_CTRL_BASE + 0x0A5C)
+#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ	(1<<6)
+
+#define MUX_VAL(OFFSET, VALUE)\
+	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
+
+#define	CP(x)	(CONTROL_PADCONF_##x)
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h
new file mode 100644
index 0000000..19155a2
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/omap.h
@@ -0,0 +1,284 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ */
+
+#ifndef _OMAP3_H_
+#define _OMAP3_H_
+
+#include <linux/sizes.h>
+
+/* Stuff on L3 Interconnect */
+#define SMX_APE_BASE			0x68000000
+
+/* GPMC */
+#define OMAP34XX_GPMC_BASE		0x6E000000
+
+/* SMS */
+#define OMAP34XX_SMS_BASE		0x6C000000
+
+/* SDRC */
+#define OMAP34XX_SDRC_BASE		0x6D000000
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP34XX_CORE_L4_IO_BASE	0x48000000
+#define OMAP34XX_WAKEUP_L4_IO_BASE	0x48300000
+#define OMAP34XX_ID_L4_IO_BASE		0x4830A200
+#define OMAP34XX_L4_PER			0x49000000
+#define OMAP34XX_L4_IO_BASE		OMAP34XX_CORE_L4_IO_BASE
+
+/* DMA4/SDMA */
+#define OMAP34XX_DMA4_BASE              0x48056000
+
+/* CONTROL */
+#define OMAP34XX_CTRL_BASE		(OMAP34XX_L4_IO_BASE + 0x2000)
+
+#ifndef __ASSEMBLY__
+/* Signal Integrity Parameter Control Registers */
+struct control_prog_io {
+	unsigned char res[0x408];
+	unsigned int io2;		/* 0x408 */
+	unsigned char res2[0x38];
+	unsigned int io0;		/* 0x444 */
+	unsigned int io1;		/* 0x448 */
+};
+#endif /* __ASSEMBLY__ */
+
+/* Bit definition for CONTROL_PROG_IO1 */
+#define PRG_I2C2_PULLUPRESX		0x00000001
+
+/* Scratchpad memory */
+#define OMAP34XX_SCRATCHPAD		(OMAP34XX_CTRL_BASE + 0x910)
+
+/* UART */
+#define OMAP34XX_UART1			(OMAP34XX_L4_IO_BASE + 0x6a000)
+#define OMAP34XX_UART2			(OMAP34XX_L4_IO_BASE + 0x6c000)
+#define OMAP34XX_UART3			(OMAP34XX_L4_PER + 0x20000)
+#define OMAP34XX_UART4			(OMAP34XX_L4_PER + 0x42000)
+
+/* General Purpose Timers */
+#define OMAP34XX_GPT1			0x48318000
+#define OMAP34XX_GPT2			0x49032000
+#define OMAP34XX_GPT3			0x49034000
+#define OMAP34XX_GPT4			0x49036000
+#define OMAP34XX_GPT5			0x49038000
+#define OMAP34XX_GPT6			0x4903A000
+#define OMAP34XX_GPT7			0x4903C000
+#define OMAP34XX_GPT8			0x4903E000
+#define OMAP34XX_GPT9			0x49040000
+#define OMAP34XX_GPT10			0x48086000
+#define OMAP34XX_GPT11			0x48088000
+#define OMAP34XX_GPT12			0x48304000
+
+/* WatchDog Timers (1 secure, 3 GP) */
+#define WD1_BASE			0x4830C000
+#define WD2_BASE			0x48314000
+#define WD3_BASE			0x49030000
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE		0x48320000
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+	unsigned char res[0x10];
+	unsigned int s32k_cr;		/* 0x10 */
+};
+
+#define DEVICE_TYPE_SHIFT		0x8
+#define DEVICE_TYPE_MASK		(0x7 << DEVICE_TYPE_SHIFT)
+
+#endif /* __ASSEMBLY__ */
+
+#ifndef __ASSEMBLY__
+struct gpio {
+	unsigned char res1[0x34];
+	unsigned int oe;		/* 0x34 */
+	unsigned int datain;		/* 0x38 */
+	unsigned char res2[0x54];
+	unsigned int cleardataout;	/* 0x90 */
+	unsigned int setdataout;	/* 0x94 */
+};
+#endif /* __ASSEMBLY__ */
+
+#define GPIO0				(0x1 << 0)
+#define GPIO1				(0x1 << 1)
+#define GPIO2				(0x1 << 2)
+#define GPIO3				(0x1 << 3)
+#define GPIO4				(0x1 << 4)
+#define GPIO5				(0x1 << 5)
+#define GPIO6				(0x1 << 6)
+#define GPIO7				(0x1 << 7)
+#define GPIO8				(0x1 << 8)
+#define GPIO9				(0x1 << 9)
+#define GPIO10				(0x1 << 10)
+#define GPIO11				(0x1 << 11)
+#define GPIO12				(0x1 << 12)
+#define GPIO13				(0x1 << 13)
+#define GPIO14				(0x1 << 14)
+#define GPIO15				(0x1 << 15)
+#define GPIO16				(0x1 << 16)
+#define GPIO17				(0x1 << 17)
+#define GPIO18				(0x1 << 18)
+#define GPIO19				(0x1 << 19)
+#define GPIO20				(0x1 << 20)
+#define GPIO21				(0x1 << 21)
+#define GPIO22				(0x1 << 22)
+#define GPIO23				(0x1 << 23)
+#define GPIO24				(0x1 << 24)
+#define GPIO25				(0x1 << 25)
+#define GPIO26				(0x1 << 26)
+#define GPIO27				(0x1 << 27)
+#define GPIO28				(0x1 << 28)
+#define GPIO29				(0x1 << 29)
+#define GPIO30				(0x1 << 30)
+#define GPIO31				(0x1 << 31)
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_OFFSET0			0x40000000
+#define SRAM_OFFSET1			0x00200000
+#define SRAM_OFFSET2			0x0000F800
+#define SRAM_VECT_CODE			(SRAM_OFFSET0 | SRAM_OFFSET1 | \
+					 SRAM_OFFSET2)
+#define SRAM_CLK_CODE			(SRAM_VECT_CODE + 64)
+
+#define NON_SECURE_SRAM_START		0x40208000 /* Works for GP & EMU */
+#define NON_SECURE_SRAM_END		0x40210000
+#define NON_SECURE_SRAM_IMG_END		0x4020F000
+#define SRAM_SCRATCH_SPACE_ADDR		(NON_SECURE_SRAM_IMG_END - SZ_1K)
+
+#define LOW_LEVEL_SRAM_STACK		0x4020FFFC
+
+/* scratch area - accessible on both EMU and GP */
+#define OMAP3_PUBLIC_SRAM_SCRATCH_AREA	NON_SECURE_SRAM_START
+
+#define DEBUG_LED1			149	/* gpio */
+#define DEBUG_LED2			150	/* gpio */
+
+#define XDR_POP		5	/* package on package part */
+#define SDR_DISCRETE	4	/* 128M memory SDR module */
+#define DDR_STACKED	3	/* stacked part on 2422 */
+#define DDR_COMBO	2	/* combo part on cpu daughter card */
+#define DDR_DISCRETE	1	/* 2x16 parts on daughter card */
+
+#define DDR_100		100	/* type found on most mem d-boards */
+#define DDR_111		111	/* some combo parts */
+#define DDR_133		133	/* most combo, some mem d-boards */
+#define DDR_165		165	/* future parts */
+
+#define CPU_3430	0x3430
+
+/*
+ * 343x real hardware:
+ *  ES1     = rev 0
+ *
+ *  ES2 onwards, the value maps to contents of IDCODE register [31:28].
+ *
+ * Note : CPU_3XX_ES20 is used in cache.S.  Please review before changing.
+ */
+#define CPU_3XX_ES10		0
+#define CPU_3XX_ES20		1
+#define CPU_3XX_ES21		2
+#define CPU_3XX_ES30		3
+#define CPU_3XX_ES31		4
+#define CPU_3XX_ES312		7
+#define CPU_3XX_MAX_REV		8
+
+/*
+ * 37xx real hardware:
+ * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
+ */
+
+#define CPU_37XX_ES10		0
+#define CPU_37XX_ES11		1
+#define CPU_37XX_ES12		2
+#define CPU_37XX_MAX_REV	3
+
+#define CPU_3XX_ID_SHIFT	28
+
+#define WIDTH_8BIT		0x0000
+#define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
+
+/*
+ * Hawkeye values
+ */
+#define HAWKEYE_OMAP34XX	0xb7ae
+#define HAWKEYE_AM35XX		0xb868
+#define HAWKEYE_OMAP36XX	0xb891
+
+#define HAWKEYE_SHIFT		12
+
+/*
+ * Define CPU families
+ */
+#define CPU_OMAP34XX		0x3400	/* OMAP34xx/OMAP35 devices */
+#define CPU_AM35XX		0x3500	/* AM35xx devices          */
+#define CPU_OMAP36XX		0x3600	/* OMAP36xx devices        */
+
+/*
+ * Control status register values corresponding to cpu variants
+ */
+#define OMAP3503		0x5c00
+#define OMAP3515		0x1c00
+#define OMAP3525		0x4c00
+#define OMAP3530		0x0c00
+
+#define AM3505			0x5c00
+#define AM3517			0x1c00
+
+#define OMAP3730		0x0c00
+#define OMAP3725		0x4c00
+#define AM3715			0x1c00
+#define AM3703			0x5c00
+
+#define OMAP3730_1GHZ		0x0e00
+#define OMAP3725_1GHZ		0x4e00
+#define AM3715_1GHZ		0x1e00
+#define AM3703_1GHZ		0x5e00
+
+/*
+ * ROM code API related flags
+ */
+#define OMAP3_GP_ROMCODE_API_L2_INVAL		1
+#define OMAP3_GP_ROMCODE_API_WRITE_L2ACR	2
+#define OMAP3_GP_ROMCODE_API_WRITE_ACR		3
+
+/*
+ * EMU device PPA HAL related flags
+ */
+#define OMAP3_EMU_HAL_API_L2_INVAL		40
+#define OMAP3_EMU_HAL_API_WRITE_ACR		42
+
+#define OMAP3_EMU_HAL_START_HAL_CRITICAL	4
+
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME		30
+#define OMAP_ABB_CLOCK_CYCLES		8
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK	(0x1 << 26)
+
+#define OMAP_REBOOT_REASON_OFFSET	0x04
+
+/* Boot parameters */
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+	unsigned int boot_message;
+	unsigned char boot_device;
+	unsigned char reserved;
+	unsigned char reset_reason;
+	unsigned char ch_flags;
+	unsigned int boot_device_descriptor;
+};
+
+int omap_reboot_mode(char *mode, unsigned int length);
+int omap_reboot_mode_clear(void);
+int omap_reboot_mode_store(char *mode);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap3/omap3-regs.h b/arch/arm/include/asm/arch-omap3/omap3-regs.h
new file mode 100644
index 0000000..7b3c6c7
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/omap3-regs.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it>
+ */
+
+#ifndef _OMAP3_REGS_H
+#define _OMAP3_REGS_H
+
+/*
+ * Register definitions for OMAP3 processors.
+ */
+
+/*
+ * GPMC_CONFIG1 - GPMC_CONFIG7
+ */
+
+/* Values for GPMC_CONFIG1 - signal control parameters */
+#define WRAPBURST                     (1 << 31)
+#define READMULTIPLE                  (1 << 30)
+#define READTYPE                      (1 << 29)
+#define WRITEMULTIPLE                 (1 << 28)
+#define WRITETYPE                     (1 << 27)
+#define CLKACTIVATIONTIME(x)          (((x) & 3) << 25)
+#define ATTACHEDDEVICEPAGELENGTH(x)   (((x) & 3) << 23)
+#define WAITREADMONITORING            (1 << 22)
+#define WAITWRITEMONITORING           (1 << 21)
+#define WAITMONITORINGTIME(x)         (((x) & 3) << 18)
+#define WAITPINSELECT(x)              (((x) & 3) << 16)
+#define DEVICESIZE(x)                 (((x) & 3) << 12)
+#define DEVICESIZE_8BIT               DEVICESIZE(0)
+#define DEVICESIZE_16BIT              DEVICESIZE(1)
+#define DEVICETYPE(x)                 (((x) & 3) << 10)
+#define DEVICETYPE_NOR                DEVICETYPE(0)
+#define DEVICETYPE_NAND               DEVICETYPE(2)
+#define MUXADDDATA                    (1 << 9)
+#define TIMEPARAGRANULARITY           (1 << 4)
+#define GPMCFCLKDIVIDER(x)            (((x) & 3) << 0)
+
+/* Values for GPMC_CONFIG2 - CS timing */
+#define CSWROFFTIME(x)   (((x) & 0x1f) << 16)
+#define CSRDOFFTIME(x)   (((x) & 0x1f) <<  8)
+#define CSEXTRADELAY     (1 << 7)
+#define CSONTIME(x)      (((x) &  0xf) <<  0)
+
+/* Values for GPMC_CONFIG3 - nADV timing */
+#define ADVWROFFTIME(x)  (((x) & 0x1f) << 16)
+#define ADVRDOFFTIME(x)  (((x) & 0x1f) <<  8)
+#define ADVEXTRADELAY    (1 << 7)
+#define ADVONTIME(x)     (((x) &  0xf) <<  0)
+
+/* Values for GPMC_CONFIG4 - nWE and nOE timing */
+#define WEOFFTIME(x)     (((x) & 0x1f) << 24)
+#define WEEXTRADELAY     (1 << 23)
+#define WEONTIME(x)      (((x) &  0xf) << 16)
+#define OEOFFTIME(x)     (((x) & 0x1f) <<  8)
+#define OEEXTRADELAY     (1 << 7)
+#define OEONTIME(x)      (((x) &  0xf) <<  0)
+
+/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */
+#define PAGEBURSTACCESSTIME(x)  (((x) &  0xf) << 24)
+#define RDACCESSTIME(x)         (((x) & 0x1f) << 16)
+#define WRCYCLETIME(x)          (((x) & 0x1f) <<  8)
+#define RDCYCLETIME(x)          (((x) & 0x1f) <<  0)
+
+/* Values for GPMC_CONFIG6 - misc timings */
+#define WRACCESSTIME(x)        (((x) & 0x1f) << 24)
+#define WRDATAONADMUXBUS(x)    (((x) &  0xf) << 16)
+#define CYCLE2CYCLEDELAY(x)    (((x) &  0xf) <<  8)
+#define CYCLE2CYCLESAMECSEN    (1 << 7)
+#define CYCLE2CYCLEDIFFCSEN    (1 << 6)
+#define BUSTURNAROUND(x)       (((x) &  0xf) <<  0)
+
+/* Values for GPMC_CONFIG7 - CS address mapping configuration */
+#define MASKADDRESS(x)         (((x) &  0xf) <<  8)
+#define CSVALID                (1 << 6)
+#define BASEADDRESS(x)         (((x) & 0x3f) <<  0)
+
+#endif /* _OMAP3_REGS_H */
diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h
new file mode 100644
index 0000000..86b1f46
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/spl.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NONE	0x00
+#define BOOT_DEVICE_XIP		0x01
+#define BOOT_DEVICE_NAND	0x02
+#define BOOT_DEVICE_ONENAND	0x03
+#define BOOT_DEVICE_MMC2	0x05
+#define BOOT_DEVICE_MMC1	0x06
+#define BOOT_DEVICE_XIPWAIT	0x07
+#define BOOT_DEVICE_MMC2_2      0x08
+#define BOOT_DEVICE_UART	0x10
+#define BOOT_DEVICE_USB		0x11
+
+#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC2
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC1
+#endif
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
new file mode 100644
index 0000000..32ac033
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ */
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+#include <linux/mtd/omap_gpmc.h>
+#include <asm/omap_common.h>
+
+typedef struct {
+	u32 mtype;
+	char *board_string;
+	char *nand_string;
+} omap3_sysinfo;
+
+struct emu_hal_params {
+	u32 num_params;
+	u32 param1;
+};
+
+/* Board SDRC timing values */
+struct board_sdrc_timings {
+	u32 sharing;
+	u32 mcfg;
+	u32 ctrla;
+	u32 ctrlb;
+	u32 rfr_ctrl;
+	u32 mr;
+};
+
+void prcm_init(void);
+void per_clocks_enable(void);
+void ehci_clocks_enable(void);
+
+void memif_init(void);
+void sdrc_init(void);
+void do_sdrc_init(u32, u32);
+
+void get_board_mem_timings(struct board_sdrc_timings *timings);
+int identify_nand_chip(int *mfr, int *id);
+void emif4_init(void);
+void gpmc_init(void);
+void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
+				u32 base, u32 size);
+void set_gpmc_cs0(int flash_type);
+
+void watchdog_init(void);
+void set_muxconf_regs(void);
+
+u32 get_cpu_family(void);
+u32 get_cpu_rev(void);
+u32 get_sku_id(void);
+u32 is_gpmc_muxed(void);
+u32 get_gpmc0_type(void);
+u32 get_gpmc0_width(void);
+u32 is_running_in_sdram(void);
+u32 is_running_in_sram(void);
+u32 is_running_in_flash(void);
+u32 get_device_type(void);
+void secureworld_exit(void);
+void try_unlock_memory(void);
+u32 get_boot_type(void);
+void invalidate_dcache(u32);
+u32 wait_on_value(u32, u32, void *, u32);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
+void sdelay(unsigned long);
+void make_cs1_contiguous(void);
+int omap_nand_switch_ecc(uint32_t, uint32_t);
+void power_init_r(void);
+void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
+void omap3_set_aux_cr_secure(u32 acr);
+u32 warm_reset(void);
+
+void save_omap_boot_params(void);
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h
new file mode 100644
index 0000000..037045c
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/clock.h
@@ -0,0 +1,252 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ */
+#ifndef _CLOCKS_OMAP4_H_
+#define _CLOCKS_OMAP4_H_
+#include <common.h>
+#include <asm/omap_common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY		1000000
+
+/* CM_DLL_CTRL */
+#define CM_DLL_CTRL_OVERRIDE_SHIFT	0
+#define CM_DLL_CTRL_OVERRIDE_MASK	(1 << 0)
+#define CM_DLL_CTRL_NO_OVERRIDE		0
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_FAST_RELOCK_BYPASS	6
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT			22
+#define CM_CLKSEL_DCC_EN_MASK			(1 << 22)
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT	0
+#define CLKSEL_L3_SHIFT		4
+#define CLKSEL_L4_SHIFT		8
+
+#define CLKSEL_CORE_X2_DIV_1	0
+#define CLKSEL_L3_CORE_DIV_2	1
+#define CLKSEL_L4_L3_DIV_2	1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT		0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK		3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2		1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
+
+/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K	(1 << 8)
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	(1 << 8)
+
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(1 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	25
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 25)
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_IND_38_4_MHZ	6
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
+
+/* PMIC */
+#define SMPS_I2C_SLAVE_ADDR	0x12
+/* TWL6030 SMPS */
+#define SMPS_REG_ADDR_VCORE1	0x55
+#define SMPS_REG_ADDR_VCORE2	0x5B
+#define SMPS_REG_ADDR_VCORE3	0x61
+/* TWL6032 SMPS */
+#define SMPS_REG_ADDR_SMPS1	0x55
+#define SMPS_REG_ADDR_SMPS2	0x5B
+#define SMPS_REG_ADDR_SMPS5	0x49
+
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV		607700
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV	709000
+
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR		0x60
+#define TPS62361_REG_ADDR_SET0		0x0
+#define TPS62361_REG_ADDR_SET1		0x1
+#define TPS62361_REG_ADDR_SET2		0x2
+#define TPS62361_REG_ADDR_SET3		0x3
+#define TPS62361_REG_ADDR_CTRL		0x4
+#define TPS62361_REG_ADDR_TEMP		0x5
+#define TPS62361_REG_ADDR_RMP_CTRL	0x6
+#define TPS62361_REG_ADDR_CHIP_ID	0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2	0x9
+
+#define TPS62361_BASE_VOLT_MV	500
+#define TPS62361_VSEL0_GPIO	7
+
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK		(1 << 8)
+#define AUXCLK_SRCSELECT_SHIFT		1
+#define AUXCLK_SRCSELECT_MASK		(3 << 1)
+#define AUXCLK_CLKDIV_SHIFT		16
+#define AUXCLK_CLKDIV_MASK		(0xF << 16)
+
+#define AUXCLK_SRCSELECT_SYS_CLK	0
+#define AUXCLK_SRCSELECT_CORE_DPLL	1
+#define AUXCLK_SRCSELECT_PER_DPLL	2
+#define AUXCLK_SRCSELECT_ALTERNATE	3
+
+#define AUXCLK_CLKDIV_2			1
+#define AUXCLK_CLKDIV_16		0xF
+
+/* ALTCLKSRC */
+#define ALTCLKSRC_MODE_MASK		3
+#define ALTCLKSRC_ENABLE_INT_MASK	4
+#define ALTCLKSRC_ENABLE_EXT_MASK	8
+
+#define ALTCLKSRC_MODE_ACTIVE		1
+
+#define DPLL_NO_LOCK	0
+#define DPLL_LOCK	1
+
+/* Clock Defines */
+#define V_OSCK			38400000	/* Clock output from T2 */
+#define V_SCLK                   V_OSCK
+
+struct omap4_scrm_regs {
+	u32 revision;           /* 0x0000 */
+	u32 pad00[63];
+	u32 clksetuptime;       /* 0x0100 */
+	u32 pmicsetuptime;      /* 0x0104 */
+	u32 pad01[2];
+	u32 altclksrc;          /* 0x0110 */
+	u32 pad02[2];
+	u32 c2cclkm;            /* 0x011c */
+	u32 pad03[56];
+	u32 extclkreq;          /* 0x0200 */
+	u32 accclkreq;          /* 0x0204 */
+	u32 pwrreq;             /* 0x0208 */
+	u32 pad04[1];
+	u32 auxclkreq0;         /* 0x0210 */
+	u32 auxclkreq1;         /* 0x0214 */
+	u32 auxclkreq2;         /* 0x0218 */
+	u32 auxclkreq3;         /* 0x021c */
+	u32 auxclkreq4;         /* 0x0220 */
+	u32 auxclkreq5;         /* 0x0224 */
+	u32 pad05[3];
+	u32 c2cclkreq;          /* 0x0234 */
+	u32 pad06[54];
+	u32 auxclk0;            /* 0x0310 */
+	u32 auxclk1;            /* 0x0314 */
+	u32 auxclk2;            /* 0x0318 */
+	u32 auxclk3;            /* 0x031c */
+	u32 auxclk4;            /* 0x0320 */
+	u32 auxclk5;            /* 0x0324 */
+	u32 pad07[54];
+	u32 rsttime_reg;        /* 0x0400 */
+	u32 pad08[6];
+	u32 c2crstctrl;         /* 0x041c */
+	u32 extpwronrstctrl;    /* 0x0420 */
+	u32 pad09[59];
+	u32 extwarmrstst_reg;   /* 0x0510 */
+	u32 apewarmrstst_reg;   /* 0x0514 */
+	u32 pad10[1];
+	u32 c2cwarmrstst_reg;   /* 0x051C */
+};
+#endif /* _CLOCKS_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h
new file mode 100644
index 0000000..4c9ed45
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2010
+ * Texas Instruments, <www.ti.com>
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#include <asm/arch/hardware.h>
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gptimer {
+	u32 tidr;		/* 0x00 r */
+	u8 res[0xc];
+	u32 tiocp_cfg;		/* 0x10 rw */
+	u32 tistat;		/* 0x14 r */
+	u32 tisr;		/* 0x18 rw */
+	u32 tier;		/* 0x1c rw */
+	u32 twer;		/* 0x20 rw */
+	u32 tclr;		/* 0x24 rw */
+	u32 tcrr;		/* 0x28 rw */
+	u32 tldr;		/* 0x2c rw */
+	u32 ttgr;		/* 0x30 rw */
+	u32 twpc;		/* 0x34 r */
+	u32 tmar;		/* 0x38 rw */
+	u32 tcar1;		/* 0x3c r */
+	u32 tcicr;		/* 0x40 rw */
+	u32 tcar2;		/* 0x44 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+	u8 res1[0x34];
+	u32 wwps;		/* 0x34 r */
+	u8 res2[0x10];
+	u32 wspr;		/* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1		0xAAAA
+#define WD_UNLOCK2		0x5555
+
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
+
+/* I2C base */
+#define I2C_BASE1		(OMAP44XX_L4_PER_BASE + 0x70000)
+#define I2C_BASE2		(OMAP44XX_L4_PER_BASE + 0x72000)
+#define I2C_BASE3		(OMAP44XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4		(OMAP44XX_L4_PER_BASE + 0x350000)
+
+/* MUSB base */
+#define MUSB_BASE		(OMAP44XX_L4_CORE_BASE + 0xAB000)
+
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0114
+#define OMAP_GPIO_IRQSTATUS1		0x0118
+#define OMAP_GPIO_IRQSTATUS2		0x0128
+#define OMAP_GPIO_IRQENABLE2		0x012c
+#define OMAP_GPIO_IRQENABLE1		0x011c
+#define OMAP_GPIO_WAKE_EN		0x0120
+#define OMAP_GPIO_CTRL			0x0130
+#define OMAP_GPIO_OE			0x0134
+#define OMAP_GPIO_DATAIN		0x0138
+#define OMAP_GPIO_DATAOUT		0x013c
+#define OMAP_GPIO_LEVELDETECT0		0x0140
+#define OMAP_GPIO_LEVELDETECT1		0x0144
+#define OMAP_GPIO_RISINGDETECT		0x0148
+#define OMAP_GPIO_FALLINGDETECT		0x014c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0160
+#define OMAP_GPIO_SETIRQENABLE1		0x0164
+#define OMAP_GPIO_CLEARWKUENA		0x0180
+#define OMAP_GPIO_SETWKUENA		0x0184
+#define OMAP_GPIO_CLEARDATAOUT		0x0190
+#define OMAP_GPIO_SETDATAOUT		0x0194
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE		0x4A306000
+#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL		PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET	0x01
+#define PRM_RSTST		(PRM_DEVICE_BASE + 0x4)
+#define PRM_RSTST_WARM_RESET_MASK	0x07EA
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap4/ehci.h b/arch/arm/include/asm/arch-omap4/ehci.h
new file mode 100644
index 0000000..30bdaad
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/ehci.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * OMAP EHCI port support
+ * Based on LINUX KERNEL
+ * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Govindraj R <govindraj.raja@ti.com>
+ */
+
+#ifndef _OMAP4_EHCI_H_
+#define _OMAP4_EHCI_H_
+
+#define OMAP_EHCI_BASE				(OMAP44XX_L4_CORE_BASE + 0x64C00)
+#define OMAP_UHH_BASE				(OMAP44XX_L4_CORE_BASE + 0x64000)
+#define OMAP_USBTLL_BASE			(OMAP44XX_L4_CORE_BASE + 0x62000)
+
+/* UHH, TLL and opt clocks */
+#define CM_L3INIT_HSUSBHOST_CLKCTRL		0x4A009358UL
+
+#define HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK	(1 << 24)
+
+/* TLL Register Set */
+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE		(1 << 3)
+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP		(1 << 2)
+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET		(1 << 1)
+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY		(1 << 8)
+#define OMAP_USBTLL_SYSSTATUS_RESETDONE		1
+
+#define OMAP_UHH_SYSCONFIG_SOFTRESET		1
+#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE	(1 << 2)
+#define OMAP_UHH_SYSCONFIG_NOIDLE		(1 << 2)
+#define OMAP_UHH_SYSCONFIG_NOSTDBY		(1 << 4)
+
+#define OMAP_UHH_SYSCONFIG_VAL	(OMAP_UHH_SYSCONFIG_NOIDLE | \
+					OMAP_UHH_SYSCONFIG_NOSTDBY)
+
+#endif /* _OMAP4_EHCI_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/gpio.h b/arch/arm/include/asm/arch-omap4/gpio.h
new file mode 100644
index 0000000..aceb3e2
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/gpio.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+#ifndef _GPIO_OMAP4_H
+#define _GPIO_OMAP4_H
+
+#include <asm/omap_gpio.h>
+
+#define OMAP_MAX_GPIO			192
+
+#define OMAP44XX_GPIO1_BASE		0x4A310000
+#define OMAP44XX_GPIO2_BASE		0x48055000
+#define OMAP44XX_GPIO3_BASE		0x48057000
+#define OMAP44XX_GPIO4_BASE		0x48059000
+#define OMAP44XX_GPIO5_BASE		0x4805B000
+#define OMAP44XX_GPIO6_BASE		0x4805D000
+
+#endif /* _GPIO_OMAP4_H */
diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h
new file mode 100644
index 0000000..48dc809
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/hardware.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * hardware.h
+ *
+ * hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef __OMAP_HARDWARE_H
+#define __OMAP_HARDWARE_H
+
+#include <asm/arch/omap.h>
+
+/*
+ * Common hardware definitions
+ */
+
+/* BCH Error Location Module */
+#define ELM_BASE			0x48078000
+
+/* GPMC Base address */
+#define GPMC_BASE			0x50000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h
new file mode 100644
index 0000000..c8f2f97
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/i2c.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef _OMAP4_I2C_H_
+#define _OMAP4_I2C_H_
+
+#define I2C_DEFAULT_BASE	I2C_BASE1
+
+#endif /* _OMAP4_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/mem.h b/arch/arm/include/asm/arch-omap4/mem.h
new file mode 100644
index 0000000..3026a00
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/mem.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ *		Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *		Richard Woodruff <r-woodruff2@ti.com>
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * M_NAND - Micron NAND
+ * STNOR - STMicrolelctronics M29W128GL
+ */
+#define GPMC_SIZE_256M		0x0
+#define GPMC_SIZE_128M		0x8
+#define GPMC_SIZE_64M		0xC
+#define GPMC_SIZE_32M		0xE
+#define GPMC_SIZE_16M		0xF
+
+#define M_NAND_GPMC_CONFIG1	0x00000800
+#define M_NAND_GPMC_CONFIG2	0x001e1e00
+#define M_NAND_GPMC_CONFIG3	0x001e1e00
+#define M_NAND_GPMC_CONFIG4	0x16051807
+#define M_NAND_GPMC_CONFIG5	0x00151e1e
+#define M_NAND_GPMC_CONFIG6	0x16000f80
+#define M_NAND_GPMC_CONFIG7	0x00000008
+
+#define STNOR_GPMC_CONFIG1	0x00001200
+#define STNOR_GPMC_CONFIG2	0x00101000
+#define STNOR_GPMC_CONFIG3	0x00030301
+#define STNOR_GPMC_CONFIG4	0x10041004
+#define STNOR_GPMC_CONFIG5	0x000C1010
+#define STNOR_GPMC_CONFIG6	0x08070280
+#define STNOR_GPMC_CONFIG7	0x00000F48
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS		8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG		7
+
+#endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
new file mode 100644
index 0000000..d067799
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+#include <asm/omap_mmc.h>
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE	0x4809C000
+#define OMAP_HSMMC2_BASE	0x480B4000
+#define OMAP_HSMMC3_BASE	0x480AD000
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap4/mux_omap4.h b/arch/arm/include/asm/arch-omap4/mux_omap4.h
new file mode 100644
index 0000000..854203c
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/mux_omap4.h
@@ -0,0 +1,328 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated
+ * Richard Woodruff		<r-woodruff2@ti.com>
+ * Aneesh V			<aneesh@ti.com>
+ * Balaji Krishnamoorthy	<balajitk@ti.com>
+ */
+#ifndef _MUX_OMAP4_H_
+#define _MUX_OMAP4_H_
+
+#include <asm/types.h>
+
+struct pad_conf_entry {
+
+	u16 offset;
+
+	u16 val;
+
+};
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_PD          (1 << 12)
+#define OFF_PU          (3 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (2 << 10)
+#define OFF_IN          (1 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (1 << 9)
+#else
+#define OFF_PD          (0 << 12)
+#define OFF_PU          (0 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (0 << 10)
+#define OFF_IN          (0 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (0 << 9)
+#endif
+
+#define IEN             (1 << 8)
+#define IDIS            (0 << 8)
+#define PTU             (3 << 3)
+#define PTD             (1 << 3)
+#define EN              (1 << 3)
+#define DIS             (0 << 3)
+
+#define M0              0
+#define M1              1
+#define M2              2
+#define M3              3
+#define M4              4
+#define M5              5
+#define M6              6
+#define M7              7
+
+#define SAFE_MODE	M7
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
+#define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
+#define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
+#define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
+#else
+#define OFF_IN_PD       0
+#define OFF_IN_PU       0
+#define OFF_OUT_PD      0
+#define OFF_OUT_PU      0
+#endif
+
+#define CORE_REVISION		0x0000
+#define CORE_HWINFO		0x0004
+#define CORE_SYSCONFIG		0x0010
+#define GPMC_AD0		0x0040
+#define GPMC_AD1		0x0042
+#define GPMC_AD2		0x0044
+#define GPMC_AD3		0x0046
+#define GPMC_AD4		0x0048
+#define GPMC_AD5		0x004A
+#define GPMC_AD6		0x004C
+#define GPMC_AD7		0x004E
+#define GPMC_AD8		0x0050
+#define GPMC_AD9		0x0052
+#define GPMC_AD10		0x0054
+#define GPMC_AD11		0x0056
+#define GPMC_AD12		0x0058
+#define GPMC_AD13		0x005A
+#define GPMC_AD14		0x005C
+#define GPMC_AD15		0x005E
+#define GPMC_A16		0x0060
+#define GPMC_A17		0x0062
+#define GPMC_A18		0x0064
+#define GPMC_A19		0x0066
+#define GPMC_A20		0x0068
+#define GPMC_A21		0x006A
+#define GPMC_A22		0x006C
+#define GPMC_A23		0x006E
+#define GPMC_A24		0x0070
+#define GPMC_A25		0x0072
+#define GPMC_NCS0		0x0074
+#define GPMC_NCS1		0x0076
+#define GPMC_NCS2		0x0078
+#define GPMC_NCS3		0x007A
+#define GPMC_NWP		0x007C
+#define GPMC_CLK		0x007E
+#define GPMC_NADV_ALE		0x0080
+#define GPMC_NOE		0x0082
+#define GPMC_NWE		0x0084
+#define GPMC_NBE0_CLE		0x0086
+#define GPMC_NBE1		0x0088
+#define GPMC_WAIT0		0x008A
+#define GPMC_WAIT1		0x008C
+#define C2C_DATA11		0x008E
+#define C2C_DATA12		0x0090
+#define C2C_DATA13		0x0092
+#define C2C_DATA14		0x0094
+#define C2C_DATA15		0x0096
+#define HDMI_HPD		0x0098
+#define HDMI_CEC		0x009A
+#define HDMI_DDC_SCL		0x009C
+#define HDMI_DDC_SDA		0x009E
+#define CSI21_DX0		0x00A0
+#define CSI21_DY0		0x00A2
+#define CSI21_DX1		0x00A4
+#define CSI21_DY1		0x00A6
+#define CSI21_DX2		0x00A8
+#define CSI21_DY2		0x00AA
+#define CSI21_DX3		0x00AC
+#define CSI21_DY3		0x00AE
+#define CSI21_DX4		0x00B0
+#define CSI21_DY4		0x00B2
+#define CSI22_DX0		0x00B4
+#define CSI22_DY0		0x00B6
+#define CSI22_DX1		0x00B8
+#define CSI22_DY1		0x00BA
+#define CAM_SHUTTER		0x00BC
+#define CAM_STROBE		0x00BE
+#define CAM_GLOBALRESET		0x00C0
+#define USBB1_ULPITLL_CLK	0x00C2
+#define USBB1_ULPITLL_STP	0x00C4
+#define USBB1_ULPITLL_DIR	0x00C6
+#define USBB1_ULPITLL_NXT	0x00C8
+#define USBB1_ULPITLL_DAT0	0x00CA
+#define USBB1_ULPITLL_DAT1	0x00CC
+#define USBB1_ULPITLL_DAT2	0x00CE
+#define USBB1_ULPITLL_DAT3	0x00D0
+#define USBB1_ULPITLL_DAT4	0x00D2
+#define USBB1_ULPITLL_DAT5	0x00D4
+#define USBB1_ULPITLL_DAT6	0x00D6
+#define USBB1_ULPITLL_DAT7	0x00D8
+#define USBB1_HSIC_DATA		0x00DA
+#define USBB1_HSIC_STROBE	0x00DC
+#define USBC1_ICUSB_DP		0x00DE
+#define USBC1_ICUSB_DM		0x00E0
+#define SDMMC1_CLK		0x00E2
+#define SDMMC1_CMD		0x00E4
+#define SDMMC1_DAT0		0x00E6
+#define SDMMC1_DAT1		0x00E8
+#define SDMMC1_DAT2		0x00EA
+#define SDMMC1_DAT3		0x00EC
+#define SDMMC1_DAT4		0x00EE
+#define SDMMC1_DAT5		0x00F0
+#define SDMMC1_DAT6		0x00F2
+#define SDMMC1_DAT7		0x00F4
+#define ABE_MCBSP2_CLKX		0x00F6
+#define ABE_MCBSP2_DR		0x00F8
+#define ABE_MCBSP2_DX		0x00FA
+#define ABE_MCBSP2_FSX		0x00FC
+#define ABE_MCBSP1_CLKX		0x00FE
+#define ABE_MCBSP1_DR		0x0100
+#define ABE_MCBSP1_DX		0x0102
+#define ABE_MCBSP1_FSX		0x0104
+#define ABE_PDM_UL_DATA		0x0106
+#define ABE_PDM_DL_DATA		0x0108
+#define ABE_PDM_FRAME		0x010A
+#define ABE_PDM_LB_CLK		0x010C
+#define ABE_CLKS		0x010E
+#define ABE_DMIC_CLK1		0x0110
+#define ABE_DMIC_DIN1		0x0112
+#define ABE_DMIC_DIN2		0x0114
+#define ABE_DMIC_DIN3		0x0116
+#define UART2_CTS		0x0118
+#define UART2_RTS		0x011A
+#define UART2_RX		0x011C
+#define UART2_TX		0x011E
+#define HDQ_SIO			0x0120
+#define I2C1_SCL		0x0122
+#define I2C1_SDA		0x0124
+#define I2C2_SCL		0x0126
+#define I2C2_SDA		0x0128
+#define I2C3_SCL		0x012A
+#define I2C3_SDA		0x012C
+#define I2C4_SCL		0x012E
+#define I2C4_SDA		0x0130
+#define MCSPI1_CLK		0x0132
+#define MCSPI1_SOMI		0x0134
+#define MCSPI1_SIMO		0x0136
+#define MCSPI1_CS0		0x0138
+#define MCSPI1_CS1		0x013A
+#define MCSPI1_CS2		0x013C
+#define MCSPI1_CS3		0x013E
+#define UART3_CTS_RCTX		0x0140
+#define UART3_RTS_SD		0x0142
+#define UART3_RX_IRRX		0x0144
+#define UART3_TX_IRTX		0x0146
+#define SDMMC5_CLK		0x0148
+#define SDMMC5_CMD		0x014A
+#define SDMMC5_DAT0		0x014C
+#define SDMMC5_DAT1		0x014E
+#define SDMMC5_DAT2		0x0150
+#define SDMMC5_DAT3		0x0152
+#define MCSPI4_CLK		0x0154
+#define MCSPI4_SIMO		0x0156
+#define MCSPI4_SOMI		0x0158
+#define MCSPI4_CS0		0x015A
+#define UART4_RX		0x015C
+#define UART4_TX		0x015E
+#define USBB2_ULPITLL_CLK	0x0160
+#define USBB2_ULPITLL_STP	0x0162
+#define USBB2_ULPITLL_DIR	0x0164
+#define USBB2_ULPITLL_NXT	0x0166
+#define USBB2_ULPITLL_DAT0	0x0168
+#define USBB2_ULPITLL_DAT1	0x016A
+#define USBB2_ULPITLL_DAT2	0x016C
+#define USBB2_ULPITLL_DAT3	0x016E
+#define USBB2_ULPITLL_DAT4	0x0170
+#define USBB2_ULPITLL_DAT5	0x0172
+#define USBB2_ULPITLL_DAT6	0x0174
+#define USBB2_ULPITLL_DAT7	0x0176
+#define USBB2_HSIC_DATA		0x0178
+#define USBB2_HSIC_STROBE	0x017A
+#define UNIPRO_TX0		0x017C
+#define UNIPRO_TY0		0x017E
+#define UNIPRO_TX1		0x0180
+#define UNIPRO_TY1		0x0182
+#define UNIPRO_TX2		0x0184
+#define UNIPRO_TY2		0x0186
+#define UNIPRO_RX0		0x0188
+#define UNIPRO_RY0		0x018A
+#define UNIPRO_RX1		0x018C
+#define UNIPRO_RY1		0x018E
+#define UNIPRO_RX2		0x0190
+#define UNIPRO_RY2		0x0192
+#define USBA0_OTG_CE		0x0194
+#define USBA0_OTG_DP		0x0196
+#define USBA0_OTG_DM		0x0198
+#define FREF_CLK1_OUT		0x019A
+#define FREF_CLK2_OUT		0x019C
+#define SYS_NIRQ1		0x019E
+#define SYS_NIRQ2		0x01A0
+#define SYS_BOOT0		0x01A2
+#define SYS_BOOT1		0x01A4
+#define SYS_BOOT2		0x01A6
+#define SYS_BOOT3		0x01A8
+#define SYS_BOOT4		0x01AA
+#define SYS_BOOT5		0x01AC
+#define DPM_EMU0		0x01AE
+#define DPM_EMU1		0x01B0
+#define DPM_EMU2		0x01B2
+#define DPM_EMU3		0x01B4
+#define DPM_EMU4		0x01B6
+#define DPM_EMU5		0x01B8
+#define DPM_EMU6		0x01BA
+#define DPM_EMU7		0x01BC
+#define DPM_EMU8		0x01BE
+#define DPM_EMU9		0x01C0
+#define DPM_EMU10		0x01C2
+#define DPM_EMU11		0x01C4
+#define DPM_EMU12		0x01C6
+#define DPM_EMU13		0x01C8
+#define DPM_EMU14		0x01CA
+#define DPM_EMU15		0x01CC
+#define DPM_EMU16		0x01CE
+#define DPM_EMU17		0x01D0
+#define DPM_EMU18		0x01D2
+#define DPM_EMU19		0x01D4
+#define WAKEUPEVENT_0		0x01D8
+#define WAKEUPEVENT_1		0x01DC
+#define WAKEUPEVENT_2		0x01E0
+#define WAKEUPEVENT_3		0x01E4
+#define WAKEUPEVENT_4		0x01E8
+#define WAKEUPEVENT_5		0x01EC
+#define WAKEUPEVENT_6		0x01F0
+
+#define WKUP_REVISION		0x0000
+#define WKUP_HWINFO		0x0004
+#define WKUP_SYSCONFIG		0x0010
+#define PAD0_SIM_IO		0x0040
+#define PAD1_SIM_CLK		0x0042
+#define PAD0_SIM_RESET		0x0044
+#define PAD1_SIM_CD		0x0046
+#define PAD0_SIM_PWRCTRL		0x0048
+#define PAD1_SR_SCL		0x004A
+#define PAD0_SR_SDA		0x004C
+#define PAD1_FREF_XTAL_IN		0x004E
+#define PAD0_FREF_SLICER_IN	0x0050
+#define PAD1_FREF_CLK_IOREQ	0x0052
+#define PAD0_FREF_CLK0_OUT		0x0054
+#define PAD1_FREF_CLK3_REQ		0x0056
+#define PAD0_FREF_CLK3_OUT		0x0058
+#define PAD1_FREF_CLK4_REQ		0x005A
+#define PAD0_FREF_CLK4_OUT		0x005C
+#define PAD1_SYS_32K		0x005E
+#define PAD0_SYS_NRESPWRON		0x0060
+#define PAD1_SYS_NRESWARM		0x0062
+#define PAD0_SYS_PWR_REQ		0x0064
+#define PAD1_SYS_PWRON_RESET	0x0066
+#define PAD0_SYS_BOOT6		0x0068
+#define PAD1_SYS_BOOT7		0x006A
+#define PAD0_JTAG_NTRST		0x006C
+#define PAD1_JTAG_TCK		0x006D
+#define PAD0_JTAG_RTCK		0x0070
+#define PAD1_JTAG_TMS_TMSC		0x0072
+#define PAD0_JTAG_TDI		0x0074
+#define PAD1_JTAG_TDO		0x0076
+#define PADCONF_WAKEUPEVENT_0	0x007C
+#define CONTROL_SMART1NOPMIO_PADCONF_0		0x05A0
+#define CONTROL_SMART1NOPMIO_PADCONF_1		0x05A4
+#define PADCONF_MODE		0x05A8
+#define CONTROL_XTAL_OSCILLATOR			0x05AC
+#define CONTROL_CONTROL_I2C_2			0x0604
+#define CONTROL_CONTROL_JTAG			0x0608
+#define CONTROL_CONTROL_SYS			0x060C
+#define CONTROL_SPARE_RW		0x0614
+#define CONTROL_SPARE_R		0x0618
+#define CONTROL_SPARE_R_C0		0x061C
+
+#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ	0x4A31E05A
+#endif /* _MUX_OMAP4_H_ */
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
new file mode 100644
index 0000000..8919088
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Authors:
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * Derived from OMAP3 work by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <x0khasim@ti.com>
+ */
+
+#ifndef _OMAP4_H_
+#define _OMAP4_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#include <linux/sizes.h>
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP44XX_L4_CORE_BASE	0x4A000000
+#define OMAP44XX_L4_WKUP_BASE	0x4A300000
+#define OMAP44XX_L4_PER_BASE	0x48000000
+
+#define OMAP44XX_DRAM_ADDR_SPACE_START	0x80000000
+#define OMAP44XX_DRAM_ADDR_SPACE_END	0xD0000000
+#define DRAM_ADDR_SPACE_START	OMAP44XX_DRAM_ADDR_SPACE_START
+#define DRAM_ADDR_SPACE_END	OMAP44XX_DRAM_ADDR_SPACE_END
+
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE		0x4A002204
+
+#define OMAP4_CONTROL_ID_CODE_ES1_0	0x0B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_0	0x1B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_1	0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2	0x4B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_3	0x6B95C02F
+#define OMAP4460_CONTROL_ID_CODE_ES1_0	0x0B94E02F
+#define OMAP4460_CONTROL_ID_CODE_ES1_1	0x2B94E02F
+#define OMAP4470_CONTROL_ID_CODE_ES1_0	0x0B97502F
+
+/* UART */
+#define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
+#define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)
+#define UART3_BASE		(OMAP44XX_L4_PER_BASE + 0x20000)
+
+/* General Purpose Timers */
+#define GPT1_BASE		(OMAP44XX_L4_WKUP_BASE + 0x18000)
+#define GPT2_BASE		(OMAP44XX_L4_PER_BASE  + 0x32000)
+#define GPT3_BASE		(OMAP44XX_L4_PER_BASE  + 0x34000)
+
+/* Watchdog Timer2 - MPU watchdog */
+#define WDT2_BASE		(OMAP44XX_L4_WKUP_BASE + 0x14000)
+
+/*
+ * Hardware Register Details
+ */
+
+/* Watchdog Timer */
+#define WD_UNLOCK1		0xAAAA
+#define WD_UNLOCK2		0x5555
+
+/* GP Timer */
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
+
+/* Control Module */
+#define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
+#define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f
+#define CONTROL_EFUSE_1_OVERRIDE	0x1C4D0110
+#define CONTROL_EFUSE_2_OVERRIDE	0x99084000
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
+#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN	0x7C7C7C7C
+#define LPDDR2IO_GR10_WD_MASK				(3 << 17)
+#define CONTROL_LPDDR2IO_3_VAL		0xA0888C0F
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
+
+#define MMC1_PWRDNZ					(1 << 26)
+#define MMC1_PBIASLITE_PWRDNZ				(1 << 22)
+#define MMC1_PBIASLITE_VMODE				(1 << 21)
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+	unsigned char res[0x10];
+	unsigned int s32k_cr;	/* 0x10 */
+};
+
+#define DEVICE_TYPE_SHIFT (0x8)
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Non-secure SRAM Addresses
+ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
+ * at 0x40304000(EMU base) so that our code works for both EMU and GP
+ */
+#define NON_SECURE_SRAM_START	0x40304000
+#define NON_SECURE_SRAM_END	0x4030E000	/* Not inclusive */
+#define NON_SECURE_SRAM_IMG_END	0x4030C000
+#define SRAM_SCRATCH_SPACE_ADDR	(NON_SECURE_SRAM_IMG_END - SZ_1K)
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_ROM_VECT_BASE	0x4030D000
+
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME		50
+#define OMAP_ABB_CLOCK_CYCLES		16
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK	(0x1 << 7)
+
+#define OMAP44XX_SAR_RAM_BASE		0x4a326000
+#define OMAP_REBOOT_REASON_OFFSET	0xA0C
+#define OMAP_REBOOT_REASON_SIZE		0x0F
+
+/* Boot parameters */
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+	unsigned int boot_message;
+	unsigned int boot_device_descriptor;
+	unsigned char boot_device;
+	unsigned char reset_reason;
+	unsigned char ch_flags;
+};
+
+int omap_reboot_mode(char *mode, unsigned int length);
+int omap_reboot_mode_clear(void);
+int omap_reboot_mode_store(char *mode);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h
new file mode 100644
index 0000000..d24944a
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/spl.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NONE	0x00
+#define BOOT_DEVICE_XIP		0x01
+#define BOOT_DEVICE_XIPWAIT	0x02
+#define BOOT_DEVICE_NAND	0x03
+#define BOOT_DEVICE_ONENAND	0x04
+#define BOOT_DEVICE_MMC1	0x05
+#define BOOT_DEVICE_MMC2	0x06
+#define BOOT_DEVICE_MMC2_2	0x07
+#define BOOT_DEVICE_UART	0x43
+#define BOOT_DEVICE_USB		0x45
+
+#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2_2
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
new file mode 100644
index 0000000..b2a6887
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/arch/omap.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/omap_common.h>
+#include <linux/mtd/omap_gpmc.h>
+#include <asm/arch/mux_omap4.h>
+#include <asm/ti-common/sys_proto.h>
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
+extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
+extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
+extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
+extern const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2;
+extern const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2;
+extern const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2;
+#else
+extern const struct lpddr2_device_details elpida_2G_S4_details;
+extern const struct lpddr2_device_details elpida_4G_S4_details;
+#endif
+
+#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+extern const struct lpddr2_device_timings jedec_default_timings;
+#else
+extern const struct lpddr2_device_timings elpida_2G_S4_timings;
+#endif
+
+struct omap_sysinfo {
+	char *board_string;
+};
+extern const struct omap_sysinfo sysinfo;
+
+void gpmc_init(void);
+void watchdog_init(void);
+u32 get_device_type(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs(void);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
+void setup_early_clocks(void);
+void prcm_init(void);
+void do_board_detect(void);
+void bypass_dpll(u32 const base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap4_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
+void sdram_init(void);
+u32 omap_sdram_size(void);
+u32 cortex_rev(void);
+void save_omap_boot_params(void);
+void init_omap_revision(void);
+void do_io_settings(void);
+void sri2c_init(void);
+int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
+u32 warm_reset(void);
+void force_emif_self_refresh(void);
+void setup_warmreset_time(void);
+
+#define OMAP4_SERVICE_PL310_CONTROL_REG_SET	0x102
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
new file mode 100644
index 0000000..e261bd4
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -0,0 +1,417 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ *	Aneesh V <aneesh@ti.com>
+ *	Sricharan R <r.sricharan@ti.com>
+ */
+#ifndef _CLOCKS_OMAP5_H_
+#define _CLOCKS_OMAP5_H_
+#include <common.h>
+#include <asm/omap_common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY		1000000
+
+/* CM_DLL_CTRL */
+#define CM_DLL_CTRL_OVERRIDE_SHIFT		0
+#define CM_DLL_CTRL_OVERRIDE_MASK		(1 << 0)
+#define CM_DLL_CTRL_NO_OVERRIDE			0
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK		(1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT	9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK	(1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT	8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK	(1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT		5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK		(0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_EN_MASK			(0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT		0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK		7
+
+#define DPLL_EN_STOP			1
+#define DPLL_EN_MN_BYPASS		4
+#define DPLL_EN_LOW_POWER_BYPASS	5
+#define DPLL_EN_FAST_RELOCK_BYPASS	6
+#define DPLL_EN_LOCK			7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK		1
+
+/* SGX */
+#define CLKSEL_GPU_HYD_GCLK_MASK		(1 << 25)
+#define CLKSEL_GPU_CORE_GCLK_MASK		(1 << 24)
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT			8
+#define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT			0
+#define CM_CLKSEL_DPLL_N_MASK			0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT			22
+#define CM_CLKSEL_DCC_EN_MASK			(1 << 22)
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT	0
+#define CLKSEL_L3_SHIFT		4
+#define CLKSEL_L4_SHIFT		8
+
+#define CLKSEL_CORE_X2_DIV_1	0
+#define CLKSEL_L3_CORE_DIV_2	1
+#define CLKSEL_L4_L3_DIV_2	1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK	1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK	0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK	1
+
+/* CM_CLKSEL_ABE_PLL_SYS */
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT	0
+#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK	1
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1		0
+#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2		1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT		0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK		3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2		1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK	1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK	4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK	8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT	8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK	(7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT	11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK		(0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT		0
+#define CD_CLKCTRL_CLKTRCTRL_MASK		3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP		0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP		1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP		2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO		3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT		0
+#define MODULE_CLKCTRL_MODULEMODE_MASK		3
+#define MODULE_CLKCTRL_IDLEST_SHIFT		16
+#define MODULE_CLKCTRL_IDLEST_MASK		(3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE		0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO		1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN	2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL	0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING	1
+#define MODULE_CLKCTRL_IDLEST_IDLE		2
+#define MODULE_CLKCTRL_IDLEST_DISABLED		3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(3 << 25)
+
+/* CM_L3INIT_SATA_CLKCTRL */
+#define SATA_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK		0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
+
+/* CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OPTFCLKEN_FUNC48M_CLK			(1 << 15)
+#define OPTFCLKEN_HSIC480M_P2_CLK		(1 << 14)
+#define OPTFCLKEN_HSIC480M_P1_CLK		(1 << 13)
+#define OPTFCLKEN_HSIC60M_P2_CLK		(1 << 12)
+#define OPTFCLKEN_HSIC60M_P1_CLK		(1 << 11)
+#define OPTFCLKEN_UTMI_P3_CLK			(1 << 10)
+#define OPTFCLKEN_UTMI_P2_CLK			(1 << 9)
+#define OPTFCLKEN_UTMI_P1_CLK			(1 << 8)
+#define OPTFCLKEN_HSIC480M_P3_CLK		(1 << 7)
+#define OPTFCLKEN_HSIC60M_P3_CLK		(1 << 6)
+
+/* CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OPTFCLKEN_USB_CH0_CLK_ENABLE	(1 << 8)
+#define OPTFCLKEN_USB_CH1_CLK_ENABLE	(1 << 9)
+#define OPTFCLKEN_USB_CH2_CLK_ENABLE	(1 << 10)
+
+/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K	(1 << 8)
+
+/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */
+#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK	(1 << 8)
+
+/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
+#define OTG_SS_CLKCTRL_MODULEMODE_HW	(1 << 0)
+#define OPTFCLKEN_REFCLK960M			(1 << 8)
+
+/* CM_L3INIT_OCP2SCP1_CLKCTRL */
+#define OCP2SCP1_CLKCTRL_MODULEMODE_HW	(1 << 0)
+
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(3 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	26
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 26)
+
+/* CM_WKUPAON_SCRM_CLKCTRL */
+#define OPTFCLKEN_SCRM_PER_SHIFT		9
+#define OPTFCLKEN_SCRM_PER_MASK			(1 << 9)
+#define OPTFCLKEN_SCRM_CORE_SHIFT		8
+#define OPTFCLKEN_SCRM_CORE_MASK		(1 << 8)
+
+/* CM_COREAON_IO_SRCOMP_CLKCTRL */
+#define OPTFCLKEN_SRCOMP_FCLK_SHIFT		8
+#define OPTFCLKEN_SRCOMP_FCLK_MASK		(1 << 8)
+
+/* PRM_RSTTIME */
+#define RSTTIME1_SHIFT				0
+#define RSTTIME1_MASK				(0x3ff << 0)
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_IND_38_4_MHZ	6
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
+
+/* CTRL_CORE_SRCOMP_NORTH_SIDE */
+#define USB2PHY_DISCHGDET	(1 << 29)
+#define USB2PHY_AUTORESUME_EN (1 << 30)
+
+/* SMPS */
+#define SMPS_I2C_SLAVE_ADDR	0x12
+#define SMPS_REG_ADDR_12_MPU	0x23
+#define SMPS_REG_ADDR_45_IVA	0x2B
+#define SMPS_REG_ADDR_8_CORE	0x37
+
+/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
+/* ES1.0 settings */
+#define VDD_MPU		1040
+#define VDD_MM		1040
+#define VDD_CORE	1040
+
+#define VDD_MPU_LOW	890
+#define VDD_MM_LOW	890
+#define VDD_CORE_LOW	890
+
+/* ES2.0 settings */
+#define VDD_MPU_ES2	1060
+#define VDD_MM_ES2	1025
+#define VDD_CORE_ES2	1040
+
+#define VDD_MPU_ES2_HIGH 1250
+#define VDD_MM_ES2_OD  1120
+
+/* Efuse register offsets for OMAP5 platform */
+#define OMAP5_ES2_EFUSE_BASE	0x4A002000
+#define OMAP5_ES2_PROD_REGBITS	16
+
+/* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */
+#define OMAP5_ES2_PROD_CORE_OPNO_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1D8)
+
+/* CONTROL_STD_FUSE_OPP_VDD_MM_4 */
+#define OMAP5_ES2_PROD_MM_OPNO_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1A4)
+/* CONTROL_STD_FUSE_OPP_VDD_MM_5 */
+#define OMAP5_ES2_PROD_MM_OPOD_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1A8)
+/* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */
+#define OMAP5_ES2_PROD_MPU_OPNO_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1C4)
+/* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */
+#define OMAP5_ES2_PROD_MPU_OPHI_VMIN	(OMAP5_ES2_EFUSE_BASE + 0x1C8)
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA7_NOM	1150
+#define VDD_CORE_DRA7_NOM	1150
+#define VDD_EVE_DRA7_NOM	1060
+#define VDD_GPU_DRA7_NOM	1060
+#define VDD_IVA_DRA7_NOM	1060
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
+#define VDD_EVE_DRA7_OD		1150
+#define VDD_GPU_DRA7_OD		1150
+#define VDD_IVA_DRA7_OD		1150
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
+#define VDD_EVE_DRA7_HIGH	1250
+#define VDD_GPU_DRA7_HIGH	1250
+#define VDD_IVA_DRA7_HIGH	1250
+
+/* Efuse register offsets for DRA7xx platform */
+#define DRA752_EFUSE_BASE	0x4A002000
+#define DRA752_EFUSE_REGBITS	16
+/* STD_FUSE_OPP_VMIN_IVA_2 */
+#define STD_FUSE_OPP_VMIN_IVA_NOM	(DRA752_EFUSE_BASE + 0x05CC)
+/* STD_FUSE_OPP_VMIN_IVA_3 */
+#define STD_FUSE_OPP_VMIN_IVA_OD	(DRA752_EFUSE_BASE + 0x05D0)
+/* STD_FUSE_OPP_VMIN_IVA_4 */
+#define STD_FUSE_OPP_VMIN_IVA_HIGH	(DRA752_EFUSE_BASE + 0x05D4)
+/* STD_FUSE_OPP_VMIN_DSPEVE_2 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_NOM	(DRA752_EFUSE_BASE + 0x05E0)
+/* STD_FUSE_OPP_VMIN_DSPEVE_3 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_OD	(DRA752_EFUSE_BASE + 0x05E4)
+/* STD_FUSE_OPP_VMIN_DSPEVE_4 */
+#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH	(DRA752_EFUSE_BASE + 0x05E8)
+/* STD_FUSE_OPP_VMIN_CORE_2 */
+#define STD_FUSE_OPP_VMIN_CORE_NOM	(DRA752_EFUSE_BASE + 0x05F4)
+/* STD_FUSE_OPP_VMIN_GPU_2 */
+#define STD_FUSE_OPP_VMIN_GPU_NOM	(DRA752_EFUSE_BASE + 0x1B08)
+/* STD_FUSE_OPP_VMIN_GPU_3 */
+#define STD_FUSE_OPP_VMIN_GPU_OD	(DRA752_EFUSE_BASE + 0x1B0C)
+/* STD_FUSE_OPP_VMIN_GPU_4 */
+#define STD_FUSE_OPP_VMIN_GPU_HIGH	(DRA752_EFUSE_BASE + 0x1B10)
+/* STD_FUSE_OPP_VMIN_MPU_2 */
+#define STD_FUSE_OPP_VMIN_MPU_NOM	(DRA752_EFUSE_BASE + 0x1B20)
+/* STD_FUSE_OPP_VMIN_MPU_3 */
+#define STD_FUSE_OPP_VMIN_MPU_OD	(DRA752_EFUSE_BASE + 0x1B24)
+/* STD_FUSE_OPP_VMIN_MPU_4 */
+#define STD_FUSE_OPP_VMIN_MPU_HIGH	(DRA752_EFUSE_BASE + 0x1B28)
+
+#if defined(CONFIG_DRA7_MPU_OPP_HIGH)
+#define DRA7_MPU_OPP	OPP_HIGH
+#elif defined(CONFIG_DRA7_MPU_OPP_OD)
+#define DRA7_MPU_OPP	OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_MPU_OPP	OPP_NOM
+#endif
+
+/* OPP_NOM only available option for CORE */
+#define DRA7_CORE_OPP	OPP_NOM
+
+#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH)
+#define DRA7_DSPEVE_OPP	OPP_HIGH
+#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD)
+#define DRA7_DSPEVE_OPP	OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_DSPEVE_OPP	OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_IVA_OPP_HIGH)
+#define DRA7_IVA_OPP	OPP_HIGH
+#elif defined(CONFIG_DRA7_IVA_OPP_OD)
+#define DRA7_IVA_OPP	OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_IVA_OPP	OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_GPU_OPP_HIGH)
+#define DRA7_GPU_OPP	OPP_HIGH
+#elif defined(CONFIG_DRA7_GPU_OPP_OD)
+#define DRA7_GPU_OPP	OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_GPU_OPP	OPP_NOM
+#endif
+
+/* Standard offset is 0.5v expressed in uv */
+#define PALMAS_SMPS_BASE_VOLT_UV 500000
+
+/* Offset is 0.73V for LP873x */
+#define LP873X_BUCK_BASE_VOLT_UV		730000
+
+/* Offset is 0.73V for LP87565 */
+#define LP87565_BUCK_BASE_VOLT_UV		730000
+
+/* TPS659038 */
+#define TPS659038_I2C_SLAVE_ADDR		0x58
+#define TPS659038_REG_ADDR_SMPS12		0x23
+#define TPS659038_REG_ADDR_SMPS45		0x2B
+#define TPS659038_REG_ADDR_SMPS6		0x2F
+#define TPS659038_REG_ADDR_SMPS7		0x33
+#define TPS659038_REG_ADDR_SMPS8		0x37
+
+/* TPS65917 */
+#define TPS65917_I2C_SLAVE_ADDR		0x58
+#define TPS65917_REG_ADDR_SMPS1		0x23
+#define TPS65917_REG_ADDR_SMPS2		0x27
+#define TPS65917_REG_ADDR_SMPS3		0x2F
+#define TPS65917_REG_ADDR_SMPS4		0x33
+
+/* LP873X */
+#define LP873X_I2C_SLAVE_ADDR		0x60
+#define LP873X_REG_ADDR_BUCK0		0x6
+#define LP873X_REG_ADDR_BUCK1		0x7
+#define LP873X_REG_ADDR_LDO1		0xA
+
+/* LP87565 */
+#define LP87565_I2C_SLAVE_ADDR		0x61
+#define LP87565_REG_ADDR_BUCK01		0xA
+#define LP87565_REG_ADDR_BUCK23		0xE
+
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR		0x60
+#define TPS62361_REG_ADDR_SET0		0x0
+#define TPS62361_REG_ADDR_SET1		0x1
+#define TPS62361_REG_ADDR_SET2		0x2
+#define TPS62361_REG_ADDR_SET3		0x3
+#define TPS62361_REG_ADDR_CTRL		0x4
+#define TPS62361_REG_ADDR_TEMP		0x5
+#define TPS62361_REG_ADDR_RMP_CTRL	0x6
+#define TPS62361_REG_ADDR_CHIP_ID	0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2	0x9
+
+#define TPS62361_BASE_VOLT_MV	500
+#define TPS62361_VSEL0_GPIO	7
+
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0		0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ	1000
+
+#define DPLL_NO_LOCK	0
+#define DPLL_LOCK	1
+
+#if defined(CONFIG_DRA7XX)
+#define V_OSCK			20000000	/* Clock output from T2 */
+#else
+#define V_OSCK			19200000	/* Clock output from T2 */
+#endif
+
+#define V_SCLK	V_OSCK
+
+/* CKO buffer control */
+#define CKOBUFFER_CLK_ENABLE_MASK	(1 << 28)
+
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK		(1 << 8)
+#define AUXCLK_SRCSELECT_SHIFT		1
+#define AUXCLK_SRCSELECT_MASK		(3 << 1)
+#define AUXCLK_CLKDIV_SHIFT		16
+#define AUXCLK_CLKDIV_MASK		(0xF << 16)
+
+#define AUXCLK_SRCSELECT_SYS_CLK	0
+#define AUXCLK_SRCSELECT_CORE_DPLL	1
+#define AUXCLK_SRCSELECT_PER_DPLL	2
+#define AUXCLK_SRCSELECT_ALTERNATE	3
+
+#endif /* _CLOCKS_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
new file mode 100644
index 0000000..9e56553
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ *	Aneesh V <aneesh@ti.com>
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#include <asm/arch/hardware.h>
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+#include <asm/ti-common/omap_wdt.h>
+
+struct gptimer {
+	u32 tidr;		/* 0x00 r */
+	u8 res1[0xc];
+	u32 tiocp_cfg;		/* 0x10 rw */
+	u8 res2[0x10];
+	u32 tisr_raw;		/* 0x24 r */
+	u32 tisr;		/* 0x28 rw */
+	u32 tier;		/* 0x2c rw */
+	u32 ticr;		/* 0x30 rw */
+	u32 twer;		/* 0x34 rw */
+	u32 tclr;		/* 0x38 rw */
+	u32 tcrr;		/* 0x3c rw */
+	u32 tldr;		/* 0x40 rw */
+	u32 ttgr;		/* 0x44 rw */
+	u32 twpc;		/* 0x48 r */
+	u32 tmar;		/* 0x4c rw */
+	u32 tcar1;		/* 0x50 r */
+	u32 tcicr;		/* 0x54 rw */
+	u32 tcar2;		/* 0x58 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+#define WDT_BASE                (OMAP54XX_L4_WKUP_BASE + 0x14000)
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+	u8 res1[0x34];
+	u32 wwps;		/* 0x34 r */
+	u8 res2[0x10];
+	u32 wspr;		/* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1		0xAAAA
+#define WD_UNLOCK2		0x5555
+
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
+
+/* I2C base */
+#define I2C_BASE1		(OMAP54XX_L4_PER_BASE + 0x70000)
+#define I2C_BASE2		(OMAP54XX_L4_PER_BASE + 0x72000)
+#define I2C_BASE3		(OMAP54XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4		(OMAP54XX_L4_PER_BASE + 0x7A000)
+#define I2C_BASE5		(OMAP54XX_L4_PER_BASE + 0x7C000)
+
+/* MUSB base */
+#define MUSB_BASE		(OMAP54XX_L4_CORE_BASE + 0xAB000)
+
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0114
+#define OMAP_GPIO_IRQSTATUS1		0x0118
+#define OMAP_GPIO_IRQSTATUS2		0x0128
+#define OMAP_GPIO_IRQENABLE2		0x012c
+#define OMAP_GPIO_IRQENABLE1		0x011c
+#define OMAP_GPIO_WAKE_EN		0x0120
+#define OMAP_GPIO_CTRL			0x0130
+#define OMAP_GPIO_OE			0x0134
+#define OMAP_GPIO_DATAIN		0x0138
+#define OMAP_GPIO_DATAOUT		0x013c
+#define OMAP_GPIO_LEVELDETECT0		0x0140
+#define OMAP_GPIO_LEVELDETECT1		0x0144
+#define OMAP_GPIO_RISINGDETECT		0x0148
+#define OMAP_GPIO_FALLINGDETECT		0x014c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0160
+#define OMAP_GPIO_SETIRQENABLE1		0x0164
+#define OMAP_GPIO_CLEARWKUENA		0x0180
+#define OMAP_GPIO_SETWKUENA		0x0184
+#define OMAP_GPIO_CLEARDATAOUT		0x0190
+#define OMAP_GPIO_SETDATAOUT		0x0194
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE		0x4AE06000
+#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL		PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET	0x01
+#define PRM_RSTST		(PRM_DEVICE_BASE + 0x4)
+#define PRM_RSTST_WARM_RESET_MASK	0x7FEA
+
+/* DRA7XX CPSW Config space */
+#define CPSW_BASE			0x48484000
+#define CPSW_MDIO_BASE			0x48485000
+
+/* gmii_sel register defines */
+#define GMII1_SEL_MII		0x0
+#define GMII1_SEL_RMII		0x1
+#define GMII1_SEL_RGMII		0x2
+#define GMII2_SEL_MII		(GMII1_SEL_MII << 4)
+#define GMII2_SEL_RMII		(GMII1_SEL_RMII << 4)
+#define GMII2_SEL_RGMII		(GMII1_SEL_RGMII << 4)
+
+#define MII_MODE_ENABLE		(GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE	(GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
new file mode 100644
index 0000000..09edfad
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated
+ *
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#ifndef _DRA7_IODELAY_H_
+#define _DRA7_IODELAY_H_
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+
+/* CONFIG_REG_0 */
+#define CFG_REG_0_OFFSET		0xC
+#define CFG_REG_ROM_READ_SHIFT		1
+#define CFG_REG_ROM_READ_MASK		(1 << 1)
+#define CFG_REG_CALIB_STRT_SHIFT	0
+#define CFG_REG_CALIB_STRT_MASK		(1 << 0)
+#define CFG_REG_CALIB_STRT		1
+#define CFG_REG_CALIB_END		0
+#define CFG_REG_ROM_READ_START		(1 << 1)
+#define CFG_REG_ROM_READ_END		(0 << 1)
+
+/* CONFIG_REG_2 */
+#define CFG_REG_2_OFFSET		0x14
+#define CFG_REG_REFCLK_PERIOD_SHIFT	0
+#define CFG_REG_REFCLK_PERIOD_MASK	(0xFFFF << 0)
+#define CFG_REG_REFCLK_PERIOD		0x2EF
+
+/* CONFIG_REG_8 */
+#define CFG_REG_8_OFFSET		0x2C
+#define CFG_IODELAY_UNLOCK_KEY		0x0000AAAA
+#define CFG_IODELAY_LOCK_KEY		0x0000AAAB
+
+/* CONFIG_REG_3/4 */
+#define CFG_REG_3_OFFSET	0x18
+#define CFG_REG_4_OFFSET	0x1C
+#define CFG_REG_DLY_CNT_SHIFT	16
+#define CFG_REG_DLY_CNT_MASK	(0xFFFF << 16)
+#define CFG_REG_REF_CNT_SHIFT	0
+#define CFG_REG_REF_CNT_MASK	(0xFFFF << 0)
+
+/* CTRL_CORE_SMA_SW_0 */
+#define CTRL_ISOLATE_SHIFT		2
+#define CTRL_ISOLATE_MASK		(1 << 2)
+#define ISOLATE_IO			1
+#define DEISOLATE_IO			0
+
+/* CTRL_CORE_SMA_SW_1 */
+#define RGMII2_ID_MODE_N_MASK		(1 << 26)
+#define RGMII1_ID_MODE_N_MASK		(1 << 25)
+
+/* PRM_IO_PMCTRL */
+#define PMCTRL_ISOCLK_OVERRIDE_SHIFT	0
+#define PMCTRL_ISOCLK_OVERRIDE_MASK	(1 << 0)
+#define PMCTRL_ISOCLK_STATUS_SHIFT	1
+#define PMCTRL_ISOCLK_STATUS_MASK	(1 << 1)
+#define PMCTRL_ISOCLK_OVERRIDE_CTRL	1
+#define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL	0
+
+#define ERR_CALIBRATE_IODELAY		0x1
+#define ERR_DEISOLATE_IO		0x2
+#define ERR_ISOLATE_IO			0x4
+#define ERR_UPDATE_DELAY		0x8
+#define ERR_CPDE			0x3
+#define ERR_FPDE			0x5
+
+/* CFG_XXX */
+#define CFG_X_SIGNATURE_SHIFT		12
+#define CFG_X_SIGNATURE_MASK		(0x3F << 12)
+#define CFG_X_LOCK_SHIFT		10
+#define CFG_X_LOCK_MASK			(0x1 << 10)
+#define CFG_X_COARSE_DLY_SHIFT		5
+#define CFG_X_COARSE_DLY_MASK		(0x1F << 5)
+#define CFG_X_FINE_DLY_SHIFT		0
+#define CFG_X_FINE_DLY_MASK		(0x1F << 0)
+#define CFG_X_SIGNATURE			0x29
+#define CFG_X_LOCK			1
+
+void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+			   struct iodelay_cfg_entry const *iodelay,
+			   int niodelays);
+void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
+			      struct iodelay_cfg_entry const *iodelay,
+			      int niodelays);
+int __recalibrate_iodelay_start(void);
+void __recalibrate_iodelay_end(int ret);
+
+int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
+		   int niodelays);
+#endif
diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h
new file mode 100644
index 0000000..1790b92
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/ehci.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com*
+ * Author: Govindraj R <govindraj.raja@ti.com>
+ */
+
+#ifndef _EHCI_H
+#define _EHCI_H
+
+#define OMAP_EHCI_BASE				(OMAP54XX_L4_CORE_BASE + 0x64C00)
+#define OMAP_UHH_BASE				(OMAP54XX_L4_CORE_BASE + 0x64000)
+#define OMAP_USBTLL_BASE			(OMAP54XX_L4_CORE_BASE + 0x62000)
+
+/* TLL Register Set */
+#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE		(1 << 3)
+#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP		(1 << 2)
+#define OMAP_USBTLL_SYSCONFIG_SOFTRESET		(1 << 1)
+#define OMAP_USBTLL_SYSCONFIG_CACTIVITY		(1 << 8)
+#define OMAP_USBTLL_SYSSTATUS_RESETDONE		1
+
+#define OMAP_UHH_SYSCONFIG_SOFTRESET		1
+#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE	(1 << 2)
+#define OMAP_UHH_SYSCONFIG_NOIDLE		(1 << 2)
+#define OMAP_UHH_SYSCONFIG_NOSTDBY		(1 << 4)
+
+#define OMAP_UHH_SYSCONFIG_VAL	(OMAP_UHH_SYSCONFIG_NOIDLE | \
+					OMAP_UHH_SYSCONFIG_NOSTDBY)
+
+#endif /* _EHCI_H */
diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h
new file mode 100644
index 0000000..1e44fb5
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/gpio.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+#ifndef _GPIO_OMAP5_H
+#define _GPIO_OMAP5_H
+
+#include <asm/omap_gpio.h>
+
+#define OMAP_MAX_GPIO			256
+
+#define OMAP54XX_GPIO1_BASE		0x4Ae10000
+#define OMAP54XX_GPIO2_BASE		0x48055000
+#define OMAP54XX_GPIO3_BASE		0x48057000
+#define OMAP54XX_GPIO4_BASE		0x48059000
+#define OMAP54XX_GPIO5_BASE		0x4805B000
+#define OMAP54XX_GPIO6_BASE		0x4805D000
+#define OMAP54XX_GPIO7_BASE		0x48051000
+#define OMAP54XX_GPIO8_BASE		0x48053000
+
+
+/* Get the GPIO index from the given bank number and bank gpio */
+#define GPIO_TO_PIN(bank, bank_gpio)	(32 * (bank - 1) + (bank_gpio))
+
+#endif /* _GPIO_OMAP5_H */
diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h
new file mode 100644
index 0000000..b6d26e9
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/hardware.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * hardware.h
+ *
+ * hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef __OMAP_HARDWARE_H
+#define __OMAP_HARDWARE_H
+
+#include <asm/arch/omap.h>
+
+/*
+ * Common hardware definitions
+ */
+
+/* BCH Error Location Module */
+#define ELM_BASE			0x48078000
+
+/* GPMC Base address */
+#define GPMC_BASE			0x50000000
+
+/* EDMA3 Base address for DRA7XX and AM57XX */
+#if defined(CONFIG_DRA7XX)
+#define EDMA3_BASE			0x43300000
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h
new file mode 100644
index 0000000..9e1edcf
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/i2c.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef _OMAP5_I2C_H_
+#define _OMAP5_I2C_H_
+
+#define I2C_DEFAULT_BASE	I2C_BASE1
+
+#endif /* _OMAP5_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/mem.h b/arch/arm/include/asm/arch-omap5/mem.h
new file mode 100644
index 0000000..bd72fb6
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/mem.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ *		Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *		Richard Woodruff <r-woodruff2@ti.com>
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * M_NAND - Micron NAND
+ * STNOR - STMicrolelctronics M29W128GL
+ */
+#define GPMC_SIZE_256M		0x0
+#define GPMC_SIZE_128M		0x8
+#define GPMC_SIZE_64M		0xC
+#define GPMC_SIZE_32M		0xE
+#define GPMC_SIZE_16M		0xF
+
+#define M_NAND_GPMC_CONFIG1	0x00000800
+#define M_NAND_GPMC_CONFIG2	0x001e1e00
+#define M_NAND_GPMC_CONFIG3	0x001e1e00
+#define M_NAND_GPMC_CONFIG4	0x16051807
+#define M_NAND_GPMC_CONFIG5	0x00151e1e
+#define M_NAND_GPMC_CONFIG6	0x16000f80
+#define M_NAND_GPMC_CONFIG7	0x00000008
+
+#define STNOR_GPMC_CONFIG1	0x00001000
+#define STNOR_GPMC_CONFIG2	0x001f1f00
+#define STNOR_GPMC_CONFIG3	0x001f1f01
+#define STNOR_GPMC_CONFIG4	0x1f011f01
+#define STNOR_GPMC_CONFIG5	0x001d1f1f
+#define STNOR_GPMC_CONFIG6	0x08070280
+#define STNOR_GPMC_CONFIG7	0x00000048
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS		8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG		7
+
+#endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
new file mode 100644
index 0000000..d067799
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+#include <asm/omap_mmc.h>
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE	0x4809C000
+#define OMAP_HSMMC2_BASE	0x480B4000
+#define OMAP_HSMMC3_BASE	0x480AD000
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
new file mode 100644
index 0000000..c7c118e
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
@@ -0,0 +1,356 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated
+ *
+ * Nishant Kamat <nskamat@ti.com>
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ */
+#ifndef _MUX_DRA7XX_H_
+#define _MUX_DRA7XX_H_
+
+#include <asm/types.h>
+
+#define PULL_ENA		(0 << 16)
+#define PULL_DIS		(1 << 16)
+#define PULL_UP			(1 << 17)
+#define INPUT_EN		(1 << 18)
+#define SLEWCONTROL		(1 << 19)
+
+/* Active pin states */
+#define PIN_OUTPUT		(0 | PULL_DIS)
+#define PIN_OUTPUT_PULLUP	(PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(0)
+#define PIN_INPUT		(INPUT_EN | PULL_DIS)
+#define PIN_INPUT_SLEW		(INPUT_EN | SLEWCONTROL)
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
+#define M0	0
+#define M1	1
+#define M2	2
+#define M3	3
+#define M4	4
+#define M5	5
+#define M6	6
+#define M7	7
+#define M8	8
+#define M9	9
+#define M10	10
+#define M11	11
+#define M12	12
+#define M13	13
+#define M14	14
+#define M15	15
+
+#define MODE_SELECT		(1 << 8)
+#define DELAYMODE_SHIFT		4
+
+#define MANUAL_MODE	MODE_SELECT
+
+#define VIRTUAL_MODE0	(MODE_SELECT | (0x0 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE1	(MODE_SELECT | (0x1 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE2	(MODE_SELECT | (0x2 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE3	(MODE_SELECT | (0x3 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE4	(MODE_SELECT | (0x4 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE5	(MODE_SELECT | (0x5 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE6	(MODE_SELECT | (0x6 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE7	(MODE_SELECT | (0x7 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE8	(MODE_SELECT | (0x8 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE9	(MODE_SELECT | (0x9 << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE10	(MODE_SELECT | (0xa << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE11	(MODE_SELECT | (0xb << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE12	(MODE_SELECT | (0xc << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE13	(MODE_SELECT | (0xd << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE14	(MODE_SELECT | (0xe << DELAYMODE_SHIFT))
+#define VIRTUAL_MODE15	(MODE_SELECT | (0xf << DELAYMODE_SHIFT))
+
+#define SAFE_MODE	M15
+
+#define GPMC_AD0	0x000
+#define GPMC_AD1	0x004
+#define GPMC_AD2	0x008
+#define GPMC_AD3	0x00C
+#define GPMC_AD4	0x010
+#define GPMC_AD5	0x014
+#define GPMC_AD6	0x018
+#define GPMC_AD7	0x01C
+#define GPMC_AD8	0x020
+#define GPMC_AD9	0x024
+#define GPMC_AD10	0x028
+#define GPMC_AD11	0x02C
+#define GPMC_AD12	0x030
+#define GPMC_AD13	0x034
+#define GPMC_AD14	0x038
+#define GPMC_AD15	0x03C
+#define GPMC_A0		0x040
+#define GPMC_A1		0x044
+#define GPMC_A2		0x048
+#define GPMC_A3		0x04C
+#define GPMC_A4		0x050
+#define GPMC_A5		0x054
+#define GPMC_A6		0x058
+#define GPMC_A7		0x05C
+#define GPMC_A8		0x060
+#define GPMC_A9		0x064
+#define GPMC_A10	0x068
+#define GPMC_A11	0x06C
+#define GPMC_A12	0x070
+#define GPMC_A13	0x074
+#define GPMC_A14	0x078
+#define GPMC_A15	0x07C
+#define GPMC_A16	0x080
+#define GPMC_A17	0x084
+#define GPMC_A18	0x088
+#define GPMC_A19	0x08C
+#define GPMC_A20	0x090
+#define GPMC_A21	0x094
+#define GPMC_A22	0x098
+#define GPMC_A23	0x09C
+#define GPMC_A24	0x0A0
+#define GPMC_A25	0x0A4
+#define GPMC_A26	0x0A8
+#define GPMC_A27	0x0AC
+#define GPMC_CS1	0x0B0
+#define GPMC_CS0	0x0B4
+#define GPMC_CS2	0x0B8
+#define GPMC_CS3	0x0BC
+#define GPMC_CLK	0x0C0
+#define GPMC_ADVN_ALE	0x0C4
+#define GPMC_OEN_REN	0x0C8
+#define GPMC_WEN	0x0CC
+#define GPMC_BEN0	0x0D0
+#define GPMC_BEN1	0x0D4
+#define GPMC_WAIT0	0x0D8
+#define VIN1A_CLK0	0x0DC
+#define VIN1B_CLK1	0x0E0
+#define VIN1A_DE0	0x0E4
+#define VIN1A_FLD0	0x0E8
+#define VIN1A_HSYNC0	0x0EC
+#define VIN1A_VSYNC0	0x0F0
+#define VIN1A_D0	0x0F4
+#define VIN1A_D1	0x0F8
+#define VIN1A_D2	0x0FC
+#define VIN1A_D3	0x100
+#define VIN1A_D4	0x104
+#define VIN1A_D5	0x108
+#define VIN1A_D6	0x10C
+#define VIN1A_D7	0x110
+#define VIN1A_D8	0x114
+#define VIN1A_D9	0x118
+#define VIN1A_D10	0x11C
+#define VIN1A_D11	0x120
+#define VIN1A_D12	0x124
+#define VIN1A_D13	0x128
+#define VIN1A_D14	0x12C
+#define VIN1A_D15	0x130
+#define VIN1A_D16	0x134
+#define VIN1A_D17	0x138
+#define VIN1A_D18	0x13C
+#define VIN1A_D19	0x140
+#define VIN1A_D20	0x144
+#define VIN1A_D21	0x148
+#define VIN1A_D22	0x14C
+#define VIN1A_D23	0x150
+#define VIN2A_CLK0	0x154
+#define VIN2A_DE0	0x158
+#define VIN2A_FLD0	0x15C
+#define VIN2A_HSYNC0	0x160
+#define VIN2A_VSYNC0	0x164
+#define VIN2A_D0	0x168
+#define VIN2A_D1	0x16C
+#define VIN2A_D2	0x170
+#define VIN2A_D3	0x174
+#define VIN2A_D4	0x178
+#define VIN2A_D5	0x17C
+#define VIN2A_D6	0x180
+#define VIN2A_D7	0x184
+#define VIN2A_D8	0x188
+#define VIN2A_D9	0x18C
+#define VIN2A_D10	0x190
+#define VIN2A_D11	0x194
+#define VIN2A_D12	0x198
+#define VIN2A_D13	0x19C
+#define VIN2A_D14	0x1A0
+#define VIN2A_D15	0x1A4
+#define VIN2A_D16	0x1A8
+#define VIN2A_D17	0x1AC
+#define VIN2A_D18	0x1B0
+#define VIN2A_D19	0x1B4
+#define VIN2A_D20	0x1B8
+#define VIN2A_D21	0x1BC
+#define VIN2A_D22	0x1C0
+#define VIN2A_D23	0x1C4
+#define VOUT1_CLK	0x1C8
+#define VOUT1_DE	0x1CC
+#define VOUT1_FLD	0x1D0
+#define VOUT1_HSYNC	0x1D4
+#define VOUT1_VSYNC	0x1D8
+#define VOUT1_D0	0x1DC
+#define VOUT1_D1	0x1E0
+#define VOUT1_D2	0x1E4
+#define VOUT1_D3	0x1E8
+#define VOUT1_D4	0x1EC
+#define VOUT1_D5	0x1F0
+#define VOUT1_D6	0x1F4
+#define VOUT1_D7	0x1F8
+#define VOUT1_D8	0x1FC
+#define VOUT1_D9	0x200
+#define VOUT1_D10	0x204
+#define VOUT1_D11	0x208
+#define VOUT1_D12	0x20C
+#define VOUT1_D13	0x210
+#define VOUT1_D14	0x214
+#define VOUT1_D15	0x218
+#define VOUT1_D16	0x21C
+#define VOUT1_D17	0x220
+#define VOUT1_D18	0x224
+#define VOUT1_D19	0x228
+#define VOUT1_D20	0x22C
+#define VOUT1_D21	0x230
+#define VOUT1_D22	0x234
+#define VOUT1_D23	0x238
+#define MDIO_MCLK	0x23C
+#define MDIO_D		0x240
+#define RMII_MHZ_50_CLK	0x244
+#define UART3_RXD	0x248
+#define UART3_TXD	0x24C
+#define RGMII0_TXC	0x250
+#define RGMII0_TXCTL	0x254
+#define RGMII0_TXD3	0x258
+#define RGMII0_TXD2	0x25C
+#define RGMII0_TXD1	0x260
+#define RGMII0_TXD0	0x264
+#define RGMII0_RXC	0x268
+#define RGMII0_RXCTL	0x26C
+#define RGMII0_RXD3	0x270
+#define RGMII0_RXD2	0x274
+#define RGMII0_RXD1	0x278
+#define RGMII0_RXD0	0x27C
+#define USB1_DRVVBUS	0x280
+#define USB2_DRVVBUS	0x284
+#define GPIO6_14	0x288
+#define GPIO6_15	0x28C
+#define GPIO6_16	0x290
+#define XREF_CLK0	0x294
+#define XREF_CLK1	0x298
+#define XREF_CLK2	0x29C
+#define XREF_CLK3	0x2A0
+#define MCASP1_ACLKX	0x2A4
+#define MCASP1_FSX	0x2A8
+#define MCASP1_ACLKR	0x2AC
+#define MCASP1_FSR	0x2B0
+#define MCASP1_AXR0	0x2B4
+#define MCASP1_AXR1	0x2B8
+#define MCASP1_AXR2	0x2BC
+#define MCASP1_AXR3	0x2C0
+#define MCASP1_AXR4	0x2C4
+#define MCASP1_AXR5	0x2C8
+#define MCASP1_AXR6	0x2CC
+#define MCASP1_AXR7	0x2D0
+#define MCASP1_AXR8	0x2D4
+#define MCASP1_AXR9	0x2D8
+#define MCASP1_AXR10	0x2DC
+#define MCASP1_AXR11	0x2E0
+#define MCASP1_AXR12	0x2E4
+#define MCASP1_AXR13	0x2E8
+#define MCASP1_AXR14	0x2EC
+#define MCASP1_AXR15	0x2F0
+#define MCASP2_ACLKX	0x2F4
+#define MCASP2_FSX	0x2F8
+#define MCASP2_ACLKR	0x2FC
+#define MCASP2_FSR	0x300
+#define MCASP2_AXR0	0x304
+#define MCASP2_AXR1	0x308
+#define MCASP2_AXR2	0x30C
+#define MCASP2_AXR3	0x310
+#define MCASP2_AXR4	0x314
+#define MCASP2_AXR5	0x318
+#define MCASP2_AXR6	0x31C
+#define MCASP2_AXR7	0x320
+#define MCASP3_ACLKX	0x324
+#define MCASP3_FSX	0x328
+#define MCASP3_AXR0	0x32C
+#define MCASP3_AXR1	0x330
+#define MCASP4_ACLKX	0x334
+#define MCASP4_FSX	0x338
+#define MCASP4_AXR0	0x33C
+#define MCASP4_AXR1	0x340
+#define MCASP5_ACLKX	0x344
+#define MCASP5_FSX	0x348
+#define MCASP5_AXR0	0x34C
+#define MCASP5_AXR1	0x350
+#define MMC1_CLK	0x354
+#define MMC1_CMD	0x358
+#define MMC1_DAT0	0x35C
+#define MMC1_DAT1	0x360
+#define MMC1_DAT2	0x364
+#define MMC1_DAT3	0x368
+#define MMC1_SDCD	0x36C
+#define MMC1_SDWP	0x370
+#define GPIO6_10	0x374
+#define GPIO6_11	0x378
+#define MMC3_CLK	0x37C
+#define MMC3_CMD	0x380
+#define MMC3_DAT0	0x384
+#define MMC3_DAT1	0x388
+#define MMC3_DAT2	0x38C
+#define MMC3_DAT3	0x390
+#define MMC3_DAT4	0x394
+#define MMC3_DAT5	0x398
+#define MMC3_DAT6	0x39C
+#define MMC3_DAT7	0x3A0
+#define SPI1_SCLK	0x3A4
+#define SPI1_D1		0x3A8
+#define SPI1_D0		0x3AC
+#define SPI1_CS0	0x3B0
+#define SPI1_CS1	0x3B4
+#define SPI1_CS2	0x3B8
+#define SPI1_CS3	0x3BC
+#define SPI2_SCLK	0x3C0
+#define SPI2_D1		0x3C4
+#define SPI2_D0		0x3C8
+#define SPI2_CS0	0x3CC
+#define DCAN1_TX	0x3D0
+#define DCAN1_RX	0x3D4
+#define DCAN2_TX	0x3D8
+#define DCAN2_RX	0x3DC
+#define UART1_RXD	0x3E0
+#define UART1_TXD	0x3E4
+#define UART1_CTSN	0x3E8
+#define UART1_RTSN	0x3EC
+#define UART2_RXD	0x3F0
+#define UART2_TXD	0x3F4
+#define UART2_CTSN	0x3F8
+#define UART2_RTSN	0x3FC
+#define I2C1_SDA	0x400
+#define I2C1_SCL	0x404
+#define I2C2_SDA	0x408
+#define I2C2_SCL	0x40C
+#define I2C3_SDA	0x410
+#define I2C3_SCL	0x414
+#define WAKEUP0		0x418
+#define WAKEUP1		0x41C
+#define WAKEUP2		0x420
+#define WAKEUP3		0x424
+#define ON_OFF		0x428
+#define RTC_PORZ	0x42C
+#define TMS		0x430
+#define TDI		0x434
+#define TDO		0x438
+#define TCLK		0x43C
+#define TRSTN		0x440
+#define RTCK		0x444
+#define EMU0		0x448
+#define EMU1		0x44C
+#define EMU2		0x450
+#define EMU3		0x454
+#define EMU4		0x458
+#define RESETN		0x45C
+#define NMIN_DSP	0x460
+#define RSTOUTN		0x464
+
+#define MCAN_SEL_ALT_MASK	0x6000
+#define MCAN_SEL		0x2000
+
+#endif /* _MUX_DRA7XX_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h
new file mode 100644
index 0000000..2460646
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h
@@ -0,0 +1,317 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated
+ * Richard Woodruff		<r-woodruff2@ti.com>
+ * Aneesh V			<aneesh@ti.com>
+ * Balaji Krishnamoorthy	<balajitk@ti.com>
+ */
+#ifndef _MUX_OMAP5_H_
+#define _MUX_OMAP5_H_
+
+#include <asm/types.h>
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_PD          (1 << 12)
+#define OFF_PU          (3 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (2 << 10)
+#define OFF_IN          (1 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (1 << 9)
+#else
+#define OFF_PD          (0 << 12)
+#define OFF_PU          (0 << 12)
+#define OFF_OUT_PTD     (0 << 10)
+#define OFF_OUT_PTU     (0 << 10)
+#define OFF_IN          (0 << 10)
+#define OFF_OUT         (0 << 10)
+#define OFF_EN          (0 << 9)
+#endif
+
+#define IEN             (1 << 8)
+#define IDIS            (0 << 8)
+#define PTU             (3 << 3)
+#define PTD             (1 << 3)
+#define EN              (1 << 3)
+#define DIS             (0 << 3)
+
+#define M0              0
+#define M1              1
+#define M2              2
+#define M3              3
+#define M4              4
+#define M5              5
+#define M6              6
+#define M7              7
+
+#define SAFE_MODE	M7
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
+#define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
+#define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
+#define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
+#else
+#define OFF_IN_PD       0
+#define OFF_IN_PU       0
+#define OFF_OUT_PD      0
+#define OFF_OUT_PU      0
+#endif
+
+#define CORE_REVISION		0x0000
+#define CORE_HWINFO		0x0004
+#define CORE_SYSCONFIG		0x0010
+#define EMMC_CLK		0x0040
+#define EMMC_CMD		0x0042
+#define EMMC_DATA0		0x0044
+#define EMMC_DATA1		0x0046
+#define EMMC_DATA2		0x0048
+#define EMMC_DATA3		0x004a
+#define EMMC_DATA4		0x004c
+#define EMMC_DATA5		0x004e
+#define EMMC_DATA6		0x0050
+#define EMMC_DATA7		0x0052
+#define C2C_CLKOUT0		0x0054
+#define C2C_CLKOUT1		0x0056
+#define C2C_CLKIN0		0x0058
+#define C2C_CLKIN1		0x005a
+#define C2C_DATAIN0		0x005c
+#define C2C_DATAIN1		0x005e
+#define C2C_DATAIN2		0x0060
+#define C2C_DATAIN3		0x0062
+#define C2C_DATAIN4		0x0064
+#define C2C_DATAIN5		0x0066
+#define C2C_DATAIN6		0x0068
+#define C2C_DATAIN7		0x006a
+#define C2C_DATAOUT0		0x006c
+#define C2C_DATAOUT1		0x006e
+#define C2C_DATAOUT2		0x0070
+#define C2C_DATAOUT3		0x0072
+#define C2C_DATAOUT4		0x0074
+#define C2C_DATAOUT5		0x0076
+#define C2C_DATAOUT6		0x0078
+#define C2C_DATAOUT7		0x007a
+#define C2C_DATA8		0x007c
+#define C2C_DATA9		0x007e
+#define C2C_DATA10		0x0080
+#define C2C_DATA11		0x0082
+#define C2C_DATA12		0x0084
+#define C2C_DATA13		0x0086
+#define C2C_DATA14		0x0088
+#define C2C_DATA15		0x008a
+#define LLIA_WAKEREQOUT		0x008c
+#define LLIB_WAKEREQOUT		0x008e
+#define HSI1_ACREADY		0x0090
+#define HSI1_CAREADY		0x0092
+#define HSI1_ACWAKE		0x0094
+#define HSI1_CAWAKE		0x0096
+#define HSI1_ACFLAG		0x0098
+#define HSI1_ACDATA		0x009a
+#define HSI1_CAFLAG		0x009c
+#define HSI1_CADATA		0x009e
+#define UART1_TX		0x00a0
+#define UART1_CTS		0x00a2
+#define UART1_RX		0x00a4
+#define UART1_RTS		0x00a6
+#define HSI2_CAREADY		0x00a8
+#define HSI2_ACREADY		0x00aa
+#define HSI2_CAWAKE		0x00ac
+#define HSI2_ACWAKE		0x00ae
+#define HSI2_CAFLAG		0x00b0
+#define HSI2_CADATA		0x00b2
+#define HSI2_ACFLAG		0x00b4
+#define HSI2_ACDATA		0x00b6
+#define UART2_RTS		0x00b8
+#define UART2_CTS		0x00ba
+#define UART2_RX		0x00bc
+#define UART2_TX		0x00be
+#define USBB1_HSIC_STROBE	0x00c0
+#define USBB1_HSIC_DATA		0x00c2
+#define USBB2_HSIC_STROBE	0x00c4
+#define USBB2_HSIC_DATA		0x00c6
+#define TIMER10_PWM_EVT		0x00c8
+#define DSIPORTA_TE0		0x00ca
+#define DSIPORTA_LANE0X		0x00cc
+#define DSIPORTA_LANE0Y		0x00ce
+#define DSIPORTA_LANE1X		0x00d0
+#define DSIPORTA_LANE1Y		0x00d2
+#define DSIPORTA_LANE2X		0x00d4
+#define DSIPORTA_LANE2Y		0x00d6
+#define DSIPORTA_LANE3X		0x00d8
+#define DSIPORTA_LANE3Y		0x00da
+#define DSIPORTA_LANE4X		0x00dc
+#define DSIPORTA_LANE4Y		0x00de
+#define DSIPORTC_LANE0X		0x00e0
+#define DSIPORTC_LANE0Y		0x00e2
+#define DSIPORTC_LANE1X		0x00e4
+#define DSIPORTC_LANE1Y		0x00e6
+#define DSIPORTC_LANE2X		0x00e8
+#define DSIPORTC_LANE2Y		0x00ea
+#define DSIPORTC_LANE3X		0x00ec
+#define DSIPORTC_LANE3Y		0x00ee
+#define DSIPORTC_LANE4X		0x00f0
+#define DSIPORTC_LANE4Y		0x00f2
+#define DSIPORTC_TE0		0x00f4
+#define TIMER9_PWM_EVT		0x00f6
+#define I2C4_SCL		0x00f8
+#define I2C4_SDA		0x00fa
+#define MCSPI2_CLK		0x00fc
+#define MCSPI2_SIMO		0x00fe
+#define MCSPI2_SOMI		0x0100
+#define MCSPI2_CS0		0x0102
+#define RFBI_DATA15		0x0104
+#define RFBI_DATA14		0x0106
+#define RFBI_DATA13		0x0108
+#define RFBI_DATA12		0x010a
+#define RFBI_DATA11		0x010c
+#define RFBI_DATA10		0x010e
+#define RFBI_DATA9		0x0110
+#define RFBI_DATA8		0x0112
+#define RFBI_DATA7		0x0114
+#define RFBI_DATA6		0x0116
+#define RFBI_DATA5		0x0118
+#define RFBI_DATA4		0x011a
+#define RFBI_DATA3		0x011c
+#define RFBI_DATA2		0x011e
+#define RFBI_DATA1		0x0120
+#define RFBI_DATA0		0x0122
+#define RFBI_WE			0x0124
+#define RFBI_CS0		0x0126
+#define RFBI_A0			0x0128
+#define RFBI_RE			0x012a
+#define RFBI_HSYNC0		0x012c
+#define RFBI_TE_VSYNC0		0x012e
+#define GPIO6_182		0x0130
+#define GPIO6_183		0x0132
+#define GPIO6_184		0x0134
+#define GPIO6_185		0x0136
+#define GPIO6_186		0x0138
+#define GPIO6_187		0x013a
+#define HDMI_CEC		0x013c
+#define HDMI_HPD		0x013e
+#define HDMI_DDC_SCL		0x0140
+#define HDMI_DDC_SDA		0x0142
+#define CSIPORTC_LANE0X		0x0144
+#define CSIPORTC_LANE0Y		0x0146
+#define CSIPORTC_LANE1X		0x0148
+#define CSIPORTC_LANE1Y		0x014a
+#define CSIPORTB_LANE0X		0x014c
+#define CSIPORTB_LANE0Y		0x014e
+#define CSIPORTB_LANE1X		0x0150
+#define CSIPORTB_LANE1Y		0x0152
+#define CSIPORTB_LANE2X		0x0154
+#define CSIPORTB_LANE2Y		0x0156
+#define CSIPORTA_LANE0X		0x0158
+#define CSIPORTA_LANE0Y		0x015a
+#define CSIPORTA_LANE1X		0x015c
+#define CSIPORTA_LANE1Y		0x015e
+#define CSIPORTA_LANE2X		0x0160
+#define CSIPORTA_LANE2Y		0x0162
+#define CSIPORTA_LANE3X		0x0164
+#define CSIPORTA_LANE3Y		0x0166
+#define CSIPORTA_LANE4X		0x0168
+#define CSIPORTA_LANE4Y		0x016a
+#define CAM_SHUTTER		0x016c
+#define CAM_STROBE		0x016e
+#define CAM_GLOBALRESET		0x0170
+#define TIMER11_PWM_EVT		0x0172
+#define TIMER5_PWM_EVT		0x0174
+#define TIMER6_PWM_EVT		0x0176
+#define TIMER8_PWM_EVT		0x0178
+#define I2C3_SCL		0x017a
+#define I2C3_SDA		0x017c
+#define GPIO8_233		0x017e
+#define GPIO8_234		0x0180
+#define ABE_CLKS		0x0182
+#define ABEDMIC_DIN1		0x0184
+#define ABEDMIC_DIN2		0x0186
+#define ABEDMIC_DIN3		0x0188
+#define ABEDMIC_CLK1		0x018a
+#define ABEDMIC_CLK2		0x018c
+#define ABEDMIC_CLK3		0x018e
+#define ABESLIMBUS1_CLOCK	0x0190
+#define ABESLIMBUS1_DATA	0x0192
+#define ABEMCBSP2_DR		0x0194
+#define ABEMCBSP2_DX		0x0196
+#define ABEMCBSP2_FSX		0x0198
+#define ABEMCBSP2_CLKX		0x019a
+#define ABEMCPDM_UL_DATA	0x019c
+#define ABEMCPDM_DL_DATA	0x019e
+#define ABEMCPDM_FRAME		0x01a0
+#define ABEMCPDM_LB_CLK		0x01a2
+#define WLSDIO_CLK		0x01a4
+#define WLSDIO_CMD		0x01a6
+#define WLSDIO_DATA0		0x01a8
+#define WLSDIO_DATA1		0x01aa
+#define WLSDIO_DATA2		0x01ac
+#define WLSDIO_DATA3		0x01ae
+#define UART5_RX		0x01b0
+#define UART5_TX		0x01b2
+#define UART5_CTS		0x01b4
+#define UART5_RTS		0x01b6
+#define I2C2_SCL		0x01b8
+#define I2C2_SDA		0x01ba
+#define MCSPI1_CLK		0x01bc
+#define MCSPI1_SOMI		0x01be
+#define MCSPI1_SIMO		0x01c0
+#define MCSPI1_CS0		0x01c2
+#define MCSPI1_CS1		0x01c4
+#define I2C5_SCL		0x01c6
+#define I2C5_SDA		0x01c8
+#define PERSLIMBUS2_CLOCK	0x01ca
+#define PERSLIMBUS2_DATA	0x01cc
+#define UART6_TX		0x01ce
+#define UART6_RX		0x01d0
+#define UART6_CTS		0x01d2
+#define UART6_RTS		0x01d4
+#define UART3_CTS_RCTX		0x01d6
+#define UART3_RTS_IRSD		0x01d8
+#define UART3_TX_IRTX		0x01da
+#define UART3_RX_IRRX		0x01dc
+#define USBB3_HSIC_STROBE	0x01de
+#define USBB3_HSIC_DATA		0x01e0
+#define SDCARD_CLK		0x01e2
+#define SDCARD_CMD		0x01e4
+#define SDCARD_DATA2		0x01e6
+#define SDCARD_DATA3		0x01e8
+#define SDCARD_DATA0		0x01ea
+#define SDCARD_DATA1		0x01ec
+#define USBD0_HS_DP		0x01ee
+#define USBD0_HS_DM		0x01f0
+#define I2C1_PMIC_SCL		0x01f2
+#define I2C1_PMIC_SDA		0x01f4
+#define USBD0_SS_RX		0x01f6
+
+#define LLIA_WAKEREQIN		0x0040
+#define LLIB_WAKEREQIN		0x0042
+#define DRM_EMU0		0x0044
+#define DRM_EMU1		0x0046
+#define JTAG_NTRST		0x0048
+#define JTAG_TCK		0x004a
+#define JTAG_RTCK		0x004c
+#define JTAG_TMSC		0x004e
+#define JTAG_TDI		0x0050
+#define JTAG_TDO		0x0052
+#define SYS_32K			0x0054
+#define FREF_CLK_IOREQ		0x0056
+#define FREF_CLK0_OUT		0x0058
+#define FREF_CLK1_OUT		0x005a
+#define FREF_CLK2_OUT		0x005c
+#define FREF_CLK2_REQ		0x005e
+#define FREF_CLK1_REQ		0x0060
+#define SYS_NRESPWRON		0x0062
+#define SYS_NRESWARM		0x0064
+#define SYS_PWR_REQ		0x0066
+#define SYS_NIRQ1		0x0068
+#define SYS_NIRQ2		0x006a
+#define SR_PMIC_SCL		0x006c
+#define SR_PMIC_SDA		0x006e
+#define SYS_BOOT0		0x0070
+#define SYS_BOOT1		0x0072
+#define SYS_BOOT2		0x0074
+#define SYS_BOOT3		0x0076
+#define SYS_BOOT4		0x0078
+#define SYS_BOOT5		0x007a
+
+#endif /* _MUX_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
new file mode 100644
index 0000000..a9c0421
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Authors:
+ *	Aneesh V <aneesh@ti.com>
+ *	Sricharan R <r.sricharan@ti.com>
+ */
+
+#ifndef _OMAP5_H_
+#define _OMAP5_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#include <linux/sizes.h>
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP54XX_L4_CORE_BASE	0x4A000000
+#define OMAP54XX_L4_WKUP_BASE	0x4Ae00000
+#define OMAP54XX_L4_PER_BASE	0x48000000
+
+/* CONTROL ID CODE */
+#define CONTROL_CORE_ID_CODE	0x4A002204
+#define CONTROL_WKUP_ID_CODE	0x4AE0C204
+
+#if defined(CONFIG_DRA7XX)
+#define CONTROL_ID_CODE		CONTROL_WKUP_ID_CODE
+#else
+#define CONTROL_ID_CODE		CONTROL_CORE_ID_CODE
+#endif
+
+#if defined(CONFIG_DRA7XX)
+#define DRA7_USB_OTG_SS1_BASE		0x48890000
+#define DRA7_USB_OTG_SS1_GLUE_BASE	0x48880000
+#define DRA7_USB3_PHY1_PLL_CTRL		0x4A084C00
+#define DRA7_USB3_PHY1_POWER		0x4A002370
+#define DRA7_USB2_PHY1_POWER		0x4A002300
+
+#define DRA7_USB_OTG_SS2_BASE		0x488D0000
+#define DRA7_USB_OTG_SS2_GLUE_BASE	0x488C0000
+#define DRA7_USB2_PHY2_POWER		0x4A002E74
+#else
+#define OMAP5XX_USB_OTG_SS_BASE		0x4A030000
+#define OMAP5XX_USB_OTG_SS_GLUE_BASE	0x4A020000
+#define OMAP5XX_USB3_PHY_PLL_CTRL	0x4A084C00
+#define OMAP5XX_USB3_PHY_POWER		0x4A002370
+#define OMAP5XX_USB2_PHY_POWER		0x4A002300
+#endif
+
+/* To be verified */
+#define OMAP5430_CONTROL_ID_CODE_ES1_0		0x0B94202F
+#define OMAP5430_CONTROL_ID_CODE_ES2_0          0x1B94202F
+#define OMAP5432_CONTROL_ID_CODE_ES1_0		0x0B99802F
+#define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
+#define DRA762_CONTROL_ID_CODE_ES1_0		0x0BB5002F
+#define DRA752_CONTROL_ID_CODE_ES1_0		0x0B99002F
+#define DRA752_CONTROL_ID_CODE_ES1_1		0x1B99002F
+#define DRA752_CONTROL_ID_CODE_ES2_0		0x2B99002F
+#define DRA722_CONTROL_ID_CODE_ES1_0		0x0B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_0		0x1B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_1		0x2B9BC02F
+
+#define DRA762_ABZ_PACKAGE			0x2
+#define DRA762_ACD_PACKAGE			0x3
+
+/* UART */
+#define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
+#define UART2_BASE		(OMAP54XX_L4_PER_BASE + 0x6c000)
+#define UART3_BASE		(OMAP54XX_L4_PER_BASE + 0x20000)
+#define UART4_BASE		(OMAP54XX_L4_PER_BASE + 0x6e000)
+
+/* General Purpose Timers */
+#define GPT1_BASE		(OMAP54XX_L4_WKUP_BASE + 0x18000)
+#define GPT2_BASE		(OMAP54XX_L4_PER_BASE  + 0x32000)
+#define GPT3_BASE		(OMAP54XX_L4_PER_BASE  + 0x34000)
+
+/* Watchdog Timer2 - MPU watchdog */
+#define WDT2_BASE		(OMAP54XX_L4_WKUP_BASE + 0x14000)
+
+/* QSPI */
+#define QSPI_BASE		0x4B300000
+
+/* SATA */
+#define DWC_AHSATA_BASE		0x4A140000
+
+/*
+ * Hardware Register Details
+ */
+
+/* Watchdog Timer */
+#define WD_UNLOCK1		0xAAAA
+#define WD_UNLOCK2		0x5555
+
+/* GP Timer */
+#define TCLR_ST			(0x1 << 0)
+#define TCLR_AR			(0x1 << 1)
+#define TCLR_PRE		(0x1 << 5)
+
+/* Control Module */
+#define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
+#define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f
+#define CONTROL_EFUSE_1_OVERRIDE	0x1C4D0110
+#define CONTROL_EFUSE_2_OVERRIDE	0x00084000
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN	0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER	0x9E9E9E9E
+#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN	0x7C7C7C7C
+#define LPDDR2IO_GR10_WD_MASK				(3 << 17)
+#define CONTROL_LPDDR2IO_3_VAL		0xA0888C00
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
+
+#define SDCARD_BIAS_PWRDNZ				(1 << 27)
+#define SDCARD_PWRDNZ					(1 << 26)
+#define SDCARD_BIAS_HIZ_MODE				(1 << 25)
+#define SDCARD_PBIASLITE_VMODE				(1 << 21)
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+	unsigned char res[0x10];
+	unsigned int s32k_cr;	/* 0x10 */
+};
+
+#define DEVICE_TYPE_SHIFT 0x6
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+
+/* Output impedance control */
+#define ds_120_ohm	0x0
+#define ds_60_ohm	0x1
+#define ds_45_ohm	0x2
+#define ds_30_ohm	0x3
+#define ds_mask		0x3
+
+/* Slew rate control */
+#define sc_slow		0x0
+#define sc_medium	0x1
+#define sc_fast		0x2
+#define sc_na		0x3
+#define sc_mask		0x3
+
+/* Target capacitance control */
+#define lb_5_12_pf	0x0
+#define lb_12_25_pf	0x1
+#define lb_25_50_pf	0x2
+#define lb_50_80_pf	0x3
+#define lb_mask		0x3
+
+#define usb_i_mask	0x7
+
+#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN   0x80828082
+#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
+#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
+#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
+#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
+
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL	0x7C7C7C6C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL	0x64646464
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE				0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE				0xBC6318DC
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE				0x0
+
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
+
+#define EFUSE_1 0x45145100
+#define EFUSE_2 0x45145100
+#define EFUSE_3 0x45145100
+#define EFUSE_4 0x45145100
+#endif /* __ASSEMBLY__ */
+
+/*
+ * In all cases, the TRM defines the RAM Memory Map for the processor
+ * and indicates the area for the downloaded image.  We use all of that
+ * space for download and once up and running may use other parts of the
+ * map for our needs.  We set a scratch space that is at the end of the
+ * OMAP5 download area, but within the DRA7xx download area (as it is
+ * much larger) and do not, at this time, make use of the additional
+ * space.
+ */
+#if defined(CONFIG_DRA7XX)
+#define NON_SECURE_SRAM_START	0x40300000
+#define NON_SECURE_SRAM_END	0x40380000	/* Not inclusive */
+#define NON_SECURE_SRAM_IMG_END	0x4037C000
+#else
+#define NON_SECURE_SRAM_START	0x40300000
+#define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
+#define NON_SECURE_SRAM_IMG_END	0x4031E000
+#endif
+#define SRAM_SCRATCH_SPACE_ADDR	(NON_SECURE_SRAM_IMG_END - SZ_1K)
+
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_ROM_VECT_BASE	0x4031F000
+
+/* CONTROL_SRCOMP_XXX_SIDE */
+#define OVERRIDE_XS_SHIFT		30
+#define OVERRIDE_XS_MASK		(1 << 30)
+#define SRCODE_READ_XS_SHIFT		12
+#define SRCODE_READ_XS_MASK		(0xff << 12)
+#define PWRDWN_XS_SHIFT			11
+#define PWRDWN_XS_MASK			(1 << 11)
+#define DIVIDE_FACTOR_XS_SHIFT		4
+#define DIVIDE_FACTOR_XS_MASK		(0x7f << 4)
+#define MULTIPLY_FACTOR_XS_SHIFT	1
+#define MULTIPLY_FACTOR_XS_MASK		(0x7 << 1)
+#define SRCODE_OVERRIDE_SEL_XS_SHIFT	0
+#define SRCODE_OVERRIDE_SEL_XS_MASK	(1 << 0)
+
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME		50
+#define OMAP_ABB_CLOCK_CYCLES		16
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK		(0x1 << 7)
+#define OMAP_ABB_MM_TXDONE_MASK			(0x1 << 31)
+#define OMAP_ABB_IVA_TXDONE_MASK		(0x1 << 30)
+#define OMAP_ABB_EVE_TXDONE_MASK		(0x1 << 29)
+#define OMAP_ABB_GPU_TXDONE_MASK		(0x1 << 28)
+
+/* ABB efuse masks */
+#define OMAP5_PROD_ABB_FUSE_VSET_MASK		(0x1F << 20)
+#define OMAP5_PROD_ABB_FUSE_ENABLE_MASK		(0x1 << 25)
+#define DRA7_ABB_FUSE_VSET_MASK			(0x1F << 20)
+#define DRA7_ABB_FUSE_ENABLE_MASK		(0x1 << 25)
+#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK	(0x1 << 10)
+#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK	(0x1f << 0)
+
+#ifndef __ASSEMBLY__
+struct srcomp_params {
+	s8 divide_factor;
+	s8 multiply_factor;
+};
+
+struct ctrl_ioregs {
+	u32 ctrl_ddrch;
+	u32 ctrl_lpddr2ch;
+	u32 ctrl_ddr3ch;
+	u32 ctrl_ddrio_0;
+	u32 ctrl_ddrio_1;
+	u32 ctrl_ddrio_2;
+	u32 ctrl_emif_sdram_config_ext;
+	u32 ctrl_emif_sdram_config_ext_final;
+	u32 ctrl_ddr_ctrl_ext_0;
+};
+
+void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits);
+
+#endif /* __ASSEMBLY__ */
+
+/* Boot parameters */
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+	unsigned int boot_message;
+	unsigned int boot_device_descriptor;
+	unsigned char boot_device;
+	unsigned char reset_reason;
+	unsigned char ch_flags;
+};
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap5/sata.h b/arch/arm/include/asm/arch-omap5/sata.h
new file mode 100644
index 0000000..96c84fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/sata.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * SATA Wrapper Register map
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ */
+
+#ifndef _TI_SATA_H
+#define _TI_SATA_H
+
+/* SATA Wrapper module */
+#define TI_SATA_WRAPPER_BASE		(OMAP54XX_L4_CORE_BASE + 0x141100)
+/* SATA PHY Module */
+#define TI_SATA_PLLCTRL_BASE		(OMAP54XX_L4_CORE_BASE + 0x96800)
+
+/* SATA Wrapper register offsets */
+#define TI_SATA_SYSCONFIG			0x00
+#define TI_SATA_CDRLOCK				0x04
+
+/* Register Set */
+#define TI_SATA_SYSCONFIG_OVERRIDE0		(1 << 16)
+#define TI_SATA_SYSCONFIG_STANDBY_MASK		(0x3 << 4)
+#define TI_SATA_SYSCONFIG_IDLE_MASK		(0x3 << 2)
+
+/* Standby modes */
+#define TI_SATA_STANDBY_FORCE			0x0
+#define TI_SATA_STANDBY_NO			(0x1 << 4)
+#define TI_SATA_STANDBY_SMART_WAKE		(0x3 << 4)
+#define TI_SATA_STANDBY_SMART			(0x2 << 4)
+
+/* Idle modes */
+#define TI_SATA_IDLE_FORCE			0x0
+#define TI_SATA_IDLE_NO				(0x1 << 2)
+#define TI_SATA_IDLE_SMART_WAKE			(0x3 << 2)
+#define TI_SATA_IDLE_SMART			(0x2 << 2)
+
+#endif /* _TI_SATA_H */
diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h
new file mode 100644
index 0000000..cda3b46
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/spl.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NONE	0x00
+#define BOOT_DEVICE_XIP		0x01
+#define BOOT_DEVICE_XIPWAIT	0x02
+#define BOOT_DEVICE_NAND	0x03
+#define BOOT_DEVICE_ONENAND	0x04
+#define BOOT_DEVICE_MMC1	0x05
+#define BOOT_DEVICE_MMC2	0x06
+#define BOOT_DEVICE_MMC2_2	0x07
+#define BOOT_DEVICE_SATA	0x09
+#define BOOT_DEVICE_SPI		0x0A
+#define BOOT_DEVICE_QSPI_1	0x0A
+#define BOOT_DEVICE_QSPI_4	0x0B
+#define BOOT_DEVICE_UART	0x43
+#define BOOT_DEVICE_DFU		0x45
+
+#define MMC_BOOT_DEVICES_START	BOOT_DEVICE_MMC1
+#define MMC_BOOT_DEVICES_END	BOOT_DEVICE_MMC2_2
+#endif
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
new file mode 100644
index 0000000..80b0c93
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/arch/omap.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/omap_common.h>
+#include <linux/mtd/omap_gpmc.h>
+#include <asm/arch/clock.h>
+#include <asm/ti-common/sys_proto.h>
+
+/*
+ * Structure for Iodelay configuration registers.
+ * Theoretical max for g_delay is 21560 ps.
+ * Theoretical max for a_delay is 1/3rd of g_delay max.
+ * So using u16 for both a/g_delay.
+ */
+struct iodelay_cfg_entry {
+	u16 offset;
+	u16 a_delay;
+	u16 g_delay;
+};
+
+struct pad_conf_entry {
+	u32 offset;
+	u32 val;
+};
+
+struct mmc_platform_fixups {
+	const char *hw_rev;
+	u32 unsupported_caps;
+	u32 max_freq;
+};
+
+struct omap_sysinfo {
+	char *board_string;
+};
+extern const struct omap_sysinfo sysinfo;
+
+void gpmc_init(void);
+void watchdog_init(void);
+u32 get_device_type(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs(void);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
+void setup_early_clocks(void);
+void prcm_init(void);
+void do_board_detect(void);
+void vcores_init(void);
+void bypass_dpll(u32 const base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap5_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
+void sdram_init(void);
+u32 omap_sdram_size(void);
+u32 cortex_rev(void);
+void save_omap_boot_params(void);
+void init_omap_revision(void);
+void init_package_revision(void);
+void do_io_settings(void);
+void sri2c_init(void);
+int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
+u32 warm_reset(void);
+void force_emif_self_refresh(void);
+void get_ioregs(const struct ctrl_ioregs **regs);
+void srcomp_enable(void);
+void setup_warmreset_time(void);
+const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr);
+
+static inline u32 div_round_up(u32 num, u32 den)
+{
+	return (num + den - 1)/den;
+}
+
+static inline u32 usec_to_32k(u32 usec)
+{
+	return div_round_up(32768 * usec, 1000000);
+}
+
+#define OMAP5_SERVICE_L2ACTLR_SET    0x104
+#define OMAP5_SERVICE_ACR_SET        0x107
+
+#endif
diff --git a/arch/arm/include/asm/arch-orion5x/spl.h b/arch/arm/include/asm/arch-orion5x/spl.h
new file mode 100644
index 0000000..dc0a9b9
--- /dev/null
+++ b/arch/arm/include/asm/arch-orion5x/spl.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ */
+
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_NOR		1
diff --git a/arch/arm/include/asm/arch-owl/clk_s900.h b/arch/arm/include/asm/arch-owl/clk_s900.h
new file mode 100644
index 0000000..88e88f7
--- /dev/null
+++ b/arch/arm/include/asm/arch-owl/clk_s900.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Actions Semi S900 Clock Definitions
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _OWL_CLK_S900_H_
+#define _OWL_CLK_S900_H_
+
+#include <clk-uclass.h>
+
+struct owl_clk_priv {
+	phys_addr_t base;
+};
+
+/* BUSCLK register definitions */
+#define CMU_PDBGDIV_8		7
+#define CMU_PDBGDIV_SHIFT	26
+#define CMU_PDBGDIV_DIV		(CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
+#define CMU_PERDIV_8		7
+#define CMU_PERDIV_SHIFT	20
+#define CMU_PERDIV_DIV		(CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
+#define CMU_NOCDIV_2		1
+#define CMU_NOCDIV_SHIFT	19
+#define CMU_NOCDIV_DIV		(CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
+#define CMU_DMMCLK_SRC_APLL	2
+#define CMU_DMMCLK_SRC_SHIFT	10
+#define CMU_DMMCLK_SRC		(CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT)
+#define CMU_APBCLK_DIV		BIT(8)
+#define CMU_NOCCLK_SRC		BIT(7)
+#define CMU_AHBCLK_DIV		BIT(4)
+#define CMU_CORECLK_MASK	3
+#define CMU_CORECLK_CPLL	BIT(1)
+#define CMU_CORECLK_HOSC	BIT(0)
+
+/* COREPLL register definitions */
+#define CMU_COREPLL_EN		BIT(9)
+#define CMU_COREPLL_HOSC_EN	BIT(8)
+#define CMU_COREPLL_OUT		(1104 / 24)
+
+/* DEVPLL register definitions */
+#define CMU_DEVPLL_CLK		BIT(12)
+#define CMU_DEVPLL_EN		BIT(8)
+#define CMU_DEVPLL_OUT		(660 / 6)
+
+/* UARTCLK register definitions */
+#define CMU_UARTCLK_SRC_DEVPLL	BIT(16)
+
+/* DEVCLKEN1 register definitions */
+#define CMU_DEVCLKEN1_UART5	BIT(21)
+
+#define PLL_STABILITY_WAIT_US	50
+
+#endif
diff --git a/arch/arm/include/asm/arch-owl/regs_s900.h b/arch/arm/include/asm/arch-owl/regs_s900.h
new file mode 100644
index 0000000..9e9106d
--- /dev/null
+++ b/arch/arm/include/asm/arch-owl/regs_s900.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Actions Semi S900 Register Definitions
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _OWL_REGS_S900_H_
+#define _OWL_REGS_S900_H_
+
+/* CMU registers */
+#define CMU_COREPLL				(0x0000)
+#define CMU_DEVPLL				(0x0004)
+#define CMU_DDRPLL				(0x0008)
+#define CMU_NANDPLL				(0x000C)
+#define CMU_DISPLAYPLL				(0x0010)
+#define CMU_AUDIOPLL				(0x0014)
+#define CMU_TVOUTPLL				(0x0018)
+#define CMU_BUSCLK				(0x001C)
+#define CMU_SENSORCLK				(0x0020)
+#define CMU_LCDCLK				(0x0024)
+#define CMU_DSICLK				(0x0028)
+#define CMU_CSICLK				(0x002C)
+#define CMU_DECLK				(0x0030)
+#define CMU_BISPCLK				(0x0034)
+#define CMU_IMXCLK				(0x0038)
+#define CMU_HDECLK				(0x003C)
+#define CMU_VDECLK				(0x0040)
+#define CMU_VCECLK				(0x0044)
+#define CMU_NANDCCLK				(0x004C)
+#define CMU_SD0CLK				(0x0050)
+#define CMU_SD1CLK				(0x0054)
+#define CMU_SD2CLK				(0x0058)
+#define CMU_UART0CLK				(0x005C)
+#define CMU_UART1CLK				(0x0060)
+#define CMU_UART2CLK				(0x0064)
+#define CMU_PWM0CLK				(0x0070)
+#define CMU_PWM1CLK				(0x0074)
+#define CMU_PWM2CLK				(0x0078)
+#define CMU_PWM3CLK				(0x007C)
+#define CMU_USBPLL				(0x0080)
+#define CMU_ASSISTPLL				(0x0084)
+#define CMU_EDPCLK				(0x0088)
+#define CMU_GPU3DCLK				(0x0090)
+#define CMU_CORECTL				(0x009C)
+#define CMU_DEVCLKEN0				(0x00A0)
+#define CMU_DEVCLKEN1				(0x00A4)
+#define CMU_DEVRST0				(0x00A8)
+#define CMU_DEVRST1				(0x00AC)
+#define CMU_UART3CLK				(0x00B0)
+#define CMU_UART4CLK				(0x00B4)
+#define CMU_UART5CLK				(0x00B8)
+#define CMU_UART6CLK				(0x00BC)
+#define CMU_TLSCLK				(0x00C0)
+#define CMU_SD3CLK				(0x00C4)
+#define CMU_PWM4CLK				(0x00C8)
+#define CMU_PWM5CLK				(0x00CC)
+#define CMU_ANALOGDEBUG				(0x00D4)
+#define CMU_TVOUTPLLDEBUG0			(0x00EC)
+#define CMU_TVOUTPLLDEBUG1			(0x00FC)
+
+#endif
diff --git a/arch/arm/include/asm/arch-pxa/bitfield.h b/arch/arm/include/asm/arch-pxa/bitfield.h
new file mode 100644
index 0000000..104a21c
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/bitfield.h
@@ -0,0 +1,112 @@
+/*
+ *	FILE		bitfield.h
+ *
+ *	Version		1.1
+ *	Author		Copyright (c) Marc A. Viredaz, 1998
+ *			DEC Western Research Laboratory, Palo Alto, CA
+ *	Date		April 1998 (April 1997)
+ *	System		Advanced RISC Machine (ARM)
+ *	Language	C or ARM Assembly
+ *	Purpose		Definition of macros to operate on bit fields.
+ */
+
+
+#ifndef __BITFIELD_H
+#define __BITFIELD_H
+
+#ifndef __ASSEMBLY__
+#define UData(Data)	((unsigned long) (Data))
+#else
+#define UData(Data)	(Data)
+#endif
+
+
+/*
+ * MACRO: Fld
+ *
+ * Purpose
+ *    The macro "Fld" encodes a bit field, given its size and its shift value
+ *    with respect to bit 0.
+ *
+ * Note
+ *    A more intuitive way to encode bit fields would have been to use their
+ *    mask. However, extracting size and shift value information from a bit
+ *    field's mask is cumbersome and might break the assembler (255-character
+ *    line-size limit).
+ *
+ * Input
+ *    Size		Size of the bit field, in number of bits.
+ *    Shft		Shift value of the bit field with respect to bit 0.
+ *
+ * Output
+ *    Fld		Encoded bit field.
+ */
+
+#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
+
+
+/*
+ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
+ *
+ * Purpose
+ *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
+ *    the size, shift value, mask, aligned mask, and first bit of a
+ *    bit field.
+ *
+ * Input
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FSize		Size of the bit field, in number of bits.
+ *    FShft		Shift value of the bit field with respect to bit 0.
+ *    FMsk		Mask for the bit field.
+ *    FAlnMsk		Mask for the bit field, aligned on bit 0.
+ *    F1stBit		First bit of the bit field.
+ */
+
+#define FSize(Field)	((Field) >> 16)
+#define FShft(Field)	((Field) & 0x0000FFFF)
+#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field)	(UData (1) << FShft (Field))
+
+
+/*
+ * MACRO: FInsrt
+ *
+ * Purpose
+ *    The macro "FInsrt" inserts a value into a bit field by shifting the
+ *    former appropriately.
+ *
+ * Input
+ *    Value		Bit-field value.
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FInsrt		Bit-field value positioned appropriately.
+ */
+
+#define FInsrt(Value, Field) \
+			(UData (Value) << FShft (Field))
+
+
+/*
+ * MACRO: FExtr
+ *
+ * Purpose
+ *    The macro "FExtr" extracts the value of a bit field by masking and
+ *    shifting it appropriately.
+ *
+ * Input
+ *    Data		Data containing the bit-field to be extracted.
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FExtr		Bit-field value.
+ */
+
+#define FExtr(Data, Field) \
+			((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+
+#endif /* __BITFIELD_H */
diff --git a/arch/arm/include/asm/arch-pxa/config.h b/arch/arm/include/asm/arch-pxa/config.h
new file mode 100644
index 0000000..75b0e49
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/config.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Andrew Ruder <andrew.ruder@elecsyscorp.com>
+ */
+
+#ifndef _ASM_ARM_PXA_CONFIG_
+#define _ASM_ARM_PXA_CONFIG_
+
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * Generic timer support
+ */
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define	CONFIG_SYS_TIMER_RATE	3250000
+#elif defined(CONFIG_CPU_PXA25X)
+#define	CONFIG_SYS_TIMER_RATE	3686400
+#else
+#error "Timer frequency unknown - please config PXA CPU type"
+#endif
+
+#define CONFIG_SYS_TIMER_COUNTER	OSCR
+
+#endif /* _ASM_ARM_PXA_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h
new file mode 100644
index 0000000..6d0023d
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/hardware.h
@@ -0,0 +1,82 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/hardware.h
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Jun 15, 2001
+ *  Copyright:	MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Note: This file was taken from linux-2.4.19-rmk4-pxa1
+ *
+ * - 2003/01/20 implementation specifics activated
+ *   Robert Schwebel <r.schwebel@pengutronix.de>
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/mach-types.h>
+
+/*
+ * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
+ * PXA300/310/320 all have distinct register mappings in some cases, that's why
+ * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
+ * drivers and compatibility glue with old source then.
+ */
+#ifndef	CONFIG_CPU_MONAHANS
+#if	defined(CONFIG_CPU_PXA300) || \
+	defined(CONFIG_CPU_PXA310) || \
+	defined(CONFIG_CPU_PXA320)
+#define	CONFIG_CPU_MONAHANS
+#endif
+#endif
+
+/*
+ * These are statically mapped PCMCIA IO space for designs using it as a
+ * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
+ * The actual PCMCIA code is mapping required IO region at run time.
+ */
+#define PCMCIA_IO_0_BASE	0xf6000000
+#define PCMCIA_IO_1_BASE	0xf7000000
+
+
+/*
+ * We requires absolute addresses.
+ */
+#define PCIO_BASE		0
+
+/*
+ * Workarounds for at least 2 errata so far require this.
+ * The mapping is set in mach-pxa/generic.c.
+ */
+#define UNCACHED_PHYS_0		0xff000000
+#define UNCACHED_ADDR		UNCACHED_PHYS_0
+
+/*
+ * Intel PXA internal I/O mappings:
+ *
+ * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
+ * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
+ * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
+ */
+
+#include "pxa-regs.h"
+
+#ifndef __ASSEMBLY__
+
+/*
+ * GPIO edge detection for IRQs:
+ * IRQs are generated on Falling-Edge, Rising-Edge, or both.
+ * This must be called *before* the corresponding IRQ is registered.
+ * Use this instead of directly setting GRER/GFER.
+ */
+#define GPIO_FALLING_EDGE	1
+#define GPIO_RISING_EDGE	2
+#define GPIO_BOTH_EDGES		3
+
+#endif
+
+#endif	/* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
new file mode 100644
index 0000000..b81b42c
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -0,0 +1,2635 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/pxa-regs.h
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Jun 15, 2001
+ *  Copyright:	MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
+ *   Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
+ *   Added include for hardware.h (for __REG definition)
+ */
+#ifndef _PXA_REGS_H_
+#define _PXA_REGS_H_
+
+#include "bitfield.h"
+#include "hardware.h"
+
+/* FIXME hack so that SA-1111.h will work [cb] */
+
+#ifndef __ASSEMBLY__
+typedef unsigned short	Word16 ;
+typedef unsigned int	Word32 ;
+typedef Word32		Word ;
+typedef Word		Quad [4] ;
+typedef void		*Address ;
+typedef void		(*ExcpHndlr) (void) ;
+#endif
+
+/*
+ * PXA Chip selects
+ */
+#ifdef CONFIG_CPU_MONAHANS
+#define PXA_CS0_PHYS   0x00000000 /* for both small and large same start */
+#define PXA_CS1_PHYS   0x04000000 /* Small partition start address (64MB) */
+#define PXA_CS1_LPHYS  0x30000000 /* Large partition start address (256MB) */
+#define PXA_CS2_PHYS   0x10000000 /* (64MB) */
+#define PXA_CS3_PHYS   0x14000000 /* (64MB) */
+#define PXA_PCMCIA_PHYS        0x20000000 /* (256MB) */
+#else
+#define PXA_CS0_PHYS	0x00000000
+#define PXA_CS1_PHYS	0x04000000
+#define PXA_CS2_PHYS	0x08000000
+#define PXA_CS3_PHYS	0x0C000000
+#define PXA_CS4_PHYS	0x10000000
+#define PXA_CS5_PHYS	0x14000000
+#endif /* CONFIG_CPU_MONAHANS */
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) sockets
+ */
+#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
+#define PCMCIASp	(4*PCMCIAPrtSp) /* PCMCIA Space [byte]		   */
+#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]	   */
+#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
+#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]	   */
+
+#ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */
+#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]	   */
+#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]	   */
+#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
+#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]	   */
+#endif
+
+#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]	   */
+#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]	   */
+#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
+#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]	   */
+
+#define _PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
+			(0x20000000 + (Nb)*PCMCIASp)
+#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]		   */
+#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]	   */ \
+			(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
+#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]		   */ \
+			(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
+
+#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0			   */
+#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O			   */
+#define _PCMCIA0Attr	_PCMCIAAttr (0) /* PCMCIA 0 Attribute		   */
+#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory		   */
+
+#ifndef CONFIG_CPU_MONAHANS             /* Monahans supports only one slot */
+#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1			   */
+#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O			   */
+#define _PCMCIA1Attr	_PCMCIAAttr (1) /* PCMCIA 1 Attribute		   */
+#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory		   */
+#endif
+
+/*
+ * DMA Controller
+ */
+#define DCSR0		0x40000000  /* DMA Control / Status Register for Channel 0 */
+#define DCSR1		0x40000004  /* DMA Control / Status Register for Channel 1 */
+#define DCSR2		0x40000008  /* DMA Control / Status Register for Channel 2 */
+#define DCSR3		0x4000000c  /* DMA Control / Status Register for Channel 3 */
+#define DCSR4		0x40000010  /* DMA Control / Status Register for Channel 4 */
+#define DCSR5		0x40000014  /* DMA Control / Status Register for Channel 5 */
+#define DCSR6		0x40000018  /* DMA Control / Status Register for Channel 6 */
+#define DCSR7		0x4000001c  /* DMA Control / Status Register for Channel 7 */
+#define DCSR8		0x40000020  /* DMA Control / Status Register for Channel 8 */
+#define DCSR9		0x40000024  /* DMA Control / Status Register for Channel 9 */
+#define DCSR10		0x40000028  /* DMA Control / Status Register for Channel 10 */
+#define DCSR11		0x4000002c  /* DMA Control / Status Register for Channel 11 */
+#define DCSR12		0x40000030  /* DMA Control / Status Register for Channel 12 */
+#define DCSR13		0x40000034  /* DMA Control / Status Register for Channel 13 */
+#define DCSR14		0x40000038  /* DMA Control / Status Register for Channel 14 */
+#define DCSR15		0x4000003c  /* DMA Control / Status Register for Channel 15 */
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define DCSR16		0x40000040  /* DMA Control / Status Register for Channel 16 */
+#define DCSR17		0x40000044  /* DMA Control / Status Register for Channel 17 */
+#define DCSR18		0x40000048  /* DMA Control / Status Register for Channel 18 */
+#define DCSR19		0x4000004c  /* DMA Control / Status Register for Channel 19 */
+#define DCSR20		0x40000050  /* DMA Control / Status Register for Channel 20 */
+#define DCSR21		0x40000054  /* DMA Control / Status Register for Channel 21 */
+#define DCSR22		0x40000058  /* DMA Control / Status Register for Channel 22 */
+#define DCSR23		0x4000005c  /* DMA Control / Status Register for Channel 23 */
+#define DCSR24		0x40000060  /* DMA Control / Status Register for Channel 24 */
+#define DCSR25		0x40000064  /* DMA Control / Status Register for Channel 25 */
+#define DCSR26		0x40000068  /* DMA Control / Status Register for Channel 26 */
+#define DCSR27		0x4000006c  /* DMA Control / Status Register for Channel 27 */
+#define DCSR28		0x40000070  /* DMA Control / Status Register for Channel 28 */
+#define DCSR29		0x40000074  /* DMA Control / Status Register for Channel 29 */
+#define DCSR30		0x40000078  /* DMA Control / Status Register for Channel 30 */
+#define DCSR31		0x4000007c  /* DMA Control / Status Register for Channel 31 */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+#define DCSR(x)		(0x40000000 | ((x) << 2))
+
+#define DCSR_RUN	(1 << 31)	/* Run Bit (read / write) */
+#define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define DCSR_EORIRQEN	(1 << 28)	/* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN	(1 << 27)	/* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN	(1 << 26)	/* STOP on an EOR */
+#define DCSR_SETCMPST	(1 << 25)	/* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST	(1 << 24)	/* Clear Descriptor Compare Status */
+#define DCSR_CMPST	(1 << 10)	/* The Descriptor Compare Status */
+#define DCSR_ENRINTR	(1 << 9)	/* The end of Receive */
+#endif
+
+#define DCSR_REQPEND	(1 << 8)	/* Request Pending (read-only) */
+#define DCSR_STOPSTATE	(1 << 3)	/* Stop State (read-only) */
+#define DCSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write) */
+#define DCSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write) */
+#define DCSR_BUSERR	(1 << 0)	/* Bus Error Interrupt (read / write) */
+
+#define DINT		0x400000f0  /* DMA Interrupt Register */
+
+#define DRCMR0		0x40000100  /* Request to Channel Map Register for DREQ 0 */
+#define DRCMR1		0x40000104  /* Request to Channel Map Register for DREQ 1 */
+#define DRCMR2		0x40000108  /* Request to Channel Map Register for I2S receive Request */
+#define DRCMR3		0x4000010c  /* Request to Channel Map Register for I2S transmit Request */
+#define DRCMR4		0x40000110  /* Request to Channel Map Register for BTUART receive Request */
+#define DRCMR5		0x40000114  /* Request to Channel Map Register for BTUART transmit Request. */
+#define DRCMR6		0x40000118  /* Request to Channel Map Register for FFUART receive Request */
+#define DRCMR7		0x4000011c  /* Request to Channel Map Register for FFUART transmit Request */
+#define DRCMR8		0x40000120  /* Request to Channel Map Register for AC97 microphone Request */
+#define DRCMR9		0x40000124  /* Request to Channel Map Register for AC97 modem receive Request */
+#define DRCMR10		0x40000128  /* Request to Channel Map Register for AC97 modem transmit Request */
+#define DRCMR11		0x4000012c  /* Request to Channel Map Register for AC97 audio receive Request */
+#define DRCMR12		0x40000130  /* Request to Channel Map Register for AC97 audio transmit Request */
+#define DRCMR13		0x40000134  /* Request to Channel Map Register for SSP receive Request */
+#define DRCMR14		0x40000138  /* Request to Channel Map Register for SSP transmit Request */
+#define DRCMR15		0x4000013c  /* Reserved */
+#define DRCMR16		0x40000140  /* Reserved */
+#define DRCMR17		0x40000144  /* Request to Channel Map Register for ICP receive Request */
+#define DRCMR18		0x40000148  /* Request to Channel Map Register for ICP transmit Request */
+#define DRCMR19		0x4000014c  /* Request to Channel Map Register for STUART receive Request */
+#define DRCMR20		0x40000150  /* Request to Channel Map Register for STUART transmit Request */
+#define DRCMR21		0x40000154  /* Request to Channel Map Register for MMC receive Request */
+#define DRCMR22		0x40000158  /* Request to Channel Map Register for MMC transmit Request */
+#define DRCMR23		0x4000015c  /* Reserved */
+#define DRCMR24		0x40000160  /* Reserved */
+#define DRCMR25		0x40000164  /* Request to Channel Map Register for USB endpoint 1 Request */
+#define DRCMR26		0x40000168  /* Request to Channel Map Register for USB endpoint 2 Request */
+#define DRCMR27		0x4000016C  /* Request to Channel Map Register for USB endpoint 3 Request */
+#define DRCMR28		0x40000170  /* Request to Channel Map Register for USB endpoint 4 Request */
+#define DRCMR29		0x40000174  /* Reserved */
+#define DRCMR30		0x40000178  /* Request to Channel Map Register for USB endpoint 6 Request */
+#define DRCMR31		0x4000017C  /* Request to Channel Map Register for USB endpoint 7 Request */
+#define DRCMR32		0x40000180  /* Request to Channel Map Register for USB endpoint 8 Request */
+#define DRCMR33		0x40000184  /* Request to Channel Map Register for USB endpoint 9 Request */
+#define DRCMR34		0x40000188  /* Reserved */
+#define DRCMR35		0x4000018C  /* Request to Channel Map Register for USB endpoint 11 Request */
+#define DRCMR36		0x40000190  /* Request to Channel Map Register for USB endpoint 12 Request */
+#define DRCMR37		0x40000194  /* Request to Channel Map Register for USB endpoint 13 Request */
+#define DRCMR38		0x40000198  /* Request to Channel Map Register for USB endpoint 14 Request */
+#define DRCMR39		0x4000019C  /* Reserved */
+
+#define DRCMR68		       0x40001110  /* Request to Channel Map Register for Camera FIFO 0 Request */
+#define DRCMR69		       0x40001114  /* Request to Channel Map Register for Camera FIFO 1 Request */
+#define DRCMR70		       0x40001118  /* Request to Channel Map Register for Camera FIFO 2 Request */
+
+#define DRCMRRXSADR	DRCMR2
+#define DRCMRTXSADR	DRCMR3
+#define DRCMRRXBTRBR	DRCMR4
+#define DRCMRTXBTTHR	DRCMR5
+#define DRCMRRXFFRBR	DRCMR6
+#define DRCMRTXFFTHR	DRCMR7
+#define DRCMRRXMCDR	DRCMR8
+#define DRCMRRXMODR	DRCMR9
+#define DRCMRTXMODR	DRCMR10
+#define DRCMRRXPCDR	DRCMR11
+#define DRCMRTXPCDR	DRCMR12
+#define DRCMRRXSSDR	DRCMR13
+#define DRCMRTXSSDR	DRCMR14
+#define DRCMRRXICDR	DRCMR17
+#define DRCMRTXICDR	DRCMR18
+#define DRCMRRXSTRBR	DRCMR19
+#define DRCMRTXSTTHR	DRCMR20
+#define DRCMRRXMMC	DRCMR21
+#define DRCMRTXMMC	DRCMR22
+
+#define DRCMR_MAPVLD	(1 << 7)	/* Map Valid (read / write) */
+#define DRCMR_CHLNUM	0x0f		/* mask for Channel Number (read / write) */
+
+#define DDADR0		0x40000200  /* DMA Descriptor Address Register Channel 0 */
+#define DSADR0		0x40000204  /* DMA Source Address Register Channel 0 */
+#define DTADR0		0x40000208  /* DMA Target Address Register Channel 0 */
+#define DCMD0		0x4000020c  /* DMA Command Address Register Channel 0 */
+#define DDADR1		0x40000210  /* DMA Descriptor Address Register Channel 1 */
+#define DSADR1		0x40000214  /* DMA Source Address Register Channel 1 */
+#define DTADR1		0x40000218  /* DMA Target Address Register Channel 1 */
+#define DCMD1		0x4000021c  /* DMA Command Address Register Channel 1 */
+#define DDADR2		0x40000220  /* DMA Descriptor Address Register Channel 2 */
+#define DSADR2		0x40000224  /* DMA Source Address Register Channel 2 */
+#define DTADR2		0x40000228  /* DMA Target Address Register Channel 2 */
+#define DCMD2		0x4000022c  /* DMA Command Address Register Channel 2 */
+#define DDADR3		0x40000230  /* DMA Descriptor Address Register Channel 3 */
+#define DSADR3		0x40000234  /* DMA Source Address Register Channel 3 */
+#define DTADR3		0x40000238  /* DMA Target Address Register Channel 3 */
+#define DCMD3		0x4000023c  /* DMA Command Address Register Channel 3 */
+#define DDADR4		0x40000240  /* DMA Descriptor Address Register Channel 4 */
+#define DSADR4		0x40000244  /* DMA Source Address Register Channel 4 */
+#define DTADR4		0x40000248  /* DMA Target Address Register Channel 4 */
+#define DCMD4		0x4000024c  /* DMA Command Address Register Channel 4 */
+#define DDADR5		0x40000250  /* DMA Descriptor Address Register Channel 5 */
+#define DSADR5		0x40000254  /* DMA Source Address Register Channel 5 */
+#define DTADR5		0x40000258  /* DMA Target Address Register Channel 5 */
+#define DCMD5		0x4000025c  /* DMA Command Address Register Channel 5 */
+#define DDADR6		0x40000260  /* DMA Descriptor Address Register Channel 6 */
+#define DSADR6		0x40000264  /* DMA Source Address Register Channel 6 */
+#define DTADR6		0x40000268  /* DMA Target Address Register Channel 6 */
+#define DCMD6		0x4000026c  /* DMA Command Address Register Channel 6 */
+#define DDADR7		0x40000270  /* DMA Descriptor Address Register Channel 7 */
+#define DSADR7		0x40000274  /* DMA Source Address Register Channel 7 */
+#define DTADR7		0x40000278  /* DMA Target Address Register Channel 7 */
+#define DCMD7		0x4000027c  /* DMA Command Address Register Channel 7 */
+#define DDADR8		0x40000280  /* DMA Descriptor Address Register Channel 8 */
+#define DSADR8		0x40000284  /* DMA Source Address Register Channel 8 */
+#define DTADR8		0x40000288  /* DMA Target Address Register Channel 8 */
+#define DCMD8		0x4000028c  /* DMA Command Address Register Channel 8 */
+#define DDADR9		0x40000290  /* DMA Descriptor Address Register Channel 9 */
+#define DSADR9		0x40000294  /* DMA Source Address Register Channel 9 */
+#define DTADR9		0x40000298  /* DMA Target Address Register Channel 9 */
+#define DCMD9		0x4000029c  /* DMA Command Address Register Channel 9 */
+#define DDADR10		0x400002a0  /* DMA Descriptor Address Register Channel 10 */
+#define DSADR10		0x400002a4  /* DMA Source Address Register Channel 10 */
+#define DTADR10		0x400002a8  /* DMA Target Address Register Channel 10 */
+#define DCMD10		0x400002ac  /* DMA Command Address Register Channel 10 */
+#define DDADR11		0x400002b0  /* DMA Descriptor Address Register Channel 11 */
+#define DSADR11		0x400002b4  /* DMA Source Address Register Channel 11 */
+#define DTADR11		0x400002b8  /* DMA Target Address Register Channel 11 */
+#define DCMD11		0x400002bc  /* DMA Command Address Register Channel 11 */
+#define DDADR12		0x400002c0  /* DMA Descriptor Address Register Channel 12 */
+#define DSADR12		0x400002c4  /* DMA Source Address Register Channel 12 */
+#define DTADR12		0x400002c8  /* DMA Target Address Register Channel 12 */
+#define DCMD12		0x400002cc  /* DMA Command Address Register Channel 12 */
+#define DDADR13		0x400002d0  /* DMA Descriptor Address Register Channel 13 */
+#define DSADR13		0x400002d4  /* DMA Source Address Register Channel 13 */
+#define DTADR13		0x400002d8  /* DMA Target Address Register Channel 13 */
+#define DCMD13		0x400002dc  /* DMA Command Address Register Channel 13 */
+#define DDADR14		0x400002e0  /* DMA Descriptor Address Register Channel 14 */
+#define DSADR14		0x400002e4  /* DMA Source Address Register Channel 14 */
+#define DTADR14		0x400002e8  /* DMA Target Address Register Channel 14 */
+#define DCMD14		0x400002ec  /* DMA Command Address Register Channel 14 */
+#define DDADR15		0x400002f0  /* DMA Descriptor Address Register Channel 15 */
+#define DSADR15		0x400002f4  /* DMA Source Address Register Channel 15 */
+#define DTADR15		0x400002f8  /* DMA Target Address Register Channel 15 */
+#define DCMD15		0x400002fc  /* DMA Command Address Register Channel 15 */
+
+#define DDADR(x)	(0x40000200 | ((x) << 4))
+#define DSADR(x)	(0x40000204 | ((x) << 4))
+#define DTADR(x)	(0x40000208 | ((x) << 4))
+#define DCMD(x)		(0x4000020c | ((x) << 4))
+
+#define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
+#define DDADR_STOP	(1 << 0)	/* Stop (read / write) */
+
+#define DCMD_INCSRCADDR (1 << 31)	/* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR (1 << 30)	/* Target Address Increment Setting. */
+#define DCMD_FLOWSRC	(1 << 29)	/* Flow Control by the source. */
+#define DCMD_FLOWTRG	(1 << 28)	/* Flow Control by the target. */
+#define DCMD_STARTIRQEN (1 << 22)	/* Start Interrupt Enable */
+#define DCMD_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
+#define DCMD_ENDIAN	(1 << 18)	/* Device Endian-ness. */
+#define DCMD_BURST8	(1 << 16)	/* 8 byte burst */
+#define DCMD_BURST16	(2 << 16)	/* 16 byte burst */
+#define DCMD_BURST32	(3 << 16)	/* 32 byte burst */
+#define DCMD_WIDTH1	(1 << 14)	/* 1 byte width */
+#define DCMD_WIDTH2	(2 << 14)	/* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4	(3 << 14)	/* 4 byte width (Word) */
+#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
+
+/* default combinations */
+#define DCMD_RXPCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
+#define DCMD_RXMCDR	(DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
+#define DCMD_TXPCDR	(DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
+
+/******************************************************************************/
+/*
+ * IrSR (Infrared Selection Register)
+ */
+#define IrSR_OFFSET 0x20
+
+#define IrSR_RXPL_NEG_IS_ZERO (1<<4)
+#define IrSR_RXPL_POS_IS_ZERO 0x0
+#define IrSR_TXPL_NEG_IS_ZERO (1<<3)
+#define IrSR_TXPL_POS_IS_ZERO 0x0
+#define IrSR_XMODE_PULSE_1_6  (1<<2)
+#define IrSR_XMODE_PULSE_3_16 0x0
+#define IrSR_RCVEIR_IR_MODE   (1<<1)
+#define IrSR_RCVEIR_UART_MODE 0x0
+#define IrSR_XMITIR_IR_MODE   (1<<0)
+#define IrSR_XMITIR_UART_MODE 0x0
+
+#define IrSR_IR_RECEIVE_ON (\
+		IrSR_RXPL_NEG_IS_ZERO | \
+		IrSR_TXPL_POS_IS_ZERO | \
+		IrSR_XMODE_PULSE_3_16 | \
+		IrSR_RCVEIR_IR_MODE   | \
+		IrSR_XMITIR_UART_MODE)
+
+#define IrSR_IR_TRANSMIT_ON (\
+		IrSR_RXPL_NEG_IS_ZERO | \
+		IrSR_TXPL_POS_IS_ZERO | \
+		IrSR_XMODE_PULSE_3_16 | \
+		IrSR_RCVEIR_UART_MODE | \
+		IrSR_XMITIR_IR_MODE)
+
+/*
+ * Serial Audio Controller
+ */
+/* FIXME the audio defines collide w/ the SA1111 defines.  I don't like these
+ * short defines because there is too much chance of namespace collision
+ */
+#define SACR0		0x40400000  /*  Global Control Register */
+#define SACR1		0x40400004  /*  Serial Audio I 2 S/MSB-Justified Control Register */
+#define SASR0		0x4040000C  /*  Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+#define SAIMR		0x40400014  /*  Serial Audio Interrupt Mask Register */
+#define SAICR		0x40400018  /*  Serial Audio Interrupt Clear Register */
+#define SADIV		0x40400060  /*  Audio Clock Divider Register. */
+#define SADR		0x40400080  /*  Serial Audio Data Register (TX and RX FIFO access Register). */
+
+/*
+ * AC97 Controller registers
+ */
+#define POCR		0x40500000  /* PCM Out Control Register */
+#define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
+
+#define PICR		0x40500004  /* PCM In Control Register */
+#define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
+
+#define MCCR		0x40500008  /* Mic In Control Register */
+#define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
+
+#define GCR		0x4050000C  /* Global Control Register */
+#define GCR_CDONE_IE	(1 << 19)	/* Command Done Interrupt Enable */
+#define GCR_SDONE_IE	(1 << 18)	/* Status Done Interrupt Enable */
+#define GCR_SECRDY_IEN	(1 << 9)	/* Secondary Ready Interrupt Enable */
+#define GCR_PRIRDY_IEN	(1 << 8)	/* Primary Ready Interrupt Enable */
+#define GCR_SECRES_IEN	(1 << 5)	/* Secondary Resume Interrupt Enable */
+#define GCR_PRIRES_IEN	(1 << 4)	/* Primary Resume Interrupt Enable */
+#define GCR_ACLINK_OFF	(1 << 3)	/* AC-link Shut Off */
+#define GCR_WARM_RST	(1 << 2)	/* AC97 Warm Reset */
+#define GCR_COLD_RST	(1 << 1)	/* AC'97 Cold Reset (0 = active) */
+#define GCR_GIE		(1 << 0)	/* Codec GPI Interrupt Enable */
+
+#define POSR		0x40500010  /* PCM Out Status Register */
+#define POSR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define PISR		0x40500014  /* PCM In Status Register */
+#define PISR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define MCSR		0x40500018  /* Mic In Status Register */
+#define MCSR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define GSR		0x4050001C  /* Global Status Register */
+#define GSR_CDONE	(1 << 19)	/* Command Done */
+#define GSR_SDONE	(1 << 18)	/* Status Done */
+#define GSR_RDCS	(1 << 15)	/* Read Completion Status */
+#define GSR_BIT3SLT12	(1 << 14)	/* Bit 3 of slot 12 */
+#define GSR_BIT2SLT12	(1 << 13)	/* Bit 2 of slot 12 */
+#define GSR_BIT1SLT12	(1 << 12)	/* Bit 1 of slot 12 */
+#define GSR_SECRES	(1 << 11)	/* Secondary Resume Interrupt */
+#define GSR_PRIRES	(1 << 10)	/* Primary Resume Interrupt */
+#define GSR_SCR		(1 << 9)	/* Secondary Codec Ready */
+#define GSR_PCR		(1 << 8)	/*  Primary Codec Ready */
+#define GSR_MINT	(1 << 7)	/* Mic In Interrupt */
+#define GSR_POINT	(1 << 6)	/* PCM Out Interrupt */
+#define GSR_PIINT	(1 << 5)	/* PCM In Interrupt */
+#define GSR_MOINT	(1 << 2)	/* Modem Out Interrupt */
+#define GSR_MIINT	(1 << 1)	/* Modem In Interrupt */
+#define GSR_GSCI	(1 << 0)	/* Codec GPI Status Change Interrupt */
+
+#define CAR		0x40500020  /* CODEC Access Register */
+#define CAR_CAIP	(1 << 0)	/* Codec Access In Progress */
+
+#define PCDR		0x40500040  /* PCM FIFO Data Register */
+#define MCDR		0x40500060  /* Mic-in FIFO Data Register */
+
+#define MOCR		0x40500100  /* Modem Out Control Register */
+#define MOCR_FEIE	(1 << 3)	/* FIFO Error */
+
+#define MICR		0x40500108  /* Modem In Control Register */
+#define MICR_FEIE	(1 << 3)	/* FIFO Error */
+
+#define MOSR		0x40500110  /* Modem Out Status Register */
+#define MOSR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define MISR		0x40500118  /* Modem In Status Register */
+#define MISR_FIFOE	(1 << 4)	/* FIFO error */
+
+#define MODR		0x40500140  /* Modem FIFO Data Register */
+
+#define PAC_REG_BASE	0x40500200  /* Primary Audio Codec */
+#define SAC_REG_BASE	0x40500300  /* Secondary Audio Codec */
+#define PMC_REG_BASE	0x40500400  /* Primary Modem Codec */
+#define SMC_REG_BASE	0x40500500  /* Secondary Modem Codec */
+
+
+/*
+ * USB Device Controller
+ */
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+
+#define UDCCR		0x40600000	/* UDC Control Register */
+#define UDCCR_UDE	(1 << 0)		/* UDC enable */
+#define UDCCR_UDA	(1 << 1)		/* UDC active */
+#define UDCCR_RSM	(1 << 2)		/* Device resume */
+#define UDCCR_EMCE	(1 << 3)		/* Endpoint Memory Configuration Error */
+#define UDCCR_SMAC	(1 << 4)		/* Switch Endpoint Memory to Active Configuration */
+#define UDCCR_RESIR	(1 << 29)		/* Resume interrupt request */
+#define UDCCR_SUSIR	(1 << 28)		/* Suspend interrupt request */
+#define UDCCR_SM	(1 << 28)		/* Suspend interrupt mask */
+#define UDCCR_RSTIR	(1 << 27)		/* Reset interrupt request */
+#define UDCCR_REM	(1 << 27)		/* Reset interrupt mask */
+#define UDCCR_RM	(1 << 29)		/* resume interrupt mask */
+#define UDCCR_SRM	(UDCCR_SM|UDCCR_RM)
+#define UDCCR_OEN	(1 << 31)		/* On-the-Go Enable */
+#define UDCCR_AALTHNP	(1 << 30)		/* A-device Alternate Host Negotiation Protocol Port Support */
+#define UDCCR_AHNP	(1 << 29)		/* A-device Host Negotiation Protocol Support */
+#define UDCCR_BHNP	(1 << 28)		/* B-device Host Negotiation Protocol Enable */
+#define UDCCR_DWRE	(1 << 16)		/* Device Remote Wake-up Enable */
+#define UDCCR_ACN	(0x03 << 11)		/* Active UDC configuration Number */
+#define UDCCR_ACN_S	11
+#define UDCCR_AIN	(0x07 << 8)		/* Active UDC interface Number */
+#define UDCCR_AIN_S	8
+#define UDCCR_AAISN	(0x07 << 5)		/* Active UDC Alternate Interface  Setting Number */
+#define UDCCR_AAISN_S	5
+
+#define UDCCS0		0x40600100	/* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0_OPR	(1 << 0)		/* OUT packet ready */
+#define UDCCS0_IPR	(1 << 1)		/* IN packet ready */
+#define UDCCS0_FTF	(1 << 2)		/* Flush Tx FIFO */
+#define UDCCS0_DRWF	(1 << 16)		/* Device remote wakeup feature */
+#define UDCCS0_SST	(1 << 4)		/* Sent stall */
+#define UDCCS0_FST	(1 << 5)		/* Force stall */
+#define UDCCS0_RNE	(1 << 6)		/* Receive FIFO no empty */
+#define UDCCS0_SA	(1 << 7)		/* Setup active */
+
+/* Bulk IN - Endpoint 1,6,11 */
+#define UDCCS1		0x40600104  /* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS6		0x40600028  /* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS11		0x4060003C  /* UDC Endpoint 11 (IN) Control/Status Register */
+
+#define UDCCS_BI_TFS	(1 << 0)	/* Transmit FIFO service */
+#define UDCCS_BI_TPC	(1 << 1)	/* Transmit packet complete */
+#define UDCCS_BI_FTF	(1 << 8)	/* Flush Tx FIFO */
+#define UDCCS_BI_TUR	(1 << 3)	/* Transmit FIFO underrun */
+#define UDCCS_BI_SST	(1 << 4)	/* Sent stall */
+#define UDCCS_BI_FST	(1 << 5)	/* Force stall */
+#define UDCCS_BI_TSP	(1 << 7)	/* Transmit short packet */
+
+/* Bulk OUT - Endpoint 2,7,12 */
+#define UDCCS2		0x40600108  /* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS7		0x4060002C  /* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS12		0x40600040  /* UDC Endpoint 12 (OUT) Control/Status Register */
+
+#define UDCCS_BO_RFS	(1 << 0)	/* Receive FIFO service */
+#define UDCCS_BO_RPC	(1 << 1)	/* Receive packet complete */
+#define UDCCS_BO_DME	(1 << 3)	/* DMA enable */
+#define UDCCS_BO_SST	(1 << 4)	/* Sent stall */
+#define UDCCS_BO_FST	(1 << 5)	/* Force stall */
+#define UDCCS_BO_RNE	(1 << 6)	/* Receive FIFO not empty */
+#define UDCCS_BO_RSP	(1 << 7)	/* Receive short packet */
+
+/* Isochronous IN - Endpoint 3,8,13 */
+#define UDCCS3		0x4060001C  /* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS8		0x40600030  /* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS13		0x40600044  /* UDC Endpoint 13 (IN) Control/Status Register */
+
+#define UDCCS_II_TFS	(1 << 0)	/* Transmit FIFO service */
+#define UDCCS_II_TPC	(1 << 1)	/* Transmit packet complete */
+#define UDCCS_II_FTF	(1 << 2)	/* Flush Tx FIFO */
+#define UDCCS_II_TUR	(1 << 3)	/* Transmit FIFO underrun */
+#define UDCCS_II_TSP	(1 << 7)	/* Transmit short packet */
+
+/* Isochronous OUT - Endpoint 4,9,14 */
+#define UDCCS4		0x40600020  /* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS9		0x40600034  /* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS14		0x40600048  /* UDC Endpoint 14 (OUT) Control/Status Register */
+
+#define UDCCS_IO_RFS	(1 << 0)	/* Receive FIFO service */
+#define UDCCS_IO_RPC	(1 << 1)	/* Receive packet complete */
+#define UDCCS_IO_ROF	(1 << 3)	/* Receive overflow */
+#define UDCCS_IO_DME	(1 << 3)	/* DMA enable */
+#define UDCCS_IO_RNE	(1 << 6)	/* Receive FIFO not empty */
+#define UDCCS_IO_RSP	(1 << 7)	/* Receive short packet */
+
+/* Interrupt IN - Endpoint 5,10,15 */
+#define UDCCS5		0x40600024  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS10		0x40600038  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS15		0x4060004C  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
+
+#define UDCCS_INT_TFS	(1 << 0)	/* Transmit FIFO service */
+#define UDCCS_INT_TPC	(1 << 1)	/* Transmit packet complete */
+#define UDCCS_INT_FTF	(1 << 2)	/* Flush Tx FIFO */
+#define UDCCS_INT_TUR	(1 << 3)	/* Transmit FIFO underrun */
+#define UDCCS_INT_SST	(1 << 4)	/* Sent stall */
+#define UDCCS_INT_FST	(1 << 5)	/* Force stall */
+#define UDCCS_INT_TSP	(1 << 7)	/* Transmit short packet */
+
+#define UFNRH		0x40600060  /* UDC Frame Number Register High */
+#define UFNRL		0x40600014  /* UDC Frame Number Register Low */
+#define UBCR2		0x40600208  /* UDC Byte Count Reg 2 */
+#define UBCR4		0x4060006c  /* UDC Byte Count Reg 4 */
+#define UBCR7		0x40600070  /* UDC Byte Count Reg 7 */
+#define UBCR9		0x40600074  /* UDC Byte Count Reg 9 */
+#define UBCR12		0x40600078  /* UDC Byte Count Reg 12 */
+#define UBCR14		0x4060007c  /* UDC Byte Count Reg 14 */
+#define UDDR0		0x40600300  /* UDC Endpoint 0 Data Register */
+#define UDDR1		0x40600304  /* UDC Endpoint 1 Data Register */
+#define UDDR2		0x40600308  /* UDC Endpoint 2 Data Register */
+#define UDDR3		0x40600200  /* UDC Endpoint 3 Data Register */
+#define UDDR4		0x40600400  /* UDC Endpoint 4 Data Register */
+#define UDDR5		0x406000A0  /* UDC Endpoint 5 Data Register */
+#define UDDR6		0x40600600  /* UDC Endpoint 6 Data Register */
+#define UDDR7		0x40600680  /* UDC Endpoint 7 Data Register */
+#define UDDR8		0x40600700  /* UDC Endpoint 8 Data Register */
+#define UDDR9		0x40600900  /* UDC Endpoint 9 Data Register */
+#define UDDR10		0x406000C0  /* UDC Endpoint 10 Data Register */
+#define UDDR11		0x40600B00  /* UDC Endpoint 11 Data Register */
+#define UDDR12		0x40600B80  /* UDC Endpoint 12 Data Register */
+#define UDDR13		0x40600C00  /* UDC Endpoint 13 Data Register */
+#define UDDR14		0x40600E00  /* UDC Endpoint 14 Data Register */
+#define UDDR15		0x406000E0  /* UDC Endpoint 15 Data Register */
+
+#define UICR0		0x40600004  /* UDC Interrupt Control Register 0 */
+
+#define UICR0_IM0	(1 << 0)	/* Interrupt mask ep 0 */
+#define UICR0_IM1	(1 << 1)	/* Interrupt mask ep 1 */
+#define UICR0_IM2	(1 << 2)	/* Interrupt mask ep 2 */
+#define UICR0_IM3	(1 << 3)	/* Interrupt mask ep 3 */
+#define UICR0_IM4	(1 << 4)	/* Interrupt mask ep 4 */
+#define UICR0_IM5	(1 << 5)	/* Interrupt mask ep 5 */
+#define UICR0_IM6	(1 << 6)	/* Interrupt mask ep 6 */
+#define UICR0_IM7	(1 << 7)	/* Interrupt mask ep 7 */
+
+#define UICR1		0x40600008  /* UDC Interrupt Control Register 1 */
+
+#define UICR1_IM8	(1 << 0)	/* Interrupt mask ep 8 */
+#define UICR1_IM9	(1 << 1)	/* Interrupt mask ep 9 */
+#define UICR1_IM10	(1 << 2)	/* Interrupt mask ep 10 */
+#define UICR1_IM11	(1 << 3)	/* Interrupt mask ep 11 */
+#define UICR1_IM12	(1 << 4)	/* Interrupt mask ep 12 */
+#define UICR1_IM13	(1 << 5)	/* Interrupt mask ep 13 */
+#define UICR1_IM14	(1 << 6)	/* Interrupt mask ep 14 */
+#define UICR1_IM15	(1 << 7)	/* Interrupt mask ep 15 */
+
+#define USIR0		0x4060000C  /* UDC Status Interrupt Register 0 */
+
+#define USIR0_IR0	(1 << 0)	/* Interrup request ep 0 */
+#define USIR0_IR1	(1 << 2)	/* Interrup request ep 1 */
+#define USIR0_IR2	(1 << 4)	/* Interrup request ep 2 */
+#define USIR0_IR3	(1 << 3)	/* Interrup request ep 3 */
+#define USIR0_IR4	(1 << 4)	/* Interrup request ep 4 */
+#define USIR0_IR5	(1 << 5)	/* Interrup request ep 5 */
+#define USIR0_IR6	(1 << 6)	/* Interrup request ep 6 */
+#define USIR0_IR7	(1 << 7)	/* Interrup request ep 7 */
+
+#define USIR1		0x40600010  /* UDC Status Interrupt Register 1 */
+
+#define USIR1_IR8	(1 << 0)	/* Interrup request ep 8 */
+#define USIR1_IR9	(1 << 1)	/* Interrup request ep 9 */
+#define USIR1_IR10	(1 << 2)	/* Interrup request ep 10 */
+#define USIR1_IR11	(1 << 3)	/* Interrup request ep 11 */
+#define USIR1_IR12	(1 << 4)	/* Interrup request ep 12 */
+#define USIR1_IR13	(1 << 5)	/* Interrup request ep 13 */
+#define USIR1_IR14	(1 << 6)	/* Interrup request ep 14 */
+#define USIR1_IR15	(1 << 7)	/* Interrup request ep 15 */
+
+
+#define UDCICR0         0x40600004	/* UDC Interrupt Control Register0 */
+#define UDCICR1         0x40600008	/* UDC Interrupt Control Register1 */
+#define UDCICR_FIFOERR	(1 << 1)			/* FIFO Error interrupt for EP */
+#define UDCICR_PKTCOMPL (1 << 0)			/* Packet Complete interrupt for EP */
+
+#define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCICR1_IECC	(1 << 31)	/* IntEn - Configuration Change */
+#define UDCICR1_IESOF	(1 << 30)	/* IntEn - Start of Frame */
+#define UDCICR1_IERU	(1 << 29)	/* IntEn - Resume */
+#define UDCICR1_IESU	(1 << 28)	/* IntEn - Suspend */
+#define UDCICR1_IERS	(1 << 27)	/* IntEn - Reset */
+
+#define UDCISR0         0x4060000C /* UDC Interrupt Status Register 0 */
+#define UDCISR1         0x40600010 /* UDC Interrupt Status Register 1 */
+#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCISR1_IRCC	(1 << 31)	/* IntEn - Configuration Change */
+#define UDCISR1_IRSOF	(1 << 30)	/* IntEn - Start of Frame */
+#define UDCISR1_IRRU	(1 << 29)	/* IntEn - Resume */
+#define UDCISR1_IRSU	(1 << 28)	/* IntEn - Suspend */
+#define UDCISR1_IRRS	(1 << 27)	/* IntEn - Reset */
+
+
+#define UDCFNR			0x40600014 /* UDC Frame Number Register */
+#define UDCOTGICR		0x40600018 /* UDC On-The-Go interrupt control */
+#define UDCOTGICR_IESF		(1 << 24)	/* OTG SET_FEATURE command recvd */
+#define UDCOTGICR_IEXR		(1 << 17)	/* Extra Transciever Interrupt Rising Edge Interrupt Enable */
+#define UDCOTGICR_IEXF		(1 << 16)	/* Extra Transciever Interrupt Falling Edge Interrupt Enable */
+#define UDCOTGICR_IEVV40R	(1 << 9)	/* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */
+#define UDCOTGICR_IEVV40F	(1 << 8)	/* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */
+#define UDCOTGICR_IEVV44R	(1 << 7)	/* OTG Vbus Valid 4.4V Rising Edge  Interrupt Enable */
+#define UDCOTGICR_IEVV44F	(1 << 6)	/* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */
+#define UDCOTGICR_IESVR		(1 << 5)	/* OTG Session Valid Rising Edge Interrupt Enable */
+#define UDCOTGICR_IESVF		(1 << 4)	/* OTG Session Valid Falling Edge Interrupt Enable */
+#define UDCOTGICR_IESDR		(1 << 3)	/* OTG A-Device SRP Detect Rising Edge Interrupt Enable */
+#define UDCOTGICR_IESDF		(1 << 2)	/* OTG A-Device SRP Detect Falling  Edge Interrupt Enable */
+#define UDCOTGICR_IEIDR		(1 << 1)	/* OTG ID Change Rising Edge Interrupt Enable */
+#define UDCOTGICR_IEIDF		(1 << 0)	/* OTG ID Change Falling Edge Interrupt Enable */
+
+#define UDCCSN(x)	(0x40600100 + ((x) << 2))
+#define UDCCSR0		0x40600100 /* UDC Control/Status register - Endpoint 0 */
+
+#define UDCCSR0_SA	(1 << 7)	/* Setup Active */
+#define UDCCSR0_RNE	(1 << 6)	/* Receive FIFO Not Empty */
+#define UDCCSR0_FST	(1 << 5)	/* Force Stall */
+#define UDCCSR0_SST	(1 << 4)	/* Sent Stall */
+#define UDCCSR0_DME	(1 << 3)	/* DMA Enable */
+#define UDCCSR0_FTF	(1 << 2)	/* Flush Transmit FIFO */
+#define UDCCSR0_IPR	(1 << 1)	/* IN Packet Ready */
+#define UDCCSR0_OPC	(1 << 0)	/* OUT Packet Complete */
+
+#define UDCCSRA         0x40600104 /* UDC Control/Status register - Endpoint A */
+#define UDCCSRB         0x40600108 /* UDC Control/Status register - Endpoint B */
+#define UDCCSRC         0x4060010C /* UDC Control/Status register - Endpoint C */
+#define UDCCSRD         0x40600110 /* UDC Control/Status register - Endpoint D */
+#define UDCCSRE         0x40600114 /* UDC Control/Status register - Endpoint E */
+#define UDCCSRF         0x40600118 /* UDC Control/Status register - Endpoint F */
+#define UDCCSRG         0x4060011C /* UDC Control/Status register - Endpoint G */
+#define UDCCSRH         0x40600120 /* UDC Control/Status register - Endpoint H */
+#define UDCCSRI         0x40600124 /* UDC Control/Status register - Endpoint I */
+#define UDCCSRJ         0x40600128 /* UDC Control/Status register - Endpoint J */
+#define UDCCSRK         0x4060012C /* UDC Control/Status register - Endpoint K */
+#define UDCCSRL         0x40600130 /* UDC Control/Status register - Endpoint L */
+#define UDCCSRM         0x40600134 /* UDC Control/Status register - Endpoint M */
+#define UDCCSRN         0x40600138 /* UDC Control/Status register - Endpoint N */
+#define UDCCSRP         0x4060013C /* UDC Control/Status register - Endpoint P */
+#define UDCCSRQ         0x40600140 /* UDC Control/Status register - Endpoint Q */
+#define UDCCSRR         0x40600144 /* UDC Control/Status register - Endpoint R */
+#define UDCCSRS         0x40600148 /* UDC Control/Status register - Endpoint S */
+#define UDCCSRT         0x4060014C /* UDC Control/Status register - Endpoint T */
+#define UDCCSRU         0x40600150 /* UDC Control/Status register - Endpoint U */
+#define UDCCSRV         0x40600154 /* UDC Control/Status register - Endpoint V */
+#define UDCCSRW         0x40600158 /* UDC Control/Status register - Endpoint W */
+#define UDCCSRX         0x4060015C /* UDC Control/Status register - Endpoint X */
+
+#define UDCCSR_DPE	(1 << 9)	/* Data Packet Error */
+#define UDCCSR_FEF	(1 << 8)	/* Flush Endpoint FIFO */
+#define UDCCSR_SP	(1 << 7)	/* Short Packet Control/Status */
+#define UDCCSR_BNE	(1 << 6)	/* Buffer Not Empty (IN endpoints) */
+#define UDCCSR_BNF	(1 << 6)	/* Buffer Not Full (OUT endpoints) */
+#define UDCCSR_FST	(1 << 5)	/* Force STALL */
+#define UDCCSR_SST	(1 << 4)	/* Sent STALL */
+#define UDCCSR_DME	(1 << 3)	/* DMA Enable */
+#define UDCCSR_TRN	(1 << 2)	/* Tx/Rx NAK */
+#define UDCCSR_PC	(1 << 1)	/* Packet Complete */
+#define UDCCSR_FS	(1 << 0)	/* FIFO needs service */
+
+#define UDCBCN(x)	(0x40600200 + ((x) << 2))
+#define UDCBCR0         0x40600200 /* Byte Count Register - EP0 */
+#define UDCBCRA         0x40600204 /* Byte Count Register - EPA */
+#define UDCBCRB         0x40600208 /* Byte Count Register - EPB */
+#define UDCBCRC         0x4060020C /* Byte Count Register - EPC */
+#define UDCBCRD         0x40600210 /* Byte Count Register - EPD */
+#define UDCBCRE         0x40600214 /* Byte Count Register - EPE */
+#define UDCBCRF         0x40600218 /* Byte Count Register - EPF */
+#define UDCBCRG         0x4060021C /* Byte Count Register - EPG */
+#define UDCBCRH         0x40600220 /* Byte Count Register - EPH */
+#define UDCBCRI         0x40600224 /* Byte Count Register - EPI */
+#define UDCBCRJ         0x40600228 /* Byte Count Register - EPJ */
+#define UDCBCRK         0x4060022C /* Byte Count Register - EPK */
+#define UDCBCRL         0x40600230 /* Byte Count Register - EPL */
+#define UDCBCRM         0x40600234 /* Byte Count Register - EPM */
+#define UDCBCRN         0x40600238 /* Byte Count Register - EPN */
+#define UDCBCRP         0x4060023C /* Byte Count Register - EPP */
+#define UDCBCRQ         0x40600240 /* Byte Count Register - EPQ */
+#define UDCBCRR         0x40600244 /* Byte Count Register - EPR */
+#define UDCBCRS         0x40600248 /* Byte Count Register - EPS */
+#define UDCBCRT         0x4060024C /* Byte Count Register - EPT */
+#define UDCBCRU         0x40600250 /* Byte Count Register - EPU */
+#define UDCBCRV         0x40600254 /* Byte Count Register - EPV */
+#define UDCBCRW         0x40600258 /* Byte Count Register - EPW */
+#define UDCBCRX         0x4060025C /* Byte Count Register - EPX */
+
+#define UDCDN(x)	(0x40600300 + ((x) << 2))
+#define UDCDR0          0x40600300 /* Data Register - EP0 */
+#define UDCDRA          0x40600304 /* Data Register - EPA */
+#define UDCDRB          0x40600308 /* Data Register - EPB */
+#define UDCDRC          0x4060030C /* Data Register - EPC */
+#define UDCDRD          0x40600310 /* Data Register - EPD */
+#define UDCDRE          0x40600314 /* Data Register - EPE */
+#define UDCDRF          0x40600318 /* Data Register - EPF */
+#define UDCDRG          0x4060031C /* Data Register - EPG */
+#define UDCDRH          0x40600320 /* Data Register - EPH */
+#define UDCDRI          0x40600324 /* Data Register - EPI */
+#define UDCDRJ          0x40600328 /* Data Register - EPJ */
+#define UDCDRK          0x4060032C /* Data Register - EPK */
+#define UDCDRL          0x40600330 /* Data Register - EPL */
+#define UDCDRM          0x40600334 /* Data Register - EPM */
+#define UDCDRN          0x40600338 /* Data Register - EPN */
+#define UDCDRP          0x4060033C /* Data Register - EPP */
+#define UDCDRQ          0x40600340 /* Data Register - EPQ */
+#define UDCDRR          0x40600344 /* Data Register - EPR */
+#define UDCDRS          0x40600348 /* Data Register - EPS */
+#define UDCDRT          0x4060034C /* Data Register - EPT */
+#define UDCDRU          0x40600350 /* Data Register - EPU */
+#define UDCDRV          0x40600354 /* Data Register - EPV */
+#define UDCDRW          0x40600358 /* Data Register - EPW */
+#define UDCDRX          0x4060035C /* Data Register - EPX */
+
+#define UDCCN(x)	(0x40600400 + ((x) << 2))
+#define UDCCRA          0x40600404 /* Configuration register EPA */
+#define UDCCRB          0x40600408 /* Configuration register EPB */
+#define UDCCRC          0x4060040C /* Configuration register EPC */
+#define UDCCRD          0x40600410 /* Configuration register EPD */
+#define UDCCRE          0x40600414 /* Configuration register EPE */
+#define UDCCRF          0x40600418 /* Configuration register EPF */
+#define UDCCRG          0x4060041C /* Configuration register EPG */
+#define UDCCRH          0x40600420 /* Configuration register EPH */
+#define UDCCRI          0x40600424 /* Configuration register EPI */
+#define UDCCRJ          0x40600428 /* Configuration register EPJ */
+#define UDCCRK          0x4060042C /* Configuration register EPK */
+#define UDCCRL          0x40600430 /* Configuration register EPL */
+#define UDCCRM          0x40600434 /* Configuration register EPM */
+#define UDCCRN          0x40600438 /* Configuration register EPN */
+#define UDCCRP          0x4060043C /* Configuration register EPP */
+#define UDCCRQ          0x40600440 /* Configuration register EPQ */
+#define UDCCRR          0x40600444 /* Configuration register EPR */
+#define UDCCRS          0x40600448 /* Configuration register EPS */
+#define UDCCRT          0x4060044C /* Configuration register EPT */
+#define UDCCRU          0x40600450 /* Configuration register EPU */
+#define UDCCRV          0x40600454 /* Configuration register EPV */
+#define UDCCRW          0x40600458 /* Configuration register EPW */
+#define UDCCRX          0x4060045C /* Configuration register EPX */
+
+#define UDCCONR_CN	(0x03 << 25)	/* Configuration Number */
+#define UDCCONR_CN_S	(25)
+#define UDCCONR_IN	(0x07 << 22)	/* Interface Number */
+#define UDCCONR_IN_S	(22)
+#define UDCCONR_AISN	(0x07 << 19)	/* Alternate Interface Number */
+#define UDCCONR_AISN_S	(19)
+#define UDCCONR_EN	(0x0f << 15)	/* Endpoint Number */
+#define UDCCONR_EN_S	(15)
+#define UDCCONR_ET	(0x03 << 13)	/* Endpoint Type: */
+#define UDCCONR_ET_S	(13)
+#define UDCCONR_ET_INT	(0x03 << 13)	/* Interrupt */
+#define UDCCONR_ET_BULK	(0x02 << 13)	/* Bulk */
+#define UDCCONR_ET_ISO	(0x01 << 13)	/* Isochronous */
+#define UDCCONR_ET_NU	(0x00 << 13)	/* Not used */
+#define UDCCONR_ED	(1 << 12)	/* Endpoint Direction */
+#define UDCCONR_MPS	(0x3ff << 2)	/* Maximum Packet Size */
+#define UDCCONR_MPS_S	(2)
+#define UDCCONR_DE	(1 << 1)	/* Double Buffering Enable */
+#define UDCCONR_EE	(1 << 0)	/* Endpoint Enable */
+
+
+#define UDC_INT_FIFOERROR	(0x2)
+#define UDC_INT_PACKETCMP	(0x1)
+#define UDC_FNR_MASK		(0x7ff)
+#define UDCCSR_WR_MASK		(UDCCSR_DME|UDCCSR_FST)
+#define UDC_BCR_MASK		(0x3ff)
+
+#endif /* CONFIG_CPU_PXA27X */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+
+/******************************************************************************/
+/*
+ * USB Host Controller
+ */
+#define OHCI_REGS_BASE	0x4C000000	/* required for ohci driver */
+#define UHCREV		0x4C000000
+#define UHCHCON		0x4C000004
+#define UHCCOMS		0x4C000008
+#define UHCINTS		0x4C00000C
+#define UHCINTE		0x4C000010
+#define UHCINTD		0x4C000014
+#define UHCHCCA		0x4C000018
+#define UHCPCED		0x4C00001C
+#define UHCCHED		0x4C000020
+#define UHCCCED		0x4C000024
+#define UHCBHED		0x4C000028
+#define UHCBCED		0x4C00002C
+#define UHCDHEAD	0x4C000030
+#define UHCFMI		0x4C000034
+#define UHCFMR		0x4C000038
+#define UHCFMN		0x4C00003C
+#define UHCPERS		0x4C000040
+#define UHCLST		0x4C000044
+#define UHCRHDA		0x4C000048
+#define UHCRHDB		0x4C00004C
+#define UHCRHS		0x4C000050
+#define UHCRHPS1	0x4C000054
+#define UHCRHPS2	0x4C000058
+#define UHCRHPS3	0x4C00005C
+#define UHCSTAT		0x4C000060
+#define UHCHR		0x4C000064
+#define UHCHIE		0x4C000068
+#define UHCHIT		0x4C00006C
+
+#define UHCCOMS_HCR	(1<<0)
+
+#define UHCHR_FSBIR	(1<<0)
+#define UHCHR_FHR	(1<<1)
+#define UHCHR_CGR	(1<<2)
+#define UHCHR_SSDC	(1<<3)
+#define UHCHR_UIT	(1<<4)
+#define UHCHR_SSE	(1<<5)
+#define UHCHR_PSPL	(1<<6)
+#define UHCHR_PCPL	(1<<7)
+#define UHCHR_SSEP0	(1<<9)
+#define UHCHR_SSEP1	(1<<10)
+#define UHCHR_SSEP2	(1<<11)
+
+#define UHCHIE_UPRIE	(1<<13)
+#define UHCHIE_UPS2IE	(1<<12)
+#define UHCHIE_UPS1IE	(1<<11)
+#define UHCHIE_TAIE	(1<<10)
+#define UHCHIE_HBAIE	(1<<8)
+#define UHCHIE_RWIE	(1<<7)
+
+#define UP2OCR		0x40600020
+
+#define UP2OCR_HXOE	(1<<17)
+#define UP2OCR_HXS	(1<<16)
+#define UP2OCR_IDON	(1<<10)
+#define UP2OCR_EXSUS	(1<<9)
+#define UP2OCR_EXSP	(1<<8)
+#define UP2OCR_DMSTATE	(1<<7)
+#define UP2OCR_VPM	(1<<6)
+#define UP2OCR_DPSTATE	(1<<5)
+#define UP2OCR_DPPUE	(1<<4)
+#define UP2OCR_DMPDE	(1<<3)
+#define UP2OCR_DPPDE	(1<<2)
+#define UP2OCR_CPVPE	(1<<1)
+#define UP2OCR_CPVEN	(1<<0)
+
+#endif	/* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+/******************************************************************************/
+/*
+ * Fast Infrared Communication Port
+ */
+#define ICCR0		0x40800000  /* ICP Control Register 0 */
+#define ICCR1		0x40800004  /* ICP Control Register 1 */
+#define ICCR2		0x40800008  /* ICP Control Register 2 */
+#define ICDR		0x4080000c  /* ICP Data Register */
+#define ICSR0		0x40800014  /* ICP Status Register 0 */
+#define ICSR1		0x40800018  /* ICP Status Register 1 */
+
+/*
+ * Real Time Clock
+ */
+#define RCNR		0x40900000  /* RTC Count Register */
+#define RTAR		0x40900004  /* RTC Alarm Register */
+#define RTSR		0x40900008  /* RTC Status Register */
+#define RTTR		0x4090000C  /* RTC Timer Trim Register */
+#define RDAR1		0x40900018  /* Wristwatch Day Alarm Reg 1 */
+#define RDAR2		0x40900020  /* Wristwatch Day Alarm Reg 2 */
+#define RYAR1		0x4090001C  /* Wristwatch Year Alarm Reg 1 */
+#define RYAR2		0x40900024  /* Wristwatch Year Alarm Reg 2 */
+#define SWAR1		0x4090002C  /* Stopwatch Alarm Register 1 */
+#define SWAR2		0x40900030  /* Stopwatch Alarm Register 2 */
+#define PIAR		0x40900038  /* Periodic Interrupt Alarm Register */
+#define RDCR		0x40900010  /* RTC Day Count Register. */
+#define RYCR		0x40900014  /* RTC Year Count Register. */
+#define SWCR		0x40900028  /* Stopwatch Count Register */
+#define RTCPICR		0x40900034  /* Periodic Interrupt Counter Register */
+
+#define RTSR_PICE	(1 << 15)	/* Peridoc interrupt count enable */
+#define RTSR_PIALE	(1 << 14)	/* Peridoc interrupt Alarm enable */
+#define RTSR_PIAL	(1 << 13)	/* Peridoc  interrupt Alarm status */
+#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
+#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
+#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
+#define RTSR_AL		(1 << 0)	/* RTC alarm detected */
+
+/******************************************************************************/
+/*
+ * OS Timer & Match Registers
+ */
+#define OSMR0		0x40A00000  /* OS Timer Match Register 0 */
+#define OSMR1		0x40A00004  /* OS Timer Match Register 1 */
+#define OSMR2		0x40A00008  /* OS Timer Match Register 2 */
+#define OSMR3		0x40A0000C  /* OS Timer Match Register 3 */
+#define OSCR		0x40A00010  /* OS Timer Counter Register */
+#define OSSR		0x40A00014  /* OS Timer Status Register */
+#define OWER		0x40A00018  /* OS Timer Watchdog Enable Register */
+#define OIER		0x40A0001C  /* OS Timer Interrupt Enable Register */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define OSCR4		0x40A00040  /* OS Timer Counter Register 4 */
+#define OSCR5		0x40A00044  /* OS Timer Counter Register 5 */
+#define OSCR6		0x40A00048  /* OS Timer Counter Register 6 */
+#define OSCR7		0x40A0004C  /* OS Timer Counter Register 7 */
+#define OSCR8		0x40A00050  /* OS Timer Counter Register 8 */
+#define OSCR9		0x40A00054  /* OS Timer Counter Register 9 */
+#define OSCR10		0x40A00058  /* OS Timer Counter Register 10 */
+#define OSCR11		0x40A0005C  /* OS Timer Counter Register 11 */
+
+#define OSMR4		0x40A00080  /* OS Timer Match Register 4 */
+#define OSMR5		0x40A00084  /* OS Timer Match Register 5 */
+#define OSMR6		0x40A00088  /* OS Timer Match Register 6 */
+#define OSMR7		0x40A0008C  /* OS Timer Match Register 7 */
+#define OSMR8		0x40A00090  /* OS Timer Match Register 8 */
+#define OSMR9		0x40A00094  /* OS Timer Match Register 9 */
+#define OSMR10		0x40A00098  /* OS Timer Match Register 10 */
+#define OSMR11		0x40A0009C  /* OS Timer Match Register 11 */
+
+#define OMCR4		0x40A000C0  /* OS Match Control Register 4 */
+#define OMCR5		0x40A000C4  /* OS Match Control Register 5 */
+#define OMCR6		0x40A000C8  /* OS Match Control Register 6 */
+#define OMCR7		0x40A000CC  /* OS Match Control Register 7 */
+#define OMCR8		0x40A000D0  /* OS Match Control Register 8 */
+#define OMCR9		0x40A000D4  /* OS Match Control Register 9 */
+#define OMCR10		0x40A000D8  /* OS Match Control Register 10 */
+#define OMCR11		0x40A000DC  /* OS Match Control Register 11 */
+
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+#define OSSR_M4		(1 << 4)	/* Match status channel 4 */
+#define OSSR_M3		(1 << 3)	/* Match status channel 3 */
+#define OSSR_M2		(1 << 2)	/* Match status channel 2 */
+#define OSSR_M1		(1 << 1)	/* Match status channel 1 */
+#define OSSR_M0		(1 << 0)	/* Match status channel 0 */
+
+#define OWER_WME	(1 << 0)	/* Watchdog Match Enable */
+
+#define OIER_E4		(1 << 4)	/* Interrupt enable channel 4 */
+#define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */
+#define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */
+#define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
+#define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */
+
+#define	OSCR_CLK_FREQ	3250
+
+/******************************************************************************/
+/*
+ * Core Clock
+ */
+
+#if defined(CONFIG_CPU_MONAHANS)
+#define ACCR		0x41340000  /* Application Subsystem Clock Configuration Register */
+#define ACSR		0x41340004  /* Application Subsystem Clock Status Register */
+#define AICSR		0x41340008  /* Application Subsystem Interrupt Control/Status Register */
+#define CKENA		0x4134000C  /* A Clock Enable Register */
+#define CKENB		0x41340010  /* B Clock Enable Register */
+#define AC97_DIV	0x41340014  /* AC97 clock divisor value register */
+
+#define ACCR_SMC_MASK	0x03800000	/* Static Memory Controller Frequency Select */
+#define ACCR_SRAM_MASK	0x000c0000	/* SRAM Controller Frequency Select */
+#define ACCR_FC_MASK	0x00030000	/* Frequency Change Frequency Select */
+#define ACCR_HSIO_MASK	0x0000c000	/* High Speed IO Frequency Select */
+#define ACCR_DDR_MASK	0x00003000	/* DDR Memory Controller Frequency Select */
+#define ACCR_XN_MASK	0x00000700	/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define ACCR_XL_MASK	0x0000001f	/* Crystal Frequency to Memory Frequency Multiplier */
+#define ACCR_XPDIS	(1 << 31)
+#define ACCR_SPDIS	(1 << 30)
+#define ACCR_13MEND1	(1 << 27)
+#define ACCR_D0CS	(1 << 26)
+#define ACCR_13MEND2	(1 << 21)
+#define ACCR_PCCE	(1 << 11)
+
+#define CKENA_30_MSL0	(1 << 30)	/* MSL0 Interface Unit Clock Enable */
+#define CKENA_29_SSP4	(1 << 29)	/* SSP3 Unit Clock Enable */
+#define CKENA_28_SSP3	(1 << 28)	/* SSP2 Unit Clock Enable */
+#define CKENA_27_SSP2	(1 << 27)	/* SSP1 Unit Clock Enable */
+#define CKENA_26_SSP1	(1 << 26)	/* SSP0 Unit Clock Enable */
+#define CKENA_25_TSI	(1 << 25)	/* TSI Clock Enable */
+#define CKENA_24_AC97	(1 << 24)	/* AC97 Unit Clock Enable */
+#define CKENA_23_STUART	(1 << 23)	/* STUART Unit Clock Enable */
+#define CKENA_22_FFUART	(1 << 22)	/* FFUART Unit Clock Enable */
+#define CKENA_21_BTUART	(1 << 21)	/* BTUART Unit Clock Enable */
+#define CKENA_20_UDC	(1 << 20)	/* UDC Clock Enable */
+#define CKENA_19_TPM	(1 << 19)	/* TPM Unit Clock Enable */
+#define CKENA_18_USIM1	(1 << 18)	/* USIM1 Unit Clock Enable */
+#define CKENA_17_USIM0	(1 << 17)	/* USIM0 Unit Clock Enable */
+#define CKENA_15_CIR	(1 << 15)	/* Consumer IR Clock Enable */
+#define CKENA_14_KEY	(1 << 14)	/* Keypad Controller Clock Enable */
+#define CKENA_13_MMC1	(1 << 13)	/* MMC1 Clock Enable */
+#define CKENA_12_MMC0	(1 << 12)	/* MMC0 Clock Enable */
+#define CKENA_11_FLASH	(1 << 11)	/* Boot ROM Clock Enable */
+#define CKENA_10_SRAM	(1 << 10)	/* SRAM Controller Clock Enable */
+#define CKENA_9_SMC	(1 << 9)	/* Static Memory Controller */
+#define CKENA_8_DMC	(1 << 8)	/* Dynamic Memory Controller */
+#define CKENA_7_GRAPHICS (1 << 7)	/* 2D Graphics Clock Enable */
+#define CKENA_6_USBCLI	(1 << 6)	/* USB Client Unit Clock Enable */
+#define CKENA_4_NAND	(1 << 4)	/* NAND Flash Controller Clock Enable */
+#define CKENA_3_CAMERA	(1 << 3)	/* Camera Interface Clock Enable */
+#define CKENA_2_USBHOST	(1 << 2)	/* USB Host Unit Clock Enable */
+#define CKENA_1_LCD	(1 << 1)	/* LCD Unit Clock Enable */
+
+#define CKENB_9_SYSBUS2	(1 << 9)	/* System bus 2 */
+#define CKENB_8_1WIRE	(1 << 8)	/* One Wire Interface Unit Clock Enable */
+#define CKENB_7_GPIO	(1 << 7)	/* GPIO Clock Enable */
+#define CKENB_6_IRQ	(1 << 6)	/* Interrupt Controller Clock Enable */
+#define CKENB_4_I2C	(1 << 4)	/* I2C Unit Clock Enable */
+#define CKENB_1_PWM1	(1 << 1)	/* PWM2 & PWM3 Clock Enable */
+#define CKENB_0_PWM0	(1 << 0)	/* PWM0 & PWM1 Clock Enable */
+
+#else /* if defined CONFIG_CPU_MONAHANS */
+
+#define CCCR		0x41300000  /* Core Clock Configuration Register */
+#define CKEN		0x41300004  /* Clock Enable Register */
+#define OSCC		0x41300008  /* Oscillator Configuration Register */
+#define CCSR		0x4130000C /* Core Clock Status Register */
+
+#define CKEN23_SSP1	(1 << 23) /* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC	(1 << 22) /* Memory Controler */
+#define CKEN21_MSHC	(1 << 21) /* Memery Stick Host Controller */
+#define CKEN20_IM	(1 << 20) /* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD	(1 << 19) /* Keypad Interface Clock Enable */
+#define CKEN18_USIM	(1 << 18) /* USIM Unit Clock Enable */
+#define CKEN17_MSL	(1 << 17) /* MSL Interface Unit Clock Enable */
+#define CKEN15_PWR_I2C	(1 << 15) /* PWR_I2C Unit Clock Enable */
+#define CKEN9_OST	(1 << 9)  /* OS Timer Unit Clock Enable */
+#define CKEN4_SSP3	(1 << 4)  /* SSP3 Unit Clock Enable */
+
+#define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#if !defined(CONFIG_CPU_PXA27X)
+#define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
+#endif
+#define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
+
+#define CKEN24_CAMERA	(1 << 24)	/* Camera Interface Clock Enable */
+#define CKEN23_SSP1	(1 << 23)	/* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC	(1 << 22)	/* Memory Controller Clock Enable */
+#define CKEN21_MEMSTK	(1 << 21)	/* Memory Stick Host Controller */
+#define CKEN20_IM	(1 << 20)	/* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD	(1 << 19)	/* Keypad Interface Clock Enable */
+#define CKEN18_USIM	(1 << 18)	/* USIM Unit Clock Enable */
+#define CKEN17_MSL	(1 << 17)	/* MSL Unit Clock Enable */
+#define CKEN16_LCD	(1 << 16)	/* LCD Unit Clock Enable */
+#define CKEN15_PWRI2C	(1 << 15)	/* PWR I2C Unit Clock Enable */
+#define CKEN14_I2C	(1 << 14)	/* I2C Unit Clock Enable */
+#define CKEN13_FICP	(1 << 13)	/* FICP Unit Clock Enable */
+#define CKEN12_MMC	(1 << 12)	/* MMC Unit Clock Enable */
+#define CKEN11_USB	(1 << 11)	/* USB Unit Clock Enable */
+#if defined(CONFIG_CPU_PXA27X)
+#define CKEN10_USBHOST	(1 << 10)	/* USB Host Unit Clock Enable */
+#define CKEN24_CAMERA	(1 << 24)	/* Camera Unit Clock Enable */
+#endif
+#define CKEN8_I2S	(1 << 8)	/* I2S Unit Clock Enable */
+#define CKEN7_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */
+#define CKEN6_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */
+#define CKEN5_STUART	(1 << 5)	/* STUART Unit Clock Enable */
+#define CKEN3_SSP	(1 << 3)	/* SSP Unit Clock Enable */
+#define CKEN2_AC97	(1 << 2)	/* AC97 Unit Clock Enable */
+#define CKEN1_PWM1	(1 << 1)	/* PWM1 Clock Enable */
+#define CKEN0_PWM0	(1 << 0)	/* PWM0 Clock Enable */
+
+#define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
+
+#if !defined(CONFIG_CPU_PXA27X)
+#define	 CCCR_L09      (0x1F)
+#define	 CCCR_L27      (0x1)
+#define	 CCCR_L32      (0x2)
+#define	 CCCR_L36      (0x3)
+#define	 CCCR_L40      (0x4)
+#define	 CCCR_L45      (0x5)
+
+#define	 CCCR_M1       (0x1 << 5)
+#define	 CCCR_M2       (0x2 << 5)
+#define	 CCCR_M4       (0x3 << 5)
+
+#define	 CCCR_N10      (0x2 << 7)
+#define	 CCCR_N15      (0x3 << 7)
+#define	 CCCR_N20      (0x4 << 7)
+#define	 CCCR_N25      (0x5 << 7)
+#define	 CCCR_N30      (0x6 << 7)
+#endif
+
+#endif /* CONFIG_CPU_MONAHANS */
+
+/******************************************************************************/
+/*
+ * Pulse Width Modulator
+ */
+#define PWM_CTRL0	0x40B00000  /* PWM 0 Control Register */
+#define PWM_PWDUTY0	0x40B00004  /* PWM 0 Duty Cycle Register */
+#define PWM_PERVAL0	0x40B00008  /* PWM 0 Period Control Register */
+
+#define PWM_CTRL1	0x40C00000  /* PWM 1 Control Register */
+#define PWM_PWDUTY1	0x40C00004  /* PWM 1 Duty Cycle Register */
+#define PWM_PERVAL1	0x40C00008  /* PWM 1 Period Control Register */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define PWM_CTRL2	0x40B00010  /* PWM 2 Control Register */
+#define PWM_PWDUTY2	0x40B00014  /* PWM 2 Duty Cycle Register */
+#define PWM_PERVAL2	0x40B00018  /* PWM 2 Period Control Register */
+
+#define PWM_CTRL3	0x40C00010  /* PWM 3 Control Register */
+#define PWM_PWDUTY3	0x40C00014  /* PWM 3 Duty Cycle Register */
+#define PWM_PERVAL3	0x40C00018  /* PWM 3 Period Control Register */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+/*
+ * Interrupt Controller
+ */
+#define ICIP		0x40D00000  /* Interrupt Controller IRQ Pending Register */
+#define ICMR		0x40D00004  /* Interrupt Controller Mask Register */
+#define ICLR		0x40D00008  /* Interrupt Controller Level Register */
+#define ICFP		0x40D0000C  /* Interrupt Controller FIQ Pending Register */
+#define ICPR		0x40D00010  /* Interrupt Controller Pending Register */
+#define ICCR		0x40D00014  /* Interrupt Controller Control Register */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define ICHP		0x40D00018  /* Interrupt Controller Highest Priority Register */
+#define ICIP2		0x40D0009C  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2		0x40D000A0  /* Interrupt Controller Mask Register 2 */
+#define ICLR2		0x40D000A4  /* Interrupt Controller Level Register 2 */
+#define ICFP2		0x40D000A8  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2		0x40D000AC  /* Interrupt Controller Pending Register 2 */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+/******************************************************************************/
+/*
+ * General Purpose I/O
+ */
+#define GPLR0		0x40E00000  /* GPIO Pin-Level Register GPIO<31:0> */
+#define GPLR1		0x40E00004  /* GPIO Pin-Level Register GPIO<63:32> */
+#define GPLR2		0x40E00008  /* GPIO Pin-Level Register GPIO<80:64> */
+
+#define GPDR0		0x40E0000C  /* GPIO Pin Direction Register GPIO<31:0> */
+#define GPDR1		0x40E00010  /* GPIO Pin Direction Register GPIO<63:32> */
+#define GPDR2		0x40E00014  /* GPIO Pin Direction Register GPIO<80:64> */
+
+#define GPSR0		0x40E00018  /* GPIO Pin Output Set Register GPIO<31:0> */
+#define GPSR1		0x40E0001C  /* GPIO Pin Output Set Register GPIO<63:32> */
+#define GPSR2		0x40E00020  /* GPIO Pin Output Set Register GPIO<80:64> */
+
+#define GPCR0		0x40E00024  /* GPIO Pin Output Clear Register GPIO<31:0> */
+#define GPCR1		0x40E00028  /* GPIO Pin Output Clear Register GPIO <63:32> */
+#define GPCR2		0x40E0002C  /* GPIO Pin Output Clear Register GPIO <80:64> */
+
+#define GRER0		0x40E00030  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
+#define GRER1		0x40E00034  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
+#define GRER2		0x40E00038  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
+
+#define GFER0		0x40E0003C  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
+#define GFER1		0x40E00040  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
+#define GFER2		0x40E00044  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
+
+#define GEDR0		0x40E00048  /* GPIO Edge Detect Status Register GPIO<31:0> */
+#define GEDR1		0x40E0004C  /* GPIO Edge Detect Status Register GPIO<63:32> */
+#define GEDR2		0x40E00050  /* GPIO Edge Detect Status Register GPIO<80:64> */
+
+#define GAFR0_L		0x40E00054  /* GPIO Alternate Function Select Register GPIO<15:0> */
+#define GAFR0_U		0x40E00058  /* GPIO Alternate Function Select Register GPIO<31:16> */
+#define GAFR1_L		0x40E0005C  /* GPIO Alternate Function Select Register GPIO<47:32> */
+#define GAFR1_U		0x40E00060  /* GPIO Alternate Function Select Register GPIO<63:48> */
+#define GAFR2_L		0x40E00064  /* GPIO Alternate Function Select Register GPIO<79:64> */
+#define GAFR2_U		0x40E00068  /* GPIO Alternate Function Select Register GPIO 80 */
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define GPLR3		0x40E00100  /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3		0x40E0010C  /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3		0x40E00118  /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3		0x40E00124  /* GPIO Pin Output Clear Register GPIO<127:96> */
+#define GRER3		0x40E00130  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3		0x40E0013C  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
+#define GEDR3		0x40E00148  /* GPIO Edge Detect Status Register GPIO<127:96> */
+#define GAFR3_L		0x40E0006C  /* GPIO Alternate Function Select Register GPIO<111:96> */
+#define GAFR3_U		0x40E00070  /* GPIO Alternate Function Select Register GPIO<127:112> */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
+
+#ifdef CONFIG_CPU_MONAHANS
+#define GSDR0		0x40E00400 /* Bit-wise Set of GPDR[31:0] */
+#define GSDR1		0x40E00404 /* Bit-wise Set of GPDR[63:32] */
+#define GSDR2		0x40E00408 /* Bit-wise Set of GPDR[95:64] */
+#define GSDR3		0x40E0040C /* Bit-wise Set of GPDR[127:96] */
+
+#define GCDR0		0x40E00420 /* Bit-wise Clear of GPDR[31:0] */
+#define GCDR1		0x40E00424 /* Bit-wise Clear of GPDR[63:32] */
+#define GCDR2		0x40E00428 /* Bit-wise Clear of GPDR[95:64] */
+#define GCDR3		0x40E0042C /* Bit-wise Clear of GPDR[127:96] */
+
+#define GSRER0		0x40E00440 /* Set Rising Edge Det. Enable [31:0] */
+#define GSRER1		0x40E00444 /* Set Rising Edge Det. Enable [63:32] */
+#define GSRER2		0x40E00448 /* Set Rising Edge Det. Enable [95:64] */
+#define GSRER3		0x40E0044C /* Set Rising Edge Det. Enable [127:96] */
+
+#define GCRER0		0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */
+#define GCRER1		0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */
+#define GCRER2		0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */
+#define GCRER3		0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */
+
+#define GSFER0		0x40E00480 /* Set Falling Edge Det. Enable [31:0] */
+#define GSFER1		0x40E00484 /* Set Falling Edge Det. Enable [63:32] */
+#define GSFER2		0x40E00488 /* Set Falling Edge Det. Enable [95:64] */
+#define GSFER3		0x40E0048C /* Set Falling Edge Det. Enable[127:96] */
+
+#define GCFER0		0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */
+#define GCFER1		0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */
+#define GCFER2		0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */
+#define GCFER3		0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */
+
+#define GSDR(x)		(0x40E00400 | ((x) & 0x60) >> 3)
+#define GCDR(x)		(0x40E00420 | ((x) & 0x60) >> 3)
+#endif
+
+#define _GPLR(x)	(0x40E00000 + (((x) & 0x60) >> 3))
+#define _GPDR(x)	(0x40E0000C + (((x) & 0x60) >> 3))
+#define _GPSR(x)	(0x40E00018 + (((x) & 0x60) >> 3))
+#define _GPCR(x)	(0x40E00024 + (((x) & 0x60) >> 3))
+#define _GRER(x)	(0x40E00030 + (((x) & 0x60) >> 3))
+#define _GFER(x)	(0x40E0003C + (((x) & 0x60) >> 3))
+#define _GEDR(x)	(0x40E00048 + (((x) & 0x60) >> 3))
+#define _GAFR(x)	(0x40E00054 + (((x) & 0x70) >> 2))
+
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define GPLR(x)		(((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
+#define GPDR(x)		(((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
+#define GPSR(x)		(((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
+#define GPCR(x)		(((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3))
+#define GRER(x)		(((((x) & 0x7f) < 96) ? _GRER(x) : GRER3))
+#define GFER(x)		(((((x) & 0x7f) < 96) ? _GFER(x) : GFER3))
+#define GEDR(x)		(((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3))
+#define GAFR(x)		(((((x) & 0x7f) < 96) ? _GAFR(x) : \
+			((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)))
+#else
+#define GPLR(x)		_GPLR(x)
+#define GPDR(x)		_GPDR(x)
+#define GPSR(x)		_GPSR(x)
+#define GPCR(x)		_GPCR(x)
+#define GRER(x)		_GRER(x)
+#define GFER(x)		_GFER(x)
+#define GEDR(x)		_GEDR(x)
+#define GAFR(x)		_GAFR(x)
+#endif
+
+#define GPIO_bit(x)	(1 << ((x) & 0x1f))
+
+/******************************************************************************/
+/*
+ * Multi-function Pin Registers:
+ */
+/* PXA320 */
+#if defined(CONFIG_CPU_PXA320)
+#define	DF_IO0		0x40e1024c
+#define	DF_IO1		0x40e10254
+#define	DF_IO2		0x40e1025c
+#define	DF_IO3		0x40e10264
+#define	DF_IO4		0x40e1026c
+#define	DF_IO5		0x40e10274
+#define	DF_IO6		0x40e1027c
+#define	DF_IO7		0x40e10284
+#define	DF_IO8		0x40e10250
+#define	DF_IO9		0x40e10258
+#define	DF_IO10		0x40e10260
+#define	DF_IO11		0x40e10268
+#define	DF_IO12		0x40e10270
+#define	DF_IO13		0x40e10278
+#define	DF_IO14		0x40e10280
+#define	DF_IO15		0x40e10288
+#define	DF_CLE_nOE	0x40e10204
+#define	DF_ALE_nWE1	0x40e10208
+#define	DF_ALE_nWE2	0x40e1021c
+#define	DF_SCLK_E	0x40e10210
+#define	DF_nCS0		0x40e10224
+#define	DF_nCS1		0x40e10228
+#define	nBE0		0x40e10214
+#define	nBE1		0x40e10218
+#define	nLUA		0x40e10234
+#define	nLLA		0x40e10238
+#define	DF_ADDR0	0x40e1023c
+#define	DF_ADDR1	0x40e10240
+#define	DF_ADDR2	0x40e10244
+#define	DF_ADDR3	0x40e10248
+#define	DF_INT_RnB	0x40e10220
+#define	DF_nCS0		0x40e10224
+#define	DF_nCS1		0x40e10228
+#define	DF_nWE		0x40e1022c
+#define	DF_nRE		0x40e10230
+
+#define	nXCVREN		0x40e10138
+
+#define	GPIO0		0x40e10124
+#define	GPIO1		0x40e10128
+#define	GPIO2		0x40e1012c
+#define	GPIO3		0x40e10130
+#define	GPIO4		0x40e10134
+#define	GPIO5		0x40e1028c
+#define	GPIO6		0x40e10290
+#define	GPIO7		0x40e10294
+#define	GPIO8		0x40e10298
+#define	GPIO9		0x40e1029c
+#define	GPIO10		0x40e10458
+#define	GPIO11		0x40e102a0
+#define	GPIO12		0x40e102a4
+#define	GPIO13		0x40e102a8
+#define	GPIO14		0x40e102ac
+#define	GPIO15		0x40e102b0
+#define	GPIO16		0x40e102b4
+#define	GPIO17		0x40e102b8
+#define	GPIO18		0x40e102bc
+#define	GPIO19		0x40e102c0
+#define	GPIO20		0x40e102c4
+#define	GPIO21		0x40e102c8
+#define	GPIO22		0x40e102cc
+#define	GPIO23		0x40e102d0
+#define	GPIO24		0x40e102d4
+#define	GPIO25		0x40e102d8
+#define	GPIO26		0x40e102dc
+
+#define	GPIO27		0x40e10400
+#define	GPIO28		0x40e10404
+#define	GPIO29		0x40e10408
+#define	GPIO30		0x40e1040c
+#define	GPIO31		0x40e10410
+#define	GPIO32		0x40e10414
+#define	GPIO33		0x40e10418
+#define	GPIO34		0x40e1041c
+#define	GPIO35		0x40e10420
+#define	GPIO36		0x40e10424
+#define	GPIO37		0x40e10428
+#define	GPIO38		0x40e1042c
+#define	GPIO39		0x40e10430
+#define	GPIO40		0x40e10434
+#define	GPIO41		0x40e10438
+#define	GPIO42		0x40e1043c
+#define	GPIO43		0x40e10440
+#define	GPIO44		0x40e10444
+#define	GPIO45		0x40e10448
+#define	GPIO46		0x40e1044c
+#define	GPIO47		0x40e10450
+#define	GPIO48		0x40e10454
+#define	GPIO49		0x40e1045c
+#define	GPIO50		0x40e10460
+#define	GPIO51		0x40e10464
+#define	GPIO52		0x40e10468
+#define	GPIO53		0x40e1046c
+#define	GPIO54		0x40e10470
+#define	GPIO55		0x40e10474
+#define	GPIO56		0x40e10478
+#define	GPIO57		0x40e1047c
+#define	GPIO58		0x40e10480
+#define	GPIO59		0x40e10484
+#define	GPIO60		0x40e10488
+#define	GPIO61		0x40e1048c
+#define	GPIO62		0x40e10490
+
+#define	GPIO6_2		0x40e10494
+#define	GPIO7_2		0x40e10498
+#define	GPIO8_2		0x40e1049c
+#define	GPIO9_2		0x40e104a0
+#define	GPIO10_2	0x40e104a4
+#define	GPIO11_2	0x40e104a8
+#define	GPIO12_2	0x40e104ac
+#define	GPIO13_2	0x40e104b0
+
+#define	GPIO63		0x40e104b4
+#define	GPIO64		0x40e104b8
+#define	GPIO65		0x40e104bc
+#define	GPIO66		0x40e104c0
+#define	GPIO67		0x40e104c4
+#define	GPIO68		0x40e104c8
+#define	GPIO69		0x40e104cc
+#define	GPIO70		0x40e104d0
+#define	GPIO71		0x40e104d4
+#define	GPIO72		0x40e104d8
+#define	GPIO73		0x40e104dc
+
+#define	GPIO14_2	0x40e104e0
+#define	GPIO15_2	0x40e104e4
+#define	GPIO16_2	0x40e104e8
+#define	GPIO17_2	0x40e104ec
+
+#define	GPIO74		0x40e104f0
+#define	GPIO75		0x40e104f4
+#define	GPIO76		0x40e104f8
+#define	GPIO77		0x40e104fc
+#define	GPIO78		0x40e10500
+#define	GPIO79		0x40e10504
+#define	GPIO80		0x40e10508
+#define	GPIO81		0x40e1050c
+#define	GPIO82		0x40e10510
+#define	GPIO83		0x40e10514
+#define	GPIO84		0x40e10518
+#define	GPIO85		0x40e1051c
+#define	GPIO86		0x40e10520
+#define	GPIO87		0x40e10524
+#define	GPIO88		0x40e10528
+#define	GPIO89		0x40e1052c
+#define	GPIO90		0x40e10530
+#define	GPIO91		0x40e10534
+#define	GPIO92		0x40e10538
+#define	GPIO93		0x40e1053c
+#define	GPIO94		0x40e10540
+#define	GPIO95		0x40e10544
+#define	GPIO96		0x40e10548
+#define	GPIO97		0x40e1054c
+#define	GPIO98		0x40e10550
+
+#define	GPIO99		0x40e10600
+#define	GPIO100		0x40e10604
+#define	GPIO101		0x40e10608
+#define	GPIO102		0x40e1060c
+#define	GPIO103		0x40e10610
+#define	GPIO104		0x40e10614
+#define	GPIO105		0x40e10618
+#define	GPIO106		0x40e1061c
+#define	GPIO107		0x40e10620
+#define	GPIO108		0x40e10624
+#define	GPIO109		0x40e10628
+#define	GPIO110		0x40e1062c
+#define	GPIO111		0x40e10630
+#define	GPIO112		0x40e10634
+
+#define	GPIO113		0x40e10638
+#define	GPIO114		0x40e1063c
+#define	GPIO115		0x40e10640
+#define	GPIO116		0x40e10644
+#define	GPIO117		0x40e10648
+#define	GPIO118		0x40e1064c
+#define	GPIO119		0x40e10650
+#define	GPIO120		0x40e10654
+#define	GPIO121		0x40e10658
+#define	GPIO122		0x40e1065c
+#define	GPIO123		0x40e10660
+#define	GPIO124		0x40e10664
+#define	GPIO125		0x40e10668
+#define	GPIO126		0x40e1066c
+#define	GPIO127		0x40e10670
+
+#define	GPIO0_2		0x40e10674
+#define	GPIO1_2		0x40e10678
+#define	GPIO2_2		0x40e1067c
+#define	GPIO3_2		0x40e10680
+#define	GPIO4_2		0x40e10684
+#define	GPIO5_2		0x40e10688
+
+/* PXA300 and PXA310 */
+#elif	defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310)
+#define	DF_IO0		0x40e10220
+#define	DF_IO1		0x40e10228
+#define	DF_IO2		0x40e10230
+#define	DF_IO3		0x40e10238
+#define	DF_IO4		0x40e10258
+#define	DF_IO5		0x40e10260
+#define	DF_IO7		0x40e10270
+#define	DF_IO6		0x40e10268
+#define	DF_IO8		0x40e10224
+#define	DF_IO9		0x40e1022c
+#define	DF_IO10		0x40e10234
+#define	DF_IO11		0x40e1023c
+#define	DF_IO12		0x40e1025c
+#define	DF_IO13		0x40e10264
+#define	DF_IO14		0x40e1026c
+#define	DF_IO15		0x40e10274
+#define	DF_CLE_NOE	0x40e10240
+#define	DF_ALE_nWE	0x40e1020c
+#define	DF_SCLK_E	0x40e10250
+#define	nCS0		0x40e100c4
+#define	nCS1		0x40e100c0
+#define	nBE0		0x40e10204
+#define	nBE1		0x40e10208
+#define	nLUA		0x40e10244
+#define	nLLA		0x40e10254
+#define	DF_ADDR0	0x40e10210
+#define	DF_ADDR1	0x40e10214
+#define	DF_ADDR2	0x40e10218
+#define	DF_ADDR3	0x40e1021c
+#define	DF_INT_RnB	0x40e100c8
+#define	DF_nCS0		0x40e10248
+#define	DF_nCS1		0x40e10278
+#define	DF_nWE		0x40e100cc
+#define	DF_nRE		0x40e10200
+
+#define	GPIO0		0x40e100b4
+#define	GPIO1		0x40e100b8
+#define	GPIO2		0x40e100bc
+#define	GPIO3		0x40e1027c
+#define	GPIO4		0x40e10280
+
+#define	GPIO5		0x40e10284
+#define	GPIO6		0x40e10288
+#define	GPIO7		0x40e1028c
+#define	GPIO8		0x40e10290
+#define	GPIO9		0x40e10294
+#define	GPIO10		0x40e10298
+#define	GPIO11		0x40e1029c
+#define	GPIO12		0x40e102a0
+#define	GPIO13		0x40e102a4
+#define	GPIO14		0x40e102a8
+#define	GPIO15		0x40e102ac
+#define	GPIO16		0x40e102b0
+#define	GPIO17		0x40e102b4
+#define	GPIO18		0x40e102b8
+#define	GPIO19		0x40e102bc
+#define	GPIO20		0x40e102c0
+#define	GPIO21		0x40e102c4
+#define	GPIO22		0x40e102c8
+#define	GPIO23		0x40e102cc
+#define	GPIO24		0x40e102d0
+#define	GPIO25		0x40e102d4
+#define	GPIO26		0x40e102d8
+
+#define	GPIO27		0x40e10400
+#define	GPIO28		0x40e10404
+#define	GPIO29		0x40e10408
+#define	ULPI_STP	0x40e1040c
+#define	ULPI_NXT	0x40e10410
+#define	ULPI_DIR	0x40e10414
+#define	GPIO30		0x40e10418
+#define	GPIO31		0x40e1041c
+#define	GPIO32		0x40e10420
+#define	GPIO33		0x40e10424
+#define	GPIO34		0x40e10428
+#define	GPIO35		0x40e1042c
+#define	GPIO36		0x40e10430
+#define	GPIO37		0x40e10434
+#define	GPIO38		0x40e10438
+#define	GPIO39		0x40e1043c
+#define	GPIO40		0x40e10440
+#define	GPIO41		0x40e10444
+#define	GPIO42		0x40e10448
+#define	GPIO43		0x40e1044c
+#define	GPIO44		0x40e10450
+#define	GPIO45		0x40e10454
+#define	GPIO46		0x40e10458
+#define	GPIO47		0x40e1045c
+#define	GPIO48		0x40e10460
+
+#define	GPIO49		0x40e10464
+#define	GPIO50		0x40e10468
+#define	GPIO51		0x40e1046c
+#define	GPIO52		0x40e10470
+#define	GPIO53		0x40e10474
+#define	GPIO54		0x40e10478
+#define	GPIO55		0x40e1047c
+#define	GPIO56		0x40e10480
+#define	GPIO57		0x40e10484
+#define	GPIO58		0x40e10488
+#define	GPIO59		0x40e1048c
+#define	GPIO60		0x40e10490
+#define	GPIO61		0x40e10494
+#define	GPIO62		0x40e10498
+#define	GPIO63		0x40e1049c
+#define	GPIO64		0x40e104a0
+#define	GPIO65		0x40e104a4
+#define	GPIO66		0x40e104a8
+#define	GPIO67		0x40e104ac
+#define	GPIO68		0x40e104b0
+#define	GPIO69		0x40e104b4
+#define	GPIO70		0x40e104b8
+#define	GPIO71		0x40e104bc
+#define	GPIO72		0x40e104c0
+#define	GPIO73		0x40e104c4
+#define	GPIO74		0x40e104c8
+#define	GPIO75		0x40e104cc
+#define	GPIO76		0x40e104d0
+#define	GPIO77		0x40e104d4
+#define	GPIO78		0x40e104d8
+#define	GPIO79		0x40e104dc
+#define	GPIO80		0x40e104e0
+#define	GPIO81		0x40e104e4
+#define	GPIO82		0x40e104e8
+#define	GPIO83		0x40e104ec
+#define	GPIO84		0x40e104f0
+#define	GPIO85		0x40e104f4
+#define	GPIO86		0x40e104f8
+#define	GPIO87		0x40e104fc
+#define	GPIO88		0x40e10500
+#define	GPIO89		0x40e10504
+#define	GPIO90		0x40e10508
+#define	GPIO91		0x40e1050c
+#define	GPIO92		0x40e10510
+#define	GPIO93		0x40e10514
+#define	GPIO94		0x40e10518
+#define	GPIO95		0x40e1051c
+#define	GPIO96		0x40e10520
+#define	GPIO97		0x40e10524
+#define	GPIO98		0x40e10528
+
+#define	GPIO99		0x40e10600
+#define	GPIO100		0x40e10604
+#define	GPIO101		0x40e10608
+#define	GPIO102		0x40e1060c
+#define	GPIO103		0x40e10610
+#define	GPIO104		0x40e10614
+#define	GPIO105		0x40e10618
+#define	GPIO106		0x40e1061c
+#define	GPIO107		0x40e10620
+#define	GPIO108		0x40e10624
+#define	GPIO109		0x40e10628
+#define	GPIO110		0x40e1062c
+#define	GPIO111		0x40e10630
+#define	GPIO112		0x40e10634
+
+#define	GPIO113		0x40e10638
+#define	GPIO114		0x40e1063c
+#define	GPIO115		0x40e10640
+#define	GPIO116		0x40e10644
+#define	GPIO117		0x40e10648
+#define	GPIO118		0x40e1064c
+#define	GPIO119		0x40e10650
+#define	GPIO120		0x40e10654
+#define	GPIO121		0x40e10658
+#define	GPIO122		0x40e1065c
+#define	GPIO123		0x40e10660
+#define	GPIO124		0x40e10664
+#define	GPIO125		0x40e10668
+#define	GPIO126		0x40e1066c
+#define	GPIO127		0x40e10670
+
+#define	GPIO0_2		0x40e10674
+#define	GPIO1_2		0x40e10678
+#define	GPIO2_2		0x40e102dc
+#define	GPIO3_2		0x40e102e0
+#define	GPIO4_2		0x40e102e4
+#define	GPIO5_2		0x40e102e8
+#define	GPIO6_2		0x40e102ec
+
+#ifndef	CONFIG_CPU_PXA300	/* PXA310 only */
+#define	GPIO7_2		0x40e1052c
+#define	GPIO8_2		0x40e10530
+#define	GPIO9_2		0x40e10534
+#define	GPIO10_2	0x40e10538
+#endif
+#endif
+
+#ifdef CONFIG_CPU_MONAHANS
+/* MFPR Bit Definitions, see 4-10, Vol. 1 */
+#define PULL_SEL	0x8000
+#define PULLUP_EN	0x4000
+#define PULLDOWN_EN	0x2000
+
+#define DRIVE_FAST_1mA	0x0
+#define DRIVE_FAST_2mA	0x400
+#define DRIVE_FAST_3mA	0x800
+#define DRIVE_FAST_4mA	0xC00
+#define DRIVE_SLOW_6mA	0x1000
+#define DRIVE_FAST_6mA	0x1400
+#define DRIVE_SLOW_10mA	0x1800
+#define DRIVE_FAST_10mA	0x1C00
+
+#define SLEEP_SEL	0x200
+#define SLEEP_DATA	0x100
+#define SLEEP_OE_N	0x80
+#define EDGE_CLEAR	0x40
+#define EDGE_FALL_EN	0x20
+#define EDGE_RISE_EN	0x10
+
+#define AF_SEL_0	0x0	/* Alternate function 0 (reset state) */
+#define AF_SEL_1	0x1	/* Alternate function 1 */
+#define AF_SEL_2	0x2	/* Alternate function 2 */
+#define AF_SEL_3	0x3	/* Alternate function 3 */
+#define AF_SEL_4	0x4	/* Alternate function 4 */
+#define AF_SEL_5	0x5	/* Alternate function 5 */
+#define AF_SEL_6	0x6	/* Alternate function 6 */
+#define AF_SEL_7	0x7	/* Alternate function 7 */
+
+#endif /* CONFIG_CPU_MONAHANS */
+
+/* GPIO alternate function assignments */
+
+#define GPIO1_RST		1	/* reset */
+#define GPIO6_MMCCLK		6	/* MMC Clock */
+#define GPIO8_48MHz		7	/* 48 MHz clock output */
+#define GPIO8_MMCCS0		8	/* MMC Chip Select 0 */
+#define GPIO9_MMCCS1		9	/* MMC Chip Select 1 */
+#define GPIO10_RTCCLK		10	/* real time clock (1 Hz) */
+#define GPIO11_3_6MHz		11	/* 3.6 MHz oscillator out */
+#define GPIO12_32KHz		12	/* 32 kHz out */
+#define GPIO13_MBGNT		13	/* memory controller grant */
+#define GPIO14_MBREQ		14	/* alternate bus master request */
+#define GPIO15_nCS_1		15	/* chip select 1 */
+#define GPIO16_PWM0		16	/* PWM0 output */
+#define GPIO17_PWM1		17	/* PWM1 output */
+#define GPIO18_RDY		18	/* Ext. Bus Ready */
+#define GPIO19_DREQ1		19	/* External DMA Request */
+#define GPIO20_DREQ0		20	/* External DMA Request */
+#define GPIO23_SCLK		23	/* SSP clock */
+#define GPIO24_SFRM		24	/* SSP Frame */
+#define GPIO25_STXD		25	/* SSP transmit */
+#define GPIO26_SRXD		26	/* SSP receive */
+#define GPIO27_SEXTCLK		27	/* SSP ext_clk */
+#define GPIO28_BITCLK		28	/* AC97/I2S bit_clk */
+#define GPIO29_SDATA_IN		29	/* AC97 Sdata_in0 / I2S Sdata_in */
+#define GPIO30_SDATA_OUT	30	/* AC97/I2S Sdata_out */
+#define GPIO31_SYNC		31	/* AC97/I2S sync */
+#define GPIO32_SDATA_IN1	32	/* AC97 Sdata_in1 */
+#define GPIO33_nCS_5		33	/* chip select 5 */
+#define GPIO34_FFRXD		34	/* FFUART receive */
+#define GPIO34_MMCCS0		34	/* MMC Chip Select 0 */
+#define GPIO35_FFCTS		35	/* FFUART Clear to send */
+#define GPIO36_FFDCD		36	/* FFUART Data carrier detect */
+#define GPIO37_FFDSR		37	/* FFUART data set ready */
+#define GPIO38_FFRI		38	/* FFUART Ring Indicator */
+#define GPIO39_MMCCS1		39	/* MMC Chip Select 1 */
+#define GPIO39_FFTXD		39	/* FFUART transmit data */
+#define GPIO40_FFDTR		40	/* FFUART data terminal Ready */
+#define GPIO41_FFRTS		41	/* FFUART request to send */
+#define GPIO42_BTRXD		42	/* BTUART receive data */
+#define GPIO43_BTTXD		43	/* BTUART transmit data */
+#define GPIO44_BTCTS		44	/* BTUART clear to send */
+#define GPIO45_BTRTS		45	/* BTUART request to send */
+#define GPIO46_ICPRXD		46	/* ICP receive data */
+#define GPIO46_STRXD		46	/* STD_UART receive data */
+#define GPIO47_ICPTXD		47	/* ICP transmit data */
+#define GPIO47_STTXD		47	/* STD_UART transmit data */
+#define GPIO48_nPOE		48	/* Output Enable for Card Space */
+#define GPIO49_nPWE		49	/* Write Enable for Card Space */
+#define GPIO50_nPIOR		50	/* I/O Read for Card Space */
+#define GPIO51_nPIOW		51	/* I/O Write for Card Space */
+#define GPIO52_nPCE_1		52	/* Card Enable for Card Space */
+#define GPIO53_nPCE_2		53	/* Card Enable for Card Space */
+#define GPIO53_MMCCLK		53	/* MMC Clock */
+#define GPIO54_MMCCLK		54	/* MMC Clock */
+#define GPIO54_pSKTSEL		54	/* Socket Select for Card Space */
+#define GPIO55_nPREG		55	/* Card Address bit 26 */
+#define GPIO56_nPWAIT		56	/* Wait signal for Card Space */
+#define GPIO57_nIOIS16		57	/* Bus Width select for I/O Card Space */
+#define GPIO58_LDD_0		58	/* LCD data pin 0 */
+#define GPIO59_LDD_1		59	/* LCD data pin 1 */
+#define GPIO60_LDD_2		60	/* LCD data pin 2 */
+#define GPIO61_LDD_3		61	/* LCD data pin 3 */
+#define GPIO62_LDD_4		62	/* LCD data pin 4 */
+#define GPIO63_LDD_5		63	/* LCD data pin 5 */
+#define GPIO64_LDD_6		64	/* LCD data pin 6 */
+#define GPIO65_LDD_7		65	/* LCD data pin 7 */
+#define GPIO66_LDD_8		66	/* LCD data pin 8 */
+#define GPIO66_MBREQ		66	/* alternate bus master req */
+#define GPIO67_LDD_9		67	/* LCD data pin 9 */
+#define GPIO67_MMCCS0		67	/* MMC Chip Select 0 */
+#define GPIO68_LDD_10		68	/* LCD data pin 10 */
+#define GPIO68_MMCCS1		68	/* MMC Chip Select 1 */
+#define GPIO69_LDD_11		69	/* LCD data pin 11 */
+#define GPIO69_MMCCLK		69	/* MMC_CLK */
+#define GPIO70_LDD_12		70	/* LCD data pin 12 */
+#define GPIO70_RTCCLK		70	/* Real Time clock (1 Hz) */
+#define GPIO71_LDD_13		71	/* LCD data pin 13 */
+#define GPIO71_3_6MHz		71	/* 3.6 MHz Oscillator clock */
+#define GPIO72_LDD_14		72	/* LCD data pin 14 */
+#define GPIO72_32kHz		72	/* 32 kHz clock */
+#define GPIO73_LDD_15		73	/* LCD data pin 15 */
+#define GPIO73_MBGNT		73	/* Memory controller grant */
+#define GPIO74_LCD_FCLK		74	/* LCD Frame clock */
+#define GPIO75_LCD_LCLK		75	/* LCD line clock */
+#define GPIO76_LCD_PCLK		76	/* LCD Pixel clock */
+#define GPIO77_LCD_ACBIAS	77	/* LCD AC Bias */
+#define GPIO78_nCS_2		78	/* chip select 2 */
+#define GPIO79_nCS_3		79	/* chip select 3 */
+#define GPIO80_nCS_4		80	/* chip select 4 */
+
+/* GPIO alternate function mode & direction */
+
+#define GPIO_IN			0x000
+#define GPIO_OUT		0x080
+#define GPIO_ALT_FN_1_IN	0x100
+#define GPIO_ALT_FN_1_OUT	0x180
+#define GPIO_ALT_FN_2_IN	0x200
+#define GPIO_ALT_FN_2_OUT	0x280
+#define GPIO_ALT_FN_3_IN	0x300
+#define GPIO_ALT_FN_3_OUT	0x380
+#define GPIO_MD_MASK_NR		0x07f
+#define GPIO_MD_MASK_DIR	0x080
+#define GPIO_MD_MASK_FN		0x300
+
+#define GPIO1_RTS_MD		( 1 | GPIO_ALT_FN_1_IN)
+#define GPIO6_MMCCLK_MD		( 6 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_48MHz_MD		( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_MMCCS0_MD		( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO9_MMCCS1_MD		( 9 | GPIO_ALT_FN_1_OUT)
+#define GPIO10_RTCCLK_MD	(10 | GPIO_ALT_FN_1_OUT)
+#define GPIO11_3_6MHz_MD	(11 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_32KHz_MD		(12 | GPIO_ALT_FN_1_OUT)
+#define GPIO13_MBGNT_MD		(13 | GPIO_ALT_FN_2_OUT)
+#define GPIO14_MBREQ_MD		(14 | GPIO_ALT_FN_1_IN)
+#define GPIO15_nCS_1_MD		(15 | GPIO_ALT_FN_2_OUT)
+#define GPIO16_PWM0_MD		(16 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_PWM1_MD		(17 | GPIO_ALT_FN_2_OUT)
+#define GPIO18_RDY_MD		(18 | GPIO_ALT_FN_1_IN)
+#define GPIO19_DREQ1_MD		(19 | GPIO_ALT_FN_1_IN)
+#define GPIO20_DREQ0_MD		(20 | GPIO_ALT_FN_1_IN)
+#define GPIO23_SCLK_md		(23 | GPIO_ALT_FN_2_OUT)
+#define GPIO24_SFRM_MD		(24 | GPIO_ALT_FN_2_OUT)
+#define GPIO25_STXD_MD		(25 | GPIO_ALT_FN_2_OUT)
+#define GPIO26_SRXD_MD		(26 | GPIO_ALT_FN_1_IN)
+#define GPIO27_SEXTCLK_MD	(27 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_AC97_MD	(28 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_I2S_MD	(28 | GPIO_ALT_FN_2_IN)
+#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
+#define GPIO29_SDATA_IN_I2S_MD	(29 | GPIO_ALT_FN_2_IN)
+#define GPIO30_SDATA_OUT_AC97_MD	(30 | GPIO_ALT_FN_2_OUT)
+#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_AC97_MD	(31 | GPIO_ALT_FN_2_OUT)
+#define GPIO31_SYNC_I2S_MD	(31 | GPIO_ALT_FN_1_OUT)
+#define GPIO32_SDATA_IN1_AC97_MD	(32 | GPIO_ALT_FN_1_IN)
+#define GPIO33_nCS_5_MD		(33 | GPIO_ALT_FN_2_OUT)
+#define GPIO34_FFRXD_MD		(34 | GPIO_ALT_FN_1_IN)
+#define GPIO34_MMCCS0_MD	(34 | GPIO_ALT_FN_2_OUT)
+#define GPIO35_FFCTS_MD		(35 | GPIO_ALT_FN_1_IN)
+#define GPIO36_FFDCD_MD		(36 | GPIO_ALT_FN_1_IN)
+#define GPIO37_FFDSR_MD		(37 | GPIO_ALT_FN_1_IN)
+#define GPIO38_FFRI_MD		(38 | GPIO_ALT_FN_1_IN)
+#define GPIO39_MMCCS1_MD	(39 | GPIO_ALT_FN_1_OUT)
+#define GPIO39_FFTXD_MD		(39 | GPIO_ALT_FN_2_OUT)
+#define GPIO40_FFDTR_MD		(40 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_FFRTS_MD		(41 | GPIO_ALT_FN_2_OUT)
+#define GPIO42_BTRXD_MD		(42 | GPIO_ALT_FN_1_IN)
+#define GPIO43_BTTXD_MD		(43 | GPIO_ALT_FN_2_OUT)
+#define GPIO44_BTCTS_MD		(44 | GPIO_ALT_FN_1_IN)
+#define GPIO45_BTRTS_MD		(45 | GPIO_ALT_FN_2_OUT)
+#define GPIO46_ICPRXD_MD	(46 | GPIO_ALT_FN_1_IN)
+#define GPIO46_STRXD_MD		(46 | GPIO_ALT_FN_2_IN)
+#define GPIO47_ICPTXD_MD	(47 | GPIO_ALT_FN_2_OUT)
+#define GPIO47_STTXD_MD		(47 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD		(48 | GPIO_ALT_FN_2_OUT)
+#define GPIO49_nPWE_MD		(49 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_nPIOR_MD		(50 | GPIO_ALT_FN_2_OUT)
+#define GPIO51_nPIOW_MD		(51 | GPIO_ALT_FN_2_OUT)
+#define GPIO52_nPCE_1_MD	(52 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_nPCE_2_MD	(53 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_MMCCLK_MD	(53 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_MMCCLK_MD	(54 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_pSKTSEL_MD	(54 | GPIO_ALT_FN_2_OUT)
+#define GPIO55_nPREG_MD		(55 | GPIO_ALT_FN_2_OUT)
+#define GPIO56_nPWAIT_MD	(56 | GPIO_ALT_FN_1_IN)
+#define GPIO57_nIOIS16_MD	(57 | GPIO_ALT_FN_1_IN)
+#define GPIO58_LDD_0_MD		(58 | GPIO_ALT_FN_2_OUT)
+#define GPIO59_LDD_1_MD		(59 | GPIO_ALT_FN_2_OUT)
+#define GPIO60_LDD_2_MD		(60 | GPIO_ALT_FN_2_OUT)
+#define GPIO61_LDD_3_MD		(61 | GPIO_ALT_FN_2_OUT)
+#define GPIO62_LDD_4_MD		(62 | GPIO_ALT_FN_2_OUT)
+#define GPIO63_LDD_5_MD		(63 | GPIO_ALT_FN_2_OUT)
+#define GPIO64_LDD_6_MD		(64 | GPIO_ALT_FN_2_OUT)
+#define GPIO65_LDD_7_MD		(65 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_LDD_8_MD		(66 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_MBREQ_MD		(66 | GPIO_ALT_FN_1_IN)
+#define GPIO67_LDD_9_MD		(67 | GPIO_ALT_FN_2_OUT)
+#define GPIO67_MMCCS0_MD	(67 | GPIO_ALT_FN_1_OUT)
+#define GPIO68_LDD_10_MD	(68 | GPIO_ALT_FN_2_OUT)
+#define GPIO68_MMCCS1_MD	(68 | GPIO_ALT_FN_1_OUT)
+#define GPIO69_LDD_11_MD	(69 | GPIO_ALT_FN_2_OUT)
+#define GPIO69_MMCCLK_MD	(69 | GPIO_ALT_FN_1_OUT)
+#define GPIO70_LDD_12_MD	(70 | GPIO_ALT_FN_2_OUT)
+#define GPIO70_RTCCLK_MD	(70 | GPIO_ALT_FN_1_OUT)
+#define GPIO71_LDD_13_MD	(71 | GPIO_ALT_FN_2_OUT)
+#define GPIO71_3_6MHz_MD	(71 | GPIO_ALT_FN_1_OUT)
+#define GPIO72_LDD_14_MD	(72 | GPIO_ALT_FN_2_OUT)
+#define GPIO72_32kHz_MD		(72 | GPIO_ALT_FN_1_OUT)
+#define GPIO73_LDD_15_MD	(73 | GPIO_ALT_FN_2_OUT)
+#define GPIO73_MBGNT_MD		(73 | GPIO_ALT_FN_1_OUT)
+#define GPIO74_LCD_FCLK_MD	(74 | GPIO_ALT_FN_2_OUT)
+#define GPIO75_LCD_LCLK_MD	(75 | GPIO_ALT_FN_2_OUT)
+#define GPIO76_LCD_PCLK_MD	(76 | GPIO_ALT_FN_2_OUT)
+#define GPIO77_LCD_ACBIAS_MD	(77 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nCS_2_MD		(78 | GPIO_ALT_FN_2_OUT)
+#define GPIO79_nCS_3_MD		(79 | GPIO_ALT_FN_2_OUT)
+#define GPIO80_nCS_4_MD		(80 | GPIO_ALT_FN_2_OUT)
+
+#define GPIO117_SCL		(117 | GPIO_ALT_FN_1_OUT)
+#define GPIO118_SDA		(118 | GPIO_ALT_FN_1_OUT)
+
+/*
+ * Power Manager
+ */
+#ifdef CONFIG_CPU_MONAHANS
+
+#define ASCR		0x40F40000  /* Application Subsystem Power Status/Control Register */
+#define ARSR		0x40F40004  /* Application Subsystem Reset Status Register */
+#define AD3ER		0x40F40008  /* Application Subsystem D3 state Wakeup Enable Register */
+#define AD3SR		0x40F4000C  /* Application Subsystem D3 state Wakeup Status Register */
+#define AD2D0ER		0x40F40010  /* Application Subsystem D2 to D0 state Wakeup Enable Register */
+#define AD2D0SR		0x40F40014  /* Application Subsystem D2 to D0 state Wakeup Status Register */
+#define AD2D1ER		0x40F40018  /* Application Subsystem D2 to D1 state Wakeup Enable Register */
+#define AD2D1SR		0x40F4001C  /* Application Subsystem D2 to D1 state Wakeup Status Register */
+#define AD1D0ER		0x40F40020  /* Application Subsystem D1 to D0 state Wakeup Enable Register */
+#define AD1D0SR		0x40F40024  /* Application Subsystem D1 to D0 state Wakeup Status Register */
+#define ASDCNT		0x40F40028  /* Application Subsystem SRAM Drowsy Count Register */
+#define AD3R		0x40F40030  /* Application Subsystem D3 State Configuration Register */
+#define AD2R		0x40F40034  /* Application Subsystem D2 State Configuration Register */
+#define AD1R		0x40F40038  /* Application Subsystem D1 State Configuration Register */
+
+#define PMCR		0x40F50000  /* Power Manager Control Register */
+#define PSR		0x40F50004  /* Power Manager S2 Status Register */
+#define PSPR		0x40F50008  /* Power Manager Scratch Pad Register */
+#define PCFR		0x40F5000C  /* Power Manager General Configuration Register */
+#define PWER		0x40F50010  /* Power Manager Wake-up Enable Register */
+#define PWSR		0x40F50014  /* Power Manager Wake-up Status Register */
+#define PECR		0x40F50018  /* Power Manager EXT_WAKEUP[1:0] Control Register */
+#define DCDCSR		0x40F50080  /* DC-DC Controller Status Register */
+#define PVCR		0x40F50100  /* Power Manager Voltage Change Control Register */
+#define    PCMD(x) (0x40F50110 + x*4)
+#define    PCMD0   (0x40F50110 + 0 * 4)
+#define    PCMD1   (0x40F50110 + 1 * 4)
+#define    PCMD2   (0x40F50110 + 2 * 4)
+#define    PCMD3   (0x40F50110 + 3 * 4)
+#define    PCMD4   (0x40F50110 + 4 * 4)
+#define    PCMD5   (0x40F50110 + 5 * 4)
+#define    PCMD6   (0x40F50110 + 6 * 4)
+#define    PCMD7   (0x40F50110 + 7 * 4)
+#define    PCMD8   (0x40F50110 + 8 * 4)
+#define    PCMD9   (0x40F50110 + 9 * 4)
+#define    PCMD10  (0x40F50110 + 10 * 4)
+#define    PCMD11  (0x40F50110 + 11 * 4)
+#define    PCMD12  (0x40F50110 + 12 * 4)
+#define    PCMD13  (0x40F50110 + 13 * 4)
+#define    PCMD14  (0x40F50110 + 14 * 4)
+#define    PCMD15  (0x40F50110 + 15 * 4)
+#define    PCMD16  (0x40F50110 + 16 * 4)
+#define    PCMD17  (0x40F50110 + 17 * 4)
+#define    PCMD18  (0x40F50110 + 18 * 4)
+#define    PCMD19  (0x40F50110 + 19 * 4)
+#define    PCMD20  (0x40F50110 + 20 * 4)
+#define    PCMD21  (0x40F50110 + 21 * 4)
+#define    PCMD22  (0x40F50110 + 22 * 4)
+#define    PCMD23  (0x40F50110 + 23 * 4)
+#define    PCMD24  (0x40F50110 + 24 * 4)
+#define    PCMD25  (0x40F50110 + 25 * 4)
+#define    PCMD26  (0x40F50110 + 26 * 4)
+#define    PCMD27  (0x40F50110 + 27 * 4)
+#define    PCMD28  (0x40F50110 + 28 * 4)
+#define    PCMD29  (0x40F50110 + 29 * 4)
+#define    PCMD30  (0x40F50110 + 30 * 4)
+#define    PCMD31  (0x40F50110 + 31 * 4)
+
+#define    PCMD_MBC    (1<<12)
+#define    PCMD_DCE    (1<<11)
+#define    PCMD_LC     (1<<10)
+#define    PCMD_SQC    (3<<8)  /* only 00 and 01 are valid */
+
+#define PVCR_FVC                   (0x1 << 28)
+#define PVCR_VCSA                  (0x1<<14)
+#define PVCR_CommandDelay          (0xf80)
+#define PVCR_ReadPointer           0x01f00000
+#define PVCR_SlaveAddress          (0x7f)
+
+#else /* ifdef CONFIG_CPU_MONAHANS */
+
+#define PMCR		0x40F00000  /* Power Manager Control Register */
+#define PSSR		0x40F00004  /* Power Manager Sleep Status Register */
+#define PSPR		0x40F00008  /* Power Manager Scratch Pad Register */
+#define PWER		0x40F0000C  /* Power Manager Wake-up Enable Register */
+#define PRER		0x40F00010  /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER		0x40F00014  /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR		0x40F00018  /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR		0x40F0001C  /* Power Manager General Configuration Register */
+#define PGSR0		0x40F00020  /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1		0x40F00024  /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2		0x40F00028  /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3		0x40F0002C  /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR		0x40F00030  /* Reset Controller Status Register */
+
+#define	   PSLR	   0x40F00034	/* Power Manager Sleep Config Register */
+#define	   PSTR	   0x40F00038	/* Power Manager Standby Config Register */
+#define	   PSNR	   0x40F0003C	/* Power Manager Sense Config Register */
+#define	   PVCR	   0x40F00040	/* Power Manager VoltageControl Register */
+#define	   PKWR	   0x40F00050	/* Power Manager KB Wake-up Enable Reg */
+#define	   PKSR	   0x40F00054	/* Power Manager KB Level-Detect Register */
+#define	   PCMD(x) (0x40F00080 + x*4)
+#define	   PCMD0   (0x40F00080 + 0 * 4)
+#define	   PCMD1   (0x40F00080 + 1 * 4)
+#define	   PCMD2   (0x40F00080 + 2 * 4)
+#define	   PCMD3   (0x40F00080 + 3 * 4)
+#define	   PCMD4   (0x40F00080 + 4 * 4)
+#define	   PCMD5   (0x40F00080 + 5 * 4)
+#define	   PCMD6   (0x40F00080 + 6 * 4)
+#define	   PCMD7   (0x40F00080 + 7 * 4)
+#define	   PCMD8   (0x40F00080 + 8 * 4)
+#define	   PCMD9   (0x40F00080 + 9 * 4)
+#define	   PCMD10  (0x40F00080 + 10 * 4)
+#define	   PCMD11  (0x40F00080 + 11 * 4)
+#define	   PCMD12  (0x40F00080 + 12 * 4)
+#define	   PCMD13  (0x40F00080 + 13 * 4)
+#define	   PCMD14  (0x40F00080 + 14 * 4)
+#define	   PCMD15  (0x40F00080 + 15 * 4)
+#define	   PCMD16  (0x40F00080 + 16 * 4)
+#define	   PCMD17  (0x40F00080 + 17 * 4)
+#define	   PCMD18  (0x40F00080 + 18 * 4)
+#define	   PCMD19  (0x40F00080 + 19 * 4)
+#define	   PCMD20  (0x40F00080 + 20 * 4)
+#define	   PCMD21  (0x40F00080 + 21 * 4)
+#define	   PCMD22  (0x40F00080 + 22 * 4)
+#define	   PCMD23  (0x40F00080 + 23 * 4)
+#define	   PCMD24  (0x40F00080 + 24 * 4)
+#define	   PCMD25  (0x40F00080 + 25 * 4)
+#define	   PCMD26  (0x40F00080 + 26 * 4)
+#define	   PCMD27  (0x40F00080 + 27 * 4)
+#define	   PCMD28  (0x40F00080 + 28 * 4)
+#define	   PCMD29  (0x40F00080 + 29 * 4)
+#define	   PCMD30  (0x40F00080 + 30 * 4)
+#define	   PCMD31  (0x40F00080 + 31 * 4)
+
+#define	   PCMD_MBC    (1<<12)
+#define	   PCMD_DCE    (1<<11)
+#define	   PCMD_LC     (1<<10)
+/* FIXME:  PCMD_SQC need be checked.   */
+#define	   PCMD_SQC    (3<<8)  /* currently only bit 8 is changerable, */
+				/* bit 9 should be 0 all day. */
+#define PVCR_VCSA		   (0x1<<14)
+#define PVCR_CommandDelay	   (0xf80)
+/* define MACRO for Power Manager General Configuration Register (PCFR) */
+#define PCFR_FVC		   (0x1 << 10)
+#define PCFR_PI2C_EN		   (0x1 << 6)
+
+#define PSSR_OTGPH	(1 << 6)	/* OTG Peripheral control Hold */
+#define PSSR_RDH	(1 << 5)	/* Read Disable Hold */
+#define PSSR_PH		(1 << 4)	/* Peripheral Control Hold */
+#define PSSR_VFS	(1 << 2)	/* VDD Fault Status */
+#define PSSR_BFS	(1 << 1)	/* Battery Fault Status */
+#define PSSR_SSS	(1 << 0)	/* Software Sleep Status */
+
+#define PCFR_DS		(1 << 3)	/* Deep Sleep Mode */
+#define PCFR_FS		(1 << 2)	/* Float Static Chip Selects */
+#define PCFR_FP		(1 << 1)	/* Float PCMCIA controls */
+#define PCFR_OPDE	(1 << 0)	/* 3.6864 MHz oscillator power-down enable */
+
+#define RCSR_GPR	(1 << 3)	/* GPIO Reset */
+#define RCSR_SMR	(1 << 2)	/* Sleep Mode */
+#define RCSR_WDR	(1 << 1)	/* Watchdog Reset */
+#define RCSR_HWR	(1 << 0)	/* Hardware Reset */
+
+#endif /* CONFIG_CPU_MONAHANS */
+
+/*
+ * SSP Serial Port Registers
+ */
+#define SSCR0		0x41000000  /* SSP Control Register 0 */
+#define SSCR1		0x41000004  /* SSP Control Register 1 */
+#define SSSR		0x41000008  /* SSP Status Register */
+#define SSITR		0x4100000C  /* SSP Interrupt Test Register */
+#define SSDR		0x41000010  /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
+
+/*
+ * MultiMediaCard (MMC) controller
+ */
+#define MMC_STRPCL	0x41100000  /* Control to start and stop MMC clock */
+#define MMC_STAT	0x41100004  /* MMC Status Register (read only) */
+#define MMC_CLKRT	0x41100008  /* MMC clock rate */
+#define MMC_SPI		0x4110000c  /* SPI mode control bits */
+#define MMC_CMDAT	0x41100010  /* Command/response/data sequence control */
+#define MMC_RESTO	0x41100014  /* Expected response time out */
+#define MMC_RDTO	0x41100018  /* Expected data read time out */
+#define MMC_BLKLEN	0x4110001c  /* Block length of data transaction */
+#define MMC_NOB		0x41100020  /* Number of blocks, for block mode */
+#define MMC_PRTBUF	0x41100024  /* Partial MMC_TXFIFO FIFO written */
+#define MMC_I_MASK	0x41100028  /* Interrupt Mask */
+#define MMC_I_REG	0x4110002c  /* Interrupt Register (read only) */
+#define MMC_CMD		0x41100030  /* Index of current command */
+#define MMC_ARGH	0x41100034  /* MSW part of the current command argument */
+#define MMC_ARGL	0x41100038  /* LSW part of the current command argument */
+#define MMC_RES		0x4110003c  /* Response FIFO (read only) */
+#define MMC_RXFIFO	0x41100040  /* Receive FIFO (read only) */
+#define MMC_TXFIFO	0x41100044  /* Transmit FIFO (write only) */
+
+
+/*
+ * LCD
+ */
+#define LCCR0		0x44000000  /* LCD Controller Control Register 0 */
+#define LCCR1		0x44000004  /* LCD Controller Control Register 1 */
+#define LCCR2		0x44000008  /* LCD Controller Control Register 2 */
+#define LCCR3		0x4400000C  /* LCD Controller Control Register 3 */
+#define DFBR0		0x44000020  /* DMA Channel 0 Frame Branch Register */
+#define DFBR1		0x44000024  /* DMA Channel 1 Frame Branch Register */
+#define LCSR0		0x44000038  /* LCD Controller Status Register */
+#define LCSR1		0x44000034  /* LCD Controller Status Register */
+#define LIIDR		0x4400003C  /* LCD Controller Interrupt ID Register */
+#define TMEDRGBR	0x44000040  /* TMED RGB Seed Register */
+#define TMEDCR		0x44000044  /* TMED Control Register */
+
+#define FDADR0		0x44000200  /* DMA Channel 0 Frame Descriptor Address Register */
+#define FSADR0		0x44000204  /* DMA Channel 0 Frame Source Address Register */
+#define FIDR0		0x44000208  /* DMA Channel 0 Frame ID Register */
+#define LDCMD0		0x4400020C  /* DMA Channel 0 Command Register */
+#define FDADR1		0x44000210  /* DMA Channel 1 Frame Descriptor Address Register */
+#define FSADR1		0x44000214  /* DMA Channel 1 Frame Source Address Register */
+#define FIDR1		0x44000218  /* DMA Channel 1 Frame ID Register */
+#define LDCMD1		0x4400021C  /* DMA Channel 1 Command Register */
+
+#define LCCR0_ENB	(1 << 0)	/* LCD Controller enable */
+#define LCCR0_CMS	(1 << 1)	/* Color = 0, Monochrome = 1 */
+#define LCCR0_SDS	(1 << 2)	/* Single Panel = 0, Dual Panel = 1 */
+#define LCCR0_LDM	(1 << 3)	/* LCD Disable Done Mask */
+#define LCCR0_SFM	(1 << 4)	/* Start of frame mask */
+#define LCCR0_IUM	(1 << 5)	/* Input FIFO underrun mask */
+#define LCCR0_EFM	(1 << 6)	/* End of Frame mask */
+#define LCCR0_PAS	(1 << 7)	/* Passive = 0, Active = 1 */
+#define LCCR0_BLE	(1 << 8)	/* Little Endian = 0, Big Endian = 1 */
+#define LCCR0_DPD	(1 << 9)	/* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
+#define LCCR0_DIS	(1 << 10)	/* LCD Disable */
+#define LCCR0_QDM	(1 << 11)	/* LCD Quick Disable mask */
+#define LCCR0_PDD	(0xff << 12)	/* Palette DMA request delay */
+#define LCCR0_PDD_S	12
+#define LCCR0_BM	(1 << 20)	/* Branch mask */
+#define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
+#if defined(CONFIG_CPU_PXA27X)
+#define LCCR0_LCDT	(1 << 22)	/* LCD Panel Type */
+#define LCCR0_RDSTM	(1 << 23)	/* Read Status Interrupt Mask */
+#define LCCR0_CMDIM	(1 << 24)	/* Command Interrupt Mask */
+#endif
+
+#define LCCR1_PPL	Fld (10, 0)	 /* Pixels Per Line - 1 */
+#define LCCR1_DisWdth(Pixel)		/* Display Width [1..800 pix.]	*/ \
+			(((Pixel) - 1) << FShft (LCCR1_PPL))
+
+#define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization	  */
+#define LCCR1_HorSnchWdth(Tpix)		/* Horizontal Synchronization	  */ \
+					/* pulse Width [1..64 Tpix]	  */ \
+			(((Tpix) - 1) << FShft (LCCR1_HSW))
+
+#define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait	   */
+					/* count - 1 [Tpix]		   */
+#define LCCR1_EndLnDel(Tpix)		/*  End-of-Line Delay		   */ \
+					/*  [1..256 Tpix]		   */ \
+			(((Tpix) - 1) << FShft (LCCR1_ELW))
+
+#define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock   */
+					/* Wait count - 1 [Tpix]	   */
+#define LCCR1_BegLnDel(Tpix)		/*  Beginning-of-Line Delay	   */ \
+					/*  [1..256 Tpix]		   */ \
+			(((Tpix) - 1) << FShft (LCCR1_BLW))
+
+
+#define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1		   */
+#define LCCR2_DisHght(Line)		/*  Display Height [1..1024 lines] */ \
+			(((Line) - 1) << FShft (LCCR2_LPP))
+
+#define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse  */
+					/* Width - 1 [Tln] (L_FCLK)	   */
+#define LCCR2_VrtSnchWdth(Tln)		/*  Vertical Synchronization pulse */ \
+					/*  Width [1..64 Tln]		   */ \
+			(((Tln) - 1) << FShft (LCCR2_VSW))
+
+#define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait	   */
+					/* count [Tln]			   */
+#define LCCR2_EndFrmDel(Tln)		/*  End-of-Frame Delay		   */ \
+					/*  [0..255 Tln]		   */ \
+			((Tln) << FShft (LCCR2_EFW))
+
+#define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock   */
+					/* Wait count [Tln]		   */
+#define LCCR2_BegFrmDel(Tln)		/*  Beginning-of-Frame Delay	   */ \
+					/*  [0..255 Tln]		   */ \
+			((Tln) << FShft (LCCR2_BFW))
+
+#define LCCR3_API	(0xf << 16)	/* AC Bias pin trasitions per interrupt */
+#define LCCR3_API_S	16
+#define LCCR3_VSP	(1 << 20)	/* vertical sync polarity */
+#define LCCR3_HSP	(1 << 21)	/* horizontal sync polarity */
+#define LCCR3_PCP	(1 << 22)	/* pixel clock polarity */
+#define LCCR3_OEP	(1 << 23)	/* output enable polarity */
+#define LCCR3_DPC	(1 << 27)	/* double pixel clock mode */
+
+#define LCCR3_PDFOR_0	 (0 << 30)
+#define LCCR3_PDFOR_1	 (1 << 30)
+#define LCCR3_PDFOR_2	 (2 << 30)
+#define LCCR3_PDFOR_3	 (3 << 30)
+
+
+#define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor */
+#define LCCR3_PixClkDiv(Div)		/* Pixel Clock Divisor */ \
+			(((Div) << FShft (LCCR3_PCD)))
+
+
+#define LCCR3_BPP	Fld (3, 24)	/* Bit Per Pixel */
+#define LCCR3_Bpp(Bpp)			/* Bit Per Pixel */ \
+			((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26)))
+
+#define LCCR3_ACB	Fld (8, 8)	/* AC Bias */
+#define LCCR3_Acb(Acb)			/* BAC Bias */ \
+			(((Acb) << FShft (LCCR3_ACB)))
+
+#define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  Horizontal Synchronization	   */
+					/*  pulse active High		   */
+#define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  Horizontal Synchronization	   */
+
+#define LCCR3_VrtSnchH	(LCCR3_VSP*0)	/*  Vertical Synchronization pulse */
+					/*  active High			   */
+#define LCCR3_VrtSnchL	(LCCR3_VSP*1)	/*  Vertical Synchronization pulse */
+					/*  active Low			   */
+
+#define LCSR0_LDD	(1 << 0)	/* LCD Disable Done */
+#define LCSR0_SOF	(1 << 1)	/* Start of frame */
+#define LCSR0_BER	(1 << 2)	/* Bus error */
+#define LCSR0_ABC	(1 << 3)	/* AC Bias count */
+#define LCSR0_IUL	(1 << 4)	/* input FIFO underrun Lower panel */
+#define LCSR0_IUU	(1 << 5)	/* input FIFO underrun Upper panel */
+#define LCSR0_OU	(1 << 6)	/* output FIFO underrun */
+#define LCSR0_QD	(1 << 7)	/* quick disable */
+#define LCSR0_EOF0	(1 << 8)	/* end of frame */
+#define LCSR0_BS	(1 << 9)	/* branch status */
+#define LCSR0_SINT	(1 << 10)	/* subsequent interrupt */
+
+#define LCSR1_SOF1	(1 << 0)
+#define LCSR1_SOF2	(1 << 1)
+#define LCSR1_SOF3	(1 << 2)
+#define LCSR1_SOF4	(1 << 3)
+#define LCSR1_SOF5	(1 << 4)
+#define LCSR1_SOF6	(1 << 5)
+
+#define LCSR1_EOF1	(1 << 8)
+#define LCSR1_EOF2	(1 << 9)
+#define LCSR1_EOF3	(1 << 10)
+#define LCSR1_EOF4	(1 << 11)
+#define LCSR1_EOF5	(1 << 12)
+#define LCSR1_EOF6	(1 << 13)
+
+#define LCSR1_BS1	(1 << 16)
+#define LCSR1_BS2	(1 << 17)
+#define LCSR1_BS3	(1 << 18)
+#define LCSR1_BS4	(1 << 19)
+#define LCSR1_BS5	(1 << 20)
+#define LCSR1_BS6	(1 << 21)
+
+#define LCSR1_IU2	(1 << 25)
+#define LCSR1_IU3	(1 << 26)
+#define LCSR1_IU4	(1 << 27)
+#define LCSR1_IU5	(1 << 28)
+#define LCSR1_IU6	(1 << 29)
+
+#define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
+#if defined(CONFIG_CPU_PXA27X)
+#define LDCMD_SOFINT	(1 << 22)
+#define LDCMD_EOFINT	(1 << 21)
+#endif
+
+/*
+ * Memory controller
+ */
+
+#ifdef CONFIG_CPU_MONAHANS
+
+/* PXA3xx */
+
+/* Static Memory Controller Registers */
+#define	MSC0		0x4A000008 /* Static Memory Control Register 0 */
+#define	MSC1		0x4A00000C /* Static Memory Control Register 1 */
+#define	MECR		0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define	SXCNFG		0x4A00001C /* Synchronous Static Memory Control Register */
+#define	MCMEM0		0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */
+#define	MCATT0		0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define	MCIO0		0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */
+#define	MEMCLKCFG	0x4A000068 /* SCLK speed configuration */
+#define	CSADRCFG0	0x4A000080 /* Address Configuration for chip select 0 */
+#define	CSADRCFG1	0x4A000084 /* Address Configuration for chip select 1 */
+#define	CSADRCFG2	0x4A000088 /* Address Configuration for chip select 2 */
+#define	CSADRCFG3	0x4A00008C /* Address Configuration for chip select 3 */
+#define	CSADRCFG_P	0x4A000090 /* Address Configuration for pcmcia card interface */
+#define	CSMSADRCFG	0x4A0000A0 /* Master Address Configuration Register */
+#define	CLK_RET_DEL	0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */
+#define	ADV_RET_DEL	0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */
+
+/* Dynamic Memory Controller Registers */
+#define	MDCNFG		0x48100000 /* SDRAM Configuration Register 0 */
+#define	MDREFR		0x48100004 /* SDRAM Refresh Control Register */
+#define	FLYCNFG		0x48100020 /* Fly-by DMA DVAL[1:0] polarities */
+#define	MDMRS		0x48100040 /* MRS value to be written to SDRAM */
+#define	DDR_SCAL	0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */
+#define	DDR_HCAL	0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
+#define	DDR_WCAL	0x48100068 /* DDR Write Strobe Calibration Register */
+#define	DMCIER		0x48100070 /* Dynamic MC Interrupt Enable Register. */
+#define	DMCISR		0x48100078 /* Dynamic MC Interrupt Status Register. */
+#define	DDR_DLS		0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */
+#define	EMPI		0x48100090 /* EMPI Control Register */
+#define	RCOMP		0x48100100
+#define	PAD_MA		0x48100110
+#define	PAD_MDMSB	0x48100114
+#define	PAD_MDLSB	0x48100118
+#define	PAD_DMEM	0x4810011c
+#define	PAD_SDCLK	0x48100120
+#define	PAD_SDCS	0x48100124
+#define	PAD_SMEM	0x48100128
+#define	PAD_SCLK	0x4810012C
+#define	TAI		0x48100F00 /* TAI Tavor Address Isolation Register */
+
+/* Some frequently used bits */
+#define MDCNFG_DMAP	0x80000000	/* SDRAM 1GB Memory Map Enable */
+#define MDCNFG_DMCEN	0x40000000	/* Enable Dynamic Memory Controller */
+#define MDCNFG_HWFREQ	0x20000000	/* Hardware Frequency Change Calibration */
+#define MDCNFG_DTYPE	0x400		/* SDRAM Type: 1=DDR SDRAM */
+
+#define MDCNFG_DTC_0	0x0		/* Timing Category of SDRAM */
+#define MDCNFG_DTC_1	0x100
+#define MDCNFG_DTC_2	0x200
+#define MDCNFG_DTC_3	0x300
+
+#define MDCNFG_DRAC_12	0x0		/* Number of Row Access Bits */
+#define MDCNFG_DRAC_13	0x20
+#define MDCNFG_DRAC_14	0x40
+
+#define MDCNFG_DCAC_9	0x0		/* Number of Column Acess Bits */
+#define MDCNFG_DCAC_10	0x08
+#define MDCNFG_DCAC_11	0x10
+
+#define MDCNFG_DBW_16	0x4		/* SDRAM Data Bus width 16bit */
+#define MDCNFG_DCSE1	0x2		/* SDRAM CS 1 Enable */
+#define MDCNFG_DCSE0	0x1		/* SDRAM CS 0 Enable */
+
+
+/* Data Flash Controller Registers */
+
+#define NDCR		0x43100000  /* Data Flash Control register */
+#define NDTR0CS0	0x43100004  /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
+/* #define NDTR0CS1	0x43100008  /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
+#define NDTR1CS0	0x4310000C  /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
+/* #define NDTR1CS1	0x43100010  /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
+#define NDSR		0x43100014  /* Data Controller Status Register */
+#define NDPCR		0x43100018  /* Data Controller Page Count Register */
+#define NDBDR0		0x4310001C  /* Data Controller Bad Block Register 0 */
+#define NDBDR1		0x43100020  /* Data Controller Bad Block Register 1 */
+#define NDDB		0x43100040  /* Data Controller Data Buffer */
+#define NDCB0		0x43100048  /* Data Controller Command Buffer0 */
+#define NDCB1		0x4310004C  /* Data Controller Command Buffer1 */
+#define NDCB2		0x43100050  /* Data Controller Command Buffer2 */
+
+#define NDCR_SPARE_EN	(0x1<<31)
+#define NDCR_ECC_EN	(0x1<<30)
+#define NDCR_DMA_EN	(0x1<<29)
+#define NDCR_ND_RUN	(0x1<<28)
+#define NDCR_DWIDTH_C	(0x1<<27)
+#define NDCR_DWIDTH_M	(0x1<<26)
+#define NDCR_PAGE_SZ	(0x3<<24)
+#define NDCR_NCSX	(0x1<<23)
+#define NDCR_ND_STOP	(0x1<<22)
+/* reserved:
+ * #define NDCR_ND_MODE	(0x3<<21)
+ * #define NDCR_NAND_MODE   0x0 */
+#define NDCR_CLR_PG_CNT	(0x1<<20)
+#define NDCR_CLR_ECC	(0x1<<19)
+#define NDCR_RD_ID_CNT	(0x7<<16)
+#define NDCR_RA_START	(0x1<<15)
+#define NDCR_PG_PER_BLK	(0x1<<14)
+#define NDCR_ND_ARB_EN	(0x1<<12)
+#define NDCR_RDYM	(0x1<<11)
+#define NDCR_CS0_PAGEDM	(0x1<<10)
+#define NDCR_CS1_PAGEDM	(0x1<<9)
+#define NDCR_CS0_CMDDM	(0x1<<8)
+#define NDCR_CS1_CMDDM	(0x1<<7)
+#define NDCR_CS0_BBDM	(0x1<<6)
+#define NDCR_CS1_BBDM	(0x1<<5)
+#define NDCR_DBERRM	(0x1<<4)
+#define NDCR_SBERRM	(0x1<<3)
+#define NDCR_WRDREQM	(0x1<<2)
+#define NDCR_RDDREQM	(0x1<<1)
+#define NDCR_WRCMDREQM	(0x1)
+
+#define NDSR_RDY	(0x1<<11)
+#define NDSR_CS0_PAGED	(0x1<<10)
+#define NDSR_CS1_PAGED	(0x1<<9)
+#define NDSR_CS0_CMDD	(0x1<<8)
+#define NDSR_CS1_CMDD	(0x1<<7)
+#define NDSR_CS0_BBD	(0x1<<6)
+#define NDSR_CS1_BBD	(0x1<<5)
+#define NDSR_DBERR	(0x1<<4)
+#define NDSR_SBERR	(0x1<<3)
+#define NDSR_WRDREQ	(0x1<<2)
+#define NDSR_RDDREQ	(0x1<<1)
+#define NDSR_WRCMDREQ	(0x1)
+
+#define NDCB0_AUTO_RS	(0x1<<25)
+#define NDCB0_CSEL	(0x1<<24)
+#define NDCB0_CMD_TYPE	(0x7<<21)
+#define NDCB0_NC	(0x1<<20)
+#define NDCB0_DBC	(0x1<<19)
+#define NDCB0_ADDR_CYC	(0x7<<16)
+#define NDCB0_CMD2	(0xff<<8)
+#define NDCB0_CMD1	(0xff)
+#define MCMEM(s) MCMEM0
+#define MCATT(s) MCATT0
+#define MCIO(s) MCIO0
+#define MECR_CIT	(1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
+
+/* Maximum values for NAND Interface Timing Registers in DFC clock
+ * periods */
+#define DFC_MAX_tCH	7
+#define DFC_MAX_tCS	7
+#define DFC_MAX_tWH	7
+#define DFC_MAX_tWP	7
+#define DFC_MAX_tRH	7
+#define DFC_MAX_tRP	15
+#define DFC_MAX_tR	65535
+#define DFC_MAX_tWHR	15
+#define DFC_MAX_tAR	15
+
+#define DFC_CLOCK	104		/* DFC Clock is 104 MHz */
+#define DFC_CLK_PER_US	DFC_CLOCK/1000	/* clock period in ns */
+
+#else /* CONFIG_CPU_MONAHANS */
+
+/* PXA2xx */
+
+#define MEMC_BASE	0x48000000  /* Base of Memory Controller */
+#define MDCNFG_OFFSET	0x0
+#define MDREFR_OFFSET	0x4
+#define MSC0_OFFSET	0x8
+#define MSC1_OFFSET	0xC
+#define MSC2_OFFSET	0x10
+#define MECR_OFFSET	0x14
+#define SXLCR_OFFSET	0x18
+#define SXCNFG_OFFSET	0x1C
+#define FLYCNFG_OFFSET	0x20
+#define SXMRS_OFFSET	0x24
+#define MCMEM0_OFFSET	0x28
+#define MCMEM1_OFFSET	0x2C
+#define MCATT0_OFFSET	0x30
+#define MCATT1_OFFSET	0x34
+#define MCIO0_OFFSET	0x38
+#define MCIO1_OFFSET	0x3C
+#define MDMRS_OFFSET	0x40
+
+#define MDCNFG		0x48000000  /* SDRAM Configuration Register 0 */
+#define MDCNFG_DE0	0x00000001
+#define MDCNFG_DE1	0x00000002
+#define MDCNFG_DE2	0x00010000
+#define MDCNFG_DE3	0x00020000
+#define MDCNFG_DWID0	0x00000004
+
+#define MDREFR		0x48000004  /* SDRAM Refresh Control Register */
+#define MSC0		0x48000008  /* Static Memory Control Register 0 */
+#define MSC1		0x4800000C  /* Static Memory Control Register 1 */
+#define MSC2		0x48000010  /* Static Memory Control Register 2 */
+#define MECR		0x48000014  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR		0x48000018  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG		0x4800001C  /* Synchronous Static Memory Control Register */
+#define FLYCNFG		0x48000020
+#define SXMRS		0x48000024  /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0		0x48000028  /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1		0x4800002C  /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0		0x48000030  /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1		0x48000034  /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0		0x48000038  /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1		0x4800003C  /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS		0x48000040  /* MRS value to be written to SDRAM */
+#define BOOT_DEF	0x48000044  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+
+#define MDREFR_ALTREFA	(1 << 31)	/* Exiting Alternate Bus Master Mode Refresh Control */
+#define MDREFR_ALTREFB	(1 << 30)	/* Entering Alternate Bus Master Mode Refresh Control */
+#define MDREFR_K0DB4	(1 << 29)	/* SDCLK0 Divide by 4 Control/Status */
+#define MDREFR_K2FREE	(1 << 25)	/* SDRAM Free-Running Control */
+#define MDREFR_K1FREE	(1 << 24)	/* SDRAM Free-Running Control */
+#define MDREFR_K0FREE	(1 << 23)	/* SDRAM Free-Running Control */
+#define MDREFR_SLFRSH	(1 << 22)	/* SDRAM Self-Refresh Control/Status */
+#define MDREFR_APD	(1 << 20)	/* SDRAM/SSRAM Auto-Power-Down Enable */
+#define MDREFR_K2DB2	(1 << 19)	/* SDCLK2 Divide by 2 Control/Status */
+#define MDREFR_K2RUN	(1 << 18)	/* SDCLK2 Run Control/Status */
+#define MDREFR_K1DB2	(1 << 17)	/* SDCLK1 Divide by 2 Control/Status */
+#define MDREFR_K1RUN	(1 << 16)	/* SDCLK1 Run Control/Status */
+#define MDREFR_E1PIN	(1 << 15)	/* SDCKE1 Level Control/Status */
+#define MDREFR_K0DB2	(1 << 14)	/* SDCLK0 Divide by 2 Control/Status */
+#define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
+#define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
+
+#if defined(CONFIG_CPU_PXA27X)
+
+#define ARB_CNTRL	0x48000048  /* Arbiter Control Register */
+
+#define ARB_DMA_SLV_PARK	(1<<31)	   /* Be parked with DMA slave when idle */
+#define ARB_CI_PARK		(1<<30)	   /* Be parked with Camera Interface when idle */
+#define ARB_EX_MEM_PARK		(1<<29)	   /* Be parked with external MEMC when idle */
+#define ARB_INT_MEM_PARK	(1<<28)	   /* Be parked with internal MEMC when idle */
+#define ARB_USB_PARK		(1<<27)	   /* Be parked with USB when idle */
+#define ARB_LCD_PARK		(1<<26)	   /* Be parked with LCD when idle */
+#define ARB_DMA_PARK		(1<<25)	   /* Be parked with DMA when idle */
+#define ARB_CORE_PARK		(1<<24)	   /* Be parked with core when idle */
+#define ARB_LOCK_FLAG		(1<<23)	   /* Only Locking masters gain access to the bus */
+
+#endif /* CONFIG_CPU_PXA27X */
+
+/* LCD registers */
+#define LCCR4		0x44000010  /* LCD Controller Control Register 4 */
+#define LCCR5		0x44000014  /* LCD Controller Control Register 5 */
+#define FBR0		0x44000020  /* DMA Channel 0 Frame Branch Register */
+#define FBR1		0x44000024  /* DMA Channel 1 Frame Branch Register */
+#define FBR2		0x44000028  /* DMA Channel 2 Frame Branch Register */
+#define FBR3		0x4400002C  /* DMA Channel 3 Frame Branch Register */
+#define FBR4		0x44000030  /* DMA Channel 4 Frame Branch Register */
+#define FDADR2		0x44000220  /* DMA Channel 2 Frame Descriptor Address Register */
+#define FSADR2		0x44000224  /* DMA Channel 2 Frame Source Address Register */
+#define FIDR2		0x44000228  /* DMA Channel 2 Frame ID Register */
+#define LDCMD2		0x4400022C  /* DMA Channel 2 Command Register */
+#define FDADR3		0x44000230  /* DMA Channel 3 Frame Descriptor Address Register */
+#define FSADR3		0x44000234  /* DMA Channel 3 Frame Source Address Register */
+#define FIDR3		0x44000238  /* DMA Channel 3 Frame ID Register */
+#define LDCMD3		0x4400023C  /* DMA Channel 3 Command Register */
+#define FDADR4		0x44000240  /* DMA Channel 4 Frame Descriptor Address Register */
+#define FSADR4		0x44000244  /* DMA Channel 4 Frame Source Address Register */
+#define FIDR4		0x44000248  /* DMA Channel 4 Frame ID Register */
+#define LDCMD4		0x4400024C  /* DMA Channel 4 Command Register */
+#define FDADR5		0x44000250  /* DMA Channel 5 Frame Descriptor Address Register */
+#define FSADR5		0x44000254  /* DMA Channel 5 Frame Source Address Register */
+#define FIDR5		0x44000258  /* DMA Channel 5 Frame ID Register */
+#define LDCMD5		0x4400025C  /* DMA Channel 5 Command Register */
+
+#define OVL1C1		0x44000050  /* Overlay 1 Control Register 1 */
+#define OVL1C2		0x44000060  /* Overlay 1 Control Register 2 */
+#define OVL2C1		0x44000070  /* Overlay 2 Control Register 1 */
+#define OVL2C2		0x44000080  /* Overlay 2 Control Register 2 */
+#define CCR		0x44000090  /* Cursor Control Register */
+
+#define FBR5		0x44000110  /* DMA Channel 5 Frame Branch Register */
+#define FBR6		0x44000114  /* DMA Channel 6 Frame Branch Register */
+
+#define LCCR0_LDDALT	(1<<26)		/* LDD Alternate mapping bit when base pixel is RGBT16 */
+#define LCCR0_OUC	(1<<25)		/* Overlay Underlay Control Bit */
+
+#define LCCR5_SOFM1	(1<<0)		/* Start Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_SOFM2	(1<<1)		/* Start Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_SOFM3	(1<<2)		/* Start Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_SOFM4	(1<<3)		/* Start Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_SOFM5	(1<<4)		/* Start Of Frame Mask for cursor (channel 5) */
+#define LCCR5_SOFM6	(1<<5)		/* Start Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_EOFM1	(1<<8)		/* End Of Frame Mask for Overlay 1 (channel 1) */
+#define LCCR5_EOFM2	(1<<9)		/* End Of Frame Mask for Overlay 2 (channel 2) */
+#define LCCR5_EOFM3	(1<<10)		/* End Of Frame Mask for Overlay 2 (channel 3) */
+#define LCCR5_EOFM4	(1<<11)		/* End Of Frame Mask for Overlay 2 (channel 4) */
+#define LCCR5_EOFM5	(1<<12)		/* End Of Frame Mask for cursor (channel 5) */
+#define LCCR5_EOFM6	(1<<13)		/* End Of Frame Mask for command data (channel 6) */
+
+#define LCCR5_BSM1	(1<<16)		/* Branch mask for Overlay 1 (channel 1) */
+#define LCCR5_BSM2	(1<<17)		/* Branch mask for Overlay 2 (channel 2) */
+#define LCCR5_BSM3	(1<<18)		/* Branch mask for Overlay 2 (channel 3) */
+#define LCCR5_BSM4	(1<<19)		/* Branch mask for Overlay 2 (channel 4) */
+#define LCCR5_BSM5	(1<<20)		/* Branch mask for cursor (channel 5) */
+#define LCCR5_BSM6	(1<<21)		/* Branch mask for data command	 (channel 6) */
+
+#define LCCR5_IUM1	(1<<24)		/* Input FIFO Underrun Mask for Overlay 1  */
+#define LCCR5_IUM2	(1<<25)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM3	(1<<26)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM4	(1<<27)		/* Input FIFO Underrun Mask for Overlay 2  */
+#define LCCR5_IUM5	(1<<28)		/* Input FIFO Underrun Mask for cursor */
+#define LCCR5_IUM6	(1<<29)		/* Input FIFO Underrun Mask for data command */
+
+#define OVL1C1_O1EN	(1<<31)		/* Enable bit for Overlay 1 */
+#define OVL2C1_O2EN	(1<<31)		/* Enable bit for Overlay 2 */
+#define CCR_CEN		(1<<31)		/* Enable bit for Cursor */
+
+/* Keypad controller */
+
+#define KPC		0x41500000 /* Keypad Interface Control register */
+#define KPDK		0x41500008 /* Keypad Interface Direct Key register */
+#define KPREC		0x41500010 /* Keypad Intefcace Rotary Encoder register */
+#define KPMK		0x41500018 /* Keypad Intefcace Matrix Key register */
+#define KPAS		0x41500020 /* Keypad Interface Automatic Scan register */
+#define KPASMKP0	0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
+#define KPASMKP1	0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
+#define KPASMKP2	0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
+#define KPASMKP3	0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
+#define KPKDI		0x41500048 /* Keypad Interface Key Debounce Interval register */
+
+#define KPC_AS		(0x1 << 30)  /* Automatic Scan bit */
+#define KPC_ASACT	(0x1 << 29)  /* Automatic Scan on Activity */
+#define KPC_MI		(0x1 << 22)  /* Matrix interrupt bit */
+#define KPC_IMKP	(0x1 << 21)  /* Ignore Multiple Key Press */
+#define KPC_MS7		(0x1 << 20)  /* Matrix scan line 7 */
+#define KPC_MS6		(0x1 << 19)  /* Matrix scan line 6 */
+#define KPC_MS5		(0x1 << 18)  /* Matrix scan line 5 */
+#define KPC_MS4		(0x1 << 17)  /* Matrix scan line 4 */
+#define KPC_MS3		(0x1 << 16)  /* Matrix scan line 3 */
+#define KPC_MS2		(0x1 << 15)  /* Matrix scan line 2 */
+#define KPC_MS1		(0x1 << 14)  /* Matrix scan line 1 */
+#define KPC_MS0		(0x1 << 13)  /* Matrix scan line 0 */
+#define KPC_ME		(0x1 << 12)  /* Matrix Keypad Enable */
+#define KPC_MIE		(0x1 << 11)  /* Matrix Interrupt Enable */
+#define KPC_DK_DEB_SEL	(0x1 <<	 9)  /* Direct Key Debounce select */
+#define KPC_DI		(0x1 <<	 5)  /* Direct key interrupt bit */
+#define KPC_DEE0	(0x1 <<	 2)  /* Rotary Encoder 0 Enable */
+#define KPC_DE		(0x1 <<	 1)  /* Direct Keypad Enable */
+#define KPC_DIE		(0x1 <<	 0)  /* Direct Keypad interrupt Enable */
+
+#define KPDK_DKP	(0x1 << 31)
+#define KPDK_DK7	(0x1 <<	 7)
+#define KPDK_DK6	(0x1 <<	 6)
+#define KPDK_DK5	(0x1 <<	 5)
+#define KPDK_DK4	(0x1 <<	 4)
+#define KPDK_DK3	(0x1 <<	 3)
+#define KPDK_DK2	(0x1 <<	 2)
+#define KPDK_DK1	(0x1 <<	 1)
+#define KPDK_DK0	(0x1 <<	 0)
+
+#define KPREC_OF1	(0x1 << 31)
+#define kPREC_UF1	(0x1 << 30)
+#define KPREC_OF0	(0x1 << 15)
+#define KPREC_UF0	(0x1 << 14)
+
+#define KPMK_MKP	(0x1 << 31)
+#define KPAS_SO		(0x1 << 31)
+#define KPASMKPx_SO	(0x1 << 31)
+
+#define GPIO113_BIT	(1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
+#define PSLR		0x40F00034
+#define PSTR		0x40F00038  /* Power Manager Standby Configuration Reg */
+#define PSNR		0x40F0003C  /* Power Manager Sense Configuration Reg */
+#define PVCR		0x40F00040  /* Power Manager Voltage Change Control Reg */
+#define PKWR		0x40F00050  /* Power Manager KB Wake-Up Enable Reg */
+#define PKSR		0x40F00054  /* Power Manager KB Level-Detect Status Reg */
+#define OSMR4		0x40A00080  /* */
+#define OSCR4		0x40A00040  /* OS Timer Counter Register */
+#define OMCR4		0x40A000C0  /* */
+
+#endif	/* CONFIG_CPU_PXA27X */
+
+#endif	/* _PXA_REGS_H_ */
diff --git a/arch/arm/include/asm/arch-pxa/pxa.h b/arch/arm/include/asm/arch-pxa/pxa.h
new file mode 100644
index 0000000..428a848
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/pxa.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * PXA common functions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#ifndef	__PXA_H__
+#define	__PXA_H__
+
+#define PXA255_A0	0x00000106
+#define PXA250_C0	0x00000105
+#define PXA250_B2	0x00000104
+#define PXA250_B1	0x00000103
+#define PXA250_B0	0x00000102
+#define PXA250_A1	0x00000101
+#define PXA250_A0	0x00000100
+#define PXA210_C0	0x00000125
+#define PXA210_B2	0x00000124
+#define PXA210_B1	0x00000123
+#define PXA210_B0	0x00000122
+
+int cpu_is_pxa25x(void);
+int cpu_is_pxa27x(void);
+uint32_t pxa_get_cpu_revision(void);
+void pxa2xx_dram_init(void);
+
+#endif	/* __PXA_H__ */
diff --git a/arch/arm/include/asm/arch-pxa/regs-mmc.h b/arch/arm/include/asm/arch-pxa/regs-mmc.h
new file mode 100644
index 0000000..6d9a736
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/regs-mmc.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#ifndef __REGS_MMC_H__
+#define __REGS_MMC_H__
+
+#define MMC0_BASE	0x41100000
+#define MMC1_BASE	0x42000000
+
+int pxa_mmc_register(int card_index);
+
+struct pxa_mmc_regs {
+	uint32_t	strpcl;
+	uint32_t	stat;
+	uint32_t	clkrt;
+	uint32_t	spi;
+	uint32_t	cmdat;
+	uint32_t	resto;
+	uint32_t	rdto;
+	uint32_t	blklen;
+	uint32_t	nob;
+	uint32_t	prtbuf;
+	uint32_t	i_mask;
+	uint32_t	i_reg;
+	uint32_t	cmd;
+	uint32_t	argh;
+	uint32_t	argl;
+	uint32_t	res;
+	uint32_t	rxfifo;
+	uint32_t	txfifo;
+};
+
+/* MMC_STRPCL */
+#define MMC_STRPCL_STOP_CLK		(1 << 0)
+#define MMC_STRPCL_START_CLK		(1 << 1)
+
+/* MMC_STAT */
+#define MMC_STAT_END_CMD_RES		(1 << 13)
+#define MMC_STAT_PRG_DONE		(1 << 12)
+#define MMC_STAT_DATA_TRAN_DONE		(1 << 11)
+#define MMC_STAT_CLK_EN			(1 << 8)
+#define MMC_STAT_RECV_FIFO_FULL		(1 << 7)
+#define MMC_STAT_XMIT_FIFO_EMPTY	(1 << 6)
+#define MMC_STAT_RES_CRC_ERROR		(1 << 5)
+#define MMC_STAT_SPI_READ_ERROR_TOKEN	(1 << 4)
+#define MMC_STAT_CRC_READ_ERROR		(1 << 3)
+#define MMC_STAT_CRC_WRITE_ERROR	(1 << 2)
+#define MMC_STAT_TIME_OUT_RESPONSE	(1 << 1)
+#define MMC_STAT_READ_TIME_OUT		(1 << 0)
+
+/* MMC_CLKRT */
+#define MMC_CLKRT_20MHZ			0
+#define MMC_CLKRT_10MHZ			1
+#define MMC_CLKRT_5MHZ			2
+#define MMC_CLKRT_2_5MHZ		3
+#define MMC_CLKRT_1_25MHZ		4
+#define MMC_CLKRT_0_625MHZ		5
+#define MMC_CLKRT_0_3125MHZ		6
+
+/* MMC_SPI */
+#define MMC_SPI_EN			(1 << 0)
+#define MMC_SPI_CS_EN			(1 << 2)
+#define MMC_SPI_CS_ADDRESS		(1 << 3)
+#define MMC_SPI_CRC_ON			(1 << 1)
+
+/* MMC_CMDAT */
+#define MMC_CMDAT_SD_4DAT		(1 << 8)
+#define MMC_CMDAT_MMC_DMA_EN		(1 << 7)
+#define MMC_CMDAT_INIT			(1 << 6)
+#define MMC_CMDAT_BUSY			(1 << 5)
+#define MMC_CMDAT_BCR			(MMC_CMDAT_BUSY | MMC_CMDAT_INIT)
+#define MMC_CMDAT_STREAM		(1 << 4)
+#define MMC_CMDAT_WRITE			(1 << 3)
+#define MMC_CMDAT_DATA_EN		(1 << 2)
+#define MMC_CMDAT_R0			0
+#define MMC_CMDAT_R1			1
+#define MMC_CMDAT_R2			2
+#define MMC_CMDAT_R3			3
+
+/* MMC_RESTO */
+#define MMC_RES_TO_MAX_MASK		0x7f
+
+/* MMC_RDTO */
+#define MMC_READ_TO_MAX_MASK		0xffff
+
+/* MMC_BLKLEN */
+#define MMC_BLK_LEN_MAX_MASK		0x3ff
+
+/* MMC_PRTBUF */
+#define MMC_PRTBUF_BUF_PART_FULL	(1 << 0)
+
+/* MMC_I_MASK */
+#define MMC_I_MASK_TXFIFO_WR_REQ	(1 << 6)
+#define MMC_I_MASK_RXFIFO_RD_REQ	(1 << 5)
+#define MMC_I_MASK_CLK_IS_OFF		(1 << 4)
+#define MMC_I_MASK_STOP_CMD		(1 << 3)
+#define MMC_I_MASK_END_CMD_RES		(1 << 2)
+#define MMC_I_MASK_PRG_DONE		(1 << 1)
+#define MMC_I_MASK_DATA_TRAN_DONE	(1 << 0)
+#define MMC_I_MASK_ALL			0x7f
+
+
+/* MMC_I_REG */
+#define MMC_I_REG_TXFIFO_WR_REQ		(1 << 6)
+#define MMC_I_REG_RXFIFO_RD_REQ		(1 << 5)
+#define MMC_I_REG_CLK_IS_OFF		(1 << 4)
+#define MMC_I_REG_STOP_CMD		(1 << 3)
+#define MMC_I_REG_END_CMD_RES		(1 << 2)
+#define MMC_I_REG_PRG_DONE		(1 << 1)
+#define MMC_I_REG_DATA_TRAN_DONE	(1 << 0)
+
+/* MMC_CMD */
+#define MMC_CMD_INDEX_MAX		0x6f
+
+#define MMC_R1_IDLE_STATE		0x01
+#define MMC_R1_ERASE_STATE		0x02
+#define MMC_R1_ILLEGAL_CMD		0x04
+#define MMC_R1_COM_CRC_ERR		0x08
+#define MMC_R1_ERASE_SEQ_ERR		0x01
+#define MMC_R1_ADDR_ERR			0x02
+#define MMC_R1_PARAM_ERR		0x04
+
+#define MMC_R1B_WP_ERASE_SKIP		0x0002
+#define MMC_R1B_ERR			0x0004
+#define MMC_R1B_CC_ERR			0x0008
+#define MMC_R1B_CARD_ECC_ERR		0x0010
+#define MMC_R1B_WP_VIOLATION		0x0020
+#define MMC_R1B_ERASE_PARAM		0x0040
+#define MMC_R1B_OOR			0x0080
+#define MMC_R1B_IDLE_STATE		0x0100
+#define MMC_R1B_ERASE_RESET		0x0200
+#define MMC_R1B_ILLEGAL_CMD		0x0400
+#define MMC_R1B_COM_CRC_ERR		0x0800
+#define MMC_R1B_ERASE_SEQ_ERR		0x1000
+#define MMC_R1B_ADDR_ERR		0x2000
+#define MMC_R1B_PARAM_ERR		0x4000
+
+#endif	/* __REGS_MMC_H__ */
diff --git a/arch/arm/include/asm/arch-pxa/regs-uart.h b/arch/arm/include/asm/arch-pxa/regs-uart.h
new file mode 100644
index 0000000..bdd0a47
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/regs-uart.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#ifndef	__REGS_UART_H__
+#define	__REGS_UART_H__
+
+#define	FFUART_BASE		0x40100000
+#define	BTUART_BASE		0x40200000
+#define	STUART_BASE		0x40700000
+#define	HWUART_BASE		0x41600000
+
+struct pxa_uart_regs {
+	union {
+		uint32_t	thr;
+		uint32_t	rbr;
+		uint32_t	dll;
+	};
+	union {
+		uint32_t	ier;
+		uint32_t	dlh;
+	};
+	union {
+		uint32_t	fcr;
+		uint32_t	iir;
+	};
+	uint32_t	lcr;
+	uint32_t	mcr;
+	uint32_t	lsr;
+	uint32_t	msr;
+	uint32_t	spr;
+	uint32_t	isr;
+};
+
+#define	IER_DMAE	(1 << 7)
+#define	IER_UUE		(1 << 6)
+#define	IER_NRZE	(1 << 5)
+#define	IER_RTIOE	(1 << 4)
+#define	IER_MIE		(1 << 3)
+#define	IER_RLSE	(1 << 2)
+#define	IER_TIE		(1 << 1)
+#define	IER_RAVIE	(1 << 0)
+
+#define	IIR_FIFOES1	(1 << 7)
+#define	IIR_FIFOES0	(1 << 6)
+#define	IIR_TOD		(1 << 3)
+#define	IIR_IID2	(1 << 2)
+#define	IIR_IID1	(1 << 1)
+#define	IIR_IP		(1 << 0)
+
+#define	FCR_ITL2	(1 << 7)
+#define	FCR_ITL1	(1 << 6)
+#define	FCR_RESETTF	(1 << 2)
+#define	FCR_RESETRF	(1 << 1)
+#define	FCR_TRFIFOE	(1 << 0)
+#define	FCR_ITL_1	0
+#define	FCR_ITL_8	(FCR_ITL1)
+#define	FCR_ITL_16	(FCR_ITL2)
+#define	FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
+
+#define	LCR_DLAB	(1 << 7)
+#define	LCR_SB		(1 << 6)
+#define	LCR_STKYP	(1 << 5)
+#define	LCR_EPS		(1 << 4)
+#define	LCR_PEN		(1 << 3)
+#define	LCR_STB		(1 << 2)
+#define	LCR_WLS1	(1 << 1)
+#define	LCR_WLS0	(1 << 0)
+
+#define	LSR_FIFOE	(1 << 7)
+#define	LSR_TEMT	(1 << 6)
+#define	LSR_TDRQ	(1 << 5)
+#define	LSR_BI		(1 << 4)
+#define	LSR_FE		(1 << 3)
+#define	LSR_PE		(1 << 2)
+#define	LSR_OE		(1 << 1)
+#define	LSR_DR		(1 << 0)
+
+#define	MCR_LOOP	(1 << 4)
+#define	MCR_OUT2	(1 << 3)
+#define	MCR_OUT1	(1 << 2)
+#define	MCR_RTS		(1 << 1)
+#define	MCR_DTR		(1 << 0)
+
+#define	MSR_DCD		(1 << 7)
+#define	MSR_RI		(1 << 6)
+#define	MSR_DSR		(1 << 5)
+#define	MSR_CTS		(1 << 4)
+#define	MSR_DDCD	(1 << 3)
+#define	MSR_TERI	(1 << 2)
+#define	MSR_DDSR	(1 << 1)
+#define	MSR_DCTS	(1 << 0)
+
+#endif	/* __REGS_UART_H__ */
diff --git a/arch/arm/include/asm/arch-pxa/regs-usb.h b/arch/arm/include/asm/arch-pxa/regs-usb.h
new file mode 100644
index 0000000..e46887c
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/regs-usb.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * PXA25x UDC definitions
+ *
+ * Copyright (C) 2012 �ukasz Dałek <luk0104@gmail.com>
+ */
+
+#ifndef __REGS_USB_H__
+#define __REGS_USB_H__
+
+struct pxa25x_udc_regs {
+	/* UDC Control Register */
+	uint32_t	udccr; /* 0x000 */
+	uint32_t	reserved1;
+
+	/* UDC Control Function Register */
+	uint32_t	udccfr; /* 0x008 */
+	uint32_t	reserved2;
+
+	/* UDC Endpoint Control/Status Registers */
+	uint32_t	udccs[16]; /* 0x010 - 0x04c */
+
+	/* UDC Interrupt Control/Status Registers */
+	uint32_t	uicr0; /* 0x050 */
+	uint32_t	uicr1; /* 0x054 */
+	uint32_t	usir0; /* 0x058 */
+	uint32_t	usir1; /* 0x05c */
+
+	/* UDC Frame Number/Byte Count Registers */
+	uint32_t	ufnrh;  /* 0x060 */
+	uint32_t	ufnrl;  /* 0x064 */
+	uint32_t	ubcr2;  /* 0x068 */
+	uint32_t	ubcr4;  /* 0x06c */
+	uint32_t	ubcr7;  /* 0x070 */
+	uint32_t	ubcr9;  /* 0x074 */
+	uint32_t	ubcr12; /* 0x078 */
+	uint32_t	ubcr14; /* 0x07c */
+
+	/* UDC Endpoint Data Registers */
+	uint32_t	uddr0;  /* 0x080 */
+	uint32_t	reserved3[7];
+	uint32_t	uddr5;  /* 0x0a0 */
+	uint32_t	reserved4[7];
+	uint32_t	uddr10; /* 0x0c0 */
+	uint32_t	reserved5[7];
+	uint32_t	uddr15; /* 0x0e0 */
+	uint32_t	reserved6[7];
+	uint32_t	uddr1;  /* 0x100 */
+	uint32_t	reserved7[31];
+	uint32_t	uddr2;  /* 0x180 */
+	uint32_t	reserved8[31];
+	uint32_t	uddr3;  /* 0x200 */
+	uint32_t	reserved9[127];
+	uint32_t	uddr4;  /* 0x400 */
+	uint32_t	reserved10[127];
+	uint32_t	uddr6;  /* 0x600 */
+	uint32_t	reserved11[31];
+	uint32_t	uddr7;  /* 0x680 */
+	uint32_t	reserved12[31];
+	uint32_t	uddr8;  /* 0x700 */
+	uint32_t	reserved13[127];
+	uint32_t	uddr9;  /* 0x900 */
+	uint32_t	reserved14[127];
+	uint32_t	uddr11; /* 0xb00 */
+	uint32_t	reserved15[31];
+	uint32_t	uddr12; /* 0xb80 */
+	uint32_t	reserved16[31];
+	uint32_t	uddr13; /* 0xc00 */
+	uint32_t	reserved17[127];
+	uint32_t	uddr14; /* 0xe00 */
+
+};
+
+#define PXA25X_UDC_BASE		0x40600000
+
+#define UDCCR_UDE		(1 << 0)
+#define UDCCR_UDA		(1 << 1)
+#define UDCCR_RSM		(1 << 2)
+#define UDCCR_RESIR		(1 << 3)
+#define UDCCR_SUSIR		(1 << 4)
+#define UDCCR_SRM		(1 << 5)
+#define UDCCR_RSTIR		(1 << 6)
+#define UDCCR_REM		(1 << 7)
+
+/* Bulk IN endpoint 1/6/11 */
+#define UDCCS_BI_TSP		(1 << 7)
+#define UDCCS_BI_FST		(1 << 5)
+#define UDCCS_BI_SST		(1 << 4)
+#define UDCCS_BI_TUR		(1 << 3)
+#define UDCCS_BI_FTF		(1 << 2)
+#define UDCCS_BI_TPC		(1 << 1)
+#define UDCCS_BI_TFS		(1 << 0)
+
+/* Bulk OUT endpoint 2/7/12 */
+#define UDCCS_BO_RSP		(1 << 7)
+#define UDCCS_BO_RNE		(1 << 6)
+#define UDCCS_BO_FST		(1 << 5)
+#define UDCCS_BO_SST		(1 << 4)
+#define UDCCS_BO_DME		(1 << 3)
+#define UDCCS_BO_RPC		(1 << 1)
+#define UDCCS_BO_RFS		(1 << 0)
+
+/* Isochronous OUT endpoint 4/9/14 */
+#define UDCCS_IO_RSP		(1 << 7)
+#define UDCCS_IO_RNE		(1 << 6)
+#define UDCCS_IO_DME		(1 << 3)
+#define UDCCS_IO_ROF		(1 << 2)
+#define UDCCS_IO_RPC		(1 << 1)
+#define UDCCS_IO_RFS		(1 << 0)
+
+/* Control endpoint 0 */
+#define UDCCS0_OPR		(1 << 0)
+#define UDCCS0_IPR		(1 << 1)
+#define UDCCS0_FTF		(1 << 2)
+#define UDCCS0_DRWF		(1 << 3)
+#define UDCCS0_SST		(1 << 4)
+#define UDCCS0_FST		(1 << 5)
+#define UDCCS0_RNE		(1 << 6)
+#define UDCCS0_SA		(1 << 7)
+
+#define UICR0_IM0		(1 << 0)
+
+#define USIR0_IR0		(1 << 0)
+#define USIR0_IR1		(1 << 1)
+#define USIR0_IR2		(1 << 2)
+#define USIR0_IR3		(1 << 3)
+#define USIR0_IR4		(1 << 4)
+#define USIR0_IR5		(1 << 5)
+#define USIR0_IR6		(1 << 6)
+#define USIR0_IR7		(1 << 7)
+
+#define UDCCFR_AREN		(1 << 7) /* ACK response enable (now) */
+#define UDCCFR_ACM		(1 << 2) /* ACK control mode (wait for AREN) */
+/*
+ * Intel(R) PXA255 Processor Specification, September 2003 (page 31)
+ * define new "must be one" bits in UDCCFR (see Table 12-13.)
+ */
+#define UDCCFR_MB1		(0xff & ~(UDCCFR_AREN | UDCCFR_ACM))
+
+#define UFNRH_SIR		(1 << 7)	/* SOF interrupt request */
+#define UFNRH_SIM		(1 << 6)	/* SOF interrupt mask */
+#define UFNRH_IPE14		(1 << 5)	/* ISO packet error, ep14 */
+#define UFNRH_IPE9		(1 << 4)	/* ISO packet error, ep9 */
+#define UFNRH_IPE4		(1 << 3)	/* ISO packet error, ep4 */
+
+#endif /* __REGS_USB_H__ */
diff --git a/arch/arm/include/asm/arch-rk3036/boot0.h b/arch/arm/include/asm/arch-rk3036/boot0.h
new file mode 100644
index 0000000..2e78b07
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3036/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3036/gpio.h b/arch/arm/include/asm/arch-rk3036/gpio.h
new file mode 100644
index 0000000..eca79d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3036/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3128/boot0.h b/arch/arm/include/asm/arch-rk3128/boot0.h
new file mode 100644
index 0000000..2e78b07
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3128/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3128/gpio.h b/arch/arm/include/asm/arch-rk3128/gpio.h
new file mode 100644
index 0000000..eca79d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3128/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3188/boot0.h b/arch/arm/include/asm/arch-rk3188/boot0.h
new file mode 100644
index 0000000..2e78b07
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3188/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3188/gpio.h b/arch/arm/include/asm/arch-rk3188/gpio.h
new file mode 100644
index 0000000..eca79d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3188/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk322x/boot0.h b/arch/arm/include/asm/arch-rk322x/boot0.h
new file mode 100644
index 0000000..2e78b07
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk322x/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk322x/gpio.h b/arch/arm/include/asm/arch-rk322x/gpio.h
new file mode 100644
index 0000000..eca79d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk322x/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3288/boot0.h b/arch/arm/include/asm/arch-rk3288/boot0.h
new file mode 100644
index 0000000..2e78b07
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3288/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3288/gpio.h b/arch/arm/include/asm/arch-rk3288/gpio.h
new file mode 100644
index 0000000..eca79d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3288/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3328/boot0.h b/arch/arm/include/asm/arch-rk3328/boot0.h
new file mode 100644
index 0000000..2e78b07
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3328/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3328/gpio.h b/arch/arm/include/asm/arch-rk3328/gpio.h
new file mode 100644
index 0000000..eca79d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3328/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3368/boot0.h b/arch/arm/include/asm/arch-rk3368/boot0.h
new file mode 100644
index 0000000..2e78b07
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3368/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3368/gpio.h b/arch/arm/include/asm/arch-rk3368/gpio.h
new file mode 100644
index 0000000..eca79d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3368/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3399/boot0.h b/arch/arm/include/asm/arch-rk3399/boot0.h
new file mode 100644
index 0000000..2e78b07
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3399/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3399/gpio.h b/arch/arm/include/asm/arch-rk3399/gpio.h
new file mode 100644
index 0000000..eca79d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3399/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h
new file mode 100644
index 0000000..0c375e5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/boot0.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+/*
+ * Execution starts on the instruction following this 4-byte header
+ * (containing the magic 'RK30', 'RK31', 'RK32' or 'RK33').  This
+ * magic constant will be written into the final image by the rkimage
+ * tool, but we need to reserve space for it here.
+ *
+ * To make life easier for everyone, we build the SPL binary with
+ * space for this 4-byte header already included in the binary.
+ */
+#ifdef CONFIG_SPL_BUILD
+	/*
+	 * We need to add 4 bytes of space for the 'RK33' at the
+	 * beginning of the executable.	 However, as we want to keep
+	 * this generic and make it applicable to builds that are like
+	 * the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no
+	 * TPL, but extra space needed in the SPL), we simply insert
+	 * a branch-to-next-instruction-word with the expectation that
+	 * the first one may be overwritten, if this is the first stage
+	 * contained in the final image created with mkimage)...
+	 */
+	b 1f	 /* if overwritten, entry-address is at the next word */
+1:
+#endif
+#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
+	adr     r3, entry_counter
+	ldr	r0, [r3]
+	cmp	r0, #1           /* check if entry_counter == 1 */
+	beq	reset            /* regular bootup */
+	add     r0, #1
+	str	r0, [r3]         /* increment the entry_counter in memory */
+	mov     r0, #0           /* return 0 to the BROM to signal 'OK' */
+	bx	lr               /* return control to the BROM */
+entry_counter:
+	.word   0
+#endif
+
+#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64))
+	/* U-Boot proper of armv7 do not need this */
+	b reset
+#endif
+
+#if !defined(CONFIG_ARM64)
+	/*
+	 * For armv7, the addr '_start' will used as vector start address
+	 * and write to VBAR register, which needs to aligned to 0x20.
+	 */
+	.align(5), 0x0
+_start:
+	ARM_VECTORS
+#endif
+
+#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \
+	(CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
+	.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM	/* space for the ATF data */
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/boot_mode.h b/arch/arm/include/asm/arch-rockchip/boot_mode.h
new file mode 100644
index 0000000..6b2a610
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/boot_mode.h
@@ -0,0 +1,25 @@
+#ifndef __REBOOT_MODE_H
+#define __REBOOT_MODE_H
+
+/* high 24 bits is tag, low 8 bits is type */
+#define REBOOT_FLAG		0x5242C300
+/* normal boot */
+#define BOOT_NORMAL		(REBOOT_FLAG + 0)
+/* enter loader rockusb mode */
+#define BOOT_LOADER		(REBOOT_FLAG + 1)
+/* enter recovery */
+#define BOOT_RECOVERY		(REBOOT_FLAG + 3)
+/* enter fastboot mode */
+#define BOOT_FASTBOOT		(REBOOT_FLAG + 9)
+/* enter charging mode */
+#define BOOT_CHARGING		(REBOOT_FLAG + 11)
+/* enter usb mass storage mode */
+#define BOOT_UMS		(REBOOT_FLAG + 12)
+/* enter bootrom download mode */
+#define BOOT_BROM_DOWNLOAD	0xEF08A53C
+
+#ifndef __ASSEMBLY__
+int setup_boot_mode(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
new file mode 100644
index 0000000..0da78f3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2017 Heiko Stuebner <heiko@sntech.de>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#ifndef _ASM_ARCH_BOOTROM_H
+#define _ASM_ARCH_BOOTROM_H
+
+/*
+ * Saved Stack pointer address.
+ * Access might be needed in some special cases.
+ */
+extern u32 SAVE_SP_ADDR;
+
+/**
+ * back_to_bootrom() - return to bootrom (for TPL/SPL), passing a
+ *                     result code
+ *
+ * Transfer control back to the Rockchip BROM, restoring necessary
+ * register context and passing a command/result code to the BROM
+ * to instruct its next actions (e.g. continue boot sequence, enter
+ * download mode, ...).
+ *
+ * This function does not return.
+ *
+ * @brom_cmd: indicates how the bootrom should continue the boot
+ *            sequence (e.g. load the next stage)
+ */
+enum rockchip_bootrom_cmd {
+	/*
+	 * These can not start at 0, as 0 has a special meaning
+	 * for setjmp().
+	 */
+
+	BROM_BOOT_NEXTSTAGE = 1,  /* continue boot-sequence */
+	BROM_BOOT_ENTER_DNL,      /* have BROM enter download-mode */
+};
+
+void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd);
+
+/**
+ * Boot-device identifiers as used by the BROM
+ */
+enum {
+	BROM_BOOTSOURCE_NAND = 1,
+	BROM_BOOTSOURCE_EMMC = 2,
+	BROM_BOOTSOURCE_SPINOR = 3,
+	BROM_BOOTSOURCE_SPINAND = 4,
+	BROM_BOOTSOURCE_SD = 5,
+	BROM_BOOTSOURCE_USB = 10,
+	BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
+};
+
+extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1];
+
+/**
+ * Locations of the boot-device identifier in SRAM
+ */
+#define BROM_BOOTSOURCE_ID_ADDR   (CONFIG_IRAM_BASE + 0x10)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
new file mode 100644
index 0000000..0eb19ca
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_CLOCK_H
+#define _ASM_ARCH_CLOCK_H
+
+/* define pll mode */
+#define RKCLK_PLL_MODE_SLOW		0
+#define RKCLK_PLL_MODE_NORMAL		1
+
+enum {
+	ROCKCHIP_SYSCON_NOC,
+	ROCKCHIP_SYSCON_GRF,
+	ROCKCHIP_SYSCON_SGRF,
+	ROCKCHIP_SYSCON_PMU,
+	ROCKCHIP_SYSCON_PMUGRF,
+	ROCKCHIP_SYSCON_PMUSGRF,
+	ROCKCHIP_SYSCON_CIC,
+	ROCKCHIP_SYSCON_MSCH,
+};
+
+/* Standard Rockchip clock numbers */
+enum rk_clk_id {
+	CLK_OSC,
+	CLK_ARM,
+	CLK_DDR,
+	CLK_CODEC,
+	CLK_GENERAL,
+	CLK_NEW,
+
+	CLK_COUNT,
+};
+
+static inline int rk_pll_id(enum rk_clk_id clk_id)
+{
+	return clk_id - 1;
+}
+
+struct sysreset_reg {
+	unsigned int glb_srst_fst_value;
+	unsigned int glb_srst_snd_value;
+};
+
+struct softreset_reg {
+        void __iomem *base;
+        unsigned int sf_reset_offset;
+        unsigned int sf_reset_num;
+};
+
+/**
+ * clk_get_divisor() - Calculate the required clock divisior
+ *
+ * Given an input rate and a required output_rate, calculate the Rockchip
+ * divisor needed to achieve this.
+ *
+ * @input_rate:		Input clock rate in Hz
+ * @output_rate:	Output clock rate in Hz
+ * @return divisor register value to use
+ */
+static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
+{
+	uint clk_div;
+
+	clk_div = input_rate / output_rate;
+	clk_div = (clk_div + 1) & 0xfffe;
+
+	return clk_div;
+}
+
+/**
+ * rockchip_get_cru() - get a pointer to the clock/reset unit registers
+ *
+ * @return pointer to registers, or -ve error on error
+ */
+void *rockchip_get_cru(void);
+
+/**
+ * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
+ *
+ * @return pointer to registers, or -ve error on error
+ */
+void *rockchip_get_pmucru(void);
+
+struct rk3288_cru;
+struct rk3288_grf;
+
+void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
+
+int rockchip_get_clk(struct udevice **devp);
+
+/*
+ * rockchip_reset_bind() - Bind soft reset device as child of clock device
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * @return 0 success, or error value
+ */
+int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
new file mode 100644
index 0000000..4722522
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_CRU_RK3036_H
+#define _ASM_ARCH_CRU_RK3036_H
+
+#include <common.h>
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#define APLL_HZ		(600 * 1000000)
+#define GPLL_HZ		(594 * 1000000)
+
+#define CORE_PERI_HZ	150000000
+#define CORE_ACLK_HZ	300000000
+
+#define BUS_ACLK_HZ	148500000
+#define BUS_HCLK_HZ	148500000
+#define BUS_PCLK_HZ	74250000
+
+#define PERI_ACLK_HZ	148500000
+#define PERI_HCLK_HZ	148500000
+#define PERI_PCLK_HZ	74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3036_clk_priv {
+	struct rk3036_cru *cru;
+	ulong rate;
+};
+
+struct rk3036_cru {
+	struct rk3036_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+		unsigned int con3;
+	} pll[4];
+	unsigned int cru_mode_con;
+	unsigned int cru_clksel_con[35];
+	unsigned int cru_clkgate_con[11];
+	unsigned int reserved;
+	unsigned int cru_glb_srst_fst_value;
+	unsigned int cru_glb_srst_snd_value;
+	unsigned int reserved1[2];
+	unsigned int cru_softrst_con[9];
+	unsigned int cru_misc_con;
+	unsigned int reserved2[2];
+	unsigned int cru_glb_cnt_th;
+	unsigned int cru_sdmmc_con[2];
+	unsigned int cru_sdio_con[2];
+	unsigned int cru_emmc_con[2];
+	unsigned int reserved3;
+	unsigned int cru_rst_st;
+	unsigned int reserved4[0x23];
+	unsigned int cru_pll_mask_con;
+};
+check_member(rk3036_cru, cru_pll_mask_con, 0x01f0);
+
+struct pll_div {
+	u32 refdiv;
+	u32 fbdiv;
+	u32 postdiv1;
+	u32 postdiv2;
+	u32 frac;
+};
+
+enum {
+	/* PLLCON0*/
+	PLL_POSTDIV1_SHIFT	= 12,
+	PLL_POSTDIV1_MASK	= 7 << PLL_POSTDIV1_SHIFT,
+	PLL_FBDIV_SHIFT		= 0,
+	PLL_FBDIV_MASK		= 0xfff,
+
+	/* PLLCON1 */
+	PLL_RST_SHIFT		= 14,
+	PLL_DSMPD_SHIFT		= 12,
+	PLL_DSMPD_MASK		= 1 << PLL_DSMPD_SHIFT,
+	PLL_LOCK_STATUS_SHIFT	= 10,
+	PLL_LOCK_STATUS_MASK	= 1 << PLL_LOCK_STATUS_SHIFT,
+	PLL_POSTDIV2_SHIFT	= 6,
+	PLL_POSTDIV2_MASK	= 7 << PLL_POSTDIV2_SHIFT,
+	PLL_REFDIV_SHIFT	= 0,
+	PLL_REFDIV_MASK		= 0x3f,
+
+	/* CRU_MODE */
+	GPLL_MODE_SHIFT		= 12,
+	GPLL_MODE_MASK		= 3 << GPLL_MODE_SHIFT,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORM,
+	GPLL_MODE_DEEP,
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 1 << DPLL_MODE_SHIFT,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORM,
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 1 << APLL_MODE_SHIFT,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORM,
+
+	/* CRU_CLK_SEL0_CON */
+	BUS_ACLK_PLL_SEL_SHIFT	= 14,
+	BUS_ACLK_PLL_SEL_MASK	= 3 << BUS_ACLK_PLL_SEL_SHIFT,
+	BUS_ACLK_PLL_SEL_APLL	= 0,
+	BUS_ACLK_PLL_SEL_DPLL,
+	BUS_ACLK_PLL_SEL_GPLL,
+	BUS_ACLK_DIV_SHIFT	= 8,
+	BUS_ACLK_DIV_MASK	= 0x1f << BUS_ACLK_DIV_SHIFT,
+	CORE_CLK_PLL_SEL_SHIFT	= 7,
+	CORE_CLK_PLL_SEL_MASK	= 1 << CORE_CLK_PLL_SEL_SHIFT,
+	CORE_CLK_PLL_SEL_APLL	= 0,
+	CORE_CLK_PLL_SEL_GPLL,
+	CORE_DIV_CON_SHIFT	= 0,
+	CORE_DIV_CON_MASK	= 0x1f << CORE_DIV_CON_SHIFT,
+
+	/* CRU_CLK_SEL1_CON */
+	BUS_PCLK_DIV_SHIFT	= 12,
+	BUS_PCLK_DIV_MASK	= 7 << BUS_PCLK_DIV_SHIFT,
+	BUS_HCLK_DIV_SHIFT	= 8,
+	BUS_HCLK_DIV_MASK	= 3 << BUS_HCLK_DIV_SHIFT,
+	CORE_ACLK_DIV_SHIFT	= 4,
+	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
+	CORE_PERI_DIV_SHIFT	= 0,
+	CORE_PERI_DIV_MASK	= 0xf << CORE_PERI_DIV_SHIFT,
+
+	/* CRU_CLKSEL10_CON */
+	PERI_PLL_SEL_SHIFT	= 14,
+	PERI_PLL_SEL_MASK	= 3 << PERI_PLL_SEL_SHIFT,
+	PERI_PLL_APLL		= 0,
+	PERI_PLL_DPLL,
+	PERI_PLL_GPLL,
+	PERI_PCLK_DIV_SHIFT	= 12,
+	PERI_PCLK_DIV_MASK	= 3 << PERI_PCLK_DIV_SHIFT,
+	PERI_HCLK_DIV_SHIFT	= 8,
+	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
+	PERI_ACLK_DIV_SHIFT	= 0,
+	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
+
+	/* CRU_CLKSEL11_CON */
+	SDIO_DIV_SHIFT		= 8,
+	SDIO_DIV_MASK		= 0x7f << SDIO_DIV_SHIFT,
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0x7f << MMC0_DIV_SHIFT,
+
+	/* CRU_CLKSEL12_CON */
+	EMMC_PLL_SHIFT		= 12,
+	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
+	EMMC_SEL_APLL		= 0,
+	EMMC_SEL_DPLL,
+	EMMC_SEL_GPLL,
+	EMMC_SEL_24M,
+	SDIO_PLL_SHIFT		= 10,
+	SDIO_PLL_MASK		= 3 << SDIO_PLL_SHIFT,
+	SDIO_SEL_APLL		= 0,
+	SDIO_SEL_DPLL,
+	SDIO_SEL_GPLL,
+	SDIO_SEL_24M,
+	MMC0_PLL_SHIFT		= 8,
+	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
+	MMC0_SEL_APLL		= 0,
+	MMC0_SEL_DPLL,
+	MMC0_SEL_GPLL,
+	MMC0_SEL_24M,
+	EMMC_DIV_SHIFT		= 0,
+	EMMC_DIV_MASK		= 0x7f << EMMC_DIV_SHIFT,
+
+	/* CRU_SOFTRST5_CON */
+	DDRCTRL_PSRST_SHIFT	= 11,
+	DDRCTRL_SRST_SHIFT	= 10,
+	DDRPHY_PSRST_SHIFT	= 9,
+	DDRPHY_SRST_SHIFT	= 8,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
new file mode 100644
index 0000000..b856560
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3128_H
+#define _ASM_ARCH_CRU_RK3128_H
+
+#include <common.h>
+
+#define MHz		1000000
+#define OSC_HZ		(24 * MHz)
+
+#define APLL_HZ		(600 * MHz)
+#define GPLL_HZ		(594 * MHz)
+
+#define CORE_PERI_HZ	150000000
+#define CORE_ACLK_HZ	300000000
+
+#define BUS_ACLK_HZ	148500000
+#define BUS_HCLK_HZ	148500000
+#define BUS_PCLK_HZ	74250000
+
+#define PERI_ACLK_HZ	148500000
+#define PERI_HCLK_HZ	148500000
+#define PERI_PCLK_HZ	74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3128_clk_priv {
+	struct rk3128_cru *cru;
+};
+
+struct rk3128_cru {
+	struct rk3128_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+		unsigned int con3;
+	} pll[4];
+	unsigned int cru_mode_con;
+	unsigned int cru_clksel_con[35];
+	unsigned int cru_clkgate_con[11];
+	unsigned int reserved;
+	unsigned int cru_glb_srst_fst_value;
+	unsigned int cru_glb_srst_snd_value;
+	unsigned int reserved1[2];
+	unsigned int cru_softrst_con[9];
+	unsigned int cru_misc_con;
+	unsigned int reserved2[2];
+	unsigned int cru_glb_cnt_th;
+	unsigned int reserved3[3];
+	unsigned int cru_glb_rst_st;
+	unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1];
+	unsigned int cru_sdmmc_con[2];
+	unsigned int cru_sdio_con[2];
+	unsigned int reserved5[2];
+	unsigned int cru_emmc_con[2];
+	unsigned int reserved6[4];
+	unsigned int cru_pll_prg_en;
+};
+check_member(rk3128_cru, cru_pll_prg_en, 0x01f0);
+
+struct pll_div {
+	u32 refdiv;
+	u32 fbdiv;
+	u32 postdiv1;
+	u32 postdiv2;
+	u32 frac;
+};
+
+enum {
+	/* PLLCON0*/
+	PLL_POSTDIV1_SHIFT	= 12,
+	PLL_POSTDIV1_MASK	= 7 << PLL_POSTDIV1_SHIFT,
+	PLL_FBDIV_SHIFT		= 0,
+	PLL_FBDIV_MASK		= 0xfff,
+
+	/* PLLCON1 */
+	PLL_RST_SHIFT		= 14,
+	PLL_PD_SHIFT		= 13,
+	PLL_PD_MASK		= 1 << PLL_PD_SHIFT,
+	PLL_DSMPD_SHIFT		= 12,
+	PLL_DSMPD_MASK		= 1 << PLL_DSMPD_SHIFT,
+	PLL_LOCK_STATUS_SHIFT	= 10,
+	PLL_LOCK_STATUS_MASK	= 1 << PLL_LOCK_STATUS_SHIFT,
+	PLL_POSTDIV2_SHIFT	= 6,
+	PLL_POSTDIV2_MASK	= 7 << PLL_POSTDIV2_SHIFT,
+	PLL_REFDIV_SHIFT	= 0,
+	PLL_REFDIV_MASK		= 0x3f,
+
+	/* CRU_MODE */
+	GPLL_MODE_SHIFT		= 12,
+	GPLL_MODE_MASK		= 3 << GPLL_MODE_SHIFT,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORM,
+	GPLL_MODE_DEEP,
+	CPLL_MODE_SHIFT		= 8,
+	CPLL_MODE_MASK		= 1 << CPLL_MODE_SHIFT,
+	CPLL_MODE_SLOW		= 0,
+	CPLL_MODE_NORM,
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 1 << DPLL_MODE_SHIFT,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORM,
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 1 << APLL_MODE_SHIFT,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORM,
+
+	/* CRU_CLK_SEL0_CON */
+	BUS_ACLK_PLL_SEL_SHIFT	= 14,
+	BUS_ACLK_PLL_SEL_MASK	= 3 << BUS_ACLK_PLL_SEL_SHIFT,
+	BUS_ACLK_PLL_SEL_CPLL	= 0,
+	BUS_ACLK_PLL_SEL_GPLL,
+	BUS_ACLK_PLL_SEL_GPLL_DIV2,
+	BUS_ACLK_PLL_SEL_GPLL_DIV3,
+	BUS_ACLK_DIV_SHIFT	= 8,
+	BUS_ACLK_DIV_MASK	= 0x1f << BUS_ACLK_DIV_SHIFT,
+	CORE_CLK_PLL_SEL_SHIFT	= 7,
+	CORE_CLK_PLL_SEL_MASK	= 1 << CORE_CLK_PLL_SEL_SHIFT,
+	CORE_CLK_PLL_SEL_APLL	= 0,
+	CORE_CLK_PLL_SEL_GPLL_DIV2,
+	CORE_DIV_CON_SHIFT	= 0,
+	CORE_DIV_CON_MASK	= 0x1f << CORE_DIV_CON_SHIFT,
+
+	/* CRU_CLK_SEL1_CON */
+	BUS_PCLK_DIV_SHIFT	= 12,
+	BUS_PCLK_DIV_MASK	= 7 << BUS_PCLK_DIV_SHIFT,
+	BUS_HCLK_DIV_SHIFT	= 8,
+	BUS_HCLK_DIV_MASK	= 3 << BUS_HCLK_DIV_SHIFT,
+	CORE_ACLK_DIV_SHIFT	= 4,
+	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
+	CORE_PERI_DIV_SHIFT	= 0,
+	CORE_PERI_DIV_MASK	= 0xf << CORE_PERI_DIV_SHIFT,
+
+	/* CRU_CLK_SEL2_CON */
+	NANDC_PLL_SEL_SHIFT	= 14,
+	NANDC_PLL_SEL_MASK	= 3 << NANDC_PLL_SEL_SHIFT,
+	NANDC_PLL_SEL_CPLL	= 0,
+	NANDC_PLL_SEL_GPLL,
+	NANDC_CLK_DIV_SHIFT	= 8,
+	NANDC_CLK_DIV_MASK	= 0x1f << NANDC_CLK_DIV_SHIFT,
+	PVTM_CLK_DIV_SHIFT	= 0,
+	PVTM_CLK_DIV_MASK	= 0x3f << PVTM_CLK_DIV_SHIFT,
+
+	/* CRU_CLKSEL10_CON */
+	PERI_PLL_SEL_SHIFT	= 14,
+	PERI_PLL_SEL_MASK	= 1 << PERI_PLL_SEL_SHIFT,
+	PERI_PLL_APLL		= 0,
+	PERI_PLL_DPLL,
+	PERI_PLL_GPLL,
+	PERI_PCLK_DIV_SHIFT	= 12,
+	PERI_PCLK_DIV_MASK	= 3 << PERI_PCLK_DIV_SHIFT,
+	PERI_HCLK_DIV_SHIFT	= 8,
+	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
+	PERI_ACLK_DIV_SHIFT	= 0,
+	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
+
+	/* CRU_CLKSEL11_CON */
+	MMC0_PLL_SHIFT		= 6,
+	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
+	MMC0_SEL_APLL		= 0,
+	MMC0_SEL_GPLL,
+	MMC0_SEL_GPLL_DIV2,
+	MMC0_SEL_24M,
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0x3f << MMC0_DIV_SHIFT,
+
+	/* CRU_CLKSEL12_CON */
+	EMMC_PLL_SHIFT		= 14,
+	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
+	EMMC_SEL_APLL		= 0,
+	EMMC_SEL_GPLL,
+	EMMC_SEL_GPLL_DIV2,
+	EMMC_SEL_24M,
+	EMMC_DIV_SHIFT		= 8,
+	EMMC_DIV_MASK		= 0x3f << EMMC_DIV_SHIFT,
+
+	/* CLKSEL_CON24 */
+	SARADC_DIV_CON_SHIFT	= 8,
+	SARADC_DIV_CON_MASK	= GENMASK(15, 8),
+	SARADC_DIV_CON_WIDTH	= 8,
+
+	/* CRU_CLKSEL27_CON*/
+	DCLK_VOP_SEL_SHIFT         = 0,
+	DCLK_VOP_SEL_MASK          = 1 << DCLK_VOP_SEL_SHIFT,
+	DCLK_VOP_PLL_SEL_CPLL           = 0,
+	DCLK_VOP_DIV_CON_SHIFT          = 8,
+	DCLK_VOP_DIV_CON_MASK           = 0xff << DCLK_VOP_DIV_CON_SHIFT,
+
+	/* CRU_CLKSEL31_CON */
+	VIO0_PLL_SHIFT		= 5,
+	VIO0_PLL_MASK		= 7 << VIO0_PLL_SHIFT,
+	VI00_SEL_CPLL		= 0,
+	VIO0_SEL_GPLL,
+	VIO0_DIV_SHIFT		= 0,
+	VIO0_DIV_MASK		= 0x1f << VIO0_DIV_SHIFT,
+	VIO1_PLL_SHIFT		= 13,
+	VIO1_PLL_MASK		= 7 << VIO1_PLL_SHIFT,
+	VI01_SEL_CPLL		= 0,
+	VIO1_SEL_GPLL,
+	VIO1_DIV_SHIFT		= 8,
+	VIO1_DIV_MASK		= 0x1f << VIO1_DIV_SHIFT,
+
+	/* CRU_SOFTRST5_CON */
+	DDRCTRL_PSRST_SHIFT	= 11,
+	DDRCTRL_SRST_SHIFT	= 10,
+	DDRPHY_PSRST_SHIFT	= 9,
+	DDRPHY_SRST_SHIFT	= 8,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h
new file mode 100644
index 0000000..eec4815
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
+ */
+#ifndef _ASM_ARCH_CRU_RK3188_H
+#define _ASM_ARCH_CRU_RK3188_H
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#define APLL_HZ		(1608 * 1000000)
+#define APLL_SAFE_HZ	(600 * 1000000)
+#define GPLL_HZ		(594 * 1000000)
+#define CPLL_HZ		(384 * 1000000)
+
+/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
+#define CPU_ACLK_HZ	297000000
+#define CPU_HCLK_HZ	148500000
+#define CPU_PCLK_HZ	74250000
+#define CPU_H2P_HZ	74250000
+
+#define PERI_ACLK_HZ	148500000
+#define PERI_HCLK_HZ	148500000
+#define PERI_PCLK_HZ	74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3188_clk_priv {
+	struct rk3188_grf *grf;
+	struct rk3188_cru *cru;
+	ulong rate;
+	bool has_bwadj;
+};
+
+struct rk3188_cru {
+	struct rk3188_pll {
+		u32 con0;
+		u32 con1;
+		u32 con2;
+		u32 con3;
+	} pll[4];
+	u32 cru_mode_con;
+	u32 cru_clksel_con[35];
+	u32 cru_clkgate_con[10];
+	u32 reserved1[2];
+	u32 cru_glb_srst_fst_value;
+	u32 cru_glb_srst_snd_value;
+	u32 reserved2[2];
+	u32 cru_softrst_con[9];
+	u32 cru_misc_con;
+	u32 reserved3[2];
+	u32 cru_glb_cnt_th;
+};
+check_member(rk3188_cru, cru_glb_cnt_th, 0x0140);
+
+/* CRU_CLKSEL0_CON */
+enum {
+	/* a9_core_div: core = core_src / (a9_core_div + 1) */
+	A9_CORE_DIV_SHIFT	= 9,
+	A9_CORE_DIV_MASK	= 0x1f,
+	CORE_PLL_SHIFT		= 8,
+	CORE_PLL_MASK		= 1,
+	CORE_PLL_SELECT_APLL	= 0,
+	CORE_PLL_SELECT_GPLL,
+
+	/* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
+	CORE_PERI_DIV_SHIFT	= 6,
+	CORE_PERI_DIV_MASK	= 3,
+
+	/* aclk_cpu pll selection */
+	CPU_ACLK_PLL_SHIFT	= 5,
+	CPU_ACLK_PLL_MASK	= 1,
+	CPU_ACLK_PLL_SELECT_APLL	= 0,
+	CPU_ACLK_PLL_SELECT_GPLL,
+
+	/* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
+	A9_CPU_DIV_SHIFT	= 0,
+	A9_CPU_DIV_MASK		= 0x1f,
+};
+
+/* CRU_CLKSEL1_CON */
+enum {
+	/* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
+	AHB2APB_DIV_SHIFT	= 14,
+	AHB2APB_DIV_MASK	= 3,
+
+	/* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
+	CPU_PCLK_DIV_SHIFT	= 12,
+	CPU_PCLK_DIV_MASK	= 3,
+
+	/* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
+	CPU_HCLK_DIV_SHIFT	= 8,
+	CPU_HCLK_DIV_MASK	= 3,
+
+	/* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
+	CORE_ACLK_DIV_SHIFT	= 3,
+	CORE_ACLK_DIV_MASK	= 7,
+};
+
+/* CRU_CLKSEL10_CON */
+enum {
+	PERI_SEL_PLL_MASK	= 1,
+	PERI_SEL_PLL_SHIFT	= 15,
+	PERI_SEL_CPLL		= 0,
+	PERI_SEL_GPLL,
+
+	/* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
+	PERI_PCLK_DIV_SHIFT	= 12,
+	PERI_PCLK_DIV_MASK	= 3,
+
+	/* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
+	PERI_HCLK_DIV_SHIFT	= 8,
+	PERI_HCLK_DIV_MASK	= 3,
+
+	/* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
+	PERI_ACLK_DIV_SHIFT	= 0,
+	PERI_ACLK_DIV_MASK	= 0x1f,
+};
+/* CRU_CLKSEL11_CON */
+enum {
+	HSICPHY_DIV_SHIFT	= 8,
+	HSICPHY_DIV_MASK	= 0x3f,
+
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0x3f,
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+	UART_PLL_SHIFT		= 15,
+	UART_PLL_MASK		= 1,
+	UART_PLL_SELECT_GENERAL	= 0,
+	UART_PLL_SELECT_CODEC,
+
+	EMMC_DIV_SHIFT		= 8,
+	EMMC_DIV_MASK		= 0x3f,
+
+	SDIO_DIV_SHIFT		= 0,
+	SDIO_DIV_MASK		= 0x3f,
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+	SPI1_DIV_SHIFT		= 8,
+	SPI1_DIV_MASK		= 0x7f,
+
+	SPI0_DIV_SHIFT		= 0,
+	SPI0_DIV_MASK		= 0x7f,
+};
+
+/* CRU_MODE_CON */
+enum {
+	GPLL_MODE_SHIFT		= 12,
+	GPLL_MODE_MASK		= 3,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORMAL,
+	GPLL_MODE_DEEP,
+
+	CPLL_MODE_SHIFT		= 8,
+	CPLL_MODE_MASK		= 3,
+	CPLL_MODE_SLOW		= 0,
+	CPLL_MODE_NORMAL,
+	CPLL_MODE_DEEP,
+
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 3,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORMAL,
+	DPLL_MODE_DEEP,
+
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 3,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORMAL,
+	APLL_MODE_DEEP,
+};
+
+/* CRU_APLL_CON0 */
+enum {
+	CLKR_SHIFT		= 8,
+	CLKR_MASK		= 0x3f,
+
+	CLKOD_SHIFT		= 0,
+	CLKOD_MASK		= 0x3f,
+};
+
+/* CRU_APLL_CON1 */
+enum {
+	CLKF_SHIFT		= 0,
+	CLKF_MASK		= 0x1fff,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
new file mode 100644
index 0000000..c87c830
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_CRU_RK322X_H
+#define _ASM_ARCH_CRU_RK322X_H
+
+#include <common.h>
+
+#define MHz		1000000
+#define OSC_HZ		(24 * MHz)
+
+#define APLL_HZ		(600 * MHz)
+#define GPLL_HZ		(594 * MHz)
+
+#define CORE_PERI_HZ	150000000
+#define CORE_ACLK_HZ	300000000
+
+#define BUS_ACLK_HZ	148500000
+#define BUS_HCLK_HZ	148500000
+#define BUS_PCLK_HZ	74250000
+
+#define PERI_ACLK_HZ	148500000
+#define PERI_HCLK_HZ	148500000
+#define PERI_PCLK_HZ	74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk322x_clk_priv {
+	struct rk322x_cru *cru;
+	ulong rate;
+};
+
+struct rk322x_cru {
+	struct rk322x_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+	} pll[4];
+	unsigned int reserved0[4];
+	unsigned int cru_mode_con;
+	unsigned int cru_clksel_con[35];
+	unsigned int cru_clkgate_con[16];
+	unsigned int cru_softrst_con[9];
+	unsigned int cru_misc_con;
+	unsigned int reserved1[2];
+	unsigned int cru_glb_cnt_th;
+	unsigned int reserved2[3];
+	unsigned int cru_glb_rst_st;
+	unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1];
+	unsigned int cru_sdmmc_con[2];
+	unsigned int cru_sdio_con[2];
+	unsigned int reserved4[2];
+	unsigned int cru_emmc_con[2];
+	unsigned int reserved5[4];
+	unsigned int cru_glb_srst_fst_value;
+	unsigned int cru_glb_srst_snd_value;
+	unsigned int cru_pll_mask_con;
+};
+check_member(rk322x_cru, cru_pll_mask_con, 0x01f8);
+
+struct pll_div {
+	u32 refdiv;
+	u32 fbdiv;
+	u32 postdiv1;
+	u32 postdiv2;
+	u32 frac;
+};
+
+enum {
+	/* PLLCON0*/
+	PLL_BP_SHIFT		= 15,
+	PLL_POSTDIV1_SHIFT	= 12,
+	PLL_POSTDIV1_MASK	= 7 << PLL_POSTDIV1_SHIFT,
+	PLL_FBDIV_SHIFT		= 0,
+	PLL_FBDIV_MASK		= 0xfff,
+
+	/* PLLCON1 */
+	PLL_RST_SHIFT		= 14,
+	PLL_PD_SHIFT		= 13,
+	PLL_PD_MASK		= 1 << PLL_PD_SHIFT,
+	PLL_DSMPD_SHIFT		= 12,
+	PLL_DSMPD_MASK		= 1 << PLL_DSMPD_SHIFT,
+	PLL_LOCK_STATUS_SHIFT	= 10,
+	PLL_LOCK_STATUS_MASK	= 1 << PLL_LOCK_STATUS_SHIFT,
+	PLL_POSTDIV2_SHIFT	= 6,
+	PLL_POSTDIV2_MASK	= 7 << PLL_POSTDIV2_SHIFT,
+	PLL_REFDIV_SHIFT	= 0,
+	PLL_REFDIV_MASK		= 0x3f,
+
+	/* CRU_MODE */
+	GPLL_MODE_SHIFT		= 12,
+	GPLL_MODE_MASK		= 1 << GPLL_MODE_SHIFT,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORM,
+	CPLL_MODE_SHIFT		= 8,
+	CPLL_MODE_MASK		= 1 << CPLL_MODE_SHIFT,
+	CPLL_MODE_SLOW		= 0,
+	CPLL_MODE_NORM,
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= 1 << DPLL_MODE_SHIFT,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORM,
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= 1 << APLL_MODE_SHIFT,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORM,
+
+	/* CRU_CLK_SEL0_CON */
+	BUS_ACLK_PLL_SEL_SHIFT	= 13,
+	BUS_ACLK_PLL_SEL_MASK	= 3 << BUS_ACLK_PLL_SEL_SHIFT,
+	BUS_ACLK_PLL_SEL_APLL	= 0,
+	BUS_ACLK_PLL_SEL_GPLL,
+	BUS_ACLK_PLL_SEL_HDMIPLL,
+	BUS_ACLK_DIV_SHIFT	= 8,
+	BUS_ACLK_DIV_MASK	= 0x1f << BUS_ACLK_DIV_SHIFT,
+	CORE_CLK_PLL_SEL_SHIFT	= 6,
+	CORE_CLK_PLL_SEL_MASK	= 3 << CORE_CLK_PLL_SEL_SHIFT,
+	CORE_CLK_PLL_SEL_APLL	= 0,
+	CORE_CLK_PLL_SEL_GPLL,
+	CORE_CLK_PLL_SEL_DPLL,
+	CORE_DIV_CON_SHIFT	= 0,
+	CORE_DIV_CON_MASK	= 0x1f << CORE_DIV_CON_SHIFT,
+
+	/* CRU_CLK_SEL1_CON */
+	BUS_PCLK_DIV_SHIFT	= 12,
+	BUS_PCLK_DIV_MASK	= 7 << BUS_PCLK_DIV_SHIFT,
+	BUS_HCLK_DIV_SHIFT	= 8,
+	BUS_HCLK_DIV_MASK	= 3 << BUS_HCLK_DIV_SHIFT,
+	CORE_ACLK_DIV_SHIFT	= 4,
+	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
+	CORE_PERI_DIV_SHIFT	= 0,
+	CORE_PERI_DIV_MASK	= 0xf << CORE_PERI_DIV_SHIFT,
+
+	/* CRU_CLKSEL5_CON */
+	GMAC_OUT_PLL_SHIFT	= 15,
+	GMAC_OUT_PLL_MASK	= 1 << GMAC_OUT_PLL_SHIFT,
+	GMAC_OUT_DIV_SHIFT	= 8,
+	GMAC_OUT_DIV_MASK	= 0x1f << GMAC_OUT_DIV_SHIFT,
+	MAC_PLL_SEL_SHIFT	= 7,
+	MAC_PLL_SEL_MASK	= 1 << MAC_PLL_SEL_SHIFT,
+	RMII_EXTCLK_SLE_SHIFT	= 5,
+	RMII_EXTCLK_SEL_MASK	= 1 << RMII_EXTCLK_SLE_SHIFT,
+	RMII_EXTCLK_SEL_INT		= 0,
+	RMII_EXTCLK_SEL_EXT,
+	CLK_MAC_DIV_SHIFT	= 0,
+	CLK_MAC_DIV_MASK	= 0x1f << CLK_MAC_DIV_SHIFT,
+
+	/* CRU_CLKSEL10_CON */
+	PERI_PCLK_DIV_SHIFT	= 12,
+	PERI_PCLK_DIV_MASK	= 7 << PERI_PCLK_DIV_SHIFT,
+	PERI_PLL_SEL_SHIFT	= 10,
+	PERI_PLL_SEL_MASK	= 3 << PERI_PLL_SEL_SHIFT,
+	PERI_PLL_CPLL		= 0,
+	PERI_PLL_GPLL,
+	PERI_PLL_HDMIPLL,
+	PERI_HCLK_DIV_SHIFT	= 8,
+	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
+	PERI_ACLK_DIV_SHIFT	= 0,
+	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
+
+	/* CRU_CLKSEL11_CON */
+	EMMC_PLL_SHIFT		= 12,
+	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
+	EMMC_SEL_CPLL		= 0,
+	EMMC_SEL_GPLL,
+	EMMC_SEL_24M,
+	SDIO_PLL_SHIFT		= 10,
+	SDIO_PLL_MASK		= 3 << SDIO_PLL_SHIFT,
+	SDIO_SEL_CPLL		= 0,
+	SDIO_SEL_GPLL,
+	SDIO_SEL_24M,
+	MMC0_PLL_SHIFT		= 8,
+	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
+	MMC0_SEL_CPLL		= 0,
+	MMC0_SEL_GPLL,
+	MMC0_SEL_24M,
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0xff << MMC0_DIV_SHIFT,
+
+	/* CRU_CLKSEL12_CON */
+	EMMC_DIV_SHIFT		= 8,
+	EMMC_DIV_MASK		= 0xff << EMMC_DIV_SHIFT,
+	SDIO_DIV_SHIFT		= 0,
+	SDIO_DIV_MASK		= 0xff << SDIO_DIV_SHIFT,
+
+	/* CRU_CLKSEL26_CON */
+	DDR_CLK_PLL_SEL_SHIFT	= 8,
+	DDR_CLK_PLL_SEL_MASK	= 3 << DDR_CLK_PLL_SEL_SHIFT,
+	DDR_CLK_SEL_DPLL	= 0,
+	DDR_CLK_SEL_GPLL,
+	DDR_CLK_SEL_APLL,
+	DDR_DIV_SEL_SHIFT	= 0,
+	DDR_DIV_SEL_MASK	= 3 << DDR_DIV_SEL_SHIFT,
+
+	/* CRU_CLKSEL27_CON */
+	VOP_DCLK_DIV_SHIFT	= 8,
+	VOP_DCLK_DIV_MASK	= 0xff << VOP_DCLK_DIV_SHIFT,
+	VOP_PLL_SEL_SHIFT	= 1,
+	VOP_PLL_SEL_MASK	= 1 << VOP_PLL_SEL_SHIFT,
+
+	/* CRU_CLKSEL29_CON */
+	GMAC_CLK_SRC_SHIFT	= 12,
+	GMAC_CLK_SRC_MASK	= 1 << GMAC_CLK_SRC_SHIFT,
+
+	/* CRU_SOFTRST5_CON */
+	DDRCTRL_PSRST_SHIFT	= 11,
+	DDRCTRL_SRST_SHIFT	= 10,
+	DDRPHY_PSRST_SHIFT	= 9,
+	DDRPHY_SRST_SHIFT	= 8,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
new file mode 100644
index 0000000..e891f20
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -0,0 +1,242 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ * Peter, Software Engineering, <superpeter.cai@gmail.com>.
+ */
+#ifndef _ASM_ARCH_CRU_RK3288_H
+#define _ASM_ARCH_CRU_RK3288_H
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#define APLL_HZ		(1800 * 1000000)
+#define GPLL_HZ		(594 * 1000000)
+#define CPLL_HZ		(384 * 1000000)
+#define NPLL_HZ		(384 * 1000000)
+
+/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
+#define PD_BUS_ACLK_HZ	297000000
+#define PD_BUS_HCLK_HZ	148500000
+#define PD_BUS_PCLK_HZ	74250000
+
+#define PERI_ACLK_HZ	148500000
+#define PERI_HCLK_HZ	148500000
+#define PERI_PCLK_HZ	74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3288_clk_priv {
+	struct rk3288_grf *grf;
+	struct rk3288_cru *cru;
+	ulong rate;
+};
+
+struct rk3288_cru {
+	struct rk3288_pll {
+		u32 con0;
+		u32 con1;
+		u32 con2;
+		u32 con3;
+	} pll[5];
+	u32 cru_mode_con;
+	u32 reserved0[3];
+	u32 cru_clksel_con[43];
+	u32 reserved1[21];
+	u32 cru_clkgate_con[19];
+	u32 reserved2;
+	u32 cru_glb_srst_fst_value;
+	u32 cru_glb_srst_snd_value;
+	u32 cru_softrst_con[12];
+	u32 cru_misc_con;
+	u32 cru_glb_cnt_th;
+	u32 cru_glb_rst_con;
+	u32 reserved3;
+	u32 cru_glb_rst_st;
+	u32 reserved4;
+	u32 cru_sdmmc_con[2];
+	u32 cru_sdio0_con[2];
+	u32 cru_sdio1_con[2];
+	u32 cru_emmc_con[2];
+};
+check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
+
+/* CRU_CLKSEL11_CON */
+enum {
+	HSICPHY_DIV_SHIFT	= 8,
+	HSICPHY_DIV_MASK	= 0x3f << HSICPHY_DIV_SHIFT,
+
+	MMC0_PLL_SHIFT		= 6,
+	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
+	MMC0_PLL_SELECT_CODEC	= 0,
+	MMC0_PLL_SELECT_GENERAL,
+	MMC0_PLL_SELECT_24MHZ,
+
+	MMC0_DIV_SHIFT		= 0,
+	MMC0_DIV_MASK		= 0x3f << MMC0_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL8_CON */
+enum {
+	I2S0_FRAC_DENOM_SHIFT	= 0,
+	I2S0_FRAC_DENOM_MASK	= 0xffff << I2S0_FRAC_DENOM_SHIFT,
+	I2S0_FRAC_NUMER_SHIFT	= 16,
+	I2S0_FRAC_NUMER_MASK	= 0xffffu << I2S0_FRAC_NUMER_SHIFT,
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+	EMMC_PLL_SHIFT		= 0xe,
+	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
+	EMMC_PLL_SELECT_CODEC	= 0,
+	EMMC_PLL_SELECT_GENERAL,
+	EMMC_PLL_SELECT_24MHZ,
+
+	EMMC_DIV_SHIFT		= 8,
+	EMMC_DIV_MASK		= 0x3f << EMMC_DIV_SHIFT,
+
+	SDIO0_PLL_SHIFT		= 6,
+	SDIO0_PLL_MASK		= 3 << SDIO0_PLL_SHIFT,
+	SDIO0_PLL_SELECT_CODEC	= 0,
+	SDIO0_PLL_SELECT_GENERAL,
+	SDIO0_PLL_SELECT_24MHZ,
+
+	SDIO0_DIV_SHIFT		= 0,
+	SDIO0_DIV_MASK		= 0x3f << SDIO0_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL21_CON */
+enum {
+	MAC_DIV_CON_SHIFT	= 0xf,
+	MAC_DIV_CON_MASK	= 0x1f << MAC_DIV_CON_SHIFT,
+
+	RMII_EXTCLK_SHIFT	= 4,
+	RMII_EXTCLK_MASK	= 1 << RMII_EXTCLK_SHIFT,
+	RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+	RMII_EXTCLK_SELECT_EXT_CLK = 1,
+
+	EMAC_PLL_SHIFT		= 0,
+	EMAC_PLL_MASK		= 0x3 << EMAC_PLL_SHIFT,
+	EMAC_PLL_SELECT_NEW	= 0x0,
+	EMAC_PLL_SELECT_CODEC	= 0x1,
+	EMAC_PLL_SELECT_GENERAL	= 0x2,
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+	SPI1_PLL_SHIFT		= 0xf,
+	SPI1_PLL_MASK		= 1 << SPI1_PLL_SHIFT,
+	SPI1_PLL_SELECT_CODEC	= 0,
+	SPI1_PLL_SELECT_GENERAL,
+
+	SPI1_DIV_SHIFT		= 8,
+	SPI1_DIV_MASK		= 0x7f << SPI1_DIV_SHIFT,
+
+	SPI0_PLL_SHIFT		= 7,
+	SPI0_PLL_MASK		= 1 << SPI0_PLL_SHIFT,
+	SPI0_PLL_SELECT_CODEC	= 0,
+	SPI0_PLL_SELECT_GENERAL,
+
+	SPI0_DIV_SHIFT		= 0,
+	SPI0_DIV_MASK		= 0x7f << SPI0_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL37_CON */
+enum {
+	PCLK_CORE_DBG_DIV_SHIFT	= 9,
+	PCLK_CORE_DBG_DIV_MASK	= 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
+
+	ATCLK_CORE_DIV_CON_SHIFT = 4,
+	ATCLK_CORE_DIV_CON_MASK	= 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
+
+	CLK_L2RAM_DIV_SHIFT	= 0,
+	CLK_L2RAM_DIV_MASK	= 7 << CLK_L2RAM_DIV_SHIFT,
+};
+
+/* CRU_CLKSEL39_CON */
+enum {
+	ACLK_HEVC_PLL_SHIFT	= 0xe,
+	ACLK_HEVC_PLL_MASK	= 3 << ACLK_HEVC_PLL_SHIFT,
+	ACLK_HEVC_PLL_SELECT_CODEC = 0,
+	ACLK_HEVC_PLL_SELECT_GENERAL,
+	ACLK_HEVC_PLL_SELECT_NEW,
+
+	ACLK_HEVC_DIV_SHIFT	= 8,
+	ACLK_HEVC_DIV_MASK	= 0x1f << ACLK_HEVC_DIV_SHIFT,
+
+	SPI2_PLL_SHIFT		= 7,
+	SPI2_PLL_MASK		= 1 << SPI2_PLL_SHIFT,
+	SPI2_PLL_SELECT_CODEC	= 0,
+	SPI2_PLL_SELECT_GENERAL,
+
+	SPI2_DIV_SHIFT		= 0,
+	SPI2_DIV_MASK		= 0x7f << SPI2_DIV_SHIFT,
+};
+
+/* CRU_MODE_CON */
+enum {
+	CRU_MODE_MASK		= 3,
+
+	NPLL_MODE_SHIFT		= 0xe,
+	NPLL_MODE_MASK		= CRU_MODE_MASK << NPLL_MODE_SHIFT,
+	NPLL_MODE_SLOW		= 0,
+	NPLL_MODE_NORMAL,
+	NPLL_MODE_DEEP,
+
+	GPLL_MODE_SHIFT		= 0xc,
+	GPLL_MODE_MASK		= CRU_MODE_MASK << GPLL_MODE_SHIFT,
+	GPLL_MODE_SLOW		= 0,
+	GPLL_MODE_NORMAL,
+	GPLL_MODE_DEEP,
+
+	CPLL_MODE_SHIFT		= 8,
+	CPLL_MODE_MASK		= CRU_MODE_MASK << CPLL_MODE_SHIFT,
+	CPLL_MODE_SLOW		= 0,
+	CPLL_MODE_NORMAL,
+	CPLL_MODE_DEEP,
+
+	DPLL_MODE_SHIFT		= 4,
+	DPLL_MODE_MASK		= CRU_MODE_MASK << DPLL_MODE_SHIFT,
+	DPLL_MODE_SLOW		= 0,
+	DPLL_MODE_NORMAL,
+	DPLL_MODE_DEEP,
+
+	APLL_MODE_SHIFT		= 0,
+	APLL_MODE_MASK		= CRU_MODE_MASK << APLL_MODE_SHIFT,
+	APLL_MODE_SLOW		= 0,
+	APLL_MODE_NORMAL,
+	APLL_MODE_DEEP,
+};
+
+/* CRU_APLL_CON0 */
+enum {
+	CLKR_SHIFT		= 8,
+	CLKR_MASK		= 0x3f << CLKR_SHIFT,
+
+	CLKOD_SHIFT		= 0,
+	CLKOD_MASK		= 0xf << CLKOD_SHIFT,
+};
+
+/* CRU_APLL_CON1 */
+enum {
+	LOCK_SHIFT		= 0x1f,
+	LOCK_MASK		= 1 << LOCK_SHIFT,
+	LOCK_UNLOCK		= 0,
+	LOCK_LOCK,
+
+	CLKF_SHIFT		= 0,
+	CLKF_MASK		= 0x1fff << CLKF_SHIFT,
+};
+
+/* CRU_GLB_RST_ST */
+enum {
+	GLB_POR_RST,
+	FST_GLB_RST_ST		= BIT(0),
+	SND_GLB_RST_ST		= BIT(1),
+	FST_GLB_TSADC_RST_ST	= BIT(2),
+	SND_GLB_TSADC_RST_ST	= BIT(3),
+	FST_GLB_WDT_RST_ST	= BIT(4),
+	SND_GLB_WDT_RST_ST	= BIT(5),
+	GLB_RST_ST_MASK		= GENMASK(5, 0),
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3328.h b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
new file mode 100644
index 0000000..15b9788
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3328.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_CRU_RK3328_H_
+#define __ASM_ARCH_CRU_RK3328_H_
+
+#include <common.h>
+
+struct rk3328_clk_priv {
+	struct rk3328_cru *cru;
+	ulong rate;
+};
+
+struct rk3328_cru {
+	u32 apll_con[5];
+	u32 reserved1[3];
+	u32 dpll_con[5];
+	u32 reserved2[3];
+	u32 cpll_con[5];
+	u32 reserved3[3];
+	u32 gpll_con[5];
+	u32 reserved4[3];
+	u32 mode_con;
+	u32 misc;
+	u32 reserved5[2];
+	u32 glb_cnt_th;
+	u32 glb_rst_st;
+	u32 glb_srst_snd_value;
+	u32 glb_srst_fst_value;
+	u32 npll_con[5];
+	u32 reserved6[(0x100 - 0xb4) / 4];
+	u32 clksel_con[53];
+	u32 reserved7[(0x200 - 0x1d4) / 4];
+	u32 clkgate_con[29];
+	u32 reserved8[3];
+	u32 ssgtbl[32];
+	u32 softrst_con[12];
+	u32 reserved9[(0x380 - 0x330) / 4];
+	u32 sdmmc_con[2];
+	u32 sdio_con[2];
+	u32 emmc_con[2];
+	u32 sdmmc_ext_con[2];
+};
+check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
+#define MHz		1000000
+#define KHz		1000
+#define OSC_HZ		(24 * MHz)
+#define APLL_HZ		(600 * MHz)
+#define GPLL_HZ		(576 * MHz)
+#define CPLL_HZ		(594 * MHz)
+
+#define CLK_CORE_HZ	(600 * MHz)
+#define ACLKM_CORE_HZ	(300 * MHz)
+#define PCLK_DBG_HZ	(300 * MHz)
+
+#define PERIHP_ACLK_HZ	(144000 * KHz)
+#define PERIHP_HCLK_HZ	(72000 * KHz)
+#define PERIHP_PCLK_HZ	(72000 * KHz)
+
+#define PWM_CLOCK_HZ    (74 * MHz)
+
+enum apll_frequencies {
+	APLL_816_MHZ,
+	APLL_600_MHZ,
+};
+
+#endif	/* __ASM_ARCH_CRU_RK3328_H_ */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
new file mode 100644
index 0000000..1fe1f01
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ */
+#ifndef _ASM_ARCH_CRU_RK3368_H
+#define _ASM_ARCH_CRU_RK3368_H
+
+#include <common.h>
+
+
+/* RK3368 clock numbers */
+enum rk3368_pll_id {
+	APLLB,
+	APLLL,
+	DPLL,
+	CPLL,
+	GPLL,
+	NPLL,
+	PLL_COUNT,
+};
+
+struct rk3368_cru {
+	struct rk3368_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+		unsigned int con3;
+	} pll[6];
+	unsigned int reserved[0x28];
+	unsigned int clksel_con[56];
+	unsigned int reserved1[8];
+	unsigned int clkgate_con[25];
+	unsigned int reserved2[7];
+	unsigned int glb_srst_fst_val;
+	unsigned int glb_srst_snd_val;
+	unsigned int reserved3[0x1e];
+	unsigned int softrst_con[15];
+	unsigned int reserved4[0x11];
+	unsigned int misc_con;
+	unsigned int glb_cnt_th;
+	unsigned int glb_rst_con;
+	unsigned int glb_rst_st;
+	unsigned int reserved5[0x1c];
+	unsigned int sdmmc_con[2];
+	unsigned int sdio0_con[2];
+	unsigned int sdio1_con[2];
+	unsigned int emmc_con[2];
+};
+check_member(rk3368_cru, emmc_con[1], 0x41c);
+
+struct rk3368_clk_priv {
+	struct rk3368_cru *cru;
+};
+
+enum {
+	/* PLL CON0 */
+	PLL_NR_SHIFT			= 8,
+	PLL_NR_MASK			= GENMASK(13, 8),
+	PLL_OD_SHIFT			= 0,
+	PLL_OD_MASK			= GENMASK(3, 0),
+
+	/* PLL CON1 */
+	PLL_LOCK_STA			= BIT(31),
+	PLL_NF_SHIFT			= 0,
+	PLL_NF_MASK			= GENMASK(12, 0),
+
+	/* PLL CON2 */
+	PLL_BWADJ_SHIFT			= 0,
+	PLL_BWADJ_MASK			= GENMASK(11, 0),
+
+	/* PLL CON3 */
+	PLL_MODE_SHIFT			= 8,
+	PLL_MODE_MASK			= GENMASK(9, 8),
+	PLL_MODE_SLOW			= 0,
+	PLL_MODE_NORMAL			= 1,
+	PLL_MODE_DEEP_SLOW		= 3,
+	PLL_RESET_SHIFT			= 5,
+	PLL_RESET			= 1,
+	PLL_RESET_MASK			= GENMASK(5, 5),
+
+	/* CLKSEL12_CON */
+	MCU_STCLK_DIV_SHIFT		= 8,
+	MCU_STCLK_DIV_MASK		= GENMASK(10, 8),
+	MCU_PLL_SEL_SHIFT		= 7,
+	MCU_PLL_SEL_MASK		= BIT(7),
+	MCU_PLL_SEL_CPLL		= 0,
+	MCU_PLL_SEL_GPLL		= 1,
+	MCU_CLK_DIV_SHIFT		= 0,
+	MCU_CLK_DIV_MASK		= GENMASK(4, 0),
+
+	/* CLKSEL_CON25 */
+	CLK_SARADC_DIV_CON_SHIFT	= 8,
+	CLK_SARADC_DIV_CON_MASK		= GENMASK(15, 8),
+	CLK_SARADC_DIV_CON_WIDTH	= 8,
+
+	/* CLKSEL43_CON */
+	GMAC_DIV_CON_SHIFT		= 0x0,
+	GMAC_DIV_CON_MASK		= GENMASK(4, 0),
+	GMAC_PLL_SHIFT			= 6,
+	GMAC_PLL_MASK			= GENMASK(7, 6),
+	GMAC_PLL_SELECT_NEW		= (0x0 << GMAC_PLL_SHIFT),
+	GMAC_PLL_SELECT_CODEC		= (0x1 << GMAC_PLL_SHIFT),
+	GMAC_PLL_SELECT_GENERAL		= (0x2 << GMAC_PLL_SHIFT),
+	GMAC_MUX_SEL_EXTCLK             = BIT(8),
+
+	/* CLKSEL51_CON */
+	MMC_PLL_SEL_SHIFT		= 8,
+	MMC_PLL_SEL_MASK		= GENMASK(9, 8),
+	MMC_PLL_SEL_CPLL		= (0 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_GPLL                = (1 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_USBPHY_480M         = (2 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_24M                 = (3 << MMC_PLL_SEL_SHIFT),
+	MMC_CLK_DIV_SHIFT		= 0,
+	MMC_CLK_DIV_MASK		= GENMASK(6, 0),
+
+	/* SOFTRST1_CON */
+	MCU_PO_SRST_MASK		= BIT(13),
+	MCU_SYS_SRST_MASK		= BIT(12),
+	DMA1_SRST_REQ                   = BIT(2),
+
+	/* SOFTRST4_CON */
+	DMA2_SRST_REQ                   = BIT(0),
+
+	/* GLB_RST_CON */
+	PMU_GLB_SRST_CTRL_SHIFT		= 2,
+	PMU_GLB_SRST_CTRL_MASK		= GENMASK(3, 2),
+	PMU_RST_BY_FST_GLB_SRST 	= 0,
+	PMU_RST_BY_SND_GLB_SRST 	= 1,
+	PMU_RST_DISABLE			= 2,
+	WDT_GLB_SRST_CTRL_SHIFT		= 1,
+	WDT_GLB_SRST_CTRL_MASK		= BIT(1),
+	WDT_TRIGGER_SND_GLB_SRST 	= 0,
+	WDT_TRIGGER_FST_GLB_SRST 	= 1,
+	TSADC_GLB_SRST_CTRL_SHIFT 	= 0,
+	TSADC_GLB_SRST_CTRL_MASK  	= BIT(0),
+	TSADC_TRIGGER_SND_GLB_SRST 	= 0,
+	TSADC_TRIGGER_FST_GLB_SRST 	= 1,
+
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
new file mode 100644
index 0000000..15eeb9c
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_CRU_RK3399_H_
+#define __ASM_ARCH_CRU_RK3399_H_
+
+#include <common.h>
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3399_clk_priv {
+	struct rk3399_cru *cru;
+};
+
+struct rk3399_pmuclk_priv {
+	struct rk3399_pmucru *pmucru;
+};
+
+struct rk3399_pmucru {
+	u32 ppll_con[6];
+	u32 reserved[0x1a];
+	u32 pmucru_clksel[6];
+	u32 pmucru_clkfrac_con[2];
+	u32 reserved2[0x18];
+	u32 pmucru_clkgate_con[3];
+	u32 reserved3;
+	u32 pmucru_softrst_con[2];
+	u32 reserved4[2];
+	u32 pmucru_rstnhold_con[2];
+	u32 reserved5[2];
+	u32 pmucru_gatedis_con[2];
+};
+check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134);
+
+struct rk3399_cru {
+	u32 apll_l_con[6];
+	u32 reserved[2];
+	u32 apll_b_con[6];
+	u32 reserved1[2];
+	u32 dpll_con[6];
+	u32 reserved2[2];
+	u32 cpll_con[6];
+	u32 reserved3[2];
+	u32 gpll_con[6];
+	u32 reserved4[2];
+	u32 npll_con[6];
+	u32 reserved5[2];
+	u32 vpll_con[6];
+	u32 reserved6[0x0a];
+	u32 clksel_con[108];
+	u32 reserved7[0x14];
+	u32 clkgate_con[35];
+	u32 reserved8[0x1d];
+	u32 softrst_con[21];
+	u32 reserved9[0x2b];
+	u32 glb_srst_fst_value;
+	u32 glb_srst_snd_value;
+	u32 glb_cnt_th;
+	u32 misc_con;
+	u32 glb_rst_con;
+	u32 glb_rst_st;
+	u32 reserved10[0x1a];
+	u32 sdmmc_con[2];
+	u32 sdio0_con[2];
+	u32 sdio1_con[2];
+};
+check_member(rk3399_cru, sdio1_con[1], 0x594);
+#define MHz		1000000
+#define KHz		1000
+#define OSC_HZ		(24*MHz)
+#define LPLL_HZ		(600*MHz)
+#define BPLL_HZ		(600*MHz)
+#define GPLL_HZ		(594*MHz)
+#define CPLL_HZ		(384*MHz)
+#define PPLL_HZ		(676*MHz)
+
+#define PMU_PCLK_HZ	(48*MHz)
+
+#define ACLKM_CORE_L_HZ	(300*MHz)
+#define ATCLK_CORE_L_HZ	(300*MHz)
+#define PCLK_DBG_L_HZ	(100*MHz)
+
+#define ACLKM_CORE_B_HZ	(300*MHz)
+#define ATCLK_CORE_B_HZ	(300*MHz)
+#define PCLK_DBG_B_HZ	(100*MHz)
+
+#define PERIHP_ACLK_HZ	(148500*KHz)
+#define PERIHP_HCLK_HZ	(148500*KHz)
+#define PERIHP_PCLK_HZ	(37125*KHz)
+
+#define PERILP0_ACLK_HZ	(99000*KHz)
+#define PERILP0_HCLK_HZ	(99000*KHz)
+#define PERILP0_PCLK_HZ	(49500*KHz)
+
+#define PERILP1_HCLK_HZ	(99000*KHz)
+#define PERILP1_PCLK_HZ	(49500*KHz)
+
+#define PWM_CLOCK_HZ    PMU_PCLK_HZ
+
+enum apll_l_frequencies {
+	APLL_L_1600_MHZ,
+	APLL_L_600_MHZ,
+};
+
+enum apll_b_frequencies {
+	APLL_B_600_MHZ,
+};
+
+void rk3399_configure_cpu_l(struct rk3399_cru *cru,
+			    enum apll_l_frequencies apll_l_freq);
+void rk3399_configure_cpu_b(struct rk3399_cru *cru,
+			    enum apll_b_frequencies apll_b_freq);
+
+#endif	/* __ASM_ARCH_CRU_RK3399_H_ */
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
new file mode 100644
index 0000000..7697e96
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h
@@ -0,0 +1,258 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ */
+#ifndef _ASM_ARCH_CRU_RV1108_H
+#define _ASM_ARCH_CRU_RV1108_H
+
+#include <common.h>
+
+#define OSC_HZ		(24 * 1000 * 1000)
+
+#define APLL_HZ		(600 * 1000000)
+#define GPLL_HZ		(1188 * 1000000)
+#define ACLK_PERI_HZ	(148500000)
+#define HCLK_PERI_HZ	(148500000)
+#define PCLK_PERI_HZ	(74250000)
+#define ACLK_BUS_HZ	(148500000)
+
+struct rv1108_clk_priv {
+	struct rv1108_cru *cru;
+	ulong rate;
+};
+
+struct rv1108_cru {
+	struct rv1108_pll {
+		unsigned int con0;
+		unsigned int con1;
+		unsigned int con2;
+		unsigned int con3;
+		unsigned int con4;
+		unsigned int con5;
+		unsigned int reserved[2];
+	} pll[3];
+	unsigned int clksel_con[46];
+	unsigned int reserved1[2];
+	unsigned int clkgate_con[20];
+	unsigned int reserved2[4];
+	unsigned int softrst_con[13];
+	unsigned int reserved3[3];
+	unsigned int glb_srst_fst_val;
+	unsigned int glb_srst_snd_val;
+	unsigned int glb_cnt_th;
+	unsigned int misc_con;
+	unsigned int glb_rst_con;
+	unsigned int glb_rst_st;
+	unsigned int sdmmc_con[2];
+	unsigned int sdio_con[2];
+	unsigned int emmc_con[2];
+};
+check_member(rv1108_cru, emmc_con[1], 0x01ec);
+
+struct pll_div {
+	u32 refdiv;
+	u32 fbdiv;
+	u32 postdiv1;
+	u32 postdiv2;
+	u32 frac;
+};
+
+enum {
+	/* PLL CON0 */
+	FBDIV_MASK		= 0xfff,
+	FBDIV_SHIFT		= 0,
+
+	/* PLL CON1 */
+	POSTDIV2_SHIFT          = 12,
+	POSTDIV2_MASK		= 7 << POSTDIV2_SHIFT,
+	POSTDIV1_SHIFT          = 8,
+	POSTDIV1_MASK		= 7 << POSTDIV1_SHIFT,
+	REFDIV_MASK		= 0x3f,
+	REFDIV_SHIFT		= 0,
+
+	/* PLL CON2 */
+	LOCK_STA_SHIFT          = 31,
+	LOCK_STA_MASK		= 1 << LOCK_STA_SHIFT,
+	FRACDIV_MASK		= 0xffffff,
+	FRACDIV_SHIFT		= 0,
+
+	/* PLL CON3 */
+	WORK_MODE_SHIFT         = 8,
+	WORK_MODE_MASK		= 1 << WORK_MODE_SHIFT,
+	WORK_MODE_SLOW		= 0,
+	WORK_MODE_NORMAL	= 1,
+	DSMPD_SHIFT             = 3,
+	DSMPD_MASK		= 1 << DSMPD_SHIFT,
+	INTEGER_MODE			= 1,
+	GLOBAL_POWER_DOWN_SHIFT		= 0,
+	GLOBAL_POWER_DOWN_MASK		= 1 << GLOBAL_POWER_DOWN_SHIFT,
+	GLOBAL_POWER_DOWN		= 1,
+	GLOBAL_POWER_UP			= 0,
+
+	/* CLKSEL0_CON */
+	CORE_PLL_SEL_SHIFT	= 8,
+	CORE_PLL_SEL_MASK	= 3 << CORE_PLL_SEL_SHIFT,
+	CORE_PLL_SEL_APLL	= 0,
+	CORE_PLL_SEL_GPLL	= 1,
+	CORE_PLL_SEL_DPLL	= 2,
+	CORE_CLK_DIV_SHIFT	= 0,
+	CORE_CLK_DIV_MASK	= 0x1f << CORE_CLK_DIV_SHIFT,
+
+	/* CLKSEL_CON1 */
+	PCLK_DBG_DIV_CON_SHIFT		= 4,
+	PCLK_DBG_DIV_CON_MASK		= 0xf << PCLK_DBG_DIV_CON_SHIFT,
+	ACLK_CORE_DIV_CON_SHIFT		= 0,
+	ACLK_CORE_DIV_CON_MASK		= 7 << ACLK_CORE_DIV_CON_SHIFT,
+
+	/* CLKSEL_CON2 */
+	ACLK_BUS_PLL_SEL_SHIFT		= 8,
+	ACLK_BUS_PLL_SEL_MASK		= 3 << ACLK_BUS_PLL_SEL_SHIFT,
+	ACLK_BUS_PLL_SEL_GPLL		= 0,
+	ACLK_BUS_PLL_SEL_APLL		= 1,
+	ACLK_BUS_PLL_SEL_DPLL		= 2,
+	ACLK_BUS_DIV_CON_SHIFT		= 0,
+	ACLK_BUS_DIV_CON_MASK		= 0x1f << ACLK_BUS_DIV_CON_SHIFT,
+	ACLK_BUS_DIV_CON_WIDTH		= 5,
+
+	/* CLKSEL_CON3 */
+	PCLK_BUS_DIV_CON_SHIFT		= 8,
+	PCLK_BUS_DIV_CON_MASK		= 0x1f << PCLK_BUS_DIV_CON_SHIFT,
+	HCLK_BUS_DIV_CON_SHIFT		= 0,
+	HCLK_BUS_DIV_CON_MASK		= 0x1f,
+
+	/* CLKSEL_CON4 */
+	CLK_DDR_PLL_SEL_SHIFT		= 8,
+	CLK_DDR_PLL_SEL_MASK		= 0x3 << CLK_DDR_PLL_SEL_SHIFT,
+	CLK_DDR_DIV_CON_SHIFT		= 0,
+	CLK_DDR_DIV_CON_MASK		= 0x3 << CLK_DDR_DIV_CON_SHIFT,
+
+	/* CLKSEL_CON19 */
+	CLK_I2C1_PLL_SEL_SHIFT		= 15,
+	CLK_I2C1_PLL_SEL_MASK		= 1 << CLK_I2C1_PLL_SEL_SHIFT,
+	CLK_I2C1_PLL_SEL_DPLL		= 0,
+	CLK_I2C1_PLL_SEL_GPLL		= 1,
+	CLK_I2C1_DIV_CON_SHIFT		= 8,
+	CLK_I2C1_DIV_CON_MASK		= 0x7f << CLK_I2C1_DIV_CON_SHIFT,
+	CLK_I2C0_PLL_SEL_SHIFT		= 7,
+	CLK_I2C0_PLL_SEL_MASK		= 1 << CLK_I2C0_PLL_SEL_SHIFT,
+	CLK_I2C0_DIV_CON_SHIFT		= 0,
+	CLK_I2C0_DIV_CON_MASK		= 0x7f,
+	I2C_DIV_CON_WIDTH		= 7,
+
+	/* CLKSEL_CON20 */
+	CLK_I2C3_PLL_SEL_SHIFT		= 15,
+	CLK_I2C3_PLL_SEL_MASK		= 1 << CLK_I2C3_PLL_SEL_SHIFT,
+	CLK_I2C3_PLL_SEL_DPLL		= 0,
+	CLK_I2C3_PLL_SEL_GPLL		= 1,
+	CLK_I2C3_DIV_CON_SHIFT		= 8,
+	CLK_I2C3_DIV_CON_MASK		= 0x7f << CLK_I2C3_DIV_CON_SHIFT,
+	CLK_I2C2_PLL_SEL_SHIFT		= 7,
+	CLK_I2C2_PLL_SEL_MASK		= 1 << CLK_I2C2_PLL_SEL_SHIFT,
+	CLK_I2C2_DIV_CON_SHIFT		= 0,
+	CLK_I2C2_DIV_CON_MASK		= 0x7f,
+
+	/* CLKSEL_CON22 */
+	CLK_SARADC_DIV_CON_SHIFT= 0,
+	CLK_SARADC_DIV_CON_MASK	= GENMASK(9, 0),
+	CLK_SARADC_DIV_CON_WIDTH= 10,
+
+	/* CLKSEL_CON23 */
+	ACLK_PERI_PLL_SEL_SHIFT		= 15,
+	ACLK_PERI_PLL_SEL_MASK		= 1 << ACLK_PERI_PLL_SEL_SHIFT,
+	ACLK_PERI_PLL_SEL_GPLL		= 0,
+	ACLK_PERI_PLL_SEL_DPLL		= 1,
+	PCLK_PERI_DIV_CON_SHIFT		= 10,
+	PCLK_PERI_DIV_CON_MASK		= 0x1f << PCLK_PERI_DIV_CON_SHIFT,
+	HCLK_PERI_DIV_CON_SHIFT		= 5,
+	HCLK_PERI_DIV_CON_MASK		= 0x1f << HCLK_PERI_DIV_CON_SHIFT,
+	ACLK_PERI_DIV_CON_SHIFT		= 0,
+	ACLK_PERI_DIV_CON_MASK		= 0x1f,
+	PERI_DIV_CON_WIDTH		= 5,
+
+	/* CLKSEL24_CON */
+	MAC_PLL_SEL_SHIFT	= 12,
+	MAC_PLL_SEL_MASK	= 1 << MAC_PLL_SEL_SHIFT,
+	MAC_PLL_SEL_APLL	= 0,
+	MAC_PLL_SEL_GPLL	= 1,
+	RMII_EXTCLK_SEL_SHIFT   = 8,
+	RMII_EXTCLK_SEL_MASK	= 1 << RMII_EXTCLK_SEL_SHIFT,
+	MAC_CLK_DIV_MASK	= 0x1f,
+	MAC_CLK_DIV_SHIFT	= 0,
+
+	/* CLKSEL25_CON */
+	EMMC_PLL_SEL_SHIFT	= 12,
+	EMMC_PLL_SEL_MASK	= 3 << EMMC_PLL_SEL_SHIFT,
+	EMMC_PLL_SEL_DPLL	= 0,
+	EMMC_PLL_SEL_GPLL,
+	EMMC_PLL_SEL_OSC,
+
+	/* CLKSEL26_CON */
+	EMMC_CLK_DIV_SHIFT	= 8,
+	EMMC_CLK_DIV_MASK	= 0xff << EMMC_CLK_DIV_SHIFT,
+
+	/* CLKSEL27_CON */
+	SFC_PLL_SEL_SHIFT	= 7,
+	SFC_PLL_SEL_MASK	= 1 << SFC_PLL_SEL_SHIFT,
+	SFC_PLL_SEL_DPLL	= 0,
+	SFC_PLL_SEL_GPLL	= 1,
+	SFC_CLK_DIV_SHIFT	= 0,
+	SFC_CLK_DIV_MASK	= 0x3f << SFC_CLK_DIV_SHIFT,
+
+	/* CLKSEL28_CON */
+	ACLK_VIO1_PLL_SEL_SHIFT		= 14,
+	ACLK_VIO1_PLL_SEL_MASK		= 3 << ACLK_VIO1_PLL_SEL_SHIFT,
+	VIO_PLL_SEL_DPLL		= 0,
+	VIO_PLL_SEL_GPLL		= 1,
+	ACLK_VIO1_CLK_DIV_SHIFT		= 8,
+	ACLK_VIO1_CLK_DIV_MASK		= 0x1f << ACLK_VIO1_CLK_DIV_SHIFT,
+	CLK_VIO_DIV_CON_WIDTH		= 5,
+	ACLK_VIO0_PLL_SEL_SHIFT		= 6,
+	ACLK_VIO0_PLL_SEL_MASK		= 3 << ACLK_VIO0_PLL_SEL_SHIFT,
+	ACLK_VIO0_CLK_DIV_SHIFT		= 0,
+	ACLK_VIO0_CLK_DIV_MASK		= 0x1f << ACLK_VIO0_CLK_DIV_SHIFT,
+
+	/* CLKSEL29_CON */
+	PCLK_VIO_CLK_DIV_SHIFT		= 8,
+	PCLK_VIO_CLK_DIV_MASK		= 0x1f << PCLK_VIO_CLK_DIV_SHIFT,
+	HCLK_VIO_CLK_DIV_SHIFT		= 0,
+	HCLK_VIO_CLK_DIV_MASK		= 0x1f << HCLK_VIO_CLK_DIV_SHIFT,
+
+	/* CLKSEL32_CON */
+	DCLK_VOP_SEL_SHIFT		= 7,
+	DCLK_VOP_SEL_MASK		= 1 << DCLK_VOP_SEL_SHIFT,
+	DCLK_VOP_SEL_HDMI		= 0,
+	DCLK_VOP_SEL_PLL		= 1,
+	DCLK_VOP_PLL_SEL_SHIFT		= 6,
+	DCLK_VOP_PLL_SEL_MASK		= 1 << DCLK_VOP_PLL_SEL_SHIFT,
+	DCLK_VOP_PLL_SEL_GPLL		= 0,
+	DCLK_VOP_PLL_SEL_DPLL		= 1,
+	DCLK_VOP_CLK_DIV_SHIFT		= 0,
+	DCLK_VOP_CLK_DIV_MASK		= 0x3f << DCLK_VOP_CLK_DIV_SHIFT,
+	DCLK_VOP_DIV_CON_WIDTH		= 6,
+
+	/* SOFTRST1_CON*/
+	DDRPHY_SRSTN_CLKDIV_REQ_SHIFT	= 0,
+	DDRPHY_SRSTN_CLKDIV_REQ		= 1,
+	DDRPHY_SRSTN_CLKDIV_DIS		= 0,
+	DDRPHY_SRSTN_CLKDIV_REQ_MASK	= 1 << DDRPHY_SRSTN_CLKDIV_REQ_SHIFT,
+	DDRPHY_SRSTN_REQ_SHIFT		= 1,
+	DDRPHY_SRSTN_REQ		= 1,
+	DDRPHY_SRSTN_DIS		= 0,
+	DDRPHY_SRSTN_REQ_MASK		= 1 << DDRPHY_SRSTN_REQ_SHIFT,
+	DDRPHY_PSRSTN_REQ_SHIFT		= 2,
+	DDRPHY_PSRSTN_REQ		= 1,
+	DDRPHY_PSRSTN_DIS		= 0,
+	DDRPHY_PSRSTN_REQ_MASK		= 1 << DDRPHY_PSRSTN_REQ_SHIFT,
+
+	/* SOFTRST2_CON*/
+	DDRUPCTL_PSRSTN_REQ_SHIFT	= 0,
+	DDRUPCTL_PSRSTN_REQ		= 1,
+	DDRUPCTL_PSRSTN_DIS		= 0,
+	DDRUPCTL_PSRSTN_REQ_MASK	= 1 << DDRUPCTL_PSRSTN_REQ_SHIFT,
+	DDRUPCTL_NSRSTN_REQ_SHIFT	= 1,
+	DDRUPCTL_NSRSTN_REQ		= 1,
+	DDRUPCTL_NSRSTN_DIS		= 0,
+	DDRUPCTL_NSRSTN_REQ_MASK	= 1 << DDRUPCTL_NSRSTN_REQ_SHIFT,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
new file mode 100644
index 0000000..db83d0e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_DDR_RK3188_H
+#define _ASM_ARCH_DDR_RK3188_H
+
+#include <asm/arch-rockchip/ddr_rk3288.h>
+
+/*
+ * RK3188 Memory scheduler register map.
+ */
+struct rk3188_msch {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+};
+check_member(rk3188_msch, readlatency, 0x0014);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
new file mode 100644
index 0000000..979d547
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
@@ -0,0 +1,443 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_DDR_RK3288_H
+#define _ASM_ARCH_DDR_RK3288_H
+
+struct rk3288_ddr_pctl {
+	u32 scfg;
+	u32 sctl;
+	u32 stat;
+	u32 intrstat;
+	u32 reserved0[12];
+	u32 mcmd;
+	u32 powctl;
+	u32 powstat;
+	u32 cmdtstat;
+	u32 tstaten;
+	u32 reserved1[3];
+	u32 mrrcfg0;
+	u32 mrrstat0;
+	u32 mrrstat1;
+	u32 reserved2[4];
+	u32 mcfg1;
+	u32 mcfg;
+	u32 ppcfg;
+	u32 mstat;
+	u32 lpddr2zqcfg;
+	u32 reserved3;
+	u32 dtupdes;
+	u32 dtuna;
+	u32 dtune;
+	u32 dtuprd0;
+	u32 dtuprd1;
+	u32 dtuprd2;
+	u32 dtuprd3;
+	u32 dtuawdt;
+	u32 reserved4[3];
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+	u32 reserved5[14];
+	u32 ecccfg;
+	u32 ecctst;
+	u32 eccclr;
+	u32 ecclog;
+	u32 reserved6[28];
+	u32 dtuwactl;
+	u32 dturactl;
+	u32 dtucfg;
+	u32 dtuectl;
+	u32 dtuwd0;
+	u32 dtuwd1;
+	u32 dtuwd2;
+	u32 dtuwd3;
+	u32 dtuwdm;
+	u32 dturd0;
+	u32 dturd1;
+	u32 dturd2;
+	u32 dturd3;
+	u32 dtulfsrwd;
+	u32 dtulfsrrd;
+	u32 dtueaf;
+	u32 dfitctrldelay;
+	u32 dfiodtcfg;
+	u32 dfiodtcfg1;
+	u32 dfiodtrankmap;
+	u32 dfitphywrdata;
+	u32 dfitphywrlat;
+	u32 reserved7[2];
+	u32 dfitrddataen;
+	u32 dfitphyrdlat;
+	u32 reserved8[2];
+	u32 dfitphyupdtype0;
+	u32 dfitphyupdtype1;
+	u32 dfitphyupdtype2;
+	u32 dfitphyupdtype3;
+	u32 dfitctrlupdmin;
+	u32 dfitctrlupdmax;
+	u32 dfitctrlupddly;
+	u32 reserved9;
+	u32 dfiupdcfg;
+	u32 dfitrefmski;
+	u32 dfitctrlupdi;
+	u32 reserved10[4];
+	u32 dfitrcfg0;
+	u32 dfitrstat0;
+	u32 dfitrwrlvlen;
+	u32 dfitrrdlvlen;
+	u32 dfitrrdlvlgateen;
+	u32 dfiststat0;
+	u32 dfistcfg0;
+	u32 dfistcfg1;
+	u32 reserved11;
+	u32 dfitdramclken;
+	u32 dfitdramclkdis;
+	u32 dfistcfg2;
+	u32 dfistparclr;
+	u32 dfistparlog;
+	u32 reserved12[3];
+	u32 dfilpcfg0;
+	u32 reserved13[3];
+	u32 dfitrwrlvlresp0;
+	u32 dfitrwrlvlresp1;
+	u32 dfitrwrlvlresp2;
+	u32 dfitrrdlvlresp0;
+	u32 dfitrrdlvlresp1;
+	u32 dfitrrdlvlresp2;
+	u32 dfitrwrlvldelay0;
+	u32 dfitrwrlvldelay1;
+	u32 dfitrwrlvldelay2;
+	u32 dfitrrdlvldelay0;
+	u32 dfitrrdlvldelay1;
+	u32 dfitrrdlvldelay2;
+	u32 dfitrrdlvlgatedelay0;
+	u32 dfitrrdlvlgatedelay1;
+	u32 dfitrrdlvlgatedelay2;
+	u32 dfitrcmd;
+	u32 reserved14[46];
+	u32 ipvr;
+	u32 iptr;
+};
+check_member(rk3288_ddr_pctl, iptr, 0x03fc);
+
+struct rk3288_ddr_publ_datx {
+	u32 dxgcr;
+	u32 dxgsr[2];
+	u32 dxdllcr;
+	u32 dxdqtr;
+	u32 dxdqstr;
+	u32 reserved[10];
+};
+
+struct rk3288_ddr_publ {
+	u32 ridr;
+	u32 pir;
+	u32 pgcr;
+	u32 pgsr;
+	u32 dllgcr;
+	u32 acdllcr;
+	u32 ptr[3];
+	u32 aciocr;
+	u32 dxccr;
+	u32 dsgcr;
+	u32 dcr;
+	u32 dtpr[3];
+	u32 mr[4];
+	u32 odtcr;
+	u32 dtar;
+	u32 dtdr[2];
+	u32 reserved1[24];
+	u32 dcuar;
+	u32 dcudr;
+	u32 dcurr;
+	u32 dculr;
+	u32 dcugcr;
+	u32 dcutpr;
+	u32 dcusr[2];
+	u32 reserved2[8];
+	u32 bist[17];
+	u32 reserved3[15];
+	u32 zq0cr[2];
+	u32 zq0sr[2];
+	u32 zq1cr[2];
+	u32 zq1sr[2];
+	u32 zq2cr[2];
+	u32 zq2sr[2];
+	u32 zq3cr[2];
+	u32 zq3sr[2];
+	struct rk3288_ddr_publ_datx datx8[4];
+};
+check_member(rk3288_ddr_publ, datx8[3].dxdqstr, 0x0294);
+
+struct rk3288_msch {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 reserved1[8];
+	u32 activate;
+	u32 devtodev;
+};
+check_member(rk3288_msch, devtodev, 0x003c);
+
+/* PCT_DFISTCFG0 */
+#define DFI_INIT_START			(1 << 0)
+
+/* PCT_DFISTCFG1 */
+#define DFI_DRAM_CLK_SR_EN		(1 << 0)
+#define DFI_DRAM_CLK_DPD_EN		(1 << 1)
+
+/* PCT_DFISTCFG2 */
+#define DFI_PARITY_INTR_EN		(1 << 0)
+#define DFI_PARITY_EN			(1 << 1)
+
+/* PCT_DFILPCFG0 */
+#define TLP_RESP_TIME_SHIFT		16
+#define LP_SR_EN			(1 << 8)
+#define LP_PD_EN			(1 << 0)
+
+/* PCT_DFITCTRLDELAY */
+#define TCTRL_DELAY_TIME_SHIFT		0
+
+/* PCT_DFITPHYWRDATA */
+#define TPHY_WRDATA_TIME_SHIFT		0
+
+/* PCT_DFITPHYRDLAT */
+#define TPHY_RDLAT_TIME_SHIFT		0
+
+/* PCT_DFITDRAMCLKDIS */
+#define TDRAM_CLK_DIS_TIME_SHIFT	0
+
+/* PCT_DFITDRAMCLKEN */
+#define TDRAM_CLK_EN_TIME_SHIFT		0
+
+/* PCTL_DFIODTCFG */
+#define RANK0_ODT_WRITE_SEL		(1 << 3)
+#define RANK1_ODT_WRITE_SEL		(1 << 11)
+
+/* PCTL_DFIODTCFG1 */
+#define ODT_LEN_BL8_W_SHIFT		16
+
+/* PUBL_ACDLLCR */
+#define ACDLLCR_DLLDIS			(1 << 31)
+#define ACDLLCR_DLLSRST			(1 << 30)
+
+/* PUBL_DXDLLCR */
+#define DXDLLCR_DLLDIS			(1 << 31)
+#define DXDLLCR_DLLSRST			(1 << 30)
+
+/* PUBL_DLLGCR */
+#define DLLGCR_SBIAS			(1 << 30)
+
+/* PUBL_DXGCR */
+#define DQSRTT				(1 << 9)
+#define DQRTT				(1 << 10)
+
+/* PIR */
+#define PIR_INIT			(1 << 0)
+#define PIR_DLLSRST			(1 << 1)
+#define PIR_DLLLOCK			(1 << 2)
+#define PIR_ZCAL			(1 << 3)
+#define PIR_ITMSRST			(1 << 4)
+#define PIR_DRAMRST			(1 << 5)
+#define PIR_DRAMINIT			(1 << 6)
+#define PIR_QSTRN			(1 << 7)
+#define PIR_RVTRN			(1 << 8)
+#define PIR_ICPC			(1 << 16)
+#define PIR_DLLBYP			(1 << 17)
+#define PIR_CTLDINIT			(1 << 18)
+#define PIR_CLRSR			(1 << 28)
+#define PIR_LOCKBYP			(1 << 29)
+#define PIR_ZCALBYP			(1 << 30)
+#define PIR_INITBYP			(1u << 31)
+
+/* PGCR */
+#define PGCR_DFTLMT_SHIFT		3
+#define PGCR_DFTCMP_SHIFT		2
+#define PGCR_DQSCFG_SHIFT		1
+#define PGCR_ITMDMD_SHIFT		0
+
+/* PGSR */
+#define PGSR_IDONE			(1 << 0)
+#define PGSR_DLDONE			(1 << 1)
+#define PGSR_ZCDONE			(1 << 2)
+#define PGSR_DIDONE			(1 << 3)
+#define PGSR_DTDONE			(1 << 4)
+#define PGSR_DTERR			(1 << 5)
+#define PGSR_DTIERR			(1 << 6)
+#define PGSR_DFTERR			(1 << 7)
+#define PGSR_RVERR			(1 << 8)
+#define PGSR_RVEIRR			(1 << 9)
+
+/* PTR0 */
+#define PRT_ITMSRST_SHIFT		18
+#define PRT_DLLLOCK_SHIFT		6
+#define PRT_DLLSRST_SHIFT		0
+
+/* PTR1 */
+#define PRT_DINIT0_SHIFT		0
+#define PRT_DINIT1_SHIFT		19
+
+/* PTR2 */
+#define PRT_DINIT2_SHIFT		0
+#define PRT_DINIT3_SHIFT		17
+
+/* DCR */
+#define DDRMD_LPDDR			0
+#define DDRMD_DDR			1
+#define DDRMD_DDR2			2
+#define DDRMD_DDR3			3
+#define DDRMD_LPDDR2_LPDDR3		4
+#define DDRMD_MASK			7
+#define DDRMD_SHIFT			0
+#define PDQ_MASK			7
+#define PDQ_SHIFT			4
+
+/* DXCCR */
+#define DQSNRES_MASK			0xf
+#define DQSNRES_SHIFT			8
+#define DQSRES_MASK			0xf
+#define DQSRES_SHIFT			4
+
+/* DTPR */
+#define TDQSCKMAX_SHIFT			27
+#define TDQSCKMAX_MASK			7
+#define TDQSCK_SHIFT			24
+#define TDQSCK_MASK			7
+
+/* DSGCR */
+#define DQSGX_SHIFT			5
+#define DQSGX_MASK			7
+#define DQSGE_SHIFT			8
+#define DQSGE_MASK			7
+
+/* SCTL */
+#define INIT_STATE			0
+#define CFG_STATE			1
+#define GO_STATE			2
+#define SLEEP_STATE			3
+#define WAKEUP_STATE			4
+
+/* STAT */
+#define LP_TRIG_SHIFT			4
+#define LP_TRIG_MASK			7
+#define PCTL_STAT_MSK			7
+#define INIT_MEM			0
+#define CONFIG				1
+#define CONFIG_REQ			2
+#define ACCESS				3
+#define ACCESS_REQ			4
+#define LOW_POWER			5
+#define LOW_POWER_ENTRY_REQ		6
+#define LOW_POWER_EXIT_REQ		7
+
+/* ZQCR*/
+#define PD_OUTPUT_SHIFT			0
+#define PU_OUTPUT_SHIFT			5
+#define PD_ONDIE_SHIFT			10
+#define PU_ONDIE_SHIFT			15
+#define ZDEN_SHIFT			28
+
+/* DDLGCR */
+#define SBIAS_BYPASS			(1 << 23)
+
+/* MCFG */
+#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT	24
+#define PD_IDLE_SHIFT			8
+#define MDDR_EN				(2 << 22)
+#define LPDDR2_EN			(3 << 22)
+#define DDR2_EN				(0 << 5)
+#define DDR3_EN				(1 << 5)
+#define LPDDR2_S2			(0 << 6)
+#define LPDDR2_S4			(1 << 6)
+#define MDDR_LPDDR2_BL_2		(0 << 20)
+#define MDDR_LPDDR2_BL_4		(1 << 20)
+#define MDDR_LPDDR2_BL_8		(2 << 20)
+#define MDDR_LPDDR2_BL_16		(3 << 20)
+#define DDR2_DDR3_BL_4			0
+#define DDR2_DDR3_BL_8			1
+#define TFAW_SHIFT			18
+#define PD_EXIT_SLOW			(0 << 17)
+#define PD_EXIT_FAST			(1 << 17)
+#define PD_TYPE_SHIFT			16
+#define BURSTLENGTH_SHIFT		20
+
+/* POWCTL */
+#define POWER_UP_START			(1 << 0)
+
+/* POWSTAT */
+#define POWER_UP_DONE			(1 << 0)
+
+/* MCMD */
+enum {
+	DESELECT_CMD			= 0,
+	PREA_CMD,
+	REF_CMD,
+	MRS_CMD,
+	ZQCS_CMD,
+	ZQCL_CMD,
+	RSTL_CMD,
+	MRR_CMD				= 8,
+	DPDE_CMD,
+};
+
+#define LPDDR2_MA_SHIFT			4
+#define LPDDR2_MA_MASK			0xff
+#define LPDDR2_OP_SHIFT			12
+#define LPDDR2_OP_MASK			0xff
+
+#define START_CMD			(1u << 31)
+
+/*
+ * DDRCONF
+ * [5:4] row(13+n)
+ * [1:0] col(9+n), assume bw=2
+ */
+#define DDRCONF_ROW_SHIFT		4
+#define DDRCONF_COL_SHIFT		0
+
+/* DEVTODEV */
+#define BUSWRTORD_SHIFT			4
+#define BUSRDTOWR_SHIFT			2
+#define BUSRDTORD_SHIFT			0
+
+/* mr1 for ddr3 */
+#define DDR3_DLL_DISABLE		1
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
new file mode 100644
index 0000000..82234cf
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#ifndef __ASM_ARCH_DDR_RK3368_H__
+#define __ASM_ARCH_DDR_RK3368_H__
+
+/*
+ * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
+ * in a few details. Most notably, it has an additional field to track
+ * tREFI in controller cycles (i.e. trefi_mem_ddr3).
+ */
+struct rk3368_ddr_pctl {
+	u32 scfg;
+	u32 sctl;
+	u32 stat;
+	u32 intrstat;
+	u32 reserved0[12];
+	u32 mcmd;
+	u32 powctl;
+	u32 powstat;
+	u32 cmdtstat;
+	u32 cmdtstaten;
+	u32 reserved1[3];
+	u32 mrrcfg0;
+	u32 mrrstat0;
+	u32 mrrstat1;
+	u32 reserved2[4];
+	u32 mcfg1;
+	u32 mcfg;
+	u32 ppcfg;
+	u32 mstat;
+	u32 lpddr2zqcfg;
+	u32 reserved3;
+	u32 dtupdes;
+	u32 dtuna;
+	u32 dtune;
+	u32 dtuprd0;
+	u32 dtuprd1;
+	u32 dtuprd2;
+	u32 dtuprd3;
+	u32 dtuawdt;
+	u32 reserved4[3];
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+	u32 trefi_mem_ddr3;
+	u32 reserved5[45];
+	u32 dtuwactl;
+	u32 dturactl;
+	u32 dtucfg;
+	u32 dtuectl;
+	u32 dtuwd0;
+	u32 dtuwd1;
+	u32 dtuwd2;
+	u32 dtuwd3;
+	u32 dtuwdm;
+	u32 dturd0;
+	u32 dturd1;
+	u32 dturd2;
+	u32 dturd3;
+	u32 dtulfsrwd;
+	u32 dtulfsrrd;
+	u32 dtueaf;
+	u32 dfitctrldelay;
+	u32 dfiodtcfg;
+	u32 dfiodtcfg1;
+	u32 dfiodtrankmap;
+	u32 dfitphywrdata;
+	u32 dfitphywrlat;
+	u32 reserved7[2];
+	u32 dfitrddataen;
+	u32 dfitphyrdlat;
+	u32 reserved8[2];
+	u32 dfitphyupdtype0;
+	u32 dfitphyupdtype1;
+	u32 dfitphyupdtype2;
+	u32 dfitphyupdtype3;
+	u32 dfitctrlupdmin;
+	u32 dfitctrlupdmax;
+	u32 dfitctrlupddly;
+	u32 reserved9;
+	u32 dfiupdcfg;
+	u32 dfitrefmski;
+	u32 dfitctrlupdi;
+	u32 reserved10[4];
+	u32 dfitrcfg0;
+	u32 dfitrstat0;
+	u32 dfitrwrlvlen;
+	u32 dfitrrdlvlen;
+	u32 dfitrrdlvlgateen;
+	u32 dfiststat0;
+	u32 dfistcfg0;
+	u32 dfistcfg1;
+	u32 reserved11;
+	u32 dfitdramclken;
+	u32 dfitdramclkdis;
+	u32 dfistcfg2;
+	u32 dfistparclr;
+	u32 dfistparlog;
+	u32 reserved12[3];
+	u32 dfilpcfg0;
+	u32 reserved13[3];
+	u32 dfitrwrlvlresp0;
+	u32 dfitrwrlvlresp1;
+	u32 dfitrwrlvlresp2;
+	u32 dfitrrdlvlresp0;
+	u32 dfitrrdlvlresp1;
+	u32 dfitrrdlvlresp2;
+	u32 dfitrwrlvldelay0;
+	u32 dfitrwrlvldelay1;
+	u32 dfitrwrlvldelay2;
+	u32 dfitrrdlvldelay0;
+	u32 dfitrrdlvldelay1;
+	u32 dfitrrdlvldelay2;
+	u32 dfitrrdlvlgatedelay0;
+	u32 dfitrrdlvlgatedelay1;
+	u32 dfitrrdlvlgatedelay2;
+	u32 dfitrcmd;
+	u32 reserved14[46];
+	u32 ipvr;
+	u32 iptr;
+};
+check_member(rk3368_ddr_pctl, iptr, 0x03fc);
+
+struct rk3368_ddrphy {
+	u32 reg[0x100];
+};
+check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
+
+struct rk3368_msch {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 reserved1[8];
+	u32 activate;
+	u32 devtodev;
+};
+check_member(rk3368_msch, devtodev, 0x003c);
+
+/* GRF_SOC_CON0 */
+enum {
+	NOC_RSP_ERR_STALL = BIT(9),
+	MOBILE_DDR_SEL = BIT(4),
+	DDR0_16BIT_EN = BIT(3),
+	MSCH0_MAINDDR3_DDR3 = BIT(2),
+	MSCH0_MAINPARTIALPOP = BIT(1),
+	UPCTL_C_ACTIVE = BIT(0),
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
new file mode 100644
index 0000000..105a335
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
@@ -0,0 +1,635 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_EDP_H
+#define _ASM_ARCH_EDP_H
+
+struct rk3288_edp {
+	u8	res0[0x10];
+	u32	dp_tx_version;
+	u8	res1[0x4];
+	u32	func_en_1;
+	u32	func_en_2;
+	u32	video_ctl_1;
+	u32	video_ctl_2;
+	u32	video_ctl_3;
+	u32	video_ctl_4;
+	u8	res2[0xc];
+	u32	video_ctl_8;
+	u8	res3[0x4];
+	u32	video_ctl_10;
+	u32	total_line_l;
+	u32	total_line_h;
+	u32	active_line_l;
+	u32	active_line_h;
+	u32	v_f_porch;
+	u32	vsync;
+	u32	v_b_porch;
+	u32	total_pixel_l;
+	u32	total_pixel_h;
+	u32	active_pixel_l;
+	u32	active_pixel_h;
+	u32	h_f_porch_l;
+	u32	h_f_porch_h;
+	u32	hsync_l;
+	u32	hysnc_h;
+	u32	h_b_porch_l;
+	u32	h_b_porch_h;
+	u32	vid_status;
+	u32	total_line_sta_l;
+	u32	total_line_sta_h;
+	u32	active_line_sta_l;
+	u32	active_line_sta_h;
+	u32	v_f_porch_sta;
+	u32	vsync_sta;
+	u32	v_b_porch_sta;
+	u32	total_pixel_sta_l;
+	u32	total_pixel_sta_h;
+	u32	active_pixel_sta_l;
+	u32	active_pixel_sta_h;
+	u32	h_f_porch_sta_l;
+	u32	h_f_porch_sta_h;
+	u32	hsync_sta_l;
+	u32	hsync_sta_h;
+	u32	h_b_porch_sta_l;
+	u32	h_b_porch__sta_h;
+	u8      res4[0x28];
+	u32	pll_reg_1;
+	u8	res5[4];
+	u32	ssc_reg;
+	u8	res6[0xc];
+	u32	tx_common;
+	u32	tx_common2;
+	u8	res7[0x4];
+	u32	dp_aux;
+	u32	dp_bias;
+	u32	dp_test;
+	u32	dp_pd;
+	u32	dp_reserv1;
+	u32	dp_reserv2;
+	u8	res8[0x224];
+	u32	lane_map;
+	u8	res9[0x14];
+	u32	analog_ctl_2;
+	u8	res10[0x48];
+	u32	int_state;
+	u32	common_int_sta_1;
+	u32	common_int_sta_2;
+	u32	common_int_sta_3;
+	u32	common_int_sta_4;
+	u32	spdif_biphase_int_sta;
+	u8	res11[0x4];
+	u32	dp_int_sta;
+	u32	common_int_mask_1;
+	u32	common_int_mask_2;
+	u32	common_int_mask_3;
+	u32	common_int_mask_4;
+	u8	res12[0x08];
+	u32	int_sta_mask;
+	u32	int_ctl;
+	u8	res13[0x200];
+	u32	sys_ctl_1;
+	u32	sys_ctl_2;
+	u32	sys_ctl_3;
+	u32	sys_ctl_4;
+	u32	dp_vid_ctl;
+	u8	res14[0x4];
+	u32	dp_aud_ctl;
+	u8	res15[0x24];
+	u32	pkt_send_ctl;
+	u8	res16[0x4];
+	u32	dp_hdcp_ctl;
+	u8	res17[0x34];
+	u32	link_bw_set;
+	u32	lane_count_set;
+	u32	dp_training_ptn_set;
+	u32	ln_link_trn_ctl[4];
+	u8	res18[0x4];
+	u32	dp_hw_link_training;
+	u8	res19[0x1c];
+	u32	dp_debug_ctl;
+	u32	hpd_deglitch_l;
+	u32	hpd_deglitch_h;
+	u8	res20[0x14];
+	u32	dp_link_debug_ctl;
+	u8	res21[0x1c];
+	u32	m_vid_0;
+	u32	m_vid_1;
+	u32	m_vid_2;
+	u32	n_vid_0;
+	u32	n_vid_1;
+	u32	n_vid_2;
+	u32	m_vid_mon;
+	u8	res22[0x14];
+	u32	dp_video_fifo_thrd;
+	u8	res23[0x8];
+	u32	dp_audio_margin;
+	u8	res24[0x20];
+	u32	dp_m_cal_ctl;
+	u32	m_vid_gen_filter_th;
+	u8	res25[0x10];
+	u32	m_aud_gen_filter_th;
+	u8	res26[0x4];
+	u32	aux_ch_sta;
+	u32	aux_err_num;
+	u32	aux_ch_defer_dtl;
+	u32	aux_rx_comm;
+	u32	buf_data_ctl;
+	u32	aux_ch_ctl_1;
+	u32	aux_addr_7_0;
+	u32	aux_addr_15_8;
+	u32	aux_addr_19_16;
+	u32	aux_ch_ctl_2;
+	u8	res27[0x18];
+	u32	buf_data[16];
+	u32	soc_general_ctl;
+	u8	res29[0x1e0];
+	u32	pll_reg_2;
+	u32	pll_reg_3;
+	u32	pll_reg_4;
+	u8	res30[0x10];
+	u32	pll_reg_5;
+};
+check_member(rk3288_edp, pll_reg_5, 0xa00);
+
+/* func_en_1 */
+#define VID_CAP_FUNC_EN_N			(0x1 << 6)
+#define VID_FIFO_FUNC_EN_N			(0x1 << 5)
+#define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
+#define AUD_FUNC_EN_N				(0x1 << 3)
+#define HDCP_FUNC_EN_N				(0x1 << 2)
+#define SW_FUNC_EN_N				(0x1 << 0)
+
+/* func_en_2 */
+#define SSC_FUNC_EN_N				(0x1 << 7)
+#define AUX_FUNC_EN_N				(0x1 << 2)
+#define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
+
+/* video_ctl_1 */
+#define VIDEO_EN				(0x1 << 7)
+#define VIDEO_MUTE				(0x1 << 6)
+
+/* video_ctl_2 */
+#define IN_D_RANGE_MASK				(0x1 << 7)
+#define IN_D_RANGE_SHIFT			(7)
+#define IN_D_RANGE_CEA				(0x1 << 7)
+#define IN_D_RANGE_VESA				(0x0 << 7)
+#define IN_BPC_MASK				(0x7 << 4)
+#define IN_BPC_SHIFT				(4)
+#define IN_BPC_12_BITS				(0x3 << 4)
+#define IN_BPC_10_BITS				(0x2 << 4)
+#define IN_BPC_8_BITS				(0x1 << 4)
+#define IN_BPC_6_BITS				(0x0 << 4)
+#define IN_COLOR_F_MASK				(0x3 << 0)
+#define IN_COLOR_F_SHIFT			(0)
+#define IN_COLOR_F_YCBCR444			(0x2 << 0)
+#define IN_COLOR_F_YCBCR422			(0x1 << 0)
+#define IN_COLOR_F_RGB				(0x0 << 0)
+
+/* video_ctl_3 */
+#define IN_YC_COEFFI_MASK			(0x1 << 7)
+#define IN_YC_COEFFI_SHIFT			(7)
+#define IN_YC_COEFFI_ITU709			(0x1 << 7)
+#define IN_YC_COEFFI_ITU601			(0x0 << 7)
+#define VID_CHK_UPDATE_TYPE_MASK		(0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_SHIFT		(4)
+#define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
+
+/* video_ctl_4 */
+#define BIST_EN					(0x1 << 3)
+#define BIST_WH_64				(0x1 << 2)
+#define BIST_WH_32				(0x0 << 2)
+#define BIST_TYPE_COLR_BAR			(0x0 << 0)
+#define BIST_TYPE_GRAY_BAR			(0x1 << 0)
+#define BIST_TYPE_MOBILE_BAR			(0x2 << 0)
+
+/* video_ctl_8 */
+#define VID_HRES_TH(x)				(((x) & 0xf) << 4)
+#define VID_VRES_TH(x)				(((x) & 0xf) << 0)
+
+/* video_ctl_10 */
+#define F_SEL					(0x1 << 4)
+#define INTERACE_SCAN_CFG			(0x1 << 2)
+#define INTERACD_SCAN_CFG_OFFSET		2
+#define VSYNC_POLARITY_CFG			(0x1 << 1)
+#define VSYNC_POLARITY_CFG_OFFSET		1
+#define HSYNC_POLARITY_CFG			(0x1 << 0)
+#define HSYNC_POLARITY_CFG_OFFSET		0
+
+/* dp_pd */
+#define PD_INC_BG				(0x1 << 7)
+#define PD_EXP_BG				(0x1 << 6)
+#define PD_AUX					(0x1 << 5)
+#define PD_PLL					(0x1 << 4)
+#define PD_CH3					(0x1 << 3)
+#define PD_CH2					(0x1 << 2)
+#define PD_CH1					(0x1 << 1)
+#define PD_CH0					(0x1 << 0)
+
+/* pll_reg_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
+/* line_map */
+#define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
+#define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
+#define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
+#define LANE3_MAP_LOGIC_LANE_3			(0x3 << 6)
+#define LANE2_MAP_LOGIC_LANE_0			(0x0 << 4)
+#define LANE2_MAP_LOGIC_LANE_1			(0x1 << 4)
+#define LANE2_MAP_LOGIC_LANE_2			(0x2 << 4)
+#define LANE2_MAP_LOGIC_LANE_3			(0x3 << 4)
+#define LANE1_MAP_LOGIC_LANE_0			(0x0 << 2)
+#define LANE1_MAP_LOGIC_LANE_1			(0x1 << 2)
+#define LANE1_MAP_LOGIC_LANE_2			(0x2 << 2)
+#define LANE1_MAP_LOGIC_LANE_3			(0x3 << 2)
+#define LANE0_MAP_LOGIC_LANE_0			(0x0 << 0)
+#define LANE0_MAP_LOGIC_LANE_1			(0x1 << 0)
+#define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
+#define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
+
+/* analog_ctl_2 */
+#define SEL_24M					(0x1 << 3)
+
+/* common_int_sta_1 */
+#define VSYNC_DET				(0x1 << 7)
+#define PLL_LOCK_CHG				(0x1 << 6)
+#define SPDIF_ERR				(0x1 << 5)
+#define SPDIF_UNSTBL				(0x1 << 4)
+#define VID_FORMAT_CHG				(0x1 << 3)
+#define AUD_CLK_CHG				(0x1 << 2)
+#define VID_CLK_CHG				(0x1 << 1)
+#define SW_INT					(0x1 << 0)
+
+/* common_int_sta_2 */
+#define ENC_EN_CHG				(0x1 << 6)
+#define HW_BKSV_RDY				(0x1 << 3)
+#define HW_SHA_DONE				(0x1 << 2)
+#define HW_AUTH_STATE_CHG			(0x1 << 1)
+#define HW_AUTH_DONE				(0x1 << 0)
+
+/* common_int_sta_3 */
+#define AFIFO_UNDER				(0x1 << 7)
+#define AFIFO_OVER				(0x1 << 6)
+#define R0_CHK_FLAG				(0x1 << 5)
+
+/* common_int_sta_4 */
+#define PSR_ACTIVE				(0x1 << 7)
+#define PSR_INACTIVE				(0x1 << 6)
+#define SPDIF_BI_PHASE_ERR			(0x1 << 5)
+#define HOTPLUG_CHG				(0x1 << 2)
+#define HPD_LOST				(0x1 << 1)
+#define PLUG					(0x1 << 0)
+
+/* dp_int_sta */
+#define INT_HPD					(0x1 << 6)
+#define HW_LT_DONE				(0x1 << 5)
+#define SINK_LOST				(0x1 << 3)
+#define LINK_LOST				(0x1 << 2)
+#define RPLY_RECEIV				(0x1 << 1)
+#define AUX_ERR					(0x1 << 0)
+
+/* int_ctl */
+#define SOFT_INT_CTRL				(0x1 << 2)
+#define INT_POL					(0x1 << 0)
+
+/* sys_ctl_1 */
+#define DET_STA					(0x1 << 2)
+#define FORCE_DET				(0x1 << 1)
+#define DET_CTRL				(0x1 << 0)
+
+/* sys_ctl_2 */
+#define CHA_CRI(x)				(((x) & 0xf) << 4)
+#define CHA_STA					(0x1 << 2)
+#define FORCE_CHA				(0x1 << 1)
+#define CHA_CTRL				(0x1 << 0)
+
+/* sys_ctl_3 */
+#define HPD_STATUS				(0x1 << 6)
+#define F_HPD					(0x1 << 5)
+#define HPD_CTRL				(0x1 << 4)
+#define HDCP_RDY				(0x1 << 3)
+#define STRM_VALID				(0x1 << 2)
+#define F_VALID					(0x1 << 1)
+#define VALID_CTRL				(0x1 << 0)
+
+/* sys_ctl_4 */
+#define FIX_M_AUD				(0x1 << 4)
+#define ENHANCED				(0x1 << 3)
+#define FIX_M_VID				(0x1 << 2)
+#define M_VID_UPDATE_CTRL			(0x3 << 0)
+
+/* pll_reg_2 */
+#define LDO_OUTPUT_V_SEL_145			(2 << 6)
+#define KVCO_DEFALUT				(1 << 4)
+#define CHG_PUMP_CUR_SEL_5US			(1 << 2)
+#define V2L_CUR_SEL_1MA				(1 << 0)
+
+/* pll_reg_3 */
+#define LOCK_DET_CNT_SEL_256			(2 << 5)
+#define LOOP_FILTER_RESET			(0 << 4)
+#define PALL_SSC_RESET				(0 << 3)
+#define LOCK_DET_BYPASS				(0 << 2)
+#define PLL_LOCK_DET_MODE			(0 << 1)
+#define PLL_LOCK_DET_FORCE			(0 << 0)
+
+/* pll_reg_5 */
+#define REGULATOR_V_SEL_950MV			(2 << 4)
+#define STANDBY_CUR_SEL				(0 << 3)
+#define CHG_PUMP_INOUT_CTRL_1200MV		(1 << 1)
+#define CHG_PUMP_INPUT_CTRL_OP			(0 << 0)
+
+/* ssc_reg */
+#define SSC_OFFSET				(0 << 6)
+#define SSC_MODE				(1 << 4)
+#define SSC_DEPTH				(9 << 0)
+
+/* tx_common */
+#define TX_SWING_PRE_EMP_MODE			(1 << 7)
+#define PRE_DRIVER_PW_CTRL1			(0 << 5)
+#define LP_MODE_CLK_REGULATOR			(0 << 4)
+#define RESISTOR_MSB_CTRL			(0 << 3)
+#define RESISTOR_CTRL				(7 << 0)
+
+/* dp_aux */
+#define DP_AUX_COMMON_MODE			(0 << 4)
+#define DP_AUX_EN				(0 << 3)
+#define AUX_TERM_50OHM				(3 << 0)
+
+/* dp_bias */
+#define DP_BG_OUT_SEL				(4 << 4)
+#define DP_DB_CUR_CTRL				(0 << 3)
+#define DP_BG_SEL				(1 << 2)
+#define DP_RESISTOR_TUNE_BG			(2 << 0)
+
+/* dp_reserv2 */
+#define CH1_CH3_SWING_EMP_CTRL			(5 << 4)
+#define CH0_CH2_SWING_EMP_CTRL			(5 << 0)
+
+/* dp_training_ptn_set */
+#define SCRAMBLING_DISABLE			(0x1 << 5)
+#define SCRAMBLING_ENABLE			(0x0 << 5)
+#define LINK_QUAL_PATTERN_SET_MASK		(0x7 << 2)
+#define LINK_QUAL_PATTERN_SET_HBR2		(0x5 << 2)
+#define LINK_QUAL_PATTERN_SET_80BIT		(0x4 << 2)
+#define LINK_QUAL_PATTERN_SET_PRBS7		(0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_D10_2		(0x1 << 2)
+#define LINK_QUAL_PATTERN_SET_DISABLE		(0x0 << 2)
+#define SW_TRAINING_PATTERN_SET_MASK		(0x3 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN2		(0x2 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
+#define SW_TRAINING_PATTERN_SET_DISABLE		(0x0 << 0)
+
+/* dp_hw_link_training_ctl */
+#define HW_LT_ERR_CODE_MASK			0x70
+#define HW_LT_ERR_CODE_SHIFT			4
+#define HW_LT_EN				(0x1 << 0)
+
+/* dp_debug_ctl */
+#define PLL_LOCK				(0x1 << 4)
+#define F_PLL_LOCK				(0x1 << 3)
+#define PLL_LOCK_CTRL				(0x1 << 2)
+#define POLL_EN					(0x1 << 1)
+#define PN_INV					(0x1 << 0)
+
+/* aux_ch_sta */
+#define AUX_BUSY				(0x1 << 4)
+#define AUX_STATUS_MASK				(0xf << 0)
+
+/* aux_ch_defer_ctl */
+#define DEFER_CTRL_EN				(0x1 << 7)
+#define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
+
+/* aux_rx_comm */
+#define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
+#define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
+
+/* buffer_data_ctl */
+#define BUF_CLR					(0x1 << 7)
+#define BUF_HAVE_DATA				(0x1 << 4)
+#define BUF_DATA_COUNT(x)			(((x) & 0xf) << 0)
+
+/* aux_ch_ctl_1 */
+#define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
+#define AUX_TX_COMM_MASK			(0xf << 0)
+#define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
+#define AUX_TX_COMM_I2C_TRANSACTION		(0x0 << 3)
+#define AUX_TX_COMM_MOT				(0x1 << 2)
+#define AUX_TX_COMM_WRITE			(0x0 << 0)
+#define AUX_TX_COMM_READ			(0x1 << 0)
+
+/* aux_ch_ctl_2 */
+#define PD_AUX_IDLE				(0x1 << 3)
+#define ADDR_ONLY				(0x1 << 1)
+#define AUX_EN					(0x1 << 0)
+
+/* tx_sw_reset */
+#define RST_DP_TX				(0x1 << 0)
+
+/* analog_ctl_1 */
+#define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
+
+/* analog_ctl_3 */
+#define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
+#define VCO_BIT_600_MICRO			(0x5 << 0)
+
+/* pll_filter_ctl_1 */
+#define PD_RING_OSC				(0x1 << 6)
+#define AUX_TERMINAL_CTRL_37_5_OHM		(0x0 << 4)
+#define AUX_TERMINAL_CTRL_45_OHM		(0x1 << 4)
+#define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
+#define AUX_TERMINAL_CTRL_65_OHM		(0x3 << 4)
+#define TX_CUR1_2X				(0x1 << 2)
+#define TX_CUR_16_MA				(0x3 << 0)
+
+/* Definition for DPCD Register */
+#define DPCD_DPCD_REV				(0x0000)
+#define DPCD_MAX_LINK_RATE			(0x0001)
+#define DPCD_MAX_LANE_COUNT			(0x0002)
+#define DP_MAX_LANE_COUNT_MASK			0x1f
+#define DP_TPS3_SUPPORTED			(1 << 6)
+#define DP_ENHANCED_FRAME_CAP			(1 << 7)
+
+#define DPCD_LINK_BW_SET			(0x0100)
+#define DPCD_LANE_COUNT_SET			(0x0101)
+
+#define DPCD_TRAINING_PATTERN_SET		(0x0102)
+#define DP_TRAINING_PATTERN_DISABLE		0
+#define DP_TRAINING_PATTERN_1			1
+#define DP_TRAINING_PATTERN_2			2
+#define DP_TRAINING_PATTERN_3			3
+#define DP_TRAINING_PATTERN_MASK		0x3
+
+#define DPCD_TRAINING_LANE0_SET			(0x0103)
+#define DP_TRAIN_VOLTAGE_SWING_MASK		0x3
+#define DP_TRAIN_VOLTAGE_SWING_SHIFT		0
+#define DP_TRAIN_MAX_SWING_REACHED		(1 << 2)
+#define DP_TRAIN_VOLTAGE_SWING_400		(0 << 0)
+#define DP_TRAIN_VOLTAGE_SWING_600		(1 << 0)
+#define DP_TRAIN_VOLTAGE_SWING_800		(2 << 0)
+#define DP_TRAIN_VOLTAGE_SWING_1200		(3 << 0)
+
+#define DP_TRAIN_PRE_EMPHASIS_MASK		(3 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_0			(0 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_3_5		(1 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_6			(2 << 3)
+#define DP_TRAIN_PRE_EMPHASIS_9_5		(3 << 3)
+
+#define DP_TRAIN_PRE_EMPHASIS_SHIFT		3
+#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED	(1 << 5)
+
+#define DPCD_LANE0_1_STATUS			(0x0202)
+#define DPCD_LANE2_3_STATUS			(0x0203)
+#define DP_LANE_CR_DONE				(1 << 0)
+#define DP_LANE_CHANNEL_EQ_DONE			(1 << 1)
+#define DP_LANE_SYMBOL_LOCKED			(1 << 2)
+#define DP_CHANNEL_EQ_BITS			(DP_LANE_CR_DONE |\
+						DP_LANE_CHANNEL_EQ_DONE |\
+						DP_LANE_SYMBOL_LOCKED)
+
+#define DPCD_LANE_ALIGN_STATUS_UPDATED		(0x0204)
+#define DP_INTERLANE_ALIGN_DONE			(1 << 0)
+#define DP_DOWNSTREAM_PORT_STATUS_CHANGED	(1 << 6)
+#define DP_LINK_STATUS_UPDATED			(1 << 7)
+
+#define DPCD_ADJUST_REQUEST_LANE0_1		(0x0206)
+#define DPCD_ADJUST_REQUEST_LANE2_3		(0x0207)
+#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK	0x03
+#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT	0
+#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK	0x0c
+#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT	2
+#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK	0x30
+#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT	4
+#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK	0xc0
+#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT	6
+
+#define DPCD_TEST_REQUEST			(0x0218)
+#define DPCD_TEST_RESPONSE			(0x0260)
+#define DPCD_TEST_EDID_CHECKSUM			(0x0261)
+#define DPCD_LINK_POWER_STATE			(0x0600)
+#define DP_SET_POWER_D0				0x1
+#define DP_SET_POWER_D3				0x2
+#define DP_SET_POWER_MASK			0x3
+
+#define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
+#define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
+#define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
+
+#define STREAM_ON_TIMEOUT 100
+#define PLL_LOCK_TIMEOUT 10
+#define DP_INIT_TRIES 10
+
+#define EDID_ADDR				0x50
+#define EDID_LENGTH				0x80
+#define EDID_HEADER				0x00
+#define EDID_EXTENSION_FLAG			0x7e
+
+
+enum dpcd_request {
+	DPCD_READ,
+	DPCD_WRITE,
+};
+
+enum dp_irq_type {
+	DP_IRQ_TYPE_HP_CABLE_IN,
+	DP_IRQ_TYPE_HP_CABLE_OUT,
+	DP_IRQ_TYPE_HP_CHANGE,
+	DP_IRQ_TYPE_UNKNOWN,
+};
+
+enum color_coefficient {
+	COLOR_YCBCR601,
+	COLOR_YCBCR709
+};
+
+enum dynamic_range {
+	VESA,
+	CEA
+};
+
+enum clock_recovery_m_value_type {
+	CALCULATED_M,
+	REGISTER_M
+};
+
+enum video_timing_recognition_type {
+	VIDEO_TIMING_FROM_CAPTURE,
+	VIDEO_TIMING_FROM_REGISTER
+};
+
+enum pattern_set {
+	PRBS7,
+	D10_2,
+	TRAINING_PTN1,
+	TRAINING_PTN2,
+	DP_NONE
+};
+
+enum color_space {
+	CS_RGB,
+	CS_YCBCR422,
+	CS_YCBCR444
+};
+
+enum color_depth {
+	COLOR_6,
+	COLOR_8,
+	COLOR_10,
+	COLOR_12
+};
+
+enum link_rate_type {
+	LINK_RATE_1_62GBPS = 0x06,
+	LINK_RATE_2_70GBPS = 0x0a
+};
+
+enum link_lane_count_type {
+	LANE_CNT1 = 1,
+	LANE_CNT2 = 2,
+	LANE_CNT4 = 4
+};
+
+enum link_training_state {
+	LT_START,
+	LT_CLK_RECOVERY,
+	LT_EQ_TRAINING,
+	FINISHED,
+	FAILED
+};
+
+enum voltage_swing_level {
+	VOLTAGE_LEVEL_0,
+	VOLTAGE_LEVEL_1,
+	VOLTAGE_LEVEL_2,
+	VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+	PRE_EMPHASIS_LEVEL_0,
+	PRE_EMPHASIS_LEVEL_1,
+	PRE_EMPHASIS_LEVEL_2,
+	PRE_EMPHASIS_LEVEL_3,
+};
+
+enum analog_power_block {
+	AUX_BLOCK,
+	CH0_BLOCK,
+	CH1_BLOCK,
+	CH2_BLOCK,
+	CH3_BLOCK,
+	ANALOG_TOTAL,
+	POWER_ALL
+};
+
+struct link_train {
+	unsigned char revision;
+	u8 link_rate;
+	u8 lane_count;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/f_rockusb.h b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
new file mode 100644
index 0000000..9772321
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/f_rockusb.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017
+ *
+ * Eddie Cai <eddie.cai.linux@gmail.com>
+ */
+
+#ifndef _F_ROCKUSB_H_
+#define _F_ROCKUSB_H_
+#include <blk.h>
+
+#define ROCKUSB_VERSION		"0.1"
+
+#define ROCKUSB_INTERFACE_CLASS	0xff
+#define ROCKUSB_INTERFACE_SUB_CLASS	0x06
+#define ROCKUSB_INTERFACE_PROTOCOL	0x05
+
+#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_2_0  0x0200
+#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1  0x0040
+#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE      0x0040
+
+#define EP_BUFFER_SIZE			4096
+/*
+ * EP_BUFFER_SIZE must always be an integral multiple of maxpacket size
+ * (64 or 512 or 1024), else we break on certain controllers like DWC3
+ * that expect bulk OUT requests to be divisible by maxpacket size.
+ */
+
+#define RKUSB_BUF_SIZE		EP_BUFFER_SIZE * 2
+#define RKBLOCK_BUF_SIZE		4096
+
+#define RKUSB_STATUS_IDLE			0
+#define RKUSB_STATUS_CMD			1
+#define RKUSB_STATUS_RXDATA			2
+#define RKUSB_STATUS_TXDATA			3
+#define RKUSB_STATUS_CSW			4
+#define RKUSB_STATUS_RXDATA_PREPARE		5
+#define RKUSB_STATUS_TXDATA_PREPARE		6
+
+enum rkusb_command {
+K_FW_TEST_UNIT_READY	= 0x00,
+K_FW_READ_FLASH_ID = 0x01,
+K_FW_SET_DEVICE_ID = 0x02,
+K_FW_TEST_BAD_BLOCK = 0x03,
+K_FW_READ_10 = 0x04,
+K_FW_WRITE_10 = 0x05,
+K_FW_ERASE_10 = 0x06,
+K_FW_WRITE_SPARE = 0x07,
+K_FW_READ_SPARE = 0x08,
+
+K_FW_ERASE_10_FORCE = 0x0b,
+K_FW_GET_VERSION = 0x0c,
+
+K_FW_LBA_READ_10 = 0x14,
+K_FW_LBA_WRITE_10 = 0x15,
+K_FW_ERASE_SYS_DISK = 0x16,
+K_FW_SDRAM_READ_10 = 0x17,
+K_FW_SDRAM_WRITE_10 = 0x18,
+K_FW_SDRAM_EXECUTE = 0x19,
+K_FW_READ_FLASH_INFO = 0x1A,
+K_FW_GET_CHIP_VER = 0x1B,
+K_FW_LOW_FORMAT = 0x1C,
+K_FW_SET_RESET_FLAG = 0x1E,
+K_FW_SPI_READ_10 = 0x21,
+K_FW_SPI_WRITE_10 = 0x22,
+K_FW_LBA_ERASE_10 = 0x25,
+
+K_FW_SESSION = 0X30,
+K_FW_RESET = 0xff,
+};
+
+#define CBW_DIRECTION_OUT		0x00
+#define CBW_DIRECTION_IN		0x80
+
+struct cmd_dispatch_info {
+	enum rkusb_command cmd;
+	/* call back function to handle rockusb command */
+	void (*cb)(struct usb_ep *ep, struct usb_request *req);
+};
+
+/* Bulk-only data structures */
+
+/* Command Block Wrapper */
+struct fsg_bulk_cb_wrap {
+	__le32  signature;              /* Contains 'USBC' */
+	u32     tag;                    /* Unique per command id */
+	__le32  data_transfer_length;   /* Size of the data */
+	u8      flags;                  /* Direction in bit 7 */
+	u8      lun;                    /* lun (normally 0) */
+	u8      length;                 /* Of the CDB, <= MAX_COMMAND_SIZE */
+	u8      CDB[16];                /* Command Data Block */
+};
+
+#define USB_BULK_CB_WRAP_LEN    31
+#define USB_BULK_CB_SIG         0x43425355      /* Spells out USBC */
+#define USB_BULK_IN_FLAG        0x80
+
+/* Command status Wrapper */
+struct bulk_cs_wrap {
+	__le32  signature;              /* Should = 'USBS' */
+	u32     tag;                    /* Same as original command */
+	__le32  residue;                /* Amount not transferred */
+	u8      status;                 /* See below */
+};
+
+#define USB_BULK_CS_WRAP_LEN    13
+#define USB_BULK_CS_SIG         0x53425355      /* Spells out 'USBS' */
+#define USB_STATUS_PASS         0
+#define USB_STATUS_FAIL         1
+#define USB_STATUS_PHASE_ERROR  2
+
+#define CSW_GOOD                0x00
+#define CSW_FAIL                0x01
+
+struct f_rockusb {
+	struct usb_function usb_function;
+	struct usb_ep *in_ep, *out_ep;
+	struct usb_request *in_req, *out_req;
+	char *dev_type;
+	unsigned int dev_index;
+	unsigned int tag;
+	unsigned int lba;
+	unsigned int dl_size;
+	unsigned int dl_bytes;
+	unsigned int ul_size;
+	unsigned int ul_bytes;
+	struct blk_desc *desc;
+	int reboot_flag;
+	void *buf;
+	void *buf_head;
+};
+
+/* init rockusb device, tell rockusb which device you want to read/write*/
+void rockusb_dev_init(char *dev_type, int dev_index);
+#endif /* _F_ROCKUSB_H_ */
+
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h b/arch/arm/include/asm/arch-rockchip/gpio.h
new file mode 100644
index 0000000..1aaec5f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+struct rockchip_gpio_regs {
+	u32 swport_dr;
+	u32 swport_ddr;
+	u32 reserved0[(0x30 - 0x08) / 4];
+	u32 inten;
+	u32 intmask;
+	u32 inttype_level;
+	u32 int_polarity;
+	u32 int_status;
+	u32 int_rawstatus;
+	u32 debounce;
+	u32 porta_eoi;
+	u32 ext_port;
+	u32 reserved1[(0x60 - 0x54) / 4];
+	u32 ls_sync;
+};
+check_member(rockchip_gpio_regs, ls_sync, 0x60);
+
+enum gpio_pu_pd {
+	GPIO_PULL_NORMAL = 0,
+	GPIO_PULL_UP,
+	GPIO_PULL_DOWN,
+	GPIO_PULL_REPEAT,
+};
+
+/* These defines are only used by spl_gpio.h */
+enum {
+	/* Banks have 8 GPIOs, so 3 bits, and there are 4 banks, so 2 bits */
+	GPIO_BANK_SHIFT		= 3,
+	GPIO_BANK_MASK		= 3 << GPIO_BANK_SHIFT,
+
+	GPIO_OFFSET_MASK	= 0x1f,
+};
+
+#define GPIO(bank, offset)	((bank) << GPIO_BANK_SHIFT | (offset))
+
+enum gpio_bank_t {
+	BANK_A = 0,
+	BANK_B,
+	BANK_C,
+	BANK_D,
+};
+
+enum gpio_dir_t {
+	GPIO_INPUT = 0,
+	GPIO_OUTPUT,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
new file mode 100644
index 0000000..5f12ebf
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_GRF_RK3036_H
+#define _ASM_ARCH_GRF_RK3036_H
+
+#include <common.h>
+
+struct rk3036_grf {
+	unsigned int reserved[0x2a];
+	unsigned int gpio0a_iomux;
+	unsigned int gpio0b_iomux;
+	unsigned int gpio0c_iomux;
+	unsigned int gpio0d_iomux;
+
+	unsigned int gpio1a_iomux;
+	unsigned int gpio1b_iomux;
+	unsigned int gpio1c_iomux;
+	unsigned int gpio1d_iomux;
+
+	unsigned int gpio2a_iomux;
+	unsigned int gpio2b_iomux;
+	unsigned int gpio2c_iomux;
+	unsigned int gpio2d_iomux;
+
+	unsigned int reserved2[0x0a];
+	unsigned int gpiods;
+	unsigned int reserved3[0x05];
+	unsigned int gpio0l_pull;
+	unsigned int gpio0h_pull;
+	unsigned int gpio1l_pull;
+	unsigned int gpio1h_pull;
+	unsigned int gpio2l_pull;
+	unsigned int gpio2h_pull;
+	unsigned int reserved4[4];
+	unsigned int soc_con0;
+	unsigned int soc_con1;
+	unsigned int soc_con2;
+	unsigned int soc_status0;
+	unsigned int reserved5;
+	unsigned int soc_con3;
+	unsigned int reserved6;
+	unsigned int dmac_con0;
+	unsigned int dmac_con1;
+	unsigned int dmac_con2;
+	unsigned int reserved7[5];
+	unsigned int uoc0_con5;
+	unsigned int reserved8[4];
+	unsigned int uoc1_con4;
+	unsigned int uoc1_con5;
+	unsigned int reserved9;
+	unsigned int ddrc_stat;
+	unsigned int uoc_con6;
+	unsigned int soc_status1;
+	unsigned int cpu_con0;
+	unsigned int cpu_con1;
+	unsigned int cpu_con2;
+	unsigned int cpu_con3;
+	unsigned int reserved10;
+	unsigned int reserved11;
+	unsigned int cpu_status0;
+	unsigned int cpu_status1;
+	unsigned int os_reg[8];
+	unsigned int reserved12[6];
+	unsigned int dll_con[4];
+	unsigned int dll_status[4];
+	unsigned int dfi_wrnum;
+	unsigned int dfi_rdnum;
+	unsigned int dfi_actnum;
+	unsigned int dfi_timerval;
+	unsigned int nfi_fifo[4];
+	unsigned int reserved13[0x10];
+	unsigned int usbphy0_con[8];
+	unsigned int usbphy1_con[8];
+	unsigned int reserved14[0x10];
+	unsigned int chip_tag;
+	unsigned int sdmmc_det_cnt;
+};
+check_member(rk3036_grf, sdmmc_det_cnt, 0x304);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3128.h b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h
new file mode 100644
index 0000000..519b36a
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3128.h
@@ -0,0 +1,550 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_GRF_RK3128_H
+#define _ASM_ARCH_GRF_RK3128_H
+
+#include <common.h>
+
+struct rk3128_grf {
+	unsigned int reserved[0x2a];
+	unsigned int gpio0a_iomux;
+	unsigned int gpio0b_iomux;
+	unsigned int gpio0c_iomux;
+	unsigned int gpio0d_iomux;
+	unsigned int gpio1a_iomux;
+	unsigned int gpio1b_iomux;
+	unsigned int gpio1c_iomux;
+	unsigned int gpio1d_iomux;
+	unsigned int gpio2a_iomux;
+	unsigned int gpio2b_iomux;
+	unsigned int gpio2c_iomux;
+	unsigned int gpio2d_iomux;
+	unsigned int gpio3a_iomux;
+	unsigned int gpio3b_iomux;
+	unsigned int gpio3c_iomux;
+	unsigned int gpio3d_iomux;
+	unsigned int gpio2c_iomux2;
+	unsigned int grf_cif_iomux;
+	unsigned int grf_cif_iomux1;
+	unsigned int reserved1[(0x118 - 0xf0) / 4 - 1];
+	unsigned int gpio0l_pull;
+	unsigned int gpio0h_pull;
+	unsigned int gpio1l_pull;
+	unsigned int gpio1h_pull;
+	unsigned int gpio2l_pull;
+	unsigned int gpio2h_pull;
+	unsigned int gpio3l_pull;
+	unsigned int gpio3h_pull;
+	unsigned int reserved2;
+	unsigned int soc_con0;
+	unsigned int soc_con1;
+	unsigned int soc_con2;
+	unsigned int soc_status0;
+	unsigned int reserved3[6];
+	unsigned int mac_con0;
+	unsigned int mac_con1;
+	unsigned int reserved4[4];
+	unsigned int uoc0_con0;
+	unsigned int reserved5;
+	unsigned int uoc1_con1;
+	unsigned int uoc1_con2;
+	unsigned int uoc1_con3;
+	unsigned int uoc1_con4;
+	unsigned int uoc1_con5;
+	unsigned int reserved6;
+	unsigned int ddrc_stat;
+	unsigned int reserved9;
+	unsigned int soc_status1;
+	unsigned int cpu_con0;
+	unsigned int cpu_con1;
+	unsigned int cpu_con2;
+	unsigned int cpu_con3;
+	unsigned int reserved10;
+	unsigned int reserved11;
+	unsigned int cpu_status0;
+	unsigned int cpu_status1;
+	unsigned int os_reg[8];
+	unsigned int reserved12[(0x280 - 0x1e4) / 4 - 1];
+	unsigned int usbphy0_con[8];
+	unsigned int usbphy1_con[8];
+	unsigned int uoc_status0;
+	unsigned int reserved13[(0x300 - 0x2c0) / 4 - 1];
+	unsigned int chip_tag;
+	unsigned int sdmmc_det_cnt;
+};
+check_member(rk3128_grf, sdmmc_det_cnt, 0x304);
+
+struct rk3128_pmu {
+	unsigned int wakeup_cfg;
+	unsigned int pwrdn_con;
+	unsigned int pwrdn_st;
+	unsigned int idle_req;
+	unsigned int idle_st;
+	unsigned int pwrmode_con;
+	unsigned int pwr_state;
+	unsigned int osc_cnt;
+	unsigned int core_pwrdwn_cnt;
+	unsigned int core_pwrup_cnt;
+	unsigned int sft_con;
+	unsigned int ddr_sref_st;
+	unsigned int int_con;
+	unsigned int int_st;
+	unsigned int sys_reg[4];
+};
+check_member(rk3128_pmu, int_st, 0x34);
+
+/* GRF_GPIO0A_IOMUX */
+enum {
+	GPIO0A7_SHIFT		= 14,
+	GPIO0A7_MASK		= 3 << GPIO0A7_SHIFT,
+	GPIO0A7_GPIO		= 0,
+	GPIO0A7_I2C3_SDA,
+
+	GPIO0A6_SHIFT		= 12,
+	GPIO0A6_MASK		= 3 << GPIO0A6_SHIFT,
+	GPIO0A6_GPIO		= 0,
+	GPIO0A6_I2C3_SCL,
+
+	GPIO0A3_SHIFT		= 6,
+	GPIO0A3_MASK		= 3 << GPIO0A3_SHIFT,
+	GPIO0A3_GPIO		= 0,
+	GPIO0A3_I2C1_SDA,
+
+	GPIO0A2_SHIFT		= 4,
+	GPIO0A2_MASK		= 1 << GPIO0A2_SHIFT,
+	GPIO0A2_GPIO		= 0,
+	GPIO0A2_I2C1_SCL,
+
+	GPIO0A1_SHIFT		= 2,
+	GPIO0A1_MASK		= 1 << GPIO0A1_SHIFT,
+	GPIO0A1_GPIO		= 0,
+	GPIO0A1_I2C0_SDA,
+
+	GPIO0A0_SHIFT		= 0,
+	GPIO0A0_MASK		= 1 << GPIO0A0_SHIFT,
+	GPIO0A0_GPIO		= 0,
+	GPIO0A0_I2C0_SCL,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+	GPIO0B6_SHIFT		= 12,
+	GPIO0B6_MASK		= 3 << GPIO0B6_SHIFT,
+	GPIO0B6_GPIO		= 0,
+	GPIO0B6_I2S_SDI,
+	GPIO0B6_SPI_CSN0,
+
+	GPIO0B5_SHIFT		= 10,
+	GPIO0B5_MASK		= 3 << GPIO0B5_SHIFT,
+	GPIO0B5_GPIO		= 0,
+	GPIO0B5_I2S_SDO,
+	GPIO0B5_SPI_RXD,
+
+	GPIO0B4_SHIFT		= 8,
+	GPIO0B4_MASK		= 1 << GPIO0B4_SHIFT,
+	GPIO0B4_GPIO		= 0,
+	GPIO0B4_I2S_LRCKTX,
+
+	GPIO0B3_SHIFT		= 6,
+	GPIO0B3_MASK		= 3 << GPIO0B3_SHIFT,
+	GPIO0B3_GPIO		= 0,
+	GPIO0B3_I2S_LRCKRX,
+	GPIO0B3_SPI_TXD,
+
+	GPIO0B1_SHIFT		= 2,
+	GPIO0B1_MASK		= 3,
+	GPIO0B1_GPIO		= 0,
+	GPIO0B1_I2S_SCLK,
+	GPIO0B1_SPI_CLK,
+
+	GPIO0B0_SHIFT		= 0,
+	GPIO0B0_MASK		= 3,
+	GPIO0B0_GPIO		= 0,
+	GPIO0B0_I2S1_MCLK,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+	GPIO0D4_SHIFT		= 8,
+	GPIO0D4_MASK		= 1 << GPIO0D4_SHIFT,
+	GPIO0D4_GPIO		= 0,
+	GPIO0D4_PWM2,
+
+	GPIO0D3_SHIFT		= 6,
+	GPIO0D3_MASK		= 1 << GPIO0D3_SHIFT,
+	GPIO0D3_GPIO		= 0,
+	GPIO0D3_PWM1,
+
+	GPIO0D2_SHIFT		= 4,
+	GPIO0D2_MASK		= 1 << GPIO0D2_SHIFT,
+	GPIO0D2_GPIO		= 0,
+	GPIO0D2_PWM0,
+
+	GPIO0D1_SHIFT		= 2,
+	GPIO0D1_MASK		= 1 << GPIO0D1_SHIFT,
+	GPIO0D1_GPIO		= 0,
+	GPIO0D1_UART2_CTSN,
+
+	GPIO0D0_SHIFT		= 0,
+	GPIO0D0_MASK		= 3 << GPIO0D0_SHIFT,
+	GPIO0D0_GPIO		= 0,
+	GPIO0D0_UART2_RTSN,
+	GPIO0D0_PMIC_SLEEP,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+	GPIO1A5_SHIFT		= 10,
+	GPIO1A5_MASK		= 3 << GPIO1A5_SHIFT,
+	GPIO1A5_GPIO		= 0,
+	GPIO1A5_I2S_SDI,
+	GPIO1A5_SDMMC_DATA3,
+
+	GPIO1A4_SHIFT		= 8,
+	GPIO1A4_MASK		= 3 << GPIO1A4_SHIFT,
+	GPIO1A4_GPIO		= 0,
+	GPIO1A4_I2S_SD0,
+	GPIO1A4_SDMMC_DATA2,
+
+	GPIO1A3_SHIFT		= 6,
+	GPIO1A3_MASK		= 1 << GPIO1A3_SHIFT,
+	GPIO1A3_GPIO		= 0,
+	GPIO1A3_I2S_LRCKTX,
+
+	GPIO1A2_SHIFT		= 4,
+	GPIO1A2_MASK		= 3 << GPIO1A2_SHIFT,
+	GPIO1A2_GPIO		= 0,
+	GPIO1A2_I2S_LRCKRX,
+	GPIO1A2_SDMMC_DATA1,
+
+	GPIO1A1_SHIFT		= 2,
+	GPIO1A1_MASK		= 3 << GPIO1A1_SHIFT,
+	GPIO1A1_GPIO		= 0,
+	GPIO1A1_I2S_SCLK,
+	GPIO1A1_SDMMC_DATA0,
+	GPIO1A1_PMIC_SLEEP,
+
+	GPIO1A0_SHIFT		= 0,
+	GPIO1A0_MASK		= 3,
+	GPIO1A0_GPIO		= 0,
+	GPIO1A0_I2S_MCLK,
+	GPIO1A0_SDMMC_CLKOUT,
+	GPIO1A0_XIN32K,
+
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+	GPIO1B7_SHIFT		= 14,
+	GPIO1B7_MASK		= 1 << GPIO1B7_SHIFT,
+	GPIO1B7_GPIO		= 0,
+	GPIO1B7_MMC0_CMD,
+
+	GPIO1B6_SHIFT		= 12,
+	GPIO1B6_MASK		= 1 << GPIO1B6_SHIFT,
+	GPIO1B6_GPIO		= 0,
+	GPIO1B6_MMC_PWREN,
+
+	GPIO1B2_SHIFT		= 4,
+	GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
+	GPIO1B2_GPIO		= 0,
+	GPIO1B2_SPI_RXD,
+	GPIO1B2_UART1_SIN,
+
+	GPIO1B1_SHIFT		= 2,
+	GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
+	GPIO1B1_GPIO		= 0,
+	GPIO1B1_SPI_TXD,
+	GPIO1B1_UART1_SOUT,
+
+	GPIO1B0_SHIFT		= 0,
+	GPIO1B0_MASK		= 3 << GPIO1B0_SHIFT,
+	GPIO1B0_GPIO		= 0,
+	GPIO1B0_SPI_CLK,
+	GPIO1B0_UART1_CTSN
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+	GPIO1C6_SHIFT		= 12,
+	GPIO1C6_MASK		= 3 << GPIO1C6_SHIFT,
+	GPIO1C6_GPIO		= 0,
+	GPIO1C6_NAND_CS2,
+	GPIO1C6_EMMC_CMD,
+
+	GPIO1C5_SHIFT		= 10,
+	GPIO1C5_MASK		= 3 << GPIO1C5_SHIFT,
+	GPIO1C5_GPIO		= 0,
+	GPIO1C5_MMC0_D3,
+	GPIO1C5_JTAG_TMS,
+
+	GPIO1C4_SHIFT		= 8,
+	GPIO1C4_MASK		= 3 << GPIO1C4_SHIFT,
+	GPIO1C4_GPIO		= 0,
+	GPIO1C4_MMC0_D2,
+	GPIO1C4_JTAG_TCK,
+
+	GPIO1C3_SHIFT		= 6,
+	GPIO1C3_MASK		= 3 << GPIO1C3_SHIFT,
+	GPIO1C3_GPIO		= 0,
+	GPIO1C3_MMC0_D1,
+	GPIO1C3_UART2_RX,
+
+	GPIO1C2_SHIFT		= 4,
+	GPIO1C2_MASK		= 3 << GPIO1C2_SHIFT,
+	GPIO1C2_GPIO		= 0,
+	GPIO1C2_MMC0_D0,
+	GPIO1C2_UART2_TX,
+
+	GPIO1C1_SHIFT		= 2,
+	GPIO1C1_MASK		= 1 << GPIO1C1_SHIFT,
+	GPIO1C1_GPIO		= 0,
+	GPIO1C1_MMC0_DETN,
+
+	GPIO1C0_SHIFT		= 0,
+	GPIO1C0_MASK		= 1 << GPIO1C0_SHIFT,
+	GPIO1C0_GPIO		= 0,
+	GPIO1C0_MMC0_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+	GPIO1D7_SHIFT		= 14,
+	GPIO1D7_MASK		= 3 << GPIO1D7_SHIFT,
+	GPIO1D7_GPIO		= 0,
+	GPIO1D7_NAND_D7,
+	GPIO1D7_EMMC_D7,
+	GPIO1D7_SPI_CSN1,
+
+	GPIO1D6_SHIFT		= 12,
+	GPIO1D6_MASK		= 3 << GPIO1D6_SHIFT,
+	GPIO1D6_GPIO		= 0,
+	GPIO1D6_NAND_D6,
+	GPIO1D6_EMMC_D6,
+	GPIO1D6_SPI_CSN0,
+
+	GPIO1D5_SHIFT		= 10,
+	GPIO1D5_MASK		= 3 << GPIO1D5_SHIFT,
+	GPIO1D5_GPIO		= 0,
+	GPIO1D5_NAND_D5,
+	GPIO1D5_EMMC_D5,
+	GPIO1D5_SPI_TXD1,
+
+	GPIO1D4_SHIFT		= 8,
+	GPIO1D4_MASK		= 3 << GPIO1D4_SHIFT,
+	GPIO1D4_GPIO		= 0,
+	GPIO1D4_NAND_D4,
+	GPIO1D4_EMMC_D4,
+	GPIO1D4_SPI_RXD1,
+
+	GPIO1D3_SHIFT		= 6,
+	GPIO1D3_MASK		= 3 << GPIO1D3_SHIFT,
+	GPIO1D3_GPIO		= 0,
+	GPIO1D3_NAND_D3,
+	GPIO1D3_EMMC_D3,
+	GPIO1D3_SFC_SIO3,
+
+	GPIO1D2_SHIFT		= 4,
+	GPIO1D2_MASK		= 3 << GPIO1D2_SHIFT,
+	GPIO1D2_GPIO		= 0,
+	GPIO1D2_NAND_D2,
+	GPIO1D2_EMMC_D2,
+	GPIO1D2_SFC_SIO2,
+
+	GPIO1D1_SHIFT		= 2,
+	GPIO1D1_MASK		= 3 << GPIO1D1_SHIFT,
+	GPIO1D1_GPIO		= 0,
+	GPIO1D1_NAND_D1,
+	GPIO1D1_EMMC_D1,
+	GPIO1D1_SFC_SIO1,
+
+	GPIO1D0_SHIFT		= 0,
+	GPIO1D0_MASK		= 3 << GPIO1D0_SHIFT,
+	GPIO1D0_GPIO		= 0,
+	GPIO1D0_NAND_D0,
+	GPIO1D0_EMMC_D0,
+	GPIO1D0_SFC_SIO0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+	GPIO2A7_SHIFT		= 14,
+	GPIO2A7_MASK		= 3 << GPIO2A7_SHIFT,
+	GPIO2A7_GPIO		= 0,
+	GPIO2A7_NAND_DQS,
+	GPIO2A7_EMMC_CLKOUT,
+
+	GPIO2A6_SHIFT		= 12,
+	GPIO2A6_MASK		= 1 << GPIO2A6_SHIFT,
+	GPIO2A6_GPIO		= 0,
+	GPIO2A6_NAND_CS0,
+
+	GPIO2A5_SHIFT		= 10,
+	GPIO2A5_MASK		= 3 << GPIO2A5_SHIFT,
+	GPIO2A5_GPIO		= 0,
+	GPIO2A5_NAND_WP,
+	GPIO2A5_EMMC_PWREN,
+
+	GPIO2A4_SHIFT		= 8,
+	GPIO2A4_MASK		= 3 << GPIO2A4_SHIFT,
+	GPIO2A4_GPIO		= 0,
+	GPIO2A4_NAND_RDY,
+	GPIO2A4_EMMC_CMD,
+	GPIO2A3_SFC_CLK,
+
+	GPIO2A3_SHIFT		= 6,
+	GPIO2A3_MASK		= 3 << GPIO2A3_SHIFT,
+	GPIO2A3_GPIO		= 0,
+	GPIO2A3_NAND_RDN,
+	GPIO2A4_SFC_CSN1,
+
+	GPIO2A2_SHIFT		= 4,
+	GPIO2A2_MASK		= 3 << GPIO2A2_SHIFT,
+	GPIO2A2_GPIO		= 0,
+	GPIO2A2_NAND_WRN,
+	GPIO2A4_SFC_CSN0,
+
+	GPIO2A1_SHIFT		= 2,
+	GPIO2A1_MASK		= 3 << GPIO2A1_SHIFT,
+	GPIO2A1_GPIO		= 0,
+	GPIO2A1_NAND_CLE,
+	GPIO2A1_EMMC_CLKOUT,
+
+	GPIO2A0_SHIFT		= 0,
+	GPIO2A0_MASK		= 3 << GPIO2A0_SHIFT,
+	GPIO2A0_GPIO		= 0,
+	GPIO2A0_NAND_ALE,
+	GPIO2A0_SPI_CLK,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+	GPIO2B7_SHIFT		= 14,
+	GPIO2B7_MASK		= 3 << GPIO2B7_SHIFT,
+	GPIO2B7_GPIO		= 0,
+	GPIO2B7_LCDC0_D13,
+	GPIO2B7_EBC_SDCE5,
+	GPIO2B7_GMAC_RXER,
+
+	GPIO2B6_SHIFT		= 12,
+	GPIO2B6_MASK		= 3 << GPIO2B6_SHIFT,
+	GPIO2B6_GPIO		= 0,
+	GPIO2B6_LCDC0_D12,
+	GPIO2B6_EBC_SDCE4,
+	GPIO2B6_GMAC_CLK,
+
+	GPIO2B5_SHIFT		= 10,
+	GPIO2B5_MASK		= 3 << GPIO2B5_SHIFT,
+	GPIO2B5_GPIO		= 0,
+	GPIO2B5_LCDC0_D11,
+	GPIO2B5_EBC_SDCE3,
+	GPIO2B5_GMAC_TXEN,
+
+	GPIO2B4_SHIFT		= 8,
+	GPIO2B4_MASK		= 3 << GPIO2B4_SHIFT,
+	GPIO2B4_GPIO		= 0,
+	GPIO2B4_LCDC0_D10,
+	GPIO2B4_EBC_SDCE2,
+	GPIO2B4_GMAC_MDIO,
+
+	GPIO2B3_SHIFT		= 6,
+	GPIO2B3_MASK		= 3 << GPIO2B3_SHIFT,
+	GPIO2B3_GPIO		= 0,
+	GPIO2B3_LCDC0_DEN,
+	GPIO2B3_EBC_GDCLK,
+	GPIO2B3_GMAC_RXCLK,
+
+	GPIO2B2_SHIFT		= 4,
+	GPIO2B2_MASK		= 3 << GPIO2B2_SHIFT,
+	GPIO2B2_GPIO		= 0,
+	GPIO2B2_LCDC0_VSYNC,
+	GPIO2B2_EBC_SDOE,
+	GPIO2B2_GMAC_CRS,
+
+	GPIO2B1_SHIFT		= 2,
+	GPIO2B1_MASK		= 3 << GPIO2B1_SHIFT,
+	GPIO2B1_GPIO		= 0,
+	GPIO2B1_LCDC0_HSYNC,
+	GPIO2B1_EBC_SDLE,
+	GPIO2B1_GMAC_TXCLK,
+
+	GPIO2B0_SHIFT		= 0,
+	GPIO2B0_MASK		= 3 << GPIO2B0_SHIFT,
+	GPIO2B0_GPIO		= 0,
+	GPIO2B0_LCDC0_DCLK,
+	GPIO2B0_EBC_SDCLK,
+	GPIO2B0_GMAC_RXDV,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+	GPIO2C3_SHIFT		= 6,
+	GPIO2C3_MASK		= 3 << GPIO2C3_SHIFT,
+	GPIO2C3_GPIO		= 0,
+	GPIO2C3_LCDC0_D17,
+	GPIO2C3_EBC_GDPWR0,
+	GPIO2C3_GMAC_TXD0,
+
+	GPIO2C2_SHIFT		= 4,
+	GPIO2C2_MASK		= 3 << GPIO2C2_SHIFT,
+	GPIO2C2_GPIO		= 0,
+	GPIO2C2_LCDC0_D16,
+	GPIO2C2_EBC_GDSP,
+	GPIO2C2_GMAC_TXD1,
+
+	GPIO2C1_SHIFT		= 2,
+	GPIO2C1_MASK		= 3 << GPIO2C1_SHIFT,
+	GPIO2C1_GPIO		= 0,
+	GPIO2C1_LCDC0_D15,
+	GPIO2C1_EBC_GDOE,
+	GPIO2C1_GMAC_RXD0,
+
+	GPIO2C0_SHIFT		= 0,
+	GPIO2C0_MASK		= 3 << GPIO2C0_SHIFT,
+	GPIO2C0_GPIO		= 0,
+	GPIO2C0_LCDC0_D14,
+	GPIO2C0_EBC_VCOM,
+	GPIO2C0_GMAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+	GPIO2D6_SHIFT		= 12,
+	GPIO2D6_MASK		= 3 << GPIO2D6_SHIFT,
+	GPIO2D6_GPIO		= 0,
+	GPIO2D6_LCDC0_D22,
+	GPIO2D6_GMAC_COL	= 4,
+
+	GPIO2D1_SHIFT		= 2,
+	GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
+	GPIO2D1_GPIO		= 0,
+	GPIO2D1_GMAC_MDC	= 3,
+};
+
+/* GRF_GPIO2C_IOMUX2 */
+enum {
+	GPIO2C7_SHIFT		= 12,
+	GPIO2C7_MASK		= 7 << GPIO2C7_SHIFT,
+	GPIO2C7_GPIO		= 0,
+	GPIO2C7_GMAC_TXD3	= 4,
+
+	GPIO2C6_SHIFT		= 12,
+	GPIO2C6_MASK		= 7 << GPIO2C6_SHIFT,
+	GPIO2C6_GPIO		= 0,
+	GPIO2C6_GMAC_TXD2	= 4,
+
+	GPIO2C5_SHIFT		= 4,
+	GPIO2C5_MASK		= 7 << GPIO2C5_SHIFT,
+	GPIO2C5_GPIO		= 0,
+	GPIO2C5_I2C2_SCL	= 3,
+	GPIO2C5_GMAC_RXD2,
+
+	GPIO2C4_SHIFT		= 0,
+	GPIO2C4_MASK		= 7 << GPIO2C4_SHIFT,
+	GPIO2C4_GPIO		= 0,
+	GPIO2C4_I2C2_SDA	= 3,
+	GPIO2C4_GMAC_RXD2,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3188.h b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
new file mode 100644
index 0000000..d051976
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3188.h
@@ -0,0 +1,250 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3188_H
+#define _ASM_ARCH_GRF_RK3188_H
+
+struct rk3188_grf_gpio_lh {
+	u32 l;
+	u32 h;
+};
+
+struct rk3188_grf {
+	struct rk3188_grf_gpio_lh gpio_dir[4];
+	struct rk3188_grf_gpio_lh gpio_do[4];
+	struct rk3188_grf_gpio_lh gpio_en[4];
+
+	u32 reserved[2];
+	u32 gpio0c_iomux;
+	u32 gpio0d_iomux;
+
+	u32 gpio1a_iomux;
+	u32 gpio1b_iomux;
+	u32 gpio1c_iomux;
+	u32 gpio1d_iomux;
+
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+	u32 gpio2c_iomux;
+	u32 gpio2d_iomux;
+
+	u32 gpio3a_iomux;
+	u32 gpio3b_iomux;
+	u32 gpio3c_iomux;
+	u32 gpio3d_iomux;
+
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_status0;
+
+	u32 busdmac_con[3];
+	u32 peridmac_con[4];
+
+	u32 cpu_con[6];
+	u32 reserved0[2];
+
+	u32 ddrc_con0;
+	u32 ddrc_stat;
+
+	u32 io_con[5];
+	u32 soc_status1;
+
+	u32 uoc0_con[4];
+	u32 uoc1_con[4];
+	u32 uoc2_con[2];
+	u32 reserved1;
+	u32 uoc3_con[2];
+	u32 hsic_stat;
+	u32 os_reg[8];
+
+	u32 gpio0_p[3];
+	u32 gpio1_p[3][4];
+
+	u32 flash_data_p;
+	u32 flash_cmd_p;
+};
+check_member(rk3188_grf, flash_cmd_p, 0x01a4);
+
+/* GRF_SOC_CON0 */
+enum {
+	HSADC_CLK_DIR_SHIFT	= 15,
+	HSADC_CLK_DIR_MASK	= 1,
+
+	HSADC_SEL_SHIFT		= 14,
+	HSADC_SEL_MASK		= 1,
+
+	NOC_REMAP_SHIFT		= 12,
+	NOC_REMAP_MASK		= 1,
+
+	EMMC_FLASH_SEL_SHIFT	= 11,
+	EMMC_FLASH_SEL_MASK	= 1,
+
+	TZPC_REVISION_SHIFT	= 7,
+	TZPC_REVISION_MASK	= 0xf,
+
+	L2CACHE_ACC_SHIFT	= 5,
+	L2CACHE_ACC_MASK	= 3,
+
+	L2RD_WAIT_SHIFT		= 3,
+	L2RD_WAIT_MASK		= 3,
+
+	IMEMRD_WAIT_SHIFT	= 1,
+	IMEMRD_WAIT_MASK	= 3,
+};
+
+/* GRF_SOC_CON1 */
+enum {
+	RKI2C4_SEL_SHIFT	= 15,
+	RKI2C4_SEL_MASK		= 1,
+
+	RKI2C3_SEL_SHIFT	= 14,
+	RKI2C3_SEL_MASK		= 1,
+
+	RKI2C2_SEL_SHIFT	= 13,
+	RKI2C2_SEL_MASK		= 1,
+
+	RKI2C1_SEL_SHIFT	= 12,
+	RKI2C1_SEL_MASK		= 1,
+
+	RKI2C0_SEL_SHIFT	= 11,
+	RKI2C0_SEL_MASK		= 1,
+
+	VCODEC_SEL_SHIFT	= 10,
+	VCODEC_SEL_MASK		= 1,
+
+	PERI_EMEM_PAUSE_SHIFT	= 9,
+	PERI_EMEM_PAUSE_MASK	= 1,
+
+	PERI_USB_PAUSE_SHIFT	= 8,
+	PERI_USB_PAUSE_MASK	= 1,
+
+	SMC_MUX_MODE_0_SHIFT	= 6,
+	SMC_MUX_MODE_0_MASK	= 1,
+
+	SMC_SRAM_MW_0_SHIFT	= 4,
+	SMC_SRAM_MW_0_MASK	= 3,
+
+	SMC_REMAP_0_SHIFT	= 3,
+	SMC_REMAP_0_MASK	= 1,
+
+	SMC_A_GT_M0_SYNC_SHIFT	= 2,
+	SMC_A_GT_M0_SYNC_MASK	= 1,
+
+	EMAC_SPEED_SHIFT	= 1,
+	EMAC_SPEEC_MASK		= 1,
+
+	EMAC_MODE_SHIFT		= 0,
+	EMAC_MODE_MASK		= 1,
+};
+
+/* GRF_SOC_CON2 */
+enum {
+	SDIO_CLK_OUT_SR_SHIFT	= 15,
+	SDIO_CLK_OUT_SR_MASK	= 1,
+
+	MEM_EMA_L2C_SHIFT	= 11,
+	MEM_EMA_L2C_MASK	= 7,
+
+	MEM_EMA_A9_SHIFT	= 8,
+	MEM_EMA_A9_MASK		= 7,
+
+	MSCH4_MAINDDR3_SHIFT	= 7,
+	MSCH4_MAINDDR3_MASK	= 1,
+	MSCH4_MAINDDR3_DDR3	= 1,
+
+	EMAC_NEWRCV_EN_SHIFT	= 6,
+	EMAC_NEWRCV_EN_MASK	= 1,
+
+	SW_ADDR15_EN_SHIFT	= 5,
+	SW_ADDR15_EN_MASK	= 1,
+
+	SW_ADDR16_EN_SHIFT	= 4,
+	SW_ADDR16_EN_MASK	= 1,
+
+	SW_ADDR17_EN_SHIFT	= 3,
+	SW_ADDR17_EN_MASK	= 1,
+
+	BANK2_TO_RANK_EN_SHIFT	= 2,
+	BANK2_TO_RANK_EN_MASK	= 1,
+
+	RANK_TO_ROW15_EN_SHIFT	= 1,
+	RANK_TO_ROW15_EN_MASK	= 1,
+
+	UPCTL_C_ACTIVE_IN_SHIFT = 0,
+	UPCTL_C_ACTIVE_IN_MASK	= 1,
+	UPCTL_C_ACTIVE_IN_MAY	= 0,
+	UPCTL_C_ACTIVE_IN_WILL,
+};
+
+/* GRF_DDRC_CON0 */
+enum {
+	DDR_16BIT_EN_SHIFT	= 15,
+	DDR_16BIT_EN_MASK	= 1,
+
+	DTO_LB_SHIFT		= 11,
+	DTO_LB_MASK		= 3,
+
+	DTO_TE_SHIFT		= 9,
+	DTO_TE_MASK		= 3,
+
+	DTO_PDR_SHIFT		= 7,
+	DTO_PDR_MASK		= 3,
+
+	DTO_PDD_SHIFT		= 5,
+	DTO_PDD_MASK		= 3,
+
+	DTO_IOM_SHIFT		= 3,
+	DTO_IOM_MASK		= 3,
+
+	DTO_OE_SHIFT		= 1,
+	DTO_OE_MASK		= 3,
+
+	ATO_AE_SHIFT		= 0,
+	ATO_AE_MASK		= 1,
+};
+
+/* GRF_UOC_CON0 */
+enum {
+	SIDDQ_SHIFT		= 13,
+	SIDDQ_MASK		= 1 << SIDDQ_SHIFT,
+
+	BYPASSSEL_SHIFT		= 9,
+	BYPASSSEL_MASK		= 1 << BYPASSSEL_SHIFT,
+
+	BYPASSDMEN_SHIFT	= 8,
+	BYPASSDMEN_MASK		= 1 << BYPASSDMEN_SHIFT,
+
+	UOC_DISABLE_SHIFT	= 4,
+	UOC_DISABLE_MASK	= 1 << UOC_DISABLE_SHIFT,
+
+	COMMON_ON_N_SHIFT	= 0,
+	COMMON_ON_N_MASK	= 1 << COMMON_ON_N_SHIFT,
+};
+
+/* GRF_UOC_CON2 */
+enum {
+	SOFT_CON_SEL_SHIFT	= 2,
+	SOFT_CON_SEL_MASK	= 1 << SOFT_CON_SEL_SHIFT,
+};
+
+/* GRF_UOC0_CON3 */
+enum {
+	TERMSEL_FULLSPEED_SHIFT	= 5,
+	TERMSEL_FULLSPEED_MASK	= 1 << TERMSEL_FULLSPEED_SHIFT,
+
+	XCVRSELECT_SHIFT	= 3,
+	XCVRSELECT_FSTRANSC	= 1,
+	XCVRSELECT_MASK		= 3 << XCVRSELECT_SHIFT,
+
+	OPMODE_SHIFT		= 1,
+	OPMODE_NODRIVING	= 1,
+	OPMODE_MASK		= 3 << OPMODE_SHIFT,
+
+	SUSPENDN_SHIFT		= 0,
+	SUSPENDN_MASK		= 1 << SUSPENDN_SHIFT,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
new file mode 100644
index 0000000..a99d137
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_GRF_RK322X_H
+#define _ASM_ARCH_GRF_RK322X_H
+
+#include <common.h>
+
+struct rk322x_grf {
+	unsigned int gpio0a_iomux;
+	unsigned int gpio0b_iomux;
+	unsigned int gpio0c_iomux;
+	unsigned int gpio0d_iomux;
+
+	unsigned int gpio1a_iomux;
+	unsigned int gpio1b_iomux;
+	unsigned int gpio1c_iomux;
+	unsigned int gpio1d_iomux;
+
+	unsigned int gpio2a_iomux;
+	unsigned int gpio2b_iomux;
+	unsigned int gpio2c_iomux;
+	unsigned int gpio2d_iomux;
+
+	unsigned int gpio3a_iomux;
+	unsigned int gpio3b_iomux;
+	unsigned int gpio3c_iomux;
+	unsigned int gpio3d_iomux;
+
+	unsigned int reserved1[4];
+	unsigned int con_iomux;
+	unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
+	unsigned int gpio0_p[4];
+	unsigned int gpio1_p[4];
+	unsigned int gpio2_p[4];
+	unsigned int gpio3_p[4];
+	unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
+	unsigned int gpio0_e[4];
+	unsigned int gpio1_e[4];
+	unsigned int gpio2_e[4];
+	unsigned int gpio3_e[4];
+	unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
+	unsigned int soc_con[7];
+	unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
+	unsigned int soc_status[3];
+	unsigned int chip_id;
+	unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
+	unsigned int cpu_con[4];
+	unsigned int reserved7[4];
+	unsigned int cpu_status[2];
+	unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
+	unsigned int os_reg[8];
+	unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
+	unsigned int ddrc_stat;
+	unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
+	unsigned int sig_detect_con[2];
+	unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
+	unsigned int sig_detect_status[2];
+	unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
+	unsigned int sig_detect_clr[2];
+	unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1];
+	unsigned int emmc_det;
+	unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1];
+	unsigned int host0_con[3];
+	unsigned int reserved15;
+	unsigned int host1_con[3];
+	unsigned int reserved16;
+	unsigned int host2_con[3];
+	unsigned int reserved17[(0x760 - 0x728) / 4 - 1];
+	unsigned int usbphy0_con[27];
+	unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1];
+	unsigned int usbphy1_con[27];
+	unsigned int reserved19[(0x880 - 0x868) / 4 - 1];
+	unsigned int otg_con0;
+	unsigned int uoc_status0;
+	unsigned int reserved20[(0x900 - 0x884) / 4 - 1];
+	unsigned int mac_con[2];
+	unsigned int reserved21[(0xb00 - 0x904) / 4 - 1];
+	unsigned int macphy_con[4];
+	unsigned int macphy_status;
+};
+check_member(rk322x_grf, ddrc_stat, 0x604);
+
+struct rk322x_sgrf {
+	unsigned int soc_con[11];
+	unsigned int busdmac_con[4];
+};
+
+/* GRF_MACPHY_CON0 */
+enum {
+	MACPHY_CFG_ENABLE_SHIFT = 0,
+	MACPHY_CFG_ENABLE_MASK  = 1 << MACPHY_CFG_ENABLE_SHIFT,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
new file mode 100644
index 0000000..894d3a4
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -0,0 +1,1155 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3288_H
+#define _ASM_ARCH_GRF_RK3288_H
+
+struct rk3288_grf_gpio_lh {
+	u32 l;
+	u32 h;
+};
+
+struct rk3288_grf {
+	u32 reserved[3];
+	u32 gpio1d_iomux;
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+
+	u32 gpio2c_iomux;
+	u32 reserved2;
+	u32 gpio3a_iomux;
+	u32 gpio3b_iomux;
+
+	u32 gpio3c_iomux;
+	u32 gpio3dl_iomux;
+	u32 gpio3dh_iomux;
+	u32 gpio4al_iomux;
+
+	u32 gpio4ah_iomux;
+	u32 gpio4bl_iomux;
+	u32 reserved3;
+	u32 gpio4c_iomux;
+
+	u32 gpio4d_iomux;
+	u32 reserved4;
+	u32 gpio5b_iomux;
+	u32 gpio5c_iomux;
+
+	u32 reserved5;
+	u32 gpio6a_iomux;
+	u32 gpio6b_iomux;
+	u32 gpio6c_iomux;
+	u32 reserved6;
+	u32 gpio7a_iomux;
+	u32 gpio7b_iomux;
+	u32 gpio7cl_iomux;
+	u32 gpio7ch_iomux;
+	u32 reserved7;
+	u32 gpio8a_iomux;
+	u32 gpio8b_iomux;
+	u32 reserved8[30];
+	struct rk3288_grf_gpio_lh gpio_sr[8];
+	u32 gpio1_p[8][4];
+	u32 gpio1_e[8][4];
+	u32 gpio_smt;
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
+	u32 soc_status[22];
+	u32 reserved9[2];
+	u32 peridmac_con[4];
+	u32 ddrc0_con0;
+	u32 ddrc1_con0;
+	u32 cpu_con[5];
+	u32 reserved10[3];
+	u32 cpu_status0;
+	u32 reserved11;
+	u32 uoc0_con[5];
+	u32 uoc1_con[5];
+	u32 uoc2_con[4];
+	u32 uoc3_con[2];
+	u32 uoc4_con[2];
+	u32 pvtm_con[3];
+	u32 pvtm_status[3];
+	u32 io_vsel;
+	u32 saradc_testbit;
+	u32 tsadc_testbit_l;
+	u32 tsadc_testbit_h;
+	u32 os_reg[4];
+	u32 reserved12;
+	u32 soc_con15;
+	u32 soc_con16;
+};
+
+struct rk3288_sgrf {
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 reserved1[(0x20-0x18)/4];
+	u32 busdmac_con[2];
+	u32 reserved2[(0x40-0x28)/4];
+	u32 cpu_con[3];
+	u32 reserved3[(0x50-0x4c)/4];
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
+	u32 soc_con15;
+	u32 soc_con16;
+	u32 soc_con17;
+	u32 soc_con18;
+	u32 soc_con19;
+	u32 soc_con20;
+	u32 soc_con21;
+	u32 reserved4[(0x100-0x90)/4];
+	u32 soc_status[2];
+	u32 reserved5[(0x120-0x108)/4];
+	u32 fast_boot_addr;
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+	GPIO1D3_SHIFT		= 6,
+	GPIO1D3_MASK		= 1,
+	GPIO1D3_GPIO		= 0,
+	GPIO1D3_LCDC0_DCLK,
+
+	GPIO1D2_SHIFT		= 4,
+	GPIO1D2_MASK		= 1,
+	GPIO1D2_GPIO		= 0,
+	GPIO1D2_LCDC0_DEN,
+
+	GPIO1D1_SHIFT		= 2,
+	GPIO1D1_MASK		= 1,
+	GPIO1D1_GPIO		= 0,
+	GPIO1D1_LCDC0_VSYNC,
+
+	GPIO1D0_SHIFT		= 0,
+	GPIO1D0_MASK		= 1,
+	GPIO1D0_GPIO		= 0,
+	GPIO1D0_LCDC0_HSYNC,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+	GPIO2C1_SHIFT		= 2,
+	GPIO2C1_MASK		= 1,
+	GPIO2C1_GPIO		= 0,
+	GPIO2C1_I2C3CAM_SDA,
+
+	GPIO2C0_SHIFT		= 0,
+	GPIO2C0_MASK		= 1,
+	GPIO2C0_GPIO		= 0,
+	GPIO2C0_I2C3CAM_SCL,
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+	GPIO3A7_SHIFT		= 14,
+	GPIO3A7_MASK		= 3,
+	GPIO3A7_GPIO		= 0,
+	GPIO3A7_FLASH0_DATA7,
+	GPIO3A7_EMMC_DATA7,
+
+	GPIO3A6_SHIFT		= 12,
+	GPIO3A6_MASK		= 3,
+	GPIO3A6_GPIO		= 0,
+	GPIO3A6_FLASH0_DATA6,
+	GPIO3A6_EMMC_DATA6,
+
+	GPIO3A5_SHIFT		= 10,
+	GPIO3A5_MASK		= 3,
+	GPIO3A5_GPIO		= 0,
+	GPIO3A5_FLASH0_DATA5,
+	GPIO3A5_EMMC_DATA5,
+
+	GPIO3A4_SHIFT		= 8,
+	GPIO3A4_MASK		= 3,
+	GPIO3A4_GPIO		= 0,
+	GPIO3A4_FLASH0_DATA4,
+	GPIO3A4_EMMC_DATA4,
+
+	GPIO3A3_SHIFT		= 6,
+	GPIO3A3_MASK		= 3,
+	GPIO3A3_GPIO		= 0,
+	GPIO3A3_FLASH0_DATA3,
+	GPIO3A3_EMMC_DATA3,
+
+	GPIO3A2_SHIFT		= 4,
+	GPIO3A2_MASK		= 3,
+	GPIO3A2_GPIO		= 0,
+	GPIO3A2_FLASH0_DATA2,
+	GPIO3A2_EMMC_DATA2,
+
+	GPIO3A1_SHIFT		= 2,
+	GPIO3A1_MASK		= 3,
+	GPIO3A1_GPIO		= 0,
+	GPIO3A1_FLASH0_DATA1,
+	GPIO3A1_EMMC_DATA1,
+
+	GPIO3A0_SHIFT		= 0,
+	GPIO3A0_MASK		= 3,
+	GPIO3A0_GPIO		= 0,
+	GPIO3A0_FLASH0_DATA0,
+	GPIO3A0_EMMC_DATA0,
+};
+
+/* GRF_GPIO3B_IOMUX */
+enum {
+	GPIO3B7_SHIFT		= 14,
+	GPIO3B7_MASK		= 1,
+	GPIO3B7_GPIO		= 0,
+	GPIO3B7_FLASH0_CSN1,
+
+	GPIO3B6_SHIFT		= 12,
+	GPIO3B6_MASK		= 1,
+	GPIO3B6_GPIO		= 0,
+	GPIO3B6_FLASH0_CSN0,
+
+	GPIO3B5_SHIFT		= 10,
+	GPIO3B5_MASK		= 1,
+	GPIO3B5_GPIO		= 0,
+	GPIO3B5_FLASH0_WRN,
+
+	GPIO3B4_SHIFT		= 8,
+	GPIO3B4_MASK		= 1,
+	GPIO3B4_GPIO		= 0,
+	GPIO3B4_FLASH0_CLE,
+
+	GPIO3B3_SHIFT		= 6,
+	GPIO3B3_MASK		= 1,
+	GPIO3B3_GPIO		= 0,
+	GPIO3B3_FLASH0_ALE,
+
+	GPIO3B2_SHIFT		= 4,
+	GPIO3B2_MASK		= 1,
+	GPIO3B2_GPIO		= 0,
+	GPIO3B2_FLASH0_RDN,
+
+	GPIO3B1_SHIFT		= 2,
+	GPIO3B1_MASK		= 3,
+	GPIO3B1_GPIO		= 0,
+	GPIO3B1_FLASH0_WP,
+	GPIO3B1_EMMC_PWREN,
+
+	GPIO3B0_SHIFT		= 0,
+	GPIO3B0_MASK		= 1,
+	GPIO3B0_GPIO		= 0,
+	GPIO3B0_FLASH0_RDY,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+	GPIO3C2_SHIFT		= 4,
+	GPIO3C2_MASK		= 3,
+	GPIO3C2_GPIO		= 0,
+	GPIO3C2_FLASH0_DQS,
+	GPIO3C2_EMMC_CLKOUT,
+
+	GPIO3C1_SHIFT		= 2,
+	GPIO3C1_MASK		= 3,
+	GPIO3C1_GPIO		= 0,
+	GPIO3C1_FLASH0_CSN3,
+	GPIO3C1_EMMC_RSTNOUT,
+
+	GPIO3C0_SHIFT		= 0,
+	GPIO3C0_MASK		= 3,
+	GPIO3C0_GPIO		= 0,
+	GPIO3C0_FLASH0_CSN2,
+	GPIO3C0_EMMC_CMD,
+};
+
+/* GRF_GPIO3DL_IOMUX */
+enum {
+	GPIO3D3_SHIFT		= 12,
+	GPIO3D3_MASK		= 7,
+	GPIO3D3_GPIO		= 0,
+	GPIO3D3_FLASH1_DATA3,
+	GPIO3D3_HOST_DOUT3,
+	GPIO3D3_MAC_RXD3,
+	GPIO3D3_SDIO1_DATA3,
+
+	GPIO3D2_SHIFT		= 8,
+	GPIO3D2_MASK		= 7,
+	GPIO3D2_GPIO		= 0,
+	GPIO3D2_FLASH1_DATA2,
+	GPIO3D2_HOST_DOUT2,
+	GPIO3D2_MAC_RXD2,
+	GPIO3D2_SDIO1_DATA2,
+
+	GPIO3D1_SHIFT		= 4,
+	GPIO3D1_MASK		= 7,
+	GPIO3D1_GPIO		= 0,
+	GPIO3DL1_FLASH1_DATA1,
+	GPIO3D1_HOST_DOUT1,
+	GPIO3D1_MAC_TXD3,
+	GPIO3D1_SDIO1_DATA1,
+
+	GPIO3D0_SHIFT		= 0,
+	GPIO3D0_MASK		= 7,
+	GPIO3D0_GPIO		= 0,
+	GPIO3D0_FLASH1_DATA0,
+	GPIO3D0_HOST_DOUT0,
+	GPIO3D0_MAC_TXD2,
+	GPIO3D0_SDIO1_DATA0,
+};
+
+/* GRF_GPIO3HL_IOMUX */
+enum {
+	GPIO3D7_SHIFT		= 12,
+	GPIO3D7_MASK		= 7,
+	GPIO3D7_GPIO		= 0,
+	GPIO3D7_FLASH1_DATA7,
+	GPIO3D7_HOST_DOUT7,
+	GPIO3D7_MAC_RXD1,
+	GPIO3D7_SDIO1_INTN,
+
+	GPIO3D6_SHIFT		= 8,
+	GPIO3D6_MASK		= 7,
+	GPIO3D6_GPIO		= 0,
+	GPIO3D6_FLASH1_DATA6,
+	GPIO3D6_HOST_DOUT6,
+	GPIO3D6_MAC_RXD0,
+	GPIO3D6_SDIO1_BKPWR,
+
+	GPIO3D5_SHIFT		= 4,
+	GPIO3D5_MASK		= 7,
+	GPIO3D5_GPIO		= 0,
+	GPIO3D5_FLASH1_DATA5,
+	GPIO3D5_HOST_DOUT5,
+	GPIO3D5_MAC_TXD1,
+	GPIO3D5_SDIO1_WRPRT,
+
+	GPIO3D4_SHIFT		= 0,
+	GPIO3D4_MASK		= 7,
+	GPIO3D4_GPIO		= 0,
+	GPIO3D4_FLASH1_DATA4,
+	GPIO3D4_HOST_DOUT4,
+	GPIO3D4_MAC_TXD0,
+	GPIO3D4_SDIO1_DETECTN,
+};
+
+/* GRF_GPIO4AL_IOMUX */
+enum {
+	GPIO4A3_SHIFT		= 12,
+	GPIO4A3_MASK		= 7,
+	GPIO4A3_GPIO		= 0,
+	GPIO4A3_FLASH1_ALE,
+	GPIO4A3_HOST_DOUT9,
+	GPIO4A3_MAC_CLK,
+	GPIO4A3_FLASH0_CSN6,
+
+	GPIO4A2_SHIFT		= 8,
+	GPIO4A2_MASK		= 7,
+	GPIO4A2_GPIO		= 0,
+	GPIO4A2_FLASH1_RDN,
+	GPIO4A2_HOST_DOUT8,
+	GPIO4A2_MAC_RXER,
+	GPIO4A2_FLASH0_CSN5,
+
+	GPIO4A1_SHIFT		= 4,
+	GPIO4A1_MASK		= 7,
+	GPIO4A1_GPIO		= 0,
+	GPIO4A1_FLASH1_WP,
+	GPIO4A1_HOST_CKOUTN,
+	GPIO4A1_MAC_TXDV,
+	GPIO4A1_FLASH0_CSN4,
+
+	GPIO4A0_SHIFT		= 0,
+	GPIO4A0_MASK		= 3,
+	GPIO4A0_GPIO		= 0,
+	GPIO4A0_FLASH1_RDY,
+	GPIO4A0_HOST_CKOUTP,
+	GPIO4A0_MAC_MDC,
+};
+
+/* GRF_GPIO4AH_IOMUX */
+enum {
+	GPIO4A7_SHIFT		= 12,
+	GPIO4A7_MASK		= 7,
+	GPIO4A7_GPIO		= 0,
+	GPIO4A7_FLASH1_CSN1,
+	GPIO4A7_HOST_DOUT13,
+	GPIO4A7_MAC_CSR,
+	GPIO4A7_SDIO1_CLKOUT,
+
+	GPIO4A6_SHIFT		= 8,
+	GPIO4A6_MASK		= 7,
+	GPIO4A6_GPIO		= 0,
+	GPIO4A6_FLASH1_CSN0,
+	GPIO4A6_HOST_DOUT12,
+	GPIO4A6_MAC_RXCLK,
+	GPIO4A6_SDIO1_CMD,
+
+	GPIO4A5_SHIFT		= 4,
+	GPIO4A5_MASK		= 3,
+	GPIO4A5_GPIO		= 0,
+	GPIO4A5_FLASH1_WRN,
+	GPIO4A5_HOST_DOUT11,
+	GPIO4A5_MAC_MDIO,
+
+	GPIO4A4_SHIFT		= 0,
+	GPIO4A4_MASK		= 7,
+	GPIO4A4_GPIO		= 0,
+	GPIO4A4_FLASH1_CLE,
+	GPIO4A4_HOST_DOUT10,
+	GPIO4A4_MAC_TXEN,
+	GPIO4A4_FLASH0_CSN7,
+};
+
+/* GRF_GPIO4BL_IOMUX */
+enum {
+	GPIO4B1_SHIFT		= 4,
+	GPIO4B1_MASK		= 7,
+	GPIO4B1_GPIO		= 0,
+	GPIO4B1_FLASH1_CSN2,
+	GPIO4B1_HOST_DOUT15,
+	GPIO4B1_MAC_TXCLK,
+	GPIO4B1_SDIO1_PWREN,
+
+	GPIO4B0_SHIFT		= 0,
+	GPIO4B0_MASK		= 7,
+	GPIO4B0_GPIO		= 0,
+	GPIO4B0_FLASH1_DQS,
+	GPIO4B0_HOST_DOUT14,
+	GPIO4B0_MAC_COL,
+	GPIO4B0_FLASH1_CSN3,
+};
+
+/* GRF_GPIO4C_IOMUX */
+enum {
+	GPIO4C7_SHIFT		= 14,
+	GPIO4C7_MASK		= 1,
+	GPIO4C7_GPIO		= 0,
+	GPIO4C7_SDIO0_DATA3,
+
+	GPIO4C6_SHIFT		= 12,
+	GPIO4C6_MASK		= 1,
+	GPIO4C6_GPIO		= 0,
+	GPIO4C6_SDIO0_DATA2,
+
+	GPIO4C5_SHIFT		= 10,
+	GPIO4C5_MASK		= 1,
+	GPIO4C5_GPIO		= 0,
+	GPIO4C5_SDIO0_DATA1,
+
+	GPIO4C4_SHIFT		= 8,
+	GPIO4C4_MASK		= 1,
+	GPIO4C4_GPIO		= 0,
+	GPIO4C4_SDIO0_DATA0,
+
+	GPIO4C3_SHIFT		= 6,
+	GPIO4C3_MASK		= 1,
+	GPIO4C3_GPIO		= 0,
+	GPIO4C3_UART0BT_RTSN,
+
+	GPIO4C2_SHIFT		= 4,
+	GPIO4C2_MASK		= 1,
+	GPIO4C2_GPIO		= 0,
+	GPIO4C2_UART0BT_CTSN,
+
+	GPIO4C1_SHIFT		= 2,
+	GPIO4C1_MASK		= 1,
+	GPIO4C1_GPIO		= 0,
+	GPIO4C1_UART0BT_SOUT,
+
+	GPIO4C0_SHIFT		= 0,
+	GPIO4C0_MASK		= 1,
+	GPIO4C0_GPIO		= 0,
+	GPIO4C0_UART0BT_SIN,
+};
+
+/* GRF_GPIO5B_IOMUX */
+enum {
+	GPIO5B7_SHIFT		= 14,
+	GPIO5B7_MASK		= 3,
+	GPIO5B7_GPIO		= 0,
+	GPIO5B7_SPI0_RXD,
+	GPIO5B7_TS0_DATA7,
+	GPIO5B7_UART4EXP_SIN,
+
+	GPIO5B6_SHIFT		= 12,
+	GPIO5B6_MASK		= 3,
+	GPIO5B6_GPIO		= 0,
+	GPIO5B6_SPI0_TXD,
+	GPIO5B6_TS0_DATA6,
+	GPIO5B6_UART4EXP_SOUT,
+
+	GPIO5B5_SHIFT		= 10,
+	GPIO5B5_MASK		= 3,
+	GPIO5B5_GPIO		= 0,
+	GPIO5B5_SPI0_CSN0,
+	GPIO5B5_TS0_DATA5,
+	GPIO5B5_UART4EXP_RTSN,
+
+	GPIO5B4_SHIFT		= 8,
+	GPIO5B4_MASK		= 3,
+	GPIO5B4_GPIO		= 0,
+	GPIO5B4_SPI0_CLK,
+	GPIO5B4_TS0_DATA4,
+	GPIO5B4_UART4EXP_CTSN,
+
+	GPIO5B3_SHIFT		= 6,
+	GPIO5B3_MASK		= 3,
+	GPIO5B3_GPIO		= 0,
+	GPIO5B3_UART1BB_RTSN,
+	GPIO5B3_TS0_DATA3,
+
+	GPIO5B2_SHIFT		= 4,
+	GPIO5B2_MASK		= 3,
+	GPIO5B2_GPIO		= 0,
+	GPIO5B2_UART1BB_CTSN,
+	GPIO5B2_TS0_DATA2,
+
+	GPIO5B1_SHIFT		= 2,
+	GPIO5B1_MASK		= 3,
+	GPIO5B1_GPIO		= 0,
+	GPIO5B1_UART1BB_SOUT,
+	GPIO5B1_TS0_DATA1,
+
+	GPIO5B0_SHIFT		= 0,
+	GPIO5B0_MASK		= 3,
+	GPIO5B0_GPIO		= 0,
+	GPIO5B0_UART1BB_SIN,
+	GPIO5B0_TS0_DATA0,
+};
+
+/* GRF_GPIO5C_IOMUX */
+enum {
+	GPIO5C3_SHIFT		= 6,
+	GPIO5C3_MASK		= 1,
+	GPIO5C3_GPIO		= 0,
+	GPIO5C3_TS0_ERR,
+
+	GPIO5C2_SHIFT		= 4,
+	GPIO5C2_MASK		= 1,
+	GPIO5C2_GPIO		= 0,
+	GPIO5C2_TS0_CLK,
+
+	GPIO5C1_SHIFT		= 2,
+	GPIO5C1_MASK		= 1,
+	GPIO5C1_GPIO		= 0,
+	GPIO5C1_TS0_VALID,
+
+	GPIO5C0_SHIFT		= 0,
+	GPIO5C0_MASK		= 3,
+	GPIO5C0_GPIO		= 0,
+	GPIO5C0_SPI0_CSN1,
+	GPIO5C0_TS0_SYNC,
+};
+
+/* GRF_GPIO6A_IOMUX */
+enum {
+	GPIO6A7_SHIFT		= 0xe,
+	GPIO6A7_MASK		= 1,
+	GPIO6A7_GPIO		= 0,
+	GPIO6A7_I2S_SDO3,
+
+	GPIO6A6_SHIFT		= 0xc,
+	GPIO6A6_MASK		= 1,
+	GPIO6A6_GPIO		= 0,
+	GPIO6A6_I2S_SDO2,
+
+	GPIO6A5_SHIFT		= 0xa,
+	GPIO6A5_MASK		= 1,
+	GPIO6A5_GPIO		= 0,
+	GPIO6A5_I2S_SDO1,
+
+	GPIO6A4_SHIFT		= 8,
+	GPIO6A4_MASK		= 1,
+	GPIO6A4_GPIO		= 0,
+	GPIO6A4_I2S_SDO0,
+
+	GPIO6A3_SHIFT		= 6,
+	GPIO6A3_MASK		= 1,
+	GPIO6A3_GPIO		= 0,
+	GPIO6A3_I2S_SDI,
+
+	GPIO6A2_SHIFT		= 4,
+	GPIO6A2_MASK		= 1,
+	GPIO6A2_GPIO		= 0,
+	GPIO6A2_I2S_LRCKTX,
+
+	GPIO6A1_SHIFT		= 2,
+	GPIO6A1_MASK		= 1,
+	GPIO6A1_GPIO		= 0,
+	GPIO6A1_I2S_LRCKRX,
+
+	GPIO6A0_SHIFT		= 0,
+	GPIO6A0_MASK		= 1,
+	GPIO6A0_GPIO		= 0,
+	GPIO6A0_I2S_SCLK,
+};
+
+/* GRF_GPIO6B_IOMUX */
+enum {
+	GPIO6B3_SHIFT		= 6,
+	GPIO6B3_MASK		= 1,
+	GPIO6B3_GPIO		= 0,
+	GPIO6B3_SPDIF_TX,
+
+	GPIO6B2_SHIFT		= 4,
+	GPIO6B2_MASK		= 1,
+	GPIO6B2_GPIO		= 0,
+	GPIO6B2_I2C1AUDIO_SCL,
+
+	GPIO6B1_SHIFT		= 2,
+	GPIO6B1_MASK		= 1,
+	GPIO6B1_GPIO		= 0,
+	GPIO6B1_I2C1AUDIO_SDA,
+
+	GPIO6B0_SHIFT		= 0,
+	GPIO6B0_MASK		= 1,
+	GPIO6B0_GPIO		= 0,
+	GPIO6B0_I2S_CLK,
+};
+
+/* GRF_GPIO6C_IOMUX */
+enum {
+	GPIO6C6_SHIFT		= 12,
+	GPIO6C6_MASK		= 1,
+	GPIO6C6_GPIO		= 0,
+	GPIO6C6_SDMMC0_DECTN,
+
+	GPIO6C5_SHIFT		= 10,
+	GPIO6C5_MASK		= 1,
+	GPIO6C5_GPIO		= 0,
+	GPIO6C5_SDMMC0_CMD,
+
+	GPIO6C4_SHIFT		= 8,
+	GPIO6C4_MASK		= 3,
+	GPIO6C4_GPIO		= 0,
+	GPIO6C4_SDMMC0_CLKOUT,
+	GPIO6C4_JTAG_TDO,
+
+	GPIO6C3_SHIFT		= 6,
+	GPIO6C3_MASK		= 3,
+	GPIO6C3_GPIO		= 0,
+	GPIO6C3_SDMMC0_DATA3,
+	GPIO6C3_JTAG_TCK,
+
+	GPIO6C2_SHIFT		= 4,
+	GPIO6C2_MASK		= 3,
+	GPIO6C2_GPIO		= 0,
+	GPIO6C2_SDMMC0_DATA2,
+	GPIO6C2_JTAG_TDI,
+
+	GPIO6C1_SHIFT		= 2,
+	GPIO6C1_MASK		= 3,
+	GPIO6C1_GPIO		= 0,
+	GPIO6C1_SDMMC0_DATA1,
+	GPIO6C1_JTAG_TRSTN,
+
+	GPIO6C0_SHIFT		= 0,
+	GPIO6C0_MASK		= 3,
+	GPIO6C0_GPIO		= 0,
+	GPIO6C0_SDMMC0_DATA0,
+	GPIO6C0_JTAG_TMS,
+};
+
+/* GRF_GPIO7A_IOMUX */
+enum {
+	GPIO7A7_SHIFT		= 14,
+	GPIO7A7_MASK		= 3,
+	GPIO7A7_GPIO		= 0,
+	GPIO7A7_UART3GPS_SIN,
+	GPIO7A7_GPS_MAG,
+	GPIO7A7_HSADCT1_DATA0,
+
+	GPIO7A1_SHIFT		= 2,
+	GPIO7A1_MASK		= 1,
+	GPIO7A1_GPIO		= 0,
+	GPIO7A1_PWM_1,
+
+	GPIO7A0_SHIFT		= 0,
+	GPIO7A0_MASK		= 3,
+	GPIO7A0_GPIO		= 0,
+	GPIO7A0_PWM_0,
+	GPIO7A0_VOP0_PWM,
+	GPIO7A0_VOP1_PWM,
+};
+
+/* GRF_GPIO7B_IOMUX */
+enum {
+	GPIO7B7_SHIFT		= 14,
+	GPIO7B7_MASK		= 3,
+	GPIO7B7_GPIO		= 0,
+	GPIO7B7_ISP_SHUTTERTRIG,
+	GPIO7B7_SPI1_TXD,
+
+	GPIO7B6_SHIFT		= 12,
+	GPIO7B6_MASK		= 3,
+	GPIO7B6_GPIO		= 0,
+	GPIO7B6_ISP_PRELIGHTTRIG,
+	GPIO7B6_SPI1_RXD,
+
+	GPIO7B5_SHIFT		= 10,
+	GPIO7B5_MASK		= 3,
+	GPIO7B5_GPIO		= 0,
+	GPIO7B5_ISP_FLASHTRIGOUT,
+	GPIO7B5_SPI1_CSN0,
+
+	GPIO7B4_SHIFT		= 8,
+	GPIO7B4_MASK		= 3,
+	GPIO7B4_GPIO		= 0,
+	GPIO7B4_ISP_SHUTTEREN,
+	GPIO7B4_SPI1_CLK,
+
+	GPIO7B3_SHIFT		= 6,
+	GPIO7B3_MASK		= 3,
+	GPIO7B3_GPIO		= 0,
+	GPIO7B3_USB_DRVVBUS1,
+	GPIO7B3_EDP_HOTPLUG,
+
+	GPIO7B2_SHIFT		= 4,
+	GPIO7B2_MASK		= 3,
+	GPIO7B2_GPIO		= 0,
+	GPIO7B2_UART3GPS_RTSN,
+	GPIO7B2_USB_DRVVBUS0,
+
+	GPIO7B1_SHIFT		= 2,
+	GPIO7B1_MASK		= 3,
+	GPIO7B1_GPIO		= 0,
+	GPIO7B1_UART3GPS_CTSN,
+	GPIO7B1_GPS_RFCLK,
+	GPIO7B1_GPST1_CLK,
+
+	GPIO7B0_SHIFT		= 0,
+	GPIO7B0_MASK		= 3,
+	GPIO7B0_GPIO		= 0,
+	GPIO7B0_UART3GPS_SOUT,
+	GPIO7B0_GPS_SIG,
+	GPIO7B0_HSADCT1_DATA1,
+};
+
+/* GRF_GPIO7CL_IOMUX */
+enum {
+	GPIO7C3_SHIFT		= 12,
+	GPIO7C3_MASK		= 3,
+	GPIO7C3_GPIO		= 0,
+	GPIO7C3_I2C5HDMI_SDA,
+	GPIO7C3_EDPHDMII2C_SDA,
+
+	GPIO7C2_SHIFT		= 8,
+	GPIO7C2_MASK		= 1,
+	GPIO7C2_GPIO		= 0,
+	GPIO7C2_I2C4TP_SCL,
+
+	GPIO7C1_SHIFT		= 4,
+	GPIO7C1_MASK		= 1,
+	GPIO7C1_GPIO		= 0,
+	GPIO7C1_I2C4TP_SDA,
+
+	GPIO7C0_SHIFT		= 0,
+	GPIO7C0_MASK		= 3,
+	GPIO7C0_GPIO		= 0,
+	GPIO7C0_ISP_FLASHTRIGIN,
+	GPIO7C0_EDPHDMI_CECINOUTT1,
+};
+
+/* GRF_GPIO7CH_IOMUX */
+enum {
+	GPIO7C7_SHIFT		= 12,
+	GPIO7C7_MASK		= 7,
+	GPIO7C7_GPIO		= 0,
+	GPIO7C7_UART2DBG_SOUT,
+	GPIO7C7_UART2DBG_SIROUT,
+	GPIO7C7_PWM_3,
+	GPIO7C7_EDPHDMI_CECINOUT,
+
+	GPIO7C6_SHIFT		= 8,
+	GPIO7C6_MASK		= 3,
+	GPIO7C6_GPIO		= 0,
+	GPIO7C6_UART2DBG_SIN,
+	GPIO7C6_UART2DBG_SIRIN,
+	GPIO7C6_PWM_2,
+
+	GPIO7C4_SHIFT		= 0,
+	GPIO7C4_MASK		= 3,
+	GPIO7C4_GPIO		= 0,
+	GPIO7C4_I2C5HDMI_SCL,
+	GPIO7C4_EDPHDMII2C_SCL,
+};
+
+/* GRF_GPIO8A_IOMUX */
+enum {
+	GPIO8A7_SHIFT		= 14,
+	GPIO8A7_MASK		= 3,
+	GPIO8A7_GPIO		= 0,
+	GPIO8A7_SPI2_CSN0,
+	GPIO8A7_SC_DETECT,
+	GPIO8A7_RESERVE,
+
+	GPIO8A6_SHIFT		= 12,
+	GPIO8A6_MASK		= 3,
+	GPIO8A6_GPIO		= 0,
+	GPIO8A6_SPI2_CLK,
+	GPIO8A6_SC_IO,
+	GPIO8A6_RESERVE,
+
+	GPIO8A5_SHIFT		= 10,
+	GPIO8A5_MASK		= 3,
+	GPIO8A5_GPIO		= 0,
+	GPIO8A5_I2C2SENSOR_SCL,
+	GPIO8A5_SC_CLK,
+
+	GPIO8A4_SHIFT		= 8,
+	GPIO8A4_MASK		= 3,
+	GPIO8A4_GPIO		= 0,
+	GPIO8A4_I2C2SENSOR_SDA,
+	GPIO8A4_SC_RST,
+
+	GPIO8A3_SHIFT		= 6,
+	GPIO8A3_MASK		= 3,
+	GPIO8A3_GPIO		= 0,
+	GPIO8A3_SPI2_CSN1,
+	GPIO8A3_SC_IOT1,
+
+	GPIO8A2_SHIFT		= 4,
+	GPIO8A2_MASK		= 1,
+	GPIO8A2_GPIO		= 0,
+	GPIO8A2_SC_DETECTT1,
+
+	GPIO8A1_SHIFT		= 2,
+	GPIO8A1_MASK		= 3,
+	GPIO8A1_GPIO		= 0,
+	GPIO8A1_PS2_DATA,
+	GPIO8A1_SC_VCC33V,
+
+	GPIO8A0_SHIFT		= 0,
+	GPIO8A0_MASK		= 3,
+	GPIO8A0_GPIO		= 0,
+	GPIO8A0_PS2_CLK,
+	GPIO8A0_SC_VCC18V,
+};
+
+/* GRF_GPIO8B_IOMUX */
+enum {
+	GPIO8B1_SHIFT		= 2,
+	GPIO8B1_MASK		= 3,
+	GPIO8B1_GPIO		= 0,
+	GPIO8B1_SPI2_TXD,
+	GPIO8B1_SC_CLK,
+
+	GPIO8B0_SHIFT		= 0,
+	GPIO8B0_MASK		= 3,
+	GPIO8B0_GPIO		= 0,
+	GPIO8B0_SPI2_RXD,
+	GPIO8B0_SC_RST,
+};
+
+/* GRF_SOC_CON0 */
+enum {
+	PAUSE_MMC_PERI_SHIFT	= 0xf,
+	PAUSE_MMC_PERI_MASK	= 1,
+
+	PAUSE_EMEM_PERI_SHIFT	= 0xe,
+	PAUSE_EMEM_PERI_MASK	= 1,
+
+	PAUSE_USB_PERI_SHIFT	= 0xd,
+	PAUSE_USB_PERI_MASK	= 1,
+
+	GRF_FORCE_JTAG_SHIFT	= 0xc,
+	GRF_FORCE_JTAG_MASK	= 1,
+
+	GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb,
+	GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1,
+
+	GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa,
+	GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1,
+
+	DDR1_16BIT_EN_SHIFT	= 9,
+	DDR1_16BIT_EN_MASK	= 1,
+
+	DDR0_16BIT_EN_SHIFT	= 8,
+	DDR0_16BIT_EN_MASK	= 1,
+
+	VCODEC_SHIFT		= 7,
+	VCODEC_MASK		= 1,
+	VCODEC_SELECT_VEPU_ACLK	= 0,
+	VCODEC_SELECT_VDPU_ACLK,
+
+	UPCTL1_C_ACTIVE_IN_SHIFT = 6,
+	UPCTL1_C_ACTIVE_IN_MASK	= 1,
+	UPCTL1_C_ACTIVE_IN_MAY	= 0,
+	UPCTL1_C_ACTIVE_IN_WILL,
+
+	UPCTL0_C_ACTIVE_IN_SHIFT = 5,
+	UPCTL0_C_ACTIVE_IN_MASK	= 1,
+	UPCTL0_C_ACTIVE_IN_MAY	= 0,
+	UPCTL0_C_ACTIVE_IN_WILL,
+
+	MSCH1_MAINDDR3_SHIFT	= 4,
+	MSCH1_MAINDDR3_MASK	= 1,
+	MSCH1_MAINDDR3_DDR3	= 1,
+
+	MSCH0_MAINDDR3_SHIFT	= 3,
+	MSCH0_MAINDDR3_MASK	= 1,
+	MSCH0_MAINDDR3_DDR3	= 1,
+
+	MSCH1_MAINPARTIALPOP_SHIFT = 2,
+	MSCH1_MAINPARTIALPOP_MASK = 1,
+
+	MSCH0_MAINPARTIALPOP_SHIFT = 1,
+	MSCH0_MAINPARTIALPOP_MASK = 1,
+};
+
+/* GRF_SOC_CON1 */
+enum {
+	RK3288_RMII_MODE_SHIFT = 14,
+	RK3288_RMII_MODE_MASK  = (1 << RK3288_RMII_MODE_SHIFT),
+	RK3288_RMII_MODE       = (1 << RK3288_RMII_MODE_SHIFT),
+
+	RK3288_GMAC_CLK_SEL_SHIFT = 12,
+	RK3288_GMAC_CLK_SEL_MASK  = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_125M  = (0 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_25M   = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
+	RK3288_GMAC_CLK_SEL_2_5M  = (2 << RK3288_GMAC_CLK_SEL_SHIFT),
+
+	RK3288_RMII_CLK_SEL_SHIFT = 11,
+	RK3288_RMII_CLK_SEL_MASK  = (1 << RK3288_RMII_CLK_SEL_SHIFT),
+	RK3288_RMII_CLK_SEL_2_5M  = (0 << RK3288_RMII_CLK_SEL_SHIFT),
+	RK3288_RMII_CLK_SEL_25M   = (1 << RK3288_RMII_CLK_SEL_SHIFT),
+
+	GMAC_SPEED_SHIFT	= 0xa,
+	GMAC_SPEED_MASK		= 1,
+	GMAC_SPEED_10M		= 0,
+	GMAC_SPEED_100M,
+
+	GMAC_FLOWCTRL_SHIFT	= 0x9,
+	GMAC_FLOWCTRL_MASK	= 1,
+
+	RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
+	RK3288_GMAC_PHY_INTF_SEL_MASK  = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3288_GMAC_PHY_INTF_SEL_RMII  = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
+
+	HOST_REMAP_SHIFT	= 0x5,
+	HOST_REMAP_MASK		= 1
+};
+
+/* GRF_SOC_CON2 */
+enum {
+	UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
+	UPCTL1_LPDDR3_ODT_EN_MASK = 1,
+	UPCTL1_LPDDR3_ODT_EN_ODT = 1,
+
+	UPCTL1_BST_DIABLE_SHIFT	= 0xc,
+	UPCTL1_BST_DIABLE_MASK	= 1,
+	UPCTL1_BST_DIABLE_DISABLE = 1,
+
+	LPDDR3_EN1_SHIFT	= 0xb,
+	LPDDR3_EN1_MASK		= 1,
+	LPDDR3_EN1_LPDDR3	= 1,
+
+	UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa,
+	UPCTL0_LPDDR3_ODT_EN_MASK = 1,
+	UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1,
+
+	UPCTL0_BST_DIABLE_SHIFT	= 9,
+	UPCTL0_BST_DIABLE_MASK	= 1,
+	UPCTL0_BST_DIABLE_DISABLE = 1,
+
+	LPDDR3_EN0_SHIFT	= 8,
+	LPDDR3_EN0_MASK		= 1,
+	LPDDR3_EN0_LPDDR3	= 1,
+
+	GRF_POC_FLASH0_CTRL_SHIFT = 7,
+	GRF_POC_FLASH0_CTRL_MASK = 1,
+	GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0,
+	GRF_POC_FLASH0_CTRL_GRF_IO_VSEL,
+
+	SIMCARD_MUX_SHIFT	= 6,
+	SIMCARD_MUX_MASK	= 1,
+	SIMCARD_MUX_USE_A	= 1,
+	SIMCARD_MUX_USE_B	= 0,
+
+	GRF_SPDIF_2CH_EN_SHIFT	= 1,
+	GRF_SPDIF_2CH_EN_MASK	= 1,
+	GRF_SPDIF_2CH_EN_8CH	= 0,
+	GRF_SPDIF_2CH_EN_2CH,
+
+	PWM_SHIFT		= 0,
+	PWM_MASK		= 1,
+	PWM_RK			= 1,
+	PWM_PWM			= 0,
+};
+
+/* GRF_SOC_CON3 */
+enum {
+	RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
+	RK3288_RXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3288_RXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
+	RK3288_TXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+	RK3288_CLK_RX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT),
+
+	RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+	RK3288_CLK_TX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT),
+};
+
+/* GRF_SOC_CON6 */
+enum GRF_SOC_CON6 {
+	RK3288_HDMI_EDP_SEL_SHIFT = 0xf,
+	RK3288_HDMI_EDP_SEL_MASK =
+		1 << RK3288_HDMI_EDP_SEL_SHIFT,
+	RK3288_HDMI_EDP_SEL_EDP = 0,
+	RK3288_HDMI_EDP_SEL_HDMI,
+
+	RK3288_DSI0_DPICOLORM_SHIFT = 0x8,
+	RK3288_DSI0_DPICOLORM_MASK =
+		1 << RK3288_DSI0_DPICOLORM_SHIFT,
+
+	RK3288_DSI0_DPISHUTDN_SHIFT = 0x7,
+	RK3288_DSI0_DPISHUTDN_MASK =
+		1 << RK3288_DSI0_DPISHUTDN_SHIFT,
+
+	RK3288_DSI0_LCDC_SEL_SHIFT = 0x6,
+	RK3288_DSI0_LCDC_SEL_MASK =
+		1 << RK3288_DSI0_LCDC_SEL_SHIFT,
+	RK3288_DSI0_LCDC_SEL_BIG = 0,
+	RK3288_DSI0_LCDC_SEL_LIT = 1,
+
+	RK3288_EDP_LCDC_SEL_SHIFT = 0x5,
+	RK3288_EDP_LCDC_SEL_MASK =
+		1 << RK3288_EDP_LCDC_SEL_SHIFT,
+	RK3288_EDP_LCDC_SEL_BIG = 0,
+	RK3288_EDP_LCDC_SEL_LIT = 1,
+
+	RK3288_HDMI_LCDC_SEL_SHIFT = 0x4,
+	RK3288_HDMI_LCDC_SEL_MASK =
+		1 << RK3288_HDMI_LCDC_SEL_SHIFT,
+	RK3288_HDMI_LCDC_SEL_BIG = 0,
+	RK3288_HDMI_LCDC_SEL_LIT = 1,
+
+	RK3288_LVDS_LCDC_SEL_SHIFT = 0x3,
+	RK3288_LVDS_LCDC_SEL_MASK =
+		1 << RK3288_LVDS_LCDC_SEL_SHIFT,
+	RK3288_LVDS_LCDC_SEL_BIG = 0,
+	RK3288_LVDS_LCDC_SEL_LIT = 1,
+};
+
+/* RK3288_SOC_CON8 */
+enum GRF_SOC_CON8 {
+	RK3288_DPHY_TX0_RXMODE_SHIFT = 4,
+	RK3288_DPHY_TX0_RXMODE_MASK =
+	   0xf << RK3288_DPHY_TX0_RXMODE_SHIFT,
+	RK3288_DPHY_TX0_RXMODE_EN = 0xf,
+	RK3288_DPHY_TX0_RXMODE_DIS = 0,
+
+	RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8,
+	RK3288_DPHY_TX0_TXSTOPMODE_MASK =
+	   0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT,
+	RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf,
+	RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0,
+
+	RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0,
+	RK3288_DPHY_TX0_TURNREQUEST_MASK =
+	   0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT,
+	RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf,
+	RK3288_DPHY_TX0_TURNREQUEST_DIS = 0,
+};
+
+/* GRF_IO_VSEL */
+enum {
+	GPIO1830_V18SEL_SHIFT		= 9,
+	GPIO1830_V18SEL_MASK		= 1,
+	GPIO1830_V18SEL_3_3V		= 0,
+	GPIO1830_V18SEL_1_8V,
+
+	GPIO30_V18SEL_SHIFT	= 8,
+	GPIO30_V18SEL_MASK	= 1,
+	GPIO30_V18SEL_3_3V	= 0,
+	GPIO30_V18SEL_1_8V,
+
+	SDCARD_V18SEL_SHIFT	= 7,
+	SDCARD_V18SEL_MASK	= 1,
+	SDCARD_V18SEL_3_3V	= 0,
+	SDCARD_V18SEL_1_8V,
+
+	AUDIO_V18SEL_SHIFT	= 6,
+	AUDIO_V18SEL_MASK	= 1,
+	AUDIO_V18SEL_3_3V	= 0,
+	AUDIO_V18SEL_1_8V,
+
+	BB_V18SEL_SHIFT		= 5,
+	BB_V18SEL_MASK		= 1,
+	BB_V18SEL_3_3V		= 0,
+	BB_V18SEL_1_8V,
+
+	WIFI_V18SEL_SHIFT	= 4,
+	WIFI_V18SEL_MASK	= 1,
+	WIFI_V18SEL_3_3V	= 0,
+	WIFI_V18SEL_1_8V,
+
+	FLASH1_V18SEL_SHIFT	= 3,
+	FLASH1_V18SEL_MASK	= 1,
+	FLASH1_V18SEL_3_3V	= 0,
+	FLASH1_V18SEL_1_8V,
+
+	FLASH0_V18SEL_SHIFT	= 2,
+	FLASH0_V18SEL_MASK	= 1,
+	FLASH0_V18SEL_3_3V	= 0,
+	FLASH0_V18SEL_1_8V,
+
+	DVP_V18SEL_SHIFT	= 1,
+	DVP_V18SEL_MASK		= 1,
+	DVP_V18SEL_3_3V		= 0,
+	DVP_V18SEL_1_8V,
+
+	LCDC_V18SEL_SHIFT	= 0,
+	LCDC_V18SEL_MASK	= 1,
+	LCDC_V18SEL_3_3V	= 0,
+	LCDC_V18SEL_1_8V,
+};
+
+/* GPIO Bias settings */
+enum GPIO_BIAS {
+	GPIO_BIAS_2MA = 0,
+	GPIO_BIAS_4MA,
+	GPIO_BIAS_8MA,
+	GPIO_BIAS_12MA,
+};
+
+#define GPIO_BIAS_MASK	0x3
+#define GPIO_BIAS_SHIFT(x)  ((x) * 2)
+
+#define GPIO_PULL_MASK	0x3
+#define GPIO_PULL_SHIFT(x)  ((x) * 2)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
new file mode 100644
index 0000000..d8a4680
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3328_GRF_H__
+#define __SOC_ROCKCHIP_RK3328_GRF_H__
+
+struct rk3328_grf_regs {
+	u32 gpio0a_iomux;
+	u32 gpio0b_iomux;
+	u32 gpio0c_iomux;
+	u32 gpio0d_iomux;
+	u32 gpio1a_iomux;
+	u32 gpio1b_iomux;
+	u32 gpio1c_iomux;
+	u32 gpio1d_iomux;
+	u32 gpio2a_iomux;
+	u32 gpio2bl_iomux;
+	u32 gpio2bh_iomux;
+	u32 gpio2cl_iomux;
+	u32 gpio2ch_iomux;
+	u32 gpio2d_iomux;
+	u32 gpio3al_iomux;
+	u32 gpio3ah_iomux;
+	u32 gpio3bl_iomux;
+	u32 gpio3bh_iomux;
+	u32 gpio3c_iomux;
+	u32 gpio3d_iomux;
+	u32 com_iomux;
+	u32 reserved1[(0x100 - 0x54) / 4];
+
+	u32 gpio0a_p;
+	u32 gpio0b_p;
+	u32 gpio0c_p;
+	u32 gpio0d_p;
+	u32 gpio1a_p;
+	u32 gpio1b_p;
+	u32 gpio1c_p;
+	u32 gpio1d_p;
+	u32 gpio2a_p;
+	u32 gpio2b_p;
+	u32 gpio2c_p;
+	u32 gpio2d_p;
+	u32 gpio3a_p;
+	u32 gpio3b_p;
+	u32 gpio3c_p;
+	u32 gpio3d_p;
+	u32 reserved2[(0x200 - 0x140) / 4];
+	u32 gpio0a_e;
+	u32 gpio0b_e;
+	u32 gpio0c_e;
+	u32 gpio0d_e;
+	u32 gpio1a_e;
+	u32 gpio1b_e;
+	u32 gpio1c_e;
+	u32 gpio1d_e;
+	u32 gpio2a_e;
+	u32 gpio2b_e;
+	u32 gpio2c_e;
+	u32 gpio2d_e;
+	u32 gpio3a_e;
+	u32 gpio3b_e;
+	u32 gpio3c_e;
+	u32 gpio3d_e;
+	u32 reserved3[(0x300 - 0x240) / 4];
+	u32 gpio0l_sr;
+	u32 gpio0h_sr;
+	u32 gpio1l_sr;
+	u32 gpio1h_sr;
+	u32 gpio2l_sr;
+	u32 gpio2h_sr;
+	u32 gpio3l_sr;
+	u32 gpio3h_sr;
+	u32 reserved4[(0x380 - 0x320) / 4];
+	u32 gpio0l_smt;
+	u32 gpio0h_smt;
+	u32 gpio1l_smt;
+	u32 gpio1h_smt;
+	u32 gpio2l_smt;
+	u32 gpio2h_smt;
+	u32 gpio3l_smt;
+	u32 gpio3h_smt;
+	u32 reserved5[(0x400 - 0x3a0) / 4];
+	u32 soc_con[11];
+	u32 reserved6[(0x480 - 0x42c) / 4];
+	u32 soc_status[5];
+	u32 reserved7[(0x4c0 - 0x494) / 4];
+	u32 otg3_con[2];
+	u32 reserved8[(0x500 - 0x4c8) / 4];
+	u32 cpu_con[2];
+	u32 reserved9[(0x520 - 0x508) / 4];
+	u32 cpu_status[2];
+	u32 reserved10[(0x5c8 - 0x528) / 4];
+	u32 os_reg[8];
+	u32 reserved11[(0x680 - 0x5e8) / 4];
+	u32 sig_detect_con;
+	u32 reserved12[3];
+	u32 sig_detect_status;
+	u32 reserved13[3];
+	u32 sig_detect_status_clr;
+	u32 reserved14[3];
+
+	u32 sdmmc_det_counter;
+	u32 reserved15[(0x700 - 0x6b4) / 4];
+	u32 host0_con[3];
+	u32 reserved16[(0x880 - 0x70c) / 4];
+	u32 otg_con0;
+	u32 reserved17[3];
+	u32 host0_status;
+	u32 reserved18[(0x900 - 0x894) / 4];
+	u32 mac_con[3];
+	u32 reserved19[(0xb00 - 0x90c) / 4];
+	u32 macphy_con[4];
+	u32 macphy_status;
+};
+check_member(rk3328_grf_regs, macphy_status, 0xb10);
+
+struct rk3328_sgrf_regs {
+	u32 soc_con[6];
+	u32 reserved0[(0x100 - 0x18) / 4];
+	u32 dmac_con[6];
+	u32 reserved1[(0x180 - 0x118) / 4];
+	u32 fast_boot_addr;
+	u32 reserved2[(0x200 - 0x184) / 4];
+	u32 chip_fuse_con;
+	u32 reserved3[(0x280 - 0x204) / 4];
+	u32 hdcp_key_reg[8];
+	u32 hdcp_key_access_mask;
+};
+check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0);
+
+#endif	/* __SOC_ROCKCHIP_RK3328_GRF_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
new file mode 100644
index 0000000..b70b08f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+#ifndef _ASM_ARCH_GRF_RK3368_H
+#define _ASM_ARCH_GRF_RK3368_H
+
+#include <common.h>
+
+struct rk3368_grf {
+	u32 gpio1a_iomux;
+	u32 gpio1b_iomux;
+	u32 gpio1c_iomux;
+	u32 gpio1d_iomux;
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+	u32 gpio2c_iomux;
+	u32 gpio2d_iomux;
+	u32 gpio3a_iomux;
+	u32 gpio3b_iomux;
+	u32 gpio3c_iomux;
+	u32 gpio3d_iomux;
+	u32 reserved[0x34];
+	u32 gpio1a_pull;
+	u32 gpio1b_pull;
+	u32 gpio1c_pull;
+	u32 gpio1d_pull;
+	u32 gpio2a_pull;
+	u32 gpio2b_pull;
+	u32 gpio2c_pull;
+	u32 gpio2d_pull;
+	u32 gpio3a_pull;
+	u32 gpio3b_pull;
+	u32 gpio3c_pull;
+	u32 gpio3d_pull;
+	u32 reserved1[0x34];
+	u32 gpio1a_drv;
+	u32 gpio1b_drv;
+	u32 gpio1c_drv;
+	u32 gpio1d_drv;
+	u32 gpio2a_drv;
+	u32 gpio2b_drv;
+	u32 gpio2c_drv;
+	u32 gpio2d_drv;
+	u32 gpio3a_drv;
+	u32 gpio3b_drv;
+	u32 gpio3c_drv;
+	u32 gpio3d_drv;
+	u32 reserved2[0x34];
+	u32 gpio1l_sr;
+	u32 gpio1h_sr;
+	u32 gpio2l_sr;
+	u32 gpio2h_sr;
+	u32 gpio3l_sr;
+	u32 gpio3h_sr;
+	u32 reserved3[0x1a];
+	u32 gpio_smt;
+	u32 reserved4[0x1f];
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
+	u32 soc_con15;
+	u32 soc_con16;
+	u32 soc_con17;
+	u32 reserved5[0x6e];
+	u32 ddrc0_con0;
+};
+check_member(rk3368_grf, soc_con17, 0x444);
+check_member(rk3368_grf, ddrc0_con0, 0x600);
+
+struct rk3368_pmu_grf {
+	u32 gpio0a_iomux;
+	u32 gpio0b_iomux;
+	u32 gpio0c_iomux;
+	u32 gpio0d_iomux;
+	u32 gpio0a_pull;
+	u32 gpio0b_pull;
+	u32 gpio0c_pull;
+	u32 gpio0d_pull;
+	u32 gpio0a_drv;
+	u32 gpio0b_drv;
+	u32 gpio0c_drv;
+	u32 gpio0d_drv;
+	u32 gpio0l_sr;
+	u32 gpio0h_sr;
+	u32 reserved[0x72];
+	u32 os_reg[4];
+};
+check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
+check_member(rk3368_pmu_grf, os_reg[0], 0x200);
+
+/*GRF_SOC_CON11/12/13*/
+enum {
+	MCU_SRAM_BASE_BIT27_BIT12_SHIFT	= 0,
+	MCU_SRAM_BASE_BIT27_BIT12_MASK	= GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON12*/
+enum {
+	MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT  = 0,
+	MCU_EXSRAM_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON13*/
+enum {
+	MCU_EXPERI_BASE_BIT27_BIT12_SHIFT  = 0,
+	MCU_EXPERI_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
+};
+
+/*GRF_SOC_CON14*/
+enum {
+	MCU_EXPERI_BASE_BIT31_BIT28_SHIFT	= 12,
+	MCU_EXPERI_BASE_BIT31_BIT28_MASK	= GENMASK(15, 12),
+	MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT	= 8,
+	MCU_EXSRAM_BASE_BIT31_BIT28_MASK	= GENMASK(11, 8),
+	MCU_SRAM_BASE_BIT31_BIT28_SHIFT		= 4,
+	MCU_SRAM_BASE_BIT31_BIT28_MASK		= GENMASK(7, 4),
+	MCU_CODE_BASE_BIT31_BIT28_SHIFT		= 0,
+	MCU_CODE_BASE_BIT31_BIT28_MASK		= GENMASK(3, 0),
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
new file mode 100644
index 0000000..dd89cd2
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h
@@ -0,0 +1,672 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
+#define __SOC_ROCKCHIP_RK3399_GRF_H__
+
+struct rk3399_grf_regs {
+	u32 reserved[0x800];
+	u32 usb3_perf_con0;
+	u32 usb3_perf_con1;
+	u32 usb3_perf_con2;
+	u32 usb3_perf_rd_max_latency_num;
+	u32 usb3_perf_rd_latency_samp_num;
+	u32 usb3_perf_rd_latency_acc_num;
+	u32 usb3_perf_rd_axi_total_byte;
+	u32 usb3_perf_wr_axi_total_byte;
+	u32 usb3_perf_working_cnt;
+	u32 reserved1[0x103];
+	u32 usb3otg0_con0;
+	u32 usb3otg0_con1;
+	u32 reserved2[2];
+	u32 usb3otg1_con0;
+	u32 usb3otg1_con1;
+	u32 reserved3[2];
+	u32 usb3otg0_status_lat0;
+	u32 usb3otg0_status_lat1;
+	u32 usb3otg0_status_cb;
+	u32 reserved4;
+	u32 usb3otg1_status_lat0;
+	u32 usb3otg1_status_lat1;
+	u32 usb3ogt1_status_cb;
+	u32 reserved5[0x6e5];
+	u32 pcie_perf_con0;
+	u32 pcie_perf_con1;
+	u32 pcie_perf_con2;
+	u32 pcie_perf_rd_max_latency_num;
+	u32 pcie_perf_rd_latency_samp_num;
+	u32 pcie_perf_rd_laterncy_acc_num;
+	u32 pcie_perf_rd_axi_total_byte;
+	u32 pcie_perf_wr_axi_total_byte;
+	u32 pcie_perf_working_cnt;
+	u32 reserved6[0x37];
+	u32 usb20_host0_con0;
+	u32 usb20_host0_con1;
+	u32 reserved7[2];
+	u32 usb20_host1_con0;
+	u32 usb20_host1_con1;
+	u32 reserved8[2];
+	u32 hsic_con0;
+	u32 hsic_con1;
+	u32 reserved9[6];
+	u32 grf_usbhost0_status;
+	u32 grf_usbhost1_Status;
+	u32 grf_hsic_status;
+	u32 reserved10[0xc9];
+	u32 hsicphy_con0;
+	u32 reserved11[3];
+	u32 usbphy0_ctrl[26];
+	u32 reserved12[6];
+	u32 usbphy1[26];
+	u32 reserved13[0x72f];
+	u32 soc_con9;
+	u32 reserved14[0x0a];
+	u32 soc_con20;
+	u32 soc_con21;
+	u32 soc_con22;
+	u32 soc_con23;
+	u32 soc_con24;
+	u32 soc_con25;
+	u32 soc_con26;
+	u32 reserved15[0xf65];
+	u32 cpu_con[4];
+	u32 reserved16[0x1c];
+	u32 cpu_status[6];
+	u32 reserved17[0x1a];
+	u32 a53_perf_con[4];
+	u32 a53_perf_rd_mon_st;
+	u32 a53_perf_rd_mon_end;
+	u32 a53_perf_wr_mon_st;
+	u32 a53_perf_wr_mon_end;
+	u32 a53_perf_rd_max_latency_num;
+	u32 a53_perf_rd_latency_samp_num;
+	u32 a53_perf_rd_laterncy_acc_num;
+	u32 a53_perf_rd_axi_total_byte;
+	u32 a53_perf_wr_axi_total_byte;
+	u32 a53_perf_working_cnt;
+	u32 a53_perf_int_status;
+	u32 reserved18[0x31];
+	u32 a72_perf_con[4];
+	u32 a72_perf_rd_mon_st;
+	u32 a72_perf_rd_mon_end;
+	u32 a72_perf_wr_mon_st;
+	u32 a72_perf_wr_mon_end;
+	u32 a72_perf_rd_max_latency_num;
+	u32 a72_perf_rd_latency_samp_num;
+	u32 a72_perf_rd_laterncy_acc_num;
+	u32 a72_perf_rd_axi_total_byte;
+	u32 a72_perf_wr_axi_total_byte;
+	u32 a72_perf_working_cnt;
+	u32 a72_perf_int_status;
+	u32 reserved19[0x7f6];
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 reserved20[0x779];
+	u32 gpio2a_iomux;
+	union {
+		u32 iomux_spi2;
+		u32 gpio2b_iomux;
+	};
+	union {
+		u32 gpio2c_iomux;
+		u32 iomux_spi5;
+	};
+	u32 gpio2d_iomux;
+	union {
+		u32 gpio3a_iomux;
+		u32 iomux_spi0;
+	};
+	u32 gpio3b_iomux;
+	u32 gpio3c_iomux;
+	union {
+		u32 iomux_i2s0;
+		u32 gpio3d_iomux;
+	};
+	union {
+		u32 iomux_i2sclk;
+		u32 gpio4a_iomux;
+	};
+	union {
+		u32 iomux_sdmmc;
+		u32 iomux_uart2a;
+		u32 gpio4b_iomux;
+	};
+	union {
+		u32 iomux_pwm_0;
+		u32 iomux_pwm_1;
+		u32 iomux_uart2b;
+		u32 iomux_uart2c;
+		u32 iomux_edp_hotplug;
+		u32 gpio4c_iomux;
+	};
+	u32 gpio4d_iomux;
+	u32 reserved21[4];
+	u32 gpio2_p[4];
+	u32 gpio3_p[4];
+	u32 gpio4_p[4];
+	u32 reserved22[4];
+	u32 gpio2_sr[3][4];
+	u32 reserved23[4];
+	u32 gpio2_smt[3][4];
+	u32 reserved24[(0xe100 - 0xe0ec)/4 - 1];
+	u32 gpio2_e[4];
+	u32 gpio3_e[7];
+	u32 gpio4_e[5];
+	u32 reserved24a[(0xe200 - 0xe13c)/4 - 1];
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5_pcie;
+	u32 reserved25;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9_pcie;
+	u32 reserved26[0x1e];
+	u32 soc_status[6];
+	u32 reserved27[0x32];
+	u32 ddrc0_con0;
+	u32 ddrc0_con1;
+	u32 ddrc1_con0;
+	u32 ddrc1_con1;
+	u32 reserved28[0xac];
+	u32 io_vsel;
+	u32 saradc_testbit;
+	u32 tsadc_testbit_l;
+	u32 tsadc_testbit_h;
+	u32 reserved29[0x6c];
+	u32 chip_id_addr;
+	u32 reserved30[0x1f];
+	u32 fast_boot_addr;
+	u32 reserved31[0x1df];
+	u32 emmccore_con[12];
+	u32 reserved32[4];
+	u32 emmccore_status[4];
+	u32 reserved33[0x1cc];
+	u32 emmcphy_con[7];
+	u32 reserved34;
+	u32 emmcphy_status;
+};
+check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
+
+struct rk3399_pmugrf_regs {
+	union {
+		u32 iomux_pwm_3a;
+		u32 gpio0a_iomux;
+	};
+	u32 gpio0b_iomux;
+	u32 reserved0[2];
+	union {
+		u32 spi1_rxd;
+		u32 tsadc_int;
+		u32 gpio1a_iomux;
+	};
+	union {
+		u32 spi1_csclktx;
+		u32 iomux_pwm_3b;
+		u32 iomux_i2c0_sda;
+		u32 gpio1b_iomux;
+	};
+	union {
+		u32 iomux_pwm_2;
+		u32 iomux_i2c0_scl;
+		u32 gpio1c_iomux;
+	};
+	u32 gpio1d_iomux;
+	u32 reserved1[8];
+	u32 gpio0_p[2];
+	u32 reserved2[2];
+	u32 gpio1_p[4];
+	u32 reserved3[8];
+	u32 gpio0a_e;
+	u32 reserved4;
+	u32 gpio0b_e;
+	u32 reserved5[5];
+	u32 gpio1a_e;
+	u32 reserved6;
+	u32 gpio1b_e;
+	u32 reserved7;
+	u32 gpio1c_e;
+	u32 reserved8;
+	u32 gpio1d_e;
+	u32 reserved9[0x11];
+	u32 gpio0l_sr;
+	u32 reserved10;
+	u32 gpio1l_sr;
+	u32 gpio1h_sr;
+	u32 reserved11[4];
+	u32 gpio0a_smt;
+	u32 gpio0b_smt;
+	u32 reserved12[2];
+	u32 gpio1a_smt;
+	u32 gpio1b_smt;
+	u32 gpio1c_smt;
+	u32 gpio1d_smt;
+	u32 reserved13[8];
+	u32 gpio0l_he;
+	u32 reserved14;
+	u32 gpio1l_he;
+	u32 gpio1h_he;
+	u32 reserved15[4];
+	u32 soc_con0;
+	u32 reserved16[9];
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 reserved17[0x24];
+	u32 pmupvtm_con0;
+	u32 pmupvtm_con1;
+	u32 pmupvtm_status0;
+	u32 pmupvtm_status1;
+	u32 grf_osc_e;
+	u32 reserved18[0x2b];
+	u32 os_reg0;
+	u32 os_reg1;
+	u32 os_reg2;
+	u32 os_reg3;
+};
+check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
+
+struct rk3399_pmusgrf_regs {
+	u32 ddr_rgn_con[35];
+	u32 reserved[0x1fe5];
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 soc_con12;
+	u32 soc_con13;
+	u32 soc_con14;
+	u32 soc_con15;
+	u32 reserved1[3];
+	u32 soc_con19;
+	u32 soc_con20;
+	u32 soc_con21;
+	u32 soc_con22;
+	u32 reserved2[0x29];
+	u32 perilp_con[9];
+	u32 reserved4[7];
+	u32 perilp_status;
+	u32 reserved5[0xfaf];
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 reserved6[0x3e];
+	u32 pmu_con[9];
+	u32 reserved7[0x17];
+	u32 fast_boot_addr;
+	u32 reserved8[0x1f];
+	u32 efuse_prg_mask;
+	u32 efuse_read_mask;
+	u32 reserved9[0x0e];
+	u32 pmu_slv_con0;
+	u32 pmu_slv_con1;
+	u32 reserved10[0x771];
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 reserved11[8];
+	u32 soc_con16;
+	u32 soc_con17;
+	u32 soc_con18;
+	u32 reserved12[0xdd];
+	u32 slv_secure_con0;
+	u32 slv_secure_con1;
+	u32 reserved13;
+	u32 slv_secure_con2;
+	u32 slv_secure_con3;
+	u32 slv_secure_con4;
+};
+check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
+
+enum {
+	/* GRF_GPIO2A_IOMUX */
+	GRF_GPIO2A0_SEL_SHIFT   = 0,
+	GRF_GPIO2A0_SEL_MASK    = 3 << GRF_GPIO2A0_SEL_SHIFT,
+	GRF_I2C2_SDA            = 2,
+	GRF_GPIO2A1_SEL_SHIFT   = 2,
+	GRF_GPIO2A1_SEL_MASK    = 3 << GRF_GPIO2A1_SEL_SHIFT,
+	GRF_I2C2_SCL            = 2,
+	GRF_GPIO2A7_SEL_SHIFT   = 14,
+	GRF_GPIO2A7_SEL_MASK    = 3 << GRF_GPIO2A7_SEL_SHIFT,
+	GRF_I2C7_SDA            = 2,
+
+	/* GRF_GPIO2B_IOMUX */
+	GRF_GPIO2B0_SEL_SHIFT   = 0,
+	GRF_GPIO2B0_SEL_MASK    = 3 << GRF_GPIO2B0_SEL_SHIFT,
+	GRF_I2C7_SCL            = 2,
+	GRF_GPIO2B1_SEL_SHIFT	= 2,
+	GRF_GPIO2B1_SEL_MASK	= 3 << GRF_GPIO2B1_SEL_SHIFT,
+	GRF_SPI2TPM_RXD		= 1,
+	GRF_I2C6_SDA            = 2,
+	GRF_GPIO2B2_SEL_SHIFT	= 4,
+	GRF_GPIO2B2_SEL_MASK	= 3 << GRF_GPIO2B2_SEL_SHIFT,
+	GRF_SPI2TPM_TXD		= 1,
+	GRF_I2C6_SCL            = 2,
+	GRF_GPIO2B3_SEL_SHIFT	= 6,
+	GRF_GPIO2B3_SEL_MASK	= 3 << GRF_GPIO2B3_SEL_SHIFT,
+	GRF_SPI2TPM_CLK		= 1,
+	GRF_GPIO2B4_SEL_SHIFT	= 8,
+	GRF_GPIO2B4_SEL_MASK	= 3 << GRF_GPIO2B4_SEL_SHIFT,
+	GRF_SPI2TPM_CSN0	= 1,
+
+	/* GRF_GPIO2C_IOMUX */
+	GRF_GPIO2C0_SEL_SHIFT   = 0,
+	GRF_GPIO2C0_SEL_MASK    = 3 << GRF_GPIO2C0_SEL_SHIFT,
+	GRF_UART0BT_SIN         = 1,
+	GRF_GPIO2C1_SEL_SHIFT   = 2,
+	GRF_GPIO2C1_SEL_MASK    = 3 << GRF_GPIO2C1_SEL_SHIFT,
+	GRF_UART0BT_SOUT        = 1,
+	GRF_GPIO2C4_SEL_SHIFT   = 8,
+	GRF_GPIO2C4_SEL_MASK    = 3 << GRF_GPIO2C4_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_RXD     = 2,
+	GRF_GPIO2C5_SEL_SHIFT   = 10,
+	GRF_GPIO2C5_SEL_MASK    = 3 << GRF_GPIO2C5_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_TXD     = 2,
+	GRF_GPIO2C6_SEL_SHIFT   = 12,
+	GRF_GPIO2C6_SEL_MASK    = 3 << GRF_GPIO2C6_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_CLK     = 2,
+	GRF_GPIO2C7_SEL_SHIFT   = 14,
+	GRF_GPIO2C7_SEL_MASK    = 3 << GRF_GPIO2C7_SEL_SHIFT,
+	GRF_SPI5EXPPLUS_CSN0    = 2,
+
+	/* GRF_GPIO3A_IOMUX */
+	GRF_GPIO3A0_SEL_SHIFT   = 0,
+	GRF_GPIO3A0_SEL_MASK    = 3 << GRF_GPIO3A0_SEL_SHIFT,
+	GRF_MAC_TXD2            = 1,
+	GRF_GPIO3A1_SEL_SHIFT   = 2,
+	GRF_GPIO3A1_SEL_MASK    = 3 << GRF_GPIO3A1_SEL_SHIFT,
+	GRF_MAC_TXD3            = 1,
+	GRF_GPIO3A2_SEL_SHIFT   = 4,
+	GRF_GPIO3A2_SEL_MASK    = 3 << GRF_GPIO3A2_SEL_SHIFT,
+	GRF_MAC_RXD2            = 1,
+	GRF_GPIO3A3_SEL_SHIFT   = 6,
+	GRF_GPIO3A3_SEL_MASK    = 3 << GRF_GPIO3A3_SEL_SHIFT,
+	GRF_MAC_RXD3            = 1,
+	GRF_GPIO3A4_SEL_SHIFT	= 8,
+	GRF_GPIO3A4_SEL_MASK	= 3 << GRF_GPIO3A4_SEL_SHIFT,
+	GRF_MAC_TXD0            = 1,
+	GRF_SPI0NORCODEC_RXD	= 2,
+	GRF_GPIO3A5_SEL_SHIFT	= 10,
+	GRF_GPIO3A5_SEL_MASK	= 3 << GRF_GPIO3A5_SEL_SHIFT,
+	GRF_MAC_TXD1            = 1,
+	GRF_SPI0NORCODEC_TXD	= 2,
+	GRF_GPIO3A6_SEL_SHIFT	= 12,
+	GRF_GPIO3A6_SEL_MASK	= 3 << GRF_GPIO3A6_SEL_SHIFT,
+	GRF_MAC_RXD0            = 1,
+	GRF_SPI0NORCODEC_CLK	= 2,
+	GRF_GPIO3A7_SEL_SHIFT	= 14,
+	GRF_GPIO3A7_SEL_MASK	= 3 << GRF_GPIO3A7_SEL_SHIFT,
+	GRF_MAC_RXD1            = 1,
+	GRF_SPI0NORCODEC_CSN0	= 2,
+
+	/* GRF_GPIO3B_IOMUX */
+	GRF_GPIO3B0_SEL_SHIFT	= 0,
+	GRF_GPIO3B0_SEL_MASK	= 3 << GRF_GPIO3B0_SEL_SHIFT,
+	GRF_MAC_MDC             = 1,
+	GRF_SPI0NORCODEC_CSN1	= 2,
+	GRF_GPIO3B1_SEL_SHIFT	= 2,
+	GRF_GPIO3B1_SEL_MASK	= 3 << GRF_GPIO3B1_SEL_SHIFT,
+	GRF_MAC_RXDV            = 1,
+	GRF_GPIO3B3_SEL_SHIFT	= 6,
+	GRF_GPIO3B3_SEL_MASK	= 3 << GRF_GPIO3B3_SEL_SHIFT,
+	GRF_MAC_CLK             = 1,
+	GRF_GPIO3B4_SEL_SHIFT	= 8,
+	GRF_GPIO3B4_SEL_MASK	= 3 << GRF_GPIO3B4_SEL_SHIFT,
+	GRF_MAC_TXEN            = 1,
+	GRF_GPIO3B5_SEL_SHIFT	= 10,
+	GRF_GPIO3B5_SEL_MASK	= 3 << GRF_GPIO3B5_SEL_SHIFT,
+	GRF_MAC_MDIO            = 1,
+	GRF_GPIO3B6_SEL_SHIFT   = 12,
+	GRF_GPIO3B6_SEL_MASK    = 3 << GRF_GPIO3B6_SEL_SHIFT,
+	GRF_MAC_RXCLK           = 1,
+	GRF_UART3_SIN           = 2,
+	GRF_GPIO3B7_SEL_SHIFT   = 14,
+	GRF_GPIO3B7_SEL_MASK    = 3 << GRF_GPIO3B7_SEL_SHIFT,
+	GRF_UART3_SOUT          = 2,
+
+	/* GRF_GPIO3C_IOMUX */
+	GRF_GPIO3C1_SEL_SHIFT	= 2,
+	GRF_GPIO3C1_SEL_MASK	= 3 << GRF_GPIO3C1_SEL_SHIFT,
+	GRF_MAC_TXCLK           = 1,
+
+	/* GRF_GPIO4A_IOMUX */
+	GRF_GPIO4A1_SEL_SHIFT   = 2,
+	GRF_GPIO4A1_SEL_MASK    = 3 << GRF_GPIO4A1_SEL_SHIFT,
+	GRF_I2C1_SDA            = 1,
+	GRF_GPIO4A2_SEL_SHIFT   = 4,
+	GRF_GPIO4A2_SEL_MASK    = 3 << GRF_GPIO4A2_SEL_SHIFT,
+	GRF_I2C1_SCL            = 1,
+
+	/* GRF_GPIO4B_IOMUX */
+	GRF_GPIO4B0_SEL_SHIFT	= 0,
+	GRF_GPIO4B0_SEL_MASK	= 3 << GRF_GPIO4B0_SEL_SHIFT,
+	GRF_SDMMC_DATA0		= 1,
+	GRF_UART2DBGA_SIN	= 2,
+	GRF_GPIO4B1_SEL_SHIFT	= 2,
+	GRF_GPIO4B1_SEL_MASK	= 3 << GRF_GPIO4B1_SEL_SHIFT,
+	GRF_SDMMC_DATA1		= 1,
+	GRF_UART2DBGA_SOUT	= 2,
+	GRF_GPIO4B2_SEL_SHIFT	= 4,
+	GRF_GPIO4B2_SEL_MASK	= 3 << GRF_GPIO4B2_SEL_SHIFT,
+	GRF_SDMMC_DATA2		= 1,
+	GRF_GPIO4B3_SEL_SHIFT	= 6,
+	GRF_GPIO4B3_SEL_MASK	= 3 << GRF_GPIO4B3_SEL_SHIFT,
+	GRF_SDMMC_DATA3		= 1,
+	GRF_GPIO4B4_SEL_SHIFT	= 8,
+	GRF_GPIO4B4_SEL_MASK    = 3 << GRF_GPIO4B4_SEL_SHIFT,
+	GRF_SDMMC_CLKOUT        = 1,
+	GRF_GPIO4B5_SEL_SHIFT   = 10,
+	GRF_GPIO4B5_SEL_MASK    = 3 << GRF_GPIO4B5_SEL_SHIFT,
+	GRF_SDMMC_CMD           = 1,
+
+	/*  GRF_GPIO4C_IOMUX */
+	GRF_GPIO4C0_SEL_SHIFT   = 0,
+	GRF_GPIO4C0_SEL_MASK    = 3 << GRF_GPIO4C0_SEL_SHIFT,
+	GRF_UART2DGBB_SIN       = 2,
+	GRF_HDMII2C_SCL         = 3,
+	GRF_GPIO4C1_SEL_SHIFT   = 2,
+	GRF_GPIO4C1_SEL_MASK    = 3 << GRF_GPIO4C1_SEL_SHIFT,
+	GRF_UART2DGBB_SOUT      = 2,
+	GRF_HDMII2C_SDA         = 3,
+	GRF_GPIO4C2_SEL_SHIFT   = 4,
+	GRF_GPIO4C2_SEL_MASK    = 3 << GRF_GPIO4C2_SEL_SHIFT,
+	GRF_PWM_0               = 1,
+	GRF_GPIO4C3_SEL_SHIFT   = 6,
+	GRF_GPIO4C3_SEL_MASK    = 3 << GRF_GPIO4C3_SEL_SHIFT,
+	GRF_UART2DGBC_SIN       = 1,
+	GRF_GPIO4C4_SEL_SHIFT   = 8,
+	GRF_GPIO4C4_SEL_MASK    = 3 << GRF_GPIO4C4_SEL_SHIFT,
+	GRF_UART2DBGC_SOUT      = 1,
+	GRF_GPIO4C6_SEL_SHIFT   = 12,
+	GRF_GPIO4C6_SEL_MASK    = 3 << GRF_GPIO4C6_SEL_SHIFT,
+	GRF_PWM_1               = 1,
+
+	/* GRF_GPIO3A_E01 */
+	GRF_GPIO3A0_E_SHIFT = 0,
+	GRF_GPIO3A0_E_MASK = 7 << GRF_GPIO3A0_E_SHIFT,
+	GRF_GPIO3A1_E_SHIFT = 3,
+	GRF_GPIO3A1_E_MASK = 7 << GRF_GPIO3A1_E_SHIFT,
+	GRF_GPIO3A2_E_SHIFT = 6,
+	GRF_GPIO3A2_E_MASK = 7 << GRF_GPIO3A2_E_SHIFT,
+	GRF_GPIO3A3_E_SHIFT = 9,
+	GRF_GPIO3A3_E_MASK = 7 << GRF_GPIO3A3_E_SHIFT,
+	GRF_GPIO3A4_E_SHIFT = 12,
+	GRF_GPIO3A4_E_MASK = 7 << GRF_GPIO3A4_E_SHIFT,
+	GRF_GPIO3A5_E0_SHIFT = 15,
+	GRF_GPIO3A5_E0_MASK = 1 << GRF_GPIO3A5_E0_SHIFT,
+
+	/*  GRF_GPIO3A_E2 */
+	GRF_GPIO3A5_E12_SHIFT = 0,
+	GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT,
+	GRF_GPIO3A6_E_SHIFT = 2,
+	GRF_GPIO3A6_E_MASK = 7 << GRF_GPIO3A6_E_SHIFT,
+	GRF_GPIO3A7_E_SHIFT = 5,
+	GRF_GPIO3A7_E_MASK = 7 << GRF_GPIO3A7_E_SHIFT,
+
+	/* GRF_GPIO3B_E01 */
+	GRF_GPIO3B0_E_SHIFT = 0,
+	GRF_GPIO3B0_E_MASK = 7 << GRF_GPIO3B0_E_SHIFT,
+	GRF_GPIO3B1_E_SHIFT = 3,
+	GRF_GPIO3B1_E_MASK = 7 << GRF_GPIO3B1_E_SHIFT,
+	GRF_GPIO3B2_E_SHIFT = 6,
+	GRF_GPIO3B2_E_MASK = 7 << GRF_GPIO3B2_E_SHIFT,
+	GRF_GPIO3B3_E_SHIFT = 9,
+	GRF_GPIO3B3_E_MASK = 7 << GRF_GPIO3B3_E_SHIFT,
+	GRF_GPIO3B4_E_SHIFT = 12,
+	GRF_GPIO3B4_E_MASK = 7 << GRF_GPIO3B4_E_SHIFT,
+	GRF_GPIO3B5_E0_SHIFT = 15,
+	GRF_GPIO3B5_E0_MASK = 1 << GRF_GPIO3B5_E0_SHIFT,
+
+	/*  GRF_GPIO3A_E2 */
+	GRF_GPIO3B5_E12_SHIFT = 0,
+	GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT,
+	GRF_GPIO3B6_E_SHIFT = 2,
+	GRF_GPIO3B6_E_MASK = 7 << GRF_GPIO3B6_E_SHIFT,
+	GRF_GPIO3B7_E_SHIFT = 5,
+	GRF_GPIO3B7_E_MASK = 7 << GRF_GPIO3B7_E_SHIFT,
+
+	/* GRF_GPIO3C_E01 */
+	GRF_GPIO3C0_E_SHIFT = 0,
+	GRF_GPIO3C0_E_MASK = 7 << GRF_GPIO3C0_E_SHIFT,
+	GRF_GPIO3C1_E_SHIFT = 3,
+	GRF_GPIO3C1_E_MASK = 7 << GRF_GPIO3C1_E_SHIFT,
+	GRF_GPIO3C2_E_SHIFT = 6,
+	GRF_GPIO3C2_E_MASK = 7 << GRF_GPIO3C2_E_SHIFT,
+	GRF_GPIO3C3_E_SHIFT = 9,
+	GRF_GPIO3C3_E_MASK = 7 << GRF_GPIO3C3_E_SHIFT,
+	GRF_GPIO3C4_E_SHIFT = 12,
+	GRF_GPIO3C4_E_MASK = 7 << GRF_GPIO3C4_E_SHIFT,
+	GRF_GPIO3C5_E0_SHIFT = 15,
+	GRF_GPIO3C5_E0_MASK = 1 << GRF_GPIO3C5_E0_SHIFT,
+
+	/*  GRF_GPIO3C_E2 */
+	GRF_GPIO3C5_E12_SHIFT = 0,
+	GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT,
+	GRF_GPIO3C6_E_SHIFT = 2,
+	GRF_GPIO3C6_E_MASK = 7 << GRF_GPIO3C6_E_SHIFT,
+	GRF_GPIO3C7_E_SHIFT = 5,
+	GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT,
+
+	/* GRF_SOC_CON7 */
+	GRF_UART_DBG_SEL_SHIFT  = 10,
+	GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
+	GRF_UART_DBG_SEL_C      = 2,
+
+	/* GRF_SOC_CON20 */
+	GRF_DSI0_VOP_SEL_SHIFT  = 0,
+	GRF_DSI0_VOP_SEL_MASK   = 1 << GRF_DSI0_VOP_SEL_SHIFT,
+	GRF_DSI0_VOP_SEL_B      = 0,
+	GRF_DSI0_VOP_SEL_L      = 1,
+	GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6,
+	GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6,
+	GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6,
+
+	/* GRF_SOC_CON22 */
+	GRF_DPHY_TX0_RXMODE_SHIFT = 0,
+	GRF_DPHY_TX0_RXMODE_MASK  = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
+	GRF_DPHY_TX0_RXMODE_EN    = 0xb,
+	GRF_DPHY_TX0_RXMODE_DIS   = 0,
+
+	GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
+	GRF_DPHY_TX0_TXSTOPMODE_MASK  = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
+	GRF_DPHY_TX0_TXSTOPMODE_EN    = 0xc,
+	GRF_DPHY_TX0_TXSTOPMODE_DIS   = 0,
+
+	GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
+	GRF_DPHY_TX0_TURNREQUEST_MASK  =
+		0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
+	GRF_DPHY_TX0_TURNREQUEST_EN    = 0x1,
+	GRF_DPHY_TX0_TURNREQUEST_DIS   = 0,
+
+	/*  PMUGRF_GPIO0A_IOMUX */
+	PMUGRF_GPIO0A6_SEL_SHIFT        = 12,
+	PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
+	PMUGRF_PWM_3A           = 1,
+
+	/*  PMUGRF_GPIO1A_IOMUX */
+	PMUGRF_GPIO1A7_SEL_SHIFT        = 14,
+	PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
+	PMUGRF_SPI1EC_RXD       = 2,
+
+	/*  PMUGRF_GPIO1B_IOMUX */
+	PMUGRF_GPIO1B0_SEL_SHIFT        = 0,
+	PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
+	PMUGRF_SPI1EC_TXD       = 2,
+	PMUGRF_GPIO1B1_SEL_SHIFT        = 2,
+	PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
+	PMUGRF_SPI1EC_CLK       = 2,
+	PMUGRF_GPIO1B2_SEL_SHIFT        = 4,
+	PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
+	PMUGRF_SPI1EC_CSN0      = 2,
+	PMUGRF_GPIO1B3_SEL_SHIFT	= 6,
+	PMUGRF_GPIO1B3_SEL_MASK	= 3 << PMUGRF_GPIO1B3_SEL_SHIFT,
+	PMUGRF_I2C4_SDA         = 1,
+	PMUGRF_GPIO1B4_SEL_SHIFT        = 8,
+	PMUGRF_GPIO1B4_SEL_MASK	= 3 << PMUGRF_GPIO1B4_SEL_SHIFT,
+	PMUGRF_I2C4_SCL	        = 1,
+	PMUGRF_GPIO1B6_SEL_SHIFT        = 12,
+	PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
+	PMUGRF_PWM_3B           = 1,
+	PMUGRF_GPIO1B7_SEL_SHIFT        = 14,
+	PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
+	PMUGRF_I2C0PMU_SDA      = 2,
+
+	/*  PMUGRF_GPIO1C_IOMUX */
+	PMUGRF_GPIO1C0_SEL_SHIFT        = 0,
+	PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
+	PMUGRF_I2C0PMU_SCL      = 2,
+	PMUGRF_GPIO1C3_SEL_SHIFT        = 6,
+	PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
+	PMUGRF_PWM_2            = 1,
+	PMUGRF_GPIO1C4_SEL_SHIFT = 8,
+	PMUGRF_GPIO1C4_SEL_MASK = 3 << PMUGRF_GPIO1C4_SEL_SHIFT,
+	PMUGRF_I2C8PMU_SDA = 1,
+	PMUGRF_GPIO1C5_SEL_SHIFT = 10,
+	PMUGRF_GPIO1C5_SEL_MASK = 3 << PMUGRF_GPIO1C5_SEL_SHIFT,
+	PMUGRF_I2C8PMU_SCL = 1,
+};
+
+/* GRF_SOC_CON5 */
+enum {
+	RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9,
+	RK3399_GMAC_PHY_INTF_SEL_MASK  = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+	RK3399_GMAC_PHY_INTF_SEL_RMII  = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+
+	RK3399_GMAC_CLK_SEL_SHIFT = 4,
+	RK3399_GMAC_CLK_SEL_MASK  = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_125M  = (0 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_25M	  = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
+	RK3399_GMAC_CLK_SEL_2_5M  = (2 << RK3399_GMAC_CLK_SEL_SHIFT),
+};
+
+/* GRF_SOC_CON6 */
+enum {
+	RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15,
+	RK3399_RXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3399_RXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3399_TXCLK_DLY_ENA_GMAC_SHIFT	= 7,
+	RK3399_TXCLK_DLY_ENA_GMAC_MASK =
+		(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
+	RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+	RK3399_TXCLK_DLY_ENA_GMAC_ENABLE =
+		(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
+
+	RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
+	RK3399_CLK_RX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT),
+
+	RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
+	RK3399_CLK_TX_DL_CFG_GMAC_MASK =
+		(0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT),
+};
+
+#endif	/* __SOC_ROCKCHIP_RK3399_GRF_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
new file mode 100644
index 0000000..9f42fbd
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_GRF_RV1108_H
+#define _ASM_ARCH_GRF_RV1108_H
+
+#include <common.h>
+
+struct rv1108_grf {
+	u32 reserved[4];
+	u32 gpio1a_iomux;
+	u32 gpio1b_iomux;
+	u32 gpio1c_iomux;
+	u32 gpio1d_iomux;
+	u32 gpio2a_iomux;
+	u32 gpio2b_iomux;
+	u32 gpio2c_iomux;
+	u32 gpio2d_iomux;
+	u32 gpio3a_iomux;
+	u32 gpio3b_iomux;
+	u32 gpio3c_iomux;
+	u32 gpio3d_iomux;
+	u32 reserved1[52];
+	u32 gpio1a_pull;
+	u32 gpio1b_pull;
+	u32 gpio1c_pull;
+	u32 gpio1d_pull;
+	u32 gpio2a_pull;
+	u32 gpio2b_pull;
+	u32 gpio2c_pull;
+	u32 gpio2d_pull;
+	u32 gpio3a_pull;
+	u32 gpio3b_pull;
+	u32 gpio3c_pull;
+	u32 gpio3d_pull;
+	u32 reserved2[52];
+	u32 gpio1a_drv;
+	u32 gpio1b_drv;
+	u32 gpio1c_drv;
+	u32 gpio1d_drv;
+	u32 gpio2a_drv;
+	u32 gpio2b_drv;
+	u32 gpio2c_drv;
+	u32 gpio2d_drv;
+	u32 gpio3a_drv;
+	u32 gpio3b_drv;
+	u32 gpio3c_drv;
+	u32 gpio3d_drv;
+	u32 reserved3[50];
+	u32 gpio1l_sr;
+	u32 gpio1h_sr;
+	u32 gpio2l_sr;
+	u32 gpio2h_sr;
+	u32 gpio3l_sr;
+	u32 gpio3h_sr;
+	u32 reserved4[26];
+	u32 gpio1l_smt;
+	u32 gpio1h_smt;
+	u32 gpio2l_smt;
+	u32 gpio2h_smt;
+	u32 gpio3l_smt;
+	u32 gpio3h_smt;
+	u32 reserved5[24];
+	u32 soc_con0;
+	u32 soc_con1;
+	u32 soc_con2;
+	u32 soc_con3;
+	u32 soc_con4;
+	u32 soc_con5;
+	u32 soc_con6;
+	u32 soc_con7;
+	u32 soc_con8;
+	u32 soc_con9;
+	u32 soc_con10;
+	u32 soc_con11;
+	u32 reserved6[20];
+	u32 soc_status0;
+	u32 soc_status1;
+	u32 reserved7[30];
+	u32 cpu_con0;
+	u32 cpu_con1;
+	u32 reserved8[30];
+	u32 os_reg0;
+	u32 os_reg1;
+	u32 os_reg2;
+	u32 os_reg3;
+	u32 reserved9[29];
+	u32 ddr_status;
+	u32 reserved10[30];
+	u32 sig_det_con;
+	u32 reserved11[3];
+	u32 sig_det_status;
+	u32 reserved12[3];
+	u32 sig_det_clr;
+	u32 reserved13[23];
+	u32 host_con0;
+	u32 host_con1;
+	u32 reserved14[2];
+	u32 dma_con0;
+	u32 dma_con1;
+	u32 reserved15[59];
+	u32 uoc_status;
+	u32 reserved16[2];
+	u32 host_status;
+	u32 reserved17[59];
+	u32 gmac_con0;
+	u32 reserved18[191];
+	u32 chip_id;
+};
+
+check_member(rv1108_grf, chip_id, 0x0c00);
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h
new file mode 100644
index 0000000..62e8bed
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/hardware.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define RK_CLRSETBITS(clr, set)		((((clr) | (set)) << 16) | (set))
+#define RK_SETBITS(set)			RK_CLRSETBITS(0, set)
+#define RK_CLRBITS(clr)			RK_CLRSETBITS(clr, 0)
+
+#define rk_clrsetreg(addr, clr, set)	\
+				writel(((clr) | (set)) << 16 | (set), addr)
+#define rk_clrreg(addr, clr)		writel((clr) << 16, addr)
+#define rk_setreg(addr, set)		writel((set) << 16 | (set), addr)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/i2c.h b/arch/arm/include/asm/arch-rockchip/i2c.h
new file mode 100644
index 0000000..b0e1936
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/i2c.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ */
+
+#ifndef __ASM_ARCH_I2C_H
+#define __ASM_ARCH_I2C_H
+
+struct i2c_regs {
+	u32 con;
+	u32 clkdiv;
+	u32 mrxaddr;
+	u32 mrxraddr;
+	u32 mtxcnt;
+	u32 mrxcnt;
+	u32 ien;
+	u32 ipd;
+	u32 fcnt;
+	u32 reserved0[0x37];
+	u32 txdata[8];
+	u32 reserved1[0x38];
+	u32 rxdata[8];
+};
+
+/* Control register */
+#define I2C_CON_EN		(1 << 0)
+#define I2C_CON_MOD(mod)	((mod) << 1)
+#define I2C_MODE_TX		0x00
+#define I2C_MODE_TRX		0x01
+#define I2C_MODE_RX		0x02
+#define I2C_MODE_RRX		0x03
+#define I2C_CON_MASK		(3 << 1)
+
+#define I2C_CON_START		(1 << 3)
+#define I2C_CON_STOP		(1 << 4)
+#define I2C_CON_LASTACK		(1 << 5)
+#define I2C_CON_ACTACK		(1 << 6)
+
+/* Clock dividor register */
+#define I2C_CLKDIV_VAL(divl, divh) \
+	(((divl) & 0xffff) | (((divh) << 16) & 0xffff0000))
+
+/* the slave address accessed  for master rx mode */
+#define I2C_MRXADDR_SET(vld, addr)	(((vld) << 24) | (addr))
+
+/* the slave register address accessed  for master rx mode */
+#define I2C_MRXRADDR_SET(vld, raddr)	(((vld) << 24) | (raddr))
+
+/* interrupt enable register */
+#define I2C_BTFIEN		(1 << 0)
+#define I2C_BRFIEN		(1 << 1)
+#define I2C_MBTFIEN		(1 << 2)
+#define I2C_MBRFIEN		(1 << 3)
+#define I2C_STARTIEN		(1 << 4)
+#define I2C_STOPIEN		(1 << 5)
+#define I2C_NAKRCVIEN		(1 << 6)
+
+/* interrupt pending register */
+#define I2C_BTFIPD              (1 << 0)
+#define I2C_BRFIPD              (1 << 1)
+#define I2C_MBTFIPD             (1 << 2)
+#define I2C_MBRFIPD             (1 << 3)
+#define I2C_STARTIPD            (1 << 4)
+#define I2C_STOPIPD             (1 << 5)
+#define I2C_NAKRCVIPD           (1 << 6)
+#define I2C_IPD_ALL_CLEAN       0x7f
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h b/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h
new file mode 100644
index 0000000..0f00df6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/lvds_rk3288.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_LVDS_RK3288_H
+#define _ASM_ARCH_LVDS_RK3288_H
+
+#define RK3288_LVDS_CH0_REG0			0x00
+#define RK3288_LVDS_CH0_REG0_LVDS_EN		BIT(7)
+#define RK3288_LVDS_CH0_REG0_TTL_EN		BIT(6)
+#define RK3288_LVDS_CH0_REG0_LANECK_EN		BIT(5)
+#define RK3288_LVDS_CH0_REG0_LANE4_EN		BIT(4)
+#define RK3288_LVDS_CH0_REG0_LANE3_EN		BIT(3)
+#define RK3288_LVDS_CH0_REG0_LANE2_EN		BIT(2)
+#define RK3288_LVDS_CH0_REG0_LANE1_EN		BIT(1)
+#define RK3288_LVDS_CH0_REG0_LANE0_EN		BIT(0)
+
+#define RK3288_LVDS_CH0_REG1			0x04
+#define RK3288_LVDS_CH0_REG1_LANECK_BIAS	BIT(5)
+#define RK3288_LVDS_CH0_REG1_LANE4_BIAS		BIT(4)
+#define RK3288_LVDS_CH0_REG1_LANE3_BIAS		BIT(3)
+#define RK3288_LVDS_CH0_REG1_LANE2_BIAS		BIT(2)
+#define RK3288_LVDS_CH0_REG1_LANE1_BIAS		BIT(1)
+#define RK3288_LVDS_CH0_REG1_LANE0_BIAS		BIT(0)
+
+#define RK3288_LVDS_CH0_REG2			0x08
+#define RK3288_LVDS_CH0_REG2_RESERVE_ON		BIT(7)
+#define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE	BIT(6)
+#define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE	BIT(5)
+#define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE	BIT(4)
+#define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE	BIT(3)
+#define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE	BIT(2)
+#define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE	BIT(1)
+#define RK3288_LVDS_CH0_REG2_PLL_FBDIV8		BIT(0)
+
+#define RK3288_LVDS_CH0_REG3			0x0c
+#define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK	0xff
+
+#define RK3288_LVDS_CH0_REG4			0x10
+#define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE	BIT(5)
+#define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE	BIT(4)
+#define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE	BIT(3)
+#define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE	BIT(2)
+#define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE	BIT(1)
+#define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE	BIT(0)
+
+#define RK3288_LVDS_CH0_REG5			0x14
+#define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA	BIT(5)
+#define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA	BIT(4)
+#define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA	BIT(3)
+#define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA	BIT(2)
+#define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA	BIT(1)
+#define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA	BIT(0)
+
+#define RK3288_LVDS_CFG_REGC			0x30
+#define RK3288_LVDS_CFG_REGC_PLL_ENABLE		0x00
+#define RK3288_LVDS_CFG_REGC_PLL_DISABLE	0xff
+
+#define RK3288_LVDS_CH0_REGD			0x34
+#define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK	0x1f
+
+#define RK3288_LVDS_CH0_REG20			0x80
+#define RK3288_LVDS_CH0_REG20_MSB		0x45
+#define RK3288_LVDS_CH0_REG20_LSB		0x44
+
+#define RK3288_LVDS_CFG_REG21			0x84
+#define RK3288_LVDS_CFG_REG21_TX_ENABLE		0x92
+#define RK3288_LVDS_CFG_REG21_TX_DISABLE	0x00
+
+/* fbdiv value is split over 2 registers, with bit8 in reg2 */
+#define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \
+		(_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)
+#define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \
+		(_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK)
+#define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \
+		(_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK)
+
+#define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT	BIT(3)
+
+#define LVDS_FMT_MASK			(7 << 16)
+#define LVDS_MSB			(1 << 3)
+#define LVDS_DUAL			(1 << 4)
+#define LVDS_FMT_1			(1 << 5)
+#define LVDS_TTL_EN			(1 << 6)
+#define LVDS_START_PHASE_RST_1		(1 << 7)
+#define LVDS_DCLK_INV			(1 << 8)
+#define LVDS_CH0_EN			(1 << 11)
+#define LVDS_CH1_EN			(1 << 12)
+#define LVDS_PWRDN			(1 << 15)
+
+#define LVDS_24BIT		(0 << 1)
+#define LVDS_18BIT		(1 << 1)
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/misc.h b/arch/arm/include/asm/arch-rockchip/misc.h
new file mode 100644
index 0000000..b6b03c9
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/misc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RK3399: Architecture common definitions
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ *      Rohan Garg <rohan.garg@collabora.com>
+ */
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+			      const u32 cpuid_length,
+			      u8 *cpuid);
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length);
+int rockchip_setup_macaddr(void);
diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h
new file mode 100644
index 0000000..2191b7d
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef _ASM_ARCH_PERIPH_H
+#define _ASM_ARCH_PERIPH_H
+
+/*
+ * The peripherals supported by the hardware. This is used to specify clocks
+ * and pinctrl settings. Some SoCs will not support all of these, but it
+ * provides a common reference for common drivers to use.
+ */
+enum periph_id {
+	PERIPH_ID_PWM0,
+	PERIPH_ID_PWM1,
+	PERIPH_ID_PWM2,
+	PERIPH_ID_PWM3,
+	PERIPH_ID_PWM4,
+	PERIPH_ID_I2C0,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_I2C4,
+	PERIPH_ID_I2C5,
+	PERIPH_ID_I2C6,
+	PERIPH_ID_I2C7,
+	PERIPH_ID_I2C8,
+	PERIPH_ID_SPI0,
+	PERIPH_ID_SPI1,
+	PERIPH_ID_SPI2,
+	PERIPH_ID_SPI3,
+	PERIPH_ID_SPI4,
+	PERIPH_ID_SPI5,
+	PERIPH_ID_UART0,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+	PERIPH_ID_UART3,
+	PERIPH_ID_UART4,
+	PERIPH_ID_LCDC0,
+	PERIPH_ID_LCDC1,
+	PERIPH_ID_SDMMC0,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_GMAC,
+	PERIPH_ID_SFC,
+	PERIPH_ID_I2S,
+
+	PERIPH_ID_COUNT,
+
+	/* Some aliases */
+	PERIPH_ID_EMMC = PERIPH_ID_SDMMC0,
+	PERIPH_ID_SDCARD = PERIPH_ID_SDMMC1,
+	PERIPH_ID_UART_BT = PERIPH_ID_UART0,
+	PERIPH_ID_UART_BB = PERIPH_ID_UART1,
+	PERIPH_ID_UART_DBG = PERIPH_ID_UART2,
+	PERIPH_ID_UART_GPS = PERIPH_ID_UART3,
+	PERIPH_ID_UART_EXP = PERIPH_ID_UART4,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h
new file mode 100644
index 0000000..f7b9a06
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3188.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
+ */
+
+#ifndef _ASM_ARCH_PMU_RK3188_H
+#define _ASM_ARCH_PMU_RK3188_H
+
+struct rk3188_pmu {
+	u32 wakeup_cfg[2];
+	u32 pwrdn_con;
+	u32 pwrdn_st;
+
+	u32 int_con;
+	u32 int_st;
+	u32 misc_con;
+
+	u32 osc_cnt;
+	u32 pll_cnt;
+	u32 pmu_cnt;
+	u32 ddrio_pwron_cnt;
+	u32 wakeup_rst_clr_cnt;
+	u32 scu_pwrdwn_cnt;
+	u32 scu_pwrup_cnt;
+	u32 misc_con1;
+	u32 gpio0_con;
+
+	u32 sys_reg[4];
+	u32 reserved0[4];
+	u32 stop_int_dly;
+	u32 gpio0_p[2];
+};
+check_member(rk3188_pmu, gpio0_p[1], 0x0068);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h
new file mode 100644
index 0000000..8553d2e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3288.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_PMU_RK3288_H
+#define _ASM_ARCH_PMU_RK3288_H
+
+struct rk3288_pmu {
+	u32 wakeup_cfg[2];
+	u32 pwrdn_con;
+	u32 pwrdn_st;
+
+	u32 idle_req;
+	u32 idle_st;
+	u32 pwrmode_con;
+	u32 pwr_state;
+
+	u32 osc_cnt;
+	u32 pll_cnt;
+	u32 stabl_cnt;
+	u32 ddr0io_pwron_cnt;
+
+	u32 ddr1io_pwron_cnt;
+	u32 core_pwrdn_cnt;
+	u32 core_pwrup_cnt;
+	u32 gpu_pwrdn_cnt;
+
+	u32 gpu_pwrup_cnt;
+	u32 wakeup_rst_clr_cnt;
+	u32 sft_con;
+	u32 ddr_sref_st;
+
+	u32 int_con;
+	u32 int_st;
+	u32 boot_addr_sel;
+	u32 grf_con;
+
+	u32 gpio_sr;
+	u32 gpio0pull[3];
+
+	u32 gpio0drv[3];
+	u32 gpio_op;
+
+	u32 gpio0_sel18;	/* 0x80 */
+	u32 gpio0_iomux[4];	/* a, b, c, d */
+	u32 sys_reg[4];
+};
+check_member(rk3288_pmu, sys_reg[3], 0x00a0);
+
+enum {
+	PMU_GPIO0_A	= 0,
+	PMU_GPIO0_B,
+	PMU_GPIO0_C,
+	PMU_GPIO0_D,
+};
+
+/* PMU_GPIO0_B_IOMUX */
+enum {
+	GPIO0_B7_SHIFT		= 14,
+	GPIO0_B7_MASK		= 1,
+	GPIO0_B7_GPIOB7		= 0,
+	GPIO0_B7_I2C0PMU_SDA,
+
+	GPIO0_B5_SHIFT		= 10,
+	GPIO0_B5_MASK		= 1,
+	GPIO0_B5_GPIOB5		= 0,
+	GPIO0_B5_CLK_27M,
+
+	GPIO0_B2_SHIFT		= 4,
+	GPIO0_B2_MASK		= 1,
+	GPIO0_B2_GPIOB2		= 0,
+	GPIO0_B2_TSADC_INT,
+};
+
+/* PMU_GPIO0_C_IOMUX */
+enum {
+	GPIO0_C1_SHIFT		= 2,
+	GPIO0_C1_MASK		= 3,
+	GPIO0_C1_GPIOC1		= 0,
+	GPIO0_C1_TEST_CLKOUT,
+	GPIO0_C1_CLKT1_27M,
+
+	GPIO0_C0_SHIFT		= 0,
+	GPIO0_C0_MASK		= 1,
+	GPIO0_C0_GPIOC0		= 0,
+	GPIO0_C0_I2C0PMU_SCL,
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
new file mode 100644
index 0000000..f1096dc
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__
+#define __SOC_ROCKCHIP_RK3399_PMU_H__
+
+struct rk3399_pmu_regs {
+	u32 pmu_wakeup_cfg[5];
+	u32 pmu_pwrdn_con;
+	u32 pmu_pwrdn_st;
+	u32 pmu_pll_con;
+	u32 pmu_pwrmode_con;
+	u32 pmu_sft_con;
+	u32 pmu_int_con;
+	u32 pmu_int_st;
+	u32 pmu_gpio0_pos_int_con;
+	u32 pmu_gpio0_net_int_con;
+	u32 pmu_gpio1_pos_int_con;
+	u32 pmu_gpio1_net_int_con;
+	u32 pmu_gpio0_pos_int_st;
+	u32 pmu_gpio0_net_int_st;
+	u32 pmu_gpio1_pos_int_st;
+	u32 pmu_gpio1_net_int_st;
+	u32 pmu_pwrdn_inten;
+	u32 pmu_pwrdn_status;
+	u32 pmu_wakeup_status;
+	u32 pmu_bus_clr;
+	u32 pmu_bus_idle_req;
+	u32 pmu_bus_idle_st;
+	u32 pmu_bus_idle_ack;
+	u32 pmu_cci500_con;
+	u32 pmu_adb400_con;
+	u32 pmu_adb400_st;
+	u32 pmu_power_st;
+	u32 pmu_core_pwr_st;
+	u32 pmu_osc_cnt;
+	u32 pmu_plllock_cnt;
+	u32 pmu_pllrst_cnt;
+	u32 pmu_stable_cnt;
+	u32 pmu_ddrio_pwron_cnt;
+	u32 pmu_wakeup_rst_clr_cnt;
+	u32 pmu_ddr_sref_st;
+	u32 pmu_scu_l_pwrdn_cnt;
+	u32 pmu_scu_l_pwrup_cnt;
+	u32 pmu_scu_b_pwrdn_cnt;
+	u32 pmu_scu_b_pwrup_cnt;
+	u32 pmu_gpu_pwrdn_cnt;
+	u32 pmu_gpu_pwrup_cnt;
+	u32 pmu_center_pwrdn_cnt;
+	u32 pmu_center_pwrup_cnt;
+	u32 pmu_timeout_cnt;
+	u32 pmu_cpu0apm_con;
+	u32 pmu_cpu1apm_con;
+	u32 pmu_cpu2apm_con;
+	u32 pmu_cpu3apm_con;
+	u32 pmu_cpu0bpm_con;
+	u32 pmu_cpu1bpm_con;
+	u32 pmu_noc_auto_ena;
+	u32 pmu_pwrdn_con1;
+	u32 reserved0[0x4];
+	u32 pmu_sys_reg_reg0;
+	u32 pmu_sys_reg_reg1;
+	u32 pmu_sys_reg_reg2;
+	u32 pmu_sys_reg_reg3;
+};
+
+check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc);
+
+#endif	/* __SOC_ROCKCHIP_RK3399_PMU_H__ */
diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h
new file mode 100644
index 0000000..b5178db
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/pwm.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Google, Inc
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ */
+
+#ifndef _ASM_ARCH_PWM_H
+#define _ASM_ARCH_PWM_H
+
+struct rk3288_pwm {
+	u32 cnt;
+	u32 period_hpr;
+	u32 duty_lpr;
+	u32 ctrl;
+};
+check_member(rk3288_pwm, ctrl, 0xc);
+
+#define RK_PWM_DISABLE                  (0 << 0)
+#define RK_PWM_ENABLE                   (1 << 0)
+
+#define PWM_ONE_SHOT                    (0 << 1)
+#define PWM_CONTINUOUS                  (1 << 1)
+#define RK_PWM_CAPTURE                  (1 << 2)
+
+#define PWM_DUTY_POSTIVE                (1 << 3)
+#define PWM_DUTY_NEGATIVE               (0 << 3)
+#define PWM_DUTY_MASK			(1 << 3)
+
+#define PWM_INACTIVE_POSTIVE            (1 << 4)
+#define PWM_INACTIVE_NEGATIVE           (0 << 4)
+#define PWM_INACTIVE_MASK		(1 << 4)
+
+#define PWM_OUTPUT_LEFT                 (0 << 5)
+#define PWM_OUTPUT_CENTER               (1 << 5)
+
+#define PWM_LP_ENABLE                   (1 << 8)
+#define PWM_LP_DISABLE                  (0 << 8)
+
+#define PWM_SEL_SCALE_CLK		(1 << 9)
+#define PWM_SEL_SRC_CLK			(0 << 9)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/qos_rk3288.h b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h
new file mode 100644
index 0000000..c24b090
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Rockchip Inc.
+ */
+#ifndef _ASM_ARCH_QOS_RK3288_H
+#define _ASM_ARCH_QOS_RK3288_H
+
+#define PRIORITY_HIGH_SHIFT	2
+#define PRIORITY_LOW_SHIFT	0
+
+#define CPU_AXI_QOS_PRIORITY    0x08
+
+#define VIO0_VOP_QOS            0xffad0400
+#define VIO1_VOP_QOS            0xffad0000
+#define VIO1_ISP_R_QOS          0xffad0900
+#define VIO1_ISP_W0_QOS         0xffad0100
+#define VIO1_ISP_W1_QOS         0xffad0180
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h b/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
new file mode 100644
index 0000000..c13957a
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/rockchip_mipi_dsi.h
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ * author: Eric Gao <eric.gao@rock-chips.com>
+ */
+
+#ifndef ROCKCHIP_MIPI_DSI_H
+#define ROCKCHIP_MIPI_DSI_H
+
+/*
+ * All these mipi controller register declaration provide reg address offset,
+ * bits width, bit offset for a specified register bits. With these message, we
+ * can set or clear every bits individually for a 32bit widthregister. We use
+ * DSI_HOST_BITS macro definition to combinat these message using the following
+ * format: val(32bit) = addr(16bit) | width(8bit) | offest(8bit)
+ * For example:
+ *    #define SHUTDOWNZ           DSI_HOST_BITS(0x004, 1, 0)
+ * means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's reg addr
+ * offset is 0x004.The conbinat result  = (0x004 << 16) | (1 << 8) | 0
+ */
+#define ADDR_SHIFT 16
+#define BITS_SHIFT 8
+#define OFFSET_SHIFT 0
+#define DSI_HOST_BITS(addr, bits, bit_offset) \
+((addr << ADDR_SHIFT) | (bits << BITS_SHIFT) | (bit_offset << OFFSET_SHIFT))
+
+/* DWC_DSI_VERSION_0x3133302A */
+#define VERSION				DSI_HOST_BITS(0x000, 32, 0)
+#define SHUTDOWNZ			DSI_HOST_BITS(0x004, 1, 0)
+#define TO_CLK_DIVISION		DSI_HOST_BITS(0x008, 8, 8)
+#define TX_ESC_CLK_DIVISION	DSI_HOST_BITS(0x008, 8, 0)
+#define DPI_VCID			DSI_HOST_BITS(0x00c, 2, 0)
+#define EN18_LOOSELY		DSI_HOST_BITS(0x010, 1, 8)
+#define DPI_COLOR_CODING	DSI_HOST_BITS(0x010, 4, 0)
+#define COLORM_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 4)
+#define SHUTD_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 3)
+#define HSYNC_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 2)
+#define VSYNC_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 1)
+#define DATAEN_ACTIVE_LOW	DSI_HOST_BITS(0x014, 1, 0)
+#define OUTVACT_LPCMD_TIME	DSI_HOST_BITS(0x018, 8, 16)
+#define INVACT_LPCMD_TIME	DSI_HOST_BITS(0x018, 8, 0)
+#define CRC_RX_EN			DSI_HOST_BITS(0x02c, 1, 4)
+#define ECC_RX_EN			DSI_HOST_BITS(0x02c, 1, 3)
+#define BTA_EN				DSI_HOST_BITS(0x02c, 1, 2)
+#define EOTP_RX_EN			DSI_HOST_BITS(0x02c, 1, 1)
+#define EOTP_TX_EN			DSI_HOST_BITS(0x02c, 1, 0)
+#define GEN_VID_RX			DSI_HOST_BITS(0x030, 2, 0)
+#define CMD_VIDEO_MODE		DSI_HOST_BITS(0x034, 1, 0)
+#define VPG_ORIENTATION		DSI_HOST_BITS(0x038, 1, 24)
+#define VPG_MODE			DSI_HOST_BITS(0x038, 1, 20)
+#define VPG_EN				DSI_HOST_BITS(0x038, 1, 16)
+#define LP_CMD_EN			DSI_HOST_BITS(0x038, 1, 15)
+#define FRAME_BTA_ACK_EN	DSI_HOST_BITS(0x038, 1, 14)
+#define LP_HFP_EN			DSI_HOST_BITS(0x038, 1, 13)
+#define LP_HBP_EN			DSI_HOST_BITS(0x038, 1, 12)
+#define LP_VACT_EN			DSI_HOST_BITS(0x038, 1, 11)
+#define LP_VFP_EN			DSI_HOST_BITS(0x038, 1, 10)
+#define LP_VBP_EN			DSI_HOST_BITS(0x038, 1, 9)
+#define LP_VSA_EN			DSI_HOST_BITS(0x038, 1, 8)
+#define VID_MODE_TYPE		DSI_HOST_BITS(0x038, 2, 0)
+#define VID_PKT_SIZE		DSI_HOST_BITS(0x03c, 14, 0)
+#define NUM_CHUNKS			DSI_HOST_BITS(0x040, 13, 0)
+#define NULL_PKT_SIZE		DSI_HOST_BITS(0x044, 13, 0)
+#define VID_HSA_TIME		DSI_HOST_BITS(0x048, 12, 0)
+#define VID_HBP_TIME		DSI_HOST_BITS(0x04c, 12, 0)
+#define VID_HLINE_TIME		DSI_HOST_BITS(0x050, 15, 0)
+#define VID_VSA_LINES		DSI_HOST_BITS(0x054, 10, 0)
+#define VID_VBP_LINES		DSI_HOST_BITS(0x058, 10, 0)
+#define VID_VFP_LINES		DSI_HOST_BITS(0x05c, 10, 0)
+#define VID_ACTIVE_LINES	DSI_HOST_BITS(0x060, 14, 0)
+#define EDPI_CMD_SIZE		DSI_HOST_BITS(0x064, 16, 0)
+#define MAX_RD_PKT_SIZE		DSI_HOST_BITS(0x068, 1, 24)
+#define DCS_LW_TX			DSI_HOST_BITS(0x068, 1, 19)
+#define DCS_SR_0P_TX		DSI_HOST_BITS(0x068, 1, 18)
+#define DCS_SW_1P_TX		DSI_HOST_BITS(0x068, 1, 17)
+#define DCS_SW_0P_TX		DSI_HOST_BITS(0x068, 1, 16)
+#define GEN_LW_TX			DSI_HOST_BITS(0x068, 1, 14)
+#define GEN_SR_2P_TX		DSI_HOST_BITS(0x068, 1, 13)
+#define GEN_SR_1P_TX		DSI_HOST_BITS(0x068, 1, 12)
+#define GEN_SR_0P_TX		DSI_HOST_BITS(0x068, 1, 11)
+#define GEN_SW_2P_TX		DSI_HOST_BITS(0x068, 1, 10)
+#define GEN_SW_1P_TX		DSI_HOST_BITS(0x068, 1, 9)
+#define GEN_SW_0P_TX		DSI_HOST_BITS(0x068, 1, 8)
+#define ACK_RQST_EN			DSI_HOST_BITS(0x068, 1, 1)
+#define TEAR_FX_EN			DSI_HOST_BITS(0x068, 1, 0)
+#define GEN_WC_MSBYTE		DSI_HOST_BITS(0x06c, 14, 16)
+#define GEN_WC_LSBYTE		DSI_HOST_BITS(0x06c, 8, 8)
+#define GEN_VC				DSI_HOST_BITS(0x06c, 2, 6)
+#define GEN_DT				DSI_HOST_BITS(0x06c, 6, 0)
+#define GEN_PLD_DATA		DSI_HOST_BITS(0x070, 32, 0)
+#define GEN_RD_CMD_BUSY		DSI_HOST_BITS(0x074, 1, 6)
+#define GEN_PLD_R_FULL		DSI_HOST_BITS(0x074, 1, 5)
+#define GEN_PLD_R_EMPTY		DSI_HOST_BITS(0x074, 1, 4)
+#define GEN_PLD_W_FULL		DSI_HOST_BITS(0x074, 1, 3)
+#define GEN_PLD_W_EMPTY		DSI_HOST_BITS(0x074, 1, 2)
+#define GEN_CMD_FULL		DSI_HOST_BITS(0x074, 1, 1)
+#define GEN_CMD_EMPTY		DSI_HOST_BITS(0x074, 1, 0)
+#define HSTX_TO_CNT			DSI_HOST_BITS(0x078, 16, 16)
+#define LPRX_TO_CNT			DSI_HOST_BITS(0x078, 16, 0)
+#define HS_RD_TO_CNT		DSI_HOST_BITS(0x07c, 16, 0)
+#define LP_RD_TO_CNT		DSI_HOST_BITS(0x080, 16, 0)
+#define PRESP_TO_MODE		DSI_HOST_BITS(0x084, 1, 24)
+#define HS_WR_TO_CNT		DSI_HOST_BITS(0x084, 16, 0)
+#define LP_WR_TO_CNT		DSI_HOST_BITS(0x088, 16, 0)
+#define BTA_TO_CNT			DSI_HOST_BITS(0x08c, 16, 0)
+#define AUTO_CLKLANE_CTRL	DSI_HOST_BITS(0x094, 1, 1)
+#define PHY_TXREQUESTCLKHS	DSI_HOST_BITS(0x094, 1, 0)
+#define PHY_HS2LP_TIME_CLK_LANE	DSI_HOST_BITS(0x098, 10, 16)
+#define PHY_HS2HS_TIME_CLK_LANE	DSI_HOST_BITS(0x098, 10, 0)
+#define PHY_HS2LP_TIME		DSI_HOST_BITS(0x09c, 8, 24)
+#define PHY_LP2HS_TIME		DSI_HOST_BITS(0x09c, 8, 16)
+#define MAX_RD_TIME			DSI_HOST_BITS(0x09c, 15, 0)
+#define PHY_FORCEPLL		DSI_HOST_BITS(0x0a0, 1, 3)
+#define PHY_ENABLECLK		DSI_HOST_BITS(0x0a0, 1, 2)
+#define PHY_RSTZ			DSI_HOST_BITS(0x0a0, 1, 1)
+#define PHY_SHUTDOWNZ		DSI_HOST_BITS(0x0a0, 1, 0)
+#define PHY_STOP_WAIT_TIME	DSI_HOST_BITS(0x0a4, 8, 8)
+#define N_LANES				DSI_HOST_BITS(0x0a4, 2, 0)
+#define PHY_TXEXITULPSLAN	DSI_HOST_BITS(0x0a8, 1, 3)
+#define PHY_TXREQULPSLAN	DSI_HOST_BITS(0x0a8, 1, 2)
+#define PHY_TXEXITULPSCLK	DSI_HOST_BITS(0x0a8, 1, 1)
+#define PHY_TXREQULPSCLK	DSI_HOST_BITS(0x0a8, 1, 0)
+#define PHY_TX_TRIGGERS		DSI_HOST_BITS(0x0ac, 4, 0)
+#define PHYSTOPSTATECLKLANE	DSI_HOST_BITS(0x0b0, 1, 2)
+#define PHYLOCK				DSI_HOST_BITS(0x0b0, 1, 0)
+#define PHY_TESTCLK			DSI_HOST_BITS(0x0b4, 1, 1)
+#define PHY_TESTCLR			DSI_HOST_BITS(0x0b4, 1, 0)
+#define PHY_TESTEN			DSI_HOST_BITS(0x0b8, 1, 16)
+#define PHY_TESTDOUT		DSI_HOST_BITS(0x0b8, 8, 8)
+#define PHY_TESTDIN			DSI_HOST_BITS(0x0b8, 8, 0)
+#define PHY_TEST_CTRL1		DSI_HOST_BITS(0x0b8, 17, 0)
+#define PHY_TEST_CTRL0		DSI_HOST_BITS(0x0b4, 2, 0)
+#define INT_ST0				DSI_HOST_BITS(0x0bc, 21, 0)
+#define INT_ST1				DSI_HOST_BITS(0x0c0, 18, 0)
+#define INT_MKS0			DSI_HOST_BITS(0x0c4, 21, 0)
+#define INT_MKS1			DSI_HOST_BITS(0x0c8, 18, 0)
+#define INT_FORCE0			DSI_HOST_BITS(0x0d8, 21, 0)
+#define INT_FORCE1			DSI_HOST_BITS(0x0dc, 18, 0)
+
+#define CODE_HS_RX_CLOCK	0x34
+#define CODE_HS_RX_LANE0	0x44
+#define CODE_HS_RX_LANE1	0x54
+#define CODE_HS_RX_LANE2	0x84
+#define CODE_HS_RX_LANE3	0x94
+
+#define CODE_PLL_VCORANGE_VCOCAP	0x10
+#define CODE_PLL_CPCTRL	0x11
+#define CODE_PLL_LPF_CP 0x12
+#define CODE_PLL_INPUT_DIV_RAT	0x17
+#define CODE_PLL_LOOP_DIV_RAT	0x18
+#define CODE_PLL_INPUT_LOOP_DIV_RAT	0x19
+#define CODE_BANDGAP_BIAS_CTRL	0x20
+#define CODE_TERMINATION_CTRL	0x21
+#define CODE_AFE_BIAS_BANDGAP_ANOLOG 0x22
+
+#define CODE_HSTXDATALANEREQUSETSTATETIME	0x70
+#define CODE_HSTXDATALANEPREPARESTATETIME	0x71
+#define CODE_HSTXDATALANEHSZEROSTATETIME	0x72
+
+/* Transmission mode between vop and MIPI controller */
+enum vid_mode_type_t {
+	NON_BURST_SYNC_PLUSE = 0,
+	NON_BURST_SYNC_EVENT,
+	BURST_MODE,
+};
+
+enum cmd_video_mode {
+	VIDEO_MODE = 0,
+	CMD_MODE,
+};
+
+/* Indicate MIPI DSI color mode */
+enum dpi_color_coding {
+	DPI_16BIT_CFG_1 = 0,
+	DPI_16BIT_CFG_2,
+	DPI_16BIT_CFG_3,
+	DPI_18BIT_CFG_1,
+	DPI_18BIT_CFG_2,
+	DPI_24BIT,
+	DPI_20BIT_YCBCR_422_LP,
+	DPI_24BIT_YCBCR_422,
+	DPI_16BIT_YCBCR_422,
+	DPI_30BIT,
+	DPI_36BIT,
+	DPI_12BIT_YCBCR_420,
+};
+
+/* Indicate which VOP the MIPI DSI use, bit or little one */
+enum  vop_id {
+	VOP_B = 0,
+	VOP_L,
+};
+
+#endif /* end of ROCKCHIP_MIPI_DSI_H */
diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h
new file mode 100644
index 0000000..9220763
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_RK3288_SDRAM_H__
+#define _ASM_ARCH_RK3288_SDRAM_H__
+
+struct rk3288_sdram_channel {
+	/*
+	 * bit width in address, eg:
+	 * 8 banks using 3 bit to address,
+	 * 2 cs using 1 bit to address.
+	 */
+	u8 rank;
+	u8 col;
+	u8 bk;
+	u8 bw;
+	u8 dbw;
+	u8 row_3_4;
+	u8 cs0_row;
+	u8 cs1_row;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	/*
+	 * For of-platdata, which would otherwise convert this into two
+	 * byte-swapped integers. With a size of 9 bytes, this struct will
+	 * appear in of-platdata as a byte array.
+	 *
+	 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
+	 */
+	u8 dummy;
+#endif
+};
+
+struct rk3288_sdram_pctl_timing {
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+};
+check_member(rk3288_sdram_pctl_timing, tdpd, 0x144 - 0xc0);
+
+struct rk3288_sdram_phy_timing {
+	u32 dtpr0;
+	u32 dtpr1;
+	u32 dtpr2;
+	u32 mr[4];
+};
+
+struct rk3288_base_params {
+	u32 noc_timing;
+	u32 noc_activate;
+	u32 ddrconfig;
+	u32 ddr_freq;
+	u32 dramtype;
+	/*
+	 * DDR Stride is address mapping for DRAM space
+	 * Stride	Ch 0 range	Ch1 range	Total
+	 * 0x00		0-256MB		256MB-512MB	512MB
+	 * 0x05		0-1GB		0-1GB		1GB
+	 * 0x09		0-2GB		0-2GB		2GB
+	 * 0x0d		0-4GB		0-4GB		4GB
+	 * 0x17		N/A		0-4GB		4GB
+	 * 0x1a		0-4GB		4GB-8GB		8GB
+	 */
+	u32 stride;
+	u32 odt;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
new file mode 100644
index 0000000..8027b53
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _ASM_ARCH_SDRAM_COMMON_H
+#define _ASM_ARCH_SDRAM_COMMON_H
+
+enum {
+	DDR4 = 0,
+	DDR3 = 0x3,
+	LPDDR2 = 0x5,
+	LPDDR3 = 0x6,
+	LPDDR4 = 0x7,
+	UNUSED = 0xFF
+};
+
+struct sdram_cap_info {
+	unsigned int rank;
+	/* dram column number, 0 means this channel is invalid */
+	unsigned int col;
+	/* dram bank number, 3:8bank, 2:4bank */
+	unsigned int bk;
+	/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
+	unsigned int bw;
+	/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
+	unsigned int dbw;
+	/*
+	 * row_3_4 = 1: 6Gb or 12Gb die
+	 * row_3_4 = 0: normal die, power of 2
+	 */
+	unsigned int row_3_4;
+	unsigned int cs0_row;
+	unsigned int cs1_row;
+	unsigned int ddrconfig;
+};
+
+struct sdram_base_params {
+	unsigned int ddr_freq;
+	unsigned int dramtype;
+	unsigned int num_channels;
+	unsigned int stride;
+	unsigned int odt;
+};
+
+/*
+ * sys_reg bitfield struct
+ * [31]		row_3_4_ch1
+ * [30]		row_3_4_ch0
+ * [29:28]	chinfo
+ * [27]		rank_ch1
+ * [26:25]	col_ch1
+ * [24]		bk_ch1
+ * [23:22]	cs0_row_ch1
+ * [21:20]	cs1_row_ch1
+ * [19:18]	bw_ch1
+ * [17:16]	dbw_ch1;
+ * [15:13]	ddrtype
+ * [12]		channelnum
+ * [11]		rank_ch0
+ * [10:9]	col_ch0
+ * [8]		bk_ch0
+ * [7:6]	cs0_row_ch0
+ * [5:4]	cs1_row_ch0
+ * [3:2]	bw_ch0
+ * [1:0]	dbw_ch0
+*/
+#define SYS_REG_DDRTYPE_SHIFT		13
+#define DDR_SYS_REG_VERSION		2
+#define SYS_REG_DDRTYPE_MASK		7
+#define SYS_REG_NUM_CH_SHIFT		12
+#define SYS_REG_NUM_CH_MASK		1
+#define SYS_REG_ROW_3_4_SHIFT(ch)	(30 + (ch))
+#define SYS_REG_ROW_3_4_MASK		1
+#define SYS_REG_ENC_ROW_3_4(n, ch)	((n) << (30 + (ch)))
+#define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
+#define SYS_REG_ENC_CHINFO(ch)		(1 << SYS_REG_CHINFO_SHIFT(ch))
+#define SYS_REG_ENC_DDRTYPE(n)		((n) << SYS_REG_DDRTYPE_SHIFT)
+#define SYS_REG_ENC_NUM_CH(n)		(((n) - SYS_REG_NUM_CH_MASK) << \
+					SYS_REG_NUM_CH_SHIFT)
+#define SYS_REG_RANK_SHIFT(ch)		(11 + (ch) * 16)
+#define SYS_REG_RANK_MASK		1
+#define SYS_REG_ENC_RANK(n, ch)		(((n) - SYS_REG_RANK_MASK) << \
+					 SYS_REG_RANK_SHIFT(ch))
+#define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
+#define SYS_REG_COL_MASK		3
+#define SYS_REG_ENC_COL(n, ch)		(((n) - 9) << SYS_REG_COL_SHIFT(ch))
+#define SYS_REG_BK_SHIFT(ch)		(8 + (ch) * 16)
+#define SYS_REG_BK_MASK			1
+#define SYS_REG_ENC_BK(n, ch)		(((n) == 3 ? 0 : 1) << \
+					SYS_REG_BK_SHIFT(ch))
+#define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
+#define SYS_REG_CS0_ROW_MASK		3
+#define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
+#define SYS_REG_CS1_ROW_MASK		3
+#define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
+#define SYS_REG_BW_MASK			3
+#define SYS_REG_ENC_BW(n, ch)		((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
+#define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
+#define SYS_REG_DBW_MASK		3
+#define SYS_REG_ENC_DBW(n, ch)		((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
+
+#define SYS_REG_ENC_VERSION(n)		((n) << 28)
+#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
+			(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
+			(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+				     (5 + 2 * (ch)); \
+		} while (0)
+
+#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
+			(os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
+			(os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
+			(os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
+			(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+				     (4 + 2 * (ch)); \
+		} while (0)
+
+#define SYS_REG_CS1_COL_SHIFT(ch)	(0 + 2 * (ch))
+#define SYS_REG_ENC_CS1_COL(n, ch)      (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch))
+
+/* Get sdram size decode from reg */
+size_t rockchip_sdram_size(phys_addr_t reg);
+
+/* Called by U-Boot board_init_r for Rockchip SoCs */
+int dram_init(void);
+
+#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
+inline void sdram_print_dram_type(unsigned char dramtype)
+{
+}
+
+inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+				 struct sdram_base_params *base)
+{
+}
+
+inline void sdram_print_stride(unsigned int stride)
+{
+}
+#else
+void sdram_print_dram_type(unsigned char dramtype);
+void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+			  struct sdram_base_params *base);
+void sdram_print_stride(unsigned int stride);
+#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h
new file mode 100644
index 0000000..5de3220
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3036.h
@@ -0,0 +1,340 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_SDRAM_RK3036_H
+#define _ASM_ARCH_SDRAM_RK3036_H
+
+#include <common.h>
+
+struct rk3036_ddr_pctl {
+	u32 scfg;
+	u32 sctl;
+	u32 stat;
+	u32 intrstat;
+	u32 reserved0[12];
+	u32 mcmd;
+	u32 powctl;
+	u32 powstat;
+	u32 cmdtstat;
+	u32 cmdtstaten;
+	u32 reserved1[3];
+	u32 mrrcfg0;
+	u32 mrrstat0;
+	u32 mrrstat1;
+	u32 reserved2[4];
+	u32 mcfg1;
+	u32 mcfg;
+	u32 ppcfg;
+	u32 mstat;
+	u32 lpddr2zqcfg;
+	u32 reserved3;
+	u32 dtupdes;
+	u32 dtuna;
+	u32 dtune;
+	u32 dtuprd0;
+	u32 dtuprd1;
+	u32 dtuprd2;
+	u32 dtuprd3;
+	u32 dtuawdt;
+	u32 reserved4[3];
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 reserved5[47];
+	u32 dtuwactl;
+	u32 dturactl;
+	u32 dtucfg;
+	u32 dtuectl;
+	u32 dtuwd0;
+	u32 dtuwd1;
+	u32 dtuwd2;
+	u32 dtuwd3;
+	u32 dtuwdm;
+	u32 dturd0;
+	u32 dturd1;
+	u32 dturd2;
+	u32 dturd3;
+	u32 dtulfsrwd;
+	u32 dtulfsrrd;
+	u32 dtueaf;
+	u32 dfitctrldelay;
+	u32 dfiodtcfg;
+	u32 dfiodtcfg1;
+	u32 dfiodtrankmap;
+	u32 dfitphywrdata;
+	u32 dfitphywrlat;
+	u32 reserved7[2];
+	u32 dfitrddataen;
+	u32 dfitphyrdlat;
+	u32 reserved8[2];
+	u32 dfitphyupdtype0;
+	u32 dfitphyupdtype1;
+	u32 dfitphyupdtype2;
+	u32 dfitphyupdtype3;
+	u32 dfitctrlupdmin;
+	u32 dfitctrlupdmax;
+	u32 dfitctrlupddly;
+	u32 reserved9;
+	u32 dfiupdcfg;
+	u32 dfitrefmski;
+	u32 dfitctrlupdi;
+	u32 reserved10[4];
+	u32 dfitrcfg0;
+	u32 dfitrstat0;
+	u32 dfitrwrlvlen;
+	u32 dfitrrdlvlen;
+	u32 dfitrrdlvlgateen;
+	u32 dfiststat0;
+	u32 dfistcfg0;
+	u32 dfistcfg1;
+	u32 reserved11;
+	u32 dfitdramclken;
+	u32 dfitdramclkdis;
+	u32 dfistcfg2;
+	u32 dfistparclr;
+	u32 dfistparlog;
+	u32 reserved12[3];
+	u32 dfilpcfg0;
+	u32 reserved13[3];
+	u32 dfitrwrlvlresp0;
+	u32 dfitrwrlvlresp1;
+	u32 dfitrwrlvlresp2;
+	u32 dfitrrdlvlresp0;
+	u32 dfitrrdlvlresp1;
+	u32 dfitrrdlvlresp2;
+	u32 dfitrwrlvldelay0;
+	u32 dfitrwrlvldelay1;
+	u32 dfitrwrlvldelay2;
+	u32 dfitrrdlvldelay0;
+	u32 dfitrrdlvldelay1;
+	u32 dfitrrdlvldelay2;
+	u32 dfitrrdlvlgatedelay0;
+	u32 dfitrrdlvlgatedelay1;
+	u32 dfitrrdlvlgatedelay2;
+	u32 dfitrcmd;
+	u32 reserved14[46];
+	u32 ipvr;
+	u32 iptr;
+};
+check_member(rk3036_ddr_pctl, iptr, 0x03fc);
+
+struct rk3036_ddr_phy {
+	u32 ddrphy_reg1;
+	u32 ddrphy_reg3;
+	u32 ddrphy_reg2;
+	u32 reserve[11];
+	u32 ddrphy_reg4a;
+	u32 ddrphy_reg4b;
+	u32 reserve1[5];
+	u32 ddrphy_reg16;
+	u32 reserve2;
+	u32 ddrphy_reg18;
+	u32 ddrphy_reg19;
+	u32 reserve3;
+	u32 ddrphy_reg21;
+	u32 reserve4;
+	u32 ddrphy_reg22;
+	u32 reserve5[3];
+	u32 ddrphy_reg25;
+	u32 ddrphy_reg26;
+	u32 ddrphy_reg27;
+	u32 ddrphy_reg28;
+	u32 reserve6[17];
+	u32 ddrphy_reg6;
+	u32 ddrphy_reg7;
+	u32 reserve7;
+	u32 ddrphy_reg8;
+	u32 ddrphy_reg0e4;
+	u32 reserve8[11];
+	u32 ddrphy_reg9;
+	u32 ddrphy_reg10;
+	u32 reserve9;
+	u32 ddrphy_reg11;
+	u32 ddrphy_reg124;
+	u32 reserve10[38];
+	u32 ddrphy_reg29;
+	u32 reserve11[40];
+	u32 ddrphy_reg264;
+	u32 reserve12[18];
+	u32 ddrphy_reg2a;
+	u32 reserve13[4];
+	u32 ddrphy_reg30;
+	u32 ddrphy_reg31;
+	u32 ddrphy_reg32;
+	u32 ddrphy_reg33;
+	u32 ddrphy_reg34;
+	u32 ddrphy_reg35;
+	u32 ddrphy_reg36;
+	u32 ddrphy_reg37;
+	u32 ddrphy_reg38;
+	u32 ddrphy_reg39;
+	u32 ddrphy_reg40;
+	u32 ddrphy_reg41;
+	u32 ddrphy_reg42;
+	u32 ddrphy_reg43;
+	u32 ddrphy_reg44;
+	u32 ddrphy_reg45;
+	u32 ddrphy_reg46;
+	u32 ddrphy_reg47;
+	u32 ddrphy_reg48;
+	u32 ddrphy_reg49;
+	u32 ddrphy_reg50;
+	u32 ddrphy_reg51;
+	u32 ddrphy_reg52;
+	u32 ddrphy_reg53;
+	u32 reserve14;
+	u32 ddrphy_reg54;
+	u32 ddrphy_reg55;
+	u32 ddrphy_reg56;
+	u32 ddrphy_reg57;
+	u32 ddrphy_reg58;
+	u32 ddrphy_reg59;
+	u32 ddrphy_reg5a;
+	u32 ddrphy_reg5b;
+	u32 ddrphy_reg5c;
+	u32 ddrphy_reg5d;
+	u32 ddrphy_reg5e;
+	u32 reserve15[28];
+	u32 ddrphy_reg5f;
+	u32 reserve16[6];
+	u32 ddrphy_reg60;
+	u32 ddrphy_reg61;
+	u32 ddrphy_reg62;
+};
+check_member(rk3036_ddr_phy, ddrphy_reg62, 0x03e8);
+
+struct rk3036_pctl_timing {
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+};
+
+struct rk3036_phy_timing {
+	u32 mr[4];
+	u32 bl;
+	u32 cl_al;
+};
+
+typedef union {
+	u32 noc_timing;
+	struct {
+		u32 acttoact:6;
+		u32 rdtomiss:6;
+		u32 wrtomiss:6;
+		u32 burstlen:3;
+		u32 rdtowr:5;
+		u32 wrtord:5;
+		u32 bwratio:1;
+	};
+} rk3036_noc_timing;
+
+struct rk3036_ddr_timing {
+	u32 freq;
+	struct rk3036_pctl_timing pctl_timing;
+	struct rk3036_phy_timing phy_timing;
+	rk3036_noc_timing noc_timing;
+};
+
+struct rk3036_service_sys {
+	u32 id_coreid;
+	u32 id_revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+};
+
+struct rk3036_ddr_config {
+	/*
+	 * 000: lpddr
+	 * 001: ddr
+	 * 010: ddr2
+	 * 011: ddr3
+	 * 100: lpddr2-s2
+	 * 101: lpddr2-s4
+	 * 110: lpddr3
+	 */
+	u32 ddr_type;
+	u32 rank;
+	u32 cs0_row;
+	u32 cs1_row;
+
+	/* 2: 4bank, 3: 8bank */
+	u32 bank;
+	u32 col;
+
+	/* bw(0: 8bit, 1: 16bit, 2: 32bit) */
+	u32 bw;
+};
+
+/* rk3036 sdram initial */
+void sdram_init(void);
+
+/* get ddr die config, implement in specific board */
+void get_ddr_config(struct rk3036_ddr_config *config);
+
+/* get ddr size on board */
+size_t sdram_size(void);
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
new file mode 100644
index 0000000..336c5d7
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
@@ -0,0 +1,573 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+#ifndef _ASM_ARCH_SDRAM_RK322X_H
+#define _ASM_ARCH_SDRAM_RK322X_H
+
+#include <common.h>
+
+struct rk322x_sdram_channel {
+	/*
+	 * bit width in address, eg:
+	 * 8 banks using 3 bit to address,
+	 * 2 cs using 1 bit to address.
+	 */
+	u8 rank;
+	u8 col;
+	u8 bk;
+	u8 bw;
+	u8 dbw;
+	u8 row_3_4;
+	u8 cs0_row;
+	u8 cs1_row;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	/*
+	 * For of-platdata, which would otherwise convert this into two
+	 * byte-swapped integers. With a size of 9 bytes, this struct will
+	 * appear in of-platdata as a byte array.
+	 *
+	 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
+	 */
+	u8 dummy;
+#endif
+};
+
+struct rk322x_ddr_pctl {
+	u32 scfg;
+	u32 sctl;
+	u32 stat;
+	u32 intrstat;
+	u32 reserved0[(0x40 - 0x10) / 4];
+	u32 mcmd;
+	u32 powctl;
+	u32 powstat;
+	u32 cmdtstat;
+	u32 cmdtstaten;
+	u32 reserved1[(0x60 - 0x54) / 4];
+	u32 mrrcfg0;
+	u32 mrrstat0;
+	u32 mrrstat1;
+	u32 reserved2[(0x7c - 0x6c) / 4];
+
+	u32 mcfg1;
+	u32 mcfg;
+	u32 ppcfg;
+	u32 mstat;
+	u32 lpddr2zqcfg;
+	u32 reserved3;
+
+	u32 dtupdes;
+	u32 dtuna;
+	u32 dtune;
+	u32 dtuprd0;
+	u32 dtuprd1;
+	u32 dtuprd2;
+	u32 dtuprd3;
+	u32 dtuawdt;
+	u32 reserved4[(0xc0 - 0xb4) / 4];
+
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+	u32 tref_mem_ddr3;
+	u32 reserved5[(0x180 - 0x14c) / 4];
+	u32 ecccfg;
+	u32 ecctst;
+	u32 eccclr;
+	u32 ecclog;
+	u32 reserved6[(0x200 - 0x190) / 4];
+	u32 dtuwactl;
+	u32 dturactl;
+	u32 dtucfg;
+	u32 dtuectl;
+	u32 dtuwd0;
+	u32 dtuwd1;
+	u32 dtuwd2;
+	u32 dtuwd3;
+	u32 dtuwdm;
+	u32 dturd0;
+	u32 dturd1;
+	u32 dturd2;
+	u32 dturd3;
+	u32 dtulfsrwd;
+	u32 dtulfsrrd;
+	u32 dtueaf;
+	/* dfi control registers */
+	u32 dfitctrldelay;
+	u32 dfiodtcfg;
+	u32 dfiodtcfg1;
+	u32 dfiodtrankmap;
+	/* dfi write data registers */
+	u32 dfitphywrdata;
+	u32 dfitphywrlat;
+	u32 reserved7[(0x260 - 0x258) / 4];
+	u32 dfitrddataen;
+	u32 dfitphyrdlat;
+	u32 reserved8[(0x270 - 0x268) / 4];
+	u32 dfitphyupdtype0;
+	u32 dfitphyupdtype1;
+	u32 dfitphyupdtype2;
+	u32 dfitphyupdtype3;
+	u32 dfitctrlupdmin;
+	u32 dfitctrlupdmax;
+	u32 dfitctrlupddly;
+	u32 reserved9;
+	u32 dfiupdcfg;
+	u32 dfitrefmski;
+	u32 dfitctrlupdi;
+	u32 reserved10[(0x2ac - 0x29c) / 4];
+	u32 dfitrcfg0;
+	u32 dfitrstat0;
+	u32 dfitrwrlvlen;
+	u32 dfitrrdlvlen;
+	u32 dfitrrdlvlgateen;
+	u32 dfiststat0;
+	u32 dfistcfg0;
+	u32 dfistcfg1;
+	u32 reserved11;
+	u32 dfitdramclken;
+	u32 dfitdramclkdis;
+	u32 dfistcfg2;
+	u32 dfistparclr;
+	u32 dfistparlog;
+	u32 reserved12[(0x2f0 - 0x2e4) / 4];
+
+	u32 dfilpcfg0;
+	u32 reserved13[(0x300 - 0x2f4) / 4];
+	u32 dfitrwrlvlresp0;
+	u32 dfitrwrlvlresp1;
+	u32 dfitrwrlvlresp2;
+	u32 dfitrrdlvlresp0;
+	u32 dfitrrdlvlresp1;
+	u32 dfitrrdlvlresp2;
+	u32 dfitrwrlvldelay0;
+	u32 dfitrwrlvldelay1;
+	u32 dfitrwrlvldelay2;
+	u32 dfitrrdlvldelay0;
+	u32 dfitrrdlvldelay1;
+	u32 dfitrrdlvldelay2;
+	u32 dfitrrdlvlgatedelay0;
+	u32 dfitrrdlvlgatedelay1;
+	u32 dfitrrdlvlgatedelay2;
+	u32 dfitrcmd;
+	u32 reserved14[(0x3f8 - 0x340) / 4];
+	u32 ipvr;
+	u32 iptr;
+};
+check_member(rk322x_ddr_pctl, iptr, 0x03fc);
+
+struct rk322x_ddr_phy {
+	u32 ddrphy_reg[0x100];
+};
+
+struct rk322x_pctl_timing {
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+	u32 trefi_mem_ddr3;
+};
+
+struct rk322x_phy_timing {
+	u32 mr[4];
+	u32 mr11;
+	u32 bl;
+	u32 cl_al;
+};
+
+struct rk322x_msch_timings {
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 activate;
+	u32 devtodev;
+};
+
+struct rk322x_service_sys {
+	u32 id_coreid;
+	u32 id_revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 activate;
+	u32 devtodev;
+};
+
+struct rk322x_base_params {
+	struct rk322x_msch_timings noc_timing;
+	u32 ddrconfig;
+	u32 ddr_freq;
+	u32 dramtype;
+	/*
+	 * unused for rk322x
+	 */
+	u32 stride;
+	u32 odt;
+};
+
+/* PCT_DFISTCFG0 */
+#define DFI_INIT_START			BIT(0)
+#define DFI_DATA_BYTE_DISABLE_EN	BIT(2)
+
+/* PCT_DFISTCFG1 */
+#define DFI_DRAM_CLK_SR_EN		BIT(0)
+#define DFI_DRAM_CLK_DPD_EN		BIT(1)
+
+/* PCT_DFISTCFG2 */
+#define DFI_PARITY_INTR_EN		BIT(0)
+#define DFI_PARITY_EN			BIT(1)
+
+/* PCT_DFILPCFG0 */
+#define TLP_RESP_TIME_SHIFT		16
+#define LP_SR_EN			BIT(8)
+#define LP_PD_EN			BIT(0)
+
+/* PCT_DFITCTRLDELAY */
+#define TCTRL_DELAY_TIME_SHIFT		0
+
+/* PCT_DFITPHYWRDATA */
+#define TPHY_WRDATA_TIME_SHIFT		0
+
+/* PCT_DFITPHYRDLAT */
+#define TPHY_RDLAT_TIME_SHIFT		0
+
+/* PCT_DFITDRAMCLKDIS */
+#define TDRAM_CLK_DIS_TIME_SHIFT	0
+
+/* PCT_DFITDRAMCLKEN */
+#define TDRAM_CLK_EN_TIME_SHIFT		0
+
+/* PCTL_DFIODTCFG */
+#define RANK0_ODT_WRITE_SEL		BIT(3)
+#define RANK1_ODT_WRITE_SEL		BIT(11)
+
+/* PCTL_DFIODTCFG1 */
+#define ODT_LEN_BL8_W_SHIFT		16
+
+/* PUBL_ACDLLCR */
+#define ACDLLCR_DLLDIS			BIT(31)
+#define ACDLLCR_DLLSRST			BIT(30)
+
+/* PUBL_DXDLLCR */
+#define DXDLLCR_DLLDIS			BIT(31)
+#define DXDLLCR_DLLSRST			BIT(30)
+
+/* PUBL_DLLGCR */
+#define DLLGCR_SBIAS			BIT(30)
+
+/* PUBL_DXGCR */
+#define DQSRTT				BIT(9)
+#define DQRTT				BIT(10)
+
+/* PIR */
+#define PIR_INIT			BIT(0)
+#define PIR_DLLSRST			BIT(1)
+#define PIR_DLLLOCK			BIT(2)
+#define PIR_ZCAL			BIT(3)
+#define PIR_ITMSRST			BIT(4)
+#define PIR_DRAMRST			BIT(5)
+#define PIR_DRAMINIT			BIT(6)
+#define PIR_QSTRN			BIT(7)
+#define PIR_RVTRN			BIT(8)
+#define PIR_ICPC			BIT(16)
+#define PIR_DLLBYP			BIT(17)
+#define PIR_CTLDINIT			BIT(18)
+#define PIR_CLRSR			BIT(28)
+#define PIR_LOCKBYP			BIT(29)
+#define PIR_ZCALBYP			BIT(30)
+#define PIR_INITBYP			BIT(31)
+
+/* PGCR */
+#define PGCR_DFTLMT_SHIFT		3
+#define PGCR_DFTCMP_SHIFT		2
+#define PGCR_DQSCFG_SHIFT		1
+#define PGCR_ITMDMD_SHIFT		0
+
+/* PGSR */
+#define PGSR_IDONE			BIT(0)
+#define PGSR_DLDONE			BIT(1)
+#define PGSR_ZCDONE			BIT(2)
+#define PGSR_DIDONE			BIT(3)
+#define PGSR_DTDONE			BIT(4)
+#define PGSR_DTERR			BIT(5)
+#define PGSR_DTIERR			BIT(6)
+#define PGSR_DFTERR			BIT(7)
+#define PGSR_RVERR			BIT(8)
+#define PGSR_RVEIRR			BIT(9)
+
+/* PTR0 */
+#define PRT_ITMSRST_SHIFT		18
+#define PRT_DLLLOCK_SHIFT		6
+#define PRT_DLLSRST_SHIFT		0
+
+/* PTR1 */
+#define PRT_DINIT0_SHIFT		0
+#define PRT_DINIT1_SHIFT		19
+
+/* PTR2 */
+#define PRT_DINIT2_SHIFT		0
+#define PRT_DINIT3_SHIFT		17
+
+/* DCR */
+#define DDRMD_LPDDR			0
+#define DDRMD_DDR			1
+#define DDRMD_DDR2			2
+#define DDRMD_DDR3			3
+#define DDRMD_LPDDR2_LPDDR3		4
+#define DDRMD_MASK			7
+#define DDRMD_SHIFT			0
+#define PDQ_MASK			7
+#define PDQ_SHIFT			4
+
+/* DXCCR */
+#define DQSNRES_MASK			0xf
+#define DQSNRES_SHIFT			8
+#define DQSRES_MASK			0xf
+#define DQSRES_SHIFT			4
+
+/* DTPR */
+#define TDQSCKMAX_SHIFT			27
+#define TDQSCKMAX_MASK			7
+#define TDQSCK_SHIFT			24
+#define TDQSCK_MASK			7
+
+/* DSGCR */
+#define DQSGX_SHIFT			5
+#define DQSGX_MASK			7
+#define DQSGE_SHIFT			8
+#define DQSGE_MASK			7
+
+/* SCTL */
+#define INIT_STATE			0
+#define CFG_STATE			1
+#define GO_STATE			2
+#define SLEEP_STATE			3
+#define WAKEUP_STATE			4
+
+/* STAT */
+#define LP_TRIG_SHIFT			4
+#define LP_TRIG_MASK			7
+#define PCTL_STAT_MASK			7
+#define INIT_MEM			0
+#define CONFIG				1
+#define CONFIG_REQ			2
+#define ACCESS				3
+#define ACCESS_REQ			4
+#define LOW_POWER			5
+#define LOW_POWER_ENTRY_REQ		6
+#define LOW_POWER_EXIT_REQ		7
+
+/* ZQCR*/
+#define PD_OUTPUT_SHIFT			0
+#define PU_OUTPUT_SHIFT			5
+#define PD_ONDIE_SHIFT			10
+#define PU_ONDIE_SHIFT			15
+#define ZDEN_SHIFT			28
+
+/* DDLGCR */
+#define SBIAS_BYPASS			BIT(23)
+
+/* MCFG */
+#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT	24
+#define PD_IDLE_SHIFT			8
+#define MDDR_EN				(2 << 22)
+#define LPDDR2_EN			(3 << 22)
+#define LPDDR3_EN			(1 << 22)
+#define DDR2_EN				(0 << 5)
+#define DDR3_EN				(1 << 5)
+#define LPDDR2_S2			(0 << 6)
+#define LPDDR2_S4			(1 << 6)
+#define MDDR_LPDDR2_BL_2		(0 << 20)
+#define MDDR_LPDDR2_BL_4		(1 << 20)
+#define MDDR_LPDDR2_BL_8		(2 << 20)
+#define MDDR_LPDDR2_BL_16		(3 << 20)
+#define DDR2_DDR3_BL_4			0
+#define DDR2_DDR3_BL_8			1
+#define TFAW_SHIFT			18
+#define PD_EXIT_SLOW			(0 << 17)
+#define PD_EXIT_FAST			(1 << 17)
+#define PD_TYPE_SHIFT			16
+#define BURSTLENGTH_SHIFT		20
+
+/* POWCTL */
+#define POWER_UP_START			BIT(0)
+
+/* POWSTAT */
+#define POWER_UP_DONE			BIT(0)
+
+/* MCMD */
+enum {
+	DESELECT_CMD			= 0,
+	PREA_CMD,
+	REF_CMD,
+	MRS_CMD,
+	ZQCS_CMD,
+	ZQCL_CMD,
+	RSTL_CMD,
+	MRR_CMD				= 8,
+	DPDE_CMD,
+};
+
+#define BANK_ADDR_MASK			7
+#define BANK_ADDR_SHIFT			17
+#define CMD_ADDR_MASK			0x1fff
+#define CMD_ADDR_SHIFT			4
+
+#define LPDDR23_MA_SHIFT		4
+#define LPDDR23_MA_MASK			0xff
+#define LPDDR23_OP_SHIFT		12
+#define LPDDR23_OP_MASK			0xff
+
+#define START_CMD			(1u << 31)
+
+/* DDRPHY REG */
+enum {
+	/* DDRPHY_REG0 */
+	SOFT_RESET_MASK				= 3,
+	SOFT_DERESET_ANALOG			= 1 << 2,
+	SOFT_DERESET_DIGITAL			= 1 << 3,
+	SOFT_RESET_SHIFT			= 2,
+
+	/* DDRPHY REG1 */
+	PHY_DDR3				= 0,
+	PHY_DDR2				= 1,
+	PHY_LPDDR3				= 2,
+	PHY_LPDDR2				= 3,
+
+	PHT_BL_8				= 1 << 2,
+	PHY_BL_4				= 0 << 2,
+
+	/* DDRPHY_REG2 */
+	MEMORY_SELECT_DDR3			= 0 << 0,
+	MEMORY_SELECT_LPDDR3			= 2 << 0,
+	MEMORY_SELECT_LPDDR2			= 3 << 0,
+	DQS_SQU_CAL_SEL_CS0_CS1			= 0 << 4,
+	DQS_SQU_CAL_SEL_CS1			= 1 << 4,
+	DQS_SQU_CAL_SEL_CS0			= 2 << 4,
+	DQS_SQU_CAL_NORMAL_MODE			= 0 << 1,
+	DQS_SQU_CAL_BYPASS_MODE			= 1 << 1,
+	DQS_SQU_CAL_START			= 1 << 0,
+	DQS_SQU_NO_CAL				= 0 << 0,
+};
+
+/* CK pull up/down driver strength control */
+enum {
+	PHY_RON_RTT_DISABLE = 0,
+	PHY_RON_RTT_451OHM = 1,
+	PHY_RON_RTT_225OHM,
+	PHY_RON_RTT_150OHM,
+	PHY_RON_RTT_112OHM,
+	PHY_RON_RTT_90OHM,
+	PHY_RON_RTT_75OHM,
+	PHY_RON_RTT_64OHM = 7,
+
+	PHY_RON_RTT_56OHM = 16,
+	PHY_RON_RTT_50OHM,
+	PHY_RON_RTT_45OHM,
+	PHY_RON_RTT_41OHM,
+	PHY_RON_RTT_37OHM,
+	PHY_RON_RTT_34OHM,
+	PHY_RON_RTT_33OHM,
+	PHY_RON_RTT_30OHM = 23,
+
+	PHY_RON_RTT_28OHM = 24,
+	PHY_RON_RTT_26OHM,
+	PHY_RON_RTT_25OHM,
+	PHY_RON_RTT_23OHM,
+	PHY_RON_RTT_22OHM,
+	PHY_RON_RTT_21OHM,
+	PHY_RON_RTT_20OHM,
+	PHY_RON_RTT_19OHM = 31,
+};
+
+/* DQS squelch DLL delay */
+enum {
+	DQS_DLL_NO_DELAY	= 0,
+	DQS_DLL_22P5_DELAY,
+	DQS_DLL_45_DELAY,
+	DQS_DLL_67P5_DELAY,
+	DQS_DLL_90_DELAY,
+	DQS_DLL_112P5_DELAY,
+	DQS_DLL_135_DELAY,
+	DQS_DLL_157P5_DELAY,
+};
+
+/* GRF_SOC_CON0 */
+#define GRF_DDR_16BIT_EN		(((0x1 << 0) << 16) | (0x1 << 0))
+#define GRF_DDR_32BIT_EN		(((0x1 << 0) << 16) | (0x0 << 0))
+#define GRF_MSCH_NOC_16BIT_EN		(((0x1 << 7) << 16) | (0x1 << 7))
+#define GRF_MSCH_NOC_32BIT_EN		(((0x1 << 7) << 16) | (0x0 << 7))
+
+#define GRF_DDRPHY_BUFFEREN_CORE_EN	(((0x1 << 8) << 16) | (0x0 << 8))
+#define GRF_DDRPHY_BUFFEREN_CORE_DIS	(((0x1 << 8) << 16) | (0x1 << 8))
+
+#define GRF_DDR3_EN			(((0x1 << 6) << 16) | (0x1 << 6))
+#define GRF_LPDDR2_3_EN			(((0x1 << 6) << 16) | (0x0 << 6))
+
+#define PHY_DRV_ODT_SET(n)		(((n) << 4) | (n))
+#define DDR3_DLL_RESET			(1 << 8)
+
+#endif /* _ASM_ARCH_SDRAM_RK322X_H */
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
new file mode 100644
index 0000000..11411ea
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
@@ -0,0 +1,441 @@
+/*
+ * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SDRAM_RK3328_H
+#define _ASM_ARCH_SDRAM_RK3328_H
+
+#define SR_IDLE		93
+#define PD_IDLE		13
+#define SDRAM_ADDR	0x00000000
+#define PATTERN		(0x5aa5f00f)
+
+/* ddr pctl registers define */
+#define DDR_PCTL2_MSTR			0x0
+#define DDR_PCTL2_STAT			0x4
+#define DDR_PCTL2_MSTR1			0x8
+#define DDR_PCTL2_MRCTRL0		0x10
+#define DDR_PCTL2_MRCTRL1		0x14
+#define DDR_PCTL2_MRSTAT		0x18
+#define DDR_PCTL2_MRCTRL2		0x1c
+#define DDR_PCTL2_DERATEEN		0x20
+#define DDR_PCTL2_DERATEINT		0x24
+#define DDR_PCTL2_PWRCTL		0x30
+#define DDR_PCTL2_PWRTMG		0x34
+#define DDR_PCTL2_HWLPCTL		0x38
+#define DDR_PCTL2_RFSHCTL0		0x50
+#define DDR_PCTL2_RFSHCTL1		0x54
+#define DDR_PCTL2_RFSHCTL2		0x58
+#define DDR_PCTL2_RFSHCTL4		0x5c
+#define DDR_PCTL2_RFSHCTL3		0x60
+#define DDR_PCTL2_RFSHTMG		0x64
+#define DDR_PCTL2_RFSHTMG1		0x68
+#define DDR_PCTL2_RFSHCTL5		0x6c
+#define DDR_PCTL2_INIT0			0xd0
+#define DDR_PCTL2_INIT1			0xd4
+#define DDR_PCTL2_INIT2			0xd8
+#define DDR_PCTL2_INIT3			0xdc
+#define DDR_PCTL2_INIT4			0xe0
+#define DDR_PCTL2_INIT5			0xe4
+#define DDR_PCTL2_INIT6			0xe8
+#define DDR_PCTL2_INIT7			0xec
+#define DDR_PCTL2_DIMMCTL		0xf0
+#define DDR_PCTL2_RANKCTL		0xf4
+#define DDR_PCTL2_CHCTL			0xfc
+#define DDR_PCTL2_DRAMTMG0		0x100
+#define DDR_PCTL2_DRAMTMG1		0x104
+#define DDR_PCTL2_DRAMTMG2		0x108
+#define DDR_PCTL2_DRAMTMG3		0x10c
+#define DDR_PCTL2_DRAMTMG4		0x110
+#define DDR_PCTL2_DRAMTMG5		0x114
+#define DDR_PCTL2_DRAMTMG6		0x118
+#define DDR_PCTL2_DRAMTMG7		0x11c
+#define DDR_PCTL2_DRAMTMG8		0x120
+#define DDR_PCTL2_DRAMTMG9		0x124
+#define DDR_PCTL2_DRAMTMG10		0x128
+#define DDR_PCTL2_DRAMTMG11		0x12c
+#define DDR_PCTL2_DRAMTMG12		0x130
+#define DDR_PCTL2_DRAMTMG13		0x134
+#define DDR_PCTL2_DRAMTMG14		0x138
+#define DDR_PCTL2_DRAMTMG15		0x13c
+#define DDR_PCTL2_DRAMTMG16		0x140
+#define DDR_PCTL2_ZQCTL0		0x180
+#define DDR_PCTL2_ZQCTL1		0x184
+#define DDR_PCTL2_ZQCTL2		0x188
+#define DDR_PCTL2_ZQSTAT		0x18c
+#define DDR_PCTL2_DFITMG0		0x190
+#define DDR_PCTL2_DFITMG1		0x194
+#define DDR_PCTL2_DFILPCFG0		0x198
+#define DDR_PCTL2_DFILPCFG1		0x19c
+#define DDR_PCTL2_DFIUPD0		0x1a0
+#define DDR_PCTL2_DFIUPD1		0x1a4
+#define DDR_PCTL2_DFIUPD2		0x1a8
+#define DDR_PCTL2_DFIMISC		0x1b0
+#define DDR_PCTL2_DFITMG2		0x1b4
+#define DDR_PCTL2_DFITMG3		0x1b8
+#define DDR_PCTL2_DFISTAT		0x1bc
+#define DDR_PCTL2_DBICTL		0x1c0
+#define DDR_PCTL2_ADDRMAP0		0x200
+#define DDR_PCTL2_ADDRMAP1		0x204
+#define DDR_PCTL2_ADDRMAP2		0x208
+#define DDR_PCTL2_ADDRMAP3		0x20c
+#define DDR_PCTL2_ADDRMAP4		0x210
+#define DDR_PCTL2_ADDRMAP5		0x214
+#define DDR_PCTL2_ADDRMAP6		0x218
+#define DDR_PCTL2_ADDRMAP7		0x21c
+#define DDR_PCTL2_ADDRMAP8		0x220
+#define DDR_PCTL2_ADDRMAP9		0x224
+#define DDR_PCTL2_ADDRMAP10		0x228
+#define DDR_PCTL2_ADDRMAP11		0x22c
+#define DDR_PCTL2_ODTCFG		0x240
+#define DDR_PCTL2_ODTMAP		0x244
+#define DDR_PCTL2_SCHED			0x250
+#define DDR_PCTL2_SCHED1		0x254
+#define DDR_PCTL2_PERFHPR1		0x25c
+#define DDR_PCTL2_PERFLPR1		0x264
+#define DDR_PCTL2_PERFWR1		0x26c
+#define DDR_PCTL2_DQMAP0		0x280
+#define DDR_PCTL2_DQMAP1		0x284
+#define DDR_PCTL2_DQMAP2		0x288
+#define DDR_PCTL2_DQMAP3		0x28c
+#define DDR_PCTL2_DQMAP4		0x290
+#define DDR_PCTL2_DQMAP5		0x294
+#define DDR_PCTL2_DBG0			0x300
+#define DDR_PCTL2_DBG1			0x304
+#define DDR_PCTL2_DBGCAM		0x308
+#define DDR_PCTL2_DBGCMD		0x30c
+#define DDR_PCTL2_DBGSTAT		0x310
+#define DDR_PCTL2_SWCTL			0x320
+#define DDR_PCTL2_SWSTAT		0x324
+#define DDR_PCTL2_POISONCFG		0x36c
+#define DDR_PCTL2_POISONSTAT		0x370
+#define DDR_PCTL2_ADVECCINDEX		0x374
+#define DDR_PCTL2_ADVECCSTAT		0x378
+#define DDR_PCTL2_PSTAT			0x3fc
+#define DDR_PCTL2_PCCFG			0x400
+#define DDR_PCTL2_PCFGR_n		0x404
+#define DDR_PCTL2_PCFGW_n		0x408
+#define DDR_PCTL2_PCTRL_n		0x490
+
+/* PCTL2_MRSTAT */
+#define MR_WR_BUSY			BIT(0)
+
+/* PHY_REG0 */
+#define DIGITAL_DERESET			BIT(3)
+#define ANALOG_DERESET			BIT(2)
+#define DIGITAL_RESET			(0 << 3)
+#define ANALOG_RESET			(0 << 2)
+
+/* PHY_REG1 */
+#define PHY_DDR2			(0)
+#define PHY_LPDDR2			(1)
+#define PHY_DDR3			(2)
+#define PHY_LPDDR3			(3)
+#define PHY_DDR4			(4)
+#define PHY_BL_4			(0 << 2)
+#define PHY_BL_8			BIT(2)
+
+/* PHY_REG2 */
+#define PHY_DTT_EN			BIT(0)
+#define PHY_DTT_DISB			(0 << 0)
+#define PHY_WRITE_LEVELING_EN		BIT(2)
+#define PHY_WRITE_LEVELING_DISB		(0 << 2)
+#define PHY_SELECT_CS0			(2)
+#define PHY_SELECT_CS1			(1)
+#define PHY_SELECT_CS0_1		(0)
+#define PHY_WRITE_LEVELING_SELECTCS(n)	(n << 6)
+#define PHY_DATA_TRAINING_SELECTCS(n)	(n << 4)
+
+#define PHY_DDR3_RON_RTT_DISABLE	(0)
+#define PHY_DDR3_RON_RTT_451ohm		(1)
+#define PHY_DDR3_RON_RTT_225ohm		(2)
+#define PHY_DDR3_RON_RTT_150ohm		(3)
+#define PHY_DDR3_RON_RTT_112ohm		(4)
+#define PHY_DDR3_RON_RTT_90ohm		(5)
+#define PHY_DDR3_RON_RTT_75ohm		(6)
+#define PHY_DDR3_RON_RTT_64ohm		(7)
+#define PHY_DDR3_RON_RTT_56ohm		(16)
+#define PHY_DDR3_RON_RTT_50ohm		(17)
+#define PHY_DDR3_RON_RTT_45ohm		(18)
+#define PHY_DDR3_RON_RTT_41ohm		(19)
+#define PHY_DDR3_RON_RTT_37ohm		(20)
+#define PHY_DDR3_RON_RTT_34ohm		(21)
+#define PHY_DDR3_RON_RTT_33ohm		(22)
+#define PHY_DDR3_RON_RTT_30ohm		(23)
+#define PHY_DDR3_RON_RTT_28ohm		(24)
+#define PHY_DDR3_RON_RTT_26ohm		(25)
+#define PHY_DDR3_RON_RTT_25ohm		(26)
+#define PHY_DDR3_RON_RTT_23ohm		(27)
+#define PHY_DDR3_RON_RTT_22ohm		(28)
+#define PHY_DDR3_RON_RTT_21ohm		(29)
+#define PHY_DDR3_RON_RTT_20ohm		(30)
+#define PHY_DDR3_RON_RTT_19ohm		(31)
+
+#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE	(0)
+#define PHY_DDR4_LPDDR3_RON_RTT_480ohm	(1)
+#define PHY_DDR4_LPDDR3_RON_RTT_240ohm	(2)
+#define PHY_DDR4_LPDDR3_RON_RTT_160ohm	(3)
+#define PHY_DDR4_LPDDR3_RON_RTT_120ohm	(4)
+#define PHY_DDR4_LPDDR3_RON_RTT_96ohm	(5)
+#define PHY_DDR4_LPDDR3_RON_RTT_80ohm	(6)
+#define PHY_DDR4_LPDDR3_RON_RTT_68ohm	(7)
+#define PHY_DDR4_LPDDR3_RON_RTT_60ohm	(16)
+#define PHY_DDR4_LPDDR3_RON_RTT_53ohm	(17)
+#define PHY_DDR4_LPDDR3_RON_RTT_48ohm	(18)
+#define PHY_DDR4_LPDDR3_RON_RTT_43ohm	(19)
+#define PHY_DDR4_LPDDR3_RON_RTT_40ohm	(20)
+#define PHY_DDR4_LPDDR3_RON_RTT_37ohm	(21)
+#define PHY_DDR4_LPDDR3_RON_RTT_34ohm	(22)
+#define PHY_DDR4_LPDDR3_RON_RTT_32ohm	(23)
+#define PHY_DDR4_LPDDR3_RON_RTT_30ohm	(24)
+#define PHY_DDR4_LPDDR3_RON_RTT_28ohm	(25)
+#define PHY_DDR4_LPDDR3_RON_RTT_26ohm	(26)
+#define PHY_DDR4_LPDDR3_RON_RTT_25ohm	(27)
+#define PHY_DDR4_LPDDR3_RON_RTT_24ohm	(28)
+#define PHY_DDR4_LPDDR3_RON_RTT_22ohm	(29)
+#define PHY_DDR4_LPDDR3_RON_RTT_21ohm	(30)
+#define PHY_DDR4_LPDDR3_RON_RTT_20ohm	(31)
+
+/* noc registers define */
+#define DDRCONF				0x8
+#define DDRTIMING			0xc
+#define DDRMODE				0x10
+#define READLATENCY			0x14
+#define AGING0				0x18
+#define AGING1				0x1c
+#define AGING2				0x20
+#define AGING3				0x24
+#define AGING4				0x28
+#define AGING5				0x2c
+#define ACTIVATE			0x38
+#define DEVTODEV			0x3c
+#define DDR4TIMING			0x40
+
+/* DDR GRF */
+#define DDR_GRF_CON(n)		(0 + (n) * 4)
+#define DDR_GRF_STATUS_BASE	(0X100)
+#define DDR_GRF_STATUS(n)	(DDR_GRF_STATUS_BASE + (n) * 4)
+
+/* CRU_SOFTRESET_CON5 */
+#define ddrphy_psrstn_req(n)    (((0x1 << 15) << 16) | (n << 15))
+#define ddrphy_srstn_req(n)     (((0x1 << 14) << 16) | (n << 14))
+#define ddrctrl_psrstn_req(n)	(((0x1 << 13) << 16) | (n << 13))
+#define ddrctrl_srstn_req(n)	(((0x1 << 12) << 16) | (n << 12))
+#define ddrmsch_srstn_req(n)	(((0x1 << 11) << 16) | (n << 11))
+#define msch_srstn_req(n)		(((0x1 << 9) << 16) | (n << 9))
+#define dfimon_srstn_req(n)		(((0x1 << 8) << 16) | (n << 8))
+#define grf_ddr_srstn_req(n)	(((0x1 << 7) << 16) | (n << 7))
+/* CRU_SOFTRESET_CON9 */
+#define ddrctrl_asrstn_req(n)		(((0x1 << 9) << 16) | (n << 9))
+
+/* CRU register */
+#define CRU_PLL_CON(pll_id, n)	((pll_id)  * 0x20 + (n) * 4)
+#define CRU_MODE				(0x80)
+#define CRU_GLB_CNT_TH			(0x90)
+#define CRU_CLKSEL_CON_BASE		0x100
+#define CRU_CLKSELS_CON(i)		(CRU_CLKSEL_CON_BASE + ((i) * 4))
+#define CRU_CLKGATE_CON_BASE		0x200
+#define CRU_CLKGATE_CON(i)		(CRU_CLKGATE_CON_BASE + ((i) * 4))
+#define CRU_CLKSFTRST_CON_BASE	0x300
+#define CRU_CLKSFTRST_CON(i)	(CRU_CLKSFTRST_CON_BASE + ((i) * 4))
+
+/* CRU_PLL_CON0 */
+#define PB(n)         ((0x1 << (15 + 16)) | ((n) << 15))
+#define POSTDIV1(n)   ((0x7 << (12 + 16)) | ((n) << 12))
+#define FBDIV(n)      ((0xFFF << 16) | (n))
+
+/* CRU_PLL_CON1 */
+#define RSTMODE(n)    ((0x1 << (15 + 16)) | ((n) << 15))
+#define RST(n)        ((0x1 << (14 + 16)) | ((n) << 14))
+#define PD(n)         ((0x1 << (13 + 16)) | ((n) << 13))
+#define DSMPD(n)      ((0x1 << (12 + 16)) | ((n) << 12))
+#define LOCK(n)       (((n) >> 10) & 0x1)
+#define POSTDIV2(n)   ((0x7 << (6 + 16)) | ((n) << 6))
+#define REFDIV(n)     ((0x3F << 16) | (n))
+
+union noc_ddrtiming {
+	u32 d32;
+	struct {
+		unsigned acttoact:6;
+		unsigned rdtomiss:6;
+		unsigned wrtomiss:6;
+		unsigned burstlen:3;
+		unsigned rdtowr:5;
+		unsigned wrtord:5;
+		unsigned bwratio:1;
+	} b;
+} NOC_TIMING_T;
+
+union noc_activate {
+	u32 d32;
+	struct {
+		unsigned rrd:4;
+		unsigned faw:6;
+		unsigned fawbank:1;
+		unsigned reserved1:21;
+	} b;
+};
+
+union noc_devtodev {
+	u32 d32;
+	struct {
+		unsigned busrdtord:2;
+		unsigned busrdtowr:2;
+		unsigned buswrtord:2;
+		unsigned reserved2:26;
+	} b;
+};
+
+union noc_ddr4timing {
+	u32 d32;
+	struct {
+		unsigned ccdl:3;
+		unsigned wrtordl:5;
+		unsigned rrdl:4;
+		unsigned reserved2:20;
+	} b;
+};
+
+union noc_ddrmode {
+	u32 d32;
+	struct {
+		unsigned autoprecharge:1;
+		unsigned bwratioextended:1;
+		unsigned reserved3:30;
+	} b;
+};
+
+u32 addrmap[21][9] = {
+	/* map0  map1  map2  map3  map4  map5  map6  map7  map8 */
+	{22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606,
+		0x06060606, 0x00000f0f, 0x3f3f},
+	{23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f0f, 0x3f3f},
+	{23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
+		0x0f080808, 0x00000f0f, 0x3f3f},
+	{24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808,
+		0x08080808, 0x00000f0f, 0x3f3f},
+	{24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909,
+		0x0f090909, 0x00000f0f, 0x3f3f},
+	{6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f0f, 0x3f3f},
+	{7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808,
+		0x08080808, 0x00000f0f, 0x3f3f},
+	{8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909,
+		0x0f090909, 0x00000f0f, 0x3f3f},
+	{22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606,
+		0x06060606, 0x00000f0f, 0x3f3f},
+	{23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707,
+		0x0f070707, 0x00000f0f, 0x3f3f},
+
+	{24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
+		0x08080808, 0x00000f0f, 0x0801},
+	{23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
+		0x0f080808, 0x00000f0f, 0x0801},
+	{24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f07, 0x0700},
+	{23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f0f, 0x0700},
+	{24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f07, 0x3f01},
+	{23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f0f, 0x3f01},
+	{24, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606,
+		0x06060606, 0x00000f06, 0x3f00},
+	{8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909,
+		0x0f090909, 0x00000f0f, 0x0801},
+	{7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808,
+		0x08080808, 0x00000f0f, 0x0700},
+	{7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808,
+		0x08080808, 0x00000f0f, 0x3f01},
+
+	{6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707,
+		0x07070707, 0x00000f07, 0x3f00}
+};
+
+struct rk3328_msch_timings {
+	union noc_ddrtiming ddrtiming;
+	union noc_ddrmode ddrmode;
+	u32 readlatency;
+	union noc_activate activate;
+	union noc_devtodev devtodev;
+	union noc_ddr4timing ddr4timing;
+	u32 agingx0;
+};
+
+struct rk3328_msch_regs {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 aging0;
+	u32 aging1;
+	u32 aging2;
+	u32 aging3;
+	u32 aging4;
+	u32 aging5;
+	u32 reserved[2];
+	u32 activate;
+	u32 devtodev;
+	u32 ddr4_timing;
+};
+
+struct rk3328_ddr_grf_regs {
+	u32 ddr_grf_con[4];
+	u32 reserved[(0x100 - 0x10) / 4];
+	u32 ddr_grf_status[11];
+};
+
+struct rk3328_ddr_pctl_regs {
+	u32 pctl[30][2];
+};
+
+struct rk3328_ddr_phy_regs {
+	u32 phy[5][2];
+};
+
+struct rk3328_ddr_skew {
+	u32 a0_a1_skew[15];
+	u32 cs0_dm0_skew[11];
+	u32 cs0_dm1_skew[11];
+	u32 cs0_dm2_skew[11];
+	u32 cs0_dm3_skew[11];
+	u32 cs1_dm0_skew[11];
+	u32 cs1_dm1_skew[11];
+	u32 cs1_dm2_skew[11];
+	u32 cs1_dm3_skew[11];
+};
+
+struct rk3328_sdram_channel {
+	unsigned int rank;
+	unsigned int col;
+	/* 3:8bank, 2:4bank */
+	unsigned int bk;
+	/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
+	unsigned int bw;
+	/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
+	unsigned int dbw;
+	unsigned int row_3_4;
+	unsigned int cs0_row;
+	unsigned int cs1_row;
+	unsigned int ddrconfig;
+	struct rk3328_msch_timings noc_timings;
+};
+
+struct rk3328_sdram_params {
+	struct rk3328_sdram_channel ch;
+	unsigned int ddr_freq;
+	unsigned int dramtype;
+	unsigned int odt;
+	struct rk3328_ddr_pctl_regs pctl_regs;
+	struct rk3328_ddr_phy_regs phy_regs;
+	struct rk3328_ddr_skew skew;
+};
+
+#define PHY_REG(base, n)		(base + 4 * (n))
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
new file mode 100644
index 0000000..dc65ae7
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _ASM_ARCH_SDRAM_RK3399_H
+#define _ASM_ARCH_SDRAM_RK3399_H
+
+struct rk3399_ddr_pctl_regs {
+	u32 denali_ctl[332];
+};
+
+struct rk3399_ddr_publ_regs {
+	u32 denali_phy[959];
+};
+
+struct rk3399_ddr_pi_regs {
+	u32 denali_pi[200];
+};
+
+union noc_ddrtimingc0 {
+	u32 d32;
+	struct {
+		unsigned burstpenalty : 4;
+		unsigned reserved0 : 4;
+		unsigned wrtomwr : 6;
+		unsigned reserved1 : 18;
+	} b;
+};
+
+union noc_ddrmode {
+	u32 d32;
+	struct {
+		unsigned autoprecharge : 1;
+		unsigned bypassfiltering : 1;
+		unsigned fawbank : 1;
+		unsigned burstsize : 2;
+		unsigned mwrsize : 2;
+		unsigned reserved2 : 1;
+		unsigned forceorder : 8;
+		unsigned forceorderstate : 8;
+		unsigned reserved3 : 8;
+	} b;
+};
+
+struct rk3399_msch_regs {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrsize;
+	u32 ddrtiminga0;
+	u32 ddrtimingb0;
+	u32 ddrtimingc0;
+	u32 devtodev0;
+	u32 reserved0[(0x110 - 0x20) / 4];
+	u32 ddrmode;
+	u32 reserved1[(0x1000 - 0x114) / 4];
+	u32 agingx0;
+};
+
+struct rk3399_msch_timings {
+	u32 ddrtiminga0;
+	u32 ddrtimingb0;
+	union noc_ddrtimingc0 ddrtimingc0;
+	u32 devtodev0;
+	union noc_ddrmode ddrmode;
+	u32 agingx0;
+};
+
+struct rk3399_ddr_cic_regs {
+	u32 cic_ctrl0;
+	u32 cic_ctrl1;
+	u32 cic_idle_th;
+	u32 cic_cg_wait_th;
+	u32 cic_status0;
+	u32 cic_status1;
+	u32 cic_ctrl2;
+	u32 cic_ctrl3;
+	u32 cic_ctrl4;
+};
+
+/* DENALI_CTL_00 */
+#define START		1
+
+/* DENALI_CTL_68 */
+#define PWRUP_SREFRESH_EXIT	(1 << 16)
+
+/* DENALI_CTL_274 */
+#define MEM_RST_VALID	1
+
+struct rk3399_sdram_channel {
+	struct sdram_cap_info cap_info;
+	struct rk3399_msch_timings noc_timings;
+};
+
+struct rk3399_sdram_params {
+	struct rk3399_sdram_channel ch[2];
+	struct sdram_base_params base;
+	struct rk3399_ddr_pctl_regs pctl_regs;
+	struct rk3399_ddr_pi_regs pi_regs;
+	struct rk3399_ddr_publ_regs phy_regs;
+};
+
+#define PI_CA_TRAINING		(1 << 0)
+#define PI_WRITE_LEVELING	(1 << 1)
+#define PI_READ_GATE_TRAINING	(1 << 2)
+#define PI_READ_LEVELING	(1 << 3)
+#define PI_WDQ_LEVELING		(1 << 4)
+#define PI_FULL_TRAINING	0xff
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h
new file mode 100644
index 0000000..de5a8f1
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co.,Ltd
+ */
+
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h
new file mode 100644
index 0000000..77b5422
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/timer.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_TIMER_H
+#define __ASM_ARCH_TIMER_H
+
+struct rk_timer {
+	u32 timer_load_count0;
+	u32 timer_load_count1;
+	u32 timer_curr_value0;
+	u32 timer_curr_value1;
+	u32 timer_ctrl_reg;
+	u32 timer_int_status;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/uart.h b/arch/arm/include/asm/arch-rockchip/uart.h
new file mode 100644
index 0000000..feede5e
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/uart.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_UART_H
+#define __ASM_ARCH_UART_H
+struct rk_uart {
+	unsigned int rbr; /* Receive buffer register. */
+	unsigned int ier; /* Interrupt enable register. */
+	unsigned int fcr; /* FIFO control register. */
+	unsigned int lcr; /* Line control register. */
+	unsigned int mcr; /* Modem control register. */
+	unsigned int lsr; /* Line status register. */
+	unsigned int msr; /* Modem status register. */
+	unsigned int scr;
+	unsigned int reserved1[(0x30 - 0x20) / 4];
+	unsigned int srbr[(0x70 - 0x30) / 4];
+	unsigned int far;
+	unsigned int tfr;
+	unsigned int rfw;
+	unsigned int usr;
+	unsigned int tfl;
+	unsigned int rfl;
+	unsigned int srr;
+	unsigned int srts;
+	unsigned int sbcr;
+	unsigned int sdmam;
+	unsigned int sfe;
+	unsigned int srt;
+	unsigned int stet;
+	unsigned int htx;
+	unsigned int dmasa;
+	unsigned int reserver2[(0xf4 - 0xac) / 4];
+	unsigned int cpr;
+	unsigned int ucv;
+	unsigned int ctr;
+};
+
+void rk_uart_init(void *base);
+void print_hex(unsigned int n);
+void print(char *s);
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
new file mode 100644
index 0000000..8398249
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h
@@ -0,0 +1,361 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ */
+
+#ifndef _ASM_ARCH_VOP_RK3288_H
+#define _ASM_ARCH_VOP_RK3288_H
+
+struct rk3288_vop {
+	u32 reg_cfg_done;
+	u32 version_info;
+	u32 sys_ctrl;
+	u32 sys_ctrl1;
+	u32 dsp_ctrl0;
+	u32 dsp_ctrl1;
+	u32 dsp_bg;
+	u32 mcu_ctrl;
+	u32 intr_ctrl0;
+	u32 intr_ctrl1;
+	u32 intr_reserved0;
+	u32 intr_reserved1;
+
+	u32 win0_ctrl0;
+	u32 win0_ctrl1;
+	u32 win0_color_key;
+	u32 win0_vir;
+	u32 win0_yrgb_mst;
+	u32 win0_cbr_mst;
+	u32 win0_act_info;
+	u32 win0_dsp_info;
+	u32 win0_dsp_st;
+	u32 win0_scl_factor_yrgb;
+	u32 win0_scl_factor_cbr;
+	u32 win0_scl_offset;
+	u32 win0_src_alpha_ctrl;
+	u32 win0_dst_alpha_ctrl;
+	u32 win0_fading_ctrl;
+	u32 win0_reserved0;
+
+	u32 win1_ctrl0;
+	u32 win1_ctrl1;
+	u32 win1_color_key;
+	u32 win1_vir;
+	u32 win1_yrgb_mst;
+	u32 win1_cbr_mst;
+	u32 win1_act_info;
+	u32 win1_dsp_info;
+	u32 win1_dsp_st;
+	u32 win1_scl_factor_yrgb;
+	u32 win1_scl_factor_cbr;
+	u32 win1_scl_offset;
+	u32 win1_src_alpha_ctrl;
+	u32 win1_dst_alpha_ctrl;
+	u32 win1_fading_ctrl;
+	u32 win1_reservd0;
+	u32 reserved2[48];
+	u32 post_dsp_hact_info;
+	u32 post_dsp_vact_info;
+	u32 post_scl_factor_yrgb;
+	u32 post_reserved;
+	u32 post_scl_ctrl;
+	u32 post_dsp_vact_info_f1;
+	u32 dsp_htotal_hs_end;
+	u32 dsp_hact_st_end;
+	u32 dsp_vtotal_vs_end;
+	u32 dsp_vact_st_end;
+	u32 dsp_vs_st_end_f1;
+	u32 dsp_vact_st_end_f1;
+};
+check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c);
+
+enum rockchip_fb_data_format_t {
+	ARGB8888 = 0,
+	RGB888 = 1,
+	RGB565 = 2,
+};
+
+enum {
+	LB_YUV_3840X5 = 0x0,
+	LB_YUV_2560X8 = 0x1,
+	LB_RGB_3840X2 = 0x2,
+	LB_RGB_2560X4 = 0x3,
+	LB_RGB_1920X5 = 0x4,
+	LB_RGB_1280X8 = 0x5
+};
+
+enum vop_modes {
+	VOP_MODE_EDP = 0,
+	VOP_MODE_HDMI,
+	VOP_MODE_LVDS,
+	VOP_MODE_MIPI,
+	VOP_MODE_NONE,
+	VOP_MODE_AUTO_DETECT,
+	VOP_MODE_UNKNOWN,
+};
+
+/* VOP_VERSION_INFO */
+#define M_FPGA_VERSION (0xffff << 16)
+#define M_RTL_VERSION  (0xffff)
+
+/* VOP_SYS_CTRL */
+#define M_AUTO_GATING_EN (1 << 23)
+#define M_STANDBY_EN     (1 << 22)
+#define M_DMA_STOP       (1 << 21)
+#define M_MMU_EN         (1 << 20)
+#define M_DAM_BURST_LENGTH (0x3 << 18)
+#define M_MIPI_OUT_EN	   (1 << 15)
+#define M_EDP_OUT_EN       (1 << 14)
+#define M_HDMI_OUT_EN      (1 << 13)
+#define M_RGB_OUT_EN       (1 << 12)
+#define M_ALL_OUT_EN		\
+		(M_MIPI_OUT_EN | M_EDP_OUT_EN | M_HDMI_OUT_EN | M_RGB_OUT_EN)
+#define M_EDPI_WMS_FS      (1 << 10)
+#define M_EDPI_WMS_MODE    (1 << 9)
+#define M_EDPI_HALT_EN     (1 << 8)
+#define M_DOUB_CH_OVERLAP_NUM (0xf << 4)
+#define M_DOUB_CHANNEL_EN     (1 << 3)
+#define M_DIRECT_PATH_LAYER_SEL (0x3 << 1)
+#define M_DIRECT_PATH_EN       (1)
+
+#define V_AUTO_GATING_EN(x) (((x) & 1) << 23)
+#define V_STANDBY_EN(x)     (((x) & 1) << 22)
+#define V_DMA_STOP(x)       (((x) & 1) << 21)
+#define V_MMU_EN(x)         (((x) & 1) << 20)
+#define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18)
+#define V_MIPI_OUT_EN(x)      (((x) & 1) << 15)
+#define V_EDP_OUT_EN(x)       (((x) & 1) << 14)
+#define V_HDMI_OUT_EN(x)      (((x) & 1) << 13)
+#define V_RGB_OUT_EN(x)       (((x) & 1) << 12)
+#define V_EDPI_WMS_FS(x)      (((x) & 1) << 10)
+#define V_EDPI_WMS_MODE(x)    (((x) & 1) << 9)
+#define V_EDPI_HALT_EN(x)     (((x)&1)<<8)
+#define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4)
+#define V_DOUB_CHANNEL_EN(x)     (((x) & 1) << 3)
+#define V_DIRECT_PATH_LAYER_SEL(x) (((x) & 3) << 1)
+#define V_DIRECT_PATH_EN(x)       ((x) & 1)
+
+/* VOP_SYS_CTRL1 */
+#define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13)
+#define M_AXI_MAX_OUTSTANDING_EN  (1 << 12)
+#define M_NOC_WIN_QOS             (3 << 10)
+#define M_NOC_QOS_EN              (1 << 9)
+#define M_NOC_HURRY_THRESHOLD     (0x3f << 3)
+#define M_NOC_HURRY_VALUE         (0x3 << 1)
+#define M_NOC_HURRY_EN            (1)
+
+#define V_AXI_OUTSTANDING_MAX_NUM(x) (((x) & 0x1f) << 13)
+#define V_AXI_MAX_OUTSTANDING_EN(x)  (((x) & 1) << 12)
+#define V_NOC_WIN_QOS(x)             (((x) & 3) << 10)
+#define V_NOC_QOS_EN(x)              (((x) & 1) << 9)
+#define V_NOC_HURRY_THRESHOLD(x)     (((x) & 0x3f) << 3)
+#define V_NOC_HURRY_VALUE(x)         (((x) & 3) << 1)
+#define V_NOC_HURRY_EN(x)            ((x) & 1)
+
+/* VOP_DSP_CTRL0 */
+#define M_DSP_Y_MIR_EN              (1 << 23)
+#define M_DSP_X_MIR_EN              (1 << 22)
+#define M_DSP_YUV_CLIP              (1 << 21)
+#define M_DSP_CCIR656_AVG           (1 << 20)
+#define M_DSP_BLACK_EN              (1 << 19)
+#define M_DSP_BLANK_EN              (1 << 18)
+#define M_DSP_OUT_ZERO              (1 << 17)
+#define M_DSP_DUMMY_SWAP            (1 << 16)
+#define M_DSP_DELTA_SWAP            (1 << 15)
+#define M_DSP_RG_SWAP               (1 << 14)
+#define M_DSP_RB_SWAP               (1 << 13)
+#define M_DSP_BG_SWAP               (1 << 12)
+#define M_DSP_FIELD_POL             (1 << 11)
+#define M_DSP_INTERLACE             (1 << 10)
+#define M_DSP_DDR_PHASE             (1 << 9)
+#define M_DSP_DCLK_DDR              (1 << 8)
+#define M_DSP_DCLK_POL              (1 << 7)
+#define M_DSP_DEN_POL               (1 << 6)
+#define M_DSP_VSYNC_POL             (1 << 5)
+#define M_DSP_HSYNC_POL             (1 << 4)
+#define M_DSP_OUT_MODE              (0xf)
+
+#define V_DSP_Y_MIR_EN(x)              (((x) & 1) << 23)
+#define V_DSP_X_MIR_EN(x)              (((x) & 1) << 22)
+#define V_DSP_YUV_CLIP(x)              (((x) & 1) << 21)
+#define V_DSP_CCIR656_AVG(x)           (((x) & 1) << 20)
+#define V_DSP_BLACK_EN(x)              (((x) & 1) << 19)
+#define V_DSP_BLANK_EN(x)              (((x) & 1) << 18)
+#define V_DSP_OUT_ZERO(x)              (((x) & 1) << 17)
+#define V_DSP_DUMMY_SWAP(x)            (((x) & 1) << 16)
+#define V_DSP_DELTA_SWAP(x)            (((x) & 1) << 15)
+#define V_DSP_RG_SWAP(x)               (((x) & 1) << 14)
+#define V_DSP_RB_SWAP(x)               (((x) & 1) << 13)
+#define V_DSP_BG_SWAP(x)               (((x) & 1) << 12)
+#define V_DSP_FIELD_POL(x)             (((x) & 1) << 11)
+#define V_DSP_INTERLACE(x)             (((x) & 1) << 10)
+#define V_DSP_DDR_PHASE(x)             (((x) & 1) << 9)
+#define V_DSP_DCLK_DDR(x)              (((x) & 1) << 8)
+#define V_DSP_DCLK_POL(x)              (((x) & 1) << 7)
+#define V_DSP_DEN_POL(x)               (((x) & 1) << 6)
+#define V_DSP_VSYNC_POL(x)             (((x) & 1) << 5)
+#define V_DSP_HSYNC_POL(x)             (((x) & 1) << 4)
+#define V_DSP_PIN_POL(x)               (((x) & 0xf) << 4)
+#define V_DSP_OUT_MODE(x)              ((x) & 0xf)
+
+/* VOP_DSP_CTRL1 */
+#define V_RK3399_DSP_MIPI_POL(x)       ((x) << 28)
+#define V_RK3399_DSP_EDP_POL(x)        ((x) << 24)
+#define V_RK3399_DSP_HDMI_POL(x)       ((x) << 20)
+#define V_RK3399_DSP_LVDS_POL(x)       ((x) << 16)
+
+#define M_RK3399_DSP_MIPI_POL          (V_RK3399_DSP_MIPI_POL(0xf))
+#define M_RK3399_DSP_EDP_POL           (V_RK3399_DSP_EDP_POL(0xf))
+#define M_RK3399_DSP_HDMI_POL          (V_RK3399_DSP_HDMI_POL(0xf))
+#define M_RK3399_DSP_LVDS_POL          (V_RK3399_DSP_LVDS_POL(0xf))
+
+#define M_DSP_LAYER3_SEL               (3 << 14)
+#define M_DSP_LAYER2_SEL               (3 << 12)
+#define M_DSP_LAYER1_SEL               (3 << 10)
+#define M_DSP_LAYER0_SEL               (3 << 8)
+#define M_DITHER_UP_EN                 (1 << 6)
+#define M_DITHER_DOWN_SEL              (1 << 4)
+#define M_DITHER_DOWN_MODE             (1 << 3)
+#define M_DITHER_DOWN_EN               (1 << 2)
+#define M_PRE_DITHER_DOWN_EN           (1 << 1)
+#define M_DSP_LUT_EN                   (1)
+
+#define V_DSP_LAYER3_SEL(x)                (((x) & 3) << 14)
+#define V_DSP_LAYER2_SEL(x)                (((x) & 3) << 12)
+#define V_DSP_LAYER1_SEL(x)                (((x) & 3) << 10)
+#define V_DSP_LAYER0_SEL(x)                (((x) & 3) << 8)
+#define V_DITHER_UP_EN(x)                  (((x) & 1) << 6)
+#define V_DITHER_DOWN_SEL(x)               (((x) & 1) << 4)
+#define V_DITHER_DOWN_MODE(x)              (((x) & 1) << 3)
+#define V_DITHER_DOWN_EN(x)                (((x) & 1) << 2)
+#define V_PRE_DITHER_DOWN_EN(x)            (((x) & 1) << 1)
+#define V_DSP_LUT_EN(x)                    ((x)&1)
+
+/* VOP_DSP_BG */
+#define M_DSP_BG_RED     (0x3f << 20)
+#define M_DSP_BG_GREEN   (0x3f << 10)
+#define M_DSP_BG_BLUE    (0x3f << 0)
+
+#define V_DSP_BG_RED(x)     (((x) & 0x3f) << 20)
+#define V_DSP_BG_GREEN(x)   (((x) & 0x3f) << 10)
+#define V_DSP_BG_BLUE(x)    (((x) & 0x3f) << 0)
+
+/* VOP_WIN0_CTRL0 */
+#define M_WIN0_YUV_CLIP     (1 << 20)
+#define M_WIN0_CBR_DEFLICK  (1 << 19)
+#define M_WIN0_YRGB_DEFLICK  (1 << 18)
+#define M_WIN0_PPAS_ZERO_EN  (1 << 16)
+#define M_WIN0_UV_SWAP       (1 << 15)
+#define M_WIN0_MID_SWAP      (1 << 14)
+#define M_WIN0_ALPHA_SWAP    (1 << 13)
+#define M_WIN0_RB_SWAP       (1 << 12)
+#define M_WIN0_CSC_MODE      (3 << 10)
+#define M_WIN0_NO_OUTSTANDING (1 << 9)
+#define M_WIN0_INTERLACE_READ  (1 << 8)
+#define M_WIN0_LB_MODE         (7 << 5)
+#define M_WIN0_FMT_10          (1 << 4)
+#define M_WIN0_DATA_FMT        (7 << 1)
+#define M_WIN0_EN              (1 << 0)
+
+#define V_WIN0_YUV_CLIP(x)       (((x) & 1) << 20)
+#define V_WIN0_CBR_DEFLICK(x)    (((x) & 1) << 19)
+#define V_WIN0_YRGB_DEFLICK(x)   (((x) & 1) << 18)
+#define V_WIN0_PPAS_ZERO_EN(x)   (((x) & 1) << 16)
+#define V_WIN0_UV_SWAP(x)        (((x) & 1) << 15)
+#define V_WIN0_MID_SWAP(x)       (((x) & 1) << 14)
+#define V_WIN0_ALPHA_SWAP(x)     (((x) & 1) << 13)
+#define V_WIN0_RB_SWAP(x)        (((x) & 1) << 12)
+#define V_WIN0_CSC_MODE(x)       (((x) & 3) << 10)
+#define V_WIN0_NO_OUTSTANDING(x) (((x) & 1) << 9)
+#define V_WIN0_INTERLACE_READ(x)  (((x) & 1) << 8)
+#define V_WIN0_LB_MODE(x)         (((x) & 7) << 5)
+#define V_WIN0_FMT_10(x)          (((x) & 1) << 4)
+#define V_WIN0_DATA_FMT(x)        (((x) & 7) << 1)
+#define V_WIN0_EN(x)              ((x) & 1)
+
+/* VOP_WIN0_CTRL1 */
+#define M_WIN0_CBR_VSD_MODE        (1 << 31)
+#define M_WIN0_CBR_VSU_MODE        (1 << 30)
+#define M_WIN0_CBR_HSD_MODE        (3 << 28)
+#define M_WIN0_CBR_VER_SCL_MODE    (3 << 26)
+#define M_WIN0_CBR_HOR_SCL_MODE    (3 << 24)
+#define M_WIN0_YRGB_VSD_MODE       (1 << 23)
+#define M_WIN0_YRGB_VSU_MODE       (1 << 22)
+#define M_WIN0_YRGB_HSD_MODE       (3 << 20)
+#define M_WIN0_YRGB_VER_SCL_MODE   (3 << 18)
+#define M_WIN0_YRGB_HOR_SCL_MODE   (3 << 16)
+#define M_WIN0_LINE_LOAD_MODE      (1 << 15)
+#define M_WIN0_CBR_AXI_GATHER_NUM  (7 << 12)
+#define M_WIN0_YRGB_AXI_GATHER_NUM (0xf << 8)
+#define M_WIN0_VSD_CBR_GT2         (1 << 7)
+#define M_WIN0_VSD_CBR_GT4         (1 << 6)
+#define M_WIN0_VSD_YRGB_GT2        (1 << 5)
+#define M_WIN0_VSD_YRGB_GT4        (1 << 4)
+#define M_WIN0_BIC_COE_SEL         (3 << 2)
+#define M_WIN0_CBR_AXI_GATHER_EN   (1 << 1)
+#define M_WIN0_YRGB_AXI_GATHER_EN  (1)
+
+#define V_WIN0_CBR_VSD_MODE(x)        (((x) & 1) << 31)
+#define V_WIN0_CBR_VSU_MODE(x)        (((x) & 1) << 30)
+#define V_WIN0_CBR_HSD_MODE(x)        (((x) & 3) << 28)
+#define V_WIN0_CBR_VER_SCL_MODE(x)    (((x) & 3) << 26)
+#define V_WIN0_CBR_HOR_SCL_MODE(x)    (((x) & 3) << 24)
+#define V_WIN0_YRGB_VSD_MODE(x)       (((x) & 1) << 23)
+#define V_WIN0_YRGB_VSU_MODE(x)       (((x) & 1) << 22)
+#define V_WIN0_YRGB_HSD_MODE(x)       (((x) & 3) << 20)
+#define V_WIN0_YRGB_VER_SCL_MODE(x)   (((x) & 3) << 18)
+#define V_WIN0_YRGB_HOR_SCL_MODE(x)   (((x) & 3) << 16)
+#define V_WIN0_LINE_LOAD_MODE(x)      (((x) & 1) << 15)
+#define V_WIN0_CBR_AXI_GATHER_NUM(x)  (((x) & 7) << 12)
+#define V_WIN0_YRGB_AXI_GATHER_NUM(x) (((x) & 0xf) << 8)
+#define V_WIN0_VSD_CBR_GT2(x)         (((x) & 1) << 7)
+#define V_WIN0_VSD_CBR_GT4(x)         (((x) & 1) << 6)
+#define V_WIN0_VSD_YRGB_GT2(x)        (((x) & 1) << 5)
+#define V_WIN0_VSD_YRGB_GT4(x)        (((x) & 1) << 4)
+#define V_WIN0_BIC_COE_SEL(x)         (((x) & 3) << 2)
+#define V_WIN0_CBR_AXI_GATHER_EN(x)   (((x) & 1) << 1)
+#define V_WIN0_YRGB_AXI_GATHER_EN(x)  ((x) & 1)
+
+/*VOP_WIN0_COLOR_KEY*/
+#define M_WIN0_KEY_EN                 (1 << 31)
+#define M_WIN0_KEY_COLOR              (0x3fffffff)
+
+#define V_WIN0_KEY_EN(x)              (((x) & 1) << 31)
+#define V_WIN0_KEY_COLOR(x)           ((x) & 0x3fffffff)
+
+/* VOP_WIN0_VIR */
+#define V_ARGB888_VIRWIDTH(x)	(((x) & 0x3fff) << 0)
+#define V_RGB888_VIRWIDTH(x)	(((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0)
+#define V_RGB565_VIRWIDTH(x)	(((x / 2) & 0x3fff) << 0)
+#define YUV_VIRWIDTH(x)		(((x / 4) & 0x3fff) << 0)
+
+/* VOP_WIN0_ACT_INFO */
+#define V_ACT_HEIGHT(x)         (((x) & 0x1fff) << 16)
+#define V_ACT_WIDTH(x)          ((x) & 0x1fff)
+
+/* VOP_WIN0_DSP_INFO */
+#define V_DSP_HEIGHT(x)         (((x) & 0xfff) << 16)
+#define V_DSP_WIDTH(x)          ((x) & 0xfff)
+
+/* VOP_WIN0_DSP_ST */
+#define V_DSP_YST(x)            (((x) & 0x1fff) << 16)
+#define V_DSP_XST(x)            ((x) & 0x1fff)
+
+/* VOP_WIN0_SCL_OFFSET */
+#define V_WIN0_VS_OFFSET_CBR(x)     (((x) & 0xff) << 24)
+#define V_WIN0_VS_OFFSET_YRGB(x)    (((x) & 0xff) << 16)
+#define V_WIN0_HS_OFFSET_CBR(x)     (((x) & 0xff) << 8)
+#define V_WIN0_HS_OFFSET_YRGB(x)    ((x) & 0xff)
+
+#define V_HSYNC(x)		(((x)&0x1fff)<<0)   /* hsync pulse width */
+#define V_HORPRD(x)		(((x)&0x1fff)<<16)   /* horizontal period */
+#define V_VSYNC(x)		(((x)&0x1fff)<<0)
+#define V_VERPRD(x)		(((x)&0x1fff)<<16)
+
+#define V_HEAP(x)		(((x)&0x1fff)<<0)/* horizontal active end */
+#define V_HASP(x)		(((x)&0x1fff)<<16)/* horizontal active start */
+#define V_VAEP(x)		(((x)&0x1fff)<<0)
+#define V_VASP(x)		(((x)&0x1fff)<<16)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rv1108/boot0.h b/arch/arm/include/asm/arch-rv1108/boot0.h
new file mode 100644
index 0000000..2e78b07
--- /dev/null
+++ b/arch/arm/include/asm/arch-rv1108/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rv1108/gpio.h b/arch/arm/include/asm/arch-rv1108/gpio.h
new file mode 100644
index 0000000..eca79d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rv1108/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-s32v234/clock.h b/arch/arm/include/asm/arch-s32v234/clock.h
new file mode 100644
index 0000000..c600654
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/clock.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_BUS_CLK,
+	MXC_PERIPHERALS_CLK,
+	MXC_UART_CLK,
+	MXC_USDHC_CLK,
+	MXC_FEC_CLK,
+	MXC_I2C_CLK,
+};
+enum pll_type {
+	ARM_PLL = 0,
+	PERIPH_PLL,
+	ENET_PLL,
+	DDR_PLL,
+	VIDEO_PLL,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+void clock_init(void);
+
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-s32v234/ddr.h b/arch/arm/include/asm/arch-s32v234/ddr.h
new file mode 100644
index 0000000..8c709af
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/ddr.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_DDR_H__
+#define __ARCH_ARM_MACH_S32V234_DDR_H__
+
+#define DDR0	0
+#define DDR1	1
+
+/* DDR offset in MSCR register */
+#define _DDR0_RESET	168
+#define _DDR0_CLK0	169
+#define _DDR0_CAS	170
+#define _DDR0_RAS	171
+#define _DDR0_WE_B	172
+#define _DDR0_CKE0	173
+#define _DDR0_CKE1	174
+#define _DDR0_CS_B0	175
+#define _DDR0_CS_B1	176
+#define _DDR0_BA0	177
+#define _DDR0_BA1	178
+#define _DDR0_BA2	179
+#define _DDR0_A0	180
+#define _DDR0_A1	181
+#define _DDR0_A2	182
+#define _DDR0_A3	183
+#define _DDR0_A4	184
+#define _DDR0_A5	185
+#define _DDR0_A6	186
+#define _DDR0_A7	187
+#define _DDR0_A8	188
+#define _DDR0_A9	189
+#define _DDR0_A10	190
+#define _DDR0_A11	191
+#define _DDR0_A12	192
+#define _DDR0_A13	193
+#define _DDR0_A14	194
+#define _DDR0_A15	195
+#define _DDR0_DM0	196
+#define _DDR0_DM1	197
+#define _DDR0_DM2	198
+#define _DDR0_DM3	199
+#define _DDR0_DQS0	200
+#define _DDR0_DQS1	201
+#define _DDR0_DQS2	202
+#define _DDR0_DQS3	203
+#define _DDR0_D0	204
+#define _DDR0_D1	205
+#define _DDR0_D2	206
+#define _DDR0_D3	207
+#define _DDR0_D4	208
+#define _DDR0_D5	209
+#define _DDR0_D6	210
+#define _DDR0_D7	211
+#define _DDR0_D8	212
+#define _DDR0_D9	213
+#define _DDR0_D10	214
+#define _DDR0_D11	215
+#define _DDR0_D12	216
+#define _DDR0_D13	217
+#define _DDR0_D14	218
+#define _DDR0_D15	219
+#define _DDR0_D16	220
+#define _DDR0_D17	221
+#define _DDR0_D18	222
+#define _DDR0_D19	223
+#define _DDR0_D20	224
+#define _DDR0_D21	225
+#define _DDR0_D22	226
+#define _DDR0_D23	227
+#define _DDR0_D24	228
+#define _DDR0_D25	229
+#define _DDR0_D26	230
+#define _DDR0_D27	231
+#define _DDR0_D28	232
+#define _DDR0_D29	233
+#define _DDR0_D30	234
+#define _DDR0_D31	235
+#define _DDR0_ODT0	236
+#define _DDR0_ODT1	237
+#define _DDR0_ZQ	238
+#define _DDR1_RESET	239
+#define _DDR1_CLK0	240
+#define _DDR1_CAS	241
+#define _DDR1_RAS	242
+#define _DDR1_WE_B	243
+#define _DDR1_CKE0	244
+#define _DDR1_CKE1	245
+#define _DDR1_CS_B0	246
+#define _DDR1_CS_B1	247
+#define _DDR1_BA0	248
+#define _DDR1_BA1	249
+#define _DDR1_BA2	250
+#define _DDR1_A0	251
+#define _DDR1_A1	252
+#define _DDR1_A2	253
+#define _DDR1_A3	254
+#define _DDR1_A4	255
+#define _DDR1_A5	256
+#define _DDR1_A6	257
+#define _DDR1_A7	258
+#define _DDR1_A8	259
+#define _DDR1_A9	260
+#define _DDR1_A10	261
+#define _DDR1_A11	262
+#define _DDR1_A12	263
+#define _DDR1_A13	264
+#define _DDR1_A14	265
+#define _DDR1_A15	266
+#define _DDR1_DM0	267
+#define _DDR1_DM1	268
+#define _DDR1_DM2	269
+#define _DDR1_DM3	270
+#define _DDR1_DQS0	271
+#define _DDR1_DQS1	272
+#define _DDR1_DQS2	273
+#define _DDR1_DQS3	274
+#define _DDR1_D0	275
+#define _DDR1_D1	276
+#define _DDR1_D2	277
+#define _DDR1_D3	278
+#define _DDR1_D4	279
+#define _DDR1_D5	280
+#define _DDR1_D6	281
+#define _DDR1_D7	282
+#define _DDR1_D8	283
+#define _DDR1_D9	284
+#define _DDR1_D10	285
+#define _DDR1_D11	286
+#define _DDR1_D12	287
+#define _DDR1_D13	288
+#define _DDR1_D14	289
+#define _DDR1_D15	290
+#define _DDR1_D16	291
+#define _DDR1_D17	292
+#define _DDR1_D18	293
+#define _DDR1_D19	294
+#define _DDR1_D20	295
+#define _DDR1_D21	296
+#define _DDR1_D22	297
+#define _DDR1_D23	298
+#define _DDR1_D24	299
+#define _DDR1_D25	300
+#define _DDR1_D26	301
+#define _DDR1_D27	302
+#define _DDR1_D28	303
+#define _DDR1_D29	304
+#define _DDR1_D30	305
+#define _DDR1_D31	306
+#define _DDR1_ODT0	307
+#define _DDR1_ODT1	308
+#define _DDR1_ZQ	309
+
+#endif
diff --git a/arch/arm/include/asm/arch-s32v234/imx-regs.h b/arch/arm/include/asm/arch-s32v234/imx-regs.h
new file mode 100644
index 0000000..9a779cc
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/imx-regs.h
@@ -0,0 +1,328 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define IRAM_BASE_ADDR      0x3E800000	/* internal ram */
+#define IRAM_SIZE           0x00400000	/* 4MB */
+
+#define AIPS0_BASE_ADDR     (0x40000000UL)
+#define AIPS1_BASE_ADDR     (0x40080000UL)
+
+/* AIPS 0 */
+#define AXBS_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00000000)
+#define CSE3_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00001000)
+#define EDMA_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00002000)
+#define XRDC_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00004000)
+#define SWT0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0000A000)
+#define SWT1_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0000B000)
+#define STM0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0000D000)
+#define NIC301_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00010000)
+#define GC3000_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00020000)
+#define DEC200_DECODER_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00026000)
+#define DEC200_ENCODER_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00027000)
+#define TWOD_ACE_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00028000)
+#define MIPI_CSI0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00030000)
+#define DMAMUX0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00031000)
+#define ENET_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00032000)
+#define FLEXRAY_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00034000)
+#define MMDC0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00036000)
+#define MEW0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00037000)
+#define MONITOR_DDR0_BASE_ADDR			(AIPS0_BASE_ADDR + 0x00038000)
+#define MONITOR_CCI0_BASE_ADDR			(AIPS0_BASE_ADDR + 0x00039000)
+#define PIT0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0003A000)
+#define MC_CGM0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0003C000)
+#define MC_CGM1_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0003F000)
+#define MC_CGM2_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00042000)
+#define MC_CGM3_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00045000)
+#define MC_RGM_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00048000)
+#define MC_ME_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0004A000)
+#define MC_PCU_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0004B000)
+#define ADC0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0004D000)
+#define FLEXTIMER_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0004F000)
+#define I2C0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00051000)
+#define LINFLEXD0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00053000)
+#define FLEXCAN0_BASE_ADDR				(AIPS0_BASE_ADDR + 0x00055000)
+#define SPI0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00057000)
+#define SPI2_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00059000)
+#define CRC0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0005B000)
+#define USDHC_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0005D000)
+#define OCOTP_CONTROLLER_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0005F000)
+#define WKPU_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00063000)
+#define VIU0_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00064000)
+#define HPSMI_SRAM_CONTROLLER_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00068000)
+#define SIUL2_BASE_ADDR					(AIPS0_BASE_ADDR + 0x0006C000)
+#define SIPI_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00074000)
+#define LFAST_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00078000)
+#define SSE_BASE_ADDR					(AIPS0_BASE_ADDR + 0x00079000)
+#define SRC_SOC_BASE_ADDR				(AIPS0_BASE_ADDR + 0x0007C000)
+
+/* AIPS 1 */
+#define ERM_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000000000)
+#define MSCM_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000001000)
+#define SEMA42_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000002000)
+#define INTC_MON_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000003000)
+#define SWT2_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000004000)
+#define SWT3_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000005000)
+#define SWT4_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000006000)
+#define STM1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000007000)
+#define EIM_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000008000)
+#define APB_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000009000)
+#define XBIC_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000012000)
+#define MIPI_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000020000)
+#define DMAMUX1_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000021000)
+#define MMDC1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000022000)
+#define MEW1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000023000)
+#define DDR1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000024000)
+#define CCI1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000025000)
+#define QUADSPI0_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000026000)
+#define PIT1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00002A000)
+#define FCCU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000030000)
+#define FLEXTIMER_FTM1_BASE_ADDR		(AIPS1_BASE_ADDR + 0X000036000)
+#define I2C1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000038000)
+#define I2C2_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00003A000)
+#define LINFLEXD1_BASE_ADDR				(AIPS1_BASE_ADDR + 0X00003C000)
+#define FLEXCAN1_BASE_ADDR				(AIPS1_BASE_ADDR + 0X00003E000)
+#define SPI1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000040000)
+#define SPI3_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000042000)
+#define IPL_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000043000)
+#define CGM_CMU_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000044000)
+#define PMC_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000048000)
+#define CRC1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00004C000)
+#define TMU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00004E000)
+#define VIU1_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000050000)
+#define JPEG_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000054000)
+#define H264_DEC_BASE_ADDR				(AIPS1_BASE_ADDR + 0X000058000)
+#define H264_ENC_BASE_ADDR				(AIPS1_BASE_ADDR + 0X00005C000)
+#define MEMU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000060000)
+#define STCU_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000064000)
+#define SLFTST_CTRL_BASE_ADDR			(AIPS1_BASE_ADDR + 0X000066000)
+#define MCT_BASE_ADDR					(AIPS1_BASE_ADDR + 0X000068000)
+#define REP_BASE_ADDR					(AIPS1_BASE_ADDR + 0X00006A000)
+#define MBIST_CONTROLLER_BASE_ADDR		(AIPS1_BASE_ADDR + 0X00006C000)
+#define BOOT_LOADER_BASE_ADDR			(AIPS1_BASE_ADDR + 0X00006F000)
+
+/* TODO Remove this after the IOMUX framework is implemented */
+#define IOMUXC_BASE_ADDR SIUL2_BASE_ADDR
+
+/* MUX mode and PAD ctrl are in one register */
+#define CONFIG_IOMUX_SHARE_CONF_REG
+
+#define FEC_QUIRK_ENET_MAC
+#define I2C_QUIRK_REG
+
+/* MSCM interrupt router */
+#define MSCM_IRSPRC_CPn_EN		3
+#define MSCM_IRSPRC_NUM			176
+#define MSCM_CPXTYPE_RYPZ_MASK		0xFF
+#define MSCM_CPXTYPE_RYPZ_OFFSET	0
+#define MSCM_CPXTYPE_PERS_MASK		0xFFFFFF00
+#define MSCM_CPXTYPE_PERS_OFFSET	8
+#define MSCM_CPXTYPE_PERS_A53		0x413533
+#define MSCM_CPXTYPE_PERS_CM4		0x434d34
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32 bmr1;
+	u32 bmr2;
+	u32 gpr1_boot;
+	u32 reserved_0x00C[61];
+	u32 gpr1;
+	u32 gpr2;
+	u32 gpr3;
+	u32 gpr4;
+	u32 gpr5;
+	u32 gpr6;
+	u32 gpr7;
+	u32 reserved_0x11C[1];
+	u32 gpr9;
+	u32 gpr10;
+	u32 gpr11;
+	u32 gpr12;
+	u32 gpr13;
+	u32 gpr14;
+	u32 gpr15;
+	u32 gpr16;
+	u32 reserved_0x140[1];
+	u32 gpr17;
+	u32 gpr18;
+	u32 gpr19;
+	u32 gpr20;
+	u32 gpr21;
+	u32 gpr22;
+	u32 gpr23;
+	u32 gpr24;
+	u32 gpr25;
+	u32 gpr26;
+	u32 gpr27;
+	u32 reserved_0x16C[5];
+	u32 pcie_config1;
+	u32 ddr_self_ref_ctrl;
+	u32 pcie_config0;
+	u32 reserved_0x18C[4];
+	u32 soc_misc_config2;
+};
+
+/* SRC registers definitions */
+
+/* SRC_GPR1 */
+#define SRC_GPR1_PLL_SOURCE(pll,val)( ((val) & SRC_GPR1_PLL_SOURCE_MASK) << \
+										(SRC_GPR1_PLL_OFFSET + (pll)) )
+#define SRC_GPR1_PLL_SOURCE_MASK	(0x1)
+
+#define SRC_GPR1_PLL_OFFSET			(27)
+#define SRC_GPR1_FIRC_CLK_SOURCE	(0x0)
+#define SRC_GPR1_XOSC_CLK_SOURCE	(0x1)
+
+/* Periodic Interrupt Timer (PIT) */
+struct pit_reg {
+	u32 mcr;
+	u32 recv0[55];
+	u32 ltmr64h;
+	u32 ltmr64l;
+	u32 recv1[6];
+	u32 ldval0;
+	u32 cval0;
+	u32 tctrl0;
+	u32 tflg0;
+	u32 ldval1;
+	u32 cval1;
+	u32 tctrl1;
+	u32 tflg1;
+	u32 ldval2;
+	u32 cval2;
+	u32 tctrl2;
+	u32 tflg2;
+	u32 ldval3;
+	u32 cval3;
+	u32 tctrl3;
+	u32 tflg3;
+	u32 ldval4;
+	u32 cval4;
+	u32 tctrl4;
+	u32 tflg4;
+	u32 ldval5;
+	u32 cval5;
+	u32 tctrl5;
+	u32 tflg5;
+};
+
+/* Watchdog Timer (WDOG) */
+struct wdog_regs {
+	u32 cr;
+	u32 ir;
+	u32 to;
+	u32 wn;
+	u32 sr;
+	u32 co;
+	u32 sk;
+};
+
+/* UART */
+struct linflex_fsl {
+	u32 lincr1;
+	u32 linier;
+	u32 linsr;
+	u32 linesr;
+	u32 uartcr;
+	u32 uartsr;
+	u32 lintcsr;
+	u32 linocr;
+	u32 lintocr;
+	u32 linfbrr;
+	u32 linibrr;
+	u32 lincfr;
+	u32 lincr2;
+	u32 bidr;
+	u32 bdrl;
+	u32 bdrm;
+	u32 ifer;
+	u32 ifmi;
+	u32 ifmr;
+	u32 ifcr0;
+	u32 ifcr1;
+	u32 ifcr2;
+	u32 ifcr3;
+	u32 ifcr4;
+	u32 ifcr5;
+	u32 ifcr6;
+	u32 ifcr7;
+	u32 ifcr8;
+	u32 ifcr9;
+	u32 ifcr10;
+	u32 ifcr11;
+	u32 ifcr12;
+	u32 ifcr13;
+	u32 ifcr14;
+	u32 ifcr15;
+	u32 gcr;
+	u32 uartpto;
+	u32 uartcto;
+	u32 dmatxe;
+	u32 dmarxe;
+};
+
+/* MSCM Interrupt Router */
+struct mscm_ir {
+	u32 cpxtype;		/* Processor x Type Register                    */
+	u32 cpxnum;		/* Processor x Number Register                  */
+	u32 cpxmaster;		/* Processor x Master Number Register   */
+	u32 cpxcount;		/* Processor x Count Register                   */
+	u32 cpxcfg0;		/* Processor x Configuration 0 Register */
+	u32 cpxcfg1;		/* Processor x Configuration 1 Register */
+	u32 cpxcfg2;		/* Processor x Configuration 2 Register */
+	u32 cpxcfg3;		/* Processor x Configuration 3 Register */
+	u32 cp0type;		/* Processor 0 Type Register                    */
+	u32 cp0num;		/* Processor 0 Number Register                  */
+	u32 cp0master;		/* Processor 0 Master Number Register   */
+	u32 cp0count;		/* Processor 0 Count Register                   */
+	u32 cp0cfg0;		/* Processor 0 Configuration 0 Register */
+	u32 cp0cfg1;		/* Processor 0 Configuration 1 Register */
+	u32 cp0cfg2;		/* Processor 0 Configuration 2 Register */
+	u32 cp0cfg3;		/* Processor 0 Configuration 3 Register */
+	u32 cp1type;		/* Processor 1 Type Register                    */
+	u32 cp1num;		/* Processor 1 Number Register                  */
+	u32 cp1master;		/* Processor 1 Master Number Register   */
+	u32 cp1count;		/* Processor 1 Count Register                   */
+	u32 cp1cfg0;		/* Processor 1 Configuration 0 Register */
+	u32 cp1cfg1;		/* Processor 1 Configuration 1 Register */
+	u32 cp1cfg2;		/* Processor 1 Configuration 2 Register */
+	u32 cp1cfg3;		/* Processor 1 Configuration 3 Register */
+	u32 reserved_0x060[232];
+	u32 ocmdr0;		/* On-Chip Memory Descriptor Register   */
+	u32 reserved_0x404[2];
+	u32 ocmdr3;		/* On-Chip Memory Descriptor Register   */
+	u32 reserved_0x410[28];
+	u32 tcmdr[4];		/* Generic Tightly Coupled Memory Descriptor Register   */
+	u32 reserved_0x490[28];
+	u32 cpce0;		/* Core Parity Checking Enable Register 0                               */
+	u32 reserved_0x504[191];
+	u32 ircp0ir;		/* Interrupt Router CP0 Interrupt Register                              */
+	u32 ircp1ir;		/* Interrupt Router CP1 Interrupt Register                              */
+	u32 reserved_0x808[6];
+	u32 ircpgir;		/* Interrupt Router CPU Generate Interrupt Register             */
+	u32 reserved_0x824[23];
+	u16 irsprc[176];	/* Interrupt Router Shared Peripheral Routing Control Register  */
+	u32 reserved_0x9e0[136];
+	u32 iahbbe0;		/* Gasket Burst Enable Register                                                 */
+	u32 reserved_0xc04[63];
+	u32 ipcge;		/* Interconnect Parity Checking Global Enable Register  */
+	u32 reserved_0xd04[3];
+	u32 ipce[4];		/* Interconnect Parity Checking Enable Register                 */
+	u32 reserved_0xd20[8];
+	u32 ipcgie;		/* Interconnect Parity Checking Global Injection Enable Register        */
+	u32 reserved_0xd44[3];
+	u32 ipcie[4];		/* Interconnect Parity Checking Injection Enable Register       */
+};
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/lpddr2.h b/arch/arm/include/asm/arch-s32v234/lpddr2.h
new file mode 100644
index 0000000..c5efee5
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/lpddr2.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015-2016, Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__
+#define __ARCH_ARM_MACH_S32V234_LPDDR2_H__
+
+/* definitions for LPDDR2 PAD values */
+#define LPDDR2_CLK0_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 |			\
+	 SIUL2_MSCR_DCYCLE_TRIM_NONE)
+#define LPDDR2_CKEn_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+	 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
+#define LPDDR2_CS_Bn_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+	 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
+#define LPDDR2_DMn_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\
+	 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm)
+#define LPDDR2_DQSn_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |	\
+	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN |						\
+	 SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE)
+#define LPDDR2_An_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |	\
+	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT		|	\
+	 SIUL2_MSCR_PUS_100K_UP)
+#define LPDDR2_Dn_PAD	\
+	(SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |	\
+	 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT		|	\
+	 SIUL2_MSCR_PUS_100K_UP)
+
+#define _MDCTL							0x03010000
+
+#define MMDC_MDSCR_CFG_VALUE			0x00008000	/* Set MDSCR[CON_REQ] (configuration request) */
+#define MMDC_MDCFG0_VALUE				0x464F61A5	/* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */
+#define MMDC_MDCFG1_VALUE				0x00180E63	/* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */
+#define MMDC_MDCFG2_VALUE				0x000000DD	/* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */
+#define MMDC_MDCFG3LP_VALUE				0x001F099B	/* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */
+#define MMDC_MDOTC_VALUE				0x00000000	/* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */
+#define MMDC_MDMISC_VALUE				0x00001688	/* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */
+#define MMDC_MDOR_VALUE					0x00000010	/* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */
+#define MMDC_MPMUR0_VALUE				0x00000800	/* Force delay line initialisation */
+#define MMDC_MDSCR_RST_VALUE			0x003F8030	/* Reset command CS0 */
+#define MMDC_MPZQLP2CTL_VALUE			0x1B5F0109	/* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */
+#define MMDC_MPZQHWCTRL_VALUE			0xA0010003	/* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */
+#define MMDC_MDSCR_MR1_VALUE			0xC2018030	/* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */
+#define MMDC_MDSCR_MR2_VALUE			0x06028030	/* Configure MR2: RL=8, WL=4 */
+#define MMDC_MDSCR_MR3_VALUE			0x01038030	/* Configure MR3: DS=34R */
+#define MMDC_MDSCR_MR10_VALUE			0xFF0A8030	/* Configure MR10: Calibration at init */
+#define MMDC_MDASP_MODULE0_VALUE		0x0000007F	/* 2Gb, 256 MB memory so CS0 is 256 MB  (0x90000000) */
+#define MMDC_MPRDDLCTL_MODULE0_VALUE	0x4D4B4F4B	/* Read delay line offsets */
+#define MMDC_MPWRDLCTL_MODULE0_VALUE	0x38383737	/* Write delay line offsets */
+#define MMDC_MPDGCTRL0_MODULE0_VALUE	0x20000000	/* Read DQS gating control 0 (disabled) */
+#define MMDC_MPDGCTRL1_MODULE0_VALUE	0x00000000	/* Read DQS gating control 1 */
+#define MMDC_MDASP_MODULE1_VALUE		0x0000007F	/* 2Gb, 256 MB memory so CS0 is 256 MB  (0xD0000000) */
+#define MMDC_MPRDDLCTL_MODULE1_VALUE	0x4D4B4F4B	/* Read delay line offsets */
+#define MMDC_MPWRDLCTL_MODULE1_VALUE	0x38383737	/* Write delay line offsets */
+#define MMDC_MPDGCTRL0_MODULE1_VALUE	0x20000000	/* Read DQS gating control 0 (disabled) */
+#define MMDC_MPDGCTRL1_MODULE1_VALUE	0x00000000	/* Read DQS gating control 1 */
+#define MMDC_MDRWD_VALUE				0x0F9F26D2	/* Read/write command delay - default used */
+#define MMDC_MDPDC_VALUE				0x00020024	/* Power down control */
+#define MMDC_MDREF_VALUE				0x30B01800	/* Refresh control */
+#define MMDC_MPODTCTRL_VALUE			0x00000000	/* No ODT */
+#define MMDC_MDSCR_DEASSERT_VALUE				0x00000000	/* Deassert the configuration request */
+
+/* set I/O pads for DDR */
+void lpddr2_config_iomux(uint8_t module);
+void config_mmdc(uint8_t module);
+
+#endif
diff --git a/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
new file mode 100644
index 0000000..957d48f
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mc_cgm_regs.h
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
+#define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+/* MC_CGM registers definitions */
+/* MC_CGM_SC_SS */
+#define CGM_SC_SS(cgm_addr)			( ((cgm_addr) + 0x000007E4) )
+#define MC_CGM_SC_SEL_FIRC			(0x0)
+#define MC_CGM_SC_SEL_XOSC			(0x1)
+#define MC_CGM_SC_SEL_ARMPLL		(0x2)
+#define MC_CGM_SC_SEL_CLKDISABLE	(0xF)
+
+/* MC_CGM_SC_DCn */
+#define CGM_SC_DCn(cgm_addr,dc)		( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )
+#define MC_CGM_SC_DCn_PREDIV(val)	(MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET))
+#define MC_CGM_SC_DCn_PREDIV_MASK	(0x00070000)
+#define MC_CGM_SC_DCn_PREDIV_OFFSET	(16)
+#define MC_CGM_SC_DCn_DE			(1 << 31)
+#define MC_CGM_SC_SEL_MASK			(0x0F000000)
+#define MC_CGM_SC_SEL_OFFSET		(24)
+
+/* MC_CGM_ACn_DCm */
+#define CGM_ACn_DCm(cgm_addr,ac,dc)		( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )
+#define MC_CGM_ACn_DCm_PREDIV(val)		(MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET))
+
+/*
+ * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown
+ * that the 5th bit is always ignored during writes if the current
+ * MC_CGM_ACn_DCm_PREDIV field has only 4 bits
+ *
+ * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits
+ *
+ * This should be changed if any problems occur.
+ */
+#define MC_CGM_ACn_DCm_PREDIV_MASK		(0x001F0000)
+#define MC_CGM_ACn_DCm_PREDIV_OFFSET	(16)
+#define MC_CGM_ACn_DCm_DE				(1 << 31)
+
+/*
+ * MC_CGM_ACn_SC/MC_CGM_ACn_SS
+ */
+#define CGM_ACn_SC(cgm_addr,ac)			((cgm_addr + 0x00000800) + ((ac) * 0x20))
+#define CGM_ACn_SS(cgm_addr,ac)			((cgm_addr + 0x00000804) + ((ac) * 0x20))
+#define MC_CGM_ACn_SEL_MASK				(0x07000000)
+#define MC_CGM_ACn_SEL_SET(source)		(MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET))
+#define MC_CGM_ACn_SEL_OFFSET			(24)
+
+#define MC_CGM_ACn_SEL_FIRC				(0x0)
+#define MC_CGM_ACn_SEL_XOSC				(0x1)
+#define MC_CGM_ACn_SEL_ARMPLL			(0x2)
+/*
+ * According to the manual some PLL can be divided by X (X={1,3,5}):
+ * PERPLLDIVX, VIDEOPLLDIVX.
+ */
+#define MC_CGM_ACn_SEL_PERPLLDIVX		(0x3)
+#define MC_CGM_ACn_SEL_ENETPLL			(0x4)
+#define MC_CGM_ACn_SEL_DDRPLL			(0x5)
+#define MC_CGM_ACn_SEL_EXTSRCPAD		(0x7)
+#define MC_CGM_ACn_SEL_SYSCLK			(0x8)
+#define MC_CGM_ACn_SEL_VIDEOPLLDIVX		(0x9)
+#define MC_CGM_ACn_SEL_PERCLK			(0xA)
+
+/* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */
+#define PLLDIG_PLLDV(pll)				((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))
+#define PLLDIG_PLLDV_MFD(div)			(PLLDIG_PLLDV_MFD_MASK & (div))
+#define PLLDIG_PLLDV_MFD_MASK			(0x000000FF)
+
+/*
+ * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to
+ * the reference manual. This other value respect the formula 2^[RFDPHIBY+1]
+ */
+#define PLLDIG_PLLDV_RFDPHI_SET(val)	(PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET))
+#define PLLDIG_PLLDV_RFDPHI_MASK		(0x003F0000)
+#define PLLDIG_PLLDV_RFDPHI_MAXVALUE	(0x3F)
+#define PLLDIG_PLLDV_RFDPHI_OFFSET		(16)
+
+#define PLLDIG_PLLDV_RFDPHI1_SET(val)	(PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET))
+#define PLLDIG_PLLDV_RFDPHI1_MASK		(0x7E000000)
+#define PLLDIG_PLLDV_RFDPHI1_MAXVALUE	(0x3F)
+#define PLLDIG_PLLDV_RFDPHI1_OFFSET		(25)
+
+#define PLLDIG_PLLDV_PREDIV_SET(val)	(PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET))
+#define PLLDIG_PLLDV_PREDIV_MASK		(0x00007000)
+#define PLLDIG_PLLDV_PREDIV_MAXVALUE	(0x7)
+#define PLLDIG_PLLDV_PREDIV_OFFSET		(12)
+
+/* PLLDIG PLL Fractional  Divide Register (PLLDIG_PLLFD) */
+#define PLLDIG_PLLFD(pll)				((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))
+#define PLLDIG_PLLFD_MFN_SET(val)		(PLLDIG_PLLFD_MFN_MASK & (val))
+#define PLLDIG_PLLFD_MFN_MASK			(0x00007FFF)
+#define PLLDIG_PLLFD_SMDEN				(1 << 30)
+
+/* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */
+#define PLLDIG_PLLCAL1(pll)				((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))
+#define PLLDIG_PLLCAL1_NDAC1_SET(val)	(PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET))
+#define PLLDIG_PLLCAL1_NDAC1_OFFSET		(24)
+#define PLLDIG_PLLCAL1_NDAC1_MASK		(0x7F000000)
+
+/* Digital Frequency Synthesizer (DFS) */
+/* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */
+#define DFS0_BASE_ADDR				(MC_CGM0_BASE_ADDR + 0x00000040)
+
+/* DFS DLL Program Register 1 */
+#define DFS_DLLPRG1(pll)			(DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80))
+
+#define DFS_DLLPRG1_V2IGC_SET(val)	(DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET))
+#define DFS_DLLPRG1_V2IGC_OFFSET	(0)
+#define DFS_DLLPRG1_V2IGC_MASK		(0x00000007)
+
+#define DFS_DLLPRG1_LCKWT_SET(val)		(DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET))
+#define DFS_DLLPRG1_LCKWT_OFFSET		(4)
+#define DFS_DLLPRG1_LCKWT_MASK			(0x00000030)
+
+#define DFS_DLLPRG1_DACIN_SET(val)		(DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET))
+#define DFS_DLLPRG1_DACIN_OFFSET		(6)
+#define DFS_DLLPRG1_DACIN_MASK			(0x000001C0)
+
+#define DFS_DLLPRG1_CALBYPEN_SET(val)	(DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET))
+#define DFS_DLLPRG1_CALBYPEN_OFFSET		(9)
+#define DFS_DLLPRG1_CALBYPEN_MASK		(0x00000200)
+
+#define DFS_DLLPRG1_VSETTLCTRL_SET(val)	(DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET))
+#define DFS_DLLPRG1_VSETTLCTRL_OFFSET	(10)
+#define DFS_DLLPRG1_VSETTLCTRL_MASK		(0x00000C00)
+
+#define DFS_DLLPRG1_CPICTRL_SET(val)	(DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET))
+#define DFS_DLLPRG1_CPICTRL_OFFSET		(12)
+#define DFS_DLLPRG1_CPICTRL_MASK		(0x00007000)
+
+/* DFS Control Register (DFS_CTRL) */
+#define DFS_CTRL(pll)					(DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80))
+#define DFS_CTRL_DLL_LOLIE				(1 << 0)
+#define DFS_CTRL_DLL_RESET				(1 << 1)
+
+/* DFS Port Status Register (DFS_PORTSR) */
+#define DFS_PORTSR(pll)						(DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80))
+/* DFS Port Reset Register (DFS_PORTRESET) */
+#define DFS_PORTRESET(pll)					(DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80))
+#define DFS_PORTRESET_PORTRESET_SET(val)	(DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET))
+#define DFS_PORTRESET_PORTRESET_MAXVAL		(0xF)
+#define DFS_PORTRESET_PORTRESET_MASK		(0x0000000F)
+#define DFS_PORTRESET_PORTRESET_OFFSET		(0)
+
+/* DFS Divide Register Portn (DFS_DVPORTn) */
+#define DFS_DVPORTn(pll,n)			(DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4)))
+
+/*
+ * The mathematical formula for fdfs_clockout is the following:
+ * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) )
+ */
+#define DFS_DVPORTn_MFI_SET(val)	(DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) )
+#define DFS_DVPORTn_MFN_SET(val)	(DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) )
+#define DFS_DVPORTn_MFI_MASK		(0x0000FF00)
+#define DFS_DVPORTn_MFN_MASK		(0x000000FF)
+#define DFS_DVPORTn_MFI_MAXVAL		(0xFF)
+#define DFS_DVPORTn_MFN_MAXVAL		(0xFF)
+#define DFS_DVPORTn_MFI_OFFSET		(8)
+#define DFS_DVPORTn_MFN_OFFSET		(0)
+#define DFS_MAXNUMBER				(4)
+
+#define DFS_PARAMS_Nr				(3)
+
+/* Frequencies are in Hz */
+#define FIRC_CLK_FREQ				(48000000)
+#define XOSC_CLK_FREQ				(40000000)
+
+#define PLL_MIN_FREQ				(650000000)
+#define PLL_MAX_FREQ				(1300000000)
+
+#define ARM_PLL_PHI0_FREQ			(1000000000)
+#define ARM_PLL_PHI1_FREQ			(1000000000)
+/* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
+#define ARM_PLL_PHI1_DFS1_EN		(1)
+#define ARM_PLL_PHI1_DFS1_MFI		(3)
+#define ARM_PLL_PHI1_DFS1_MFN		(194)
+/* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
+#define ARM_PLL_PHI1_DFS2_EN		(1)
+#define ARM_PLL_PHI1_DFS2_MFI		(1)
+#define ARM_PLL_PHI1_DFS2_MFN		(170)
+/* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
+#define ARM_PLL_PHI1_DFS3_EN		(1)
+#define ARM_PLL_PHI1_DFS3_MFI		(1)
+#define ARM_PLL_PHI1_DFS3_MFN		(170)
+#define ARM_PLL_PHI1_DFS_Nr			(3)
+#define ARM_PLL_PLLDV_PREDIV		(2)
+#define ARM_PLL_PLLDV_MFD			(50)
+#define ARM_PLL_PLLDV_MFN			(0)
+
+#define PERIPH_PLL_PHI0_FREQ		(400000000)
+#define PERIPH_PLL_PHI1_FREQ		(100000000)
+#define PERIPH_PLL_PHI1_DFS_Nr		(0)
+#define PERIPH_PLL_PLLDV_PREDIV		(1)
+#define PERIPH_PLL_PLLDV_MFD		(30)
+#define PERIPH_PLL_PLLDV_MFN		(0)
+
+#define ENET_PLL_PHI0_FREQ			(500000000)
+#define ENET_PLL_PHI1_FREQ			(1000000000)
+/* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
+#define ENET_PLL_PHI1_DFS1_EN		(1)
+#define ENET_PLL_PHI1_DFS1_MFI		(2)
+#define ENET_PLL_PHI1_DFS1_MFN		(219)
+/* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
+#define ENET_PLL_PHI1_DFS2_EN		(1)
+#define ENET_PLL_PHI1_DFS2_MFI		(2)
+#define ENET_PLL_PHI1_DFS2_MFN		(219)
+/* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
+#define ENET_PLL_PHI1_DFS3_EN		(1)
+#define ENET_PLL_PHI1_DFS3_MFI		(3)
+#define ENET_PLL_PHI1_DFS3_MFN		(32)
+/* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
+#define ENET_PLL_PHI1_DFS4_EN		(1)
+#define ENET_PLL_PHI1_DFS4_MFI		(2)
+#define ENET_PLL_PHI1_DFS4_MFN		(0)
+#define ENET_PLL_PHI1_DFS_Nr		(4)
+#define ENET_PLL_PLLDV_PREDIV		(2)
+#define ENET_PLL_PLLDV_MFD			(50)
+#define ENET_PLL_PLLDV_MFN			(0)
+
+#define DDR_PLL_PHI0_FREQ			(533000000)
+#define DDR_PLL_PHI1_FREQ			(1066000000)
+/* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
+#define DDR_PLL_PHI1_DFS1_EN		(1)
+#define DDR_PLL_PHI1_DFS1_MFI		(2)
+#define DDR_PLL_PHI1_DFS1_MFN		(33)
+/* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */
+#define DDR_PLL_PHI1_DFS2_EN		(1)
+#define DDR_PLL_PHI1_DFS2_MFI		(2)
+#define DDR_PLL_PHI1_DFS2_MFN		(33)
+/* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */
+#define DDR_PLL_PHI1_DFS3_EN		(1)
+#define DDR_PLL_PHI1_DFS3_MFI		(3)
+#define DDR_PLL_PHI1_DFS3_MFN		(11)
+#define DDR_PLL_PHI1_DFS_Nr			(3)
+#define DDR_PLL_PLLDV_PREDIV		(2)
+#define DDR_PLL_PLLDV_MFD			(53)
+#define DDR_PLL_PLLDV_MFN			(6144)
+
+#define VIDEO_PLL_PHI0_FREQ			(600000000)
+#define VIDEO_PLL_PHI1_FREQ			(0)
+#define VIDEO_PLL_PHI1_DFS_Nr		(0)
+#define VIDEO_PLL_PLLDV_PREDIV		(1)
+#define VIDEO_PLL_PLLDV_MFD			(30)
+#define VIDEO_PLL_PLLDV_MFN			(0)
+
+#endif
+
+#endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mc_me_regs.h b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h
new file mode 100644
index 0000000..1671af4
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mc_me_regs.h
@@ -0,0 +1,198 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
+#define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+/* MC_ME registers definitions */
+
+/* MC_ME_GS */
+#define MC_ME_GS						(MC_ME_BASE_ADDR + 0x00000000)
+
+#define MC_ME_GS_S_SYSCLK_FIRC			(0x0 << 0)
+#define MC_ME_GS_S_SYSCLK_FXOSC			(0x1 << 0)
+#define MC_ME_GS_S_SYSCLK_ARMPLL		(0x2 << 0)
+#define MC_ME_GS_S_STSCLK_DISABLE		(0xF << 0)
+#define MC_ME_GS_S_FIRC					(1 << 4)
+#define MC_ME_GS_S_XOSC					(1 << 5)
+#define MC_ME_GS_S_ARMPLL				(1 << 6)
+#define MC_ME_GS_S_PERPLL				(1 << 7)
+#define MC_ME_GS_S_ENETPLL				(1 << 8)
+#define MC_ME_GS_S_DDRPLL				(1 << 9)
+#define MC_ME_GS_S_VIDEOPLL				(1 << 10)
+#define MC_ME_GS_S_MVR					(1 << 20)
+#define MC_ME_GS_S_PDO					(1 << 23)
+#define MC_ME_GS_S_MTRANS				(1 << 27)
+#define MC_ME_GS_S_CRT_MODE_RESET		(0x0 << 28)
+#define MC_ME_GS_S_CRT_MODE_TEST		(0x1 << 28)
+#define MC_ME_GS_S_CRT_MODE_DRUN		(0x3 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN0		(0x4 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN1		(0x5 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN2		(0x6 << 28)
+#define MC_ME_GS_S_CRT_MODE_RUN3		(0x7 << 28)
+
+/* MC_ME_MCTL */
+#define MC_ME_MCTL						(MC_ME_BASE_ADDR + 0x00000004)
+
+#define MC_ME_MCTL_KEY					(0x00005AF0)
+#define MC_ME_MCTL_INVERTEDKEY			(0x0000A50F)
+#define MC_ME_MCTL_RESET				(0x0 << 28)
+#define MC_ME_MCTL_TEST					(0x1 << 28)
+#define MC_ME_MCTL_DRUN					(0x3 << 28)
+#define MC_ME_MCTL_RUN0					(0x4 << 28)
+#define MC_ME_MCTL_RUN1					(0x5 << 28)
+#define MC_ME_MCTL_RUN2					(0x6 << 28)
+#define MC_ME_MCTL_RUN3					(0x7 << 28)
+
+/* MC_ME_ME */
+#define MC_ME_ME						(MC_ME_BASE_ADDR + 0x00000008)
+
+#define MC_ME_ME_RESET_FUNC				(1 << 0)
+#define MC_ME_ME_TEST					(1 << 1)
+#define MC_ME_ME_DRUN					(1 << 3)
+#define MC_ME_ME_RUN0					(1 << 4)
+#define MC_ME_ME_RUN1					(1 << 5)
+#define MC_ME_ME_RUN2					(1 << 6)
+#define MC_ME_ME_RUN3					(1 << 7)
+
+/* MC_ME_RUN_PCn */
+#define MC_ME_RUN_PCn(n)				(MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n))
+
+#define MC_ME_RUN_PCn_RESET				(1 << 0)
+#define MC_ME_RUN_PCn_TEST				(1 << 1)
+#define MC_ME_RUN_PCn_DRUN				(1 << 3)
+#define MC_ME_RUN_PCn_RUN0				(1 << 4)
+#define MC_ME_RUN_PCn_RUN1				(1 << 5)
+#define MC_ME_RUN_PCn_RUN2				(1 << 6)
+#define MC_ME_RUN_PCn_RUN3				(1 << 7)
+
+/*
+ * MC_ME_RESET_MC/MC_ME_TEST_MC
+ * MC_ME_DRUN_MC
+ * MC_ME_RUNn_MC
+ */
+#define MC_ME_RESET_MC						(MC_ME_BASE_ADDR + 0x00000020)
+#define MC_ME_TEST_MC						(MC_ME_BASE_ADDR + 0x00000024)
+#define MC_ME_DRUN_MC						(MC_ME_BASE_ADDR + 0x0000002C)
+#define MC_ME_RUNn_MC(n)					(MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n))
+
+#define MC_ME_RUNMODE_MC_SYSCLK(val)	(MC_ME_RUNMODE_MC_SYSCLK_MASK & (val))
+#define MC_ME_RUNMODE_MC_SYSCLK_MASK	(0x0000000F)
+#define MC_ME_RUNMODE_MC_FIRCON			(1 << 4)
+#define MC_ME_RUNMODE_MC_XOSCON			(1 << 5)
+#define MC_ME_RUNMODE_MC_PLL(pll)		(1 << (6 + (pll)))
+#define MC_ME_RUNMODE_MC_MVRON			(1 << 20)
+#define MC_ME_RUNMODE_MC_PDO			(1 << 23)
+#define MC_ME_RUNMODE_MC_PWRLVL0		(1 << 28)
+#define MC_ME_RUNMODE_MC_PWRLVL1		(1 << 29)
+#define MC_ME_RUNMODE_MC_PWRLVL2		(1 << 30)
+
+/* MC_ME_DRUN_SEC_CC_I */
+#define MC_ME_DRUN_SEC_CC_I					(MC_ME_BASE_ADDR + 0x260)
+/* MC_ME_RUNn_SEC_CC_I */
+#define MC_ME_RUNn_SEC_CC_I(n)				(MC_ME_BASE_ADDR + 0x270 + (n) * 0x10)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset)	((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET	(4)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET	(8)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET	(12)
+#define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK		(0x3)
+
+/*
+ * ME_PCTLn
+ * Please note that these registers are 8 bits width, so
+ * the operations over them should be done using 8 bits operations.
+ */
+#define MC_ME_PCTLn_RUNPCm(n)			( (n) & MC_ME_PCTLn_RUNPCm_MASK )
+#define MC_ME_PCTLn_RUNPCm_MASK			(0x7)
+
+/* DEC200 Peripheral Control Register		*/
+#define MC_ME_PCTL39	(MC_ME_BASE_ADDR + 0x000000E4)
+/* 2D-ACE Peripheral Control Register		*/
+#define MC_ME_PCTL40	(MC_ME_BASE_ADDR + 0x000000EB)
+/* ENET Peripheral Control Register		*/
+#define MC_ME_PCTL50	(MC_ME_BASE_ADDR + 0x000000F1)
+/* DMACHMUX0 Peripheral Control Register	*/
+#define MC_ME_PCTL49	(MC_ME_BASE_ADDR + 0x000000F2)
+/* CSI0 Peripheral Control Register			*/
+#define MC_ME_PCTL48	(MC_ME_BASE_ADDR + 0x000000F3)
+/* MMDC0 Peripheral Control Register		*/
+#define MC_ME_PCTL54	(MC_ME_BASE_ADDR + 0x000000F5)
+/* FRAY Peripheral Control Register			*/
+#define MC_ME_PCTL52	(MC_ME_BASE_ADDR + 0x000000F7)
+/* PIT0 Peripheral Control Register			*/
+#define MC_ME_PCTL58	(MC_ME_BASE_ADDR + 0x000000F9)
+/* FlexTIMER0 Peripheral Control Register	*/
+#define MC_ME_PCTL79	(MC_ME_BASE_ADDR + 0x0000010C)
+/* SARADC0 Peripheral Control Register		*/
+#define MC_ME_PCTL77	(MC_ME_BASE_ADDR + 0x0000010E)
+/* LINFLEX0 Peripheral Control Register		*/
+#define MC_ME_PCTL83	(MC_ME_BASE_ADDR + 0x00000110)
+/* IIC0 Peripheral Control Register			*/
+#define MC_ME_PCTL81	(MC_ME_BASE_ADDR + 0x00000112)
+/* DSPI0 Peripheral Control Register		*/
+#define MC_ME_PCTL87	(MC_ME_BASE_ADDR + 0x00000114)
+/* CANFD0 Peripheral Control Register		*/
+#define MC_ME_PCTL85	(MC_ME_BASE_ADDR + 0x00000116)
+/* CRC0 Peripheral Control Register			*/
+#define MC_ME_PCTL91	(MC_ME_BASE_ADDR + 0x00000118)
+/* DSPI2 Peripheral Control Register		*/
+#define MC_ME_PCTL89	(MC_ME_BASE_ADDR + 0x0000011A)
+/* SDHC Peripheral Control Register			*/
+#define MC_ME_PCTL93	(MC_ME_BASE_ADDR + 0x0000011E)
+/* VIU0 Peripheral Control Register			*/
+#define MC_ME_PCTL100	(MC_ME_BASE_ADDR + 0x00000127)
+/* HPSMI Peripheral Control Register		*/
+#define MC_ME_PCTL104	(MC_ME_BASE_ADDR + 0x0000012B)
+/* SIPI Peripheral Control Register			*/
+#define MC_ME_PCTL116	(MC_ME_BASE_ADDR + 0x00000137)
+/* LFAST Peripheral Control Register		*/
+#define MC_ME_PCTL120	(MC_ME_BASE_ADDR + 0x0000013B)
+/* MMDC1 Peripheral Control Register		*/
+#define MC_ME_PCTL162	(MC_ME_BASE_ADDR + 0x00000161)
+/* DMACHMUX1 Peripheral Control Register	*/
+#define MC_ME_PCTL161	(MC_ME_BASE_ADDR + 0x00000162)
+/* CSI1 Peripheral Control Register			*/
+#define MC_ME_PCTL160	(MC_ME_BASE_ADDR + 0x00000163)
+/* QUADSPI0 Peripheral Control Register		*/
+#define MC_ME_PCTL166	(MC_ME_BASE_ADDR + 0x00000165)
+/* PIT1 Peripheral Control Register			*/
+#define MC_ME_PCTL170	(MC_ME_BASE_ADDR + 0x00000169)
+/* FlexTIMER1 Peripheral Control Register	*/
+#define MC_ME_PCTL182	(MC_ME_BASE_ADDR + 0x00000175)
+/* IIC2 Peripheral Control Register			*/
+#define MC_ME_PCTL186	(MC_ME_BASE_ADDR + 0x00000179)
+/* IIC1 Peripheral Control Register			*/
+#define MC_ME_PCTL184	(MC_ME_BASE_ADDR + 0x0000017B)
+/* CANFD1 Peripheral Control Register		*/
+#define MC_ME_PCTL190	(MC_ME_BASE_ADDR + 0x0000017D)
+/* LINFLEX1 Peripheral Control Register		*/
+#define MC_ME_PCTL188	(MC_ME_BASE_ADDR + 0x0000017F)
+/* DSPI3 Peripheral Control Register		*/
+#define MC_ME_PCTL194	(MC_ME_BASE_ADDR + 0x00000181)
+/* DSPI1 Peripheral Control Register		*/
+#define MC_ME_PCTL192	(MC_ME_BASE_ADDR + 0x00000183)
+/* TSENS Peripheral Control Register		*/
+#define MC_ME_PCTL206	(MC_ME_BASE_ADDR + 0x0000018D)
+/* CRC1 Peripheral Control Register			*/
+#define MC_ME_PCTL204	(MC_ME_BASE_ADDR + 0x0000018F)
+/* VIU1 Peripheral Control Register		*/
+#define MC_ME_PCTL208	(MC_ME_BASE_ADDR + 0x00000193)
+/* JPEG Peripheral Control Register		*/
+#define MC_ME_PCTL212	(MC_ME_BASE_ADDR + 0x00000197)
+/* H264_DEC Peripheral Control Register	*/
+#define MC_ME_PCTL216	(MC_ME_BASE_ADDR + 0x0000019B)
+/* H264_ENC Peripheral Control Register	*/
+#define MC_ME_PCTL220	(MC_ME_BASE_ADDR + 0x0000019F)
+/* MBIST Peripheral Control Register	*/
+#define MC_ME_PCTL236	(MC_ME_BASE_ADDR + 0x000001A9)
+
+/* Core status register */
+#define MC_ME_CS               (MC_ME_BASE_ADDR + 0x000001C0)
+
+#endif
+
+#endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
new file mode 100644
index 0000000..34501b2
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mc_rgm_regs.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
+#define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
+
+#define MC_RGM_DES			(MC_RGM_BASE_ADDR)
+#define MC_RGM_FES			(MC_RGM_BASE_ADDR + 0x300)
+#define MC_RGM_FERD			(MC_RGM_BASE_ADDR + 0x310)
+#define MC_RGM_FBRE			(MC_RGM_BASE_ADDR + 0x330)
+#define MC_RGM_FESS			(MC_RGM_BASE_ADDR + 0x340)
+#define MC_RGM_DDR_HE			(MC_RGM_BASE_ADDR + 0x350)
+#define MC_RGM_DDR_HS			(MC_RGM_BASE_ADDR + 0x354)
+#define MC_RGM_FRHE			(MC_RGM_BASE_ADDR + 0x358)
+#define MC_RGM_FREC			(MC_RGM_BASE_ADDR + 0x600)
+#define MC_RGM_FRET			(MC_RGM_BASE_ADDR + 0x607)
+#define MC_RGM_DRET			(MC_RGM_BASE_ADDR + 0x60B)
+
+/* function reset sources mask */
+#define F_SWT4				0x8000
+#define F_JTAG				0x400
+#define F_FCCU_SOFT			0x40
+#define F_FCCU_HARD			0x20
+#define F_SOFT_FUNC			0x8
+#define F_ST_DONE			0x4
+#define F_EXT_RST			0x1
+
+#endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-s32v234/mmdc.h b/arch/arm/include/asm/arch-s32v234/mmdc.h
new file mode 100644
index 0000000..8d74ae0
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/mmdc.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
+#define __ARCH_ARM_MACH_S32V234_MMDC_H__
+
+#define MMDC0				0
+#define MMDC1				1
+
+#define MMDC_MDCTL			0x0
+#define MMDC_MDPDC			0x4
+#define MMDC_MDOTC			0x8
+#define MMDC_MDCFG0			0xC
+#define MMDC_MDCFG1			0x10
+#define MMDC_MDCFG2			0x14
+#define MMDC_MDMISC			0x18
+#define MMDC_MDSCR			0x1C
+#define MMDC_MDREF			0x20
+#define MMDC_MDRWD			0x2C
+#define MMDC_MDOR			0x30
+#define MMDC_MDMRR			0x34
+#define MMDC_MDCFG3LP		0x38
+#define MMDC_MDMR4			0x3C
+#define MMDC_MDASP			0x40
+#define MMDC_MAARCR			0x400
+#define MMDC_MAPSR			0x404
+#define MMDC_MAEXIDR0		0x408
+#define MMDC_MAEXIDR1		0x40C
+#define MMDC_MADPCR0		0x410
+#define MMDC_MADPCR1		0x414
+#define MMDC_MADPSR0		0x418
+#define MMDC_MADPSR1		0x41C
+#define MMDC_MADPSR2		0x420
+#define MMDC_MADPSR3		0x424
+#define MMDC_MADPSR4		0x428
+#define MMDC_MADPSR5		0x42C
+#define MMDC_MASBS0			0x430
+#define MMDC_MASBS1			0x434
+#define MMDC_MAGENP			0x440
+#define MMDC_MPZQHWCTRL		0x800
+#define MMDC_MPWLGCR		0x808
+#define MMDC_MPWLDECTRL0	0x80C
+#define MMDC_MPWLDECTRL1	0x810
+#define MMDC_MPWLDLST		0x814
+#define MMDC_MPODTCTRL		0x818
+#define MMDC_MPRDDQBY0DL	0x81C
+#define MMDC_MPRDDQBY1DL	0x820
+#define MMDC_MPRDDQBY2DL	0x824
+#define MMDC_MPRDDQBY3DL	0x828
+#define MMDC_MPDGCTRL0		0x83C
+#define MMDC_MPDGCTRL1		0x840
+#define MMDC_MPDGDLST0		0x844
+#define MMDC_MPRDDLCTL		0x848
+#define MMDC_MPRDDLST		0x84C
+#define MMDC_MPWRDLCTL		0x850
+#define MMDC_MPWRDLST		0x854
+#define MMDC_MPZQLP2CTL		0x85C
+#define MMDC_MPRDDLHWCTL	0x860
+#define MMDC_MPWRDLHWCTL	0x864
+#define MMDC_MPRDDLHWST0	0x868
+#define MMDC_MPRDDLHWST1	0x86C
+#define MMDC_MPWRDLHWST1	0x870
+#define MMDC_MPWRDLHWST2	0x874
+#define MMDC_MPWLHWERR		0x878
+#define MMDC_MPDGHWST0		0x87C
+#define MMDC_MPDGHWST1		0x880
+#define MMDC_MPDGHWST2		0x884
+#define MMDC_MPDGHWST3		0x888
+#define MMDC_MPPDCMPR1		0x88C
+#define MMDC_MPPDCMPR2		0x890
+#define MMDC_MPSWDAR0		0x894
+#define MMDC_MPSWDRDR0		0x898
+#define MMDC_MPSWDRDR1		0x89C
+#define MMDC_MPSWDRDR2		0x8A0
+#define MMDC_MPSWDRDR3		0x8A4
+#define MMDC_MPSWDRDR4		0x8A8
+#define MMDC_MPSWDRDR5		0x8AC
+#define MMDC_MPSWDRDR6		0x8B0
+#define MMDC_MPSWDRDR7		0x8B4
+#define MMDC_MPMUR0			0x8B8
+#define MMDC_MPDCCR			0x8C0
+
+#define MMDC_MPMUR0_FRC_MSR			(1 << 11)
+#define MMDC_MPZQHWCTRL_ZQ_HW_FOR	(1 << 16)
+
+#endif
diff --git a/arch/arm/include/asm/arch-s32v234/siul.h b/arch/arm/include/asm/arch-s32v234/siul.h
new file mode 100644
index 0000000..7572581
--- /dev/null
+++ b/arch/arm/include/asm/arch-s32v234/siul.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015, Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_S32V234_SIUL_H__
+#define __ARCH_ARM_MACH_S32V234_SIUL_H__
+
+#include "ddr.h"
+
+#define SIUL2_MIDR1				(SIUL2_BASE_ADDR + 0x00000004)
+#define SIUL2_MIDR2				(SIUL2_BASE_ADDR + 0x00000008)
+#define SIUL2_DISR0				(SIUL2_BASE_ADDR + 0x00000010)
+#define SIUL2_DIRER0				(SIUL2_BASE_ADDR + 0x00000018)
+#define SIUL2_DIRSR0				(SIUL2_BASE_ADDR + 0x00000020)
+#define SIUL2_IREER0				(SIUL2_BASE_ADDR + 0x00000028)
+#define SIUL2_IFEER0				(SIUL2_BASE_ADDR + 0x00000030)
+#define SIUL2_IFER0				(SIUL2_BASE_ADDR + 0x00000038)
+
+#define SIUL2_IFMCR_BASE			(SIUL2_BASE_ADDR + 0x00000040)
+#define SIUL2_IFMCRn(i)				(SIUL2_IFMCR_BASE + 4 * (i))
+
+#define SIUL2_IFCPR				(SIUL2_BASE_ADDR + 0x000000C0)
+
+/* SIUL2_MSCR specifications as stated in Reference Manual:
+ * 0 - 359 Output Multiplexed Signal Configuration Registers
+ * 512- 1023 Input Multiplexed Signal Configuration Registers */
+#define SIUL2_MSCR_BASE				(SIUL2_BASE_ADDR + 0x00000240)
+#define SIUL2_MSCRn(i)				(SIUL2_MSCR_BASE + 4 * (i))
+
+#define SIUL2_IMCR_BASE				(SIUL2_BASE_ADDR + 0x00000A40)
+#define SIUL2_IMCRn(i)				(SIUL2_IMCR_BASE +  4 * (i))
+
+#define SIUL2_GPDO_BASE				(SIUL2_BASE_ADDR + 0x00001300)
+#define SIUL2_GPDOn(i)				(SIUL2_GPDO_BASE + 4 * (i))
+
+#define SIUL2_GPDI_BASE				(SIUL2_BASE_ADDR + 0x00001500)
+#define SIUL2_GPDIn(i)				(SIUL2_GPDI_BASE + 4 * (i))
+
+#define SIUL2_PGPDO_BASE			(SIUL2_BASE_ADDR + 0x00001700)
+#define SIUL2_PGPDOn(i)				(SIUL2_PGPDO_BASE +  2 * (i))
+
+#define SIUL2_PGPDI_BASE			(SIUL2_BASE_ADDR + 0x00001740)
+#define SIUL2_PGPDIn(i)				(SIUL2_PGPDI_BASE + 2 * (i))
+
+#define SIUL2_MPGPDO_BASE			(SIUL2_BASE_ADDR + 0x00001780)
+#define SIUL2_MPGPDOn(i)			(SIUL2_MPGPDO_BASE + 4 * (i))
+
+/* SIUL2_MSCR masks */
+#define SIUL2_MSCR_DDR_DO_TRIM(v)	((v) & 0xC0000000)
+#define SIUL2_MSCR_DDR_DO_TRIM_MIN	(0 << 30)
+#define SIUL2_MSCR_DDR_DO_TRIM_50PS	(1 << 30)
+#define SIUL2_MSCR_DDR_DO_TRIM_100PS	(2 << 30)
+#define SIUL2_MSCR_DDR_DO_TRIM_150PS	(3 << 30)
+
+#define SIUL2_MSCR_DDR_INPUT(v)		((v) & 0x20000000)
+#define SIUL2_MSCR_DDR_INPUT_CMOS	(0 << 29)
+#define SIUL2_MSCR_DDR_INPUT_DIFF_DDR	(1 << 29)
+
+#define SIUL2_MSCR_DDR_SEL(v)		((v) & 0x18000000)
+#define SIUL2_MSCR_DDR_SEL_DDR3		(0 << 27)
+#define SIUL2_MSCR_DDR_SEL_LPDDR2	(2 << 27)
+
+#define SIUL2_MSCR_DDR_ODT(v)		((v) & 0x07000000)
+#define SIUL2_MSCR_DDR_ODT_120ohm	(1 << 24)
+#define SIUL2_MSCR_DDR_ODT_60ohm	(2 << 24)
+#define SIUL2_MSCR_DDR_ODT_40ohm	(3 << 24)
+#define SIUL2_MSCR_DDR_ODT_30ohm	(4 << 24)
+#define SIUL2_MSCR_DDR_ODT_24ohm	(5 << 24)
+#define SIUL2_MSCR_DDR_ODT_20ohm	(6 << 24)
+#define SIUL2_MSCR_DDR_ODT_17ohm	(7 << 24)
+
+#define SIUL2_MSCR_DCYCLE_TRIM(v)	((v) & 0x00C00000)
+#define SIUL2_MSCR_DCYCLE_TRIM_NONE	(0 << 22)
+#define SIUL2_MSCR_DCYCLE_TRIM_LEFT	(1 << 22)
+#define SIUL2_MSCR_DCYCLE_TRIM_RIGHT	(2 << 22)
+
+#define SIUL2_MSCR_OBE(v)		((v) & 0x00200000)
+#define SIUL2_MSCR_OBE_EN		(1 << 21)
+
+#define SIUL2_MSCR_ODE(v)		((v) & 0x00100000)
+#define SIUL2_MSCR_ODE_EN		(1 << 20)
+
+#define SIUL2_MSCR_IBE(v)		((v) & 0x00010000)
+#define SIUL2_MSCR_IBE_EN		(1 << 19)
+
+#define SIUL2_MSCR_HYS(v)		((v) & 0x00400000)
+#define SIUL2_MSCR_HYS_EN		(1 << 18)
+
+#define SIUL2_MSCR_INV(v)		((v) & 0x00020000)
+#define SIUL2_MSCR_INV_EN		(1 << 17)
+
+#define SIUL2_MSCR_PKE(v)		((v) & 0x00010000)
+#define SIUL2_MSCR_PKE_EN		(1 << 16)
+
+#define SIUL2_MSCR_SRE(v)		((v) & 0x0000C000)
+#define SIUL2_MSCR_SRE_SPEED_LOW_50	(0 << 14)
+#define SIUL2_MSCR_SRE_SPEED_LOW_100	(1 << 14)
+#define SIUL2_MSCR_SRE_SPEED_HIGH_100	(2 << 14)
+#define SIUL2_MSCR_SRE_SPEED_HIGH_200	(3 << 14)
+
+#define SIUL2_MSCR_PUE(v)		((v) & 0x00002000)
+#define SIUL2_MSCR_PUE_EN		(1 << 13)
+
+#define SIUL2_MSCR_PUS(v)		((v) & 0x00001800)
+#define SIUL2_MSCR_PUS_100K_DOWN	(0 << 11)
+#define SIUL2_MSCR_PUS_50K_DOWN		(1 << 11)
+#define SIUL2_MSCR_PUS_100K_UP		(2 << 11)
+#define SIUL2_MSCR_PUS_33K_UP		(3 << 11)
+
+#define SIUL2_MSCR_DSE(v)		((v) & 0x00000700)
+#define SIUL2_MSCR_DSE_240ohm		(1 << 8)
+#define SIUL2_MSCR_DSE_120ohm		(2 << 8)
+#define SIUL2_MSCR_DSE_80ohm		(3 << 8)
+#define SIUL2_MSCR_DSE_60ohm		(4 << 8)
+#define SIUL2_MSCR_DSE_48ohm		(5 << 8)
+#define SIUL2_MSCR_DSE_40ohm		(6 << 8)
+#define SIUL2_MSCR_DSE_34ohm		(7 << 8)
+
+#define SIUL2_MSCR_CRPOINT_TRIM(v)	((v) & 0x000000C0)
+#define SIUL2_MSCR_CRPOINT_TRIM_1	(1 << 6)
+
+#define SIUL2_MSCR_SMC(v)		((v) & 0x00000020)
+#define SIUL2_MSCR_MUX_MODE(v)		((v) & 0x0000000f)
+#define SIUL2_MSCR_MUX_MODE_ALT1	(0x1)
+#define SIUL2_MSCR_MUX_MODE_ALT2	(0x2)
+#define SIUL2_MSCR_MUX_MODE_ALT3	(0x3)
+
+/* UART settings */
+#define SIUL2_UART0_TXD_PAD	12
+#define SIUL2_UART_TXD		(SIUL2_MSCR_OBE_EN | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_60ohm |	\
+				SIUL2_MSCR_SRE_SPEED_LOW_100 | SIUL2_MSCR_MUX_MODE_ALT1)
+
+#define SIUL2_UART0_MSCR_RXD_PAD	11
+#define SIUL2_UART0_IMCR_RXD_PAD	200
+
+#define SIUL2_UART_MSCR_RXD	(SIUL2_MSCR_PUE_EN | SIUL2_MSCR_IBE_EN | SIUL2_MSCR_DCYCLE_TRIM_RIGHT)
+#define SIUL2_UART_IMCR_RXD	(SIUL2_MSCR_MUX_MODE_ALT2)
+
+/* uSDHC settings */
+#define SIUL2_USDHC_PAD_CTRL_BASE	(SIUL2_MSCR_SRE_SPEED_HIGH_200 | SIUL2_MSCR_OBE_EN |	\
+						SIUL2_MSCR_DSE_34ohm | SIUL2_MSCR_PKE_EN | SIUL2_MSCR_IBE_EN |		\
+						SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_PUE_EN )
+#define SIUL2_USDHC_PAD_CTRL_CMD	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT1)
+#define SIUL2_USDHC_PAD_CTRL_CLK	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
+#define SIUL2_USDHC_PAD_CTRL_DAT0_3	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT2)
+#define SIUL2_USDHC_PAD_CTRL_DAT4_7	(SIUL2_USDHC_PAD_CTRL_BASE | SIUL2_MSCR_MUX_MODE_ALT3)
+
+#endif /*__ARCH_ARM_MACH_S32V234_SIUL_H__ */
diff --git a/arch/arm/include/asm/arch-sa1100/bitfield.h b/arch/arm/include/asm/arch-sa1100/bitfield.h
new file mode 100644
index 0000000..104a21c
--- /dev/null
+++ b/arch/arm/include/asm/arch-sa1100/bitfield.h
@@ -0,0 +1,112 @@
+/*
+ *	FILE		bitfield.h
+ *
+ *	Version		1.1
+ *	Author		Copyright (c) Marc A. Viredaz, 1998
+ *			DEC Western Research Laboratory, Palo Alto, CA
+ *	Date		April 1998 (April 1997)
+ *	System		Advanced RISC Machine (ARM)
+ *	Language	C or ARM Assembly
+ *	Purpose		Definition of macros to operate on bit fields.
+ */
+
+
+#ifndef __BITFIELD_H
+#define __BITFIELD_H
+
+#ifndef __ASSEMBLY__
+#define UData(Data)	((unsigned long) (Data))
+#else
+#define UData(Data)	(Data)
+#endif
+
+
+/*
+ * MACRO: Fld
+ *
+ * Purpose
+ *    The macro "Fld" encodes a bit field, given its size and its shift value
+ *    with respect to bit 0.
+ *
+ * Note
+ *    A more intuitive way to encode bit fields would have been to use their
+ *    mask. However, extracting size and shift value information from a bit
+ *    field's mask is cumbersome and might break the assembler (255-character
+ *    line-size limit).
+ *
+ * Input
+ *    Size		Size of the bit field, in number of bits.
+ *    Shft		Shift value of the bit field with respect to bit 0.
+ *
+ * Output
+ *    Fld		Encoded bit field.
+ */
+
+#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
+
+
+/*
+ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
+ *
+ * Purpose
+ *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
+ *    the size, shift value, mask, aligned mask, and first bit of a
+ *    bit field.
+ *
+ * Input
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FSize		Size of the bit field, in number of bits.
+ *    FShft		Shift value of the bit field with respect to bit 0.
+ *    FMsk		Mask for the bit field.
+ *    FAlnMsk		Mask for the bit field, aligned on bit 0.
+ *    F1stBit		First bit of the bit field.
+ */
+
+#define FSize(Field)	((Field) >> 16)
+#define FShft(Field)	((Field) & 0x0000FFFF)
+#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field)	(UData (1) << FShft (Field))
+
+
+/*
+ * MACRO: FInsrt
+ *
+ * Purpose
+ *    The macro "FInsrt" inserts a value into a bit field by shifting the
+ *    former appropriately.
+ *
+ * Input
+ *    Value		Bit-field value.
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FInsrt		Bit-field value positioned appropriately.
+ */
+
+#define FInsrt(Value, Field) \
+			(UData (Value) << FShft (Field))
+
+
+/*
+ * MACRO: FExtr
+ *
+ * Purpose
+ *    The macro "FExtr" extracts the value of a bit field by masking and
+ *    shifting it appropriately.
+ *
+ * Input
+ *    Data		Data containing the bit-field to be extracted.
+ *    Field		Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FExtr		Bit-field value.
+ */
+
+#define FExtr(Data, Field) \
+			((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+
+#endif /* __BITFIELD_H */
diff --git a/arch/arm/include/asm/arch-spear/clk.h b/arch/arm/include/asm/arch-spear/clk.h
new file mode 100644
index 0000000..b193f76
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/clk.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010, STMicroelectronics - All Rights Reserved
+ * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
+ */
+
+static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
+{
+	return 83000000;
+}
diff --git a/arch/arm/include/asm/arch-spear/gpio.h b/arch/arm/include/asm/arch-spear/gpio.h
new file mode 100644
index 0000000..4c8c40b
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/gpio.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ */
+
+
+#ifndef __ASM_ARCH_SPEAR_GPIO_H
+#define __ASM_ARCH_SPEAR_GPIO_H
+
+enum gpio_direction {
+	GPIO_DIRECTION_IN,
+	GPIO_DIRECTION_OUT,
+};
+
+struct gpio_regs {
+	u32 gpiodata[0x100];	/* 0x000 ... 0x3fc */
+	u32 gpiodir;		/* 0x400 */
+};
+
+#define SPEAR_GPIO_COUNT		8
+#define DATA_REG_ADDR(gpio)		(1 << (gpio + 2))
+
+#endif	/* __ASM_ARCH_SPEAR_GPIO_H */
diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h
new file mode 100644
index 0000000..c05bd44
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/hardware.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
+ * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define CONFIG_SYS_USBD_BASE			0xE1100000
+#define CONFIG_SYS_PLUG_BASE			0xE1200000
+#define CONFIG_SYS_FIFO_BASE			0xE1000800
+#define CONFIG_SYS_UHC0_EHCI_BASE		0xE1800000
+#define CONFIG_SYS_UHC1_EHCI_BASE		0xE2000000
+#define CONFIG_SYS_SMI_BASE			0xFC000000
+#define CONFIG_SPEAR_SYSCNTLBASE		0xFCA00000
+#define CONFIG_SPEAR_TIMERBASE			0xFC800000
+#define CONFIG_SPEAR_MISCBASE			0xFCA80000
+#define CONFIG_SPEAR_ETHBASE			0xE0800000
+#define CONFIG_SPEAR_MPMCBASE			0xFC600000
+#define CONFIG_SSP1_BASE			0xD0100000
+#define CONFIG_SSP2_BASE			0xD0180000
+#define CONFIG_SSP3_BASE			0xD8180000
+#define CONFIG_GPIO_BASE			0xD8100000
+
+#define CONFIG_SYS_NAND_CLE			(1 << 16)
+#define CONFIG_SYS_NAND_ALE			(1 << 17)
+
+#if defined(CONFIG_SPEAR600)
+#define CONFIG_SYS_FSMC_BASE			0xD1800000
+#define CONFIG_FSMC_NAND_BASE			0xD2000000
+
+#define CONFIG_SPEAR_BOOTSTRAPCFG		0xFCA80000
+#define CONFIG_SPEAR_BOOTSTRAPSHFT		16
+#define CONFIG_SPEAR_BOOTSTRAPMASK		0xB
+#define CONFIG_SPEAR_ONLYSNORBOOT		0xA
+#define CONFIG_SPEAR_NORNANDBOOT		0xB
+#define CONFIG_SPEAR_NORNAND8BOOT		0x8
+#define CONFIG_SPEAR_NORNAND16BOOT		0x9
+#define CONFIG_SPEAR_USBBOOT			0x8
+
+#define CONFIG_SPEAR_MPMCREGS			100
+
+#elif defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_FSMC_BASE			0x94000000
+
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_FSMC_BASE			0x44000000
+
+#undef CONFIG_SYS_NAND_CLE
+#undef CONFIG_SYS_NAND_ALE
+#define CONFIG_SYS_NAND_CLE			(1 << 17)
+#define CONFIG_SYS_NAND_ALE			(1 << 16)
+
+#define CONFIG_SPEAR_EMIBASE			0x4F000000
+#define CONFIG_SPEAR_RASBASE			0xB4000000
+
+#define CONFIG_SYS_MACB0_BASE			0xB0000000
+#define CONFIG_SYS_MACB1_BASE			0xB0800000
+#define CONFIG_SYS_MACB2_BASE			0xB1000000
+#define CONFIG_SYS_MACB3_BASE			0xB1800000
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_FSMC_BASE			0x4C000000
+
+#define CONFIG_SPEAR_EMIBASE			0x40000000
+#define CONFIG_SPEAR_RASBASE			0xB3000000
+
+#define CONFIG_SYS_MACB0_BASE			0xAA000000
+
+#endif
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h
new file mode 100644
index 0000000..d09e7eb
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spr_defs.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#ifndef __SPR_DEFS_H__
+#define __SPR_DEFS_H__
+
+extern int spear_board_init(ulong);
+extern void setfreq(unsigned int, unsigned int);
+extern unsigned int setfreq_sz;
+
+void plat_ddr_init(void);
+void spear_late_init(void);
+
+int snor_boot_selected(void);
+int nand_boot_selected(void);
+int pnor_boot_selected(void);
+int usb_boot_selected(void);
+int uart_boot_selected(void);
+int tftp_boot_selected(void);
+int i2c_boot_selected(void);
+int spi_boot_selected(void);
+int mmc_boot_selected(void);
+
+extern u32 mpmc_conf_vals[];
+
+struct chip_data {
+	int cpufreq;
+	int dramfreq;
+	int dramtype;
+	uchar version[32];
+};
+
+/* HW mac id in i2c memory definitions */
+#define MAGIC_OFF	0x0
+#define MAGIC_LEN	0x2
+#define MAGIC_BYTE0	0x55
+#define MAGIC_BYTE1	0xAA
+#define MAC_OFF		0x2
+#define MAC_LEN		0x6
+
+#define PNOR_WIDTH_8			0
+#define	PNOR_WIDTH_16			1
+#define	PNOR_WIDTH_32			2
+#define PNOR_WIDTH_NUM			3
+#define PNOR_WIDTH_SEARCH		0xff
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_emi.h b/arch/arm/include/asm/arch-spear/spr_emi.h
new file mode 100644
index 0000000..7b1cf35
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spr_emi.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
+ */
+
+#ifndef __SPEAR_EMI_H__
+#define __SPEAR_EMI_H__
+
+#ifdef CONFIG_SPEAR_EMI
+
+struct emi_bank_regs {
+	u32 tap;
+	u32 tsdp;
+	u32 tdpw;
+	u32 tdpr;
+	u32 tdcs;
+	u32 control;
+};
+
+struct emi_regs {
+	struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS];
+	u32 tout;
+	u32 ack;
+	u32 irq;
+};
+
+#define EMI_ACKMSK		0x40
+
+/* control register definitions */
+#define EMI_CNTL_ENBBYTEW	(1 << 2)
+#define EMI_CNTL_ENBBYTER	(1 << 3)
+#define EMI_CNTL_ENBBYTERW	(EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_gpt.h b/arch/arm/include/asm/arch-spear/spr_gpt.h
new file mode 100644
index 0000000..dced0a1
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spr_gpt.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#ifndef _SPR_GPT_H
+#define _SPR_GPT_H
+
+struct gpt_regs {
+	u8 reserved[0x80];
+	u32 control;
+	u32 status;
+	u32 compare;
+	u32 count;
+	u32 capture_re;
+	u32 capture_fe;
+};
+
+/*
+ * TIMER_CONTROL register settings
+ */
+
+#define GPT_PRESCALER_MASK		0x000F
+#define GPT_PRESCALER_1			0x0000
+#define GPT_PRESCALER_2 		0x0001
+#define GPT_PRESCALER_4 		0x0002
+#define GPT_PRESCALER_8 		0x0003
+#define GPT_PRESCALER_16		0x0004
+#define GPT_PRESCALER_32		0x0005
+#define GPT_PRESCALER_64		0x0006
+#define GPT_PRESCALER_128		0x0007
+#define GPT_PRESCALER_256		0x0008
+
+#define GPT_MODE_SINGLE_SHOT		0x0010
+#define GPT_MODE_AUTO_RELOAD		0x0000
+
+#define GPT_ENABLE			0x0020
+
+#define GPT_CAPT_MODE_MASK		0x00C0
+#define GPT_CAPT_MODE_NONE		0x0000
+#define GPT_CAPT_MODE_RE		0x0040
+#define GPT_CAPT_MODE_FE		0x0080
+#define GPT_CAPT_MODE_BOTH		0x00C0
+
+#define GPT_INT_MATCH			0x0100
+#define GPT_INT_FE			0x0200
+#define GPT_INT_RE			0x0400
+
+/*
+ * TIMER_STATUS register settings
+ */
+
+#define GPT_STS_MATCH			0x0001
+#define GPT_STS_FE			0x0002
+#define GPT_STS_RE			0x0004
+
+/*
+ * TIMER_COMPARE register settings
+ */
+
+#define GPT_FREE_RUNNING		0xFFFF
+
+/* Timer, HZ specific defines */
+#define CONFIG_SPEAR_HZ			1000
+#define CONFIG_SPEAR_HZ_CLOCK		8300000
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
new file mode 100644
index 0000000..0171119
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -0,0 +1,260 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#ifndef _SPR_MISC_H
+#define _SPR_MISC_H
+
+struct misc_regs {
+	u32 auto_cfg_reg;	/* 0x0 */
+	u32 armdbg_ctr_reg;	/* 0x4 */
+	u32 pll1_cntl;		/* 0x8 */
+	u32 pll1_frq;		/* 0xc */
+	u32 pll1_mod;		/* 0x10 */
+	u32 pll2_cntl;		/* 0x14 */
+	u32 pll2_frq;		/* 0x18 */
+	u32 pll2_mod;		/* 0x1C */
+	u32 pll_ctr_reg;	/* 0x20 */
+	u32 amba_clk_cfg;	/* 0x24 */
+	u32 periph_clk_cfg;	/* 0x28 */
+	u32 periph1_clken;	/* 0x2C */
+	u32 soc_core_id;	/* 0x30 */
+	u32 ras_clken;		/* 0x34 */
+	u32 periph1_rst;	/* 0x38 */
+	u32 periph2_rst;	/* 0x3C */
+	u32 ras_rst;		/* 0x40 */
+	u32 prsc1_clk_cfg;	/* 0x44 */
+	u32 prsc2_clk_cfg;	/* 0x48 */
+	u32 prsc3_clk_cfg;	/* 0x4C */
+	u32 amem_cfg_ctrl;	/* 0x50 */
+	u32 expi_clk_cfg;	/* 0x54 */
+	u32 reserved_1;		/* 0x58 */
+	u32 clcd_synth_clk;	/* 0x5C */
+	u32 irda_synth_clk;	/* 0x60 */
+	u32 uart_synth_clk;	/* 0x64 */
+	u32 gmac_synth_clk;	/* 0x68 */
+	u32 ras_synth1_clk;	/* 0x6C */
+	u32 ras_synth2_clk;	/* 0x70 */
+	u32 ras_synth3_clk;	/* 0x74 */
+	u32 ras_synth4_clk;	/* 0x78 */
+	u32 arb_icm_ml1;	/* 0x7C */
+	u32 arb_icm_ml2;	/* 0x80 */
+	u32 arb_icm_ml3;	/* 0x84 */
+	u32 arb_icm_ml4;	/* 0x88 */
+	u32 arb_icm_ml5;	/* 0x8C */
+	u32 arb_icm_ml6;	/* 0x90 */
+	u32 arb_icm_ml7;	/* 0x94 */
+	u32 arb_icm_ml8;	/* 0x98 */
+	u32 arb_icm_ml9;	/* 0x9C */
+	u32 dma_src_sel;	/* 0xA0 */
+	u32 uphy_ctr_reg;	/* 0xA4 */
+	u32 gmac_ctr_reg;	/* 0xA8 */
+	u32 port_bridge_ctrl;	/* 0xAC */
+	u32 reserved_2[4];	/* 0xB0--0xBC */
+	u32 prc1_ilck_ctrl_reg;	/* 0xC0 */
+	u32 prc2_ilck_ctrl_reg;	/* 0xC4 */
+	u32 prc3_ilck_ctrl_reg;	/* 0xC8 */
+	u32 prc4_ilck_ctrl_reg;	/* 0xCC */
+	u32 prc1_intr_ctrl_reg;	/* 0xD0 */
+	u32 prc2_intr_ctrl_reg;	/* 0xD4 */
+	u32 prc3_intr_ctrl_reg;	/* 0xD8 */
+	u32 prc4_intr_ctrl_reg;	/* 0xDC */
+	u32 powerdown_cfg_reg;	/* 0xE0 */
+	u32 ddr_1v8_compensation;	/* 0xE4  */
+	u32 ddr_2v5_compensation;	/* 0xE8 */
+	u32 core_3v3_compensation;	/* 0xEC */
+	u32 ddr_pad;		/* 0xF0 */
+	u32 bist1_ctr_reg;	/* 0xF4 */
+	u32 bist2_ctr_reg;	/* 0xF8 */
+	u32 bist3_ctr_reg;	/* 0xFC */
+	u32 bist4_ctr_reg;	/* 0x100 */
+	u32 bist5_ctr_reg;	/* 0x104 */
+	u32 bist1_rslt_reg;	/* 0x108 */
+	u32 bist2_rslt_reg;	/* 0x10C */
+	u32 bist3_rslt_reg;	/* 0x110 */
+	u32 bist4_rslt_reg;	/* 0x114 */
+	u32 bist5_rslt_reg;	/* 0x118 */
+	u32 syst_error_reg;	/* 0x11C */
+	u32 reserved_3[0x1FB8];	/* 0x120--0x7FFC */
+	u32 ras_gpp1_in;	/* 0x8000 */
+	u32 ras_gpp2_in;	/* 0x8004 */
+	u32 ras_gpp1_out;	/* 0x8008 */
+	u32 ras_gpp2_out;	/* 0x800C */
+};
+
+/* SYNTH_CLK value*/
+#define SYNTH23			0x00020003
+
+/* PLLx_FRQ value */
+#if defined(CONFIG_SPEAR3XX)
+#define FREQ_332		0xA600010C
+#define FREQ_266		0x8500010C
+#elif defined(CONFIG_SPEAR600)
+#define FREQ_332		0xA600010F
+#define FREQ_266		0x8500010F
+#endif
+
+/* PLL_CTR_REG   */
+#define MEM_CLK_SEL_MSK		0x70000000
+#define MEM_CLK_HCLK		0x00000000
+#define MEM_CLK_2HCLK		0x10000000
+#define MEM_CLK_PLL2		0x30000000
+
+#define EXPI_CLK_CFG_LOW_COMPR	0x2000
+#define EXPI_CLK_CFG_CLK_EN	0x0400
+#define EXPI_CLK_CFG_RST	0x0200
+#define EXPI_CLK_SYNT_EN	0x0010
+#define EXPI_CLK_CFG_SEL_PLL2	0x0004
+#define EXPI_CLK_CFG_INT_CLK_EN	0x0001
+
+#define PLL2_CNTL_6UA		0x1c00
+#define PLL2_CNTL_SAMPLE	0x0008
+#define PLL2_CNTL_ENABLE	0x0004
+#define PLL2_CNTL_RESETN	0x0002
+#define PLL2_CNTL_LOCK		0x0001
+
+/* AUTO_CFG_REG value */
+#define MISC_SOCCFGMSK                  0x0000003F
+#define MISC_SOCCFG30                   0x0000000C
+#define MISC_SOCCFG31                   0x0000000D
+#define MISC_NANDDIS			0x00020000
+
+/* PERIPH_CLK_CFG value */
+#define MISC_GPT3SYNTH			0x00000400
+#define MISC_GPT4SYNTH			0x00000800
+#define CONFIG_SPEAR_UART48M		0
+#define CONFIG_SPEAR_UARTCLKMSK		(0x1 << 4)
+
+/* PRSC_CLK_CFG value */
+/*
+ * Fout = Fin / (2^(N+1) * (M + 1))
+ */
+#define MISC_PRSC_N_1			0x00001000
+#define MISC_PRSC_M_9			0x00000009
+#define MISC_PRSC_N_4			0x00004000
+#define MISC_PRSC_M_399			0x0000018F
+#define MISC_PRSC_N_6			0x00006000
+#define MISC_PRSC_M_2593		0x00000A21
+#define MISC_PRSC_M_124			0x0000007C
+#define MISC_PRSC_CFG			(MISC_PRSC_N_1 | MISC_PRSC_M_9)
+
+/* PERIPH1_CLKEN, PERIPH1_RST value */
+#define MISC_USBDENB			0x01000000
+#define MISC_ETHENB			0x00800000
+#define MISC_SMIENB			0x00200000
+#define MISC_GPIO3ENB			0x00040000
+#define MISC_GPT3ENB			0x00010000
+#define MISC_SSP3ENB			0x00004000
+#define MISC_GPIO4ENB			0x00002000
+#define MISC_GPT2ENB			0x00000800
+#define MISC_FSMCENB			0x00000200
+#define MISC_I2CENB			0x00000080
+#define MISC_SSP2ENB			0x00000040
+#define MISC_SSP1ENB			0x00000020
+#define MISC_UART0ENB			0x00000008
+
+/*   PERIPH_CLK_CFG   */
+#define  XTALTIMEEN		0x00000001
+#define  PLLTIMEEN		0x00000002
+#define  CLCDCLK_SYNTH		0x00000000
+#define  CLCDCLK_48MHZ		0x00000004
+#define  CLCDCLK_EXT		0x00000008
+#define  UARTCLK_MASK		(0x1 << 4)
+#define  UARTCLK_48MHZ		0x00000000
+#define  UARTCLK_SYNTH		0x00000010
+#define  IRDACLK_48MHZ		0x00000000
+#define  IRDACLK_SYNTH		0x00000020
+#define  IRDACLK_EXT		0x00000040
+#define  RTC_DISABLE		0x00000080
+#define  GPT1CLK_48MHZ		0x00000000
+#define  GPT1CLK_SYNTH		0x00000100
+#define  GPT2CLK_48MHZ		0x00000000
+#define  GPT2CLK_SYNTH		0x00000200
+#define  GPT3CLK_48MHZ		0x00000000
+#define  GPT3CLK_SYNTH		0x00000400
+#define  GPT4CLK_48MHZ		0x00000000
+#define  GPT4CLK_SYNTH		0x00000800
+#define  GPT5CLK_48MHZ		0x00000000
+#define  GPT5CLK_SYNTH		0x00001000
+#define  GPT1_FREEZE		0x00002000
+#define  GPT2_FREEZE		0x00004000
+#define  GPT3_FREEZE		0x00008000
+#define  GPT4_FREEZE		0x00010000
+#define  GPT5_FREEZE		0x00020000
+
+/*  PERIPH1_CLKEN bits  */
+#define PERIPH_ARM1_WE		0x00000001
+#define PERIPH_ARM1		0x00000002
+#define PERIPH_ARM2		0x00000004
+#define PERIPH_UART1		0x00000008
+#define PERIPH_UART2		0x00000010
+#define PERIPH_SSP1		0x00000020
+#define PERIPH_SSP2		0x00000040
+#define PERIPH_I2C		0x00000080
+#define PERIPH_JPEG		0x00000100
+#define PERIPH_FSMC		0x00000200
+#define PERIPH_FIRDA		0x00000400
+#define PERIPH_GPT4		0x00000800
+#define PERIPH_GPT5		0x00001000
+#define PERIPH_GPIO4		0x00002000
+#define PERIPH_SSP3		0x00004000
+#define PERIPH_ADC		0x00008000
+#define PERIPH_GPT3		0x00010000
+#define PERIPH_RTC		0x00020000
+#define PERIPH_GPIO3		0x00040000
+#define PERIPH_DMA		0x00080000
+#define PERIPH_ROM		0x00100000
+#define PERIPH_SMI		0x00200000
+#define PERIPH_CLCD		0x00400000
+#define PERIPH_GMAC		0x00800000
+#define PERIPH_USBD		0x01000000
+#define PERIPH_USBH1		0x02000000
+#define PERIPH_USBH2		0x04000000
+#define PERIPH_MPMC		0x08000000
+#define PERIPH_RAMW		0x10000000
+#define PERIPH_MPMC_EN		0x20000000
+#define PERIPH_MPMC_WE		0x40000000
+#define PERIPH_MPMCMSK		0x60000000
+
+#define PERIPH_CLK_ALL		0x0FFFFFF8
+#define PERIPH_RST_ALL		0x00000004
+
+/* DDR_PAD values */
+#define DDR_PAD_CNF_MSK		0x0000ffff
+#define DDR_PAD_SW_CONF		0x00060000
+#define DDR_PAD_SSTL_SEL	0x00000001
+#define DDR_PAD_DRAM_TYPE	0x00008000
+
+/* DDR_COMP values */
+#define DDR_COMP_ACCURATE	0x00000010
+
+/* SoC revision stuff */
+#define SOC_PRI_SHFT		16
+#define SOC_SEC_SHFT		8
+
+/* Revision definitions */
+#define SOC_SPEAR_NA		0
+
+/*
+ * The definitons have started from
+ * 101 for SPEAr6xx
+ * 201 for SPEAr3xx
+ * 301 for SPEAr13xx
+ */
+#define SOC_SPEAR600_AA		101
+#define SOC_SPEAR600_AB		102
+#define SOC_SPEAR600_BA		103
+#define SOC_SPEAR600_BB		104
+#define SOC_SPEAR600_BC		105
+#define SOC_SPEAR600_BD		106
+
+#define SOC_SPEAR300		201
+#define SOC_SPEAR310		202
+#define SOC_SPEAR320		203
+
+extern int get_socrev(void);
+int fsmc_nand_switch_ecc(uint32_t eccstrength);
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_ssp.h b/arch/arm/include/asm/arch-spear/spr_ssp.h
new file mode 100644
index 0000000..088d34b
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spr_ssp.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _SPR_SSP_H
+#define _SPR_SSP_H
+
+struct ssp_regs {
+	u32 sspcr0;
+	u32 sspcr1;
+	u32 sspdr;
+	u32 sspsr;
+	u32 sspcpsr;
+	u32 sspimsc;
+	u32 sspicr;
+	u32 sspdmacr;
+};
+
+#define SSPCR0_FRF_MOT_SPI	0x0000
+#define SSPCR0_DSS_16BITS	0x000f
+
+#define SSPCR1_SSE		0x0002
+
+#define SSPSR_TNF		0x2
+#define SSPSR_TFE		0x1
+
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_syscntl.h b/arch/arm/include/asm/arch-spear/spr_syscntl.h
new file mode 100644
index 0000000..6a83d87
--- /dev/null
+++ b/arch/arm/include/asm/arch-spear/spr_syscntl.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
+ */
+
+#ifndef __SYSCTRL_H
+#define __SYSCTRL_H
+
+struct syscntl_regs {
+	u32 scctrl;
+	u32 scsysstat;
+	u32 scimctrl;
+	u32 scimsysstat;
+	u32 scxtalctrl;
+	u32 scpllctrl;
+	u32 scpllfctrl;
+	u32 scperctrl0;
+	u32 scperctrl1;
+	u32 scperen;
+	u32 scperdis;
+	const u32 scperclken;
+	const u32 scperstat;
+};
+
+#define MODE_SHIFT          0x00000003
+
+#define NORMAL              0x00000004
+#define SLOW                0x00000002
+#define DOZE                0x00000001
+#define SLEEP               0x00000000
+
+#define PLL_TIM             0x01FFFFFF
+
+#endif
diff --git a/arch/arm/include/asm/arch-stih410/sdhci.h b/arch/arm/include/asm/arch-stih410/sdhci.h
new file mode 100644
index 0000000..105d358
--- /dev/null
+++ b/arch/arm/include/asm/arch-stih410/sdhci.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef __STI_SDHCI_H__
+#define __STI_SDHCI_H__
+
+#define FLASHSS_MMC_CORE_CONFIG_1			0x400
+#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ	BIT(24)
+#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN	BIT(12)
+
+#define STI_FLASHSS_MMC_CORE_CONFIG_1			\
+	(FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ	| \
+	 FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN)
+
+#define FLASHSS_MMC_CORE_CONFIG_2			0x404
+#define FLASHSS_MMC_CORECFG_HIGH_SPEED			BIT(28)
+#define FLASHSS_MMC_CORECFG_8BIT_EMMC			BIT(20)
+#define MAX_BLK_LENGTH_1024				BIT(16)
+#define BASE_CLK_FREQ_200				0xc8
+
+#define STI_FLASHSS_MMC_CORE_CONFIG2	\
+	(FLASHSS_MMC_CORECFG_HIGH_SPEED	| \
+	 FLASHSS_MMC_CORECFG_8BIT_EMMC	| \
+	 MAX_BLK_LENGTH_1024		| \
+	 BASE_CLK_FREQ_200 << 0)
+
+#define STI_FLASHSS_SDCARD_CORE_CONFIG2			\
+	(FLASHSS_MMC_CORECFG_HIGH_SPEED			| \
+	 MAX_BLK_LENGTH_1024				| \
+	 BASE_CLK_FREQ_200)
+
+#define FLASHSS_MMC_CORE_CONFIG_3			0x408
+#define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC		BIT(28)
+#define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT		BIT(20)
+#define FLASHSS_MMC_CORECFG_3P3_VOLT			BIT(8)
+#define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT		BIT(4)
+#define FLASHSS_MMC_CORECFG_SDMA			BIT(0)
+
+#define STI_FLASHSS_MMC_CORE_CONFIG3			\
+	 (FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC		| \
+	 FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT	| \
+	 FLASHSS_MMC_CORECFG_3P3_VOLT			| \
+	 FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT		| \
+	 FLASHSS_MMC_CORECFG_SDMA)
+
+#define STI_FLASHSS_SDCARD_CORE_CONFIG3			\
+	 (FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT	| \
+	 FLASHSS_MMC_CORECFG_3P3_VOLT			| \
+	 FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT		| \
+	 FLASHSS_MMC_CORECFG_SDMA)
+
+#define FLASHSS_MMC_CORE_CONFIG_4			0x40c
+#define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT		BIT(20)
+#define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT		BIT(16)
+#define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT		BIT(12)
+
+#define STI_FLASHSS_MMC_CORE_CONFIG4			\
+	(FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT		| \
+	 FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT		| \
+	 FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT)
+
+#define ST_MMC_CCONFIG_REG_5		0x210
+#define SYSCONF_MMC1_ENABLE_BIT		3
+
+#endif	/* _STI_SDHCI_H_ */
diff --git a/arch/arm/include/asm/arch-stih410/sys_proto.h b/arch/arm/include/asm/arch-stih410/sys_proto.h
new file mode 100644
index 0000000..f9e8d37
--- /dev/null
+++ b/arch/arm/include/asm/arch-stih410/sys_proto.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef _ASM_ARCH_SYS_PROTO_H
+#define _ASM_ARCH_SYS_PROTO_H
+
+#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/arch-stm32/gpio.h b/arch/arm/include/asm/arch-stm32/gpio.h
new file mode 100644
index 0000000..570e80a
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32/gpio.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#define STM32_GPIOS_PER_BANK		16
+
+enum stm32_gpio_port {
+	STM32_GPIO_PORT_A = 0,
+	STM32_GPIO_PORT_B,
+	STM32_GPIO_PORT_C,
+	STM32_GPIO_PORT_D,
+	STM32_GPIO_PORT_E,
+	STM32_GPIO_PORT_F,
+	STM32_GPIO_PORT_G,
+	STM32_GPIO_PORT_H,
+	STM32_GPIO_PORT_I
+};
+
+enum stm32_gpio_pin {
+	STM32_GPIO_PIN_0 = 0,
+	STM32_GPIO_PIN_1,
+	STM32_GPIO_PIN_2,
+	STM32_GPIO_PIN_3,
+	STM32_GPIO_PIN_4,
+	STM32_GPIO_PIN_5,
+	STM32_GPIO_PIN_6,
+	STM32_GPIO_PIN_7,
+	STM32_GPIO_PIN_8,
+	STM32_GPIO_PIN_9,
+	STM32_GPIO_PIN_10,
+	STM32_GPIO_PIN_11,
+	STM32_GPIO_PIN_12,
+	STM32_GPIO_PIN_13,
+	STM32_GPIO_PIN_14,
+	STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_mode {
+	STM32_GPIO_MODE_IN = 0,
+	STM32_GPIO_MODE_OUT,
+	STM32_GPIO_MODE_AF,
+	STM32_GPIO_MODE_AN
+};
+
+enum stm32_gpio_otype {
+	STM32_GPIO_OTYPE_PP = 0,
+	STM32_GPIO_OTYPE_OD
+};
+
+enum stm32_gpio_speed {
+	STM32_GPIO_SPEED_2M = 0,
+	STM32_GPIO_SPEED_25M,
+	STM32_GPIO_SPEED_50M,
+	STM32_GPIO_SPEED_100M
+};
+
+enum stm32_gpio_pupd {
+	STM32_GPIO_PUPD_NO = 0,
+	STM32_GPIO_PUPD_UP,
+	STM32_GPIO_PUPD_DOWN
+};
+
+enum stm32_gpio_af {
+	STM32_GPIO_AF0 = 0,
+	STM32_GPIO_AF1,
+	STM32_GPIO_AF2,
+	STM32_GPIO_AF3,
+	STM32_GPIO_AF4,
+	STM32_GPIO_AF5,
+	STM32_GPIO_AF6,
+	STM32_GPIO_AF7,
+	STM32_GPIO_AF8,
+	STM32_GPIO_AF9,
+	STM32_GPIO_AF10,
+	STM32_GPIO_AF11,
+	STM32_GPIO_AF12,
+	STM32_GPIO_AF13,
+	STM32_GPIO_AF14,
+	STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+	enum stm32_gpio_port	port;
+	enum stm32_gpio_pin	pin;
+};
+
+struct stm32_gpio_ctl {
+	enum stm32_gpio_mode	mode;
+	enum stm32_gpio_otype	otype;
+	enum stm32_gpio_speed	speed;
+	enum stm32_gpio_pupd	pupd;
+	enum stm32_gpio_af	af;
+};
+
+struct stm32_gpio_regs {
+	u32 moder;	/* GPIO port mode */
+	u32 otyper;	/* GPIO port output type */
+	u32 ospeedr;	/* GPIO port output speed */
+	u32 pupdr;	/* GPIO port pull-up/pull-down */
+	u32 idr;	/* GPIO port input data */
+	u32 odr;	/* GPIO port output data */
+	u32 bsrr;	/* GPIO port bit set/reset */
+	u32 lckr;	/* GPIO port configuration lock */
+	u32 afr[2];	/* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+	struct stm32_gpio_regs *regs;
+	unsigned int gpio_range;
+};
+
+int stm32_offset_to_index(struct udevice *dev, unsigned int offset);
+
+#endif /* _GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32/stm32f.h b/arch/arm/include/asm/arch-stm32/stm32f.h
new file mode 100644
index 0000000..bd3f4fd
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32/stm32f.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef _ASM_ARCH_STM32F_H
+#define _ASM_ARCH_STM32F_H
+
+#define STM32_PERIPH_BASE	0x40000000UL
+
+#define STM32_APB2_PERIPH_BASE	(STM32_PERIPH_BASE + 0x00010000)
+#define STM32_AHB1_PERIPH_BASE	(STM32_PERIPH_BASE + 0x00020000)
+
+#define STM32_SYSCFG_BASE	(STM32_APB2_PERIPH_BASE + 0x3800)
+#define STM32_FLASH_CNTL_BASE	(STM32_AHB1_PERIPH_BASE + 0x3C00)
+
+void stm32_flash_latency_cfg(int latency);
+
+#endif /* _ASM_ARCH_STM32F_H */
+
diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h
new file mode 100644
index 0000000..490f686
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/gpio.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+
+#include <asm/arch-stm32/gpio.h>
+
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
new file mode 100644
index 0000000..2094bd7
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ */
+
+#ifndef _MACH_STM32_H_
+#define _MACH_STM32_H_
+
+#include <asm/arch-stm32/stm32f.h>
+
+/*
+ * Peripheral memory map
+ */
+#define STM32_SYSMEM_BASE	0x1FFF0000
+
+/*
+ * Register maps
+ */
+struct stm32_u_id_regs {
+	u32 u_id_low;
+	u32 u_id_mid;
+	u32 u_id_high;
+};
+
+/*
+ * Registers access macros
+ */
+#define STM32_U_ID_BASE		(STM32_SYSMEM_BASE + 0x7A10)
+#define STM32_U_ID		((struct stm32_u_id_regs *)STM32_U_ID_BASE)
+static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
+	[0 ... 3] =	16 * 1024,
+	[4] =		64 * 1024,
+	[5 ... 11] =	128 * 1024
+};
+
+#endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
new file mode 100644
index 0000000..de42996
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN			BIT(16)
+#define PWR_CR1_ODSWEN			BIT(17)
+#define PWR_CSR1_ODRDY			BIT(16)
+#define PWR_CSR1_ODSWRDY		BIT(17)
+
+struct stm32_pwr_regs {
+	u32 cr1;   /* power control register 1 */
+	u32 csr1;  /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f7/gpio.h b/arch/arm/include/asm/arch-stm32f7/gpio.h
new file mode 100644
index 0000000..21f4e0f
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/gpio.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+
+#include <asm/arch-stm32/gpio.h>
+
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
new file mode 100644
index 0000000..3451e74
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#include <asm/arch-stm32/stm32f.h>
+
+static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
+	[0 ... 3] =	32 * 1024,
+	[4] =		128 * 1024,
+	[5 ... 7] =	256 * 1024
+};
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
new file mode 100644
index 0000000..c93fc5a
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef __STM32_PWR_H_
+
+/*
+ * Offsets of some PWR registers
+ */
+#define PWR_CR1_ODEN			BIT(16)
+#define PWR_CR1_ODSWEN			BIT(17)
+#define PWR_CSR1_ODRDY			BIT(16)
+#define PWR_CSR1_ODSWRDY		BIT(17)
+
+struct stm32_pwr_regs {
+	u32 cr1;   /* power control register 1 */
+	u32 csr1;  /* power control/status register 2 */
+	u32 cr2;   /* power control register 2 */
+	u32 csr2;  /* power control/status register 2 */
+};
+
+#endif /* __STM32_PWR_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f7/syscfg.h b/arch/arm/include/asm/arch-stm32f7/syscfg.h
new file mode 100644
index 0000000..ce2a952
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f7/syscfg.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016
+ * Michael Kurz, michi.kurz@gmail.com.
+ */
+
+#ifndef _STM32_SYSCFG_H
+#define _STM32_SYSCFG_H
+
+struct stm32_syscfg_regs {
+	u32 memrmp;
+	u32 pmc;
+	u32 exticr1;
+	u32 exticr2;
+	u32 exticr3;
+	u32 exticr4;
+	u32 cmpcr;
+};
+
+/*
+ * SYSCFG registers base
+ */
+#define STM32_SYSCFG		((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE)
+
+/* SYSCFG peripheral mode configuration register */
+#define SYSCFG_PMC_MII_RMII_SEL	BIT(23)
+
+#endif
diff --git a/arch/arm/include/asm/arch-stm32h7/gpio.h b/arch/arm/include/asm/arch-stm32h7/gpio.h
new file mode 100644
index 0000000..2dad52a
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32h7/gpio.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+
+#include <asm/arch-stm32/gpio.h>
+
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32h7/stm32.h b/arch/arm/include/asm/arch-stm32h7/stm32.h
new file mode 100644
index 0000000..458baca
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32h7/stm32.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+/*
+ * This empty files is needed to not break compilation
+ * Some common drivers to STM32F4/F7 and H7 include a stm32.h file
+ * Some cleanup need to be done to communalize all the following
+ * stm32.h files:
+ *
+ * arch/arm/include/asm/arch-stm32f1/stm32.h
+ * arch/arm/include/asm/arch-stm32f4/stm32.h
+ * arch/arm/include/asm/arch-stm32f7/stm32.h
+ */
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-stv0991/gpio.h b/arch/arm/include/asm/arch-stv0991/gpio.h
new file mode 100644
index 0000000..b27f407
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/gpio.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef __ASM_ARCH_STV0991_GPIO_H
+#define __ASM_ARCH_STV0991_GPIO_H
+
+enum gpio_direction {
+	GPIO_DIRECTION_IN,
+	GPIO_DIRECTION_OUT,
+};
+
+struct gpio_regs {
+	u32 data;		/* offset 0x0 */
+	u32 reserved[0xff];	/* 0x4--0x3fc */
+	u32 dir;		/* offset 0x400 */
+};
+
+#endif	/* __ASM_ARCH_STV0991_GPIO_H */
diff --git a/arch/arm/include/asm/arch-stv0991/hardware.h b/arch/arm/include/asm/arch-stv0991/hardware.h
new file mode 100644
index 0000000..ea8f820
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/hardware.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+/* STV0991 */
+#define SRAM0_BASE_ADDR                          0x00000000UL
+#define SRAM1_BASE_ADDR                          0x00068000UL
+#define SRAM2_BASE_ADDR                          0x000D0000UL
+#define SRAM3_BASE_ADDR                          0x00138000UL
+#define CFS_SRAM0_BASE_ADDR                      0x00198000UL
+#define CFS_SRAM1_BASE_ADDR                      0x001B8000UL
+#define FAST_SRAM_BASE_ADDR                      0x001D8000UL
+#define FLASH_BASE_ADDR                          0x40000000UL
+#define PL310_BASE_ADDR                          0x70000000UL
+#define HSAXIM_BASE_ADDR                         0x70100000UL
+#define IMGSS_BASE_ADDR                          0x70200000UL
+#define ADC_BASE_ADDR                            0x80000000UL
+#define GPIOA_BASE_ADDR                          0x80001000UL
+#define GPIOB_BASE_ADDR                          0x80002000UL
+#define GPIOC_BASE_ADDR                          0x80003000UL
+#define HDM_BASE_ADDR                            0x80004000UL
+#define THSENS_BASE_ADDR                         0x80200000UL
+#define GPTIMER2_BASE_ADDR                       0x80201000UL
+#define GPTIMER1_BASE_ADDR                       0x80202000UL
+#define QSPI_BASE_ADDR                           0x80203000UL
+#define CGU_BASE_ADDR                            0x80204000UL
+#define CREG_BASE_ADDR                           0x80205000UL
+#define PEC_BASE_ADDR                            0x80206000UL
+#define WDRU_BASE_ADDR                           0x80207000UL
+#define BSEC_BASE_ADDR                           0x80208000UL
+#define DAP_ROM_BASE_ADDR                        0x80210000UL
+#define SOC_CTI_BASE_ADDR                        0x80211000UL
+#define TPIU_BASE_ADDR                           0x80212000UL
+#define TMC_ETF_BASE_ADDR                        0x80213000UL
+#define R4_ETM_BASE_ADDR                         0x80214000UL
+#define R4_CTI_BASE_ADDR                         0x80215000UL
+#define R4_DBG_BASE_ADDR                         0x80216000UL
+#define GMAC_BASE_ADDR                           0x80300000UL
+#define RNSS_BASE_ADDR                           0x80302000UL
+#define CRYP_BASE_ADDR                           0x80303000UL
+#define HASH_BASE_ADDR                           0x80304000UL
+#define GPDMA_BASE_ADDR                          0x80305000UL
+#define ISA_BASE_ADDR                            0x8032A000UL
+#define HCI_BASE_ADDR                            0x80400000UL
+#define I2C1_BASE_ADDR                           0x80401000UL
+#define I2C2_BASE_ADDR                           0x80402000UL
+#define SAI_BASE_ADDR                            0x80403000UL
+#define USI_BASE_ADDR                            0x80404000UL
+#define SPI1_BASE_ADDR                           0x80405000UL
+#define UART_BASE_ADDR                           0x80406000UL
+#define SPI2_BASE_ADDR                           0x80500000UL
+#define CAN_BASE_ADDR                            0x80501000UL
+#define USART1_BASE_ADDR                         0x80502000UL
+#define USART2_BASE_ADDR                         0x80503000UL
+#define USART3_BASE_ADDR                         0x80504000UL
+#define USART4_BASE_ADDR                         0x80505000UL
+#define USART5_BASE_ADDR                         0x80506000UL
+#define USART6_BASE_ADDR                         0x80507000UL
+#define SDI2_BASE_ADDR                           0x80600000UL
+#define SDI1_BASE_ADDR                           0x80601000UL
+#define VICA_BASE_ADDR                           0x81000000UL
+#define VICB_BASE_ADDR                           0x81001000UL
+#define STM_CHANNELS_BASE_ADDR                   0x81100000UL
+#define STM_BASE_ADDR                            0x81110000UL
+#define SROM_BASE_ADDR                           0xFFFF0000UL
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
new file mode 100644
index 0000000..df9dd54
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef _STV0991_CGU_H
+#define _STV0991_CGU_H
+
+struct stv0991_cgu_regs {
+	u32 cpu_freq;		/* offset 0x0 */
+	u32 icn2_freq;		/* offset 0x4 */
+	u32 dma_freq;		/* offset 0x8 */
+	u32 isp_freq;		/* offset 0xc */
+	u32 h264_freq;		/* offset 0x10 */
+	u32 osif_freq;		/* offset 0x14 */
+	u32 ren_freq;		/* offset 0x18 */
+	u32 tim_freq;		/* offset 0x1c */
+	u32 sai_freq;		/* offset 0x20 */
+	u32 eth_freq;		/* offset 0x24 */
+	u32 i2c_freq;		/* offset 0x28 */
+	u32 spi_freq;		/* offset 0x2c */
+	u32 uart_freq;		/* offset 0x30 */
+	u32 qspi_freq;		/* offset 0x34 */
+	u32 sdio_freq;		/* offset 0x38 */
+	u32 usi_freq;		/* offset 0x3c */
+	u32 can_line_freq;	/* offset 0x40 */
+	u32 debug_freq;		/* offset 0x44 */
+	u32 trace_freq;		/* offset 0x48 */
+	u32 stm_freq;		/* offset 0x4c */
+	u32 eth_ctrl;		/* offset 0x50 */
+	u32 reserved[3];	/* offset 0x54 */
+	u32 osc_ctrl;		/* offset 0x60 */
+	u32 pll1_ctrl;		/* offset 0x64 */
+	u32 pll1_freq;		/* offset 0x68 */
+	u32 pll1_fract;		/* offset 0x6c */
+	u32 pll1_spread;	/* offset 0x70 */
+	u32 pll1_status;	/* offset 0x74 */
+	u32 pll2_ctrl;		/* offset 0x78 */
+	u32 pll2_freq;		/* offset 0x7c */
+	u32 pll2_fract;		/* offset 0x80 */
+	u32 pll2_spread;	/* offset 0x84 */
+	u32 pll2_status;	/* offset 0x88 */
+	u32 cgu_enable_1;	/* offset 0x8c */
+	u32 cgu_enable_2;	/* offset 0x90 */
+	u32 cgu_isp_pulse;	/* offset 0x94 */
+	u32 cgu_h264_pulse;	/* offset 0x98 */
+	u32 cgu_osif_pulse;	/* offset 0x9c */
+	u32 cgu_ren_pulse;	/* offset 0xa0 */
+
+};
+
+/* CGU Timer */
+#define CLK_TMR_OSC			0
+#define CLK_TMR_MCLK			1
+#define CLK_TMR_PLL1			2
+#define CLK_TMR_PLL2			3
+#define MDIV_SHIFT_TMR			3
+#define DIV_SHIFT_TMR			6
+
+#define TIMER1_CLK_CFG			(0 << DIV_SHIFT_TMR \
+					| 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
+
+/* Clock Enable/Disable */
+
+#define TIMER1_CLK_EN			(1 << 15)
+
+/* CGU Uart config */
+#define CLK_UART_MCLK			0
+#define CLK_UART_PLL1			1
+#define CLK_UART_PLL2			2
+
+#define MDIV_SHIFT_UART			3
+#define DIV_SHIFT_UART			6
+
+#define UART_CLK_CFG			(4 << DIV_SHIFT_UART \
+					| 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
+
+/* CGU Ethernet clock config */
+#define CLK_ETH_MCLK			0
+#define CLK_ETH_PLL1			1
+#define CLK_ETH_PLL2			2
+
+#define MDIV_SHIFT_ETH			3
+#define DIV_SHIFT_ETH			6
+#define DIV_ETH_125			9
+#define DIV_ETH_50			12
+#define DIV_ETH_P2P			15
+
+#define ETH_CLK_CFG			(4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
+					| 1 << DIV_ETH_125 \
+					| 0 << DIV_SHIFT_ETH \
+					| 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
+ /* CGU Ethernet control */
+
+#define ETH_CLK_TX_EXT_PHY		0
+#define ETH_CLK_TX_125M			1
+#define ETH_CLK_TX_25M			2
+#define ETH_CLK_TX_2M5			3
+#define ETH_CLK_TX_DIS			7
+
+#define ETH_CLK_RX_EXT_PHY		0
+#define ETH_CLK_RX_25M			1
+#define ETH_CLK_RX_2M5			2
+#define ETH_CLK_RX_DIS			3
+#define RX_CLK_SHIFT			3
+#define ETH_CLK_MASK			~(0x1F)
+
+#define ETH_PHY_MODE_GMII		0
+#define ETH_PHY_MODE_RMII		1
+#define ETH_PHY_CLK_DIS			1
+
+#define ETH_CLK_CTRL			(ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
+					| ETH_CLK_TX_EXT_PHY)
+/* CGU qspi clock */
+#define DIV_HCLK1_SHIFT			9
+#define DIV_CRYP_SHIFT			6
+#define MDIV_QSPI_SHIFT			3
+
+#define CLK_QSPI_OSC			0
+#define CLK_QSPI_MCLK			1
+#define CLK_QSPI_PLL1			2
+#define CLK_QSPI_PLL2			3
+
+#define QSPI_CLK_CTRL			(3 << DIV_HCLK1_SHIFT \
+					| 1 << DIV_CRYP_SHIFT \
+					| 0 << MDIV_QSPI_SHIFT \
+					| CLK_QSPI_OSC)
+
+#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_creg.h b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
new file mode 100644
index 0000000..4d444a6
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef _STV0991_CREG_H
+#define _STV0991_CREG_H
+
+struct stv0991_creg {
+	u32 version;		/* offset 0x0 */
+	u32 hdpctl;		/* offset 0x4 */
+	u32 hdpval;		/* offset 0x8 */
+	u32 hdpgposet;		/* offset 0xc */
+	u32 hdpgpoclr;		/* offset 0x10 */
+	u32 hdpgpoval;		/* offset 0x14 */
+	u32 stm_mux;		/* offset 0x18 */
+	u32 sysctrl_1;		/* offset 0x1c */
+	u32 sysctrl_2;		/* offset 0x20 */
+	u32 sysctrl_3;		/* offset 0x24 */
+	u32 sysctrl_4;		/* offset 0x28 */
+	u32 reserved_1[0x35];	/* offset 0x2C-0xFC */
+	u32 mux1;		/* offset 0x100 */
+	u32 mux2;		/* offset 0x104 */
+	u32 mux3;		/* offset 0x108 */
+	u32 mux4;		/* offset 0x10c */
+	u32 mux5;		/* offset 0x110 */
+	u32 mux6;		/* offset 0x114 */
+	u32 mux7;		/* offset 0x118 */
+	u32 mux8;		/* offset 0x11c */
+	u32 mux9;		/* offset 0x120 */
+	u32 mux10;		/* offset 0x124 */
+	u32 mux11;		/* offset 0x128 */
+	u32 mux12;		/* offset 0x12c */
+	u32 mux13;		/* offset 0x130 */
+	u32 reserved_2[0x33];	/* offset 0x134-0x1FC */
+	u32 cfg_pad1;		/* offset 0x200 */
+	u32 cfg_pad2;		/* offset 0x204 */
+	u32 cfg_pad3;		/* offset 0x208 */
+	u32 cfg_pad4;		/* offset 0x20c */
+	u32 cfg_pad5;		/* offset 0x210 */
+	u32 cfg_pad6;		/* offset 0x214 */
+	u32 cfg_pad7;		/* offset 0x218 */
+	u32 reserved_3[0x39];	/* offset 0x21C-0x2FC */
+	u32 vdd_pad1;		/* offset 0x300 */
+	u32 vdd_pad2;		/* offset 0x304 */
+	u32 reserved_4[0x3e];	/* offset 0x308-0x3FC */
+	u32 vdd_comp1;		/* offset 0x400 */
+};
+
+/* CREG MUX 13 register */
+#define FLASH_CS_NC_SHIFT	4
+#define FLASH_CS_NC_MASK	~(7 << FLASH_CS_NC_SHIFT)
+#define CFG_FLASH_CS_NC		(0 << FLASH_CS_NC_SHIFT)
+
+#define FLASH_CLK_SHIFT		0
+#define FLASH_CLK_MASK		~(7 << FLASH_CLK_SHIFT)
+#define CFG_FLASH_CLK		(0 << FLASH_CLK_SHIFT)
+
+/* CREG MUX 12 register */
+#define GPIOC_30_MUX_SHIFT	24
+#define GPIOC_30_MUX_MASK	~(1 << GPIOC_30_MUX_SHIFT)
+#define CFG_GPIOC_30_UART_TX	(1 << GPIOC_30_MUX_SHIFT)
+
+#define GPIOC_31_MUX_SHIFT	28
+#define GPIOC_31_MUX_MASK	~(1 << GPIOC_31_MUX_SHIFT)
+#define CFG_GPIOC_31_UART_RX	(1 << GPIOC_31_MUX_SHIFT)
+
+/* CREG MUX 7 register */
+#define GPIOB_16_MUX_SHIFT	0
+#define GPIOB_16_MUX_MASK	~(1 << GPIOB_16_MUX_SHIFT)
+#define CFG_GPIOB_16_UART_TX	(1 << GPIOB_16_MUX_SHIFT)
+
+#define GPIOB_17_MUX_SHIFT	4
+#define GPIOB_17_MUX_MASK	~(1 << GPIOB_17_MUX_SHIFT)
+#define CFG_GPIOB_17_UART_RX	(1 << GPIOB_17_MUX_SHIFT)
+
+/* CREG CFG_PAD6 register */
+
+#define GPIOC_31_MODE_SHIFT	30
+#define GPIOC_31_MODE_MASK	~(1 << GPIOC_31_MODE_SHIFT)
+#define CFG_GPIOC_31_MODE_OD	(0 << GPIOC_31_MODE_SHIFT)
+#define CFG_GPIOC_31_MODE_PP	(1 << GPIOC_31_MODE_SHIFT)
+
+#define GPIOC_30_MODE_SHIFT	28
+#define GPIOC_30_MODE_MASK	~(1 << GPIOC_30_MODE_SHIFT)
+#define CFG_GPIOC_30_MODE_LOW	(0 << GPIOC_30_MODE_SHIFT)
+#define CFG_GPIOC_30_MODE_HIGH	(1 << GPIOC_30_MODE_SHIFT)
+
+/* CREG Ethernet pad config */
+
+#define VDD_ETH_PS_1V8		0
+#define VDD_ETH_PS_2V5		2
+#define VDD_ETH_PS_3V3		3
+#define VDD_ETH_PS_MASK		0x3
+
+#define VDD_ETH_PS_SHIFT	12
+#define ETH_VDD_CFG		(VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT)
+
+#define VDD_ETH_M_PS_SHIFT	28
+#define ETH_M_VDD_CFG		(VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT)
+
+#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_defs.h b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h
new file mode 100644
index 0000000..97d28b2
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_defs.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef __STV0991_DEFS_H__
+#define __STV0991_DEFS_H__
+#include <asm/arch/stv0991_periph.h>
+
+extern int stv0991_pinmux_config(enum periph_id);
+extern int clock_setup(enum periph_clock);
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
new file mode 100644
index 0000000..cd27472
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef _STV0991_GPT_H
+#define _STV0991_GPT_H
+
+#include <asm/arch-stv0991/hardware.h>
+
+struct gpt_regs {
+	u32 cr1;
+	u32 cr2;
+	u32 reserved_1;
+	u32 dier;	/* dma_int_en */
+	u32 sr;		/* status reg */
+	u32 egr;	/* event gen */
+	u32 reserved_2[3];	/* offset 0x18--0x20*/
+	u32 cnt;
+	u32 psc;
+	u32 arr;
+};
+
+struct gpt_regs *const gpt1_regs_ptr =
+	(struct gpt_regs *) GPTIMER1_BASE_ADDR;
+
+/* Timer control1 register  */
+#define GPT_CR1_CEN			0x0001
+#define GPT_MODE_AUTO_RELOAD		(1 << 7)
+
+/* Timer prescalar reg */
+#define GPT_PRESCALER_128		0x128
+
+/* Auto reload register for free running config */
+#define GPT_FREE_RUNNING		0xFFFF
+
+/* Timer, HZ specific defines */
+#define CONFIG_STV0991_HZ		1000
+#define CONFIG_STV0991_HZ_CLOCK		(27*1000*1000)/GPT_PRESCALER_128
+
+#endif
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_periph.h b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
new file mode 100644
index 0000000..7a50be1
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals required for pinmux configuration. List will
+ * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
+ *
+ */
+enum periph_id {
+	UART_GPIOC_30_31 = 0,
+	UART_GPIOB_16_17,
+	ETH_GPIOB_10_31_C_0_4,
+	QSPI_CS_CLK_PAD,
+	PERIPH_ID_I2C0,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_I2C4,
+	PERIPH_ID_I2C5,
+	PERIPH_ID_I2C6,
+	PERIPH_ID_I2C7,
+	PERIPH_ID_SPI0,
+	PERIPH_ID_SPI1,
+	PERIPH_ID_SPI2,
+	PERIPH_ID_SDMMC0,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_I2S1,
+};
+
+enum periph_clock {
+	UART_CLOCK_CFG = 0,
+	ETH_CLOCK_CFG,
+	QSPI_CLOCK_CFG,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
new file mode 100644
index 0000000..8cb8a8a
--- /dev/null
+++ b/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef _STV0991_WD_RST_H
+#define _STV0991_WD_RST_H
+#include <asm/arch-stv0991/hardware.h>
+
+struct stv0991_wd_ru {
+	u32 wdru_config;
+	u32 wdru_ctrl1;
+	u32 wdru_ctrl2;
+	u32 wdru_tim;
+	u32 wdru_count;
+	u32 wdru_stat;
+	u32 wdru_wrlock;
+};
+
+struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \
+		(struct stv0991_wd_ru *)WDRU_BASE_ADDR;
+
+/* Watchdog control register */
+#define WDRU_RST_SYS		0x1
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
new file mode 100644
index 0000000..54c144a
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Allwinner A64 (sun50i) CPU
+ */
+
+#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD)
+/* reserve space for BOOT0 header information */
+	b	reset
+	.space	1532
+#elif defined(CONFIG_ARM_BOOT_HOOK_RMR)
+/*
+ * Switch into AArch64 if needed.
+ * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source.
+ */
+	tst     x0, x0                  // this is "b #0x84" in ARM
+	b       reset
+	.space  0x7c
+	.word	0xe59f1024	// ldr     r1, [pc, #36] ; 0x170000a0
+	.word	0xe59f0024	// ldr     r0, [pc, #36] ; CONFIG_*_TEXT_BASE
+	.word	0xe5810000	// str     r0, [r1]
+	.word	0xf57ff04f	// dsb     sy
+	.word	0xf57ff06f	// isb     sy
+	.word	0xee1c0f50	// mrc     15, 0, r0, cr12, cr0, {2} ; RMR
+	.word	0xe3800003	// orr     r0, r0, #3
+	.word	0xee0c0f50	// mcr     15, 0, r0, cr12, cr0, {2} ; RMR
+	.word	0xf57ff06f	// isb     sy
+	.word	0xe320f003	// wfi
+	.word	0xeafffffd	// b       @wfi
+#ifndef CONFIG_MACH_SUN50I_H6
+	.word	0x017000a0	// writeable RVBAR mapping address
+#else
+	.word	0x09010040	// writeable RVBAR mapping address
+#endif
+#ifdef CONFIG_SPL_BUILD
+	.word	CONFIG_SPL_TEXT_BASE
+#else
+	.word   CONFIG_SYS_TEXT_BASE
+#endif
+#else
+/* normal execution */
+	b	reset
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h
new file mode 100644
index 0000000..5dd97ab
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/ccu.h
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#ifndef _ASM_ARCH_CCU_H
+#define _ASM_ARCH_CCU_H
+
+/**
+ * enum ccu_flags - ccu clock/reset flags
+ *
+ * @CCU_CLK_F_IS_VALID:		is given clock gate is valid?
+ * @CCU_RST_F_IS_VALID:		is given reset control is valid?
+ */
+enum ccu_flags {
+	CCU_CLK_F_IS_VALID		= BIT(0),
+	CCU_RST_F_IS_VALID		= BIT(1),
+};
+
+/**
+ * struct ccu_clk_gate - ccu clock gate
+ * @off:	gate offset
+ * @bit:	gate bit
+ * @flags:	ccu clock gate flags
+ */
+struct ccu_clk_gate {
+	u16 off;
+	u32 bit;
+	enum ccu_flags flags;
+};
+
+#define GATE(_off, _bit) {			\
+	.off = _off,				\
+	.bit = _bit,				\
+	.flags = CCU_CLK_F_IS_VALID,		\
+}
+
+/**
+ * struct ccu_reset - ccu reset
+ * @off:	reset offset
+ * @bit:	reset bit
+ * @flags:	ccu reset control flags
+ */
+struct ccu_reset {
+	u16 off;
+	u32 bit;
+	enum ccu_flags flags;
+};
+
+#define RESET(_off, _bit) {			\
+	.off = _off,				\
+	.bit = _bit,				\
+	.flags = CCU_RST_F_IS_VALID,		\
+}
+
+/**
+ * struct ccu_desc - clock control unit descriptor
+ *
+ * @gates:	clock gates
+ * @resets:	reset unit
+ */
+struct ccu_desc {
+	const struct ccu_clk_gate *gates;
+	const struct ccu_reset *resets;
+};
+
+/**
+ * struct ccu_priv - sunxi clock control unit
+ *
+ * @base:	base address
+ * @desc:	ccu descriptor
+ */
+struct ccu_priv {
+	void *base;
+	const struct ccu_desc *desc;
+};
+
+/**
+ * sunxi_clk_probe - common sunxi clock probe
+ * @dev:	clock device
+ */
+int sunxi_clk_probe(struct udevice *dev);
+
+extern struct clk_ops sunxi_clk_ops;
+
+/**
+ * sunxi_reset_bind() - reset binding
+ *
+ * @dev:       reset device
+ * @count:     reset count
+ * @return 0 success, or error value
+ */
+int sunxi_reset_bind(struct udevice *dev, ulong count);
+
+#endif /* _ASM_ARCH_CCU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
new file mode 100644
index 0000000..5994130
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#ifndef _SUNXI_CLOCK_H
+#define _SUNXI_CLOCK_H
+
+#include <linux/types.h>
+
+#define CLK_GATE_OPEN			0x1
+#define CLK_GATE_CLOSE			0x0
+
+/* clock control module regs definition */
+#if defined(CONFIG_MACH_SUN8I_A83T)
+#include <asm/arch/clock_sun8i_a83t.h>
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#include <asm/arch/clock_sun50i_h6.h>
+#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
+      defined(CONFIG_MACH_SUN50I)
+#include <asm/arch/clock_sun6i.h>
+#elif defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/clock_sun9i.h>
+#else
+#include <asm/arch/clock_sun4i.h>
+#endif
+
+#ifndef __ASSEMBLY__
+int clock_init(void);
+int clock_twi_onoff(int port, int state);
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
+void clock_init_safe(void);
+void clock_init_sec(void);
+void clock_init_uart(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
new file mode 100644
index 0000000..2cec91c
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -0,0 +1,362 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * sun4i, sun5i and sun7i clock register definitions
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#ifndef _SUNXI_CLOCK_SUN4I_H
+#define _SUNXI_CLOCK_SUN4I_H
+
+struct sunxi_ccm_reg {
+	u32 pll1_cfg;		/* 0x00 pll1 control */
+	u32 pll1_tun;		/* 0x04 pll1 tuning */
+	u32 pll2_cfg;		/* 0x08 pll2 control */
+	u32 pll2_tun;		/* 0x0c pll2 tuning */
+	u32 pll3_cfg;		/* 0x10 pll3 control */
+	u8 res0[0x4];
+	u32 pll4_cfg;		/* 0x18 pll4 control */
+	u8 res1[0x4];
+	u32 pll5_cfg;		/* 0x20 pll5 control */
+	u32 pll5_tun;		/* 0x24 pll5 tuning */
+	u32 pll6_cfg;		/* 0x28 pll6 control */
+	u32 pll6_tun;		/* 0x2c pll6 tuning */
+	u32 pll7_cfg;		/* 0x30 pll7 control */
+	u32 pll1_tun2;		/* 0x34 pll5 tuning2 */
+	u8 res2[0x4];
+	u32 pll5_tun2;		/* 0x3c pll5 tuning2 */
+	u8 res3[0xc];
+	u32 pll_lock_dbg;	/* 0x4c pll lock time debug */
+	u32 osc24m_cfg;		/* 0x50 osc24m control */
+	u32 cpu_ahb_apb0_cfg;	/* 0x54 cpu,ahb and apb0 divide ratio */
+	u32 apb1_clk_div_cfg;	/* 0x58 apb1 clock dividor */
+	u32 axi_gate;		/* 0x5c axi module clock gating */
+	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
+	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
+	u32 apb0_gate;		/* 0x68 apb0 module clock gating */
+	u32 apb1_gate;		/* 0x6c apb1 module clock gating */
+	u8 res4[0x10];
+	u32 nand0_clk_cfg;	/* 0x80 nand sub clock control */
+	u32 ms_sclk_cfg;	/* 0x84 memory stick sub clock control */
+	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
+	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
+	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
+	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
+	u32 ts_clk_cfg;		/* 0x98 transport stream clock control */
+	u32 ss_clk_cfg;		/* 0x9c */
+	u32 spi0_clk_cfg;	/* 0xa0 */
+	u32 spi1_clk_cfg;	/* 0xa4 */
+	u32 spi2_clk_cfg;	/* 0xa8 */
+	u32 pata_clk_cfg;	/* 0xac */
+	u32 ir0_clk_cfg;	/* 0xb0 */
+	u32 ir1_clk_cfg;	/* 0xb4 */
+	u32 iis_clk_cfg;	/* 0xb8 */
+	u32 ac97_clk_cfg;	/* 0xbc */
+	u32 spdif_clk_cfg;	/* 0xc0 */
+	u32 keypad_clk_cfg;	/* 0xc4 */
+	u32 sata_clk_cfg;	/* 0xc8 */
+	u32 usb_clk_cfg;	/* 0xcc */
+	u32 gps_clk_cfg;	/* 0xd0 */
+	u32 spi3_clk_cfg;	/* 0xd4 */
+	u8 res5[0x28];
+	u32 dram_clk_gate;	/* 0x100 */
+	u32 be0_clk_cfg;	/* 0x104 */
+	u32 be1_clk_cfg;	/* 0x108 */
+	u32 fe0_clk_cfg;	/* 0x10c */
+	u32 fe1_clk_cfg;	/* 0x110 */
+	u32 mp_clk_cfg;		/* 0x114 */
+	u32 lcd0_ch0_clk_cfg;	/* 0x118 */
+	u32 lcd1_ch0_clk_cfg;	/* 0x11c */
+	u32 csi_isp_clk_cfg;	/* 0x120 */
+	u8 res6[0x4];
+	u32 tvd_clk_reg;	/* 0x128 */
+	u32 lcd0_ch1_clk_cfg;	/* 0x12c */
+	u32 lcd1_ch1_clk_cfg;	/* 0x130 */
+	u32 csi0_clk_cfg;	/* 0x134 */
+	u32 csi1_clk_cfg;	/* 0x138 */
+	u32 ve_clk_cfg;		/* 0x13c */
+	u32 audio_codec_clk_cfg;	/* 0x140 */
+	u32 avs_clk_cfg;	/* 0x144 */
+	u32 ace_clk_cfg;	/* 0x148 */
+	u32 lvds_clk_cfg;	/* 0x14c */
+	u32 hdmi_clk_cfg;	/* 0x150 */
+	u32 mali_clk_cfg;	/* 0x154 */
+	u8 res7[0x4];
+	u32 mbus_clk_cfg;	/* 0x15c */
+	u8 res8[0x4];
+	u32 gmac_clk_cfg;	/* 0x164 */
+};
+
+/* apb1 bit field */
+#define APB1_CLK_SRC_OSC24M		(0x0 << 24)
+#define APB1_CLK_SRC_PLL6		(0x1 << 24)
+#define APB1_CLK_SRC_LOSC		(0x2 << 24)
+#define APB1_CLK_SRC_MASK		(0x3 << 24)
+#define APB1_CLK_RATE_N_1		(0x0 << 16)
+#define APB1_CLK_RATE_N_2		(0x1 << 16)
+#define APB1_CLK_RATE_N_4		(0x2 << 16)
+#define APB1_CLK_RATE_N_8		(0x3 << 16)
+#define APB1_CLK_RATE_N_MASK		(3 << 16)
+#define APB1_CLK_RATE_M(m)		(((m)-1) << 0)
+#define APB1_CLK_RATE_M_MASK            (0x1f << 0)
+
+/* apb1 gate field */
+#define APB1_GATE_UART_SHIFT	(16)
+#define APB1_GATE_UART_MASK		(0xff << APB1_GATE_UART_SHIFT)
+#define APB1_GATE_TWI_SHIFT	(0)
+#define APB1_GATE_TWI_MASK		(0xf << APB1_GATE_TWI_SHIFT)
+
+/* clock divide */
+#define AXI_DIV_SHIFT		(0)
+#define AXI_DIV_1			0
+#define AXI_DIV_2			1
+#define AXI_DIV_3			2
+#define AXI_DIV_4			3
+#define AHB_DIV_SHIFT		(4)
+#define AHB_DIV_1			0
+#define AHB_DIV_2			1
+#define AHB_DIV_4			2
+#define AHB_DIV_8			3
+#define APB0_DIV_SHIFT		(8)
+#define APB0_DIV_1			0
+#define APB0_DIV_2			1
+#define APB0_DIV_4			2
+#define APB0_DIV_8			3
+#define CPU_CLK_SRC_SHIFT	(16)
+#define CPU_CLK_SRC_OSC24M		1
+#define CPU_CLK_SRC_PLL1		2
+
+#define CCM_PLL1_CFG_ENABLE_SHIFT		31
+#define CCM_PLL1_CFG_VCO_RST_SHIFT		30
+#define CCM_PLL1_CFG_VCO_BIAS_SHIFT		26
+#define CCM_PLL1_CFG_PLL4_EXCH_SHIFT		25
+#define CCM_PLL1_CFG_BIAS_CUR_SHIFT		20
+#define CCM_PLL1_CFG_DIVP_SHIFT			16
+#define CCM_PLL1_CFG_LCK_TMR_SHIFT		13
+#define CCM_PLL1_CFG_FACTOR_N_SHIFT		8
+#define CCM_PLL1_CFG_FACTOR_K_SHIFT		4
+#define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT	3
+#define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT	2
+#define CCM_PLL1_CFG_FACTOR_M_SHIFT		0
+
+#define PLL1_CFG_DEFAULT	0xa1005000
+
+#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
+/*
+ * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
+ * halving the mbus frequency, so set it to 300 MHz ourselves and base the
+ * mbus divider on that.
+ */
+#define PLL6_CFG_DEFAULT	0xa1009900
+#else
+#define PLL6_CFG_DEFAULT	0xa1009911
+#endif
+
+/* nand clock */
+#define NAND_CLK_SRC_OSC24		0
+#define NAND_CLK_DIV_N			0
+#define NAND_CLK_DIV_M			0
+
+/* gps clock */
+#define GPS_SCLK_GATING_OFF		0
+#define GPS_RESET			0
+
+/* ahb clock gate bit offset */
+#define AHB_GATE_OFFSET_GPS		26
+#define AHB_GATE_OFFSET_SATA		25
+#define AHB_GATE_OFFSET_PATA		24
+#define AHB_GATE_OFFSET_SPI3		23
+#define AHB_GATE_OFFSET_SPI2		22
+#define AHB_GATE_OFFSET_SPI1		21
+#define AHB_GATE_OFFSET_SPI0		20
+#define AHB_GATE_OFFSET_TS0		18
+#define AHB_GATE_OFFSET_EMAC		17
+#define AHB_GATE_OFFSET_ACE		16
+#define AHB_GATE_OFFSET_DLL		15
+#define AHB_GATE_OFFSET_SDRAM		14
+#define AHB_GATE_OFFSET_NAND0		13
+#define AHB_GATE_OFFSET_MS		12
+#define AHB_GATE_OFFSET_MMC3		11
+#define AHB_GATE_OFFSET_MMC2		10
+#define AHB_GATE_OFFSET_MMC1		9
+#define AHB_GATE_OFFSET_MMC0		8
+#define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_BIST		7
+#define AHB_GATE_OFFSET_DMA		6
+#define AHB_GATE_OFFSET_SS		5
+#define AHB_GATE_OFFSET_USB_OHCI1	4
+#define AHB_GATE_OFFSET_USB_EHCI1	3
+#define AHB_GATE_OFFSET_USB_OHCI0	2
+#define AHB_GATE_OFFSET_USB_EHCI0	1
+#define AHB_GATE_OFFSET_USB0		0
+
+/* ahb clock gate bit offset (second register) */
+#define AHB_GATE_OFFSET_GMAC		17
+#define AHB_GATE_OFFSET_DE_FE0		14
+#define AHB_GATE_OFFSET_DE_BE0		12
+#define AHB_GATE_OFFSET_HDMI		11
+#define AHB_GATE_OFFSET_LCD1		5
+#define AHB_GATE_OFFSET_LCD0		4
+#define AHB_GATE_OFFSET_TVE1		3
+#define AHB_GATE_OFFSET_TVE0		2
+
+#define CCM_AHB_GATE_GPS (0x1 << 26)
+#define CCM_AHB_GATE_SDRAM (0x1 << 14)
+#define CCM_AHB_GATE_DLL (0x1 << 15)
+#define CCM_AHB_GATE_ACE (0x1 << 16)
+
+#define CCM_PLL3_CTRL_M_SHIFT		0
+#define CCM_PLL3_CTRL_M_MASK		(0x7f << CCM_PLL3_CTRL_M_SHIFT)
+#define CCM_PLL3_CTRL_M(n)		(((n) & 0x7f) << 0)
+#define CCM_PLL3_CTRL_INTEGER_MODE	(0x1 << 15)
+#define CCM_PLL3_CTRL_EN		(0x1 << 31)
+
+#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0)
+#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
+#define CCM_PLL5_CTRL_M_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2)
+#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
+#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4)
+#define CCM_PLL5_CTRL_K_SHIFT 4
+#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
+#define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_LDO (0x1 << 7)
+#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8)
+#define CCM_PLL5_CTRL_N_SHIFT 8
+#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
+#define CCM_PLL5_CTRL_N_X(n) (n)
+#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16)
+#define CCM_PLL5_CTRL_P_SHIFT 16
+#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
+#define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_BW (0x1 << 18)
+#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19)
+#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20)
+#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f)
+#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1)
+#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25)
+#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29)
+#define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
+#define CCM_PLL5_CTRL_EN (0x1 << 31)
+
+#define CCM_PLL6_CTRL_EN		31
+#define CCM_PLL6_CTRL_BYPASS_EN		30
+#define CCM_PLL6_CTRL_SATA_EN_SHIFT	14
+#define CCM_PLL6_CTRL_N_SHIFT		8
+#define CCM_PLL6_CTRL_N_MASK		(0x1f << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT		4
+#define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
+
+#define CCM_GPS_CTRL_RESET (0x1 << 0)
+#define CCM_GPS_CTRL_GATE (0x1 << 1)
+
+#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15)
+
+#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0)
+#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf)
+#define CCM_MBUS_CTRL_M_X(n) ((n) - 1)
+#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16)
+#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf)
+#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0)))
+#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24)
+#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3)
+#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0
+#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1
+#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
+#define CCM_MBUS_CTRL_GATE (0x1 << 31)
+
+#define CCM_NAND_CTRL_M(x)		((x) - 1)
+#define CCM_NAND_CTRL_N(x)		((x) << 16)
+#define CCM_NAND_CTRL_OSCM24		(0x0 << 24)
+#define CCM_NAND_CTRL_PLL6		(0x1 << 24)
+#define CCM_NAND_CTRL_PLL5		(0x2 << 24)
+#define CCM_NAND_CTRL_ENABLE		(0x1 << 31)
+
+#define CCM_MMC_CTRL_M(x)		((x) - 1)
+#define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
+#define CCM_MMC_CTRL_N(x)		((x) << 16)
+#define CCM_MMC_CTRL_SCLK_DLY(x)	((x) << 20)
+#define CCM_MMC_CTRL_OSCM24		(0x0 << 24)
+#define CCM_MMC_CTRL_PLL6		(0x1 << 24)
+#define CCM_MMC_CTRL_PLL5		(0x2 << 24)
+#define CCM_MMC_CTRL_ENABLE		(0x1 << 31)
+
+#define CCM_DRAM_GATE_OFFSET_DE_FE1	24 /* Note the order of FE1 and */
+#define CCM_DRAM_GATE_OFFSET_DE_FE0	25 /* FE0 is swapped ! */
+#define CCM_DRAM_GATE_OFFSET_DE_BE0	26
+#define CCM_DRAM_GATE_OFFSET_DE_BE1	27
+
+#define CCM_LCD_CH0_CTRL_PLL3		(0 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7		(1 << 24)
+#define CCM_LCD_CH0_CTRL_PLL3_2X	(2 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7_2X	(3 << 24)
+#define CCM_LCD_CH0_CTRL_MIPI_PLL	0 /* No mipi pll on sun4i/5i/7i */
+#ifdef CONFIG_MACH_SUN5I
+#define CCM_LCD_CH0_CTRL_TVE_RST	(0x1 << 29)
+#else
+#define CCM_LCD_CH0_CTRL_TVE_RST	0 /* No separate tve-rst on sun4i/7i */
+#endif
+#define CCM_LCD_CH0_CTRL_RST		(0x1 << 30)
+#define CCM_LCD_CH0_CTRL_GATE		(0x1 << 31)
+
+#define CCM_LCD_CH1_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_LCD_CH1_CTRL_HALF_SCLK1	(1 << 11)
+#define CCM_LCD_CH1_CTRL_PLL3		(0 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7		(1 << 24)
+#define CCM_LCD_CH1_CTRL_PLL3_2X	(2 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7_2X	(3 << 24)
+/* Enable / disable both ch1 sclk1 and sclk2 at the same time */
+#define CCM_LCD_CH1_CTRL_GATE		(0x1 << 31 | 0x1 << 15)
+
+#define CCM_LVDS_CTRL_RST		(1 << 0)
+
+#define CCM_HDMI_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_HDMI_CTRL_PLL_MASK		(3 << 24)
+#define CCM_HDMI_CTRL_PLL3		(0 << 24)
+#define CCM_HDMI_CTRL_PLL7		(1 << 24)
+#define CCM_HDMI_CTRL_PLL3_2X		(2 << 24)
+#define CCM_HDMI_CTRL_PLL7_2X		(3 << 24)
+/* No separate ddc gate on sun4i, sun5i and sun7i */
+#define CCM_HDMI_CTRL_DDC_GATE		0
+#define CCM_HDMI_CTRL_GATE		(0x1 << 31)
+
+#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
+#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
+#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
+#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
+#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+#define CCM_GMAC_CTRL_RX_CLK_DELAY(x)	((x) << 5)
+#define CCM_GMAC_CTRL_TX_CLK_DELAY(x)	((x) << 10)
+
+#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
+#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 6)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 7)
+#define CCM_USB_CTRL_PHYGATE (0x1 << 8)
+/* These 3 are sun6i only, define them as 0 on sun4i */
+#define CCM_USB_CTRL_PHY0_CLK 0
+#define CCM_USB_CTRL_PHY1_CLK 0
+#define CCM_USB_CTRL_PHY2_CLK 0
+
+/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
+#define CCM_DE_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_DE_CTRL_PLL_MASK		(3 << 24)
+#define CCM_DE_CTRL_PLL3		(0 << 24)
+#define CCM_DE_CTRL_PLL7		(1 << 24)
+#define CCM_DE_CTRL_PLL5P		(2 << 24)
+#define CCM_DE_CTRL_RST			(1 << 30)
+#define CCM_DE_CTRL_GATE		(1 << 31)
+
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
+unsigned int clock_get_pll3(void);
+unsigned int clock_get_pll5p(void);
+unsigned int clock_get_pll6(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
new file mode 100644
index 0000000..e369370
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -0,0 +1,320 @@
+/*
+ * Allwinner H6 clock register definitions
+ *
+ * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN50I_H6_H
+#define _SUNXI_CLOCK_SUN50I_H6_H
+
+struct sunxi_ccm_reg {
+	u32 pll1_cfg;		/* 0x000 pll1 (cpux) control */
+	u8 reserved_0x004[12];
+	u32 pll5_cfg;		/* 0x010 pll5 (ddr) control */
+	u8 reserved_0x014[12];
+	u32 pll6_cfg;		/* 0x020 pll6 (periph0) control */
+	u8 reserved_0x020[4];
+	u32 pll_periph1_cfg;	/* 0x028 pll periph1 control */
+	u8 reserved_0x028[4];
+	u32 pll7_cfg;		/* 0x030 pll7 (gpu) control */
+	u8 reserved_0x034[12];
+	u32 pll3_cfg;		/* 0x040 pll3 (video0) control */
+	u8 reserved_0x044[4];
+	u32 pll_video1_cfg;	/* 0x048 pll video1 control */
+	u8 reserved_0x04c[12];
+	u32 pll4_cfg;		/* 0x058 pll4 (ve) control */
+	u8 reserved_0x05c[4];
+	u32 pll10_cfg;		/* 0x060 pll10 (de) control */
+	u8 reserved_0x064[12];
+	u32 pll9_cfg;		/* 0x070 pll9 (hsic) control */
+	u8 reserved_0x074[4];
+	u32 pll2_cfg;		/* 0x078 pll2 (audio) control */
+	u8 reserved_0x07c[148];
+	u32 pll5_pat;		/* 0x110 pll5 (ddr) pattern */
+	u8 reserved_0x114[20];
+	u32 pll_periph1_pat0;	/* 0x128 pll periph1 pattern0 */
+	u32 pll_periph1_pat1;	/* 0x12c pll periph1 pattern1 */
+	u32 pll7_pat0;		/* 0x130 pll7 (gpu) pattern0 */
+	u32 pll7_pat1;		/* 0x134 pll7 (gpu) pattern1 */
+	u8 reserved_0x138[8];
+	u32 pll3_pat0;		/* 0x140 pll3 (video0) pattern0 */
+	u32 pll3_pat1;		/* 0x144 pll3 (video0) pattern1 */
+	u32 pll_video1_pat0;	/* 0x148 pll video1 pattern0 */
+	u32 pll_video1_pat1;	/* 0x14c pll video1 pattern1 */
+	u8 reserved_0x150[8];
+	u32 pll4_pat0;		/* 0x158 pll4 (ve) pattern0 */
+	u32 pll4_pat1;		/* 0x15c pll4 (ve) pattern1 */
+	u32 pll10_pat0;		/* 0x160 pll10 (de) pattern0 */
+	u32 pll10_pat1;		/* 0x164 pll10 (de) pattern1 */
+	u8 reserved_0x168[8];
+	u32 pll9_pat0;		/* 0x170 pll9 (hsic) pattern0 */
+	u32 pll9_pat1;		/* 0x174 pll9 (hsic) pattern1 */
+	u32 pll2_pat0;		/* 0x178 pll2 (audio) pattern0 */
+	u32 pll2_pat1;		/* 0x17c pll2 (audio) pattern1 */
+	u8 reserved_0x180[384];
+	u32 pll1_bias;		/* 0x300 pll1 (cpux) bias */
+	u8 reserved_0x304[12];
+	u32 pll5_bias;		/* 0x310 pll5 (ddr) bias */
+	u8 reserved_0x314[12];
+	u32 pll6_bias;		/* 0x320 pll6 (periph0) bias */
+	u8 reserved_0x324[4];
+	u32 pll_periph1_bias;	/* 0x328 pll periph1 bias */
+	u8 reserved_0x32c[4];
+	u32 pll7_bias;		/* 0x330 pll7 (gpu) bias */
+	u8 reserved_0x334[12];
+	u32 pll3_bias;		/* 0x340 pll3 (video0) bias */
+	u8 reserved_0x344[4];
+	u32 pll_video1_bias;	/* 0x348 pll video1 bias */
+	u8 reserved_0x34c[12];
+	u32 pll4_bias;		/* 0x358 pll4 (ve) bias */
+	u8 reserved_0x35c[4];
+	u32 pll10_bias;		/* 0x360 pll10 (de) bias */
+	u8 reserved_0x364[12];
+	u32 pll9_bias;		/* 0x370 pll9 (hsic) bias */
+	u8 reserved_0x374[4];
+	u32 pll2_bias;		/* 0x378 pll2 (audio) bias */
+	u8 reserved_0x37c[132];
+	u32 pll1_tun;		/* 0x400 pll1 (cpux) tunning */
+	u8 reserved_0x404[252];
+	u32 cpu_axi_cfg;	/* 0x500 CPUX/AXI clock control*/
+	u8 reserved_0x504[12];
+	u32 psi_ahb1_ahb2_cfg;	/* 0x510 PSI/AHB1/AHB2 clock control */
+	u8 reserved_0x514[8];
+	u32 ahb3_cfg;		/* 0x51c AHB3 clock control */
+	u32 apb1_cfg;		/* 0x520 APB1 clock control */
+	u32 apb2_cfg;		/* 0x524 APB2 clock control */
+	u8 reserved_0x528[24];
+	u32 mbus_cfg;		/* 0x540 MBUS clock control */
+	u8 reserved_0x544[188];
+	u32 de_clk_cfg;		/* 0x600 DE clock control */
+	u8 reserved_0x604[8];
+	u32 de_gate_reset;	/* 0x60c DE gate/reset control */
+	u8 reserved_0x610[16];
+	u32 di_clk_cfg;		/* 0x620 DI clock control */
+	u8 reserved_0x024[8];
+	u32 di_gate_reset;	/* 0x62c DI gate/reset control */
+	u8 reserved_0x630[64];
+	u32 gpu_clk_cfg;	/* 0x670 GPU clock control */
+	u8 reserved_0x674[8];
+	u32 gpu_gate_reset;	/* 0x67c GPU gate/reset control */
+	u32 ce_clk_cfg;		/* 0x680 CE clock control */
+	u8 reserved_0x684[8];
+	u32 ce_gate_reset;	/* 0x68c CE gate/reset control */
+	u32 ve_clk_cfg;		/* 0x690 VE clock control */
+	u8 reserved_0x694[8];
+	u32 ve_gate_reset;	/* 0x69c VE gate/reset control */
+	u8 reserved_0x6a0[16];
+	u32 emce_clk_cfg;	/* 0x6b0 EMCE clock control */
+	u8 reserved_0x6b4[8];
+	u32 emce_gate_reset;	/* 0x6bc EMCE gate/reset control */
+	u32 vp9_clk_cfg;	/* 0x6c0 VP9 clock control */
+	u8 reserved_0x6c4[8];
+	u32 vp9_gate_reset;	/* 0x6cc VP9 gate/reset control */
+	u8 reserved_0x6d0[60];
+	u32 dma_gate_reset;	/* 0x70c DMA gate/reset control */
+	u8 reserved_0x710[12];
+	u32 msgbox_gate_reset;	/* 0x71c Message Box gate/reset control */
+	u8 reserved_0x720[12];
+	u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */
+	u8 reserved_0x730[12];
+	u32 hstimer_gate_reset;	/* 0x73c HS Timer gate/reset control */
+	u32 avs_gate_reset;	/* 0x740 AVS gate/reset control */
+	u8 reserved_0x744[72];
+	u32 dbgsys_gate_reset;	/* 0x78c Debugging system gate/reset control */
+	u8 reserved_0x790[12];
+	u32 psi_gate_reset;	/* 0x79c PSI gate/reset control */
+	u8 reserved_0x7a0[12];
+	u32 pwm_gate_reset;	/* 0x7ac PWM gate/reset control */
+	u8 reserved_0x7b0[12];
+	u32 iommu_gate_reset;	/* 0x7bc IOMMU gate/reset control */
+	u8 reserved_0x7c0[64];
+	u32 dram_clk_cfg;		/* 0x800 DRAM clock control */
+	u32 mbus_gate;		/* 0x804 MBUS gate control */
+	u8 reserved_0x808[4];
+	u32 dram_gate_reset;	/* 0x80c DRAM gate/reset control */
+	u32 nand0_clk_cfg;	/* 0x810 NAND0 clock control */
+	u32 nand1_clk_cfg;	/* 0x814 NAND1 clock control */
+	u8 reserved_0x818[20];
+	u32 nand_gate_reset;	/* 0x82c NAND gate/reset control */
+	u32 sd0_clk_cfg;	/* 0x830 MMC0 clock control */
+	u32 sd1_clk_cfg;	/* 0x834 MMC1 clock control */
+	u32 sd2_clk_cfg;	/* 0x838 MMC2 clock control */
+	u8 reserved_0x83c[16];
+	u32 sd_gate_reset;	/* 0x84c MMC gate/reset control */
+	u8 reserved_0x850[188];
+	u32 uart_gate_reset;	/* 0x90c UART gate/reset control */
+	u8 reserved_0x910[12];
+	u32 twi_gate_reset;	/* 0x91c I2C gate/reset control */
+	u8 reserved_0x920[28];
+	u32 scr_gate_reset;	/* 0x93c SCR gate/reset control */
+	u32 spi0_clk_cfg;	/* 0x940 SPI0 clock control */
+	u32 spi1_clk_cfg;	/* 0x944 SPI1 clock control */
+	u8 reserved_0x948[36];
+	u32 spi_gate_reset;	/* 0x96c SPI gate/reset control */
+	u8 reserved_0x970[12];
+	u32 emac_gate_reset;	/* 0x97c EMAC gate/reset control */
+	u8 reserved_0x980[48];
+	u32 ts_clk_cfg;		/* 0x9b0 TS clock control */
+	u8 reserved_0x9b4[8];
+	u32 ts_gate_reset;	/* 0x9bc TS gate/reset control */
+	u32 irtx_clk_cfg;	/* 0x9c0 IR TX clock control */
+	u8 reserved_0x9c4[8];
+	u32 irtx_gate_reset;	/* 0x9cc IR TX gate/reset control */
+	u8 reserved_0x9d0[44];
+	u32 ths_gate_reset;	/* 0x9fc THS gate/reset control */
+	u8 reserved_0xa00[12];
+	u32 i2s3_clk_cfg;	/* 0xa0c I2S3 clock control */
+	u32 i2s0_clk_cfg;	/* 0xa10 I2S0 clock control */
+	u32 i2s1_clk_cfg;	/* 0xa14 I2S1 clock control */
+	u32 i2s2_clk_cfg;	/* 0xa18 I2S2 clock control */
+	u32 i2s_gate_reset;	/* 0xa1c I2S gate/reset control */
+	u32 spdif_clk_cfg;	/* 0xa20 SPDIF clock control */
+	u8 reserved_0xa24[8];
+	u32 spdif_gate_reset;	/* 0xa2c SPDIF gate/reset control */
+	u8 reserved_0xa30[16];
+	u32 dmic_clk_cfg;	/* 0xa40 DMIC clock control */
+	u8 reserved_0xa44[8];
+	u32 dmic_gate_reset;	/* 0xa4c DMIC gate/reset control */
+	u8 reserved_0xa50[16];
+	u32 ahub_clk_cfg;	/* 0xa60 Audio HUB clock control */
+	u8 reserved_0xa64[8];
+	u32 ahub_gate_reset;	/* 0xa6c Audio HUB gate/reset control */
+	u32 usb0_clk_cfg;	/* 0xa70 USB0(OTG) clock control */
+	u32 usb1_clk_cfg;	/* 0xa74 USB1(XHCI) clock control */
+	u8 reserved_0xa78[4];
+	u32 usb3_clk_cfg;	/* 0xa78 USB3 clock control */
+	u8 reserved_0xa80[12];
+	u32 usb_gate_reset;	/* 0xa8c USB gate/reset control */
+	u8 reserved_0xa90[32];
+	u32 pcie_ref_clk_cfg;	/* 0xab0 PCIE REF clock control */
+	u32 pcie_axi_clk_cfg;	/* 0xab4 PCIE AXI clock control */
+	u32 pcie_aux_clk_cfg;	/* 0xab8 PCIE AUX clock control */
+	u32 pcie_gate_reset;	/* 0xabc PCIE gate/reset control */
+	u8 reserved_0xac0[64];
+	u32 hdmi_clk_cfg;	/* 0xb00 HDMI clock control */
+	u32 hdmi_slow_clk_cfg;	/* 0xb04 HDMI slow clock control */
+	u8 reserved_0xb08[8];
+	u32 hdmi_cec_clk_cfg;	/* 0xb10 HDMI CEC clock control */
+	u8 reserved_0xb14[8];
+	u32 hdmi_gate_reset;	/* 0xb1c HDMI gate/reset control */
+	u8 reserved_0xb20[60];
+	u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */
+	u32 tcon_lcd0_clk_cfg;	/* 0xb60 TCON LCD0 clock control */
+	u8 reserved_0xb64[24];
+	u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */
+	u32 tcon_tv0_clk_cfg;	/* 0xb80 TCON TV0 clock control */
+	u8 reserved_0xb84[24];
+	u32 tcon_tv_gate_reset;	/* 0xb9c TCON TV gate/reset control */
+	u8 reserved_0xba0[96];
+	u32 csi_misc_clk_cfg;	/* 0xc00 CSI MISC clock control */
+	u32 csi_top_clk_cfg;	/* 0xc04 CSI TOP clock control */
+	u32 csi_mclk_cfg;	/* 0xc08 CSI Master clock control */
+	u8 reserved_0xc0c[32];
+	u32 csi_gate_reset;	/* 0xc2c CSI gate/reset control */
+	u8 reserved_0xc30[16];
+	u32 hdcp_clk_cfg;	/* 0xc40 HDCP clock control */
+	u8 reserved_0xc44[8];
+	u32 hdcp_gate_reset;	/* 0xc4c HDCP gate/reset control */
+	u8 reserved_0xc50[688];
+	u32 ccu_sec_switch;	/* 0xf00 CCU security switch */
+	u32 pll_lock_dbg_ctrl;	/* 0xf04 PLL lock debugging control */
+};
+
+/* pll1 bit field */
+#define CCM_PLL1_CTRL_EN		BIT(31)
+#define CCM_PLL1_LOCK_EN		BIT(29)
+#define CCM_PLL1_LOCK			BIT(28)
+#define CCM_PLL1_CLOCK_TIME_2		(2 << 24)
+#define CCM_PLL1_CTRL_P(p)		((p) << 16)
+#define CCM_PLL1_CTRL_N(n)		((n) << 8)
+
+/* pll5 bit field */
+#define CCM_PLL5_CTRL_EN		BIT(31)
+#define CCM_PLL5_LOCK_EN		BIT(29)
+#define CCM_PLL5_LOCK			BIT(28)
+#define CCM_PLL5_CTRL_N(n)		((n) << 8)
+#define CCM_PLL5_CTRL_DIV1(div1)	((div1) << 0)
+#define CCM_PLL5_CTRL_DIV2(div0)	((div0) << 1)
+
+/* pll6 bit field */
+#define CCM_PLL6_CTRL_EN		BIT(31)
+#define CCM_PLL6_LOCK_EN		BIT(29)
+#define CCM_PLL6_LOCK			BIT(28)
+#define CCM_PLL6_CTRL_N_SHIFT		8
+#define CCM_PLL6_CTRL_N_MASK		(0xff << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_DIV1_SHIFT	0
+#define CCM_PLL6_CTRL_DIV1_MASK		(0x1 << CCM_PLL6_CTRL_DIV1_SHIFT)
+#define CCM_PLL6_CTRL_DIV2_SHIFT	1
+#define CCM_PLL6_CTRL_DIV2_MASK		(0x1 << CCM_PLL6_CTRL_DIV2_SHIFT)
+#define CCM_PLL6_DEFAULT		0xa0006300
+
+/* cpu_axi bit field*/
+#define CCM_CPU_AXI_MUX_MASK		(0x3 << 24)
+#define CCM_CPU_AXI_MUX_OSC24M		(0x0 << 24)
+#define CCM_CPU_AXI_MUX_PLL_CPUX	(0x3 << 24)
+#define CCM_CPU_AXI_APB_MASK		0x300
+#define CCM_CPU_AXI_AXI_MASK		0x3
+#define CCM_CPU_AXI_DEFAULT_FACTORS	0x301
+
+/* psi_ahb1_ahb2 bit field */
+#define CCM_PSI_AHB1_AHB2_DEFAULT	0x03000102
+
+/* ahb3 bit field */
+#define CCM_AHB3_DEFAULT		0x03000002
+
+/* apb1 bit field */
+#define CCM_APB1_DEFAULT		0x03000102
+
+/* apb2 bit field */
+#define APB2_CLK_SRC_OSC24M		(0x0 << 24)
+#define APB2_CLK_SRC_OSC32K		(0x1 << 24)
+#define APB2_CLK_SRC_PSI		(0x2 << 24)
+#define APB2_CLK_SRC_PLL6		(0x3 << 24)
+#define APB2_CLK_SRC_MASK		(0x3 << 24)
+#define APB2_CLK_RATE_N_1		(0x0 << 8)
+#define APB2_CLK_RATE_N_2		(0x1 << 8)
+#define APB2_CLK_RATE_N_4		(0x2 << 8)
+#define APB2_CLK_RATE_N_8		(0x3 << 8)
+#define APB2_CLK_RATE_N_MASK		(3 << 8)
+#define APB2_CLK_RATE_M(m)		(((m)-1) << 0)
+#define APB2_CLK_RATE_M_MASK            (3 << 0)
+
+/* MBUS clock bit field */
+#define MBUS_ENABLE			BIT(31)
+#define MBUS_RESET			BIT(30)
+#define MBUS_CLK_SRC_MASK		GENMASK(25, 24)
+#define MBUS_CLK_SRC_OSCM24		(0 << 24)
+#define MBUS_CLK_SRC_PLL6X2		(1 << 24)
+#define MBUS_CLK_SRC_PLL5		(2 << 24)
+#define MBUS_CLK_SRC_PLL6X4		(3 << 24)
+#define MBUS_CLK_M(m)			(((m)-1) << 0)
+
+/* Module gate/reset shift*/
+#define RESET_SHIFT			(16)
+
+/* DRAM clock bit field */
+#define DRAM_MOD_RESET			BIT(30)
+#define DRAM_CLK_UPDATE			BIT(27)
+#define DRAM_CLK_SRC_MASK		GENMASK(25, 24)
+#define DRAM_CLK_SRC_PLL5		(0 << 24)
+#define DRAM_CLK_M(m)			(((m)-1) << 0)
+
+/* MMC clock bit field */
+#define CCM_MMC_CTRL_M(x)		((x) - 1)
+#define CCM_MMC_CTRL_N(x)		((x) << 8)
+#define CCM_MMC_CTRL_OSCM24		(0x0 << 24)
+#define CCM_MMC_CTRL_PLL6X2		(0x1 << 24)
+#define CCM_MMC_CTRL_PLL_PERIPH2X2	(0x2 << 24)
+#define CCM_MMC_CTRL_ENABLE		(0x1 << 31)
+/* H6 doesn't have these delays */
+#define CCM_MMC_CTRL_OCLK_DLY(a)	((void) (a), 0)
+#define CCM_MMC_CTRL_SCLK_DLY(a)	((void) (a), 0)
+
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+unsigned int clock_get_pll6(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_SUN50I_H6_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
new file mode 100644
index 0000000..ee38712
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -0,0 +1,533 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * sun6i clock register definitions
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#ifndef _SUNXI_CLOCK_SUN6I_H
+#define _SUNXI_CLOCK_SUN6I_H
+
+struct sunxi_ccm_reg {
+	u32 pll1_cfg;		/* 0x00 pll1 control */
+	u32 reserved0;
+	u32 pll2_cfg;		/* 0x08 pll2 control */
+	u32 reserved1;
+	u32 pll3_cfg;		/* 0x10 pll3 control */
+	u32 reserved2;
+	u32 pll4_cfg;		/* 0x18 pll4 control */
+	u32 reserved3;
+	u32 pll5_cfg;		/* 0x20 pll5 control */
+	u32 reserved4;
+	u32 pll6_cfg;		/* 0x28 pll6 control */
+	u32 reserved5;
+	u32 pll7_cfg;		/* 0x30 pll7 control */
+	u32 sata_pll_cfg;	/* 0x34 SATA pll control (R40 only) */
+	u32 pll8_cfg;		/* 0x38 pll8 control */
+	u32 reserved7;
+	u32 mipi_pll_cfg;	/* 0x40 MIPI pll control */
+	u32 pll9_cfg;		/* 0x44 pll9 control */
+	u32 pll10_cfg;		/* 0x48 pll10 control */
+	u32 pll11_cfg;		/* 0x4c pll11 (ddr1) control (A33 only) */
+	u32 cpu_axi_cfg;	/* 0x50 CPU/AXI divide ratio */
+	u32 ahb1_apb1_div;	/* 0x54 AHB1/APB1 divide ratio */
+	u32 apb2_div;		/* 0x58 APB2 divide ratio */
+	u32 axi_gate;		/* 0x5c axi module clock gating */
+	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
+	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
+	u32 apb1_gate;		/* 0x68 apb1 module clock gating */
+	u32 apb2_gate;		/* 0x6c apb2 module clock gating */
+	u32 bus_gate4;          /* 0x70 gate 4 module clock gating */
+	u8 res3[0xc];
+	u32 nand0_clk_cfg;	/* 0x80 nand0 clock control */
+	u32 nand1_clk_cfg;	/* 0x84 nand1 clock control */
+	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
+	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
+	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
+	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
+	u32 ts_clk_cfg;		/* 0x98 transport stream clock control */
+	u32 ss_clk_cfg;		/* 0x9c security system clock control */
+	u32 spi0_clk_cfg;	/* 0xa0 spi0 clock control */
+	u32 spi1_clk_cfg;	/* 0xa4 spi1 clock control */
+	u32 spi2_clk_cfg;	/* 0xa8 spi2 clock control */
+	u32 spi3_clk_cfg;	/* 0xac spi3 clock control */
+	u32 i2s0_clk_cfg;	/* 0xb0 I2S0 clock control*/
+	u32 i2s1_clk_cfg;	/* 0xb4 I2S1 clock control */
+	u32 reserved10[2];
+	u32 spdif_clk_cfg;	/* 0xc0 SPDIF clock control */
+	u32 reserved11;
+	u32 sata_clk_cfg;	/* 0xc8 SATA clock control (R40 only) */
+	u32 usb_clk_cfg;	/* 0xcc USB clock control */
+#ifdef CONFIG_MACH_SUN8I_R40
+	u32 cir0_clk_cfg;	/* 0xd0 CIR0 clock control (R40 only) */
+#else
+	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control (not for R40) */
+#endif
+	u32 reserved12[7];
+	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
+	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
+	u32 dram_pll_cfg;	/* 0xf8 PLL_DDR cfg register, A33 only */
+	u32 mbus_reset;		/* 0xfc MBUS reset control, A33 only */
+	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
+#ifdef CONFIG_SUNXI_DE2
+	u32 de_clk_cfg;		/* 0x104 DE module clock */
+#else
+	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
+#endif
+	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
+	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
+	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
+	u32 mp_clk_cfg;		/* 0x114 MP module clock */
+#ifdef CONFIG_SUNXI_DE2
+	u32 lcd0_clk_cfg;	/* 0x118 LCD0 module clock */
+	u32 lcd1_clk_cfg;	/* 0x11c LCD1 module clock */
+#else
+	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
+	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
+#endif
+	u32 tve_clk_cfg;	/* 0x120 H3/H5 TVE module clock */
+	u32 reserved14[2];
+	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
+	u32 lcd1_ch1_clk_cfg;	/* 0x130 LCD1 CH1 module clock */
+	u32 csi0_clk_cfg;	/* 0x134 CSI0 module clock */
+	u32 csi1_clk_cfg;	/* 0x138 CSI1 module clock */
+	u32 ve_clk_cfg;		/* 0x13c VE module clock */
+	u32 adda_clk_cfg;	/* 0x140 ADDA module clock */
+	u32 avs_clk_cfg;	/* 0x144 AVS module clock */
+	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
+	u32 reserved15;
+	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
+#ifdef CONFIG_SUNXI_DE2
+	u32 hdmi_slow_clk_cfg;	/* 0x154 HDMI slow module clock */
+#else
+	u32 ps_clk_cfg;		/* 0x154 PS module clock */
+#endif
+	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
+	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
+	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
+#ifdef CONFIG_MACH_SUN8I_R40
+	u32 gmac_clk_cfg;	/* 0x164 GMAC clock control (R40 only) */
+#else
+	u32 reserved16;
+#endif
+	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
+	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
+	u32 reserved17[4];
+	u32 iep_drc0_clk_cfg;	/* 0x180 IEP DRC0 module clock */
+	u32 iep_drc1_clk_cfg;	/* 0x184 IEP DRC1 module clock */
+	u32 iep_deu0_clk_cfg;	/* 0x188 IEP DEU0 module clock */
+	u32 iep_deu1_clk_cfg;	/* 0x18c IEP DEU1 module clock */
+	u32 reserved18[4];
+	u32 gpu_core_clk_cfg;	/* 0x1a0 GPU core clock config */
+	u32 gpu_mem_clk_cfg;	/* 0x1a4 GPU memory clock config */
+	u32 gpu_hyd_clk_cfg;	/* 0x1a0 GPU HYD clock config */
+	u32 reserved19[21];
+	u32 pll_lock;		/* 0x200 PLL Lock Time */
+	u32 pll1_lock;		/* 0x204 PLL1 Lock Time */
+	u32 reserved20[6];
+	u32 pll1_bias_cfg;	/* 0x220 PLL1 Bias config */
+	u32 pll2_bias_cfg;	/* 0x224 PLL2 Bias config */
+	u32 pll3_bias_cfg;	/* 0x228 PLL3 Bias config */
+	u32 pll4_bias_cfg;	/* 0x22c PLL4 Bias config */
+	u32 pll5_bias_cfg;	/* 0x230 PLL5 Bias config */
+	u32 pll6_bias_cfg;	/* 0x234 PLL6 Bias config */
+	u32 pll7_bias_cfg;	/* 0x238 PLL7 Bias config */
+	u32 pll8_bias_cfg;	/* 0x23c PLL8 Bias config */
+	u32 mipi_bias_cfg;	/* 0x240 MIPI Bias config */
+	u32 pll9_bias_cfg;	/* 0x244 PLL9 Bias config */
+	u32 pll10_bias_cfg;	/* 0x248 PLL10 Bias config */
+	u32 reserved21[5];
+	u32 pll5_tuning_cfg;	/* 0x260 PLL5 Tuning config */
+	u32 reserved21_5[7];
+	u32 pll1_pattern_cfg;	/* 0x280 PLL1 Pattern config */
+	u32 pll2_pattern_cfg;	/* 0x284 PLL2 Pattern config */
+	u32 pll3_pattern_cfg;	/* 0x288 PLL3 Pattern config */
+	u32 pll4_pattern_cfg;	/* 0x28c PLL4 Pattern config */
+	u32 pll5_pattern_cfg;	/* 0x290 PLL5 Pattern config */
+	u32 pll6_pattern_cfg;	/* 0x294 PLL6 Pattern config */
+	u32 pll7_pattern_cfg;	/* 0x298 PLL7 Pattern config */
+	u32 pll8_pattern_cfg;	/* 0x29c PLL8 Pattern config */
+	u32 mipi_pattern_cfg;	/* 0x2a0 MIPI Pattern config */
+	u32 pll9_pattern_cfg;	/* 0x2a4 PLL9 Pattern config */
+	u32 pll10_pattern_cfg;	/* 0x2a8 PLL10 Pattern config */
+	u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */
+	u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */
+	u32 reserved22[3];
+	u32 ahb_reset0_cfg;	/* 0x2c0 AHB1 Reset 0 config */
+	u32 ahb_reset1_cfg;	/* 0x2c4 AHB1 Reset 1 config */
+	u32 ahb_reset2_cfg;	/* 0x2c8 AHB1 Reset 2 config */
+	u32 reserved23;
+	u32 apb1_reset_cfg;	/* 0x2d0 APB1 Reset config */
+	u32 reserved24;
+	u32 apb2_reset_cfg;	/* 0x2d8 APB2 Reset config */
+	u32 reserved25[5];
+	u32 ccu_sec_switch;	/* 0x2f0 CCU Security Switch, H3 only */
+	u32 reserved26[11];
+	u32 pll_lock_ctrl;	/* 0x320 PLL lock control, R40 only */
+};
+
+/* apb2 bit field */
+#define APB2_CLK_SRC_LOSC		(0x0 << 24)
+#define APB2_CLK_SRC_OSC24M		(0x1 << 24)
+#define APB2_CLK_SRC_PLL6		(0x2 << 24)
+#define APB2_CLK_SRC_MASK		(0x3 << 24)
+#define APB2_CLK_RATE_N_1		(0x0 << 16)
+#define APB2_CLK_RATE_N_2		(0x1 << 16)
+#define APB2_CLK_RATE_N_4		(0x2 << 16)
+#define APB2_CLK_RATE_N_8		(0x3 << 16)
+#define APB2_CLK_RATE_N_MASK		(3 << 16)
+#define APB2_CLK_RATE_M(m)		(((m)-1) << 0)
+#define APB2_CLK_RATE_M_MASK            (0x1f << 0)
+
+/* apb2 gate field */
+#define APB2_GATE_UART_SHIFT	(16)
+#define APB2_GATE_UART_MASK		(0xff << APB2_GATE_UART_SHIFT)
+#define APB2_GATE_TWI_SHIFT	(0)
+#define APB2_GATE_TWI_MASK		(0xf << APB2_GATE_TWI_SHIFT)
+
+/* cpu_axi_cfg bits */
+#define AXI_DIV_SHIFT			0
+#define ATB_DIV_SHIFT			8
+#define CPU_CLK_SRC_SHIFT		16
+
+#define AXI_DIV_1			0
+#define AXI_DIV_2			1
+#define AXI_DIV_3			2
+#define AXI_DIV_4			3
+#define ATB_DIV_1			0
+#define ATB_DIV_2			1
+#define ATB_DIV_4			2
+#define AHB_DIV_1			0
+#define CPU_CLK_SRC_OSC24M		1
+#define CPU_CLK_SRC_PLL1		2
+
+#define CCM_PLL1_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
+#define CCM_PLL1_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
+#define CCM_PLL1_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
+#define CCM_PLL1_CTRL_P(n)		(((n) & 0x3) << 16)
+#define CCM_PLL1_CTRL_EN		(0x1 << 31)
+
+#define CCM_PLL3_CTRL_M_SHIFT		0
+#define CCM_PLL3_CTRL_M_MASK		(0xf << CCM_PLL3_CTRL_M_SHIFT)
+#define CCM_PLL3_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_PLL3_CTRL_N_SHIFT		8
+#define CCM_PLL3_CTRL_N_MASK		(0x7f << CCM_PLL3_CTRL_N_SHIFT)
+#define CCM_PLL3_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
+#define CCM_PLL3_CTRL_INTEGER_MODE	(0x1 << 24)
+#define CCM_PLL3_CTRL_LOCK		(0x1 << 28)
+#define CCM_PLL3_CTRL_EN		(0x1 << 31)
+
+#define CCM_PLL5_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
+#define CCM_PLL5_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
+#define CCM_PLL5_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
+#define CCM_PLL5_CTRL_UPD		(0x1 << 20)
+#define CCM_PLL5_CTRL_SIGMA_DELTA_EN	(0x1 << 24)
+#define CCM_PLL5_CTRL_EN		(0x1 << 31)
+
+#define PLL6_CFG_DEFAULT		0x90041811 /* 600 MHz */
+
+#define CCM_PLL6_CTRL_N_SHIFT		8
+#define CCM_PLL6_CTRL_N_MASK		(0x1f << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_K_SHIFT		4
+#define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL6_CTRL_LOCK		(1 << 28)
+
+#define CCM_SATA_PLL_DEFAULT		0x90005811 /* 100 MHz */
+
+#define CCM_MIPI_PLL_CTRL_M_SHIFT	0
+#define CCM_MIPI_PLL_CTRL_M_MASK	(0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)
+#define CCM_MIPI_PLL_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_MIPI_PLL_CTRL_K_SHIFT	4
+#define CCM_MIPI_PLL_CTRL_K_MASK	(0x3 << CCM_MIPI_PLL_CTRL_K_SHIFT)
+#define CCM_MIPI_PLL_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
+#define CCM_MIPI_PLL_CTRL_N_SHIFT	8
+#define CCM_MIPI_PLL_CTRL_N_MASK	(0xf << CCM_MIPI_PLL_CTRL_N_SHIFT)
+#define CCM_MIPI_PLL_CTRL_N(n)		((((n) - 1) & 0xf) << 8)
+#define CCM_MIPI_PLL_CTRL_LDO_EN	(0x3 << 22)
+#define CCM_MIPI_PLL_CTRL_EN		(0x1 << 31)
+
+#define CCM_PLL10_CTRL_M_SHIFT		0
+#define CCM_PLL10_CTRL_M_MASK		(0xf << CCM_PLL10_CTRL_M_SHIFT)
+#define CCM_PLL10_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_PLL10_CTRL_N_SHIFT		8
+#define CCM_PLL10_CTRL_N_MASK		(0x7f << CCM_PLL10_CTRL_N_SHIFT)
+#define CCM_PLL10_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
+#define CCM_PLL10_CTRL_INTEGER_MODE	(0x1 << 24)
+#define CCM_PLL10_CTRL_LOCK		(0x1 << 28)
+#define CCM_PLL10_CTRL_EN		(0x1 << 31)
+
+#define CCM_PLL11_CTRL_N(n)		((((n) - 1) & 0x3f) << 8)
+#define CCM_PLL11_CTRL_SIGMA_DELTA_EN	(0x1 << 24)
+#define CCM_PLL11_CTRL_UPD		(0x1 << 30)
+#define CCM_PLL11_CTRL_EN		(0x1 << 31)
+
+#define CCM_PLL5_TUN_LOCK_TIME(x)	(((x) & 0x7) << 24)
+#define CCM_PLL5_TUN_LOCK_TIME_MASK	CCM_PLL5_TUN_LOCK_TIME(0x7)
+#define CCM_PLL5_TUN_INIT_FREQ(x)	(((x) & 0x7f) << 16)
+#define CCM_PLL5_TUN_INIT_FREQ_MASK	CCM_PLL5_TUN_INIT_FREQ(0x7f)
+
+#if defined(CONFIG_MACH_SUN50I)
+/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
+#define AHB1_ABP1_DIV_DEFAULT		0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
+#else
+#define AHB1_ABP1_DIV_DEFAULT		0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
+#endif
+
+#define AXI_GATE_OFFSET_DRAM		0
+
+/* ahb_gate0 offsets */
+#ifdef CONFIG_MACH_SUNXI_H3_H5
+/*
+ * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
+ * them 0 - 2 like they were called on older SoCs.
+ */
+#define AHB_GATE_OFFSET_USB_OHCI3	31
+#define AHB_GATE_OFFSET_USB_OHCI2	30
+#define AHB_GATE_OFFSET_USB_OHCI1	29
+#define AHB_GATE_OFFSET_USB_OHCI0	28
+#define AHB_GATE_OFFSET_USB_EHCI3	27
+#define AHB_GATE_OFFSET_USB_EHCI2	26
+#define AHB_GATE_OFFSET_USB_EHCI1	25
+#define AHB_GATE_OFFSET_USB_EHCI0	24
+#elif defined(CONFIG_MACH_SUN50I)
+#define AHB_GATE_OFFSET_USB_OHCI0	28
+#define AHB_GATE_OFFSET_USB_OHCI1	29
+#define AHB_GATE_OFFSET_USB_EHCI0	24
+#define AHB_GATE_OFFSET_USB_EHCI1	25
+#else
+#define AHB_GATE_OFFSET_USB_OHCI1	30
+#define AHB_GATE_OFFSET_USB_OHCI0	29
+#define AHB_GATE_OFFSET_USB_EHCI1	27
+#define AHB_GATE_OFFSET_USB_EHCI0	26
+#endif
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNXI_H3_H5)
+#define AHB_GATE_OFFSET_USB0		23
+#elif !defined(CONFIG_MACH_SUN8I_R40)
+#define AHB_GATE_OFFSET_USB0		24
+#else
+#define AHB_GATE_OFFSET_USB0		25
+#define AHB_GATE_OFFSET_SATA		24
+#endif
+#define AHB_GATE_OFFSET_MCTL		14
+#define AHB_GATE_OFFSET_GMAC		17
+#define AHB_GATE_OFFSET_NAND0		13
+#define AHB_GATE_OFFSET_NAND1		12
+#define AHB_GATE_OFFSET_MMC3		11
+#define AHB_GATE_OFFSET_MMC2		10
+#define AHB_GATE_OFFSET_MMC1		9
+#define AHB_GATE_OFFSET_MMC0		8
+#define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_DMA		6
+#define AHB_GATE_OFFSET_SS		5
+
+/* ahb_gate1 offsets */
+#define AHB_GATE_OFFSET_DRC0		25
+#define AHB_GATE_OFFSET_DE_FE0		14
+#define AHB_GATE_OFFSET_DE_BE0		12
+#define AHB_GATE_OFFSET_DE		12
+#define AHB_GATE_OFFSET_HDMI		11
+#define AHB_GATE_OFFSET_TVE		9
+#ifndef CONFIG_SUNXI_DE2
+#define AHB_GATE_OFFSET_LCD1		5
+#define AHB_GATE_OFFSET_LCD0		4
+#else
+#define AHB_GATE_OFFSET_LCD1		4
+#define AHB_GATE_OFFSET_LCD0		3
+#endif
+
+#define CCM_NAND_CTRL_M(x)		((x) - 1)
+#define CCM_NAND_CTRL_N(x)		((x) << 16)
+#define CCM_NAND_CTRL_PLL6		(0x1 << 24)
+#define CCM_NAND_CTRL_ENABLE		(0x1 << 31)
+
+#define CCM_MMC_CTRL_M(x)		((x) - 1)
+#define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
+#define CCM_MMC_CTRL_N(x)		((x) << 16)
+#define CCM_MMC_CTRL_SCLK_DLY(x)	((x) << 20)
+#define CCM_MMC_CTRL_OSCM24		(0x0 << 24)
+#define CCM_MMC_CTRL_PLL6		(0x1 << 24)
+#define CCM_MMC_CTRL_ENABLE		(0x1 << 31)
+
+#define CCM_SATA_CTRL_ENABLE		(0x1 << 31)
+#define CCM_SATA_CTRL_USE_EXTCLK	(0x1 << 24)
+
+#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
+#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_PHY3_RST (0x1 << 3)
+/* There is no global phy clk gate on sun6i, define as 0 */
+#define CCM_USB_CTRL_PHYGATE 0
+#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
+#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
+#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
+#ifdef CONFIG_MACH_SUNXI_H3_H5
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19)
+#else
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#endif
+
+#define CCM_GMAC_CTRL_TX_CLK_SRC_MII	0x0
+#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
+#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
+#define CCM_GMAC_CTRL_GPIT_MII		(0x0 << 2)
+#define CCM_GMAC_CTRL_GPIT_RGMII	(0x1 << 2)
+#define CCM_GMAC_CTRL_RX_CLK_DELAY(x)	((x) << 5)
+#define CCM_GMAC_CTRL_TX_CLK_DELAY(x)	((x) << 10)
+
+#define MDFS_CLK_DEFAULT		0x81000002 /* PLL6 / 3 */
+
+#define CCM_DRAMCLK_CFG_DIV(x)		((x - 1) << 0)
+#define CCM_DRAMCLK_CFG_DIV_MASK	(0xf << 0)
+#define CCM_DRAMCLK_CFG_DIV0(x)		((x - 1) << 8)
+#define CCM_DRAMCLK_CFG_DIV0_MASK	(0xf << 8)
+#define CCM_DRAMCLK_CFG_SRC_PLL5	(0x0 << 20)
+#define CCM_DRAMCLK_CFG_SRC_PLL6x2	(0x1 << 20)
+#define CCM_DRAMCLK_CFG_SRC_PLL11	(0x1 << 20) /* A64 only */
+#define CCM_DRAMCLK_CFG_SRC_MASK	(0x3 << 20)
+#define CCM_DRAMCLK_CFG_UPD		(0x1 << 16)
+#define CCM_DRAMCLK_CFG_RST		(0x1 << 31)
+
+#define CCM_DRAMPLL_CFG_SRC_PLL5	(0x0 << 16) /* Select PLL5 (DDR0) */
+#define CCM_DRAMPLL_CFG_SRC_PLL11	(0x1 << 16) /* Select PLL11 (DDR1) */
+#define CCM_DRAMPLL_CFG_SRC_MASK	(0x1 << 16)
+
+#define CCM_MBUS_RESET_RESET		(0x1 << 31)
+
+#define CCM_DRAM_GATE_OFFSET_DE_FE0	24
+#define CCM_DRAM_GATE_OFFSET_DE_FE1	25
+#define CCM_DRAM_GATE_OFFSET_DE_BE0	26
+#define CCM_DRAM_GATE_OFFSET_DE_BE1	27
+
+#define CCM_LCD_CH0_CTRL_PLL3		(0 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7		(1 << 24)
+#define CCM_LCD_CH0_CTRL_PLL3_2X	(2 << 24)
+#define CCM_LCD_CH0_CTRL_PLL7_2X	(3 << 24)
+#define CCM_LCD_CH0_CTRL_MIPI_PLL	(4 << 24)
+/* No reset bit in ch0_clk_cfg (reset is controlled through ahb_reset1) */
+#define CCM_LCD_CH0_CTRL_RST		0
+#define CCM_LCD_CH0_CTRL_GATE		(0x1 << 31)
+
+#define CCM_LCD_CH1_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_LCD_CH1_CTRL_HALF_SCLK1	0 /* no seperate sclk1 & 2 on sun6i */
+#define CCM_LCD_CH1_CTRL_PLL3		(0 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7		(1 << 24)
+#define CCM_LCD_CH1_CTRL_PLL3_2X	(2 << 24)
+#define CCM_LCD_CH1_CTRL_PLL7_2X	(3 << 24)
+#define CCM_LCD_CH1_CTRL_GATE		(0x1 << 31)
+
+#define CCM_LCD0_CTRL_GATE		(0x1 << 31)
+#define CCM_LCD0_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+
+#define CCM_LCD1_CTRL_GATE		(0x1 << 31)
+#define CCM_LCD1_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+
+#define CCM_HDMI_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_HDMI_CTRL_PLL_MASK		(3 << 24)
+#define CCM_HDMI_CTRL_PLL3		(0 << 24)
+#define CCM_HDMI_CTRL_PLL7		(1 << 24)
+#define CCM_HDMI_CTRL_PLL3_2X		(2 << 24)
+#define CCM_HDMI_CTRL_PLL7_2X		(3 << 24)
+#define CCM_HDMI_CTRL_DDC_GATE		(0x1 << 30)
+#define CCM_HDMI_CTRL_GATE		(0x1 << 31)
+
+#define CCM_HDMI_SLOW_CTRL_DDC_GATE	(1 << 31)
+
+#define CCM_TVE_CTRL_GATE		(0x1 << 31)
+#define CCM_TVE_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+
+#if defined(CONFIG_MACH_SUN50I)
+#define MBUS_CLK_DEFAULT		0x81000002 /* PLL6x2 / 3 */
+#elif defined(CONFIG_MACH_SUN8I)
+#define MBUS_CLK_DEFAULT		0x81000003 /* PLL6 / 4 */
+#else
+#define MBUS_CLK_DEFAULT		0x81000001 /* PLL6 / 2 */
+#endif
+#define MBUS_CLK_GATE			(0x1 << 31)
+
+#define CCM_PLL5_PATTERN		0xd1303333
+#define CCM_PLL11_PATTERN		0xf5860000
+
+/* ahb_reset0 offsets */
+#ifdef CONFIG_MACH_SUN8I_R40
+#define AHB_RESET_OFFSET_SATA		24
+#endif
+#define AHB_RESET_OFFSET_GMAC		17
+#define AHB_RESET_OFFSET_MCTL		14
+#define AHB_RESET_OFFSET_MMC3		11
+#define AHB_RESET_OFFSET_MMC2		10
+#define AHB_RESET_OFFSET_MMC1		9
+#define AHB_RESET_OFFSET_MMC0		8
+#define AHB_RESET_OFFSET_MMC(n)		(AHB_RESET_OFFSET_MMC0 + (n))
+#define AHB_RESET_OFFSET_SS		5
+
+/* ahb_reset1 offsets */
+#define AHB_RESET_OFFSET_SAT		26
+#define AHB_RESET_OFFSET_DRC0		25
+#define AHB_RESET_OFFSET_DE_FE0		14
+#define AHB_RESET_OFFSET_DE_BE0		12
+#define AHB_RESET_OFFSET_DE		12
+#define AHB_RESET_OFFSET_HDMI		11
+#define AHB_RESET_OFFSET_HDMI2		10
+#define AHB_RESET_OFFSET_TVE		9
+#ifndef CONFIG_SUNXI_DE2
+#define AHB_RESET_OFFSET_LCD1		5
+#define AHB_RESET_OFFSET_LCD0		4
+#else
+#define AHB_RESET_OFFSET_LCD1		4
+#define AHB_RESET_OFFSET_LCD0		3
+#endif
+
+/* ahb_reset2 offsets */
+#define AHB_RESET_OFFSET_EPHY		2
+#define AHB_RESET_OFFSET_LVDS		0
+
+/* apb2 reset */
+#define APB2_RESET_UART_SHIFT		(16)
+#define APB2_RESET_UART_MASK		(0xff << APB2_RESET_UART_SHIFT)
+#define APB2_RESET_TWI_SHIFT		(0)
+#define APB2_RESET_TWI_MASK		(0xf << APB2_RESET_TWI_SHIFT)
+
+/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
+#define CCM_DE_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_DE_CTRL_PLL_MASK		(0xf << 24)
+#define CCM_DE_CTRL_PLL3		(0 << 24)
+#define CCM_DE_CTRL_PLL7		(1 << 24)
+#define CCM_DE_CTRL_PLL6_2X		(2 << 24)
+#define CCM_DE_CTRL_PLL8		(3 << 24)
+#define CCM_DE_CTRL_PLL9		(4 << 24)
+#define CCM_DE_CTRL_PLL10		(5 << 24)
+#define CCM_DE_CTRL_GATE		(1 << 31)
+
+/* CCM bits common to all Display Engine 2.0 clock ctrl regs */
+#define CCM_DE2_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_DE2_CTRL_PLL_MASK		(3 << 24)
+#define CCM_DE2_CTRL_PLL6_2X		(0 << 24)
+#define CCM_DE2_CTRL_PLL10		(1 << 24)
+#define CCM_DE2_CTRL_GATE		(0x1 << 31)
+
+/* CCU security switch, H3 only */
+#define CCM_SEC_SWITCH_MBUS_NONSEC	(1 << 2)
+#define CCM_SEC_SWITCH_BUS_NONSEC	(1 << 1)
+#define CCM_SEC_SWITCH_PLL_NONSEC	(1 << 0)
+
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
+void clock_set_pll3_factors(int m, int n);
+void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
+void clock_set_pll10(unsigned int hz);
+void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
+void clock_set_mipi_pll(unsigned int hz);
+unsigned int clock_get_pll3(void);
+unsigned int clock_get_pll6(void);
+unsigned int clock_get_mipi_pll(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_SUN6I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
new file mode 100644
index 0000000..14df3cc
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * sun8i a83t clock register definitions
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * from sun6i.h
+ */
+
+#ifndef _SUNXI_CLOCK_SUN8I_A83T_H
+#define _SUNXI_CLOCK_SUN8I_A83T_H
+
+struct sunxi_ccm_reg {
+	u32 pll1_c0_cfg;	/* 0x00 c1cpu# pll control */
+	u32 pll1_c1_cfg;	/* 0x04 c1cpu# pll control */
+	u32 pll2_cfg;		/* 0x08 pll2 audio control */
+	u32 reserved1;
+	u32 pll3_cfg;		/* 0x10 pll3 video0 control */
+	u32 reserved2;
+	u32 pll4_cfg;		/* 0x18 pll4 ve control */
+	u32 reserved3;
+	u32 pll5_cfg;		/* 0x20 pll5 ddr control */
+	u32 reserved4;
+	u32 pll6_cfg;		/* 0x28 pll6 peripheral control */
+	u32 reserved5[3];	/* 0x2c */
+	u32 pll7_cfg;		/* 0x38 pll7 gpu control */
+	u32 reserved6[2];	/* 0x3c */
+	u32 pll8_cfg;		/* 0x44 pll8 hsic control */
+	u32 pll9_cfg;		/* 0x48 pll9 de control */
+	u32 pll10_cfg;		/* 0x4c pll10 video1 control */
+	u32 cpu_axi_cfg;	/* 0x50 CPU/AXI divide ratio */
+	u32 ahb1_apb1_div;	/* 0x54 AHB1/APB1 divide ratio */
+	u32 apb2_div;		/* 0x58 APB2 divide ratio */
+	u32 ahb2_div;		/* 0x5c AHB2 divide ratio */
+	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
+	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
+	u32 apb1_gate;		/* 0x68 apb1 module clock gating 3 */
+	u32 apb2_gate;		/* 0x6c apb2 module clock gating 4 */
+	u32 reserved7[2];	/* 0x70 */
+	u32 cci400_cfg;		/* 0x78 cci400 clock configuration A83T only */
+	u32 reserved8;		/* 0x7c */
+	u32 nand0_clk_cfg;	/* 0x80 nand clock control */
+	u32 reserved9;		/* 0x84 */
+	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
+	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
+	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
+	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
+	u32 reserved10;		/* 0x98 */
+	u32 ss_clk_cfg;		/* 0x9c security system clock control */
+	u32 spi0_clk_cfg;	/* 0xa0 spi0 clock control */
+	u32 spi1_clk_cfg;	/* 0xa4 spi1 clock control */
+	u32 reserved11[2];	/* 0xa8 */
+	u32 i2s0_clk_cfg;	/* 0xb0 I2S0 clock control */
+	u32 i2s1_clk_cfg;	/* 0xb4 I2S1 clock control */
+	u32 i2s2_clk_cfg;	/* 0xb8 I2S2 clock control */
+	u32 tdm_clk_cfg;	/* 0xbc TDM clock control */
+	u32 spdif_clk_cfg;      /* 0xc0 SPDIF clock control */
+	u32 reserved12[2];	/* 0xc4 */
+	u32 usb_clk_cfg;	/* 0xcc USB clock control */
+	u32 reserved13[9];	/* 0xd0 */
+	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
+	u32 dram_pll_cfg;	/* 0xf8 PLL_DDR cfg register */
+	u32 mbus_reset;		/* 0xfc MBUS reset control */
+	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
+	u32 reserved14[5];	/* 0x104 BE0 */
+	u32 lcd0_clk_cfg;	/* 0x118 LCD0 module clock */
+	u32 lcd1_clk_cfg;	/* 0x11c LCD1 module clock */
+	u32 reserved15[4];	/* 0x120 */
+	u32 mipi_csi_clk_cfg;	/* 0x130 MIPI CSI module clock */
+	u32 csi_clk_cfg;	/* 0x134 CSI module clock */
+	u32 reserved16;		/* 0x138 */
+	u32 ve_clk_cfg;		/* 0x13c VE module clock */
+	u32 reserved17;		/* 0x140 */
+	u32 avs_clk_cfg;	/* 0x144 AVS module clock */
+	u32 reserved18[2];	/* 0x148 */
+	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
+	u32 hdmi_slow_clk_cfg;	/* 0x154 HDMI slow module clock */
+	u32 reserved19;		/* 0x158 */
+	u32 mbus_clk_cfg;	/* 0x15c MBUS module clock */
+	u32 reserved20[2];	/* 0x160 */
+	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
+	u32 reserved21[13];	/* 0x16c */
+	u32 gpu_core_clk_cfg;	/* 0x1a0 GPU core clock config */
+	u32 gpu_mem_clk_cfg;	/* 0x1a4 GPU memory clock config */
+	u32 gpu_hyd_clk_cfg;	/* 0x1a8 GPU HYD clock config */
+	u32 reserved22[21];	/* 0x1ac */
+	u32 pll_stable0;	/* 0x200 PLL stable time 0 */
+	u32 pll_stable1;	/* 0x204 PLL stable time 1 */
+	u32 reserved23;		/* 0x208 */
+	u32 pll_stable_status;	/* 0x20c PLL stable status register */
+	u32 reserved24[4];	/* 0x210 */
+	u32 pll1_c0_bias_cfg;	/* 0x220 PLL1 c0cpu# Bias config */
+	u32 pll2_bias_cfg;	/* 0x224 PLL2 audio Bias config */
+	u32 pll3_bias_cfg;	/* 0x228 PLL3 video Bias config */
+	u32 pll4_bias_cfg;	/* 0x22c PLL4 ve Bias config */
+	u32 pll5_bias_cfg;	/* 0x230 PLL5 ddr Bias config */
+	u32 pll6_bias_cfg;	/* 0x234 PLL6 periph Bias config */
+	u32 pll1_c1_bias_cfg;	/* 0x238 PLL1 c1cpu# Bias config */
+	u32 pll8_bias_cfg;	/* 0x23c PLL7 Bias config */
+	u32 reserved25;		/* 0x240 */
+	u32 pll9_bias_cfg;	/* 0x244 PLL9 hsic Bias config */
+	u32 de_bias_cfg;	/* 0x248 display engine Bias config */
+	u32 video1_bias_cfg;	/* 0x24c pll video1 bias register */
+	u32 c0_tuning_cfg;	/* 0x250 pll c0cpu# tuning register */
+	u32 c1_tuning_cfg;	/* 0x254 pll c1cpu# tuning register */
+	u32 reserved26[11];	/* 0x258 */
+	u32 pll2_pattern_cfg0;	/* 0x284 PLL2 Pattern register 0 */
+	u32 pll3_pattern_cfg0;	/* 0x288 PLL3 Pattern register 0 */
+	u32 reserved27;		/* 0x28c */
+	u32 pll5_pattern_cfg0;	/* 0x290 PLL5 Pattern register 0*/
+	u32 reserved28[4];	/* 0x294 */
+	u32 pll2_pattern_cfg1;	/* 0x2a4 PLL2 Pattern register 1 */
+	u32 pll3_pattern_cfg1;	/* 0x2a8 PLL3 Pattern register 1 */
+	u32 reserved29;		/* 0x2ac */
+	u32 pll5_pattern_cfg1;	/* 0x2b0 PLL5 Pattern register 1 */
+	u32 reserved30[3];	/* 0x2b4 */
+	u32 ahb_reset0_cfg;	/* 0x2c0 AHB1 Reset 0 config */
+	u32 ahb_reset1_cfg;	/* 0x2c4 AHB1 Reset 1 config */
+	u32 ahb_reset2_cfg;	/* 0x2c8 AHB1 Reset 2 config */
+	u32 reserved31;
+	u32 ahb_reset3_cfg;	/* 0x2d0 AHB1 Reset 3 config */
+	u32 reserved32;		/* 0x2d4 */
+	u32 apb2_reset_cfg;	/* 0x2d8 BUS Reset 4 config */
+};
+
+/* apb2 bit field */
+#define APB2_CLK_SRC_LOSC		(0x0 << 24)
+#define APB2_CLK_SRC_OSC24M		(0x1 << 24)
+#define APB2_CLK_SRC_PLL6		(0x2 << 24)
+#define APB2_CLK_SRC_MASK		(0x3 << 24)
+#define APB2_CLK_RATE_N_1		(0x0 << 16)
+#define APB2_CLK_RATE_N_2		(0x1 << 16)
+#define APB2_CLK_RATE_N_4		(0x2 << 16)
+#define APB2_CLK_RATE_N_8		(0x3 << 16)
+#define APB2_CLK_RATE_N_MASK		(3 << 16)
+#define APB2_CLK_RATE_M(m)		(((m)-1) << 0)
+#define APB2_CLK_RATE_M_MASK            (0x1f << 0)
+
+/* apb2 gate field */
+#define APB2_GATE_UART_SHIFT	(16)
+#define APB2_GATE_UART_MASK		(0xff << APB2_GATE_UART_SHIFT)
+#define APB2_GATE_TWI_SHIFT	(0)
+#define APB2_GATE_TWI_MASK		(0xf << APB2_GATE_TWI_SHIFT)
+
+/* cpu_axi_cfg bits */
+#define AXI0_DIV_SHIFT			0
+#define AXI1_DIV_SHIFT			16
+#define C0_CPUX_CLK_SRC_SHIFT		12
+#define C1_CPUX_CLK_SRC_SHIFT		28
+
+#define AXI_DIV_1			0
+#define AXI_DIV_2			1
+#define AXI_DIV_3			2
+#define AXI_DIV_4			3
+#define CPU_CLK_SRC_OSC24M		0
+#define CPU_CLK_SRC_PLL1		1
+
+#define CCM_PLL1_CTRL_N(n)		(((n) & 0xff) << 8)
+#define CCM_PLL1_CTRL_P(n)		(((n) & 0x1) << 16)
+#define CCM_PLL1_CTRL_EN		(0x1 << 31)
+#define CMM_PLL1_CLOCK_TIME_2		(0x2 << 24)
+
+#define PLL8_CFG_DEFAULT		0x42800
+#define CCM_CCI400_CLK_SEL_HSIC		(0x2<<24)
+
+#define CCM_PLL5_DIV1_SHIFT		16
+#define CCM_PLL5_DIV2_SHIFT		18
+#define CCM_PLL5_CTRL_N(n)		(((n) - 1) << 8)
+#define CCM_PLL5_CTRL_UPD		(0x1 << 30)
+#define CCM_PLL5_CTRL_EN		(0x1 << 31)
+
+#define PLL6_CFG_DEFAULT		0x80001900 /* 600 MHz */
+#define CCM_PLL6_CTRL_N_SHIFT		8
+#define CCM_PLL6_CTRL_N_MASK		(0xff << CCM_PLL6_CTRL_N_SHIFT)
+#define CCM_PLL6_CTRL_DIV1_SHIFT	16
+#define CCM_PLL6_CTRL_DIV1_MASK		(0x1 << CCM_PLL6_CTRL_DIV1_SHIFT)
+#define CCM_PLL6_CTRL_DIV2_SHIFT	18
+#define CCM_PLL6_CTRL_DIV2_MASK		(0x1 << CCM_PLL6_CTRL_DIV2_SHIFT)
+
+#define AHB1_ABP1_DIV_DEFAULT		0x00002190
+#define AHB1_CLK_SRC_MASK		(0x3<<12)
+#define AHB1_CLK_SRC_INTOSC		(0x0<<12)
+#define AHB1_CLK_SRC_OSC24M		(0x1<<12)
+#define AHB1_CLK_SRC_PLL6		(0x2<<12)
+
+#define AXI_GATE_OFFSET_DRAM		0
+
+/* ahb_gate0 offsets */
+#define AHB_GATE_OFFSET_USB_OHCI1	30
+#define AHB_GATE_OFFSET_USB_OHCI0	29
+#define AHB_GATE_OFFSET_USB_EHCI1	27
+#define AHB_GATE_OFFSET_USB_EHCI0	26
+#define AHB_GATE_OFFSET_USB0		24
+#define AHB_GATE_OFFSET_SPI1		21
+#define AHB_GATE_OFFSET_SPI0		20
+#define AHB_GATE_OFFSET_HSTIMER		19
+#define AHB_GATE_OFFSET_EMAC		17
+#define AHB_GATE_OFFSET_MCTL		14
+#define AHB_GATE_OFFSET_GMAC		17
+#define AHB_GATE_OFFSET_NAND0		13
+#define AHB_GATE_OFFSET_MMC0		8
+#define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_DMA		6
+#define AHB_GATE_OFFSET_SS		5
+
+/* ahb_gate1 offsets */
+#define AHB_GATE_OFFSET_DRC0		25
+#define AHB_GATE_OFFSET_DE_FE0		14
+#define AHB_GATE_OFFSET_DE_BE0		12
+#define AHB_GATE_OFFSET_HDMI		11
+#define AHB_GATE_OFFSET_LCD1		5
+#define AHB_GATE_OFFSET_LCD0		4
+
+#define CCM_MMC_CTRL_M(x)		((x) - 1)
+#define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
+#define CCM_MMC_CTRL_N(x)		((x) << 16)
+#define CCM_MMC_CTRL_SCLK_DLY(x)	((x) << 20)
+#define CCM_MMC_CTRL_OSCM24		(0x0 << 24)
+#define CCM_MMC_CTRL_PLL6		(0x1 << 24)
+#define CCM_MMC_CTRL_MODE_SEL_NEW	(0x1 << 30)
+#define CCM_MMC_CTRL_ENABLE		(0x1 << 31)
+
+#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
+#define CCM_USB_CTRL_HSIC_RST (0x1 << 2)
+/* There is no global phy clk gate on sun6i, define as 0 */
+#define CCM_USB_CTRL_PHYGATE 0
+#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
+#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
+#define CCM_USB_CTRL_HSIC_CLK (0x1 << 10)
+#define CCM_USB_CTRL_12M_CLK (0x1 << 11)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+
+#define CCM_GMAC_CTRL_TX_CLK_SRC_MII	0x0
+#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
+#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
+#define CCM_GMAC_CTRL_GPIT_MII		(0x0 << 2)
+#define CCM_GMAC_CTRL_GPIT_RGMII	(0x1 << 2)
+#define CCM_GMAC_CTRL_RX_CLK_DELAY(x)	((x) << 5)
+#define CCM_GMAC_CTRL_TX_CLK_DELAY(x)	((x) << 10)
+
+#define MDFS_CLK_DEFAULT		0x81000002 /* PLL6 / 3 */
+
+#define CCM_DRAMCLK_CFG_DIV(x)		((x - 1) << 0)
+#define CCM_DRAMCLK_CFG_DIV_MASK	(0xf << 0)
+#define CCM_DRAMCLK_CFG_DIV0(x)		((x - 1) << 8)
+#define CCM_DRAMCLK_CFG_DIV0_MASK	(0xf << 8)
+#define CCM_DRAMCLK_CFG_UPD		(0x1 << 16)
+#define CCM_DRAMCLK_CFG_RST		(0x1 << 31)
+
+#define CCM_DRAMPLL_CFG_SRC_PLL5	(0x0 << 16) /* Select PLL5 (DDR0) */
+#define CCM_DRAMPLL_CFG_SRC_PLL11	(0x1 << 16) /* Select PLL11 (DDR1) */
+#define CCM_DRAMPLL_CFG_SRC_MASK	(0x1 << 16)
+
+#define CCM_MBUS_RESET_RESET		(0x1 << 31)
+
+#define CCM_DRAM_GATE_OFFSET_DE_FE0	24
+#define CCM_DRAM_GATE_OFFSET_DE_FE1	25
+#define CCM_DRAM_GATE_OFFSET_DE_BE0	26
+#define CCM_DRAM_GATE_OFFSET_DE_BE1	27
+
+
+#define MBUS_CLK_DEFAULT		0x81000002 /* PLL6 / 2 */
+
+#define MBUS_CLK_GATE			(0x1 << 31)
+
+/* ahb_reset0 offsets */
+#define AHB_RESET_OFFSET_GMAC		17
+#define AHB_RESET_OFFSET_MCTL		14
+#define AHB_RESET_OFFSET_MMC3		11
+#define AHB_RESET_OFFSET_MMC2		10
+#define AHB_RESET_OFFSET_MMC1		9
+#define AHB_RESET_OFFSET_MMC0		8
+#define AHB_RESET_OFFSET_MMC(n)		(AHB_RESET_OFFSET_MMC0 + (n))
+#define AHB_RESET_OFFSET_SS		5
+
+/* ahb_reset1 offsets */
+#define AHB_RESET_OFFSET_SAT		26
+#define AHB_RESET_OFFSET_DRC0		25
+#define AHB_RESET_OFFSET_DE_FE0		14
+#define AHB_RESET_OFFSET_DE_BE0		12
+#define AHB_RESET_OFFSET_HDMI		11
+#define AHB_RESET_OFFSET_LCD1		5
+#define AHB_RESET_OFFSET_LCD0		4
+
+/* ahb_reset2 offsets */
+#define AHB_RESET_OFFSET_LVDS		0
+
+/* apb2 reset */
+#define APB2_RESET_UART_SHIFT		(16)
+#define APB2_RESET_UART_MASK		(0xff << APB2_RESET_UART_SHIFT)
+#define APB2_RESET_TWI_SHIFT		(0)
+#define APB2_RESET_TWI_MASK		(0xf << APB2_RESET_TWI_SHIFT)
+
+
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll5(unsigned int clk);
+unsigned int clock_get_pll6(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_SUN8I_A83T_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
new file mode 100644
index 0000000..530e0dd
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * sun9i clock register definitions
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ */
+
+#ifndef _SUNXI_CLOCK_SUN9I_H
+#define _SUNXI_CLOCK_SUN9I_H
+
+struct sunxi_ccm_reg {
+	u32 pll1_c0_cfg;	/* 0x00 c0cpu# pll configuration */
+	u32 pll2_c1_cfg;	/* 0x04 c1cpu# pll configuration */
+	u32 pll3_audio_cfg;	/* 0x08 audio pll configuration */
+	u32 pll4_periph0_cfg;	/* 0x0c peripheral0 pll configuration */
+	u32 pll5_ve_cfg;	/* 0x10 videoengine pll configuration */
+	u32 pll6_ddr_cfg;	/* 0x14 ddr pll configuration */
+	u32 pll7_video0_cfg;	/* 0x18 video0 pll configuration */
+	u32 pll8_video1_cfg;	/* 0x1c video1 pll configuration */
+	u32 pll9_gpu_cfg;	/* 0x20 gpu pll configuration */
+	u32 pll10_de_cfg;	/* 0x24 displayengine pll configuration */
+	u32 pll11_isp_cfg;	/* 0x28 isp pll6 ontrol */
+	u32 pll12_periph1_cfg;	/* 0x2c peripheral1 pll configuration */
+	u8 reserved1[0x20];	/* 0x30 */
+	u32 cpu_clk_source;	/* 0x50 cpu clk source configuration */
+	u32 c0_cfg;		/* 0x54 cpu cluster 0 clock configuration */
+	u32 c1_cfg;		/* 0x58 cpu cluster 1 clock configuration */
+	u32 gtbus_cfg;		/* 0x5c gtbus clock configuration */
+	u32 ahb0_cfg;		/* 0x60 ahb0 clock configuration */
+	u32 ahb1_cfg;		/* 0x64 ahb1 clock configuration */
+	u32 ahb2_cfg;		/* 0x68 ahb2 clock configuration */
+	u8 reserved2[0x04];	/* 0x6c */
+	u32 apb0_cfg;		/* 0x70 apb0 clock configuration */
+	u32 apb1_cfg;		/* 0x74 apb1 clock configuration */
+	u32 cci400_cfg;		/* 0x78 cci400 clock configuration */
+	u8 reserved3[0x04];	/* 0x7c */
+	u32 ats_cfg;		/* 0x80 ats clock configuration */
+	u32 trace_cfg;		/* 0x84 trace clock configuration */
+	u8 reserved4[0x14];     /* 0x88 */
+	u32 pll_stable_status;  /* 0x9c */
+	u8 reserved5[0xe0];	/* 0xa0 */
+	u32 clk_output_a;	/* 0x180 clk_output_a */
+	u32 clk_output_b;	/* 0x184 clk_output_a */
+	u8 reserved6[0x278];	/* 0x188 */
+
+	u32 nand0_clk_cfg;	/* 0x400 nand0 clock configuration0 */
+	u32 nand0_clk_cfg1;	/* 0x404 nand1 clock configuration */
+	u8 reserved7[0x08];	/* 0x408 */
+	u32 sd0_clk_cfg;	/* 0x410 sd0 clock configuration */
+	u32 sd1_clk_cfg;	/* 0x414 sd1 clock configuration */
+	u32 sd2_clk_cfg;	/* 0x418 sd2 clock configuration */
+	u32 sd3_clk_cfg;	/* 0x41c sd3 clock configuration */
+	u8 reserved8[0x08];	/* 0x420 */
+	u32 ts_clk_cfg;		/* 0x428 transport stream clock cfg */
+	u32 ss_clk_cfg;		/* 0x42c security system clock cfg */
+	u32 spi0_clk_cfg;	/* 0x430 spi0 clock configuration */
+	u32 spi1_clk_cfg;	/* 0x434 spi1 clock configuration */
+	u32 spi2_clk_cfg;	/* 0x438 spi2 clock configuration */
+	u32 spi3_clk_cfg;	/* 0x43c spi3 clock configuration */
+	u8 reserved9[0x44];	/* 0x440 */
+	u32 dram_clk_cfg;       /* 0x484 DRAM (controller) clock config */
+	u8 reserved10[0x8];     /* 0x488 */
+	u32 de_clk_cfg;		/* 0x490 display engine clock configuration */
+	u8 reserved11[0x04];	/* 0x494 */
+	u32 mp_clk_cfg;		/* 0x498 mp clock configuration */
+	u32 lcd0_clk_cfg;	/* 0x49c LCD0 module clock */
+	u32 lcd1_clk_cfg;	/* 0x4a0 LCD1 module clock */
+	u8 reserved12[0x1c];	/* 0x4a4 */
+	u32 csi_isp_clk_cfg;	/* 0x4c0 CSI ISP module clock */
+	u32 csi0_clk_cfg;	/* 0x4c4 CSI0 module clock */
+	u32 csi1_clk_cfg;	/* 0x4c8 CSI1 module clock */
+	u32 fd_clk_cfg;		/* 0x4cc FD module clock */
+	u32 ve_clk_cfg;		/* 0x4d0 VE module clock */
+	u32 avs_clk_cfg;	/* 0x4d4 AVS module clock */
+	u8 reserved13[0x18];	/* 0x4d8 */
+	u32 gpu_core_clk_cfg;	/* 0x4f0 GPU core clock config */
+	u32 gpu_mem_clk_cfg;	/* 0x4f4 GPU memory clock config */
+	u32 gpu_axi_clk_cfg;	/* 0x4f8 GPU AXI clock config */
+	u8 reserved14[0x10];	/* 0x4fc */
+	u32 gp_adc_clk_cfg;	/* 0x50c General Purpose ADC clk config */
+	u8 reserved15[0x70];	/* 0x510 */
+
+	u32 ahb_gate0;		/* 0x580 AHB0 Gating Register */
+	u32 ahb_gate1;		/* 0x584 AHB1 Gating Register */
+	u32 ahb_gate2;		/* 0x588 AHB2 Gating Register */
+	u8 reserved16[0x04];	/* 0x58c */
+	u32 apb0_gate;		/* 0x590 APB0 Clock Gating Register */
+	u32 apb1_gate;		/* 0x594 APB1 Clock Gating Register */
+	u8 reserved17[0x08];	/* 0x598 */
+	u32 ahb_reset0_cfg;	/* 0x5a0 AHB0 Software Reset Register */
+	u32 ahb_reset1_cfg;	/* 0x5a4 AHB1 Software Reset Register */
+	u32 ahb_reset2_cfg;	/* 0x5a8 AHB2 Software Reset Register */
+	u8 reserved18[0x04];	/* 0x5ac */
+	u32 apb0_reset_cfg;	/* 0x5b0 Bus Software Reset Register 3 */
+	u32 apb1_reset_cfg;	/* 0x5b4 Bus Software Reset Register 4 */
+};
+
+#define CCM_PLL4_CTRL_N_SHIFT		8
+#define CCM_PLL4_CTRL_N_MASK		(0xff << CCM_PLL4_CTRL_N_SHIFT)
+#define CCM_PLL4_CTRL_P_SHIFT		16
+#define CCM_PLL4_CTRL_P_MASK		(0x1 << CCM_PLL4_CTRL_P_SHIFT)
+#define CCM_PLL4_CTRL_M_SHIFT		18
+#define CCM_PLL4_CTRL_M_MASK		(0x1 << CCM_PLL4_CTRL_M_SHIFT)
+
+/* pllx_cfg bits */
+#define CCM_PLL1_CTRL_N(n)		(((n) & 0xff) << 8)
+#define CCM_PLL1_CTRL_P(n)		(((n) & 0x1) << 16)
+#define CCM_PLL1_CTRL_EN		(1 << 31)
+#define CCM_PLL1_CLOCK_TIME_2		(2 << 24)
+
+#define CCM_PLL2_CTRL_N(n)		(((n) & 0xff) << 8)
+#define CCM_PLL2_CTRL_P(n)		(((n) & 0x1) << 16)
+#define CCM_PLL2_CTRL_EN		(1 << 31)
+#define CCM_PLL2_CLOCK_TIME_2		(2 << 24)
+
+#define CCM_PLL4_CTRL_N(n)		(((n) & 0xff) << 8)
+#define CCM_PLL4_CTRL_EN		(1 << 31)
+
+#define CCM_PLL6_CTRL_N(n)		(((n) & 0xff) << 8)
+#define CCM_PLL6_CTRL_P(p)		(((p) & 0x1) << 16)
+#define CCM_PLL6_CTRL_EN		(1 << 31)
+#define CCM_PLL6_CFG_UPDATE             (1 << 30)
+
+#define CCM_PLL12_CTRL_N(n)		(((n) & 0xff) << 8)
+#define CCM_PLL12_CTRL_EN		(1 << 31)
+
+#define PLL_C0CPUX_STATUS               (1 << 0)
+#define PLL_C1CPUX_STATUS               (1 << 1)
+#define PLL_DDR_STATUS                  (1 << 5)
+#define PLL_PERIPH1_STATUS              (1 << 11)
+
+/* cpu_clk_source bits */
+#define C0_CPUX_CLK_SRC_SHIFT           0
+#define C1_CPUX_CLK_SRC_SHIFT           8
+#define C0_CPUX_CLK_SRC_MASK            (1 << C0_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_MASK            (1 << C1_CPUX_CLK_SRC_SHIFT)
+#define C0_CPUX_CLK_SRC_OSC24M		(0 << C0_CPUX_CLK_SRC_SHIFT)
+#define C0_CPUX_CLK_SRC_PLL1		(1 << C0_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_OSC24M		(0 << C1_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_PLL2		(1 << C1_CPUX_CLK_SRC_SHIFT)
+
+/* c0_cfg */
+#define C0_CFG_AXI0_CLK_DIV_RATIO(n)    (((n - 1) & 0x3) << 0)
+#define C0_CFG_APB0_CLK_DIV_RATIO(n)    (((n - 1) & 0x3) << 8)
+
+/* ahbx_cfg */
+#define AHBx_SRC_CLK_SELECT_SHIFT       24
+#define AHBx_SRC_MASK                   (0x3 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB0_SRC_GTBUS_CLK              (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB1_SRC_GTBUS_CLK              (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB2_SRC_OSC24M                 (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_SRC_PLL_PERIPH0            (0x1 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_SRC_PLL_PERIPH1            (0x2 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_CLK_DIV_RATIO(n)           (((ffs(n) - 1) & 0x3) << 0)
+
+/* apb0_cfg */
+#define APB0_SRC_CLK_SELECT_SHIFT       24
+#define APB0_SRC_MASK                   (0x1 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_SRC_OSC24M                 (0x0 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_SRC_PLL_PERIPH0            (0x1 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_CLK_DIV_RATIO(n)           (((ffs(n) - 1) & 0x3) << 0)
+
+/* gtbus_clk_cfg */
+#define GTBUS_SRC_CLK_SELECT_SHIFT      24
+#define GTBUS_SRC_MASK                  (0x3 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_OSC24M                (0x0 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_PLL_PERIPH0           (0x1 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_PLL_PERIPH1           (0x2 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_CLK_DIV_RATIO(n)          (((n - 1) & 0x3) << 0)
+
+/* cci400_clk_cfg */
+#define CCI400_SRC_CLK_SELECT_SHIFT     24
+#define CCI400_SRC_MASK                 (0x3 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_OSC24M               (0x0 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_PLL_PERIPH0          (0x1 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_PLL_PERIPH1          (0x2 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_CLK_DIV_RATIO(n)         (((n - 1) & 0x3) << 0)
+
+/* sd#_clk_cfg fields */
+#define CCM_MMC_CTRL_M(x)		((x) - 1)
+#define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
+#define CCM_MMC_CTRL_N(x)		((x) << 16)
+#define CCM_MMC_CTRL_SCLK_DLY(x)	((x) << 20)
+#define CCM_MMC_CTRL_OSCM24		(0 << 24)
+#define CCM_MMC_CTRL_PLL_PERIPH0	(1 << 24)
+#define CCM_MMC_CTRL_ENABLE		(1 << 31)
+
+/* ahb_gate0 fields */
+#define AHB_GATE_OFFSET_MCTL		14
+
+/* On sun9i all sdc-s share their ahb gate, so ignore (x) */
+#define AHB_GATE_OFFSET_NAND0		13
+#define AHB_GATE_OFFSET_MMC(x)		8
+
+/* ahb gate1 field */
+#define AHB_GATE_OFFSET_DMA		24
+
+/* apb1_gate fields */
+#define APB1_GATE_UART_SHIFT		16
+#define APB1_GATE_UART_MASK		(0xff << APB1_GATE_UART_SHIFT)
+#define APB1_GATE_TWI_SHIFT		0
+#define APB1_GATE_TWI_MASK		(0xf << APB1_GATE_TWI_SHIFT)
+
+/* ahb_reset0_cfg fields */
+#define AHB_RESET_OFFSET_MCTL		14
+
+/* On sun9i all sdc-s share their ahb reset, so ignore (x) */
+#define AHB_RESET_OFFSET_MMC(x)		8
+
+/* apb1_reset_cfg fields */
+#define APB1_RESET_UART_SHIFT		16
+#define APB1_RESET_UART_MASK		(0xff << APB1_RESET_UART_SHIFT)
+#define APB1_RESET_TWI_SHIFT		0
+#define APB1_RESET_TWI_MASK		(0xf << APB1_RESET_TWI_SHIFT)
+
+
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int clk);
+void clock_set_pll2(unsigned int clk);
+void clock_set_pll4(unsigned int clk);
+void clock_set_pll6(unsigned int clk);
+void clock_set_pll12(unsigned int clk);
+unsigned int clock_get_pll4_periph0(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_SUN9I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
new file mode 100644
index 0000000..4c399b0
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ */
+
+#ifndef _SUNXI_CPU_H
+#define _SUNXI_CPU_H
+
+#if defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/cpu_sun9i.h>
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#include <asm/arch/cpu_sun50i_h6.h>
+#else
+#include <asm/arch/cpu_sun4i.h>
+#endif
+
+#define SOCID_A64	0x1689
+#define SOCID_H3	0x1680
+#define SOCID_H5	0x1718
+#define SOCID_R40	0x1701
+
+#endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
new file mode 100644
index 0000000..02ce739
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#ifndef _SUNXI_CPU_SUN4I_H
+#define _SUNXI_CPU_SUN4I_H
+
+#define SUNXI_SRAM_A1_BASE		0x00000000
+#define SUNXI_SRAM_A1_SIZE		(16 * 1024)	/* 16 kiB */
+
+#define SUNXI_SRAM_A2_BASE		0x00004000	/* 16 kiB */
+#define SUNXI_SRAM_A3_BASE		0x00008000	/* 13 kiB */
+#define SUNXI_SRAM_A4_BASE		0x0000b400	/* 3 kiB */
+#define SUNXI_SRAM_D_BASE		0x00010000	/* 4 kiB */
+#define SUNXI_SRAM_B_BASE		0x00020000	/* 64 kiB (secure) */
+
+#define SUNXI_DE2_BASE			0x01000000
+
+#ifdef CONFIG_MACH_SUN8I_A83T
+#define SUNXI_CPUCFG_BASE		0x01700000
+#endif
+
+#define SUNXI_SRAMC_BASE		0x01c00000
+#define SUNXI_DRAMC_BASE		0x01c01000
+#define SUNXI_DMA_BASE			0x01c02000
+#define SUNXI_NFC_BASE			0x01c03000
+#define SUNXI_TS_BASE			0x01c04000
+#define SUNXI_SPI0_BASE			0x01c05000
+#define SUNXI_SPI1_BASE			0x01c06000
+#define SUNXI_MS_BASE			0x01c07000
+#define SUNXI_TVD_BASE			0x01c08000
+#define SUNXI_CSI0_BASE			0x01c09000
+#ifndef CONFIG_MACH_SUNXI_H3_H5
+#define SUNXI_TVE0_BASE			0x01c0a000
+#endif
+#define SUNXI_EMAC_BASE			0x01c0b000
+#define SUNXI_LCD0_BASE			0x01c0C000
+#define SUNXI_LCD1_BASE			0x01c0d000
+#define SUNXI_VE_BASE			0x01c0e000
+#define SUNXI_MMC0_BASE			0x01c0f000
+#define SUNXI_MMC1_BASE			0x01c10000
+#define SUNXI_MMC2_BASE			0x01c11000
+#define SUNXI_MMC3_BASE			0x01c12000
+#ifdef CONFIG_SUNXI_GEN_SUN4I
+#define SUNXI_USB0_BASE			0x01c13000
+#define SUNXI_USB1_BASE			0x01c14000
+#endif
+#define SUNXI_SS_BASE			0x01c15000
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
+#define SUNXI_HDMI_BASE			0x01c16000
+#endif
+#define SUNXI_SPI2_BASE			0x01c17000
+#define SUNXI_SATA_BASE			0x01c18000
+#ifdef CONFIG_SUNXI_GEN_SUN4I
+#define SUNXI_PATA_BASE			0x01c19000
+#define SUNXI_ACE_BASE			0x01c1a000
+#define SUNXI_TVE1_BASE			0x01c1b000
+#define SUNXI_USB2_BASE			0x01c1c000
+#endif
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+#define SUNXI_USBPHY_BASE		0x01c19000
+#define SUNXI_USB0_BASE			SUNXI_USBPHY_BASE
+#define SUNXI_USB1_BASE			0x01c1a000
+#define SUNXI_USB2_BASE			0x01c1b000
+#define SUNXI_USB3_BASE			0x01c1c000
+#define SUNXI_USB4_BASE			0x01c1d000
+#else
+#define SUNXI_USB0_BASE			0x01c19000
+#define SUNXI_USB1_BASE			0x01c1a000
+#define SUNXI_USB2_BASE			0x01c1b000
+#endif
+#endif
+#define SUNXI_CSI1_BASE			0x01c1d000
+#define SUNXI_TZASC_BASE		0x01c1e000
+#define SUNXI_SPI3_BASE			0x01c1f000
+
+#define SUNXI_CCM_BASE			0x01c20000
+#define SUNXI_INTC_BASE			0x01c20400
+#define SUNXI_PIO_BASE			0x01c20800
+#define SUNXI_TIMER_BASE		0x01c20c00
+#ifndef CONFIG_SUNXI_GEN_SUN6I
+#define SUNXI_PWM_BASE			0x01c20e00
+#endif
+#define SUNXI_SPDIF_BASE		0x01c21000
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+#define SUNXI_PWM_BASE			0x01c21400
+#else
+#define SUNXI_AC97_BASE			0x01c21400
+#endif
+#define SUNXI_IR0_BASE			0x01c21800
+#define SUNXI_IR1_BASE			0x01c21c00
+
+#define SUNXI_IIS_BASE			0x01c22400
+#define SUNXI_LRADC_BASE		0x01c22800
+#define SUNXI_AD_DA_BASE		0x01c22c00
+#define SUNXI_KEYPAD_BASE		0x01c23000
+#define SUNXI_TZPC_BASE			0x01c23400
+
+#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \
+defined(CONFIG_MACH_SUN50I)
+/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
+#define SUNXI_SIDC_BASE			0x01c14000
+#define SUNXI_SID_BASE			0x01c14200
+#else
+#define SUNXI_SID_BASE			0x01c23800
+#endif
+
+#define SUNXI_SJTAG_BASE		0x01c23c00
+
+#define SUNXI_TP_BASE			0x01c25000
+#define SUNXI_PMU_BASE			0x01c25400
+
+#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40
+#define SUNXI_CPUCFG_BASE		0x01c25c00
+#endif
+
+#define SUNXI_UART0_BASE		0x01c28000
+#define SUNXI_UART1_BASE		0x01c28400
+#define SUNXI_UART2_BASE		0x01c28800
+#define SUNXI_UART3_BASE		0x01c28c00
+#define SUNXI_UART4_BASE		0x01c29000
+#define SUNXI_UART5_BASE		0x01c29400
+#define SUNXI_UART6_BASE		0x01c29800
+#define SUNXI_UART7_BASE		0x01c29c00
+#define SUNXI_PS2_0_BASE		0x01c2a000
+#define SUNXI_PS2_1_BASE		0x01c2a400
+
+#define SUNXI_TWI0_BASE			0x01c2ac00
+#define SUNXI_TWI1_BASE			0x01c2b000
+#define SUNXI_TWI2_BASE			0x01c2b400
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_TWI3_BASE			0x01c0b800
+#endif
+#ifdef CONFIG_MACH_SUN7I
+#define SUNXI_TWI3_BASE			0x01c2b800
+#define SUNXI_TWI4_BASE			0x01c2c000
+#endif
+
+#define SUNXI_CAN_BASE			0x01c2bc00
+
+#define SUNXI_SCR_BASE			0x01c2c400
+
+#ifndef CONFIG_MACH_SUN6I
+#define SUNXI_GPS_BASE			0x01c30000
+#define SUNXI_MALI400_BASE		0x01c40000
+#define SUNXI_GMAC_BASE			0x01c50000
+#else
+#define SUNXI_GMAC_BASE			0x01c30000
+#endif
+
+#define SUNXI_DRAM_COM_BASE		0x01c62000
+#define SUNXI_DRAM_CTL0_BASE		0x01c63000
+#define SUNXI_DRAM_CTL1_BASE		0x01c64000
+#define SUNXI_DRAM_PHY0_BASE		0x01c65000
+#define SUNXI_DRAM_PHY1_BASE		0x01c66000
+
+#define SUNXI_GIC400_BASE		0x01c80000
+
+/* module sram */
+#define SUNXI_SRAM_C_BASE		0x01d00000
+
+#ifndef CONFIG_MACH_SUN8I_H3
+#define SUNXI_DE_FE0_BASE		0x01e00000
+#else
+#define SUNXI_TVE0_BASE			0x01e00000
+#endif
+#define SUNXI_DE_FE1_BASE		0x01e20000
+#define SUNXI_DE_BE0_BASE		0x01e60000
+#ifndef CONFIG_MACH_SUN50I_H5
+#define SUNXI_DE_BE1_BASE		0x01e40000
+#else
+#define SUNXI_TVE0_BASE			0x01e40000
+#endif
+#define SUNXI_MP_BASE			0x01e80000
+#define SUNXI_AVG_BASE			0x01ea0000
+
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+#define SUNXI_HDMI_BASE			0x01ee0000
+#endif
+
+#define SUNXI_RTC_BASE			0x01f00000
+#define SUNXI_PRCM_BASE			0x01f01400
+
+#if defined CONFIG_SUNXI_GEN_SUN6I && \
+    !defined CONFIG_MACH_SUN8I_A83T && \
+    !defined CONFIG_MACH_SUN8I_R40
+#define SUNXI_CPUCFG_BASE		0x01f01c00
+#endif
+
+#define SUNXI_R_TWI_BASE		0x01f02400
+#define SUNXI_R_UART_BASE		0x01f02800
+#define SUNXI_R_PIO_BASE		0x01f02c00
+#define SUN6I_P2WI_BASE			0x01f03400
+#define SUNXI_RSB_BASE			0x01f03400
+
+/* CoreSight Debug Module */
+#define SUNXI_CSDM_BASE			0x3f500000
+
+#define SUNXI_DDRII_DDRIII_BASE		0x40000000	/* 2 GiB */
+
+#define SUNXI_BROM_BASE			0xffff0000	/* 32 kiB */
+
+#define SUNXI_CPU_CFG			(SUNXI_TIMER_BASE + 0x13c)
+
+/* SS bonding ids used for cpu identification */
+#define SUNXI_SS_BOND_ID_A31		4
+#define SUNXI_SS_BOND_ID_A31S		5
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_ss_bonding_id(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SUNXI_CPU_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
new file mode 100644
index 0000000..6392cb0
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUN50I_H6_H
+#define _SUNXI_CPU_SUN50I_H6_H
+
+#define SUNXI_SRAM_A1_BASE		CONFIG_SUNXI_SRAM_ADDRESS
+#define SUNXI_SRAM_C_BASE		0x00028000
+#define SUNXI_SRAM_A2_BASE		0x00100000
+
+#define SUNXI_DE3_BASE			0x01000000
+#define SUNXI_SS_BASE			0x01904000
+#define SUNXI_EMCE_BASE			0x01905000
+
+#define SUNXI_SRAMC_BASE		0x03000000
+#define SUNXI_CCM_BASE			0x03001000
+#define SUNXI_DMA_BASE			0x03002000
+/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
+#define SUNXI_SIDC_BASE			0x03006000
+#define SUNXI_SID_BASE			0x03006200
+#define SUNXI_TIMER_BASE		0x03009000
+#define SUNXI_PIO_BASE			0x0300B000
+#define SUNXI_PSI_BASE			0x0300C000
+
+#define SUNXI_GIC400_BASE		0x03020000
+#define SUNXI_IOMMU_BASE		0x030F0000
+
+#define SUNXI_DRAM_COM_BASE		0x04002000
+#define SUNXI_DRAM_CTL0_BASE		0x04003000
+#define SUNXI_DRAM_PHY0_BASE		0x04005000
+#define SUNXI_NFC_BASE			0x04011000
+#define SUNXI_MMC0_BASE			0x04020000
+#define SUNXI_MMC1_BASE			0x04021000
+#define SUNXI_MMC2_BASE			0x04022000
+
+#define SUNXI_UART0_BASE		0x05000000
+#define SUNXI_UART1_BASE		0x05000400
+#define SUNXI_UART2_BASE		0x05000800
+#define SUNXI_UART3_BASE		0x05000C00
+#define SUNXI_TWI0_BASE			0x05002000
+#define SUNXI_TWI1_BASE			0x05002400
+#define SUNXI_TWI2_BASE			0x05002800
+#define SUNXI_TWI3_BASE			0x05002C00
+#define SUNXI_SPI0_BASE			0x05010000
+#define SUNXI_SPI1_BASE			0x05011000
+#define SUNXI_GMAC_BASE			0x05020000
+#define SUNXI_USB0_BASE			0x05100000
+#define SUNXI_XHCI_BASE			0x05200000
+#define SUNXI_USB3_BASE			0x05311000
+#define SUNXI_PCIE_BASE			0x05400000
+
+#define SUNXI_HDMI_BASE			0x06000000
+#define SUNXI_TCON_TOP_BASE		0x06510000
+#define SUNXI_TCON_LCD0_BASE		0x06511000
+#define SUNXI_TCON_TV0_BASE		0x06515000
+
+#define SUNXI_RTC_BASE			0x07000000
+#define SUNXI_R_CPUCFG_BASE		0x07000400
+#define SUNXI_PRCM_BASE			0x07010000
+#define SUNXI_R_WDOG_BASE		0x07020400
+#define SUNXI_R_PIO_BASE		0x07022000
+#define SUNXI_R_UART_BASE		0x07080000
+#define SUNXI_R_TWI_BASE		0x07081400
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif
+
+#endif /* _SUNXI_CPU_SUN9I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
new file mode 100644
index 0000000..9c2d11b
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Jerry Wang <wangflord@allwinnertech.com>
+ */
+
+#ifndef _SUNXI_CPU_SUN9I_H
+#define _SUNXI_CPU_SUN9I_H
+
+#define REGS_AHB0_BASE			0x01C00000
+#define REGS_AHB1_BASE			0x00800000
+#define REGS_AHB2_BASE			0x03000000
+#define REGS_APB0_BASE			0x06000000
+#define REGS_APB1_BASE			0x07000000
+#define REGS_RCPUS_BASE			0x08000000
+
+#define SUNXI_SRAM_D_BASE		0x08100000
+
+/* AHB0 Module */
+#define SUNXI_NFC_BASE			(REGS_AHB0_BASE + 0x3000)
+#define SUNXI_TSC_BASE			(REGS_AHB0_BASE + 0x4000)
+
+#define SUNXI_GTBUS_BASE		(REGS_AHB0_BASE + 0x9000)
+/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */
+#define SUNXI_SID_BASE			(REGS_AHB0_BASE + 0xe200)
+
+#define SUNXI_MMC0_BASE			(REGS_AHB0_BASE + 0x0f000)
+#define SUNXI_MMC1_BASE			(REGS_AHB0_BASE + 0x10000)
+#define SUNXI_MMC2_BASE			(REGS_AHB0_BASE + 0x11000)
+#define SUNXI_MMC3_BASE			(REGS_AHB0_BASE + 0x12000)
+#define SUNXI_MMC_COMMON_BASE		(REGS_AHB0_BASE + 0x13000)
+
+#define SUNXI_SPI0_BASE			(REGS_AHB0_BASE + 0x1A000)
+#define SUNXI_SPI1_BASE			(REGS_AHB0_BASE + 0x1B000)
+#define SUNXI_SPI2_BASE			(REGS_AHB0_BASE + 0x1C000)
+#define SUNXI_SPI3_BASE			(REGS_AHB0_BASE + 0x1D000)
+
+#define SUNXI_GIC400_BASE		(REGS_AHB0_BASE + 0x40000)
+#define SUNXI_ARMA9_GIC_BASE		(REGS_AHB0_BASE + 0x41000)
+#define SUNXI_ARMA9_CPUIF_BASE		(REGS_AHB0_BASE + 0x42000)
+
+#define SUNXI_DRAM_COM_BASE		(REGS_AHB0_BASE + 0x62000)
+#define SUNXI_DRAM_CTL0_BASE		(REGS_AHB0_BASE + 0x63000)
+#define SUNXI_DRAM_CTL1_BASE		(REGS_AHB0_BASE + 0x64000)
+#define SUNXI_DRAM_PHY0_BASE		(REGS_AHB0_BASE + 0x65000)
+#define SUNXI_DRAM_PHY1_BASE		(REGS_AHB0_BASE + 0x66000)
+
+/* AHB1 Module */
+#define SUNXI_DMA_BASE			(REGS_AHB1_BASE + 0x002000)
+#define SUNXI_USBOTG_BASE		(REGS_AHB1_BASE + 0x100000)
+#define SUNXI_USBEHCI0_BASE		(REGS_AHB1_BASE + 0x200000)
+#define SUNXI_USBEHCI1_BASE		(REGS_AHB1_BASE + 0x201000)
+#define SUNXI_USBEHCI2_BASE		(REGS_AHB1_BASE + 0x202000)
+
+/* AHB2 Module */
+#define SUNXI_DE_SYS_BASE		(REGS_AHB2_BASE + 0x000000)
+#define SUNXI_DISP_SYS_BASE		(REGS_AHB2_BASE + 0x010000)
+#define SUNXI_DE_FE0_BASE		(REGS_AHB2_BASE + 0x100000)
+#define SUNXI_DE_FE1_BASE		(REGS_AHB2_BASE + 0x140000)
+#define SUNXI_DE_FE2_BASE		(REGS_AHB2_BASE + 0x180000)
+
+#define SUNXI_DE_BE0_BASE		(REGS_AHB2_BASE + 0x200000)
+#define SUNXI_DE_BE1_BASE		(REGS_AHB2_BASE + 0x240000)
+#define SUNXI_DE_BE2_BASE		(REGS_AHB2_BASE + 0x280000)
+
+#define SUNXI_DE_DEU0_BASE		(REGS_AHB2_BASE + 0x300000)
+#define SUNXI_DE_DEU1_BASE		(REGS_AHB2_BASE + 0x340000)
+#define SUNXI_DE_DRC0_BASE		(REGS_AHB2_BASE + 0x400000)
+#define SUNXI_DE_DRC1_BASE		(REGS_AHB2_BASE + 0x440000)
+
+#define SUNXI_LCD0_BASE			(REGS_AHB2_BASE + 0xC00000)
+#define SUNXI_LCD1_BASE			(REGS_AHB2_BASE + 0xC10000)
+#define SUNXI_LCD2_BASE			(REGS_AHB2_BASE + 0xC20000)
+#define SUNXI_MIPI_DSI0_BASE		(REGS_AHB2_BASE + 0xC40000)
+/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */
+#define SUNXI_MIPI_DSI0_DPHY_BASE	(REGS_AHB2_BASE + 0xC40100)
+#define SUNXI_HDMI_BASE			(REGS_AHB2_BASE + 0xD00000)
+
+/* APB0 Module */
+#define SUNXI_CCM_BASE			(REGS_APB0_BASE + 0x0000)
+#define SUNXI_CCMMODULE_BASE		(REGS_APB0_BASE + 0x0400)
+#define SUNXI_PIO_BASE			(REGS_APB0_BASE + 0x0800)
+#define SUNXI_TIMER_BASE		(REGS_APB0_BASE + 0x0C00)
+#define SUNXI_PWM_BASE			(REGS_APB0_BASE + 0x1400)
+#define SUNXI_LRADC_BASE		(REGS_APB0_BASE + 0x1800)
+
+/* APB1 Module */
+#define SUNXI_UART0_BASE		(REGS_APB1_BASE + 0x0000)
+#define SUNXI_UART1_BASE		(REGS_APB1_BASE + 0x0400)
+#define SUNXI_UART2_BASE		(REGS_APB1_BASE + 0x0800)
+#define SUNXI_UART3_BASE		(REGS_APB1_BASE + 0x0C00)
+#define SUNXI_UART4_BASE		(REGS_APB1_BASE + 0x1000)
+#define SUNXI_UART5_BASE		(REGS_APB1_BASE + 0x1400)
+#define SUNXI_TWI0_BASE			(REGS_APB1_BASE + 0x2800)
+#define SUNXI_TWI1_BASE			(REGS_APB1_BASE + 0x2C00)
+#define SUNXI_TWI2_BASE			(REGS_APB1_BASE + 0x3000)
+#define SUNXI_TWI3_BASE			(REGS_APB1_BASE + 0x3400)
+#define SUNXI_TWI4_BASE			(REGS_APB1_BASE + 0x3800)
+
+/* RCPUS Module */
+#define SUNXI_PRCM_BASE			(REGS_RCPUS_BASE + 0x1400)
+#define SUNXI_R_UART_BASE		(REGS_RCPUS_BASE + 0x2800)
+#define SUNXI_R_PIO_BASE		(REGS_RCPUS_BASE + 0x2c00)
+#define SUNXI_RSB_BASE			(REGS_RCPUS_BASE + 0x3400)
+
+/* Misc. */
+#define SUNXI_BROM_BASE			0xFFFF0000 /* 32K */
+#define SUNXI_CPU_CFG			(SUNXI_TIMER_BASE + 0x13c)
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif
+
+#endif /* _SUNXI_CPU_SUN9I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h b/arch/arm/include/asm/arch-sunxi/cpucfg.h
new file mode 100644
index 0000000..4aaebe0
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sunxi A31 CPUCFG register definition.
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com
+ */
+
+#ifndef _SUNXI_CPUCFG_H
+#define _SUNXI_CPUCFG_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#ifndef __ASSEMBLY__
+
+struct __packed sunxi_cpucfg_cpu {
+	u32 rst;		/* base + 0x0 */
+	u32 ctrl;		/* base + 0x4 */
+	u32 status;		/* base + 0x8 */
+	u8 res[0x34];		/* base + 0xc */
+};
+
+struct __packed sunxi_cpucfg_reg {
+	u8 res0[0x40];		/* 0x000 */
+	struct sunxi_cpucfg_cpu cpu[4];		/* 0x040 */
+	u8 res1[0x44];		/* 0x140 */
+	u32 gen_ctrl;		/* 0x184 */
+	u32 l2_status;		/* 0x188 */
+	u8 res2[0x4];		/* 0x18c */
+	u32 event_in;		/* 0x190 */
+	u8 res3[0xc];		/* 0x194 */
+	u32 super_standy_flag;	/* 0x1a0 */
+	u32 priv0;		/* 0x1a4 */
+	u32 priv1;		/* 0x1a8 */
+	u8 res4[0x4];		/* 0x1ac */
+	u32 cpu1_pwr_clamp;	/* 0x1b0 sun7i only */
+	u32 cpu1_pwroff;	/* 0x1b4 sun7i only */
+	u8 res5[0x2c];		/* 0x1b8 */
+	u32 dbg_ctrl1;		/* 0x1e4 */
+	u8 res6[0x18];		/* 0x1e8 */
+	u32 idle_cnt0_low;	/* 0x200 */
+	u32 idle_cnt0_high;	/* 0x204 */
+	u32 idle_cnt0_ctrl;	/* 0x208 */
+	u8 res8[0x4];		/* 0x20c */
+	u32 idle_cnt1_low;	/* 0x210 */
+	u32 idle_cnt1_high;	/* 0x214 */
+	u32 idle_cnt1_ctrl;	/* 0x218 */
+	u8 res9[0x4];		/* 0x21c */
+	u32 idle_cnt2_low;	/* 0x220 */
+	u32 idle_cnt2_high;	/* 0x224 */
+	u32 idle_cnt2_ctrl;	/* 0x228 */
+	u8 res10[0x4];		/* 0x22c */
+	u32 idle_cnt3_low;	/* 0x230 */
+	u32 idle_cnt3_high;	/* 0x234 */
+	u32 idle_cnt3_ctrl;	/* 0x238 */
+	u8 res11[0x4];		/* 0x23c */
+	u32 idle_cnt4_low;	/* 0x240 */
+	u32 idle_cnt4_high;	/* 0x244 */
+	u32 idle_cnt4_ctrl;	/* 0x248 */
+	u8 res12[0x34];		/* 0x24c */
+	u32 cnt64_ctrl;		/* 0x280 */
+	u32 cnt64_low;		/* 0x284 */
+	u32 cnt64_high;		/* 0x288 */
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* _SUNXI_CPUCFG_H */
diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h
new file mode 100644
index 0000000..525f9cb
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -0,0 +1,352 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sunxi platform display controller register and constant defines
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ */
+
+#ifndef _SUNXI_DISPLAY_H
+#define _SUNXI_DISPLAY_H
+
+struct sunxi_de_fe_reg {
+	u32 enable;			/* 0x000 */
+	u32 frame_ctrl;			/* 0x004 */
+	u32 bypass;			/* 0x008 */
+	u32 algorithm_sel;		/* 0x00c */
+	u32 line_int_ctrl;		/* 0x010 */
+	u8 res0[0x0c];			/* 0x014 */
+	u32 ch0_addr;			/* 0x020 */
+	u32 ch1_addr;			/* 0x024 */
+	u32 ch2_addr;			/* 0x028 */
+	u32 field_sequence;		/* 0x02c */
+	u32 ch0_offset;			/* 0x030 */
+	u32 ch1_offset;			/* 0x034 */
+	u32 ch2_offset;			/* 0x038 */
+	u8 res1[0x04];			/* 0x03c */
+	u32 ch0_stride;			/* 0x040 */
+	u32 ch1_stride;			/* 0x044 */
+	u32 ch2_stride;			/* 0x048 */
+	u32 input_fmt;			/* 0x04c */
+	u32 ch3_addr;			/* 0x050 */
+	u32 ch4_addr;			/* 0x054 */
+	u32 ch5_addr;			/* 0x058 */
+	u32 output_fmt;			/* 0x05c */
+	u32 int_enable;			/* 0x060 */
+	u32 int_status;			/* 0x064 */
+	u32 status;			/* 0x068 */
+	u8 res2[0x04];			/* 0x06c */
+	u32 csc_coef00;			/* 0x070 */
+	u32 csc_coef01;			/* 0x074 */
+	u32 csc_coef02;			/* 0x078 */
+	u32 csc_coef03;			/* 0x07c */
+	u32 csc_coef10;			/* 0x080 */
+	u32 csc_coef11;			/* 0x084 */
+	u32 csc_coef12;			/* 0x088 */
+	u32 csc_coef13;			/* 0x08c */
+	u32 csc_coef20;			/* 0x090 */
+	u32 csc_coef21;			/* 0x094 */
+	u32 csc_coef22;			/* 0x098 */
+	u32 csc_coef23;			/* 0x09c */
+	u32 deinterlace_ctrl;		/* 0x0a0 */
+	u32 deinterlace_diag;		/* 0x0a4 */
+	u32 deinterlace_tempdiff;	/* 0x0a8 */
+	u32 deinterlace_sawtooth;	/* 0x0ac */
+	u32 deinterlace_spatcomp;	/* 0x0b0 */
+	u32 deinterlace_burstlen;	/* 0x0b4 */
+	u32 deinterlace_preluma;	/* 0x0b8 */
+	u32 deinterlace_tile_addr;	/* 0x0bc */
+	u32 deinterlace_tile_stride;	/* 0x0c0 */
+	u8 res3[0x0c];			/* 0x0c4 */
+	u32 wb_stride_enable;		/* 0x0d0 */
+	u32 ch3_stride;			/* 0x0d4 */
+	u32 ch4_stride;			/* 0x0d8 */
+	u32 ch5_stride;			/* 0x0dc */
+	u32 fe_3d_ctrl;			/* 0x0e0 */
+	u32 fe_3d_ch0_addr;		/* 0x0e4 */
+	u32 fe_3d_ch1_addr;		/* 0x0e8 */
+	u32 fe_3d_ch2_addr;		/* 0x0ec */
+	u32 fe_3d_ch0_offset;		/* 0x0f0 */
+	u32 fe_3d_ch1_offset;		/* 0x0f4 */
+	u32 fe_3d_ch2_offset;		/* 0x0f8 */
+	u8 res4[0x04];			/* 0x0fc */
+	u32 ch0_insize;			/* 0x100 */
+	u32 ch0_outsize;		/* 0x104 */
+	u32 ch0_horzfact;		/* 0x108 */
+	u32 ch0_vertfact;		/* 0x10c */
+	u32 ch0_horzphase;		/* 0x110 */
+	u32 ch0_vertphase0;		/* 0x114 */
+	u32 ch0_vertphase1;		/* 0x118 */
+	u8 res5[0x04];			/* 0x11c */
+	u32 ch0_horztapoffset0;		/* 0x120 */
+	u32 ch0_horztapoffset1;		/* 0x124 */
+	u32 ch0_verttapoffset;		/* 0x128 */
+	u8 res6[0xd4];			/* 0x12c */
+	u32 ch1_insize;			/* 0x200 */
+	u32 ch1_outsize;		/* 0x204 */
+	u32 ch1_horzfact;		/* 0x208 */
+	u32 ch1_vertfact;		/* 0x20c */
+	u32 ch1_horzphase;		/* 0x210 */
+	u32 ch1_vertphase0;		/* 0x214 */
+	u32 ch1_vertphase1;		/* 0x218 */
+	u8 res7[0x04];			/* 0x21c */
+	u32 ch1_horztapoffset0;		/* 0x220 */
+	u32 ch1_horztapoffset1;		/* 0x224 */
+	u32 ch1_verttapoffset;		/* 0x228 */
+	u8 res8[0x1d4];			/* 0x22c */
+	u32 ch0_horzcoef0[32];		/* 0x400 */
+	u32 ch0_horzcoef1[32];		/* 0x480 */
+	u32 ch0_vertcoef[32];		/* 0x500 */
+	u8 res9[0x80];			/* 0x580 */
+	u32 ch1_horzcoef0[32];		/* 0x600 */
+	u32 ch1_horzcoef1[32];		/* 0x680 */
+	u32 ch1_vertcoef[32];		/* 0x700 */
+	u8 res10[0x280];		/* 0x780 */
+	u32 vpp_enable;			/* 0xa00 */
+	u32 vpp_dcti;			/* 0xa04 */
+	u32 vpp_lp1;			/* 0xa08 */
+	u32 vpp_lp2;			/* 0xa0c */
+	u32 vpp_wle;			/* 0xa10 */
+	u32 vpp_ble;			/* 0xa14 */
+};
+
+struct sunxi_de_be_reg {
+	u8 res0[0x800];			/* 0x000 */
+	u32 mode;			/* 0x800 */
+	u32 backcolor;			/* 0x804 */
+	u32 disp_size;			/* 0x808 */
+	u8 res1[0x4];			/* 0x80c */
+	u32 layer0_size;		/* 0x810 */
+	u32 layer1_size;		/* 0x814 */
+	u32 layer2_size;		/* 0x818 */
+	u32 layer3_size;		/* 0x81c */
+	u32 layer0_pos;			/* 0x820 */
+	u32 layer1_pos;			/* 0x824 */
+	u32 layer2_pos;			/* 0x828 */
+	u32 layer3_pos;			/* 0x82c */
+	u8 res2[0x10];			/* 0x830 */
+	u32 layer0_stride;		/* 0x840 */
+	u32 layer1_stride;		/* 0x844 */
+	u32 layer2_stride;		/* 0x848 */
+	u32 layer3_stride;		/* 0x84c */
+	u32 layer0_addr_low32b;		/* 0x850 */
+	u32 layer1_addr_low32b;		/* 0x854 */
+	u32 layer2_addr_low32b;		/* 0x858 */
+	u32 layer3_addr_low32b;		/* 0x85c */
+	u32 layer0_addr_high4b;		/* 0x860 */
+	u32 layer1_addr_high4b;		/* 0x864 */
+	u32 layer2_addr_high4b;		/* 0x868 */
+	u32 layer3_addr_high4b;		/* 0x86c */
+	u32 reg_ctrl;			/* 0x870 */
+	u8 res3[0xc];			/* 0x874 */
+	u32 color_key_max;		/* 0x880 */
+	u32 color_key_min;		/* 0x884 */
+	u32 color_key_config;		/* 0x888 */
+	u8 res4[0x4];			/* 0x88c */
+	u32 layer0_attr0_ctrl;		/* 0x890 */
+	u32 layer1_attr0_ctrl;		/* 0x894 */
+	u32 layer2_attr0_ctrl;		/* 0x898 */
+	u32 layer3_attr0_ctrl;		/* 0x89c */
+	u32 layer0_attr1_ctrl;		/* 0x8a0 */
+	u32 layer1_attr1_ctrl;		/* 0x8a4 */
+	u32 layer2_attr1_ctrl;		/* 0x8a8 */
+	u32 layer3_attr1_ctrl;		/* 0x8ac */
+	u8 res5[0x110];			/* 0x8b0 */
+	u32 output_color_ctrl;		/* 0x9c0 */
+	u8 res6[0xc];			/* 0x9c4 */
+	u32 output_color_coef[12];	/* 0x9d0 */
+};
+
+struct sunxi_hdmi_reg {
+	u32 version_id;			/* 0x000 */
+	u32 ctrl;			/* 0x004 */
+	u32 irq;			/* 0x008 */
+	u32 hpd;			/* 0x00c */
+	u32 video_ctrl;			/* 0x010 */
+	u32 video_size;			/* 0x014 */
+	u32 video_bp;			/* 0x018 */
+	u32 video_fp;			/* 0x01c */
+	u32 video_spw;			/* 0x020 */
+	u32 video_polarity;		/* 0x024 */
+	u8 res0[0x58];			/* 0x028 */
+	u8 avi_info_frame[0x14];	/* 0x080 */
+	u8 res1[0x4c];			/* 0x094 */
+	u32 qcp_packet0;		/* 0x0e0 */
+	u32 qcp_packet1;		/* 0x0e4 */
+	u8 res2[0x118];			/* 0x0e8 */
+	u32 pad_ctrl0;			/* 0x200 */
+	u32 pad_ctrl1;			/* 0x204 */
+	u32 pll_ctrl;			/* 0x208 */
+	u32 pll_dbg0;			/* 0x20c */
+	u32 pll_dbg1;			/* 0x210 */
+	u32 hpd_cec;			/* 0x214 */
+	u8 res3[0x28];			/* 0x218 */
+	u8 vendor_info_frame[0x14];	/* 0x240 */
+	u8 res4[0x9c];			/* 0x254 */
+	u32 pkt_ctrl0;			/* 0x2f0 */
+	u32 pkt_ctrl1;			/* 0x2f4 */
+	u8 res5[0x8];			/* 0x2f8 */
+	u32 unknown;			/* 0x300 */
+	u8 res6[0xc];			/* 0x304 */
+	u32 audio_sample_count;		/* 0x310 */
+	u8 res7[0xec];			/* 0x314 */
+	u32 audio_tx_fifo;		/* 0x400 */
+	u8 res8[0xfc];			/* 0x404 */
+#ifndef CONFIG_MACH_SUN6I
+	u32 ddc_ctrl;			/* 0x500 */
+	u32 ddc_addr;			/* 0x504 */
+	u32 ddc_int_mask;		/* 0x508 */
+	u32 ddc_int_status;		/* 0x50c */
+	u32 ddc_fifo_ctrl;		/* 0x510 */
+	u32 ddc_fifo_status;		/* 0x514 */
+	u32 ddc_fifo_data;		/* 0x518 */
+	u32 ddc_byte_count;		/* 0x51c */
+	u32 ddc_cmnd;			/* 0x520 */
+	u32 ddc_exreg;			/* 0x524 */
+	u32 ddc_clock;			/* 0x528 */
+	u8 res9[0x14];			/* 0x52c */
+	u32 ddc_line_ctrl;		/* 0x540 */
+#else
+	u32 ddc_ctrl;			/* 0x500 */
+	u32 ddc_exreg;			/* 0x504 */
+	u32 ddc_cmnd;			/* 0x508 */
+	u32 ddc_addr;			/* 0x50c */
+	u32 ddc_int_mask;		/* 0x510 */
+	u32 ddc_int_status;		/* 0x514 */
+	u32 ddc_fifo_ctrl;		/* 0x518 */
+	u32 ddc_fifo_status;		/* 0x51c */
+	u32 ddc_clock;			/* 0x520 */
+	u32 ddc_timeout;		/* 0x524 */
+	u8 res9[0x18];			/* 0x528 */
+	u32 ddc_dbg;			/* 0x540 */
+	u8 res10[0x3c];			/* 0x544 */
+	u32 ddc_fifo_data;		/* 0x580 */
+#endif
+};
+
+/*
+ * DE-FE register constants.
+ */
+#define SUNXI_DE_FE_WIDTH(x)			(((x) - 1) << 0)
+#define SUNXI_DE_FE_HEIGHT(y)			(((y) - 1) << 16)
+#define SUNXI_DE_FE_FACTOR_INT(n)		((n) << 16)
+#define SUNXI_DE_FE_ENABLE_EN			(1 << 0)
+#define SUNXI_DE_FE_FRAME_CTRL_REG_RDY		(1 << 0)
+#define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY		(1 << 1)
+#define SUNXI_DE_FE_FRAME_CTRL_FRM_START	(1 << 16)
+#define SUNXI_DE_FE_BYPASS_CSC_BYPASS		(1 << 1)
+#define SUNXI_DE_FE_INPUT_FMT_ARGB8888		0x00000151
+#define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888		0x00000002
+
+/*
+ * DE-BE register constants.
+ */
+#define SUNXI_DE_BE_WIDTH(x)			(((x) - 1) << 0)
+#define SUNXI_DE_BE_HEIGHT(y)			(((y) - 1) << 16)
+#define SUNXI_DE_BE_MODE_ENABLE			(1 << 0)
+#define SUNXI_DE_BE_MODE_START			(1 << 1)
+#define SUNXI_DE_BE_MODE_DEFLICKER_ENABLE	(1 << 4)
+#define SUNXI_DE_BE_MODE_LAYER0_ENABLE		(1 << 8)
+#define SUNXI_DE_BE_MODE_INTERLACE_ENABLE	(1 << 28)
+#define SUNXI_DE_BE_LAYER_STRIDE(x)		((x) << 5)
+#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS		(1 << 0)
+#define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0		0x00000002
+#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888	(0x09 << 8)
+#define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE	1
+
+/*
+ * HDMI register constants.
+ */
+#define SUNXI_HDMI_X(x)				(((x) - 1) << 0)
+#define SUNXI_HDMI_Y(y)				(((y) - 1) << 16)
+#define SUNXI_HDMI_CTRL_ENABLE			(1 << 31)
+#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF		(1 << 0)
+#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF		(1 << 1)
+#define SUNXI_HDMI_IRQ_STATUS_BITS		0x73
+#define SUNXI_HDMI_HPD_DETECT			(1 << 0)
+#define SUNXI_HDMI_VIDEO_CTRL_ENABLE		(1 << 31)
+#define SUNXI_HDMI_VIDEO_CTRL_HDMI		(1 << 30)
+#define SUNXI_HDMI_VIDEO_POL_HOR		(1 << 0)
+#define SUNXI_HDMI_VIDEO_POL_VER		(1 << 1)
+#define SUNXI_HDMI_VIDEO_POL_TX_CLK		(0x3e0 << 16)
+#define SUNXI_HDMI_QCP_PACKET0			3
+#define SUNXI_HDMI_QCP_PACKET1			0
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_PAD_CTRL0_HDP		0x7e80000f
+#define SUNXI_HDMI_PAD_CTRL0_RUN		0x7e8000ff
+#else
+#define SUNXI_HDMI_PAD_CTRL0_HDP		0xfe800000
+#define SUNXI_HDMI_PAD_CTRL0_RUN		0xfe800000
+#endif
+
+#ifdef CONFIG_MACH_SUN4I
+#define SUNXI_HDMI_PAD_CTRL1			0x00d8c820
+#elif defined CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_PAD_CTRL1			0x01ded030
+#else
+#define SUNXI_HDMI_PAD_CTRL1			0x00d8c830
+#endif
+#define SUNXI_HDMI_PAD_CTRL1_HALVE		(1 << 6)
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_PLL_CTRL			0xba48a308
+#define SUNXI_HDMI_PLL_CTRL_DIV(n)		(((n) - 1) << 4)
+#else
+#define SUNXI_HDMI_PLL_CTRL			0xfa4ef708
+#define SUNXI_HDMI_PLL_CTRL_DIV(n)		((n) << 4)
+#endif
+#define SUNXI_HDMI_PLL_CTRL_DIV_MASK		(0xf << 4)
+
+#define SUNXI_HDMI_PLL_DBG0_PLL3		(0 << 21)
+#define SUNXI_HDMI_PLL_DBG0_PLL7		(1 << 21)
+
+#define SUNXI_HDMI_PKT_CTRL0			0x00000f21
+#define SUNXI_HDMI_PKT_CTRL1			0x0000000f
+#define SUNXI_HDMI_UNKNOWN_INPUT_SYNC		0x08000000
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HMDI_DDC_CTRL_ENABLE		(1 << 0)
+#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE		(1 << 4)
+#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE		(1 << 6)
+#define SUNXI_HMDI_DDC_CTRL_START		(1 << 27)
+#define SUNXI_HMDI_DDC_CTRL_RESET		(1 << 31)
+#else
+#define SUNXI_HMDI_DDC_CTRL_RESET		(1 << 0)
+/* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */
+#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE		0
+#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE		0
+#define SUNXI_HMDI_DDC_CTRL_START		(1 << 30)
+#define SUNXI_HMDI_DDC_CTRL_ENABLE		(1 << 31)
+#endif
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR		(0xa0 << 0)
+#else
+#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR		(0x50 << 0)
+#endif
+#define SUNXI_HMDI_DDC_ADDR_OFFSET(n)		(((n) & 0xff) << 8)
+#define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR		(0x60 << 16)
+#define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n)	((n) << 24)
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR		(1 << 15)
+#else
+#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR		(1 << 31)
+#endif
+
+#define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ	6
+#define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ	7
+
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_HDMI_DDC_CLOCK			0x61
+#else
+/* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */
+#define SUNXI_HDMI_DDC_CLOCK			0x0d
+#endif
+
+#define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE	(1 << 8)
+#define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE	(1 << 9)
+
+int sunxi_simplefb_setup(void *blob);
+
+#endif /* _SUNXI_DISPLAY_H */
diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h
new file mode 100644
index 0000000..7202d27
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/display2.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sunxi platform display controller register and constant defines
+ *
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ *
+ * Based on out of tree Linux DRM driver defines:
+ * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
+ * Copyright (c) 2016 Allwinnertech Co., Ltd.
+ */
+
+#ifndef _SUNXI_DISPLAY2_H
+#define _SUNXI_DISPLAY2_H
+
+/* internal clock settings */
+struct de_clk {
+	u32 gate_cfg;
+	u32 bus_cfg;
+	u32 rst_cfg;
+	u32 div_cfg;
+	u32 sel_cfg;
+};
+
+/* global control */
+struct de_glb {
+	u32 ctl;
+	u32 status;
+	u32 dbuff;
+	u32 size;
+};
+
+/* alpha blending */
+struct de_bld {
+	u32 fcolor_ctl;
+	struct {
+		u32 fcolor;
+		u32 insize;
+		u32 offset;
+		u32 dum;
+	} attr[4];
+	u32 dum0[15];
+	u32 route;
+	u32 premultiply;
+	u32 bkcolor;
+	u32 output_size;
+	u32 bld_mode[4];
+	u32 dum1[4];
+	u32 ck_ctl;
+	u32 ck_cfg;
+	u32 dum2[2];
+	u32 ck_max[4];
+	u32 dum3[4];
+	u32 ck_min[4];
+	u32 dum4[3];
+	u32 out_ctl;
+};
+
+/* VI channel */
+struct de_vi {
+	struct {
+		u32 attr;
+		u32 size;
+		u32 coord;
+		u32 pitch[3];
+		u32 top_laddr[3];
+		u32 bot_laddr[3];
+	} cfg[4];
+	u32 fcolor[4];
+	u32 top_haddr[3];
+	u32 bot_haddr[3];
+	u32 ovl_size[2];
+	u32 hori[2];
+	u32 vert[2];
+};
+
+struct de_ui {
+	struct {
+		u32 attr;
+		u32 size;
+		u32 coord;
+		u32 pitch;
+		u32 top_laddr;
+		u32 bot_laddr;
+		u32 fcolor;
+		u32 dum;
+	} cfg[4];
+	u32 top_haddr;
+	u32 bot_haddr;
+	u32 ovl_size;
+};
+
+struct de_csc {
+	u32 csc_ctl;
+	u8 res[0xc];
+	u32 coef11;
+	u32 coef12;
+	u32 coef13;
+	u32 coef14;
+	u32 coef21;
+	u32 coef22;
+	u32 coef23;
+	u32 coef24;
+	u32 coef31;
+	u32 coef32;
+	u32 coef33;
+	u32 coef34;
+};
+
+/*
+ * DE register constants.
+ */
+#define SUNXI_DE2_MUX0_BASE			(SUNXI_DE2_BASE + 0x100000)
+#define SUNXI_DE2_MUX1_BASE			(SUNXI_DE2_BASE + 0x200000)
+
+#define SUNXI_DE2_MUX_GLB_REGS			0x00000
+#define SUNXI_DE2_MUX_BLD_REGS			0x01000
+#define SUNXI_DE2_MUX_CHAN_REGS			0x02000
+#define SUNXI_DE2_MUX_CHAN_SZ			0x1000
+#define SUNXI_DE2_MUX_VSU_REGS			0x20000
+#define SUNXI_DE2_MUX_GSU1_REGS			0x30000
+#define SUNXI_DE2_MUX_GSU2_REGS			0x40000
+#define SUNXI_DE2_MUX_GSU3_REGS			0x50000
+#define SUNXI_DE2_MUX_FCE_REGS			0xa0000
+#define SUNXI_DE2_MUX_BWS_REGS			0xa2000
+#define SUNXI_DE2_MUX_LTI_REGS			0xa4000
+#define SUNXI_DE2_MUX_PEAK_REGS			0xa6000
+#define SUNXI_DE2_MUX_ASE_REGS			0xa8000
+#define SUNXI_DE2_MUX_FCC_REGS			0xaa000
+#define SUNXI_DE2_MUX_DCSC_REGS			0xb0000
+
+#define SUNXI_DE2_FORMAT_XRGB_8888		4
+#define SUNXI_DE2_FORMAT_RGB_565		10
+
+#define SUNXI_DE2_MUX_GLB_CTL_EN		(1 << 0)
+#define SUNXI_DE2_UI_CFG_ATTR_EN		(1 << 0)
+#define SUNXI_DE2_UI_CFG_ATTR_FMT(f)		((f & 0xf) << 8)
+
+#define SUNXI_DE2_WH(w, h)			(((h - 1) << 16) | (w - 1))
+
+#endif /* _SUNXI_DISPLAY2_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dma.h b/arch/arm/include/asm/arch-sunxi/dma.h
new file mode 100644
index 0000000..bd4c84f
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dma.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
+ */
+
+#ifndef _SUNXI_DMA_H
+#define _SUNXI_DMA_H
+
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+#include <asm/arch/dma_sun4i.h>
+#else
+#error "DMA definition not available for this architecture"
+#endif
+
+#endif /* _SUNXI_DMA_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dma_sun4i.h b/arch/arm/include/asm/arch-sunxi/dma_sun4i.h
new file mode 100644
index 0000000..309dc4f
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dma_sun4i.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
+ */
+
+#ifndef _SUNXI_DMA_SUN4I_H
+#define _SUNXI_DMA_SUN4I_H
+
+struct sunxi_dma_cfg
+{
+	u32 ctl;		/* 0x00 Control */
+	u32 src_addr;		/* 0x04 Source address */
+	u32 dst_addr;		/* 0x08 Destination address */
+	u32 bc;			/* 0x0C Byte counter */
+	u32 res0[2];
+	u32 ddma_para;		/* 0x18 extra parameter (dedicated DMA only) */
+	u32 res1;
+};
+
+struct sunxi_dma
+{
+	u32 irq_en;			/* 0x000 IRQ enable */
+	u32 irq_pend;			/* 0x004 IRQ pending */
+	u32 auto_gate;			/* 0x008 auto gating */
+	u32 res0[61];
+	struct sunxi_dma_cfg ndma[8];	/* 0x100 Normal DMA */
+	u32 res1[64];
+	struct sunxi_dma_cfg ddma[8];	/* 0x300 Dedicated DMA */
+};
+
+enum ddma_drq_type {
+	DDMA_DST_DRQ_SRAM = 0,
+	DDMA_SRC_DRQ_SRAM = 0,
+	DDMA_DST_DRQ_SDRAM = 1,
+	DDMA_SRC_DRQ_SDRAM = 1,
+	DDMA_DST_DRQ_PATA = 2,
+	DDMA_SRC_DRQ_PATA = 2,
+	DDMA_DST_DRQ_NAND = 3,
+	DDMA_SRC_DRQ_NAND = 3,
+	DDMA_DST_DRQ_USB0 = 4,
+	DDMA_SRC_DRQ_USB0 = 4,
+	DDMA_DST_DRQ_ETHERNET_MAC_TX = 6,
+	DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7,
+	DDMA_DST_DRQ_SPI1_TX = 8,
+	DDMA_SRC_DRQ_SPI1_RX = 9,
+	DDMA_DST_DRQ_SECURITY_SYS_TX = 10,
+	DDMA_SRC_DRQ_SECURITY_SYS_RX = 11,
+	DDMA_DST_DRQ_TCON0 = 14,
+	DDMA_DST_DRQ_TCON1 = 15,
+	DDMA_DST_DRQ_MSC = 23,
+	DDMA_SRC_DRQ_MSC = 23,
+	DDMA_DST_DRQ_SPI0_TX = 26,
+	DDMA_SRC_DRQ_SPI0_RX = 27,
+	DDMA_DST_DRQ_SPI2_TX = 28,
+	DDMA_SRC_DRQ_SPI2_RX = 29,
+	DDMA_DST_DRQ_SPI3_TX = 30,
+	DDMA_SRC_DRQ_SPI3_RX = 31,
+};
+
+#define SUNXI_DMA_CTL_SRC_DRQ(a)		((a) & 0x1f)
+#define SUNXI_DMA_CTL_MODE_IO			(1 << 5)
+#define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32		(2 << 9)
+#define SUNXI_DMA_CTL_DST_DRQ(a)		(((a) & 0x1f) << 16)
+#define SUNXI_DMA_CTL_DST_DATA_WIDTH_32		(2 << 25)
+#define SUNXI_DMA_CTL_TRIGGER			(1 << 31)
+
+#endif /* _SUNXI_DMA_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h
new file mode 100644
index 0000000..8002b7e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Sunxi platform dram register definition.
+ */
+
+#ifndef _SUNXI_DRAM_H
+#define _SUNXI_DRAM_H
+
+#include <asm/io.h>
+#include <linux/types.h>
+
+/* dram regs definition */
+#if defined(CONFIG_MACH_SUN6I)
+#include <asm/arch/dram_sun6i.h>
+#elif defined(CONFIG_MACH_SUN8I_A23)
+#include <asm/arch/dram_sun8i_a23.h>
+#elif defined(CONFIG_MACH_SUN8I_A33)
+#include <asm/arch/dram_sun8i_a33.h>
+#elif defined(CONFIG_MACH_SUN8I_A83T)
+#include <asm/arch/dram_sun8i_a83t.h>
+#elif defined(CONFIG_SUNXI_DRAM_DW)
+#include <asm/arch/dram_sunxi_dw.h>
+#elif defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/dram_sun9i.h>
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#include <asm/arch/dram_sun50i_h6.h>
+#else
+#include <asm/arch/dram_sun4i.h>
+#endif
+
+unsigned long sunxi_dram_init(void);
+void mctl_await_completion(u32 *reg, u32 mask, u32 val);
+bool mctl_mem_matches(u32 offset);
+
+#endif /* _SUNXI_DRAM_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h
new file mode 100644
index 0000000..69c6600
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Sunxi platform dram register definition.
+ */
+
+#ifndef _SUNXI_DRAM_SUN4I_H
+#define _SUNXI_DRAM_SUN4I_H
+
+struct sunxi_dram_reg {
+	u32 ccr;		/* 0x00 controller configuration register */
+	u32 dcr;		/* 0x04 dram configuration register */
+	u32 iocr;		/* 0x08 i/o configuration register */
+	u32 csr;		/* 0x0c controller status register */
+	u32 drr;		/* 0x10 dram refresh register */
+	u32 tpr0;		/* 0x14 dram timing parameters register 0 */
+	u32 tpr1;		/* 0x18 dram timing parameters register 1 */
+	u32 tpr2;		/* 0x1c dram timing parameters register 2 */
+	u32 gdllcr;		/* 0x20 global dll control register */
+	u8 res0[0x28];
+	u32 rslr0;		/* 0x4c rank system latency register */
+	u32 rslr1;		/* 0x50 rank system latency register */
+	u8 res1[0x8];
+	u32 rdgr0;		/* 0x5c rank dqs gating register */
+	u32 rdgr1;		/* 0x60 rank dqs gating register */
+	u8 res2[0x34];
+	u32 odtcr;		/* 0x98 odt configuration register */
+	u32 dtr0;		/* 0x9c data training register 0 */
+	u32 dtr1;		/* 0xa0 data training register 1 */
+	u32 dtar;		/* 0xa4 data training address register */
+	u32 zqcr0;		/* 0xa8 zq control register 0 */
+	u32 zqcr1;		/* 0xac zq control register 1 */
+	u32 zqsr;		/* 0xb0 zq status register */
+	u32 idcr;		/* 0xb4 initializaton delay configure reg */
+	u8 res3[0x138];
+	u32 mr;			/* 0x1f0 mode register */
+	u32 emr;		/* 0x1f4 extended mode register */
+	u32 emr2;		/* 0x1f8 extended mode register */
+	u32 emr3;		/* 0x1fc extended mode register */
+	u32 dllctr;		/* 0x200 dll control register */
+	u32 dllcr[5];		/* 0x204 dll control register 0(byte 0) */
+	/* 0x208 dll control register 1(byte 1) */
+	/* 0x20c dll control register 2(byte 2) */
+	/* 0x210 dll control register 3(byte 3) */
+	/* 0x214 dll control register 4(byte 4) */
+	u32 dqtr0;		/* 0x218 dq timing register */
+	u32 dqtr1;		/* 0x21c dq timing register */
+	u32 dqtr2;		/* 0x220 dq timing register */
+	u32 dqtr3;		/* 0x224 dq timing register */
+	u32 dqstr;		/* 0x228 dqs timing register */
+	u32 dqsbtr;		/* 0x22c dqsb timing register */
+	u32 mcr;		/* 0x230 mode configure register */
+	u8 res[0x8];
+	u32 ppwrsctl;		/* 0x23c pad power save control */
+	u32 apr;		/* 0x240 arbiter period register */
+	u32 pldtr;		/* 0x244 priority level data threshold reg */
+	u8 res5[0x8];
+	u32 hpcr[32];		/* 0x250 host port configure register */
+	u8 res6[0x10];
+	u32 csel;		/* 0x2e0 controller select register */
+};
+
+struct dram_para {
+	u32 clock;
+	u32 mbus_clock;
+	u32 type;
+	u32 rank_num;
+	u32 density;
+	u32 io_width;
+	u32 bus_width;
+	u32 cas;
+	u32 zq;
+	u32 odt_en;
+	u32 size; /* For compat with dram.c files from u-boot-sunxi, unused */
+	u32 tpr0;
+	u32 tpr1;
+	u32 tpr2;
+	u32 tpr3;
+	u32 tpr4;
+	u32 tpr5;
+	u32 emr1;
+	u32 emr2;
+	u32 emr3;
+	u32 dqs_gating_delay;
+	u32 active_windowing;
+};
+
+#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
+#define DRAM_CCR_DQS_GATE (0x1 << 14)
+#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17)
+#define DRAM_CCR_ITM_OFF (0x1 << 28)
+#define DRAM_CCR_DATA_TRAINING (0x1 << 30)
+#define DRAM_CCR_INIT (0x1 << 31)
+
+#define DRAM_MEMORY_TYPE_DDR1 1
+#define DRAM_MEMORY_TYPE_DDR2 2
+#define DRAM_MEMORY_TYPE_DDR3 3
+#define DRAM_MEMORY_TYPE_LPDDR2 4
+#define DRAM_MEMORY_TYPE_LPDDR 5
+#define DRAM_DCR_TYPE (0x1 << 0)
+#define DRAM_DCR_TYPE_DDR2 0x0
+#define DRAM_DCR_TYPE_DDR3 0x1
+#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1)
+#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3)
+#define DRAM_DCR_IO_WIDTH_8BIT 0x0
+#define DRAM_DCR_IO_WIDTH_16BIT 0x1
+#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3)
+#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7)
+#define DRAM_DCR_CHIP_DENSITY_256M 0x0
+#define DRAM_DCR_CHIP_DENSITY_512M 0x1
+#define DRAM_DCR_CHIP_DENSITY_1024M 0x2
+#define DRAM_DCR_CHIP_DENSITY_2048M 0x3
+#define DRAM_DCR_CHIP_DENSITY_4096M 0x4
+#define DRAM_DCR_CHIP_DENSITY_8192M 0x5
+#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6)
+#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7)
+#define DRAM_DCR_BUS_WIDTH_32BIT 0x3
+#define DRAM_DCR_BUS_WIDTH_16BIT 0x1
+#define DRAM_DCR_BUS_WIDTH_8BIT 0x0
+#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
+#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
+#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
+#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13)
+#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3)
+#define DRAM_DCR_MODE_SEQ 0x0
+#define DRAM_DCR_MODE_INTERLEAVE 0x1
+
+#define DRAM_CSR_DTERR  (0x1 << 20)
+#define DRAM_CSR_DTIERR (0x1 << 21)
+#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
+
+#define DRAM_DRR_TRFC(n) ((n) & 0xff)
+#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)
+#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24)
+
+#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
+#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
+#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
+#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3)
+#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4)
+#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3)
+#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6)
+#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3)
+#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8)
+#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7)
+#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11)
+#define DRAM_MCR_RESET (0x1 << 12)
+#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13)
+#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3)
+#define DRAM_MCR_DCLK_OUT (0x1 << 16)
+
+#define DRAM_DLLCR_NRESET (0x1 << 30)
+#define DRAM_DLLCR_DISABLE (0x1 << 31)
+
+#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
+#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
+#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */
+#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */
+
+#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */
+
+#define DRAM_IOCR_ODT_EN ((3 << 30) | (3 << 0))
+
+#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0)
+#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7)
+#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4)
+#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7)
+#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9)
+#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7)
+#define DRAM_MR_POWER_DOWN (0x1 << 12)
+
+#define DRAM_CSEL_MAGIC 0x16237495
+
+unsigned long dramc_init(struct dram_para *para);
+
+#endif /* _SUNXI_DRAM_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
new file mode 100644
index 0000000..0a1da02
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
@@ -0,0 +1,332 @@
+/*
+ * H6 dram controller register and constant defines
+ *
+ * (C) Copyright 2017  Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN50I_H6_H
+#define _SUNXI_DRAM_SUN50I_H6_H
+
+#include <stdbool.h>
+
+enum sunxi_dram_type {
+	SUNXI_DRAM_TYPE_DDR3 = 3,
+	SUNXI_DRAM_TYPE_DDR4,
+	SUNXI_DRAM_TYPE_LPDDR2 = 6,
+	SUNXI_DRAM_TYPE_LPDDR3,
+};
+
+static inline bool sunxi_dram_is_lpddr(int type)
+{
+	return type >= SUNXI_DRAM_TYPE_LPDDR2;
+}
+
+/*
+ * The following information is mainly retrieved by disassembly and some FPGA
+ * test code of sun50iw3 platform.
+ */
+struct sunxi_mctl_com_reg {
+	u32 cr;			/* 0x000 control register */
+	u8 reserved_0x004[4];	/* 0x004 */
+	u32 unk_0x008;		/* 0x008 */
+	u32 tmr;		/* 0x00c timer register */
+	u8 reserved_0x010[4];	/* 0x010 */
+	u32 unk_0x014;		/* 0x014 */
+	u8 reserved_0x018[8];	/* 0x018 */
+	u32 maer0;		/* 0x020 master enable register 0 */
+	u32 maer1;		/* 0x024 master enable register 1 */
+	u32 maer2;		/* 0x028 master enable register 2 */
+	u8 reserved_0x02c[468];	/* 0x02c */
+	u32 bwcr;		/* 0x200 bandwidth control register */
+	u8 reserved_0x204[12];	/* 0x204 */
+	/*
+	 * The last master configured by BSP libdram is at 0x49x, so the
+	 * size of this struct array is set to 41 (0x29) now.
+	 */
+	struct {
+		u32 cfg0;		/* 0x0 */
+		u32 cfg1;		/* 0x4 */
+		u8 reserved_0x8[8];	/* 0x8 */
+	} master[41];		/* 0x210 + index * 0x10 */
+};
+check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498);
+
+/*
+ * The following register information are retrieved from some similar DRAM
+ * controllers, including the DRAM controllers in Allwinner A23/A80 SoCs,
+ * Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs.
+ *
+ * The DRAM controller in Allwinner A23/A80 SoCs and NXP i.MX7 SoCs seems
+ * to be older than the one in Allwinner H6, as the DRAMTMG9 register
+ * is missing in these SoCs. (From the product specifications of these
+ * SoCs they're not capable of DDR4)
+ *
+ * Information sources:
+ * - dram_sun9i.h and dram_sun8i_a23.h in the same directory.
+ * - sdram_rk3328.h from the RK3328 TPL DRAM patchset
+ * - i.MX 7Solo Applications Processor Reference Manual (IMX7SRM)
+ * - Zynq UltraScale+ MPSoC Register Reference (UG1087)
+ */
+struct sunxi_mctl_ctl_reg {
+	u32 mstr;		/* 0x000 */
+	u32 statr;		/* 0x004 unused */
+	u32 mstr1;		/* 0x008 unused */
+	u32 unk_0x00c;		/* 0x00c */
+	u32 mrctrl0;		/* 0x010 unused */
+	u32 mrctrl1;		/* 0x014 unused */
+	u32 mrstatr;		/* 0x018 unused */
+	u32 mrctrl2;		/* 0x01c unused */
+	u32 derateen;		/* 0x020 unused */
+	u32 derateint;		/* 0x024 unused */
+	u8 reserved_0x028[8];	/* 0x028 */
+	u32 pwrctl;		/* 0x030 unused */
+	u32 pwrtmg;		/* 0x034 unused */
+	u32 hwlpctl;		/* 0x038 unused */
+	u8 reserved_0x03c[20];	/* 0x03c */
+	u32 rfshctl0;		/* 0x050 unused */
+	u32 rfshctl1;		/* 0x054 unused */
+	u8 reserved_0x058[8];	/* 0x05c */
+	u32 rfshctl3;		/* 0x060 */
+	u32 rfshtmg;		/* 0x064 */
+	u8 reserved_0x068[104];	/* 0x068 reserved for ECC&CRC (from ZynqMP) */
+	u32 init[8];		/* 0x0d0 */
+	u32 dimmctl;		/* 0x0f0 unused */
+	u32 rankctl;		/* 0x0f4 */
+	u8 reserved_0x0f8[8];	/* 0x0f8 */
+	u32 dramtmg[17];	/* 0x100 */
+	u8 reserved_0x144[60];	/* 0x144 */
+	u32 zqctl[3];		/* 0x180 */
+	u32 zqstat;		/* 0x18c unused */
+	u32 dfitmg0;		/* 0x190 */
+	u32 dfitmg1;		/* 0x194 */
+	u32 dfilpcfg[2];	/* 0x198 unused */
+	u32 dfiupd[3];		/* 0x1a0 */
+	u32 reserved_0x1ac;	/* 0x1ac */
+	u32 dfimisc;		/* 0x1b0 */
+	u32 dfitmg2;		/* 0x1b4 unused, may not exist */
+	u8 reserved_0x1b8[8];	/* 0x1b8 */
+	u32 dbictl;		/* 0x1c0 */
+	u8 reserved_0x1c4[60];	/* 0x1c4 */
+	u32 addrmap[12];	/* 0x200 */
+	u8 reserved_0x230[16];	/* 0x230 */
+	u32 odtcfg;		/* 0x240 */
+	u32 odtmap;		/* 0x244 */
+	u8 reserved_0x248[8];	/* 0x248 */
+	u32 sched[2];		/* 0x250 */
+	u8 reserved_0x258[180];	/* 0x258 */
+	u32 dbgcmd;		/* 0x30c unused */
+	u32 dbgstat;		/* 0x310 unused */
+	u8 reserved_0x314[12];	/* 0x314 */
+	u32 swctl;		/* 0x320 */
+	u32 swstat;		/* 0x324 */
+};
+check_member(sunxi_mctl_ctl_reg, swstat, 0x324);
+
+#define MSTR_DEVICETYPE_DDR3	BIT(0)
+#define MSTR_DEVICETYPE_LPDDR2	BIT(2)
+#define MSTR_DEVICETYPE_LPDDR3	BIT(3)
+#define MSTR_DEVICETYPE_DDR4	BIT(4)
+#define MSTR_DEVICETYPE_MASK	GENMASK(5, 0)
+#define MSTR_2TMODE		BIT(10)
+#define MSTR_BUSWIDTH_FULL	(0 << 12)
+#define MSTR_BUSWIDTH_HALF	(1 << 12)
+#define MSTR_ACTIVE_RANKS(x)	(((x == 2) ? 3 : 1) << 24)
+#define MSTR_BURST_LENGTH(x)	(((x) >> 1) << 16)
+
+/*
+ * The following register information is based on Zynq UltraScale+
+ * MPSoC Register Reference, as it's the currently only known
+ * DDR PHY similar to the one used in H6; however although the
+ * map is similar, the bit fields definitions are different.
+ *
+ * Other DesignWare DDR PHY's have similar register names, but the
+ * offset and definitions are both different.
+ */
+struct sunxi_mctl_phy_reg {
+	u32 ver;		/* 0x000 guess based on similar PHYs */
+	u32 pir;		/* 0x004 */
+	u8 reserved_0x008[8];	/* 0x008 */
+	/*
+	 * The ZynqMP manual didn't document PGCR1, however this register
+	 * exists on H6 and referenced by libdram.
+	 */
+	u32 pgcr[8];		/* 0x010 */
+	/*
+	 * By comparing the hardware and the ZynqMP manual, the PGSR seems
+	 * to start at 0x34 on H6.
+	 */
+	u8 reserved_0x030[4];	/* 0x030 */
+	u32 pgsr[3];		/* 0x034 */
+	u32 ptr[7];		/* 0x040 */
+	/*
+	 * According to ZynqMP reference there's PLLCR0~6 in this area,
+	 * but they're tagged "Type B PLL Only" and H6 seems to have
+	 * no them.
+	 * 0x080 is not present in ZynqMP reference but it seems to be
+	 * present on H6.
+	 */
+	u8 reserved_0x05c[36];	/* 0x05c */
+	u32 unk_0x080;		/* 0x080 */
+	u8 reserved_0x084[4];	/* 0x084 */
+	u32 dxccr;		/* 0x088 */
+	u8 reserved_0x08c[4];	/* 0x08c */
+	u32 dsgcr;		/* 0x090 */
+	u8 reserved_0x094[4];	/* 0x094 */
+	u32 odtcr;		/* 0x098 */
+	u8 reserved_0x09c[4];	/* 0x09c */
+	u32 aacr;		/* 0x0a0 */
+	u8 reserved_0x0a4[32];	/* 0x0a4 */
+	u32 gpr1;		/* 0x0c4 */
+	u8 reserved_0x0c8[56];	/* 0x0c8 */
+	u32 dcr;		/* 0x100 */
+	u8 reserved_0x104[12];	/* 0x104 */
+	u32 dtpr[7];		/* 0x110 */
+	u8 reserved_0x12c[20];	/* 0x12c */
+	u32 rdimmgcr[3];	/* 0x140 */
+	u8 reserved_0x14c[4];	/* 0x14c */
+	u32 rdimmcr[5];		/* 0x150 */
+	u8 reserved_0x164[4];	/* 0x164 */
+	u32 schcr[2];		/* 0x168 */
+	u8 reserved_0x170[16];	/* 0x170 */
+	/*
+	 * The ZynqMP manual documents MR0~7, 11~14 and 22.
+	 */
+	u32 mr[23];		/* 0x180 */
+	u8 reserved_0x1dc[36];	/* 0x1dc */
+	u32 dtcr[2];		/* 0x200 */
+	u32 dtar[3];		/* 0x208 */
+	u8 reserved_0x214[4];	/* 0x214 */
+	u32 dtdr[2];		/* 0x218 */
+	u8 reserved_0x220[16];	/* 0x220 */
+	u32 dtedr0;		/* 0x230 */
+	u32 dtedr1;		/* 0x234 */
+	u32 dtedr2;		/* 0x238 */
+	u32 vtdr;		/* 0x23c */
+	u32 catr[2];		/* 0x240 */
+	u8 reserved_0x248[8];
+	u32 dqsdr[3];		/* 0x250 */
+	u32 dtedr3;		/* 0x25c */
+	u8 reserved_0x260[160];	/* 0x260 */
+	u32 dcuar;		/* 0x300 */
+	u32 dcudr;		/* 0x304 */
+	u32 dcurr;		/* 0x308 */
+	u32 dculr;		/* 0x30c */
+	u32 dcugcr;		/* 0x310 */
+	u32 dcutpr;		/* 0x314 */
+	u32 dcusr[2];		/* 0x318 */
+	u8 reserved_0x320[444];	/* 0x320 */
+	u32 rankidr;		/* 0x4dc */
+	u32 riocr[6];		/* 0x4e0 */
+	u8 reserved_0x4f8[8];	/* 0x4f8 */
+	u32 aciocr[6];		/* 0x500 */
+	u8 reserved_0x518[8];	/* 0x518 */
+	u32 iovcr[2];		/* 0x520 */
+	u32 vtcr[2];		/* 0x528 */
+	u8 reserved_0x530[16];	/* 0x530 */
+	u32 acbdlr[17];		/* 0x540 */
+	u32 aclcdlr;		/* 0x584 */
+	u8 reserved_0x588[24];	/* 0x588 */
+	u32 acmdlr[2];		/* 0x5a0 */
+	u8 reserved_0x5a8[216];	/* 0x5a8 */
+	struct {
+		u32 zqcr;	/* 0x00 only the first one valid */
+		u32 zqpr[2];	/* 0x04 */
+		u32 zqdr[2];	/* 0x0c */
+		u32 zqor[2];	/* 0x14 */
+		u32 zqsr;	/* 0x1c */
+	} zq[2];		/* 0x680, 0x6a0 */
+	u8 reserved_0x6c0[64];	/* 0x6c0 */
+	struct {
+		u32 gcr[7];		/* 0x00 */
+		u8 reserved_0x1c[36];	/* 0x1c */
+		u32 bdlr0;		/* 0x40 */
+		u32 bdlr1;		/* 0x44 */
+		u32 bdlr2;		/* 0x48 */
+		u8 reserved_0x4c[4];	/* 0x4c */
+		u32 bdlr3;		/* 0x50 */
+		u32 bdlr4;		/* 0x54 */
+		u32 bdlr5;		/* 0x58 */
+		u8 reserved_0x5c[4];	/* 0x5c */
+		u32 bdlr6;		/* 0x60 */
+		u8 reserved_0x64[28];	/* 0x64 */
+		u32 lcdlr[6];		/* 0x80 */
+		u8 reserved_0x98[8];	/* 0x98 */
+		u32 mdlr[2];		/* 0xa0 */
+		u8 reserved_0xa8[24];	/* 0xa8 */
+		u32 gtr0;		/* 0xc0 */
+		u8 reserved_0xc4[12];	/* 0xc4 */
+		/*
+		 * DXnRSR0 is not documented in ZynqMP manual but
+		 * it's used in libdram.
+		 */
+		u32 rsr[4];		/* 0xd0 */
+		u32 gsr[4];		/* 0xe0 */
+		u8 reserved_0xf0[16];	/* 0xf0 */
+	} dx[4];		/* 0x700, 0x800, 0x900, 0xa00 */
+};
+check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0);
+
+#define PIR_INIT	BIT(0)
+#define PIR_ZCAL	BIT(1)
+#define PIR_CA		BIT(2)
+#define PIR_PLLINIT	BIT(4)
+#define PIR_DCAL	BIT(5)
+#define PIR_PHYRST	BIT(6)
+#define PIR_DRAMRST	BIT(7)
+#define PIR_DRAMINIT	BIT(8)
+#define PIR_WL		BIT(9)
+#define PIR_QSGATE	BIT(10)
+#define PIR_WLADJ	BIT(11)
+#define PIR_RDDSKW	BIT(12)
+#define PIR_WRDSKW	BIT(13)
+#define PIR_RDEYE	BIT(14)
+#define PIR_WREYE	BIT(15)
+#define PIR_VREF	BIT(17)
+#define PIR_CTLDINIT	BIT(18)
+#define PIR_DQS2DQ	BIT(20)
+#define PIR_DCALPSE	BIT(29)
+#define PIR_ZCALBYP	BIT(30)
+
+#define DCR_LPDDR3	(1 << 0)
+#define DCR_DDR3	(3 << 0)
+#define DCR_DDR4	(4 << 0)
+#define DCR_DDR8BANK	BIT(3)
+#define DCR_DDR2T	BIT(28)
+
+/*
+ * The delay parameters allow to allegedly specify delay times of some
+ * unknown unit for each individual bit trace in each of the four data bytes
+ * the 32-bit wide access consists of. Also three control signals can be
+ * adjusted individually.
+ */
+#define NR_OF_BYTE_LANES	(32 / BITS_PER_BYTE)
+/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */
+#define WR_LINES_PER_BYTE_LANE	(BITS_PER_BYTE + 4)
+/*
+ * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN,
+ * Termination and Power down
+ */
+#define RD_LINES_PER_BYTE_LANE	(BITS_PER_BYTE + 6)
+struct dram_para {
+	u32 clk;
+	enum sunxi_dram_type type;
+	u8 cols;
+	u8 rows;
+	u8 ranks;
+	const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
+	const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
+};
+
+
+static inline int ns_to_t(int nanoseconds)
+{
+	const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
+
+	return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+
+void mctl_set_timing_params(struct dram_para *para);
+
+#endif /* _SUNXI_DRAM_SUN50I_H6_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun6i.h b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h
new file mode 100644
index 0000000..929450f
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h
@@ -0,0 +1,358 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sun6i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ */
+
+#ifndef _SUNXI_DRAM_SUN6I_H
+#define _SUNXI_DRAM_SUN6I_H
+
+struct sunxi_mctl_com_reg {
+	u32 cr;			/* 0x00 */
+	u32 ccr;		/* 0x04 controller configuration register */
+	u32 dbgcr;		/* 0x08 */
+	u32 dbgcr1;		/* 0x0c */
+	u32 rmcr[8];		/* 0x10 */
+	u32 mmcr[16];		/* 0x30 */
+	u32 mbagcr[6];		/* 0x70 */
+	u32 maer;		/* 0x88 */
+	u8 res0[0x14];		/* 0x8c */
+	u32 mdfscr;		/* 0x100 */
+	u32 mdfsmer;		/* 0x104 */
+	u32 mdfsmrmr;		/* 0x108 */
+	u32 mdfstr0;		/* 0x10c */
+	u32 mdfstr1;		/* 0x110 */
+	u32 mdfstr2;		/* 0x114 */
+	u32 mdfstr3;		/* 0x118 */
+	u32 mdfsgcr;		/* 0x11c */
+	u8 res1[0x1c];		/* 0x120 */
+	u32 mdfsivr;		/* 0x13c */
+	u8 res2[0x0c];		/* 0x140 */
+	u32 mdfstcr;		/* 0x14c */
+};
+
+struct sunxi_mctl_ctl_reg {
+	u8 res0[0x04];		/* 0x00 */
+	u32 sctl;		/* 0x04 */
+	u32 sstat;		/* 0x08 */
+	u8 res1[0x34];		/* 0x0c */
+	u32 mcmd;		/* 0x40 */
+	u8 res2[0x08];		/* 0x44 */
+	u32 cmdstat;		/* 0x4c */
+	u32 cmdstaten;		/* 0x50 */
+	u8 res3[0x0c];		/* 0x54 */
+	u32 mrrcfg0;		/* 0x60 */
+	u32 mrrstat0;		/* 0x64 */
+	u32 mrrstat1;		/* 0x68 */
+	u8 res4[0x10];		/* 0x6c */
+	u32 mcfg1;		/* 0x7c */
+	u32 mcfg;		/* 0x80 */
+	u32 ppcfg;		/* 0x84 */
+	u32 mstat;		/* 0x88 */
+	u32 lp2zqcfg;		/* 0x8c */
+	u8 res5[0x04];		/* 0x90 */
+	u32 dtustat;		/* 0x94 */
+	u32 dtuna;		/* 0x98 */
+	u32 dtune;		/* 0x9c */
+	u32 dtuprd0;		/* 0xa0 */
+	u32 dtuprd1;		/* 0xa4 */
+	u32 dtuprd2;		/* 0xa8 */
+	u32 dtuprd3;		/* 0xac */
+	u32 dtuawdt;		/* 0xb0 */
+	u8 res6[0x0c];		/* 0xb4 */
+	u32 togcnt1u;		/* 0xc0 */
+	u8 res7[0x08];		/* 0xc4 */
+	u32 togcnt100n;		/* 0xcc */
+	u32 trefi;		/* 0xd0 */
+	u32 tmrd;		/* 0xd4 */
+	u32 trfc;		/* 0xd8 */
+	u32 trp;		/* 0xdc */
+	u32 trtw;		/* 0xe0 */
+	u32 tal;		/* 0xe4 */
+	u32 tcl;		/* 0xe8 */
+	u32 tcwl;		/* 0xec */
+	u32 tras;		/* 0xf0 */
+	u32 trc;		/* 0xf4 */
+	u32 trcd;		/* 0xf8 */
+	u32 trrd;		/* 0xfc */
+	u32 trtp;		/* 0x100 */
+	u32 twr;		/* 0x104 */
+	u32 twtr;		/* 0x108 */
+	u32 texsr;		/* 0x10c */
+	u32 txp;		/* 0x110 */
+	u32 txpdll;		/* 0x114 */
+	u32 tzqcs;		/* 0x118 */
+	u32 tzqcsi;		/* 0x11c */
+	u32 tdqs;		/* 0x120 */
+	u32 tcksre;		/* 0x124 */
+	u32 tcksrx;		/* 0x128 */
+	u32 tcke;		/* 0x12c */
+	u32 tmod;		/* 0x130 */
+	u32 trstl;		/* 0x134 */
+	u32 tzqcl;		/* 0x138 */
+	u32 tmrr;		/* 0x13c */
+	u32 tckesr;		/* 0x140 */
+	u32 tdpd;		/* 0x144 */
+	u8 res8[0xb8];		/* 0x148 */
+	u32 dtuwactl;		/* 0x200 */
+	u32 dturactl;		/* 0x204 */
+	u32 dtucfg;		/* 0x208 */
+	u32 dtuectl;		/* 0x20c */
+	u32 dtuwd0;		/* 0x210 */
+	u32 dtuwd1;		/* 0x214 */
+	u32 dtuwd2;		/* 0x218 */
+	u32 dtuwd3;		/* 0x21c */
+	u32 dtuwdm;		/* 0x220 */
+	u32 dturd0;		/* 0x224 */
+	u32 dturd1;		/* 0x228 */
+	u32 dturd2;		/* 0x22c */
+	u32 dturd3;		/* 0x230 */
+	u32 dtulfsrwd;		/* 0x234 */
+	u32 dtulfsrrd;		/* 0x238 */
+	u32 dtueaf;		/* 0x23c */
+	u32 dfitctldly;		/* 0x240 */
+	u32 dfiodtcfg;		/* 0x244 */
+	u32 dfiodtcfg1;		/* 0x248 */
+	u32 dfiodtrmap;		/* 0x24c */
+	u32 dfitphywrd;		/* 0x250 */
+	u32 dfitphywrl;		/* 0x254 */
+	u8 res9[0x08];		/* 0x258 */
+	u32 dfitrdden;		/* 0x260 */
+	u32 dfitphyrdl;		/* 0x264 */
+	u8 res10[0x08];		/* 0x268 */
+	u32 dfitphyupdtype0;	/* 0x270 */
+	u32 dfitphyupdtype1;	/* 0x274 */
+	u32 dfitphyupdtype2;	/* 0x278 */
+	u32 dfitphyupdtype3;	/* 0x27c */
+	u32 dfitctrlupdmin;	/* 0x280 */
+	u32 dfitctrlupdmax;	/* 0x284 */
+	u32 dfitctrlupddly;	/* 0x288 */
+	u8 res11[4];		/* 0x28c */
+	u32 dfiupdcfg;		/* 0x290 */
+	u32 dfitrefmski;	/* 0x294 */
+	u32 dfitcrlupdi;	/* 0x298 */
+	u8 res12[0x10];		/* 0x29c */
+	u32 dfitrcfg0;		/* 0x2ac */
+	u32 dfitrstat0;		/* 0x2b0 */
+	u32 dfitrwrlvlen;	/* 0x2b4 */
+	u32 dfitrrdlvlen;	/* 0x2b8 */
+	u32 dfitrrdlvlgateen;	/* 0x2bc */
+	u8 res13[0x04];		/* 0x2c0 */
+	u32 dfistcfg0;		/* 0x2c4 */
+	u32 dfistcfg1;		/* 0x2c8 */
+	u8 res14[0x04];		/* 0x2cc */
+	u32 dfitdramclken;	/* 0x2d0 */
+	u32 dfitdramclkdis;	/* 0x2d4 */
+	u8 res15[0x18];		/* 0x2d8 */
+	u32 dfilpcfg0;		/* 0x2f0 */
+};
+
+struct sunxi_mctl_phy_reg {
+	u8 res0[0x04];		/* 0x00 */
+	u32 pir;		/* 0x04 */
+	u32 pgcr;		/* 0x08 phy general configuration register */
+	u32 pgsr;		/* 0x0c */
+	u32 dllgcr;		/* 0x10 */
+	u32 acdllcr;		/* 0x14 */
+	u32 ptr0;		/* 0x18 */
+	u32 ptr1;		/* 0x1c */
+	u32 ptr2;		/* 0x20 */
+	u32 aciocr;		/* 0x24 */
+	u32 dxccr;		/* 0x28 DATX8 common configuration register */
+	u32 dsgcr;		/* 0x2c dram system general config register */
+	u32 dcr;		/* 0x30 */
+	u32 dtpr0;		/* 0x34 dram timing parameters register 0 */
+	u32 dtpr1;		/* 0x38 dram timing parameters register 1 */
+	u32 dtpr2;		/* 0x3c dram timing parameters register 2 */
+	u32 mr0;		/* 0x40 mode register 0 */
+	u32 mr1;		/* 0x44 mode register 1 */
+	u32 mr2;		/* 0x48 mode register 2 */
+	u32 mr3;		/* 0x4c mode register 3 */
+	u32 odtcr;		/* 0x50 */
+	u32 dtar;		/* 0x54 data training address register */
+	u32 dtd0;		/* 0x58 */
+	u32 dtd1;		/* 0x5c */
+	u8 res1[0x60];		/* 0x60 */
+	u32 dcuar;		/* 0xc0 */
+	u32 dcudr;		/* 0xc4 */
+	u32 dcurr;		/* 0xc8 */
+	u32 dculr;		/* 0xcc */
+	u32 dcugcr;		/* 0xd0 */
+	u32 dcutpr;		/* 0xd4 */
+	u32 dcusr0;		/* 0xd8 */
+	u32 dcusr1;		/* 0xdc */
+	u8 res2[0x20];		/* 0xe0 */
+	u32 bistrr;		/* 0x100 */
+	u32 bistmskr0;		/* 0x104 */
+	u32 bistmskr1;		/* 0x108 */
+	u32 bistwcr;		/* 0x10c */
+	u32 bistlsr;		/* 0x110 */
+	u32 bistar0;		/* 0x114 */
+	u32 bistar1;		/* 0x118 */
+	u32 bistar2;		/* 0x11c */
+	u32 bistupdr;		/* 0x120 */
+	u32 bistgsr;		/* 0x124 */
+	u32 bistwer;		/* 0x128 */
+	u32 bistber0;		/* 0x12c */
+	u32 bistber1;		/* 0x130 */
+	u32 bistber2;		/* 0x134 */
+	u32 bistwcsr;		/* 0x138 */
+	u32 bistfwr0;		/* 0x13c */
+	u32 bistfwr1;		/* 0x140 */
+	u8 res3[0x3c];		/* 0x144 */
+	u32 zq0cr0;		/* 0x180 zq 0 control register 0 */
+	u32 zq0cr1;		/* 0x184 zq 0 control register 1 */
+	u32 zq0sr0;		/* 0x188 zq 0 status register 0 */
+	u32 zq0sr1;		/* 0x18c zq 0 status register 1 */
+	u8 res4[0x30];		/* 0x190 */
+	u32 dx0gcr;		/* 0x1c0 */
+	u32 dx0gsr0;		/* 0x1c4 */
+	u32 dx0gsr1;		/* 0x1c8 */
+	u32 dx0dllcr;		/* 0x1cc */
+	u32 dx0dqtr;		/* 0x1d0 */
+	u32 dx0dqstr;		/* 0x1d4 */
+	u8 res5[0x28];		/* 0x1d8 */
+	u32 dx1gcr;		/* 0x200 */
+	u32 dx1gsr0;		/* 0x204 */
+	u32 dx1gsr1;		/* 0x208 */
+	u32 dx1dllcr;		/* 0x20c */
+	u32 dx1dqtr;		/* 0x210 */
+	u32 dx1dqstr;		/* 0x214 */
+	u8 res6[0x28];		/* 0x218 */
+	u32 dx2gcr;		/* 0x240 */
+	u32 dx2gsr0;		/* 0x244 */
+	u32 dx2gsr1;		/* 0x248 */
+	u32 dx2dllcr;		/* 0x24c */
+	u32 dx2dqtr;		/* 0x250 */
+	u32 dx2dqstr;		/* 0x254 */
+	u8 res7[0x28];		/* 0x258 */
+	u32 dx3gcr;		/* 0x280 */
+	u32 dx3gsr0;		/* 0x284 */
+	u32 dx3gsr1;		/* 0x288 */
+	u32 dx3dllcr;		/* 0x28c */
+	u32 dx3dqtr;		/* 0x290 */
+	u32 dx3dqstr;		/* 0x294 */
+};
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_RANK_MASK		(3 << 0)
+#define MCTL_CR_RANK(x)			(((x) - 1) << 0)
+#define MCTL_CR_BANK_MASK		(3 << 2)
+#define MCTL_CR_BANK(x)			((x) << 2)
+#define MCTL_CR_ROW_MASK		(0xf << 4)
+#define MCTL_CR_ROW(x)			(((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK		(0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x)		((fls(x) - 4) << 8)
+#define MCTL_CR_BUSW_MASK		(3 << 12)
+#define MCTL_CR_BUSW16			(1 << 12)
+#define MCTL_CR_BUSW32			(3 << 12)
+#define MCTL_CR_SEQUENCE		(1 << 15)
+#define MCTL_CR_DDR3			(3 << 16)
+#define MCTL_CR_CHANNEL_MASK		(1 << 19)
+#define MCTL_CR_CHANNEL(x)		(((x) - 1) << 19)
+#define MCTL_CR_UNKNOWN			((1 << 22) | (1 << 20))
+#define MCTL_CCR_CH0_CLK_EN		(1 << 0)
+#define MCTL_CCR_CH1_CLK_EN		(1 << 1)
+#define MCTL_CCR_MASTER_CLK_EN		(1 << 2)
+
+/*
+ * DRAM control (sunxi_mctl_ctl_reg) register constants.
+ * Note that we use constant values for a lot of the timings, this is what
+ * the original boot0 bootloader does.
+ */
+#define MCTL_SCTL_CONFIG		1
+#define MCTL_SCTL_ACCESS		2
+#define MCTL_MCMD_NOP			0x88000000
+#define MCTL_MCMD_BUSY			0x80000000
+#define MCTL_MCFG_DDR3			0x70061
+#define MCTL_TREFI			78
+#define MCTL_TMRD			4
+#define MCTL_TRFC			115
+#define MCTL_TRP			9
+#define MCTL_TPREA			0
+#define MCTL_TRTW			2
+#define MCTL_TAL			0
+#define MCTL_TCL			9
+#define MCTL_TCWL			8
+#define MCTL_TRAS			18
+#define MCTL_TRC			23
+#define MCTL_TRCD			9
+#define MCTL_TRRD			4
+#define MCTL_TRTP			4
+#define MCTL_TWR			8
+#define MCTL_TWTR			4
+#define MCTL_TEXSR			512
+#define MCTL_TXP			4
+#define MCTL_TXPDLL			14
+#define MCTL_TZQCS			64
+#define MCTL_TZQCSI			0
+#define MCTL_TDQS			1
+#define MCTL_TCKSRE			5
+#define MCTL_TCKSRX			5
+#define MCTL_TCKE			4
+#define MCTL_TMOD			12
+#define MCTL_TRSTL			80
+#define MCTL_TZQCL			512
+#define MCTL_TMRR			2
+#define MCTL_TCKESR			5
+#define MCTL_TDPD			0
+#define MCTL_DFITPHYRDL			15
+#define MCTL_DFIUPDCFG_UPD		(1 << 1)
+#define MCTL_DFISTCFG0			5
+
+/*
+ * DRAM phy (sunxi_mctl_phy_reg) register values / constants.
+ */
+#define MCTL_PIR_CLEAR_STATUS		(1 << 28)
+#define MCTL_PIR_STEP1			0xe9
+#define MCTL_PIR_STEP2			0x81
+#define MCTL_PGCR_RANK			(1 << 19)
+#define MCTL_PGCR			0x018c0202
+#define MCTL_PGSR_TRAIN_ERR_MASK	(3 << 5)
+/* constants for both acdllcr as well as dx#dllcr */
+#define MCTL_DLLCR_NRESET		(1 << 30)
+#define MCTL_DLLCR_DISABLE		(1 << 31)
+/* ptr constants these are or-ed together to get the final ptr# values */
+#define MCTL_TITMSRST			10
+#define MCTL_TDLLLOCK			2250
+#define MCTL_TDLLSRST			23
+#define MCTL_TDINIT0			217000
+#define MCTL_TDINIT1			160
+#define MCTL_TDINIT2			87000
+#define MCTL_TDINIT3			433
+/* end ptr constants */
+#define MCTL_ACIOCR_DISABLE		((3 << 18) | (1 << 8) | (1 << 3))
+#define MCTL_DXCCR_DISABLE		((1 << 3) | (1 << 2))
+#define MCTL_DXCCR			0x800
+#define MCTL_DSGCR_ENABLE		(1 << 28)
+#define MCTL_DSGCR			0xf200001b
+#define MCTL_DCR_DDR3			0x0b
+/* dtpr constants these are or-ed together to get the final dtpr# values */
+#define MCTL_TCCD			0
+#define MCTL_TDQSCKMAX			1
+#define MCTL_TDQSCK			1
+#define MCTL_TRTODT			0
+#define MCTL_TFAW			20
+#define MCTL_TAOND			0
+#define MCTL_TDLLK			512
+/* end dtpr constants */
+#define MCTL_MR0			0x1a50
+#define MCTL_MR1			0x4
+#define MCTL_MR2			((MCTL_TCWL - 5) << 3)
+#define MCTL_MR3			0x0
+#define MCTL_DX_GCR_EN			(1 << 0)
+#define MCTL_DX_GCR			0x880
+#define MCTL_DX_GSR0_RANK0_TRAIN_DONE	(1 << 0)
+#define MCTL_DX_GSR0_RANK1_TRAIN_DONE	(1 << 1)
+#define MCTL_DX_GSR0_RANK0_TRAIN_ERR	(1 << 4)
+#define MCTL_DX_GSR0_RANK1_TRAIN_ERR	(1 << 5)
+
+#endif /* _SUNXI_DRAM_SUN6I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h
new file mode 100644
index 0000000..ca98597
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h
@@ -0,0 +1,266 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sun8i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * CPL <cplanxy@allwinnertech.com>
+ * Jerry Wang <wangflord@allwinnertech.com>
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_H
+#define _SUNXI_DRAM_SUN8I_H
+
+struct dram_para {
+	u32 clock;
+	u32 type;
+	u32 zq;
+	u32 odt_en;
+	s32 odt_correction;
+	u32 para1;
+	u32 para2;
+	u32 mr0;
+	u32 mr1;
+	u32 mr2;
+	u32 mr3;
+	u32 tpr0;
+	u32 tpr1;
+	u32 tpr2;
+	u32 tpr3;
+	u32 tpr4;
+	u32 tpr5;
+	u32 tpr6;
+	u32 tpr7;
+	u32 tpr8;
+	u32 tpr9;
+	u32 tpr10;
+	u32 tpr11;
+	u32 tpr12;
+	u32 tpr13;
+};
+
+struct sunxi_mctl_com_reg {
+	u32 cr;			/* 0x00 */
+	u32 ccr;		/* 0x04 controller configuration register */
+	u32 dbgcr;		/* 0x08 */
+	u8 res0[0x4];		/* 0x0c */
+	u32 mcr0_0;		/* 0x10 */
+	u32 mcr1_0;		/* 0x14 */
+	u32 mcr0_1;		/* 0x18 */
+	u32 mcr1_1;		/* 0x1c */
+	u32 mcr0_2;		/* 0x20 */
+	u32 mcr1_2;		/* 0x24 */
+	u32 mcr0_3;		/* 0x28 */
+	u32 mcr1_3;		/* 0x2c */
+	u32 mcr0_4;		/* 0x30 */
+	u32 mcr1_4;		/* 0x34 */
+	u32 mcr0_5;		/* 0x38 */
+	u32 mcr1_5;		/* 0x3c */
+	u32 mcr0_6;		/* 0x40 */
+	u32 mcr1_6;		/* 0x44 */
+	u32 mcr0_7;		/* 0x48 */
+	u32 mcr1_7;		/* 0x4c */
+	u32 mcr0_8;		/* 0x50 */
+	u32 mcr1_8;		/* 0x54 */
+	u32 mcr0_9;		/* 0x58 */
+	u32 mcr1_9;		/* 0x5c */
+	u32 mcr0_10;		/* 0x60 */
+	u32 mcr1_10;		/* 0x64 */
+	u32 mcr0_11;		/* 0x68 */
+	u32 mcr1_11;		/* 0x6c */
+	u32 mcr0_12;		/* 0x70 */
+	u32 mcr1_12;		/* 0x74 */
+	u32 mcr0_13;		/* 0x78 */
+	u32 mcr1_13;		/* 0x7c */
+	u32 mcr0_14;		/* 0x80 */
+	u32 mcr1_14;		/* 0x84 */
+	u32 mcr0_15;		/* 0x88 */
+	u32 mcr1_15;		/* 0x8c */
+	u32 bwcr;		/* 0x90 */
+	u32 maer;		/* 0x94 */
+	u8 res1[0x4];		/* 0x98 */
+	u32 mcgcr;		/* 0x9c */
+	u32 bwctr;		/* 0xa0 */
+	u8 res2[0x4];		/* 0xa4 */
+	u32 swonr;		/* 0xa8 */
+	u32 swoffr;		/* 0xac */
+};
+
+struct sunxi_mctl_ctl_reg {
+	u32 mstr;		/* 0x00 */
+	u32 statr;		/* 0x04 */
+	u8 res0[0x08];		/* 0x08 */
+	u32 mrctrl0;		/* 0x10 */
+	u32 mrctrl1;		/* 0x14 */
+	u32 mrstatr;		/* 0x18 */
+	u8 res1[0x04];		/* 0x1c */
+	u32 derateen;		/* 0x20 */
+	u32 deratenint;		/* 0x24 */
+	u8 res2[0x08];		/* 0x28 */
+	u32 pwrctl;		/* 0x30 */
+	u32 pwrtmg;		/* 0x34 */
+	u8 res3[0x18];		/* 0x38 */
+	u32 rfshctl0;		/* 0x50 */
+	u32 rfshctl1;		/* 0x54 */
+	u8 res4[0x8];		/* 0x58 */
+	u32 rfshctl3;		/* 0x60 */
+	u32 rfshtmg;		/* 0x64 */
+	u8 res6[0x68];		/* 0x68 */
+	u32 init0;		/* 0xd0 */
+	u32 init1;		/* 0xd4 */
+	u32 init2;		/* 0xd8 */
+	u32 init3;		/* 0xdc */
+	u32 init4;		/* 0xe0 */
+	u32 init5;		/* 0xe4 */
+	u8 res7[0x0c];		/* 0xe8 */
+	u32 rankctl;		/* 0xf4 */
+	u8 res8[0x08];		/* 0xf8 */
+	u32 dramtmg0;		/* 0x100 */
+	u32 dramtmg1;		/* 0x104 */
+	u32 dramtmg2;		/* 0x108 */
+	u32 dramtmg3;		/* 0x10c */
+	u32 dramtmg4;		/* 0x110 */
+	u32 dramtmg5;		/* 0x114 */
+	u32 dramtmg6;		/* 0x118 */
+	u32 dramtmg7;		/* 0x11c */
+	u32 dramtmg8;		/* 0x120 */
+	u8 res9[0x5c];		/* 0x124 */
+	u32 zqctl0;		/* 0x180 */
+	u32 zqctl1;		/* 0x184 */
+	u32 zqctl2;		/* 0x188 */
+	u32 zqstat;		/* 0x18c */
+	u32 pitmg0;		/* 0x190 */
+	u32 pitmg1;		/* 0x194 */
+	u32 plpcfg0;		/* 0x198 */
+	u8 res10[0x04];		/* 0x19c */
+	u32 upd0;		/* 0x1a0 */
+	u32 upd1;		/* 0x1a4 */
+	u32 upd2;		/* 0x1a8 */
+	u32 upd3;		/* 0x1ac */
+	u32 pimisc;		/* 0x1b0 */
+	u8 res11[0x1c];		/* 0x1b4 */
+	u32 trainctl0;		/* 0x1d0 */
+	u32 trainctl1;		/* 0x1d4 */
+	u32 trainctl2;		/* 0x1d8 */
+	u32 trainstat;		/* 0x1dc */
+	u8 res12[0x60];		/* 0x1e0 */
+	u32 odtcfg;		/* 0x240 */
+	u32 odtmap;		/* 0x244 */
+	u8 res13[0x08];		/* 0x248 */
+	u32 sched;		/* 0x250 */
+	u8 res14[0x04];		/* 0x254 */
+	u32 perfshpr0;		/* 0x258 */
+	u32 perfshpr1;		/* 0x25c */
+	u32 perflpr0;		/* 0x260 */
+	u32 perflpr1;		/* 0x264 */
+	u32 perfwr0;		/* 0x268 */
+	u32 perfwr1;		/* 0x26c */
+};
+
+struct sunxi_mctl_phy_reg {
+	u8 res0[0x04];		/* 0x00 */
+	u32 pir;		/* 0x04 */
+	u32 pgcr0;		/* 0x08 phy general configuration register */
+	u32 pgcr1;		/* 0x0c phy general configuration register */
+	u32 pgsr0;		/* 0x10 */
+	u32 pgsr1;		/* 0x14 */
+	u32 dllgcr;		/* 0x18 */
+	u32 ptr0;		/* 0x1c */
+	u32 ptr1;		/* 0x20 */
+	u32 ptr2;		/* 0x24 */
+	u32 ptr3;		/* 0x28 */
+	u32 ptr4;		/* 0x2c */
+	u32 acmdlr;		/* 0x30 */
+	u32 acbdlr;		/* 0x34 */
+	u32 aciocr;		/* 0x38 */
+	u32 dxccr;		/* 0x3c DATX8 common configuration register */
+	u32 dsgcr;		/* 0x40 dram system general config register */
+	u32 dcr;		/* 0x44 */
+	u32 dtpr0;		/* 0x48 dram timing parameters register 0 */
+	u32 dtpr1;		/* 0x4c dram timing parameters register 1 */
+	u32 dtpr2;		/* 0x50 dram timing parameters register 2 */
+	u32 mr0;		/* 0x54 mode register 0 */
+	u32 mr1;		/* 0x58 mode register 1 */
+	u32 mr2;		/* 0x5c mode register 2 */
+	u32 mr3;		/* 0x60 mode register 3 */
+	u32 odtcr;		/* 0x64 */
+	u32 dtcr;		/* 0x68 */
+	u32 dtar0;		/* 0x6c data training address register 0 */
+	u32 dtar1;		/* 0x70 data training address register 1 */
+	u32 dtar2;		/* 0x74 data training address register 2 */
+	u32 dtar3;		/* 0x78 data training address register 3 */
+	u32 dtdr0;		/* 0x7c */
+	u32 dtdr1;		/* 0x80 */
+	u32 dtedr0;		/* 0x84 */
+	u32 dtedr1;		/* 0x88 */
+	u32 pgcr2;		/* 0x8c */
+	u8 res1[0x70];		/* 0x90 */
+	u32 bistrr;		/* 0x100 */
+	u32 bistwcr;		/* 0x104 */
+	u32 bistmskr0;		/* 0x108 */
+	u32 bistmskr1;		/* 0x10c */
+	u32 bistmskr2;		/* 0x110 */
+	u32 bistlsr;		/* 0x114 */
+	u32 bistar0;		/* 0x118 */
+	u32 bistar1;		/* 0x11c */
+	u32 bistar2;		/* 0x120 */
+	u32 bistupdr;		/* 0x124 */
+	u32 bistgsr;		/* 0x128 */
+	u32 bistwer;		/* 0x12c */
+	u32 bistber0;		/* 0x130 */
+	u32 bistber1;		/* 0x134 */
+	u32 bistber2;		/* 0x138 */
+	u32 bistber3;		/* 0x13c */
+	u32 bistwcsr;		/* 0x140 */
+	u32 bistfwr0;		/* 0x144 */
+	u32 bistfwr1;		/* 0x148 */
+	u32 bistfwr2;		/* 0x14c */
+	u8 res2[0x30];		/* 0x150 */
+	u32 zqcr0;		/* 0x180 zq control register 0 */
+	u32 zqcr1;		/* 0x184 zq control register 1 */
+	u32 zqsr0;		/* 0x188 zq status register 0 */
+	u32 zqsr1;		/* 0x18c zq status register 1 */
+	u32 zqcr2;		/* 0x190 zq control register 2 */
+	u8 res3[0x2c];		/* 0x194 */
+	u32 dx0gcr;		/* 0x1c0 */
+	u32 dx0gsr0;		/* 0x1c4 */
+	u32 dx0gsr1;		/* 0x1c8 */
+	u32 dx0bdlr0;		/* 0x1cc */
+	u32 dx0bdlr1;		/* 0x1d0 */
+	u32 dx0bdlr2;		/* 0x1d4 */
+	u32 dx0bdlr3;		/* 0x1d8 */
+	u32 dx0bdlr4;		/* 0x1dc */
+	u32 dx0lcdlr0;		/* 0x1e0 */
+	u32 dx0lcdlr1;		/* 0x1e4 */
+	u32 dx0lcdlr2;		/* 0x1e8 */
+	u32 dx0mdlr;		/* 0x1ec */
+	u32 dx0gtr;		/* 0x1f0 */
+	u32 dx0gsr2;		/* 0x1f4 */
+	u8 res4[0x08];		/* 0x1f8 */
+	u32 dx1gcr;		/* 0x200 */
+	u32 dx1gsr0;		/* 0x204 */
+	u32 dx1gsr1;		/* 0x208 */
+	u32 dx1bdlr0;		/* 0x20c */
+	u32 dx1bdlr1;		/* 0x210 */
+	u32 dx1bdlr2;		/* 0x214 */
+	u32 dx1bdlr3;		/* 0x218 */
+	u32 dx1bdlr4;		/* 0x21c */
+	u32 dx1lcdlr0;		/* 0x220 */
+	u32 dx1lcdlr1;		/* 0x224 */
+	u32 dx1lcdlr2;		/* 0x228 */
+	u32 dx1mdlr;		/* 0x22c */
+	u32 dx1gtr;		/* 0x230 */
+	u32 dx1gsr2;		/* 0x234 */
+};
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_ROW_MASK		(0xf << 4)
+#define MCTL_CR_ROW(x)			(((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK		(0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x)		((x) << 8)
+
+#endif /* _SUNXI_DRAM_SUN8I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h
new file mode 100644
index 0000000..49a6108
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sun8i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ *                         Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_A33_H
+#define _SUNXI_DRAM_SUN8I_A33_H
+
+struct sunxi_mctl_com_reg {
+	u32 cr;			/* 0x00 */
+	u32 ccr;		/* 0x04 controller configuration register */
+	u32 dbgcr;		/* 0x08 */
+	u8 res0[0x4];		/* 0x0c */
+	u32 mcr0_0;		/* 0x10 */
+	u32 mcr1_0;		/* 0x14 */
+	u32 mcr0_1;		/* 0x18 */
+	u32 mcr1_1;		/* 0x1c */
+	u32 mcr0_2;		/* 0x20 */
+	u32 mcr1_2;		/* 0x24 */
+	u32 mcr0_3;		/* 0x28 */
+	u32 mcr1_3;		/* 0x2c */
+	u32 mcr0_4;		/* 0x30 */
+	u32 mcr1_4;		/* 0x34 */
+	u32 mcr0_5;		/* 0x38 */
+	u32 mcr1_5;		/* 0x3c */
+	u32 mcr0_6;		/* 0x40 */
+	u32 mcr1_6;		/* 0x44 */
+	u32 mcr0_7;		/* 0x48 */
+	u32 mcr1_7;		/* 0x4c */
+	u32 mcr0_8;		/* 0x50 */
+	u32 mcr1_8;		/* 0x54 */
+	u32 mcr0_9;		/* 0x58 */
+	u32 mcr1_9;		/* 0x5c */
+	u32 mcr0_10;		/* 0x60 */
+	u32 mcr1_10;		/* 0x64 */
+	u32 mcr0_11;		/* 0x68 */
+	u32 mcr1_11;		/* 0x6c */
+	u32 mcr0_12;		/* 0x70 */
+	u32 mcr1_12;		/* 0x74 */
+	u32 mcr0_13;		/* 0x78 */
+	u32 mcr1_13;		/* 0x7c */
+	u32 mcr0_14;		/* 0x80 */
+	u32 mcr1_14;		/* 0x84 */
+	u32 mcr0_15;		/* 0x88 */
+	u32 mcr1_15;		/* 0x8c */
+	u32 bwcr;		/* 0x90 */
+	u32 maer;		/* 0x94 */
+	u32 mapr;		/* 0x98 */
+	u32 mcgcr;		/* 0x9c */
+	u32 bwctr;		/* 0xa0 */
+	u8 res2[0x8];		/* 0xa4 */
+	u32 swoffr;		/* 0xac */
+	u8 res3[0x10];		/* 0xb0 */
+	u32 swonr;		/* 0xc0 */
+	u8 res4[0x3c];		/* 0xc4 */
+	u32 mdfscr;		/* 0x100 */
+	u32 mdfsmer;		/* 0x104 */
+};
+
+struct sunxi_mctl_ctl_reg {
+	u32 pir;		/* 0x00 */
+	u32 pwrctl;		/* 0x04 */
+	u32 mrctrl0;		/* 0x08 */
+	u32 clken;		/* 0x0c */
+	u32 pgsr0;		/* 0x10 */
+	u32 pgsr1;		/* 0x14 */
+	u32 statr;		/* 0x18 */
+	u8 res1[0x14];		/* 0x1c */
+	u32 mr0;		/* 0x30 */
+	u32 mr1;		/* 0x34 */
+	u32 mr2;		/* 0x38 */
+	u32 mr3;		/* 0x3c */
+	u32 pllgcr;		/* 0x40 */
+	u32 ptr0;		/* 0x44 */
+	u32 ptr1;		/* 0x48 */
+	u32 ptr2;		/* 0x4c */
+	u32 ptr3;		/* 0x50 */
+	u32 ptr4;		/* 0x54 */
+	u32 dramtmg0;		/* 0x58 dram timing parameters register 0 */
+	u32 dramtmg1;		/* 0x5c dram timing parameters register 1 */
+	u32 dramtmg2;		/* 0x60 dram timing parameters register 2 */
+	u32 dramtmg3;		/* 0x64 dram timing parameters register 3 */
+	u32 dramtmg4;		/* 0x68 dram timing parameters register 4 */
+	u32 dramtmg5;		/* 0x6c dram timing parameters register 5 */
+	u32 dramtmg6;		/* 0x70 dram timing parameters register 6 */
+	u32 dramtmg7;		/* 0x74 dram timing parameters register 7 */
+	u32 dramtmg8;		/* 0x78 dram timing parameters register 8 */
+	u32 odtcfg;		/* 0x7c */
+	u32 pitmg0;		/* 0x80 */
+	u32 pitmg1;		/* 0x84 */
+	u8 res2[0x4];		/* 0x88 */
+	u32 rfshctl0;		/* 0x8c */
+	u32 rfshtmg;		/* 0x90 */
+	u32 rfshctl1;		/* 0x94 */
+	u32 pwrtmg;		/* 0x98 */
+	u8  res3[0x20];		/* 0x9c */
+	u32 dqsgmr;		/* 0xbc */
+	u32 dtcr;		/* 0xc0 */
+	u32 dtar0;		/* 0xc4 */
+	u32 dtar1;		/* 0xc8 */
+	u32 dtar2;		/* 0xcc */
+	u32 dtar3;		/* 0xd0 */
+	u32 dtdr0;		/* 0xd4 */
+	u32 dtdr1;		/* 0xd8 */
+	u32 dtmr0;		/* 0xdc */
+	u32 dtmr1;		/* 0xe0 */
+	u32 dtbmr;		/* 0xe4 */
+	u32 catr0;		/* 0xe8 */
+	u32 catr1;		/* 0xec */
+	u32 dtedr0;		/* 0xf0 */
+	u32 dtedr1;		/* 0xf4 */
+	u8 res4[0x8];		/* 0xf8 */
+	u32 pgcr0;		/* 0x100 */
+	u32 pgcr1;		/* 0x104 */
+	u32 pgcr2;		/* 0x108 */
+	u8 res5[0x4];		/* 0x10c */
+	u32 iovcr0;		/* 0x110 */
+	u32 iovcr1;		/* 0x114 */
+	u32 dqsdr;		/* 0x118 */
+	u32 dxccr;		/* 0x11c */
+	u32 odtmap;		/* 0x120 */
+	u32 zqctl0;		/* 0x124 */
+	u32 zqctl1;		/* 0x128 */
+	u8 res6[0x14];		/* 0x12c */
+	u32 zqcr0;		/* 0x140 zq control register 0 */
+	u32 zqcr1;		/* 0x144 zq control register 1 */
+	u32 zqcr2;		/* 0x148 zq control register 2 */
+	u32 zqsr0;		/* 0x14c zq status register 0 */
+	u32 zqsr1;		/* 0x150 zq status register 1 */
+	u8 res7[0x6c];		/* 0x154 */
+	u32 sched;		/* 0x1c0 */
+	u32 perfhpr0;		/* 0x1c4 */
+	u32 perfhpr1;		/* 0x1c8 */
+	u32 perflpr0;		/* 0x1cc */
+	u32 perflpr1;		/* 0x1d0 */
+	u32 perfwr0;		/* 0x1d4 */
+	u32 perfwr1;		/* 0x1d8 */
+};
+
+#define DXnGTR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
+#define DXnGCR0(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
+#define DXnGSR0(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
+#define DXnGSR1(x)	(SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
+#define DXnGSR2(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_RANK_MASK		(3 << 0)
+#define MCTL_CR_RANK(x)			(((x) - 1) << 0)
+#define MCTL_CR_BANK_MASK		(3 << 2)
+#define MCTL_CR_BANK(x)			((x) << 2)
+#define MCTL_CR_ROW_MASK		(0xf << 4)
+#define MCTL_CR_ROW(x)			(((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK		(0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x)		((fls(x) - 4) << 8)
+#define MCTL_CR_BUSW_MASK		(7 << 12)
+#define MCTL_CR_BUSW8			(0 << 12)
+#define MCTL_CR_BUSW16			(1 << 12)
+#define MCTL_CR_SEQUENCE		(1 << 15)
+#define MCTL_CR_DDR3			(3 << 16)
+#define MCTL_CR_CHANNEL_MASK		(1 << 19)
+#define MCTL_CR_CHANNEL(x)		(((x) - 1) << 19)
+#define MCTL_CR_UNKNOWN			(0x4 << 20)
+#define MCTL_CR_CS1_CONTROL(x)		((x) << 24)
+
+/* DRAM control (sunxi_mctl_ctl_reg) register constants */
+#define MCTL_MR0			0x1c70 /* CL=11, WR=12 */
+#define MCTL_MR1			0x40
+#define MCTL_MR2			0x18 /* CWL=8 */
+#define MCTL_MR3			0x0
+
+#endif /* _SUNXI_DRAM_SUN8I_A33_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
new file mode 100644
index 0000000..d4634e5
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sun8i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ *                         Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_A83T_H
+#define _SUNXI_DRAM_SUN8I_A83T_H
+
+struct sunxi_mctl_com_reg {
+	u32 cr;			/* 0x00 */
+	u32 ccr;		/* 0x04 controller configuration register */
+	u32 dbgcr;		/* 0x08 */
+	u8 res0[0x4];		/* 0x0c */
+	u32 mcr0_0;		/* 0x10 */
+	u32 mcr1_0;		/* 0x14 */
+	u32 mcr0_1;		/* 0x18 */
+	u32 mcr1_1;		/* 0x1c */
+	u32 mcr0_2;		/* 0x20 */
+	u32 mcr1_2;		/* 0x24 */
+	u32 mcr0_3;		/* 0x28 */
+	u32 mcr1_3;		/* 0x2c */
+	u32 mcr0_4;		/* 0x30 */
+	u32 mcr1_4;		/* 0x34 */
+	u32 mcr0_5;		/* 0x38 */
+	u32 mcr1_5;		/* 0x3c */
+	u32 mcr0_6;		/* 0x40 */
+	u32 mcr1_6;		/* 0x44 */
+	u32 mcr0_7;		/* 0x48 */
+	u32 mcr1_7;		/* 0x4c */
+	u32 mcr0_8;		/* 0x50 */
+	u32 mcr1_8;		/* 0x54 */
+	u32 mcr0_9;		/* 0x58 */
+	u32 mcr1_9;		/* 0x5c */
+	u32 mcr0_10;		/* 0x60 */
+	u32 mcr1_10;		/* 0x64 */
+	u32 mcr0_11;		/* 0x68 */
+	u32 mcr1_11;		/* 0x6c */
+	u32 mcr0_12;		/* 0x70 */
+	u32 mcr1_12;		/* 0x74 */
+	u32 mcr0_13;		/* 0x78 */
+	u32 mcr1_13;		/* 0x7c */
+	u32 mcr0_14;		/* 0x80 */
+	u32 mcr1_14;		/* 0x84 */
+	u32 mcr0_15;		/* 0x88 */
+	u32 mcr1_15;		/* 0x8c */
+	u32 bwcr;		/* 0x90 */
+	u32 maer;		/* 0x94 */
+	u32 mapr;		/* 0x98 */
+	u32 mcgcr;		/* 0x9c */
+	u32 bwctr;		/* 0xa0 */
+	u8 res2[0x8];		/* 0xa4 */
+	u32 swoffr;		/* 0xac */
+	u8 res3[0x10];		/* 0xb0 */
+	u32 swonr;		/* 0xc0 */
+	u8 res4[0x3c];		/* 0xc4 */
+	u32 mdfscr;		/* 0x100 */
+	u32 mdfsmer;		/* 0x104 */
+};
+
+struct sunxi_mctl_ctl_reg {
+	u32 pir;		/* 0x00 */
+	u32 pwrctl;		/* 0x04 */
+	u32 mrctrl0;		/* 0x08 */
+	u32 clken;		/* 0x0c */
+	u32 pgsr0;		/* 0x10 */
+	u32 pgsr1;		/* 0x14 */
+	u32 statr;		/* 0x18 */
+	u8 res1[0x14];		/* 0x1c */
+	u32 mr0;		/* 0x30 */
+	u32 mr1;		/* 0x34 */
+	u32 mr2;		/* 0x38 */
+	u32 mr3;		/* 0x3c */
+	u32 pllgcr;		/* 0x40 */
+	u32 ptr0;		/* 0x44 */
+	u32 ptr1;		/* 0x48 */
+	u32 ptr2;		/* 0x4c */
+	u32 ptr3;		/* 0x50 */
+	u32 ptr4;		/* 0x54 */
+	u32 dramtmg0;		/* 0x58 dram timing parameters register 0 */
+	u32 dramtmg1;		/* 0x5c dram timing parameters register 1 */
+	u32 dramtmg2;		/* 0x60 dram timing parameters register 2 */
+	u32 dramtmg3;		/* 0x64 dram timing parameters register 3 */
+	u32 dramtmg4;		/* 0x68 dram timing parameters register 4 */
+	u32 dramtmg5;		/* 0x6c dram timing parameters register 5 */
+	u32 dramtmg6;		/* 0x70 dram timing parameters register 6 */
+	u32 dramtmg7;		/* 0x74 dram timing parameters register 7 */
+	u32 dramtmg8;		/* 0x78 dram timing parameters register 8 */
+	u32 odtcfg;		/* 0x7c */
+	u32 pitmg0;		/* 0x80 */
+	u32 pitmg1;		/* 0x84 */
+	u8 res2[0x4];		/* 0x88 */
+	u32 rfshctl0;		/* 0x8c */
+	u32 rfshtmg;		/* 0x90 */
+	u32 rfshctl1;		/* 0x94 */
+	u32 pwrtmg;		/* 0x98 */
+	u8  res3[0x20];		/* 0x9c */
+	u32 dqsgmr;		/* 0xbc */
+	u32 dtcr;		/* 0xc0 */
+	u32 dtar0;		/* 0xc4 */
+	u32 dtar1;		/* 0xc8 */
+	u32 dtar2;		/* 0xcc */
+	u32 dtar3;		/* 0xd0 */
+	u32 dtdr0;		/* 0xd4 */
+	u32 dtdr1;		/* 0xd8 */
+	u32 dtmr0;		/* 0xdc */
+	u32 dtmr1;		/* 0xe0 */
+	u32 dtbmr;		/* 0xe4 */
+	u32 catr0;		/* 0xe8 */
+	u32 catr1;		/* 0xec */
+	u32 dtedr0;		/* 0xf0 */
+	u32 dtedr1;		/* 0xf4 */
+	u8 res4[0x8];		/* 0xf8 */
+	u32 pgcr0;		/* 0x100 */
+	u32 pgcr1;		/* 0x104 */
+	u32 pgcr2;		/* 0x108 */
+	u32 pgcr3;		/* 0x10c */
+	u32 iovcr0;		/* 0x110 */
+	u32 iovcr1;		/* 0x114 */
+	u32 dqsdr;		/* 0x118 */
+	u32 dxccr;		/* 0x11c */
+	u32 odtmap;		/* 0x120 */
+	u32 zqctl0;		/* 0x124 */
+	u32 zqctl1;		/* 0x128 */
+	u8 res6[0x14];		/* 0x12c */
+	u32 zqncr;		/* 0x140 zq control register 0 */
+	u32 zqnpr;		/* 0x144 zq control register 1 */
+	u32 zqndr;		/* 0x148 zq control register 2 */
+	u32 zqnsr;		/* 0x14c zq status register 0 */
+	u32 res7;		/* 0x150 zq status register 1 */
+	u8 res8[0x6c];		/* 0x154 */
+	u32 sched;		/* 0x1c0 */
+	u32 perfhpr0;		/* 0x1c4 */
+	u32 perfhpr1;		/* 0x1c8 */
+	u32 perflpr0;		/* 0x1cc */
+	u32 perflpr1;		/* 0x1d0 */
+	u32 perfwr0;		/* 0x1d4 */
+	u32 perfwr1;		/* 0x1d8 */
+};
+
+
+#define ZQnPR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x)
+#define ZQnDR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x)
+#define ZQnSR(x)	(SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x)
+
+#define DXnGTR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
+#define DXnGCR0(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
+#define DXnGSR0(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
+#define DXnGSR1(x)	(SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
+#define DXnGSR2(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
+
+#define CAIOCR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x))
+#define DXnMDLR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x)
+#define DXMDLR0		(SUNXI_DRAM_CTL0_BASE + 0x00000300)
+#define DXnLCDLR0(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000304 + 0x80 * x)
+#define DXnLCDLR1(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000308 + 0x80 * x)
+#define DXnLCDLR2(x)	(SUNXI_DRAM_CTL0_BASE + 0x0000030c + 0x80 * x)
+#define DATX0IOCR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000310 + 0x4 * x)
+#define DATX1IOCR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000390 + 0x4 * x)
+#define DATX2IOCR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000410 + 0x4 * x)
+#define DATX3IOCR(x)	(SUNXI_DRAM_CTL0_BASE + 0x00000490 + 0x4 * x)
+#define MX_UPD0		(SUNXI_DRAM_CTL0_BASE + 0x00000880)
+#define MX_UPD2		(SUNXI_DRAM_CTL0_BASE + 0x00000888)
+
+#define MCTL_PROTECT		(SUNXI_DRAM_COM_BASE + 0x800)
+#define MCTL_MASTER_CFG0(x)	(SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x)
+#define MCTL_MASTER_CFG1(x)	(SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x)
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_RANK_MASK		(3 << 0)
+#define MCTL_CR_RANK(x)			(((x) - 1) << 0)
+#define MCTL_CR_BANK_MASK		(3 << 2)
+#define MCTL_CR_BANK(x)			((x) << 2)
+#define MCTL_CR_ROW_MASK		(0xf << 4)
+#define MCTL_CR_ROW(x)			(((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK		(0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x)		((fls(x) - 4) << 8)
+#define MCTL_CR_BUSW_MASK		(7 << 12)
+#define MCTL_CR_BUSW8			(0 << 12)
+#define MCTL_CR_BUSW16			(1 << 12)
+#define MCTL_CR_SEQUENCE		(1 << 15)
+#define MCTL_CR_DRAM_TYPE(x)		((x) << 16)
+#define MCTL_CR_CHANNEL_MASK		(1 << 19)
+#define MCTL_CR_CHANNEL(x)		(((x) - 1) << 19)
+#define MCTL_CR_UNKNOWN			(0x4 << 20)
+#define MCTL_CR_CS1_CONTROL(x)		((x) << 24)
+
+/* DRAM control (sunxi_mctl_ctl_reg) register constants */
+#define MCTL_MR0			0x1c70 /* CL=11, WR=12 */
+#define MCTL_MR1			0x40
+#define MCTL_MR2			0x18 /* CWL=8 */
+#define MCTL_MR3			0x0
+
+#define MCTL_LPDDR3_MR0			0x0
+#define MCTL_LPDDR3_MR1			0xc3	/* twr=8, bl=8 */
+#define MCTL_LPDDR3_MR2			0xa	/* RL=12, CWL=6 */
+#define MCTL_LPDDR3_MR3			0x0
+
+#define DRAM_TYPE_DDR3		3
+#define DRAM_TYPE_LPDDR3	7
+#endif /* _SUNXI_DRAM_SUN8I_A83T_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h
new file mode 100644
index 0000000..603850b
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h
@@ -0,0 +1,277 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sun8i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ *                         Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2016  Theobroma Systems Design und Consulting GmbH
+ *                     Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+ */
+
+#ifndef _SUNXI_DRAM_SUN9I_H
+#define _SUNXI_DRAM_SUN9I_H
+
+struct sunxi_mctl_com_reg {
+	u32 cr;			/* 0x00 */
+	u32 ccr;		/* 0x04 controller configuration register */
+	u32 dbgcr;		/* 0x08 */
+	u32 dbgcr1;		/* 0x0c */
+	u32 rmcr;		/* 0x10 */
+	u8 res1[0x1c];		/* 0x14 */
+	u32 mmcr;		/* 0x30 */
+	u8 res2[0x3c];		/* 0x34 */
+	u32 mbagcr;		/* 0x70 */
+	u32 mbacr;		/* 0x74 */
+	u8 res3[0x10];		/* 0x78 */
+	u32 maer;		/* 0x88 */
+	u8 res4[0x74];		/* 0x8c */
+	u32 mdfscr;		/* 0x100 */
+	u32 mdfsmer;		/* 0x104 */
+	u32 mdfsmrmr;		/* 0x108 */
+	u32 mdfstr[4];		/* 0x10c */
+	u32 mdfsgcr;		/* 0x11c */
+	u8 res5[0x1c];		/* 0x120 */
+	u32 mdfsivr;		/* 0x13c */
+	u8 res6[0xc];		/* 0x140 */
+	u32 mdfstcr;		/* 0x14c */
+};
+
+
+struct sunxi_mctl_ctl_reg {
+	u32 mstr;		/* 0x00 master register */
+	u32 stat;		/* 0x04 operating mode status register */
+	u8 res1[0x8];		/* 0x08 */
+	u32 mrctrl[2];		/* 0x10 mode register read/write control reg */
+	u32 mstat;		/* 0x18 mode register read/write status reg */
+	u8 res2[0x4];		/* 0x1c */
+	u32 derateen;		/* 0x20 temperature derate enable register */
+	u32 derateint;		/* 0x24 temperature derate interval register */
+	u8 res3[0x8];		/* 0x28 */
+	u32 pwrctl;		/* 0x30 low power control register */
+	u32 pwrtmg;		/* 0x34 low power timing register */
+	u8 res4[0x18];		/* 0x38 */
+	u32 rfshctl0;		/* 0x50 refresh control register 0 */
+	u32 rfshctl1;		/* 0x54 refresh control register 1 */
+	u8 res5[0x8];		/* 0x58 */
+	u32 rfshctl3;		/* 0x60 refresh control register 3 */
+	u32 rfshtmg;		/* 0x64 refresh timing register */
+	u8 res6[0x68];		/* 0x68 */
+	u32 init[6];		/* 0xd0 SDRAM initialisation register */
+	u8 res7[0xc];		/* 0xe8 */
+	u32 rankctl;		/* 0xf4 rank control register */
+	u8 res8[0x8];		/* 0xf8 */
+	u32 dramtmg[9];		/* 0x100 DRAM timing register */
+	u8 res9[0x5c];		/* 0x124 */
+	u32 zqctrl[3];		/* 0x180 ZQ control register */
+	u32 zqstat;		/* 0x18c ZQ status register */
+	u32 dfitmg[2];		/* 0x190 DFI timing register */
+	u32 dfilpcfg;		/* 0x198 DFI low power configuration register */
+	u8 res10[0x4];		/* 0x19c */
+	u32 dfiupd[4];		/* 0x1a0 DFI update register */
+	u32 dfimisc;		/* 0x1b0 DFI miscellaneous control register */
+	u8 res11[0x1c];		/* 0x1b4 */
+	u32 trainctl[3];	/* 0x1d0 */
+	u32 trainstat;	        /* 0x1dc */
+	u8 res12[0x20];		/* 0x1e0 */
+	u32 addrmap[7];	        /* 0x200 address map register */
+	u8 res13[0x24];		/* 0x21c */
+	u32 odtcfg;		/* 0x240 ODT configuration register */
+	u32 odtmap;		/* 0x244 ODT/rank map register */
+	u8 res14[0x8];		/* 0x248 */
+	u32 sched;		/* 0x250 scheduler control register */
+	u8 res15[0x4];		/* 0x254 */
+	u32 perfhpr0;		/* 0x258 high priority read CAM register 0 */
+	u32 perfhpr1;		/* 0x25c high priority read CAM register 1 */
+	u32 perflpr0;		/* 0x260 low priority read CAM register 0 */
+	u32 perflpr1;		/* 0x264 low priority read CAM register 1 */
+	u32 perfwr0;		/* 0x268 write CAM register 0 */
+	u32 perfwr1;		/* 0x26c write CAM register 1 */
+};
+
+
+struct sunxi_mctl_phy_reg {
+	u8 res0[0x04];		/* 0x00 revision id ??? */
+	u32 pir;		/* 0x04 PHY initialisation register */
+	u32 pgcr[4];		/* 0x08 PHY general configuration register */
+	u32 pgsr[2];		/* 0x18 PHY general status register */
+	u32 pllcr;		/* 0x20 PLL control register */
+	u32 ptr[5];		/* 0x24 PHY timing register */
+	u32 acmdlr;		/* 0x38 AC master delay line register */
+	u32 aclcdlr;		/* 0x3c AC local calibrated delay line reg */
+	u32 acbdlr[10];		/* 0x40 AC bit delay line register */
+	u32 aciocr[6];		/* 0x68 AC IO configuration register */
+	u32 dxccr;		/* 0x80 DATX8 common configuration register */
+	u32 dsgcr;		/* 0x84 DRAM system general config register */
+	u32 dcr;		/* 0x88 DRAM configuration register */
+	u32 dtpr[4];		/* 0x8c DRAM timing parameters register */
+	u32 mr0;		/* 0x9c mode register 0 */
+	u32 mr1;		/* 0xa0 mode register 1 */
+	u32 mr2;		/* 0xa4 mode register 2 */
+	u32 mr3;		/* 0xa8 mode register 3 */
+	u32 odtcr;		/* 0xac ODT configuration register */
+	u32 dtcr;		/* 0xb0 data training configuration register */
+	u32 dtar[4];		/* 0xb4 data training address register */
+	u32 dtdr[2];		/* 0xc4 data training data register */
+	u32 dtedr[2];		/* 0xcc data training eye data register */
+	u32 rdimmgcr[2];	/* 0xd4 RDIMM general configuration register */
+	u32 rdimmcr[2];		/* 0xdc RDIMM control register */
+	u32 gpr[2];		/* 0xe4 general purpose register */
+	u32 catr[2];		/* 0xec CA training register */
+	u32 dqdsr;		/* 0xf4 DQS drift register */
+	u8 res1[0xc8];		/* 0xf8 */
+	u32 bistrr;		/* 0x1c0 BIST run register */
+	u32 bistwcr;		/* 0x1c4 BIST word count register */
+	u32 bistmskr[3];	/* 0x1c8 BIST mask register */
+	u32 bistlsr;		/* 0x1d4 BIST LFSR seed register */
+	u32 bistar[3];		/* 0x1d8 BIST address register */
+	u32 bistupdr;		/* 0x1e4 BIST user pattern data register */
+	u32 bistgsr;		/* 0x1e8 BIST general status register */
+	u32 bistwer;		/* 0x1dc BIST word error register */
+	u32 bistber[4];		/* 0x1f0 BIST bit error register */
+	u32 bistwcsr;		/* 0x200 BIST word count status register */
+	u32 bistfwr[3];		/* 0x204 BIST fail word register */
+	u8 res2[0x28];		/* 0x210 */
+	u32 iovcr[2];		/* 0x238 IO VREF control register */
+	struct ddrphy_zq {
+		u32 cr;              /* impedance control register */
+		u32 pr;              /* impedance control data register */
+		u32 dr;              /* impedance control data register */
+		u32 sr;              /* impedance control status register */
+	} zq[4];                /* 0x240, 0x250, 0x260, 0x270 */
+	struct ddrphy_dx {
+		u32 gcr[4];          /* DATX8 general configuration register */
+		u32 gsr[3];          /* DATX8 general status register */
+		u32 bdlr[7];         /* DATX8 bit delay line register */
+		u32 lcdlr[3];        /* DATX8 local calibrated delay line reg */
+		u32 mdlr;            /* DATX8 master delay line register */
+		u32 gtr;             /* DATX8 general timing register */
+		u8 res[0x34];
+	} dx[4];                /* 0x280, 0x300, 0x380, 0x400 */
+};
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_RANK_MASK		(3 << 0)
+#define MCTL_CR_RANK(x)			(((x) - 1) << 0)
+#define MCTL_CR_BANK_MASK		(3 << 2)
+#define MCTL_CR_BANK(x)			((x) << 2)
+#define MCTL_CR_ROW_MASK		(0xf << 4)
+#define MCTL_CR_ROW(x)			(((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK		(0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x)		((fls(x) - 4) << 8)
+#define MCTL_CR_BUSW_MASK		(3 << 12)
+#define MCTL_CR_BUSW16			(1 << 12)
+#define MCTL_CR_BUSW32			(3 << 12)
+#define MCTL_CR_DRAMTYPE_MASK           (7 << 16)
+#define MCTL_CR_DRAMTYPE_DDR2		(2 << 16)
+#define MCTL_CR_DRAMTYPE_DDR3		(3 << 16)
+#define MCTL_CR_DRAMTYPE_LPDDR2		(6 << 16)
+
+#define MCTL_CR_CHANNEL_MASK		((1 << 22) | (1 << 20) | (1 << 19))
+#define MCTL_CR_CHANNEL_SINGLE          (1 << 22)
+#define MCTL_CR_CHANNEL_DUAL            ((1 << 22) | (1 << 20) | (1 << 19))
+
+#define MCTL_CCR_CH0_CLK_EN		(1 << 15)
+#define MCTL_CCR_CH1_CLK_EN		(1 << 31)
+
+/*
+ * post_cke_x1024 [bits 16..25]: Cycles to wait after driving CKE high
+ * to start the SDRAM initialization sequence (in 1024s of cycles).
+ */
+#define MCTL_INIT0_POST_CKE_x1024(n)    ((n & 0x0fff) << 16)
+/*
+ * pre_cke_x1024 [bits 0..11] Cycles to wait after reset before driving
+ * CKE high to start the SDRAM initialization (in 1024s of cycles)
+ */
+#define MCTL_INIT0_PRE_CKE_x1024(n)     ((n & 0x0fff) <<  0)
+#define MCTL_INIT1_DRAM_RSTN_x1024(n)   ((n & 0xff) << 16)
+#define MCTL_INIT1_FINAL_WAIT_x32(n)    ((n & 0x3f) <<  8)
+#define MCTL_INIT1_PRE_OCD_x32(n)       ((n & 0x0f) <<  0)
+#define MCTL_INIT2_IDLE_AFTER_RESET_x32(n)  ((n & 0xff) << 8)
+#define MCTL_INIT2_MIN_STABLE_CLOCK_x1(n)   ((n & 0x0f) << 0)
+#define MCTL_INIT3_MR(n)                ((n & 0xffff) << 16)
+#define MCTL_INIT3_EMR(n)               ((n & 0xffff) <<  0)
+#define MCTL_INIT4_EMR2(n)              ((n & 0xffff) << 16)
+#define MCTL_INIT4_EMR3(n)              ((n & 0xffff) <<  0)
+#define MCTL_INIT5_DEV_ZQINIT_x32(n)        ((n & 0x00ff) << 16)
+#define MCTL_INIT5_MAX_AUTO_INIT_x1024(n)   ((n & 0x03ff) <<  0);
+
+#define MCTL_DFIMISC_DFI_INIT_COMPLETE_EN  (1 << 0)
+#define MCTL_DFIUPD0_DIS_AUTO_CTRLUPD      (1 << 31)
+
+#define MCTL_MSTR_DEVICETYPE_DDR3          1
+#define MCTL_MSTR_DEVICETYPE_LPDDR2        4
+#define MCTL_MSTR_DEVICETYPE_LPDDR3        8
+#define MCTL_MSTR_DEVICETYPE(type) \
+	((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_DEVICETYPE_DDR3 : \
+		((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_DEVICETYPE_LPDDR2 : \
+					      MCTL_MSTR_DEVICETYPE_LPDDR3))
+#define MCTL_MSTR_BURSTLENGTH4             (2 << 16)
+#define MCTL_MSTR_BURSTLENGTH8             (4 << 16)
+#define MCTL_MSTR_BURSTLENGTH16            (8 << 16)
+#define MCTL_MSTR_BURSTLENGTH(type) \
+	((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_BURSTLENGTH8 : \
+		((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_BURSTLENGTH4 : \
+					      MCTL_MSTR_BURSTLENGTH8))
+#define MCTL_MSTR_ACTIVERANKS(x)           (((x == 2) ? 3 : 1) << 24)
+#define MCTL_MSTR_BUSWIDTH8                (2 << 12)
+#define MCTL_MSTR_BUSWIDTH16               (1 << 12)
+#define MCTL_MSTR_BUSWIDTH32               (0 << 12)
+#define MCTL_MSTR_2TMODE                   (1 << 10)
+
+#define MCTL_RFSHCTL3_DIS_AUTO_REFRESH     (1 << 0)
+
+#define MCTL_ZQCTRL0_TZQCS(x)              (x << 0)
+#define MCTL_ZQCTRL0_TZQCL(x)              (x << 16)
+#define MCTL_ZQCTRL0_ZQCL_DIS              (1 << 30)
+#define MCTL_ZQCTRL0_ZQCS_DIS              (1 << 31)
+#define MCTL_ZQCTRL1_TZQRESET(x)           (x << 20)
+#define MCTL_ZQCTRL1_TZQSI_x1024(x)        (x << 0)
+#define MCTL_ZQCTRL2_TZRESET_TRIGGER       (1 << 0)
+
+#define MCTL_PHY_DCR_BYTEMASK              (1 << 10)
+#define MCTL_PHY_DCR_2TMODE                (1 << 28)
+#define MCTL_PHY_DCR_DDR8BNK               (1 << 3)
+#define MCTL_PHY_DRAMMODE_DDR3             3
+#define MCTL_PHY_DRAMMODE_LPDDR2           0
+#define MCTL_PHY_DRAMMODE_LPDDR3           1
+
+#define MCTL_DTCR_DEFAULT                  0x00003007
+#define MCTL_DTCR_RANKEN(n)                (((n == 2) ? 3 : 1) << 24)
+
+#define MCTL_PGCR1_ZCKSEL_MASK             (3 << 23)
+#define MCTL_PGCR1_IODDRM_MASK             (3 << 7)
+#define MCTL_PGCR1_IODDRM_DDR3             (1 << 7)
+#define MCTL_PGCR1_IODDRM_DDR3L            (2 << 7)
+#define MCTL_PGCR1_INHVT_EN                (1 << 26)
+
+#define MCTL_PLLGCR_PLL_BYPASS             (1 << 31)
+#define MCTL_PLLGCR_PLL_POWERDOWN          (1 << 29)
+
+#define MCTL_PIR_PLL_BYPASS                (1 << 17)
+#define MCTL_PIR_MASK                      (~(1 << 17))
+#define MCTL_PIR_INIT                      (1 << 0)
+
+#define MCTL_PGSR0_ERRORS                  (0x1ff << 20)
+
+/* Constants for assembling MR0 */
+#define DDR3_MR0_PPD_FAST_EXIT             (1 << 12)
+#define DDR3_MR0_WR(n) \
+	((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
+#define DDR3_MR0_CL(n) \
+	((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
+#define DDR3_MR0_BL8                       (0 << 0)
+
+#define DDR3_MR1_RTT120OHM                 ((0 << 9) | (1 << 6) | (0 << 2))
+
+#define DDR3_MR2_TWL(n) \
+	(((n - 5) & 0x7) << 3)
+
+#define MCTL_NS2CYCLES_CEIL(ns)	((ns * (CONFIG_DRAM_CLK / 2) + 999) / 1000)
+
+#define DRAM_TYPE_DDR3		3
+#define DRAM_TYPE_LPDDR2	6
+#define DRAM_TYPE_LPDDR3	7
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
new file mode 100644
index 0000000..a5a7ebd
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
@@ -0,0 +1,238 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * sun8i H3 platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ *                         Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2015      Jens Kuske <jenskuske@gmail.com>
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_H3_H
+#define _SUNXI_DRAM_SUN8I_H3_H
+
+#include <linux/bitops.h>
+
+struct sunxi_mctl_com_reg {
+	u32 cr;			/* 0x00 control register */
+	u32 cr_r1;		/* 0x04 rank 1 control register (R40 only) */
+	u8 res0[0x4];		/* 0x08 */
+	u32 tmr;		/* 0x0c (unused on H3) */
+	u32 mcr[16][2];		/* 0x10 */
+	u32 bwcr;		/* 0x90 bandwidth control register */
+	u32 maer;		/* 0x94 master enable register */
+	u32 mapr;		/* 0x98 master priority register */
+	u32 mcgcr;		/* 0x9c */
+	u32 cpu_bwcr;		/* 0xa0 */
+	u32 gpu_bwcr;		/* 0xa4 */
+	u32 ve_bwcr;		/* 0xa8 */
+	u32 disp_bwcr;		/* 0xac */
+	u32 other_bwcr;		/* 0xb0 */
+	u32 total_bwcr;		/* 0xb4 */
+	u8 res1[0x8];		/* 0xb8 */
+	u32 swonr;		/* 0xc0 */
+	u32 swoffr;		/* 0xc4 */
+	u8 res2[0x8];		/* 0xc8 */
+	u32 cccr;		/* 0xd0 */
+	u8 res3[0x54];		/* 0xd4 */
+	u32 mdfs_bwlr[3];	/* 0x128 (unused on H3) */
+	u8 res4[0x6cc];		/* 0x134 */
+	u32 protect;		/* 0x800 */
+};
+
+#define MCTL_CR_BL8		(0x4 << 20)
+
+#define MCTL_CR_1T		(0x1 << 19)
+#define MCTL_CR_2T		(0x0 << 19)
+
+#define MCTL_CR_LPDDR3		(0x7 << 16)
+#define MCTL_CR_LPDDR2		(0x6 << 16)
+#define MCTL_CR_DDR3		(0x3 << 16)
+#define MCTL_CR_DDR2		(0x2 << 16)
+
+#define MCTL_CR_SEQUENTIAL	(0x1 << 15)
+#define MCTL_CR_INTERLEAVED	(0x0 << 15)
+
+#define MCTL_CR_FULL_WIDTH	(0x1 << 12)
+#define MCTL_CR_HALF_WIDTH	(0x0 << 12)
+#define MCTL_CR_BUS_FULL_WIDTH(x)	((x) << 12)
+
+#define MCTL_CR_PAGE_SIZE(x)	((fls(x) - 4) << 8)
+#define MCTL_CR_ROW_BITS(x)	(((x) - 1) << 4)
+#define MCTL_CR_EIGHT_BANKS	(0x1 << 2)
+#define MCTL_CR_FOUR_BANKS	(0x0 << 2)
+#define MCTL_CR_DUAL_RANK	(0x1 << 0)
+#define MCTL_CR_SINGLE_RANK	(0x0 << 0)
+
+/*
+ * CR_R1 is a register found in the R40's DRAM controller. It sets various
+ * parameters for rank 1. Bits [11:0] have the same meaning as the bits in
+ * MCTL_CR, but they apply to rank 1 only. This implies we can have
+ * different chips for rank 1 than rank 0.
+ *
+ * As address line A15 and CS1 chip select for rank 1 are muxed on the same
+ * pin, if single rank is used, A15 must be muxed in.
+ */
+#define MCTL_CR_R1_MUX_A15	(0x1 << 21)
+
+#define PROTECT_MAGIC		(0x94be6fa3)
+
+struct sunxi_mctl_ctl_reg {
+	u32 pir;		/* 0x00 PHY initialization register */
+	u32 pwrctl;		/* 0x04 */
+	u32 mrctrl;		/* 0x08 */
+	u32 clken;		/* 0x0c */
+	u32 pgsr[2];		/* 0x10 PHY general status registers */
+	u32 statr;		/* 0x18 */
+	u8 res1[0x10];		/* 0x1c */
+	u32 lp3mr11;		/* 0x2c */
+	u32 mr[4];		/* 0x30 mode registers */
+	u32 pllgcr;		/* 0x40 */
+	u32 ptr[5];		/* 0x44 PHY timing registers */
+	u32 dramtmg[9];		/* 0x58 DRAM timing registers */
+	u32 odtcfg;		/* 0x7c */
+	u32 pitmg[2];		/* 0x80 PHY interface timing registers */
+	u8 res2[0x4];		/* 0x88 */
+	u32 rfshctl0;		/* 0x8c */
+	u32 rfshtmg;		/* 0x90 refresh timing */
+	u32 rfshctl1;		/* 0x94 */
+	u32 pwrtmg;		/* 0x98 */
+	u8 res3[0x1c];		/* 0x9c */
+	u32 vtfcr;		/* 0xb8 (unused on H3) */
+	u32 dqsgmr;		/* 0xbc */
+	u32 dtcr;		/* 0xc0 */
+	u32 dtar[4];		/* 0xc4 */
+	u32 dtdr[2];		/* 0xd4 */
+	u32 dtmr[2];		/* 0xdc */
+	u32 dtbmr;		/* 0xe4 */
+	u32 catr[2];		/* 0xe8 */
+	u32 dtedr[2];		/* 0xf0 */
+	u8 res4[0x8];		/* 0xf8 */
+	u32 pgcr[4];		/* 0x100 PHY general configuration registers */
+	u32 iovcr[2];		/* 0x110 */
+	u32 dqsdr;		/* 0x118 */
+	u32 dxccr;		/* 0x11c */
+	u32 odtmap;		/* 0x120 */
+	u32 zqctl[2];		/* 0x124 */
+	u8 res6[0x14];		/* 0x12c */
+	u32 zqcr;		/* 0x140 ZQ control register */
+	u32 zqsr;		/* 0x144 ZQ status register */
+	u32 zqdr[3];		/* 0x148 ZQ data registers */
+	u8 res7[0x6c];		/* 0x154 */
+	u32 sched;		/* 0x1c0 */
+	u32 perfhpr[2];		/* 0x1c4 */
+	u32 perflpr[2];		/* 0x1cc */
+	u32 perfwr[2];		/* 0x1d4 */
+	u8 res8[0x24];		/* 0x1dc */
+	u32 acmdlr;		/* 0x200 AC master delay line register */
+	u32 aclcdlr;		/* 0x204 AC local calibrated delay line register */
+	u32 aciocr;		/* 0x208 AC I/O configuration register */
+	u8 res9[0x4];		/* 0x20c */
+	u32 acbdlr[31];		/* 0x210 AC bit delay line registers */
+	u8 res10[0x74];		/* 0x28c */
+	struct {		/* 0x300 DATX8 modules*/
+		u32 mdlr;		/* 0x00 master delay line register */
+		u32 lcdlr[3];		/* 0x04 local calibrated delay line registers */
+		u32 bdlr[11];		/* 0x10 bit delay line registers */
+		u32 sdlr;		/* 0x3c output enable bit delay registers */
+		u32 gtr;		/* 0x40 general timing register */
+		u32 gcr;		/* 0x44 general configuration register */
+		u32 gsr[3];		/* 0x48 general status registers */
+		u8 res0[0x2c];		/* 0x54 */
+	} dx[4];
+	u8 res11[0x388];	/* 0x500 */
+	u32 upd2;		/* 0x888 */
+};
+
+#define PTR3_TDINIT1(x)		((x) << 20)
+#define PTR3_TDINIT0(x)		((x) <<  0)
+
+#define PTR4_TDINIT3(x)		((x) << 20)
+#define PTR4_TDINIT2(x)		((x) <<  0)
+
+#define DRAMTMG0_TWTP(x)	((x) << 24)
+#define DRAMTMG0_TFAW(x)	((x) << 16)
+#define DRAMTMG0_TRAS_MAX(x)	((x) <<  8)
+#define DRAMTMG0_TRAS(x)	((x) <<  0)
+
+#define DRAMTMG1_TXP(x)		((x) << 16)
+#define DRAMTMG1_TRTP(x)	((x) <<  8)
+#define DRAMTMG1_TRC(x)		((x) <<  0)
+
+#define DRAMTMG2_TCWL(x)	((x) << 24)
+#define DRAMTMG2_TCL(x)		((x) << 16)
+#define DRAMTMG2_TRD2WR(x)	((x) <<  8)
+#define DRAMTMG2_TWR2RD(x)	((x) <<  0)
+
+#define DRAMTMG3_TMRW(x)	((x) << 16)
+#define DRAMTMG3_TMRD(x)	((x) << 12)
+#define DRAMTMG3_TMOD(x)	((x) <<  0)
+
+#define DRAMTMG4_TRCD(x)	((x) << 24)
+#define DRAMTMG4_TCCD(x)	((x) << 16)
+#define DRAMTMG4_TRRD(x)	((x) <<  8)
+#define DRAMTMG4_TRP(x)		((x) <<  0)
+
+#define DRAMTMG5_TCKSRX(x)	((x) << 24)
+#define DRAMTMG5_TCKSRE(x)	((x) << 16)
+#define DRAMTMG5_TCKESR(x)	((x) <<  8)
+#define DRAMTMG5_TCKE(x)	((x) <<  0)
+
+#define RFSHTMG_TREFI(x)	((x) << 16)
+#define RFSHTMG_TRFC(x)		((x) <<  0)
+
+#define PIR_CLRSR	(0x1 << 27)	/* clear status registers */
+#define PIR_QSGATE	(0x1 << 10)	/* Read DQS gate training */
+#define PIR_DRAMINIT	(0x1 << 8)	/* DRAM initialization */
+#define PIR_DRAMRST	(0x1 << 7)	/* DRAM reset */
+#define PIR_PHYRST	(0x1 << 6)	/* PHY reset */
+#define PIR_DCAL	(0x1 << 5)	/* DDL calibration */
+#define PIR_PLLINIT	(0x1 << 4)	/* PLL initialization */
+#define PIR_ZCAL	(0x1 << 1)	/* ZQ calibration */
+#define PIR_INIT	(0x1 << 0)	/* PHY initialization trigger */
+
+#define PGSR_INIT_DONE	(0x1 << 0)	/* PHY init done */
+
+#define ZQCR_PWRDOWN	(1U << 31)	/* ZQ power down */
+
+#define ACBDLR_WRITE_DELAY(x)	((x) << 8)
+
+#define DXBDLR_DQ(x)	(x)		/* DQ0-7 BDLR index */
+#define DXBDLR_DM	8		/* DM BDLR index */
+#define DXBDLR_DQS	9		/* DQS BDLR index */
+#define DXBDLR_DQSN	10		/* DQSN BDLR index */
+
+#define DXBDLR_WRITE_DELAY(x)	((x) << 8)
+#define DXBDLR_READ_DELAY(x)	((x) << 0)
+
+/*
+ * The delay parameters below allow to allegedly specify delay times of some
+ * unknown unit for each individual bit trace in each of the four data bytes
+ * the 32-bit wide access consists of. Also three control signals can be
+ * adjusted individually.
+ */
+#define NR_OF_BYTE_LANES	(32 / BITS_PER_BYTE)
+/* The eight data lines (DQn) plus DM, DQS and DQSN */
+#define LINES_PER_BYTE_LANE	(BITS_PER_BYTE + 3)
+struct dram_para {
+	u16 page_size;
+	u8 bus_full_width;
+	u8 dual_rank;
+	u8 row_bits;
+	u8 bank_bits;
+	const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+	const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+	const u8 ac_delays[31];
+};
+
+static inline int ns_to_t(int nanoseconds)
+{
+	const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
+
+	return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para);
+
+#endif /* _SUNXI_DRAM_SUN8I_H3_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
new file mode 100644
index 0000000..40a3f84
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#ifndef _SUNXI_GPIO_H
+#define _SUNXI_GPIO_H
+
+#include <linux/types.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * sunxi has 9 banks of gpio, they are:
+ * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
+ * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
+ * PG0 - PG9  | PH0 - PH27 | PI0 - PI12
+ */
+
+#define SUNXI_GPIO_A	0
+#define SUNXI_GPIO_B	1
+#define SUNXI_GPIO_C	2
+#define SUNXI_GPIO_D	3
+#define SUNXI_GPIO_E	4
+#define SUNXI_GPIO_F	5
+#define SUNXI_GPIO_G	6
+#define SUNXI_GPIO_H	7
+#define SUNXI_GPIO_I	8
+
+/*
+ * This defines the number of GPIO banks for the _main_ GPIO controller.
+ * You should fix up the padding in struct sunxi_gpio_reg below if you
+ * change this.
+ */
+#define SUNXI_GPIO_BANKS 9
+
+/*
+ * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
+ * at a different register offset.
+ *
+ * sun6i has 2 banks:
+ * PL0 - PL8  | PM0 - PM7
+ *
+ * sun8i has 1 bank:
+ * PL0 - PL11
+ *
+ * sun9i has 3 banks:
+ * PL0 - PL9  | PM0 - PM15  | PN0 - PN1
+ */
+#define SUNXI_GPIO_L	11
+#define SUNXI_GPIO_M	12
+#define SUNXI_GPIO_N	13
+
+struct sunxi_gpio {
+	u32 cfg[4];
+	u32 dat;
+	u32 drv[2];
+	u32 pull[2];
+};
+
+/* gpio interrupt control */
+struct sunxi_gpio_int {
+	u32 cfg[3];
+	u32 ctl;
+	u32 sta;
+	u32 deb;		/* interrupt debounce */
+};
+
+struct sunxi_gpio_reg {
+	struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
+	u8 res[0xbc];
+	struct sunxi_gpio_int gpio_int;
+};
+
+#define BANK_TO_GPIO(bank)	(((bank) < SUNXI_GPIO_L) ? \
+	&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
+	&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
+
+#define GPIO_BANK(pin)		((pin) >> 5)
+#define GPIO_NUM(pin)		((pin) & 0x1f)
+
+#define GPIO_CFG_INDEX(pin)	(((pin) & 0x1f) >> 3)
+#define GPIO_CFG_OFFSET(pin)	((((pin) & 0x1f) & 0x7) << 2)
+
+#define GPIO_DRV_INDEX(pin)	(((pin) & 0x1f) >> 4)
+#define GPIO_DRV_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
+
+#define GPIO_PULL_INDEX(pin)	(((pin) & 0x1f) >> 4)
+#define GPIO_PULL_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
+
+/* GPIO bank sizes */
+#define SUNXI_GPIO_A_NR		32
+#define SUNXI_GPIO_B_NR		32
+#define SUNXI_GPIO_C_NR		32
+#define SUNXI_GPIO_D_NR		32
+#define SUNXI_GPIO_E_NR		32
+#define SUNXI_GPIO_F_NR		32
+#define SUNXI_GPIO_G_NR		32
+#define SUNXI_GPIO_H_NR		32
+#define SUNXI_GPIO_I_NR		32
+#define SUNXI_GPIO_L_NR		32
+#define SUNXI_GPIO_M_NR		32
+
+#define SUNXI_GPIO_NEXT(__gpio) \
+	((__gpio##_START) + (__gpio##_NR) + 0)
+
+enum sunxi_gpio_number {
+	SUNXI_GPIO_A_START = 0,
+	SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),
+	SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),
+	SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),
+	SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),
+	SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),
+	SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
+	SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
+	SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
+	SUNXI_GPIO_L_START = 352,
+	SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
+	SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
+	SUNXI_GPIO_AXP0_START = 1024,
+};
+
+/* SUNXI GPIO number definitions */
+#define SUNXI_GPA(_nr)	(SUNXI_GPIO_A_START + (_nr))
+#define SUNXI_GPB(_nr)	(SUNXI_GPIO_B_START + (_nr))
+#define SUNXI_GPC(_nr)	(SUNXI_GPIO_C_START + (_nr))
+#define SUNXI_GPD(_nr)	(SUNXI_GPIO_D_START + (_nr))
+#define SUNXI_GPE(_nr)	(SUNXI_GPIO_E_START + (_nr))
+#define SUNXI_GPF(_nr)	(SUNXI_GPIO_F_START + (_nr))
+#define SUNXI_GPG(_nr)	(SUNXI_GPIO_G_START + (_nr))
+#define SUNXI_GPH(_nr)	(SUNXI_GPIO_H_START + (_nr))
+#define SUNXI_GPI(_nr)	(SUNXI_GPIO_I_START + (_nr))
+#define SUNXI_GPL(_nr)	(SUNXI_GPIO_L_START + (_nr))
+#define SUNXI_GPM(_nr)	(SUNXI_GPIO_M_START + (_nr))
+#define SUNXI_GPN(_nr)	(SUNXI_GPIO_N_START + (_nr))
+
+#define SUNXI_GPAXP0(_nr)	(SUNXI_GPIO_AXP0_START + (_nr))
+
+/* GPIO pin function config */
+#define SUNXI_GPIO_INPUT	0
+#define SUNXI_GPIO_OUTPUT	1
+#define SUNXI_GPIO_DISABLE	7
+
+#define SUNXI_GPA_EMAC		2
+#define SUN6I_GPA_GMAC		2
+#define SUN7I_GPA_GMAC		5
+#define SUN6I_GPA_SDC2		5
+#define SUN6I_GPA_SDC3		4
+#define SUN8I_H3_GPA_UART0	2
+
+#define SUN4I_GPB_PWM		2
+#define SUN4I_GPB_TWI0		2
+#define SUN4I_GPB_TWI1		2
+#define SUN5I_GPB_TWI1		2
+#define SUN4I_GPB_TWI2		2
+#define SUN5I_GPB_TWI2		2
+#define SUN4I_GPB_UART0		2
+#define SUN5I_GPB_UART0		2
+#define SUN8I_GPB_UART2		2
+#define SUN8I_A33_GPB_UART0	3
+#define SUN8I_A83T_GPB_UART0	2
+#define SUN8I_V3S_GPB_UART0	3
+#define SUN50I_GPB_UART0	4
+
+#define SUNXI_GPC_NAND		2
+#define SUNXI_GPC_SPI0		3
+#define SUNXI_GPC_SDC2		3
+#define SUN6I_GPC_SDC3		4
+#define SUN50I_GPC_SPI0		4
+
+#define SUN8I_GPD_SDC1		3
+#define SUNXI_GPD_LCD0		2
+#define SUNXI_GPD_LVDS0		3
+#define SUNXI_GPD_PWM		2
+
+#define SUN5I_GPE_SDC2		3
+#define SUN8I_GPE_TWI2		3
+#define SUN50I_GPE_TWI2		3
+
+#define SUNXI_GPF_SDC0		2
+#define SUNXI_GPF_UART0		4
+#define SUN8I_GPF_UART0		3
+
+#define SUN4I_GPG_SDC1		4
+#define SUN5I_GPG_SDC1		2
+#define SUN6I_GPG_SDC1		2
+#define SUN8I_GPG_SDC1		2
+#define SUN6I_GPG_TWI3		2
+#define SUN5I_GPG_UART1		4
+
+#define SUN6I_GPH_PWM		2
+#define SUN8I_GPH_PWM		2
+#define SUN4I_GPH_SDC1		5
+#define SUN6I_GPH_TWI0		2
+#define SUN8I_GPH_TWI0		2
+#define SUN50I_GPH_TWI0		2
+#define SUN6I_GPH_TWI1		2
+#define SUN8I_GPH_TWI1		2
+#define SUN50I_GPH_TWI1		2
+#define SUN6I_GPH_TWI2		2
+#define SUN6I_GPH_UART0		2
+#define SUN9I_GPH_UART0		2
+#define SUN50I_H6_GPH_UART0	2
+
+#define SUNXI_GPI_SDC3		2
+#define SUN7I_GPI_TWI3		3
+#define SUN7I_GPI_TWI4		3
+
+#define SUN6I_GPL0_R_P2WI_SCK	3
+#define SUN6I_GPL1_R_P2WI_SDA	3
+
+#define SUN8I_GPL_R_RSB		2
+#define SUN8I_H3_GPL_R_TWI	2
+#define SUN8I_A23_GPL_R_TWI	3
+#define SUN8I_GPL_R_UART	2
+#define SUN50I_GPL_R_TWI	2
+
+#define SUN9I_GPN_R_RSB		3
+
+/* GPIO pin pull-up/down config */
+#define SUNXI_GPIO_PULL_DISABLE	0
+#define SUNXI_GPIO_PULL_UP	1
+#define SUNXI_GPIO_PULL_DOWN	2
+
+/* Virtual AXP0 GPIOs */
+#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
+#define SUNXI_GPIO_AXP0_VBUS_DETECT	4
+#define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
+#define SUNXI_GPIO_AXP0_GPIO_COUNT	6
+
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
+int sunxi_gpio_get_cfgpin(u32 pin);
+int sunxi_gpio_set_drv(u32 pin, u32 val);
+int sunxi_gpio_set_pull(u32 pin, u32 val);
+int sunxi_name_to_gpio_bank(const char *name);
+int sunxi_name_to_gpio(const char *name);
+#define name_to_gpio(name) sunxi_name_to_gpio(name)
+
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
+int axp_gpio_init(void);
+#else
+static inline int axp_gpio_init(void) { return 0; }
+#endif
+
+#endif /* _SUNXI_GPIO_H */
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus.h b/arch/arm/include/asm/arch-sunxi/gtbus.h
new file mode 100644
index 0000000..a89102e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * GTBUS initialisation
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ *                    Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+ */
+
+#ifndef _SUNXI_GTBUS_H
+#define _SUNXI_GTBUS_H
+
+#if defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/gtbus_sun9i.h>
+#endif
+
+#ifndef __ASSEMBLY__
+void gtbus_init(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
new file mode 100644
index 0000000..f962992
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * GTBUS initialisation for sun9i
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ *                    Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+ */
+
+#ifndef _SUNXI_GTBUS_SUN9I_H
+#define _SUNXI_GTBUS_SUN9I_H
+
+#include <linux/types.h>
+
+struct sunxi_gtbus_reg {
+	u32 mst_cfg[36];           /* 0x000 */
+	u8  reserved1[0x70];       /* 0x090 */
+	u32 bw_wdw_cfg;            /* 0x100 */
+	u32 mst_read_prio_cfg[2];  /* 0x104 */
+	u32 lvl2_mst_cfg;          /* 0x10c */
+	u32 sw_clk_on;             /* 0x110 */
+	u32 sw_clk_off;            /* 0x114 */
+	u32 pmu_mst_en;            /* 0x118 */
+	u32 pmu_cfg;               /* 0x11c */
+	u32 pmu_cnt[19];           /* 0x120 */
+	u32 reserved2[0x94];       /* 0x16c */
+	u32 cci400_config[3];      /* 0x200 */
+	u32 cci400_status[2];      /* 0x20c */
+};
+
+/* for register GT_MST_CFG_REG(n) */
+#define GT_ENABLE_REQ           (1<<31) /* clock on */
+#define GT_DISABLE_REQ          (1<<30) /* clock off */
+#define GT_QOS_SHIFT            28
+#define GT_THD1_SHIFT           16
+#define GT_REQN_MAX             0xf /* max no master requests in one cycle */
+#define GT_REQN_SHIFT           12
+#define GT_THD0_SHIFT           0
+
+#define GT_QOS_MAX              0x3
+#define GT_THD_MAX              0xfff
+#define GT_BW_WDW_MAX           0xffff
+
+/* mst_read_prio_cfg */
+#define GT_PRIO_LOW     0
+#define GT_PRIO_HIGH    1
+
+/* GTBUS port ids */
+#define GT_PORT_CPUM1   0
+#define GT_PORT_CPUM2   1
+#define GT_PORT_SATA    2
+#define	GT_PORT_USB3    3
+#define	GT_PORT_FE0     4
+#define	GT_PORT_BE1     5
+#define	GT_PORT_BE2     6
+#define	GT_PORT_IEP0    7
+#define	GT_PORT_FE1     8
+#define	GT_PORT_BE0     9
+#define	GT_PORT_FE2     10
+#define	GT_PORT_IEP1    11
+#define	GT_PORT_VED     12
+#define	GT_PORT_VEE     13
+#define	GT_PORT_FD      14
+#define	GT_PORT_CSI     15
+#define	GT_PORT_MP      16
+#define	GT_PORT_HSI     17
+#define	GT_PORT_SS      18
+#define	GT_PORT_TS      19
+#define	GT_PORT_DMA     20
+#define	GT_PORT_NDFC0   21
+#define	GT_PORT_NDFC1   22
+#define	GT_PORT_CPUS    23
+#define	GT_PORT_TH      24
+#define	GT_PORT_GMAC    25
+#define	GT_PORT_USB0    26
+#define	GT_PORT_MSTG0   27
+#define	GT_PORT_MSTG1   28
+#define	GT_PORT_MSTG2   29
+#define	GT_PORT_MSTG3   30
+#define	GT_PORT_USB1    31
+#define	GT_PORT_GPU0    32
+#define	GT_PORT_GPU1    33
+#define	GT_PORT_USB2    34
+#define	GT_PORT_CPUM0   35
+
+#define GP_MST_CFG_DEFAULT \
+	((GT_QOS_MAX << GT_QOS_SHIFT)   | \
+	 (GT_THD_MAX << GT_THD1_SHIFT)  | \
+	 (GT_REQN_MAX << GT_REQN_SHIFT) | \
+	 (GT_THD_MAX << GT_THD0_SHIFT))
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
new file mode 100644
index 0000000..1cb2ba6
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ */
+#ifndef _SUNXI_I2C_H_
+#define _SUNXI_I2C_H_
+
+#include <asm/arch/cpu.h>
+
+#ifdef CONFIG_I2C0_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE0	SUNXI_TWI0_BASE
+#endif
+#ifdef CONFIG_I2C1_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE1	SUNXI_TWI1_BASE
+#endif
+#ifdef CONFIG_I2C2_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE2	SUNXI_TWI2_BASE
+#endif
+#ifdef CONFIG_I2C3_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE3	SUNXI_TWI3_BASE
+#endif
+#ifdef CONFIG_I2C4_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE4	SUNXI_TWI4_BASE
+#endif
+#ifdef CONFIG_R_I2C_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE
+#endif
+
+/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
+#define CONFIG_SYS_TCLK		24000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/lcdc.h b/arch/arm/include/asm/arch-sunxi/lcdc.h
new file mode 100644
index 0000000..90216bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/lcdc.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sunxi platform timing controller register and constant defines
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ */
+
+#ifndef _LCDC_H
+#define _LCDC_H
+
+#include <fdtdec.h>
+
+struct sunxi_lcdc_reg {
+	u32 ctrl;			/* 0x00 */
+	u32 int0;			/* 0x04 */
+	u32 int1;			/* 0x08 */
+	u8 res0[0x04];			/* 0x0c */
+	u32 tcon0_frm_ctrl;		/* 0x10 */
+	u32 tcon0_frm_seed[6];		/* 0x14 */
+	u32 tcon0_frm_table[4];		/* 0x2c */
+	u8 res1[4];			/* 0x3c */
+	u32 tcon0_ctrl;			/* 0x40 */
+	u32 tcon0_dclk;			/* 0x44 */
+	u32 tcon0_timing_active;	/* 0x48 */
+	u32 tcon0_timing_h;		/* 0x4c */
+	u32 tcon0_timing_v;		/* 0x50 */
+	u32 tcon0_timing_sync;		/* 0x54 */
+	u32 tcon0_hv_intf;		/* 0x58 */
+	u8 res2[0x04];			/* 0x5c */
+	u32 tcon0_cpu_intf;		/* 0x60 */
+	u32 tcon0_cpu_wr_dat;		/* 0x64 */
+	u32 tcon0_cpu_rd_dat0;		/* 0x68 */
+	u32 tcon0_cpu_rd_dat1;		/* 0x6c */
+	u32 tcon0_ttl_timing0;		/* 0x70 */
+	u32 tcon0_ttl_timing1;		/* 0x74 */
+	u32 tcon0_ttl_timing2;		/* 0x78 */
+	u32 tcon0_ttl_timing3;		/* 0x7c */
+	u32 tcon0_ttl_timing4;		/* 0x80 */
+	u32 tcon0_lvds_intf;		/* 0x84 */
+	u32 tcon0_io_polarity;		/* 0x88 */
+	u32 tcon0_io_tristate;		/* 0x8c */
+	u32 tcon1_ctrl;			/* 0x90 */
+	u32 tcon1_timing_source;	/* 0x94 */
+	u32 tcon1_timing_scale;		/* 0x98 */
+	u32 tcon1_timing_out;		/* 0x9c */
+	u32 tcon1_timing_h;		/* 0xa0 */
+	u32 tcon1_timing_v;		/* 0xa4 */
+	u32 tcon1_timing_sync;		/* 0xa8 */
+	u8 res3[0x44];			/* 0xac */
+	u32 tcon1_io_polarity;		/* 0xf0 */
+	u32 tcon1_io_tristate;		/* 0xf4 */
+	u8 res4[0x108];			/* 0xf8 */
+	u32 mux_ctrl;			/* 0x200 */
+	u8 res5[0x1c];			/* 0x204 */
+	u32 lvds_ana0;			/* 0x220 */
+	u32 lvds_ana1;			/* 0x224 */
+};
+
+/*
+ * LCDC register constants.
+ */
+#define SUNXI_LCDC_X(x)				(((x) - 1) << 16)
+#define SUNXI_LCDC_Y(y)				(((y) - 1) << 0)
+#define SUNXI_LCDC_TCON_VSYNC_MASK		(1 << 24)
+#define SUNXI_LCDC_TCON_HSYNC_MASK		(1 << 25)
+#define SUNXI_LCDC_CTRL_IO_MAP_MASK		(1 << 0)
+#define SUNXI_LCDC_CTRL_IO_MAP_TCON0		(0 << 0)
+#define SUNXI_LCDC_CTRL_IO_MAP_TCON1		(1 << 0)
+#define SUNXI_LCDC_CTRL_TCON_ENABLE		(1 << 31)
+#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666	((1 << 31) | (0 << 4))
+#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565	((1 << 31) | (5 << 4))
+#define SUNXI_LCDC_TCON0_FRM_SEED		0x11111111
+#define SUNXI_LCDC_TCON0_FRM_TAB0		0x01010000
+#define SUNXI_LCDC_TCON0_FRM_TAB1		0x15151111
+#define SUNXI_LCDC_TCON0_FRM_TAB2		0x57575555
+#define SUNXI_LCDC_TCON0_FRM_TAB3		0x7f7f7777
+#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
+#define SUNXI_LCDC_TCON0_CTRL_ENABLE		(1 << 31)
+#define SUNXI_LCDC_TCON0_DCLK_DIV(n)		((n) << 0)
+#define SUNXI_LCDC_TCON0_DCLK_ENABLE		(0xf << 28)
+#define SUNXI_LCDC_TCON0_TIMING_H_BP(n)		(((n) - 1) << 0)
+#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
+#define SUNXI_LCDC_TCON0_TIMING_V_BP(n)		(((n) - 1) << 0)
+#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n)	(((n) * 2) << 16)
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	(1 << 20)
+#else
+#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	0 /* NA */
+#endif
+#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n)	((n) << 26)
+#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE	(1 << 31)
+#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x)	((x) << 28)
+#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
+#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE	(1 << 20)
+#define SUNXI_LCDC_TCON1_CTRL_ENABLE		(1 << 31)
+#define SUNXI_LCDC_TCON1_TIMING_H_BP(n)		(((n) - 1) << 0)
+#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
+#define SUNXI_LCDC_TCON1_TIMING_V_BP(n)		(((n) - 1) << 0)
+#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n)	((n) << 16)
+#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK		(0xf << 0)
+#define SUNXI_LCDC_MUX_CTRL_SRC0(x)		((x) << 0)
+#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK		(0xf << 4)
+#define SUNXI_LCDC_MUX_CTRL_SRC1(x)		((x) << 4)
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+#define SUNXI_LCDC_LVDS_ANA0			0x40040320
+#define SUNXI_LCDC_LVDS_ANA0_EN_MB		(1 << 31)
+#define SUNXI_LCDC_LVDS_ANA0_DRVC		(1 << 24)
+#define SUNXI_LCDC_LVDS_ANA0_DRVD(x)		((x) << 20)
+#else
+#define SUNXI_LCDC_LVDS_ANA0			0x3f310000
+#define SUNXI_LCDC_LVDS_ANA0_UPDATE		(1 << 22)
+#endif
+#define SUNXI_LCDC_LVDS_ANA1_INIT1		(0x1f << 26 | 0x1f << 10)
+#define SUNXI_LCDC_LVDS_ANA1_INIT2		(0x1f << 16 | 0x1f << 00)
+
+void lcdc_init(struct sunxi_lcdc_reg * const lcdc);
+void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth);
+void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
+			 const struct display_timing *mode,
+			 int clk_div, bool for_ext_vga_dac,
+			 int depth, int dclk_phase);
+void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
+			 const struct display_timing *mode,
+			 bool ext_hvsync, bool is_composite);
+void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon,
+		  int dotclock, int *clk_div, int *clk_double,
+		  bool is_composite);
+
+#endif /* _LCDC_H */
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
new file mode 100644
index 0000000..f2deafd
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Aaron <leafy.myeh@allwinnertech.com>
+ *
+ * MMC register definition for allwinner sunxi platform.
+ */
+
+#ifndef _SUNXI_MMC_H
+#define _SUNXI_MMC_H
+
+#include <linux/types.h>
+
+struct sunxi_mmc {
+	u32 gctrl;		/* 0x00 global control */
+	u32 clkcr;		/* 0x04 clock control */
+	u32 timeout;		/* 0x08 time out */
+	u32 width;		/* 0x0c bus width */
+	u32 blksz;		/* 0x10 block size */
+	u32 bytecnt;		/* 0x14 byte count */
+	u32 cmd;		/* 0x18 command */
+	u32 arg;		/* 0x1c argument */
+	u32 resp0;		/* 0x20 response 0 */
+	u32 resp1;		/* 0x24 response 1 */
+	u32 resp2;		/* 0x28 response 2 */
+	u32 resp3;		/* 0x2c response 3 */
+	u32 imask;		/* 0x30 interrupt mask */
+	u32 mint;		/* 0x34 masked interrupt status */
+	u32 rint;		/* 0x38 raw interrupt status */
+	u32 status;		/* 0x3c status */
+	u32 ftrglevel;		/* 0x40 FIFO threshold watermark*/
+	u32 funcsel;		/* 0x44 function select */
+	u32 cbcr;		/* 0x48 CIU byte count */
+	u32 bbcr;		/* 0x4c BIU byte count */
+	u32 dbgc;		/* 0x50 debug enable */
+	u32 res0;		/* 0x54 reserved */
+	u32 a12a;		/* 0x58 Auto command 12 argument */
+	u32 ntsr;		/* 0x5c	New timing set register */
+	u32 res1[8];
+	u32 dmac;		/* 0x80 internal DMA control */
+	u32 dlba;		/* 0x84 internal DMA descr list base address */
+	u32 idst;		/* 0x88 internal DMA status */
+	u32 idie;		/* 0x8c internal DMA interrupt enable */
+	u32 chda;		/* 0x90 */
+	u32 cbda;		/* 0x94 */
+	u32 res2[26];
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
+	u32 res3[17];
+	u32 samp_dl;
+	u32 res4[46];
+#endif
+	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
+};
+
+#define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
+#define SUNXI_MMC_CLK_ENABLE		(0x1 << 16)
+#define SUNXI_MMC_CLK_DIVIDER_MASK	(0xff)
+
+#define SUNXI_MMC_GCTRL_SOFT_RESET	(0x1 << 0)
+#define SUNXI_MMC_GCTRL_FIFO_RESET	(0x1 << 1)
+#define SUNXI_MMC_GCTRL_DMA_RESET	(0x1 << 2)
+#define SUNXI_MMC_GCTRL_RESET		(SUNXI_MMC_GCTRL_SOFT_RESET|\
+					 SUNXI_MMC_GCTRL_FIFO_RESET|\
+					 SUNXI_MMC_GCTRL_DMA_RESET)
+#define SUNXI_MMC_GCTRL_DMA_ENABLE	(0x1 << 5)
+#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB   (0x1 << 31)
+
+#define SUNXI_MMC_CMD_RESP_EXPIRE	(0x1 << 6)
+#define SUNXI_MMC_CMD_LONG_RESPONSE	(0x1 << 7)
+#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC	(0x1 << 8)
+#define SUNXI_MMC_CMD_DATA_EXPIRE	(0x1 << 9)
+#define SUNXI_MMC_CMD_WRITE		(0x1 << 10)
+#define SUNXI_MMC_CMD_AUTO_STOP		(0x1 << 12)
+#define SUNXI_MMC_CMD_WAIT_PRE_OVER	(0x1 << 13)
+#define SUNXI_MMC_CMD_SEND_INIT_SEQ	(0x1 << 15)
+#define SUNXI_MMC_CMD_UPCLK_ONLY	(0x1 << 21)
+#define SUNXI_MMC_CMD_START		(0x1 << 31)
+
+#define SUNXI_MMC_RINT_RESP_ERROR		(0x1 << 1)
+#define SUNXI_MMC_RINT_COMMAND_DONE		(0x1 << 2)
+#define SUNXI_MMC_RINT_DATA_OVER		(0x1 << 3)
+#define SUNXI_MMC_RINT_TX_DATA_REQUEST		(0x1 << 4)
+#define SUNXI_MMC_RINT_RX_DATA_REQUEST		(0x1 << 5)
+#define SUNXI_MMC_RINT_RESP_CRC_ERROR		(0x1 << 6)
+#define SUNXI_MMC_RINT_DATA_CRC_ERROR		(0x1 << 7)
+#define SUNXI_MMC_RINT_RESP_TIMEOUT		(0x1 << 8)
+#define SUNXI_MMC_RINT_DATA_TIMEOUT		(0x1 << 9)
+#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE	(0x1 << 10)
+#define SUNXI_MMC_RINT_FIFO_RUN_ERROR		(0x1 << 11)
+#define SUNXI_MMC_RINT_HARD_WARE_LOCKED		(0x1 << 12)
+#define SUNXI_MMC_RINT_START_BIT_ERROR		(0x1 << 13)
+#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE	(0x1 << 14)
+#define SUNXI_MMC_RINT_END_BIT_ERROR		(0x1 << 15)
+#define SUNXI_MMC_RINT_SDIO_INTERRUPT		(0x1 << 16)
+#define SUNXI_MMC_RINT_CARD_INSERT		(0x1 << 30)
+#define SUNXI_MMC_RINT_CARD_REMOVE		(0x1 << 31)
+#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT      \
+	(SUNXI_MMC_RINT_RESP_ERROR |		\
+	 SUNXI_MMC_RINT_RESP_CRC_ERROR |	\
+	 SUNXI_MMC_RINT_DATA_CRC_ERROR |	\
+	 SUNXI_MMC_RINT_RESP_TIMEOUT |		\
+	 SUNXI_MMC_RINT_DATA_TIMEOUT |		\
+	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE |	\
+	 SUNXI_MMC_RINT_FIFO_RUN_ERROR |	\
+	 SUNXI_MMC_RINT_HARD_WARE_LOCKED |	\
+	 SUNXI_MMC_RINT_START_BIT_ERROR |	\
+	 SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
+#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT	\
+	(SUNXI_MMC_RINT_AUTO_COMMAND_DONE |	\
+	 SUNXI_MMC_RINT_DATA_OVER |		\
+	 SUNXI_MMC_RINT_COMMAND_DONE |		\
+	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
+
+#define SUNXI_MMC_STATUS_RXWL_FLAG		(0x1 << 0)
+#define SUNXI_MMC_STATUS_TXWL_FLAG		(0x1 << 1)
+#define SUNXI_MMC_STATUS_FIFO_EMPTY		(0x1 << 2)
+#define SUNXI_MMC_STATUS_FIFO_FULL		(0x1 << 3)
+#define SUNXI_MMC_STATUS_CARD_PRESENT		(0x1 << 8)
+#define SUNXI_MMC_STATUS_CARD_DATA_BUSY		(0x1 << 9)
+#define SUNXI_MMC_STATUS_DATA_FSM_BUSY		(0x1 << 10)
+
+#define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
+
+#define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
+#define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
+#define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
+
+#define SUNXI_MMC_IDIE_TXIRQ		(0x1 << 0)
+#define SUNXI_MMC_IDIE_RXIRQ		(0x1 << 1)
+
+#define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
+#define SUNXI_MMC_COMMON_RESET			(1 << 18)
+
+#define SUNXI_MMC_CAL_DL_SW_EN		(0x1 << 7)
+
+struct mmc *sunxi_mmc_init(int sdc_no);
+#endif /* _SUNXI_MMC_H */
diff --git a/arch/arm/include/asm/arch-sunxi/p2wi.h b/arch/arm/include/asm/arch-sunxi/p2wi.h
new file mode 100644
index 0000000..5f2a898
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/p2wi.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sunxi platform Push-Push i2c register definition.
+ *
+ * (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * (c)Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#ifndef _SUNXI_P2WI_H
+#define _SUNXI_P2WI_H
+
+#include <linux/types.h>
+
+#define P2WI_CTRL_RESET (0x1 << 0)
+#define P2WI_CTRL_IRQ_EN (0x1 << 1)
+#define P2WI_CTRL_TRANS_ABORT (0x1 << 6)
+#define P2WI_CTRL_TRANS_START (0x1 << 7)
+
+#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0)
+#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff)
+#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1)
+#define P2WI_CC_CLK_DIV(n) \
+	__P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n))
+#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8)
+#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7)
+
+#define P2WI_IRQ_TRANS_DONE (0x1 << 0)
+#define P2WI_IRQ_TRANS_ERR (0x1 << 1)
+#define P2WI_IRQ_LOAD_BUSY (0x1 << 2)
+
+#define P2WI_STAT_TRANS_DONE (0x1 << 0)
+#define P2WI_STAT_TRANS_ERR (0x1 << 1)
+#define P2WI_STAT_LOAD_BUSY (0x1 << 2)
+#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8)
+#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff)
+#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01
+#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02
+#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04
+#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08
+#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10
+#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20
+#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40
+#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80
+#define P2WI_STAT_TRANS_ERR_BYTE_1 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1)
+#define P2WI_STAT_TRANS_ERR_BYTE_2 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2)
+#define P2WI_STAT_TRANS_ERR_BYTE_3 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3)
+#define P2WI_STAT_TRANS_ERR_BYTE_4 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4)
+#define P2WI_STAT_TRANS_ERR_BYTE_5 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5)
+#define P2WI_STAT_TRANS_ERR_BYTE_6 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6)
+#define P2WI_STAT_TRANS_ERR_BYTE_7 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7)
+#define P2WI_STAT_TRANS_ERR_BYTE_8 \
+	__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8)
+
+#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0)
+#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff)
+#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8)
+#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff)
+#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16)
+#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff)
+#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24)
+#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff)
+#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0)
+#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff)
+#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8)
+#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff)
+#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16)
+#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff)
+#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24)
+#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff)
+
+#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0)
+#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7)
+#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1)
+#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4)
+
+#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0)
+#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff)
+#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8)
+#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff)
+#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16)
+#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff)
+#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24)
+#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff)
+#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0)
+#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff)
+#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8)
+#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff)
+#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16)
+#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff)
+#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24)
+#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff)
+
+#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0)
+#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1)
+#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2)
+#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3)
+#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4)
+#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5)
+
+#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0)
+#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff)
+#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8)
+#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff)
+#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16)
+#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff)
+#define P2WI_PM_INIT_SEND (0x1 << 31)
+
+struct sunxi_p2wi_reg {
+	u32 ctrl;	/* 0x00 control */
+	u32 cc;		/* 0x04 clock control */
+	u32 irq;	/* 0x08 interrupt */
+	u32 status;	/* 0x0c status */
+	u32 dataddr0;	/* 0x10 data address 0 */
+	u32 dataddr1;	/* 0x14 data address 1 */
+	u32 numbytes;	/* 0x18 num bytes */
+	u32 data0;	/* 0x1c data buffer 0 */
+	u32 data1;	/* 0x20 data buffer 1 */
+	u32 linectrl;	/* 0x24 line control */
+	u32 pm;		/* 0x28 power management */
+};
+
+void p2wi_init(void);
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data);
+int p2wi_read(const u8 addr, u8 *data);
+int p2wi_write(const u8 addr, u8 data);
+
+#endif /* _SUNXI_P2WI_H */
diff --git a/arch/arm/include/asm/arch-sunxi/pmic_bus.h b/arch/arm/include/asm/arch-sunxi/pmic_bus.h
new file mode 100644
index 0000000..3ccfe13
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/pmic_bus.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Sunxi PMIC bus access helpers header
+ */
+
+#ifndef _SUNXI_PMIC_BUS_H
+#define _SUNXI_PMIS_BUS_H
+
+int pmic_bus_init(void);
+int pmic_bus_read(u8 reg, u8 *data);
+int pmic_bus_write(u8 reg, u8 data);
+int pmic_bus_setbits(u8 reg, u8 bits);
+int pmic_bus_clrbits(u8 reg, u8 bits);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
new file mode 100644
index 0000000..58a3689
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sunxi A31 Power Management Unit register definition.
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#ifndef _SUNXI_PRCM_H
+#define _SUNXI_PRCM_H
+
+#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)
+#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
+#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)
+#define PRCM_CPUS_CFG_PRE_DIV(n) \
+	__PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
+#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)
+#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
+#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
+#define PRCM_CPUS_CFG_POST_DIV(n) \
+	__PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
+#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)
+#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
+#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
+#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
+#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
+#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
+#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
+#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
+#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
+	__PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
+
+#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0)
+#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
+#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)
+#define PRCM_APB0_RATIO_DIV(n) \
+	__PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
+
+#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)
+#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)
+
+#define PRCM_APB0_GATE_PIO (0x1 << 0)
+#define PRCM_APB0_GATE_IR (0x1 << 1)
+#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
+#define PRCM_APB0_GATE_P2WI (0x1 << 3)		/* sun6i */
+#define PRCM_APB0_GATE_RSB (0x1 << 3)		/* sun8i */
+#define PRCM_APB0_GATE_UART (0x1 << 4)
+#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
+#define PRCM_APB0_GATE_I2C (0x1 << 6)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)
+#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)
+#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)
+#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(0x3)
+#define __PRCM_PLL_CTRL_USB_CLK_0 0x0
+#define __PRCM_PLL_CTRL_USB_CLK_1 0x1
+#define __PRCM_PLL_CTRL_USB_CLK_2 0x2
+#define __PRCM_PLL_CTRL_USB_CLK_3 0x3
+#define PRCM_PLL_CTRL_USB_CLK_0 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)
+#define PRCM_PLL_CTRL_USB_CLK_1 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)
+#define PRCM_PLL_CTRL_USB_CLK_2 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)
+#define PRCM_PLL_CTRL_USB_CLK_3 \
+	__PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3)
+#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \
+	__PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3)
+#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \
+	__PRCM_PLL_CTRL_INT_PLL_IN_SEL(n)
+#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20)
+#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3)
+#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0
+#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1
+#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2
+#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3
+#define PRCM_PLL_CTRL_HOSC_CLK_0 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0)
+#define PRCM_PLL_CTRL_HOSC_CLK_1 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1)
+#define PRCM_PLL_CTRL_HOSC_CLK_2 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2)
+#define PRCM_PLL_CTRL_HOSC_CLK_3 \
+	__PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3)
+#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24)
+#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0)
+#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1)
+#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2)
+#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3)
+#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */
+#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16)
+#define PRCM_PLL_CTRL_LDO_OUT_MASK \
+	__PRCM_PLL_CTRL_LDO_OUT(0x7)
+/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
+#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
+	__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
+#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
+#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)
+
+#define PRCM_CLK_1WIRE_GATE (0x1 << 31)
+
+#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0)
+#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf)
+#define __PRCM_CLK_MOD0_M_X(n) (n - 1)
+#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n))
+#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7)
+#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16)
+#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3)
+#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n))
+#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7)
+#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24)
+#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7)
+#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31)
+
+#define PRCM_APB0_RESET_PIO (0x1 << 0)
+#define PRCM_APB0_RESET_IR (0x1 << 1)
+#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
+#define PRCM_APB0_RESET_P2WI (0x1 << 3)
+#define PRCM_APB0_RESET_UART (0x1 << 4)
+#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
+#define PRCM_APB0_RESET_I2C (0x1 << 6)
+
+#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8)
+#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7)
+#define __PRCM_CLK_OUTD_M_X() ((n) - 1)
+#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n))
+#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20)
+#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7)
+#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1)
+#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n)
+#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24)
+#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3)
+#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0
+#define __PRCM_CLK_OUTD_SRC_LOSC 0x1
+#define __PRCM_CLK_OUTD_SRC_HOSC 0x2
+#define __PRCM_CLK_OUTD_SRC_ERR 0x3
+#define PRCM_CLK_OUTD_SRC_LOSC2 \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2)
+#define PRCM_CLK_OUTD_SRC_LOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC)
+#define PRCM_CLK_OUTD_SRC_HOSC \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC)
+#define PRCM_CLK_OUTD_SRC_ERR \
+#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR)
+#define PRCM_CLK_OUTD_EN (0x1 << 31)
+
+#define PRCM_CPU0_PWROFF (0x1 << 0)
+#define PRCM_CPU1_PWROFF (0x1 << 1)
+#define PRCM_CPU2_PWROFF (0x1 << 2)
+#define PRCM_CPU3_PWROFF (0x1 << 3)
+#define PRCM_CPU_ALL_PWROFF (0xf << 0)
+
+#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0)
+#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1)
+#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2)
+#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3)
+
+#define PRCM_VDD_GPU_PWROFF (0x1 << 0)
+
+#define PRCM_VDD_SYS_RESET (0x1 << 0)
+
+#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff)
+
+#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff)
+
+#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
+#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
+
+#define PRCM_SEC_SWITCH_APB0_CLK_NONSEC (0x1 << 0)
+#define PRCM_SEC_SWITCH_PLL_CFG_NONSEC (0x1 << 1)
+#define PRCM_SEC_SWITCH_PWR_GATE_NONSEC (0x1 << 2)
+
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+
+struct __packed sunxi_prcm_reg {
+	u32 cpus_cfg;		/* 0x000 */
+	u8 res0[0x8];		/* 0x004 */
+	u32 apb0_ratio;		/* 0x00c */
+	u32 cpu0_cfg;		/* 0x010 */
+	u32 cpu1_cfg;		/* 0x014 */
+	u32 cpu2_cfg;		/* 0x018 */
+	u32 cpu3_cfg;		/* 0x01c */
+	u8 res1[0x8];		/* 0x020 */
+	u32 apb0_gate;		/* 0x028 */
+	u8 res2[0x14];		/* 0x02c */
+	u32 pll_ctrl0;		/* 0x040 */
+	u32 pll_ctrl1;		/* 0x044 */
+	u8 res3[0x8];		/* 0x048 */
+	u32 clk_1wire;		/* 0x050 */
+	u32 clk_ir;		/* 0x054 */
+	u8 res4[0x58];		/* 0x058 */
+	u32 apb0_reset;		/* 0x0b0 */
+	u8 res5[0x3c];		/* 0x0b4 */
+	u32 clk_outd;		/* 0x0f0 */
+	u8 res6[0xc];		/* 0x0f4 */
+	u32 cpu_pwroff;		/* 0x100 */
+	u8 res7[0xc];		/* 0x104 */
+	u32 vdd_sys_pwroff;	/* 0x110 */
+	u8 res8[0x4];		/* 0x114 */
+	u32 gpu_pwroff;		/* 0x118 */
+	u8 res9[0x4];		/* 0x11c */
+	u32 vdd_pwr_reset;	/* 0x120 */
+	u8 res10[0x1c];		/* 0x124 */
+	u32 cpu_pwr_clamp[4];	/* 0x140 but first one is actually unused */
+	u8 res11[0x30];		/* 0x150 */
+	u32 dram_pwr;		/* 0x180 */
+	u8 res12[0xc];		/* 0x184 */
+	u32 dram_tst;		/* 0x190 */
+	u8 res13[0x3c];		/* 0x194 */
+	u32 prcm_sec_switch;	/* 0x1d0 */
+};
+
+void prcm_apb0_enable(u32 flags);
+void prcm_apb0_disable(u32 flags);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _PRCM_H */
diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h
new file mode 100644
index 0000000..dca283c
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/pwm.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ */
+
+#ifndef _SUNXI_PWM_H
+#define _SUNXI_PWM_H
+
+#define SUNXI_PWM_CTRL_REG		(SUNXI_PWM_BASE + 0)
+#define SUNXI_PWM_CH0_PERIOD		(SUNXI_PWM_BASE + 4)
+
+#define SUNXI_PWM_CTRL_PRESCALE0(x)	((x) & 0xf)
+#define SUNXI_PWM_CTRL_PRESCALE0_MASK	0xf
+#define SUNXI_PWM_CTRL_ENABLE0		(0x5 << 4)
+#define SUNXI_PWM_CTRL_POLARITY0(x)	((x) << 5)
+#define SUNXI_PWM_CTRL_CH0_ACT_STA	BIT(5)
+#define SUNXI_PWM_CTRL_CLK_GATE		BIT(6)
+
+#define SUNXI_PWM_CH0_PERIOD_MAX	(0xffff)
+#define SUNXI_PWM_CH0_PERIOD_PRD(x)	((x & 0xffff) << 16)
+#define SUNXI_PWM_CH0_PERIOD_DUTY(x)	((x) & 0xffff)
+
+#define SUNXI_PWM_PERIOD_80PCT		0x04af03c0
+
+#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN5I
+#define SUNXI_PWM_PIN0			SUNXI_GPB(2)
+#define SUNXI_PWM_MUX			SUN4I_GPB_PWM
+#endif
+
+#if defined CONFIG_MACH_SUN6I
+#define SUNXI_PWM_PIN0			SUNXI_GPH(13)
+#define SUNXI_PWM_MUX			SUN6I_GPH_PWM
+#endif
+
+#if defined CONFIG_MACH_SUN8I_A23 || defined CONFIG_MACH_SUN8I_A33
+#define SUNXI_PWM_PIN0			SUNXI_GPH(0)
+#define SUNXI_PWM_MUX			SUN8I_GPH_PWM
+#endif
+
+struct sunxi_pwm {
+	u32 ctrl;
+	u32 ch0_period;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h b/arch/arm/include/asm/arch-sunxi/rsb.h
new file mode 100644
index 0000000..616b6e2
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/rsb.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Based on allwinner u-boot sources rsb code which is:
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * lixiang <lixiang@allwinnertech.com>
+ */
+
+#ifndef __SUNXI_RSB_H
+#define __SUNXI_RSB_H
+
+#include <common.h>
+#include <asm/io.h>
+
+struct sunxi_rsb_reg {
+	u32 ctrl;	/* 0x00 */
+	u32 ccr;	/* 0x04 */
+	u32 inte;	/* 0x08 */
+	u32 stat;	/* 0x0c */
+	u32 addr;	/* 0x10 */
+	u8 res0[8];	/* 0x14 */
+	u32 data;	/* 0x1c */
+	u8 res1[4];	/* 0x20 */
+	u32 lcr;	/* 0x24 */
+	u32 dmcr;	/* 0x28 */
+	u32 cmd;	/* 0x2c */
+	u32 devaddr;	/* 0x30 */
+};
+
+#define RSB_CTRL_SOFT_RST		(1 << 0)
+#define RSB_CTRL_START_TRANS		(1 << 7)
+
+#define RSB_STAT_TOVER_INT		(1 << 0)
+#define RSB_STAT_TERR_INT		(1 << 1)
+#define RSB_STAT_LBSY_INT		(1 << 2)
+
+#define RSB_DMCR_DEVICE_MODE_DATA	0x7c3e00
+#define RSB_DMCR_DEVICE_MODE_START	(1 << 31)
+
+#define RSB_CMD_BYTE_WRITE		0x4e
+#define RSB_CMD_BYTE_READ		0x8b
+#define RSB_CMD_SET_RTSADDR		0xe8
+
+#define RSB_DEVADDR_RUNTIME_ADDR(x)	((x) << 16)
+#define RSB_DEVADDR_DEVICE_ADDR(x)	((x) << 0)
+
+int rsb_init(void);
+int rsb_set_device_address(u16 device_addr, u16 runtime_addr);
+int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data);
+int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
new file mode 100644
index 0000000..8c916e8
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT0_MAGIC		"eGON.BT0"
+#define SPL_SIGNATURE		"SPL" /* marks "sunxi" SPL header */
+#define SPL_MAJOR_BITS		3
+#define SPL_MINOR_BITS		5
+#define SPL_VERSION(maj, min)						\
+	((((maj) & ((1U << SPL_MAJOR_BITS) - 1)) << SPL_MINOR_BITS) | \
+	((min) & ((1U << SPL_MINOR_BITS) - 1)))
+
+#define SPL_HEADER_VERSION	SPL_VERSION(0, 2)
+
+#define SPL_ENV_HEADER_VERSION	SPL_VERSION(0, 1)
+#define SPL_DT_HEADER_VERSION	SPL_VERSION(0, 2)
+#define SPL_DRAM_HEADER_VERSION	SPL_VERSION(0, 3)
+
+#define SPL_ADDR		CONFIG_SUNXI_SRAM_ADDRESS
+
+/* The low 8-bits of the 'boot_media' field in the SPL header */
+#define SUNXI_BOOTED_FROM_MMC0	0
+#define SUNXI_BOOTED_FROM_NAND	1
+#define SUNXI_BOOTED_FROM_MMC2	2
+#define SUNXI_BOOTED_FROM_SPI	3
+#define SUNXI_BOOTED_FROM_MMC0_HIGH	0x10
+#define SUNXI_BOOTED_FROM_MMC2_HIGH	0x12
+
+/* boot head definition from sun4i boot code */
+struct boot_file_head {
+	uint32_t b_instruction;	/* one intruction jumping to real code */
+	uint8_t magic[8];	/* ="eGON.BT0" or "eGON.BT1", not C-style str */
+	uint32_t check_sum;	/* generated by PC */
+	uint32_t length;	/* generated by PC */
+	/*
+	 * We use a simplified header, only filling in what is needed
+	 * by the boot ROM. To be compatible with Allwinner tools we
+	 * would need to implement the proper fields here instead of
+	 * padding.
+	 *
+	 * Actually we want the ability to recognize our "sunxi" variant
+	 * of the SPL. To do so, let's place a special signature into the
+	 * "pub_head_size" field. We can reasonably expect Allwinner's
+	 * boot0 to always have the upper 16 bits of this set to 0 (after
+	 * all the value shouldn't be larger than the limit imposed by
+	 * SRAM size).
+	 * If the signature is present (at 0x14), then we know it's safe
+	 * to use the remaining 8 bytes (at 0x18) for our own purposes.
+	 * (E.g. sunxi-tools "fel" utility can pass information there.)
+	 */
+	union {
+		uint32_t pub_head_size;
+		uint8_t spl_signature[4];
+	};
+	uint32_t fel_script_address;	/* since v0.1, set by sunxi-fel */
+	/*
+	 * If the fel_uEnv_length member below is set to a non-zero value,
+	 * it specifies the size (byte count) of data at fel_script_address.
+	 * At the same time this indicates that the data is in uEnv.txt
+	 * compatible format, ready to be imported via "env import -t".
+	 */
+	uint32_t fel_uEnv_length;	/* since v0.1, set by sunxi-fel */
+	/*
+	 * Offset of an ASCIIZ string (relative to the SPL header), which
+	 * contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE).
+	 * This is optional and may be set to NULL. Is intended to be used
+	 * by flash programming tools for providing nice informative messages
+	 * to the users.
+	 */
+	uint32_t dt_name_offset;	/* since v0.2, set by mksunxiboot */
+	uint32_t dram_size;		/* in MiB, since v0.3, set by SPL */
+	uint32_t boot_media;		/* written here by the boot ROM */
+	/* A padding area (may be used for storing text strings) */
+	uint32_t string_pool[13];	/* since v0.2, filled by mksunxiboot */
+	/* The header must be a multiple of 32 bytes (for VBAR alignment) */
+};
+
+/* Compile time check to assure proper alignment of structure */
+typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)];
+
+#define is_boot0_magic(addr)	(memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
+
+uint32_t sunxi_get_boot_device(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h
new file mode 100644
index 0000000..0646022
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <linux/types.h>
+
+void sdelay(unsigned long);
+
+/* return_to_fel() - Return to BROM from SPL
+ *
+ * This returns back into the BROM after U-Boot SPL has performed its initial
+ * init. It uses the provided lr and sp to do so.
+ *
+ * @lr:		BROM link register value (return address)
+ * @sp:		BROM stack pointer
+ */
+void return_to_fel(uint32_t lr, uint32_t sp);
+
+/* Board / SoC level designware gmac init */
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC
+void eth_init_board(void);
+#else
+static inline void eth_init_board(void) {}
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h
new file mode 100644
index 0000000..6f138d0
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Configuration settings for the Allwinner A10-evb board.
+ */
+
+#ifndef _SUNXI_TIMER_H_
+#define _SUNXI_TIMER_H_
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <asm/arch/watchdog.h>
+
+/* General purpose timer */
+struct sunxi_timer {
+	u32 ctl;
+	u32 inter;
+	u32 val;
+	u8 res[4];
+};
+
+/* Audio video sync*/
+struct sunxi_avs {
+	u32 ctl;		/* 0x80 */
+	u32 cnt0;		/* 0x84 */
+	u32 cnt1;		/* 0x88 */
+	u32 div;		/* 0x8c */
+};
+
+/* 64 bit counter */
+struct sunxi_64cnt {
+	u32 ctl;		/* 0xa0 */
+	u32 lo;			/* 0xa4 */
+	u32 hi;			/* 0xa8 */
+};
+
+/* Rtc */
+struct sunxi_rtc {
+	u32 ctl;		/* 0x100 */
+	u32 yymmdd;		/* 0x104 */
+	u32 hhmmss;		/* 0x108 */
+};
+
+/* Alarm */
+struct sunxi_alarm {
+	u32 ddhhmmss;		/* 0x10c */
+	u32 hhmmss;		/* 0x110 */
+	u32 en;			/* 0x114 */
+	u32 irqen;		/* 0x118 */
+	u32 irqsta;		/* 0x11c */
+};
+
+/* Timer general purpose register */
+struct sunxi_tgp {
+	u32 tgpd;
+};
+
+struct sunxi_timer_reg {
+	u32 tirqen;		/* 0x00 */
+	u32 tirqsta;		/* 0x04 */
+	u8 res1[8];
+	struct sunxi_timer timer[6];	/* We have 6 timers */
+	u8 res2[16];
+	struct sunxi_avs avs;
+#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
+	struct sunxi_wdog wdog;	/* 0x90 */
+	/* XXX the following is not accurate for sun5i/sun7i */
+	struct sunxi_64cnt cnt64;	/* 0xa0 */
+	u8 res4[0x58];
+	struct sunxi_rtc rtc;
+	struct sunxi_alarm alarm;
+	struct sunxi_tgp tgp[4];
+	u8 res5[8];
+	u32 cpu_cfg;
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
+	u8 res3[16];
+	struct sunxi_wdog wdog[5];	/* We have 5 watchdogs */
+#endif
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/tve.h b/arch/arm/include/asm/arch-sunxi/tve.h
new file mode 100644
index 0000000..46cd87e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/tve.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sunxi TV encoder register and constant defines
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ */
+
+#ifndef _TVE_H
+#define _TVE_H
+
+enum tve_mode {
+	tve_mode_vga,
+	tve_mode_composite_pal,
+	tve_mode_composite_ntsc,
+	tve_mode_composite_pal_m,
+	tve_mode_composite_pal_nc,
+};
+
+/*
+ * This is based on the A10s User Manual, and the A10s only supports
+ * composite video and not vga like the A10 / A20 does, still other
+ * than the removed vga out capability the tvencoder seems to be the same.
+ * "unknown#" registers are registers which are used in the A10 kernel code,
+ * but not documented in the A10s User Manual.
+ */
+struct sunxi_tve_reg {
+	u32 gctrl;			/* 0x000 */
+	u32 cfg0;			/* 0x004 */
+	u32 dac_cfg0;			/* 0x008 */
+	u32 filter;			/* 0x00c */
+	u32 chroma_freq;		/* 0x010 */
+	u32 porch_num;			/* 0x014 */
+	u32 unknown0;			/* 0x018 */
+	u32 line_num;			/* 0x01c */
+	u32 blank_black_level;		/* 0x020 */
+	u32 unknown1;			/* 0x024, seems to be 1 byte per dac */
+	u8 res0[0x08];			/* 0x028 */
+	u32 auto_detect_en;		/* 0x030 */
+	u32 auto_detect_int_status;	/* 0x034 */
+	u32 auto_detect_status;		/* 0x038 */
+	u32 auto_detect_debounce;	/* 0x03c */
+	u32 csc_reg0;			/* 0x040 */
+	u32 csc_reg1;			/* 0x044 */
+	u32 csc_reg2;			/* 0x048 */
+	u32 csc_reg3;			/* 0x04c */
+	u8 res1[0xb0];			/* 0x050 */
+	u32 color_burst;		/* 0x100 */
+	u32 vsync_num;			/* 0x104 */
+	u32 notch_freq;			/* 0x108 */
+	u32 cbr_level;			/* 0x10c */
+	u32 burst_phase;		/* 0x110 */
+	u32 burst_width;		/* 0x114 */
+	u32 unknown2;			/* 0x118 */
+	u32 sync_vbi_level;		/* 0x11c */
+	u32 white_level;		/* 0x120 */
+	u32 active_num;			/* 0x124 */
+	u32 chroma_bw_gain;		/* 0x128 */
+	u32 notch_width;		/* 0x12c */
+	u32 resync_num;			/* 0x130 */
+	u32 slave_para;			/* 0x134 */
+	u32 cfg1;			/* 0x138 */
+	u32 cfg2;			/* 0x13c */
+};
+
+/*
+ * TVE register constants.
+ */
+#define SUNXI_TVE_GCTRL_ENABLE			(1 << 0)
+/*
+ * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed
+ * dac from tve1. When using tve1 the mux value must be written to both tve0's
+ * and tve1's gctrl reg.
+ */
+#define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac)	(0xf << (((dac) + 1) * 4))
+#define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel)	((sel) << (((dac) + 1) * 4))
+#define SUNXI_TVE_CFG0_VGA			0x20000000
+#define SUNXI_TVE_CFG0_PAL			0x07030001
+#define SUNXI_TVE_CFG0_NTSC			0x07030000
+#define SUNXI_TVE_DAC_CFG0_VGA			0x403e1ac7
+#ifdef CONFIG_MACH_SUN5I
+#define SUNXI_TVE_DAC_CFG0_COMPOSITE		0x433f0009
+#else
+#define SUNXI_TVE_DAC_CFG0_COMPOSITE		0x403f0008
+#endif
+#define SUNXI_TVE_FILTER_COMPOSITE		0x00000120
+#define SUNXI_TVE_CHROMA_FREQ_PAL_M		0x21e6efe3
+#define SUNXI_TVE_CHROMA_FREQ_PAL_NC		0x21f69446
+#define SUNXI_TVE_PORCH_NUM_PAL			0x008a0018
+#define SUNXI_TVE_PORCH_NUM_NTSC		0x00760020
+#define SUNXI_TVE_LINE_NUM_PAL			0x00160271
+#define SUNXI_TVE_LINE_NUM_NTSC			0x0016020d
+#define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL		0x00fc00fc
+#define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC	0x00f0011a
+#define SUNXI_TVE_UNKNOWN1_VGA			0x00000000
+#define SUNXI_TVE_UNKNOWN1_COMPOSITE		0x18181818
+#define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac)	(1 << ((dac) + 0))
+#define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac)	(1 << ((dac) + 16))
+#define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac)	(1 << ((dac) + 0))
+#define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac)	((dac) * 8)
+#define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac)	(3 << ((dac) * 8))
+#define SUNXI_TVE_AUTO_DETECT_STATUS_NONE	0
+#define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED	1
+#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND	3
+#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d)	((d) * 8)
+#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d)	(0xf << ((d) * 8))
+#define SUNXI_TVE_CSC_REG0_ENABLE		(1 << 31)
+#define SUNXI_TVE_CSC_REG0			0x08440832
+#define SUNXI_TVE_CSC_REG1			0x3b6dace1
+#define SUNXI_TVE_CSC_REG2			0x0e1d13dc
+#define SUNXI_TVE_CSC_REG3			0x00108080
+#define SUNXI_TVE_COLOR_BURST_PAL_M		0x00000000
+#define SUNXI_TVE_CBR_LEVEL_PAL			0x00002828
+#define SUNXI_TVE_CBR_LEVEL_NTSC		0x0000004f
+#define SUNXI_TVE_BURST_PHASE_NTSC		0x00000000
+#define SUNXI_TVE_BURST_WIDTH_COMPOSITE		0x0016447e
+#define SUNXI_TVE_UNKNOWN2_PAL			0x0000e0e0
+#define SUNXI_TVE_UNKNOWN2_NTSC			0x0000a0a0
+#define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC		0x001000f0
+#define SUNXI_TVE_ACTIVE_NUM_COMPOSITE		0x000005a0
+#define SUNXI_TVE_CHROMA_BW_GAIN_COMP		0x00000002
+#define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE		0x00000101
+#define SUNXI_TVE_RESYNC_NUM_PAL		0x800d000c
+#define SUNXI_TVE_RESYNC_NUM_NTSC		0x000e000c
+#define SUNXI_TVE_SLAVE_PARA_COMPOSITE		0x00000000
+
+void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode);
+void tvencoder_enable(struct sunxi_tve_reg * const tve);
+
+#endif /* _TVE_H */
diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h
new file mode 100644
index 0000000..7a6fcae
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/tzpc.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Chen-Yu Tsai <wens@csie.org>
+ */
+
+#ifndef _SUNXI_TZPC_H
+#define _SUNXI_TZPC_H
+
+#ifndef __ASSEMBLY__
+struct sunxi_tzpc {
+	u32 r0size;		/* 0x00 Size of secure RAM region */
+	u32 decport0_status;	/* 0x04 Status of decode protection port 0 */
+	u32 decport0_set;	/* 0x08 Set decode protection port 0 */
+	u32 decport0_clear;	/* 0x0c Clear decode protection port 0 */
+	/* For A80 and later SoCs */
+	u32 decport1_status;	/* 0x10 Status of decode protection port 1 */
+	u32 decport1_set;	/* 0x14 Set decode protection port 1 */
+	u32 decport1_clear;	/* 0x18 Clear decode protection port 1 */
+	u32 decport2_status;	/* 0x1c Status of decode protection port 2 */
+	u32 decport2_set;	/* 0x20 Set decode protection port 2 */
+	u32 decport2_clear;	/* 0x24 Clear decode protection port 2 */
+};
+#endif
+
+#define SUN6I_TZPC_DECPORT0_RTC	(1 << 1)
+
+#define SUN8I_H3_TZPC_DECPORT0_ALL  0xbe
+#define SUN8I_H3_TZPC_DECPORT1_ALL  0xff
+#define SUN8I_H3_TZPC_DECPORT2_ALL  0x7f
+
+void tzpc_init(void);
+
+#endif /* _SUNXI_TZPC_H */
diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h
new file mode 100644
index 0000000..38e2ef2
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/watchdog.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * Watchdog register definitions
+ */
+
+#ifndef _SUNXI_WATCHDOG_H_
+#define _SUNXI_WATCHDOG_H_
+
+#define WDT_CTRL_RESTART	(0x1 << 0)
+#define WDT_CTRL_KEY		(0x0a57 << 1)
+
+#if defined(CONFIG_MACH_SUN4I) || \
+    defined(CONFIG_MACH_SUN5I) || \
+    defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I_R40)
+
+#define WDT_MODE_EN		(0x1 << 0)
+#define WDT_MODE_RESET_EN	(0x1 << 1)
+
+struct sunxi_wdog {
+	u32 ctl;		/* 0x00 */
+	u32 mode;		/* 0x04 */
+	u32 res[2];
+};
+
+#else
+
+#define WDT_CFG_RESET		(0x1)
+#define WDT_MODE_EN		(0x1)
+
+struct sunxi_wdog {
+	u32 irq_en;		/* 0x00 */
+	u32 irq_sta;		/* 0x04 */
+	u32 res1[2];
+	u32 ctl;		/* 0x10 */
+	u32 cfg;		/* 0x14 */
+	u32 mode;		/* 0x18 */
+	u32 res2;
+};
+
+#endif
+
+#endif /* _SUNXI_WATCHDOG_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h
new file mode 100644
index 0000000..de21dff
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+#include <asm/types.h>
+
+/* Stabilization delays, in usec */
+#define PLL_STABILIZATION_DELAY	(300)
+#define IO_STABILIZATION_DELAY	(1000)
+
+#define PLLX_ENABLED		(1 << 30)
+#define CCLK_BURST_POLICY	0x20008888
+#define SUPER_CCLK_DIVIDER	0x80000000
+
+/* Calculate clock fractional divider value from ref and target frequencies */
+#define CLK_DIVIDER(REF, FREQ)	((((REF) * 2) / FREQ) - 2)
+
+/* Calculate clock frequency value from reference and clock divider value */
+#define CLK_FREQUENCY(REF, REG)	(((REF) * 2) / (REG + 2))
+
+/* AVP/CPU ID */
+#define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
+#define PG_UP_TAG_0		0x0
+
+/* AP base physical address of internal SRAM */
+#define NV_PA_BASE_SRAM		0x40000000
+
+#define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
+#define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
+#define CSITE_CPU_DBG1_LAR		(NV_PA_CSITE_BASE + 0x12FB0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS	(NV_PA_FLOW_BASE + 4)
+#define FLOW_MODE_STOP			2
+#define HALT_COP_EVENT_JTAG		(1 << 28)
+#define HALT_COP_EVENT_IRQ_1		(1 << 11)
+#define HALT_COP_EVENT_FIQ_1		(1 << 9)
+
+/* This is the main entry into U-Boot, used by the Cortex-A9 */
+extern void _start(void);
+
+/**
+ * Works out the SOC/SKU type used for clocks settings
+ *
+ * @return	SOC type - see TEGRA_SOC...
+ */
+int tegra_get_chip_sku(void);
+
+/**
+ * Returns the pure SOC (chip ID) from the HIDREV register
+ *
+ * @return	SOC ID - see CHIPID_TEGRAxx...
+ */
+int tegra_get_chip(void);
+
+/**
+ * Returns the SKU ID from the sku_info register
+ *
+ * @return	SKU ID - see SKU_ID_Txx...
+ */
+int tegra_get_sku_info(void);
+
+/* Do any chip-specific cache config */
+void config_cache(void);
+
+#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
+bool tegra_cpu_is_non_secure(void);
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/apb_misc.h b/arch/arm/include/asm/arch-tegra/apb_misc.h
new file mode 100644
index 0000000..d438966
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/apb_misc.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef _GP_PADCTRL_H_
+#define _GP_PADCTRL_H_
+
+/* APB_MISC_PP registers */
+struct apb_misc_pp_ctlr {
+	u32	reserved0[2];
+	u32	strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
+	u32	reserved1[6];	/* 0x0c .. 0x20 */
+	u32	cfg_ctl;	/* 0x24 */
+};
+
+/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
+#define RAM_CODE_SHIFT		4
+#define RAM_CODE_MASK		(0xf << RAM_CODE_SHIFT)
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h
new file mode 100644
index 0000000..24d0db8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_BOARD_H_
+#define _TEGRA_BOARD_H_
+
+/* Set up pinmux to make UART usable */
+void gpio_early_init_uart(void);
+
+/* Set up early UART output */
+void board_init_uart_f(void);
+
+/* Set up any early GPIOs the board might need for proper operation */
+void gpio_early_init(void);  /* overrideable GPIO config        */
+
+/*
+ * Hooks to allow boards to set up the pinmux for a specific function.
+ * Has to be implemented in the board files as we don't yet support pinmux
+ * setup from FDT. If a board file does not implement one of those functions
+ * an empty stub function will be called.
+ */
+
+void pinmux_init(void);      /* overridable general pinmux setup */
+void pin_mux_usb(void);      /* overridable USB pinmux setup     */
+void pin_mux_spi(void);      /* overridable SPI pinmux setup     */
+void pin_mux_nand(void);     /* overridable NAND pinmux setup    */
+void pin_mux_mmc(void);      /* overridable mmc pinmux setup     */
+void pin_mux_display(void);  /* overridable DISPLAY pinmux setup */
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/bpmp_abi.h b/arch/arm/include/asm/arch-tegra/bpmp_abi.h
new file mode 100644
index 0000000..373da52
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/bpmp_abi.h
@@ -0,0 +1,1590 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _ABI_BPMP_ABI_H_
+#define _ABI_BPMP_ABI_H_
+
+#ifdef LK
+#include <stdint.h>
+#endif
+
+#ifndef __ABI_PACKED
+#define __ABI_PACKED __attribute__((packed))
+#endif
+
+#ifdef NO_GCC_EXTENSIONS
+#define EMPTY char empty;
+#define EMPTY_ARRAY 1
+#else
+#define EMPTY
+#define EMPTY_ARRAY 0
+#endif
+
+#ifndef __UNION_ANON
+#define __UNION_ANON
+#endif
+/**
+ * @file
+ */
+
+
+/**
+ * @defgroup MRQ MRQ Messages
+ * @brief Messages sent to/from BPMP via IPC
+ * @{
+ *   @defgroup MRQ_Format Message Format
+ *   @defgroup MRQ_Codes Message Request (MRQ) Codes
+ *   @defgroup MRQ_Payloads Message Payloads
+ *   @defgroup Error_Codes Error Codes
+ * @}
+ */
+
+/**
+ * @addtogroup MRQ_Format Message Format
+ * @{
+ * The CPU requests the BPMP to perform a particular service by
+ * sending it an IVC frame containing a single MRQ message. An MRQ
+ * message consists of a @ref mrq_request followed by a payload whose
+ * format depends on mrq_request::mrq.
+ *
+ * The BPMP processes the data and replies with an IVC frame (on the
+ * same IVC channel) containing and MRQ response. An MRQ response
+ * consists of a @ref mrq_response followed by a payload whose format
+ * depends on the associated mrq_request::mrq.
+ *
+ * A well-defined subset of the MRQ messages that the CPU sends to the
+ * BPMP can lead to BPMP eventually sending an MRQ message to the
+ * CPU. For example, when the CPU uses an #MRQ_THERMAL message to set
+ * a thermal trip point, the BPMP may eventually send a single
+ * #MRQ_THERMAL message of its own to the CPU indicating that the trip
+ * point has been crossed.
+ * @}
+ */
+
+/**
+ * @ingroup MRQ_Format
+ * @brief header for an MRQ message
+ *
+ * Provides the MRQ number for the MRQ message: #mrq. The remainder of
+ * the MRQ message is a payload (immediately following the
+ * mrq_request) whose format depends on mrq.
+ *
+ * @todo document the flags
+ */
+struct mrq_request {
+	/** @brief MRQ number of the request */
+	uint32_t mrq;
+	/** @brief flags for the request */
+	uint32_t flags;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Format
+ * @brief header for an MRQ response
+ *
+ *  Provides an error code for the associated MRQ message. The
+ *  remainder of the MRQ response is a payload (immediately following
+ *  the mrq_response) whose format depends on the associated
+ *  mrq_request::mrq
+ *
+ * @todo document the flags
+ */
+struct mrq_response {
+	/** @brief error code for the MRQ request itself */
+	int32_t err;
+	/** @brief flags for the response */
+	uint32_t flags;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Format
+ * Minimum needed size for an IPC message buffer
+ */
+#define MSG_MIN_SZ	128
+/**
+ * @ingroup MRQ_Format
+ *  Minimum size guaranteed for data in an IPC message buffer
+ */
+#define MSG_DATA_MIN_SZ	120
+
+/**
+ * @ingroup MRQ_Codes
+ * @name Legal MRQ codes
+ * These are the legal values for mrq_request::mrq
+ * @{
+ */
+
+#define MRQ_PING		0
+#define MRQ_QUERY_TAG		1
+#define MRQ_MODULE_LOAD		4
+#define MRQ_MODULE_UNLOAD	5
+#define MRQ_TRACE_MODIFY	7
+#define MRQ_WRITE_TRACE		8
+#define MRQ_THREADED_PING	9
+#define MRQ_MODULE_MAIL		11
+#define MRQ_DEBUGFS		19
+#define MRQ_RESET		20
+#define MRQ_I2C			21
+#define MRQ_CLK			22
+#define MRQ_QUERY_ABI		23
+#define MRQ_PG_READ_STATE	25
+#define MRQ_PG_UPDATE_STATE	26
+#define MRQ_THERMAL		27
+#define MRQ_CPU_VHINT		28
+#define MRQ_ABI_RATCHET		29
+#define MRQ_EMC_DVFS_LATENCY	31
+#define MRQ_TRACE_ITER		64
+
+/** @} */
+
+/**
+ * @ingroup MRQ_Codes
+ * @brief Maximum MRQ code to be sent by CPU software to
+ * BPMP. Subject to change in future
+ */
+#define MAX_CPU_MRQ_ID		64
+
+/**
+ * @addtogroup MRQ_Payloads Message Payloads
+ * @{
+ *   @defgroup Ping
+ *   @defgroup Query_Tag Query Tag
+ *   @defgroup Module Loadable Modules
+ *   @defgroup Trace
+ *   @defgroup Debugfs
+ *   @defgroup Reset
+ *   @defgroup I2C
+ *   @defgroup Clocks
+ *   @defgroup ABI_info ABI Info
+ *   @defgroup MC_Flush MC Flush
+ *   @defgroup Powergating
+ *   @defgroup Thermal
+ *   @defgroup Vhint CPU Voltage hint
+ *   @defgroup MRQ_Deprecated Deprecated MRQ messages
+ *   @defgroup EMC
+ * @}
+ */
+
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_PING
+ * @brief A simple ping
+ *
+ * * Platforms: All
+ * * Initiators: Any
+ * * Targets: Any
+ * * Request Payload: @ref mrq_ping_request
+ * * Response Payload: @ref mrq_ping_response
+ *
+ * @ingroup MRQ_Codes
+ * @def MRQ_THREADED_PING
+ * @brief A deeper ping
+ *
+ * * Platforms: All
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_ping_request
+ * * Response Payload: @ref mrq_ping_response
+ *
+ * Behavior is equivalent to a simple #MRQ_PING except that BPMP
+ * responds from a thread context (providing a slightly more robust
+ * sign of life).
+ *
+ */
+
+/**
+ * @ingroup Ping
+ * @brief request with #MRQ_PING
+ *
+ * Used by the sender of an #MRQ_PING message to request a pong from
+ * recipient. The response from the recipient is computed based on
+ * #challenge.
+ */
+struct mrq_ping_request {
+/** @brief arbitrarily chosen value */
+	uint32_t challenge;
+} __ABI_PACKED;
+
+/**
+ * @ingroup Ping
+ * @brief response to #MRQ_PING
+ *
+ * Sent in response to an #MRQ_PING message. #reply should be the
+ * mrq_ping_request challenge left shifted by 1 with the carry-bit
+ * dropped.
+ *
+ */
+struct mrq_ping_response {
+	/** @brief response to the MRQ_PING challege */
+	uint32_t reply;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_QUERY_TAG
+ * @brief Query BPMP firmware's tag (i.e. version information)
+ *
+ * * Platforms: All
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_query_tag_request
+ * * Response Payload: N/A
+ *
+ */
+
+/**
+ * @ingroup Query_Tag
+ * @brief request with #MRQ_QUERY_TAG
+ *
+ * Used by #MRQ_QUERY_TAG call to ask BPMP to fill in the memory
+ * pointed by #addr with BPMP firmware header.
+ *
+ * The sender is reponsible for ensuring that #addr is mapped in to
+ * the recipient's address map.
+ */
+struct mrq_query_tag_request {
+  /** @brief base address to store the firmware header */
+	uint32_t addr;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_MODULE_LOAD
+ * @brief dynamically load a BPMP code module
+ *
+ * * Platforms: All
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_module_load_request
+ * * Response Payload: @ref mrq_module_load_response
+ *
+ * @note This MRQ is disabled on production systems
+ *
+ */
+
+/**
+ * @ingroup Module
+ * @brief request with #MRQ_MODULE_LOAD
+ *
+ * Used by #MRQ_MODULE_LOAD calls to ask the recipient to dynamically
+ * load the code located at #phys_addr and having size #size
+ * bytes. #phys_addr is treated as a void pointer.
+ *
+ * The recipient copies the code from #phys_addr to locally allocated
+ * memory prior to responding to this message.
+ *
+ * @todo document the module header format
+ *
+ * The sender is responsible for ensuring that the code is mapped in
+ * the recipient's address map.
+ *
+ */
+struct mrq_module_load_request {
+	/** @brief base address of the code to load. Treated as (void *) */
+	uint32_t phys_addr; /* (void *) */
+	/** @brief size in bytes of code to load */
+	uint32_t size;
+} __ABI_PACKED;
+
+/**
+ * @ingroup Module
+ * @brief response to #MRQ_MODULE_LOAD
+ *
+ * @todo document mrq_response::err
+ */
+struct mrq_module_load_response {
+	/** @brief handle to the loaded module */
+	uint32_t base;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_MODULE_UNLOAD
+ * @brief unload a previously loaded code module
+ *
+ * * Platforms: All
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_module_unload_request
+ * * Response Payload: N/A
+ *
+ * @note This MRQ is disabled on production systems
+ */
+
+/**
+ * @ingroup Module
+ * @brief request with #MRQ_MODULE_UNLOAD
+ *
+ * Used by #MRQ_MODULE_UNLOAD calls to request that a previously loaded
+ * module be unloaded.
+ */
+struct mrq_module_unload_request {
+	/** @brief handle of the module to unload */
+	uint32_t base;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_TRACE_MODIFY
+ * @brief modify the set of enabled trace events
+ *
+ * * Platforms: All
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_trace_modify_request
+ * * Response Payload: @ref mrq_trace_modify_response
+ *
+ * @note This MRQ is disabled on production systems
+ */
+
+/**
+ * @ingroup Trace
+ * @brief request with #MRQ_TRACE_MODIFY
+ *
+ * Used by %MRQ_TRACE_MODIFY calls to enable or disable specify trace
+ * events.  #set takes precedence for any bit set in both #set and
+ * #clr.
+ */
+struct mrq_trace_modify_request {
+	/** @brief bit mask of trace events to disable */
+	uint32_t clr;
+	/** @brief bit mask of trace events to enable */
+	uint32_t set;
+} __ABI_PACKED;
+
+/**
+ * @ingroup Trace
+ * @brief response to #MRQ_TRACE_MODIFY
+ *
+ * Sent in repsonse to an #MRQ_TRACE_MODIFY message. #mask reflects the
+ * state of which events are enabled after the recipient acted on the
+ * message.
+ *
+ */
+struct mrq_trace_modify_response {
+	/** @brief bit mask of trace event enable states */
+	uint32_t mask;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_WRITE_TRACE
+ * @brief Write trace data to a buffer
+ *
+ * * Platforms: All
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_write_trace_request
+ * * Response Payload: @ref mrq_write_trace_response
+ *
+ * mrq_response::err depends on the @ref mrq_write_trace_request field
+ * values. err is -#BPMP_EINVAL if size is zero or area is NULL or
+ * area is in an illegal range. A positive value for err indicates the
+ * number of bytes written to area.
+ *
+ * @note This MRQ is disabled on production systems
+ */
+
+/**
+ * @ingroup Trace
+ * @brief request with #MRQ_WRITE_TRACE
+ *
+ * Used by MRQ_WRITE_TRACE calls to ask the recipient to copy trace
+ * data from the recipient's local buffer to the output buffer. #area
+ * is treated as a byte-aligned pointer in the recipient's address
+ * space.
+ *
+ * The sender is responsible for ensuring that the output
+ * buffer is mapped in the recipient's address map. The recipient is
+ * responsible for protecting its own code and data from accidental
+ * overwrites.
+ */
+struct mrq_write_trace_request {
+	/** @brief base address of output buffer */
+	uint32_t area;
+	/** @brief size in bytes of the output buffer */
+	uint32_t size;
+} __ABI_PACKED;
+
+/**
+ * @ingroup Trace
+ * @brief response to #MRQ_WRITE_TRACE
+ *
+ * Once this response is sent, the respondent will not access the
+ * output buffer further.
+ */
+struct mrq_write_trace_response {
+	/**
+	 * @brief flag whether more data remains in local buffer
+	 *
+	 * Value is 1 if the entire local trace buffer has been
+	 * drained to the outputbuffer. Value is 0 otherwise.
+	 */
+	uint32_t eof;
+} __ABI_PACKED;
+
+/** @private */
+struct mrq_threaded_ping_request {
+	uint32_t challenge;
+} __ABI_PACKED;
+
+/** @private */
+struct mrq_threaded_ping_response {
+	uint32_t reply;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_MODULE_MAIL
+ * @brief send a message to a loadable module
+ *
+ * * Platforms: All
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_module_mail_request
+ * * Response Payload: @ref mrq_module_mail_response
+ *
+ * @note This MRQ is disabled on production systems
+ */
+
+/**
+ * @ingroup Module
+ * @brief request with #MRQ_MODULE_MAIL
+ */
+struct mrq_module_mail_request {
+	/** @brief handle to the previously loaded module */
+	uint32_t base;
+	/** @brief module-specific mail payload
+	 *
+	 * The length of data[ ] is unknown to the BPMP core firmware
+	 * but it is limited to the size of an IPC message.
+	 */
+	uint8_t data[EMPTY_ARRAY];
+} __ABI_PACKED;
+
+/**
+ * @ingroup Module
+ * @brief response to #MRQ_MODULE_MAIL
+ */
+struct mrq_module_mail_response {
+	/** @brief module-specific mail payload
+	 *
+	 * The length of data[ ] is unknown to the BPMP core firmware
+	 * but it is limited to the size of an IPC message.
+	 */
+	uint8_t data[EMPTY_ARRAY];
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_DEBUGFS
+ * @brief Interact with BPMP's debugfs file nodes
+ *
+ * * Platforms: T186
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_debugfs_request
+ * * Response Payload: @ref mrq_debugfs_response
+ */
+
+/**
+ * @addtogroup Debugfs
+ * @{
+ *
+ * The BPMP firmware implements a pseudo-filesystem called
+ * debugfs. Any driver within the firmware may register with debugfs
+ * to expose an arbitrary set of "files" in the filesystem. When
+ * software on the CPU writes to a debugfs file, debugfs passes the
+ * written data to a callback provided by the driver. When software on
+ * the CPU reads a debugfs file, debugfs queries the driver for the
+ * data to return to the CPU. The intention of the debugfs filesystem
+ * is to provide information useful for debugging the system at
+ * runtime.
+ *
+ * @note The files exposed via debugfs are not part of the
+ * BPMP firmware's ABI. debugfs files may be added or removed in any
+ * given version of the firmware. Typically the semantics of a debugfs
+ * file are consistent from version to version but even that is not
+ * guaranteed.
+ *
+ * @}
+ */
+/** @ingroup Debugfs */
+enum mrq_debugfs_commands {
+	CMD_DEBUGFS_READ = 1,
+	CMD_DEBUGFS_WRITE = 2,
+	CMD_DEBUGFS_DUMPDIR = 3,
+	CMD_DEBUGFS_MAX
+};
+
+/**
+ * @ingroup Debugfs
+ * @brief parameters for CMD_DEBUGFS_READ/WRITE command
+ */
+struct cmd_debugfs_fileop_request {
+	/** @brief physical address pointing at filename */
+	uint32_t fnameaddr;
+	/** @brief length in bytes of filename buffer */
+	uint32_t fnamelen;
+	/** @brief physical address pointing to data buffer */
+	uint32_t dataaddr;
+	/** @brief length in bytes of data buffer */
+	uint32_t datalen;
+} __ABI_PACKED;
+
+/**
+ * @ingroup Debugfs
+ * @brief parameters for CMD_DEBUGFS_READ/WRITE command
+ */
+struct cmd_debugfs_dumpdir_request {
+	/** @brief physical address pointing to data buffer */
+	uint32_t dataaddr;
+	/** @brief length in bytes of data buffer */
+	uint32_t datalen;
+} __ABI_PACKED;
+
+/**
+ * @ingroup Debugfs
+ * @brief response data for CMD_DEBUGFS_READ/WRITE command
+ */
+struct cmd_debugfs_fileop_response {
+	/** @brief always 0 */
+	uint32_t reserved;
+	/** @brief number of bytes read from or written to data buffer */
+	uint32_t nbytes;
+} __ABI_PACKED;
+
+/**
+ * @ingroup Debugfs
+ * @brief response data for CMD_DEBUGFS_DUMPDIR command
+ */
+struct cmd_debugfs_dumpdir_response {
+	/** @brief always 0 */
+	uint32_t reserved;
+	/** @brief number of bytes read from or written to data buffer */
+	uint32_t nbytes;
+} __ABI_PACKED;
+
+/**
+ * @ingroup Debugfs
+ * @brief request with #MRQ_DEBUGFS.
+ *
+ * The sender of an MRQ_DEBUGFS message uses #cmd to specify a debugfs
+ * command to execute. Legal commands are the values of @ref
+ * mrq_debugfs_commands. Each command requires a specific additional
+ * payload of data.
+ *
+ * |command            |payload|
+ * |-------------------|-------|
+ * |CMD_DEBUGFS_READ   |fop    |
+ * |CMD_DEBUGFS_WRITE  |fop    |
+ * |CMD_DEBUGFS_DUMPDIR|dumpdir|
+ */
+struct mrq_debugfs_request {
+	uint32_t cmd;
+	union {
+		struct cmd_debugfs_fileop_request fop;
+		struct cmd_debugfs_dumpdir_request dumpdir;
+	} __UNION_ANON;
+} __ABI_PACKED;
+
+/**
+ * @ingroup Debugfs
+ */
+struct mrq_debugfs_response {
+	/** @brief always 0 */
+	int32_t reserved;
+	union {
+		/** @brief response data for CMD_DEBUGFS_READ OR
+		 * CMD_DEBUGFS_WRITE command
+		 */
+		struct cmd_debugfs_fileop_response fop;
+		/** @brief response data for CMD_DEBUGFS_DUMPDIR command */
+		struct cmd_debugfs_dumpdir_response dumpdir;
+	} __UNION_ANON;
+} __ABI_PACKED;
+
+/**
+ * @addtogroup Debugfs
+ * @{
+ */
+#define DEBUGFS_S_ISDIR	(1 << 9)
+#define DEBUGFS_S_IRUSR	(1 << 8)
+#define DEBUGFS_S_IWUSR	(1 << 7)
+/** @} */
+
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_RESET
+ * @brief reset an IP block
+ *
+ * * Platforms: T186
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_reset_request
+ * * Response Payload: N/A
+ */
+
+/**
+ * @ingroup Reset
+ */
+enum mrq_reset_commands {
+	CMD_RESET_ASSERT = 1,
+	CMD_RESET_DEASSERT = 2,
+	CMD_RESET_MODULE = 3,
+	CMD_RESET_MAX, /* not part of ABI and subject to change */
+};
+
+/**
+ * @ingroup Reset
+ * @brief request with MRQ_RESET
+ *
+ * Used by the sender of an #MRQ_RESET message to request BPMP to
+ * assert or or deassert a given reset line.
+ */
+struct mrq_reset_request {
+	/** @brief reset action to perform (@enum mrq_reset_commands) */
+	uint32_t cmd;
+	/** @brief id of the reset to affected */
+	uint32_t reset_id;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_I2C
+ * @brief issue an i2c transaction
+ *
+ * * Platforms: T186
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_i2c_request
+ * * Response Payload: @ref mrq_i2c_response
+ */
+
+/**
+ * @addtogroup I2C
+ * @{
+ */
+#define TEGRA_I2C_IPC_MAX_IN_BUF_SIZE	(MSG_DATA_MIN_SZ - 12)
+#define TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE	(MSG_DATA_MIN_SZ - 4)
+/** @} */
+
+/**
+ * @ingroup I2C
+ * @name Serial I2C flags
+ * Use these flags with serial_i2c_request::flags
+ * @{
+ */
+#define SERIALI2C_TEN           0x0010
+#define SERIALI2C_RD            0x0001
+#define SERIALI2C_STOP          0x8000
+#define SERIALI2C_NOSTART       0x4000
+#define SERIALI2C_REV_DIR_ADDR  0x2000
+#define SERIALI2C_IGNORE_NAK    0x1000
+#define SERIALI2C_NO_RD_ACK     0x0800
+#define SERIALI2C_RECV_LEN      0x0400
+/** @} */
+/** @ingroup I2C */
+enum {
+	CMD_I2C_XFER = 1
+};
+
+/**
+ * @ingroup I2C
+ * @brief serializable i2c request
+ *
+ * Instances of this structure are packed (little-endian) into
+ * cmd_i2c_xfer_request::data_buf. Each instance represents a single
+ * transaction (or a portion of a transaction with repeated starts) on
+ * an i2c bus.
+ *
+ * Because these structures are packed, some instances are likely to
+ * be misaligned. Additionally because #data is variable length, it is
+ * not possible to iterate through a serialized list of these
+ * structures without inspecting #len in each instance.  It may be
+ * easier to serialize or deserialize cmd_i2c_xfer_request::data_buf
+ * manually rather than using this structure definition.
+*/
+struct serial_i2c_request {
+	/** @brief I2C slave address */
+	uint16_t addr;
+	/** @brief bitmask of SERIALI2C_ flags */
+	uint16_t flags;
+	/** @brief length of I2C transaction in bytes */
+	uint16_t len;
+	/** @brief for write transactions only, #len bytes of data */
+	uint8_t data[];
+} __ABI_PACKED;
+
+/**
+ * @ingroup I2C
+ * @brief trigger one or more i2c transactions
+ */
+struct cmd_i2c_xfer_request {
+	/** @brief valid bus number from mach-t186/i2c-t186.h*/
+	uint32_t bus_id;
+
+	/** @brief count of valid bytes in #data_buf*/
+	uint32_t data_size;
+
+	/** @brief serialized packed instances of @ref serial_i2c_request*/
+	uint8_t data_buf[TEGRA_I2C_IPC_MAX_IN_BUF_SIZE];
+} __ABI_PACKED;
+
+/**
+ * @ingroup I2C
+ * @brief container for data read from the i2c bus
+ *
+ * Processing an cmd_i2c_xfer_request::data_buf causes BPMP to execute
+ * zero or more I2C reads. The data read from the bus is serialized
+ * into #data_buf.
+ */
+struct cmd_i2c_xfer_response {
+	/** @brief count of valid bytes in #data_buf*/
+	uint32_t data_size;
+	/** @brief i2c read data */
+	uint8_t data_buf[TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE];
+} __ABI_PACKED;
+
+/**
+ * @ingroup I2C
+ * @brief request with #MRQ_I2C
+ */
+struct mrq_i2c_request {
+	/** @brief always CMD_I2C_XFER (i.e. 1) */
+	uint32_t cmd;
+	/** @brief parameters of the transfer request */
+	struct cmd_i2c_xfer_request xfer;
+} __ABI_PACKED;
+
+/**
+ * @ingroup I2C
+ * @brief response to #MRQ_I2C
+ */
+struct mrq_i2c_response {
+	struct cmd_i2c_xfer_response xfer;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_CLK
+ *
+ * * Platforms: T186
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_clk_request
+ * * Response Payload: @ref mrq_clk_response
+ * @addtogroup Clocks
+ * @{
+ */
+
+/**
+ * @name MRQ_CLK sub-commands
+ * @{
+ */
+enum {
+	CMD_CLK_GET_RATE = 1,
+	CMD_CLK_SET_RATE = 2,
+	CMD_CLK_ROUND_RATE = 3,
+	CMD_CLK_GET_PARENT = 4,
+	CMD_CLK_SET_PARENT = 5,
+	CMD_CLK_IS_ENABLED = 6,
+	CMD_CLK_ENABLE = 7,
+	CMD_CLK_DISABLE = 8,
+	CMD_CLK_GET_ALL_INFO = 14,
+	CMD_CLK_GET_MAX_CLK_ID = 15,
+	CMD_CLK_MAX,
+};
+/** @} */
+
+#define MRQ_CLK_NAME_MAXLEN	40
+#define MRQ_CLK_MAX_PARENTS	16
+
+/** @private */
+struct cmd_clk_get_rate_request {
+	EMPTY
+} __ABI_PACKED;
+
+struct cmd_clk_get_rate_response {
+	int64_t rate;
+} __ABI_PACKED;
+
+struct cmd_clk_set_rate_request {
+	int32_t unused;
+	int64_t rate;
+} __ABI_PACKED;
+
+struct cmd_clk_set_rate_response {
+	int64_t rate;
+} __ABI_PACKED;
+
+struct cmd_clk_round_rate_request {
+	int32_t unused;
+	int64_t rate;
+} __ABI_PACKED;
+
+struct cmd_clk_round_rate_response {
+	int64_t rate;
+} __ABI_PACKED;
+
+/** @private */
+struct cmd_clk_get_parent_request {
+	EMPTY
+} __ABI_PACKED;
+
+struct cmd_clk_get_parent_response {
+	uint32_t parent_id;
+} __ABI_PACKED;
+
+struct cmd_clk_set_parent_request {
+	uint32_t parent_id;
+} __ABI_PACKED;
+
+struct cmd_clk_set_parent_response {
+	uint32_t parent_id;
+} __ABI_PACKED;
+
+/** @private */
+struct cmd_clk_is_enabled_request {
+	EMPTY
+} __ABI_PACKED;
+
+struct cmd_clk_is_enabled_response {
+	int32_t state;
+} __ABI_PACKED;
+
+/** @private */
+struct cmd_clk_enable_request {
+	EMPTY
+} __ABI_PACKED;
+
+/** @private */
+struct cmd_clk_enable_response {
+	EMPTY
+} __ABI_PACKED;
+
+/** @private */
+struct cmd_clk_disable_request {
+	EMPTY
+} __ABI_PACKED;
+
+/** @private */
+struct cmd_clk_disable_response {
+	EMPTY
+} __ABI_PACKED;
+
+/** @private */
+struct cmd_clk_get_all_info_request {
+	EMPTY
+} __ABI_PACKED;
+
+struct cmd_clk_get_all_info_response {
+	uint32_t flags;
+	uint32_t parent;
+	uint32_t parents[MRQ_CLK_MAX_PARENTS];
+	uint8_t num_parents;
+	uint8_t name[MRQ_CLK_NAME_MAXLEN];
+} __ABI_PACKED;
+
+/** @private */
+struct cmd_clk_get_max_clk_id_request {
+	EMPTY
+} __ABI_PACKED;
+
+struct cmd_clk_get_max_clk_id_response {
+	uint32_t max_id;
+} __ABI_PACKED;
+/** @} */
+
+/**
+ * @ingroup Clocks
+ * @brief request with #MRQ_CLK
+ *
+ * Used by the sender of an #MRQ_CLK message to control clocks. The
+ * clk_request is split into several sub-commands. Some sub-commands
+ * require no additional data. Others have a sub-command specific
+ * payload
+ *
+ * |sub-command                 |payload                |
+ * |----------------------------|-----------------------|
+ * |CMD_CLK_GET_RATE            |-                      |
+ * |CMD_CLK_SET_RATE            |clk_set_rate           |
+ * |CMD_CLK_ROUND_RATE          |clk_round_rate         |
+ * |CMD_CLK_GET_PARENT          |-                      |
+ * |CMD_CLK_SET_PARENT          |clk_set_parent         |
+ * |CMD_CLK_IS_ENABLED          |-                      |
+ * |CMD_CLK_ENABLE              |-                      |
+ * |CMD_CLK_DISABLE             |-                      |
+ * |CMD_CLK_GET_ALL_INFO        |-                      |
+ * |CMD_CLK_GET_MAX_CLK_ID      |-                      |
+ *
+ */
+
+struct mrq_clk_request {
+	/** @brief sub-command and clock id concatenated to 32-bit word.
+	 * - bits[31..24] is the sub-cmd.
+	 * - bits[23..0] is the clock id
+	 */
+	uint32_t cmd_and_id;
+
+	union {
+		/** @private */
+		struct cmd_clk_get_rate_request clk_get_rate;
+		struct cmd_clk_set_rate_request clk_set_rate;
+		struct cmd_clk_round_rate_request clk_round_rate;
+		/** @private */
+		struct cmd_clk_get_parent_request clk_get_parent;
+		struct cmd_clk_set_parent_request clk_set_parent;
+		/** @private */
+		struct cmd_clk_enable_request clk_enable;
+		/** @private */
+		struct cmd_clk_disable_request clk_disable;
+		/** @private */
+		struct cmd_clk_is_enabled_request clk_is_enabled;
+		/** @private */
+		struct cmd_clk_get_all_info_request clk_get_all_info;
+		/** @private */
+		struct cmd_clk_get_max_clk_id_request clk_get_max_clk_id;
+	} __UNION_ANON;
+} __ABI_PACKED;
+
+/**
+ * @ingroup Clocks
+ * @brief response to MRQ_CLK
+ *
+ * Each sub-command supported by @ref mrq_clk_request may return
+ * sub-command-specific data. Some do and some do not as indicated in
+ * the following table
+ *
+ * |sub-command                 |payload                 |
+ * |----------------------------|------------------------|
+ * |CMD_CLK_GET_RATE            |clk_get_rate            |
+ * |CMD_CLK_SET_RATE            |clk_set_rate            |
+ * |CMD_CLK_ROUND_RATE          |clk_round_rate          |
+ * |CMD_CLK_GET_PARENT          |clk_get_parent          |
+ * |CMD_CLK_SET_PARENT          |clk_set_parent          |
+ * |CMD_CLK_IS_ENABLED          |clk_is_enabled          |
+ * |CMD_CLK_ENABLE              |-                       |
+ * |CMD_CLK_DISABLE             |-                       |
+ * |CMD_CLK_GET_ALL_INFO        |clk_get_all_info        |
+ * |CMD_CLK_GET_MAX_CLK_ID      |clk_get_max_id          |
+ *
+ */
+
+struct mrq_clk_response {
+	union {
+		struct cmd_clk_get_rate_response clk_get_rate;
+		struct cmd_clk_set_rate_response clk_set_rate;
+		struct cmd_clk_round_rate_response clk_round_rate;
+		struct cmd_clk_get_parent_response clk_get_parent;
+		struct cmd_clk_set_parent_response clk_set_parent;
+		/** @private */
+		struct cmd_clk_enable_response clk_enable;
+		/** @private */
+		struct cmd_clk_disable_response clk_disable;
+		struct cmd_clk_is_enabled_response clk_is_enabled;
+		struct cmd_clk_get_all_info_response clk_get_all_info;
+		struct cmd_clk_get_max_clk_id_response clk_get_max_clk_id;
+	} __UNION_ANON;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_QUERY_ABI
+ * @brief check if an MRQ is implemented
+ *
+ * * Platforms: All
+ * * Initiators: Any
+ * * Targets: Any
+ * * Request Payload: @ref mrq_query_abi_request
+ * * Response Payload: @ref mrq_query_abi_response
+ */
+
+/**
+ * @ingroup ABI_info
+ * @brief request with MRQ_QUERY_ABI
+ *
+ * Used by #MRQ_QUERY_ABI call to check if MRQ code #mrq is supported
+ * by the recipient.
+ */
+struct mrq_query_abi_request {
+	/** @brief MRQ code to query */
+	uint32_t mrq;
+} __ABI_PACKED;
+
+/**
+ * @ingroup ABI_info
+ * @brief response to MRQ_QUERY_ABI
+ */
+struct mrq_query_abi_response {
+	/** @brief 0 if queried MRQ is supported. Else, -#BPMP_ENODEV */
+	int32_t status;
+} __ABI_PACKED;
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_PG_READ_STATE
+ * @brief read the power-gating state of a partition
+ *
+ * * Platforms: T186
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_pg_read_state_request
+ * * Response Payload: @ref mrq_pg_read_state_response
+ * @addtogroup Powergating
+ * @{
+ */
+
+/**
+ * @brief request with #MRQ_PG_READ_STATE
+ *
+ * Used by MRQ_PG_READ_STATE call to read the current state of a
+ * partition.
+ */
+struct mrq_pg_read_state_request {
+	/** @brief ID of partition */
+	uint32_t partition_id;
+} __ABI_PACKED;
+
+/**
+ * @brief response to MRQ_PG_READ_STATE
+ * @todo define possible errors.
+ */
+struct mrq_pg_read_state_response {
+	/** @brief read as don't care */
+	uint32_t sram_state;
+	/** @brief state of power partition
+	 * * 0 : off
+	 * * 1 : on
+	 */
+	uint32_t logic_state;
+} __ABI_PACKED;
+
+/** @} */
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_PG_UPDATE_STATE
+ * @brief modify the power-gating state of a partition
+ *
+ * * Platforms: T186
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_pg_update_state_request
+ * * Response Payload: N/A
+ * @addtogroup Powergating
+ * @{
+ */
+
+/**
+ * @brief request with mrq_pg_update_state_request
+ *
+ * Used by #MRQ_PG_UPDATE_STATE call to request BPMP to change the
+ * state of a power partition #partition_id.
+ */
+struct mrq_pg_update_state_request {
+	/** @brief ID of partition */
+	uint32_t partition_id;
+	/** @brief secondary control of power partition
+	 *  @details Ignored by many versions of the BPMP
+	 *  firmware. For maximum compatibility, set the value
+	 *  according to @logic_state
+	 * *  0x1: power ON partition (@ref logic_state == 0x3)
+	 * *  0x3: power OFF partition (@ref logic_state == 0x1)
+	 */
+	uint32_t sram_state;
+	/** @brief controls state of power partition, legal values are
+	 * *  0x1 : power OFF partition
+	 * *  0x3 : power ON partition
+	 */
+	uint32_t logic_state;
+	/** @brief change state of clocks of the power partition, legal values
+	 * *  0x0 : do not change clock state
+	 * *  0x1 : disable partition clocks (only applicable when
+	 *          @ref logic_state == 0x1)
+	 * *  0x3 : enable partition clocks (only applicable when
+	 *          @ref logic_state == 0x3)
+	 */
+	uint32_t clock_state;
+} __ABI_PACKED;
+/** @} */
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_THERMAL
+ * @brief interact with BPMP thermal framework
+ *
+ * * Platforms: T186
+ * * Initiators: Any
+ * * Targets: Any
+ * * Request Payload: TODO
+ * * Response Payload: TODO
+ *
+ * @addtogroup Thermal
+ *
+ * The BPMP firmware includes a thermal framework. Drivers within the
+ * bpmp firmware register with the framework to provide thermal
+ * zones. Each thermal zone corresponds to an entity whose temperature
+ * can be measured. The framework also has a notion of trip points. A
+ * trip point consists of a thermal zone id, a temperature, and a
+ * callback routine. The framework invokes the callback when the zone
+ * hits the indicated temperature. The BPMP firmware uses this thermal
+ * framework interally to implement various temperature-dependent
+ * functions.
+ *
+ * Software on the CPU can use #MRQ_THERMAL (with payload @ref
+ * mrq_thermal_host_to_bpmp_request) to interact with the BPMP thermal
+ * framework. The CPU must It can query the number of supported zones,
+ * query zone temperatures, and set trip points.
+ *
+ * When a trip point set by the CPU gets crossed, BPMP firmware issues
+ * an IPC to the CPU having mrq_request::mrq = #MRQ_THERMAL and a
+ * payload of @ref mrq_thermal_bpmp_to_host_request.
+ * @{
+ */
+enum mrq_thermal_host_to_bpmp_cmd {
+	/**
+	 * @brief Check whether the BPMP driver supports the specified
+	 * request type.
+	 *
+	 * Host needs to supply request parameters.
+	 *
+	 * mrq_response::err is 0 if the specified request is
+	 * supported and -#BPMP_ENODEV otherwise.
+	 */
+	CMD_THERMAL_QUERY_ABI = 0,
+
+	/**
+	 * @brief Get the current temperature of the specified zone.
+	 *
+	 * Host needs to supply request parameters.
+	 *
+	 * mrq_response::err is
+	 * *  0: Temperature query succeeded.
+	 * *  -#BPMP_EINVAL: Invalid request parameters.
+	 * *  -#BPMP_ENOENT: No driver registered for thermal zone..
+	 * *  -#BPMP_EFAULT: Problem reading temperature measurement.
+	 */
+	CMD_THERMAL_GET_TEMP = 1,
+
+	/**
+	 * @brief Enable or disable and set the lower and upper
+	 *   thermal limits for a thermal trip point. Each zone has
+	 *   one trip point.
+	 *
+	 * Host needs to supply request parameters. Once the
+	 * temperature hits a trip point, the BPMP will send a message
+	 * to the CPU having MRQ=MRQ_THERMAL and
+	 * type=CMD_THERMAL_HOST_TRIP_REACHED
+	 *
+	 * mrq_response::err is
+	 * *  0: Trip successfully set.
+	 * *  -#BPMP_EINVAL: Invalid request parameters.
+	 * *  -#BPMP_ENOENT: No driver registered for thermal zone.
+	 * *  -#BPMP_EFAULT: Problem setting trip point.
+	 */
+	CMD_THERMAL_SET_TRIP = 2,
+
+	/**
+	 * @brief Get the number of supported thermal zones.
+	 *
+	 * No request parameters required.
+	 *
+	 * mrq_response::err is always 0, indicating success.
+	 */
+	CMD_THERMAL_GET_NUM_ZONES = 3,
+
+	/** @brief: number of supported host-to-bpmp commands. May
+	 * increase in future
+	 */
+	CMD_THERMAL_HOST_TO_BPMP_NUM
+};
+
+enum mrq_thermal_bpmp_to_host_cmd {
+	/**
+	 * @brief Indication that the temperature for a zone has
+	 *   exceeded the range indicated in the thermal trip point
+	 *   for the zone.
+	 *
+	 * BPMP needs to supply request parameters. Host only needs to
+	 * acknowledge.
+	 */
+	CMD_THERMAL_HOST_TRIP_REACHED = 100,
+
+	/** @brief: number of supported bpmp-to-host commands. May
+	 * increase in future
+	 */
+	CMD_THERMAL_BPMP_TO_HOST_NUM
+};
+
+/*
+ * Host->BPMP request data for request type CMD_THERMAL_QUERY_ABI
+ *
+ * zone: Request type for which to check existence.
+ */
+struct cmd_thermal_query_abi_request {
+	uint32_t type;
+} __ABI_PACKED;
+
+/*
+ * Host->BPMP request data for request type CMD_THERMAL_GET_TEMP
+ *
+ * zone: Number of thermal zone.
+ */
+struct cmd_thermal_get_temp_request {
+	uint32_t zone;
+} __ABI_PACKED;
+
+/*
+ * BPMP->Host reply data for request CMD_THERMAL_GET_TEMP
+ *
+ * error: 0 if request succeeded.
+ *	-BPMP_EINVAL if request parameters were invalid.
+ *      -BPMP_ENOENT if no driver was registered for the specified thermal zone.
+ *      -BPMP_EFAULT for other thermal zone driver errors.
+ * temp: Current temperature in millicelsius.
+ */
+struct cmd_thermal_get_temp_response {
+	int32_t temp;
+} __ABI_PACKED;
+
+/*
+ * Host->BPMP request data for request type CMD_THERMAL_SET_TRIP
+ *
+ * zone: Number of thermal zone.
+ * low: Temperature of lower trip point in millicelsius
+ * high: Temperature of upper trip point in millicelsius
+ * enabled: 1 to enable trip point, 0 to disable trip point
+ */
+struct cmd_thermal_set_trip_request {
+	uint32_t zone;
+	int32_t low;
+	int32_t high;
+	uint32_t enabled;
+} __ABI_PACKED;
+
+/*
+ * BPMP->Host request data for request type CMD_THERMAL_HOST_TRIP_REACHED
+ *
+ * zone: Number of thermal zone where trip point was reached.
+ */
+struct cmd_thermal_host_trip_reached_request {
+	uint32_t zone;
+} __ABI_PACKED;
+
+/*
+ * BPMP->Host reply data for request type CMD_THERMAL_GET_NUM_ZONES
+ *
+ * num: Number of supported thermal zones. The thermal zones are indexed
+ *      starting from zero.
+ */
+struct cmd_thermal_get_num_zones_response {
+	uint32_t num;
+} __ABI_PACKED;
+
+/*
+ * Host->BPMP request data.
+ *
+ * Reply type is union mrq_thermal_bpmp_to_host_response.
+ *
+ * type: Type of request. Values listed in enum mrq_thermal_type.
+ * data: Request type specific parameters.
+ */
+struct mrq_thermal_host_to_bpmp_request {
+	uint32_t type;
+	union {
+		struct cmd_thermal_query_abi_request query_abi;
+		struct cmd_thermal_get_temp_request get_temp;
+		struct cmd_thermal_set_trip_request set_trip;
+	} __UNION_ANON;
+} __ABI_PACKED;
+
+/*
+ * BPMP->Host request data.
+ *
+ * type: Type of request. Values listed in enum mrq_thermal_type.
+ * data: Request type specific parameters.
+ */
+struct mrq_thermal_bpmp_to_host_request {
+	uint32_t type;
+	union {
+		struct cmd_thermal_host_trip_reached_request host_trip_reached;
+	} __UNION_ANON;
+} __ABI_PACKED;
+
+/*
+ * Data in reply to a Host->BPMP request.
+ */
+union mrq_thermal_bpmp_to_host_response {
+	struct cmd_thermal_get_temp_response get_temp;
+	struct cmd_thermal_get_num_zones_response get_num_zones;
+} __ABI_PACKED;
+/** @} */
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_CPU_VHINT
+ * @brief Query CPU voltage hint data
+ *
+ * * Platforms: T186
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_cpu_vhint_request
+ * * Response Payload: N/A
+ *
+ * @addtogroup Vhint CPU Voltage hint
+ * @{
+ */
+
+/**
+ * @brief request with #MRQ_CPU_VHINT
+ *
+ * Used by #MRQ_CPU_VHINT call by CCPLEX to retrieve voltage hint data
+ * from BPMP to memory space pointed by #addr. CCPLEX is responsible
+ * to allocate sizeof(cpu_vhint_data) sized block of memory and
+ * appropriately map it for BPMP before sending the request.
+ */
+struct mrq_cpu_vhint_request {
+	/** @brief IOVA address for the #cpu_vhint_data */
+	uint32_t addr; /* struct cpu_vhint_data * */
+	/** @brief ID of the cluster whose data is requested */
+	uint32_t cluster_id; /* enum cluster_id */
+} __ABI_PACKED;
+
+/**
+ * @brief description of the CPU v/f relation
+ *
+ * Used by #MRQ_CPU_VHINT call to carry data pointed by #addr of
+ * struct mrq_cpu_vhint_request
+ */
+struct cpu_vhint_data {
+	uint32_t ref_clk_hz; /**< reference frequency in Hz */
+	uint16_t pdiv; /**< post divider value */
+	uint16_t mdiv; /**< input divider value */
+	uint16_t ndiv_max; /**< fMAX expressed with max NDIV value */
+	/** table of ndiv values as a function of vINDEX (voltage index) */
+	uint16_t ndiv[80];
+	/** minimum allowed NDIV value */
+	uint16_t ndiv_min;
+	/** minimum allowed voltage hint value (as in vINDEX) */
+	uint16_t vfloor;
+	/** maximum allowed voltage hint value (as in vINDEX) */
+	uint16_t vceil;
+	/** post-multiplier for vindex value */
+	uint16_t vindex_mult;
+	/** post-divider for vindex value */
+	uint16_t vindex_div;
+	/** reserved for future use */
+	uint16_t reserved[328];
+} __ABI_PACKED;
+
+/** @} */
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_ABI_RATCHET
+ * @brief ABI ratchet value query
+ *
+ * * Platforms: T186
+ * * Initiators: Any
+ * * Targets: BPMP
+ * * Request Payload: @ref mrq_abi_ratchet_request
+ * * Response Payload: @ref mrq_abi_ratchet_response
+ * @addtogroup ABI_info
+ * @{
+ */
+
+/**
+ * @brief an ABI compatibility mechanism
+ *
+ * BPMP_ABI_RATCHET_VALUE may increase for various reasons in a future
+ * revision of this header file.
+ * 1. That future revision deprecates some MRQ
+ * 2. That future revision introduces a breaking change to an existing
+ *    MRQ or
+ * 3. A bug is discovered in an existing implementation of the BPMP-FW
+ *    (or possibly one of its clients) which warrants deprecating that
+ *    implementation.
+ */
+#define BPMP_ABI_RATCHET_VALUE 3
+
+/**
+ * @brief request with #MRQ_ABI_RATCHET.
+ *
+ * #ratchet should be #BPMP_ABI_RATCHET_VALUE from the ABI header
+ * against which the requester was compiled.
+ *
+ * If ratchet is less than BPMP's #BPMP_ABI_RATCHET_VALUE, BPMP may
+ * reply with mrq_response::err = -#BPMP_ERANGE to indicate that
+ * BPMP-FW cannot interoperate correctly with the requester. Requester
+ * should cease further communication with BPMP.
+ *
+ * Otherwise, err shall be 0.
+ */
+struct mrq_abi_ratchet_request {
+	/** @brief requester's ratchet value */
+	uint16_t ratchet;
+};
+
+/**
+ * @brief response to #MRQ_ABI_RATCHET
+ *
+ * #ratchet shall be #BPMP_ABI_RATCHET_VALUE from the ABI header
+ * against which BPMP firwmare was compiled.
+ *
+ * If #ratchet is less than the requester's #BPMP_ABI_RATCHET_VALUE,
+ * the requster must either interoperate with BPMP according to an ABI
+ * header version with BPMP_ABI_RATCHET_VALUE = ratchet or cease
+ * communication with BPMP.
+ *
+ * If mrq_response::err is 0 and ratchet is greater than or equal to the
+ * requester's BPMP_ABI_RATCHET_VALUE, the requester should continue
+ * normal operation.
+ */
+struct mrq_abi_ratchet_response {
+	/** @brief BPMP's ratchet value */
+	uint16_t ratchet;
+};
+/** @} */
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_EMC_DVFS_LATENCY
+ * @brief query frequency dependent EMC DVFS latency
+ *
+ * * Platforms: T186
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: N/A
+ * * Response Payload: @ref mrq_emc_dvfs_latency_response
+ * @addtogroup EMC
+ * @{
+ */
+
+/**
+ * @brief used by @ref mrq_emc_dvfs_latency_response
+ */
+struct emc_dvfs_latency {
+	/** @brief EMC frequency in kHz */
+	uint32_t freq;
+	/** @brief EMC DVFS latency in nanoseconds */
+	uint32_t latency;
+} __ABI_PACKED;
+
+#define EMC_DVFS_LATENCY_MAX_SIZE	14
+/**
+ * @brief response to #MRQ_EMC_DVFS_LATENCY
+ */
+struct mrq_emc_dvfs_latency_response {
+	/** @brief the number valid entries in #pairs */
+	uint32_t num_pairs;
+	/** @brief EMC <frequency, latency> information */
+	struct emc_dvfs_latency pairs[EMC_DVFS_LATENCY_MAX_SIZE];
+} __ABI_PACKED;
+
+/** @} */
+
+/**
+ * @ingroup MRQ_Codes
+ * @def MRQ_TRACE_ITER
+ * @brief manage the trace iterator
+ *
+ * * Platforms: All
+ * * Initiators: CCPLEX
+ * * Targets: BPMP
+ * * Request Payload: N/A
+ * * Response Payload: @ref mrq_trace_iter_request
+ * @addtogroup Trace
+ * @{
+ */
+enum {
+	/** @brief (re)start the tracing now. Ignore older events */
+	TRACE_ITER_INIT = 0,
+	/** @brief clobber all events in the trace buffer */
+	TRACE_ITER_CLEAN = 1
+};
+
+/**
+ * @brief request with #MRQ_TRACE_ITER
+ */
+struct mrq_trace_iter_request {
+	/** @brief TRACE_ITER_INIT or TRACE_ITER_CLEAN */
+	uint32_t cmd;
+} __ABI_PACKED;
+
+/** @} */
+
+/*
+ *  4. Enumerations
+ */
+
+/*
+ *   4.1 CPU enumerations
+ *
+ * See <mach-t186/system-t186.h>
+ *
+ *   4.2 CPU Cluster enumerations
+ *
+ * See <mach-t186/system-t186.h>
+ *
+ *   4.3 System low power state enumerations
+ *
+ * See <mach-t186/system-t186.h>
+ */
+
+/*
+ *   4.4 Clock enumerations
+ *
+ * For clock enumerations, see <mach-t186/clk-t186.h>
+ */
+
+/*
+ *   4.5 Reset enumerations
+ *
+ * For reset enumerations, see <mach-t186/reset-t186.h>
+ */
+
+/*
+ *   4.6 Thermal sensor enumerations
+ *
+ * For thermal sensor enumerations, see <mach-t186/thermal-t186.h>
+ */
+
+/**
+ * @defgroup Error_Codes
+ * Negative values for mrq_response::err generally indicate some
+ * error. The ABI defines the following error codes. Negating these
+ * defines is an exercise left to the user.
+ * @{
+ */
+/** @brief No such file or directory */
+#define BPMP_ENOENT	2
+/** @brief No MRQ handler */
+#define BPMP_ENOHANDLER	3
+/** @brief I/O error */
+#define BPMP_EIO	5
+/** @brief Bad sub-MRQ command */
+#define BPMP_EBADCMD	6
+/** @brief Not enough memory */
+#define BPMP_ENOMEM	12
+/** @brief Permission denied */
+#define BPMP_EACCES	13
+/** @brief Bad address */
+#define BPMP_EFAULT	14
+/** @brief No such device */
+#define BPMP_ENODEV	19
+/** @brief Argument is a directory */
+#define BPMP_EISDIR	21
+/** @brief Invalid argument */
+#define BPMP_EINVAL	22
+/** @brief Timeout during operation */
+#define BPMP_ETIMEDOUT  23
+/** @brief Out of range */
+#define BPMP_ERANGE	34
+/** @} */
+/** @} */
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/cboot.h b/arch/arm/include/asm/arch-tegra/cboot.h
new file mode 100644
index 0000000..021c246
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/cboot.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 NVIDIA Corporation. All rights reserved.
+ */
+
+#ifndef _TEGRA_CBOOT_H_
+#define _TEGRA_CBOOT_H_
+
+#ifdef CONFIG_ARM64
+extern unsigned long cboot_boot_x0;
+
+void cboot_save_boot_params(unsigned long x0, unsigned long x1,
+			    unsigned long x2, unsigned long x3);
+int cboot_dram_init(void);
+int cboot_dram_init_banksize(void);
+ulong cboot_get_usable_ram_top(ulong total_size);
+int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN]);
+#else
+static inline void cboot_save_boot_params(unsigned long x0, unsigned long x1,
+					  unsigned long x2, unsigned long x3)
+{
+}
+
+static inline int cboot_dram_init(void)
+{
+	return -ENOSYS;
+}
+
+static inline int cboot_dram_init_banksize(void)
+{
+	return -ENOSYS;
+}
+
+static inline ulong cboot_get_usable_ram_top(ulong total_size)
+{
+	return 0;
+}
+
+static inline int cboot_get_ethaddr(const void *fdt, uint8_t mac[ETH_ALEN])
+{
+	return -ENOSYS;
+}
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
new file mode 100644
index 0000000..2359e14
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -0,0 +1,451 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010-2014
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_CLK_RST_H_
+#define _TEGRA_CLK_RST_H_
+
+/* PLL registers - there are several PLLs in the clock controller */
+struct clk_pll {
+	uint pll_base;		/* the control register */
+	/* pll_out[0] is output A control, pll_out[1] is output B control */
+	uint pll_out[2];
+	uint pll_misc;		/* other misc things */
+};
+
+/* PLL registers - there are several PLLs in the clock controller */
+struct clk_pll_simple {
+	uint pll_base;		/* the control register */
+	uint pll_misc;		/* other misc things */
+};
+
+struct clk_pllm {
+	uint pllm_base;		/* the control register */
+	uint pllm_out;		/* output control */
+	uint pllm_misc1;	/* misc1 */
+	uint pllm_misc2;	/* misc2 */
+};
+
+/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
+struct clk_set_clr {
+	uint set;
+	uint clr;
+};
+
+/*
+ * Most PLLs use the clk_pll structure, but some have a simpler two-member
+ * structure for which we use clk_pll_simple. The reason for this non-
+ * othogonal setup is not stated.
+ */
+enum {
+	TEGRA_CLK_PLLS		= 6,	/* Number of normal PLLs */
+	TEGRA_CLK_SIMPLE_PLLS	= 3,	/* Number of simple PLLs */
+	TEGRA_CLK_REGS		= 3,	/* Number of clock enable regs L/H/U */
+	TEGRA_CLK_SOURCES	= 64,	/* Number of ppl clock sources L/H/U */
+	TEGRA_CLK_REGS_VW	= 2,	/* Number of clock enable regs V/W */
+	TEGRA_CLK_SOURCES_VW	= 32,	/* Number of ppl clock sources V/W */
+	TEGRA_CLK_SOURCES_X	= 32,	/* Number of ppl clock sources X */
+	TEGRA_CLK_SOURCES_Y	= 18,	/* Number of ppl clock sources Y */
+};
+
+/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
+struct clk_rst_ctlr {
+	uint crc_rst_src;			/* _RST_SOURCE_0,0x00 */
+	uint crc_rst_dev[TEGRA_CLK_REGS];	/* _RST_DEVICES_L/H/U_0 */
+	uint crc_clk_out_enb[TEGRA_CLK_REGS];	/* _CLK_OUT_ENB_L/H/U_0 */
+	uint crc_reserved0;		/* reserved_0,		0x1C */
+	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0, 0x20 */
+	uint crc_super_cclk_div;	/* _SUPER_CCLK_DIVIDER_0,0x24 */
+	uint crc_sclk_brst_pol;		/* _SCLK_BURST_POLICY_0, 0x28 */
+	uint crc_super_sclk_div;	/* _SUPER_SCLK_DIVIDER_0,0x2C */
+	uint crc_clk_sys_rate;		/* _CLK_SYSTEM_RATE_0,	0x30 */
+	uint crc_prog_dly_clk;		/* _PROG_DLY_CLK_0,	0x34 */
+	uint crc_aud_sync_clk_rate;	/* _AUDIO_SYNC_CLK_RATE_0,0x38 */
+	uint crc_reserved1;		/* reserved_1,		0x3C */
+	uint crc_cop_clk_skip_plcy;	/* _COP_CLK_SKIP_POLICY_0,0x40 */
+	uint crc_clk_mask_arm;		/* _CLK_MASK_ARM_0,	0x44 */
+	uint crc_misc_clk_enb;		/* _MISC_CLK_ENB_0,	0x48 */
+	uint crc_clk_cpu_cmplx;		/* _CLK_CPU_CMPLX_0,	0x4C */
+	uint crc_osc_ctrl;		/* _OSC_CTRL_0,		0x50 */
+	uint crc_pll_lfsr;		/* _PLL_LFSR_0,		0x54 */
+	uint crc_osc_freq_det;		/* _OSC_FREQ_DET_0,	0x58 */
+	uint crc_osc_freq_det_stat;	/* _OSC_FREQ_DET_STATUS_0,0x5C */
+	uint crc_reserved2[8];		/* reserved_2[8],	0x60-7C */
+
+	struct clk_pll crc_pll[TEGRA_CLK_PLLS];	/* PLLs from 0x80 to 0xdc */
+
+	/* PLLs from 0xe0 to 0xf4    */
+	struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
+
+	uint crc_reserved10;		/* _reserved_10,	0xF8 */
+	uint crc_reserved11;		/* _reserved_11,	0xFC */
+
+	uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0...	0x100-1fc */
+
+	uint crc_reserved20[32];	/* _reserved_20,	0x200-27c */
+
+	uint crc_clk_out_enb_x;		/* _CLK_OUT_ENB_X_0,	0x280 */
+	uint crc_clk_enb_x_set;		/* _CLK_ENB_X_SET_0,	0x284 */
+	uint crc_clk_enb_x_clr;		/* _CLK_ENB_X_CLR_0,	0x288 */
+
+	uint crc_rst_devices_x;		/* _RST_DEVICES_X_0,	0x28c */
+	uint crc_rst_dev_x_set;		/* _RST_DEV_X_SET_0,	0x290 */
+	uint crc_rst_dev_x_clr;		/* _RST_DEV_X_CLR_0,	0x294 */
+
+	uint crc_clk_out_enb_y;		/* _CLK_OUT_ENB_Y_0,	0x298 */
+	uint crc_clk_enb_y_set;		/* _CLK_ENB_Y_SET_0,	0x29c */
+	uint crc_clk_enb_y_clr;		/* _CLK_ENB_Y_CLR_0,	0x2a0 */
+
+	uint crc_rst_devices_y;		/* _RST_DEVICES_Y_0,	0x2a4 */
+	uint crc_rst_dev_y_set;		/* _RST_DEV_Y_SET_0,	0x2a8 */
+	uint crc_rst_dev_y_clr;		/* _RST_DEV_Y_CLR_0,	0x2ac */
+
+	uint crc_reserved21[17];	/* _reserved_21,	0x2b0-2f0 */
+
+	uint crc_dfll_base;		/* _DFLL_BASE_0,	0x2f4 */
+
+	uint crc_reserved22[2];		/* _reserved_22,	0x2f8-2fc */
+
+	/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
+	struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
+
+	uint crc_reserved30[2];		/* _reserved_30,	0x318, 0x31c */
+
+	/* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
+	struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
+
+	uint crc_reserved31[2];		/* _reserved_31,	0x338, 0x33c */
+
+	uint crc_cpu_cmplx_set;		/* _RST_CPU_CMPLX_SET_0,    0x340 */
+	uint crc_cpu_cmplx_clr;		/* _RST_CPU_CMPLX_CLR_0,    0x344 */
+
+	/* Additional (T30) registers */
+	uint crc_clk_cpu_cmplx_set;	/* _CLK_CPU_CMPLX_SET_0,    0x348 */
+	uint crc_clk_cpu_cmplx_clr;	/* _CLK_CPU_CMPLX_SET_0,    0x34c */
+
+	uint crc_reserved32[2];		/* _reserved_32,      0x350,0x354 */
+
+	uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
+	uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
+	uint crc_cclkg_brst_pol;	/* _CCLKG_BURST_POLICY_0,   0x368 */
+	uint crc_super_cclkg_div;	/* _SUPER_CCLKG_DIVIDER_0,  0x36C */
+	uint crc_cclklp_brst_pol;	/* _CCLKLP_BURST_POLICY_0,  0x370 */
+	uint crc_super_cclkp_div;	/* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
+	uint crc_clk_cpug_cmplx;	/* _CLK_CPUG_CMPLX_0,       0x378 */
+	uint crc_clk_cpulp_cmplx;	/* _CLK_CPULP_CMPLX_0,      0x37C */
+	uint crc_cpu_softrst_ctrl;	/* _CPU_SOFTRST_CTRL_0,     0x380 */
+	uint crc_cpu_softrst_ctrl1;	/* _CPU_SOFTRST_CTRL1_0,    0x384 */
+	uint crc_cpu_softrst_ctrl2;	/* _CPU_SOFTRST_CTRL2_0,    0x388 */
+	uint crc_reserved33[9];		/* _reserved_33,        0x38c-3ac */
+	uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW];	/* 0x3B0-0x42C */
+	/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
+	struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
+	/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
+	struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
+	/* Additional (T114+) registers */
+	uint crc_rst_cpug_cmplx_set;	/* _RST_CPUG_CMPLX_SET_0,  0x450 */
+	uint crc_rst_cpug_cmplx_clr;	/* _RST_CPUG_CMPLX_CLR_0,  0x454 */
+	uint crc_rst_cpulp_cmplx_set;	/* _RST_CPULP_CMPLX_SET_0, 0x458 */
+	uint crc_rst_cpulp_cmplx_clr;	/* _RST_CPULP_CMPLX_CLR_0, 0x45C */
+	uint crc_clk_cpug_cmplx_set;	/* _CLK_CPUG_CMPLX_SET_0,  0x460 */
+	uint crc_clk_cpug_cmplx_clr;	/* _CLK_CPUG_CMPLX_CLR_0,  0x464 */
+	uint crc_clk_cpulp_cmplx_set;	/* _CLK_CPULP_CMPLX_SET_0, 0x468 */
+	uint crc_clk_cpulp_cmplx_clr;	/* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
+	uint crc_cpu_cmplx_status;	/* _CPU_CMPLX_STATUS_0,    0x470 */
+	uint crc_reserved40[1];		/* _reserved_40,        0x474 */
+	uint crc_intstatus;		/* __INTSTATUS_0,       0x478 */
+	uint crc_intmask;		/* __INTMASK_0,         0x47C */
+	uint crc_utmip_pll_cfg0;	/* _UTMIP_PLL_CFG0_0,	0x480 */
+	uint crc_utmip_pll_cfg1;	/* _UTMIP_PLL_CFG1_0,	0x484 */
+	uint crc_utmip_pll_cfg2;	/* _UTMIP_PLL_CFG2_0,	0x488 */
+
+	uint crc_plle_aux;		/* _PLLE_AUX_0,		0x48C */
+	uint crc_sata_pll_cfg0;		/* _SATA_PLL_CFG0_0,	0x490 */
+	uint crc_sata_pll_cfg1;		/* _SATA_PLL_CFG1_0,	0x494 */
+	uint crc_pcie_pll_cfg0;		/* _PCIE_PLL_CFG0_0,	0x498 */
+
+	uint crc_prog_audio_dly_clk;	/* _PROG_AUDIO_DLY_CLK_0, 0x49C */
+	uint crc_audio_sync_clk_i2s0;	/* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
+	uint crc_audio_sync_clk_i2s1;	/* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
+	uint crc_audio_sync_clk_i2s2;	/* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
+	uint crc_audio_sync_clk_i2s3;	/* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
+	uint crc_audio_sync_clk_i2s4;	/* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
+	uint crc_audio_sync_clk_spdif;	/* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
+
+	uint crc_plld2_base;		/* _PLLD2_BASE_0, 0x4B8 */
+	uint crc_plld2_misc;		/* _PLLD2_MISC_0, 0x4BC */
+	uint crc_utmip_pll_cfg3;	/* _UTMIP_PLL_CFG3_0, 0x4C0 */
+	uint crc_pllrefe_base;		/* _PLLREFE_BASE_0, 0x4C4 */
+	uint crc_pllrefe_misc;		/* _PLLREFE_MISC_0, 0x4C8 */
+	uint crs_reserved_50[7];	/* _reserved_50, 0x4CC-0x4E4 */
+	uint crc_pllc2_base;		/* _PLLC2_BASE_0, 0x4E8 */
+	uint crc_pllc2_misc0;		/* _PLLC2_MISC_0_0, 0x4EC */
+	uint crc_pllc2_misc1;		/* _PLLC2_MISC_1_0, 0x4F0 */
+	uint crc_pllc2_misc2;		/* _PLLC2_MISC_2_0, 0x4F4 */
+	uint crc_pllc2_misc3;		/* _PLLC2_MISC_3_0, 0x4F8 */
+	uint crc_pllc3_base;		/* _PLLC3_BASE_0, 0x4FC */
+	uint crc_pllc3_misc0;		/* _PLLC3_MISC_0_0, 0x500 */
+	uint crc_pllc3_misc1;		/* _PLLC3_MISC_1_0, 0x504 */
+	uint crc_pllc3_misc2;		/* _PLLC3_MISC_2_0, 0x508 */
+	uint crc_pllc3_misc3;		/* _PLLC3_MISC_3_0, 0x50C */
+	uint crc_pllx_misc1;		/* _PLLX_MISC_1_0, 0x510 */
+	uint crc_pllx_misc2;		/* _PLLX_MISC_2_0, 0x514 */
+	uint crc_pllx_misc3;		/* _PLLX_MISC_3_0, 0x518 */
+	uint crc_xusbio_pll_cfg0;	/* _XUSBIO_PLL_CFG0_0, 0x51C */
+	uint crc_xusbio_pll_cfg1;	/* _XUSBIO_PLL_CFG0_1, 0x520 */
+	uint crc_plle_aux1;		/* _PLLE_AUX1_0, 0x524 */
+	uint crc_pllp_reshift;		/* _PLLP_RESHIFT_0, 0x528 */
+	uint crc_utmipll_hw_pwrdn_cfg0;	/* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
+	uint crc_pllu_hw_pwrdn_cfg0;	/* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
+	uint crc_xusb_pll_cfg0;		/* _XUSB_PLL_CFG0_0, 0x534 */
+	uint crc_reserved51[1];		/* _reserved_51, 0x538 */
+	uint crc_clk_cpu_misc;		/* _CLK_CPU_MISC_0, 0x53C */
+	uint crc_clk_cpug_misc;		/* _CLK_CPUG_MISC_0, 0x540 */
+	uint crc_clk_cpulp_misc;	/* _CLK_CPULP_MISC_0, 0x544 */
+	uint crc_pllx_hw_ctrl_cfg;	/* _PLLX_HW_CTRL_CFG_0, 0x548 */
+	uint crc_pllx_sw_ramp_cfg;	/* _PLLX_SW_RAMP_CFG_0, 0x54C */
+	uint crc_pllx_hw_ctrl_status;	/* _PLLX_HW_CTRL_STATUS_0, 0x550 */
+	uint crc_reserved52[1];		/* _reserved_52, 0x554 */
+	uint crc_super_gr3d_clk_div;	/* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
+	uint crc_spare_reg0;		/* _SPARE_REG0_0, 0x55C */
+	u32 _rsv32[4];                  /*                    0x560-0x56c */
+	u32 crc_plld2_ss_cfg;		/* _PLLD2_SS_CFG            0x570 */
+	u32 _rsv32_1[7];		/*                      0x574-58c */
+	struct clk_pll_simple plldp;	/* _PLLDP_BASE, 0x590 _PLLDP_MISC */
+	u32 crc_plldp_ss_cfg;		/* _PLLDP_SS_CFG, 0x598 */
+
+	/* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
+	uint _rsrv32_2[25];			/* _0x59C - 0x5FC */
+	uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
+
+	/* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
+	uint crc_reserved61[5];	/* _reserved_61, 0x680 - 0x690 */
+	/*
+	 * NOTE: PLLA1 regs are in the middle of this Y region. Break this in
+	 * two later if PLLA1 is needed, but for now this is cleaner.
+	 */
+	uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
+};
+
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
+#define CPU3_CLK_STP_SHIFT	11
+#define CPU2_CLK_STP_SHIFT	10
+#define CPU1_CLK_STP_SHIFT	9
+#define CPU0_CLK_STP_SHIFT	8
+#define CPU0_CLK_STP_MASK	(1U << CPU0_CLK_STP_SHIFT)
+
+/* CLK_RST_CONTROLLER_PLLx_BASE_0 */
+#define PLL_BYPASS_SHIFT	31
+#define PLL_BYPASS_MASK		(1U << PLL_BYPASS_SHIFT)
+
+#define PLL_ENABLE_SHIFT	30
+#define PLL_ENABLE_MASK		(1U << PLL_ENABLE_SHIFT)
+
+#define PLL_BASE_OVRRIDE_MASK	(1U << 28)
+
+#define PLL_LOCK_SHIFT		27
+#define PLL_LOCK_MASK		(1U << PLL_LOCK_SHIFT)
+
+/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
+#define PLL_OUT_RSTN		(1 << 0)
+#define PLL_OUT_CLKEN		(1 << 1)
+#define PLL_OUT_OVRRIDE		(1 << 2)
+
+#define PLL_OUT_RATIO_SHIFT	8
+#define PLL_OUT_RATIO_MASK	(0xffU << PLL_OUT_RATIO_SHIFT)
+
+/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
+#define PLL_DCCON_SHIFT		20
+#define PLL_DCCON_MASK		(1U << PLL_DCCON_SHIFT)
+
+#define PLLP_OUT1_OVR		(1 << 2)
+#define PLLP_OUT2_OVR		(1 << 18)
+#define PLLP_OUT3_OVR		(1 << 2)
+#define PLLP_OUT4_OVR		(1 << 18)
+#define PLLP_OUT1_RATIO		8
+#define PLLP_OUT2_RATIO		24
+#define PLLP_OUT3_RATIO		8
+#define PLLP_OUT4_RATIO		24
+
+enum {
+	IN_408_OUT_204_DIVISOR = 2,
+	IN_408_OUT_102_DIVISOR = 6,
+	IN_408_OUT_48_DIVISOR = 15,
+	IN_408_OUT_9_6_DIVISOR = 83,
+};
+
+#define PLLP_OUT1_RSTN_DIS	(1 << 0)
+#define PLLP_OUT1_RSTN_EN	(0 << 0)
+#define PLLP_OUT1_CLKEN		(1 << 1)
+#define PLLP_OUT2_RSTN_DIS	(1 << 16)
+#define PLLP_OUT2_RSTN_EN	(0 << 16)
+#define PLLP_OUT2_CLKEN		(1 << 17)
+
+#define PLLP_OUT3_RSTN_DIS	(1 << 0)
+#define PLLP_OUT3_RSTN_EN	(0 << 0)
+#define PLLP_OUT3_CLKEN		(1 << 1)
+#define PLLP_OUT4_RSTN_DIS	(1 << 16)
+#define PLLP_OUT4_RSTN_EN	(0 << 16)
+#define PLLP_OUT4_CLKEN		(1 << 17)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
+#define PLLU_POWERDOWN		(1 << 16)
+#define PLL_ENABLE_POWERDOWN	(1 << 14)
+#define PLL_ACTIVE_POWERDOWN	(1 << 12)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN		(1 << 4)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN		(1 << 2)
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN		(1 << 0)
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
+#define OSC_XOE_SHIFT			0
+#define OSC_XOE_MASK			(1 << OSC_XOE_SHIFT)
+#define OSC_XOE_ENABLE			(1 << OSC_XOE_SHIFT)
+#define OSC_XOBP_SHIFT			1
+#define OSC_XOBP_MASK			(1U << OSC_XOBP_SHIFT)
+#define OSC_XOFS_SHIFT			4
+#define OSC_XOFS_MASK			(0x3F << OSC_XOFS_SHIFT)
+#define OSC_DRIVE_STRENGTH		7
+
+/*
+ * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
+ * but can be 16. We could use knowledge we have to restrict the mask in
+ * the 8-bit cases (the divider_bits value returned by
+ * get_periph_clock_source()) but it does not seem worth it since the code
+ * already checks the ranges of values it is writing, in clk_get_divider().
+ */
+#define OUT_CLK_DIVISOR_SHIFT	0
+#define OUT_CLK_DIVISOR_MASK	(0xffff << OUT_CLK_DIVISOR_SHIFT)
+
+#define OUT_CLK_SOURCE_31_30_SHIFT	30
+#define OUT_CLK_SOURCE_31_30_MASK	(3U << OUT_CLK_SOURCE_31_30_SHIFT)
+
+#define OUT_CLK_SOURCE_31_29_SHIFT	29
+#define OUT_CLK_SOURCE_31_29_MASK	(7U << OUT_CLK_SOURCE_31_29_SHIFT)
+
+/* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
+#define OUT_CLK_SOURCE_31_28_SHIFT	28
+#define OUT_CLK_SOURCE_31_28_MASK	(15U << OUT_CLK_SOURCE_31_28_SHIFT)
+
+/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
+#define SCLK_SYS_STATE_SHIFT    28U
+#define SCLK_SYS_STATE_MASK     (15U << SCLK_SYS_STATE_SHIFT)
+enum {
+	SCLK_SYS_STATE_STDBY,
+	SCLK_SYS_STATE_IDLE,
+	SCLK_SYS_STATE_RUN,
+	SCLK_SYS_STATE_IRQ = 4U,
+	SCLK_SYS_STATE_FIQ = 8U,
+};
+#define SCLK_COP_FIQ_MASK       (1 << 27)
+#define SCLK_CPU_FIQ_MASK       (1 << 26)
+#define SCLK_COP_IRQ_MASK       (1 << 25)
+#define SCLK_CPU_IRQ_MASK       (1 << 24)
+
+#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT		12
+#define SCLK_SWAKEUP_FIQ_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT		8
+#define SCLK_SWAKEUP_IRQ_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT		4
+#define SCLK_SWAKEUP_RUN_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT		0
+
+#define SCLK_SWAKEUP_IDLE_SOURCE_MASK		\
+		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+enum {
+	SCLK_SOURCE_CLKM,
+	SCLK_SOURCE_PLLC_OUT1,
+	SCLK_SOURCE_PLLP_OUT4,
+	SCLK_SOURCE_PLLP_OUT3,
+	SCLK_SOURCE_PLLP_OUT2,
+	SCLK_SOURCE_CLKD,
+	SCLK_SOURCE_CLKS,
+	SCLK_SOURCE_PLLM_OUT1,
+};
+#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1    (7 << 12)
+#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1    (7 << 8)
+#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1    (7 << 4)
+#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1   (7 << 0)
+
+/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
+#define SUPER_SCLK_ENB_SHIFT		31U
+#define SUPER_SCLK_ENB_MASK		(1U << 31)
+#define SUPER_SCLK_DIVIDEND_SHIFT	8
+#define SUPER_SCLK_DIVIDEND_MASK	(0xff << SUPER_SCLK_DIVIDEND_SHIFT)
+#define SUPER_SCLK_DIVISOR_SHIFT	0
+#define SUPER_SCLK_DIVISOR_MASK		(0xff << SUPER_SCLK_DIVISOR_SHIFT)
+
+/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
+#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
+#define CLK_SYS_RATE_HCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
+#define CLK_SYS_RATE_AHB_RATE_SHIFT     4
+#define CLK_SYS_RATE_AHB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
+#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
+#define CLK_SYS_RATE_PCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
+#define CLK_SYS_RATE_APB_RATE_SHIFT     0
+#define CLK_SYS_RATE_APB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
+
+/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */
+#define CLR_CPURESET0			(1 << 0)
+#define CLR_CPURESET1			(1 << 1)
+#define CLR_CPURESET2			(1 << 2)
+#define CLR_CPURESET3			(1 << 3)
+#define CLR_DBGRESET0			(1 << 12)
+#define CLR_DBGRESET1			(1 << 13)
+#define CLR_DBGRESET2			(1 << 14)
+#define CLR_DBGRESET3			(1 << 15)
+#define CLR_CORERESET0			(1 << 16)
+#define CLR_CORERESET1			(1 << 17)
+#define CLR_CORERESET2			(1 << 18)
+#define CLR_CORERESET3			(1 << 19)
+#define CLR_CXRESET0			(1 << 20)
+#define CLR_CXRESET1			(1 << 21)
+#define CLR_CXRESET2			(1 << 22)
+#define CLR_CXRESET3			(1 << 23)
+#define CLR_L2RESET			(1 << 24)
+#define CLR_NONCPURESET			(1 << 29)
+#define CLR_PRESETDBG			(1 << 30)
+
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */
+#define CLR_CPU0_CLK_STP		(1 << 8)
+#define CLR_CPU1_CLK_STP		(1 << 9)
+#define CLR_CPU2_CLK_STP		(1 << 10)
+#define CLR_CPU3_CLK_STP		(1 << 11)
+
+/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
+#define MSELECT_CLK_SRC_PLLP_OUT0	(0 << 29)
+
+/* CRC_CLK_ENB_V_SET_0 0x440 */
+#define SET_CLK_ENB_CPUG_ENABLE		(1 << 0)
+#define SET_CLK_ENB_CPULP_ENABLE	(1 << 1)
+#define SET_CLK_ENB_MSELECT_ENABLE	(1 << 3)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
+#define PLL_ACTIVE_POWERDOWN		(1 << 12)
+#define PLL_ENABLE_POWERDOWN		(1 << 14)
+#define PLLU_POWERDOWN			(1 << 16)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN	(1 << 0)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN	(1 << 2)
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN	(1 << 4)
+
+/* CLK_RST_CONTROLLER_PLLX_MISC_3 */
+#define PLLX_IDDQ_SHIFT			3
+#define PLLX_IDDQ_MASK			(1U << PLLX_IDDQ_SHIFT)
+
+/* CLK_RST_PLLDP_SS_CFG */
+#define PLLDP_SS_CFG_CLAMP		(1 << 22)
+#define PLLDP_SS_CFG_UNDOCUMENTED	(1 << 24)
+#define PLLDP_SS_CFG_DITHER		(1 << 28)
+
+/* CLK_RST_PLLD_MISC */
+#define PLLD_CLKENABLE			30
+
+#endif	/* _TEGRA_CLK_RST_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
new file mode 100644
index 0000000..8aa90d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -0,0 +1,421 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+/* Tegra clock control functions */
+
+#ifndef _TEGRA_CLOCK_H_
+#define _TEGRA_CLOCK_H_
+
+/* Set of oscillator frequencies supported in the internal API. */
+enum clock_osc_freq {
+	/* All in MHz, so 13_0 is 13.0MHz */
+	CLOCK_OSC_FREQ_13_0,
+	CLOCK_OSC_FREQ_19_2,
+	CLOCK_OSC_FREQ_12_0,
+	CLOCK_OSC_FREQ_26_0,
+	CLOCK_OSC_FREQ_38_4,
+	CLOCK_OSC_FREQ_48_0,
+
+	CLOCK_OSC_FREQ_COUNT,
+};
+
+/*
+ * Note that no Tegra clock register actually uses all of bits 31:28 as
+ * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
+ * those cases, nothing is stored in the bits about the mux field, so it's
+ * safe to pretend that the mux field extends all the way to the end of the
+ * register. As such, the U-Boot clock driver is currently a bit lazy, and
+ * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
+ * them all together and pretends they're all 31:28.
+ */
+enum {
+	MASK_BITS_31_30,
+	MASK_BITS_31_29,
+	MASK_BITS_31_28,
+};
+
+#include <asm/arch/clock-tables.h>
+/* PLL stabilization delay in usec */
+#define CLOCK_PLL_STABLE_DELAY_US 300
+
+/* return the current oscillator clock frequency */
+enum clock_osc_freq clock_get_osc_freq(void);
+
+/* return the clk_m frequency */
+unsigned int clk_m_get_rate(unsigned int parent_rate);
+
+/**
+ * Start PLL using the provided configuration parameters.
+ *
+ * @param id	clock id
+ * @param divm	input divider
+ * @param divn	feedback divider
+ * @param divp	post divider 2^n
+ * @param cpcon	charge pump setup control
+ * @param lfcon	loop filter setup control
+ *
+ * @returns monotonic time in us that the PLL will be stable
+ */
+unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
+		u32 divp, u32 cpcon, u32 lfcon);
+
+/**
+ * Set PLL output frequency
+ *
+ * @param clkid	clock id
+ * @param pllout	pll output id
+ * @param rate		desired output rate
+ *
+ * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
+ */
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
+		unsigned rate);
+
+/**
+ * Read low-level parameters of a PLL.
+ *
+ * @param id	clock id to read (note: USB is not supported)
+ * @param divm	returns input divider
+ * @param divn	returns feedback divider
+ * @param divp	returns post divider 2^n
+ * @param cpcon	returns charge pump setup control
+ * @param lfcon	returns loop filter setup control
+ *
+ * @returns 0 if ok, -1 on error (invalid clock id)
+ */
+int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
+		u32 *divp, u32 *cpcon, u32 *lfcon);
+
+/*
+ * Enable a clock
+ *
+ * @param id	clock id
+ */
+void clock_enable(enum periph_id clkid);
+
+/*
+ * Disable a clock
+ *
+ * @param id	clock id
+ */
+void clock_disable(enum periph_id clkid);
+
+/*
+ * Set whether a clock is enabled or disabled.
+ *
+ * @param id		clock id
+ * @param enable	1 to enable, 0 to disable
+ */
+void clock_set_enable(enum periph_id clkid, int enable);
+
+/**
+ * Reset a peripheral. This puts it in reset, waits for a delay, then takes
+ * it out of reset and waits for th delay again.
+ *
+ * @param periph_id	peripheral to reset
+ * @param us_delay	time to delay in microseconds
+ */
+void reset_periph(enum periph_id periph_id, int us_delay);
+
+/**
+ * Put a peripheral into or out of reset.
+ *
+ * @param periph_id	peripheral to reset
+ * @param enable	1 to put into reset, 0 to take out of reset
+ */
+void reset_set_enable(enum periph_id periph_id, int enable);
+
+
+/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
+enum crc_reset_id {
+	/* Things we can hold in reset for each CPU */
+	crc_rst_cpu = 1,
+	crc_rst_de = 1 << 4,	/* What is de? */
+	crc_rst_watchdog = 1 << 8,
+	crc_rst_debug = 1 << 12,
+};
+
+/**
+ * Put parts of the CPU complex into or out of reset.\
+ *
+ * @param cpu		cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
+ * @param which		which parts of the complex to affect (OR of crc_reset_id)
+ * @param reset		1 to assert reset, 0 to de-assert
+ */
+void reset_cmplx_set_enable(int cpu, int which, int reset);
+
+/**
+ * Set the source for a peripheral clock. This plus the divisor sets the
+ * clock rate. You need to look up the datasheet to see the meaning of the
+ * source parameter as it changes for each peripheral.
+ *
+ * Warning: This function is only for use pre-relocation. Please use
+ * clock_start_periph_pll() instead.
+ *
+ * @param periph_id	peripheral to adjust
+ * @param source	source clock (0, 1, 2 or 3)
+ */
+void clock_ll_set_source(enum periph_id periph_id, unsigned source);
+
+/**
+ * This function is similar to clock_ll_set_source() except that it can be
+ * used for clocks with more than 2 mux bits.
+ *
+ * @param periph_id	peripheral to adjust
+ * @param mux_bits	number of mux bits for the clock
+ * @param source	source clock (0-15 depending on mux_bits)
+ */
+int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
+			     unsigned source);
+
+/**
+ * Set the source and divisor for a peripheral clock. This sets the
+ * clock rate. You need to look up the datasheet to see the meaning of the
+ * source parameter as it changes for each peripheral.
+ *
+ * Warning: This function is only for use pre-relocation. Please use
+ * clock_start_periph_pll() instead.
+ *
+ * @param periph_id	peripheral to adjust
+ * @param source	source clock (0, 1, 2 or 3)
+ * @param divisor	divisor value to use
+ */
+void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
+		unsigned divisor);
+
+/**
+ * Returns the current parent clock ID of a given peripheral. This can be
+ * useful in order to call clock_*_periph_*() from generic code that has no
+ * specific knowledge of system-level clock tree structure.
+ *
+ * @param periph_id	peripheral to query
+ * @return clock ID of the peripheral's current parent clock
+ */
+enum clock_id clock_get_periph_parent(enum periph_id periph_id);
+
+/**
+ * Start a peripheral PLL clock at the given rate. This also resets the
+ * peripheral.
+ *
+ * @param periph_id	peripheral to start
+ * @param parent	PLL id of required parent clock
+ * @param rate		Required clock rate in Hz
+ * @return rate selected in Hz, or -1U if something went wrong
+ */
+unsigned clock_start_periph_pll(enum periph_id periph_id,
+		enum clock_id parent, unsigned rate);
+
+/**
+ * Returns the rate of a peripheral clock in Hz. Since the caller almost
+ * certainly knows the parent clock (having just set it) we require that
+ * this be passed in so we don't need to work it out.
+ *
+ * @param periph_id	peripheral to start
+ * @param parent	PLL id of parent clock (used to calculate rate, you
+ *			must know this!)
+ * @return clock rate of peripheral in Hz
+ */
+unsigned long clock_get_periph_rate(enum periph_id periph_id,
+		enum clock_id parent);
+
+/**
+ * Adjust peripheral PLL clock to the given rate. This does not reset the
+ * peripheral. If a second stage divisor is not available, pass NULL for
+ * extra_div. If it is available, then this parameter will return the
+ * divisor selected (which will be a power of 2 from 1 to 256).
+ *
+ * @param periph_id	peripheral to start
+ * @param parent	PLL id of required parent clock
+ * @param rate		Required clock rate in Hz
+ * @param extra_div	value for the second-stage divisor (NULL if one is
+			not available)
+ * @return rate selected in Hz, or -1U if something went wrong
+ */
+unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
+		enum clock_id parent, unsigned rate, int *extra_div);
+
+/**
+ * Returns the clock rate of a specified clock, in Hz.
+ *
+ * @param parent	PLL id of clock to check
+ * @return rate of clock in Hz
+ */
+unsigned clock_get_rate(enum clock_id clkid);
+
+/**
+ * Start up a UART using low-level calls
+ *
+ * Prior to relocation clock_start_periph_pll() cannot be called. This
+ * function provides a way to set up a UART using low-level calls which
+ * do not require BSS.
+ *
+ * @param periph_id	Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
+ */
+void clock_ll_start_uart(enum periph_id periph_id);
+
+/**
+ * Decode a peripheral ID from a device tree node.
+ *
+ * This works by looking up the peripheral's 'clocks' node and reading out
+ * the second cell, which is the clock number / peripheral ID.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Node to look at
+ * @return peripheral ID, or PERIPH_ID_NONE if none
+ */
+int clock_decode_periph_id(struct udevice *dev);
+
+/**
+ * Checks if the oscillator bypass is enabled (XOBP bit)
+ *
+ * @return 1 if bypass is enabled, 0 if not
+ */
+int clock_get_osc_bypass(void);
+
+/*
+ * Checks that clocks are valid and prints a warning if not
+ *
+ * @return 0 if ok, -1 on error
+ */
+int clock_verify(void);
+
+/* Initialize the clocks */
+void clock_init(void);
+
+/* Initialize the PLLs */
+void clock_early_init(void);
+
+/* @return true if hardware indicates that clock_early_init() was called */
+bool clock_early_init_done(void);
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id);
+
+/* Returns a pointer to the given 'simple' PLL */
+struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
+
+/*
+ * Given a peripheral ID, determine where the mux bits are in the peripheral
+ * clock's register, the number of divider bits the clock has, and the SoC-
+ * specific clock type.
+ *
+ * This is an internal API between the core Tegra clock code and the SoC-
+ * specific clock code.
+ *
+ * @param periph_id     peripheral to query
+ * @param mux_bits      Set to number of bits in mux register
+ * @param divider_bits  Set to the relevant MASK_BITS_* value
+ * @param type          Set to the SoC-specific clock type
+ * @return 0 on success, -1 on error
+ */
+int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
+			  int *divider_bits, int *type);
+
+/*
+ * Given a peripheral ID and clock source mux value, determine the clock_id
+ * of that peripheral's parent.
+ *
+ * This is an internal API between the core Tegra clock code and the SoC-
+ * specific clock code.
+ *
+ * @param periph_id     peripheral to query
+ * @param source        raw clock source mux value
+ * @return the CLOCK_ID_* value @source represents
+ */
+enum clock_id get_periph_clock_id(enum periph_id periph_id, int source);
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id     peripheral to start
+ * @param source        PLL id of required parent clock
+ * @param mux_bits      Set to number of bits in mux register: 2 or 4
+ * @param divider_bits  Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+		enum clock_id parent, int *mux_bits, int *divider_bits);
+
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id        Clock ID according to tegra30 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id);
+
+/**
+ * Set the output frequency you want for each PLL clock.
+ * PLL output frequencies are programmed by setting their N, M and P values.
+ * The governing equations are:
+ *     VCO = (Fi / m) * n, Fo = VCO / (2^p)
+ *     where Fo is the output frequency from the PLL.
+ * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
+ *     216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
+ * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
+ *
+ * @param n PLL feedback divider(DIVN)
+ * @param m PLL input divider(DIVN)
+ * @param p post divider(DIVP)
+ * @param cpcon base PLL charge pump(CPCON)
+ * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
+ *              be overridden), 1 if PLL is already correct
+ */
+int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
+
+/* return 1 if a peripheral ID is in range */
+#define clock_type_id_isvalid(id) ((id) >= 0 && \
+		(id) < CLOCK_TYPE_COUNT)
+
+/* return 1 if a periphc_internal_id is in range */
+#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
+		(id) < PERIPHC_COUNT)
+
+/* SoC-specific TSC init */
+void arch_timer_init(void);
+
+void tegra30_set_up_pllp(void);
+
+/* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
+#define CLOCK_ID_PLL_COUNT	(CLOCK_ID_COUNT - 3)
+
+struct clk_pll_info {
+	u32	m_shift:5;	/* DIVM_SHIFT */
+	u32	n_shift:5;	/* DIVN_SHIFT */
+	u32	p_shift:5;	/* DIVP_SHIFT */
+	u32	kcp_shift:5;	/* KCP/cpcon SHIFT */
+	u32	kvco_shift:5;	/* KVCO/lfcon SHIFT */
+	u32	lock_ena:6;	/* LOCK_ENABLE/EN_LOCKDET shift */
+	u32	rsvd:1;
+	u32	m_mask:10;	/* DIVM_MASK */
+	u32	n_mask:12;	/* DIVN_MASK */
+	u32	p_mask:10;	/* DIVP_MASK or VCO_MASK */
+	u32	kcp_mask:10;	/* KCP/CPCON MASK */
+	u32	kvco_mask:10;	/* KVCO/LFCON MASK */
+	u32	lock_det:6;	/* LOCK_DETECT/LOCKED shift */
+	u32	rsvd2:6;
+};
+extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
+
+struct periph_clk_init {
+	enum periph_id periph_id;
+	enum clock_id parent_clock_id;
+};
+extern struct periph_clk_init periph_clk_init_table[];
+
+/**
+ * Enable output clock for external peripherals
+ *
+ * @param clk_id	Clock ID to output (1, 2 or 3)
+ * @return 0 if OK. -ve on error
+ */
+int clock_external_output(int clk_id);
+
+#endif  /* _TEGRA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h
new file mode 100644
index 0000000..59347dd
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -0,0 +1,568 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DC_H
+#define __ASM_ARCH_TEGRA_DC_H
+
+/* Register definitions for the Tegra display controller */
+
+/* CMD register 0x000 ~ 0x43 */
+struct dc_cmd_reg {
+	/* Address 0x000 ~ 0x002 */
+	uint gen_incr_syncpt;		/* _CMD_GENERAL_INCR_SYNCPT_0 */
+	uint gen_incr_syncpt_ctrl;	/* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
+	uint gen_incr_syncpt_err;	/* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
+
+	uint reserved0[5];		/* reserved_0[5] */
+
+	/* Address 0x008 ~ 0x00a */
+	uint win_a_incr_syncpt;		/* _CMD_WIN_A_INCR_SYNCPT_0 */
+	uint win_a_incr_syncpt_ctrl;	/* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
+	uint win_a_incr_syncpt_err;	/* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
+
+	uint reserved1[5];		/* reserved_1[5] */
+
+	/* Address 0x010 ~ 0x012 */
+	uint win_b_incr_syncpt;		/* _CMD_WIN_B_INCR_SYNCPT_0 */
+	uint win_b_incr_syncpt_ctrl;	/* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
+	uint win_b_incr_syncpt_err;	/* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */
+
+	uint reserved2[5];		/* reserved_2[5] */
+
+	/* Address 0x018 ~ 0x01a */
+	uint win_c_incr_syncpt;		/* _CMD_WIN_C_INCR_SYNCPT_0 */
+	uint win_c_incr_syncpt_ctrl;	/* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */
+	uint win_c_incr_syncpt_err;	/* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */
+
+	uint reserved3[13];		/* reserved_3[13] */
+
+	/* Address 0x028 */
+	uint cont_syncpt_vsync;		/* _CMD_CONT_SYNCPT_VSYNC_0 */
+
+	uint reserved4[7];		/* reserved_4[7] */
+
+	/* Address 0x030 ~ 0x033 */
+	uint ctxsw;			/* _CMD_CTXSW_0 */
+	uint disp_cmd_opt0;		/* _CMD_DISPLAY_COMMAND_OPTION0_0 */
+	uint disp_cmd;			/* _CMD_DISPLAY_COMMAND_0 */
+	uint sig_raise;			/* _CMD_SIGNAL_RAISE_0 */
+
+	uint reserved5[2];		/* reserved_0[2] */
+
+	/* Address 0x036 ~ 0x03e */
+	uint disp_pow_ctrl;		/* _CMD_DISPLAY_POWER_CONTROL_0 */
+	uint int_stat;			/* _CMD_INT_STATUS_0 */
+	uint int_mask;			/* _CMD_INT_MASK_0 */
+	uint int_enb;			/* _CMD_INT_ENABLE_0 */
+	uint int_type;			/* _CMD_INT_TYPE_0 */
+	uint int_polarity;		/* _CMD_INT_POLARITY_0 */
+	uint sig_raise1;		/* _CMD_SIGNAL_RAISE1_0 */
+	uint sig_raise2;		/* _CMD_SIGNAL_RAISE2_0 */
+	uint sig_raise3;		/* _CMD_SIGNAL_RAISE3_0 */
+
+	uint reserved6;			/* reserved_6 */
+
+	/* Address 0x040 ~ 0x043 */
+	uint state_access;		/* _CMD_STATE_ACCESS_0 */
+	uint state_ctrl;		/* _CMD_STATE_CONTROL_0 */
+	uint disp_win_header;		/* _CMD_DISPLAY_WINDOW_HEADER_0 */
+	uint reg_act_ctrl;		/* _CMD_REG_ACT_CONTROL_0 */
+};
+
+enum {
+	PIN_REG_COUNT		= 4,
+	PIN_OUTPUT_SEL_COUNT	= 7,
+};
+
+/* COM register 0x300 ~ 0x329 */
+struct dc_com_reg {
+	/* Address 0x300 ~ 0x301 */
+	uint crc_ctrl;			/* _COM_CRC_CONTROL_0 */
+	uint crc_checksum;		/* _COM_CRC_CHECKSUM_0 */
+
+	/* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */
+	uint pin_output_enb[PIN_REG_COUNT];
+
+	/* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */
+	uint pin_output_polarity[PIN_REG_COUNT];
+
+	/* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */
+	uint pin_output_data[PIN_REG_COUNT];
+
+	/* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */
+	uint pin_input_enb[PIN_REG_COUNT];
+
+	/* Address 0x312 ~ 0x313 */
+	uint pin_input_data0;		/* _COM_PIN_INPUT_DATA0_0 */
+	uint pin_input_data1;		/* _COM_PIN_INPUT_DATA1_0 */
+
+	/* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */
+	uint pin_output_sel[PIN_OUTPUT_SEL_COUNT];
+
+	/* Address 0x31b ~ 0x329 */
+	uint pin_misc_ctrl;		/* _COM_PIN_MISC_CONTROL_0 */
+	uint pm0_ctrl;			/* _COM_PM0_CONTROL_0 */
+	uint pm0_duty_cycle;		/* _COM_PM0_DUTY_CYCLE_0 */
+	uint pm1_ctrl;			/* _COM_PM1_CONTROL_0 */
+	uint pm1_duty_cycle;		/* _COM_PM1_DUTY_CYCLE_0 */
+	uint spi_ctrl;			/* _COM_SPI_CONTROL_0 */
+	uint spi_start_byte;		/* _COM_SPI_START_BYTE_0 */
+	uint hspi_wr_data_ab;		/* _COM_HSPI_WRITE_DATA_AB_0 */
+	uint hspi_wr_data_cd;		/* _COM_HSPI_WRITE_DATA_CD */
+	uint hspi_cs_dc;		/* _COM_HSPI_CS_DC_0 */
+	uint scratch_reg_a;		/* _COM_SCRATCH_REGISTER_A_0 */
+	uint scratch_reg_b;		/* _COM_SCRATCH_REGISTER_B_0 */
+	uint gpio_ctrl;			/* _COM_GPIO_CTRL_0 */
+	uint gpio_debounce_cnt;		/* _COM_GPIO_DEBOUNCE_COUNTER_0 */
+	uint crc_checksum_latched;	/* _COM_CRC_CHECKSUM_LATCHED_0 */
+};
+
+enum dc_disp_h_pulse_pos {
+	H_PULSE0_POSITION_A,
+	H_PULSE0_POSITION_B,
+	H_PULSE0_POSITION_C,
+	H_PULSE0_POSITION_D,
+	H_PULSE0_POSITION_COUNT,
+};
+
+struct _disp_h_pulse {
+	/* _DISP_H_PULSE0/1/2_CONTROL_0 */
+	uint h_pulse_ctrl;
+	/* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */
+	uint h_pulse_pos[H_PULSE0_POSITION_COUNT];
+};
+
+enum dc_disp_v_pulse_pos {
+	V_PULSE0_POSITION_A,
+	V_PULSE0_POSITION_B,
+	V_PULSE0_POSITION_C,
+	V_PULSE0_POSITION_COUNT,
+};
+
+struct _disp_v_pulse0 {
+	/* _DISP_H_PULSE0/1_CONTROL_0 */
+	uint v_pulse_ctrl;
+	/* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */
+	uint v_pulse_pos[V_PULSE0_POSITION_COUNT];
+};
+
+struct _disp_v_pulse2 {
+	/* _DISP_H_PULSE2/3_CONTROL_0 */
+	uint v_pulse_ctrl;
+	/* _DISP_H_PULSE2/3_POSITION_A_0 */
+	uint v_pulse_pos_a;
+};
+
+enum dc_disp_h_pulse_reg {
+	H_PULSE0,
+	H_PULSE1,
+	H_PULSE2,
+	H_PULSE_COUNT,
+};
+
+enum dc_disp_pp_select {
+	PP_SELECT_A,
+	PP_SELECT_B,
+	PP_SELECT_C,
+	PP_SELECT_D,
+	PP_SELECT_COUNT,
+};
+
+/* DISP register 0x400 ~ 0x4c1 */
+struct dc_disp_reg {
+	/* Address 0x400 ~ 0x40a */
+	uint disp_signal_opt0;		/* _DISP_DISP_SIGNAL_OPTIONS0_0 */
+	uint disp_signal_opt1;		/* _DISP_DISP_SIGNAL_OPTIONS1_0 */
+	uint disp_win_opt;		/* _DISP_DISP_WIN_OPTIONS_0 */
+	uint mem_high_pri;		/* _DISP_MEM_HIGH_PRIORITY_0 */
+	uint mem_high_pri_timer;	/* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */
+	uint disp_timing_opt;		/* _DISP_DISP_TIMING_OPTIONS_0 */
+	uint ref_to_sync;		/* _DISP_REF_TO_SYNC_0 */
+	uint sync_width;		/* _DISP_SYNC_WIDTH_0 */
+	uint back_porch;		/* _DISP_BACK_PORCH_0 */
+	uint disp_active;		/* _DISP_DISP_ACTIVE_0 */
+	uint front_porch;		/* _DISP_FRONT_PORCH_0 */
+
+	/* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_  */
+	struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
+
+	/* Address 0x41a ~ 0x421 */
+	struct _disp_v_pulse0 v_pulse0;	/* _DISP_V_PULSE0_ */
+	struct _disp_v_pulse0 v_pulse1;	/* _DISP_V_PULSE1_ */
+
+	/* Address 0x422 ~ 0x425 */
+	struct _disp_v_pulse2 v_pulse3;	/* _DISP_V_PULSE2_ */
+	struct _disp_v_pulse2 v_pulse4;	/* _DISP_V_PULSE3_ */
+
+	/* Address 0x426 ~ 0x429 */
+	uint m0_ctrl;			/* _DISP_M0_CONTROL_0 */
+	uint m1_ctrl;			/* _DISP_M1_CONTROL_0 */
+	uint di_ctrl;			/* _DISP_DI_CONTROL_0 */
+	uint pp_ctrl;			/* _DISP_PP_CONTROL_0 */
+
+	/* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */
+	uint pp_select[PP_SELECT_COUNT];
+
+	/* Address 0x42e ~ 0x435 */
+	uint disp_clk_ctrl;		/* _DISP_DISP_CLOCK_CONTROL_0 */
+	uint disp_interface_ctrl;	/* _DISP_DISP_INTERFACE_CONTROL_0 */
+	uint disp_color_ctrl;		/* _DISP_DISP_COLOR_CONTROL_0 */
+	uint shift_clk_opt;		/* _DISP_SHIFT_CLOCK_OPTIONS_0 */
+	uint data_enable_opt;		/* _DISP_DATA_ENABLE_OPTIONS_0 */
+	uint serial_interface_opt;	/* _DISP_SERIAL_INTERFACE_OPTIONS_0 */
+	uint lcd_spi_opt;		/* _DISP_LCD_SPI_OPTIONS_0 */
+	uint border_color;		/* _DISP_BORDER_COLOR_0 */
+
+	/* Address 0x436 ~ 0x439 */
+	uint color_key0_lower;		/* _DISP_COLOR_KEY0_LOWER_0 */
+	uint color_key0_upper;		/* _DISP_COLOR_KEY0_UPPER_0 */
+	uint color_key1_lower;		/* _DISP_COLOR_KEY1_LOWER_0 */
+	uint color_key1_upper;		/* _DISP_COLOR_KEY1_UPPER_0 */
+
+	uint reserved0[2];		/* reserved_0[2] */
+
+	/* Address 0x43c ~ 0x442 */
+	uint cursor_foreground;		/* _DISP_CURSOR_FOREGROUND_0 */
+	uint cursor_background;		/* _DISP_CURSOR_BACKGROUND_0 */
+	uint cursor_start_addr;		/* _DISP_CURSOR_START_ADDR_0 */
+	uint cursor_start_addr_ns;	/* _DISP_CURSOR_START_ADDR_NS_0 */
+	uint cursor_pos;		/* _DISP_CURSOR_POSITION_0 */
+	uint cursor_pos_ns;		/* _DISP_CURSOR_POSITION_NS_0 */
+	uint seq_ctrl;			/* _DISP_INIT_SEQ_CONTROL_0 */
+
+	/* Address 0x443 ~ 0x446 */
+	uint spi_init_seq_data_a;	/* _DISP_SPI_INIT_SEQ_DATA_A_0 */
+	uint spi_init_seq_data_b;	/* _DISP_SPI_INIT_SEQ_DATA_B_0 */
+	uint spi_init_seq_data_c;	/* _DISP_SPI_INIT_SEQ_DATA_C_0 */
+	uint spi_init_seq_data_d;	/* _DISP_SPI_INIT_SEQ_DATA_D_0 */
+
+	uint reserved1[0x39];		/* reserved1[0x39], */
+
+	/* Address 0x480 ~ 0x484 */
+	uint dc_mccif_fifoctrl;		/* _DISP_DC_MCCIF_FIFOCTRL_0 */
+	uint mccif_disp0a_hyst;		/* _DISP_MCCIF_DISPLAY0A_HYST_0 */
+	uint mccif_disp0b_hyst;		/* _DISP_MCCIF_DISPLAY0B_HYST_0 */
+	uint mccif_disp0c_hyst;		/* _DISP_MCCIF_DISPLAY0C_HYST_0 */
+	uint mccif_disp1b_hyst;		/* _DISP_MCCIF_DISPLAY1B_HYST_0 */
+
+	uint reserved2[0x3b];		/* reserved2[0x3b] */
+
+	/* Address 0x4c0 ~ 0x4c1 */
+	uint dac_crt_ctrl;		/* _DISP_DAC_CRT_CTRL_0 */
+	uint disp_misc_ctrl;		/* _DISP_DISP_MISC_CONTROL_0 */
+
+	u32 rsvd_4c2[34];		/* 4c2 - 4e3 */
+
+	/* Address 0x4e4 */
+	u32 blend_background_color;	/* _DISP_BLEND_BACKGROUND_COLOR_0 */
+};
+
+enum dc_winc_filter_p {
+	WINC_FILTER_COUNT	= 0x10,
+};
+
+/* Window A/B/C register 0x500 ~ 0x628 */
+struct dc_winc_reg {
+
+	/* Address 0x500 */
+	uint color_palette;		/* _WINC_COLOR_PALETTE_0 */
+
+	uint reserved0[0xff];		/* reserved_0[0xff] */
+
+	/* Address 0x600 */
+	uint palette_color_ext;		/* _WINC_PALETTE_COLOR_EXT_0 */
+
+	/* _WINC_H_FILTER_P00~0F_0 */
+	/* Address 0x601 ~ 0x610 */
+	uint h_filter_p[WINC_FILTER_COUNT];
+
+	/* Address 0x611 ~ 0x618 */
+	uint csc_yof;			/* _WINC_CSC_YOF_0 */
+	uint csc_kyrgb;			/* _WINC_CSC_KYRGB_0 */
+	uint csc_kur;			/* _WINC_CSC_KUR_0 */
+	uint csc_kvr;			/* _WINC_CSC_KVR_0 */
+	uint csc_kug;			/* _WINC_CSC_KUG_0 */
+	uint csc_kvg;			/* _WINC_CSC_KVG_0 */
+	uint csc_kub;			/* _WINC_CSC_KUB_0 */
+	uint csc_kvb;			/* _WINC_CSC_KVB_0 */
+
+	/* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
+	uint v_filter_p[WINC_FILTER_COUNT];
+};
+
+/* WIN A/B/C Register 0x700 ~ 0x719*/
+struct dc_win_reg {
+	/* Address 0x700 ~ 0x719 */
+	uint win_opt;			/* _WIN_WIN_OPTIONS_0 */
+	uint byte_swap;			/* _WIN_BYTE_SWAP_0 */
+	uint buffer_ctrl;		/* _WIN_BUFFER_CONTROL_0 */
+	uint color_depth;		/* _WIN_COLOR_DEPTH_0 */
+	uint pos;			/* _WIN_POSITION_0 */
+	uint size;			/* _WIN_SIZE_0 */
+	uint prescaled_size;		/* _WIN_PRESCALED_SIZE_0 */
+	uint h_initial_dda;		/* _WIN_H_INITIAL_DDA_0 */
+	uint v_initial_dda;		/* _WIN_V_INITIAL_DDA_0 */
+	uint dda_increment;		/* _WIN_DDA_INCREMENT_0 */
+	uint line_stride;		/* _WIN_LINE_STRIDE_0 */
+	uint buf_stride;		/* _WIN_BUF_STRIDE_0 */
+	uint uv_buf_stride;		/* _WIN_UV_BUF_STRIDE_0 */
+	uint buffer_addr_mode;		/* _WIN_BUFFER_ADDR_MODE_0 */
+	uint dv_ctrl;			/* _WIN_DV_CONTROL_0 */
+	uint blend_nokey;		/* _WIN_BLEND_NOKEY_0 */
+	uint blend_1win;		/* _WIN_BLEND_1WIN_0 */
+	uint blend_2win_x;		/* _WIN_BLEND_2WIN_X_0 */
+	uint blend_2win_y;		/* _WIN_BLEND_2WIN_Y_0 */
+	uint blend_3win_xy;		/* _WIN_BLEND_3WIN_XY_0 */
+	uint hp_fetch_ctrl;		/* _WIN_HP_FETCH_CONTROL_0 */
+	uint global_alpha;		/* _WIN_GLOBAL_ALPHA */
+	uint blend_layer_ctrl;		/* _WINBUF_BLEND_LAYER_CONTROL_0 */
+	uint blend_match_select;	/* _WINBUF_BLEND_MATCH_SELECT_0 */
+	uint blend_nomatch_select;	/* _WINBUF_BLEND_NOMATCH_SELECT_0 */
+	uint blend_alpha_1bit;		/* _WINBUF_BLEND_ALPHA_1BIT_0 */
+};
+
+/* WINBUF A/B/C Register 0x800 ~ 0x80d */
+struct dc_winbuf_reg {
+	/* Address 0x800 ~ 0x80d */
+	uint start_addr;		/* _WINBUF_START_ADDR_0 */
+	uint start_addr_ns;		/* _WINBUF_START_ADDR_NS_0 */
+	uint start_addr_u;		/* _WINBUF_START_ADDR_U_0 */
+	uint start_addr_u_ns;		/* _WINBUF_START_ADDR_U_NS_0 */
+	uint start_addr_v;		/* _WINBUF_START_ADDR_V_0 */
+	uint start_addr_v_ns;		/* _WINBUF_START_ADDR_V_NS_0 */
+	uint addr_h_offset;		/* _WINBUF_ADDR_H_OFFSET_0 */
+	uint addr_h_offset_ns;		/* _WINBUF_ADDR_H_OFFSET_NS_0 */
+	uint addr_v_offset;		/* _WINBUF_ADDR_V_OFFSET_0 */
+	uint addr_v_offset_ns;		/* _WINBUF_ADDR_V_OFFSET_NS_0 */
+	uint uflow_status;		/* _WINBUF_UFLOW_STATUS_0 */
+	uint buffer_surface_kind;	/* DC_WIN_BUFFER_SURFACE_KIND */
+	uint rsvd_80c;
+	uint start_addr_hi;		/* DC_WINBUF_START_ADDR_HI_0 */
+};
+
+/* Display Controller (DC_) regs */
+struct dc_ctlr {
+	struct dc_cmd_reg cmd;		/* CMD register 0x000 ~ 0x43 */
+	uint reserved0[0x2bc];
+
+	struct dc_com_reg com;		/* COM register 0x300 ~ 0x329 */
+	uint reserved1[0xd6];
+
+	struct dc_disp_reg disp;	/* DISP register 0x400 ~ 0x4e4 */
+	uint reserved2[0x1b];
+
+	struct dc_winc_reg winc;	/* Window A/B/C 0x500 ~ 0x628 */
+	uint reserved3[0xd7];
+
+	struct dc_win_reg win;		/* WIN A/B/C 0x700 ~ 0x719*/
+	uint reserved4[0xe6];
+
+	struct dc_winbuf_reg winbuf;	/* WINBUF A/B/C 0x800 ~ 0x80d */
+};
+
+/* DC_CMD_DISPLAY_COMMAND 0x032 */
+#define CTRL_MODE_SHIFT		5
+#define CTRL_MODE_MASK		(0x3 << CTRL_MODE_SHIFT)
+enum {
+	CTRL_MODE_STOP,
+	CTRL_MODE_C_DISPLAY,
+	CTRL_MODE_NC_DISPLAY,
+};
+
+/* _WIN_COLOR_DEPTH_0 */
+enum win_color_depth_id {
+	COLOR_DEPTH_P1,
+	COLOR_DEPTH_P2,
+	COLOR_DEPTH_P4,
+	COLOR_DEPTH_P8,
+	COLOR_DEPTH_B4G4R4A4,
+	COLOR_DEPTH_B5G5R5A,
+	COLOR_DEPTH_B5G6R5,
+	COLOR_DEPTH_AB5G5R5,
+	COLOR_DEPTH_B8G8R8A8 = 12,
+	COLOR_DEPTH_R8G8B8A8,
+	COLOR_DEPTH_B6x2G6x2R6x2A8,
+	COLOR_DEPTH_R6x2G6x2B6x2A8,
+	COLOR_DEPTH_YCbCr422,
+	COLOR_DEPTH_YUV422,
+	COLOR_DEPTH_YCbCr420P,
+	COLOR_DEPTH_YUV420P,
+	COLOR_DEPTH_YCbCr422P,
+	COLOR_DEPTH_YUV422P,
+	COLOR_DEPTH_YCbCr422R,
+	COLOR_DEPTH_YUV422R,
+	COLOR_DEPTH_YCbCr422RA,
+	COLOR_DEPTH_YUV422RA,
+};
+
+/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */
+#define PW0_ENABLE		BIT(0)
+#define PW1_ENABLE		BIT(2)
+#define PW2_ENABLE		BIT(4)
+#define PW3_ENABLE		BIT(6)
+#define PW4_ENABLE		BIT(8)
+#define PM0_ENABLE		BIT(16)
+#define PM1_ENABLE		BIT(18)
+#define SPI_ENABLE		BIT(24)
+#define HSPI_ENABLE		BIT(25)
+
+/* DC_CMD_STATE_ACCESS 0x040 */
+#define  READ_MUX_ASSEMBLY	(0 << 0)
+#define  READ_MUX_ACTIVE	(1 << 0)
+#define  WRITE_MUX_ASSEMBLY	(0 << 2)
+#define  WRITE_MUX_ACTIVE	(1 << 2)
+
+/* DC_CMD_STATE_CONTROL 0x041 */
+#define GENERAL_ACT_REQ		BIT(0)
+#define WIN_A_ACT_REQ		BIT(1)
+#define WIN_B_ACT_REQ		BIT(2)
+#define WIN_C_ACT_REQ		BIT(3)
+#define WIN_D_ACT_REQ		BIT(4)
+#define WIN_H_ACT_REQ		BIT(5)
+#define CURSOR_ACT_REQ		BIT(7)
+#define GENERAL_UPDATE		BIT(8)
+#define WIN_A_UPDATE		BIT(9)
+#define WIN_B_UPDATE		BIT(10)
+#define WIN_C_UPDATE		BIT(11)
+#define WIN_D_UPDATE		BIT(12)
+#define WIN_H_UPDATE		BIT(13)
+#define CURSOR_UPDATE		BIT(15)
+#define NC_HOST_TRIG		BIT(24)
+
+/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */
+#define WINDOW_A_SELECT		BIT(4)
+#define WINDOW_B_SELECT		BIT(5)
+#define WINDOW_C_SELECT		BIT(6)
+#define	WINDOW_D_SELECT		BIT(7)
+#define	WINDOW_H_SELECT		BIT(8)
+
+/* DC_DISP_DISP_WIN_OPTIONS 0x402 */
+#define	CURSOR_ENABLE		BIT(16)
+#define	SOR_ENABLE		BIT(25)
+#define	TVO_ENABLE		BIT(28)
+#define	DSI_ENABLE		BIT(29)
+#define	HDMI_ENABLE		BIT(30)
+
+/* DC_DISP_DISP_TIMING_OPTIONS 0x405 */
+#define	VSYNC_H_POSITION(x)	((x) & 0xfff)
+
+/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */
+#define SHIFT_CLK_DIVIDER_SHIFT	0
+#define SHIFT_CLK_DIVIDER_MASK	(0xff << SHIFT_CLK_DIVIDER_SHIFT)
+#define	PIXEL_CLK_DIVIDER_SHIFT	8
+#define	PIXEL_CLK_DIVIDER_MSK	(0xf << PIXEL_CLK_DIVIDER_SHIFT)
+enum {
+	PIXEL_CLK_DIVIDER_PCD1,
+	PIXEL_CLK_DIVIDER_PCD1H,
+	PIXEL_CLK_DIVIDER_PCD2,
+	PIXEL_CLK_DIVIDER_PCD3,
+	PIXEL_CLK_DIVIDER_PCD4,
+	PIXEL_CLK_DIVIDER_PCD6,
+	PIXEL_CLK_DIVIDER_PCD8,
+	PIXEL_CLK_DIVIDER_PCD9,
+	PIXEL_CLK_DIVIDER_PCD12,
+	PIXEL_CLK_DIVIDER_PCD16,
+	PIXEL_CLK_DIVIDER_PCD18,
+	PIXEL_CLK_DIVIDER_PCD24,
+	PIXEL_CLK_DIVIDER_PCD13,
+};
+
+/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */
+#define DATA_FORMAT_SHIFT	0
+#define DATA_FORMAT_MASK	(0xf << DATA_FORMAT_SHIFT)
+enum {
+	DATA_FORMAT_DF1P1C,
+	DATA_FORMAT_DF1P2C24B,
+	DATA_FORMAT_DF1P2C18B,
+	DATA_FORMAT_DF1P2C16B,
+	DATA_FORMAT_DF2S,
+	DATA_FORMAT_DF3S,
+	DATA_FORMAT_DFSPI,
+	DATA_FORMAT_DF1P3C24B,
+	DATA_FORMAT_DF1P3C18B,
+};
+#define DATA_ALIGNMENT_SHIFT	8
+enum {
+	DATA_ALIGNMENT_MSB,
+	DATA_ALIGNMENT_LSB,
+};
+#define DATA_ORDER_SHIFT	9
+enum {
+	DATA_ORDER_RED_BLUE,
+	DATA_ORDER_BLUE_RED,
+};
+
+/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
+#define DE_SELECT_SHIFT		0
+#define DE_SELECT_MASK		(0x3 << DE_SELECT_SHIFT)
+#define DE_SELECT_ACTIVE_BLANK	0x0
+#define DE_SELECT_ACTIVE	0x1
+#define DE_SELECT_ACTIVE_IS	0x2
+#define DE_CONTROL_SHIFT	2
+#define DE_CONTROL_MASK		(0x7 << DE_CONTROL_SHIFT)
+enum {
+	DE_CONTROL_ONECLK,
+	DE_CONTROL_NORMAL,
+	DE_CONTROL_EARLY_EXT,
+	DE_CONTROL_EARLY,
+	DE_CONTROL_ACTIVE_BLANK,
+};
+
+/* DC_WIN_WIN_OPTIONS 0x700 */
+#define H_DIRECTION		BIT(0)
+enum {
+	H_DIRECTION_INCREMENT,
+	H_DIRECTION_DECREMENT,
+};
+#define V_DIRECTION		BIT(2)
+enum {
+	V_DIRECTION_INCREMENT,
+	V_DIRECTION_DECREMENT,
+};
+#define COLOR_EXPAND		BIT(6)
+#define CP_ENABLE		BIT(16)
+#define DV_ENABLE		BIT(20)
+#define WIN_ENABLE		BIT(30)
+
+/* DC_WIN_BYTE_SWAP 0x701 */
+#define BYTE_SWAP_SHIFT		0
+#define BYTE_SWAP_MASK		(3 << BYTE_SWAP_SHIFT)
+enum {
+	BYTE_SWAP_NOSWAP,
+	BYTE_SWAP_SWAP2,
+	BYTE_SWAP_SWAP4,
+	BYTE_SWAP_SWAP4HW
+};
+
+/* DC_WIN_POSITION 0x704 */
+#define H_POSITION_SHIFT	0
+#define H_POSITION_MASK		(0x1FFF << H_POSITION_SHIFT)
+#define V_POSITION_SHIFT	16
+#define V_POSITION_MASK		(0x1FFF << V_POSITION_SHIFT)
+
+/* DC_WIN_SIZE 0x705 */
+#define H_SIZE_SHIFT		0
+#define H_SIZE_MASK		(0x1FFF << H_SIZE_SHIFT)
+#define V_SIZE_SHIFT		16
+#define V_SIZE_MASK		(0x1FFF << V_SIZE_SHIFT)
+
+/* DC_WIN_PRESCALED_SIZE 0x706 */
+#define H_PRESCALED_SIZE_SHIFT	0
+#define H_PRESCALED_SIZE_MASK	(0x7FFF << H_PRESCALED_SIZE)
+#define V_PRESCALED_SIZE_SHIFT	16
+#define V_PRESCALED_SIZE_MASK	(0x1FFF << V_PRESCALED_SIZE)
+
+/* DC_WIN_DDA_INCREMENT 0x709 */
+#define H_DDA_INC_SHIFT		0
+#define H_DDA_INC_MASK		(0xFFFF << H_DDA_INC_SHIFT)
+#define V_DDA_INC_SHIFT		16
+#define V_DDA_INC_MASK		(0xFFFF << V_DDA_INC_SHIFT)
+
+#define DC_POLL_TIMEOUT_MS		50
+#define DC_N_WINDOWS			5
+#define DC_REG_SAVE_SPACE		(DC_N_WINDOWS + 5)
+
+#endif /* __ASM_ARCH_TEGRA_DC_H */
diff --git a/arch/arm/include/asm/arch-tegra/funcmux.h b/arch/arm/include/asm/arch-tegra/funcmux.h
new file mode 100644
index 0000000..cf3ce3b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/funcmux.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+/* Tegra high-level function multiplexing */
+
+#ifndef _TEGRA_FUNCMUX_H_
+#define _TEGRA_FUNCMUX_H_
+
+/**
+ * Select a config for a particular peripheral.
+ *
+ * Each peripheral can operate through a number of configurations,
+ * which are sets of pins that it uses to bring out its signals.
+ * The basic config is 0, and higher numbers indicate different
+ * pinmux settings to bring the peripheral out on other pins,
+ *
+ * This function also disables tristate for the function's pins,
+ * so that they operate in normal mode.
+ *
+ * @param id		Peripheral id
+ * @param config	Configuration to use (FUNCMUX_...), 0 for default
+ * @return 0 if ok, -1 on error (e.g. incorrect id or config)
+ */
+int funcmux_select(enum periph_id id, int config);
+
+#endif	/* _TEGRA_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/fuse.h b/arch/arm/include/asm/arch-tegra/fuse.h
new file mode 100644
index 0000000..5b8e0bd
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/fuse.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _FUSE_H_
+#define _FUSE_H_
+
+/* FUSE registers */
+struct fuse_regs {
+	u32 reserved0[64];		/* 0x00 - 0xFC: */
+	u32 production_mode;		/* 0x100: FUSE_PRODUCTION_MODE */
+	u32 reserved1[3];		/* 0x104 - 0x10c: */
+	u32 sku_info;			/* 0x110 */
+	u32 reserved2[13];		/* 0x114 - 0x144: */
+	u32 fa;				/* 0x148: FUSE_FA */
+	u32 reserved3[21];		/* 0x14C - 0x19C: */
+	u32 security_mode;		/* 0x1A0: FUSE_SECURITY_MODE */
+};
+
+#endif	/* ifndef _FUSE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
new file mode 100644
index 0000000..4362c53
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010-2015
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_GP_PADCTRL_H_
+#define _TEGRA_GP_PADCTRL_H_
+
+#define GP_HIDREV			0x804
+
+/* bit fields definitions for APB_MISC_GP_HIDREV register */
+#define HIDREV_CHIPID_SHIFT		8
+#define HIDREV_CHIPID_MASK		(0xff << HIDREV_CHIPID_SHIFT)
+#define HIDREV_MAJORPREV_SHIFT		4
+#define HIDREV_MAJORPREV_MASK		(0xf << HIDREV_MAJORPREV_SHIFT)
+
+/* CHIPID field returned from APB_MISC_GP_HIDREV register */
+#define CHIPID_TEGRA20			0x20
+#define CHIPID_TEGRA30			0x30
+#define CHIPID_TEGRA114			0x35
+#define CHIPID_TEGRA124			0x40
+#define CHIPID_TEGRA210			0x21
+
+#endif	/* _TEGRA_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h
new file mode 100644
index 0000000..fe7b3a5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/gpio.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ */
+
+#ifndef _TEGRA_GPIO_H_
+#define _TEGRA_GPIO_H_
+
+#include <dt-bindings/gpio/tegra-gpio.h>
+
+#define TEGRA_GPIOS_PER_PORT	8
+#define TEGRA_PORTS_PER_BANK	4
+#define MAX_NUM_GPIOS           (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
+#define GPIO_NAME_SIZE		20	/* gpio_request max label len */
+
+#define GPIO_BANK(x)		((x) >> 5)
+#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
+#define GPIO_FULLPORT(x)	((x) >> 3)
+#define GPIO_BIT(x)		((x) & 0x7)
+
+enum tegra_gpio_init {
+	TEGRA_GPIO_INIT_IN,
+	TEGRA_GPIO_INIT_OUT0,
+	TEGRA_GPIO_INIT_OUT1,
+};
+
+struct tegra_gpio_config {
+	u32 gpio:16;
+	u32 init:2;
+};
+
+/**
+ * Configure a list of GPIOs
+ *
+ * @param config	List of GPIO configurations
+ * @param len		Number of config items in list
+ */
+void gpio_config_table(const struct tegra_gpio_config *config, int len);
+
+#endif	/* TEGRA_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/gpu.h b/arch/arm/include/asm/arch-tegra/gpu.h
new file mode 100644
index 0000000..d4d6deb
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/gpu.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2015
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __ASM_ARCH_TEGRA_GPU_H
+#define __ASM_ARCH_TEGRA_GPU_H
+
+#if defined(CONFIG_TEGRA_GPU)
+
+void tegra_gpu_config(void);
+
+#else /* CONFIG_TEGRA_GPU */
+
+static inline void tegra_gpu_config(void)
+{
+}
+
+#endif /* CONFIG_TEGRA_GPU */
+
+#if defined(CONFIG_OF_LIBFDT)
+
+int tegra_gpu_enable_node(void *blob, const char *gpupath);
+
+#else /* CONFIG_OF_LIBFDT */
+
+static inline int tegra_gpu_enable_node(void *blob, const char *compat)
+{
+	return 0;
+}
+
+#endif /* CONFIG_OF_LIBFDT */
+
+#endif	/* __ASM_ARCH_TEGRA_GPU_H */
diff --git a/arch/arm/include/asm/arch-tegra/ivc.h b/arch/arm/include/asm/arch-tegra/ivc.h
new file mode 100644
index 0000000..53cb56d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/ivc.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _ASM_ARCH_TEGRA_IVC_H
+#define _ASM_ARCH_TEGRA_IVC_H
+
+#include <common.h>
+
+/*
+ * Tegra IVC is a communication protocol that transfers fixed-size frames
+ * bi-directionally and in-order between the local CPU and some remote entity.
+ * Communication is via a statically sized and allocated buffer in shared
+ * memory and a notification mechanism.
+ *
+ * This API handles all aspects of the shared memory buffer's metadata, and
+ * leaves all aspects of the frame content to the calling code; frames
+ * typically contain some higher-level protocol. The notification mechanism is
+ * also handled externally to this API, since it can vary from instance to
+ * instance.
+ *
+ * The client model is to first find some free (for TX) or filled (for RX)
+ * frame, process that frame's memory buffer (fill or read it), and then
+ * inform the protocol that the frame has been filled/read, i.e. advance the
+ * write/read pointer. If the channel is full, there may be no available frames
+ * to fill/read. In this case, client code may either poll for an available
+ * frame, or wait for the remote entity to send a notification to the local
+ * CPU.
+ */
+
+/**
+ * struct tegra_ivc - In-memory shared memory layout.
+ *
+ * This is described in detail in ivc.c.
+ */
+struct tegra_ivc_channel_header;
+
+/**
+ * struct tegra_ivc - Software state of an IVC channel.
+ *
+ * This state is internal to the IVC code and should not be accessed directly
+ * by clients. It is public solely so clients can allocate storage for the
+ * structure.
+ */
+struct tegra_ivc {
+	/**
+	 * rx_channel - Pointer to the shared memory region used to receive
+	 * messages from the remote entity.
+	 */
+	struct tegra_ivc_channel_header *rx_channel;
+	/**
+	 * tx_channel - Pointer to the shared memory region used to send
+	 * messages to the remote entity.
+	 */
+	struct tegra_ivc_channel_header *tx_channel;
+	/**
+	 * r_pos - The position in list of frames in rx_channel that we are
+	 * reading from.
+	 */
+	uint32_t r_pos;
+	/**
+	 * w_pos - The position in list of frames in tx_channel that we are
+	 * writing to.
+	 */
+	uint32_t w_pos;
+	/**
+	 * nframes - The number of frames allocated (in each direction) in
+	 * shared memory.
+	 */
+	uint32_t nframes;
+	/**
+	 * frame_size - The size of each frame in shared memory.
+	 */
+	uint32_t frame_size;
+	/**
+	 * notify - Function to call to notify the remote processor of a
+	 * change in channel state.
+	 */
+	void (*notify)(struct tegra_ivc *);
+};
+
+/**
+ * tegra_ivc_read_get_next_frame - Locate the next frame to receive.
+ *
+ * Locate the next frame to be received/processed, return the address of the
+ * frame, and do not remove it from the queue. Repeated calls to this function
+ * will return the same address until tegra_ivc_read_advance() is called.
+ *
+ * @ivc		The IVC channel.
+ * @frame	Pointer to be filled with the address of the frame to receive.
+ *
+ * @return 0 if a frame is available, else a negative error code.
+ */
+int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame);
+
+/**
+ * tegra_ivc_read_advance - Advance the read queue.
+ *
+ * Inform the protocol and remote entity that the frame returned by
+ * tegra_ivc_read_get_next_frame() has been processed. The remote end may then
+ * re-use it to transmit further data. Subsequent to this function returning,
+ * tegra_ivc_read_get_next_frame() will return a different frame.
+ *
+ * @ivc		The IVC channel.
+ *
+ * @return 0 if OK, else a negative error code.
+ */
+int tegra_ivc_read_advance(struct tegra_ivc *ivc);
+
+/**
+ * tegra_ivc_write_get_next_frame - Locate the next frame to fill for transmit.
+ *
+ * Locate the next frame to be filled for transmit, return the address of the
+ * frame, and do not add it to the queue. Repeated calls to this function
+ * will return the same address until tegra_ivc_read_advance() is called.
+ *
+ * @ivc		The IVC channel.
+ * @frame	Pointer to be filled with the address of the frame to fill.
+ *
+ * @return 0 if a frame is available, else a negative error code.
+ */
+int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame);
+
+/**
+ * tegra_ivc_write_advance - Advance the write queue.
+ *
+ * Inform the protocol and remote entity that the frame returned by
+ * tegra_ivc_write_get_next_frame() has been filled and should be transmitted.
+ * The remote end may then read data from it. Subsequent to this function
+ * returning, tegra_ivc_write_get_next_frame() will return a different frame.
+ *
+ * @ivc		The IVC channel.
+ *
+ * @return 0 if OK, else a negative error code.
+ */
+int tegra_ivc_write_advance(struct tegra_ivc *ivc);
+
+/**
+ * tegra_ivc_channel_notified - handle internal messages
+ *
+ * This function must be called following every notification.
+ *
+ * @ivc		The IVC channel.
+ *
+ * @return 0 if the channel is ready for communication, or -EAGAIN if a
+ * channel reset is in progress.
+ */
+int tegra_ivc_channel_notified(struct tegra_ivc *ivc);
+
+/**
+ * tegra_ivc_channel_reset - initiates a reset of the shared memory state
+ *
+ * This function must be called after a channel is initialized but before it
+ * is used for communication. The channel will be ready for use when a
+ * subsequent call to notify the remote of the channel reset indicates the
+ * reset operation is complete.
+ *
+ * @ivc		The IVC channel.
+ */
+void tegra_ivc_channel_reset(struct tegra_ivc *ivc);
+
+/**
+ * tegra_ivc_init - Initialize a channel's software state.
+ *
+ * @ivc		The IVC channel.
+ * @rx_base	Address of the the RX shared memory buffer.
+ * @tx_base	Address of the the TX shared memory buffer.
+ * @nframes	Number of frames in each shared memory buffer.
+ * @frame_size	Size of each frame.
+ *
+ * @return 0 if OK, else a negative error code.
+ */
+int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base,
+		   uint32_t nframes, uint32_t frame_size,
+		   void (*notify)(struct tegra_ivc *));
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
new file mode 100644
index 0000000..4b6e841
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -0,0 +1,249 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_PINMUX_H_
+#define _TEGRA_PINMUX_H_
+
+#include <linux/types.h>
+
+#include <asm/arch/tegra.h>
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+	PMUX_PULL_NORMAL = 0,
+	PMUX_PULL_DOWN,
+	PMUX_PULL_UP,
+};
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+	PMUX_TRI_NORMAL = 0,
+	PMUX_TRI_TRISTATE = 1,
+};
+
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
+enum pmux_pin_io {
+	PMUX_PIN_OUTPUT = 0,
+	PMUX_PIN_INPUT = 1,
+	PMUX_PIN_NONE,
+};
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
+enum pmux_pin_lock {
+	PMUX_PIN_LOCK_DEFAULT = 0,
+	PMUX_PIN_LOCK_DISABLE,
+	PMUX_PIN_LOCK_ENABLE,
+};
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_OD
+enum pmux_pin_od {
+	PMUX_PIN_OD_DEFAULT = 0,
+	PMUX_PIN_OD_DISABLE,
+	PMUX_PIN_OD_ENABLE,
+};
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
+enum pmux_pin_ioreset {
+	PMUX_PIN_IO_RESET_DEFAULT = 0,
+	PMUX_PIN_IO_RESET_DISABLE,
+	PMUX_PIN_IO_RESET_ENABLE,
+};
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
+enum pmux_pin_rcv_sel {
+	PMUX_PIN_RCV_SEL_DEFAULT = 0,
+	PMUX_PIN_RCV_SEL_NORMAL,
+	PMUX_PIN_RCV_SEL_HIGH,
+};
+#endif
+
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+enum pmux_pin_e_io_hv {
+	PMUX_PIN_E_IO_HV_DEFAULT = 0,
+	PMUX_PIN_E_IO_HV_NORMAL,
+	PMUX_PIN_E_IO_HV_HIGH,
+};
+#endif
+
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
+/* Defines a pin group cfg's low-power mode select */
+enum pmux_lpmd {
+	PMUX_LPMD_X8 = 0,
+	PMUX_LPMD_X4,
+	PMUX_LPMD_X2,
+	PMUX_LPMD_X,
+	PMUX_LPMD_NONE = -1,
+};
+#endif
+
+#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pmux_schmt {
+	PMUX_SCHMT_DISABLE = 0,
+	PMUX_SCHMT_ENABLE = 1,
+	PMUX_SCHMT_NONE = -1,
+};
+#endif
+
+#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pmux_hsm {
+	PMUX_HSM_DISABLE = 0,
+	PMUX_HSM_ENABLE = 1,
+	PMUX_HSM_NONE = -1,
+};
+#endif
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pmux_pingrp_config {
+	u32 pingrp:16;		/* pin group PMUX_PINGRP_...        */
+	u32 func:8;		/* function to assign PMUX_FUNC_... */
+	u32 pull:2;		/* pull up/down/normal PMUX_PULL_...*/
+	u32 tristate:2;		/* tristate or normal PMUX_TRI_...  */
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
+	u32 io:2;		/* input or output PMUX_PIN_...     */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_LOCK
+	u32 lock:2;		/* lock enable/disable PMUX_PIN...  */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_OD
+	u32 od:2;		/* open-drain or push-pull driver   */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
+	u32 ioreset:2;		/* input/output reset PMUX_PIN...   */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
+	u32 rcv_sel:2;		/* select between High and Normal  */
+				/* VIL/VIH receivers */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
+	u32 e_io_hv:2;		/* select 3.3v tolerant receivers */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_SCHMT
+	u32 schmt:2;		/* schmitt enable            */
+#endif
+#ifdef TEGRA_PMX_PINS_HAVE_HSM
+	u32 hsm:2;		/* high-speed mode enable    */
+#endif
+};
+
+#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
+/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
+void pinmux_set_tristate_input_clamping(void);
+void pinmux_clear_tristate_input_clamping(void);
+#endif
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+#endif
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config	List of config items
+ * @param len		Number of config items in list
+ */
+void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
+				int len);
+
+struct pmux_pingrp_desc {
+	u8 funcs[4];
+#if defined(CONFIG_TEGRA20)
+	u8 ctl_id;
+	u8 pull_id;
+#endif /* CONFIG_TEGRA20 */
+};
+
+extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+
+#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
+
+#define PMUX_SLWF_MIN	0
+#define PMUX_SLWF_MAX	3
+#define PMUX_SLWF_NONE	-1
+
+#define PMUX_SLWR_MIN	0
+#define PMUX_SLWR_MAX	3
+#define PMUX_SLWR_NONE	-1
+
+#define PMUX_DRVUP_MIN	0
+#define PMUX_DRVUP_MAX	127
+#define PMUX_DRVUP_NONE	-1
+
+#define PMUX_DRVDN_MIN	0
+#define PMUX_DRVDN_MAX	127
+#define PMUX_DRVDN_NONE	-1
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct pmux_drvgrp_config {
+	u32 drvgrp:16;	/* pin group PMUX_DRVGRP_x   */
+	u32 slwf:3;		/* falling edge slew         */
+	u32 slwr:3;		/* rising edge slew          */
+	u32 drvup:8;		/* pull-up drive strength    */
+	u32 drvdn:8;		/* pull-down drive strength  */
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
+	u32 lpmd:3;		/* low-power mode selection  */
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
+	u32 schmt:2;		/* schmidt enable            */
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
+	u32 hsm:2;		/* high-speed mode enable    */
+#endif
+};
+
+/**
+ * Set the GP pad configs
+ *
+ * @param config	List of config items
+ * @param len		Number of config items in list
+ */
+void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
+				int len);
+
+#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
+
+#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
+struct pmux_mipipadctrlgrp_config {
+	u32 grp:16;	/* pin group PMUX_MIPIPADCTRLGRP_x   */
+	u32 func:8;	/* function to assign PMUX_FUNC_... */
+};
+
+void pinmux_config_mipipadctrlgrp_table(
+	const struct pmux_mipipadctrlgrp_config *config, int len);
+
+struct pmux_mipipadctrlgrp_desc {
+	u8 funcs[2];
+};
+
+extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups;
+#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
+
+#endif /* _TEGRA_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
new file mode 100644
index 0000000..1524bf2
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -0,0 +1,409 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010-2019
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _PMC_H_
+#define _PMC_H_
+
+/* Power Management Controller (APBDEV_PMC_) registers */
+struct pmc_ctlr {
+	uint pmc_cntrl;			/* _CNTRL_0, offset 00 */
+	uint pmc_sec_disable;		/* _SEC_DISABLE_0, offset 04 */
+	uint pmc_pmc_swrst;		/* _PMC_SWRST_0, offset 08 */
+	uint pmc_wake_mask;		/* _WAKE_MASK_0, offset 0C */
+	uint pmc_wake_lvl;		/* _WAKE_LVL_0, offset 10 */
+	uint pmc_wake_status;		/* _WAKE_STATUS_0, offset 14 */
+	uint pmc_sw_wake_status;	/* _SW_WAKE_STATUS_0, offset 18 */
+	uint pmc_dpd_pads_oride;	/* _DPD_PADS_ORIDE_0, offset 1C */
+	uint pmc_dpd_sample;		/* _DPD_PADS_SAMPLE_0, offset 20 */
+	uint pmc_dpd_enable;		/* _DPD_PADS_ENABLE_0, offset 24 */
+	uint pmc_pwrgate_timer_off;	/* _PWRGATE_TIMER_OFF_0, offset 28 */
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
+	uint pmc_pwrgate_timer_on;	/* _PWRGATE_TIMER_ON_0, offset 2C */
+#else
+	uint pmc_clamp_status;		/* _CLAMP_STATUS_0, offset 2C */
+#endif
+	uint pmc_pwrgate_toggle;	/* _PWRGATE_TOGGLE_0, offset 30 */
+	uint pmc_remove_clamping;	/* _REMOVE_CLAMPING_CMD_0, offset 34 */
+	uint pmc_pwrgate_status;	/* _PWRGATE_STATUS_0, offset 38 */
+	uint pmc_pwrgood_timer;		/* _PWRGOOD_TIMER_0, offset 3C */
+	uint pmc_blink_timer;		/* _BLINK_TIMER_0, offset 40 */
+	uint pmc_no_iopower;		/* _NO_IOPOWER_0, offset 44 */
+	uint pmc_pwr_det;		/* _PWR_DET_0, offset 48 */
+	uint pmc_pwr_det_latch;		/* _PWR_DET_LATCH_0, offset 4C */
+
+	uint pmc_scratch0;		/* _SCRATCH0_0, offset 50 */
+	uint pmc_scratch1;		/* _SCRATCH1_0, offset 54 */
+	uint pmc_scratch2;		/* _SCRATCH2_0, offset 58 */
+	uint pmc_scratch3;		/* _SCRATCH3_0, offset 5C */
+	uint pmc_scratch4;		/* _SCRATCH4_0, offset 60 */
+	uint pmc_scratch5;		/* _SCRATCH5_0, offset 64 */
+	uint pmc_scratch6;		/* _SCRATCH6_0, offset 68 */
+	uint pmc_scratch7;		/* _SCRATCH7_0, offset 6C */
+	uint pmc_scratch8;		/* _SCRATCH8_0, offset 70 */
+	uint pmc_scratch9;		/* _SCRATCH9_0, offset 74 */
+	uint pmc_scratch10;		/* _SCRATCH10_0, offset 78 */
+	uint pmc_scratch11;		/* _SCRATCH11_0, offset 7C */
+	uint pmc_scratch12;		/* _SCRATCH12_0, offset 80 */
+	uint pmc_scratch13;		/* _SCRATCH13_0, offset 84 */
+	uint pmc_scratch14;		/* _SCRATCH14_0, offset 88 */
+	uint pmc_scratch15;		/* _SCRATCH15_0, offset 8C */
+	uint pmc_scratch16;		/* _SCRATCH16_0, offset 90 */
+	uint pmc_scratch17;		/* _SCRATCH17_0, offset 94 */
+	uint pmc_scratch18;		/* _SCRATCH18_0, offset 98 */
+	uint pmc_scratch19;		/* _SCRATCH19_0, offset 9C */
+	uint pmc_scratch20;		/* _SCRATCH20_0, offset A0 */
+	uint pmc_scratch21;		/* _SCRATCH21_0, offset A4 */
+	uint pmc_scratch22;		/* _SCRATCH22_0, offset A8 */
+	uint pmc_scratch23;		/* _SCRATCH23_0, offset AC */
+
+	uint pmc_secure_scratch0;	/* _SECURE_SCRATCH0_0, offset B0 */
+	uint pmc_secure_scratch1;	/* _SECURE_SCRATCH1_0, offset B4 */
+	uint pmc_secure_scratch2;	/* _SECURE_SCRATCH2_0, offset B8 */
+	uint pmc_secure_scratch3;	/* _SECURE_SCRATCH3_0, offset BC */
+	uint pmc_secure_scratch4;	/* _SECURE_SCRATCH4_0, offset C0 */
+	uint pmc_secure_scratch5;	/* _SECURE_SCRATCH5_0, offset C4 */
+
+	uint pmc_cpupwrgood_timer;	/* _CPUPWRGOOD_TIMER_0, offset C8 */
+	uint pmc_cpupwroff_timer;	/* _CPUPWROFF_TIMER_0, offset CC */
+	uint pmc_pg_mask;		/* _PG_MASK_0, offset D0 */
+	uint pmc_pg_mask_1;		/* _PG_MASK_1_0, offset D4 */
+	uint pmc_auto_wake_lvl;		/* _AUTO_WAKE_LVL_0, offset D8 */
+	uint pmc_auto_wake_lvl_mask;	/* _AUTO_WAKE_LVL_MASK_0, offset DC */
+	uint pmc_wake_delay;		/* _WAKE_DELAY_0, offset E0 */
+	uint pmc_pwr_det_val;		/* _PWR_DET_VAL_0, offset E4 */
+	uint pmc_ddr_pwr;		/* _DDR_PWR_0, offset E8 */
+	uint pmc_usb_debounce_del;	/* _USB_DEBOUNCE_DEL_0, offset EC */
+	uint pmc_usb_ao;		/* _USB_AO_0, offset F0 */
+	uint pmc_crypto_op;		/* _CRYPTO_OP__0, offset F4 */
+	uint pmc_pllp_wb0_override;	/* _PLLP_WB0_OVERRIDE_0, offset F8 */
+
+	uint pmc_scratch24;		/* _SCRATCH24_0, offset FC */
+	uint pmc_scratch25;		/* _SCRATCH24_0, offset 100 */
+	uint pmc_scratch26;		/* _SCRATCH24_0, offset 104 */
+	uint pmc_scratch27;		/* _SCRATCH24_0, offset 108 */
+	uint pmc_scratch28;		/* _SCRATCH24_0, offset 10C */
+	uint pmc_scratch29;		/* _SCRATCH24_0, offset 110 */
+	uint pmc_scratch30;		/* _SCRATCH24_0, offset 114 */
+	uint pmc_scratch31;		/* _SCRATCH24_0, offset 118 */
+	uint pmc_scratch32;		/* _SCRATCH24_0, offset 11C */
+	uint pmc_scratch33;		/* _SCRATCH24_0, offset 120 */
+	uint pmc_scratch34;		/* _SCRATCH24_0, offset 124 */
+	uint pmc_scratch35;		/* _SCRATCH24_0, offset 128 */
+	uint pmc_scratch36;		/* _SCRATCH24_0, offset 12C */
+	uint pmc_scratch37;		/* _SCRATCH24_0, offset 130 */
+	uint pmc_scratch38;		/* _SCRATCH24_0, offset 134 */
+	uint pmc_scratch39;		/* _SCRATCH24_0, offset 138 */
+	uint pmc_scratch40;		/* _SCRATCH24_0, offset 13C */
+	uint pmc_scratch41;		/* _SCRATCH24_0, offset 140 */
+	uint pmc_scratch42;		/* _SCRATCH24_0, offset 144 */
+
+	uint pmc_bo_mirror0;		/* _BOUNDOUT_MIRROR0_0, offset 148 */
+	uint pmc_bo_mirror1;		/* _BOUNDOUT_MIRROR1_0, offset 14C */
+	uint pmc_bo_mirror2;		/* _BOUNDOUT_MIRROR2_0, offset 150 */
+	uint pmc_sys_33v_en;		/* _SYS_33V_EN_0, offset 154 */
+	uint pmc_bo_mirror_access;	/* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
+	uint pmc_gate;			/* _GATE_0, offset 15C */
+	/* The following fields are in Tegra124 and later only */
+	uint pmc_wake2_mask;		/* _WAKE2_MASK_0, offset 160 */
+	uint pmc_wake2_lvl;		/* _WAKE2_LVL_0,  offset 164 */
+	uint pmc_wake2_stat;		/* _WAKE2_STATUS_0, offset 168 */
+	uint pmc_sw_wake2_stat;		/* _SW_WAKE2_STATUS_0, offset 16C */
+	uint pmc_auto_wake2_lvl_mask;	/* _AUTO_WAKE2_LVL_MASK_0, offset 170 */
+	uint pmc_pg_mask2;		/* _PG_MASK_2_0, offset 174 */
+	uint pmc_pg_mask_ce1;		/* _PG_MASK_CE1_0, offset 178 */
+	uint pmc_pg_mask_ce2;		/* _PG_MASK_CE2_0, offset 17C */
+	uint pmc_pg_mask_ce3;		/* _PG_MASK_CE3_0, offset 180 */
+	uint pmc_pwrgate_timer_ce0;	/* _PWRGATE_TIMER_CE_0_0, offset 184 */
+	uint pmc_pwrgate_timer_ce1;	/* _PWRGATE_TIMER_CE_1_0, offset 188 */
+	uint pmc_pwrgate_timer_ce2;	/* _PWRGATE_TIMER_CE_2_0, offset 18C */
+	uint pmc_pwrgate_timer_ce3;	/* _PWRGATE_TIMER_CE_3_0, offset 190 */
+	uint pmc_pwrgate_timer_ce4;	/* _PWRGATE_TIMER_CE_4_0, offset 194 */
+	uint pmc_pwrgate_timer_ce5;	/* _PWRGATE_TIMER_CE_5_0, offset 198 */
+	uint pmc_pwrgate_timer_ce6;	/* _PWRGATE_TIMER_CE_6_0, offset 19C */
+	uint pmc_pcx_edpd_cntrl;	/* _PCX_EDPD_CNTRL_0, offset 1A0 */
+	uint pmc_osc_edpd_over;		/* _OSC_EDPD_OVER_0, offset 1A4 */
+	uint pmc_clk_out_cntrl;		/* _CLK_OUT_CNTRL_0, offset 1A8 */
+	uint pmc_sata_pwrgate;		/* _SATA_PWRGT_0, offset 1AC */
+	uint pmc_sensor_ctrl;		/* _SENSOR_CTRL_0, offset 1B0 */
+	uint pmc_reset_status;		/* _RTS_STATUS_0, offset 1B4 */
+	uint pmc_io_dpd_req;		/* _IO_DPD_REQ_0, offset 1B8 */
+	uint pmc_io_dpd_stat;		/* _IO_DPD_STATUS_0, offset 1BC */
+	uint pmc_io_dpd2_req;		/* _IO_DPD2_REQ_0, offset 1C0 */
+	uint pmc_io_dpd2_stat;		/* _IO_DPD2_STATUS_0, offset 1C4 */
+	uint pmc_sel_dpd_tim;		/* _SEL_DPD_TIM_0, offset 1C8 */
+	uint pmc_vddp_sel;		/* _VDDP_SEL_0, offset 1CC */
+
+	uint pmc_ddr_cfg;		/* _DDR_CFG_0, offset 1D0 */
+	uint pmc_e_no_vttgen;		/* _E_NO_VTTGEN_0, offset 1D4 */
+	uint pmc_reserved0;		/* _RESERVED, offset 1D8 */
+	uint pmc_pllm_wb0_ovrride_frq;	/* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */
+	uint pmc_test_pwrgate;		/* _TEST_PWRGATE_0, offset 1E0 */
+	uint pmc_pwrgate_timer_mult;	/* _PWRGATE_TIMER_MULT_0, offset 1E4 */
+	uint pmc_dsi_sel_dpd;		/* _DSI_SEL_DPD_0, offset 1E8 */
+	uint pmc_utmip_uhsic_triggers;	/* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */
+	uint pmc_utmip_uhsic_saved_st;  /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */
+	uint pmc_utmip_pad_cfg;		/* _UTMIP_PAD_CFG_0, offset 1F4 */
+	uint pmc_utmip_term_pad_cfg;	/* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */
+	uint pmc_utmip_uhsic_sleep_cfg;	/* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */
+
+	uint pmc_todo_0[9];		/* offset 200-220 */
+	uint pmc_secure_scratch6;	/* _SECURE_SCRATCH6_0, offset 224 */
+	uint pmc_secure_scratch7;	/* _SECURE_SCRATCH7_0, offset 228 */
+	uint pmc_scratch43;		/* _SCRATCH43_0, offset 22C */
+	uint pmc_scratch44;		/* _SCRATCH44_0, offset 230 */
+	uint pmc_scratch45;
+	uint pmc_scratch46;
+	uint pmc_scratch47;
+	uint pmc_scratch48;
+	uint pmc_scratch49;
+	uint pmc_scratch50;
+	uint pmc_scratch51;
+	uint pmc_scratch52;
+	uint pmc_scratch53;
+	uint pmc_scratch54;
+	uint pmc_scratch55;		/* _SCRATCH55_0, offset 25C */
+	uint pmc_scratch0_eco;		/* _SCRATCH0_ECO_0, offset 260 */
+	uint pmc_por_dpd_ctrl;		/* _POR_DPD_CTRL_0, offset 264 */
+	uint pmc_scratch2_eco;		/* _SCRATCH2_ECO_0, offset 268 */
+	uint pmc_todo_1[17];		/* TODO: 26C ~ 2AC */
+	uint pmc_pllm_wb0_override2;	/* _PLLM_WB0_OVERRIDE2, offset 2B0 */
+	uint pmc_tsc_mult;		/* _TSC_MULT_0, offset 2B4 */
+	uint pmc_cpu_vsense_override;	/* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */
+	uint pmc_glb_amap_cfg;		/* _GLB_AMAP_CFG_0, offset 2BC */
+	uint pmc_sticky_bits;		/* _STICKY_BITS_0, offset 2C0 */
+	uint pmc_sec_disable2;		/* _SEC_DISALBE2, offset 2C4 */
+	uint pmc_weak_bias;		/* _WEAK_BIAS_0, offset 2C8 */
+	uint pmc_todo_3[13];		/* TODO: 2CC ~ 2FC */
+	uint pmc_secure_scratch8;	/* _SECURE_SCRATCH8_0, offset 300 */
+	uint pmc_secure_scratch9;
+	uint pmc_secure_scratch10;
+	uint pmc_secure_scratch11;
+	uint pmc_secure_scratch12;
+	uint pmc_secure_scratch13;
+	uint pmc_secure_scratch14;
+	uint pmc_secure_scratch15;
+	uint pmc_secure_scratch16;
+	uint pmc_secure_scratch17;
+	uint pmc_secure_scratch18;
+	uint pmc_secure_scratch19;
+	uint pmc_secure_scratch20;
+	uint pmc_secure_scratch21;
+	uint pmc_secure_scratch22;
+	uint pmc_secure_scratch23;
+	uint pmc_secure_scratch24;	/* _SECURE_SCRATCH24_0, offset 340 */
+	uint pmc_secure_scratch25;
+	uint pmc_secure_scratch26;
+	uint pmc_secure_scratch27;
+	uint pmc_secure_scratch28;
+	uint pmc_secure_scratch29;
+	uint pmc_secure_scratch30;
+	uint pmc_secure_scratch31;
+	uint pmc_secure_scratch32;
+	uint pmc_secure_scratch33;
+	uint pmc_secure_scratch34;
+	uint pmc_secure_scratch35;	/* _SECURE_SCRATCH35_0, offset 36C */
+
+	uint pmc_reserved1[52];		/* RESERVED: 370 ~ 43C */
+	uint pmc_cntrl2;		/* _CNTRL2_0, offset 440 */
+	uint pmc_reserved2[6];		/* RESERVED: 444 ~ 458 */
+	uint pmc_io_dpd3_req;		/* _IO_DPD3_REQ_0, offset 45c */
+	uint pmc_io_dpd3_stat;		/* _IO_DPD3_STATUS_0, offset 460 */
+	uint pmc_strap_opt_a;		/* _STRAPPING_OPT_A_0, offset 464 */
+	uint pmc_reserved3[102];	/* RESERVED: 468 ~ 5FC */
+
+	uint pmc_scratch56;		/* _SCRATCH56_0, offset 600 */
+	uint pmc_scratch57;
+	uint pmc_scratch58;
+	uint pmc_scratch59;
+	uint pmc_scratch60;
+	uint pmc_scratch61;
+	uint pmc_scratch62;
+	uint pmc_scratch63;
+	uint pmc_scratch64;
+	uint pmc_scratch65;
+	uint pmc_scratch66;
+	uint pmc_scratch67;
+	uint pmc_scratch68;
+	uint pmc_scratch69;
+	uint pmc_scratch70;
+	uint pmc_scratch71;
+	uint pmc_scratch72;
+	uint pmc_scratch73;
+	uint pmc_scratch74;
+	uint pmc_scratch75;
+	uint pmc_scratch76;
+	uint pmc_scratch77;
+	uint pmc_scratch78;
+	uint pmc_scratch79;
+	uint pmc_scratch80;
+	uint pmc_scratch81;
+	uint pmc_scratch82;
+	uint pmc_scratch83;
+	uint pmc_scratch84;
+	uint pmc_scratch85;
+	uint pmc_scratch86;
+	uint pmc_scratch87;
+	uint pmc_scratch88;
+	uint pmc_scratch89;
+	uint pmc_scratch90;
+	uint pmc_scratch91;
+	uint pmc_scratch92;
+	uint pmc_scratch93;
+	uint pmc_scratch94;
+	uint pmc_scratch95;
+	uint pmc_scratch96;
+	uint pmc_scratch97;
+	uint pmc_scratch98;
+	uint pmc_scratch99;
+	uint pmc_scratch100;
+	uint pmc_scratch101;
+	uint pmc_scratch102;
+	uint pmc_scratch103;
+	uint pmc_scratch104;
+	uint pmc_scratch105;
+	uint pmc_scratch106;
+	uint pmc_scratch107;
+	uint pmc_scratch108;
+	uint pmc_scratch109;
+	uint pmc_scratch110;
+	uint pmc_scratch111;
+	uint pmc_scratch112;
+	uint pmc_scratch113;
+	uint pmc_scratch114;
+	uint pmc_scratch115;
+	uint pmc_scratch116;
+	uint pmc_scratch117;
+	uint pmc_scratch118;
+	uint pmc_scratch119;
+	uint pmc_scratch1_eco;	/* offset 700 */
+};
+
+#define CPU_PWRED	1
+#define CPU_CLMP	1
+
+#define PARTID_CP	0xFFFFFFF8
+#define START_CP	(1 << 8)
+
+#define CPUPWRREQ_OE	(1 << 16)
+#define CPUPWRREQ_POL	(1 << 15)
+
+#define CRAIL		0
+#define CE0		14
+#define C0NC		15
+#define SOR		17
+
+#define PMC_XOFS_SHIFT	1
+#define PMC_XOFS_MASK	(0x3F << PMC_XOFS_SHIFT)
+
+#if defined(CONFIG_TEGRA114)
+#define TIMER_MULT_SHIFT	0
+#define TIMER_MULT_MASK		(3 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT	2
+#define TIMER_MULT_CPU_MASK	(3 << TIMER_MULT_CPU_SHIFT)
+#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
+#define TIMER_MULT_SHIFT	0
+#define TIMER_MULT_MASK		(7 << TIMER_MULT_SHIFT)
+#define TIMER_MULT_CPU_SHIFT	3
+#define TIMER_MULT_CPU_MASK	(7 << TIMER_MULT_CPU_SHIFT)
+#endif
+
+#define MULT_1			0
+#define MULT_2			1
+#define MULT_4			2
+#define MULT_8			3
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
+#define MULT_16			4
+#endif
+
+#define AMAP_WRITE_SHIFT	20
+#define AMAP_WRITE_ON		(1 << AMAP_WRITE_SHIFT)
+
+/* SEC_DISABLE_0, 0x04 */
+#define SEC_DISABLE_WRITE0_ON			(1 << 4)
+#define SEC_DISABLE_READ0_ON			(1 << 5)
+#define SEC_DISABLE_WRITE1_ON			(1 << 6)
+#define SEC_DISABLE_READ1_ON			(1 << 7)
+#define SEC_DISABLE_WRITE2_ON			(1 << 8)
+#define SEC_DISABLE_READ2_ON			(1 << 9)
+#define SEC_DISABLE_WRITE3_ON			(1 << 10)
+#define SEC_DISABLE_READ3_ON			(1 << 11)
+#define SEC_DISABLE_AMAP_WRITE_ON		(1 << 20)
+
+/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */
+#define PWRGATE_TOGGLE_PARTID_CRAIL		0
+#define PWRGATE_TOGGLE_PARTID_TD		1
+#define PWRGATE_TOGGLE_PARTID_VE		2
+#define PWRGATE_TOGGLE_PARTID_PCX		3
+#define PWRGATE_TOGGLE_PARTID_VDE		4
+#define PWRGATE_TOGGLE_PARTID_L2C		5
+#define PWRGATE_TOGGLE_PARTID_MPE		6
+#define PWRGATE_TOGGLE_PARTID_HEG		7
+#define PWRGATE_TOGGLE_PARTID_SAX		8
+#define PWRGATE_TOGGLE_PARTID_CE1		9
+#define PWRGATE_TOGGLE_PARTID_CE2		10
+#define PWRGATE_TOGGLE_PARTID_CE3		11
+#define PWRGATE_TOGGLE_PARTID_CELP		12
+#define PWRGATE_TOGGLE_PARTID_CE0		14
+#define PWRGATE_TOGGLE_PARTID_C0NC		15
+#define PWRGATE_TOGGLE_PARTID_C1NC		16
+#define PWRGATE_TOGGLE_PARTID_SOR		17
+#define PWRGATE_TOGGLE_PARTID_DIS		18
+#define PWRGATE_TOGGLE_PARTID_DISB		19
+#define PWRGATE_TOGGLE_PARTID_XUSBA		20
+#define PWRGATE_TOGGLE_PARTID_XUSBB		21
+#define PWRGATE_TOGGLE_PARTID_XUSBC		22
+#define PWRGATE_TOGGLE_PARTID_VIC		23
+#define PWRGATE_TOGGLE_PARTID_IRAM		24
+#define PWRGATE_TOGGLE_START			(1 << 8)
+
+/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */
+#define PWRGATE_STATUS_CRAIL_ENABLE		(1 << 0)
+#define PWRGATE_STATUS_TD_ENABLE		(1 << 1)
+#define PWRGATE_STATUS_VE_ENABLE		(1 << 2)
+#define PWRGATE_STATUS_PCX_ENABLE		(1 << 3)
+#define PWRGATE_STATUS_VDE_ENABLE		(1 << 4)
+#define PWRGATE_STATUS_L2C_ENABLE		(1 << 5)
+#define PWRGATE_STATUS_MPE_ENABLE		(1 << 6)
+#define PWRGATE_STATUS_HEG_ENABLE		(1 << 7)
+#define PWRGATE_STATUS_SAX_ENABLE		(1 << 8)
+#define PWRGATE_STATUS_CE1_ENABLE		(1 << 9)
+#define PWRGATE_STATUS_CE2_ENABLE		(1 << 10)
+#define PWRGATE_STATUS_CE3_ENABLE		(1 << 11)
+#define PWRGATE_STATUS_CELP_ENABLE		(1 << 12)
+#define PWRGATE_STATUS_CE0_ENABLE		(1 << 14)
+#define PWRGATE_STATUS_C0NC_ENABLE		(1 << 15)
+#define PWRGATE_STATUS_C1NC_ENABLE		(1 << 16)
+#define PWRGATE_STATUS_SOR_ENABLE		(1 << 17)
+#define PWRGATE_STATUS_DIS_ENABLE		(1 << 18)
+#define PWRGATE_STATUS_DISB_ENABLE		(1 << 19)
+#define PWRGATE_STATUS_XUSBA_ENABLE		(1 << 20)
+#define PWRGATE_STATUS_XUSBB_ENABLE		(1 << 21)
+#define PWRGATE_STATUS_XUSBC_ENABLE		(1 << 22)
+#define PWRGATE_STATUS_VIC_ENABLE		(1 << 23)
+#define PWRGATE_STATUS_IRAM_ENABLE		(1 << 24)
+
+/* APBDEV_PMC_CNTRL2_0 0x440 */
+#define HOLD_CKE_LOW_EN				(1 << 12)
+
+/* PMC read/write functions */
+u32 tegra_pmc_readl(unsigned long offset);
+void tegra_pmc_writel(u32 value, unsigned long offset);
+
+#define PMC_CNTRL		0x0
+#define  PMC_CNTRL_MAIN_RST	BIT(4)
+
+#if IS_ENABLED(CONFIG_TEGRA186)
+#  define PMC_SCRATCH0 0x32000
+#else
+#  define PMC_SCRATCH0 0x00050
+#endif
+
+/* for secure PMC */
+#define TEGRA_SMC_PMC		0xc2fffe00
+#define  TEGRA_SMC_PMC_READ	0xaa
+#define  TEGRA_SMC_PMC_WRITE	0xbb
+
+#endif	/* PMC_H */
diff --git a/arch/arm/include/asm/arch-tegra/pmu.h b/arch/arm/include/asm/arch-tegra/pmu.h
new file mode 100644
index 0000000..e850875
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/pmu.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_PMU_H_
+#define _TEGRA_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif	/* _TEGRA_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/powergate.h b/arch/arm/include/asm/arch-tegra/powergate.h
new file mode 100644
index 0000000..2e491f1
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/powergate.h
@@ -0,0 +1,39 @@
+#ifndef _TEGRA_POWERGATE_H_
+#define _TEGRA_POWERGATE_H_
+
+#include <asm/arch/clock.h>
+
+enum tegra_powergate {
+	TEGRA_POWERGATE_CPU,
+	TEGRA_POWERGATE_3D,
+	TEGRA_POWERGATE_VENC,
+	TEGRA_POWERGATE_PCIE,
+	TEGRA_POWERGATE_VDEC,
+	TEGRA_POWERGATE_L2,
+	TEGRA_POWERGATE_MPE,
+	TEGRA_POWERGATE_HEG,
+	TEGRA_POWERGATE_SATA,
+	TEGRA_POWERGATE_CPU1,
+	TEGRA_POWERGATE_CPU2,
+	TEGRA_POWERGATE_CPU3,
+	TEGRA_POWERGATE_CELP,
+	TEGRA_POWERGATE_3D1,
+	TEGRA_POWERGATE_CPU0,
+	TEGRA_POWERGATE_C0NC,
+	TEGRA_POWERGATE_C1NC,
+	TEGRA_POWERGATE_SOR,
+	TEGRA_POWERGATE_DIS,
+	TEGRA_POWERGATE_DISB,
+	TEGRA_POWERGATE_XUSBA,
+	TEGRA_POWERGATE_XUSBB,
+	TEGRA_POWERGATE_XUSBC,
+	TEGRA_POWERGATE_VIC,
+	TEGRA_POWERGATE_IRAM,
+};
+
+int tegra_powergate_sequence_power_up(enum tegra_powergate id,
+				      enum periph_id periph);
+int tegra_powergate_power_on(enum tegra_powergate id);
+int tegra_powergate_power_off(enum tegra_powergate id);
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/pwm.h b/arch/arm/include/asm/arch-tegra/pwm.h
new file mode 100644
index 0000000..eebd104
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/pwm.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_ARCH_TEGRA_PWM_H
+#define __ASM_ARCH_TEGRA_PWM_H
+
+/* This is a single PWM channel */
+struct pwm_ctlr {
+	uint control;		/* Control register */
+	uint reserved[3];	/* Space space */
+};
+
+#define PWM_NUM_CHANNELS	4
+
+/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
+#define PWM_ENABLE_SHIFT	31
+#define PWM_ENABLE_MASK	(0x1 << PWM_ENABLE_SHIFT)
+
+#define PWM_WIDTH_SHIFT	16
+#define PWM_WIDTH_MASK		(0x7FFF << PWM_WIDTH_SHIFT)
+
+#define PWM_DIVIDER_SHIFT	0
+#define PWM_DIVIDER_MASK	(0x1FFF << PWM_DIVIDER_SHIFT)
+
+#endif	/* __ASM_ARCH_TEGRA_PWM_H */
diff --git a/arch/arm/include/asm/arch-tegra/scu.h b/arch/arm/include/asm/arch-tegra/scu.h
new file mode 100644
index 0000000..afe0764
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/scu.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _SCU_H_
+#define _SCU_H_
+
+/* ARM Snoop Control Unit (SCU) registers */
+struct scu_ctlr {
+	uint scu_ctrl;		/* SCU Control Register, offset 00 */
+	uint scu_cfg;		/* SCU Config Register, offset 04 */
+	uint scu_cpu_pwr_stat;	/* SCU CPU Power Status Register, offset 08 */
+	uint scu_inv_all;	/* SCU Invalidate All Register, offset 0C */
+	uint scu_reserved0[12];	/* reserved, offset 10-3C */
+	uint scu_filt_start;	/* SCU Filtering Start Address Reg, offset 40 */
+	uint scu_filt_end;	/* SCU Filtering End Address Reg, offset 44 */
+	uint scu_reserved1[2];	/* reserved, offset 48-4C */
+	uint scu_acc_ctl;	/* SCU Access Control Register, offset 50 */
+	uint scu_ns_acc_ctl;	/* SCU Non-secure Access Cntrl Reg, offset 54 */
+};
+
+#define SCU_CTRL_ENABLE		(1 << 0)
+
+#endif	/* SCU_H */
diff --git a/arch/arm/include/asm/arch-tegra/sys_proto.h b/arch/arm/include/asm/arch-tegra/sys_proto.h
new file mode 100644
index 0000000..62e1c7b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/sys_proto.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+void invalidate_dcache(void);
+
+/**
+ * tegra_board_id() - Get the board iD
+ *
+ * @return a board ID, or -ve on error
+ */
+int tegra_board_id(void);
+
+/**
+ * tegra_lcd_pmic_init() - Set up the PMIC for a board
+ *
+ * @board_id: Board ID which may be used to select LCD type
+ * @return 0 if OK, -ve on error
+ */
+int tegra_lcd_pmic_init(int board_id);
+
+/**
+ * nvidia_board_init() - perform any board-specific init
+ *
+ * @return 0 if OK, -ve on error
+ */
+int nvidia_board_init(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
new file mode 100644
index 0000000..7a4e097
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_H_
+#define _TEGRA_H_
+
+#define NV_PA_ARM_PERIPHBASE	0x50040000
+#define NV_PA_PG_UP_BASE	0x60000000
+#define NV_PA_TMRUS_BASE	0x60005010
+#define NV_PA_CLK_RST_BASE	0x60006000
+#define NV_PA_FLOW_BASE		0x60007000
+#define NV_PA_GPIO_BASE		0x6000D000
+#define NV_PA_EVP_BASE		0x6000F000
+#define NV_PA_APB_MISC_BASE	0x70000000
+#define NV_PA_APB_MISC_GP_BASE	(NV_PA_APB_MISC_BASE + 0x0800)
+#define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
+#define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
+#define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
+#define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
+#define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
+#define NV_PA_NAND_BASE		(NV_PA_APB_MISC_BASE + 0x8000)
+#define NV_PA_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_SLINK1_BASE	(NV_PA_APB_MISC_BASE + 0xD400)
+#define NV_PA_SLINK2_BASE	(NV_PA_APB_MISC_BASE + 0xD600)
+#define NV_PA_SLINK3_BASE	(NV_PA_APB_MISC_BASE + 0xD800)
+#define NV_PA_SLINK4_BASE	(NV_PA_APB_MISC_BASE + 0xDA00)
+#define NV_PA_SLINK5_BASE	(NV_PA_APB_MISC_BASE + 0xDC00)
+#define NV_PA_SLINK6_BASE	(NV_PA_APB_MISC_BASE + 0xDE00)
+#define TEGRA_DVC_BASE		(NV_PA_APB_MISC_BASE + 0xD000)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+	defined(CONFIG_TEGRA114) || defined(CONFIG_TEGRA124) || \
+	defined(CONFIG_TEGRA132) || defined(CONFIG_TEGRA210)
+#define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
+#else
+#define NV_PA_PMC_BASE		0xc360000
+#endif
+#define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
+#define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
+	defined(CONFIG_TEGRA114)
+#define NV_PA_CSITE_BASE	0x70040000
+#else
+#define NV_PA_CSITE_BASE	0x70800000
+#endif
+#define TEGRA_USB_ADDR_MASK	0xFFFFC000
+
+#define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
+#define LOW_LEVEL_SRAM_STACK	0x4000FFFC
+#define EARLY_AVP_STACK		(NV_PA_SDRAM_BASE + 0x20000)
+#define EARLY_CPU_STACK		(EARLY_AVP_STACK - 4096)
+#define PG_UP_TAG_AVP		0xAAAAAAAA
+
+#ifndef __ASSEMBLY__
+struct timerus {
+	unsigned int cntr_1us;
+};
+
+/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
+#define NV_WB_RUN_ADDRESS	0x40020000
+
+#define NVBOOTTYPE_RECOVERY	2	/* BR entered RCM */
+#define NVBOOTINFOTABLE_BOOTTYPE 0xC	/* Boot type in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTSIZE	0x38	/* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR	0x3C	/* BCT pointer in BIT in IRAM */
+
+/* These are the available SKUs (product types) for Tegra */
+enum {
+	SKU_ID_T20_7		= 0x7,
+	SKU_ID_T20		= 0x8,
+	SKU_ID_T25SE		= 0x14,
+	SKU_ID_AP25		= 0x17,
+	SKU_ID_T25		= 0x18,
+	SKU_ID_AP25E		= 0x1b,
+	SKU_ID_T25E		= 0x1c,
+	SKU_ID_T33		= 0x80,
+	SKU_ID_T30		= 0x81, /* Cardhu value */
+	SKU_ID_TM30MQS_P_A3	= 0xb1,
+	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
+	SKU_ID_T114_1		= 0x01,
+	SKU_ID_T124_ENG		= 0x00, /* Venice2 value, unfused */
+	SKU_ID_T210_ENG		= 0x00, /* unfused value TBD */
+};
+
+/*
+ * These are used to distinguish SOC types for setting up clocks. Mostly
+ * we can tell the clocking required by looking at the SOC sku_id, but
+ * for T30 it is a user option as to whether to run PLLP in fast or slow
+ * mode, so we have two options there.
+ */
+enum {
+	TEGRA_SOC_T20,
+	TEGRA_SOC_T25,
+	TEGRA_SOC_T30,
+	TEGRA_SOC_T114,
+	TEGRA_SOC_T124,
+	TEGRA_SOC_T210,
+
+	TEGRA_SOC_CNT,
+	TEGRA_SOC_UNKNOWN	= -1,
+};
+
+/* Tegra system controller (SYSCON) devices */
+enum {
+	TEGRA_SYSCON_PMC,
+};
+
+#else  /* __ASSEMBLY__ */
+#define PRM_RSTCTRL		NV_PA_PMC_BASE
+#endif
+
+#endif	/* TEGRA_H */
diff --git a/arch/arm/include/asm/arch-tegra/tegra_ahub.h b/arch/arm/include/asm/arch-tegra/tegra_ahub.h
new file mode 100644
index 0000000..96d542a
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/tegra_ahub.h
@@ -0,0 +1,475 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * tegra_ahub.h - Definitions for Tegra124 audio hub driver
+ * Taken from dc tegra_ahub.h
+ *
+ * Copyright 2018 Google LLC
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA_AHUB_H_
+#define _TEGRA_AHUB_H_
+
+/*
+ * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio
+ * transmitted by a particular TX CIF.
+ */
+struct xbar_regs {
+	u32 apbif_rx0;		/* AUDIO_APBIF_RX0, offset 0x00 */
+	u32 apbif_rx1;		/* AUDIO_APBIF_RX1, offset 0x04 */
+	u32 apbif_rx2;		/* AUDIO_APBIF_RX2, offset 0x08 */
+	u32 apbif_rx3;		/* AUDIO_APBIF_RX3, offset 0x0C */
+
+	u32 i2s0_rx0;		/* AUDIO_I2S0_RX0,  offset 0x10 */
+	u32 i2s1_rx0;		/* AUDIO_I2S1_RX0,  offset 0x14 */
+	u32 i2s2_rx0;		/* AUDIO_I2S2_RX0,  offset 0x18 */
+	u32 i2s3_rx0;		/* AUDIO_I2S3_RX0,  offset 0x1C */
+	u32 i2s4_rx0;		/* AUDIO_I2S4_RX0,  offset 0x20 */
+
+	u32 dam0_rx0;		/* AUDIO_DAM0_RX0,  offset 0x24 */
+	u32 dam0_rx1;		/* AUDIO_DAM0_RX1,  offset 0x28 */
+	u32 dam1_rx0;		/* AUDIO_DAM1_RX0,  offset 0x2C */
+	u32 dam1_rx1;		/* AUDIO_DAM1_RX1,  offset 0x30 */
+	u32 dam2_rx0;		/* AUDIO_DAM2_RX0,  offset 0x34 */
+	u32 dam2_rx1;		/* AUDIO_DAM2_RX1,  offset 0x38 */
+
+	u32 spdif_rx0;		/* AUDIO_SPDIF_RX0, offset 0x3C */
+	u32 spdif_rx1;		/* AUDIO_SPDIF_RX1, offset 0x40 */
+
+	u32 apbif_rx4;		/* AUDIO_APBIF_RX4, offset 0x44 */
+	u32 apbif_rx5;		/* AUDIO_APBIF_RX4, offset 0x48 */
+	u32 apbif_rx6;		/* AUDIO_APBIF_RX4, offset 0x4C */
+	u32 apbif_rx7;		/* AUDIO_APBIF_RX4, offset 0x50 */
+	u32 apbif_rx8;		/* AUDIO_APBIF_RX4, offset 0x54 */
+	u32 apbif_rx9;		/* AUDIO_APBIF_RX4, offset 0x58 */
+
+	u32 amx0_rx0;		/* AUDIO_AMX0_RX0,  offset 0x5C */
+	u32 amx0_rx1;		/* AUDIO_AMX0_RX1,  offset 0x60 */
+	u32 amx0_rx2;		/* AUDIO_AMX0_RX2,  offset 0x64 */
+	u32 amx0_rx3;		/* AUDIO_AMX0_RX3,  offset 0x68 */
+
+	u32 adx0_rx0;		/* AUDIO_ADX0_RX0,  offset 0x6C */
+};
+
+struct apbif_regs {
+	u32 channel0_ctrl;		/* APBIF_CHANNEL0_CTRL */
+	u32 channel0_clr;		/* APBIF_CHANNEL0_CLEAR */
+	u32 channel0_stat;		/* APBIF_CHANNEL0_STATUS */
+	u32 channel0_txfifo;		/* APBIF_CHANNEL0_TXFIFO */
+	u32 channel0_rxfifo;		/* APBIF_CHANNEL0_RXFIFO */
+	u32 channel0_cif_tx0_ctrl;	/* APBIF_AUDIOCIF_TX0_CTRL */
+	u32 channel0_cif_rx0_ctrl;	/* APBIF_AUDIOCIF_RX0_CTRL */
+	u32 channel0_reserved0;		/* RESERVED, offset 0x1C */
+	/* ahub_channel1_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+	/* ahub_channel2_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+	/* ahub_channel3_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */
+	u32 reserved123[3 * 8];
+	u32 config_link_ctrl;		/* APBIF_CONFIG_LINK_CTRL_0, off 0x80 */
+	u32 misc_ctrl;			/* APBIF_MISC_CTRL_0, offset 0x84 */
+	u32 apbdma_live_stat;		/* APBIF_APBDMA_LIVE_STATUS_0 */
+	u32 i2s_live_stat;		/* APBIF_I2S_LIVE_STATUS_0 */
+	u32 dam0_live_stat;		/* APBIF_DAM0_LIVE_STATUS_0 */
+	u32 dam1_live_stat;		/* APBIF_DAM0_LIVE_STATUS_0 */
+	u32 dam2_live_stat;		/* APBIF_DAM0_LIVE_STATUS_0 */
+	u32 spdif_live_stat;		/* APBIF_SPDIF_LIVE_STATUS_0 */
+	u32 i2s_int_mask;		/* APBIF_I2S_INT_MASK_0, offset B0 */
+	u32 dam_int_mask;		/* APBIF_DAM_INT_MASK_0 */
+	u32 reserved_int_mask;		/* RESERVED, offset 0xB8 */
+	u32 spdif_int_mask;		/* APBIF_SPDIF_INT_MASK_0 */
+	u32 apbif_int_mask;		/* APBIF_APBIF_INT_MASK_0, off C0 */
+	u32 reserved2_int_mask;		/* RESERVED, offset 0xC4 */
+	u32 i2s_int_stat;		/* APBIF_I2S_INT_STATUS_0, offset C8 */
+	u32 dam_int_stat;		/* APBIF_DAM_INT_STATUS_0 */
+	u32 reserved_int_stat;		/* RESERVED, offset 0xD0 */
+	u32 spdif_int_stat;		/* APBIF_SPDIF_INT_STATUS_0 */
+	u32 apbif_int_stat;		/* APBIF_APBIF_INT_STATUS_0 */
+	u32 reserved2_int_stat;		/* RESERVED, offset 0xDC */
+	u32 i2s_int_src;		/* APBIF_I2S_INT_SOURCE_0, offset E0 */
+	u32 dam_int_src;		/* APBIF_DAM_INT_SOURCE_0 */
+	u32 reserved_int_src;		/* RESERVED, offset 0xE8 */
+	u32 spdif_int_src;		/* APBIF_SPDIF_INT_SOURCE_0 */
+	u32 apbif_int_src;		/* APBIF_APBIF_INT_SOURCE_0, off F0 */
+	u32 reserved2_int_src;		/* RESERVED, offset 0xF4 */
+	u32 i2s_int_set;		/* APBIF_I2S_INT_SET_0, offset 0xF8 */
+	u32 dam_int_set;		/* APBIF_DAM_INT_SET_0, offset 0xFC */
+	u32 spdif_int_set;		/* APBIF_SPDIF_INT_SET_0, off 0x100 */
+	u32 apbif_int_set;		/* APBIF_APBIF_INT_SET_0, off 0x104 */
+};
+
+/*
+ * Tegra AHUB Registers Definition
+ */
+enum {
+	TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT = 24,
+	TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US = 0x3f,
+	TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK =
+			TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US <<
+			TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT,
+
+	/* Channel count minus 1 */
+	TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT = 20,
+	TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US = 0xf,
+	TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK =
+			TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US <<
+			TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT,
+
+	/* Channel count minus 1 */
+	TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT = 16,
+	TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US = 0xf,
+	TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK =
+			TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US <<
+			TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT,
+
+	TEGRA_AUDIOCIF_BITS_4 = 0,
+	TEGRA_AUDIOCIF_BITS_8 = 1,
+	TEGRA_AUDIOCIF_BITS_12 = 2,
+	TEGRA_AUDIOCIF_BITS_16 = 3,
+	TEGRA_AUDIOCIF_BITS_20 = 4,
+	TEGRA_AUDIOCIF_BITS_24 = 5,
+	TEGRA_AUDIOCIF_BITS_28 = 6,
+	TEGRA_AUDIOCIF_BITS_32 = 7,
+
+	TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT = 12,
+	TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_MASK =
+		7 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_4 =
+		TEGRA_AUDIOCIF_BITS_4  << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_8 =
+		TEGRA_AUDIOCIF_BITS_8  << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_12 =
+		TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_16 =
+		TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_20 =
+		TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_24 =
+		TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_28 =
+		TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_32 =
+		TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT,
+
+	TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT = 8,
+	TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_MASK =
+		7 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_4 =
+		TEGRA_AUDIOCIF_BITS_4  << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_8 =
+		TEGRA_AUDIOCIF_BITS_8  << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_12 =
+		TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_16 =
+		TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_20 =
+		TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_24 =
+		TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_28 =
+		TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_32 =
+		TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT,
+
+	TEGRA_AUDIOCIF_EXPAND_ZERO = 0,
+	TEGRA_AUDIOCIF_EXPAND_ONE = 1,
+	TEGRA_AUDIOCIF_EXPAND_LFSR = 2,
+
+	TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT = 6,
+	TEGRA_AUDIOCIF_CTRL_EXPAND_MASK = 3 << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_EXPAND_ZERO =
+		TEGRA_AUDIOCIF_EXPAND_ZERO << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_EXPAND_ONE =
+		TEGRA_AUDIOCIF_EXPAND_ONE  << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_EXPAND_LFSR =
+		TEGRA_AUDIOCIF_EXPAND_LFSR << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT,
+
+	TEGRA_AUDIOCIF_STEREO_CONV_CH0 = 0,
+	TEGRA_AUDIOCIF_STEREO_CONV_CH1 = 1,
+	TEGRA_AUDIOCIF_STEREO_CONV_AVG = 2,
+
+	TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT = 4,
+	TEGRA_AUDIOCIF_CTRL_STEREO_CONV_MASK =
+			3 << TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH0 =
+			TEGRA_AUDIOCIF_STEREO_CONV_CH0 <<
+			TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH1 =
+			TEGRA_AUDIOCIF_STEREO_CONV_CH1 <<
+			TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_STEREO_CONV_AVG =
+			TEGRA_AUDIOCIF_STEREO_CONV_AVG <<
+			TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT,
+
+	TEGRA_AUDIOCIF_CTRL_REPLICATE = 3,
+
+	TEGRA_AUDIOCIF_DIRECTION_TX = 0,
+	TEGRA_AUDIOCIF_DIRECTION_RX = 1,
+
+	TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT = 2,
+	TEGRA_AUDIOCIF_CTRL_DIRECTION_MASK =
+			1 << TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_DIRECTION_TX =
+			TEGRA_AUDIOCIF_DIRECTION_TX <<
+			TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_DIRECTION_RX =
+			TEGRA_AUDIOCIF_DIRECTION_RX <<
+			TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT,
+
+	TEGRA_AUDIOCIF_TRUNCATE_ROUND = 0,
+	TEGRA_AUDIOCIF_TRUNCATE_CHOP = 1,
+
+	TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT = 1,
+	TEGRA_AUDIOCIF_CTRL_TRUNCATE_MASK =
+			1 << TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_TRUNCATE_ROUND =
+			TEGRA_AUDIOCIF_TRUNCATE_ROUND <<
+			TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_TRUNCATE_CHOP =
+			TEGRA_AUDIOCIF_TRUNCATE_CHOP  <<
+			TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT,
+
+	TEGRA_AUDIOCIF_MONO_CONV_ZERO = 0,
+	TEGRA_AUDIOCIF_MONO_CONV_COPY = 1,
+
+	TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT = 0,
+	TEGRA_AUDIOCIF_CTRL_MONO_CONV_MASK =
+			1 << TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_MONO_CONV_ZERO =
+			TEGRA_AUDIOCIF_MONO_CONV_ZERO <<
+			TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT,
+	TEGRA_AUDIOCIF_CTRL_MONO_CONV_COPY =
+			TEGRA_AUDIOCIF_MONO_CONV_COPY <<
+			TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT,
+
+	/* Registers within TEGRA_AUDIO_CLUSTER_BASE */
+
+	TEGRA_AHUB_CHANNEL_CTRL = 0x0,
+	TEGRA_AHUB_CHANNEL_CTRL_STRIDE = 0x20,
+	TEGRA_AHUB_CHANNEL_CTRL_COUNT = 4,
+	TEGRA_AHUB_CHANNEL_CTRL_TX_EN = 1 << 31,
+	TEGRA_AHUB_CHANNEL_CTRL_RX_EN = 1 << 30,
+	TEGRA_AHUB_CHANNEL_CTRL_LOOPBACK = 1 << 29,
+
+	TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT = 16,
+	TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US = 0xff,
+	TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK =
+			TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US <<
+			TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT,
+
+	TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT = 8,
+	TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US = 0xff,
+	TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK =
+			TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US <<
+			TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT,
+
+	TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN = 1 << 6,
+
+	TEGRA_PACK_8_4 = 2,
+	TEGRA_PACK_16 = 3,
+
+	TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT = 4,
+	TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US = 3,
+	TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK =
+		TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US <<
+		TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT,
+	TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_8_4 =
+		TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT,
+	TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 =
+		TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT,
+
+	TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_EN = 1 << 2,
+
+	TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT = 0,
+	TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US = 3,
+	TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK =
+		TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US <<
+		TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT,
+	TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_8_4 =
+		TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT,
+	TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_16 =
+		TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT,
+
+	/* TEGRA_AHUB_CHANNEL_CLEAR */
+
+	TEGRA_AHUB_CHANNEL_CLEAR = 0x4,
+	TEGRA_AHUB_CHANNEL_CLEAR_STRIDE = 0x20,
+	TEGRA_AHUB_CHANNEL_CLEAR_COUNT = 4,
+	TEGRA_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET = 1 << 31,
+	TEGRA_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET = 1 << 30,
+
+	TEGRA_AHUB_CHANNEL_STATUS = 0x8,
+	TEGRA_AHUB_CHANNEL_STATUS_STRIDE = 0x20,
+	TEGRA_AHUB_CHANNEL_STATUS_COUNT = 4,
+	TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT = 24,
+	TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US = 0xff,
+	TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK =
+			TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US <<
+			TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT,
+	TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT = 16,
+	TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US = 0xff,
+	TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK =
+			TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US <<
+			TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT,
+	TEGRA_AHUB_CHANNEL_STATUS_TX_TRIG = 1 << 1,
+	TEGRA_AHUB_CHANNEL_STATUS_RX_TRIG = 1 << 0,
+
+	TEGRA_AHUB_CHANNEL_TXFIFO = 0xc,
+	TEGRA_AHUB_CHANNEL_TXFIFO_STRIDE = 0x20,
+	TEGRA_AHUB_CHANNEL_TXFIFO_COUNT = 4,
+
+	TEGRA_AHUB_CHANNEL_RXFIFO = 0x10,
+	TEGRA_AHUB_CHANNEL_RXFIFO_STRIDE = 0x20,
+	TEGRA_AHUB_CHANNEL_RXFIFO_COUNT = 4,
+
+	TEGRA_AHUB_CIF_TX_CTRL = 0x14,
+	TEGRA_AHUB_CIF_TX_CTRL_STRIDE = 0x20,
+	TEGRA_AHUB_CIF_TX_CTRL_COUNT = 4,
+	/* Uses field from TEGRA_AUDIOCIF_CTRL_* */
+
+	TEGRA_AHUB_CIF_RX_CTRL = 0x18,
+	TEGRA_AHUB_CIF_RX_CTRL_STRIDE = 0x20,
+	TEGRA_AHUB_CIF_RX_CTRL_COUNT = 4,
+	/* Uses field from TEGRA_AUDIOCIF_CTRL_* */
+
+	TEGRA_AHUB_CONFIG_LINK_CTRL = 0x80,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT = 28,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US = 0xf,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK =
+		TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US <<
+		TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT = 16,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US = 0xfff,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK =
+		TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US <<
+		TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT = 4,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US = 0xfff,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK =
+		TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US <<
+		TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_CG_EN = 1 << 2,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR = 1 << 1,
+	TEGRA_AHUB_CONFIG_LINK_CTRL_SOFT_RESET = 1 << 0,
+
+	TEGRA_AHUB_MISC_CTRL = 0x84,
+	TEGRA_AHUB_MISC_CTRL_AUDIO_ACTIVE = 1 << 31,
+	TEGRA_AHUB_MISC_CTRL_AUDIO_CG_EN = 1 << 8,
+	TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT = 0,
+	TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK =
+			0x1f << TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT,
+
+	TEGRA_AHUB_APBDMA_LIVE_STATUS = 0x88,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL = 1 << 31,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL = 1 << 30,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL = 1 << 29,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL = 1 << 28,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL = 1 << 27,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL = 1 << 26,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL = 1 << 25,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL = 1 << 24,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY = 1 << 23,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY = 1 << 22,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY = 1 << 21,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY = 1 << 20,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY = 1 << 19,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY = 1 << 18,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY = 1 << 17,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY = 1 << 16,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL = 1 << 15,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL = 1 << 14,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL = 1 << 13,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL = 1 << 12,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL = 1 << 11,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL = 1 << 10,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL = 1 << 9,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL = 1 << 8,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY = 1 << 7,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY = 1 << 6,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY = 1 << 5,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY = 1 << 4,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY = 1 << 3,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY = 1 << 2,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY = 1 << 1,
+	TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY = 1 << 0,
+
+	TEGRA_AHUB_I2S_LIVE_STATUS = 0x8c,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL = 1 << 29,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL = 1 << 28,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL = 1 << 27,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL = 1 << 26,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL = 1 << 25,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL = 1 << 24,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL = 1 << 23,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL = 1 << 22,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL = 1 << 21,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL = 1 << 20,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED = 1 << 19,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED = 1 << 18,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED = 1 << 17,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED = 1 << 16,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED = 1 << 15,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED = 1 << 14,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED = 1 << 13,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED = 1 << 12,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED = 1 << 11,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED = 1 << 10,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY = 1 << 9,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY = 1 << 8,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY = 1 << 7,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY = 1 << 6,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY = 1 << 5,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY = 1 << 4,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY = 1 << 3,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY = 1 << 2,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY = 1 << 1,
+	TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY = 1 << 0,
+
+	TEGRA_AHUB_DAM_LIVE_STATUS = 0x90,
+	TEGRA_AHUB_DAM_LIVE_STATUS_STRIDE = 0x8,
+	TEGRA_AHUB_DAM_LIVE_STATUS_COUNT = 3,
+	TEGRA_AHUB_DAM_LIVE_STATUS_TX_ENABLED = 1 << 26,
+	TEGRA_AHUB_DAM_LIVE_STATUS_RX1_ENABLED = 1 << 25,
+	TEGRA_AHUB_DAM_LIVE_STATUS_RX0_ENABLED = 1 << 24,
+	TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL = 1 << 15,
+	TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL = 1 << 9,
+	TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL = 1 << 8,
+	TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY = 1 << 7,
+	TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY = 1 << 1,
+	TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY = 1 << 0,
+
+	TEGRA_AHUB_SPDIF_LIVE_STATUS = 0xa8,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED = 1 << 11,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED = 1 << 10,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED = 1 << 9,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED = 1 << 8,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL = 1 << 7,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL = 1 << 6,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL = 1 << 5,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL = 1 << 4,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY = 1 << 3,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY = 1 << 2,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY = 1 << 1,
+	TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY = 1 << 0,
+
+	TEGRA_AHUB_I2S_INT_MASK = 0xb0,
+	TEGRA_AHUB_DAM_INT_MASK = 0xb4,
+	TEGRA_AHUB_SPDIF_INT_MASK = 0xbc,
+	TEGRA_AHUB_APBIF_INT_MASK = 0xc0,
+	TEGRA_AHUB_I2S_INT_STATUS = 0xc8,
+	TEGRA_AHUB_DAM_INT_STATUS = 0xcc,
+	TEGRA_AHUB_SPDIF_INT_STATUS = 0xd4,
+	TEGRA_AHUB_APBIF_INT_STATUS = 0xd8,
+	TEGRA_AHUB_I2S_INT_SOURCE = 0xe0,
+	TEGRA_AHUB_DAM_INT_SOURCE = 0xe4,
+	TEGRA_AHUB_SPDIF_INT_SOURCE = 0xec,
+	TEGRA_AHUB_APBIF_INT_SOURCE = 0xf0,
+	TEGRA_AHUB_I2S_INT_SET = 0xf8,
+	TEGRA_AHUB_DAM_INT_SET = 0xfc,
+	TEGRA_AHUB_SPDIF_INT_SET = 0x100,
+	TEGRA_AHUB_APBIF_INT_SET = 0x104,
+
+	TEGRA_AHUB_AUDIO_RX = 0x0,
+	TEGRA_AHUB_AUDIO_RX_STRIDE = 0x4,
+	TEGRA_AHUB_AUDIO_RX_COUNT = 17,
+};
+
+#endif	/* _TEGRA_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h
new file mode 100644
index 0000000..5316bc4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * NVIDIA Tegra I2C controller
+ *
+ * Copyright 2010-2011 NVIDIA Corporation
+ */
+
+#ifndef _TEGRA_I2C_H_
+#define _TEGRA_I2C_H_
+
+#include <asm/types.h>
+
+enum {
+	I2C_TIMEOUT_USEC = 10000,	/* Wait time for completion */
+	I2C_FIFO_DEPTH = 8,		/* I2C fifo depth */
+};
+
+enum i2c_transaction_flags {
+	I2C_IS_WRITE = 0x1,		/* for I2C write operation */
+	I2C_IS_10_BIT_ADDRESS = 0x2,	/* for 10-bit I2C slave address */
+	I2C_USE_REPEATED_START = 0x4,	/* for repeat start */
+	I2C_NO_ACK = 0x8,		/* for slave that won't generate ACK */
+	I2C_SOFTWARE_CONTROLLER	= 0x10,	/* for I2C transfer using GPIO */
+	I2C_NO_STOP = 0x20,
+};
+
+/* Contians the I2C transaction details */
+struct i2c_trans_info {
+	/* flags to indicate the transaction details */
+	enum i2c_transaction_flags flags;
+	u32 address;	/* I2C slave device address */
+	u32 num_bytes;	/* number of bytes to be transferred */
+	/*
+	 * Send/receive buffer. For the I2C send operation this buffer should
+	 * be filled with the data to be sent to the slave device. For the I2C
+	 * receive operation this buffer is filled with the data received from
+	 * the slave device.
+	 */
+	u8 *buf;
+	int is_10bit_address;
+};
+
+struct i2c_control {
+	u32 tx_fifo;
+	u32 rx_fifo;
+	u32 packet_status;
+	u32 fifo_control;
+	u32 fifo_status;
+	u32 int_mask;
+	u32 int_status;
+};
+
+struct dvc_ctlr {
+	u32 ctrl1;			/* 00: DVC_CTRL_REG1 */
+	u32 ctrl2;			/* 04: DVC_CTRL_REG2 */
+	u32 ctrl3;			/* 08: DVC_CTRL_REG3 */
+	u32 status;			/* 0C: DVC_STATUS_REG */
+	u32 ctrl;			/* 10: DVC_I2C_CTRL_REG */
+	u32 addr_data;			/* 14: DVC_I2C_ADDR_DATA_REG */
+	u32 reserved_0[2];		/* 18: */
+	u32 req;			/* 20: DVC_REQ_REGISTER */
+	u32 addr_data3;			/* 24: DVC_I2C_ADDR_DATA_REG_3 */
+	u32 reserved_1[6];		/* 28: */
+	u32 cnfg;			/* 40: DVC_I2C_CNFG */
+	u32 cmd_addr0;			/* 44: DVC_I2C_CMD_ADDR0 */
+	u32 cmd_addr1;			/* 48: DVC_I2C_CMD_ADDR1 */
+	u32 cmd_data1;			/* 4C: DVC_I2C_CMD_DATA1 */
+	u32 cmd_data2;			/* 50: DVC_I2C_CMD_DATA2 */
+	u32 reserved_2[2];		/* 54: */
+	u32 i2c_status;			/* 5C: DVC_I2C_STATUS */
+	struct i2c_control control;	/* 60 ~ 78 */
+};
+
+struct i2c_ctlr {
+	u32 cnfg;			/* 00: I2C_I2C_CNFG */
+	u32 cmd_addr0;			/* 04: I2C_I2C_CMD_ADDR0 */
+	u32 cmd_addr1;			/* 08: I2C_I2C_CMD_DATA1 */
+	u32 cmd_data1;			/* 0C: I2C_I2C_CMD_DATA2 */
+	u32 cmd_data2;			/* 10: DVC_I2C_CMD_DATA2 */
+	u32 reserved_0[2];		/* 14: */
+	u32 status;			/* 1C: I2C_I2C_STATUS */
+	u32 sl_cnfg;			/* 20: I2C_I2C_SL_CNFG */
+	u32 sl_rcvd;			/* 24: I2C_I2C_SL_RCVD */
+	u32 sl_status;			/* 28: I2C_I2C_SL_STATUS */
+	u32 sl_addr1;			/* 2C: I2C_I2C_SL_ADDR1 */
+	u32 sl_addr2;			/* 30: I2C_I2C_SL_ADDR2 */
+	u32 reserved_1[2];		/* 34: */
+	u32 sl_delay_count;		/* 3C: I2C_I2C_SL_DELAY_COUNT */
+	u32 reserved_2[4];		/* 40: */
+	struct i2c_control control;	/* 50 ~ 68 */
+	u32 clk_div;			/* 6C: I2C_I2C_CLOCK_DIVISOR */
+};
+
+/* bit fields definitions for IO Packet Header 1 format */
+#define PKT_HDR1_PROTOCOL_SHIFT		4
+#define PKT_HDR1_PROTOCOL_MASK		(0xf << PKT_HDR1_PROTOCOL_SHIFT)
+#define PKT_HDR1_CTLR_ID_SHIFT		12
+#define PKT_HDR1_CTLR_ID_MASK		(0xf << PKT_HDR1_CTLR_ID_SHIFT)
+#define PKT_HDR1_PKT_ID_SHIFT		16
+#define PKT_HDR1_PKT_ID_MASK		(0xff << PKT_HDR1_PKT_ID_SHIFT)
+#define PROTOCOL_TYPE_I2C		1
+
+/* bit fields definitions for IO Packet Header 2 format */
+#define PKT_HDR2_PAYLOAD_SIZE_SHIFT	0
+#define PKT_HDR2_PAYLOAD_SIZE_MASK	(0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
+
+/* bit fields definitions for IO Packet Header 3 format */
+#define PKT_HDR3_READ_MODE_SHIFT	19
+#define PKT_HDR3_READ_MODE_MASK		(1 << PKT_HDR3_READ_MODE_SHIFT)
+#define PKT_HDR3_REPEAT_START_SHIFT	16
+#define PKT_HDR3_REPEAT_START_MASK	(1 << PKT_HDR3_REPEAT_START_SHIFT)
+#define PKT_HDR3_SLAVE_ADDR_SHIFT	0
+#define PKT_HDR3_SLAVE_ADDR_MASK	(0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
+
+#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT	26
+#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK	\
+				(1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
+
+/* I2C_CNFG */
+#define I2C_CNFG_NEW_MASTER_FSM_SHIFT	11
+#define I2C_CNFG_NEW_MASTER_FSM_MASK	(1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
+#define I2C_CNFG_PACKET_MODE_SHIFT	10
+#define I2C_CNFG_PACKET_MODE_MASK	(1 << I2C_CNFG_PACKET_MODE_SHIFT)
+
+/* I2C_SL_CNFG */
+#define I2C_SL_CNFG_NEWSL_SHIFT		2
+#define I2C_SL_CNFG_NEWSL_MASK		(1 << I2C_SL_CNFG_NEWSL_SHIFT)
+
+/* I2C_FIFO_STATUS */
+#define TX_FIFO_FULL_CNT_SHIFT		0
+#define TX_FIFO_FULL_CNT_MASK		(0xf << TX_FIFO_FULL_CNT_SHIFT)
+#define TX_FIFO_EMPTY_CNT_SHIFT		4
+#define TX_FIFO_EMPTY_CNT_MASK		(0xf << TX_FIFO_EMPTY_CNT_SHIFT)
+
+/* I2C_INTERRUPT_STATUS */
+#define I2C_INT_XFER_COMPLETE_SHIFT	7
+#define I2C_INT_XFER_COMPLETE_MASK	(1 << I2C_INT_XFER_COMPLETE_SHIFT)
+#define I2C_INT_NO_ACK_SHIFT		3
+#define I2C_INT_NO_ACK_MASK		(1 << I2C_INT_NO_ACK_SHIFT)
+#define I2C_INT_ARBITRATION_LOST_SHIFT	2
+#define I2C_INT_ARBITRATION_LOST_MASK	(1 << I2C_INT_ARBITRATION_LOST_SHIFT)
+
+/* I2C_CLK_DIVISOR_REGISTER */
+#define CLK_DIV_STD_FAST_MODE		0x19
+#define CLK_DIV_HS_MODE			1
+#define CLK_MULT_STD_FAST_MODE		8
+
+/**
+ * Returns the bus number of the DVC controller
+ *
+ * @return number of bus, or -1 if there is no DVC active
+ */
+int tegra_i2c_get_dvc_bus(struct udevice **busp);
+
+#endif	/* _TEGRA_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2s.h b/arch/arm/include/asm/arch-tegra/tegra_i2s.h
new file mode 100644
index 0000000..9319383
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/tegra_i2s.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * tegra_i2s.h - Definitions for Tegra124 I2S driver.
+ * Note, some structures (ex, CIF) are different in Tegra114.
+ *
+ * NVIDIA Tegra I2S controller
+ * Modified from dc tegra_regs.h
+ *
+ * Copyright 2018 Google LLC
+ *
+ * Copyright (c) 2011-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA_I2S_H_
+#define _TEGRA_I2S_H_
+
+struct i2s_ctlr {
+	u32 ctrl;		/* I2S_CTRL_0, 0x00 */
+	u32 timing;		/* I2S_TIMING_0, 0x04 */
+	u32 offset;		/* I2S_OFFSET_0, 0x08 */
+	u32 ch_ctrl;		/* I2S_CH_CTRL_0, 0x0C */
+	u32 slot_ctrl;		/* I2S_SLOT_CTRL_0, 0x10 */
+	u32 cif_tx_ctrl;	/* I2S_CIF_TX_CTRL_0, 0x14 */
+	u32 cif_rx_ctrl;	/* I2S_CIF_RX_CTRL_0, 0x18 */
+	u32 flowctl;		/* I2S_FLOWCTL_0, 0x1C */
+	u32 tx_step;		/* I2S_TX_STEP_0, 0x20 */
+	u32 flow_status;	/* I2S_FLOW_STATUS_0, 0x24 */
+	u32 flow_total;		/* I2S_FLOW_TOTAL_0, 0x28 */
+	u32 flow_over;		/* I2S_FLOW_OVER_0, 0x2C */
+	u32 flow_under;		/* I2S_FLOW_UNDER_0, 0x30 */
+	u32 reserved[12];	/* RESERVED, 0x34 - 0x60 */
+	u32 slot_ctrl2;		/* I2S_SLOT_CTRL2_0, 0x64*/
+};
+
+enum {
+	I2S_CTRL_XFER_EN_TX = 1 << 31,
+	I2S_CTRL_XFER_EN_RX = 1 << 30,
+	I2S_CTRL_CG_EN = 1 << 29,
+	I2S_CTRL_SOFT_RESET = 1 << 28,
+	I2S_CTRL_TX_FLOWCTL_EN = 1 << 27,
+
+	I2S_CTRL_OBS_SEL_SHIFT = 24,
+	I2S_CTRL_OBS_SEL_MASK = 7 << I2S_CTRL_OBS_SEL_SHIFT,
+
+	I2S_FRAME_FORMAT_LRCK = 0,
+	I2S_FRAME_FORMAT_FSYNC = 1,
+
+	I2S_CTRL_FRAME_FORMAT_SHIFT = 12,
+	I2S_CTRL_FRAME_FORMAT_MASK = 7 << I2S_CTRL_FRAME_FORMAT_SHIFT,
+	I2S_CTRL_FRAME_FORMAT_LRCK = I2S_FRAME_FORMAT_LRCK <<
+				     I2S_CTRL_FRAME_FORMAT_SHIFT,
+	I2S_CTRL_FRAME_FORMAT_FSYNC = I2S_FRAME_FORMAT_FSYNC <<
+				      I2S_CTRL_FRAME_FORMAT_SHIFT,
+
+	I2S_CTRL_MASTER_ENABLE = 1 << 10,
+
+	I2S_LRCK_LEFT_LOW = 0,
+	I2S_LRCK_RIGHT_LOW = 1,
+
+	I2S_CTRL_LRCK_SHIFT = 9,
+	I2S_CTRL_LRCK_MASK = 1 << I2S_CTRL_LRCK_SHIFT,
+	I2S_CTRL_LRCK_L_LOW = I2S_LRCK_LEFT_LOW  << I2S_CTRL_LRCK_SHIFT,
+	I2S_CTRL_LRCK_R_LOW = I2S_LRCK_RIGHT_LOW << I2S_CTRL_LRCK_SHIFT,
+
+	I2S_CTRL_LPBK_ENABLE = 1 << 8,
+
+	I2S_BIT_CODE_LINEAR = 0,
+	I2S_BIT_CODE_ULAW = 1,
+	I2S_BIT_CODE_ALAW = 2,
+
+	I2S_CTRL_BIT_CODE_SHIFT = 4,
+	I2S_CTRL_BIT_CODE_MASK = 3 << I2S_CTRL_BIT_CODE_SHIFT,
+	I2S_CTRL_BIT_CODE_LINEAR = I2S_BIT_CODE_LINEAR <<
+				   I2S_CTRL_BIT_CODE_SHIFT,
+	I2S_CTRL_BIT_CODE_ULAW = I2S_BIT_CODE_ULAW << I2S_CTRL_BIT_CODE_SHIFT,
+	I2S_CTRL_BIT_CODE_ALAW = I2S_BIT_CODE_ALAW << I2S_CTRL_BIT_CODE_SHIFT,
+
+	I2S_BITS_8 = 1,
+	I2S_BITS_12 = 2,
+	I2S_BITS_16 = 3,
+	I2S_BITS_20 = 4,
+	I2S_BITS_24 = 5,
+	I2S_BITS_28 = 6,
+	I2S_BITS_32 = 7,
+
+	/* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */
+	I2S_CTRL_BIT_SIZE_SHIFT = 0,
+	I2S_CTRL_BIT_SIZE_MASK = 7 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_8 = I2S_BITS_8  << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_12 = I2S_BITS_12 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_16 = I2S_BITS_16 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_20 = I2S_BITS_20 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_24 = I2S_BITS_24 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_28 = I2S_BITS_28 << I2S_CTRL_BIT_SIZE_SHIFT,
+	I2S_CTRL_BIT_SIZE_32 = I2S_BITS_32 << I2S_CTRL_BIT_SIZE_SHIFT,
+
+	I2S_TIMING_NON_SYM_ENABLE = 1 << 12,
+	I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT = 0,
+	I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US = 0x7ff,
+	I2S_TIMING_CHANNEL_BIT_COUNT_MASK =
+			I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US <<
+			I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT,
+
+	I2S_OFFSET_RX_DATA_OFFSET_SHIFT = 16,
+	I2S_OFFSET_RX_DATA_OFFSET_MASK_US = 0x7ff,
+	I2S_OFFSET_RX_DATA_OFFSET_MASK = I2S_OFFSET_RX_DATA_OFFSET_MASK_US <<
+					 I2S_OFFSET_RX_DATA_OFFSET_SHIFT,
+	I2S_OFFSET_TX_DATA_OFFSET_SHIFT = 0,
+	I2S_OFFSET_TX_DATA_OFFSET_MASK_US = 0x7ff,
+	I2S_OFFSET_TX_DATA_OFFSET_MASK = I2S_OFFSET_TX_DATA_OFFSET_MASK_US <<
+					 I2S_OFFSET_TX_DATA_OFFSET_SHIFT,
+
+	/* FSYNC width - 1 in bit clocks */
+	I2S_CH_CTRL_FSYNC_WIDTH_SHIFT = 24,
+	I2S_CH_CTRL_FSYNC_WIDTH_MASK_US = 0xff,
+	I2S_CH_CTRL_FSYNC_WIDTH_MASK = I2S_CH_CTRL_FSYNC_WIDTH_MASK_US <<
+				       I2S_CH_CTRL_FSYNC_WIDTH_SHIFT,
+
+	I2S_HIGHZ_NO = 0,
+	I2S_HIGHZ_YES = 1,
+	I2S_HIGHZ_ON_HALF_BIT_CLK = 2,
+
+	I2S_CH_CTRL_HIGHZ_CTRL_SHIFT = 12,
+	I2S_CH_CTRL_HIGHZ_CTRL_MASK = 3 << I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+	I2S_CH_CTRL_HIGHZ_CTRL_NO = I2S_HIGHZ_NO <<
+				    I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+	I2S_CH_CTRL_HIGHZ_CTRL_YES = I2S_HIGHZ_YES <<
+				     I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+	I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK = I2S_HIGHZ_ON_HALF_BIT_CLK <<
+						 I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
+
+	I2S_MSB_FIRST = 0,
+	I2S_LSB_FIRST = 1,
+
+	I2S_CH_CTRL_RX_BIT_ORDER_SHIFT = 10,
+	I2S_CH_CTRL_RX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
+	I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
+					     I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
+	I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
+					     I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
+	I2S_CH_CTRL_TX_BIT_ORDER_SHIFT = 9,
+	I2S_CH_CTRL_TX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
+	I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
+					     I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
+	I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
+					     I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
+
+	I2S_POS_EDGE = 0,
+	I2S_NEG_EDGE = 1,
+
+	I2S_CH_CTRL_EGDE_CTRL_SHIFT = 8,
+	I2S_CH_CTRL_EGDE_CTRL_MASK = 1 << I2S_CH_CTRL_EGDE_CTRL_SHIFT,
+	I2S_CH_CTRL_EGDE_CTRL_POS_EDGE = I2S_POS_EDGE <<
+					 I2S_CH_CTRL_EGDE_CTRL_SHIFT,
+	I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE = I2S_NEG_EDGE <<
+					 I2S_CH_CTRL_EGDE_CTRL_SHIFT,
+
+	/* Sample size is # bits from BIT_SIZE minus this field */
+	I2S_CH_CTRL_RX_MASK_BITS_SHIFT = 4,
+	I2S_CH_CTRL_RX_MASK_BITS_MASK_US = 7,
+	I2S_CH_CTRL_RX_MASK_BITS_MASK = I2S_CH_CTRL_RX_MASK_BITS_MASK_US <<
+					I2S_CH_CTRL_RX_MASK_BITS_SHIFT,
+
+	I2S_CH_CTRL_TX_MASK_BITS_SHIFT = 0,
+	I2S_CH_CTRL_TX_MASK_BITS_MASK_US = 7,
+	I2S_CH_CTRL_TX_MASK_BITS_MASK = I2S_CH_CTRL_TX_MASK_BITS_MASK_US <<
+					I2S_CH_CTRL_TX_MASK_BITS_SHIFT,
+
+	/* Number of slots in frame, minus 1 */
+	I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT = 16,
+	I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US = 7,
+	I2S_SLOT_CTRL_TOTAL_SLOTS_MASK = I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US <<
+					 I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT,
+
+	/* TDM mode slot enable bitmask */
+	I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT = 8,
+	I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK =
+			0xff << I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT,
+
+	I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT = 0,
+	I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK = 0xff <<
+					   I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT,
+
+	I2S_FILTER_LINEAR = 0,
+	I2S_FILTER_QUAD = 1,
+
+	I2S_FLOWCTL_FILTER_SHIFT = 31,
+	I2S_FLOWCTL_FILTER_MASK = 1 << I2S_FLOWCTL_FILTER_SHIFT,
+	I2S_FLOWCTL_FILTER_LINEAR = I2S_FILTER_LINEAR <<
+				    I2S_FLOWCTL_FILTER_SHIFT,
+	I2S_FLOWCTL_FILTER_QUAD = I2S_FILTER_QUAD << I2S_FLOWCTL_FILTER_SHIFT,
+
+	I2S_TX_STEP_SHIFT = 0,
+	I2S_TX_STEP_MASK_US = 0xffff,
+	I2S_TX_STEP_MASK = I2S_TX_STEP_MASK_US << I2S_TX_STEP_SHIFT,
+
+	I2S_FLOW_STATUS_UNDERFLOW = 1 << 31,
+	I2S_FLOW_STATUS_OVERFLOW = 1 << 30,
+	I2S_FLOW_STATUS_MONITOR_INT_EN = 1 << 4,
+	I2S_FLOW_STATUS_COUNTER_CLR = 1 << 3,
+	I2S_FLOW_STATUS_MONITOR_CLR = 1 << 2,
+	I2S_FLOW_STATUS_COUNTER_EN = 1 << 1,
+	I2S_FLOW_STATUS_MONITOR_EN = 1 << 0,
+};
+
+#endif	/* _TEGRA_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
new file mode 100644
index 0000000..a2b6f63
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Portions Copyright (C) 2011-2012 NVIDIA Corporation
+ */
+
+#ifndef __TEGRA_MMC_H_
+#define __TEGRA_MMC_H_
+
+#include <common.h>
+#include <clk.h>
+#include <reset.h>
+#include <fdtdec.h>
+#include <asm/gpio.h>
+
+/* for mmc_config definition */
+#include <mmc.h>
+
+#ifndef __ASSEMBLY__
+struct tegra_mmc {
+	unsigned int	sysad;		/* _SYSTEM_ADDRESS_0 */
+	unsigned short	blksize;	/* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
+	unsigned short	blkcnt;		/* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
+	unsigned int	argument;	/* _ARGUMENT_0 */
+	unsigned short	trnmod;		/* _CMD_XFER_MODE_0 15:00 xfer mode */
+	unsigned short	cmdreg;		/* _CMD_XFER_MODE_0 31:16 cmd reg */
+	unsigned int	rspreg0;	/* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
+	unsigned int	rspreg1;	/* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
+	unsigned int	rspreg2;	/* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
+	unsigned int	rspreg3;	/* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
+	unsigned int	bdata;		/* _BUFFER_DATA_PORT_0 */
+	unsigned int	prnsts;		/* _PRESENT_STATE_0 */
+	unsigned char	hostctl;	/* _POWER_CONTROL_HOST_0 7:00 */
+	unsigned char	pwrcon;		/* _POWER_CONTROL_HOST_0 15:8 */
+	unsigned char	blkgap;		/* _POWER_CONTROL_HOST_9 23:16 */
+	unsigned char	wakcon;		/* _POWER_CONTROL_HOST_0 31:24 */
+	unsigned short	clkcon;		/* _CLOCK_CONTROL_0 15:00 */
+	unsigned char	timeoutcon;	/* _TIMEOUT_CTRL 23:16 */
+	unsigned char	swrst;		/* _SW_RESET_ 31:24 */
+	unsigned int	norintsts;	/* _INTERRUPT_STATUS_0 */
+	unsigned int	norintstsen;	/* _INTERRUPT_STATUS_ENABLE_0 */
+	unsigned int	norintsigen;	/* _INTERRUPT_SIGNAL_ENABLE_0 */
+	unsigned short	acmd12errsts;	/* _AUTO_CMD12_ERR_STATUS_0 15:00 */
+	unsigned char	res1[2];	/* _RESERVED 31:16 */
+	unsigned int	capareg;	/* _CAPABILITIES_0 */
+	unsigned char	res2[4];	/* RESERVED, offset 44h-47h */
+	unsigned int	maxcurr;	/* _MAXIMUM_CURRENT_0 */
+	unsigned char	res3[4];	/* RESERVED, offset 4Ch-4Fh */
+	unsigned short	setacmd12err;	/* offset 50h */
+	unsigned short	setinterr;	/* offset 52h */
+	unsigned char	admaerr;	/* offset 54h */
+	unsigned char	res4[3];	/* RESERVED, offset 55h-57h */
+	unsigned long	admaaddr;	/* offset 58h-5Fh */
+	unsigned char	res5[0xa0];	/* RESERVED, offset 60h-FBh */
+	unsigned short	slotintstatus;	/* offset FCh */
+	unsigned short	hcver;		/* HOST Version */
+	unsigned int	venclkctl;	/* _VENDOR_CLOCK_CNTRL_0,    100h */
+	unsigned int	venspictl;	/* _VENDOR_SPI_CNTRL_0,      104h */
+	unsigned int	venspiintsts;	/* _VENDOR_SPI_INT_STATUS_0, 108h */
+	unsigned int	venceatactl;	/* _VENDOR_CEATA_CNTRL_0,    10Ch */
+	unsigned int	venbootctl;	/* _VENDOR_BOOT_CNTRL_0,     110h */
+	unsigned int	venbootacktout;	/* _VENDOR_BOOT_ACK_TIMEOUT, 114h */
+	unsigned int	venbootdattout;	/* _VENDOR_BOOT_DAT_TIMEOUT, 118h */
+	unsigned int	vendebouncecnt;	/* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */
+	unsigned int	venmiscctl;	/* _VENDOR_MISC_CNTRL_0,     120h */
+	unsigned int	res6[47];	/* 0x124 ~ 0x1DC */
+	unsigned int	sdmemcmppadctl;	/* _SDMEMCOMPPADCTRL_0,      1E0h */
+	unsigned int	autocalcfg;	/* _AUTO_CAL_CONFIG_0,       1E4h */
+	unsigned int	autocalintval;	/* _AUTO_CAL_INTERVAL_0,     1E8h */
+	unsigned int	autocalsts;	/* _AUTO_CAL_STATUS_0,       1ECh */
+};
+
+#define TEGRA_MMC_PWRCTL_SD_BUS_POWER				(1 << 0)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8			(5 << 1)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0			(6 << 1)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3			(7 << 1)
+
+#define TEGRA_MMC_HOSTCTL_DMASEL_MASK				(3 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA				(0 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT			(2 << 3)
+#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT			(3 << 3)
+
+#define TEGRA_MMC_TRNMOD_DMA_ENABLE				(1 << 0)
+#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE			(1 << 1)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE		(0 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ			(1 << 4)
+#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT			(1 << 5)
+
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK			(3 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE		(0 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136		(1 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48		(2 << 0)
+#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY	(3 << 0)
+
+#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK				(1 << 3)
+#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK			(1 << 4)
+#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER	(1 << 5)
+
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD			(1 << 0)
+#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT			(1 << 1)
+
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE			(1 << 0)
+#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE			(1 << 1)
+#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE			(1 << 2)
+
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT			8
+#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK			(0xff << 8)
+
+#define TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK			(1 << 17)
+
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL			(1 << 0)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE			(1 << 1)
+#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE			(1 << 2)
+
+#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE			(1 << 0)
+#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE			(1 << 1)
+#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT			(1 << 3)
+#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT			(1 << 15)
+#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT				(1 << 16)
+
+#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE			(1 << 0)
+#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE			(1 << 1)
+#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT			(1 << 3)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY		(1 << 4)
+#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY			(1 << 5)
+
+#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE			(1 << 1)
+
+/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+#define MEMCOMP_PADCTRL_VREF	7
+#define AUTO_CAL_ENABLED	(1 << 29)
+#define AUTO_CAL_PD_OFFSET	(0x70 << 8)
+#define AUTO_CAL_PU_OFFSET	(0x62 << 0)
+
+#endif	/* __ASSEMBLY__ */
+#endif	/* __TEGRA_MMC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/timer.h b/arch/arm/include/asm/arch-tegra/timer.h
new file mode 100644
index 0000000..1c4deca
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/timer.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+/* Tegra20 timer functions */
+
+#ifndef _TEGRA_TIMER_H
+#define _TEGRA_TIMER_H
+
+/* returns the current monotonic timer value in microseconds */
+unsigned long timer_get_us(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/uart.h b/arch/arm/include/asm/arch-tegra/uart.h
new file mode 100644
index 0000000..24f0bdd
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/uart.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _UART_H_
+#define _UART_H_
+
+/* UART registers */
+struct uart_ctlr {
+	uint uart_thr_dlab_0;		/* UART_THR_DLAB_0_0, offset 00 */
+	uint uart_ier_dlab_0;		/* UART_IER_DLAB_0_0, offset 04 */
+	uint uart_iir_fcr;		/* UART_IIR_FCR_0, offset 08 */
+	uint uart_lcr;			/* UART_LCR_0, offset 0C */
+	uint uart_mcr;			/* UART_MCR_0, offset 10 */
+	uint uart_lsr;			/* UART_LSR_0, offset 14 */
+	uint uart_msr;			/* UART_MSR_0, offset 18 */
+	uint uart_spr;			/* UART_SPR_0, offset 1C */
+	uint uart_irda_csr;		/* UART_IRDA_CSR_0, offset 20 */
+	uint uart_reserved[6];		/* Reserved, unused, offset 24-38*/
+	uint uart_asr;			/* UART_ASR_0, offset 3C */
+};
+
+#define NVRM_PLLP_FIXED_FREQ_KHZ	216000
+#define NV_DEFAULT_DEBUG_BAUD		115200
+
+#define UART_FCR_TRIGGER_3	0x30	/* Mask for trigger set at 3 */
+
+#endif	/* UART_H */
diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h
new file mode 100644
index 0000000..6e6ea14
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -0,0 +1,360 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
+ */
+
+#ifndef _TEGRA_USB_H_
+#define _TEGRA_USB_H_
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[2];
+
+#ifdef CONFIG_TEGRA20
+	/* 0x130 */
+	uint reserved4_2[4];
+
+	/* 0x140 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x150 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint async_tt_sts;
+
+	/* 0x160 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;   /* is this port_sc1 on some controllers? */
+	uint icusb_ctrl;
+
+	/* 0x170 */
+	uint ulpi_viewport;
+	uint reserved7;
+	uint endpt_nak;
+	uint endpt_nak_enable;
+
+	/* 0x180 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x1a0 */
+	uint reserved9;
+	uint otgsc;
+	uint usb_mode;
+	uint endpt_setup_stat;
+
+	/* 0x1b0 */
+	uint reserved10[20];
+
+	/* 0x200 */
+	uint reserved11[0x80];
+#else
+	/* 0x130 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x140 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint reserved5_1;
+
+	/* 0x150 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;
+	uint icusb_ctrl;
+
+	/* 0x160 */
+	uint ulpi_viewport;
+	uint reserved7[3];
+
+	/* 0x170 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x190 */
+	uint reserved9[8];
+
+	/* 0x1b0 */
+	uint reserved10;
+	uint hostpc1_devlc;
+	uint reserved10_1[2];
+
+	/* 0x1c0 */
+	uint reserved10_2[4];
+
+	/* 0x1d0 */
+	uint reserved10_3[4];
+
+	/* 0x1e0 */
+	uint reserved10_4[4];
+
+	/* 0x1f0 */
+	uint reserved10_5;
+	uint otgsc;
+	uint usb_mode;
+	uint reserved10_6;
+
+	/* 0x200 */
+	uint endpt_nak;
+	uint endpt_nak_enable;
+	uint endpt_setup_stat;
+	uint reserved11_1[0x7D];
+#endif
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+#ifdef CONFIG_TEGRA20
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[4];
+
+	/* 0x424 */
+	uint ulpi_timing_ctrl_0;
+	uint ulpi_timing_ctrl_1;
+	uint reserved13[53];
+#else
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[3];
+
+	/* 0x420 */
+	uint reserved13[56];
+#endif
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+/* USB1_LEGACY_CTRL */
+#define USB1_NO_LEGACY_MODE		1
+
+#define VBUS_SENSE_CTL_SHIFT			1
+#define VBUS_SENSE_CTL_MASK			(3 << VBUS_SENSE_CTL_SHIFT)
+#define VBUS_SENSE_CTL_VBUS_WAKEUP		0
+#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP	1
+#define VBUS_SENSE_CTL_AB_SESS_VLD		2
+#define VBUS_SENSE_CTL_A_SESS_VLD		3
+
+/* USBx_IF_USB_SUSP_CTRL_0 */
+#define UTMIP_PHY_ENB			        (1 << 12)
+#define UTMIP_RESET			        (1 << 11)
+#define USB_PHY_CLK_VALID			(1 << 7)
+#define USB_SUSP_CLR				(1 << 5)
+
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
+/* USB2_IF_USB_SUSP_CTRL_0 */
+#define ULPI_PHY_ENB				(1 << 13)
+
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP			(1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP			(1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD			(1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD		(1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD			(1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x)			(((x) & 0x7) << 25)
+#endif
+
+/* USBx_UTMIP_MISC_CFG0 */
+#define UTMIP_SUSPEND_EXIT_ON_EDGE		(1 << 22)
+
+/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PHY_XTAL_CLOCKEN			(1 << 30)
+
+/*
+ * Tegra 3 and later: Moved to Clock and Reset register space, see
+ * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
+ */
+#define UTMIP_PLLU_STABLE_COUNT_SHIFT		6
+#define UTMIP_PLLU_STABLE_COUNT_MASK		\
+				(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+/*
+ * Tegra 3 and later: Moved to Clock and Reset register space, see
+ * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
+ */
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT	18
+#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK		\
+				(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+
+/* USBx_UTMIP_PLL_CFG1_0 */
+/* Tegra 3 and later: Moved to Clock and Reset register space */
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT	27
+#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK	\
+				(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define UTMIP_XTAL_FREQ_COUNT_SHIFT		0
+#define UTMIP_XTAL_FREQ_COUNT_MASK		0xfff
+
+/* USBx_UTMIP_BIAS_CFG0_0 */
+#define UTMIP_HSDISCON_LEVEL_MSB		(1 << 24)
+#define UTMIP_OTGPD				(1 << 11)
+#define UTMIP_BIASPD				(1 << 10)
+#define UTMIP_HSDISCON_LEVEL_SHIFT		2
+#define UTMIP_HSDISCON_LEVEL_MASK		\
+				(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
+#define UTMIP_HSSQUELCH_LEVEL_SHIFT		0
+#define UTMIP_HSSQUELCH_LEVEL_MASK		\
+				(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
+
+/* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_FORCE_PDTRK_POWERDOWN		1
+#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT	8
+#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK	\
+				(0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
+#define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
+#define UTMIP_BIAS_PDTRK_COUNT_MASK		\
+				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+
+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
+#define UTMIP_DEBOUNCE_CFG0_SHIFT		0
+#define UTMIP_DEBOUNCE_CFG0_MASK		0xffff
+
+/* USBx_UTMIP_TX_CFG0_0 */
+#define UTMIP_FS_PREAMBLE_J			(1 << 19)
+
+/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
+#define UTMIP_PD_CHRG				1
+
+/* USBx_UTMIP_SPARE_CFG0_0 */
+#define FUSE_SETUP_SEL				(1 << 3)
+
+/* USBx_UTMIP_HSRX_CFG0_0 */
+#define UTMIP_IDLE_WAIT_SHIFT			15
+#define UTMIP_IDLE_WAIT_MASK			(0x1f << UTMIP_IDLE_WAIT_SHIFT)
+#define UTMIP_ELASTIC_LIMIT_SHIFT		10
+#define UTMIP_ELASTIC_LIMIT_MASK		\
+				(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
+
+/* USBx_UTMIP_HSRX_CFG1_0 */
+#define UTMIP_HS_SYNC_START_DLY_SHIFT		1
+#define UTMIP_HS_SYNC_START_DLY_MASK		\
+				(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
+
+/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
+#define IC_ENB1					(1 << 3)
+
+#ifdef CONFIG_TEGRA20
+/* PORTSC1, USB1 */
+#define PTS1_SHIFT				31
+#define PTS1_MASK				(1 << PTS1_SHIFT)
+#define STS1					(1 << 30)
+
+/* PORTSC, USB2, USB3 */
+#define PTS_SHIFT		30
+#define PTS_MASK		(3U << PTS_SHIFT)
+#define STS			(1 << 29)
+#else
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT				29
+#define PTS_MASK				(0x7U << PTS_SHIFT)
+#define STS						(1 << 28)
+#endif
+
+#define PTS_UTMI	0
+#define PTS_RESERVED	1
+#define PTS_ULPI	2
+#define PTS_ICUSB_SER	3
+#define PTS_HSIC	4
+
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
+#define WKOC				(1 << 22)
+#define WKDS				(1 << 21)
+#define WKCN				(1 << 20)
+
+/* USBx_UTMIP_XCVR_CFG0_0 */
+#define UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
+#define UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
+#define UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
+#define UTMIP_XCVR_LSBIAS_SE			(1 << 21)
+#define UTMIP_XCVR_HSSLEW_MSB_SHIFT		25
+#define UTMIP_XCVR_HSSLEW_MSB_MASK		\
+			(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_MSB_SHIFT	22
+#define UTMIP_XCVR_SETUP_MSB_MASK	(0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_SHIFT		0
+#define UTMIP_XCVR_SETUP_MASK		(0xf << UTMIP_XCVR_SETUP_SHIFT)
+
+/* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT		18
+#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK		\
+			(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
+#define UTMIP_FORCE_PDDISC_POWERDOWN		(1 << 0)
+#define UTMIP_FORCE_PDCHRP_POWERDOWN		(1 << 2)
+#define UTMIP_FORCE_PDDR_POWERDOWN		(1 << 4)
+
+/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
+#define VBUS_VLD_STS			(1 << 26)
+#define VBUS_B_SESS_VLD_SW_VALUE	(1 << 12)
+#define VBUS_B_SESS_VLD_SW_EN		(1 << 11)
+
+/* Setup USB on the board */
+int usb_process_devicetree(const void *blob);
+
+#endif	/* _TEGRA_USB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/warmboot.h b/arch/arm/include/asm/arch-tegra/warmboot.h
new file mode 100644
index 0000000..3f02073
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/warmboot.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _WARM_BOOT_H_
+#define _WARM_BOOT_H_
+
+#define STRAP_OPT_A_RAM_CODE_SHIFT	4
+#define STRAP_OPT_A_RAM_CODE_MASK	(0xf << STRAP_OPT_A_RAM_CODE_SHIFT)
+
+/* Defines the supported operating modes */
+enum fuse_operating_mode {
+	MODE_PRODUCTION = 3,
+	MODE_UNDEFINED,
+};
+
+/* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */
+enum {
+	HASH_LENGTH = 4
+};
+
+/* Defines the storage for a hash value (128 bits) */
+struct hash {
+	u32 hash[HASH_LENGTH];
+};
+
+/*
+ * Defines the code header information for the boot rom.
+ *
+ * The code immediately follows the code header.
+ *
+ * Note that the code header needs to be 16 bytes aligned to preserve
+ * the alignment of relevant data for hash and decryption computations without
+ * requiring extra copies to temporary memory areas.
+ */
+struct wb_header {
+	u32 length_insecure;	/* length of the code header */
+	u32 reserved[3];
+	struct hash hash;	/* hash of header+code, starts next field*/
+	struct hash random_aes_block;	/* a data block to aid security. */
+	u32 length_secure;	/* length of the code header */
+	u32 destination;	/* destination address to put the wb code */
+	u32 entry_point;	/* execution address of the wb code */
+	u32 code_length;	/* length of the code */
+};
+
+/*
+ * The warm boot code needs direct access to these registers since it runs in
+ * SRAM and cannot call other U-Boot code.
+ */
+union osc_ctrl_reg {
+	struct {
+		u32 xoe:1;
+		u32 xobp:1;
+		u32 reserved0:2;
+		u32 xofs:6;
+		u32 reserved1:2;
+		u32 xods:5;
+		u32 reserved2:3;
+		u32 oscfi_spare:8;
+		u32 pll_ref_div:2;
+		u32 osc_freq:2;
+	};
+	u32 word;
+};
+
+union pllx_base_reg {
+	struct {
+		u32 divm:5;
+		u32 reserved0:3;
+		u32 divn:10;
+		u32 reserved1:2;
+		u32 divp:3;
+		u32 reserved2:4;
+		u32 lock:1;
+		u32 reserved3:1;
+		u32 ref_dis:1;
+		u32 enable:1;
+		u32 bypass:1;
+	};
+	u32 word;
+};
+
+union pllx_misc_reg {
+	struct {
+		u32 vcocon:4;
+		u32 lfcon:4;
+		u32 cpcon:4;
+		u32 lock_sel:6;
+		u32 reserved0:1;
+		u32 lock_enable:1;
+		u32 reserved1:1;
+		u32 dccon:1;
+		u32 pts:2;
+		u32 reserved2:6;
+		u32 out1_div_byp:1;
+		u32 out1_inv_clk:1;
+	};
+	u32 word;
+};
+
+/*
+ * TODO: This register is not documented in the TRM yet. We could move this
+ * into the EMC and give it a proper interface, but not while it is
+ * undocumented.
+ */
+union scratch3_reg {
+	struct {
+		u32 pllx_base_divm:5;
+		u32 pllx_base_divn:10;
+		u32 pllx_base_divp:3;
+		u32 pllx_misc_lfcon:4;
+		u32 pllx_misc_cpcon:4;
+	};
+	u32 word;
+};
+
+
+/**
+ * Save warmboot memory settings for a later resume
+ *
+ * @return 0 if ok, -1 on error
+ */
+int warmboot_save_sdram_params(void);
+
+int warmboot_prepare_code(u32 seg_address, u32 seg_length);
+int sign_data_block(u8 *source, u32 length, u8 *signature);
+void wb_start(void);	/* Start of WB assembly code */
+void wb_end(void);	/* End of WB assembly code */
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
new file mode 100644
index 0000000..deccdf4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
@@ -0,0 +1,24 @@
+#ifndef _TEGRA_XUSB_PADCTL_H_
+#define _TEGRA_XUSB_PADCTL_H_
+
+struct tegra_xusb_phy;
+
+/**
+ * tegra_xusb_phy_get() - obtain a reference to a specified padctl PHY
+ * @type: the type of PHY to obtain
+ *
+ * The type of PHY varies between SoC generations. Typically there are XUSB,
+ * PCIe and SATA PHYs, though not all generations support all of them. The
+ * value of type can usually be directly parsed from a device tree.
+ *
+ * Return: a pointer to the PHY or NULL if no such PHY exists
+ */
+struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
+
+void tegra_xusb_padctl_init(void);
+int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
+int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy);
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h
new file mode 100644
index 0000000..9b95b33
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h
@@ -0,0 +1,392 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+/* Tegra114 clock PLL tables */
+
+#ifndef _TEGRA114_CLOCK_TABLES_H_
+#define _TEGRA114_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SOC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+	CLOCK_ID_CLK_M,
+
+	CLOCK_ID_COUNT,	/* number of PLLs */
+	CLOCK_ID_DISPLAY2,	/* placeholder */
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 (DEVICES_L) */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_RESERVED3,
+	PERIPH_ID_RTC,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_NDFLASH,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_RESERVED16,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_EPP,
+	PERIPH_ID_VI,
+	PERIPH_ID_2D,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_3D,
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S0,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 (DEVICES_H) */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_KBC,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_PMC,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_RESERVED45,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_I2C5,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_TVO,
+	PERIPH_ID_MIPI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_TVDAC,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_RESERVED56,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_MPE,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 (DEVICES_U) */
+	PERIPH_ID_SPEEDO,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_RESERVED76,
+	PERIPH_ID_RESERVED77,
+	PERIPH_ID_RESERVED78,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_NANDSPEED,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_RESERVED83,
+	PERIPH_ID_IRAMA,
+	PERIPH_ID_IRAMB,
+	PERIPH_ID_IRAMC,
+	PERIPH_ID_IRAMD,
+
+	/* 88 */
+	PERIPH_ID_CRAM2,
+	PERIPH_ID_RESERVED89,
+	PERIPH_ID_MDOUBLER,
+	PERIPH_ID_RESERVED91,
+	PERIPH_ID_SUSOUT,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_RESERVED95,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_3D2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_TSENSOR,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2C4,
+
+	/* 104 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AUDIO,
+	PERIPH_ID_APBIF,
+	PERIPH_ID_DAM0,
+	PERIPH_ID_DAM1,
+	PERIPH_ID_DAM2,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 112 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_EX_RESERVED17,
+	PERIPH_ID_EX_RESERVED18,
+	PERIPH_ID_EX_RESERVED19,
+	PERIPH_ID_EX_RESERVED20,
+	PERIPH_ID_EX_RESERVED21,
+	PERIPH_ID_EX_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 120 */
+	PERIPH_ID_EX_RESERVED24,
+	PERIPH_ID_EX_RESERVED25,
+	PERIPH_ID_EX_RESERVED26,
+	PERIPH_ID_EX_RESERVED27,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_EX_RESERVED30,
+	PERIPH_ID_EX_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_RESERVED1_SATACOLD,
+	PERIPH_ID_RESERVED2_PCIERX0,
+	PERIPH_ID_RESERVED3_PCIERX1,
+	PERIPH_ID_RESERVED4_PCIERX2,
+	PERIPH_ID_RESERVED5_PCIERX3,
+	PERIPH_ID_RESERVED6_PCIERX4,
+	PERIPH_ID_RESERVED7_PCIERX5,
+
+	/* 136 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_PCIE2_IOBIST,
+	PERIPH_ID_EMC_IOBIST,
+	PERIPH_ID_HDMI_IOBIST,
+	PERIPH_ID_SATA_IOBIST,
+	PERIPH_ID_MIPI_IOBIST,
+	PERIPH_ID_EMC1_IOBIST,
+	PERIPH_ID_XUSB,
+
+	/* 144 */
+	PERIPH_ID_CILAB,
+	PERIPH_ID_CILCD,
+	PERIPH_ID_CILE,
+	PERIPH_ID_DSIA_LP,
+	PERIPH_ID_DSIB_LP,
+	PERIPH_ID_RESERVED21_ENTROPY,
+	PERIPH_ID_RESERVED22_W,
+	PERIPH_ID_RESERVED23_W,
+
+	/* 152 */
+	PERIPH_ID_RESERVED24_W,
+	PERIPH_ID_AMX0,
+	PERIPH_ID_ADX0,
+	PERIPH_ID_DVFS,
+	PERIPH_ID_XUSB_SS,
+	PERIPH_ID_EMC_DLL,
+	PERIPH_ID_MC1,
+	PERIPH_ID_EMC1,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_I2C5,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_CVE,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_EPP,
+	PERIPHC_MPE,
+	PERIPHC_MIPI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_TVO,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S0,
+	PERIPHC_37h,
+
+	PERIPHC_VW_FIRST,
+	/* 0x38 */
+	PERIPHC_G3D2 = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x40 */
+	PERIPHC_AUDIO,
+	PERIPHC_41h,
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x48 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_SPEEDO,
+	PERIPHC_4eh,
+	PERIPHC_4fh,
+
+	/* 0x50 */
+	PERIPHC_50h,
+	PERIPHC_51h,
+	PERIPHC_52h,
+	PERIPHC_53h,
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+
+	PERIPHC_COUNT,
+
+	PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _TEGRA114_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h
new file mode 100644
index 0000000..84e1da4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/clock.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+/* Tegra114 clock control functions */
+
+#ifndef _TEGRA114_CLOCK_H_
+#define _TEGRA114_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
+#define PLLC_IDDQ		(1 << 26)
+
+#endif	/* _TEGRA114_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/flow.h b/arch/arm/include/asm/arch-tegra114/flow.h
new file mode 100644
index 0000000..4f0fc3b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/flow.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA114_FLOW_H_
+#define _TEGRA114_FLOW_H_
+
+struct flow_ctlr {
+	u32 halt_cpu_events;
+	u32 halt_cop_events;
+	u32 cpu_csr;
+	u32 cop_csr;
+	u32 xrq_events;
+	u32 halt_cpu1_events;
+	u32 cpu1_csr;
+	u32 halt_cpu2_events;
+	u32 cpu2_csr;
+	u32 halt_cpu3_events;
+	u32 cpu3_csr;
+	u32 cluster_control;
+};
+
+#endif	/* _TEGRA114_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/funcmux.h b/arch/arm/include/asm/arch-tegra114/funcmux.h
new file mode 100644
index 0000000..f3b1bd4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/funcmux.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+/* Tegra114 high-level function multiplexing */
+
+#ifndef _TEGRA114_FUNCMUX_H_
+#define _TEGRA114_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART4_GMI = 0,
+};
+#endif	/* _TEGRA114_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
new file mode 100644
index 0000000..69b35a1
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA114_GP_PADCTRL_H_
+#define _TEGRA114_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	reserved1;	/* 0x8C: */
+	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	reserved2[3];	/* 0xA4 - 0xAC: */
+	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	reserved3[9];	/* 0xC8-0xE8: */
+	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+	u32	reserved4[3];	/* 0xF0-0xF8: */
+	u32	ddccfg;		/* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+	u32	gmacfg;		/* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+	u32	reserved5[3];	/* 0x104-0x10C: */
+	u32	gmecfg;		/* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+	u32	gmfcfg;		/* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+	u32	gmgcfg;		/* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+	u32	gmhcfg;		/* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+	u32	owrcfg;		/* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+	u32	uadcfg;		/* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+	u32	reserved6;	/* 0x128: */
+	u32	dev3cfg;	/* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+	u32	reserved7[2];	/* 0x130 - 0x134: */
+	u32	ceccfg;		/* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+	u32	reserved8[22];	/* 0x13C - 0x190: */
+	u32	atcfg6;		/* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+	u32	dap5cfg;	/* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+	u32	vbuscfg;	/* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+	u32	aocfg3;		/* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+	u32	hvccfg0;	/* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+	u32	sdio4cfg;	/* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+	u32	aocfg0;		/* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
+};
+
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF	0
+#define SDIOCFG_DRVDN_SLWR	0
+#define SDIOCFG_DRVUP		0x24
+#define SDIOCFG_DRVDN		0x14
+
+#endif	/* _TEGRA114_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/gpio.h b/arch/arm/include/asm/arch-tegra114/gpio.h
new file mode 100644
index 0000000..4f084e2
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/gpio.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA114_GPIO_H_
+#define _TEGRA114_GPIO_H_
+
+/*
+ * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	8	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+#include <asm/arch-tegra30/gpio.h>
+
+#endif	/* _TEGRA114_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/mc.h b/arch/arm/include/asm/arch-tegra114/mc.h
new file mode 100644
index 0000000..3930bab
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/mc.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2014
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA114_MC_H_
+#define _TEGRA114_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+	u32 reserved0[4];			/* offset 0x00 - 0x0C */
+	u32 mc_smmu_config;			/* offset 0x10 */
+	u32 mc_smmu_tlb_config;			/* offset 0x14 */
+	u32 mc_smmu_ptc_config;			/* offset 0x18 */
+	u32 mc_smmu_ptb_asid;			/* offset 0x1C */
+	u32 mc_smmu_ptb_data;			/* offset 0x20 */
+	u32 reserved1[3];			/* offset 0x24 - 0x2C */
+	u32 mc_smmu_tlb_flush;			/* offset 0x30 */
+	u32 mc_smmu_ptc_flush;			/* offset 0x34 */
+	u32 reserved2[6];			/* offset 0x38 - 0x4C */
+	u32 mc_emem_cfg;			/* offset 0x50 */
+	u32 mc_emem_adr_cfg;			/* offset 0x54 */
+	u32 mc_emem_adr_cfg_dev0;		/* offset 0x58 */
+	u32 mc_emem_adr_cfg_dev1;		/* offset 0x5C */
+	u32 reserved3[12];			/* offset 0x60 - 0x8C */
+	u32 mc_emem_arb_reserved[28];		/* offset 0x90 - 0xFC */
+	u32 reserved4[338];			/* offset 0x100 - 0x644 */
+	u32 mc_video_protect_bom;		/* offset 0x648 */
+	u32 mc_video_protect_size_mb;		/* offset 0x64c */
+	u32 mc_video_protect_reg_ctrl;		/* offset 0x650 */
+};
+
+#endif	/* _TEGRA114_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
new file mode 100644
index 0000000..414b22e
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -0,0 +1,328 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef _TEGRA114_PINMUX_H_
+#define _TEGRA114_PINMUX_H_
+
+enum pmux_pingrp {
+	PMUX_PINGRP_ULPI_DATA0_PO1,
+	PMUX_PINGRP_ULPI_DATA1_PO2,
+	PMUX_PINGRP_ULPI_DATA2_PO3,
+	PMUX_PINGRP_ULPI_DATA3_PO4,
+	PMUX_PINGRP_ULPI_DATA4_PO5,
+	PMUX_PINGRP_ULPI_DATA5_PO6,
+	PMUX_PINGRP_ULPI_DATA6_PO7,
+	PMUX_PINGRP_ULPI_DATA7_PO0,
+	PMUX_PINGRP_ULPI_CLK_PY0,
+	PMUX_PINGRP_ULPI_DIR_PY1,
+	PMUX_PINGRP_ULPI_NXT_PY2,
+	PMUX_PINGRP_ULPI_STP_PY3,
+	PMUX_PINGRP_DAP3_FS_PP0,
+	PMUX_PINGRP_DAP3_DIN_PP1,
+	PMUX_PINGRP_DAP3_DOUT_PP2,
+	PMUX_PINGRP_DAP3_SCLK_PP3,
+	PMUX_PINGRP_PV0,
+	PMUX_PINGRP_PV1,
+	PMUX_PINGRP_SDMMC1_CLK_PZ0,
+	PMUX_PINGRP_SDMMC1_CMD_PZ1,
+	PMUX_PINGRP_SDMMC1_DAT3_PY4,
+	PMUX_PINGRP_SDMMC1_DAT2_PY5,
+	PMUX_PINGRP_SDMMC1_DAT1_PY6,
+	PMUX_PINGRP_SDMMC1_DAT0_PY7,
+	PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+	PMUX_PINGRP_CLK2_REQ_PCC5,
+	PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+	PMUX_PINGRP_DDC_SCL_PV4,
+	PMUX_PINGRP_DDC_SDA_PV5,
+	PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+	PMUX_PINGRP_UART2_TXD_PC2,
+	PMUX_PINGRP_UART2_RTS_N_PJ6,
+	PMUX_PINGRP_UART2_CTS_N_PJ5,
+	PMUX_PINGRP_UART3_TXD_PW6,
+	PMUX_PINGRP_UART3_RXD_PW7,
+	PMUX_PINGRP_UART3_CTS_N_PA1,
+	PMUX_PINGRP_UART3_RTS_N_PC0,
+	PMUX_PINGRP_PU0,
+	PMUX_PINGRP_PU1,
+	PMUX_PINGRP_PU2,
+	PMUX_PINGRP_PU3,
+	PMUX_PINGRP_PU4,
+	PMUX_PINGRP_PU5,
+	PMUX_PINGRP_PU6,
+	PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+	PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+	PMUX_PINGRP_DAP4_FS_PP4,
+	PMUX_PINGRP_DAP4_DIN_PP5,
+	PMUX_PINGRP_DAP4_DOUT_PP6,
+	PMUX_PINGRP_DAP4_SCLK_PP7,
+	PMUX_PINGRP_CLK3_OUT_PEE0,
+	PMUX_PINGRP_CLK3_REQ_PEE1,
+	PMUX_PINGRP_GMI_WP_N_PC7,
+	PMUX_PINGRP_GMI_IORDY_PI5,
+	PMUX_PINGRP_GMI_WAIT_PI7,
+	PMUX_PINGRP_GMI_ADV_N_PK0,
+	PMUX_PINGRP_GMI_CLK_PK1,
+	PMUX_PINGRP_GMI_CS0_N_PJ0,
+	PMUX_PINGRP_GMI_CS1_N_PJ2,
+	PMUX_PINGRP_GMI_CS2_N_PK3,
+	PMUX_PINGRP_GMI_CS3_N_PK4,
+	PMUX_PINGRP_GMI_CS4_N_PK2,
+	PMUX_PINGRP_GMI_CS6_N_PI3,
+	PMUX_PINGRP_GMI_CS7_N_PI6,
+	PMUX_PINGRP_GMI_AD0_PG0,
+	PMUX_PINGRP_GMI_AD1_PG1,
+	PMUX_PINGRP_GMI_AD2_PG2,
+	PMUX_PINGRP_GMI_AD3_PG3,
+	PMUX_PINGRP_GMI_AD4_PG4,
+	PMUX_PINGRP_GMI_AD5_PG5,
+	PMUX_PINGRP_GMI_AD6_PG6,
+	PMUX_PINGRP_GMI_AD7_PG7,
+	PMUX_PINGRP_GMI_AD8_PH0,
+	PMUX_PINGRP_GMI_AD9_PH1,
+	PMUX_PINGRP_GMI_AD10_PH2,
+	PMUX_PINGRP_GMI_AD11_PH3,
+	PMUX_PINGRP_GMI_AD12_PH4,
+	PMUX_PINGRP_GMI_AD13_PH5,
+	PMUX_PINGRP_GMI_AD14_PH6,
+	PMUX_PINGRP_GMI_AD15_PH7,
+	PMUX_PINGRP_GMI_A16_PJ7,
+	PMUX_PINGRP_GMI_A17_PB0,
+	PMUX_PINGRP_GMI_A18_PB1,
+	PMUX_PINGRP_GMI_A19_PK7,
+	PMUX_PINGRP_GMI_WR_N_PI0,
+	PMUX_PINGRP_GMI_OE_N_PI1,
+	PMUX_PINGRP_GMI_DQS_P_PJ3,
+	PMUX_PINGRP_GMI_RST_N_PI4,
+	PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+	PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+	PMUX_PINGRP_SDMMC4_CLK_PCC4,
+	PMUX_PINGRP_SDMMC4_CMD_PT7,
+	PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+	PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+	PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+	PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+	PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+	PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+	PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+	PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+	PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+	PMUX_PINGRP_PCC1,
+	PMUX_PINGRP_PBB0,
+	PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+	PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+	PMUX_PINGRP_PBB3,
+	PMUX_PINGRP_PBB4,
+	PMUX_PINGRP_PBB5,
+	PMUX_PINGRP_PBB6,
+	PMUX_PINGRP_PBB7,
+	PMUX_PINGRP_PCC2,
+	PMUX_PINGRP_JTAG_RTCK,
+	PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+	PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+	PMUX_PINGRP_KB_ROW0_PR0,
+	PMUX_PINGRP_KB_ROW1_PR1,
+	PMUX_PINGRP_KB_ROW2_PR2,
+	PMUX_PINGRP_KB_ROW3_PR3,
+	PMUX_PINGRP_KB_ROW4_PR4,
+	PMUX_PINGRP_KB_ROW5_PR5,
+	PMUX_PINGRP_KB_ROW6_PR6,
+	PMUX_PINGRP_KB_ROW7_PR7,
+	PMUX_PINGRP_KB_ROW8_PS0,
+	PMUX_PINGRP_KB_ROW9_PS1,
+	PMUX_PINGRP_KB_ROW10_PS2,
+	PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4),
+	PMUX_PINGRP_KB_COL1_PQ1,
+	PMUX_PINGRP_KB_COL2_PQ2,
+	PMUX_PINGRP_KB_COL3_PQ3,
+	PMUX_PINGRP_KB_COL4_PQ4,
+	PMUX_PINGRP_KB_COL5_PQ5,
+	PMUX_PINGRP_KB_COL6_PQ6,
+	PMUX_PINGRP_KB_COL7_PQ7,
+	PMUX_PINGRP_CLK_32K_OUT_PA0,
+	PMUX_PINGRP_SYS_CLK_REQ_PZ5,
+	PMUX_PINGRP_CORE_PWR_REQ,
+	PMUX_PINGRP_CPU_PWR_REQ,
+	PMUX_PINGRP_PWR_INT_N,
+	PMUX_PINGRP_CLK_32K_IN,
+	PMUX_PINGRP_OWR,
+	PMUX_PINGRP_DAP1_FS_PN0,
+	PMUX_PINGRP_DAP1_DIN_PN1,
+	PMUX_PINGRP_DAP1_DOUT_PN2,
+	PMUX_PINGRP_DAP1_SCLK_PN3,
+	PMUX_PINGRP_CLK1_REQ_PEE2,
+	PMUX_PINGRP_CLK1_OUT_PW4,
+	PMUX_PINGRP_SPDIF_IN_PK6,
+	PMUX_PINGRP_SPDIF_OUT_PK5,
+	PMUX_PINGRP_DAP2_FS_PA2,
+	PMUX_PINGRP_DAP2_DIN_PA4,
+	PMUX_PINGRP_DAP2_DOUT_PA5,
+	PMUX_PINGRP_DAP2_SCLK_PA3,
+	PMUX_PINGRP_DVFS_PWM_PX0,
+	PMUX_PINGRP_GPIO_X1_AUD_PX1,
+	PMUX_PINGRP_GPIO_X3_AUD_PX3,
+	PMUX_PINGRP_DVFS_CLK_PX2,
+	PMUX_PINGRP_GPIO_X4_AUD_PX4,
+	PMUX_PINGRP_GPIO_X5_AUD_PX5,
+	PMUX_PINGRP_GPIO_X6_AUD_PX6,
+	PMUX_PINGRP_GPIO_X7_AUD_PX7,
+	PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+	PMUX_PINGRP_SDMMC3_CMD_PA7,
+	PMUX_PINGRP_SDMMC3_DAT0_PB7,
+	PMUX_PINGRP_SDMMC3_DAT1_PB6,
+	PMUX_PINGRP_SDMMC3_DAT2_PB5,
+	PMUX_PINGRP_SDMMC3_DAT3_PB4,
+	PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+	PMUX_PINGRP_SDMMC1_WP_N_PV3,
+	PMUX_PINGRP_SDMMC3_CD_N_PV2,
+	PMUX_PINGRP_GPIO_W2_AUD_PW2,
+	PMUX_PINGRP_GPIO_W3_AUD_PW3,
+	PMUX_PINGRP_USB_VBUS_EN0_PN4,
+	PMUX_PINGRP_USB_VBUS_EN1_PN5,
+	PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+	PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+	PMUX_PINGRP_GMI_CLK_LB,
+	PMUX_PINGRP_RESET_OUT_N,
+	PMUX_PINGRP_COUNT,
+};
+
+enum pmux_drvgrp {
+	PMUX_DRVGRP_AO1,
+	PMUX_DRVGRP_AO2,
+	PMUX_DRVGRP_AT1,
+	PMUX_DRVGRP_AT2,
+	PMUX_DRVGRP_AT3,
+	PMUX_DRVGRP_AT4,
+	PMUX_DRVGRP_AT5,
+	PMUX_DRVGRP_CDEV1,
+	PMUX_DRVGRP_CDEV2,
+	PMUX_DRVGRP_DAP1 = (0x28 / 4),
+	PMUX_DRVGRP_DAP2,
+	PMUX_DRVGRP_DAP3,
+	PMUX_DRVGRP_DAP4,
+	PMUX_DRVGRP_DBG,
+	PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+	PMUX_DRVGRP_SPI,
+	PMUX_DRVGRP_UAA,
+	PMUX_DRVGRP_UAB,
+	PMUX_DRVGRP_UART2,
+	PMUX_DRVGRP_UART3,
+	PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+	PMUX_DRVGRP_DDC = (0x94 / 4),
+	PMUX_DRVGRP_GMA,
+	PMUX_DRVGRP_GME = (0xa8 / 4),
+	PMUX_DRVGRP_GMF,
+	PMUX_DRVGRP_GMG,
+	PMUX_DRVGRP_GMH,
+	PMUX_DRVGRP_OWR,
+	PMUX_DRVGRP_UDA,
+	PMUX_DRVGRP_DEV3 = (0xc4 / 4),
+	PMUX_DRVGRP_CEC = (0xd0 / 4),
+	PMUX_DRVGRP_AT6 = (0x12c / 4),
+	PMUX_DRVGRP_DAP5,
+	PMUX_DRVGRP_USB_VBUS_EN,
+	PMUX_DRVGRP_AO3,
+	PMUX_DRVGRP_HV0,
+	PMUX_DRVGRP_SDIO4,
+	PMUX_DRVGRP_AO0,
+	PMUX_DRVGRP_COUNT,
+};
+
+enum pmux_func {
+	PMUX_FUNC_DEFAULT,
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLDVFS,
+	PMUX_FUNC_CLK,
+	PMUX_FUNC_CLK12,
+	PMUX_FUNC_CPU,
+	PMUX_FUNC_DAP,
+	PMUX_FUNC_DAP1,
+	PMUX_FUNC_DAP2,
+	PMUX_FUNC_DEV3,
+	PMUX_FUNC_DISPLAYA,
+	PMUX_FUNC_DISPLAYA_ALT,
+	PMUX_FUNC_DISPLAYB,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_EMC_DLL,
+	PMUX_FUNC_EXTPERIPH1,
+	PMUX_FUNC_EXTPERIPH2,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_ALT,
+	PMUX_FUNC_HDA,
+	PMUX_FUNC_HSI,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_I2C4,
+	PMUX_FUNC_I2CPWR,
+	PMUX_FUNC_I2S0,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4,
+	PMUX_FUNC_IRDA,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_NAND,
+	PMUX_FUNC_NAND_ALT,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PMI,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_PWRON,
+	PMUX_FUNC_RESET_OUT_N,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC2,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SDMMC4,
+	PMUX_FUNC_SOC,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_SPI5,
+	PMUX_FUNC_SPI6,
+	PMUX_FUNC_SYSCLK,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_USB,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_ALT1,
+	PMUX_FUNC_VI_ALT3,
+	PMUX_FUNC_RSVD1,
+	PMUX_FUNC_RSVD2,
+	PMUX_FUNC_RSVD3,
+	PMUX_FUNC_RSVD4,
+	PMUX_FUNC_COUNT,
+};
+
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
+#define TEGRA_PMX_PINS_HAVE_RCV_SEL
+#include <asm/arch-tegra/pinmux.h>
+
+#endif /* _TEGRA114_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/powergate.h b/arch/arm/include/asm/arch-tegra114/powergate.h
new file mode 100644
index 0000000..260ea80
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/powergate.h
@@ -0,0 +1,6 @@
+#ifndef _TEGRA114_POWERGATE_H_
+#define _TEGRA114_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA114_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/include/asm/arch-tegra114/sysctr.h
new file mode 100644
index 0000000..228f423
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/sysctr.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA114_SYSCTR_H_
+#define _TEGRA114_SYSCTR_H_
+
+struct sysctr_ctlr {
+	u32 cntcr;		/* 0x00: SYSCTR0_CNTCR Counter Control */
+	u32 cntsr;		/* 0x04: SYSCTR0_CNTSR Counter Status */
+	u32 cntcv0;		/* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+	u32 cntcv1;		/* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+	u32 reserved1[4];	/* 0x10 - 0x1C */
+	u32 cntfid0;		/* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+	u32 cntfid1;		/* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+	u32 reserved2[1002];	/* 0x28 - 0xFCC */
+	u32 counterid[12];	/* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
+#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
+
+#endif	/* _TEGRA114_SYSCTR_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
new file mode 100644
index 0000000..317b4bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra114/tegra.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA114_H_
+#define _TEGRA114_H_
+
+#define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T114 */
+#define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
+#define NV_PA_MC_BASE		0x70019000
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET	1752	/* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE        0x48    /* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x4C    /* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU            4
+
+#endif /* TEGRA114_H */
diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h
new file mode 100644
index 0000000..d88cdfe
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/ahb.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA124_AHB_H_
+#define _TEGRA124_AHB_H_
+
+struct ahb_ctlr {
+	u32 reserved0;			/* 00h */
+	u32 arbitration_disable;	/* _ARBITRATION_DISABLE_0,	04h */
+	u32 arbitration_priority_ctrl;	/* _ARBITRATION_PRIORITY_CTRL_0,08h */
+	u32 arbitration_usr_protect;	/* _ARBITRATION_USR_PROTECT_0,	0ch */
+	u32 gizmo_ahb_mem;		/* _GIZMO_AHB_MEM_0,		10h */
+	u32 gizmo_apb_dma;		/* _GIZMO_APB_DMA_0,		14h */
+	u32 reserved6[2];		/* 18h, 1ch */
+	u32 gizmo_usb;			/* _GIZMO_USB_0,		20h */
+	u32 gizmo_ahb_xbar_bridge;	/* _GIZMO_AHB_XBAR_BRIDGE_0,	24h */
+	u32 gizmo_cpu_ahb_bridge;	/* _GIZMO_CPU_AHB_BRIDGE_0,	28h */
+	u32 gizmo_cop_ahb_bridge;	/* _GIZMO_COP_AHB_BRIDGE_0,	2ch */
+	u32 gizmo_xbar_apb_ctlr;	/* _GIZMO_XBAR_APB_CTLR_0,	30h */
+	u32 gizmo_vcp_ahb_bridge;	/* _GIZMO_VCP_AHB_BRIDGE_0,	34h */
+	u32 reserved13[2];		/* 38h, 3ch */
+	u32 gizmo_nand;			/* _GIZMO_NAND_0,		40h */
+	u32 reserved15;			/* 44h */
+	u32 gizmo_sdmmc4;		/* _GIZMO_SDMMC4_0,		48h */
+	u32 reserved17;			/* 4ch */
+	u32 gizmo_se;			/* _GIZMO_SE_0,			50h */
+	u32 gizmo_tzram;		/* _GIZMO_TZRAM_0,		54h */
+	u32 reserved20[3];		/* 58h, 5ch, 60h */
+	u32 gizmo_bsev;			/* _GIZMO_BSEV_0,		64h */
+	u32 reserved22[3];		/* 68h, 6ch, 70h */
+	u32 gizmo_bsea;			/* _GIZMO_BSEA_0,		74h */
+	u32 gizmo_nor;			/* _GIZMO_NOR_0,		78h */
+	u32 gizmo_usb2;			/* _GIZMO_USB2_0,		7ch */
+	u32 gizmo_usb3;			/* _GIZMO_USB3_0,		80h */
+	u32 gizmo_sdmmc1;		/* _GIZMO_SDMMC1_0,		84h */
+	u32 gizmo_sdmmc2;		/* _GIZMO_SDMMC2_0,		88h */
+	u32 gizmo_sdmmc3;		/* _GIZMO_SDMMC3_0,		8ch */
+	u32 reserved30[13];		/* 90h ~ c0h */
+	u32 ahb_wrq_empty;		/* _AHB_WRQ_EMPTY_0,		c4h */
+	u32 reserved32[5];		/* c8h ~ d8h */
+	u32 ahb_mem_prefetch_cfg_x;	/* _AHB_MEM_PREFETCH_CFG_X_0,	dch */
+	u32 arbitration_xbar_ctrl;	/* _ARBITRATION_XBAR_CTRL_0,	e0h */
+	u32 ahb_mem_prefetch_cfg3;	/* _AHB_MEM_PREFETCH_CFG3_0,	e4h */
+	u32 ahb_mem_prefetch_cfg4;	/* _AHB_MEM_PREFETCH_CFG3_0,	e8h */
+	u32 avp_ppcs_rd_coh_status;	/* _AVP_PPCS_RD_COH_STATUS_0,	ech */
+	u32 ahb_mem_prefetch_cfg1;	/* _AHB_MEM_PREFETCH_CFG1_0,	f0h */
+	u32 ahb_mem_prefetch_cfg2;	/* _AHB_MEM_PREFETCH_CFG2_0,	f4h */
+	u32 ahbslvmem_status;		/* _AHBSLVMEM_STATUS_0, f8h */
+	/* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
+	u32 arbitration_ahb_mem_wrque_mst_id;
+	u32 arbitration_cpu_abort_addr;	/* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
+	u32 arbitration_cpu_abort_info;	/* _ARBITRATION_CPU_ABORT_INFO_0,104h */
+	u32 arbitration_cop_abort_addr;	/* _ARBITRATION_COP_ABORT_ADDR_0,108h */
+	u32 arbitration_cop_abort_info;	/* _ARBITRATION_COP_ABORT_INFO_0,10ch */
+	u32 reserved46[4];		/* 110h ~ 11ch */
+	u32 avpc_mccif_fifoctrl;	/* _AVPC_MCCIF_FIFOCTRL_0,	120h */
+	u32 timeout_wcoal_avpc;		/* _TIMEOUT_WCOAL_AVPC_0,	124h */
+	u32 mpcorelp_mccif_fifoctrl;	/* _MPCORELP_MCCIF_FIFOCTRL_0,	128h */
+	u32 mpcore_mccif_fifoctrl;	/* _MPCORE_MCCIF_FIFOCTRL_0,	12ch */
+	u32 axicif_fastsync_ctrl;	/* AXICIF_FASTSYNC_CTRL_0,	130h */
+	u32 axicif_fastsync_statistics;	/* _AXICIF_FASTSYNC_STATISTICS_0,134h */
+	/* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0,	138h */
+	u32 axicif_fastsync0_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
+	u32 axicif_fastsync1_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
+	u32 axicif_fastsync2_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
+	u32 axicif_fastsync0_mcclk_to_cpuclk;
+	/* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
+	u32 axicif_fastsync1_mcclk_to_cpuclk;
+	/* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
+	u32 axicif_fastsync2_mcclk_to_cpuclk;
+};
+
+#define PPSB_STOPCLK_ENABLE	(1 << 2)
+
+#define GIZ_ENABLE_SPLIT	(1 << 0)
+#define GIZ_ENB_FAST_REARB	(1 << 2)
+#define GIZ_DONT_SPLIT_AHB_WR	(1 << 7)
+
+#define GIZ_USB_IMMEDIATE	(1 << 18)
+
+/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
+#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE	(1 << 2)
+
+#endif	/* _TEGRA124_AHB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h
new file mode 100644
index 0000000..9f53125
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h
@@ -0,0 +1,497 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+/* Tegra124 clock PLL tables */
+
+#ifndef _TEGRA124_CLOCK_TABLES_H_
+#define _TEGRA124_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+	CLOCK_ID_DP,	/* Special for Tegra124 */
+
+	/* These are the base clocks (inputs to the Tegra SoC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+	CLOCK_ID_CLK_M,
+
+	CLOCK_ID_COUNT,	/* number of PLLs */
+
+	/*
+	 * These are clock IDs that are used in table clock_source[][]
+	 * but will not be assigned as a clock source for any peripheral.
+	 */
+	CLOCK_ID_DISPLAY2,
+	CLOCK_ID_CGENERAL2,
+	CLOCK_ID_CGENERAL3,
+	CLOCK_ID_MEMORY2,
+	CLOCK_ID_SRC2,
+
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 (DEVICES_L) */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_ISPB,
+	PERIPH_ID_RESERVED4,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_RESERVED13,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_TCW,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_RESERVED19,
+	PERIPH_ID_VI,
+	PERIPH_ID_RESERVED21,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_RESERVED25,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S0,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 (DEVICES_H) */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_RESERVED36,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_RESERVED38,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_XIO,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_I2C5,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_RESERVED49,
+	PERIPH_ID_HSI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_RESERVED53,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_MIPI_CAL,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_RESERVED60,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 (DEVICES_U) */
+	PERIPH_ID_RESERVED64,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_LA,
+	PERIPH_ID_TRACECLKIN,
+	PERIPH_ID_SOC_THERM,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_RESERVED80,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_TSEC,
+	PERIPH_ID_RESERVED84,
+	PERIPH_ID_RESERVED85,
+	PERIPH_ID_RESERVED86,
+	PERIPH_ID_EMUCIF,
+
+	/* 88 */
+	PERIPH_ID_RESERVED88,
+	PERIPH_ID_XUSB_HOST,
+	PERIPH_ID_RESERVED90,
+	PERIPH_ID_MSENC,
+	PERIPH_ID_RESERVED92,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_XUSB_DEV,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_V_RESERVED2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_V_RESERVED4,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2C4,
+
+	/* 104 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AUDIO,
+	PERIPH_ID_APBIF,
+	PERIPH_ID_DAM0,
+	PERIPH_ID_DAM1,
+	PERIPH_ID_DAM2,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 112 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_V_RESERVED17,
+	PERIPH_ID_V_RESERVED18,
+	PERIPH_ID_V_RESERVED19,
+	PERIPH_ID_V_RESERVED20,
+	PERIPH_ID_V_RESERVED21,
+	PERIPH_ID_V_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 120 */
+	PERIPH_ID_EXTPERIPH1,
+	PERIPH_ID_EXTPERIPH2,
+	PERIPH_ID_EXTPERIPH3,
+	PERIPH_ID_OOB,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_V_RESERVED30,
+	PERIPH_ID_V_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_SATACOLD,
+	PERIPH_ID_W_RESERVED2,
+	PERIPH_ID_W_RESERVED3,
+	PERIPH_ID_W_RESERVED4,
+	PERIPH_ID_W_RESERVED5,
+	PERIPH_ID_W_RESERVED6,
+	PERIPH_ID_W_RESERVED7,
+
+	/* 136 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_W_RESERVED9,
+	PERIPH_ID_W_RESERVED10,
+	PERIPH_ID_W_RESERVED11,
+	PERIPH_ID_W_RESERVED12,
+	PERIPH_ID_W_RESERVED13,
+	PERIPH_ID_XUSB_PADCTL,
+	PERIPH_ID_W_RESERVED15,
+
+	/* 144 */
+	PERIPH_ID_W_RESERVED16,
+	PERIPH_ID_W_RESERVED17,
+	PERIPH_ID_W_RESERVED18,
+	PERIPH_ID_W_RESERVED19,
+	PERIPH_ID_W_RESERVED20,
+	PERIPH_ID_ENTROPY,
+	PERIPH_ID_DDS,
+	PERIPH_ID_W_RESERVED23,
+
+	/* 152 */
+	PERIPH_ID_DP2,
+	PERIPH_ID_AMX0,
+	PERIPH_ID_ADX0,
+	PERIPH_ID_DVFS,
+	PERIPH_ID_XUSB_SS,
+	PERIPH_ID_W_RESERVED29,
+	PERIPH_ID_W_RESERVED30,
+	PERIPH_ID_W_RESERVED31,
+
+	PERIPH_ID_X_FIRST,
+	/* X word: 31:0 */
+	PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
+	PERIPH_ID_X_RESERVED1,
+	PERIPH_ID_X_RESERVED2,
+	PERIPH_ID_X_RESERVED3,
+	PERIPH_ID_CAM_MCLK,
+	PERIPH_ID_CAM_MCLK2,
+	PERIPH_ID_I2C6,
+	PERIPH_ID_X_RESERVED7,
+
+	/* 168 */
+	PERIPH_ID_X_RESERVED8,
+	PERIPH_ID_X_RESERVED9,
+	PERIPH_ID_X_RESERVED10,
+	PERIPH_ID_VIM2_CLK,
+	PERIPH_ID_X_RESERVED12,
+	PERIPH_ID_X_RESERVED13,
+	PERIPH_ID_EMC_DLL,
+	PERIPH_ID_X_RESERVED15,
+
+	/* 176 */
+	PERIPH_ID_HDMI_AUDIO,
+	PERIPH_ID_CLK72MHZ,
+	PERIPH_ID_VIC,
+	PERIPH_ID_X_RESERVED19,
+	PERIPH_ID_ADX1,
+	PERIPH_ID_DPAUX,
+	PERIPH_ID_SOR0,
+	PERIPH_ID_X_RESERVED23,
+
+	/* 184 */
+	PERIPH_ID_GPU,
+	PERIPH_ID_AMX1,
+	PERIPH_ID_AFC5,
+	PERIPH_ID_AFC4,
+	PERIPH_ID_AFC3,
+	PERIPH_ID_AFC2,
+	PERIPH_ID_AFC1,
+	PERIPH_ID_AFC0,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_I2C5,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_10h,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_18h,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_1Bh,
+	PERIPHC_1Ch,
+	PERIPHC_HSI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_22h,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_25h,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S0,
+	PERIPHC_DTV,
+
+	/* 0x38 */
+	PERIPHC_38h,
+	PERIPHC_39h,
+	PERIPHC_3ah,
+	PERIPHC_3bh,
+	PERIPHC_MSENC,
+	PERIPHC_TSEC,
+	PERIPHC_3eh,
+	PERIPHC_OSC,
+
+	PERIPHC_VW_FIRST,
+	/* 0x40 */
+	PERIPHC_40h = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x48 */
+	PERIPHC_AUDIO,
+	PERIPHC_49h,
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x50 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_52h,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_55h,
+	PERIPHC_56h,
+	PERIPHC_57h,
+
+	/* 0x58 */
+	PERIPHC_58h,
+	PERIPHC_SOR,
+	PERIPHC_5ah,
+	PERIPHC_5bh,
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,		/* 0x428 */
+	PERIPHC_5fh,
+
+	PERIPHC_X_FIRST,
+	/* 0x60 */
+	PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST,	/* 0x600 */
+	PERIPHC_XUSB_FALCON,
+	PERIPHC_XUSB_FS,
+	PERIPHC_XUSB_CORE_DEV,
+	PERIPHC_XUSB_SS,
+	PERIPHC_CILAB,
+	PERIPHC_CILCD,
+	PERIPHC_CILE,
+
+	/* 0x68 */
+	PERIPHC_DSIA_LP,
+	PERIPHC_DSIB_LP,
+	PERIPHC_ENTROPY,
+	PERIPHC_DVFS_REF,
+	PERIPHC_DVFS_SOC,
+	PERIPHC_TRACECLKIN,
+	PERIPHC_ADX0,
+	PERIPHC_AMX0,
+
+	/* 0x70 */
+	PERIPHC_EMC_LATENCY,
+	PERIPHC_SOC_THERM,
+	PERIPHC_72h,
+	PERIPHC_73h,
+	PERIPHC_74h,
+	PERIPHC_75h,
+	PERIPHC_VI_SENSOR2,
+	PERIPHC_I2C6,
+
+	/* 0x78 */
+	PERIPHC_78h,
+	PERIPHC_EMC_DLL,
+	PERIPHC_HDMI_AUDIO,
+	PERIPHC_CLK72MHZ,
+	PERIPHC_ADX1,
+	PERIPHC_AMX1,
+	PERIPHC_VIC,
+	PERIPHC_7fh,
+
+	PERIPHC_COUNT,
+
+	PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _TEGRA124_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h
new file mode 100644
index 0000000..3f54d36
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/clock.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+/* Tegra124 clock control definitions */
+
+#ifndef _TEGRA124_CLOCK_H_
+#define _TEGRA124_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
+#define PLLC_IDDQ			(1 << 26)
+
+/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */
+#define SOR0_CLK_SEL0			(1 << 14)
+#define SOR0_CLK_SEL1			(1 << 15)
+
+int tegra_plle_enable(void);
+
+void clock_sor_enable_edp_clock(void);
+
+/**
+ * clock_set_display_rate() - Set the display clock rate
+ *
+ * @frequency: the requested PLLD frequency
+ *
+ * Return the PLLD frequenc (which may not quite what was requested), or 0
+ * on failure
+ */
+u32 clock_set_display_rate(u32 frequency);
+
+/**
+ * clock_set_up_plldp() - Set up the EDP clock ready for use
+ */
+void clock_set_up_plldp(void);
+
+#endif	/* _TEGRA124_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/display.h b/arch/arm/include/asm/arch-tegra124/display.h
new file mode 100644
index 0000000..47e0056
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/display.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
+#define __ASM_ARCH_TEGRA_DISPLAY_H
+
+/**
+ * Register a new display based on device tree configuration.
+ *
+ * The frame buffer can be positioned by U-Boot or overridden by the fdt.
+ * You should pass in the U-Boot address here, and check the contents of
+ * struct fdt_disp_config to see what was actually chosen.
+ *
+ * @param blob			Device tree blob
+ * @param default_lcd_base	Default address of LCD frame buffer
+ * @return 0 if ok, -1 on error (unsupported bits per pixel)
+ */
+int tegra_display_probe(const void *blob, void *default_lcd_base);
+
+/**
+ * Return the current display configuration
+ *
+ * @return pointer to display configuration, or NULL if there is no valid
+ * config
+ */
+struct fdt_disp_config *tegra_display_get_config(void);
+
+/**
+ * Perform the next stage of the LCD init if it is time to do so.
+ *
+ * LCD init can be time-consuming because of the number of delays we need
+ * while waiting for the backlight power supply, etc. This function can
+ * be called at various times during U-Boot operation to advance the
+ * initialization of the LCD to the next stage if sufficient time has
+ * passed since the last stage. It keeps track of what stage it is up to
+ * and the time that it is permitted to move to the next stage.
+ *
+ * The final call should have wait=1 to complete the init.
+ *
+ * @param blob	fdt blob containing LCD information
+ * @param wait	1 to wait until all init is complete, and then return
+ *		0 to return immediately, potentially doing nothing if it is
+ *		not yet time for the next init.
+ */
+int tegra_lcd_check_next_stage(const void *blob, int wait);
+
+/**
+ * Set up the maximum LCD size so we can size the frame buffer.
+ *
+ * @param blob	fdt blob containing LCD information
+ */
+void tegra_lcd_early_init(const void *blob);
+
+#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h
new file mode 100644
index 0000000..62947bf
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/flow.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA124_FLOW_H_
+#define _TEGRA124_FLOW_H_
+
+struct flow_ctlr {
+	u32 halt_cpu_events;	/* offset 0x00 */
+	u32 halt_cop_events;	/* offset 0x04 */
+	u32 cpu_csr;		/* offset 0x08 */
+	u32 cop_csr;		/* offset 0x0c */
+	u32 xrq_events;		/* offset 0x10 */
+	u32 halt_cpu1_events;	/* offset 0x14 */
+	u32 cpu1_csr;		/* offset 0x18 */
+	u32 halt_cpu2_events;	/* offset 0x1c */
+	u32 cpu2_csr;		/* offset 0x20 */
+	u32 halt_cpu3_events;	/* offset 0x24 */
+	u32 cpu3_csr;		/* offset 0x28 */
+	u32 cluster_control;	/* offset 0x2c */
+	u32 halt_cop1_events;	/* offset 0x30 */
+	u32 halt_cop1_csr;	/* offset 0x34 */
+	u32 cpu_pwr_csr;	/* offset 0x38 */
+	u32 mpid;		/* offset 0x3c */
+	u32 ram_repair;		/* offset 0x40 */
+	u32 flow_dbg_sel;	/* offset 0x44 */
+	u32 flow_dbg_cnt0;	/* offset 0x48 */
+	u32 flow_dbg_cnt1;	/* offset 0x4c */
+	u32 flow_dbg_qual;	/* offset 0x50 */
+	u32 flow_ctrl_spare;	/* offset 0x54 */
+	u32 ram_repair_cluster1;/* offset 0x58 */
+};
+
+/* HALT_COP_EVENTS_0, 0x04 */
+#define EVENT_MSEC		(1 << 24)
+#define EVENT_USEC		(1 << 25)
+#define EVENT_JTAG		(1 << 28)
+#define EVENT_MODE_STOP		(2 << 29)
+
+/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
+#define ACTIVE_LP		(1 << 0)
+
+/* CPUn_CSR_0 */
+#define CSR_ENABLE		(1 << 0)
+#define CSR_IMMEDIATE_WAKE	(1 << 3)
+#define CSR_WAIT_WFI_SHIFT	8
+#define CSR_PWR_OFF_STS		(1 << 16)
+
+#define RAM_REPAIR_REQ		BIT(0)
+#define RAM_REPAIR_STS		BIT(1)
+#define RAM_REPAIR_BYPASS_EN	BIT(2)
+
+#endif	/*  _TEGRA124_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/funcmux.h b/arch/arm/include/asm/arch-tegra124/funcmux.h
new file mode 100644
index 0000000..8d4501e
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/funcmux.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#ifndef _TEGRA124_FUNCMUX_H_
+#define _TEGRA124_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART1_KBC = 0,
+	FUNCMUX_UART4_GPIO = 0,
+};
+#endif	/* _TEGRA124_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/gp_padctrl.h b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
new file mode 100644
index 0000000..750a2dc
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/gp_padctrl.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010-2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA124_GP_PADCTRL_H_
+#define _TEGRA124_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	reserved1;	/* 0x8C: */
+	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	reserved2[3];	/* 0xA4 - 0xAC: */
+	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	reserved3[9];	/* 0xC8-0xE8: */
+	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+	u32	reserved4[3];	/* 0xF0-0xF8: */
+	u32	ddccfg;		/* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+	u32	gmacfg;		/* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+	u32	reserved5[3];	/* 0x104-0x10C: */
+	u32	gmecfg;		/* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+	u32	gmfcfg;		/* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+	u32	gmgcfg;		/* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+	u32	gmhcfg;		/* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+	u32	owrcfg;		/* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+	u32	uadcfg;		/* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+	u32	reserved6;	/* 0x128: */
+	u32	dev3cfg;	/* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+	u32	reserved7[2];	/* 0x130 - 0x134: */
+	u32	ceccfg;		/* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+	u32	reserved8[22];	/* 0x13C - 0x190: */
+	u32	atcfg6;		/* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+	u32	dap5cfg;	/* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+	u32	vbuscfg;	/* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+	u32	aocfg3;		/* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+	u32	hvccfg0;	/* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+	u32	sdio4cfg;	/* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+	u32	aocfg0;		/* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
+};
+
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF	0
+#define SDIOCFG_DRVDN_SLWR	0
+#define SDIOCFG_DRVUP		0x24
+#define SDIOCFG_DRVDN		0x14
+
+#endif	/* _TEGRA124_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h
new file mode 100644
index 0000000..e5ea281
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/gpio.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA124_GPIO_H_
+#define _TEGRA124_GPIO_H_
+
+/*
+ * The Tegra124 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	8	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+	uint gpio_masked_config[TEGRA_GPIO_PORTS];
+	uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_in[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+#endif	/* _TEGRA124_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h
new file mode 100644
index 0000000..617e55a
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA124_MC_H_
+#define _TEGRA124_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+	u32 reserved0[4];			/* offset 0x00 - 0x0C */
+	u32 mc_smmu_config;			/* offset 0x10 */
+	u32 mc_smmu_tlb_config;			/* offset 0x14 */
+	u32 mc_smmu_ptc_config;			/* offset 0x18 */
+	u32 mc_smmu_ptb_asid;			/* offset 0x1C */
+	u32 mc_smmu_ptb_data;			/* offset 0x20 */
+	u32 reserved1[3];			/* offset 0x24 - 0x2C */
+	u32 mc_smmu_tlb_flush;			/* offset 0x30 */
+	u32 mc_smmu_ptc_flush;			/* offset 0x34 */
+	u32 reserved2[6];			/* offset 0x38 - 0x4C */
+	u32 mc_emem_cfg;			/* offset 0x50 */
+	u32 mc_emem_adr_cfg;			/* offset 0x54 */
+	u32 mc_emem_adr_cfg_dev0;		/* offset 0x58 */
+	u32 mc_emem_adr_cfg_dev1;		/* offset 0x5C */
+	u32 reserved3[4];			/* offset 0x60 - 0x6C */
+	u32 mc_security_cfg0;			/* offset 0x70 */
+	u32 mc_security_cfg1;			/* offset 0x74 */
+	u32 reserved4[6];			/* offset 0x7C - 0x8C */
+	u32 mc_emem_arb_reserved[28];		/* offset 0x90 - 0xFC */
+	u32 reserved5[74];			/* offset 0x100 - 0x224 */
+	u32 mc_smmu_translation_enable_0;	/* offset 0x228 */
+	u32 mc_smmu_translation_enable_1;	/* offset 0x22C */
+	u32 mc_smmu_translation_enable_2;	/* offset 0x230 */
+	u32 mc_smmu_translation_enable_3;	/* offset 0x234 */
+	u32 mc_smmu_afi_asid;			/* offset 0x238 */
+	u32 mc_smmu_avpc_asid;			/* offset 0x23C */
+	u32 mc_smmu_dc_asid;			/* offset 0x240 */
+	u32 mc_smmu_dcb_asid;			/* offset 0x244 */
+	u32 reserved6[2];                       /* offset 0x248 - 0x24C */
+	u32 mc_smmu_hc_asid;			/* offset 0x250 */
+	u32 mc_smmu_hda_asid;			/* offset 0x254 */
+	u32 mc_smmu_isp2_asid;			/* offset 0x258 */
+	u32 reserved7[2];                       /* offset 0x25C - 0x260 */
+	u32 mc_smmu_msenc_asid;			/* offset 0x264 */
+	u32 mc_smmu_nv_asid;			/* offset 0x268 */
+	u32 mc_smmu_nv2_asid;			/* offset 0x26C */
+	u32 mc_smmu_ppcs_asid;			/* offset 0x270 */
+	u32 mc_smmu_sata_asid;			/* offset 0x274 */
+	u32 reserved8[1];                       /* offset 0x278 */
+	u32 mc_smmu_vde_asid;			/* offset 0x27C */
+	u32 mc_smmu_vi_asid;			/* offset 0x280 */
+	u32 mc_smmu_vic_asid;			/* offset 0x284 */
+	u32 mc_smmu_xusb_host_asid;		/* offset 0x288 */
+	u32 mc_smmu_xusb_dev_asid;		/* offset 0x28C */
+	u32 reserved9[1];                       /* offset 0x290 */
+	u32 mc_smmu_tsec_asid;			/* offset 0x294 */
+	u32 mc_smmu_ppcs1_asid;			/* offset 0x298 */
+	u32 reserved10[235];			/* offset 0x29C - 0x644 */
+	u32 mc_video_protect_bom;		/* offset 0x648 */
+	u32 mc_video_protect_size_mb;		/* offset 0x64c */
+	u32 mc_video_protect_reg_ctrl;		/* offset 0x650 */
+};
+
+#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
+
+#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED		(0 << 0)
+#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED	(1 << 0)
+
+#endif	/* _TEGRA124_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
new file mode 100644
index 0000000..4c593aa
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -0,0 +1,359 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef _TEGRA124_PINMUX_H_
+#define _TEGRA124_PINMUX_H_
+
+enum pmux_pingrp {
+	PMUX_PINGRP_ULPI_DATA0_PO1,
+	PMUX_PINGRP_ULPI_DATA1_PO2,
+	PMUX_PINGRP_ULPI_DATA2_PO3,
+	PMUX_PINGRP_ULPI_DATA3_PO4,
+	PMUX_PINGRP_ULPI_DATA4_PO5,
+	PMUX_PINGRP_ULPI_DATA5_PO6,
+	PMUX_PINGRP_ULPI_DATA6_PO7,
+	PMUX_PINGRP_ULPI_DATA7_PO0,
+	PMUX_PINGRP_ULPI_CLK_PY0,
+	PMUX_PINGRP_ULPI_DIR_PY1,
+	PMUX_PINGRP_ULPI_NXT_PY2,
+	PMUX_PINGRP_ULPI_STP_PY3,
+	PMUX_PINGRP_DAP3_FS_PP0,
+	PMUX_PINGRP_DAP3_DIN_PP1,
+	PMUX_PINGRP_DAP3_DOUT_PP2,
+	PMUX_PINGRP_DAP3_SCLK_PP3,
+	PMUX_PINGRP_PV0,
+	PMUX_PINGRP_PV1,
+	PMUX_PINGRP_SDMMC1_CLK_PZ0,
+	PMUX_PINGRP_SDMMC1_CMD_PZ1,
+	PMUX_PINGRP_SDMMC1_DAT3_PY4,
+	PMUX_PINGRP_SDMMC1_DAT2_PY5,
+	PMUX_PINGRP_SDMMC1_DAT1_PY6,
+	PMUX_PINGRP_SDMMC1_DAT0_PY7,
+	PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+	PMUX_PINGRP_CLK2_REQ_PCC5,
+	PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+	PMUX_PINGRP_DDC_SCL_PV4,
+	PMUX_PINGRP_DDC_SDA_PV5,
+	PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+	PMUX_PINGRP_UART2_TXD_PC2,
+	PMUX_PINGRP_UART2_RTS_N_PJ6,
+	PMUX_PINGRP_UART2_CTS_N_PJ5,
+	PMUX_PINGRP_UART3_TXD_PW6,
+	PMUX_PINGRP_UART3_RXD_PW7,
+	PMUX_PINGRP_UART3_CTS_N_PA1,
+	PMUX_PINGRP_UART3_RTS_N_PC0,
+	PMUX_PINGRP_PU0,
+	PMUX_PINGRP_PU1,
+	PMUX_PINGRP_PU2,
+	PMUX_PINGRP_PU3,
+	PMUX_PINGRP_PU4,
+	PMUX_PINGRP_PU5,
+	PMUX_PINGRP_PU6,
+	PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+	PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+	PMUX_PINGRP_DAP4_FS_PP4,
+	PMUX_PINGRP_DAP4_DIN_PP5,
+	PMUX_PINGRP_DAP4_DOUT_PP6,
+	PMUX_PINGRP_DAP4_SCLK_PP7,
+	PMUX_PINGRP_CLK3_OUT_PEE0,
+	PMUX_PINGRP_CLK3_REQ_PEE1,
+	PMUX_PINGRP_PC7,
+	PMUX_PINGRP_PI5,
+	PMUX_PINGRP_PI7,
+	PMUX_PINGRP_PK0,
+	PMUX_PINGRP_PK1,
+	PMUX_PINGRP_PJ0,
+	PMUX_PINGRP_PJ2,
+	PMUX_PINGRP_PK3,
+	PMUX_PINGRP_PK4,
+	PMUX_PINGRP_PK2,
+	PMUX_PINGRP_PI3,
+	PMUX_PINGRP_PI6,
+	PMUX_PINGRP_PG0,
+	PMUX_PINGRP_PG1,
+	PMUX_PINGRP_PG2,
+	PMUX_PINGRP_PG3,
+	PMUX_PINGRP_PG4,
+	PMUX_PINGRP_PG5,
+	PMUX_PINGRP_PG6,
+	PMUX_PINGRP_PG7,
+	PMUX_PINGRP_PH0,
+	PMUX_PINGRP_PH1,
+	PMUX_PINGRP_PH2,
+	PMUX_PINGRP_PH3,
+	PMUX_PINGRP_PH4,
+	PMUX_PINGRP_PH5,
+	PMUX_PINGRP_PH6,
+	PMUX_PINGRP_PH7,
+	PMUX_PINGRP_PJ7,
+	PMUX_PINGRP_PB0,
+	PMUX_PINGRP_PB1,
+	PMUX_PINGRP_PK7,
+	PMUX_PINGRP_PI0,
+	PMUX_PINGRP_PI1,
+	PMUX_PINGRP_PI2,
+	PMUX_PINGRP_PI4,
+	PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+	PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+	PMUX_PINGRP_SDMMC4_CLK_PCC4,
+	PMUX_PINGRP_SDMMC4_CMD_PT7,
+	PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+	PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+	PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+	PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+	PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+	PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+	PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+	PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+	PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+	PMUX_PINGRP_PCC1,
+	PMUX_PINGRP_PBB0,
+	PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+	PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+	PMUX_PINGRP_PBB3,
+	PMUX_PINGRP_PBB4,
+	PMUX_PINGRP_PBB5,
+	PMUX_PINGRP_PBB6,
+	PMUX_PINGRP_PBB7,
+	PMUX_PINGRP_PCC2,
+	PMUX_PINGRP_JTAG_RTCK,
+	PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+	PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+	PMUX_PINGRP_KB_ROW0_PR0,
+	PMUX_PINGRP_KB_ROW1_PR1,
+	PMUX_PINGRP_KB_ROW2_PR2,
+	PMUX_PINGRP_KB_ROW3_PR3,
+	PMUX_PINGRP_KB_ROW4_PR4,
+	PMUX_PINGRP_KB_ROW5_PR5,
+	PMUX_PINGRP_KB_ROW6_PR6,
+	PMUX_PINGRP_KB_ROW7_PR7,
+	PMUX_PINGRP_KB_ROW8_PS0,
+	PMUX_PINGRP_KB_ROW9_PS1,
+	PMUX_PINGRP_KB_ROW10_PS2,
+	PMUX_PINGRP_KB_ROW11_PS3,
+	PMUX_PINGRP_KB_ROW12_PS4,
+	PMUX_PINGRP_KB_ROW13_PS5,
+	PMUX_PINGRP_KB_ROW14_PS6,
+	PMUX_PINGRP_KB_ROW15_PS7,
+	PMUX_PINGRP_KB_COL0_PQ0,
+	PMUX_PINGRP_KB_COL1_PQ1,
+	PMUX_PINGRP_KB_COL2_PQ2,
+	PMUX_PINGRP_KB_COL3_PQ3,
+	PMUX_PINGRP_KB_COL4_PQ4,
+	PMUX_PINGRP_KB_COL5_PQ5,
+	PMUX_PINGRP_KB_COL6_PQ6,
+	PMUX_PINGRP_KB_COL7_PQ7,
+	PMUX_PINGRP_CLK_32K_OUT_PA0,
+	PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
+	PMUX_PINGRP_CPU_PWR_REQ,
+	PMUX_PINGRP_PWR_INT_N,
+	PMUX_PINGRP_CLK_32K_IN,
+	PMUX_PINGRP_OWR,
+	PMUX_PINGRP_DAP1_FS_PN0,
+	PMUX_PINGRP_DAP1_DIN_PN1,
+	PMUX_PINGRP_DAP1_DOUT_PN2,
+	PMUX_PINGRP_DAP1_SCLK_PN3,
+	PMUX_PINGRP_DAP_MCLK1_REQ_PEE2,
+	PMUX_PINGRP_DAP_MCLK1_PW4,
+	PMUX_PINGRP_SPDIF_IN_PK6,
+	PMUX_PINGRP_SPDIF_OUT_PK5,
+	PMUX_PINGRP_DAP2_FS_PA2,
+	PMUX_PINGRP_DAP2_DIN_PA4,
+	PMUX_PINGRP_DAP2_DOUT_PA5,
+	PMUX_PINGRP_DAP2_SCLK_PA3,
+	PMUX_PINGRP_DVFS_PWM_PX0,
+	PMUX_PINGRP_GPIO_X1_AUD_PX1,
+	PMUX_PINGRP_GPIO_X3_AUD_PX3,
+	PMUX_PINGRP_DVFS_CLK_PX2,
+	PMUX_PINGRP_GPIO_X4_AUD_PX4,
+	PMUX_PINGRP_GPIO_X5_AUD_PX5,
+	PMUX_PINGRP_GPIO_X6_AUD_PX6,
+	PMUX_PINGRP_GPIO_X7_AUD_PX7,
+	PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+	PMUX_PINGRP_SDMMC3_CMD_PA7,
+	PMUX_PINGRP_SDMMC3_DAT0_PB7,
+	PMUX_PINGRP_SDMMC3_DAT1_PB6,
+	PMUX_PINGRP_SDMMC3_DAT2_PB5,
+	PMUX_PINGRP_SDMMC3_DAT3_PB4,
+	PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
+	PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
+	PMUX_PINGRP_PEX_WAKE_N_PDD3,
+	PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
+	PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
+	PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+	PMUX_PINGRP_SDMMC1_WP_N_PV3,
+	PMUX_PINGRP_SDMMC3_CD_N_PV2,
+	PMUX_PINGRP_GPIO_W2_AUD_PW2,
+	PMUX_PINGRP_GPIO_W3_AUD_PW3,
+	PMUX_PINGRP_USB_VBUS_EN0_PN4,
+	PMUX_PINGRP_USB_VBUS_EN1_PN5,
+	PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+	PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+	PMUX_PINGRP_GMI_CLK_LB,
+	PMUX_PINGRP_RESET_OUT_N,
+	PMUX_PINGRP_KB_ROW16_PT0,
+	PMUX_PINGRP_KB_ROW17_PT1,
+	PMUX_PINGRP_USB_VBUS_EN2_PFF1,
+	PMUX_PINGRP_PFF2,
+	PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
+	PMUX_PINGRP_COUNT,
+};
+
+enum pmux_drvgrp {
+	PMUX_DRVGRP_AO1,
+	PMUX_DRVGRP_AO2,
+	PMUX_DRVGRP_AT1,
+	PMUX_DRVGRP_AT2,
+	PMUX_DRVGRP_AT3,
+	PMUX_DRVGRP_AT4,
+	PMUX_DRVGRP_AT5,
+	PMUX_DRVGRP_CDEV1,
+	PMUX_DRVGRP_CDEV2,
+	PMUX_DRVGRP_DAP1 = (0x28 / 4),
+	PMUX_DRVGRP_DAP2,
+	PMUX_DRVGRP_DAP3,
+	PMUX_DRVGRP_DAP4,
+	PMUX_DRVGRP_DBG,
+	PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+	PMUX_DRVGRP_SPI,
+	PMUX_DRVGRP_UAA,
+	PMUX_DRVGRP_UAB,
+	PMUX_DRVGRP_UART2,
+	PMUX_DRVGRP_UART3,
+	PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+	PMUX_DRVGRP_DDC = (0x94 / 4),
+	PMUX_DRVGRP_GMA,
+	PMUX_DRVGRP_GME = (0xa8 / 4),
+	PMUX_DRVGRP_GMF,
+	PMUX_DRVGRP_GMG,
+	PMUX_DRVGRP_GMH,
+	PMUX_DRVGRP_OWR,
+	PMUX_DRVGRP_UDA,
+	PMUX_DRVGRP_GPV,
+	PMUX_DRVGRP_DEV3,
+	PMUX_DRVGRP_CEC = (0xd0 / 4),
+	PMUX_DRVGRP_AT6 = (0x12c / 4),
+	PMUX_DRVGRP_DAP5,
+	PMUX_DRVGRP_USB_VBUS_EN,
+	PMUX_DRVGRP_AO3 = (0x140 / 4),
+	PMUX_DRVGRP_AO0 = (0x148 / 4),
+	PMUX_DRVGRP_HV0,
+	PMUX_DRVGRP_SDIO4 = (0x15c / 4),
+	PMUX_DRVGRP_AO4,
+	PMUX_DRVGRP_COUNT,
+};
+
+enum pmux_mipipadctrlgrp {
+	PMUX_MIPIPADCTRLGRP_DSI_B,
+	PMUX_MIPIPADCTRLGRP_COUNT,
+};
+
+enum pmux_func {
+	PMUX_FUNC_DEFAULT,
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CCLA,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLDVFS,
+	PMUX_FUNC_CLK,
+	PMUX_FUNC_CLK12,
+	PMUX_FUNC_CPU,
+	PMUX_FUNC_CSI,
+	PMUX_FUNC_DAP,
+	PMUX_FUNC_DAP1,
+	PMUX_FUNC_DAP2,
+	PMUX_FUNC_DEV3,
+	PMUX_FUNC_DISPLAYA,
+	PMUX_FUNC_DISPLAYA_ALT,
+	PMUX_FUNC_DISPLAYB,
+	PMUX_FUNC_DP,
+	PMUX_FUNC_DSI_B,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_EXTPERIPH1,
+	PMUX_FUNC_EXTPERIPH2,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_ALT,
+	PMUX_FUNC_HDA,
+	PMUX_FUNC_HSI,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_I2C4,
+	PMUX_FUNC_I2CPWR,
+	PMUX_FUNC_I2S0,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4,
+	PMUX_FUNC_IRDA,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PE,
+	PMUX_FUNC_PE0,
+	PMUX_FUNC_PE1,
+	PMUX_FUNC_PMI,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_PWRON,
+	PMUX_FUNC_RESET_OUT_N,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SATA,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC2,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SDMMC4,
+	PMUX_FUNC_SOC,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_SPI5,
+	PMUX_FUNC_SPI6,
+	PMUX_FUNC_SYS,
+	PMUX_FUNC_TMDS,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_USB,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_ALT1,
+	PMUX_FUNC_VI_ALT3,
+	PMUX_FUNC_VIMCLK2,
+	PMUX_FUNC_VIMCLK2_ALT,
+	PMUX_FUNC_RSVD1,
+	PMUX_FUNC_RSVD2,
+	PMUX_FUNC_RSVD3,
+	PMUX_FUNC_RSVD4,
+	PMUX_FUNC_COUNT,
+};
+
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820
+#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
+#define TEGRA_PMX_PINS_HAVE_RCV_SEL
+#include <asm/arch-tegra/pinmux.h>
+
+#endif /* _TEGRA124_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/powergate.h b/arch/arm/include/asm/arch-tegra124/powergate.h
new file mode 100644
index 0000000..8a0cfba
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/powergate.h
@@ -0,0 +1,6 @@
+#ifndef _TEGRA124_POWERGATE_H_
+#define _TEGRA124_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA124_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pwm.h b/arch/arm/include/asm/arch-tegra124/pwm.h
new file mode 100644
index 0000000..9ab23e8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/pwm.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_ARCH_TEGRA124_PWM_H
+#define __ASM_ARCH_TEGRA124_PWM_H
+
+#include <asm/arch-tegra/pwm.h>
+
+#endif	/* __ASM_ARCH_TEGRA124_PWM_H */
diff --git a/arch/arm/include/asm/arch-tegra124/sysctr.h b/arch/arm/include/asm/arch-tegra124/sysctr.h
new file mode 100644
index 0000000..6567104
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/sysctr.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA124_SYSCTR_H_
+#define _TEGRA124_SYSCTR_H_
+
+struct sysctr_ctlr {
+	u32 cntcr;		/* 0x00: SYSCTR0_CNTCR Counter Control */
+	u32 cntsr;		/* 0x04: SYSCTR0_CNTSR Counter Status */
+	u32 cntcv0;		/* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+	u32 cntcv1;		/* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+	u32 reserved1[4];	/* 0x10 - 0x1C */
+	u32 cntfid0;		/* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+	u32 cntfid1;		/* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+	u32 reserved2[1002];	/* 0x28 - 0xFCC */
+	u32 counterid[12];	/* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
+#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
+
+#endif	/* _TEGRA124_SYSCTR_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h
new file mode 100644
index 0000000..34070b8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/tegra.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA124_H_
+#define _TEGRA124_H_
+
+#define NV_PA_SDRAM_BASE	0x80000000
+#define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
+#define NV_PA_MC_BASE		0x70019000	/* Mem Ctlr regs (MCB, etc.) */
+#define NV_PA_AHB_BASE		0x6000C000	/* System regs (AHB, etc.) */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET	1704	/* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE	0x48	/* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR	0x4C	/* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU		4
+#define MCB_EMEM_ARB_OVERRIDE	(NV_PA_MC_BASE + 0xE8)
+
+#define TEGRA_USB1_BASE		0x7D000000
+
+#endif /* _TEGRA124_H_ */
diff --git a/arch/arm/include/asm/arch-tegra186/gpio.h b/arch/arm/include/asm/arch-tegra186/gpio.h
new file mode 100644
index 0000000..8b7e409
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _TEGRA186_GPIO_H_
+#define _TEGRA186_GPIO_H_
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra186/tegra.h b/arch/arm/include/asm/arch-tegra186/tegra.h
new file mode 100644
index 0000000..d86cedb
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/tegra.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2013-2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _TEGRA186_TEGRA_H_
+#define _TEGRA186_TEGRA_H_
+
+#define GICD_BASE		0x03881000	/* Generic Int Cntrlr Distrib */
+#define GICC_BASE		0x03882000	/* Generic Int Cntrlr CPU I/F */
+#define NV_PA_SDRAM_BASE	0x80000000
+
+#include <asm/arch-tegra/tegra.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h
new file mode 100644
index 0000000..861b3d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com>
+ */
+
+/* Tegra20 clock PLL tables */
+
+#ifndef _CLOCK_TABLES_H_
+#define _CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SOC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+	CLOCK_ID_CLK_M,
+
+	CLOCK_ID_COUNT,	/* number of clocks */
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_RESERVED1,
+	PERIPH_ID_RESERVED2,
+	PERIPH_ID_AC97,
+	PERIPH_ID_RTC,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_NDFLASH,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_TWC,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_EPP,
+	PERIPH_ID_VI,
+	PERIPH_ID_2D,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_3D,
+	PERIPH_ID_IDE,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_RESERVED30,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_KBC,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_PMC,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_SPI1,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_XIO,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_DVC_I2C,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_TVO,
+	PERIPH_ID_MIPI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_TVDAC,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_RESERVED56,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_MPE,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 */
+	PERIPH_ID_SPEEDO,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_RESERVED76,
+	PERIPH_ID_RESERVED77,
+	PERIPH_ID_RESERVED78,
+	PERIPH_ID_RESERVED79,
+
+	/* 80 */
+	PERIPH_ID_RESERVED80,
+	PERIPH_ID_RESERVED81,
+	PERIPH_ID_RESERVED82,
+	PERIPH_ID_RESERVED83,
+	PERIPH_ID_IRAMA,
+	PERIPH_ID_IRAMB,
+	PERIPH_ID_IRAMC,
+	PERIPH_ID_IRAMD,
+
+	/* 88 */
+	PERIPH_ID_CRAM2,
+	PERIPH_ID_SYNC_CLK_DOUBLER,
+	PERIPH_ID_CLK_M_DOUBLER,
+	PERIPH_ID_RESERVED91,
+	PERIPH_ID_SUS_OUT,
+	PERIPH_ID_DEV2_OUT,
+	PERIPH_ID_DEV1_OUT,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
+#define PERIPH_REG(id) ((id) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range, and not a simple PLL */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
+		(id) < CLOCK_ID_FIRST_SIMPLE)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/clock.h b/arch/arm/include/asm/arch-tegra20/clock.h
new file mode 100644
index 0000000..8158b83
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/clock.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+/* Tegra20 clock control functions */
+
+#ifndef _TEGRA20_CLOCK_H
+#define _TEGRA20_CLOCK_H
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          30
+#define OSC_FREQ_MASK           (3U << OSC_FREQ_SHIFT)
+
+int tegra_plle_enable(void);
+
+#endif	/* _TEGRA20_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h
new file mode 100644
index 0000000..e7b3cff
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/display.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
+#define __ASM_ARCH_TEGRA_DISPLAY_H
+
+#include <asm/arch-tegra/dc.h>
+
+/* This holds information about a window which can be displayed */
+struct disp_ctl_win {
+	enum win_color_depth_id fmt;	/* Color depth/format */
+	unsigned	bpp;		/* Bits per pixel */
+	phys_addr_t	phys_addr;	/* Physical address in memory */
+	unsigned	x;		/* Horizontal address offset (bytes) */
+	unsigned	y;		/* Veritical address offset (bytes) */
+	unsigned	w;		/* Width of source window */
+	unsigned	h;		/* Height of source window */
+	unsigned	stride;		/* Number of bytes per line */
+	unsigned	out_x;		/* Left edge of output window (col) */
+	unsigned	out_y;		/* Top edge of output window (row) */
+	unsigned	out_w;		/* Width of output window in pixels */
+	unsigned	out_h;		/* Height of output window in pixels */
+};
+
+#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
diff --git a/arch/arm/include/asm/arch-tegra20/emc.h b/arch/arm/include/asm/arch-tegra20/emc.h
new file mode 100644
index 0000000..58ee08c
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/emc.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _ARCH_EMC_H_
+#define _ARCH_EMC_H_
+
+#include <asm/types.h>
+
+#define TEGRA_EMC_NUM_REGS	46
+
+/* EMC Registers */
+struct emc_ctlr {
+	u32 cfg;		/* 0x00: EMC_CFG */
+	u32 reserved0[3];	/* 0x04 ~ 0x0C */
+	u32 adr_cfg;		/* 0x10: EMC_ADR_CFG */
+	u32 adr_cfg1;		/* 0x14: EMC_ADR_CFG_1 */
+	u32 reserved1[2];	/* 0x18 ~ 0x18 */
+	u32 refresh_ctrl;	/* 0x20: EMC_REFCTRL */
+	u32 pin;		/* 0x24: EMC_PIN */
+	u32 timing_ctrl;	/* 0x28: EMC_TIMING_CONTROL */
+	u32 rc;			/* 0x2C: EMC_RC */
+	u32 rfc;		/* 0x30: EMC_RFC */
+	u32 ras;		/* 0x34: EMC_RAS */
+	u32 rp;			/* 0x38: EMC_RP */
+	u32 r2w;		/* 0x3C: EMC_R2W */
+	u32 w2r;		/* 0x40: EMC_W2R */
+	u32 r2p;		/* 0x44: EMC_R2P */
+	u32 w2p;		/* 0x48: EMC_W2P */
+	u32 rd_rcd;		/* 0x4C: EMC_RD_RCD */
+	u32 wd_rcd;		/* 0x50: EMC_WD_RCD */
+	u32 rrd;		/* 0x54: EMC_RRD */
+	u32 rext;		/* 0x58: EMC_REXT */
+	u32 wdv;		/* 0x5C: EMC_WDV */
+	u32 quse;		/* 0x60: EMC_QUSE */
+	u32 qrst;		/* 0x64: EMC_QRST */
+	u32 qsafe;		/* 0x68: EMC_QSAFE */
+	u32 rdv;		/* 0x6C: EMC_RDV */
+	u32 refresh;		/* 0x70: EMC_REFRESH */
+	u32 burst_refresh_num;	/* 0x74: EMC_BURST_REFRESH_NUM */
+	u32 pdex2wr;		/* 0x78: EMC_PDEX2WR */
+	u32 pdex2rd;		/* 0x7c: EMC_PDEX2RD */
+	u32 pchg2pden;		/* 0x80: EMC_PCHG2PDEN */
+	u32 act2pden;		/* 0x84: EMC_ACT2PDEN */
+	u32 ar2pden;		/* 0x88: EMC_AR2PDEN */
+	u32 rw2pden;		/* 0x8C: EMC_RW2PDEN */
+	u32 txsr;		/* 0x90: EMC_TXSR */
+	u32 tcke;		/* 0x94: EMC_TCKE */
+	u32 tfaw;		/* 0x98: EMC_TFAW */
+	u32 trpab;		/* 0x9C: EMC_TRPAB */
+	u32 tclkstable;		/* 0xA0: EMC_TCLKSTABLE */
+	u32 tclkstop;		/* 0xA4: EMC_TCLKSTOP */
+	u32 trefbw;		/* 0xA8: EMC_TREFBW */
+	u32 quse_extra;		/* 0xAC: EMC_QUSE_EXTRA */
+	u32 odt_write;		/* 0xB0: EMC_ODT_WRITE */
+	u32 odt_read;		/* 0xB4: EMC_ODT_READ */
+	u32 reserved2[5];	/* 0xB8 ~ 0xC8 */
+	u32 mrs;		/* 0xCC: EMC_MRS */
+	u32 emrs;		/* 0xD0: EMC_EMRS */
+	u32 ref;		/* 0xD4: EMC_REF */
+	u32 pre;		/* 0xD8: EMC_PRE */
+	u32 nop;		/* 0xDC: EMC_NOP */
+	u32 self_ref;		/* 0xE0: EMC_SELF_REF */
+	u32 dpd;		/* 0xE4: EMC_DPD */
+	u32 mrw;		/* 0xE8: EMC_MRW */
+	u32 mrr;		/* 0xEC: EMC_MRR */
+	u32 reserved3;		/* 0xF0: */
+	u32 fbio_cfg1;		/* 0xF4: EMC_FBIO_CFG1 */
+	u32 fbio_dqsib_dly;	/* 0xF8: EMC_FBIO_DQSIB_DLY */
+	u32 fbio_dqsib_dly_msb;	/* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */
+	u32 fbio_spare;		/* 0x100: SBIO_SPARE */
+				/* There are more registers ... */
+};
+
+/**
+ * Set up the EMC for the given rate. The timing parameters are retrieved
+ * from the device tree "nvidia,tegra20-emc" node and its
+ * "nvidia,tegra20-emc-table" sub-nodes.
+ *
+ * @param blob	Device tree blob
+ * @param rate	Clock speed of memory controller in Hz (=2x memory bus rate)
+ * @return 0 if ok, else -ve error code (look in emc.c to decode it)
+ */
+int tegra_set_emc(const void *blob, unsigned rate);
+
+/**
+ * Get a pointer to the EMC controller from the device tree.
+ *
+ * @param blob	Device tree blob
+ * @return pointer to EMC controller
+ */
+struct emc_ctlr *emc_get_controller(const void *blob);
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra20/flow.h b/arch/arm/include/asm/arch-tegra20/flow.h
new file mode 100644
index 0000000..33be841
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/flow.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010, 2011
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _FLOW_H_
+#define _FLOW_H_
+
+struct flow_ctlr {
+	u32	halt_cpu_events;
+	u32	halt_cop_events;
+	u32	cpu_csr;
+	u32	cop_csr;
+	u32	halt_cpu1_events;
+	u32	cpu1_csr;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h
new file mode 100644
index 0000000..e9e96c1
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/funcmux.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+/* Tegra20 high-level function multiplexing */
+
+#ifndef _TEGRA20_FUNCMUX_H_
+#define _TEGRA20_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART1_IRRX_IRTX = 0,
+	FUNCMUX_UART1_UAA_UAB,
+	FUNCMUX_UART1_GPU,
+	FUNCMUX_UART1_SDIO1,
+	FUNCMUX_UART2_UAD = 0,
+	FUNCMUX_UART4_GMC = 0,
+
+	/* I2C configs */
+	FUNCMUX_DVC_I2CP = 0,
+	FUNCMUX_I2C1_RM = 0,
+	FUNCMUX_I2C2_DDC = 0,
+	FUNCMUX_I2C2_PTA,
+	FUNCMUX_I2C3_DTF = 0,
+
+	/* SDMMC configs */
+	FUNCMUX_SDMMC1_SDIO1_4BIT = 0,
+	FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0,
+	FUNCMUX_SDMMC3_SDB_4BIT = 0,
+	FUNCMUX_SDMMC3_SDB_SLXA_8BIT,
+	FUNCMUX_SDMMC4_ATC_ATD_8BIT = 0,
+	FUNCMUX_SDMMC4_ATB_GMA_4_BIT,
+	FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT,
+
+	/* USB configs */
+	FUNCMUX_USB2_ULPI = 0,
+
+	/* Serial Flash configs */
+	FUNCMUX_SPI1_GMC_GMD = 0,
+
+	/* NAND flags */
+	FUNCMUX_NDFLASH_ATC = 0,
+	FUNCMUX_NDFLASH_KBC_8_BIT,
+};
+#endif	/* _TEGRA20_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
new file mode 100644
index 0000000..dd2ee12
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA20_GP_PADCTRL_H_
+#define _TEGRA20_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	cdevcfg1;	/* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdevcfg2;	/* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	csuscfg;	/* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */
+	u32	dap1cfg;	/* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0x94: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	lcdcfg1;	/* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */
+	u32	lcdcfg2;	/* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */
+	u32	sdmmc2_cfg;	/* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */
+	u32	sdmmc3_cfg;	/* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */
+	u32	spicfg;		/* 0xA8: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xAC: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xB0: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	vicfg1;		/* 0xBC: APB_MISC_GP_VICFG1PADCTRL */
+	u32	vicfg2;		/* 0xC0: APB_MISC_GP_VICFG2PADCTRL */
+	u32	xm2cfga;	/* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */
+	u32	xm2cfgc;	/* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */
+	u32	xm2cfgd;	/* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */
+	u32	xm2clkcfg;	/* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */
+	u32	memcomp;	/* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
+};
+
+#endif	/* _TEGRA20_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h
new file mode 100644
index 0000000..6818c28
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/gpio.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * Portions Copyright 2011-2012 NVIDIA Corporation
+ */
+
+#ifndef _TEGRA20_GPIO_H_
+#define _TEGRA20_GPIO_H_
+
+/*
+ * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	7	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+#endif	/* TEGRA20_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/mc.h b/arch/arm/include/asm/arch-tegra20/mc.h
new file mode 100644
index 0000000..71283e4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/mc.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2014
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA20_MC_H_
+#define _TEGRA20_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+	u32 reserved0[3];			/* offset 0x00 - 0x08 */
+	u32 mc_emem_cfg;			/* offset 0x0C */
+	u32 mc_emem_adr_cfg;			/* offset 0x10 */
+	u32 mc_emem_arb_cfg0;			/* offset 0x14 */
+	u32 mc_emem_arb_cfg1;			/* offset 0x18 */
+	u32 mc_emem_arb_cfg2;			/* offset 0x1C */
+	u32 reserved1;				/* offset 0x20 */
+	u32 mc_gart_cfg;			/* offset 0x24 */
+	u32 mc_gart_entry_addr;			/* offset 0x28 */
+	u32 mc_gart_entry_data;			/* offset 0x2C */
+	u32 mc_gart_error_req;			/* offset 0x30 */
+	u32 mc_gart_error_addr;			/* offset 0x34 */
+	u32 reserved2;				/* offset 0x38 */
+	u32 mc_timeout_ctrl;			/* offset 0x3C */
+	u32 reserved3[6];			/* offset 0x40 - 0x54 */
+	u32 mc_decerr_emem_others_status;	/* offset 0x58 */
+	u32 mc_decerr_emem_others_adr;		/* offset 0x5C */
+	u32 reserved4[40];			/* offset 0x60 - 0xFC */
+	u32 reserved5[93];			/* offset 0x100 - 0x270 */
+};
+
+#endif	/* _TEGRA20_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
new file mode 100644
index 0000000..e9e3801
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -0,0 +1,238 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA20_PINMUX_H_
+#define _TEGRA20_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ *	- function
+ *	- pullup / pulldown
+ *	- tristate or normal
+ */
+enum pmux_pingrp {
+	/* APB_MISC_PP_TRISTATE_REG_A_0 */
+	PMUX_PINGRP_ATA,
+	PMUX_PINGRP_ATB,
+	PMUX_PINGRP_ATC,
+	PMUX_PINGRP_ATD,
+	PMUX_PINGRP_CDEV1,
+	PMUX_PINGRP_CDEV2,
+	PMUX_PINGRP_CSUS,
+	PMUX_PINGRP_DAP1,
+
+	PMUX_PINGRP_DAP2,
+	PMUX_PINGRP_DAP3,
+	PMUX_PINGRP_DAP4,
+	PMUX_PINGRP_DTA,
+	PMUX_PINGRP_DTB,
+	PMUX_PINGRP_DTC,
+	PMUX_PINGRP_DTD,
+	PMUX_PINGRP_DTE,
+
+	PMUX_PINGRP_GPU,
+	PMUX_PINGRP_GPV,
+	PMUX_PINGRP_I2CP,
+	PMUX_PINGRP_IRTX,
+	PMUX_PINGRP_IRRX,
+	PMUX_PINGRP_KBCB,
+	PMUX_PINGRP_KBCA,
+	PMUX_PINGRP_PMC,
+
+	PMUX_PINGRP_PTA,
+	PMUX_PINGRP_RM,
+	PMUX_PINGRP_KBCE,
+	PMUX_PINGRP_KBCF,
+	PMUX_PINGRP_GMA,
+	PMUX_PINGRP_GMC,
+	PMUX_PINGRP_SDIO1,
+	PMUX_PINGRP_OWC,
+
+	/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
+	PMUX_PINGRP_GME,
+	PMUX_PINGRP_SDC,
+	PMUX_PINGRP_SDD,
+	PMUX_PINGRP_RESERVED0,
+	PMUX_PINGRP_SLXA,
+	PMUX_PINGRP_SLXC,
+	PMUX_PINGRP_SLXD,
+	PMUX_PINGRP_SLXK,
+
+	PMUX_PINGRP_SPDI,
+	PMUX_PINGRP_SPDO,
+	PMUX_PINGRP_SPIA,
+	PMUX_PINGRP_SPIB,
+	PMUX_PINGRP_SPIC,
+	PMUX_PINGRP_SPID,
+	PMUX_PINGRP_SPIE,
+	PMUX_PINGRP_SPIF,
+
+	PMUX_PINGRP_SPIG,
+	PMUX_PINGRP_SPIH,
+	PMUX_PINGRP_UAA,
+	PMUX_PINGRP_UAB,
+	PMUX_PINGRP_UAC,
+	PMUX_PINGRP_UAD,
+	PMUX_PINGRP_UCA,
+	PMUX_PINGRP_UCB,
+
+	PMUX_PINGRP_RESERVED1,
+	PMUX_PINGRP_ATE,
+	PMUX_PINGRP_KBCC,
+	PMUX_PINGRP_RESERVED2,
+	PMUX_PINGRP_RESERVED3,
+	PMUX_PINGRP_GMB,
+	PMUX_PINGRP_GMD,
+	PMUX_PINGRP_DDC,
+
+	/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
+	PMUX_PINGRP_LD0,
+	PMUX_PINGRP_LD1,
+	PMUX_PINGRP_LD2,
+	PMUX_PINGRP_LD3,
+	PMUX_PINGRP_LD4,
+	PMUX_PINGRP_LD5,
+	PMUX_PINGRP_LD6,
+	PMUX_PINGRP_LD7,
+
+	PMUX_PINGRP_LD8,
+	PMUX_PINGRP_LD9,
+	PMUX_PINGRP_LD10,
+	PMUX_PINGRP_LD11,
+	PMUX_PINGRP_LD12,
+	PMUX_PINGRP_LD13,
+	PMUX_PINGRP_LD14,
+	PMUX_PINGRP_LD15,
+
+	PMUX_PINGRP_LD16,
+	PMUX_PINGRP_LD17,
+	PMUX_PINGRP_LHP0,
+	PMUX_PINGRP_LHP1,
+	PMUX_PINGRP_LHP2,
+	PMUX_PINGRP_LVP0,
+	PMUX_PINGRP_LVP1,
+	PMUX_PINGRP_HDINT,
+
+	PMUX_PINGRP_LM0,
+	PMUX_PINGRP_LM1,
+	PMUX_PINGRP_LVS,
+	PMUX_PINGRP_LSC0,
+	PMUX_PINGRP_LSC1,
+	PMUX_PINGRP_LSCK,
+	PMUX_PINGRP_LDC,
+	PMUX_PINGRP_LCSN,
+
+	/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
+	PMUX_PINGRP_LSPI,
+	PMUX_PINGRP_LSDA,
+	PMUX_PINGRP_LSDI,
+	PMUX_PINGRP_LPW0,
+	PMUX_PINGRP_LPW1,
+	PMUX_PINGRP_LPW2,
+	PMUX_PINGRP_LDI,
+	PMUX_PINGRP_LHS,
+
+	PMUX_PINGRP_LPP,
+	PMUX_PINGRP_RESERVED4,
+	PMUX_PINGRP_KBCD,
+	PMUX_PINGRP_GPU7,
+	PMUX_PINGRP_DTF,
+	PMUX_PINGRP_UDA,
+	PMUX_PINGRP_CRTP,
+	PMUX_PINGRP_SDB,
+
+	/* these pin groups only have pullup and pull down control */
+	PMUX_PINGRP_CK32,
+	PMUX_PINGRP_DDRC,
+	PMUX_PINGRP_PMCA,
+	PMUX_PINGRP_PMCB,
+	PMUX_PINGRP_PMCC,
+	PMUX_PINGRP_PMCD,
+	PMUX_PINGRP_PMCE,
+	PMUX_PINGRP_XM2C,
+	PMUX_PINGRP_XM2D,
+	PMUX_PINGRP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+	PMUX_FUNC_DEFAULT,
+	PMUX_FUNC_AHB_CLK,
+	PMUX_FUNC_APB_CLK,
+	PMUX_FUNC_AUDIO_SYNC,
+	PMUX_FUNC_CRT,
+	PMUX_FUNC_DAP1,
+	PMUX_FUNC_DAP2,
+	PMUX_FUNC_DAP3,
+	PMUX_FUNC_DAP4,
+	PMUX_FUNC_DAP5,
+	PMUX_FUNC_DISPA,
+	PMUX_FUNC_DISPB,
+	PMUX_FUNC_EMC_TEST0_DLL,
+	PMUX_FUNC_EMC_TEST1_DLL,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_INT,
+	PMUX_FUNC_HDMI,
+	PMUX_FUNC_I2C,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_IDE,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_MIO,
+	PMUX_FUNC_MIPI_HS,
+	PMUX_FUNC_NAND,
+	PMUX_FUNC_OSC,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PCIE,
+	PMUX_FUNC_PLLA_OUT,
+	PMUX_FUNC_PLLC_OUT1,
+	PMUX_FUNC_PLLM_OUT1,
+	PMUX_FUNC_PLLP_OUT2,
+	PMUX_FUNC_PLLP_OUT3,
+	PMUX_FUNC_PLLP_OUT4,
+	PMUX_FUNC_PWM,
+	PMUX_FUNC_PWR_INTR,
+	PMUX_FUNC_PWR_ON,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SDIO1,
+	PMUX_FUNC_SDIO2,
+	PMUX_FUNC_SDIO3,
+	PMUX_FUNC_SDIO4,
+	PMUX_FUNC_SFLASH,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI2_ALT,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_TWC,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_UARTE,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_SENSOR_CLK,
+	PMUX_FUNC_XIO,
+	PMUX_FUNC_RSVD1,
+	PMUX_FUNC_RSVD2,
+	PMUX_FUNC_RSVD3,
+	PMUX_FUNC_RSVD4,
+	PMUX_FUNC_COUNT,
+};
+
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#include <asm/arch-tegra/pinmux.h>
+
+#endif /* _TEGRA20_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/powergate.h b/arch/arm/include/asm/arch-tegra20/powergate.h
new file mode 100644
index 0000000..439d88b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/powergate.h
@@ -0,0 +1,6 @@
+#ifndef _TEGRA20_POWERGATE_H_
+#define _TEGRA20_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA20_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/pwm.h b/arch/arm/include/asm/arch-tegra20/pwm.h
new file mode 100644
index 0000000..9467617
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/pwm.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_ARCH_TEGRA20_PWM_H
+#define __ASM_ARCH_TEGRA20_PWM_H
+
+#include <asm/arch-tegra/pwm.h>
+
+#endif	/* __ASM_ARCH_TEGRA20_PWM_H */
diff --git a/arch/arm/include/asm/arch-tegra20/sdram_param.h b/arch/arm/include/asm/arch-tegra20/sdram_param.h
new file mode 100644
index 0000000..3d1405f
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/sdram_param.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010, 2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _SDRAM_PARAM_H_
+#define _SDRAM_PARAM_H_
+
+/*
+ * Defines the number of 32-bit words provided in each set of SDRAM parameters
+ * for arbitration configuration data.
+ */
+#define BCT_SDRAM_ARB_CONFIG_WORDS 27
+
+enum memory_type {
+	MEMORY_TYPE_NONE = 0,
+	MEMORY_TYPE_DDR,
+	MEMORY_TYPE_LPDDR,
+	MEMORY_TYPE_DDR2,
+	MEMORY_TYPE_LPDDR2,
+	MEMORY_TYPE_NUM,
+	MEMORY_TYPE_FORCE32 = 0x7FFFFFFF
+};
+
+/* Defines the SDRAM parameter structure */
+struct sdram_params {
+	enum memory_type memory_type;
+	u32 pllm_charge_pump_setup_control;
+	u32 pllm_loop_filter_setup_control;
+	u32 pllm_input_divider;
+	u32 pllm_feedback_divider;
+	u32 pllm_post_divider;
+	u32 pllm_stable_time;
+	u32 emc_clock_divider;
+	u32 emc_auto_cal_interval;
+	u32 emc_auto_cal_config;
+	u32 emc_auto_cal_wait;
+	u32 emc_pin_program_wait;
+	u32 emc_rc;
+	u32 emc_rfc;
+	u32 emc_ras;
+	u32 emc_rp;
+	u32 emc_r2w;
+	u32 emc_w2r;
+	u32 emc_r2p;
+	u32 emc_w2p;
+	u32 emc_rd_rcd;
+	u32 emc_wr_rcd;
+	u32 emc_rrd;
+	u32 emc_rext;
+	u32 emc_wdv;
+	u32 emc_quse;
+	u32 emc_qrst;
+	u32 emc_qsafe;
+	u32 emc_rdv;
+	u32 emc_refresh;
+	u32 emc_burst_refresh_num;
+	u32 emc_pdex2wr;
+	u32 emc_pdex2rd;
+	u32 emc_pchg2pden;
+	u32 emc_act2pden;
+	u32 emc_ar2pden;
+	u32 emc_rw2pden;
+	u32 emc_txsr;
+	u32 emc_tcke;
+	u32 emc_tfaw;
+	u32 emc_trpab;
+	u32 emc_tclkstable;
+	u32 emc_tclkstop;
+	u32 emc_trefbw;
+	u32 emc_quseextra;
+	u32 emc_fbioc_fg1;
+	u32 emc_fbio_dqsib_dly;
+	u32 emc_fbio_dqsib_dly_msb;
+	u32 emc_fbio_quse_dly;
+	u32 emc_fbio_quse_dly_msb;
+	u32 emc_fbio_cfg5;
+	u32 emc_fbio_cfg6;
+	u32 emc_fbio_spare;
+	u32 emc_mrs;
+	u32 emc_emrs;
+	u32 emc_mrw1;
+	u32 emc_mrw2;
+	u32 emc_mrw3;
+	u32 emc_mrw_reset_command;
+	u32 emc_mrw_reset_init_wait;
+	u32 emc_adr_cfg;
+	u32 emc_adr_cfg1;
+	u32 emc_emem_cfg;
+	u32 emc_low_latency_config;
+	u32 emc_cfg;
+	u32 emc_cfg2;
+	u32 emc_dbg;
+	u32 ahb_arbitration_xbar_ctrl;
+	u32 emc_cfg_dig_dll;
+	u32 emc_dll_xform_dqs;
+	u32 emc_dll_xform_quse;
+	u32 warm_boot_wait;
+	u32 emc_ctt_term_ctrl;
+	u32 emc_odt_write;
+	u32 emc_odt_read;
+	u32 emc_zcal_ref_cnt;
+	u32 emc_zcal_wait_cnt;
+	u32 emc_zcal_mrw_cmd;
+	u32 emc_mrs_reset_dll;
+	u32 emc_mrw_zq_init_dev0;
+	u32 emc_mrw_zq_init_dev1;
+	u32 emc_mrw_zq_init_wait;
+	u32 emc_mrs_reset_dll_wait;
+	u32 emc_emrs_emr2;
+	u32 emc_emrs_emr3;
+	u32 emc_emrs_ddr2_dll_enable;
+	u32 emc_mrs_ddr2_dll_reset;
+	u32 emc_emrs_ddr2_ocd_calib;
+	u32 emc_edr2_wait;
+	u32 emc_cfg_clktrim0;
+	u32 emc_cfg_clktrim1;
+	u32 emc_cfg_clktrim2;
+	u32 pmc_ddr_pwr;
+	u32 apb_misc_gp_xm2cfga_padctrl;
+	u32 apb_misc_gp_xm2cfgc_padctrl;
+	u32 apb_misc_gp_xm2cfgc_padctrl2;
+	u32 apb_misc_gp_xm2cfgd_padctrl;
+	u32 apb_misc_gp_xm2cfgd_padctrl2;
+	u32 apb_misc_gp_xm2clkcfg_padctrl;
+	u32 apb_misc_gp_xm2comp_padctrl;
+	u32 apb_misc_gp_xm2vttgen_padctrl;
+	u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS];
+};
+#endif
diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h
new file mode 100644
index 0000000..3fecbcd
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/tegra.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA20_H_
+#define _TEGRA20_H_
+
+#define NV_PA_SDRAM_BASE	0x00000000
+#define NV_PA_MC_BASE		0x7000F000
+
+#include <asm/arch-tegra/tegra.h>
+
+#define TEGRA_USB1_BASE		0xC5000000
+
+#define BCT_ODMDATA_OFFSET	4068	/* 12 bytes from end of BCT */
+
+#define MAX_NUM_CPU		2
+
+#endif	/* TEGRA20_H */
diff --git a/arch/arm/include/asm/arch-tegra210/ahb.h b/arch/arm/include/asm/arch-tegra210/ahb.h
new file mode 100644
index 0000000..8ecd6d9
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/ahb.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA210_AHB_H_
+#define _TEGRA210_AHB_H_
+
+struct ahb_ctlr {
+	u32 reserved0;			/* 00h */
+	u32 arbitration_disable;	/* _ARBITRATION_DISABLE_0,	04h */
+	u32 arbitration_priority_ctrl;	/* _ARBITRATION_PRIORITY_CTRL_0,08h */
+	u32 arbitration_usr_protect;	/* _ARBITRATION_USR_PROTECT_0,	0ch */
+	u32 gizmo_ahb_mem;		/* _GIZMO_AHB_MEM_0,		10h */
+	u32 gizmo_apb_dma;		/* _GIZMO_APB_DMA_0,		14h */
+	u32 reserved6[2];		/* 18h, 1ch */
+	u32 gizmo_usb;			/* _GIZMO_USB_0,		20h */
+	u32 gizmo_ahb_xbar_bridge;	/* _GIZMO_AHB_XBAR_BRIDGE_0,	24h */
+	u32 gizmo_cpu_ahb_bridge;	/* _GIZMO_CPU_AHB_BRIDGE_0,	28h */
+	u32 gizmo_cop_ahb_bridge;	/* _GIZMO_COP_AHB_BRIDGE_0,	2ch */
+	u32 gizmo_xbar_apb_ctlr;	/* _GIZMO_XBAR_APB_CTLR_0,	30h */
+	u32 gizmo_vcp_ahb_bridge;	/* _GIZMO_VCP_AHB_BRIDGE_0,	34h */
+	u32 reserved13[2];		/* 38h, 3ch */
+	u32 gizmo_nand;			/* _GIZMO_NAND_0,		40h */
+	u32 reserved15;			/* 44h */
+	u32 gizmo_sdmmc4;		/* _GIZMO_SDMMC4_0,		48h */
+	u32 reserved17;			/* 4ch */
+	u32 gizmo_se;			/* _GIZMO_SE_0,			50h */
+	u32 gizmo_tzram;		/* _GIZMO_TZRAM_0,		54h */
+	u32 reserved20[3];		/* 58h, 5ch, 60h */
+	u32 gizmo_bsev;			/* _GIZMO_BSEV_0,		64h */
+	u32 reserved22[3];		/* 68h, 6ch, 70h */
+	u32 gizmo_bsea;			/* _GIZMO_BSEA_0,		74h */
+	u32 gizmo_nor;			/* _GIZMO_NOR_0,		78h */
+	u32 gizmo_usb2;			/* _GIZMO_USB2_0,		7ch */
+	u32 gizmo_usb3;			/* _GIZMO_USB3_0,		80h */
+	u32 gizmo_sdmmc1;		/* _GIZMO_SDMMC1_0,		84h */
+	u32 gizmo_sdmmc2;		/* _GIZMO_SDMMC2_0,		88h */
+	u32 gizmo_sdmmc3;		/* _GIZMO_SDMMC3_0,		8ch */
+	u32 reserved30[13];		/* 90h ~ c0h */
+	u32 ahb_wrq_empty;		/* _AHB_WRQ_EMPTY_0,		c4h */
+	u32 reserved32[5];		/* c8h ~ d8h */
+	u32 ahb_mem_prefetch_cfg_x;	/* _AHB_MEM_PREFETCH_CFG_X_0,	dch */
+	u32 arbitration_xbar_ctrl;	/* _ARBITRATION_XBAR_CTRL_0,	e0h */
+	u32 ahb_mem_prefetch_cfg3;	/* _AHB_MEM_PREFETCH_CFG3_0,	e4h */
+	u32 ahb_mem_prefetch_cfg4;	/* _AHB_MEM_PREFETCH_CFG3_0,	e8h */
+	u32 avp_ppcs_rd_coh_status;	/* _AVP_PPCS_RD_COH_STATUS_0,	ech */
+	u32 ahb_mem_prefetch_cfg1;	/* _AHB_MEM_PREFETCH_CFG1_0,	f0h */
+	u32 ahb_mem_prefetch_cfg2;	/* _AHB_MEM_PREFETCH_CFG2_0,	f4h */
+	u32 ahbslvmem_status;		/* _AHBSLVMEM_STATUS_0, f8h */
+	/* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
+	u32 arbitration_ahb_mem_wrque_mst_id;
+	u32 arbitration_cpu_abort_addr;	/* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
+	u32 arbitration_cpu_abort_info;	/* _ARBITRATION_CPU_ABORT_INFO_0,104h */
+	u32 arbitration_cop_abort_addr;	/* _ARBITRATION_COP_ABORT_ADDR_0,108h */
+	u32 arbitration_cop_abort_info;	/* _ARBITRATION_COP_ABORT_INFO_0,10ch */
+	u32 reserved46[4];		/* 110h ~ 11ch */
+	u32 avpc_mccif_fifoctrl;	/* _AVPC_MCCIF_FIFOCTRL_0,	120h */
+	u32 timeout_wcoal_avpc;		/* _TIMEOUT_WCOAL_AVPC_0,	124h */
+	u32 mpcorelp_mccif_fifoctrl;	/* _MPCORELP_MCCIF_FIFOCTRL_0,	128h */
+	u32 mpcore_mccif_fifoctrl;	/* _MPCORE_MCCIF_FIFOCTRL_0,	12ch */
+	u32 axicif_fastsync_ctrl;	/* AXICIF_FASTSYNC_CTRL_0,	130h */
+	u32 axicif_fastsync_statistics;	/* _AXICIF_FASTSYNC_STATISTICS_0,134h */
+	/* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0,	138h */
+	u32 axicif_fastsync0_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
+	u32 axicif_fastsync1_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
+	u32 axicif_fastsync2_cpuclk_to_mcclk;
+	/* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
+	u32 axicif_fastsync0_mcclk_to_cpuclk;
+	/* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
+	u32 axicif_fastsync1_mcclk_to_cpuclk;
+	/* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
+	u32 axicif_fastsync2_mcclk_to_cpuclk;
+};
+
+#define PPSB_STOPCLK_ENABLE	(1 << 2)
+
+#define GIZ_ENABLE_SPLIT	(1 << 0)
+#define GIZ_ENB_FAST_REARB	(1 << 2)
+#define GIZ_DONT_SPLIT_AHB_WR	(1 << 7)
+
+#define GIZ_USB_IMMEDIATE	(1 << 18)
+
+/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
+#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE	(1 << 2)
+
+#endif	/* _TEGRA210_AHB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h
new file mode 100644
index 0000000..c6d7487
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h
@@ -0,0 +1,567 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+/* Tegra210 clock PLL tables */
+
+#ifndef _TEGRA210_CLOCK_TABLES_H_
+#define _TEGRA210_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+	CLOCK_ID_DP,
+
+	/* These are the base clocks (inputs to the Tegra SoC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+	CLOCK_ID_CLK_M,
+
+	CLOCK_ID_COUNT,	/* number of PLLs */
+
+	/*
+	 * These are clock IDs that are used in table clock_source[][]
+	 * but will not be assigned as a clock source for any peripheral.
+	 */
+	CLOCK_ID_DISPLAY2,
+	CLOCK_ID_CGENERAL_0,
+	CLOCK_ID_CGENERAL_1,
+	CLOCK_ID_CGENERAL2,
+	CLOCK_ID_CGENERAL3,
+	CLOCK_ID_CGENERAL4_0,
+	CLOCK_ID_CGENERAL4_1,
+	CLOCK_ID_CGENERAL4_2,
+	CLOCK_ID_MEMORY2,
+	CLOCK_ID_SRC2,
+
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 (DEVICES_L) */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_ISPB,
+	PERIPH_ID_RESERVED4,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_RESERVED13,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_TCW,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_RESERVED19,
+	PERIPH_ID_VI,
+	PERIPH_ID_RESERVED21,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_RESERVED25,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 (DEVICES_H) */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_RESERVED36,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_RESERVED38,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_XIO,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_I2C5,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_RESERVED49,
+	PERIPH_ID_HSI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_RESERVED53,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_MIPI_CAL,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_RESERVED60,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 (DEVICES_U) */
+	PERIPH_ID_RESERVED64,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_LA,
+	PERIPH_ID_TRACECLKIN,
+	PERIPH_ID_SOC_THERM,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_RESERVED80,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_TSEC,
+	PERIPH_ID_RESERVED84,
+	PERIPH_ID_RESERVED85,
+	PERIPH_ID_RESERVED86,
+	PERIPH_ID_EMUCIF,
+
+	/* 88 */
+	PERIPH_ID_RESERVED88,
+	PERIPH_ID_XUSB_HOST,
+	PERIPH_ID_RESERVED90,
+	PERIPH_ID_MSENC,
+	PERIPH_ID_RESERVED92,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_XUSB_DEV,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_V_RESERVED2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_V_RESERVED4,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2S5,
+	PERIPH_ID_I2C4,
+
+	/* 104 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AHUB,
+	PERIPH_ID_APB2APE,
+	PERIPH_ID_V_RESERVED12,
+	PERIPH_ID_V_RESERVED13,
+	PERIPH_ID_V_RESERVED14,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 112 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_V_RESERVED17,
+	PERIPH_ID_V_RESERVED18,
+	PERIPH_ID_V_RESERVED19,
+	PERIPH_ID_V_RESERVED20,
+	PERIPH_ID_V_RESERVED21,
+	PERIPH_ID_V_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 120 */
+	PERIPH_ID_EXTPERIPH1,
+	PERIPH_ID_EXTPERIPH2,
+	PERIPH_ID_EXTPERIPH3,
+	PERIPH_ID_OOB,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_V_RESERVED30,
+	PERIPH_ID_V_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_SATACOLD,
+	PERIPH_ID_W_RESERVED2,
+	PERIPH_ID_W_RESERVED3,
+	PERIPH_ID_W_RESERVED4,
+	PERIPH_ID_W_RESERVED5,
+	PERIPH_ID_W_RESERVED6,
+	PERIPH_ID_W_RESERVED7,
+
+	/* 136 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_W_RESERVED9,
+	PERIPH_ID_W_RESERVED10,
+	PERIPH_ID_W_RESERVED11,
+	PERIPH_ID_W_RESERVED12,
+	PERIPH_ID_W_RESERVED13,
+	PERIPH_ID_XUSB_PADCTL,
+	PERIPH_ID_W_RESERVED15,
+
+	/* 144 */
+	PERIPH_ID_W_RESERVED16,
+	PERIPH_ID_W_RESERVED17,
+	PERIPH_ID_W_RESERVED18,
+	PERIPH_ID_W_RESERVED19,
+	PERIPH_ID_W_RESERVED20,
+	PERIPH_ID_ENTROPY,
+	PERIPH_ID_DDS,
+	PERIPH_ID_W_RESERVED23,
+
+	/* 152 */
+	PERIPH_ID_W_RESERVED24,
+	PERIPH_ID_W_RESERVED25,
+	PERIPH_ID_W_RESERVED26,
+	PERIPH_ID_DVFS,
+	PERIPH_ID_XUSB_SS,
+	PERIPH_ID_W_RESERVED29,
+	PERIPH_ID_W_RESERVED30,
+	PERIPH_ID_W_RESERVED31,
+
+	PERIPH_ID_X_FIRST,
+	/* X word: 31:0 */
+	PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
+	PERIPH_ID_X_RESERVED1,
+	PERIPH_ID_X_RESERVED2,
+	PERIPH_ID_X_RESERVED3,
+	PERIPH_ID_CAM_MCLK,
+	PERIPH_ID_CAM_MCLK2,
+	PERIPH_ID_I2C6,
+	PERIPH_ID_X_RESERVED7,
+
+	/* 168 */
+	PERIPH_ID_X_RESERVED8,
+	PERIPH_ID_X_RESERVED9,
+	PERIPH_ID_X_RESERVED10,
+	PERIPH_ID_VIM2_CLK,
+	PERIPH_ID_X_RESERVED12,
+	PERIPH_ID_X_RESERVED13,
+	PERIPH_ID_EMC_DLL,
+	PERIPH_ID_X_RESERVED15,
+
+	/* 176 */
+	PERIPH_ID_HDMI_AUDIO,
+	PERIPH_ID_CLK72MHZ,
+	PERIPH_ID_VIC,
+	PERIPH_ID_X_RESERVED19,
+	PERIPH_ID_X_RESERVED20,
+	PERIPH_ID_DPAUX,
+	PERIPH_ID_SOR0,
+	PERIPH_ID_X_RESERVED23,
+
+	/* 184 */
+	PERIPH_ID_GPU,
+	PERIPH_ID_X_RESERVED25,
+	PERIPH_ID_X_RESERVED26,
+	PERIPH_ID_X_RESERVED27,
+	PERIPH_ID_X_RESERVED28,
+	PERIPH_ID_X_RESERVED29,
+	PERIPH_ID_X_RESERVED30,
+	PERIPH_ID_X_RESERVED31,
+
+	PERIPH_ID_Y_FIRST,
+	/* Y word: 31:0 (192:223) */
+	PERIPH_ID_SPARE1 = PERIPH_ID_Y_FIRST,
+	PERIPH_ID_Y_RESERVED1,
+	PERIPH_ID_Y_RESERVED2,
+	PERIPH_ID_Y_RESERVED3,
+	PERIPH_ID_Y_RESERVED4,
+	PERIPH_ID_Y_RESERVED5,
+	PERIPH_ID_APE,
+	PERIPH_ID_Y_RESERVED7,
+
+	/* 200 */
+	PERIPH_ID_MC_CDPA,
+	PERIPH_ID_Y_RESERVED9,
+	PERIPH_ID_Y_RESERVED10,
+	PERIPH_ID_Y_RESERVED11,
+	PERIPH_ID_Y_RESERVED12,
+	PERIPH_ID_PEX_USB_UPHY,
+	PERIPH_ID_Y_RESERVED14,
+	PERIPH_ID_Y_RESERVED15,
+
+	/* 208 */
+	PERIPH_ID_VI_I2C,
+	PERIPH_ID_Y_RESERVED17,
+	PERIPH_ID_Y_RESERVED18,
+	PERIPH_ID_QSPI,
+	PERIPH_ID_Y_RESERVED20,
+	PERIPH_ID_Y_RESERVED21,
+	PERIPH_ID_Y_RESERVED22,
+	PERIPH_ID_Y_RESERVED23,
+
+	/* 216 */
+	PERIPH_ID_Y_RESERVED24,
+	PERIPH_ID_Y_RESERVED25,
+	PERIPH_ID_Y_RESERVED26,
+	PERIPH_ID_Y_RESERVED27,
+	PERIPH_ID_Y_RESERVED28,
+	PERIPH_ID_Y_RESERVED29,
+	PERIPH_ID_Y_RESERVED30,
+	PERIPH_ID_Y_RESERVED31,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S2,
+	PERIPHC_I2S3,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_I2C5,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_10h,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_18h,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_1Bh,
+	PERIPHC_1Ch,
+	PERIPHC_HSI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_22h,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_25h,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S1,
+	PERIPHC_DTV,
+
+	/* 0x38 */
+	PERIPHC_38h,
+	PERIPHC_39h,
+	PERIPHC_3ah,
+	PERIPHC_3bh,
+	PERIPHC_MSENC,
+	PERIPHC_TSEC,
+	PERIPHC_3eh,
+	PERIPHC_OSC,
+
+	PERIPHC_VW_FIRST,
+	/* 0x40 */
+	PERIPHC_40h = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S4,
+	PERIPHC_I2S5,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x48 */
+	PERIPHC_AUDIO,
+	PERIPHC_49h,
+	PERIPHC_4ah,
+	PERIPHC_4bh,
+	PERIPHC_4ch,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x50 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_52h,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_55h,
+	PERIPHC_56h,
+	PERIPHC_57h,
+
+	/* 0x58 */
+	PERIPHC_58h,
+	PERIPHC_59h,
+	PERIPHC_5ah,
+	PERIPHC_5bh,
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,		/* 0x428 */
+	PERIPHC_5fh,
+
+	PERIPHC_X_FIRST,
+	/* 0x60 */
+	PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST,	/* 0x600 */
+	PERIPHC_XUSB_FALCON,
+	PERIPHC_XUSB_FS,
+	PERIPHC_XUSB_CORE_DEV,
+	PERIPHC_XUSB_SS,
+	PERIPHC_CILAB,
+	PERIPHC_CILCD,
+	PERIPHC_CILE,
+
+	/* 0x68 */
+	PERIPHC_DSIA_LP,
+	PERIPHC_DSIB_LP,
+	PERIPHC_ENTROPY,
+	PERIPHC_DVFS_REF,
+	PERIPHC_DVFS_SOC,
+	PERIPHC_TRACECLKIN,
+	PERIPHC_6Eh,
+	PERIPHC_6Fh,
+
+	/* 0x70 */
+	PERIPHC_EMC_LATENCY,
+	PERIPHC_SOC_THERM,
+	PERIPHC_72h,
+	PERIPHC_73h,
+	PERIPHC_74h,
+	PERIPHC_75h,
+	PERIPHC_VI_SENSOR2,
+	PERIPHC_I2C6,
+
+	/* 0x78 */
+	PERIPHC_78h,
+	PERIPHC_EMC_DLL,
+	PERIPHC_7ah,
+	PERIPHC_CLK72MHZ,
+	PERIPHC_7ch,
+	PERIPHC_7dh,
+	PERIPHC_VIC,
+	PERIPHC_7fh,
+
+	PERIPHC_Y_FIRST,
+	/* 0x80 */
+	PERIPHC_SDMMC_LEGACY_TM = PERIPHC_Y_FIRST,	/* 0x694 */
+	PERIPHC_NVDEC,			/* 0x698 */
+	PERIPHC_NVJPG,			/* 0x69c */
+	PERIPHC_NVENC,			/* 0x6a0 */
+	PERIPHC_84h,
+	PERIPHC_85h,
+	PERIPHC_86h,
+	PERIPHC_87h,
+
+	/* 0x88 */
+	PERIPHC_88h,
+	PERIPHC_89h,
+	PERIPHC_DMIC3,			/* 0x6bc:  */
+	PERIPHC_APE,			/* 0x6c0:  */
+	PERIPHC_QSPI,			/* 0x6c4:  */
+	PERIPHC_VI_I2C,			/* 0x6c8:  */
+	PERIPHC_USB2_HSIC_TRK,		/* 0x6cc:  */
+	PERIPHC_PEX_SATA_USB_RX_BYP,	/* 0x6d0:  */
+
+	/* 0x90 */
+	PERIPHC_MAUD,			/* 0x6d4:  */
+	PERIPHC_TSECB,			/* 0x6d8:  */
+
+	PERIPHC_COUNT,
+	PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _TEGRA210_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/clock.h b/arch/arm/include/asm/arch-tegra210/clock.h
new file mode 100644
index 0000000..438a6f4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/clock.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+/* Tegra210 clock control definitions */
+
+#ifndef _TEGRA210_CLOCK_H_
+#define _TEGRA210_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+/* PLL bits that differ from generic clk_rst.h */
+#define PLLC_RESET		30
+#define PLLC_IDDQ		27
+#define PLLD_ENABLE_CLK		21
+#define PLLD_EN_LCKDET		28
+
+int tegra_plle_enable(void);
+
+#endif	/* _TEGRA210_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/flow.h b/arch/arm/include/asm/arch-tegra210/flow.h
new file mode 100644
index 0000000..ef0be19
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/flow.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA210_FLOW_H_
+#define _TEGRA210_FLOW_H_
+
+struct flow_ctlr {
+	u32 halt_cpu_events;	/* offset 0x00 */
+	u32 halt_cop_events;	/* offset 0x04 */
+	u32 cpu_csr;		/* offset 0x08 */
+	u32 cop_csr;		/* offset 0x0c */
+	u32 xrq_events;		/* offset 0x10 */
+	u32 halt_cpu1_events;	/* offset 0x14 */
+	u32 cpu1_csr;		/* offset 0x18 */
+	u32 halt_cpu2_events;	/* offset 0x1c */
+	u32 cpu2_csr;		/* offset 0x20 */
+	u32 halt_cpu3_events;	/* offset 0x24 */
+	u32 cpu3_csr;		/* offset 0x28 */
+	u32 cluster_control;	/* offset 0x2c */
+	u32 halt_cop1_events;	/* offset 0x30 */
+	u32 halt_cop1_csr;	/* offset 0x34 */
+	u32 cpu_pwr_csr;	/* offset 0x38 */
+	u32 mpid;		/* offset 0x3c */
+	u32 ram_repair;		/* offset 0x40 */
+};
+
+/* HALT_COP_EVENTS_0, 0x04 */
+#define EVENT_MSEC		(1 << 24)
+#define EVENT_USEC		(1 << 25)
+#define EVENT_JTAG		(1 << 28)
+#define EVENT_MODE_STOP		(2 << 29)
+
+/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
+#define ACTIVE_LP		(1 << 0)
+
+/* CPUn_CSR_0 */
+#define CSR_ENABLE		(1 << 0)
+#define CSR_IMMEDIATE_WAKE	(1 << 3)
+#define CSR_WAIT_WFI_SHIFT	8
+
+#endif /*  _TEGRA210_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h b/arch/arm/include/asm/arch-tegra210/funcmux.h
new file mode 100644
index 0000000..f6270e5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/funcmux.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+/* Tegra210 high-level function multiplexing */
+
+#ifndef _TEGRA210_FUNCMUX_H_
+#define _TEGRA210_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART1_UART1 = 0,
+	FUNCMUX_UART4_UART4 = 0,
+};
+#endif	/* _TEGRA210_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h
new file mode 100644
index 0000000..e9ff903
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA210_GP_PADCTRL_H_
+#define _TEGRA210_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	reserved1;	/* 0x8C: */
+	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	reserved2[3];	/* 0xA4 - 0xAC: */
+	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	reserved3[9];	/* 0xC8-0xE8: */
+	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+	u32	reserved4[3];	/* 0xF0-0xF8: */
+	u32	ddccfg;		/* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+	u32	gmacfg;		/* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+	u32	reserved5[3];	/* 0x104-0x10C: */
+	u32	gmecfg;		/* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+	u32	gmfcfg;		/* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+	u32	gmgcfg;		/* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+	u32	gmhcfg;		/* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+	u32	owrcfg;		/* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+	u32	uadcfg;		/* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+	u32	reserved6;	/* 0x128: */
+	u32	dev3cfg;	/* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+	u32	reserved7[2];	/* 0x130 - 0x134: */
+	u32	ceccfg;		/* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+	u32	reserved8[22];	/* 0x13C - 0x190: */
+	u32	atcfg6;		/* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+	u32	dap5cfg;	/* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+	u32	vbuscfg;	/* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+	u32	aocfg3;		/* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+	u32	hvccfg0;	/* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+	u32	sdio4cfg;	/* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+	u32	aocfg0;		/* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
+};
+
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF	0
+#define SDIOCFG_DRVDN_SLWR	0
+#define SDIOCFG_DRVUP		0x24
+#define SDIOCFG_DRVDN		0x14
+
+#endif	/* _TEGRA210_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h
new file mode 100644
index 0000000..cb91b10
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/gpio.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA210_GPIO_H_
+#define _TEGRA210_GPIO_H_
+
+/*
+ * The Tegra210 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	8	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+	uint gpio_masked_config[TEGRA_GPIO_PORTS];
+	uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_in[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+#endif	/* _TEGRA210_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/mc.h b/arch/arm/include/asm/arch-tegra210/mc.h
new file mode 100644
index 0000000..5a2a568
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/mc.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef _TEGRA210_MC_H_
+#define _TEGRA210_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+	u32 reserved0[4];			/* offset 0x00 - 0x0C */
+	u32 mc_smmu_config;			/* offset 0x10 */
+	u32 mc_smmu_tlb_config;			/* offset 0x14 */
+	u32 mc_smmu_ptc_config;			/* offset 0x18 */
+	u32 mc_smmu_ptb_asid;			/* offset 0x1C */
+	u32 mc_smmu_ptb_data;			/* offset 0x20 */
+	u32 reserved1[3];			/* offset 0x24 - 0x2C */
+	u32 mc_smmu_tlb_flush;			/* offset 0x30 */
+	u32 mc_smmu_ptc_flush;			/* offset 0x34 */
+	u32 reserved2[6];			/* offset 0x38 - 0x4C */
+	u32 mc_emem_cfg;			/* offset 0x50 */
+	u32 mc_emem_adr_cfg;			/* offset 0x54 */
+	u32 mc_emem_adr_cfg_dev0;		/* offset 0x58 */
+	u32 mc_emem_adr_cfg_dev1;		/* offset 0x5C */
+	u32 reserved3[4];			/* offset 0x60 - 0x6C */
+	u32 mc_security_cfg0;			/* offset 0x70 */
+	u32 mc_security_cfg1;			/* offset 0x74 */
+	u32 reserved4[6];			/* offset 0x7C - 0x8C */
+	u32 mc_emem_arb_reserved[28];		/* offset 0x90 - 0xFC */
+	u32 reserved5[74];			/* offset 0x100 - 0x224 */
+	u32 mc_smmu_translation_enable_0;	/* offset 0x228 */
+	u32 mc_smmu_translation_enable_1;	/* offset 0x22C */
+	u32 mc_smmu_translation_enable_2;	/* offset 0x230 */
+	u32 mc_smmu_translation_enable_3;	/* offset 0x234 */
+	u32 mc_smmu_afi_asid;			/* offset 0x238 */
+	u32 mc_smmu_avpc_asid;			/* offset 0x23C */
+	u32 mc_smmu_dc_asid;			/* offset 0x240 */
+	u32 mc_smmu_dcb_asid;			/* offset 0x244 */
+	u32 reserved6[2];                       /* offset 0x248 - 0x24C */
+	u32 mc_smmu_hc_asid;			/* offset 0x250 */
+	u32 mc_smmu_hda_asid;			/* offset 0x254 */
+	u32 mc_smmu_isp2_asid;			/* offset 0x258 */
+	u32 reserved7[2];                       /* offset 0x25C - 0x260 */
+	u32 mc_smmu_msenc_asid;			/* offset 0x264 */
+	u32 mc_smmu_nv_asid;			/* offset 0x268 */
+	u32 mc_smmu_nv2_asid;			/* offset 0x26C */
+	u32 mc_smmu_ppcs_asid;			/* offset 0x270 */
+	u32 mc_smmu_sata_asid;			/* offset 0x274 */
+	u32 reserved8[1];                       /* offset 0x278 */
+	u32 mc_smmu_vde_asid;			/* offset 0x27C */
+	u32 mc_smmu_vi_asid;			/* offset 0x280 */
+	u32 mc_smmu_vic_asid;			/* offset 0x284 */
+	u32 mc_smmu_xusb_host_asid;		/* offset 0x288 */
+	u32 mc_smmu_xusb_dev_asid;		/* offset 0x28C */
+	u32 reserved9[1];                       /* offset 0x290 */
+	u32 mc_smmu_tsec_asid;			/* offset 0x294 */
+	u32 mc_smmu_ppcs1_asid;			/* offset 0x298 */
+	u32 reserved10[235];			/* offset 0x29C - 0x644 */
+	u32 mc_video_protect_bom;		/* offset 0x648 */
+	u32 mc_video_protect_size_mb;		/* offset 0x64c */
+	u32 mc_video_protect_reg_ctrl;		/* offset 0x650 */
+};
+
+#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
+
+#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED		(0 << 0)
+#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED	(1 << 0)
+
+#endif	/* _TEGRA210_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/pinmux.h b/arch/arm/include/asm/arch-tegra210/pinmux.h
new file mode 100644
index 0000000..9e94074
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/pinmux.h
@@ -0,0 +1,415 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef _TEGRA210_PINMUX_H_
+#define _TEGRA210_PINMUX_H_
+
+enum pmux_pingrp {
+	PMUX_PINGRP_SDMMC1_CLK_PM0,
+	PMUX_PINGRP_SDMMC1_CMD_PM1,
+	PMUX_PINGRP_SDMMC1_DAT3_PM2,
+	PMUX_PINGRP_SDMMC1_DAT2_PM3,
+	PMUX_PINGRP_SDMMC1_DAT1_PM4,
+	PMUX_PINGRP_SDMMC1_DAT0_PM5,
+	PMUX_PINGRP_SDMMC3_CLK_PP0 = (0x1c / 4),
+	PMUX_PINGRP_SDMMC3_CMD_PP1,
+	PMUX_PINGRP_SDMMC3_DAT0_PP5,
+	PMUX_PINGRP_SDMMC3_DAT1_PP4,
+	PMUX_PINGRP_SDMMC3_DAT2_PP3,
+	PMUX_PINGRP_SDMMC3_DAT3_PP2,
+	PMUX_PINGRP_PEX_L0_RST_N_PA0 = (0x38 / 4),
+	PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1,
+	PMUX_PINGRP_PEX_WAKE_N_PA2,
+	PMUX_PINGRP_PEX_L1_RST_N_PA3,
+	PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4,
+	PMUX_PINGRP_SATA_LED_ACTIVE_PA5,
+	PMUX_PINGRP_SPI1_MOSI_PC0,
+	PMUX_PINGRP_SPI1_MISO_PC1,
+	PMUX_PINGRP_SPI1_SCK_PC2,
+	PMUX_PINGRP_SPI1_CS0_PC3,
+	PMUX_PINGRP_SPI1_CS1_PC4,
+	PMUX_PINGRP_SPI2_MOSI_PB4,
+	PMUX_PINGRP_SPI2_MISO_PB5,
+	PMUX_PINGRP_SPI2_SCK_PB6,
+	PMUX_PINGRP_SPI2_CS0_PB7,
+	PMUX_PINGRP_SPI2_CS1_PDD0,
+	PMUX_PINGRP_SPI4_MOSI_PC7,
+	PMUX_PINGRP_SPI4_MISO_PD0,
+	PMUX_PINGRP_SPI4_SCK_PC5,
+	PMUX_PINGRP_SPI4_CS0_PC6,
+	PMUX_PINGRP_QSPI_SCK_PEE0,
+	PMUX_PINGRP_QSPI_CS_N_PEE1,
+	PMUX_PINGRP_QSPI_IO0_PEE2,
+	PMUX_PINGRP_QSPI_IO1_PEE3,
+	PMUX_PINGRP_QSPI_IO2_PEE4,
+	PMUX_PINGRP_QSPI_IO3_PEE5,
+	PMUX_PINGRP_DMIC1_CLK_PE0 = (0xa4 / 4),
+	PMUX_PINGRP_DMIC1_DAT_PE1,
+	PMUX_PINGRP_DMIC2_CLK_PE2,
+	PMUX_PINGRP_DMIC2_DAT_PE3,
+	PMUX_PINGRP_DMIC3_CLK_PE4,
+	PMUX_PINGRP_DMIC3_DAT_PE5,
+	PMUX_PINGRP_GEN1_I2C_SCL_PJ1,
+	PMUX_PINGRP_GEN1_I2C_SDA_PJ0,
+	PMUX_PINGRP_GEN2_I2C_SCL_PJ2,
+	PMUX_PINGRP_GEN2_I2C_SDA_PJ3,
+	PMUX_PINGRP_GEN3_I2C_SCL_PF0,
+	PMUX_PINGRP_GEN3_I2C_SDA_PF1,
+	PMUX_PINGRP_CAM_I2C_SCL_PS2,
+	PMUX_PINGRP_CAM_I2C_SDA_PS3,
+	PMUX_PINGRP_PWR_I2C_SCL_PY3,
+	PMUX_PINGRP_PWR_I2C_SDA_PY4,
+	PMUX_PINGRP_UART1_TX_PU0,
+	PMUX_PINGRP_UART1_RX_PU1,
+	PMUX_PINGRP_UART1_RTS_PU2,
+	PMUX_PINGRP_UART1_CTS_PU3,
+	PMUX_PINGRP_UART2_TX_PG0,
+	PMUX_PINGRP_UART2_RX_PG1,
+	PMUX_PINGRP_UART2_RTS_PG2,
+	PMUX_PINGRP_UART2_CTS_PG3,
+	PMUX_PINGRP_UART3_TX_PD1,
+	PMUX_PINGRP_UART3_RX_PD2,
+	PMUX_PINGRP_UART3_RTS_PD3,
+	PMUX_PINGRP_UART3_CTS_PD4,
+	PMUX_PINGRP_UART4_TX_PI4,
+	PMUX_PINGRP_UART4_RX_PI5,
+	PMUX_PINGRP_UART4_RTS_PI6,
+	PMUX_PINGRP_UART4_CTS_PI7,
+	PMUX_PINGRP_DAP1_FS_PB0,
+	PMUX_PINGRP_DAP1_DIN_PB1,
+	PMUX_PINGRP_DAP1_DOUT_PB2,
+	PMUX_PINGRP_DAP1_SCLK_PB3,
+	PMUX_PINGRP_DAP2_FS_PAA0,
+	PMUX_PINGRP_DAP2_DIN_PAA2,
+	PMUX_PINGRP_DAP2_DOUT_PAA3,
+	PMUX_PINGRP_DAP2_SCLK_PAA1,
+	PMUX_PINGRP_DAP4_FS_PJ4,
+	PMUX_PINGRP_DAP4_DIN_PJ5,
+	PMUX_PINGRP_DAP4_DOUT_PJ6,
+	PMUX_PINGRP_DAP4_SCLK_PJ7,
+	PMUX_PINGRP_CAM1_MCLK_PS0,
+	PMUX_PINGRP_CAM2_MCLK_PS1,
+	PMUX_PINGRP_JTAG_RTCK,
+	PMUX_PINGRP_CLK_32K_IN,
+	PMUX_PINGRP_CLK_32K_OUT_PY5,
+	PMUX_PINGRP_BATT_BCL,
+	PMUX_PINGRP_CLK_REQ,
+	PMUX_PINGRP_CPU_PWR_REQ,
+	PMUX_PINGRP_PWR_INT_N,
+	PMUX_PINGRP_SHUTDOWN,
+	PMUX_PINGRP_CORE_PWR_REQ,
+	PMUX_PINGRP_AUD_MCLK_PBB0,
+	PMUX_PINGRP_DVFS_PWM_PBB1,
+	PMUX_PINGRP_DVFS_CLK_PBB2,
+	PMUX_PINGRP_GPIO_X1_AUD_PBB3,
+	PMUX_PINGRP_GPIO_X3_AUD_PBB4,
+	PMUX_PINGRP_PCC7,
+	PMUX_PINGRP_HDMI_CEC_PCC0,
+	PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1,
+	PMUX_PINGRP_SPDIF_OUT_PCC2,
+	PMUX_PINGRP_SPDIF_IN_PCC3,
+	PMUX_PINGRP_USB_VBUS_EN0_PCC4,
+	PMUX_PINGRP_USB_VBUS_EN1_PCC5,
+	PMUX_PINGRP_DP_HPD0_PCC6,
+	PMUX_PINGRP_WIFI_EN_PH0,
+	PMUX_PINGRP_WIFI_RST_PH1,
+	PMUX_PINGRP_WIFI_WAKE_AP_PH2,
+	PMUX_PINGRP_AP_WAKE_BT_PH3,
+	PMUX_PINGRP_BT_RST_PH4,
+	PMUX_PINGRP_BT_WAKE_AP_PH5,
+	PMUX_PINGRP_AP_WAKE_NFC_PH7,
+	PMUX_PINGRP_NFC_EN_PI0,
+	PMUX_PINGRP_NFC_INT_PI1,
+	PMUX_PINGRP_GPS_EN_PI2,
+	PMUX_PINGRP_GPS_RST_PI3,
+	PMUX_PINGRP_CAM_RST_PS4,
+	PMUX_PINGRP_CAM_AF_EN_PS5,
+	PMUX_PINGRP_CAM_FLASH_EN_PS6,
+	PMUX_PINGRP_CAM1_PWDN_PS7,
+	PMUX_PINGRP_CAM2_PWDN_PT0,
+	PMUX_PINGRP_CAM1_STROBE_PT1,
+	PMUX_PINGRP_LCD_TE_PY2,
+	PMUX_PINGRP_LCD_BL_PWM_PV0,
+	PMUX_PINGRP_LCD_BL_EN_PV1,
+	PMUX_PINGRP_LCD_RST_PV2,
+	PMUX_PINGRP_LCD_GPIO1_PV3,
+	PMUX_PINGRP_LCD_GPIO2_PV4,
+	PMUX_PINGRP_AP_READY_PV5,
+	PMUX_PINGRP_TOUCH_RST_PV6,
+	PMUX_PINGRP_TOUCH_CLK_PV7,
+	PMUX_PINGRP_MODEM_WAKE_AP_PX0,
+	PMUX_PINGRP_TOUCH_INT_PX1,
+	PMUX_PINGRP_MOTION_INT_PX2,
+	PMUX_PINGRP_ALS_PROX_INT_PX3,
+	PMUX_PINGRP_TEMP_ALERT_PX4,
+	PMUX_PINGRP_BUTTON_POWER_ON_PX5,
+	PMUX_PINGRP_BUTTON_VOL_UP_PX6,
+	PMUX_PINGRP_BUTTON_VOL_DOWN_PX7,
+	PMUX_PINGRP_BUTTON_SLIDE_SW_PY0,
+	PMUX_PINGRP_BUTTON_HOME_PY1,
+	PMUX_PINGRP_PA6,
+	PMUX_PINGRP_PE6,
+	PMUX_PINGRP_PE7,
+	PMUX_PINGRP_PH6,
+	PMUX_PINGRP_PK0,
+	PMUX_PINGRP_PK1,
+	PMUX_PINGRP_PK2,
+	PMUX_PINGRP_PK3,
+	PMUX_PINGRP_PK4,
+	PMUX_PINGRP_PK5,
+	PMUX_PINGRP_PK6,
+	PMUX_PINGRP_PK7,
+	PMUX_PINGRP_PL0,
+	PMUX_PINGRP_PL1,
+	PMUX_PINGRP_PZ0,
+	PMUX_PINGRP_PZ1,
+	PMUX_PINGRP_PZ2,
+	PMUX_PINGRP_PZ3,
+	PMUX_PINGRP_PZ4,
+	PMUX_PINGRP_PZ5,
+	PMUX_PINGRP_COUNT,
+};
+
+enum pmux_drvgrp {
+	PMUX_DRVGRP_ALS_PROX_INT = (0x10 / 4),
+	PMUX_DRVGRP_AP_READY,
+	PMUX_DRVGRP_AP_WAKE_BT,
+	PMUX_DRVGRP_AP_WAKE_NFC,
+	PMUX_DRVGRP_AUD_MCLK,
+	PMUX_DRVGRP_BATT_BCL,
+	PMUX_DRVGRP_BT_RST,
+	PMUX_DRVGRP_BT_WAKE_AP,
+	PMUX_DRVGRP_BUTTON_HOME,
+	PMUX_DRVGRP_BUTTON_POWER_ON,
+	PMUX_DRVGRP_BUTTON_SLIDE_SW,
+	PMUX_DRVGRP_BUTTON_VOL_DOWN,
+	PMUX_DRVGRP_BUTTON_VOL_UP,
+	PMUX_DRVGRP_CAM1_MCLK,
+	PMUX_DRVGRP_CAM1_PWDN,
+	PMUX_DRVGRP_CAM1_STROBE,
+	PMUX_DRVGRP_CAM2_MCLK,
+	PMUX_DRVGRP_CAM2_PWDN,
+	PMUX_DRVGRP_CAM_AF_EN,
+	PMUX_DRVGRP_CAM_FLASH_EN,
+	PMUX_DRVGRP_CAM_I2C_SCL,
+	PMUX_DRVGRP_CAM_I2C_SDA,
+	PMUX_DRVGRP_CAM_RST,
+	PMUX_DRVGRP_CLK_32K_IN,
+	PMUX_DRVGRP_CLK_32K_OUT,
+	PMUX_DRVGRP_CLK_REQ,
+	PMUX_DRVGRP_CORE_PWR_REQ,
+	PMUX_DRVGRP_CPU_PWR_REQ,
+	PMUX_DRVGRP_DAP1_DIN,
+	PMUX_DRVGRP_DAP1_DOUT,
+	PMUX_DRVGRP_DAP1_FS,
+	PMUX_DRVGRP_DAP1_SCLK,
+	PMUX_DRVGRP_DAP2_DIN,
+	PMUX_DRVGRP_DAP2_DOUT,
+	PMUX_DRVGRP_DAP2_FS,
+	PMUX_DRVGRP_DAP2_SCLK,
+	PMUX_DRVGRP_DAP4_DIN,
+	PMUX_DRVGRP_DAP4_DOUT,
+	PMUX_DRVGRP_DAP4_FS,
+	PMUX_DRVGRP_DAP4_SCLK,
+	PMUX_DRVGRP_DMIC1_CLK,
+	PMUX_DRVGRP_DMIC1_DAT,
+	PMUX_DRVGRP_DMIC2_CLK,
+	PMUX_DRVGRP_DMIC2_DAT,
+	PMUX_DRVGRP_DMIC3_CLK,
+	PMUX_DRVGRP_DMIC3_DAT,
+	PMUX_DRVGRP_DP_HPD0,
+	PMUX_DRVGRP_DVFS_CLK,
+	PMUX_DRVGRP_DVFS_PWM,
+	PMUX_DRVGRP_GEN1_I2C_SCL,
+	PMUX_DRVGRP_GEN1_I2C_SDA,
+	PMUX_DRVGRP_GEN2_I2C_SCL,
+	PMUX_DRVGRP_GEN2_I2C_SDA,
+	PMUX_DRVGRP_GEN3_I2C_SCL,
+	PMUX_DRVGRP_GEN3_I2C_SDA,
+	PMUX_DRVGRP_PA6,
+	PMUX_DRVGRP_PCC7,
+	PMUX_DRVGRP_PE6,
+	PMUX_DRVGRP_PE7,
+	PMUX_DRVGRP_PH6,
+	PMUX_DRVGRP_PK0,
+	PMUX_DRVGRP_PK1,
+	PMUX_DRVGRP_PK2,
+	PMUX_DRVGRP_PK3,
+	PMUX_DRVGRP_PK4,
+	PMUX_DRVGRP_PK5,
+	PMUX_DRVGRP_PK6,
+	PMUX_DRVGRP_PK7,
+	PMUX_DRVGRP_PL0,
+	PMUX_DRVGRP_PL1,
+	PMUX_DRVGRP_PZ0,
+	PMUX_DRVGRP_PZ1,
+	PMUX_DRVGRP_PZ2,
+	PMUX_DRVGRP_PZ3,
+	PMUX_DRVGRP_PZ4,
+	PMUX_DRVGRP_PZ5,
+	PMUX_DRVGRP_GPIO_X1_AUD,
+	PMUX_DRVGRP_GPIO_X3_AUD,
+	PMUX_DRVGRP_GPS_EN,
+	PMUX_DRVGRP_GPS_RST,
+	PMUX_DRVGRP_HDMI_CEC,
+	PMUX_DRVGRP_HDMI_INT_DP_HPD,
+	PMUX_DRVGRP_JTAG_RTCK,
+	PMUX_DRVGRP_LCD_BL_EN,
+	PMUX_DRVGRP_LCD_BL_PWM,
+	PMUX_DRVGRP_LCD_GPIO1,
+	PMUX_DRVGRP_LCD_GPIO2,
+	PMUX_DRVGRP_LCD_RST,
+	PMUX_DRVGRP_LCD_TE,
+	PMUX_DRVGRP_MODEM_WAKE_AP,
+	PMUX_DRVGRP_MOTION_INT,
+	PMUX_DRVGRP_NFC_EN,
+	PMUX_DRVGRP_NFC_INT,
+	PMUX_DRVGRP_PEX_L0_CLKREQ_N,
+	PMUX_DRVGRP_PEX_L0_RST_N,
+	PMUX_DRVGRP_PEX_L1_CLKREQ_N,
+	PMUX_DRVGRP_PEX_L1_RST_N,
+	PMUX_DRVGRP_PEX_WAKE_N,
+	PMUX_DRVGRP_PWR_I2C_SCL,
+	PMUX_DRVGRP_PWR_I2C_SDA,
+	PMUX_DRVGRP_PWR_INT_N,
+	PMUX_DRVGRP_QSPI_SCK = (0x1bc / 4),
+	PMUX_DRVGRP_SATA_LED_ACTIVE,
+	PMUX_DRVGRP_SDMMC1,
+	PMUX_DRVGRP_SDMMC2,
+	PMUX_DRVGRP_SDMMC3 = (0x1dc / 4),
+	PMUX_DRVGRP_SDMMC4,
+	PMUX_DRVGRP_SHUTDOWN = (0x1f4 / 4),
+	PMUX_DRVGRP_SPDIF_IN,
+	PMUX_DRVGRP_SPDIF_OUT,
+	PMUX_DRVGRP_SPI1_CS0,
+	PMUX_DRVGRP_SPI1_CS1,
+	PMUX_DRVGRP_SPI1_MISO,
+	PMUX_DRVGRP_SPI1_MOSI,
+	PMUX_DRVGRP_SPI1_SCK,
+	PMUX_DRVGRP_SPI2_CS0,
+	PMUX_DRVGRP_SPI2_CS1,
+	PMUX_DRVGRP_SPI2_MISO,
+	PMUX_DRVGRP_SPI2_MOSI,
+	PMUX_DRVGRP_SPI2_SCK,
+	PMUX_DRVGRP_SPI4_CS0,
+	PMUX_DRVGRP_SPI4_MISO,
+	PMUX_DRVGRP_SPI4_MOSI,
+	PMUX_DRVGRP_SPI4_SCK,
+	PMUX_DRVGRP_TEMP_ALERT,
+	PMUX_DRVGRP_TOUCH_CLK,
+	PMUX_DRVGRP_TOUCH_INT,
+	PMUX_DRVGRP_TOUCH_RST,
+	PMUX_DRVGRP_UART1_CTS,
+	PMUX_DRVGRP_UART1_RTS,
+	PMUX_DRVGRP_UART1_RX,
+	PMUX_DRVGRP_UART1_TX,
+	PMUX_DRVGRP_UART2_CTS,
+	PMUX_DRVGRP_UART2_RTS,
+	PMUX_DRVGRP_UART2_RX,
+	PMUX_DRVGRP_UART2_TX,
+	PMUX_DRVGRP_UART3_CTS,
+	PMUX_DRVGRP_UART3_RTS,
+	PMUX_DRVGRP_UART3_RX,
+	PMUX_DRVGRP_UART3_TX,
+	PMUX_DRVGRP_UART4_CTS,
+	PMUX_DRVGRP_UART4_RTS,
+	PMUX_DRVGRP_UART4_RX,
+	PMUX_DRVGRP_UART4_TX,
+	PMUX_DRVGRP_USB_VBUS_EN0,
+	PMUX_DRVGRP_USB_VBUS_EN1,
+	PMUX_DRVGRP_WIFI_EN,
+	PMUX_DRVGRP_WIFI_RST,
+	PMUX_DRVGRP_WIFI_WAKE_AP,
+	PMUX_DRVGRP_COUNT,
+};
+
+enum pmux_func {
+	PMUX_FUNC_DEFAULT,
+	PMUX_FUNC_AUD,
+	PMUX_FUNC_BCL,
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CCLA,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLDVFS,
+	PMUX_FUNC_CLK,
+	PMUX_FUNC_CORE,
+	PMUX_FUNC_CPU,
+	PMUX_FUNC_DISPLAYA,
+	PMUX_FUNC_DISPLAYB,
+	PMUX_FUNC_DMIC1,
+	PMUX_FUNC_DMIC2,
+	PMUX_FUNC_DMIC3,
+	PMUX_FUNC_DP,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_I2CPMU,
+	PMUX_FUNC_I2CVI,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4A,
+	PMUX_FUNC_I2S4B,
+	PMUX_FUNC_I2S5A,
+	PMUX_FUNC_I2S5B,
+	PMUX_FUNC_IQC0,
+	PMUX_FUNC_IQC1,
+	PMUX_FUNC_JTAG,
+	PMUX_FUNC_PE,
+	PMUX_FUNC_PE0,
+	PMUX_FUNC_PE1,
+	PMUX_FUNC_PMI,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_QSPI,
+	PMUX_FUNC_SATA,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SHUTDOWN,
+	PMUX_FUNC_SOC,
+	PMUX_FUNC_SOR0,
+	PMUX_FUNC_SOR1,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_SYS,
+	PMUX_FUNC_TOUCH,
+	PMUX_FUNC_UART,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_USB,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+	PMUX_FUNC_VIMCLK,
+	PMUX_FUNC_VIMCLK2,
+	PMUX_FUNC_RSVD0,
+	PMUX_FUNC_RSVD1,
+	PMUX_FUNC_RSVD2,
+	PMUX_FUNC_RSVD3,
+	PMUX_FUNC_COUNT,
+};
+
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4
+#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_E_IO_HV
+#include <asm/arch-tegra/pinmux.h>
+
+#endif /* _TEGRA210_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/powergate.h b/arch/arm/include/asm/arch-tegra210/powergate.h
new file mode 100644
index 0000000..ec8f518
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/powergate.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef _TEGRA210_POWERGATE_H_
+#define _TEGRA210_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA210_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/sysctr.h b/arch/arm/include/asm/arch-tegra210/sysctr.h
new file mode 100644
index 0000000..cb1c499
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/sysctr.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA210_SYSCTR_H_
+#define _TEGRA210_SYSCTR_H_
+
+struct sysctr_ctlr {
+	u32 cntcr;		/* 0x00: SYSCTR0_CNTCR Counter Control */
+	u32 cntsr;		/* 0x04: SYSCTR0_CNTSR Counter Status */
+	u32 cntcv0;		/* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
+	u32 cntcv1;		/* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
+	u32 reserved1[4];	/* 0x10 - 0x1C */
+	u32 cntfid0;		/* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
+	u32 cntfid1;		/* 0x24: SYSCTR0_CNTFID1 Freq Table End */
+	u32 reserved2[1002];	/* 0x28 - 0xFCC */
+	u32 counterid[12];	/* 0xFD0 - 0xFxx CounterID regs, RO */
+};
+
+#define TSC_CNTCR_ENABLE	(1 << 0)	/* Enable */
+#define TSC_CNTCR_HDBG		(1 << 1)	/* Halt on debug */
+
+#endif	/* _TEGRA210_SYSCTR_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h b/arch/arm/include/asm/arch-tegra210/tegra.h
new file mode 100644
index 0000000..1c6fba6
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra210/tegra.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA210_TEGRA_H_
+#define _TEGRA210_TEGRA_H_
+
+#define GICD_BASE		0x50041000	/* Generic Int Cntrlr Distrib */
+#define GICC_BASE		0x50042000	/* Generic Int Cntrlr CPU I/F */
+#define NV_PA_AHB_BASE		0x6000C000	/* System regs (AHB, etc.) */
+#define NV_PA_TSC_BASE		0x700F0000	/* System Counter TSC regs */
+#define NV_PA_MC_BASE		0x70019000	/* Mem Ctlr regs (MCB, etc.) */
+#define NV_PA_SDRAM_BASE	0x80000000
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET	1288	/* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE	0x48	/* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR	0x4C	/* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU		4
+#define MCB_EMEM_ARB_OVERRIDE	(NV_PA_MC_BASE + 0xE8)
+
+#define TEGRA_USB1_BASE		0x7D000000
+
+#endif /* _TEGRA210_TEGRA_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h
new file mode 100644
index 0000000..8588009
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h
@@ -0,0 +1,372 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+/* Tegra30 clock PLL tables */
+
+#ifndef _TEGRA30_CLOCK_TABLES_H_
+#define _TEGRA30_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+	CLOCK_ID_FIRST,
+	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+	CLOCK_ID_MEMORY,
+	CLOCK_ID_PERIPH,
+	CLOCK_ID_AUDIO,
+	CLOCK_ID_USB,
+	CLOCK_ID_DISPLAY,
+
+	/* now the simple ones */
+	CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+	CLOCK_ID_EPCI,
+	CLOCK_ID_SFROM32KHZ,
+
+	/* These are the base clocks (inputs to the Tegra SOC) */
+	CLOCK_ID_32KHZ,
+	CLOCK_ID_OSC,
+	CLOCK_ID_CLK_M,
+
+	CLOCK_ID_COUNT,	/* number of PLLs */
+	CLOCK_ID_DISPLAY2,	/* Tegra3, placeholder */
+	CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+	PERIPH_ID_FIRST,
+
+	/* Low word: 31:0 */
+	PERIPH_ID_CPU = PERIPH_ID_FIRST,
+	PERIPH_ID_COP,
+	PERIPH_ID_TRIGSYS,
+	PERIPH_ID_RESERVED3,
+	PERIPH_ID_RESERVED4,
+	PERIPH_ID_TMR,
+	PERIPH_ID_UART1,
+	PERIPH_ID_UART2,
+
+	/* 8 */
+	PERIPH_ID_GPIO,
+	PERIPH_ID_SDMMC2,
+	PERIPH_ID_SPDIF,
+	PERIPH_ID_I2S1,
+	PERIPH_ID_I2C1,
+	PERIPH_ID_NDFLASH,
+	PERIPH_ID_SDMMC1,
+	PERIPH_ID_SDMMC4,
+
+	/* 16 */
+	PERIPH_ID_RESERVED16,
+	PERIPH_ID_PWM,
+	PERIPH_ID_I2S2,
+	PERIPH_ID_EPP,
+	PERIPH_ID_VI,
+	PERIPH_ID_2D,
+	PERIPH_ID_USBD,
+	PERIPH_ID_ISP,
+
+	/* 24 */
+	PERIPH_ID_3D,
+	PERIPH_ID_RESERVED24,
+	PERIPH_ID_DISP2,
+	PERIPH_ID_DISP1,
+	PERIPH_ID_HOST1X,
+	PERIPH_ID_VCP,
+	PERIPH_ID_I2S0,
+	PERIPH_ID_CACHE2,
+
+	/* Middle word: 63:32 */
+	PERIPH_ID_MEM,
+	PERIPH_ID_AHBDMA,
+	PERIPH_ID_APBDMA,
+	PERIPH_ID_RESERVED35,
+	PERIPH_ID_KBC,
+	PERIPH_ID_STAT_MON,
+	PERIPH_ID_PMC,
+	PERIPH_ID_FUSE,
+
+	/* 40 */
+	PERIPH_ID_KFUSE,
+	PERIPH_ID_SBC1,
+	PERIPH_ID_SNOR,
+	PERIPH_ID_RESERVED43,
+	PERIPH_ID_SBC2,
+	PERIPH_ID_RESERVED45,
+	PERIPH_ID_SBC3,
+	PERIPH_ID_DVC_I2C,
+
+	/* 48 */
+	PERIPH_ID_DSI,
+	PERIPH_ID_TVO,
+	PERIPH_ID_MIPI,
+	PERIPH_ID_HDMI,
+	PERIPH_ID_CSI,
+	PERIPH_ID_TVDAC,
+	PERIPH_ID_I2C2,
+	PERIPH_ID_UART3,
+
+	/* 56 */
+	PERIPH_ID_RESERVED56,
+	PERIPH_ID_EMC,
+	PERIPH_ID_USB2,
+	PERIPH_ID_USB3,
+	PERIPH_ID_MPE,
+	PERIPH_ID_VDE,
+	PERIPH_ID_BSEA,
+	PERIPH_ID_BSEV,
+
+	/* Upper word 95:64 */
+	PERIPH_ID_SPEEDO,
+	PERIPH_ID_UART4,
+	PERIPH_ID_UART5,
+	PERIPH_ID_I2C3,
+	PERIPH_ID_SBC4,
+	PERIPH_ID_SDMMC3,
+	PERIPH_ID_PCIE,
+	PERIPH_ID_OWR,
+
+	/* 72 */
+	PERIPH_ID_AFI,
+	PERIPH_ID_CORESIGHT,
+	PERIPH_ID_PCIEXCLK,
+	PERIPH_ID_AVPUCQ,
+	PERIPH_ID_RESERVED76,
+	PERIPH_ID_RESERVED77,
+	PERIPH_ID_RESERVED78,
+	PERIPH_ID_DTV,
+
+	/* 80 */
+	PERIPH_ID_NANDSPEED,
+	PERIPH_ID_I2CSLOW,
+	PERIPH_ID_DSIB,
+	PERIPH_ID_RESERVED83,
+	PERIPH_ID_IRAMA,
+	PERIPH_ID_IRAMB,
+	PERIPH_ID_IRAMC,
+	PERIPH_ID_IRAMD,
+
+	/* 88 */
+	PERIPH_ID_CRAM2,
+	PERIPH_ID_RESERVED89,
+	PERIPH_ID_MDOUBLER,
+	PERIPH_ID_RESERVED91,
+	PERIPH_ID_SUSOUT,
+	PERIPH_ID_RESERVED93,
+	PERIPH_ID_RESERVED94,
+	PERIPH_ID_RESERVED95,
+
+	PERIPH_ID_VW_FIRST,
+	/* V word: 31:0 */
+	PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+	PERIPH_ID_CPULP,
+	PERIPH_ID_3D2,
+	PERIPH_ID_MSELECT,
+	PERIPH_ID_TSENSOR,
+	PERIPH_ID_I2S3,
+	PERIPH_ID_I2S4,
+	PERIPH_ID_I2C4,
+
+	/* 08 */
+	PERIPH_ID_SBC5,
+	PERIPH_ID_SBC6,
+	PERIPH_ID_AUDIO,
+	PERIPH_ID_APBIF,
+	PERIPH_ID_DAM0,
+	PERIPH_ID_DAM1,
+	PERIPH_ID_DAM2,
+	PERIPH_ID_HDA2CODEC2X,
+
+	/* 16 */
+	PERIPH_ID_ATOMICS,
+	PERIPH_ID_EX_RESERVED17,
+	PERIPH_ID_EX_RESERVED18,
+	PERIPH_ID_EX_RESERVED19,
+	PERIPH_ID_EX_RESERVED20,
+	PERIPH_ID_EX_RESERVED21,
+	PERIPH_ID_EX_RESERVED22,
+	PERIPH_ID_ACTMON,
+
+	/* 24 */
+	PERIPH_ID_EX_RESERVED24,
+	PERIPH_ID_EX_RESERVED25,
+	PERIPH_ID_EX_RESERVED26,
+	PERIPH_ID_EX_RESERVED27,
+	PERIPH_ID_SATA,
+	PERIPH_ID_HDA,
+	PERIPH_ID_EX_RESERVED30,
+	PERIPH_ID_EX_RESERVED31,
+
+	/* W word: 31:0 */
+	PERIPH_ID_HDA2HDMICODEC,
+	PERIPH_ID_SATACOLD,
+	PERIPH_ID_RESERVED0_PCIERX0,
+	PERIPH_ID_RESERVED1_PCIERX1,
+	PERIPH_ID_RESERVED2_PCIERX2,
+	PERIPH_ID_RESERVED3_PCIERX3,
+	PERIPH_ID_RESERVED4_PCIERX4,
+	PERIPH_ID_RESERVED5_PCIERX5,
+
+	/* 40 */
+	PERIPH_ID_CEC,
+	PERIPH_ID_RESERVED6_PCIE2,
+	PERIPH_ID_RESERVED7_EMC,
+	PERIPH_ID_RESERVED8_HDMI,
+	PERIPH_ID_RESERVED9_SATA,
+	PERIPH_ID_RESERVED10_MIPI,
+	PERIPH_ID_EX_RESERVED46,
+	PERIPH_ID_EX_RESERVED47,
+
+	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+	/* 0x00 */
+	PERIPHC_I2S1,
+	PERIPHC_I2S2,
+	PERIPHC_SPDIF_OUT,
+	PERIPHC_SPDIF_IN,
+	PERIPHC_PWM,
+	PERIPHC_05h,
+	PERIPHC_SBC2,
+	PERIPHC_SBC3,
+
+	/* 0x08 */
+	PERIPHC_08h,
+	PERIPHC_I2C1,
+	PERIPHC_DVC_I2C,
+	PERIPHC_0bh,
+	PERIPHC_0ch,
+	PERIPHC_SBC1,
+	PERIPHC_DISP1,
+	PERIPHC_DISP2,
+
+	/* 0x10 */
+	PERIPHC_CVE,
+	PERIPHC_11h,
+	PERIPHC_VI,
+	PERIPHC_13h,
+	PERIPHC_SDMMC1,
+	PERIPHC_SDMMC2,
+	PERIPHC_G3D,
+	PERIPHC_G2D,
+
+	/* 0x18 */
+	PERIPHC_NDFLASH,
+	PERIPHC_SDMMC4,
+	PERIPHC_VFIR,
+	PERIPHC_EPP,
+	PERIPHC_MPE,
+	PERIPHC_MIPI,
+	PERIPHC_UART1,
+	PERIPHC_UART2,
+
+	/* 0x20 */
+	PERIPHC_HOST1X,
+	PERIPHC_21h,
+	PERIPHC_TVO,
+	PERIPHC_HDMI,
+	PERIPHC_24h,
+	PERIPHC_TVDAC,
+	PERIPHC_I2C2,
+	PERIPHC_EMC,
+
+	/* 0x28 */
+	PERIPHC_UART3,
+	PERIPHC_29h,
+	PERIPHC_VI_SENSOR,
+	PERIPHC_2bh,
+	PERIPHC_2ch,
+	PERIPHC_SBC4,
+	PERIPHC_I2C3,
+	PERIPHC_SDMMC3,
+
+	/* 0x30 */
+	PERIPHC_UART4,
+	PERIPHC_UART5,
+	PERIPHC_VDE,
+	PERIPHC_OWR,
+	PERIPHC_NOR,
+	PERIPHC_CSITE,
+	PERIPHC_I2S0,
+	PERIPHC_37h,
+
+	PERIPHC_VW_FIRST,
+	/* 0x38 */
+	PERIPHC_G3D2 = PERIPHC_VW_FIRST,
+	PERIPHC_MSELECT,
+	PERIPHC_TSENSOR,
+	PERIPHC_I2S3,
+	PERIPHC_I2S4,
+	PERIPHC_I2C4,
+	PERIPHC_SBC5,
+	PERIPHC_SBC6,
+
+	/* 0x40 */
+	PERIPHC_AUDIO,
+	PERIPHC_41h,
+	PERIPHC_DAM0,
+	PERIPHC_DAM1,
+	PERIPHC_DAM2,
+	PERIPHC_HDA2CODEC2X,
+	PERIPHC_ACTMON,
+	PERIPHC_EXTPERIPH1,
+
+	/* 0x48 */
+	PERIPHC_EXTPERIPH2,
+	PERIPHC_EXTPERIPH3,
+	PERIPHC_NANDSPEED,
+	PERIPHC_I2CSLOW,
+	PERIPHC_SYS,
+	PERIPHC_SPEEDO,
+	PERIPHC_4eh,
+	PERIPHC_4fh,
+
+	/* 0x50 */
+	PERIPHC_50h,
+	PERIPHC_51h,
+	PERIPHC_52h,
+	PERIPHC_53h,
+	PERIPHC_SATAOOB,
+	PERIPHC_SATA,
+	PERIPHC_HDA,
+
+	PERIPHC_COUNT,
+
+	PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+	(id < PERIPH_ID_VW_FIRST) ? \
+		((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+		(id) < PERIPH_ID_COUNT)
+
+#endif	/* _TEGRA30_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/include/asm/arch-tegra30/clock.h
new file mode 100644
index 0000000..7f5a115
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/clock.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+/* Tegra30 clock control functions */
+
+#ifndef _TEGRA30_CLOCK_H_
+#define _TEGRA30_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT          28
+#define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
+
+int tegra_plle_enable(void);
+
+#endif	/* _TEGRA30_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/flow.h b/arch/arm/include/asm/arch-tegra30/flow.h
new file mode 100644
index 0000000..f3e947e
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/flow.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA30_FLOW_H_
+#define _TEGRA30_FLOW_H_
+
+struct flow_ctlr {
+	u32 halt_cpu_events;
+	u32 halt_cop_events;
+	u32 cpu_csr;
+	u32 cop_csr;
+	u32 xrq_events;
+	u32 halt_cpu1_events;
+	u32 cpu1_csr;
+	u32 halt_cpu2_events;
+	u32 cpu2_csr;
+	u32 halt_cpu3_events;
+	u32 cpu3_csr;
+	u32 cluster_control;
+};
+
+#endif	/* _TEGRA30_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h
new file mode 100644
index 0000000..2e8b335
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/funcmux.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+/* Tegra30 high-level function multiplexing */
+
+#ifndef _TEGRA30_FUNCMUX_H_
+#define _TEGRA30_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+	FUNCMUX_DEFAULT = 0,	/* default config */
+
+	/* UART configs */
+	FUNCMUX_UART1_ULPI = 0,
+};
+#endif	/* _TEGRA30_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
new file mode 100644
index 0000000..4ff785d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA30_GP_PADCTRL_H_
+#define _TEGRA30_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+	u32	modereg;	/* 0x00: APB_MISC_GP_MODEREG */
+	u32	hidrev;		/* 0x04: APB_MISC_GP_HIDREV */
+	u32	reserved0[22];	/* 0x08 - 0x5C: */
+	u32	emu_revid;	/* 0x60: APB_MISC_GP_EMU_REVID */
+	u32	xactor_scratch;	/* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+	u32	aocfg1;		/* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+	u32	aocfg2;		/* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+	u32	atcfg1;		/* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+	u32	atcfg2;		/* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+	u32	atcfg3;		/* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+	u32	atcfg4;		/* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+	u32	atcfg5;		/* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+	u32	cdev1cfg;	/* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+	u32	cdev2cfg;	/* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+	u32	csuscfg;	/* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
+	u32	dap1cfg;	/* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+	u32	dap2cfg;	/* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+	u32	dap3cfg;	/* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+	u32	dap4cfg;	/* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+	u32	dbgcfg;		/* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+	u32	lcdcfg1;	/* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
+	u32	lcdcfg2;	/* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
+	u32	sdio2cfg;	/* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
+	u32	sdio3cfg;	/* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+	u32	spicfg;		/* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+	u32	uaacfg;		/* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+	u32	uabcfg;		/* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+	u32	uart2cfg;	/* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+	u32	uart3cfg;	/* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+	u32	vicfg1;		/* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
+	u32	vivttgen;	/* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
+	u32	reserved1[7];	/* 0xD0-0xE8: */
+	u32	sdio1cfg;	/* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+};
+
+/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+#define SDIOCFG_DRVUP_SLWF	1
+#define SDIOCFG_DRVDN_SLWR	1
+#define SDIOCFG_DRVUP		0x2E
+#define SDIOCFG_DRVDN		0x2A
+
+#endif	/* _TEGRA30_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h
new file mode 100644
index 0000000..1dd2e42
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/gpio.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA30_GPIO_H_
+#define _TEGRA30_GPIO_H_
+
+/*
+ * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
+#define TEGRA_GPIO_BANKS	8	/* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+	uint gpio_config[TEGRA_GPIO_PORTS];
+	uint gpio_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_out[TEGRA_GPIO_PORTS];
+	uint gpio_in[TEGRA_GPIO_PORTS];
+	uint gpio_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_int_clear[TEGRA_GPIO_PORTS];
+	uint gpio_masked_config[TEGRA_GPIO_PORTS];
+	uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_out[TEGRA_GPIO_PORTS];
+	uint gpio_masked_in[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+	uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+#endif	/* _TEGRA30_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/mc.h b/arch/arm/include/asm/arch-tegra30/mc.h
new file mode 100644
index 0000000..bbb0fe7
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/mc.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2014
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA30_MC_H_
+#define _TEGRA30_MC_H_
+
+/**
+ * Defines the memory controller registers we need/care about
+ */
+struct mc_ctlr {
+	u32 reserved0[4];			/* offset 0x00 - 0x0C */
+	u32 mc_smmu_config;			/* offset 0x10 */
+	u32 mc_smmu_tlb_config;			/* offset 0x14 */
+	u32 mc_smmu_ptc_config;			/* offset 0x18 */
+	u32 mc_smmu_ptb_asid;			/* offset 0x1C */
+	u32 mc_smmu_ptb_data;			/* offset 0x20 */
+	u32 reserved1[3];			/* offset 0x24 - 0x2C */
+	u32 mc_smmu_tlb_flush;			/* offset 0x30 */
+	u32 mc_smmu_ptc_flush;			/* offset 0x34 */
+	u32 mc_smmu_asid_security;		/* offset 0x38 */
+	u32 reserved2[5];			/* offset 0x3C - 0x4C */
+	u32 mc_emem_cfg;			/* offset 0x50 */
+	u32 mc_emem_adr_cfg;			/* offset 0x54 */
+	u32 mc_emem_adr_cfg_dev0;		/* offset 0x58 */
+	u32 mc_emem_adr_cfg_dev1;		/* offset 0x5C */
+	u32 reserved3[12];			/* offset 0x60 - 0x8C */
+	u32 mc_emem_arb_reserved[28];		/* offset 0x90 - 0xFC */
+	u32 reserved4[338];			/* offset 0x100 - 0x644 */
+	u32 mc_video_protect_bom;		/* offset 0x648 */
+	u32 mc_video_protect_size_mb;		/* offset 0x64c */
+	u32 mc_video_protect_reg_ctrl;		/* offset 0x650 */
+};
+
+#endif	/* _TEGRA30_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
new file mode 100644
index 0000000..1261943
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -0,0 +1,404 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#ifndef _TEGRA30_PINMUX_H_
+#define _TEGRA30_PINMUX_H_
+
+enum pmux_pingrp {
+	PMUX_PINGRP_ULPI_DATA0_PO1,
+	PMUX_PINGRP_ULPI_DATA1_PO2,
+	PMUX_PINGRP_ULPI_DATA2_PO3,
+	PMUX_PINGRP_ULPI_DATA3_PO4,
+	PMUX_PINGRP_ULPI_DATA4_PO5,
+	PMUX_PINGRP_ULPI_DATA5_PO6,
+	PMUX_PINGRP_ULPI_DATA6_PO7,
+	PMUX_PINGRP_ULPI_DATA7_PO0,
+	PMUX_PINGRP_ULPI_CLK_PY0,
+	PMUX_PINGRP_ULPI_DIR_PY1,
+	PMUX_PINGRP_ULPI_NXT_PY2,
+	PMUX_PINGRP_ULPI_STP_PY3,
+	PMUX_PINGRP_DAP3_FS_PP0,
+	PMUX_PINGRP_DAP3_DIN_PP1,
+	PMUX_PINGRP_DAP3_DOUT_PP2,
+	PMUX_PINGRP_DAP3_SCLK_PP3,
+	PMUX_PINGRP_PV0,
+	PMUX_PINGRP_PV1,
+	PMUX_PINGRP_SDMMC1_CLK_PZ0,
+	PMUX_PINGRP_SDMMC1_CMD_PZ1,
+	PMUX_PINGRP_SDMMC1_DAT3_PY4,
+	PMUX_PINGRP_SDMMC1_DAT2_PY5,
+	PMUX_PINGRP_SDMMC1_DAT1_PY6,
+	PMUX_PINGRP_SDMMC1_DAT0_PY7,
+	PMUX_PINGRP_PV2,
+	PMUX_PINGRP_PV3,
+	PMUX_PINGRP_CLK2_OUT_PW5,
+	PMUX_PINGRP_CLK2_REQ_PCC5,
+	PMUX_PINGRP_LCD_PWR1_PC1,
+	PMUX_PINGRP_LCD_PWR2_PC6,
+	PMUX_PINGRP_LCD_SDIN_PZ2,
+	PMUX_PINGRP_LCD_SDOUT_PN5,
+	PMUX_PINGRP_LCD_WR_N_PZ3,
+	PMUX_PINGRP_LCD_CS0_N_PN4,
+	PMUX_PINGRP_LCD_DC0_PN6,
+	PMUX_PINGRP_LCD_SCK_PZ4,
+	PMUX_PINGRP_LCD_PWR0_PB2,
+	PMUX_PINGRP_LCD_PCLK_PB3,
+	PMUX_PINGRP_LCD_DE_PJ1,
+	PMUX_PINGRP_LCD_HSYNC_PJ3,
+	PMUX_PINGRP_LCD_VSYNC_PJ4,
+	PMUX_PINGRP_LCD_D0_PE0,
+	PMUX_PINGRP_LCD_D1_PE1,
+	PMUX_PINGRP_LCD_D2_PE2,
+	PMUX_PINGRP_LCD_D3_PE3,
+	PMUX_PINGRP_LCD_D4_PE4,
+	PMUX_PINGRP_LCD_D5_PE5,
+	PMUX_PINGRP_LCD_D6_PE6,
+	PMUX_PINGRP_LCD_D7_PE7,
+	PMUX_PINGRP_LCD_D8_PF0,
+	PMUX_PINGRP_LCD_D9_PF1,
+	PMUX_PINGRP_LCD_D10_PF2,
+	PMUX_PINGRP_LCD_D11_PF3,
+	PMUX_PINGRP_LCD_D12_PF4,
+	PMUX_PINGRP_LCD_D13_PF5,
+	PMUX_PINGRP_LCD_D14_PF6,
+	PMUX_PINGRP_LCD_D15_PF7,
+	PMUX_PINGRP_LCD_D16_PM0,
+	PMUX_PINGRP_LCD_D17_PM1,
+	PMUX_PINGRP_LCD_D18_PM2,
+	PMUX_PINGRP_LCD_D19_PM3,
+	PMUX_PINGRP_LCD_D20_PM4,
+	PMUX_PINGRP_LCD_D21_PM5,
+	PMUX_PINGRP_LCD_D22_PM6,
+	PMUX_PINGRP_LCD_D23_PM7,
+	PMUX_PINGRP_LCD_CS1_N_PW0,
+	PMUX_PINGRP_LCD_M1_PW1,
+	PMUX_PINGRP_LCD_DC1_PD2,
+	PMUX_PINGRP_HDMI_INT_PN7,
+	PMUX_PINGRP_DDC_SCL_PV4,
+	PMUX_PINGRP_DDC_SDA_PV5,
+	PMUX_PINGRP_CRT_HSYNC_PV6,
+	PMUX_PINGRP_CRT_VSYNC_PV7,
+	PMUX_PINGRP_VI_D0_PT4,
+	PMUX_PINGRP_VI_D1_PD5,
+	PMUX_PINGRP_VI_D2_PL0,
+	PMUX_PINGRP_VI_D3_PL1,
+	PMUX_PINGRP_VI_D4_PL2,
+	PMUX_PINGRP_VI_D5_PL3,
+	PMUX_PINGRP_VI_D6_PL4,
+	PMUX_PINGRP_VI_D7_PL5,
+	PMUX_PINGRP_VI_D8_PL6,
+	PMUX_PINGRP_VI_D9_PL7,
+	PMUX_PINGRP_VI_D10_PT2,
+	PMUX_PINGRP_VI_D11_PT3,
+	PMUX_PINGRP_VI_PCLK_PT0,
+	PMUX_PINGRP_VI_MCLK_PT1,
+	PMUX_PINGRP_VI_VSYNC_PD6,
+	PMUX_PINGRP_VI_HSYNC_PD7,
+	PMUX_PINGRP_UART2_RXD_PC3,
+	PMUX_PINGRP_UART2_TXD_PC2,
+	PMUX_PINGRP_UART2_RTS_N_PJ6,
+	PMUX_PINGRP_UART2_CTS_N_PJ5,
+	PMUX_PINGRP_UART3_TXD_PW6,
+	PMUX_PINGRP_UART3_RXD_PW7,
+	PMUX_PINGRP_UART3_CTS_N_PA1,
+	PMUX_PINGRP_UART3_RTS_N_PC0,
+	PMUX_PINGRP_PU0,
+	PMUX_PINGRP_PU1,
+	PMUX_PINGRP_PU2,
+	PMUX_PINGRP_PU3,
+	PMUX_PINGRP_PU4,
+	PMUX_PINGRP_PU5,
+	PMUX_PINGRP_PU6,
+	PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+	PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+	PMUX_PINGRP_DAP4_FS_PP4,
+	PMUX_PINGRP_DAP4_DIN_PP5,
+	PMUX_PINGRP_DAP4_DOUT_PP6,
+	PMUX_PINGRP_DAP4_SCLK_PP7,
+	PMUX_PINGRP_CLK3_OUT_PEE0,
+	PMUX_PINGRP_CLK3_REQ_PEE1,
+	PMUX_PINGRP_GMI_WP_N_PC7,
+	PMUX_PINGRP_GMI_IORDY_PI5,
+	PMUX_PINGRP_GMI_WAIT_PI7,
+	PMUX_PINGRP_GMI_ADV_N_PK0,
+	PMUX_PINGRP_GMI_CLK_PK1,
+	PMUX_PINGRP_GMI_CS0_N_PJ0,
+	PMUX_PINGRP_GMI_CS1_N_PJ2,
+	PMUX_PINGRP_GMI_CS2_N_PK3,
+	PMUX_PINGRP_GMI_CS3_N_PK4,
+	PMUX_PINGRP_GMI_CS4_N_PK2,
+	PMUX_PINGRP_GMI_CS6_N_PI3,
+	PMUX_PINGRP_GMI_CS7_N_PI6,
+	PMUX_PINGRP_GMI_AD0_PG0,
+	PMUX_PINGRP_GMI_AD1_PG1,
+	PMUX_PINGRP_GMI_AD2_PG2,
+	PMUX_PINGRP_GMI_AD3_PG3,
+	PMUX_PINGRP_GMI_AD4_PG4,
+	PMUX_PINGRP_GMI_AD5_PG5,
+	PMUX_PINGRP_GMI_AD6_PG6,
+	PMUX_PINGRP_GMI_AD7_PG7,
+	PMUX_PINGRP_GMI_AD8_PH0,
+	PMUX_PINGRP_GMI_AD9_PH1,
+	PMUX_PINGRP_GMI_AD10_PH2,
+	PMUX_PINGRP_GMI_AD11_PH3,
+	PMUX_PINGRP_GMI_AD12_PH4,
+	PMUX_PINGRP_GMI_AD13_PH5,
+	PMUX_PINGRP_GMI_AD14_PH6,
+	PMUX_PINGRP_GMI_AD15_PH7,
+	PMUX_PINGRP_GMI_A16_PJ7,
+	PMUX_PINGRP_GMI_A17_PB0,
+	PMUX_PINGRP_GMI_A18_PB1,
+	PMUX_PINGRP_GMI_A19_PK7,
+	PMUX_PINGRP_GMI_WR_N_PI0,
+	PMUX_PINGRP_GMI_OE_N_PI1,
+	PMUX_PINGRP_GMI_DQS_PI2,
+	PMUX_PINGRP_GMI_RST_N_PI4,
+	PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+	PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+	PMUX_PINGRP_SDMMC4_CLK_PCC4,
+	PMUX_PINGRP_SDMMC4_CMD_PT7,
+	PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+	PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+	PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+	PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+	PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+	PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+	PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+	PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+	PMUX_PINGRP_SDMMC4_RST_N_PCC3,
+	PMUX_PINGRP_CAM_MCLK_PCC0,
+	PMUX_PINGRP_PCC1,
+	PMUX_PINGRP_PBB0,
+	PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+	PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+	PMUX_PINGRP_PBB3,
+	PMUX_PINGRP_PBB4,
+	PMUX_PINGRP_PBB5,
+	PMUX_PINGRP_PBB6,
+	PMUX_PINGRP_PBB7,
+	PMUX_PINGRP_PCC2,
+	PMUX_PINGRP_JTAG_RTCK_PU7,
+	PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+	PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+	PMUX_PINGRP_KB_ROW0_PR0,
+	PMUX_PINGRP_KB_ROW1_PR1,
+	PMUX_PINGRP_KB_ROW2_PR2,
+	PMUX_PINGRP_KB_ROW3_PR3,
+	PMUX_PINGRP_KB_ROW4_PR4,
+	PMUX_PINGRP_KB_ROW5_PR5,
+	PMUX_PINGRP_KB_ROW6_PR6,
+	PMUX_PINGRP_KB_ROW7_PR7,
+	PMUX_PINGRP_KB_ROW8_PS0,
+	PMUX_PINGRP_KB_ROW9_PS1,
+	PMUX_PINGRP_KB_ROW10_PS2,
+	PMUX_PINGRP_KB_ROW11_PS3,
+	PMUX_PINGRP_KB_ROW12_PS4,
+	PMUX_PINGRP_KB_ROW13_PS5,
+	PMUX_PINGRP_KB_ROW14_PS6,
+	PMUX_PINGRP_KB_ROW15_PS7,
+	PMUX_PINGRP_KB_COL0_PQ0,
+	PMUX_PINGRP_KB_COL1_PQ1,
+	PMUX_PINGRP_KB_COL2_PQ2,
+	PMUX_PINGRP_KB_COL3_PQ3,
+	PMUX_PINGRP_KB_COL4_PQ4,
+	PMUX_PINGRP_KB_COL5_PQ5,
+	PMUX_PINGRP_KB_COL6_PQ6,
+	PMUX_PINGRP_KB_COL7_PQ7,
+	PMUX_PINGRP_CLK_32K_OUT_PA0,
+	PMUX_PINGRP_SYS_CLK_REQ_PZ5,
+	PMUX_PINGRP_CORE_PWR_REQ,
+	PMUX_PINGRP_CPU_PWR_REQ,
+	PMUX_PINGRP_PWR_INT_N,
+	PMUX_PINGRP_CLK_32K_IN,
+	PMUX_PINGRP_OWR,
+	PMUX_PINGRP_DAP1_FS_PN0,
+	PMUX_PINGRP_DAP1_DIN_PN1,
+	PMUX_PINGRP_DAP1_DOUT_PN2,
+	PMUX_PINGRP_DAP1_SCLK_PN3,
+	PMUX_PINGRP_CLK1_REQ_PEE2,
+	PMUX_PINGRP_CLK1_OUT_PW4,
+	PMUX_PINGRP_SPDIF_IN_PK6,
+	PMUX_PINGRP_SPDIF_OUT_PK5,
+	PMUX_PINGRP_DAP2_FS_PA2,
+	PMUX_PINGRP_DAP2_DIN_PA4,
+	PMUX_PINGRP_DAP2_DOUT_PA5,
+	PMUX_PINGRP_DAP2_SCLK_PA3,
+	PMUX_PINGRP_SPI2_MOSI_PX0,
+	PMUX_PINGRP_SPI2_MISO_PX1,
+	PMUX_PINGRP_SPI2_CS0_N_PX3,
+	PMUX_PINGRP_SPI2_SCK_PX2,
+	PMUX_PINGRP_SPI1_MOSI_PX4,
+	PMUX_PINGRP_SPI1_SCK_PX5,
+	PMUX_PINGRP_SPI1_CS0_N_PX6,
+	PMUX_PINGRP_SPI1_MISO_PX7,
+	PMUX_PINGRP_SPI2_CS1_N_PW2,
+	PMUX_PINGRP_SPI2_CS2_N_PW3,
+	PMUX_PINGRP_SDMMC3_CLK_PA6,
+	PMUX_PINGRP_SDMMC3_CMD_PA7,
+	PMUX_PINGRP_SDMMC3_DAT0_PB7,
+	PMUX_PINGRP_SDMMC3_DAT1_PB6,
+	PMUX_PINGRP_SDMMC3_DAT2_PB5,
+	PMUX_PINGRP_SDMMC3_DAT3_PB4,
+	PMUX_PINGRP_SDMMC3_DAT4_PD1,
+	PMUX_PINGRP_SDMMC3_DAT5_PD0,
+	PMUX_PINGRP_SDMMC3_DAT6_PD3,
+	PMUX_PINGRP_SDMMC3_DAT7_PD4,
+	PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0,
+	PMUX_PINGRP_PEX_L0_RST_N_PDD1,
+	PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
+	PMUX_PINGRP_PEX_WAKE_N_PDD3,
+	PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4,
+	PMUX_PINGRP_PEX_L1_RST_N_PDD5,
+	PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
+	PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7,
+	PMUX_PINGRP_PEX_L2_RST_N_PCC6,
+	PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7,
+	PMUX_PINGRP_HDMI_CEC_PEE3,
+	PMUX_PINGRP_COUNT,
+};
+
+enum pmux_drvgrp {
+	PMUX_DRVGRP_AO1,
+	PMUX_DRVGRP_AO2,
+	PMUX_DRVGRP_AT1,
+	PMUX_DRVGRP_AT2,
+	PMUX_DRVGRP_AT3,
+	PMUX_DRVGRP_AT4,
+	PMUX_DRVGRP_AT5,
+	PMUX_DRVGRP_CDEV1,
+	PMUX_DRVGRP_CDEV2,
+	PMUX_DRVGRP_CSUS,
+	PMUX_DRVGRP_DAP1,
+	PMUX_DRVGRP_DAP2,
+	PMUX_DRVGRP_DAP3,
+	PMUX_DRVGRP_DAP4,
+	PMUX_DRVGRP_DBG,
+	PMUX_DRVGRP_LCD1,
+	PMUX_DRVGRP_LCD2,
+	PMUX_DRVGRP_SDIO2,
+	PMUX_DRVGRP_SDIO3,
+	PMUX_DRVGRP_SPI,
+	PMUX_DRVGRP_UAA,
+	PMUX_DRVGRP_UAB,
+	PMUX_DRVGRP_UART2,
+	PMUX_DRVGRP_UART3,
+	PMUX_DRVGRP_VI1,
+	PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+	PMUX_DRVGRP_CRT = (0x90 / 4),
+	PMUX_DRVGRP_DDC,
+	PMUX_DRVGRP_GMA,
+	PMUX_DRVGRP_GMB,
+	PMUX_DRVGRP_GMC,
+	PMUX_DRVGRP_GMD,
+	PMUX_DRVGRP_GME,
+	PMUX_DRVGRP_GMF,
+	PMUX_DRVGRP_GMG,
+	PMUX_DRVGRP_GMH,
+	PMUX_DRVGRP_OWR,
+	PMUX_DRVGRP_UDA,
+	PMUX_DRVGRP_GPV,
+	PMUX_DRVGRP_DEV3,
+	PMUX_DRVGRP_CEC = (0xd0 / 4),
+	PMUX_DRVGRP_COUNT,
+};
+
+enum pmux_func {
+	PMUX_FUNC_DEFAULT,
+	PMUX_FUNC_BLINK,
+	PMUX_FUNC_CEC,
+	PMUX_FUNC_CLK_12M_OUT,
+	PMUX_FUNC_CLK_32K_IN,
+	PMUX_FUNC_CORE_PWR_REQ,
+	PMUX_FUNC_CPU_PWR_REQ,
+	PMUX_FUNC_CRT,
+	PMUX_FUNC_DAP,
+	PMUX_FUNC_DDR,
+	PMUX_FUNC_DEV3,
+	PMUX_FUNC_DISPLAYA,
+	PMUX_FUNC_DISPLAYB,
+	PMUX_FUNC_DTV,
+	PMUX_FUNC_EXTPERIPH1,
+	PMUX_FUNC_EXTPERIPH2,
+	PMUX_FUNC_EXTPERIPH3,
+	PMUX_FUNC_GMI,
+	PMUX_FUNC_GMI_ALT,
+	PMUX_FUNC_HDA,
+	PMUX_FUNC_HDCP,
+	PMUX_FUNC_HDMI,
+	PMUX_FUNC_HSI,
+	PMUX_FUNC_I2C1,
+	PMUX_FUNC_I2C2,
+	PMUX_FUNC_I2C3,
+	PMUX_FUNC_I2C4,
+	PMUX_FUNC_I2CPWR,
+	PMUX_FUNC_I2S0,
+	PMUX_FUNC_I2S1,
+	PMUX_FUNC_I2S2,
+	PMUX_FUNC_I2S3,
+	PMUX_FUNC_I2S4,
+	PMUX_FUNC_INVALID,
+	PMUX_FUNC_KBC,
+	PMUX_FUNC_MIO,
+	PMUX_FUNC_NAND,
+	PMUX_FUNC_NAND_ALT,
+	PMUX_FUNC_OWR,
+	PMUX_FUNC_PCIE,
+	PMUX_FUNC_PWM0,
+	PMUX_FUNC_PWM1,
+	PMUX_FUNC_PWM2,
+	PMUX_FUNC_PWM3,
+	PMUX_FUNC_PWR_INT_N,
+	PMUX_FUNC_RTCK,
+	PMUX_FUNC_SATA,
+	PMUX_FUNC_SDMMC1,
+	PMUX_FUNC_SDMMC2,
+	PMUX_FUNC_SDMMC3,
+	PMUX_FUNC_SDMMC4,
+	PMUX_FUNC_SPDIF,
+	PMUX_FUNC_SPI1,
+	PMUX_FUNC_SPI2,
+	PMUX_FUNC_SPI2_ALT,
+	PMUX_FUNC_SPI3,
+	PMUX_FUNC_SPI4,
+	PMUX_FUNC_SPI5,
+	PMUX_FUNC_SPI6,
+	PMUX_FUNC_SYSCLK,
+	PMUX_FUNC_TEST,
+	PMUX_FUNC_TRACE,
+	PMUX_FUNC_UARTA,
+	PMUX_FUNC_UARTB,
+	PMUX_FUNC_UARTC,
+	PMUX_FUNC_UARTD,
+	PMUX_FUNC_UARTE,
+	PMUX_FUNC_ULPI,
+	PMUX_FUNC_VGP1,
+	PMUX_FUNC_VGP2,
+	PMUX_FUNC_VGP3,
+	PMUX_FUNC_VGP4,
+	PMUX_FUNC_VGP5,
+	PMUX_FUNC_VGP6,
+	PMUX_FUNC_VI,
+	PMUX_FUNC_VI_ALT1,
+	PMUX_FUNC_VI_ALT2,
+	PMUX_FUNC_VI_ALT3,
+	PMUX_FUNC_RSVD1,
+	PMUX_FUNC_RSVD2,
+	PMUX_FUNC_RSVD3,
+	PMUX_FUNC_RSVD4,
+	PMUX_FUNC_COUNT,
+};
+
+#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
+#define TEGRA_PMX_PINS_HAVE_E_INPUT
+#define TEGRA_PMX_PINS_HAVE_LOCK
+#define TEGRA_PMX_PINS_HAVE_OD
+#define TEGRA_PMX_PINS_HAVE_IO_RESET
+#include <asm/arch-tegra/pinmux.h>
+
+#endif /* _TEGRA30_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/powergate.h b/arch/arm/include/asm/arch-tegra30/powergate.h
new file mode 100644
index 0000000..c70e44b
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/powergate.h
@@ -0,0 +1,6 @@
+#ifndef _TEGRA30_POWERGATE_H_
+#define _TEGRA30_POWERGATE_H_
+
+#include <asm/arch-tegra/powergate.h>
+
+#endif /* _TEGRA30_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
new file mode 100644
index 0000000..1de7d2f
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra30/tegra.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA30_H_
+#define _TEGRA30_H_
+
+#define NV_PA_MC_BASE		0x7000F000
+#define NV_PA_SDRAM_BASE	0x80000000	/* 0x80000000 for real T30 */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define TEGRA_USB1_BASE		0x7D000000
+
+#define BCT_ODMDATA_OFFSET	6116	/* 12 bytes from end of BCT */
+
+#define MAX_NUM_CPU		4
+
+#endif	/* TEGRA30_H */
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h
new file mode 100644
index 0000000..72184fd
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_BUS_CLK,
+	MXC_IPG_CLK,
+	MXC_UART_CLK,
+	MXC_ESDHC_CLK,
+	MXC_FEC_CLK,
+	MXC_I2C_CLK,
+	MXC_DSPI_CLK,
+};
+
+void enable_ocotp_clk(unsigned char enable);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+u32 get_lpuart_clk(void);
+#ifdef CONFIG_SYS_I2C_MXC
+int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
+#endif
+
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
new file mode 100644
index 0000000..0c9ed52
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -0,0 +1,275 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
+#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+/* Clock Controller Module (CCM) */
+struct ccm_reg {
+	u32 ccr;
+	u32 csr;
+	u32 ccsr;
+	u32 cacrr;
+	u32 cscmr1;
+	u32 cscdr1;
+	u32 cscdr2;
+	u32 cscdr3;
+	u32 cscmr2;
+	u32 cscdr4;
+	u32 ctor;
+	u32 clpcr;
+	u32 cisr;
+	u32 cimr;
+	u32 ccosr;
+	u32 cgpr;
+	u32 ccgr0;
+	u32 ccgr1;
+	u32 ccgr2;
+	u32 ccgr3;
+	u32 ccgr4;
+	u32 ccgr5;
+	u32 ccgr6;
+	u32 ccgr7;
+	u32 ccgr8;
+	u32 ccgr9;
+	u32 ccgr10;
+	u32 ccgr11;
+	u32 cmeor0;
+	u32 cmeor1;
+	u32 cmeor2;
+	u32 cmeor3;
+	u32 cmeor4;
+	u32 cmeor5;
+	u32 cppdsr;
+	u32 ccowr;
+	u32 ccpgr0;
+	u32 ccpgr1;
+	u32 ccpgr2;
+	u32 ccpgr3;
+};
+
+/* Analog components control digital interface (ANADIG) */
+struct anadig_reg {
+	u32 reserved_0x000[4];
+	u32 pll3_ctrl;
+	u32 reserved_0x014[3];
+	u32 pll7_ctrl;
+	u32 reserved_0x024[3];
+	u32 pll2_ctrl;
+	u32 reserved_0x034[3];
+	u32 pll2_ss;
+	u32 reserved_0x044[3];
+	u32 pll2_num;
+	u32 reserved_0x054[3];
+	u32 pll2_denom;
+	u32 reserved_0x064[3];
+	u32 pll4_ctrl;
+	u32 reserved_0x074[3];
+	u32 pll4_num;
+	u32 reserved_0x084[3];
+	u32 pll4_denom;
+	u32 reserved_0x094[3];
+	u32 pll6_ctrl;
+	u32 reserved_0x0A4[3];
+	u32 pll6_num;
+	u32 reserved_0x0B4[3];
+	u32 pll6_denom;
+	u32 reserved_0x0C4[7];
+	u32 pll5_ctrl;
+	u32 reserved_0x0E4[3];
+	u32 pll3_pfd;
+	u32 reserved_0x0F4[3];
+	u32 pll2_pfd;
+	u32 reserved_0x104[3];
+	u32 reg_1p1;
+	u32 reserved_0x114[3];
+	u32 reg_3p0;
+	u32 reserved_0x124[3];
+	u32 reg_2p5;
+	u32 reserved_0x134[7];
+	u32 ana_misc0;
+	u32 reserved_0x154[3];
+	u32 ana_misc1;
+	u32 reserved_0x164[63];
+	u32 anadig_digprog;
+	u32 reserved_0x264[3];
+	u32 pll1_ctrl;
+	u32 reserved_0x274[3];
+	u32 pll1_ss;
+	u32 reserved_0x284[3];
+	u32 pll1_num;
+	u32 reserved_0x294[3];
+	u32 pll1_denom;
+	u32 reserved_0x2A4[3];
+	u32 pll1_pdf;
+	u32 reserved_0x2B4[3];
+	u32 pll_lock;
+};
+#endif
+
+#define CCM_CCR_FIRC_EN				(1 << 16)
+#define CCM_CCR_OSCNT_MASK			0xff
+#define CCM_CCR_OSCNT(v)			((v) & 0xff)
+
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET	19
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK		(0x7 << 19)
+#define CCM_CCSR_PLL2_PFD_CLK_SEL(v)		(((v) & 0x7) << 19)
+
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET	16
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK		(0x7 << 16)
+#define CCM_CCSR_PLL1_PFD_CLK_SEL(v)		(((v) & 0x7) << 16)
+
+#define CCM_CCSR_PLL2_PFD4_EN			(1 << 15)
+#define CCM_CCSR_PLL2_PFD3_EN			(1 << 14)
+#define CCM_CCSR_PLL2_PFD2_EN			(1 << 13)
+#define CCM_CCSR_PLL2_PFD1_EN			(1 << 12)
+#define CCM_CCSR_PLL1_PFD4_EN			(1 << 11)
+#define CCM_CCSR_PLL1_PFD3_EN			(1 << 10)
+#define CCM_CCSR_PLL1_PFD2_EN			(1 << 9)
+#define CCM_CCSR_PLL1_PFD1_EN			(1 << 8)
+
+#define CCM_CCSR_DDRC_CLK_SEL(v)		((v) << 6)
+#define CCM_CCSR_FAST_CLK_SEL(v)		((v) << 5)
+
+#define CCM_CCSR_SYS_CLK_SEL_OFFSET		0
+#define CCM_CCSR_SYS_CLK_SEL_MASK		0x7
+#define CCM_CCSR_SYS_CLK_SEL(v)			((v) & 0x7)
+
+#define CCM_CACRR_IPG_CLK_DIV_OFFSET		11
+#define CCM_CACRR_IPG_CLK_DIV_MASK		(0x3 << 11)
+#define CCM_CACRR_IPG_CLK_DIV(v)		(((v) & 0x3) << 11)
+#define CCM_CACRR_BUS_CLK_DIV_OFFSET		3
+#define CCM_CACRR_BUS_CLK_DIV_MASK		(0x7 << 3)
+#define CCM_CACRR_BUS_CLK_DIV(v)		(((v) & 0x7) << 3)
+#define CCM_CACRR_ARM_CLK_DIV_OFFSET		0
+#define CCM_CACRR_ARM_CLK_DIV_MASK		0x7
+#define CCM_CACRR_ARM_CLK_DIV(v)		((v) & 0x7)
+
+#define CCM_CSCMR1_DCU1_CLK_SEL			(1 << 29)
+#define CCM_CSCMR1_DCU0_CLK_SEL			(1 << 28)
+
+#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET		22
+#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK		(0x3 << 22)
+#define CCM_CSCMR1_QSPI0_CLK_SEL(v)		(((v) & 0x3) << 22)
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET	18
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK		(0x3 << 18)
+#define CCM_CSCMR1_ESDHC1_CLK_SEL(v)		(((v) & 0x3) << 18)
+#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET		12
+#define CCM_CSCMR1_NFC_CLK_SEL_MASK		(0x3 << 12)
+#define CCM_CSCMR1_NFC_CLK_SEL(v)		(((v) & 0x3) << 12)
+
+#define CCM_CSCDR1_RMII_CLK_EN			(1 << 24)
+
+#define CCM_CSCDR2_NFC_EN			(1 << 9)
+#define CCM_CSCDR2_NFC_FRAC_DIV_EN		(1 << 13)
+#define CCM_CSCDR2_NFC_CLK_INV			(1 << 14)
+#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET		4
+#define CCM_CSCDR2_NFC_FRAC_DIV_MASK		(0xf << 4)
+#define CCM_CSCDR2_NFC_FRAC_DIV(v)		(((v) & 0xf) << 4)
+
+#define CCM_CSCDR2_ESDHC1_EN			(1 << 29)
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET	20
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK		(0xf << 20)
+#define CCM_CSCDR2_ESDHC1_CLK_DIV(v)		(((v) & 0xf) << 20)
+
+#define CCM_CSCDR3_DCU1_EN			(1 << 23)
+#define CCM_CSCDR3_DCU1_DIV_MASK		(0x7 << 20)
+#define CCM_CSCDR3_DCU1_DIV(v)			(((v) & 0x7) << 20)
+#define CCM_CSCDR3_DCU0_EN			(1 << 19)
+#define CCM_CSCDR3_DCU0_DIV_MASK		(0x7 << 16)
+#define CCM_CSCDR3_DCU0_DIV(v)			(((v) & 0x7) << 16)
+
+#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET		13
+#define CCM_CSCDR3_NFC_PRE_DIV_MASK		(0x7 << 13)
+#define CCM_CSCDR3_NFC_PRE_DIV(v)		(((v) & 0x7) << 13)
+#define CCM_CSCDR3_QSPI0_EN			(1 << 4)
+#define CCM_CSCDR3_QSPI0_DIV(v)			((v) << 3)
+#define CCM_CSCDR3_QSPI0_X2_DIV(v)		((v) << 2)
+#define CCM_CSCDR3_QSPI0_X4_DIV(v)		((v) & 0x3)
+
+#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET		4
+#define CCM_CSCMR2_RMII_CLK_SEL_MASK		(0x3 << 4)
+#define CCM_CSCMR2_RMII_CLK_SEL(v)		(((v) & 0x3) << 4)
+
+#define CCM_REG_CTRL_MASK			0xffffffff
+#define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
+#define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR0_UART2_CTRL_MASK		(0x3 << 18)
+#define CCM_CCGR0_DSPI0_CTRL_MASK		(0x3 << 24)
+#define CCM_CCGR0_DSPI1_CTRL_MASK		(0x3 << 26)
+#define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
+#define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
+#define CCM_CCGR1_TCON0_CTRL_MASK		(0x3 << 26)
+#define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
+#define CCM_CCGR2_QSPI0_CTRL_MASK		(0x3 << 8)
+#define CCM_CCGR2_IOMUXC_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR2_PORTA_CTRL_MASK		(0x3 << 18)
+#define CCM_CCGR2_PORTB_CTRL_MASK		(0x3 << 20)
+#define CCM_CCGR2_PORTC_CTRL_MASK		(0x3 << 22)
+#define CCM_CCGR2_PORTD_CTRL_MASK		(0x3 << 24)
+#define CCM_CCGR2_PORTE_CTRL_MASK		(0x3 << 26)
+#define CCM_CCGR3_ANADIG_CTRL_MASK		0x3
+#define CCM_CCGR3_SCSC_CTRL_MASK        (0x3 << 4)
+#define CCM_CCGR3_DCU0_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR4_WKUP_CTRL_MASK		(0x3 << 20)
+#define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
+#define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
+#define CCM_CCGR4_I2C0_CTRL_MASK		(0x3 << 12)
+#define CCM_CCGR4_I2C1_CTRL_MASK		(0x3 << 14)
+#define CCM_CCGR6_OCOTP_CTRL_MASK		(0x3 << 10)
+#define CCM_CCGR6_DSPI2_CTRL_MASK		(0x3 << 24)
+#define CCM_CCGR6_DSPI3_CTRL_MASK		(0x3 << 26)
+#define CCM_CCGR6_DDRMC_CTRL_MASK		(0x3 << 28)
+#define CCM_CCGR7_SDHC1_CTRL_MASK		(0x3 << 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK       (0x3 << 8)
+#define CCM_CCGR9_FEC0_CTRL_MASK		0x3
+#define CCM_CCGR9_FEC1_CTRL_MASK		(0x3 << 2)
+#define CCM_CCGR10_NFC_CTRL_MASK		0x3
+#define CCM_CCGR10_I2C2_CTRL_MASK		(0x3 << 12)
+#define CCM_CCGR10_I2C3_CTRL_MASK		(0x3 << 14)
+
+#define ANADIG_PLL7_CTRL_BYPASS         (1 << 16)
+#define ANADIG_PLL7_CTRL_ENABLE         (1 << 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN      (1 << 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT     (1 << 1)
+#define ANADIG_PLL5_CTRL_BYPASS                 (1 << 16)
+#define ANADIG_PLL5_CTRL_ENABLE                 (1 << 13)
+#define ANADIG_PLL5_CTRL_POWERDOWN              (1 << 12)
+#define ANADIG_PLL5_CTRL_DIV_SELECT		1
+#define ANADIG_PLL3_CTRL_BYPASS         (1 << 16)
+#define ANADIG_PLL3_CTRL_ENABLE         (1 << 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN      (1 << 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT     (1 << 1)
+#define ANADIG_PLL2_CTRL_ENABLE			(1 << 13)
+#define ANADIG_PLL2_CTRL_POWERDOWN		(1 << 12)
+#define ANADIG_PLL2_CTRL_DIV_SELECT		1
+#define ANADIG_PLL1_CTRL_ENABLE			(1 << 13)
+#define ANADIG_PLL1_CTRL_POWERDOWN		(1 << 12)
+#define ANADIG_PLL1_CTRL_DIV_SELECT		1
+
+#define FASE_CLK_FREQ		24000000
+#define SLOW_CLK_FREQ		32000
+#define PLL1_PFD1_FREQ		500000000
+#define PLL1_PFD2_FREQ		452000000
+#define PLL1_PFD3_FREQ		396000000
+#define PLL1_PFD4_FREQ		528000000
+#define PLL1_MAIN_FREQ		528000000
+#define PLL2_PFD1_FREQ		500000000
+#define PLL2_PFD2_FREQ		396000000
+#define PLL2_PFD3_FREQ		339000000
+#define PLL2_PFD4_FREQ		413000000
+#define PLL2_MAIN_FREQ		528000000
+#define PLL3_MAIN_FREQ		480000000
+#define PLL3_PFD3_FREQ		298000000
+#define PLL5_MAIN_FREQ		500000000
+
+#define ENET_EXTERNAL_CLK	50000000
+#define AUDIO_EXTERNAL_CLK	24576000
+
+#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
new file mode 100644
index 0000000..03e3cec
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015
+ * Toradex, Inc.
+ *
+ * Authors: Stefan Agner
+ *          Sanchayan Maity
+ */
+
+#ifndef __ASM_ARCH_VF610_DDRMC_H
+#define __ASM_ARCH_VF610_DDRMC_H
+
+#include <asm/arch/iomux-vf610.h>
+
+struct ddr3_jedec_timings {
+	u8 tinit;
+	u32 trst_pwron;
+	u32 cke_inactive;
+	u8 wrlat;
+	u8 caslat_lin;
+	u8 trc;
+	u8 trrd;
+	u8 tccd;
+	u8 tbst_int_interval;
+	u8 tfaw;
+	u8 trp;
+	u8 twtr;
+	u8 tras_min;
+	u8 tmrd;
+	u8 trtp;
+	u32 tras_max;
+	u8 tmod;
+	u8 tckesr;
+	u8 tcke;
+	u8 trcd_int;
+	u8 tras_lockout;
+	u8 tdal;
+	u8 bstlen;
+	u16 tdll;
+	u8 trp_ab;
+	u16 tref;
+	u8 trfc;
+	u16 tref_int;
+	u8 tpdex;
+	u8 txpdll;
+	u8 txsnr;
+	u16 txsr;
+	u8 cksrx;
+	u8 cksre;
+	u8 freq_chg_en;
+	u16 zqcl;
+	u16 zqinit;
+	u8 zqcs;
+	u8 ref_per_zq;
+	u8 zqcs_rotate;
+	u8 aprebit;
+	u8 cmd_age_cnt;
+	u8 age_cnt;
+	u8 q_fullness;
+	u8 odt_rd_mapcs0;
+	u8 odt_wr_mapcs0;
+	u8 wlmrd;
+	u8 wldqsen;
+};
+
+struct ddrmc_cr_setting {
+	u32	setting;
+	int	cr_rnum; /* CR register ; -1 for last entry */
+};
+
+struct ddrmc_phy_setting {
+	u32	setting;
+	int	phy_rnum; /* PHY register ; -1 for last entry */
+};
+
+void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
+void ddrmc_phy_init(void);
+void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
+			  struct ddrmc_cr_setting *board_cr_settings,
+			  struct ddrmc_phy_setting *board_phy_settings,
+			  int col_diff, int row_diff);
+
+#endif
diff --git a/arch/arm/include/asm/arch-vf610/gpio.h b/arch/arm/include/asm/arch-vf610/gpio.h
new file mode 100644
index 0000000..9bfdf16
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/gpio.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015
+ * Bhuvanchandra DV, Toradex, Inc.
+ */
+
+#ifndef __ASM_ARCH_VF610_GPIO_H
+#define __ASM_ARCH_VF610_GPIO_H
+
+#define VYBRID_GPIO_COUNT		32
+#define VF610_GPIO_DIRECTION_IN	0x0
+#define VF610_GPIO_DIRECTION_OUT	0x1
+
+/* GPIO registers */
+struct vybrid_gpio_regs {
+	u32 gpio_pdor;
+	u32 gpio_psor;
+	u32 gpio_pcor;
+	u32 gpio_ptor;
+	u32 gpio_pdir;
+};
+
+struct vybrid_gpio_platdata {
+	unsigned int chip;
+	u32 base;
+	const char *port_name;
+};
+#endif	/* __ASM_ARCH_VF610_GPIO_H */
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
new file mode 100644
index 0000000..ae0a187
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -0,0 +1,479 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define IRAM_BASE_ADDR		0x3F000000	/* internal ram */
+#define IRAM_SIZE		0x00080000	/* 512 KB */
+
+#define AIPS0_BASE_ADDR		0x40000000
+#define AIPS1_BASE_ADDR		0x40080000
+
+/* AIPS 0 */
+#define MSCM_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00001000)
+#define MSCM_IR_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00001800)
+#define CA5SCU_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00002000)
+#define CA5_INTD_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00003000)
+#define CA5_L2C_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00006000)
+#define NIC0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00008000)
+#define NIC1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00009000)
+#define NIC2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000A000)
+#define NIC3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000B000)
+#define NIC4_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000C000)
+#define NIC5_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000D000)
+#define NIC6_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000E000)
+#define NIC7_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0000F000)
+#define AHBTZASC_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00010000)
+#define TZASC_SYS0_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00011000)
+#define TZASC_SYS1_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00012000)
+#define TZASC_GFX_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00013000)
+#define TZASC_DDR0_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00014000)
+#define TZASC_DDR1_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00015000)
+#define CSU_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00017000)
+#define DMA0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00018000)
+#define DMA0_TCD_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00019000)
+#define SEMA4_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0001D000)
+#define FB_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0001E000)
+#define DMA_MUX0_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00024000)
+#define UART0_BASE		(AIPS0_BASE_ADDR + 0x00027000)
+#define UART1_BASE		(AIPS0_BASE_ADDR + 0x00028000)
+#define UART2_BASE		(AIPS0_BASE_ADDR + 0x00029000)
+#define UART3_BASE		(AIPS0_BASE_ADDR + 0x0002A000)
+#define SPI0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0002C000)
+#define SPI1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0002D000)
+#define SAI0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0002F000)
+#define SAI1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00030000)
+#define SAI2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00031000)
+#define SAI3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00032000)
+#define CRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00033000)
+#define USBC0_BASE_ADDR     (AIPS0_BASE_ADDR + 0x00034000)
+#define PDB_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00036000)
+#define PIT_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00037000)
+#define FTM0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00038000)
+#define FTM1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00039000)
+#define ADC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0003B000)
+#define TCON0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0003D000)
+#define WDOG1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0003E000)
+#define LPTMR_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00040000)
+#define RLE_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00042000)
+#define MLB_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00043000)
+#define QSPI0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00044000)
+#define IOMUXC_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00048000)
+#define ANADIG_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00050000)
+#define USB_PHY0_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050800)
+#define USB_PHY1_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050C00)
+#define SCSC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00052000)
+#define DCU0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00058000)
+#define ASRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00060000)
+#define SPDIF_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00061000)
+#define ESAI_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00062000)
+#define ESAI_FIFO_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00063000)
+#define WDOG_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00065000)
+#define I2C1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00066000)
+#define I2C2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00067000)
+#define I2C3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000E6000)
+#define I2C4_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000E7000)
+#define WKUP_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006A000)
+#define CCM_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006B000)
+#define GPC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006C000)
+#define VREG_DIG_BASE_ADDR	(AIPS0_BASE_ADDR + 0x0006D000)
+#define SRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006E000)
+#define CMU_BASE_ADDR		(AIPS0_BASE_ADDR + 0x0006F000)
+#define GPIO0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF000)
+#define GPIO1_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF040)
+#define GPIO2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF080)
+#define GPIO3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF0C0)
+#define GPIO4_BASE_ADDR		(AIPS0_BASE_ADDR + 0x000FF100)
+
+/* AIPS 1 */
+#define OCOTP_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00025000)
+#define DDR_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0002E000)
+#define ESDHC0_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00031000)
+#define ESDHC1_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00032000)
+#define USBC1_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00034000)
+#define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
+#define ENET1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00051000)
+#define DCU1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00058000)
+#define NFC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00060000)
+
+#define QSPI0_AMBA_BASE		0x20000000
+
+/* MUX mode and PAD ctrl are in one register */
+#define CONFIG_IOMUX_SHARE_CONF_REG
+
+#define FEC_QUIRK_ENET_MAC
+#define I2C_QUIRK_REG
+
+/* MSCM interrupt rounter */
+#define MSCM_IRSPRC_CP0_EN				1
+#define MSCM_IRSPRC_NUM					112
+
+/* DDRMC */
+#define DDRMC_PHY_DQ_TIMING				0x00002613
+#define DDRMC_PHY_DQS_TIMING				0x00002615
+#define DDRMC_PHY_CTRL					0x00210000
+#define DDRMC_PHY_MASTER_CTRL				0x0001012a
+#define DDRMC_PHY_SLAVE_CTRL				0x00002000
+#define DDRMC_PHY_OFF					0x00000000
+#define DDRMC_PHY_PROC_PAD_ODT				0x00010101
+
+#define DDRMC_PHY50_DDR3_MODE				(1 << 12)
+#define DDRMC_PHY50_EN_SW_HALF_CYCLE			(1 << 8)
+
+#define DDRMC_CR00_DRAM_CLASS_DDR3			(0x6 << 8)
+#define DDRMC_CR00_DRAM_CLASS_LPDDR2			(0x5 << 8)
+#define DDRMC_CR00_START				1
+#define DDRMC_CR02_DRAM_TINIT(v)			((v) & 0xffffff)
+#define DDRMC_CR10_TRST_PWRON(v)			(v)
+#define DDRMC_CR11_CKE_INACTIVE(v)			(v)
+#define DDRMC_CR12_WRLAT(v)				(((v) & 0x1f) << 8)
+#define DDRMC_CR12_CASLAT_LIN(v)			((v) & 0x3f)
+#define DDRMC_CR13_TRC(v)				(((v) & 0xff) << 24)
+#define DDRMC_CR13_TRRD(v)				(((v) & 0xff) << 16)
+#define DDRMC_CR13_TCCD(v)				(((v) & 0x1f) << 8)
+#define DDRMC_CR13_TBST_INT_INTERVAL(v)			((v) & 0x7)
+#define DDRMC_CR14_TFAW(v)				(((v) & 0x3f) << 24)
+#define DDRMC_CR14_TRP(v)				(((v) & 0x1f) << 16)
+#define DDRMC_CR14_TWTR(v)				(((v) & 0xf) << 8)
+#define DDRMC_CR14_TRAS_MIN(v)				((v) & 0xff)
+#define DDRMC_CR16_TMRD(v)				(((v) & 0x1f) << 24)
+#define DDRMC_CR16_TRTP(v)				(((v) & 0xf) << 16)
+#define DDRMC_CR17_TRAS_MAX(v)				(((v) & 0x1ffff) << 8)
+#define DDRMC_CR17_TMOD(v)				((v) & 0xff)
+#define DDRMC_CR18_TCKESR(v)				(((v) & 0x1f) << 8)
+#define DDRMC_CR18_TCKE(v)				((v) & 0x7)
+#define DDRMC_CR20_AP_EN				(1 << 24)
+#define DDRMC_CR21_TRCD_INT(v)				(((v) & 0xff) << 16)
+#define DDRMC_CR21_TRAS_LOCKOUT(v)			((v) << 8)
+#define DDRMC_CR21_CCMAP_EN				1
+#define DDRMC_CR22_TDAL(v)				(((v) & 0x3f) << 16)
+#define DDRMC_CR23_BSTLEN(v)				(((v) & 0x7) << 24)
+#define DDRMC_CR23_TDLL(v)				((v) & 0xffff)
+#define DDRMC_CR24_TRP_AB(v)				((v) & 0x1f)
+#define DDRMC_CR25_TREF_EN				(1 << 16)
+#define DDRMC_CR26_TREF(v)				(((v) & 0xffff) << 16)
+#define DDRMC_CR26_TRFC(v)				((v) & 0x3ff)
+#define DDRMC_CR28_TREF_INT(v)				((v) & 0xffff)
+#define DDRMC_CR29_TPDEX(v)				((v) & 0xffff)
+#define DDRMC_CR30_TXPDLL(v)				((v) & 0xffff)
+#define DDRMC_CR31_TXSNR(v)				(((v) & 0xffff) << 16)
+#define DDRMC_CR31_TXSR(v)				((v) & 0xffff)
+#define DDRMC_CR33_EN_QK_SREF				(1 << 16)
+#define DDRMC_CR34_CKSRX(v)				(((v) & 0xf) << 16)
+#define DDRMC_CR34_CKSRE(v)				(((v) & 0xf) << 8)
+#define DDRMC_CR38_FREQ_CHG_EN(v)			(((v) & 0x1) << 8)
+#define DDRMC_CR39_PHY_INI_COM(v)			(((v) & 0xffff) << 16)
+#define DDRMC_CR39_PHY_INI_STA(v)			(((v) & 0xff) << 8)
+#define DDRMC_CR39_FRQ_CH_DLLOFF(v)			((v) & 0x3)
+#define DDRMC_CR41_PHY_INI_STRT_INI_DIS			1
+#define DDRMC_CR48_MR1_DA_0(v)				(((v) & 0xffff) << 16)
+#define DDRMC_CR48_MR0_DA_0(v)				((v) & 0xffff)
+#define DDRMC_CR66_ZQCL(v)				(((v) & 0xfff) << 16)
+#define DDRMC_CR66_ZQINIT(v)				((v) & 0xfff)
+#define DDRMC_CR67_ZQCS(v)				((v) & 0xfff)
+#define DDRMC_CR69_ZQ_ON_SREF_EX(v)			(((v) & 0xf) << 8)
+#define DDRMC_CR70_REF_PER_ZQ(v)			(v)
+#define DDRMC_CR72_ZQCS_ROTATE(v)			(((v) & 0x1) << 24)
+#define DDRMC_CR73_APREBIT(v)				(((v) & 0xf) << 24)
+#define DDRMC_CR73_COL_DIFF(v)				(((v) & 0x7) << 16)
+#define DDRMC_CR73_ROW_DIFF(v)				(((v) & 0x3) << 8)
+#define DDRMC_CR74_BANKSPLT_EN				(1 << 24)
+#define DDRMC_CR74_ADDR_CMP_EN				(1 << 16)
+#define DDRMC_CR74_CMD_AGE_CNT(v)			(((v) & 0xff) << 8)
+#define DDRMC_CR74_AGE_CNT(v)				((v) & 0xff)
+#define DDRMC_CR75_RW_PG_EN				(1 << 24)
+#define DDRMC_CR75_RW_EN				(1 << 16)
+#define DDRMC_CR75_PRI_EN				(1 << 8)
+#define DDRMC_CR75_PLEN					1
+#define DDRMC_CR76_NQENT_ACTDIS(v)			(((v) & 0x7) << 24)
+#define DDRMC_CR76_D_RW_G_BKCN(v)			(((v) & 0x3) << 16)
+#define DDRMC_CR76_W2R_SPLT_EN				(1 << 8)
+#define DDRMC_CR76_CS_EN				1
+#define DDRMC_CR77_CS_MAP				(1 << 24)
+#define DDRMC_CR77_DI_RD_INTLEAVE			(1 << 8)
+#define DDRMC_CR77_SWAP_EN				1
+#define DDRMC_CR78_Q_FULLNESS(v)			(((v) & 0x7) << 24)
+#define DDRMC_CR78_BUR_ON_FLY_BIT(v)			((v) & 0xf)
+#define DDRMC_CR79_CTLUPD_AREF(v)			(((v) & 0x1) << 24)
+#define DDRMC_CR80_MC_INIT_COMPLETE			(1 << 8)
+#define DDRMC_CR82_INT_MASK				(1 << 28)
+#define DDRMC_CR87_ODT_WR_MAPCS0(v)			((v) << 24)
+#define DDRMC_CR87_ODT_RD_MAPCS0(v)			((v) << 16)
+#define DDRMC_CR88_TODTL_CMD(v)				(((v) & 0x1f) << 16)
+#define DDRMC_CR89_AODT_RWSMCS(v)			((v) & 0xf)
+#define DDRMC_CR91_R2W_SMCSDL(v)			(((v) & 0x7) << 16)
+#define DDRMC_CR93_SW_LVL_MODE_OFF			(8)
+#define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << DDRMC_CR93_SW_LVL_MODE_OFF)
+#define DDRMC_CR93_SWLVL_LOAD				BIT(16)
+#define DDRMC_CR93_SWLVL_START				BIT(24)
+#define DDRMC_CR94_SWLVL_EXIT				BIT(0)
+#define DDRMC_CR94_SWLVL_OP_DONE			BIT(8)
+#define DDRMC_CR94_SWLVL_RESP_0_OFF			(24)
+#define DDRMC_CR95_SWLVL_RESP_1_OFF			(0)
+#define DDRMC_CR96_WLMRD(v)				(((v) & 0x3f) << 8)
+#define DDRMC_CR96_WLDQSEN(v)				((v) & 0x3f)
+#define DDRMC_CR97_WRLVL_EN				(1 << 24)
+#define DDRMC_CR98_WRLVL_DL_0(v)			((v) & 0xffff)
+#define DDRMC_CR99_WRLVL_DL_1(v)			((v) & 0xffff)
+#define DDRMC_CR101_PHY_RDLVL_EDGE_OFF			(24)
+#define DDRMC_CR101_PHY_RDLVL_EDGE BIT(DDRMC_CR101_PHY_RDLVL_EDGE_OFF)
+#define DDRMC_CR102_RDLVL_GT_REGEN			(1 << 16)
+#define DDRMC_CR102_RDLVL_REG_EN			(1 << 8)
+#define DDRMC_CR105_RDLVL_DL_0_OFF			(8)
+#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << DDRMC_CR105_RDLVL_DL_0_OFF)
+#define DDRMC_CR106_RDLVL_GTDL_0(v)			((v) & 0xff)
+#define DDRMC_CR110_RDLVL_DL_1_OFF			(0)
+#define DDRMC_CR110_RDLVL_DL_1(v)			((v) & 0xff)
+#define DDRMC_CR110_RDLVL_GTDL_1(v)			(((v) & 0xff) << 16)
+#define DDRMC_CR114_RDLVL_GTDL_2(v)			(((v) & 0xffff) << 8)
+#define DDRMC_CR115_RDLVL_GTDL_2(v)			((v) & 0xff)
+#define DDRMC_CR117_AXI0_W_PRI(v)			(((v) & 0x3) << 8)
+#define DDRMC_CR117_AXI0_R_PRI(v)			((v) & 0x3)
+#define DDRMC_CR118_AXI1_W_PRI(v)			(((v) & 0x3) << 24)
+#define DDRMC_CR118_AXI1_R_PRI(v)			(((v) & 0x3) << 16)
+#define DDRMC_CR120_AXI0_PRI1_RPRI(v)			(((v) & 0xf) << 24)
+#define DDRMC_CR120_AXI0_PRI0_RPRI(v)			(((v) & 0xf) << 16)
+#define DDRMC_CR121_AXI0_PRI3_RPRI(v)			(((v) & 0xf) << 8)
+#define DDRMC_CR121_AXI0_PRI2_RPRI(v)			((v) & 0xf)
+#define DDRMC_CR122_AXI1_PRI1_RPRI(v)			(((v) & 0xf) << 24)
+#define DDRMC_CR122_AXI1_PRI0_RPRI(v)			(((v) & 0xf) << 16)
+#define DDRMC_CR122_AXI0_PRIRLX(v)			((v) & 0x3ff)
+#define DDRMC_CR123_AXI1_PRI3_RPRI(v)			(((v) & 0xf) << 8)
+#define DDRMC_CR123_AXI1_PRI2_RPRI(v)			((v) & 0xf)
+#define DDRMC_CR123_AXI1_P_ODR_EN			(1 << 16)
+#define DDRMC_CR124_AXI1_PRIRLX(v)			((v) & 0x3ff)
+#define DDRMC_CR126_PHY_RDLAT(v)			(((v) & 0x3f) << 8)
+#define DDRMC_CR132_WRLAT_ADJ(v)			(((v) & 0x1f) << 8)
+#define DDRMC_CR132_RDLAT_ADJ(v)			((v) & 0x3f)
+#define DDRMC_CR137_PHYCTL_DL(v)			(((v) & 0xf) << 16)
+#define DDRMC_CR138_PHY_WRLV_MXDL(v)			(((v) & 0xffff) << 16)
+#define DDRMC_CR138_PHYDRAM_CK_EN(v)			(((v) & 0x7) << 8)
+#define DDRMC_CR139_PHY_WRLV_RESPLAT(v)			(((v) & 0xff) << 24)
+#define DDRMC_CR139_PHY_WRLV_LOAD(v)			(((v) & 0xff) << 16)
+#define DDRMC_CR139_PHY_WRLV_DLL(v)			(((v) & 0xff) << 8)
+#define DDRMC_CR139_PHY_WRLV_EN(v)			((v) & 0xff)
+#define DDRMC_CR140_PHY_WRLV_WW(v)			((v) & 0x3ff)
+#define DDRMC_CR143_RDLV_GAT_MXDL(v)			(((v) & 0xffff) << 16)
+#define DDRMC_CR143_RDLV_MXDL(v)			((v) & 0xffff)
+#define DDRMC_CR144_PHY_RDLVL_RES(v)			(((v) & 0xff) << 24)
+#define DDRMC_CR144_PHY_RDLV_LOAD(v)			(((v) & 0xff) << 16)
+#define DDRMC_CR144_PHY_RDLV_DLL(v)			(((v) & 0xff) << 8)
+#define DDRMC_CR144_PHY_RDLV_EN(v)			((v) & 0xff)
+#define DDRMC_CR145_PHY_RDLV_RR(v)			((v) & 0x3ff)
+#define DDRMC_CR146_PHY_RDLVL_RESP(v)			(v)
+#define DDRMC_CR147_RDLV_RESP_MASK(v)			((v) & 0xfffff)
+#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v)		((v) & 0xfffff)
+#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v)		(((v) & 0xf) << 8)
+#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v)		((v) & 0xf)
+#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v)	(((v) & 0x1f) << 27)
+#define DDRMC_CR154_PAD_ZQ_MODE(v)			(((v) & 0x3) << 21)
+#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v)		(((v) & 0x3) << 18)
+#define DDRMC_CR154_PAD_ZQ_HW_FOR(v)			(((v) & 0x1) << 14)
+#define DDRMC_CR155_AXI0_AWCACHE			(1 << 10)
+#define DDRMC_CR155_PAD_ODT_BYTE1(v)			(((v) & 0x7) << 3)
+#define DDRMC_CR155_PAD_ODT_BYTE0(v)			((v) & 0x7)
+#define DDRMC_CR158_TWR(v)				((v) & 0x3f)
+#define DDRMC_CR161_ODT_EN(v)				(((v) & 0x1) << 16)
+#define DDRMC_CR161_TODTH_RD(v)				(((v) & 0xf) << 8)
+#define DDRMC_CR161_TODTH_WR(v)				((v) & 0xf)
+
+/* System Reset Controller (SRC) */
+#define SRC_SRSR_SW_RST					(0x1 << 18)
+#define SRC_SRSR_RESETB					(0x1 << 7)
+#define SRC_SRSR_JTAG_RST				(0x1 << 5)
+#define SRC_SRSR_WDOG_M4				(0x1 << 4)
+#define SRC_SRSR_WDOG_A5				(0x1 << 3)
+#define SRC_SRSR_POR_RST				(0x1 << 0)
+#define SRC_SBMR1_BOOTCFG1_SDMMC        BIT(6)
+#define SRC_SBMR1_BOOTCFG1_MMC          BIT(4)
+#define SRC_SBMR2_BMOD_MASK             (0x3 << 24)
+#define SRC_SBMR2_BMOD_SHIFT            24
+#define SRC_SBMR2_BMOD_FUSES            0x0
+#define SRC_SBMR2_BMOD_SERIAL           0x1
+#define SRC_SBMR2_BMOD_RCON             0x2
+
+/* Slow Clock Source Controller Module (SCSC) */
+#define SCSC_SOSC_CTR_SOSC_EN            0x1
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* System Reset Controller (SRC) */
+struct src {
+	u32 scr;
+	u32 sbmr1;
+	u32 srsr;
+	u32 secr;
+	u32 gpsr;
+	u32 sicr;
+	u32 simr;
+	u32 sbmr2;
+	u32 gpr0;
+	u32 gpr1;
+	u32 gpr2;
+	u32 gpr3;
+	u32 gpr4;
+	u32 hab0;
+	u32 hab1;
+	u32 hab2;
+	u32 hab3;
+	u32 hab4;
+	u32 hab5;
+	u32 misc0;
+	u32 misc1;
+	u32 misc2;
+	u32 misc3;
+};
+
+/* Periodic Interrupt Timer (PIT) */
+struct pit_reg {
+	u32 mcr;
+	u32 recv0[55];
+	u32 ltmr64h;
+	u32 ltmr64l;
+	u32 recv1[6];
+	u32 ldval0;
+	u32 cval0;
+	u32 tctrl0;
+	u32 tflg0;
+	u32 ldval1;
+	u32 cval1;
+	u32 tctrl1;
+	u32 tflg1;
+	u32 ldval2;
+	u32 cval2;
+	u32 tctrl2;
+	u32 tflg2;
+	u32 ldval3;
+	u32 cval3;
+	u32 tctrl3;
+	u32 tflg3;
+	u32 ldval4;
+	u32 cval4;
+	u32 tctrl4;
+	u32 tflg4;
+	u32 ldval5;
+	u32 cval5;
+	u32 tctrl5;
+	u32 tflg5;
+	u32 ldval6;
+	u32 cval6;
+	u32 tctrl6;
+	u32 tflg6;
+	u32 ldval7;
+	u32 cval7;
+	u32 tctrl7;
+	u32 tflg7;
+};
+
+/* Watchdog Timer (WDOG) */
+struct wdog_regs {
+	u16 wcr;
+	u16 wsr;
+	u16 wrsr;
+	u16 wicr;
+	u16 wmcr;
+};
+
+/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */
+struct ddrmr_regs {
+	u32 cr[162];
+	u32 rsvd[94];
+	u32 phy[53];
+};
+
+/* On-Chip One Time Programmable Controller (OCOTP) */
+struct ocotp_regs {
+	u32 ctrl;
+	u32 ctrl_set;
+	u32 ctrl_clr;
+	u32 ctrl_tog;
+	u32 timing;
+	u32 rsvd0[3];
+	u32 data;
+	u32 rsvd1[3];
+	u32 read_ctrl;
+	u32 rsvd2[3];
+	u32 read_fuse_data;
+	u32 rsvd3[7];
+	u32 scs;
+	u32 scs_set;
+	u32 scs_clr;
+	u32 scs_tog;
+	u32 crc_addr;
+	u32 rsvd4[3];
+	u32 crc_value;
+	u32 rsvd5[3];
+	u32 version;
+	u32 rsvd6[0xdb];
+
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+	} bank[16];
+};
+
+struct fuse_bank0_regs {
+	u32 lock;
+	u32 rsvd0[3];
+	u32 uid_low;
+	u32 rsvd1[3];
+	u32 uid_high;
+	u32 rsvd2[0x17];
+};
+
+struct fuse_bank4_regs {
+	u32 sjc_resp0;
+	u32 rsvd0[3];
+	u32 sjc_resp1;
+	u32 rsvd1[3];
+	u32 mac_addr0;
+	u32 rsvd2[3];
+	u32 mac_addr1;
+	u32 rsvd3[3];
+	u32 mac_addr2;
+	u32 rsvd4[3];
+	u32 mac_addr3;
+	u32 rsvd5[3];
+	u32 gp1;
+	u32 rsvd6[3];
+	u32 gp2;
+	u32 rsvd7[3];
+};
+
+/* MSCM Interrupt Router */
+struct mscm_ir {
+	u32 ircp0ir;
+	u32 ircp1ir;
+	u32 rsvd1[6];
+	u32 ircpgir;
+	u32 rsvd2[23];
+	u16 irsprc[112];
+	u16 rsvd3[848];
+};
+
+/* SCSC */
+struct scsc_reg {
+	u32 sirc_ctr;
+	u32 sosc_ctr;
+};
+
+/* MSCM */
+struct mscm {
+	u32 cpxtype;
+	u32 cpxnum;
+	u32 cpxmaster;
+	u32 cpxcount;
+	u32 cpxcfg0;
+	u32 cpxcfg1;
+	u32 cpxcfg2;
+	u32 cpxcfg3;
+};
+
+#endif	/* __ASSEMBLER__*/
+
+#endif	/* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
new file mode 100644
index 0000000..8ba03e5
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __IOMUX_VF610_H__
+#define __IOMUX_VF610_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+/* Pad control groupings */
+#define VF610_UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \
+				PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_SDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | \
+				PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+				PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
+#define VF610_DDR_PAD_CTRL_1	(PAD_CTL_DSE_25ohm | \
+				PAD_CTL_INPUT_DIFFERENTIAL)
+#define VF610_I2C_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+				PAD_CTL_SPEED_HIGH | PAD_CTL_ODE | \
+				PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_NFC_IO_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+				PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | \
+				PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_NFC_CN_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+				PAD_CTL_DSE_25ohm | PAD_CTL_OBE_ENABLE)
+#define VF610_NFC_RB_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+				PAD_CTL_PUS_22K_UP | PAD_CTL_IBE_ENABLE)
+
+#define VF610_QSPI_PAD_CTRL	(PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \
+				PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
+
+#define VF610_GPIO_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \
+				PAD_CTL_IBE_ENABLE)
+
+#define VF610_DSPI_PAD_CTRL	(PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \
+				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
+#define VF610_DSPI_SIN_PAD_CTRL	(PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \
+				PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
+#define VF610_DCU_PAD_CTRL     (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
+				PAD_CTL_DSE_37ohm | PAD_CTL_OBE_ENABLE)
+
+enum {
+	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTA6__RMII0_CLKOUT		= IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTA7__GPIO_134		= IOMUX_PAD(0x0218, 0x0218, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTA17__GPIO_7			= IOMUX_PAD(0x001c, 0x001c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTA20__GPIO_10		= IOMUX_PAD(0x0028, 0x0028, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTA21__GPIO_11		= IOMUX_PAD(0x002c, 0x002c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTA30__GPIO_20		= IOMUX_PAD(0x0050, 0x0050, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTA31__GPIO_21		= IOMUX_PAD(0x0054, 0x0054, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB0__GPIO_22			= IOMUX_PAD(0x0058, 0x0058, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB1__GPIO_23			= IOMUX_PAD(0x005C, 0x005C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB4__UART1_TX		= IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTB5__UART1_RX		= IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTB6__GPIO_28			= IOMUX_PAD(0x0070, 0x0070, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB7__GPIO_29			= IOMUX_PAD(0x0074, 0x0074, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB8__GPIO_30			= IOMUX_PAD(0x0078, 0x0078, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB9__GPIO_31			= IOMUX_PAD(0x007C, 0x007C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB10__UART0_TX		= IOMUX_PAD(0x0080, 0x0080, 1, __NA_, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTB11__UART0_RX		= IOMUX_PAD(0x0084, 0x0084, 1, __NA_, 0, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTB12__GPIO_34		= IOMUX_PAD(0x0088, 0x0088, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB13__GPIO_35		= IOMUX_PAD(0x008c, 0x008c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB16__GPIO_38		= IOMUX_PAD(0x0098, 0x0098, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB17__GPIO_39		= IOMUX_PAD(0x009c, 0x009c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB18__GPIO_40		= IOMUX_PAD(0x00a0, 0x00a0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB21__GPIO_43		= IOMUX_PAD(0x00ac, 0x00ac, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB22__GPIO_44		= IOMUX_PAD(0x00b0, 0x00b0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB23__GPIO_93		= IOMUX_PAD(0x0174, 0x0174, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB26__GPIO_96		= IOMUX_PAD(0x0180, 0x0180, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTB28__GPIO_98		= IOMUX_PAD(0x0188, 0x0188, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC1__GPIO_46			= IOMUX_PAD(0x00b8, 0x00b8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC1__RMII0_MDIO		= IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC0__GPIO_45			= IOMUX_PAD(0x00b4, 0x00b4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC0__RMII0_MDC		= IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC2__RMII0_CRS_DV		= IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC2__GPIO_47			= IOMUX_PAD(0x00bc, 0x00bc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC3__RMII0_RD1		= IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC3__GPIO_48			= IOMUX_PAD(0x00c0, 0x00c0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC4__RMII0_RD0		= IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC4__GPIO_49			= IOMUX_PAD(0x00c4, 0x00c4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC5__RMII0_RXER		= IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC5__GPIO_50			= IOMUX_PAD(0x00c8, 0x00c8, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC6__RMII0_TD1		= IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC6__GPIO_51			= IOMUX_PAD(0x00cc, 0x00cc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC7__RMII0_TD0		= IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC7__GPIO_52			= IOMUX_PAD(0x00D0, 0x00D0, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC8__RMII0_TXEN		= IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC8__GPIO_53			= IOMUX_PAD(0x00D4, 0x00D4, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC10__RMII1_MDIO		= IOMUX_PAD(0x00dc, 0x00dc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC9__RMII1_MDC		= IOMUX_PAD(0x00d8, 0x00d8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC11__RMII1_CRS_DV		= IOMUX_PAD(0x00e0, 0x00e0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC12__RMII1_RD1		= IOMUX_PAD(0x00e4, 0x00e4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC13__RMII1_RD0		= IOMUX_PAD(0x00e8, 0x00e8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC14__RMII1_RXER		= IOMUX_PAD(0x00ec, 0x00ec, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC15__RMII1_TD1		= IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC16__RMII1_TD0		= IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTC17__RMII1_TXEN		= IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+	VF610_PAD_PTD5__DSPI1_CS0		= IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL),
+	VF610_PAD_PTD6__DSPI1_SIN		= IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL),
+	VF610_PAD_PTD7__DSPI1_SOUT		= IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL),
+	VF610_PAD_PTD8__DSPI1_SCK		= IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL),
+	VF610_PAD_PTC29__GPIO_102		= IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTC30__GPIO_103		= IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTA24__ESDHC1_CLK		= IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTA25__ESDHC1_CMD		= IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTA26__ESDHC1_DAT0		= IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTA27__ESDHC1_DAT1		= IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTA28__ESDHC1_DAT2		= IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTA29__ESDHC1_DAT3		= IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+	VF610_PAD_PTB14__I2C0_SCL		= IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
+	VF610_PAD_PTB15__I2C0_SDA		= IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
+	VF610_PAD_PTA22__I2C2_SCL		= IOMUX_PAD(0x0030, 0x0030, 6, 0x034c, 0, VF610_I2C_PAD_CTRL),
+	VF610_PAD_PTA23__I2C2_SDA		= IOMUX_PAD(0x0034, 0x0034, 6, 0x0350, 0, VF610_I2C_PAD_CTRL),
+	VF610_PAD_PTD31__NF_IO15		= IOMUX_PAD(0x00fc, 0x00fc, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD31__GPIO_63		= IOMUX_PAD(0x00fc, 0x00fc, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD30__NF_IO14		= IOMUX_PAD(0x0100, 0x0100, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD30__GPIO_64		= IOMUX_PAD(0x0100, 0x0100, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD29__NF_IO13		= IOMUX_PAD(0x0104, 0x0104, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD29__GPIO_65		= IOMUX_PAD(0x0104, 0x0104, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD28__NF_IO12		= IOMUX_PAD(0x0108, 0x0108, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD28__GPIO_66		= IOMUX_PAD(0x0108, 0x0108, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD27__NF_IO11		= IOMUX_PAD(0x010c, 0x010c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD27__GPIO_67		= IOMUX_PAD(0x010c, 0x010c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD26__NF_IO10		= IOMUX_PAD(0x0110, 0x0110, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD26__GPIO_68		= IOMUX_PAD(0x0110, 0x0110, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD25__NF_IO9			= IOMUX_PAD(0x0114, 0x0114, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD25__GPIO_69		= IOMUX_PAD(0x0114, 0x0114, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD24__NF_IO8			= IOMUX_PAD(0x0118, 0x0118, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD24__GPIO_70		= IOMUX_PAD(0x0118, 0x0118, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD23__NF_IO7			= IOMUX_PAD(0x011c, 0x011c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD0__QSPI0_A_QSCK		= IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD0__UART2_TX		= IOMUX_PAD(0x013c, 0x013c, 2, 0x38c, 2, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTD1__QSPI0_A_CS0		= IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD1__UART2_RX		= IOMUX_PAD(0x0140, 0x0140, 2, 0x388, 2, VF610_UART_PAD_CTRL),
+	VF610_PAD_PTD2__QSPI0_A_DATA3		= IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD2__GPIO_81			= IOMUX_PAD(0x0144, 0x0144, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD3__QSPI0_A_DATA2		= IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD3__GPIO_82			= IOMUX_PAD(0x0148, 0x0148, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD4__GPIO_83			= IOMUX_PAD(0x014C, 0x014C, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD4__QSPI0_A_DATA1		= IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD5__QSPI0_A_DATA0		= IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD7__QSPI0_B_QSCK		= IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD8__QSPI0_B_CS0		= IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD9__QSPI0_B_DATA3		= IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD9__GPIO_88			= IOMUX_PAD(0x0160, 0x0160, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD10__QSPI0_B_DATA2		= IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD10__GPIO_89		= IOMUX_PAD(0x0164, 0x0164, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD11__QSPI0_B_DATA1		= IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD11__GPIO_90		= IOMUX_PAD(0x0168, 0x0168, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD12__QSPI0_B_DATA0		= IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD12__GPIO_91		= IOMUX_PAD(0x016c, 0x016c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD13__GPIO_92		= IOMUX_PAD(0x0170, 0x0170, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
+	VF610_PAD_PTD22__NF_IO6			= IOMUX_PAD(0x0120, 0x0120, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD21__NF_IO5			= IOMUX_PAD(0x0124, 0x0124, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD20__NF_IO4			= IOMUX_PAD(0x0128, 0x0128, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD19__NF_IO3			= IOMUX_PAD(0x012c, 0x012c, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD18__NF_IO2			= IOMUX_PAD(0x0130, 0x0130, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD17__NF_IO1			= IOMUX_PAD(0x0134, 0x0134, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTD16__NF_IO0			= IOMUX_PAD(0x0138, 0x0138, 2, __NA_, 0, VF610_NFC_IO_PAD_CTRL),
+	VF610_PAD_PTB24__NF_WE_B		= IOMUX_PAD(0x0178, 0x0178, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+	VF610_PAD_PTB25__NF_CE0_B		= IOMUX_PAD(0x017c, 0x017c, 5, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
+	VF610_PAD_PTB27__NF_RE_B 		= IOMUX_PAD(0x0184, 0x0184, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
+	VF610_PAD_PTC26__NF_RB_B 		= IOMUX_PAD(0x018C, 0x018C, 5, __NA_, 0, VF610_NFC_RB_PAD_CTRL),
+
+	VF610_PAD_PTC27__NF_ALE  		= IOMUX_PAD(0x0190, 0x0190, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
+	VF610_PAD_PTC28__NF_CLE  		= IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
+
+	VF610_PAD_PTE0__DCU0_HSYNC		= IOMUX_PAD(0x01a4, 0x01a4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE1__DCU0_VSYNC		= IOMUX_PAD(0x01a8, 0x01a8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE2__DCU0_PCLK		= IOMUX_PAD(0x01ac, 0x01ac, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE4__DCU0_DE			= IOMUX_PAD(0x01b4, 0x01b4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE5__DCU0_R0			= IOMUX_PAD(0x01b8, 0x01b8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE6__DCU0_R1			= IOMUX_PAD(0x01bc, 0x01bc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE7__DCU0_R2			= IOMUX_PAD(0x01c0, 0x01c0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE8__DCU0_R3			= IOMUX_PAD(0x01c4, 0x01c4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE9__DCU0_R4			= IOMUX_PAD(0x01c8, 0x01c8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE10__DCU0_R5		= IOMUX_PAD(0x01cc, 0x01cc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE11__DCU0_R6		= IOMUX_PAD(0x01d0, 0x01d0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE12__DCU0_R7		= IOMUX_PAD(0x01d4, 0x01d4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE13__DCU0_G0		= IOMUX_PAD(0x01d8, 0x01d8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE14__DCU0_G1		= IOMUX_PAD(0x01dc, 0x01dc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE15__DCU0_G2		= IOMUX_PAD(0x01e0, 0x01e0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE16__DCU0_G3		= IOMUX_PAD(0x01e4, 0x01e4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE17__DCU0_G4		= IOMUX_PAD(0x01e8, 0x01e8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE18__DCU0_G5		= IOMUX_PAD(0x01ec, 0x01ec, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE19__DCU0_G6		= IOMUX_PAD(0x01f0, 0x01f0, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE20__DCU0_G7		= IOMUX_PAD(0x01f4, 0x01f4, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE21__DCU0_B0		= IOMUX_PAD(0x01f8, 0x01f8, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE22__DCU0_B1		= IOMUX_PAD(0x01fc, 0x01fc, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE23__DCU0_B2		= IOMUX_PAD(0x0200, 0x0200, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE24__DCU0_B3		= IOMUX_PAD(0x0204, 0x0204, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE25__DCU0_B4		= IOMUX_PAD(0x0208, 0x0208, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE26__DCU0_B5		= IOMUX_PAD(0x020c, 0x020c, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE27__DCU0_B6		= IOMUX_PAD(0x0210, 0x0210, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+	VF610_PAD_PTE28__DCU0_B7		= IOMUX_PAD(0x0214, 0x0214, 1, __NA_, 0, VF610_DCU_PAD_CTRL),
+
+	VF610_PAD_DDR_RESETB			= IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A15__DDR_A_15		= IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A14__DDR_A_14		= IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A13__DDR_A_13		= IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A12__DDR_A_12		= IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A11__DDR_A_11		= IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A10__DDR_A_10		= IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A9__DDR_A_9		= IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A8__DDR_A_8		= IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A7__DDR_A_7		= IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A6__DDR_A_6		= IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A5__DDR_A_5		= IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A4__DDR_A_4		= IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A3__DDR_A_3		= IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A2__DDR_A_2		= IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A1__DDR_A_1		= IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_A0__DDR_A_0		= IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_BA2__DDR_BA_2		= IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_BA1__DDR_BA_1		= IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_BA0__DDR_BA_0		= IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_CAS__DDR_CAS_B		= IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_CKE__DDR_CKE_0		= IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_CLK__DDR_CLK_0		= IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_CS__DDR_CS_B_0		= IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_D15__DDR_D_15		= IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D14__DDR_D_14		= IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D13__DDR_D_13		= IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D12__DDR_D_12		= IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D11__DDR_D_11		= IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D10__DDR_D_10		= IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D9__DDR_D_9		= IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D8__DDR_D_8		= IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D7__DDR_D_7		= IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D6__DDR_D_6		= IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D5__DDR_D_5		= IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D4__DDR_D_4		= IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D3__DDR_D_3		= IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D2__DDR_D_2		= IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D1__DDR_D_1		= IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_D0__DDR_D_0		= IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_DQM1__DDR_DQM_1		= IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_DQM0__DDR_DQM_0		= IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_DQS1__DDR_DQS_1		= IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_DQS0__DDR_DQS_0		= IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+	VF610_PAD_DDR_RAS__DDR_RAS_B		= IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_WE__DDR_WE_B		= IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_ODT1__DDR_ODT_0		= IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_ODT0__DDR_ODT_1		= IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1	= IOMUX_PAD(0x02dc, 0x02dc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2	= IOMUX_PAD(0x02e0, 0x02e0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+};
+
+#endif	/* __IOMUX_VF610_H__ */
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
new file mode 100644
index 0000000..2fb824b
--- /dev/null
+++ b/arch/arm/include/asm/armv7.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ */
+#ifndef ARMV7_H
+#define ARMV7_H
+
+/* Cortex-A9 revisions */
+#define MIDR_CORTEX_A9_R0P1	0x410FC091
+#define MIDR_CORTEX_A9_R1P2	0x411FC092
+#define MIDR_CORTEX_A9_R1P3	0x411FC093
+#define MIDR_CORTEX_A9_R2P10	0x412FC09A
+
+/* Cortex-A15 revisions */
+#define MIDR_CORTEX_A15_R0P0	0x410FC0F0
+#define MIDR_CORTEX_A15_R2P2	0x412FC0F2
+
+/* Cortex-A7 revisions */
+#define MIDR_CORTEX_A7_R0P0	0x410FC070
+
+#define MIDR_PRIMARY_PART_MASK	0xFF0FFFF0
+
+/* ID_PFR1 feature fields */
+#define CPUID_ARM_SEC_SHIFT		4
+#define CPUID_ARM_SEC_MASK		(0xF << CPUID_ARM_SEC_SHIFT)
+#define CPUID_ARM_VIRT_SHIFT		12
+#define CPUID_ARM_VIRT_MASK		(0xF << CPUID_ARM_VIRT_SHIFT)
+#define CPUID_ARM_GENTIMER_SHIFT	16
+#define CPUID_ARM_GENTIMER_MASK		(0xF << CPUID_ARM_GENTIMER_SHIFT)
+
+/* valid bits in CBAR register / PERIPHBASE value */
+#define CBAR_MASK			0xFFFF8000
+
+/* CCSIDR */
+#define CCSIDR_LINE_SIZE_OFFSET		0
+#define CCSIDR_LINE_SIZE_MASK		0x7
+#define CCSIDR_ASSOCIATIVITY_OFFSET	3
+#define CCSIDR_ASSOCIATIVITY_MASK	(0x3FF << 3)
+#define CCSIDR_NUM_SETS_OFFSET		13
+#define CCSIDR_NUM_SETS_MASK		(0x7FFF << 13)
+
+/*
+ * Values for InD field in CSSELR
+ * Selects the type of cache
+ */
+#define ARMV7_CSSELR_IND_DATA_UNIFIED	0
+#define ARMV7_CSSELR_IND_INSTRUCTION	1
+
+/* Values for Ctype fields in CLIDR */
+#define ARMV7_CLIDR_CTYPE_NO_CACHE		0
+#define ARMV7_CLIDR_CTYPE_INSTRUCTION_ONLY	1
+#define ARMV7_CLIDR_CTYPE_DATA_ONLY		2
+#define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA	3
+#define ARMV7_CLIDR_CTYPE_UNIFIED		4
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/barriers.h>
+
+/* read L2 control register (L2CTLR) */
+static inline uint32_t read_l2ctlr(void)
+{
+	uint32_t val = 0;
+
+	asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
+
+	return val;
+}
+
+/* write L2 control register (L2CTLR) */
+static inline void write_l2ctlr(uint32_t val)
+{
+	/*
+	 * Note: L2CTLR can only be written when the L2 memory system
+	 * is idle, ie before the MMU is enabled.
+	 */
+	asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
+	isb();
+}
+
+/*
+ * Workaround for ARM errata # 798870
+ * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
+ * stalled for 1024 cycles to verify that its hazard condition still exists.
+ */
+static inline void v7_enable_l2_hazard_detect(void)
+{
+	uint32_t val;
+
+	/* L2ACTLR[7]: Enable hazard detect timeout */
+	asm volatile ("mrc     p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
+	val |= (1 << 7);
+	asm volatile ("mcr     p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
+}
+
+/*
+ * Workaround for ARM errata # 799270
+ * Ensure that the L2 logic has been used within the previous 256 cycles
+ * before modifying the ACTLR.SMP bit. This is required during boot before
+ * MMU has been enabled, or during a specified reset or power down sequence.
+ */
+static inline void v7_enable_smp(uint32_t address)
+{
+	uint32_t temp, val;
+
+	/* Read auxiliary control register */
+	asm volatile ("mrc     p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
+
+	/* Enable SMP */
+	val |= (1 << 6);
+
+	/* Dummy read to assure L2 access */
+	temp = readl(address);
+	temp &= 0;
+	val |= temp;
+
+	/* Write auxiliary control register */
+	asm volatile ("mcr     p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
+
+	CP15DSB;
+	CP15ISB;
+}
+
+void v7_en_l2_hazard_detect(void);
+void v7_outer_cache_enable(void);
+void v7_outer_cache_disable(void);
+void v7_outer_cache_flush_all(void);
+void v7_outer_cache_inval_all(void);
+void v7_outer_cache_flush_range(u32 start, u32 end);
+void v7_outer_cache_inval_range(u32 start, u32 end);
+
+#ifdef CONFIG_ARMV7_NONSEC
+
+int armv7_init_nonsec(void);
+int armv7_apply_memory_carveout(u64 *start, u64 *size);
+bool armv7_boot_nonsec(void);
+
+/* defined in assembly file */
+unsigned int _nonsec_init(void);
+void _do_nonsec_entry(void *target_pc, unsigned long r0,
+		      unsigned long r1, unsigned long r2);
+void _smp_pen(void);
+
+extern char __secure_start[];
+extern char __secure_end[];
+extern char __secure_stack_start[];
+extern char __secure_stack_end[];
+
+#endif /* CONFIG_ARMV7_NONSEC */
+
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
+				 u32 cpu_rev_comb, u32 cpu_variant,
+				 u32 cpu_rev);
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+			  u32 cpu_variant, u32 cpu_rev);
+#endif /* ! __ASSEMBLY__ */
+
+#endif
diff --git a/arch/arm/include/asm/armv7_mpu.h b/arch/arm/include/asm/armv7_mpu.h
new file mode 100644
index 0000000..8f77ec4
--- /dev/null
+++ b/arch/arm/include/asm/armv7_mpu.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef _ASM_ARMV7_MPU_H
+#define _ASM_ARMV7_MPU_H
+
+#ifdef CONFIG_CPU_V7M
+#define AP_SHIFT			24
+#define XN_SHIFT			28
+#define TEX_SHIFT			19
+#define S_SHIFT				18
+#define C_SHIFT				17
+#define B_SHIFT				16
+#else /* CONFIG_CPU_V7R */
+#define XN_SHIFT			12
+#define AP_SHIFT			8
+#define TEX_SHIFT			3
+#define S_SHIFT				2
+#define C_SHIFT				1
+#define B_SHIFT				0
+#endif /* CONFIG_CPU_V7R */
+
+#define CACHEABLE			BIT(C_SHIFT)
+#define BUFFERABLE			BIT(B_SHIFT)
+#define SHAREABLE			BIT(S_SHIFT)
+#define REGION_SIZE_SHIFT		1
+#define ENABLE_REGION			BIT(0)
+#define DISABLE_REGION			0
+
+enum region_number {
+	REGION_0 = 0,
+	REGION_1,
+	REGION_2,
+	REGION_3,
+	REGION_4,
+	REGION_5,
+	REGION_6,
+	REGION_7,
+};
+
+enum ap {
+	NO_ACCESS = 0,
+	PRIV_RW_USR_NO,
+	PRIV_RW_USR_RO,
+	PRIV_RW_USR_RW,
+	UNPREDICTABLE,
+	PRIV_RO_USR_NO,
+	PRIV_RO_USR_RO,
+};
+
+enum mr_attr {
+	STRONG_ORDER = 0,
+	SHARED_WRITE_BUFFERED,
+	O_I_WT_NO_WR_ALLOC,
+	O_I_WB_NO_WR_ALLOC,
+	O_I_NON_CACHEABLE,
+	O_I_WB_RD_WR_ALLOC,
+	DEVICE_NON_SHARED,
+};
+enum size {
+	REGION_8MB = 22,
+	REGION_16MB,
+	REGION_32MB,
+	REGION_64MB,
+	REGION_128MB,
+	REGION_256MB,
+	REGION_512MB,
+	REGION_1GB,
+	REGION_2GB,
+	REGION_4GB,
+};
+
+enum xn {
+	XN_DIS = 0,
+	XN_EN,
+};
+
+struct mpu_region_config {
+	uint32_t start_addr;
+	enum region_number region_no;
+	enum xn xn;
+	enum ap ap;
+	enum mr_attr mr_attr;
+	enum size reg_size;
+};
+
+void disable_mpu(void);
+void enable_mpu(void);
+int mpu_enabled(void);
+void mpu_config(struct mpu_region_config *reg_config);
+void setup_mpu_regions(struct mpu_region_config *rgns, u32 num_rgns);
+
+static inline u32 get_attr_encoding(u32 mr_attr)
+{
+	u32 attr;
+
+	switch (mr_attr) {
+	case STRONG_ORDER:
+		attr = SHAREABLE;
+		break;
+	case SHARED_WRITE_BUFFERED:
+		attr = BUFFERABLE;
+		break;
+	case O_I_WT_NO_WR_ALLOC:
+		attr = CACHEABLE;
+		break;
+	case O_I_WB_NO_WR_ALLOC:
+		attr = CACHEABLE | BUFFERABLE;
+		break;
+	case O_I_NON_CACHEABLE:
+		attr = 1 << TEX_SHIFT;
+		break;
+	case O_I_WB_RD_WR_ALLOC:
+		attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE;
+		break;
+	case DEVICE_NON_SHARED:
+		attr = (2 << TEX_SHIFT) | BUFFERABLE;
+		break;
+	default:
+		attr = 0; /* strongly ordered */
+		break;
+	};
+
+	return attr;
+}
+
+#endif /* _ASM_ARMV7_MPU_H */
diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h
new file mode 100644
index 0000000..ad67b4f
--- /dev/null
+++ b/arch/arm/include/asm/armv7m.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010,2011
+ * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ */
+
+#ifndef ARMV7M_H
+#define ARMV7M_H
+
+/* armv7m fixed base addresses */
+#define V7M_SCS_BASE		0xE000E000
+#define V7M_NVIC_BASE		(V7M_SCS_BASE + 0x0100)
+#define V7M_SCB_BASE		(V7M_SCS_BASE + 0x0D00)
+#define V7M_PROC_FTR_BASE	(V7M_SCS_BASE + 0x0D78)
+#define V7M_MPU_BASE		(V7M_SCS_BASE + 0x0D90)
+#define V7M_FPU_BASE		(V7M_SCS_BASE + 0x0F30)
+#define V7M_CACHE_MAINT_BASE	(V7M_SCS_BASE + 0x0F50)
+#define V7M_ACCESS_CNTL_BASE	(V7M_SCS_BASE + 0x0F90)
+
+#define V7M_SCB_VTOR		0x08
+
+#if !defined(__ASSEMBLY__)
+struct v7m_scb {
+	uint32_t cpuid;		/* CPUID Base Register */
+	uint32_t icsr;		/* Interrupt Control and State Register */
+	uint32_t vtor;		/* Vector Table Offset Register */
+	uint32_t aircr;		/* App Interrupt and Reset Control Register */
+	uint32_t scr;		/* offset 0x10: System Control Register */
+	uint32_t ccr;		/* offset 0x14: Config and Control Register */
+	uint32_t shpr1;		/* offset 0x18: System Handler Priority Reg 1 */
+	uint32_t shpr2;		/* offset 0x1c: System Handler Priority Reg 2 */
+	uint32_t shpr3;		/* offset 0x20: System Handler Priority Reg 3 */
+	uint32_t shcrs;		/* offset 0x24: System Handler Control State */
+	uint32_t cfsr;		/* offset 0x28: Configurable Fault Status Reg */
+	uint32_t hfsr;		/* offset 0x2C: HardFault Status Register */
+	uint32_t res;		/* offset 0x30: reserved */
+	uint32_t mmar;		/* offset 0x34: MemManage Fault Address Reg */
+	uint32_t bfar;		/* offset 0x38: BusFault Address Reg */
+	uint32_t afsr;		/* offset 0x3C: Auxiliary Fault Status Reg */
+};
+#define V7M_SCB				((struct v7m_scb *)V7M_SCB_BASE)
+
+#define V7M_AIRCR_VECTKEY		0x5fa
+#define V7M_AIRCR_VECTKEY_SHIFT		16
+#define V7M_AIRCR_ENDIAN		(1 << 15)
+#define V7M_AIRCR_PRIGROUP_SHIFT	8
+#define V7M_AIRCR_PRIGROUP_MSK		(0x7 << V7M_AIRCR_PRIGROUP_SHIFT)
+#define V7M_AIRCR_SYSRESET		(1 << 2)
+
+#define V7M_ICSR_VECTACT_MSK		0xFF
+
+#define V7M_CCR_DCACHE			16
+#define V7M_CCR_ICACHE			17
+
+struct v7m_mpu {
+	uint32_t type;		/* Type Register */
+	uint32_t ctrl;		/* Control Register */
+	uint32_t rnr;		/* Region Number Register */
+	uint32_t rbar;		/* Region Base Address Register */
+	uint32_t rasr;		/* Region Attribute and Size Register */
+};
+#define V7M_MPU				((struct v7m_mpu *)V7M_MPU_BASE)
+
+#endif /* !defined(__ASSEMBLY__) */
+#endif /* ARMV7M_H */
diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h
new file mode 100644
index 0000000..40d54dc
--- /dev/null
+++ b/arch/arm/include/asm/armv8/cpu.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define MIDR_PARTNUM_CORTEX_A35	0xD04
+#define MIDR_PARTNUM_CORTEX_A53	0xD03
+#define MIDR_PARTNUM_CORTEX_A72	0xD08
+#define MIDR_PARTNUM_SHIFT	0x4
+#define MIDR_PARTNUM_MASK	(0xFFF << 0x4)
+
+static inline unsigned int read_midr(void)
+{
+	unsigned long val;
+
+	asm volatile("mrs %0, midr_el1" : "=r" (val));
+
+	return val;
+}
+
+#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)
+#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)
+#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
+			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
new file mode 100644
index 0000000..4a57320
--- /dev/null
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ */
+
+#ifndef _ASM_ARMV8_MMU_H_
+#define _ASM_ARMV8_MMU_H_
+
+#include <linux/const.h>
+
+/*
+ * block/section address mask and size definitions.
+ */
+
+/* PAGE_SHIFT determines the page size */
+#undef  PAGE_SIZE
+#define PAGE_SHIFT		12
+#define PAGE_SIZE		(1 << PAGE_SHIFT)
+#define PAGE_MASK		(~(PAGE_SIZE - 1))
+
+/***************************************************************/
+
+/*
+ * Memory types
+ */
+#define MT_DEVICE_NGNRNE	0
+#define MT_DEVICE_NGNRE		1
+#define MT_DEVICE_GRE		2
+#define MT_NORMAL_NC		3
+#define MT_NORMAL		4
+
+#define MEMORY_ATTRIBUTES	((0x00 << (MT_DEVICE_NGNRNE * 8)) |	\
+				(0x04 << (MT_DEVICE_NGNRE * 8))   |	\
+				(0x0c << (MT_DEVICE_GRE * 8))     |	\
+				(0x44 << (MT_NORMAL_NC * 8))      |	\
+				(UL(0xff) << (MT_NORMAL * 8)))
+
+/*
+ * Hardware page table definitions.
+ *
+ */
+
+#define PTE_TYPE_MASK		(3 << 0)
+#define PTE_TYPE_FAULT		(0 << 0)
+#define PTE_TYPE_TABLE		(3 << 0)
+#define PTE_TYPE_PAGE		(3 << 0)
+#define PTE_TYPE_BLOCK		(1 << 0)
+#define PTE_TYPE_VALID		(1 << 0)
+
+#define PTE_TABLE_PXN		(1UL << 59)
+#define PTE_TABLE_XN		(1UL << 60)
+#define PTE_TABLE_AP		(1UL << 61)
+#define PTE_TABLE_NS		(1UL << 63)
+
+/*
+ * Block
+ */
+#define PTE_BLOCK_MEMTYPE(x)	((x) << 2)
+#define PTE_BLOCK_NS            (1 << 5)
+#define PTE_BLOCK_NON_SHARE	(0 << 8)
+#define PTE_BLOCK_OUTER_SHARE	(2 << 8)
+#define PTE_BLOCK_INNER_SHARE	(3 << 8)
+#define PTE_BLOCK_AF		(1 << 10)
+#define PTE_BLOCK_NG		(1 << 11)
+#define PTE_BLOCK_PXN		(UL(1) << 53)
+#define PTE_BLOCK_UXN		(UL(1) << 54)
+
+/*
+ * AttrIndx[2:0]
+ */
+#define PMD_ATTRINDX(t)		((t) << 2)
+#define PMD_ATTRINDX_MASK	(7 << 2)
+#define PMD_ATTRMASK		(PTE_BLOCK_PXN		| \
+				 PTE_BLOCK_UXN		| \
+				 PMD_ATTRINDX_MASK	| \
+				 PTE_TYPE_VALID)
+
+/*
+ * TCR flags.
+ */
+#define TCR_T0SZ(x)		((64 - (x)) << 0)
+#define TCR_IRGN_NC		(0 << 8)
+#define TCR_IRGN_WBWA		(1 << 8)
+#define TCR_IRGN_WT		(2 << 8)
+#define TCR_IRGN_WBNWA		(3 << 8)
+#define TCR_IRGN_MASK		(3 << 8)
+#define TCR_ORGN_NC		(0 << 10)
+#define TCR_ORGN_WBWA		(1 << 10)
+#define TCR_ORGN_WT		(2 << 10)
+#define TCR_ORGN_WBNWA		(3 << 10)
+#define TCR_ORGN_MASK		(3 << 10)
+#define TCR_SHARED_NON		(0 << 12)
+#define TCR_SHARED_OUTER	(2 << 12)
+#define TCR_SHARED_INNER	(3 << 12)
+#define TCR_TG0_4K		(0 << 14)
+#define TCR_TG0_64K		(1 << 14)
+#define TCR_TG0_16K		(2 << 14)
+#define TCR_EPD1_DISABLE	(1 << 23)
+
+#define TCR_EL1_RSVD		(1 << 31)
+#define TCR_EL2_RSVD		(1 << 31 | 1 << 23)
+#define TCR_EL3_RSVD		(1 << 31 | 1 << 23)
+
+#ifndef __ASSEMBLY__
+static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
+{
+	asm volatile("dsb sy");
+	if (el == 1) {
+		asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
+	} else if (el == 2) {
+		asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
+	} else if (el == 3) {
+		asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
+	} else {
+		hang();
+	}
+	asm volatile("isb");
+}
+
+struct mm_region {
+	u64 virt;
+	u64 phys;
+	u64 size;
+	u64 attrs;
+};
+
+extern struct mm_region *mem_map;
+void setup_pgtables(void);
+u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
+#endif
+
+#endif /* _ASM_ARMV8_MMU_H_ */
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h
new file mode 100644
index 0000000..0f86c72
--- /dev/null
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 NXP Semiconductor, Inc.
+ */
+
+#ifndef __SEC_FIRMWARE_H_
+#define __SEC_FIRMWARE_H_
+
+#define PSCI_INVALID_VER		0xffffffff
+#define SEC_JR3_OFFSET			0x40000
+#define WORD_MASK			0xffffffff
+#define WORD_SHIFT			32
+
+int sec_firmware_init(const void *, u32 *, u32 *, u32 *, u32 *);
+int _sec_firmware_entry(const void *, u32 *, u32 *);
+bool sec_firmware_is_valid(const void *);
+bool sec_firmware_support_hwrng(void);
+int sec_firmware_get_random(uint8_t *rand, int bytes);
+int fdt_fixup_kaslr(void *fdt);
+#ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI
+unsigned int sec_firmware_support_psci_version(void);
+unsigned int _sec_firmware_support_psci_version(void);
+#else
+static inline unsigned int sec_firmware_support_psci_version(void)
+{
+	return PSCI_INVALID_VER;
+}
+#endif
+
+static inline unsigned int sec_firmware_used_jobring_offset(void)
+{
+	return SEC_JR3_OFFSET;
+}
+
+#endif /* __SEC_FIRMWARE_H_ */
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
new file mode 100644
index 0000000..b146918
--- /dev/null
+++ b/arch/arm/include/asm/assembler.h
@@ -0,0 +1,84 @@
+/*
+ *  arch/arm/include/asm/assembler.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This file contains arm architecture specific defines
+ *  for the different processors.
+ *
+ *  Do not include any C declarations in this file - it is included by
+ *  assembler source.
+ */
+
+#include <config.h>
+#include <asm/unified.h>
+
+/*
+ * Endian independent macros for shifting bytes within registers.
+ */
+#ifndef __ARMEB__
+#define lspull		lsr
+#define lspush		lsl
+#define get_byte_0	lsl #0
+#define get_byte_1	lsr #8
+#define get_byte_2	lsr #16
+#define get_byte_3	lsr #24
+#define put_byte_0	lsl #0
+#define put_byte_1	lsl #8
+#define put_byte_2	lsl #16
+#define put_byte_3	lsl #24
+#else
+#define lspull		lsl
+#define lspush		lsr
+#define get_byte_0	lsr #24
+#define get_byte_1	lsr #16
+#define get_byte_2	lsr #8
+#define get_byte_3      lsl #0
+#define put_byte_0	lsl #24
+#define put_byte_1	lsl #16
+#define put_byte_2	lsl #8
+#define put_byte_3      lsl #0
+#endif
+
+/*
+ * Data preload for architectures that support it
+ */
+#if defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) || \
+	defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || \
+	defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || \
+	defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_7A__) || \
+	defined(__ARM_ARCH_7R__)
+#define PLD(code...)	code
+#else
+#define PLD(code...)
+#endif
+
+/*
+ * We only support cores that support at least Thumb-1 and thus we use
+ * 'bx lr'
+ */
+	.irp	c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
+	.macro	ret\c, reg
+	.ifeqs	"\reg", "lr"
+	bx\c	\reg
+	.else
+	mov\c	pc, \reg
+	.endif
+	.endm
+	.endr
+
+/*
+ * Cache aligned, used for optimized memcpy/memset
+ * In the kernel this is only enabled for Feroceon CPU's...
+ * We disable it especially for Thumb builds since those instructions
+ * are not made in a Thumb ready way...
+ */
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+#define CALGN(code...)
+#else
+#define CALGN(code...) code
+#endif
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
new file mode 100644
index 0000000..5822b0a
--- /dev/null
+++ b/arch/arm/include/asm/atomic.h
@@ -0,0 +1,32 @@
+/*
+ *  linux/include/asm-arm/atomic.h
+ *
+ *  Copyright (c) 1996 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   13-04-1997	RMK	Made functions atomic!
+ *   07-12-1997	RMK	Upgraded for v2.1.
+ *   26-08-1998	PJB	Added #ifdef __KERNEL__
+ */
+#ifndef __ASM_ARM_ATOMIC_H
+#define __ASM_ARM_ATOMIC_H
+
+#ifdef CONFIG_SMP
+#error SMP not supported
+#endif
+
+#include <asm/proc-armv/system.h>
+#include <asm-generic/atomic.h>
+
+/* Atomic operations are already serializing on ARM */
+#define smp_mb__before_atomic_dec()	barrier()
+#define smp_mb__after_atomic_dec()	barrier()
+#define smp_mb__before_atomic_inc()	barrier()
+#define smp_mb__after_atomic_inc()	barrier()
+
+#endif
diff --git a/arch/arm/include/asm/barriers.h b/arch/arm/include/asm/barriers.h
new file mode 100644
index 0000000..75b9eb4
--- /dev/null
+++ b/arch/arm/include/asm/barriers.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ *
+ * ARM and ARM64 barrier instructions
+ * split from armv7.h to allow sharing between ARM and ARM64
+ *
+ * Original copyright in armv7.h was:
+ * (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com>
+ *
+ * Much of the original barrier code was contributed by:
+ *   Valentine Barshak <valentine.barshak@cogentembedded.com>
+ */
+#ifndef __BARRIERS_H__
+#define __BARRIERS_H__
+
+#ifndef __ASSEMBLY__
+
+#ifndef CONFIG_ARM64
+/*
+ * CP15 Barrier instructions
+ * Please note that we have separate barrier instructions in ARMv7
+ * However, we use the CP15 based instructtions because we use
+ * -march=armv5 in U-Boot
+ */
+#define CP15ISB	asm volatile ("mcr     p15, 0, %0, c7, c5, 4" : : "r" (0))
+#define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
+#define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
+
+#endif /* !CONFIG_ARM64 */
+
+#if __LINUX_ARM_ARCH__ >= 7
+#define ISB	asm volatile ("isb sy" : : : "memory")
+#define DSB	asm volatile ("dsb sy" : : : "memory")
+#define DMB	asm volatile ("dmb sy" : : : "memory")
+#elif __LINUX_ARM_ARCH__ == 6
+#define ISB	CP15ISB
+#define DSB	CP15DSB
+#define DMB	CP15DMB
+#else
+#define ISB	asm volatile ("" : : : "memory")
+#define DSB	CP15DSB
+#define DMB	asm volatile ("" : : : "memory")
+#endif
+
+#define isb()	ISB
+#define dsb()	DSB
+#define dmb()	DMB
+#endif	/* __ASSEMBLY__ */
+#endif	/* __BARRIERS_H__ */
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
new file mode 100644
index 0000000..b02c454
--- /dev/null
+++ b/arch/arm/include/asm/bitops.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_ARM_BITOPS_H
+#define __ASM_ARM_BITOPS_H
+
+#include <asm-generic/bitops/__ffs.h>
+
+#ifdef __KERNEL__
+
+#include <asm/proc-armv/system.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, volatile void * addr);
+
+extern void clear_bit(int nr, volatile void * addr);
+
+extern void change_bit(int nr, volatile void * addr);
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p ^= mask;
+}
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old | mask;
+	return (old & mask) != 0;
+}
+
+static inline int test_and_set_bit(int nr, volatile void * addr)
+{
+	unsigned long flags = 0;
+	int out;
+
+	local_irq_save(flags);
+	out = __test_and_set_bit(nr, addr);
+	local_irq_restore(flags);
+
+	return out;
+}
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old & ~mask;
+	return (old & mask) != 0;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+	unsigned long flags = 0;
+	int out;
+
+	local_irq_save(flags);
+	out = __test_and_clear_bit(nr, addr);
+	local_irq_restore(flags);
+
+	return out;
+}
+
+extern int test_and_change_bit(int nr, volatile void * addr);
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old ^ mask;
+	return (old & mask) != 0;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void * addr)
+{
+    return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+static inline int __ilog2(unsigned int x)
+{
+	return generic_fls(x) - 1;
+}
+
+#define ffz(x)  __ffs(~(x))
+
+static inline int find_next_zero_bit(void *addr, int size, int offset)
+{
+	unsigned long *p = ((unsigned long *)addr) + (offset / BITS_PER_LONG);
+	unsigned long result = offset & ~(BITS_PER_LONG - 1);
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= (BITS_PER_LONG - 1);
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (BITS_PER_LONG - offset);
+		if (size < BITS_PER_LONG)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= BITS_PER_LONG;
+		result += BITS_PER_LONG;
+	}
+	while (size & ~(BITS_PER_LONG - 1)) {
+		tmp = *(p++);
+		if (~tmp)
+			goto found_middle;
+		result += BITS_PER_LONG;
+		size -= BITS_PER_LONG;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	tmp |= ~0UL << size;
+found_middle:
+	return result + ffz(tmp);
+}
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr,addr)	test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr)		set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr)	test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr)		test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size)	find_first_zero_bit(addr,size)
+
+#endif /* __KERNEL__ */
+
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/fls64.h>
+
+#endif /* _ARM_BITOPS_H */
diff --git a/arch/arm/include/asm/boot0-linux-kernel-header.h b/arch/arm/include/asm/boot0-linux-kernel-header.h
new file mode 100644
index 0000000..c6cd76f
--- /dev/null
+++ b/arch/arm/include/asm/boot0-linux-kernel-header.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2017 NVIDIA Corporation <www.nvidia.com>
+ *
+ * Derived from Linux kernel v4.14 files:
+ *
+ * arch/arm64/include/asm/assembler.h:
+ * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S
+ * Copyright (C) 1996-2000 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * arch/arm64/kernel/head.S:
+ * Based on arch/arm/kernel/head.S
+ * Copyright (C) 1994-2002 Russell King
+ * Copyright (C) 2003-2012 ARM Ltd.
+ * Authors:	Catalin Marinas <catalin.marinas@arm.com>
+ *		Will Deacon <will.deacon@arm.com>
+ *
+ * arch/arm64/kernel/image.h:
+ * Copyright (C) 2014 ARM Ltd.
+ */
+
+	/*
+	 * Emit a 64-bit absolute little endian symbol reference in a way that
+	 * ensures that it will be resolved at build time, even when building a
+	 * PIE binary. This requires cooperation from the linker script, which
+	 * must emit the lo32/hi32 halves individually.
+	 */
+	.macro	le64sym, sym
+	.long	\sym\()_lo32
+	.long	\sym\()_hi32
+	.endm
+
+.globl _start
+_start:
+	/*
+	 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
+	 */
+	b	reset				/* branch to kernel start, magic */
+	.long	0				/* reserved */
+	le64sym	_kernel_offset_le		/* Image load offset from start of RAM, little-endian */
+	le64sym	_kernel_size_le			/* Effective size of kernel image, little-endian */
+	le64sym	_kernel_flags_le		/* Informative flags, little-endian */
+	.quad	0				/* reserved */
+	.quad	0				/* reserved */
+	.quad	0				/* reserved */
+	.ascii	"ARM\x64"			/* Magic number */
+	.long	0				/* reserved */
diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h
new file mode 100644
index 0000000..a2131ca
--- /dev/null
+++ b/arch/arm/include/asm/bootm.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ */
+#ifndef ARM_BOOTM_H
+#define ARM_BOOTM_H
+
+extern void udc_disconnect(void);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+		defined(CONFIG_CMDLINE_TAG) || \
+		defined(CONFIG_INITRD_TAG) || \
+		defined(CONFIG_SERIAL_TAG) || \
+		defined(CONFIG_REVISION_TAG)
+# define BOOTM_ENABLE_TAGS		1
+#else
+# define BOOTM_ENABLE_TAGS		0
+#endif
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+# define BOOTM_ENABLE_MEMORY_TAGS	1
+#else
+# define BOOTM_ENABLE_MEMORY_TAGS	0
+#endif
+
+#ifdef CONFIG_CMDLINE_TAG
+ #define BOOTM_ENABLE_CMDLINE_TAG	1
+#else
+ #define BOOTM_ENABLE_CMDLINE_TAG	0
+#endif
+
+#ifdef CONFIG_INITRD_TAG
+ #define BOOTM_ENABLE_INITRD_TAG	1
+#else
+ #define BOOTM_ENABLE_INITRD_TAG	0
+#endif
+
+struct tag_serialnr;
+#ifdef CONFIG_SERIAL_TAG
+ #define BOOTM_ENABLE_SERIAL_TAG	1
+void get_board_serial(struct tag_serialnr *serialnr);
+#else
+ #define BOOTM_ENABLE_SERIAL_TAG	0
+static inline void get_board_serial(struct tag_serialnr *serialnr)
+{
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+ #define BOOTM_ENABLE_REVISION_TAG	1
+u32 get_board_rev(void);
+#else
+ #define BOOTM_ENABLE_REVISION_TAG	0
+static inline u32 get_board_rev(void)
+{
+	return 0;
+}
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/byteorder.h b/arch/arm/include/asm/byteorder.h
new file mode 100644
index 0000000..20cce76
--- /dev/null
+++ b/arch/arm/include/asm/byteorder.h
@@ -0,0 +1,32 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+#ifndef __ASM_ARM_BYTEORDER_H
+#define __ASM_ARM_BYTEORDER_H
+
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#if defined(__ARMEB__) || defined(__AARCH64EB__)
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
new file mode 100644
index 0000000..950ec1e
--- /dev/null
+++ b/arch/arm/include/asm/cache.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+#include <asm/system.h>
+
+#ifndef CONFIG_ARM64
+
+/*
+ * Invalidate L2 Cache using co-proc instruction
+ */
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+void invalidate_l2_cache(void);
+#else
+static inline void invalidate_l2_cache(void)
+{
+	unsigned int val=0;
+
+	asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
+		: : "r" (val) : "cc");
+	isb();
+}
+#endif
+
+int check_cache_range(unsigned long start, unsigned long stop);
+
+void l2_cache_enable(void);
+void l2_cache_disable(void);
+void set_section_dcache(int section, enum dcache_option option);
+
+void arm_init_before_mmu(void);
+void arm_init_domains(void);
+void cpu_cache_initialization(void);
+void dram_bank_mmu_setup(int bank);
+
+#endif
+
+/*
+ * The value of the largest data cache relevant to DMA operations shall be set
+ * for us in CONFIG_SYS_CACHELINE_SIZE.  In some cases this may be a larger
+ * value than found in the L1 cache but this is OK to use in terms of
+ * alignment.
+ */
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
new file mode 100644
index 0000000..bf692ce
--- /dev/null
+++ b/arch/arm/include/asm/config.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#if defined(CONFIG_ARCH_LS1021A) || \
+	defined(CONFIG_CPU_PXA27X) || \
+	defined(CONFIG_CPU_MONAHANS) || \
+	defined(CONFIG_CPU_PXA25X) || \
+	defined(CONFIG_FSL_LAYERSCAPE)
+#include <asm/arch/config.h>
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/davinci_rtc.h b/arch/arm/include/asm/davinci_rtc.h
new file mode 100644
index 0000000..7894bd9
--- /dev/null
+++ b/arch/arm/include/asm/davinci_rtc.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * -------------------------------------------------------------------------
+ *
+ *  linux/include/asm-arm/arch-davinci/hardware.h
+ *
+ *  Copyright (C) 2006 Texas Instruments.
+ */
+#ifndef __ASM_DAVINCI_RTC_H
+#define __ASM_DAVINCI_RTC_H
+
+struct davinci_rtc {
+	unsigned int	second;
+	unsigned int	minutes;
+	unsigned int	hours;
+	unsigned int	day;
+	unsigned int	month; /* 0x10 */
+	unsigned int	year;
+	unsigned int	dotw;
+	unsigned int	resv1;
+	unsigned int	alarmsecond; /* 0x20 */
+	unsigned int	alarmminute;
+	unsigned int	alarmhour;
+	unsigned int	alarmday;
+	unsigned int	alarmmonth; /* 0x30 */
+	unsigned int	alarmyear;
+	unsigned int	resv2[2];
+	unsigned int	ctrl; /* 0x40 */
+	unsigned int	status;
+	unsigned int	irq;
+	unsigned int	complsb;
+	unsigned int	compmsb; /* 0x50 */
+	unsigned int	osc;
+	unsigned int	resv3[2];
+	unsigned int	scratch0; /* 0x60 */
+	unsigned int	scratch1;
+	unsigned int	scratch2;
+	unsigned int	kick0r;
+	unsigned int	kick1r; /* 0x70 */
+};
+
+#define RTC_STATE_BUSY	0x01
+#define RTC_STATE_RUN	0x02
+
+#define RTC_KICK0R_WE	0x83e70b13
+#define RTC_KICK1R_WE	0x95a4f1e0
+#endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
new file mode 100644
index 0000000..fc5b8f6
--- /dev/null
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+#ifndef __ASM_ARM_DMA_MAPPING_H
+#define __ASM_ARM_DMA_MAPPING_H
+
+#include <linux/dma-direction.h>
+
+#define	dma_mapping_error(x, y)	0
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN));
+	return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+	free(addr);
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+					   enum dma_data_direction dir)
+{
+	return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+				    unsigned long paddr)
+{
+}
+
+#endif /* __ASM_ARM_DMA_MAPPING_H */
diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h
new file mode 100644
index 0000000..1549f7b
--- /dev/null
+++ b/arch/arm/include/asm/ehci-omap.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * OMAP EHCI port support
+ * Based on LINUX KERNEL
+ * drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com*
+ * Author: Govindraj R <govindraj.raja@ti.com>
+ */
+
+#ifndef _OMAP_COMMON_EHCI_H_
+#define _OMAP_COMMON_EHCI_H_
+
+enum usbhs_omap_port_mode {
+	OMAP_USBHS_PORT_MODE_UNUSED,
+	OMAP_EHCI_PORT_MODE_PHY,
+	OMAP_EHCI_PORT_MODE_TLL,
+	OMAP_EHCI_PORT_MODE_HSIC,
+};
+
+#define OMAP_HS_USB_PORTS	3
+
+#define is_ehci_phy_mode(x)	((x) == OMAP_EHCI_PORT_MODE_PHY)
+#define is_ehci_tll_mode(x)	((x) == OMAP_EHCI_PORT_MODE_TLL)
+#define is_ehci_hsic_mode(x)	((x) == OMAP_EHCI_PORT_MODE_HSIC)
+
+/* Values of UHH_REVISION - Note: these are not given in the TRM */
+#define OMAP_USBHS_REV1					0x00000010 /* OMAP3 */
+#define OMAP_USBHS_REV2					0x50700100 /* OMAP4 */
+#define OMAP_USBHS_REV2_1				0x50700101 /* OMAP5 */
+
+/* UHH Register Set */
+#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN		(1 << 2)
+#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN		(1 << 3)
+#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN		(1 << 4)
+#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN		(1 << 5)
+
+#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS		1
+#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS		(1 << 11)
+#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS		(1 << 12)
+#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK		(1 << 31)
+
+#define OMAP_P1_MODE_CLEAR				(3 << 16)
+#define OMAP_P1_MODE_TLL				(1 << 16)
+#define OMAP_P1_MODE_HSIC				(3 << 16)
+#define OMAP_P2_MODE_CLEAR				(3 << 18)
+#define OMAP_P2_MODE_TLL				(1 << 18)
+#define OMAP_P2_MODE_HSIC				(3 << 18)
+#define OMAP_P3_MODE_CLEAR				(3 << 20)
+#define OMAP_P3_MODE_HSIC				(3 << 20)
+
+/* EHCI Register Set */
+#define EHCI_INSNREG04_DISABLE_UNSUSPEND		(1 << 5)
+#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT		31
+#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT		24
+#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT			22
+#define EHCI_INSNREG05_ULPI_REGADD_SHIFT		16
+
+#define OMAP_REV1_TLL_CHANNEL_COUNT			3
+#define OMAP_REV2_TLL_CHANNEL_COUNT			2
+
+/* TLL Register Set */
+#define OMAP_TLL_CHANNEL_CONF(num)			(0x004 * num)
+#define OMAP_TLL_CHANNEL_CONF_DRVVBUS			(1 << 16)
+#define OMAP_TLL_CHANNEL_CONF_CHRGVBUS			(1 << 15)
+#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF		(1 << 11)
+#define OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI	(2 << 1)
+#define OMAP_TLL_CHANNEL_CONF_CHANEN			1
+
+struct omap_usbhs_board_data {
+	enum usbhs_omap_port_mode port_mode[OMAP_HS_USB_PORTS];
+};
+
+struct omap_usbtll {
+	u32 rev;		/* 0x00 */
+	u32 hwinfo;		/* 0x04 */
+	u8 reserved1[0x8];
+	u32 sysc;		/* 0x10 */
+	u32 syss;		/* 0x14 */
+	u32 irqst;		/* 0x18 */
+	u32 irqen;		/* 0x1c */
+	u8 reserved2[0x10];
+	u32 shared_conf;	/* 0x30 */
+	u8 reserved3[0xc];
+	u32 channel_conf;	/* 0x40 */
+};
+
+struct omap_uhh {
+	u32 rev;	/* 0x00 */
+	u32 hwinfo;	/* 0x04 */
+	u8 reserved1[0x8];
+	u32 sysc;	/* 0x10 */
+	u32 syss;	/* 0x14 */
+	u8 reserved2[0x28];
+	u32 hostconfig;	/* 0x40 */
+	u32 debugcsr;	/* 0x44 */
+};
+
+struct omap_ehci {
+	u32 hccapbase;		/* 0x00 */
+	u32 hcsparams;		/* 0x04 */
+	u32 hccparams;		/* 0x08 */
+	u8 reserved1[0x04];
+	u32 usbcmd;		/* 0x10 */
+	u32 usbsts;		/* 0x14 */
+	u32 usbintr;		/* 0x18 */
+	u32 frindex;		/* 0x1c */
+	u32 ctrldssegment;	/* 0x20 */
+	u32 periodiclistbase;	/* 0x24 */
+	u32 asysnclistaddr;	/* 0x28 */
+	u8 reserved2[0x24];
+	u32 configflag;		/* 0x50 */
+	u32 portsc_i;		/* 0x54 */
+	u8 reserved3[0x38];
+	u32 insreg00;		/* 0x90 */
+	u32 insreg01;		/* 0x94 */
+	u32 insreg02;		/* 0x98 */
+	u32 insreg03;		/* 0x9c */
+	u32 insreg04;		/* 0xa0 */
+	u32 insreg05_utmi_ulpi;	/* 0xa4 */
+	u32 insreg06;		/* 0xa8 */
+	u32 insreg07;		/* 0xac */
+	u32 insreg08;		/* 0xb0 */
+};
+
+/*
+ * FIXME: forward declaration of this structs needed because omap got the
+ * ehci implementation backwards. move out ehci_hcd_x from board files
+ */
+struct ehci_hccr;
+struct ehci_hcor;
+
+int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
+		       struct ehci_hccr **hccr, struct ehci_hcor **hcor);
+int omap_ehci_hcd_stop(void);
+
+#endif /* _OMAP_COMMON_EHCI_H_ */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
new file mode 100644
index 0000000..dc398ef
--- /dev/null
+++ b/arch/arm/include/asm/emif.h
@@ -0,0 +1,1304 @@
+/*
+ * OMAP44xx EMIF header
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+#include <asm/types.h>
+#include <common.h>
+#include <asm/io.h>
+
+/* Base address */
+#ifndef EMIF1_BASE
+#define EMIF1_BASE				0x4c000000
+#endif
+#define EMIF2_BASE				0x4d000000
+
+#define EMIF_4D					0x4
+#define EMIF_4D5				0x5
+
+/* Registers shifts, masks and values */
+
+/* EMIF_MOD_ID_REV */
+#define EMIF_REG_SCHEME_SHIFT			30
+#define EMIF_REG_SCHEME_MASK			(0x3 << 30)
+#define EMIF_REG_MODULE_ID_SHIFT			16
+#define EMIF_REG_MODULE_ID_MASK			(0xfff << 16)
+#define EMIF_REG_RTL_VERSION_SHIFT			11
+#define EMIF_REG_RTL_VERSION_MASK			(0x1f << 11)
+#define EMIF_REG_MAJOR_REVISION_SHIFT		8
+#define EMIF_REG_MAJOR_REVISION_MASK		(0x7 << 8)
+#define EMIF_REG_MINOR_REVISION_SHIFT		0
+#define EMIF_REG_MINOR_REVISION_MASK		(0x3f << 0)
+
+/* STATUS */
+#define EMIF_REG_BE_SHIFT				31
+#define EMIF_REG_BE_MASK				(1 << 31)
+#define EMIF_REG_DUAL_CLK_MODE_SHIFT		30
+#define EMIF_REG_DUAL_CLK_MODE_MASK			(1 << 30)
+#define EMIF_REG_FAST_INIT_SHIFT			29
+#define EMIF_REG_FAST_INIT_MASK			(1 << 29)
+#define EMIF_REG_LEVLING_TO_SHIFT		4
+#define EMIF_REG_LEVELING_TO_MASK		(7 << 4)
+#define EMIF_REG_PHY_DLL_READY_SHIFT		2
+#define EMIF_REG_PHY_DLL_READY_MASK			(1 << 2)
+
+/* SDRAM_CONFIG */
+#define EMIF_REG_SDRAM_TYPE_SHIFT			29
+#define EMIF_REG_SDRAM_TYPE_MASK			(0x7 << 29)
+#define EMIF_REG_SDRAM_TYPE_DDR1			0
+#define EMIF_REG_SDRAM_TYPE_LPDDR1			1
+#define EMIF_REG_SDRAM_TYPE_DDR2			2
+#define EMIF_REG_SDRAM_TYPE_DDR3			3
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S4			4
+#define EMIF_REG_SDRAM_TYPE_LPDDR2_S2			5
+#define EMIF_REG_IBANK_POS_SHIFT			27
+#define EMIF_REG_IBANK_POS_MASK			(0x3 << 27)
+#define EMIF_REG_DDR_TERM_SHIFT			24
+#define EMIF_REG_DDR_TERM_MASK			(0x7 << 24)
+#define EMIF_REG_DDR2_DDQS_SHIFT			23
+#define EMIF_REG_DDR2_DDQS_MASK			(1 << 23)
+#define EMIF_REG_DYN_ODT_SHIFT			21
+#define EMIF_REG_DYN_ODT_MASK			(0x3 << 21)
+#define EMIF_REG_DDR_DISABLE_DLL_SHIFT		20
+#define EMIF_REG_DDR_DISABLE_DLL_MASK		(1 << 20)
+#define EMIF_REG_SDRAM_DRIVE_SHIFT			18
+#define EMIF_REG_SDRAM_DRIVE_MASK			(0x3 << 18)
+#define EMIF_REG_CWL_SHIFT				16
+#define EMIF_REG_CWL_MASK				(0x3 << 16)
+#define EMIF_REG_NARROW_MODE_SHIFT			14
+#define EMIF_REG_NARROW_MODE_MASK			(0x3 << 14)
+#define EMIF_REG_CL_SHIFT				10
+#define EMIF_REG_CL_MASK				(0xf << 10)
+#define EMIF_REG_ROWSIZE_SHIFT			7
+#define EMIF_REG_ROWSIZE_MASK			(0x7 << 7)
+#define EMIF_REG_IBANK_SHIFT			4
+#define EMIF_REG_IBANK_MASK				(0x7 << 4)
+#define EMIF_REG_EBANK_SHIFT			3
+#define EMIF_REG_EBANK_MASK				(1 << 3)
+#define EMIF_REG_PAGESIZE_SHIFT			0
+#define EMIF_REG_PAGESIZE_MASK			(0x7 << 0)
+
+/* SDRAM_CONFIG_2 */
+#define EMIF_REG_CS1NVMEN_SHIFT			30
+#define EMIF_REG_CS1NVMEN_MASK			(1 << 30)
+#define EMIF_REG_EBANK_POS_SHIFT			27
+#define EMIF_REG_EBANK_POS_MASK			(1 << 27)
+#define EMIF_REG_RDBNUM_SHIFT			4
+#define EMIF_REG_RDBNUM_MASK			(0x3 << 4)
+#define EMIF_REG_RDBSIZE_SHIFT			0
+#define EMIF_REG_RDBSIZE_MASK			(0x7 << 0)
+
+/* SDRAM_REF_CTRL */
+#define EMIF_REG_INITREF_DIS_SHIFT			31
+#define EMIF_REG_INITREF_DIS_MASK			(1 << 31)
+#define EMIF_REG_SRT_SHIFT				29
+#define EMIF_REG_SRT_MASK				(1 << 29)
+#define EMIF_REG_ASR_SHIFT				28
+#define EMIF_REG_ASR_MASK				(1 << 28)
+#define EMIF_REG_PASR_SHIFT				24
+#define EMIF_REG_PASR_MASK				(0x7 << 24)
+#define EMIF_REG_REFRESH_RATE_SHIFT			0
+#define EMIF_REG_REFRESH_RATE_MASK			(0xffff << 0)
+
+/* SDRAM_REF_CTRL_SHDW */
+#define EMIF_REG_REFRESH_RATE_SHDW_SHIFT		0
+#define EMIF_REG_REFRESH_RATE_SHDW_MASK		(0xffff << 0)
+
+/* SDRAM_TIM_1 */
+#define EMIF_REG_T_RP_SHIFT				25
+#define EMIF_REG_T_RP_MASK				(0xf << 25)
+#define EMIF_REG_T_RCD_SHIFT			21
+#define EMIF_REG_T_RCD_MASK				(0xf << 21)
+#define EMIF_REG_T_WR_SHIFT				17
+#define EMIF_REG_T_WR_MASK				(0xf << 17)
+#define EMIF_REG_T_RAS_SHIFT			12
+#define EMIF_REG_T_RAS_MASK				(0x1f << 12)
+#define EMIF_REG_T_RC_SHIFT				6
+#define EMIF_REG_T_RC_MASK				(0x3f << 6)
+#define EMIF_REG_T_RRD_SHIFT			3
+#define EMIF_REG_T_RRD_MASK				(0x7 << 3)
+#define EMIF_REG_T_WTR_SHIFT			0
+#define EMIF_REG_T_WTR_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_1_SHDW */
+#define EMIF_REG_T_RP_SHDW_SHIFT			25
+#define EMIF_REG_T_RP_SHDW_MASK			(0xf << 25)
+#define EMIF_REG_T_RCD_SHDW_SHIFT			21
+#define EMIF_REG_T_RCD_SHDW_MASK			(0xf << 21)
+#define EMIF_REG_T_WR_SHDW_SHIFT			17
+#define EMIF_REG_T_WR_SHDW_MASK			(0xf << 17)
+#define EMIF_REG_T_RAS_SHDW_SHIFT			12
+#define EMIF_REG_T_RAS_SHDW_MASK			(0x1f << 12)
+#define EMIF_REG_T_RC_SHDW_SHIFT			6
+#define EMIF_REG_T_RC_SHDW_MASK			(0x3f << 6)
+#define EMIF_REG_T_RRD_SHDW_SHIFT			3
+#define EMIF_REG_T_RRD_SHDW_MASK			(0x7 << 3)
+#define EMIF_REG_T_WTR_SHDW_SHIFT			0
+#define EMIF_REG_T_WTR_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_2 */
+#define EMIF_REG_T_XP_SHIFT				28
+#define EMIF_REG_T_XP_MASK				(0x7 << 28)
+#define EMIF_REG_T_ODT_SHIFT			25
+#define EMIF_REG_T_ODT_MASK				(0x7 << 25)
+#define EMIF_REG_T_XSNR_SHIFT			16
+#define EMIF_REG_T_XSNR_MASK			(0x1ff << 16)
+#define EMIF_REG_T_XSRD_SHIFT			6
+#define EMIF_REG_T_XSRD_MASK			(0x3ff << 6)
+#define EMIF_REG_T_RTP_SHIFT			3
+#define EMIF_REG_T_RTP_MASK				(0x7 << 3)
+#define EMIF_REG_T_CKE_SHIFT			0
+#define EMIF_REG_T_CKE_MASK				(0x7 << 0)
+
+/* SDRAM_TIM_2_SHDW */
+#define EMIF_REG_T_XP_SHDW_SHIFT			28
+#define EMIF_REG_T_XP_SHDW_MASK			(0x7 << 28)
+#define EMIF_REG_T_ODT_SHDW_SHIFT			25
+#define EMIF_REG_T_ODT_SHDW_MASK			(0x7 << 25)
+#define EMIF_REG_T_XSNR_SHDW_SHIFT			16
+#define EMIF_REG_T_XSNR_SHDW_MASK			(0x1ff << 16)
+#define EMIF_REG_T_XSRD_SHDW_SHIFT			6
+#define EMIF_REG_T_XSRD_SHDW_MASK			(0x3ff << 6)
+#define EMIF_REG_T_RTP_SHDW_SHIFT			3
+#define EMIF_REG_T_RTP_SHDW_MASK			(0x7 << 3)
+#define EMIF_REG_T_CKE_SHDW_SHIFT			0
+#define EMIF_REG_T_CKE_SHDW_MASK			(0x7 << 0)
+
+/* SDRAM_TIM_3 */
+#define EMIF_REG_T_CKESR_SHIFT			21
+#define EMIF_REG_T_CKESR_MASK			(0x7 << 21)
+#define EMIF_REG_ZQ_ZQCS_SHIFT			15
+#define EMIF_REG_ZQ_ZQCS_MASK			(0x3f << 15)
+#define EMIF_REG_T_TDQSCKMAX_SHIFT			13
+#define EMIF_REG_T_TDQSCKMAX_MASK			(0x3 << 13)
+#define EMIF_REG_T_RFC_SHIFT			4
+#define EMIF_REG_T_RFC_MASK				(0x1ff << 4)
+#define EMIF_REG_T_RAS_MAX_SHIFT			0
+#define EMIF_REG_T_RAS_MAX_MASK			(0xf << 0)
+
+/* SDRAM_TIM_3_SHDW */
+#define EMIF_REG_T_CKESR_SHDW_SHIFT			21
+#define EMIF_REG_T_CKESR_SHDW_MASK			(0x7 << 21)
+#define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT			15
+#define EMIF_REG_ZQ_ZQCS_SHDW_MASK			(0x3f << 15)
+#define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT		13
+#define EMIF_REG_T_TDQSCKMAX_SHDW_MASK		(0x3 << 13)
+#define EMIF_REG_T_RFC_SHDW_SHIFT			4
+#define EMIF_REG_T_RFC_SHDW_MASK			(0x1ff << 4)
+#define EMIF_REG_T_RAS_MAX_SHDW_SHIFT		0
+#define EMIF_REG_T_RAS_MAX_SHDW_MASK		(0xf << 0)
+
+/* LPDDR2_NVM_TIM */
+#define EMIF_REG_NVM_T_XP_SHIFT			28
+#define EMIF_REG_NVM_T_XP_MASK			(0x7 << 28)
+#define EMIF_REG_NVM_T_WTR_SHIFT			24
+#define EMIF_REG_NVM_T_WTR_MASK			(0x7 << 24)
+#define EMIF_REG_NVM_T_RP_SHIFT			20
+#define EMIF_REG_NVM_T_RP_MASK			(0xf << 20)
+#define EMIF_REG_NVM_T_WRA_SHIFT			16
+#define EMIF_REG_NVM_T_WRA_MASK			(0xf << 16)
+#define EMIF_REG_NVM_T_RRD_SHIFT			8
+#define EMIF_REG_NVM_T_RRD_MASK			(0xff << 8)
+#define EMIF_REG_NVM_T_RCDMIN_SHIFT			0
+#define EMIF_REG_NVM_T_RCDMIN_MASK			(0xff << 0)
+
+/* LPDDR2_NVM_TIM_SHDW */
+#define EMIF_REG_NVM_T_XP_SHDW_SHIFT		28
+#define EMIF_REG_NVM_T_XP_SHDW_MASK			(0x7 << 28)
+#define EMIF_REG_NVM_T_WTR_SHDW_SHIFT		24
+#define EMIF_REG_NVM_T_WTR_SHDW_MASK		(0x7 << 24)
+#define EMIF_REG_NVM_T_RP_SHDW_SHIFT		20
+#define EMIF_REG_NVM_T_RP_SHDW_MASK			(0xf << 20)
+#define EMIF_REG_NVM_T_WRA_SHDW_SHIFT		16
+#define EMIF_REG_NVM_T_WRA_SHDW_MASK		(0xf << 16)
+#define EMIF_REG_NVM_T_RRD_SHDW_SHIFT		8
+#define EMIF_REG_NVM_T_RRD_SHDW_MASK		(0xff << 8)
+#define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT		0
+#define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK		(0xff << 0)
+
+/* PWR_MGMT_CTRL */
+#define EMIF_REG_IDLEMODE_SHIFT			30
+#define EMIF_REG_IDLEMODE_MASK			(0x3 << 30)
+#define EMIF_REG_PD_TIM_SHIFT			12
+#define EMIF_REG_PD_TIM_MASK			(0xf << 12)
+#define EMIF_REG_DPD_EN_SHIFT			11
+#define EMIF_REG_DPD_EN_MASK			(1 << 11)
+#define EMIF_REG_LP_MODE_SHIFT			8
+#define EMIF_REG_LP_MODE_MASK			(0x7 << 8)
+#define EMIF_REG_SR_TIM_SHIFT			4
+#define EMIF_REG_SR_TIM_MASK			(0xf << 4)
+#define EMIF_REG_CS_TIM_SHIFT			0
+#define EMIF_REG_CS_TIM_MASK			(0xf << 0)
+
+/* PWR_MGMT_CTRL_SHDW */
+#define EMIF_REG_PD_TIM_SHDW_SHIFT			12
+#define EMIF_REG_PD_TIM_SHDW_MASK			(0xf << 12)
+#define EMIF_REG_SR_TIM_SHDW_SHIFT			4
+#define EMIF_REG_SR_TIM_SHDW_MASK			(0xf << 4)
+#define EMIF_REG_CS_TIM_SHDW_SHIFT			0
+#define EMIF_REG_CS_TIM_SHDW_MASK			(0xf << 0)
+
+/* LPDDR2_MODE_REG_DATA */
+#define EMIF_REG_VALUE_0_SHIFT			0
+#define EMIF_REG_VALUE_0_MASK			(0x7f << 0)
+
+/* LPDDR2_MODE_REG_CFG */
+#define EMIF_REG_CS_SHIFT				31
+#define EMIF_REG_CS_MASK				(1 << 31)
+#define EMIF_REG_REFRESH_EN_SHIFT			30
+#define EMIF_REG_REFRESH_EN_MASK			(1 << 30)
+#define EMIF_REG_ADDRESS_SHIFT			0
+#define EMIF_REG_ADDRESS_MASK			(0xff << 0)
+
+/* OCP_CONFIG */
+#define EMIF_REG_SYS_THRESH_MAX_SHIFT		24
+#define EMIF_REG_SYS_THRESH_MAX_MASK		(0xf << 24)
+#define EMIF_REG_MPU_THRESH_MAX_SHIFT		20
+#define EMIF_REG_MPU_THRESH_MAX_MASK		(0xf << 20)
+#define EMIF_REG_LL_THRESH_MAX_SHIFT		16
+#define EMIF_REG_LL_THRESH_MAX_MASK			(0xf << 16)
+#define EMIF_REG_PR_OLD_COUNT_SHIFT			0
+#define EMIF_REG_PR_OLD_COUNT_MASK			(0xff << 0)
+
+/* OCP_CFG_VAL_1 */
+#define EMIF_REG_SYS_BUS_WIDTH_SHIFT		30
+#define EMIF_REG_SYS_BUS_WIDTH_MASK			(0x3 << 30)
+#define EMIF_REG_LL_BUS_WIDTH_SHIFT			28
+#define EMIF_REG_LL_BUS_WIDTH_MASK			(0x3 << 28)
+#define EMIF_REG_WR_FIFO_DEPTH_SHIFT		8
+#define EMIF_REG_WR_FIFO_DEPTH_MASK			(0xff << 8)
+#define EMIF_REG_CMD_FIFO_DEPTH_SHIFT		0
+#define EMIF_REG_CMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* OCP_CFG_VAL_2 */
+#define EMIF_REG_RREG_FIFO_DEPTH_SHIFT		16
+#define EMIF_REG_RREG_FIFO_DEPTH_MASK		(0xff << 16)
+#define EMIF_REG_RSD_FIFO_DEPTH_SHIFT		8
+#define EMIF_REG_RSD_FIFO_DEPTH_MASK		(0xff << 8)
+#define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT		0
+#define EMIF_REG_RCMD_FIFO_DEPTH_MASK		(0xff << 0)
+
+/* IODFT_TLGC */
+#define EMIF_REG_TLEC_SHIFT				16
+#define EMIF_REG_TLEC_MASK				(0xffff << 16)
+#define EMIF_REG_MT_SHIFT				14
+#define EMIF_REG_MT_MASK				(1 << 14)
+#define EMIF_REG_ACT_CAP_EN_SHIFT			13
+#define EMIF_REG_ACT_CAP_EN_MASK			(1 << 13)
+#define EMIF_REG_OPG_LD_SHIFT			12
+#define EMIF_REG_OPG_LD_MASK			(1 << 12)
+#define EMIF_REG_RESET_PHY_SHIFT			10
+#define EMIF_REG_RESET_PHY_MASK			(1 << 10)
+#define EMIF_REG_MMS_SHIFT				8
+#define EMIF_REG_MMS_MASK				(1 << 8)
+#define EMIF_REG_MC_SHIFT				4
+#define EMIF_REG_MC_MASK				(0x3 << 4)
+#define EMIF_REG_PC_SHIFT				1
+#define EMIF_REG_PC_MASK				(0x7 << 1)
+#define EMIF_REG_TM_SHIFT				0
+#define EMIF_REG_TM_MASK				(1 << 0)
+
+/* IODFT_CTRL_MISR_RSLT */
+#define EMIF_REG_DQM_TLMR_SHIFT			16
+#define EMIF_REG_DQM_TLMR_MASK			(0x3ff << 16)
+#define EMIF_REG_CTL_TLMR_SHIFT			0
+#define EMIF_REG_CTL_TLMR_MASK			(0x7ff << 0)
+
+/* IODFT_ADDR_MISR_RSLT */
+#define EMIF_REG_ADDR_TLMR_SHIFT			0
+#define EMIF_REG_ADDR_TLMR_MASK			(0x1fffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_1 */
+#define EMIF_REG_DATA_TLMR_31_0_SHIFT		0
+#define EMIF_REG_DATA_TLMR_31_0_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_2 */
+#define EMIF_REG_DATA_TLMR_63_32_SHIFT		0
+#define EMIF_REG_DATA_TLMR_63_32_MASK		(0xffffffff << 0)
+
+/* IODFT_DATA_MISR_RSLT_3 */
+#define EMIF_REG_DATA_TLMR_66_64_SHIFT		0
+#define EMIF_REG_DATA_TLMR_66_64_MASK		(0x7 << 0)
+
+/* PERF_CNT_1 */
+#define EMIF_REG_COUNTER1_SHIFT			0
+#define EMIF_REG_COUNTER1_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_2 */
+#define EMIF_REG_COUNTER2_SHIFT			0
+#define EMIF_REG_COUNTER2_MASK			(0xffffffff << 0)
+
+/* PERF_CNT_CFG */
+#define EMIF_REG_CNTR2_MCONNID_EN_SHIFT		31
+#define EMIF_REG_CNTR2_MCONNID_EN_MASK		(1 << 31)
+#define EMIF_REG_CNTR2_REGION_EN_SHIFT		30
+#define EMIF_REG_CNTR2_REGION_EN_MASK		(1 << 30)
+#define EMIF_REG_CNTR2_CFG_SHIFT			16
+#define EMIF_REG_CNTR2_CFG_MASK			(0xf << 16)
+#define EMIF_REG_CNTR1_MCONNID_EN_SHIFT		15
+#define EMIF_REG_CNTR1_MCONNID_EN_MASK		(1 << 15)
+#define EMIF_REG_CNTR1_REGION_EN_SHIFT		14
+#define EMIF_REG_CNTR1_REGION_EN_MASK		(1 << 14)
+#define EMIF_REG_CNTR1_CFG_SHIFT			0
+#define EMIF_REG_CNTR1_CFG_MASK			(0xf << 0)
+
+/* PERF_CNT_SEL */
+#define EMIF_REG_MCONNID2_SHIFT			24
+#define EMIF_REG_MCONNID2_MASK			(0xff << 24)
+#define EMIF_REG_REGION_SEL2_SHIFT			16
+#define EMIF_REG_REGION_SEL2_MASK			(0x3 << 16)
+#define EMIF_REG_MCONNID1_SHIFT			8
+#define EMIF_REG_MCONNID1_MASK			(0xff << 8)
+#define EMIF_REG_REGION_SEL1_SHIFT			0
+#define EMIF_REG_REGION_SEL1_MASK			(0x3 << 0)
+
+/* PERF_CNT_TIM */
+#define EMIF_REG_TOTAL_TIME_SHIFT			0
+#define EMIF_REG_TOTAL_TIME_MASK			(0xffffffff << 0)
+
+/* READ_IDLE_CTRL */
+#define EMIF_REG_READ_IDLE_LEN_SHIFT		16
+#define EMIF_REG_READ_IDLE_LEN_MASK			(0xf << 16)
+#define EMIF_REG_READ_IDLE_INTERVAL_SHIFT		0
+#define EMIF_REG_READ_IDLE_INTERVAL_MASK		(0x1ff << 0)
+
+/* READ_IDLE_CTRL_SHDW */
+#define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT		16
+#define EMIF_REG_READ_IDLE_LEN_SHDW_MASK		(0xf << 16)
+#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT	0
+#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK	(0x1ff << 0)
+
+/* IRQ_EOI */
+#define EMIF_REG_EOI_SHIFT				0
+#define EMIF_REG_EOI_MASK				(1 << 0)
+
+/* IRQSTATUS_RAW_SYS */
+#define EMIF_REG_DNV_SYS_SHIFT			2
+#define EMIF_REG_DNV_SYS_MASK			(1 << 2)
+#define EMIF_REG_TA_SYS_SHIFT			1
+#define EMIF_REG_TA_SYS_MASK			(1 << 1)
+#define EMIF_REG_ERR_SYS_SHIFT			0
+#define EMIF_REG_ERR_SYS_MASK			(1 << 0)
+
+/* IRQSTATUS_RAW_LL */
+#define EMIF_REG_DNV_LL_SHIFT			2
+#define EMIF_REG_DNV_LL_MASK			(1 << 2)
+#define EMIF_REG_TA_LL_SHIFT			1
+#define EMIF_REG_TA_LL_MASK				(1 << 1)
+#define EMIF_REG_ERR_LL_SHIFT			0
+#define EMIF_REG_ERR_LL_MASK			(1 << 0)
+
+/* IRQSTATUS_SYS */
+
+/* IRQSTATUS_LL */
+
+/* IRQENABLE_SET_SYS */
+#define EMIF_REG_EN_DNV_SYS_SHIFT			2
+#define EMIF_REG_EN_DNV_SYS_MASK			(1 << 2)
+#define EMIF_REG_EN_TA_SYS_SHIFT			1
+#define EMIF_REG_EN_TA_SYS_MASK			(1 << 1)
+#define EMIF_REG_EN_ERR_SYS_SHIFT			0
+#define EMIF_REG_EN_ERR_SYS_MASK			(1 << 0)
+
+/* IRQENABLE_SET_LL */
+#define EMIF_REG_EN_DNV_LL_SHIFT			2
+#define EMIF_REG_EN_DNV_LL_MASK			(1 << 2)
+#define EMIF_REG_EN_TA_LL_SHIFT			1
+#define EMIF_REG_EN_TA_LL_MASK			(1 << 1)
+#define EMIF_REG_EN_ERR_LL_SHIFT			0
+#define EMIF_REG_EN_ERR_LL_MASK			(1 << 0)
+
+/* IRQENABLE_CLR_SYS */
+
+/* IRQENABLE_CLR_LL */
+
+/* ZQ_CONFIG */
+#define EMIF_REG_ZQ_CS1EN_SHIFT			31
+#define EMIF_REG_ZQ_CS1EN_MASK			(1 << 31)
+#define EMIF_REG_ZQ_CS0EN_SHIFT			30
+#define EMIF_REG_ZQ_CS0EN_MASK			(1 << 30)
+#define EMIF_REG_ZQ_DUALCALEN_SHIFT			29
+#define EMIF_REG_ZQ_DUALCALEN_MASK			(1 << 29)
+#define EMIF_REG_ZQ_SFEXITEN_SHIFT			28
+#define EMIF_REG_ZQ_SFEXITEN_MASK			(1 << 28)
+#define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT		18
+#define EMIF_REG_ZQ_ZQINIT_MULT_MASK		(0x3 << 18)
+#define EMIF_REG_ZQ_ZQCL_MULT_SHIFT			16
+#define EMIF_REG_ZQ_ZQCL_MULT_MASK			(0x3 << 16)
+#define EMIF_REG_ZQ_REFINTERVAL_SHIFT		0
+#define EMIF_REG_ZQ_REFINTERVAL_MASK		(0xffff << 0)
+
+/* TEMP_ALERT_CONFIG */
+#define EMIF_REG_TA_CS1EN_SHIFT			31
+#define EMIF_REG_TA_CS1EN_MASK			(1 << 31)
+#define EMIF_REG_TA_CS0EN_SHIFT			30
+#define EMIF_REG_TA_CS0EN_MASK			(1 << 30)
+#define EMIF_REG_TA_SFEXITEN_SHIFT			28
+#define EMIF_REG_TA_SFEXITEN_MASK			(1 << 28)
+#define EMIF_REG_TA_DEVWDT_SHIFT			26
+#define EMIF_REG_TA_DEVWDT_MASK			(0x3 << 26)
+#define EMIF_REG_TA_DEVCNT_SHIFT			24
+#define EMIF_REG_TA_DEVCNT_MASK			(0x3 << 24)
+#define EMIF_REG_TA_REFINTERVAL_SHIFT		0
+#define EMIF_REG_TA_REFINTERVAL_MASK		(0x3fffff << 0)
+
+/* OCP_ERR_LOG */
+#define EMIF_REG_MADDRSPACE_SHIFT			14
+#define EMIF_REG_MADDRSPACE_MASK			(0x3 << 14)
+#define EMIF_REG_MBURSTSEQ_SHIFT			11
+#define EMIF_REG_MBURSTSEQ_MASK			(0x7 << 11)
+#define EMIF_REG_MCMD_SHIFT				8
+#define EMIF_REG_MCMD_MASK				(0x7 << 8)
+#define EMIF_REG_MCONNID_SHIFT			0
+#define EMIF_REG_MCONNID_MASK			(0xff << 0)
+
+/* DDR_PHY_CTRL_1 */
+#define EMIF_REG_DDR_PHY_CTRL_1_SHIFT		4
+#define EMIF_REG_DDR_PHY_CTRL_1_MASK		(0xfffffff << 4)
+#define EMIF_REG_READ_LATENCY_SHIFT			0
+#define EMIF_REG_READ_LATENCY_MASK			(0xf << 0)
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT		4
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK		(0xFF << 4)
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT	12
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK	(0xFFFFF << 12)
+
+/* DDR_PHY_CTRL_1_SHDW */
+#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT		4
+#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK		(0xfffffff << 4)
+#define EMIF_REG_READ_LATENCY_SHDW_SHIFT		0
+#define EMIF_REG_READ_LATENCY_SHDW_MASK		(0xf << 0)
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT	4
+#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK	(0xFF << 4)
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
+#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK	(0xFFFFF << 12)
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT		25
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK		(1 << 25)
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT	26
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK		(1 << 26)
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT		27
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK		(1 << 27)
+
+/* DDR_PHY_CTRL_2 */
+#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT		0
+#define EMIF_REG_DDR_PHY_CTRL_2_MASK		(0xffffffff << 0)
+
+/*EMIF_READ_WRITE_LEVELING_CONTROL*/
+#define EMIF_REG_RDWRLVLFULL_START_SHIFT	31
+#define EMIF_REG_RDWRLVLFULL_START_MASK		(1 << 31)
+#define EMIF_REG_RDWRLVLINC_PRE_SHIFT		24
+#define EMIF_REG_RDWRLVLINC_PRE_MASK		(0x7F << 24)
+#define EMIF_REG_RDLVLINC_INT_SHIFT		16
+#define EMIF_REG_RDLVLINC_INT_MASK		(0xFF << 16)
+#define EMIF_REG_RDLVLGATEINC_INT_SHIFT		8
+#define EMIF_REG_RDLVLGATEINC_INT_MASK		(0xFF << 8)
+#define EMIF_REG_WRLVLINC_INT_SHIFT		0
+#define EMIF_REG_WRLVLINC_INT_MASK		(0xFF << 0)
+
+/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/
+#define EMIF_REG_RDWRLVL_EN_SHIFT		31
+#define EMIF_REG_RDWRLVL_EN_MASK		(1 << 31)
+#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT	24
+#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK	(0x7F << 24)
+#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT		16
+#define EMIF_REG_RDLVLINC_RMP_INT_MASK		(0xFF << 16)
+#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT	8
+#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK	(0xFF << 8)
+#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT		0
+#define EMIF_REG_WRLVLINC_RMP_INT_MASK		(0xFF << 0)
+
+/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/
+#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT	0
+#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK	(0x1FFF << 0)
+
+/* EMIF_PHY_CTRL_36 */
+#define EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR	(1 << 8)
+
+#define PHY_RDDQS_RATIO_REGS		5
+#define PHY_FIFO_WE_SLAVE_RATIO_REGS	5
+#define PHY_REG_WR_DQ_SLAVE_RATIO_REGS	10
+
+/*Leveling Fields */
+#define DDR3_WR_LVL_INT		0x73
+#define DDR3_RD_LVL_INT		0x33
+#define DDR3_RD_LVL_GATE_INT	0x59
+#define RD_RW_LVL_INC_PRE	0x0
+#define DDR3_FULL_LVL		(1 << EMIF_REG_RDWRLVL_EN_SHIFT)
+
+#define DDR3_INC_LVL	((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT)   \
+		| (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \
+		| (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT)      \
+		| (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT))
+
+#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES	0x0000C1A7
+#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES	0x000001A7
+#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7
+
+/* DMM */
+#define DMM_BASE			0x4E000040
+
+/* Memory Adapter */
+#define MA_BASE				0x482AF040
+#define MA_PRIORITY			0x482A2000
+#define MA_HIMEM_INTERLEAVE_UN_SHIFT	8
+#define MA_HIMEM_INTERLEAVE_UN_MASK	(1 << 8)
+
+/* DMM_LISA_MAP */
+#define EMIF_SYS_ADDR_SHIFT		24
+#define EMIF_SYS_ADDR_MASK		(0xff << 24)
+#define EMIF_SYS_SIZE_SHIFT		20
+#define EMIF_SYS_SIZE_MASK		(0x7 << 20)
+#define EMIF_SDRC_INTL_SHIFT	18
+#define EMIF_SDRC_INTL_MASK		(0x3 << 18)
+#define EMIF_SDRC_ADDRSPC_SHIFT	16
+#define EMIF_SDRC_ADDRSPC_MASK	(0x3 << 16)
+#define EMIF_SDRC_MAP_SHIFT		8
+#define EMIF_SDRC_MAP_MASK		(0x3 << 8)
+#define EMIF_SDRC_ADDR_SHIFT	0
+#define EMIF_SDRC_ADDR_MASK		(0xff << 0)
+
+/* DMM_LISA_MAP fields */
+#define DMM_SDRC_MAP_UNMAPPED		0
+#define DMM_SDRC_MAP_EMIF1_ONLY		1
+#define DMM_SDRC_MAP_EMIF2_ONLY		2
+#define DMM_SDRC_MAP_EMIF1_AND_EMIF2	3
+
+#define DMM_SDRC_INTL_NONE		0
+#define DMM_SDRC_INTL_128B		1
+#define DMM_SDRC_INTL_256B		2
+#define DMM_SDRC_INTL_512		3
+
+#define DMM_SDRC_ADDR_SPC_SDRAM		0
+#define DMM_SDRC_ADDR_SPC_NVM		1
+#define DMM_SDRC_ADDR_SPC_INVALID	2
+
+#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL		(\
+	(DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
+	(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
+	(DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
+	(CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
+
+#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
+
+#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL	(\
+	(DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
+
+/* Trap for invalid TILER PAT entries */
+#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
+	(0  << EMIF_SDRC_ADDR_SHIFT) |\
+	(DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\
+	(0xFF << EMIF_SYS_ADDR_SHIFT))
+
+#define EMIF_EXT_PHY_CTRL_TIMING_REG	0x5
+
+/* EMIF ECC CTRL reg */
+#define EMIF_ECC_CTRL_REG_ECC_EN_SHIFT			31
+#define EMIF_ECC_CTRL_REG_ECC_EN_MASK			(1 << 31)
+#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_SHIFT	30
+#define EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK	(1 << 30)
+#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_SHIFT		29
+#define EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK		(1 << 29)
+#define EMIF_ECC_REG_RMW_EN_SHIFT			28
+#define EMIF_ECC_REG_RMW_EN_MASK			(1 << 28)
+#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_SHIFT		1
+#define EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK		(1 << 1)
+#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_SHIFT		0
+#define EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK		(1 << 0)
+
+/* EMIF ECC ADDRESS RANGE */
+#define EMIF_ECC_REG_ECC_END_ADDR_SHIFT			16
+#define EMIF_ECC_REG_ECC_END_ADDR_MASK			(0xffff << 16)
+#define EMIF_ECC_REG_ECC_START_ADDR_SHIFT		0
+#define EMIF_ECC_REG_ECC_START_ADDR_MASK		(0xffff << 0)
+
+/* EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS */
+#define EMIF_INT_ONEBIT_ECC_ERR_SYS_SHIFT		5
+#define EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK		(1 << 5)
+#define EMIF_INT_TWOBIT_ECC_ERR_SYS_SHIFT		4
+#define EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK		(1 << 4)
+#define EMIF_INT_WR_ECC_ERR_SYS_SHIFT			3
+#define EMIF_INT_WR_ECC_ERR_SYS_MASK			(1 << 3)
+
+/* Reg mapping structure */
+struct emif_reg_struct {
+	u32 emif_mod_id_rev;
+	u32 emif_status;
+	u32 emif_sdram_config;
+	u32 emif_lpddr2_nvm_config;
+	u32 emif_sdram_ref_ctrl;
+	u32 emif_sdram_ref_ctrl_shdw;
+	u32 emif_sdram_tim_1;
+	u32 emif_sdram_tim_1_shdw;
+	u32 emif_sdram_tim_2;
+	u32 emif_sdram_tim_2_shdw;
+	u32 emif_sdram_tim_3;
+	u32 emif_sdram_tim_3_shdw;
+	u32 emif_lpddr2_nvm_tim;
+	u32 emif_lpddr2_nvm_tim_shdw;
+	u32 emif_pwr_mgmt_ctrl;
+	u32 emif_pwr_mgmt_ctrl_shdw;
+	u32 emif_lpddr2_mode_reg_data;
+	u32 padding1[1];
+	u32 emif_lpddr2_mode_reg_data_es2;
+	u32 padding11[1];
+	u32 emif_lpddr2_mode_reg_cfg;
+	u32 emif_l3_config;
+	u32 emif_l3_cfg_val_1;
+	u32 emif_l3_cfg_val_2;
+	u32 emif_iodft_tlgc;
+	u32 padding2[7];
+	u32 emif_perf_cnt_1;
+	u32 emif_perf_cnt_2;
+	u32 emif_perf_cnt_cfg;
+	u32 emif_perf_cnt_sel;
+	u32 emif_perf_cnt_tim;
+	u32 padding3;
+	u32 emif_read_idlectrl;
+	u32 emif_read_idlectrl_shdw;
+	u32 padding4;
+	u32 emif_irqstatus_raw_sys;
+	u32 emif_irqstatus_raw_ll;
+	u32 emif_irqstatus_sys;
+	u32 emif_irqstatus_ll;
+	u32 emif_irqenable_set_sys;
+	u32 emif_irqenable_set_ll;
+	u32 emif_irqenable_clr_sys;
+	u32 emif_irqenable_clr_ll;
+	u32 padding5;
+	u32 emif_zq_config;
+	u32 emif_temp_alert_config;
+	u32 emif_l3_err_log;
+	u32 emif_rd_wr_lvl_rmp_win;
+	u32 emif_rd_wr_lvl_rmp_ctl;
+	u32 emif_rd_wr_lvl_ctl;
+	u32 padding6[1];
+	u32 emif_ddr_phy_ctrl_1;
+	u32 emif_ddr_phy_ctrl_1_shdw;
+	u32 emif_ddr_phy_ctrl_2;
+	u32 padding7[4];
+	u32 emif_prio_class_serv_map;
+	u32 emif_connect_id_serv_1_map;
+	u32 emif_connect_id_serv_2_map;
+	u32 padding8;
+	u32 emif_ecc_ctrl_reg;
+	u32 emif_ecc_address_range_1;
+	u32 emif_ecc_address_range_2;
+	u32 padding8_1;
+	u32 emif_rd_wr_exec_thresh;
+	u32 emif_cos_config;
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_ARCH_KEYSTONE)
+	u32 padding9[2];
+	u32 emif_1b_ecc_err_cnt;
+	u32 emif_1b_ecc_err_thrush;
+	u32 emif_1b_ecc_err_dist_1;
+	u32 emif_1b_ecc_err_addr_log;
+	u32 emif_2b_ecc_err_addr_log;
+	u32 emif_ddr_phy_status[28];
+	u32 padding10[19];
+#else
+	u32 padding9[6];
+	u32 emif_ddr_phy_status[28];
+	u32 padding10[20];
+#endif
+	u32 emif_ddr_ext_phy_ctrl_1;
+	u32 emif_ddr_ext_phy_ctrl_1_shdw;
+	u32 emif_ddr_ext_phy_ctrl_2;
+	u32 emif_ddr_ext_phy_ctrl_2_shdw;
+	u32 emif_ddr_ext_phy_ctrl_3;
+	u32 emif_ddr_ext_phy_ctrl_3_shdw;
+	u32 emif_ddr_ext_phy_ctrl_4;
+	u32 emif_ddr_ext_phy_ctrl_4_shdw;
+	u32 emif_ddr_ext_phy_ctrl_5;
+	u32 emif_ddr_ext_phy_ctrl_5_shdw;
+	u32 emif_ddr_ext_phy_ctrl_6;
+	u32 emif_ddr_ext_phy_ctrl_6_shdw;
+	u32 emif_ddr_ext_phy_ctrl_7;
+	u32 emif_ddr_ext_phy_ctrl_7_shdw;
+	u32 emif_ddr_ext_phy_ctrl_8;
+	u32 emif_ddr_ext_phy_ctrl_8_shdw;
+	u32 emif_ddr_ext_phy_ctrl_9;
+	u32 emif_ddr_ext_phy_ctrl_9_shdw;
+	u32 emif_ddr_ext_phy_ctrl_10;
+	u32 emif_ddr_ext_phy_ctrl_10_shdw;
+	u32 emif_ddr_ext_phy_ctrl_11;
+	u32 emif_ddr_ext_phy_ctrl_11_shdw;
+	u32 emif_ddr_ext_phy_ctrl_12;
+	u32 emif_ddr_ext_phy_ctrl_12_shdw;
+	u32 emif_ddr_ext_phy_ctrl_13;
+	u32 emif_ddr_ext_phy_ctrl_13_shdw;
+	u32 emif_ddr_ext_phy_ctrl_14;
+	u32 emif_ddr_ext_phy_ctrl_14_shdw;
+	u32 emif_ddr_ext_phy_ctrl_15;
+	u32 emif_ddr_ext_phy_ctrl_15_shdw;
+	u32 emif_ddr_ext_phy_ctrl_16;
+	u32 emif_ddr_ext_phy_ctrl_16_shdw;
+	u32 emif_ddr_ext_phy_ctrl_17;
+	u32 emif_ddr_ext_phy_ctrl_17_shdw;
+	u32 emif_ddr_ext_phy_ctrl_18;
+	u32 emif_ddr_ext_phy_ctrl_18_shdw;
+	u32 emif_ddr_ext_phy_ctrl_19;
+	u32 emif_ddr_ext_phy_ctrl_19_shdw;
+	u32 emif_ddr_ext_phy_ctrl_20;
+	u32 emif_ddr_ext_phy_ctrl_20_shdw;
+	u32 emif_ddr_ext_phy_ctrl_21;
+	u32 emif_ddr_ext_phy_ctrl_21_shdw;
+	u32 emif_ddr_ext_phy_ctrl_22;
+	u32 emif_ddr_ext_phy_ctrl_22_shdw;
+	u32 emif_ddr_ext_phy_ctrl_23;
+	u32 emif_ddr_ext_phy_ctrl_23_shdw;
+	u32 emif_ddr_ext_phy_ctrl_24;
+	u32 emif_ddr_ext_phy_ctrl_24_shdw;
+	u32 emif_ddr_ext_phy_ctrl_25;
+	u32 emif_ddr_ext_phy_ctrl_25_shdw;
+	u32 emif_ddr_ext_phy_ctrl_26;
+	u32 emif_ddr_ext_phy_ctrl_26_shdw;
+	u32 emif_ddr_ext_phy_ctrl_27;
+	u32 emif_ddr_ext_phy_ctrl_27_shdw;
+	u32 emif_ddr_ext_phy_ctrl_28;
+	u32 emif_ddr_ext_phy_ctrl_28_shdw;
+	u32 emif_ddr_ext_phy_ctrl_29;
+	u32 emif_ddr_ext_phy_ctrl_29_shdw;
+	u32 emif_ddr_ext_phy_ctrl_30;
+	u32 emif_ddr_ext_phy_ctrl_30_shdw;
+	u32 emif_ddr_ext_phy_ctrl_31;
+	u32 emif_ddr_ext_phy_ctrl_31_shdw;
+	u32 emif_ddr_ext_phy_ctrl_32;
+	u32 emif_ddr_ext_phy_ctrl_32_shdw;
+	u32 emif_ddr_ext_phy_ctrl_33;
+	u32 emif_ddr_ext_phy_ctrl_33_shdw;
+	u32 emif_ddr_ext_phy_ctrl_34;
+	u32 emif_ddr_ext_phy_ctrl_34_shdw;
+	u32 emif_ddr_ext_phy_ctrl_35;
+	u32 emif_ddr_ext_phy_ctrl_35_shdw;
+	union {
+		u32 emif_ddr_ext_phy_ctrl_36;
+		u32 emif_ddr_fifo_misaligned_clear_1;
+	};
+	union {
+		u32 emif_ddr_ext_phy_ctrl_36_shdw;
+		u32 emif_ddr_fifo_misaligned_clear_2;
+	};
+};
+
+struct dmm_lisa_map_regs {
+	u32 dmm_lisa_map_0;
+	u32 dmm_lisa_map_1;
+	u32 dmm_lisa_map_2;
+	u32 dmm_lisa_map_3;
+	u8 is_ma_present;
+};
+
+#define CS0	0
+#define CS1	1
+/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
+#define MAX_LPDDR2_FREQ	400000000	/* 400 MHz */
+
+/*
+ * The period of DDR clk is represented as numerator and denominator for
+ * better accuracy in integer based calculations. However, if the numerator
+ * and denominator are very huge there may be chances of overflow in
+ * calculations. So, as a trade-off keep denominator(and consequently
+ * numerator) within a limit sacrificing some accuracy - but not much
+ * If denominator and numerator are already small (such as at 400 MHz)
+ * no adjustment is needed
+ */
+#define EMIF_PERIOD_DEN_LIMIT	1000
+/*
+ * Maximum number of different frequencies supported by EMIF driver
+ * Determines the number of entries in the pointer array for register
+ * cache
+ */
+#define EMIF_MAX_NUM_FREQUENCIES	6
+/*
+ * Indices into the Addressing Table array.
+ * One entry each for all the different types of devices with different
+ * addressing schemes
+ */
+#define ADDR_TABLE_INDEX64M	0
+#define ADDR_TABLE_INDEX128M	1
+#define ADDR_TABLE_INDEX256M	2
+#define ADDR_TABLE_INDEX512M	3
+#define ADDR_TABLE_INDEX1GS4	4
+#define ADDR_TABLE_INDEX2GS4	5
+#define ADDR_TABLE_INDEX4G	6
+#define ADDR_TABLE_INDEX8G	7
+#define ADDR_TABLE_INDEX1GS2	8
+#define ADDR_TABLE_INDEX2GS2	9
+#define ADDR_TABLE_INDEXMAX	10
+
+/* Number of Row bits */
+#define ROW_9  0
+#define ROW_10 1
+#define ROW_11 2
+#define ROW_12 3
+#define ROW_13 4
+#define ROW_14 5
+#define ROW_15 6
+#define ROW_16 7
+
+/* Number of Column bits */
+#define COL_8   0
+#define COL_9   1
+#define COL_10  2
+#define COL_11  3
+#define COL_7   4 /*Not supported by OMAP included for completeness */
+
+/* Number of Banks*/
+#define BANKS1 0
+#define BANKS2 1
+#define BANKS4 2
+#define BANKS8 3
+
+/* Refresh rate in micro seconds x 10 */
+#define T_REFI_15_6	156
+#define T_REFI_7_8	78
+#define T_REFI_3_9	39
+
+#define EBANK_CS1_DIS	0
+#define EBANK_CS1_EN	1
+
+/* Read Latency used by the device at reset */
+#define RL_BOOT		3
+/* Read Latency for the highest frequency you want to use */
+#ifdef CONFIG_OMAP54XX
+#define RL_FINAL	8
+#else
+#define RL_FINAL	6
+#endif
+
+
+/* Interleaving policies at EMIF level- between banks and Chip Selects */
+#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING	0
+#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING	3
+
+/*
+ * Interleaving policy to be used
+ * Currently set to MAX interleaving for better performance
+ */
+#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
+
+/* State of the core voltage:
+ * This is important for some parameters such as read idle control and
+ * ZQ calibration timings. Timings are much stricter when voltage ramp
+ * is happening compared to when the voltage is stable.
+ * We need to calculate two sets of values for these parameters and use
+ * them accordingly
+ */
+#define LPDDR2_VOLTAGE_STABLE	0
+#define LPDDR2_VOLTAGE_RAMPING	1
+
+/* Length of the forced read idle period in terms of cycles */
+#define EMIF_REG_READ_IDLE_LEN_VAL	5
+
+/* Interval between forced 'read idles' */
+/* To be used when voltage is changed for DPS/DVFS - 1us */
+#define READ_IDLE_INTERVAL_DVFS		(1*1000)
+/*
+ * To be used when voltage is not scaled except by Smart Reflex
+ * 50us - or maximum value will do
+ */
+#define READ_IDLE_INTERVAL_NORMAL	(50*1000)
+
+
+/*
+ * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
+ * be enough. This shoule be enough also in the case when voltage is changing
+ * due to smart-reflex.
+ */
+#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US	(50*1000)
+/*
+ * If voltage is changing due to DVFS ZQCS should be performed more
+ * often(every 50us)
+ */
+#define EMIF_ZQCS_INTERVAL_DVFS_IN_US	50
+
+/* The interval between ZQCL commands as a multiple of ZQCS interval */
+#define REG_ZQ_ZQCL_MULT		4
+/* The interval between ZQINIT commands as a multiple of ZQCL interval */
+#define REG_ZQ_ZQINIT_MULT		3
+/* Enable ZQ Calibration on exiting Self-refresh */
+#define REG_ZQ_SFEXITEN_ENABLE		1
+/*
+ * ZQ Calibration simultaneously on both chip-selects:
+ * Needs one calibration resistor per CS
+ * None of the boards that we know of have this capability
+ * So disabled by default
+ */
+#define REG_ZQ_DUALCALEN_DISABLE	0
+/*
+ * Enable ZQ Calibration by default on CS0. If we are asked to program
+ * the EMIF there will be something connected to CS0 for sure
+ */
+#define REG_ZQ_CS0EN_ENABLE		1
+
+/* EMIF_PWR_MGMT_CTRL register */
+/* Low power modes */
+#define LP_MODE_DISABLE		0
+#define LP_MODE_CLOCK_STOP	1
+#define LP_MODE_SELF_REFRESH	2
+#define LP_MODE_PWR_DN		3
+
+/* REG_DPD_EN */
+#define DPD_DISABLE	0
+#define DPD_ENABLE	1
+
+/* Maximum delay before Low Power Modes */
+#define REG_CS_TIM		0x0
+#define REG_SR_TIM		0xF
+#define REG_PD_TIM		0xF
+
+
+/* EMIF_PWR_MGMT_CTRL register */
+#define EMIF_PWR_MGMT_CTRL (\
+	((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
+	((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
+	((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
+	((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)\
+			& EMIF_REG_LP_MODE_MASK) |\
+	((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
+			& EMIF_REG_DPD_EN_MASK))\
+
+#define EMIF_PWR_MGMT_CTRL_SHDW (\
+	((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\
+			& EMIF_REG_CS_TIM_SHDW_MASK) |\
+	((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
+			& EMIF_REG_SR_TIM_SHDW_MASK) |\
+	((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
+			& EMIF_REG_PD_TIM_SHDW_MASK))
+
+/* EMIF_L3_CONFIG register value */
+#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0	0x0A0000FF
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0	0x0A500000
+
+/*
+ * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
+ * All these fields have magic values dependent on frequency and
+ * determined by PHY and DLL integration with EMIF. Setting the magic
+ * values suggested by hw team.
+ */
+#define EMIF_DDR_PHY_CTRL_1_BASE_VAL			0x049FF
+#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ			0x41
+#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ			0x80
+#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS	0xFF
+
+/*
+* MR1 value:
+* Burst length	: 8
+* Burst type	: sequential
+* Wrap		: enabled
+* nWR		: 3(default). EMIF does not do pre-charge.
+*		: So nWR is don't care
+*/
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3	0x23
+#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8	0xc3
+
+/* MR2 */
+#define MR2_RL3_WL1			1
+#define MR2_RL4_WL2			2
+#define MR2_RL5_WL2			3
+#define MR2_RL6_WL3			4
+
+/* MR10: ZQ calibration codes */
+#define MR10_ZQ_ZQCS		0x56
+#define MR10_ZQ_ZQCL		0xAB
+#define MR10_ZQ_ZQINIT		0xFF
+#define MR10_ZQ_ZQRESET		0xC3
+
+/* TEMP_ALERT_CONFIG */
+#define TEMP_ALERT_POLL_INTERVAL_MS	360 /* for temp gradient - 5 C/s */
+#define TEMP_ALERT_CONFIG_DEVCT_1	0
+#define TEMP_ALERT_CONFIG_DEVWDT_32	2
+
+/* MR16 value: refresh full array(no partial array self refresh) */
+#define MR16_REF_FULL_ARRAY	0
+
+/*
+ * Maximum number of entries we keep in our array of timing tables
+ * We need not keep all the speed bins supported by the device
+ * We need to keep timing tables for only the speed bins that we
+ * are interested in
+ */
+#define MAX_NUM_SPEEDBINS	4
+
+/* LPDDR2 Densities */
+#define LPDDR2_DENSITY_64Mb	0
+#define LPDDR2_DENSITY_128Mb	1
+#define LPDDR2_DENSITY_256Mb	2
+#define LPDDR2_DENSITY_512Mb	3
+#define LPDDR2_DENSITY_1Gb	4
+#define LPDDR2_DENSITY_2Gb	5
+#define LPDDR2_DENSITY_4Gb	6
+#define LPDDR2_DENSITY_8Gb	7
+#define LPDDR2_DENSITY_16Gb	8
+#define LPDDR2_DENSITY_32Gb	9
+
+/* LPDDR2 type */
+#define	LPDDR2_TYPE_S4	0
+#define	LPDDR2_TYPE_S2	1
+#define	LPDDR2_TYPE_NVM	2
+
+/* LPDDR2 IO width */
+#define	LPDDR2_IO_WIDTH_32	0
+#define	LPDDR2_IO_WIDTH_16	1
+#define	LPDDR2_IO_WIDTH_8	2
+
+/* Mode register numbers */
+#define LPDDR2_MR0	0
+#define LPDDR2_MR1	1
+#define LPDDR2_MR2	2
+#define LPDDR2_MR3	3
+#define LPDDR2_MR4	4
+#define LPDDR2_MR5	5
+#define LPDDR2_MR6	6
+#define LPDDR2_MR7	7
+#define LPDDR2_MR8	8
+#define LPDDR2_MR9	9
+#define LPDDR2_MR10	10
+#define LPDDR2_MR11	11
+#define LPDDR2_MR16	16
+#define LPDDR2_MR17	17
+#define LPDDR2_MR18	18
+
+/* MR0 */
+#define LPDDR2_MR0_DAI_SHIFT	0
+#define LPDDR2_MR0_DAI_MASK	1
+#define LPDDR2_MR0_DI_SHIFT	1
+#define LPDDR2_MR0_DI_MASK	(1 << 1)
+#define LPDDR2_MR0_DNVI_SHIFT	2
+#define LPDDR2_MR0_DNVI_MASK	(1 << 2)
+
+/* MR4 */
+#define MR4_SDRAM_REF_RATE_SHIFT	0
+#define MR4_SDRAM_REF_RATE_MASK		7
+#define MR4_TUF_SHIFT			7
+#define MR4_TUF_MASK			(1 << 7)
+
+/* MR4 SDRAM Refresh Rate field values */
+#define SDRAM_TEMP_LESS_LOW_SHUTDOWN			0x0
+#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS		0x1
+#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS		0x2
+#define SDRAM_TEMP_NOMINAL				0x3
+#define SDRAM_TEMP_RESERVED_4				0x4
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH			0x5
+#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS	0x6
+#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN			0x7
+
+#define LPDDR2_MANUFACTURER_SAMSUNG	1
+#define LPDDR2_MANUFACTURER_QIMONDA	2
+#define LPDDR2_MANUFACTURER_ELPIDA	3
+#define LPDDR2_MANUFACTURER_ETRON	4
+#define LPDDR2_MANUFACTURER_NANYA	5
+#define LPDDR2_MANUFACTURER_HYNIX	6
+#define LPDDR2_MANUFACTURER_MOSEL	7
+#define LPDDR2_MANUFACTURER_WINBOND	8
+#define LPDDR2_MANUFACTURER_ESMT	9
+#define LPDDR2_MANUFACTURER_SPANSION 11
+#define LPDDR2_MANUFACTURER_SST		12
+#define LPDDR2_MANUFACTURER_ZMOS	13
+#define LPDDR2_MANUFACTURER_INTEL	14
+#define LPDDR2_MANUFACTURER_NUMONYX	254
+#define LPDDR2_MANUFACTURER_MICRON	255
+
+/* MR8 register fields */
+#define MR8_TYPE_SHIFT		0x0
+#define MR8_TYPE_MASK		0x3
+#define MR8_DENSITY_SHIFT	0x2
+#define MR8_DENSITY_MASK	(0xF << 0x2)
+#define MR8_IO_WIDTH_SHIFT	0x6
+#define MR8_IO_WIDTH_MASK	(0x3 << 0x6)
+
+/* SDRAM TYPE */
+#define EMIF_SDRAM_TYPE_DDR2	0x2
+#define EMIF_SDRAM_TYPE_DDR3	0x3
+#define EMIF_SDRAM_TYPE_LPDDR2	0x4
+
+struct lpddr2_addressing {
+	u8	num_banks;
+	u8	t_REFI_us_x10;
+	u8	row_sz[2]; /* One entry each for x32 and x16 */
+	u8	col_sz[2]; /* One entry each for x32 and x16 */
+};
+
+/* Structure for timings from the DDR datasheet */
+struct lpddr2_ac_timings {
+	u32 max_freq;
+	u8 RL;
+	u8 tRPab;
+	u8 tRCD;
+	u8 tWR;
+	u8 tRASmin;
+	u8 tRRD;
+	u8 tWTRx2;
+	u8 tXSR;
+	u8 tXPx2;
+	u8 tRFCab;
+	u8 tRTPx2;
+	u8 tCKE;
+	u8 tCKESR;
+	u8 tZQCS;
+	u32 tZQCL;
+	u32 tZQINIT;
+	u8 tDQSCKMAXx2;
+	u8 tRASmax;
+	u8 tFAW;
+
+};
+
+/*
+ * Min tCK values for some of the parameters:
+ * If the calculated clock cycles for the respective parameter is
+ * less than the corresponding min tCK value, we need to set the min
+ * tCK value. This may happen at lower frequencies.
+ */
+struct lpddr2_min_tck {
+	u32 tRL;
+	u32 tRP_AB;
+	u32 tRCD;
+	u32 tWR;
+	u32 tRAS_MIN;
+	u32 tRRD;
+	u32 tWTR;
+	u32 tXP;
+	u32 tRTP;
+	u8  tCKE;
+	u32 tCKESR;
+	u32 tFAW;
+};
+
+struct lpddr2_device_details {
+	u8	type;
+	u8	density;
+	u8	io_width;
+	u8	manufacturer;
+};
+
+struct lpddr2_device_timings {
+	const struct lpddr2_ac_timings **ac_timings;
+	const struct lpddr2_min_tck *min_tck;
+};
+
+/* Details of the devices connected to each chip-select of an EMIF instance */
+struct emif_device_details {
+	const struct lpddr2_device_details *cs0_device_details;
+	const struct lpddr2_device_details *cs1_device_details;
+	const struct lpddr2_device_timings *cs0_device_timings;
+	const struct lpddr2_device_timings *cs1_device_timings;
+};
+
+/*
+ * Structure containing shadow of important registers in EMIF
+ * The calculation function fills in this structure to be later used for
+ * initialization and DVFS
+ */
+struct emif_regs {
+	u32 freq;
+	u32 sdram_config_init;
+	u32 sdram_config;
+	u32 sdram_config2;
+	u32 ref_ctrl;
+	u32 ref_ctrl_final;
+	u32 sdram_tim1;
+	u32 sdram_tim2;
+	u32 sdram_tim3;
+	u32 ocp_config;
+	u32 read_idle_ctrl;
+	u32 zq_config;
+	u32 temp_alert_config;
+	u32 emif_ddr_phy_ctlr_1_init;
+	u32 emif_ddr_phy_ctlr_1;
+	u32 emif_ddr_ext_phy_ctrl_1;
+	u32 emif_ddr_ext_phy_ctrl_2;
+	u32 emif_ddr_ext_phy_ctrl_3;
+	u32 emif_ddr_ext_phy_ctrl_4;
+	u32 emif_ddr_ext_phy_ctrl_5;
+	u32 emif_rd_wr_lvl_rmp_win;
+	u32 emif_rd_wr_lvl_rmp_ctl;
+	u32 emif_rd_wr_lvl_ctl;
+	u32 emif_rd_wr_exec_thresh;
+	u32 emif_prio_class_serv_map;
+	u32 emif_connect_id_serv_1_map;
+	u32 emif_connect_id_serv_2_map;
+	u32 emif_cos_config;
+	u32 emif_ecc_ctrl_reg;
+	u32 emif_ecc_address_range_1;
+	u32 emif_ecc_address_range_2;
+};
+
+struct lpddr2_mr_regs {
+	s8 mr1;
+	s8 mr2;
+	s8 mr3;
+	s8 mr10;
+	s8 mr16;
+};
+
+struct read_write_regs {
+	u32 read_reg;
+	u32 write_reg;
+};
+
+static inline u32 get_emif_rev(u32 base)
+{
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
+		>> EMIF_REG_MAJOR_REVISION_SHIFT;
+}
+
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+static inline u32 emif_sdram_type(u32 sdram_config)
+{
+	return (sdram_config & EMIF_REG_SDRAM_TYPE_MASK)
+	       >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
+
+/* assert macros */
+#if defined(DEBUG)
+#define emif_assert(c)	({ if (!(c)) for (;;); })
+#else
+#define emif_assert(c)	({ if (0) hang(); })
+#endif
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
+#else
+struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details);
+void emif_get_device_timings(u32 emif_nr,
+		const struct lpddr2_device_timings **cs0_device_timings,
+		const struct lpddr2_device_timings **cs1_device_timings);
+#endif
+
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
+
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+extern u32 *const T_num;
+extern u32 *const T_den;
+#endif
+
+void config_data_eye_leveling_samples(u32 emif_base);
+const struct read_write_regs *get_bug_regs(u32 *iterations);
+#endif
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
new file mode 100644
index 0000000..b0c7599
--- /dev/null
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef __FSL_SECURE_BOOT_H
+#define __FSL_SECURE_BOOT_H
+
+#ifdef CONFIG_CHAIN_OF_TRUST
+#define CONFIG_FSL_SEC_MON
+
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Define the key hash for U-Boot here if public/private key pair used to
+ * sign U-boot are different from the SRK hash put in the fuse
+ * Example of defining KEY_HASH is
+ * #define CONFIG_SPL_UBOOT_KEY_HASH \
+ *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ * else leave it defined as NULL
+ */
+
+#define CONFIG_SPL_UBOOT_KEY_HASH	NULL
+#endif /* ifdef CONFIG_SPL_BUILD */
+
+#define CONFIG_KEY_REVOCATION
+
+#if defined(CONFIG_FSL_LAYERSCAPE)
+/*
+ * For fsl layerscape based platforms, ESBC image Address in Header
+ * is 64 bit.
+ */
+#define CONFIG_ESBC_ADDR_64BIT
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_SYS_RAMBOOT
+/* The key used for verification of next level images
+ * is picked up from an Extension Table which has
+ * been verified by the ISBC (Internal Secure boot Code)
+ * in boot ROM of the SoC.
+ * The feature is only applicable in case of NOR boot and is
+ * not applicable in case of RAMBOOT (NAND, SD, SPI).
+ * For LS, this feature is available for all device if IE Table
+ * is copied to XIP memory
+ * Also, for LS, ISBC doesn't verify this table.
+ */
+#define CONFIG_FSL_ISBC_KEY_EXT
+
+#endif
+
+#ifdef CONFIG_ARCH_LS2080A
+#define CONFIG_EXTRA_ENV \
+	"setenv fdt_high 0xa0000000;"	\
+	"setenv initrd_high 0xcfffffff;"	\
+	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
+#else
+#define CONFIG_EXTRA_ENV \
+	"setenv fdt_high 0xffffffff;"	\
+	"setenv initrd_high 0xffffffff;"	\
+	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
+#endif
+
+/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
+ * Non-XIP Memory (Nand/SD)*/
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \
+	defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT)
+#define CONFIG_BOOTSCRIPT_COPY_RAM
+#endif
+/* The address needs to be modified according to NOR, NAND, SD and
+ * DDR memory map
+ */
+#ifdef CONFIG_FSL_LSCH3
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_BS_ADDR_DEVICE		0x20600000
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x20640000
+#else /* NOR BOOT */
+#define CONFIG_BS_ADDR_DEVICE		0x580600000
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x580640000
+#endif /*ifdef CONFIG_QSPI_BOOT */
+#define CONFIG_BS_SIZE			0x00001000
+#define CONFIG_BS_HDR_SIZE		0x00004000
+#define CONFIG_BS_ADDR_RAM		0xa0600000
+#define CONFIG_BS_HDR_ADDR_RAM		0xa0640000
+#else
+#ifdef CONFIG_SD_BOOT
+/* For SD boot address and size are assigned in terms of sector
+ * offset and no. of sectors respectively.
+ */
+#define CONFIG_BS_ADDR_DEVICE		0x00003000
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x00003200
+#define CONFIG_BS_SIZE			0x00000008
+#define CONFIG_BS_HDR_SIZE		0x00000010
+#elif defined(CONFIG_NAND_BOOT)
+#define CONFIG_BS_ADDR_DEVICE		0x00600000
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x00640000
+#define CONFIG_BS_SIZE			0x00001000
+#define CONFIG_BS_HDR_SIZE		0x00002000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_BS_ADDR_DEVICE		0x40600000
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x40640000
+#define CONFIG_BS_SIZE			0x00001000
+#define CONFIG_BS_HDR_SIZE		0x00002000
+#else /* Default NOR Boot */
+#define CONFIG_BS_ADDR_DEVICE		0x60600000
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x60640000
+#define CONFIG_BS_SIZE			0x00001000
+#define CONFIG_BS_HDR_SIZE		0x00002000
+#endif
+#define CONFIG_BS_ADDR_RAM		0x81000000
+#define CONFIG_BS_HDR_ADDR_RAM		0x81020000
+#endif
+
+#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
+#define CONFIG_BOOTSCRIPT_ADDR		CONFIG_BS_ADDR_RAM
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
+#else
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_DEVICE
+/* BOOTSCRIPT_ADDR is not required */
+#endif
+
+#ifdef CONFIG_FSL_LS_PPA
+/* Define the key hash here if SRK used for signing PPA image is
+ * different from SRK hash put in SFP used for U-Boot.
+ * Example
+ * #define PPA_KEY_HASH \
+ *	"41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ */
+#define PPA_KEY_HASH		NULL
+#endif /* ifdef CONFIG_FSL_LS_PPA */
+
+#include <config_fsl_chain_trust.h>
+#endif /* #ifndef CONFIG_SPL_BUILD */
+#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
+#endif
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
new file mode 100644
index 0000000..bd3a80c
--- /dev/null
+++ b/arch/arm/include/asm/gic.h
@@ -0,0 +1,110 @@
+#ifndef __GIC_H__
+#define __GIC_H__
+
+/* Register offsets for the ARM generic interrupt controller (GIC) */
+
+#define GIC_DIST_OFFSET		0x1000
+#define GIC_CPU_OFFSET_A9	0x0100
+#define GIC_CPU_OFFSET_A15	0x2000
+
+/* Distributor Registers */
+#define GICD_CTLR		0x0000
+#define GICD_TYPER		0x0004
+#define GICD_IIDR		0x0008
+#define GICD_STATUSR		0x0010
+#define GICD_SETSPI_NSR		0x0040
+#define GICD_CLRSPI_NSR		0x0048
+#define GICD_SETSPI_SR		0x0050
+#define GICD_CLRSPI_SR		0x0058
+#define GICD_SEIR		0x0068
+#define GICD_IGROUPRn		0x0080
+#define GICD_ISENABLERn		0x0100
+#define GICD_ICENABLERn		0x0180
+#define GICD_ISPENDRn		0x0200
+#define GICD_ICPENDRn		0x0280
+#define GICD_ISACTIVERn		0x0300
+#define GICD_ICACTIVERn		0x0380
+#define GICD_IPRIORITYRn	0x0400
+#define GICD_ITARGETSRn		0x0800
+#define GICD_ICFGR		0x0c00
+#define GICD_IGROUPMODRn	0x0d00
+#define GICD_NSACRn		0x0e00
+#define GICD_SGIR		0x0f00
+#define GICD_CPENDSGIRn		0x0f10
+#define GICD_SPENDSGIRn		0x0f20
+#define GICD_IROUTERn		0x6000
+
+/* Cpu Interface Memory Mapped Registers */
+#define GICC_CTLR		0x0000
+#define GICC_PMR		0x0004
+#define GICC_BPR		0x0008
+#define GICC_IAR		0x000C
+#define GICC_EOIR		0x0010
+#define GICC_RPR		0x0014
+#define GICC_HPPIR		0x0018
+#define GICC_ABPR		0x001c
+#define GICC_AIAR		0x0020
+#define GICC_AEOIR		0x0024
+#define GICC_AHPPIR		0x0028
+#define GICC_APRn		0x00d0
+#define GICC_NSAPRn		0x00e0
+#define GICC_IIDR		0x00fc
+#define GICC_DIR		0x1000
+
+/* ReDistributor Registers for Control and Physical LPIs */
+#define GICR_CTLR		0x0000
+#define GICR_IIDR		0x0004
+#define GICR_TYPER		0x0008
+#define GICR_STATUSR		0x0010
+#define GICR_WAKER		0x0014
+#define GICR_SETLPIR		0x0040
+#define GICR_CLRLPIR		0x0048
+#define GICR_SEIR		0x0068
+#define GICR_PROPBASER		0x0070
+#define GICR_PENDBASER		0x0078
+#define GICR_INVLPIR		0x00a0
+#define GICR_INVALLR		0x00b0
+#define GICR_SYNCR		0x00c0
+#define GICR_MOVLPIR		0x0100
+#define GICR_MOVALLR		0x0110
+
+/* ReDistributor Registers for SGIs and PPIs */
+#define GICR_IGROUPRn		0x0080
+#define GICR_ISENABLERn		0x0100
+#define GICR_ICENABLERn		0x0180
+#define GICR_ISPENDRn		0x0200
+#define GICR_ICPENDRn		0x0280
+#define GICR_ISACTIVERn		0x0300
+#define GICR_ICACTIVERn		0x0380
+#define GICR_IPRIORITYRn	0x0400
+#define GICR_ICFGR0		0x0c00
+#define GICR_ICFGR1		0x0c04
+#define GICR_IGROUPMODRn	0x0d00
+#define GICR_NSACRn		0x0e00
+
+/* Cpu Interface System Registers */
+#define ICC_IAR0_EL1		S3_0_C12_C8_0
+#define ICC_IAR1_EL1		S3_0_C12_C12_0
+#define ICC_EOIR0_EL1		S3_0_C12_C8_1
+#define ICC_EOIR1_EL1		S3_0_C12_C12_1
+#define ICC_HPPIR0_EL1		S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1		S3_0_C12_C12_2
+#define ICC_BPR0_EL1		S3_0_C12_C8_3
+#define ICC_BPR1_EL1		S3_0_C12_C12_3
+#define ICC_DIR_EL1		S3_0_C12_C11_1
+#define ICC_PMR_EL1		S3_0_C4_C6_0
+#define ICC_RPR_EL1		S3_0_C12_C11_3
+#define ICC_CTLR_EL1		S3_0_C12_C12_4
+#define ICC_CTLR_EL3		S3_6_C12_C12_4
+#define ICC_SRE_EL1		S3_0_C12_C12_5
+#define ICC_SRE_EL2		S3_4_C12_C9_5
+#define ICC_SRE_EL3		S3_6_C12_C12_5
+#define ICC_IGRPEN0_EL1		S3_0_C12_C12_6
+#define ICC_IGRPEN1_EL1		S3_0_C12_C12_7
+#define ICC_IGRPEN1_EL3		S3_6_C12_C12_7
+#define ICC_SEIEN_EL1		S3_0_C12_C13_0
+#define ICC_SGI0R_EL1		S3_0_C12_C11_7
+#define ICC_SGI1R_EL1		S3_0_C12_C11_5
+#define ICC_ASGI1R_EL1		S3_0_C12_C11_6
+
+#endif /* __GIC_H__ */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
new file mode 100644
index 0000000..1774014
--- /dev/null
+++ b/arch/arm/include/asm/global_data.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+/* Architecture-specific global data */
+struct arch_global_data {
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
+	u32 sdhc_clk;
+#endif
+
+#if defined(CONFIG_U_QE)
+	u32 qe_clk;
+	u32 brg_clk;
+	uint mp_alloc_base;
+	uint mp_alloc_top;
+#endif /* CONFIG_U_QE */
+
+#ifdef CONFIG_AT91FAMILY
+	/* "static data" needed by at91's clock.c */
+	unsigned long	cpu_clk_rate_hz;
+	unsigned long	main_clk_rate_hz;
+	unsigned long	mck_rate_hz;
+	unsigned long	plla_rate_hz;
+	unsigned long	pllb_rate_hz;
+	unsigned long	at91_pllb_usb_init;
+#endif
+	/* "static data" needed by most of timer.c on ARM platforms */
+	unsigned long timer_rate_hz;
+	unsigned int tbu;
+	unsigned int tbl;
+	unsigned long lastinc;
+	unsigned long long timer_reset_value;
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+	unsigned long tlb_addr;
+	unsigned long tlb_size;
+#if defined(CONFIG_ARM64)
+	unsigned long tlb_fillptr;
+	unsigned long tlb_emerg;
+#endif
+#endif
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+#define MEM_RESERVE_SECURE_SECURED	0x1
+#define MEM_RESERVE_SECURE_MAINTAINED	0x2
+#define MEM_RESERVE_SECURE_ADDR_MASK	(~0x3)
+	/*
+	 * Secure memory addr
+	 * This variable needs maintenance if the RAM base is not zero,
+	 * or if RAM splits into non-consecutive banks. It also has a
+	 * flag indicating the secure memory is marked as secure by MMU.
+	 * Flags used: 0x1 secured
+	 *             0x2 maintained
+	 */
+	phys_addr_t secure_ram;
+	unsigned long tlb_allocated;
+#endif
+#ifdef CONFIG_RESV_RAM
+	/*
+	 * Reserved RAM for memory resident, eg. Management Complex (MC)
+	 * driver which continues to run after U-Boot exits.
+	 */
+	phys_addr_t resv_ram;
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2PLUS
+	u32 omap_boot_device;
+	u32 omap_boot_mode;
+	u8 omap_ch_flags;
+#endif
+#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
+	unsigned long mem2_clk;
+#endif
+
+#ifdef CONFIG_ARCH_IMX8
+	struct udevice *scu_dev;
+#endif
+};
+
+#include <asm-generic/global_data.h>
+
+#ifdef __clang__
+
+#define DECLARE_GLOBAL_DATA_PTR
+#define gd	get_gd()
+
+static inline gd_t *get_gd(void)
+{
+	gd_t *gd_ptr;
+
+#ifdef CONFIG_ARM64
+	/*
+	 * Make will already error that reserving x18 is not supported at the
+	 * time of writing, clang: error: unknown argument: '-ffixed-x18'
+	 */
+	__asm__ volatile("mov %0, x18\n" : "=r" (gd_ptr));
+#else
+	__asm__ volatile("mov %0, r9\n" : "=r" (gd_ptr));
+#endif
+
+	return gd_ptr;
+}
+
+#else
+
+#ifdef CONFIG_ARM64
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("x18")
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("r9")
+#endif
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
new file mode 100644
index 0000000..6ff5f42
--- /dev/null
+++ b/arch/arm/include/asm/gpio.h
@@ -0,0 +1,9 @@
+#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
+	!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \
+	!defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \
+	!defined(CONFIG_ARCH_LX2160A) && !defined(CONFIG_ARCH_LS1028A) && \
+	!defined(CONFIG_ARCH_LS2080A) && !defined(CONFIG_ARCH_LS1088A) && \
+	!defined(CONFIG_ARCH_ASPEED)
+#include <asm/arch/gpio.h>
+#endif
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/include/asm/hardware.h b/arch/arm/include/asm/hardware.h
new file mode 100644
index 0000000..1fd1a5b
--- /dev/null
+++ b/arch/arm/include/asm/hardware.h
@@ -0,0 +1,18 @@
+/*
+ *  linux/include/asm-arm/hardware.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Common hardware definitions
+ */
+
+#ifndef __ASM_HARDWARE_H
+#define __ASM_HARDWARE_H
+
+#include <asm/arch/hardware.h>
+
+#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
new file mode 100644
index 0000000..723f3cf
--- /dev/null
+++ b/arch/arm/include/asm/io.h
@@ -0,0 +1,381 @@
+/*
+ *  linux/include/asm-arm/io.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_ARM_IO_H
+#define __ASM_ARM_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+#include <asm/memory.h>
+#include <asm/barriers.h>
+#if 0	/* XXX###XXX */
+#include <asm/arch/hardware.h>
+#endif	/* XXX###XXX */
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+#define __arch_getq(a)			(*(volatile unsigned long long *)(a))
+
+#define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
+#define __arch_putq(v,a)		(*(volatile unsigned long long *)(a) = (v))
+
+static inline void __raw_writesb(unsigned long addr, const void *data,
+				 int bytelen)
+{
+	uint8_t *buf = (uint8_t *)data;
+	while(bytelen--)
+		__arch_putb(*buf++, addr);
+}
+
+static inline void __raw_writesw(unsigned long addr, const void *data,
+				 int wordlen)
+{
+	uint16_t *buf = (uint16_t *)data;
+	while(wordlen--)
+		__arch_putw(*buf++, addr);
+}
+
+static inline void __raw_writesl(unsigned long addr, const void *data,
+				 int longlen)
+{
+	uint32_t *buf = (uint32_t *)data;
+	while(longlen--)
+		__arch_putl(*buf++, addr);
+}
+
+static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
+{
+	uint8_t *buf = (uint8_t *)data;
+	while(bytelen--)
+		*buf++ = __arch_getb(addr);
+}
+
+static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
+{
+	uint16_t *buf = (uint16_t *)data;
+	while(wordlen--)
+		*buf++ = __arch_getw(addr);
+}
+
+static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
+{
+	uint32_t *buf = (uint32_t *)data;
+	while(longlen--)
+		*buf++ = __arch_getl(addr);
+}
+
+#define __raw_writeb(v,a)	__arch_putb(v,a)
+#define __raw_writew(v,a)	__arch_putw(v,a)
+#define __raw_writel(v,a)	__arch_putl(v,a)
+#define __raw_writeq(v,a)	__arch_putq(v,a)
+
+#define __raw_readb(a)		__arch_getb(a)
+#define __raw_readw(a)		__arch_getw(a)
+#define __raw_readl(a)		__arch_getl(a)
+#define __raw_readq(a)		__arch_getq(a)
+
+/*
+ * TODO: The kernel offers some more advanced versions of barriers, it might
+ * have some advantages to use them instead of the simple one here.
+ */
+#define mb()		dsb()
+#define __iormb()	dmb()
+#define __iowmb()	dmb()
+
+#define writeb(v,c)	({ u8  __v = v; __iowmb(); __arch_putb(__v,c); __v; })
+#define writew(v,c)	({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
+#define writel(v,c)	({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
+#define writeq(v,c)	({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; })
+
+#define readb(c)	({ u8  __v = __arch_getb(c); __iormb(); __v; })
+#define readw(c)	({ u16 __v = __arch_getw(c); __iormb(); __v; })
+#define readl(c)	({ u32 __v = __arch_getl(c); __iormb(); __v; })
+#define readq(c)	({ u64 __v = __arch_getq(c); __iormb(); __v; })
+
+/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses.
+ */
+#define readb_relaxed(c)	({ u8  __r = __raw_readb(c); __r; })
+#define readw_relaxed(c)	({ u16 __r = le16_to_cpu((__force __le16) \
+						__raw_readw(c)); __r; })
+#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32) \
+						__raw_readl(c)); __r; })
+#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64) \
+						__raw_readq(c)); __r; })
+
+#define writeb_relaxed(v, c)	((void)__raw_writeb((v), (c)))
+#define writew_relaxed(v, c)	((void)__raw_writew((__force u16) \
+						    cpu_to_le16(v), (c)))
+#define writel_relaxed(v, c)	((void)__raw_writel((__force u32) \
+						    cpu_to_le32(v), (c)))
+#define writeq_relaxed(v, c)	((void)__raw_writeq((__force u64) \
+						    cpu_to_le64(v), (c)))
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val,base,off)	__arch_base_putb(val,base,off)
+#define __raw_base_writew(val,base,off)	__arch_base_putw(val,base,off)
+#define __raw_base_writel(val,base,off)	__arch_base_putl(val,base,off)
+
+#define __raw_base_readb(base,off)	__arch_base_getb(base,off)
+#define __raw_base_readw(base,off)	__arch_base_getw(base,off)
+#define __raw_base_readl(base,off)	__arch_base_getl(base,off)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define out_arch(type,endian,a,v)	__raw_write##type(cpu_to_##endian(v),a)
+#define in_arch(type,endian,a)		endian##_to_cpu(__raw_read##type(a))
+
+#define out_le64(a,v)	out_arch(q,le64,a,v)
+#define out_le32(a,v)	out_arch(l,le32,a,v)
+#define out_le16(a,v)	out_arch(w,le16,a,v)
+
+#define in_le64(a)	in_arch(q,le64,a)
+#define in_le32(a)	in_arch(l,le32,a)
+#define in_le16(a)	in_arch(w,le16,a)
+
+#define out_be32(a,v)	out_arch(l,be32,a,v)
+#define out_be16(a,v)	out_arch(w,be16,a,v)
+
+#define in_be32(a)	in_arch(l,be32,a)
+#define in_be16(a)	in_arch(w,be16,a)
+
+#define out_32(a,v)	__raw_writel(v,a)
+#define out_16(a,v)	__raw_writew(v,a)
+#define out_8(a,v)	__raw_writeb(v,a)
+
+#define in_32(a)	__raw_readl(a)
+#define in_16(a)	__raw_readw(a)
+#define in_8(a)		__raw_readb(a)
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_32(addr, clear) clrbits(32, addr, clear)
+#define setbits_32(addr, set) setbits(32, addr, set)
+#define clrsetbits_32(addr, clear, set) clrsetbits(32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_16(addr, clear) clrbits(16, addr, clear)
+#define setbits_16(addr, set) setbits(16, addr, set)
+#define clrsetbits_16(addr, clear, set) clrsetbits(16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ */
+#if 0	/* XXX###XXX */
+#include <asm/arch/io.h>
+#endif	/* XXX###XXX */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The ARM doesn't have special IO access instructions; all IO is memory
+ * mapped.  Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerous
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v,p)			__raw_writeb(v,__io(p))
+#define outw(v,p)			__raw_writew(cpu_to_le16(v),__io(p))
+#define outl(v,p)			__raw_writel(cpu_to_le32(v),__io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p,d,l)			__raw_writesb(__io(p),d,l)
+#define outsw(p,d,l)			__raw_writesw(__io(p),d,l)
+#define outsl(p,d,l)			__raw_writesl(__io(p),d,l)
+
+#define insb(p,d,l)			__raw_readsb(__io(p),d,l)
+#define insw(p,d,l)			__raw_readsw(__io(p),d,l)
+#define insl(p,d,l)			__raw_readsl(__io(p),d,l)
+#endif
+
+#define outb_p(val,port)		outb((val),(port))
+#define outw_p(val,port)		outw((val),(port))
+#define outl_p(val,port)		outl((val),(port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port,from,len)		outsb(port,from,len)
+#define outsw_p(port,from,len)		outsw(port,from,len)
+#define outsl_p(port,from,len)		outsl(port,from,len)
+#define insb_p(port,to,len)		insb(port,to,len)
+#define insw_p(port,to,len)		insw(port,to,len)
+#define insl_p(port,to,len)		insl(port,to,len)
+
+#define writesl(a, d, s)	__raw_writesl((unsigned long)a, d, s)
+#define readsl(a, d, s)		__raw_readsl((unsigned long)a, d, s)
+#define writesw(a, d, s)	__raw_writesw((unsigned long)a, d, s)
+#define readsw(a, d, s)		__raw_readsw((unsigned long)a, d, s)
+#define writesb(a, d, s)	__raw_writesb((unsigned long)a, d, s)
+#define readsb(a, d, s)		__raw_readsb((unsigned long)a, d, s)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+#define memset_io(a, b, c)		memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)		memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)		memcpy((void *)(a), (b), (c))
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val,addr)		__raw_writeb(val,__mem_isa(addr))
+#define isa_writew(val,addr)		__raw_writew(val,__mem_isa(addr))
+#define isa_writel(val,addr)		__raw_writel(val,__mem_isa(addr))
+#define isa_memset_io(a,b,c)		_memset_io(__mem_isa(a),(b),(c))
+#define isa_memcpy_fromio(a,b,c)	_memcpy_fromio((a),__mem_isa(b),(c))
+#define isa_memcpy_toio(a,b,c)		_memcpy_toio(__mem_isa((a)),(b),(c))
+
+#define isa_eth_io_copy_and_sum(a,b,c,d) \
+				eth_copy_and_sum((a),__mem_isa(b),(c),(d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+		    int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"),0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"),0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"),0)
+#define isa_writeb(val,addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val,addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val,addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a,b,c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a,b,c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a,b,c)		__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a,b,c,d) \
+				__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io,sig,len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+
+#include <asm-generic/io.h>
+#include <iotrace.h>
+
+#endif	/* __ASM_ARM_IO_H */
diff --git a/arch/arm/include/asm/iproc-common/armpll.h b/arch/arm/include/asm/iproc-common/armpll.h
new file mode 100644
index 0000000..f5b60b1
--- /dev/null
+++ b/arch/arm/include/asm/iproc-common/armpll.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#ifndef __ARMPLL_H
+#define __ARMPLL_H
+
+#include <linux/types.h>
+
+uint32_t armpll_config(uint32_t clkmhz);
+
+#endif /*__ARMPLL_H */
diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h
new file mode 100644
index 0000000..96c4f54
--- /dev/null
+++ b/arch/arm/include/asm/iproc-common/configs.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#ifndef __IPROC_COMMON_CONFIGS_H
+#define __IPROC_COMMON_CONFIGS_H
+
+#include <linux/stringify.h>
+
+/* Architecture, CPU, chip, etc */
+#define CONFIG_IPROC
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+
+/* Memory Info */
+#define CONFIG_SYS_SDRAM_BASE		0x61000000
+
+#endif /* __IPROC_COMMON_CONFIGS_H */
diff --git a/arch/arm/include/asm/iproc-common/iproc_sdhci.h b/arch/arm/include/asm/iproc-common/iproc_sdhci.h
new file mode 100644
index 0000000..4e29921
--- /dev/null
+++ b/arch/arm/include/asm/iproc-common/iproc_sdhci.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: <SPDX License Expression> */
+/*
+ * Copyright 2019 Broadcom
+ *
+ */
+
+#ifndef __IPROC_SDHCI_H
+#define __IPROC_SDHCI_H
+
+int iproc_sdhci_init(int dev_index, u32 quirks);
+
+#endif
diff --git a/arch/arm/include/asm/iproc-common/sysmap.h b/arch/arm/include/asm/iproc-common/sysmap.h
new file mode 100644
index 0000000..efd2f35
--- /dev/null
+++ b/arch/arm/include/asm/iproc-common/sysmap.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#ifndef __SYSMAP_H
+#define __SYSMAP_H
+
+#define IHOST_PROC_CLK_PLLARMA					0X19000C00
+#define IHOST_PROC_CLK_PLLARMB					0X19000C04
+#define IHOST_PROC_CLK_PLLARMA__PLLARM_PDIV_R				24
+
+#define IHOST_PROC_CLK_WR_ACCESS				0X19000000
+#define IHOST_PROC_CLK_POLICY_FREQ				0X19000008
+#define IHOST_PROC_CLK_POLICY_FREQ__PRIV_ACCESS_MODE			31
+#define IHOST_PROC_CLK_POLICY_FREQ__POLICY3_FREQ_R			24
+#define IHOST_PROC_CLK_POLICY_FREQ__POLICY2_FREQ_R			16
+#define IHOST_PROC_CLK_POLICY_FREQ__POLICY1_FREQ_R			 8
+#define IHOST_PROC_CLK_POLICY_CTL				0X1900000C
+#define IHOST_PROC_CLK_POLICY_CTL__GO					 0
+#define IHOST_PROC_CLK_POLICY_CTL__GO_AC				 1
+#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R			 0
+#define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH			20
+#define IHOST_PROC_CLK_PLLARMA__PLLARM_LOCK				28
+#define IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R			 0
+#define IHOST_PROC_CLK_PLLARMA__PLLARM_NDIV_INT_R			 8
+#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB			 1
+#define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB			 0
+#define IHOST_PROC_CLK_CORE0_CLKGATE				0X19000200
+#define IHOST_PROC_CLK_CORE1_CLKGATE				0X19000204
+#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE			0X19000210
+#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE			0X19000300
+#define IHOST_PROC_CLK_APB0_CLKGATE				0X19000400
+#define IPROC_CLKCT_HDELAY_SW_EN				0x00000303
+
+#define IPROC_REG_WRITE_ACCESS					0x00a5a501
+
+#define IPROC_PERIPH_BASE					0x19020000
+#define IPROC_PERIPH_INT_CTRL_REG_BASE		(IPROC_PERIPH_BASE +  0x100)
+#define IPROC_PERIPH_GLB_TIM_REG_BASE		(IPROC_PERIPH_BASE +  0x200)
+#define IPROC_PERIPH_PVT_TIM_REG_BASE		(IPROC_PERIPH_BASE +  0x600)
+#define IPROC_PERIPH_INT_DISTR_REG_BASE		(IPROC_PERIPH_BASE + 0x1000)
+
+#define PLL_AXI_CLK						0x1DCD6500
+
+#endif /* __SYSMAP_H */
diff --git a/arch/arm/include/asm/iproc-common/timer.h b/arch/arm/include/asm/iproc-common/timer.h
new file mode 100644
index 0000000..44810c8
--- /dev/null
+++ b/arch/arm/include/asm/iproc-common/timer.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#ifndef __TIMER_H
+#define __TIMER_H
+
+#include <linux/types.h>
+
+void timer_systick_init(uint32_t tick_ms);
+void timer_global_init(void);
+
+/* ARM A9 Private Timer */
+#define TIMER_PVT_LOAD_OFFSET			0x00000000
+#define TIMER_PVT_COUNTER_OFFSET		0x00000004
+#define TIMER_PVT_CTRL_OFFSET			0x00000008
+#define TIMER_PVT_STATUS_OFFSET			0x0000000C
+#define TIMER_PVT_TIM_CTRL_TIM_EN		0x00000001
+#define TIMER_PVT_TIM_CTRL_AUTO_RELD		0x00000002
+#define TIMER_PVT_TIM_CTRL_INT_EN		0x00000004
+#define TIMER_PVT_TIM_CTRL_PRESC_MASK		0x0000FF00
+#define TIMER_PVT_TIM_INT_STATUS_SET		0x00000001
+
+/* Global timer */
+#define TIMER_GLB_LOW_OFFSET			0x00000000
+#define TIMER_GLB_HI_OFFSET			0x00000004
+#define TIMER_GLB_CTRL_OFFSET			0x00000008
+#define TIMER_GLB_TIM_CTRL_TIM_EN		0x00000001
+#define TIMER_GLB_TIM_CTRL_COMP_EN		0x00000002
+#define TIMER_GLB_TIM_CTRL_INT_EN		0x00000004
+#define TIMER_GLB_TIM_CTRL_AUTO_INC		0x00000008
+#define TIMER_GLB_TIM_CTRL_PRESC_MASK		0x0000FF00
+#define TIMER_GLB_TIM_INT_STATUS_SET		0x00000001
+
+#endif /*__TIMER_H */
diff --git a/arch/arm/include/asm/kona-common/clk.h b/arch/arm/include/asm/kona-common/clk.h
new file mode 100644
index 0000000..fded004
--- /dev/null
+++ b/arch/arm/include/asm/kona-common/clk.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+/* This API file is loosely based on u-boot/drivers/video/ipu.h and linux */
+
+#ifndef __KONA_COMMON_CLK_H
+#define __KONA_COMMON_CLK_H
+
+#include <linux/types.h>
+
+struct clk;
+
+/* Only implement required functions for your specific architecture */
+int clk_init(void);
+struct clk *clk_get(const char *id);
+int clk_enable(struct clk *clk);
+void clk_disable(struct clk *clk);
+unsigned long clk_get_rate(struct clk *clk);
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
+int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
+
+#endif
diff --git a/arch/arm/include/asm/kona-common/kona_sdhci.h b/arch/arm/include/asm/kona-common/kona_sdhci.h
new file mode 100644
index 0000000..22db651
--- /dev/null
+++ b/arch/arm/include/asm/kona-common/kona_sdhci.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#ifndef __KONA_SDHCI_H
+#define __KONA_SDHCI_H
+
+int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks);
+
+#endif
diff --git a/arch/arm/include/asm/linkage.h b/arch/arm/include/asm/linkage.h
new file mode 100644
index 0000000..dbe4b4e
--- /dev/null
+++ b/arch/arm/include/asm/linkage.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#define __ALIGN .align 0
+#define __ALIGN_STR ".align 0"
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h b/arch/arm/include/asm/mach-imx/boot_mode.h
new file mode 100644
index 0000000..3a483b6
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ */
+
+#ifndef _ASM_BOOT_MODE_H
+#define _ASM_BOOT_MODE_H
+#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
+	((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
+
+enum boot_device {
+	WEIM_NOR_BOOT,
+	ONE_NAND_BOOT,
+	PATA_BOOT,
+	SATA_BOOT,
+	I2C_BOOT,
+	SPI_NOR_BOOT,
+	SD1_BOOT,
+	SD2_BOOT,
+	SD3_BOOT,
+	SD4_BOOT,
+	MMC1_BOOT,
+	MMC2_BOOT,
+	MMC3_BOOT,
+	MMC4_BOOT,
+	NAND_BOOT,
+	QSPI_BOOT,
+	FLEXSPI_BOOT,
+	USB_BOOT,
+	UNKNOWN_BOOT,
+	BOOT_DEV_NUM = UNKNOWN_BOOT,
+};
+
+/* Boot device type */
+#define BOOT_TYPE_SD		0x1
+#define BOOT_TYPE_MMC		0x2
+#define BOOT_TYPE_NAND		0x3
+#define BOOT_TYPE_QSPI		0x4
+#define BOOT_TYPE_WEIM		0x5
+#define BOOT_TYPE_SPINOR	0x6
+#define BOOT_TYPE_USB		0xF
+
+struct boot_mode {
+	const char *name;
+	unsigned cfg_val;
+};
+
+void add_board_boot_modes(const struct boot_mode *p);
+void boot_mode_apply(unsigned cfg_val);
+extern const struct boot_mode soc_boot_modes[];
+#endif
diff --git a/arch/arm/include/asm/mach-imx/dma.h b/arch/arm/include/asm/mach-imx/dma.h
new file mode 100644
index 0000000..ca70731
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/dma.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 APBH DMA
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __DMA_H__
+#define __DMA_H__
+
+#include <linux/list.h>
+#include <linux/compiler.h>
+
+#define DMA_PIO_WORDS		15
+#define MXS_DMA_ALIGNMENT	ARCH_DMA_MINALIGN
+
+/*
+ * MXS DMA channels
+ */
+#if defined(CONFIG_MX23)
+enum {
+	MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP0,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+	MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+	MXS_MAX_DMA_CHANNELS,
+};
+#elif defined(CONFIG_MX28)
+enum {
+	MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP2,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP3,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+	MXS_DMA_CHANNEL_AHB_APBH_HSADC,
+	MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
+	MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+	MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
+	MXS_MAX_DMA_CHANNELS,
+};
+#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
+enum {
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+	MXS_MAX_DMA_CHANNELS,
+};
+#endif
+
+/*
+ * MXS DMA hardware command.
+ *
+ * This structure describes the in-memory layout of an entire DMA command,
+ * including space for the maximum number of PIO accesses. See the appropriate
+ * reference manual for a detailed description of what these fields mean to the
+ * DMA hardware.
+ */
+#define	MXS_DMA_DESC_COMMAND_MASK	0x3
+#define	MXS_DMA_DESC_COMMAND_OFFSET	0
+#define	MXS_DMA_DESC_COMMAND_NO_DMAXFER	0x0
+#define	MXS_DMA_DESC_COMMAND_DMA_WRITE	0x1
+#define	MXS_DMA_DESC_COMMAND_DMA_READ	0x2
+#define	MXS_DMA_DESC_COMMAND_DMA_SENSE	0x3
+#define	MXS_DMA_DESC_CHAIN		(1 << 2)
+#define	MXS_DMA_DESC_IRQ		(1 << 3)
+#define	MXS_DMA_DESC_NAND_LOCK		(1 << 4)
+#define	MXS_DMA_DESC_NAND_WAIT_4_READY	(1 << 5)
+#define	MXS_DMA_DESC_DEC_SEM		(1 << 6)
+#define	MXS_DMA_DESC_WAIT4END		(1 << 7)
+#define	MXS_DMA_DESC_HALT_ON_TERMINATE	(1 << 8)
+#define	MXS_DMA_DESC_TERMINATE_FLUSH	(1 << 9)
+#define	MXS_DMA_DESC_PIO_WORDS_MASK	(0xf << 12)
+#define	MXS_DMA_DESC_PIO_WORDS_OFFSET	12
+#define	MXS_DMA_DESC_BYTES_MASK		(0xffff << 16)
+#define	MXS_DMA_DESC_BYTES_OFFSET	16
+
+struct mxs_dma_cmd {
+	unsigned long		next;
+	unsigned long		data;
+	union {
+		dma_addr_t	address;
+		unsigned long	alternate;
+	};
+	unsigned long		pio_words[DMA_PIO_WORDS];
+};
+
+/*
+ * MXS DMA command descriptor.
+ *
+ * This structure incorporates an MXS DMA hardware command structure, along
+ * with metadata.
+ */
+#define	MXS_DMA_DESC_FIRST	(1 << 0)
+#define	MXS_DMA_DESC_LAST	(1 << 1)
+#define	MXS_DMA_DESC_READY	(1 << 31)
+
+struct mxs_dma_desc {
+	struct mxs_dma_cmd	cmd;
+	unsigned int		flags;
+	dma_addr_t		address;
+	void			*buffer;
+	struct list_head	node;
+} __aligned(MXS_DMA_ALIGNMENT);
+
+/**
+ * MXS DMA channel
+ *
+ * This structure represents a single DMA channel. The MXS platform code
+ * maintains an array of these structures to represent every DMA channel in the
+ * system (see mxs_dma_channels).
+ */
+#define	MXS_DMA_FLAGS_IDLE	0
+#define	MXS_DMA_FLAGS_BUSY	(1 << 0)
+#define	MXS_DMA_FLAGS_FREE	0
+#define	MXS_DMA_FLAGS_ALLOCATED	(1 << 16)
+#define	MXS_DMA_FLAGS_VALID	(1 << 31)
+
+struct mxs_dma_chan {
+	const char *name;
+	unsigned long dev;
+	struct mxs_dma_device *dma;
+	unsigned int flags;
+	unsigned int active_num;
+	unsigned int pending_num;
+	struct list_head active;
+	struct list_head done;
+};
+
+struct mxs_dma_desc *mxs_dma_desc_alloc(void);
+void mxs_dma_desc_free(struct mxs_dma_desc *);
+int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
+
+int mxs_dma_go(int chan);
+void mxs_dma_init(void);
+int mxs_dma_init_channel(int chan);
+int mxs_dma_release(int chan);
+
+void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);
+
+#endif	/* __DMA_H__ */
diff --git a/arch/arm/include/asm/mach-imx/gpio.h b/arch/arm/include/asm/mach-imx/gpio.h
new file mode 100644
index 0000000..1b7c9cd
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/gpio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ */
+
+
+#ifndef __ASM_ARCH_IMX_GPIO_H
+#define __ASM_ARCH_IMX_GPIO_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/* GPIO registers */
+struct gpio_regs {
+	u32 gpio_dr;	/* data */
+	u32 gpio_dir;	/* direction */
+	u32 gpio_psr;	/* pad satus */
+};
+#endif
+
+#define IMX_GPIO_NR(port, index)		((((port)-1)*32)+((index)&31))
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h
new file mode 100644
index 0000000..d8bd770
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/hab.h
@@ -0,0 +1,208 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+*/
+
+#ifndef __SECURE_MX6Q_H__
+#define __SECURE_MX6Q_H__
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+/*
+ * IVT header definitions
+ * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors,
+ * Rev. 0, 03/2017
+ * Section : 6.7.1.1
+ */
+#define IVT_HEADER_MAGIC	0xD1
+#define IVT_TOTAL_LENGTH	0x20
+#define IVT_HEADER_V1		0x40
+#define IVT_HEADER_V2		0x41
+
+struct __packed ivt_header {
+	uint8_t		magic;
+	uint16_t	length;
+	uint8_t		version;
+};
+
+struct ivt {
+	struct ivt_header hdr;	/* IVT header above */
+	uint32_t entry;		/* Absolute address of first instruction */
+	uint32_t reserved1;	/* Reserved should be zero */
+	uint32_t dcd;		/* Absolute address of the image DCD */
+	uint32_t boot;		/* Absolute address of the boot data */
+	uint32_t self;		/* Absolute address of the IVT */
+	uint32_t csf;		/* Absolute address of the CSF */
+	uint32_t reserved2;	/* Reserved should be zero */
+};
+
+struct __packed hab_hdr {
+	u8 tag;              /* Tag field */
+	u8 len[2];           /* Length field in bytes (big-endian) */
+	u8 par;              /* Parameters field */
+};
+
+/* -------- start of HAB API updates ------------*/
+/* The following are taken from HAB4 SIS */
+
+/* Status definitions */
+enum hab_status {
+	HAB_STS_ANY = 0x00,
+	HAB_FAILURE = 0x33,
+	HAB_WARNING = 0x69,
+	HAB_SUCCESS = 0xf0
+};
+
+/* Security Configuration definitions */
+enum hab_config {
+	HAB_CFG_RETURN = 0x33,	/* < Field Return IC */
+	HAB_CFG_OPEN = 0xf0,	/* < Non-secure IC */
+	HAB_CFG_CLOSED = 0xcc	/* < Secure IC */
+};
+
+/* State definitions */
+enum hab_state {
+	HAB_STATE_INITIAL = 0x33,	/* Initialising state (transitory) */
+	HAB_STATE_CHECK = 0x55,		/* Check state (non-secure) */
+	HAB_STATE_NONSECURE = 0x66,	/* Non-secure state */
+	HAB_STATE_TRUSTED = 0x99,	/* Trusted state */
+	HAB_STATE_SECURE = 0xaa,	/* Secure state */
+	HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */
+	HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */
+	HAB_STATE_NONE = 0xf0,		/* No security state machine */
+	HAB_STATE_MAX
+};
+
+enum hab_reason {
+	HAB_RSN_ANY = 0x00,			/* Match any reason */
+	HAB_ENG_FAIL = 0x30,		/* Engine failure */
+	HAB_INV_ADDRESS = 0x22,		/* Invalid address: access denied */
+	HAB_INV_ASSERTION = 0x0c,   /* Invalid assertion */
+	HAB_INV_CALL = 0x28,		/* Function called out of sequence */
+	HAB_INV_CERTIFICATE = 0x21, /* Invalid certificate */
+	HAB_INV_COMMAND = 0x06,     /* Invalid command: command malformed */
+	HAB_INV_CSF = 0x11,			/* Invalid csf */
+	HAB_INV_DCD = 0x27,			/* Invalid dcd */
+	HAB_INV_INDEX = 0x0f,		/* Invalid index: access denied */
+	HAB_INV_IVT = 0x05,			/* Invalid ivt */
+	HAB_INV_KEY = 0x1d,			/* Invalid key */
+	HAB_INV_RETURN = 0x1e,		/* Failed callback function */
+	HAB_INV_SIGNATURE = 0x18,   /* Invalid signature */
+	HAB_INV_SIZE = 0x17,		/* Invalid data size */
+	HAB_MEM_FAIL = 0x2e,		/* Memory failure */
+	HAB_OVR_COUNT = 0x2b,		/* Expired poll count */
+	HAB_OVR_STORAGE = 0x2d,		/* Exhausted storage region */
+	HAB_UNS_ALGORITHM = 0x12,   /* Unsupported algorithm */
+	HAB_UNS_COMMAND = 0x03,		/* Unsupported command */
+	HAB_UNS_ENGINE = 0x0a,		/* Unsupported engine */
+	HAB_UNS_ITEM = 0x24,		/* Unsupported configuration item */
+	HAB_UNS_KEY = 0x1b,	        /* Unsupported key type/parameters */
+	HAB_UNS_PROTOCOL = 0x14,	/* Unsupported protocol */
+	HAB_UNS_STATE = 0x09,		/* Unsuitable state */
+	HAB_RSN_MAX
+};
+
+enum hab_context {
+	HAB_CTX_ANY = 0x00,			/* Match any context */
+	HAB_CTX_FAB = 0xff,		    /* Event logged in hab_fab_test() */
+	HAB_CTX_ENTRY = 0xe1,		/* Event logged in hab_rvt.entry() */
+	HAB_CTX_TARGET = 0x33,	    /* Event logged in hab_rvt.check_target() */
+	HAB_CTX_AUTHENTICATE = 0x0a,/* Logged in hab_rvt.authenticate_image() */
+	HAB_CTX_DCD = 0xdd,         /* Event logged in hab_rvt.run_dcd() */
+	HAB_CTX_CSF = 0xcf,         /* Event logged in hab_rvt.run_csf() */
+	HAB_CTX_COMMAND = 0xc0,     /* Event logged executing csf/dcd command */
+	HAB_CTX_AUT_DAT = 0xdb,		/* Authenticated data block */
+	HAB_CTX_ASSERT = 0xa0,		/* Event logged in hab_rvt.assert() */
+	HAB_CTX_EXIT = 0xee,		/* Event logged in hab_rvt.exit() */
+	HAB_CTX_MAX
+};
+
+enum hab_target {
+	HAB_TGT_MEMORY		= 0x0f,
+	HAB_TGT_PERIPHERAL	= 0xf0,
+	HAB_TGT_ANY		= 0x55,
+};
+
+struct imx_sec_config_fuse_t {
+	int bank;
+	int word;
+};
+
+#if defined(CONFIG_IMX_HAB)
+extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
+#endif
+
+/*Function prototype description*/
+typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
+		uint8_t* , size_t*);
+typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
+		enum hab_state *);
+typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
+typedef enum hab_status hab_rvt_entry_t(void);
+typedef enum hab_status hab_rvt_exit_t(void);
+typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
+		void **, size_t *, hab_loader_callback_f_t);
+typedef enum hab_status hab_rvt_check_target_t(enum hab_target, const void *,
+					       size_t);
+typedef void hab_rvt_failsafe_t(void);
+typedef void hapi_clock_init_t(void);
+
+#define HAB_ENG_ANY		0x00   /* Select first compatible engine */
+#define HAB_ENG_SCC		0x03   /* Security controller */
+#define HAB_ENG_RTIC	0x05   /* Run-time integrity checker */
+#define HAB_ENG_SAHARA  0x06   /* Crypto accelerator */
+#define HAB_ENG_CSU		0x0a   /* Central Security Unit */
+#define HAB_ENG_SRTC	0x0c   /* Secure clock */
+#define HAB_ENG_DCP		0x1b   /* Data Co-Processor */
+#define HAB_ENG_CAAM	0x1d   /* CAAM */
+#define HAB_ENG_SNVS	0x1e   /* Secure Non-Volatile Storage */
+#define HAB_ENG_OCOTP	0x21   /* Fuse controller */
+#define HAB_ENG_DTCP	0x22   /* DTCP co-processor */
+#define HAB_ENG_ROM		0x36   /* Protected ROM area */
+#define HAB_ENG_HDCP	0x24   /* HDCP co-processor */
+#define HAB_ENG_RTL		0x77   /* RTL simulation engine */
+#define HAB_ENG_SW		0xff   /* Software engine */
+
+#ifdef CONFIG_ROM_UNIFIED_SECTIONS
+#define HAB_RVT_BASE			0x00000100
+#else
+#define HAB_RVT_BASE_NEW		0x00000098
+#define HAB_RVT_BASE_OLD		0x00000094
+#define HAB_RVT_BASE ((is_mx6dqp()) ?					\
+			HAB_RVT_BASE_NEW :				\
+			(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?	\
+			HAB_RVT_BASE_NEW :				\
+			(is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?	\
+			HAB_RVT_BASE_NEW : HAB_RVT_BASE_OLD)
+#endif
+
+#define HAB_RVT_ENTRY			(*(uint32_t *)(HAB_RVT_BASE + 0x04))
+#define HAB_RVT_EXIT			(*(uint32_t *)(HAB_RVT_BASE + 0x08))
+#define HAB_RVT_CHECK_TARGET		(*(uint32_t *)(HAB_RVT_BASE + 0x0C))
+#define HAB_RVT_AUTHENTICATE_IMAGE	(*(uint32_t *)(HAB_RVT_BASE + 0x10))
+#define HAB_RVT_REPORT_EVENT		(*(uint32_t *)(HAB_RVT_BASE + 0x20))
+#define HAB_RVT_REPORT_STATUS		(*(uint32_t *)(HAB_RVT_BASE + 0x24))
+#define HAB_RVT_FAILSAFE		(*(uint32_t *)(HAB_RVT_BASE + 0x28))
+
+#define HAB_CID_ROM 0 /**< ROM Caller ID */
+#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
+
+#define HAB_TAG_RVT          0xDD  /* ROM Vector Table */
+#define HAB_CMD_HDR          0xD4  /* CSF Header */
+#define HAB_CMD_WRT_DAT      0xCC  /* Write Data command tag */
+#define HAB_CMD_CHK_DAT      0xCF  /* Check Data command tag */
+#define HAB_CMD_SET          0xB1  /* Set command tag */
+#define HAB_PAR_MID          0x01  /* MID parameter value */
+
+#define IVT_SIZE			0x20
+#define CSF_PAD_SIZE			0x2000
+
+/* ----------- end of HAB API updates ------------*/
+
+int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
+			       uint32_t ivt_offset);
+bool imx_hab_is_enabled(void);
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/imx-nandbcb.h b/arch/arm/include/asm/mach-imx/imx-nandbcb.h
new file mode 100644
index 0000000..033659a
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/imx-nandbcb.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _IMX_NAND_BCB_H_
+#define _IMX_NAND_BCB_H_
+
+#define FCB_FINGERPRINT		0x20424346      /* 'FCB' */
+#define FCB_VERSION_1		0x01000000
+
+#define DBBT_FINGERPRINT2	0x54424244	/* 'DBBT' */
+#define DBBT_VERSION_1		0x01000000
+
+struct dbbt_block {
+	u32 checksum;	/* reserved on i.MX6 */
+	u32 fingerprint;
+	u32 version;
+	u32 numberbb;	/* reserved on i.MX6 */
+	u32 dbbtpages;
+};
+
+struct fcb_block {
+	u32 checksum;		/* First fingerprint in first byte */
+	u32 fingerprint;	/* 2nd fingerprint at byte 4 */
+	u32 version;		/* 3rd fingerprint at byte 8 */
+	u8 datasetup;
+	u8 datahold;
+	u8 addr_setup;
+	u8 dsample_time;
+
+	/* These are for application use only and not for ROM. */
+	u8 nandtiming;
+	u8 rea;
+	u8 rloh;
+	u8 rhoh;
+	u32 pagesize;		/* 2048 for 2K pages, 4096 for 4K pages */
+	u32 oob_pagesize;	/* 2112 for 2K pages, 4314 for 4K pages */
+	u32 sectors;		/* Number of 2K sections per block */
+	u32 nr_nand;		/* Total Number of NANDs - not used by ROM */
+	u32 nr_die;		/* Number of separate chips in this NAND */
+	u32 celltype;		/* MLC or SLC */
+	u32 ecc_type;		/* Type of ECC, can be one of BCH-0-20 */
+	u32 ecc_nr;		/* Number of bytes for Block0 - BCH */
+
+	/* Block size in bytes for all blocks other than Block0 - BCH */
+	u32 ecc_size;
+	u32 ecc_level;		/* Ecc level for Block 0 - BCH */
+	u32 meta_size;		/* Metadata size - BCH */
+	/* Number of blocks per page for ROM use - BCH */
+	u32 nr_blocks;
+	u32 ecc_type_sdk;	/* Type of ECC, can be one of BCH-0-20 */
+	u32 ecc_nr_sdk;		/* Number of bytes for Block0 - BCH */
+	/* Block size in bytes for all blocks other than Block0 - BCH */
+	u32 ecc_size_sdk;
+	u32 ecc_level_sdk;	/* Ecc level for Block 0 - BCH */
+	/* Number of blocks per page for SDK use - BCH */
+	u32 nr_blocks_sdk;
+	u32 meta_size_sdk;	/* Metadata size - BCH */
+	u32 erase_th;		/* To set into BCH_MODE register */
+
+	/*
+	 * 0: normal boot
+	 * 1: to load patch starting next to FCB
+	 */
+	u32 bootpatch;
+	u32 patch_size;	/* Size of patch in sectors */
+	u32 fw1_start;	/* Firmware image starts on this sector */
+	u32 fw2_start;	/* Secondary FW Image starting Sector */
+	u32 fw1_pages;	/* Number of sectors in firmware image */
+	u32 fw2_pages;	/* Number of sector in secondary FW image */
+	u32 dbbt_start; /* Page address where dbbt search area begins */
+
+	/*
+	 * Byte in page data that have manufacturer marked bad block marker,
+	 * this will be swapped with metadata[0] to complete page data.
+	 */
+	u32 bb_byte;
+
+	/*
+	 * For BCH ECC sizes other than 8 and 16 the bad block marker does not
+	 * start at 0th bit of bb_byte. This field is used to get to
+	 * the start bit of bad block marker byte with in bb_byte
+	 */
+	u32 bb_start_bit;
+
+	/*
+	 * FCB value that gives byte offset for
+	 * bad block marker on physical NAND page
+	 */
+	u32 phy_offset;
+	u32 bchtype;
+
+	u32 readlatency;
+	u32 predelay;
+	u32 cedelay;
+	u32 postdelay;
+	u32 cmdaddpause;
+	u32 datapause;
+	u32 tmspeed;
+	u32 busytimeout;
+
+	/* the flag to enable (1)/disable(0) bi swap */
+	u32 disbbm;
+
+	/* The swap position of main area in spare area */
+	u32 spare_offset;
+};
+
+#endif	/* _IMX_NAND_BCB_H_ */
diff --git a/arch/arm/include/asm/mach-imx/imximage.cfg b/arch/arm/include/asm/mach-imx/imximage.cfg
new file mode 100644
index 0000000..8fbc062
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/imximage.cfg
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * i.MX image header offset values
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ */
+
+/*
+ * NOTE: This file must be kept in sync with tools/imximage.h because
+ *       tools/imximage.c can not cross-include headers from arch/arm/
+ *       and vice-versa.
+ */
+
+#ifndef __ASM_IMX_COMMON_IMXIMAGE_CFG__
+#define __ASM_IMX_COMMON_IMXIMAGE_CFG__
+
+/* Standard image header offset for NAND, SATA, SD, SPI flash. */
+#define FLASH_OFFSET_STANDARD	0x400
+/* Specific image header offset for booting from OneNAND. */
+#define FLASH_OFFSET_ONENAND	0x100
+/* Specific image header offset for booting from memory-mapped NOR. */
+#define FLASH_OFFSET_NOR	0x1000
+
+#endif  /* __ASM_IMX_COMMON_IMXIMAGE_CFG__ */
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
new file mode 100644
index 0000000..720e8f7
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -0,0 +1,301 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on Linux i.MX iomux-v3.h file:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *			<armlinux@phytec.de>
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __MACH_IOMUX_V3_H__
+#define __MACH_IOMUX_V3_H__
+
+#include <common.h>
+
+/*
+ *	build IOMUX_PAD structure
+ *
+ * This iomux scheme is based around pads, which are the physical balls
+ * on the processor.
+ *
+ * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
+ *   things like driving strength and pullup/pulldown.
+ * - Each pad can have but not necessarily does have an output routing register
+ *   (IOMUXC_SW_MUX_CTL_PAD_x).
+ * - Each pad can have but not necessarily does have an input routing register
+ *   (IOMUXC_x_SELECT_INPUT)
+ *
+ * The three register sets do not have a fixed offset to each other,
+ * hence we order this table by pad control registers (which all pads
+ * have) and put the optional i/o routing registers into additional
+ * fields.
+ *
+ * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ *
+ * IOMUX/PAD Bit field definitions
+ *
+ * MUX_CTRL_OFS:	    0..11 (12)
+ * PAD_CTRL_OFS:	   12..23 (12)
+ * SEL_INPUT_OFS:	   24..35 (12)
+ * MUX_MODE + SION + LPSR: 36..41  (6)
+ * PAD_CTRL + NO_PAD_CTRL: 42..59 (18)
+ * SEL_INP:		   60..63  (4)
+*/
+
+typedef u64 iomux_v3_cfg_t;
+
+#define MUX_CTRL_OFS_SHIFT	0
+#define MUX_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
+#define MUX_PAD_CTRL_OFS_SHIFT	12
+#define MUX_PAD_CTRL_OFS_MASK	((iomux_v3_cfg_t)0xfff << \
+	MUX_PAD_CTRL_OFS_SHIFT)
+#define MUX_SEL_INPUT_OFS_SHIFT	24
+#define MUX_SEL_INPUT_OFS_MASK	((iomux_v3_cfg_t)0xfff << \
+	MUX_SEL_INPUT_OFS_SHIFT)
+
+#define MUX_MODE_SHIFT		36
+#define MUX_MODE_MASK		((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL_SHIFT	42
+#define MUX_PAD_CTRL_MASK	((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
+#define MUX_SEL_INPUT_SHIFT	60
+#define MUX_SEL_INPUT_MASK	((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
+
+#define MUX_MODE_SION		((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
+	MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL(x)		((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+
+#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,	\
+		sel_input, pad_ctrl)					\
+	(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT)     |	\
+	((iomux_v3_cfg_t)(mux_mode)      << MUX_MODE_SHIFT)         |	\
+	((iomux_v3_cfg_t)(pad_ctrl_ofs)  << MUX_PAD_CTRL_OFS_SHIFT) |	\
+	((iomux_v3_cfg_t)(pad_ctrl)      << MUX_PAD_CTRL_SHIFT)     |	\
+	((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)|	\
+	((iomux_v3_cfg_t)(sel_input)     << MUX_SEL_INPUT_SHIFT))
+
+#define NEW_PAD_CTRL(cfg, pad)	(((cfg) & ~MUX_PAD_CTRL_MASK) | \
+					MUX_PAD_CTRL(pad))
+
+#define __NA_			0x000
+#define NO_MUX_I		0
+#define NO_PAD_I		0
+
+#define NO_PAD_CTRL		(1 << 17)
+
+#define IOMUX_CONFIG_LPSR       0x20
+#define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
+				MUX_MODE_SHIFT)
+#ifdef CONFIG_IMX8M
+#define PAD_CTL_DSE0		(0x0 << 0)
+#define PAD_CTL_DSE1		(0x1 << 0)
+#define PAD_CTL_DSE2		(0x2 << 0)
+#define PAD_CTL_DSE3		(0x3 << 0)
+#define PAD_CTL_DSE4		(0x4 << 0)
+#define PAD_CTL_DSE5		(0x5 << 0)
+#define PAD_CTL_DSE6		(0x6 << 0)
+#define PAD_CTL_DSE7		(0x7 << 0)
+
+#define PAD_CTL_FSEL0		(0x0 << 3)
+#define PAD_CTL_FSEL1		(0x1 << 3)
+#define PAD_CTL_FSEL2		(0x2 << 3)
+#define PAD_CTL_FSEL3		(0x3 << 3)
+
+#define PAD_CTL_ODE		(0x1 << 5)
+#define PAD_CTL_PUE		(0x1 << 6)
+#define PAD_CTL_HYS		(0x1 << 7)
+#ifdef CONFIG_IMX8MM
+#define PAD_CTL_PE		(0x1 << 8)
+#else
+#define PAD_CTL_LVTTL		(0x1 << 8)
+#endif
+
+#elif defined CONFIG_MX7
+
+#define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
+
+#define PAD_CTL_DSE_1P8V_140OHM   (0x0<<0)
+#define PAD_CTL_DSE_1P8V_35OHM    (0x1<<0)
+#define PAD_CTL_DSE_1P8V_70OHM    (0x2<<0)
+#define PAD_CTL_DSE_1P8V_23OHM    (0x3<<0)
+
+#define PAD_CTL_DSE_3P3V_196OHM   (0x0<<0)
+#define PAD_CTL_DSE_3P3V_49OHM    (0x1<<0)
+#define PAD_CTL_DSE_3P3V_98OHM    (0x2<<0)
+#define PAD_CTL_DSE_3P3V_32OHM    (0x3<<0)
+
+#define PAD_CTL_SRE_FAST     (0 << 2)
+#define PAD_CTL_SRE_SLOW     (0x1 << 2)
+
+#define PAD_CTL_HYS       (0x1 << 3)
+#define PAD_CTL_PUE       (0x1 << 4)
+
+#define PAD_CTL_PUS_PD100KOHM  ((0x0 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU5KOHM    ((0x1 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU47KOHM   ((0x2 << 5) | PAD_CTL_PUE)
+#define PAD_CTL_PUS_PU100KOHM  ((0x3 << 5) | PAD_CTL_PUE)
+
+#else
+
+#ifdef CONFIG_MX6
+
+#define PAD_CTL_HYS		(1 << 16)
+
+#define PAD_CTL_PUS_100K_DOWN	(0 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP	(1 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP	(2 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP	(3 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUE		(1 << 13 | PAD_CTL_PKE)
+#define PAD_CTL_PKE		(1 << 12)
+
+#define PAD_CTL_ODE		(1 << 11)
+
+#if defined(CONFIG_MX6SL)
+#define PAD_CTL_SPEED_LOW	(1 << 6)
+#else
+#define PAD_CTL_SPEED_LOW	(0 << 6)
+#endif
+#define PAD_CTL_SPEED_MED	(2 << 6)
+#define PAD_CTL_SPEED_HIGH	(3 << 6)
+
+#define PAD_CTL_DSE_DISABLE	(0 << 3)
+#define PAD_CTL_DSE_240ohm	(1 << 3)
+#define PAD_CTL_DSE_120ohm	(2 << 3)
+#define PAD_CTL_DSE_80ohm	(3 << 3)
+#define PAD_CTL_DSE_60ohm	(4 << 3)
+#define PAD_CTL_DSE_48ohm	(5 << 3)
+#define PAD_CTL_DSE_40ohm	(6 << 3)
+#define PAD_CTL_DSE_34ohm	(7 << 3)
+
+#define PAD_CTL_DSE_260ohm	(1 << 3)
+#define PAD_CTL_DSE_130ohm	(2 << 3)
+#define PAD_CTL_DSE_88ohm	(3 << 3)
+#define PAD_CTL_DSE_65ohm	(4 << 3)
+#define PAD_CTL_DSE_52ohm	(5 << 3)
+#define PAD_CTL_DSE_43ohm	(6 << 3)
+#define PAD_CTL_DSE_37ohm	(7 << 3)
+
+/* i.MX6SL/SLL */
+#define PAD_CTL_LVE		(1 << 1)
+#define PAD_CTL_LVE_BIT		(1 << 22)
+
+/* i.MX6SLL */
+#define PAD_CTL_IPD_BIT		(1 << 27)
+
+#elif defined(CONFIG_VF610)
+
+#define PAD_MUX_MODE_SHIFT	20
+
+#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
+
+#define PAD_CTL_SPEED_MED	(1 << 12)
+#define PAD_CTL_SPEED_HIGH	(3 << 12)
+
+#define PAD_CTL_SRE		(1 << 11)
+
+#define PAD_CTL_ODE		(1 << 10)
+
+#define PAD_CTL_DSE_150ohm	(1 << 6)
+#define PAD_CTL_DSE_75ohm	(2 << 6)
+#define PAD_CTL_DSE_50ohm	(3 << 6)
+#define PAD_CTL_DSE_37ohm	(4 << 6)
+#define PAD_CTL_DSE_30ohm	(5 << 6)
+#define PAD_CTL_DSE_25ohm	(6 << 6)
+#define PAD_CTL_DSE_20ohm	(7 << 6)
+
+#define PAD_CTL_PUS_47K_UP	(1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP	(2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP	(3 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PKE		(1 << 3)
+#define PAD_CTL_PUE		(1 << 2 | PAD_CTL_PKE)
+
+#define PAD_CTL_OBE_IBE_ENABLE	(3 << 0)
+#define PAD_CTL_OBE_ENABLE	(1 << 1)
+#define PAD_CTL_IBE_ENABLE	(1 << 0)
+
+#else
+
+#define PAD_CTL_DVS		(1 << 13)
+#define PAD_CTL_INPUT_DDR	(1 << 9)
+#define PAD_CTL_HYS		(1 << 8)
+
+#define PAD_CTL_PKE		(1 << 7)
+#define PAD_CTL_PUE		(1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN	(0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP	(1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP	(2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP	(3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE		(1 << 3)
+
+#define PAD_CTL_DSE_LOW		(0 << 1)
+#define PAD_CTL_DSE_MED		(1 << 1)
+#define PAD_CTL_DSE_HIGH	(2 << 1)
+#define PAD_CTL_DSE_MAX		(3 << 1)
+
+#endif
+
+#define PAD_CTL_SRE_SLOW	(0 << 0)
+#define PAD_CTL_SRE_FAST	(1 << 0)
+
+#endif
+
+#define IOMUX_CONFIG_SION	0x10
+
+#define GPIO_PIN_MASK		0x1f
+#define GPIO_PORT_SHIFT		5
+#define GPIO_PORT_MASK		(0x7 << GPIO_PORT_SHIFT)
+#define GPIO_PORTA		(0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB		(1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC		(2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD		(3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE		(4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF		(5 << GPIO_PORT_SHIFT)
+
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+				     unsigned count);
+/*
+* Set bits for general purpose registers
+*/
+void imx_iomux_set_gpr_register(int group, int start_bit,
+					 int num_bits, int value);
+#ifdef CONFIG_IOMUX_SHARE_CONF_REG
+void imx_iomux_gpio_set_direction(unsigned int gpio,
+				unsigned int direction);
+void imx_iomux_gpio_get_function(unsigned int gpio,
+				u32 *gpio_state);
+#endif
+
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def)					\
+if (is_mx6dq() || is_mx6dqp()) {				\
+	imx_iomux_v3_setup_pad(MX6Q_##def);			\
+} else {							\
+	imx_iomux_v3_setup_pad(MX6DL_##def);			\
+}
+#define SETUP_IOMUX_PADS(x)					\
+	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def)					\
+	imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x)					\
+	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#define IOMUX_PADS(x) MX6_##x
+#define SETUP_IOMUX_PAD(def)					\
+	imx_iomux_v3_setup_pad(MX6_##def);
+#define SETUP_IOMUX_PADS(x)					\
+	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def)					\
+	imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x)					\
+	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
+
+#endif	/* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/include/asm/mach-imx/mx5_video.h b/arch/arm/include/asm/mach-imx/mx5_video.h
new file mode 100644
index 0000000..dc6aa00
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/mx5_video.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012
+ * Anatolij Gustschin, DENX Software Engineering, <agust@denx.de>
+ */
+#ifndef __MX5_VIDEO_H
+#define __MX5_VIDEO_H
+
+#ifdef CONFIG_VIDEO
+void lcd_enable(void);
+void setup_iomux_lcd(void);
+#else
+static inline void lcd_enable(void) { }
+static inline void setup_iomux_lcd(void) { }
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/mxc_i2c.h b/arch/arm/include/asm/mach-imx/mxc_i2c.h
new file mode 100644
index 0000000..81fd981
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/mxc_i2c.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+#ifndef __ASM_ARCH_MXC_MXC_I2C_H__
+#define __ASM_ARCH_MXC_MXC_I2C_H__
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#if CONFIG_IS_ENABLED(CLK)
+#include <clk.h>
+#endif
+
+struct i2c_pin_ctrl {
+	iomux_v3_cfg_t i2c_mode;
+	iomux_v3_cfg_t gpio_mode;
+	unsigned char gp;
+	unsigned char spare;
+};
+
+struct i2c_pads_info {
+	struct i2c_pin_ctrl scl;
+	struct i2c_pin_ctrl sda;
+};
+
+/*
+ * Information about i2c controller
+ * struct mxc_i2c_bus - information about the i2c[x] bus
+ * @index: i2c bus index
+ * @base: Address of I2C bus controller
+ * @driver_data: Flags for different platforms, such as I2C_QUIRK_FLAG.
+ * @speed: Speed of I2C bus
+ * @pads_info: pinctrl info for this i2c bus, will be used when pinctrl is ok.
+ * The following two is only to be compatible with non-DM part.
+ * @idle_bus_fn: function to force bus idle
+ * @idle_bus_data: parameter for idle_bus_fun
+ * For DM:
+ * bus: The device structure for i2c bus controller
+ * scl-gpio: specify the gpio related to SCL pin
+ * sda-gpio: specify the gpio related to SDA pin
+ */
+struct mxc_i2c_bus {
+	/*
+	 * board file can use this index to locate which i2c_pads_info is for
+	 * i2c_idle_bus. When pinmux is implement, this entry can be
+	 * discarded. Here we do not use dev->seq, because we do not want to
+	 * export device to board file.
+	 */
+	int index;
+	ulong base;
+	ulong driver_data;
+	int speed;
+	struct i2c_pads_info *pads_info;
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk per_clk;
+#endif
+#ifndef CONFIG_DM_I2C
+	int (*idle_bus_fn)(void *p);
+	void *idle_bus_data;
+#else
+	struct udevice *bus;
+	/* Use gpio to force bus idle when bus state is abnormal */
+	struct gpio_desc scl_gpio;
+	struct gpio_desc sda_gpio;
+#endif
+};
+
+#if defined(CONFIG_MX6QDL)
+#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
+	struct i2c_pads_info mx6q_##name = {		\
+		.scl = {				\
+			.i2c_mode = MX6Q_##scl_i2c,	\
+			.gpio_mode = MX6Q_##scl_gpio,	\
+			.gp = scl_gp,			\
+		},					\
+		.sda = {				\
+			.i2c_mode = MX6Q_##sda_i2c,	\
+			.gpio_mode = MX6Q_##sda_gpio,	\
+			.gp = sda_gp,			\
+		}					\
+	};						\
+	struct i2c_pads_info mx6s_##name = {		\
+		.scl = {				\
+			.i2c_mode = MX6DL_##scl_i2c,	\
+			.gpio_mode = MX6DL_##scl_gpio,	\
+			.gp = scl_gp,			\
+		},					\
+		.sda = {				\
+			.i2c_mode = MX6DL_##sda_i2c,	\
+			.gpio_mode = MX6DL_##sda_gpio,	\
+			.gp = sda_gp,			\
+		}					\
+	};
+
+
+#define I2C_PADS_INFO(name)	\
+	(is_mx6dq() || is_mx6dqp()) ? &mx6q_##name : &mx6s_##name
+#endif
+
+int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
+	      struct i2c_pads_info *p);
+void bus_i2c_init(int index, int speed, int slave_addr,
+		int (*idle_bus_fn)(void *p), void *p);
+int force_idle_bus(void *priv);
+int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus);
+#endif
diff --git a/arch/arm/include/asm/mach-imx/rdc-sema.h b/arch/arm/include/asm/mach-imx/rdc-sema.h
new file mode 100644
index 0000000..70d6a76
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/rdc-sema.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __RDC_SEMA_H__
+#define __RDC_SEMA_H__
+
+/*
+ * rdc_peri_cfg_t and rdc_ma_cft_t use the same layout.
+ *
+ *   [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]
+ *      d3      d2      d1       d0    | master id  |  peri id
+ *   d[x] means domain[x], x can be [3 - 0].
+ */
+typedef u32 rdc_peri_cfg_t;
+typedef u32 rdc_ma_cfg_t;
+
+#define RDC_PERI_SHIFT		0
+#define RDC_PERI_MASK		0xFF
+
+#define RDC_DOMAIN_SHIFT_BASE	16
+#define RDC_DOMAIN_MASK		0xFF0000
+#define RDC_DOMAIN_SHIFT(x)	(RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
+#define RDC_DOMAIN(x)		((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
+
+#define RDC_MASTER_SHIFT	8
+#define RDC_MASTER_MASK		0xFF00
+#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \
+					(domain_id << RDC_DOMAIN_SHIFT_BASE))
+
+/* The Following macro definitions are common to i.MX6SX and i.MX7D */
+#define SEMA_GATES_NUM		64
+
+#define RDC_MDA_DID_SHIFT	0
+#define RDC_MDA_DID_MASK	(0x3 << RDC_MDA_DID_SHIFT)
+#define RDC_MDA_LCK_SHIFT	31
+#define RDC_MDA_LCK_MASK	(0x1 << RDC_MDA_LCK_SHIFT)
+
+#define RDC_PDAP_DW_SHIFT(domain)	((domain) << 1)
+#define RDC_PDAP_DR_SHIFT(domain)	(1 + RDC_PDAP_DW_SHIFT(domain))
+#define RDC_PDAP_DW_MASK(domain)	(1 << RDC_PDAP_DW_SHIFT(domain))
+#define RDC_PDAP_DR_MASK(domain)	(1 << RDC_PDAP_DR_SHIFT(domain))
+#define RDC_PDAP_DRW_MASK(domain)	(RDC_PDAP_DW_MASK(domain) | \
+					 RDC_PDAP_DR_MASK(domain))
+
+#define RDC_PDAP_SREQ_SHIFT	30
+#define RDC_PDAP_SREQ_MASK	(0x1 << RDC_PDAP_SREQ_SHIFT)
+#define RDC_PDAP_LCK_SHIFT	31
+#define RDC_PDAP_LCK_MASK	(0x1 << RDC_PDAP_LCK_SHIFT)
+
+#define RDC_MRSA_SADR_SHIFT	7
+#define RDC_MRSA_SADR_MASK	(0x1ffffff << RDC_MRSA_SADR_SHIFT)
+
+#define RDC_MREA_EADR_SHIFT	7
+#define RDC_MREA_EADR_MASK	(0x1ffffff << RDC_MREA_EADR_SHIFT)
+
+#define RDC_MRC_DW_SHIFT(domain)	(domain)
+#define RDC_MRC_DR_SHIFT(domain)	(1 + RDC_MRC_DW_SHIFT(domain))
+#define RDC_MRC_DW_MASK(domain)		(1 << RDC_MRC_DW_SHIFT(domain))
+#define RDC_MRC_DR_MASK(domain)		(1 << RDC_MRC_DR_SHIFT(domain))
+#define RDC_MRC_DRW_MASK(domain)	(RDC_MRC_DW_MASK(domain) | \
+					 RDC_MRC_DR_MASK(domain))
+#define RDC_MRC_ENA_SHIFT	30
+#define RDC_MRC_ENA_MASK	(0x1 << RDC_MRC_ENA_SHIFT)
+#define RDC_MRC_LCK_SHIFT	31
+#define RDC_MRC_LCK_MASK	(0x1 << RDC_MRC_LCK_SHIFT)
+
+#define RDC_MRVS_VDID_SHIFT	0
+#define RDC_MRVS_VDID_MASK	(0x3 << RDC_MRVS_VDID_SHIFT)
+#define RDC_MRVS_AD_SHIFT	4
+#define RDC_MRVS_AD_MASK	(0x1 << RDC_MRVS_AD_SHIFT)
+#define RDC_MRVS_VADDR_SHIFT	5
+#define RDC_MRVS_VADDR_MASK	(0x7ffffff << RDC_MRVS_VADDR_SHIFT)
+
+#define RDC_SEMA_GATE_GTFSM_SHIFT	0
+#define RDC_SEMA_GATE_GTFSM_MASK	(0xf << RDC_SEMA_GATE_GTFSM_SHIFT)
+#define RDC_SEMA_GATE_LDOM_SHIFT	5
+#define RDC_SEMA_GATE_LDOM_MASK		(0x3 << RDC_SEMA_GATE_LDOM_SHIFT)
+
+#define RDC_SEMA_RSTGT_RSTGDP_SHIFT	0
+#define RDC_SEMA_RSTGT_RSTGDP_MASK	(0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT)
+#define RDC_SEMA_RSTGT_RSTGSM_SHIFT	2
+#define RDC_SEMA_RSTGT_RSTGSM_MASK	(0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT)
+#define RDC_SEMA_RSTGT_RSTGMS_SHIFT	4
+#define RDC_SEMA_RSTGT_RSTGMS_MASK	(0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT)
+#define RDC_SEMA_RSTGT_RSTGTN_SHIFT	8
+#define RDC_SEMA_RSTGT_RSTGTN_MASK	(0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)
+
+int imx_rdc_check_permission(int per_id, int dom_id);
+int imx_rdc_sema_lock(int per_id);
+int imx_rdc_sema_unlock(int per_id);
+int imx_rdc_setup_peri(rdc_peri_cfg_t p);
+int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
+			      unsigned count);
+int imx_rdc_setup_ma(rdc_ma_cfg_t p);
+int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);
+
+#endif	/* __RDC_SEMA_H__*/
diff --git a/arch/arm/include/asm/mach-imx/regs-apbh.h b/arch/arm/include/asm/mach-imx/regs-apbh.h
new file mode 100644
index 0000000..d7baf13
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/regs-apbh.h
@@ -0,0 +1,588 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 APBH Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __REGS_APBH_H__
+#define __REGS_APBH_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+
+#if defined(CONFIG_MX23)
+struct mxs_apbh_regs {
+	mxs_reg_32(hw_apbh_ctrl0)
+	mxs_reg_32(hw_apbh_ctrl1)
+	mxs_reg_32(hw_apbh_ctrl2)
+	mxs_reg_32(hw_apbh_channel_ctrl)
+
+	union {
+	struct {
+		mxs_reg_32(hw_apbh_ch_curcmdar)
+		mxs_reg_32(hw_apbh_ch_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch_cmd)
+		mxs_reg_32(hw_apbh_ch_bar)
+		mxs_reg_32(hw_apbh_ch_sema)
+		mxs_reg_32(hw_apbh_ch_debug1)
+		mxs_reg_32(hw_apbh_ch_debug2)
+	} ch[8];
+	struct {
+		mxs_reg_32(hw_apbh_ch0_curcmdar)
+		mxs_reg_32(hw_apbh_ch0_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch0_cmd)
+		mxs_reg_32(hw_apbh_ch0_bar)
+		mxs_reg_32(hw_apbh_ch0_sema)
+		mxs_reg_32(hw_apbh_ch0_debug1)
+		mxs_reg_32(hw_apbh_ch0_debug2)
+		mxs_reg_32(hw_apbh_ch1_curcmdar)
+		mxs_reg_32(hw_apbh_ch1_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch1_cmd)
+		mxs_reg_32(hw_apbh_ch1_bar)
+		mxs_reg_32(hw_apbh_ch1_sema)
+		mxs_reg_32(hw_apbh_ch1_debug1)
+		mxs_reg_32(hw_apbh_ch1_debug2)
+		mxs_reg_32(hw_apbh_ch2_curcmdar)
+		mxs_reg_32(hw_apbh_ch2_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch2_cmd)
+		mxs_reg_32(hw_apbh_ch2_bar)
+		mxs_reg_32(hw_apbh_ch2_sema)
+		mxs_reg_32(hw_apbh_ch2_debug1)
+		mxs_reg_32(hw_apbh_ch2_debug2)
+		mxs_reg_32(hw_apbh_ch3_curcmdar)
+		mxs_reg_32(hw_apbh_ch3_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch3_cmd)
+		mxs_reg_32(hw_apbh_ch3_bar)
+		mxs_reg_32(hw_apbh_ch3_sema)
+		mxs_reg_32(hw_apbh_ch3_debug1)
+		mxs_reg_32(hw_apbh_ch3_debug2)
+		mxs_reg_32(hw_apbh_ch4_curcmdar)
+		mxs_reg_32(hw_apbh_ch4_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch4_cmd)
+		mxs_reg_32(hw_apbh_ch4_bar)
+		mxs_reg_32(hw_apbh_ch4_sema)
+		mxs_reg_32(hw_apbh_ch4_debug1)
+		mxs_reg_32(hw_apbh_ch4_debug2)
+		mxs_reg_32(hw_apbh_ch5_curcmdar)
+		mxs_reg_32(hw_apbh_ch5_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch5_cmd)
+		mxs_reg_32(hw_apbh_ch5_bar)
+		mxs_reg_32(hw_apbh_ch5_sema)
+		mxs_reg_32(hw_apbh_ch5_debug1)
+		mxs_reg_32(hw_apbh_ch5_debug2)
+		mxs_reg_32(hw_apbh_ch6_curcmdar)
+		mxs_reg_32(hw_apbh_ch6_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch6_cmd)
+		mxs_reg_32(hw_apbh_ch6_bar)
+		mxs_reg_32(hw_apbh_ch6_sema)
+		mxs_reg_32(hw_apbh_ch6_debug1)
+		mxs_reg_32(hw_apbh_ch6_debug2)
+		mxs_reg_32(hw_apbh_ch7_curcmdar)
+		mxs_reg_32(hw_apbh_ch7_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch7_cmd)
+		mxs_reg_32(hw_apbh_ch7_bar)
+		mxs_reg_32(hw_apbh_ch7_sema)
+		mxs_reg_32(hw_apbh_ch7_debug1)
+		mxs_reg_32(hw_apbh_ch7_debug2)
+	};
+	};
+	mxs_reg_32(hw_apbh_version)
+};
+
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
+struct mxs_apbh_regs {
+	mxs_reg_32(hw_apbh_ctrl0)
+	mxs_reg_32(hw_apbh_ctrl1)
+	mxs_reg_32(hw_apbh_ctrl2)
+	mxs_reg_32(hw_apbh_channel_ctrl)
+	mxs_reg_32(hw_apbh_devsel)
+	mxs_reg_32(hw_apbh_dma_burst_size)
+	mxs_reg_32(hw_apbh_debug)
+
+	uint32_t	reserved[36];
+
+	union {
+	struct {
+		mxs_reg_32(hw_apbh_ch_curcmdar)
+		mxs_reg_32(hw_apbh_ch_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch_cmd)
+		mxs_reg_32(hw_apbh_ch_bar)
+		mxs_reg_32(hw_apbh_ch_sema)
+		mxs_reg_32(hw_apbh_ch_debug1)
+		mxs_reg_32(hw_apbh_ch_debug2)
+	} ch[16];
+	struct {
+		mxs_reg_32(hw_apbh_ch0_curcmdar)
+		mxs_reg_32(hw_apbh_ch0_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch0_cmd)
+		mxs_reg_32(hw_apbh_ch0_bar)
+		mxs_reg_32(hw_apbh_ch0_sema)
+		mxs_reg_32(hw_apbh_ch0_debug1)
+		mxs_reg_32(hw_apbh_ch0_debug2)
+		mxs_reg_32(hw_apbh_ch1_curcmdar)
+		mxs_reg_32(hw_apbh_ch1_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch1_cmd)
+		mxs_reg_32(hw_apbh_ch1_bar)
+		mxs_reg_32(hw_apbh_ch1_sema)
+		mxs_reg_32(hw_apbh_ch1_debug1)
+		mxs_reg_32(hw_apbh_ch1_debug2)
+		mxs_reg_32(hw_apbh_ch2_curcmdar)
+		mxs_reg_32(hw_apbh_ch2_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch2_cmd)
+		mxs_reg_32(hw_apbh_ch2_bar)
+		mxs_reg_32(hw_apbh_ch2_sema)
+		mxs_reg_32(hw_apbh_ch2_debug1)
+		mxs_reg_32(hw_apbh_ch2_debug2)
+		mxs_reg_32(hw_apbh_ch3_curcmdar)
+		mxs_reg_32(hw_apbh_ch3_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch3_cmd)
+		mxs_reg_32(hw_apbh_ch3_bar)
+		mxs_reg_32(hw_apbh_ch3_sema)
+		mxs_reg_32(hw_apbh_ch3_debug1)
+		mxs_reg_32(hw_apbh_ch3_debug2)
+		mxs_reg_32(hw_apbh_ch4_curcmdar)
+		mxs_reg_32(hw_apbh_ch4_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch4_cmd)
+		mxs_reg_32(hw_apbh_ch4_bar)
+		mxs_reg_32(hw_apbh_ch4_sema)
+		mxs_reg_32(hw_apbh_ch4_debug1)
+		mxs_reg_32(hw_apbh_ch4_debug2)
+		mxs_reg_32(hw_apbh_ch5_curcmdar)
+		mxs_reg_32(hw_apbh_ch5_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch5_cmd)
+		mxs_reg_32(hw_apbh_ch5_bar)
+		mxs_reg_32(hw_apbh_ch5_sema)
+		mxs_reg_32(hw_apbh_ch5_debug1)
+		mxs_reg_32(hw_apbh_ch5_debug2)
+		mxs_reg_32(hw_apbh_ch6_curcmdar)
+		mxs_reg_32(hw_apbh_ch6_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch6_cmd)
+		mxs_reg_32(hw_apbh_ch6_bar)
+		mxs_reg_32(hw_apbh_ch6_sema)
+		mxs_reg_32(hw_apbh_ch6_debug1)
+		mxs_reg_32(hw_apbh_ch6_debug2)
+		mxs_reg_32(hw_apbh_ch7_curcmdar)
+		mxs_reg_32(hw_apbh_ch7_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch7_cmd)
+		mxs_reg_32(hw_apbh_ch7_bar)
+		mxs_reg_32(hw_apbh_ch7_sema)
+		mxs_reg_32(hw_apbh_ch7_debug1)
+		mxs_reg_32(hw_apbh_ch7_debug2)
+		mxs_reg_32(hw_apbh_ch8_curcmdar)
+		mxs_reg_32(hw_apbh_ch8_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch8_cmd)
+		mxs_reg_32(hw_apbh_ch8_bar)
+		mxs_reg_32(hw_apbh_ch8_sema)
+		mxs_reg_32(hw_apbh_ch8_debug1)
+		mxs_reg_32(hw_apbh_ch8_debug2)
+		mxs_reg_32(hw_apbh_ch9_curcmdar)
+		mxs_reg_32(hw_apbh_ch9_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch9_cmd)
+		mxs_reg_32(hw_apbh_ch9_bar)
+		mxs_reg_32(hw_apbh_ch9_sema)
+		mxs_reg_32(hw_apbh_ch9_debug1)
+		mxs_reg_32(hw_apbh_ch9_debug2)
+		mxs_reg_32(hw_apbh_ch10_curcmdar)
+		mxs_reg_32(hw_apbh_ch10_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch10_cmd)
+		mxs_reg_32(hw_apbh_ch10_bar)
+		mxs_reg_32(hw_apbh_ch10_sema)
+		mxs_reg_32(hw_apbh_ch10_debug1)
+		mxs_reg_32(hw_apbh_ch10_debug2)
+		mxs_reg_32(hw_apbh_ch11_curcmdar)
+		mxs_reg_32(hw_apbh_ch11_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch11_cmd)
+		mxs_reg_32(hw_apbh_ch11_bar)
+		mxs_reg_32(hw_apbh_ch11_sema)
+		mxs_reg_32(hw_apbh_ch11_debug1)
+		mxs_reg_32(hw_apbh_ch11_debug2)
+		mxs_reg_32(hw_apbh_ch12_curcmdar)
+		mxs_reg_32(hw_apbh_ch12_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch12_cmd)
+		mxs_reg_32(hw_apbh_ch12_bar)
+		mxs_reg_32(hw_apbh_ch12_sema)
+		mxs_reg_32(hw_apbh_ch12_debug1)
+		mxs_reg_32(hw_apbh_ch12_debug2)
+		mxs_reg_32(hw_apbh_ch13_curcmdar)
+		mxs_reg_32(hw_apbh_ch13_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch13_cmd)
+		mxs_reg_32(hw_apbh_ch13_bar)
+		mxs_reg_32(hw_apbh_ch13_sema)
+		mxs_reg_32(hw_apbh_ch13_debug1)
+		mxs_reg_32(hw_apbh_ch13_debug2)
+		mxs_reg_32(hw_apbh_ch14_curcmdar)
+		mxs_reg_32(hw_apbh_ch14_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch14_cmd)
+		mxs_reg_32(hw_apbh_ch14_bar)
+		mxs_reg_32(hw_apbh_ch14_sema)
+		mxs_reg_32(hw_apbh_ch14_debug1)
+		mxs_reg_32(hw_apbh_ch14_debug2)
+		mxs_reg_32(hw_apbh_ch15_curcmdar)
+		mxs_reg_32(hw_apbh_ch15_nxtcmdar)
+		mxs_reg_32(hw_apbh_ch15_cmd)
+		mxs_reg_32(hw_apbh_ch15_bar)
+		mxs_reg_32(hw_apbh_ch15_sema)
+		mxs_reg_32(hw_apbh_ch15_debug1)
+		mxs_reg_32(hw_apbh_ch15_debug2)
+	};
+	};
+	mxs_reg_32(hw_apbh_version)
+};
+#endif
+
+#endif
+
+#define	APBH_CTRL0_SFTRST				(1 << 31)
+#define	APBH_CTRL0_CLKGATE				(1 << 30)
+#define	APBH_CTRL0_AHB_BURST8_EN			(1 << 29)
+#define	APBH_CTRL0_APB_BURST_EN				(1 << 28)
+#if defined(CONFIG_MX23)
+#define	APBH_CTRL0_RSVD0_MASK				(0xf << 24)
+#define	APBH_CTRL0_RSVD0_OFFSET				24
+#define	APBH_CTRL0_RESET_CHANNEL_MASK			(0xff << 16)
+#define	APBH_CTRL0_RESET_CHANNEL_OFFSET			16
+#define	APBH_CTRL0_CLKGATE_CHANNEL_MASK			(0xff << 8)
+#define	APBH_CTRL0_CLKGATE_CHANNEL_OFFSET		8
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP0			0x02
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP1			0x04
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND0		0x10
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND1		0x20
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND2		0x40
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND3		0x80
+#elif defined(CONFIG_MX28)
+#define	APBH_CTRL0_RSVD0_MASK				(0xfff << 16)
+#define	APBH_CTRL0_RSVD0_OFFSET				16
+#define	APBH_CTRL0_CLKGATE_CHANNEL_MASK			0xffff
+#define	APBH_CTRL0_CLKGATE_CHANNEL_OFFSET		0
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP0			0x0001
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP1			0x0002
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP2			0x0004
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP3			0x0008
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND0		0x0010
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND1		0x0020
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND2		0x0040
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND3		0x0080
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND4		0x0100
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND5		0x0200
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND6		0x0400
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND7		0x0800
+#define	APBH_CTRL0_CLKGATE_CHANNEL_HSADC		0x1000
+#define	APBH_CTRL0_CLKGATE_CHANNEL_LCDIF		0x2000
+#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#define	APBH_CTRL0_CLKGATE_CHANNEL_OFFSET		0
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND0		0x0001
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND1		0x0002
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND2		0x0004
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND3		0x0008
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND4		0x0010
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND5		0x0020
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND6		0x0040
+#define	APBH_CTRL0_CLKGATE_CHANNEL_NAND7		0x0080
+#define	APBH_CTRL0_CLKGATE_CHANNEL_SSP			0x0100
+#endif
+
+#define	APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN			(1 << 31)
+#define	APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN			(1 << 30)
+#define	APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN			(1 << 29)
+#define	APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN			(1 << 28)
+#define	APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN			(1 << 27)
+#define	APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN			(1 << 26)
+#define	APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN			(1 << 25)
+#define	APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN			(1 << 24)
+#define	APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN			(1 << 23)
+#define	APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN			(1 << 22)
+#define	APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN			(1 << 21)
+#define	APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN			(1 << 20)
+#define	APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN			(1 << 19)
+#define	APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN			(1 << 18)
+#define	APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN			(1 << 17)
+#define	APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN			(1 << 16)
+#define	APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET		16
+#define	APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK		(0xffff << 16)
+#define	APBH_CTRL1_CH15_CMDCMPLT_IRQ			(1 << 15)
+#define	APBH_CTRL1_CH14_CMDCMPLT_IRQ			(1 << 14)
+#define	APBH_CTRL1_CH13_CMDCMPLT_IRQ			(1 << 13)
+#define	APBH_CTRL1_CH12_CMDCMPLT_IRQ			(1 << 12)
+#define	APBH_CTRL1_CH11_CMDCMPLT_IRQ			(1 << 11)
+#define	APBH_CTRL1_CH10_CMDCMPLT_IRQ			(1 << 10)
+#define	APBH_CTRL1_CH9_CMDCMPLT_IRQ			(1 << 9)
+#define	APBH_CTRL1_CH8_CMDCMPLT_IRQ			(1 << 8)
+#define	APBH_CTRL1_CH7_CMDCMPLT_IRQ			(1 << 7)
+#define	APBH_CTRL1_CH6_CMDCMPLT_IRQ			(1 << 6)
+#define	APBH_CTRL1_CH5_CMDCMPLT_IRQ			(1 << 5)
+#define	APBH_CTRL1_CH4_CMDCMPLT_IRQ			(1 << 4)
+#define	APBH_CTRL1_CH3_CMDCMPLT_IRQ			(1 << 3)
+#define	APBH_CTRL1_CH2_CMDCMPLT_IRQ			(1 << 2)
+#define	APBH_CTRL1_CH1_CMDCMPLT_IRQ			(1 << 1)
+#define	APBH_CTRL1_CH0_CMDCMPLT_IRQ			(1 << 0)
+
+#define	APBH_CTRL2_CH15_ERROR_STATUS			(1 << 31)
+#define	APBH_CTRL2_CH14_ERROR_STATUS			(1 << 30)
+#define	APBH_CTRL2_CH13_ERROR_STATUS			(1 << 29)
+#define	APBH_CTRL2_CH12_ERROR_STATUS			(1 << 28)
+#define	APBH_CTRL2_CH11_ERROR_STATUS			(1 << 27)
+#define	APBH_CTRL2_CH10_ERROR_STATUS			(1 << 26)
+#define	APBH_CTRL2_CH9_ERROR_STATUS			(1 << 25)
+#define	APBH_CTRL2_CH8_ERROR_STATUS			(1 << 24)
+#define	APBH_CTRL2_CH7_ERROR_STATUS			(1 << 23)
+#define	APBH_CTRL2_CH6_ERROR_STATUS			(1 << 22)
+#define	APBH_CTRL2_CH5_ERROR_STATUS			(1 << 21)
+#define	APBH_CTRL2_CH4_ERROR_STATUS			(1 << 20)
+#define	APBH_CTRL2_CH3_ERROR_STATUS			(1 << 19)
+#define	APBH_CTRL2_CH2_ERROR_STATUS			(1 << 18)
+#define	APBH_CTRL2_CH1_ERROR_STATUS			(1 << 17)
+#define	APBH_CTRL2_CH0_ERROR_STATUS			(1 << 16)
+#define	APBH_CTRL2_CH15_ERROR_IRQ			(1 << 15)
+#define	APBH_CTRL2_CH14_ERROR_IRQ			(1 << 14)
+#define	APBH_CTRL2_CH13_ERROR_IRQ			(1 << 13)
+#define	APBH_CTRL2_CH12_ERROR_IRQ			(1 << 12)
+#define	APBH_CTRL2_CH11_ERROR_IRQ			(1 << 11)
+#define	APBH_CTRL2_CH10_ERROR_IRQ			(1 << 10)
+#define	APBH_CTRL2_CH9_ERROR_IRQ			(1 << 9)
+#define	APBH_CTRL2_CH8_ERROR_IRQ			(1 << 8)
+#define	APBH_CTRL2_CH7_ERROR_IRQ			(1 << 7)
+#define	APBH_CTRL2_CH6_ERROR_IRQ			(1 << 6)
+#define	APBH_CTRL2_CH5_ERROR_IRQ			(1 << 5)
+#define	APBH_CTRL2_CH4_ERROR_IRQ			(1 << 4)
+#define	APBH_CTRL2_CH3_ERROR_IRQ			(1 << 3)
+#define	APBH_CTRL2_CH2_ERROR_IRQ			(1 << 2)
+#define	APBH_CTRL2_CH1_ERROR_IRQ			(1 << 1)
+#define	APBH_CTRL2_CH0_ERROR_IRQ			(1 << 0)
+
+#if defined(CONFIG_MX28)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK		(0xffff << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET		16
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0		(0x0001 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1		(0x0002 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2		(0x0004 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3		(0x0008 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0		(0x0010 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1		(0x0020 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2		(0x0040 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3		(0x0080 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4		(0x0100 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5		(0x0200 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6		(0x0400 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7		(0x0800 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC		(0x1000 << 16)
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF		(0x2000 << 16)
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK		0xffff
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET		0
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0		0x0001
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1		0x0002
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2		0x0004
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3		0x0008
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0		0x0010
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1		0x0020
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2		0x0040
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3		0x0080
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4		0x0100
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5		0x0200
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6		0x0400
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7		0x0800
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC		0x1000
+#define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF		0x2000
+#endif
+
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#define	APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET		16
+#endif
+
+#if defined(CONFIG_MX23)
+#define	APBH_DEVSEL_CH7_MASK				(0xf << 28)
+#define	APBH_DEVSEL_CH7_OFFSET				28
+#define	APBH_DEVSEL_CH6_MASK				(0xf << 24)
+#define	APBH_DEVSEL_CH6_OFFSET				24
+#define	APBH_DEVSEL_CH5_MASK				(0xf << 20)
+#define	APBH_DEVSEL_CH5_OFFSET				20
+#define	APBH_DEVSEL_CH4_MASK				(0xf << 16)
+#define	APBH_DEVSEL_CH4_OFFSET				16
+#define	APBH_DEVSEL_CH3_MASK				(0xf << 12)
+#define	APBH_DEVSEL_CH3_OFFSET				12
+#define	APBH_DEVSEL_CH2_MASK				(0xf << 8)
+#define	APBH_DEVSEL_CH2_OFFSET				8
+#define	APBH_DEVSEL_CH1_MASK				(0xf << 4)
+#define	APBH_DEVSEL_CH1_OFFSET				4
+#define	APBH_DEVSEL_CH0_MASK				(0xf << 0)
+#define	APBH_DEVSEL_CH0_OFFSET				0
+#elif defined(CONFIG_MX28)
+#define	APBH_DEVSEL_CH15_MASK				(0x3 << 30)
+#define	APBH_DEVSEL_CH15_OFFSET				30
+#define	APBH_DEVSEL_CH14_MASK				(0x3 << 28)
+#define	APBH_DEVSEL_CH14_OFFSET				28
+#define	APBH_DEVSEL_CH13_MASK				(0x3 << 26)
+#define	APBH_DEVSEL_CH13_OFFSET				26
+#define	APBH_DEVSEL_CH12_MASK				(0x3 << 24)
+#define	APBH_DEVSEL_CH12_OFFSET				24
+#define	APBH_DEVSEL_CH11_MASK				(0x3 << 22)
+#define	APBH_DEVSEL_CH11_OFFSET				22
+#define	APBH_DEVSEL_CH10_MASK				(0x3 << 20)
+#define	APBH_DEVSEL_CH10_OFFSET				20
+#define	APBH_DEVSEL_CH9_MASK				(0x3 << 18)
+#define	APBH_DEVSEL_CH9_OFFSET				18
+#define	APBH_DEVSEL_CH8_MASK				(0x3 << 16)
+#define	APBH_DEVSEL_CH8_OFFSET				16
+#define	APBH_DEVSEL_CH7_MASK				(0x3 << 14)
+#define	APBH_DEVSEL_CH7_OFFSET				14
+#define	APBH_DEVSEL_CH6_MASK				(0x3 << 12)
+#define	APBH_DEVSEL_CH6_OFFSET				12
+#define	APBH_DEVSEL_CH5_MASK				(0x3 << 10)
+#define	APBH_DEVSEL_CH5_OFFSET				10
+#define	APBH_DEVSEL_CH4_MASK				(0x3 << 8)
+#define	APBH_DEVSEL_CH4_OFFSET				8
+#define	APBH_DEVSEL_CH3_MASK				(0x3 << 6)
+#define	APBH_DEVSEL_CH3_OFFSET				6
+#define	APBH_DEVSEL_CH2_MASK				(0x3 << 4)
+#define	APBH_DEVSEL_CH2_OFFSET				4
+#define	APBH_DEVSEL_CH1_MASK				(0x3 << 2)
+#define	APBH_DEVSEL_CH1_OFFSET				2
+#define	APBH_DEVSEL_CH0_MASK				(0x3 << 0)
+#define	APBH_DEVSEL_CH0_OFFSET				0
+#endif
+
+#if defined(CONFIG_MX28)
+#define	APBH_DMA_BURST_SIZE_CH15_MASK			(0x3 << 30)
+#define	APBH_DMA_BURST_SIZE_CH15_OFFSET			30
+#define	APBH_DMA_BURST_SIZE_CH14_MASK			(0x3 << 28)
+#define	APBH_DMA_BURST_SIZE_CH14_OFFSET			28
+#define	APBH_DMA_BURST_SIZE_CH13_MASK			(0x3 << 26)
+#define	APBH_DMA_BURST_SIZE_CH13_OFFSET			26
+#define	APBH_DMA_BURST_SIZE_CH12_MASK			(0x3 << 24)
+#define	APBH_DMA_BURST_SIZE_CH12_OFFSET			24
+#define	APBH_DMA_BURST_SIZE_CH11_MASK			(0x3 << 22)
+#define	APBH_DMA_BURST_SIZE_CH11_OFFSET			22
+#define	APBH_DMA_BURST_SIZE_CH10_MASK			(0x3 << 20)
+#define	APBH_DMA_BURST_SIZE_CH10_OFFSET			20
+#define	APBH_DMA_BURST_SIZE_CH9_MASK			(0x3 << 18)
+#define	APBH_DMA_BURST_SIZE_CH9_OFFSET			18
+#define	APBH_DMA_BURST_SIZE_CH8_MASK			(0x3 << 16)
+#define	APBH_DMA_BURST_SIZE_CH8_OFFSET			16
+#define	APBH_DMA_BURST_SIZE_CH8_BURST0			(0x0 << 16)
+#define	APBH_DMA_BURST_SIZE_CH8_BURST4			(0x1 << 16)
+#define	APBH_DMA_BURST_SIZE_CH8_BURST8			(0x2 << 16)
+#define	APBH_DMA_BURST_SIZE_CH7_MASK			(0x3 << 14)
+#define	APBH_DMA_BURST_SIZE_CH7_OFFSET			14
+#define	APBH_DMA_BURST_SIZE_CH6_MASK			(0x3 << 12)
+#define	APBH_DMA_BURST_SIZE_CH6_OFFSET			12
+#define	APBH_DMA_BURST_SIZE_CH5_MASK			(0x3 << 10)
+#define	APBH_DMA_BURST_SIZE_CH5_OFFSET			10
+#define	APBH_DMA_BURST_SIZE_CH4_MASK			(0x3 << 8)
+#define	APBH_DMA_BURST_SIZE_CH4_OFFSET			8
+#define	APBH_DMA_BURST_SIZE_CH3_MASK			(0x3 << 6)
+#define	APBH_DMA_BURST_SIZE_CH3_OFFSET			6
+#define	APBH_DMA_BURST_SIZE_CH3_BURST0			(0x0 << 6)
+#define	APBH_DMA_BURST_SIZE_CH3_BURST4			(0x1 << 6)
+#define	APBH_DMA_BURST_SIZE_CH3_BURST8			(0x2 << 6)
+
+#define	APBH_DMA_BURST_SIZE_CH2_MASK			(0x3 << 4)
+#define	APBH_DMA_BURST_SIZE_CH2_OFFSET			4
+#define	APBH_DMA_BURST_SIZE_CH2_BURST0			(0x0 << 4)
+#define	APBH_DMA_BURST_SIZE_CH2_BURST4			(0x1 << 4)
+#define	APBH_DMA_BURST_SIZE_CH2_BURST8			(0x2 << 4)
+#define	APBH_DMA_BURST_SIZE_CH1_MASK			(0x3 << 2)
+#define	APBH_DMA_BURST_SIZE_CH1_OFFSET			2
+#define	APBH_DMA_BURST_SIZE_CH1_BURST0			(0x0 << 2)
+#define	APBH_DMA_BURST_SIZE_CH1_BURST4			(0x1 << 2)
+#define	APBH_DMA_BURST_SIZE_CH1_BURST8			(0x2 << 2)
+
+#define	APBH_DMA_BURST_SIZE_CH0_MASK			0x3
+#define	APBH_DMA_BURST_SIZE_CH0_OFFSET			0
+#define	APBH_DMA_BURST_SIZE_CH0_BURST0			0x0
+#define	APBH_DMA_BURST_SIZE_CH0_BURST4			0x1
+#define	APBH_DMA_BURST_SIZE_CH0_BURST8			0x2
+
+#define	APBH_DEBUG_GPMI_ONE_FIFO			(1 << 0)
+#endif
+
+#define	APBH_CHn_CURCMDAR_CMD_ADDR_MASK			0xffffffff
+#define	APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET		0
+
+#define	APBH_CHn_NXTCMDAR_CMD_ADDR_MASK			0xffffffff
+#define	APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET		0
+
+#define	APBH_CHn_CMD_XFER_COUNT_MASK			(0xffff << 16)
+#define	APBH_CHn_CMD_XFER_COUNT_OFFSET			16
+#define	APBH_CHn_CMD_CMDWORDS_MASK			(0xf << 12)
+#define	APBH_CHn_CMD_CMDWORDS_OFFSET			12
+#define	APBH_CHn_CMD_HALTONTERMINATE			(1 << 8)
+#define	APBH_CHn_CMD_WAIT4ENDCMD			(1 << 7)
+#define	APBH_CHn_CMD_SEMAPHORE				(1 << 6)
+#define	APBH_CHn_CMD_NANDWAIT4READY			(1 << 5)
+#define	APBH_CHn_CMD_NANDLOCK				(1 << 4)
+#define	APBH_CHn_CMD_IRQONCMPLT				(1 << 3)
+#define	APBH_CHn_CMD_CHAIN				(1 << 2)
+#define	APBH_CHn_CMD_COMMAND_MASK			0x3
+#define	APBH_CHn_CMD_COMMAND_OFFSET			0
+#define	APBH_CHn_CMD_COMMAND_NO_DMA_XFER		0x0
+#define	APBH_CHn_CMD_COMMAND_DMA_WRITE			0x1
+#define	APBH_CHn_CMD_COMMAND_DMA_READ			0x2
+#define	APBH_CHn_CMD_COMMAND_DMA_SENSE			0x3
+
+#define	APBH_CHn_BAR_ADDRESS_MASK			0xffffffff
+#define	APBH_CHn_BAR_ADDRESS_OFFSET			0
+
+#define	APBH_CHn_SEMA_RSVD2_MASK			(0xff << 24)
+#define	APBH_CHn_SEMA_RSVD2_OFFSET			24
+#define	APBH_CHn_SEMA_PHORE_MASK			(0xff << 16)
+#define	APBH_CHn_SEMA_PHORE_OFFSET			16
+#define	APBH_CHn_SEMA_RSVD1_MASK			(0xff << 8)
+#define	APBH_CHn_SEMA_RSVD1_OFFSET			8
+#define	APBH_CHn_SEMA_INCREMENT_SEMA_MASK		(0xff << 0)
+#define	APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET		0
+
+#define	APBH_CHn_DEBUG1_REQ				(1 << 31)
+#define	APBH_CHn_DEBUG1_BURST				(1 << 30)
+#define	APBH_CHn_DEBUG1_KICK				(1 << 29)
+#define	APBH_CHn_DEBUG1_END				(1 << 28)
+#define	APBH_CHn_DEBUG1_SENSE				(1 << 27)
+#define	APBH_CHn_DEBUG1_READY				(1 << 26)
+#define	APBH_CHn_DEBUG1_LOCK				(1 << 25)
+#define	APBH_CHn_DEBUG1_NEXTCMDADDRVALID		(1 << 24)
+#define	APBH_CHn_DEBUG1_RD_FIFO_EMPTY			(1 << 23)
+#define	APBH_CHn_DEBUG1_RD_FIFO_FULL			(1 << 22)
+#define	APBH_CHn_DEBUG1_WR_FIFO_EMPTY			(1 << 21)
+#define	APBH_CHn_DEBUG1_WR_FIFO_FULL			(1 << 20)
+#define	APBH_CHn_DEBUG1_RSVD1_MASK			(0x7fff << 5)
+#define	APBH_CHn_DEBUG1_RSVD1_OFFSET			5
+#define	APBH_CHn_DEBUG1_STATEMACHINE_MASK		0x1f
+#define	APBH_CHn_DEBUG1_STATEMACHINE_OFFSET		0
+#define	APBH_CHn_DEBUG1_STATEMACHINE_IDLE		0x00
+#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1		0x01
+#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3		0x02
+#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2		0x03
+#define	APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE	0x04
+#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT		0x05
+#define	APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4		0x06
+#define	APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ		0x07
+#define	APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH		0x08
+#define	APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT		0x09
+#define	APBH_CHn_DEBUG1_STATEMACHINE_WRITE		0x0c
+#define	APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ		0x0d
+#define	APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN	0x0e
+#define	APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE	0x0f
+#define	APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE		0x14
+#define	APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END		0x15
+#define	APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT		0x1c
+#define	APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM	0x1d
+#define	APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT		0x1e
+#define	APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY		0x1f
+
+#define	APBH_CHn_DEBUG2_APB_BYTES_MASK			(0xffff << 16)
+#define	APBH_CHn_DEBUG2_APB_BYTES_OFFSET		16
+#define	APBH_CHn_DEBUG2_AHB_BYTES_MASK			0xffff
+#define	APBH_CHn_DEBUG2_AHB_BYTES_OFFSET		0
+
+#define	APBH_VERSION_MAJOR_MASK				(0xff << 24)
+#define	APBH_VERSION_MAJOR_OFFSET			24
+#define	APBH_VERSION_MINOR_MASK				(0xff << 16)
+#define	APBH_VERSION_MINOR_OFFSET			16
+#define	APBH_VERSION_STEP_MASK				0xffff
+#define	APBH_VERSION_STEP_OFFSET			0
+
+#endif	/* __REGS_APBH_H__ */
diff --git a/arch/arm/include/asm/mach-imx/regs-bch.h b/arch/arm/include/asm/mach-imx/regs-bch.h
new file mode 100644
index 0000000..39ac5f4
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/regs-bch.h
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 BCH Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __MX28_REGS_BCH_H__
+#define __MX28_REGS_BCH_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_bch_regs {
+	mxs_reg_32(hw_bch_ctrl)
+	mxs_reg_32(hw_bch_status0)
+	mxs_reg_32(hw_bch_mode)
+	mxs_reg_32(hw_bch_encodeptr)
+	mxs_reg_32(hw_bch_dataptr)
+	mxs_reg_32(hw_bch_metaptr)
+
+	uint32_t	reserved[4];
+
+	mxs_reg_32(hw_bch_layoutselect)
+	mxs_reg_32(hw_bch_flash0layout0)
+	mxs_reg_32(hw_bch_flash0layout1)
+	mxs_reg_32(hw_bch_flash1layout0)
+	mxs_reg_32(hw_bch_flash1layout1)
+	mxs_reg_32(hw_bch_flash2layout0)
+	mxs_reg_32(hw_bch_flash2layout1)
+	mxs_reg_32(hw_bch_flash3layout0)
+	mxs_reg_32(hw_bch_flash3layout1)
+	mxs_reg_32(hw_bch_dbgkesread)
+	mxs_reg_32(hw_bch_dbgcsferead)
+	mxs_reg_32(hw_bch_dbgsyndegread)
+	mxs_reg_32(hw_bch_dbgahbmread)
+	mxs_reg_32(hw_bch_blockname)
+	mxs_reg_32(hw_bch_version)
+};
+#endif
+
+#define	BCH_CTRL_SFTRST					(1 << 31)
+#define	BCH_CTRL_CLKGATE				(1 << 30)
+#define	BCH_CTRL_DEBUGSYNDROME				(1 << 22)
+#define	BCH_CTRL_M2M_LAYOUT_MASK			(0x3 << 18)
+#define	BCH_CTRL_M2M_LAYOUT_OFFSET			18
+#define	BCH_CTRL_M2M_ENCODE				(1 << 17)
+#define	BCH_CTRL_M2M_ENABLE				(1 << 16)
+#define	BCH_CTRL_DEBUG_STALL_IRQ_EN			(1 << 10)
+#define	BCH_CTRL_COMPLETE_IRQ_EN			(1 << 8)
+#define	BCH_CTRL_BM_ERROR_IRQ				(1 << 3)
+#define	BCH_CTRL_DEBUG_STALL_IRQ			(1 << 2)
+#define	BCH_CTRL_COMPLETE_IRQ				(1 << 0)
+
+#define	BCH_STATUS0_HANDLE_MASK				(0xfff << 20)
+#define	BCH_STATUS0_HANDLE_OFFSET			20
+#define	BCH_STATUS0_COMPLETED_CE_MASK			(0xf << 16)
+#define	BCH_STATUS0_COMPLETED_CE_OFFSET			16
+#define	BCH_STATUS0_STATUS_BLK0_MASK			(0xff << 8)
+#define	BCH_STATUS0_STATUS_BLK0_OFFSET			8
+#define	BCH_STATUS0_STATUS_BLK0_ZERO			(0x00 << 8)
+#define	BCH_STATUS0_STATUS_BLK0_ERROR1			(0x01 << 8)
+#define	BCH_STATUS0_STATUS_BLK0_ERROR2			(0x02 << 8)
+#define	BCH_STATUS0_STATUS_BLK0_ERROR3			(0x03 << 8)
+#define	BCH_STATUS0_STATUS_BLK0_ERROR4			(0x04 << 8)
+#define	BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE		(0xfe << 8)
+#define	BCH_STATUS0_STATUS_BLK0_ERASED			(0xff << 8)
+#define	BCH_STATUS0_ALLONES				(1 << 4)
+#define	BCH_STATUS0_CORRECTED				(1 << 3)
+#define	BCH_STATUS0_UNCORRECTABLE			(1 << 2)
+
+#define	BCH_MODE_ERASE_THRESHOLD_MASK			0xff
+#define	BCH_MODE_ERASE_THRESHOLD_OFFSET			0
+
+#define	BCH_ENCODEPTR_ADDR_MASK				0xffffffff
+#define	BCH_ENCODEPTR_ADDR_OFFSET			0
+
+#define	BCH_DATAPTR_ADDR_MASK				0xffffffff
+#define	BCH_DATAPTR_ADDR_OFFSET				0
+
+#define	BCH_METAPTR_ADDR_MASK				0xffffffff
+#define	BCH_METAPTR_ADDR_OFFSET				0
+
+#define	BCH_LAYOUTSELECT_CS15_SELECT_MASK		(0x3 << 30)
+#define	BCH_LAYOUTSELECT_CS15_SELECT_OFFSET		30
+#define	BCH_LAYOUTSELECT_CS14_SELECT_MASK		(0x3 << 28)
+#define	BCH_LAYOUTSELECT_CS14_SELECT_OFFSET		28
+#define	BCH_LAYOUTSELECT_CS13_SELECT_MASK		(0x3 << 26)
+#define	BCH_LAYOUTSELECT_CS13_SELECT_OFFSET		26
+#define	BCH_LAYOUTSELECT_CS12_SELECT_MASK		(0x3 << 24)
+#define	BCH_LAYOUTSELECT_CS12_SELECT_OFFSET		24
+#define	BCH_LAYOUTSELECT_CS11_SELECT_MASK		(0x3 << 22)
+#define	BCH_LAYOUTSELECT_CS11_SELECT_OFFSET		22
+#define	BCH_LAYOUTSELECT_CS10_SELECT_MASK		(0x3 << 20)
+#define	BCH_LAYOUTSELECT_CS10_SELECT_OFFSET		20
+#define	BCH_LAYOUTSELECT_CS9_SELECT_MASK		(0x3 << 18)
+#define	BCH_LAYOUTSELECT_CS9_SELECT_OFFSET		18
+#define	BCH_LAYOUTSELECT_CS8_SELECT_MASK		(0x3 << 16)
+#define	BCH_LAYOUTSELECT_CS8_SELECT_OFFSET		16
+#define	BCH_LAYOUTSELECT_CS7_SELECT_MASK		(0x3 << 14)
+#define	BCH_LAYOUTSELECT_CS7_SELECT_OFFSET		14
+#define	BCH_LAYOUTSELECT_CS6_SELECT_MASK		(0x3 << 12)
+#define	BCH_LAYOUTSELECT_CS6_SELECT_OFFSET		12
+#define	BCH_LAYOUTSELECT_CS5_SELECT_MASK		(0x3 << 10)
+#define	BCH_LAYOUTSELECT_CS5_SELECT_OFFSET		10
+#define	BCH_LAYOUTSELECT_CS4_SELECT_MASK		(0x3 << 8)
+#define	BCH_LAYOUTSELECT_CS4_SELECT_OFFSET		8
+#define	BCH_LAYOUTSELECT_CS3_SELECT_MASK		(0x3 << 6)
+#define	BCH_LAYOUTSELECT_CS3_SELECT_OFFSET		6
+#define	BCH_LAYOUTSELECT_CS2_SELECT_MASK		(0x3 << 4)
+#define	BCH_LAYOUTSELECT_CS2_SELECT_OFFSET		4
+#define	BCH_LAYOUTSELECT_CS1_SELECT_MASK		(0x3 << 2)
+#define	BCH_LAYOUTSELECT_CS1_SELECT_OFFSET		2
+#define	BCH_LAYOUTSELECT_CS0_SELECT_MASK		(0x3 << 0)
+#define	BCH_LAYOUTSELECT_CS0_SELECT_OFFSET		0
+
+#define	BCH_FLASHLAYOUT0_NBLOCKS_MASK			(0xff << 24)
+#define	BCH_FLASHLAYOUT0_NBLOCKS_OFFSET			24
+#define	BCH_FLASHLAYOUT0_META_SIZE_MASK			(0xff << 16)
+#define	BCH_FLASHLAYOUT0_META_SIZE_OFFSET		16
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#define	BCH_FLASHLAYOUT0_ECC0_MASK			(0x1f << 11)
+#define	BCH_FLASHLAYOUT0_ECC0_OFFSET			11
+#else
+#define	BCH_FLASHLAYOUT0_ECC0_MASK			(0xf << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_OFFSET			12
+#endif
+#define	BCH_FLASHLAYOUT0_ECC0_NONE			(0x0 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC2			(0x1 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC4			(0x2 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC6			(0x3 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC8			(0x4 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC10			(0x5 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC12			(0x6 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC14			(0x7 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC16			(0x8 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC18			(0x9 << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC20			(0xa << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC22			(0xb << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC24			(0xc << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC26			(0xd << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC28			(0xe << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC30			(0xf << 12)
+#define	BCH_FLASHLAYOUT0_ECC0_ECC32			(0x10 << 12)
+#define	BCH_FLASHLAYOUT0_GF13_0_GF14_1			(1 << 10)
+#define	BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET		10
+#define	BCH_FLASHLAYOUT0_DATA0_SIZE_MASK		0xfff
+#define	BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET		0
+
+#define	BCH_FLASHLAYOUT1_PAGE_SIZE_MASK			(0xffff << 16)
+#define	BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET		16
+#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#define	BCH_FLASHLAYOUT1_ECCN_MASK			(0x1f << 11)
+#define	BCH_FLASHLAYOUT1_ECCN_OFFSET			11
+#else
+#define	BCH_FLASHLAYOUT1_ECCN_MASK			(0xf << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_OFFSET			12
+#endif
+#define	BCH_FLASHLAYOUT1_ECCN_NONE			(0x0 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC2			(0x1 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC4			(0x2 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC6			(0x3 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC8			(0x4 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC10			(0x5 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC12			(0x6 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC14			(0x7 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC16			(0x8 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC18			(0x9 << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC20			(0xa << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC22			(0xb << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC24			(0xc << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC26			(0xd << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC28			(0xe << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC30			(0xf << 12)
+#define	BCH_FLASHLAYOUT1_ECCN_ECC32			(0x10 << 12)
+#define	BCH_FLASHLAYOUT1_GF13_0_GF14_1			(1 << 10)
+#define	BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET		10
+#define	BCH_FLASHLAYOUT1_DATAN_SIZE_MASK		0xfff
+#define	BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET		0
+
+#define	BCH_DEBUG0_RSVD1_MASK				(0x1f << 27)
+#define	BCH_DEBUG0_RSVD1_OFFSET				27
+#define	BCH_DEBUG0_ROM_BIST_ENABLE			(1 << 26)
+#define	BCH_DEBUG0_ROM_BIST_COMPLETE			(1 << 25)
+#define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK	(0x1ff << 16)
+#define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET	16
+#define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL	(0x0 << 16)
+#define	BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE	(0x1 << 16)
+#define	BCH_DEBUG0_KES_DEBUG_SHIFT_SYND			(1 << 15)
+#define	BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG		(1 << 14)
+#define	BCH_DEBUG0_KES_DEBUG_MODE4K			(1 << 13)
+#define	BCH_DEBUG0_KES_DEBUG_KICK			(1 << 12)
+#define	BCH_DEBUG0_KES_STANDALONE			(1 << 11)
+#define	BCH_DEBUG0_KES_DEBUG_STEP			(1 << 10)
+#define	BCH_DEBUG0_KES_DEBUG_STALL			(1 << 9)
+#define	BCH_DEBUG0_BM_KES_TEST_BYPASS			(1 << 8)
+#define	BCH_DEBUG0_RSVD0_MASK				(0x3 << 6)
+#define	BCH_DEBUG0_RSVD0_OFFSET				6
+#define	BCH_DEBUG0_DEBUG_REG_SELECT_MASK		0x3f
+#define	BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET		0
+
+#define	BCH_DBGKESREAD_VALUES_MASK			0xffffffff
+#define	BCH_DBGKESREAD_VALUES_OFFSET			0
+
+#define	BCH_DBGCSFEREAD_VALUES_MASK			0xffffffff
+#define	BCH_DBGCSFEREAD_VALUES_OFFSET			0
+
+#define	BCH_DBGSYNDGENREAD_VALUES_MASK			0xffffffff
+#define	BCH_DBGSYNDGENREAD_VALUES_OFFSET		0
+
+#define	BCH_DBGAHBMREAD_VALUES_MASK			0xffffffff
+#define	BCH_DBGAHBMREAD_VALUES_OFFSET			0
+
+#define	BCH_BLOCKNAME_NAME_MASK				0xffffffff
+#define	BCH_BLOCKNAME_NAME_OFFSET			0
+
+#define	BCH_VERSION_MAJOR_MASK				(0xff << 24)
+#define	BCH_VERSION_MAJOR_OFFSET			24
+#define	BCH_VERSION_MINOR_MASK				(0xff << 16)
+#define	BCH_VERSION_MINOR_OFFSET			16
+#define	BCH_VERSION_STEP_MASK				0xffff
+#define	BCH_VERSION_STEP_OFFSET				0
+
+#endif	/* __MX28_REGS_BCH_H__ */
diff --git a/arch/arm/include/asm/mach-imx/regs-common.h b/arch/arm/include/asm/mach-imx/regs-common.h
new file mode 100644
index 0000000..0f9bd3c
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/regs-common.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MXS Register Accessors
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+
+#ifndef __MXS_REGS_COMMON_H__
+#define __MXS_REGS_COMMON_H__
+
+#include <linux/types.h>
+
+/*
+ * The i.MXS has interesting feature when it comes to register access. There
+ * are four kinds of access to one particular register. Those are:
+ *
+ * 1) Common read/write access. To use this mode, just write to the address of
+ *    the register.
+ * 2) Set bits only access. To set bits, write which bits you want to set to the
+ *    address of the register + 0x4.
+ * 3) Clear bits only access. To clear bits, write which bits you want to clear
+ *    to the address of the register + 0x8.
+ * 4) Toggle bits only access. To toggle bits, write which bits you want to
+ *    toggle to the address of the register + 0xc.
+ *
+ * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits
+ * can be set/cleared by pure write as in access type 1, some need to be
+ * explicitly set/cleared by using access type 2-3.
+ *
+ * The following macros and structures allow the user to either access the
+ * register in all aforementioned modes (by accessing reg_name, reg_name_set,
+ * reg_name_clr, reg_name_tog) or pass the register structure further into
+ * various functions with correct type information (by accessing reg_name_reg).
+ *
+ */
+
+#define	__mxs_reg_8(name)		\
+	uint8_t	name[4];		\
+	uint8_t	name##_set[4];		\
+	uint8_t	name##_clr[4];		\
+	uint8_t	name##_tog[4];		\
+
+#define	__mxs_reg_32(name)		\
+	uint32_t name;			\
+	uint32_t name##_set;		\
+	uint32_t name##_clr;		\
+	uint32_t name##_tog;
+
+struct mxs_register_8 {
+	__mxs_reg_8(reg)
+};
+
+struct mxs_register_32 {
+	__mxs_reg_32(reg)
+};
+
+#define	mxs_reg_8(name)				\
+	union {						\
+		struct { __mxs_reg_8(name) };		\
+		struct mxs_register_8 name##_reg;	\
+	};
+
+#define	mxs_reg_32(name)				\
+	union {						\
+		struct { __mxs_reg_32(name) };		\
+		struct mxs_register_32 name##_reg;	\
+	};
+
+#endif	/* __MXS_REGS_COMMON_H__ */
diff --git a/arch/arm/include/asm/mach-imx/regs-gpmi.h b/arch/arm/include/asm/mach-imx/regs-gpmi.h
new file mode 100644
index 0000000..80cb731
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/regs-gpmi.h
@@ -0,0 +1,208 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28 GPMI Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __MX28_REGS_GPMI_H__
+#define __MX28_REGS_GPMI_H__
+
+#include <asm/mach-imx/regs-common.h>
+
+#ifndef	__ASSEMBLY__
+struct mxs_gpmi_regs {
+	mxs_reg_32(hw_gpmi_ctrl0)
+	mxs_reg_32(hw_gpmi_compare)
+	mxs_reg_32(hw_gpmi_eccctrl)
+	mxs_reg_32(hw_gpmi_ecccount)
+	mxs_reg_32(hw_gpmi_payload)
+	mxs_reg_32(hw_gpmi_auxiliary)
+	mxs_reg_32(hw_gpmi_ctrl1)
+	mxs_reg_32(hw_gpmi_timing0)
+	mxs_reg_32(hw_gpmi_timing1)
+
+	uint32_t	reserved[4];
+
+	mxs_reg_32(hw_gpmi_data)
+	mxs_reg_32(hw_gpmi_stat)
+	mxs_reg_32(hw_gpmi_debug)
+	mxs_reg_32(hw_gpmi_version)
+};
+#endif
+
+#define	GPMI_CTRL0_SFTRST				(1 << 31)
+#define	GPMI_CTRL0_CLKGATE				(1 << 30)
+#define	GPMI_CTRL0_RUN					(1 << 29)
+#define	GPMI_CTRL0_DEV_IRQ_EN				(1 << 28)
+#define	GPMI_CTRL0_LOCK_CS				(1 << 27)
+#define	GPMI_CTRL0_UDMA					(1 << 26)
+#define	GPMI_CTRL0_COMMAND_MODE_MASK			(0x3 << 24)
+#define	GPMI_CTRL0_COMMAND_MODE_OFFSET			24
+#define	GPMI_CTRL0_COMMAND_MODE_WRITE			(0x0 << 24)
+#define	GPMI_CTRL0_COMMAND_MODE_READ			(0x1 << 24)
+#define	GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE	(0x2 << 24)
+#define	GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY		(0x3 << 24)
+#define	GPMI_CTRL0_WORD_LENGTH				(1 << 23)
+#define	GPMI_CTRL0_CS_MASK				(0x7 << 20)
+#define	GPMI_CTRL0_CS_OFFSET				20
+#define	GPMI_CTRL0_ADDRESS_MASK				(0x7 << 17)
+#define	GPMI_CTRL0_ADDRESS_OFFSET			17
+#define	GPMI_CTRL0_ADDRESS_NAND_DATA			(0x0 << 17)
+#define	GPMI_CTRL0_ADDRESS_NAND_CLE			(0x1 << 17)
+#define	GPMI_CTRL0_ADDRESS_NAND_ALE			(0x2 << 17)
+#define	GPMI_CTRL0_ADDRESS_INCREMENT			(1 << 16)
+#define	GPMI_CTRL0_XFER_COUNT_MASK			0xffff
+#define	GPMI_CTRL0_XFER_COUNT_OFFSET			0
+
+#define	GPMI_COMPARE_MASK_MASK				(0xffff << 16)
+#define	GPMI_COMPARE_MASK_OFFSET			16
+#define	GPMI_COMPARE_REFERENCE_MASK			0xffff
+#define	GPMI_COMPARE_REFERENCE_OFFSET			0
+
+#define	GPMI_ECCCTRL_HANDLE_MASK			(0xffff << 16)
+#define	GPMI_ECCCTRL_HANDLE_OFFSET			16
+#define	GPMI_ECCCTRL_ECC_CMD_MASK			(0x3 << 13)
+#define	GPMI_ECCCTRL_ECC_CMD_OFFSET			13
+#define	GPMI_ECCCTRL_ECC_CMD_DECODE			(0x0 << 13)
+#define	GPMI_ECCCTRL_ECC_CMD_ENCODE			(0x1 << 13)
+#define	GPMI_ECCCTRL_ENABLE_ECC				(1 << 12)
+#define	GPMI_ECCCTRL_BUFFER_MASK_MASK			0x1ff
+#define	GPMI_ECCCTRL_BUFFER_MASK_OFFSET			0
+#define	GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY		0x100
+#define	GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE		0x1ff
+
+#define	GPMI_ECCCOUNT_COUNT_MASK			0xffff
+#define	GPMI_ECCCOUNT_COUNT_OFFSET			0
+
+#define	GPMI_PAYLOAD_ADDRESS_MASK			(0x3fffffff << 2)
+#define	GPMI_PAYLOAD_ADDRESS_OFFSET			2
+
+#define	GPMI_AUXILIARY_ADDRESS_MASK			(0x3fffffff << 2)
+#define	GPMI_AUXILIARY_ADDRESS_OFFSET			2
+
+#define	GPMI_CTRL1_DECOUPLE_CS				(1 << 24)
+#define	GPMI_CTRL1_WRN_DLY_SEL_MASK			(0x3 << 22)
+#define	GPMI_CTRL1_WRN_DLY_SEL_OFFSET			22
+#define	GPMI_CTRL1_TIMEOUT_IRQ_EN			(1 << 20)
+#define	GPMI_CTRL1_GANGED_RDYBUSY			(1 << 19)
+#define	GPMI_CTRL1_BCH_MODE				(1 << 18)
+#define	GPMI_CTRL1_DLL_ENABLE				(1 << 17)
+#define	GPMI_CTRL1_HALF_PERIOD				(1 << 16)
+#define	GPMI_CTRL1_RDN_DELAY_MASK			(0xf << 12)
+#define	GPMI_CTRL1_RDN_DELAY_OFFSET			12
+#define	GPMI_CTRL1_DMA2ECC_MODE				(1 << 11)
+#define	GPMI_CTRL1_DEV_IRQ				(1 << 10)
+#define	GPMI_CTRL1_TIMEOUT_IRQ				(1 << 9)
+#define	GPMI_CTRL1_BURST_EN				(1 << 8)
+#define	GPMI_CTRL1_ABORT_WAIT_REQUEST			(1 << 7)
+#define	GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK	(0x7 << 4)
+#define	GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET	4
+#define	GPMI_CTRL1_DEV_RESET				(1 << 3)
+#define	GPMI_CTRL1_ATA_IRQRDY_POLARITY			(1 << 2)
+#define	GPMI_CTRL1_CAMERA_MODE				(1 << 1)
+#define	GPMI_CTRL1_GPMI_MODE				(1 << 0)
+
+#define	GPMI_TIMING0_ADDRESS_SETUP_MASK			(0xff << 16)
+#define	GPMI_TIMING0_ADDRESS_SETUP_OFFSET		16
+#define	GPMI_TIMING0_DATA_HOLD_MASK			(0xff << 8)
+#define	GPMI_TIMING0_DATA_HOLD_OFFSET			8
+#define	GPMI_TIMING0_DATA_SETUP_MASK			0xff
+#define	GPMI_TIMING0_DATA_SETUP_OFFSET			0
+
+#define	GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK		(0xffff << 16)
+#define	GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET		16
+
+#define	GPMI_TIMING2_UDMA_TRP_MASK			(0xff << 24)
+#define	GPMI_TIMING2_UDMA_TRP_OFFSET			24
+#define	GPMI_TIMING2_UDMA_ENV_MASK			(0xff << 16)
+#define	GPMI_TIMING2_UDMA_ENV_OFFSET			16
+#define	GPMI_TIMING2_UDMA_HOLD_MASK			(0xff << 8)
+#define	GPMI_TIMING2_UDMA_HOLD_OFFSET			8
+#define	GPMI_TIMING2_UDMA_SETUP_MASK			0xff
+#define	GPMI_TIMING2_UDMA_SETUP_OFFSET			0
+
+#define	GPMI_DATA_DATA_MASK				0xffffffff
+#define	GPMI_DATA_DATA_OFFSET				0
+
+#define	GPMI_STAT_READY_BUSY_MASK			(0xff << 24)
+#define	GPMI_STAT_READY_BUSY_OFFSET			24
+#define	GPMI_STAT_RDY_TIMEOUT_MASK			(0xff << 16)
+#define	GPMI_STAT_RDY_TIMEOUT_OFFSET			16
+#define	GPMI_STAT_DEV7_ERROR				(1 << 15)
+#define	GPMI_STAT_DEV6_ERROR				(1 << 14)
+#define	GPMI_STAT_DEV5_ERROR				(1 << 13)
+#define	GPMI_STAT_DEV4_ERROR				(1 << 12)
+#define	GPMI_STAT_DEV3_ERROR				(1 << 11)
+#define	GPMI_STAT_DEV2_ERROR				(1 << 10)
+#define	GPMI_STAT_DEV1_ERROR				(1 << 9)
+#define	GPMI_STAT_DEV0_ERROR				(1 << 8)
+#define	GPMI_STAT_ATA_IRQ				(1 << 4)
+#define	GPMI_STAT_INVALID_BUFFER_MASK			(1 << 3)
+#define	GPMI_STAT_FIFO_EMPTY				(1 << 2)
+#define	GPMI_STAT_FIFO_FULL				(1 << 1)
+#define	GPMI_STAT_PRESENT				(1 << 0)
+
+#define	GPMI_DEBUG_WAIT_FOR_READY_END_MASK		(0xff << 24)
+#define	GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET		24
+#define	GPMI_DEBUG_DMA_SENSE_MASK			(0xff << 16)
+#define	GPMI_DEBUG_DMA_SENSE_OFFSET			16
+#define	GPMI_DEBUG_DMAREQ_MASK				(0xff << 8)
+#define	GPMI_DEBUG_DMAREQ_OFFSET			8
+#define	GPMI_DEBUG_CMD_END_MASK				0xff
+#define	GPMI_DEBUG_CMD_END_OFFSET			0
+
+#define	GPMI_VERSION_MAJOR_MASK				(0xff << 24)
+#define	GPMI_VERSION_MAJOR_OFFSET			24
+#define	GPMI_VERSION_MINOR_MASK				(0xff << 16)
+#define	GPMI_VERSION_MINOR_OFFSET			16
+#define	GPMI_VERSION_STEP_MASK				0xffff
+#define	GPMI_VERSION_STEP_OFFSET			0
+
+#define	GPMI_DEBUG2_UDMA_STATE_MASK			(0xf << 24)
+#define	GPMI_DEBUG2_UDMA_STATE_OFFSET			24
+#define	GPMI_DEBUG2_BUSY				(1 << 23)
+#define	GPMI_DEBUG2_PIN_STATE_MASK			(0x7 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_OFFSET			20
+#define	GPMI_DEBUG2_PIN_STATE_PSM_IDLE			(0x0 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT		(0x1 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_ADDR			(0x2 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_STALL			(0x3 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_STROBE		(0x4 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_ATARDY		(0x5 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_DHOLD			(0x6 << 20)
+#define	GPMI_DEBUG2_PIN_STATE_PSM_DONE			(0x7 << 20)
+#define	GPMI_DEBUG2_MAIN_STATE_MASK			(0xf << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_OFFSET			16
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_IDLE			(0x0 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT		(0x1 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE		(0x2 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR		(0x3 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ		(0x4 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK		(0x5 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF		(0x6 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO		(0x7 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR		(0x8 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP		(0x9 << 16)
+#define	GPMI_DEBUG2_MAIN_STATE_MSM_DONE			(0xa << 16)
+#define	GPMI_DEBUG2_SYND2GPMI_BE_MASK			(0xf << 12)
+#define	GPMI_DEBUG2_SYND2GPMI_BE_OFFSET			12
+#define	GPMI_DEBUG2_GPMI2SYND_VALID			(1 << 11)
+#define	GPMI_DEBUG2_GPMI2SYND_READY			(1 << 10)
+#define	GPMI_DEBUG2_SYND2GPMI_VALID			(1 << 9)
+#define	GPMI_DEBUG2_SYND2GPMI_READY			(1 << 8)
+#define	GPMI_DEBUG2_VIEW_DELAYED_RDN			(1 << 7)
+#define	GPMI_DEBUG2_UPDATE_WINDOW			(1 << 6)
+#define	GPMI_DEBUG2_RDN_TAP_MASK			0x3f
+#define	GPMI_DEBUG2_RDN_TAP_OFFSET			0
+
+#define	GPMI_DEBUG3_APB_WORD_CNTR_MASK			(0xffff << 16)
+#define	GPMI_DEBUG3_APB_WORD_CNTR_OFFSET		16
+#define	GPMI_DEBUG3_DEV_WORD_CNTR_MASK			0xffff
+#define	GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET		0
+
+#endif	/* __MX28_REGS_GPMI_H__ */
diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h
new file mode 100644
index 0000000..b4c430a
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
@@ -0,0 +1,240 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX28/6SX/6UL/7D LCDIF Register Definitions
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * Based on code from LTIB:
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __IMX_REGS_LCDIF_H__
+#define __IMX_REGS_LCDIF_H__
+
+#ifndef	__ASSEMBLY__
+#include <asm/mach-imx/regs-common.h>
+
+struct mxs_lcdif_regs {
+	mxs_reg_32(hw_lcdif_ctrl)		/* 0x00 */
+	mxs_reg_32(hw_lcdif_ctrl1)		/* 0x10 */
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+	defined(CONFIG_IMX8M)
+	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
+#endif
+	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
+	mxs_reg_32(hw_lcdif_cur_buf)		/* 0x30/0x40 */
+	mxs_reg_32(hw_lcdif_next_buf)		/* 0x40/0x50 */
+
+#if defined(CONFIG_MX23)
+	uint32_t	reserved1[4];
+#endif
+
+	mxs_reg_32(hw_lcdif_timing)		/* 0x60 */
+	mxs_reg_32(hw_lcdif_vdctrl0)		/* 0x70 */
+	mxs_reg_32(hw_lcdif_vdctrl1)		/* 0x80 */
+	mxs_reg_32(hw_lcdif_vdctrl2)		/* 0x90 */
+	mxs_reg_32(hw_lcdif_vdctrl3)		/* 0xa0 */
+	mxs_reg_32(hw_lcdif_vdctrl4)		/* 0xb0 */
+	mxs_reg_32(hw_lcdif_dvictrl0)		/* 0xc0 */
+	mxs_reg_32(hw_lcdif_dvictrl1)		/* 0xd0 */
+	mxs_reg_32(hw_lcdif_dvictrl2)		/* 0xe0 */
+	mxs_reg_32(hw_lcdif_dvictrl3)		/* 0xf0 */
+	mxs_reg_32(hw_lcdif_dvictrl4)		/* 0x100 */
+	mxs_reg_32(hw_lcdif_csc_coeffctrl0)	/* 0x110 */
+	mxs_reg_32(hw_lcdif_csc_coeffctrl1)	/* 0x120 */
+	mxs_reg_32(hw_lcdif_csc_coeffctrl2)	/* 0x130 */
+	mxs_reg_32(hw_lcdif_csc_coeffctrl3)	/* 0x140 */
+	mxs_reg_32(hw_lcdif_csc_coeffctrl4)	/* 0x150 */
+	mxs_reg_32(hw_lcdif_csc_offset)	/* 0x160 */
+	mxs_reg_32(hw_lcdif_csc_limit)		/* 0x170 */
+
+#if defined(CONFIG_MX23)
+	uint32_t	reserved2[12];
+#endif
+	mxs_reg_32(hw_lcdif_data)		/* 0x1b0/0x180 */
+	mxs_reg_32(hw_lcdif_bm_error_stat)	/* 0x1c0/0x190 */
+#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+	defined(CONFIG_IMX8M)
+	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
+#endif
+	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
+	mxs_reg_32(hw_lcdif_version)		/* 0x1e0/0x1c0 */
+	mxs_reg_32(hw_lcdif_debug0)		/* 0x1f0/0x1d0 */
+	mxs_reg_32(hw_lcdif_debug1)		/* 0x200/0x1e0 */
+	mxs_reg_32(hw_lcdif_debug2)		/* 0x1f0 */
+#if defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
+	defined(CONFIG_IMX8M)
+	mxs_reg_32(hw_lcdif_thres)
+	mxs_reg_32(hw_lcdif_as_ctrl)
+	mxs_reg_32(hw_lcdif_as_buf)
+	mxs_reg_32(hw_lcdif_as_next_buf)
+	mxs_reg_32(hw_lcdif_as_clrkeylow)
+	mxs_reg_32(hw_lcdif_as_clrkeyhigh)
+	mxs_reg_32(hw_lcdif_as_sync_delay)
+	mxs_reg_32(hw_lcdif_as_debug3)
+	mxs_reg_32(hw_lcdif_as_debug4)
+	mxs_reg_32(hw_lcdif_as_debug5)
+#endif
+};
+#endif
+
+#define	LCDIF_CTRL_SFTRST					(1 << 31)
+#define	LCDIF_CTRL_CLKGATE					(1 << 30)
+#define	LCDIF_CTRL_YCBCR422_INPUT				(1 << 29)
+#define	LCDIF_CTRL_READ_WRITEB					(1 << 28)
+#define	LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE				(1 << 27)
+#define	LCDIF_CTRL_DATA_SHIFT_DIR				(1 << 26)
+#define	LCDIF_CTRL_SHIFT_NUM_BITS_MASK				(0x1f << 21)
+#define	LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET			21
+#define	LCDIF_CTRL_DVI_MODE					(1 << 20)
+#define	LCDIF_CTRL_BYPASS_COUNT					(1 << 19)
+#define	LCDIF_CTRL_VSYNC_MODE					(1 << 18)
+#define	LCDIF_CTRL_DOTCLK_MODE					(1 << 17)
+#define	LCDIF_CTRL_DATA_SELECT					(1 << 16)
+#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK			(0x3 << 14)
+#define	LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET			14
+#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK			(0x3 << 12)
+#define	LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET			12
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK			(0x3 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET			10
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT			(0 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT			(1 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT			(2 << 10)
+#define	LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT			(3 << 10)
+#define	LCDIF_CTRL_WORD_LENGTH_MASK				(0x3 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_OFFSET				8
+#define	LCDIF_CTRL_WORD_LENGTH_16BIT				(0 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_8BIT				(1 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_18BIT				(2 << 8)
+#define	LCDIF_CTRL_WORD_LENGTH_24BIT				(3 << 8)
+#define	LCDIF_CTRL_RGB_TO_YCBCR422_CSC				(1 << 7)
+#define	LCDIF_CTRL_LCDIF_MASTER					(1 << 5)
+#define	LCDIF_CTRL_DATA_FORMAT_16_BIT				(1 << 3)
+#define	LCDIF_CTRL_DATA_FORMAT_18_BIT				(1 << 2)
+#define	LCDIF_CTRL_DATA_FORMAT_24_BIT				(1 << 1)
+#define	LCDIF_CTRL_RUN						(1 << 0)
+
+#define	LCDIF_CTRL1_COMBINE_MPU_WR_STRB				(1 << 27)
+#define	LCDIF_CTRL1_BM_ERROR_IRQ_EN				(1 << 26)
+#define	LCDIF_CTRL1_BM_ERROR_IRQ				(1 << 25)
+#define	LCDIF_CTRL1_RECOVER_ON_UNDERFLOW			(1 << 24)
+#define	LCDIF_CTRL1_INTERLACE_FIELDS				(1 << 23)
+#define	LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD		(1 << 22)
+#define	LCDIF_CTRL1_FIFO_CLEAR					(1 << 21)
+#define	LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS			(1 << 20)
+#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK			(0xf << 16)
+#define	LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET			16
+#define	LCDIF_CTRL1_OVERFLOW_IRQ_EN				(1 << 15)
+#define	LCDIF_CTRL1_UNDERFLOW_IRQ_EN				(1 << 14)
+#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN			(1 << 13)
+#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN				(1 << 12)
+#define	LCDIF_CTRL1_OVERFLOW_IRQ				(1 << 11)
+#define	LCDIF_CTRL1_UNDERFLOW_IRQ				(1 << 10)
+#define	LCDIF_CTRL1_CUR_FRAME_DONE_IRQ				(1 << 9)
+#define	LCDIF_CTRL1_VSYNC_EDGE_IRQ				(1 << 8)
+#define	LCDIF_CTRL1_BUSY_ENABLE					(1 << 2)
+#define	LCDIF_CTRL1_MODE86					(1 << 1)
+#define	LCDIF_CTRL1_RESET					(1 << 0)
+
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_MASK			(0x7 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET			21
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1			(0x0 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2			(0x1 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4			(0x2 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8			(0x3 << 21)
+#define	LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16			(0x4 << 21)
+#define	LCDIF_CTRL2_BURST_LEN_8					(1 << 20)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_MASK			(0x7 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET			16
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_RGB			(0x0 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_RBG			(0x1 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_GBR			(0x2 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_GRB			(0x3 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_BRG			(0x4 << 16)
+#define	LCDIF_CTRL2_ODD_LINE_PATTERN_BGR			(0x5 << 16)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK			(0x7 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET			12
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB			(0x0 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG			(0x1 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR			(0x2 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB			(0x3 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG			(0x4 << 12)
+#define	LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR			(0x5 << 12)
+#define	LCDIF_CTRL2_READ_PACK_DIR				(1 << 10)
+#define	LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT		(1 << 9)
+#define	LCDIF_CTRL2_READ_MODE_6_BIT_INPUT			(1 << 8)
+#define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK		(0x7 << 4)
+#define	LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET	4
+#define	LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK			(0x7 << 1)
+#define	LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET			1
+
+#define	LCDIF_TRANSFER_COUNT_V_COUNT_MASK			(0xffff << 16)
+#define	LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET			16
+#define	LCDIF_TRANSFER_COUNT_H_COUNT_MASK			(0xffff << 0)
+#define	LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET			0
+
+#define	LCDIF_CUR_BUF_ADDR_MASK					0xffffffff
+#define	LCDIF_CUR_BUF_ADDR_OFFSET				0
+
+#define	LCDIF_NEXT_BUF_ADDR_MASK				0xffffffff
+#define	LCDIF_NEXT_BUF_ADDR_OFFSET				0
+
+#define	LCDIF_TIMING_CMD_HOLD_MASK				(0xff << 24)
+#define	LCDIF_TIMING_CMD_HOLD_OFFSET				24
+#define	LCDIF_TIMING_CMD_SETUP_MASK				(0xff << 16)
+#define	LCDIF_TIMING_CMD_SETUP_OFFSET				16
+#define	LCDIF_TIMING_DATA_HOLD_MASK				(0xff << 8)
+#define	LCDIF_TIMING_DATA_HOLD_OFFSET				8
+#define	LCDIF_TIMING_DATA_SETUP_MASK				(0xff << 0)
+#define	LCDIF_TIMING_DATA_SETUP_OFFSET				0
+
+#define	LCDIF_VDCTRL0_VSYNC_OEB					(1 << 29)
+#define	LCDIF_VDCTRL0_ENABLE_PRESENT				(1 << 28)
+#define	LCDIF_VDCTRL0_VSYNC_POL					(1 << 27)
+#define	LCDIF_VDCTRL0_HSYNC_POL					(1 << 26)
+#define	LCDIF_VDCTRL0_DOTCLK_POL				(1 << 25)
+#define	LCDIF_VDCTRL0_ENABLE_POL				(1 << 24)
+#define	LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT				(1 << 21)
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT			(1 << 20)
+#define	LCDIF_VDCTRL0_HALF_LINE					(1 << 19)
+#define	LCDIF_VDCTRL0_HALF_LINE_MODE				(1 << 18)
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK			0x3ffff
+#define	LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET			0
+
+#define	LCDIF_VDCTRL1_VSYNC_PERIOD_MASK				0xffffffff
+#define	LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET			0
+
+#if defined(CONFIG_MX23)
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0xff << 24)
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			24
+#else
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK			(0x3fff << 18)
+#define	LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET			18
+#endif
+#define	LCDIF_VDCTRL2_HSYNC_PERIOD_MASK				0x3ffff
+#define	LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET			0
+
+#define	LCDIF_VDCTRL3_MUX_SYNC_SIGNALS				(1 << 29)
+#define	LCDIF_VDCTRL3_VSYNC_ONLY				(1 << 28)
+#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK			(0xfff << 16)
+#define	LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET		16
+#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK			(0xffff << 0)
+#define	LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET			0
+
+#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK			(0x7 << 29)
+#define	LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET			29
+#define	LCDIF_VDCTRL4_SYNC_SIGNALS_ON				(1 << 18)
+#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK		0x3ffff
+#define	LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET		0
+
+#endif /* __IMX_REGS_LCDIF_H__ */
diff --git a/arch/arm/include/asm/mach-imx/regs-usbphy.h b/arch/arm/include/asm/mach-imx/regs-usbphy.h
new file mode 100644
index 0000000..2b18ec2
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/regs-usbphy.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale USB PHY Register Definitions
+ *
+ */
+
+#ifndef __REGS_USBPHY_H__
+#define __REGS_USBPHY_H__
+
+#define USBPHY_CTRL						0x00000030
+#define USBPHY_CTRL_SET					0x00000034
+#define USBPHY_CTRL_CLR					0x00000038
+#define USBPHY_CTRL_TOG					0x0000003C
+#define USBPHY_PWD						0x00000000
+#define USBPHY_TX						0x00000010
+#define USBPHY_RX						0x00000020
+#define USBPHY_DEBUG					0x00000050
+
+#define USBPHY_CTRL_ENUTMILEVEL2		(1 << 14)
+#define USBPHY_CTRL_ENUTMILEVEL3		(1 << 15)
+#define USBPHY_CTRL_OTG_ID				(1 << 27)
+#define USBPHY_CTRL_CLKGATE				(1 << 30)
+#define USBPHY_CTRL_SFTRST				(1 << 31)
+
+#endif /* __REGS_USBPHY_H__ */
diff --git a/arch/arm/include/asm/mach-imx/sata.h b/arch/arm/include/asm/mach-imx/sata.h
new file mode 100644
index 0000000..cf9b73e
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/sata.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __IMX_SATA_H_
+#define __IMX_SATA_H_
+
+/*
+ * SATA setup for i.mx6 quad based platform
+ */
+
+int setup_sata(void);
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/spi.h b/arch/arm/include/asm/mach-imx/spi.h
new file mode 100644
index 0000000..598a996
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/spi.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __MXC_SPI_H_
+#define __MXC_SPI_H_
+
+/*
+ * Board-level chip-select callback
+ * Should return GPIO # to be used for chip-select
+ */
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs);
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
new file mode 100644
index 0000000..aa66fdc
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/io.h>
+#include <asm/mach-imx/regs-common.h>
+#include <common.h>
+#include "../arch-imx/cpu.h"
+
+#define soc_rev() (get_cpu_rev() & 0xFF)
+#define is_soc_rev(rev) (soc_rev() == rev)
+
+/* returns MXC_CPU_ value */
+#define cpu_type(rev) (((rev) >> 12) & 0xff)
+#define soc_type(rev) (((rev) >> 12) & 0xf0)
+/* both macros return/take MXC_CPU_ constants */
+#define get_cpu_type() (cpu_type(get_cpu_rev()))
+#define get_soc_type() (soc_type(get_cpu_rev()))
+#define is_cpu_type(cpu) (get_cpu_type() == cpu)
+#define is_soc_type(soc) (get_soc_type() == soc)
+
+#define is_mx6() (is_soc_type(MXC_SOC_MX6))
+#define is_mx7() (is_soc_type(MXC_SOC_MX7))
+#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
+#define is_imx8() (is_soc_type(MXC_SOC_IMX8))
+
+#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
+#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
+#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
+#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
+#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
+#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
+#define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ))
+#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
+
+#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
+
+#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
+#define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM))
+#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
+	is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
+	is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
+#define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
+#define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
+#define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
+#define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
+#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
+#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
+
+#ifdef CONFIG_MX6
+#define IMX6_SRC_GPR10_BMODE		BIT(28)
+
+#define IMX6_BMODE_MASK			GENMASK(7, 0)
+#define	IMX6_BMODE_SHIFT		4
+#define IMX6_BMODE_EMI_MASK		BIT(3)
+#define IMX6_BMODE_EMI_SHIFT		3
+#define IMX6_BMODE_SERIAL_ROM_MASK	GENMASK(26, 24)
+#define IMX6_BMODE_SERIAL_ROM_SHIFT	24
+
+enum imx6_bmode_serial_rom {
+	IMX6_BMODE_ECSPI1,
+	IMX6_BMODE_ECSPI2,
+	IMX6_BMODE_ECSPI3,
+	IMX6_BMODE_ECSPI4,
+	IMX6_BMODE_ECSPI5,
+	IMX6_BMODE_I2C1,
+	IMX6_BMODE_I2C2,
+	IMX6_BMODE_I2C3,
+};
+
+enum imx6_bmode_emi {
+	IMX6_BMODE_NOR,
+	IMX6_BMODE_ONENAND,
+};
+
+enum imx6_bmode {
+	IMX6_BMODE_EMI,
+#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+	IMX6_BMODE_QSPI,
+	IMX6_BMODE_RESERVED,
+#else
+	IMX6_BMODE_RESERVED,
+	IMX6_BMODE_SATA,
+#endif
+	IMX6_BMODE_SERIAL_ROM,
+	IMX6_BMODE_SD,
+	IMX6_BMODE_ESD,
+	IMX6_BMODE_MMC,
+	IMX6_BMODE_EMMC,
+	IMX6_BMODE_NAND_MIN,
+	IMX6_BMODE_NAND_MAX = 0xf,
+};
+
+static inline u8 imx6_is_bmode_from_gpr9(void)
+{
+	return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE;
+}
+
+u32 imx6_src_get_boot_mode(void);
+void gpr_init(void);
+
+#endif /* CONFIG_MX6 */
+
+u32 get_nr_cpus(void);
+u32 get_cpu_rev(void);
+u32 get_cpu_speed_grade_hz(void);
+u32 get_cpu_temp_grade(int *minc, int *maxc);
+const char *get_imx_type(u32 imxtype);
+u32 imx_ddr_size(void);
+void sdelay(unsigned long);
+void set_chipselect_size(int const);
+
+void init_aips(void);
+void init_src(void);
+void init_snvs(void);
+void imx_wdog_disable_powerdown(void);
+
+int board_mmc_get_env_dev(int devno);
+
+int nxp_board_rev(void);
+char nxp_board_rev_string(void);
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int fecmxc_initialize(bd_t *bis);
+u32 get_ahb_clk(void);
+u32 get_periph_clk(void);
+
+void lcdif_power_down(void);
+
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+
+unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
+			   unsigned long reg1, unsigned long reg2);
+unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
+				unsigned long *reg1, unsigned long reg2,
+				unsigned long reg3);
+#endif
diff --git a/arch/arm/include/asm/mach-imx/syscounter.h b/arch/arm/include/asm/mach-imx/syscounter.h
new file mode 100644
index 0000000..a2cae1e
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/syscounter.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
+#define _ASM_ARCH_SYSTEM_COUNTER_H
+
+/* System Counter */
+struct sctr_regs {
+	u32 cntcr;
+	u32 cntsr;
+	u32 cntcv1;
+	u32 cntcv2;
+	u32 resv1[4];
+	u32 cntfid0;
+	u32 cntfid1;
+	u32 cntfid2;
+	u32 resv2[1001];
+	u32 counterid[1];
+};
+
+#define SC_CNTCR_ENABLE		(1 << 0)
+#define SC_CNTCR_HDBG		(1 << 1)
+#define SC_CNTCR_FREQ0		(1 << 8)
+#define SC_CNTCR_FREQ1		(1 << 9)
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/video.h b/arch/arm/include/asm/mach-imx/video.h
new file mode 100644
index 0000000..d1a14ad
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/video.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __IMX_VIDEO_H_
+#define __IMX_VIDEO_H_
+
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+struct display_info_t {
+	int	bus;
+	int	addr;
+	int	pixfmt;
+	int	di;
+	int	(*detect)(struct display_info_t const *dev);
+	void	(*enable)(struct display_info_t const *dev);
+	struct	fb_videomode mode;
+};
+
+#ifdef CONFIG_IMX_HDMI
+extern int detect_hdmi(struct display_info_t const *dev);
+#endif
+
+#ifdef CONFIG_IMX_VIDEO_SKIP
+extern struct display_info_t const displays[];
+extern size_t display_count;
+#endif
+
+int ipu_set_ldb_clock(int rate);
+int ipu_displays_init(void);
+#endif
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
new file mode 100644
index 0000000..32532b3
--- /dev/null
+++ b/arch/arm/include/asm/mach-types.h
@@ -0,0 +1,5054 @@
+/*
+ * This was automagically generated from arch/arm/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_ARM_MACH_TYPE_H
+#define __ASM_ARM_MACH_TYPE_H
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_EBSA110              0
+#define MACH_TYPE_RISCPC               1
+#define MACH_TYPE_NEXUSPCI             3
+#define MACH_TYPE_EBSA285              4
+#define MACH_TYPE_NETWINDER            5
+#define MACH_TYPE_CATS                 6
+#define MACH_TYPE_TBOX                 7
+#define MACH_TYPE_CO285                8
+#define MACH_TYPE_CLPS7110             9
+#define MACH_TYPE_ARCHIMEDES           10
+#define MACH_TYPE_A5K                  11
+#define MACH_TYPE_ETOILE               12
+#define MACH_TYPE_LACIE_NAS            13
+#define MACH_TYPE_CLPS7500             14
+#define MACH_TYPE_SHARK                15
+#define MACH_TYPE_BRUTUS               16
+#define MACH_TYPE_PERSONAL_SERVER      17
+#define MACH_TYPE_ITSY                 18
+#define MACH_TYPE_L7200                19
+#define MACH_TYPE_PLEB                 20
+#define MACH_TYPE_INTEGRATOR           21
+#define MACH_TYPE_H3600                22
+#define MACH_TYPE_IXP1200              23
+#define MACH_TYPE_P720T                24
+#define MACH_TYPE_ASSABET              25
+#define MACH_TYPE_VICTOR               26
+#define MACH_TYPE_LART                 27
+#define MACH_TYPE_RANGER               28
+#define MACH_TYPE_GRAPHICSCLIENT       29
+#define MACH_TYPE_XP860                30
+#define MACH_TYPE_CERF                 31
+#define MACH_TYPE_NANOENGINE           32
+#define MACH_TYPE_FPIC                 33
+#define MACH_TYPE_EXTENEX1             34
+#define MACH_TYPE_SHERMAN              35
+#define MACH_TYPE_ACCELENT_SA          36
+#define MACH_TYPE_ACCELENT_L7200       37
+#define MACH_TYPE_NETPORT              38
+#define MACH_TYPE_PANGOLIN             39
+#define MACH_TYPE_YOPY                 40
+#define MACH_TYPE_COOLIDGE             41
+#define MACH_TYPE_HUW_WEBPANEL         42
+#define MACH_TYPE_SPOTME               43
+#define MACH_TYPE_FREEBIRD             44
+#define MACH_TYPE_TI925                45
+#define MACH_TYPE_RISCSTATION          46
+#define MACH_TYPE_CAVY                 47
+#define MACH_TYPE_JORNADA720           48
+#define MACH_TYPE_OMNIMETER            49
+#define MACH_TYPE_EDB7211              50
+#define MACH_TYPE_CITYGO               51
+#define MACH_TYPE_PFS168               52
+#define MACH_TYPE_SPOT                 53
+#define MACH_TYPE_FLEXANET             54
+#define MACH_TYPE_WEBPAL               55
+#define MACH_TYPE_LINPDA               56
+#define MACH_TYPE_ANAKIN               57
+#define MACH_TYPE_MVI                  58
+#define MACH_TYPE_JUPITER              59
+#define MACH_TYPE_PSIONW               60
+#define MACH_TYPE_ALN                  61
+#define MACH_TYPE_CAMELOT              62
+#define MACH_TYPE_GDS2200              63
+#define MACH_TYPE_PSION_SERIES7        64
+#define MACH_TYPE_XFILE                65
+#define MACH_TYPE_ACCELENT_EP9312      66
+#define MACH_TYPE_IC200                67
+#define MACH_TYPE_CREDITLART           68
+#define MACH_TYPE_HTM                  69
+#define MACH_TYPE_IQ80310              70
+#define MACH_TYPE_FREEBOT              71
+#define MACH_TYPE_ENTEL                72
+#define MACH_TYPE_ENP3510              73
+#define MACH_TYPE_TRIZEPS              74
+#define MACH_TYPE_NESA                 75
+#define MACH_TYPE_VENUS                76
+#define MACH_TYPE_TARDIS               77
+#define MACH_TYPE_MERCURY              78
+#define MACH_TYPE_EMPEG                79
+#define MACH_TYPE_I80200FCC            80
+#define MACH_TYPE_ITT_CPB              81
+#define MACH_TYPE_SVC                  82
+#define MACH_TYPE_ALPHA2               84
+#define MACH_TYPE_ALPHA1               85
+#define MACH_TYPE_NETARM               86
+#define MACH_TYPE_SIMPAD               87
+#define MACH_TYPE_PDA1                 88
+#define MACH_TYPE_LUBBOCK              89
+#define MACH_TYPE_ANIKO                90
+#define MACH_TYPE_CLEP7212             91
+#define MACH_TYPE_CS89712              92
+#define MACH_TYPE_WEARARM              93
+#define MACH_TYPE_POSSIO_PX            94
+#define MACH_TYPE_SIDEARM              95
+#define MACH_TYPE_STORK                96
+#define MACH_TYPE_SHANNON              97
+#define MACH_TYPE_ACE                  98
+#define MACH_TYPE_BALLYARM             99
+#define MACH_TYPE_SIMPUTER             100
+#define MACH_TYPE_NEXTERM              101
+#define MACH_TYPE_SA1100_ELF           102
+#define MACH_TYPE_GATOR                103
+#define MACH_TYPE_GRANITE              104
+#define MACH_TYPE_CONSUS               105
+#define MACH_TYPE_AAED2000             106
+#define MACH_TYPE_CDB89712             107
+#define MACH_TYPE_GRAPHICSMASTER       108
+#define MACH_TYPE_ADSBITSY             109
+#define MACH_TYPE_PXA_IDP              110
+#define MACH_TYPE_PLCE                 111
+#define MACH_TYPE_PT_SYSTEM3           112
+#define MACH_TYPE_MEDALB               113
+#define MACH_TYPE_EAGLE                114
+#define MACH_TYPE_DSC21                115
+#define MACH_TYPE_DSC24                116
+#define MACH_TYPE_TI5472               117
+#define MACH_TYPE_AUTCPU12             118
+#define MACH_TYPE_UENGINE              119
+#define MACH_TYPE_BLUESTEM             120
+#define MACH_TYPE_XINGU8               121
+#define MACH_TYPE_BUSHSTB              122
+#define MACH_TYPE_EPSILON1             123
+#define MACH_TYPE_BALLOON              124
+#define MACH_TYPE_PUPPY                125
+#define MACH_TYPE_ELROY                126
+#define MACH_TYPE_GMS720               127
+#define MACH_TYPE_S24X                 128
+#define MACH_TYPE_JTEL_CLEP7312        129
+#define MACH_TYPE_CX821XX              130
+#define MACH_TYPE_EDB7312              131
+#define MACH_TYPE_BSA1110              132
+#define MACH_TYPE_POWERPIN             133
+#define MACH_TYPE_OPENARM              134
+#define MACH_TYPE_WHITECHAPEL          135
+#define MACH_TYPE_H3100                136
+#define MACH_TYPE_H3800                137
+#define MACH_TYPE_BLUE_V1              138
+#define MACH_TYPE_PXA_CERF             139
+#define MACH_TYPE_ARM7TEVB             140
+#define MACH_TYPE_D7400                141
+#define MACH_TYPE_PIRANHA              142
+#define MACH_TYPE_SBCAMELOT            143
+#define MACH_TYPE_KINGS                144
+#define MACH_TYPE_SMDK2400             145
+#define MACH_TYPE_COLLIE               146
+#define MACH_TYPE_IDR                  147
+#define MACH_TYPE_BADGE4               148
+#define MACH_TYPE_WEBNET               149
+#define MACH_TYPE_D7300                150
+#define MACH_TYPE_CEP                  151
+#define MACH_TYPE_FORTUNET             152
+#define MACH_TYPE_VC547X               153
+#define MACH_TYPE_FILEWALKER           154
+#define MACH_TYPE_NETGATEWAY           155
+#define MACH_TYPE_SYMBOL2800           156
+#define MACH_TYPE_SUNS                 157
+#define MACH_TYPE_FRODO                158
+#define MACH_TYPE_MACH_TYTE_MS301      159
+#define MACH_TYPE_MX1ADS               160
+#define MACH_TYPE_H7201                161
+#define MACH_TYPE_H7202                162
+#define MACH_TYPE_AMICO                163
+#define MACH_TYPE_IAM                  164
+#define MACH_TYPE_TT530                165
+#define MACH_TYPE_SAM2400              166
+#define MACH_TYPE_JORNADA56X           167
+#define MACH_TYPE_ACTIVE               168
+#define MACH_TYPE_IQ80321              169
+#define MACH_TYPE_WID                  170
+#define MACH_TYPE_SABINAL              171
+#define MACH_TYPE_IXP425_MATACUMBE     172
+#define MACH_TYPE_MINIPRINT            173
+#define MACH_TYPE_ADM510X              174
+#define MACH_TYPE_SVS200               175
+#define MACH_TYPE_ATG_TCU              176
+#define MACH_TYPE_JORNADA820           177
+#define MACH_TYPE_S3C44B0              178
+#define MACH_TYPE_MARGIS2              179
+#define MACH_TYPE_KS8695               180
+#define MACH_TYPE_BRH                  181
+#define MACH_TYPE_S3C2410              182
+#define MACH_TYPE_POSSIO_PX30          183
+#define MACH_TYPE_S3C2800              184
+#define MACH_TYPE_FLEETWOOD            185
+#define MACH_TYPE_OMAHA                186
+#define MACH_TYPE_TA7                  187
+#define MACH_TYPE_NOVA                 188
+#define MACH_TYPE_HMK                  189
+#define MACH_TYPE_KARO                 190
+#define MACH_TYPE_FESTER               191
+#define MACH_TYPE_GPI                  192
+#define MACH_TYPE_SMDK2410             193
+#define MACH_TYPE_I519                 194
+#define MACH_TYPE_NEXIO                195
+#define MACH_TYPE_BITBOX               196
+#define MACH_TYPE_G200                 197
+#define MACH_TYPE_GILL                 198
+#define MACH_TYPE_PXA_MERCURY          199
+#define MACH_TYPE_CEIVA                200
+#define MACH_TYPE_FRET                 201
+#define MACH_TYPE_EMAILPHONE           202
+#define MACH_TYPE_H3900                203
+#define MACH_TYPE_PXA1                 204
+#define MACH_TYPE_KOAN369              205
+#define MACH_TYPE_COGENT               206
+#define MACH_TYPE_ESL_SIMPUTER         207
+#define MACH_TYPE_ESL_SIMPUTER_CLR     208
+#define MACH_TYPE_ESL_SIMPUTER_BW      209
+#define MACH_TYPE_HHP_CRADLE           210
+#define MACH_TYPE_HE500                211
+#define MACH_TYPE_INHANDELF2           212
+#define MACH_TYPE_INHANDFTIP           213
+#define MACH_TYPE_DNP1110              214
+#define MACH_TYPE_PNP1110              215
+#define MACH_TYPE_CSB226               216
+#define MACH_TYPE_ARNOLD               217
+#define MACH_TYPE_VOICEBLUE            218
+#define MACH_TYPE_JZ8028               219
+#define MACH_TYPE_H5400                220
+#define MACH_TYPE_FORTE                221
+#define MACH_TYPE_ACAM                 222
+#define MACH_TYPE_ABOX                 223
+#define MACH_TYPE_ATMEL                224
+#define MACH_TYPE_SITSANG              225
+#define MACH_TYPE_CPU1110LCDNET        226
+#define MACH_TYPE_MPL_VCMA9            227
+#define MACH_TYPE_OPUS_A1              228
+#define MACH_TYPE_DAYTONA              229
+#define MACH_TYPE_KILLBEAR             230
+#define MACH_TYPE_YOHO                 231
+#define MACH_TYPE_JASPER               232
+#define MACH_TYPE_DSC25                233
+#define MACH_TYPE_OMAP_INNOVATOR       234
+#define MACH_TYPE_RAMSES               235
+#define MACH_TYPE_S28X                 236
+#define MACH_TYPE_MPORT3               237
+#define MACH_TYPE_PXA_EAGLE250         238
+#define MACH_TYPE_PDB                  239
+#define MACH_TYPE_BLUE_2G              240
+#define MACH_TYPE_BLUEARCH             241
+#define MACH_TYPE_IXDP2400             242
+#define MACH_TYPE_IXDP2800             243
+#define MACH_TYPE_EXPLORER             244
+#define MACH_TYPE_IXDP425              245
+#define MACH_TYPE_CHIMP                246
+#define MACH_TYPE_STORK_NEST           247
+#define MACH_TYPE_STORK_EGG            248
+#define MACH_TYPE_WISMO                249
+#define MACH_TYPE_EZLINX               250
+#define MACH_TYPE_AT91RM9200           251
+#define MACH_TYPE_ADTECH_ORION         252
+#define MACH_TYPE_NEPTUNE              253
+#define MACH_TYPE_HACKKIT              254
+#define MACH_TYPE_PXA_WINS30           255
+#define MACH_TYPE_LAVINNA              256
+#define MACH_TYPE_PXA_UENGINE          257
+#define MACH_TYPE_INNOKOM              258
+#define MACH_TYPE_BMS                  259
+#define MACH_TYPE_IXCDP1100            260
+#define MACH_TYPE_PRPMC1100            261
+#define MACH_TYPE_AT91RM9200DK         262
+#define MACH_TYPE_ARMSTICK             263
+#define MACH_TYPE_ARMONIE              264
+#define MACH_TYPE_MPORT1               265
+#define MACH_TYPE_S3C5410              266
+#define MACH_TYPE_ZCP320A              267
+#define MACH_TYPE_I_BOX                268
+#define MACH_TYPE_STLC1502             269
+#define MACH_TYPE_SIREN                270
+#define MACH_TYPE_GREENLAKE            271
+#define MACH_TYPE_ARGUS                272
+#define MACH_TYPE_COMBADGE             273
+#define MACH_TYPE_ROKEPXA              274
+#define MACH_TYPE_CINTEGRATOR          275
+#define MACH_TYPE_GUIDEA07             276
+#define MACH_TYPE_TAT257               277
+#define MACH_TYPE_IGP2425              278
+#define MACH_TYPE_BLUEGRAMMA           279
+#define MACH_TYPE_IPOD                 280
+#define MACH_TYPE_ADSBITSYX            281
+#define MACH_TYPE_TRIZEPS2             282
+#define MACH_TYPE_VIPER                283
+#define MACH_TYPE_ADSBITSYPLUS         284
+#define MACH_TYPE_ADSAGC               285
+#define MACH_TYPE_STP7312              286
+#define MACH_TYPE_NX_PHNX              287
+#define MACH_TYPE_WEP_EP250            288
+#define MACH_TYPE_INHANDELF3           289
+#define MACH_TYPE_ADI_COYOTE           290
+#define MACH_TYPE_IYONIX               291
+#define MACH_TYPE_DAMICAM_SA1110       292
+#define MACH_TYPE_MEG03                293
+#define MACH_TYPE_PXA_WHITECHAPEL      294
+#define MACH_TYPE_NWSC                 295
+#define MACH_TYPE_NWLARM               296
+#define MACH_TYPE_IXP425_MGUARD        297
+#define MACH_TYPE_PXA_NETDCU4          298
+#define MACH_TYPE_IXDP2401             299
+#define MACH_TYPE_IXDP2801             300
+#define MACH_TYPE_ZODIAC               301
+#define MACH_TYPE_ARMMODUL             302
+#define MACH_TYPE_KETOP                303
+#define MACH_TYPE_AV7200               304
+#define MACH_TYPE_ARCH_TI925           305
+#define MACH_TYPE_ACQ200               306
+#define MACH_TYPE_PT_DAFIT             307
+#define MACH_TYPE_IHBA                 308
+#define MACH_TYPE_QUINQUE              309
+#define MACH_TYPE_NIMBRAONE            310
+#define MACH_TYPE_NIMBRA29X            311
+#define MACH_TYPE_NIMBRA210            312
+#define MACH_TYPE_HHP_D95XX            313
+#define MACH_TYPE_LABARM               314
+#define MACH_TYPE_M825XX               315
+#define MACH_TYPE_M7100                316
+#define MACH_TYPE_NIPC2                317
+#define MACH_TYPE_FU7202               318
+#define MACH_TYPE_ADSAGX               319
+#define MACH_TYPE_PXA_POOH             320
+#define MACH_TYPE_BANDON               321
+#define MACH_TYPE_PCM7210              322
+#define MACH_TYPE_NMS9200              323
+#define MACH_TYPE_LOGODL               324
+#define MACH_TYPE_M7140                325
+#define MACH_TYPE_KOREBOT              326
+#define MACH_TYPE_IQ31244              327
+#define MACH_TYPE_KOAN393              328
+#define MACH_TYPE_INHANDFTIP3          329
+#define MACH_TYPE_GONZO                330
+#define MACH_TYPE_BAST                 331
+#define MACH_TYPE_SCANPASS             332
+#define MACH_TYPE_EP7312_POOH          333
+#define MACH_TYPE_TA7S                 334
+#define MACH_TYPE_TA7V                 335
+#define MACH_TYPE_ICARUS               336
+#define MACH_TYPE_H1900                337
+#define MACH_TYPE_GEMINI               338
+#define MACH_TYPE_AXIM                 339
+#define MACH_TYPE_AUDIOTRON            340
+#define MACH_TYPE_H2200                341
+#define MACH_TYPE_LOOX600              342
+#define MACH_TYPE_NIOP                 343
+#define MACH_TYPE_DM310                344
+#define MACH_TYPE_SEEDPXA_C2           345
+#define MACH_TYPE_IXP4XX_MGUARD_PCI    346
+#define MACH_TYPE_H1940                347
+#define MACH_TYPE_SCORPIO              348
+#define MACH_TYPE_VIVA                 349
+#define MACH_TYPE_PXA_XCARD            350
+#define MACH_TYPE_CSB335               351
+#define MACH_TYPE_IXRD425              352
+#define MACH_TYPE_IQ80315              353
+#define MACH_TYPE_NMP7312              354
+#define MACH_TYPE_CX861XX              355
+#define MACH_TYPE_ENP2611              356
+#define MACH_TYPE_XDA                  357
+#define MACH_TYPE_CSIR_IMS             358
+#define MACH_TYPE_IXP421_DNAEETH       359
+#define MACH_TYPE_POCKETSERV9200       360
+#define MACH_TYPE_TOTO                 361
+#define MACH_TYPE_S3C2440              362
+#define MACH_TYPE_KS8695P              363
+#define MACH_TYPE_SE4000               364
+#define MACH_TYPE_QUADRICEPS           365
+#define MACH_TYPE_BRONCO               366
+#define MACH_TYPE_ESL_WIRELESS_TAB     367
+#define MACH_TYPE_ESL_SOFCOMP          368
+#define MACH_TYPE_S5C7375              369
+#define MACH_TYPE_SPEARHEAD            370
+#define MACH_TYPE_PANTERA              371
+#define MACH_TYPE_PRAYOGLITE           372
+#define MACH_TYPE_GUMSTIX              373
+#define MACH_TYPE_RCUBE                374
+#define MACH_TYPE_REA_OLV              375
+#define MACH_TYPE_PXA_IPHONE           376
+#define MACH_TYPE_S3C3410              377
+#define MACH_TYPE_ESPD_4510B           378
+#define MACH_TYPE_MP1X                 379
+#define MACH_TYPE_AT91RM9200TB         380
+#define MACH_TYPE_ADSVGX               381
+#define MACH_TYPE_OMAP_H2              382
+#define MACH_TYPE_PELEE                383
+#define MACH_TYPE_E740                 384
+#define MACH_TYPE_IQ80331              385
+#define MACH_TYPE_VERSATILE_PB         387
+#define MACH_TYPE_KEV7A400             388
+#define MACH_TYPE_LPD7A400             389
+#define MACH_TYPE_LPD7A404             390
+#define MACH_TYPE_FUJITSU_CAMELOT      391
+#define MACH_TYPE_JANUS2M              392
+#define MACH_TYPE_EMBTF                393
+#define MACH_TYPE_HPM                  394
+#define MACH_TYPE_SMDK2410TK           395
+#define MACH_TYPE_SMDK2410AJ           396
+#define MACH_TYPE_STREETRACER          397
+#define MACH_TYPE_EFRAME               398
+#define MACH_TYPE_CSB337               399
+#define MACH_TYPE_PXA_LARK             400
+#define MACH_TYPE_PNP2110              401
+#define MACH_TYPE_TCC72X               402
+#define MACH_TYPE_ALTAIR               403
+#define MACH_TYPE_KC3                  404
+#define MACH_TYPE_SINTEFTD             405
+#define MACH_TYPE_MAINSTONE            406
+#define MACH_TYPE_ADAY4X               407
+#define MACH_TYPE_LITE300              408
+#define MACH_TYPE_S5C7376              409
+#define MACH_TYPE_MT02                 410
+#define MACH_TYPE_MPORT3S              411
+#define MACH_TYPE_RA_ALPHA             412
+#define MACH_TYPE_XCEP                 413
+#define MACH_TYPE_ARCOM_VULCAN         414
+#define MACH_TYPE_STARGATE             415
+#define MACH_TYPE_ARMADILLOJ           416
+#define MACH_TYPE_ELROY_JACK           417
+#define MACH_TYPE_BACKEND              418
+#define MACH_TYPE_S5LINBOX             419
+#define MACH_TYPE_NOMADIK              420
+#define MACH_TYPE_IA_CPU_9200          421
+#define MACH_TYPE_AT91_BJA1            422
+#define MACH_TYPE_CORGI                423
+#define MACH_TYPE_POODLE               424
+#define MACH_TYPE_TEN                  425
+#define MACH_TYPE_ROVERP5P             426
+#define MACH_TYPE_SC2700               427
+#define MACH_TYPE_EX_EAGLE             428
+#define MACH_TYPE_NX_PXA12             429
+#define MACH_TYPE_NX_PXA5              430
+#define MACH_TYPE_BLACKBOARD2          431
+#define MACH_TYPE_I819                 432
+#define MACH_TYPE_IXMB995E             433
+#define MACH_TYPE_SKYRIDER             434
+#define MACH_TYPE_SKYHAWK              435
+#define MACH_TYPE_ENTERPRISE           436
+#define MACH_TYPE_DEP2410              437
+#define MACH_TYPE_ARMCORE              438
+#define MACH_TYPE_HOBBIT               439
+#define MACH_TYPE_H7210                440
+#define MACH_TYPE_PXA_NETDCU5          441
+#define MACH_TYPE_ACC                  442
+#define MACH_TYPE_ESL_SARVA            443
+#define MACH_TYPE_XM250                444
+#define MACH_TYPE_T6TC1XB              445
+#define MACH_TYPE_ESS710               446
+#define MACH_TYPE_MX31ADS              447
+#define MACH_TYPE_HIMALAYA             448
+#define MACH_TYPE_BOLFENK              449
+#define MACH_TYPE_AT91RM9200KR         450
+#define MACH_TYPE_EDB9312              451
+#define MACH_TYPE_OMAP_GENERIC         452
+#define MACH_TYPE_AXIMX3               453
+#define MACH_TYPE_EB67XDIP             454
+#define MACH_TYPE_WEBTXS               455
+#define MACH_TYPE_HAWK                 456
+#define MACH_TYPE_CCAT91SBC001         457
+#define MACH_TYPE_EXPRESSO             458
+#define MACH_TYPE_H4000                459
+#define MACH_TYPE_DINO                 460
+#define MACH_TYPE_ML675K               461
+#define MACH_TYPE_EDB9301              462
+#define MACH_TYPE_EDB9315              463
+#define MACH_TYPE_RECIVA_TT            464
+#define MACH_TYPE_CSTCB01              465
+#define MACH_TYPE_CSTCB1               466
+#define MACH_TYPE_SHADWELL             467
+#define MACH_TYPE_GOEPEL263            468
+#define MACH_TYPE_ACQ100               469
+#define MACH_TYPE_MX1FS2               470
+#define MACH_TYPE_HIPTOP_G1            471
+#define MACH_TYPE_SPARKY               472
+#define MACH_TYPE_NS9750               473
+#define MACH_TYPE_PHOENIX              474
+#define MACH_TYPE_VR1000               475
+#define MACH_TYPE_DEISTERPXA           476
+#define MACH_TYPE_BCM1160              477
+#define MACH_TYPE_PCM022               478
+#define MACH_TYPE_ADSGCX               479
+#define MACH_TYPE_DREADNAUGHT          480
+#define MACH_TYPE_DM320                481
+#define MACH_TYPE_MARKOV               482
+#define MACH_TYPE_COS7A400             483
+#define MACH_TYPE_MILANO               484
+#define MACH_TYPE_UE9328               485
+#define MACH_TYPE_UEX255               486
+#define MACH_TYPE_UE2410               487
+#define MACH_TYPE_A620                 488
+#define MACH_TYPE_OCELOT               489
+#define MACH_TYPE_CHEETAH              490
+#define MACH_TYPE_OMAP_PERSEUS2        491
+#define MACH_TYPE_ZVUE                 492
+#define MACH_TYPE_ROVERP1              493
+#define MACH_TYPE_ASIDIAL2             494
+#define MACH_TYPE_S3C24A0              495
+#define MACH_TYPE_E800                 496
+#define MACH_TYPE_E750                 497
+#define MACH_TYPE_S3C5500              498
+#define MACH_TYPE_SMDK5500             499
+#define MACH_TYPE_SIGNALSYNC           500
+#define MACH_TYPE_NBC                  501
+#define MACH_TYPE_KODIAK               502
+#define MACH_TYPE_NETBOOKPRO           503
+#define MACH_TYPE_HW90200              504
+#define MACH_TYPE_CONDOR               505
+#define MACH_TYPE_CUP                  506
+#define MACH_TYPE_KITE                 507
+#define MACH_TYPE_SCB9328              508
+#define MACH_TYPE_OMAP_H3              509
+#define MACH_TYPE_OMAP_H4              510
+#define MACH_TYPE_N10                  511
+#define MACH_TYPE_MONTAJADE            512
+#define MACH_TYPE_SG560                513
+#define MACH_TYPE_DP1000               514
+#define MACH_TYPE_OMAP_OSK             515
+#define MACH_TYPE_RG100V3              516
+#define MACH_TYPE_MX2ADS               517
+#define MACH_TYPE_PXA_KILO             518
+#define MACH_TYPE_IXP4XX_EAGLE         519
+#define MACH_TYPE_TOSA                 520
+#define MACH_TYPE_MB2520F              521
+#define MACH_TYPE_EMC1000              522
+#define MACH_TYPE_TIDSC25              523
+#define MACH_TYPE_AKCPMXL              524
+#define MACH_TYPE_AV3XX                525
+#define MACH_TYPE_AVILA                526
+#define MACH_TYPE_PXA_MPM10            527
+#define MACH_TYPE_PXA_KYANITE          528
+#define MACH_TYPE_SGOLD                529
+#define MACH_TYPE_OSCAR                530
+#define MACH_TYPE_EPXA4USB2            531
+#define MACH_TYPE_XSENGINE             532
+#define MACH_TYPE_IP600                533
+#define MACH_TYPE_MCAN2                534
+#define MACH_TYPE_DDI_BLUERIDGE        535
+#define MACH_TYPE_SKYMINDER            536
+#define MACH_TYPE_LPD79520             537
+#define MACH_TYPE_EDB9302              538
+#define MACH_TYPE_HW90340              539
+#define MACH_TYPE_CIP_BOX              540
+#define MACH_TYPE_IVPN                 541
+#define MACH_TYPE_RSOC2                542
+#define MACH_TYPE_HUSKY                543
+#define MACH_TYPE_BOXER                544
+#define MACH_TYPE_SHEPHERD             545
+#define MACH_TYPE_AML42800AA           546
+#define MACH_TYPE_LPC2294              548
+#define MACH_TYPE_SWITCHGRASS          549
+#define MACH_TYPE_ENS_CMU              550
+#define MACH_TYPE_MM6_SDB              551
+#define MACH_TYPE_SATURN               552
+#define MACH_TYPE_I30030EVB            553
+#define MACH_TYPE_MXC27530EVB          554
+#define MACH_TYPE_SMDK2800             555
+#define MACH_TYPE_MTWILSON             556
+#define MACH_TYPE_ZITI                 557
+#define MACH_TYPE_GRANDFATHER          558
+#define MACH_TYPE_TENGINE              559
+#define MACH_TYPE_S3C2460              560
+#define MACH_TYPE_PDM                  561
+#define MACH_TYPE_H4700                562
+#define MACH_TYPE_H6300                563
+#define MACH_TYPE_RZ1700               564
+#define MACH_TYPE_A716                 565
+#define MACH_TYPE_ESTK2440A            566
+#define MACH_TYPE_ATWIXP425            567
+#define MACH_TYPE_CSB336               568
+#define MACH_TYPE_RIRM2                569
+#define MACH_TYPE_CX23518              570
+#define MACH_TYPE_CX2351X              571
+#define MACH_TYPE_COMPUTIME            572
+#define MACH_TYPE_IZARUS               573
+#define MACH_TYPE_RTS                  574
+#define MACH_TYPE_SE5100               575
+#define MACH_TYPE_S3C2510              576
+#define MACH_TYPE_CSB437TL             577
+#define MACH_TYPE_SLAUSON              578
+#define MACH_TYPE_PEARLRIVER           579
+#define MACH_TYPE_TDC_P210             580
+#define MACH_TYPE_SG580                581
+#define MACH_TYPE_WRSBCARM7            582
+#define MACH_TYPE_IPD                  583
+#define MACH_TYPE_PXA_DNP2110          584
+#define MACH_TYPE_XAENIAX              585
+#define MACH_TYPE_SOMN4250             586
+#define MACH_TYPE_PLEB2                587
+#define MACH_TYPE_CORNWALLIS           588
+#define MACH_TYPE_GURNEY_DRV           589
+#define MACH_TYPE_CHAFFEE              590
+#define MACH_TYPE_RMS101               591
+#define MACH_TYPE_RX3715               592
+#define MACH_TYPE_SWIFT                593
+#define MACH_TYPE_ROVERP7              594
+#define MACH_TYPE_PR818S               595
+#define MACH_TYPE_TRXPRO               596
+#define MACH_TYPE_NSLU2                597
+#define MACH_TYPE_E400                 598
+#define MACH_TYPE_TRAB                 599
+#define MACH_TYPE_CMC_PU2              600
+#define MACH_TYPE_FULCRUM              601
+#define MACH_TYPE_NETGATE42X           602
+#define MACH_TYPE_STR710               603
+#define MACH_TYPE_IXDPG425             604
+#define MACH_TYPE_TOMTOMGO             605
+#define MACH_TYPE_VERSATILE_AB         606
+#define MACH_TYPE_EDB9307              607
+#define MACH_TYPE_SG565                608
+#define MACH_TYPE_LPD79524             609
+#define MACH_TYPE_LPD79525             610
+#define MACH_TYPE_RMS100               611
+#define MACH_TYPE_KB9200               612
+#define MACH_TYPE_SX1                  613
+#define MACH_TYPE_HMS39C7092           614
+#define MACH_TYPE_ARMADILLO            615
+#define MACH_TYPE_IPCU                 616
+#define MACH_TYPE_LOOX720              617
+#define MACH_TYPE_IXDP465              618
+#define MACH_TYPE_IXDP2351             619
+#define MACH_TYPE_ADSVIX               620
+#define MACH_TYPE_DM270                621
+#define MACH_TYPE_SOCLTPLUS            622
+#define MACH_TYPE_ECIA                 623
+#define MACH_TYPE_CM4008               624
+#define MACH_TYPE_P2001                625
+#define MACH_TYPE_MUDSHARK             627
+#define MACH_TYPE_HB2                  628
+#define MACH_TYPE_IQ80332              629
+#define MACH_TYPE_SENDT                630
+#define MACH_TYPE_MX2JAZZ              631
+#define MACH_TYPE_MULTIIO              632
+#define MACH_TYPE_HRDISPLAY            633
+#define MACH_TYPE_MXC27530ADS          634
+#define MACH_TYPE_TRIZEPS3             635
+#define MACH_TYPE_ZEFEERDZA            636
+#define MACH_TYPE_ZEFEERDZB            637
+#define MACH_TYPE_ZEFEERDZG            638
+#define MACH_TYPE_ZEFEERDZN            639
+#define MACH_TYPE_ZEFEERDZQ            640
+#define MACH_TYPE_GTWX5715             641
+#define MACH_TYPE_ASTRO_JACK           643
+#define MACH_TYPE_TIP03                644
+#define MACH_TYPE_A9200EC              645
+#define MACH_TYPE_PNX0105              646
+#define MACH_TYPE_ADCPOECPU            647
+#define MACH_TYPE_CSB637               648
+#define MACH_TYPE_MB9200               650
+#define MACH_TYPE_KULUN                651
+#define MACH_TYPE_SNAPPER              652
+#define MACH_TYPE_OPTIMA               653
+#define MACH_TYPE_DLHSBC               654
+#define MACH_TYPE_X30                  655
+#define MACH_TYPE_N30                  656
+#define MACH_TYPE_MANGA_KS8695         657
+#define MACH_TYPE_AJAX                 658
+#define MACH_TYPE_NEC_MP900            659
+#define MACH_TYPE_VVTK1000             661
+#define MACH_TYPE_KAFA                 662
+#define MACH_TYPE_VVTK3000             663
+#define MACH_TYPE_PIMX1                664
+#define MACH_TYPE_OLLIE                665
+#define MACH_TYPE_SKYMAX               666
+#define MACH_TYPE_JAZZ                 667
+#define MACH_TYPE_TEL_T3               668
+#define MACH_TYPE_AISINO_FCR255        669
+#define MACH_TYPE_BTWEB                670
+#define MACH_TYPE_DBG_LH79520          671
+#define MACH_TYPE_CM41XX               672
+#define MACH_TYPE_TS72XX               673
+#define MACH_TYPE_NGGPXA               674
+#define MACH_TYPE_CSB535               675
+#define MACH_TYPE_CSB536               676
+#define MACH_TYPE_PXA_TRAKPOD          677
+#define MACH_TYPE_PRAXIS               678
+#define MACH_TYPE_LH75411              679
+#define MACH_TYPE_OTOM                 680
+#define MACH_TYPE_NEXCODER_2440        681
+#define MACH_TYPE_LOOX410              682
+#define MACH_TYPE_WESTLAKE             683
+#define MACH_TYPE_NSB                  684
+#define MACH_TYPE_ESL_SARVA_STN        685
+#define MACH_TYPE_ESL_SARVA_TFT        686
+#define MACH_TYPE_ESL_SARVA_IAD        687
+#define MACH_TYPE_ESL_SARVA_ACC        688
+#define MACH_TYPE_TYPHOON              689
+#define MACH_TYPE_CNAV                 690
+#define MACH_TYPE_A730                 691
+#define MACH_TYPE_NETSTAR              692
+#define MACH_TYPE_PHASEFALE_SUPERCON   693
+#define MACH_TYPE_SHIVA1100            694
+#define MACH_TYPE_ETEXSC               695
+#define MACH_TYPE_IXDPG465             696
+#define MACH_TYPE_A9M2410              697
+#define MACH_TYPE_A9M2440              698
+#define MACH_TYPE_A9M9750              699
+#define MACH_TYPE_A9M9360              700
+#define MACH_TYPE_UNC90                701
+#define MACH_TYPE_ECO920               702
+#define MACH_TYPE_SATVIEW              703
+#define MACH_TYPE_ROADRUNNER           704
+#define MACH_TYPE_AT91RM9200EK         705
+#define MACH_TYPE_GP32                 706
+#define MACH_TYPE_GEM                  707
+#define MACH_TYPE_I858                 708
+#define MACH_TYPE_HX2750               709
+#define MACH_TYPE_MXC91131EVB          710
+#define MACH_TYPE_P700                 711
+#define MACH_TYPE_CPE                  712
+#define MACH_TYPE_SPITZ                713
+#define MACH_TYPE_NIMBRA340            714
+#define MACH_TYPE_LPC22XX              715
+#define MACH_TYPE_COMET3               716
+#define MACH_TYPE_COMET4               717
+#define MACH_TYPE_CSB625               718
+#define MACH_TYPE_FORTUNET2            719
+#define MACH_TYPE_S5H2200              720
+#define MACH_TYPE_OPTORM920            721
+#define MACH_TYPE_ADSBITSYXB           722
+#define MACH_TYPE_ADSSPHERE            723
+#define MACH_TYPE_ADSPORTAL            724
+#define MACH_TYPE_LN2410SBC            725
+#define MACH_TYPE_CB3RUFC              726
+#define MACH_TYPE_MP2USB               727
+#define MACH_TYPE_NTNP425C             728
+#define MACH_TYPE_COLIBRI              729
+#define MACH_TYPE_PCM7220              730
+#define MACH_TYPE_GATEWAY7001          731
+#define MACH_TYPE_PCM027               732
+#define MACH_TYPE_CMPXA                733
+#define MACH_TYPE_ANUBIS               734
+#define MACH_TYPE_ITE8152              735
+#define MACH_TYPE_LPC3XXX              736
+#define MACH_TYPE_PUPPETEER            737
+#define MACH_TYPE_E570                 739
+#define MACH_TYPE_X50                  740
+#define MACH_TYPE_RECON                741
+#define MACH_TYPE_XBOARDGP8            742
+#define MACH_TYPE_FPIC2                743
+#define MACH_TYPE_AKITA                744
+#define MACH_TYPE_A81                  745
+#define MACH_TYPE_SVM_SC25X            746
+#define MACH_TYPE_VADATECH020          747
+#define MACH_TYPE_TLI                  748
+#define MACH_TYPE_EDB9315LC            749
+#define MACH_TYPE_PASSEC               750
+#define MACH_TYPE_DS_TIGER             751
+#define MACH_TYPE_E310                 752
+#define MACH_TYPE_E330                 753
+#define MACH_TYPE_RT3000               754
+#define MACH_TYPE_NOKIA770             755
+#define MACH_TYPE_PNX0106              756
+#define MACH_TYPE_HX21XX               757
+#define MACH_TYPE_FARADAY              758
+#define MACH_TYPE_SBC9312              759
+#define MACH_TYPE_BATMAN               760
+#define MACH_TYPE_JPD201               761
+#define MACH_TYPE_MIPSA                762
+#define MACH_TYPE_KACOM                763
+#define MACH_TYPE_SWARCOCPU            764
+#define MACH_TYPE_SWARCODSL            765
+#define MACH_TYPE_BLUEANGEL            766
+#define MACH_TYPE_HAIRYGRAMA           767
+#define MACH_TYPE_BANFF                768
+#define MACH_TYPE_CARMEVA              769
+#define MACH_TYPE_SAM255               770
+#define MACH_TYPE_PPM10                771
+#define MACH_TYPE_EDB9315A             772
+#define MACH_TYPE_SUNSET               773
+#define MACH_TYPE_STARGATE2            774
+#define MACH_TYPE_INTELMOTE2           775
+#define MACH_TYPE_TRIZEPS4             776
+#define MACH_TYPE_MAINSTONE2           777
+#define MACH_TYPE_EZ_IXP42X            778
+#define MACH_TYPE_TAPWAVE_ZODIAC       779
+#define MACH_TYPE_UNIVERSALMETER       780
+#define MACH_TYPE_HICOARM9             781
+#define MACH_TYPE_PNX4008              782
+#define MACH_TYPE_KWS6000              783
+#define MACH_TYPE_PORTUX920T           784
+#define MACH_TYPE_EZ_X5                785
+#define MACH_TYPE_OMAP_RUDOLPH         786
+#define MACH_TYPE_CPUAT91              787
+#define MACH_TYPE_REA9200              788
+#define MACH_TYPE_ACTS_PUNE_SA1110     789
+#define MACH_TYPE_IXP425               790
+#define MACH_TYPE_I30030ADS            791
+#define MACH_TYPE_PERCH                792
+#define MACH_TYPE_EIS05R1              793
+#define MACH_TYPE_PEPPERPAD            794
+#define MACH_TYPE_SB3010               795
+#define MACH_TYPE_RM9200               796
+#define MACH_TYPE_DMA03                797
+#define MACH_TYPE_ROAD_S101            798
+#define MACH_TYPE_IQ81340SC            799
+#define MACH_TYPE_IQ_NEXTGEN_B         800
+#define MACH_TYPE_IQ81340MC            801
+#define MACH_TYPE_IQ_NEXTGEN_D         802
+#define MACH_TYPE_IQ_NEXTGEN_E         803
+#define MACH_TYPE_MALLOW_AT91          804
+#define MACH_TYPE_CYBERTRACKER_I       805
+#define MACH_TYPE_GESBC931X            806
+#define MACH_TYPE_CENTIPAD             807
+#define MACH_TYPE_ARMSOC               808
+#define MACH_TYPE_SE4200               809
+#define MACH_TYPE_EMS197A              810
+#define MACH_TYPE_MICRO9               811
+#define MACH_TYPE_MICRO9L              812
+#define MACH_TYPE_UC5471DSP            813
+#define MACH_TYPE_SJ5471ENG            814
+#define MACH_TYPE_CMPXA26X             815
+#define MACH_TYPE_NC                   816
+#define MACH_TYPE_OMAP_PALMTE          817
+#define MACH_TYPE_AJAX52X              818
+#define MACH_TYPE_SIRIUSTAR            819
+#define MACH_TYPE_IODATA_HDLG          820
+#define MACH_TYPE_AT91RM9200UTL        821
+#define MACH_TYPE_BIOSAFE              822
+#define MACH_TYPE_MP1000               823
+#define MACH_TYPE_PARSY                824
+#define MACH_TYPE_CCXP                 825
+#define MACH_TYPE_OMAP_GSAMPLE         826
+#define MACH_TYPE_REALVIEW_EB          827
+#define MACH_TYPE_SAMOA                828
+#define MACH_TYPE_PALMT3               829
+#define MACH_TYPE_I878                 830
+#define MACH_TYPE_BORZOI               831
+#define MACH_TYPE_GECKO                832
+#define MACH_TYPE_DS101                833
+#define MACH_TYPE_OMAP_PALMTT2         834
+#define MACH_TYPE_PALMLD               835
+#define MACH_TYPE_CC9C                 836
+#define MACH_TYPE_SBC1670              837
+#define MACH_TYPE_IXDP28X5             838
+#define MACH_TYPE_OMAP_PALMTT          839
+#define MACH_TYPE_ML696K               840
+#define MACH_TYPE_ARCOM_ZEUS           841
+#define MACH_TYPE_OSIRIS               842
+#define MACH_TYPE_MAESTRO              843
+#define MACH_TYPE_PALMTE2              844
+#define MACH_TYPE_IXBBM                845
+#define MACH_TYPE_MX27ADS              846
+#define MACH_TYPE_AX8004               847
+#define MACH_TYPE_AT91SAM9261EK        848
+#define MACH_TYPE_LOFT                 849
+#define MACH_TYPE_MAGPIE               850
+#define MACH_TYPE_MX21ADS              851
+#define MACH_TYPE_MB87M3400            852
+#define MACH_TYPE_MGUARD_DELTA         853
+#define MACH_TYPE_DAVINCI_DVDP         854
+#define MACH_TYPE_HTCUNIVERSAL         855
+#define MACH_TYPE_TPAD                 856
+#define MACH_TYPE_ROVERP3              857
+#define MACH_TYPE_JORNADA928           858
+#define MACH_TYPE_MV88FXX81            859
+#define MACH_TYPE_STMP36XX             860
+#define MACH_TYPE_SXNI79524            861
+#define MACH_TYPE_AMS_DELTA            862
+#define MACH_TYPE_URANIUM              863
+#define MACH_TYPE_UCON                 864
+#define MACH_TYPE_NAS100D              865
+#define MACH_TYPE_L083_1000            866
+#define MACH_TYPE_EZX                  867
+#define MACH_TYPE_PNX5220              868
+#define MACH_TYPE_BUTTE                869
+#define MACH_TYPE_SRM2                 870
+#define MACH_TYPE_DSBR                 871
+#define MACH_TYPE_CRYSTALBALL          872
+#define MACH_TYPE_TINYPXA27X           873
+#define MACH_TYPE_HERBIE               874
+#define MACH_TYPE_MAGICIAN             875
+#define MACH_TYPE_CM4002               876
+#define MACH_TYPE_B4                   877
+#define MACH_TYPE_MAUI                 878
+#define MACH_TYPE_CYBERTRACKER_G       879
+#define MACH_TYPE_NXDKN                880
+#define MACH_TYPE_MIO8390              881
+#define MACH_TYPE_OMI_BOARD            882
+#define MACH_TYPE_MX21CIV              883
+#define MACH_TYPE_MAHI_CDAC            884
+#define MACH_TYPE_PALMTX               885
+#define MACH_TYPE_S3C2413              887
+#define MACH_TYPE_SAMSYS_EP0           888
+#define MACH_TYPE_WG302V1              889
+#define MACH_TYPE_WG302V2              890
+#define MACH_TYPE_EB42X                891
+#define MACH_TYPE_IQ331ES              892
+#define MACH_TYPE_COSYDSP              893
+#define MACH_TYPE_UPLAT7D              894
+#define MACH_TYPE_PTDAVINCI            895
+#define MACH_TYPE_MBUS                 896
+#define MACH_TYPE_NADIA2VB             897
+#define MACH_TYPE_R1000                898
+#define MACH_TYPE_HW90250              899
+#define MACH_TYPE_OMAP_2430SDP         900
+#define MACH_TYPE_DAVINCI_EVM          901
+#define MACH_TYPE_OMAP_TORNADO         902
+#define MACH_TYPE_OLOCREEK             903
+#define MACH_TYPE_PALMZ72              904
+#define MACH_TYPE_NXDB500              905
+#define MACH_TYPE_APF9328              906
+#define MACH_TYPE_OMAP_WIPOQ           907
+#define MACH_TYPE_OMAP_TWIP            908
+#define MACH_TYPE_TREO650              909
+#define MACH_TYPE_ACUMEN               910
+#define MACH_TYPE_XP100                911
+#define MACH_TYPE_FS2410               912
+#define MACH_TYPE_PXA270_CERF          913
+#define MACH_TYPE_SQ2FTLPALM           914
+#define MACH_TYPE_BSEMSERVER           915
+#define MACH_TYPE_NETCLIENT            916
+#define MACH_TYPE_PALMT5               917
+#define MACH_TYPE_PALMTC               918
+#define MACH_TYPE_OMAP_APOLLON         919
+#define MACH_TYPE_MXC30030EVB          920
+#define MACH_TYPE_REA_2D               921
+#define MACH_TYPE_TI3E524              922
+#define MACH_TYPE_ATEB9200             923
+#define MACH_TYPE_AUCKLAND             924
+#define MACH_TYPE_AK3320M              925
+#define MACH_TYPE_DURAMAX              926
+#define MACH_TYPE_N35                  927
+#define MACH_TYPE_PRONGHORN            928
+#define MACH_TYPE_FUNDY                929
+#define MACH_TYPE_LOGICPD_PXA270       930
+#define MACH_TYPE_CPU777               931
+#define MACH_TYPE_SIMICON9201          932
+#define MACH_TYPE_LEAP2_HPM            933
+#define MACH_TYPE_CM922TXA10           934
+#define MACH_TYPE_PXA                  935
+#define MACH_TYPE_SANDGATE2            936
+#define MACH_TYPE_SANDGATE2G           937
+#define MACH_TYPE_SANDGATE2P           938
+#define MACH_TYPE_FRED_JACK            939
+#define MACH_TYPE_TTG_COLOR1           940
+#define MACH_TYPE_NXEB500HMI           941
+#define MACH_TYPE_NETDCU8              942
+#define MACH_TYPE_NG_FVX538            944
+#define MACH_TYPE_NG_FVS338            945
+#define MACH_TYPE_PNX4103              946
+#define MACH_TYPE_HESDB                947
+#define MACH_TYPE_XSILO                948
+#define MACH_TYPE_ESPRESSO             949
+#define MACH_TYPE_EMLC                 950
+#define MACH_TYPE_SISTERON             951
+#define MACH_TYPE_RX1950               952
+#define MACH_TYPE_TSC_VENUS            953
+#define MACH_TYPE_DS101J               954
+#define MACH_TYPE_MXC30030ADS          955
+#define MACH_TYPE_FUJITSU_WIMAXSOC     956
+#define MACH_TYPE_DUALPCMODEM          957
+#define MACH_TYPE_GESBC9312            958
+#define MACH_TYPE_HTCAPACHE            959
+#define MACH_TYPE_IXDP435              960
+#define MACH_TYPE_CATPROVT100          961
+#define MACH_TYPE_PICOTUX1XX           962
+#define MACH_TYPE_PICOTUX2XX           963
+#define MACH_TYPE_DSMG600              964
+#define MACH_TYPE_EMPC2                965
+#define MACH_TYPE_VENTURA              966
+#define MACH_TYPE_PHIDGET_SBC          967
+#define MACH_TYPE_IJ3K                 968
+#define MACH_TYPE_PISGAH               969
+#define MACH_TYPE_OMAP_FSAMPLE         970
+#define MACH_TYPE_SG720                971
+#define MACH_TYPE_REDFOX               972
+#define MACH_TYPE_MYSH_EP9315_1        973
+#define MACH_TYPE_TPF106               974
+#define MACH_TYPE_AT91RM9200KG         975
+#define MACH_TYPE_SLEDB                976
+#define MACH_TYPE_ONTRACK              977
+#define MACH_TYPE_PM1200               978
+#define MACH_TYPE_ESS24XXX             979
+#define MACH_TYPE_COREMP7              980
+#define MACH_TYPE_NEXCODER_6446        981
+#define MACH_TYPE_STVC8380             982
+#define MACH_TYPE_TEKLYNX              983
+#define MACH_TYPE_CARBONADO            984
+#define MACH_TYPE_SYSMOS_MP730         985
+#define MACH_TYPE_SNAPPER_CL15         986
+#define MACH_TYPE_PGIGIM               987
+#define MACH_TYPE_PTX9160P2            988
+#define MACH_TYPE_DCORE1               989
+#define MACH_TYPE_VICTORPXA            990
+#define MACH_TYPE_MX2DTB               991
+#define MACH_TYPE_PXA_IREX_ER0100      992
+#define MACH_TYPE_OMAP_PALMZ71         993
+#define MACH_TYPE_BARTEC_DEG           994
+#define MACH_TYPE_HW50251              995
+#define MACH_TYPE_IBOX                 996
+#define MACH_TYPE_ATLASLH7A404         997
+#define MACH_TYPE_PT2026               998
+#define MACH_TYPE_HTCALPINE            999
+#define MACH_TYPE_BARTEC_VTU           1000
+#define MACH_TYPE_VCOREII              1001
+#define MACH_TYPE_PDNB3                1002
+#define MACH_TYPE_HTCBEETLES           1003
+#define MACH_TYPE_S3C6400              1004
+#define MACH_TYPE_S3C2443              1005
+#define MACH_TYPE_OMAP_LDK             1006
+#define MACH_TYPE_SMDK2460             1007
+#define MACH_TYPE_SMDK2440             1008
+#define MACH_TYPE_SMDK2412             1009
+#define MACH_TYPE_WEBBOX               1010
+#define MACH_TYPE_CWWNDP               1011
+#define MACH_TYPE_DRAGON               1012
+#define MACH_TYPE_OPENDO_CPU_BOARD     1013
+#define MACH_TYPE_CCM2200              1014
+#define MACH_TYPE_ETWARM               1015
+#define MACH_TYPE_M93030               1016
+#define MACH_TYPE_CC7U                 1017
+#define MACH_TYPE_MTT_RANGER           1018
+#define MACH_TYPE_NEXUS                1019
+#define MACH_TYPE_DESMAN               1020
+#define MACH_TYPE_BKDE303              1021
+#define MACH_TYPE_SMDK2413             1022
+#define MACH_TYPE_AML_M7200            1023
+#define MACH_TYPE_AML_M5900            1024
+#define MACH_TYPE_SG640                1025
+#define MACH_TYPE_EDG79524             1026
+#define MACH_TYPE_AI2410               1027
+#define MACH_TYPE_IXP465               1028
+#define MACH_TYPE_BALLOON3             1029
+#define MACH_TYPE_HEINS                1030
+#define MACH_TYPE_MPLUSEVA             1031
+#define MACH_TYPE_RT042                1032
+#define MACH_TYPE_CWIEM                1033
+#define MACH_TYPE_CM_X270              1034
+#define MACH_TYPE_CM_X255              1035
+#define MACH_TYPE_ESH_AT91             1036
+#define MACH_TYPE_SANDGATE3            1037
+#define MACH_TYPE_PRIMO                1038
+#define MACH_TYPE_GEMSTONE             1039
+#define MACH_TYPE_PRONGHORNMETRO       1040
+#define MACH_TYPE_SIDEWINDER           1041
+#define MACH_TYPE_PICOMOD1             1042
+#define MACH_TYPE_SG590                1043
+#define MACH_TYPE_AKAI9307             1044
+#define MACH_TYPE_FONTAINE             1045
+#define MACH_TYPE_WOMBAT               1046
+#define MACH_TYPE_ACQ300               1047
+#define MACH_TYPE_MOD_270              1048
+#define MACH_TYPE_VC0820               1049
+#define MACH_TYPE_ANI_AIM              1050
+#define MACH_TYPE_JELLYFISH            1051
+#define MACH_TYPE_AMANITA              1052
+#define MACH_TYPE_VLINK                1053
+#define MACH_TYPE_DEXFLEX              1054
+#define MACH_TYPE_EIGEN_TTQ            1055
+#define MACH_TYPE_ARCOM_TITAN          1056
+#define MACH_TYPE_TABLA                1057
+#define MACH_TYPE_MDIRAC3              1058
+#define MACH_TYPE_MRHFBP2              1059
+#define MACH_TYPE_AT91RM9200RB         1060
+#define MACH_TYPE_ANI_APM              1061
+#define MACH_TYPE_ELLA1                1062
+#define MACH_TYPE_INHAND_PXA27X        1063
+#define MACH_TYPE_INHAND_PXA25X        1064
+#define MACH_TYPE_EMPOS_XM             1065
+#define MACH_TYPE_EMPOS                1066
+#define MACH_TYPE_EMPOS_TINY           1067
+#define MACH_TYPE_EMPOS_SM             1068
+#define MACH_TYPE_EGRET                1069
+#define MACH_TYPE_OSTRICH              1070
+#define MACH_TYPE_N50                  1071
+#define MACH_TYPE_ECBAT91              1072
+#define MACH_TYPE_STAREAST             1073
+#define MACH_TYPE_DSPG_DW              1074
+#define MACH_TYPE_ONEARM               1075
+#define MACH_TYPE_MRG110_6             1076
+#define MACH_TYPE_WRT300NV2            1077
+#define MACH_TYPE_XM_BULVERDE          1078
+#define MACH_TYPE_MSM6100              1079
+#define MACH_TYPE_ETI_B1               1080
+#define MACH_TYPE_ZILOG_ZA9L           1081
+#define MACH_TYPE_BIT2440              1082
+#define MACH_TYPE_NBI                  1083
+#define MACH_TYPE_SMDK2443             1084
+#define MACH_TYPE_VDAVINCI             1085
+#define MACH_TYPE_ATC6                 1086
+#define MACH_TYPE_MULTMDW              1087
+#define MACH_TYPE_MBA2440              1088
+#define MACH_TYPE_ECSD                 1089
+#define MACH_TYPE_PALMZ31              1090
+#define MACH_TYPE_FSG                  1091
+#define MACH_TYPE_RAZOR101             1092
+#define MACH_TYPE_OPERA_TDM            1093
+#define MACH_TYPE_COMCERTO             1094
+#define MACH_TYPE_TB0319               1095
+#define MACH_TYPE_KWS8000              1096
+#define MACH_TYPE_B2                   1097
+#define MACH_TYPE_LCL54                1098
+#define MACH_TYPE_AT91SAM9260EK        1099
+#define MACH_TYPE_GLANTANK             1100
+#define MACH_TYPE_N2100                1101
+#define MACH_TYPE_N4100                1102
+#define MACH_TYPE_VERTICAL_RSC4        1103
+#define MACH_TYPE_SG8100               1104
+#define MACH_TYPE_IM42XX               1105
+#define MACH_TYPE_FTXX                 1106
+#define MACH_TYPE_LWFUSION             1107
+#define MACH_TYPE_QT2410               1108
+#define MACH_TYPE_KIXRP435             1109
+#define MACH_TYPE_CCW9C                1110
+#define MACH_TYPE_DABHS                1111
+#define MACH_TYPE_GZMX                 1112
+#define MACH_TYPE_IPNW100AP            1113
+#define MACH_TYPE_CC9P9360DEV          1114
+#define MACH_TYPE_CC9P9750DEV          1115
+#define MACH_TYPE_CC9P9360VAL          1116
+#define MACH_TYPE_CC9P9750VAL          1117
+#define MACH_TYPE_NX70V                1118
+#define MACH_TYPE_AT91RM9200DF         1119
+#define MACH_TYPE_SE_PILOT2            1120
+#define MACH_TYPE_MTCN_T800            1121
+#define MACH_TYPE_VCMX212              1122
+#define MACH_TYPE_LYNX                 1123
+#define MACH_TYPE_AT91SAM9260ID        1124
+#define MACH_TYPE_HW86052              1125
+#define MACH_TYPE_PILZ_PMI3            1126
+#define MACH_TYPE_EDB9302A             1127
+#define MACH_TYPE_EDB9307A             1128
+#define MACH_TYPE_CT_DFS               1129
+#define MACH_TYPE_PILZ_PMI4            1130
+#define MACH_TYPE_XCEEDNP_IXP          1131
+#define MACH_TYPE_SMDK2442B            1132
+#define MACH_TYPE_XNODE                1133
+#define MACH_TYPE_AIDX270              1134
+#define MACH_TYPE_REMA                 1135
+#define MACH_TYPE_BPS1000              1136
+#define MACH_TYPE_HW90350              1137
+#define MACH_TYPE_OMAP_3430SDP         1138
+#define MACH_TYPE_BLUETOUCH            1139
+#define MACH_TYPE_VSTMS                1140
+#define MACH_TYPE_XSBASE270            1141
+#define MACH_TYPE_AT91SAM9260EK_CN     1142
+#define MACH_TYPE_ADSTURBOXB           1143
+#define MACH_TYPE_OTI4110              1144
+#define MACH_TYPE_HME_PXA              1145
+#define MACH_TYPE_DEISTERDCA           1146
+#define MACH_TYPE_CES_SSEM2            1147
+#define MACH_TYPE_CES_MTR              1148
+#define MACH_TYPE_TDS_AVNG_SBC         1149
+#define MACH_TYPE_EVEREST              1150
+#define MACH_TYPE_PNX4010              1151
+#define MACH_TYPE_OXNAS                1152
+#define MACH_TYPE_FIORI                1153
+#define MACH_TYPE_ML1200               1154
+#define MACH_TYPE_PECOS                1155
+#define MACH_TYPE_NB2XXX               1156
+#define MACH_TYPE_HW6900               1157
+#define MACH_TYPE_CDCS_QUOLL           1158
+#define MACH_TYPE_QUICKSILVER          1159
+#define MACH_TYPE_UPLAT926             1160
+#define MACH_TYPE_DEP2410_THOMAS       1161
+#define MACH_TYPE_DTK2410              1162
+#define MACH_TYPE_CHILI                1163
+#define MACH_TYPE_DEMETER              1164
+#define MACH_TYPE_DIONYSUS             1165
+#define MACH_TYPE_AS352X               1166
+#define MACH_TYPE_SERVICE              1167
+#define MACH_TYPE_CS_E9301             1168
+#define MACH_TYPE_MICRO9M              1169
+#define MACH_TYPE_IA_MOSPCK            1170
+#define MACH_TYPE_QL201B               1171
+#define MACH_TYPE_BBM                  1174
+#define MACH_TYPE_EXXX                 1175
+#define MACH_TYPE_WMA11B               1176
+#define MACH_TYPE_PELCO_ATLAS          1177
+#define MACH_TYPE_G500                 1178
+#define MACH_TYPE_BUG                  1179
+#define MACH_TYPE_MX33ADS              1180
+#define MACH_TYPE_CHUB                 1181
+#define MACH_TYPE_NEO1973_GTA01        1182
+#define MACH_TYPE_W90N740              1183
+#define MACH_TYPE_MEDALLION_SA2410     1184
+#define MACH_TYPE_IA_CPU_9200_2        1185
+#define MACH_TYPE_DIMMRM9200           1186
+#define MACH_TYPE_PM9261               1187
+#define MACH_TYPE_ML7304               1189
+#define MACH_TYPE_UCP250               1190
+#define MACH_TYPE_INTBOARD             1191
+#define MACH_TYPE_GULFSTREAM           1192
+#define MACH_TYPE_LABQUEST             1193
+#define MACH_TYPE_VCMX313              1194
+#define MACH_TYPE_URG200               1195
+#define MACH_TYPE_CPUX255LCDNET        1196
+#define MACH_TYPE_NETDCU9              1197
+#define MACH_TYPE_NETDCU10             1198
+#define MACH_TYPE_DSPG_DGA             1199
+#define MACH_TYPE_DSPG_DVW             1200
+#define MACH_TYPE_SOLOS                1201
+#define MACH_TYPE_AT91SAM9263EK        1202
+#define MACH_TYPE_OSSTBOX              1203
+#define MACH_TYPE_KBAT9261             1204
+#define MACH_TYPE_CT1100               1205
+#define MACH_TYPE_AKCPPXA              1206
+#define MACH_TYPE_OCHAYA1020           1207
+#define MACH_TYPE_HITRACK              1208
+#define MACH_TYPE_SYME1                1209
+#define MACH_TYPE_SYHL1                1210
+#define MACH_TYPE_EMPCA400             1211
+#define MACH_TYPE_EM7210               1212
+#define MACH_TYPE_HTCHERMES            1213
+#define MACH_TYPE_ETI_C1               1214
+#define MACH_TYPE_AC100                1216
+#define MACH_TYPE_SNEETCH              1217
+#define MACH_TYPE_STUDENTMATE          1218
+#define MACH_TYPE_ZIR2410              1219
+#define MACH_TYPE_ZIR2413              1220
+#define MACH_TYPE_DLONIP3              1221
+#define MACH_TYPE_INSTREAM             1222
+#define MACH_TYPE_AMBARELLA            1223
+#define MACH_TYPE_NEVIS                1224
+#define MACH_TYPE_HTC_TRINITY          1225
+#define MACH_TYPE_QL202B               1226
+#define MACH_TYPE_VPAC270              1227
+#define MACH_TYPE_RD129                1228
+#define MACH_TYPE_HTCWIZARD            1229
+#define MACH_TYPE_TREO680              1230
+#define MACH_TYPE_TECON_TMEZON         1231
+#define MACH_TYPE_ZYLONITE             1233
+#define MACH_TYPE_GENE1270             1234
+#define MACH_TYPE_ZIR2412              1235
+#define MACH_TYPE_MX31LITE             1236
+#define MACH_TYPE_T700WX               1237
+#define MACH_TYPE_VF100                1238
+#define MACH_TYPE_NSB2                 1239
+#define MACH_TYPE_NXHMI_BB             1240
+#define MACH_TYPE_NXHMI_RE             1241
+#define MACH_TYPE_N4100PRO             1242
+#define MACH_TYPE_SAM9260              1243
+#define MACH_TYPE_OMAP_TREO600         1244
+#define MACH_TYPE_INDY2410             1245
+#define MACH_TYPE_NELT_A               1246
+#define MACH_TYPE_N311                 1248
+#define MACH_TYPE_AT91SAM9260VGK       1249
+#define MACH_TYPE_AT91LEPPE            1250
+#define MACH_TYPE_AT91LEPCCN           1251
+#define MACH_TYPE_APC7100              1252
+#define MACH_TYPE_STARGAZER            1253
+#define MACH_TYPE_SONATA               1254
+#define MACH_TYPE_SCHMOOGIE            1255
+#define MACH_TYPE_AZTOOL               1256
+#define MACH_TYPE_MIOA701              1257
+#define MACH_TYPE_SXNI9260             1258
+#define MACH_TYPE_MXC27520EVB          1259
+#define MACH_TYPE_ARMADILLO5X0         1260
+#define MACH_TYPE_MB9260               1261
+#define MACH_TYPE_MB9263               1262
+#define MACH_TYPE_IPAC9302             1263
+#define MACH_TYPE_CC9P9360JS           1264
+#define MACH_TYPE_GALLIUM              1265
+#define MACH_TYPE_MSC2410              1266
+#define MACH_TYPE_GHI270               1267
+#define MACH_TYPE_DAVINCI_LEONARDO     1268
+#define MACH_TYPE_OIAB                 1269
+#define MACH_TYPE_SMDK6400             1270
+#define MACH_TYPE_NOKIA_N800           1271
+#define MACH_TYPE_GREENPHONE           1272
+#define MACH_TYPE_COMPEXWP18           1273
+#define MACH_TYPE_XMATE                1274
+#define MACH_TYPE_ENERGIZER            1275
+#define MACH_TYPE_IME1                 1276
+#define MACH_TYPE_SWEDATMS             1277
+#define MACH_TYPE_NTNP435C             1278
+#define MACH_TYPE_SPECTRO2             1279
+#define MACH_TYPE_H6039                1280
+#define MACH_TYPE_EP80219              1281
+#define MACH_TYPE_SAMOA_II             1282
+#define MACH_TYPE_CWMXL                1283
+#define MACH_TYPE_AS9200               1284
+#define MACH_TYPE_SFX1149              1285
+#define MACH_TYPE_NAVI010              1286
+#define MACH_TYPE_MULTMDP              1287
+#define MACH_TYPE_SCB9520              1288
+#define MACH_TYPE_HTCATHENA            1289
+#define MACH_TYPE_XP179                1290
+#define MACH_TYPE_H4300                1291
+#define MACH_TYPE_GORAMO_MLR           1292
+#define MACH_TYPE_MXC30020EVB          1293
+#define MACH_TYPE_ADSBITSYG5           1294
+#define MACH_TYPE_ADSPORTALPLUS        1295
+#define MACH_TYPE_MMSP2PLUS            1296
+#define MACH_TYPE_EM_X270              1297
+#define MACH_TYPE_TPP302               1298
+#define MACH_TYPE_TPM104               1299
+#define MACH_TYPE_TPM102               1300
+#define MACH_TYPE_TPM109               1301
+#define MACH_TYPE_FBXO1                1302
+#define MACH_TYPE_HXD8                 1303
+#define MACH_TYPE_NEO1973_GTA02        1304
+#define MACH_TYPE_EMTEST               1305
+#define MACH_TYPE_AD6900               1306
+#define MACH_TYPE_EUROPA               1307
+#define MACH_TYPE_METROCONNECT         1308
+#define MACH_TYPE_EZ_S2410             1309
+#define MACH_TYPE_EZ_S2440             1310
+#define MACH_TYPE_EZ_EP9312            1311
+#define MACH_TYPE_EZ_EP9315            1312
+#define MACH_TYPE_EZ_X7                1313
+#define MACH_TYPE_GODOTDB              1314
+#define MACH_TYPE_MISTRAL              1315
+#define MACH_TYPE_MSM                  1316
+#define MACH_TYPE_CT5910               1317
+#define MACH_TYPE_CT5912               1318
+#define MACH_TYPE_HYNET_INE            1319
+#define MACH_TYPE_HYNET_APP            1320
+#define MACH_TYPE_MSM7200              1321
+#define MACH_TYPE_MSM7600              1322
+#define MACH_TYPE_CEB255               1323
+#define MACH_TYPE_CIEL                 1324
+#define MACH_TYPE_SLM5650              1325
+#define MACH_TYPE_AT91SAM9RLEK         1326
+#define MACH_TYPE_COMTECH_ROUTER       1327
+#define MACH_TYPE_SBC2410X             1328
+#define MACH_TYPE_AT4X0BD              1329
+#define MACH_TYPE_CBIFR                1330
+#define MACH_TYPE_ARCOM_QUANTUM        1331
+#define MACH_TYPE_MATRIX520            1332
+#define MACH_TYPE_MATRIX510            1333
+#define MACH_TYPE_MATRIX500            1334
+#define MACH_TYPE_M501                 1335
+#define MACH_TYPE_AAEON1270            1336
+#define MACH_TYPE_MATRIX500EV          1337
+#define MACH_TYPE_PAC500               1338
+#define MACH_TYPE_PNX8181              1339
+#define MACH_TYPE_COLIBRI320           1340
+#define MACH_TYPE_AZTOOLBB             1341
+#define MACH_TYPE_AZTOOLG2             1342
+#define MACH_TYPE_DVLHOST              1343
+#define MACH_TYPE_ZIR9200              1344
+#define MACH_TYPE_ZIR9260              1345
+#define MACH_TYPE_COCOPAH              1346
+#define MACH_TYPE_NDS                  1347
+#define MACH_TYPE_ROSENCRANTZ          1348
+#define MACH_TYPE_FTTX_ODSC            1349
+#define MACH_TYPE_CLASSE_R6904         1350
+#define MACH_TYPE_CAM60                1351
+#define MACH_TYPE_MXC30031ADS          1352
+#define MACH_TYPE_DATACALL             1353
+#define MACH_TYPE_AT91EB01             1354
+#define MACH_TYPE_RTY                  1355
+#define MACH_TYPE_DWL2100              1356
+#define MACH_TYPE_VINSI                1357
+#define MACH_TYPE_DB88F5281            1358
+#define MACH_TYPE_CSB726               1359
+#define MACH_TYPE_TIK27                1360
+#define MACH_TYPE_MX_UC7420            1361
+#define MACH_TYPE_RIRM3                1362
+#define MACH_TYPE_PELCO_ODYSSEY        1363
+#define MACH_TYPE_ADX_ABOX             1365
+#define MACH_TYPE_ADX_TPID             1366
+#define MACH_TYPE_MINICHECK            1367
+#define MACH_TYPE_IDAM                 1368
+#define MACH_TYPE_MARIO_MX             1369
+#define MACH_TYPE_VI1888               1370
+#define MACH_TYPE_ZR4230               1371
+#define MACH_TYPE_T1_IX_BLUE           1372
+#define MACH_TYPE_SYHQ2                1373
+#define MACH_TYPE_COMPUTIME_R3         1374
+#define MACH_TYPE_ORATIS               1375
+#define MACH_TYPE_MIKKO                1376
+#define MACH_TYPE_HOLON                1377
+#define MACH_TYPE_OLIP8                1378
+#define MACH_TYPE_GHI270HG             1379
+#define MACH_TYPE_DAVINCI_DM6467_EVM   1380
+#define MACH_TYPE_DAVINCI_DM355_EVM    1381
+#define MACH_TYPE_BLACKRIVER           1383
+#define MACH_TYPE_SANDGATEWP           1384
+#define MACH_TYPE_CDOTBWSG             1385
+#define MACH_TYPE_QUARK963             1386
+#define MACH_TYPE_CSB735               1387
+#define MACH_TYPE_LITTLETON            1388
+#define MACH_TYPE_MIO_P550             1389
+#define MACH_TYPE_MOTION2440           1390
+#define MACH_TYPE_IMM500               1391
+#define MACH_TYPE_HOMEMATIC            1392
+#define MACH_TYPE_ERMINE               1393
+#define MACH_TYPE_KB9202B              1394
+#define MACH_TYPE_HS1XX                1395
+#define MACH_TYPE_STUDENTMATE2440      1396
+#define MACH_TYPE_ARVOO_L1_Z1          1397
+#define MACH_TYPE_DEP2410K             1398
+#define MACH_TYPE_XXSVIDEO             1399
+#define MACH_TYPE_IM4004               1400
+#define MACH_TYPE_OCHAYA1050           1401
+#define MACH_TYPE_LEP9261              1402
+#define MACH_TYPE_SVENMEB              1403
+#define MACH_TYPE_FORTUNET2NE          1404
+#define MACH_TYPE_NXHX                 1406
+#define MACH_TYPE_REALVIEW_PB11MP      1407
+#define MACH_TYPE_IDS500               1408
+#define MACH_TYPE_ORS_N725             1409
+#define MACH_TYPE_HSDARM               1410
+#define MACH_TYPE_SHA_PON003           1411
+#define MACH_TYPE_SHA_PON004           1412
+#define MACH_TYPE_SHA_PON007           1413
+#define MACH_TYPE_SHA_PON011           1414
+#define MACH_TYPE_H6042                1415
+#define MACH_TYPE_H6043                1416
+#define MACH_TYPE_LOOXC550             1417
+#define MACH_TYPE_CNTY_TITAN           1418
+#define MACH_TYPE_APP3XX               1419
+#define MACH_TYPE_SIDEOATSGRAMA        1420
+#define MACH_TYPE_TREO700P             1421
+#define MACH_TYPE_TREO700W             1422
+#define MACH_TYPE_TREO750              1423
+#define MACH_TYPE_TREO755P             1424
+#define MACH_TYPE_EZREGANUT9200        1425
+#define MACH_TYPE_SARGE                1426
+#define MACH_TYPE_A696                 1427
+#define MACH_TYPE_TURTLE               1428
+#define MACH_TYPE_MX27_3DS             1430
+#define MACH_TYPE_BISHOP               1431
+#define MACH_TYPE_PXX                  1432
+#define MACH_TYPE_REDWOOD              1433
+#define MACH_TYPE_OMAP_2430DLP         1436
+#define MACH_TYPE_OMAP_2430OSK         1437
+#define MACH_TYPE_SARDINE              1438
+#define MACH_TYPE_HALIBUT              1439
+#define MACH_TYPE_TROUT                1440
+#define MACH_TYPE_GOLDFISH             1441
+#define MACH_TYPE_GESBC2440            1442
+#define MACH_TYPE_NOMAD                1443
+#define MACH_TYPE_ROSALIND             1444
+#define MACH_TYPE_CC9P9215             1445
+#define MACH_TYPE_CC9P9210             1446
+#define MACH_TYPE_CC9P9215JS           1447
+#define MACH_TYPE_CC9P9210JS           1448
+#define MACH_TYPE_NASFFE               1449
+#define MACH_TYPE_TN2X0BD              1450
+#define MACH_TYPE_GWMPXA               1451
+#define MACH_TYPE_EXYPLUS              1452
+#define MACH_TYPE_JADOO21              1453
+#define MACH_TYPE_LOOXN560             1454
+#define MACH_TYPE_BONSAI               1455
+#define MACH_TYPE_ADSMILGATO           1456
+#define MACH_TYPE_GBA                  1457
+#define MACH_TYPE_H6044                1458
+#define MACH_TYPE_APP                  1459
+#define MACH_TYPE_TCT_HAMMER           1460
+#define MACH_TYPE_HERALD               1461
+#define MACH_TYPE_ARTEMIS              1462
+#define MACH_TYPE_HTCTITAN             1463
+#define MACH_TYPE_QRANIUM              1464
+#define MACH_TYPE_ADX_WSC2             1465
+#define MACH_TYPE_ADX_MEDCOM           1466
+#define MACH_TYPE_BBOARD               1467
+#define MACH_TYPE_CAMBRIA              1468
+#define MACH_TYPE_MT7XXX               1469
+#define MACH_TYPE_MATRIX512            1470
+#define MACH_TYPE_MATRIX522            1471
+#define MACH_TYPE_IPAC5010             1472
+#define MACH_TYPE_SAKURA               1473
+#define MACH_TYPE_GROCX                1474
+#define MACH_TYPE_PM9263               1475
+#define MACH_TYPE_SIM_ONE              1476
+#define MACH_TYPE_ACQ132               1477
+#define MACH_TYPE_DATR                 1478
+#define MACH_TYPE_ACTUX1               1479
+#define MACH_TYPE_ACTUX2               1480
+#define MACH_TYPE_ACTUX3               1481
+#define MACH_TYPE_FLEXIT               1482
+#define MACH_TYPE_BH2X0BD              1483
+#define MACH_TYPE_ATB2002              1484
+#define MACH_TYPE_XENON                1485
+#define MACH_TYPE_FM607                1486
+#define MACH_TYPE_MATRIX514            1487
+#define MACH_TYPE_MATRIX524            1488
+#define MACH_TYPE_INPOD                1489
+#define MACH_TYPE_JIVE                 1490
+#define MACH_TYPE_TLL_MX21             1491
+#define MACH_TYPE_SBC2800              1492
+#define MACH_TYPE_CC7UCAMRY            1493
+#define MACH_TYPE_UBISYS_P9_SC15       1494
+#define MACH_TYPE_UBISYS_P9_SSC2D10    1495
+#define MACH_TYPE_UBISYS_P9_RCU3       1496
+#define MACH_TYPE_AML_M8000            1497
+#define MACH_TYPE_SNAPPER_270          1498
+#define MACH_TYPE_OMAP_BBX             1499
+#define MACH_TYPE_UCN2410              1500
+#define MACH_TYPE_SAM9_L9260           1501
+#define MACH_TYPE_ETI_C2               1502
+#define MACH_TYPE_AVALANCHE            1503
+#define MACH_TYPE_REALVIEW_PB1176      1504
+#define MACH_TYPE_DP1500               1505
+#define MACH_TYPE_APPLE_IPHONE         1506
+#define MACH_TYPE_YL9200               1507
+#define MACH_TYPE_RD88F5182            1508
+#define MACH_TYPE_KUROBOX_PRO          1509
+#define MACH_TYPE_SE_POET              1510
+#define MACH_TYPE_MX31_3DS             1511
+#define MACH_TYPE_R270                 1512
+#define MACH_TYPE_ARMOUR21             1513
+#define MACH_TYPE_DT2                  1514
+#define MACH_TYPE_VT4                  1515
+#define MACH_TYPE_TYCO320              1516
+#define MACH_TYPE_ADMA                 1517
+#define MACH_TYPE_WP188                1518
+#define MACH_TYPE_CORSICA              1519
+#define MACH_TYPE_BIGEYE               1520
+#define MACH_TYPE_TLL5000              1522
+#define MACH_TYPE_BEBOT                1523
+#define MACH_TYPE_QONG                 1524
+#define MACH_TYPE_TCOMPACT             1525
+#define MACH_TYPE_PUMA5                1526
+#define MACH_TYPE_ELARA                1527
+#define MACH_TYPE_ELLINGTON            1528
+#define MACH_TYPE_XDA_ATOM             1529
+#define MACH_TYPE_ENERGIZER2           1530
+#define MACH_TYPE_ODIN                 1531
+#define MACH_TYPE_ACTUX4               1532
+#define MACH_TYPE_ESL_OMAP             1533
+#define MACH_TYPE_OMAP2EVM             1534
+#define MACH_TYPE_OMAP3EVM             1535
+#define MACH_TYPE_ADX_PCU57            1536
+#define MACH_TYPE_MONACO               1537
+#define MACH_TYPE_LEVANTE              1538
+#define MACH_TYPE_TMXIPX425            1539
+#define MACH_TYPE_LEEP                 1540
+#define MACH_TYPE_RAAD                 1541
+#define MACH_TYPE_DNS323               1542
+#define MACH_TYPE_AP1000               1543
+#define MACH_TYPE_A9SAM6432            1544
+#define MACH_TYPE_SHINY                1545
+#define MACH_TYPE_OMAP3_BEAGLE         1546
+#define MACH_TYPE_CSR_BDB2             1547
+#define MACH_TYPE_NOKIA_N810           1548
+#define MACH_TYPE_C270                 1549
+#define MACH_TYPE_SENTRY               1550
+#define MACH_TYPE_PCM038               1551
+#define MACH_TYPE_ANC300               1552
+#define MACH_TYPE_HTCKAISER            1553
+#define MACH_TYPE_SBAT100              1554
+#define MACH_TYPE_MODUNORM             1555
+#define MACH_TYPE_PELOS_TWARM          1556
+#define MACH_TYPE_FLANK                1557
+#define MACH_TYPE_SIRLOIN              1558
+#define MACH_TYPE_BRISKET              1559
+#define MACH_TYPE_CHUCK                1560
+#define MACH_TYPE_OTTER                1561
+#define MACH_TYPE_DAVINCI_LDK          1562
+#define MACH_TYPE_PHREEDOM             1563
+#define MACH_TYPE_SG310                1564
+#define MACH_TYPE_TS209                1565
+#define MACH_TYPE_AT91CAP9ADK          1566
+#define MACH_TYPE_TION9315             1567
+#define MACH_TYPE_MAST                 1568
+#define MACH_TYPE_PFW                  1569
+#define MACH_TYPE_YL_P2440             1570
+#define MACH_TYPE_ZSBC32               1571
+#define MACH_TYPE_OMAP_PACE2           1572
+#define MACH_TYPE_IMX_PACE2            1573
+#define MACH_TYPE_MX31MOBOARD          1574
+#define MACH_TYPE_MX37_3DS             1575
+#define MACH_TYPE_RCC                  1576
+#define MACH_TYPE_ARM9                 1577
+#define MACH_TYPE_VISION_EP9307        1578
+#define MACH_TYPE_SCLY1000             1579
+#define MACH_TYPE_FONTEL_EP            1580
+#define MACH_TYPE_VOICEBLUE3G          1581
+#define MACH_TYPE_TT9200               1582
+#define MACH_TYPE_DIGI2410             1583
+#define MACH_TYPE_TERASTATION_PRO2     1584
+#define MACH_TYPE_LINKSTATION_PRO      1585
+#define MACH_TYPE_MOTOROLA_A780        1587
+#define MACH_TYPE_MOTOROLA_E6          1588
+#define MACH_TYPE_MOTOROLA_E2          1589
+#define MACH_TYPE_MOTOROLA_E680        1590
+#define MACH_TYPE_UR2410               1591
+#define MACH_TYPE_TAS9261              1592
+#define MACH_TYPE_HERMES_HD            1593
+#define MACH_TYPE_PERSEO_HD            1594
+#define MACH_TYPE_STARGAZER2           1595
+#define MACH_TYPE_E350                 1596
+#define MACH_TYPE_WPCM450              1597
+#define MACH_TYPE_CARTESIO             1598
+#define MACH_TYPE_TOYBOX               1599
+#define MACH_TYPE_TX27                 1600
+#define MACH_TYPE_TS409                1601
+#define MACH_TYPE_P300                 1602
+#define MACH_TYPE_XDACOMET             1603
+#define MACH_TYPE_DEXFLEX2             1604
+#define MACH_TYPE_OW                   1605
+#define MACH_TYPE_ARMEBS3              1606
+#define MACH_TYPE_U3                   1607
+#define MACH_TYPE_SMDK2450             1608
+#define MACH_TYPE_RSI_EWS              1609
+#define MACH_TYPE_TNB                  1610
+#define MACH_TYPE_TOEPATH              1611
+#define MACH_TYPE_KB9263               1612
+#define MACH_TYPE_MT7108               1613
+#define MACH_TYPE_SMTR2440             1614
+#define MACH_TYPE_MANAO                1615
+#define MACH_TYPE_CM_X300              1616
+#define MACH_TYPE_GULFSTREAM_KP        1617
+#define MACH_TYPE_LANREADYFN522        1618
+#define MACH_TYPE_ARMA37               1619
+#define MACH_TYPE_MENDEL               1620
+#define MACH_TYPE_PELCO_ILIAD          1621
+#define MACH_TYPE_UNIT2P               1622
+#define MACH_TYPE_INC20OTTER           1623
+#define MACH_TYPE_AT91SAM9G20EK        1624
+#define MACH_TYPE_STORCENTER           1625
+#define MACH_TYPE_SMDK6410             1626
+#define MACH_TYPE_U300                 1627
+#define MACH_TYPE_U500                 1628
+#define MACH_TYPE_DS9260               1629
+#define MACH_TYPE_RIVERROCK            1630
+#define MACH_TYPE_SCIBATH              1631
+#define MACH_TYPE_AT91SAM7SE512EK      1632
+#define MACH_TYPE_WRT350N_V2           1633
+#define MACH_TYPE_MULTIMEDIA           1634
+#define MACH_TYPE_MARVIN               1635
+#define MACH_TYPE_X500                 1636
+#define MACH_TYPE_AWLUG4LCU            1637
+#define MACH_TYPE_PALERMOC             1638
+#define MACH_TYPE_OMAP_LDP             1639
+#define MACH_TYPE_IP500                1640
+#define MACH_TYPE_ASE2                 1642
+#define MACH_TYPE_MX35EVB              1643
+#define MACH_TYPE_AML_M8050            1644
+#define MACH_TYPE_MX35_3DS             1645
+#define MACH_TYPE_MARS                 1646
+#define MACH_TYPE_NEUROS_OSD2          1647
+#define MACH_TYPE_BADGER               1648
+#define MACH_TYPE_TRIZEPS4WL           1649
+#define MACH_TYPE_TRIZEPS5             1650
+#define MACH_TYPE_MARLIN               1651
+#define MACH_TYPE_TS78XX               1652
+#define MACH_TYPE_HPIPAQ214            1653
+#define MACH_TYPE_AT572D940DCM         1654
+#define MACH_TYPE_NE1BOARD             1655
+#define MACH_TYPE_ZANTE                1656
+#define MACH_TYPE_SFFSDR               1657
+#define MACH_TYPE_TW2662               1658
+#define MACH_TYPE_VF10XX               1659
+#define MACH_TYPE_ZORAN43XX            1660
+#define MACH_TYPE_SONIX926             1661
+#define MACH_TYPE_CELESTIALSEMI        1662
+#define MACH_TYPE_CC9M2443JS           1663
+#define MACH_TYPE_TW5334               1664
+#define MACH_TYPE_HTCARTEMIS           1665
+#define MACH_TYPE_NAL_HLITE            1666
+#define MACH_TYPE_HTCVOGUE             1667
+#define MACH_TYPE_SMARTWEB             1668
+#define MACH_TYPE_MV86XX               1669
+#define MACH_TYPE_MV87XX               1670
+#define MACH_TYPE_SONGYOUNGHO          1671
+#define MACH_TYPE_YOUNGHOTEMA          1672
+#define MACH_TYPE_PCM037               1673
+#define MACH_TYPE_MMVP                 1674
+#define MACH_TYPE_MMAP                 1675
+#define MACH_TYPE_PTID2410             1676
+#define MACH_TYPE_JAMES_926            1677
+#define MACH_TYPE_FM6000               1678
+#define MACH_TYPE_DB88F6281_BP         1680
+#define MACH_TYPE_RD88F6192_NAS        1681
+#define MACH_TYPE_RD88F6281            1682
+#define MACH_TYPE_DB78X00_BP           1683
+#define MACH_TYPE_SMDK2416             1685
+#define MACH_TYPE_OCE_SPIDER_SI        1686
+#define MACH_TYPE_OCE_SPIDER_SK        1687
+#define MACH_TYPE_ROVERN6              1688
+#define MACH_TYPE_PELCO_EVOLUTION      1689
+#define MACH_TYPE_WBD111               1690
+#define MACH_TYPE_ELARACPE             1691
+#define MACH_TYPE_MABV3                1692
+#define MACH_TYPE_MV2120               1693
+#define MACH_TYPE_CSB737               1695
+#define MACH_TYPE_MX51_3DS             1696
+#define MACH_TYPE_G900                 1697
+#define MACH_TYPE_APF27                1698
+#define MACH_TYPE_GGUS2000             1699
+#define MACH_TYPE_OMAP_2430_MIMIC      1700
+#define MACH_TYPE_IMX27LITE            1701
+#define MACH_TYPE_ALMEX                1702
+#define MACH_TYPE_CONTROL              1703
+#define MACH_TYPE_MBA2410              1704
+#define MACH_TYPE_VOLCANO              1705
+#define MACH_TYPE_ZENITH               1706
+#define MACH_TYPE_MUCHIP               1707
+#define MACH_TYPE_MAGELLAN             1708
+#define MACH_TYPE_USB_A9260            1709
+#define MACH_TYPE_USB_A9263            1710
+#define MACH_TYPE_QIL_A9260            1711
+#define MACH_TYPE_CME9210              1712
+#define MACH_TYPE_HCZH4                1713
+#define MACH_TYPE_SPEARBASIC           1714
+#define MACH_TYPE_DEP2440              1715
+#define MACH_TYPE_HDL_GXR              1716
+#define MACH_TYPE_HDL_GT               1717
+#define MACH_TYPE_HDL_4G               1718
+#define MACH_TYPE_S3C6000              1719
+#define MACH_TYPE_MMSP2_MDK            1720
+#define MACH_TYPE_MPX220               1721
+#define MACH_TYPE_KZM_ARM11_01         1722
+#define MACH_TYPE_HTC_POLARIS          1723
+#define MACH_TYPE_HTC_KAISER           1724
+#define MACH_TYPE_LG_KS20              1725
+#define MACH_TYPE_HHGPS                1726
+#define MACH_TYPE_NOKIA_N810_WIMAX     1727
+#define MACH_TYPE_INSIGHT              1728
+#define MACH_TYPE_SAPPHIRE             1729
+#define MACH_TYPE_CSB637XO             1730
+#define MACH_TYPE_EVISIONG             1731
+#define MACH_TYPE_STMP37XX             1732
+#define MACH_TYPE_STMP378X             1733
+#define MACH_TYPE_TNT                  1734
+#define MACH_TYPE_TBXT                 1735
+#define MACH_TYPE_PLAYMATE             1736
+#define MACH_TYPE_PNS10                1737
+#define MACH_TYPE_EZNAVI               1738
+#define MACH_TYPE_PS4000               1739
+#define MACH_TYPE_EZX_A780             1740
+#define MACH_TYPE_EZX_E680             1741
+#define MACH_TYPE_EZX_A1200            1742
+#define MACH_TYPE_EZX_E6               1743
+#define MACH_TYPE_EZX_E2               1744
+#define MACH_TYPE_EZX_A910             1745
+#define MACH_TYPE_CWMX31               1746
+#define MACH_TYPE_SL2312               1747
+#define MACH_TYPE_BLENNY               1748
+#define MACH_TYPE_DS107                1749
+#define MACH_TYPE_DSX07                1750
+#define MACH_TYPE_PICOCOM1             1751
+#define MACH_TYPE_LYNX_WOLVERINE       1752
+#define MACH_TYPE_UBISYS_P9_SC19       1753
+#define MACH_TYPE_KRATOS_LOW           1754
+#define MACH_TYPE_M700                 1755
+#define MACH_TYPE_EDMINI_V2            1756
+#define MACH_TYPE_ZIPIT2               1757
+#define MACH_TYPE_HSLFEMTOCELL         1758
+#define MACH_TYPE_DAINTREE_AT91        1759
+#define MACH_TYPE_SG560USB             1760
+#define MACH_TYPE_OMAP3_PANDORA        1761
+#define MACH_TYPE_USR8200              1762
+#define MACH_TYPE_S1S65K               1763
+#define MACH_TYPE_S2S65A               1764
+#define MACH_TYPE_ICORE                1765
+#define MACH_TYPE_MSS2                 1766
+#define MACH_TYPE_BELMONT              1767
+#define MACH_TYPE_ASUSP525             1768
+#define MACH_TYPE_LB88RC8480           1769
+#define MACH_TYPE_HIPXA                1770
+#define MACH_TYPE_MX25_3DS             1771
+#define MACH_TYPE_M800                 1772
+#define MACH_TYPE_OMAP3530_LV_SOM      1773
+#define MACH_TYPE_PRIMA_EVB            1774
+#define MACH_TYPE_MX31BT1              1775
+#define MACH_TYPE_ATLAS4_EVB           1776
+#define MACH_TYPE_MX31CICADA           1777
+#define MACH_TYPE_MI424WR              1778
+#define MACH_TYPE_AXS_ULTRAX           1779
+#define MACH_TYPE_AT572D940DEB         1780
+#define MACH_TYPE_DAVINCI_DA830_EVM    1781
+#define MACH_TYPE_EP9302               1782
+#define MACH_TYPE_AT572D940HFEB        1783
+#define MACH_TYPE_CYBOOK3              1784
+#define MACH_TYPE_WDG002               1785
+#define MACH_TYPE_SG560ADSL            1786
+#define MACH_TYPE_NEXTIO_N2800_ICA     1787
+#define MACH_TYPE_DOVE_DB              1788
+#define MACH_TYPE_VANDIHUD             1790
+#define MACH_TYPE_MAGX_E8              1791
+#define MACH_TYPE_MAGX_Z6              1792
+#define MACH_TYPE_MAGX_V8              1793
+#define MACH_TYPE_MAGX_U9              1794
+#define MACH_TYPE_TOUGHCF08            1795
+#define MACH_TYPE_ZW4400               1796
+#define MACH_TYPE_MARAT91              1797
+#define MACH_TYPE_OVERO                1798
+#define MACH_TYPE_AT2440EVB            1799
+#define MACH_TYPE_NEOCORE926           1800
+#define MACH_TYPE_WNR854T              1801
+#define MACH_TYPE_IMX27                1802
+#define MACH_TYPE_MOOSE_DB             1803
+#define MACH_TYPE_FAB4                 1804
+#define MACH_TYPE_HTCDIAMOND           1805
+#define MACH_TYPE_FIONA                1806
+#define MACH_TYPE_MXC30030_X           1807
+#define MACH_TYPE_BMP1000              1808
+#define MACH_TYPE_LOGI9200             1809
+#define MACH_TYPE_TQMA31               1810
+#define MACH_TYPE_CCW9P9215JS          1811
+#define MACH_TYPE_RD88F5181L_GE        1812
+#define MACH_TYPE_SIFMAIN              1813
+#define MACH_TYPE_SAM9_L9261           1814
+#define MACH_TYPE_CC9M2443             1815
+#define MACH_TYPE_XARIA300             1816
+#define MACH_TYPE_IT9200               1817
+#define MACH_TYPE_RD88F5181L_FXO       1818
+#define MACH_TYPE_KRISS_SENSOR         1819
+#define MACH_TYPE_PILZ_PMI5            1820
+#define MACH_TYPE_JADE                 1821
+#define MACH_TYPE_KS8695_SOFTPLC       1822
+#define MACH_TYPE_GPRISC3              1823
+#define MACH_TYPE_STAMP9G20            1824
+#define MACH_TYPE_SMDK6430             1825
+#define MACH_TYPE_SMDKC100             1826
+#define MACH_TYPE_TAVOREVB             1827
+#define MACH_TYPE_SAAR                 1828
+#define MACH_TYPE_DEISTER_EYECAM       1829
+#define MACH_TYPE_AT91SAM9M10G45EK     1830
+#define MACH_TYPE_LINKSTATION_PRODUO   1831
+#define MACH_TYPE_HIT_B0               1832
+#define MACH_TYPE_ADX_RMU              1833
+#define MACH_TYPE_XG_CPE_MAIN          1834
+#define MACH_TYPE_EDB9407A             1835
+#define MACH_TYPE_DTB9608              1836
+#define MACH_TYPE_EM104V1              1837
+#define MACH_TYPE_DEMO                 1838
+#define MACH_TYPE_LOGI9260             1839
+#define MACH_TYPE_MX31_EXM32           1840
+#define MACH_TYPE_USB_A9G20            1841
+#define MACH_TYPE_PICPROJE2008         1842
+#define MACH_TYPE_CS_E9315             1843
+#define MACH_TYPE_QIL_A9G20            1844
+#define MACH_TYPE_SHA_PON020           1845
+#define MACH_TYPE_NAD                  1846
+#define MACH_TYPE_SBC35_A9260          1847
+#define MACH_TYPE_SBC35_A9G20          1848
+#define MACH_TYPE_DAVINCI_BEGINNING    1849
+#define MACH_TYPE_UWC                  1850
+#define MACH_TYPE_MXLADS               1851
+#define MACH_TYPE_HTCNIKE              1852
+#define MACH_TYPE_DEISTER_PXA270       1853
+#define MACH_TYPE_CME9210JS            1854
+#define MACH_TYPE_CC9P9360             1855
+#define MACH_TYPE_MOCHA                1856
+#define MACH_TYPE_WAPD170AG            1857
+#define MACH_TYPE_LINKSTATION_MINI     1858
+#define MACH_TYPE_AFEB9260             1859
+#define MACH_TYPE_W90X900              1860
+#define MACH_TYPE_W90X700              1861
+#define MACH_TYPE_KT300IP              1862
+#define MACH_TYPE_KT300IP_G20          1863
+#define MACH_TYPE_SRCM                 1864
+#define MACH_TYPE_WLNX_9260            1865
+#define MACH_TYPE_OPENMOKO_GTA03       1866
+#define MACH_TYPE_OSPREY2              1867
+#define MACH_TYPE_KBIO9260             1868
+#define MACH_TYPE_GINZA                1869
+#define MACH_TYPE_A636N                1870
+#define MACH_TYPE_IMX27IPCAM           1871
+#define MACH_TYPE_NEMOC                1872
+#define MACH_TYPE_GENEVA               1873
+#define MACH_TYPE_HTCPHAROS            1874
+#define MACH_TYPE_NEONC                1875
+#define MACH_TYPE_NAS7100              1876
+#define MACH_TYPE_TEUPHONE             1877
+#define MACH_TYPE_ANNAX_ETH2           1878
+#define MACH_TYPE_CSB733               1879
+#define MACH_TYPE_BK3                  1880
+#define MACH_TYPE_OMAP_EM32            1881
+#define MACH_TYPE_ET9261CP             1882
+#define MACH_TYPE_JASPERC              1883
+#define MACH_TYPE_ISSI_ARM9            1884
+#define MACH_TYPE_UED                  1885
+#define MACH_TYPE_ESIBLADE             1886
+#define MACH_TYPE_EYE02                1887
+#define MACH_TYPE_IMX27KBD             1888
+#define MACH_TYPE_KIXVP435             1890
+#define MACH_TYPE_KIXNP435             1891
+#define MACH_TYPE_AFRICA               1892
+#define MACH_TYPE_NH233                1893
+#define MACH_TYPE_RD88F6183AP_GE       1894
+#define MACH_TYPE_BCM4760              1895
+#define MACH_TYPE_EDDY_V2              1896
+#define MACH_TYPE_REALVIEW_PBA8        1897
+#define MACH_TYPE_HID_A7               1898
+#define MACH_TYPE_HERO                 1899
+#define MACH_TYPE_OMAP_POSEIDON        1900
+#define MACH_TYPE_REALVIEW_PBX         1901
+#define MACH_TYPE_MICRO9S              1902
+#define MACH_TYPE_MAKO                 1903
+#define MACH_TYPE_XDAFLAME             1904
+#define MACH_TYPE_PHIDGET_SBC2         1905
+#define MACH_TYPE_LIMESTONE            1906
+#define MACH_TYPE_IPROBE_C32           1907
+#define MACH_TYPE_RUT100               1908
+#define MACH_TYPE_ASUSP535             1909
+#define MACH_TYPE_HTCRAPHAEL           1910
+#define MACH_TYPE_SYGDG1               1911
+#define MACH_TYPE_SYGDG2               1912
+#define MACH_TYPE_SEOUL                1913
+#define MACH_TYPE_SALERNO              1914
+#define MACH_TYPE_UCN_S3C64XX          1915
+#define MACH_TYPE_MSM7201A             1916
+#define MACH_TYPE_LPR1                 1917
+#define MACH_TYPE_ARMADILLO500FX       1918
+#define MACH_TYPE_G3EVM                1919
+#define MACH_TYPE_Z3_DM355             1920
+#define MACH_TYPE_W90P910EVB           1921
+#define MACH_TYPE_W90P920EVB           1922
+#define MACH_TYPE_W90P950EVB           1923
+#define MACH_TYPE_W90N960EVB           1924
+#define MACH_TYPE_CAMHD                1925
+#define MACH_TYPE_MVC100               1926
+#define MACH_TYPE_ELECTRUM_200         1927
+#define MACH_TYPE_HTCJADE              1928
+#define MACH_TYPE_MEMPHIS              1929
+#define MACH_TYPE_IMX27SBC             1930
+#define MACH_TYPE_LEXTAR               1931
+#define MACH_TYPE_MV88F6281GTW_GE      1932
+#define MACH_TYPE_NCP                  1933
+#define MACH_TYPE_Z32AN                1934
+#define MACH_TYPE_TMQ_CAPD             1935
+#define MACH_TYPE_OMAP3_WL             1936
+#define MACH_TYPE_CHUMBY               1937
+#define MACH_TYPE_ATSARM9              1938
+#define MACH_TYPE_DAVINCI_DM365_EVM    1939
+#define MACH_TYPE_BAHAMAS              1940
+#define MACH_TYPE_DAS                  1941
+#define MACH_TYPE_MINIDAS              1942
+#define MACH_TYPE_VK1000               1943
+#define MACH_TYPE_CENTRO               1944
+#define MACH_TYPE_CTERA_2BAY           1945
+#define MACH_TYPE_EDGECONNECT          1946
+#define MACH_TYPE_ND27000              1947
+#define MACH_TYPE_GEMALTO_COBRA        1948
+#define MACH_TYPE_INGELABS_COMET       1949
+#define MACH_TYPE_POLLUX_WIZ           1950
+#define MACH_TYPE_BLACKSTONE           1951
+#define MACH_TYPE_TOPAZ                1952
+#define MACH_TYPE_AIXLE                1953
+#define MACH_TYPE_MW998                1954
+#define MACH_TYPE_NOKIA_RX51           1955
+#define MACH_TYPE_VSC5605EV            1956
+#define MACH_TYPE_NT98700DK            1957
+#define MACH_TYPE_ICONTACT             1958
+#define MACH_TYPE_SWARCO_FRCPU         1959
+#define MACH_TYPE_SWARCO_SCPU          1960
+#define MACH_TYPE_BBOX_P16             1961
+#define MACH_TYPE_BSTD                 1962
+#define MACH_TYPE_SBC2440II            1963
+#define MACH_TYPE_PCM034               1964
+#define MACH_TYPE_NESO                 1965
+#define MACH_TYPE_WLNX_9G20            1966
+#define MACH_TYPE_OMAP_ZOOM2           1967
+#define MACH_TYPE_TOTEMNOVA            1968
+#define MACH_TYPE_C5000                1969
+#define MACH_TYPE_UNIPO_AT91SAM9263    1970
+#define MACH_TYPE_ETHERNUT5            1971
+#define MACH_TYPE_ARM11                1972
+#define MACH_TYPE_CPUAT9260            1973
+#define MACH_TYPE_CPUPXA255            1974
+#define MACH_TYPE_EUKREA_CPUIMX27      1975
+#define MACH_TYPE_CHEFLUX              1976
+#define MACH_TYPE_EB_CPUX9K2           1977
+#define MACH_TYPE_OPCOTEC              1978
+#define MACH_TYPE_YT                   1979
+#define MACH_TYPE_MOTOQ                1980
+#define MACH_TYPE_BSB1                 1981
+#define MACH_TYPE_ACS5K                1982
+#define MACH_TYPE_MILAN                1983
+#define MACH_TYPE_QUARTZV2             1984
+#define MACH_TYPE_RSVP                 1985
+#define MACH_TYPE_RMP200               1986
+#define MACH_TYPE_SNAPPER_9260         1987
+#define MACH_TYPE_DSM320               1988
+#define MACH_TYPE_ADSGCM               1989
+#define MACH_TYPE_ASE2_400             1990
+#define MACH_TYPE_PIZZA                1991
+#define MACH_TYPE_SPOT_NGPL            1992
+#define MACH_TYPE_ARMATA               1993
+#define MACH_TYPE_EXEDA                1994
+#define MACH_TYPE_MX31SF005            1995
+#define MACH_TYPE_F5D8231_4_V2         1996
+#define MACH_TYPE_Q2440                1997
+#define MACH_TYPE_QQ2440               1998
+#define MACH_TYPE_MINI2440             1999
+#define MACH_TYPE_COLIBRI300           2000
+#define MACH_TYPE_JADES                2001
+#define MACH_TYPE_SPARK                2002
+#define MACH_TYPE_BENZINA              2003
+#define MACH_TYPE_BLAZE                2004
+#define MACH_TYPE_LINKSTATION_LS_HGL   2005
+#define MACH_TYPE_HTCKOVSKY            2006
+#define MACH_TYPE_SONY_PRS505          2007
+#define MACH_TYPE_HANLIN_V3            2008
+#define MACH_TYPE_SAPPHIRA             2009
+#define MACH_TYPE_DACK_SDA_01          2010
+#define MACH_TYPE_ARMBOX               2011
+#define MACH_TYPE_HARRIS_RVP           2012
+#define MACH_TYPE_RIBALDO              2013
+#define MACH_TYPE_AGORA                2014
+#define MACH_TYPE_OMAP3_MINI           2015
+#define MACH_TYPE_A9SAM6432_B          2016
+#define MACH_TYPE_USG2410              2017
+#define MACH_TYPE_PC72052_I10_REVB     2018
+#define MACH_TYPE_MX35_EXM32           2019
+#define MACH_TYPE_TOPAS910             2020
+#define MACH_TYPE_HYENA                2021
+#define MACH_TYPE_POSPAX               2022
+#define MACH_TYPE_HDL_GX               2023
+#define MACH_TYPE_CTERA_4BAY           2024
+#define MACH_TYPE_CTERA_PLUG_C         2025
+#define MACH_TYPE_CRWEA_PLUG_I         2026
+#define MACH_TYPE_EGAUGE2              2027
+#define MACH_TYPE_DIDJ                 2028
+#define MACH_TYPE_MEISTER              2029
+#define MACH_TYPE_HTCBLACKSTONE        2030
+#define MACH_TYPE_CPUAT9G20            2031
+#define MACH_TYPE_SMDK6440             2032
+#define MACH_TYPE_OMAP_35XX_MVP        2033
+#define MACH_TYPE_CTERA_PLUG_I         2034
+#define MACH_TYPE_PVG610               2035
+#define MACH_TYPE_HPRW6815             2036
+#define MACH_TYPE_OMAP3_OSWALD         2037
+#define MACH_TYPE_NAS4220B             2038
+#define MACH_TYPE_HTCRAPHAEL_CDMA      2039
+#define MACH_TYPE_HTCDIAMOND_CDMA      2040
+#define MACH_TYPE_SCALER               2041
+#define MACH_TYPE_ZYLONITE2            2042
+#define MACH_TYPE_ASPENITE             2043
+#define MACH_TYPE_TETON                2044
+#define MACH_TYPE_TTC_DKB              2045
+#define MACH_TYPE_BISHOP2              2046
+#define MACH_TYPE_IPPV5                2047
+#define MACH_TYPE_FARM926              2048
+#define MACH_TYPE_MMCCPU               2049
+#define MACH_TYPE_SGMSFL               2050
+#define MACH_TYPE_TT8000               2051
+#define MACH_TYPE_ZRN4300LP            2052
+#define MACH_TYPE_MPTC                 2053
+#define MACH_TYPE_H6051                2054
+#define MACH_TYPE_PVG610_101           2055
+#define MACH_TYPE_STAMP9261_PC_EVB     2056
+#define MACH_TYPE_PELCO_ODYSSEUS       2057
+#define MACH_TYPE_TNY_A9260            2058
+#define MACH_TYPE_TNY_A9G20            2059
+#define MACH_TYPE_AESOP_MP2530F        2060
+#define MACH_TYPE_DX900                2061
+#define MACH_TYPE_CPODC2               2062
+#define MACH_TYPE_TILT_8925            2063
+#define MACH_TYPE_DAVINCI_DM357_EVM    2064
+#define MACH_TYPE_SWORDFISH            2065
+#define MACH_TYPE_CORVUS               2066
+#define MACH_TYPE_TAURUS               2067
+#define MACH_TYPE_AXM                  2068
+#define MACH_TYPE_AXC                  2069
+#define MACH_TYPE_BABY                 2070
+#define MACH_TYPE_MP200                2071
+#define MACH_TYPE_PCM043               2072
+#define MACH_TYPE_HANLIN_V3C           2073
+#define MACH_TYPE_KBK9G20              2074
+#define MACH_TYPE_ADSTURBOG5           2075
+#define MACH_TYPE_AVENGER_LITE1        2076
+#define MACH_TYPE_SUC                  2077
+#define MACH_TYPE_AT91SAM7S256         2078
+#define MACH_TYPE_MENDOZA              2079
+#define MACH_TYPE_KIRA                 2080
+#define MACH_TYPE_MX1HBM               2081
+#define MACH_TYPE_QUATRO43XX           2082
+#define MACH_TYPE_QUATRO4230           2083
+#define MACH_TYPE_NSB400               2084
+#define MACH_TYPE_DRP255               2085
+#define MACH_TYPE_THOTH                2086
+#define MACH_TYPE_FIRESTONE            2087
+#define MACH_TYPE_ASUSP750             2088
+#define MACH_TYPE_CTERA_DL             2089
+#define MACH_TYPE_SOCR                 2090
+#define MACH_TYPE_HTCOXYGEN            2091
+#define MACH_TYPE_HEROC                2092
+#define MACH_TYPE_ZENO6800             2093
+#define MACH_TYPE_SC2MCS               2094
+#define MACH_TYPE_GENE100              2095
+#define MACH_TYPE_AS353X               2096
+#define MACH_TYPE_SHEEVAPLUG           2097
+#define MACH_TYPE_AT91SAM9G20          2098
+#define MACH_TYPE_MV88F6192GTW_FE      2099
+#define MACH_TYPE_CC9200               2100
+#define MACH_TYPE_SM9200               2101
+#define MACH_TYPE_TP9200               2102
+#define MACH_TYPE_SNAPPERDV            2103
+#define MACH_TYPE_AVENGERS_LITE        2104
+#define MACH_TYPE_AVENGERS_LITE1       2105
+#define MACH_TYPE_OMAP3AXON            2106
+#define MACH_TYPE_MA8XX                2107
+#define MACH_TYPE_MP201EK              2108
+#define MACH_TYPE_DAVINCI_TUX          2109
+#define MACH_TYPE_MPA1600              2110
+#define MACH_TYPE_PELCO_TROY           2111
+#define MACH_TYPE_NSB667               2112
+#define MACH_TYPE_ROVERS5_4MPIX        2113
+#define MACH_TYPE_TWOCOM               2114
+#define MACH_TYPE_UBISYS_P9_RCU3R2     2115
+#define MACH_TYPE_HERO_ESPRESSO        2116
+#define MACH_TYPE_AFEUSB               2117
+#define MACH_TYPE_T830                 2118
+#define MACH_TYPE_SPD8020_CC           2119
+#define MACH_TYPE_OM_3D7K              2120
+#define MACH_TYPE_PICOCOM2             2121
+#define MACH_TYPE_UWG4MX27             2122
+#define MACH_TYPE_UWG4MX31             2123
+#define MACH_TYPE_CHERRY               2124
+#define MACH_TYPE_MX51_BABBAGE         2125
+#define MACH_TYPE_S3C2440TURKIYE       2126
+#define MACH_TYPE_TX37                 2127
+#define MACH_TYPE_SBC2800_9G20         2128
+#define MACH_TYPE_BENZGLB              2129
+#define MACH_TYPE_BENZTD               2130
+#define MACH_TYPE_CARTESIO_PLUS        2131
+#define MACH_TYPE_SOLRAD_G20           2132
+#define MACH_TYPE_MX27WALLACE          2133
+#define MACH_TYPE_FMZWEBMODUL          2134
+#define MACH_TYPE_RD78X00_MASA         2135
+#define MACH_TYPE_SMALLOGGER           2136
+#define MACH_TYPE_CCW9P9215            2137
+#define MACH_TYPE_DM355_LEOPARD        2138
+#define MACH_TYPE_TS219                2139
+#define MACH_TYPE_TNY_A9263            2140
+#define MACH_TYPE_APOLLO               2141
+#define MACH_TYPE_AT91CAP9STK          2142
+#define MACH_TYPE_SPC300               2143
+#define MACH_TYPE_EKO                  2144
+#define MACH_TYPE_CCW9M2443            2145
+#define MACH_TYPE_CCW9M2443JS          2146
+#define MACH_TYPE_M2M_ROUTER_DEVICE    2147
+#define MACH_TYPE_STAR9104NAS          2148
+#define MACH_TYPE_PCA100               2149
+#define MACH_TYPE_Z3_DM365_MOD_01      2150
+#define MACH_TYPE_HIPOX                2151
+#define MACH_TYPE_OMAP3_PITEDS         2152
+#define MACH_TYPE_BM150R               2153
+#define MACH_TYPE_TBONE                2154
+#define MACH_TYPE_MERLIN               2155
+#define MACH_TYPE_FALCON               2156
+#define MACH_TYPE_DAVINCI_DA850_EVM    2157
+#define MACH_TYPE_S5P6440              2158
+#define MACH_TYPE_AT91SAM9G10EK        2159
+#define MACH_TYPE_OMAP_4430SDP         2160
+#define MACH_TYPE_LPC313X              2161
+#define MACH_TYPE_MAGX_ZN5             2162
+#define MACH_TYPE_MAGX_EM30            2163
+#define MACH_TYPE_MAGX_VE66            2164
+#define MACH_TYPE_MEESC                2165
+#define MACH_TYPE_OTC570               2166
+#define MACH_TYPE_BCU2412              2167
+#define MACH_TYPE_BEACON               2168
+#define MACH_TYPE_ACTIA_TGW            2169
+#define MACH_TYPE_E4430                2170
+#define MACH_TYPE_QL300                2171
+#define MACH_TYPE_BTMAVB101            2172
+#define MACH_TYPE_BTMAWB101            2173
+#define MACH_TYPE_SQ201                2174
+#define MACH_TYPE_QUATRO45XX           2175
+#define MACH_TYPE_OPENPAD              2176
+#define MACH_TYPE_TX25                 2177
+#define MACH_TYPE_OMAP3_TORPEDO        2178
+#define MACH_TYPE_HTCRAPHAEL_K         2179
+#define MACH_TYPE_LAL43                2181
+#define MACH_TYPE_HTCRAPHAEL_CDMA500   2182
+#define MACH_TYPE_ANW6410              2183
+#define MACH_TYPE_HTCPROPHET           2185
+#define MACH_TYPE_CFA_10022            2186
+#define MACH_TYPE_IMX27_VISSTRIM_M10   2187
+#define MACH_TYPE_PX2IMX27             2188
+#define MACH_TYPE_STM3210E_EVAL        2189
+#define MACH_TYPE_DVS10                2190
+#define MACH_TYPE_PORTUXG20            2191
+#define MACH_TYPE_ARM_SPV              2192
+#define MACH_TYPE_SMDKC110             2193
+#define MACH_TYPE_CABESPRESSO          2194
+#define MACH_TYPE_HMC800               2195
+#define MACH_TYPE_SHOLES               2196
+#define MACH_TYPE_BTMXC31              2197
+#define MACH_TYPE_DT501                2198
+#define MACH_TYPE_KTX                  2199
+#define MACH_TYPE_OMAP3517EVM          2200
+#define MACH_TYPE_NETSPACE_V2          2201
+#define MACH_TYPE_NETSPACE_MAX_V2      2202
+#define MACH_TYPE_D2NET_V2             2203
+#define MACH_TYPE_NET2BIG_V2           2204
+#define MACH_TYPE_NET4BIG_V2           2205
+#define MACH_TYPE_NET5BIG_V2           2206
+#define MACH_TYPE_ENDB2443             2207
+#define MACH_TYPE_INETSPACE_V2         2208
+#define MACH_TYPE_TROS                 2209
+#define MACH_TYPE_PELCO_HOMER          2210
+#define MACH_TYPE_OFSP8                2211
+#define MACH_TYPE_AT91SAM9G45EKES      2212
+#define MACH_TYPE_GUF_CUPID            2213
+#define MACH_TYPE_EAB1R                2214
+#define MACH_TYPE_DESIREC              2215
+#define MACH_TYPE_CORDOBA              2216
+#define MACH_TYPE_IRVINE               2217
+#define MACH_TYPE_SFF772               2218
+#define MACH_TYPE_PELCO_MILANO         2219
+#define MACH_TYPE_PC7302               2220
+#define MACH_TYPE_BIP6000              2221
+#define MACH_TYPE_SILVERMOON           2222
+#define MACH_TYPE_VC0830               2223
+#define MACH_TYPE_DT430                2224
+#define MACH_TYPE_JI42PF               2225
+#define MACH_TYPE_GNET_KSM             2226
+#define MACH_TYPE_GNET_SGM             2227
+#define MACH_TYPE_GNET_SGR             2228
+#define MACH_TYPE_OMAP3_ICETEKEVM      2229
+#define MACH_TYPE_PNP                  2230
+#define MACH_TYPE_CTERA_2BAY_K         2231
+#define MACH_TYPE_CTERA_2BAY_U         2232
+#define MACH_TYPE_SAS_C                2233
+#define MACH_TYPE_VMA2315              2234
+#define MACH_TYPE_VCS                  2235
+#define MACH_TYPE_SPEAR600             2236
+#define MACH_TYPE_SPEAR300             2237
+#define MACH_TYPE_SPEAR1300            2238
+#define MACH_TYPE_LILLY1131            2239
+#define MACH_TYPE_ARVOO_AX301          2240
+#define MACH_TYPE_MAPPHONE             2241
+#define MACH_TYPE_LEGEND               2242
+#define MACH_TYPE_SALSA                2243
+#define MACH_TYPE_LOUNGE               2244
+#define MACH_TYPE_VISION               2245
+#define MACH_TYPE_VMB20                2246
+#define MACH_TYPE_HY2410               2247
+#define MACH_TYPE_HY9315               2248
+#define MACH_TYPE_BULLWINKLE           2249
+#define MACH_TYPE_ARM_ULTIMATOR2       2250
+#define MACH_TYPE_VS_V210              2252
+#define MACH_TYPE_VS_V212              2253
+#define MACH_TYPE_HMT                  2254
+#define MACH_TYPE_KM_KIRKWOOD          2255
+#define MACH_TYPE_VESPER               2256
+#define MACH_TYPE_STR9                 2257
+#define MACH_TYPE_OMAP3_WL_FF          2258
+#define MACH_TYPE_SIMCOM               2259
+#define MACH_TYPE_MCWEBIO              2260
+#define MACH_TYPE_OMAP3_PHRAZER        2261
+#define MACH_TYPE_DARWIN               2262
+#define MACH_TYPE_ORATISCOMU           2263
+#define MACH_TYPE_RTSBC20              2264
+#define MACH_TYPE_I780                 2265
+#define MACH_TYPE_GEMINI324            2266
+#define MACH_TYPE_ORATISLAN            2267
+#define MACH_TYPE_ORATISALOG           2268
+#define MACH_TYPE_ORATISMADI           2269
+#define MACH_TYPE_ORATISOT16           2270
+#define MACH_TYPE_ORATISDESK           2271
+#define MACH_TYPE_VEXPRESS             2272
+#define MACH_TYPE_SINTEXO              2273
+#define MACH_TYPE_CM3389               2274
+#define MACH_TYPE_OMAP3_CIO            2275
+#define MACH_TYPE_SGH_I900             2276
+#define MACH_TYPE_BST100               2277
+#define MACH_TYPE_PASSION              2278
+#define MACH_TYPE_INDESIGN_AT91SAM     2279
+#define MACH_TYPE_C4_BADGER            2280
+#define MACH_TYPE_C4_VIPER             2281
+#define MACH_TYPE_D2NET                2282
+#define MACH_TYPE_BIGDISK              2283
+#define MACH_TYPE_NOTALVISION          2284
+#define MACH_TYPE_OMAP3_KBOC           2285
+#define MACH_TYPE_CYCLONE              2286
+#define MACH_TYPE_NINJA                2287
+#define MACH_TYPE_AT91SAM9G20EK_2MMC   2288
+#define MACH_TYPE_BCMRING              2289
+#define MACH_TYPE_RESOL_DL2            2290
+#define MACH_TYPE_IFOSW                2291
+#define MACH_TYPE_HTCRHODIUM           2292
+#define MACH_TYPE_HTCTOPAZ             2293
+#define MACH_TYPE_MATRIX504            2294
+#define MACH_TYPE_MRFSA                2295
+#define MACH_TYPE_SC_P270              2296
+#define MACH_TYPE_ATLAS5_EVB           2297
+#define MACH_TYPE_PELCO_LOBOX          2298
+#define MACH_TYPE_DILAX_PCU200         2299
+#define MACH_TYPE_LEONARDO             2300
+#define MACH_TYPE_ZORAN_APPROACH7      2301
+#define MACH_TYPE_DP6XX                2302
+#define MACH_TYPE_BCM2153_VESPER       2303
+#define MACH_TYPE_MAHIMAHI             2304
+#define MACH_TYPE_CLICKC               2305
+#define MACH_TYPE_ZB_GATEWAY           2306
+#define MACH_TYPE_TAZCARD              2307
+#define MACH_TYPE_TAZDEV               2308
+#define MACH_TYPE_ANNAX_CB_ARM         2309
+#define MACH_TYPE_ANNAX_DM3            2310
+#define MACH_TYPE_CEREBRIC             2311
+#define MACH_TYPE_ORCA                 2312
+#define MACH_TYPE_PC9260               2313
+#define MACH_TYPE_EMS285A              2314
+#define MACH_TYPE_GEC2410              2315
+#define MACH_TYPE_GEC2440              2316
+#define MACH_TYPE_ARCH_MW903           2317
+#define MACH_TYPE_MW2440               2318
+#define MACH_TYPE_ECAC2378             2319
+#define MACH_TYPE_TAZKIOSK             2320
+#define MACH_TYPE_WHITERABBIT_MCH      2321
+#define MACH_TYPE_SBOX9263             2322
+#define MACH_TYPE_SMDK6442             2324
+#define MACH_TYPE_OPENRD_BASE          2325
+#define MACH_TYPE_INCREDIBLE           2326
+#define MACH_TYPE_INCREDIBLEC          2327
+#define MACH_TYPE_HEROCT               2328
+#define MACH_TYPE_MMNET1000            2329
+#define MACH_TYPE_DEVKIT8000           2330
+#define MACH_TYPE_DEVKIT9000           2331
+#define MACH_TYPE_MX31TXTR             2332
+#define MACH_TYPE_U380                 2333
+#define MACH_TYPE_HUALU_BOARD          2334
+#define MACH_TYPE_NPCMX50              2335
+#define MACH_TYPE_MX51_EFIKAMX         2336
+#define MACH_TYPE_MX51_LANGE52         2337
+#define MACH_TYPE_RIOM                 2338
+#define MACH_TYPE_COMCAS               2339
+#define MACH_TYPE_WSI_MX27             2340
+#define MACH_TYPE_CM_T35               2341
+#define MACH_TYPE_NET2BIG              2342
+#define MACH_TYPE_MOTOROLA_A1600       2343
+#define MACH_TYPE_IGEP0020             2344
+#define MACH_TYPE_IGEP0010             2345
+#define MACH_TYPE_MV6281GTWGE2         2346
+#define MACH_TYPE_SCAT100              2347
+#define MACH_TYPE_SANMINA              2348
+#define MACH_TYPE_MOMENTO              2349
+#define MACH_TYPE_NUC9XX               2350
+#define MACH_TYPE_NUC910EVB            2351
+#define MACH_TYPE_NUC920EVB            2352
+#define MACH_TYPE_NUC950EVB            2353
+#define MACH_TYPE_NUC945EVB            2354
+#define MACH_TYPE_NUC960EVB            2355
+#define MACH_TYPE_NUC932EVB            2356
+#define MACH_TYPE_NUC900               2357
+#define MACH_TYPE_SD1SOC               2358
+#define MACH_TYPE_LN2440BC             2359
+#define MACH_TYPE_RSBC                 2360
+#define MACH_TYPE_OPENRD_CLIENT        2361
+#define MACH_TYPE_HPIPAQ11X            2362
+#define MACH_TYPE_WAYLAND              2363
+#define MACH_TYPE_ACNBSX102            2364
+#define MACH_TYPE_HWAT91               2365
+#define MACH_TYPE_AT91SAM9263CS        2366
+#define MACH_TYPE_CSB732               2367
+#define MACH_TYPE_U8500                2368
+#define MACH_TYPE_HUQIU                2369
+#define MACH_TYPE_MX51_EFIKASB         2370
+#define MACH_TYPE_PMT1G                2371
+#define MACH_TYPE_HTCELF               2372
+#define MACH_TYPE_ARMADILLO420         2373
+#define MACH_TYPE_ARMADILLO440         2374
+#define MACH_TYPE_U_CHIP_DUAL_ARM      2375
+#define MACH_TYPE_CSR_BDB3             2376
+#define MACH_TYPE_DOLBY_CAT1018        2377
+#define MACH_TYPE_HY9307               2378
+#define MACH_TYPE_A_ES                 2379
+#define MACH_TYPE_DAVINCI_IRIF         2380
+#define MACH_TYPE_AGAMA9263            2381
+#define MACH_TYPE_MARVELL_JASPER       2382
+#define MACH_TYPE_FLINT                2383
+#define MACH_TYPE_TAVOREVB3            2384
+#define MACH_TYPE_SCH_M490             2386
+#define MACH_TYPE_RBL01                2387
+#define MACH_TYPE_OMNIFI               2388
+#define MACH_TYPE_OTAVALO              2389
+#define MACH_TYPE_HTC_EXCALIBUR_S620   2391
+#define MACH_TYPE_HTC_OPAL             2392
+#define MACH_TYPE_TOUCHBOOK            2393
+#define MACH_TYPE_LATTE                2394
+#define MACH_TYPE_XA200                2395
+#define MACH_TYPE_NIMROD               2396
+#define MACH_TYPE_CC9P9215_3G          2397
+#define MACH_TYPE_CC9P9215_3GJS        2398
+#define MACH_TYPE_TK71                 2399
+#define MACH_TYPE_COMHAM3525           2400
+#define MACH_TYPE_MX31EREBUS           2401
+#define MACH_TYPE_MCARDMX27            2402
+#define MACH_TYPE_PARADISE             2403
+#define MACH_TYPE_TIDE                 2404
+#define MACH_TYPE_WZL2440              2405
+#define MACH_TYPE_SDRDEMO              2406
+#define MACH_TYPE_ETHERCAN2            2407
+#define MACH_TYPE_ECMIMG20             2408
+#define MACH_TYPE_OMAP_DRAGON          2409
+#define MACH_TYPE_HALO                 2410
+#define MACH_TYPE_HUANGSHAN            2411
+#define MACH_TYPE_VL_MA2SC             2412
+#define MACH_TYPE_RAUMFELD_RC          2413
+#define MACH_TYPE_RAUMFELD_CONNECTOR   2414
+#define MACH_TYPE_RAUMFELD_SPEAKER     2415
+#define MACH_TYPE_MULTIBUS_MASTER      2416
+#define MACH_TYPE_MULTIBUS_PBK         2417
+#define MACH_TYPE_TNETV107X            2418
+#define MACH_TYPE_SNAKE                2419
+#define MACH_TYPE_CWMX27               2420
+#define MACH_TYPE_SCH_M480             2421
+#define MACH_TYPE_PLATYPUS             2422
+#define MACH_TYPE_PSS2                 2423
+#define MACH_TYPE_DAVINCI_APM150       2424
+#define MACH_TYPE_STR9100              2425
+#define MACH_TYPE_NET5BIG              2426
+#define MACH_TYPE_SEABED9263           2427
+#define MACH_TYPE_MX51_M2ID            2428
+#define MACH_TYPE_OCTVOCPLUS_EB        2429
+#define MACH_TYPE_KLK_FIREFOX          2430
+#define MACH_TYPE_KLK_WIRMA_MODULE     2431
+#define MACH_TYPE_KLK_WIRMA_MMI        2432
+#define MACH_TYPE_SUPERSONIC           2433
+#define MACH_TYPE_LIBERTY              2434
+#define MACH_TYPE_MH355                2435
+#define MACH_TYPE_PC7802               2436
+#define MACH_TYPE_GNET_SGC             2437
+#define MACH_TYPE_EINSTEIN15           2438
+#define MACH_TYPE_CMPD                 2439
+#define MACH_TYPE_DAVINCI_HASE1        2440
+#define MACH_TYPE_LGEINCITEPHONE       2441
+#define MACH_TYPE_EA313X               2442
+#define MACH_TYPE_FWBD_39064           2443
+#define MACH_TYPE_FWBD_390128          2444
+#define MACH_TYPE_PELCO_MOE            2445
+#define MACH_TYPE_MINIMIX27            2446
+#define MACH_TYPE_OMAP3_THUNDER        2447
+#define MACH_TYPE_PASSIONC             2448
+#define MACH_TYPE_MX27AMATA            2449
+#define MACH_TYPE_BGAT1                2450
+#define MACH_TYPE_BUZZ                 2451
+#define MACH_TYPE_MB9G20               2452
+#define MACH_TYPE_YUSHAN               2453
+#define MACH_TYPE_LIZARD               2454
+#define MACH_TYPE_OMAP3POLYCOM         2455
+#define MACH_TYPE_SMDKV210             2456
+#define MACH_TYPE_BRAVO                2457
+#define MACH_TYPE_SIOGENTOO1           2458
+#define MACH_TYPE_SIOGENTOO2           2459
+#define MACH_TYPE_SM3K                 2460
+#define MACH_TYPE_ACER_TEMPO_F900      2461
+#define MACH_TYPE_GLITTERTIND          2463
+#define MACH_TYPE_OMAP_ZOOM3           2464
+#define MACH_TYPE_OMAP_3630SDP         2465
+#define MACH_TYPE_CYBOOK2440           2466
+#define MACH_TYPE_TORINO_S             2467
+#define MACH_TYPE_HAVANA               2468
+#define MACH_TYPE_BEAUMONT_11          2469
+#define MACH_TYPE_VANGUARD             2470
+#define MACH_TYPE_S5PC110_DRACO        2471
+#define MACH_TYPE_CARTESIO_TWO         2472
+#define MACH_TYPE_ASTER                2473
+#define MACH_TYPE_VOGUESV210           2474
+#define MACH_TYPE_ACM500X              2475
+#define MACH_TYPE_KM9260               2476
+#define MACH_TYPE_NIDEFLEXG1           2477
+#define MACH_TYPE_CTERA_PLUG_IO        2478
+#define MACH_TYPE_SMARTQ7              2479
+#define MACH_TYPE_AT91SAM9G10EK2       2480
+#define MACH_TYPE_ASUSP527             2481
+#define MACH_TYPE_AT91SAM9G20MPM2      2482
+#define MACH_TYPE_TOPASA900            2483
+#define MACH_TYPE_ELECTRUM_100         2484
+#define MACH_TYPE_MX51GRB              2485
+#define MACH_TYPE_XEA300               2486
+#define MACH_TYPE_HTCSTARTREK          2487
+#define MACH_TYPE_LIMA                 2488
+#define MACH_TYPE_CSB740               2489
+#define MACH_TYPE_USB_S8815            2490
+#define MACH_TYPE_WATSON_EFM_PLUGIN    2491
+#define MACH_TYPE_MILKYWAY             2492
+#define MACH_TYPE_G4EVM                2493
+#define MACH_TYPE_PICOMOD6             2494
+#define MACH_TYPE_OMAPL138_HAWKBOARD   2495
+#define MACH_TYPE_IP6000               2496
+#define MACH_TYPE_IP6010               2497
+#define MACH_TYPE_UTM400               2498
+#define MACH_TYPE_OMAP3_ZYBEX          2499
+#define MACH_TYPE_WIRELESS_SPACE       2500
+#define MACH_TYPE_SX560                2501
+#define MACH_TYPE_TS41X                2502
+#define MACH_TYPE_ELPHEL10373          2503
+#define MACH_TYPE_RHOBOT               2504
+#define MACH_TYPE_MX51_REFRESH         2505
+#define MACH_TYPE_LS9260               2506
+#define MACH_TYPE_SHANK                2507
+#define MACH_TYPE_QSD8X50_ST1          2508
+#define MACH_TYPE_AT91SAM9M10EKES      2509
+#define MACH_TYPE_HIRAM                2510
+#define MACH_TYPE_PHY3250              2511
+#define MACH_TYPE_EA3250               2512
+#define MACH_TYPE_FDI3250              2513
+#define MACH_TYPE_AT91SAM9263NIT       2515
+#define MACH_TYPE_CCMX51               2516
+#define MACH_TYPE_CCMX51JS             2517
+#define MACH_TYPE_CCWMX51              2518
+#define MACH_TYPE_CCWMX51JS            2519
+#define MACH_TYPE_MINI6410             2520
+#define MACH_TYPE_TINY6410             2521
+#define MACH_TYPE_NANO6410             2522
+#define MACH_TYPE_AT572D940HFNLDB      2523
+#define MACH_TYPE_HTCLEO               2524
+#define MACH_TYPE_AVP13                2525
+#define MACH_TYPE_XXSVIDEOD            2526
+#define MACH_TYPE_VPNEXT               2527
+#define MACH_TYPE_SWARCO_ITC3          2528
+#define MACH_TYPE_TX51                 2529
+#define MACH_TYPE_DOLBY_CAT1021        2530
+#define MACH_TYPE_MX28EVK              2531
+#define MACH_TYPE_PHOENIX260           2532
+#define MACH_TYPE_UVACA_STORK          2533
+#define MACH_TYPE_SMARTQ5              2534
+#define MACH_TYPE_ALL3078              2535
+#define MACH_TYPE_CTERA_2BAY_DS        2536
+#define MACH_TYPE_SIOGENTOO3           2537
+#define MACH_TYPE_EPB5000              2538
+#define MACH_TYPE_HY9263               2539
+#define MACH_TYPE_ACER_TEMPO_M900      2540
+#define MACH_TYPE_ACER_TEMPO_DX900     2541
+#define MACH_TYPE_ACER_TEMPO_X960      2542
+#define MACH_TYPE_ACER_ETEN_V900       2543
+#define MACH_TYPE_ACER_ETEN_X900       2544
+#define MACH_TYPE_BONNELL              2545
+#define MACH_TYPE_OHT_MX27             2546
+#define MACH_TYPE_HTCQUARTZ            2547
+#define MACH_TYPE_DAVINCI_DM6467TEVM   2548
+#define MACH_TYPE_C3AX03               2549
+#define MACH_TYPE_MXT_TD60             2550
+#define MACH_TYPE_ESYX                 2551
+#define MACH_TYPE_DOVE_DB2             2552
+#define MACH_TYPE_BULLDOG              2553
+#define MACH_TYPE_DERELL_ME2000        2554
+#define MACH_TYPE_BCMRING_BASE         2555
+#define MACH_TYPE_BCMRING_EVM          2556
+#define MACH_TYPE_BCMRING_EVM_JAZZ     2557
+#define MACH_TYPE_BCMRING_SP           2558
+#define MACH_TYPE_BCMRING_SV           2559
+#define MACH_TYPE_BCMRING_SV_JAZZ      2560
+#define MACH_TYPE_BCMRING_TABLET       2561
+#define MACH_TYPE_BCMRING_VP           2562
+#define MACH_TYPE_BCMRING_EVM_SEIKOR   2563
+#define MACH_TYPE_BCMRING_SP_WQVGA     2564
+#define MACH_TYPE_BCMRING_CUSTOM       2565
+#define MACH_TYPE_ACER_S200            2566
+#define MACH_TYPE_BT270                2567
+#define MACH_TYPE_ISEO                 2568
+#define MACH_TYPE_CEZANNE              2569
+#define MACH_TYPE_LUCCA                2570
+#define MACH_TYPE_SUPERSMART           2571
+#define MACH_TYPE_CS_MISANO            2572
+#define MACH_TYPE_MAGNOLIA2            2573
+#define MACH_TYPE_EMXX                 2574
+#define MACH_TYPE_OUTLAW               2575
+#define MACH_TYPE_RIOT_BEI2            2576
+#define MACH_TYPE_RIOT_VOX             2577
+#define MACH_TYPE_RIOT_X37             2578
+#define MACH_TYPE_MEGA25MX             2579
+#define MACH_TYPE_BENZINA2             2580
+#define MACH_TYPE_IGNITE               2581
+#define MACH_TYPE_FOGGIA               2582
+#define MACH_TYPE_AREZZO               2583
+#define MACH_TYPE_LEICA_SKYWALKER      2584
+#define MACH_TYPE_JACINTO2_JAMR        2585
+#define MACH_TYPE_GTS_NOVA             2586
+#define MACH_TYPE_P3600                2587
+#define MACH_TYPE_DLT2                 2588
+#define MACH_TYPE_DF3120               2589
+#define MACH_TYPE_ECUCORE_9G20         2590
+#define MACH_TYPE_NAUTEL_LPC3240       2591
+#define MACH_TYPE_GLACIER              2592
+#define MACH_TYPE_PHRAZER_BULLDOG      2593
+#define MACH_TYPE_OMAP3_BULLDOG        2594
+#define MACH_TYPE_PCA101               2595
+#define MACH_TYPE_BUZZC                2596
+#define MACH_TYPE_SASIE2               2597
+#define MACH_TYPE_SMARTMETER_DL        2599
+#define MACH_TYPE_WZL6410              2600
+#define MACH_TYPE_WZL6410M             2601
+#define MACH_TYPE_WZL6410F             2602
+#define MACH_TYPE_WZL6410I             2603
+#define MACH_TYPE_SPACECOM1            2604
+#define MACH_TYPE_PINGU920             2605
+#define MACH_TYPE_BRAVOC               2606
+#define MACH_TYPE_VDSSW                2608
+#define MACH_TYPE_ROMULUS              2609
+#define MACH_TYPE_OMAP_MAGIC           2610
+#define MACH_TYPE_ELTD100              2611
+#define MACH_TYPE_CAPC7117             2612
+#define MACH_TYPE_SWAN                 2613
+#define MACH_TYPE_VEU                  2614
+#define MACH_TYPE_RM2                  2615
+#define MACH_TYPE_TT2100               2616
+#define MACH_TYPE_VENICE               2617
+#define MACH_TYPE_PC7323               2618
+#define MACH_TYPE_MASP                 2619
+#define MACH_TYPE_FUJITSU_TVSTBSOC     2620
+#define MACH_TYPE_FUJITSU_TVSTBSOC1    2621
+#define MACH_TYPE_LEXIKON              2622
+#define MACH_TYPE_MINI2440V2           2623
+#define MACH_TYPE_ICONTROL             2624
+#define MACH_TYPE_GPLUGD               2625
+#define MACH_TYPE_QSD8X50A_ST1_1       2626
+#define MACH_TYPE_QSD8X50A_ST1_5       2627
+#define MACH_TYPE_BEE                  2628
+#define MACH_TYPE_MX23EVK              2629
+#define MACH_TYPE_AP4EVB               2630
+#define MACH_TYPE_STOCKHOLM            2631
+#define MACH_TYPE_LPC_H3131            2632
+#define MACH_TYPE_STINGRAY             2633
+#define MACH_TYPE_KRAKEN               2634
+#define MACH_TYPE_GW2388               2635
+#define MACH_TYPE_JADECPU              2636
+#define MACH_TYPE_CARLISLE             2637
+#define MACH_TYPE_LUX_SF9              2638
+#define MACH_TYPE_NEMID_TB             2639
+#define MACH_TYPE_TERRIER              2640
+#define MACH_TYPE_TURBOT               2641
+#define MACH_TYPE_SANDDAB              2642
+#define MACH_TYPE_MX35_CICADA          2643
+#define MACH_TYPE_GHI2703D             2644
+#define MACH_TYPE_LUX_SFX9             2645
+#define MACH_TYPE_LUX_SF9G             2646
+#define MACH_TYPE_LUX_EDK9             2647
+#define MACH_TYPE_HW90240              2648
+#define MACH_TYPE_DM365_LEOPARD        2649
+#define MACH_TYPE_MITYOMAPL138         2650
+#define MACH_TYPE_SCAT110              2651
+#define MACH_TYPE_ACER_A1              2652
+#define MACH_TYPE_CMCONTROL            2653
+#define MACH_TYPE_PELCO_LAMAR          2654
+#define MACH_TYPE_RFP43                2655
+#define MACH_TYPE_SK86R0301            2656
+#define MACH_TYPE_CTPXA                2657
+#define MACH_TYPE_EPB_ARM9_A           2658
+#define MACH_TYPE_GURUPLUG             2659
+#define MACH_TYPE_SPEAR310             2660
+#define MACH_TYPE_SPEAR320             2661
+#define MACH_TYPE_ROBOTX               2662
+#define MACH_TYPE_LSXHL                2663
+#define MACH_TYPE_SMARTLITE            2664
+#define MACH_TYPE_CWS2                 2665
+#define MACH_TYPE_M619                 2666
+#define MACH_TYPE_SMARTVIEW            2667
+#define MACH_TYPE_LSA_SALSA            2668
+#define MACH_TYPE_KIZBOX               2669
+#define MACH_TYPE_HTCCHARMER           2670
+#define MACH_TYPE_GUF_NESO_LT          2671
+#define MACH_TYPE_PM9G45               2672
+#define MACH_TYPE_HTCPANTHER           2673
+#define MACH_TYPE_HTCPANTHER_CDMA      2674
+#define MACH_TYPE_REB01                2675
+#define MACH_TYPE_AQUILA               2676
+#define MACH_TYPE_SPARK_SLS_HW2        2677
+#define MACH_TYPE_ESATA_SHEEVAPLUG     2678
+#define MACH_TYPE_MSM7X30_SURF         2679
+#define MACH_TYPE_MICRO2440            2680
+#define MACH_TYPE_AM2440               2681
+#define MACH_TYPE_TQ2440               2682
+#define MACH_TYPE_EA2478DEVKIT         2683
+#define MACH_TYPE_AK880X               2684
+#define MACH_TYPE_COBRA3530            2685
+#define MACH_TYPE_PMPPB                2686
+#define MACH_TYPE_U6715                2687
+#define MACH_TYPE_AXAR1500_SENDER      2688
+#define MACH_TYPE_G30_DVB              2689
+#define MACH_TYPE_VC088X               2690
+#define MACH_TYPE_MIOA702              2691
+#define MACH_TYPE_HPMIN                2692
+#define MACH_TYPE_AK880XAK             2693
+#define MACH_TYPE_ARM926TOMAP850       2694
+#define MACH_TYPE_LKEVM                2695
+#define MACH_TYPE_MW6410               2696
+#define MACH_TYPE_TERASTATION_WXL      2697
+#define MACH_TYPE_CPU8000E             2698
+#define MACH_TYPE_TOKYO                2700
+#define MACH_TYPE_MSM7201A_SURF        2701
+#define MACH_TYPE_MSM7201A_FFA         2702
+#define MACH_TYPE_MSM7X25_SURF         2703
+#define MACH_TYPE_MSM7X25_FFA          2704
+#define MACH_TYPE_MSM7X27_SURF         2705
+#define MACH_TYPE_MSM7X27_FFA          2706
+#define MACH_TYPE_MSM7X30_FFA          2707
+#define MACH_TYPE_QSD8X50_SURF         2708
+#define MACH_TYPE_QSD8X50_COMET        2709
+#define MACH_TYPE_QSD8X50_FFA          2710
+#define MACH_TYPE_QSD8X50A_SURF        2711
+#define MACH_TYPE_QSD8X50A_FFA         2712
+#define MACH_TYPE_ADX_XGCP10           2713
+#define MACH_TYPE_MCGWUMTS2A           2714
+#define MACH_TYPE_MOBIKT               2715
+#define MACH_TYPE_MX53_EVK             2716
+#define MACH_TYPE_IGEP0030             2717
+#define MACH_TYPE_AXELL_H40_H50_CTRL   2718
+#define MACH_TYPE_DTCOMMOD             2719
+#define MACH_TYPE_GOULD                2720
+#define MACH_TYPE_SIBERIA              2721
+#define MACH_TYPE_SBC3530              2722
+#define MACH_TYPE_QARM                 2723
+#define MACH_TYPE_MIPS                 2724
+#define MACH_TYPE_MX27GRB              2725
+#define MACH_TYPE_SBC8100              2726
+#define MACH_TYPE_SAARB                2727
+#define MACH_TYPE_OMAP3MINI            2728
+#define MACH_TYPE_CNMBOOK7SE           2729
+#define MACH_TYPE_CATAN                2730
+#define MACH_TYPE_HARMONY              2731
+#define MACH_TYPE_TONGA                2732
+#define MACH_TYPE_CYBOOK_ORIZON        2733
+#define MACH_TYPE_HTCRHODIUMCDMA       2734
+#define MACH_TYPE_EPC_G45              2735
+#define MACH_TYPE_EPC_LPC3250          2736
+#define MACH_TYPE_MXC91341EVB          2737
+#define MACH_TYPE_RTW1000              2738
+#define MACH_TYPE_BOBCAT               2739
+#define MACH_TYPE_TRIZEPS6             2740
+#define MACH_TYPE_MSM7X30_FLUID        2741
+#define MACH_TYPE_NEDAP9263            2742
+#define MACH_TYPE_NETGEAR_MS2110       2743
+#define MACH_TYPE_BMX                  2744
+#define MACH_TYPE_NETSTREAM            2745
+#define MACH_TYPE_VPNEXT_RCU           2746
+#define MACH_TYPE_VPNEXT_MPU           2747
+#define MACH_TYPE_BCMRING_TABLET_V1    2748
+#define MACH_TYPE_SGARM10              2749
+#define MACH_TYPE_OMAP3_CPS            2751
+#define MACH_TYPE_AXAR1500_RECEIVER    2752
+#define MACH_TYPE_WBD222               2753
+#define MACH_TYPE_MT65XX               2754
+#define MACH_TYPE_MSM8X60_SURF         2755
+#define MACH_TYPE_MSM8X60_SIM          2756
+#define MACH_TYPE_TCC8000_SDK          2758
+#define MACH_TYPE_NANOS                2759
+#define MACH_TYPE_STAMP9G10            2760
+#define MACH_TYPE_STAMP9G45            2761
+#define MACH_TYPE_H6053                2762
+#define MACH_TYPE_SMINT01              2763
+#define MACH_TYPE_PRTLVT2              2764
+#define MACH_TYPE_AP420                2765
+#define MACH_TYPE_DAVINCI_DM365_FC     2767
+#define MACH_TYPE_MSM8X55_SURF         2768
+#define MACH_TYPE_MSM8X55_FFA          2769
+#define MACH_TYPE_ESL_VAMANA           2770
+#define MACH_TYPE_SBC35                2771
+#define MACH_TYPE_MPX6446              2772
+#define MACH_TYPE_OREO_CONTROLLER      2773
+#define MACH_TYPE_KOPIN_MODELS         2774
+#define MACH_TYPE_TTC_VISION2          2775
+#define MACH_TYPE_CNS3420VB            2776
+#define MACH_TYPE_LPC2                 2777
+#define MACH_TYPE_OLYMPUS              2778
+#define MACH_TYPE_VORTEX               2779
+#define MACH_TYPE_S5PC200              2780
+#define MACH_TYPE_ECUCORE_9263         2781
+#define MACH_TYPE_SMDKC200             2782
+#define MACH_TYPE_EMSISO_SX27          2783
+#define MACH_TYPE_APX_SOM9G45_EK       2784
+#define MACH_TYPE_SONGSHAN             2785
+#define MACH_TYPE_TIANSHAN             2786
+#define MACH_TYPE_VPX500               2787
+#define MACH_TYPE_AM3517SAM            2788
+#define MACH_TYPE_SKAT91_SIM508        2789
+#define MACH_TYPE_SKAT91_S3E           2790
+#define MACH_TYPE_OMAP4_PANDA          2791
+#define MACH_TYPE_DF7220               2792
+#define MACH_TYPE_NEMINI               2793
+#define MACH_TYPE_T8200                2794
+#define MACH_TYPE_APF51                2795
+#define MACH_TYPE_DR_RC_UNIT           2796
+#define MACH_TYPE_BORDEAUX             2797
+#define MACH_TYPE_CATANIA_B            2798
+#define MACH_TYPE_MX51_OCEAN           2799
+#define MACH_TYPE_TI8168EVM            2800
+#define MACH_TYPE_NEOCOREOMAP          2801
+#define MACH_TYPE_WITHINGS_WBP         2802
+#define MACH_TYPE_DBPS                 2803
+#define MACH_TYPE_PCBFP0001            2805
+#define MACH_TYPE_SPEEDY               2806
+#define MACH_TYPE_CHRYSAOR             2807
+#define MACH_TYPE_TANGO                2808
+#define MACH_TYPE_SYNOLOGY_DSX11       2809
+#define MACH_TYPE_HANLIN_V3EXT         2810
+#define MACH_TYPE_HANLIN_V5            2811
+#define MACH_TYPE_HANLIN_V3PLUS        2812
+#define MACH_TYPE_IRIVER_STORY         2813
+#define MACH_TYPE_IREX_ILIAD           2814
+#define MACH_TYPE_IREX_DR1000          2815
+#define MACH_TYPE_TETON_BGA            2816
+#define MACH_TYPE_SNAPPER9G45          2817
+#define MACH_TYPE_TAM3517              2818
+#define MACH_TYPE_PDC100               2819
+#define MACH_TYPE_EUKREA_CPUIMX25SD    2820
+#define MACH_TYPE_EUKREA_CPUIMX35SD    2821
+#define MACH_TYPE_EUKREA_CPUIMX51SD    2822
+#define MACH_TYPE_EUKREA_CPUIMX51      2823
+#define MACH_TYPE_P565                 2824
+#define MACH_TYPE_ACER_A4              2825
+#define MACH_TYPE_DAVINCI_DM368_BIP    2826
+#define MACH_TYPE_ESHARE               2827
+#define MACH_TYPE_WLBARGN              2829
+#define MACH_TYPE_BM170                2830
+#define MACH_TYPE_NETSPACE_MINI_V2     2831
+#define MACH_TYPE_NETSPACE_PLUG_V2     2832
+#define MACH_TYPE_SIEMENS_L1           2833
+#define MACH_TYPE_ELV_LCU1             2834
+#define MACH_TYPE_MCU1                 2835
+#define MACH_TYPE_OMAP3_TAO3530        2836
+#define MACH_TYPE_OMAP3_PCUTOUCH       2837
+#define MACH_TYPE_SMDKC210             2838
+#define MACH_TYPE_OMAP3_BRAILLO        2839
+#define MACH_TYPE_SPYPLUG              2840
+#define MACH_TYPE_GINGER               2841
+#define MACH_TYPE_TNY_T3530            2842
+#define MACH_TYPE_PCAAL1               2843
+#define MACH_TYPE_SPADE                2844
+#define MACH_TYPE_MXC25_TOPAZ          2845
+#define MACH_TYPE_T5325                2846
+#define MACH_TYPE_GW2361               2847
+#define MACH_TYPE_ELOG                 2848
+#define MACH_TYPE_INCOME               2849
+#define MACH_TYPE_BCM589X              2850
+#define MACH_TYPE_ETNA                 2851
+#define MACH_TYPE_HAWKS                2852
+#define MACH_TYPE_MESON                2853
+#define MACH_TYPE_XSBASE255            2854
+#define MACH_TYPE_PVM2030              2855
+#define MACH_TYPE_MIOA502              2856
+#define MACH_TYPE_VVBOX_SDORIG2        2857
+#define MACH_TYPE_VVBOX_SDLITE2        2858
+#define MACH_TYPE_VVBOX_SDPRO4         2859
+#define MACH_TYPE_HTC_SPV_M700         2860
+#define MACH_TYPE_MX257SX              2861
+#define MACH_TYPE_GONI                 2862
+#define MACH_TYPE_MSM8X55_SVLTE_FFA    2863
+#define MACH_TYPE_MSM8X55_SVLTE_SURF   2864
+#define MACH_TYPE_QUICKSTEP            2865
+#define MACH_TYPE_DMW96                2866
+#define MACH_TYPE_HAMMERHEAD           2867
+#define MACH_TYPE_TRIDENT              2868
+#define MACH_TYPE_LIGHTNING            2869
+#define MACH_TYPE_ICONNECT             2870
+#define MACH_TYPE_AUTOBOT              2871
+#define MACH_TYPE_COCONUT              2872
+#define MACH_TYPE_DURIAN               2873
+#define MACH_TYPE_CAYENNE              2874
+#define MACH_TYPE_FUJI                 2875
+#define MACH_TYPE_SYNOLOGY_6282        2876
+#define MACH_TYPE_EM1SY                2877
+#define MACH_TYPE_M502                 2878
+#define MACH_TYPE_MATRIX518            2879
+#define MACH_TYPE_TINY_GURNARD         2880
+#define MACH_TYPE_SPEAR1310            2881
+#define MACH_TYPE_BV07                 2882
+#define MACH_TYPE_MXT_TD61             2883
+#define MACH_TYPE_OPENRD_ULTIMATE      2884
+#define MACH_TYPE_DEVIXP               2885
+#define MACH_TYPE_MICCPT               2886
+#define MACH_TYPE_MIC256               2887
+#define MACH_TYPE_AS1167               2888
+#define MACH_TYPE_OMAP3_IBIZA          2889
+#define MACH_TYPE_U5500                2890
+#define MACH_TYPE_DAVINCI_PICTO        2891
+#define MACH_TYPE_MECHA                2892
+#define MACH_TYPE_BUBBA3               2893
+#define MACH_TYPE_PUPITRE              2894
+#define MACH_TYPE_TEGRA_VOGUE          2896
+#define MACH_TYPE_TEGRA_E1165          2897
+#define MACH_TYPE_SIMPLENET            2898
+#define MACH_TYPE_EC4350TBM            2899
+#define MACH_TYPE_PEC_TC               2900
+#define MACH_TYPE_PEC_HC2              2901
+#define MACH_TYPE_ESL_MOBILIS_A        2902
+#define MACH_TYPE_ESL_MOBILIS_B        2903
+#define MACH_TYPE_ESL_WAVE_A           2904
+#define MACH_TYPE_ESL_WAVE_B           2905
+#define MACH_TYPE_UNISENSE_MMM         2906
+#define MACH_TYPE_BLUESHARK            2907
+#define MACH_TYPE_E10                  2908
+#define MACH_TYPE_APP3K_ROBIN          2909
+#define MACH_TYPE_POV15HD              2910
+#define MACH_TYPE_STELLA               2911
+#define MACH_TYPE_LINKSTATION_LSCHL    2913
+#define MACH_TYPE_NETWALKER            2914
+#define MACH_TYPE_ACSX106              2915
+#define MACH_TYPE_ATLAS5_C1            2916
+#define MACH_TYPE_NSB3AST              2917
+#define MACH_TYPE_GNET_SLC             2918
+#define MACH_TYPE_AF4000               2919
+#define MACH_TYPE_ARK9431              2920
+#define MACH_TYPE_FS_S5PC100           2921
+#define MACH_TYPE_OMAP3505NOVA8        2922
+#define MACH_TYPE_OMAP3621_EDP1        2923
+#define MACH_TYPE_ORATISAES            2924
+#define MACH_TYPE_SMDKV310             2925
+#define MACH_TYPE_SIEMENS_L0           2926
+#define MACH_TYPE_VENTANA              2927
+#define MACH_TYPE_WM8505_7IN_NETBOOK   2928
+#define MACH_TYPE_EC4350SDB            2929
+#define MACH_TYPE_MIMAS                2930
+#define MACH_TYPE_TITAN                2931
+#define MACH_TYPE_CRANEBOARD           2932
+#define MACH_TYPE_ES2440               2933
+#define MACH_TYPE_NAJAY_A9263          2934
+#define MACH_TYPE_HTCTORNADO           2935
+#define MACH_TYPE_DIMM_MX257           2936
+#define MACH_TYPE_JIGEN                2937
+#define MACH_TYPE_SMDK6450             2938
+#define MACH_TYPE_MENO_QNG             2939
+#define MACH_TYPE_NS2416               2940
+#define MACH_TYPE_RPC353               2941
+#define MACH_TYPE_TQ6410               2942
+#define MACH_TYPE_SKY6410              2943
+#define MACH_TYPE_DYNASTY              2944
+#define MACH_TYPE_VIVO                 2945
+#define MACH_TYPE_BURY_BL7582          2946
+#define MACH_TYPE_BURY_BPS5270         2947
+#define MACH_TYPE_BASI                 2948
+#define MACH_TYPE_TN200                2949
+#define MACH_TYPE_C2MMI                2950
+#define MACH_TYPE_MESON_6236M          2951
+#define MACH_TYPE_MESON_8626M          2952
+#define MACH_TYPE_TUBE                 2953
+#define MACH_TYPE_MESSINA              2954
+#define MACH_TYPE_MX50_ARM2            2955
+#define MACH_TYPE_CETUS9263            2956
+#define MACH_TYPE_BROWNSTONE           2957
+#define MACH_TYPE_VMX25                2958
+#define MACH_TYPE_VMX51                2959
+#define MACH_TYPE_ABACUS               2960
+#define MACH_TYPE_CM4745               2961
+#define MACH_TYPE_ORATISLINK           2962
+#define MACH_TYPE_DAVINCI_DM365_DVR    2963
+#define MACH_TYPE_NETVIZ               2964
+#define MACH_TYPE_FLEXIBITY            2965
+#define MACH_TYPE_WLAN_COMPUTER        2966
+#define MACH_TYPE_LPC24XX              2967
+#define MACH_TYPE_SPICA                2968
+#define MACH_TYPE_GPSDISPLAY           2969
+#define MACH_TYPE_BIPNET               2970
+#define MACH_TYPE_OVERO_CTU_INERTIAL   2971
+#define MACH_TYPE_DAVINCI_DM355_MMM    2972
+#define MACH_TYPE_PC9260_V2            2973
+#define MACH_TYPE_PTX7545              2974
+#define MACH_TYPE_TM_EFDC              2975
+#define MACH_TYPE_OMAP3_WALDO1         2977
+#define MACH_TYPE_FLYER                2978
+#define MACH_TYPE_TORNADO3240          2979
+#define MACH_TYPE_SOLI_01              2980
+#define MACH_TYPE_OMAPL138_EUROPALC    2981
+#define MACH_TYPE_HELIOS_V1            2982
+#define MACH_TYPE_NETSPACE_LITE_V2     2983
+#define MACH_TYPE_SSC                  2984
+#define MACH_TYPE_PREMIERWAVE_EN       2985
+#define MACH_TYPE_WASABI               2986
+#define MACH_TYPE_MX50_RDP             2988
+#define MACH_TYPE_UNIVERSAL_C210       2989
+#define MACH_TYPE_REAL6410             2990
+#define MACH_TYPE_SPX_SAKURA           2991
+#define MACH_TYPE_IJ3K_2440            2992
+#define MACH_TYPE_OMAP3_BC10           2993
+#define MACH_TYPE_THEBE                2994
+#define MACH_TYPE_RV082                2995
+#define MACH_TYPE_ARMLGUEST            2996
+#define MACH_TYPE_TJINC1000            2997
+#define MACH_TYPE_DOCKSTAR             2998
+#define MACH_TYPE_AX8008               2999
+#define MACH_TYPE_GNET_SGCE            3000
+#define MACH_TYPE_PXWNAS_500_1000      3001
+#define MACH_TYPE_AWM2                 3003
+#define MACH_TYPE_TI8148EVM            3004
+#define MACH_TYPE_SEABOARD             3005
+#define MACH_TYPE_LINKSTATION_CHLV2    3006
+#define MACH_TYPE_TERA_PRO2_RACK       3007
+#define MACH_TYPE_RUBYS                3008
+#define MACH_TYPE_AQUARIUS             3009
+#define MACH_TYPE_MX53_ARD             3010
+#define MACH_TYPE_MX53_SMD             3011
+#define MACH_TYPE_LSWXL                3012
+#define MACH_TYPE_DOVE_AVNG_V3         3013
+#define MACH_TYPE_SDI_ESS_9263         3014
+#define MACH_TYPE_JOCPU550             3015
+#define MACH_TYPE_MSM8X60_RUMI3        3016
+#define MACH_TYPE_MSM8X60_FFA          3017
+#define MACH_TYPE_YANOMAMI             3018
+#define MACH_TYPE_GTA04                3019
+#define MACH_TYPE_CM_A510              3020
+#define MACH_TYPE_OMAP3_RFS200         3021
+#define MACH_TYPE_KX33XX               3022
+#define MACH_TYPE_PTX7510              3023
+#define MACH_TYPE_TOP9000              3024
+#define MACH_TYPE_TEENOTE              3025
+#define MACH_TYPE_TS3                  3026
+#define MACH_TYPE_A0                   3027
+#define MACH_TYPE_FSM9XXX_SURF         3028
+#define MACH_TYPE_FSM9XXX_FFA          3029
+#define MACH_TYPE_FRRHWCDMA60W         3030
+#define MACH_TYPE_REMUS                3031
+#define MACH_TYPE_AT91CAP7XDK          3032
+#define MACH_TYPE_AT91CAP7STK          3033
+#define MACH_TYPE_KT_SBC_SAM9_1        3034
+#define MACH_TYPE_ARMADA_XP_DB         3036
+#define MACH_TYPE_SPDM                 3037
+#define MACH_TYPE_GTIB                 3038
+#define MACH_TYPE_DGM3240              3039
+#define MACH_TYPE_ATLAS_I_LPE          3040
+#define MACH_TYPE_HTCMEGA              3041
+#define MACH_TYPE_TRICORDER            3042
+#define MACH_TYPE_TX28                 3043
+#define MACH_TYPE_BSTBRD               3044
+#define MACH_TYPE_PWB3090              3045
+#define MACH_TYPE_IDEA6410             3046
+#define MACH_TYPE_QBC9263              3047
+#define MACH_TYPE_BORABORA             3048
+#define MACH_TYPE_VALDEZ               3049
+#define MACH_TYPE_LS9G20               3050
+#define MACH_TYPE_MIOS_V1              3051
+#define MACH_TYPE_S5PC110_CRESPO       3052
+#define MACH_TYPE_CONTROLTEK9G20       3053
+#define MACH_TYPE_TIN307               3054
+#define MACH_TYPE_TIN510               3055
+#define MACH_TYPE_EP3517               3056
+#define MACH_TYPE_BLUECHEESE           3057
+#define MACH_TYPE_TEM3X30              3058
+#define MACH_TYPE_HARVEST_DESOTO       3059
+#define MACH_TYPE_MSM8X60_QRDC         3060
+#define MACH_TYPE_SPEAR900             3061
+#define MACH_TYPE_PCONTROL_G20         3062
+#define MACH_TYPE_RDSTOR               3063
+#define MACH_TYPE_USDLOADER            3064
+#define MACH_TYPE_TSOPLOADER           3065
+#define MACH_TYPE_KRONOS               3066
+#define MACH_TYPE_FFCORE               3067
+#define MACH_TYPE_MONE                 3068
+#define MACH_TYPE_UNIT2S               3069
+#define MACH_TYPE_ACER_A5              3070
+#define MACH_TYPE_ETHERPRO_ISP         3071
+#define MACH_TYPE_STRETCHS7000         3072
+#define MACH_TYPE_P87_SMARTSIM         3073
+#define MACH_TYPE_TULIP                3074
+#define MACH_TYPE_SUNFLOWER            3075
+#define MACH_TYPE_RIB                  3076
+#define MACH_TYPE_CLOD                 3077
+#define MACH_TYPE_RUMP                 3078
+#define MACH_TYPE_TENDERLOIN           3079
+#define MACH_TYPE_SHORTLOIN            3080
+#define MACH_TYPE_ANTARES              3082
+#define MACH_TYPE_WB40N                3083
+#define MACH_TYPE_HERRING              3084
+#define MACH_TYPE_NAXY400              3085
+#define MACH_TYPE_NAXY1200             3086
+#define MACH_TYPE_VPR200               3087
+#define MACH_TYPE_BUG20                3088
+#define MACH_TYPE_GOFLEXNET            3089
+#define MACH_TYPE_TORBRECK             3090
+#define MACH_TYPE_SAARB_MG1            3091
+#define MACH_TYPE_CALLISTO             3092
+#define MACH_TYPE_MULTHSU              3093
+#define MACH_TYPE_SALUDA               3094
+#define MACH_TYPE_PEMP_OMAP3_APOLLO    3095
+#define MACH_TYPE_VC0718               3096
+#define MACH_TYPE_MVBLX                3097
+#define MACH_TYPE_INHAND_APEIRON       3098
+#define MACH_TYPE_INHAND_FURY          3099
+#define MACH_TYPE_INHAND_SIREN         3100
+#define MACH_TYPE_HDNVP                3101
+#define MACH_TYPE_SOFTWINNER           3102
+#define MACH_TYPE_PRIMA2_EVB           3103
+#define MACH_TYPE_NAS6210              3104
+#define MACH_TYPE_UNISDEV              3105
+#define MACH_TYPE_SBCA11               3106
+#define MACH_TYPE_SAGA                 3107
+#define MACH_TYPE_NS_K330              3108
+#define MACH_TYPE_TANNA                3109
+#define MACH_TYPE_IMATE8502            3110
+#define MACH_TYPE_ASPEN                3111
+#define MACH_TYPE_DAINTREE_CWAC        3112
+#define MACH_TYPE_ZMX25                3113
+#define MACH_TYPE_MAPLE1               3114
+#define MACH_TYPE_QSD8X72_SURF         3115
+#define MACH_TYPE_QSD8X72_FFA          3116
+#define MACH_TYPE_ABILENE              3117
+#define MACH_TYPE_EIGEN_TTR            3118
+#define MACH_TYPE_IOMEGA_IX2_200       3119
+#define MACH_TYPE_CORETEC_VCX7400      3120
+#define MACH_TYPE_SANTIAGO             3121
+#define MACH_TYPE_MX257SOL             3122
+#define MACH_TYPE_STRASBOURG           3123
+#define MACH_TYPE_MSM8X60_FLUID        3124
+#define MACH_TYPE_SMARTQV5             3125
+#define MACH_TYPE_SMARTQV3             3126
+#define MACH_TYPE_SMARTQV7             3127
+#define MACH_TYPE_PAZ00                3128
+#define MACH_TYPE_ACMENETUSFOXG20      3129
+#define MACH_TYPE_FWBD_0404            3131
+#define MACH_TYPE_HDGU                 3132
+#define MACH_TYPE_PYRAMID              3133
+#define MACH_TYPE_EPIPHAN              3134
+#define MACH_TYPE_OMAP_BENDER          3135
+#define MACH_TYPE_GURNARD              3136
+#define MACH_TYPE_GTL_IT5100           3137
+#define MACH_TYPE_BCM2708              3138
+#define MACH_TYPE_MX51_GGC             3139
+#define MACH_TYPE_SHARESPACE           3140
+#define MACH_TYPE_HABA_KNX_EXPLORER    3141
+#define MACH_TYPE_SIMTEC_KIRKMOD       3142
+#define MACH_TYPE_CRUX                 3143
+#define MACH_TYPE_MX51_BRAVO           3144
+#define MACH_TYPE_CHARON               3145
+#define MACH_TYPE_PICOCOM3             3146
+#define MACH_TYPE_PICOCOM4             3147
+#define MACH_TYPE_SERRANO              3148
+#define MACH_TYPE_DOUBLESHOT           3149
+#define MACH_TYPE_EVSY                 3150
+#define MACH_TYPE_HUASHAN              3151
+#define MACH_TYPE_LAUSANNE             3152
+#define MACH_TYPE_EMERALD              3153
+#define MACH_TYPE_TQMA35               3154
+#define MACH_TYPE_MARVEL               3155
+#define MACH_TYPE_MANUAE               3156
+#define MACH_TYPE_CHACHA               3157
+#define MACH_TYPE_LEMON                3158
+#define MACH_TYPE_CSC                  3159
+#define MACH_TYPE_GIRA_KNXIP_ROUTER    3160
+#define MACH_TYPE_T20                  3161
+#define MACH_TYPE_HDMINI               3162
+#define MACH_TYPE_SCIPHONE_G2          3163
+#define MACH_TYPE_EXPRESS              3164
+#define MACH_TYPE_EXPRESS_KT           3165
+#define MACH_TYPE_MAXIMASP             3166
+#define MACH_TYPE_NITROGEN_IMX51       3167
+#define MACH_TYPE_NITROGEN_IMX53       3168
+#define MACH_TYPE_SUNFIRE              3169
+#define MACH_TYPE_AROWANA              3170
+#define MACH_TYPE_TEGRA_DAYTONA        3171
+#define MACH_TYPE_TEGRA_SWORDFISH      3172
+#define MACH_TYPE_EDISON               3173
+#define MACH_TYPE_SVP8500V1            3174
+#define MACH_TYPE_SVP8500V2            3175
+#define MACH_TYPE_SVP5500              3176
+#define MACH_TYPE_B5500                3177
+#define MACH_TYPE_S5500                3178
+#define MACH_TYPE_ICON                 3179
+#define MACH_TYPE_ELEPHANT             3180
+#define MACH_TYPE_SHOOTER              3182
+#define MACH_TYPE_SPADE_LTE            3183
+#define MACH_TYPE_PHILHWANI            3184
+#define MACH_TYPE_GSNCOMM              3185
+#define MACH_TYPE_STRASBOURG_A2        3186
+#define MACH_TYPE_MMM                  3187
+#define MACH_TYPE_DAVINCI_DM365_BV     3188
+#define MACH_TYPE_AG5EVM               3189
+#define MACH_TYPE_SC575PLC             3190
+#define MACH_TYPE_SC575IPC             3191
+#define MACH_TYPE_OMAP3_TDM3730        3192
+#define MACH_TYPE_TOP9000_EVAL         3194
+#define MACH_TYPE_TOP9000_SU           3195
+#define MACH_TYPE_UTM300               3196
+#define MACH_TYPE_TSUNAGI              3197
+#define MACH_TYPE_TS75XX               3198
+#define MACH_TYPE_TS47XX               3200
+#define MACH_TYPE_DA850_K5             3201
+#define MACH_TYPE_AX502                3202
+#define MACH_TYPE_IGEP0032             3203
+#define MACH_TYPE_ANTERO               3204
+#define MACH_TYPE_SYNERGY              3205
+#define MACH_TYPE_ICS_IF_VOIP          3206
+#define MACH_TYPE_WLF_CRAGG_6410       3207
+#define MACH_TYPE_PUNICA               3208
+#define MACH_TYPE_TRIMSLICE            3209
+#define MACH_TYPE_MX27_WMULTRA         3210
+#define MACH_TYPE_MACKEREL             3211
+#define MACH_TYPE_FA9X27               3213
+#define MACH_TYPE_NS2816TB             3214
+#define MACH_TYPE_NS2816_NTPAD         3215
+#define MACH_TYPE_NS2816_NTNB          3216
+#define MACH_TYPE_KAEN                 3217
+#define MACH_TYPE_NV1000               3218
+#define MACH_TYPE_NUC950TS             3219
+#define MACH_TYPE_NOKIA_RM680          3220
+#define MACH_TYPE_AST2200              3221
+#define MACH_TYPE_LEAD                 3222
+#define MACH_TYPE_UNINO1               3223
+#define MACH_TYPE_GREECO               3224
+#define MACH_TYPE_VERDI                3225
+#define MACH_TYPE_DM6446_ADBOX         3226
+#define MACH_TYPE_QUAD_SALSA           3227
+#define MACH_TYPE_ABB_GMA_1_1          3228
+#define MACH_TYPE_SVCID                3229
+#define MACH_TYPE_MSM8960_SIM          3230
+#define MACH_TYPE_MSM8960_RUMI3        3231
+#define MACH_TYPE_ICON_G               3232
+#define MACH_TYPE_MB3                  3233
+#define MACH_TYPE_GSIA18S              3234
+#define MACH_TYPE_PIVICC               3235
+#define MACH_TYPE_PCM048               3236
+#define MACH_TYPE_DDS                  3237
+#define MACH_TYPE_CHALTEN_XA1          3238
+#define MACH_TYPE_TS48XX               3239
+#define MACH_TYPE_TONGA2_TFTTIMER      3240
+#define MACH_TYPE_WHISTLER             3241
+#define MACH_TYPE_ASL_PHOENIX          3242
+#define MACH_TYPE_AT91SAM9263OTLITE    3243
+#define MACH_TYPE_DDPLUG               3244
+#define MACH_TYPE_D2PLUG               3245
+#define MACH_TYPE_KZM9D                3246
+#define MACH_TYPE_VERDI_LTE            3247
+#define MACH_TYPE_NANOZOOM             3248
+#define MACH_TYPE_DM3730_SOM_LV        3249
+#define MACH_TYPE_DM3730_TORPEDO       3250
+#define MACH_TYPE_ANCHOVY              3251
+#define MACH_TYPE_RE2REV20             3253
+#define MACH_TYPE_RE2REV21             3254
+#define MACH_TYPE_CNS21XX              3255
+#define MACH_TYPE_RIDER                3257
+#define MACH_TYPE_NSK330               3258
+#define MACH_TYPE_CNS2133EVB           3259
+#define MACH_TYPE_Z3_816X_MOD          3260
+#define MACH_TYPE_Z3_814X_MOD          3261
+#define MACH_TYPE_BEECT                3262
+#define MACH_TYPE_DMA_THUNDERBUG       3263
+#define MACH_TYPE_OMN_AT91SAM9G20      3264
+#define MACH_TYPE_MX25_E2S_UC          3265
+#define MACH_TYPE_MIONE                3266
+#define MACH_TYPE_TOP9000_TCU          3267
+#define MACH_TYPE_TOP9000_BSL          3268
+#define MACH_TYPE_KINGDOM              3269
+#define MACH_TYPE_ARMADILLO460         3270
+#define MACH_TYPE_LQ2                  3271
+#define MACH_TYPE_SWEDA_TMS2           3272
+#define MACH_TYPE_MX53_LOCO            3273
+#define MACH_TYPE_ACER_A8              3275
+#define MACH_TYPE_ACER_GAUGUIN         3276
+#define MACH_TYPE_GUPPY                3277
+#define MACH_TYPE_MX61_ARD             3278
+#define MACH_TYPE_TX53                 3279
+#define MACH_TYPE_OMAPL138_CASE_A3     3280
+#define MACH_TYPE_UEMD                 3281
+#define MACH_TYPE_CCWMX51MUT           3282
+#define MACH_TYPE_ROCKHOPPER           3283
+#define MACH_TYPE_ENCORE               3284
+#define MACH_TYPE_HKDKC100             3285
+#define MACH_TYPE_TS42XX               3286
+#define MACH_TYPE_AEBL                 3287
+#define MACH_TYPE_WARIO                3288
+#define MACH_TYPE_GFS_SPM              3289
+#define MACH_TYPE_CM_T3730             3290
+#define MACH_TYPE_ISC3                 3291
+#define MACH_TYPE_RASCAL               3292
+#define MACH_TYPE_HREFV60              3293
+#define MACH_TYPE_TPT_2_0              3294
+#define MACH_TYPE_PYRAMID_TD           3295
+#define MACH_TYPE_SPLENDOR             3296
+#define MACH_TYPE_GUF_PLANET           3297
+#define MACH_TYPE_MSM8X60_QT           3298
+#define MACH_TYPE_HTC_HD_MINI          3299
+#define MACH_TYPE_ATHENE               3300
+#define MACH_TYPE_DEEP_R_EK_1          3301
+#define MACH_TYPE_VIVOW_CT             3302
+#define MACH_TYPE_NERY_1000            3303
+#define MACH_TYPE_RFL109145_SSRV       3304
+#define MACH_TYPE_NMH                  3305
+#define MACH_TYPE_WN802T               3306
+#define MACH_TYPE_DRAGONET             3307
+#define MACH_TYPE_GENEVA_B             3308
+#define MACH_TYPE_AT91SAM9263DESK16L   3309
+#define MACH_TYPE_BCMHANA_SV           3310
+#define MACH_TYPE_BCMHANA_TABLET       3311
+#define MACH_TYPE_KOI                  3312
+#define MACH_TYPE_TS4800               3313
+#define MACH_TYPE_TQMA9263             3314
+#define MACH_TYPE_HOLIDAY              3315
+#define MACH_TYPE_DMA6410              3316
+#define MACH_TYPE_PCATS_OVERLAY        3317
+#define MACH_TYPE_HWGW6410             3318
+#define MACH_TYPE_SHENZHOU             3319
+#define MACH_TYPE_CWME9210             3320
+#define MACH_TYPE_CWME9210JS           3321
+#define MACH_TYPE_PGS_SITARA           3322
+#define MACH_TYPE_COLIBRI_TEGRA2       3323
+#define MACH_TYPE_W21                  3324
+#define MACH_TYPE_POLYSAT1             3325
+#define MACH_TYPE_DATAWAY              3326
+#define MACH_TYPE_COBRAL138            3327
+#define MACH_TYPE_ROVERPCS8            3328
+#define MACH_TYPE_MARVELC              3329
+#define MACH_TYPE_NAVEFIHID            3330
+#define MACH_TYPE_DM365_CV100          3331
+#define MACH_TYPE_ABLE                 3332
+#define MACH_TYPE_LEGACY               3333
+#define MACH_TYPE_ICONG                3334
+#define MACH_TYPE_ROVER_G8             3335
+#define MACH_TYPE_T5388P               3336
+#define MACH_TYPE_DINGO                3337
+#define MACH_TYPE_GOFLEXHOME           3338
+#define MACH_TYPE_LANREADYFN511        3340
+#define MACH_TYPE_OMAP3_BAIA           3341
+#define MACH_TYPE_OMAP3SMARTDISPLAY    3342
+#define MACH_TYPE_XILINX               3343
+#define MACH_TYPE_A2F                  3344
+#define MACH_TYPE_SKY25                3345
+#define MACH_TYPE_CCMX53               3346
+#define MACH_TYPE_CCMX53JS             3347
+#define MACH_TYPE_CCWMX53              3348
+#define MACH_TYPE_CCWMX53JS            3349
+#define MACH_TYPE_FRISMS               3350
+#define MACH_TYPE_MSM7X27A_FFA         3351
+#define MACH_TYPE_MSM7X27A_SURF        3352
+#define MACH_TYPE_MSM7X27A_RUMI3       3353
+#define MACH_TYPE_DIMMSAM9G20          3354
+#define MACH_TYPE_DIMM_IMX28           3355
+#define MACH_TYPE_AMK_A4               3356
+#define MACH_TYPE_GNET_SGME            3357
+#define MACH_TYPE_SHOOTER_U            3358
+#define MACH_TYPE_VMX53                3359
+#define MACH_TYPE_RHINO                3360
+#define MACH_TYPE_ARMLEX4210           3361
+#define MACH_TYPE_SWARCOEXTMODEM       3362
+#define MACH_TYPE_SNOWBALL             3363
+#define MACH_TYPE_PCM049               3364
+#define MACH_TYPE_VIGOR                3365
+#define MACH_TYPE_OSLO_AMUNDSEN        3366
+#define MACH_TYPE_GSL_DIAMOND          3367
+#define MACH_TYPE_CV2201               3368
+#define MACH_TYPE_CV2202               3369
+#define MACH_TYPE_CV2203               3370
+#define MACH_TYPE_VIT_IBOX             3371
+#define MACH_TYPE_DM6441_ESP           3372
+#define MACH_TYPE_AT91SAM9X5EK         3373
+#define MACH_TYPE_LIBRA                3374
+#define MACH_TYPE_EASYCRRH             3375
+#define MACH_TYPE_TRIPEL               3376
+#define MACH_TYPE_ENDIAN_MINI          3377
+#define MACH_TYPE_XILINX_EP107         3378
+#define MACH_TYPE_NURI                 3379
+#define MACH_TYPE_JANUS                3380
+#define MACH_TYPE_DDNAS                3381
+#define MACH_TYPE_TAG                  3382
+#define MACH_TYPE_TAGW                 3383
+#define MACH_TYPE_NITROGEN_VM_IMX51    3384
+#define MACH_TYPE_VIPRINET             3385
+#define MACH_TYPE_BOCKW                3386
+#define MACH_TYPE_EVA2000              3387
+#define MACH_TYPE_STEELYARD            3388
+#define MACH_TYPE_LPC2468OEM           3389
+#define MACH_TYPE_MACH_SDH001          3390
+#define MACH_TYPE_LPC2478MICROBLOX     3391
+#define MACH_TYPE_NSSLSBOARD           3392
+#define MACH_TYPE_GENEVA_B5            3393
+#define MACH_TYPE_SPEAR1340            3394
+#define MACH_TYPE_REXMAS               3395
+#define MACH_TYPE_MSM8960_CDP          3396
+#define MACH_TYPE_MSM8960_MDP          3397
+#define MACH_TYPE_MSM8960_FLUID        3398
+#define MACH_TYPE_MSM8960_APQ          3399
+#define MACH_TYPE_HELIOS_V2            3400
+#define MACH_TYPE_MIF10P               3401
+#define MACH_TYPE_IAM28                3402
+#define MACH_TYPE_PICASSO              3403
+#define MACH_TYPE_MR301A               3404
+#define MACH_TYPE_NOTLE                3405
+#define MACH_TYPE_EELX2                3406
+#define MACH_TYPE_MOON                 3407
+#define MACH_TYPE_RUBY                 3408
+#define MACH_TYPE_GOLDENGATE           3409
+#define MACH_TYPE_CTBU_GEN2            3410
+#define MACH_TYPE_KMP_AM17_01          3411
+#define MACH_TYPE_WTPLUG               3412
+#define MACH_TYPE_MX27SU2              3413
+#define MACH_TYPE_NB31                 3414
+#define MACH_TYPE_HJSDU                3415
+#define MACH_TYPE_TD3_REV1             3416
+#define MACH_TYPE_EAG_CI4000           3417
+#define MACH_TYPE_NET5BIG_NAND_V2      3418
+#define MACH_TYPE_CPX2                 3419
+#define MACH_TYPE_NET2BIG_NAND_V2      3420
+#define MACH_TYPE_ECUV5                3421
+#define MACH_TYPE_HSGX6D               3422
+#define MACH_TYPE_DAWAD7               3423
+#define MACH_TYPE_SAM9REPEATER         3424
+#define MACH_TYPE_GT_I5700             3425
+#define MACH_TYPE_CTERA_PLUG_C2        3426
+#define MACH_TYPE_MARVELCT             3427
+#define MACH_TYPE_AG11005              3428
+#define MACH_TYPE_OMAP_BLAZE           3429
+#define MACH_TYPE_VANGOGH              3430
+#define MACH_TYPE_MATRIX505            3431
+#define MACH_TYPE_OCE_NIGMA            3432
+#define MACH_TYPE_T55                  3433
+#define MACH_TYPE_BIO3K                3434
+#define MACH_TYPE_EXPRESSCT            3435
+#define MACH_TYPE_CARDHU               3436
+#define MACH_TYPE_ARUBA                3437
+#define MACH_TYPE_BONAIRE              3438
+#define MACH_TYPE_NUC700EVB            3439
+#define MACH_TYPE_NUC710EVB            3440
+#define MACH_TYPE_NUC740EVB            3441
+#define MACH_TYPE_NUC745EVB            3442
+#define MACH_TYPE_TRANSCEDE            3443
+#define MACH_TYPE_MORA                 3444
+#define MACH_TYPE_NDA_EVM              3445
+#define MACH_TYPE_TIMU                 3446
+#define MACH_TYPE_EXPRESSH             3447
+#define MACH_TYPE_VERIDIS_A300         3448
+#define MACH_TYPE_DM368_LEOPARD        3449
+#define MACH_TYPE_OMAP_MCOP            3450
+#define MACH_TYPE_TRITIP               3451
+#define MACH_TYPE_SM1K                 3452
+#define MACH_TYPE_MONCH                3453
+#define MACH_TYPE_CURACAO              3454
+#define MACH_TYPE_ORIGEN               3455
+#define MACH_TYPE_EPC10                3456
+#define MACH_TYPE_SGH_I740             3457
+#define MACH_TYPE_TUNA                 3458
+#define MACH_TYPE_MX51_TULIP           3459
+#define MACH_TYPE_MX51_ASTER7          3460
+#define MACH_TYPE_ACRO37XBRD           3461
+#define MACH_TYPE_ELKE                 3462
+#define MACH_TYPE_SBC6000X             3463
+#define MACH_TYPE_R1801E               3464
+#define MACH_TYPE_H1600                3465
+#define MACH_TYPE_MINI210              3466
+#define MACH_TYPE_MINI8168             3467
+#define MACH_TYPE_PC7308               3468
+#define MACH_TYPE_GE863                3469
+#define MACH_TYPE_KMM2M01              3470
+#define MACH_TYPE_MX51EREBUS           3471
+#define MACH_TYPE_WM8650REFBOARD       3472
+#define MACH_TYPE_TUXRAIL              3473
+#define MACH_TYPE_ARTHUR               3474
+#define MACH_TYPE_DOORBOY              3475
+#define MACH_TYPE_XARINA               3476
+#define MACH_TYPE_ROVERX7              3477
+#define MACH_TYPE_SDVR                 3478
+#define MACH_TYPE_ACER_MAYA            3479
+#define MACH_TYPE_PICO                 3480
+#define MACH_TYPE_CWMX233              3481
+#define MACH_TYPE_CWAM1808             3482
+#define MACH_TYPE_CWDM365              3483
+#define MACH_TYPE_MX51_MORAY           3484
+#define MACH_TYPE_THALES_CBC           3485
+#define MACH_TYPE_BLUEPOINT            3486
+#define MACH_TYPE_DIR665               3487
+#define MACH_TYPE_ACMEROVER1           3488
+#define MACH_TYPE_SHOOTER_CT           3489
+#define MACH_TYPE_BLISS                3490
+#define MACH_TYPE_BLISSC               3491
+#define MACH_TYPE_THALES_ADC           3492
+#define MACH_TYPE_UBISYS_P9D_EVP       3493
+#define MACH_TYPE_ATDGP318             3494
+#define MACH_TYPE_DMA210U              3495
+#define MACH_TYPE_EM_T3                3496
+#define MACH_TYPE_HTX3250              3497
+#define MACH_TYPE_G50                  3498
+#define MACH_TYPE_ECO5                 3499
+#define MACH_TYPE_WINTERGRASP          3500
+#define MACH_TYPE_PURO                 3501
+#define MACH_TYPE_SHOOTER_K            3502
+#define MACH_TYPE_NSPIRE               3503
+#define MACH_TYPE_MICKXX               3504
+#define MACH_TYPE_LXMB                 3505
+#define MACH_TYPE_TMDXSCBP6616X        3506
+#define MACH_TYPE_ADAM                 3507
+#define MACH_TYPE_B1004                3508
+#define MACH_TYPE_OBOEA                3509
+#define MACH_TYPE_A1015                3510
+#define MACH_TYPE_ROBIN_VBDT30         3511
+#define MACH_TYPE_TEGRA_ENTERPRISE     3512
+#define MACH_TYPE_RFL108200_MK10       3513
+#define MACH_TYPE_RFL108300_MK16       3514
+#define MACH_TYPE_ROVER_V7             3515
+#define MACH_TYPE_MIPHONE              3516
+#define MACH_TYPE_FEMTOBTS             3517
+#define MACH_TYPE_MONOPOLI             3518
+#define MACH_TYPE_BOSS                 3519
+#define MACH_TYPE_DAVINCI_DM368_VTAM   3520
+#define MACH_TYPE_CLCON                3521
+#define MACH_TYPE_NOKIA_RM696          3522
+#define MACH_TYPE_TAHITI               3523
+#define MACH_TYPE_FIGHTER              3524
+#define MACH_TYPE_SGH_I710             3525
+#define MACH_TYPE_INTEGREPROSCB        3526
+#define MACH_TYPE_MONZA                3527
+#define MACH_TYPE_MX6Q_SABREAUTO       3529
+#define MACH_TYPE_GMA01X               3530
+#define MACH_TYPE_SBC51                3531
+#define MACH_TYPE_FIT                  3532
+#define MACH_TYPE_STEELHEAD            3533
+#define MACH_TYPE_PANTHER              3534
+#define MACH_TYPE_MSM8960_LIQUID       3535
+#define MACH_TYPE_LEXIKONCT            3536
+#define MACH_TYPE_NS2816_STB           3537
+#define MACH_TYPE_SEI_MM2_LPC3250      3538
+#define MACH_TYPE_CMIMX53              3539
+#define MACH_TYPE_SANDWICH             3540
+#define MACH_TYPE_CHIEF                3541
+#define MACH_TYPE_POGO_E02             3542
+#define MACH_TYPE_MIKRAP_X168          3543
+#define MACH_TYPE_HTCMOZART            3544
+#define MACH_TYPE_HTCGOLD              3545
+#define MACH_TYPE_MT72XX               3546
+#define MACH_TYPE_MX51_IVY             3547
+#define MACH_TYPE_MX51_LVD             3548
+#define MACH_TYPE_OMAP3_WISER2         3549
+#define MACH_TYPE_DREAMPLUG            3550
+#define MACH_TYPE_COBAS_C_111          3551
+#define MACH_TYPE_COBAS_U_411          3552
+#define MACH_TYPE_HSSD                 3553
+#define MACH_TYPE_IOM35X               3554
+#define MACH_TYPE_PSOM_OMAP            3555
+#define MACH_TYPE_IPHONE_2G            3556
+#define MACH_TYPE_IPHONE_3G            3557
+#define MACH_TYPE_IPOD_TOUCH_1G        3558
+#define MACH_TYPE_PHAROS_TPC           3559
+#define MACH_TYPE_MX53_HYDRA           3560
+#define MACH_TYPE_NS2816_DEV_BOARD     3561
+#define MACH_TYPE_IPHONE_3GS           3562
+#define MACH_TYPE_IPHONE_4             3563
+#define MACH_TYPE_IPOD_TOUCH_4G        3564
+#define MACH_TYPE_DRAGON_E1100         3565
+#define MACH_TYPE_TOPSIDE              3566
+#define MACH_TYPE_IRISIII              3567
+#define MACH_TYPE_DETO_MACARM9         3568
+#define MACH_TYPE_ETI_D1               3569
+#define MACH_TYPE_SOM3530SDK           3570
+#define MACH_TYPE_OC_ENGINE            3571
+#define MACH_TYPE_APQ8064_SIM          3572
+#define MACH_TYPE_ALPS                 3575
+#define MACH_TYPE_TNY_T3730            3576
+#define MACH_TYPE_GERYON_NFE           3577
+#define MACH_TYPE_NS2816_REF_BOARD     3578
+#define MACH_TYPE_SILVERSTONE          3579
+#define MACH_TYPE_MTT2440              3580
+#define MACH_TYPE_YNICDB               3581
+#define MACH_TYPE_BCT                  3582
+#define MACH_TYPE_TUSCAN               3583
+#define MACH_TYPE_XBT_SAM9G45          3584
+#define MACH_TYPE_ENBW_CMC             3585
+#define MACH_TYPE_APQ8060_DRAGON       3586
+#define MACH_TYPE_CH104MX257           3587
+#define MACH_TYPE_OPENPRI              3588
+#define MACH_TYPE_AM335XEVM            3589
+#define MACH_TYPE_PICODMB              3590
+#define MACH_TYPE_WALUIGI              3591
+#define MACH_TYPE_PUNICAG7             3592
+#define MACH_TYPE_IPAD_1G              3593
+#define MACH_TYPE_APPLETV_2G           3594
+#define MACH_TYPE_MACH_ECOG45          3595
+#define MACH_TYPE_AIT_CAM_ENC_4XX      3596
+#define MACH_TYPE_RUNNYMEDE            3597
+#define MACH_TYPE_PLAY                 3598
+#define MACH_TYPE_HW90260              3599
+#define MACH_TYPE_TAGH                 3600
+#define MACH_TYPE_FILBERT              3601
+#define MACH_TYPE_GETINGE_NETCOMV3     3602
+#define MACH_TYPE_CW20                 3603
+#define MACH_TYPE_CINEMA               3604
+#define MACH_TYPE_CINEMA_TEA           3605
+#define MACH_TYPE_CINEMA_COFFEE        3606
+#define MACH_TYPE_CINEMA_JUICE         3607
+#define MACH_TYPE_THEPAD               3608
+#define MACH_TYPE_MX53_MIRAGE2         3609
+#define MACH_TYPE_MX53_EFIKASB         3610
+#define MACH_TYPE_STM_B2000            3612
+#define MACH_TYPE_M28EVK               3613
+#define MACH_TYPE_PDA                  3614
+#define MACH_TYPE_MERAKI_MR58          3615
+#define MACH_TYPE_KOTA2                3616
+#define MACH_TYPE_LETCOOL              3617
+#define MACH_TYPE_MX27IAT              3618
+#define MACH_TYPE_APOLLO_TD            3619
+#define MACH_TYPE_ARENA                3620
+#define MACH_TYPE_GSNGATEWAY           3621
+#define MACH_TYPE_LF2000               3622
+#define MACH_TYPE_BONITO               3623
+#define MACH_TYPE_ASYMPTOTE            3624
+#define MACH_TYPE_BST2BRD              3625
+#define MACH_TYPE_TX335S               3626
+#define MACH_TYPE_PELCO_TESLA          3627
+#define MACH_TYPE_RRHTESTPLAT          3628
+#define MACH_TYPE_VIDTONIC_PRO         3629
+#define MACH_TYPE_PL_APOLLO            3630
+#define MACH_TYPE_PL_PHOENIX           3631
+#define MACH_TYPE_M28CU3               3632
+#define MACH_TYPE_VVBOX_HD             3633
+#define MACH_TYPE_COREWARE_SAM9260_    3634
+#define MACH_TYPE_MARMADUKE            3635
+#define MACH_TYPE_AMG_XLCORE_CAMERA    3636
+#define MACH_TYPE_OMAP3_EGF            3637
+#define MACH_TYPE_SMDK4212             3638
+#define MACH_TYPE_DNP9200              3639
+#define MACH_TYPE_TF101                3640
+#define MACH_TYPE_OMAP3SILVIO          3641
+#define MACH_TYPE_PICASSO2             3642
+#define MACH_TYPE_VANGOGH2             3643
+#define MACH_TYPE_OLPC_XO_1_75         3644
+#define MACH_TYPE_GX400                3645
+#define MACH_TYPE_GS300                3646
+#define MACH_TYPE_ACER_A9              3647
+#define MACH_TYPE_VIVOW_EVM            3648
+#define MACH_TYPE_VELOCE_CXQ           3649
+#define MACH_TYPE_VELOCE_CXM           3650
+#define MACH_TYPE_P1852                3651
+#define MACH_TYPE_NAXY100              3652
+#define MACH_TYPE_TAISHAN              3653
+#define MACH_TYPE_TOUCHLINK            3654
+#define MACH_TYPE_STM32F103ZE          3655
+#define MACH_TYPE_STM_NMHDK_FLI7610    3657
+#define MACH_TYPE_TOP28X               3658
+#define MACH_TYPE_OKL4VP_MICROVISOR    3659
+#define MACH_TYPE_POP                  3660
+#define MACH_TYPE_LAYER                3661
+#define MACH_TYPE_TRONDHEIM            3662
+#define MACH_TYPE_EVA                  3663
+#define MACH_TYPE_TRUST_TAURUS         3664
+#define MACH_TYPE_NS2816_HUASHAN       3665
+#define MACH_TYPE_NS2816_YANGCHENG     3666
+#define MACH_TYPE_P852                 3667
+#define MACH_TYPE_FLEA3                3668
+#define MACH_TYPE_BOWFIN               3669
+#define MACH_TYPE_MV88DE3100           3670
+#define MACH_TYPE_PIA_AM35X            3671
+#define MACH_TYPE_CEDAR                3672
+#define MACH_TYPE_PICASSO_E            3673
+#define MACH_TYPE_SAMSUNG_E60          3674
+#define MACH_TYPE_MDM9615              3675
+#define MACH_TYPE_SDVR_MINI            3676
+#define MACH_TYPE_OMAP3_IJ3K           3677
+#define MACH_TYPE_MODASMC1             3678
+#define MACH_TYPE_APQ8064_RUMI3        3679
+#define MACH_TYPE_MATRIX506            3680
+#define MACH_TYPE_MSM9615_MTP          3681
+#define MACH_TYPE_DM36X_SPAWNDC        3682
+#define MACH_TYPE_SFF792               3683
+#define MACH_TYPE_AM335XIAEVM          3684
+#define MACH_TYPE_G3C2440              3685
+#define MACH_TYPE_TION270              3686
+#define MACH_TYPE_W22Q7ARM02           3687
+#define MACH_TYPE_OMAP_CAT             3688
+#define MACH_TYPE_AT91SAM9N12EK        3689
+#define MACH_TYPE_MORRISON             3690
+#define MACH_TYPE_SVDU                 3691
+#define MACH_TYPE_LPP01                3692
+#define MACH_TYPE_UBC283               3693
+#define MACH_TYPE_ZEPPELIN             3694
+#define MACH_TYPE_MOTUS                3695
+#define MACH_TYPE_NEOMAINBOARD         3696
+#define MACH_TYPE_DEVKIT3250           3697
+#define MACH_TYPE_DEVKIT7000           3698
+#define MACH_TYPE_FMC_UIC              3699
+#define MACH_TYPE_FMC_DCM              3700
+#define MACH_TYPE_BATWM                3701
+#define MACH_TYPE_ATLAS6CB             3702
+#define MACH_TYPE_QUATTROF             3703
+#define MACH_TYPE_QUATTROU             3704
+#define MACH_TYPE_BLUE                 3705
+#define MACH_TYPE_COLORADO             3706
+#define MACH_TYPE_POPC                 3707
+#define MACH_TYPE_PROMWAD_JADE         3708
+#define MACH_TYPE_AMP                  3709
+#define MACH_TYPE_GNET_AMP             3710
+#define MACH_TYPE_TOQUES               3711
+#define MACH_TYPE_APX4DEVKIT           3712
+#define MACH_TYPE_DCT_STORM            3713
+#define MACH_TYPE_Z3                   3714
+#define MACH_TYPE_OWL                  3715
+#define MACH_TYPE_COGENT_CSB1741       3716
+#define MACH_TYPE_OMAP3                3717
+#define MACH_TYPE_ADILLUSTRA610        3718
+#define MACH_TYPE_ECAFE_NA04           3719
+#define MACH_TYPE_POPCT                3720
+#define MACH_TYPE_OMAP3_HELENA         3721
+#define MACH_TYPE_ACH                  3722
+#define MACH_TYPE_MODULE_DTB           3723
+#define MACH_TYPE_RACKBOX              3724
+#define MACH_TYPE_OSLO_ELISABETH       3725
+#define MACH_TYPE_TT01                 3726
+#define MACH_TYPE_MSM8930_CDP          3727
+#define MACH_TYPE_MSM8930_MTP          3728
+#define MACH_TYPE_MSM8930_FLUID        3729
+#define MACH_TYPE_LTU11                3730
+#define MACH_TYPE_AM1808_SPAWNCO       3731
+#define MACH_TYPE_FLX6410              3732
+#define MACH_TYPE_MX6Q_QSB             3733
+#define MACH_TYPE_MX53_PLT424          3734
+#define MACH_TYPE_JASMINE              3735
+#define MACH_TYPE_L138_OWLBOARD_PLUS   3736
+#define MACH_TYPE_WR21                 3737
+#define MACH_TYPE_PEABOY               3739
+#define MACH_TYPE_MX28_PLATO           3740
+#define MACH_TYPE_KACOM2               3741
+#define MACH_TYPE_SLCO                 3742
+#define MACH_TYPE_IMX51PICO            3743
+#define MACH_TYPE_GLINK1               3744
+#define MACH_TYPE_DIAMOND              3745
+#define MACH_TYPE_D9000                3746
+#define MACH_TYPE_W5300E01             3747
+#define MACH_TYPE_IM6000               3748
+#define MACH_TYPE_MX51_FRED51          3749
+#define MACH_TYPE_STM32F2              3750
+#define MACH_TYPE_VILLE                3751
+#define MACH_TYPE_PTIP_MURNAU          3752
+#define MACH_TYPE_PTIP_CLASSIC         3753
+#define MACH_TYPE_MX53GRB              3754
+#define MACH_TYPE_GAGARIN              3755
+#define MACH_TYPE_MSM7X27A_QRD1        3756
+#define MACH_TYPE_NAS2BIG              3757
+#define MACH_TYPE_SUPERFEMTO           3758
+#define MACH_TYPE_TEUFEL               3759
+#define MACH_TYPE_DINARA               3760
+#define MACH_TYPE_VANQUISH             3761
+#define MACH_TYPE_ZIPABOX1             3762
+#define MACH_TYPE_U9540                3763
+#define MACH_TYPE_JET                  3764
+#define MACH_TYPE_SMDK4412             3765
+#define MACH_TYPE_ELITE                3766
+#define MACH_TYPE_SPEAR320_HMI         3767
+#define MACH_TYPE_ONTARIO              3768
+#define MACH_TYPE_MX6Q_SABRELITE       3769
+#define MACH_TYPE_VC200                3770
+#define MACH_TYPE_MSM7625A_FFA         3771
+#define MACH_TYPE_MSM7625A_SURF        3772
+#define MACH_TYPE_BENTHOSSBP           3773
+#define MACH_TYPE_SMDK5210             3774
+#define MACH_TYPE_EMPQ2300             3775
+#define MACH_TYPE_MINIPOS              3776
+#define MACH_TYPE_OMAP5_SEVM           3777
+#define MACH_TYPE_SHELTER              3778
+#define MACH_TYPE_OMAP3_DEVKIT8500     3779
+#define MACH_TYPE_EDGETD               3780
+#define MACH_TYPE_COPPERYARD           3781
+#define MACH_TYPE_EDGE                 3782
+#define MACH_TYPE_EDGE_U               3783
+#define MACH_TYPE_EDGE_TD              3784
+#define MACH_TYPE_WDSS                 3785
+#define MACH_TYPE_DL_PB25              3786
+#define MACH_TYPE_DSS11                3787
+#define MACH_TYPE_CPA                  3788
+#define MACH_TYPE_APTP2000             3789
+#define MACH_TYPE_MARZEN               3790
+#define MACH_TYPE_ST_TURBINE           3791
+#define MACH_TYPE_GTL_IT3300           3792
+#define MACH_TYPE_MX6_MULE             3793
+#define MACH_TYPE_V7PXA_DT             3794
+#define MACH_TYPE_V7MMP_DT             3795
+#define MACH_TYPE_DRAGON7              3796
+#define MACH_TYPE_KROME                3797
+#define MACH_TYPE_ORATISDANTE          3798
+#define MACH_TYPE_FATHOM               3799
+#define MACH_TYPE_DNS325               3800
+#define MACH_TYPE_SARNEN               3801
+#define MACH_TYPE_UBISYS_G1            3802
+#define MACH_TYPE_MX53_PF1             3803
+#define MACH_TYPE_ASANTI               3804
+#define MACH_TYPE_VOLTA                3805
+#define MACH_TYPE_S5P6450              3806
+#define MACH_TYPE_KNIGHT               3807
+#define MACH_TYPE_BEAGLEBONE           3808
+#define MACH_TYPE_BECKER               3809
+#define MACH_TYPE_FC360                3810
+#define MACH_TYPE_PMI2_XLS             3811
+#define MACH_TYPE_TARANTO              3812
+#define MACH_TYPE_PLUTUX               3813
+#define MACH_TYPE_IPMP_MEDCOM          3814
+#define MACH_TYPE_ABSOLUT              3815
+#define MACH_TYPE_AWPB3                3816
+#define MACH_TYPE_NFP32XX_DT           3817
+#define MACH_TYPE_DL_PB53              3818
+#define MACH_TYPE_ACU_II               3819
+#define MACH_TYPE_AVALON               3820
+#define MACH_TYPE_SPHINX               3821
+#define MACH_TYPE_TITAN_T              3822
+#define MACH_TYPE_HARVEST_BORIS        3823
+#define MACH_TYPE_MACH_MSM7X30_M3S     3824
+#define MACH_TYPE_SMDK5250             3825
+#define MACH_TYPE_IMXT_LITE            3826
+#define MACH_TYPE_IMXT_STD             3827
+#define MACH_TYPE_IMXT_LOG             3828
+#define MACH_TYPE_IMXT_NAV             3829
+#define MACH_TYPE_IMXT_FULL            3830
+#define MACH_TYPE_AG09015              3831
+#define MACH_TYPE_DP1ARM9              3833
+#define MACH_TYPE_PICASSO_M            3834
+#define MACH_TYPE_VIDEO_GADGET         3835
+#define MACH_TYPE_MTT_OM3X             3836
+#define MACH_TYPE_MX6Q_ARM2            3837
+#define MACH_TYPE_PICOSAM9G45          3838
+#define MACH_TYPE_VPM_DM365            3839
+#define MACH_TYPE_BONFIRE              3840
+#define MACH_TYPE_MT2P2D               3841
+#define MACH_TYPE_SIGPDA01             3842
+#define MACH_TYPE_CN27                 3843
+#define MACH_TYPE_MX25_CWTAP           3844
+#define MACH_TYPE_APF28                3845
+#define MACH_TYPE_PELCO_MAXWELL        3846
+#define MACH_TYPE_GE_PHOENIX           3847
+#define MACH_TYPE_EMPC_A500            3848
+#define MACH_TYPE_IMS_ARM9             3849
+#define MACH_TYPE_MINI2416             3850
+#define MACH_TYPE_MINI2450             3851
+#define MACH_TYPE_MINI310              3852
+#define MACH_TYPE_SPEAR_HURRICANE      3853
+#define MACH_TYPE_MT7208               3854
+#define MACH_TYPE_LPC178X              3855
+#define MACH_TYPE_FARLEYS              3856
+#define MACH_TYPE_EFM32GG_DK3750       3857
+#define MACH_TYPE_ZEUS_BOARD           3858
+#define MACH_TYPE_CC51                 3859
+#define MACH_TYPE_FXI_C210             3860
+#define MACH_TYPE_MSM8627_CDP          3861
+#define MACH_TYPE_MSM8627_MTP          3862
+#define MACH_TYPE_ARMADILLO800EVA      3863
+#define MACH_TYPE_PRIMOU               3864
+#define MACH_TYPE_PRIMOC               3865
+#define MACH_TYPE_PRIMOCT              3866
+#define MACH_TYPE_A9500                3867
+#define MACH_TYPE_PULSE_TD             3868
+#define MACH_TYPE_PLUTO                3869
+#define MACH_TYPE_ACFX100              3870
+#define MACH_TYPE_MSM8625_RUMI3        3871
+#define MACH_TYPE_VALENTE              3872
+#define MACH_TYPE_CRFS_RFEYE           3873
+#define MACH_TYPE_RFEYE                3874
+#define MACH_TYPE_PHIDGET_SBC3         3875
+#define MACH_TYPE_TCW_MIKA             3876
+#define MACH_TYPE_IMX28_EGF            3877
+#define MACH_TYPE_VALENTE_WX           3878
+#define MACH_TYPE_HUANGSHANS           3879
+#define MACH_TYPE_BOSPHORUS1           3880
+#define MACH_TYPE_PRIMA                3881
+#define MACH_TYPE_M3_SKT               3882
+#define MACH_TYPE_M3_REF               3883
+#define MACH_TYPE_EVITA_ULK            3884
+#define MACH_TYPE_MERISC600            3885
+#define MACH_TYPE_DOLAK                3886
+#define MACH_TYPE_SBC53                3887
+#define MACH_TYPE_ELITE_ULK            3888
+#define MACH_TYPE_POV2                 3889
+#define MACH_TYPE_IPOD_TOUCH_2G        3890
+#define MACH_TYPE_DA850_PQAB           3891
+#define MACH_TYPE_FERMI                3892
+#define MACH_TYPE_CCARDWMX28           3893
+#define MACH_TYPE_CCARDMX28            3894
+#define MACH_TYPE_FS20_FCM2050         3895
+#define MACH_TYPE_KINETIS              3896
+#define MACH_TYPE_KAI                  3897
+#define MACH_TYPE_BCTHB2               3898
+#define MACH_TYPE_INELS3_CU            3899
+#define MACH_TYPE_JUNIPER              3900
+#define MACH_TYPE_DA850_APOLLO         3901
+#define MACH_TYPE_TRACNAS              3902
+#define MACH_TYPE_MITYARM335X          3903
+#define MACH_TYPE_XCGZ7X               3904
+#define MACH_TYPE_CUBOX                3905
+#define MACH_TYPE_TERMINATOR           3906
+#define MACH_TYPE_EYE03                3907
+#define MACH_TYPE_KOTA3                3908
+#define MACH_TYPE_MX5                  3909
+#define MACH_TYPE_PSCPE                3910
+#define MACH_TYPE_AKT1100              3911
+#define MACH_TYPE_PCAAXL2              3912
+#define MACH_TYPE_PRIMODD_CT           3913
+#define MACH_TYPE_NSBC                 3914
+#define MACH_TYPE_MESON2_SKT           3915
+#define MACH_TYPE_MESON2_REF           3916
+#define MACH_TYPE_CCARDWMX28JS         3917
+#define MACH_TYPE_CCARDMX28JS          3918
+#define MACH_TYPE_INDICO               3919
+#define MACH_TYPE_MSM8960DT            3920
+#define MACH_TYPE_PRIMODS              3921
+#define MACH_TYPE_BELUGA_M1388         3922
+#define MACH_TYPE_PRIMOTD              3923
+#define MACH_TYPE_VARAN_MASTER         3924
+#define MACH_TYPE_PRIMODD              3925
+#define MACH_TYPE_JETDUO               3926
+#define MACH_TYPE_MX53_UMOBO           3927
+#define MACH_TYPE_TRATS                3928
+#define MACH_TYPE_STARCRAFT            3929
+#define MACH_TYPE_QSEVEN_TEGRA2        3930
+#define MACH_TYPE_LICHEE_SUN4I_DEVBD   3931
+#define MACH_TYPE_MOVENOW              3932
+#define MACH_TYPE_GOLF_U               3933
+#define MACH_TYPE_MSM7627A_EVB         3934
+#define MACH_TYPE_RAMBO                3935
+#define MACH_TYPE_GOLFU                3936
+#define MACH_TYPE_MANGO310             3937
+#define MACH_TYPE_DNS343               3938
+#define MACH_TYPE_VAR_SOM_OM44         3939
+#define MACH_TYPE_NAON                 3940
+#define MACH_TYPE_VP4000               3941
+#define MACH_TYPE_IMPCARD              3942
+#define MACH_TYPE_SMOOVCAM             3943
+#define MACH_TYPE_COBHAM3725           3944
+#define MACH_TYPE_COBHAM3730           3945
+#define MACH_TYPE_COBHAM3703           3946
+#define MACH_TYPE_QUETZAL              3947
+#define MACH_TYPE_APQ8064_CDP          3948
+#define MACH_TYPE_APQ8064_MTP          3949
+#define MACH_TYPE_APQ8064_FLUID        3950
+#define MACH_TYPE_APQ8064_LIQUID       3951
+#define MACH_TYPE_MANGO210             3952
+#define MACH_TYPE_MANGO100             3953
+#define MACH_TYPE_MANGO24              3954
+#define MACH_TYPE_MANGO64              3955
+#define MACH_TYPE_NSA320               3956
+#define MACH_TYPE_ELV_CCU2             3957
+#define MACH_TYPE_TRITON_X00           3958
+#define MACH_TYPE_TRITON_1500_2000     3959
+#define MACH_TYPE_POGOPLUGV4           3960
+#define MACH_TYPE_VENUS_CL             3961
+#define MACH_TYPE_VULCANO_G20          3962
+#define MACH_TYPE_SGS_I9100            3963
+#define MACH_TYPE_STSV2                3964
+#define MACH_TYPE_CSB1724              3965
+#define MACH_TYPE_OMAPL138_LCDK        3966
+#define MACH_TYPE_JEWEL_DD             3967
+#define MACH_TYPE_PVD_MX25             3968
+#define MACH_TYPE_MESON6_SKT           3969
+#define MACH_TYPE_MESON6_REF           3970
+#define MACH_TYPE_PXM                  3971
+#define MACH_TYPE_S3                   3972
+#define MACH_TYPE_POGOPLUGV3           3973
+#define MACH_TYPE_MLP89626             3974
+#define MACH_TYPE_IOMEGAHMNDCE         3975
+#define MACH_TYPE_POGOPLUGV3PCI        3976
+#define MACH_TYPE_BNTV250              3977
+#define MACH_TYPE_MX53_QSEVEN          3978
+#define MACH_TYPE_GTL_IT1100           3979
+#define MACH_TYPE_MX6Q_SABRESD         3980
+#define MACH_TYPE_MT4                  3981
+#define MACH_TYPE_JUMBO_D              3982
+#define MACH_TYPE_JUMBO_I              3983
+#define MACH_TYPE_FS20_DMP             3984
+#define MACH_TYPE_DNS320               3985
+#define MACH_TYPE_MX28BACOS            3986
+#define MACH_TYPE_TL80                 3987
+#define MACH_TYPE_POLATIS_NIC_1001     3988
+#define MACH_TYPE_TELY                 3989
+#define MACH_TYPE_U8520                3990
+#define MACH_TYPE_MANTA                3991
+#define MACH_TYPE_SPEAR_EM_S900        3992
+#define MACH_TYPE_MPQ8064_CDP          3993
+#define MACH_TYPE_MPQ8064_STB          3994
+#define MACH_TYPE_MPQ8064_DTV          3995
+#define MACH_TYPE_DM368SOM             3996
+#define MACH_TYPE_GPRISB2              3997
+#define MACH_TYPE_CHAMMID              3998
+#define MACH_TYPE_SEOUL2               3999
+#define MACH_TYPE_OMAP4_NOOKTABLET     4000
+#define MACH_TYPE_AALTO                4001
+#define MACH_TYPE_METRO                4002
+#define MACH_TYPE_CYDM3730             4003
+#define MACH_TYPE_TQMA53               4004
+#define MACH_TYPE_MSM7627A_QRD3        4005
+#define MACH_TYPE_MX28_CANBY           4006
+#define MACH_TYPE_TIGER                4007
+#define MACH_TYPE_PCATS_9307_TYPE_A    4008
+#define MACH_TYPE_PCATS_9307_TYPE_O    4009
+#define MACH_TYPE_PCATS_9307_TYPE_R    4010
+#define MACH_TYPE_STREAMPLUG           4011
+#define MACH_TYPE_ICECHICKEN_DEV       4012
+#define MACH_TYPE_HEDGEHOG             4013
+#define MACH_TYPE_YUSEND_OBC           4014
+#define MACH_TYPE_IMXNINJA             4015
+#define MACH_TYPE_OMAP4_JAROD          4016
+#define MACH_TYPE_ECO5_PK              4017
+#define MACH_TYPE_QJ2440               4018
+#define MACH_TYPE_MX6Q_MERCURY         4019
+#define MACH_TYPE_CM6810               4020
+#define MACH_TYPE_OMAP4_TORPEDO        4021
+#define MACH_TYPE_NSA310               4022
+#define MACH_TYPE_TMX536               4023
+#define MACH_TYPE_KTT20                4024
+#define MACH_TYPE_DRAGONIX             4025
+#define MACH_TYPE_LUNGCHING            4026
+#define MACH_TYPE_BULOGICS             4027
+#define MACH_TYPE_MX535_SX             4028
+#define MACH_TYPE_NGUI3250             4029
+#define MACH_TYPE_SALUTEC_DAC          4030
+#define MACH_TYPE_LOCO                 4031
+#define MACH_TYPE_CTERA_PLUG_USI       4032
+#define MACH_TYPE_SCEPTER              4033
+#define MACH_TYPE_SGA                  4034
+#define MACH_TYPE_P_81_J5              4035
+#define MACH_TYPE_P_81_O4              4036
+#define MACH_TYPE_MSM8625_SURF         4037
+#define MACH_TYPE_CARALLON_SHARK       4038
+#define MACH_TYPE_LSGCICAM             4039
+#define MACH_TYPE_ORDOG                4040
+#define MACH_TYPE_PUENTE_IO            4041
+#define MACH_TYPE_MSM8625_EVB          4042
+#define MACH_TYPE_EV_AM1707            4043
+#define MACH_TYPE_EV_AM1707E2          4044
+#define MACH_TYPE_EV_AM3517E2          4045
+#define MACH_TYPE_CALABRIA             4046
+#define MACH_TYPE_EV_IMX287            4047
+#define MACH_TYPE_ERAU                 4048
+#define MACH_TYPE_SICHUAN              4049
+#define MACH_TYPE_WIRMA3               4050
+#define MACH_TYPE_DAVINCI_DA850        4051
+#define MACH_TYPE_OMAP138_TRUNARC      4052
+#define MACH_TYPE_BCM4761              4053
+#define MACH_TYPE_PICASSO_E2           4054
+#define MACH_TYPE_PICASSO_MF           4055
+#define MACH_TYPE_MIRO                 4056
+#define MACH_TYPE_AT91SAM9G20EWON3     4057
+#define MACH_TYPE_YOYO                 4058
+#define MACH_TYPE_WINDJKL              4059
+#define MACH_TYPE_MONARUDO             4060
+#define MACH_TYPE_BATAN                4061
+#define MACH_TYPE_TADAO                4062
+#define MACH_TYPE_BASO                 4063
+#define MACH_TYPE_MAHON                4064
+#define MACH_TYPE_VILLEC2              4065
+#define MACH_TYPE_ASI1230              4066
+#define MACH_TYPE_ALASKA               4067
+#define MACH_TYPE_SWARCO_SHDSL2        4068
+#define MACH_TYPE_OXRTU                4069
+#define MACH_TYPE_OMAP5_PANDA          4070
+#define MACH_TYPE_MX28XDI              4071
+#define MACH_TYPE_C8000                4072
+#define MACH_TYPE_BJE_DISPLAY3_5       4073
+#define MACH_TYPE_PICOMOD7             4074
+#define MACH_TYPE_PICOCOM5             4075
+#define MACH_TYPE_QBLISSA8             4076
+#define MACH_TYPE_ARMSTONEA8           4077
+#define MACH_TYPE_NETDCU14             4078
+#define MACH_TYPE_AT91SAM9X5_EPIPHAN   4079
+#define MACH_TYPE_P2U                  4080
+#define MACH_TYPE_DORIS                4081
+#define MACH_TYPE_J49                  4082
+#define MACH_TYPE_VDSS2E               4083
+#define MACH_TYPE_VC300                4084
+#define MACH_TYPE_NS115_PAD_TEST       4085
+#define MACH_TYPE_NS115_PAD_REF        4086
+#define MACH_TYPE_NS115_PHONE_TEST     4087
+#define MACH_TYPE_NS115_PHONE_REF      4088
+#define MACH_TYPE_GOLFC                4089
+#define MACH_TYPE_XEROX_OLYMPUS        4090
+#define MACH_TYPE_MX6SL_ARM2           4091
+#define MACH_TYPE_CSB1701_CSB1726      4092
+#define MACH_TYPE_AT91SAM9XEEK         4093
+#define MACH_TYPE_EBV210               4094
+#define MACH_TYPE_MSM7627A_QRD7        4095
+#define MACH_TYPE_SVTHIN               4096
+#define MACH_TYPE_DUOVERO              4097
+#define MACH_TYPE_CHUPACABRA           4098
+#define MACH_TYPE_SCORPION             4099
+#define MACH_TYPE_DAVINCI_HE_HMI10     4100
+#define MACH_TYPE_TOPKICK              4101
+#define MACH_TYPE_M3_AUGUESTRUSH       4102
+#define MACH_TYPE_IPC335X              4103
+#define MACH_TYPE_SUN4I                4104
+#define MACH_TYPE_IMX233_OLINUXINO     4105
+#define MACH_TYPE_K2_WL                4106
+#define MACH_TYPE_K2_UL                4107
+#define MACH_TYPE_K2_CL                4108
+#define MACH_TYPE_MINBARI_W            4109
+#define MACH_TYPE_MINBARI_M            4110
+#define MACH_TYPE_K035                 4111
+#define MACH_TYPE_ARIEL                4112
+#define MACH_TYPE_ARIELSAARC           4113
+#define MACH_TYPE_ARIELDKB             4114
+#define MACH_TYPE_ARMADILLO810         4115
+#define MACH_TYPE_TAM335X              4116
+#define MACH_TYPE_GROUPER              4117
+#define MACH_TYPE_MPCSA21_9G20         4118
+#define MACH_TYPE_M6U_CPU              4119
+#define MACH_TYPE_DAVINCI_DP10         4120
+#define MACH_TYPE_GINKGO               4121
+#define MACH_TYPE_CGT_QMX6             4122
+#define MACH_TYPE_PROFPGA              4123
+#define MACH_TYPE_ACFX100OC            4124
+#define MACH_TYPE_ACFX100NB            4125
+#define MACH_TYPE_CAPRICORN            4126
+#define MACH_TYPE_PISCES               4127
+#define MACH_TYPE_ARIES                4128
+#define MACH_TYPE_CANCER               4129
+#define MACH_TYPE_LEO                  4130
+#define MACH_TYPE_VIRGO                4131
+#define MACH_TYPE_SAGITTARIUS          4132
+#define MACH_TYPE_DEVIL                4133
+#define MACH_TYPE_BALLANTINES          4134
+#define MACH_TYPE_OMAP3_PROCERUSVPU    4135
+#define MACH_TYPE_MY27                 4136
+#define MACH_TYPE_SUN6I                4137
+#define MACH_TYPE_SUN5I                4138
+#define MACH_TYPE_MX512_MX             4139
+#define MACH_TYPE_KZM9G                4140
+#define MACH_TYPE_VDSTBN               4141
+#define MACH_TYPE_CFA10036             4142
+#define MACH_TYPE_CFA10049             4143
+#define MACH_TYPE_PCM051               4144
+#define MACH_TYPE_VYBRID_VF7XX         4145
+#define MACH_TYPE_VYBRID_VF6XX         4146
+#define MACH_TYPE_VYBRID_VF5XX         4147
+#define MACH_TYPE_VYBRID_VF4XX         4148
+#define MACH_TYPE_ARIA_G25             4149
+#define MACH_TYPE_BCM21553             4150
+#define MACH_TYPE_SMDK5410             4151
+#define MACH_TYPE_LPC18XX              4152
+#define MACH_TYPE_ORATISPARTY          4153
+#define MACH_TYPE_QSEVEN               4154
+#define MACH_TYPE_GMV_GENERIC          4155
+#define MACH_TYPE_TH_LINK_ETH          4156
+#define MACH_TYPE_TN_MUNINN            4157
+#define MACH_TYPE_RAMPAGE              4158
+#define MACH_TYPE_VISSTRIM_MV10        4159
+#define MACH_TYPE_MONACO_TDU           4160
+#define MACH_TYPE_MONACO_UL            4161
+#define MACH_TYPE_ENRC2_U              4162
+#define MACH_TYPE_EVITA_UL             4163
+#define MACH_TYPE_MX28_WILMA           4164
+#define MACH_TYPE_MONACO_U             4165
+#define MACH_TYPE_MSM8625_FFA          4166
+#define MACH_TYPE_VPU101               4167
+#define MACH_TYPE_OPERA_UL             4168
+#define MACH_TYPE_BAILEYS              4169
+#define MACH_TYPE_FAMILYBOX            4170
+#define MACH_TYPE_ENSEMBLE_MX35        4171
+#define MACH_TYPE_SC_SPS_1             4172
+#define MACH_TYPE_UCSIMPLY_SAM9260     4173
+#define MACH_TYPE_UNICORN              4174
+#define MACH_TYPE_M9G45A               4175
+#define MACH_TYPE_MTWEBIF              4176
+#define MACH_TYPE_PLAYSTONE            4177
+#define MACH_TYPE_CHELSEA              4178
+#define MACH_TYPE_BAYERN               4179
+#define MACH_TYPE_MITWO                4180
+#define MACH_TYPE_MX25_NOAH            4181
+#define MACH_TYPE_STM_B2020            4182
+#define MACH_TYPE_ANNAX_SRC            4183
+#define MACH_TYPE_IONICS_STRATUS       4184
+#define MACH_TYPE_HUGO                 4185
+#define MACH_TYPE_EM300                4186
+#define MACH_TYPE_MMP3_QSEVEN          4187
+#define MACH_TYPE_BOSPHORUS2           4188
+#define MACH_TYPE_TT2200               4189
+#define MACH_TYPE_OCELOT3              4190
+#define MACH_TYPE_TEK_COBRA            4191
+#define MACH_TYPE_PROTOU               4192
+#define MACH_TYPE_MSM8625_EVT          4193
+#define MACH_TYPE_MX53_SELLWOOD        4194
+#define MACH_TYPE_SOMIQ_AM35           4195
+#define MACH_TYPE_SOMIQ_AM37           4196
+#define MACH_TYPE_K2_PLC_CL            4197
+#define MACH_TYPE_TC2                  4198
+#define MACH_TYPE_DULEX_J              4199
+#define MACH_TYPE_STM_B2044            4200
+#define MACH_TYPE_DELUXE_J             4201
+#define MACH_TYPE_MANGO2443            4202
+#define MACH_TYPE_CP2DCG               4203
+#define MACH_TYPE_CP2DTG               4204
+#define MACH_TYPE_CP2DUG               4205
+#define MACH_TYPE_VAR_SOM_AM33         4206
+#define MACH_TYPE_PEPPER               4207
+#define MACH_TYPE_MANGO2450            4208
+#define MACH_TYPE_VALENTE_WX_C9        4209
+#define MACH_TYPE_MINITV               4210
+#define MACH_TYPE_U8540                4211
+#define MACH_TYPE_IV_ATLAS_I_Z7E       4212
+#define MACH_TYPE_COGENT_CSB1733       4213
+#define MACH_TYPE_MACH_TYPE_SKY        4214
+#define MACH_TYPE_BLUESKY              4215
+#define MACH_TYPE_NGROUTER             4216
+#define MACH_TYPE_MX53_DENETIM         4217
+#define MACH_TYPE_OPAL                 4218
+#define MACH_TYPE_GNET_US3GREF         4219
+#define MACH_TYPE_GNET_NC3G            4220
+#define MACH_TYPE_GNET_GE3G            4221
+#define MACH_TYPE_ADP2                 4222
+#define MACH_TYPE_TQMA28               4223
+#define MACH_TYPE_KACOM3               4224
+#define MACH_TYPE_RRHDEMO              4225
+#define MACH_TYPE_PROTODUG             4226
+#define MACH_TYPE_LAGO                 4227
+#define MACH_TYPE_KTT30                4228
+#define MACH_TYPE_TS43XX               4229
+#define MACH_TYPE_MX6Q_DENSO           4230
+#define MACH_TYPE_COMSAT_GSMUMTS8      4231
+#define MACH_TYPE_DREAMX               4232
+#define MACH_TYPE_THUNDERSTONEM        4233
+#define MACH_TYPE_YOYOPAD              4234
+#define MACH_TYPE_YOYOPATIENT          4235
+#define MACH_TYPE_A10L                 4236
+#define MACH_TYPE_MQ60                 4237
+#define MACH_TYPE_LINKSTATION_LSQL     4238
+#define MACH_TYPE_AM3703GATEWAY        4239
+#define MACH_TYPE_ACCIPITER            4240
+#define MACH_TYPE_P1853                4241
+#define MACH_TYPE_MAGNIDUG             4242
+#define MACH_TYPE_HYDRA                4243
+#define MACH_TYPE_SUN3I                4244
+#define MACH_TYPE_STM_B2078            4245
+#define MACH_TYPE_AT91SAM9263DESKV2    4246
+#define MACH_TYPE_DELUXE_R             4247
+#define MACH_TYPE_P_98_V               4248
+#define MACH_TYPE_P_98_C               4249
+#define MACH_TYPE_DAVINCI_AM18XX_OMN   4250
+#define MACH_TYPE_SOCFPGA_CYCLONE5     4251
+#define MACH_TYPE_CABATUIN             4252
+#define MACH_TYPE_YOYOPAD_FT           4253
+#define MACH_TYPE_DAN2400EVB           4254
+#define MACH_TYPE_DAN3400EVB           4255
+#define MACH_TYPE_EDM_SF_IMX6          4256
+#define MACH_TYPE_EDM_CF_IMX6          4257
+#define MACH_TYPE_VPOS3XX              4258
+#define MACH_TYPE_VULCANO_9X5          4259
+#define MACH_TYPE_SPMP8000             4260
+#define MACH_TYPE_CATALINA             4261
+#define MACH_TYPE_RD88F5181L_FE        4262
+#define MACH_TYPE_MX535_MX             4263
+#define MACH_TYPE_ARMADILLO840         4264
+#define MACH_TYPE_SPC9000BASEBOARD     4265
+#define MACH_TYPE_IRIS                 4266
+#define MACH_TYPE_PROTODCG             4267
+#define MACH_TYPE_PALMTREE             4268
+#define MACH_TYPE_NOVENA               4269
+#define MACH_TYPE_MA_UM                4270
+#define MACH_TYPE_MA_AM                4271
+#define MACH_TYPE_EMS348               4272
+#define MACH_TYPE_CM_FX6               4273
+#define MACH_TYPE_ARNDALE              4274
+#define MACH_TYPE_Q5XR5                4275
+#define MACH_TYPE_WILLOW               4276
+#define MACH_TYPE_OMAP3621_ODYV3       4277
+#define MACH_TYPE_OMAPL138_PRESONUS    4278
+#define MACH_TYPE_DVF99                4279
+#define MACH_TYPE_IMPRESSION_J         4280
+#define MACH_TYPE_QBLISSA9             4281
+#define MACH_TYPE_ROBIN_HELIVIEW10     4282
+#define MACH_TYPE_SUN7I                4283
+#define MACH_TYPE_MX6Q_HDMIDONGLE      4284
+#define MACH_TYPE_MX6_SID2             4285
+#define MACH_TYPE_HELIOS_V3            4286
+#define MACH_TYPE_HELIOS_V4            4287
+#define MACH_TYPE_Q7_IMX6              4288
+#define MACH_TYPE_ODROIDX              4289
+#define MACH_TYPE_ROBPRO               4290
+#define MACH_TYPE_RESEARCH59IF_MK1     4291
+#define MACH_TYPE_BOBSLEIGH            4292
+#define MACH_TYPE_DCSHGWT3             4293
+#define MACH_TYPE_GLD1018              4294
+#define MACH_TYPE_EV10                 4295
+#define MACH_TYPE_NITROGEN6X           4296
+#define MACH_TYPE_P_107_BB             4297
+#define MACH_TYPE_EVITA_UTL            4298
+#define MACH_TYPE_FALCONWING           4299
+#define MACH_TYPE_DCT3                 4300
+#define MACH_TYPE_CPX2E_CELL           4301
+#define MACH_TYPE_AMIRO                4302
+#define MACH_TYPE_MX6Q_BRASSBOARD      4303
+#define MACH_TYPE_DALMORE              4304
+#define MACH_TYPE_OMAP3_PORTAL7CP      4305
+#define MACH_TYPE_TEGRA_PLUTO          4306
+#define MACH_TYPE_MX6SL_EVK            4307
+#define MACH_TYPE_M7                   4308
+#define MACH_TYPE_PXM2                 4309
+#define MACH_TYPE_HABA_KNX_LITE        4310
+#define MACH_TYPE_TAI                  4311
+#define MACH_TYPE_PROTOTD              4312
+#define MACH_TYPE_DST_TONTO            4313
+#define MACH_TYPE_DRACO                4314
+#define MACH_TYPE_DXR2                 4315
+#define MACH_TYPE_RUT                  4316
+#define MACH_TYPE_AM180X_WSC           4317
+#define MACH_TYPE_DELUXE_U             4318
+#define MACH_TYPE_DELUXE_UL            4319
+#define MACH_TYPE_AT91SAM9260MEDTHS    4320
+#define MACH_TYPE_MATRIX516            4321
+#define MACH_TYPE_VID401X              4322
+#define MACH_TYPE_HELIOS_V5            4323
+#define MACH_TYPE_PLAYPAQ2             4324
+#define MACH_TYPE_IGAM                 4325
+#define MACH_TYPE_AMICO_I              4326
+#define MACH_TYPE_AMICO_E              4327
+#define MACH_TYPE_SENTIENT_MM3_CK      4328
+#define MACH_TYPE_SMX6                 4329
+#define MACH_TYPE_PANGO                4330
+#define MACH_TYPE_NS115_STICK          4331
+#define MACH_TYPE_BCTRM3               4332
+#define MACH_TYPE_DOCTORWS             4333
+#define MACH_TYPE_M2601                4334
+#define MACH_TYPE_GRIDCO_TRINITY       4335
+#define MACH_TYPE_PC3032               4336
+#define MACH_TYPE_VGG1111              4337
+#define MACH_TYPE_COUNTACH             4338
+#define MACH_TYPE_VISSTRIM_SM20        4339
+#define MACH_TYPE_A639                 4340
+#define MACH_TYPE_SPACEMONKEY          4341
+#define MACH_TYPE_ZPDU_STAMP           4342
+#define MACH_TYPE_HTC_G7_CLONE         4343
+#define MACH_TYPE_FT2080_CORVUS        4344
+#define MACH_TYPE_FISLAND              4345
+#define MACH_TYPE_ZPDU                 4346
+#define MACH_TYPE_URT                  4347
+#define MACH_TYPE_CONTI_OVIP           4348
+#define MACH_TYPE_OMAPL138_NAGRA       4349
+#define MACH_TYPE_DA850_AT3KP1         4350
+#define MACH_TYPE_DA850_AT3KP2         4351
+#define MACH_TYPE_SURMA                4352
+#define MACH_TYPE_STM_B2092            4353
+#define MACH_TYPE_MX535_YCR            4354
+#define MACH_TYPE_M7_WL                4355
+#define MACH_TYPE_M7_U                 4356
+#define MACH_TYPE_OMAP3_STNDT_EVM      4357
+#define MACH_TYPE_M7_WLV               4358
+#define MACH_TYPE_XAM3517              4359
+#define MACH_TYPE_A220                 4360
+#define MACH_TYPE_ACLIMA_ODIE          4361
+#define MACH_TYPE_VIBBLE               4362
+#define MACH_TYPE_K2_U                 4363
+#define MACH_TYPE_MX53_EGF             4364
+#define MACH_TYPE_NOVPEK_IMX53         4365
+#define MACH_TYPE_NOVPEK_IMX6X         4366
+#define MACH_TYPE_MX25_SMARTBOX        4367
+#define MACH_TYPE_EICG6410             4368
+#define MACH_TYPE_PICASSO_E3           4369
+#define MACH_TYPE_MOTONAVIGATOR        4370
+#define MACH_TYPE_VARIOCONNECT2        4371
+#define MACH_TYPE_DELUXE_TW            4372
+#define MACH_TYPE_KORE3                4374
+#define MACH_TYPE_MX6S_DRS             4375
+#define MACH_TYPE_CMIMX6               4376
+#define MACH_TYPE_ROTH                 4377
+#define MACH_TYPE_EQ4UX                4378
+#define MACH_TYPE_X1PLUS               4379
+#define MACH_TYPE_MODIMX27             4380
+#define MACH_TYPE_VIDEON_HDUAC         4381
+#define MACH_TYPE_BLACKBIRD            4382
+#define MACH_TYPE_RUNMASTER            4383
+#define MACH_TYPE_CERES                4384
+#define MACH_TYPE_NAD435               4385
+#define MACH_TYPE_NS115_PROTO_TYPE     4386
+#define MACH_TYPE_FS20_VCC             4387
+#define MACH_TYPE_MESON6TV             4388
+#define MACH_TYPE_MESON6TV_SKT         4389
+#define MACH_TYPE_KEYSTONE             4390
+#define MACH_TYPE_PCM052               4391
+#define MACH_TYPE_TYPE                 4392
+#define MACH_TYPE_QRD_SKUD_PRIME       4393
+#define MACH_TYPE_RAINBOWG15           4394
+#define MACH_TYPE_GUF_SANTARO          4395
+#define MACH_TYPE_SHEEPSHEAD           4396
+#define MACH_TYPE_MX6_IWG15M_MXM       4397
+#define MACH_TYPE_MX6_IWG15M_Q7        4398
+#define MACH_TYPE_AT91SAM9263IF8MIC    4399
+#define MACH_TYPE_EXCEL                4400
+#define MACH_TYPE_MARCOPOLO            4401
+#define MACH_TYPE_MX535_SDCR           4402
+#define MACH_TYPE_MX53_CSB2733         4403
+#define MACH_TYPE_DIVA                 4404
+#define MACH_TYPE_NCR_7744             4405
+#define MACH_TYPE_MACALLAN             4406
+#define MACH_TYPE_WNR3500              4407
+#define MACH_TYPE_PGAVRF               4408
+#define MACH_TYPE_HELIOS_V6            4409
+#define MACH_TYPE_LCCT                 4410
+#define MACH_TYPE_CSNDUG               4411
+#define MACH_TYPE_WANDBOARD_IMX6       4412
+#define MACH_TYPE_OMAP4_JET            4413
+#define MACH_TYPE_TEGRA_ROTH           4414
+#define MACH_TYPE_M7DCG                4415
+#define MACH_TYPE_M7DUG                4416
+#define MACH_TYPE_M7DTG                4417
+#define MACH_TYPE_AP42X                4418
+#define MACH_TYPE_VAR_SOM_MX6          4419
+#define MACH_TYPE_PDLU                 4420
+#define MACH_TYPE_HYDROGEN             4421
+#define MACH_TYPE_NPA211E              4422
+#define MACH_TYPE_ARCADIA              4423
+#define MACH_TYPE_ARCADIA_L            4424
+#define MACH_TYPE_MSM8930DT            4425
+#define MACH_TYPE_KTAM3874             4426
+#define MACH_TYPE_CEC4                 4427
+#define MACH_TYPE_APE6EVM              4428
+#define MACH_TYPE_TX6                  4429
+#define MACH_TYPE_OWENSOM              4430
+#define MACH_TYPE_CFA10037             4431
+#define MACH_TYPE_NATEKS_VOIP          4432
+#define MACH_TYPE_EZP1000              4433
+#define MACH_TYPE_WGR826V              4434
+#define MACH_TYPE_EXUMA                4435
+#define MACH_TYPE_FREGATE              4436
+#define MACH_TYPE_OSIRISIMX508         4437
+#define MACH_TYPE_ST_EXIGO             4438
+#define MACH_TYPE_PISMO                4439
+#define MACH_TYPE_ATC7                 4440
+#define MACH_TYPE_NSPIRECLP            4441
+#define MACH_TYPE_NSPIRETP             4442
+#define MACH_TYPE_NSPIRECX             4443
+#define MACH_TYPE_MAYA                 4444
+#define MACH_TYPE_WECCT                4445
+#define MACH_TYPE_M2S                  4446
+#define MACH_TYPE_MSM8625Q_EVBD        4447
+#define MACH_TYPE_TINY210              4448
+#define MACH_TYPE_G3                   4449
+#define MACH_TYPE_HURRICANE            4450
+#define MACH_TYPE_MX6_POD              4451
+#define MACH_TYPE_ELONDCN              4452
+#define MACH_TYPE_CWMX535              4453
+#define MACH_TYPE_M7_WLJ               4454
+#define MACH_TYPE_QSP_ARM              4455
+#define MACH_TYPE_MSM8625Q_SKUD        4456
+#define MACH_TYPE_HTCMONDRIAN          4457
+#define MACH_TYPE_WATSON_EAD           4458
+#define MACH_TYPE_MITWOA               4459
+#define MACH_TYPE_OMAP3_WOLVERINE      4460
+#define MACH_TYPE_MAPLETREE            4461
+#define MACH_TYPE_MSM8625_FIH_SAE      4462
+#define MACH_TYPE_EPC35                4463
+#define MACH_TYPE_SMARTRTU             4464
+#define MACH_TYPE_RCM101               4465
+#define MACH_TYPE_AMX_IMX53_MXX        4466
+#define MACH_TYPE_CP3DCG               4467
+#define MACH_TYPE_CP3DTG               4468
+#define MACH_TYPE_CP3DUG               4469
+#define MACH_TYPE_ACER_A12             4470
+#define MACH_TYPE_SBC6X                4471
+#define MACH_TYPE_U2                   4472
+#define MACH_TYPE_SMDK4270             4473
+#define MACH_TYPE_PRISCILLAG           4474
+#define MACH_TYPE_PRISCILLAC           4475
+#define MACH_TYPE_PRISCILLA            4476
+#define MACH_TYPE_INNOVA_SHPU_V2       4477
+#define MACH_TYPE_M7CDTU               4478
+#define MACH_TYPE_MACH_TYPE_DEP2410    4479
+#define MACH_TYPE_BCTRE3               4480
+#define MACH_TYPE_OMAP_M100            4481
+#define MACH_TYPE_FLO                  4482
+#define MACH_TYPE_NANOBONE             4483
+#define MACH_TYPE_STM_B2105            4484
+#define MACH_TYPE_OMAP4_BSC_BAP_V3     4485
+#define MACH_TYPE_SS1PAM               4486
+#define MACH_TYPE_DLXP_WL              4487
+#define MACH_TYPE_PRIMOMINIU           4488
+#define MACH_TYPE_MRT_35HD_DUALNAS_E   4489
+#define MACH_TYPE_KIWI                 4490
+#define MACH_TYPE_HW90496              4491
+#define MACH_TYPE_MEP2440              4492
+#define MACH_TYPE_COLIBRI_T30          4493
+#define MACH_TYPE_CWV1                 4494
+#define MACH_TYPE_NSA325               4495
+#define MACH_TYPE_DLXP_UL              4496
+#define MACH_TYPE_DPXMTC               4497
+#define MACH_TYPE_TT_STUTTGART         4498
+#define MACH_TYPE_MIRANDA_APCII        4499
+#define MACH_TYPE_MX6Q_MODEROX         4500
+#define MACH_TYPE_MUDSKIPPER           4501
+#define MACH_TYPE_URANIA               4502
+#define MACH_TYPE_STM_B2112            4503
+#define MACH_TYPE_GTOU                 4504
+#define MACH_TYPE_MX6Q_ATS_PHOENIX     4505
+#define MACH_TYPE_STM_B2116            4506
+#define MACH_TYPE_MYTHOLOGY            4507
+#define MACH_TYPE_FC360V1              4508
+#define MACH_TYPE_GPS_SENSOR           4509
+#define MACH_TYPE_GAZELLE              4510
+#define MACH_TYPE_MPQ8064_DMA          4511
+#define MACH_TYPE_WEMS_ASD01           4512
+#define MACH_TYPE_APALIS_T30           4513
+#define MACH_TYPE_MX6Q_QSBC35_C398     4514
+#define MACH_TYPE_ARMSTONEA9           4515
+#define MACH_TYPE_OMAP_BLAZETABLET     4516
+#define MACH_TYPE_AR6MXQ               4517
+#define MACH_TYPE_AR6MXS               4518
+#define MACH_TYPE_DETO_APOS_MX6        4519
+#define MACH_TYPE_GWVENTANA            4520
+#define MACH_TYPE_IGEP0033             4521
+#define MACH_TYPE_RACA                 4522
+#define MACH_TYPE_APPLESODA            4523
+#define MACH_TYPE_H52C1_CONCERTO       4524
+#define MACH_TYPE_FCMBRD               4525
+#define MACH_TYPE_PCAAXS1              4526
+#define MACH_TYPE_LS_ORCA              4527
+#define MACH_TYPE_PCM051LB             4528
+#define MACH_TYPE_MX6S_LP507_GVCI      4529
+#define MACH_TYPE_DIDO                 4530
+#define MACH_TYPE_SWARCO_ITC3_9G20     4531
+#define MACH_TYPE_ROBO_ROADY           4532
+#define MACH_TYPE_RSKRZA1              4533
+#define MACH_TYPE_SWARCO_SID           4534
+#define MACH_TYPE_MX6_IWG15S_SBC       4535
+#define MACH_TYPE_MX6Q_CAMARO          4536
+#define MACH_TYPE_HB6MXS               4537
+#define MACH_TYPE_LAGER                4538
+#define MACH_TYPE_LP8X4X               4539
+#define MACH_TYPE_TEGRATAB7            4540
+#define MACH_TYPE_ANDROMEDA            4541
+#define MACH_TYPE_BOOTES               4542
+#define MACH_TYPE_NETHMI               4543
+#define MACH_TYPE_TEGRATAB             4544
+#define MACH_TYPE_SOM5_EVB             4545
+#define MACH_TYPE_VENATICORUM          4546
+#define MACH_TYPE_STM_B2110            4547
+#define MACH_TYPE_ELUX_HATHOR          4548
+#define MACH_TYPE_HELIOS_V7            4549
+#define MACH_TYPE_XC10V1               4550
+#define MACH_TYPE_CP2U                 4551
+#define MACH_TYPE_IAP_F                4552
+#define MACH_TYPE_IAP_G                4553
+#define MACH_TYPE_AAE                  4554
+#define MACH_TYPE_PEGASUS              4555
+#define MACH_TYPE_CYGNUS               4556
+#define MACH_TYPE_CENTAURUS            4557
+#define MACH_TYPE_MSM8930_QRD8930      4558
+#define MACH_TYPE_QUBY_TIM             4559
+#define MACH_TYPE_ZEDI3250A            4560
+#define MACH_TYPE_GRUS                 4561
+#define MACH_TYPE_APOLLO3              4562
+#define MACH_TYPE_COWON_R7             4563
+#define MACH_TYPE_TONGA3               4564
+#define MACH_TYPE_P535                 4565
+#define MACH_TYPE_SA3874I              4566
+#define MACH_TYPE_MX6_NAVICO_COM       4567
+#define MACH_TYPE_PROXMOBIL2           4568
+#define MACH_TYPE_UBINUX1              4569
+#define MACH_TYPE_ISTOS                4570
+#define MACH_TYPE_BENVOLIO4            4571
+#define MACH_TYPE_ECO5_BX2             4572
+#define MACH_TYPE_EUKREA_CPUIMX28SD    4573
+#define MACH_TYPE_DOMOTAB              4574
+#define MACH_TYPE_PFLA03               4575
+#define MACH_TYPE_ET_CPU_301_16        4576
+#define MACH_TYPE_SKYWALKER            4577
+#define MACH_TYPE_SCORPIUS             4578
+#define MACH_TYPE_CAPRICORNUS          4579
+#define MACH_TYPE_LYRA                 4580
+#define MACH_TYPE_GATERO               4581
+#define MACH_TYPE_GATERO01             4582
+#define MACH_TYPE_Z4DTG                4583
+#define MACH_TYPE_LUPUS                4584
+#define MACH_TYPE_LEAP101              4585
+#define MACH_TYPE_CM_T335              4586
+#define MACH_TYPE_PNA                  4587
+#define MACH_TYPE_ECOFOREST_CPU2013    4588
+#define MACH_TYPE_APQ8064_DMA          4589
+#define MACH_TYPE_MX53_ARMOUR          4590
+#define MACH_TYPE_EUROFUNK_AEPL3       4591
+#define MACH_TYPE_EUROFUNK_MHLS3       4592
+#define MACH_TYPE_EUROFUNK_E1IF        4593
+#define MACH_TYPE_LEPUS                4594
+#define MACH_TYPE_BORA                 4595
+#define MACH_TYPE_ADS4011              4596
+#define MACH_TYPE_BEAVER               4597
+#define MACH_TYPE_IMX233_IUNGO         4598
+#define MACH_TYPE_CEPHEUS              4599
+#define MACH_TYPE_CETUS                4600
+#define MACH_TYPE_CHAMAELEON           4601
+#define MACH_TYPE_ARDBEG               4602
+#define MACH_TYPE_IXORA                4603
+#define MACH_TYPE_JUGLANS              4604
+#define MACH_TYPE_CANISMAJOR           4605
+#define MACH_TYPE_AT91SAM9263MIB       4606
+#define MACH_TYPE_COSINO_9G35          4607
+#define MACH_TYPE_TINY4412             4608
+#define MACH_TYPE_BALLOON4             4609
+#define MACH_TYPE_PGG                  4610
+#define MACH_TYPE_XXSQ701              4611
+#define MACH_TYPE_MX6_NAVICO_RDR       4612
+#define MACH_TYPE_PHANTOM              4613
+#define MACH_TYPE_CANISMINORH          4614
+#define MACH_TYPE_CARINA               4615
+#define MACH_TYPE_E1859                4616
+#define MACH_TYPE_ARMSTONEA5           4617
+#define MACH_TYPE_PICOCOMA5            4618
+#define MACH_TYPE_NETDCUA5             4619
+#define MACH_TYPE_MOLLY                4620
+#define MACH_TYPE_MASERATI             4621
+#define MACH_TYPE_MX53_IDEBX           4622
+#define MACH_TYPE_MX53_C2CB            4623
+#define MACH_TYPE_MIPSEE               4624
+#define MACH_TYPE_SEEKLOP              4625
+#define MACH_TYPE_AUDISEE              4626
+#define MACH_TYPE_TX48                 4627
+#define MACH_TYPE_TL7689_PAD_REF       4628
+#define MACH_TYPE_TL7689_PAD_TEST      4629
+#define MACH_TYPE_TL7689_PHONE_REF     4630
+#define MACH_TYPE_TL7689_PHONE_TEST    4631
+#define MACH_TYPE_SWARCO_SCC_WKS       4632
+#define MACH_TYPE_ACCORDO2             4633
+#define MACH_TYPE_TRIZEPS7             4634
+#define MACH_TYPE_F100                 4635
+#define MACH_TYPE_ARMADILLO410         4636
+#define MACH_TYPE_TINY2416             4637
+#define MACH_TYPE_TINY2451             4638
+#define MACH_TYPE_MINI2451             4639
+#define MACH_TYPE_TINY5250             4640
+#define MACH_TYPE_TINY3358             4641
+#define MACH_TYPE_T6_UL                4642
+#define MACH_TYPE_T6_U                 4643
+#define MACH_TYPE_T6_ULA               4644
+#define MACH_TYPE_T6_WL                4645
+#define MACH_TYPE_T6_WHL               4646
+#define MACH_TYPE_CIRCINUS             4647
+#define MACH_TYPE_SOCPK255             4648
+#define MACH_TYPE_SOCPRV270            4649
+#define MACH_TYPE_SOCPRC270            4650
+#define MACH_TYPE_MACH_CP5DTU          4651
+#define MACH_TYPE_CP5DTU               4652
+#define MACH_TYPE_CP5DUG               4653
+#define MACH_TYPE_CP5DWG               4654
+#define MACH_TYPE_AM335X_EGF           4655
+#define MACH_TYPE_AZM9G45              4656
+#define MACH_TYPE_AZM335X              4657
+#define MACH_TYPE_LYNBRD               4658
+#define MACH_TYPE_AM35X_EGF            4659
+#define MACH_TYPE_SEVULCAN             4660
+#define MACH_TYPE_AX8008M              4661
+#define MACH_TYPE_AX8008MR             4662
+#define MACH_TYPE_XYNIX                4663
+#define MACH_TYPE_OMAP3621_ODYV4       4664
+#define MACH_TYPE_MX6_CAMERONET        4665
+#define MACH_TYPE_OMAP4_DART           4666
+#define MACH_TYPE_MX6Q_ENZO            4667
+#define MACH_TYPE_EV_IMX287MICRO       4668
+#define MACH_TYPE_EV_IMX287MINI        4669
+#define MACH_TYPE_MX53_CEC2            4670
+#define MACH_TYPE_HELIOS_V8            4671
+#define MACH_TYPE_HELIOS_V9            4672
+#define MACH_TYPE_COGNAC               4673
+#define MACH_TYPE_ZEST                 4674
+#define MACH_TYPE_GC3                  4675
+#define MACH_TYPE_DAD_MEDIA            4676
+#define MACH_TYPE_HTOUCH               4677
+#define MACH_TYPE_SPT7500BASEBOARD     4678
+#define MACH_TYPE_OMAP4_DART_EVM       4679
+#define MACH_TYPE_MX53_TLV             4680
+#define MACH_TYPE_PDAK2H               4681
+#define MACH_TYPE_MATRIX513            4682
+#define MACH_TYPE_LIVEBOX01            4683
+#define MACH_TYPE_CEVRZA1L             4684
+#define MACH_TYPE_B1010                4685
+#define MACH_TYPE_FWTMK1               4686
+#define MACH_TYPE_GRENADA              4687
+#define MACH_TYPE_HASSEL               4688
+#define MACH_TYPE_ODROIDXU             4689
+#define MACH_TYPE_ODROIDU2             4690
+#define MACH_TYPE_NAIAD                4691
+#define MACH_TYPE_HARRIER              4692
+#define MACH_TYPE_PCL052               4693
+#define MACH_TYPE_LIBRA2404            4694
+#define MACH_TYPE_MX6_LEMONBOARD       4695
+#define MACH_TYPE_MX6_ATLAS            4696
+#define MACH_TYPE_ELECSYS_Z2           4697
+#define MACH_TYPE_ELECSYS_Z4           4698
+#define MACH_TYPE_IPQ806X_DB149        4699
+#define MACH_TYPE_PULSAR               4700
+#define MACH_TYPE_SCALANCEM            4701
+#define MACH_TYPE_NA11                 4702
+#define MACH_TYPE_IPQ806X_DB147        4703
+#define MACH_TYPE_IPQ806X_AP148        4704
+#define MACH_TYPE_AMLTD_IMX6           4705
+#define MACH_TYPE_PIA_AM335X           4706
+#define MACH_TYPE_BLADE                4707
+#define MACH_TYPE_MATISSE              4708
+#define MACH_TYPE_IKEBANA              4709
+#define MACH_TYPE_LF3000               4710
+#define MACH_TYPE_CARALLON_STINGRAY    4711
+#define MACH_TYPE_MENSA                4712
+#define MACH_TYPE_CES_COREBOARD        4713
+#define MACH_TYPE_VYBRID_IWG16M_UMXM   4714
+#define MACH_TYPE_LOKI                 4715
+#define MACH_TYPE_PCM053               4716
+#define MACH_TYPE_SMM200               4717
+#define MACH_TYPE_M507                 4718
+#define MACH_TYPE_ORSOC_ARMSOC_8695    4719
+#define MACH_TYPE_AM335X_ZY            4720
+#define MACH_TYPE_ARRAKIS              4721
+#define MACH_TYPE_SXLT                 4722
+#define MACH_TYPE_YLCM                 4723
+#define MACH_TYPE_EAGLE6D              4724
+#define MACH_TYPE_LCU1                 4725
+#define MACH_TYPE_MX6DL_IWG15M_Q7      4726
+#define MACH_TYPE_SBCPHYFLEXAM335      4727
+#define MACH_TYPE_SBCPHYCARDAM335      4728
+#define MACH_TYPE_SBCPHYFLEXIMX6       4729
+#define MACH_TYPE_HOMESERVERSTICK      4730
+#define MACH_TYPE_ECXEC                4731
+#define MACH_TYPE_HH300                4732
+#define MACH_TYPE_CPUCA8               4733
+#define MACH_TYPE_A0057_LSEMBEDDEDPC   4734
+#define MACH_TYPE_IPROC                4735
+#define MACH_TYPE_NEMESIS_NFE          4736
+#define MACH_TYPE_MABV3X25             4737
+#define MACH_TYPE_OCTANT               4738
+#define MACH_TYPE_MSM7X27_THUNDER      4739
+#define MACH_TYPE_MAXIM                4740
+#define MACH_TYPE_TELEMATICCTRLUNIT    4741
+#define MACH_TYPE_MX6Q_JCDBOX          4742
+#define MACH_TYPE_CKB_1808             4743
+#define MACH_TYPE_CKB_3352             4744
+#define MACH_TYPE_HIKIRK               4745
+#define MACH_TYPE_DNS320L              4746
+#define MACH_TYPE_STM_B2120            4747
+#define MACH_TYPE_STM_B2089            4748
+#define MACH_TYPE_COLIBRI_VF50         4749
+#define MACH_TYPE_COLIBRI_VF61         4750
+#define MACH_TYPE_SYNERGY2             4751
+#define MACH_TYPE_PCM051_HMI           4752
+#define MACH_TYPE_TEK2                 4753
+#define MACH_TYPE_DUCKBILL             4754
+#define MACH_TYPE_MX50_SEISMIC         4755
+#define MACH_TYPE_TWOFACE              4756
+#define MACH_TYPE_T10                  4757
+#define MACH_TYPE_LIB1313              4758
+#define MACH_TYPE_HIMX                 4759
+#define MACH_TYPE_VCM30_T30            4760
+#define MACH_TYPE_CORNERVIEW           4761
+#define MACH_TYPE_P01600               4762
+#define MACH_TYPE_AXEL                 4763
+#define MACH_TYPE_IMX6_ANDY            4764
+#define MACH_TYPE_NSA220               4765
+#define MACH_TYPE_TI8168HSC1           4766
+#define MACH_TYPE_DORY                 4767
+#define MACH_TYPE_ECV4                 4768
+#define MACH_TYPE_WEBBG3FLIGHT         4769
+#define MACH_TYPE_SBC_PHYCORE_AM335X   4770
+#define MACH_TYPE_TSC                  4771
+#define MACH_TYPE_IMX6_CLOUS           4772
+#define MACH_TYPE_C1                   4773
+#define MACH_TYPE_VCM30T30             4774
+#define MACH_TYPE_IMX6_EMSYM_BLURR     4775
+#define MACH_TYPE_PDIS_M               4776
+#define MACH_TYPE_MX6Q_REX             4777
+#define MACH_TYPE_SWARCO_FR_ANYBUS     4778
+#define MACH_TYPE_SHMAC                4779
+#define MACH_TYPE_CKB_RZA1H            4780
+#define MACH_TYPE_AZETI_SP_NG01        4781
+#define MACH_TYPE_E6210                4782
+#define MACH_TYPE_MH9001               4783
+#define MACH_TYPE_STM_B2147            4784
+#define MACH_TYPE_OMAP5_VARSOM         4785
+#define MACH_TYPE_CUBEA5               4786
+#define MACH_TYPE_CP5                  4787
+#define MACH_TYPE_FORNAX               4788
+#define MACH_TYPE_ICU                  4789
+#define MACH_TYPE_COMUS3               4790
+#define MACH_TYPE_LIBRA4344            4791
+#define MACH_TYPE_LIBRA4644            4792
+#define MACH_TYPE_PAVO                 4793
+#define MACH_TYPE_XL824                4794
+#define MACH_TYPE_XL850                4795
+#define MACH_TYPE_MX6_PICO_ITX         4796
+#define MACH_TYPE_AMICO_S              4797
+#define MACH_TYPE_AMICO_P              4798
+#define MACH_TYPE_MINNOW               4799
+#define MACH_TYPE_DAVINCI_DM365_ZY     4800
+#define MACH_TYPE_PAVO_2               4801
+#define MACH_TYPE_IAVS                 4802
+#define MACH_TYPE_RANA                 4803
+#define MACH_TYPE_MERAKI_MS26          4804
+#define MACH_TYPE_VP2_REFRESH          4805
+#define MACH_TYPE_MCB1800              4806
+#define MACH_TYPE_MX6Q_DEVONIT_TC3     4807
+#define MACH_TYPE_UC81XX               4808
+#define MACH_TYPE_UC84XX               4809
+#define MACH_TYPE_IPQ806X_AP145        4810
+#define MACH_TYPE_IPQ806X_DB149_MMC    4811
+#define MACH_TYPE_IPQ806X_AP145_MMC    4812
+#define MACH_TYPE_E3QT                 4813
+#define MACH_TYPE_U222                 4814
+#define MACH_TYPE_UFO878               4815
+#define MACH_TYPE_GEKKO                4816
+#define MACH_TYPE_MINI2440ARM          4817
+#define MACH_TYPE_MPCSB2_9G20          4818
+#define MACH_TYPE_TL7689_PAD_706       4819
+#define MACH_TYPE_TDA7                 4820
+#define MACH_TYPE_CUBOXI               4821
+#define MACH_TYPE_TIBIDABO             4822
+#define MACH_TYPE_T216MINI             4823
+#define MACH_TYPE_HERA_IMX6            4824
+#define MACH_TYPE_GRIDPOINT_EC1K       4825
+#define MACH_TYPE_LIBRA4404            4826
+#define MACH_TYPE_MI_MOCHA             4827
+#define MACH_TYPE_BCM2835              4828
+#define MACH_TYPE_NFP6XXX              4829
+#define MACH_TYPE_TETRA                4830
+#define MACH_TYPE_NECO                 4831
+#define MACH_TYPE_PROTONEX_VPM402      4832
+#define MACH_TYPE_MX6Q_SAVAGE          4833
+#define MACH_TYPE_MX6Q_SOMB            4834
+#define MACH_TYPE_FILI_DL              4835
+#define MACH_TYPE_ADAPT_SDRDC          4836
+#define MACH_TYPE_DS_QUARTZ            4837
+#define MACH_TYPE_ULTRAFLEX            4838
+#define MACH_TYPE_APQ8064_ADP_2        4839
+#define MACH_TYPE_BEAN                 4840
+#define MACH_TYPE_BALDR                4841
+#define MACH_TYPE_CCIMX6ADPT           4842
+#define MACH_TYPE_TS4900               4843
+#define MACH_TYPE_ZEPLUG               4844
+#define MACH_TYPE_MSM8X60_DUPLICITY    4845
+#define MACH_TYPE_CTERA_2BAY_A         4846
+#define MACH_TYPE_AM335X_BAP_V3_1      4847
+#define MACH_TYPE_XPECT01              4848
+#define MACH_TYPE_ESI23                4849
+#define MACH_TYPE_MX6DL_SBC35_C398     4850
+#define MACH_TYPE_MX6SOLO_SBC35_C398   4851
+#define MACH_TYPE_KSP5012              4852
+#define MACH_TYPE_MX6Q_ZEUS            4853
+#define MACH_TYPE_INNOVA_MATRIX        4854
+#define MACH_TYPE_RF6XXR               4855
+#define MACH_TYPE_PECORINO             4856
+#define MACH_TYPE_MHPLAY_W             4857
+#define MACH_TYPE_PELCO_DRAGONFLY      4858
+#define MACH_TYPE_VSM_CHAMHIGH         4859
+#define MACH_TYPE_HACHIKO              4860
+#define MACH_TYPE_TL7689_PHONE_IN260   4861
+#define MACH_TYPE_CWMX6                4862
+#define MACH_TYPE_HD3                  4863
+#define MACH_TYPE_UHD4                 4864
+#define MACH_TYPE_BULPRINT_BOARD       4865
+#define MACH_TYPE_PELCO_SPECTRAHD2     4866
+#define MACH_TYPE_VISTEONV2X           4867
+#define MACH_TYPE_PHIDGET_VINTSBC      4868
+#define MACH_TYPE_LMU7030              4869
+#define MACH_TYPE_ECC2                 4870
+#define MACH_TYPE_CDS_CTS              4871
+#define MACH_TYPE_AXELLITE             4872
+#define MACH_TYPE_ARNIE                4873
+#define MACH_TYPE_AGATEWAY             4874
+#define MACH_TYPE_PICOMODA9            4875
+#define MACH_TYPE_P_137_I6             4876
+#define MACH_TYPE_VVDN_MCAM            4877
+#define MACH_TYPE_MX6_INSIGHT          4878
+#define MACH_TYPE_VIPRINET_200         4879
+#define MACH_TYPE_ELLYPTO              4880
+#define MACH_TYPE_G7P                  4881
+#define MACH_TYPE_YSE5250              4882
+#define MACH_TYPE_NG500                4883
+#define MACH_TYPE_DTSC02               4884
+#define MACH_TYPE_MX6DL_SBB            4885
+#define MACH_TYPE_APALIS_IMX6Q         4886
+#define MACH_TYPE_WOMBAT6              4887
+#define MACH_TYPE_BALTO                4888
+#define MACH_TYPE_TNGSBL               4889
+#define MACH_TYPE_H6061                4890
+#define MACH_TYPE_XA300                4891
+#define MACH_TYPE_PELCO_WOOFF          4892
+#define MACH_TYPE_PELCO_EVM            4893
+#define MACH_TYPE_MX6Q_IMXB            4894
+#define MACH_TYPE_SMARTTAB_V55         4895
+#define MACH_TYPE_SMARTTAB_V11A        4896
+#define MACH_TYPE_SMARTTAB_V71A        4897
+#define MACH_TYPE_NOVASOM5             4898
+#define MACH_TYPE_CCIMX6SBC            4899
+#define MACH_TYPE_INTOUCH              4900
+#define MACH_TYPE_MX6S_HAWTHORNE       4901
+#define MACH_TYPE_SEAH                 4902
+#define MACH_TYPE_AM335X_EC3           4903
+#define MACH_TYPE_EMBEST_MARS          4904
+#define MACH_TYPE_MX6DL_VIKITOUCH      4905
+#define MACH_TYPE_IX2_NG               4906
+#define MACH_TYPE_PEKQSD               4907
+#define MACH_TYPE_PTEKN                4908
+#define MACH_TYPE_APQ8064_ADP2_ES2     4909
+#define MACH_TYPE_GHIIMX6              4910
+#define MACH_TYPE_M3000                4911
+#define MACH_TYPE_TCW101               4912
+#define MACH_TYPE_IPQ806X_AP148_1XX    4913
+#define MACH_TYPE_HNS_ACADIA           4914
+#define MACH_TYPE_MX6S_VIKITOUCH       4915
+#define MACH_TYPE_CM_QS600             4916
+#define MACH_TYPE_IPQ806X_DB149_2XX    4917
+#define MACH_TYPE_EAG_UGW400           4918
+#define MACH_TYPE_SK_GRANT_OEM         4919
+#define MACH_TYPE_KNOBLOCH_TXT         4920
+#define MACH_TYPE_MX6SL_SHD            4921
+#define MACH_TYPE_HIMX0294             4922
+#define MACH_TYPE_MX6Q_TTJ500          4923
+#define MACH_TYPE_CONTI_SGM358         4924
+#define MACH_TYPE_DENSOJ6REF           4925
+#define MACH_TYPE_KEVIN                4926
+#define MACH_TYPE_VVDN_TOII            4927
+#define MACH_TYPE_PENGWYN              4928
+#define MACH_TYPE_XARINA_ENTRY         4929
+#define MACH_TYPE_CONTI_MRNEVO         4930
+#define MACH_TYPE_NSA310S              4931
+#define MACH_TYPE_POWERECU             4932
+#define MACH_TYPE_Q7M120               4933
+#define MACH_TYPE_H6829                4934
+#define MACH_TYPE_AG13008              4935
+#define MACH_TYPE_IPQ806X_STORM        4936
+#define MACH_TYPE_DM3725_GSOM          4937
+#define MACH_TYPE_HP_PRIME             4938
+#define MACH_TYPE_FIRESTORM            4939
+#define MACH_TYPE_WINGZ                4940
+#define MACH_TYPE_ANDROMED             4941
+#define MACH_TYPE_SCM120               4942
+#define MACH_TYPE_CM_3G                4943
+#define MACH_TYPE_IPA400               4944
+#define MACH_TYPE_HYDRA_MKII           4945
+#define MACH_TYPE_AXM2                 4946
+#define MACH_TYPE_CALOPUS              4947
+#define MACH_TYPE_BCTRM3S              4948
+#define MACH_TYPE_DM385LB              4949
+#define MACH_TYPE_SURMA_MKII           4950
+#define MACH_TYPE_OMAP4_SKHU_HCAM      4951
+#define MACH_TYPE_SCMCON               4952
+#define MACH_TYPE_KLK_IMX6S_G          4953
+#define MACH_TYPE_AM335XMX             4954
+#define MACH_TYPE_DMVA2_BTFU_WCAM      4955
+#define MACH_TYPE_UXC                  4956
+#define MACH_TYPE_ELARM_A              4957
+#define MACH_TYPE_EMPC_AIMX6           4958
+#define MACH_TYPE_BCTRE2G2             4959
+#define MACH_TYPE_DMD                  4960
+#define MACH_TYPE_DISCOVERY            4961
+#define MACH_TYPE_RELIAGATE_10_20      4962
+#define MACH_TYPE_MX6Q_DSA2LS          4963
+#define MACH_TYPE_MX6SL_ECT5           4964
+#define MACH_TYPE_COBHAM_MDC3          4965
+#define MACH_TYPE_TS_WAV               4966
+#define MACH_TYPE_XIN_GIGE_CAM         4967
+#define MACH_TYPE_ASAIIOTG             4968
+#define MACH_TYPE_DAU                  4969
+#define MACH_TYPE_SOCFPGA_ARRIA5       4970
+#define MACH_TYPE_IPQ806X_AP160        4971
+#define MACH_TYPE_IPQ806X_AP161        4972
+#define MACH_TYPE_GEMX6                4973
+#define MACH_TYPE_EFUSA9               4974
+#define MACH_TYPE_DYNACOR_10_20        4975
+#define MACH_TYPE_BLUELIGHTNING        4976
+#define MACH_TYPE_SILVERBULLET         4977
+#define MACH_TYPE_MX6_MAEXLE           4978
+#define MACH_TYPE_PAYTEC_EPT           4979
+#define MACH_TYPE_ATLASCOPCO_ITMK2     4980
+#define MACH_TYPE_ATLASCOPCO_FLEXDRV   4981
+#define MACH_TYPE_ATLASCOPCO_FLEXIT    4982
+#define MACH_TYPE_PCDON                4983
+#define MACH_TYPE_DM8168_IWG12M_Q7     4984
+#define MACH_TYPE_RTM9431              4985
+#define MACH_TYPE_ARM11_CAR            4986
+#define MACH_TYPE_VIDEOPHONE           4987
+#define MACH_TYPE_MPFA                 4988
+#define MACH_TYPE_PS10                 4989
+#define MACH_TYPE_HGATEWAY             4990
+#define MACH_TYPE_IPQ806X_AP160_2      4991
+#define MACH_TYPE_ECP5COM              4992
+#define MACH_TYPE_H6064                4993
+#define MACH_TYPE_MX6X_MX              4994
+#define MACH_TYPE_MAJIC5422            4995
+#define MACH_TYPE_EMINDS               4996
+#define MACH_TYPE_TI8168TOII           4997
+#define MACH_TYPE_VXR10                4998
+#define MACH_TYPE_DS5                  4999
+#define MACH_TYPE_DS3                  5000
+#define MACH_TYPE_NOKIAN97             5001
+#define MACH_TYPE_TECNINT_ODBC         5002
+#define MACH_TYPE_C111                 5003
+#define MACH_TYPE_ML300DU              5004
+#define MACH_TYPE_YAK                  5005
+#define MACH_TYPE_NSA221               5006
+#define MACH_TYPE_GINKGOP              5007
+#define MACH_TYPE_MANGO                5008
+#define MACH_TYPE_AMBS2E               5009
+#define MACH_TYPE_AMBS3L               5010
+#define MACH_TYPE_DRA7XX_EVM           5011
+#define MACH_TYPE_DENSODRA74XMID       5012
+#define MACH_TYPE_MILD                 5013
+#define MACH_TYPE_YLCM_MK2             5014
+#define MACH_TYPE_DS_CB                5015
+#define MACH_TYPE_EMPEROR              5016
+#define MACH_TYPE_ARTPEC               5017
+#define MACH_TYPE_DCIM                 5018
+#define MACH_TYPE_WS1XX                5019
+#define MACH_TYPE_IPQ806X_AK01_1XX     5020
+#define MACH_TYPE_MGWACE_DEC           5021
+#define MACH_TYPE_W6000                5022
+#define MACH_TYPE_WATSON_FIB_PLUGIN    5023
+#define MACH_TYPE_MX6Q_TINYREX         5024
+#define MACH_TYPE_MX6S_TINYREX         5025
+#define MACH_TYPE_MX6Q_MODEROS         5026
+#define MACH_TYPE_AFI                  5027
+#define MACH_TYPE_RCPRO                5028
+#define MACH_TYPE_ONBOX                5029
+#define MACH_TYPE_EXYNOS4412           5030
+#define MACH_TYPE_EXYNOS4413           5031
+#define MACH_TYPE_PELCO_DF20_EVT       5032
+#define MACH_TYPE_LION_DUG             5033
+#define MACH_TYPE_LIONP_DUG            5034
+#define MACH_TYPE_ESSE                 5035
+#define MACH_TYPE_ILLINOIS             5036
+#define MACH_TYPE_TI8168KSIPOLARIS     5037
+#define MACH_TYPE_YSE_BOARD            5038
+#define MACH_TYPE_PELCO_HWE0_EVT       5039
+#define MACH_TYPE_PELCO_S2E_EVM        5040
+#define MACH_TYPE_PELCO_DRAGONFLY20    5041
+#define MACH_TYPE_PELCO_HAWKEYE        5042
+#define MACH_TYPE_ARM                  5043
+#define MACH_TYPE_TCAM                 5044
+#define MACH_TYPE_MX6Q_HOBBY           5045
+#define MACH_TYPE_H6067                5046
+#define MACH_TYPE_DENSODRA72XLOW       5047
+#define MACH_TYPE_MX6_UNETBIT          5048
+#define MACH_TYPE_BT_OAK               5049
+#define MACH_TYPE_BT500                5050
+#define MACH_TYPE_FARWATER_GEO         5051
+#define MACH_TYPE_YT2                  5052
+#define MACH_TYPE_EH9000               5053
+#define MACH_TYPE_GVPU                 5054
+#define MACH_TYPE_CEDEX                5055
+#define MACH_TYPE_NT450R5G             5056
+#define MACH_TYPE_MSA23XX              5057
+#define MACH_TYPE_OMAP3_MOSS           5058
+#define MACH_TYPE_KYEONGHAWOO          5059
+#define MACH_TYPE_GIRA_IM03            5060
+#define MACH_TYPE_EUROFUNK_AIIF        5061
+#define MACH_TYPE_BCU1                 5062
+#define MACH_TYPE_DIYEFIS6410          5063
+#define MACH_TYPE_MX53_TURING          5064
+#define MACH_TYPE_MX6X_TURING          5065
+#define MACH_TYPE_MX6DL_TURING         5066
+#define MACH_TYPE_MX53_INDASH          5067
+#define MACH_TYPE_MX6Q_INDASH          5068
+#define MACH_TYPE_MX6DL_INDASH         5069
+#define MACH_TYPE_RTS_G6               5070
+#define MACH_TYPE_KA_TITAN             5071
+#define MACH_TYPE_CL_SOM_IMX7          5072
+#define MACH_TYPE_VVDN_MGSI_VSIS       5073
+#define MACH_TYPE_MX6Q_NANO            5074
+#define MACH_TYPE_PDU001               5075
+#define MACH_TYPE_CAB_PROYK            5076
+#define MACH_TYPE_KLIN                 5077
+#define MACH_TYPE_ENMAN_STEUERBOX      5078
+#define MACH_TYPE_LS_STINGRAY          5079
+#define MACH_TYPE_IPDU                 5080
+#define MACH_TYPE_LINDA                5081
+#define MACH_TYPE_MX6Q_OPENREX         5082
+#define MACH_TYPE_ON100                5083
+#define MACH_TYPE_EMINDS_RTU12         5084
+#define MACH_TYPE_EMINDS_AVL10         5085
+#define MACH_TYPE_MAIN_PLC_LME         5086
+#define MACH_TYPE_MSPX                 5087
+#define MACH_TYPE_CGW_300              5088
+#define MACH_TYPE_MX7D_CICADA          5089
+#define MACH_TYPE_VIRT2REAL_DM365      5090
+#define MACH_TYPE_DM365_VIRT2REAL      5091
+#define MACH_TYPE_H6073                5092
+#define MACH_TYPE_GTGATEWAY            5093
+#define MACH_TYPE_XARINA_STANDARD      5094
+#define MACH_TYPE_NOVASOMS             5095
+#define MACH_TYPE_NOVASOMP             5096
+#define MACH_TYPE_NOVASOMU             5097
+#define MACH_TYPE_MX6Q_MPBD            5098
+#define MACH_TYPE_NCR_1930             5099
+#define MACH_TYPE_UAP301               5100
+#define MACH_TYPE_URT02                5101
+#define MACH_TYPE_ATC8                 5102
+#define MACH_TYPE_IOT_GATEWAY          5103
+#define MACH_TYPE_HSM_PHOENIX          5104
+#define MACH_TYPE_MISSOURI             5105
+#define MACH_TYPE_REMARKABLE           5106
+#define MACH_TYPE_FA0113               5107
+#define MACH_TYPE_INNOVA_STATNETTAWM   5108
+#define MACH_TYPE_TEGRA3               5109
+#define MACH_TYPE_MALI400              5110
+#define MACH_TYPE_MALI450              5111
+#define MACH_TYPE_NASM25               5112
+#define MACH_TYPE_TOMATO               5113
+#define MACH_TYPE_OMAP3_MRC3D          5114
+#endif
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
new file mode 100644
index 0000000..bb33b4b
--- /dev/null
+++ b/arch/arm/include/asm/macro.h
@@ -0,0 +1,337 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/asm-arm/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ */
+
+#ifndef __ASM_ARM_MACRO_H__
+#define __ASM_ARM_MACRO_H__
+
+#ifdef CONFIG_ARM64
+#include <asm/system.h>
+#endif
+
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to any address.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any ARM architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro	write32, addr, data
+	ldr	r4, =\addr
+	ldr	r5, =\data
+	str	r5, [r4]
+.endm
+
+.macro	write16, addr, data
+	ldr	r4, =\addr
+	ldrh	r5, =\data
+	strh	r5, [r4]
+.endm
+
+.macro	write8, addr, data
+	ldr	r4, =\addr
+	ldrb	r5, =\data
+	strb	r5, [r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any ARM architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro	wait_timer, time
+	ldr	r4, =\time
+1:
+	nop
+	subs	r4, r4, #1
+	bcs	1b
+.endm
+
+#ifdef CONFIG_ARM64
+/*
+ * Register aliases.
+ */
+lr	.req	x30
+
+/*
+ * Branch according to exception level
+ */
+.macro	switch_el, xreg, el3_label, el2_label, el1_label
+	mrs	\xreg, CurrentEL
+	cmp	\xreg, 0xc
+	b.eq	\el3_label
+	cmp	\xreg, 0x8
+	b.eq	\el2_label
+	cmp	\xreg, 0x4
+	b.eq	\el1_label
+.endm
+
+/*
+ * Branch if current processor is a Cortex-A57 core.
+ */
+.macro	branch_if_a57_core, xreg, a57_label
+	mrs	\xreg, midr_el1
+	lsr	\xreg, \xreg, #4
+	and	\xreg, \xreg, #0x00000FFF
+	cmp	\xreg, #0xD07		/* Cortex-A57 MPCore processor. */
+	b.eq	\a57_label
+.endm
+
+/*
+ * Branch if current processor is a Cortex-A53 core.
+ */
+.macro	branch_if_a53_core, xreg, a53_label
+	mrs	\xreg, midr_el1
+	lsr	\xreg, \xreg, #4
+	and	\xreg, \xreg, #0x00000FFF
+	cmp	\xreg, #0xD03		/* Cortex-A53 MPCore processor. */
+	b.eq	\a53_label
+.endm
+
+/*
+ * Branch if current processor is a slave,
+ * choose processor with all zero affinity value as the master.
+ */
+.macro	branch_if_slave, xreg, slave_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+	/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
+	mrs	\xreg, mpidr_el1
+	tst	\xreg, #0xff		/* Test Affinity 0 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #8
+	tst	\xreg, #0xff		/* Test Affinity 1 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #8
+	tst	\xreg, #0xff		/* Test Affinity 2 */
+	b.ne	\slave_label
+	lsr	\xreg, \xreg, #16
+	tst	\xreg, #0xff		/* Test Affinity 3 */
+	b.ne	\slave_label
+#endif
+.endm
+
+/*
+ * Branch if current processor is a master,
+ * choose processor with all zero affinity value as the master.
+ */
+.macro	branch_if_master, xreg1, xreg2, master_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+	/* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
+	mrs	\xreg1, mpidr_el1
+	lsr	\xreg2, \xreg1, #32
+	lsl	\xreg2, \xreg2, #32
+	lsl	\xreg1, \xreg1, #40
+	lsr	\xreg1, \xreg1, #40
+	orr	\xreg1, \xreg1, \xreg2
+	cbz	\xreg1, \master_label
+#else
+	b 	\master_label
+#endif
+.endm
+
+/*
+ * Switch from EL3 to EL2 for ARMv8
+ * @ep:     kernel entry point
+ * @flag:   The execution state flag for lower exception
+ *          level, ES_TO_AARCH64 or ES_TO_AARCH32
+ * @tmp:    temporary register
+ *
+ * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
+ * For loading 64-bit OS, x0 is physical address to the FDT blob.
+ * They will be passed to the guest.
+ */
+.macro armv8_switch_to_el2_m, ep, flag, tmp
+	msr	cptr_el3, xzr		/* Disable coprocessor traps to EL3 */
+	mov	\tmp, #CPTR_EL2_RES1
+	msr	cptr_el2, \tmp		/* Disable coprocessor traps to EL2 */
+
+	/* Initialize Generic Timers */
+	msr	cntvoff_el2, xzr
+
+	/* Initialize SCTLR_EL2
+	 *
+	 * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
+	 * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
+	 * EE,WXN,I,SA,C,A,M to 0
+	 */
+	ldr	\tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\
+			SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\
+			SCTLR_EL2_SA_DIS | SCTLR_EL2_DCACHE_DIS |\
+			SCTLR_EL2_ALIGN_DIS | SCTLR_EL2_MMU_DIS)
+	msr	sctlr_el2, \tmp
+
+	mov	\tmp, sp
+	msr	sp_el2, \tmp		/* Migrate SP */
+	mrs	\tmp, vbar_el3
+	msr	vbar_el2, \tmp		/* Migrate VBAR */
+
+	/* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */
+	cmp	\flag, #ES_TO_AARCH32
+	b.eq	1f
+
+	/*
+	 * The next lower exception level is AArch64, 64bit EL2 | HCE |
+	 * RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+	 * and the SMD depends on requirements.
+	 */
+#ifdef CONFIG_ARMV8_PSCI
+	ldr	\tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
+			SCR_EL3_RES1 | SCR_EL3_NS_EN)
+#else
+	ldr	\tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
+			SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
+			SCR_EL3_NS_EN)
+#endif
+
+#ifdef CONFIG_ARMV8_EA_EL3_FIRST
+	orr	\tmp, \tmp, #SCR_EL3_EA_EN
+#endif
+	msr	scr_el3, \tmp
+
+	/* Return to the EL2_SP2 mode from EL3 */
+	ldr	\tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
+			SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
+			SPSR_EL_M_AARCH64 | SPSR_EL_M_EL2H)
+	msr	spsr_el3, \tmp
+	msr	elr_el3, \ep
+	eret
+
+1:
+	/*
+	 * The next lower exception level is AArch32, 32bit EL2 | HCE |
+	 * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+	 */
+	ldr	\tmp, =(SCR_EL3_RW_AARCH32 | SCR_EL3_HCE_EN |\
+			SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
+			SCR_EL3_NS_EN)
+	msr	scr_el3, \tmp
+
+	/* Return to AArch32 Hypervisor mode */
+	ldr     \tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
+			SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
+			SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
+			SPSR_EL_M_HYP)
+	msr	spsr_el3, \tmp
+	msr     elr_el3, \ep
+	eret
+.endm
+
+/*
+ * Switch from EL2 to EL1 for ARMv8
+ * @ep:     kernel entry point
+ * @flag:   The execution state flag for lower exception
+ *          level, ES_TO_AARCH64 or ES_TO_AARCH32
+ * @tmp:    temporary register
+ *
+ * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
+ * For loading 64-bit OS, x0 is physical address to the FDT blob.
+ * They will be passed to the guest.
+ */
+.macro armv8_switch_to_el1_m, ep, flag, tmp
+	/* Initialize Generic Timers */
+	mrs	\tmp, cnthctl_el2
+	/* Enable EL1 access to timers */
+	orr	\tmp, \tmp, #(CNTHCTL_EL2_EL1PCEN_EN |\
+		CNTHCTL_EL2_EL1PCTEN_EN)
+	msr	cnthctl_el2, \tmp
+	msr	cntvoff_el2, xzr
+
+	/* Initilize MPID/MPIDR registers */
+	mrs	\tmp, midr_el1
+	msr	vpidr_el2, \tmp
+	mrs	\tmp, mpidr_el1
+	msr	vmpidr_el2, \tmp
+
+	/* Disable coprocessor traps */
+	mov	\tmp, #CPTR_EL2_RES1
+	msr	cptr_el2, \tmp		/* Disable coprocessor traps to EL2 */
+	msr	hstr_el2, xzr		/* Disable coprocessor traps to EL2 */
+	mov	\tmp, #CPACR_EL1_FPEN_EN
+	msr	cpacr_el1, \tmp		/* Enable FP/SIMD at EL1 */
+
+	/* SCTLR_EL1 initialization
+	 *
+	 * setting RES1 bits (29,28,23,22,20,11) to 1
+	 * and RES0 bits (31,30,27,21,17,13,10,6) +
+	 * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
+	 * CP15BEN,SA0,SA,C,A,M to 0
+	 */
+	ldr	\tmp, =(SCTLR_EL1_RES1 | SCTLR_EL1_UCI_DIS |\
+			SCTLR_EL1_EE_LE | SCTLR_EL1_WXN_DIS |\
+			SCTLR_EL1_NTWE_DIS | SCTLR_EL1_NTWI_DIS |\
+			SCTLR_EL1_UCT_DIS | SCTLR_EL1_DZE_DIS |\
+			SCTLR_EL1_ICACHE_DIS | SCTLR_EL1_UMA_DIS |\
+			SCTLR_EL1_SED_EN | SCTLR_EL1_ITD_EN |\
+			SCTLR_EL1_CP15BEN_DIS | SCTLR_EL1_SA0_DIS |\
+			SCTLR_EL1_SA_DIS | SCTLR_EL1_DCACHE_DIS |\
+			SCTLR_EL1_ALIGN_DIS | SCTLR_EL1_MMU_DIS)
+	msr	sctlr_el1, \tmp
+
+	mov	\tmp, sp
+	msr	sp_el1, \tmp		/* Migrate SP */
+	mrs	\tmp, vbar_el2
+	msr	vbar_el1, \tmp		/* Migrate VBAR */
+
+	/* Check switch to AArch64 EL1 or AArch32 Supervisor mode */
+	cmp	\flag, #ES_TO_AARCH32
+	b.eq	1f
+
+	/* Initialize HCR_EL2 */
+	ldr	\tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
+	msr	hcr_el2, \tmp
+
+	/* Return to the EL1_SP1 mode from EL2 */
+	ldr	\tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
+			SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
+			SPSR_EL_M_AARCH64 | SPSR_EL_M_EL1H)
+	msr	spsr_el2, \tmp
+	msr     elr_el2, \ep
+	eret
+
+1:
+	/* Initialize HCR_EL2 */
+	ldr	\tmp, =(HCR_EL2_RW_AARCH32 | HCR_EL2_HCD_DIS)
+	msr	hcr_el2, \tmp
+
+	/* Return to AArch32 Supervisor mode from EL2 */
+	ldr	\tmp, =(SPSR_EL_END_LE | SPSR_EL_ASYN_MASK |\
+			SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
+			SPSR_EL_T_A32 | SPSR_EL_M_AARCH32 |\
+			SPSR_EL_M_SVC)
+	msr     spsr_el2, \tmp
+	msr     elr_el2, \ep
+	eret
+.endm
+
+#if defined(CONFIG_GICV3)
+.macro gic_wait_for_interrupt_m xreg1
+0 :	wfi
+	mrs     \xreg1, ICC_IAR1_EL1
+	msr     ICC_EOIR1_EL1, \xreg1
+	cbnz    \xreg1, 0b
+.endm
+#elif defined(CONFIG_GICV2)
+.macro gic_wait_for_interrupt_m xreg1, wreg2
+0 :	wfi
+	ldr     \wreg2, [\xreg1, GICC_AIAR]
+	str     \wreg2, [\xreg1, GICC_AEOIR]
+	and	\wreg2, \wreg2, #0x3ff
+	cbnz    \wreg2, 0b
+.endm
+#endif
+
+#endif /* CONFIG_ARM64 */
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H__ */
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
new file mode 100644
index 0000000..6b46078
--- /dev/null
+++ b/arch/arm/include/asm/memory.h
@@ -0,0 +1,136 @@
+/*
+ *  linux/include/asm-arm/memory.h
+ *
+ *  Copyright (C) 2000-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Note: this file should not be included by non-asm/.h files
+ */
+#ifndef __ASM_ARM_MEMORY_H
+#define __ASM_ARM_MEMORY_H
+
+#if 0	/* XXX###XXX */
+
+#include <asm/arch/memory.h>
+
+/*
+ * PFNs are used to describe any physical page; this means
+ * PFN 0 == physical address 0.
+ *
+ * This is the PFN of the first RAM page in the kernel
+ * direct-mapped view.  We assume this is the first page
+ * of RAM in the mem_map as well.
+ */
+#define PHYS_PFN_OFFSET	(PHYS_OFFSET >> PAGE_SHIFT)
+
+/*
+ * These are *only* valid on the kernel direct mapped RAM memory.
+ */
+static inline unsigned long virt_to_phys(void *x)
+{
+	return __virt_to_phys((unsigned long)(x));
+}
+
+static inline void *phys_to_virt(unsigned long x)
+{
+	return (void *)(__phys_to_virt((unsigned long)(x)));
+}
+
+#define __pa(x)			__virt_to_phys((unsigned long)(x))
+#define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
+
+/*
+ * Virtual <-> DMA view memory address translations
+ * Again, these are *only* valid on the kernel direct mapped RAM
+ * memory.  Use of these is *deprecated*.
+ */
+#define virt_to_bus(x)		(__virt_to_bus((unsigned long)(x)))
+#define bus_to_virt(x)		((void *)(__bus_to_virt((unsigned long)(x))))
+
+/*
+ * Conversion between a struct page and a physical address.
+ *
+ * Note: when converting an unknown physical address to a
+ * struct page, the resulting pointer must be validated
+ * using VALID_PAGE().  It must return an invalid struct page
+ * for any physical address not corresponding to a system
+ * RAM address.
+ *
+ *  page_to_pfn(page)	convert a struct page * to a PFN number
+ *  pfn_to_page(pfn)	convert a _valid_ PFN number to struct page *
+ *  pfn_valid(pfn)	indicates whether a PFN number is valid
+ *
+ *  virt_to_page(k)	convert a _valid_ virtual address to struct page *
+ *  virt_addr_valid(k)	indicates whether a virtual address is valid
+ */
+#ifndef CONFIG_DISCONTIGMEM
+
+#define page_to_pfn(page)	(((page) - mem_map) + PHYS_PFN_OFFSET)
+#define pfn_to_page(pfn)	((mem_map + (pfn)) - PHYS_PFN_OFFSET)
+#define pfn_valid(pfn)		((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
+
+#define virt_to_page(kaddr)	(pfn_to_page(__pa(kaddr) >> PAGE_SHIFT))
+#define virt_addr_valid(kaddr)	((kaddr) >= PAGE_OFFSET && (kaddr) < (unsigned long)high_memory)
+
+#define PHYS_TO_NID(addr)	(0)
+
+#define VALID_PAGE(page)	((page - mem_map) < max_mapnr)
+
+#else
+
+/*
+ * This is more complex.  We have a set of mem_map arrays spread
+ * around in memory.
+ */
+#define page_to_pfn(page)					\
+	(((page) - page_zone(page)->zone_mem_map)		\
+	  + (page_zone(page)->zone_start_paddr >> PAGE_SHIFT))
+
+#define pfn_to_page(pfn)					\
+	(PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT))
+
+#define pfn_valid(pfn)						\
+  ({								\
+	unsigned int node = PFN_TO_NID(pfn);			\
+	struct pglist_data *nd = NODE_DATA(node);		\
+	((node < NR_NODES) &&					\
+	 ((pfn - (nd->node_start_paddr >> PAGE_SHIFT)) < nd->node_size));\
+   })
+
+#define virt_to_page(kaddr)					\
+	(ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
+
+#define virt_addr_valid(kaddr)	(KVADDR_TO_NID(kaddr) < NR_NODES)
+
+/*
+ * Common discontigmem stuff.
+ *  PHYS_TO_NID is used by the ARM kernel/setup.c
+ */
+#define PHYS_TO_NID(addr)	PFN_TO_NID((addr) >> PAGE_SHIFT)
+
+/*
+ * 2.4 compatibility
+ *
+ * VALID_PAGE returns a non-zero value if given page pointer is valid.
+ * This assumes all node's mem_maps are stored within the node they
+ * refer to.  This is actually inherently buggy.
+ */
+#define VALID_PAGE(page) \
+({ unsigned int node = KVADDR_TO_NID(page); \
+   ((node < NR_NODES) && \
+     ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size)); \
+})
+
+#endif
+
+/*
+ * We should really eliminate virt_to_bus() here - it's deprecated.
+ */
+#define page_to_bus(page)	(virt_to_bus(page_address(page)))
+
+#endif	/* XXX###XXX */
+
+#endif	/* __ASM_ARM_MEMORY_H */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
new file mode 100644
index 0000000..54b7cd1
--- /dev/null
+++ b/arch/arm/include/asm/omap_common.h
@@ -0,0 +1,836 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ */
+#ifndef	_OMAP_COMMON_H_
+#define	_OMAP_COMMON_H_
+
+#ifndef __ASSEMBLY__
+
+#include <common.h>
+
+#define NUM_SYS_CLKS	7
+
+struct prcm_regs {
+	/* cm1.ckgen */
+	u32 cm_clksel_core;
+	u32 cm_clksel_abe;
+	u32 cm_dll_ctrl;
+	u32 cm_clkmode_dpll_core;
+	u32 cm_idlest_dpll_core;
+	u32 cm_autoidle_dpll_core;
+	u32 cm_clksel_dpll_core;
+	u32 cm_div_m2_dpll_core;
+	u32 cm_div_m3_dpll_core;
+	u32 cm_div_h11_dpll_core;
+	u32 cm_div_h12_dpll_core;
+	u32 cm_div_h13_dpll_core;
+	u32 cm_div_h14_dpll_core;
+	u32 cm_div_h21_dpll_core;
+	u32 cm_div_h24_dpll_core;
+	u32 cm_ssc_deltamstep_dpll_core;
+	u32 cm_ssc_modfreqdiv_dpll_core;
+	u32 cm_emu_override_dpll_core;
+	u32 cm_div_h22_dpllcore;
+	u32 cm_div_h23_dpll_core;
+	u32 cm_clkmode_dpll_mpu;
+	u32 cm_idlest_dpll_mpu;
+	u32 cm_autoidle_dpll_mpu;
+	u32 cm_clksel_dpll_mpu;
+	u32 cm_div_m2_dpll_mpu;
+	u32 cm_ssc_deltamstep_dpll_mpu;
+	u32 cm_ssc_modfreqdiv_dpll_mpu;
+	u32 cm_bypclk_dpll_mpu;
+	u32 cm_clkmode_dpll_iva;
+	u32 cm_idlest_dpll_iva;
+	u32 cm_autoidle_dpll_iva;
+	u32 cm_clksel_dpll_iva;
+	u32 cm_div_h11_dpll_iva;
+	u32 cm_div_h12_dpll_iva;
+	u32 cm_ssc_deltamstep_dpll_iva;
+	u32 cm_ssc_modfreqdiv_dpll_iva;
+	u32 cm_bypclk_dpll_iva;
+	u32 cm_clkmode_dpll_abe;
+	u32 cm_idlest_dpll_abe;
+	u32 cm_autoidle_dpll_abe;
+	u32 cm_clksel_dpll_abe;
+	u32 cm_div_m2_dpll_abe;
+	u32 cm_div_m3_dpll_abe;
+	u32 cm_ssc_deltamstep_dpll_abe;
+	u32 cm_ssc_modfreqdiv_dpll_abe;
+	u32 cm_clkmode_dpll_ddrphy;
+	u32 cm_idlest_dpll_ddrphy;
+	u32 cm_autoidle_dpll_ddrphy;
+	u32 cm_clksel_dpll_ddrphy;
+	u32 cm_div_m2_dpll_ddrphy;
+	u32 cm_div_h11_dpll_ddrphy;
+	u32 cm_div_h12_dpll_ddrphy;
+	u32 cm_div_h13_dpll_ddrphy;
+	u32 cm_ssc_deltamstep_dpll_ddrphy;
+	u32 cm_clkmode_dpll_dsp;
+	u32 cm_shadow_freq_config1;
+	u32 cm_clkmode_dpll_gmac;
+	u32 cm_mpu_mpu_clkctrl;
+
+	/* cm1.dsp */
+	u32 cm_dsp_clkstctrl;
+	u32 cm_dsp_dsp_clkctrl;
+
+	/* cm1.abe */
+	u32 cm1_abe_clkstctrl;
+	u32 cm1_abe_l4abe_clkctrl;
+	u32 cm1_abe_aess_clkctrl;
+	u32 cm1_abe_pdm_clkctrl;
+	u32 cm1_abe_dmic_clkctrl;
+	u32 cm1_abe_mcasp_clkctrl;
+	u32 cm1_abe_mcbsp1_clkctrl;
+	u32 cm1_abe_mcbsp2_clkctrl;
+	u32 cm1_abe_mcbsp3_clkctrl;
+	u32 cm1_abe_slimbus_clkctrl;
+	u32 cm1_abe_timer5_clkctrl;
+	u32 cm1_abe_timer6_clkctrl;
+	u32 cm1_abe_timer7_clkctrl;
+	u32 cm1_abe_timer8_clkctrl;
+	u32 cm1_abe_wdt3_clkctrl;
+
+	/* cm2.ckgen */
+	u32 cm_clksel_mpu_m3_iss_root;
+	u32 cm_clksel_usb_60mhz;
+	u32 cm_scale_fclk;
+	u32 cm_core_dvfs_perf1;
+	u32 cm_core_dvfs_perf2;
+	u32 cm_core_dvfs_perf3;
+	u32 cm_core_dvfs_perf4;
+	u32 cm_core_dvfs_current;
+	u32 cm_iva_dvfs_perf_tesla;
+	u32 cm_iva_dvfs_perf_ivahd;
+	u32 cm_iva_dvfs_perf_abe;
+	u32 cm_iva_dvfs_current;
+	u32 cm_clkmode_dpll_per;
+	u32 cm_idlest_dpll_per;
+	u32 cm_autoidle_dpll_per;
+	u32 cm_clksel_dpll_per;
+	u32 cm_div_m2_dpll_per;
+	u32 cm_div_m3_dpll_per;
+	u32 cm_div_h11_dpll_per;
+	u32 cm_div_h12_dpll_per;
+	u32 cm_div_h13_dpll_per;
+	u32 cm_div_h14_dpll_per;
+	u32 cm_ssc_deltamstep_dpll_per;
+	u32 cm_ssc_modfreqdiv_dpll_per;
+	u32 cm_emu_override_dpll_per;
+	u32 cm_clkmode_dpll_usb;
+	u32 cm_idlest_dpll_usb;
+	u32 cm_autoidle_dpll_usb;
+	u32 cm_clksel_dpll_usb;
+	u32 cm_div_m2_dpll_usb;
+	u32 cm_ssc_deltamstep_dpll_usb;
+	u32 cm_ssc_modfreqdiv_dpll_usb;
+	u32 cm_clkdcoldo_dpll_usb;
+	u32 cm_clkmode_dpll_pcie_ref;
+	u32 cm_clkmode_apll_pcie;
+	u32 cm_idlest_apll_pcie;
+	u32 cm_div_m2_apll_pcie;
+	u32 cm_clkvcoldo_apll_pcie;
+	u32 cm_clkmode_dpll_unipro;
+	u32 cm_idlest_dpll_unipro;
+	u32 cm_autoidle_dpll_unipro;
+	u32 cm_clksel_dpll_unipro;
+	u32 cm_div_m2_dpll_unipro;
+	u32 cm_ssc_deltamstep_dpll_unipro;
+	u32 cm_ssc_modfreqdiv_dpll_unipro;
+	u32 cm_coreaon_usb_phy1_core_clkctrl;
+	u32 cm_coreaon_usb_phy2_core_clkctrl;
+	u32 cm_coreaon_usb_phy3_core_clkctrl;
+	u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
+
+	/* cm2.core */
+	u32 cm_coreaon_bandgap_clkctrl;
+	u32 cm_coreaon_io_srcomp_clkctrl;
+	u32 cm_l3_1_clkstctrl;
+	u32 cm_l3_1_dynamicdep;
+	u32 cm_l3_1_l3_1_clkctrl;
+	u32 cm_l3_2_clkstctrl;
+	u32 cm_l3_2_dynamicdep;
+	u32 cm_l3_2_l3_2_clkctrl;
+	u32 cm_l3_gpmc_clkctrl;
+	u32 cm_l3_2_ocmc_ram_clkctrl;
+	u32 cm_mpu_m3_clkstctrl;
+	u32 cm_mpu_m3_staticdep;
+	u32 cm_mpu_m3_dynamicdep;
+	u32 cm_mpu_m3_mpu_m3_clkctrl;
+	u32 cm_sdma_clkstctrl;
+	u32 cm_sdma_staticdep;
+	u32 cm_sdma_dynamicdep;
+	u32 cm_sdma_sdma_clkctrl;
+	u32 cm_memif_clkstctrl;
+	u32 cm_memif_dmm_clkctrl;
+	u32 cm_memif_emif_fw_clkctrl;
+	u32 cm_memif_emif_1_clkctrl;
+	u32 cm_memif_emif_2_clkctrl;
+	u32 cm_memif_dll_clkctrl;
+	u32 cm_memif_emif_h1_clkctrl;
+	u32 cm_memif_emif_h2_clkctrl;
+	u32 cm_memif_dll_h_clkctrl;
+	u32 cm_c2c_clkstctrl;
+	u32 cm_c2c_staticdep;
+	u32 cm_c2c_dynamicdep;
+	u32 cm_c2c_sad2d_clkctrl;
+	u32 cm_c2c_modem_icr_clkctrl;
+	u32 cm_c2c_sad2d_fw_clkctrl;
+	u32 cm_l4cfg_clkstctrl;
+	u32 cm_l4cfg_dynamicdep;
+	u32 cm_l4cfg_l4_cfg_clkctrl;
+	u32 cm_l4cfg_hw_sem_clkctrl;
+	u32 cm_l4cfg_mailbox_clkctrl;
+	u32 cm_l4cfg_sar_rom_clkctrl;
+	u32 cm_l3instr_clkstctrl;
+	u32 cm_l3instr_l3_3_clkctrl;
+	u32 cm_l3instr_l3_instr_clkctrl;
+	u32 cm_l3instr_intrconn_wp1_clkctrl;
+
+	/* cm2.ivahd */
+	u32 cm_ivahd_clkstctrl;
+	u32 cm_ivahd_ivahd_clkctrl;
+	u32 cm_ivahd_sl2_clkctrl;
+
+	/* cm2.cam */
+	u32 cm_cam_clkstctrl;
+	u32 cm_cam_iss_clkctrl;
+	u32 cm_cam_fdif_clkctrl;
+	u32 cm_cam_vip1_clkctrl;
+	u32 cm_cam_vip2_clkctrl;
+	u32 cm_cam_vip3_clkctrl;
+	u32 cm_cam_lvdsrx_clkctrl;
+	u32 cm_cam_csi1_clkctrl;
+	u32 cm_cam_csi2_clkctrl;
+
+	/* cm2.dss */
+	u32 cm_dss_clkstctrl;
+	u32 cm_dss_dss_clkctrl;
+
+	/* cm2.sgx */
+	u32 cm_sgx_clkstctrl;
+	u32 cm_sgx_sgx_clkctrl;
+
+	/* cm2.l3init */
+	u32 cm_l3init_clkstctrl;
+
+	/* cm2.l3init */
+	u32 cm_l3init_hsmmc1_clkctrl;
+	u32 cm_l3init_hsmmc2_clkctrl;
+	u32 cm_l3init_hsi_clkctrl;
+	u32 cm_l3init_hsusbhost_clkctrl;
+	u32 cm_l3init_hsusbotg_clkctrl;
+	u32 cm_l3init_hsusbtll_clkctrl;
+	u32 cm_l3init_p1500_clkctrl;
+	u32 cm_l3init_sata_clkctrl;
+	u32 cm_l3init_fsusb_clkctrl;
+	u32 cm_l3init_ocp2scp1_clkctrl;
+	u32 cm_l3init_ocp2scp3_clkctrl;
+	u32 cm_l3init_usb_otg_ss1_clkctrl;
+	u32 cm_l3init_usb_otg_ss2_clkctrl;
+
+	u32 prm_irqstatus_mpu;
+	u32 prm_irqstatus_mpu_2;
+
+	/* cm2.l4per */
+	u32 cm_l4per_clkstctrl;
+	u32 cm_l4per_dynamicdep;
+	u32 cm_l4per_adc_clkctrl;
+	u32 cm_l4per_gptimer10_clkctrl;
+	u32 cm_l4per_gptimer11_clkctrl;
+	u32 cm_l4per_gptimer2_clkctrl;
+	u32 cm_l4per_gptimer3_clkctrl;
+	u32 cm_l4per_gptimer4_clkctrl;
+	u32 cm_l4per_gptimer9_clkctrl;
+	u32 cm_l4per_elm_clkctrl;
+	u32 cm_l4per_gpio2_clkctrl;
+	u32 cm_l4per_gpio3_clkctrl;
+	u32 cm_l4per_gpio4_clkctrl;
+	u32 cm_l4per_gpio5_clkctrl;
+	u32 cm_l4per_gpio6_clkctrl;
+	u32 cm_l4per_hdq1w_clkctrl;
+	u32 cm_l4per_hecc1_clkctrl;
+	u32 cm_l4per_hecc2_clkctrl;
+	u32 cm_l4per_i2c1_clkctrl;
+	u32 cm_l4per_i2c2_clkctrl;
+	u32 cm_l4per_i2c3_clkctrl;
+	u32 cm_l4per_i2c4_clkctrl;
+	u32 cm_l4per_l4per_clkctrl;
+	u32 cm_l4per_mcasp2_clkctrl;
+	u32 cm_l4per_mcasp3_clkctrl;
+	u32 cm_l4per_mgate_clkctrl;
+	u32 cm_l4per_mcspi1_clkctrl;
+	u32 cm_l4per_mcspi2_clkctrl;
+	u32 cm_l4per_mcspi3_clkctrl;
+	u32 cm_l4per_mcspi4_clkctrl;
+	u32 cm_l4per_gpio7_clkctrl;
+	u32 cm_l4per_gpio8_clkctrl;
+	u32 cm_l4per_mmcsd3_clkctrl;
+	u32 cm_l4per_mmcsd4_clkctrl;
+	u32 cm_l4per_msprohg_clkctrl;
+	u32 cm_l4per_slimbus2_clkctrl;
+	u32 cm_l4per_qspi_clkctrl;
+	u32 cm_l4per_uart1_clkctrl;
+	u32 cm_l4per_uart2_clkctrl;
+	u32 cm_l4per_uart3_clkctrl;
+	u32 cm_l4per_uart4_clkctrl;
+	u32 cm_l4per_mmcsd5_clkctrl;
+	u32 cm_l4per_i2c5_clkctrl;
+	u32 cm_l4per_uart5_clkctrl;
+	u32 cm_l4per_uart6_clkctrl;
+	u32 cm_l4sec_clkstctrl;
+	u32 cm_l4sec_staticdep;
+	u32 cm_l4sec_dynamicdep;
+	u32 cm_l4sec_aes1_clkctrl;
+	u32 cm_l4sec_aes2_clkctrl;
+	u32 cm_l4sec_des3des_clkctrl;
+	u32 cm_l4sec_pkaeip29_clkctrl;
+	u32 cm_l4sec_rng_clkctrl;
+	u32 cm_l4sec_sha2md51_clkctrl;
+	u32 cm_l4sec_cryptodma_clkctrl;
+
+	/* l4 wkup regs */
+	u32 cm_abe_pll_ref_clksel;
+	u32 cm_sys_clksel;
+	u32 cm_abe_pll_sys_clksel;
+	u32 cm_wkup_clkstctrl;
+	u32 cm_wkup_l4wkup_clkctrl;
+	u32 cm_wkup_wdtimer1_clkctrl;
+	u32 cm_wkup_wdtimer2_clkctrl;
+	u32 cm_wkup_gpio1_clkctrl;
+	u32 cm_wkup_gptimer1_clkctrl;
+	u32 cm_wkup_gptimer12_clkctrl;
+	u32 cm_wkup_synctimer_clkctrl;
+	u32 cm_wkup_usim_clkctrl;
+	u32 cm_wkup_sarram_clkctrl;
+	u32 cm_wkup_keyboard_clkctrl;
+	u32 cm_wkup_rtc_clkctrl;
+	u32 cm_wkup_bandgap_clkctrl;
+	u32 cm_wkupaon_scrm_clkctrl;
+	u32 cm_wkupaon_io_srcomp_clkctrl;
+	u32 prm_rstctrl;
+	u32 prm_rstst;
+	u32 prm_rsttime;
+	u32 prm_io_pmctrl;
+	u32 prm_vc_val_bypass;
+	u32 prm_vc_cfg_i2c_mode;
+	u32 prm_vc_cfg_i2c_clk;
+	u32 prm_abbldo_mpu_setup;
+	u32 prm_abbldo_mpu_ctrl;
+	u32 prm_abbldo_mm_setup;
+	u32 prm_abbldo_mm_ctrl;
+	u32 prm_abbldo_iva_setup;
+	u32 prm_abbldo_iva_ctrl;
+	u32 prm_abbldo_eve_setup;
+	u32 prm_abbldo_eve_ctrl;
+	u32 prm_abbldo_gpu_setup;
+	u32 prm_abbldo_gpu_ctrl;
+
+	u32 cm_div_m4_dpll_core;
+	u32 cm_div_m5_dpll_core;
+	u32 cm_div_m6_dpll_core;
+	u32 cm_div_m7_dpll_core;
+	u32 cm_div_m4_dpll_iva;
+	u32 cm_div_m5_dpll_iva;
+	u32 cm_div_m4_dpll_ddrphy;
+	u32 cm_div_m5_dpll_ddrphy;
+	u32 cm_div_m6_dpll_ddrphy;
+	u32 cm_div_m4_dpll_per;
+	u32 cm_div_m5_dpll_per;
+	u32 cm_div_m6_dpll_per;
+	u32 cm_div_m7_dpll_per;
+	u32 cm_l3instr_intrconn_wp1_clkct;
+	u32 cm_l3init_usbphy_clkctrl;
+	u32 cm_l4per_mcbsp4_clkctrl;
+	u32 prm_vc_cfg_channel;
+
+	/* SCRM stuff, used by some boards */
+	u32 scrm_auxclk0;
+	u32 scrm_auxclk1;
+
+	/* GMAC Clk Ctrl */
+	u32 cm_gmac_gmac_clkctrl;
+	u32 cm_gmac_clkstctrl;
+
+	/* IPU */
+	u32 cm_ipu_clkstctrl;
+	u32 cm_ipu_i2c5_clkctrl;
+
+	/*l3main1 edma*/
+	u32 cm_l3main1_tptc1_clkctrl;
+	u32 cm_l3main1_tptc2_clkctrl;
+};
+
+struct omap_sys_ctrl_regs {
+	u32 control_status;
+	u32 control_core_mac_id_0_lo;
+	u32 control_core_mac_id_0_hi;
+	u32 control_core_mac_id_1_lo;
+	u32 control_core_mac_id_1_hi;
+	u32 control_phy_power_usb;
+	u32 control_core_mmr_lock1;
+	u32 control_core_mmr_lock2;
+	u32 control_core_mmr_lock3;
+	u32 control_core_mmr_lock4;
+	u32 control_core_mmr_lock5;
+	u32 control_core_control_io1;
+	u32 control_core_control_io2;
+	u32 control_id_code;
+	u32 control_std_fuse_die_id_0;
+	u32 control_std_fuse_die_id_1;
+	u32 control_std_fuse_die_id_2;
+	u32 control_std_fuse_die_id_3;
+	u32 control_std_fuse_opp_bgap;
+	u32 control_ldosram_iva_voltage_ctrl;
+	u32 control_ldosram_mpu_voltage_ctrl;
+	u32 control_ldosram_core_voltage_ctrl;
+	u32 control_usbotghs_ctrl;
+	u32 control_phy_power_sata;
+	u32 control_padconf_core_base;
+	u32 control_paconf_global;
+	u32 control_paconf_mode;
+	u32 control_smart1io_padconf_0;
+	u32 control_smart1io_padconf_1;
+	u32 control_smart1io_padconf_2;
+	u32 control_smart2io_padconf_0;
+	u32 control_smart2io_padconf_1;
+	u32 control_smart2io_padconf_2;
+	u32 control_smart3io_padconf_0;
+	u32 control_smart3io_padconf_1;
+	u32 control_pbias;
+	u32 control_i2c_0;
+	u32 control_camera_rx;
+	u32 control_hdmi_tx_phy;
+	u32 control_uniportm;
+	u32 control_dsiphy;
+	u32 control_mcbsplp;
+	u32 control_usb2phycore;
+	u32 control_hdmi_1;
+	u32 control_hsi;
+	u32 control_ddr3ch1_0;
+	u32 control_ddr3ch2_0;
+	u32 control_ddrch1_0;
+	u32 control_ddrch1_1;
+	u32 control_ddrch2_0;
+	u32 control_ddrch2_1;
+	u32 control_lpddr2ch1_0;
+	u32 control_lpddr2ch1_1;
+	u32 control_ddrio_0;
+	u32 control_ddrio_1;
+	u32 control_ddrio_2;
+	u32 control_ddr_control_ext_0;
+	u32 control_lpddr2io1_0;
+	u32 control_lpddr2io1_1;
+	u32 control_lpddr2io1_2;
+	u32 control_lpddr2io1_3;
+	u32 control_lpddr2io2_0;
+	u32 control_lpddr2io2_1;
+	u32 control_lpddr2io2_2;
+	u32 control_lpddr2io2_3;
+	u32 control_hyst_1;
+	u32 control_usbb_hsic_control;
+	u32 control_c2c;
+	u32 control_core_control_spare_rw;
+	u32 control_core_control_spare_r;
+	u32 control_core_control_spare_r_c0;
+	u32 control_srcomp_north_side;
+	u32 control_srcomp_south_side;
+	u32 control_srcomp_east_side;
+	u32 control_srcomp_west_side;
+	u32 control_srcomp_code_latch;
+	u32 control_pbiaslite;
+	u32 control_port_emif1_sdram_config;
+	u32 control_port_emif1_lpddr2_nvm_config;
+	u32 control_port_emif2_sdram_config;
+	u32 control_emif1_sdram_config_ext;
+	u32 control_emif2_sdram_config_ext;
+	u32 control_wkup_ldovbb_mpu_voltage_ctrl;
+	u32 control_wkup_ldovbb_mm_voltage_ctrl;
+	u32 control_wkup_ldovbb_iva_voltage_ctrl;
+	u32 control_wkup_ldovbb_eve_voltage_ctrl;
+	u32 control_wkup_ldovbb_gpu_voltage_ctrl;
+	u32 control_smart1nopmio_padconf_0;
+	u32 control_smart1nopmio_padconf_1;
+	u32 control_padconf_mode;
+	u32 control_xtal_oscillator;
+	u32 control_i2c_2;
+	u32 control_ckobuffer;
+	u32 control_wkup_control_spare_rw;
+	u32 control_wkup_control_spare_r;
+	u32 control_wkup_control_spare_r_c0;
+	u32 control_srcomp_east_side_wkup;
+	u32 control_efuse_1;
+	u32 control_efuse_2;
+	u32 control_efuse_3;
+	u32 control_efuse_4;
+	u32 control_efuse_5;
+	u32 control_efuse_6;
+	u32 control_efuse_7;
+	u32 control_efuse_8;
+	u32 control_efuse_9;
+	u32 control_efuse_10;
+	u32 control_efuse_11;
+	u32 control_efuse_12;
+	u32 control_efuse_13;
+	u32 control_padconf_wkup_base;
+	u32 iodelay_config_base;
+	u32 ctrl_core_sma_sw_0;
+	u32 ctrl_core_sma_sw_1;
+};
+
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
+struct dpll_params {
+	u32 m;
+	u32 n;
+	s8 m2;
+	s8 m3;
+	s8 m4_h11;
+	s8 m5_h12;
+	s8 m6_h13;
+	s8 m7_h14;
+	s8 h21;
+	s8 h22;
+	s8 h23;
+	s8 h24;
+};
+
+struct dpll_regs {
+	u32 cm_clkmode_dpll;
+	u32 cm_idlest_dpll;
+	u32 cm_autoidle_dpll;
+	u32 cm_clksel_dpll;
+	u32 cm_div_m2_dpll;
+	u32 cm_div_m3_dpll;
+	u32 cm_div_m4_h11_dpll;
+	u32 cm_div_m5_h12_dpll;
+	u32 cm_div_m6_h13_dpll;
+	u32 cm_div_m7_h14_dpll;
+	u32 reserved[2];
+	u32 cm_div_h21_dpll;
+	u32 cm_div_h22_dpll;
+	u32 cm_div_h23_dpll;
+	u32 cm_div_h24_dpll;
+};
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
+
+struct dplls {
+	const struct dpll_params *mpu;
+	const struct dpll_params *core;
+	const struct dpll_params *per;
+	const struct dpll_params *abe;
+	const struct dpll_params *iva;
+	const struct dpll_params *usb;
+	const struct dpll_params *ddr;
+	const struct dpll_params *gmac;
+};
+
+struct pmic_data {
+	u32 base_offset;
+	u32 step;
+	u32 start_code;
+	unsigned gpio;
+	int gpio_en;
+	u32 i2c_slave_addr;
+	void (*pmic_bus_init)(void);
+	int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
+};
+
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
+enum {
+	OPP_LOW,
+	OPP_NOM,
+	OPP_OD,
+	OPP_HIGH,
+	NUM_OPPS,
+};
+
+/**
+ * struct volts_efuse_data - efuse definition for voltage
+ * @reg:	register address for efuse
+ * @reg_bits:	Number of bits in a register address, mandatory.
+ */
+struct volts_efuse_data {
+	u32 reg[NUM_OPPS];
+	u8 reg_bits;
+};
+
+struct volts {
+	u32 value[NUM_OPPS];
+	u32 addr;
+	struct volts_efuse_data efuse;
+	struct pmic_data *pmic;
+
+	u32 abb_tx_done_mask;
+};
+
+enum {
+	VOLT_MPU,
+	VOLT_CORE,
+	VOLT_MM,
+	VOLT_GPU,
+	VOLT_EVE,
+	VOLT_IVA,
+	NUM_VOLT_RAILS,
+};
+
+struct vcores_data {
+	struct volts mpu;
+	struct volts core;
+	struct volts mm;
+	struct volts gpu;
+	struct volts eve;
+	struct volts iva;
+};
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
+
+extern struct prcm_regs const **prcm;
+extern struct prcm_regs const omap5_es1_prcm;
+extern struct prcm_regs const omap5_es2_prcm;
+extern struct prcm_regs const omap4_prcm;
+extern struct prcm_regs const dra7xx_prcm;
+extern struct dplls const **dplls_data;
+extern struct dplls dra7xx_dplls;
+extern struct dplls dra72x_dplls;
+extern struct dplls dra76x_dplls;
+extern struct vcores_data const **omap_vcores;
+extern const u32 sys_clk_array[8];
+extern struct omap_sys_ctrl_regs const **ctrl;
+extern struct omap_sys_ctrl_regs const am33xx_ctrl;
+extern struct omap_sys_ctrl_regs const omap3_ctrl;
+extern struct omap_sys_ctrl_regs const omap4_ctrl;
+extern struct omap_sys_ctrl_regs const omap5_ctrl;
+extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
+
+extern struct pmic_data tps659038;
+extern struct pmic_data lp8733;
+extern struct pmic_data lp87565;
+
+void hw_data_init(void);
+
+const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
+const struct dpll_params *get_core_dpll_params(struct dplls const *);
+const struct dpll_params *get_per_dpll_params(struct dplls const *);
+const struct dpll_params *get_iva_dpll_params(struct dplls const *);
+const struct dpll_params *get_usb_dpll_params(struct dplls const *);
+const struct dpll_params *get_abe_dpll_params(struct dplls const *);
+
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
+void do_enable_clocks(u32 const *clk_domains,
+		      u32 const *clk_modules_hw_auto,
+		      u32 const *clk_modules_explicit_en,
+		      u8 wait_for_enable);
+
+void do_disable_clocks(u32 const *clk_domains,
+		       u32 const *clk_modules_disable,
+		       u8 wait_for_disable);
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
+
+void setup_post_dividers(u32 const base,
+			const struct dpll_params *params);
+u32 omap_ddr_clk(void);
+u32 get_sys_clk_index(void);
+void enable_basic_clocks(void);
+void enable_basic_uboot_clocks(void);
+
+void enable_usb_clocks(int index);
+void disable_usb_clocks(int index);
+
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
+void scale_vcores(struct vcores_data const *);
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
+int get_voltrail_opp(int rail_offset);
+u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
+void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
+	       u32 txdone, u32 txdone_mask, u32 opp);
+s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
+
+struct tag_serialnr;
+
+void omap_die_id_serial(void);
+void omap_die_id_get_board_serial(struct tag_serialnr *serialnr);
+void omap_die_id_usbethaddr(void);
+void omap_die_id_display(void);
+
+#ifdef CONFIG_FASTBOOT_FLASH
+void omap_set_fastboot_vars(void);
+#else
+static inline void omap_set_fastboot_vars(void) { }
+#endif
+
+void recalibrate_iodelay(void);
+
+void omap_smc1(u32 service, u32 val);
+
+/*
+ * Low-level helper function used when performing secure ROM calls on high-
+ * security (HS) device variants by doing a specially-formed smc entry.
+ */
+u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
+u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
+
+void enable_edma3_clocks(void);
+void disable_edma3_clocks(void);
+
+void omap_die_id(unsigned int *die_id);
+
+/* Initialize general purpose I2C(0) on the SoC */
+void gpi2c_init(void);
+
+/* Common FDT Fixups */
+int ft_hs_disable_rng(void *fdt, bd_t *bd);
+int ft_hs_fixup_dram(void *fdt, bd_t *bd);
+int ft_hs_add_tee(void *fdt, bd_t *bd);
+
+/* ABB */
+#define OMAP_ABB_NOMINAL_OPP		0
+#define OMAP_ABB_FAST_OPP		1
+#define OMAP_ABB_SLOW_OPP		3
+#define OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK		(0x1 << 0)
+#define OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK		(0x1 << 1)
+#define OMAP_ABB_CONTROL_OPP_CHANGE_MASK		(0x1 << 2)
+#define OMAP_ABB_CONTROL_SR2_IN_TRANSITION_MASK		(0x1 << 6)
+#define OMAP_ABB_SETUP_SR2EN_MASK			(0x1 << 0)
+#define OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK		(0x1 << 2)
+#define OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK		(0x1 << 1)
+#define OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK		(0xff << 8)
+
+static inline u32 omap_revision(void)
+{
+	extern u32 *const omap_si_rev;
+	return *omap_si_rev;
+}
+
+#define OMAP44xx	0x44000000
+
+static inline u8 is_omap44xx(void)
+{
+	extern u32 *const omap_si_rev;
+	return (*omap_si_rev & 0xFF000000) == OMAP44xx;
+};
+
+#define OMAP54xx	0x54000000
+
+static inline u8 is_omap54xx(void)
+{
+	extern u32 *const omap_si_rev;
+	return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
+}
+
+#define DRA7XX		0x07000000
+#define DRA72X		0x07200000
+#define DRA76X		0x07600000
+
+static inline u8 is_dra7xx(void)
+{
+	extern u32 *const omap_si_rev;
+	return ((*omap_si_rev & 0xFF000000) == DRA7XX);
+}
+
+static inline u8 is_dra72x(void)
+{
+	extern u32 *const omap_si_rev;
+	return (*omap_si_rev & 0xFFF00000) == DRA72X;
+}
+
+static inline u8 is_dra76x(void)
+{
+	extern u32 *const omap_si_rev;
+	return (*omap_si_rev & 0xFFF00000) == DRA76X;
+}
+
+static inline u8 is_dra76x_abz(void)
+{
+	extern u32 *const omap_si_rev;
+	return (*omap_si_rev & 0xF) == 2;
+}
+
+static inline u8 is_dra76x_acd(void)
+{
+	extern u32 *const omap_si_rev;
+	return (*omap_si_rev & 0xF) == 3;
+}
+#endif
+
+/*
+ * silicon revisions.
+ * Moving this to common, so that most of code can be moved to common,
+ * directories.
+ */
+
+/* omap4 */
+#define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
+#define OMAP4430_ES1_0	0x44300100
+#define OMAP4430_ES2_0	0x44300200
+#define OMAP4430_ES2_1	0x44300210
+#define OMAP4430_ES2_2	0x44300220
+#define OMAP4430_ES2_3	0x44300230
+#define OMAP4460_ES1_0	0x44600100
+#define OMAP4460_ES1_1	0x44600110
+#define OMAP4470_ES1_0	0x44700100
+
+/* omap5 */
+#define OMAP5430_SILICON_ID_INVALID	0
+#define OMAP5430_ES1_0	0x54300100
+#define OMAP5432_ES1_0	0x54320100
+#define OMAP5430_ES2_0  0x54300200
+#define OMAP5432_ES2_0  0x54320200
+
+/* DRA7XX */
+#define DRA762_ES1_0	0x07620100
+#define DRA752_ES1_0	0x07520100
+#define DRA752_ES1_1	0x07520110
+#define DRA752_ES2_0	0x07520200
+#define DRA722_ES1_0	0x07220100
+#define DRA722_ES2_0	0x07220200
+#define DRA722_ES2_1	0x07220210
+
+#define DRA762_ABZ_ES1_0	0x07620102
+#define DRA762_ACD_ES1_0	0x07620103
+/*
+ * silicon device type
+ * Moving to common from cpu.h, since it is shared by various omap devices
+ */
+#define TST_DEVICE          0x0
+#define EMU_DEVICE          0x1
+#define HS_DEVICE           0x2
+#define GP_DEVICE           0x3
+
+
+/*
+ * SRAM scratch space entries
+ */
+#define OMAP_SRAM_SCRATCH_OMAP_REV	SRAM_SCRATCH_SPACE_ADDR
+#define OMAP_SRAM_SCRATCH_EMIF_SIZE	(SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP_SRAM_SCRATCH_SYS_CTRL	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP_SRAM_SCRATCH_BOOT_PARAMS	(SRAM_SCRATCH_SPACE_ADDR + 0x24)
+#ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#endif
+#define OMAP_SRAM_SCRATCH_SPACE_END	(TI_SRAM_SCRATCH_BOARD_EEPROM_END)
+
+/* Boot parameters */
+#define DEVICE_DATA_OFFSET	0x18
+#define BOOT_MODE_OFFSET	0x8
+
+#define CH_FLAGS_CHSETTINGS	(1 << 0)
+#define CH_FLAGS_CHRAM		(1 << 1)
+#define CH_FLAGS_CHFLASH	(1 << 2)
+#define CH_FLAGS_CHMMCSD	(1 << 3)
+
+#ifndef __ASSEMBLY__
+u32 omap_sys_boot_device(void);
+#endif
+
+#endif /* _OMAP_COMMON_H_ */
diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h
new file mode 100644
index 0000000..20268fa
--- /dev/null
+++ b/arch/arm/include/asm/omap_gpio.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+#ifndef _GPIO_H
+#define _GPIO_H
+
+#include <asm/arch/cpu.h>
+
+#ifdef CONFIG_DM_GPIO
+
+/* Information about a GPIO bank */
+struct omap_gpio_platdata {
+	int bank_index;
+	ulong base;	/* address of registers in physical memory */
+	const char *port_name;
+};
+
+#else
+
+struct gpio_bank {
+	void *base;
+};
+
+extern const struct gpio_bank *const omap_gpio_bank;
+
+/**
+ * Check if gpio is valid.
+ *
+ * @param gpio	GPIO number
+ * @return 1 if ok, 0 on error
+ */
+int gpio_is_valid(int gpio);
+#endif
+
+#endif /* _GPIO_H_ */
diff --git a/arch/arm/include/asm/omap_i2c.h b/arch/arm/include/asm/omap_i2c.h
new file mode 100644
index 0000000..a697540
--- /dev/null
+++ b/arch/arm/include/asm/omap_i2c.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _OMAP_I2C_H
+#define _OMAP_I2C_H
+
+#ifdef CONFIG_DM_I2C
+
+/* Information about a GPIO bank */
+struct omap_i2c_platdata {
+	ulong base;	/* address of registers in physical memory */
+	int speed;
+	int ip_rev;
+};
+
+#endif
+
+enum {
+	OMAP_I2C_REV_V1 = 0,
+	OMAP_I2C_REV_V2 = 1,
+};
+
+#endif /* _OMAP_I2C_H */
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
new file mode 100644
index 0000000..6d31cc4
--- /dev/null
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -0,0 +1,237 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef OMAP_MMC_H_
+#define OMAP_MMC_H_
+
+#include <mmc.h>
+
+struct hsmmc {
+#ifndef CONFIG_OMAP34XX
+	unsigned int hl_rev;
+	unsigned int hl_hwinfo;
+	unsigned int hl_sysconfig;
+	unsigned char res0[0xf4];
+#endif
+	unsigned char res1[0x10];
+	unsigned int sysconfig;		/* 0x10 */
+	unsigned int sysstatus;		/* 0x14 */
+	unsigned char res2[0x14];
+	unsigned int con;		/* 0x2C */
+	unsigned int pwcnt;		/* 0x30 */
+	unsigned int dll;		/* 0x34 */
+	unsigned char res3[0xcc];
+	unsigned int blk;		/* 0x104 */
+	unsigned int arg;		/* 0x108 */
+	unsigned int cmd;		/* 0x10C */
+	unsigned int rsp10;		/* 0x110 */
+	unsigned int rsp32;		/* 0x114 */
+	unsigned int rsp54;		/* 0x118 */
+	unsigned int rsp76;		/* 0x11C */
+	unsigned int data;		/* 0x120 */
+	unsigned int pstate;		/* 0x124 */
+	unsigned int hctl;		/* 0x128 */
+	unsigned int sysctl;		/* 0x12C */
+	unsigned int stat;		/* 0x130 */
+	unsigned int ie;		/* 0x134 */
+	unsigned char res4[0x4];
+	unsigned int ac12;		/* 0x13C */
+	unsigned int capa;		/* 0x140 */
+	unsigned int capa2;		/* 0x144 */
+	unsigned char res5[0xc];
+	unsigned int admaes;		/* 0x154 */
+	unsigned int admasal;		/* 0x158 */
+};
+
+struct omap_hsmmc_plat {
+	struct mmc_config cfg;
+	struct hsmmc *base_addr;
+	struct mmc *mmc;
+	u32 controller_flags;
+	const char *hw_rev;
+};
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MADMA_EN			(0x1 << 0)
+#define MMC_SOFTRESET			(0x1 << 1)
+#define RESETDONE			(0x1 << 0)
+#define NOOPENDRAIN			(0x0 << 0)
+#define OPENDRAIN			(0x1 << 0)
+#define OD				(0x1 << 0)
+#define INIT_NOINIT			(0x0 << 1)
+#define INIT_INITSTREAM			(0x1 << 1)
+#define HR_NOHOSTRESP			(0x0 << 2)
+#define STR_BLOCK			(0x0 << 3)
+#define MODE_FUNC			(0x0 << 4)
+#define DW8_1_4BITMODE			(0x0 << 5)
+#define MIT_CTO				(0x0 << 6)
+#define CDP_ACTIVEHIGH			(0x0 << 7)
+#define WPP_ACTIVEHIGH			(0x0 << 8)
+#define RESERVED_MASK			(0x3 << 9)
+#define CTPL_MMC_SD			(0x0 << 11)
+#define DDR				(0x1 << 19)
+#define DMA_MASTER			(0x1 << 20)
+#define BLEN_512BYTESLEN		(0x200 << 0)
+#define NBLK_STPCNT			(0x0 << 16)
+#define DE_ENABLE			(0x1 << 0)
+#define BCE_ENABLE			(0x1 << 1)
+#define ACEN_ENABLE			(0x1 << 2)
+#define DDIR_OFFSET			(4)
+#define DDIR_MASK			(0x1 << 4)
+#define DDIR_WRITE			(0x0 << 4)
+#define DDIR_READ			(0x1 << 4)
+#define MSBS_SGLEBLK			(0x0 << 5)
+#define MSBS_MULTIBLK			(0x1 << 5)
+#define RSP_TYPE_OFFSET			(16)
+#define RSP_TYPE_MASK			(0x3 << 16)
+#define RSP_TYPE_NORSP			(0x0 << 16)
+#define RSP_TYPE_LGHT136		(0x1 << 16)
+#define RSP_TYPE_LGHT48			(0x2 << 16)
+#define RSP_TYPE_LGHT48B		(0x3 << 16)
+#define CCCE_NOCHECK			(0x0 << 19)
+#define CCCE_CHECK			(0x1 << 19)
+#define CICE_NOCHECK			(0x0 << 20)
+#define CICE_CHECK			(0x1 << 20)
+#define DP_OFFSET			(21)
+#define DP_MASK				(0x1 << 21)
+#define DP_NO_DATA			(0x0 << 21)
+#define DP_DATA				(0x1 << 21)
+#define CMD_TYPE_NORMAL			(0x0 << 22)
+#define INDEX_OFFSET			(24)
+#define INDEX_MASK			(0x3f << 24)
+#define INDEX(i)			(i << 24)
+#define DATI_MASK			(0x1 << 1)
+#define CMDI_MASK			(0x1 << 0)
+#define DTW_1_BITMODE			(0x0 << 1)
+#define DTW_4_BITMODE			(0x1 << 1)
+#define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
+#define SDBP_PWROFF			(0x0 << 8)
+#define SDBP_PWRON			(0x1 << 8)
+#define SDVS_MASK			(0x7 << 9)
+#define SDVS_1V8			(0x5 << 9)
+#define SDVS_3V0			(0x6 << 9)
+#define SDVS_3V3			(0x7 << 9)
+#define DMA_SELECT			(0x2 << 3)
+#define ICE_MASK			(0x1 << 0)
+#define ICE_STOP			(0x0 << 0)
+#define ICS_MASK			(0x1 << 1)
+#define ICS_NOTREADY			(0x0 << 1)
+#define ICE_OSCILLATE			(0x1 << 0)
+#define CEN_MASK			(0x1 << 2)
+#define CEN_ENABLE			(0x1 << 2)
+#define CLKD_OFFSET			(6)
+#define CLKD_MASK			(0x3FF << 6)
+#define DTO_MASK			(0xF << 16)
+#define DTO_15THDTO			(0xE << 16)
+#define SOFTRESETALL			(0x1 << 24)
+#define CC_MASK				(0x1 << 0)
+#define TC_MASK				(0x1 << 1)
+#define BWR_MASK			(0x1 << 4)
+#define BRR_MASK			(0x1 << 5)
+#define ERRI_MASK			(0x1 << 15)
+#define IE_CC				(0x01 << 0)
+#define IE_TC				(0x01 << 1)
+#define IE_BWR				(0x01 << 4)
+#define IE_BRR				(0x01 << 5)
+#define IE_CTO				(0x01 << 16)
+#define IE_CCRC				(0x01 << 17)
+#define IE_CEB				(0x01 << 18)
+#define IE_CIE				(0x01 << 19)
+#define IE_DTO				(0x01 << 20)
+#define IE_DCRC				(0x01 << 21)
+#define IE_DEB				(0x01 << 22)
+#define IE_ADMAE			(0x01 << 25)
+#define IE_CERR				(0x01 << 28)
+#define IE_BADA				(0x01 << 29)
+
+#define VS33_3V3SUP			BIT(24)
+#define VS30_3V0SUP			BIT(25)
+#define VS18_1V8SUP			BIT(26)
+
+#define AC12_ET				BIT(22)
+#define AC12_V1V8_SIGEN			BIT(19)
+#define AC12_SCLK_SEL			BIT(23)
+#define AC12_UHSMC_MASK			(7 << 16)
+#define AC12_UHSMC_DDR50		(4 << 16)
+#define AC12_UHSMC_SDR104		(3 << 16)
+#define AC12_UHSMC_SDR50		(2 << 16)
+#define AC12_UHSMC_SDR25		(1 << 16)
+#define AC12_UHSMC_SDR12		(0 << 16)
+#define AC12_UHSMC_RES			(0x7 << 16)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE		512
+#define MMC_CARD			0
+#define SD_CARD				1
+#define BYTE_MODE			0
+#define SECTOR_MODE			1
+#define CLK_INITSEQ			0
+#define CLK_400KHZ			1
+#define CLK_MISC			2
+
+#define CLKD_MAX			0x3FF	/* max clock divisor: 1023 */
+
+#define RSP_TYPE_NONE	(RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0	(INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#ifdef CONFIG_OMAP54XX
+#define MMC_CLOCK_REFERENCE	192 /* MHz */
+#else
+#define MMC_CLOCK_REFERENCE	96 /* MHz */
+#endif
+
+/* DLL */
+#define DLL_SWT			BIT(20)
+#define DLL_FORCE_SR_C_SHIFT	13
+#define DLL_FORCE_SR_C_MASK	0x7f
+#define DLL_FORCE_VALUE		BIT(12)
+#define DLL_CALIB		BIT(1)
+
+#define MAX_PHASE_DELAY		0x7c
+
+/* CAPA2 */
+#define CAPA2_TSDR50		BIT(13)
+
+#define mmc_reg_out(addr, mask, val)\
+	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\
+		IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\
+		IE_BRR | IE_BWR | IE_TC | IE_CC)
+
+#define CON_CLKEXTFREE		BIT(16)
+#define CON_PADEN		BIT(15)
+#define PSTATE_CLEV		BIT(24)
+#define PSTATE_DLEV		(0xF << 20)
+#define PSTATE_DLEV_DAT0	(0x1 << 20)
+
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
+		int wp_gpio);
+
+void vmmc_pbias_config(uint voltage);
+void board_mmc_poweron_ldo(uint voltage);
+#endif /* OMAP_MMC_H_ */
diff --git a/arch/arm/include/asm/omap_musb.h b/arch/arm/include/asm/omap_musb.h
new file mode 100644
index 0000000..b40ea00
--- /dev/null
+++ b/arch/arm/include/asm/omap_musb.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board data structure for musb gadget on OMAPs
+ *
+ * Copyright (C) 2012, Ilya Yanok <ilya.yanok@gmail.com>
+ */
+
+#ifndef __ASM_ARM_OMAP_MUSB_H
+#define __ASM_ARM_OMAP_MUSB_H
+#include <linux/usb/musb.h>
+
+extern struct musb_platform_ops musb_dsps_ops;
+extern const struct musb_platform_ops am35x_ops;
+extern const struct musb_platform_ops omap2430_ops;
+
+struct omap_musb_board_data {
+	u8 interface_type;
+	struct udevice *dev;
+	void (*set_phy_power)(struct udevice *dev, u8 on);
+	void (*clear_irq)(struct udevice *dev);
+	void (*reset)(struct udevice *dev);
+};
+
+enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
+
+struct ti_musb_platdata {
+	void *base;
+	void *ctrl_mod_base;
+	struct musb_hdrc_platform_data plat;
+};
+
+#endif /* __ASM_ARM_OMAP_MUSB_H */
diff --git a/arch/arm/include/asm/omap_sec_common.h b/arch/arm/include/asm/omap_sec_common.h
new file mode 100644
index 0000000..f10a41f
--- /dev/null
+++ b/arch/arm/include/asm/omap_sec_common.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016
+ * Texas Instruments, <www.ti.com>
+ *
+ * Andreas Dannenberg <dannenberg@ti.com>
+ */
+#ifndef	_OMAP_SEC_COMMON_H_
+#define	_OMAP_SEC_COMMON_H_
+
+#include <common.h>
+
+/*
+ * Invoke secure ROM API on high-security (HS) device variants. It formats
+ * the variable argument list into the format expected by the ROM code before
+ * triggering the actual low-level smc entry.
+ */
+u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...);
+
+/*
+ * Invoke a secure ROM API on high-secure (HS) device variants that can be used
+ * to verify a secure blob by authenticating and optionally decrypting it. The
+ * exact operation performed depends on how the certificate that was embedded
+ * into the blob during the signing/encryption step when the secure blob was
+ * first created.
+ */
+int secure_boot_verify_image(void **p_image, size_t *p_size);
+
+/*
+ * Return the start of secure reserved RAM, if a default start address has
+ * not been configured then return a region at the end of the external DRAM.
+ */
+u32 get_sec_mem_start(void);
+
+/*
+ * Invoke a secure HAL API that allows configuration of the external memory
+ * firewall regions.
+ */
+int secure_emif_firewall_setup(uint8_t region_num, uint32_t start_addr,
+			       uint32_t size, uint32_t access_perm,
+			       uint32_t initiator_perm);
+
+/*
+ * Invoke a secure HAL API on high-secure (HS) device variants that reserves a
+ * region of external memory for secure world use, and protects it using memory
+ * firewalls that prevent public world access. This API is intended to setaside
+ * memory that will be used for a secure world OS/TEE.
+ */
+int secure_emif_reserve(void);
+
+/*
+ * Invoke a secure HAL API to lock the external memory firewall configurations.
+ * After this API is called, none of the HAL APIs for configuring the that
+ * firewall will be usable (calls to those APIs will return failure and have
+ * no effect).
+ */
+int secure_emif_firewall_lock(void);
+
+/*
+ * Invoke a secure HAL API to authenticate and install a Trusted Execution
+ * Environment (TEE) image.
+ */
+int secure_tee_install(u32 tee_image);
+
+#endif /* _OMAP_SEC_COMMON_H_ */
diff --git a/arch/arm/include/asm/opcodes-sec.h b/arch/arm/include/asm/opcodes-sec.h
new file mode 100644
index 0000000..55c696c
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-sec.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 ARM Limited
+ */
+
+#ifndef __ASM_ARM_OPCODES_SEC_H
+#define __ASM_ARM_OPCODES_SEC_H
+
+#include <asm/opcodes.h>
+
+#define __SMC(imm4) __inst_arm_thumb32(					\
+	0xE1600070 | (((imm4) & 0xF) << 0),				\
+	0xF7F08000 | (((imm4) & 0xF) << 16)				\
+)
+
+#endif /* __ASM_ARM_OPCODES_SEC_H */
diff --git a/arch/arm/include/asm/opcodes-virt.h b/arch/arm/include/asm/opcodes-virt.h
new file mode 100644
index 0000000..437b9a8
--- /dev/null
+++ b/arch/arm/include/asm/opcodes-virt.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * opcodes-virt.h: Opcode definitions for the ARM virtualization extensions
+ * Copyright (C) 2012  Linaro Limited
+ */
+#ifndef __ASM_ARM_OPCODES_VIRT_H
+#define __ASM_ARM_OPCODES_VIRT_H
+
+#include <asm/opcodes.h>
+
+#define __HVC(imm16) __inst_arm_thumb32(				\
+	0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F),	\
+	0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF)	\
+)
+
+#define __ERET	__inst_arm_thumb32(					\
+	0xE160006E,							\
+	0xF3DE8F00							\
+)
+
+#define __MSR_ELR_HYP(regnum)	__inst_arm_thumb32(			\
+	0xE12EF300 | regnum,						\
+	0xF3808E30 | (regnum << 16)					\
+)
+
+#endif /* ! __ASM_ARM_OPCODES_VIRT_H */
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
new file mode 100644
index 0000000..21b3344
--- /dev/null
+++ b/arch/arm/include/asm/opcodes.h
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  arch/arm/include/asm/opcodes.h
+ */
+
+#ifndef __ASM_ARM_OPCODES_H
+#define __ASM_ARM_OPCODES_H
+
+#ifndef __ASSEMBLY__
+#include <linux/linkage.h>
+extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
+#endif
+
+#define ARM_OPCODE_CONDTEST_FAIL   0
+#define ARM_OPCODE_CONDTEST_PASS   1
+#define ARM_OPCODE_CONDTEST_UNCOND 2
+
+
+/*
+ * Assembler opcode byteswap helpers.
+ * These are only intended for use by this header: don't use them directly,
+ * because they will be suboptimal in most cases.
+ */
+#define ___asm_opcode_swab32(x) (	\
+	  (((x) << 24) & 0xFF000000)	\
+	| (((x) <<  8) & 0x00FF0000)	\
+	| (((x) >>  8) & 0x0000FF00)	\
+	| (((x) >> 24) & 0x000000FF)	\
+)
+#define ___asm_opcode_swab16(x) (	\
+	  (((x) << 8) & 0xFF00)		\
+	| (((x) >> 8) & 0x00FF)		\
+)
+#define ___asm_opcode_swahb32(x) (	\
+	  (((x) << 8) & 0xFF00FF00)	\
+	| (((x) >> 8) & 0x00FF00FF)	\
+)
+#define ___asm_opcode_swahw32(x) (	\
+	  (((x) << 16) & 0xFFFF0000)	\
+	| (((x) >> 16) & 0x0000FFFF)	\
+)
+#define ___asm_opcode_identity32(x) ((x) & 0xFFFFFFFF)
+#define ___asm_opcode_identity16(x) ((x) & 0xFFFF)
+
+
+/*
+ * Opcode byteswap helpers
+ *
+ * These macros help with converting instructions between a canonical integer
+ * format and in-memory representation, in an endianness-agnostic manner.
+ *
+ * __mem_to_opcode_*() convert from in-memory representation to canonical form.
+ * __opcode_to_mem_*() convert from canonical form to in-memory representation.
+ *
+ *
+ * Canonical instruction representation:
+ *
+ *	ARM:		0xKKLLMMNN
+ *	Thumb 16-bit:	0x0000KKLL, where KK < 0xE8
+ *	Thumb 32-bit:	0xKKLLMMNN, where KK >= 0xE8
+ *
+ * There is no way to distinguish an ARM instruction in canonical representation
+ * from a Thumb instruction (just as these cannot be distinguished in memory).
+ * Where this distinction is important, it needs to be tracked separately.
+ *
+ * Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not
+ * represent any valid Thumb-2 instruction.  For this range,
+ * __opcode_is_thumb32() and __opcode_is_thumb16() will both be false.
+ *
+ * The ___asm variants are intended only for use by this header, in situations
+ * involving inline assembler.  For .S files, the normal __opcode_*() macros
+ * should do the right thing.
+ */
+#ifdef __ASSEMBLY__
+
+#define ___opcode_swab32(x) ___asm_opcode_swab32(x)
+#define ___opcode_swab16(x) ___asm_opcode_swab16(x)
+#define ___opcode_swahb32(x) ___asm_opcode_swahb32(x)
+#define ___opcode_swahw32(x) ___asm_opcode_swahw32(x)
+#define ___opcode_identity32(x) ___asm_opcode_identity32(x)
+#define ___opcode_identity16(x) ___asm_opcode_identity16(x)
+
+#else /* ! __ASSEMBLY__ */
+
+#include <linux/types.h>
+#include <linux/swab.h>
+
+#define ___opcode_swab32(x) swab32(x)
+#define ___opcode_swab16(x) swab16(x)
+#define ___opcode_swahb32(x) swahb32(x)
+#define ___opcode_swahw32(x) swahw32(x)
+#define ___opcode_identity32(x) ((u32)(x))
+#define ___opcode_identity16(x) ((u16)(x))
+
+#endif /* ! __ASSEMBLY__ */
+
+
+#ifdef CONFIG_CPU_ENDIAN_BE8
+
+#define __opcode_to_mem_arm(x) ___opcode_swab32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_swab16(x)
+#define __opcode_to_mem_thumb32(x) ___opcode_swahb32(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_swab32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_swab16(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahb32(x)
+
+#else /* ! CONFIG_CPU_ENDIAN_BE8 */
+
+#define __opcode_to_mem_arm(x) ___opcode_identity32(x)
+#define __opcode_to_mem_thumb16(x) ___opcode_identity16(x)
+#define ___asm_opcode_to_mem_arm(x) ___asm_opcode_identity32(x)
+#define ___asm_opcode_to_mem_thumb16(x) ___asm_opcode_identity16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
+/*
+ * On BE32 systems, using 32-bit accesses to store Thumb instructions will not
+ * work in all cases, due to alignment constraints.  For now, a correct
+ * version is not provided for BE32.
+ */
+#define __opcode_to_mem_thumb32(x) ___opcode_swahw32(x)
+#define ___asm_opcode_to_mem_thumb32(x) ___asm_opcode_swahw32(x)
+#endif
+
+#endif /* ! CONFIG_CPU_ENDIAN_BE8 */
+
+#define __mem_to_opcode_arm(x) __opcode_to_mem_arm(x)
+#define __mem_to_opcode_thumb16(x) __opcode_to_mem_thumb16(x)
+#ifndef CONFIG_CPU_ENDIAN_BE32
+#define __mem_to_opcode_thumb32(x) __opcode_to_mem_thumb32(x)
+#endif
+
+/* Operations specific to Thumb opcodes */
+
+/* Instruction size checks: */
+#define __opcode_is_thumb32(x) (		\
+	   ((x) & 0xF8000000) == 0xE8000000	\
+	|| ((x) & 0xF0000000) == 0xF0000000	\
+)
+#define __opcode_is_thumb16(x) (					\
+	   ((x) & 0xFFFF0000) == 0					\
+	&& !(((x) & 0xF800) == 0xE800 || ((x) & 0xF000) == 0xF000)	\
+)
+
+/* Operations to construct or split 32-bit Thumb instructions: */
+#define __opcode_thumb32_first(x) (___opcode_identity16((x) >> 16))
+#define __opcode_thumb32_second(x) (___opcode_identity16(x))
+#define __opcode_thumb32_compose(first, second) (			\
+	  (___opcode_identity32(___opcode_identity16(first)) << 16)	\
+	| ___opcode_identity32(___opcode_identity16(second))		\
+)
+#define ___asm_opcode_thumb32_first(x) (___asm_opcode_identity16((x) >> 16))
+#define ___asm_opcode_thumb32_second(x) (___asm_opcode_identity16(x))
+#define ___asm_opcode_thumb32_compose(first, second) (			    \
+	  (___asm_opcode_identity32(___asm_opcode_identity16(first)) << 16) \
+	| ___asm_opcode_identity32(___asm_opcode_identity16(second))	    \
+)
+
+/*
+ * Opcode injection helpers
+ *
+ * In rare cases it is necessary to assemble an opcode which the
+ * assembler does not support directly, or which would normally be
+ * rejected because of the CFLAGS or AFLAGS used to build the affected
+ * file.
+ *
+ * Before using these macros, consider carefully whether it is feasible
+ * instead to change the build flags for your file, or whether it really
+ * makes sense to support old assembler versions when building that
+ * particular kernel feature.
+ *
+ * The macros defined here should only be used where there is no viable
+ * alternative.
+ *
+ *
+ * __inst_arm(x): emit the specified ARM opcode
+ * __inst_thumb16(x): emit the specified 16-bit Thumb opcode
+ * __inst_thumb32(x): emit the specified 32-bit Thumb opcode
+ *
+ * __inst_arm_thumb16(arm, thumb): emit either the specified arm or
+ *	16-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ * __inst_arm_thumb32(arm, thumb): emit either the specified arm or
+ *	32-bit Thumb opcode, depending on whether an ARM or Thumb-2
+ *	kernel is being built
+ *
+ *
+ * Note that using these macros directly is poor practice.  Instead, you
+ * should use them to define human-readable wrapper macros to encode the
+ * instructions that you care about.  In code which might run on ARMv7 or
+ * above, you can usually use the __inst_arm_thumb{16,32} macros to
+ * specify the ARM and Thumb alternatives at the same time.  This ensures
+ * that the correct opcode gets emitted depending on the instruction set
+ * used for the kernel build.
+ *
+ * Look at opcodes-virt.h for an example of how to use these macros.
+ */
+#include <linux/stringify.h>
+
+#define __inst_arm(x) ___inst_arm(___asm_opcode_to_mem_arm(x))
+#define __inst_thumb32(x) ___inst_thumb32(				\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_first(x)),	\
+	___asm_opcode_to_mem_thumb16(___asm_opcode_thumb32_second(x))	\
+)
+#define __inst_thumb16(x) ___inst_thumb16(___asm_opcode_to_mem_thumb16(x))
+
+#ifdef CONFIG_THUMB2_KERNEL
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) \
+	__inst_thumb16(thumb_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) \
+	__inst_thumb32(thumb_opcode)
+#else
+#define __inst_arm_thumb16(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#define __inst_arm_thumb32(arm_opcode, thumb_opcode) __inst_arm(arm_opcode)
+#endif
+
+/* Helpers for the helpers.  Don't use these directly. */
+#ifdef __ASSEMBLY__
+#define ___inst_arm(x) .long x
+#define ___inst_thumb16(x) .short x
+#define ___inst_thumb32(first, second) .short first, second
+#else
+#define ___inst_arm(x) ".long " __stringify(x) "\n\t"
+#define ___inst_thumb16(x) ".short " __stringify(x) "\n\t"
+#define ___inst_thumb32(first, second) \
+	".short " __stringify(first) ", " __stringify(second) "\n\t"
+#endif
+
+#endif /* __ASM_ARM_OPCODES_H */
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
new file mode 100644
index 0000000..f69e9e4
--- /dev/null
+++ b/arch/arm/include/asm/pl310.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ */
+#ifndef _PL310_H_
+#define _PL310_H_
+
+#include <linux/types.h>
+
+/* Register bit fields */
+#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK	(1 << 16)
+#define L2X0_DYNAMIC_CLK_GATING_EN		(1 << 1)
+#define L2X0_STNDBY_MODE_EN			(1 << 0)
+#define L2X0_CTRL_EN				1
+
+#define L310_SHARED_ATT_OVERRIDE_ENABLE		(1 << 22)
+#define L310_AUX_CTRL_DATA_PREFETCH_MASK	(1 << 28)
+#define L310_AUX_CTRL_INST_PREFETCH_MASK	(1 << 29)
+#define L310_LATENCY_CTRL_SETUP(n)		((n) << 0)
+#define L310_LATENCY_CTRL_RD(n)			((n) << 4)
+#define L310_LATENCY_CTRL_WR(n)			((n) << 8)
+
+#define L2X0_CACHE_ID_PART_MASK     (0xf << 6)
+#define L2X0_CACHE_ID_PART_L310     (3 << 6)
+#define L2X0_CACHE_ID_RTL_MASK          0x3f
+#define L2X0_CACHE_ID_RTL_R3P2          0x8
+
+struct pl310_regs {
+	u32 pl310_cache_id;
+	u32 pl310_cache_type;
+	u32 pad1[62];
+	u32 pl310_ctrl;
+	u32 pl310_aux_ctrl;
+	u32 pl310_tag_latency_ctrl;
+	u32 pl310_data_latency_ctrl;
+	u32 pad2[60];
+	u32 pl310_event_cnt_ctrl;
+	u32 pl310_event_cnt1_cfg;
+	u32 pl310_event_cnt0_cfg;
+	u32 pl310_event_cnt1_val;
+	u32 pl310_event_cnt0_val;
+	u32 pl310_intr_mask;
+	u32 pl310_masked_intr_stat;
+	u32 pl310_raw_intr_stat;
+	u32 pl310_intr_clear;
+	u32 pad3[323];
+	u32 pl310_cache_sync;
+	u32 pad4[15];
+	u32 pl310_inv_line_pa;
+	u32 pad5[2];
+	u32 pl310_inv_way;
+	u32 pad6[12];
+	u32 pl310_clean_line_pa;
+	u32 pad7[1];
+	u32 pl310_clean_line_idx;
+	u32 pl310_clean_way;
+	u32 pad8[12];
+	u32 pl310_clean_inv_line_pa;
+	u32 pad9[1];
+	u32 pl310_clean_inv_line_idx;
+	u32 pl310_clean_inv_way;
+	u32 pad10[64];
+	u32 pl310_lockdown_dbase;
+	u32 pl310_lockdown_ibase;
+	u32 pad11[190];
+	u32 pl310_addr_filter_start;
+	u32 pl310_addr_filter_end;
+	u32 pad12[190];
+	u32 pl310_test_operation;
+	u32 pad13[3];
+	u32 pl310_line_data;
+	u32 pad14[7];
+	u32 pl310_line_tag;
+	u32 pad15[3];
+	u32 pl310_debug_ctrl;
+	u32 pad16[7];
+	u32 pl310_prefetch_ctrl;
+	u32 pad17[7];
+	u32 pl310_power_ctrl;
+};
+
+void pl310_inval_all(void);
+void pl310_clean_inval_all(void);
+void pl310_inval_range(u32 start, u32 end);
+void pl310_clean_inval_range(u32 start, u32 end);
+
+#endif
diff --git a/arch/arm/include/asm/posix_types.h b/arch/arm/include/asm/posix_types.h
new file mode 100644
index 0000000..d254b95
--- /dev/null
+++ b/arch/arm/include/asm/posix_types.h
@@ -0,0 +1,87 @@
+/*
+ *  linux/include/asm-arm/posix_types.h
+ *
+ *  Copyright (C) 1996-1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ */
+#ifndef __ARCH_ARM_POSIX_TYPES_H
+#define __ARCH_ARM_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+
+#ifdef	__aarch64__
+typedef unsigned long		__kernel_size_t;
+typedef long			__kernel_ssize_t;
+typedef long			__kernel_ptrdiff_t;
+#else
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+#endif
+
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char *			__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp)))
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/proc-armv/domain.h b/arch/arm/include/asm/proc-armv/domain.h
new file mode 100644
index 0000000..aadc831
--- /dev/null
+++ b/arch/arm/include/asm/proc-armv/domain.h
@@ -0,0 +1,50 @@
+/*
+ *  linux/include/asm-arm/proc-armv/domain.h
+ *
+ *  Copyright (C) 1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROC_DOMAIN_H
+#define __ASM_PROC_DOMAIN_H
+
+/*
+ * Domain numbers
+ *
+ *  DOMAIN_IO     - domain 2 includes all IO only
+ *  DOMAIN_KERNEL - domain 1 includes all kernel memory only
+ *  DOMAIN_USER   - domain 0 includes all user memory only
+ */
+#define DOMAIN_USER	0
+#define DOMAIN_KERNEL	1
+#define DOMAIN_TABLE	1
+#define DOMAIN_IO	2
+
+/*
+ * Domain types
+ */
+#define DOMAIN_NOACCESS	0
+#define DOMAIN_CLIENT	1
+#define DOMAIN_MANAGER	3
+
+#define domain_val(dom,type)	((type) << 2*(dom))
+
+#define set_domain(x)					\
+	do {						\
+	__asm__ __volatile__(				\
+	"mcr	p15, 0, %0, c3, c0	@ set domain"	\
+	  : : "r" (x));					\
+	} while (0)
+
+#define modify_domain(dom,type)				\
+	do {						\
+	unsigned int domain = current->thread.domain;	\
+	domain &= ~domain_val(dom, DOMAIN_MANAGER);	\
+	domain |= domain_val(dom, type);		\
+	current->thread.domain = domain;		\
+	set_domain(current->thread.domain);		\
+	} while (0)
+
+#endif
diff --git a/arch/arm/include/asm/proc-armv/processor.h b/arch/arm/include/asm/proc-armv/processor.h
new file mode 100644
index 0000000..532f207
--- /dev/null
+++ b/arch/arm/include/asm/proc-armv/processor.h
@@ -0,0 +1,74 @@
+/*
+ *  linux/include/asm-arm/proc-armv/processor.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   20-09-1996	RMK	Created
+ *   26-09-1996	RMK	Added 'EXTRA_THREAD_STRUCT*'
+ *   28-09-1996	RMK	Moved start_thread into the processor dependencies
+ *   09-09-1998	PJB	Delete redundant `wp_works_ok'
+ *   30-05-1999	PJB	Save sl across context switches
+ *   31-07-1999	RMK	Added 'domain' stuff
+ */
+#ifndef __ASM_PROC_PROCESSOR_H
+#define __ASM_PROC_PROCESSOR_H
+
+#include <asm/proc-armv/domain.h>
+
+#define KERNEL_STACK_SIZE	PAGE_SIZE
+
+struct context_save_struct {
+	unsigned long cpsr;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long sl;
+	unsigned long fp;
+	unsigned long pc;
+};
+
+#define INIT_CSS (struct context_save_struct){ SVC_MODE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+
+#define EXTRA_THREAD_STRUCT						\
+	unsigned int	domain;
+
+#define EXTRA_THREAD_STRUCT_INIT					\
+	domain:	  domain_val(DOMAIN_USER, DOMAIN_CLIENT) |		\
+		  domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) |		\
+		  domain_val(DOMAIN_IO, DOMAIN_CLIENT)
+
+#define start_thread(regs,pc,sp)					\
+({									\
+	unsigned long *stack = (unsigned long *)sp;			\
+	set_fs(USER_DS);						\
+	memzero(regs->uregs, sizeof(regs->uregs));			\
+	if (current->personality & ADDR_LIMIT_32BIT)			\
+		regs->ARM_cpsr = USR_MODE;				\
+	else								\
+		regs->ARM_cpsr = USR26_MODE;				\
+	regs->ARM_pc = pc;		/* pc */			\
+	regs->ARM_sp = sp;		/* sp */			\
+	regs->ARM_r2 = stack[2];	/* r2 (envp) */			\
+	regs->ARM_r1 = stack[1];	/* r1 (argv) */			\
+	regs->ARM_r0 = stack[0];	/* r0 (argc) */			\
+})
+
+#define KSTK_EIP(tsk)	(((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
+#define KSTK_ESP(tsk)	(((unsigned long *)(4096+(unsigned long)(tsk)))[1017])
+
+/* Allocation and freeing of basic task resources. */
+/*
+ * NOTE! The task struct and the stack go together
+ */
+#define ll_alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
+#define ll_free_task_struct(p) free_pages((unsigned long)(p),1)
+
+#endif
diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h
new file mode 100644
index 0000000..e37ad8f
--- /dev/null
+++ b/arch/arm/include/asm/proc-armv/ptrace.h
@@ -0,0 +1,131 @@
+/*
+ *  linux/include/asm-arm/proc-armv/ptrace.h
+ *
+ *  Copyright (C) 1996-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROC_PTRACE_H
+#define __ASM_PROC_PTRACE_H
+
+#ifdef CONFIG_ARM64
+
+#define PCMASK		0
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are stored
+ * on the stack during an exception.
+ */
+struct pt_regs {
+	unsigned long elr;
+	unsigned long regs[31];
+};
+
+#endif	/* __ASSEMBLY__ */
+
+#else	/* CONFIG_ARM64 */
+
+#define USR26_MODE	0x00
+#define FIQ26_MODE	0x01
+#define IRQ26_MODE	0x02
+#define SVC26_MODE	0x03
+#define USR_MODE	0x10
+#define FIQ_MODE	0x11
+#define IRQ_MODE	0x12
+#define SVC_MODE	0x13
+#define MON_MODE	0x16
+#define ABT_MODE	0x17
+#define HYP_MODE	0x1a
+#define UND_MODE	0x1b
+#define SYSTEM_MODE	0x1f
+#define MODE_MASK	0x1f
+#define T_BIT		0x20
+#define F_BIT		0x40
+#define I_BIT		0x80
+#define A_BIT		0x100
+#define CC_V_BIT	(1 << 28)
+#define CC_C_BIT	(1 << 29)
+#define CC_Z_BIT	(1 << 30)
+#define CC_N_BIT	(1 << 31)
+#define PCMASK		0
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+struct pt_regs {
+	long uregs[18];
+};
+
+#define ARM_cpsr	uregs[16]
+#define ARM_pc		uregs[15]
+#define ARM_lr		uregs[14]
+#define ARM_sp		uregs[13]
+#define ARM_ip		uregs[12]
+#define ARM_fp		uregs[11]
+#define ARM_r10		uregs[10]
+#define ARM_r9		uregs[9]
+#define ARM_r8		uregs[8]
+#define ARM_r7		uregs[7]
+#define ARM_r6		uregs[6]
+#define ARM_r5		uregs[5]
+#define ARM_r4		uregs[4]
+#define ARM_r3		uregs[3]
+#define ARM_r2		uregs[2]
+#define ARM_r1		uregs[1]
+#define ARM_r0		uregs[0]
+#define ARM_ORIG_r0	uregs[17]
+
+#ifdef __KERNEL__
+
+#define user_mode(regs)	\
+	(((regs)->ARM_cpsr & 0xf) == 0)
+
+#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+#define thumb_mode(regs) \
+	(((regs)->ARM_cpsr & T_BIT))
+#else
+#define thumb_mode(regs) (0)
+#endif
+
+#define processor_mode(regs) \
+	((regs)->ARM_cpsr & MODE_MASK)
+
+#define interrupts_enabled(regs) \
+	(!((regs)->ARM_cpsr & I_BIT))
+
+#define fast_interrupts_enabled(regs) \
+	(!((regs)->ARM_cpsr & F_BIT))
+
+#define condition_codes(regs) \
+	((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
+
+/* Are the current registers suitable for user mode?
+ * (used to maintain security in signal handlers)
+ */
+static inline int valid_user_regs(struct pt_regs *regs)
+{
+	if ((regs->ARM_cpsr & 0xf) == 0 &&
+	    (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0)
+		return 1;
+
+	/*
+	 * Force CPSR to something logical...
+	 */
+	regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10);
+
+	return 0;
+}
+
+#endif	/* __KERNEL__ */
+
+#endif	/* __ASSEMBLY__ */
+
+#endif	/* CONFIG_ARM64 */
+
+#endif
diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h
new file mode 100644
index 0000000..c61374e
--- /dev/null
+++ b/arch/arm/include/asm/proc-armv/system.h
@@ -0,0 +1,224 @@
+/*
+ *  linux/include/asm-arm/proc-armv/system.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROC_SYSTEM_H
+#define __ASM_PROC_SYSTEM_H
+
+/*
+ * Save the current interrupt enable state & disable IRQs
+ */
+#ifdef CONFIG_ARM64
+
+/*
+ * Save the current interrupt enable state
+ * and disable IRQs/FIQs
+ */
+#define local_irq_save(flags)					\
+	({							\
+	asm volatile(						\
+	"mrs	%0, daif\n"					\
+	"msr	daifset, #3"					\
+	: "=r" (flags)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+#define local_irq_restore(flags)				\
+	({							\
+	asm volatile(						\
+	"msr	daif, %0"					\
+	:							\
+	: "r" (flags)						\
+	: "memory");						\
+	})
+
+/*
+ * Enable IRQs/FIQs
+ */
+#define local_irq_enable()					\
+	({							\
+	asm volatile(						\
+	"msr	daifclr, #3"					\
+	:							\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Disable IRQs/FIQs
+ */
+#define local_irq_disable()					\
+	({							\
+	asm volatile(						\
+	"msr	daifset, #3"					\
+	:							\
+	:							\
+	: "memory");						\
+	})
+
+#else	/* CONFIG_ARM64 */
+
+#define local_irq_save(x)					\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_irq_save\n"	\
+"	orr	%1, %0, #128\n"					\
+"	msr	cpsr_c, %1"					\
+	: "=r" (x), "=r" (temp)					\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Enable IRQs
+ */
+#define local_irq_enable()					\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_irq_enable\n"	\
+"	bic	%0, %0, #128\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Disable IRQs
+ */
+#define local_irq_disable()					\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_irq_disable\n"	\
+"	orr	%0, %0, #128\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Enable FIQs
+ */
+#define __stf()							\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ stf\n"		\
+"	bic	%0, %0, #64\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Disable FIQs
+ */
+#define __clf()							\
+	({							\
+		unsigned long temp;				\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ clf\n"		\
+"	orr	%0, %0, #64\n"					\
+"	msr	cpsr_c, %0"					\
+	: "=r" (temp)						\
+	:							\
+	: "memory");						\
+	})
+
+/*
+ * Save the current interrupt enable state.
+ */
+#define local_save_flags(x)					\
+	({							\
+	__asm__ __volatile__(					\
+	"mrs	%0, cpsr		@ local_save_flags\n"	\
+	  : "=r" (x)						\
+	  :							\
+	  : "memory");						\
+	})
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+#define local_irq_restore(x)					\
+	__asm__ __volatile__(					\
+	"msr	cpsr_c, %0		@ local_irq_restore\n"	\
+	:							\
+	: "r" (x)						\
+	: "memory")
+
+#endif	/* CONFIG_ARM64 */
+
+#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \
+	defined(CONFIG_ARM64)
+/*
+ * On the StrongARM, "swp" is terminally broken since it bypasses the
+ * cache totally.  This means that the cache becomes inconsistent, and,
+ * since we use normal loads/stores as well, this is really bad.
+ * Typically, this causes oopsen in filp_close, but could have other,
+ * more disasterous effects.  There are two work-arounds:
+ *  1. Disable interrupts and emulate the atomic swap
+ *  2. Clean the cache, perform atomic swap, flush the cache
+ *
+ * We choose (1) since its the "easiest" to achieve here and is not
+ * dependent on the processor type.
+ */
+#define swp_is_buggy
+#endif
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+{
+	extern void __bad_xchg(volatile void *, int);
+	unsigned long ret;
+#ifdef swp_is_buggy
+	unsigned long flags;
+#endif
+
+	switch (size) {
+#ifdef swp_is_buggy
+		case 1:
+			local_irq_save(flags);
+			ret = *(volatile unsigned char *)ptr;
+			*(volatile unsigned char *)ptr = x;
+			local_irq_restore(flags);
+			break;
+
+		case 4:
+			local_irq_save(flags);
+			ret = *(volatile unsigned long *)ptr;
+			*(volatile unsigned long *)ptr = x;
+			local_irq_restore(flags);
+			break;
+#else
+		case 1:	__asm__ __volatile__ ("swpb %0, %1, [%2]"
+					: "=&r" (ret)
+					: "r" (x), "r" (ptr)
+					: "memory");
+			break;
+		case 4:	__asm__ __volatile__ ("swp %0, %1, [%2]"
+					: "=&r" (ret)
+					: "r" (x), "r" (ptr)
+					: "memory");
+			break;
+#endif
+		default: __bad_xchg(ptr, size), ret = 0;
+	}
+
+	return ret;
+}
+
+#endif
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
new file mode 100644
index 0000000..83481c6
--- /dev/null
+++ b/arch/arm/include/asm/processor.h
@@ -0,0 +1,134 @@
+/*
+ *  linux/include/asm-arm/processor.h
+ *
+ *  Copyright (C) 1995-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_PROCESSOR_H
+#define __ASM_ARM_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#define FP_SIZE 35
+
+struct fp_hard_struct {
+	unsigned int save[FP_SIZE];		/* as yet undefined */
+};
+
+struct fp_soft_struct {
+	unsigned int save[FP_SIZE];		/* undefined information */
+};
+
+union fp_state {
+	struct fp_hard_struct	hard;
+	struct fp_soft_struct	soft;
+};
+
+typedef unsigned long mm_segment_t;		/* domain register	*/
+
+#ifdef __KERNEL__
+
+#define EISA_bus 0
+#define MCA_bus 0
+#define MCA_bus__is_a_macro
+
+#include <asm/atomic.h>
+#include <asm/ptrace.h>
+#if 0	/* XXX###XXX */
+#include <asm/arch/memory.h>
+#endif	/* XXX###XXX */
+#include <asm/proc-armv/processor.h>
+#include <asm/types.h>
+
+union debug_insn {
+	u32	arm;
+	u16	thumb;
+};
+
+struct debug_entry {
+	u32			address;
+	union debug_insn	insn;
+};
+
+struct debug_info {
+	int			nsaved;
+	struct debug_entry	bp[2];
+};
+
+struct thread_struct {
+	atomic_t			refcount;
+							/* fault info	  */
+	unsigned long			address;
+	unsigned long			trap_no;
+	unsigned long			error_code;
+							/* floating point */
+	union fp_state			fpstate;
+							/* debugging	  */
+	struct debug_info		debug;
+							/* context info	  */
+	struct context_save_struct	*save;
+	EXTRA_THREAD_STRUCT
+};
+
+#define INIT_THREAD  {					\
+	refcount:	ATOMIC_INIT(1),			\
+	EXTRA_THREAD_STRUCT_INIT			\
+}
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+static inline unsigned long thread_saved_pc(struct thread_struct *t)
+{
+	return t->save ? pc_pointer(t->save->pc) : 0;
+}
+
+static inline unsigned long thread_saved_fp(struct thread_struct *t)
+{
+	return t->save ? t->save->fp : 0;
+}
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+
+/* Copy and release all segment info associated with a VM */
+#define copy_segments(tsk, mm)		do { } while (0)
+#define release_segments(mm)		do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define THREAD_SIZE	(8192)
+
+extern struct task_struct *alloc_task_struct(void);
+extern void __free_task_struct(struct task_struct *);
+#define get_task_struct(p)	atomic_inc(&(p)->thread.refcount)
+#define free_task_struct(p)					\
+ do {								\
+	if (atomic_dec_and_test(&(p)->thread.refcount))		\
+		__free_task_struct((p));			\
+ } while (0)
+
+#define init_task	(init_task_union.task)
+#define init_stack	(init_task_union.stack)
+
+#define cpu_relax()	barrier()
+
+/*
+ * Create a new kernel thread
+ */
+extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+#endif
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
new file mode 100644
index 0000000..95f18e8
--- /dev/null
+++ b/arch/arm/include/asm/psci.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM_PSCI_H__
+#define __ARM_PSCI_H__
+
+#define ARM_PSCI_VER_1_0		(0x00010000)
+#define ARM_PSCI_VER_0_2		(0x00000002)
+
+/* PSCI 0.1 interface */
+#define ARM_PSCI_FN_BASE		0x95c1ba5e
+#define ARM_PSCI_FN(n)			(ARM_PSCI_FN_BASE + (n))
+
+#define ARM_PSCI_FN_CPU_SUSPEND		ARM_PSCI_FN(0)
+#define ARM_PSCI_FN_CPU_OFF		ARM_PSCI_FN(1)
+#define ARM_PSCI_FN_CPU_ON		ARM_PSCI_FN(2)
+#define ARM_PSCI_FN_MIGRATE		ARM_PSCI_FN(3)
+
+#define ARM_PSCI_RET_SUCCESS		0
+#define ARM_PSCI_RET_NI			(-1)
+#define ARM_PSCI_RET_INVAL		(-2)
+#define ARM_PSCI_RET_DENIED		(-3)
+#define ARM_PSCI_RET_ALREADY_ON		(-4)
+#define ARM_PSCI_RET_ON_PENDING		(-5)
+#define ARM_PSCI_RET_INTERNAL_FAILURE	(-6)
+#define ARM_PSCI_RET_NOT_PRESENT	(-7)
+#define ARM_PSCI_RET_DISABLED		(-8)
+#define ARM_PSCI_RET_INVALID_ADDRESS	(-9)
+
+/* PSCI 0.2 interface */
+#define ARM_PSCI_0_2_FN_BASE			0x84000000
+#define ARM_PSCI_0_2_FN(n)			(ARM_PSCI_0_2_FN_BASE + (n))
+
+#define ARM_PSCI_0_2_FN64_BASE			0xC4000000
+#define ARM_PSCI_0_2_FN64(n)			(ARM_PSCI_0_2_FN64_BASE + (n))
+
+#define ARM_PSCI_0_2_FN_PSCI_VERSION		ARM_PSCI_0_2_FN(0)
+#define ARM_PSCI_0_2_FN_CPU_SUSPEND		ARM_PSCI_0_2_FN(1)
+#define ARM_PSCI_0_2_FN_CPU_OFF			ARM_PSCI_0_2_FN(2)
+#define ARM_PSCI_0_2_FN_CPU_ON			ARM_PSCI_0_2_FN(3)
+#define ARM_PSCI_0_2_FN_AFFINITY_INFO		ARM_PSCI_0_2_FN(4)
+#define ARM_PSCI_0_2_FN_MIGRATE			ARM_PSCI_0_2_FN(5)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE	ARM_PSCI_0_2_FN(6)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU	ARM_PSCI_0_2_FN(7)
+#define ARM_PSCI_0_2_FN_SYSTEM_OFF		ARM_PSCI_0_2_FN(8)
+#define ARM_PSCI_0_2_FN_SYSTEM_RESET		ARM_PSCI_0_2_FN(9)
+
+#define ARM_PSCI_0_2_FN64_CPU_SUSPEND		ARM_PSCI_0_2_FN64(1)
+#define ARM_PSCI_0_2_FN64_CPU_ON		ARM_PSCI_0_2_FN64(3)
+#define ARM_PSCI_0_2_FN64_AFFINITY_INFO		ARM_PSCI_0_2_FN64(4)
+#define ARM_PSCI_0_2_FN64_MIGRATE		ARM_PSCI_0_2_FN64(5)
+#define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU	ARM_PSCI_0_2_FN64(7)
+
+/* PSCI 1.0 interface */
+#define ARM_PSCI_1_0_FN_PSCI_FEATURES		ARM_PSCI_0_2_FN(10)
+#define ARM_PSCI_1_0_FN_CPU_FREEZE		ARM_PSCI_0_2_FN(11)
+#define ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND	ARM_PSCI_0_2_FN(12)
+#define ARM_PSCI_1_0_FN_NODE_HW_STATE		ARM_PSCI_0_2_FN(13)
+#define ARM_PSCI_1_0_FN_SYSTEM_SUSPEND		ARM_PSCI_0_2_FN(14)
+#define ARM_PSCI_1_0_FN_SET_SUSPEND_MODE	ARM_PSCI_0_2_FN(15)
+#define ARM_PSCI_1_0_FN_STAT_RESIDENCY		ARM_PSCI_0_2_FN(16)
+#define ARM_PSCI_1_0_FN_STAT_COUNT		ARM_PSCI_0_2_FN(17)
+
+#define ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND	ARM_PSCI_0_2_FN64(12)
+#define ARM_PSCI_1_0_FN64_NODE_HW_STATE		ARM_PSCI_0_2_FN64(13)
+#define ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND	ARM_PSCI_0_2_FN64(14)
+#define ARM_PSCI_1_0_FN64_STAT_RESIDENCY	ARM_PSCI_0_2_FN64(16)
+#define ARM_PSCI_1_0_FN64_STAT_COUNT		ARM_PSCI_0_2_FN64(17)
+
+/* 1KB stack per core */
+#define ARM_PSCI_STACK_SHIFT	10
+#define ARM_PSCI_STACK_SIZE	(1 << ARM_PSCI_STACK_SHIFT)
+
+/* PSCI affinity level state returned by AFFINITY_INFO */
+#define PSCI_AFFINITY_LEVEL_ON		0
+#define PSCI_AFFINITY_LEVEL_OFF		1
+#define PSCI_AFFINITY_LEVEL_ON_PENDING	2
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* These 3 helper functions assume cpu < CONFIG_ARMV7_PSCI_NR_CPUS */
+u32 psci_get_target_pc(int cpu);
+u32 psci_get_context_id(int cpu);
+void psci_save(int cpu, u32 pc, u32 context_id);
+
+void psci_cpu_entry(void);
+u32 psci_get_cpu_id(void);
+void psci_cpu_off_common(void);
+
+int psci_update_dt(void *fdt);
+void psci_board_init(void);
+int fdt_psci(void *fdt);
+
+void psci_v7_flush_dcache_all(void);
+#endif /* ! __ASSEMBLY__ */
+
+#endif /* __ARM_PSCI_H__ */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
new file mode 100644
index 0000000..a836f6c
--- /dev/null
+++ b/arch/arm/include/asm/ptrace.h
@@ -0,0 +1,33 @@
+#ifndef __ASM_ARM_PTRACE_H
+#define __ASM_ARM_PTRACE_H
+
+#define PTRACE_GETREGS		12
+#define PTRACE_SETREGS		13
+#define PTRACE_GETFPREGS	14
+#define PTRACE_SETFPREGS	15
+
+#define PTRACE_SETOPTIONS	21
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD	0x00000001
+
+#include <asm/proc-armv/ptrace.h>
+
+#ifndef __ASSEMBLY__
+#define pc_pointer(v) \
+	((v) & ~PCMASK)
+
+#define instruction_pointer(regs) \
+	(pc_pointer((regs)->ARM_pc))
+
+#ifdef __KERNEL__
+extern void show_regs(struct pt_regs *);
+
+#define predicate(x)	(x & 0xf0000000)
+#define PREDICATE_ALWAYS	0xe0000000
+
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/arm/include/asm/sections.h b/arch/arm/include/asm/sections.h
new file mode 100644
index 0000000..dff3bc2
--- /dev/null
+++ b/arch/arm/include/asm/sections.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_ARM_SECTIONS_H
+#define __ASM_ARM_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
new file mode 100644
index 0000000..50582c9
--- /dev/null
+++ b/arch/arm/include/asm/secure.h
@@ -0,0 +1,60 @@
+#ifndef __ASM_SECURE_H
+#define __ASM_SECURE_H
+
+#include <config.h>
+
+#define __secure __attribute__ ((section ("._secure.text")))
+#define __secure_data __attribute__ ((section ("._secure.data")))
+
+#ifndef __ASSEMBLY__
+
+typedef struct secure_svc_tbl {
+	u32	id;
+#ifdef CONFIG_ARMV8_PSCI
+	u8	pad[4];
+#endif
+	void	*func;
+} secure_svc_tbl_t;
+
+/*
+ * Macro to declare a SiP function service in '_secure_svc_tbl_entries' section
+ */
+#define DECLARE_SECURE_SVC(_name, _id, _fn) \
+	static const secure_svc_tbl_t __secure_svc_ ## _name \
+		__attribute__((used, section("._secure_svc_tbl_entries"))) \
+			 = { \
+				.id = _id, \
+				.func = _fn }
+
+#else
+
+#ifdef CONFIG_ARMV8_PSCI
+#define SECURE_SVC_TBL_OFFSET		16
+#else
+#define SECURE_SVC_TBL_OFFSET		8
+
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
+/*
+ * Warning, horror ahead.
+ *
+ * The target code lives in our "secure ram", but u-boot doesn't know
+ * that, and has blindly added reloc_off to every relocation
+ * entry. Gahh. Do the opposite conversion. This hack also prevents
+ * GCC from generating code veeners, which u-boot doesn't relocate at
+ * all...
+ */
+#define secure_ram_addr(_fn) ({						\
+			DECLARE_GLOBAL_DATA_PTR;			\
+			void *__fn = _fn;				\
+			typeof(_fn) *__tmp = (__fn - gd->reloc_off);	\
+			__tmp;						\
+		})
+#else
+#define secure_ram_addr(_fn)	(_fn)
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h
new file mode 100644
index 0000000..662bec8
--- /dev/null
+++ b/arch/arm/include/asm/setjmp.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ * (C) Copyright 2016 Alexander Graf <agraf@suse.de>
+ */
+
+#ifndef _SETJMP_H_
+#define _SETJMP_H_	1
+
+/*
+ * This really should be opaque, but the EFI implementation wrongly
+ * assumes that a 'struct jmp_buf_data' is defined.
+ */
+struct jmp_buf_data {
+#if defined(__aarch64__)
+	u64  regs[13];
+#else
+	u32  regs[10];  /* r4-r9, sl, fp, sp, lr */
+#endif
+};
+
+typedef struct jmp_buf_data jmp_buf[1];
+
+int setjmp(jmp_buf jmp);
+void longjmp(jmp_buf jmp, int ret);
+
+#endif /* _SETJMP_H_ */
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
new file mode 100644
index 0000000..3a4e902
--- /dev/null
+++ b/arch/arm/include/asm/setup.h
@@ -0,0 +1,274 @@
+/*
+ *  linux/include/asm/setup.h
+ *
+ *  Copyright (C) 1997-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Structure passed to kernel to tell it about the
+ *  hardware it's running on.  See linux/Documentation/arm/Setup
+ *  for more info.
+ *
+ * NOTE:
+ *  This file contains two ways to pass information from the boot
+ *  loader to the kernel. The old struct param_struct is deprecated,
+ *  but it will be kept in the kernel for 5 years from now
+ *  (2001). This will allow boot loaders to convert to the new struct
+ *  tag way.
+ */
+#ifndef __ASMARM_SETUP_H
+#define __ASMARM_SETUP_H
+
+/*
+ * Usage:
+ *  - do not go blindly adding fields, add them at the end
+ *  - when adding fields, don't rely on the address until
+ *    a patch from me has been released
+ *  - unused fields should be zero (for future expansion)
+ *  - this structure is relatively short-lived - only
+ *    guaranteed to contain useful data in setup_arch()
+ */
+#define COMMAND_LINE_SIZE 1024
+
+/* This is the old deprecated way to pass parameters to the kernel */
+struct param_struct {
+    union {
+	struct {
+	    unsigned long page_size;		/*  0 */
+	    unsigned long nr_pages;		/*  4 */
+	    unsigned long ramdisk_size;		/*  8 */
+	    unsigned long flags;		/* 12 */
+#define FLAG_READONLY	1
+#define FLAG_RDLOAD	4
+#define FLAG_RDPROMPT	8
+	    unsigned long rootdev;		/* 16 */
+	    unsigned long video_num_cols;	/* 20 */
+	    unsigned long video_num_rows;	/* 24 */
+	    unsigned long video_x;		/* 28 */
+	    unsigned long video_y;		/* 32 */
+	    unsigned long memc_control_reg;	/* 36 */
+	    unsigned char sounddefault;		/* 40 */
+	    unsigned char adfsdrives;		/* 41 */
+	    unsigned char bytes_per_char_h;	/* 42 */
+	    unsigned char bytes_per_char_v;	/* 43 */
+	    unsigned long pages_in_bank[4];	/* 44 */
+	    unsigned long pages_in_vram;	/* 60 */
+	    unsigned long initrd_start;		/* 64 */
+	    unsigned long initrd_size;		/* 68 */
+	    unsigned long rd_start;		/* 72 */
+	    unsigned long system_rev;		/* 76 */
+	    unsigned long system_serial_low;	/* 80 */
+	    unsigned long system_serial_high;	/* 84 */
+	    unsigned long mem_fclk_21285;       /* 88 */
+	} s;
+	char unused[256];
+    } u1;
+    union {
+	char paths[8][128];
+	struct {
+	    unsigned long magic;
+	    char n[1024 - sizeof(unsigned long)];
+	} s;
+    } u2;
+    char commandline[COMMAND_LINE_SIZE];
+};
+
+
+/*
+ * The new way of passing information: a list of tagged entries
+ */
+
+/* The list ends with an ATAG_NONE node. */
+#define ATAG_NONE	0x00000000
+
+struct tag_header {
+	u32 size;
+	u32 tag;
+};
+
+/* The list must start with an ATAG_CORE node */
+#define ATAG_CORE	0x54410001
+
+struct tag_core {
+	u32 flags;		/* bit 0 = read-only */
+	u32 pagesize;
+	u32 rootdev;
+};
+
+/* it is allowed to have multiple ATAG_MEM nodes */
+#define ATAG_MEM	0x54410002
+
+struct tag_mem32 {
+	u32	size;
+	u32	start;	/* physical start address */
+};
+
+/* VGA text type displays */
+#define ATAG_VIDEOTEXT	0x54410003
+
+struct tag_videotext {
+	u8		x;
+	u8		y;
+	u16		video_page;
+	u8		video_mode;
+	u8		video_cols;
+	u16		video_ega_bx;
+	u8		video_lines;
+	u8		video_isvga;
+	u16		video_points;
+};
+
+/* describes how the ramdisk will be used in kernel */
+#define ATAG_RAMDISK	0x54410004
+
+struct tag_ramdisk {
+	u32 flags;	/* bit 0 = load, bit 1 = prompt */
+	u32 size;	/* decompressed ramdisk size in _kilo_ bytes */
+	u32 start;	/* starting block of floppy-based RAM disk image */
+};
+
+/* describes where the compressed ramdisk image lives (virtual address) */
+/*
+ * this one accidentally used virtual addresses - as such,
+ * it's deprecated.
+ */
+#define ATAG_INITRD	0x54410005
+
+/* describes where the compressed ramdisk image lives (physical address) */
+#define ATAG_INITRD2	0x54420005
+
+struct tag_initrd {
+	u32 start;	/* physical start address */
+	u32 size;	/* size of compressed ramdisk image in bytes */
+};
+
+/* board serial number. "64 bits should be enough for everybody" */
+#define ATAG_SERIAL	0x54410006
+
+struct tag_serialnr {
+	u32 low;
+	u32 high;
+};
+
+/* board revision */
+#define ATAG_REVISION	0x54410007
+
+struct tag_revision {
+	u32 rev;
+};
+
+/* initial values for vesafb-type framebuffers. see struct screen_info
+ * in include/linux/tty.h
+ */
+#define ATAG_VIDEOLFB	0x54410008
+
+struct tag_videolfb {
+	u16		lfb_width;
+	u16		lfb_height;
+	u16		lfb_depth;
+	u16		lfb_linelength;
+	u32		lfb_base;
+	u32		lfb_size;
+	u8		red_size;
+	u8		red_pos;
+	u8		green_size;
+	u8		green_pos;
+	u8		blue_size;
+	u8		blue_pos;
+	u8		rsvd_size;
+	u8		rsvd_pos;
+};
+
+/* command line: \0 terminated string */
+#define ATAG_CMDLINE	0x54410009
+
+struct tag_cmdline {
+	char	cmdline[1];	/* this is the minimum size */
+};
+
+/* acorn RiscPC specific information */
+#define ATAG_ACORN	0x41000101
+
+struct tag_acorn {
+	u32 memc_control_reg;
+	u32 vram_pages;
+	u8 sounddefault;
+	u8 adfsdrives;
+};
+
+/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
+#define ATAG_MEMCLK	0x41000402
+
+struct tag_memclk {
+	u32 fmemclk;
+};
+
+struct tag {
+	struct tag_header hdr;
+	union {
+		struct tag_core		core;
+		struct tag_mem32	mem;
+		struct tag_videotext	videotext;
+		struct tag_ramdisk	ramdisk;
+		struct tag_initrd	initrd;
+		struct tag_serialnr	serialnr;
+		struct tag_revision	revision;
+		struct tag_videolfb	videolfb;
+		struct tag_cmdline	cmdline;
+
+		/*
+		 * Acorn specific
+		 */
+		struct tag_acorn	acorn;
+
+		/*
+		 * DC21285 specific
+		 */
+		struct tag_memclk	memclk;
+	} u;
+};
+
+struct tagtable {
+	u32 tag;
+	int (*parse)(const struct tag *);
+};
+
+#define __tag __attribute__((unused, __section__(".taglist")))
+#define __tagtable(tag, fn) \
+static struct tagtable __tagtable_##fn __tag = { tag, fn }
+
+#define tag_member_present(tag,member)				\
+	((unsigned long)(&((struct tag *)0L)->member + 1)	\
+		<= (tag)->hdr.size * 4)
+
+#define tag_next(t)	((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_size(type)	((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
+
+#define for_each_tag(t,base)		\
+	for (t = base; t->hdr.size; t = tag_next(t))
+
+/*
+ * Memory map description
+ */
+#define NR_BANKS 8
+
+struct meminfo {
+	int nr_banks;
+	unsigned long end;
+	struct {
+		unsigned long start;
+		unsigned long size;
+		int           node;
+	} bank[NR_BANKS];
+};
+
+extern struct meminfo meminfo;
+
+#endif
+
+/*
+ * Board specified tags
+ */
+void setup_board_tags(struct tag **in_params);
diff --git a/arch/arm/include/asm/spin_table.h b/arch/arm/include/asm/spin_table.h
new file mode 100644
index 0000000..dec18c6
--- /dev/null
+++ b/arch/arm/include/asm/spin_table.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASM_SPIN_TABLE_H__
+#define __ASM_SPIN_TABLE_H__
+
+extern u64 spin_table_cpu_release_addr;
+extern char spin_table_reserve_begin;
+extern char spin_table_reserve_end;
+
+int spin_table_update_dt(void *fdt);
+
+#endif /* __ASM_SPIN_TABLE_H__ */
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
new file mode 100644
index 0000000..e568af2
--- /dev/null
+++ b/arch/arm/include/asm/spl.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef	_ASM_SPL_H_
+#define	_ASM_SPL_H_
+
+#if defined(CONFIG_ARCH_OMAP2PLUS) \
+	|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
+	|| defined(CONFIG_EXYNOS4210) || defined(CONFIG_ARCH_K3)
+/* Platform-specific defines */
+#include <asm/arch/spl.h>
+
+#else
+enum {
+	BOOT_DEVICE_RAM,
+	BOOT_DEVICE_MMC1,
+	BOOT_DEVICE_MMC2,
+	BOOT_DEVICE_MMC2_2,
+	BOOT_DEVICE_NAND,
+	BOOT_DEVICE_ONENAND,
+	BOOT_DEVICE_NOR,
+	BOOT_DEVICE_UART,
+	BOOT_DEVICE_SPI,
+	BOOT_DEVICE_USB,
+	BOOT_DEVICE_SATA,
+	BOOT_DEVICE_I2C,
+	BOOT_DEVICE_BOARD,
+	BOOT_DEVICE_DFU,
+	BOOT_DEVICE_XIP,
+	BOOT_DEVICE_BOOTROM,
+	BOOT_DEVICE_NONE
+};
+#endif
+
+/* Linker symbols. */
+extern char __bss_start[], __bss_end[];
+
+#ifndef CONFIG_DM
+extern gd_t gdata;
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h
new file mode 100644
index 0000000..11eaa34
--- /dev/null
+++ b/arch/arm/include/asm/string.h
@@ -0,0 +1,53 @@
+#ifndef __ASM_ARM_STRING_H
+#define __ASM_ARM_STRING_H
+
+#include <config.h>
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char * strrchr(const char * s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char * strchr(const char * s, int c);
+
+#if CONFIG_IS_ENABLED(USE_ARCH_MEMCPY)
+#define __HAVE_ARCH_MEMCPY
+#endif
+extern void * memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void * memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#if CONFIG_IS_ENABLED(USE_ARCH_MEMSET)
+#define __HAVE_ARCH_MEMSET
+#endif
+extern void * memset(void *, int, __kernel_size_t);
+
+#if 0
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p,v,n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p),(n));			\
+			else						\
+				memset((p),(v),(n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
new file mode 100644
index 0000000..a1a5e35
--- /dev/null
+++ b/arch/arm/include/asm/system.h
@@ -0,0 +1,591 @@
+#ifndef __ASM_ARM_SYSTEM_H
+#define __ASM_ARM_SYSTEM_H
+
+#include <common.h>
+#include <linux/compiler.h>
+#include <asm/barriers.h>
+
+#ifdef CONFIG_ARM64
+
+/*
+ * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
+ */
+#define CR_M		(1 << 0)	/* MMU enable			*/
+#define CR_A		(1 << 1)	/* Alignment abort enable	*/
+#define CR_C		(1 << 2)	/* Dcache enable		*/
+#define CR_SA		(1 << 3)	/* Stack Alignment Check Enable	*/
+#define CR_I		(1 << 12)	/* Icache enable		*/
+#define CR_WXN		(1 << 19)	/* Write Permision Imply XN	*/
+#define CR_EE		(1 << 25)	/* Exception (Big) Endian	*/
+
+#define ES_TO_AARCH64		1
+#define ES_TO_AARCH32		0
+
+/*
+ * SCR_EL3 bits definitions
+ */
+#define SCR_EL3_RW_AARCH64	(1 << 10) /* Next lower level is AArch64     */
+#define SCR_EL3_RW_AARCH32	(0 << 10) /* Lower lowers level are AArch32  */
+#define SCR_EL3_HCE_EN		(1 << 8)  /* Hypervisor Call enable          */
+#define SCR_EL3_SMD_DIS		(1 << 7)  /* Secure Monitor Call disable     */
+#define SCR_EL3_RES1		(3 << 4)  /* Reserved, RES1                  */
+#define SCR_EL3_EA_EN		(1 << 3)  /* External aborts taken to EL3    */
+#define SCR_EL3_NS_EN		(1 << 0)  /* EL0 and EL1 in Non-scure state  */
+
+/*
+ * SPSR_EL3/SPSR_EL2 bits definitions
+ */
+#define SPSR_EL_END_LE		(0 << 9)  /* Exception Little-endian          */
+#define SPSR_EL_DEBUG_MASK	(1 << 9)  /* Debug exception masked           */
+#define SPSR_EL_ASYN_MASK	(1 << 8)  /* Asynchronous data abort masked   */
+#define SPSR_EL_SERR_MASK	(1 << 8)  /* System Error exception masked    */
+#define SPSR_EL_IRQ_MASK	(1 << 7)  /* IRQ exception masked             */
+#define SPSR_EL_FIQ_MASK	(1 << 6)  /* FIQ exception masked             */
+#define SPSR_EL_T_A32		(0 << 5)  /* AArch32 instruction set A32      */
+#define SPSR_EL_M_AARCH64	(0 << 4)  /* Exception taken from AArch64     */
+#define SPSR_EL_M_AARCH32	(1 << 4)  /* Exception taken from AArch32     */
+#define SPSR_EL_M_SVC		(0x3)     /* Exception taken from SVC mode    */
+#define SPSR_EL_M_HYP		(0xa)     /* Exception taken from HYP mode    */
+#define SPSR_EL_M_EL1H		(5)       /* Exception taken from EL1h mode   */
+#define SPSR_EL_M_EL2H		(9)       /* Exception taken from EL2h mode   */
+
+/*
+ * CPTR_EL2 bits definitions
+ */
+#define CPTR_EL2_RES1		(3 << 12 | 0x3ff)           /* Reserved, RES1 */
+
+/*
+ * SCTLR_EL2 bits definitions
+ */
+#define SCTLR_EL2_RES1		(3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\
+				 1 << 11 | 3 << 4)	    /* Reserved, RES1 */
+#define SCTLR_EL2_EE_LE		(0 << 25) /* Exception Little-endian          */
+#define SCTLR_EL2_WXN_DIS	(0 << 19) /* Write permission is not XN       */
+#define SCTLR_EL2_ICACHE_DIS	(0 << 12) /* Instruction cache disabled       */
+#define SCTLR_EL2_SA_DIS	(0 << 3)  /* Stack Alignment Check disabled   */
+#define SCTLR_EL2_DCACHE_DIS	(0 << 2)  /* Data cache disabled              */
+#define SCTLR_EL2_ALIGN_DIS	(0 << 1)  /* Alignment check disabled         */
+#define SCTLR_EL2_MMU_DIS	(0)       /* MMU disabled                     */
+
+/*
+ * CNTHCTL_EL2 bits definitions
+ */
+#define CNTHCTL_EL2_EL1PCEN_EN	(1 << 1)  /* Physical timer regs accessible   */
+#define CNTHCTL_EL2_EL1PCTEN_EN	(1 << 0)  /* Physical counter accessible      */
+
+/*
+ * HCR_EL2 bits definitions
+ */
+#define HCR_EL2_RW_AARCH64	(1 << 31) /* EL1 is AArch64                   */
+#define HCR_EL2_RW_AARCH32	(0 << 31) /* Lower levels are AArch32         */
+#define HCR_EL2_HCD_DIS		(1 << 29) /* Hypervisor Call disabled         */
+
+/*
+ * CPACR_EL1 bits definitions
+ */
+#define CPACR_EL1_FPEN_EN	(3 << 20) /* SIMD and FP instruction enabled  */
+
+/*
+ * SCTLR_EL1 bits definitions
+ */
+#define SCTLR_EL1_RES1		(3 << 28 | 3 << 22 | 1 << 20 |\
+				 1 << 11) /* Reserved, RES1                   */
+#define SCTLR_EL1_UCI_DIS	(0 << 26) /* Cache instruction disabled       */
+#define SCTLR_EL1_EE_LE		(0 << 25) /* Exception Little-endian          */
+#define SCTLR_EL1_WXN_DIS	(0 << 19) /* Write permission is not XN       */
+#define SCTLR_EL1_NTWE_DIS	(0 << 18) /* WFE instruction disabled         */
+#define SCTLR_EL1_NTWI_DIS	(0 << 16) /* WFI instruction disabled         */
+#define SCTLR_EL1_UCT_DIS	(0 << 15) /* CTR_EL0 access disabled          */
+#define SCTLR_EL1_DZE_DIS	(0 << 14) /* DC ZVA instruction disabled      */
+#define SCTLR_EL1_ICACHE_DIS	(0 << 12) /* Instruction cache disabled       */
+#define SCTLR_EL1_UMA_DIS	(0 << 9)  /* User Mask Access disabled        */
+#define SCTLR_EL1_SED_EN	(0 << 8)  /* SETEND instruction enabled       */
+#define SCTLR_EL1_ITD_EN	(0 << 7)  /* IT instruction enabled           */
+#define SCTLR_EL1_CP15BEN_DIS	(0 << 5)  /* CP15 barrier operation disabled  */
+#define SCTLR_EL1_SA0_DIS	(0 << 4)  /* Stack Alignment EL0 disabled     */
+#define SCTLR_EL1_SA_DIS	(0 << 3)  /* Stack Alignment EL1 disabled     */
+#define SCTLR_EL1_DCACHE_DIS	(0 << 2)  /* Data cache disabled              */
+#define SCTLR_EL1_ALIGN_DIS	(0 << 1)  /* Alignment check disabled         */
+#define SCTLR_EL1_MMU_DIS	(0)       /* MMU disabled                     */
+
+#ifndef __ASSEMBLY__
+
+u64 get_page_table_size(void);
+#define PGTABLE_SIZE	get_page_table_size()
+
+/* 2MB granularity */
+#define MMU_SECTION_SHIFT	21
+#define MMU_SECTION_SIZE	(1 << MMU_SECTION_SHIFT)
+
+/* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
+enum dcache_option {
+	DCACHE_OFF = 0 << 2,
+	DCACHE_WRITETHROUGH = 3 << 2,
+	DCACHE_WRITEBACK = 4 << 2,
+	DCACHE_WRITEALLOC = 4 << 2,
+};
+
+#define wfi()				\
+	({asm volatile(			\
+	"wfi" : : : "memory");		\
+	})
+
+static inline unsigned int current_el(void)
+{
+	unsigned int el;
+	asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
+	return el >> 2;
+}
+
+static inline unsigned int get_sctlr(void)
+{
+	unsigned int el, val;
+
+	el = current_el();
+	if (el == 1)
+		asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
+	else if (el == 2)
+		asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
+	else
+		asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
+
+	return val;
+}
+
+static inline void set_sctlr(unsigned int val)
+{
+	unsigned int el;
+
+	el = current_el();
+	if (el == 1)
+		asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
+	else if (el == 2)
+		asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
+	else
+		asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
+
+	asm volatile("isb");
+}
+
+static inline unsigned long read_mpidr(void)
+{
+	unsigned long val;
+
+	asm volatile("mrs %0, mpidr_el1" : "=r" (val));
+
+	return val;
+}
+
+#define BSP_COREID	0
+
+void __asm_flush_dcache_all(void);
+void __asm_invalidate_dcache_all(void);
+void __asm_flush_dcache_range(u64 start, u64 end);
+
+/**
+ * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses
+ *
+ * This performance an invalidate from @start to @end - 1. Both addresses
+ * should be cache-aligned, otherwise this function will align the start
+ * address and may continue past the end address.
+ *
+ * Data in the address range is evicted from the cache and is not written back
+ * to memory.
+ *
+ * @start: Start address to invalidate
+ * @end: End address to invalidate up to (exclusive)
+ */
+void __asm_invalidate_dcache_range(u64 start, u64 end);
+void __asm_invalidate_tlb_all(void);
+void __asm_invalidate_icache_all(void);
+int __asm_invalidate_l3_dcache(void);
+int __asm_flush_l3_dcache(void);
+int __asm_invalidate_l3_icache(void);
+void __asm_switch_ttbr(u64 new_ttbr);
+
+/*
+ * Switch from EL3 to EL2 for ARMv8
+ *
+ * @args:        For loading 64-bit OS, fdt address.
+ *               For loading 32-bit OS, zero.
+ * @mach_nr:     For loading 64-bit OS, zero.
+ *               For loading 32-bit OS, machine nr
+ * @fdt_addr:    For loading 64-bit OS, zero.
+ *               For loading 32-bit OS, fdt address.
+ * @arg4:	 Input argument.
+ * @entry_point: kernel entry point
+ * @es_flag:     execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
+ */
+void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
+				    u64 arg4, u64 entry_point, u64 es_flag);
+/*
+ * Switch from EL2 to EL1 for ARMv8
+ *
+ * @args:        For loading 64-bit OS, fdt address.
+ *               For loading 32-bit OS, zero.
+ * @mach_nr:     For loading 64-bit OS, zero.
+ *               For loading 32-bit OS, machine nr
+ * @fdt_addr:    For loading 64-bit OS, zero.
+ *               For loading 32-bit OS, fdt address.
+ * @arg4:	 Input argument.
+ * @entry_point: kernel entry point
+ * @es_flag:     execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
+ */
+void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr,
+			 u64 arg4, u64 entry_point, u64 es_flag);
+void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr,
+			  u64 arg4, u64 entry_point);
+void gic_init(void);
+void gic_send_sgi(unsigned long sgino);
+void wait_for_wakeup(void);
+void protect_secure_region(void);
+void smp_kick_all_cpus(void);
+
+void flush_l3_cache(void);
+void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
+
+/*
+ *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
+ * DEN0028A
+ *
+ * @args: input and output arguments
+ *
+ */
+void smc_call(struct pt_regs *args);
+
+void __noreturn psci_system_reset(void);
+void __noreturn psci_system_off(void);
+
+#ifdef CONFIG_ARMV8_PSCI
+extern char __secure_start[];
+extern char __secure_end[];
+extern char __secure_stack_start[];
+extern char __secure_stack_end[];
+
+void armv8_setup_psci(void);
+void psci_setup_vectors(void);
+void psci_arch_init(void);
+#endif
+
+#endif	/* __ASSEMBLY__ */
+
+#else /* CONFIG_ARM64 */
+
+#ifdef __KERNEL__
+
+#define CPU_ARCH_UNKNOWN	0
+#define CPU_ARCH_ARMv3		1
+#define CPU_ARCH_ARMv4		2
+#define CPU_ARCH_ARMv4T		3
+#define CPU_ARCH_ARMv5		4
+#define CPU_ARCH_ARMv5T		5
+#define CPU_ARCH_ARMv5TE	6
+#define CPU_ARCH_ARMv5TEJ	7
+#define CPU_ARCH_ARMv6		8
+#define CPU_ARCH_ARMv7		9
+
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M	(1 << 0)	/* MMU enable				*/
+#define CR_A	(1 << 1)	/* Alignment abort enable		*/
+#define CR_C	(1 << 2)	/* Dcache enable			*/
+#define CR_W	(1 << 3)	/* Write buffer enable			*/
+#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
+#define CR_D	(1 << 5)	/* 32-bit data address range		*/
+#define CR_L	(1 << 6)	/* Implementation defined		*/
+#define CR_B	(1 << 7)	/* Big endian				*/
+#define CR_S	(1 << 8)	/* System MMU protection		*/
+#define CR_R	(1 << 9)	/* ROM MMU protection			*/
+#define CR_F	(1 << 10)	/* Implementation defined		*/
+#define CR_Z	(1 << 11)	/* Implementation defined		*/
+#define CR_I	(1 << 12)	/* Icache enable			*/
+#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
+#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
+#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/
+#define CR_DT	(1 << 16)
+#define CR_IT	(1 << 18)
+#define CR_ST	(1 << 19)
+#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/
+#define CR_U	(1 << 22)	/* Unaligned access operation		*/
+#define CR_XP	(1 << 23)	/* Extended page tables			*/
+#define CR_VE	(1 << 24)	/* Vectored interrupts			*/
+#define CR_EE	(1 << 25)	/* Exception (Big) Endian		*/
+#define CR_TRE	(1 << 28)	/* TEX remap enable			*/
+#define CR_AFE	(1 << 29)	/* Access flag enable			*/
+#define CR_TE	(1 << 30)	/* Thumb exception enable		*/
+
+#if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
+#define PGTABLE_SIZE		(4096 * 5)
+#elif !defined(PGTABLE_SIZE)
+#define PGTABLE_SIZE		(4096 * 4)
+#endif
+
+/*
+ * This is used to ensure the compiler did actually allocate the register we
+ * asked it for some inline assembly sequences.  Apparently we can't trust
+ * the compiler from one version to another so a bit of paranoia won't hurt.
+ * This string is meant to be concatenated with the inline asm string and
+ * will cause compilation to stop on mismatch.
+ * (for details, see gcc PR 15089)
+ */
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_ARMV7_LPAE
+void switch_to_hypervisor_ret(void);
+#endif
+
+#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
+
+#ifdef __ARM_ARCH_7A__
+#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
+#else
+#define wfi()
+#endif
+
+static inline unsigned long get_cpsr(void)
+{
+	unsigned long cpsr;
+
+	asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
+	return cpsr;
+}
+
+static inline int is_hyp(void)
+{
+#ifdef CONFIG_ARMV7_LPAE
+	/* HYP mode requires LPAE ... */
+	return ((get_cpsr() & 0x1f) == 0x1a);
+#else
+	/* ... so without LPAE support we can optimize all hyp code away */
+	return 0;
+#endif
+}
+
+static inline unsigned int get_cr(void)
+{
+	unsigned int val;
+
+	if (is_hyp())
+		asm volatile("mrc p15, 4, %0, c1, c0, 0	@ get CR" : "=r" (val)
+								  :
+								  : "cc");
+	else
+		asm volatile("mrc p15, 0, %0, c1, c0, 0	@ get CR" : "=r" (val)
+								  :
+								  : "cc");
+	return val;
+}
+
+static inline void set_cr(unsigned int val)
+{
+	if (is_hyp())
+		asm volatile("mcr p15, 4, %0, c1, c0, 0	@ set CR" :
+								  : "r" (val)
+								  : "cc");
+	else
+		asm volatile("mcr p15, 0, %0, c1, c0, 0	@ set CR" :
+								  : "r" (val)
+								  : "cc");
+	isb();
+}
+
+static inline unsigned int get_dacr(void)
+{
+	unsigned int val;
+	asm("mrc p15, 0, %0, c3, c0, 0	@ get DACR" : "=r" (val) : : "cc");
+	return val;
+}
+
+static inline void set_dacr(unsigned int val)
+{
+	asm volatile("mcr p15, 0, %0, c3, c0, 0	@ set DACR"
+	  : : "r" (val) : "cc");
+	isb();
+}
+
+#ifdef CONFIG_ARMV7_LPAE
+/* Long-Descriptor Translation Table Level 1/2 Bits */
+#define TTB_SECT_XN_MASK	(1ULL << 54)
+#define TTB_SECT_NG_MASK	(1 << 11)
+#define TTB_SECT_AF		(1 << 10)
+#define TTB_SECT_SH_MASK	(3 << 8)
+#define TTB_SECT_NS_MASK	(1 << 5)
+#define TTB_SECT_AP		(1 << 6)
+/* Note: TTB AP bits are set elsewhere */
+#define TTB_SECT_MAIR(x)	((x & 0x7) << 2) /* Index into MAIR */
+#define TTB_SECT		(1 << 0)
+#define TTB_PAGETABLE		(3 << 0)
+
+/* TTBCR flags */
+#define TTBCR_EAE		(1 << 31)
+#define TTBCR_T0SZ(x)		((x) << 0)
+#define TTBCR_T1SZ(x)		((x) << 16)
+#define TTBCR_USING_TTBR0	(TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
+#define TTBCR_IRGN0_NC		(0 << 8)
+#define TTBCR_IRGN0_WBWA	(1 << 8)
+#define TTBCR_IRGN0_WT		(2 << 8)
+#define TTBCR_IRGN0_WBNWA	(3 << 8)
+#define TTBCR_IRGN0_MASK	(3 << 8)
+#define TTBCR_ORGN0_NC		(0 << 10)
+#define TTBCR_ORGN0_WBWA	(1 << 10)
+#define TTBCR_ORGN0_WT		(2 << 10)
+#define TTBCR_ORGN0_WBNWA	(3 << 10)
+#define TTBCR_ORGN0_MASK	(3 << 10)
+#define TTBCR_SHARED_NON	(0 << 12)
+#define TTBCR_SHARED_OUTER	(2 << 12)
+#define TTBCR_SHARED_INNER	(3 << 12)
+#define TTBCR_EPD0		(0 << 7)
+
+/*
+ * Memory types
+ */
+#define MEMORY_ATTRIBUTES	((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
+				 (0xcc << (2 * 8)) | (0xff << (3 * 8)))
+
+/* options available for data cache on each page */
+enum dcache_option {
+	DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
+	DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
+	DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
+	DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
+};
+#elif defined(CONFIG_CPU_V7A)
+/* Short-Descriptor Translation Table Level 1 Bits */
+#define TTB_SECT_NS_MASK	(1 << 19)
+#define TTB_SECT_NG_MASK	(1 << 17)
+#define TTB_SECT_S_MASK		(1 << 16)
+/* Note: TTB AP bits are set elsewhere */
+#define TTB_SECT_AP		(3 << 10)
+#define TTB_SECT_TEX(x)		((x & 0x7) << 12)
+#define TTB_SECT_DOMAIN(x)	((x & 0xf) << 5)
+#define TTB_SECT_XN_MASK	(1 << 4)
+#define TTB_SECT_C_MASK		(1 << 3)
+#define TTB_SECT_B_MASK		(1 << 2)
+#define TTB_SECT			(2 << 0)
+
+/* options available for data cache on each page */
+enum dcache_option {
+	DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
+	DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
+	DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
+	DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
+};
+#else
+#define TTB_SECT_AP		(3 << 10)
+/* options available for data cache on each page */
+enum dcache_option {
+	DCACHE_OFF = 0x12,
+	DCACHE_WRITETHROUGH = 0x1a,
+	DCACHE_WRITEBACK = 0x1e,
+	DCACHE_WRITEALLOC = 0x16,
+};
+#endif
+
+/* Size of an MMU section */
+enum {
+#ifdef CONFIG_ARMV7_LPAE
+	MMU_SECTION_SHIFT	= 21, /* 2MB */
+#else
+	MMU_SECTION_SHIFT	= 20, /* 1MB */
+#endif
+	MMU_SECTION_SIZE	= 1 << MMU_SECTION_SHIFT,
+};
+
+#ifdef CONFIG_CPU_V7A
+/* TTBR0 bits */
+#define TTBR0_BASE_ADDR_MASK	0xFFFFC000
+#define TTBR0_RGN_NC			(0 << 3)
+#define TTBR0_RGN_WBWA			(1 << 3)
+#define TTBR0_RGN_WT			(2 << 3)
+#define TTBR0_RGN_WB			(3 << 3)
+/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
+#define TTBR0_IRGN_NC			(0 << 0 | 0 << 6)
+#define TTBR0_IRGN_WBWA			(0 << 0 | 1 << 6)
+#define TTBR0_IRGN_WT			(1 << 0 | 0 << 6)
+#define TTBR0_IRGN_WB			(1 << 0 | 1 << 6)
+#endif
+
+/**
+ * Register an update to the page tables, and flush the TLB
+ *
+ * \param start		start address of update in page table
+ * \param stop		stop address of update in page table
+ */
+void mmu_page_table_flush(unsigned long start, unsigned long stop);
+
+#ifdef CONFIG_ARMV7_PSCI
+void psci_arch_cpu_entry(void);
+u32 psci_version(void);
+s32 psci_features(u32 function_id, u32 psci_fid);
+s32 psci_cpu_off(void);
+s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
+		u32 context_id);
+s32 psci_affinity_info(u32 function_id, u32 target_affinity,
+		       u32  lowest_affinity_level);
+u32 psci_migrate_info_type(void);
+void psci_system_off(void);
+void psci_system_reset(void);
+s32 psci_features(u32 function_id, u32 psci_fid);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#define arch_align_stack(x) (x)
+
+#endif /* __KERNEL__ */
+
+#endif /* CONFIG_ARM64 */
+
+#ifndef __ASSEMBLY__
+/**
+ * save_boot_params() - Save boot parameters before starting reset sequence
+ *
+ * If you provide this function it will be called immediately U-Boot starts,
+ * both for SPL and U-Boot proper.
+ *
+ * All registers are unchanged from U-Boot entry. No registers need be
+ * preserved.
+ *
+ * This is not a normal C function. There is no stack. Return by branching to
+ * save_boot_params_ret.
+ *
+ * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
+ */
+
+/**
+ * save_boot_params_ret() - Return from save_boot_params()
+ *
+ * If you provide save_boot_params(), then you should jump back to this
+ * function when done. Try to preserve all registers.
+ *
+ * If your implementation of save_boot_params() is in C then it is acceptable
+ * to simply call save_boot_params_ret() at the end of your function. Since
+ * there is no link register set up, you cannot just exit the function. U-Boot
+ * will return to the (initialised) value of lr, and likely crash/hang.
+ *
+ * If your implementation of save_boot_params() is in assembler then you
+ * should use 'b' or 'bx' to return to save_boot_params_ret.
+ */
+void save_boot_params_ret(void);
+
+/**
+ * Change the cache settings for a region.
+ *
+ * \param start		start address of memory region to change
+ * \param size		size of memory region to change
+ * \param option	dcache option to select
+ */
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+				     enum dcache_option option);
+
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+void noncached_init(void);
+phys_addr_t noncached_alloc(size_t size, size_t align);
+#endif /* CONFIG_SYS_NONCACHED_MEMORY */
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h
new file mode 100644
index 0000000..28842c3
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/davinci_nand.h
@@ -0,0 +1,98 @@
+/*
+ * NAND Flash Driver
+ *
+ * Copyright (C) 2006-2014 Texas Instruments.
+ *
+ * Based on Linux DaVinci NAND driver by TI.
+ */
+
+#ifndef _DAVINCI_NAND_H_
+#define _DAVINCI_NAND_H_
+
+#include <linux/mtd/rawnand.h>
+#include <asm/arch/hardware.h>
+
+#define NAND_READ_START  	0x00
+#define NAND_READ_END    	0x30
+#define NAND_STATUS      	0x70
+
+#define MASK_CLE		0x10
+#define MASK_ALE		0x08
+
+#ifdef CONFIG_SYS_NAND_MASK_CLE
+#undef MASK_CLE
+#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
+#endif
+#ifdef CONFIG_SYS_NAND_MASK_ALE
+#undef MASK_ALE
+#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
+#endif
+
+struct davinci_emif_regs {
+	uint32_t	ercsr;
+	uint32_t	awccr;
+	uint32_t	sdbcr;
+	uint32_t	sdrcr;
+	union {
+		uint32_t abncr[4];
+		struct {
+			uint32_t ab1cr;
+			uint32_t ab2cr;
+			uint32_t ab3cr;
+			uint32_t ab4cr;
+		};
+	};
+	uint32_t	sdtimr;
+	uint32_t	ddrsr;
+	uint32_t	ddrphycr;
+	uint32_t	ddrphysr;
+	uint32_t	totar;
+	uint32_t	totactr;
+	uint32_t	ddrphyid_rev;
+	uint32_t	sdsretr;
+	uint32_t	eirr;
+	uint32_t	eimr;
+	uint32_t	eimsr;
+	uint32_t	eimcr;
+	uint32_t	ioctrlr;
+	uint32_t	iostatr;
+	uint32_t	rsvd0;
+	uint32_t	one_nand_cr;
+	uint32_t	nandfcr;
+	uint32_t	nandfsr;
+	uint32_t	rsvd1[2];
+	uint32_t	nandfecc[4];
+	uint32_t	rsvd2[15];
+	uint32_t	nand4biteccload;
+	uint32_t	nand4bitecc[4];
+	uint32_t	nanderradd1;
+	uint32_t	nanderradd2;
+	uint32_t	nanderrval1;
+	uint32_t	nanderrval2;
+};
+
+#define davinci_emif_regs \
+	((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
+
+#define DAVINCI_NANDFCR_NAND_ENABLE(n)			(1 << ((n) - 2))
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK		(3 << 4)
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n)			(((n) - 2) << 4)
+#define DAVINCI_NANDFCR_1BIT_ECC_START(n)		(1 << (8 + ((n) - 2)))
+#define DAVINCI_NANDFCR_4BIT_ECC_START			(1 << 12)
+#define DAVINCI_NANDFCR_4BIT_CALC_START			(1 << 13)
+#define DAVINCI_NANDFCR_CS2NAND				(1 << 0)
+
+/* Chip Select setup */
+#define DAVINCI_ABCR_STROBE_SELECT			(1 << 31)
+#define DAVINCI_ABCR_EXT_WAIT				(1 << 30)
+#define DAVINCI_ABCR_WSETUP(n)				(n << 26)
+#define DAVINCI_ABCR_WSTROBE(n)				(n << 20)
+#define DAVINCI_ABCR_WHOLD(n)				(n << 17)
+#define DAVINCI_ABCR_RSETUP(n)				(n << 13)
+#define DAVINCI_ABCR_RSTROBE(n)				(n << 7)
+#define DAVINCI_ABCR_RHOLD(n)				(n << 4)
+#define DAVINCI_ABCR_TA(n)				(n << 2)
+#define DAVINCI_ABCR_ASIZE_16BIT			1
+#define DAVINCI_ABCR_ASIZE_8BIT				0
+
+#endif
diff --git a/arch/arm/include/asm/ti-common/keystone_nav.h b/arch/arm/include/asm/ti-common/keystone_nav.h
new file mode 100644
index 0000000..e577514
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/keystone_nav.h
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Multicore Navigator definitions
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef _KEYSTONE_NAV_H_
+#define _KEYSTONE_NAV_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define QM_OK                    0
+#define QM_ERR                  -1
+#define QM_DESC_TYPE_HOST        0
+#define QM_DESC_PSINFO_IN_DESCR  0
+#define QM_DESC_DEFAULT_DESCINFO    (QM_DESC_TYPE_HOST << 30) | \
+					(QM_DESC_PSINFO_IN_DESCR << 22)
+
+/* Packet Info */
+#define QM_DESC_PINFO_EPIB              1
+#define QM_DESC_PINFO_RETURN_OWN        1
+#define QM_DESC_DEFAULT_PINFO           (QM_DESC_PINFO_EPIB << 31) | \
+					(QM_DESC_PINFO_RETURN_OWN << 15)
+
+struct qm_cfg_reg {
+	u32	revision;
+	u32	__pad1;
+	u32	divert;
+	u32	link_ram_base0;
+	u32	link_ram_size0;
+	u32	link_ram_base1;
+	u32	link_ram_size1;
+	u32	link_ram_base2;
+	u32	starvation[0];
+};
+
+struct	descr_mem_setup_reg {
+	u32	base_addr;
+	u32	start_idx;
+	u32	desc_reg_size;
+	u32	_res0;
+};
+
+struct qm_reg_queue {
+	u32	entry_count;
+	u32	byte_count;
+	u32	packet_size;
+	u32	ptr_size_thresh;
+};
+
+struct qm_config {
+	/* QM module addresses */
+	u32	stat_cfg;	/* status and config		*/
+	struct qm_reg_queue *queue;	/* management region	*/
+	u32	mngr_vbusm;	/* management region (VBUSM)	*/
+	u32	i_lram;		/* internal linking RAM		*/
+	struct qm_reg_queue *proxy;
+	u32	status_ram;
+	struct qm_cfg_reg *mngr_cfg;
+				/* Queue manager config region	*/
+	u32	intd_cfg;	/* QMSS INTD config region	*/
+	struct	descr_mem_setup_reg *desc_mem;
+				/* descritor memory setup region*/
+	u32	region_num;
+	u32	pdsp_cmd;	/* PDSP1 command interface	*/
+	u32	pdsp_ctl;	/* PDSP1 control registers	*/
+	u32	pdsp_iram;
+	/* QM configuration parameters */
+
+	u32	qpool_num;	/* */
+};
+
+struct qm_host_desc {
+	u32 desc_info;
+	u32 tag_info;
+	u32 packet_info;
+	u32 buff_len;
+	u32 buff_ptr;
+	u32 next_bdptr;
+	u32 orig_buff_len;
+	u32 orig_buff_ptr;
+	u32 timestamp;
+	u32 swinfo[3];
+	u32 ps_data[20];
+};
+
+#define HDESC_NUM        256
+
+int	qm_init(void);
+void	qm_close(void);
+void	qm_push(struct qm_host_desc *hd, u32 qnum);
+struct qm_host_desc *qm_pop(u32 qnum);
+
+void	qm_buff_push(struct qm_host_desc *hd, u32 qnum,
+		     void *buff_ptr, u32 buff_len);
+
+struct	qm_host_desc *qm_pop_from_free_pool(void);
+void	queue_close(u32 qnum);
+
+/*
+ * DMA API
+ */
+#define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \
+				     psloc, sopoff, qmgr, qnum) \
+	(((einfo & 1) << 30)  | \
+	 ((psinfo & 1) << 29) | \
+	 ((rxerr & 1) << 28)  | \
+	 ((desc & 3) << 26)   | \
+	 ((psloc & 1) << 25)  | \
+	 ((sopoff & 0x1ff) << 16) | \
+	 ((qmgr & 3) << 12)   | \
+	 ((qnum & 0xfff) << 0))
+
+#define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \
+	(((fd0qm & 3) << 28)  | \
+	 ((fd0qnum & 0xfff) << 16) | \
+	 ((fd1qm & 3) << 12)  | \
+	 ((fd1qnum & 0xfff) <<  0))
+
+#define CPDMA_CHAN_A_ENABLE ((u32)1 << 31)
+#define CPDMA_CHAN_A_TDOWN  (1 << 30)
+#define TDOWN_TIMEOUT_COUNT  100
+
+struct global_ctl_regs {
+	u32	revision;
+	u32	perf_control;
+	u32	emulation_control;
+	u32	priority_control;
+	u32	qm_base_addr[4];
+};
+
+struct tx_chan_regs {
+	u32	cfg_a;
+	u32	cfg_b;
+	u32	res[6];
+};
+
+struct rx_chan_regs {
+	u32	cfg_a;
+	u32	res[7];
+};
+
+struct rx_flow_regs {
+	u32	control;
+	u32	tags;
+	u32	tag_sel;
+	u32	fdq_sel[2];
+	u32	thresh[3];
+};
+
+struct pktdma_cfg {
+	struct global_ctl_regs	*global;
+	struct tx_chan_regs	*tx_ch;
+	u32			tx_ch_num;
+	struct rx_chan_regs	*rx_ch;
+	u32			rx_ch_num;
+	u32			*tx_sched;
+	struct rx_flow_regs	*rx_flows;
+	u32			rx_flow_num;
+
+	u32			rx_free_q;
+	u32			rx_rcv_q;
+	u32			tx_snd_q;
+
+	u32			rx_flow; /* flow that is used for RX */
+};
+
+extern struct pktdma_cfg netcp_pktdma;
+
+/*
+ * packet dma user allocates memory for rx buffers
+ * and describe it in the following structure
+ */
+struct rx_buff_desc {
+	u8	*buff_ptr;
+	u32	num_buffs;
+	u32	buff_len;
+	u32	rx_flow;
+};
+
+int ksnav_close(struct pktdma_cfg *pktdma);
+int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers);
+int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2);
+void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes);
+void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
+
+#endif  /* _KEYSTONE_NAV_H_ */
diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h
new file mode 100644
index 0000000..bba1048
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/keystone_net.h
@@ -0,0 +1,232 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * emac definitions for keystone2 devices
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef _KEYSTONE_NET_H_
+#define _KEYSTONE_NET_H_
+
+#include <asm/io.h>
+#include <phy.h>
+
+/* EMAC */
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define GBETH_BASE			(CONFIG_KSNET_NETCP_BASE + 0x00090000)
+#define EMAC_EMACSL_BASE_ADDR		(GBETH_BASE + 0x900)
+#define EMAC_MDIO_BASE_ADDR		(GBETH_BASE + 0x300)
+#define EMAC_SGMII_BASE_ADDR		(GBETH_BASE + 0x100)
+#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL		0x04
+#define CPGMACSL_REG_STATUS		0x08
+#define CPGMACSL_REG_RESET		0x0c
+#define CPGMACSL_REG_MAXLEN		0x10
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define GBETH_BASE			(CONFIG_KSNET_NETCP_BASE + 0x00200000)
+#define CPGMACSL_REG_RX_PRI_MAP		0x020
+#define EMAC_EMACSL_BASE_ADDR		(GBETH_BASE + 0x22000)
+#define EMAC_MDIO_BASE_ADDR		(GBETH_BASE + 0x00f00)
+#define EMAC_SGMII_BASE_ADDR		(GBETH_BASE + 0x00100)
+#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL		0x330
+#define CPGMACSL_REG_STATUS		0x334
+#define CPGMACSL_REG_RESET		0x338
+#define CPGMACSL_REG_MAXLEN		0x024
+
+#endif
+
+#define KEYSTONE2_EMAC_GIG_ENABLE
+
+#define MAC_ID_BASE_ADDR		CONFIG_KSNET_MAC_ID_BASE
+
+/* MDIO module input frequency */
+#ifdef CONFIG_SOC_K2G
+#define EMAC_MDIO_BUS_FREQ		(ks_clk_get_rate(sys_clk0_3_clk))
+#else
+#define EMAC_MDIO_BUS_FREQ		(ks_clk_get_rate(pass_pll_clk))
+#endif
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ		2500000	/* 2.5 MHz */
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE		0x20
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE	0x1
+#define EMAC_MACCONTROL_GIGABIT_ENABLE		BIT(7)
+#define EMAC_MACCONTROL_GIGFORCE		BIT(17)
+#define EMAC_MACCONTROL_RMIISPEED_100		BIT(15)
+
+#define EMAC_MIN_ETHERNET_PKT_SIZE		60
+
+struct mac_sl_cfg {
+	u_int32_t max_rx_len;	/* Maximum receive packet length. */
+	u_int32_t ctl;		/* Control bitfield */
+};
+
+/**
+ * Definition: Control bitfields used in the ctl field of mac_sl_cfg
+ */
+#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES	BIT(24)
+#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES	BIT(23)
+#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES	BIT(22)
+#define GMACSL_RX_ENABLE_EXT_CTL		BIT(18)
+#define GMACSL_RX_ENABLE_GIG_FORCE		BIT(17)
+#define GMACSL_RX_ENABLE_IFCTL_B		BIT(16)
+#define GMACSL_RX_ENABLE_IFCTL_A		BIT(15)
+#define GMACSL_RX_ENABLE_CMD_IDLE		BIT(11)
+#define GMACSL_TX_ENABLE_SHORT_GAP		BIT(10)
+#define GMACSL_ENABLE_GIG_MODE			BIT(7)
+#define GMACSL_TX_ENABLE_PACE			BIT(6)
+#define GMACSL_ENABLE				BIT(5)
+#define GMACSL_TX_ENABLE_FLOW_CTL		BIT(4)
+#define GMACSL_RX_ENABLE_FLOW_CTL		BIT(3)
+#define GMACSL_ENABLE_LOOPBACK			BIT(1)
+#define GMACSL_ENABLE_FULL_DUPLEX		BIT(0)
+
+/* EMAC SL function return values */
+#define GMACSL_RET_OK				0
+#define GMACSL_RET_INVALID_PORT			-1
+#define GMACSL_RET_WARN_RESET_INCOMPLETE	-2
+#define GMACSL_RET_WARN_MAXLEN_TOO_BIG		-3
+#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE	-4
+
+/* EMAC SL register definitions */
+#define DEVICE_EMACSL_RESET_POLL_COUNT		100
+
+/* Soft reset register values */
+#define CPGMAC_REG_RESET_VAL_RESET_MASK		BIT(0)
+#define CPGMAC_REG_RESET_VAL_RESET		BIT(0)
+#define CPGMAC_REG_MAXLEN_LEN			0x3fff
+
+/* CPSW */
+/* Control bitfields */
+#define CPSW_CTL_P2_PASS_PRI_TAGGED		BIT(5)
+#define CPSW_CTL_P1_PASS_PRI_TAGGED		BIT(4)
+#define CPSW_CTL_P0_PASS_PRI_TAGGED		BIT(3)
+#define CPSW_CTL_P0_ENABLE			BIT(2)
+#define CPSW_CTL_VLAN_AWARE			BIT(1)
+#define CPSW_CTL_FIFO_LOOPBACK			BIT(0)
+
+#define DEVICE_CPSW_NUM_PORTS			CONFIG_KSNET_CPSW_NUM_PORTS
+#define DEVICE_N_GMACSL_PORTS			(DEVICE_CPSW_NUM_PORTS - 1)
+
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define DEVICE_CPSW_BASE			(GBETH_BASE + 0x800)
+#define CPSW_REG_CTL				0x004
+#define CPSW_REG_STAT_PORT_EN			0x00c
+#define CPSW_REG_MAXLEN				0x040
+#define CPSW_REG_ALE_CONTROL			0x608
+#define CPSW_REG_ALE_PORTCTL(x)			(0x640 + (x) * 4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL		0xf
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define DEVICE_CPSW_BASE			(GBETH_BASE + 0x20000)
+#define CPSW_REG_CTL				0x00004
+#define CPSW_REG_STAT_PORT_EN			0x00014
+#define CPSW_REG_MAXLEN				0x01024
+#define CPSW_REG_ALE_CONTROL			0x1e008
+#define CPSW_REG_ALE_PORTCTL(x)			(0x1e040 + (x) * 4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL		0x1ff
+
+#endif
+
+#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE	((u_int32_t)0xc0000000)
+#define CPSW_REG_VAL_ALE_CTL_BYPASS		((u_int32_t)0x00000010)
+#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE	0x3
+
+#define target_get_switch_ctl()			CPSW_CTL_P0_ENABLE
+#define SWITCH_MAX_PKT_SIZE			9000
+
+/* SGMII */
+#define SGMII_REG_STATUS_LOCK			BIT(4)
+#define SGMII_REG_STATUS_LINK			BIT(0)
+#define SGMII_REG_STATUS_AUTONEG		BIT(2)
+#define SGMII_REG_CONTROL_AUTONEG		BIT(0)
+#define SGMII_REG_CONTROL_MASTER		BIT(5)
+#define SGMII_REG_MR_ADV_ENABLE			BIT(0)
+#define SGMII_REG_MR_ADV_LINK			BIT(15)
+#define SGMII_REG_MR_ADV_FULL_DUPLEX		BIT(12)
+#define SGMII_REG_MR_ADV_GIG_MODE		BIT(11)
+
+#define SGMII_LINK_MAC_MAC_AUTONEG		0
+#define SGMII_LINK_MAC_PHY			1
+#define SGMII_LINK_MAC_MAC_FORCED		2
+#define SGMII_LINK_MAC_FIBER			3
+#define SGMII_LINK_MAC_PHY_FORCED		4
+
+#ifdef CONFIG_KSNET_NETCP_V1_0
+#define SGMII_OFFSET(x)		((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
+#elif defined CONFIG_KSNET_NETCP_V1_5
+#define SGMII_OFFSET(x)		((x) * 0x100)
+#endif
+
+#define SGMII_IDVER_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
+#define SGMII_SRESET_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
+#define SGMII_CTL_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
+#define SGMII_STATUS_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
+#define SGMII_MRADV_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
+#define SGMII_LPADV_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
+#define SGMII_TXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
+#define SGMII_RXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
+#define SGMII_AUXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
+
+/* RGMII */
+#define RGMII_REG_STATUS_LINK		BIT(0)
+
+#define RGMII_STATUS_REG		(GBETH_BASE + 0x18)
+
+/* PSS */
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR	(CONFIG_KSNET_NETCP_BASE + 0x604)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x06060606
+#define hw_config_streaming_switch()\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR	(CONFIG_KSNET_NETCP_BASE + 0x500)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x0
+
+#define hw_config_streaming_switch()\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+4);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+8);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+12);
+
+#endif
+
+/* EMAC MDIO Registers Structure */
+struct mdio_regs {
+	u32 version;
+	u32 control;
+	u32 alive;
+	u32 link;
+	u32 linkintraw;
+	u32 linkintmasked;
+	u32 rsvd0[2];
+	u32 userintraw;
+	u32 userintmasked;
+	u32 userintmaskset;
+	u32 userintmaskclear;
+	u32 rsvd1[20];
+	u32 useraccess0;
+	u32 userphysel0;
+	u32 useraccess1;
+	u32 userphysel1;
+};
+
+#endif  /* _KEYSTONE_NET_H_ */
diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h b/arch/arm/include/asm/ti-common/keystone_serdes.h
new file mode 100644
index 0000000..6234388
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/keystone_serdes.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Texas Instruments Keystone SerDes driver
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef __TI_KEYSTONE_SERDES_H__
+#define __TI_KEYSTONE_SERDES_H__
+
+/* SERDES Reference clock */
+enum ks2_serdes_clock {
+	SERDES_CLOCK_100M,		/* 100 MHz */
+	SERDES_CLOCK_122P88M,		/* 122.88 MHz */
+	SERDES_CLOCK_125M,		/* 125 MHz */
+	SERDES_CLOCK_156P25M,		/* 156.25 MHz */
+	SERDES_CLOCK_312P5M,		/* 312.5 MHz */
+};
+
+/* SERDES Lane Baud Rate */
+enum ks2_serdes_rate {
+	SERDES_RATE_4P9152G,		/* 4.9152 GBaud */
+	SERDES_RATE_5G,			/* 5 GBaud */
+	SERDES_RATE_6P144G,		/* 6.144 GBaud */
+	SERDES_RATE_6P25G,		/* 6.25 GBaud */
+	SERDES_RATE_10p3125g,		/* 10.3215 GBaud */
+	SERDES_RATE_12p5g,		/* 12.5 GBaud */
+};
+
+/* SERDES Lane Rate Mode */
+enum ks2_serdes_rate_mode {
+	SERDES_FULL_RATE,
+	SERDES_HALF_RATE,
+	SERDES_QUARTER_RATE,
+};
+
+/* SERDES PHY TYPE */
+enum ks2_serdes_interface {
+	SERDES_PHY_SGMII,
+	SERDES_PHY_PCSR,		/* XGE SERDES */
+};
+
+struct ks2_serdes {
+	enum ks2_serdes_clock clk;
+	enum ks2_serdes_rate rate;
+	enum ks2_serdes_rate_mode rate_mode;
+	enum ks2_serdes_interface intf;
+	u32 loopback;
+};
+
+int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes);
+
+#endif /* __TI_KEYSTONE_SERDES_H__ */
diff --git a/arch/arm/include/asm/ti-common/omap_wdt.h b/arch/arm/include/asm/ti-common/omap_wdt.h
new file mode 100644
index 0000000..fbc421b
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/omap_wdt.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * omap_wdt.h
+ *
+ * OMAP Watchdog header file
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ */
+
+#ifndef __OMAP_WDT_H__
+#define __OMAP_WDT_H__
+
+/*
+ * Watchdog:
+ * Using the prescaler, the OMAP watchdog could go for many
+ * months before firing.  These limits work without scaling,
+ * with the 60 second default assumed by most tools and docs.
+ */
+#define TIMER_MARGIN_MAX	(24 * 60 * 60)	/* 1 day */
+#define TIMER_MARGIN_DEFAULT	60	/* 60 secs */
+#define TIMER_MARGIN_MIN	1
+
+#define PTV			0	/* prescale */
+#define GET_WLDR_VAL(secs)	(0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
+#define WDT_WWPS_PEND_WCLR	BIT(0)
+#define WDT_WWPS_PEND_WLDR	BIT(2)
+#define WDT_WWPS_PEND_WTGR	BIT(3)
+#define WDT_WWPS_PEND_WSPR	BIT(4)
+
+#define WDT_WCLR_PRE		BIT(5)
+#define WDT_WCLR_PTV_OFF	2
+
+/* Watchdog timer registers */
+struct wd_timer {
+	unsigned int resv1[4];
+	unsigned int wdtwdsc;	/* offset 0x010 */
+	unsigned int wdtwdst;	/* offset 0x014 */
+	unsigned int wdtwisr;	/* offset 0x018 */
+	unsigned int wdtwier;	/* offset 0x01C */
+	unsigned int wdtwwer;	/* offset 0x020 */
+	unsigned int wdtwclr;	/* offset 0x024 */
+	unsigned int wdtwcrr;	/* offset 0x028 */
+	unsigned int wdtwldr;	/* offset 0x02C */
+	unsigned int wdtwtgr;	/* offset 0x030 */
+	unsigned int wdtwwps;	/* offset 0x034 */
+	unsigned int resv2[3];
+	unsigned int wdtwdly;	/* offset 0x044 */
+	unsigned int wdtwspr;	/* offset 0x048 */
+	unsigned int resv3[1];
+	unsigned int wdtwqeoi;	/* offset 0x050 */
+	unsigned int wdtwqstar;	/* offset 0x054 */
+	unsigned int wdtwqsta;	/* offset 0x058 */
+	unsigned int wdtwqens;	/* offset 0x05C */
+	unsigned int wdtwqenc;	/* offset 0x060 */
+	unsigned int resv4[39];
+	unsigned int wdt_unfr;	/* offset 0x100 */
+};
+
+struct omap3_wdt_priv {
+	struct wd_timer *regs;
+	unsigned int wdt_trgr_pattern;
+};
+
+#endif /* __OMAP_WDT_H__ */
diff --git a/arch/arm/include/asm/ti-common/sys_proto.h b/arch/arm/include/asm/ti-common/sys_proto.h
new file mode 100644
index 0000000..db042a1
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/sys_proto.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef _TI_COMMON_SYS_PROTO_H_
+#define _TI_COMMON_SYS_PROTO_H_
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ARCH_OMAP2PLUS
+#define TI_ARMV7_DRAM_ADDR_SPACE_START	0x80000000
+#define TI_ARMV7_DRAM_ADDR_SPACE_END	0xFFFFFFFF
+
+#define OMAP_INIT_CONTEXT_SPL			0
+#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR	1
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL	2
+#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH	3
+
+static inline u32 running_from_sdram(void)
+{
+	u32 pc;
+	asm volatile ("mov %0, pc" : "=r" (pc));
+	return ((pc >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
+	    (pc < TI_ARMV7_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+	/*
+	 * u-boot can be running from sdram either because of configuration
+	 * Header or by SPL. If because of CH, then the romcode sets the
+	 * CHSETTINGS executed bit to true in the boot parameter structure that
+	 * it passes to the bootloader.This parameter is stored in the ch_flags
+	 * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
+	 * mandatory section if CH is present.
+	 */
+	if (gd->arch.omap_ch_flags & CH_FLAGS_CHSETTINGS)
+		return 0;
+	else
+		return running_from_sdram();
+}
+
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ *  1. SPL running from SRAM
+ *  2. U-Boot running from FLASH
+ *  3. Non-XIP U-Boot loaded to SDRAM by SPL
+ *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ *     Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap_hw_init_context(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	return OMAP_INIT_CONTEXT_SPL;
+#else
+	if (uboot_loaded_by_spl())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
+	else if (running_from_sdram())
+		return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
+	else
+		return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
+#endif
+}
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/ti-common/ti-aemif.h b/arch/arm/include/asm/ti-common/ti-aemif.h
new file mode 100644
index 0000000..a775386
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/ti-aemif.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * AEMIF definitions
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef _AEMIF_H_
+#define _AEMIF_H_
+
+#define AEMIF_NUM_CS               4
+#define AEMIF_MODE_NOR             0
+#define AEMIF_MODE_NAND            1
+#define AEMIF_MODE_ONENAND         2
+#define AEMIF_PRESERVE             -1
+
+struct aemif_config {
+	unsigned mode;
+	unsigned select_strobe;
+	unsigned extend_wait;
+	unsigned wr_setup;
+	unsigned wr_strobe;
+	unsigned wr_hold;
+	unsigned rd_setup;
+	unsigned rd_strobe;
+	unsigned rd_hold;
+	unsigned turn_around;
+	enum {
+		AEMIF_WIDTH_8	= 0,
+		AEMIF_WIDTH_16	= 1,
+		AEMIF_WIDTH_32	= 2,
+	} width;
+};
+
+void aemif_init(int num_cs, struct aemif_config *config);
+
+#endif
diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h
new file mode 100644
index 0000000..96c8a31
--- /dev/null
+++ b/arch/arm/include/asm/ti-common/ti-edma3.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Enhanced Direct Memory Access (EDMA3) Controller
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef _EDMA3_H_
+#define _EDMA3_H_
+
+#include <linux/stddef.h>
+
+#define EDMA3_PARSET_NULL_LINK			0xffff
+
+/*
+ * All parameter RAM set options
+ * opt field in edma3_param_set_config structure
+ */
+#define EDMA3_SLOPT_PRIV_LEVEL			BIT(31)
+#define EDMA3_SLOPT_PRIV_ID(id)			((0xf & (id)) << 24)
+#define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB	BIT(23)
+#define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB	BIT(22)
+#define EDMA3_SLOPT_INTERM_COMP_INT_ENB		BIT(21)
+#define EDMA3_SLOPT_TRANS_COMP_INT_ENB		BIT(20)
+#define EDMA3_SLOPT_COMP_CODE(code)		((0x3f & (code)) << 12)
+#define EDMA3_SLOPT_FIFO_WIDTH_8		0
+#define EDMA3_SLOPT_FIFO_WIDTH_16		(1 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_32		(2 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_64		(3 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_128		(4 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_256		(5 << 8)
+#define EDMA3_SLOPT_FIFO_WIDTH_SET(w)		((w & 0x7) << 8)
+#define EDMA3_SLOPT_STATIC			BIT(3)
+#define EDMA3_SLOPT_AB_SYNC			BIT(2)
+#define EDMA3_SLOPT_DST_ADDR_CONST_MODE		BIT(1)
+#define EDMA3_SLOPT_SRC_ADDR_CONST_MODE		BIT(0)
+
+enum edma3_address_mode {
+	INCR = 0,
+	FIFO = 1
+};
+
+enum edma3_fifo_width {
+	W8BIT = 0,
+	W16BIT = 1,
+	W32BIT = 2,
+	W64BIT = 3,
+	W128BIT = 4,
+	W256BIT = 5
+};
+
+enum edma3_sync_dimension {
+	ASYNC = 0,
+	ABSYNC = 1
+};
+
+/* PaRAM slots are laid out like this */
+struct edma3_slot_layout {
+	u32 opt;
+	u32 src;
+	u32 a_b_cnt;
+	u32 dst;
+	u32 src_dst_bidx;
+	u32 link_bcntrld;
+	u32 src_dst_cidx;
+	u32 ccnt;
+} __packed;
+
+/*
+ * Use this to assign trigger word number of edma3_slot_layout struct.
+ * trigger_word_name - is the exact name from edma3_slot_layout.
+ */
+#define EDMA3_TWORD(trigger_word_name)\
+		(offsetof(struct edma3_slot_layout, trigger_word_name) / 4)
+
+struct edma3_slot_config {
+	u32 opt;
+	u32 src;
+	u32 dst;
+	int bcnt;
+	int acnt;
+	int ccnt;
+	int src_bidx;
+	int dst_bidx;
+	int src_cidx;
+	int dst_cidx;
+	int bcntrld;
+	int link;
+};
+
+struct edma3_channel_config {
+	int slot;
+	int chnum;
+	int complete_code;	/* indicate pending complete interrupt */
+	int trigger_slot_word;	/* only used for qedma */
+};
+
+void qedma3_start(u32 base, struct edma3_channel_config *cfg);
+void qedma3_stop(u32 base, struct edma3_channel_config *cfg);
+void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg);
+int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg);
+void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param);
+void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param);
+
+void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
+		    enum edma3_fifo_width width);
+void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_dest_addr(u32 base, int slot, u32 dst);
+
+void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
+		   enum edma3_fifo_width width);
+void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx);
+void edma3_set_src_addr(u32 base, int slot, u32 src);
+
+void edma3_set_transfer_params(u32 base, int slot, int acnt,
+			       int bcnt, int ccnt, u16 bcnt_rld,
+			       enum edma3_sync_dimension sync_mode);
+void edma3_transfer(unsigned long edma3_base_addr, unsigned int
+		edma_slot_num, void *dst, void *src, size_t len);
+void edma3_fill(unsigned long edma3_base_addr, unsigned int edma_slot_num,
+		void *dst, u8 val, size_t len);
+
+#endif
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
new file mode 100644
index 0000000..900b261
--- /dev/null
+++ b/arch/arm/include/asm/types.h
@@ -0,0 +1,45 @@
+#ifndef __ASM_ARM_TYPES_H
+#define __ASM_ARM_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+typedef unsigned short umode_t;
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#ifdef	CONFIG_ARM64
+#define BITS_PER_LONG 64
+#else	/* CONFIG_ARM64 */
+#define BITS_PER_LONG 32
+#endif	/* CONFIG_ARM64 */
+
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+#else
+/* DMA addresses are 32-bits wide */
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+#endif
+
+/*
+ * A dma_addr_t can hold any valid DMA address, i.e., any address returned
+ * by the DMA API.
+ *
+ * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32
+ * bits wide.  Bus addresses, e.g., PCI BARs, may be wider than 32 bits,
+ * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses,
+ * so they don't care about the size of the actual bus addresses.
+ */
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+typedef unsigned long long dma_addr_t;
+#else
+typedef u32 dma_addr_t;
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
new file mode 100644
index 0000000..2e8c8e5
--- /dev/null
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ */
+
+#ifndef _U_BOOT_ARM_H_
+#define _U_BOOT_ARM_H_	1
+
+#ifndef __ASSEMBLY__
+
+/* for the following variables, see start.S */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+extern ulong _datarel_start_ofs;
+extern ulong _datarelrolocal_start_ofs;
+extern ulong _datarellocal_start_ofs;
+extern ulong _datarelro_start_ofs;
+extern ulong IRQ_STACK_START_IN;	/* 8 bytes in IRQ stack */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* Set up ARMv7 MMU, caches and TLBs */
+void	cpu_init_cp15(void);
+
+/* cpu/.../arch/cpu.c */
+int	arch_misc_init(void);
+
+/* board/.../... */
+int	board_init(void);
+
+/* calls to c from vectors.S */
+struct pt_regs;
+
+void bad_mode(void);
+void do_undefined_instruction(struct pt_regs *pt_regs);
+void do_software_interrupt(struct pt_regs *pt_regs);
+void do_prefetch_abort(struct pt_regs *pt_regs);
+void do_data_abort(struct pt_regs *pt_regs);
+void do_not_used(struct pt_regs *pt_regs);
+#ifdef CONFIG_ARM64
+void do_fiq(struct pt_regs *pt_regs, unsigned int esr);
+void do_irq(struct pt_regs *pt_regs, unsigned int esr);
+#else
+void do_fiq(struct pt_regs *pt_regs);
+void do_irq(struct pt_regs *pt_regswq);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif	/* _U_BOOT_ARM_H_ */
diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h
new file mode 100644
index 0000000..07528a4
--- /dev/null
+++ b/arch/arm/include/asm/u-boot.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#include <asm/u-boot-arm.h>
+
+/* For image.h:image_check_target_arch() */
+#ifndef CONFIG_ARM64
+#define IH_ARCH_DEFAULT IH_ARCH_ARM
+#else
+#define IH_ARCH_DEFAULT IH_ARCH_ARM64
+#endif
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h
new file mode 100644
index 0000000..0a228fb
--- /dev/null
+++ b/arch/arm/include/asm/unaligned.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_ARM_UNALIGNED_H
+#define _ASM_ARM_UNALIGNED_H
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+/*
+ * Select endianness
+ */
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define get_unaligned	__get_unaligned_le
+#define put_unaligned	__put_unaligned_le
+#else
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+#endif
+
+#endif /* _ASM_ARM_UNALIGNED_H */
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
new file mode 100644
index 0000000..2fae54e
--- /dev/null
+++ b/arch/arm/include/asm/unified.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
+ *
+ * Copyright (C) 2008 ARM Limited
+ */
+
+#ifndef __ASM_UNIFIED_H
+#define __ASM_UNIFIED_H
+
+#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED)
+	.syntax unified
+#endif
+
+#ifdef CONFIG_CPU_V7M
+#define AR_CLASS(x...)
+#define M_CLASS(x...)	x
+#else
+#define AR_CLASS(x...)	x
+#define M_CLASS(x...)
+#endif
+
+#ifdef CONFIG_THUMB2_KERNEL
+
+#if __GNUC__ < 4
+#error Thumb-2 kernel requires gcc >= 4
+#endif
+
+/* The CPSR bit describing the instruction set (Thumb) */
+#define PSR_ISETSTATE	PSR_T_BIT
+
+#define ARM(x...)
+#define THUMB(x...)	x
+#ifdef __ASSEMBLY__
+#define W(instr)	instr.w
+#else
+#define WASM(instr)	#instr ".w"
+#endif
+
+#else	/* !CONFIG_THUMB2_KERNEL */
+
+/* The CPSR bit describing the instruction set (ARM) */
+#define PSR_ISETSTATE	0
+
+#define ARM(x...)	x
+#define THUMB(x...)
+#ifdef __ASSEMBLY__
+#define W(instr)	instr
+#else
+#define WASM(instr)	#instr
+#endif
+
+#endif	/* CONFIG_THUMB2_KERNEL */
+
+#ifndef CONFIG_ARM_ASM_UNIFIED
+
+/*
+ * If the unified assembly syntax isn't used (in ARM mode), these
+ * macros expand to an empty string
+ */
+#ifdef __ASSEMBLY__
+	.macro	it, cond
+	.endm
+	.macro	itt, cond
+	.endm
+	.macro	ite, cond
+	.endm
+	.macro	ittt, cond
+	.endm
+	.macro	itte, cond
+	.endm
+	.macro	itet, cond
+	.endm
+	.macro	itee, cond
+	.endm
+	.macro	itttt, cond
+	.endm
+	.macro	ittte, cond
+	.endm
+	.macro	ittet, cond
+	.endm
+	.macro	ittee, cond
+	.endm
+	.macro	itett, cond
+	.endm
+	.macro	itete, cond
+	.endm
+	.macro	iteet, cond
+	.endm
+	.macro	iteee, cond
+	.endm
+#else	/* !__ASSEMBLY__ */
+__asm__(
+"	.macro	it, cond\n"
+"	.endm\n"
+"	.macro	itt, cond\n"
+"	.endm\n"
+"	.macro	ite, cond\n"
+"	.endm\n"
+"	.macro	ittt, cond\n"
+"	.endm\n"
+"	.macro	itte, cond\n"
+"	.endm\n"
+"	.macro	itet, cond\n"
+"	.endm\n"
+"	.macro	itee, cond\n"
+"	.endm\n"
+"	.macro	itttt, cond\n"
+"	.endm\n"
+"	.macro	ittte, cond\n"
+"	.endm\n"
+"	.macro	ittet, cond\n"
+"	.endm\n"
+"	.macro	ittee, cond\n"
+"	.endm\n"
+"	.macro	itett, cond\n"
+"	.endm\n"
+"	.macro	itete, cond\n"
+"	.endm\n"
+"	.macro	iteet, cond\n"
+"	.endm\n"
+"	.macro	iteee, cond\n"
+"	.endm\n");
+#endif	/* __ASSEMBLY__ */
+
+#endif	/* CONFIG_ARM_ASM_UNIFIED */
+
+#endif	/* !__ASM_UNIFIED_H */
diff --git a/arch/arm/include/asm/utils.h b/arch/arm/include/asm/utils.h
new file mode 100644
index 0000000..eee60c5
--- /dev/null
+++ b/arch/arm/include/asm/utils.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ */
+#ifndef _UTILS_H_
+#define _UTILS_H_
+
+static inline s32 log_2_n_round_up(u32 n)
+{
+	s32 log2n = -1;
+	u32 temp = n;
+
+	while (temp) {
+		log2n++;
+		temp >>= 1;
+	}
+
+	if (n & (n - 1))
+		return log2n + 1; /* not power of 2 - round up */
+	else
+		return log2n; /* power of 2 */
+}
+
+static inline s32 log_2_n_round_down(u32 n)
+{
+	s32 log2n = -1;
+	u32 temp = n;
+
+	while (temp) {
+		log2n++;
+		temp >>= 1;
+	}
+
+	return log2n;
+}
+
+#endif
diff --git a/arch/arm/include/debug/8250.S b/arch/arm/include/debug/8250.S
new file mode 100644
index 0000000..5e37536
--- /dev/null
+++ b/arch/arm/include/debug/8250.S
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * arch/arm/include/debug/8250.S
+ *
+ *  Copyright (C) 1994-2013 Russell King
+ */
+#include <linux/serial_reg.h>
+
+		.macro	addruart, rp, rv, tmp
+		ldr	\rp, =CONFIG_DEBUG_UART_PHYS
+		ldr	\rv, =CONFIG_DEBUG_UART_VIRT
+		.endm
+
+#ifdef CONFIG_DEBUG_UART_8250_WORD
+		.macro	store, rd, rx:vararg
+		str	\rd, \rx
+		.endm
+
+		.macro	load, rd, rx:vararg
+		ldr	\rd, \rx
+		.endm
+#else
+		.macro	store, rd, rx:vararg
+		strb	\rd, \rx
+		.endm
+
+		.macro	load, rd, rx:vararg
+		ldrb	\rd, \rx
+		.endm
+#endif
+
+#define UART_SHIFT CONFIG_DEBUG_UART_8250_SHIFT
+
+		.macro	senduart,rd,rx
+		store	\rd, [\rx, #UART_TX << UART_SHIFT]
+		.endm
+
+		.macro	busyuart,rd,rx
+1002:		load	\rd, [\rx, #UART_LSR << UART_SHIFT]
+		and	\rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+		teq	\rd, #UART_LSR_TEMT | UART_LSR_THRE
+		bne	1002b
+		.endm
+
+		.macro	waituart,rd,rx
+#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL
+1001:		load	\rd, [\rx, #UART_MSR << UART_SHIFT]
+		tst	\rd, #UART_MSR_CTS
+		beq	1001b
+#endif
+		.endm
diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h
new file mode 100644
index 0000000..4a3f6b9
--- /dev/null
+++ b/arch/m68k/include/asm/bitops.h
@@ -0,0 +1,55 @@
+/*
+ * bitops.h: Bit string operations on the m68k
+ */
+
+#ifndef _M68K_BITOPS_H
+#define _M68K_BITOPS_H
+
+#include <asm/byteorder.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+extern void set_bit(int nr, volatile void *addr);
+extern void clear_bit(int nr, volatile void *addr);
+extern void change_bit(int nr, volatile void *addr);
+extern int test_and_clear_bit(int nr, volatile void *addr);
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+#ifdef __KERNEL__
+
+
+static inline int test_bit(int nr, __const__ volatile void *addr)
+{
+	__const__ unsigned int *p = (__const__ unsigned int *) addr;
+
+	return (p[nr >> 5] & (1UL << (nr & 31))) != 0;
+}
+
+static inline int test_and_set_bit(int nr, volatile void *vaddr)
+{
+	char retval;
+
+	volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3];
+	__asm__ __volatile__ ("bset %2,(%4); sne %0"
+	     : "=d" (retval), "=m" (*p)
+	     : "di" (nr & 7), "m" (*p), "a" (p));
+
+	return retval;
+}
+
+#define __ffs(x) (ffs(x) - 1)
+
+/*
+ *  * hweightN: returns the hamming weight (i.e. the number
+ *   * of bits set) of a N-bit word
+ *    */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+#endif /* _M68K_BITOPS_H */
diff --git a/arch/m68k/include/asm/byteorder.h b/arch/m68k/include/asm/byteorder.h
new file mode 100644
index 0000000..9179622
--- /dev/null
+++ b/arch/m68k/include/asm/byteorder.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef _M68K_BYTEORDER_H
+#define _M68K_BYTEORDER_H
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+static inline __u32 __sw32(__u32 x)
+{
+	__u32 v = x;
+
+	return v << 24 |
+		(v & (__u32)0x0000ff00UL) <<  8 |
+		(v & (__u32)0x00ff0000UL) >>  8 |
+		v >> 24;
+}
+
+static inline __u16 __sw16(__u16 x)
+{
+	__u16 v = x;
+
+	return (v & (__u16)0x00ffU) << 8 |
+		(v & (__u16)0xff00U) >> 8;
+}
+
+static __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+{
+	return __sw16(*addr);
+}
+
+static __inline__ void st_le16(volatile unsigned short *addr,
+			       const unsigned val)
+{
+	*addr = __sw16(val);
+}
+
+static __inline__ unsigned ld_le32(const volatile unsigned *addr)
+{
+	return __sw32(*addr);
+}
+
+static __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+{
+	*addr = __sw32(val);
+}
+
+#if 0
+/* alas, egcs sounds like it has a bug in this code that doesn't use the
+   inline asm correctly, and can cause file corruption. Until I hear that
+   it's fixed, I can live without the extra speed. I hope. */
+#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
+#if 0
+#  define __arch_swab16(x) ld_le16(&x)
+#  define __arch_swab32(x) ld_le32(&x)
+#else
+static __inline__ __attribute__ ((const))
+__u16 ___arch__swab16(__u16 value)
+{
+	return __sw16(value);
+}
+
+static __inline__ __attribute__ ((const))
+__u32 ___arch__swab32(__u32 value)
+{
+	return __sw32(value);
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+#endif				/* 0 */
+
+#endif
+
+/* The same, but returns converted value from the location pointer by addr. */
+#define __arch__swab16p(addr) ld_le16(addr)
+#define __arch__swab32p(addr) ld_le32(addr)
+
+/* The same, but do the conversion in situ, ie. put the value back to addr. */
+#define __arch__swab16s(addr) st_le16(addr,*addr)
+#define __arch__swab32s(addr) st_le32(addr,*addr)
+#endif
+
+#endif				/* __GNUC__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#define __BYTEORDER_HAS_U64__
+#endif
+#include <linux/byteorder/big_endian.h>
+
+#endif				/* _M68K_BYTEORDER_H */
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
new file mode 100644
index 0000000..a1eeabc
--- /dev/null
+++ b/arch/m68k/include/asm/cache.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ColdFire cache
+ *
+ * Copyright 2004-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
+    defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x)
+#define CONFIG_CF_V2
+#endif
+
+#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
+    defined(CONFIG_MCF5301x)
+#define CONFIG_CF_V3
+#endif
+
+#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
+#define CONFIG_CF_V4
+#elif defined(CONFIG_MCF5441x)
+#define CONFIG_CF_V4E		/* Four Extra ACRn */
+#endif
+
+/* ***** CACR ***** */
+/* V2 Core */
+#ifdef CONFIG_CF_V2
+
+#define CF_CACR_CENB		(1 << 31)
+#define CF_CACR_CPD		(1 << 28)
+#define CF_CACR_CFRZ		(1 << 27)
+#define CF_CACR_CEIB		(1 << 10)
+#define CF_CACR_DCM		(1 << 9)
+#define CF_CACR_DBWE		(1 << 8)
+
+#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253)
+#define CF_CACR_DWP		(1 << 6)
+#else
+#define CF_CACR_CINV		(1 << 24)
+#define CF_CACR_DISI		(1 << 23)
+#define CF_CACR_DISD		(1 << 22)
+#define CF_CACR_INVI		(1 << 21)
+#define CF_CACR_INVD		(1 << 20)
+#define CF_CACR_DWP		(1 << 5)
+#define CF_CACR_EUSP		(1 << 4)
+#endif				/* CONFIG_MCF5249 || CONFIG_MCF5253 */
+
+#endif				/* CONFIG_CF_V2 */
+
+/* V3 Core */
+#ifdef CONFIG_CF_V3
+
+#define CF_CACR_EC		(1 << 31)
+#define CF_CACR_ESB		(1 << 29)
+#define CF_CACR_DPI		(1 << 28)
+#define CF_CACR_HLCK		(1 << 27)
+#define CF_CACR_CINVA		(1 << 24)
+#define CF_CACR_DNFB		(1 << 10)
+#define CF_CACR_DCM_UNMASK	0xFFFFFCFF
+#define CF_CACR_DCM_WT		(0 << 8)
+#define CF_CACR_DCM_CB		(1 << 8)
+#define CF_CACR_DCM_P		(2 << 8)
+#define CF_CACR_DCM_IP		(3 << 8)
+#define CF_CACR_DW		(1 << 5)
+#define CF_CACR_EUSP		(1 << 4)
+
+#endif				/* CONFIG_CF_V3 */
+
+/* V4 Core */
+#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+
+#define CF_CACR_DEC		(1 << 31)
+#define CF_CACR_DW		(1 << 30)
+#define CF_CACR_DESB		(1 << 29)
+#define CF_CACR_DDPI		(1 << 28)
+#define CF_CACR_DHLCK		(1 << 27)
+#define CF_CACR_DDCM_UNMASK	(0xF9FFFFFF)
+#define CF_CACR_DDCM_WT		(0 << 25)
+#define CF_CACR_DDCM_CB		(1 << 25)
+#define CF_CACR_DDCM_P		(2 << 25)
+#define CF_CACR_DDCM_IP		(3 << 25)
+#define CF_CACR_DCINVA		(1 << 24)
+
+#define CF_CACR_DDSP		(1 << 23)
+#define CF_CACR_BEC		(1 << 19)
+#define CF_CACR_BCINVA		(1 << 18)
+#define CF_CACR_IEC		(1 << 15)
+#define CF_CACR_DNFB		(1 << 13)
+#define CF_CACR_IDPI		(1 << 12)
+#define CF_CACR_IHLCK		(1 << 11)
+#define CF_CACR_IDCM		(1 << 10)
+#define CF_CACR_ICINVA		(1 << 8)
+#define CF_CACR_IDSP		(1 << 7)
+#define CF_CACR_EUSP		(1 << 5)
+
+#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
+#define CF_CACR_IVO		(1 << 20)
+#define CF_CACR_SPA		(1 << 14)
+#else
+#define CF_CACR_DF		(1 << 4)
+#endif
+
+#endif				/* CONFIG_CF_V4 */
+
+/* ***** ACR ***** */
+#define CF_ACR_ADR_UNMASK	(0x00FFFFFF)
+#define CF_ACR_ADR(x)		((x & 0xFF) << 24)
+#define CF_ACR_ADRMSK_UNMASK	(0xFF00FFFF)
+#define CF_ACR_ADRMSK(x)	((x & 0xFF) << 16)
+#define CF_ACR_EN		(1 << 15)
+#define CF_ACR_SM_UNMASK	(0xFFFF9FFF)
+#define CF_ACR_SM_UM		(0 << 13)
+#define CF_ACR_SM_SM		(1 << 13)
+#define CF_ACR_SM_ALL		(3 << 13)
+#define CF_ACR_WP		(1 << 2)
+
+/* V2 Core */
+#ifdef CONFIG_CF_V2
+#define CF_ACR_CM		(1 << 6)
+#define CF_ACR_BWE		(1 << 5)
+#else
+/* V3 & V4 */
+#define CF_ACR_CM_UNMASK	(0xFFFFFF9F)
+#define CF_ACR_CM_WT		(0 << 5)
+#define CF_ACR_CM_CB		(1 << 5)
+#define CF_ACR_CM_P		(2 << 5)
+#define CF_ACR_CM_IP		(3 << 5)
+#endif				/* CONFIG_CF_V2 */
+
+/* V4 Core */
+#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#define CF_ACR_AMM		(1 << 10)
+#define CF_ACR_SP		(1 << 3)
+#endif				/* CONFIG_CF_V4 */
+
+
+#ifndef CONFIG_SYS_CACHE_ICACR
+#define CONFIG_SYS_CACHE_ICACR	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_DCACR
+#ifdef CONFIG_SYS_CACHE_ICACR
+#define CONFIG_SYS_CACHE_DCACR	CONFIG_SYS_CACHE_ICACR
+#else
+#define CONFIG_SYS_CACHE_DCACR	0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR0
+#define CONFIG_SYS_CACHE_ACR0	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR1
+#define CONFIG_SYS_CACHE_ACR1	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR2
+#define CONFIG_SYS_CACHE_ACR2	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR3
+#define CONFIG_SYS_CACHE_ACR3	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR4
+#define CONFIG_SYS_CACHE_ACR4	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR5
+#define CONFIG_SYS_CACHE_ACR5	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR6
+#define CONFIG_SYS_CACHE_ACR6	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR7
+#define CONFIG_SYS_CACHE_ACR7	0
+#endif
+
+#define CF_ADDRMASK(x)		(((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
+
+#ifndef __ASSEMBLY__		/* put C only stuff in this section */
+
+void icache_invalid(void);
+void dcache_invalid(void);
+
+#endif
+
+/*
+ * m68k uses 16 byte L1 data cache line sizes.  Use this for DMA buffer
+ * alignment unless the board configuration has specified a new value.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	16
+#endif
+
+#endif				/* __CACHE_H */
diff --git a/arch/m68k/include/asm/coldfire/ata.h b/arch/m68k/include/asm/coldfire/ata.h
new file mode 100644
index 0000000..d85c052
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/ata.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ATA Internal Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __ATA_H__
+#define __ATA_H__
+
+/* ATA */
+typedef struct atac {
+	/* PIO */
+	u8 toff;		/* 0x00 */
+	u8 ton;			/* 0x01 */
+	u8 t1;			/* 0x02 */
+	u8 t2w;			/* 0x03 */
+	u8 t2r;			/* 0x04 */
+	u8 ta;			/* 0x05 */
+	u8 trd;			/* 0x06 */
+	u8 t4;			/* 0x07 */
+	u8 t9;			/* 0x08 */
+
+	/* DMA */
+	u8 tm;			/* 0x09 */
+	u8 tn;			/* 0x0A */
+	u8 td;			/* 0x0B */
+	u8 tk;			/* 0x0C */
+	u8 tack;		/* 0x0D */
+	u8 tenv;		/* 0x0E */
+	u8 trp;			/* 0x0F */
+	u8 tzah;		/* 0x10 */
+	u8 tmli;		/* 0x11 */
+	u8 tdvh;		/* 0x12 */
+	u8 tdzfs;		/* 0x13 */
+	u8 tdvs;		/* 0x14 */
+	u8 tcvh;		/* 0x15 */
+	u8 tss;			/* 0x16 */
+	u8 tcyc;		/* 0x17 */
+
+	/* FIFO */
+	u32 fifo32;		/* 0x18 */
+	u16 fifo16;		/* 0x1C */
+	u8 rsvd0[2];
+	u8 ffill;		/* 0x20 */
+	u8 rsvd1[3];
+
+	/* ATA */
+	u8 cr;			/* 0x24 */
+	u8 rsvd2[3];
+	u8 isr;			/* 0x28 */
+	u8 rsvd3[3];
+	u8 ier;			/* 0x2C */
+	u8 rsvd4[3];
+	u8 icr;			/* 0x30 */
+	u8 rsvd5[3];
+	u8 falarm;		/* 0x34 */
+	u8 rsvd6[106];
+} atac_t;
+
+#endif				/* __ATA_H__ */
diff --git a/arch/m68k/include/asm/coldfire/crossbar.h b/arch/m68k/include/asm/coldfire/crossbar.h
new file mode 100644
index 0000000..e26da13
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/crossbar.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Cross Bar Switch Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __CROSSBAR_H__
+#define __CROSSBAR_H__
+
+/*********************************************************************
+* Cross-bar switch (XBS)
+*********************************************************************/
+typedef struct xbs {
+	u32 prs1;		/* 0x100 Priority Register Slave 1 */
+	u32 res1[3];		/* 0x104 - 0F */
+	u32 crs1;		/* 0x110 Control Register Slave 1 */
+	u32 res2[187];		/* 0x114 - 0x3FF */
+
+	u32 prs4;		/* 0x400 Priority Register Slave 4 */
+	u32 res3[3];		/* 0x404 - 0F */
+	u32 crs4;		/* 0x410 Control Register Slave 4 */
+	u32 res4[123];		/* 0x414 - 0x5FF */
+
+	u32 prs6;		/* 0x600 Priority Register Slave 6 */
+	u32 res5[3];		/* 0x604 - 0F */
+	u32 crs6;		/* 0x610 Control Register Slave 6 */
+	u32 res6[59];		/* 0x614 - 0x6FF */
+
+	u32 prs7;		/* 0x700 Priority Register Slave 7 */
+	u32 res7[3];		/* 0x704 - 0F */
+	u32 crs7;		/* 0x710 Control Register Slave 7 */
+} xbs_t;
+
+/* Bit definitions and macros for PRS group */
+#define XBS_PRS_M0(x)			(((x)&0x00000007))	/* Core */
+#define XBS_PRS_M1(x)			(((x)&0x00000007)<<4)	/* eDMA */
+#define XBS_PRS_M2(x)			(((x)&0x00000007)<<8)	/* FEC0 */
+#define XBS_PRS_M3(x)			(((x)&0x00000007)<<12)	/* FEC1 */
+#define XBS_PRS_M5(x)			(((x)&0x00000007)<<20)	/* PCI controller */
+#define XBS_PRS_M6(x)			(((x)&0x00000007)<<24)	/* USB OTG */
+#define XBS_PRS_M7(x)			(((x)&0x00000007)<<28)	/* Serial Boot */
+
+/* Bit definitions and macros for CRS group */
+#define XBS_CRS_PARK(x)			(((x)&0x00000007))	/* Master parking ctrl */
+#define XBS_CRS_PCTL(x)			(((x)&0x00000003)<<4)	/* Parking mode ctrl */
+#define XBS_CRS_ARB			(0x00000100)	/* Arbitration Mode */
+#define XBS_CRS_RO			(0x80000000)	/* Read Only */
+
+#define XBS_CRS_PCTL_PARK_FIELD		(0)
+#define XBS_CRS_PCTL_PARK_ON_LAST	(1)
+#define XBS_CRS_PCTL_PARK_NONE		(2)
+#define XBS_CRS_PCTL_PARK_CORE		(0)
+#define XBS_CRS_PCTL_PARK_EDMA		(1)
+#define XBS_CRS_PCTL_PARK_FEC0		(2)
+#define XBS_CRS_PCTL_PARK_FEC1		(3)
+#define XBS_CRS_PCTL_PARK_PCI		(5)
+#define XBS_CRS_PCTL_PARK_USB		(6)
+#define XBS_CRS_PCTL_PARK_SBF		(7)
+
+#endif				/* __CROSSBAR_H__ */
diff --git a/arch/m68k/include/asm/coldfire/dspi.h b/arch/m68k/include/asm/coldfire/dspi.h
new file mode 100644
index 0000000..ddd8f33
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/dspi.h
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5227x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __DSPI_H__
+#define __DSPI_H__
+
+/* DMA Serial Peripheral Interface (DSPI) */
+typedef struct dspi {
+	u32 mcr;	/* 0x00 */
+	u32 resv0;	/* 0x04 */
+	u32 tcr;	/* 0x08 */
+	u32 ctar[8];	/* 0x0C - 0x28 */
+	u32 sr;		/* 0x2C */
+	u32 irsr;	/* 0x30 */
+	u32 tfr;	/* 0x34 - PUSHR */
+	u16 resv1;	/* 0x38 */
+	u16 rfr;	/* 0x3A - POPR */
+#ifdef CONFIG_MCF547x_8x
+	u32 tfdr[4];	/* 0x3C */
+	u8 resv2[0x30];	/* 0x40 */
+	u32 rfdr[4];	/* 0x7C */
+#else
+	u32 tfdr[16];	/* 0x3C */
+	u32 rfdr[16];	/* 0x7C */
+#endif
+} dspi_t;
+
+/* Module configuration */
+#define DSPI_MCR_MSTR			(0x80000000)
+#define DSPI_MCR_CSCK			(0x40000000)
+#define DSPI_MCR_DCONF(x)		(((x)&0x03)<<28)
+#define DSPI_MCR_FRZ			(0x08000000)
+#define DSPI_MCR_MTFE			(0x04000000)
+#define DSPI_MCR_PCSSE			(0x02000000)
+#define DSPI_MCR_ROOE			(0x01000000)
+#define DSPI_MCR_CSIS7			(0x00800000)
+#define DSPI_MCR_CSIS6			(0x00400000)
+#define DSPI_MCR_CSIS5			(0x00200000)
+#define DSPI_MCR_CSIS4			(0x00100000)
+#define DSPI_MCR_CSIS3			(0x00080000)
+#define DSPI_MCR_CSIS2			(0x00040000)
+#define DSPI_MCR_CSIS1			(0x00020000)
+#define DSPI_MCR_CSIS0			(0x00010000)
+#define DSPI_MCR_MDIS			(0x00004000)
+#define DSPI_MCR_DTXF			(0x00002000)
+#define DSPI_MCR_DRXF			(0x00001000)
+#define DSPI_MCR_CTXF			(0x00000800)
+#define DSPI_MCR_CRXF			(0x00000400)
+#define DSPI_MCR_SMPL_PT(x)		(((x)&0x03)<<8)
+#define DSPI_MCR_HALT			(0x00000001)
+
+/* Transfer count */
+#define DSPI_TCR_SPI_TCNT(x)		(((x)&0x0000FFFF)<<16)
+
+/* Clock and transfer attributes */
+#define DSPI_CTAR_DBR			(0x80000000)
+#define DSPI_CTAR_TRSZ(x)		(((x)&0x0F)<<27)
+#define DSPI_CTAR_CPOL			(0x04000000)
+#define DSPI_CTAR_CPHA			(0x02000000)
+#define DSPI_CTAR_LSBFE			(0x01000000)
+#define DSPI_CTAR_PCSSCK(x)		(((x)&0x03)<<22)
+#define DSPI_CTAR_PCSSCK_7CLK		(0x00A00000)
+#define DSPI_CTAR_PCSSCK_5CLK		(0x00800000)
+#define DSPI_CTAR_PCSSCK_3CLK		(0x00400000)
+#define DSPI_CTAR_PCSSCK_1CLK		(0x00000000)
+#define DSPI_CTAR_PASC(x)		(((x)&0x03)<<20)
+#define DSPI_CTAR_PASC_7CLK		(0x00300000)
+#define DSPI_CTAR_PASC_5CLK		(0x00200000)
+#define DSPI_CTAR_PASC_3CLK		(0x00100000)
+#define DSPI_CTAR_PASC_1CLK		(0x00000000)
+#define DSPI_CTAR_PDT(x)		(((x)&0x03)<<18)
+#define DSPI_CTAR_PDT_7CLK		(0x000A0000)
+#define DSPI_CTAR_PDT_5CLK		(0x00080000)
+#define DSPI_CTAR_PDT_3CLK		(0x00040000)
+#define DSPI_CTAR_PDT_1CLK		(0x00000000)
+#define DSPI_CTAR_PBR(x)		(((x)&0x03)<<16)
+#define DSPI_CTAR_PBR_7CLK		(0x00030000)
+#define DSPI_CTAR_PBR_5CLK		(0x00020000)
+#define DSPI_CTAR_PBR_3CLK		(0x00010000)
+#define DSPI_CTAR_PBR_1CLK		(0x00000000)
+#define DSPI_CTAR_CSSCK(x)		(((x)&0x0F)<<12)
+#define DSPI_CTAR_ASC(x)		(((x)&0x0F)<<8)
+#define DSPI_CTAR_DT(x)			(((x)&0x0F)<<4)
+#define DSPI_CTAR_BR(x)			(((x)&0x0F))
+
+/* Status */
+#define DSPI_SR_TCF			(0x80000000)
+#define DSPI_SR_TXRXS			(0x40000000)
+#define DSPI_SR_EOQF			(0x10000000)
+#define DSPI_SR_TFUF			(0x08000000)
+#define DSPI_SR_TFFF			(0x02000000)
+#define DSPI_SR_RFOF			(0x00080000)
+#define DSPI_SR_RFDF			(0x00020000)
+#define DSPI_SR_TXCTR(x)		(((x)&0x0F)<<12)
+#define DSPI_SR_TXPTR(x)		(((x)&0x0F)<<8)
+#define DSPI_SR_RXCTR(x)		(((x)&0x0F)<<4)
+#define DSPI_SR_RXPTR(x)		(((x)&0x0F))
+
+/* DMA/interrupt request selct and enable */
+#define DSPI_IRSR_TCFE			(0x80000000)
+#define DSPI_IRSR_EOQFE			(0x10000000)
+#define DSPI_IRSR_TFUFE			(0x08000000)
+#define DSPI_IRSR_TFFFE			(0x02000000)
+#define DSPI_IRSR_TFFFS			(0x01000000)
+#define DSPI_IRSR_RFOFE			(0x00080000)
+#define DSPI_IRSR_RFDFE			(0x00020000)
+#define DSPI_IRSR_RFDFS			(0x00010000)
+
+/* Transfer control - 32-bit access */
+#define DSPI_TFR_CONT			(0x80000000)
+#define DSPI_TFR_CTAS(x)		(((x)&0x07)<<12)
+#define DSPI_TFR_EOQ			(0x08000000)
+#define DSPI_TFR_CTCNT			(0x04000000)
+#define DSPI_TFR_CS7			(0x00800000)
+#define DSPI_TFR_CS6			(0x00400000)
+#define DSPI_TFR_CS5			(0x00200000)
+#define DSPI_TFR_CS4			(0x00100000)
+#define DSPI_TFR_CS3			(0x00080000)
+#define DSPI_TFR_CS2			(0x00040000)
+#define DSPI_TFR_CS1			(0x00020000)
+#define DSPI_TFR_CS0			(0x00010000)
+
+/* Transfer Fifo */
+#define DSPI_TFR_TXDATA(x)		(((x)&0xFFFF))
+
+/* Bit definitions and macros for DRFR */
+#define DSPI_RFR_RXDATA(x)		(((x)&0xFFFF))
+
+/* Bit definitions and macros for DTFDR group */
+#define DSPI_TFDR_TXDATA(x)		(((x)&0x0000FFFF))
+#define DSPI_TFDR_TXCMD(x)		(((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for DRFDR group */
+#define DSPI_RFDR_RXDATA(x)		(((x)&0x0000FFFF))
+
+/* Architecture-related operations */
+void dspi_chip_select(int cs);
+void dspi_chip_unselect(int cs);
+
+#endif				/* __DSPI_H__ */
diff --git a/arch/m68k/include/asm/coldfire/edma.h b/arch/m68k/include/asm/coldfire/edma.h
new file mode 100644
index 0000000..a89d02a
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/edma.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * EDMA Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __EDMA_H__
+#define __EDMA_H__
+
+/*********************************************************************
+* Enhanced DMA (EDMA)
+*********************************************************************/
+
+/* eDMA module registers */
+typedef struct edma_ctrl {
+	u32 cr;			/* 0x00 Control Register */
+	u32 es;			/* 0x04 Error Status Register */
+	u16 res1[3];		/* 0x08 - 0x0D */
+	u16 erq;		/* 0x0E Enable Request Register */
+	u16 res2[3];		/* 0x10 - 0x15 */
+	u16 eei;		/* 0x16 Enable Error Interrupt Request */
+	u8 serq;		/* 0x18 Set Enable Request */
+	u8 cerq;		/* 0x19 Clear Enable Request */
+	u8 seei;		/* 0x1A Set En Error Interrupt Request */
+	u8 ceei;		/* 0x1B Clear En Error Interrupt Request */
+	u8 cint;		/* 0x1C Clear Interrupt Enable */
+	u8 cerr;		/* 0x1D Clear Error */
+	u8 ssrt;		/* 0x1E Set START Bit */
+	u8 cdne;		/* 0x1F Clear DONE Status Bit */
+	u16 res3[3];		/* 0x20 - 0x25 */
+	u16 intr;		/* 0x26 Interrupt Request */
+	u16 res4[3];		/* 0x28 - 0x2D */
+	u16 err;		/* 0x2E Error Register */
+	u32 res5[52];		/* 0x30 - 0xFF */
+	u8 dchpri0;		/* 0x100 Channel 0 Priority */
+	u8 dchpri1;		/* 0x101 Channel 1 Priority */
+	u8 dchpri2;		/* 0x102 Channel 2 Priority */
+	u8 dchpri3;		/* 0x103 Channel 3 Priority */
+	u8 dchpri4;		/* 0x104 Channel 4 Priority */
+	u8 dchpri5;		/* 0x105 Channel 5 Priority */
+	u8 dchpri6;		/* 0x106 Channel 6 Priority */
+	u8 dchpri7;		/* 0x107 Channel 7 Priority */
+	u8 dchpri8;		/* 0x108 Channel 8 Priority */
+	u8 dchpri9;		/* 0x109 Channel 9 Priority */
+	u8 dchpri10;		/* 0x110 Channel 10 Priority */
+	u8 dchpri11;		/* 0x111 Channel 11 Priority */
+	u8 dchpri12;		/* 0x112 Channel 12 Priority */
+	u8 dchpri13;		/* 0x113 Channel 13 Priority */
+	u8 dchpri14;		/* 0x114 Channel 14 Priority */
+	u8 dchpri15;		/* 0x115 Channel 15 Priority */
+} edma_t;
+
+/* TCD - eDMA*/
+typedef struct tcd_ctrl {
+	u32 saddr;		/* 0x00 Source Address */
+	u16 attr;		/* 0x04 Transfer Attributes */
+	u16 soff;		/* 0x06 Signed Source Address Offset */
+	u32 nbytes;		/* 0x08 Minor Byte Count */
+	u32 slast;		/* 0x0C Last Source Address Adjustment */
+	u32 daddr;		/* 0x10 Destination address */
+	u16 citer;		/* 0x14 Cur Minor Loop Link, Major Loop Cnt */
+	u16 doff;		/* 0x16 Signed Destination Address Offset */
+	u32 dlast_sga;		/* 0x18 Last Dest Adr Adj/Scatter Gather Adr */
+	u16 biter;		/* 0x1C Minor Loop Lnk, Major Loop Cnt */
+	u16 csr;		/* 0x1E Control and Status */
+} tcd_st;
+
+typedef struct tcd_multiple {
+	tcd_st tcd[16];
+} tcd_t;
+
+/* Bit definitions and macros for EPPAR */
+#define EPORT_EPPAR_EPPA1(x)		(((x)&0x0003)<<2)
+#define EPORT_EPPAR_EPPA2(x)		(((x)&0x0003)<<4)
+#define EPORT_EPPAR_EPPA3(x)		(((x)&0x0003)<<6)
+#define EPORT_EPPAR_EPPA4(x)		(((x)&0x0003)<<8)
+#define EPORT_EPPAR_EPPA5(x)		(((x)&0x0003)<<10)
+#define EPORT_EPPAR_EPPA6(x)		(((x)&0x0003)<<12)
+#define EPORT_EPPAR_EPPA7(x)		(((x)&0x0003)<<14)
+#define EPORT_EPPAR_LEVEL		(0)
+#define EPORT_EPPAR_RISING		(1)
+#define EPORT_EPPAR_FALLING		(2)
+#define EPORT_EPPAR_BOTH		(3)
+#define EPORT_EPPAR_EPPA7_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA7_RISING	(0x4000)
+#define EPORT_EPPAR_EPPA7_FALLING	(0x8000)
+#define EPORT_EPPAR_EPPA7_BOTH		(0xC000)
+#define EPORT_EPPAR_EPPA6_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA6_RISING	(0x1000)
+#define EPORT_EPPAR_EPPA6_FALLING	(0x2000)
+#define EPORT_EPPAR_EPPA6_BOTH		(0x3000)
+#define EPORT_EPPAR_EPPA5_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA5_RISING	(0x0400)
+#define EPORT_EPPAR_EPPA5_FALLING	(0x0800)
+#define EPORT_EPPAR_EPPA5_BOTH		(0x0C00)
+#define EPORT_EPPAR_EPPA4_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA4_RISING	(0x0100)
+#define EPORT_EPPAR_EPPA4_FALLING	(0x0200)
+#define EPORT_EPPAR_EPPA4_BOTH		(0x0300)
+#define EPORT_EPPAR_EPPA3_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA3_RISING	(0x0040)
+#define EPORT_EPPAR_EPPA3_FALLING	(0x0080)
+#define EPORT_EPPAR_EPPA3_BOTH		(0x00C0)
+#define EPORT_EPPAR_EPPA2_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA2_RISING	(0x0010)
+#define EPORT_EPPAR_EPPA2_FALLING	(0x0020)
+#define EPORT_EPPAR_EPPA2_BOTH		(0x0030)
+#define EPORT_EPPAR_EPPA1_LEVEL		(0x0000)
+#define EPORT_EPPAR_EPPA1_RISING	(0x0004)
+#define EPORT_EPPAR_EPPA1_FALLING	(0x0008)
+#define EPORT_EPPAR_EPPA1_BOTH		(0x000C)
+
+/* Bit definitions and macros for EPDDR */
+#define EPORT_EPDDR_EPDD1		(0x02)
+#define EPORT_EPDDR_EPDD2		(0x04)
+#define EPORT_EPDDR_EPDD3		(0x08)
+#define EPORT_EPDDR_EPDD4		(0x10)
+#define EPORT_EPDDR_EPDD5		(0x20)
+#define EPORT_EPDDR_EPDD6		(0x40)
+#define EPORT_EPDDR_EPDD7		(0x80)
+
+/* Bit definitions and macros for EPIER */
+#define EPORT_EPIER_EPIE1		(0x02)
+#define EPORT_EPIER_EPIE2		(0x04)
+#define EPORT_EPIER_EPIE3		(0x08)
+#define EPORT_EPIER_EPIE4		(0x10)
+#define EPORT_EPIER_EPIE5		(0x20)
+#define EPORT_EPIER_EPIE6		(0x40)
+#define EPORT_EPIER_EPIE7		(0x80)
+
+/* Bit definitions and macros for EPDR */
+#define EPORT_EPDR_EPD1			(0x02)
+#define EPORT_EPDR_EPD2			(0x04)
+#define EPORT_EPDR_EPD3			(0x08)
+#define EPORT_EPDR_EPD4			(0x10)
+#define EPORT_EPDR_EPD5			(0x20)
+#define EPORT_EPDR_EPD6			(0x40)
+#define EPORT_EPDR_EPD7			(0x80)
+
+/* Bit definitions and macros for EPPDR */
+#define EPORT_EPPDR_EPPD1		(0x02)
+#define EPORT_EPPDR_EPPD2		(0x04)
+#define EPORT_EPPDR_EPPD3		(0x08)
+#define EPORT_EPPDR_EPPD4		(0x10)
+#define EPORT_EPPDR_EPPD5		(0x20)
+#define EPORT_EPPDR_EPPD6		(0x40)
+#define EPORT_EPPDR_EPPD7		(0x80)
+
+/* Bit definitions and macros for EPFR */
+#define EPORT_EPFR_EPF1			(0x02)
+#define EPORT_EPFR_EPF2			(0x04)
+#define EPORT_EPFR_EPF3			(0x08)
+#define EPORT_EPFR_EPF4			(0x10)
+#define EPORT_EPFR_EPF5			(0x20)
+#define EPORT_EPFR_EPF6			(0x40)
+#define EPORT_EPFR_EPF7			(0x80)
+
+#endif					/* __EDMA_H__ */
diff --git a/arch/m68k/include/asm/coldfire/eport.h b/arch/m68k/include/asm/coldfire/eport.h
new file mode 100644
index 0000000..0e64bef
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/eport.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Edge Port Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __EPORT_H__
+#define __EPORT_H__
+
+/* Edge Port Module (EPORT) */
+typedef struct eport {
+#ifdef CONFIG_MCF547x_8x
+	u16 par;	/* 0x00 */
+	u16 res0;	/* 0x02 */
+	u8 ddr;		/* 0x04 */
+	u8 ier;		/* 0x05 */
+	u16 res1;	/* 0x06 */
+	u8 dr;		/* 0x08 */
+	u8 pdr;		/* 0x09 */
+	u16 res2;	/* 0x0A */
+	u8 fr;		/* 0x0C */
+	u8 res3[3];	/* 0x0D */
+#else
+	u16 par;	/* 0x00 Pin Assignment */
+	u8 ddr;		/* 0x02 Data Direction */
+	u8 ier;		/* 0x03 Interrupt Enable */
+	u8 dr;		/* 0x04 Data */
+	u8 pdr;		/* 0x05 Pin Data */
+	u8 fr;		/* 0x06 Flag */
+	u8 res0;
+#endif
+} eport_t;
+
+/* EPPAR */
+#define EPORT_PAR_EPPA1(x)		(((x)&0x0003)<<2)
+#define EPORT_PAR_EPPA2(x)		(((x)&0x0003)<<4)
+#define EPORT_PAR_EPPA3(x)		(((x)&0x0003)<<6)
+#define EPORT_PAR_EPPA4(x)		(((x)&0x0003)<<8)
+#define EPORT_PAR_EPPA5(x)		(((x)&0x0003)<<10)
+#define EPORT_PAR_EPPA6(x)		(((x)&0x0003)<<12)
+#define EPORT_PAR_EPPA7(x)		(((x)&0x0003)<<14)
+#define EPORT_PAR_LEVEL			(0)
+#define EPORT_PAR_RISING		(1)
+#define EPORT_PAR_FALLING		(2)
+#define EPORT_PAR_BOTH			(3)
+#define EPORT_PAR_EPPA7_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA7_RISING		(0x4000)
+#define EPORT_PAR_EPPA7_FALLING		(0x8000)
+#define EPORT_PAR_EPPA7_BOTH		(0xC000)
+#define EPORT_PAR_EPPA6_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA6_RISING		(0x1000)
+#define EPORT_PAR_EPPA6_FALLING		(0x2000)
+#define EPORT_PAR_EPPA6_BOTH		(0x3000)
+#define EPORT_PAR_EPPA5_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA5_RISING		(0x0400)
+#define EPORT_PAR_EPPA5_FALLING		(0x0800)
+#define EPORT_PAR_EPPA5_BOTH		(0x0C00)
+#define EPORT_PAR_EPPA4_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA4_RISING		(0x0100)
+#define EPORT_PAR_EPPA4_FALLING		(0x0200)
+#define EPORT_PAR_EPPA4_BOTH		(0x0300)
+#define EPORT_PAR_EPPA3_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA3_RISING		(0x0040)
+#define EPORT_PAR_EPPA3_FALLING		(0x0080)
+#define EPORT_PAR_EPPA3_BOTH		(0x00C0)
+#define EPORT_PAR_EPPA2_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA2_RISING		(0x0010)
+#define EPORT_PAR_EPPA2_FALLING		(0x0020)
+#define EPORT_PAR_EPPA2_BOTH		(0x0030)
+#define EPORT_PAR_EPPA1_LEVEL		(0x0000)
+#define EPORT_PAR_EPPA1_RISING		(0x0004)
+#define EPORT_PAR_EPPA1_FALLING		(0x0008)
+#define EPORT_PAR_EPPA1_BOTH		(0x000C)
+
+/* EPDDR */
+#define EPORT_DDR_EPDD1			(0x02)
+#define EPORT_DDR_EPDD2			(0x04)
+#define EPORT_DDR_EPDD3			(0x08)
+#define EPORT_DDR_EPDD4			(0x10)
+#define EPORT_DDR_EPDD5			(0x20)
+#define EPORT_DDR_EPDD6			(0x40)
+#define EPORT_DDR_EPDD7			(0x80)
+
+/* EPIER */
+#define EPORT_IER_EPIE1			(0x02)
+#define EPORT_IER_EPIE2			(0x04)
+#define EPORT_IER_EPIE3			(0x08)
+#define EPORT_IER_EPIE4			(0x10)
+#define EPORT_IER_EPIE5			(0x20)
+#define EPORT_IER_EPIE6			(0x40)
+#define EPORT_IER_EPIE7			(0x80)
+
+/* EPDR */
+#define EPORT_DR_EPD1			(0x02)
+#define EPORT_DR_EPD2			(0x04)
+#define EPORT_DR_EPD3			(0x08)
+#define EPORT_DR_EPD4			(0x10)
+#define EPORT_DR_EPD5			(0x20)
+#define EPORT_DR_EPD6			(0x40)
+#define EPORT_DR_EPD7			(0x80)
+
+/* EPPDR */
+#define EPORT_PDR_EPPD1			(0x02)
+#define EPORT_PDR_EPPD2			(0x04)
+#define EPORT_PDR_EPPD3			(0x08)
+#define EPORT_PDR_EPPD4			(0x10)
+#define EPORT_PDR_EPPD5			(0x20)
+#define EPORT_PDR_EPPD6			(0x40)
+#define EPORT_PDR_EPPD7			(0x80)
+
+/* EPFR */
+#define EPORT_FR_EPF1			(0x02)
+#define EPORT_FR_EPF2			(0x04)
+#define EPORT_FR_EPF3			(0x08)
+#define EPORT_FR_EPF4			(0x10)
+#define EPORT_FR_EPF5			(0x20)
+#define EPORT_FR_EPF6			(0x40)
+#define EPORT_FR_EPF7			(0x80)
+
+#endif				/* __EPORT_H__ */
diff --git a/arch/m68k/include/asm/coldfire/flexbus.h b/arch/m68k/include/asm/coldfire/flexbus.h
new file mode 100644
index 0000000..c47787a
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/flexbus.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * FlexBus Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __FLEXBUS_H
+#define __FLEXBUS_H
+
+/*********************************************************************
+* FlexBus Chip Selects (FBCS)
+*********************************************************************/
+#ifdef CONFIG_M5235
+typedef struct fbcs {
+    u16 csar0;      /* Chip-select Address */
+    u16 res1;
+    u32 csmr0;      /* Chip-select Mask */
+    u16 res2;
+    u16 cscr0;      /* Chip-select Control */
+
+    u16 csar1;
+    u16 res3;
+    u32 csmr1;
+    u16 res4;
+    u16 cscr1;
+
+    u16 csar2;
+    u16 res5;
+    u32 csmr2;
+    u16 res6;
+    u16 cscr2;
+
+    u16 csar3;
+    u16 res7;
+    u32 csmr3;
+    u16 res8;
+    u16 cscr3;
+
+    u16 csar4;
+    u16 res9;
+    u32 csmr4;
+    u16 res10;
+    u16 cscr4;
+
+    u16 csar5;
+    u16 res11;
+    u32 csmr5;
+    u16 res12;
+    u16 cscr5;
+
+    u16 csar6;
+    u16 res13;
+    u32 csmr6;
+    u16 res14;
+    u16 cscr6;
+
+    u16 csar7;
+    u16 res15;
+    u32 csmr7;
+    u16 res16;
+    u16 cscr7;
+} fbcs_t;
+#else
+typedef struct fbcs {
+	u32 csar0;		/* Chip-select Address */
+	u32 csmr0;		/* Chip-select Mask */
+	u32 cscr0;		/* Chip-select Control */
+	u32 csar1;
+	u32 csmr1;
+	u32 cscr1;
+	u32 csar2;
+	u32 csmr2;
+	u32 cscr2;
+	u32 csar3;
+	u32 csmr3;
+	u32 cscr3;
+	u32 csar4;
+	u32 csmr4;
+	u32 cscr4;
+	u32 csar5;
+	u32 csmr5;
+	u32 cscr5;
+	u32 csar6;
+	u32 csmr6;
+	u32 cscr6;
+	u32 csar7;
+	u32 csmr7;
+	u32 cscr7;
+} fbcs_t;
+#endif
+
+#define FBCS_CSAR_BA(x)			((x) & 0xFFFF0000)
+
+#define FBCS_CSMR_BAM(x)		(((x) & 0xFFFF) << 16)
+#define FBCS_CSMR_BAM_MASK		(0x0000FFFF)
+#define FBCS_CSMR_BAM_4G		(0xFFFF0000)
+#define FBCS_CSMR_BAM_2G		(0x7FFF0000)
+#define FBCS_CSMR_BAM_1G		(0x3FFF0000)
+#define FBCS_CSMR_BAM_1024M		(0x3FFF0000)
+#define FBCS_CSMR_BAM_512M		(0x1FFF0000)
+#define FBCS_CSMR_BAM_256M		(0x0FFF0000)
+#define FBCS_CSMR_BAM_128M		(0x07FF0000)
+#define FBCS_CSMR_BAM_64M		(0x03FF0000)
+#define FBCS_CSMR_BAM_32M		(0x01FF0000)
+#define FBCS_CSMR_BAM_16M		(0x00FF0000)
+#define FBCS_CSMR_BAM_8M		(0x007F0000)
+#define FBCS_CSMR_BAM_4M		(0x003F0000)
+#define FBCS_CSMR_BAM_2M		(0x001F0000)
+#define FBCS_CSMR_BAM_1M		(0x000F0000)
+#define FBCS_CSMR_BAM_1024K		(0x000F0000)
+#define FBCS_CSMR_BAM_512K		(0x00070000)
+#define FBCS_CSMR_BAM_256K		(0x00030000)
+#define FBCS_CSMR_BAM_128K		(0x00010000)
+#define FBCS_CSMR_BAM_64K		(0x00000000)
+
+#ifdef CONFIG_M5249
+#define FBCS_CSMR_WP			(0x00000080)
+#define FBCS_CSMR_AM			(0x00000040)
+#define FBCS_CSMR_CI			(0x00000020)
+#define FBCS_CSMR_SC			(0x00000010)
+#define FBCS_CSMR_SD			(0x00000008)
+#define FBCS_CSMR_UC			(0x00000004)
+#define FBCS_CSMR_UD			(0x00000002)
+#else
+#define FBCS_CSMR_WP			(0x00000100)
+#endif
+#define FBCS_CSMR_V			(0x00000001)	/* Valid bit */
+
+#ifdef CONFIG_M5235
+#define FBCS_CSCR_SRWS(x)       (((x) & 0x3) << 14)
+#define FBCS_CSCR_IWS(x)        (((x) & 0xF) << 10)
+#define FBCS_CSCR_AA_ON         (1 << 8)
+#define FBCS_CSCR_AA_OFF        (0 << 8)
+#define FBCS_CSCR_PS_32         (0 << 6)
+#define FBCS_CSCR_PS_16         (2 << 6)
+#define FBCS_CSCR_PS_8          (1 << 6)
+#define FBCS_CSCR_BEM_ON        (1 << 5)
+#define FBCS_CSCR_BEM_OFF       (0 << 5)
+#define FBCS_CSCR_BSTR_ON       (1 << 4)
+#define FBCS_CSCR_BSTR_OFF      (0 << 4)
+#define FBCS_CSCR_BSTW_ON       (1 << 3)
+#define FBCS_CSCR_BSTW_OFF      (0 << 3)
+#define FBCS_CSCR_SWWS(x)       (((x) & 0x7) << 0)
+#else
+#define FBCS_CSCR_SWS(x)		(((x) & 0x3F) << 26)
+#define FBCS_CSCR_SWS_MASK		(0x03FFFFFF)
+#define FBCS_CSCR_SWSEN			(0x00800000)
+#define FBCS_CSCR_ASET(x)		(((x) & 0x03) << 20)
+#define FBCS_CSCR_ASET_MASK		(0xFFCFFFFF)
+#define FBCS_CSCR_RDAH(x)		(((x) & 0x03) << 18)
+#define FBCS_CSCR_RDAH_MASK		(0xFFF3FFFF)
+#define FBCS_CSCR_WRAH(x)		(((x) & 0x03) << 16)
+#define FBCS_CSCR_WRAH_MASK		(0xFFFCFFFF)
+#define FBCS_CSCR_WS(x)			(((x) & 0x3F) << 10)
+#define FBCS_CSCR_WS_MASK		(0xFFFF03FF)
+#define FBCS_CSCR_SBM			(0x00000200)
+#define FBCS_CSCR_AA			(0x00000100)
+#define FBCS_CSCR_PS(x)			(((x) & 0x03) << 6)
+#define FBCS_CSCR_PS_MASK		(0xFFFFFF3F)
+#define FBCS_CSCR_BEM			(0x00000020)
+#define FBCS_CSCR_BSTR			(0x00000010)
+#define FBCS_CSCR_BSTW			(0x00000008)
+
+#define FBCS_CSCR_PS_16			(0x00000080)
+#define FBCS_CSCR_PS_8			(0x00000040)
+#define FBCS_CSCR_PS_32			(0x00000000)
+#endif
+
+#endif				/* __FLEXBUS_H */
diff --git a/arch/m68k/include/asm/coldfire/flexcan.h b/arch/m68k/include/asm/coldfire/flexcan.h
new file mode 100644
index 0000000..7d8e9e2
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/flexcan.h
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Flex CAN Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __FLEXCAN_H__
+#define __FLEXCAN_H__
+
+/* FlexCan Message Buffer */
+typedef struct can_msgbuf_ctrl {
+#ifdef CONFIG_M5282
+	u8 tmstamp;		/* 0x00 Timestamp */
+	u8 ctrl;		/* 0x01 Control */
+	u16 idh;		/* 0x02 ID High */
+	u16 idl;		/* 0x04 ID High */
+	u8 data[8];		/* 0x06 8 Byte Data Field */
+	u16 res;		/* 0x0E */
+#else
+	u16 ctrl;		/* 0x00 Control/Status */
+	u16 tmstamp;		/* 0x02 Timestamp */
+	u32 id;			/* 0x04 Identifier */
+	u8 data[8];		/* 0x08 8 Byte Data Field */
+#endif
+} can_msg_t;
+
+#ifdef CONFIG_M5282
+/* MSGBUF CTRL */
+#define CAN_MSGBUF_CTRL_CODE(x)		(((x) & 0x0F) << 4)
+#define CAN_MSGBUF_CTRL_CODE_MASK	(0x0F)
+#define CAN_MSGBUF_CTRL_LEN(x)		((x) & 0x0F)
+#define CAN_MSGBUF_CTRL_LEN_MASK	(0xF0)
+
+/* MSGBUF ID */
+#define CAN_MSGBUF_IDH_STD(x)		(((x) & 0x07FF) << 5)
+#define CAN_MSGBUF_IDH_STD_MASK		(0xE003FFFF)
+#define CAN_MSGBUF_IDH_SRR		(0x0010)
+#define CAN_MSGBUF_IDH_IDE		(0x0080)
+#define CAN_MSGBUF_IDH_EXTH(x)		((x) & 0x07)
+#define CAN_MSGBUF_IDH_EXTH_MASK	(0xFFF8)
+#define CAN_MSGBUF_IDL_EXTL(x)		(((x) & 0x7FFF) << 1)
+#define CAN_MSGBUF_IDL_EXTL_MASK		(0xFFFE)
+#define CAN_MSGBUF_IDL_RTR		(0x0001)
+#else
+/* MSGBUF CTRL */
+#define CAN_MSGBUF_CTRL_CODE(x)		(((x) & 0x000F) << 8)
+#define CAN_MSGBUF_CTRL_CODE_MASK	(0xF0FF)
+#define CAN_MSGBUF_CTRL_SRR		(0x0040)
+#define CAN_MSGBUF_CTRL_IDE		(0x0020)
+#define CAN_MSGBUF_CTRL_RTR		(0x0010)
+#define CAN_MSGBUF_CTRL_LEN(x)		((x) & 0x000F)
+#define CAN_MSGBUF_CTRL_LEN_MASK	(0xFFF0)
+
+/* MSGBUF ID */
+#define CAN_MSGBUF_ID_STD(x)		(((x) & 0x000007FF) << 18)
+#define CAN_MSGBUF_ID_STD_MASK		(0xE003FFFF)
+#define CAN_MSGBUF_ID_EXT(x)		((x) & 0x0003FFFF)
+#define CAN_MSGBUF_ID_EXT_MASK		(0xFFFC0000)
+#endif
+
+/* FlexCan module */
+typedef struct can_ctrl {
+	u32 mcr;		/* 0x00 Module Configuration */
+	u32 ctrl;		/* 0x04 Control */
+	u32 timer;		/* 0x08 Free Running Timer */
+	u32 res1;		/* 0x0C */
+	u32 rxgmsk;		/* 0x10 Rx Global Mask */
+	u32 rx14msk;		/* 0x14 RxBuffer 14 Mask */
+	u32 rx15msk;		/* 0x18 RxBuffer 15 Mask */
+#ifdef CONFIG_M5282
+	u32 res2;		/* 0x1C */
+	u16 errstat;		/* 0x20 Error and status */
+	u16 imsk;		/* 0x22 Interrupt Mask */
+	u16 iflag;		/* 0x24 Interrupt Flag */
+	u16 errcnt;		/* 0x26 Error Counter */
+	u32 res3[3];		/* 0x28 - 0x33 */
+#else
+	u16 res2;		/* 0x1C */
+	u16 errcnt;		/* 0x1E Error Counter */
+	u16 res3;		/* 0x20 */
+	u16 errstat;		/* 0x22 Error and status */
+	u32 res4;		/* 0x24 */
+	u32 imsk;		/* 0x28 Interrupt Mask */
+	u32 res5;		/* 0x2C */
+	u16 iflag;		/* 0x30 Interrupt Flag */
+#endif
+	u32 res6[19];		/* 0x34 - 0x7F */
+	void *msgbuf;		/* 0x80 Message Buffer 0-15 */
+} can_t;
+
+/* MCR */
+#define CAN_MCR_MDIS			(0x80000000)
+#define CAN_MCR_FRZ			(0x40000000)
+#define CAN_MCR_HALT			(0x10000000)
+#define CAN_MCR_NORDY			(0x08000000)
+#define CAN_MCF_WAKEMSK			(0x04000000)	/* 5282 */
+#define CAN_MCR_SOFTRST			(0x02000000)
+#define CAN_MCR_FRZACK			(0x01000000)
+#define CAN_MCR_SUPV			(0x00800000)
+#define CAN_MCR_SELFWAKE		(0x00400000)	/* 5282 */
+#define CAN_MCR_APS			(0x00200000)	/* 5282 */
+#define CAN_MCR_LPMACK			(0x00100000)
+#define CAN_MCF_BCC			(0x00010000)
+#define CAN_MCR_MAXMB(x)		((x) & 0x0F)
+#define CAN_MCR_MAXMB_MASK		(0xFFFFFFF0)
+
+/* CTRL */
+#define CAN_CTRL_PRESDIV(x)		(((x) & 0xFF) << 24)
+#define CAN_CTRL_PRESDIV_MASK		(0x00FFFFFF)
+#define CAN_CTRL_RJW(x)			(((x) & 0x03) << 22)
+#define CAN_CTRL_RJW_MASK		(0xFF3FFFFF)
+#define CAN_CTRL_PSEG1(x)		(((x) & 0x07) << 19)
+#define CAN_CTRL_PSEG1_MASK		(0xFFC7FFFF)
+#define CAN_CTRL_PSEG2(x)		(((x) & 0x07) << 16)
+#define CAN_CTRL_PSEG2_MASK		(0xFFF8FFFF)
+#define CAN_CTRL_BOFFMSK		(0x00008000)
+#define CAN_CTRL_ERRMSK			(0x00004000)
+#define CAN_CTRL_CLKSRC			(0x00002000)
+#define CAN_CTRL_LPB			(0x00001000)
+#define CAN_CTRL_RXMODE			(0x00000400)	/* 5282 */
+#define CAN_CTRL_TXMODE(x)		(((x) & 0x03) << 8)	/* 5282 */
+#define CAN_CTRL_TXMODE_MASK		(0xFFFFFCFF)	/* 5282 */
+#define CAN_CTRL_TXMODE_CAN0		(0x00000000)	/* 5282 */
+#define CAN_CTRL_TXMODE_CAN1		(0x00000100)	/* 5282 */
+#define CAN_CTRL_TXMODE_OPEN		(0x00000200)	/* 5282 */
+#define CAN_CTRL_SMP			(0x00000080)
+#define CAN_CTRL_BOFFREC		(0x00000040)
+#define CAN_CTRL_TSYNC			(0x00000020)
+#define CAN_CTRL_LBUF			(0x00000010)
+#define CAN_CTRL_LOM			(0x00000008)
+#define CAN_CTRL_PROPSEG(x)		((x) & 0x07)
+#define CAN_CTRL_PROPSEG_MASK		(0xFFFFFFF8)
+
+/* TIMER */
+/* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */
+#define CAN_TIMER(x)			((x) & 0xFFFF)
+#define CAN_TIMER_MASK			(0xFFFF0000)
+
+/* RXGMASK */
+#ifdef CONFIG_M5282
+#define CAN_RXGMSK_MI_STD(x)		(((x) & 0x000007FF) << 21)
+#define CAN_RXGMSK_MI_STD_MASK		(0x001FFFFF)
+#define CAN_RXGMSK_MI_EXT(x)		(((x) & 0x0003FFFF) << 1)
+#define CAN_RXGMSK_MI_EXT_MASK		(0xFFF80001)
+#else
+#define CAN_RXGMSK_MI_STD(x)		(((x) & 0x000007FF) << 18)
+#define CAN_RXGMSK_MI_STD_MASK		(0xE003FFFF)
+#define CAN_RXGMSK_MI_EXT(x)		((x) & 0x0003FFFF)
+#define CAN_RXGMSK_MI_EXT_MASK		(0xFFFC0000)
+#endif
+
+/* ERRCNT */
+#define CAN_ERRCNT_RXECTR(x)		(((x) & 0xFF) << 8)
+#define CAN_ERRCNT_RXECTR_MASK		(0x00FF)
+#define CAN_ERRCNT_TXECTR(x)		((x) & 0xFF)
+#define CAN_ERRCNT_TXECTR_MASK		(0xFF00)
+
+/* ERRSTAT */
+#define CAN_ERRSTAT_BITERR1		(0x8000)
+#define CAN_ERRSTAT_BITERR0		(0x4000)
+#define CAN_ERRSTAT_ACKERR		(0x2000)
+#define CAN_ERRSTAT_CRCERR		(0x1000)
+#define CAN_ERRSTAT_FRMERR		(0x0800)
+#define CAN_ERRSTAT_STFERR		(0x0400)
+#define CAN_ERRSTAT_TXWRN		(0x0200)
+#define CAN_ERRSTAT_RXWRN		(0x0100)
+#define CAN_ERRSTAT_IDLE		(0x0080)
+#define CAN_ERRSTAT_TXRX		(0x0040)
+#define CAN_ERRSTAT_FLT_MASK		(0xFFCF)
+#define CAN_ERRSTAT_FLT_BUSOFF		(0x0020)
+#define CAN_ERRSTAT_FLT_PASSIVE		(0x0010)
+#define CAN_ERRSTAT_FLT_ACTIVE		(0x0000)
+#ifdef CONFIG_M5282
+#define CAN_ERRSTAT_BOFFINT		(0x0004)
+#define CAN_ERRSTAT_ERRINT		(0x0002)
+#else
+#define CAN_ERRSTAT_ERRINT		(0x0004)
+#define CAN_ERRSTAT_BOFFINT		(0x0002)
+#define CAN_ERRSTAT_WAKEINT		(0x0001)
+#endif
+
+/* IMASK */
+#ifdef CONFIG_M5253
+#define CAN_IMASK_BUFnM(x)		(1 << (x & 0xFFFFFFFF))
+#define CAN_IMASK_BUFnM_MASKBIT(x)	~CAN_IMASK_BUFnM(x)
+#else
+#define CAN_IMASK_BUFnM(x)		(1 << (x & 0xFFFF))
+#define CAN_IMASK_BUFnM_MASKBIT(x)	~CAN_IMASK_BUFnM(x)
+#endif
+
+/* IFLAG */
+#ifdef CONFIG_M5253
+#define CAN_IFLAG_BUFnM(x)		(1 << (x & 0xFFFFFFFF))
+#define CAN_IFLAG_BUFnM_MASKBIT(x)	~CAN_IFLAG_BUFnM(x)
+#else
+#define CAN_IFLAG_BUFnM(x)		(1 << (x & 0xFFFF))
+#define CAN_IFLAG_BUFnM_MASKBIT(x)	~CAN_IFLAG_BUFnM(x)
+#endif
+
+#endif				/* __FLEXCAN_H__ */
diff --git a/arch/m68k/include/asm/coldfire/intctrl.h b/arch/m68k/include/asm/coldfire/intctrl.h
new file mode 100644
index 0000000..7b42e65
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/intctrl.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Interrupt Controller Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __INTCTRL_H__
+#define __INTCTRL_H__
+
+#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
+    defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
+    defined(CONFIG_M547x) || defined(CONFIG_M548x)
+#	define	CONFIG_SYS_CF_INTC_REG1
+#endif
+
+typedef struct int0_ctrl {
+	/* Interrupt Controller 0 */
+	u32 iprh0;		/* 0x00 Pending High */
+	u32 iprl0;		/* 0x04 Pending Low */
+	u32 imrh0;		/* 0x08 Mask High */
+	u32 imrl0;		/* 0x0C Mask Low */
+	u32 frch0;		/* 0x10 Force High */
+	u32 frcl0;		/* 0x14 Force Low */
+#if defined(CONFIG_SYS_CF_INTC_REG1)
+	u8 irlr;		/* 0x18 */
+	u8 iacklpr;		/* 0x19 */
+	u16 res1[19];		/* 0x1a - 0x3c */
+#else
+	u16 res1;		/* 0x18 - 0x19 */
+	u16 icfg0;		/* 0x1A Configuration */
+	u8 simr0;		/* 0x1C Set Interrupt Mask */
+	u8 cimr0;		/* 0x1D Clear Interrupt Mask */
+	u8 clmask0;		/* 0x1E Current Level Mask */
+	u8 slmask;		/* 0x1F Saved Level Mask */
+	u32 res2[8];		/* 0x20 - 0x3F */
+#endif
+	u8 icr0[64];		/* 0x40 - 0x7F Control registers */
+	u32 res3[24];		/* 0x80 - 0xDF */
+	u8 swiack0;		/* 0xE0 Software Interrupt ack */
+	u8 res4[3];		/* 0xE1 - 0xE3 */
+	u8 L1iack0;		/* 0xE4 Level n interrupt ack */
+	u8 res5[3];		/* 0xE5 - 0xE7 */
+	u8 L2iack0;		/* 0xE8 Level n interrupt ack */
+	u8 res6[3];		/* 0xE9 - 0xEB */
+	u8 L3iack0;		/* 0xEC Level n interrupt ack */
+	u8 res7[3];		/* 0xED - 0xEF */
+	u8 L4iack0;		/* 0xF0 Level n interrupt ack */
+	u8 res8[3];		/* 0xF1 - 0xF3 */
+	u8 L5iack0;		/* 0xF4 Level n interrupt ack */
+	u8 res9[3];		/* 0xF5 - 0xF7 */
+	u8 L6iack0;		/* 0xF8 Level n interrupt ack */
+	u8 resa[3];		/* 0xF9 - 0xFB */
+	u8 L7iack0;		/* 0xFC Level n interrupt ack */
+	u8 resb[3];		/* 0xFD - 0xFF */
+} int0_t;
+
+typedef struct int1_ctrl {
+	/* Interrupt Controller 1 */
+	u32 iprh1;		/* 0x00 Pending High */
+	u32 iprl1;		/* 0x04 Pending Low */
+	u32 imrh1;		/* 0x08 Mask High */
+	u32 imrl1;		/* 0x0C Mask Low */
+	u32 frch1;		/* 0x10 Force High */
+	u32 frcl1;		/* 0x14 Force Low */
+#if defined(CONFIG_SYS_CF_INTC_REG1)
+	u8 irlr;		/* 0x18 */
+	u8 iacklpr;		/* 0x19 */
+	u16 res1[19];		/* 0x1a - 0x3c */
+#else
+	u16 res1;		/* 0x18 */
+	u16 icfg1;		/* 0x1A Configuration */
+	u8 simr1;		/* 0x1C Set Interrupt Mask */
+	u8 cimr1;		/* 0x1D Clear Interrupt Mask */
+	u16 res2;		/* 0x1E - 0x1F */
+	u32 res3[8];		/* 0x20 - 0x3F */
+#endif
+	u8 icr1[64];		/* 0x40 - 0x7F */
+	u32 res4[24];		/* 0x80 - 0xDF */
+	u8 swiack1;		/* 0xE0 Software Interrupt ack */
+	u8 res5[3];		/* 0xE1 - 0xE3 */
+	u8 L1iack1;		/* 0xE4 Level n interrupt ack */
+	u8 res6[3];		/* 0xE5 - 0xE7 */
+	u8 L2iack1;		/* 0xE8 Level n interrupt ack */
+	u8 res7[3];		/* 0xE9 - 0xEB */
+	u8 L3iack1;		/* 0xEC Level n interrupt ack */
+	u8 res8[3];		/* 0xED - 0xEF */
+	u8 L4iack1;		/* 0xF0 Level n interrupt ack */
+	u8 res9[3];		/* 0xF1 - 0xF3 */
+	u8 L5iack1;		/* 0xF4 Level n interrupt ack */
+	u8 resa[3];		/* 0xF5 - 0xF7 */
+	u8 L6iack1;		/* 0xF8 Level n interrupt ack */
+	u8 resb[3];		/* 0xF9 - 0xFB */
+	u8 L7iack1;		/* 0xFC Level n interrupt ack */
+	u8 resc[3];		/* 0xFD - 0xFF */
+} int1_t;
+
+typedef struct intgack_ctrl1 {
+	/* Global IACK Registers */
+	u8 swiack;		/* 0x00 Global Software Interrupt ack */
+	u8 res0[0x3];
+	u8 gl1iack;		/* 0x04 */
+	u8 resv1[0x3];
+	u8 gl2iack;		/* 0x08 */
+	u8 res2[0x3];
+	u8 gl3iack;		/* 0x0C */
+	u8 res3[0x3];
+	u8 gl4iack;		/* 0x10 */
+	u8 res4[0x3];
+	u8 gl5iack;		/* 0x14 */
+	u8 res5[0x3];
+	u8 gl6iack;		/* 0x18 */
+	u8 res6[0x3];
+	u8 gl7iack;		/* 0x1C */
+	u8 res7[0x3];
+} intgack_t;
+
+#define INTC_IPRH_INT63			(0x80000000)
+#define INTC_IPRH_INT62			(0x40000000)
+#define INTC_IPRH_INT61			(0x20000000)
+#define INTC_IPRH_INT60			(0x10000000)
+#define INTC_IPRH_INT59			(0x08000000)
+#define INTC_IPRH_INT58			(0x04000000)
+#define INTC_IPRH_INT57			(0x02000000)
+#define INTC_IPRH_INT56			(0x01000000)
+#define INTC_IPRH_INT55			(0x00800000)
+#define INTC_IPRH_INT54			(0x00400000)
+#define INTC_IPRH_INT53			(0x00200000)
+#define INTC_IPRH_INT52			(0x00100000)
+#define INTC_IPRH_INT51			(0x00080000)
+#define INTC_IPRH_INT50			(0x00040000)
+#define INTC_IPRH_INT49			(0x00020000)
+#define INTC_IPRH_INT48			(0x00010000)
+#define INTC_IPRH_INT47			(0x00008000)
+#define INTC_IPRH_INT46			(0x00004000)
+#define INTC_IPRH_INT45			(0x00002000)
+#define INTC_IPRH_INT44			(0x00001000)
+#define INTC_IPRH_INT43			(0x00000800)
+#define INTC_IPRH_INT42			(0x00000400)
+#define INTC_IPRH_INT41			(0x00000200)
+#define INTC_IPRH_INT40			(0x00000100)
+#define INTC_IPRH_INT39			(0x00000080)
+#define INTC_IPRH_INT38			(0x00000040)
+#define INTC_IPRH_INT37			(0x00000020)
+#define INTC_IPRH_INT36			(0x00000010)
+#define INTC_IPRH_INT35			(0x00000008)
+#define INTC_IPRH_INT34			(0x00000004)
+#define INTC_IPRH_INT33			(0x00000002)
+#define INTC_IPRH_INT32			(0x00000001)
+
+#define INTC_IPRL_INT31			(0x80000000)
+#define INTC_IPRL_INT30			(0x40000000)
+#define INTC_IPRL_INT29			(0x20000000)
+#define INTC_IPRL_INT28			(0x10000000)
+#define INTC_IPRL_INT27			(0x08000000)
+#define INTC_IPRL_INT26			(0x04000000)
+#define INTC_IPRL_INT25			(0x02000000)
+#define INTC_IPRL_INT24			(0x01000000)
+#define INTC_IPRL_INT23			(0x00800000)
+#define INTC_IPRL_INT22			(0x00400000)
+#define INTC_IPRL_INT21			(0x00200000)
+#define INTC_IPRL_INT20			(0x00100000)
+#define INTC_IPRL_INT19			(0x00080000)
+#define INTC_IPRL_INT18			(0x00040000)
+#define INTC_IPRL_INT17			(0x00020000)
+#define INTC_IPRL_INT16			(0x00010000)
+#define INTC_IPRL_INT15			(0x00008000)
+#define INTC_IPRL_INT14			(0x00004000)
+#define INTC_IPRL_INT13			(0x00002000)
+#define INTC_IPRL_INT12			(0x00001000)
+#define INTC_IPRL_INT11			(0x00000800)
+#define INTC_IPRL_INT10			(0x00000400)
+#define INTC_IPRL_INT9			(0x00000200)
+#define INTC_IPRL_INT8			(0x00000100)
+#define INTC_IPRL_INT7			(0x00000080)
+#define INTC_IPRL_INT6			(0x00000040)
+#define INTC_IPRL_INT5			(0x00000020)
+#define INTC_IPRL_INT4			(0x00000010)
+#define INTC_IPRL_INT3			(0x00000008)
+#define INTC_IPRL_INT2			(0x00000004)
+#define INTC_IPRL_INT1			(0x00000002)
+#define INTC_IPRL_INT0			(0x00000001)
+
+#define INTC_IMRLn_MASKALL		(0x00000001)
+
+#define INTC_IRLR(x)			(((x) & 0x7F) << 1)
+#define INTC_IRLR_MASK			(0x01)
+
+#define INTC_IACKLPR_LVL(x)		(((x) & 0x07) << 4)
+#define INTC_IACKLPR_LVL_MASK		(0x8F)
+#define INTC_IACKLPR_PRI(x)		((x) & 0x0F)
+#define INTC_IACKLPR_PRI_MASK		(0xF0)
+
+#if defined(CONFIG_SYS_CF_INTC_REG1)
+#define INTC_ICR_IL(x)			(((x) & 0x07) << 3)
+#define INTC_ICR_IL_MASK		(0xC7)
+#define INTC_ICR_IP(x)			((x) & 0x07)
+#define INTC_ICR_IP_MASK		(0xF8)
+#else
+#define INTC_ICR_IL(x)			((x) & 0x07)
+#define INTC_ICR_IL_MASK		(0xF8)
+#endif
+
+#define INTC_ICONFIG_ELVLPRI_MASK	(0x01FF)
+#define INTC_ICONFIG_ELVLPRI7		(0x8000)
+#define INTC_ICONFIG_ELVLPRI6		(0x4000)
+#define INTC_ICONFIG_ELVLPRI5		(0x2000)
+#define INTC_ICONFIG_ELVLPRI4		(0x1000)
+#define INTC_ICONFIG_ELVLPRI3		(0x0800)
+#define INTC_ICONFIG_ELVLPRI2		(0x0400)
+#define INTC_ICONFIG_ELVLPRI1		(0x0200)
+#define INTC_ICONFIG_EMASK		(0x0020)
+
+#define INTC_SIMR_ALL			(0x40)
+#define INTC_SIMR(x)			((x) & 0x3F)
+#define INTC_SIMR_MASK			(0x80)
+
+#define INTC_CIMR_ALL			(0x40)
+#define INTC_CIMR(x)			((x) & 0x3F)
+#define INTC_CIMR_MASK			(0x80)
+
+#define INTC_CLMASK(x)			((x) & 0x0F)
+#define INTC_CLMASK_MASK		(0xF0)
+
+#define INTC_SLMASK(x)			((x) & 0x0F)
+#define INTC_SLMASK_MASK		(0xF0)
+
+#endif				/* __INTCTRL_H__ */
diff --git a/arch/m68k/include/asm/coldfire/lcd.h b/arch/m68k/include/asm/coldfire/lcd.h
new file mode 100644
index 0000000..a347bed
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/lcd.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * LCD controller Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __LCDC_H__
+#define __LCDC_H__
+
+/* LCD module registers */
+typedef struct lcd_ctrl {
+	u32 ssar;		/* 0x00 Screen Start Address Register */
+	u32 sr;			/* 0x04 LCD Size Register */
+	u32 vpw;		/* 0x08 Virtual Page Width Register */
+	u32 cpr;		/* 0x0C Cursor Position Register */
+	u32 cwhb;		/* 0x10 Cursor Width Height and Blink Register */
+	u32 ccmr;		/* 0x14 Color Cursor Mapping Register */
+	u32 pcr;		/* 0x18 Panel Configuration Register */
+	u32 hcr;		/* 0x1C Horizontal Configuration Register */
+	u32 vcr;		/* 0x20 Vertical Configuration Register */
+	u32 por;		/* 0x24 Panning Offset Register */
+	u32 scr;		/* 0x28 Sharp Configuration Register */
+	u32 pccr;		/* 0x2C PWM Contrast Control Register */
+	u32 dcr;		/* 0x30 DMA Control Register */
+	u32 rmcr;		/* 0x34 Refresh Mode Control Register */
+	u32 icr;		/* 0x38 Refresh Mode Control Register */
+	u32 ier;		/* 0x3C Interrupt Enable Register */
+	u32 isr;		/* 0x40 Interrupt Status Register */
+	u32 res[4];
+	u32 gwsar;		/* 0x50 Graphic Window Start Address Register */
+	u32 gwsr;		/* 0x54 Graphic Window Size Register */
+	u32 gwvpw;		/* 0x58 Graphic Window Virtual Page Width Register */
+	u32 gwpor;		/* 0x5C Graphic Window Panning Offset Register */
+	u32 gwpr;		/* 0x60 Graphic Window Position Register */
+	u32 gwcr;		/* 0x64 Graphic Window Control Register */
+	u32 gwdcr;		/* 0x68 Graphic Window DMA Control Register */
+} lcd_t;
+
+typedef struct lcdbg_ctrl {
+	u32 bglut[255];
+} lcdbg_t;
+
+typedef struct lcdgw_ctrl {
+	u32 gwlut[255];
+} lcdgw_t;
+
+/* Bit definitions and macros for LCDC_LSSAR */
+#define LCDC_SSAR_SSA(x)		(((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LSR */
+#define LCDC_SR_XMAX(x)			(((x)&0x0000003F)<<20)
+#define LCDC_SR_YMAX(x)			((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LVPWR */
+#define LCDC_VPWR_VPW(x)		(((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LCPR */
+#define LCDC_CPR_CC(x)			(((x)&0x00000003)<<30)
+#define LCDC_CPR_CC_AND			(0xC0000000)
+#define LCDC_CPR_CC_XOR			(0x80000000)
+#define LCDC_CPR_CC_OR			(0x40000000)
+#define LCDC_CPR_CC_TRANSPARENT		(0x00000000)
+#define LCDC_CPR_OP			(0x10000000)
+#define LCDC_CPR_CXP(x)			(((x)&0x000003FF)<<16)
+#define LCDC_CPR_CYP(x)			((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LCWHBR */
+#define LCDC_CWHBR_BK_EN		(0x80000000)
+#define LCDC_CWHBR_CW(x)		(((x)&0x0000001F)<<24)
+#define LCDC_CWHBR_CH(x)		(((x)&0x0000001F)<<16)
+#define LCDC_CWHBR_BD(x)		((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_LCCMR */
+#define LCDC_CCMR_CUR_COL_R(x)		(((x)&0x0000003F)<<12)
+#define LCDC_CCMR_CUR_COL_G(x)		(((x)&0x0000003F)<<6)
+#define LCDC_CCMR_CUR_COL_B(x)		((x)&0x0000003F)
+
+/* Bit definitions and macros for LCDC_LPCR */
+#define LCDC_PCR_PANEL_TYPE(x)		(((x)&0x00000003)<<30)
+#define LCDC_PCR_MODE_TFT		(0xC0000000)
+#define LCDC_PCR_MODE_CSTN		(0x40000000)
+#define LCDC_PCR_MODE_MONOCHROME	(0x00000000)
+#define LCDC_PCR_TFT			(0x80000000)
+#define LCDC_PCR_COLOR			(0x40000000)
+#define LCDC_PCR_PBSIZ(x)		(((x)&0x00000003)<<28)
+#define LCDC_PCR_PBSIZ_8		(0x30000000)
+#define LCDC_PCR_PBSIZ_4		(0x20000000)
+#define LCDC_PCR_PBSIZ_2		(0x10000000)
+#define LCDC_PCR_PBSIZ_1		(0x00000000)
+#define LCDC_PCR_BPIX(x)		(((x)&0x00000007)<<25)
+#define LCDC_PCR_BPIX_18bpp		(0x0C000000)
+#define LCDC_PCR_BPIX_16bpp		(0x0A000000)
+#define LCDC_PCR_BPIX_12bpp		(0x08000000)
+#define LCDC_PCR_BPIX_8bpp		(0x06000000)
+#define LCDC_PCR_BPIX_4bpp		(0x04000000)
+#define LCDC_PCR_BPIX_2bpp		(0x02000000)
+#define LCDC_PCR_BPIX_1bpp		(0x00000000)
+#define LCDC_PCR_PIXPOL			(0x01000000)
+#define LCDC_PCR_FLM			(0x00800000)
+#define LCDC_PCR_LPPOL			(0x00400000)
+#define LCDC_PCR_CLKPOL			(0x00200000)
+#define LCDC_PCR_OEPOL			(0x00100000)
+#define LCDC_PCR_SCLKIDLE		(0x00080000)
+#define LCDC_PCR_ENDSEL			(0x00040000)
+#define LCDC_PCR_SWAP_SEL		(0x00020000)
+#define LCDC_PCR_REV_VS			(0x00010000)
+#define LCDC_PCR_ACDSEL			(0x00008000)
+#define LCDC_PCR_ACD(x)			(((x)&0x0000007F)<<8)
+#define LCDC_PCR_SCLKSEL		(0x00000080)
+#define LCDC_PCR_SHARP			(0x00000040)
+#define LCDC_PCR_PCD(x)			((x)&0x0000003F)
+
+/* Bit definitions and macros for LCDC_LHCR */
+#define LCDC_HCR_H_WIDTH(x)		(((x)&0x0000003F)<<26)
+#define LCDC_HCR_H_WAIT_1(x)		(((x)&0x000000FF)<<8)
+#define LCDC_HCR_H_WAIT_2(x)		((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_LVCR */
+#define LCDC_VCR_V_WIDTH(x)		(((x)&0x0000003F)<<26)
+#define LCDC_VCR_V_WAIT_1(x)		(((x)&0x000000FF)<<8)
+#define LCDC_VCR_V_WAIT_2(x)		((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_SCR */
+#define LCDC_SCR_PS_R_DELAY(x)		(((x)&0x0000003F) << 26)
+#define LCDC_SCR_CLS_R_DELAY(x)		(((x)&0x000000FF) << 16)
+#define LCDC_SCR_RTG_DELAY(x)		(((x)&0x0000000F) << 8)
+#define LCDC_SCR_GRAY2(x)		(((x)&0x0000000F) << 4)
+#define LCDC_SCR_GRAY1(x)		((x)&&0x0000000F)
+
+/* Bit definitions and macros for LCDC_LPCCR */
+#define LCDC_PCCR_CLS_HI_WID(x)		(((x)&0x000001FF)<<16)
+#define LCDC_PCCR_LDMSK			(0x00008000)
+#define LCDC_PCCR_SCR(x)		(((x)&0x00000003)<<9)
+#define LCDC_PCCR_SCR_LCDCLK		(0x00000400)
+#define LCDC_PCCR_SCR_PIXCLK		(0x00000200)
+#define LCDC_PCCR_SCR_LNPULSE		(0x00000000)
+#define LCDC_PCCR_CC_EN			(0x00000100)
+#define LCDC_PCCR_PW(x)			((x)&0x000000FF)
+
+/* Bit definitions and macros for LCDC_LDCR */
+#define LCDC_DCR_BURST			(0x80000000)
+#define LCDC_DCR_HM(x)			(((x)&0x0000001F)<<16)
+#define LCDC_DCR_TM(x)			((x)&0x0000001F)
+
+/* Bit definitions and macros for LCDC_LRMCR */
+#define LCDC_RMCR_SEL_REF		(0x00000001)
+
+/* Bit definitions and macros for LCDC_LICR */
+#define LCDC_ICR_GW_INT_CON		(0x00000010)
+#define LCDC_ICR_INTSYN			(0x00000004)
+#define LCDC_ICR_INTCON			(0x00000001)
+
+/* Bit definitions and macros for LCDC_LIER */
+#define LCDC_IER_GW_UDR			(0x00000080)
+#define LCDC_IER_GW_ERR			(0x00000040)
+#define LCDC_IER_GW_EOF			(0x00000020)
+#define LCDC_IER_GW_BOF			(0x00000010)
+#define LCDC_IER_UDR			(0x00000008)
+#define LCDC_IER_ERR			(0x00000004)
+#define LCDC_IER_EOF			(0x00000002)
+#define LCDC_IER_BOF			(0x00000001)
+
+/* Bit definitions and macros for LCDC_LGWSAR */
+#define LCDC_GWSAR_GWSA(x)		(((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for LCDC_LGWSR */
+#define LCDC_GWSR_GWW(x)		(((x)&0x0000003F)<<20)
+#define LCDC_GWSR_GWH(x)		((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LGWVPWR */
+#define LCDC_GWVPWR_GWVPW(x)		((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LGWPOR */
+#define LCDC_GWPOR_GWPO(x)		((x)&0x0000001F)
+
+/* Bit definitions and macros for LCDC_LGWPR */
+#define LCDC_GWPR_GWXP(x)		(((x)&0x000003FF)<<16)
+#define LCDC_GWPR_GWYP(x)		((x)&0x000003FF)
+
+/* Bit definitions and macros for LCDC_LGWCR */
+#define LCDC_GWCR_GWAV(x)		(((x)&0x000000FF)<<24)
+#define LCDC_GWCR_GWCKE			(0x00800000)
+#define LCDC_LGWCR_GWE			(0x00400000)
+#define LCDC_LGWCR_GW_RVS		(0x00200000)
+#define LCDC_LGWCR_GWCKR(x)		(((x)&0x0000003F)<<12)
+#define LCDC_LGWCR_GWCKG(x)		(((x)&0x0000003F)<<6)
+#define LCDC_LGWCR_GWCKB(x)		((x)&0x0000003F)
+
+/* Bit definitions and macros for LCDC_LGWDCR */
+#define LCDC_LGWDCR_GWBT		(0x80000000)
+#define LCDC_LGWDCR_GWHM(x)		(((x)&0x0000001F)<<16)
+#define LCDC_LGWDCR_GWTM(x)		((x)&0x0000001F)
+
+#endif				/* __LCDC_H__ */
diff --git a/arch/m68k/include/asm/coldfire/mdha.h b/arch/m68k/include/asm/coldfire/mdha.h
new file mode 100644
index 0000000..be3dae9
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/mdha.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Message Digest Hardware Accelerator Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __MDHA_H__
+#define __MDHA_H__
+
+/* Message Digest Hardware Accelerator */
+typedef struct mdha_ctrl {
+	u32 mr;			/* 0x00 MDHA Mode */
+	u32 cr;			/* 0x04 Control */
+	u32 cmd;		/* 0x08 Command */
+	u32 sr;			/* 0x0C Status */
+	u32 isr;		/* 0x10 Interrupt Status */
+	u32 imr;		/* 0x14 Interrupt Mask */
+	u32 dsz;		/* 0x1C Data Size */
+	u32 inp;		/* 0x20 Input FIFO */
+	u32 res1[3];		/* 0x24 - 0x2F */
+	u32 mda0;		/* 0x30 Message Digest AO */
+	u32 mdb0;		/* 0x34 Message Digest BO */
+	u32 mdc0;		/* 0x38 Message Digest CO */
+	u32 mdd0;		/* 0x3C Message Digest DO */
+	u32 mde0;		/* 0x40 Message Digest EO */
+	u32 mdsz;		/* 0x44 Message Data Size */
+	u32 res[10];		/* 0x48 - 0x6F */
+	u32 mda1;		/* 0x70 Message Digest A1 */
+	u32 mdb1;		/* 0x74 Message Digest B1 */
+	u32 mdc1;		/* 0x78 Message Digest C1 */
+	u32 mdd1;		/* 0x7C Message Digest D1 */
+	u32 mde1;		/* 0x80 Message Digest E1 */
+} mdha_t;
+
+#define MDHA_MR_SSL		(0x00000400)
+#define MDHA_MR_MACFUL		(0x00000200)
+#define MDHA_MR_SWAP		(0x00000100)
+#define MDHA_MR_OPAD		(0x00000080)
+#define MDHA_MR_IPAD		(0x00000040)
+#define MDHA_MR_INIT		(0x00000020)
+#define MDHA_MR_MAC(x)		(((x) & 0x03) << 3)
+#define MDHA_MR_MAC_MASK	(0xFFFFFFE7)
+#define MDHA_MR_MAC_EHMAC	(0x00000010)
+#define MDHA_MR_MAC_HMAC	(0x00000008)
+#define MDHA_MR_MAC_NONE	(0x00000000)
+#define MDHA_MR_PDATA		(0x00000004)
+#define MDHA_MR_ALG		(0x00000001)
+
+#define MDHA_CR_DMAL(x)		(((x) & 0x1F) << 16)	/* 532x */
+#define MDHA_CR_DMAL_MASK	(0xFFE0FFFF)		/* 532x */
+#define MDHA_CR_END		(0x00000004)		/* 532x */
+#define MDHA_CR_DMA		(0x00000002)		/* 532x */
+#define MDHA_CR_IE		(0x00000001)
+
+#define MDHA_CMD_GO		(0x00000008)
+#define MDHA_CMD_CI		(0x00000004)
+#define MDHA_CMD_RI		(0x00000001)
+#define MDHA_CMD_SWR		(0x00000001)
+
+#define MDHA_SR_IFL(x)		(((x) & 0xFF) << 16)
+#define MDHA_SR_IFL_MASK	(0xFF00FFFF)
+#define MDHA_SR_APD(x)		(((x) & 0x7) << 13)
+#define MDHA_SR_APD_MASK	(0xFFFF1FFF)
+#define MDHA_SR_FS(x)		(((x) & 0x7) << 8)
+#define MDHA_SR_FS_MASK		(0xFFFFF8FF)
+#define MDHA_SR_GNW		(0x00000080)
+#define MDHA_SR_HSH		(0x00000040)
+#define MDHA_SR_BUSY		(0x00000010)
+#define MDHA_SR_RD		(0x00000008)
+#define MDHA_SR_ERR		(0x00000004)
+#define MDHA_SR_DONE		(0x00000002)
+#define MDHA_SR_INT		(0x00000001)
+
+#define MDHA_ISR_DRL		(0x00000400)		/* 532x */
+#define MDHA_ISR_GTDS		(0x00000200)
+#define MDHA_ISR_ERE		(0x00000100)
+#define MDHA_ISR_RMDP		(0x00000080)
+#define MDHA_ISR_DSE		(0x00000020)
+#define MDHA_ISR_IME		(0x00000010)
+#define MDHA_ISR_NEIF		(0x00000004)
+#define MDHA_ISR_IFO		(0x00000001)
+
+#endif				/* __MDHA_H__ */
diff --git a/arch/m68k/include/asm/coldfire/pwm.h b/arch/m68k/include/asm/coldfire/pwm.h
new file mode 100644
index 0000000..1b83acf
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/pwm.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Pulse Width Modulation Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __ATA_H__
+#define __ATA_H__
+
+/* Pulse Width Modulation (PWM) */
+typedef struct pwm_ctrl {
+#ifdef CONFIG_M5272
+	u8 cr0;
+	u8 res1[3];
+	u8 cr1;
+	u8 res2[3];
+	u8 cr2;
+	u8 res3[7];
+	u8 pwr0;
+	u8 res4[3];
+	u8 pwr1;
+	u8 res5[3];
+	u8 pwr2;
+	u8 res6[7];
+#else
+	u8 en;			/* 0x00 PWM Enable */
+	u8 pol;			/* 0x01 Polarity */
+	u8 clk;			/* 0x02 Clock Select */
+	u8 prclk;		/* 0x03 Prescale Clock Select */
+	u8 cae;			/* 0x04 Center Align Enable */
+	u8 ctl;			/* 0x05 Control */
+	u16 res1;		/* 0x06 - 0x07 */
+	u8 scla;		/* 0x08 Scale A */
+	u8 sclb;		/* 0x09 Scale B */
+	u16 res2;		/* 0x0A - 0x0B */
+#ifdef CONFIG_M5275
+	u8 cnt[4];		/* 0x0C Channel n Counter */
+	u16 res3;		/* 0x10 - 0x11 */
+	u8 per[4];		/* 0x14 Channel n Period */
+	u16 res4;		/* 0x16 - 0x17 */
+	u8 dty[4];		/* 0x18 Channel n Duty */
+#else
+	u8 cnt[8];		/* 0x0C Channel n Counter */
+	u8 per[8];		/* 0x14 Channel n Period */
+	u8 dty[8];		/* 0x1C Channel n Duty */
+	u8 sdn;			/* 0x24 Shutdown */
+	u8 res3[3];		/* 0x25 - 0x27 */
+#endif				/* CONFIG_M5275 */
+#endif				/* CONFIG_M5272 */
+} pwm_t;
+
+#ifdef CONFIG_M5272
+
+#define PWM_CR_EN			(0x80)
+#define PWM_CR_FRC1			(0x40)
+#define PWM_CR_LVL			(0x20)
+#define PWM_CR_CLKSEL(x)		((x) & 0x0F)
+#define PWM_CR_CLKSEL_MASK		(0xF0)
+
+#else
+
+#define PWM_EN_PWMEn(x)			(1 << ((x) & 0x07))
+#define PWM_EN_PWMEn_MASK		(0xF0)
+
+#define PWM_POL_PPOLn(x)		(1 << ((x) & 0x07))
+#define PWM_POL_PPOLn_MASK		(0xF0)
+
+#define PWM_CLK_PCLKn(x)		(1 << ((x) & 0x07))
+#define PWM_CLK_PCLKn_MASK		(0xF0)
+
+#define PWM_PRCLK_PCKB(x)		(((x) & 0x07) << 4)
+#define PWM_PRCLK_PCKB_MASK		(0x8F)
+#define PWM_PRCLK_PCKA(x)		((x) & 0x07)
+#define PWM_PRCLK_PCKA_MASK		(0xF8)
+
+#define PWM_CLK_PCLKn(x)		(1 << ((x) & 0x07))
+#define PWM_CLK_PCLKn_MASK		(0xF0)
+
+#define PWM_CTL_CON67			(0x80)
+#define PWM_CTL_CON45			(0x40)
+#define PWM_CTL_CON23			(0x20)
+#define PWM_CTL_CON01			(0x10)
+#define PWM_CTL_PSWAR			(0x08)
+#define PWM_CTL_PFRZ			(0x04)
+
+#define PWM_SDN_IF			(0x80)
+#define PWM_SDN_IE			(0x40)
+#define PWM_SDN_RESTART			(0x20)
+#define PWM_SDN_LVL			(0x10)
+#define PWM_SDN_PWM7IN			(0x04)
+#define PWM_SDN_PWM7IL			(0x02)
+#define PWM_SDN_SDNEN			(0x01)
+
+#endif				/* CONFIG_M5272 */
+
+#endif				/* __ATA_H__ */
diff --git a/arch/m68k/include/asm/coldfire/qspi.h b/arch/m68k/include/asm/coldfire/qspi.h
new file mode 100644
index 0000000..dd4565a
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/qspi.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Queue Serial Peripheral Interface Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __QSPI_H__
+#define __QSPI_H__
+
+/* QSPI module registers */
+typedef struct qspi_ctrl {
+	u16 mr;			/* 0x00 Mode */
+	u16 res1;
+	u16 dlyr;		/* 0x04 Delay */
+	u16 res2;
+	u16 wr;			/* 0x08 Wrap */
+	u16 res3;
+	u16 ir;			/* 0x0C Interrupt */
+	u16 res4;
+	u16 ar;			/* 0x10 Address */
+	u16 res5;
+	u16 dr;			/* 0x14 Data */
+	u16 res6;
+} qspi_t;
+
+/* MR */
+#define QSPI_QMR_MSTR			(0x8000)
+#define QSPI_QMR_DOHIE			(0x4000)
+#define QSPI_QMR_BITS(x)		(((x)&0x000F)<<10)
+#define QSPI_QMR_BITS_MASK		(0xC3FF)
+#define QSPI_QMR_BITS_8			(0x2000)
+#define QSPI_QMR_BITS_9			(0x2400)
+#define QSPI_QMR_BITS_10		(0x2800)
+#define QSPI_QMR_BITS_11		(0x2C00)
+#define QSPI_QMR_BITS_12		(0x3000)
+#define QSPI_QMR_BITS_13		(0x3400)
+#define QSPI_QMR_BITS_14		(0x3800)
+#define QSPI_QMR_BITS_15		(0x3C00)
+#define QSPI_QMR_BITS_16		(0x0000)
+#define QSPI_QMR_CPOL			(0x0200)
+#define QSPI_QMR_CPHA			(0x0100)
+#define QSPI_QMR_BAUD(x)		((x)&0x00FF)
+#define QSPI_QMR_BAUD_MASK		(0xFF00)
+
+/* DLYR */
+#define QSPI_QDLYR_SPE			(0x8000)
+#define QSPI_QDLYR_QCD(x)		(((x)&0x007F)<<8)
+#define QSPI_QDLYR_QCD_MASK		(0x80FF)
+#define QSPI_QDLYR_DTL(x)		((x)&0x00FF)
+#define QSPI_QDLYR_DTL_MASK		(0xFF00)
+
+/* WR */
+#define QSPI_QWR_HALT			(0x8000)
+#define QSPI_QWR_WREN			(0x4000)
+#define QSPI_QWR_WRTO			(0x2000)
+#define QSPI_QWR_CSIV			(0x1000)
+#define QSPI_QWR_ENDQP(x)		(((x)&0x000F)<<8)
+#define QSPI_QWR_ENDQP_MASK		(0xF0FF)
+#define QSPI_QWR_CPTQP(x)		(((x)&0x000F)<<4)
+#define QSPI_QWR_CPTQP_MASK		(0xFF0F)
+#define QSPI_QWR_NEWQP(x)		((x)&0x000F)
+#define QSPI_QWR_NEWQP_MASK		(0xFFF0)
+
+/* IR */
+#define QSPI_QIR_WCEFB			(0x8000)
+#define QSPI_QIR_ABRTB			(0x4000)
+#define QSPI_QIR_ABRTL			(0x1000)
+#define QSPI_QIR_WCEFE			(0x0800)
+#define QSPI_QIR_ABRTE			(0x0400)
+#define QSPI_QIR_SPIFE			(0x0100)
+#define QSPI_QIR_WCEF			(0x0008)
+#define QSPI_QIR_ABRT			(0x0004)
+#define QSPI_QIR_SPIF			(0x0001)
+
+/* AR */
+#define QSPI_QAR_ADDR(x)		((x)&0x003F)
+#define QSPI_QAR_ADDR_MASK		(0xFFC0)
+#define QSPI_QAR_TRANS			(0x0000)
+#define QSPI_QAR_RECV			(0x0010)
+#define QSPI_QAR_CMD			(0x0020)
+
+/* DR with RAM command word definitions */
+#define QSPI_QDR_CONT			(0x8000)
+#define QSPI_QDR_BITSE			(0x4000)
+#define QSPI_QDR_DT			(0x2000)
+#define QSPI_QDR_DSCK			(0x1000)
+#define QSPI_QDR_QSPI_CS3		(0x0800)
+#define QSPI_QDR_QSPI_CS2		(0x0400)
+#define QSPI_QDR_QSPI_CS1		(0x0200)
+#define QSPI_QDR_QSPI_CS0		(0x0100)
+
+#endif				/* __QSPI_H__ */
diff --git a/arch/m68k/include/asm/coldfire/rng.h b/arch/m68k/include/asm/coldfire/rng.h
new file mode 100644
index 0000000..88124e3
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/rng.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RNG Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __RNG_H__
+#define __RNG_H__
+
+/* Random Number Generator */
+typedef struct rng_ctrl {
+	u32 cr;			/* 0x00 Control */
+	u32 sr;			/* 0x04 Status */
+	u32 er;			/* 0x08 Entropy */
+	u32 out;		/* 0x0C Output FIFO */
+} rng_t;
+
+#define RNG_CR_SLM		(0x00000010)	/* Sleep mode - 5445x */
+#define RNG_CR_CI		(0x00000008)	/* Clear interrupt */
+#define RNG_CR_IM		(0x00000004)	/* Interrupt mask */
+#define RNG_CR_HA		(0x00000002)	/* High assurance */
+#define RNG_CR_GO		(0x00000001)	/* Go bit */
+
+#define RNG_SR_OFS(x)		(((x) & 0x000000FF) << 16)
+#define RNG_SR_OFS_MASK		(0xFF00FFFF)
+#define RNG_SR_OFL(x)		(((x) & 0x000000FF) << 8)
+#define RNG_SR_OFL_MASK		(0xFFFF00FF)
+#define RNG_SR_EI		(0x00000008)
+#define RNG_SR_FUF		(0x00000004)
+#define RNG_SR_LRS		(0x00000002)
+#define RNG_SR_SV		(0x00000001)
+
+#endif				/* __RNG_H__ */
diff --git a/arch/m68k/include/asm/coldfire/skha.h b/arch/m68k/include/asm/coldfire/skha.h
new file mode 100644
index 0000000..3b48dc9
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/skha.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Symmetric Key Hardware Accelerator Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __SKHA_H__
+#define __SKHA_H__
+
+typedef struct skha_ctrl {
+	u32 mr;			/* 0x00 Mode */
+	u32 cr;			/* 0x04 Control */
+	u32 cmr;		/* 0x08 Command */
+	u32 sr;			/* 0x0C Status */
+	u32 esr;		/* 0x10 Error Status */
+	u32 emr;		/* 0x14 Error Status Mask Register) */
+	u32 ksr;		/* 0x18 Key Size */
+	u32 dsr;		/* 0x1C Data Size */
+	u32 in;			/* 0x20 Input FIFO */
+	u32 out;		/* 0x24 Output FIFO */
+	u32 res1[2];		/* 0x28 - 0x2F */
+	u32 kdr1;		/* 0x30 Key Data 1  */
+	u32 kdr2;		/* 0x34 Key Data 2 */
+	u32 kdr3;		/* 0x38 Key Data 3 */
+	u32 kdr4;		/* 0x3C Key Data 4 */
+	u32 kdr5;		/* 0x40 Key Data 5 */
+	u32 kdr6;		/* 0x44 Key Data 6 */
+	u32 res2[10];		/* 0x48 - 0x6F */
+	u32 c1;			/* 0x70 Context 1 */
+	u32 c2;			/* 0x74 Context 2 */
+	u32 c3;			/* 0x78 Context 3 */
+	u32 c4;			/* 0x7C Context 4 */
+	u32 c5;			/* 0x80 Context 5 */
+	u32 c6;			/* 0x84 Context 6 */
+	u32 c7;			/* 0x88 Context 7 */
+	u32 c8;			/* 0x8C Context 8 */
+	u32 c9;			/* 0x90 Context 9 */
+	u32 c10;		/* 0x94 Context 10 */
+	u32 c11;		/* 0x98 Context 11 */
+	u32 c12;		/* 0x9C Context 12 - 5235, 5271, 5272 */
+} skha_t;
+
+#ifdef CONFIG_MCF532x
+#define	SKHA_MODE_CTRM(x)	(((x) & 0x0F) << 9)
+#define	SKHA_MODE_CTRM_MASK	(0xFFFFE1FF)
+#define	SKHA_MODE_DKP		(0x00000100)
+#else
+#define	SKHA_MODE_CTRM(x)	(((x) & 0x0F) << 8)
+#define	SKHA_MODE_CTRM_MASK	(0xFFFFF0FF)
+#define	SKHA_MODE_DKP		(0x00000080)
+#endif
+#define	SKHA_MODE_CM(x)		(((x) & 0x03) << 3)
+#define	SKHA_MODE_CM_MASK	(0xFFFFFFE7)
+#define	SKHA_MODE_DIR		(0x00000004)
+#define	SKHA_MODE_ALG(x)	((x) & 0x03)
+#define	SKHA_MODE_ALG_MASK	(0xFFFFFFFC)
+
+#define SHKA_CR_ODMAL(x)	(((x) & 0x3F) << 24)
+#define SHKA_CR_ODMAL_MASK	(0xC0FFFFFF)
+#define SHKA_CR_IDMAL(x)	(((x) & 0x3F) << 16)
+#define SHKA_CR_IDMAL_MASK	(0xFFC0FFFF)
+#define SHKA_CR_END		(0x00000008)
+#define SHKA_CR_ODMA		(0x00000004)
+#define SHKA_CR_IDMA		(0x00000002)
+#define	SKHA_CR_IE		(0x00000001)
+
+#define	SKHA_CMR_GO		(0x00000008)
+#define	SKHA_CMR_CI		(0x00000004)
+#define	SKHA_CMR_RI		(0x00000002)
+#define	SKHA_CMR_SWR		(0x00000001)
+
+#define SKHA_SR_OFL(x)		(((x) & 0xFF) << 24)
+#define SKHA_SR_OFL_MASK	(0x00FFFFFF)
+#define SKHA_SR_IFL(x)		(((x) & 0xFF) << 16)
+#define SKHA_SR_IFL_MASK	(0xFF00FFFF)
+#define SKHA_SR_AESES(x)	(((x) & 0x1F) << 11)
+#define SKHA_SR_AESES_MASK	(0xFFFF07FF)
+#define SKHA_SR_DESES(x)	(((x) & 0x7) << 8)
+#define SKHA_SR_DESES_MASK	(0xFFFFF8FF)
+#define SKHA_SR_BUSY		(0x00000010)
+#define SKHA_SR_RD		(0x00000008)
+#define SKHA_SR_ERR		(0x00000004)
+#define SKHA_SR_DONE		(0x00000002)
+#define SKHA_SR_INT		(0x00000001)
+
+#define SHKA_ESE_DRL		(0x00000800)
+#define	SKHA_ESR_KRE		(0x00000400)
+#define	SKHA_ESR_KPE		(0x00000200)
+#define	SKHA_ESR_ERE		(0x00000100)
+#define	SKHA_ESR_RMDP		(0x00000080)
+#define	SKHA_ESR_KSE		(0x00000040)
+#define	SKHA_ESR_DSE		(0x00000020)
+#define	SKHA_ESR_IME		(0x00000010)
+#define	SKHA_ESR_NEOF		(0x00000008)
+#define	SKHA_ESR_NEIF		(0x00000004)
+#define	SKHA_ESR_OFU		(0x00000002)
+#define	SKHA_ESR_IFO		(0x00000001)
+
+#define	SKHA_KSR_SZ(x)		((x) & 0x3F)
+#define	SKHA_KSR_SZ_MASK	(0xFFFFFFC0)
+
+#endif				/* __SKHA_H__ */
diff --git a/arch/m68k/include/asm/coldfire/ssi.h b/arch/m68k/include/asm/coldfire/ssi.h
new file mode 100644
index 0000000..900d6bd
--- /dev/null
+++ b/arch/m68k/include/asm/coldfire/ssi.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * SSI Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __SSI_H__
+#define __SSI_H__
+
+typedef struct ssi {
+	u32 tx0;
+	u32 tx1;
+	u32 rx0;
+	u32 rx1;
+	u32 cr;
+	u32 isr;
+	u32 ier;
+	u32 tcr;
+	u32 rcr;
+	u32 ccr;
+	u8 resv0[0x4];
+	u32 fcsr;
+	u8 resv1[0x8];
+	u32 acr;
+	u32 acadd;
+	u32 acdat;
+	u32 atag;
+	u32 tmask;
+	u32 rmask;
+} ssi_t;
+
+#define SSI_CR_CIS			(0x00000200)
+#define SSI_CR_TCH			(0x00000100)
+#define SSI_CR_MCE			(0x00000080)
+#define SSI_CR_I2S_MASK			(0xFFFFFF9F)
+#define SSI_CR_I2S_SLAVE		(0x00000040)
+#define SSI_CR_I2S_MASTER		(0x00000020)
+#define SSI_CR_I2S_NORMAL		(0x00000000)
+#define SSI_CR_SYN			(0x00000010)
+#define SSI_CR_NET			(0x00000008)
+#define SSI_CR_RE			(0x00000004)
+#define SSI_CR_TE			(0x00000002)
+#define SSI_CR_SSI_EN			(0x00000001)
+
+#define SSI_ISR_CMDAU			(0x00040000)
+#define SSI_ISR_CMDDU			(0x00020000)
+#define SSI_ISR_RXT			(0x00010000)
+#define SSI_ISR_RDR1			(0x00008000)
+#define SSI_ISR_RDR0			(0x00004000)
+#define SSI_ISR_TDE1			(0x00002000)
+#define SSI_ISR_TDE0			(0x00001000)
+#define SSI_ISR_ROE1			(0x00000800)
+#define SSI_ISR_ROE0			(0x00000400)
+#define SSI_ISR_TUE1			(0x00000200)
+#define SSI_ISR_TUE0			(0x00000100)
+#define SSI_ISR_TFS			(0x00000080)
+#define SSI_ISR_RFS			(0x00000040)
+#define SSI_ISR_TLS			(0x00000020)
+#define SSI_ISR_RLS			(0x00000010)
+#define SSI_ISR_RFF1			(0x00000008)
+#define SSI_ISR_RFF0			(0x00000004)
+#define SSI_ISR_TFE1			(0x00000002)
+#define SSI_ISR_TFE0			(0x00000001)
+
+#define SSI_IER_RDMAE			(0x00400000)
+#define SSI_IER_RIE			(0x00200000)
+#define SSI_IER_TDMAE			(0x00100000)
+#define SSI_IER_TIE			(0x00080000)
+#define SSI_IER_CMDAU			(0x00040000)
+#define SSI_IER_CMDU			(0x00020000)
+#define SSI_IER_RXT			(0x00010000)
+#define SSI_IER_RDR1			(0x00008000)
+#define SSI_IER_RDR0			(0x00004000)
+#define SSI_IER_TDE1			(0x00002000)
+#define SSI_IER_TDE0			(0x00001000)
+#define SSI_IER_ROE1			(0x00000800)
+#define SSI_IER_ROE0			(0x00000400)
+#define SSI_IER_TUE1			(0x00000200)
+#define SSI_IER_TUE0			(0x00000100)
+#define SSI_IER_TFS			(0x00000080)
+#define SSI_IER_RFS			(0x00000040)
+#define SSI_IER_TLS			(0x00000020)
+#define SSI_IER_RLS			(0x00000010)
+#define SSI_IER_RFF1			(0x00000008)
+#define SSI_IER_RFF0			(0x00000004)
+#define SSI_IER_TFE1			(0x00000002)
+#define SSI_IER_TFE0			(0x00000001)
+
+#define SSI_TCR_TXBIT0			(0x00000200)
+#define SSI_TCR_TFEN1			(0x00000100)
+#define SSI_TCR_TFEN0			(0x00000080)
+#define SSI_TCR_TFDIR			(0x00000040)
+#define SSI_TCR_TXDIR			(0x00000020)
+#define SSI_TCR_TSHFD			(0x00000010)
+#define SSI_TCR_TSCKP			(0x00000008)
+#define SSI_TCR_TFSI			(0x00000004)
+#define SSI_TCR_TFSL			(0x00000002)
+#define SSI_TCR_TEFS			(0x00000001)
+
+#define SSI_RCR_RXEXT			(0x00000400)
+#define SSI_RCR_RXBIT0			(0x00000200)
+#define SSI_RCR_RFEN1			(0x00000100)
+#define SSI_RCR_RFEN0			(0x00000080)
+#define SSI_RCR_RSHFD			(0x00000010)
+#define SSI_RCR_RSCKP			(0x00000008)
+#define SSI_RCR_RFSI			(0x00000004)
+#define SSI_RCR_RFSL			(0x00000002)
+#define SSI_RCR_REFS			(0x00000001)
+
+#define SSI_CCR_DIV2			(0x00040000)
+#define SSI_CCR_PSR			(0x00020000)
+#define SSI_CCR_WL(x)			(((x) & 0x0F) << 13)
+#define SSI_CCR_WL_MASK			(0xFFFE1FFF)
+#define SSI_CCR_DC(x)			(((x)& 0x1F) << 8)
+#define SSI_CCR_DC_MASK			(0xFFFFE0FF)
+#define SSI_CCR_PM(x)			((x) & 0xFF)
+#define SSI_CCR_PM_MASK			(0xFFFFFF00)
+
+#define SSI_FCSR_RFCNT1(x)		(((x) & 0x0F) << 28)
+#define SSI_FCSR_RFCNT1_MASK		(0x0FFFFFFF)
+#define SSI_FCSR_TFCNT1(x)		(((x) & 0x0F) << 24)
+#define SSI_FCSR_TFCNT1_MASK		(0xF0FFFFFF)
+#define SSI_FCSR_RFWM1(x)		(((x) & 0x0F) << 20)
+#define SSI_FCSR_RFWM1_MASK		(0xFF0FFFFF)
+#define SSI_FCSR_TFWM1(x)		(((x) & 0x0F) << 16)
+#define SSI_FCSR_TFWM1_MASK		(0xFFF0FFFF)
+#define SSI_FCSR_RFCNT0(x)		(((x) & 0x0F) << 12)
+#define SSI_FCSR_RFCNT0_MASK		(0xFFFF0FFF)
+#define SSI_FCSR_TFCNT0(x)		(((x) & 0x0F) << 8)
+#define SSI_FCSR_TFCNT0_MASK		(0xFFFFF0FF)
+#define SSI_FCSR_RFWM0(x)		(((x) & 0x0F) << 4)
+#define SSI_FCSR_RFWM0_MASK		(0xFFFFFF0F)
+#define SSI_FCSR_TFWM0(x)		((x) & 0x0F)
+#define SSI_FCSR_TFWM0_MASK		(0xFFFFFFF0)
+
+#define SSI_ACR_FRDIV(x)		(((x) & 0x3F) << 5)
+#define SSI_ACR_FRDIV_MASK		(0xFFFFF81F)
+#define SSI_ACR_WR			(0x00000010)
+#define SSI_ACR_RD			(0x00000008)
+#define SSI_ACR_TIF			(0x00000004)
+#define SSI_ACR_FV			(0x00000002)
+#define SSI_ACR_AC97EN			(0x00000001)
+
+#define SSI_ACADD_SSI_ACADD(x)		((x) & 0x0007FFFF)
+
+#define SSI_ACDAT_SSI_ACDAT(x)		((x) & 0x0007FFFF)
+
+#define SSI_ATAG_DDI_ATAG(x)		((x) & 0x0000FFFF)
+
+#endif					/* __SSI_H__ */
diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h
new file mode 100644
index 0000000..c7363c0
--- /dev/null
+++ b/arch/m68k/include/asm/config.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_NEEDS_MANUAL_RELOC
+
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#endif
diff --git a/arch/m68k/include/asm/fec.h b/arch/m68k/include/asm/fec.h
new file mode 100644
index 0000000..5742829
--- /dev/null
+++ b/arch/m68k/include/asm/fec.h
@@ -0,0 +1,350 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * fec.h -- Fast Ethernet Controller definitions
+ *
+ * Some definitions copied from commproc.h for MPC8xx:
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * Add FEC Structure and definitions
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef	fec_h
+#define	fec_h
+
+#include <phy.h>
+
+/* Buffer descriptors used FEC.
+*/
+typedef struct cpm_buf_desc {
+	ushort cbd_sc;		/* Status and Control */
+	ushort cbd_datlen;	/* Data length in buffer */
+	uint cbd_bufaddr;	/* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY		((ushort)0x8000)	/* Receive is empty */
+#define BD_SC_READY		((ushort)0x8000)	/* Transmit is ready */
+#define BD_SC_WRAP		((ushort)0x2000)	/* Last buffer descriptor */
+#define BD_SC_INTRPT		((ushort)0x1000)	/* Interrupt on change */
+#define BD_SC_LAST		((ushort)0x0800)	/* Last buffer in frame */
+#define BD_SC_TC		((ushort)0x0400)	/* Transmit CRC */
+#define BD_SC_CM		((ushort)0x0200)	/* Continous mode */
+#define BD_SC_ID		((ushort)0x0100)	/* Rec'd too many idles */
+#define BD_SC_P			((ushort)0x0100)	/* xmt preamble */
+#define BD_SC_BR		((ushort)0x0020)	/* Break received */
+#define BD_SC_FR		((ushort)0x0010)	/* Framing error */
+#define BD_SC_PR		((ushort)0x0008)	/* Parity error */
+#define BD_SC_OV		((ushort)0x0002)	/* Overrun */
+#define BD_SC_CD		((ushort)0x0001)	/* Carrier Detect lost */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_RO1		((ushort)0x4000)
+#define BD_ENET_RX_WRAP		((ushort)0x2000)
+#define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_RO2		BD_ENET_RX_INTR
+#define BD_ENET_RX_LAST		((ushort)0x0800)
+#define BD_ENET_RX_FIRST	((ushort)0x0400)
+#define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_BC		((ushort)0x0080)
+#define BD_ENET_RX_MC		((ushort)0x0040)
+#define BD_ENET_RX_LG		((ushort)0x0020)
+#define BD_ENET_RX_NO		((ushort)0x0010)
+#define BD_ENET_RX_SH		((ushort)0x0008)
+#define BD_ENET_RX_CR		((ushort)0x0004)
+#define BD_ENET_RX_OV		((ushort)0x0002)
+#define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_TR		BD_ENET_RX_CL
+#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY	((ushort)0x8000)
+#define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_TO1		BD_ENET_TX_PAD
+#define BD_ENET_TX_WRAP		((ushort)0x2000)
+#define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_TO2		BD_ENET_TX_INTR_
+#define BD_ENET_TX_LAST		((ushort)0x0800)
+#define BD_ENET_TX_TC		((ushort)0x0400)
+#define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_ABC		BD_ENET_TX_DEF
+#define BD_ENET_TX_HB		((ushort)0x0100)
+#define BD_ENET_TX_LC		((ushort)0x0080)
+#define BD_ENET_TX_RL		((ushort)0x0040)
+#define BD_ENET_TX_RCMASK	((ushort)0x003c)
+#define BD_ENET_TX_UN		((ushort)0x0002)
+#define BD_ENET_TX_CSL		((ushort)0x0001)
+#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
+
+/*********************************************************************
+* Fast Ethernet Controller (FEC)
+*********************************************************************/
+/* FEC private information */
+struct fec_info_s {
+	int index;
+	u32 iobase;
+	u32 pinmux;
+	u32 miibase;
+	int phy_addr;
+	int dup_spd;
+	char *phy_name;
+	int phyname_init;
+	cbd_t *rxbd;		/* Rx BD */
+	cbd_t *txbd;		/* Tx BD */
+	uint rxIdx;
+	uint txIdx;
+	char *txbuf;
+	int initialized;
+	struct fec_info_s *next;
+};
+
+#ifdef CONFIG_MCFFEC
+/* Register read/write struct */
+typedef struct fec {
+#ifdef CONFIG_M5272
+	u32 ecr;		/* 0x00 */
+	u32 eir;		/* 0x04 */
+	u32 eimr;		/* 0x08 */
+	u32 ivsr;		/* 0x0C */
+	u32 rdar;		/* 0x10 */
+	u32 tdar;		/* 0x14 */
+	u8 resv1[0x28];		/* 0x18 */
+	u32 mmfr;		/* 0x40 */
+	u32 mscr;		/* 0x44 */
+	u8 resv2[0x44];		/* 0x48 */
+	u32 frbr;		/* 0x8C */
+	u32 frsr;		/* 0x90 */
+	u8 resv3[0x10];		/* 0x94 */
+	u32 tfwr;		/* 0xA4 */
+	u32 res4;		/* 0xA8 */
+	u32 tfsr;		/* 0xAC */
+	u8 resv4[0x50];		/* 0xB0 */
+	u32 opd;		/* 0x100 - dummy  */
+	u32 rcr;		/* 0x104 */
+	u32 mibc;		/* 0x108 */
+	u8 resv5[0x38];		/* 0x10C */
+	u32 tcr;		/* 0x144 */
+	u8 resv6[0x270];	/* 0x148 */
+	u32 iaur;		/* 0x3B8 - dummy */
+	u32 ialr;		/* 0x3BC - dummy  */
+	u32 palr;		/* 0x3C0 */
+	u32 paur;		/* 0x3C4 */
+	u32 gaur;		/* 0x3C8 */
+	u32 galr;		/* 0x3CC */
+	u32 erdsr;		/* 0x3D0 */
+	u32 etdsr;		/* 0x3D4 */
+	u32 emrbr;		/* 0x3D8 */
+	u8 resv12[0x74];	/* 0x18C */
+#else
+	u8 resv0[0x4];
+	u32 eir;
+	u32 eimr;
+	u8 resv1[0x4];
+	u32 rdar;
+	u32 tdar;
+	u8 resv2[0xC];
+	u32 ecr;
+	u8 resv3[0x18];
+	u32 mmfr;
+	u32 mscr;
+	u8 resv4[0x1C];
+	u32 mibc;
+	u8 resv5[0x1C];
+	u32 rcr;
+	u8 resv6[0x3C];
+	u32 tcr;
+	u8 resv7[0x1C];
+	u32 palr;
+	u32 paur;
+	u32 opd;
+	u8 resv8[0x28];
+	u32 iaur;
+	u32 ialr;
+	u32 gaur;
+	u32 galr;
+	u8 resv9[0x1C];
+	u32 tfwr;
+	u8 resv10[0x4];
+	u32 frbr;
+	u32 frsr;
+	u8 resv11[0x2C];
+	u32 erdsr;
+	u32 etdsr;
+	u32 emrbr;
+	u8 resv12[0x74];
+#endif
+
+	u32 rmon_t_drop;
+	u32 rmon_t_packets;
+	u32 rmon_t_bc_pkt;
+	u32 rmon_t_mc_pkt;
+	u32 rmon_t_crc_align;
+	u32 rmon_t_undersize;
+	u32 rmon_t_oversize;
+	u32 rmon_t_frag;
+	u32 rmon_t_jab;
+	u32 rmon_t_col;
+	u32 rmon_t_p64;
+	u32 rmon_t_p65to127;
+	u32 rmon_t_p128to255;
+	u32 rmon_t_p256to511;
+	u32 rmon_t_p512to1023;
+	u32 rmon_t_p1024to2047;
+	u32 rmon_t_p_gte2048;
+	u32 rmon_t_octets;
+
+	u32 ieee_t_drop;
+	u32 ieee_t_frame_ok;
+	u32 ieee_t_1col;
+	u32 ieee_t_mcol;
+	u32 ieee_t_def;
+	u32 ieee_t_lcol;
+	u32 ieee_t_excol;
+	u32 ieee_t_macerr;
+	u32 ieee_t_cserr;
+	u32 ieee_t_sqe;
+	u32 ieee_t_fdxfc;
+	u32 ieee_t_octets_ok;
+	u8 resv13[0x8];
+
+	u32 rmon_r_drop;
+	u32 rmon_r_packets;
+	u32 rmon_r_bc_pkt;
+	u32 rmon_r_mc_pkt;
+	u32 rmon_r_crc_align;
+	u32 rmon_r_undersize;
+	u32 rmon_r_oversize;
+	u32 rmon_r_frag;
+	u32 rmon_r_jab;
+	u32 rmon_r_resvd_0;
+	u32 rmon_r_p64;
+	u32 rmon_r_p65to127;
+	u32 rmon_r_p128to255;
+	u32 rmon_r_p256to511;
+	u32 rmon_r_p512to1023;
+	u32 rmon_r_p1024to2047;
+	u32 rmon_r_p_gte2048;
+	u32 rmon_r_octets;
+
+	u32 ieee_r_drop;
+	u32 ieee_r_frame_ok;
+	u32 ieee_r_crc;
+	u32 ieee_r_align;
+	u32 ieee_r_macerr;
+	u32 ieee_r_fdxfc;
+	u32 ieee_r_octets_ok;
+} fec_t;
+#endif				/* CONFIG_MCFFEC */
+
+/*********************************************************************
+* Fast Ethernet Controller (FEC)
+*********************************************************************/
+/* Bit definitions and macros for FEC_EIR */
+#define FEC_EIR_CLEAR_ALL		(0xFFF80000)
+#define FEC_EIR_HBERR			(0x80000000)
+#define FEC_EIR_BABR			(0x40000000)
+#define FEC_EIR_BABT			(0x20000000)
+#define FEC_EIR_GRA			(0x10000000)
+#define FEC_EIR_TXF			(0x08000000)
+#define FEC_EIR_TXB			(0x04000000)
+#define FEC_EIR_RXF			(0x02000000)
+#define FEC_EIR_RXB			(0x01000000)
+#define FEC_EIR_MII			(0x00800000)
+#define FEC_EIR_EBERR			(0x00400000)
+#define FEC_EIR_LC			(0x00200000)
+#define FEC_EIR_RL			(0x00100000)
+#define FEC_EIR_UN			(0x00080000)
+
+/* Bit definitions and macros for FEC_RDAR */
+#define FEC_RDAR_R_DES_ACTIVE		(0x01000000)
+
+/* Bit definitions and macros for FEC_TDAR */
+#define FEC_TDAR_X_DES_ACTIVE		(0x01000000)
+
+/* Bit definitions and macros for FEC_ECR */
+#define FEC_ECR_ETHER_EN		(0x00000002)
+#define FEC_ECR_RESET			(0x00000001)
+
+/* Bit definitions and macros for FEC_MMFR */
+#define FEC_MMFR_DATA(x)		(((x)&0xFFFF))
+#define FEC_MMFR_ST(x)			(((x)&0x03)<<30)
+#define FEC_MMFR_ST_01			(0x40000000)
+#define FEC_MMFR_OP_RD			(0x20000000)
+#define FEC_MMFR_OP_WR			(0x10000000)
+#define FEC_MMFR_PA(x)			(((x)&0x1F)<<23)
+#define FEC_MMFR_RA(x)			(((x)&0x1F)<<18)
+#define FEC_MMFR_TA(x)			(((x)&0x03)<<16)
+#define FEC_MMFR_TA_10			(0x00020000)
+
+/* Bit definitions and macros for FEC_MSCR */
+#define FEC_MSCR_DIS_PREAMBLE		(0x00000080)
+#define FEC_MSCR_MII_SPEED(x)		(((x)&0x3F)<<1)
+
+/* Bit definitions and macros for FEC_MIBC */
+#define FEC_MIBC_MIB_DISABLE		(0x80000000)
+#define FEC_MIBC_MIB_IDLE		(0x40000000)
+
+/* Bit definitions and macros for FEC_RCR */
+#define FEC_RCR_MAX_FL(x)		(((x)&0x7FF)<<16)
+#define FEC_RCR_FCE			(0x00000020)
+#define FEC_RCR_BC_REJ			(0x00000010)
+#define FEC_RCR_PROM			(0x00000008)
+#define FEC_RCR_MII_MODE		(0x00000004)
+#define FEC_RCR_DRT			(0x00000002)
+#define FEC_RCR_LOOP			(0x00000001)
+
+/* Bit definitions and macros for FEC_TCR */
+#define FEC_TCR_RFC_PAUSE		(0x00000010)
+#define FEC_TCR_TFC_PAUSE		(0x00000008)
+#define FEC_TCR_FDEN			(0x00000004)
+#define FEC_TCR_HBC			(0x00000002)
+#define FEC_TCR_GTS			(0x00000001)
+
+/* Bit definitions and macros for FEC_PAUR */
+#define FEC_PAUR_PADDR2(x)		(((x)&0xFFFF)<<16)
+#define FEC_PAUR_TYPE(x)		((x)&0xFFFF)
+
+/* Bit definitions and macros for FEC_OPD */
+#define FEC_OPD_PAUSE_DUR(x)		(((x)&0x0000FFFF)<<0)
+#define FEC_OPD_OPCODE(x)		(((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for FEC_TFWR */
+#define FEC_TFWR_X_WMRK(x)		((x)&0x03)
+#define FEC_TFWR_X_WMRK_64		(0x01)
+#define FEC_TFWR_X_WMRK_128		(0x02)
+#define FEC_TFWR_X_WMRK_192		(0x03)
+
+/* Bit definitions and macros for FEC_FRBR */
+#define FEC_FRBR_R_BOUND(x)		(((x)&0xFF)<<2)
+
+/* Bit definitions and macros for FEC_FRSR */
+#define FEC_FRSR_R_FSTART(x)		(((x)&0xFF)<<2)
+
+/* Bit definitions and macros for FEC_ERDSR */
+#define FEC_ERDSR_R_DES_START(x)	(((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for FEC_ETDSR */
+#define FEC_ETDSR_X_DES_START(x)	(((x)&0x3FFFFFFF)<<2)
+
+/* Bit definitions and macros for FEC_EMRBR */
+#define FEC_EMRBR_R_BUF_SIZE(x)		(((x)&0x7F)<<4)
+
+#define	FEC_RESET_DELAY			100
+#define FEC_RX_TOUT			100
+
+int fecpin_setclear(struct eth_device *dev, int setclear);
+
+#ifdef CONFIG_SYS_DISCOVER_PHY
+void __mii_init(void);
+uint mii_send(uint mii_cmd);
+int mii_discover_phy(struct eth_device *dev);
+int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
+int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
+			u16 value);
+#endif
+
+#endif				/* fec_h */
diff --git a/arch/m68k/include/asm/fsl_i2c.h b/arch/m68k/include/asm/fsl_i2c.h
new file mode 100644
index 0000000..9c54fde
--- /dev/null
+++ b/arch/m68k/include/asm/fsl_i2c.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Freescale I2C Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
+ * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
+ * and Jeff Brown.
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
+ */
+
+#ifndef _ASM_FSL_I2C_H_
+#define _ASM_FSL_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct fsl_i2c_base {
+
+	u8 adr;		/* I2C slave address */
+	u8 res0[3];
+#define I2C_ADR		0xFE
+#define I2C_ADR_SHIFT	1
+#define I2C_ADR_RES	~(I2C_ADR)
+
+	u8 fdr;		/* I2C frequency divider register */
+	u8 res1[3];
+#define IC2_FDR		0x3F
+#define IC2_FDR_SHIFT	0
+#define IC2_FDR_RES	~(IC2_FDR)
+
+	u8 cr;		/* I2C control redister	*/
+	u8 res2[3];
+#define I2C_CR_MEN	0x80
+#define I2C_CR_MIEN	0x40
+#define I2C_CR_MSTA	0x20
+#define I2C_CR_MTX	0x10
+#define I2C_CR_TXAK	0x08
+#define I2C_CR_RSTA	0x04
+#define I2C_CR_BCST	0x01
+
+	u8 sr;		/* I2C status register */
+	u8 res3[3];
+#define I2C_SR_MCF	0x80
+#define I2C_SR_MAAS	0x40
+#define I2C_SR_MBB	0x20
+#define I2C_SR_MAL	0x10
+#define I2C_SR_BCSTM	0x08
+#define I2C_SR_SRW	0x04
+#define I2C_SR_MIF	0x02
+#define I2C_SR_RXAK	0x01
+
+	u8 dr;		/* I2C data register */
+	u8 res4[3];
+#define I2C_DR		0xFF
+#define I2C_DR_SHIFT	0
+#define I2C_DR_RES	~(I2C_DR)
+} fsl_i2c_t;
+
+#endif	/* _ASM_I2C_H_ */
diff --git a/arch/m68k/include/asm/fsl_mcdmafec.h b/arch/m68k/include/asm/fsl_mcdmafec.h
new file mode 100644
index 0000000..c283ad4
--- /dev/null
+++ b/arch/m68k/include/asm/fsl_mcdmafec.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef fsl_mcdmafec_h
+#define fsl_mcdmafec_h
+
+/* Re-use of the definitions */
+#include <asm/fec.h>
+
+typedef struct fecdma {
+	u32 rsvd0;		/* 0x000 */
+	u32 eir;		/* 0x004 */
+	u32 eimr;		/* 0x008 */
+	u32 rsvd1[6];		/* 0x00C - 0x023 */
+	u32 ecr;		/* 0x024 */
+	u32 rsvd2[6];		/* 0x028 - 0x03F */
+	u32 mmfr;		/* 0x040 */
+	u32 mscr;		/* 0x044 */
+	u32 rsvd3[7];		/* 0x048 - 0x063 */
+	u32 mibc;		/* 0x064 */
+	u32 rsvd4[7];		/* 0x068 - 0x083 */
+	u32 rcr;		/* 0x084 */
+	u32 rhr;		/* 0x088 */
+	u32 rsvd5[14];		/* 0x08C - 0x0C3 */
+	u32 tcr;		/* 0x0C4 */
+	u32 rsvd6[7];		/* 0x0C8 - 0x0E3 */
+	u32 palr;		/* 0x0E4 */
+	u32 paur;		/* 0x0E8 */
+	u32 opd;		/* 0x0EC */
+	u32 rsvd7[10];		/* 0x0F0 - 0x117 */
+	u32 iaur;		/* 0x118 */
+	u32 ialr;		/* 0x11C */
+	u32 gaur;		/* 0x120 */
+	u32 galr;		/* 0x124 */
+	u32 rsvd8[7];		/* 0x128 - 0x143 */
+	u32 tfwr;		/* 0x144 */
+	u32 rsvd9[14];		/* 0x148 - 0x17F */
+	u32 fmc;		/* 0x180 */
+	u32 rfdr;		/* 0x184 */
+	u32 rfsr;		/* 0x188 */
+	u32 rfcr;		/* 0x18C */
+	u32 rlrfp;		/* 0x190 */
+	u32 rlwfp;		/* 0x194 */
+	u32 rfar;		/* 0x198 */
+	u32 rfrp;		/* 0x19C */
+	u32 rfwp;		/* 0x1A0 */
+	u32 tfdr;		/* 0x1A4 */
+	u32 tfsr;		/* 0x1A8 */
+	u32 tfcr;		/* 0x1AC */
+	u32 tlrfp;		/* 0x1B0 */
+	u32 tlwfp;		/* 0x1B4 */
+	u32 tfar;		/* 0x1B8 */
+	u32 tfrp;		/* 0x1BC */
+	u32 tfwp;		/* 0x1C0 */
+	u32 frst;		/* 0x1C4 */
+	u32 ctcwr;		/* 0x1C8 */
+} fecdma_t;
+
+struct fec_info_dma {
+	int index;
+	u32 iobase;
+	u32 pinmux;
+	u32 miibase;
+	int phy_addr;
+	int dup_spd;
+	char *phy_name;
+	int phyname_init;
+	cbd_t *rxbd;		/* Rx BD */
+	cbd_t *txbd;		/* Tx BD */
+	uint rxIdx;
+	uint txIdx;
+	char *txbuf;
+	int initialized;
+	struct fec_info_dma *next;
+
+	u16 rxTask;		/* DMA receive Task Number */
+	u16 txTask;		/* DMA Transmit Task Number */
+	u16 rxPri;		/* DMA Receive Priority */
+	u16 txPri;		/* DMA Transmit Priority */
+	u16 rxInit;		/* DMA Receive Initiator */
+	u16 txInit;		/* DMA Transmit Initiator */
+	u16 usedTbdIdx;		/* next transmit BD to clean */
+	u16 cleanTbdNum;	/* the number of available transmit BDs */
+};
+
+/* Bit definitions and macros for IEVENT */
+#define FEC_EIR_TXERR		(0x00040000)
+#define FEC_EIR_RXERR		(0x00020000)
+#undef FEC_EIR_CLEAR_ALL
+#define FEC_EIR_CLEAR_ALL	(0xFFFE0000)
+
+/* Bit definitions and macros for R_HASH */
+#define FEC_RHASH_FCE_DC	(0x80000000)
+#define FEC_RHASH_MULTCAST	(0x40000000)
+#define FEC_RHASH_HASH(x)	(((x)&0x0000003F)<<24)
+
+/* Bit definitions and macros for FEC_TFWR */
+#undef FEC_TFWR_X_WMRK
+#undef FEC_TFWR_X_WMRK_64
+#undef FEC_TFWR_X_WMRK_128
+#undef FEC_TFWR_X_WMRK_192
+
+#define FEC_TFWR_X_WMRK(x)	((x)&0x0F)
+#define FEC_TFWR_X_WMRK_64	(0x00)
+#define FEC_TFWR_X_WMRK_128	(0x01)
+#define FEC_TFWR_X_WMRK_192	(0x02)
+#define FEC_TFWR_X_WMRK_256	(0x03)
+#define FEC_TFWR_X_WMRK_320	(0x04)
+#define FEC_TFWR_X_WMRK_384	(0x05)
+#define FEC_TFWR_X_WMRK_448	(0x06)
+#define FEC_TFWR_X_WMRK_512	(0x07)
+#define FEC_TFWR_X_WMRK_576	(0x08)
+#define FEC_TFWR_X_WMRK_640	(0x09)
+#define FEC_TFWR_X_WMRK_704	(0x0A)
+#define FEC_TFWR_X_WMRK_768	(0x0B)
+#define FEC_TFWR_X_WMRK_832	(0x0C)
+#define FEC_TFWR_X_WMRK_896	(0x0D)
+#define FEC_TFWR_X_WMRK_960	(0x0E)
+#define FEC_TFWR_X_WMRK_1024	(0x0F)
+
+/* FIFO definitions */
+/* Bit definitions and macros for FSTAT */
+#define FIFO_STAT_IP		(0x80000000)
+#define FIFO_STAT_FRAME(x)	(((x)&0x0000000F)<<24)
+#define FIFO_STAT_FAE		(0x00800000)
+#define FIFO_STAT_RXW		(0x00400000)
+#define FIFO_STAT_UF		(0x00200000)
+#define FIFO_STAT_OF		(0x00100000)
+#define FIFO_STAT_FR		(0x00080000)
+#define FIFO_STAT_FULL		(0x00040000)
+#define FIFO_STAT_ALARM		(0x00020000)
+#define FIFO_STAT_EMPTY		(0x00010000)
+
+/* Bit definitions and macros for FCTRL */
+#define FIFO_CTRL_WCTL		(0x40000000)
+#define FIFO_CTRL_WFR		(0x20000000)
+#define FIFO_CTRL_FRAME		(0x08000000)
+#define FIFO_CTRL_GR(x)		(((x)&0x00000007)<<24)
+#define FIFO_CTRL_IPMASK	(0x00800000)
+#define FIFO_CTRL_FAEMASK	(0x00400000)
+#define FIFO_CTRL_RXWMASK	(0x00200000)
+#define FIFO_CTRL_UFMASK	(0x00100000)
+#define FIFO_CTRL_OFMASK	(0x00080000)
+
+#endif				/* fsl_mcdmafec_h */
diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h
new file mode 100644
index 0000000..188055e
--- /dev/null
+++ b/arch/m68k/include/asm/global_data.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002 - 2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+/* Architecture-specific global data */
+struct arch_global_data {
+#ifdef CONFIG_SYS_I2C_FSL
+	unsigned long	i2c1_clk;
+	unsigned long	i2c2_clk;
+#endif
+#ifdef CONFIG_EXTRA_CLOCK
+	unsigned long inp_clk;
+	unsigned long vco_clk;
+	unsigned long flb_clk;
+#endif
+#ifdef CONFIG_MCF5441x
+	unsigned long sdhc_clk;
+#endif
+};
+
+#include <asm-generic/global_data.h>
+
+#if 0
+extern gd_t *global_data;
+#define DECLARE_GLOBAL_DATA_PTR     gd_t *gd = global_data
+#else
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("d7")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
new file mode 100644
index 0000000..80fa257
--- /dev/null
+++ b/arch/m68k/include/asm/immap.h
@@ -0,0 +1,504 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ColdFire Internal Memory Map and Defines
+ *
+ * Copyright 2004-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __IMMAP_H
+#define __IMMAP_H
+
+#if defined(CONFIG_MCF520x)
+#include <asm/immap_520x.h>
+#include <asm/m520x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+#endif				/* CONFIG_M520x */
+
+#ifdef CONFIG_M52277
+#include <asm/immap_5227x.h>
+#include <asm/m5227x.h>
+
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+
+#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
+
+#ifdef CONFIG_LCD
+#define	CONFIG_SYS_LCD_BASE		(MMAP_LCD)
+#endif
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+#endif				/* CONFIG_M52277 */
+
+#ifdef CONFIG_M5235
+#include <asm/immap_5235.h>
+#include <asm/m5235.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+#endif				/* CONFIG_M5235 */
+
+#ifdef CONFIG_M5249
+#include <asm/immap_5249.h>
+#include <asm/m5249.h>
+
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS		(64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
+#define CONFIG_SYS_TMRINTR_NO		(31)
+#define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
+#endif
+#endif				/* CONFIG_M5249 */
+
+#ifdef CONFIG_M5253
+#include <asm/immap_5253.h>
+#include <asm/m5249.h>
+#include <asm/m5253.h>
+
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS		(64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
+#define CONFIG_SYS_TMRINTR_NO		(27)
+#define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
+#endif
+#endif				/* CONFIG_M5253 */
+
+#ifdef CONFIG_M5271
+#include <asm/immap_5271.h>
+#include <asm/m5271.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E) /* Interrupt level 3, priority 6 */
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+#endif				/* CONFIG_M5271 */
+
+#ifdef CONFIG_M5272
+#include <asm/immap_5272.h>
+#include <asm/m5272.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS		(64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_TMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_TMR3)
+#define CONFIG_SYS_TMRPND_REG		(((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
+#define CONFIG_SYS_TMRINTR_NO		(INT_TMR3)
+#define CONFIG_SYS_TMRINTR_MASK	(INT_ISR_INT24)
+#define CONFIG_SYS_TMRINTR_PEND	(0)
+#define CONFIG_SYS_TMRINTR_PRI		(INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif				/* CONFIG_M5272 */
+
+#ifdef CONFIG_M5275
+#include <asm/immap_5275.h>
+#include <asm/m5275.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(192)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif				/* CONFIG_M5275 */
+
+#ifdef CONFIG_M5282
+#include <asm/immap_5282.h>
+#include <asm/m5282.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CONFIG_SYS_TMRINTR_MASK	(1 << INT0_LO_DTMR3)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif				/* CONFIG_M5282 */
+
+#ifdef CONFIG_M5307
+#include <asm/immap_5307.h>
+#include <asm/m5307.h>
+
+#define CONFIG_SYS_UART_BASE            (MMAP_UART0 + \
+					(CONFIG_SYS_UART_PORT * 0x40))
+#define CONFIG_SYS_INTR_BASE            (MMAP_INTC)
+#define CONFIG_SYS_NUM_IRQS             (64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE          (MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE             (MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(((volatile intctrl_t *) \
+					(CONFIG_SYS_INTR_BASE))->ipr)
+#define CONFIG_SYS_TMRINTR_NO           (31)
+#define CONFIG_SYS_TMRINTR_MASK		(0x00000400)
+#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI          (MCFSIM_ICR_AUTOVEC | \
+					MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CONFIG_SYS_TIMER_PRESCALER      (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+#endif                          /* CONFIG_M5307 */
+
+#if defined(CONFIG_MCF5301x)
+#include <asm/immap_5301x.h>
+#include <asm/m5301x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+
+#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+#endif				/* CONFIG_M5301x */
+
+#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
+#include <asm/immap_5329.h>
+#include <asm/m5329.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+#endif				/* CONFIG_M5329 && CONFIG_M5373 */
+
+#if defined(CONFIG_M54418)
+#include <asm/immap_5441x.h>
+#include <asm/m5441x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
+
+#if (CONFIG_SYS_UART_PORT < 4)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + \
+					(CONFIG_SYS_UART_PORT * 0x4000))
+#else
+#define CONFIG_SYS_UART_BASE		(MMAP_UART4 + \
+					((CONFIG_SYS_UART_PORT - 4) * 0x4000))
+#endif
+
+#define MMAP_DSPI			MMAP_DSPI0
+#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG	(((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(192)
+
+#endif				/* CONFIG_M54418 */
+
+#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
+#include <asm/immap_5445x.h>
+#include <asm/m5445x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#if defined(CONFIG_M54455EVB)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
+#endif
+
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
+
+#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_PCI_BAR0		(CONFIG_SYS_MBAR)
+#define CONFIG_SYS_PCI_BAR5		(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
+#define CONFIG_SYS_PCI_TBATR5		(CONFIG_SYS_SDRAM_BASE)
+#endif
+#endif				/* CONFIG_M54451 || CONFIG_M54455 */
+
+#ifdef CONFIG_M547x
+#include <asm/immap_547x_8x.h>
+#include <asm/m547x_8x.h>
+
+#ifdef CONFIG_FSLDMAFEC
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
+
+#define FEC0_RX_TASK		0
+#define FEC0_TX_TASK		1
+#define FEC0_RX_PRIORITY	6
+#define FEC0_TX_PRIORITY	7
+#define FEC0_RX_INIT		16
+#define FEC0_TX_INIT		17
+#define FEC1_RX_TASK		2
+#define FEC1_TX_TASK		3
+#define FEC1_RX_PRIORITY	6
+#define FEC1_TX_PRIORITY	7
+#define FEC1_RX_INIT		30
+#define FEC1_TX_INIT		31
+#endif
+
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
+
+#ifdef CONFIG_SLTTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
+#define CONFIG_SYS_TMR_BASE		(MMAP_SLT0)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
+#define CONFIG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_PCI_BAR0		(0x40000000)
+#define CONFIG_SYS_PCI_BAR1		(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
+#define CONFIG_SYS_PCI_TBATR1		(CONFIG_SYS_SDRAM_BASE)
+#endif
+#endif				/* CONFIG_M547x */
+
+#ifdef CONFIG_M548x
+#include <asm/immap_547x_8x.h>
+#include <asm/m547x_8x.h>
+
+#ifdef CONFIG_FSLDMAFEC
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
+
+#define FEC0_RX_TASK		0
+#define FEC0_TX_TASK		1
+#define FEC0_RX_PRIORITY	6
+#define FEC0_TX_PRIORITY	7
+#define FEC0_RX_INIT		16
+#define FEC0_TX_INIT		17
+#define FEC1_RX_TASK		2
+#define FEC1_TX_TASK		3
+#define FEC1_RX_PRIORITY	6
+#define FEC1_TX_PRIORITY	7
+#define FEC1_RX_INIT		30
+#define FEC1_TX_INIT		31
+#endif
+
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
+
+/* Timer */
+#ifdef CONFIG_SLTTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
+#define CONFIG_SYS_TMR_BASE		(MMAP_SLT0)
+#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
+#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
+#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
+#define CONFIG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_PCI_BAR0		(CONFIG_SYS_MBAR)
+#define CONFIG_SYS_PCI_BAR1		(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
+#define CONFIG_SYS_PCI_TBATR1		(CONFIG_SYS_SDRAM_BASE)
+#endif
+#endif				/* CONFIG_M548x */
+
+#endif				/* __IMMAP_H */
diff --git a/arch/m68k/include/asm/immap_520x.h b/arch/m68k/include/asm/immap_520x.h
new file mode 100644
index 0000000..bb12374
--- /dev/null
+++ b/arch/m68k/include/asm/immap_520x.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF520x Internal Memory Map
+ *
+ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __IMMAP_520X__
+#define __IMMAP_520X__
+
+#define MMAP_SCM1	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS	(CONFIG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00008000)
+#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00030000)
+#define MMAP_SCM2	(CONFIG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA	(CONFIG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00048000)
+#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00058000)
+#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00084000)
+#define MMAP_EPORT0	(CONFIG_SYS_MBAR + 0x00088000)
+#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x0008C000)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00090000)
+#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x000A4000)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x000A8000)
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/qspi.h>
+
+/* System Controller Module */
+typedef struct scm1 {
+	u32 mpr;		/* 0x00 Master Privilege */
+	u32 rsvd1[7];
+	u32 pacra;		/* 0x20 Peripheral Access Ctrl A */
+	u32 pacrb;		/* 0x24 Peripheral Access Ctrl B */
+	u32 pacrc;		/* 0x28 Peripheral Access Ctrl C */
+	u32 pacrd;		/* 0x2C Peripheral Access Ctrl D */
+	u32 rsvd2[4];
+	u32 pacre;		/* 0x40 Peripheral Access Ctrl E */
+	u32 pacrf;		/* 0x44 Peripheral Access Ctrl F */
+	u32 rsvd3[3];
+	u32 bmt;		/* 0x50 bus monitor */
+} scm1_t;
+
+typedef struct scm2 {
+	u8 rsvd1[19];		/* 0x00 - 0x12 */
+	u8 wcr;			/* 0x13 */
+	u16 rsvd2;		/* 0x14 - 0x15 */
+	u16 cwcr;		/* 0x16 */
+	u8 rsvd3[3];		/* 0x18 - 0x1A */
+	u8 cwsr;		/* 0x1B */
+	u8 rsvd4[3];		/* 0x1C - 0x1E */
+	u8 scmisr;		/* 0x1F */
+	u8 rsvd5[79];		/* 0x20 - 0x6F */
+	u32 cfadr;		/* 0x70 */
+	u8 rsvd7;		/* 0x74 */
+	u8 cfier;		/* 0x75 */
+	u8 cfloc;		/* 0x76 */
+	u8 cfatr;		/* 0x77 */
+	u32 rsvd8;		/* 0x78 - 0x7B */
+	u32 cfdtr;		/* 0x7C */
+} scm2_t;
+
+/* Chip configuration module */
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
+typedef struct ccm_ctrl {
+	u16 ccr;		/* 0x00 Chip Cfg */
+	u16 res1;		/* 0x02 */
+	u16 rcon;		/* 0x04 Reset Cfg */
+	u16 cir;		/* 0x06 Chip ID */
+} ccm_t;
+
+/* GPIO port */
+typedef struct gpio_ctrl {
+	/* Port Output Data */
+	u8 podr_busctl;		/* 0x00 */
+	u8 podr_be;		/* 0x01 */
+	u8 podr_cs;		/* 0x02 */
+	u8 podr_feci2c;		/* 0x03 */
+	u8 podr_qspi;		/* 0x04 */
+	u8 podr_timer;		/* 0x05 */
+	u8 podr_uart;		/* 0x06 */
+	u8 podr_fech;		/* 0x07 */
+	u8 podr_fecl;		/* 0x08 */
+	u8 res01[3];		/* 0x9 - 0x0B */
+
+	/* Port Data Direction */
+	u8 pddr_busctl;		/* 0x0C */
+	u8 pddr_be;		/* 0x0D */
+	u8 pddr_cs;		/* 0x0E */
+	u8 pddr_feci2c;		/* 0x0F */
+	u8 pddr_qspi;		/* 0x10*/
+	u8 pddr_timer;		/* 0x11 */
+	u8 pddr_uart;		/* 0x12 */
+	u8 pddr_fech;		/* 0x13 */
+	u8 pddr_fecl;		/* 0x14 */
+	u8 res02[5];		/* 0x15 - 0x19 */
+
+	/* Port Data Direction */
+	u8 ppdr_cs;		/* 0x1A */
+	u8 ppdr_feci2c;		/* 0x1B */
+	u8 ppdr_qspi;		/* 0x1C */
+	u8 ppdr_timer;		/* 0x1D */
+	u8 ppdr_uart;		/* 0x1E */
+	u8 ppdr_fech;		/* 0x1F */
+	u8 ppdr_fecl;		/* 0x20 */
+	u8 res03[3];		/* 0x21 - 0x23 */
+
+	/* Port Clear Output Data */
+	u8 pclrr_busctl;	/* 0x24 */
+	u8 pclrr_be;		/* 0x25 */
+	u8 pclrr_cs;		/* 0x26 */
+	u8 pclrr_feci2c;	/* 0x27 */
+	u8 pclrr_qspi;		/* 0x28 */
+	u8 pclrr_timer;		/* 0x29 */
+	u8 pclrr_uart;		/* 0x2A */
+	u8 pclrr_fech;		/* 0x2B */
+	u8 pclrr_fecl;		/* 0x2C */
+	u8 res04[3];		/* 0x2D - 0x2F */
+
+	/* Pin Assignment */
+	u8 par_busctl;		/* 0x30 */
+	u8 par_be;		/* 0x31 */
+	u8 par_cs;		/* 0x32 */
+	u8 par_feci2c;		/* 0x33 */
+	u8 par_qspi;		/* 0x34 */
+	u8 par_timer;		/* 0x35 */
+	u16 par_uart;		/* 0x36 */
+	u8 par_fec;		/* 0x38 */
+	u8 par_irq;		/* 0x39 */
+
+	/* Mode Select Control */
+	/* Drive Strength Control */
+	u8 mscr_fb;		/* 0x3A */
+	u8 mscr_sdram;		/* 0x3B */
+
+	u8 dscr_i2c;		/* 0x3C */
+	u8 dscr_misc;		/* 0x3D */
+	u8 dscr_fec;		/* 0x3E */
+	u8 dscr_uart;		/* 0x3F */
+	u8 dscr_qspi;		/* 0x40 */
+} gpio_t;
+
+/* SDRAM controller */
+typedef struct sdram_ctrl {
+	u32 mode;		/* 0x00 Mode/Extended Mode */
+	u32 ctrl;		/* 0x04 Ctrl */
+	u32 cfg1;		/* 0x08 Cfg 1 */
+	u32 cfg2;		/* 0x0C Cfg 2 */
+	u32 res1[64];		/* 0x10 - 0x10F */
+	u32 cs0;		/* 0x110 Chip Select 0 Cfg */
+	u32 cs1;		/* 0x114 Chip Select 1 Cfg */
+} sdram_t;
+
+/* Clock Module */
+typedef struct pll_ctrl {
+	u8 odr;			/* 0x00 Output divider */
+	u8 rsvd1;
+	u8 cr;			/* 0x02 Control */
+	u8 rsvd2;
+	u8 mdr;			/* 0x04 Modulation Divider */
+	u8 rsvd3;
+	u8 fdr;			/* 0x06 Feedback Divider */
+	u8 rsvd4;
+} pll_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+	u16 cr;			/* 0x00 Control */
+	u16 mr;			/* 0x02 Modulus */
+	u16 cntr;		/* 0x04 Count */
+	u16 sr;			/* 0x06 Service */
+} wdog_t;
+
+#endif				/* __IMMAP_520X__ */
diff --git a/arch/m68k/include/asm/immap_5227x.h b/arch/m68k/include/asm/immap_5227x.h
new file mode 100644
index 0000000..710d6f5
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5227x.h
@@ -0,0 +1,237 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5227x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __IMMAP_5227X__
+#define __IMMAP_5227X__
+
+/* Module Base Addresses */
+#define MMAP_SCM1	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS	(CONFIG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00008000)
+#define MMAP_CAN	(CONFIG_SYS_MBAR + 0x00020000)
+#define MMAP_RTC	(CONFIG_SYS_MBAR + 0x0003C000)
+#define MMAP_SCM2	(CONFIG_SYS_MBAR + 0x00040010)
+#define MMAP_SCM3	(CONFIG_SYS_MBAR + 0x00040070)
+#define MMAP_EDMA	(CONFIG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00048000)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x0004C000)
+#define MMAP_IACK	(CONFIG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00058000)
+#define MMAP_DSPI	(CONFIG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00084000)
+#define MMAP_PWM	(CONFIG_SYS_MBAR + 0x00090000)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00094000)
+#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x000A4000)
+#define MMAP_ADC	(CONFIG_SYS_MBAR + 0x000A8000)
+#define MMAP_LCD	(CONFIG_SYS_MBAR + 0x000AC000)
+#define MMAP_LCD_BGLUT	(CONFIG_SYS_MBAR + 0x000AC800)
+#define MMAP_LCD_GWLUT	(CONFIG_SYS_MBAR + 0x000ACC00)
+#define MMAP_USBHW	(CONFIG_SYS_MBAR + 0x000B0000)
+#define MMAP_USBCAPS	(CONFIG_SYS_MBAR + 0x000B0100)
+#define MMAP_USBEHCI	(CONFIG_SYS_MBAR + 0x000B0140)
+#define MMAP_USBOTG	(CONFIG_SYS_MBAR + 0x000B01A0)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x000B8000)
+#define MMAP_SSI	(CONFIG_SYS_MBAR + 0x000BC000)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x000C0000)
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/lcd.h>
+#include <asm/coldfire/pwm.h>
+#include <asm/coldfire/ssi.h>
+
+/* Reset Controller Module (RCM) */
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
+/* Chip Configuration Module (CCM) */
+typedef struct ccm {
+	u16 ccr;		/* Chip Configuration (Rd-only) */
+	u16 resv1;
+	u16 rcon;		/* Reset Configuration (Rd-only) */
+	u16 cir;		/* Chip Identification (Rd-only) */
+	u32 resv2;
+	u16 misccr;		/* Miscellaneous Control */
+	u16 cdr;		/* Clock Divider */
+	u16 uocsr;		/* USB On-the-Go Controller Status */
+	u16 resv4;
+	u16 sbfsr;		/* Serial Boot Status */
+	u16 sbfcr;		/* Serial Boot Control */
+} ccm_t;
+
+typedef struct canex_ctrl {
+	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
+	u32 res0[0x700];	/* 0x100 */
+	can_msg_t rxim[16];	/* 0x800 Rx Individual Mask 0-15 */
+} canex_t;
+
+/* General Purpose I/O Module (GPIO) */
+typedef struct gpio {
+	/* Port Output Data Registers */
+	u8 podr_be;		/* 0x00 */
+	u8 podr_cs;		/* 0x01 */
+	u8 podr_fbctl;		/* 0x02 */
+	u8 podr_i2c;		/* 0x03 */
+	u8 rsvd1;		/* 0x04 */
+	u8 podr_uart;		/* 0x05 */
+	u8 podr_dspi;		/* 0x06 */
+	u8 podr_timer;		/* 0x07 */
+	u8 podr_lcdctl;		/* 0x08 */
+	u8 podr_lcddatah;	/* 0x09 */
+	u8 podr_lcddatam;	/* 0x0A */
+	u8 podr_lcddatal;	/* 0x0B */
+
+	/* Port Data Direction Registers */
+	u8 pddr_be;		/* 0x0C */
+	u8 pddr_cs;		/* 0x0D */
+	u8 pddr_fbctl;		/* 0x0E */
+	u8 pddr_i2c;		/* 0x0F */
+	u8 rsvd2;		/* 0x10 */
+	u8 pddr_uart;		/* 0x11 */
+	u8 pddr_dspi;		/* 0x12 */
+	u8 pddr_timer;		/* 0x13 */
+	u8 pddr_lcdctl;		/* 0x14 */
+	u8 pddr_lcddatah;	/* 0x15 */
+	u8 pddr_lcddatam;	/* 0x16 */
+	u8 pddr_lcddatal;	/* 0x17 */
+
+	/* Port Pin Data/Set Data Registers */
+	u8 ppdsdr_be;		/* 0x18 */
+	u8 ppdsdr_cs;		/* 0x19 */
+	u8 ppdsdr_fbctl;	/* 0x1A */
+	u8 ppdsdr_i2c;		/* 0x1B */
+	u8 rsvd3;		/* 0x1C */
+	u8 ppdsdr_uart;		/* 0x1D */
+	u8 ppdsdr_dspi;		/* 0x1E */
+	u8 ppdsdr_timer;	/* 0x1F */
+	u8 ppdsdr_lcdctl;	/* 0x20 */
+	u8 ppdsdr_lcddatah;	/* 0x21 */
+	u8 ppdsdr_lcddatam;	/* 0x22 */
+	u8 ppdsdr_lcddatal;	/* 0x23 */
+
+	/* Port Clear Output Data Registers */
+	u8 pclrr_be;		/* 0x24 */
+	u8 pclrr_cs;		/* 0x25 */
+	u8 pclrr_fbctl;		/* 0x26 */
+	u8 pclrr_i2c;		/* 0x27 */
+	u8 rsvd4;		/* 0x28 */
+	u8 pclrr_uart;		/* 0x29 */
+	u8 pclrr_dspi;		/* 0x2A */
+	u8 pclrr_timer;		/* 0x2B */
+	u8 pclrr_lcdctl;	/* 0x2C */
+	u8 pclrr_lcddatah;	/* 0x2D */
+	u8 pclrr_lcddatam;	/* 0x2E */
+	u8 pclrr_lcddatal;	/* 0x2F */
+
+	/* Pin Assignment Registers */
+	u8 par_be;		/* 0x30 */
+	u8 par_cs;		/* 0x31 */
+	u8 par_fbctl;		/* 0x32 */
+	u8 par_i2c;		/* 0x33 */
+	u16 par_uart;		/* 0x34 */
+	u8 par_dspi;		/* 0x36 */
+	u8 par_timer;		/* 0x37 */
+	u8 par_lcdctl;		/* 0x38 */
+	u8 par_irq;		/* 0x39 */
+	u16 rsvd6;		/* 0x3A - 0x3B */
+	u32 par_lcdh;		/* 0x3C */
+	u32 par_lcdl;		/* 0x40 */
+
+	/* Mode select control registers */
+	u8 mscr_fb;		/* 0x44 */
+	u8 mscr_sdram;		/* 0x45 */
+
+	u16 rsvd7;		/* 0x46 - 0x47 */
+	u8 dscr_dspi;		/* 0x48 */
+	u8 dscr_timer;		/* 0x49 */
+	u8 dscr_i2c;		/* 0x4A */
+	u8 dscr_lcd;		/* 0x4B */
+	u8 dscr_debug;		/* 0x4C */
+	u8 dscr_clkrst;		/* 0x4D */
+	u8 dscr_irq;		/* 0x4E */
+	u8 dscr_uart;		/* 0x4F */
+} gpio_t;
+
+/* SDRAM Controller (SDRAMC) */
+typedef struct sdramc {
+	u32 sdmr;		/* Mode/Extended Mode */
+	u32 sdcr;		/* Control */
+	u32 sdcfg1;		/* Configuration 1 */
+	u32 sdcfg2;		/* Chip Select */
+	u8 resv0[0x100];
+	u32 sdcs0;		/* Mode/Extended Mode */
+	u32 sdcs1;		/* Mode/Extended Mode */
+} sdramc_t;
+
+/* Phase Locked Loop (PLL) */
+typedef struct pll {
+	u32 pcr;		/* PLL Control */
+	u32 psr;		/* PLL Status */
+} pll_t;
+
+/* System Control Module register  */
+typedef struct scm1 {
+	u32 mpr;		/* 0x00 Master Privilege */
+	u32 rsvd1[7];
+	u32 pacra;		/* 0x20 */
+	u32 pacrb;		/* 0x24 */
+	u32 pacrc;		/* 0x28 */
+	u32 pacrd;		/* 0x2C */
+	u32 rsvd2[4];
+	u32 pacre;		/* 0x40 */
+	u32 pacrf;		/* 0x44 */
+	u32 pacrg;		/* 0x48 */
+	u32 rsvd3;
+	u32 pacri;		/* 0x50 */
+} scm1_t;
+
+typedef struct scm2_ctrl {
+	u8 res1[3];		/* 0x00 - 0x02 */
+	u8 wcr;			/* 0x03 wakeup control */
+	u16 res2;		/* 0x04 - 0x05 */
+	u16 cwcr;		/* 0x06 Core Watchdog Control */
+	u8 res3[3];		/* 0x08 - 0x0A */
+	u8 cwsr;		/* 0x0B Core Watchdog Service */
+	u8 res4[2];		/* 0x0C - 0x0D */
+	u8 scmisr;		/* 0x0F Interrupt Status */
+	u32 res5;		/* 0x20 */
+	u32 bcr;		/* 0x24 Burst Configuration */
+} scm2_t;
+
+typedef struct scm3_ctrl {
+	u32 cfadr;		/* 0x00 Core Fault Address */
+	u8 res7;		/* 0x04 */
+	u8 cfier;		/* 0x05 Core Fault Interrupt Enable */
+	u8 cfloc;		/* 0x06 Core Fault Location */
+	u8 cfatr;		/* 0x07 Core Fault Attributes */
+	u32 cfdtr;		/* 0x08 Core Fault Data */
+} scm3_t;
+
+typedef struct rtcex {
+	u32 rsvd1[3];
+	u32 gocu;
+	u32 gocl;
+} rtcex_t;
+#endif				/* __IMMAP_5227X__ */
diff --git a/arch/m68k/include/asm/immap_5235.h b/arch/m68k/include/asm/immap_5235.h
new file mode 100644
index 0000000..27d905e
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5235.h
@@ -0,0 +1,219 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5329 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __IMMAP_5235__
+#define __IMMAP_5235__
+
+#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1	(CONFIG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU	(CONFIG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2	(CONFIG_SYS_MBAR + 0x001F0000)
+
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/mdha.h>
+#include <asm/coldfire/qspi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/coldfire/skha.h>
+
+/* System Control Module register */
+typedef struct scm_ctrl {
+	u32 ipsbar;		/* 0x00 - MBAR */
+	u32 res1;		/* 0x04 */
+	u32 rambar;		/* 0x08 - RAMBAR */
+	u32 res2;		/* 0x0C */
+	u8 crsr;		/* 0x10 Core Reset Status Register */
+	u8 cwcr;		/* 0x11 Core Watchdog Control Register */
+	u8 lpicr;		/* 0x12 Low-Power Interrupt Control Register */
+	u8 cwsr;		/* 0x13 Core Watchdog Service Register */
+	u32 dmareqc;		/* 0x14 */
+	u32 res3;		/* 0x18 */
+	u32 mpark;		/* 0x1C */
+	u8 mpr;			/* 0x20 */
+	u8 res4[3];		/* 0x21 - 0x23 */
+	u8 pacr0;		/* 0x24 */
+	u8 pacr1;		/* 0x25 */
+	u8 pacr2;		/* 0x26 */
+	u8 pacr3;		/* 0x27 */
+	u8 pacr4;		/* 0x28 */
+	u32 res5;		/* 0x29 */
+	u8 pacr5;		/* 0x2a */
+	u8 pacr6;		/* 0x2b */
+	u8 pacr7;		/* 0x2c */
+	u32 res6;		/* 0x2d */
+	u8 pacr8;		/* 0x2e */
+	u32 res7;		/* 0x2f */
+	u8 gpacr;		/* 0x30 */
+	u8 res8[3];		/* 0x31 - 0x33 */
+} scm_t;
+
+/* SDRAM controller registers */
+typedef struct sdram_ctrl {
+	u16 dcr;		/* 0x00 Control register */
+	u16 res1[3];		/* 0x02 - 0x07 */
+	u32 dacr0;		/* 0x08 address and control register 0 */
+	u32 dmr0;		/* 0x0C mask register block 0 */
+	u32 dacr1;		/* 0x10 address and control register 1 */
+	u32 dmr1;		/* 0x14 mask register block 1 */
+} sdram_t;
+
+typedef struct canex_ctrl {
+	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
+} canex_t;
+
+/* GPIO port registers */
+typedef struct gpio_ctrl {
+	/* Port Output Data Registers */
+	u8 podr_addr;		/* 0x00 */
+	u8 podr_datah;		/* 0x01 */
+	u8 podr_datal;		/* 0x02 */
+	u8 podr_busctl;		/* 0x03 */
+	u8 podr_bs;		/* 0x04 */
+	u8 podr_cs;		/* 0x05 */
+	u8 podr_sdram;		/* 0x06 */
+	u8 podr_feci2c;		/* 0x07 */
+	u8 podr_uarth;		/* 0x08 */
+	u8 podr_uartl;		/* 0x09 */
+	u8 podr_qspi;		/* 0x0A */
+	u8 podr_timer;		/* 0x0B */
+	u8 podr_etpu;		/* 0x0C */
+	u8 res1[3];		/* 0x0D - 0x0F */
+
+	/* Port Data Direction Registers */
+	u8 pddr_addr;		/* 0x10 */
+	u8 pddr_datah;		/* 0x11 */
+	u8 pddr_datal;		/* 0x12 */
+	u8 pddr_busctl;		/* 0x13 */
+	u8 pddr_bs;		/* 0x14 */
+	u8 pddr_cs;		/* 0x15 */
+	u8 pddr_sdram;		/* 0x16 */
+	u8 pddr_feci2c;		/* 0x17 */
+	u8 pddr_uarth;		/* 0x18 */
+	u8 pddr_uartl;		/* 0x19 */
+	u8 pddr_qspi;		/* 0x1A */
+	u8 pddr_timer;		/* 0x1B */
+	u8 pddr_etpu;		/* 0x1C */
+	u8 res2[3];		/* 0x1D - 0x1F */
+
+	/* Port Data Direction Registers */
+	u8 ppdsdr_addr;		/* 0x20 */
+	u8 ppdsdr_datah;	/* 0x21 */
+	u8 ppdsdr_datal;	/* 0x22 */
+	u8 ppdsdr_busctl;	/* 0x23 */
+	u8 ppdsdr_bs;		/* 0x24 */
+	u8 ppdsdr_cs;		/* 0x25 */
+	u8 ppdsdr_sdram;	/* 0x26 */
+	u8 ppdsdr_feci2c;	/* 0x27 */
+	u8 ppdsdr_uarth;	/* 0x28 */
+	u8 ppdsdr_uartl;	/* 0x29 */
+	u8 ppdsdr_qspi;		/* 0x2A */
+	u8 ppdsdr_timer;	/* 0x2B */
+	u8 ppdsdr_etpu;		/* 0x2C */
+	u8 res3[3];		/* 0x2D - 0x2F */
+
+	/* Port Clear Output Data Registers */
+	u8 pclrr_addr;		/* 0x30 */
+	u8 pclrr_datah;		/* 0x31 */
+	u8 pclrr_datal;		/* 0x32 */
+	u8 pclrr_busctl;	/* 0x33 */
+	u8 pclrr_bs;		/* 0x34 */
+	u8 pclrr_cs;		/* 0x35 */
+	u8 pclrr_sdram;		/* 0x36 */
+	u8 pclrr_feci2c;	/* 0x37 */
+	u8 pclrr_uarth;		/* 0x38 */
+	u8 pclrr_uartl;		/* 0x39 */
+	u8 pclrr_qspi;		/* 0x3A */
+	u8 pclrr_timer;		/* 0x3B */
+	u8 pclrr_etpu;		/* 0x3C */
+	u8 res4[3];		/* 0x3D - 0x3F */
+
+	/* Pin Assignment Registers */
+	u8 par_ad;		/* 0x40 */
+	u8 res5;		/* 0x41 */
+	u16 par_busctl;		/* 0x42 */
+	u8 par_bs;		/* 0x44 */
+	u8 par_cs;		/* 0x45 */
+	u8 par_sdram;		/* 0x46 */
+	u8 par_feci2c;		/* 0x47 */
+	u16 par_uart;		/* 0x48 */
+	u8 par_qspi;		/* 0x4A */
+	u8 res6;		/* 0x4B */
+	u16 par_timer;		/* 0x4C */
+	u8 par_etpu;		/* 0x4E */
+	u8 res7;		/* 0x4F */
+
+	/* Drive Strength Control Registers */
+	u8 dscr_eim;		/* 0x50 */
+	u8 dscr_etpu;		/* 0x51 */
+	u8 dscr_feci2c;		/* 0x52 */
+	u8 dscr_uart;		/* 0x53 */
+	u8 dscr_qspi;		/* 0x54 */
+	u8 dscr_timer;		/* 0x55 */
+	u16 res8;		/* 0x56 */
+} gpio_t;
+
+/*Chip configuration module registers */
+typedef struct ccm_ctrl {
+	u8 rcr;			/* 0x01 */
+	u8 rsr;			/* 0x02 */
+	u16 res1;		/* 0x03 */
+	u16 ccr;		/* 0x04 Chip configuration register */
+	u16 lpcr;		/* 0x06 Low-power Control register */
+	u16 rcon;		/* 0x08 Rreset configuration register */
+	u16 cir;		/* 0x0a Chip identification register */
+} ccm_t;
+
+/* Clock Module registers */
+typedef struct pll_ctrl {
+	u32 syncr;		/* 0x00 synthesizer control register */
+	u32 synsr;		/* 0x04 synthesizer status register */
+} pll_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+	u16 cr;			/* 0x00 Control register */
+	u16 mr;			/* 0x02 Modulus register */
+	u16 cntr;		/* 0x04 Count register */
+	u16 sr;			/* 0x06 Service register */
+} wdog_t;
+
+#endif				/* __IMMAP_5235__ */
diff --git a/arch/m68k/include/asm/immap_5249.h b/arch/m68k/include/asm/immap_5249.h
new file mode 100644
index 0000000..b599ca6
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5249.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5249 Internal Memory Map
+ *
+ * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ */
+
+#ifndef __IMMAP_5249__
+#define __IMMAP_5249__
+
+#define MMAP_INTC		(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS		(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0		(CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1		(CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0		(CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1		(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_QSPI		(CONFIG_SYS_MBAR + 0x00000400)
+
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/qspi.h>
+
+#endif				/* __IMMAP_5249__ */
diff --git a/arch/m68k/include/asm/immap_5253.h b/arch/m68k/include/asm/immap_5253.h
new file mode 100644
index 0000000..883782a
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5253.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5253 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __IMMAP_5253__
+#define __IMMAP_5253__
+
+#define MMAP_INTC		(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS		(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DTMR0		(CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1		(CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0		(CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1		(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_I2C0		(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_QSPI		(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_CAN0		(CONFIG_SYS_MBAR + 0x00010000)
+#define MMAP_CAN1		(CONFIG_SYS_MBAR + 0x00011000)
+
+#define MMAP_PAR		(CONFIG_SYS_MBAR2 + 0x0000019C)
+#define MMAP_I2C1		(CONFIG_SYS_MBAR2 + 0x00000440)
+#define MMAP_UART2		(CONFIG_SYS_MBAR2 + 0x00000C00)
+
+#include <asm/coldfire/ata.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/qspi.h>
+
+typedef struct canex_ctrl {
+	can_msg_t msg[32];	/* 0x80 Message Buffer 0-31 */
+} canex_t;
+
+#endif				/* __IMMAP_5253__ */
diff --git a/arch/m68k/include/asm/immap_5271.h b/arch/m68k/include/asm/immap_5271.h
new file mode 100644
index 0000000..27d7861
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5271.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5272 Internal Memory Map
+ *
+ * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *               2006 Zachary P. Landau <zachary.landau@labxtechnologies.com>
+ */
+
+#ifndef __IMMAP_5271__
+#define __IMMAP_5271__
+
+#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN1	(CONFIG_SYS_MBAR + 0x001C0000)
+#define MMAP_ETPU	(CONFIG_SYS_MBAR + 0x001D0000)
+#define MMAP_CAN2	(CONFIG_SYS_MBAR + 0x001F0000)
+
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/mdha.h>
+#include <asm/coldfire/qspi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/coldfire/skha.h>
+
+
+#endif				/* __IMMAP_5271__ */
diff --git a/arch/m68k/include/asm/immap_5272.h b/arch/m68k/include/asm/immap_5272.h
new file mode 100644
index 0000000..cd7b672
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5272.h
@@ -0,0 +1,303 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5272 Internal Memory Map
+ *
+ * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ */
+
+#ifndef __IMMAP_5272__
+#define __IMMAP_5272__
+
+#define MMAP_CFG	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC	(CONFIG_SYS_MBAR + 0x00000020)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x000000A0)
+#define MMAP_PWM	(CONFIG_SYS_MBAR + 0x000000C0)
+#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x000000E0)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_TMR0	(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_TMR1	(CONFIG_SYS_MBAR + 0x00000220)
+#define MMAP_TMR2	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_TMR3	(CONFIG_SYS_MBAR + 0x00000260)
+#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_PLIC	(CONFIG_SYS_MBAR + 0x00000300)
+#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00000840)
+#define MMAP_USB	(CONFIG_SYS_MBAR + 0x00001000)
+
+#include <asm/coldfire/pwm.h>
+
+/* System configuration registers */
+typedef struct sys_ctrl {
+	uint sc_mbar;
+	ushort sc_scr;
+	ushort sc_spr;
+	uint sc_pmr;
+	char res1[2];
+	ushort sc_alpr;
+	uint sc_dir;
+	char res2[12];
+} sysctrl_t;
+
+/* Interrupt module registers */
+typedef struct int_ctrl {
+	uint int_icr1;
+	uint int_icr2;
+	uint int_icr3;
+	uint int_icr4;
+	uint int_isr;
+	uint int_pitr;
+	uint int_piwr;
+	uchar res1[3];
+	uchar int_pivr;
+} intctrl_t;
+
+/* Chip select module registers */
+typedef struct cs_ctlr {
+	uint cs_br0;
+	uint cs_or0;
+	uint cs_br1;
+	uint cs_or1;
+	uint cs_br2;
+	uint cs_or2;
+	uint cs_br3;
+	uint cs_or3;
+	uint cs_br4;
+	uint cs_or4;
+	uint cs_br5;
+	uint cs_or5;
+	uint cs_br6;
+	uint cs_or6;
+	uint cs_br7;
+	uint cs_or7;
+} csctrl_t;
+
+/* GPIO port registers */
+typedef struct gpio_ctrl {
+	uint gpio_pacnt;
+	ushort gpio_paddr;
+	ushort gpio_padat;
+	uint gpio_pbcnt;
+	ushort gpio_pbddr;
+	ushort gpio_pbdat;
+	uchar res1[4];
+	ushort gpio_pcddr;
+	ushort gpio_pcdat;
+	uint gpio_pdcnt;
+	uchar res2[4];
+} gpio_t;
+
+/* DMA module registers */
+typedef struct dma_ctrl {
+	ulong dma_dmr;
+	uchar res1[2];
+	ushort dma_dir;
+	ulong dma_dbcr;
+	ulong dma_dsar;
+	ulong dma_ddar;
+	uchar res2[12];
+} dma_t;
+
+/* SDRAM controller registers, offset: 0x180 */
+typedef struct sdram_ctrl {
+	uchar res1[2];
+	ushort sdram_sdcr;
+	uchar res2[2];
+	ushort sdram_sdtr;
+	uchar res3[120];
+} sdramctrl_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+	ushort wdog_wrrr;
+	ushort res1;
+	ushort wdog_wirr;
+	ushort res2;
+	ushort wdog_wcr;
+	ushort res3;
+	ushort wdog_wer;
+	uchar res4[114];
+} wdog_t;
+
+/* PLIC module registers */
+typedef struct plic_ctrl {
+	ulong plic_p0b1rr;
+	ulong plic_p1b1rr;
+	ulong plic_p2b1rr;
+	ulong plic_p3b1rr;
+	ulong plic_p0b2rr;
+	ulong plic_p1b2rr;
+	ulong plic_p2b2rr;
+	ulong plic_p3b2rr;
+	uchar plic_p0drr;
+	uchar plic_p1drr;
+	uchar plic_p2drr;
+	uchar plic_p3drr;
+	uchar res1[4];
+	ulong plic_p0b1tr;
+	ulong plic_p1b1tr;
+	ulong plic_p2b1tr;
+	ulong plic_p3b1tr;
+	ulong plic_p0b2tr;
+	ulong plic_p1b2tr;
+	ulong plic_p2b2tr;
+	ulong plic_p3b2tr;
+	uchar plic_p0dtr;
+	uchar plic_p1dtr;
+	uchar plic_p2dtr;
+	uchar plic_p3dtr;
+	uchar res2[4];
+	ushort plic_p0cr;
+	ushort plic_p1cr;
+	ushort plic_p2cr;
+	ushort plic_p3cr;
+	ushort plic_p0icr;
+	ushort plic_p1icr;
+	ushort plic_p2icr;
+	ushort plic_p3icr;
+	ushort plic_p0gmr;
+	ushort plic_p1gmr;
+	ushort plic_p2gmr;
+	ushort plic_p3gmr;
+	ushort plic_p0gmt;
+	ushort plic_p1gmt;
+	ushort plic_p2gmt;
+	ushort plic_p3gmt;
+	uchar res3;
+	uchar plic_pgmts;
+	uchar plic_pgmta;
+	uchar res4;
+	uchar plic_p0gcir;
+	uchar plic_p1gcir;
+	uchar plic_p2gcir;
+	uchar plic_p3gcir;
+	uchar plic_p0gcit;
+	uchar plic_p1gcit;
+	uchar plic_p2gcit;
+	uchar plic_p3gcit;
+	uchar res5[3];
+	uchar plic_pgcitsr;
+	uchar res6[3];
+	uchar plic_pdcsr;
+	ushort plic_p0psr;
+	ushort plic_p1psr;
+	ushort plic_p2psr;
+	ushort plic_p3psr;
+	ushort plic_pasr;
+	uchar res7;
+	uchar plic_plcr;
+	ushort res8;
+	ushort plic_pdrqr;
+	ushort plic_p0sdr;
+	ushort plic_p1sdr;
+	ushort plic_p2sdr;
+	ushort plic_p3sdr;
+	ushort res9;
+	ushort plic_pcsr;
+	uchar res10[1184];
+} plic_t;
+
+/* USB module registers */
+typedef struct usb {
+	ushort res1;
+	ushort usb_fnr;
+	ushort res2;
+	ushort usb_fnmr;
+	ushort res3;
+	ushort usb_rfmr;
+	ushort res4;
+	ushort usb_rfmmr;
+	uchar res5[3];
+	uchar usb_far;
+	ulong usb_asr;
+	ulong usb_drr1;
+	ulong usb_drr2;
+	ushort res6;
+	ushort usb_specr;
+	ushort res7;
+	ushort usb_ep0sr;
+	ulong usb_iep0cfg;
+	ulong usb_oep0cfg;
+	ulong usb_ep1cfg;
+	ulong usb_ep2cfg;
+	ulong usb_ep3cfg;
+	ulong usb_ep4cfg;
+	ulong usb_ep5cfg;
+	ulong usb_ep6cfg;
+	ulong usb_ep7cfg;
+	ulong usb_ep0ctl;
+	ushort res8;
+	ushort usb_ep1ctl;
+	ushort res9;
+	ushort usb_ep2ctl;
+	ushort res10;
+	ushort usb_ep3ctl;
+	ushort res11;
+	ushort usb_ep4ctl;
+	ushort res12;
+	ushort usb_ep5ctl;
+	ushort res13;
+	ushort usb_ep6ctl;
+	ushort res14;
+	ushort usb_ep7ctl;
+	ulong usb_ep0isr;
+	ushort res15;
+	ushort usb_ep1isr;
+	ushort res16;
+	ushort usb_ep2isr;
+	ushort res17;
+	ushort usb_ep3isr;
+	ushort res18;
+	ushort usb_ep4isr;
+	ushort res19;
+	ushort usb_ep5isr;
+	ushort res20;
+	ushort usb_ep6isr;
+	ushort res21;
+	ushort usb_ep7isr;
+	ulong usb_ep0imr;
+	ushort res22;
+	ushort usb_ep1imr;
+	ushort res23;
+	ushort usb_ep2imr;
+	ushort res24;
+	ushort usb_ep3imr;
+	ushort res25;
+	ushort usb_ep4imr;
+	ushort res26;
+	ushort usb_ep5imr;
+	ushort res27;
+	ushort usb_ep6imr;
+	ushort res28;
+	ushort usb_ep7imr;
+	ulong usb_ep0dr;
+	ulong usb_ep1dr;
+	ulong usb_ep2dr;
+	ulong usb_ep3dr;
+	ulong usb_ep4dr;
+	ulong usb_ep5dr;
+	ulong usb_ep6dr;
+	ulong usb_ep7dr;
+	ushort res29;
+	ushort usb_ep0dpr;
+	ushort res30;
+	ushort usb_ep1dpr;
+	ushort res31;
+	ushort usb_ep2dpr;
+	ushort res32;
+	ushort usb_ep3dpr;
+	ushort res33;
+	ushort usb_ep4dpr;
+	ushort res34;
+	ushort usb_ep5dpr;
+	ushort res35;
+	ushort usb_ep6dpr;
+	ushort res36;
+	ushort usb_ep7dpr;
+	uchar res37[788];
+	uchar usb_cfgram[1024];
+} usb_t;
+
+#endif				/* __IMMAP_5272__ */
diff --git a/arch/m68k/include/asm/immap_5275.h b/arch/m68k/include/asm/immap_5275.h
new file mode 100644
index 0000000..8b1a08b
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5275.h
@@ -0,0 +1,350 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5274/5 Internal Memory Map
+ *
+ * Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
+ * Based on work Copyright (c) 2003 Josef Baumgartner
+ *                                  <josef.baumgartner@telex.de>
+ */
+
+#ifndef __IMMAP_5275__
+#define __IMMAP_5275__
+
+#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000110)
+#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000120)
+#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x00000130)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_FEC0FIFO	(CONFIG_SYS_MBAR + 0x00001400)
+#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00001800)
+#define MMAP_FEC1FIFO	(CONFIG_SYS_MBAR + 0x00001C00)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
+#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x00110000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110004)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
+#define MMAP_MDHA	(CONFIG_SYS_MBAR + 0x00190000)
+#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x001A0000)
+#define MMAP_SKHA	(CONFIG_SYS_MBAR + 0x001B0000)
+#define MMAP_USB	(CONFIG_SYS_MBAR + 0x001C0000)
+#define MMAP_PWM0	(CONFIG_SYS_MBAR + 0x001D0000)
+
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/mdha.h>
+#include <asm/coldfire/pwm.h>
+#include <asm/coldfire/qspi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/coldfire/skha.h>
+
+/* System configuration registers
+*/
+typedef	struct sys_ctrl {
+	u32 ipsbar;
+	u32 res1;
+	u32 rambar;
+	u32 res2;
+	u8 crsr;
+	u8 cwcr;
+	u8 lpicr;
+	u8 cwsr;
+	u8 res3[8];
+	u32 mpark;
+	u8 mpr;
+	u8 res4[3];
+	u8 pacr0;
+	u8 pacr1;
+	u8 pacr2;
+	u8 pacr3;
+	u8 pacr4;
+	u8 res5;
+	u8 pacr5;
+	u8 pacr6;
+	u8 pacr7;
+	u8 res6;
+	u8 pacr8;
+	u8 res7;
+	u8 gpacr;
+	u8 res8[3];
+} sysctrl_t;
+/* SDRAM controller registers, offset: 0x040
+ */
+typedef struct sdram_ctrl {
+	u32 sdmr;
+	u32 sdcr;
+	u32 sdcfg1;
+	u32 sdcfg2;
+	u32 sdbar0;
+	u32 sdbmr0;
+	u32 sdbar1;
+	u32 sdbmr1;
+} sdramctrl_t;
+
+/* DMA module registers, offset 0x100
+ */
+typedef struct	dma_ctrl {
+	u32 sar;
+	u32 dar;
+	u32 dsrbcr;
+	u32 dcr;
+} dma_t;
+
+/* GPIO port registers
+*/
+typedef struct	gpio_ctrl {
+	/* Port Output Data Registers */
+	u8 podr_res1[4];
+	u8 podr_busctl;
+	u8 podr_addr;
+	u8 podr_res2[2];
+	u8 podr_cs;
+	u8 podr_res3;
+	u8 podr_fec0h;
+	u8 podr_fec0l;
+	u8 podr_feci2c;
+	u8 podr_qspi;
+	u8 podr_sdram;
+	u8 podr_timerh;
+	u8 podr_timerl;
+	u8 podr_uartl;
+	u8 podr_fec1h;
+	u8 podr_fec1l;
+	u8 podr_bs;
+	u8 podr_res4;
+	u8 podr_usbh;
+	u8 podr_usbl;
+	u8 podr_uarth;
+	u8 podr_res5[3];
+	/* Port Data Direction Registers */
+	u8 pddr_res1[4];
+	u8 pddr_busctl;
+	u8 pddr_addr;
+	u8 pddr_res2[2];
+	u8 pddr_cs;
+	u8 pddr_res3;
+	u8 pddr_fec0h;
+	u8 pddr_fec0l;
+	u8 pddr_feci2c;
+	u8 pddr_qspi;
+	u8 pddr_sdram;
+	u8 pddr_timerh;
+	u8 pddr_timerl;
+	u8 pddr_uartl;
+	u8 pddr_fec1h;
+	u8 pddr_fec1l;
+	u8 pddr_bs;
+	u8 pddr_res4;
+	u8 pddr_usbh;
+	u8 pddr_usbl;
+	u8 pddr_uarth;
+	u8 pddr_res5[3];
+	/* Port Pin Data/Set Registers */
+	u8 ppdsdr_res1[4];
+	u8 ppdsdr_busctl;
+	u8 ppdsdr_addr;
+	u8 ppdsdr_res2[2];
+	u8 ppdsdr_cs;
+	u8 ppdsdr_res3;
+	u8 ppdsdr_fec0h;
+	u8 ppdsdr_fec0l;
+	u8 ppdsdr_feci2c;
+	u8 ppdsdr_qspi;
+	u8 ppdsdr_sdram;
+	u8 ppdsdr_timerh;
+	u8 ppdsdr_timerl;
+	u8 ppdsdr_uartl;
+	u8 ppdsdr_fec1h;
+	u8 ppdsdr_fec1l;
+	u8 ppdsdr_bs;
+	u8 ppdsdr_res4;
+	u8 ppdsdr_usbh;
+	u8 ppdsdr_usbl;
+	u8 ppdsdr_uarth;
+	u8 ppdsdr_res5[3];
+	/* Port Clear Output Data Registers */
+	u8 pclrr_res1[4];
+	u8 pclrr_busctl;
+	u8 pclrr_addr;
+	u8 pclrr_res2[2];
+	u8 pclrr_cs;
+	u8 pclrr_res3;
+	u8 pclrr_fec0h;
+	u8 pclrr_fec0l;
+	u8 pclrr_feci2c;
+	u8 pclrr_qspi;
+	u8 pclrr_sdram;
+	u8 pclrr_timerh;
+	u8 pclrr_timerl;
+	u8 pclrr_uartl;
+	u8 pclrr_fec1h;
+	u8 pclrr_fec1l;
+	u8 pclrr_bs;
+	u8 pclrr_res4;
+	u8 pclrr_usbh;
+	u8 pclrr_usbl;
+	u8 pclrr_uarth;
+	u8 pclrr_res5[3];
+	/* Pin Assignment Registers */
+	u8 par_addr;
+	u8 par_cs;
+	u16 par_busctl;
+	u8 par_res1[2];
+	u16 par_usb;
+	u8 par_fec0hl;
+	u8 par_fec1hl;
+	u16 par_timer;
+	u16 par_uart;
+	u16 par_qspi;
+	u16 par_sdram;
+	u16 par_feci2c;
+	u8 par_bs;
+	u8 par_res2[3];
+} gpio_t;
+
+
+/* Watchdog registers
+ */
+typedef struct wdog_ctrl {
+	u16 wcr;
+	u16 wmr;
+	u16 wcntr;
+	u16 wsr;
+	u8 res4[114];
+} wdog_t;
+
+/* USB module registers
+*/
+typedef struct usb {
+	u16 res1;
+	u16 fnr;
+	u16 res2;
+	u16 fnmr;
+	u16 res3;
+	u16 rfmr;
+	u16 res4;
+	u16 rfmmr;
+	u8 res5[3];
+	u8 far;
+	u32 asr;
+	u32 drr1;
+	u32 drr2;
+	u16 res6;
+	u16 specr;
+	u16 res7;
+	u16 ep0sr;
+	u32 iep0cfg;
+	u32 oep0cfg;
+	u32 ep1cfg;
+	u32 ep2cfg;
+	u32 ep3cfg;
+	u32 ep4cfg;
+	u32 ep5cfg;
+	u32 ep6cfg;
+	u32 ep7cfg;
+	u32 ep0ctl;
+	u16 res8;
+	u16 ep1ctl;
+	u16 res9;
+	u16 ep2ctl;
+	u16 res10;
+	u16 ep3ctl;
+	u16 res11;
+	u16 ep4ctl;
+	u16 res12;
+	u16 ep5ctl;
+	u16 res13;
+	u16 ep6ctl;
+	u16 res14;
+	u16 ep7ctl;
+	u32 ep0isr;
+	u16 res15;
+	u16 ep1isr;
+	u16 res16;
+	u16 ep2isr;
+	u16 res17;
+	u16 ep3isr;
+	u16 res18;
+	u16 ep4isr;
+	u16 res19;
+	u16 ep5isr;
+	u16 res20;
+	u16 ep6isr;
+	u16 res21;
+	u16 ep7isr;
+	u32 ep0imr;
+	u16 res22;
+	u16 ep1imr;
+	u16 res23;
+	u16 ep2imr;
+	u16 res24;
+	u16 ep3imr;
+	u16 res25;
+	u16 ep4imr;
+	u16 res26;
+	u16 ep5imr;
+	u16 res27;
+	u16 ep6imr;
+	u16 res28;
+	u16 ep7imr;
+	u32 ep0dr;
+	u32 ep1dr;
+	u32 ep2dr;
+	u32 ep3dr;
+	u32 ep4dr;
+	u32 ep5dr;
+	u32 ep6dr;
+	u32 ep7dr;
+	u16 res29;
+	u16 ep0dpr;
+	u16 res30;
+	u16 ep1dpr;
+	u16 res31;
+	u16 ep2dpr;
+	u16 res32;
+	u16 ep3dpr;
+	u16 res33;
+	u16 ep4dpr;
+	u16 res34;
+	u16 ep5dpr;
+	u16 res35;
+	u16 ep6dpr;
+	u16 res36;
+	u16 ep7dpr;
+	u8 res37[788];
+	u8 cfgram[1024];
+} usb_t;
+
+/* PLL module registers
+ */
+typedef struct pll_ctrl {
+	u32 syncr;
+	u32 synsr;
+} pll_t;
+
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
+#endif /* __IMMAP_5275__ */
diff --git a/arch/m68k/include/asm/immap_5282.h b/arch/m68k/include/asm/immap_5282.h
new file mode 100644
index 0000000..d7c68f5
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5282.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5282 Internal Memory Map
+ *
+ * Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ */
+
+#ifndef __IMMAP_5282__
+#define __IMMAP_5282__
+
+#define MMAP_SCM	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAMC	(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DMA0	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DMA1	(CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DMA2	(CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_DMA3	(CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00000280)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00000300)
+#define MMAP_QSPI	(CONFIG_SYS_MBAR + 0x00000340)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000400)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000440)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00000480)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x000004C0)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000C00)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x00000D00)
+#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00000F00)
+#define MMAP_FEC	(CONFIG_SYS_MBAR + 0x00001000)
+#define MMAP_FECFIFO	(CONFIG_SYS_MBAR + 0x00001400)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00100000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x00110000)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x00120000)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00130000)
+#define MMAP_WDOG	(CONFIG_SYS_MBAR + 0x00140000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00150000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00160000)
+#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00170000)
+#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x00180000)
+#define MMAP_QADC	(CONFIG_SYS_MBAR + 0x00190000)
+#define MMAP_GPTMRA	(CONFIG_SYS_MBAR + 0x001A0000)
+#define MMAP_GPTMRB	(CONFIG_SYS_MBAR + 0x001B0000)
+#define MMAP_CAN	(CONFIG_SYS_MBAR + 0x001C0000)
+#define MMAP_CFMC	(CONFIG_SYS_MBAR + 0x001D0000)
+#define MMAP_CFMMEM	(CONFIG_SYS_MBAR + 0x04000000)
+
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/qspi.h>
+
+/* System Control Module */
+typedef struct scm_ctrl {
+	u32 ipsbar;
+	u32 res1;
+	u32 rambar;
+	u32 res2;
+	u8 crsr;
+	u8 cwcr;
+	u8 lpicr;
+	u8 cwsr;
+	u32 res3;
+	u8 mpark;
+	u8 res4[3];
+	u8 pacr0;
+	u8 pacr1;
+	u8 pacr2;
+	u8 pacr3;
+	u8 pacr4;
+	u8 res5;
+	u8 pacr5;
+	u8 pacr6;
+	u8 pacr7;
+	u8 res6;
+	u8 pacr8;
+	u8 res7;
+	u8 gpacr0;
+	u8 gpacr1;
+	u16 res8;
+} scm_t;
+
+typedef struct canex_ctrl {
+	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
+} canex_t;
+
+/* Clock Module registers */
+typedef struct pll_ctrl {
+	u16 syncr;		/* 0x00 synthesizer control register */
+	u16 synsr;		/* 0x02 synthesizer status register */
+} pll_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+	ushort wcr;
+	ushort wmr;
+	ushort wcntr;
+	ushort wsr;
+} wdog_t;
+
+#endif				/* __IMMAP_5282__ */
diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h
new file mode 100644
index 0000000..29e6086
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5301x.h
@@ -0,0 +1,307 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5301x Internal Memory Map
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __IMMAP_5301X__
+#define __IMMAP_5301X__
+
+#define MMAP_SCM1	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_XBS	(CONFIG_SYS_MBAR + 0x00004000)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00008000)
+#define MMAP_MPU	(CONFIG_SYS_MBAR + 0x00014000)
+#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00030000)
+#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00034000)
+#define MMAP_SCM2	(CONFIG_SYS_MBAR + 0x00040000)
+#define MMAP_EDMA	(CONFIG_SYS_MBAR + 0x00044000)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00048000)
+#define MMAP_INTC1	(CONFIG_SYS_MBAR + 0x0004C000)
+#define MMAP_INTCACK	(CONFIG_SYS_MBAR + 0x00054000)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00058000)
+#define MMAP_DSPI	(CONFIG_SYS_MBAR + 0x0005C000)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00060000)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00064000)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00068000)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00070000)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00074000)
+#define MMAP_DTMR2	(CONFIG_SYS_MBAR + 0x00078000)
+#define MMAP_DTMR3	(CONFIG_SYS_MBAR + 0x0007C000)
+#define MMAP_PIT0	(CONFIG_SYS_MBAR + 0x00080000)
+#define MMAP_PIT1	(CONFIG_SYS_MBAR + 0x00084000)
+#define MMAP_PIT2	(CONFIG_SYS_MBAR + 0x00088000)
+#define MMAP_PIT3	(CONFIG_SYS_MBAR + 0x0008C000)
+#define MMAP_EPORT0	(CONFIG_SYS_MBAR + 0x00090000)
+#define MMAP_EPORT1	(CONFIG_SYS_MBAR + 0x00094000)
+#define MMAP_VOICOD	(CONFIG_SYS_MBAR + 0x0009C000)
+#define MMAP_RCM	(CONFIG_SYS_MBAR + 0x000A0000)
+#define MMAP_CCM	(CONFIG_SYS_MBAR + 0x000A0004)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x000A4000)
+#define MMAP_RTC	(CONFIG_SYS_MBAR + 0x000A8000)
+#define MMAP_SIM	(CONFIG_SYS_MBAR + 0x000AC000)
+#define MMAP_USBOTG	(CONFIG_SYS_MBAR + 0x000B0000)
+#define MMAP_USBH	(CONFIG_SYS_MBAR + 0x000B4000)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x000B8000)
+#define MMAP_SSI	(CONFIG_SYS_MBAR + 0x000BC000)
+#define MMAP_PLL	(CONFIG_SYS_MBAR + 0x000C0000)
+#define MMAP_RNG	(CONFIG_SYS_MBAR + 0x000C4000)
+#define MMAP_IIM	(CONFIG_SYS_MBAR + 0x000C8000)
+#define MMAP_ESDHC	(CONFIG_SYS_MBAR + 0x000CC000)
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/ssi.h>
+#include <asm/coldfire/rng.h>
+#include <asm/rtc.h>
+
+/* System Controller Module */
+typedef struct scm1 {
+	u32 mpr;		/* 0x00 Master Privilege */
+	u32 rsvd1[7];
+	u32 pacra;		/* 0x20 Peripheral Access Ctrl A */
+	u32 pacrb;		/* 0x24 Peripheral Access Ctrl B */
+	u32 pacrc;		/* 0x28 Peripheral Access Ctrl C */
+	u32 pacrd;		/* 0x2C Peripheral Access Ctrl D */
+	u32 rsvd2[4];
+	u32 pacre;		/* 0x40 Peripheral Access Ctrl E */
+	u32 pacrf;		/* 0x44 Peripheral Access Ctrl F */
+	u32 pacrg;		/* 0x48 Peripheral Access Ctrl G */
+} scm1_t;
+
+typedef struct scm2 {
+	u8 rsvd1[19];		/* 0x00 - 0x12 */
+	u8 wcr;			/* 0x13 */
+	u16 rsvd2;		/* 0x14 - 0x15 */
+	u16 cwcr;		/* 0x16 */
+	u8 rsvd3[3];		/* 0x18 - 0x1A */
+	u8 cwsr;		/* 0x1B */
+	u8 rsvd4[3];		/* 0x1C - 0x1E */
+	u8 scmisr;		/* 0x1F */
+	u32 rsvd5;		/* 0x20 - 0x23 */
+	u8 bcr;			/* 0x24 */
+	u8 rsvd6[74];		/* 0x25 - 0x6F */
+	u32 cfadr;		/* 0x70 */
+	u8 rsvd7;		/* 0x74 */
+	u8 cfier;		/* 0x75 */
+	u8 cfloc;		/* 0x76 */
+	u8 cfatr;		/* 0x77 */
+	u32 rsvd8;		/* 0x78 - 0x7B */
+	u32 cfdtr;		/* 0x7C */
+} scm2_t;
+
+/* PWM module */
+typedef struct pwm_ctrl {
+	u8 en;			/* 0x00 PWM Enable */
+	u8 pol;			/* 0x01 Polarity */
+	u8 clk;			/* 0x02 Clock Select */
+	u8 prclk;		/* 0x03 Prescale Clock Select */
+	u8 cae;			/* 0x04 Center Align Enable */
+	u8 ctl;			/* 0x05 Ctrl */
+	u8 res1[2];		/* 0x06 - 0x07 */
+	u8 scla;		/* 0x08 Scale A */
+	u8 sclb;		/* 0x09 Scale B */
+	u8 res2[2];		/* 0x0A - 0x0B */
+	u8 cnt0;		/* 0x0C Channel 0 Counter */
+	u8 cnt1;		/* 0x0D Channel 1 Counter */
+	u8 cnt2;		/* 0x0E Channel 2 Counter */
+	u8 cnt3;		/* 0x0F Channel 3 Counter */
+	u8 cnt4;		/* 0x10 Channel 4 Counter */
+	u8 cnt5;		/* 0x11 Channel 5 Counter */
+	u8 cnt6;		/* 0x12 Channel 6 Counter */
+	u8 cnt7;		/* 0x13 Channel 7 Counter */
+	u8 per0;		/* 0x14 Channel 0 Period */
+	u8 per1;		/* 0x15 Channel 1 Period */
+	u8 per2;		/* 0x16 Channel 2 Period */
+	u8 per3;		/* 0x17 Channel 3 Period */
+	u8 per4;		/* 0x18 Channel 4 Period */
+	u8 per5;		/* 0x19 Channel 5 Period */
+	u8 per6;		/* 0x1A Channel 6 Period */
+	u8 per7;		/* 0x1B Channel 7 Period */
+	u8 dty0;		/* 0x1C Channel 0 Duty */
+	u8 dty1;		/* 0x1D Channel 1 Duty */
+	u8 dty2;		/* 0x1E Channel 2 Duty */
+	u8 dty3;		/* 0x1F Channel 3 Duty */
+	u8 dty4;		/* 0x20 Channel 4 Duty */
+	u8 dty5;		/* 0x21 Channel 5 Duty */
+	u8 dty6;		/* 0x22 Channel 6 Duty */
+	u8 dty7;		/* 0x23 Channel 7 Duty */
+	u8 sdn;			/* 0x24 Shutdown */
+	u8 res3[3];		/* 0x25 - 0x27 */
+} pwm_t;
+
+/* Chip configuration module */
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
+typedef struct ccm_ctrl {
+	u16 ccr;		/* 0x00 Chip Cfg */
+	u16 res1;		/* 0x02 */
+	u16 rcon;		/* 0x04 Reset Cfg */
+	u16 cir;		/* 0x06 Chip ID */
+	u32 res2;		/* 0x08 */
+	u16 misccr;		/* 0x0A Misc Ctrl */
+	u16 cdr;		/* 0x0C Clock divider */
+	u16 uhcsr;		/* 0x10 USB Host status */
+	u16 uocsr;		/* 0x12 USB On-the-Go Status */
+	u16 res3;		/* 0x14 */
+	u16 codeccr;		/* 0x16 Codec Control */
+	u16 misccr2;		/* 0x18 Misc2 Ctrl */
+} ccm_t;
+
+/* GPIO port */
+typedef struct gpio_ctrl {
+	/* Port Output Data */
+	u8 podr_fbctl;		/* 0x00 */
+	u8 podr_be;		/* 0x01 */
+	u8 podr_cs;		/* 0x02 */
+	u8 podr_dspi;		/* 0x03 */
+	u8 res01;		/* 0x04 */
+	u8 podr_fec0;		/* 0x05 */
+	u8 podr_feci2c;		/* 0x06 */
+	u8 res02[2];		/* 0x07 - 0x08 */
+	u8 podr_simp1;		/* 0x09 */
+	u8 podr_simp0;		/* 0x0A */
+	u8 podr_timer;		/* 0x0B */
+	u8 podr_uart;		/* 0x0C */
+	u8 podr_debug;		/* 0x0D */
+	u8 res03;		/* 0x0E */
+	u8 podr_sdhc;		/* 0x0F */
+	u8 podr_ssi;		/* 0x10 */
+	u8 res04[3];		/* 0x11 - 0x13 */
+
+	/* Port Data Direction */
+	u8 pddr_fbctl;		/* 0x14 */
+	u8 pddr_be;		/* 0x15 */
+	u8 pddr_cs;		/* 0x16 */
+	u8 pddr_dspi;		/* 0x17 */
+	u8 res05;		/* 0x18 */
+	u8 pddr_fec0;		/* 0x19 */
+	u8 pddr_feci2c;		/* 0x1A */
+	u8 res06[2];		/* 0x1B - 0x1C */
+	u8 pddr_simp1;		/* 0x1D */
+	u8 pddr_simp0;		/* 0x1E */
+	u8 pddr_timer;		/* 0x1F */
+	u8 pddr_uart;		/* 0x20 */
+	u8 pddr_debug;		/* 0x21 */
+	u8 res07;		/* 0x22 */
+	u8 pddr_sdhc;		/* 0x23 */
+	u8 pddr_ssi;		/* 0x24 */
+	u8 res08[3];		/* 0x25 - 0x27 */
+
+	/* Port Data Direction */
+	u8 ppdr_fbctl;		/* 0x28 */
+	u8 ppdr_be;		/* 0x29 */
+	u8 ppdr_cs;		/* 0x2A */
+	u8 ppdr_dspi;		/* 0x2B */
+	u8 res09;		/* 0x2C */
+	u8 ppdr_fec0;		/* 0x2D */
+	u8 ppdr_feci2c;		/* 0x2E */
+	u8 res10[2];		/* 0x2F - 0x30 */
+	u8 ppdr_simp1;		/* 0x31 */
+	u8 ppdr_simp0;		/* 0x32 */
+	u8 ppdr_timer;		/* 0x33 */
+	u8 ppdr_uart;		/* 0x34 */
+	u8 ppdr_debug;		/* 0x35 */
+	u8 res11;		/* 0x36 */
+	u8 ppdr_sdhc;		/* 0x37 */
+	u8 ppdr_ssi;		/* 0x38 */
+	u8 res12[3];		/* 0x39 - 0x3B */
+
+	/* Port Clear Output Data */
+	u8 pclrr_fbctl;		/* 0x3C */
+	u8 pclrr_be;		/* 0x3D */
+	u8 pclrr_cs;		/* 0x3E */
+	u8 pclrr_dspi;		/* 0x3F */
+	u8 res13;		/* 0x40 */
+	u8 pclrr_fec0;		/* 0x41 */
+	u8 pclrr_feci2c;	/* 0x42 */
+	u8 res14[2];		/* 0x43 - 0x44 */
+	u8 pclrr_simp1;		/* 0x45 */
+	u8 pclrr_simp0;		/* 0x46 */
+	u8 pclrr_timer;		/* 0x47 */
+	u8 pclrr_uart;		/* 0x48 */
+	u8 pclrr_debug;		/* 0x49 */
+	u8 res15;		/* 0x4A */
+	u8 pclrr_sdhc;		/* 0x4B */
+	u8 pclrr_ssi;		/* 0x4C */
+	u8 res16[3];		/* 0x4D - 0x4F */
+
+	/* Pin Assignment */
+	u8 par_fbctl;		/* 0x50 */
+	u8 par_be;		/* 0x51 */
+	u8 par_cs;		/* 0x52 */
+	u8 res17;		/* 0x53 */
+	u8 par_dspih;		/* 0x54 */
+	u8 par_dspil;		/* 0x55 */
+	u8 par_fec;		/* 0x56 */
+	u8 par_feci2c;		/* 0x57 */
+	u8 par_irq0h;		/* 0x58 */
+	u8 par_irq0l;		/* 0x59 */
+	u8 par_irq1h;		/* 0x5A */
+	u8 par_irq1l;		/* 0x5B */
+	u8 par_simp1h;		/* 0x5C */
+	u8 par_simp1l;		/* 0x5D */
+	u8 par_simp0;		/* 0x5E */
+	u8 par_timer;		/* 0x5F */
+	u8 par_uart;		/* 0x60 */
+	u8 res18;		/* 0x61 */
+	u8 par_debug;		/* 0x62 */
+	u8 par_sdhc;		/* 0x63 */
+	u8 par_ssih;		/* 0x64 */
+	u8 par_ssil;		/* 0x65 */
+	u8 res19[2];		/* 0x66 - 0x67 */
+
+	/* Mode Select Control */
+	/* Drive Strength Control */
+	u8 mscr_mscr1;		/* 0x68 */
+	u8 mscr_mscr2;		/* 0x69 */
+	u8 mscr_mscr3;		/* 0x6A */
+	u8 mscr_mscr45;		/* 0x6B */
+	u8 srcr_dspi;		/* 0x6C */
+	u8 dscr_fec;		/* 0x6D */
+	u8 srcr_i2c;		/* 0x6E */
+	u8 srcr_irq;		/* 0x6F */
+
+	u8 srcr_sim;		/* 0x70 */
+	u8 srcr_timer;		/* 0x71 */
+	u8 srcr_uart;		/* 0x72 */
+	u8 res20;		/* 0x73 */
+	u8 srcr_sdhc;		/* 0x74 */
+	u8 srcr_ssi;		/* 0x75 */
+	u8 res21[2];		/* 0x76 - 0x77 */
+	u8 pcr_pcrh;		/* 0x78 */
+	u8 pcr_pcrl;		/* 0x79 */
+} gpio_t;
+
+/* SDRAM controller */
+typedef struct sdram_ctrl {
+	u32 mode;		/* 0x00 Mode/Extended Mode */
+	u32 ctrl;		/* 0x04 Ctrl */
+	u32 cfg1;		/* 0x08 Cfg 1 */
+	u32 cfg2;		/* 0x0C Cfg 2 */
+	u32 res1[64];		/* 0x10 - 0x10F */
+	u32 cs0;		/* 0x110 Chip Select 0 Cfg */
+	u32 cs1;		/* 0x114 Chip Select 1 Cfg */
+} sdram_t;
+
+/* Clock Module */
+typedef struct pll_ctrl {
+	u32 pcr;		/* 0x00 Ctrl */
+	u32 pdr;		/* 0x04 Divider */
+	u32 psr;		/* 0x08 Status */
+} pll_t;
+
+typedef struct rtcex {
+	u32 rsvd1[3];
+	u32 gocu;
+	u32 gocl;
+} rtcex_t;
+#endif				/* __IMMAP_5301X__ */
diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h
new file mode 100644
index 0000000..e041e7e
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5307.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+ *
+ */
+
+#ifndef __IMMAP_5307__
+#define __IMMAP_5307__
+
+#define MMAP_SIM	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_INTC	(CONFIG_SYS_MBAR + 0x00000040)
+#define MMAP_CSM	(CONFIG_SYS_MBAR + 0x00000080)
+#define MMAP_DRAMC	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_DTMR0	(CONFIG_SYS_MBAR + 0x00000140)
+#define MMAP_DTMR1	(CONFIG_SYS_MBAR + 0x00000180)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x000001C0)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00000200)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00000244)
+
+typedef struct sim {
+	u8  rsr;
+	u8  sypcr;
+	u8  swivr;
+	u8  swsr;
+	u16 par;
+	u8  irqpar;
+	u8  res1;
+	u8  pllcr;
+	u8  res2;
+	u16 res3;
+	u8  mpark;
+	u8  res4;
+	u16 res5;
+	u32 res6;
+} sim_t;
+
+typedef struct intctrl {
+	u32 ipr;
+	u32 imr;
+	u16 res7;
+	u8  res8;
+	u8  avr;
+	u8  icr0;
+	u8  icr1;
+	u8  icr2;
+	u8  icr3;
+	u8  icr4;
+	u8  icr5;
+	u8  icr6;
+	u8  icr7;
+	u8  icr8;
+	u8  icr9;
+	u16 res9;
+} intctrl_t;
+
+typedef struct csm {
+	u16 csar0;      /* Chip-select Address */
+	u16 res1;
+	u32 csmr0;      /* Chip-select Mask */
+	u16 res2;
+	u16 cscr0;      /* Chip-select Control */
+	u16 csar1;
+	u16 res3;
+	u32 csmr1;
+	u16 res4;
+	u16 cscr1;
+	u16 csar2;
+	u16 res5;
+	u32 csmr2;
+	u16 res6;
+	u16 cscr2;
+	u16 csar3;
+	u16 res7;
+	u32 csmr3;
+	u16 res8;
+	u16 cscr3;
+	u16 csar4;
+	u16 res9;
+	u32 csmr4;
+	u16 res10;
+	u16 cscr4;
+	u16 csar5;
+	u16 res11;
+	u32 csmr5;
+	u16 res12;
+	u16 cscr5;
+	u16 csar6;
+	u16 res13;
+	u32 csmr6;
+	u16 res14;
+	u16 cscr6;
+	u16 csar7;
+	u16 res15;
+	u32 csmr7;
+	u16 res16;
+	u16 cscr7;
+} csm_t;
+
+typedef struct sdramctrl {
+	u16 dcr;
+	u16 res1;
+	u32 res2;
+	u32 dacr0;
+	u32 dmr0;
+	u32 dacr1;
+	u32 dmr1;
+} sdramctrl_t;
+
+typedef struct gpio {
+	u16 paddr;
+	u16 res1;
+	u16 padat;
+	u16 res2;
+} gpio_t;
+
+#endif				/* __IMMAP_5307__ */
+
diff --git a/arch/m68k/include/asm/immap_5329.h b/arch/m68k/include/asm/immap_5329.h
new file mode 100644
index 0000000..dbf3a22
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5329.h
@@ -0,0 +1,385 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5329 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __IMMAP_5329__
+#define __IMMAP_5329__
+
+#define MMAP_SCM1	0xEC000000
+#define MMAP_MDHA	0xEC080000
+#define MMAP_SKHA	0xEC084000
+#define MMAP_RNG	0xEC088000
+#define MMAP_SCM2	0xFC000000
+#define MMAP_XBS	0xFC004000
+#define MMAP_FBCS	0xFC008000
+#define MMAP_CAN	0xFC020000
+#define MMAP_FEC	0xFC030000
+#define MMAP_SCM3	0xFC040000
+#define MMAP_EDMA	0xFC044000
+#define MMAP_TCD	0xFC045000
+#define MMAP_INTC0	0xFC048000
+#define MMAP_INTC1	0xFC04C000
+#define MMAP_INTCACK	0xFC054000
+#define MMAP_I2C	0xFC058000
+#define MMAP_QSPI	0xFC05C000
+#define MMAP_UART0	0xFC060000
+#define MMAP_UART1	0xFC064000
+#define MMAP_UART2	0xFC068000
+#define MMAP_DTMR0	0xFC070000
+#define MMAP_DTMR1	0xFC074000
+#define MMAP_DTMR2	0xFC078000
+#define MMAP_DTMR3	0xFC07C000
+#define MMAP_PIT0	0xFC080000
+#define MMAP_PIT1	0xFC084000
+#define MMAP_PIT2	0xFC088000
+#define MMAP_PIT3	0xFC08C000
+#define MMAP_PWM	0xFC090000
+#define MMAP_EPORT	0xFC094000
+#define MMAP_WDOG	0xFC098000
+#define MMAP_RCM	0xFC0A0000
+#define MMAP_CCM	0xFC0A0004
+#define MMAP_GPIO	0xFC0A4000
+#define MMAP_RTC	0xFC0A8000
+#define MMAP_LCDC	0xFC0AC000
+#define MMAP_USBOTG	0xFC0B0000
+#define MMAP_USBH	0xFC0B4000
+#define MMAP_SDRAM	0xFC0B8000
+#define MMAP_SSI	0xFC0BC000
+#define MMAP_PLL	0xFC0C0000
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/qspi.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/lcd.h>
+#include <asm/coldfire/mdha.h>
+#include <asm/coldfire/pwm.h>
+#include <asm/coldfire/ssi.h>
+#include <asm/coldfire/skha.h>
+
+/* System control module registers */
+typedef struct scm1_ctrl {
+	u32 mpr0;		/* 0x00 Master Privilege Register 0 */
+	u32 res1[15];		/* 0x04 - 0x3F */
+	u32 pacrh;		/* 0x40 Peripheral Access Control Register H */
+	u32 res2[3];		/* 0x44 - 0x53 */
+	u32 bmt0;		/*0x54 Bus Monitor Timeout 0 */
+} scm1_t;
+
+/* System control module registers 2 */
+typedef struct scm2_ctrl {
+	u32 mpr1;		/* 0x00 Master Privilege Register */
+	u32 res1[7];		/* 0x04 - 0x1F */
+	u32 pacra;		/* 0x20 Peripheral Access Control Register A */
+	u32 pacrb;		/* 0x24 Peripheral Access Control Register B */
+	u32 pacrc;		/* 0x28 Peripheral Access Control Register C */
+	u32 pacrd;		/* 0x2C Peripheral Access Control Register D */
+	u32 res2[4];		/* 0x30 - 0x3F */
+	u32 pacre;		/* 0x40 Peripheral Access Control Register E */
+	u32 pacrf;		/* 0x44 Peripheral Access Control Register F */
+	u32 pacrg;		/* 0x48 Peripheral Access Control Register G */
+	u32 res3[2];		/* 0x4C - 0x53 */
+	u32 bmt1;		/* 0x54 Bus Monitor Timeout 1 */
+} scm2_t;
+
+/* System Control Module register 3 */
+typedef struct scm3_ctrl {
+	u8 res1[19];		/* 0x00 - 0x12 */
+	u8 wcr;			/* 0x13 wakeup control register */
+	u16 res2;		/* 0x14 - 0x15 */
+	u16 cwcr;		/* 0x16 Core Watchdog Control Register */
+	u8 res3[3];		/* 0x18 - 0x1A */
+	u8 cwsr;		/* 0x1B Core Watchdog Service Register */
+	u8 res4[2];		/* 0x1C - 0x1D */
+	u8 scmisr;		/* 0x1F Interrupt Status Register */
+	u32 res5;		/* 0x20 */
+	u32 bcr;		/* 0x24 Burst Configuration Register */
+	u32 res6[18];		/* 0x28 - 0x6F */
+	u32 cfadr;		/* 0x70 Core Fault Address Register */
+	u8 res7[4];		/* 0x71 - 0x74 */
+	u8 cfier;		/* 0x75 Core Fault Interrupt Enable Register */
+	u8 cfloc;		/* 0x76 Core Fault Location Register */
+	u8 cfatr;		/* 0x77 Core Fault Attributes Register */
+	u32 res8;		/* 0x78 */
+	u32 cfdtr;		/* 0x7C Core Fault Data Register */
+} scm3_t;
+
+typedef struct canex_ctrl {
+	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
+} canex_t;
+
+/* Watchdog registers */
+typedef struct wdog_ctrl {
+	u16 cr;			/* 0x00 Control register */
+	u16 mr;			/* 0x02 Modulus register */
+	u16 cntr;		/* 0x04 Count register */
+	u16 sr;			/* 0x06 Service register */
+} wdog_t;
+
+/*Chip configuration module registers */
+typedef struct ccm_ctrl {
+	u16 ccr;		/* 0x00 Chip configuration register */
+	u16 res2;		/* 0x02 */
+	u16 rcon;		/* 0x04 Rreset configuration register */
+	u16 cir;		/* 0x06 Chip identification register */
+	u32 res3;		/* 0x08 */
+	u16 misccr;		/* 0x0A Miscellaneous control register */
+	u16 cdr;		/* 0x0C Clock divider register */
+	u16 uhcsr;		/* 0x10 USB Host controller status register */
+	u16 uocsr;		/* 0x12 USB On-the-Go Controller Status Reg */
+} ccm_t;
+
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
+/* GPIO port registers */
+typedef struct gpio_ctrl {
+	/* Port Output Data Registers */
+#ifdef CONFIG_M5329
+	u8 podr_fech;		/* 0x00 */
+	u8 podr_fecl;		/* 0x01 */
+#else
+	u16 res00;		/* 0x00 - 0x01 */
+#endif
+	u8 podr_ssi;		/* 0x02 */
+	u8 podr_busctl;		/* 0x03 */
+	u8 podr_be;		/* 0x04 */
+	u8 podr_cs;		/* 0x05 */
+	u8 podr_pwm;		/* 0x06 */
+	u8 podr_feci2c;		/* 0x07 */
+	u8 res08;		/* 0x08 */
+	u8 podr_uart;		/* 0x09 */
+	u8 podr_qspi;		/* 0x0A */
+	u8 podr_timer;		/* 0x0B */
+#ifdef CONFIG_M5329
+	u8 res0C;		/* 0x0C */
+	u8 podr_lcddatah;	/* 0x0D */
+	u8 podr_lcddatam;	/* 0x0E */
+	u8 podr_lcddatal;	/* 0x0F */
+	u8 podr_lcdctlh;	/* 0x10 */
+	u8 podr_lcdctll;	/* 0x11 */
+#else
+	u16 res0C;		/* 0x0C - 0x0D */
+	u8 podr_fech;		/* 0x0E */
+	u8 podr_fecl;		/* 0x0F */
+	u16 res10[3];		/* 0x10 - 0x15 */
+#endif
+
+	/* Port Data Direction Registers */
+#ifdef CONFIG_M5329
+	u16 res12;		/* 0x12 - 0x13 */
+	u8 pddr_fech;		/* 0x14 */
+	u8 pddr_fecl;		/* 0x15 */
+#endif
+	u8 pddr_ssi;		/* 0x16 */
+	u8 pddr_busctl;		/* 0x17 */
+	u8 pddr_be;		/* 0x18 */
+	u8 pddr_cs;		/* 0x19 */
+	u8 pddr_pwm;		/* 0x1A */
+	u8 pddr_feci2c;		/* 0x1B */
+	u8 res1C;		/* 0x1C */
+	u8 pddr_uart;		/* 0x1D */
+	u8 pddr_qspi;		/* 0x1E */
+	u8 pddr_timer;		/* 0x1F */
+#ifdef CONFIG_M5329
+	u8 res20;		/* 0x20 */
+	u8 pddr_lcddatah;	/* 0x21 */
+	u8 pddr_lcddatam;	/* 0x22 */
+	u8 pddr_lcddatal;	/* 0x23 */
+	u8 pddr_lcdctlh;	/* 0x24 */
+	u8 pddr_lcdctll;	/* 0x25 */
+	u16 res26;		/* 0x26 - 0x27 */
+#else
+	u16 res20;		/* 0x20 - 0x21 */
+	u8 pddr_fech;		/* 0x22 */
+	u8 pddr_fecl;		/* 0x23 */
+	u16 res24[3];		/* 0x24 - 0x29 */
+#endif
+
+	/* Port Data Direction Registers */
+#ifdef CONFIG_M5329
+	u8 ppd_fech;		/* 0x28 */
+	u8 ppd_fecl;		/* 0x29 */
+#endif
+	u8 ppd_ssi;		/* 0x2A */
+	u8 ppd_busctl;		/* 0x2B */
+	u8 ppd_be;		/* 0x2C */
+	u8 ppd_cs;		/* 0x2D */
+	u8 ppd_pwm;		/* 0x2E */
+	u8 ppd_feci2c;		/* 0x2F */
+	u8 res30;		/* 0x30 */
+	u8 ppd_uart;		/* 0x31 */
+	u8 ppd_qspi;		/* 0x32 */
+	u8 ppd_timer;		/* 0x33 */
+#ifdef CONFIG_M5329
+	u8 res34;		/* 0x34 */
+	u8 ppd_lcddatah;	/* 0x35 */
+	u8 ppd_lcddatam;	/* 0x36 */
+	u8 ppd_lcddatal;	/* 0x37 */
+	u8 ppd_lcdctlh;		/* 0x38 */
+	u8 ppd_lcdctll;		/* 0x39 */
+	u16 res3A;		/* 0x3A - 0x3B */
+#else
+	u16 res34;		/* 0x34 - 0x35 */
+	u8 ppd_fech;		/* 0x36 */
+	u8 ppd_fecl;		/* 0x37 */
+	u16 res38[3];		/* 0x38 - 0x3D */
+#endif
+
+	/* Port Clear Output Data Registers */
+#ifdef CONFIG_M5329
+	u8 res3C;		/* 0x3C */
+	u8 pclrr_fech;		/* 0x3D */
+	u8 pclrr_fecl;		/* 0x3E */
+#else
+	u8 pclrr_ssi;		/* 0x3E */
+#endif
+	u8 pclrr_busctl;	/* 0x3F */
+	u8 pclrr_be;		/* 0x40 */
+	u8 pclrr_cs;		/* 0x41 */
+	u8 pclrr_pwm;		/* 0x42 */
+	u8 pclrr_feci2c;	/* 0x43 */
+	u8 res44;		/* 0x44 */
+	u8 pclrr_uart;		/* 0x45 */
+	u8 pclrr_qspi;		/* 0x46 */
+	u8 pclrr_timer;		/* 0x47 */
+#ifdef CONFIG_M5329
+	u8 pclrr_lcddatah;	/* 0x48 */
+	u8 pclrr_lcddatam;	/* 0x49 */
+	u8 pclrr_lcddatal;	/* 0x4A */
+	u8 pclrr_ssi;		/* 0x4B */
+	u8 pclrr_lcdctlh;	/* 0x4C */
+	u8 pclrr_lcdctll;	/* 0x4D */
+	u16 res4E;		/* 0x4E - 0x4F */
+#else
+	u16 res48;		/* 0x48 - 0x49 */
+	u8 pclrr_fech;		/* 0x4A */
+	u8 pclrr_fecl;		/* 0x4B */
+	u8 res4C[5];		/* 0x4C - 0x50 */
+#endif
+
+	/* Pin Assignment Registers */
+#ifdef CONFIG_M5329
+	u8 par_fec;		/* 0x50 */
+#endif
+	u8 par_pwm;		/* 0x51 */
+	u8 par_busctl;		/* 0x52 */
+	u8 par_feci2c;		/* 0x53 */
+	u8 par_be;		/* 0x54 */
+	u8 par_cs;		/* 0x55 */
+	u16 par_ssi;		/* 0x56 */
+	u16 par_uart;		/* 0x58 */
+	u16 par_qspi;		/* 0x5A */
+	u8 par_timer;		/* 0x5C */
+#ifdef CONFIG_M5329
+	u8 par_lcddata;		/* 0x5D */
+	u16 par_lcdctl;		/* 0x5E */
+#else
+	u8 par_fec;		/* 0x5D */
+	u16 res5E;		/* 0x5E - 0x5F */
+#endif
+	u16 par_irq;		/* 0x60 */
+	u16 res62;		/* 0x62 - 0x63 */
+
+	/* Mode Select Control Registers */
+	u8 mscr_flexbus;	/* 0x64 */
+	u8 mscr_sdram;		/* 0x65 */
+	u16 res66;		/* 0x66 - 0x67 */
+
+	/* Drive Strength Control Registers */
+	u8 dscr_i2c;		/* 0x68 */
+	u8 dscr_pwm;		/* 0x69 */
+	u8 dscr_fec;		/* 0x6A */
+	u8 dscr_uart;		/* 0x6B */
+	u8 dscr_qspi;		/* 0x6C */
+	u8 dscr_timer;		/* 0x6D */
+	u8 dscr_ssi;		/* 0x6E */
+#ifdef CONFIG_M5329
+	u8 dscr_lcd;		/* 0x6F */
+#else
+	u8 res6F;		/* 0x6F */
+#endif
+	u8 dscr_debug;		/* 0x70 */
+	u8 dscr_clkrst;		/* 0x71 */
+	u8 dscr_irq;		/* 0x72 */
+} gpio_t;
+
+/* USB OTG module registers */
+typedef struct usb_otg {
+	u32 id;			/* 0x000 Identification Register */
+	u32 hwgeneral;		/* 0x004 General HW Parameters */
+	u32 hwhost;		/* 0x008 Host HW Parameters */
+	u32 hwdev;		/* 0x00C Device HW parameters */
+	u32 hwtxbuf;		/* 0x010 TX Buffer HW Parameters */
+	u32 hwrxbuf;		/* 0x014 RX Buffer HW Parameters */
+	u32 res1[58];		/* 0x18 - 0xFF */
+	u8 caplength;		/* 0x100 Capability Register Length */
+	u8 res2;		/* 0x101 */
+	u16 hciver;		/* 0x102 Host Interface Version Number */
+	u32 hcsparams;		/* 0x104 Host Structural Parameters */
+	u32 hccparams;		/* 0x108 Host Capability Parameters */
+	u32 res3[5];		/* 0x10C - 0x11F */
+	u16 dciver;		/* 0x120 Device Interface Version Number */
+	u16 res4;		/* 0x122 */
+	u32 dccparams;		/* 0x124 Device Capability Parameters */
+	u32 res5[6];		/* 0x128 - 0x13F */
+	u32 cmd;		/* 0x140 USB Command */
+	u32 sts;		/* 0x144 USB Status */
+	u32 intr;		/* 0x148 USB Interrupt Enable */
+	u32 frindex;		/* 0x14C USB Frame Index */
+	u32 res6;		/* 0x150 */
+	u32 prd_dev;		/* 0x154 Periodic Frame List Base or Device Address */
+	u32 aync_ep;		/* 0x158 Current Asynchronous List or Address at Endpoint List Address */
+	u32 ttctrl;		/* 0x15C Host TT Asynchronous Buffer Control */
+	u32 burstsize;		/* 0x160 Master Interface Data Burst Size */
+	u32 txfill;		/* 0x164 Host Transmit FIFO Tuning Control */
+	u32 res7[6];		/* 0x168 - 0x17F */
+	u32 cfgflag;		/* 0x180 Configure Flag Register */
+	u32 portsc1;		/* 0x184 Port Status/Control */
+	u32 res8[7];		/* 0x188 - 0x1A3 */
+	u32 otgsc;		/* 0x1A4 On The Go Status and Control */
+	u32 mode;		/* 0x1A8 USB mode register */
+	u32 eptsetstat;		/* 0x1AC Endpoint Setup status */
+	u32 eptprime;		/* 0x1B0 Endpoint initialization */
+	u32 eptflush;		/* 0x1B4 Endpoint de-initialize */
+	u32 eptstat;		/* 0x1B8 Endpoint status */
+	u32 eptcomplete;	/* 0x1BC Endpoint Complete */
+	u32 eptctrl0;		/* 0x1C0 Endpoint control 0 */
+	u32 eptctrl1;		/* 0x1C4 Endpoint control 1 */
+	u32 eptctrl2;		/* 0x1C8 Endpoint control 2 */
+	u32 eptctrl3;		/* 0x1CC Endpoint control 3 */
+} usbotg_t;
+
+/* SDRAM controller registers */
+typedef struct sdram_ctrl {
+	u32 mode;		/* 0x00 Mode/Extended Mode register */
+	u32 ctrl;		/* 0x04 Control register */
+	u32 cfg1;		/* 0x08 Configuration register 1 */
+	u32 cfg2;		/* 0x0C Configuration register 2 */
+	u32 res1[64];		/* 0x10 - 0x10F */
+	u32 cs0;		/* 0x110 Chip Select 0 Configuration */
+	u32 cs1;		/* 0x114 Chip Select 1 Configuration */
+} sdram_t;
+
+/* Clock Module registers */
+typedef struct pll_ctrl {
+	u8 podr;		/* 0x00 Output Divider Register */
+	u8 res1[3];
+	u8 pcr;			/* 0x04 Control Register */
+	u8 res2[3];
+	u8 pmdr;		/* 0x08 Modulation Divider Register */
+	u8 res3[3];
+	u8 pfdr;		/* 0x0C Feedback Divider Register */
+	u8 res4[3];
+} pll_t;
+
+#endif				/* __IMMAP_5329__ */
diff --git a/arch/m68k/include/asm/immap_5441x.h b/arch/m68k/include/asm/immap_5441x.h
new file mode 100644
index 0000000..708d0db
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5441x.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5441x Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __IMMAP_5441X__
+#define __IMMAP_5441X__
+
+/* Module Base Addresses */
+#define MMAP_XBS	0xFC004000
+#define MMAP_FBCS	0xFC008000
+#define MMAP_CAN0	0xFC020000
+#define MMAP_CAN1	0xFC024000
+#define MMAP_I2C1	0xFC038000
+#define MMAP_DSPI1	0xFC03C000
+#define MMAP_SCM	0xFC040000
+#define MMAP_PM		0xFC04002C
+#define MMAP_EDMA	0xFC044000
+#define MMAP_INTC0	0xFC048000
+#define MMAP_INTC1	0xFC04C000
+#define MMAP_INTC2	0xFC050000
+#define MMAP_IACK	0xFC054000
+#define MMAP_I2C0	0xFC058000
+#define MMAP_DSPI0	0xFC05C000
+#define MMAP_UART0	0xFC060000
+#define MMAP_UART1	0xFC064000
+#define MMAP_UART2	0xFC068000
+#define MMAP_UART3	0xFC06C000
+#define MMAP_DTMR0	0xFC070000
+#define MMAP_DTMR1	0xFC074000
+#define MMAP_DTMR2	0xFC078000
+#define MMAP_DTMR3	0xFC07C000
+#define MMAP_PIT0	0xFC080000
+#define MMAP_PIT1	0xFC084000
+#define MMAP_PIT2	0xFC088000
+#define MMAP_PIT3	0xFC08C000
+#define MMAP_EPORT0	0xFC090000
+#define MMAP_ADC	0xFC094000
+#define MMAP_DAC0	0xFC098000
+#define MMAP_DAC1	0xFC09C000
+#define MMAP_RRTC	0xFC0A8000
+#define MMAP_SIM	0xFC0AC000
+#define MMAP_USBOTG	0xFC0B0000
+#define MMAP_USBEHCI	0xFC0B4000
+#define MMAP_SDRAM	0xFC0B8000
+#define MMAP_SSI0	0xFC0BC000
+#define MMAP_PLL	0xFC0C0000
+#define MMAP_RNG	0xFC0C4000
+#define MMAP_SSI1	0xFC0C8000
+#define MMAP_ESDHC	0xFC0CC000
+#define MMAP_FEC0	0xFC0D4000
+#define MMAP_FEC1	0xFC0D8000
+#define MMAP_L2_SW0	0xFC0DC000
+#define MMAP_L2_SW1	0xFC0E0000
+
+#define MMAP_NFC_RAM	0xFC0FC000
+#define MMAP_NFC	0xFC0FF000
+
+#define MMAP_1WIRE	0xEC008000
+#define MMAP_I2C2	0xEC010000
+#define MMAP_I2C3	0xEC014000
+#define MMAP_I2C4	0xEC018000
+#define MMAP_I2C5	0xEC01C000
+#define MMAP_DSPI2	0xEC038000
+#define MMAP_DSPI3	0xEC03C000
+#define MMAP_UART4	0xEC060000
+#define MMAP_UART5	0xEC064000
+#define MMAP_UART6	0xEC068000
+#define MMAP_UART7	0xEC06C000
+#define MMAP_UART8	0xEC070000
+#define MMAP_UART9	0xEC074000
+#define MMAP_RCM	0xEC090000
+#define MMAP_CCM	0xEC090000
+#define MMAP_GPIO	0xEC094000
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/ssi.h>
+
+/* Serial Boot Facility (SBF) */
+typedef struct sbf {
+	u8 resv0[0x18];
+	u16 sbfsr;		/* Serial Boot Facility Status */
+	u8 resv1[0x6];
+	u16 sbfcr;		/* Serial Boot Facility Control */
+} sbf_t;
+
+/* Reset Controller Module (RCM) */
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
+/* Chip Configuration Module (CCM) */
+typedef struct ccm {
+	u8 ccm_resv0[0x4];	/* 0x00 */
+	u16 ccr;		/* 0x04 Chip Configuration */
+	u8 resv1[0x2];		/* 0x06 */
+	u16 rcon;		/* 0x08 Reset Configuration */
+	u16 cir;		/* 0x0A Chip Identification */
+	u8 resv2[0x2];		/* 0x0C */
+	u16 misccr;		/* 0x0E Miscellaneous Control */
+	u16 cdrh;		/* 0x10 Clock Divider */
+	u16 cdrl;		/* 0x12 Clock Divider */
+	u16 uocsr;		/* 0x14 USB On-the-Go Controller Status */
+	u16 uhcsr;		/* 0x16 */
+	u16 misccr3;		/* 0x18 */
+	u16 misccr2;		/* 0x1A */
+	u16 adctsr;		/* 0x1C */
+	u16 dactsr;		/* 0x1E */
+	u16 sbfsr;		/* 0x20 */
+	u16 sbfcr;		/* 0x22 */
+	u32 fnacr;		/* 0x24 */
+} ccm_t;
+
+/* General Purpose I/O Module (GPIO) */
+typedef struct gpio {
+	u8 podr_a;		/* 0x00 */
+	u8 podr_b;		/* 0x01 */
+	u8 podr_c;		/* 0x02 */
+	u8 podr_d;		/* 0x03 */
+	u8 podr_e;		/* 0x04 */
+	u8 podr_f;		/* 0x05 */
+	u8 podr_g;		/* 0x06 */
+	u8 podr_h;		/* 0x07 */
+	u8 podr_i;		/* 0x08 */
+	u8 podr_j;		/* 0x09 */
+	u8 podr_k;		/* 0x0A */
+	u8 rsvd0;		/* 0x0B */
+
+	u8 pddr_a;		/* 0x0C */
+	u8 pddr_b;		/* 0x0D */
+	u8 pddr_c;		/* 0x0E */
+	u8 pddr_d;		/* 0x0F */
+	u8 pddr_e;		/* 0x10 */
+	u8 pddr_f;		/* 0x11 */
+	u8 pddr_g;		/* 0x12 */
+	u8 pddr_h;		/* 0x13 */
+	u8 pddr_i;		/* 0x14 */
+	u8 pddr_j;		/* 0x15 */
+	u8 pddr_k;		/* 0x16 */
+	u8 rsvd1;		/* 0x17 */
+
+	u8 ppdsdr_a;		/* 0x18 */
+	u8 ppdsdr_b;		/* 0x19 */
+	u8 ppdsdr_c;		/* 0x1A */
+	u8 ppdsdr_d;		/* 0x1B */
+	u8 ppdsdr_e;		/* 0x1C */
+	u8 ppdsdr_f;		/* 0x1D */
+	u8 ppdsdr_g;		/* 0x1E */
+	u8 ppdsdr_h;		/* 0x1F */
+	u8 ppdsdr_i;		/* 0x20 */
+	u8 ppdsdr_j;		/* 0x21 */
+	u8 ppdsdr_k;		/* 0x22 */
+	u8 rsvd2;		/* 0x23 */
+
+	u8 pclrr_a;		/* 0x24 */
+	u8 pclrr_b;		/* 0x25 */
+	u8 pclrr_c;		/* 0x26 */
+	u8 pclrr_d;		/* 0x27 */
+	u8 pclrr_e;		/* 0x28 */
+	u8 pclrr_f;		/* 0x29 */
+	u8 pclrr_g;		/* 0x2A */
+	u8 pclrr_h;		/* 0x2B */
+	u8 pclrr_i;		/* 0x2C */
+	u8 pclrr_j;		/* 0x2D */
+	u8 pclrr_k;		/* 0x2E */
+	u8 rsvd3;		/* 0x2F */
+
+	u16 pcr_a;		/* 0x30 */
+	u16 pcr_b;		/* 0x32 */
+	u16 pcr_c;		/* 0x34 */
+	u16 pcr_d;		/* 0x36 */
+	u16 pcr_e;		/* 0x38 */
+	u16 pcr_f;		/* 0x3A */
+	u16 pcr_g;		/* 0x3C */
+	u16 pcr_h;		/* 0x3E */
+	u16 pcr_i;		/* 0x40 */
+	u16 pcr_j;		/* 0x42 */
+	u16 pcr_k;		/* 0x44 */
+	u16 rsvd4;		/* 0x46 */
+
+	u8 par_fbctl;		/* 0x48 */
+	u8 par_be;		/* 0x49 */
+	u8 par_cs;		/* 0x4A */
+	u8 par_cani2c;		/* 0x4B */
+	u8 par_irqh;		/* 0x4C */
+	u8 par_irql;		/* 0x4D */
+	u8 par_dspi0;		/* 0x4E */
+	u8 par_dspiow;		/* 0x4F */
+	u8 par_timer;		/* 0x50 */
+	u8 par_uart2;		/* 0x51 */
+	u8 par_uart1;		/* 0x52 */
+	u8 par_uart0;		/* 0x53 */
+	u8 par_sdhch;		/* 0x54 */
+	u8 par_sdhcl;		/* 0x55 */
+	u8 par_simp0h;		/* 0x56 */
+	u8 par_simp1h;		/* 0x57 */
+	u8 par_ssi0h;		/* 0x58 */
+	u8 par_ssi0l;		/* 0x59 */
+	u8 par_dbg1h;		/* 0x5A */
+	u8 par_dbg0h;		/* 0x5B */
+	u8 par_dbgl;		/* 0x5C */
+	u8 rsvd5;		/* 0x5D */
+	u8 par_fec;		/* 0x5E */
+	u8 rsvd6;		/* 0x5F */
+
+	u8 mscr_sdram;		/* 0x60 */
+	u8 rsvd7[3];		/* 0x61-0x63 */
+
+	u8 srcr_fb1;		/* 0x64 */
+	u8 srcr_fb2;		/* 0x65 */
+	u8 srcr_fb3;		/* 0x66 */
+	u8 srcr_fb4;		/* 0x67 */
+	u8 srcr_dspiow;		/* 0x68 */
+	u8 srcr_cani2c;		/* 0x69 */
+	u8 srcr_irq;		/* 0x6A */
+	u8 srcr_timer;		/* 0x6B */
+	u8 srcr_uart;		/* 0x6C */
+	u8 srcr_fec;		/* 0x6D */
+	u8 srcr_sdhc;		/* 0x6E */
+	u8 srcr_simp0;		/* 0x6F */
+	u8 srcr_ssi0;		/* 0x70 */
+	u8 rsvd8[3];		/* 0x71-0x73 */
+
+	u16 urts_pol;		/* 0x74 */
+	u16 ucts_pol;		/* 0x76 */
+	u16 utxd_wom;		/* 0x78 */
+	u32 urxd_wom;		/* 0x7c */
+
+	u32 hcr1;		/* 0x80 */
+	u32 hcr0;		/* 0x84 */
+} gpio_t;
+
+/* SDRAM Controller (SDRAMC) */
+typedef struct sdramc {
+	u32 cr00;		/* 0x00 */
+	u32 cr01;		/* 0x04 */
+	u32 cr02;		/* 0x08 */
+	u32 cr03;		/* 0x0C */
+	u32 cr04;		/* 0x10 */
+	u32 cr05;		/* 0x14 */
+	u32 cr06;		/* 0x18 */
+	u32 cr07;		/* 0x1C */
+
+	u32 cr08;		/* 0x20 */
+	u32 cr09;		/* 0x24 */
+	u32 cr10;		/* 0x28 */
+	u32 cr11;		/* 0x2C */
+	u32 cr12;		/* 0x30 */
+	u32 cr13;		/* 0x34 */
+	u32 cr14;		/* 0x38 */
+	u32 cr15;		/* 0x3C */
+
+	u32 cr16;		/* 0x40 */
+	u32 cr17;		/* 0x44 */
+	u32 cr18;		/* 0x48 */
+	u32 cr19;		/* 0x4C */
+	u32 cr20;		/* 0x50 */
+	u32 cr21;		/* 0x54 */
+	u32 cr22;		/* 0x58 */
+	u32 cr23;		/* 0x5C */
+
+	u32 cr24;		/* 0x60 */
+	u32 cr25;		/* 0x64 */
+	u32 cr26;		/* 0x68 */
+	u32 cr27;		/* 0x6C */
+	u32 cr28;		/* 0x70 */
+	u32 cr29;		/* 0x74 */
+	u32 cr30;		/* 0x78 */
+	u32 cr31;		/* 0x7C */
+
+	u32 cr32;		/* 0x80 */
+	u32 cr33;		/* 0x84 */
+	u32 cr34;		/* 0x88 */
+	u32 cr35;		/* 0x8C */
+	u32 cr36;		/* 0x90 */
+	u32 cr37;		/* 0x94 */
+	u32 cr38;		/* 0x98 */
+	u32 cr39;		/* 0x9C */
+
+	u32 cr40;		/* 0xA0 */
+	u32 cr41;		/* 0xA4 */
+	u32 cr42;		/* 0xA8 */
+	u32 cr43;		/* 0xAC */
+	u32 cr44;		/* 0xB0 */
+	u32 cr45;		/* 0xB4 */
+	u32 cr46;		/* 0xB8 */
+	u32 cr47;		/* 0xBC */
+	u32 cr48;		/* 0xC0 */
+	u32 cr49;		/* 0xC4 */
+	u32 cr50;		/* 0xC8 */
+	u32 cr51;		/* 0xCC */
+	u32 cr52;		/* 0xD0 */
+	u32 cr53;		/* 0xD4 */
+	u32 cr54;		/* 0xD8 */
+	u32 cr55;		/* 0xDC */
+	u32 cr56;		/* 0xE0 */
+	u32 cr57;		/* 0xE4 */
+	u32 cr58;		/* 0xE8 */
+	u32 cr59;		/* 0xEC */
+	u32 cr60;		/* 0xF0 */
+	u32 cr61;		/* 0xF4 */
+	u32 cr62;		/* 0xF8 */
+	u32 cr63;		/* 0xFC */
+
+	u32 rsvd3[32];		/* 0xF4-0x1A8 */
+
+	u32 rcrcr;		/* 0x180 */
+	u32 swrcr;		/* 0x184 */
+	u32 rcr;		/* 0x188 */
+	u32 msovr;		/* 0x18C */
+	u32 rcrdbg;		/* 0x190 */
+	u32 sl0adj;		/* 0x194 */
+	u32 sl1adj;		/* 0x198 */
+	u32 sl2adj;		/* 0x19C */
+	u32 sl3adj;		/* 0x1A0 */
+	u32 sl4adj;		/* 0x1A4 */
+	u32 flight_tm;		/* 0x1A8 */
+	u32 padcr;		/* 0x1AC */
+} sdramc_t;
+
+/* Phase Locked Loop (PLL) */
+typedef struct pll {
+	u32 pcr;		/* Control */
+	u32 pdr;		/* Divider */
+	u32 psr;		/* Status */
+} pll_t;
+
+typedef struct scm {
+	u8 rsvd1[19];		/* 0x00 - 0x12 */
+	u8 wcr;			/* 0x13 */
+	u16 rsvd2;		/* 0x14 - 0x15 */
+	u16 cwcr;		/* 0x16 */
+	u8 rsvd3[3];		/* 0x18 - 0x1A */
+	u8 cwsr;		/* 0x1B */
+	u8 rsvd4[3];		/* 0x1C - 0x1E */
+	u8 scmisr;		/* 0x1F */
+	u32 rsvd5;		/* 0x20 - 0x23 */
+	u32 bcr;		/* 0x24 */
+	u8 rsvd6[72];		/* 0x28 - 0x6F */
+	u32 cfadr;		/* 0x70 */
+	u8 rsvd7;		/* 0x74 */
+	u8 cfier;		/* 0x75 */
+	u8 cfloc;		/* 0x76 */
+	u8 cfatr;		/* 0x77 */
+	u32 rsvd8;		/* 0x78 - 0x7B */
+	u32 cfdtr;		/* 0x7C */
+} scm_t;
+
+typedef struct pm {
+	u8 pmsr0;		/* */
+	u8 pmcr0;
+	u8 pmsr1;
+	u8 pmcr1;
+	u32 pmhr0;
+	u32 pmlr0;
+	u32 pmhr1;
+	u32 pmlr1;
+} pm_t;
+
+#endif				/* __IMMAP_5441X__ */
diff --git a/arch/m68k/include/asm/immap_5445x.h b/arch/m68k/include/asm/immap_5445x.h
new file mode 100644
index 0000000..3111d00
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5445x.h
@@ -0,0 +1,335 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5445x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __IMMAP_5445X__
+#define __IMMAP_5445X__
+
+/* Module Base Addresses */
+#define MMAP_SCM1	0xFC000000
+#define MMAP_XBS	0xFC004000
+#define MMAP_FBCS	0xFC008000
+#define MMAP_FEC0	0xFC030000
+#define MMAP_FEC1	0xFC034000
+#define MMAP_RTC	0xFC03C000
+#define MMAP_SCM2	0xFC040000
+#define MMAP_EDMA	0xFC044000
+#define MMAP_INTC0	0xFC048000
+#define MMAP_INTC1	0xFC04C000
+#define MMAP_IACK	0xFC054000
+#define MMAP_I2C	0xFC058000
+#define MMAP_DSPI	0xFC05C000
+#define MMAP_UART0	0xFC060000
+#define MMAP_UART1	0xFC064000
+#define MMAP_UART2	0xFC068000
+#define MMAP_DTMR0	0xFC070000
+#define MMAP_DTMR1	0xFC074000
+#define MMAP_DTMR2	0xFC078000
+#define MMAP_DTMR3	0xFC07C000
+#define MMAP_PIT0	0xFC080000
+#define MMAP_PIT1	0xFC084000
+#define MMAP_PIT2	0xFC088000
+#define MMAP_PIT3	0xFC08C000
+#define MMAP_EPORT	0xFC094000
+#define MMAP_WTM	0xFC098000
+#define MMAP_SBF	0xFC0A0000
+#define MMAP_RCM	0xFC0A0000
+#define MMAP_CCM	0xFC0A0000
+#define MMAP_GPIO	0xFC0A4000
+#define MMAP_PCI	0xFC0A8000
+#define MMAP_PCIARB	0xFC0AC000
+#define MMAP_RNG	0xFC0B4000
+#define MMAP_SDRAM	0xFC0B8000
+#define MMAP_SSI	0xFC0BC000
+#define MMAP_PLL	0xFC0C4000
+#define MMAP_ATA	0x90000000
+#define MMAP_USBHW	0xFC0B0000
+#define MMAP_USBCAPS	0xFC0B0100
+#define MMAP_USBEHCI	0xFC0B0140
+#define MMAP_USBOTG	0xFC0B01A0
+
+#include <asm/coldfire/ata.h>
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/ssi.h>
+
+/* Watchdog Timer Modules (WTM) */
+typedef struct wtm {
+	u16 wcr;
+	u16 wmr;
+	u16 wcntr;
+	u16 wsr;
+} wtm_t;
+
+/* Serial Boot Facility (SBF) */
+typedef struct sbf {
+	u8 resv0[0x18];
+	u16 sbfsr;		/* Serial Boot Facility Status Register */
+	u8 resv1[0x6];
+	u16 sbfcr;		/* Serial Boot Facility Control Register */
+} sbf_t;
+
+/* Reset Controller Module (RCM) */
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
+/* Chip Configuration Module (CCM) */
+typedef struct ccm {
+	u8 ccm_resv0[0x4];
+	u16 ccr;		/* Chip Configuration Register (256 TEPBGA, Read-only) */
+	u8 resv1[0x2];
+	u16 rcon;		/* Reset Configuration (256 TEPBGA, Read-only) */
+	u16 cir;		/* Chip Identification Register (Read-only) */
+	u8 resv2[0x4];
+	u16 misccr;		/* Miscellaneous Control Register */
+	u16 cdr;		/* Clock Divider Register */
+	u16 uocsr;		/* USB On-the-Go Controller Status Register */
+} ccm_t;
+
+/* General Purpose I/O Module (GPIO) */
+typedef struct gpio {
+	u8 podr_fec0h;		/* FEC0 High Port Output Data Register */
+	u8 podr_fec0l;		/* FEC0 Low Port Output Data Register */
+	u8 podr_ssi;		/* SSI Port Output Data Register */
+	u8 podr_fbctl;		/* Flexbus Control Port Output Data Register */
+	u8 podr_be;		/* Flexbus Byte Enable Port Output Data Register */
+	u8 podr_cs;		/* Flexbus Chip-Select Port Output Data Register */
+	u8 podr_dma;		/* DMA Port Output Data Register */
+	u8 podr_feci2c;		/* FEC1 / I2C Port Output Data Register */
+	u8 resv0[0x1];
+	u8 podr_uart;		/* UART Port Output Data Register */
+	u8 podr_dspi;		/* DSPI Port Output Data Register */
+	u8 podr_timer;		/* Timer Port Output Data Register */
+	u8 podr_pci;		/* PCI Port Output Data Register */
+	u8 podr_usb;		/* USB Port Output Data Register */
+	u8 podr_atah;		/* ATA High Port Output Data Register */
+	u8 podr_atal;		/* ATA Low Port Output Data Register */
+	u8 podr_fec1h;		/* FEC1 High Port Output Data Register */
+	u8 podr_fec1l;		/* FEC1 Low Port Output Data Register */
+	u8 resv1[0x2];
+	u8 podr_fbadh;		/* Flexbus AD High Port Output Data Register */
+	u8 podr_fbadmh;		/* Flexbus AD Med-High Port Output Data Register */
+	u8 podr_fbadml;		/* Flexbus AD Med-Low Port Output Data Register */
+	u8 podr_fbadl;		/* Flexbus AD Low Port Output Data Register */
+	u8 pddr_fec0h;		/* FEC0 High Port Data Direction Register */
+	u8 pddr_fec0l;		/* FEC0 Low Port Data Direction Register */
+	u8 pddr_ssi;		/* SSI Port Data Direction Register */
+	u8 pddr_fbctl;		/* Flexbus Control Port Data Direction Register */
+	u8 pddr_be;		/* Flexbus Byte Enable Port Data Direction Register */
+	u8 pddr_cs;		/* Flexbus Chip-Select Port Data Direction Register */
+	u8 pddr_dma;		/* DMA Port Data Direction Register */
+	u8 pddr_feci2c;		/* FEC1 / I2C Port Data Direction Register */
+	u8 resv2[0x1];
+	u8 pddr_uart;		/* UART Port Data Direction Register */
+	u8 pddr_dspi;		/* DSPI Port Data Direction Register */
+	u8 pddr_timer;		/* Timer Port Data Direction Register */
+	u8 pddr_pci;		/* PCI Port Data Direction Register */
+	u8 pddr_usb;		/* USB Port Data Direction Register */
+	u8 pddr_atah;		/* ATA High Port Data Direction Register */
+	u8 pddr_atal;		/* ATA Low Port Data Direction Register */
+	u8 pddr_fec1h;		/* FEC1 High Port Data Direction Register */
+	u8 pddr_fec1l;		/* FEC1 Low Port Data Direction Register */
+	u8 resv3[0x2];
+	u8 pddr_fbadh;		/* Flexbus AD High Port Data Direction Register */
+	u8 pddr_fbadmh;		/* Flexbus AD Med-High Port Data Direction Register */
+	u8 pddr_fbadml;		/* Flexbus AD Med-Low Port Data Direction Register */
+	u8 pddr_fbadl;		/* Flexbus AD Low Port Data Direction Register */
+	u8 ppdsdr_fec0h;	/* FEC0 High Port Pin Data/Set Data Register */
+	u8 ppdsdr_fec0l;	/* FEC0 Low Port Clear Output Data Register */
+	u8 ppdsdr_ssi;		/* SSI Port Pin Data/Set Data Register */
+	u8 ppdsdr_fbctl;	/* Flexbus Control Port Pin Data/Set Data Register */
+	u8 ppdsdr_be;		/* Flexbus Byte Enable Port Pin Data/Set Data Register */
+	u8 ppdsdr_cs;		/* Flexbus Chip-Select Port Pin Data/Set Data Register */
+	u8 ppdsdr_dma;		/* DMA Port Pin Data/Set Data Register */
+	u8 ppdsdr_feci2c;	/* FEC1 / I2C Port Pin Data/Set Data Register */
+	u8 resv4[0x1];
+	u8 ppdsdr_uart;		/* UART Port Pin Data/Set Data Register */
+	u8 ppdsdr_dspi;		/* DSPI Port Pin Data/Set Data Register */
+	u8 ppdsdr_timer;	/* FTimer Port Pin Data/Set Data Register */
+	u8 ppdsdr_pci;		/* PCI Port Pin Data/Set Data Register */
+	u8 ppdsdr_usb;		/* USB Port Pin Data/Set Data Register */
+	u8 ppdsdr_atah;		/* ATA High Port Pin Data/Set Data Register */
+	u8 ppdsdr_atal;		/* ATA Low Port Pin Data/Set Data Register */
+	u8 ppdsdr_fec1h;	/* FEC1 High Port Pin Data/Set Data Register */
+	u8 ppdsdr_fec1l;	/* FEC1 Low Port Pin Data/Set Data Register */
+	u8 resv5[0x2];
+	u8 ppdsdr_fbadh;	/* Flexbus AD High Port Pin Data/Set Data Register */
+	u8 ppdsdr_fbadmh;	/* Flexbus AD Med-High Port Pin Data/Set Data Register */
+	u8 ppdsdr_fbadml;	/* Flexbus AD Med-Low Port Pin Data/Set Data Register */
+	u8 ppdsdr_fbadl;	/* Flexbus AD Low Port Pin Data/Set Data Register */
+	u8 pclrr_fec0h;		/* FEC0 High Port Clear Output Data Register */
+	u8 pclrr_fec0l;		/* FEC0 Low Port Pin Data/Set Data Register */
+	u8 pclrr_ssi;		/* SSI Port Clear Output Data Register */
+	u8 pclrr_fbctl;		/* Flexbus Control Port Clear Output Data Register */
+	u8 pclrr_be;		/* Flexbus Byte Enable Port Clear Output Data Register */
+	u8 pclrr_cs;		/* Flexbus Chip-Select Port Clear Output Data Register */
+	u8 pclrr_dma;		/* DMA Port Clear Output Data Register */
+	u8 pclrr_feci2c;	/* FEC1 / I2C Port Clear Output Data Register */
+	u8 resv6[0x1];
+	u8 pclrr_uart;		/* UART Port Clear Output Data Register */
+	u8 pclrr_dspi;		/* DSPI Port Clear Output Data Register */
+	u8 pclrr_timer;		/* Timer Port Clear Output Data Register */
+	u8 pclrr_pci;		/* PCI Port Clear Output Data Register */
+	u8 pclrr_usb;		/* USB Port Clear Output Data Register */
+	u8 pclrr_atah;		/* ATA High Port Clear Output Data Register */
+	u8 pclrr_atal;		/* ATA Low Port Clear Output Data Register */
+	u8 pclrr_fec1h;		/* FEC1 High Port Clear Output Data Register */
+	u8 pclrr_fec1l;		/* FEC1 Low Port Clear Output Data Register */
+	u8 resv7[0x2];
+	u8 pclrr_fbadh;		/* Flexbus AD High Port Clear Output Data Register */
+	u8 pclrr_fbadmh;	/* Flexbus AD Med-High Port Clear Output Data Register */
+	u8 pclrr_fbadml;	/* Flexbus AD Med-Low Port Clear Output Data Register */
+	u8 pclrr_fbadl;		/* Flexbus AD Low Port Clear Output Data Register */
+	u8 par_fec;		/* FEC Pin Assignment Register */
+	u8 par_dma;		/* DMA Pin Assignment Register */
+	u8 par_fbctl;		/* Flexbus Control Pin Assignment Register */
+	u8 par_dspi;		/* DSPI Pin Assignment Register */
+	u8 par_be;		/* Flexbus Byte-Enable Pin Assignment Register */
+	u8 par_cs;		/* Flexbus Chip-Select Pin Assignment Register */
+	u8 par_timer;		/* Time Pin Assignment Register */
+	u8 par_usb;		/* USB Pin Assignment Register */
+	u8 resv8[0x1];
+	u8 par_uart;		/* UART Pin Assignment Register */
+	u16 par_feci2c;		/* FEC / I2C Pin Assignment Register */
+	u16 par_ssi;		/* SSI Pin Assignment Register */
+	u16 par_ata;		/* ATA Pin Assignment Register */
+	u8 par_irq;		/* IRQ Pin Assignment Register */
+	u8 resv9[0x1];
+	u16 par_pci;		/* PCI Pin Assignment Register */
+	u8 mscr_sdram;		/* SDRAM Mode Select Control Register */
+	u8 mscr_pci;		/* PCI Mode Select Control Register */
+	u8 resv10[0x2];
+	u8 dscr_i2c;		/* I2C Drive Strength Control Register */
+	u8 dscr_flexbus;	/* FLEXBUS Drive Strength Control Register */
+	u8 dscr_fec;		/* FEC Drive Strength Control Register */
+	u8 dscr_uart;		/* UART Drive Strength Control Register */
+	u8 dscr_dspi;		/* DSPI Drive Strength Control Register */
+	u8 dscr_timer;		/* TIMER Drive Strength Control Register */
+	u8 dscr_ssi;		/* SSI Drive Strength Control Register */
+	u8 dscr_dma;		/* DMA Drive Strength Control Register */
+	u8 dscr_debug;		/* DEBUG Drive Strength Control Register */
+	u8 dscr_reset;		/* RESET Drive Strength Control Register */
+	u8 dscr_irq;		/* IRQ Drive Strength Control Register */
+	u8 dscr_usb;		/* USB Drive Strength Control Register */
+	u8 dscr_ata;		/* ATA Drive Strength Control Register */
+} gpio_t;
+
+/* SDRAM Controller (SDRAMC) */
+typedef struct sdramc {
+	u32 sdmr;		/* SDRAM Mode/Extended Mode Register */
+	u32 sdcr;		/* SDRAM Control Register */
+	u32 sdcfg1;		/* SDRAM Configuration Register 1 */
+	u32 sdcfg2;		/* SDRAM Chip Select Register */
+	u8 resv0[0x100];
+	u32 sdcs0;		/* SDRAM Mode/Extended Mode Register */
+	u32 sdcs1;		/* SDRAM Mode/Extended Mode Register */
+} sdramc_t;
+
+/* Phase Locked Loop (PLL) */
+typedef struct pll {
+	u32 pcr;		/* PLL Control Register */
+	u32 psr;		/* PLL Status Register */
+} pll_t;
+
+typedef struct pci {
+	u32 idr;		/* 0x00 Device Id / Vendor Id Register */
+	u32 scr;		/* 0x04 Status / command Register */
+	u32 ccrir;		/* 0x08 Class Code / Revision Id Register */
+	u32 cr1;		/* 0x0c Configuration 1 Register */
+	u32 bar0;		/* 0x10 Base address register 0 Register */
+	u32 bar1;		/* 0x14 Base address register 1 Register */
+	u32 bar2;		/* 0x18 Base address register 2 Register */
+	u32 bar3;		/* 0x1c Base address register 3 Register */
+	u32 bar4;		/* 0x20 Base address register 4 Register */
+	u32 bar5;		/* 0x24 Base address register 5 Register */
+	u32 ccpr;		/* 0x28 Cardbus CIS Pointer Register */
+	u32 sid;		/* 0x2c Subsystem ID / Subsystem Vendor ID Register */
+	u32 erbar;		/* 0x30 Expansion ROM Base Address Register */
+	u32 cpr;		/* 0x34 Capabilities Pointer Register */
+	u32 rsvd1;		/* 0x38 */
+	u32 cr2;		/* 0x3c Configuration Register 2 */
+	u32 rsvd2[8];		/* 0x40 - 0x5f */
+
+	/* General control / status registers */
+	u32 gscr;		/* 0x60 Global Status / Control Register */
+	u32 tbatr0a;		/* 0x64 Target Base Address Translation Register  0 */
+	u32 tbatr1a;		/* 0x68 Target Base Address Translation Register  1 */
+	u32 tcr1;		/* 0x6c Target Control 1 Register */
+	u32 iw0btar;		/* 0x70 Initiator Window 0 Base/Translation addr */
+	u32 iw1btar;		/* 0x74 Initiator Window 1 Base/Translation addr */
+	u32 iw2btar;		/* 0x78 Initiator Window 2 Base/Translation addr */
+	u32 rsvd3;		/* 0x7c */
+	u32 iwcr;		/* 0x80 Initiator Window Configuration Register */
+	u32 icr;		/* 0x84 Initiator Control Register */
+	u32 isr;		/* 0x88 Initiator Status Register */
+	u32 tcr2;		/* 0x8c Target Control 2 Register */
+	u32 tbatr0;		/* 0x90 Target Base Address Translation Register  0 */
+	u32 tbatr1;		/* 0x94 Target Base Address Translation Register  1 */
+	u32 tbatr2;		/* 0x98 Target Base Address Translation Register  2 */
+	u32 tbatr3;		/* 0x9c Target Base Address Translation Register  3 */
+	u32 tbatr4;		/* 0xa0 Target Base Address Translation Register  4 */
+	u32 tbatr5;		/* 0xa4 Target Base Address Translation Register  5 */
+	u32 intr;		/* 0xa8 Interrupt Register */
+	u32 rsvd4[19];		/* 0xac - 0xf7 */
+	u32 car;		/* 0xf8 Configuration Address Register */
+} pci_t;
+
+typedef struct pci_arbiter {
+	/* Pci Arbiter Registers */
+	union {
+		u32 acr;	/* Arbiter Control Register */
+		u32 asr;	/* Arbiter Status Register */
+	};
+} pciarb_t;
+
+/* Register read/write struct */
+typedef struct scm1 {
+	u32 mpr;		/* 0x00 Master Privilege Register */
+	u32 rsvd1[7];
+	u32 pacra;		/* 0x20 Peripheral Access Control Register A */
+	u32 pacrb;		/* 0x24 Peripheral Access Control Register B */
+	u32 pacrc;		/* 0x28 Peripheral Access Control Register C */
+	u32 pacrd;		/* 0x2C Peripheral Access Control Register D */
+	u32 rsvd2[4];
+	u32 pacre;		/* 0x40 Peripheral Access Control Register E */
+	u32 pacrf;		/* 0x44 Peripheral Access Control Register F */
+	u32 pacrg;		/* 0x48 Peripheral Access Control Register G */
+} scm1_t;
+
+typedef struct scm2 {
+	u8 rsvd1[19];		/* 0x00 - 0x12 */
+	u8 wcr;			/* 0x13 */
+	u16 rsvd2;		/* 0x14 - 0x15 */
+	u16 cwcr;		/* 0x16 */
+	u8 rsvd3[3];		/* 0x18 - 0x1A */
+	u8 cwsr;		/* 0x1B */
+	u8 rsvd4[3];		/* 0x1C - 0x1E */
+	u8 scmisr;		/* 0x1F */
+	u32 rsvd5;		/* 0x20 - 0x23 */
+	u8 bcr;			/* 0x24 */
+	u8 rsvd6[74];		/* 0x25 - 0x6F */
+	u32 cfadr;		/* 0x70 */
+	u8 rsvd7;		/* 0x74 */
+	u8 cfier;		/* 0x75 */
+	u8 cfloc;		/* 0x76 */
+	u8 cfatr;		/* 0x77 */
+	u32 rsvd8;		/* 0x78 - 0x7B */
+	u32 cfdtr;		/* 0x7C */
+} scm2_t;
+
+typedef struct rtcex {
+	u32 rsvd1[3];
+	u32 gocu;
+	u32 gocl;
+} rtcex_t;
+#endif				/* __IMMAP_5445X__ */
diff --git a/arch/m68k/include/asm/immap_547x_8x.h b/arch/m68k/include/asm/immap_547x_8x.h
new file mode 100644
index 0000000..5e13456
--- /dev/null
+++ b/arch/m68k/include/asm/immap_547x_8x.h
@@ -0,0 +1,258 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF547x_8x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __IMMAP_547x_8x__
+#define __IMMAP_547x_8x__
+
+#define MMAP_SIU	(CONFIG_SYS_MBAR + 0x00000000)
+#define MMAP_SDRAM	(CONFIG_SYS_MBAR + 0x00000100)
+#define MMAP_XARB	(CONFIG_SYS_MBAR + 0x00000240)
+#define MMAP_FBCS	(CONFIG_SYS_MBAR + 0x00000500)
+#define MMAP_INTC0	(CONFIG_SYS_MBAR + 0x00000700)
+#define MMAP_GPTMR	(CONFIG_SYS_MBAR + 0x00000800)
+#define MMAP_SLT0	(CONFIG_SYS_MBAR + 0x00000900)
+#define MMAP_SLT1	(CONFIG_SYS_MBAR + 0x00000910)
+#define MMAP_GPIO	(CONFIG_SYS_MBAR + 0x00000A00)
+#define MMAP_PCI	(CONFIG_SYS_MBAR + 0x00000B00)
+#define MMAP_PCIARB	(CONFIG_SYS_MBAR + 0x00000C00)
+#define MMAP_EXTDMA	(CONFIG_SYS_MBAR + 0x00000D00)
+#define MMAP_EPORT	(CONFIG_SYS_MBAR + 0x00000F00)
+#define MMAP_CTM	(CONFIG_SYS_MBAR + 0x00007F00)
+#define MMAP_MCDMA	(CONFIG_SYS_MBAR + 0x00008000)
+#define MMAP_SCPCI	(CONFIG_SYS_MBAR + 0x00008400)
+#define MMAP_UART0	(CONFIG_SYS_MBAR + 0x00008600)
+#define MMAP_UART1	(CONFIG_SYS_MBAR + 0x00008700)
+#define MMAP_UART2	(CONFIG_SYS_MBAR + 0x00008800)
+#define MMAP_UART3	(CONFIG_SYS_MBAR + 0x00008900)
+#define MMAP_DSPI	(CONFIG_SYS_MBAR + 0x00008A00)
+#define MMAP_I2C	(CONFIG_SYS_MBAR + 0x00008F00)
+#define MMAP_FEC0	(CONFIG_SYS_MBAR + 0x00009000)
+#define MMAP_FEC1	(CONFIG_SYS_MBAR + 0x00009800)
+#define MMAP_CAN0	(CONFIG_SYS_MBAR + 0x0000A000)
+#define MMAP_CAN1	(CONFIG_SYS_MBAR + 0x0000A800)
+#define MMAP_USBD	(CONFIG_SYS_MBAR + 0x0000B000)
+#define MMAP_SRAM	(CONFIG_SYS_MBAR + 0x00010000)
+#define MMAP_SRAMCFG	(CONFIG_SYS_MBAR + 0x0001FF00)
+#define MMAP_SEC	(CONFIG_SYS_MBAR + 0x00020000)
+
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+
+typedef struct siu {
+	u32 mbar;		/* 0x00 */
+	u32 drv;		/* 0x04 */
+	u32 rsvd1[2];		/* 0x08 - 0x1F */
+	u32 sbcr;		/* 0x10 */
+	u32 rsvd2[3];		/* 0x14 - 0x1F */
+	u32 cs0cfg;		/* 0x20 */
+	u32 cs1cfg;		/* 0x24 */
+	u32 cs2cfg;		/* 0x28 */
+	u32 cs3cfg;		/* 0x2C */
+	u32 rsvd3[2];		/* 0x30 - 0x37 */
+	u32 secsacr;		/* 0x38 */
+	u32 rsvd4[2];		/* 0x3C - 0x43 */
+	u32 rsr;		/* 0x44 */
+	u32 rsvd5[2];		/* 0x48 - 0x4F */
+	u32 jtagid;		/* 0x50 */
+} siu_t;
+
+typedef struct sdram {
+	u32 mode;		/* 0x00 */
+	u32 ctrl;		/* 0x04 */
+	u32 cfg1;		/* 0x08 */
+	u32 cfg2;		/* 0x0c */
+} sdram_t;
+
+typedef struct xlb_arb {
+	u32 cfg;		/* 0x240 */
+	u32 ver;		/* 0x244 */
+	u32 sr;			/* 0x248 */
+	u32 imr;		/* 0x24c */
+	u32 adrcap;		/* 0x250 */
+	u32 sigcap;		/* 0x254 */
+	u32 adrto;		/* 0x258 */
+	u32 datto;		/* 0x25c */
+	u32 busto;		/* 0x260 */
+	u32 prien;		/* 0x264 */
+	u32 pri;		/* 0x268 */
+} xlbarb_t;
+
+typedef struct gptmr {
+	u8 ocpw;
+	u8 octict;
+	u8 ctrl;
+	u8 mode;
+
+	u16 pre;		/* Prescale */
+	u16 cnt;
+
+	u16 pwmwidth;
+	u8 pwmop;		/* Output Polarity */
+	u8 pwmld;		/* Immediate Update */
+
+	u16 cap;		/* Capture internal counter */
+	u8 ovfpin;		/* Ovf and Pin */
+	u8 intr;		/* Interrupts */
+} gptmr_t;
+
+typedef struct canex_ctrl {
+	can_msg_t msg[16];	/* 0x00 Message Buffer 0-15 */
+} canex_t;
+
+
+typedef struct slt {
+	u32 tcnt;		/* 0x00 */
+	u32 cr;			/* 0x04 */
+	u32 cnt;		/* 0x08 */
+	u32 sr;			/* 0x0C */
+} slt_t;
+
+typedef struct gpio {
+	/* Port Output Data Registers */
+	u8 podr_fbctl;		/*0x00 */
+	u8 podr_fbcs;		/*0x01 */
+	u8 podr_dma;		/*0x02 */
+	u8 rsvd1;		/*0x03 */
+	u8 podr_fec0h;		/*0x04 */
+	u8 podr_fec0l;		/*0x05 */
+	u8 podr_fec1h;		/*0x06 */
+	u8 podr_fec1l;		/*0x07 */
+	u8 podr_feci2c;		/*0x08 */
+	u8 podr_pcibg;		/*0x09 */
+	u8 podr_pcibr;		/*0x0A */
+	u8 rsvd2;		/*0x0B */
+	u8 podr_psc3psc2;	/*0x0C */
+	u8 podr_psc1psc0;	/*0x0D */
+	u8 podr_dspi;		/*0x0E */
+	u8 rsvd3;		/*0x0F */
+
+	/* Port Data Direction Registers */
+	u8 pddr_fbctl;		/*0x10 */
+	u8 pddr_fbcs;		/*0x11 */
+	u8 pddr_dma;		/*0x12 */
+	u8 rsvd4;		/*0x13 */
+	u8 pddr_fec0h;		/*0x14 */
+	u8 pddr_fec0l;		/*0x15 */
+	u8 pddr_fec1h;		/*0x16 */
+	u8 pddr_fec1l;		/*0x17 */
+	u8 pddr_feci2c;		/*0x18 */
+	u8 pddr_pcibg;		/*0x19 */
+	u8 pddr_pcibr;		/*0x1A */
+	u8 rsvd5;		/*0x1B */
+	u8 pddr_psc3psc2;	/*0x1C */
+	u8 pddr_psc1psc0;	/*0x1D */
+	u8 pddr_dspi;		/*0x1E */
+	u8 rsvd6;		/*0x1F */
+
+	/* Port Pin Data/Set Data Registers */
+	u8 ppdsdr_fbctl;	/*0x20 */
+	u8 ppdsdr_fbcs;		/*0x21 */
+	u8 ppdsdr_dma;		/*0x22 */
+	u8 rsvd7;		/*0x23 */
+	u8 ppdsdr_fec0h;	/*0x24 */
+	u8 ppdsdr_fec0l;	/*0x25 */
+	u8 ppdsdr_fec1h;	/*0x26 */
+	u8 ppdsdr_fec1l;	/*0x27 */
+	u8 ppdsdr_feci2c;	/*0x28 */
+	u8 ppdsdr_pcibg;	/*0x29 */
+	u8 ppdsdr_pcibr;	/*0x2A */
+	u8 rsvd8;		/*0x2B */
+	u8 ppdsdr_psc3psc2;	/*0x2C */
+	u8 ppdsdr_psc1psc0;	/*0x2D */
+	u8 ppdsdr_dspi;		/*0x2E */
+	u8 rsvd9;		/*0x2F */
+
+	/* Port Clear Output Data Registers */
+	u8 pclrr_fbctl;		/*0x30 */
+	u8 pclrr_fbcs;		/*0x31 */
+	u8 pclrr_dma;		/*0x32 */
+	u8 rsvd10;		/*0x33 */
+	u8 pclrr_fec0h;		/*0x34 */
+	u8 pclrr_fec0l;		/*0x35 */
+	u8 pclrr_fec1h;		/*0x36 */
+	u8 pclrr_fec1l;		/*0x37 */
+	u8 pclrr_feci2c;	/*0x38 */
+	u8 pclrr_pcibg;		/*0x39 */
+	u8 pclrr_pcibr;		/*0x3A */
+	u8 rsvd11;		/*0x3B */
+	u8 pclrr_psc3psc2;	/*0x3C */
+	u8 pclrr_psc1psc0;	/*0x3D */
+	u8 pclrr_dspi;		/*0x3E */
+	u8 rsvd12;		/*0x3F */
+
+	/* Pin Assignment Registers */
+	u16 par_fbctl;		/*0x40 */
+	u8 par_fbcs;		/*0x42 */
+	u8 par_dma;		/*0x43 */
+	u16 par_feci2cirq;	/*0x44 */
+	u16 rsvd13;		/*0x46 */
+	u16 par_pcibg;		/*0x48 */
+	u16 par_pcibr;		/*0x4A */
+	u8 par_psc3;		/*0x4C */
+	u8 par_psc2;		/*0x4D */
+	u8 par_psc1;		/*0x4E */
+	u8 par_psc0;		/*0x4F */
+	u16 par_dspi;		/*0x50 */
+	u8 par_timer;		/*0x52 */
+	u8 rsvd14;		/*0x53 */
+} gpio_t;
+
+typedef struct pci {
+	u32 idr;		/* 0x00 Device Id / Vendor Id */
+	u32 scr;		/* 0x04 Status / command */
+	u32 ccrir;		/* 0x08 Class Code / Revision Id */
+	u32 cr1;		/* 0x0c Configuration 1 */
+	u32 bar0;		/* 0x10 Base address register 0 */
+	u32 bar1;		/* 0x14 Base address register 1 */
+	u32 bar2;		/* 0x18 NA */
+	u32 bar3;		/* 0x1c NA */
+	u32 bar4;		/* 0x20 NA */
+	u32 bar5;		/* 0x24 NA */
+	u32 ccpr;		/* 0x28 Cardbus CIS Pointer */
+	u32 sid;		/* 0x2c Subsystem ID / Subsystem Vendor ID */
+	u32 erbar;		/* 0x30 Expansion ROM Base Address */
+	u32 cpr;		/* 0x34 Capabilities Pointer */
+	u32 rsvd1;		/* 0x38 */
+	u32 cr2;		/* 0x3c Configuration 2 */
+	u32 rsvd2[8];		/* 0x40 - 0x5f */
+
+	/* General control / status registers */
+	u32 gscr;		/* 0x60 Global Status / Control */
+	u32 tbatr0a;		/* 0x64 Target Base Adr Translation 0 */
+	u32 tbatr1a;		/* 0x68 Target Base Adr Translation 1 */
+	u32 tcr1;		/* 0x6c Target Control 1 Register */
+	u32 iw0btar;		/* 0x70 Initiator Win 0 Base/Translation adr */
+	u32 iw1btar;		/* 0x74 Initiator Win 1 Base/Translation adr */
+	u32 iw2btar;		/* 0x78 NA */
+	u32 rsvd3;		/* 0x7c */
+	u32 iwcr;		/* 0x80 Initiator Window Configuration */
+	u32 icr;		/* 0x84 Initiator Control */
+	u32 isr;		/* 0x88 Initiator Status */
+	u32 tcr2;		/* 0x8c NA */
+	u32 tbatr0;		/* 0x90 NA */
+	u32 tbatr1;		/* 0x94 NA */
+	u32 tbatr2;		/* 0x98 NA */
+	u32 tbatr3;		/* 0x9c NA */
+	u32 tbatr4;		/* 0xa0 NA */
+	u32 tbatr5;		/* 0xa4 NA */
+	u32 intr;		/* 0xa8 NA */
+	u32 rsvd4[19];		/* 0xac - 0xf7 */
+	u32 car;		/* 0xf8 Configuration Address */
+} pci_t;
+
+typedef struct pci_arbiter {
+	/* Pci Arbiter Registers */
+	union {
+		u32 acr;	/* Arbiter Control */
+		u32 asr;	/* Arbiter Status */
+	};
+} pciarb_t;
+#endif				/* __IMMAP_547x_8x__ */
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
new file mode 100644
index 0000000..35ad4a1
--- /dev/null
+++ b/arch/m68k/include/asm/io.h
@@ -0,0 +1,257 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * IO header file
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __ASM_M68K_IO_H__
+#define __ASM_M68K_IO_H__
+
+#include <asm/byteorder.h>
+
+#ifndef _IO_BASE
+#define _IO_BASE 0
+#endif
+
+#define __raw_readb(addr) (*(volatile u8 *)(addr))
+#define __raw_readw(addr) (*(volatile u16 *)(addr))
+#define __raw_readl(addr) (*(volatile u32 *)(addr))
+
+#define __raw_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
+#define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w))
+#define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l))
+
+#define readb(addr)		in_8((volatile u8 *)(addr))
+#define writeb(b,addr)		out_8((volatile u8 *)(addr), (b))
+#if !defined(__BIG_ENDIAN)
+#define readw(addr)		(*(volatile u16 *) (addr))
+#define readl(addr)		(*(volatile u32 *) (addr))
+#define writew(b,addr)		((*(volatile u16 *) (addr)) = (b))
+#define writel(b,addr)		((*(volatile u32 *) (addr)) = (b))
+#else
+#define readw(addr)		in_be16((volatile u16 *)(addr))
+#define readl(addr)		in_be32((volatile u32 *)(addr))
+#define writew(b,addr)		out_be16((volatile u16 *)(addr),(b))
+#define writel(b,addr)		out_be32((volatile u32 *)(addr),(b))
+#endif
+
+/*
+ * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * They are only used in practice for transferring buffers which
+ * are arrays of bytes, and byte-swapping is not appropriate in
+ * that case.  - paulus
+ */
+#define insb(port, buf, ns)	_insb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define outsb(port, buf, ns)	_outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns)	_insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns)	_outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl(port, buf, nl)	_insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl(port, buf, nl)	_outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define inb(port)		in_8((u8 *)((port)+_IO_BASE))
+#define outb(val, port)		out_8((u8 *)((port)+_IO_BASE), (val))
+#if !defined(__BIG_ENDIAN)
+#define inw(port)		in_be16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)		out_be16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)		in_be32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)		out_be32((u32 *)((port)+_IO_BASE), (val))
+#else
+#define inw(port)		in_le16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)		out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)		in_le32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)		out_le32((u32 *)((port)+_IO_BASE), (val))
+#endif
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+static inline void _insb(volatile u8 * port, void *buf, int ns)
+{
+	u8 *data = (u8 *) buf;
+	while (ns--)
+		*data++ = *port;
+}
+
+static inline void _outsb(volatile u8 * port, const void *buf, int ns)
+{
+	u8 *data = (u8 *) buf;
+	while (ns--)
+		*port = *data++;
+}
+
+static inline void _insw(volatile u16 * port, void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--)
+		*data++ = __sw16(*port);
+}
+
+static inline void _outsw(volatile u16 * port, const void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--) {
+		*port = __sw16(*data);
+		data++;
+	}
+}
+
+static inline void _insl(volatile u32 * port, void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--)
+		*data++ = __sw32(*port);
+}
+
+static inline void _outsl(volatile u32 * port, const void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--) {
+		*port = __sw32(*data);
+		data++;
+	}
+}
+
+static inline void _insw_ns(volatile u16 * port, void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--)
+		*data++ = *port;
+}
+
+static inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--) {
+		*port = *data++;
+	}
+}
+
+static inline void _insl_ns(volatile u32 * port, void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--)
+		*data++ = *port;
+}
+
+static inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--) {
+		*port = *data;
+		data++;
+	}
+}
+
+/*
+ * The *_ns versions below don't do byte-swapping.
+ * Neither do the standard versions now, these are just here
+ * for older code.
+ */
+#define insw_ns(port, buf, ns)	_insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns)	_outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl_ns(port, buf, nl)	_insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl_ns(port, buf, nl)	_outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define IO_SPACE_LIMIT ~0
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ */
+static inline int in_8(volatile u8 * addr)
+{
+	return (int)*addr;
+}
+
+static inline void out_8(volatile u8 * addr, int val)
+{
+	*addr = (u8) val;
+}
+
+static inline int in_le16(volatile u16 * addr)
+{
+	return __sw16(*addr);
+}
+
+static inline int in_be16(volatile u16 * addr)
+{
+	return (*addr & 0xFFFF);
+}
+
+static inline void out_le16(volatile u16 * addr, int val)
+{
+	*addr = __sw16(val);
+}
+
+static inline void out_be16(volatile u16 * addr, int val)
+{
+	*addr = (u16) val;
+}
+
+static inline unsigned in_le32(volatile u32 * addr)
+{
+	return __sw32(*addr);
+}
+
+static inline unsigned in_be32(volatile u32 * addr)
+{
+	return (*addr);
+}
+
+static inline void out_le32(volatile unsigned *addr, int val)
+{
+	*addr = __sw32(val);
+}
+
+static inline void out_be32(volatile unsigned *addr, int val)
+{
+	*addr = val;
+}
+
+/* Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+static inline void sync(void)
+{
+	/* This sync function is for PowerPC or other architecture instruction
+	 * ColdFire does not have this instruction. Dummy function, added for
+	 * compatibility (CFI driver)
+	 */
+}
+
+#include <asm-generic/io.h>
+
+#endif				/* __ASM_M68K_IO_H__ */
diff --git a/arch/m68k/include/asm/linkage.h b/arch/m68k/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/m68k/include/asm/linkage.h
diff --git a/arch/m68k/include/asm/m520x.h b/arch/m68k/include/asm/m520x.h
new file mode 100644
index 0000000..ce271ec
--- /dev/null
+++ b/arch/m68k/include/asm/m520x.h
@@ -0,0 +1,340 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * m520x.h -- Definitions for Freescale Coldfire 520x
+ *
+ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __M520X__
+#define __M520X__
+
+/* *** System Control Module (SCM) *** */
+#define SCM_MPR_MPROT0(x)		(((x) & 0x0F) << 28)
+#define SCM_MPR_MPROT1(x)		(((x) & 0x0F) << 24)
+#define SCM_MPR_MPROT2(x)		(((x) & 0x0F) << 20)
+#define MPROT_MTR			4
+#define MPROT_MTW			2
+#define MPROT_MPL			1
+
+#define SCM_PACRA_PACR0(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRA_PACR1(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRA_PACR2(x)		(((x) & 0x0F) << 20)
+
+#define SCM_PACRB_PACR12(x)		(((x) & 0x0F) << 12)
+
+#define SCM_PACRC_PACR16(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRC_PACR17(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRC_PACR18(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRC_PACR21(x)		(((x) & 0x0F) << 8)
+#define SCM_PACRC_PACR22(x)		(((x) & 0x0F) << 4)
+#define SCM_PACRC_PACR23(x)		((x) & 0x0F)
+
+#define SCM_PACRD_PACR24(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRD_PACR25(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRD_PACR26(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRD_PACR28(x)		(((x) & 0x0F) << 12)
+#define SCM_PACRD_PACR29(x)		(((x) & 0x0F) << 8)
+#define SCM_PACRD_PACR30(x)		(((x) & 0x0F) << 4)
+#define SCM_PACRD_PACR31(x)		((x) & 0x0F)
+
+#define SCM_PACRE_PACR32(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRE_PACR33(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRE_PACR34(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRE_PACR35(x)		(((x) & 0x0F) << 16)
+#define SCM_PACRE_PACR36(x)		(((x) & 0x0F) << 12)
+
+#define SCM_PACRF_PACR40(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRF_PACR41(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRF_PACR42(x)		(((x) & 0x0F) << 20)
+
+#define PACR_SP	4
+#define PACR_WP	2
+#define PACR_TP	1
+
+#define SCM_BMT_BME			(0x00000008)
+#define SCM_BMT_BMT(x)			((x) & 0x07)
+#define SCM_BMT_BMT1024			(0x0000)
+#define SCM_BMT_BMT512			(0x0001)
+#define SCM_BMT_BMT256			(0x0002)
+#define SCM_BMT_BMT128			(0x0003)
+#define SCM_BMT_BMT64			(0x0004)
+#define SCM_BMT_BMT32			(0x0005)
+#define SCM_BMT_BMT16			(0x0006)
+#define SCM_BMT_BMT8			(0x0007)
+
+#define SCM_CWCR_RO			(0x8000)
+#define SCM_CWCR_CWR_WH			(0x0100)
+#define SCM_CWCR_CWE			(0x0080)
+#define SCM_CWRI_WINDOW			(0x0060)
+#define SCM_CWRI_RESET			(0x0040)
+#define SCM_CWRI_INT_RESET		(0x0020)
+#define SCM_CWRI_INT			(0x0000)
+#define SCM_CWCR_CWT(x)			(((x) & 0x001F))
+
+#define SCM_ISR_CFEI			(0x02)
+#define SCM_ISR_CWIC			(0x01)
+
+#define SCM_CFIER_ECFEI			(0x01)
+
+#define SCM_CFLOC_LOC			(0x80)
+
+#define SCM_CFATR_WRITE			(0x80)
+#define SCM_CFATR_SZ32			(0x20)
+#define SCM_CFATR_SZ16			(0x10)
+#define SCM_CFATR_SZ08			(0x00)
+#define SCM_CFATR_CACHE			(0x08)
+#define SCM_CFATR_MODE			(0x02)
+#define SCM_CFATR_TYPE			(0x01)
+
+/* *** Interrupt Controller (INTC) *** */
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT_F1		(1)
+#define INT0_LO_EPORT_F4		(2)
+#define INT0_LO_EPORT_F7		(3)
+#define INT1_LO_PIT0			(4)
+#define INT1_LO_PIT1			(5)
+/* 6 - 7 rsvd */
+#define INT0_LO_EDMA_00			(8)
+#define INT0_LO_EDMA_01			(9)
+#define INT0_LO_EDMA_02			(10)
+#define INT0_LO_EDMA_03			(11)
+#define INT0_LO_EDMA_04			(12)
+#define INT0_LO_EDMA_05			(13)
+#define INT0_LO_EDMA_06			(14)
+#define INT0_LO_EDMA_07			(15)
+#define INT0_LO_EDMA_08			(16)
+#define INT0_LO_EDMA_09			(17)
+#define INT0_LO_EDMA_10			(18)
+#define INT0_LO_EDMA_11			(19)
+#define INT0_LO_EDMA_12			(20)
+#define INT0_LO_EDMA_13			(21)
+#define INT0_LO_EDMA_14			(22)
+#define INT0_LO_EDMA_15			(23)
+#define INT0_LO_EDMA_ERR		(24)
+#define INT0_LO_SCM_CWIC		(25)
+#define INT0_LO_UART0			(26)
+#define INT0_LO_UART1			(27)
+#define INT0_LO_UART2			(28)
+/* 29 rsvd */
+#define INT0_LO_I2C			(30)
+#define INT0_LO_QSPI			(31)
+
+#define INT0_HI_DTMR0			(32)
+#define INT0_HI_DTMR1			(33)
+#define INT0_HI_DTMR2			(34)
+#define INT0_HI_DTMR3			(35)
+#define INT0_HI_FEC0_TXF		(36)
+#define INT0_HI_FEC0_TXB		(37)
+#define INT0_HI_FEC0_UN			(38)
+#define INT0_HI_FEC0_RL			(39)
+#define INT0_HI_FEC0_RXF		(40)
+#define INT0_HI_FEC0_RXB		(41)
+#define INT0_HI_FEC0_MII		(42)
+#define INT0_HI_FEC0_LC			(43)
+#define INT0_HI_FEC0_HBERR		(44)
+#define INT0_HI_FEC0_GRA		(45)
+#define INT0_HI_FEC0_EBERR		(46)
+#define INT0_HI_FEC0_BABT		(47)
+#define INT0_HI_FEC0_BABR		(48)
+/* 49 - 61 rsvd */
+#define INT0_HI_SCMISR_CFEI		(62)
+
+/* *** Reset Controller Module (RCM) *** */
+#define RCM_RCR_SOFTRST			(0x80)
+#define RCM_RCR_FRCRSTOUT		(0x40)
+
+#define RCM_RSR_SOFT			(0x20)
+#define RCM_RSR_WDOG			(0x10)
+#define RCM_RSR_POR			(0x08)
+#define RCM_RSR_EXT			(0x04)
+#define RCM_RSR_WDR_CORE		(0x02)
+#define RCM_RSR_LOL			(0x01)
+
+/* *** Chip Configuration Module (CCM) *** */
+#define CCM_CCR_CSC			(0x0200)
+#define CCM_CCR_OSCFREQ			(0x0080)
+#define CCM_CCR_LIMP			(0x0040)
+#define CCM_CCR_LOAD			(0x0020)
+#define CCM_CCR_BOOTPS(x)		(((x) & 0x0003) << 3)
+#define CCM_CCR_OSC_MODE		(0x0004)
+#define CCM_CCR_PLL_MODE		(0x0002)
+#define CCM_CCR_RESERVED		(0x0001)
+
+#define CCM_CIR_PIN(x)			(((x) & 0xFFC0) >> 6)
+#define CCM_CIR_PRN(x)			((x) & 0x003F)
+
+/* *** General Purpose I/O (GPIO) *** */
+#define GPIO_PDR_BUSCTL(x)		((x) & 0x0F)
+#define GPIO_PDR_BE(x)			((x) & 0x0F)
+#define GPIO_PDR_CS(x)			(((x) & 0x07) << 1)
+#define GPIO_PDR_FECI2C(x)		((x) & 0x0F)
+#define GPIO_PDR_QSPI(x)		((x) & 0x0F)
+#define GPIO_PDR_TIMER(x)		((x) & 0x0F)
+#define GPIO_PDR_UART(x)		((x) & 0xFF)
+#define GPIO_PDR_FECH(x)		((x) & 0xFF)
+#define GPIO_PDR_FECL(x)		((x) & 0xFF)
+
+#define GPIO_PAR_FBCTL_OE		(0x10)
+#define GPIO_PAR_FBCTL_TA		(0x08)
+#define GPIO_PAR_FBCTL_RWB		(0x04)
+#define GPIO_PAR_FBCTL_TS_UNMASK	(0xFC)
+#define GPIO_PAR_FBCTL_TS_TS		(0x03)
+#define GPIO_PAR_FBCTL_TS_DMA		(0x02)
+
+#define GPIO_PAR_BE3			(0x08)
+#define GPIO_PAR_BE2			(0x04)
+#define GPIO_PAR_BE1			(0x02)
+#define GPIO_PAR_BE0			(0x01)
+
+#define GPIO_PAR_CS3			(0x08)
+#define GPIO_PAR_CS2			(0x04)
+#define GPIO_PAR_CS1_UNMASK		(0xFC)
+#define GPIO_PAR_CS1_CS1		(0x03)
+#define GPIO_PAR_CS1_SDCS1		(0x02)
+
+#define GPIO_PAR_FECI2C_RMII_UNMASK	(0x0F)
+#define GPIO_PAR_FECI2C_MDC_UNMASK	(0x3F)
+#define GPIO_PAR_FECI2C_MDC_MDC		(0xC0)
+#define GPIO_PAR_FECI2C_MDC_SCL		(0x80)
+#define GPIO_PAR_FECI2C_MDC_U2TXD	(0x40)
+#define GPIO_PAR_FECI2C_MDIO_UNMASK	(0xCF)
+#define GPIO_PAR_FECI2C_MDIO_MDIO	(0x30)
+#define GPIO_PAR_FECI2C_MDIO_SDA	(0x20)
+#define GPIO_PAR_FECI2C_MDIO_U2RXD	(0x10)
+#define GPIO_PAR_FECI2C_I2C_UNMASK	(0xF0)
+#define GPIO_PAR_FECI2C_SCL_UNMASK	(0xF3)
+#define GPIO_PAR_FECI2C_SCL_SCL		(0x0C)
+#define GPIO_PAR_FECI2C_SCL_U2RXD	(0x04)
+#define GPIO_PAR_FECI2C_SDA_UNMASK	(0xFC)
+#define GPIO_PAR_FECI2C_SDA_SDA		(0x03)
+#define GPIO_PAR_FECI2C_SDA_U2TXD	(0x01)
+
+#define GPIO_PAR_QSPI_PCS2_UNMASK	(0x3F)
+#define GPIO_PAR_QSPI_PCS2_PCS2		(0xC0)
+#define GPIO_PAR_QSPI_PCS2_DACK0	(0x80)
+#define GPIO_PAR_QSPI_PCS2_U2RTS	(0x40)
+#define GPIO_PAR_QSPI_DIN_UNMASK	(0xCF)
+#define GPIO_PAR_QSPI_DIN_DIN		(0x30)
+#define GPIO_PAR_QSPI_DIN_DREQ0		(0x20)
+#define GPIO_PAR_QSPI_DIN_U2CTS		(0x10)
+#define GPIO_PAR_QSPI_DOUT_UNMASK	(0xF3)
+#define GPIO_PAR_QSPI_DOUT_DOUT		(0x0C)
+#define GPIO_PAR_QSPI_DOUT_SDA		(0x08)
+#define GPIO_PAR_QSPI_SCK_UNMASK	(0xFC)
+#define GPIO_PAR_QSPI_SCK_SCK		(0x03)
+#define GPIO_PAR_QSPI_SCK_SCL		(0x02)
+
+#define GPIO_PAR_TMR_TIN3(x)		(((x) & 0x03) << 6)
+#define GPIO_PAR_TMR_TIN2(x)		(((x) & 0x03) << 4)
+#define GPIO_PAR_TMR_TIN1(x)		(((x) & 0x03) << 2)
+#define GPIO_PAR_TMR_TIN0(x)		((x) & 0x03)
+#define GPIO_PAR_TMR_TIN3_UNMASK	(0x3F)
+#define GPIO_PAR_TMR_TIN3_TIN3		(0xC0)
+#define GPIO_PAR_TMR_TIN3_TOUT3		(0x80)
+#define GPIO_PAR_TMR_TIN3_U2CTS		(0x40)
+#define GPIO_PAR_TMR_TIN2_UNMASK	(0xCF)
+#define GPIO_PAR_TMR_TIN2_TIN2		(0x30)
+#define GPIO_PAR_TMR_TIN2_TOUT2		(0x20)
+#define GPIO_PAR_TMR_TIN2_U2RTS		(0x10)
+#define GPIO_PAR_TMR_TIN1_UNMASK	(0xF3)
+#define GPIO_PAR_TMR_TIN1_TIN1		(0x0C)
+#define GPIO_PAR_TMR_TIN1_TOUT1		(0x08)
+#define GPIO_PAR_TMR_TIN1_U2RXD		(0x04)
+#define GPIO_PAR_TMR_TIN0_UNMASK	(0xFC)
+#define GPIO_PAR_TMR_TIN0_TIN0		(0x03)
+#define GPIO_PAR_TMR_TIN0_TOUT0		(0x02)
+#define GPIO_PAR_TMR_TIN0_U2TXD		(0x01)
+
+#define GPIO_PAR_UART1_UNMASK		(0xF03F)
+#define GPIO_PAR_UART0_UNMASK		(0xFFC0)
+#define GPIO_PAR_UART_U1CTS_UNMASK	(0xF3FF)
+#define GPIO_PAR_UART_U1CTS_U1CTS	(0x0C00)
+#define GPIO_PAR_UART_U1CTS_TIN1	(0x0800)
+#define GPIO_PAR_UART_U1CTS_PCS1	(0x0400)
+#define GPIO_PAR_UART_U1RTS_UNMASK	(0xFCFF)
+#define GPIO_PAR_UART_U1RTS_U1RTS	(0x0300)
+#define GPIO_PAR_UART_U1RTS_TOUT1	(0x0200)
+#define GPIO_PAR_UART_U1RTS_PCS1	(0x0100)
+#define GPIO_PAR_UART_U1TXD		(0x0080)
+#define GPIO_PAR_UART_U1RXD		(0x0040)
+#define GPIO_PAR_UART_U0CTS_UNMASK	(0xFFCF)
+#define GPIO_PAR_UART_U0CTS_U0CTS	(0x0030)
+#define GPIO_PAR_UART_U0CTS_TIN0	(0x0020)
+#define GPIO_PAR_UART_U0CTS_PCS0	(0x0010)
+#define GPIO_PAR_UART_U0RTS_UNMASK	(0xFFF3)
+#define GPIO_PAR_UART_U0RTS_U0RTS	(0x000C)
+#define GPIO_PAR_UART_U0RTS_TOUT0	(0x0008)
+#define GPIO_PAR_UART_U0RTS_PCS0	(0x0004)
+#define GPIO_PAR_UART_U0TXD		(0x0002)
+#define GPIO_PAR_UART_U0RXD		(0x0001)
+
+#define GPIO_PAR_FEC_7W_UNMASK		(0xF3)
+#define GPIO_PAR_FEC_7W_FEC		(0x0C)
+#define GPIO_PAR_FEC_7W_U1RTS		(0x04)
+#define GPIO_PAR_FEC_MII_UNMASK		(0xFC)
+#define GPIO_PAR_FEC_MII_FEC		(0x03)
+#define GPIO_PAR_FEC_MII_UnCTS		(0x01)
+
+#define GPIO_PAR_IRQ_IRQ4		(0x01)
+
+#define GPIO_MSCR_FB_FBCLK(x)		(((x) & 0x03) << 6)
+#define GPIO_MSCR_FB_DUP(x)		(((x) & 0x03) << 4)
+#define GPIO_MSCR_FB_DLO(x)		(((x) & 0x03) << 2)
+#define GPIO_MSCR_FB_ADRCTL(x)		((x) & 0x03)
+#define GPIO_MSCR_FB_FBCLK_UNMASK	(0x3F)
+#define GPIO_MSCR_FB_DUP_UNMASK		(0xCF)
+#define GPIO_MSCR_FB_DLO_UNMASK		(0xF3)
+#define GPIO_MSCR_FB_ADRCTL_UNMASK	(0xFC)
+
+#define GPIO_MSCR_SDR_SDCLKB(x)		(((x) & 0x03) << 4)
+#define GPIO_MSCR_SDR_SDCLK(x)		(((x) & 0x03) << 2)
+#define GPIO_MSCR_SDR_SDRAM(x)		((x) & 0x03)
+#define GPIO_MSCR_SDR_SDCLKB_UNMASK	(0xCF)
+#define GPIO_MSCR_SDR_SDCLK_UNMASK	(0xF3)
+#define GPIO_MSCR_SDR_SDRAM_UNMASK	(0xFC)
+
+#define MSCR_25VDDR			(0x03)
+#define MSCR_18VDDR_FULL		(0x02)
+#define MSCR_OPENDRAIN			(0x01)
+#define MSCR_18VDDR_HALF		(0x00)
+
+#define GPIO_DSCR_I2C(x)		((x) & 0x03)
+#define GPIO_DSCR_I2C_UNMASK		(0xFC)
+
+#define GPIO_DSCR_MISC_DBG(x)		(((x) & 0x03) << 4)
+#define GPIO_DSCR_MISC_DBG_UNMASK	(0xCF)
+#define GPIO_DSCR_MISC_RSTOUT(x)	(((x) & 0x03) << 2)
+#define GPIO_DSCR_MISC_RSTOUT_UNMASK	(0xF3)
+#define GPIO_DSCR_MISC_TIMER(x)		((x) & 0x03)
+#define GPIO_DSCR_MISC_TIMER_UNMASK	(0xFC)
+
+#define GPIO_DSCR_FEC(x)		((x) & 0x03)
+#define GPIO_DSCR_FEC_UNMASK		(0xFC)
+
+#define GPIO_DSCR_UART_UART1(x)		(((x) & 0x03) << 4)
+#define GPIO_DSCR_UART_UART1_UNMASK	(0xCF)
+#define GPIO_DSCR_UART_UART0(x)		(((x) & 0x03) << 2)
+#define GPIO_DSCR_UART_UART0_UNMASK	(0xF3)
+#define GPIO_DSCR_UART_IRQ(x)		((x) & 0x03)
+#define GPIO_DSCR_UART_IRQ_UNMASK	(0xFC)
+
+#define GPIO_DSCR_QSPI(x)		((x) & 0x03)
+#define GPIO_DSCR_QSPI_UNMASK		(0xFC)
+
+#define DSCR_50PF			(0x03)
+#define DSCR_30PF			(0x02)
+#define DSCR_20PF			(0x01)
+#define DSCR_10PF			(0x00)
+
+/* *** Phase Locked Loop (PLL) *** */
+#define PLL_PODR_CPUDIV(x)		(((x) & 0x0F) << 4)
+#define PLL_PODR_CPUDIV_UNMASK		(0x0F)
+#define PLL_PODR_BUSDIV(x)		((x) & 0x0F)
+#define PLL_PODR_BUSDIV_UNMASK		(0xF0)
+
+#define PLL_PCR_DITHEN			(0x80)
+#define PLL_PCR_DITHDEV(x)		((x) & 0x07)
+#define PLL_PCR_DITHDEV_UNMASK		(0xF8)
+
+#endif				/* __M520X__ */
diff --git a/arch/m68k/include/asm/m5227x.h b/arch/m68k/include/asm/m5227x.h
new file mode 100644
index 0000000..67c16e0
--- /dev/null
+++ b/arch/m68k/include/asm/m5227x.h
@@ -0,0 +1,546 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5227x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __MCF5227X__
+#define __MCF5227X__
+
+/* Interrupt Controller (INTC) */
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_EDMA_00			(8)
+#define INT0_LO_EDMA_01			(9)
+#define INT0_LO_EDMA_02			(10)
+#define INT0_LO_EDMA_03			(11)
+#define INT0_LO_EDMA_04			(12)
+#define INT0_LO_EDMA_05			(13)
+#define INT0_LO_EDMA_06			(14)
+#define INT0_LO_EDMA_07			(15)
+#define INT0_LO_EDMA_08			(16)
+#define INT0_LO_EDMA_09			(17)
+#define INT0_LO_EDMA_10			(18)
+#define INT0_LO_EDMA_11			(19)
+#define INT0_LO_EDMA_12			(20)
+#define INT0_LO_EDMA_13			(21)
+#define INT0_LO_EDMA_14			(22)
+#define INT0_LO_EDMA_15			(23)
+#define INT0_LO_EDMA_ERR		(24)
+#define INT0_LO_SCM_CWIC		(25)
+#define INT0_LO_UART0			(26)
+#define INT0_LO_UART1			(27)
+#define INT0_LO_UART2			(28)
+#define INT0_LO_I2C			(30)
+#define INT0_LO_DSPI			(31)
+#define INT0_HI_DTMR0			(32)
+#define INT0_HI_DTMR1			(33)
+#define INT0_HI_DTMR2			(34)
+#define INT0_HI_DTMR3			(35)
+#define INT0_HI_SCMIR			(62)
+#define INT0_HI_RTC_ISR			(63)
+
+#define INT1_HI_CAN_BOFFINT		(1)
+#define INT1_HI_CAN_ERRINT		(3)
+#define INT1_HI_CAN_BUF0I		(4)
+#define INT1_HI_CAN_BUF1I		(5)
+#define INT1_HI_CAN_BUF2I		(6)
+#define INT1_HI_CAN_BUF3I		(7)
+#define INT1_HI_CAN_BUF4I		(8)
+#define INT1_HI_CAN_BUF5I		(9)
+#define INT1_HI_CAN_BUF6I		(10)
+#define INT1_HI_CAN_BUF7I		(11)
+#define INT1_HI_CAN_BUF8I		(12)
+#define INT1_HI_CAN_BUF9I		(13)
+#define INT1_HI_CAN_BUF10I		(14)
+#define INT1_HI_CAN_BUF11I		(15)
+#define INT1_HI_CAN_BUF12I		(16)
+#define INT1_HI_CAN_BUF13I		(17)
+#define INT1_HI_CAN_BUF14I		(18)
+#define INT1_HI_CAN_BUF15I		(19)
+#define INT1_HI_PIT0_PIF		(43)
+#define INT1_HI_PIT1_PIF		(44)
+#define INT1_HI_USBOTG_STS		(47)
+#define INT1_HI_SSI_ISR			(49)
+#define INT1_HI_PWM_INT			(50)
+#define INT1_HI_LCDC_ISR		(51)
+#define INT1_HI_CCM_UOCSR		(53)
+#define INT1_HI_DSPI_EOQF		(54)
+#define INT1_HI_DSPI_TFFF		(55)
+#define INT1_HI_DSPI_TCF		(56)
+#define INT1_HI_DSPI_TFUF		(57)
+#define INT1_HI_DSPI_RFDF		(58)
+#define INT1_HI_DSPI_RFOF		(59)
+#define INT1_HI_DSPI_RFOF_TFUF		(60)
+#define INT1_HI_TOUCH_ADC		(61)
+#define INT1_HI_PLL_LOCKS		(62)
+
+/*********************************************************************
+* Reset Controller Module (RCM)
+*********************************************************************/
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT		(0x40)
+#define RCM_RCR_SOFTRST			(0x80)
+
+/* Bit definitions and macros for RSR */
+#define RCM_RSR_LOL			(0x01)
+#define RCM_RSR_WDR_CORE		(0x02)
+#define RCM_RSR_EXT			(0x04)
+#define RCM_RSR_POR			(0x08)
+#define RCM_RSR_SOFT			(0x20)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+
+/* Bit definitions and macros for CCR */
+#define CCM_CCR_DRAMSEL			(0x0100)
+#define CCM_CCR_CSC_UNMASK		(0xFF3F)
+#define CCM_CCR_CSC_FBCS5_CS4		(0x00C0)
+#define CCM_CCR_CSC_FBCS5_A22		(0x0080)
+#define CCM_CCR_CSC_FB_A23_A22		(0x0040)
+#define CCM_CCR_LIMP			(0x0020)
+#define CCM_CCR_LOAD			(0x0010)
+#define CCM_CCR_BOOTPS_UNMASK		(0xFFF3)
+#define CCM_CCR_BOOTPS_PS16		(0x0008)
+#define CCM_CCR_BOOTPS_PS8		(0x0004)
+#define CCM_CCR_BOOTPS_PS32		(0x0000)
+#define CCM_CCR_OSCMODE_OSCBYPASS	(0x0002)
+
+/* Bit definitions and macros for RCON */
+#define CCM_RCON_CSC_UNMASK		(0xFF3F)
+#define CCM_RCON_CSC_FBCS5_CS4		(0x00C0)
+#define CCM_RCON_CSC_FBCS5_A22		(0x0080)
+#define CCM_RCON_CSC_FB_A23_A22		(0x0040)
+#define CCM_RCON_LIMP			(0x0020)
+#define CCM_RCON_LOAD			(0x0010)
+#define CCM_RCON_BOOTPS_UNMASK		(0xFFF3)
+#define CCM_RCON_BOOTPS_PS16		(0x0008)
+#define CCM_RCON_BOOTPS_PS8		(0x0004)
+#define CCM_RCON_BOOTPS_PS32		(0x0000)
+#define CCM_RCON_OSCMODE_OSCBYPASS	(0x0002)
+
+/* Bit definitions and macros for CIR */
+#define CCM_CIR_PIN(x)			(((x) & 0xFFC0) >> 6)
+#define CCM_CIR_PRN(x)			((x) & 0x003F)
+#define CCM_CIR_PIN_MCF52277		(0x0000)
+
+/* Bit definitions and macros for MISCCR */
+#define CCM_MISCCR_RTCSRC		(0x4000)
+#define CCM_MISCCR_USBPUE		(0x2000)	/* USB transceiver pull-up */
+#define CCM_MISCCR_LIMP			(0x1000)	/* Limp mode enable */
+
+#define CCM_MISCCR_BME			(0x0800)	/* Bus monitor ext en bit */
+#define CCM_MISCCR_BMT_65536		(0)
+#define CCM_MISCCR_BMT_32768		(1)
+#define CCM_MISCCR_BMT_16384		(2)
+#define CCM_MISCCR_BMT_8192		(3)
+#define CCM_MISCCR_BMT_4096		(4)
+#define CCM_MISCCR_BMT_2048		(5)
+#define CCM_MISCCR_BMT_1024		(6)
+#define CCM_MISCCR_BMT_512		(7)
+
+#define CCM_MISCCR_SSIPUE		(0x0080)	/* SSI RXD/TXD pull enable */
+#define CCM_MISCCR_SSIPUS		(0x0040)	/* SSI RXD/TXD pull select */
+#define CCM_MISCCR_TIMDMA		(0x0020)	/* Timer DMA mux selection */
+#define CCM_MISCCR_SSISRC		(0x0010)	/* SSI clock source */
+#define CCM_MISCCR_LCDCHEN		(0x0004)	/* LCD Int CLK en */
+#define CCM_MISCCR_USBOC		(0x0002)	/* USB VBUS over-current sense pol */
+#define CCM_MISCCR_USBSRC		(0x0001)	/* USB clock source */
+
+/* Bit definitions and macros for CDR */
+#define CCM_CDR_USBDIV(x)		(((x)&0x0003)<<12)
+#define CCM_CDR_LPDIV(x)		(((x)&0x000F)<<8)	/* Low power clk div */
+#define CCM_CDR_SSIDIV(x)		(((x)&0x00FF))	/* SSI oversampling clk div */
+
+/* Bit definitions and macros for UOCSR */
+#define CCM_UOCSR_DPPD			(0x2000)	/* D+ 15Kohm pull-down (rd-only) */
+#define CCM_UOCSR_DMPD			(0x1000)	/* D- 15Kohm pull-down (rd-only) */
+#define CCM_UOCSR_CRG_VBUS		(0x0400)	/* VBUS charge resistor enabled (rd-only) */
+#define CCM_UOCSR_DCR_VBUS		(0x0200)	/* VBUS discharge resistor en (rd-only) */
+#define CCM_UOCSR_DPPU			(0x0100)	/* D+ pull-up for FS enabled (rd-only) */
+#define CCM_UOCSR_AVLD			(0x0080)	/* A-peripheral valid indicator */
+#define CCM_UOCSR_BVLD			(0x0040)	/* B-peripheral valid indicator */
+#define CCM_UOCSR_VVLD			(0x0020)	/* VBUS valid indicator */
+#define CCM_UOCSR_SEND			(0x0010)	/* Session end */
+#define CCM_UOCSR_WKUP			(0x0004)	/* USB OTG controller wake-up event */
+#define CCM_UOCSR_UOMIE			(0x0002)	/* USB OTG misc interrupt en */
+#define CCM_UOCSR_XPDE			(0x0001)	/* On-chip transceiver pull-down en */
+
+/*********************************************************************
+* General Purpose I/O Module (GPIO)
+*********************************************************************/
+/* Bit definitions and macros for PAR_BE */
+#define GPIO_PAR_BE_UNMASK		(0x0F)
+#define GPIO_PAR_BE_BE3_BE3		(0x08)
+#define GPIO_PAR_BE_BE3_GPIO		(0x00)
+#define GPIO_PAR_BE_BE2_BE2		(0x04)
+#define GPIO_PAR_BE_BE2_GPIO		(0x00)
+#define GPIO_PAR_BE_BE1_BE1		(0x02)
+#define GPIO_PAR_BE_BE1_GPIO		(0x00)
+#define GPIO_PAR_BE_BE0_BE0		(0x01)
+#define GPIO_PAR_BE_BE0_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_CS */
+#define GPIO_PAR_CS_CS3			(0x10)
+#define GPIO_PAR_CS_CS2			(0x08)
+#define GPIO_PAR_CS_CS1_FBCS1		(0x06)
+#define GPIO_PAR_CS_CS1_SDCS1		(0x04)
+#define GPIO_PAR_CS_CS1_GPIO		(0x00)
+#define GPIO_PAR_CS_CS0			(0x01)
+
+/* Bit definitions and macros for PAR_FBCTL */
+#define GPIO_PAR_FBCTL_OE		(0x80)
+#define GPIO_PAR_FBCTL_TA		(0x40)
+#define GPIO_PAR_FBCTL_RW		(0x20)
+#define GPIO_PAR_FBCTL_TS_UNMASK	(0xE7)
+#define GPIO_PAR_FBCTL_TS_FBTS		(0x18)
+#define GPIO_PAR_FBCTL_TS_DMAACK	(0x10)
+#define GPIO_PAR_FBCTL_TS_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_FECI2C */
+#define GPIO_PAR_I2C_SCL_UNMASK		(0xF3)
+#define GPIO_PAR_I2C_SCL_SCL		(0x0C)
+#define GPIO_PAR_I2C_SCL_CANTXD		(0x08)
+#define GPIO_PAR_I2C_SCL_U2TXD		(0x04)
+#define GPIO_PAR_I2C_SCL_GPIO		(0x00)
+
+#define GPIO_PAR_I2C_SDA_UNMASK		(0xFC)
+#define GPIO_PAR_I2C_SDA_SDA		(0x03)
+#define GPIO_PAR_I2C_SDA_CANRXD		(0x02)
+#define GPIO_PAR_I2C_SDA_U2RXD		(0x01)
+#define GPIO_PAR_I2C_SDA_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_UART */
+#define GPIO_PAR_UART_U1CTS_UNMASK	(0x3FFF)
+#define GPIO_PAR_UART_U1CTS_U1CTS	(0xC000)
+#define GPIO_PAR_UART_U1CTS_SSIBCLK	(0x8000)
+#define GPIO_PAR_UART_U1CTS_LCDCLS	(0x4000)
+#define GPIO_PAR_UART_U1CTS_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U1RTS_UNMASK	(0xCFFF)
+#define GPIO_PAR_UART_U1RTS_U1RTS	(0x3000)
+#define GPIO_PAR_UART_U1RTS_SSIFS	(0x2000)
+#define GPIO_PAR_UART_U1RTS_LCDPS	(0x1000)
+#define GPIO_PAR_UART_U1RTS_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U1RXD_UNMASK	(0xF3FF)
+#define GPIO_PAR_UART_U1RXD_U1RXD	(0x0C00)
+#define GPIO_PAR_UART_U1RXD_SSIRXD	(0x0800)
+#define GPIO_PAR_UART_U1RXD_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U1TXD_UNMASK	(0xFCFF)
+#define GPIO_PAR_UART_U1TXD_U1TXD	(0x0300)
+#define GPIO_PAR_UART_U1TXD_SSITXD	(0x0200)
+#define GPIO_PAR_UART_U1TXD_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U0CTS_UNMASK	(0xFF3F)
+#define GPIO_PAR_UART_U0CTS_U0CTS	(0x00C0)
+#define GPIO_PAR_UART_U0CTS_T1OUT	(0x0080)
+#define GPIO_PAR_UART_U0CTS_USBVBUSEN	(0x0040)
+#define GPIO_PAR_UART_U0CTS_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U0RTS_UNMASK	(0xFFCF)
+#define GPIO_PAR_UART_U0RTS_U0RTS	(0x0030)
+#define GPIO_PAR_UART_U0RTS_T1IN	(0x0020)
+#define GPIO_PAR_UART_U0RTS_USBVBUSOC	(0x0010)
+#define GPIO_PAR_UART_U0RTS_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U0RXD_UNMASK	(0xFFF3)
+#define GPIO_PAR_UART_U0RXD_U0RXD	(0x000C)
+#define GPIO_PAR_UART_U0RXD_CANRX	(0x0008)
+#define GPIO_PAR_UART_U0RXD_GPIO	(0x0000)
+
+#define GPIO_PAR_UART_U0TXD_UNMASK	(0xFFFC)
+#define GPIO_PAR_UART_U0TXD_U0TXD	(0x0003)
+#define GPIO_PAR_UART_U0TXD_CANTX	(0x0002)
+#define GPIO_PAR_UART_U0TXD_GPIO	(0x0000)
+
+/* Bit definitions and macros for PAR_DSPI */
+#define GPIO_PAR_DSPI_PCS0_UNMASK	(0x3F)
+#define GPIO_PAR_DSPI_PCS0_PCS0		(0xC0)
+#define GPIO_PAR_DSPI_PCS0_U2RTS	(0x80)
+#define GPIO_PAR_DSPI_PCS0_GPIO		(0x00)
+#define GPIO_PAR_DSPI_SIN_UNMASK	(0xCF)
+#define GPIO_PAR_DSPI_SIN_SIN		(0x30)
+#define GPIO_PAR_DSPI_SIN_U2RXD		(0x20)
+#define GPIO_PAR_DSPI_SIN_GPIO		(0x00)
+#define GPIO_PAR_DSPI_SOUT_UNMASK	(0xF3)
+#define GPIO_PAR_DSPI_SOUT_SOUT		(0x0C)
+#define GPIO_PAR_DSPI_SOUT_U2TXD	(0x08)
+#define GPIO_PAR_DSPI_SOUT_GPIO		(0x00)
+#define GPIO_PAR_DSPI_SCK_UNMASK	(0xFC)
+#define GPIO_PAR_DSPI_SCK_SCK		(0x03)
+#define GPIO_PAR_DSPI_SCK_U2CTS		(0x02)
+#define GPIO_PAR_DSPI_SCK_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_TIMER */
+#define GPIO_PAR_TIMER_T3IN_UNMASK	(0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
+#define GPIO_PAR_TIMER_T3IN_SSIMCLK	(0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T2IN_UNMASK	(0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
+#define GPIO_PAR_TIMER_T2IN_DSPIPCS2	(0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T1IN_UNMASK	(0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
+#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST	(0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T0IN_UNMASK	(0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
+#define GPIO_PAR_TIMER_T0IN_LCDREV	(0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO	(0x00)
+
+/* Bit definitions and macros for GPIO_PAR_LCDCTL */
+#define GPIO_PAR_LCDCTL_ACDOE_UNMASK	(0xE7)
+#define GPIO_PAR_LCDCTL_ACDOE_ACDOE	(0x18)
+#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR	(0x10)
+#define GPIO_PAR_LCDCTL_ACDOE_GPIO	(0x00)
+#define GPIO_PAR_LCDCTL_FLM_VSYNC	(0x04)
+#define GPIO_PAR_LCDCTL_LP_HSYNC	(0x02)
+#define GPIO_PAR_LCDCTL_LSCLK		(0x01)
+
+/* Bit definitions and macros for PAR_IRQ */
+#define GPIO_PAR_IRQ_IRQ4_UNMASK	(0xF3)
+#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK	(0x0C)
+#define GPIO_PAR_IRQ_IRQ4_DMAREQ0	(0x08)
+#define GPIO_PAR_IRQ_IRQ4_GPIO		(0x00)
+#define GPIO_PAR_IRQ_IRQ1_UNMASK	(0xFC)
+#define GPIO_PAR_IRQ_IRQ1_PCIINT	(0x03)
+#define GPIO_PAR_IRQ_IRQ1_USBCLKIN	(0x02)
+#define GPIO_PAR_IRQ_IRQ1_SSICLKIN	(0x01)
+#define GPIO_PAR_IRQ_IRQ1_GPIO		(0x00)
+
+/* Bit definitions and macros for GPIO_PAR_LCDH */
+#define GPIO_PAR_LCDH_LD17_UNMASK	(0xFFFFF3FF)
+#define GPIO_PAR_LCDH_LD17_LD17		(0x00000C00)
+#define GPIO_PAR_LCDH_LD17_LD11		(0x00000800)
+#define GPIO_PAR_LCDH_LD17_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDH_LD16_UNMASK	(0xFFFFFCFF)
+#define GPIO_PAR_LCDH_LD16_LD16		(0x00000300)
+#define GPIO_PAR_LCDH_LD16_LD10		(0x00000200)
+#define GPIO_PAR_LCDH_LD16_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDH_LD15_UNMASK	(0xFFFFFF3F)
+#define GPIO_PAR_LCDH_LD15_LD15		(0x000000C0)
+#define GPIO_PAR_LCDH_LD15_LD9		(0x00000080)
+#define GPIO_PAR_LCDH_LD15_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDH_LD14_UNMASK	(0xFFFFFFCF)
+#define GPIO_PAR_LCDH_LD14_LD14		(0x00000030)
+#define GPIO_PAR_LCDH_LD14_LD8		(0x00000020)
+#define GPIO_PAR_LCDH_LD14_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDH_LD13_UNMASK	(0xFFFFFFF3)
+#define GPIO_PAR_LCDH_LD13_LD13		(0x0000000C)
+#define GPIO_PAR_LCDH_LD13_CANTX	(0x00000008)
+#define GPIO_PAR_LCDH_LD13_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDH_LD12_UNMASK	(0xFFFFFFFC)
+#define GPIO_PAR_LCDH_LD12_LD12		(0x00000003)
+#define GPIO_PAR_LCDH_LD12_CANRX	(0x00000002)
+#define GPIO_PAR_LCDH_LD12_GPIO		(0x00000000)
+
+/* Bit definitions and macros for GPIO_PAR_LCDL */
+#define GPIO_PAR_LCDL_LD11_UNMASK	(0x3FFFFFFF)
+#define GPIO_PAR_LCDL_LD11_LD11		(0xC0000000)
+#define GPIO_PAR_LCDL_LD11_LD7		(0x80000000)
+#define GPIO_PAR_LCDL_LD11_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD10_UNMASK	(0xCFFFFFFF)
+#define GPIO_PAR_LCDL_LD10_LD10		(0x30000000)
+#define GPIO_PAR_LCDL_LD10_LD6		(0x20000000)
+#define GPIO_PAR_LCDL_LD10_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD9_UNMASK	(0xF3FFFFFF)
+#define GPIO_PAR_LCDL_LD9_LD9		(0x0C000000)
+#define GPIO_PAR_LCDL_LD9_LD5		(0x08000000)
+#define GPIO_PAR_LCDL_LD9_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD8_UNMASK	(0xFCFFFFFF)
+#define GPIO_PAR_LCDL_LD8_LD8		(0x03000000)
+#define GPIO_PAR_LCDL_LD8_LD4		(0x02000000)
+#define GPIO_PAR_LCDL_LD8_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD7_UNMASK	(0xFF3FFFFF)
+#define GPIO_PAR_LCDL_LD7_LD7		(0x00C00000)
+#define GPIO_PAR_LCDL_LD7_PWM7		(0x00800000)
+#define GPIO_PAR_LCDL_LD7_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD6_UNMASK	(0xFFCFFFFF)
+#define GPIO_PAR_LCDL_LD6_LD6		(0x00300000)
+#define GPIO_PAR_LCDL_LD6_PWM5		(0x00200000)
+#define GPIO_PAR_LCDL_LD6_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD5_UNMASK	(0xFFF3FFFF)
+#define GPIO_PAR_LCDL_LD5_LD5		(0x000C0000)
+#define GPIO_PAR_LCDL_LD5_LD3		(0x00080000)
+#define GPIO_PAR_LCDL_LD5_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD4_UNMASK	(0xFFFCFFFF)
+#define GPIO_PAR_LCDL_LD4_LD4		(0x00030000)
+#define GPIO_PAR_LCDL_LD4_LD2		(0x00020000)
+#define GPIO_PAR_LCDL_LD4_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD3_UNMASK	(0xFFFF3FFF)
+#define GPIO_PAR_LCDL_LD3_LD3		(0x0000C000)
+#define GPIO_PAR_LCDL_LD3_LD1		(0x00008000)
+#define GPIO_PAR_LCDL_LD3_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD2_UNMASK	(0xFFFFCFFF)
+#define GPIO_PAR_LCDL_LD2_LD2		(0x00003000)
+#define GPIO_PAR_LCDL_LD2_LD0		(0x00002000)
+#define GPIO_PAR_LCDL_LD2_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD1_UNMASK	(0xFFFFF3FF)
+#define GPIO_PAR_LCDL_LD1_LD1		(0x00000C00)
+#define GPIO_PAR_LCDL_LD1_PWM3		(0x00000800)
+#define GPIO_PAR_LCDL_LD1_GPIO		(0x00000000)
+
+#define GPIO_PAR_LCDL_LD0_UNMASK	(0xFFFFFCFF)
+#define GPIO_PAR_LCDL_LD0_LD0		(0x00000300)
+#define GPIO_PAR_LCDL_LD0_PWM1		(0x00000200)
+#define GPIO_PAR_LCDL_LD0_GPIO		(0x00000000)
+
+/* Bit definitions and macros for MSCR_FB */
+#define GPIO_MSCR_FB_DUPPER_UNMASK	(0xCF)
+#define GPIO_MSCR_FB_DUPPER_25V_33V	(0x30)
+#define GPIO_MSCR_FB_DUPPER_FULL_18V	(0x20)
+#define GPIO_MSCR_FB_DUPPER_OD		(0x10)
+#define GPIO_MSCR_FB_DUPPER_HALF_18V	(0x00)
+
+#define GPIO_MSCR_FB_DLOWER_UNMASK	(0xF3)
+#define GPIO_MSCR_FB_DLOWER_25V_33V	(0x0C)
+#define GPIO_MSCR_FB_DLOWER_FULL_18V	(0x08)
+#define GPIO_MSCR_FB_DLOWER_OD		(0x04)
+#define GPIO_MSCR_FB_DLOWER_HALF_18V	(0x00)
+
+#define GPIO_MSCR_FB_ADDRCTL_UNMASK	(0xFC)
+#define GPIO_MSCR_FB_ADDRCTL_25V_33V	(0x03)
+#define GPIO_MSCR_FB_ADDRCTL_FULL_18V	(0x02)
+#define GPIO_MSCR_FB_ADDRCTL_OD		(0x01)
+#define GPIO_MSCR_FB_ADDRCTL_HALF_18V	(0x00)
+
+/* Bit definitions and macros for MSCR_SDRAM */
+#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK	(0xCF)
+#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V	(0x30)
+#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V	(0x20)
+#define GPIO_MSCR_SDRAM_SDCLKB_OD	(0x10)
+#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V	(0x00)
+
+#define GPIO_MSCR_SDRAM_SDCLK_UNMASK	(0xF3)
+#define GPIO_MSCR_SDRAM_SDCLK_25V_33V	(0x0C)
+#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V	(0x08)
+#define GPIO_MSCR_SDRAM_SDCLK_OPD	(0x04)
+#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V	(0x00)
+
+#define GPIO_MSCR_SDRAM_SDCTL_UNMASK	(0xFC)
+#define GPIO_MSCR_SDRAM_SDCTL_25V_33V	(0x03)
+#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V	(0x02)
+#define GPIO_MSCR_SDRAM_SDCTL_OPD	(0x01)
+#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V	(0x00)
+
+/* Bit definitions and macros for Drive Strength Control */
+#define DSCR_LOAD_50PF	(0x03)
+#define DSCR_LOAD_30PF	(0x02)
+#define DSCR_LOAD_20PF	(0x01)
+#define DSCR_LOAD_10PF	(0x00)
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+
+/* Bit definitions and macros for SDMR */
+#define SDRAMC_SDMR_DDR2_AD(x)		(((x)&0x00003FFF))	/* Address for DDR2 */
+#define SDRAMC_SDMR_CMD			(0x00010000)	/* Command */
+#define SDRAMC_SDMR_AD(x)		(((x)&0x00000FFF)<<18)	/* Address */
+#define SDRAMC_SDMR_BK(x)		(((x)&0x00000003)<<30)	/* Bank Address */
+#define SDRAMC_SDMR_BK_LMR		(0x00000000)
+#define SDRAMC_SDMR_BK_LEMR		(0x40000000)
+
+/* Bit definitions and macros for SDCR */
+#define SDRAMC_SDCR_DPD			(0x00000001)	/* Deep Power-Down Mode */
+#define SDRAMC_SDCR_IPALL		(0x00000002)	/* Initiate Precharge All */
+#define SDRAMC_SDCR_IREF		(0x00000004)	/* Initiate Refresh */
+#define SDRAMC_SDCR_DQS_OE(x)		(((x)&0x00000003)<<10)	/* DQS Output Enable */
+#define SDRAMC_SDCR_MEM_PS		(0x00002000)	/* Data Port Size */
+#define SDRAMC_SDCR_REF_CNT(x)		(((x)&0x0000003F)<<16)	/* Periodic Refresh Counter */
+#define SDRAMC_SDCR_OE_RULE		(0x00400000)	/* Drive Rule Selection */
+#define SDRAMC_SDCR_ADDR_MUX(x)		(((x)&0x00000003)<<24)	/* Internal Address Mux Select */
+#define SDRAMC_SDCR_DDR2_MODE		(0x08000000)	/* DDR2 Mode Select */
+#define SDRAMC_SDCR_REF_EN		(0x10000000)	/* Refresh Enable */
+#define SDRAMC_SDCR_DDR_MODE		(0x20000000)	/* DDR Mode Select */
+#define SDRAMC_SDCR_CKE			(0x40000000)	/* Clock Enable */
+#define SDRAMC_SDCR_MODE_EN		(0x80000000)	/* SDRAM Mode Register Programming Enable */
+#define SDRAMC_SDCR_DQS_OE_BOTH		(0x00000C000)
+
+/* Bit definitions and macros for SDCFG1 */
+#define SDRAMC_SDCFG1_WT_LAT(x)		(((x)&0x00000007)<<4)	/* Write Latency */
+#define SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8)	/* Refresh to active delay */
+#define SDRAMC_SDCFG1_PRE2ACT(x)	(((x)&0x00000007)<<12)	/* Precharge to active delay */
+#define SDRAMC_SDCFG1_ACT2RW(x)		(((x)&0x00000007)<<16)	/* Active to read/write delay */
+#define SDRAMC_SDCFG1_RD_LAT(x)		(((x)&0x0000000F)<<20)	/* Read CAS Latency */
+#define SDRAMC_SDCFG1_SWT2RWP(x)	(((x)&0x00000007)<<24)	/* Single write to read/write/precharge delay */
+#define SDRAMC_SDCFG1_SRD2RWP(x)	(((x)&0x0000000F)<<28)	/* Single read to read/write/precharge delay */
+
+/* Bit definitions and macros for SDCFG2 */
+#define SDRAMC_SDCFG2_BL(x)		(((x)&0x0000000F)<<16)	/* Burst Length */
+#define SDRAMC_SDCFG2_BRD2W(x)		(((x)&0x0000000F)<<20)	/* Burst read to write delay */
+#define SDRAMC_SDCFG2_BWT2RWP(x)	(((x)&0x0000000F)<<24)	/* Burst write to read/write/precharge delay */
+#define SDRAMC_SDCFG2_BRD2RP(x)		(((x)&0x0000000F)<<28)	/* Burst read to read/precharge delay */
+
+/* Bit definitions and macros for SDCS group */
+#define SDRAMC_SDCS_CSSZ(x)		(((x)&0x0000001F))	/* Chip-Select Size */
+#define SDRAMC_SDCS_CSBA(x)		(((x)&0x00000FFF)<<20)	/* Chip-Select Base Address */
+#define SDRAMC_SDCS_BA(x)		((x)&0xFFF00000)
+#define SDRAMC_SDCS_CSSZ_DISABLE	(0x00000000)
+#define SDRAMC_SDCS_CSSZ_1MBYTE		(0x00000013)
+#define SDRAMC_SDCS_CSSZ_2MBYTE		(0x00000014)
+#define SDRAMC_SDCS_CSSZ_4MBYTE		(0x00000015)
+#define SDRAMC_SDCS_CSSZ_8MBYTE		(0x00000016)
+#define SDRAMC_SDCS_CSSZ_16MBYTE	(0x00000017)
+#define SDRAMC_SDCS_CSSZ_32MBYTE	(0x00000018)
+#define SDRAMC_SDCS_CSSZ_64MBYTE	(0x00000019)
+#define SDRAMC_SDCS_CSSZ_128MBYTE	(0x0000001A)
+#define SDRAMC_SDCS_CSSZ_256MBYTE	(0x0000001B)
+#define SDRAMC_SDCS_CSSZ_512MBYTE	(0x0000001C)
+#define SDRAMC_SDCS_CSSZ_1GBYTE		(0x0000001D)
+#define SDRAMC_SDCS_CSSZ_2GBYTE		(0x0000001E)
+#define SDRAMC_SDCS_CSSZ_4GBYTE		(0x0000001F)
+
+/*********************************************************************
+* Phase Locked Loop (PLL)
+*********************************************************************/
+
+/* Bit definitions and macros for PCR */
+#define PLL_PCR_OUTDIV1(x)		(((x)&0x0000000F))	/* Output divider for CPU clock frequency */
+#define PLL_PCR_OUTDIV2(x)		(((x)&0x0000000F)<<4)	/* Output divider for bus/flexbus clock frequency */
+#define PLL_PCR_OUTDIV3(x)		(((x)&0x0000000F)<<8)	/* Output divider for SDRAM clock frequency */
+#define PLL_PCR_OUTDIV5(x)		(((x)&0x0000000F)<<16)	/* Output divider for USB clock frequency */
+#define PLL_PCR_PFDR(x)			(((x)&0x000000FF)<<24)	/* Feedback divider for VCO frequency */
+#define PLL_PCR_PFDR_MASK		(0x000F0000)
+#define PLL_PCR_OUTDIV5_MASK		(0x000F0000)
+#define PLL_PCR_OUTDIV3_MASK		(0x00000F00)
+#define PLL_PCR_OUTDIV2_MASK		(0x000000F0)
+#define PLL_PCR_OUTDIV1_MASK		(0x0000000F)
+
+/* Bit definitions and macros for PSR */
+#define PLL_PSR_LOCKS			(0x00000001)	/* PLL lost lock - sticky */
+#define PLL_PSR_LOCK			(0x00000002)	/* PLL lock status */
+#define PLL_PSR_LOLIRQ			(0x00000004)	/* PLL loss-of-lock interrupt enable */
+#define PLL_PSR_LOLRE			(0x00000008)	/* PLL loss-of-lock reset enable */
+
+/********************************************************************/
+
+#endif				/* __MCF5227X__ */
diff --git a/arch/m68k/include/asm/m5235.h b/arch/m68k/include/asm/m5235.h
new file mode 100644
index 0000000..2d942f3
--- /dev/null
+++ b/arch/m68k/include/asm/m5235.h
@@ -0,0 +1,585 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * mcf5329.h -- Definitions for Freescale Coldfire 5329
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef mcf5235_h
+#define mcf5235_h
+/****************************************************************************/
+
+/*********************************************************************
+* System Control Module (SCM)
+*********************************************************************/
+
+/* Bit definition and macros for SCM_IPSBAR */
+#define SCM_IPSBAR_BA(x)		(((x)&0x03)<<30)
+#define SCM_IPSBAR_V			(0x00000001)
+
+/* Bit definition and macros for SCM_RAMBAR */
+#define SCM_RAMBAR_BA(x)		(((x)&0xFFFF)<<16)
+#define SCM_RAMBAR_BDE			(0x00000200)
+
+/* Bit definition and macros for SCM_CRSR */
+#define SCM_CRSR_EXT			(0x80)
+
+/* Bit definitions and macros for SCM_CWCR */
+#define SCM_CWCR_CWE			(0x80)
+#define SCM_CWCR_CWRI			(0x40)
+#define SCM_CWCR_CWT(x)			(((x)&0x07)<<3)
+#define SCM_CWCR_CWTA			(0x04)
+#define SCM_CWCR_CWTAVAL		(0x02)
+#define SCM_CWCR_CWTIC			(0x01)
+
+/* Bit definitions and macros for SCM_LPICR */
+#define SCM_LPICR_ENBSTOP		(0x80)
+#define SCM_LPICR_XLPM_IPL(x)		(((x)&0x07)<<4)
+#define SCM_LPICR_XLPM_IPL_ANY		(0x00)
+#define SCM_LPICR_XLPM_IPL_L2_7		(0x10)
+#define SCM_LPICR_XLPM_IPL_L3_7		(0x20)
+#define SCM_LPICR_XLPM_IPL_L4_7		(0x30)
+#define SCM_LPICR_XLPM_IPL_L5_7		(0x40)
+#define SCM_LPICR_XLPM_IPL_L6_7		(0x50)
+#define SCM_LPICR_XLPM_IPL_L7		(0x70)
+
+/* Bit definitions and macros for SCM_DMAREQC */
+#define SCM_DMAREQC_EXT(x)		(((x)&0x0F)<<16)
+#define SCM_DMAREQC_EXT_ETPU		(0x00080000)
+#define SCM_DMAREQC_EXT_EXTDREQ2	(0x00040000)
+#define SCM_DMAREQC_EXT_EXTDREQ1	(0x00020000)
+#define SCM_DMAREQC_EXT_EXTDREQ0	(0x00010000)
+#define SCM_DMAREQC_DMAC3(x)		(((x)&0x0F)<<12)
+#define SCM_DMAREQC_DMAC2(x)		(((x)&0x0F)<<8)
+#define SCM_DMAREQC_DMAC1(x)		(((x)&0x0F)<<4)
+#define SCM_DMAREQC_DMAC0(x)		(((x)&0x0F))
+#define SCM_DMAREQC_DMACn_DTMR0		(0x04)
+#define SCM_DMAREQC_DMACn_DTMR1		(0x05)
+#define SCM_DMAREQC_DMACn_DTMR2		(0x06)
+#define SCM_DMAREQC_DMACn_DTMR3		(0x07)
+#define SCM_DMAREQC_DMACn_UART0RX	(0x08)
+#define SCM_DMAREQC_DMACn_UART1RX	(0x09)
+#define SCM_DMAREQC_DMACn_UART2RX	(0x0A)
+#define SCM_DMAREQC_DMACn_UART0TX	(0x0C)
+#define SCM_DMAREQC_DMACn_UART1TX	(0x0D)
+#define SCM_DMAREQC_DMACn_UART3TX	(0x0E)
+
+/* Bit definitions and macros for SCM_MPARK */
+#define SCM_MPARK_M2_P_EN		(0x02000000)
+#define SCM_MPARK_M3_PRTY_MSK		(0x00C00000)
+#define SCM_MPARK_M3_PRTY_4TH		(0x00000000)
+#define SCM_MPARK_M3_PRTY_3RD		(0x00400000)
+#define SCM_MPARK_M3_PRTY_2ND		(0x00800000)
+#define SCM_MPARK_M3_PRTY_1ST		(0x00C00000)
+#define SCM_MPARK_M2_PRTY_MSK		(0x00300000)
+#define SCM_MPARK_M2_PRTY_4TH		(0x00000000)
+#define SCM_MPARK_M2_PRTY_3RD		(0x00100000)
+#define SCM_MPARK_M2_PRTY_2ND		(0x00200000)
+#define SCM_MPARK_M2_PRTY_1ST		(0x00300000)
+#define SCM_MPARK_M0_PRTY_MSK		(0x000C0000)
+#define SCM_MPARK_M0_PRTY_4TH		(0x00000000)
+#define SCM_MPARK_M0_PRTY_3RD		(0x00040000)
+#define SCM_MPARK_M0_PRTY_2ND		(0x00080000)
+#define SCM_MPARK_M0_PRTY_1ST		(0x000C0000)
+#define SCM_MPARK_FIXED			(0x00004000)
+#define SCM_MPARK_TIMEOUT		(0x00002000)
+#define SCM_MPARK_PRKLAST		(0x00001000)
+#define SCM_MPARK_LCKOUT_TIME(x)	(((x)&0x0F)<<8)
+
+/* Bit definitions and macros for SCM_MPR */
+#define SCM_MPR_MPR3			(0x08)
+#define SCM_MPR_MPR2			(0x04)
+#define SCM_MPR_MPR1			(0x02)
+#define SCM_MPR_MPR0			(0x01)
+
+/* Bit definitions and macros for SCM_PACRn */
+#define SCM_PACRn_LOCK1			(0x80)
+#define SCM_PACRn_ACCESSCTRL1(x)	(((x)&0x07)<<4)
+#define SCM_PACRn_LOCK0			(0x08)
+#define SCM_PACRn_ACCESSCTRL0(x)	(((x)&0x07))
+
+/* Bit definitions and macros for SCM_GPACR */
+#define SCM_PACRn_LOCK			(0x80)
+#define SCM_PACRn_ACCESSCTRL0(x)	(((x)&0x07))
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+/* Bit definitions and macros for SDRAMC_DCR */
+#define SDRAMC_DCR_NAM			(0x2000)
+#define SDRAMC_DCR_COC			(0x1000)
+#define SDRAMC_DCR_IS			(0x0800)
+#define SDRAMC_DCR_RTIM_MASK		(0x0C00)
+#define SDRAMC_DCR_RTIM_3CLKS		(0x0000)
+#define SDRAMC_DCR_RTIM_6CLKS		(0x0200)
+#define SDRAMC_DCR_RTIM_9CLKS		(0x0400)
+#define SDRAMC_DCR_RC(x)		(((x)&0xFF)<<8)
+
+/* Bit definitions and macros for SDRAMC_DARCn */
+#define SDRAMC_DARCn_BA(x)		((x)&0xFFFC0000)
+#define SDRAMC_DARCn_RE			(0x00008000)
+#define SDRAMC_DARCn_CASL_MASK		(0x00003000)
+#define SDRAMC_DARCn_CASL_C0		(0x00000000)
+#define SDRAMC_DARCn_CASL_C1		(0x00001000)
+#define SDRAMC_DARCn_CASL_C2		(0x00002000)
+#define SDRAMC_DARCn_CASL_C3		(0x00003000)
+#define SDRAMC_DARCn_CBM_MASK		(0x00000700)
+#define SDRAMC_DARCn_CBM_CMD17		(0x00000000)
+#define SDRAMC_DARCn_CBM_CMD18		(0x00000100)
+#define SDRAMC_DARCn_CBM_CMD19		(0x00000200)
+#define SDRAMC_DARCn_CBM_CMD20		(0x00000300)
+#define SDRAMC_DARCn_CBM_CMD21		(0x00000400)
+#define SDRAMC_DARCn_CBM_CMD22		(0x00000500)
+#define SDRAMC_DARCn_CBM_CMD23		(0x00000600)
+#define SDRAMC_DARCn_CBM_CMD24		(0x00000700)
+#define SDRAMC_DARCn_IMRS		(0x00000040)
+#define SDRAMC_DARCn_PS_MASK		(0x00000030)
+#define SDRAMC_DARCn_PS_32		(0x00000000)
+#define SDRAMC_DARCn_PS_16		(0x00000010)
+#define SDRAMC_DARCn_PS_8		(0x00000020)
+#define SDRAMC_DARCn_IP			(0x00000008)
+
+/* Bit definitions and macros for SDRAMC_DMRn */
+#define SDRAMC_DMRn_BAM(x)		(((x)&0x3FFF)<<18)
+#define SDRAMC_DMRn_WP			(0x00000100)
+#define SDRAMC_DMRn_V			(0x00000001)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_SCM			(8)
+#define INT0_LO_DMA0			(9)
+#define INT0_LO_DMA1			(10)
+#define INT0_LO_DMA2			(11)
+#define INT0_LO_DMA3			(12)
+#define INT0_LO_UART0			(13)
+#define INT0_LO_UART1			(14)
+#define INT0_LO_UART2			(15)
+#define INT0_LO_RSVD1			(16)
+#define INT0_LO_I2C			(17)
+#define INT0_LO_QSPI			(18)
+#define INT0_LO_DTMR0			(19)
+#define INT0_LO_DTMR1			(20)
+#define INT0_LO_DTMR2			(21)
+#define INT0_LO_DTMR3			(22)
+#define INT0_LO_FEC_TXF			(23)
+#define INT0_LO_FEC_TXB			(24)
+#define INT0_LO_FEC_UN			(25)
+#define INT0_LO_FEC_RL			(26)
+#define INT0_LO_FEC_RXF			(27)
+#define INT0_LO_FEC_RXB			(28)
+#define INT0_LO_FEC_MII			(29)
+#define INT0_LO_FEC_LC			(30)
+#define INT0_LO_FEC_HBERR		(31)
+#define INT0_HI_FEC_GRA			(32)
+#define INT0_HI_FEC_EBERR		(33)
+#define INT0_HI_FEC_BABT		(34)
+#define INT0_HI_FEC_BABR		(35)
+#define INT0_HI_PIT0			(36)
+#define INT0_HI_PIT1			(37)
+#define INT0_HI_PIT2			(38)
+#define INT0_HI_PIT3			(39)
+#define INT0_HI_RNG			(40)
+#define INT0_HI_SKHA			(41)
+#define INT0_HI_MDHA			(42)
+#define INT0_HI_CAN1_BUF0I		(43)
+#define INT0_HI_CAN1_BUF1I		(44)
+#define INT0_HI_CAN1_BUF2I		(45)
+#define INT0_HI_CAN1_BUF3I		(46)
+#define INT0_HI_CAN1_BUF4I		(47)
+#define INT0_HI_CAN1_BUF5I		(48)
+#define INT0_HI_CAN1_BUF6I		(49)
+#define INT0_HI_CAN1_BUF7I		(50)
+#define INT0_HI_CAN1_BUF8I		(51)
+#define INT0_HI_CAN1_BUF9I		(52)
+#define INT0_HI_CAN1_BUF10I		(53)
+#define INT0_HI_CAN1_BUF11I		(54)
+#define INT0_HI_CAN1_BUF12I		(55)
+#define INT0_HI_CAN1_BUF13I		(56)
+#define INT0_HI_CAN1_BUF14I		(57)
+#define INT0_HI_CAN1_BUF15I		(58)
+#define INT0_HI_CAN1_ERRINT		(59)
+#define INT0_HI_CAN1_BOFFINT		(60)
+/* 60-63 Reserved */
+
+/* 0 - 7 Reserved */
+#define INT1_LO_CAN1_BUF0I		(8)
+#define INT1_LO_CAN1_BUF1I		(9)
+#define INT1_LO_CAN1_BUF2I		(10)
+#define INT1_LO_CAN1_BUF3I		(11)
+#define INT1_LO_CAN1_BUF4I		(12)
+#define INT1_LO_CAN1_BUF5I		(13)
+#define INT1_LO_CAN1_BUF6I		(14)
+#define INT1_LO_CAN1_BUF7I		(15)
+#define INT1_LO_CAN1_BUF8I		(16)
+#define INT1_LO_CAN1_BUF9I		(17)
+#define INT1_LO_CAN1_BUF10I		(18)
+#define INT1_LO_CAN1_BUF11I		(19)
+#define INT1_LO_CAN1_BUF12I		(20)
+#define INT1_LO_CAN1_BUF13I		(21)
+#define INT1_LO_CAN1_BUF14I		(22)
+#define INT1_LO_CAN1_BUF15I		(23)
+#define INT1_LO_CAN1_ERRINT		(24)
+#define INT1_LO_CAN1_BOFFINT		(25)
+/* 26 Reserved */
+#define INT1_LO_ETPU_TC0F		(27)
+#define INT1_LO_ETPU_TC1F		(28)
+#define INT1_LO_ETPU_TC2F		(29)
+#define INT1_LO_ETPU_TC3F		(30)
+#define INT1_LO_ETPU_TC4F		(31)
+#define INT1_HI_ETPU_TC5F		(32)
+#define INT1_HI_ETPU_TC6F		(33)
+#define INT1_HI_ETPU_TC7F		(34)
+#define INT1_HI_ETPU_TC8F		(35)
+#define INT1_HI_ETPU_TC9F		(36)
+#define INT1_HI_ETPU_TC10F		(37)
+#define INT1_HI_ETPU_TC11F		(38)
+#define INT1_HI_ETPU_TC12F		(39)
+#define INT1_HI_ETPU_TC13F		(40)
+#define INT1_HI_ETPU_TC14F		(41)
+#define INT1_HI_ETPU_TC15F		(42)
+#define INT1_HI_ETPU_TC16F		(43)
+#define INT1_HI_ETPU_TC17F		(44)
+#define INT1_HI_ETPU_TC18F		(45)
+#define INT1_HI_ETPU_TC19F		(46)
+#define INT1_HI_ETPU_TC20F		(47)
+#define INT1_HI_ETPU_TC21F		(48)
+#define INT1_HI_ETPU_TC22F		(49)
+#define INT1_HI_ETPU_TC23F		(50)
+#define INT1_HI_ETPU_TC24F		(51)
+#define INT1_HI_ETPU_TC25F		(52)
+#define INT1_HI_ETPU_TC26F		(53)
+#define INT1_HI_ETPU_TC27F		(54)
+#define INT1_HI_ETPU_TC28F		(55)
+#define INT1_HI_ETPU_TC29F		(56)
+#define INT1_HI_ETPU_TC30F		(57)
+#define INT1_HI_ETPU_TC31F		(58)
+#define INT1_HI_ETPU_TGIF		(59)
+
+/*********************************************************************
+* General Purpose I/O (GPIO)
+*********************************************************************/
+/* Bit definitions and macros for GPIO_PODR */
+#define GPIO_PODR_ADDR(x)		(((x)&0x07)<<5)
+#define GPIO_PODR_ADDR_MASK		(0xE0)
+#define GPIO_PODR_BS(x)			((x)&0x0F)
+#define GPIO_PODR_BS_MASK		(0x0F)
+#define GPIO_PODR_CS(x)			(((x)&0x7F)<<1)
+#define GPIO_PODR_CS_MASK		(0xFE)
+#define GPIO_PODR_SDRAM(X)		((x)&0x3F)
+#define GPIO_PODR_SDRAM_MASK		(0x3F)
+#define GPIO_PODR_FECI2C(x)		GPIO_PODR_BS(x)
+#define GPIO_PODR_FECI2C_MASK		GPIO_PODR_BS_MASK
+#define GPIO_PODR_UARTH(x)		((x)&0x03)
+#define GPIO_PODR_UARTH_MASK		(0x03)
+#define GPIO_PODR_QSPI(x)		((x)&0x1F)
+#define GPIO_PODR_QSPI_MASK		(0x1F)
+#define GPIO_PODR_ETPU(x)		((x)&0x07)
+#define GPIO_PODR_ETPU_MASK		(0x07)
+
+/* Bit definitions and macros for GPIO_PDDR */
+#define GPIO_PDDR_ADDR(x)		GPIO_PODR_ADDR(x)
+#define GPIO_PDDR_ADDR_MASK		GPIO_PODR_ADDR_MASK
+#define GPIO_PDDR_BS(x)			GPIO_PODR_BS(x)
+#define GPIO_PDDR_BS_MASK		GPIO_PODR_BS_MASK
+#define GPIO_PDDR_CS(x)			GPIO_PODR_CS(x)
+#define GPIO_PDDR_CS_MASK		GPIO_PODR_CS_MASK
+#define GPIO_PDDR_SDRAM(X)		GPIO_PODR_SDRAM(X)
+#define GPIO_PDDR_SDRAM_MASK		GPIO_PODR_SDRAM_MASK
+#define GPIO_PDDR_FECI2C(x)		GPIO_PDDR_BS(x)
+#define GPIO_PDDR_FECI2C_MASK		GPIO_PDDR_BS_MASK
+#define GPIO_PDDR_UARTH(x)		GPIO_PODR_UARTH(x)
+#define GPIO_PDDR_UARTH_MASK		GPIO_PODR_UARTH_MASK
+#define GPIO_PDDR_QSPI(x)		GPIO_PODR_QSPI(x)
+#define GPIO_PDDR_QSPI_MASK		GPIO_PODR_QSPI_MASK
+#define GPIO_PDDR_ETPU(x)		GPIO_PODR_ETPU(x)
+#define GPIO_PDDR_ETPU_MASK		GPIO_PODR_ETPU_MASK
+
+/* Bit definitions and macros for GPIO_PPDSDR */
+#define GPIO_PPDSDR_ADDR(x)		GPIO_PODR_ADDR(x)
+#define GPIO_PPDSDR_ADDR_MASK		GPIO_PODR_ADDR_MASK
+#define GPIO_PPDSDR_BS(x)		GPIO_PODR_BS(x)
+#define GPIO_PPDSDR_BS_MASK		GPIO_PODR_BS_MASK
+#define GPIO_PPDSDR_CS(x)		GPIO_PODR_CS(x)
+#define GPIO_PPDSDR_CS_MASK		GPIO_PODR_CS_MASK
+#define GPIO_PPDSDR_SDRAM(X)		GPIO_PODR_SDRAM(X)
+#define GPIO_PPDSDR_SDRAM_MASK		GPIO_PODR_SDRAM_MASK
+#define GPIO_PPDSDR_FECI2C(x)		GPIO_PPDSDR_BS(x)
+#define GPIO_PPDSDR_FECI2C_MASK		GPIO_PPDSDR_BS_MASK
+#define GPIO_PPDSDR_UARTH(x)		GPIO_PODR_UARTH(x)
+#define GPIO_PPDSDR_UARTH_MASK		GPIO_PODR_UARTH_MASK
+#define GPIO_PPDSDR_QSPI(x)		GPIO_PODR_QSPI(x)
+#define GPIO_PPDSDR_QSPI_MASK		GPIO_PODR_QSPI_MASK
+#define GPIO_PPDSDR_ETPU(x)		GPIO_PODR_ETPU(x)
+#define GPIO_PPDSDR_ETPU_MASK		GPIO_PODR_ETPU_MASK
+
+/* Bit definitions and macros for GPIO_PCLRR */
+#define GPIO_PCLRR_ADDR(x)		GPIO_PODR_ADDR(x)
+#define GPIO_PCLRR_ADDR_MASK		GPIO_PODR_ADDR_MASK
+#define GPIO_PCLRR_BS(x)		GPIO_PODR_BS(x)
+#define GPIO_PCLRR_BS_MASK		GPIO_PODR_BS_MASK
+#define GPIO_PCLRR_CS(x)		GPIO_PODR_CS(x)
+#define GPIO_PCLRR_CS_MASK		GPIO_PODR_CS_MASK
+#define GPIO_PCLRR_SDRAM(X)		GPIO_PODR_SDRAM(X)
+#define GPIO_PCLRR_SDRAM_MASK		GPIO_PODR_SDRAM_MASK
+#define GPIO_PCLRR_FECI2C(x)		GPIO_PCLRR_BS(x)
+#define GPIO_PCLRR_FECI2C_MASK		GPIO_PCLRR_BS_MASK
+#define GPIO_PCLRR_UARTH(x)		GPIO_PODR_UARTH(x)
+#define GPIO_PCLRR_UARTH_MASK		GPIO_PODR_UARTH_MASK
+#define GPIO_PCLRR_QSPI(x)		GPIO_PODR_QSPI(x)
+#define GPIO_PCLRR_QSPI_MASK		GPIO_PODR_QSPI_MASK
+#define GPIO_PCLRR_ETPU(x)		GPIO_PODR_ETPU(x)
+#define GPIO_PCLRR_ETPU_MASK		GPIO_PODR_ETPU_MASK
+
+/* Bit definitions and macros for GPIO_PAR */
+#define GPIO_PAR_AD_ADDR23		(0x80)
+#define GPIO_PAR_AD_ADDR22		(0x40)
+#define GPIO_PAR_AD_ADDR21		(0x20)
+#define GPIO_PAR_AD_DATAL		(0x01)
+#define GPIO_PAR_BUSCTL_OE		(0x4000)
+#define GPIO_PAR_BUSCTL_TA		(0x1000)
+#define GPIO_PAR_BUSCTL_TEA(x)		(((x)&0x03)<<10)
+#define GPIO_PAR_BUSCTL_TEA_MASK	(0x0C00)
+#define GPIO_PAR_BUSCTL_TEA_GPIO	(0x0400)
+#define GPIO_PAR_BUSCTL_TEA_DREQ1	(0x0800)
+#define GPIO_PAR_BUSCTL_TEA_EXTBUS	(0x0C00)
+#define GPIO_PAR_BUSCTL_RWB		(0x0100)
+#define GPIO_PAR_BUSCTL_TSIZ1		(0x0040)
+#define GPIO_PAR_BUSCTL_TSIZ0		(0x0010)
+#define GPIO_PAR_BUSCTL_TS(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_BUSCTL_TS_MASK		(0x0C)
+#define GPIO_PAR_BUSCTL_TS_GPIO		(0x04)
+#define GPIO_PAR_BUSCTL_TS_DACK2	(0x08)
+#define GPIO_PAR_BUSCTL_TS_EXTBUS	(0x0C)
+#define GPIO_PAR_BUSCTL_TIP(x)		((x)&0x03)
+#define GPIO_PAR_BUSCTL_TIP_MASK	(0x03)
+#define GPIO_PAR_BUSCTL_TIP_GPIO	(0x01)
+#define GPIO_PAR_BUSCTL_TIP_DREQ0	(0x02)
+#define GPIO_PAR_BUSCTL_TIP_EXTBUS	(0x03)
+#define GPIO_PAR_BS(x)			((x)&0x0F)
+#define GPIO_PAR_BS_MASK		(0x0F)
+#define GPIO_PAR_CS(x)			(((x)&0x7F)<<1)
+#define GPIO_PAR_CS_MASK		(0xFE)
+#define GPIO_PAR_CS_CS7			(0x80)
+#define GPIO_PAR_CS_CS6			(0x40)
+#define GPIO_PAR_CS_CS5			(0x20)
+#define GPIO_PAR_CS_CS4			(0x10)
+#define GPIO_PAR_CS_CS3			(0x08)
+#define GPIO_PAR_CS_CS2			(0x04)
+#define GPIO_PAR_CS_CS1			(0x02)
+#define GPIO_PAR_CS_SD3			GPIO_PAR_CS_CS3
+#define GPIO_PAR_CS_SD2			GPIO_PAR_CS_CS2
+#define GPIO_PAR_SDRAM_CSSDCS(x)	(((x)&0x03)<<6)
+#define GPIO_PAR_SDRAM_CSSDCS_MASK	(0xC0)
+#define GPIO_PAR_SDRAM_SDWE		(0x20)
+#define GPIO_PAR_SDRAM_SCAS		(0x10)
+#define GPIO_PAR_SDRAM_SRAS		(0x08)
+#define GPIO_PAR_SDRAM_SCKE		(0x04)
+#define GPIO_PAR_SDRAM_SDCS(x)		((x)&0x03)
+#define GPIO_PAR_SDRAM_SDCS_MASK	(0x03)
+#define GPIO_PAR_FECI2C_EMDC(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_FECI2C_EMDC_MASK	(0xC0)
+#define GPIO_PAR_FECI2C_EMDC_U2TXD	(0x40)
+#define GPIO_PAR_FECI2C_EMDC_I2CSCL	(0x80)
+#define GPIO_PAR_FECI2C_EMDC_FECEMDC	(0xC0)
+#define GPIO_PAR_FECI2C_EMDIO(x)	(((x)&0x03)<<4)
+#define GPIO_PAR_FECI2C_EMDIO_MASK	(0x30)
+#define GPIO_PAR_FECI2C_EMDIO_U2RXD	(0x10)
+#define GPIO_PAR_FECI2C_EMDIO_I2CSDA	(0x20)
+#define GPIO_PAR_FECI2C_EMDIO_FECEMDIO	(0x30)
+#define GPIO_PAR_FECI2C_SCL(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_FECI2C_SCL_MASK	(0x0C)
+#define GPIO_PAR_FECI2C_SCL_CAN0RX	(0x08)
+#define GPIO_PAR_FECI2C_SCL_I2CSCL	(0x0C)
+#define GPIO_PAR_FECI2C_SDA(x)		((x)&0x03)
+#define GPIO_PAR_FECI2C_SDA_MASK	(0x03)
+#define GPIO_PAR_FECI2C_SDA_CAN0TX	(0x02)
+#define GPIO_PAR_FECI2C_SDA_I2CSDA	(0x03)
+#define GPIO_PAR_UART_DREQ2		(0x8000)
+#define GPIO_PAR_UART_CAN1EN		(0x4000)
+#define GPIO_PAR_UART_U2RXD		(0x2000)
+#define GPIO_PAR_UART_U2TXD		(0x1000)
+#define GPIO_PAR_UART_U1RXD(x)		(((x)&0x03)<<10)
+#define GPIO_PAR_UART_U1RXD_MASK	(0x0C00)
+#define GPIO_PAR_UART_U1RXD_CAN0RX	(0x0800)
+#define GPIO_PAR_UART_U1RXD_U1RXD	(0x0C00)
+#define GPIO_PAR_UART_U1TXD(x)		(((x)&0x03)<<8)
+#define GPIO_PAR_UART_U1TXD_MASK	(0x0300)
+#define GPIO_PAR_UART_U1TXD_CAN0TX	(0x0200)
+#define GPIO_PAR_UART_U1TXD_U1TXD	(0x0300)
+#define GPIO_PAR_UART_U1CTS(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_UART_U1CTS_MASK	(0x00C0)
+#define GPIO_PAR_UART_U1CTS_U2CTS	(0x0080)
+#define GPIO_PAR_UART_U1CTS_U1CTS	(0x00C0)
+#define GPIO_PAR_UART_U1RTS(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_UART_U1RTS_MASK	(0x0030)
+#define GPIO_PAR_UART_U1RTS_U2RTS	(0x0020)
+#define GPIO_PAR_UART_U1RTS_U1RTS	(0x0030)
+#define GPIO_PAR_UART_U0RXD		(0x0008)
+#define GPIO_PAR_UART_U0TXD		(0x0004)
+#define GPIO_PAR_UART_U0CTS		(0x0002)
+#define GPIO_PAR_UART_U0RTS		(0x0001)
+#define GPIO_PAR_QSPI_CS1(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_QSPI_CS1_MASK		(0xC0)
+#define GPIO_PAR_QSPI_CS1_SDRAMSCKE	(0x80)
+#define GPIO_PAR_QSPI_CS1_QSPICS1	(0xC0)
+#define GPIO_PAR_QSPI_CS0		(0x20)
+#define GPIO_PAR_QSPI_DIN(x)		(((x)&0x03)<<3)
+#define GPIO_PAR_QSPI_DIN_MASK		(0x18)
+#define GPIO_PAR_QSPI_DIN_I2CSDA	(0x10)
+#define GPIO_PAR_QSPI_DIN_QSPIDIN	(0x18)
+#define GPIO_PAR_QSPI_DOUT		(0x04)
+#define GPIO_PAR_QSPI_SCK(x)		((x)&0x03)
+#define GPIO_PAR_QSPI_SCK_MASK		(0x03)
+#define GPIO_PAR_QSPI_SCK_I2CSCL	(0x02)
+#define GPIO_PAR_QSPI_SCK_QSPISCK	(0x03)
+#define GPIO_PAR_DT3IN(x)		(((x)&0x03)<<14)
+#define GPIO_PAR_DT3IN_MASK		(0xC000)
+#define GPIO_PAR_DT3IN_QSPICS2		(0x4000)
+#define GPIO_PAR_DT3IN_U2CTS		(0x8000)
+#define GPIO_PAR_DT3IN_DT3IN		(0xC000)
+#define GPIO_PAR_DT2IN(x)		(((x)&0x03)<<12)
+#define GPIO_PAR_DT2IN_MASK		(0x3000)
+#define GPIO_PAR_DT2IN_DT2OUT		(0x1000)
+#define GPIO_PAR_DT2IN_DREQ2		(0x2000)
+#define GPIO_PAR_DT2IN_DT2IN		(0x3000)
+#define GPIO_PAR_DT1IN(x)		(((x)&0x03)<<10)
+#define GPIO_PAR_DT1IN_MASK		(0x0C00)
+#define GPIO_PAR_DT1IN_DT1OUT		(0x0400)
+#define GPIO_PAR_DT1IN_DREQ1		(0x0800)
+#define GPIO_PAR_DT1IN_DT1IN		(0x0C00)
+#define GPIO_PAR_DT0IN(x)		(((x)&0x03)<<8)
+#define GPIO_PAR_DT0IN_MASK		(0x0300)
+#define GPIO_PAR_DT0IN_DREQ0		(0x0200)
+#define GPIO_PAR_DT0IN_DT0IN		(0x0300)
+#define GPIO_PAR_DT3OUT(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_DT3OUT_MASK		(0x00C0)
+#define GPIO_PAR_DT3OUT_QSPICS3		(0x0040)
+#define GPIO_PAR_DT3OUT_U2RTS		(0x0080)
+#define GPIO_PAR_DT3OUT_DT3OUT		(0x00C0)
+#define GPIO_PAR_DT2OUT(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_DT2OUT_MASK		(0x0030)
+#define GPIO_PAR_DT2OUT_DACK2		(0x0020)
+#define GPIO_PAR_DT2OUT_DT2OUT		(0x0030)
+#define GPIO_PAR_DT1OUT(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_DT1OUT_MASK		(0x000C)
+#define GPIO_PAR_DT1OUT_DACK1		(0x0008)
+#define GPIO_PAR_DT1OUT_DT1OUT		(0x000C)
+#define GPIO_PAR_DT0OUT(x)		((x)&0x03)
+#define GPIO_PAR_DT0OUT_MASK		(0x0003)
+#define GPIO_PAR_DT0OUT_DACK0		(0x0002)
+#define GPIO_PAR_DT0OUT_DT0OUT		(0x0003)
+#define GPIO_PAR_ETPU_TCRCLK		(0x04)
+#define GPIO_PAR_ETPU_UTPU_ODIS		(0x02)
+#define GPIO_PAR_ETPU_LTPU_ODIS		(0x01)
+
+/* Bit definitions and macros for GPIO_DSCR */
+#define GPIO_DSCR_EIM_EIM1		(0x10)
+#define GPIO_DSCR_EIM_EIM0		(0x01)
+#define GPIO_DSCR_ETPU_ETPU31_24	(0x40)
+#define GPIO_DSCR_ETPU_ETPU23_16	(0x10)
+#define GPIO_DSCR_ETPU_ETPU15_8		(0x04)
+#define GPIO_DSCR_ETPU_ETPU7_0		(0x01)
+#define GPIO_DSCR_FECI2C_FEC		(0x10)
+#define GPIO_DSCR_FECI2C_I2C		(0x01)
+#define GPIO_DSCR_UART_IRQ		(0x40)
+#define GPIO_DSCR_UART_UART2		(0x10)
+#define GPIO_DSCR_UART_UART1		(0x04)
+#define GPIO_DSCR_UART_UART0		(0x01)
+#define GPIO_DSCR_QSPI_QSPI		(0x01)
+#define GPIO_DSCR_TIMER			(0x01)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+/* Bit definitions and macros for CCM_RCR */
+#define CCM_RCR_SOFTRST			(0x80)
+#define CCM_RCR_FRCRSTOUT		(0x40)
+
+/* Bit definitions and macros for CCM_RSR */
+#define CCM_RSR_SOFT			(0x20)
+#define CCM_RSR_WDR			(0x10)
+#define CCM_RSR_POR			(0x08)
+#define CCM_RSR_EXT			(0x04)
+#define CCM_RSR_LOC			(0x02)
+#define CCM_RSR_LOL			(0x01)
+
+/* Bit definitions and macros for CCM_CCR */
+#define CCM_CCR_LOAD			(0x8000)
+#define CCM_CCR_SZEN			(0x0040)
+#define CCM_CCR_PSTEN			(0x0020)
+#define CCM_CCR_BME			(0x0008)
+#define CCM_CCR_BMT(x)			((x)&0x07)
+#define CCM_CCR_BMT_MASK		(0x0007)
+#define CCM_CCR_BMT_64K			(0x0000)
+#define CCM_CCR_BMT_32K			(0x0001)
+#define CCM_CCR_BMT_16K			(0x0002)
+#define CCM_CCR_BMT_8K			(0x0003)
+#define CCM_CCR_BMT_4K			(0x0004)
+#define CCM_CCR_BMT_2K			(0x0005)
+#define CCM_CCR_BMT_1K			(0x0006)
+#define CCM_CCR_BMT_512			(0x0007)
+
+/* Bit definitions and macros for CCM_RCON */
+#define CCM_RCON_RCSC(x)		(((x)&0x0003)<<8)
+#define CCM_RCON_RLOAD			(0x0020)
+#define CCM_RCON_BOOTPS(x)		(((x)&0x0003)<<3)
+#define CCM_RCON_BOOTPS_MASK		(0x0018)
+#define CCM_RCON_BOOTPS_32		(0x0018)
+#define CCM_RCON_BOOTPS_16		(0x0008)
+#define CCM_RCON_BOOTPS_8		(0x0010)
+#define CCM_RCON_MODE			(0x0001)
+
+/* Bit definitions and macros for CCM_CIR */
+#define CCM_CIR_PIN(x)			(((x) & 0xFFC0) >> 6)
+#define CCM_CIR_PRN(x)			((x) & 0x003F)
+
+/*********************************************************************
+* PLL Clock Module
+*********************************************************************/
+/* Bit definitions and macros for PLL_SYNCR */
+#define PLL_SYNCR_MFD(x)		(((x)&0x07)<<24)
+#define PLL_SYNCR_MFD_MASK		(0x07000000)
+#define PLL_SYNCR_RFC(x)		(((x)&0x07)<<19)
+#define PLL_SYNCR_RFC_MASK		(0x00380000)
+#define PLL_SYNCR_LOCEN			(0x00040000)
+#define PLL_SYNCR_LOLRE			(0x00020000)
+#define PLL_SYNCR_LOCRE			(0x00010000)
+#define PLL_SYNCR_DISCLK		(0x00008000)
+#define PLL_SYNCR_LOLIRQ		(0x00004000)
+#define PLL_SYNCR_LOCIRQ		(0x00002000)
+#define PLL_SYNCR_RATE			(0x00001000)
+#define PLL_SYNCR_DEPTH(x)		(((x)&0x03)<<10)
+#define PLL_SYNCR_EXP(x)		((x)&0x03FF)
+
+/* Bit definitions and macros for PLL_SYNSR */
+#define PLL_SYNSR_LOLF			(0x00000200)
+#define PLL_SYNSR_LOC			(0x00000100)
+#define PLL_SYNSR_MODE			(0x00000080)
+#define PLL_SYNSR_PLLSEL		(0x00000040)
+#define PLL_SYNSR_PLLREF		(0x00000020)
+#define PLL_SYNSR_LOCKS			(0x00000010)
+#define PLL_SYNSR_LOCK			(0x00000008)
+#define PLL_SYNSR_LOCF			(0x00000004)
+#define PLL_SYNSR_CALDONE		(0x00000002)
+#define PLL_SYNSR_CALPASS		(0x00000001)
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+/* Bit definitions and macros for WTM_WCR */
+#define WTM_WCR_WAIT			(0x0008)
+#define WTM_WCR_DOZE			(0x0004)
+#define WTM_WCR_HALTED			(0x0002)
+#define WTM_WCR_EN			(0x0001)
+
+#endif				/* mcf5235_h */
diff --git a/arch/m68k/include/asm/m5249.h b/arch/m68k/include/asm/m5249.h
new file mode 100644
index 0000000..9303629
--- /dev/null
+++ b/arch/m68k/include/asm/m5249.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * mcf5249.h -- Definitions for Motorola Coldfire 5249
+ *
+ * Based on mcf5272sim.h of uCLinux distribution:
+ *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ */
+
+#ifndef	mcf5249_h
+#define	mcf5249_h
+/****************************************************************************/
+
+/*
+ * useful definitions for reading/writing MBAR offset memory
+ */
+#define mbar_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
+#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar2_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x))
+#define mbar2_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y
+#define mbar2_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y
+#define mbar2_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y
+
+/*
+ * Size of internal RAM
+ */
+
+#define INT_RAM_SIZE 32768	/* RAMBAR0 - 32k */
+#define INT_RAM_SIZE2 65536	/* RAMBAR1 - 64k */
+
+/*
+ *	Define the 5249 SIM register set addresses.
+ */
+
+/*****************
+ ***** MBAR1 *****
+ *****************/
+#define	MCFSIM_RSR		0x00	/* Reset Status reg (r/w) */
+#define	MCFSIM_SYPCR		0x01	/* System Protection reg (r/w) */
+#define	MCFSIM_SWIVR		0x02	/* SW Watchdog intr reg (r/w) */
+#define	MCFSIM_SWSR		0x03	/* SW Watchdog service (r/w) */
+#define MCFSIM_MPARK		0x0c	/* Bus master park register (r/w) */
+
+#define	MCFSIM_SIMR		0x00	/* SIM Config reg (r/w) */
+#define	MCFSIM_ICR0		0x4c	/* Intr Ctrl reg 0 (r/w) */
+#define	MCFSIM_ICR1		0x4d	/* Intr Ctrl reg 1 (r/w) */
+#define	MCFSIM_ICR2		0x4e	/* Intr Ctrl reg 2 (r/w) */
+#define	MCFSIM_ICR3		0x4f	/* Intr Ctrl reg 3 (r/w) */
+#define	MCFSIM_ICR4		0x50	/* Intr Ctrl reg 4 (r/w) */
+#define	MCFSIM_ICR5		0x51	/* Intr Ctrl reg 5 (r/w) */
+#define	MCFSIM_ICR6		0x52	/* Intr Ctrl reg 6 (r/w) */
+#define	MCFSIM_ICR7		0x53	/* Intr Ctrl reg 7 (r/w) */
+#define	MCFSIM_ICR8		0x54	/* Intr Ctrl reg 8 (r/w) */
+#define	MCFSIM_ICR9		0x55	/* Intr Ctrl reg 9 (r/w) */
+#define	MCFSIM_ICR10		0x56	/* Intr Ctrl reg 10 (r/w) */
+#define	MCFSIM_ICR11		0x57	/* Intr Ctrl reg 11 (r/w) */
+
+#define MCFSIM_IPR		0x40	/* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR		0x44	/* Interrupt Mask reg (r/w) */
+
+#define MCFSIM_DCR		0x100	/* DRAM Control reg (r/w) */
+#define MCFSIM_DACR0		0x108	/* DRAM 0 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR0		0x10c	/* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DACR1		0x110	/* DRAM 1 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR1		0x114	/* DRAM 1 Mask reg (r/w) */
+
+/*****************
+ ***** MBAR2 *****
+ *****************/
+
+/*  GPIO Addresses
+ *  Note: These are offset from MBAR2!
+ */
+#define MCFSIM_GPIO_READ	0x00	/* Read-Only access to gpio 0-31 (MBAR2) (r) */
+#define MCFSIM_GPIO_OUT		0x04	/* Output register for gpio 0-31 (MBAR2) (r/w) */
+#define MCFSIM_GPIO_EN		0x08	/* gpio 0-31 enable (r/w) */
+#define MCFSIM_GPIO_FUNC	0x0c	/* gpio 0-31 function select (r/w) */
+#define MCFSIM_GPIO1_READ	0xb0	/* Read-Only access to gpio 32-63 (MBAR2) (r) */
+#define MCFSIM_GPIO1_OUT	0xb4	/* Output register for gpio 32-63 (MBAR2) (r/w) */
+#define MCFSIM_GPIO1_EN		0xb8	/* gpio 32-63 enable (r/w) */
+#define MCFSIM_GPIO1_FUNC	0xbc	/* gpio 32-63 function select (r/w) */
+
+#define MCFSIM_GPIO_INT_STAT	0xc0	/* Secondary Interrupt status (r) */
+#define MCFSIM_GPIO_INT_CLEAR	0xc0	/* Secondary Interrupt status (w) */
+#define MCFSIM_GPIO_INT_EN	0xc4	/* Secondary Interrupt status (r/w) */
+
+#define MCFSIM_INT_STAT3	0xe0	/* 3rd Interrupt ctrl status (r) */
+#define MCFSIM_INT_CLEAR3	0xe0	/* 3rd Interrupt ctrl clear (w) */
+#define MCFSIM_INT_EN3		0xe4	/* 3rd Interrupt ctrl enable (r/w) */
+
+#define MCFSIM_INTLEV1		0x140	/* Interrupts 0 - 7 (r/w) */
+#define MCFSIM_INTLEV2		0x144	/* Interrupts 8 -15 (r/w) */
+#define MCFSIM_INTLEV3		0x148	/* Interrupts 16-23 (r/w) */
+#define MCFSIM_INTLEV4		0x14c	/* Interrupts 24-31 (r/w) */
+#define MCFSIM_INTLEV5		0x150	/* Interrupts 32-39 (r/w) */
+#define MCFSIM_INTLEV6		0x154	/* Interrupts 40-47 (r/w) */
+#define MCFSIM_INTLEV7		0x158	/* Interrupts 48-55 (r/w) */
+#define MCFSIM_INTLEV8		0x15c	/* Interrupts 56-63 (r/w) */
+
+#define MCFSIM_SPURVEC		0x167	/* Spurious Vector Register (r/w) */
+#define MCFSIM_INTBASE		0x16b	/* Software interrupt base address (r/w) */
+
+#define MCFSIM_IDECONFIG1	0x18c	/* IDE config register 1 (r/w) */
+#define MCFSIM_IDECONFIG2	0x190	/* IDE config register 1 (r/w) */
+
+#define MCFSIM_PLLCR		0x180	/* PLL Control register */
+
+/*
+ *  Some symbol defines for the above...
+ */
+#define	MCFSIM_SWDICR		MCFSIM_ICR0	/* Watchdog timer ICR */
+#define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
+#define	MCFSIM_TIMER2ICR	MCFSIM_ICR2	/* Timer 2 ICR */
+#define	MCFSIM_I2CICR		MCFSIM_ICR3	/* I2C ICR */
+#define	MCFSIM_UART1ICR		MCFSIM_ICR4	/* UART 1 ICR */
+#define	MCFSIM_UART2ICR		MCFSIM_ICR5	/* UART 2 ICR */
+/* XXX - If needed, DMA ICRs go here */
+#define	MCFSIM_QSPIICR		MCFSIM_ICR10	/* QSPI ICR */
+
+/*
+ *	Bit definitions for the ICR family of registers.
+ */
+#define	MCFSIM_ICR_AUTOVEC	0x80	/* Auto-vectored intr */
+#define	MCFSIM_ICR_LEVEL0	0x00	/* Level 0 intr */
+#define	MCFSIM_ICR_LEVEL1	0x04	/* Level 1 intr */
+#define	MCFSIM_ICR_LEVEL2	0x08	/* Level 2 intr */
+#define	MCFSIM_ICR_LEVEL3	0x0c	/* Level 3 intr */
+#define	MCFSIM_ICR_LEVEL4	0x10	/* Level 4 intr */
+#define	MCFSIM_ICR_LEVEL5	0x14	/* Level 5 intr */
+#define	MCFSIM_ICR_LEVEL6	0x18	/* Level 6 intr */
+#define	MCFSIM_ICR_LEVEL7	0x1c	/* Level 7 intr */
+
+#define	MCFSIM_ICR_PRI0		0x00	/* Priority 0 intr */
+#define	MCFSIM_ICR_PRI1		0x01	/* Priority 1 intr */
+#define	MCFSIM_ICR_PRI2		0x02	/* Priority 2 intr */
+#define	MCFSIM_ICR_PRI3		0x03	/* Priority 3 intr */
+
+/*
+ *  Macros to read/set IMR register. It is 32 bits on the 5249.
+ */
+
+#define	mcf_getimr()		\
+	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
+
+#define	mcf_setimr(imr)		\
+	*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
+
+#endif				/* mcf5249_h */
diff --git a/arch/m68k/include/asm/m5253.h b/arch/m68k/include/asm/m5253.h
new file mode 100644
index 0000000..a2fdad7
--- /dev/null
+++ b/arch/m68k/include/asm/m5253.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef m5253_h
+#define m5253_h
+/****************************************************************************/
+
+/*
+* PLL Module (PLL)
+*/
+
+/* Register read/write macros */
+#define PLL_PLLCR		(0x000180)
+
+#define SIM_RSR			(0x000000)
+#define SIM_SYPCR		(0x000001)
+#define SIM_SWIVR		(0x000002)
+#define SIM_SWSR		(0x000003)
+#define SIM_MPARK		(0x00000C)
+
+/* Bit definitions and macros for RSR */
+#define SIM_RSR_SWTR		(0x20)
+#define SIM_RSR_HRST		(0x80)
+
+/* Register read/write macros */
+#define CIM_MISCCR		(0x000500)
+#define CIM_ATA_DADDR		(0x000504)
+#define CIM_ATA_DCOUNT		(0x000508)
+#define CIM_RTC_TIME		(0x00050C)
+#define CIM_USB_CANCLK		(0x000510)
+
+/* Bit definitions and macros for MISCCR */
+#define CIM_MISCCR_ADTA		(0x00000001)
+#define CIM_MISCCR_ADTD		(0x00000002)
+#define CIM_MISCCR_ADIE		(0x00000004)
+#define CIM_MISCCR_ADIC		(0x00000008)
+#define CIM_MISCCR_ADIP		(0x00000010)
+#define CIM_MISCCR_CPUEND	(0x00000020)
+#define CIM_MISCCR_DMAEND	(0x00000040)
+#define CIM_MISCCR_RTCCLR	(0x00000080)
+#define CIM_MISCCR_RTCPL	(0x00000100)
+#define CIM_MISCCR_URIE		(0x00000800)
+#define CIM_MISCCR_URIC		(0x00001000)
+#define CIM_MISCCR_URIP		(0x00002000)
+
+/* Bit definitions and macros for ATA_DADDR */
+#define CIM_ATA_DADDR_ATAADDR(x)	(((x)&0x00003FFF)<<2)
+#define CIM_ATA_DADDR_RAMADDR(x)	(((x)&0x00003FFF)<<18)
+
+/* Bit definitions and macros for ATA_DCOUNT */
+#define CIM_ATA_DCOUNT_COUNT(x)		(((x)&0x0000FFFF))
+
+#endif				/* m5253_h */
diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h
new file mode 100644
index 0000000..dce0d26
--- /dev/null
+++ b/arch/m68k/include/asm/m5271.h
@@ -0,0 +1,273 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * mcf5271.h -- Definitions for Motorola Coldfire 5271
+ *
+ * (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com>
+ * Based on mcf5272sim.h of uCLinux distribution:
+ *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ */
+
+#ifndef	_MCF5271_H_
+#define	_MCF5271_H_
+
+#define mbar_readLong(x)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
+#define mbar_readShort(x)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x))
+#define mbar_readByte(x)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x))
+#define mbar_writeLong(x,y)	*((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_writeShort(x,y)	*((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
+#define mbar_writeByte(x,y)	*((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
+
+#define MCF_FMPLL_SYNCR				0x120000
+#define MCF_FMPLL_SYNSR				0x120004
+
+#define MCF_FMPLL_SYNCR_MFD(x)			((x&0x7)<<24)
+#define MCF_SYNCR_MFD_4X		0x00000000
+#define MCF_SYNCR_MFD_6X		0x01000000
+#define MCF_SYNCR_MFD_8X		0x02000000
+#define MCF_SYNCR_MFD_10X		0x03000000
+#define MCF_SYNCR_MFD_12X		0x04000000
+#define MCF_SYNCR_MFD_14X		0x05000000
+#define MCF_SYNCR_MFD_16X		0x06000000
+#define MCF_SYNCR_MFD_18X		0x07000000
+
+#define MCF_FMPLL_SYNCR_RFD(x)			((x&0x7)<<19)
+#define MCF_SYNCR_RFD_DIV1		0x00000000
+#define MCF_SYNCR_RFD_DIV2		0x00080000
+#define MCF_SYNCR_RFD_DIV4		0x00100000
+#define MCF_SYNCR_RFD_DIV8		0x00180000
+#define MCF_SYNCR_RFD_DIV16		0x00200000
+#define MCF_SYNCR_RFD_DIV32		0x00280000
+#define MCF_SYNCR_RFD_DIV64		0x00300000
+#define MCF_SYNCR_RFD_DIV128		0x00380000
+
+#define MCF_FMPLL_SYNSR_LOCK			0x8
+
+#define MCF_WTM_WCR				0x140000
+#define MCF_WTM_WCNTR				0x140004
+#define MCF_WTM_WSR				0x140006
+#define MCF_WTM_WCR_EN				0x0001
+
+#define MCF_RCM_RCR				0x110000
+#define MCF_RCM_RCR_FRCRSTOUT			0x40
+#define MCF_RCM_RCR_SOFTRST			0x80
+
+#define MCF_GPIO_PODR_ADDR			0x100000
+#define MCF_GPIO_PODR_DATAH			0x100001
+#define MCF_GPIO_PODR_DATAL			0x100002
+#define MCF_GPIO_PODR_BUSCTL			0x100003
+#define MCF_GPIO_PODR_BS			0x100004
+#define MCF_GPIO_PODR_CS			0x100005
+#define MCF_GPIO_PODR_SDRAM			0x100006
+#define MCF_GPIO_PODR_FECI2C			0x100007
+#define MCF_GPIO_PODR_UARTH			0x100008
+#define MCF_GPIO_PODR_UARTL			0x100009
+#define MCF_GPIO_PODR_QSPI			0x10000A
+#define MCF_GPIO_PODR_TIMER			0x10000B
+
+#define MCF_GPIO_PDDR_ADDR			0x100010
+#define MCF_GPIO_PDDR_DATAH			0x100011
+#define MCF_GPIO_PDDR_DATAL			0x100012
+#define MCF_GPIO_PDDR_BUSCTL			0x100013
+#define MCF_GPIO_PDDR_BS			0x100014
+#define MCF_GPIO_PDDR_CS			0x100015
+#define MCF_GPIO_PDDR_SDRAM			0x100016
+#define MCF_GPIO_PDDR_FECI2C			0x100017
+#define MCF_GPIO_PDDR_UARTH			0x100018
+#define MCF_GPIO_PDDR_UARTL			0x100019
+#define MCF_GPIO_PDDR_QSPI			0x10001A
+#define MCF_GPIO_PDDR_TIMER			0x10001B
+
+#define MCF_GPIO_PPDSDR_ADDR			0x100020
+#define MCF_GPIO_PPDSDR_DATAH			0x100021
+#define MCF_GPIO_PPDSDR_DATAL			0x100022
+#define MCF_GPIO_PPDSDR_BUSCTL			0x100023
+#define MCF_GPIO_PPDSDR_BS			0x100024
+#define MCF_GPIO_PPDSDR_CS			0x100025
+#define MCF_GPIO_PPDSDR_SDRAM			0x100026
+#define MCF_GPIO_PPDSDR_FECI2C			0x100027
+#define MCF_GPIO_PPDSDR_UARTH			0x100028
+#define MCF_GPIO_PPDSDR_UARTL			0x100029
+#define MCF_GPIO_PPDSDR_QSPI			0x10002A
+#define MCF_GPIO_PPDSDR_TIMER			0x10002B
+
+#define MCF_GPIO_PCLRR_ADDR			0x100030
+#define MCF_GPIO_PCLRR_DATAH			0x100031
+#define MCF_GPIO_PCLRR_DATAL			0x100032
+#define MCF_GPIO_PCLRR_BUSCTL			0x100033
+#define MCF_GPIO_PCLRR_BS			0x100034
+#define MCF_GPIO_PCLRR_CS			0x100035
+#define MCF_GPIO_PCLRR_SDRAM			0x100036
+#define MCF_GPIO_PCLRR_FECI2C			0x100037
+#define MCF_GPIO_PCLRR_UARTH			0x100038
+#define MCF_GPIO_PCLRR_UARTL			0x100039
+#define MCF_GPIO_PCLRR_QSPI			0x10003A
+#define MCF_GPIO_PCLRR_TIMER			0x10003B
+
+#define MCF_GPIO_PAR_AD				0x100040
+#define MCF_GPIO_PAR_BUSCTL			0x100042
+#define MCF_GPIO_PAR_BS				0x100044
+#define MCF_GPIO_PAR_CS				0x100045
+#define MCF_GPIO_PAR_SDRAM			0x100046
+#define MCF_GPIO_PAR_FECI2C			0x100047
+#define MCF_GPIO_PAR_UART			0x100048
+#define MCF_GPIO_PAR_QSPI			0x10004A
+#define MCF_GPIO_PAR_TIMER			0x10004C
+
+#define MCF_DSCR_EIM				0x100050
+#define MCF_DCSR_FEC12C 			0x100052
+#define MCF_DCSR_UART				0x100053
+#define MCF_DCSR_QSPI				0x100054
+#define MCF_DCSR_TIMER				0x100055
+
+#define MCF_CCM_CIR				0x11000A
+#define MCF_CCM_CIR_PRN_MASK			0x3F
+#define MCF_CCM_CIR_PIN_LEN			6
+#define MCF_CCM_CIR_PIN_MCF5270			0x002e
+#define MCF_CCM_CIR_PIN_MCF5271			0x0032
+
+#define MCF_GPIO_AD_ADDR23			0x80
+#define MCF_GPIO_AD_ADDR22			0x40
+#define MCF_GPIO_AD_ADDR21			0x20
+#define MCF_GPIO_AD_DATAL			0x01
+#define MCF_GPIO_AD_MASK			0xe1
+
+#define MCF_GPIO_PAR_CS_PAR_CS2			0x04
+
+#define MCF_GPIO_SDRAM_CSSDCS_00		0x00	/* CS[3:2] pins: CS3, CS2 */
+#define MCF_GPIO_SDRAM_CSSDCS_01		0x40	/* CS[3:2] pins: CS3, SD_CS0 */
+#define MCF_GPIO_SDRAM_CSSDCS_10		0x80	/* CS[3:2] pins: SD_CS1, SC2 */
+#define MCF_GPIO_SDRAM_CSSDCS_11		0xc0	/* CS[3:2] pins: SD_CS1, SD_CS0 */
+#define MCF_GPIO_SDRAM_SDWE			0x20	/* WE pin */
+#define MCF_GPIO_SDRAM_SCAS			0x10	/* CAS pin */
+#define MCF_GPIO_SDRAM_SRAS			0x08	/* RAS pin */
+#define MCF_GPIO_SDRAM_SCKE			0x04	/* CKE pin */
+#define MCF_GPIO_SDRAM_SDCS_00			0x00	/* SD_CS[0:1] pins: GPIO, GPIO */
+#define MCF_GPIO_SDRAM_SDCS_01			0x01	/* SD_CS[0:1] pins: GPIO, SD_CS0 */
+#define MCF_GPIO_SDRAM_SDCS_10			0x02	/* SD_CS[0:1] pins: SD_CS1, GPIO */
+#define MCF_GPIO_SDRAM_SDCS_11			0x03	/* SD_CS[0:1] pins: SD_CS1, SD_CS0 */
+
+#define MCF_GPIO_PAR_UART_U0RTS			0x0001
+#define MCF_GPIO_PAR_UART_U0CTS			0x0002
+#define MCF_GPIO_PAR_UART_U0TXD			0x0004
+#define MCF_GPIO_PAR_UART_U0RXD			0x0008
+#define MCF_GPIO_PAR_UART_U1RXD_UART1		0x0C00
+#define MCF_GPIO_PAR_UART_U1TXD_UART1		0x0300
+
+/* Bit definitions and macros for PAR_QSPI */
+#define MCF_GPIO_PAR_QSPI_PCS1_UNMASK		0x3F
+#define MCF_GPIO_PAR_QSPI_PCS1_PCS1		0xC0
+#define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE	0x80
+#define MCF_GPIO_PAR_QSPI_PCS1_GPIO		0x00
+#define MCF_GPIO_PAR_QSPI_PCS0_UNMASK		0xDF
+#define MCF_GPIO_PAR_QSPI_PCS0_PCS0		0x20
+#define MCF_GPIO_PAR_QSPI_PCS0_GPIO		0x00
+#define MCF_GPIO_PAR_QSPI_SIN_UNMASK		0xE7
+#define MCF_GPIO_PAR_QSPI_SIN_SIN		0x18
+#define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA		0x10
+#define MCF_GPIO_PAR_QSPI_SIN_GPIO		0x00
+#define MCF_GPIO_PAR_QSPI_SOUT_UNMASK		0xFB
+#define MCF_GPIO_PAR_QSPI_SOUT_SOUT		0x04
+#define MCF_GPIO_PAR_QSPI_SOUT_GPIO		0x00
+#define MCF_GPIO_PAR_QSPI_SCK_UNMASK		0xFC
+#define MCF_GPIO_PAR_QSPI_SCK_SCK		0x03
+#define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL		0x02
+#define MCF_GPIO_PAR_QSPI_SCK_GPIO		0x00
+
+/* Bit definitions and macros for PAR_TIMER for QSPI */
+#define MCF_GPIO_PAR_TIMER_T3IN_UNMASK		0x3FFF
+#define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2	0x4000
+#define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK		0xFF3F
+#define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3	0x0040
+
+#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x)	(((x)&0x03)<<6)
+
+#define MCF_SDRAMC_DCR				0x000040
+#define MCF_SDRAMC_DACR0			0x000048
+#define MCF_SDRAMC_DMR0				0x00004C
+
+#define MCF_SDRAMC_DCR_RC(x)			(((x)&0x01FF)<<0)
+#define MCF_SDRAMC_DCR_RTIM(x)			(((x)&0x0003)<<9)
+#define MCF_SDRAMC_DCR_IS			0x0800
+#define MCF_SDRAMC_DCR_COC			0x1000
+#define MCF_SDRAMC_DCR_NAM			0x2000
+
+#define MCF_SDRAMC_DACRn_IP			0x00000008
+#define MCF_SDRAMC_DACRn_PS(x)			(((x)&0x00000003)<<4)
+#define MCF_SDRAMC_DACRn_MRS			0x00000040
+#define MCF_SDRAMC_DACRn_CBM(x)			(((x)&0x00000007)<<8)
+#define MCF_SDRAMC_DACRn_CASL(x)		(((x)&0x00000003)<<12)
+#define MCF_SDRAMC_DACRn_RE			0x00008000
+#define MCF_SDRAMC_DACRn_BA(x)			(((x)&0x00003FFF)<<18)
+
+#define MCF_SDRAMC_DMRn_BAM_8M			0x007C0000
+#define MCF_SDRAMC_DMRn_BAM_16M			0x00FC0000
+#define MCF_SDRAMC_DMRn_V			0x00000001
+
+#define MCFSIM_ICR1				0x000C41
+
+/* Interrupt Controller (INTC) */
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_SCM			(8)
+#define INT0_LO_DMA0			(9)
+#define INT0_LO_DMA1			(10)
+#define INT0_LO_DMA2			(11)
+#define INT0_LO_DMA3			(12)
+#define INT0_LO_UART0			(13)
+#define INT0_LO_UART1			(14)
+#define INT0_LO_UART2			(15)
+#define INT0_LO_RSVD1			(16)
+#define INT0_LO_I2C			(17)
+#define INT0_LO_QSPI			(18)
+#define INT0_LO_DTMR0			(19)
+#define INT0_LO_DTMR1			(20)
+#define INT0_LO_DTMR2			(21)
+#define INT0_LO_DTMR3			(22)
+#define INT0_LO_FEC_TXF			(23)
+#define INT0_LO_FEC_TXB			(24)
+#define INT0_LO_FEC_UN			(25)
+#define INT0_LO_FEC_RL			(26)
+#define INT0_LO_FEC_RXF			(27)
+#define INT0_LO_FEC_RXB			(28)
+#define INT0_LO_FEC_MII			(29)
+#define INT0_LO_FEC_LC			(30)
+#define INT0_LO_FEC_HBERR		(31)
+#define INT0_HI_FEC_GRA			(32)
+#define INT0_HI_FEC_EBERR		(33)
+#define INT0_HI_FEC_BABT		(34)
+#define INT0_HI_FEC_BABR		(35)
+#define INT0_HI_PIT0			(36)
+#define INT0_HI_PIT1			(37)
+#define INT0_HI_PIT2			(38)
+#define INT0_HI_PIT3			(39)
+#define INT0_HI_RNG			(40)
+#define INT0_HI_SKHA			(41)
+#define INT0_HI_MDHA			(42)
+#define INT0_HI_CAN1_BUF0I		(43)
+#define INT0_HI_CAN1_BUF1I		(44)
+#define INT0_HI_CAN1_BUF2I		(45)
+#define INT0_HI_CAN1_BUF3I		(46)
+#define INT0_HI_CAN1_BUF4I		(47)
+#define INT0_HI_CAN1_BUF5I		(48)
+#define INT0_HI_CAN1_BUF6I		(49)
+#define INT0_HI_CAN1_BUF7I		(50)
+#define INT0_HI_CAN1_BUF8I		(51)
+#define INT0_HI_CAN1_BUF9I		(52)
+#define INT0_HI_CAN1_BUF10I		(53)
+#define INT0_HI_CAN1_BUF11I		(54)
+#define INT0_HI_CAN1_BUF12I		(55)
+#define INT0_HI_CAN1_BUF13I		(56)
+#define INT0_HI_CAN1_BUF14I		(57)
+#define INT0_HI_CAN1_BUF15I		(58)
+#define INT0_HI_CAN1_ERRINT		(59)
+#define INT0_HI_CAN1_BOFFINT		(60)
+/* 60-63 Reserved */
+
+#endif				/* _MCF5271_H_ */
diff --git a/arch/m68k/include/asm/m5272.h b/arch/m68k/include/asm/m5272.h
new file mode 100644
index 0000000..1315845
--- /dev/null
+++ b/arch/m68k/include/asm/m5272.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * mcf5272.h -- Definitions for Motorola Coldfire 5272
+ *
+ * Based on mcf5272sim.h of uCLinux distribution:
+ *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
+ *      (C) Copyright 2000, Lineo Inc. (www.lineo.com)
+ */
+
+#ifndef	mcf5272_h
+#define	mcf5272_h
+/****************************************************************************/
+
+/*
+ * Size of internal RAM
+ */
+
+#define INT_RAM_SIZE 4096
+
+#define GPIO_PACNT_PA15MSK		(0xC0000000)
+#define GPIO_PACNT_DGNT1		(0x40000000)
+#define GPIO_PACNT_PA14MSK		(0x30000000)
+#define GPIO_PACNT_DREQ1		(0x10000000)
+#define GPIO_PACNT_PA13MSK		(0x0C000000)
+#define GPIO_PACNT_DFSC3		(0x04000000)
+#define GPIO_PACNT_PA12MSK		(0x03000000)
+#define GPIO_PACNT_DFSC2		(0x01000000)
+#define GPIO_PACNT_PA11MSK		(0x00C00000)
+#define GPIO_PACNT_QSPI_CS1		(0x00800000)
+#define GPIO_PACNT_PA10MSK		(0x00300000)
+#define GPIO_PACNT_DREQ0		(0x00100000)
+#define GPIO_PACNT_PA9MSK		(0x000C0000)
+#define GPIO_PACNT_DGNT0		(0x00040000)
+#define GPIO_PACNT_PA8MSK		(0x00030000)
+#define GPIO_PACNT_FSC0			(0x00010000)
+#define GPIO_PACNT_FSR0			(0x00010000)
+#define GPIO_PACNT_PA7MSK		(0x0000C000)
+#define GPIO_PACNT_DOUT3		(0x00008000)
+#define GPIO_PACNT_QSPI_CS3		(0x00004000)
+#define GPIO_PACNT_PA6MSK		(0x00003000)
+#define GPIO_PACNT_USB_RXD		(0x00001000)
+#define GPIO_PACNT_PA5MSK		(0x00000C00)
+#define GPIO_PACNT_USB_TXEN		(0x00000400)
+#define GPIO_PACNT_PA4MSK		(0x00000300)
+#define GPIO_PACNT_USB_SUSP		(0x00000100)
+#define GPIO_PACNT_PA3MSK		(0x000000C0)
+#define GPIO_PACNT_USB_TN		(0x00000040)
+#define GPIO_PACNT_PA2MSK		(0x00000030)
+#define GPIO_PACNT_USB_RN		(0x00000010)
+#define GPIO_PACNT_PA1MSK		(0x0000000C)
+#define GPIO_PACNT_USB_RP		(0x00000004)
+#define GPIO_PACNT_PA0MSK		(0x00000003)
+#define GPIO_PACNT_USB_TP		(0x00000001)
+
+#define GPIO_PBCNT_PB15MSK		(0xC0000000)
+#define GPIO_PBCNT_E_MDC		(0x40000000)
+#define GPIO_PBCNT_PB14MSK		(0x30000000)
+#define GPIO_PBCNT_E_RXER		(0x10000000)
+#define GPIO_PBCNT_PB13MSK		(0x0C000000)
+#define GPIO_PBCNT_E_RXD1		(0x04000000)
+#define GPIO_PBCNT_PB12MSK		(0x03000000)
+#define GPIO_PBCNT_E_RXD2		(0x01000000)
+#define GPIO_PBCNT_PB11MSK		(0x00C00000)
+#define GPIO_PBCNT_E_RXD3		(0x00400000)
+#define GPIO_PBCNT_PB10MSK		(0x00300000)
+#define GPIO_PBCNT_E_TXD1		(0x00100000)
+#define GPIO_PBCNT_PB9MSK		(0x000C0000)
+#define GPIO_PBCNT_E_TXD2		(0x00040000)
+#define GPIO_PBCNT_PB8MSK		(0x00030000)
+#define GPIO_PBCNT_E_TXD3		(0x00010000)
+#define GPIO_PBCNT_PB7MSK		(0x0000C000)
+#define GPIO_PBCNT_TOUT0		(0x00004000)
+#define GPIO_PBCNT_PB6MSK		(0x00003000)
+#define GPIO_PBCNT_TA			(0x00001000)
+#define GPIO_PBCNT_PB4MSK		(0x00000300)
+#define GPIO_PBCNT_URT0_CLK		(0x00000100)
+#define GPIO_PBCNT_PB3MSK		(0x000000C0)
+#define GPIO_PBCNT_URT0_RTS		(0x00000040)
+#define GPIO_PBCNT_PB2MSK		(0x00000030)
+#define GPIO_PBCNT_URT0_CTS		(0x00000010)
+#define GPIO_PBCNT_PB1MSK		(0x0000000C)
+#define GPIO_PBCNT_URT0_RXD		(0x00000004)
+#define GPIO_PBCNT_URT0_TIN2		(0x00000004)
+#define GPIO_PBCNT_PB0MSK		(0x00000003)
+#define GPIO_PBCNT_URT0_TXD		(0x00000001)
+
+#define GPIO_PDCNT_PD7MSK		(0x0000C000)
+#define GPIO_PDCNT_TIN1			(0x00008000)
+#define GPIO_PDCNT_PWM_OUT2		(0x00004000)
+#define GPIO_PDCNT_PD6MSK		(0x00003000)
+#define GPIO_PDCNT_TOUT1		(0x00002000)
+#define GPIO_PDCNT_PWM_OUT1		(0x00001000)
+#define GPIO_PDCNT_PD5MSK		(0x00000C00)
+#define GPIO_PDCNT_INT4			(0x00000C00)
+#define GPIO_PDCNT_DIN3			(0x00000800)
+#define GPIO_PDCNT_PD4MSK		(0x00000300)
+#define GPIO_PDCNT_URT1_TXD		(0x00000200)
+#define GPIO_PDCNT_DOUT0		(0x00000100)
+#define GPIO_PDCNT_PD3MSK		(0x000000C0)
+#define GPIO_PDCNT_INT5			(0x000000C0)
+#define GPIO_PDCNT_URT1_RTS		(0x00000080)
+#define GPIO_PDCNT_PD2MSK		(0x00000030)
+#define GPIO_PDCNT_QSPI_CS2		(0x00000030)
+#define GPIO_PDCNT_URT1_CTS		(0x00000020)
+#define GPIO_PDCNT_PD1MSK		(0x0000000C)
+#define GPIO_PDCNT_URT1_RXD		(0x00000008)
+#define GPIO_PDCNT_URT1_TIN3		(0x00000008)
+#define GPIO_PDCNT_DIN0			(0x00000004)
+#define GPIO_PDCNT_PD0MSK		(0x00000003)
+#define GPIO_PDCNT_URT1_CLK		(0x00000002)
+#define GPIO_PDCNT_DCL0			(0x00000001)
+
+#define INT_RSVD0			(0)
+#define INT_INT1			(1)
+#define INT_INT2			(2)
+#define INT_INT3			(3)
+#define INT_INT4			(4)
+#define INT_TMR0			(5)
+#define INT_TMR1			(6)
+#define INT_TMR2			(7)
+#define INT_TMR3			(8)
+#define INT_UART1			(9)
+#define INT_UART2			(10)
+#define INT_PLIP			(11)
+#define INT_PLIA			(12)
+#define INT_USB0			(13)
+#define INT_USB1			(14)
+#define INT_USB2			(15)
+#define INT_USB3			(16)
+#define INT_USB4			(17)
+#define INT_USB5			(18)
+#define INT_USB6			(19)
+#define INT_USB7			(20)
+#define INT_DMA				(21)
+#define INT_ERX				(22)
+#define INT_ETX				(23)
+#define INT_ENTC			(24)
+#define INT_QSPI			(25)
+#define INT_INT5			(26)
+#define INT_INT6			(27)
+#define INT_SWTO			(28)
+
+#define INT_ICR1_TMR0MASK		(0x000F000)
+#define INT_ICR1_TMR0PI			(0x0008000)
+#define INT_ICR1_TMR0IPL(x)		(((x)&0x7)<<12)
+#define INT_ICR1_TMR1MASK		(0x0000F00)
+#define INT_ICR1_TMR1PI			(0x0000800)
+#define INT_ICR1_TMR1IPL(x)		(((x)&0x7)<<8)
+#define INT_ICR1_TMR2MASK		(0x00000F0)
+#define INT_ICR1_TMR2PI			(0x0000080)
+#define INT_ICR1_TMR2IPL(x)		(((x)&0x7)<<4)
+#define INT_ICR1_TMR3MASK		(0x000000F)
+#define INT_ICR1_TMR3PI			(0x0000008)
+#define INT_ICR1_TMR3IPL(x)		(((x)&0x7))
+
+#define INT_ISR_INT31			(0x80000000)
+#define INT_ISR_INT30			(0x40000000)
+#define INT_ISR_INT29			(0x20000000)
+#define INT_ISR_INT28			(0x10000000)
+#define INT_ISR_INT27			(0x08000000)
+#define INT_ISR_INT26			(0x04000000)
+#define INT_ISR_INT25			(0x02000000)
+#define INT_ISR_INT24			(0x01000000)
+#define INT_ISR_INT23			(0x00800000)
+#define INT_ISR_INT22			(0x00400000)
+#define INT_ISR_INT21			(0x00200000)
+#define INT_ISR_INT20			(0x00100000)
+#define INT_ISR_INT19			(0x00080000)
+#define INT_ISR_INT18			(0x00040000)
+#define INT_ISR_INT17			(0x00020000)
+#define INT_ISR_INT16			(0x00010000)
+#define INT_ISR_INT15			(0x00008000)
+#define INT_ISR_INT14			(0x00004000)
+#define INT_ISR_INT13			(0x00002000)
+#define INT_ISR_INT12			(0x00001000)
+#define INT_ISR_INT11			(0x00000800)
+#define INT_ISR_INT10			(0x00000400)
+#define INT_ISR_INT9			(0x00000200)
+#define INT_ISR_INT8			(0x00000100)
+#define INT_ISR_INT7			(0x00000080)
+#define INT_ISR_INT6			(0x00000040)
+#define INT_ISR_INT5			(0x00000020)
+#define INT_ISR_INT4			(0x00000010)
+#define INT_ISR_INT3			(0x00000008)
+#define INT_ISR_INT2			(0x00000004)
+#define INT_ISR_INT1			(0x00000002)
+#define INT_ISR_INT0			(0x00000001)
+
+#endif				/* mcf5272_h */
diff --git a/arch/m68k/include/asm/m5275.h b/arch/m68k/include/asm/m5275.h
new file mode 100644
index 0000000..86790c5
--- /dev/null
+++ b/arch/m68k/include/asm/m5275.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5275 Internal Memory Map
+ *
+ * Copyright (C) 2003-2004, Greg Ungerer (gerg@snapgear.com)
+ * Copyright (C) 2004-2008 Arthur Shipkowski (art@videon-central.com)
+ */
+
+#ifndef	__M5275_H__
+#define	__M5275_H__
+
+/*
+ * Define the 5275 SIM register set addresses. These are similar,
+ * but not quite identical to the 5282 registers and offsets.
+ */
+#define MCF_GPIO_PAR_UART	0x10007c
+#define UART0_ENABLE_MASK	0x000f
+#define UART1_ENABLE_MASK	0x00f0
+#define UART2_ENABLE_MASK	0x3f00
+
+#define MCF_GPIO_PAR_FECI2C	0x100082
+#define PAR_SDA_ENABLE_MASK	0x0003
+#define PAR_SCL_ENABLE_MASK	0x000c
+
+#define MCFSIM_WRRR		0x140000
+#define MCFSIM_SDCR		0x40
+
+/*********************************************************************
+ * SDRAM Controller (SDRAMC)
+ *********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDMR		(*(vuint32*)(void*)(&__IPSBAR[0x000040]))
+#define MCF_SDRAMC_SDCR		(*(vuint32*)(void*)(&__IPSBAR[0x000044]))
+#define MCF_SDRAMC_SDCFG1	(*(vuint32*)(void*)(&__IPSBAR[0x000048]))
+#define MCF_SDRAMC_SDCFG2	(*(vuint32*)(void*)(&__IPSBAR[0x00004C]))
+#define MCF_SDRAMC_SDBAR0	(*(vuint32*)(void*)(&__IPSBAR[0x000050]))
+#define MCF_SDRAMC_SDBAR1	(*(vuint32*)(void*)(&__IPSBAR[0x000058]))
+#define MCF_SDRAMC_SDMR0	(*(vuint32*)(void*)(&__IPSBAR[0x000054]))
+#define MCF_SDRAMC_SDMR1	(*(vuint32*)(void*)(&__IPSBAR[0x00005C]))
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD		(0x00010000)
+#define MCF_SDRAMC_SDMR_AD(x)		(((x)&0x00000FFF)<<18)
+#define MCF_SDRAMC_SDMR_BNKAD(x)	(((x)&0x00000003)<<30)
+#define MCF_SDRAMC_SDMR_BNKAD_LMR	(0x00000000)
+#define MCF_SDRAMC_SDMR_BNKAD_LEMR	(0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL		(0x00000002)
+#define MCF_SDRAMC_SDCR_IREF		(0x00000004)
+#define MCF_SDRAMC_SDCR_DQS_OE(x)	(((x)&0x00000003)<<10)
+#define MCF_SDRAMC_SDCR_DQP_BP		(0x00008000)
+#define MCF_SDRAMC_SDCR_RCNT(x)		(((x)&0x0000003F)<<16)
+#define MCF_SDRAMC_SDCR_MUX(x)		(((x)&0x00000003)<<24)
+#define MCF_SDRAMC_SDCR_REF		(0x10000000)
+#define MCF_SDRAMC_SDCR_CKE		(0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN		(0x80000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x)	(((x)&0x00000007)<<4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)	(((x)&0x00000007)<<12)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x)	(((x)&0x00000007)<<16)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x)	(((x)&0x0000000F)<<20)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x)	(((x)&0x00000007)<<24)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x)	(((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x)		(((x)&0x0000000F)<<16)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x)	(((x)&0x0000000F)<<20)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x)	(((x)&0x0000000F)<<24)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x)	(((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDBARn */
+#define MCF_SDRAMC_SDBARn_BASE(x)	(((x)&0x00003FFF)<<18)
+#define MCF_SDRAMC_SDBARn_BA(x)		((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMRn */
+#define MCF_SDRAMC_SDMRn_V		(0x00000001)
+#define MCF_SDRAMC_SDMRn_WP		(0x00000080)
+#define MCF_SDRAMC_SDMRn_MASK(x)	(((x)&0x00003FFF)<<18)
+#define MCF_SDRAMC_SDMRn_BAM_4G		(0xFFFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_2G		(0x7FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_1G		(0x3FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_1024M	(0x3FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_512M	(0x1FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_256M	(0x0FFF0000)
+#define MCF_SDRAMC_SDMRn_BAM_128M	(0x07FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_64M	(0x03FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_32M	(0x01FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_16M	(0x00FF0000)
+#define MCF_SDRAMC_SDMRn_BAM_8M		(0x007F0000)
+#define MCF_SDRAMC_SDMRn_BAM_4M		(0x003F0000)
+#define MCF_SDRAMC_SDMRn_BAM_2M		(0x001F0000)
+#define MCF_SDRAMC_SDMRn_BAM_1M		(0x000F0000)
+#define MCF_SDRAMC_SDMRn_BAM_1024K	(0x000F0000)
+#define MCF_SDRAMC_SDMRn_BAM_512K	(0x00070000)
+#define MCF_SDRAMC_SDMRn_BAM_256K	(0x00030000)
+#define MCF_SDRAMC_SDMRn_BAM_128K	(0x00010000)
+#define MCF_SDRAMC_SDMRn_BAM_64K	(0x00000000)
+
+/*********************************************************************
+ * Interrupt Controller (INTC)
+ ********************************************************************/
+#define INT0_LO_RSVD0		(0)
+#define INT0_LO_EPORT1		(1)
+#define INT0_LO_EPORT2		(2)
+#define INT0_LO_EPORT3		(3)
+#define INT0_LO_EPORT4		(4)
+#define INT0_LO_EPORT5		(5)
+#define INT0_LO_EPORT6		(6)
+#define INT0_LO_EPORT7		(7)
+#define INT0_LO_SCM		(8)
+#define INT0_LO_DMA0		(9)
+#define INT0_LO_DMA1		(10)
+#define INT0_LO_DMA2		(11)
+#define INT0_LO_DMA3		(12)
+#define INT0_LO_UART0		(13)
+#define INT0_LO_UART1		(14)
+#define INT0_LO_UART2		(15)
+#define INT0_LO_RSVD1		(16)
+#define INT0_LO_I2C		(17)
+#define INT0_LO_QSPI		(18)
+#define INT0_LO_DTMR0		(19)
+#define INT0_LO_DTMR1		(20)
+#define INT0_LO_DTMR2		(21)
+#define INT0_LO_DTMR3		(22)
+#define INT0_LO_FEC0_TXF	(23)
+#define INT0_LO_FEC0_TXB	(24)
+#define INT0_LO_FEC0_UN		(25)
+#define INT0_LO_FEC0_RL		(26)
+#define INT0_LO_FEC0_RXF	(27)
+#define INT0_LO_FEC0_RXB	(28)
+#define INT0_LO_FEC0_MII	(29)
+#define INT0_LO_FEC0_LC		(30)
+#define INT0_LO_FEC0_HBERR	(31)
+#define INT0_HI_FEC0_GRA	(32)
+#define INT0_HI_FEC0_EBERR	(33)
+#define INT0_HI_FEC0_BABT	(34)
+#define INT0_HI_FEC0_BABR	(35)
+#define INT0_HI_PIT0		(36)
+#define INT0_HI_PIT1		(37)
+#define INT0_HI_PIT2		(38)
+#define INT0_HI_PIT3		(39)
+#define INT0_HI_RNG		(40)
+#define INT0_HI_SKHA		(41)
+#define INT0_HI_MDHA		(42)
+#define INT0_HI_USB		(43)
+#define INT0_HI_USB_EP0		(44)
+#define INT0_HI_USB_EP1		(45)
+#define INT0_HI_USB_EP2		(46)
+#define INT0_HI_USB_EP3		(47)
+/* 48-63 Reserved */
+
+/* 0-22 Reserved */
+#define INT1_LO_FEC1_TXF	(23)
+#define INT1_LO_FEC1_TXB	(24)
+#define INT1_LO_FEC1_UN		(25)
+#define INT1_LO_FEC1_RL		(26)
+#define INT1_LO_FEC1_RXF	(27)
+#define INT1_LO_FEC1_RXB	(28)
+#define INT1_LO_FEC1_MII	(29)
+#define INT1_LO_FEC1_LC		(30)
+#define INT1_LO_FEC1_HBERR	(31)
+#define INT1_HI_FEC1_GRA	(32)
+#define INT1_HI_FEC1_EBERR	(33)
+#define INT1_HI_FEC1_BABT	(34)
+#define INT1_HI_FEC1_BABR	(35)
+/* 36-63 Reserved */
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT	(0x40)
+#define RCM_RCR_SOFTRST		(0x80)
+
+#define FMPLL_SYNSR_LOCK	(0x00000008)
+
+#endif	/* __M5275_H__ */
diff --git a/arch/m68k/include/asm/m5282.h b/arch/m68k/include/asm/m5282.h
new file mode 100644
index 0000000..0c91cf4
--- /dev/null
+++ b/arch/m68k/include/asm/m5282.h
@@ -0,0 +1,591 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * mcf5282.h -- Definitions for Motorola Coldfire 5282
+ */
+
+/****************************************************************************/
+#ifndef	m5282_h
+#define	m5282_h
+
+/*********************************************************************
+* PLL Clock Module
+*********************************************************************/
+/* Bit definitions and macros for PLL_SYNCR */
+#define PLL_SYNCR_LOLRE			(0x8000)
+#define PLL_SYNCR_MFD2			(0x4000)
+#define PLL_SYNCR_MFD1			(0x2000)
+#define PLL_SYNCR_MFD0			(0x1000)
+#define PLL_SYNCR_LOCRE			(0x0800)
+#define PLL_SYNCR_RFC2			(0x0400)
+#define PLL_SYNCR_RFC1			(0x0200)
+#define PLL_SYNCR_RFC0			(0x0100)
+#define PLL_SYNCR_LOCEN			(0x0080)
+#define PLL_SYNCR_DISCLK		(0x0040)
+#define PLL_SYNCR_FWKUP			(0x0020)
+#define PLL_SYNCR_STPMD1		(0x0008)
+#define PLL_SYNCR_STPMD0		(0x0004)
+
+/* Bit definitions and macros for PLL_SYNSR */
+#define PLL_SYNSR_MODE			(0x0080)
+#define PLL_SYNSR_PLLSEL		(0x0040)
+#define PLL_SYNSR_PLLREF		(0x0020)
+#define PLL_SYNSR_LOCKS			(0x0010)
+#define PLL_SYNSR_LOCK			(0x0008)
+#define PLL_SYNSR_LOCS			(0x0004)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_SCM_SWT1		(8)
+#define INT0_LO_DMA_00			(9)
+#define INT0_LO_DMA_01			(10)
+#define INT0_LO_DMA_02			(11)
+#define INT0_LO_DMA_03			(12)
+#define INT0_LO_UART0			(13)
+#define INT0_LO_UART1			(14)
+#define INT0_LO_UART2			(15)
+#define INT0_LO_RSVD1			(16)
+#define INT0_LO_I2C			(17)
+#define INT0_LO_QSPI			(18)
+#define INT0_LO_DTMR0			(19)
+#define INT0_LO_DTMR1			(20)
+#define INT0_LO_DTMR2			(21)
+#define INT0_LO_DTMR3			(22)
+#define INT0_LO_FEC_TXF			(23)
+#define INT0_LO_FEC_TXB			(24)
+#define INT0_LO_FEC_UN			(25)
+#define INT0_LO_FEC_RL			(26)
+#define INT0_LO_FEC_RXF			(27)
+#define INT0_LO_FEC_RXB			(28)
+#define INT0_LO_FEC_MII			(29)
+#define INT0_LO_FEC_LC			(30)
+#define INT0_LO_FEC_HBERR		(31)
+#define INT0_HI_FEC_GRA			(32)
+#define INT0_HI_FEC_EBERR		(33)
+#define INT0_HI_FEC_BABT		(34)
+#define INT0_HI_FEC_BABR		(35)
+#define INT0_HI_PMM_LVDF		(36)
+#define INT0_HI_QADC_CF1		(37)
+#define INT0_HI_QADC_CF2		(38)
+#define INT0_HI_QADC_PF1		(39)
+#define INT0_HI_QADC_PF2		(40)
+#define INT0_HI_GPTA_TOF		(41)
+#define INT0_HI_GPTA_PAIF		(42)
+#define INT0_HI_GPTA_PAOVF		(43)
+#define INT0_HI_GPTA_C0F		(44)
+#define INT0_HI_GPTA_C1F		(45)
+#define INT0_HI_GPTA_C2F		(46)
+#define INT0_HI_GPTA_C3F		(47)
+#define INT0_HI_GPTB_TOF		(48)
+#define INT0_HI_GPTB_PAIF		(49)
+#define INT0_HI_GPTB_PAOVF		(50)
+#define INT0_HI_GPTB_C0F		(51)
+#define INT0_HI_GPTB_C1F		(52)
+#define INT0_HI_GPTB_C2F		(53)
+#define INT0_HI_GPTB_C3F		(54)
+#define INT0_HI_PIT0			(55)
+#define INT0_HI_PIT1			(56)
+#define INT0_HI_PIT2			(57)
+#define INT0_HI_PIT3			(58)
+#define INT0_HI_CFM_CBEIF		(59)
+#define INT0_HI_CFM_CCIF		(60)
+#define INT0_HI_CFM_PVIF		(61)
+#define INT0_HI_CFM_AEIF		(62)
+
+/*
+ * Size of internal RAM
+ */
+
+#define INT_RAM_SIZE	65536
+
+/* General Purpose I/O Module GPIO */
+
+#define MCFGPIO_PORTA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100000))
+#define MCFGPIO_PORTB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100001))
+#define MCFGPIO_PORTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100002))
+#define MCFGPIO_PORTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100003))
+#define MCFGPIO_PORTE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100004))
+#define MCFGPIO_PORTF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100005))
+#define MCFGPIO_PORTG		(*(vu_char *) (CONFIG_SYS_MBAR+0x100006))
+#define MCFGPIO_PORTH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100007))
+#define MCFGPIO_PORTJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100008))
+#define MCFGPIO_PORTDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100009))
+#define MCFGPIO_PORTEH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000A))
+#define MCFGPIO_PORTEL		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000B))
+#define MCFGPIO_PORTAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000C))
+#define MCFGPIO_PORTQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000D))
+#define MCFGPIO_PORTSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000E))
+#define MCFGPIO_PORTTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10000F))
+#define MCFGPIO_PORTTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100010))
+#define MCFGPIO_PORTUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100011))
+
+#define MCFGPIO_DDRA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100014))
+#define MCFGPIO_DDRB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100015))
+#define MCFGPIO_DDRC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100016))
+#define MCFGPIO_DDRD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100017))
+#define MCFGPIO_DDRE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100018))
+#define MCFGPIO_DDRF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100019))
+#define MCFGPIO_DDRG		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001A))
+#define MCFGPIO_DDRH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001B))
+#define MCFGPIO_DDRJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001C))
+#define MCFGPIO_DDRDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001D))
+#define MCFGPIO_DDREH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001E))
+#define MCFGPIO_DDREL		(*(vu_char *) (CONFIG_SYS_MBAR+0x10001F))
+#define MCFGPIO_DDRAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100020))
+#define MCFGPIO_DDRQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100021))
+#define MCFGPIO_DDRSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100022))
+#define MCFGPIO_DDRTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100023))
+#define MCFGPIO_DDRTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100024))
+#define MCFGPIO_DDRUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100025))
+
+#define MCFGPIO_PORTAP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
+#define MCFGPIO_PORTBP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
+#define MCFGPIO_PORTCP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
+#define MCFGPIO_PORTDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
+#define MCFGPIO_PORTEP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
+#define MCFGPIO_PORTFP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
+#define MCFGPIO_PORTGP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
+#define MCFGPIO_PORTHP		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
+#define MCFGPIO_PORTJP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
+#define MCFGPIO_PORTDDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
+#define MCFGPIO_PORTEHP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
+#define MCFGPIO_PORTELP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
+#define MCFGPIO_PORTASP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
+#define MCFGPIO_PORTQSP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
+#define MCFGPIO_PORTSDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
+#define MCFGPIO_PORTTCP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
+#define MCFGPIO_PORTTDP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
+#define MCFGPIO_PORTUAP		(*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
+
+#define MCFGPIO_SETA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100028))
+#define MCFGPIO_SETB		(*(vu_char *) (CONFIG_SYS_MBAR+0x100029))
+#define MCFGPIO_SETC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002A))
+#define MCFGPIO_SETD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002B))
+#define MCFGPIO_SETE		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002C))
+#define MCFGPIO_SETF		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002D))
+#define MCFGPIO_SETG		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002E))
+#define MCFGPIO_SETH		(*(vu_char *) (CONFIG_SYS_MBAR+0x10002F))
+#define MCFGPIO_SETJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100030))
+#define MCFGPIO_SETDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100031))
+#define MCFGPIO_SETEH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100032))
+#define MCFGPIO_SETEL		(*(vu_char *) (CONFIG_SYS_MBAR+0x100033))
+#define MCFGPIO_SETAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100034))
+#define MCFGPIO_SETQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100035))
+#define MCFGPIO_SETSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100036))
+#define MCFGPIO_SETTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x100037))
+#define MCFGPIO_SETTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100038))
+#define MCFGPIO_SETUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x100039))
+
+#define MCFGPIO_CLRA		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003C))
+#define MCFGPIO_CLRB		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003D))
+#define MCFGPIO_CLRC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003E))
+#define MCFGPIO_CLRD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10003F))
+#define MCFGPIO_CLRE		(*(vu_char *) (CONFIG_SYS_MBAR+0x100040))
+#define MCFGPIO_CLRF		(*(vu_char *) (CONFIG_SYS_MBAR+0x100041))
+#define MCFGPIO_CLRG		(*(vu_char *) (CONFIG_SYS_MBAR+0x100042))
+#define MCFGPIO_CLRH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100043))
+#define MCFGPIO_CLRJ		(*(vu_char *) (CONFIG_SYS_MBAR+0x100044))
+#define MCFGPIO_CLRDD		(*(vu_char *) (CONFIG_SYS_MBAR+0x100045))
+#define MCFGPIO_CLREH		(*(vu_char *) (CONFIG_SYS_MBAR+0x100046))
+#define MCFGPIO_CLREL		(*(vu_char *) (CONFIG_SYS_MBAR+0x100047))
+#define MCFGPIO_CLRAS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100048))
+#define MCFGPIO_CLRQS		(*(vu_char *) (CONFIG_SYS_MBAR+0x100049))
+#define MCFGPIO_CLRSD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004A))
+#define MCFGPIO_CLRTC		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004B))
+#define MCFGPIO_CLRTD		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004C))
+#define MCFGPIO_CLRUA		(*(vu_char *) (CONFIG_SYS_MBAR+0x10004D))
+
+#define MCFGPIO_PBCDPAR	(*(vu_char *) (CONFIG_SYS_MBAR+0x100050))
+#define MCFGPIO_PFPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100051))
+#define MCFGPIO_PEPAR		(*(vu_short *)(CONFIG_SYS_MBAR+0x100052))
+#define MCFGPIO_PJPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100054))
+#define MCFGPIO_PSDPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100055))
+#define MCFGPIO_PASPAR		(*(vu_short *)(CONFIG_SYS_MBAR+0x100056))
+#define MCFGPIO_PEHLPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100058))
+#define MCFGPIO_PQSPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x100059))
+#define MCFGPIO_PTCPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005A))
+#define MCFGPIO_PTDPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005B))
+#define MCFGPIO_PUAPAR		(*(vu_char *) (CONFIG_SYS_MBAR+0x10005C))
+
+/* Bit level definitions and macros */
+#define MCFGPIO_PORT7			(0x80)
+#define MCFGPIO_PORT6			(0x40)
+#define MCFGPIO_PORT5			(0x20)
+#define MCFGPIO_PORT4			(0x10)
+#define MCFGPIO_PORT3			(0x08)
+#define MCFGPIO_PORT2			(0x04)
+#define MCFGPIO_PORT1			(0x02)
+#define MCFGPIO_PORT0			(0x01)
+#define MCFGPIO_PORT(x)			(0x01<<x)
+
+#define MCFGPIO_DDR7			(0x80)
+#define MCFGPIO_DDR6			(0x40)
+#define MCFGPIO_DDR5			(0x20)
+#define MCFGPIO_DDR4			(0x10)
+#define MCFGPIO_DDR3			(0x08)
+#define MCFGPIO_DDR2			(0x04)
+#define MCFGPIO_DDR1			(0x02)
+#define MCFGPIO_DDR0			(0x01)
+#define MCFGPIO_DDR(x)			(0x01<<x)
+
+#define MCFGPIO_Px7			(0x80)
+#define MCFGPIO_Px6			(0x40)
+#define MCFGPIO_Px5			(0x20)
+#define MCFGPIO_Px4			(0x10)
+#define MCFGPIO_Px3			(0x08)
+#define MCFGPIO_Px2			(0x04)
+#define MCFGPIO_Px1			(0x02)
+#define MCFGPIO_Px0			(0x01)
+#define MCFGPIO_Px(x)			(0x01<<x)
+
+#define MCFGPIO_PBCDPAR_PBPA		(0x80)
+#define MCFGPIO_PBCDPAR_PCDPA		(0x40)
+
+#define MCFGPIO_PEPAR_PEPA7		(0x4000)
+#define MCFGPIO_PEPAR_PEPA6		(0x1000)
+#define MCFGPIO_PEPAR_PEPA5		(0x0400)
+#define MCFGPIO_PEPAR_PEPA4		(0x0100)
+#define MCFGPIO_PEPAR_PEPA3		(0x0040)
+#define MCFGPIO_PEPAR_PEPA2		(0x0010)
+#define MCFGPIO_PEPAR_PEPA1(x)		(((x)&0x3)<<2)
+#define MCFGPIO_PEPAR_PEPA0(x)		(((x)&0x3))
+
+#define MCFGPIO_PFPAR_PFPA7		(0x80)
+#define MCFGPIO_PFPAR_PFPA6		(0x40)
+#define MCFGPIO_PFPAR_PFPA5		(0x20)
+
+#define MCFGPIO_PJPAR_PJPA7		(0x80)
+#define MCFGPIO_PJPAR_PJPA6		(0x40)
+#define MCFGPIO_PJPAR_PJPA5		(0x20)
+#define MCFGPIO_PJPAR_PJPA4		(0x10)
+#define MCFGPIO_PJPAR_PJPA3		(0x08)
+#define MCFGPIO_PJPAR_PJPA2		(0x04)
+#define MCFGPIO_PJPAR_PJPA1		(0x02)
+#define MCFGPIO_PJPAR_PJPA0		(0x01)
+#define MCFGPIO_PJPAR_PJPA(x)		(0x01<<x)
+
+#define MCFGPIO_PSDPAR_PSDPA		(0x80)
+
+#define MCFGPIO_PASPAR_PASPA5(x)	(((x)&0x3)<<10)
+#define MCFGPIO_PASPAR_PASPA4(x)	(((x)&0x3)<<8)
+#define MCFGPIO_PASPAR_PASPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PASPAR_PASPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PASPAR_PASPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PASPAR_PASPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PEHLPAR_PEHPA		(0x80)
+#define MCFGPIO_PEHLPAR_PELPA		(0x40)
+
+#define MCFGPIO_PQSPAR_PQSPA6		(0x40)
+#define MCFGPIO_PQSPAR_PQSPA5		(0x20)
+#define MCFGPIO_PQSPAR_PQSPA4		(0x10)
+#define MCFGPIO_PQSPAR_PQSPA3		(0x08)
+#define MCFGPIO_PQSPAR_PQSPA2		(0x04)
+#define MCFGPIO_PQSPAR_PQSPA1		(0x02)
+#define MCFGPIO_PQSPAR_PQSPA0		(0x01)
+#define MCFGPIO_PQSPAR_PQSPA(x)		(0x01<<x)
+
+#define MCFGPIO_PTCPAR_PTCPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PTCPAR_PTCPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PTCPAR_PTCPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PTCPAR_PTCPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PTDPAR_PTDPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PTDPAR_PTDPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PTDPAR_PTDPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PTDPAR_PTDPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PUAPAR_PUAPA3		(0x08)
+#define MCFGPIO_PUAPAR_PUAPA2		(0x04)
+#define MCFGPIO_PUAPAR_PUAPA1		(0x02)
+#define MCFGPIO_PUAPAR_PUAPA0		(0x01)
+
+/* System Conrol Module SCM */
+
+#define MCFSCM_RAMBAR		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000008))
+#define MCFSCM_CRSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000010))
+#define MCFSCM_CWCR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000011))
+#define MCFSCM_LPICR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000012))
+#define MCFSCM_CWSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000013))
+
+#define MCFSCM_MPARK		(*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C))
+#define MCFSCM_MPR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000020))
+#define MCFSCM_PACR0		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000024))
+#define MCFSCM_PACR1		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000025))
+#define MCFSCM_PACR2		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000026))
+#define MCFSCM_PACR3		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000027))
+#define MCFSCM_PACR4		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000028))
+#define MCFSCM_PACR5		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A))
+#define MCFSCM_PACR6		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B))
+#define MCFSCM_PACR7		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C))
+#define MCFSCM_PACR8		(*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E))
+#define MCFSCM_GPACR0		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000030))
+#define MCFSCM_GPACR1		(*(vu_char *) (CONFIG_SYS_MBAR+0x00000031))
+
+#define MCFSCM_CRSR_EXT		(0x80)
+#define MCFSCM_CRSR_CWDR	(0x20)
+#define MCFSCM_RAMBAR_BA(x)	((x)&0xFFFF0000)
+#define MCFSCM_RAMBAR_BDE	(0x00000200)
+
+/* Reset Controller Module RCM */
+
+#define MCFRESET_RCR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00110000))
+#define MCFRESET_RSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x00110001))
+
+#define MCFRESET_RCR_SOFTRST	(0x80)
+#define MCFRESET_RCR_FRCRSTOUT	(0x40)
+#define MCFRESET_RCR_LVDF	(0x10)
+#define MCFRESET_RCR_LVDIE	(0x08)
+#define MCFRESET_RCR_LVDRE	(0x04)
+#define MCFRESET_RCR_LVDE	(0x01)
+
+#define MCFRESET_RSR_LVD	(0x40)
+#define MCFRESET_RSR_SOFT	(0x20)
+#define MCFRESET_RSR_WDR	(0x10)
+#define MCFRESET_RSR_POR	(0x08)
+#define MCFRESET_RSR_EXT	(0x04)
+#define MCFRESET_RSR_LOC	(0x02)
+#define MCFRESET_RSR_LOL	(0x01)
+#define MCFRESET_RSR_ALL	(0x7F)
+#define MCFRESET_RCR_SOFTRST	(0x80)
+#define MCFRESET_RCR_FRCRSTOUT	(0x40)
+
+/* Chip Configuration Module CCM */
+
+#define MCFCCM_CCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00110004))
+#define MCFCCM_RCON		(*(vu_short *)(CONFIG_SYS_MBAR+0x00110008))
+#define MCFCCM_CIR		(*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A))
+
+/* Bit level definitions and macros */
+#define MCFCCM_CCR_LOAD		(0x8000)
+#define MCFCCM_CCR_MODE(x)	(((x)&0x0007)<<8)
+#define MCFCCM_CCR_SZEN		(0x0040)
+#define MCFCCM_CCR_PSTEN	(0x0020)
+#define MCFCCM_CCR_BME		(0x0008)
+#define MCFCCM_CCR_BMT(x)	(((x)&0x0007))
+
+#define MCFCCM_CIR_PIN_MASK	(0xFF00)
+#define MCFCCM_CIR_PRN_MASK	(0x00FF)
+
+/* Clock Module */
+
+#define MCFCLOCK_SYNCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x120000))
+#define MCFCLOCK_SYNSR		(*(vu_char *) (CONFIG_SYS_MBAR+0x120002))
+
+#define MCFCLOCK_SYNCR_MFD(x)	(((x)&0x0007)<<12)
+#define MCFCLOCK_SYNCR_RFD(x)	(((x)&0x0007)<<8)
+#define MCFCLOCK_SYNSR_LOCK	0x08
+
+#define MCFSDRAMC_DCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00000040))
+#define MCFSDRAMC_DACR0		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000048))
+#define MCFSDRAMC_DMR0		(*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c))
+#define MCFSDRAMC_DACR1		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000050))
+#define MCFSDRAMC_DMR1		(*(vu_long *) (CONFIG_SYS_MBAR+0x00000054))
+
+#define MCFSDRAMC_DCR_NAM	(0x2000)
+#define MCFSDRAMC_DCR_COC	(0x1000)
+#define MCFSDRAMC_DCR_IS	(0x0800)
+#define MCFSDRAMC_DCR_RTIM_3	(0x0000)
+#define MCFSDRAMC_DCR_RTIM_6	(0x0200)
+#define MCFSDRAMC_DCR_RTIM_9	(0x0400)
+#define MCFSDRAMC_DCR_RC(x)	((x)&0x01FF)
+
+#define MCFSDRAMC_DACR_BASE(x)	((x)&0xFFFC0000)
+#define MCFSDRAMC_DACR_RE	(0x00008000)
+#define MCFSDRAMC_DACR_CASL(x)	(((x)&0x03)<<12)
+#define MCFSDRAMC_DACR_CBM(x)	(((x)&0x07)<<8)
+#define MCFSDRAMC_DACR_PS_32	(0x00000000)
+#define MCFSDRAMC_DACR_PS_16	(0x00000020)
+#define MCFSDRAMC_DACR_PS_8	(0x00000010)
+#define MCFSDRAMC_DACR_IP	(0x00000008)
+#define MCFSDRAMC_DACR_IMRS	(0x00000040)
+
+#define MCFSDRAMC_DMR_BAM_16M	(0x00FC0000)
+#define MCFSDRAMC_DMR_WP	(0x00000100)
+#define MCFSDRAMC_DMR_CI	(0x00000040)
+#define MCFSDRAMC_DMR_AM	(0x00000020)
+#define MCFSDRAMC_DMR_SC	(0x00000010)
+#define MCFSDRAMC_DMR_SD	(0x00000008)
+#define MCFSDRAMC_DMR_UC	(0x00000004)
+#define MCFSDRAMC_DMR_UD	(0x00000002)
+#define MCFSDRAMC_DMR_V		(0x00000001)
+
+#define MCFWTM_WCR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140000))
+#define MCFWTM_WMR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140002))
+#define MCFWTM_WCNTR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140004))
+#define MCFWTM_WSR		(*(vu_short *)(CONFIG_SYS_MBAR+0x00140006))
+
+/*********************************************************************
+* General Purpose Timer (GPT) Module
+*********************************************************************/
+
+#define MCFGPTA_GPTIOS		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000))
+#define MCFGPTA_GPTCFORC	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001))
+#define MCFGPTA_GPTOC3M		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002))
+#define MCFGPTA_GPTOC3D		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003))
+#define MCFGPTA_GPTCNT		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004))
+#define MCFGPTA_GPTSCR1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006))
+#define MCFGPTA_GPTTOV		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008))
+#define MCFGPTA_GPTCTL1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009))
+#define MCFGPTA_GPTCTL2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B))
+#define MCFGPTA_GPTIE		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C))
+#define MCFGPTA_GPTSCR2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D))
+#define MCFGPTA_GPTFLG1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E))
+#define MCFGPTA_GPTFLG2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F))
+#define MCFGPTA_GPTC0		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010))
+#define MCFGPTA_GPTC1		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012))
+#define MCFGPTA_GPTC2		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014))
+#define MCFGPTA_GPTC3		(*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016))
+#define MCFGPTA_GPTPACTL	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018))
+#define MCFGPTA_GPTPAFLG	(*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019))
+#define MCFGPTA_GPTPACNT	(*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A))
+#define MCFGPTA_GPTPORT		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D))
+#define MCFGPTA_GPTDDR		(*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E))
+
+#define MCFGPTB_GPTIOS		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000))
+#define MCFGPTB_GPTCFORC	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001))
+#define MCFGPTB_GPTOC3M		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002))
+#define MCFGPTB_GPTOC3D		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003))
+#define MCFGPTB_GPTCNT		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004))
+#define MCFGPTB_GPTSCR1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006))
+#define MCFGPTB_GPTTOV		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008))
+#define MCFGPTB_GPTCTL1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009))
+#define MCFGPTB_GPTCTL2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B))
+#define MCFGPTB_GPTIE		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C))
+#define MCFGPTB_GPTSCR2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D))
+#define MCFGPTB_GPTFLG1		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E))
+#define MCFGPTB_GPTFLG2		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F))
+#define MCFGPTB_GPTC0		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010))
+#define MCFGPTB_GPTC1		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012))
+#define MCFGPTB_GPTC2		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014))
+#define MCFGPTB_GPTC3		(*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016))
+#define MCFGPTB_GPTPACTL	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018))
+#define MCFGPTB_GPTPAFLG	(*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019))
+#define MCFGPTB_GPTPACNT	(*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A))
+#define MCFGPTB_GPTPORT		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D))
+#define MCFGPTB_GPTDDR		(*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E))
+
+/* Bit level definitions and macros */
+#define MCFGPT_GPTIOS_IOS3		(0x08)
+#define MCFGPT_GPTIOS_IOS2		(0x04)
+#define MCFGPT_GPTIOS_IOS1		(0x02)
+#define MCFGPT_GPTIOS_IOS0		(0x01)
+
+#define MCFGPT_GPTCFORC_FOC3		(0x08)
+#define MCFGPT_GPTCFORC_FOC2		(0x04)
+#define MCFGPT_GPTCFORC_FOC1		(0x02)
+#define MCFGPT_GPTCFORC_FOC0		(0x01)
+
+#define MCFGPT_GPTOC3M_OC3M3		(0x08)
+#define MCFGPT_GPTOC3M_OC3M2		(0x04)
+#define MCFGPT_GPTOC3M_OC3M1		(0x02)
+#define MCFGPT_GPTOC3M_OC3M0		(0x01)
+
+#define MCFGPT_GPTOC3M_OC3D(x)		(((x)&0x04))
+
+#define MCFGPT_GPTSCR1_GPTEN		(0x80)
+#define MCFGPT_GPTSCR1_TFFCA		(0x10)
+
+#define MCFGPT_GPTTOV3			(0x08)
+#define MCFGPT_GPTTOV2			(0x04)
+#define MCFGPT_GPTTOV1			(0x02)
+#define MCFGPT_GPTTOV0			(0x01)
+
+#define MCFGPT_GPTCTL_OMOL3(x)		(((x)&0x03)<<6)
+#define MCFGPT_GPTCTL_OMOL2(x)		(((x)&0x03)<<4)
+#define MCFGPT_GPTCTL_OMOL1(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTCTL_OMOL0(x)		(((x)&0x03))
+
+#define MCFGPT_GPTCTL2_EDG3(x)		(((x)&0x03)<<6)
+#define MCFGPT_GPTCTL2_EDG2(x)		(((x)&0x03)<<4)
+#define MCFGPT_GPTCTL2_EDG1(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTCTL2_EDG0(x)		(((x)&0x03))
+
+#define MCFGPT_GPTIE_C3I		(0x08)
+#define MCFGPT_GPTIE_C2I		(0x04)
+#define MCFGPT_GPTIE_C1I		(0x02)
+#define MCFGPT_GPTIE_C0I		(0x01)
+
+#define MCFGPT_GPTSCR2_TOI		(0x80)
+#define MCFGPT_GPTSCR2_PUPT		(0x20)
+#define MCFGPT_GPTSCR2_RDPT		(0x10)
+#define MCFGPT_GPTSCR2_TCRE		(0x08)
+#define MCFGPT_GPTSCR2_PR(x)		(((x)&0x07))
+
+#define MCFGPT_GPTFLG1_C3F		(0x08)
+#define MCFGPT_GPTFLG1_C2F		(0x04)
+#define MCFGPT_GPTFLG1_C1F		(0x02)
+#define MCFGPT_GPTFLG1_C0F		(0x01)
+
+#define MCFGPT_GPTFLG2_TOF		(0x80)
+#define MCFGPT_GPTFLG2_C3F		(0x08)
+#define MCFGPT_GPTFLG2_C2F		(0x04)
+#define MCFGPT_GPTFLG2_C1F		(0x02)
+#define MCFGPT_GPTFLG2_C0F		(0x01)
+
+#define MCFGPT_GPTPACTL_PAE		(0x40)
+#define MCFGPT_GPTPACTL_PAMOD		(0x20)
+#define MCFGPT_GPTPACTL_PEDGE		(0x10)
+#define MCFGPT_GPTPACTL_CLK_PACLK	(0x04)
+#define MCFGPT_GPTPACTL_CLK_PACLK256	(0x08)
+#define MCFGPT_GPTPACTL_CLK_PACLK65536	(0x0C)
+#define MCFGPT_GPTPACTL_CLK(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTPACTL_PAOVI		(0x02)
+#define MCFGPT_GPTPACTL_PAI		(0x01)
+
+#define MCFGPT_GPTPAFLG_PAOVF		(0x02)
+#define MCFGPT_GPTPAFLG_PAIF		(0x01)
+
+#define MCFGPT_GPTPORT_PORTT3		(0x08)
+#define MCFGPT_GPTPORT_PORTT2		(0x04)
+#define MCFGPT_GPTPORT_PORTT1		(0x02)
+#define MCFGPT_GPTPORT_PORTT0		(0x01)
+
+#define MCFGPT_GPTDDR_DDRT3		(0x08)
+#define MCFGPT_GPTDDR_DDRT2		(0x04)
+#define MCFGPT_GPTDDR_DDRT1		(0x02)
+#define MCFGPT_GPTDDR_DDRT0		(0x01)
+
+/* Coldfire Flash Module CFM */
+
+#define MCFCFM_MCR			(*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000))
+#define MCFCFM_MCR_LOCK			(0x0400)
+#define MCFCFM_MCR_PVIE			(0x0200)
+#define MCFCFM_MCR_AEIE			(0x0100)
+#define MCFCFM_MCR_CBEIE		(0x0080)
+#define MCFCFM_MCR_CCIE			(0x0040)
+#define MCFCFM_MCR_KEYACC		(0x0020)
+
+#define MCFCFM_CLKD			(*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002))
+
+#define MCFCFM_SEC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008))
+#define MCFCFM_SEC_KEYEN		(0x80000000)
+#define MCFCFM_SEC_SECSTAT		(0x40000000)
+
+#define MCFCFM_PROT			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010))
+#define MCFCFM_SACC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014))
+#define MCFCFM_DACC			(*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018))
+#define MCFCFM_USTAT			(*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020))
+#define MCFCFM_USTAT_CBEIF		0x80
+#define MCFCFM_USTAT_CCIF		0x40
+#define MCFCFM_USTAT_PVIOL		0x20
+#define MCFCFM_USTAT_ACCERR		0x10
+#define MCFCFM_USTAT_BLANK		0x04
+
+#define MCFCFM_CMD			(*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024))
+#define MCFCFM_CMD_ERSVER		0x05
+#define MCFCFM_CMD_PGERSVER		0x06
+#define MCFCFM_CMD_PGM			0x20
+#define MCFCFM_CMD_PGERS		0x40
+#define MCFCFM_CMD_MASERS		0x41
+
+/****************************************************************************/
+#endif				/* m5282_h */
diff --git a/arch/m68k/include/asm/m5301x.h b/arch/m68k/include/asm/m5301x.h
new file mode 100644
index 0000000..40a05d2
--- /dev/null
+++ b/arch/m68k/include/asm/m5301x.h
@@ -0,0 +1,591 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * m5301x.h -- Definitions for Freescale Coldfire 5301x
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef m5301x_h
+#define m5301x_h
+
+/* *** System Control Module (SCM) *** */
+#define SCM_MPR_MPROT0(x)		(((x) & 0x0F) << 28)
+#define SCM_MPR_MPROT1(x)		(((x) & 0x0F) << 24)
+#define SCM_MPR_MPROT2(x)		(((x) & 0x0F) << 20)
+#define SCM_MPR_MPROT4(x)		(((x) & 0x0F) << 12)
+#define SCM_MPR_MPROT5(x)		(((x) & 0x0F) << 8)
+#define SCM_MPR_MPROT6(x)		(((x) & 0x0F) << 4)
+#define MPROT_MTR			4
+#define MPROT_MTW			2
+#define MPROT_MPL			1
+
+#define SCM_PACRA_PACR0(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRA_PACR1(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRA_PACR2(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRA_PACR5(x)		(((x) & 0x0F) << 8)
+
+#define SCM_PACRB_PACR12(x)		(((x) & 0x0F) << 12)
+#define SCM_PACRB_PACR13(x)		(((x) & 0x0F) << 8)
+
+#define SCM_PACRC_PACR16(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRC_PACR17(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRC_PACR18(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRC_PACR19(x)		(((x) & 0x0F) << 16)
+#define SCM_PACRC_PACR21(x)		(((x) & 0x0F) << 8)
+#define SCM_PACRC_PACR22(x)		(((x) & 0x0F) << 4)
+#define SCM_PACRC_PACR23(x)		((x) & 0x0F)
+
+#define SCM_PACRD_PACR24(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRD_PACR25(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRD_PACR26(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRD_PACR28(x)		(((x) & 0x0F) << 12)
+#define SCM_PACRD_PACR29(x)		(((x) & 0x0F) << 8)
+#define SCM_PACRD_PACR30(x)		(((x) & 0x0F) << 4)
+#define SCM_PACRD_PACR31(x)		((x) & 0x0F)
+
+#define SCM_PACRE_PACR32(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRE_PACR33(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRE_PACR34(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRE_PACR35(x)		(((x) & 0x0F) << 16)
+#define SCM_PACRE_PACR36(x)		(((x) & 0x0F) << 12)
+#define SCM_PACRE_PACR37(x)		(((x) & 0x0F) << 8)
+#define SCM_PACRE_PACR39(x)		((x) & 0x0F)
+
+#define SCM_PACRF_PACR40(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRF_PACR41(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRF_PACR42(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRF_PACR43(x)		(((x) & 0x0F) << 16)
+#define SCM_PACRF_PACR44(x)		(((x) & 0x0F) << 12)
+#define SCM_PACRF_PACR45(x)		(((x) & 0x0F) << 8)
+#define SCM_PACRF_PACR46(x)		(((x) & 0x0F) << 4)
+#define SCM_PACRF_PACR47(x)		((x) & 0x0F)
+
+#define SCM_PACRG_PACR48(x)		(((x) & 0x0F) << 28)
+#define SCM_PACRG_PACR49(x)		(((x) & 0x0F) << 24)
+#define SCM_PACRG_PACR50(x)		(((x) & 0x0F) << 20)
+#define SCM_PACRG_PACR51(x)		(((x) & 0x0F) << 16)
+
+#define PACR_SP	4
+#define PACR_WP	2
+#define PACR_TP	1
+
+#define SCM_CWCR_RO			(0x8000)
+#define SCM_CWCR_CWR_WH			(0x0100)
+#define SCM_CWCR_CWE			(0x0080)
+#define SCM_CWCR_CWRI_WINDOW		(0x0060)
+#define SCM_CWCR_CWRI_RESET		(0x0040)
+#define SCM_CWCR_CWRI_INT_RESET		(0x0020)
+#define SCM_CWCR_CWRI_INT		(0x0000)
+#define SCM_CWCR_CWT(x)			(((x) & 0x001F))
+
+#define SCM_ISR_CFEI			(0x02)
+#define SCM_ISR_CWIC			(0x01)
+
+#define BCR_GBR				(0x00000200)
+#define BCR_GBW				(0x00000100)
+#define BCR_S7				(0x00000080)
+#define BCR_S6				(0x00000040)
+#define BCR_S4				(0x00000010)
+#define BCR_S1				(0x00000002)
+
+#define SCM_CFIER_ECFEI			(0x01)
+
+#define SCM_CFLOC_LOC			(0x80)
+
+#define SCM_CFATR_WRITE			(0x80)
+#define SCM_CFATR_SZ32			(0x20)
+#define SCM_CFATR_SZ16			(0x10)
+#define SCM_CFATR_SZ08			(0x00)
+#define SCM_CFATR_CACHE			(0x08)
+#define SCM_CFATR_MODE			(0x02)
+#define SCM_CFATR_TYPE			(0x01)
+
+/* *** Interrupt Controller (INTC) *** */
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_EDMA_00			(8)
+#define INT0_LO_EDMA_01			(9)
+#define INT0_LO_EDMA_02			(10)
+#define INT0_LO_EDMA_03			(11)
+#define INT0_LO_EDMA_04			(12)
+#define INT0_LO_EDMA_05			(13)
+#define INT0_LO_EDMA_06			(14)
+#define INT0_LO_EDMA_07			(15)
+#define INT0_LO_EDMA_08			(16)
+#define INT0_LO_EDMA_09			(17)
+#define INT0_LO_EDMA_10			(18)
+#define INT0_LO_EDMA_11			(19)
+#define INT0_LO_EDMA_12			(20)
+#define INT0_LO_EDMA_13			(21)
+#define INT0_LO_EDMA_14			(22)
+#define INT0_LO_EDMA_15			(23)
+#define INT0_LO_EDMA_ERR		(24)
+#define INT0_LO_SCM_CWIC		(25)
+#define INT0_LO_UART0			(26)
+#define INT0_LO_UART1			(27)
+#define INT0_LO_UART2			(28)
+#define INT0_LO_RSVD1			(29)
+#define INT0_LO_I2C			(30)
+#define INT0_LO_DSPI			(31)
+#define INT0_HI_DTMR0			(32)
+#define INT0_HI_DTMR1			(33)
+#define INT0_HI_DTMR2			(34)
+#define INT0_HI_DTMR3			(35)
+#define INT0_HI_FEC0_TXF		(36)
+#define INT0_HI_FEC0_TXB		(37)
+#define INT0_HI_FEC0_UN			(38)
+#define INT0_HI_FEC0_RL			(39)
+#define INT0_HI_FEC0_RXF		(40)
+#define INT0_HI_FEC0_RXB		(41)
+#define INT0_HI_FEC0_MII		(42)
+#define INT0_HI_FEC0_LC			(43)
+#define INT0_HI_FEC0_HBERR		(44)
+#define INT0_HI_FEC0_GRA		(45)
+#define INT0_HI_FEC0_EBERR		(46)
+#define INT0_HI_FEC0_BABT		(47)
+#define INT0_HI_FEC0_BABR		(48)
+#define INT0_HI_FEC1_TXF		(49)
+#define INT0_HI_FEC1_TXB		(50)
+#define INT0_HI_FEC1_UN			(51)
+#define INT0_HI_FEC1_RL			(52)
+#define INT0_HI_FEC1_RXF		(53)
+#define INT0_HI_FEC1_RXB		(54)
+#define INT0_HI_FEC1_MII		(55)
+#define INT0_HI_FEC1_LC			(56)
+#define INT0_HI_FEC1_HBERR		(57)
+#define INT0_HI_FEC1_GRA		(58)
+#define INT0_HI_FEC1_EBERR		(59)
+#define INT0_HI_FEC1_BABT		(60)
+#define INT0_HI_FEC1_BABR		(61)
+#define INT0_HI_SCM_CFEI		(62)
+
+/* 0 - 24 reserved */
+#define INT1_LO_EPORT1_FLAG0		(25)
+#define INT1_LO_EPORT1_FLAG1		(26)
+#define INT1_LO_EPORT1_FLAG2		(27)
+#define INT1_LO_EPORT1_FLAG3		(28)
+#define INT1_LO_EPORT1_FLAG4		(29)
+#define INT1_LO_EPORT1_FLAG5		(30)
+#define INT1_LO_EPORT1_FLAG6		(31)
+#define INT1_LO_EPORT1_FLAG7		(32)
+#define INT1_HI_DSPI_EOQF		(33)
+#define INT1_HI_DSPI_TFFF		(34)
+#define INT1_HI_DSPI_TCF		(35)
+#define INT1_HI_DSPI_TFUF		(36)
+#define INT1_HI_DSPI_RFDF		(37)
+#define INT1_HI_DSPI_RFOF		(38)
+#define INT1_HI_DSPI_RFOF_TFUF		(39)
+#define INT1_HI_RNG_EI			(40)
+#define INT1_HI_PLL_LOCF		(41)
+#define INT1_HI_PLL_LOLF		(42)
+#define INT1_HI_PIT0			(43)
+#define INT1_HI_PIT1			(44)
+#define INT1_HI_PIT2			(45)
+#define INT1_HI_PIT3			(46)
+#define INT1_HI_USBOTG_STS		(47)
+#define INT1_HI_USBHOST_STS		(48)
+#define INT1_HI_SSI			(49)
+/* 50 - 51 reserved */
+#define INT1_HI_RTC			(52)
+#define INT1_HI_CCM_USBSTAT		(53)
+#define INT1_HI_CODEC_OR		(54)
+#define INT1_HI_CODEC_RF_TE		(55)
+#define INT1_HI_CODEC_ROE		(56)
+#define INT1_HI_CODEC_TUE		(57)
+/* 58 reserved */
+#define INT1_HI_SIM1_DATA		(59)
+#define INT1_HI_SIM1_GENERAL		(60)
+/* 61 - 62 reserved */
+#define INT1_HI_SDHC			(63)
+
+/* *** Reset Controller Module (RCM) *** */
+#define RCM_RCR_SOFTRST			(0x80)
+#define RCM_RCR_FRCRSTOUT		(0x40)
+
+#define RCM_RSR_SOFT			(0x20)
+#define RCM_RSR_LOC			(0x10)
+#define RCM_RSR_POR			(0x08)
+#define RCM_RSR_EXT			(0x04)
+#define RCM_RSR_WDR_CORE		(0x02)
+#define RCM_RSR_LOL			(0x01)
+
+/* *** Chip Configuration Module (CCM) *** */
+#define CCM_CCR_CSC			(0x0020)
+#define CCM_CCR_BOOTPS			(0x0010)
+#define CCM_CCR_LOAD			(0x0008)
+#define CCM_CCR_OSC_MODE		(0x0004)
+#define CCM_CCR_SDR_MODE		(0x0002)
+#define CCM_CCR_RESERVED		(0x0001)
+
+#define CCM_RCON_SDR_32BIT_UNIFIED	(0x0012)
+#define CCM_RCON_DDR_8BIT_SPLIT		(0x0010)
+#define CCM_RCON_SDR_16BIT_UNIFIED	(0x0002)
+#define CCM_RCON_DDR_16BIT_SPLIT	(0x0000)
+
+#define CCM_CIR_PIN(x)			(((x) & 0x03FF) << 6)
+#define CCM_CIR_PRN(x)			((x) & 0x003F)
+
+#define CCM_MISCCR_FECM			(0x8000)
+#define CCM_MISCCR_CDCSRC		(0x4000)
+#define CCM_MISCCR_PLL_LOCK		(0x2000)
+#define CCM_MISCCR_LIMP			(0x1000)
+#define CCM_MISCCR_BME			(0x8000)
+#define CCM_MISCCR_BMT_UNMASK		(0xF8FF)
+#define CCM_MISCCR_BMT(x)		(((x) & 0x0007) << 8)
+#define CCM_MISCCR_BMT_512		(0x0700)
+#define CCM_MISCCR_BMT_1024		(0x0600)
+#define CCM_MISCCR_BMT_2048		(0x0500)
+#define CCM_MISCCR_BMT_4096		(0x0400)
+#define CCM_MISCCR_BMT_8192		(0x0300)
+#define CCM_MISCCR_BMT_16384		(0x0200)
+#define CCM_MISCCR_BMT_32768		(0x0100)
+#define CCM_MISCCR_BMT_65536		(0x0000)
+#define CCM_MISCCR_TIM_DMA		(0x0020)
+#define CCM_MISCCR_SSI_SRC		(0x0010)
+#define CCM_MISCCR_USBH_OC		(0x0008)
+#define CCM_MISCCR_USBO_OC		(0x0004)
+#define CCM_MISCCR_USB_PUE		(0x0002)
+#define CCM_MISCCR_USB_SRC		(0x0001)
+
+#define CCM_CDR_LPDIV(x)		(((x) & 0x0F) << 8)
+#define CCM_CDR_SSIDIV(x)		((x) & 0xFF)
+
+#define CCM_UOCSR_DPPD			(0x2000)
+#define CCM_UOCSR_DMPD			(0x1000)
+#define CCM_UOCSR_DRV_VBUS		(0x0800)
+#define CCM_UOCSR_CRG_VBUS		(0x0400)
+#define CCM_UOCSR_DCR_VBUS		(0x0200)
+#define CCM_UOCSR_DPPU			(0x0100)
+#define CCM_UOCSR_AVLD			(0x0080)
+#define CCM_UOCSR_BVLD			(0x0040)
+#define CCM_UOCSR_VVLD			(0x0020)
+#define CCM_UOCSR_SEND			(0x0010)
+#define CCM_UOCSR_PWRFLT		(0x0008)
+#define CCM_UOCSR_WKUP			(0x0004)
+#define CCM_UOCSR_UOMIE			(0x0002)
+#define CCM_UOCSR_XPDE			(0x0001)
+
+#define CCM_UHCSR_PORTIND(x)		(((x) & 0x0003) << 14)
+#define CCM_UHCSR_DRV_VBUS		(0x0010)
+#define CCM_UHCSR_PWRFLT		(0x0008)
+#define CCM_UHCSR_WKUP			(0x0004)
+#define CCM_UHCSR_UHMIE			(0x0002)
+#define CCM_UHCSR_XPDE			(0x0001)
+
+#define CCM_CODCR_BGREN			(0x8000)
+#define CCM_CODCR_REGEN			(0x0080)
+
+#define CCM_MISC2_IGNLL			(0x0008)
+#define CCM_MISC2_DPS			(0x0001)
+
+/* *** General Purpose I/O (GPIO) *** */
+#define GPIO_PDR_FBCTL			((x) & 0x0F)
+#define GPIO_PDR_BE			((x) & 0x0F)
+#define GPIO_PDR_CS32			(((x) & 0x03) << 4)
+#define GPIO_PDR_CS10			(((x) & 0x03) << 4)
+#define GPIO_PDR_DSPI			((x) & 0x7F)
+#define GPIO_PDR_FEC0			((x) & 0x7F)
+#define GPIO_PDR_FECI2C			((x) & 0x3F)
+#define GPIO_PDR_SIMP1			((x) & 0x1F)
+#define GPIO_PDR_SIMP0			((x) & 0x1F)
+#define GPIO_PDR_TIMER			((x) & 0x0F)
+#define GPIO_PDR_UART			((x) & 0x3F)
+#define GPIO_PDR_DEBUG			(0x01)
+#define GPIO_PDR_SDHC			((x) & 0x3F)
+#define GPIO_PDR_SSI			((x) & 0x1F)
+
+#define GPIO_PAR_FBCTL_OE		(0x80)
+#define GPIO_PAR_FBCTL_TA		(0x40)
+#define GPIO_PAR_FBCTL_RWB		(0x20)
+#define GPIO_PAR_FBCTL_TS		(0x18)
+
+#define GPIO_PAR_BE3			(0x40)
+#define GPIO_PAR_BE2			(0x10)
+#define GPIO_PAR_BE1			(0x04)
+#define GPIO_PAR_BE0			(0x01)
+
+#define GPIO_PAR_CS5			(0x40)
+#define GPIO_PAR_CS4			(0x10)
+#define GPIO_PAR_CS1_UNMASK		(0xF3)
+#define GPIO_PAR_CS1_CS1		(0x0C)
+#define GPIO_PAR_CS1_SDCS1		(0x08)
+#define GPIO_PAR_CS0_UNMASK		(0xFC)
+#define GPIO_PAR_CS0_CS0		(0x03)
+#define GPIO_PAR_CS0_CS4		(0x02)
+
+#define GPIO_PAR_DSPIH_SIN_UNMASK	(0x3F)
+#define GPIO_PAR_DSPIH_SIN		(0xC0)
+#define GPIO_PAR_DSPIH_SIN_U2RXD	(0x80)
+#define GPIO_PAR_DSPIH_SOUT_UNMASK	(0xCF)
+#define GPIO_PAR_DSPIH_SOUT		(0x30)
+#define GPIO_PAR_DSPIH_SOUT_U2TXD	(0x20)
+#define GPIO_PAR_DSPIH_SCK_UNMASK	(0xF3)
+#define GPIO_PAR_DSPIH_SCK		(0x0C)
+#define GPIO_PAR_DSPIH_SCK_U2CTS	(0x08)
+#define GPIO_PAR_DSPIH_PCS0_UNMASK	(0xFC)
+#define GPIO_PAR_DSPIH_PCS0		(0x03)
+#define GPIO_PAR_DSPIH_PCS0_U2RTS	(0x02)
+
+#define GPIO_PAR_DSPIL_PCS1_UNMASK	(0x3F)
+#define GPIO_PAR_DSPIL_PCS1		(0xC0)
+#define GPIO_PAR_DSPIL_PCS2_UNMASK	(0xCF)
+#define GPIO_PAR_DSPIL_PCS2		(0x30)
+#define GPIO_PAR_DSPIL_PCS2_USBH_OC	(0x20)
+#define GPIO_PAR_DSPIL_PCS3_UNMASK	(0xF3)
+#define GPIO_PAR_DSPIL_PCS3		(0x0C)
+#define GPIO_PAR_DSPIL_PCS3_USBH_EN	(0x08)
+
+#define GPIO_PAR_FEC1_7W_FEC		(0x40)
+#define GPIO_PAR_FEC1_RMII_FEC		(0x10)
+#define GPIO_PAR_FEC0_7W_FEC		(0x04)
+#define GPIO_PAR_FEC0_RMII_FEC		(0x01)
+
+/* GPIO_PAR_FECI2C */
+#define GPIO_PAR_FECI2C_RMII0_UNMASK	(0x3F)
+#define GPIO_PAR_FECI2C_MDC0		(0x80)
+#define GPIO_PAR_FECI2C_MDIO0		(0x40)
+#define GPIO_PAR_FECI2C_RMII1_UNMASK	(0xCF)
+#define GPIO_PAR_FECI2C_MDC1		(0x20)
+#define GPIO_PAR_FECI2C_MDIO1		(0x10)
+#define GPIO_PAR_FECI2C_SDA_UNMASK	(0xF3)
+#define GPIO_PAR_FECI2C_SDA(x)		(((x) & 0x03) << 2)
+#define GPIO_PAR_FECI2C_SDA_SDA		(0x0C)
+#define GPIO_PAR_FECI2C_SDA_U2TXD	(0x08)
+#define GPIO_PAR_FECI2C_SDA_MDIO1	(0x04)
+#define GPIO_PAR_FECI2C_SCL_UNMASK	(0xFC)
+#define GPIO_PAR_FECI2C_SCL(x)		((x) & 0x03)
+#define GPIO_PAR_FECI2C_SCL_SCL		(0x03)
+#define GPIO_PAR_FECI2C_SCL_U2RXD	(0x02)
+#define GPIO_PAR_FECI2C_SCL_MDC1	(0x01)
+
+#define GPIO_PAR_IRQ0H_IRQ07_UNMASK	(0x3F)
+#define GPIO_PAR_IRQ0H_IRQ06_UNMASK	(0xCF)
+#define GPIO_PAR_IRQ0H_IRQ06_USBCLKIN	(0x10)
+#define GPIO_PAR_IRQ0H_IRQ04_UNMASK	(0xFC)
+#define GPIO_PAR_IRQ0H_IRQ04_DREQ0	(0x02)
+
+#define GPIO_PAR_IRQ0L_IRQ01_UNMASK	(0xF3)
+#define GPIO_PAR_IRQ0L_IRQ01_DREQ1	(0x08)
+
+#define GPIO_PAR_IRQ1H_IRQ17_DDATA3	(0x40)
+#define GPIO_PAR_IRQ1H_IRQ16_DDATA2	(0x10)
+#define GPIO_PAR_IRQ1H_IRQ15_DDATA1	(0x04)
+#define GPIO_PAR_IRQ1H_IRQ14_DDATA0	(0x01)
+
+#define GPIO_PAR_IRQ1L_IRQ13_PST3	(0x40)
+#define GPIO_PAR_IRQ1L_IRQ12_PST2	(0x10)
+#define GPIO_PAR_IRQ1L_IRQ11_PST1	(0x04)
+#define GPIO_PAR_IRQ1L_IRQ10_PST0	(0x01)
+
+#define GPIO_PAR_SIMP1H_DATA1_UNMASK	(0x3F)
+#define GPIO_PAR_SIMP1H_DATA1_SIMDATA1	(0xC0)
+#define GPIO_PAR_SIMP1H_DATA1_SSITXD	(0x80)
+#define GPIO_PAR_SIMP1H_DATA1_U1TXD	(0x40)
+#define GPIO_PAR_SIMP1H_VEN1_UNMASK	(0xCF)
+#define GPIO_PAR_SIMP1H_VEN1_SIMVEN1	(0x30)
+#define GPIO_PAR_SIMP1H_VEN1_SSIRXD	(0x20)
+#define GPIO_PAR_SIMP1H_VEN1_U1RXD	(0x10)
+#define GPIO_PAR_SIMP1H_RST1_UNMASK	(0xF3)
+#define GPIO_PAR_SIMP1H_RST1_SIMRST1	(0x0C)
+#define GPIO_PAR_SIMP1H_RST1_SSIFS	(0x08)
+#define GPIO_PAR_SIMP1H_RST1_U1RTS	(0x04)
+#define GPIO_PAR_SIMP1H_PD1_UNMASK	(0xFC)
+#define GPIO_PAR_SIMP1H_PD1_SIMPD1	(0x03)
+#define GPIO_PAR_SIMP1H_PD1_SSIBCLK	(0x02)
+#define GPIO_PAR_SIMP1H_PD1_U1CTS	(0x01)
+
+#define GPIO_PAR_SIMP1L_CLK_UNMASK	(0x3F)
+#define GPIO_PAR_SIMP1L_CLK_CLK1	(0xC0)
+#define GPIO_PAR_SIMP1L_CLK_SSIMCLK	(0x80)
+
+#define GPIO_PAR_SIMP0_DATA0		(0x10)
+#define GPIO_PAR_SIMP0_VEN0		(0x08)
+#define GPIO_PAR_SIMP0_RST0		(0x04)
+#define GPIO_PAR_SIMP0_PD0		(0x02)
+#define GPIO_PAR_SIMP0_CLK0		(0x01)
+
+#define GPIO_PAR_TIN3(x)		(((x) & 0x03) << 6)
+#define GPIO_PAR_TIN2(x)		(((x) & 0x03) << 4)
+#define GPIO_PAR_TIN1(x)		(((x) & 0x03) << 2)
+#define GPIO_PAR_TIN0(x)		((x) & 0x03)
+#define GPIO_PAR_TIN3_UNMASK		(0x3F)
+#define GPIO_PAR_TIN3_TIN3		(0xC0)
+#define GPIO_PAR_TIN3_TOUT3		(0x80)
+#define GPIO_PAR_TIN3_IRQ03		(0x40)
+#define GPIO_PAR_TIN2_UNMASK		(0xCF)
+#define GPIO_PAR_TIN2_TIN2		(0x30)
+#define GPIO_PAR_TIN2_TOUT2		(0x20)
+#define GPIO_PAR_TIN2_IRQ02		(0x10)
+#define GPIO_PAR_TIN1_UNMASK		(0xF3)
+#define GPIO_PAR_TIN1_TIN1		(0x0C)
+#define GPIO_PAR_TIN1_TOUT1		(0x08)
+#define GPIO_PAR_TIN1_DACK1		(0x04)
+#define GPIO_PAR_TIN0_UNMASK		(0xFC)
+#define GPIO_PAR_TIN0_TIN0		(0x03)
+#define GPIO_PAR_TIN0_TOUT0		(0x02)
+#define GPIO_PAR_TIN0_CODEC_ALTCLK	(0x01)
+
+#define GPIO_PAR_UART_U2TXD		(0x80)
+#define GPIO_PAR_UART_U2RXD		(0x40)
+#define GPIO_PAR_UART_U0TXD		(0x20)
+#define GPIO_PAR_UART_U0RXD		(0x10)
+#define GPIO_PAR_UART_RTS0(x)		(((x) & 0x03) << 2)
+#define GPIO_PAR_UART_CTS0(x)		((x) & 0x03)
+#define GPIO_PAR_UART_RTS0_UNMASK	(0xF3)
+#define GPIO_PAR_UART_RTS0_U0RTS	(0x0C)
+#define GPIO_PAR_UART_RTS0_USBO_VBOC	(0x08)
+#define GPIO_PAR_UART_CTS0_UNMASK	(0xFC)
+#define GPIO_PAR_UART_CTS0_U0CTS	(0x03)
+#define GPIO_PAR_UART_CTS0_USB0_VBEN	(0x02)
+#define GPIO_PAR_UART_CTS0_USB_PULLUP	(0x01)
+
+#define GPIO_PAR_DEBUG_ALLPST		(0x80)
+
+#define GPIO_PAR_SDHC_DATA3		(0x20)
+#define GPIO_PAR_SDHC_DATA2		(0x10)
+#define GPIO_PAR_SDHC_DATA1		(0x08)
+#define GPIO_PAR_SDHC_DATA0		(0x04)
+#define GPIO_PAR_SDHC_CMD		(0x02)
+#define GPIO_PAR_SDHC_CLK		(0x01)
+
+#define GPIO_PAR_SSIH_RXD(x)		(((x) & 0x03) << 6)
+#define GPIO_PAR_SSIH_TXD(x)		(((x) & 0x03) << 4)
+#define GPIO_PAR_SSIH_FS(x)		(((x) & 0x03) << 2)
+#define GPIO_PAR_SSIH_MCLK(x)		((x) & 0x03)
+#define GPIO_PAR_SSIH_RXD_UNMASK	(0x3F)
+#define GPIO_PAR_SSIH_RXD_SSIRXD	(0xC0)
+#define GPIO_PAR_SSIH_RXD_U1RXD		(0x40)
+#define GPIO_PAR_SSIH_TXD_UNMASK	(0xCF)
+#define GPIO_PAR_SSIH_TXD_SSIRXD	(0x30)
+#define GPIO_PAR_SSIH_TXD_U1TXD		(0x10)
+#define GPIO_PAR_SSIH_FS_UNMASK		(0xF3)
+#define GPIO_PAR_SSIH_FS_SSIFS		(0x0C)
+#define GPIO_PAR_SSIH_FS_U1RTS		(0x04)
+#define GPIO_PAR_SSIH_MCLK_UNMASK	(0xFC)
+#define GPIO_PAR_SSIH_MCLK_SSIMCLK	(0x03)
+#define GPIO_PAR_SSIH_MCLK_SSICLKIN	(0x01)
+
+#define GPIO_PAR_SSIL_UNMASK		(0x3F)
+#define GPIO_PAR_SSIL_BCLK		(0xC0)
+#define GPIO_PAR_SSIL_U1CTS		(0x40)
+
+#define GPIO_MSCR_MSCR1(x)		(((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCR2(x)		(((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCR3(x)		(((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCR4(x)		(((x) & 0x07) << 5)
+#define GPIO_MSCR_MSCRn_UNMASK		(0x1F)
+#define GPIO_MSCR_MSCRn_SDR		(0xE0)
+#define GPIO_MSCR_MSCRn_25VDDR		(0x60)
+#define GPIO_MSCR_MSCRn_18VDDR_FULL	(0x20)
+#define GPIO_MSCR_MSCRn_18VDDR_HALF	(0x00)
+
+#define GPIO_MSCR_MSCR5(x)		(((x) & 0x07) << 2)
+#define GPIO_MSCR_MSCR5_UNMASK		(0xE3)
+#define GPIO_MSCR_MSCR5_SDR		(0x1C)
+#define GPIO_MSCR_MSCR5_25VDDR		(0x0C)
+#define GPIO_MSCR_MSCR5_18VDDR_FULL	(0x04)
+#define GPIO_MSCR_MSCR5_18VDDR_HALF	(0x00)
+
+#define GPIO_SRCR_DSPI_UNMASK		(0xFC)
+#define GPIO_SRCR_DSPI(x)		((x) & 0x03)
+#define GPIO_SRCR_I2C_UNMASK		(0xFC)
+#define GPIO_SRCR_I2C(x)		((x) & 0x03)
+#define GPIO_SRCR_IRQ_IRQ0_UNMASK	(0xF3)
+#define GPIO_SRCR_IRQ_IRQ0(x)		(((x) & 0x03) << 2)
+#define GPIO_SRCR_IRQ_IRQ1DBG_UNMASK	(0xFC)
+#define GPIO_SRCR_IRQ_IRQ1DBG(x)	((x) & 0x03)
+#define GPIO_SRCR_SIM_SIMP0_UNMASK	(0xF3)
+#define GPIO_SRCR_SIM_SIMP0(x)		(((x) & 0x03) << 2)
+#define GPIO_SRCR_SIM_SIMP1_UNMASK	(0xFC)
+#define GPIO_SRCR_SIM_SIMP1(x)		((x) & 0x03)
+#define GPIO_SRCR_TIMER_UNMASK		(0xFC)
+#define GPIO_SRCR_TIMER(x)		((x) & 0x03)
+#define GPIO_SRCR_UART2_UNMASK		(0xF3)
+#define GPIO_SRCR_UART2(x)		(((x) & 0x03) << 2)
+#define GPIO_SRCR_UART0_UNMASK		(0xFC)
+#define GPIO_SRCR_UART0(x)		((x) & 0x03)
+#define GPIO_SRCR_SDHC_UNMASK		(0xFC)
+#define GPIO_SRCR_SDHC(x)		((x) & 0x03)
+#define GPIO_SRCR_SSI_UNMASK		(0xFC)
+#define GPIO_SRCR_SSI(x)		((x) & 0x03)
+
+#define SRCR_HIGHEST			(0x03)
+#define SRCR_HIGH			(0x02)
+#define SRCR_LOW			(0x01)
+#define SRCR_LOWEST			(0x00)
+
+#define GPIO_DSCR_FEC_RMIICLK_UNMASK	(0xCF)
+#define GPIO_DSCR_FEC_RMIICLK(x)	(((x) & 0x03) << 4)
+#define GPIO_DSCR_FEC_RMII0_UNMASK	(0xF3)
+#define GPIO_DSCR_FEC_RMII0(x)		(((x) & 0x03) << 2)
+#define GPIO_DSCR_FEC_RMII1_UNMASK	(0xFC)
+#define GPIO_DSCR_FEC_RMII1(x)		((x) & 0x03)
+
+#define DSCR_50PF			(0x03)
+#define DSCR_30PF			(0x02)
+#define DSCR_20PF			(0x01)
+#define DSCR_10PF			(0x00)
+
+#define GPIO_PCRH_DSPI_PCS0_PULLUP_EN	(0x80)
+#define GPIO_PCRH_SIM_VEN1_PULLUP_EN	(0x40)
+#define GPIO_PCRH_SIM_VEN1_PULLUP	(0x20)
+#define GPIO_PCRH_SIM_DATA1_PULLUP_EN	(0x10)
+#define GPIO_PCRH_SIM_DATA1_PULLUP	(0x08)
+#define GPIO_PCRH_SSI_PULLUP_EN		(0x02)
+#define GPIO_PCRH_SSI_PULLUP		(0x01)
+
+#define GPIO_PCRL_SDHC_DATA3_PULLUP_EN	(0x80)
+#define GPIO_PCRL_SDHC_DATA3_PULLUP	(0x40)
+#define GPIO_PCRL_SDHC_DATA2_PULLUP_EN	(0x20)
+#define GPIO_PCRL_SDHC_DATA1_PULLUP_EN	(0x10)
+#define GPIO_PCRL_SDHC_DATA0_PULLUP_EN	(0x08)
+#define GPIO_PCRL_SDHC_CMD_PULLUP_EN	(0x04)
+
+/* *** Phase Locked Loop (PLL) *** */
+#define PLL_PCR_LOC_IRQ			(0x00040000)
+#define PLL_PCR_LOC_RE			(0x00020000)
+#define PLL_PCR_LOC_EN			(0x00010000)
+#define PLL_PCR_LOL_IRQ			(0x00004000)
+#define PLL_PCR_LOL_RE			(0x00002000)
+#define PLL_PCR_LOL_EN			(0x00001000)
+#define PLL_PCR_REFDIV_UNMASK		(0xFFFFF8FF)
+#define PLL_PCR_REFDIV(x)		(((x) & 0x07) << 8)
+#define PLL_PCR_FBDIV_UNMASK		(0xFFFFFFC0)
+#define PLL_PCR_FBDIV(x)		((x) & 0x3F)
+
+#define PLL_PDR_OUTDIV4_UNMASK		(0x0FFF)
+#define PLL_PDR_OUTDIV4(x)		(((x) & 0x0000000F) << 12)
+#define PLL_PDR_OUTDIV3_UNMASK		(0xF0FF)
+#define PLL_PDR_OUTDIV3(x)		(((x) & 0x0000000F) << 8)
+#define PLL_PDR_OUTDIV2_UNMASK		(0xFF0F)
+#define PLL_PDR_OUTDIV2(x)		(((x) & 0x0000000F) << 4)
+#define PLL_PDR_OUTDIV1_UNMASK		(0xFFF0)
+#define PLL_PDR_OUTDIV1(x)		((x) & 0x0000000F)
+#define PLL_PDR_USB(x)			PLL_PDR_OUTDIV4(x)
+#define PLL_PDR_SDRAM(x)		PLL_PDR_OUTDIV3(x)
+#define PLL_PDR_FB(x)			PLL_PDR_OUTDIV2(x)
+#define PLL_PDR_CPU(x)			PLL_PDR_OUTDIV1(x)
+
+#define PLL_PSR_LOCF			(0x00000200)
+#define PLL_PSR_LOC			(0x00000100)
+#define PLL_PSR_LOLF			(0x00000040)
+#define PLL_PSR_LOCKS			(0x00000020)
+#define PLL_PSR_LOCK			(0x00000010)
+#define PLL_PSR_MODE(x)			((x) & 0x07)
+
+/* *** Real Time Clock *** */
+#define RTC_OCEN_OSCBYP			(0x00000010)
+#define RTC_OCEN_CLKEN			(0x00000008)
+
+/* SDRAM */
+#define SDRAMC_SDCR_CKE			(0x40000000)
+#define SDRAMC_SDCR_REF			(0x10000000)
+
+#endif				/* m5301x_h */
diff --git a/arch/m68k/include/asm/m5307.h b/arch/m68k/include/asm/m5307.h
new file mode 100644
index 0000000..f96e6ca
--- /dev/null
+++ b/arch/m68k/include/asm/m5307.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+ *
+ */
+
+#ifndef	mcf5307_h
+#define	mcf5307_h
+
+/*
+ * Size of internal RAM  (RAMBAR)
+ */
+#define INT_RAM_SIZE 4096
+
+/* Bit definitions and macros for SYPCR */
+#define SYPCR_SWTAVAL		0x02
+#define SYPCR_SWTA		0x04
+#define SYPCR_SWT(x)		((x&0x3)<<3)
+#define SYPCR_SWP		0x20
+#define SYPCR_SWRI		0x40
+#define SYPCR_SWE		0x80
+
+/* Bit definitions and macros for CSMR */
+#define CSMR_V			0x01
+#define CSMR_UD			0x02
+#define CSMR_UC			0x04
+#define CSMR_SD			0x08
+#define CSMR_SC			0x10
+#define CSMR_CI			0x20
+#define CSMR_AM			0x40
+#define CSMR_WP			0x100
+
+/* Bit definitions and macros for DACR (SDRAM) */
+#define DACR_PM_CONTINUOUS	0x04
+#define DACR_IP_PRECHG_ALL	0x08
+#define DACR_PORT_SZ_32		0
+#define DACR_PORT_SZ_8		(1<<4)
+#define DACR_PORT_SZ_16		(2<<4)
+#define DACR_IMRS_INIT_CMD	(1<<6)
+#define DACR_CMD_PIN(x)		((x&7)<<8)
+#define DACR_CASL(x)		((x&3)<<12)
+#define DACR_RE			(1<<15)
+
+/* Bit definitions and macros for CSCR */
+#define CSCR_BSTW		0x08
+#define CSCR_BSTR		0x10
+#define CSCR_BEM		0x20
+#define CSCR_PS(x)		((x&0x3)<<6)
+#define CSCR_AA			0x100
+#define CSCR_WS			((x&0xf)<<10)
+
+/* Bit definitions for the ICR family of registers */
+#define	MCFSIM_ICR_AUTOVEC	0x80	/* Auto-vectored intr */
+#define	MCFSIM_ICR_LEVEL0	0x00	/* Level 0 intr */
+#define	MCFSIM_ICR_LEVEL1	0x04	/* Level 1 intr */
+#define	MCFSIM_ICR_LEVEL2	0x08	/* Level 2 intr */
+#define	MCFSIM_ICR_LEVEL3	0x0c	/* Level 3 intr */
+#define	MCFSIM_ICR_LEVEL4	0x10	/* Level 4 intr */
+#define	MCFSIM_ICR_LEVEL5	0x14	/* Level 5 intr */
+#define	MCFSIM_ICR_LEVEL6	0x18	/* Level 6 intr */
+#define	MCFSIM_ICR_LEVEL7	0x1c	/* Level 7 intr */
+
+#define	MCFSIM_ICR_PRI0		0x00	/* Priority 0 intr */
+#define	MCFSIM_ICR_PRI1		0x01	/* Priority 1 intr */
+#define	MCFSIM_ICR_PRI2		0x02	/* Priority 2 intr */
+#define	MCFSIM_ICR_PRI3		0x03	/* Priority 3 intr */
+
+#endif	/* mcf5307_h */
+
diff --git a/arch/m68k/include/asm/m5329.h b/arch/m68k/include/asm/m5329.h
new file mode 100644
index 0000000..4e30ddf
--- /dev/null
+++ b/arch/m68k/include/asm/m5329.h
@@ -0,0 +1,1033 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * mcf5329.h -- Definitions for Freescale Coldfire 5329
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef mcf5329_h
+#define mcf5329_h
+/****************************************************************************/
+
+/*********************************************************************
+* System Control Module (SCM)
+*********************************************************************/
+/* Bit definitions and macros for SCM_MPR */
+#define SCM_MPR_MPROT0(x)		(((x)&0x0F)<<28)
+#define SCM_MPR_MPROT1(x)		(((x)&0x0F)<<24)
+#define SCM_MPR_MPROT2(x)		(((x)&0x0F)<<20)
+#define SCM_MPR_MPROT4(x)		(((x)&0x0F)<<12)
+#define SCM_MPR_MPROT5(x)		(((x)&0x0F)<<8)
+#define SCM_MPR_MPROT6(x)		(((x)&0x0F)<<4)
+#define MPROT_MTR			4
+#define MPROT_MTW			2
+#define MPROT_MPL			1
+
+/* Bit definitions and macros for SCM_BMT */
+#define BMT_BME				(0x08)
+#define BMT_8				(0x07)
+#define BMT_16				(0x06)
+#define BMT_32				(0x05)
+#define BMT_64				(0x04)
+#define BMT_128				(0x03)
+#define BMT_256				(0x02)
+#define BMT_512				(0x01)
+#define BMT_1024			(0x00)
+
+/* Bit definitions and macros for SCM_PACRA */
+#define SCM_PACRA_PACR0(x)		(((x)&0x0F)<<28)
+#define SCM_PACRA_PACR1(x)		(((x)&0x0F)<<24)
+#define SCM_PACRA_PACR2(x)		(((x)&0x0F)<<20)
+#define PACR_SP	4
+#define PACR_WP	2
+#define PACR_TP	1
+
+/* Bit definitions and macros for SCM_PACRB */
+#define SCM_PACRB_PACR8(x)		(((x)&0x0F)<<28)
+#define SCM_PACRB_PACR12(x)		(((x)&0x0F)<<12)
+
+/* Bit definitions and macros for SCM_PACRC */
+#define SCM_PACRC_PACR16(x)		(((x)&0x0F)<<28)
+#define SCM_PACRC_PACR17(x)		(((x)&0x0F)<<24)
+#define SCM_PACRC_PACR18(x)		(((x)&0x0F)<<20)
+#define SCM_PACRC_PACR19(x)		(((x)&0x0F)<<16)
+#define SCM_PACRC_PACR21(x)		(((x)&0x0F)<<8)
+#define SCM_PACRC_PACR22(x)		(((x)&0x0F)<<4)
+#define SCM_PACRC_PACR23(x)		(((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRD */
+#define SCM_PACRD_PACR24(x)		(((x)&0x0F)<<28)
+#define SCM_PACRD_PACR25(x)		(((x)&0x0F)<<24)
+#define SCM_PACRD_PACR26(x)		(((x)&0x0F)<<20)
+#define SCM_PACRD_PACR28(x)		(((x)&0x0F)<<12)
+#define SCM_PACRD_PACR29(x)		(((x)&0x0F)<<8)
+#define SCM_PACRD_PACR30(x)		(((x)&0x0F)<<4)
+#define SCM_PACRD_PACR31(x)		(((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRE */
+#define SCM_PACRE_PACR32(x)		(((x)&0x0F)<<28)
+#define SCM_PACRE_PACR33(x)		(((x)&0x0F)<<24)
+#define SCM_PACRE_PACR34(x)		(((x)&0x0F)<<20)
+#define SCM_PACRE_PACR35(x)		(((x)&0x0F)<<16)
+#define SCM_PACRE_PACR36(x)		(((x)&0x0F)<<12)
+#define SCM_PACRE_PACR37(x)		(((x)&0x0F)<<8)
+#define SCM_PACRE_PACR38(x)		(((x)&0x0F)<<4)
+
+/* Bit definitions and macros for SCM_PACRF */
+#define SCM_PACRF_PACR40(x)		(((x)&0x0F)<<28)
+#define SCM_PACRF_PACR41(x)		(((x)&0x0F)<<24)
+#define SCM_PACRF_PACR42(x)		(((x)&0x0F)<<20)
+#define SCM_PACRF_PACR43(x)		(((x)&0x0F)<<16)
+#define SCM_PACRF_PACR44(x)		(((x)&0x0F)<<12)
+#define SCM_PACRF_PACR45(x)		(((x)&0x0F)<<8)
+#define SCM_PACRF_PACR46(x)		(((x)&0x0F)<<4)
+#define SCM_PACRF_PACR47(x)		(((x)&0x0F)<<0)
+
+/* Bit definitions and macros for SCM_PACRG */
+#define SCM_PACRG_PACR48(x)		(((x)&0x0F)<<28)
+
+/* Bit definitions and macros for SCM_PACRH */
+#define SCM_PACRH_PACR56(x)		(((x)&0x0F)<<28)
+#define SCM_PACRH_PACR57(x)		(((x)&0x0F)<<24)
+#define SCM_PACRH_PACR58(x)		(((x)&0x0F)<<20)
+
+/* PACRn Assignments */
+#define PACR0(x)			SCM_PACRA_PACR0(x)
+#define PACR1(x)			SCM_PACRA_PACR1(x)
+#define PACR2(x)			SCM_PACRA_PACR2(x)
+#define PACR8(x)			SCM_PACRB_PACR8(x)
+#define PACR12(x)			SCM_PACRB_PACR12(x)
+#define PACR16(x)			SCM_PACRC_PACR16(x)
+#define PACR17(x)			SCM_PACRC_PACR17(x)
+#define PACR18(x)			SCM_PACRC_PACR18(x)
+#define PACR19(x)			SCM_PACRC_PACR19(x)
+#define PACR21(x)			SCM_PACRC_PACR21(x)
+#define PACR22(x)			SCM_PACRC_PACR22(x)
+#define PACR23(x)			SCM_PACRC_PACR23(x)
+#define PACR24(x)			SCM_PACRD_PACR24(x)
+#define PACR25(x)			SCM_PACRD_PACR25(x)
+#define PACR26(x)			SCM_PACRD_PACR26(x)
+#define PACR28(x)			SCM_PACRD_PACR28(x)
+#define PACR29(x)			SCM_PACRD_PACR29(x)
+#define PACR30(x)			SCM_PACRD_PACR30(x)
+#define PACR31(x)			SCM_PACRD_PACR31(x)
+#define PACR32(x)			SCM_PACRE_PACR32(x)
+#define PACR33(x)			SCM_PACRE_PACR33(x)
+#define PACR34(x)			SCM_PACRE_PACR34(x)
+#define PACR35(x)			SCM_PACRE_PACR35(x)
+#define PACR36(x)			SCM_PACRE_PACR36(x)
+#define PACR37(x)			SCM_PACRE_PACR37(x)
+#define PACR38(x)			SCM_PACRE_PACR38(x)
+#define PACR40(x)			SCM_PACRF_PACR40(x)
+#define PACR41(x)			SCM_PACRF_PACR41(x)
+#define PACR42(x)			SCM_PACRF_PACR42(x)
+#define PACR43(x)			SCM_PACRF_PACR43(x)
+#define PACR44(x)			SCM_PACRF_PACR44(x)
+#define PACR45(x)			SCM_PACRF_PACR45(x)
+#define PACR46(x)			SCM_PACRF_PACR46(x)
+#define PACR47(x)			SCM_PACRF_PACR47(x)
+#define PACR48(x)			SCM_PACRG_PACR48(x)
+#define PACR56(x)			SCM_PACRH_PACR56(x)
+#define PACR57(x)			SCM_PACRH_PACR57(x)
+#define PACR58(x)			SCM_PACRH_PACR58(x)
+
+/* Bit definitions and macros for SCM_CWCR */
+#define CWCR_RO				(0x8000)
+#define CWCR_CWR_WH			(0x0100)
+#define CWCR_CWE			(0x0080)
+#define CWRI_WINDOW			(0x0060)
+#define CWRI_RESET			(0x0040)
+#define CWRI_INT_RESET			(0x0020)
+#define CWRI_INT			(0x0000)
+#define CWCR_CWT(x)			(((x)&0x001F))
+
+/* Bit definitions and macros for SCM_ISR */
+#define SCMISR_CFEI			(0x02)
+#define SCMISR_CWIC			(0x01)
+
+/* Bit definitions and macros for SCM_BCR */
+#define BCR_GBR				(0x00000200)
+#define BCR_GBW				(0x00000100)
+#define BCR_S7				(0x00000080)
+#define BCR_S6				(0x00000040)
+#define BCR_S4				(0x00000010)
+#define BCR_S1				(0x00000002)
+
+/* Bit definitions and macros for SCM_CFIER */
+#define CFIER_ECFEI			(0x01)
+
+/* Bit definitions and macros for SCM_CFLOC */
+#define CFLOC_LOC			(0x80)
+
+/* Bit definitions and macros for SCM_CFATR */
+#define CFATR_WRITE			(0x80)
+#define CFATR_SZ32			(0x20)
+#define CFATR_SZ16			(0x10)
+#define CFATR_SZ08			(0x00)
+#define CFATR_CACHE			(0x08)
+#define CFATR_MODE			(0x02)
+#define CFATR_TYPE			(0x01)
+
+/*********************************************************************
+* Reset Controller Module (RCM)
+*********************************************************************/
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT		(0x40)
+#define RCM_RCR_SOFTRST			(0x80)
+
+/* Bit definitions and macros for RSR */
+#define RCM_RSR_LOL			(0x01)
+#define RCM_RSR_WDR_CORE		(0x02)
+#define RCM_RSR_EXT			(0x04)
+#define RCM_RSR_POR			(0x08)
+#define RCM_RSR_SOFT			(0x20)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INTC0_EPORT			INTC_IPRL_INT1
+
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_EDMA_00			(8)
+#define INT0_LO_EDMA_01			(9)
+#define INT0_LO_EDMA_02			(10)
+#define INT0_LO_EDMA_03			(11)
+#define INT0_LO_EDMA_04			(12)
+#define INT0_LO_EDMA_05			(13)
+#define INT0_LO_EDMA_06			(14)
+#define INT0_LO_EDMA_07			(15)
+#define INT0_LO_EDMA_08			(16)
+#define INT0_LO_EDMA_09			(17)
+#define INT0_LO_EDMA_10			(18)
+#define INT0_LO_EDMA_11			(19)
+#define INT0_LO_EDMA_12			(20)
+#define INT0_LO_EDMA_13			(21)
+#define INT0_LO_EDMA_14			(22)
+#define INT0_LO_EDMA_15			(23)
+#define INT0_LO_EDMA_ERR		(24)
+#define INT0_LO_SCM			(25)
+#define INT0_LO_UART0			(26)
+#define INT0_LO_UART1			(27)
+#define INT0_LO_UART2			(28)
+#define INT0_LO_RSVD1			(29)
+#define INT0_LO_I2C			(30)
+#define INT0_LO_QSPI			(31)
+#define INT0_HI_DTMR0			(32)
+#define INT0_HI_DTMR1			(33)
+#define INT0_HI_DTMR2			(34)
+#define INT0_HI_DTMR3			(35)
+#define INT0_HI_FEC_TXF			(36)
+#define INT0_HI_FEC_TXB			(37)
+#define INT0_HI_FEC_UN			(38)
+#define INT0_HI_FEC_RL			(39)
+#define INT0_HI_FEC_RXF			(40)
+#define INT0_HI_FEC_RXB			(41)
+#define INT0_HI_FEC_MII			(42)
+#define INT0_HI_FEC_LC			(43)
+#define INT0_HI_FEC_HBERR		(44)
+#define INT0_HI_FEC_GRA			(45)
+#define INT0_HI_FEC_EBERR		(46)
+#define INT0_HI_FEC_BABT		(47)
+#define INT0_HI_FEC_BABR		(48)
+/* 49 - 61 Reserved */
+#define INT0_HI_SCM			(62)
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+/* Bit definitions and macros for WTM_WCR */
+#define WTM_WCR_WAIT			(0x0008)
+#define WTM_WCR_DOZE			(0x0004)
+#define WTM_WCR_HALTED			(0x0002)
+#define WTM_WCR_EN			(0x0001)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+/* Bit definitions and macros for CCM_CCR */
+#define CCM_CCR_CSC(x)			(((x)&0x0003)<<8|0x0001)
+#define CCM_CCR_LIMP			(0x0041)
+#define CCM_CCR_LOAD			(0x0021)
+#define CCM_CCR_BOOTPS(x)		(((x)&0x0003)<<3|0x0001)
+#define CCM_CCR_OSC_MODE		(0x0005)
+#define CCM_CCR_PLL_MODE		(0x0003)
+#define CCM_CCR_RESERVED		(0x0001)
+
+/* Bit definitions and macros for CCM_RCON */
+#define CCM_RCON_CSC(x)			(((x)&0x0003)<<8|0x0001)
+#define CCM_RCON_LIMP			(0x0041)
+#define CCM_RCON_LOAD			(0x0021)
+#define CCM_RCON_BOOTPS(x)		(((x)&0x0003)<<3|0x0001)
+#define CCM_RCON_OSC_MODE		(0x0005)
+#define CCM_RCON_PLL_MODE		(0x0003)
+#define CCM_RCON_RESERVED		(0x0001)
+
+/* Bit definitions and macros for CCM_CIR */
+#define CCM_CIR_PIN(x)			(((x)&0x03FF)<<6)
+#define CCM_CIR_PRN(x)			((x)&0x003F)
+
+/* Bit definitions and macros for CCM_MISCCR */
+#define CCM_MISCCR_PLL_LOCK		(0x2000)
+#define CCM_MISCCR_LIMP			(0x1000)
+#define CCM_MISCCR_LCD_CHEN		(0x0100)
+#define CCM_MISCCR_SSI_PUE		(0x0080)
+#define CCM_MISCCR_SSI_PUS		(0x0040)
+#define CCM_MISCCR_TIM_DMA		(0x0020)
+#define CCM_MISCCR_SSI_SRC		(0x0010)
+#define CCM_MISCCR_USBDIV		(0x0002)
+#define CCM_MISCCR_USBSRC		(0x0001)
+
+/* Bit definitions and macros for CCM_CDR */
+#define CCM_CDR_LPDIV(x)		(((x)&0x000F)<<8)
+#define CCM_CDR_SSIDIV(x)		((x)&0x000F)
+
+/* Bit definitions and macros for CCM_UHCSR */
+#define CCM_UHCSR_PORTIND(x)		(((x)&0x0003)<<14)
+#define CCM_UHCSR_WKUP			(0x0004)
+#define CCM_UHCSR_UHMIE			(0x0002)
+#define CCM_UHCSR_XPDE			(0x0001)
+
+/* Bit definitions and macros for CCM_UOCSR */
+#define CCM_UOCSR_PORTIND(x)		(((x)&0x0003)<<14)
+#define CCM_UOCSR_DPPD			(0x2000)
+#define CCM_UOCSR_DMPD			(0x1000)
+#define CCM_UOCSR_DRV_VBUS		(0x0800)
+#define CCM_UOCSR_CRG_VBUS		(0x0400)
+#define CCM_UOCSR_DCR_VBUS		(0x0200)
+#define CCM_UOCSR_DPPU			(0x0100)
+#define CCM_UOCSR_AVLD			(0x0080)
+#define CCM_UOCSR_BVLD			(0x0040)
+#define CCM_UOCSR_VVLD			(0x0020)
+#define CCM_UOCSR_SEND			(0x0010)
+#define CCM_UOCSR_PWRFLT		(0x0008)
+#define CCM_UOCSR_WKUP			(0x0004)
+#define CCM_UOCSR_UOMIE			(0x0002)
+#define CCM_UOCSR_XPDE			(0x0001)
+
+/* not done yet */
+/*********************************************************************
+* General Purpose I/O (GPIO)
+*********************************************************************/
+/* Bit definitions and macros for GPIO_PODR_FECH_L */
+#define GPIO_PODR_FECH_L7		(0x80)
+#define GPIO_PODR_FECH_L6		(0x40)
+#define GPIO_PODR_FECH_L5		(0x20)
+#define GPIO_PODR_FECH_L4		(0x10)
+#define GPIO_PODR_FECH_L3		(0x08)
+#define GPIO_PODR_FECH_L2		(0x04)
+#define GPIO_PODR_FECH_L1		(0x02)
+#define GPIO_PODR_FECH_L0		(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_SSI */
+#define GPIO_PODR_SSI_4			(0x10)
+#define GPIO_PODR_SSI_3			(0x08)
+#define GPIO_PODR_SSI_2			(0x04)
+#define GPIO_PODR_SSI_1			(0x02)
+#define GPIO_PODR_SSI_0			(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_BUSCTL */
+#define GPIO_PODR_BUSCTL_3		(0x08)
+#define GPIO_PODR_BUSCTL_2		(0x04)
+#define GPIO_PODR_BUSCTL_1		(0x02)
+#define GPIO_PODR_BUSCTL_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_BE */
+#define GPIO_PODR_BE_3			(0x08)
+#define GPIO_PODR_BE_2			(0x04)
+#define GPIO_PODR_BE_1			(0x02)
+#define GPIO_PODR_BE_0			(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_CS */
+#define GPIO_PODR_CS_5			(0x20)
+#define GPIO_PODR_CS_4			(0x10)
+#define GPIO_PODR_CS_3			(0x08)
+#define GPIO_PODR_CS_2			(0x04)
+#define GPIO_PODR_CS_1			(0x02)
+
+/* Bit definitions and macros for GPIO_PODR_PWM */
+#define GPIO_PODR_PWM_5			(0x20)
+#define GPIO_PODR_PWM_4			(0x10)
+#define GPIO_PODR_PWM_3			(0x08)
+#define GPIO_PODR_PWM_2			(0x04)
+
+/* Bit definitions and macros for GPIO_PODR_FECI2C */
+#define GPIO_PODR_FECI2C_3		(0x08)
+#define GPIO_PODR_FECI2C_2		(0x04)
+#define GPIO_PODR_FECI2C_1		(0x02)
+#define GPIO_PODR_FECI2C_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_UART */
+#define GPIO_PODR_UART_7		(0x80)
+#define GPIO_PODR_UART_6		(0x40)
+#define GPIO_PODR_UART_5		(0x20)
+#define GPIO_PODR_UART_4		(0x10)
+#define GPIO_PODR_UART_3		(0x08)
+#define GPIO_PODR_UART_2		(0x04)
+#define GPIO_PODR_UART_1		(0x02)
+#define GPIO_PODR_UART_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_QSPI */
+#define GPIO_PODR_QSPI_5		(0x20)
+#define GPIO_PODR_QSPI_4		(0x10)
+#define GPIO_PODR_QSPI_3		(0x08)
+#define GPIO_PODR_QSPI_2		(0x04)
+#define GPIO_PODR_QSPI_1		(0x02)
+#define GPIO_PODR_QSPI_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_TIMER */
+#define GPIO_PODR_TIMER_3		(0x08)
+#define GPIO_PODR_TIMER_2		(0x04)
+#define GPIO_PODR_TIMER_1		(0x02)
+#define GPIO_PODR_TIMER_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAH */
+#define GPIO_PODR_LCDDATAH_1		(0x02)
+#define GPIO_PODR_LCDDATAH_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAM */
+#define GPIO_PODR_LCDDATAM_7		(0x80)
+#define GPIO_PODR_LCDDATAM_6		(0x40)
+#define GPIO_PODR_LCDDATAM_5		(0x20)
+#define GPIO_PODR_LCDDATAM_4		(0x10)
+#define GPIO_PODR_LCDDATAM_3		(0x08)
+#define GPIO_PODR_LCDDATAM_2		(0x04)
+#define GPIO_PODR_LCDDATAM_1		(0x02)
+#define GPIO_PODR_LCDDATAM_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDDATAL */
+#define GPIO_PODR_LCDDATAL_7		(0x80)
+#define GPIO_PODR_LCDDATAL_6		(0x40)
+#define GPIO_PODR_LCDDATAL_5		(0x20)
+#define GPIO_PODR_LCDDATAL_4		(0x10)
+#define GPIO_PODR_LCDDATAL_3		(0x08)
+#define GPIO_PODR_LCDDATAL_2		(0x04)
+#define GPIO_PODR_LCDDATAL_1		(0x02)
+#define GPIO_PODR_LCDDATAL_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDCTLH */
+#define GPIO_PODR_LCDCTLH_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PODR_LCDCTLL */
+#define GPIO_PODR_LCDCTLL_7		(0x80)
+#define GPIO_PODR_LCDCTLL_6		(0x40)
+#define GPIO_PODR_LCDCTLL_5		(0x20)
+#define GPIO_PODR_LCDCTLL_4		(0x10)
+#define GPIO_PODR_LCDCTLL_3		(0x08)
+#define GPIO_PODR_LCDCTLL_2		(0x04)
+#define GPIO_PODR_LCDCTLL_1		(0x02)
+#define GPIO_PODR_LCDCTLL_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_FECH */
+#define GPIO_PDDR_FECH_L7		(0x80)
+#define GPIO_PDDR_FECH_L6		(0x40)
+#define GPIO_PDDR_FECH_L5		(0x20)
+#define GPIO_PDDR_FECH_L4		(0x10)
+#define GPIO_PDDR_FECH_L3		(0x08)
+#define GPIO_PDDR_FECH_L2		(0x04)
+#define GPIO_PDDR_FECH_L1		(0x02)
+#define GPIO_PDDR_FECH_L0		(0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_SSI */
+#define GPIO_PDDR_SSI_4			(0x10)
+#define GPIO_PDDR_SSI_3			(0x08)
+#define GPIO_PDDR_SSI_2			(0x04)
+#define GPIO_PDDR_SSI_1			(0x02)
+#define GPIO_PDDR_SSI_0			(0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_BUSCTL */
+#define GPIO_PDDR_BUSCTL_3		(0x08)
+#define GPIO_PDDR_BUSCTL_2		(0x04)
+#define GPIO_PDDR_BUSCTL_1		(0x02)
+#define GPIO_PDDR_BUSCTL_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_BE */
+#define GPIO_PDDR_BE_3			(0x08)
+#define GPIO_PDDR_BE_2			(0x04)
+#define GPIO_PDDR_BE_1			(0x02)
+#define GPIO_PDDR_BE_0			(0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_CS */
+#define GPIO_PDDR_CS_1			(0x02)
+#define GPIO_PDDR_CS_2			(0x04)
+#define GPIO_PDDR_CS_3			(0x08)
+#define GPIO_PDDR_CS_4			(0x10)
+#define GPIO_PDDR_CS_5			(0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_PWM */
+#define GPIO_PDDR_PWM_2			(0x04)
+#define GPIO_PDDR_PWM_3			(0x08)
+#define GPIO_PDDR_PWM_4			(0x10)
+#define GPIO_PDDR_PWM_5			(0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_FECI2C */
+#define GPIO_PDDR_FECI2C_0		(0x01)
+#define GPIO_PDDR_FECI2C_1		(0x02)
+#define GPIO_PDDR_FECI2C_2		(0x04)
+#define GPIO_PDDR_FECI2C_3		(0x08)
+
+/* Bit definitions and macros for GPIO_PDDR_UART */
+#define GPIO_PDDR_UART_0		(0x01)
+#define GPIO_PDDR_UART_1		(0x02)
+#define GPIO_PDDR_UART_2		(0x04)
+#define GPIO_PDDR_UART_3		(0x08)
+#define GPIO_PDDR_UART_4		(0x10)
+#define GPIO_PDDR_UART_5		(0x20)
+#define GPIO_PDDR_UART_6		(0x40)
+#define GPIO_PDDR_UART_7		(0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_QSPI */
+#define GPIO_PDDR_QSPI_0		(0x01)
+#define GPIO_PDDR_QSPI_1		(0x02)
+#define GPIO_PDDR_QSPI_2		(0x04)
+#define GPIO_PDDR_QSPI_3		(0x08)
+#define GPIO_PDDR_QSPI_4		(0x10)
+#define GPIO_PDDR_QSPI_5		(0x20)
+
+/* Bit definitions and macros for GPIO_PDDR_TIMER */
+#define GPIO_PDDR_TIMER_0		(0x01)
+#define GPIO_PDDR_TIMER_1		(0x02)
+#define GPIO_PDDR_TIMER_2		(0x04)
+#define GPIO_PDDR_TIMER_3		(0x08)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAH */
+#define GPIO_PDDR_LCDDATAH_0		(0x01)
+#define GPIO_PDDR_LCDDATAH_1		(0x02)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAM */
+#define GPIO_PDDR_LCDDATAM_0		(0x01)
+#define GPIO_PDDR_LCDDATAM_1		(0x02)
+#define GPIO_PDDR_LCDDATAM_2		(0x04)
+#define GPIO_PDDR_LCDDATAM_3		(0x08)
+#define GPIO_PDDR_LCDDATAM_4		(0x10)
+#define GPIO_PDDR_LCDDATAM_5		(0x20)
+#define GPIO_PDDR_LCDDATAM_6		(0x40)
+#define GPIO_PDDR_LCDDATAM_7		(0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDDATAL */
+#define GPIO_PDDR_LCDDATAL_0		(0x01)
+#define GPIO_PDDR_LCDDATAL_1		(0x02)
+#define GPIO_PDDR_LCDDATAL_2		(0x04)
+#define GPIO_PDDR_LCDDATAL_3		(0x08)
+#define GPIO_PDDR_LCDDATAL_4		(0x10)
+#define GPIO_PDDR_LCDDATAL_5		(0x20)
+#define GPIO_PDDR_LCDDATAL_6		(0x40)
+#define GPIO_PDDR_LCDDATAL_7		(0x80)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDCTLH */
+#define GPIO_PDDR_LCDCTLH_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PDDR_LCDCTLL */
+#define GPIO_PDDR_LCDCTLL_0		(0x01)
+#define GPIO_PDDR_LCDCTLL_1		(0x02)
+#define GPIO_PDDR_LCDCTLL_2		(0x04)
+#define GPIO_PDDR_LCDCTLL_3		(0x08)
+#define GPIO_PDDR_LCDCTLL_4		(0x10)
+#define GPIO_PDDR_LCDCTLL_5		(0x20)
+#define GPIO_PDDR_LCDCTLL_6		(0x40)
+#define GPIO_PDDR_LCDCTLL_7		(0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_FECH */
+#define GPIO_PPDSDR_FECH_L0		(0x01)
+#define GPIO_PPDSDR_FECH_L1		(0x02)
+#define GPIO_PPDSDR_FECH_L2		(0x04)
+#define GPIO_PPDSDR_FECH_L3		(0x08)
+#define GPIO_PPDSDR_FECH_L4		(0x10)
+#define GPIO_PPDSDR_FECH_L5		(0x20)
+#define GPIO_PPDSDR_FECH_L6		(0x40)
+#define GPIO_PPDSDR_FECH_L7		(0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_SSI */
+#define GPIO_PPDSDR_SSI_0		(0x01)
+#define GPIO_PPDSDR_SSI_1		(0x02)
+#define GPIO_PPDSDR_SSI_2		(0x04)
+#define GPIO_PPDSDR_SSI_3		(0x08)
+#define GPIO_PPDSDR_SSI_4		(0x10)
+
+/* Bit definitions and macros for GPIO_PPDSDR_BUSCTL */
+#define GPIO_PPDSDR_BUSCTL_0		(0x01)
+#define GPIO_PPDSDR_BUSCTL_1		(0x02)
+#define GPIO_PPDSDR_BUSCTL_2		(0x04)
+#define GPIO_PPDSDR_BUSCTL_3		(0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_BE */
+#define GPIO_PPDSDR_BE_0		(0x01)
+#define GPIO_PPDSDR_BE_1		(0x02)
+#define GPIO_PPDSDR_BE_2		(0x04)
+#define GPIO_PPDSDR_BE_3		(0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_CS */
+#define GPIO_PPDSDR_CS_1		(0x02)
+#define GPIO_PPDSDR_CS_2		(0x04)
+#define GPIO_PPDSDR_CS_3		(0x08)
+#define GPIO_PPDSDR_CS_4		(0x10)
+#define GPIO_PPDSDR_CS_5		(0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_PWM */
+#define GPIO_PPDSDR_PWM_2		(0x04)
+#define GPIO_PPDSDR_PWM_3		(0x08)
+#define GPIO_PPDSDR_PWM_4		(0x10)
+#define GPIO_PPDSDR_PWM_5		(0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_FECI2C */
+#define GPIO_PPDSDR_FECI2C_0		(0x01)
+#define GPIO_PPDSDR_FECI2C_1		(0x02)
+#define GPIO_PPDSDR_FECI2C_2		(0x04)
+#define GPIO_PPDSDR_FECI2C_3		(0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_UART */
+#define GPIO_PPDSDR_UART_0		(0x01)
+#define GPIO_PPDSDR_UART_1		(0x02)
+#define GPIO_PPDSDR_UART_2		(0x04)
+#define GPIO_PPDSDR_UART_3		(0x08)
+#define GPIO_PPDSDR_UART_4		(0x10)
+#define GPIO_PPDSDR_UART_5		(0x20)
+#define GPIO_PPDSDR_UART_6		(0x40)
+#define GPIO_PPDSDR_UART_7		(0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_QSPI */
+#define GPIO_PPDSDR_QSPI_0		(0x01)
+#define GPIO_PPDSDR_QSPI_1		(0x02)
+#define GPIO_PPDSDR_QSPI_2		(0x04)
+#define GPIO_PPDSDR_QSPI_3		(0x08)
+#define GPIO_PPDSDR_QSPI_4		(0x10)
+#define GPIO_PPDSDR_QSPI_5		(0x20)
+
+/* Bit definitions and macros for GPIO_PPDSDR_TIMER */
+#define GPIO_PPDSDR_TIMER_0		(0x01)
+#define GPIO_PPDSDR_TIMER_1		(0x02)
+#define GPIO_PPDSDR_TIMER_2		(0x04)
+#define GPIO_PPDSDR_TIMER_3		(0x08)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAH */
+#define GPIO_PPDSDR_LCDDATAH_0		(0x01)
+#define GPIO_PPDSDR_LCDDATAH_1		(0x02)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAM */
+#define GPIO_PPDSDR_LCDDATAM_0		(0x01)
+#define GPIO_PPDSDR_LCDDATAM_1		(0x02)
+#define GPIO_PPDSDR_LCDDATAM_2		(0x04)
+#define GPIO_PPDSDR_LCDDATAM_3		(0x08)
+#define GPIO_PPDSDR_LCDDATAM_4		(0x10)
+#define GPIO_PPDSDR_LCDDATAM_5		(0x20)
+#define GPIO_PPDSDR_LCDDATAM_6		(0x40)
+#define GPIO_PPDSDR_LCDDATAM_7		(0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDDATAL */
+#define GPIO_PPDSDR_LCDDATAL_0		(0x01)
+#define GPIO_PPDSDR_LCDDATAL_1		(0x02)
+#define GPIO_PPDSDR_LCDDATAL_2		(0x04)
+#define GPIO_PPDSDR_LCDDATAL_3		(0x08)
+#define GPIO_PPDSDR_LCDDATAL_4		(0x10)
+#define GPIO_PPDSDR_LCDDATAL_5		(0x20)
+#define GPIO_PPDSDR_LCDDATAL_6		(0x40)
+#define GPIO_PPDSDR_LCDDATAL_7		(0x80)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLH */
+#define GPIO_PPDSDR_LCDCTLH_0		(0x01)
+
+/* Bit definitions and macros for GPIO_PPDSDR_LCDCTLL */
+#define GPIO_PPDSDR_LCDCTLL_0		(0x01)
+#define GPIO_PPDSDR_LCDCTLL_1		(0x02)
+#define GPIO_PPDSDR_LCDCTLL_2		(0x04)
+#define GPIO_PPDSDR_LCDCTLL_3		(0x08)
+#define GPIO_PPDSDR_LCDCTLL_4		(0x10)
+#define GPIO_PPDSDR_LCDCTLL_5		(0x20)
+#define GPIO_PPDSDR_LCDCTLL_6		(0x40)
+#define GPIO_PPDSDR_LCDCTLL_7		(0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_FECH */
+#define GPIO_PCLRR_FECH_L0		(0x01)
+#define GPIO_PCLRR_FECH_L1		(0x02)
+#define GPIO_PCLRR_FECH_L2		(0x04)
+#define GPIO_PCLRR_FECH_L3		(0x08)
+#define GPIO_PCLRR_FECH_L4		(0x10)
+#define GPIO_PCLRR_FECH_L5		(0x20)
+#define GPIO_PCLRR_FECH_L6		(0x40)
+#define GPIO_PCLRR_FECH_L7		(0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_SSI */
+#define GPIO_PCLRR_SSI_0		(0x01)
+#define GPIO_PCLRR_SSI_1		(0x02)
+#define GPIO_PCLRR_SSI_2		(0x04)
+#define GPIO_PCLRR_SSI_3		(0x08)
+#define GPIO_PCLRR_SSI_4		(0x10)
+
+/* Bit definitions and macros for GPIO_PCLRR_BUSCTL */
+#define GPIO_PCLRR_BUSCTL_L0		(0x01)
+#define GPIO_PCLRR_BUSCTL_L1		(0x02)
+#define GPIO_PCLRR_BUSCTL_L2		(0x04)
+#define GPIO_PCLRR_BUSCTL_L3		(0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_BE */
+#define GPIO_PCLRR_BE_0			(0x01)
+#define GPIO_PCLRR_BE_1			(0x02)
+#define GPIO_PCLRR_BE_2			(0x04)
+#define GPIO_PCLRR_BE_3			(0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_CS */
+#define GPIO_PCLRR_CS_1			(0x02)
+#define GPIO_PCLRR_CS_2			(0x04)
+#define GPIO_PCLRR_CS_3			(0x08)
+#define GPIO_PCLRR_CS_4			(0x10)
+#define GPIO_PCLRR_CS_5			(0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_PWM */
+#define GPIO_PCLRR_PWM_2		(0x04)
+#define GPIO_PCLRR_PWM_3		(0x08)
+#define GPIO_PCLRR_PWM_4		(0x10)
+#define GPIO_PCLRR_PWM_5		(0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_FECI2C */
+#define GPIO_PCLRR_FECI2C_0		(0x01)
+#define GPIO_PCLRR_FECI2C_1		(0x02)
+#define GPIO_PCLRR_FECI2C_2		(0x04)
+#define GPIO_PCLRR_FECI2C_3		(0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_UART */
+#define GPIO_PCLRR_UART0		(0x01)
+#define GPIO_PCLRR_UART1		(0x02)
+#define GPIO_PCLRR_UART2		(0x04)
+#define GPIO_PCLRR_UART3		(0x08)
+#define GPIO_PCLRR_UART4		(0x10)
+#define GPIO_PCLRR_UART5		(0x20)
+#define GPIO_PCLRR_UART6		(0x40)
+#define GPIO_PCLRR_UART7		(0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_QSPI */
+#define GPIO_PCLRR_QSPI0		(0x01)
+#define GPIO_PCLRR_QSPI1		(0x02)
+#define GPIO_PCLRR_QSPI2		(0x04)
+#define GPIO_PCLRR_QSPI3		(0x08)
+#define GPIO_PCLRR_QSPI4		(0x10)
+#define GPIO_PCLRR_QSPI5		(0x20)
+
+/* Bit definitions and macros for GPIO_PCLRR_TIMER */
+#define GPIO_PCLRR_TIMER0		(0x01)
+#define GPIO_PCLRR_TIMER1		(0x02)
+#define GPIO_PCLRR_TIMER2		(0x04)
+#define GPIO_PCLRR_TIMER3		(0x08)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAH */
+#define GPIO_PCLRR_LCDDATAH0		(0x01)
+#define GPIO_PCLRR_LCDDATAH1		(0x02)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAM */
+#define GPIO_PCLRR_LCDDATAM0		(0x01)
+#define GPIO_PCLRR_LCDDATAM1		(0x02)
+#define GPIO_PCLRR_LCDDATAM2		(0x04)
+#define GPIO_PCLRR_LCDDATAM3		(0x08)
+#define GPIO_PCLRR_LCDDATAM4		(0x10)
+#define GPIO_PCLRR_LCDDATAM5		(0x20)
+#define GPIO_PCLRR_LCDDATAM6		(0x40)
+#define GPIO_PCLRR_LCDDATAM7		(0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDDATAL */
+#define GPIO_PCLRR_LCDDATAL0		(0x01)
+#define GPIO_PCLRR_LCDDATAL1		(0x02)
+#define GPIO_PCLRR_LCDDATAL2		(0x04)
+#define GPIO_PCLRR_LCDDATAL3		(0x08)
+#define GPIO_PCLRR_LCDDATAL4		(0x10)
+#define GPIO_PCLRR_LCDDATAL5		(0x20)
+#define GPIO_PCLRR_LCDDATAL6		(0x40)
+#define GPIO_PCLRR_LCDDATAL7		(0x80)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDCTLH */
+#define GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0		(0x01)
+
+/* Bit definitions and macros for GPIO_PCLRR_LCDCTLL */
+#define GPIO_PCLRR_LCDCTLL0		(0x01)
+#define GPIO_PCLRR_LCDCTLL1		(0x02)
+#define GPIO_PCLRR_LCDCTLL2		(0x04)
+#define GPIO_PCLRR_LCDCTLL3		(0x08)
+#define GPIO_PCLRR_LCDCTLL4		(0x10)
+#define GPIO_PCLRR_LCDCTLL5		(0x20)
+#define GPIO_PCLRR_LCDCTLL6		(0x40)
+#define GPIO_PCLRR_LCDCTLL7		(0x80)
+
+/* Bit definitions and macros for GPIO_PAR_FEC */
+#ifdef CONFIG_M5329
+#define GPIO_PAR_FEC_MII(x)		(((x)&0x03)<<0)
+#define GPIO_PAR_FEC_7W(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_FEC_7W_GPIO		(0x00)
+#define GPIO_PAR_FEC_7W_URTS1		(0x04)
+#define GPIO_PAR_FEC_7W_FEC		(0x0C)
+#define GPIO_PAR_FEC_MII_GPIO		(0x00)
+#define GPIO_PAR_FEC_MII_UART		(0x01)
+#define GPIO_PAR_FEC_MII_FEC		(0x03)
+#else
+#define GPIO_PAR_FEC_7W_FEC		(0x08)
+#define GPIO_PAR_FEC_MII_FEC		(0x02)
+#endif
+
+/* Bit definitions and macros for GPIO_PAR_PWM */
+#define GPIO_PAR_PWM1(x)		(((x)&0x03)<<0)
+#define GPIO_PAR_PWM3(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_PWM5			(0x10)
+#define GPIO_PAR_PWM7			(0x20)
+
+/* Bit definitions and macros for GPIO_PAR_BUSCTL */
+#define GPIO_PAR_BUSCTL_TS(x)		(((x)&0x03)<<3)
+#define GPIO_PAR_BUSCTL_RWB		(0x20)
+#define GPIO_PAR_BUSCTL_TA		(0x40)
+#define GPIO_PAR_BUSCTL_OE		(0x80)
+#define GPIO_PAR_BUSCTL_OE_GPIO		(0x00)
+#define GPIO_PAR_BUSCTL_OE_OE		(0x80)
+#define GPIO_PAR_BUSCTL_TA_GPIO		(0x00)
+#define GPIO_PAR_BUSCTL_TA_TA		(0x40)
+#define GPIO_PAR_BUSCTL_RWB_GPIO	(0x00)
+#define GPIO_PAR_BUSCTL_RWB_RWB		(0x20)
+#define GPIO_PAR_BUSCTL_TS_GPIO		(0x00)
+#define GPIO_PAR_BUSCTL_TS_DACK0	(0x10)
+#define GPIO_PAR_BUSCTL_TS_TS		(0x18)
+
+/* Bit definitions and macros for GPIO_PAR_FECI2C */
+#define GPIO_PAR_FECI2C_SDA(x)		(((x)&0x03)<<0)
+#define GPIO_PAR_FECI2C_SCL(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_FECI2C_MDIO(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_FECI2C_MDC(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_FECI2C_MDC_GPIO	(0x00)
+#define GPIO_PAR_FECI2C_MDC_UTXD2	(0x40)
+#define GPIO_PAR_FECI2C_MDC_SCL		(0x80)
+#define GPIO_PAR_FECI2C_MDC_EMDC	(0xC0)
+#define GPIO_PAR_FECI2C_MDIO_GPIO	(0x00)
+#define GPIO_PAR_FECI2C_MDIO_URXD2	(0x10)
+#define GPIO_PAR_FECI2C_MDIO_SDA	(0x20)
+#define GPIO_PAR_FECI2C_MDIO_EMDIO	(0x30)
+#define GPIO_PAR_FECI2C_SCL_GPIO	(0x00)
+#define GPIO_PAR_FECI2C_SCL_UTXD2	(0x04)
+#define GPIO_PAR_FECI2C_SCL_SCL		(0x0C)
+#define GPIO_PAR_FECI2C_SDA_GPIO	(0x00)
+#define GPIO_PAR_FECI2C_SDA_URXD2	(0x02)
+#define GPIO_PAR_FECI2C_SDA_SDA		(0x03)
+
+/* Bit definitions and macros for GPIO_PAR_BE */
+#define GPIO_PAR_BE0			(0x01)
+#define GPIO_PAR_BE1			(0x02)
+#define GPIO_PAR_BE2			(0x04)
+#define GPIO_PAR_BE3			(0x08)
+
+/* Bit definitions and macros for GPIO_PAR_CS */
+#define GPIO_PAR_CS1			(0x02)
+#define GPIO_PAR_CS2			(0x04)
+#define GPIO_PAR_CS3			(0x08)
+#define GPIO_PAR_CS4			(0x10)
+#define GPIO_PAR_CS5			(0x20)
+#define GPIO_PAR_CS1_GPIO		(0x00)
+#define GPIO_PAR_CS1_SDCS1		(0x01)
+#define GPIO_PAR_CS1_CS1		(0x03)
+
+/* Bit definitions and macros for GPIO_PAR_SSI */
+#define GPIO_PAR_SSI_MCLK		(0x0080)
+#define GPIO_PAR_SSI_TXD(x)		(((x)&0x0003)<<8)
+#define GPIO_PAR_SSI_RXD(x)		(((x)&0x0003)<<10)
+#define GPIO_PAR_SSI_FS(x)		(((x)&0x0003)<<12)
+#define GPIO_PAR_SSI_BCLK(x)		(((x)&0x0003)<<14)
+
+/* Bit definitions and macros for GPIO_PAR_UART */
+#define GPIO_PAR_UART_TXD0		(0x0001)
+#define GPIO_PAR_UART_RXD0		(0x0002)
+#define GPIO_PAR_UART_RTS0		(0x0004)
+#define GPIO_PAR_UART_CTS0		(0x0008)
+#define GPIO_PAR_UART_TXD1(x)		(((x)&0x0003)<<4)
+#define GPIO_PAR_UART_RXD1(x)		(((x)&0x0003)<<6)
+#define GPIO_PAR_UART_RTS1(x)		(((x)&0x0003)<<8)
+#define GPIO_PAR_UART_CTS1(x)		(((x)&0x0003)<<10)
+#define GPIO_PAR_UART_CTS1_GPIO		(0x0000)
+#define GPIO_PAR_UART_CTS1_SSI_BCLK	(0x0800)
+#define GPIO_PAR_UART_CTS1_ULPI_D7	(0x0400)
+#define GPIO_PAR_UART_CTS1_UCTS1	(0x0C00)
+#define GPIO_PAR_UART_RTS1_GPIO		(0x0000)
+#define GPIO_PAR_UART_RTS1_SSI_FS	(0x0200)
+#define GPIO_PAR_UART_RTS1_ULPI_D6	(0x0100)
+#define GPIO_PAR_UART_RTS1_URTS1	(0x0300)
+#define GPIO_PAR_UART_RXD1_GPIO		(0x0000)
+#define GPIO_PAR_UART_RXD1_SSI_RXD	(0x0080)
+#define GPIO_PAR_UART_RXD1_ULPI_D5	(0x0040)
+#define GPIO_PAR_UART_RXD1_URXD1	(0x00C0)
+#define GPIO_PAR_UART_TXD1_GPIO		(0x0000)
+#define GPIO_PAR_UART_TXD1_SSI_TXD	(0x0020)
+#define GPIO_PAR_UART_TXD1_ULPI_D4	(0x0010)
+#define GPIO_PAR_UART_TXD1_UTXD1	(0x0030)
+
+/* Bit definitions and macros for GPIO_PAR_QSPI */
+#define GPIO_PAR_QSPI_SCK(x)		(((x)&0x0003)<<4)
+#define GPIO_PAR_QSPI_DOUT(x)		(((x)&0x0003)<<6)
+#define GPIO_PAR_QSPI_DIN(x)		(((x)&0x0003)<<8)
+#define GPIO_PAR_QSPI_PCS0(x)		(((x)&0x0003)<<10)
+#define GPIO_PAR_QSPI_PCS1(x)		(((x)&0x0003)<<12)
+#define GPIO_PAR_QSPI_PCS2(x)		(((x)&0x0003)<<14)
+
+/* Bit definitions and macros for GPIO_PAR_TIMER */
+#define GPIO_PAR_TIN0(x)		(((x)&0x03)<<0)
+#define GPIO_PAR_TIN1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_TIN2(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_TIN3(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_TIN3_GPIO		(0x00)
+#define GPIO_PAR_TIN3_TOUT3		(0x80)
+#define GPIO_PAR_TIN3_URXD2		(0x40)
+#define GPIO_PAR_TIN3_TIN3		(0xC0)
+#define GPIO_PAR_TIN2_GPIO		(0x00)
+#define GPIO_PAR_TIN2_TOUT2		(0x20)
+#define GPIO_PAR_TIN2_UTXD2		(0x10)
+#define GPIO_PAR_TIN2_TIN2		(0x30)
+#define GPIO_PAR_TIN1_GPIO		(0x00)
+#define GPIO_PAR_TIN1_TOUT1		(0x08)
+#define GPIO_PAR_TIN1_DACK1		(0x04)
+#define GPIO_PAR_TIN1_TIN1		(0x0C)
+#define GPIO_PAR_TIN0_GPIO		(0x00)
+#define GPIO_PAR_TIN0_TOUT0		(0x02)
+#define GPIO_PAR_TIN0_DREQ0		(0x01)
+#define GPIO_PAR_TIN0_TIN0		(0x03)
+
+/* Bit definitions and macros for GPIO_PAR_LCDDATA */
+#define GPIO_PAR_LCDDATA_LD7_0(x)	((x)&0x03)
+#define GPIO_PAR_LCDDATA_LD15_8(x)	(((x)&0x03)<<2)
+#define GPIO_PAR_LCDDATA_LD16(x)	(((x)&0x03)<<4)
+#define GPIO_PAR_LCDDATA_LD17(x)	(((x)&0x03)<<6)
+
+/* Bit definitions and macros for GPIO_PAR_LCDCTL */
+#define GPIO_PAR_LCDCTL_CLS		(0x0001)
+#define GPIO_PAR_LCDCTL_PS		(0x0002)
+#define GPIO_PAR_LCDCTL_REV		(0x0004)
+#define GPIO_PAR_LCDCTL_SPL_SPR		(0x0008)
+#define GPIO_PAR_LCDCTL_CONTRAST	(0x0010)
+#define GPIO_PAR_LCDCTL_LSCLK		(0x0020)
+#define GPIO_PAR_LCDCTL_LP_HSYNC	(0x0040)
+#define GPIO_PAR_LCDCTL_FLM_VSYNC	(0x0080)
+#define GPIO_PAR_LCDCTL_ACD_OE		(0x0100)
+
+/* Bit definitions and macros for GPIO_PAR_IRQ */
+#define GPIO_PAR_IRQ1(x)		(((x)&0x0003)<<4)
+#define GPIO_PAR_IRQ2(x)		(((x)&0x0003)<<6)
+#define GPIO_PAR_IRQ4(x)		(((x)&0x0003)<<8)
+#define GPIO_PAR_IRQ5(x)		(((x)&0x0003)<<10)
+#define GPIO_PAR_IRQ6(x)		(((x)&0x0003)<<12)
+
+/* Bit definitions and macros for GPIO_MSCR_FLEXBUS */
+#define GPIO_MSCR_FLEXBUS_ADDRCTL(x)	((x)&0x03)
+#define GPIO_MSCR_FLEXBUS_DLOWER(x)	(((x)&0x03)<<2)
+#define GPIO_MSCR_FLEXBUS_DUPPER(x)	(((x)&0x03)<<4)
+
+/* Bit definitions and macros for GPIO_MSCR_SDRAM */
+#define GPIO_MSCR_SDRAM_SDRAM(x)	((x)&0x03)
+#define GPIO_MSCR_SDRAM_SDCLK(x)	(((x)&0x03)<<2)
+#define GPIO_MSCR_SDRAM_SDCLKB(x)	(((x)&0x03)<<4)
+
+/* Bit definitions and macros for GPIO_DSCR_I2C */
+#define GPIO_DSCR_I2C_DSE(x)		((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_PWM */
+#define GPIO_DSCR_PWM_DSE(x)		((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_FEC */
+#define GPIO_DSCR_FEC_DSE(x)		((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_UART */
+#define GPIO_DSCR_UART0_DSE(x)		((x)&0x03)
+#define GPIO_DSCR_UART1_DSE(x)		(((x)&0x03)<<2)
+
+/* Bit definitions and macros for GPIO_DSCR_QSPI */
+#define GPIO_DSCR_QSPI_DSE(x)		((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_TIMER */
+#define GPIO_DSCR_TIMER_DSE(x)		((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_SSI */
+#define GPIO_DSCR_SSI_DSE(x)		((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_LCD */
+#define GPIO_DSCR_LCD_DSE(x)		((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_DEBUG */
+#define GPIO_DSCR_DEBUG_DSE(x)		((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_CLKRST */
+#define GPIO_DSCR_CLKRST_DSE(x)		((x)&0x03)
+
+/* Bit definitions and macros for GPIO_DSCR_IRQ */
+#define GPIO_DSCR_IRQ_DSE(x)		((x)&0x03)
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+/* Bit definitions and macros for SDRAMC_SDMR */
+#define SDRAMC_SDMR_BNKAD_LEMR		(0x40000000)
+#define SDRAMC_SDMR_BNKAD_LMR		(0x00000000)
+#define SDRAMC_SDMR_AD(x)		(((x)&0x00000FFF)<<18)
+#define SDRAMC_SDMR_CMD			(0x00010000)
+
+/* Bit definitions and macros for SDRAMC_SDCR */
+#define SDRAMC_SDCR_MODE_EN		(0x80000000)
+#define SDRAMC_SDCR_CKE			(0x40000000)
+#define SDRAMC_SDCR_DDR			(0x20000000)
+#define SDRAMC_SDCR_REF			(0x10000000)
+#define SDRAMC_SDCR_MUX(x)		(((x)&0x00000003)<<24)
+#define SDRAMC_SDCR_OE_RULE		(0x00400000)
+#define SDRAMC_SDCR_RCNT(x)		(((x)&0x0000003F)<<16)
+#define SDRAMC_SDCR_PS_32		(0x00000000)
+#define SDRAMC_SDCR_PS_16		(0x00002000)
+#define SDRAMC_SDCR_DQS_OE(x)		(((x)&0x0000000F)<<8)
+#define SDRAMC_SDCR_IREF		(0x00000004)
+#define SDRAMC_SDCR_IPALL		(0x00000002)
+
+/* Bit definitions and macros for SDRAMC_SDCFG1 */
+#define SDRAMC_SDCFG1_SRD2RW(x)		(((x)&0x0000000F)<<28)
+#define SDRAMC_SDCFG1_SWT2RD(x)		(((x)&0x00000007)<<24)
+#define SDRAMC_SDCFG1_RDLAT(x)		(((x)&0x0000000F)<<20)
+#define SDRAMC_SDCFG1_ACT2RW(x)		(((x)&0x00000007)<<16)
+#define SDRAMC_SDCFG1_PRE2ACT(x)	(((x)&0x00000007)<<12)
+#define SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8)
+#define SDRAMC_SDCFG1_WTLAT(x)		(((x)&0x00000007)<<4)
+
+/* Bit definitions and macros for SDRAMC_SDCFG2 */
+#define SDRAMC_SDCFG2_BRD2PRE(x)	(((x)&0x0000000F)<<28)
+#define SDRAMC_SDCFG2_BWT2RW(x)		(((x)&0x0000000F)<<24)
+#define SDRAMC_SDCFG2_BRD2WT(x)		(((x)&0x0000000F)<<20)
+#define SDRAMC_SDCFG2_BL(x)		(((x)&0x0000000F)<<16)
+
+/* Bit definitions and macros for SDRAMC_SDDS */
+#define SDRAMC_SDDS_SB_E(x)		(((x)&0x00000003)<<8)
+#define SDRAMC_SDDS_SB_C(x)		(((x)&0x00000003)<<6)
+#define SDRAMC_SDDS_SB_A(x)		(((x)&0x00000003)<<4)
+#define SDRAMC_SDDS_SB_S(x)		(((x)&0x00000003)<<2)
+#define SDRAMC_SDDS_SB_D(x)		((x)&0x00000003)
+
+/* Bit definitions and macros for SDRAMC_SDCS */
+#define SDRAMC_SDCS_BASE(x)		(((x)&0x00000FFF)<<20)
+#define SDRAMC_SDCS_CSSZ(x)		((x)&0x0000001F)
+#define SDRAMC_SDCS_CSSZ_4GBYTE		(0x0000001F)
+#define SDRAMC_SDCS_CSSZ_2GBYTE		(0x0000001E)
+#define SDRAMC_SDCS_CSSZ_1GBYTE		(0x0000001D)
+#define SDRAMC_SDCS_CSSZ_512MBYTE	(0x0000001C)
+#define SDRAMC_SDCS_CSSZ_256MBYTE	(0x0000001B)
+#define SDRAMC_SDCS_CSSZ_128MBYTE	(0x0000001A)
+#define SDRAMC_SDCS_CSSZ_64MBYTE	(0x00000019)
+#define SDRAMC_SDCS_CSSZ_32MBYTE	(0x00000018)
+#define SDRAMC_SDCS_CSSZ_16MBYTE	(0x00000017)
+#define SDRAMC_SDCS_CSSZ_8MBYTE		(0x00000016)
+#define SDRAMC_SDCS_CSSZ_4MBYTE		(0x00000015)
+#define SDRAMC_SDCS_CSSZ_2MBYTE		(0x00000014)
+#define SDRAMC_SDCS_CSSZ_1MBYTE		(0x00000013)
+#define SDRAMC_SDCS_CSSZ_DIABLE		(0x00000000)
+
+/*********************************************************************
+* Phase Locked Loop (PLL)
+*********************************************************************/
+/* Bit definitions and macros for PLL_PODR */
+#define PLL_PODR_CPUDIV(x)		(((x)&0x0F)<<4)
+#define PLL_PODR_BUSDIV(x)		((x)&0x0F)
+
+/* Bit definitions and macros for PLL_PLLCR */
+#define PLL_PLLCR_DITHEN		(0x80)
+#define PLL_PLLCR_DITHDEV(x)		((x)&0x07)
+
+#endif				/* mcf5329_h */
diff --git a/arch/m68k/include/asm/m5441x.h b/arch/m68k/include/asm/m5441x.h
new file mode 100644
index 0000000..f2e7e7f
--- /dev/null
+++ b/arch/m68k/include/asm/m5441x.h
@@ -0,0 +1,870 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5441X Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __MCF5441X__
+#define __MCF5441X__
+
+/* Interrupt Controller (INTC) */
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_EDMA_00		(8)
+#define INT0_LO_EDMA_01		(9)
+#define INT0_LO_EDMA_02		(10)
+#define INT0_LO_EDMA_03		(11)
+#define INT0_LO_EDMA_04		(12)
+#define INT0_LO_EDMA_05		(13)
+#define INT0_LO_EDMA_06		(14)
+#define INT0_LO_EDMA_07		(15)
+#define INT0_LO_EDMA_08		(16)
+#define INT0_LO_EDMA_09		(17)
+#define INT0_LO_EDMA_10		(18)
+#define INT0_LO_EDMA_11		(19)
+#define INT0_LO_EDMA_12		(20)
+#define INT0_LO_EDMA_13		(21)
+#define INT0_LO_EDMA_14		(22)
+#define INT0_LO_EDMA_15		(23)
+#define INT0_LO_EDMA_ERR		(24)
+#define INT0_LO_SCM			(25)
+#define INT0_LO_UART0			(26)
+#define INT0_LO_UART1			(27)
+#define INT0_LO_UART2			(28)
+#define INT0_LO_UART3			(29)
+#define INT0_LO_I2C0			(30)
+#define INT0_LO_DSPI0			(31)
+#define INT0_HI_DTMR0			(32)
+#define INT0_HI_DTMR1			(33)
+#define INT0_HI_DTMR2			(34)
+#define INT0_HI_DTMR3			(35)
+#define INT0_HI_MACNET0_TXF		(36)
+#define INT0_HI_MACNET0_TXB		(37)
+#define INT0_HI_MACNET0_UN		(38)
+#define INT0_HI_MACNET0_RL		(39)
+#define INT0_HI_MACNET0_RXF		(40)
+#define INT0_HI_MACNET0_RXB		(41)
+#define INT0_HI_MACNET0_MII		(42)
+#define INT0_HI_MACNET0_LC		(43)
+/* not used 44 */
+#define INT0_HI_MACNET0_GRA		(45)
+#define INT0_HI_MACNET0_EBERR		(46)
+#define INT0_HI_MACNET0_BABT		(47)
+#define INT0_HI_MACNET0_BABR		(48)
+#define INT0_HI_MACNET1_TXF		(49)
+#define INT0_HI_MACNET1_TXB		(50)
+#define INT0_HI_MACNET1_UN		(51)
+#define INT0_HI_MACNET1_RL		(52)
+#define INT0_HI_MACNET1_RXF		(53)
+#define INT0_HI_MACNET1_RXB		(54)
+#define INT0_HI_MACNET1_MII		(55)
+#define INT0_HI_MACNET1_LC		(56)
+/* not used 57 */
+#define INT0_HI_MACNET1_GRA		(58)
+#define INT0_HI_MACNET1_EBERR		(59)
+#define INT0_HI_MACNET1_BABT		(60)
+#define INT0_HI_MACNET1_BABR		(61)
+#define INT0_HI_SCMIR			(62)
+#define INT0_HI_OW			(63)
+
+#define INT1_LO_CAN0_IFG		(0)
+#define INT1_LO_CAN0_BOFF		(1)
+/* not used 2 */
+#define INT1_LO_CAN0_TXRXWRN		(3)
+#define INT1_LO_CAN1_IFG		(4)
+#define INT1_LO_CAN1_BOFF		(5)
+/* not used 6 */
+#define INT1_LO_CAN1_TXRXWRN		(7)
+#define INT1_LO_EDMA_16		(8)
+#define INT1_LO_EDMA_17		(9)
+#define INT1_LO_EDMA_18		(10)
+#define INT1_LO_EDMA_19		(11)
+#define INT1_LO_EDMA_20		(12)
+#define INT1_LO_EDMA_21		(13)
+#define INT1_LO_EDMA_22		(14)
+#define INT1_LO_EDMA_23		(15)
+#define INT1_LO_EDMA_24		(16)
+#define INT1_LO_EDMA_25		(17)
+#define INT1_LO_EDMA_26		(18)
+#define INT1_LO_EDMA_27		(19)
+#define INT1_LO_EDMA_28		(20)
+#define INT1_LO_EDMA_29		(21)
+#define INT1_LO_EDMA_30		(22)
+#define INT1_LO_EDMA_31		(23)
+#define INT1_LO_EDMA_32		(24)
+#define INT1_LO_EDMA_33		(25)
+#define INT1_LO_EDMA_34		(26)
+#define INT1_LO_EDMA_35		(27)
+#define INT1_LO_EDMA_36		(28)
+#define INT1_LO_EDMA_37		(29)
+#define INT1_LO_EDMA_38		(30)
+#define INT1_LO_EDMA_39		(31)
+#define INT1_LO_EDMA_40		(32)
+#define INT1_HI_EDMA_41		(33)
+#define INT1_HI_EDMA_42		(34)
+#define INT1_HI_EDMA_43		(35)
+#define INT1_HI_EDMA_44		(36)
+#define INT1_HI_EDMA_45		(37)
+#define INT1_HI_EDMA_46		(38)
+#define INT1_HI_EDMA_47		(39)
+#define INT1_HI_EDMA_48		(40)
+#define INT1_HI_EDMA_49		(41)
+#define INT1_HI_EDMA_50		(42)
+#define INT1_HI_EDMA_51		(43)
+#define INT1_HI_EDMA_52		(44)
+#define INT1_HI_EDMA_53		(45)
+#define INT1_HI_EDMA_54		(46)
+#define INT1_HI_EDMA_55		(47)
+#define INT1_HI_UART4			(48)
+#define INT1_HI_UART5			(49)
+#define INT1_HI_UART6			(50)
+#define INT1_HI_UART7			(51)
+#define INT1_HI_UART8			(52)
+#define INT1_HI_UART9			(53)
+#define INT1_HI_DSPI1			(54)
+#define INT1_HI_DSPI2			(55)
+#define INT1_HI_DSPI3			(56)
+#define INT1_HI_I2C1			(57)
+#define INT1_HI_I2C2			(58)
+#define INT1_HI_I2C3			(59)
+#define INT1_HI_I2C4			(60)
+#define INT1_HI_I2C5			(61)
+
+#define INT2_LO_EDMA56_63		(0)
+#define INT2_LO_PWM_SM0SR_CF		(1)
+#define INT2_LO_PWM_SM1SR_CF		(2)
+#define INT2_LO_PWM_SM2SR_CF		(3)
+#define INT2_LO_PWM_SM3SR_CF		(4)
+#define INT2_LO_PWM_SM0SR_RF		(5)
+#define INT2_LO_PWM_SM1SR_RF		(6)
+#define INT2_LO_PWM_SM2SR_RF		(7)
+#define INT2_LO_PWM_SM3SR_RF		(8)
+#define INT2_LO_PWM_FSR		(9)
+#define INT2_LO_PWM_SMSR_REF		(10)
+#define INT2_LO_PLL_SR_LOCF		(11)
+#define INT2_LO_PLL_SR_LOLF		(12)
+#define INT2_LO_PIT0_PIF		(13)
+#define INT2_LO_PIT1_PIF		(14)
+#define INT2_LO_PIT2_PIF		(15)
+#define INT2_LO_PIT3_PIF		(16)
+#define INT2_LO_USBOTG_USBSTS		(17)
+#define INT2_LO_USBH_USBSTS		(18)
+/* not used 19-20 */
+#define INT2_LO_SSI0			(21)
+#define INT2_LO_SSI1			(22)
+#define INT2_LO_NFC			(23)
+/* not used 24-25 */
+#define INT2_LO_RTC			(26)
+#define INT2_LO_CCM_UOCSR		(27)
+#define INT2_LO_RNG_EI			(28)
+#define INT2_LO_SIM1_DATA		(29)
+#define INT2_LO_SIM1			(30)
+#define INT2_LO_SDHC			(31)
+/* not used 32-37 */
+#define INT2_HI_L2SW_BERR		(38)
+#define INT2_HI_L2SW_RXB		(39)
+#define INT2_HI_L2SW_RXF		(40)
+#define INT2_HI_L2SW_TXB		(41)
+#define INT2_HI_L2SW_TXF		(42)
+#define INT2_HI_L2SW_QM		(43)
+#define INT2_HI_L2SW_OD0		(44)
+#define INT2_HI_L2SW_OD1		(45)
+#define INT2_HI_L2SW_OD2		(46)
+#define INT2_HI_L2SW_LRN		(47)
+#define INT2_HI_MACNET0_TS		(48)
+#define INT2_HI_MACNET0_WAKE		(49)
+#define INT2_HI_MACNET0_PLR		(50)
+/* not used 51-54 */
+#define INT2_HI_MACNET1_TS		(51)
+#define INT2_HI_MACNET1_WAKE		(52)
+#define INT2_HI_MACNET1_PLR		(53)
+
+/* Serial Boot Facility (SBF) */
+#define SBF_SBFCR_BLDIV(x)		(((x)&0x000F))
+#define SBF_SBFCR_FR			(0x0010)
+
+/* Reset Controller Module (RCM) */
+#define RCM_RCR_SOFTRST		(0x80)
+#define RCM_RCR_FRCRSTOUT		(0x40)
+
+#define RCM_RSR_SOFT			(0x20)
+#define RCM_RSR_LOC			(0x10)
+#define RCM_RSR_POR			(0x08)
+#define RCM_RSR_EXT			(0x04)
+#define RCM_RSR_WDR_CORE		(0x02)
+#define RCM_RSR_LOL			(0x01)
+
+/* Chip Configuration Module (CCM) */
+#define CCM_CCR_BOOTMOD		(0xC000)
+#define CCM_CCR_PLLMULT		(0x0FC0)
+#define CCM_CCR_BOOTPS			(0x0030)
+#define CCM_CCR_BOOTPS_32		(0x0000)
+#define CCM_CCR_BOOTPS_16		(0x0020)
+#define CCM_CCR_BOOTPS_8		(0x0010)
+#define CCM_CCR_BOOTPS_		(0x0000)
+#define CCM_CCR_ALESEL			(0x0008)
+#define CCM_CCR_OSCMOD			(0x0004)
+#define CCM_CCR_PLLMOD			(0x0002)
+#define CCM_CCR_BOOTMEM		(0x0001)
+
+#define CCM_CIR_PIN_MASK		(0xFFC0)
+#define CCM_CIR_PRN_MASK		(0x003F)
+#define CCM_CIR_PIN_MCF54410		(0x9F<<6)
+#define CCM_CIR_PIN_MCF54415		(0xA0<<6)
+#define CCM_CIR_PIN_MCF54416		(0xA1<<6)
+#define CCM_CIR_PIN_MCF54417		(0xA2<<6)
+#define CCM_CIR_PIN_MCF54418		(0xA3<<6)
+
+#define CCM_MISCCR_PWM_EXTCLK(x)	(((x)&(0x0003)<<14)
+#define CCM_MISCCR_PWM_EXTCLK_MASK	(0x3FFF)
+#define CCM_MISCCR_PWM_EXTCLK_TMR0	(0x0000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR1	(0x4000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR2	(0x8000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR3	(0xC000)
+#define CCM_MISCCR_LIMP		(0x1000)
+#define CCM_MISCCR_BME			(0x0800)
+#define CCM_MISCCR_BMT(x)		(((x)&0x0007)<<8)
+#define CCM_MISCCR_BMT_65536		(0)
+#define CCM_MISCCR_BMT_32768		(1)
+#define CCM_MISCCR_BMT_16384		(2)
+#define CCM_MISCCR_BMT_8192		(3)
+#define CCM_MISCCR_BMT_4096		(4)
+#define CCM_MISCCR_BMT_2048		(5)
+#define CCM_MISCCR_BMT_1024		(6)
+#define CCM_MISCCR_BMT_512		(7)
+#define CCM_MISCCR_SDHCSRC		(0x0040)
+#define CCM_MISCCR_SSI1SRC		(0x0020)
+#define CCM_MISCCR_SSI0SRC		(0x0010)
+#define CCM_MISCCR_USBHOC		(0x0008)
+#define CCM_MISCCR_USBOOC		(0x0004)
+#define CCM_MISCCR_USBPUE		(0x0002)
+#define CCM_MISCCR_USBSRC		(0x0001)
+
+#define CCM_CDRH_SSI0DIV(x)		(((x)&0x00FF)<<8)
+#define CCM_CDRH_SSI0DIV_MASK		(0x00FF)
+#define CCM_CDRH_SSI1DIV(x)		(((x)&0x00FF))
+#define CCM_CDRH_SSI1DIV_MASK		(0xFF00)
+#define CCM_CDRL_LPDIV(x)		(((x)&0x000F)<<8)
+#define CCM_CDRL_LPDIV_MASK		(0xFF0F)
+#define CCM_CDR_LPDIV(x)		CCM_CDRL_LPDIV(x)
+
+#define CCM_UOCSR_DPPD			(0x2000)
+#define CCM_UOCSR_DMPD			(0x1000)
+#define CCM_UOCSR_DRV_VBUS		(0x0800)
+#define CCM_UOCSR_CRG_VBUS		(0x0400)
+#define CCM_UOCSR_DCR_VBUS		(0x0200)
+#define CCM_UOCSR_DPPU			(0x0100)
+#define CCM_UOCSR_AVLD			(0x0080)
+#define CCM_UOCSR_BVLD			(0x0040)
+#define CCM_UOCSR_VVLD			(0x0020)
+#define CCM_UOCSR_SEND			(0x0010)
+#define CCM_UOCSR_PWRFLT		(0x0008)
+#define CCM_UOCSR_WKUP			(0x0004)
+#define CCM_UOCSR_UOMIE		(0x0002)
+#define CCM_UOCSR_XPDE			(0x0001)
+
+#define CCM_UHCSR_DRV_VBUS		(0x0010)
+#define CCM_UHCSR_PWRFLT		(0x0008)
+#define CCM_UHCSR_WKUP			(0x0004)
+#define CCM_UHCSR_UOMIE		(0x0002)
+#define CCM_UHCSR_XPDE			(0x0001)
+
+#define CCM_MISCCR3_TMR_ENET		(0x1000)
+#define CCM_MISCCR3_ENETCLK(x)		(((x)&7)<<8)
+#define CCM_MISCCR3_ENETCLK_MASK	(0xF8FF)
+#define CCM_MISCCR3_ENETCLK_MII	(0x0700)
+#define CCM_MISCCR3_ENETCLK_OSC	(0x0600)
+#define CCM_MISCCR3_ENETCLK_USB	(0x0500)
+#define CCM_MISCCR3_ENETCLK_TMR3	(0x0400)
+#define CCM_MISCCR3_ENETCLK_TMR2	(0x0300)
+#define CCM_MISCCR3_ENETCLK_TMR1	(0x0200)
+#define CCM_MISCCR3_ENETCLK_TMR0	(0x0100)
+#define CCM_MISCCR3_ENETCLK_INTBUS	(0x0000)
+
+#define CCM_MISCCR2_EXTCLKBYP		(0x8000)
+#define CCM_MISCCR2_DDR2CLK		(0x4000)
+#define CCM_MISCCR2_RGPIO_HALF		(0x2000)
+#define CCM_MISCCR2_SWTSCR		(0x1000)
+#define CCM_MISCCR2_PLLMODE(x)		(((x)&7)<<8)
+#define CCM_MISCCR2_PLLMODE_MASK	(0xF8FF)
+#define CCM_MISCCR2_DCCBYP		(0x0080)
+#define CCM_MISCCR2_DAC1SEL		(0x0040)
+#define CCM_MISCCR2_DAC0SEL		(0x0020)
+#define CCM_MISCCR2_ADCEN		(0x0010)
+#define CCM_MISCCR2_ADC7SEL		(0x0008)
+#define CCM_MISCCR2_ADC3SEL		(0x0004)
+#define CCM_MISCCR2_FBHALF		(0x0002)
+#define CCM_MISCCR2_ULPI		(0x0001)
+
+#define CCM_FNACR_PCR(x)		(((x)&0x0F)<<24)
+#define CCM_FNACR_PCR_MASK		(0xF0FFFFFF)
+#define CCM_FNACR_MCC(x)		((x)&0xFFFF)
+#define CCM_FNACR_MCC_MASK		(0xFFFF0000)
+
+/* General Purpose I/O Module (GPIO) */
+#define GPIO_PAR_FBCTL_ALE(x)		(((x)&3)<<6)
+#define GPIO_PAR_FBCTL_ALE_MASK	(0x3F)
+#define GPIO_PAR_FBCTL_ALE_FB_ALE	(0xC0)
+#define GPIO_PAR_FBCTL_ALE_FB_TS	(0x80)
+#define GPIO_PAR_FBCTL_ALE_GPIO	(0x00)
+#define GPIO_PAR_FBCTL_OE(x)		(((x)&3)<<4)
+#define GPIO_PAR_FBCTL_OE_MASK		(0xCF)
+#define GPIO_PAR_FBCTL_OE_FB_OE	(0x30)
+#define GPIO_PAR_FBCTL_OE_FB_TBST	(0x20)
+#define GPIO_PAR_FBCTL_OE_NFC_RE	(0x20)
+#define GPIO_PAR_FBCTL_OE_GPIO		(0x00)
+#define GPIO_PAR_FBCTL_FBCLK		(0x08)
+#define GPIO_PAR_FBCTL_RW		(0x04)
+#define GPIO_PAR_FBCTL_TA(x)		((x)&3)
+#define GPIO_PAR_FBCTL_TA_MASK		(0xFC)
+#define GPIO_PAR_FBCTL_TA_TA		(0x03)
+#define GPIO_PAR_FBCTL_TA_NFC_RB	(0x01)
+#define GPIO_PAR_FBCTL_TA_GPIO		(0x00)
+
+#define GPIO_PAR_BE_BS3(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_BE_BE3_MASK		(0x3F)
+#define GPIO_PAR_BE_BE3_BE3		(0xC0)
+#define GPIO_PAR_BE_BE3_CS3		(0x80)
+#define GPIO_PAR_BE_BE3_FB_A1		(0x40)
+#define GPIO_PAR_BE_BE3_NFC_ALE	(0x40)
+#define GPIO_PAR_BE_BE3_GPIO		(0x00)
+#define GPIO_PAR_BE_BS2(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_BE_BE2_MASK		(0xCF)
+#define GPIO_PAR_BE_BE2_BE2		(0x30)
+#define GPIO_PAR_BE_BE2_CS2		(0x20)
+#define GPIO_PAR_BE_BE2_FB_A0		(0x10)
+#define GPIO_PAR_BE_BE2_NFC_CLE	(0x10)
+#define GPIO_PAR_BE_BE2_GPIO		(0x00)
+#define GPIO_PAR_BE_BS1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_BE_BE1_MASK		(0xF3)
+#define GPIO_PAR_BE_BE1_BE1		(0x0C)
+#define GPIO_PAR_BE_BE1_FB_TSZ1	(0x08)
+#define GPIO_PAR_BE_BE1_GPIO		(0x00)
+#define GPIO_PAR_BE_BS0(x)		((x)&0x03)
+#define GPIO_PAR_BE_BE0_MASK		(0xFC)
+#define GPIO_PAR_BE_BE0_BE0		(0x03)
+#define GPIO_PAR_BE_BE0_FB_TSZ0	(0x02)
+#define GPIO_PAR_BE_BE0_GPIO		(0x00)
+
+#define GPIO_PAR_CS_CS5(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_CS_CS5_MASK		(0x3F)
+#define GPIO_PAR_CS_CS5_CS5		(0xC0)
+#define GPIO_PAR_CS_CS5_DACK1		(0x80)
+#define GPIO_PAR_CS_CS5_GPIO		(0x00)
+#define GPIO_PAR_CS_CS4(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_CS_CS4_MASK		(0xCF)
+#define GPIO_PAR_CS_CS4_CS4		(0x30)
+#define GPIO_PAR_CS_CS4_DREQ1		(0x20)
+#define GPIO_PAR_CS_CS4_GPIO		(0x00)
+#define GPIO_PAR_CS_CS1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_CS_CS1_MASK		(0xF3)
+#define GPIO_PAR_CS_CS1_CS1		(0x0C)
+#define GPIO_PAR_CS_CS1_NFC_CE		(0x04)
+#define GPIO_PAR_CS_CS1_GPIO		(0x00)
+#define GPIO_PAR_CS_CS0_CS0		(0x01)
+
+#define GPIO_PAR_CANI2C_I2C0SCL(x)	(((x)&0x03)<<6)
+#define GPIO_PAR_CANI2C_I2C0SCL_MASK	(0x3F)
+#define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL	(0xC0)
+#define GPIO_PAR_CANI2C_I2C0SCL_U8TXD	(0x80)
+#define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX	(0x40)
+#define GPIO_PAR_CANI2C_I2C0SCL_GPIO	(0x00)
+#define GPIO_PAR_CANI2C_I2C0SDA(x)	(((x)&0x03)<<4)
+#define GPIO_PAR_CANI2C_I2C0SDA_MASK	(0xCF)
+#define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA	(0x30)
+#define GPIO_PAR_CANI2C_I2C0SDA_U8RXD	(0x20)
+#define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX	(0x10)
+#define GPIO_PAR_CANI2C_I2C0SDA_GPIO	(0x00)
+#define GPIO_PAR_CANI2C_CAN1TX(x)	(((x)&0x03)<<2)
+#define GPIO_PAR_CANI2C_CAN1TX_MASK	(0xF3)
+#define GPIO_PAR_CANI2C_CAN1TX_CAN1TX	(0x0C)
+#define GPIO_PAR_CANI2C_CAN1TX_U9TXD	(0x08)
+#define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL	(0x04)
+#define GPIO_PAR_CANI2C_CAN1TX_GPIO	(0x00)
+#define GPIO_PAR_CANI2C_CAN1RX(x)	((x)&0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_MASK	(0xFC)
+#define GPIO_PAR_CANI2C_CAN1RX_CAN1RX	(0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_U9RXD	(0x02)
+#define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA	(0x01)
+#define GPIO_PAR_CANI2C_CAN1RX_GPIO	(0x00)
+
+#define GPIO_PAR_IRQH_IRQ7		(0x10)
+#define GPIO_PAR_IRQH_IRQ4(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_IRQH_IRQ4_MASK	(0xF3)
+#define GPIO_PAR_IRQH_IRQ4_IRQ4	(0x0C)
+#define GPIO_PAR_IRQH_IRQ4_DREQ0	(0x08)
+#define GPIO_PAR_IRQH_IRQ4_GPIO	(0x00)
+#define GPIO_PAR_IRQH_IRQ1		(0x03)
+
+#define GPIO_PAR_IRQL_IRQ6(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_IRQL_IRQ6_MASK	(0x3F)
+#define GPIO_PAR_IRQL_IRQ6_IRQ6	(0xC0)
+#define GPIO_PAR_IRQL_IRQ6_USBCLKIN	(0x40)
+#define GPIO_PAR_IRQL_IRQ6_GPIO	(0x00)
+#define GPIO_PAR_IRQL_IRQ3(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_IRQL_IRQ3_MASK	(0xCF)
+#define GPIO_PAR_IRQL_IRQ3_IRQ3	(0x30)
+#define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3	(0x20)
+#define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN	(0x10)
+#define GPIO_PAR_IRQL_IRQ3_GPIO	(0x00)
+#define GPIO_PAR_IRQL_IRQ2(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_IRQL_IRQ2_MASK	(0xF3)
+#define GPIO_PAR_IRQL_IRQ2_IRQ2	(0x0C)
+#define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2	(0x08)
+#define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC	(0x04)
+#define GPIO_PAR_IRQL_IRQ2_GPIO	(0x00)
+
+#define GPIO_PAR_DSPI0_SIN(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_DSPI0_SIN_MASK	(0x3F)
+#define GPIO_PAR_DSPI0_SIN_DSPI0SIN	(0xC0)
+#define GPIO_PAR_DSPI0_SIN_SBF_DI	(0xC0)
+#define GPIO_PAR_DSPI0_SIN_U3RXD	(0x80)
+#define GPIO_PAR_DSPI0_SIN_SDHC_CMD	(0x40)
+#define GPIO_PAR_DSPI0_SIN_GPIO	(0x00)
+#define GPIO_PAR_DSPI0_SOUT(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_DSPI0_SOUT_MASK	(0xCF)
+#define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT	(0x30)
+#define GPIO_PAR_DSPI0_SOUT_SBF_DO	(0x30)
+#define GPIO_PAR_DSPI0_SOUT_U3TXD	(0x20)
+#define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0	(0x10)
+#define GPIO_PAR_DSPI0_SOUT_GPIO	(0x00)
+#define GPIO_PAR_DSPI0_SCK(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_DSPI0_SCK_MASK	(0xF3)
+#define GPIO_PAR_DSPI0_SCK_DSPI0SCK	(0x0C)
+#define GPIO_PAR_DSPI0_SCK_SBF_CK	(0x0C)
+#define GPIO_PAR_DSPI0_SCK_I2C3SCL	(0x08)
+#define GPIO_PAR_DSPI0_SCK_SDHC_CLK	(0x04)
+#define GPIO_PAR_DSPI0_SCK_GPIO	(0x00)
+#define GPIO_PAR_DSPI0_PCS0(x)		((x)&0x03)
+#define GPIO_PAR_DSPI0_PCS0_MASK	(0xFC)
+#define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0	(0x03)
+#define GPIO_PAR_DSPI0_PCS0_SS		(0x03)
+#define GPIO_PAR_DSPI0_PCS0_I2C3SDA	(0x02)
+#define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3	(0x01)
+#define GPIO_PAR_DSPI0_PCS0_GPIO	(0x00)
+
+#define GPIO_PAR_DSPIOW_DSPI0PSC1	(0x80)
+#define GPIO_PAR_DSPIOW_SBF_CS		(0x80)
+#define GPIO_PAR_DSPIOW_OWDAT		(((x)&0x03)<<4)
+#define GPIO_PAR_DSPIOW_OWDAT_MASK	(0xCF)
+#define GPIO_PAR_DSPIOW_OWDAT_OWDAT	(0x30)
+#define GPIO_PAR_DSPIOW_OWDAT_DACK0	(0x20)
+#define GPIO_PAR_DSPIOW_OWDAT_GPIO	(0x00)
+
+#define GPIO_PAR_TIMER_T3IN(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_TIMER_T3IN_MASK	(0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
+#define GPIO_PAR_TIMER_T3IN_EXTA3	(0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
+#define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN	(0x40)
+#define GPIO_PAR_TIMER_T3IN_ULIPI_DIR	(0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T2IN(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_T2IN_MASK	(0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
+#define GPIO_PAR_TIMER_T2IN_EXTA2	(0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
+#define GPIO_PAR_TIMER_T2IN_SDHC_DAT2	(0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T1IN(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_TIMER_T1IN_MASK	(0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
+#define GPIO_PAR_TIMER_T1IN_EXTA1	(0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
+#define GPIO_PAR_TIMER_T1IN_SDHC_DAT1	(0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T0IN(x)		((x)&0x03)
+#define GPIO_PAR_TIMER_T0IN_MASK	(0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
+#define GPIO_PAR_TIMER_T0IN_EXTA0	(0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
+#define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC	(0x01)
+#define GPIO_PAR_TIMER_T0IN_ULPI_NXT	(0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO	(0x00)
+
+#define GPIO_PAR_UART2_U2CTS(x)	(((x)&0x03)<<6)
+#define GPIO_PAR_UART2_U2CTS_MASK	(0x3F)
+#define GPIO_PAR_UART2_U2CTS_U2CTS	(0xC0)
+#define GPIO_PAR_UART2_U2CTS_U6TXD	(0x80)
+#define GPIO_PAR_UART2_U2CTS_SSI1_BCLK	(0x40)
+#define GPIO_PAR_UART2_U2CTS_GPIO	(0x00)
+#define GPIO_PAR_UART2_U2RTS(x)	(((x)&0x03)<<4)
+#define GPIO_PAR_UART2_U2RTS_MASK	(0xCF)
+#define GPIO_PAR_UART2_U2RTS_U2RTS	(0x30)
+#define GPIO_PAR_UART2_U2RTS_U6RXD	(0x20)
+#define GPIO_PAR_UART2_U2RTS_SSI1_FS	(0x10)
+#define GPIO_PAR_UART2_U2RTS_GPIO	(0x00)
+#define GPIO_PAR_UART2_U2RXD(x)	(((x)&0x03)<<2)
+#define GPIO_PAR_UART2_U2RXD_MASK	(0xF3)
+#define GPIO_PAR_UART2_U2RXD_U2RXD	(0x0C)
+#define GPIO_PAR_UART2_U2RXD_PWM_A3	(0x08)
+#define GPIO_PAR_UART2_U2RXD_SSI1_RXD	(0x04)
+#define GPIO_PAR_UART2_U2RXD_GPIO	(0x00)
+#define GPIO_PAR_UART2_U2TXD(x)	((x)&0x03)
+#define GPIO_PAR_UART2_U2TXD_MASK	(0xFC)
+#define GPIO_PAR_UART2_U2TXD_U2TXD	(0x03)
+#define GPIO_PAR_UART2_U2TXD_PWM_B3	(0x02)
+#define GPIO_PAR_UART2_U2TXD_SSI1_TXD	(0x01)
+#define GPIO_PAR_UART2_U2TXD_GPIO	(0x00)
+
+#define GPIO_PAR_UART1_U1CTS(x)	(((x)&0x03)<<6)
+#define GPIO_PAR_UART1_U1CTS_MASK	(0x3F)
+#define GPIO_PAR_UART1_U1CTS_U1CTS	(0xC0)
+#define GPIO_PAR_UART1_U1CTS_U5TXD	(0x80)
+#define GPIO_PAR_UART1_U1CTS_DSPI3_SCK	(0x40)
+#define GPIO_PAR_UART1_U1CTS_GPIO	(0x00)
+#define GPIO_PAR_UART1_U1RTS(x)	(((x)&0x03)<<4)
+#define GPIO_PAR_UART1_U1RTS_MASK	(0xCF)
+#define GPIO_PAR_UART1_U1RTS_U1RTS	(0x30)
+#define GPIO_PAR_UART1_U1RTS_U5RXD	(0x20)
+#define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0	(0x10)
+#define GPIO_PAR_UART1_U1RTS_GPIO	(0x00)
+#define GPIO_PAR_UART1_U1RXD(x)	(((x)&0x03)<<2)
+#define GPIO_PAR_UART1_U1RXD_MASK	(0xF3)
+#define GPIO_PAR_UART1_U1RXD_U1RXD	(0x0C)
+#define GPIO_PAR_UART1_U1RXD_I2C5SDA	(0x08)
+#define GPIO_PAR_UART1_U1RXD_DSPI3_SIN	(0x04)
+#define GPIO_PAR_UART1_U1RXD_GPIO	(0x00)
+#define GPIO_PAR_UART1_U1TXD(x)	((x)&0x03)
+#define GPIO_PAR_UART1_U1TXD_MASK	(0xFC)
+#define GPIO_PAR_UART1_U1TXD_U1TXD	(0x03)
+#define GPIO_PAR_UART1_U1TXD_I2C5SCL	(0x02)
+#define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT	(0x01)
+#define GPIO_PAR_UART1_U1TXD_GPIO	(0x00)
+
+#define GPIO_PAR_UART0_U0CTS(x)	(((x)&0x03)<<6)
+#define GPIO_PAR_UART0_U0CTS_MASK	(0x3F)
+#define GPIO_PAR_UART0_U0CTS_U0CTS	(0xC0)
+#define GPIO_PAR_UART0_U0CTS_U4TXD	(0x80)
+#define GPIO_PAR_UART0_U0CTS_DSPI2_SCK	(0x40)
+#define GPIO_PAR_UART0_U0CTS_GPIO	(0x00)
+#define GPIO_PAR_UART0_U0RTS(x)	(((x)&0x03)<<4)
+#define GPIO_PAR_UART0_U0RTS_MASK	(0xCF)
+#define GPIO_PAR_UART0_U0RTS_U0RTS	(0x30)
+#define GPIO_PAR_UART0_U0RTS_U4RXD	(0x20)
+#define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0	(0x10)
+#define GPIO_PAR_UART0_U0RTS_GPIO	(0x00)
+#define GPIO_PAR_UART0_U0RXD(x)	(((x)&0x03)<<2)
+#define GPIO_PAR_UART0_U0RXD_MASK	(0xF3)
+#define GPIO_PAR_UART0_U0RXD_U0RXD	(0x0C)
+#define GPIO_PAR_UART0_U0RXD_I2C4SDA	(0x08)
+#define GPIO_PAR_UART0_U0RXD_DSPI2_SIN	(0x04)
+#define GPIO_PAR_UART0_U0RXD_GPIO	(0x00)
+#define GPIO_PAR_UART0_U0TXD(x)	((x)&0x03)
+#define GPIO_PAR_UART0_U0TXD_MASK	(0xFC)
+#define GPIO_PAR_UART0_U0TXD_U0TXD	(0x03)
+#define GPIO_PAR_UART0_U0TXD_I2C4SCL	(0x02)
+#define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT	(0x01)
+#define GPIO_PAR_UART0_U0TXD_GPIO	(0x00)
+
+#define GPIO_PAR_SDHCH_DAT3(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_SDHCH_DAT3_MASK	(0x3F)
+#define GPIO_PAR_SDHCH_DAT3_DAT3	(0xC0)
+#define GPIO_PAR_SDHCH_DAT3_PWM_A1	(0x80)
+#define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0	(0x40)
+#define GPIO_PAR_SDHCH_DAT3_GPIO	(0x00)
+#define GPIO_PAR_SDHCH_DAT2(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_SDHCH_DAT2_MASK	(0xCF)
+#define GPIO_PAR_SDHCH_DAT2_DAT2	(0x30)
+#define GPIO_PAR_SDHCH_DAT2_PWM_B1	(0x20)
+#define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2	(0x10)
+#define GPIO_PAR_SDHCH_DAT2_GPIO	(0x00)
+#define GPIO_PAR_SDHCH_DAT1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SDHCH_DAT1_MASK	(0xF3)
+#define GPIO_PAR_SDHCH_DAT1_DAT1	(0x0C)
+#define GPIO_PAR_SDHCH_DAT1_PWM_A2	(0x08)
+#define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1	(0x04)
+#define GPIO_PAR_SDHCH_DAT1_GPIO	(0x00)
+#define GPIO_PAR_SDHCH_DAT0(x)		((x)&0x03)
+#define GPIO_PAR_SDHCH_DAT0_MASK	(0xFC)
+#define GPIO_PAR_SDHCH_DAT0_DAT0	(0x03)
+#define GPIO_PAR_SDHCH_DAT0_PWM_B2	(0x02)
+#define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT	(0x01)
+#define GPIO_PAR_SDHCH_DAT0_GPIO	(0x00)
+
+#define GPIO_PAR_SDHCL_CMD(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SDHCL_CMD_MASK	(0xF3)
+#define GPIO_PAR_SDHCL_CMD_CMD		(0x0C)
+#define GPIO_PAR_SDHCL_CMD_PWM_A0	(0x08)
+#define GPIO_PAR_SDHCL_CMD_DSPI1_SIN	(0x04)
+#define GPIO_PAR_SDHCL_CMD_GPIO	(0x00)
+#define GPIO_PAR_SDHCL_CLK(x)		((x)&0x03)
+#define GPIO_PAR_SDHCL_CLK_MASK	(0xFC)
+#define GPIO_PAR_SDHCL_CLK_CLK		(0x03)
+#define GPIO_PAR_SDHCL_CLK_PWM_B0	(0x02)
+#define GPIO_PAR_SDHCL_CLK_DSPI1_SCK	(0x01)
+#define GPIO_PAR_SDHCL_CLK_GPIO	(0x00)
+
+#define GPIO_PAR_SIMP0H_DAT(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_SIMP0H_DAT_MASK	(0x3F)
+#define GPIO_PAR_SIMP0H_DAT_DAT	(0xC0)
+#define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2	(0x80)
+#define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7	(0x40)
+#define GPIO_PAR_SIMP0H_DAT_GPIO	(0x00)
+#define GPIO_PAR_SIMP0H_VEN(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_SIMP0H_VEN_MASK	(0xCF)
+#define GPIO_PAR_SIMP0H_VEN_VEN	(0x30)
+#define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0	(0x20)
+#define GPIO_PAR_SIMP0H_VEN_GPIO	(0x00)
+#define GPIO_PAR_SIMP0H_RST(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SIMP0H_RST_MASK	(0xF3)
+#define GPIO_PAR_SIMP0H_RST_RST	(0x0C)
+#define GPIO_PAR_SIMP0H_RST_PWM_FORCE	(0x08)
+#define GPIO_PAR_SIMP0H_RST_SDHC_DAT6	(0x04)
+#define GPIO_PAR_SIMP0H_RST_GPIO	(0x00)
+#define GPIO_PAR_SIMP0H_PD(x)		((x)&0x03)
+#define GPIO_PAR_SIMP0H_PD_MASK	(0xFC)
+#define GPIO_PAR_SIMP0H_PD_PD		(0x03)
+#define GPIO_PAR_SIMP0H_PD_PWM_SYNC	(0x02)
+#define GPIO_PAR_SIMP0H_PD_SDHC_DAT5	(0x01)
+#define GPIO_PAR_SIMP0H_PD_GPIO	(0x00)
+
+#define GPIO_PAR_SIMP0L_CLK(x)		((x)&0x03)
+#define GPIO_PAR_SIMP0L_CLK_MASK	(0xFC)
+#define GPIO_PAR_SIMP0L_CLK_CLK	(0x03)
+#define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1	(0x02)
+#define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4	(0x01)
+#define GPIO_PAR_SIMP0L_CLK_GPIO	(0x00)
+
+#define GPIO_PAR_SSI0H_RXD(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_SSI0H_RXD_MASK	(0x3F)
+#define GPIO_PAR_SSI0H_RXD_RXD		(0xC0)
+#define GPIO_PAR_SSI0H_RXD_I2C2SDA	(0x80)
+#define GPIO_PAR_SSI0H_RXD_SIM1_VEN	(0x40)
+#define GPIO_PAR_SSI0H_RXD_GPIO	(0x00)
+#define GPIO_PAR_SSI0H_TXD(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_SSI0H_TXD_MASK	(0xCF)
+#define GPIO_PAR_SSI0H_TXD_TXD		(0x30)
+#define GPIO_PAR_SSI0H_TXD_I2C2SCL	(0x20)
+#define GPIO_PAR_SSI0H_TXD_SIM1_DAT	(0x10)
+#define GPIO_PAR_SSI0H_TXD_GPIO	(0x00)
+#define GPIO_PAR_SSI0H_FS(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SSI0H_FS_MASK		(0xF3)
+#define GPIO_PAR_SSI0H_FS_FS		(0x0C)
+#define GPIO_PAR_SSI0H_FS_U7TXD	(0x08)
+#define GPIO_PAR_SSI0H_FS_SIM1_RST	(0x04)
+#define GPIO_PAR_SSI0H_FS_GPIO		(0x00)
+#define GPIO_PAR_SSI0H_MCLK(x)		((x)&0x03)
+#define GPIO_PAR_SSI0H_MCLK_MASK	(0xFC)
+#define GPIO_PAR_SSI0H_MCLK_MCLK	(0x03)
+#define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN	(0x02)
+#define GPIO_PAR_SSI0H_MCLK_SIM1_CLK	(0x01)
+#define GPIO_PAR_SSI0H_MCLK_GPIO	(0x00)
+
+#define GPIO_PAR_SSI0L_BCLK(x)		((x)&0x03)
+#define GPIO_PAR_SSI0L_BCLK_MASK	(0xFC)
+#define GPIO_PAR_SSI0L_BCLK_BCLK	(0x03)
+#define GPIO_PAR_SSI0L_BCLK_U7RXD	(0x02)
+#define GPIO_PAR_SSI0L_BCLK_SIM1_PD	(0x01)
+#define GPIO_PAR_SSI0L_BCLK_GPIO	(0x00)
+
+#define GPIO_PAR_DEBUGH1_DAT3		(0x40)
+#define GPIO_PAR_DEBUGH1_DAT2		(0x10)
+#define GPIO_PAR_DEBUGH1_DAT1		(0x04)
+#define GPIO_PAR_DEBUGH1_DAT0		(0x01)
+
+#define GPIO_PAR_DEBUGH0_PST3		(0x40)
+#define GPIO_PAR_DEBUGH0_PST2		(0x10)
+#define GPIO_PAR_DEBUGH0_PST1		(0x04)
+#define GPIO_PAR_DEBUGH0_PST0		(0x01)
+
+#define GPIO_PODR_G4_VAL		(0x01 << 4)
+#define GPIO_PODR_G4_MASK		(0xff & ~GPIO_PODR_G4_VAL)
+#define GPIO_PDDR_G4_OUTPUT		(0x01 << 4)
+#define GPIO_PDDR_G4_MASK		(0xff & ~GPIO_PDDR_G4_OUTPUT)
+
+#define GPIO_PAR_DEBUGL_ALLPST		(0x01)
+
+#define GPIO_PAR_FEC_FEC(x)		((x)&0x0F)
+#define GPIO_PAR_FEC_FEC_MASK		(0xF0)
+#define GPIO_PAR_FEC_FEC_GPIO		(0x0D)
+#define GPIO_PAR_FEC_FEC_RMII1		(0x0C)
+#define GPIO_PAR_FEC_FEC_RMII1FUL	(0x0B)
+#define GPIO_PAR_FEC_FEC_RMII_ULPI	(0x0A)
+#define GPIO_PAR_FEC_FEC_RMII0		(0x09)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI	(0x08)
+#define GPIO_PAR_FEC_FEC_RMII0FUL	(0x07)
+#define GPIO_PAR_FEC_FEC_RMII0_1FUL	(0x06)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1	(0x05)	/* 0:Full 1: */
+/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
+#define GPIO_PAR_FEC_FEC_RMII0_1	(0x04)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL	(0x03)
+#define GPIO_PAR_FEC_FEC_MII		(0x01)	/* MDC & MDIO - GPIO */
+#define GPIO_PAR_FEC_FEC_MIIFUL	(0x00)
+
+
+/* TC: Need to edit here.... */
+
+/* Mode Select Control */
+#define GPIO_MSCR_SDRAM_MSC(x)		((x)&0x03)
+#define GPIO_MSCR_SDRAM_MSC_MASK	(0xFC)
+
+/* Slew Rate Control */
+
+#define GPIO_SRCR_FB3_FB3(x)		((x)&0x03)
+#define GPIO_SRCR_FB3_FB3_MASK		(0xFC)
+
+#define GPIO_SRCR_FB2_FB2(x)		((x)&0x03)
+#define GPIO_SRCR_FB2_FB2_MASK		(0xFC)
+
+#define GPIO_SRCR_FB1_FB1(x)		((x)&0x03)
+#define GPIO_SRCR_FB1_FB1_MASK		(0xFC)
+
+#define GPIO_SRCR_FB4_FB5(x)		(((x)&0x03)<<2)
+#define GPIO_SRCR_FB4_FB5_MASK		(0xF3)
+#define GPIO_SRCR_FB4_FB4(x)		((x)&0x03)
+#define GPIO_SRCR_FB4_FB4_MASK		(0xFC)
+
+#define GPIO_SRCR_DSPIOW_OWDAT(x)	(((x)&0x03)<<4)
+#define GPIO_SRCR_DSPIOW_OWDAT_MASK	(0xCF)
+#define GPIO_SRCR_DSPIOW_DSPI0(x)	((x)&0x03)
+#define GPIO_SRCR_DSPIOW_DSPI0_MASK	(0xFC)
+
+#define GPIO_SRCR_CANI2C_CAN1(x)	(((x)&0x03)<<2)
+#define GPIO_SRCR_CANI2C_CAN1_MASK	(0xF3)
+#define GPIO_SRCR_CANI2C_I2C0(x)	((x)&0x03)
+#define GPIO_SRCR_CANI2C_I2C0_MASK	(0xFC)
+
+#define GPIO_SRCR_IRQ0_IRQ0(x)		((x)&0x03)
+#define GPIO_SRCR_IRQ0_IRQ0_MASK	(0xFC)
+
+#define GPIO_SRCR_TIMER_TMR3(x)	(((x)&0x03)<<6)
+#define GPIO_SRCR_TIMER_TMR3_MASK	(0x3F)
+#define GPIO_SRCR_TIMER_TMR2(x)	(((x)&0x03)<<4)
+#define GPIO_SRCR_TIMER_TMR2_MASK	(0xCF)
+#define GPIO_SRCR_TIMER_TMR1(x)	(((x)&0x03)<<2)
+#define GPIO_SRCR_TIMER_TMR1_MASK	(0xF3)
+#define GPIO_SRCR_TIMER_TMR0(x)	((x)&0x03)
+#define GPIO_SRCR_TIMER_TMR0_MASK	(0xFC)
+
+#define GPIO_SRCR_UART_U2(x)		(((x)&0x03)<<4)
+#define GPIO_SRCR_UART_U2_MASK		(0xCF)
+#define GPIO_SRCR_UART_U1(x)		(((x)&0x03)<<2)
+#define GPIO_SRCR_UART_U1_MASK		(0xF3)
+#define GPIO_SRCR_UART_U0(x)		((x)&0x03)
+#define GPIO_SRCR_UART_U0_MASK		(0xFC)
+
+#define GPIO_SRCR_FEC_RMII0(x)		(((x)&0x03)<<2)
+#define GPIO_SRCR_FEC_RMII0_MASK	(0xF3)
+#define GPIO_SRCR_FEC_RMII1(x)		((x)&0x03)
+#define GPIO_SRCR_FEC_RMII1_MASK	(0xFC)
+
+#define GPIO_SRCR_SDHC_SDHC(x)		((x)&0x03)
+#define GPIO_SRCR_SDHC_SDHC_MASK	(0xFC)
+
+#define GPIO_SRCR_SIM0_SIMP0(x)	((x)&0x03)
+#define GPIO_SRCR_SIM0_SIMP0_MASK	(0xFC)
+
+#define GPIO_SRCR_SSI0_SSI0(x)		((x)&0x03)
+#define GPIO_SRCR_SSI0_SSI0_MASK	(0xFC)
+
+#define GPIO_PCR_URTS_U2		(0x0004)
+#define GPIO_PCR_URTS_U1		(0x0002)
+#define GPIO_PCR_URTS_U0		(0x0001)
+
+#define GPIO_PCR_UCTS_U2		(0x0004)
+#define GPIO_PCR_UCTS_U1		(0x0002)
+#define GPIO_PCR_UCTS_U0		(0x0001)
+
+#define GPIO_UTXD_WOM_U9		(0x0200)
+#define GPIO_UTXD_WOM_U8		(0x0100)
+#define GPIO_UTXD_WOM_U7		(0x0080)
+#define GPIO_UTXD_WOM_U6		(0x0040)
+#define GPIO_UTXD_WOM_U5		(0x0020)
+#define GPIO_UTXD_WOM_U4		(0x0010)
+#define GPIO_UTXD_WOM_U3		(0x0008)
+#define GPIO_UTXD_WOM_U2		(0x0004)
+#define GPIO_UTXD_WOM_U1		(0x0002)
+#define GPIO_UTXD_WOM_U0		(0x0001)
+
+#define GPIO_URXD_WOM_U9(x)		(((x)&3)<<18)
+#define GPIO_URXD_WOM_U9_MASK		(0xFFF3FFFF)
+#define GPIO_URXD_WOM_U8(x)		(((x)&3)<<16)
+#define GPIO_URXD_WOM_U8_MASK		(0xFFFCFFFF)
+#define GPIO_URXD_WOM_U7(x)		(((x)&3)<<14)
+#define GPIO_URXD_WOM_U7_MASK		(0xFFFF3FFF)
+#define GPIO_URXD_WOM_U6(x)		(((x)&3)<<12)
+#define GPIO_URXD_WOM_U6_MASK		(0xFFFFCFFF)
+#define GPIO_URXD_WOM_U5(x)		(((x)&3)<<10)
+#define GPIO_URXD_WOM_U5_MASK		(0xFFFFF3FF)
+#define GPIO_URXD_WOM_U4(x)		(((x)&3)<<8)
+#define GPIO_URXD_WOM_U4_MASK		(0xFFFFFCFF)
+#define GPIO_URXD_WOM_U3(x)		(((x)&3)<<6)
+#define GPIO_URXD_WOM_U3_MASK		(0xFFFFFF3F)
+#define GPIO_URXD_WOM_U2(x)		(((x)&3)<<4)
+#define GPIO_URXD_WOM_U2_MASK		(0xFFFFFFCF)
+#define GPIO_URXD_WOM_U1(x)		(((x)&3)<<2)
+#define GPIO_URXD_WOM_U1_MASK		(0xFFFFFFF3)
+#define GPIO_URXD_WOM_U0(x)		((x)&3)
+#define GPIO_URXD_WOM_U0_MASK		(0xFFFFFFFC)
+
+#define GPIO_HCR1_PG4_0(x)		(((x)&0x1F)<<27)
+#define GPIO_HCR1_PG4_0_MASK		(0x07FFFFFF)
+#define GPIO_HCR1_PF7_3(x)		(((x)&0x1F)<<22)
+#define GPIO_HCR1_PF7_3_MASK		(0xF83FFFFF)
+#define GPIO_HCR1_PE6_0(x)		(((x)&0x7F)<<15)
+#define GPIO_HCR1_PE6_0_MASK		(0xFFC07FFF)
+#define GPIO_HCR1_PD7_3(x)		(((x)&0x1F)<<10)
+#define GPIO_HCR1_PD7_3_MASK		(0xFFFF83FF)
+#define GPIO_HCR1_PC7_1(x)		(((x)&0x7F)<<3)
+#define GPIO_HCR1_PC7_1_MASK		(0xFFFFFC07)
+#define GPIO_HCR1_PB2_0(x)		((x)&7)
+#define GPIO_HCR1_PB2_0_MASK		(0xFFFFFFF8)
+
+#define GPIO_HCR0_PK3			(0x00000400)
+#define GPIO_HCR0_PK0			(0x00000200)
+#define GPIO_HCR0_PD2_0(x)		(((x)&7)<<6)
+#define GPIO_HCR0_PD2_0_MASK		(0xFFFFFE3F)
+#define GPIO_HCR0_PE7			(0x00000020)
+#define GPIO_HCR0_PH7_3(x)		((x)&0x1F)
+#define GPIO_HCR0_PH7_3_MASK(x)	(0xFFFFFFE0)
+
+/* SDRAM Controller (SDRAMC) */
+
+/* Phase Locked Loop (PLL) */
+#define PLL_CR_LOCIRQ			(0x00040000)
+#define PLL_CR_LOCRE			(0x00020000)
+#define PLL_CR_LOCEN			(0x00010000)
+#define PLL_CR_LOLIRQ			(0x00004000)
+#define PLL_CR_LOLRE			(0x00002000)
+#define PLL_CR_LOLEN			(0x00001000)
+#define PLL_CR_REFDIV(x)		(((x)&7)<<8)
+#define PLL_CR_REFDIV_MASK		(0xFFFFF8FF)
+#define PLL_CR_FBKDIV(x)		((x)&0x3F)
+#define PLL_CR_FBKDIV_MASK		(0xFFFFFFC0)
+#define PLL_CR_FBKDIV_BITS		(0x3F)
+
+#define PLL_DR_OUTDIV5(x)		(((x)&0x1F)<<21)
+#define PLL_DR_OUTDIV5_MASK		(0xFC1FFFFF)
+#define PLL_DR_OUTDIV5_BITS		(0x03E00000)
+#define PLL_DR_OUTDIV4(x)		(((x)&0x1F)<<16)
+#define PLL_DR_OUTDIV4_MASK		(0xFFE0FFFF)
+#define PLL_DR_OUTDIV4_BITS		(0x001F0000)
+#define PLL_DR_OUTDIV3(x)		(((x)&0x1F)<<10)
+#define PLL_DR_OUTDIV3_MASK		(0xFFFF83FF)
+#define PLL_DR_OUTDIV3_BITS		(0x00007C00)
+#define PLL_DR_OUTDIV2(x)		(((x)&0x1F)<<5)
+#define PLL_DR_OUTDIV2_MASK		(0xFFFFFC1F)
+#define PLL_DR_OUTDIV2_BITS		(0x000003E0)
+#define PLL_DR_OUTDIV1(x)		((x)&0x1F)
+#define PLL_DR_OUTDIV1_MASK		(0xFFFFFFE0)
+#define PLL_DR_OUTDIV1_BITS		(0x0000001F)
+
+#define PLL_SR_LOCF			(0x00000200)
+#define PLL_SR_LOC			(0x00000100)
+#define PLL_SR_LOLF			(0x00000040)
+#define PLL_SR_LOCKS			(0x00000020)
+#define PLL_SR_LOCK			(0x00000010)
+#define PLL_PSR_LOCK			PLL_SR_LOCK	/* compatible with 5x */
+#define PLL_SR_MODE(x)			((x)&7)
+#define PLL_SR_MODE_MASK		(0xFFFFFFF8)
+
+#endif				/* __MCF5441X__ */
diff --git a/arch/m68k/include/asm/m5445x.h b/arch/m68k/include/asm/m5445x.h
new file mode 100644
index 0000000..498c225
--- /dev/null
+++ b/arch/m68k/include/asm/m5445x.h
@@ -0,0 +1,888 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MCF5445x Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __MCF5445X__
+#define __MCF5445X__
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_EDMA_00			(8)
+#define INT0_LO_EDMA_01			(9)
+#define INT0_LO_EDMA_02			(10)
+#define INT0_LO_EDMA_03			(11)
+#define INT0_LO_EDMA_04			(12)
+#define INT0_LO_EDMA_05			(13)
+#define INT0_LO_EDMA_06			(14)
+#define INT0_LO_EDMA_07			(15)
+#define INT0_LO_EDMA_08			(16)
+#define INT0_LO_EDMA_09			(17)
+#define INT0_LO_EDMA_10			(18)
+#define INT0_LO_EDMA_11			(19)
+#define INT0_LO_EDMA_12			(20)
+#define INT0_LO_EDMA_13			(21)
+#define INT0_LO_EDMA_14			(22)
+#define INT0_LO_EDMA_15			(23)
+#define INT0_LO_EDMA_ERR		(24)
+#define INT0_LO_SCM			(25)
+#define INT0_LO_UART0			(26)
+#define INT0_LO_UART1			(27)
+#define INT0_LO_UART2			(28)
+#define INT0_LO_RSVD1			(29)
+#define INT0_LO_I2C			(30)
+#define INT0_LO_QSPI			(31)
+#define INT0_HI_DTMR0			(32)
+#define INT0_HI_DTMR1			(33)
+#define INT0_HI_DTMR2			(34)
+#define INT0_HI_DTMR3			(35)
+#define INT0_HI_FEC0_TXF		(36)
+#define INT0_HI_FEC0_TXB		(37)
+#define INT0_HI_FEC0_UN			(38)
+#define INT0_HI_FEC0_RL			(39)
+#define INT0_HI_FEC0_RXF		(40)
+#define INT0_HI_FEC0_RXB		(41)
+#define INT0_HI_FEC0_MII		(42)
+#define INT0_HI_FEC0_LC			(43)
+#define INT0_HI_FEC0_HBERR		(44)
+#define INT0_HI_FEC0_GRA		(45)
+#define INT0_HI_FEC0_EBERR		(46)
+#define INT0_HI_FEC0_BABT		(47)
+#define INT0_HI_FEC0_BABR		(48)
+#define INT0_HI_FEC1_TXF		(49)
+#define INT0_HI_FEC1_TXB		(50)
+#define INT0_HI_FEC1_UN			(51)
+#define INT0_HI_FEC1_RL			(52)
+#define INT0_HI_FEC1_RXF		(53)
+#define INT0_HI_FEC1_RXB		(54)
+#define INT0_HI_FEC1_MII		(55)
+#define INT0_HI_FEC1_LC			(56)
+#define INT0_HI_FEC1_HBERR		(57)
+#define INT0_HI_FEC1_GRA		(58)
+#define INT0_HI_FEC1_EBERR		(59)
+#define INT0_HI_FEC1_BABT		(60)
+#define INT0_HI_FEC1_BABR		(61)
+#define INT0_HI_SCMIR			(62)
+#define INT0_HI_RTC_ISR			(63)
+
+#define INT1_HI_DSPI_EOQF		(33)
+#define INT1_HI_DSPI_TFFF		(34)
+#define INT1_HI_DSPI_TCF		(35)
+#define INT1_HI_DSPI_TFUF		(36)
+#define INT1_HI_DSPI_RFDF		(37)
+#define INT1_HI_DSPI_RFOF		(38)
+#define INT1_HI_DSPI_RFOF_TFUF		(39)
+#define INT1_HI_RNG_EI			(40)
+#define INT1_HI_PIT0_PIF		(43)
+#define INT1_HI_PIT1_PIF		(44)
+#define INT1_HI_PIT2_PIF		(45)
+#define INT1_HI_PIT3_PIF		(46)
+#define INT1_HI_USBOTG_USBSTS		(47)
+#define INT1_HI_SSI_ISR			(49)
+#define INT1_HI_CCM_UOCSR		(53)
+#define INT1_HI_ATA_ISR			(54)
+#define INT1_HI_PCI_SCR			(55)
+#define INT1_HI_PCI_ASR			(56)
+#define INT1_HI_PLL_LOCKS		(57)
+
+/*********************************************************************
+* Watchdog Timer Modules (WTM)
+*********************************************************************/
+
+/* Bit definitions and macros for WCR */
+#define WTM_WCR_EN			(0x0001)
+#define WTM_WCR_HALTED			(0x0002)
+#define WTM_WCR_DOZE			(0x0004)
+#define WTM_WCR_WAIT			(0x0008)
+
+/*********************************************************************
+* Serial Boot Facility (SBF)
+*********************************************************************/
+
+/* Bit definitions and macros for SBFCR */
+#define SBF_SBFCR_BLDIV(x)		(((x)&0x000F))	/* Boot loader clock divider */
+#define SBF_SBFCR_FR			(0x0010)	/* Fast read */
+
+/*********************************************************************
+* Reset Controller Module (RCM)
+*********************************************************************/
+
+/* Bit definitions and macros for RCR */
+#define RCM_RCR_FRCRSTOUT		(0x40)
+#define RCM_RCR_SOFTRST			(0x80)
+
+/* Bit definitions and macros for RSR */
+#define RCM_RSR_LOL			(0x01)
+#define RCM_RSR_WDR_CORE		(0x02)
+#define RCM_RSR_EXT			(0x04)
+#define RCM_RSR_POR			(0x08)
+#define RCM_RSR_SOFT			(0x20)
+
+/*********************************************************************
+* Chip Configuration Module (CCM)
+*********************************************************************/
+
+/* Bit definitions and macros for CCR_360 */
+#define CCM_CCR_360_PLLMULT2(x)		(((x)&0x0003))	/* 2-Bit PLL clock mode */
+#define CCM_CCR_360_PCISLEW		(0x0004)	/* PCI pad slew rate mode */
+#define CCM_CCR_360_PCIMODE		(0x0008)	/* PCI host/agent mode */
+#define CCM_CCR_360_PLLMODE		(0x0010)	/* PLL Mode */
+#define CCM_CCR_360_FBCONFIG(x)		(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */
+#define CCM_CCR_360_PLLMULT3(x)		(((x)&0x0007))	/* 3-Bit PLL Clock Mode */
+#define CCM_CCR_360_OSCMODE		(0x0008)	/* Oscillator Clock Mode */
+#define CCM_CCR_360_FBCONFIG_MASK	(0x00E0)
+#define CCM_CCR_360_PLLMULT2_MASK	(0x0003)
+#define CCM_CCR_360_PLLMULT3_MASK	(0x0007)
+#define CCM_CCR_360_FBCONFIG_NM_NP_32	(0x0000)
+#define CCM_CCR_360_FBCONFIG_NM_NP_8	(0x0020)
+#define CCM_CCR_360_FBCONFIG_NM_NP_16	(0x0040)
+#define CCM_CCR_360_FBCONFIG_M_P_16	(0x0060)
+#define CCM_CCR_360_FBCONFIG_M_NP_32	(0x0080)
+#define CCM_CCR_360_FBCONFIG_M_NP_8	(0x00A0)
+#define CCM_CCR_360_FBCONFIG_M_NP_16	(0x00C0)
+#define CCM_CCR_360_FBCONFIG_M_P_8	(0x00E0)
+#define CCM_CCR_360_PLLMULT2_12X	(0x0000)
+#define CCM_CCR_360_PLLMULT2_6X		(0x0001)
+#define CCM_CCR_360_PLLMULT2_16X	(0x0002)
+#define CCM_CCR_360_PLLMULT2_8X		(0x0003)
+#define CCM_CCR_360_PLLMULT3_20X	(0x0000)
+#define CCM_CCR_360_PLLMULT3_10X	(0x0001)
+#define CCM_CCR_360_PLLMULT3_24X	(0x0002)
+#define CCM_CCR_360_PLLMULT3_18X	(0x0003)
+#define CCM_CCR_360_PLLMULT3_12X	(0x0004)
+#define CCM_CCR_360_PLLMULT3_6X		(0x0005)
+#define CCM_CCR_360_PLLMULT3_16X	(0x0006)
+#define CCM_CCR_360_PLLMULT3_8X		(0x0007)
+
+/* Bit definitions and macros for CCR_256 */
+#define CCM_CCR_256_PLLMULT3(x)		(((x)&0x0007))	/* 3-Bit PLL clock mode */
+#define CCM_CCR_256_OSCMODE		(0x0008)	/* Oscillator clock mode */
+#define CCM_CCR_256_PLLMODE		(0x0010)	/* PLL Mode */
+#define CCM_CCR_256_FBCONFIG(x)		(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */
+#define CCM_CCR_256_FBCONFIG_MASK	(0x00E0)
+#define CCM_CCR_256_FBCONFIG_NM_32	(0x0000)
+#define CCM_CCR_256_FBCONFIG_NM_8	(0x0020)
+#define CCM_CCR_256_FBCONFIG_NM_16	(0x0040)
+#define CCM_CCR_256_FBCONFIG_M_32	(0x0080)
+#define CCM_CCR_256_FBCONFIG_M_8	(0x00A0)
+#define CCM_CCR_256_FBCONFIG_M_16	(0x00C0)
+#define CCM_CCR_256_PLLMULT3_MASK	(0x0007)
+#define CCM_CCR_256_PLLMULT3_20X	(0x0000)
+#define CCM_CCR_256_PLLMULT3_10X	(0x0001)
+#define CCM_CCR_256_PLLMULT3_24X	(0x0002)
+#define CCM_CCR_256_PLLMULT3_18X	(0x0003)
+#define CCM_CCR_256_PLLMULT3_12X	(0x0004)
+#define CCM_CCR_256_PLLMULT3_6X		(0x0005)
+#define CCM_CCR_256_PLLMULT3_16X	(0x0006)
+#define CCM_CCR_256_PLLMULT3_8X		(0x0007)
+
+/* Bit definitions and macros for RCON_360 */
+#define CCM_RCON_360_PLLMULT(x)		(((x)&0x0003))	/* PLL clock mode */
+#define CCM_RCON_360_PCISLEW		(0x0004)	/* PCI pad slew rate mode */
+#define CCM_RCON_360_PCIMODE		(0x0008)	/* PCI host/agent mode */
+#define CCM_RCON_360_PLLMODE		(0x0010)	/* PLL Mode */
+#define CCM_RCON_360_FBCONFIG(x)	(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */
+
+/* Bit definitions and macros for RCON_256 */
+#define CCM_RCON_256_PLLMULT(x)		(((x)&0x0007))	/* PLL clock mode */
+#define CCM_RCON_256_OSCMODE		(0x0008)	/* Oscillator clock mode */
+#define CCM_RCON_256_PLLMODE		(0x0010)	/* PLL Mode */
+#define CCM_RCON_256_FBCONFIG(x)	(((x)&0x0007)<<5)	/* Flexbus/PCI port size configuration */
+
+/* Bit definitions and macros for CIR */
+#define CCM_CIR_PRN(x)			(((x)&0x003F))	/* Part revision number */
+#define CCM_CIR_PIN(x)			(((x)&0x03FF)<<6)	/* Part identification number */
+#define CCM_CIR_PIN_MASK		(0xFFC0)
+#define CCM_CIR_PRN_MASK		(0x003F)
+#define CCM_CIR_PIN_MCF54450		(0x4F<<6)
+#define CCM_CIR_PIN_MCF54451		(0x4D<<6)
+#define CCM_CIR_PIN_MCF54452		(0x4B<<6)
+#define CCM_CIR_PIN_MCF54453		(0x49<<6)
+#define CCM_CIR_PIN_MCF54454		(0x4A<<6)
+#define CCM_CIR_PIN_MCF54455		(0x48<<6)
+
+/* Bit definitions and macros for MISCCR */
+#define CCM_MISCCR_USBSRC		(0x0001)	/* USB clock source */
+#define CCM_MISCCR_USBOC		(0x0002)	/* USB VBUS over-current sense polarity */
+#define CCM_MISCCR_USBPUE		(0x0004)	/* USB transceiver pull-up enable */
+#define CCM_MISCCR_SSISRC		(0x0010)	/* SSI clock source */
+#define CCM_MISCCR_TIMDMA		(0x0020)	/* Timer DMA mux selection */
+#define CCM_MISCCR_SSIPUS		(0x0040)	/* SSI RXD/TXD pull select */
+#define CCM_MISCCR_SSIPUE		(0x0080)	/* SSI RXD/TXD pull enable */
+#define CCM_MISCCR_BMT(x)		(((x)&0x0007)<<8)	/* Bus monitor timing field */
+#define CCM_MISCCR_BME			(0x0800)	/* Bus monitor external enable bit */
+#define CCM_MISCCR_LIMP			(0x1000)	/* Limp mode enable */
+#define CCM_MISCCR_BMT_65536		(0)
+#define CCM_MISCCR_BMT_32768		(1)
+#define CCM_MISCCR_BMT_16384		(2)
+#define CCM_MISCCR_BMT_8192		(3)
+#define CCM_MISCCR_BMT_4096		(4)
+#define CCM_MISCCR_BMT_2048		(5)
+#define CCM_MISCCR_BMT_1024		(6)
+#define CCM_MISCCR_BMT_512		(7)
+#define CCM_MISCCR_SSIPUS_UP		(1)
+#define CCM_MISCCR_SSIPUS_DOWN		(0)
+#define CCM_MISCCR_TIMDMA_TIM		(1)
+#define CCM_MISCCR_TIMDMA_SSI		(0)
+#define CCM_MISCCR_SSISRC_CLKIN		(0)
+#define CCM_MISCCR_SSISRC_PLL		(1)
+#define CCM_MISCCR_USBOC_ACTHI		(0)
+#define CCM_MISCCR_USBOV_ACTLO		(1)
+#define CCM_MISCCR_USBSRC_CLKIN		(0)
+#define CCM_MISCCR_USBSRC_PLL		(1)
+
+/* Bit definitions and macros for CDR */
+#define CCM_CDR_SSIDIV(x)		(((x)&0x00FF))	/* SSI oversampling clock divider */
+#define CCM_CDR_LPDIV(x)		(((x)&0x000F)<<8)	/* Low power clock divider */
+
+/* Bit definitions and macros for UOCSR */
+#define CCM_UOCSR_XPDE			(0x0001)	/* On-chip transceiver pull-down enable */
+#define CCM_UOCSR_UOMIE			(0x0002)	/* USB OTG misc interrupt enable */
+#define CCM_UOCSR_WKUP			(0x0004)	/* USB OTG controller wake-up event */
+#define CCM_UOCSR_PWRFLT		(0x0008)	/* VBUS power fault */
+#define CCM_UOCSR_SEND			(0x0010)	/* Session end */
+#define CCM_UOCSR_VVLD			(0x0020)	/* VBUS valid indicator */
+#define CCM_UOCSR_BVLD			(0x0040)	/* B-peripheral valid indicator */
+#define CCM_UOCSR_AVLD			(0x0080)	/* A-peripheral valid indicator */
+#define CCM_UOCSR_DPPU			(0x0100)	/* D+ pull-up for FS enabled (read-only) */
+#define CCM_UOCSR_DCR_VBUS		(0x0200)	/* VBUS discharge resistor enabled (read-only) */
+#define CCM_UOCSR_CRG_VBUS		(0x0400)	/* VBUS charge resistor enabled (read-only) */
+#define CCM_UOCSR_DMPD			(0x1000)	/* D- 15Kohm pull-down (read-only) */
+#define CCM_UOCSR_DPPD			(0x2000)	/* D+ 15Kohm pull-down (read-only) */
+
+/*********************************************************************
+* General Purpose I/O Module (GPIO)
+*********************************************************************/
+
+/* Bit definitions and macros for PAR_FEC */
+#define GPIO_PAR_FEC_FEC0(x)		(((x)&0x07))
+#define GPIO_PAR_FEC_FEC1(x)		(((x)&0x07)<<4)
+#define GPIO_PAR_FEC_FEC1_UNMASK	(0x8F)
+#define GPIO_PAR_FEC_FEC1_MII		(0x70)
+#define GPIO_PAR_FEC_FEC1_RMII_GPIO	(0x30)
+#define GPIO_PAR_FEC_FEC1_RMII_ATA	(0x20)
+#define GPIO_PAR_FEC_FEC1_ATA		(0x10)
+#define GPIO_PAR_FEC_FEC1_GPIO		(0x00)
+#define GPIO_PAR_FEC_FEC0_UNMASK	(0xF8)
+#define GPIO_PAR_FEC_FEC0_MII		(0x07)
+#define GPIO_PAR_FEC_FEC0_RMII_GPIO	(0x03)
+#define GPIO_PAR_FEC_FEC0_RMII_ULPI	(0x02)
+#define GPIO_PAR_FEC_FEC0_ULPI		(0x01)
+#define GPIO_PAR_FEC_FEC0_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_DMA */
+#define GPIO_PAR_DMA_DREQ0		(0x01)
+#define GPIO_PAR_DMA_DACK0(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_DMA_DREQ1(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_DMA_DACK1(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_DMA_DACK1_UNMASK	(0x3F)
+#define GPIO_PAR_DMA_DACK1_DACK1	(0xC0)
+#define GPIO_PAR_DMA_DACK1_ULPI_DIR	(0x40)
+#define GPIO_PAR_DMA_DACK1_GPIO		(0x00)
+#define GPIO_PAR_DMA_DREQ1_UNMASK	(0xCF)
+#define GPIO_PAR_DMA_DREQ1_DREQ1	(0x30)
+#define GPIO_PAR_DMA_DREQ1_USB_CLKIN	(0x10)
+#define GPIO_PAR_DMA_DREQ1_GPIO		(0x00)
+#define GPIO_PAR_DMA_DACK0_UNMASK	(0xF3)
+#define GPIO_PAR_DMA_DACK0_DACK1	(0x0C)
+#define GPIO_PAR_DMA_DACK0_PCS3		(0x08)
+#define GPIO_PAR_DMA_DACK0_ULPI_DIR	(0x04)
+#define GPIO_PAR_DMA_DACK0_GPIO		(0x00)
+#define GPIO_PAR_DMA_DREQ0_DREQ0	(0x01)
+#define GPIO_PAR_DMA_DREQ0_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_FBCTL */
+#define GPIO_PAR_FBCTL_TS(x)		(((x)&0x03)<<3)
+#define GPIO_PAR_FBCTL_RW		(0x20)
+#define GPIO_PAR_FBCTL_TA		(0x40)
+#define GPIO_PAR_FBCTL_OE		(0x80)
+#define GPIO_PAR_FBCTL_OE_OE		(0x80)
+#define GPIO_PAR_FBCTL_OE_GPIO		(0x00)
+#define GPIO_PAR_FBCTL_TA_TA		(0x40)
+#define GPIO_PAR_FBCTL_TA_GPIO		(0x00)
+#define GPIO_PAR_FBCTL_RW_RW		(0x20)
+#define GPIO_PAR_FBCTL_RW_GPIO		(0x00)
+#define GPIO_PAR_FBCTL_TS_UNMASK	(0xE7)
+#define GPIO_PAR_FBCTL_TS_TS		(0x18)
+#define GPIO_PAR_FBCTL_TS_ALE		(0x10)
+#define GPIO_PAR_FBCTL_TS_TBST		(0x08)
+#define GPIO_PAR_FBCTL_TS_GPIO		(0x80)
+
+/* Bit definitions and macros for PAR_DSPI */
+#define GPIO_PAR_DSPI_SCK		(0x01)
+#define GPIO_PAR_DSPI_SOUT		(0x02)
+#define GPIO_PAR_DSPI_SIN		(0x04)
+#define GPIO_PAR_DSPI_PCS0		(0x08)
+#define GPIO_PAR_DSPI_PCS1		(0x10)
+#define GPIO_PAR_DSPI_PCS2		(0x20)
+#define GPIO_PAR_DSPI_PCS5		(0x40)
+#define GPIO_PAR_DSPI_PCS5_PCS5		(0x40)
+#define GPIO_PAR_DSPI_PCS5_GPIO		(0x00)
+#define GPIO_PAR_DSPI_PCS2_PCS2		(0x20)
+#define GPIO_PAR_DSPI_PCS2_GPIO		(0x00)
+#define GPIO_PAR_DSPI_PCS1_PCS1		(0x10)
+#define GPIO_PAR_DSPI_PCS1_GPIO		(0x00)
+#define GPIO_PAR_DSPI_PCS0_PCS0		(0x08)
+#define GPIO_PAR_DSPI_PCS0_GPIO		(0x00)
+#define GPIO_PAR_DSPI_SIN_SIN		(0x04)
+#define GPIO_PAR_DSPI_SIN_GPIO		(0x00)
+#define GPIO_PAR_DSPI_SOUT_SOUT		(0x02)
+#define GPIO_PAR_DSPI_SOUT_GPIO		(0x00)
+#define GPIO_PAR_DSPI_SCK_SCK		(0x01)
+#define GPIO_PAR_DSPI_SCK_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_BE */
+#define GPIO_PAR_BE_BS0			(0x01)
+#define GPIO_PAR_BE_BS1			(0x04)
+#define GPIO_PAR_BE_BS2(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_BE_BS3(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_BE_BE3_UNMASK		(0x3F)
+#define GPIO_PAR_BE_BE3_BE3		(0xC0)
+#define GPIO_PAR_BE_BE3_TSIZ1		(0x80)
+#define GPIO_PAR_BE_BE3_GPIO		(0x00)
+#define GPIO_PAR_BE_BE2_UNMASK		(0xCF)
+#define GPIO_PAR_BE_BE2_BE2		(0x30)
+#define GPIO_PAR_BE_BE2_TSIZ0		(0x20)
+#define GPIO_PAR_BE_BE2_GPIO		(0x00)
+#define GPIO_PAR_BE_BE1_BE1		(0x04)
+#define GPIO_PAR_BE_BE1_GPIO		(0x00)
+#define GPIO_PAR_BE_BE0_BE0		(0x01)
+#define GPIO_PAR_BE_BE0_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_CS */
+#define GPIO_PAR_CS_CS1			(0x02)
+#define GPIO_PAR_CS_CS2			(0x04)
+#define GPIO_PAR_CS_CS3			(0x08)
+#define GPIO_PAR_CS_CS3_CS3		(0x08)
+#define GPIO_PAR_CS_CS3_GPIO		(0x00)
+#define GPIO_PAR_CS_CS2_CS2		(0x04)
+#define GPIO_PAR_CS_CS2_GPIO		(0x00)
+#define GPIO_PAR_CS_CS1_CS1		(0x02)
+#define GPIO_PAR_CS_CS1_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_TIMER */
+#define GPIO_PAR_TIMER_T0IN(x)		(((x)&0x03))
+#define GPIO_PAR_TIMER_T1IN(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_TIMER_T2IN(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_T3IN(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_TIMER_T3IN_UNMASK	(0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
+#define GPIO_PAR_TIMER_T3IN_U2RXD	(0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T2IN_UNMASK	(0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
+#define GPIO_PAR_TIMER_T2IN_U2TXD	(0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T1IN_UNMASK	(0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
+#define GPIO_PAR_TIMER_T1IN_U2CTS	(0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T0IN_UNMASK	(0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
+#define GPIO_PAR_TIMER_T0IN_U2RTS	(0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO	(0x00)
+
+/* Bit definitions and macros for PAR_USB */
+#define GPIO_PAR_USB_VBUSOC(x)		(((x)&0x03))
+#define GPIO_PAR_USB_VBUSEN(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_USB_VBUSEN_UNMASK	(0xF3)
+#define GPIO_PAR_USB_VBUSEN_VBUSEN	(0x0C)
+#define GPIO_PAR_USB_VBUSEN_USBPULLUP	(0x08)
+#define GPIO_PAR_USB_VBUSEN_ULPI_NXT	(0x04)
+#define GPIO_PAR_USB_VBUSEN_GPIO	(0x00)
+#define GPIO_PAR_USB_VBUSOC_UNMASK	(0xFC)
+#define GPIO_PAR_USB_VBUSOC_VBUSOC	(0x03)
+#define GPIO_PAR_USB_VBUSOC_ULPI_STP	(0x01)
+#define GPIO_PAR_USB_VBUSOC_GPIO	(0x00)
+
+/* Bit definitions and macros for PAR_UART */
+#define GPIO_PAR_UART_U0TXD		(0x01)
+#define GPIO_PAR_UART_U0RXD		(0x02)
+#define GPIO_PAR_UART_U0RTS		(0x04)
+#define GPIO_PAR_UART_U0CTS		(0x08)
+#define GPIO_PAR_UART_U1TXD		(0x10)
+#define GPIO_PAR_UART_U1RXD		(0x20)
+#define GPIO_PAR_UART_U1RTS		(0x40)
+#define GPIO_PAR_UART_U1CTS		(0x80)
+#define GPIO_PAR_UART_U1CTS_U1CTS	(0x80)
+#define GPIO_PAR_UART_U1CTS_GPIO	(0x00)
+#define GPIO_PAR_UART_U1RTS_U1RTS	(0x40)
+#define GPIO_PAR_UART_U1RTS_GPIO	(0x00)
+#define GPIO_PAR_UART_U1RXD_U1RXD	(0x20)
+#define GPIO_PAR_UART_U1RXD_GPIO	(0x00)
+#define GPIO_PAR_UART_U1TXD_U1TXD	(0x10)
+#define GPIO_PAR_UART_U1TXD_GPIO	(0x00)
+#define GPIO_PAR_UART_U0CTS_U0CTS	(0x08)
+#define GPIO_PAR_UART_U0CTS_GPIO	(0x00)
+#define GPIO_PAR_UART_U0RTS_U0RTS	(0x04)
+#define GPIO_PAR_UART_U0RTS_GPIO	(0x00)
+#define GPIO_PAR_UART_U0RXD_U0RXD	(0x02)
+#define GPIO_PAR_UART_U0RXD_GPIO	(0x00)
+#define GPIO_PAR_UART_U0TXD_U0TXD	(0x01)
+#define GPIO_PAR_UART_U0TXD_GPIO	(0x00)
+
+/* Bit definitions and macros for PAR_FECI2C */
+#define GPIO_PAR_FECI2C_SDA(x)		(((x)&0x0003))
+#define GPIO_PAR_FECI2C_SCL(x)		(((x)&0x0003)<<2)
+#define GPIO_PAR_FECI2C_MDIO0		(0x0010)
+#define GPIO_PAR_FECI2C_MDC0		(0x0040)
+#define GPIO_PAR_FECI2C_MDIO1(x)	(((x)&0x0003)<<8)
+#define GPIO_PAR_FECI2C_MDC1(x)		(((x)&0x0003)<<10)
+#define GPIO_PAR_FECI2C_MDC1_UNMASK	(0xF3FF)
+#define GPIO_PAR_FECI2C_MDC1_MDC1	(0x0C00)
+#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR	(0x0800)
+#define GPIO_PAR_FECI2C_MDC1_GPIO	(0x0000)
+#define GPIO_PAR_FECI2C_MDIO1_UNMASK	(0xFCFF)
+#define GPIO_PAR_FECI2C_MDIO1_MDIO1	(0x0300)
+#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW	(0x0200)
+#define GPIO_PAR_FECI2C_MDIO1_GPIO	(0x0000)
+#define GPIO_PAR_FECI2C_MDC0_MDC0	(0x0040)
+#define GPIO_PAR_FECI2C_MDC0_GPIO	(0x0000)
+#define GPIO_PAR_FECI2C_MDIO0_MDIO0	(0x0010)
+#define GPIO_PAR_FECI2C_MDIO0_GPIO	(0x0000)
+#define GPIO_PAR_FECI2C_SCL_UNMASK	(0xFFF3)
+#define GPIO_PAR_FECI2C_SCL_SCL		(0x000C)
+#define GPIO_PAR_FECI2C_SCL_U2TXD	(0x0004)
+#define GPIO_PAR_FECI2C_SCL_GPIO	(0x0000)
+#define GPIO_PAR_FECI2C_SDA_UNMASK	(0xFFFC)
+#define GPIO_PAR_FECI2C_SDA_SDA		(0x0003)
+#define GPIO_PAR_FECI2C_SDA_U2RXD	(0x0001)
+#define GPIO_PAR_FECI2C_SDA_GPIO	(0x0000)
+
+/* Bit definitions and macros for PAR_SSI */
+#define GPIO_PAR_SSI_MCLK		(0x0001)
+#define GPIO_PAR_SSI_STXD(x)		(((x)&0x0003)<<2)
+#define GPIO_PAR_SSI_SRXD(x)		(((x)&0x0003)<<4)
+#define GPIO_PAR_SSI_FS(x)		(((x)&0x0003)<<6)
+#define GPIO_PAR_SSI_BCLK(x)		(((x)&0x0003)<<8)
+#define GPIO_PAR_SSI_BCLK_UNMASK	(0xFCFF)
+#define GPIO_PAR_SSI_BCLK_BCLK		(0x0300)
+#define GPIO_PAR_SSI_BCLK_U1CTS		(0x0200)
+#define GPIO_PAR_SSI_BCLK_GPIO		(0x0000)
+#define GPIO_PAR_SSI_FS_UNMASK		(0xFF3F)
+#define GPIO_PAR_SSI_FS_FS		(0x00C0)
+#define GPIO_PAR_SSI_FS_U1RTS		(0x0080)
+#define GPIO_PAR_SSI_FS_GPIO		(0x0000)
+#define GPIO_PAR_SSI_SRXD_UNMASK	(0xFFCF)
+#define GPIO_PAR_SSI_SRXD_SRXD		(0x0030)
+#define GPIO_PAR_SSI_SRXD_U1RXD		(0x0020)
+#define GPIO_PAR_SSI_SRXD_GPIO		(0x0000)
+#define GPIO_PAR_SSI_STXD_UNMASK	(0xFFF3)
+#define GPIO_PAR_SSI_STXD_STXD		(0x000C)
+#define GPIO_PAR_SSI_STXD_U1TXD		(0x0008)
+#define GPIO_PAR_SSI_STXD_GPIO		(0x0000)
+#define GPIO_PAR_SSI_MCLK_MCLK		(0x0001)
+#define GPIO_PAR_SSI_MCLK_GPIO		(0x0000)
+
+/* Bit definitions and macros for PAR_ATA */
+#define GPIO_PAR_ATA_IORDY		(0x0001)
+#define GPIO_PAR_ATA_DMARQ		(0x0002)
+#define GPIO_PAR_ATA_RESET		(0x0004)
+#define GPIO_PAR_ATA_DA0		(0x0020)
+#define GPIO_PAR_ATA_DA1		(0x0040)
+#define GPIO_PAR_ATA_DA2		(0x0080)
+#define GPIO_PAR_ATA_CS0		(0x0100)
+#define GPIO_PAR_ATA_CS1		(0x0200)
+#define GPIO_PAR_ATA_BUFEN		(0x0400)
+#define GPIO_PAR_ATA_BUFEN_BUFEN	(0x0400)
+#define GPIO_PAR_ATA_BUFEN_GPIO		(0x0000)
+#define GPIO_PAR_ATA_CS1_CS1		(0x0200)
+#define GPIO_PAR_ATA_CS1_GPIO		(0x0000)
+#define GPIO_PAR_ATA_CS0_CS0		(0x0100)
+#define GPIO_PAR_ATA_CS0_GPIO		(0x0000)
+#define GPIO_PAR_ATA_DA2_DA2		(0x0080)
+#define GPIO_PAR_ATA_DA2_GPIO		(0x0000)
+#define GPIO_PAR_ATA_DA1_DA1		(0x0040)
+#define GPIO_PAR_ATA_DA1_GPIO		(0x0000)
+#define GPIO_PAR_ATA_DA0_DA0		(0x0020)
+#define GPIO_PAR_ATA_DA0_GPIO		(0x0000)
+#define GPIO_PAR_ATA_RESET_RESET	(0x0004)
+#define GPIO_PAR_ATA_RESET_GPIO		(0x0000)
+#define GPIO_PAR_ATA_DMARQ_DMARQ	(0x0002)
+#define GPIO_PAR_ATA_DMARQ_GPIO		(0x0000)
+#define GPIO_PAR_ATA_IORDY_IORDY	(0x0001)
+#define GPIO_PAR_ATA_IORDY_GPIO		(0x0000)
+
+/* Bit definitions and macros for PAR_IRQ */
+#define GPIO_PAR_IRQ_IRQ1		(0x02)
+#define GPIO_PAR_IRQ_IRQ4		(0x10)
+#define GPIO_PAR_IRQ_IRQ4_IRQ4		(0x10)
+#define GPIO_PAR_IRQ_IRQ4_GPIO		(0x00)
+#define GPIO_PAR_IRQ_IRQ1_IRQ1		(0x02)
+#define GPIO_PAR_IRQ_IRQ1_GPIO		(0x00)
+
+/* Bit definitions and macros for PAR_PCI */
+#define GPIO_PAR_PCI_REQ0		(0x0001)
+#define GPIO_PAR_PCI_REQ1		(0x0004)
+#define GPIO_PAR_PCI_REQ2		(0x0010)
+#define GPIO_PAR_PCI_REQ3(x)		(((x)&0x0003)<<6)
+#define GPIO_PAR_PCI_GNT0		(0x0100)
+#define GPIO_PAR_PCI_GNT1		(0x0400)
+#define GPIO_PAR_PCI_GNT2		(0x1000)
+#define GPIO_PAR_PCI_GNT3(x)		(((x)&0x0003)<<14)
+#define GPIO_PAR_PCI_GNT3_UNMASK	(0x3FFF)
+#define GPIO_PAR_PCI_GNT3_GNT3		(0xC000)
+#define GPIO_PAR_PCI_GNT3_ATA_DMACK	(0x8000)
+#define GPIO_PAR_PCI_GNT3_GPIO		(0x0000)
+#define GPIO_PAR_PCI_GNT2_GNT2		(0x1000)
+#define GPIO_PAR_PCI_GNT2_GPIO		(0x0000)
+#define GPIO_PAR_PCI_GNT1_GNT1		(0x0400)
+#define GPIO_PAR_PCI_GNT1_GPIO		(0x0000)
+#define GPIO_PAR_PCI_GNT0_GNT0		(0x0100)
+#define GPIO_PAR_PCI_GNT0_GPIO		(0x0000)
+#define GPIO_PAR_PCI_REQ3_UNMASK	(0xFF3F)
+#define GPIO_PAR_PCI_REQ3_REQ3		(0x00C0)
+#define GPIO_PAR_PCI_REQ3_ATA_INTRQ	(0x0080)
+#define GPIO_PAR_PCI_REQ3_GPIO		(0x0000)
+#define GPIO_PAR_PCI_REQ2_REQ2		(0x0010)
+#define GPIO_PAR_PCI_REQ2_GPIO		(0x0000)
+#define GPIO_PAR_PCI_REQ1_REQ1		(0x0040)
+#define GPIO_PAR_PCI_REQ1_GPIO		(0x0000)
+#define GPIO_PAR_PCI_REQ0_REQ0		(0x0001)
+#define GPIO_PAR_PCI_REQ0_GPIO		(0x0000)
+
+/* Bit definitions and macros for MSCR_SDRAM */
+#define GPIO_MSCR_SDRAM_SDCTL(x)	(((x)&0x03))
+#define GPIO_MSCR_SDRAM_SDCLK(x)	(((x)&0x03)<<2)
+#define GPIO_MSCR_SDRAM_SDDQS(x)	(((x)&0x03)<<4)
+#define GPIO_MSCR_SDRAM_SDDATA(x)	(((x)&0x03)<<6)
+#define GPIO_MSCR_SDRAM_SDDATA_UNMASK	(0x3F)
+#define GPIO_MSCR_SDRAM_SDDATA_DDR1	(0xC0)
+#define GPIO_MSCR_SDRAM_SDDATA_DDR2	(0x80)
+#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR	(0x40)
+#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR	(0x00)
+#define GPIO_MSCR_SDRAM_SDDQS_UNMASK	(0xCF)
+#define GPIO_MSCR_SDRAM_SDDQS_DDR1	(0x30)
+#define GPIO_MSCR_SDRAM_SDDQS_DDR2	(0x20)
+#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR	(0x10)
+#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR	(0x00)
+#define GPIO_MSCR_SDRAM_SDCLK_UNMASK	(0xF3)
+#define GPIO_MSCR_SDRAM_SDCLK_DDR1	(0x0C)
+#define GPIO_MSCR_SDRAM_SDCLK_DDR2	(0x08)
+#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR	(0x04)
+#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR	(0x00)
+#define GPIO_MSCR_SDRAM_SDCTL_UNMASK	(0xFC)
+#define GPIO_MSCR_SDRAM_SDCTL_DDR1	(0x03)
+#define GPIO_MSCR_SDRAM_SDCTL_DDR2	(0x02)
+#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR	(0x01)
+#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR	(0x00)
+
+/* Bit definitions and macros for MSCR_PCI */
+#define GPIO_MSCR_PCI_PCI		(0x01)
+#define GPIO_MSCR_PCI_PCI_HI_66MHZ	(0x01)
+#define GPIO_MSCR_PCI_PCI_LO_33MHZ	(0x00)
+
+/* Bit definitions and macros for DSCR_I2C */
+#define GPIO_DSCR_I2C_I2C(x)		(((x)&0x03))
+#define GPIO_DSCR_I2C_I2C_LOAD_50PF	(0x03)
+#define GPIO_DSCR_I2C_I2C_LOAD_30PF	(0x02)
+#define GPIO_DSCR_I2C_I2C_LOAD_20PF	(0x01)
+#define GPIO_DSCR_I2C_I2C_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_FLEXBUS */
+#define GPIO_DSCR_FLEXBUS_FBADL(x)		(((x)&0x03))
+#define GPIO_DSCR_FLEXBUS_FBADH(x)		(((x)&0x03)<<2)
+#define GPIO_DSCR_FLEXBUS_FBCTL(x)		(((x)&0x03)<<4)
+#define GPIO_DSCR_FLEXBUS_FBCLK(x)		(((x)&0x03)<<6)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF	(0xC0)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF	(0x80)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF	(0x40)
+#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF	(0x00)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF	(0x30)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF	(0x20)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF	(0x10)
+#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF	(0x00)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF	(0x0C)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF	(0x08)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF	(0x04)
+#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF	(0x00)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF	(0x03)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF	(0x02)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF	(0x01)
+#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_FEC */
+#define GPIO_DSCR_FEC_FEC0(x)		(((x)&0x03))
+#define GPIO_DSCR_FEC_FEC1(x)		(((x)&0x03)<<2)
+#define GPIO_DSCR_FEC_FEC1_LOAD_50PF	(0x0C)
+#define GPIO_DSCR_FEC_FEC1_LOAD_30PF	(0x08)
+#define GPIO_DSCR_FEC_FEC1_LOAD_20PF	(0x04)
+#define GPIO_DSCR_FEC_FEC1_LOAD_10PF	(0x00)
+#define GPIO_DSCR_FEC_FEC0_LOAD_50PF	(0x03)
+#define GPIO_DSCR_FEC_FEC0_LOAD_30PF	(0x02)
+#define GPIO_DSCR_FEC_FEC0_LOAD_20PF	(0x01)
+#define GPIO_DSCR_FEC_FEC0_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_UART */
+#define GPIO_DSCR_UART_UART0(x)		(((x)&0x03))
+#define GPIO_DSCR_UART_UART1(x)		(((x)&0x03)<<2)
+#define GPIO_DSCR_UART_UART1_LOAD_50PF	(0x0C)
+#define GPIO_DSCR_UART_UART1_LOAD_30PF	(0x08)
+#define GPIO_DSCR_UART_UART1_LOAD_20PF	(0x04)
+#define GPIO_DSCR_UART_UART1_LOAD_10PF	(0x00)
+#define GPIO_DSCR_UART_UART0_LOAD_50PF	(0x03)
+#define GPIO_DSCR_UART_UART0_LOAD_30PF	(0x02)
+#define GPIO_DSCR_UART_UART0_LOAD_20PF	(0x01)
+#define GPIO_DSCR_UART_UART0_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_DSPI */
+#define GPIO_DSCR_DSPI_DSPI(x)		(((x)&0x03))
+#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF	(0x03)
+#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF	(0x02)
+#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF	(0x01)
+#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_TIMER */
+#define GPIO_DSCR_TIMER_TIMER(x)	(((x)&0x03))
+#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF	(0x03)
+#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF	(0x02)
+#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF	(0x01)
+#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_SSI */
+#define GPIO_DSCR_SSI_SSI(x)		(((x)&0x03))
+#define GPIO_DSCR_SSI_SSI_LOAD_50PF	(0x03)
+#define GPIO_DSCR_SSI_SSI_LOAD_30PF	(0x02)
+#define GPIO_DSCR_SSI_SSI_LOAD_20PF	(0x01)
+#define GPIO_DSCR_SSI_SSI_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_DMA */
+#define GPIO_DSCR_DMA_DMA(x)		(((x)&0x03))
+#define GPIO_DSCR_DMA_DMA_LOAD_50PF	(0x03)
+#define GPIO_DSCR_DMA_DMA_LOAD_30PF	(0x02)
+#define GPIO_DSCR_DMA_DMA_LOAD_20PF	(0x01)
+#define GPIO_DSCR_DMA_DMA_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_DEBUG */
+#define GPIO_DSCR_DEBUG_DEBUG(x)	(((x)&0x03))
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF	(0x03)
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF	(0x02)
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF	(0x01)
+#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_RESET */
+#define GPIO_DSCR_RESET_RESET(x)	(((x)&0x03))
+#define GPIO_DSCR_RESET_RESET_LOAD_50PF	(0x03)
+#define GPIO_DSCR_RESET_RESET_LOAD_30PF	(0x02)
+#define GPIO_DSCR_RESET_RESET_LOAD_20PF	(0x01)
+#define GPIO_DSCR_RESET_RESET_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_IRQ */
+#define GPIO_DSCR_IRQ_IRQ(x)		(((x)&0x03))
+#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF	(0x03)
+#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF	(0x02)
+#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF	(0x01)
+#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_USB */
+#define GPIO_DSCR_USB_USB(x)		(((x)&0x03))
+#define GPIO_DSCR_USB_USB_LOAD_50PF	(0x03)
+#define GPIO_DSCR_USB_USB_LOAD_30PF	(0x02)
+#define GPIO_DSCR_USB_USB_LOAD_20PF	(0x01)
+#define GPIO_DSCR_USB_USB_LOAD_10PF	(0x00)
+
+/* Bit definitions and macros for DSCR_ATA */
+#define GPIO_DSCR_ATA_ATA(x)		(((x)&0x03))
+#define GPIO_DSCR_ATA_ATA_LOAD_50PF	(0x03)
+#define GPIO_DSCR_ATA_ATA_LOAD_30PF	(0x02)
+#define GPIO_DSCR_ATA_ATA_LOAD_20PF	(0x01)
+#define GPIO_DSCR_ATA_ATA_LOAD_10PF	(0x00)
+
+/*********************************************************************
+* SDRAM Controller (SDRAMC)
+*********************************************************************/
+
+/* Bit definitions and macros for SDMR */
+#define SDRAMC_SDMR_DDR2_AD(x)		(((x)&0x00003FFF))	/* Address for DDR2 */
+#define SDRAMC_SDMR_CMD			(0x00010000)	/* Command */
+#define SDRAMC_SDMR_AD(x)		(((x)&0x00000FFF)<<18)	/* Address */
+#define SDRAMC_SDMR_BK(x)		(((x)&0x00000003)<<30)	/* Bank Address */
+#define SDRAMC_SDMR_BK_LMR		(0x00000000)
+#define SDRAMC_SDMR_BK_LEMR		(0x40000000)
+
+/* Bit definitions and macros for SDCR */
+#define SDRAMC_SDCR_DPD			(0x00000001)	/* Deep Power-Down Mode */
+#define SDRAMC_SDCR_IPALL		(0x00000002)	/* Initiate Precharge All */
+#define SDRAMC_SDCR_IREF		(0x00000004)	/* Initiate Refresh */
+#define SDRAMC_SDCR_DQS_OE(x)		(((x)&0x00000003)<<10)	/* DQS Output Enable */
+#define SDRAMC_SDCR_MEM_PS		(0x00002000)	/* Data Port Size */
+#define SDRAMC_SDCR_REF_CNT(x)		(((x)&0x0000003F)<<16)	/* Periodic Refresh Counter */
+#define SDRAMC_SDCR_OE_RULE		(0x00400000)	/* Drive Rule Selection */
+#define SDRAMC_SDCR_ADDR_MUX(x)		(((x)&0x00000003)<<24)	/* Internal Address Mux Select */
+#define SDRAMC_SDCR_DDR2_MODE		(0x08000000)	/* DDR2 Mode Select */
+#define SDRAMC_SDCR_REF_EN		(0x10000000)	/* Refresh Enable */
+#define SDRAMC_SDCR_DDR_MODE		(0x20000000)	/* DDR Mode Select */
+#define SDRAMC_SDCR_CKE			(0x40000000)	/* Clock Enable */
+#define SDRAMC_SDCR_MODE_EN		(0x80000000)	/* SDRAM Mode Register Programming Enable */
+#define SDRAMC_SDCR_DQS_OE_BOTH		(0x00000C000)
+
+/* Bit definitions and macros for SDCFG1 */
+#define SDRAMC_SDCFG1_WT_LAT(x)		(((x)&0x00000007)<<4)	/* Write Latency */
+#define SDRAMC_SDCFG1_REF2ACT(x)	(((x)&0x0000000F)<<8)	/* Refresh to active delay */
+#define SDRAMC_SDCFG1_PRE2ACT(x)	(((x)&0x00000007)<<12)	/* Precharge to active delay */
+#define SDRAMC_SDCFG1_ACT2RW(x)		(((x)&0x00000007)<<16)	/* Active to read/write delay */
+#define SDRAMC_SDCFG1_RD_LAT(x)		(((x)&0x0000000F)<<20)	/* Read CAS Latency */
+#define SDRAMC_SDCFG1_SWT2RWP(x)	(((x)&0x00000007)<<24)	/* Single write to read/write/precharge delay */
+#define SDRAMC_SDCFG1_SRD2RWP(x)	(((x)&0x0000000F)<<28)	/* Single read to read/write/precharge delay */
+
+/* Bit definitions and macros for SDCFG2 */
+#define SDRAMC_SDCFG2_BL(x)		(((x)&0x0000000F)<<16)	/* Burst Length */
+#define SDRAMC_SDCFG2_BRD2W(x)		(((x)&0x0000000F)<<20)	/* Burst read to write delay */
+#define SDRAMC_SDCFG2_BWT2RWP(x)	(((x)&0x0000000F)<<24)	/* Burst write to read/write/precharge delay */
+#define SDRAMC_SDCFG2_BRD2RP(x)		(((x)&0x0000000F)<<28)	/* Burst read to read/precharge delay */
+
+/* Bit definitions and macros for SDCS group */
+#define SDRAMC_SDCS_CSSZ(x)		(((x)&0x0000001F))	/* Chip-Select Size */
+#define SDRAMC_SDCS_CSBA(x)		(((x)&0x00000FFF)<<20)	/* Chip-Select Base Address */
+#define SDRAMC_SDCS_BA(x)		((x)&0xFFF00000)
+#define SDRAMC_SDCS_CSSZ_DISABLE	(0x00000000)
+#define SDRAMC_SDCS_CSSZ_1MBYTE		(0x00000013)
+#define SDRAMC_SDCS_CSSZ_2MBYTE		(0x00000014)
+#define SDRAMC_SDCS_CSSZ_4MBYTE		(0x00000015)
+#define SDRAMC_SDCS_CSSZ_8MBYTE		(0x00000016)
+#define SDRAMC_SDCS_CSSZ_16MBYTE	(0x00000017)
+#define SDRAMC_SDCS_CSSZ_32MBYTE	(0x00000018)
+#define SDRAMC_SDCS_CSSZ_64MBYTE	(0x00000019)
+#define SDRAMC_SDCS_CSSZ_128MBYTE	(0x0000001A)
+#define SDRAMC_SDCS_CSSZ_256MBYTE	(0x0000001B)
+#define SDRAMC_SDCS_CSSZ_512MBYTE	(0x0000001C)
+#define SDRAMC_SDCS_CSSZ_1GBYTE		(0x0000001D)
+#define SDRAMC_SDCS_CSSZ_2GBYTE		(0x0000001E)
+#define SDRAMC_SDCS_CSSZ_4GBYTE		(0x0000001F)
+
+/*********************************************************************
+* Phase Locked Loop (PLL)
+*********************************************************************/
+
+/* Bit definitions and macros for PCR */
+#define PLL_PCR_OUTDIV1(x)		(((x)&0x0000000F))	/* Output divider for CPU clock frequency */
+#define PLL_PCR_OUTDIV2(x)		(((x)&0x0000000F)<<4)	/* Output divider for internal bus clock frequency */
+#define PLL_PCR_OUTDIV3(x)		(((x)&0x0000000F)<<8)	/* Output divider for Flexbus clock frequency */
+#define PLL_PCR_OUTDIV4(x)		(((x)&0x0000000F)<<12)	/* Output divider for PCI clock frequency */
+#define PLL_PCR_OUTDIV5(x)		(((x)&0x0000000F)<<16)	/* Output divider for USB clock frequency */
+#define PLL_PCR_PFDR(x)			(((x)&0x000000FF)<<24)	/* Feedback divider for VCO frequency */
+#define PLL_PCR_PFDR_MASK		(0x000F0000)
+#define PLL_PCR_OUTDIV5_MASK		(0x000F0000)
+#define PLL_PCR_OUTDIV4_MASK		(0x0000F000)
+#define PLL_PCR_OUTDIV3_MASK		(0x00000F00)
+#define PLL_PCR_OUTDIV2_MASK		(0x000000F0)
+#define PLL_PCR_OUTDIV1_MASK		(0x0000000F)
+
+/* Bit definitions and macros for PSR */
+#define PLL_PSR_LOCKS			(0x00000001)	/* PLL lost lock - sticky */
+#define PLL_PSR_LOCK			(0x00000002)	/* PLL lock status */
+#define PLL_PSR_LOLIRQ			(0x00000004)	/* PLL loss-of-lock interrupt enable */
+#define PLL_PSR_LOLRE			(0x00000008)	/* PLL loss-of-lock reset enable */
+
+/*********************************************************************
+* PCI
+*********************************************************************/
+
+/* Bit definitions and macros for SCR */
+#define PCI_SCR_PE			(0x80000000)	/* Parity Error detected */
+#define PCI_SCR_SE			(0x40000000)	/* System error signalled */
+#define PCI_SCR_MA			(0x20000000)	/* Master aboart received */
+#define PCI_SCR_TR			(0x10000000)	/* Target abort received */
+#define PCI_SCR_TS			(0x08000000)	/* Target abort signalled */
+#define PCI_SCR_DT			(0x06000000)	/* PCI_DEVSEL timing */
+#define PCI_SCR_DP			(0x01000000)	/* Master data parity err */
+#define PCI_SCR_FC			(0x00800000)	/* Fast back-to-back */
+#define PCI_SCR_R			(0x00400000)	/* Reserved */
+#define PCI_SCR_66M			(0x00200000)	/* 66Mhz */
+#define PCI_SCR_C			(0x00100000)	/* Capabilities list */
+#define PCI_SCR_F			(0x00000200)	/* Fast back-to-back enable */
+#define PCI_SCR_S			(0x00000100)	/* SERR enable */
+#define PCI_SCR_ST			(0x00000080)	/* Addr and Data stepping */
+#define PCI_SCR_PER			(0x00000040)	/* Parity error response */
+#define PCI_SCR_V			(0x00000020)	/* VGA palette snoop enable */
+#define PCI_SCR_MW			(0x00000010)	/* Memory write and invalidate enable */
+#define PCI_SCR_SP			(0x00000008)	/* Special cycle monitor or ignore */
+#define PCI_SCR_B			(0x00000004)	/* Bus master enable */
+#define PCI_SCR_M			(0x00000002)	/* Memory access control */
+#define PCI_SCR_IO			(0x00000001)	/* I/O access control */
+
+#define PCI_CR1_BIST(x)			((x & 0xFF) << 24)	/* Built in self test */
+#define PCI_CR1_HDR(x)			((x & 0xFF) << 16)	/* Header type */
+#define PCI_CR1_LTMR(x)			((x & 0xF8) << 8)	/* Latency timer */
+#define PCI_CR1_CLS(x)			(x & 0x0F)	/* Cache line size */
+
+#define PCI_BAR_BAR0(x)			(x & 0xFFFC0000)
+#define PCI_BAR_BAR1(x)			(x & 0xFFF00000)
+#define PCI_BAR_BAR2(x)			(x & 0xFFC00000)
+#define PCI_BAR_BAR3(x)			(x & 0xFF000000)
+#define PCI_BAR_BAR4(x)			(x & 0xF8000000)
+#define PCI_BAR_BAR5(x)			(x & 0xE0000000)
+#define PCI_BAR_PREF			(0x00000004)	/* Prefetchable access */
+#define PCI_BAR_RANGE			(0x00000002)	/* Fixed to 00 */
+#define PCI_BAR_IO_M			(0x00000001)	/* IO / memory space */
+
+#define PCI_CR2_MAXLAT(x)		((x & 0xFF) << 24)	/* Maximum latency */
+#define PCI_CR2_MINGNT(x)		((x & 0xFF) << 16)	/* Minimum grant */
+#define PCI_CR2_INTPIN(x)		((x & 0xFF) << 8)	/* Interrupt Pin */
+#define PCI_CR2_INTLIN(x)		(x & 0xFF)	/* Interrupt Line */
+
+#define PCI_GSCR_DRD			(0x80000000)	/* Delayed read discarded */
+#define PCI_GSCR_PE			(0x20000000)	/* PCI_PERR detected */
+#define PCI_GSCR_SE			(0x10000000)	/* SERR detected */
+#define PCI_GSCR_ER			(0x08000000)	/* Error response detected */
+#define PCI_GSCR_DRDE			(0x00008000)	/* Delayed read discarded enable */
+#define PCI_GSCR_PEE			(0x00002000)	/* PERR detected interrupt enable */
+#define PCI_GSCR_SEE			(0x00001000)	/* SERR detected interrupt enable */
+#define PCI_GSCR_PR			(0x00000001)	/* PCI reset */
+
+#define PCI_TCR1_LD			(0x01000000)	/* Latency rule disable */
+#define PCI_TCR1_PID			(0x00020000)	/* Prefetch invalidate and disable */
+#define PCI_TCR1_P			(0x00010000)	/* Prefetch reads */
+#define PCI_TCR1_WCD			(0x00000100)	/* Write combine disable */
+
+#define PCI_TCR2_B5E			(0x00002000)	/*  */
+#define PCI_TCR2_B4E			(0x00001000)	/*  */
+#define PCI_TCR2_B3E			(0x00000800)	/*  */
+#define PCI_TCR2_B2E			(0x00000400)	/*  */
+#define PCI_TCR2_B1E			(0x00000200)	/*  */
+#define PCI_TCR2_B0E			(0x00000100)	/*  */
+#define PCI_TCR2_CR			(0x00000001)	/*  */
+
+#define PCI_TBATR_BAT(x)		((x & 0xFFF) << 20)
+#define PCI_TBATR_EN			(0x00000001)	/* Enable */
+
+#define PCI_IWCR_W0C_IO			(0x08000000)	/* Windows Maps to PCI I/O */
+#define PCI_IWCR_W0C_PRC_RDMUL		(0x04000000)	/* PCI Memory Read multiple */
+#define PCI_IWCR_W0C_PRC_RDLN		(0x02000000)	/* PCI Memory Read line */
+#define PCI_IWCR_W0C_PRC_RD		(0x00000000)	/* PCI Memory Read */
+#define PCI_IWCR_W0C_EN			(0x01000000)	/* Enable - Register initialize */
+#define PCI_IWCR_W1C_IO			(0x00080000)	/* Windows Maps to PCI I/O */
+#define PCI_IWCR_W1C_PRC_RDMUL		(0x00040000)	/* PCI Memory Read multiple */
+#define PCI_IWCR_W1C_PRC_RDLN		(0x00020000)	/* PCI Memory Read line */
+#define PCI_IWCR_W1C_PRC_RD		(0x00000000)	/* PCI Memory Read */
+#define PCI_IWCR_W1C_EN			(0x00010000)	/* Enable - Register initialize */
+#define PCI_IWCR_W2C_IO			(0x00000800)	/* Windows Maps to PCI I/O */
+#define PCI_IWCR_W2C_PRC_RDMUL		(0x00000400)	/* PCI Memory Read multiple */
+#define PCI_IWCR_W2C_PRC_RDLN		(0x00000200)	/* PCI Memory Read line */
+#define PCI_IWCR_W2C_PRC_RD		(0x00000000)	/* PCI Memory Read */
+#define PCI_IWCR_W2C_EN			(0x00000100)	/* Enable - Register initialize */
+
+#define PCI_ICR_REE			(0x04000000)	/* Retry error enable */
+#define PCI_ICR_IAE			(0x02000000)	/* Initiator abort enable */
+#define PCI_ICR_TAE			(0x01000000)	/* Target abort enable */
+#define PCI_ICR_MAXRETRY(x)		((x) & 0x000000FF)
+
+/********************************************************************/
+
+#endif				/* __MCF5445X__ */
diff --git a/arch/m68k/include/asm/m547x_8x.h b/arch/m68k/include/asm/m547x_8x.h
new file mode 100644
index 0000000..30f1200
--- /dev/null
+++ b/arch/m68k/include/asm/m547x_8x.h
@@ -0,0 +1,417 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef mcf547x_8x_h
+#define mcf547x_8x_h
+
+/*********************************************************************
+* XLB Arbiter (XLB)
+*********************************************************************/
+/* Bit definitions and macros for XARB_CFG */
+#define XARB_CFG_AT			(0x00000002)
+#define XARB_CFG_DT			(0x00000004)
+#define XARB_CFG_BA			(0x00000008)
+#define XARB_CFG_PM(x)			(((x)&0x00000003)<<5)
+#define XARB_CFG_SP(x)			(((x)&0x00000007)<<8)
+#define XARB_CFG_PLDIS			(0x80000000)
+
+/* Bit definitions and macros for XARB_SR */
+#define XARB_SR_AT			(0x00000001)
+#define XARB_SR_DT			(0x00000002)
+#define XARB_SR_BA			(0x00000004)
+#define XARB_SR_TTM			(0x00000008)
+#define XARB_SR_ECW			(0x00000010)
+#define XARB_SR_TTR			(0x00000020)
+#define XARB_SR_TTA			(0x00000040)
+#define XARB_SR_MM			(0x00000080)
+#define XARB_SR_SEA			(0x00000100)
+
+/* Bit definitions and macros for XARB_IMR */
+#define XARB_IMR_ATE			(0x00000001)
+#define XARB_IMR_DTE			(0x00000002)
+#define XARB_IMR_BAE			(0x00000004)
+#define XARB_IMR_TTME			(0x00000008)
+#define XARB_IMR_ECWE			(0x00000010)
+#define XARB_IMR_TTRE			(0x00000020)
+#define XARB_IMR_TTAE			(0x00000040)
+#define XARB_IMR_MME			(0x00000080)
+#define XARB_IMR_SEAE			(0x00000100)
+
+/* Bit definitions and macros for XARB_SIGCAP */
+#define XARB_SIGCAP_TT(x)		((x)&0x0000001F)
+#define XARB_SIGCAP_TBST		(0x00000020)
+#define XARB_SIGCAP_TSIZ(x)		(((x)&0x00000007)<<7)
+
+/* Bit definitions and macros for XARB_PRIEN */
+#define XARB_PRIEN_M0			(0x00000001)
+#define XARB_PRIEN_M2			(0x00000004)
+#define XARB_PRIEN_M3			(0x00000008)
+
+/* Bit definitions and macros for XARB_PRI */
+#define XARB_PRI_M0P(x)			(((x)&0x00000007)<<0)
+#define XARB_PRI_M2P(x)			(((x)&0x00000007)<<8)
+#define XARB_PRI_M3P(x)			(((x)&0x00000007)<<12)
+
+/*********************************************************************
+* General Purpose I/O (GPIO)
+*********************************************************************/
+/* Bit definitions and macros for GPIO_PAR_FBCTL */
+#define GPIO_PAR_FBCTL_TS(x)		(((x)&0x0003)<<0)
+#define GPIO_PAR_FBCTL_TA		(0x0004)
+#define GPIO_PAR_FBCTL_RWB(x)		(((x)&0x0003)<<4)
+#define GPIO_PAR_FBCTL_OE		(0x0040)
+#define GPIO_PAR_FBCTL_BWE0		(0x0100)
+#define GPIO_PAR_FBCTL_BWE1		(0x0400)
+#define GPIO_PAR_FBCTL_BWE2		(0x1000)
+#define GPIO_PAR_FBCTL_BWE3		(0x4000)
+#define GPIO_PAR_FBCTL_TS_GPIO		(0)
+#define GPIO_PAR_FBCTL_TS_TBST		(2)
+#define GPIO_PAR_FBCTL_TS_TS		(3)
+#define GPIO_PAR_FBCTL_RWB_GPIO		(0x0000)
+#define GPIO_PAR_FBCTL_RWB_TBST		(0x0020)
+#define GPIO_PAR_FBCTL_RWB_RWB		(0x0030)
+
+/* Bit definitions and macros for GPIO_PAR_FBCS */
+#define GPIO_PAR_FBCS_CS1		(0x02)
+#define GPIO_PAR_FBCS_CS2		(0x04)
+#define GPIO_PAR_FBCS_CS3		(0x08)
+#define GPIO_PAR_FBCS_CS4		(0x10)
+#define GPIO_PAR_FBCS_CS5		(0x20)
+
+/* Bit definitions and macros for GPIO_PAR_DMA */
+#define GPIO_PAR_DMA_DREQ0(x)		(((x)&0x03)<<0)
+#define GPIO_PAR_DMA_DREQ1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_DMA_DACK0(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_DMA_DACK1(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_DMA_DACKx_GPIO		(0)
+#define GPIO_PAR_DMA_DACKx_TOUT		(2)
+#define GPIO_PAR_DMA_DACKx_DACK		(3)
+#define GPIO_PAR_DMA_DREQx_GPIO		(0)
+#define GPIO_PAR_DMA_DREQx_TIN		(2)
+#define GPIO_PAR_DMA_DREQx_DREQ		(3)
+
+/* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */
+#define GPIO_PAR_FECI2CIRQ_IRQ5		(0x0001)
+#define GPIO_PAR_FECI2CIRQ_IRQ6		(0x0002)
+#define GPIO_PAR_FECI2CIRQ_SCL		(0x0004)
+#define GPIO_PAR_FECI2CIRQ_SDA		(0x0008)
+#define GPIO_PAR_FECI2CIRQ_E1MDC(x)	(((x)&0x0003)<<6)
+#define GPIO_PAR_FECI2CIRQ_E1MDIO(x)	(((x)&0x0003)<<8)
+#define GPIO_PAR_FECI2CIRQ_E1MII	(0x0400)
+#define GPIO_PAR_FECI2CIRQ_E17		(0x0800)
+#define GPIO_PAR_FECI2CIRQ_E0MDC	(0x1000)
+#define GPIO_PAR_FECI2CIRQ_E0MDIO	(0x2000)
+#define GPIO_PAR_FECI2CIRQ_E0MII	(0x4000)
+#define GPIO_PAR_FECI2CIRQ_E07		(0x8000)
+#define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX	(0x0000)
+#define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA	(0x0200)
+#define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO	(0x0300)
+#define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX	(0x0000)
+#define GPIO_PAR_FECI2CIRQ_E1MDC_SCL	(0x0080)
+#define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC	(0x00C0)
+
+/* Bit definitions and macros for GPIO_PAR_PCIBG */
+#define GPIO_PAR_PCIBG_PCIBG0(x)	(((x)&0x0003)<<0)
+#define GPIO_PAR_PCIBG_PCIBG1(x)	(((x)&0x0003)<<2)
+#define GPIO_PAR_PCIBG_PCIBG2(x)	(((x)&0x0003)<<4)
+#define GPIO_PAR_PCIBG_PCIBG3(x)	(((x)&0x0003)<<6)
+#define GPIO_PAR_PCIBG_PCIBG4(x)	(((x)&0x0003)<<8)
+
+/* Bit definitions and macros for GPIO_PAR_PCIBR */
+#define GPIO_PAR_PCIBR_PCIBR0(x)	(((x)&0x0003)<<0)
+#define GPIO_PAR_PCIBR_PCIBR1(x)	(((x)&0x0003)<<2)
+#define GPIO_PAR_PCIBR_PCIBR2(x)	(((x)&0x0003)<<4)
+#define GPIO_PAR_PCIBR_PCIBR3(x)	(((x)&0x0003)<<6)
+#define GPIO_PAR_PCIBR_PCIBR4(x)	(((x)&0x0003)<<8)
+
+/* Bit definitions and macros for GPIO_PAR_PSC3 */
+#define GPIO_PAR_PSC3_TXD3		(0x04)
+#define GPIO_PAR_PSC3_RXD3		(0x08)
+#define GPIO_PAR_PSC3_RTS3(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_PSC3_CTS3(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_PSC3_CTS3_GPIO		(0x00)
+#define GPIO_PAR_PSC3_CTS3_BCLK		(0x80)
+#define GPIO_PAR_PSC3_CTS3_CTS		(0xC0)
+#define GPIO_PAR_PSC3_RTS3_GPIO		(0x00)
+#define GPIO_PAR_PSC3_RTS3_FSYNC	(0x20)
+#define GPIO_PAR_PSC3_RTS3_RTS		(0x30)
+#define GPIO_PAR_PSC3_CTS2_CANRX	(0x40)
+
+/* Bit definitions and macros for GPIO_PAR_PSC2 */
+#define GPIO_PAR_PSC2_TXD2		(0x04)
+#define GPIO_PAR_PSC2_RXD2		(0x08)
+#define GPIO_PAR_PSC2_RTS2(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_PSC2_CTS2(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_PSC2_CTS2_GPIO		(0x00)
+#define GPIO_PAR_PSC2_CTS2_BCLK		(0x80)
+#define GPIO_PAR_PSC2_CTS2_CTS		(0xC0)
+#define GPIO_PAR_PSC2_RTS2_GPIO		(0x00)
+#define GPIO_PAR_PSC2_RTS2_CANTX	(0x10)
+#define GPIO_PAR_PSC2_RTS2_FSYNC	(0x20)
+#define GPIO_PAR_PSC2_RTS2_RTS		(0x30)
+
+/* Bit definitions and macros for GPIO_PAR_PSC1 */
+#define GPIO_PAR_PSC1_TXD1		(0x04)
+#define GPIO_PAR_PSC1_RXD1		(0x08)
+#define GPIO_PAR_PSC1_RTS1(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_PSC1_CTS1(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_PSC1_CTS1_GPIO		(0x00)
+#define GPIO_PAR_PSC1_CTS1_BCLK		(0x80)
+#define GPIO_PAR_PSC1_CTS1_CTS		(0xC0)
+#define GPIO_PAR_PSC1_RTS1_GPIO		(0x00)
+#define GPIO_PAR_PSC1_RTS1_FSYNC	(0x20)
+#define GPIO_PAR_PSC1_RTS1_RTS		(0x30)
+
+/* Bit definitions and macros for GPIO_PAR_PSC0 */
+#define GPIO_PAR_PSC0_TXD0		(0x04)
+#define GPIO_PAR_PSC0_RXD0		(0x08)
+#define GPIO_PAR_PSC0_RTS0(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_PSC0_CTS0(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_PSC0_CTS0_GPIO		(0x00)
+#define GPIO_PAR_PSC0_CTS0_BCLK		(0x80)
+#define GPIO_PAR_PSC0_CTS0_CTS		(0xC0)
+#define GPIO_PAR_PSC0_RTS0_GPIO		(0x00)
+#define GPIO_PAR_PSC0_RTS0_FSYNC	(0x20)
+#define GPIO_PAR_PSC0_RTS0_RTS		(0x30)
+
+/* Bit definitions and macros for GPIO_PAR_DSPI */
+#define GPIO_PAR_DSPI_SOUT(x)		(((x)&0x0003)<<0)
+#define GPIO_PAR_DSPI_SIN(x)		(((x)&0x0003)<<2)
+#define GPIO_PAR_DSPI_SCK(x)		(((x)&0x0003)<<4)
+#define GPIO_PAR_DSPI_CS0(x)		(((x)&0x0003)<<6)
+#define GPIO_PAR_DSPI_CS2(x)		(((x)&0x0003)<<8)
+#define GPIO_PAR_DSPI_CS3(x)		(((x)&0x0003)<<10)
+#define GPIO_PAR_DSPI_CS5		(0x1000)
+#define GPIO_PAR_DSPI_CS3_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_CS3_CANTX		(0x0400)
+#define GPIO_PAR_DSPI_CS3_TOUT		(0x0800)
+#define GPIO_PAR_DSPI_CS3_DSPICS	(0x0C00)
+#define GPIO_PAR_DSPI_CS2_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_CS2_CANTX		(0x0100)
+#define GPIO_PAR_DSPI_CS2_TOUT		(0x0200)
+#define GPIO_PAR_DSPI_CS2_DSPICS	(0x0300)
+#define GPIO_PAR_DSPI_CS0_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_CS0_FSYNC		(0x0040)
+#define GPIO_PAR_DSPI_CS0_RTS		(0x0080)
+#define GPIO_PAR_DSPI_CS0_DSPICS	(0x00C0)
+#define GPIO_PAR_DSPI_SCK_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_SCK_BCLK		(0x0010)
+#define GPIO_PAR_DSPI_SCK_CTS		(0x0020)
+#define GPIO_PAR_DSPI_SCK_SCK		(0x0030)
+#define GPIO_PAR_DSPI_SIN_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_SIN_RXD		(0x0008)
+#define GPIO_PAR_DSPI_SIN_SIN		(0x000C)
+#define GPIO_PAR_DSPI_SOUT_GPIO		(0x0000)
+#define GPIO_PAR_DSPI_SOUT_TXD		(0x0002)
+#define GPIO_PAR_DSPI_SOUT_SOUT		(0x0003)
+
+/* Bit definitions and macros for GPIO_PAR_TIMER */
+#define GPIO_PAR_TIMER_TOUT2		(0x01)
+#define GPIO_PAR_TIMER_TIN2(x)		(((x)&0x03)<<1)
+#define GPIO_PAR_TIMER_TOUT3		(0x08)
+#define GPIO_PAR_TIMER_TIN3(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_TIN3_CANRX	(0x00)
+#define GPIO_PAR_TIMER_TIN3_IRQ		(0x20)
+#define GPIO_PAR_TIMER_TIN3_TIN		(0x30)
+#define GPIO_PAR_TIMER_TIN2_CANRX	(0x00)
+#define GPIO_PAR_TIMER_TIN2_IRQ		(0x04)
+#define GPIO_PAR_TIMER_TIN2_TIN		(0x06)
+
+/*********************************************************************
+* Slice Timer (SLT)
+*********************************************************************/
+#define SLT_CR_RUN			(0x04000000)
+#define SLT_CR_IEN			(0x02000000)
+#define SLT_CR_TEN			(0x01000000)
+
+#define SLT_SR_BE			(0x02000000)
+#define SLT_SR_ST			(0x01000000)
+
+/*********************************************************************
+* Interrupt Controller (INTC)
+*********************************************************************/
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_EP0ISR			(15)
+#define INT0_LO_EP1ISR			(16)
+#define INT0_LO_EP2ISR			(17)
+#define INT0_LO_EP3ISR			(18)
+#define INT0_LO_EP4ISR			(19)
+#define INT0_LO_EP5ISR			(20)
+#define INT0_LO_EP6ISR			(21)
+#define INT0_LO_USBISR			(22)
+#define INT0_LO_USBAISR			(23)
+#define INT0_LO_USB			(24)
+#define INT1_LO_DSPI_RFOF_TFUF		(25)
+#define INT1_LO_DSPI_RFOF		(26)
+#define INT1_LO_DSPI_RFDF		(27)
+#define INT1_LO_DSPI_TFUF		(28)
+#define INT1_LO_DSPI_TCF		(29)
+#define INT1_LO_DSPI_TFFF		(30)
+#define INT1_LO_DSPI_EOQF		(31)
+
+#define INT0_HI_UART3			(32)
+#define INT0_HI_UART2			(33)
+#define INT0_HI_UART1			(34)
+#define INT0_HI_UART0			(35)
+#define INT0_HI_COMMTIM_TC		(36)
+#define INT0_HI_SEC			(37)
+#define INT0_HI_FEC1			(38)
+#define INT0_HI_FEC0			(39)
+#define INT0_HI_I2C			(40)
+#define INT0_HI_PCIARB			(41)
+#define INT0_HI_CBPCI			(42)
+#define INT0_HI_XLBPCI			(43)
+#define INT0_HI_XLBARB			(47)
+#define INT0_HI_DMA			(48)
+#define INT0_HI_CAN0_ERROR		(49)
+#define INT0_HI_CAN0_BUSOFF		(50)
+#define INT0_HI_CAN0_MBOR		(51)
+#define INT0_HI_SLT1			(53)
+#define INT0_HI_SLT0			(54)
+#define INT0_HI_CAN1_ERROR		(55)
+#define INT0_HI_CAN1_BUSOFF		(56)
+#define INT0_HI_CAN1_MBOR		(57)
+#define INT0_HI_GPT3			(59)
+#define INT0_HI_GPT2			(60)
+#define INT0_HI_GPT1			(61)
+#define INT0_HI_GPT0			(62)
+
+/*********************************************************************
+* General Purpose Timers (GPTMR)
+*********************************************************************/
+/* Enable and Mode Select */
+#define GPT_OCT(x)			(x & 0x3)<<4	/* Output Compare Type */
+#define GPT_ICT(x)			(x & 0x3)	/* Input Capture Type */
+#define GPT_CTRL_WDEN			0x80		/* Watchdog Enable */
+#define GPT_CTRL_CE			0x10		/* Counter Enable */
+#define GPT_CTRL_STPCNT			0x04		/* Stop continous */
+#define GPT_CTRL_ODRAIN			0x02		/* Open Drain */
+#define GPT_CTRL_INTEN			0x01		/* Interrupt Enable */
+#define GPT_MODE_GPIO(x)		(x & 0x3)<<4	/* Gpio Mode Type */
+#define GPT_TMS_ICT			0x01		/* Input Capture Enable */
+#define GPT_TMS_OCT			0x02		/* Output Capture Enable */
+#define GPT_TMS_PWM			0x03		/* PWM Capture Enable */
+#define GPT_TMS_SGPIO			0x04		/* PWM Capture Enable */
+
+#define GPT_PWM_WIDTH(x)		(x & 0xffff)
+
+/* Status */
+#define GPT_STA_CAPTURE(x)		(x & 0xffff)
+
+#define GPT_OVFPIN_OVF(x)		(x & 0x70)
+#define GPT_OVFPIN_PIN			0x01
+
+#define GPT_INT_TEXP			0x08
+#define GPT_INT_PWMP			0x04
+#define GPT_INT_COMP			0x02
+#define GPT_INT_CAPT			0x01
+
+/*********************************************************************
+* PCI
+*********************************************************************/
+
+/* Bit definitions and macros for SCR */
+#define PCI_SCR_PE			(0x80000000)	/* Parity Error detected */
+#define PCI_SCR_SE			(0x40000000)	/* System error signalled */
+#define PCI_SCR_MA			(0x20000000)	/* Master aboart received */
+#define PCI_SCR_TR			(0x10000000)	/* Target abort received */
+#define PCI_SCR_TS			(0x08000000)	/* Target abort signalled */
+#define PCI_SCR_DT			(0x06000000)	/* PCI_DEVSEL timing */
+#define PCI_SCR_DP			(0x01000000)	/* Master data parity err */
+#define PCI_SCR_FC			(0x00800000)	/* Fast back-to-back */
+#define PCI_SCR_R			(0x00400000)	/* Reserved */
+#define PCI_SCR_66M			(0x00200000)	/* 66Mhz */
+#define PCI_SCR_C			(0x00100000)	/* Capabilities list */
+#define PCI_SCR_F			(0x00000200)	/* Fast back-to-back enable */
+#define PCI_SCR_S			(0x00000100)	/* SERR enable */
+#define PCI_SCR_ST			(0x00000080)	/* Addr and Data stepping */
+#define PCI_SCR_PER			(0x00000040)	/* Parity error response */
+#define PCI_SCR_V			(0x00000020)	/* VGA palette snoop enable */
+#define PCI_SCR_MW			(0x00000010)	/* Memory write and invalidate enable */
+#define PCI_SCR_SP			(0x00000008)	/* Special cycle monitor or ignore */
+#define PCI_SCR_B			(0x00000004)	/* Bus master enable */
+#define PCI_SCR_M			(0x00000002)	/* Memory access control */
+#define PCI_SCR_IO			(0x00000001)	/* I/O access control */
+
+#define PCI_CR1_BIST(x)			((x & 0xFF) << 24)	/* Built in self test */
+#define PCI_CR1_HDR(x)			((x & 0xFF) << 16)	/* Header type */
+#define PCI_CR1_LTMR(x)			((x & 0xF8) << 8)	/* Latency timer */
+#define PCI_CR1_CLS(x)			(x & 0x0F)		/* Cache line size */
+
+#define PCI_BAR_BAR0(x)			(x & 0xFFFC0000)
+#define PCI_BAR_BAR1(x)			(x & 0xC0000000)
+#define PCI_BAR_PREF			(0x00000004)	/* Prefetchable access */
+#define PCI_BAR_RANGE			(0x00000002)	/* Fixed to 00 */
+#define PCI_BAR_IO_M			(0x00000001)	/* IO / memory space */
+
+#define PCI_CR2_MAXLAT(x)		((x & 0xFF) << 24)	/* Maximum latency */
+#define PCI_CR2_MINGNT(x)		((x & 0xFF) << 16)	/* Minimum grant */
+#define PCI_CR2_INTPIN(x)		((x & 0xFF) << 8)	/* Interrupt Pin */
+#define PCI_CR2_INTLIN(x)		(x & 0xFF)	/* Interrupt Line */
+
+#define PCI_GSCR_DRD			(0x80000000)	/* Delayed read discarded */
+#define PCI_GSCR_PE			(0x20000000)	/* PCI_PERR detected */
+#define PCI_GSCR_SE			(0x10000000)	/* SERR detected */
+#define PCI_GSCR_ER			(0x08000000)	/* Error response detected */
+#define PCI_GSCR_DRDE			(0x00008000)	/* Delayed read discarded enable */
+#define PCI_GSCR_PEE			(0x00002000)	/* PERR detected interrupt enable */
+#define PCI_GSCR_SEE			(0x00001000)	/* SERR detected interrupt enable */
+#define PCI_GSCR_PR			(0x00000001)	/* PCI reset */
+
+#define PCI_TCR1_LD			(0x01000000)	/* Latency rule disable */
+#define PCI_TCR1_PID			(0x00020000)	/* Prefetch invalidate and disable */
+#define PCI_TCR1_P			(0x00010000)	/* Prefetch reads */
+#define PCI_TCR1_WCD			(0x00000100)	/* Write combine disable */
+
+#define PCI_TCR1_B5E			(0x00002000)	/*  */
+#define PCI_TCR1_B4E			(0x00001000)	/*  */
+#define PCI_TCR1_B3E			(0x00000800)	/*  */
+#define PCI_TCR1_B2E			(0x00000400)	/*  */
+#define PCI_TCR1_B1E			(0x00000200)	/*  */
+#define PCI_TCR1_B0E			(0x00000100)	/*  */
+#define PCI_TCR1_CR			(0x00000001)	/*  */
+
+#define PCI_TBATR_BAT0(x)		(x & 0xFFFC0000)
+#define PCI_TBATR_BAT1(x)		(x & 0xC0000000)
+#define PCI_TBATR_EN			(0x00000001)	/* Enable */
+
+#define PCI_IWCR_W0C_IO			(0x08000000)	/* Windows Maps to PCI I/O */
+#define PCI_IWCR_W0C_PRC_RDMUL		(0x04000000)	/* PCI Memory Read multiple */
+#define PCI_IWCR_W0C_PRC_RDLN		(0x02000000)	/* PCI Memory Read line */
+#define PCI_IWCR_W0C_PRC_RD		(0x00000000)	/* PCI Memory Read */
+#define PCI_IWCR_W0C_EN			(0x01000000)	/* Enable - Register initialize */
+#define PCI_IWCR_W1C_IO			(0x00080000)	/* Windows Maps to PCI I/O */
+#define PCI_IWCR_W1C_PRC_RDMUL		(0x00040000)	/* PCI Memory Read multiple */
+#define PCI_IWCR_W1C_PRC_RDLN		(0x00020000)	/* PCI Memory Read line */
+#define PCI_IWCR_W1C_PRC_RD		(0x00000000)	/* PCI Memory Read */
+#define PCI_IWCR_W1C_EN			(0x00010000)	/* Enable - Register initialize */
+#define PCI_IWCR_W2C_IO			(0x00000800)	/* Windows Maps to PCI I/O */
+#define PCI_IWCR_W2C_PRC_RDMUL		(0x00000400)	/* PCI Memory Read multiple */
+#define PCI_IWCR_W2C_PRC_RDLN		(0x00000200)	/* PCI Memory Read line */
+#define PCI_IWCR_W2C_PRC_RD		(0x00000000)	/* PCI Memory Read */
+#define PCI_IWCR_W2C_EN			(0x00000100)	/* Enable - Register initialize */
+
+#define PCI_ICR_REE			(0x04000000)	/* Retry error enable */
+#define PCI_ICR_IAE			(0x02000000)	/* Initiator abort enable */
+#define PCI_ICR_TAE			(0x01000000)	/* Target abort enable */
+#define PCI_ICR_MAXRETRY(x)		((x) & 0x000000FF)
+
+#define PCIARB_ACR_DS			(0x80000000)
+#define PCIARB_ARC_EXTMINTEN(x)		(((x)&0x1F) << 17)
+#define PCIARB_ARC_INTMINTEN		(0x00010000)
+#define PCIARB_ARC_EXTMPRI(x)		(((x)&0x1F) << 1)
+#define PCIARB_ARC_INTMPRI		(0x00000001)
+
+#endif				/* mcf547x_8x_h */
diff --git a/arch/m68k/include/asm/posix_types.h b/arch/m68k/include/asm/posix_types.h
new file mode 100644
index 0000000..4fbc040
--- /dev/null
+++ b/arch/m68k/include/asm/posix_types.h
@@ -0,0 +1,109 @@
+#ifndef _M68K_POSIX_TYPES_H
+#define _M68K_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned int	__kernel_dev_t;
+typedef unsigned int	__kernel_ino_t;
+typedef unsigned int	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned int	__kernel_uid_t;
+typedef unsigned int	__kernel_gid_t;
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef long		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef short             __kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned int	__kernel_old_uid_t;
+typedef unsigned int	__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+	int	val[2];
+} __kernel_fsid_t;
+
+#ifndef __GNUC__
+
+#define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+#define	__FD_CLR(d, set)	((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+#define	__FD_ISSET(d, set)	((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+#define	__FD_ZERO(set)	\
+  ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
+
+#else /* __GNUC__ */
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
+    || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
+/* With GNU C, use inline functions instead so args are evaluated only once: */
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *p)
+{
+	unsigned int *tmp = (unsigned int *)p->fds_bits;
+	int i;
+
+	if (__builtin_constant_p(__FDSET_LONGS)) {
+		switch (__FDSET_LONGS) {
+			case 8:
+				tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
+				tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
+				return;
+		}
+	}
+	i = __FDSET_LONGS;
+	while (i) {
+		i--;
+		*tmp = 0;
+		tmp++;
+	}
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* __GNUC__ */
+#endif /* _M68K_POSIX_TYPES_H */
diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h
new file mode 100644
index 0000000..4af6919
--- /dev/null
+++ b/arch/m68k/include/asm/processor.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_M68K_PROCESSOR_H
+#define __ASM_M68K_PROCESSOR_H
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+
+#define _GLOBAL(n)\
+	.globl n;\
+n:
+
+/* Macros for setting and retrieving special purpose registers */
+#define setvbr(v)	asm volatile("movec %0,%%VBR" : : "r" (v))
+
+#endif /* __ASM_M68K_PROCESSOR_H */
diff --git a/arch/m68k/include/asm/ptrace.h b/arch/m68k/include/asm/ptrace.h
new file mode 100644
index 0000000..d419824
--- /dev/null
+++ b/arch/m68k/include/asm/ptrace.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _M68K_PTRACE_H
+#define _M68K_PTRACE_H
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during an exception.
+ */
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+	ulong d0;
+	ulong d1;
+	ulong d2;
+	ulong d3;
+	ulong d4;
+	ulong d5;
+	ulong d6;
+	ulong d7;
+	ulong a0;
+	ulong a1;
+	ulong a2;
+	ulong a3;
+	ulong a4;
+	ulong a5;
+	ulong a6;
+#if defined(__M68K__)
+	unsigned format:4;	/* frame format specifier */
+	unsigned vector:12;	/* vector offset */
+	unsigned short sr;
+	unsigned long pc;
+#else
+	unsigned short sr;
+	unsigned long pc;
+#endif
+};
+
+#endif				/* #ifndef __ASSEMBLY__ */
+
+#endif				/* #ifndef _M68K_PTRACE_H */
diff --git a/arch/m68k/include/asm/rtc.h b/arch/m68k/include/asm/rtc.h
new file mode 100644
index 0000000..1fb492c
--- /dev/null
+++ b/arch/m68k/include/asm/rtc.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RealTime Clock
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef __MCFRTC_H__
+#define __MCFRTC_H__
+
+/* Real time Clock */
+typedef struct rtc_ctrl {
+	u32 hourmin;		/* 0x00 Hours and Minutes Counter Register */
+	u32 seconds;		/* 0x04 Seconds Counter Register */
+	u32 alrm_hm;		/* 0x08 Hours and Minutes Alarm Register */
+	u32 alrm_sec;		/* 0x0C Seconds Alarm Register */
+	u32 cr;			/* 0x10 Control Register */
+	u32 isr;		/* 0x14 Interrupt Status Register */
+	u32 ier;		/* 0x18 Interrupt Enable Register */
+	u32 stpwatch;		/* 0x1C Stopwatch Minutes Register */
+	u32 days;		/* 0x20 Days Counter Register */
+	u32 alrm_day;		/* 0x24 Days Alarm Register */
+	void *extended;
+} rtc_t;
+
+/* Bit definitions and macros for HOURMIN */
+#define RTC_HOURMIN_MINUTES(x)	(((x)&0x0000003F))
+#define RTC_HOURMIN_HOURS(x)	(((x)&0x0000001F)<<8)
+
+/* Bit definitions and macros for SECONDS */
+#define RTC_SECONDS_SECONDS(x)	(((x)&0x0000003F))
+
+/* Bit definitions and macros for ALRM_HM */
+#define RTC_ALRM_HM_MINUTES(x)	(((x)&0x0000003F))
+#define RTC_ALRM_HM_HOURS(x)	(((x)&0x0000001F)<<8)
+
+/* Bit definitions and macros for ALRM_SEC */
+#define RTC_ALRM_SEC_SECONDS(x)	(((x)&0x0000003F))
+
+/* Bit definitions and macros for CR */
+#define RTC_CR_SWR		(0x00000001)
+#define RTC_CR_XTL(x)		(((x)&0x00000003)<<5)
+#define RTC_CR_EN		(0x00000080)
+#define RTC_CR_32768		(0x0)
+#define RTC_CR_32000		(0x1)
+#define RTC_CR_38400		(0x2)
+
+/* Bit definitions and macros for ISR */
+#define RTC_ISR_SW		(0x00000001)
+#define RTC_ISR_MIN		(0x00000002)
+#define RTC_ISR_ALM		(0x00000004)
+#define RTC_ISR_DAY		(0x00000008)
+#define RTC_ISR_1HZ		(0x00000010)
+#define RTC_ISR_HR		(0x00000020)
+#define RTC_ISR_2HZ		(0x00000080)
+#define RTC_ISR_SAM0		(0x00000100)
+#define RTC_ISR_SAM1		(0x00000200)
+#define RTC_ISR_SAM2		(0x00000400)
+#define RTC_ISR_SAM3		(0x00000800)
+#define RTC_ISR_SAM4		(0x00001000)
+#define RTC_ISR_SAM5		(0x00002000)
+#define RTC_ISR_SAM6		(0x00004000)
+#define RTC_ISR_SAM7		(0x00008000)
+
+/* Bit definitions and macros for IER */
+#define RTC_IER_SW		(0x00000001)
+#define RTC_IER_MIN		(0x00000002)
+#define RTC_IER_ALM		(0x00000004)
+#define RTC_IER_DAY		(0x00000008)
+#define RTC_IER_1HZ		(0x00000010)
+#define RTC_IER_HR		(0x00000020)
+#define RTC_IER_2HZ		(0x00000080)
+#define RTC_IER_SAM0		(0x00000100)
+#define RTC_IER_SAM1		(0x00000200)
+#define RTC_IER_SAM2		(0x00000400)
+#define RTC_IER_SAM3		(0x00000800)
+#define RTC_IER_SAM4		(0x00001000)
+#define RTC_IER_SAM5		(0x00002000)
+#define RTC_IER_SAM6		(0x00004000)
+#define RTC_IER_SAM7		(0x00008000)
+
+/* Bit definitions and macros for STPWCH */
+#define RTC_STPWCH_CNT(x)	(((x)&0x0000003F))
+
+/* Bit definitions and macros for DAYS */
+#define RTC_DAYS_DAYS(x)	(((x)&0x0000FFFF))
+
+/* Bit definitions and macros for ALRM_DAY */
+#define RTC_ALRM_DAY_DAYS(x)	(((x)&0x0000FFFF))
+
+#endif				/* __MCFRTC_H__ */
diff --git a/arch/m68k/include/asm/sections.h b/arch/m68k/include/asm/sections.h
new file mode 100644
index 0000000..3cb8aa0
--- /dev/null
+++ b/arch/m68k/include/asm/sections.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_M68K_SECTIONS_H
+#define __ASM_M68K_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/m68k/include/asm/string.h b/arch/m68k/include/asm/string.h
new file mode 100644
index 0000000..ecf5e56
--- /dev/null
+++ b/arch/m68k/include/asm/string.h
@@ -0,0 +1,31 @@
+#ifndef _M68K_STRING_H_
+#define _M68K_STRING_H_
+
+#if 0
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRNCPY
+#define __HAVE_ARCH_STRLEN
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRCAT
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_BCOPY
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMMOVE
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_MEMCHR
+#endif
+
+extern int strcasecmp(const char *, const char *);
+extern int strncasecmp(const char *, const char *, __kernel_size_t);
+extern char * strcpy(char *,const char *);
+extern char * strncpy(char *,const char *, __kernel_size_t);
+extern __kernel_size_t strlen(const char *);
+extern int strcmp(const char *,const char *);
+extern char * strcat(char *, const char *);
+extern void * memset(void *,int,__kernel_size_t);
+extern void * memcpy(void *,const void *,__kernel_size_t);
+extern void * memmove(void *,const void *,__kernel_size_t);
+extern int memcmp(const void *,const void *,__kernel_size_t);
+extern void * memchr(const void *,int,__kernel_size_t);
+
+#endif
diff --git a/arch/m68k/include/asm/timer.h b/arch/m68k/include/asm/timer.h
new file mode 100644
index 0000000..982d71a
--- /dev/null
+++ b/arch/m68k/include/asm/timer.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * timer.h -- ColdFire internal TIMER support defines.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/****************************************************************************/
+#ifndef	timer_h
+#define	timer_h
+/****************************************************************************/
+
+/****************************************************************************/
+/* Timer structure */
+/****************************************************************************/
+/* DMA Timer module registers */
+typedef struct dtimer_ctrl {
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+    defined(CONFIG_M5272) || defined(CONFIG_M5307)
+	u16 tmr;		/* 0x00 Mode register */
+	u16 res1;		/* 0x02 */
+	u16 trr;		/* 0x04 Reference register */
+	u16 res2;		/* 0x06 */
+	u16 tcr;		/* 0x08 Capture register */
+	u16 res3;		/* 0x0A */
+	u16 tcn;		/* 0x0C Counter register */
+	u16 res4;		/* 0x0E */
+	u8 res6;		/* 0x10 */
+	u8 ter;			/* 0x11 Event register */
+	u16 res7;		/* 0x12 */
+#else
+	u16 tmr;		/* 0x00 Mode register */
+	u8 txmr;		/* 0x02 Extended Mode register */
+	u8 ter;			/* 0x03 Event register */
+	u32 trr;		/* 0x04 Reference register */
+	u32 tcr;		/* 0x08 Capture register */
+	u32 tcn;		/* 0x0C Counter register */
+#endif
+} dtmr_t;
+
+/*Programmable Interrupt Timer */
+typedef struct pit_ctrl {
+	u16 pcsr;		/* 0x00 Control and Status Register */
+	u16 pmr;		/* 0x02 Modulus Register */
+	u16 pcntr;		/* 0x04 Count Register */
+} pit_t;
+
+/*********************************************************************
+* DMA Timers (DTIM)
+*********************************************************************/
+/* Bit definitions and macros for DTMR */
+#define DTIM_DTMR_RST		(0x0001)	/* Reset */
+#define DTIM_DTMR_CLK(x)	(((x)&0x0003)<<1)	/* Input clock source */
+#define DTIM_DTMR_FRR		(0x0008)	/* Free run/restart */
+#define DTIM_DTMR_ORRI		(0x0010)	/* Output reference request/interrupt enable */
+#define DTIM_DTMR_OM		(0x0020)	/* Output Mode */
+#define DTIM_DTMR_CE(x)		(((x)&0x0003)<<6)	/* Capture Edge */
+#define DTIM_DTMR_PS(x)		(((x)&0x00FF)<<8)	/* Prescaler value */
+#define DTIM_DTMR_RST_EN	(0x0001)
+#define DTIM_DTMR_RST_RST	(0x0000)
+#define DTIM_DTMR_CE_ANY	(0x00C0)
+#define DTIM_DTMR_CE_FALL	(0x0080)
+#define DTIM_DTMR_CE_RISE	(0x0040)
+#define DTIM_DTMR_CE_NONE	(0x0000)
+#define DTIM_DTMR_CLK_DTIN	(0x0006)
+#define DTIM_DTMR_CLK_DIV16	(0x0004)
+#define DTIM_DTMR_CLK_DIV1	(0x0002)
+#define DTIM_DTMR_CLK_STOP	(0x0000)
+
+/* Bit definitions and macros for DTXMR */
+#define DTIM_DTXMR_MODE16	(0x01)	/* Increment Mode */
+#define DTIM_DTXMR_DMAEN	(0x80)	/* DMA request */
+
+/* Bit definitions and macros for DTER */
+#define DTIM_DTER_CAP		(0x01)	/* Capture event */
+#define DTIM_DTER_REF		(0x02)	/* Output reference event */
+
+/*********************************************************************
+*
+* Programmable Interrupt Timer Modules (PIT)
+*
+*********************************************************************/
+
+/* Bit definitions and macros for PCSR */
+#define PIT_PCSR_EN		(0x0001)
+#define PIT_PCSR_RLD		(0x0002)
+#define PIT_PCSR_PIF		(0x0004)
+#define PIT_PCSR_PIE		(0x0008)
+#define PIT_PCSR_OVW		(0x0010)
+#define PIT_PCSR_HALTED		(0x0020)
+#define PIT_PCSR_DOZE		(0x0040)
+#define PIT_PCSR_PRE(x)		(((x)&0x000F)<<8)
+
+/* Bit definitions and macros for PMR */
+#define PIT_PMR_PM(x)		(x)
+
+/* Bit definitions and macros for PCNTR */
+#define PIT_PCNTR_PC(x)		(x)
+
+/****************************************************************************/
+#endif				/* timer_h */
diff --git a/arch/m68k/include/asm/types.h b/arch/m68k/include/asm/types.h
new file mode 100644
index 0000000..5d39b97
--- /dev/null
+++ b/arch/m68k/include/asm/types.h
@@ -0,0 +1,27 @@
+#ifndef _M68K_TYPES_H
+#define _M68K_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+typedef struct {
+	__u32 u[4];
+} __attribute__((aligned(16))) vector128;
+
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+/* DMA addresses are 32-bits wide */
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h
new file mode 100644
index 0000000..803f76f
--- /dev/null
+++ b/arch/m68k/include/asm/u-boot.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000 - 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __U_BOOT_H__
+#define __U_BOOT_H__
+
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_M68K
+
+#endif				/* __U_BOOT_H__ */
diff --git a/arch/m68k/include/asm/uart.h b/arch/m68k/include/asm/uart.h
new file mode 100644
index 0000000..e4a9650
--- /dev/null
+++ b/arch/m68k/include/asm/uart.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * uart.h -- ColdFire internal UART support defines.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/****************************************************************************/
+#ifndef	uart_h
+#define	uart_h
+/****************************************************************************/
+
+/* UART module registers */
+/* Register read/write struct */
+typedef struct uart {
+	u8 umr;			/* 0x00 Mode Register */
+	u8 resv0[0x3];
+	union {
+		u8 usr;		/* 0x04 Status Register */
+		u8 ucsr;	/* 0x04 Clock Select Register */
+	};
+	u8 resv1[0x3];
+	u8 ucr;			/* 0x08 Command Register */
+	u8 resv2[0x3];
+	union {
+		u8 utb;		/* 0x0c Transmit Buffer */
+		u8 urb;		/* 0x0c Receive Buffer */
+	};
+	u8 resv3[0x3];
+	union {
+		u8 uipcr;	/* 0x10 Input Port Change Register */
+		u8 uacr;	/* 0x10 Auxiliary Control reg */
+	};
+	u8 resv4[0x3];
+	union {
+		u8 uimr;	/* 0x14 Interrupt Mask reg */
+		u8 uisr;	/* 0x14 Interrupt Status reg */
+	};
+	u8 resv5[0x3];
+	u8 ubg1;		/* 0x18 Counter Timer Upper Register */
+	u8 resv6[0x3];
+	u8 ubg2;		/* 0x1c Counter Timer Lower Register */
+	u8 resv7[0x17];
+	u8 uip;			/* 0x34 Input Port Register */
+	u8 resv8[0x3];
+	u8 uop1;		/* 0x38 Output Port Set Register */
+	u8 resv9[0x3];
+	u8 uop0;		/* 0x3c Output Port Reset Register */
+} uart_t;
+
+/*********************************************************************
+* Universal Asynchronous Receiver Transmitter (UART)
+*********************************************************************/
+/* Bit definitions and macros for UMR */
+#define UART_UMR_BC(x)			(((x)&0x03))
+#define UART_UMR_PT			(0x04)
+#define UART_UMR_PM(x)			(((x)&0x03)<<3)
+#define UART_UMR_ERR			(0x20)
+#define UART_UMR_RXIRQ			(0x40)
+#define UART_UMR_RXRTS			(0x80)
+#define UART_UMR_SB(x)			(((x)&0x0F))
+#define UART_UMR_TXCTS			(0x10)	/* Trsnsmit CTS */
+#define UART_UMR_TXRTS			(0x20)	/* Transmit RTS */
+#define UART_UMR_CM(x)			(((x)&0x03)<<6)	/* CM bits */
+#define UART_UMR_PM_MULTI_ADDR		(0x1C)
+#define UART_UMR_PM_MULTI_DATA		(0x18)
+#define UART_UMR_PM_NONE		(0x10)
+#define UART_UMR_PM_FORCE_HI		(0x0C)
+#define UART_UMR_PM_FORCE_LO		(0x08)
+#define UART_UMR_PM_ODD			(0x04)
+#define UART_UMR_PM_EVEN		(0x00)
+#define UART_UMR_BC_5			(0x00)
+#define UART_UMR_BC_6			(0x01)
+#define UART_UMR_BC_7			(0x02)
+#define UART_UMR_BC_8			(0x03)
+#define UART_UMR_CM_NORMAL		(0x00)
+#define UART_UMR_CM_ECH			(0x40)
+#define UART_UMR_CM_LOCAL_LOOP		(0x80)
+#define UART_UMR_CM_REMOTE_LOOP		(0xC0)
+#define UART_UMR_SB_STOP_BITS_1		(0x07)
+#define UART_UMR_SB_STOP_BITS_15	(0x08)
+#define UART_UMR_SB_STOP_BITS_2		(0x0F)
+
+/* Bit definitions and macros for USR */
+#define UART_USR_RXRDY			(0x01)
+#define UART_USR_FFULL			(0x02)
+#define UART_USR_TXRDY			(0x04)
+#define UART_USR_TXEMP			(0x08)
+#define UART_USR_OE			(0x10)
+#define UART_USR_PE			(0x20)
+#define UART_USR_FE			(0x40)
+#define UART_USR_RB			(0x80)
+
+/* Bit definitions and macros for UCSR */
+#define UART_UCSR_TCS(x)		(((x)&0x0F))
+#define UART_UCSR_RCS(x)		(((x)&0x0F)<<4)
+#define UART_UCSR_RCS_SYS_CLK		(0xD0)
+#define UART_UCSR_RCS_CTM16		(0xE0)
+#define UART_UCSR_RCS_CTM		(0xF0)
+#define UART_UCSR_TCS_SYS_CLK		(0x0D)
+#define UART_UCSR_TCS_CTM16		(0x0E)
+#define UART_UCSR_TCS_CTM		(0x0F)
+
+/* Bit definitions and macros for UCR */
+#define UART_UCR_RXC(x)			(((x)&0x03))
+#define UART_UCR_TXC(x)			(((x)&0x03)<<2)
+#define UART_UCR_MISC(x)		(((x)&0x07)<<4)
+#define UART_UCR_NONE			(0x00)
+#define UART_UCR_STOP_BREAK		(0x70)
+#define UART_UCR_START_BREAK		(0x60)
+#define UART_UCR_BKCHGINT		(0x50)
+#define UART_UCR_RESET_ERROR		(0x40)
+#define UART_UCR_RESET_TX		(0x30)
+#define UART_UCR_RESET_RX		(0x20)
+#define UART_UCR_RESET_MR		(0x10)
+#define UART_UCR_TX_DISABLED		(0x08)
+#define UART_UCR_TX_ENABLED		(0x04)
+#define UART_UCR_RX_DISABLED		(0x02)
+#define UART_UCR_RX_ENABLED		(0x01)
+
+/* Bit definitions and macros for UIPCR */
+#define UART_UIPCR_CTS			(0x01)
+#define UART_UIPCR_COS			(0x10)
+
+/* Bit definitions and macros for UACR */
+#define UART_UACR_IEC			(0x01)
+
+/* Bit definitions and macros for UIMR */
+#define UART_UIMR_TXRDY			(0x01)
+#define UART_UIMR_RXRDY_FU		(0x02)
+#define UART_UIMR_DB			(0x04)
+#define UART_UIMR_COS			(0x80)
+
+/* Bit definitions and macros for UISR */
+#define UART_UISR_TXRDY			(0x01)
+#define UART_UISR_RXRDY_FU		(0x02)
+#define UART_UISR_DB			(0x04)
+#define UART_UISR_RXFTO			(0x08)
+#define UART_UISR_TXFIFO		(0x10)
+#define UART_UISR_RXFIFO		(0x20)
+#define UART_UISR_COS			(0x80)
+
+/* Bit definitions and macros for UIP */
+#define UART_UIP_CTS			(0x01)
+
+/* Bit definitions and macros for UOP1 */
+#define UART_UOP1_RTS			(0x01)
+
+/* Bit definitions and macros for UOP0 */
+#define UART_UOP0_RTS			(0x01)
+
+/****************************************************************************/
+#endif				/* mcfuart_h */
diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h
new file mode 100644
index 0000000..328aa0c
--- /dev/null
+++ b/arch/m68k/include/asm/unaligned.h
@@ -0,0 +1,15 @@
+#ifndef _ASM_M68K_UNALIGNED_H
+#define _ASM_M68K_UNALIGNED_H
+
+#ifdef CONFIG_COLDFIRE
+#include <linux/unaligned/be_byteshift.h>
+#else
+#include <linux/unaligned/access_ok.h>
+#endif
+
+#include <linux/unaligned/generic.h>
+
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+
+#endif /* _ASM_M68K_UNALIGNED_H */
diff --git a/arch/microblaze/include/asm/asm.h b/arch/microblaze/include/asm/asm.h
new file mode 100644
index 0000000..fb8fe38
--- /dev/null
+++ b/arch/microblaze/include/asm/asm.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ */
+
+/* FSL macros */
+#define NGET(val, fslnum) \
+	__asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val));
+
+#define GET(val, fslnum) \
+	__asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val));
+
+#define NCGET(val, fslnum) \
+	__asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val));
+
+#define CGET(val, fslnum) \
+	__asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val));
+
+#define NPUT(val, fslnum) \
+	__asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
+
+#define PUT(val, fslnum) \
+	__asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val));
+
+#define NCPUT(val, fslnum) \
+	__asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val));
+
+#define CPUT(val, fslnum) \
+	__asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val));
+
+/* CPU dependent */
+/* machine status register */
+#define MFS(val, reg) \
+	__asm__ __volatile__ ("mfs %0," #reg :"=r" (val));
+
+#define MTS(val, reg) \
+	__asm__ __volatile__ ("mts " #reg ", %0"::"r" (val));
+
+/* get return address from interrupt */
+#define R14(val) \
+	__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
+
+/* get return address from interrupt */
+#define R17(val) \
+	__asm__ __volatile__ ("addi %0, r17, 0" : "=r" (val));
+
+#define NOP	__asm__ __volatile__ ("nop");
+
+/* use machine status registe USE_MSR_REG */
+#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 1
+#define MSRSET(val) \
+	__asm__ __volatile__ ("msrset r0," #val );
+
+#define MSRCLR(val) \
+	__asm__ __volatile__ ("msrclr r0," #val );
+
+#else
+#define MSRSET(val)						\
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs	%0, rmsr;			\
+			ori	%0, %0, "#val";			\
+			mts	rmsr, %0;			\
+			nop;"					\
+			: "=r" (tmp)				\
+			: "d" (val)				\
+			: "memory");				\
+}
+
+#define MSRCLR(val)						\
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs	%0, rmsr;			\
+			andi	%0, %0, ~"#val";		\
+			mts	rmsr, %0;			\
+			nop;"					\
+			: "=r" (tmp)				\
+			: "d" (val)				\
+			: "memory");				\
+}
+#endif
diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h
new file mode 100644
index 0000000..2cab2ac
--- /dev/null
+++ b/arch/microblaze/include/asm/bitops.h
@@ -0,0 +1,375 @@
+#ifndef _MICROBLAZE_BITOPS_H
+#define _MICROBLAZE_BITOPS_H
+
+/*
+ * Copyright 1992, Linus Torvalds.
+ */
+
+#include <asm/byteorder.h>	/* swab32 */
+#include <asm/system.h>		/* save_flags */
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+#ifdef __KERNEL__
+/*
+ * The __ functions are not atomic
+ */
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	unsigned long result = 0;
+
+	while(word & 1) {
+		result++;
+		word >>= 1;
+	}
+	return result;
+}
+
+
+static inline void set_bit(int nr, volatile void *addr)
+{
+	int	* a = (int *) addr;
+	int	mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_flags_cli(flags);
+	*a |= mask;
+	restore_flags(flags);
+}
+
+static inline void __set_bit(int nr, volatile void *addr)
+{
+	int	* a = (int *) addr;
+	int	mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+#define PLATFORM__SET_BIT
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+
+static inline void clear_bit(int nr, volatile void *addr)
+{
+	int	* a = (int *) addr;
+	int	mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_flags_cli(flags);
+	*a &= ~mask;
+	restore_flags(flags);
+}
+
+#define __clear_bit(nr, addr) clear_bit(nr, addr)
+#define PLATFORM__CLEAR_BIT
+
+static inline void change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long flags;
+	unsigned long *ADDR = (unsigned long *) addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	save_flags_cli(flags);
+	*ADDR ^= mask;
+	restore_flags(flags);
+}
+
+static inline void __change_bit(int nr, volatile void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *) addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+static inline int test_and_set_bit(int nr, volatile void *addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_flags_cli(flags);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	restore_flags(flags);
+
+	return retval;
+}
+
+static inline int __test_and_set_bit(int nr, volatile void *addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void *addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_flags_cli(flags);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	restore_flags(flags);
+
+	return retval;
+}
+
+static inline int __test_and_clear_bit(int nr, volatile void *addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+static inline int test_and_change_bit(int nr, volatile void *addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	save_flags_cli(flags);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	restore_flags(flags);
+
+	return retval;
+}
+
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = (volatile unsigned int *) addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int __constant_test_bit(int nr, const volatile void *addr)
+{
+	return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
+}
+
+static inline int __test_bit(int nr, volatile void *addr)
+{
+	int	* a = (int *) addr;
+	int	mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	return ((mask & *a) != 0);
+}
+
+#define test_bit(nr,addr) \
+(__builtin_constant_p(nr) ? \
+ __constant_test_bit((nr),(addr)) : \
+ __test_bit((nr),(addr)))
+
+#define find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
+
+static inline int find_next_zero_bit(void *addr, int size, int offset)
+{
+	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (32-offset);
+		if (size < 32)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size & ~31UL) {
+		if (~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	tmp |= ~0UL >> size;
+found_middle:
+	return result + ffz(tmp);
+}
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+
+static inline int ext2_set_bit(int nr, volatile void *addr)
+{
+	int		mask, retval;
+	unsigned long	flags;
+	volatile unsigned char	*ADDR = (unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	save_flags_cli(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR |= mask;
+	restore_flags(flags);
+	return retval;
+}
+
+static inline int ext2_clear_bit(int nr, volatile void *addr)
+{
+	int		mask, retval;
+	unsigned long	flags;
+	volatile unsigned char	*ADDR = (unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	save_flags_cli(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR &= ~mask;
+	restore_flags(flags);
+	return retval;
+}
+
+static inline int ext2_test_bit(int nr, const volatile void *addr)
+{
+	int			mask;
+	const volatile unsigned char	*ADDR = (const unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	return ((mask & *ADDR) != 0);
+}
+
+#define ext2_find_first_zero_bit(addr, size) \
+	ext2_find_next_zero_bit((addr), (size), 0)
+
+static inline unsigned long ext2_find_next_zero_bit(void *addr,
+				unsigned long size, unsigned long offset)
+{
+	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if(offset) {
+		/* We hold the little endian value in tmp, but then the
+		 * shift is illegal. So we could keep a big endian value
+		 * in tmp, like this:
+		 *
+		 * tmp = __swab32(*(p++));
+		 * tmp |= ~0UL >> (32-offset);
+		 *
+		 * but this would decrease preformance, so we change the
+		 * shift:
+		 */
+		tmp = *(p++);
+		tmp |= __swab32(~0UL >> (32-offset));
+		if(size < 32)
+			goto found_first;
+		if(~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while(size & ~31UL) {
+		if(~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if(!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	/* tmp is little endian, so we would have to swab the shift,
+	 * see above. But then we have to swab tmp below for ffz, so
+	 * we might as well do this here.
+	 */
+	return result + ffz(__swab32(tmp) | (~0UL << size));
+found_middle:
+	return result + ffz(__swab32(tmp));
+}
+
+/* Bitmap functions for the minix filesystem.  */
+#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
+
+/**
+ * hweightN - returns the hamming weight of a N-bit word
+ * @x: the word to weigh
+ *
+ * The Hamming Weight of a number is the total number of bits set in it.
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+#endif /* _MICROBLAZE_BITOPS_H */
diff --git a/arch/microblaze/include/asm/byteorder.h b/arch/microblaze/include/asm/byteorder.h
new file mode 100644
index 0000000..f3a471d
--- /dev/null
+++ b/arch/microblaze/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ * include/asm-microblaze/byteorder.h -- Endian id and conversion ops
+ *
+ *  Copyright (C) 2003  John Williams <jwilliams@itee.uq.edu.au>
+ *  Copyright (C) 2001  NEC Corporation
+ *  Copyright (C) 2001  Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_BYTEORDER_H__
+#define __MICROBLAZE_BYTEORDER_H__
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __GNUC__ */
+
+#ifdef __MICROBLAZEEL__
+#include <linux/byteorder/little_endian.h>
+#else
+#include <linux/byteorder/big_endian.h>
+#endif
+
+#endif /* __MICROBLAZE_BYTEORDER_H__ */
diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h
new file mode 100644
index 0000000..baee01a
--- /dev/null
+++ b/arch/microblaze/include/asm/cache.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __MICROBLAZE_CACHE_H__
+#define __MICROBLAZE_CACHE_H__
+
+/*
+ * The microblaze can have either a 4 or 16 byte cacheline depending on whether
+ * you are using OPB(4) or CacheLink(16).  If the board config has not specified
+ * a cacheline size we assume the larger value of 16 bytes for DMA buffer
+ * alignment.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	16
+#endif
+
+#endif /* __MICROBLAZE_CACHE_H__ */
diff --git a/arch/microblaze/include/asm/config.h b/arch/microblaze/include/asm/config.h
new file mode 100644
index 0000000..1124272
--- /dev/null
+++ b/arch/microblaze/include/asm/config.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_LMB
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_NEEDS_MANUAL_RELOC
+#endif
+
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#endif
diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h
new file mode 100644
index 0000000..05868ac
--- /dev/null
+++ b/arch/microblaze/include/asm/global_data.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+/* Architecture-specific global data */
+struct arch_global_data {
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r31")
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/microblaze/include/asm/gpio.h b/arch/microblaze/include/asm/gpio.h
new file mode 100644
index 0000000..306ab4c
--- /dev/null
+++ b/arch/microblaze/include/asm/gpio.h
@@ -0,0 +1 @@
+#include <asm-generic/gpio.h>
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
new file mode 100644
index 0000000..8e6be0a
--- /dev/null
+++ b/arch/microblaze/include/asm/io.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/asm-microblaze/io.h -- Misc I/O operations
+ *
+ *  Copyright (C) 2003     John Williams <jwilliams@itee.uq.edu.au>
+ *  Copyright (C) 2001,02  NEC Corporation
+ *  Copyright (C) 2001,02  Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_IO_H__
+#define __MICROBLAZE_IO_H__
+
+#include <asm/types.h>
+
+#define IO_SPACE_LIMIT 0xFFFFFFFF
+
+#define readb(addr) \
+	({ unsigned char __v = (*(volatile unsigned char *)(addr)); __v; })
+
+#define readw(addr) \
+	({ unsigned short __v = (*(volatile unsigned short *)(addr)); __v; })
+
+#define readl(addr) \
+	({ unsigned int __v = (*(volatile unsigned int *)(addr)); __v; })
+
+#define writeb(b, addr) \
+	(void)((*(volatile unsigned char *)(addr)) = (b))
+
+#define writew(b, addr) \
+	(void)((*(volatile unsigned short *)(addr)) = (b))
+
+#define writel(b, addr) \
+	(void)((*(volatile unsigned int *)(addr)) = (b))
+
+#define memset_io(a, b, c)        memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)    memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)      memcpy((void *)(a), (b), (c))
+
+#define inb(addr)	readb(addr)
+#define inw(addr)	readw(addr)
+#define inl(addr)	readl(addr)
+#define outb(x, addr)	((void)writeb(x, addr))
+#define outw(x, addr)	((void)writew(x, addr))
+#define outl(x, addr)	((void)writel(x, addr))
+
+/* Some #definitions to keep strange Xilinx code happy */
+#define in_8(addr)	readb(addr)
+#define in_be16(addr)	readw(addr)
+#define in_be32(addr)	readl(addr)
+
+#define out_8(addr, x)		outb(x, addr)
+#define out_be16(addr, x)	outw(x, addr)
+#define out_be32(addr, x)	outl(x, addr)
+
+#define inb_p(port)		inb((port))
+#define outb_p(val, port)	outb((val), (port))
+#define inw_p(port)		inw((port))
+#define outw_p(val, port)	outw((val), (port))
+#define inl_p(port)		inl((port))
+#define outl_p(val, port)	outl((val), (port))
+
+/* Some defines to keep the MTD flash drivers happy */
+
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+
+static inline void io_insb(unsigned long port, void *dst, unsigned long count)
+{
+	unsigned char *p = dst;
+
+	while (count--)
+		*p++ = inb(port);
+}
+
+static inline void io_insw(unsigned long port, void *dst, unsigned long count)
+{
+	unsigned short *p = dst;
+
+	while (count--)
+		*p++ = inw(port);
+}
+
+static inline void io_insl(unsigned long port, void *dst, unsigned long count)
+{
+	unsigned long *p = dst;
+
+	while (count--)
+		*p++ = inl(port);
+}
+
+static inline void
+io_outsb(unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned char *p = src;
+
+	while (count--)
+		outb(*p++, port);
+}
+
+static inline void
+io_outsw(unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned short *p = src;
+
+	while (count--)
+		outw(*p++, port);
+}
+
+static inline void
+io_outsl(unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned long *p = src;
+
+	while (count--)
+		outl(*p++, port);
+}
+
+#define outsb(a, b, l) io_outsb(a, b, l)
+#define outsw(a, b, l) io_outsw(a, b, l)
+#define outsl(a, b, l) io_outsl(a, b, l)
+
+#define insb(a, b, l) io_insb(a, b, l)
+#define insw(a, b, l) io_insw(a, b, l)
+#define insl(a, b, l) io_insl(a, b, l)
+
+#define ioremap_nocache(physaddr, size)		(physaddr)
+#define ioremap_writethrough(physaddr, size)	(physaddr)
+#define ioremap_fullcache(physaddr, size)	(physaddr)
+
+static inline void sync(void)
+{
+}
+
+#include <asm-generic/io.h>
+
+#endif /* __MICROBLAZE_IO_H__ */
diff --git a/arch/microblaze/include/asm/linkage.h b/arch/microblaze/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/microblaze/include/asm/linkage.h
diff --git a/arch/microblaze/include/asm/microblaze_intc.h b/arch/microblaze/include/asm/microblaze_intc.h
new file mode 100644
index 0000000..b4e0fc6
--- /dev/null
+++ b/arch/microblaze/include/asm/microblaze_intc.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.cz>
+ */
+
+typedef volatile struct microblaze_intc_t {
+	int isr; /* interrupt status register */
+	int ipr; /* interrupt pending register */
+	int ier; /* interrupt enable register */
+	int iar; /* interrupt acknowledge register */
+	int sie; /* set interrupt enable bits */
+	int cie; /* clear interrupt enable bits */
+	int ivr; /* interrupt vector register */
+	int mer; /* master enable register */
+} microblaze_intc_t;
+
+struct irq_action {
+	interrupt_handler_t *handler; /* pointer to interrupt rutine */
+	void *arg;
+	int count; /* number of interrupt */
+};
+
+/**
+ * Register and unregister interrupt handler rutines
+ *
+ * @param irq	IRQ number
+ * @param hdlr	Interrupt handler rutine
+ * @param arg	Pointer to argument which is passed to int. handler rutine
+ * @return	0 if registration pass, 1 if unregistration pass,
+ *		or an error code < 0 otherwise
+ */
+int install_interrupt_handler(int irq, interrupt_handler_t *hdlr,
+				       void *arg);
diff --git a/arch/microblaze/include/asm/microblaze_timer.h b/arch/microblaze/include/asm/microblaze_timer.h
new file mode 100644
index 0000000..2ed1651
--- /dev/null
+++ b/arch/microblaze/include/asm/microblaze_timer.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.cz>
+ */
+
+#define TIMER_ENABLE_ALL    0x400 /* ENALL */
+#define TIMER_PWM           0x200 /* PWMA0 */
+#define TIMER_INTERRUPT     0x100 /* T0INT */
+#define TIMER_ENABLE        0x080 /* ENT0 */
+#define TIMER_ENABLE_INTR   0x040 /* ENIT0 */
+#define TIMER_RESET         0x020 /* LOAD0 */
+#define TIMER_RELOAD        0x010 /* ARHT0 */
+#define TIMER_EXT_CAPTURE   0x008 /* CAPT0 */
+#define TIMER_EXT_COMPARE   0x004 /* GENT0 */
+#define TIMER_DOWN_COUNT    0x002 /* UDT0 */
+#define TIMER_CAPTURE_MODE  0x001 /* MDT0 */
+
+typedef volatile struct microblaze_timer_t {
+	int control; /* control/statuc register TCSR */
+	int loadreg; /* load register TLR */
+	int counter; /* timer/counter register */
+} microblaze_timer_t;
+
+int timer_init(void);
diff --git a/arch/microblaze/include/asm/posix_types.h b/arch/microblaze/include/asm/posix_types.h
new file mode 100644
index 0000000..ccc6235
--- /dev/null
+++ b/arch/microblaze/include/asm/posix_types.h
@@ -0,0 +1,77 @@
+/*
+ * include/asm-microblaze/posix_types.h -- Kernel versions of standard types
+ *
+ *  Copyright (C) 2003       John Williams <jwilliams@itee.uq.edu.au>
+ *  Copyright (C) 2001,2002  NEC Corporation
+ *  Copyright (C) 2001,2002  Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_POSIX_TYPES_H__
+#define __MICROBLAZE_POSIX_TYPES_H__
+
+typedef unsigned int	__kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned long long __kernel_ino64_t;
+typedef unsigned int	__kernel_mode_t;
+typedef unsigned int	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef long long	__kernel_loff_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned int	__kernel_uid_t;
+typedef unsigned int	__kernel_gid_t;
+#ifdef __GNUC__
+typedef __SIZE_TYPE__  __kernel_size_t;
+#else
+typedef unsigned int	__kernel_size_t;
+#endif
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fd_set) \
+  __set_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
+#undef __FD_CLR
+#define __FD_CLR(fd, fd_set) \
+  __clear_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fd_set) \
+  __test_bit (fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits)
+#undef	__FD_ZERO
+#define __FD_ZERO(fd_set) \
+  memset (fd_set, 0, sizeof (*(fd_set *)fd_set))
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __MICROBLAZE_POSIX_TYPES_H__ */
diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h
new file mode 100644
index 0000000..16e0d0e
--- /dev/null
+++ b/arch/microblaze/include/asm/processor.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
+ */
+
+#ifndef __ASM_MICROBLAZE_PROCESSOR_H
+#define __ASM_MICROBLAZE_PROCESSOR_H
+
+/* References to section boundaries */
+
+extern char __end[];
+extern char __text_start[];
+
+/* Microblaze board initialization function */
+void board_init(void);
+
+/* Watchdog functions */
+extern void hw_watchdog_disable(void);
+
+#endif /* __ASM_MICROBLAZE_PROCESSOR_H */
diff --git a/arch/microblaze/include/asm/ptrace.h b/arch/microblaze/include/asm/ptrace.h
new file mode 100644
index 0000000..b796d4f
--- /dev/null
+++ b/arch/microblaze/include/asm/ptrace.h
@@ -0,0 +1,116 @@
+/*
+ * include/asm-microblaze/ptrace.h -- Access to CPU registers
+ *
+ *  Copyright (C) 2003       John Williams <jwilliams@itee.uq.edu.au>
+ *  Copyright (C) 2001,2002  NEC Corporation
+ *  Copyright (C) 2001,2002  Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_PTRACE_H__
+#define __MICROBLAZE_PTRACE_H__
+
+
+/* Microblaze general purpose registers with special meanings.  */
+#define GPR_ZERO	0	/* constant zero */
+#define GPR_ASM		18	/* reserved for assembler */
+#define GPR_SP		1	/* stack pointer */
+#define GPR_GP		2	/* global data pointer */
+#define GPR_EP		30	/* `element pointer' */
+#define GPR_LP		15	/* link pointer (current return address) */
+
+/* These aren't official names, but they make some code more descriptive.  */
+#define GPR_ARG0	5
+#define GPR_ARG1	6
+#define GPR_ARG2	7
+#define GPR_ARG3	8
+#define GPR_ARG4	9
+#define GPR_ARG5	10
+#define GPR_RVAL0	3
+#define GPR_RVAL1	4
+#define GPR_RVAL	GPR_RVAL0
+
+#define NUM_GPRS	32
+
+/* `system' registers.  */
+/* Note these are old v850 values, microblaze has many fewer */
+#define SR_EIPC		0
+#define SR_EIPSW	1
+#define SR_FEPC		2
+#define SR_FEPSW	3
+#define SR_ECR		4
+#define SR_PSW		5
+#define SR_CTPC		16
+#define SR_CTPSW	17
+#define SR_DBPC		18
+#define SR_DBPSW	19
+#define SR_CTBP		20
+#define SR_DIR		21
+#define SR_ASID		23
+
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long microblaze_reg_t;
+
+/* How processor state is stored on the stack during a syscall/signal.
+   If you change this structure, change the associated assembly-language
+   macros below too (PT_*)!  */
+struct pt_regs
+{
+	/* General purpose registers.  */
+	microblaze_reg_t gpr[NUM_GPRS];
+
+	microblaze_reg_t pc;		/* program counter */
+	microblaze_reg_t psw;		/* program status word */
+
+	microblaze_reg_t kernel_mode;	/* 1 if in `kernel mode', 0 if user mode */
+	microblaze_reg_t single_step;	/* 1 if in single step mode */
+};
+
+
+#define instruction_pointer(regs)	((regs)->pc)
+#define user_mode(regs)			(!(regs)->kernel_mode)
+
+/* When a struct pt_regs is used to save user state for a system call in
+   the kernel, the system call is stored in the space for R0 (since it's
+   never used otherwise, R0 being a constant 0).  Non-system-calls
+   simply store 0 there.  */
+#define PT_REGS_SYSCALL(regs)		(regs)->gpr[0]
+#define PT_REGS_SET_SYSCALL(regs, val)	((regs)->gpr[0] = (val))
+
+#endif /* !__ASSEMBLY__ */
+
+
+/* The number of bytes used to store each register.  */
+#define _PT_REG_SIZE	4
+
+/* Offset of a general purpose register in a stuct pt_regs.  */
+#define PT_GPR(num)	((num) * _PT_REG_SIZE)
+
+/* Offsets of various special registers & fields in a struct pt_regs.  */
+#define NUM_SPECIAL	4
+#define PT_PC		((NUM_GPRS + 0) * _PT_REG_SIZE)
+#define PT_PSW		((NUM_GPRS + 1) * _PT_REG_SIZE)
+#define PT_KERNEL_MODE	((NUM_GPRS + 2) * _PT_REG_SIZE)
+#define PT_SINGLESTEP	((NUM_GPRS + 3) * _PT_REG_SIZE)
+
+#define PT_SYSCALL	PT_GPR(0)
+
+/* Size of struct pt_regs, including alignment.  */
+#define PT_SIZE		((NUM_GPRS + NUM_SPECIAL) * _PT_REG_SIZE)
+
+/* These are `magic' values for PTRACE_PEEKUSR that return info about where
+   a process is located in memory.  */
+#define PT_TEXT_ADDR    (PT_SIZE + 1)
+#define PT_TEXT_LEN     (PT_SIZE + 2)
+#define PT_DATA_ADDR    (PT_SIZE + 3)
+#define PT_DATA_LEN     (PT_SIZE + 4)
+
+#endif /* __MICROBLAZE_PTRACE_H__ */
diff --git a/arch/microblaze/include/asm/sections.h b/arch/microblaze/include/asm/sections.h
new file mode 100644
index 0000000..740783c
--- /dev/null
+++ b/arch/microblaze/include/asm/sections.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_MICROBLAZE_SECTIONS_H
+#define __ASM_MICROBLAZE_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/microblaze/include/asm/spl.h b/arch/microblaze/include/asm/spl.h
new file mode 100644
index 0000000..350d283
--- /dev/null
+++ b/arch/microblaze/include/asm/spl.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 - 2014 Xilinx, Inc
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#ifndef _ASM_MICROBLAZE_SPL_H_
+#define _ASM_MICROBLAZE_SPL_H_
+
+#define BOOT_DEVICE_RAM		1
+#define BOOT_DEVICE_NOR		2
+#define BOOT_DEVICE_SPI		3
+
+#endif
diff --git a/arch/microblaze/include/asm/string.h b/arch/microblaze/include/asm/string.h
new file mode 100644
index 0000000..8f67ec7
--- /dev/null
+++ b/arch/microblaze/include/asm/string.h
@@ -0,0 +1,29 @@
+/*
+ * include/asm-microblaze/string.h -- Architecture specific string routines
+ *
+ *  Copyright (C) 2003       John Williams <jwilliams@itee.uq.edu.au>
+ *  Copyright (C) 2001,2002  NEC Corporation
+ *  Copyright (C) 2001,2002  Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_STRING_H__
+#define __MICROBLAZE_STRING_H__
+
+#if 0
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMMOVE
+
+extern void *memcpy (void *, const void *, __kernel_size_t);
+extern void *memset (void *, int, __kernel_size_t);
+extern void *memmove (void *, const void *, __kernel_size_t);
+#endif
+
+#endif /* __MICROBLAZE_STRING_H__ */
diff --git a/arch/microblaze/include/asm/system.h b/arch/microblaze/include/asm/system.h
new file mode 100644
index 0000000..3107748
--- /dev/null
+++ b/arch/microblaze/include/asm/system.h
@@ -0,0 +1,161 @@
+/*
+ * include/asm-microblaze/system.h -- Low-level interrupt/thread ops
+ *
+ *  Copyright (C) 2003	John Williams (jwilliams@itee.uq.edu.au)
+ *			based upon microblaze version
+ *  Copyright (C) 2001	NEC Corporation
+ *  Copyright (C) 2001	Miles Bader <miles@gnu.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file COPYING in the main directory of this
+ * archive for more details.
+ *
+ * Written by Miles Bader <miles@gnu.org>
+ * Microblaze port by John Williams
+ * Microblaze port by John Williams
+ */
+
+#ifndef __MICROBLAZE_SYSTEM_H__
+#define __MICROBLAZE_SYSTEM_H__
+
+#if 0
+#include <linux/linkage.h>
+#endif
+#include <asm/ptrace.h>
+
+#define prepare_to_switch()	do { } while (0)
+
+/*
+ * switch_to(n) should switch tasks to task ptr, first checking that
+ * ptr isn't the current task, in which case it does nothing.
+ */
+struct thread_struct;
+extern void *switch_thread (struct thread_struct *last,
+			    struct thread_struct *next);
+#define switch_to(prev,next,last) do {					\
+	if (prev != next) {						\
+		(last) = switch_thread (&prev->thread, &next->thread);	\
+	}								\
+} while (0)
+
+
+/* Enable/disable interrupts.  */
+#define __sti() \
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs	%0, rmsr;			\
+			ori	%0, %0, 2;			\
+			mts	rmsr, %0"			\
+			: "=r" (tmp)				\
+			:					\
+			: "memory");				\
+}
+
+#define __cli() \
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs	%0, rmsr;			\
+			andi	%0, %0, ~2;			\
+			mts	rmsr, %0"			\
+			: "=r" (tmp)				\
+			:					\
+			: "memory");				\
+}
+
+#define __save_flags(flags) \
+	__asm__ __volatile__ ("mfs	%0, rmsr" : "=r" (flags))
+#define __restore_flags(flags) \
+	__asm__ __volatile__ ("mts	rmsr, %0" :: "r" (flags))
+
+#define __save_flags_cli(flags) \
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs	%0, rmsr;			\
+			andi	%1, %0, ~2;			\
+			mts	rmsr, %1;"			\
+			: "=r" (flags), "=r" (tmp)		\
+			:					\
+			: "memory");				\
+}
+
+#define __save_flags_sti(flags)					\
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs	%0, rmsr;			\
+			ori	%1, %0, 2;			\
+			mts	rmsr, %1;"			\
+			: "=r" (flags) ,"=r" (tmp)		\
+			:					\
+			: "memory");				\
+}
+
+/* For spinlocks etc */
+#define local_irq_save(flags)	__save_flags_cli (flags)
+#define local_irq_set(flags)	__save_flags_sti (flags)
+#define local_irq_restore(flags) __restore_flags (flags)
+#define local_irq_disable()	__cli ()
+#define local_irq_enable()	__sti ()
+
+#define cli()			__cli ()
+#define sti()			__sti ()
+#define save_flags(flags)	__save_flags (flags)
+#define restore_flags(flags)	__restore_flags (flags)
+#define save_flags_cli(flags)	__save_flags_cli (flags)
+
+/*
+ * Force strict CPU ordering.
+ * Not really required on microblaze...
+ */
+#define nop()			__asm__ __volatile__ ("nop")
+#define mb()			__asm__ __volatile__ ("nop" ::: "memory")
+#define rmb()			mb ()
+#define wmb()			mb ()
+#define set_mb(var, value)	do { var = value; mb(); } while (0)
+#define set_wmb(var, value)	do { var = value; wmb (); } while (0)
+
+#ifdef CONFIG_SMP
+#define smp_mb()	mb ()
+#define smp_rmb()	rmb ()
+#define smp_wmb()	wmb ()
+#else
+#define smp_mb()	barrier ()
+#define smp_rmb()	barrier ()
+#define smp_wmb()	barrier ()
+#endif
+
+#define xchg(ptr, with) \
+  ((__typeof__ (*(ptr)))__xchg ((unsigned long)(with), (ptr), sizeof (*(ptr))))
+#define tas(ptr) (xchg ((ptr), 1))
+
+static inline unsigned long __xchg(unsigned long with,
+				    __volatile__ void *ptr, int size)
+{
+	unsigned long tmp, flags;
+
+	save_flags_cli (flags);
+
+	switch (size) {
+	case 1:
+		tmp = *(unsigned char *)ptr;
+		*(unsigned char *)ptr = with;
+		break;
+	case 2:
+		tmp = *(unsigned short *)ptr;
+		*(unsigned short *)ptr = with;
+		break;
+	case 4:
+		tmp = *(unsigned long *)ptr;
+		*(unsigned long *)ptr = with;
+		break;
+	}
+
+	restore_flags (flags);
+
+	return tmp;
+}
+
+#endif /* __MICROBLAZE_SYSTEM_H__ */
diff --git a/arch/microblaze/include/asm/types.h b/arch/microblaze/include/asm/types.h
new file mode 100644
index 0000000..056a313
--- /dev/null
+++ b/arch/microblaze/include/asm/types.h
@@ -0,0 +1,31 @@
+#ifndef _ASM_TYPES_H
+#define _ASM_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+typedef unsigned short umode_t;
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_TYPES_H */
diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h
new file mode 100644
index 0000000..a922122
--- /dev/null
+++ b/arch/microblaze/include/asm/u-boot.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_
+
+#include <asm-generic/u-boot.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_MICROBLAZE
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/microblaze/include/asm/unaligned.h b/arch/microblaze/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/microblaze/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
new file mode 100644
index 0000000..b6d3876
--- /dev/null
+++ b/arch/mips/include/asm/addrspace.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1996, 99 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
+ */
+#ifndef _ASM_ADDRSPACE_H
+#define _ASM_ADDRSPACE_H
+
+#include <spaces.h>
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ATYPE_
+#define _ATYPE32_
+#define _ATYPE64_
+#define _CONST64_(x)	x
+#else
+#define _ATYPE_		__PTRDIFF_TYPE__
+#define _ATYPE32_	int
+#define _ATYPE64_	__s64
+#ifdef CONFIG_64BIT
+#define _CONST64_(x)	x ## L
+#else
+#define _CONST64_(x)	x ## LL
+#endif
+#endif
+
+/*
+ *  32-bit MIPS address spaces
+ */
+#ifdef __ASSEMBLY__
+#define _ACAST32_
+#define _ACAST64_
+#else
+#define _ACAST32_		(_ATYPE_)(_ATYPE32_)	/* widen if necessary */
+#define _ACAST64_		(_ATYPE64_)		/* do _not_ narrow */
+#endif
+
+/*
+ * Returns the kernel segment base of a given address
+ */
+#define KSEGX(a)		((_ACAST32_ (a)) & 0xe0000000)
+
+/*
+ * Returns the physical address of a CKSEGx / XKPHYS address
+ */
+#define CPHYSADDR(a)		((_ACAST32_(a)) & 0x1fffffff)
+#define XPHYSADDR(a)		((_ACAST64_(a)) &			\
+				 _CONST64_(0x0000ffffffffffff))
+
+#ifdef CONFIG_64BIT
+
+/*
+ * Memory segments (64bit kernel mode addresses)
+ * The compatibility segments use the full 64-bit sign extended value.  Note
+ * the R8000 doesn't have them so don't reference these in generic MIPS code.
+ */
+#define XKUSEG			_CONST64_(0x0000000000000000)
+#define XKSSEG			_CONST64_(0x4000000000000000)
+#define XKPHYS			_CONST64_(0x8000000000000000)
+#define XKSEG			_CONST64_(0xc000000000000000)
+#define CKSEG0			_CONST64_(0xffffffff80000000)
+#define CKSEG1			_CONST64_(0xffffffffa0000000)
+#define CKSSEG			_CONST64_(0xffffffffc0000000)
+#define CKSEG3			_CONST64_(0xffffffffe0000000)
+
+#define CKSEG0ADDR(a)		(CPHYSADDR(a) | CKSEG0)
+#define CKSEG1ADDR(a)		(CPHYSADDR(a) | CKSEG1)
+#define CKSEG2ADDR(a)		(CPHYSADDR(a) | CKSEG2)
+#define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
+
+#else
+
+#define CKSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
+#define CKSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
+#define CKSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2)
+#define CKSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
+
+/*
+ * Map an address to a certain kernel segment
+ */
+#define KSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
+#define KSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
+#define KSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2)
+#define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
+
+/*
+ * Memory segments (32bit kernel mode addresses)
+ * These are the traditional names used in the 32-bit universe.
+ */
+#define KUSEG			0x00000000
+#define KSEG0			0x80000000
+#define KSEG1			0xa0000000
+#define KSEG2			0xc0000000
+#define KSEG3			0xe0000000
+
+#define CKUSEG			0x00000000
+#define CKSEG0			0x80000000
+#define CKSEG1			0xa0000000
+#define CKSEG2			0xc0000000
+#define CKSEG3			0xe0000000
+
+#endif
+
+/*
+ * Cache modes for XKPHYS address conversion macros
+ */
+#define K_CALG_COH_EXCL1_NOL2	0
+#define K_CALG_COH_SHRL1_NOL2	1
+#define K_CALG_UNCACHED		2
+#define K_CALG_NONCOHERENT	3
+#define K_CALG_COH_EXCL		4
+#define K_CALG_COH_SHAREABLE	5
+#define K_CALG_NOTUSED		6
+#define K_CALG_UNCACHED_ACCEL	7
+
+/*
+ * 64-bit address conversions
+ */
+#define PHYS_TO_XKSEG_UNCACHED(p)	PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
+#define PHYS_TO_XKSEG_CACHED(p)		PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
+#define XKPHYS_TO_PHYS(p)		((p) & TO_PHYS_MASK)
+#define PHYS_TO_XKPHYS(cm, a)		(_CONST64_(0x8000000000000000) | \
+					 (_CONST64_(cm) << 59) | (a))
+
+/*
+ * Returns the uncached address of a sdram address
+ */
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_TB0229)
+/* We use a 36 bit physical address map here and
+   cannot access physical memory directly from core */
+#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
+#else	/* !CONFIG_TB0229 */
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
+#endif	/* CONFIG_TB0229 */
+#endif	/* __ASSEMBLY__ */
+
+/*
+ * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
+ * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
+ * R8000 implements most with its 48-bit physical address space.
+ */
+#define TO_PHYS_MASK	_CONST64_(0x07ffffffffffffff)	/* 2^^59 - 1 */
+
+#ifndef CONFIG_CPU_R8000
+
+/*
+ * The R8000 doesn't have the 32-bit compat spaces so we don't define them
+ * in order to catch bugs in the source code.
+ */
+
+#define COMPAT_K1BASE32		_CONST64_(0xffffffffa0000000)
+#define PHYS_TO_COMPATK1(x)	((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
+
+#endif
+
+#define KDM_TO_PHYS(x)		(_ACAST64_ (x) & TO_PHYS_MASK)
+#define PHYS_TO_K0(x)		(_ACAST64_ (x) | CAC_BASE)
+
+#endif /* _ASM_ADDRSPACE_H */
diff --git a/arch/mips/include/asm/asm-offsets.h b/arch/mips/include/asm/asm-offsets.h
new file mode 100644
index 0000000..b722499
--- /dev/null
+++ b/arch/mips/include/asm/asm-offsets.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#include <generated/asm-offsets.h>
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
new file mode 100644
index 0000000..7abcf6d
--- /dev/null
+++ b/arch/mips/include/asm/asm.h
@@ -0,0 +1,424 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
+ * Copyright (C) 1999 by Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
+ *
+ * Some useful macros for MIPS assembler code
+ *
+ * Some of the routines below contain useless nops that will be optimized
+ * away by gas in -O mode. These nops are however required to fill delay
+ * slots in noreorder mode.
+ */
+#ifndef __ASM_ASM_H
+#define __ASM_ASM_H
+
+#include <asm/sgidefs.h>
+
+#ifndef CAT
+#ifdef __STDC__
+#define __CAT(str1, str2) str1##str2
+#else
+#define __CAT(str1, str2) str1/**/str2
+#endif
+#define CAT(str1, str2) __CAT(str1, str2)
+#endif
+
+/*
+ * PIC specific declarations
+ * Not used for the kernel but here seems to be the right place.
+ */
+#ifdef __PIC__
+#define CPRESTORE(register)				\
+		.cprestore register
+#define CPADD(register)					\
+		.cpadd	register
+#define CPLOAD(register)				\
+		.cpload register
+#else
+#define CPRESTORE(register)
+#define CPADD(register)
+#define CPLOAD(register)
+#endif
+
+#define ENTRY(symbol)					\
+		.globl	symbol;				\
+		.type	symbol, @function;		\
+		.ent	symbol, 0;			\
+symbol:
+
+/*
+ * LEAF - declare leaf routine
+ */
+#define LEAF(symbol)					\
+		.globl	symbol;				\
+		.align	2;				\
+		.type	symbol, @function;		\
+		.ent	symbol, 0;			\
+		.section .text.symbol, "x";             \
+symbol:		.frame	sp, 0, ra
+
+/*
+ * NESTED - declare nested routine entry point
+ */
+#define NESTED(symbol, framesize, rpc)			\
+		.globl	symbol;				\
+		.align	2;				\
+		.type	symbol, @function;		\
+		.ent	symbol, 0;			\
+		.section .text.symbol, "x";             \
+symbol:		.frame	sp, framesize, rpc
+
+/*
+ * END - mark end of function
+ */
+#define END(function)					\
+		.end	function;			\
+		.size	function, .-function
+
+/*
+ * EXPORT - export definition of symbol
+ */
+#define EXPORT(symbol)					\
+		.globl	symbol;				\
+symbol:
+
+/*
+ * FEXPORT - export definition of a function symbol
+ */
+#define FEXPORT(symbol)					\
+		.globl	symbol;				\
+		.type	symbol, @function;		\
+symbol:
+
+/*
+ * ABS - export absolute symbol
+ */
+#define ABS(symbol,value)				\
+		.globl	symbol;				\
+symbol		=	value
+
+#define PANIC(msg)					\
+		.set	push;				\
+		.set	reorder;			\
+		PTR_LA	a0, 8f;				 \
+		jal	panic;				\
+9:		b	9b;				\
+		.set	pop;				\
+		TEXT(msg)
+
+/*
+ * Print formatted string
+ */
+#ifdef CONFIG_PRINTK
+#define PRINT(string)					\
+		.set	push;				\
+		.set	reorder;			\
+		PTR_LA	a0, 8f;				 \
+		jal	printk;				\
+		.set	pop;				\
+		TEXT(string)
+#else
+#define PRINT(string)
+#endif
+
+#define TEXT(msg)					\
+		.pushsection .data;			\
+8:		.asciiz msg;				\
+		.popsection;
+
+/*
+ * Build text tables
+ */
+#define TTABLE(string)					\
+		.pushsection .text;			\
+		.word	1f;				\
+		.popsection				\
+		.pushsection .data;			\
+1:		.asciiz string;				\
+		.popsection
+
+/*
+ * MIPS IV pref instruction.
+ * Use with .set noreorder only!
+ *
+ * MIPS IV implementations are free to treat this as a nop.  The R5000
+ * is one of them.  So we should have an option not to use this instruction.
+ */
+#ifdef CONFIG_CPU_HAS_PREFETCH
+
+#define PREF(hint, addr)				\
+		.set	push;				\
+		.set	arch=r5000;			\
+		pref	hint, addr;			\
+		.set	pop
+
+#define PREFE(hint, addr)				\
+		.set	push;				\
+		.set	mips0;				\
+		.set	eva;				\
+		prefe	hint, addr;			\
+		.set	pop
+
+#define PREFX(hint, addr)				\
+		.set	push;				\
+		.set	arch=r5000;			\
+		prefx	hint, addr;			\
+		.set	pop
+
+#else /* !CONFIG_CPU_HAS_PREFETCH */
+
+#define PREF(hint, addr)
+#define PREFE(hint, addr)
+#define PREFX(hint, addr)
+
+#endif /* !CONFIG_CPU_HAS_PREFETCH */
+
+/*
+ * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
+ */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
+#define MOVN(rd, rs, rt)				\
+		.set	push;				\
+		.set	reorder;			\
+		beqz	rt, 9f;				\
+		move	rd, rs;				\
+		.set	pop;				\
+9:
+#define MOVZ(rd, rs, rt)				\
+		.set	push;				\
+		.set	reorder;			\
+		bnez	rt, 9f;				\
+		move	rd, rs;				\
+		.set	pop;				\
+9:
+#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
+#define MOVN(rd, rs, rt)				\
+		.set	push;				\
+		.set	noreorder;			\
+		bnezl	rt, 9f;				\
+		 move	rd, rs;				\
+		.set	pop;				\
+9:
+#define MOVZ(rd, rs, rt)				\
+		.set	push;				\
+		.set	noreorder;			\
+		beqzl	rt, 9f;				\
+		 move	rd, rs;				\
+		.set	pop;				\
+9:
+#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
+#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
+    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+#define MOVN(rd, rs, rt)				\
+		movn	rd, rs, rt
+#define MOVZ(rd, rs, rt)				\
+		movz	rd, rs, rt
+#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
+
+/*
+ * Stack alignment
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define ALSZ	7
+#define ALMASK	~7
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define ALSZ	15
+#define ALMASK	~15
+#endif
+
+/*
+ * Macros to handle different pointer/register sizes for 32/64-bit code
+ */
+
+/*
+ * Size of a register
+ */
+#ifdef __mips64
+#define SZREG	8
+#else
+#define SZREG	4
+#endif
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define REG_S		sw
+#define REG_L		lw
+#define REG_SUBU	subu
+#define REG_ADDU	addu
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define REG_S		sd
+#define REG_L		ld
+#define REG_SUBU	dsubu
+#define REG_ADDU	daddu
+#endif
+
+/*
+ * How to add/sub/load/store/shift C int variables.
+ */
+#if (_MIPS_SZINT == 32)
+#define INT_ADD		add
+#define INT_ADDU	addu
+#define INT_ADDI	addi
+#define INT_ADDIU	addiu
+#define INT_SUB		sub
+#define INT_SUBU	subu
+#define INT_L		lw
+#define INT_S		sw
+#define INT_SLL		sll
+#define INT_SLLV	sllv
+#define INT_SRL		srl
+#define INT_SRLV	srlv
+#define INT_SRA		sra
+#define INT_SRAV	srav
+#endif
+
+#if (_MIPS_SZINT == 64)
+#define INT_ADD		dadd
+#define INT_ADDU	daddu
+#define INT_ADDI	daddi
+#define INT_ADDIU	daddiu
+#define INT_SUB		dsub
+#define INT_SUBU	dsubu
+#define INT_L		ld
+#define INT_S		sd
+#define INT_SLL		dsll
+#define INT_SLLV	dsllv
+#define INT_SRL		dsrl
+#define INT_SRLV	dsrlv
+#define INT_SRA		dsra
+#define INT_SRAV	dsrav
+#endif
+
+/*
+ * How to add/sub/load/store/shift C long variables.
+ */
+#if (_MIPS_SZLONG == 32)
+#define LONG_ADD	add
+#define LONG_ADDU	addu
+#define LONG_ADDI	addi
+#define LONG_ADDIU	addiu
+#define LONG_SUB	sub
+#define LONG_SUBU	subu
+#define LONG_L		lw
+#define LONG_S		sw
+#define LONG_SP		swp
+#define LONG_SLL	sll
+#define LONG_SLLV	sllv
+#define LONG_SRL	srl
+#define LONG_SRLV	srlv
+#define LONG_SRA	sra
+#define LONG_SRAV	srav
+
+#define LONG		.word
+#define LONGSIZE	4
+#define LONGMASK	3
+#define LONGLOG		2
+#endif
+
+#if (_MIPS_SZLONG == 64)
+#define LONG_ADD	dadd
+#define LONG_ADDU	daddu
+#define LONG_ADDI	daddi
+#define LONG_ADDIU	daddiu
+#define LONG_SUB	dsub
+#define LONG_SUBU	dsubu
+#define LONG_L		ld
+#define LONG_S		sd
+#define LONG_SP		sdp
+#define LONG_SLL	dsll
+#define LONG_SLLV	dsllv
+#define LONG_SRL	dsrl
+#define LONG_SRLV	dsrlv
+#define LONG_SRA	dsra
+#define LONG_SRAV	dsrav
+
+#define LONG		.dword
+#define LONGSIZE	8
+#define LONGMASK	7
+#define LONGLOG		3
+#endif
+
+/*
+ * How to add/sub/load/store/shift pointers.
+ */
+#if (_MIPS_SZPTR == 32)
+#define PTR_ADD		add
+#define PTR_ADDU	addu
+#define PTR_ADDI	addi
+#define PTR_ADDIU	addiu
+#define PTR_SUB		sub
+#define PTR_SUBU	subu
+#define PTR_L		lw
+#define PTR_S		sw
+#define PTR_LA		la
+#define PTR_LI		li
+#define PTR_SLL		sll
+#define PTR_SLLV	sllv
+#define PTR_SRL		srl
+#define PTR_SRLV	srlv
+#define PTR_SRA		sra
+#define PTR_SRAV	srav
+
+#define PTR_SCALESHIFT	2
+
+#define PTR		.word
+#define PTRSIZE		4
+#define PTRLOG		2
+#endif
+
+#if (_MIPS_SZPTR == 64)
+#define PTR_ADD		dadd
+#define PTR_ADDU	daddu
+#define PTR_ADDI	daddi
+#define PTR_ADDIU	daddiu
+#define PTR_SUB		dsub
+#define PTR_SUBU	dsubu
+#define PTR_L		ld
+#define PTR_S		sd
+#define PTR_LA		dla
+#define PTR_LI		dli
+#define PTR_SLL		dsll
+#define PTR_SLLV	dsllv
+#define PTR_SRL		dsrl
+#define PTR_SRLV	dsrlv
+#define PTR_SRA		dsra
+#define PTR_SRAV	dsrav
+
+#define PTR_SCALESHIFT	3
+
+#define PTR		.dword
+#define PTRSIZE		8
+#define PTRLOG		3
+#endif
+
+/*
+ * Some cp0 registers were extended to 64bit for MIPS III.
+ */
+#if (_MIPS_SIM == _MIPS_SIM_ABI32)
+#define MFC0		mfc0
+#define MTC0		mtc0
+#endif
+#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
+#define MFC0		dmfc0
+#define MTC0		dmtc0
+#endif
+
+#define SSNOP		sll zero, zero, 1
+
+#ifdef CONFIG_SGI_IP28
+/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
+#include <asm/cacheops.h>
+#define R10KCBARRIER(addr)  cache   CACHE_BARRIER, addr;
+#else
+#define R10KCBARRIER(addr)
+#endif
+
+#endif /* __ASM_ASM_H */
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
new file mode 100644
index 0000000..c4f08b7
--- /dev/null
+++ b/arch/mips/include/asm/atomic.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _MIPS_ATOMIC_H
+#define _MIPS_ATOMIC_H
+
+#include <asm/system.h>
+#include <asm-generic/atomic.h>
+
+#endif
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
new file mode 100644
index 0000000..321d322
--- /dev/null
+++ b/arch/mips/include/asm/bitops.h
@@ -0,0 +1,903 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 1994 - 1997, 1999, 2000  Ralf Baechle (ralf@gnu.org)
+ * Copyright (c) 2000  Silicon Graphics, Inc.
+ */
+#ifndef _ASM_BITOPS_H
+#define _ASM_BITOPS_H
+
+#include <linux/types.h>
+#include <asm/byteorder.h>		/* sigh ... */
+
+#ifdef __KERNEL__
+
+#include <asm/sgidefs.h>
+#include <asm/system.h>
+
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+
+/*
+ * Only disable interrupt for kernel mode stuff to keep usermode stuff
+ * that dares to use kernel include files alive.
+ */
+#define __bi_flags unsigned long flags
+#define __bi_cli() __cli()
+#define __bi_save_flags(x) __save_flags(x)
+#define __bi_save_and_cli(x) __save_and_cli(x)
+#define __bi_restore_flags(x) __restore_flags(x)
+#else
+#define __bi_flags
+#define __bi_cli()
+#define __bi_save_flags(x)
+#define __bi_save_and_cli(x)
+#define __bi_restore_flags(x)
+#endif /* __KERNEL__ */
+
+#ifdef CONFIG_CPU_HAS_LLSC
+
+#include <asm/mipsregs.h>
+
+/*
+ * These functions for MIPS ISA > 1 are interrupt and SMP proof and
+ * interrupt friendly
+ */
+
+/*
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered.  See __set_bit()
+ * if you do not require the atomic guarantees.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static __inline__ void
+set_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp;
+
+	__asm__ __volatile__(
+		"1:\tll\t%0, %1\t\t# set_bit\n\t"
+		"or\t%0, %2\n\t"
+		"sc\t%0, %1\n\t"
+		"beqz\t%0, 1b"
+		: "=&r" (temp), "=m" (*m)
+		: "ir" (1UL << (nr & 0x1f)), "m" (*m));
+}
+
+/*
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static __inline__ void __set_bit(int nr, volatile void * addr)
+{
+	unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
+
+	*m |= 1UL << (nr & 31);
+}
+#define PLATFORM__SET_BIT
+
+/*
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+static __inline__ void
+clear_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp;
+
+	__asm__ __volatile__(
+		"1:\tll\t%0, %1\t\t# clear_bit\n\t"
+		"and\t%0, %2\n\t"
+		"sc\t%0, %1\n\t"
+		"beqz\t%0, 1b\n\t"
+		: "=&r" (temp), "=m" (*m)
+		: "ir" (~(1UL << (nr & 0x1f))), "m" (*m));
+}
+
+/*
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static __inline__ void
+change_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp;
+
+	__asm__ __volatile__(
+		"1:\tll\t%0, %1\t\t# change_bit\n\t"
+		"xor\t%0, %2\n\t"
+		"sc\t%0, %1\n\t"
+		"beqz\t%0, 1b"
+		: "=&r" (temp), "=m" (*m)
+		: "ir" (1UL << (nr & 0x1f)), "m" (*m));
+}
+
+/*
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static __inline__ void __change_bit(int nr, volatile void * addr)
+{
+	unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
+
+	*m ^= 1UL << (nr & 31);
+}
+
+/*
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int
+test_and_set_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp, res;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# test_and_set_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"or\t%2, %0, %3\n\t"
+		"sc\t%2, %1\n\t"
+		"beqz\t%2, 1b\n\t"
+		" and\t%2, %0, %3\n\t"
+		".set\treorder"
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & 0x1f)), "m" (*m)
+		: "memory");
+
+	return res != 0;
+}
+
+/*
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
+{
+	int mask, retval;
+	volatile int *a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+
+	return retval;
+}
+
+/*
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int
+test_and_clear_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp, res;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# test_and_clear_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"or\t%2, %0, %3\n\t"
+		"xor\t%2, %3\n\t"
+		"sc\t%2, %1\n\t"
+		"beqz\t%2, 1b\n\t"
+		" and\t%2, %0, %3\n\t"
+		".set\treorder"
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & 0x1f)), "m" (*m)
+		: "memory");
+
+	return res != 0;
+}
+
+/*
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+
+	return retval;
+}
+
+/*
+ * test_and_change_bit - Change a bit and return its new value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int
+test_and_change_bit(int nr, volatile void *addr)
+{
+	unsigned long *m = ((unsigned long *) addr) + (nr >> 5);
+	unsigned long temp, res;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t# test_and_change_bit\n"
+		"1:\tll\t%0, %1\n\t"
+		"xor\t%2, %0, %3\n\t"
+		"sc\t%2, %1\n\t"
+		"beqz\t%2, 1b\n\t"
+		" and\t%2, %0, %3\n\t"
+		".set\treorder"
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & 0x1f)), "m" (*m)
+		: "memory");
+
+	return res != 0;
+}
+
+/*
+ * __test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+
+	return retval;
+}
+
+#else /* MIPS I */
+
+/*
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered.  See __set_bit()
+ * if you do not require the atomic guarantees.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static __inline__ void set_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	*a |= mask;
+	__bi_restore_flags(flags);
+}
+
+/*
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static __inline__ void __set_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+/*
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+static __inline__ void clear_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	*a &= ~mask;
+	__bi_restore_flags(flags);
+}
+
+/*
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static __inline__ void change_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	*a ^= mask;
+	__bi_restore_flags(flags);
+}
+
+/*
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static __inline__ void __change_bit(int nr, volatile void * addr)
+{
+	unsigned long * m = ((unsigned long *) addr) + (nr >> 5);
+
+	*m ^= 1UL << (nr & 31);
+}
+
+/*
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int test_and_set_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	__bi_restore_flags(flags);
+
+	return retval;
+}
+
+/*
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+
+	return retval;
+}
+
+/*
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	__bi_restore_flags(flags);
+
+	return retval;
+}
+
+/*
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+
+	return retval;
+}
+
+/*
+ * test_and_change_bit - Change a bit and return its new value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int test_and_change_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+	__bi_flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	__bi_save_and_cli(flags);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	__bi_restore_flags(flags);
+
+	return retval;
+}
+
+/*
+ * __test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile int	*a = addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+
+	return retval;
+}
+
+#undef __bi_flags
+#undef __bi_cli
+#undef __bi_save_flags
+#undef __bi_restore_flags
+
+#endif /* MIPS I */
+
+/*
+ * test_bit - Determine whether a bit is set
+ * @nr: bit number to test
+ * @addr: Address to start counting from
+ */
+static __inline__ int test_bit(int nr, const volatile void *addr)
+{
+	return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0;
+}
+
+#ifndef __MIPSEB__
+
+/* Little endian versions. */
+
+/*
+ * find_first_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first zero bit, not the number of the byte
+ * containing a bit.
+ */
+static __inline__ int find_first_zero_bit (void *addr, unsigned size)
+{
+	unsigned long dummy;
+	int res;
+
+	if (!size)
+		return 0;
+
+	__asm__ (".set\tnoreorder\n\t"
+		".set\tnoat\n"
+		"1:\tsubu\t$1,%6,%0\n\t"
+		"blez\t$1,2f\n\t"
+		"lw\t$1,(%5)\n\t"
+		"addiu\t%5,4\n\t"
+#if (_MIPS_ISA == _MIPS_ISA_MIPS2 ) || (_MIPS_ISA == _MIPS_ISA_MIPS3 ) || \
+    (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5 ) || \
+    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
+		"beql\t%1,$1,1b\n\t"
+		"addiu\t%0,32\n\t"
+#else
+		"addiu\t%0,32\n\t"
+		"beq\t%1,$1,1b\n\t"
+		"nop\n\t"
+		"subu\t%0,32\n\t"
+#endif
+#ifdef __MIPSEB__
+#error "Fix this for big endian"
+#endif /* __MIPSEB__ */
+		"li\t%1,1\n"
+		"1:\tand\t%2,$1,%1\n\t"
+		"beqz\t%2,2f\n\t"
+		"sll\t%1,%1,1\n\t"
+		"bnez\t%1,1b\n\t"
+		"add\t%0,%0,1\n\t"
+		".set\tat\n\t"
+		".set\treorder\n"
+		"2:"
+		: "=r" (res), "=r" (dummy), "=r" (addr)
+		: "0" ((signed int) 0), "1" ((unsigned int) 0xffffffff),
+		  "2" (addr), "r" (size)
+		: "$1");
+
+	return res;
+}
+
+/*
+ * find_next_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+static __inline__ int find_next_zero_bit (void * addr, int size, int offset)
+{
+	unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
+	int set = 0, bit = offset & 31, res;
+	unsigned long dummy;
+
+	if (bit) {
+		/*
+		 * Look for zero in first byte
+		 */
+#ifdef __MIPSEB__
+#error "Fix this for big endian byte order"
+#endif
+		__asm__(".set\tnoreorder\n\t"
+			".set\tnoat\n"
+			"1:\tand\t$1,%4,%1\n\t"
+			"beqz\t$1,1f\n\t"
+			"sll\t%1,%1,1\n\t"
+			"bnez\t%1,1b\n\t"
+			"addiu\t%0,1\n\t"
+			".set\tat\n\t"
+			".set\treorder\n"
+			"1:"
+			: "=r" (set), "=r" (dummy)
+			: "0" (0), "1" (1 << bit), "r" (*p)
+			: "$1");
+		if (set < (32 - bit))
+			return set + offset;
+		set = 32 - bit;
+		p++;
+	}
+	/*
+	 * No zero yet, search remaining full bytes for a zero
+	 */
+	res = find_first_zero_bit(p, size - 32 * (p - (unsigned int *) addr));
+	return offset + set + res;
+}
+
+#endif /* !(__MIPSEB__) */
+
+/*
+ * ffz - find first zero in word.
+ * @word: The word to search
+ *
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+static __inline__ unsigned long ffz(unsigned long word)
+{
+	unsigned int	__res;
+	unsigned int	mask = 1;
+
+	__asm__ (
+		".set\tnoreorder\n\t"
+		".set\tnoat\n\t"
+		"move\t%0,$0\n"
+		"1:\tand\t$1,%2,%1\n\t"
+		"beqz\t$1,2f\n\t"
+		"sll\t%1,1\n\t"
+		"bnez\t%1,1b\n\t"
+		"addiu\t%0,1\n\t"
+		".set\tat\n\t"
+		".set\treorder\n"
+		"2:\n\t"
+		: "=&r" (__res), "=r" (mask)
+		: "r" (word), "1" (mask)
+		: "$1");
+
+	return __res;
+}
+
+#ifdef __KERNEL__
+
+/*
+ * hweightN - returns the hamming weight of a N-bit word
+ * @x: the word to weigh
+ *
+ * The Hamming Weight of a number is the total number of bits set in it.
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+#ifdef __MIPSEB__
+/*
+ * find_next_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
+{
+	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp |= ~0UL >> (32-offset);
+		if (size < 32)
+			goto found_first;
+		if (~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size & ~31UL) {
+		if (~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	tmp |= ~0UL << size;
+found_middle:
+	return result + ffz(tmp);
+}
+
+/* Linus sez that gcc can optimize the following correctly, we'll see if this
+ * holds on the Sparc as it does for the ALPHA.
+ */
+
+#if 0 /* Fool kernel-doc since it doesn't do macros yet */
+/*
+ * find_first_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first zero bit, not the number of the byte
+ * containing a bit.
+ */
+static int find_first_zero_bit (void *addr, unsigned size);
+#endif
+
+#define find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
+
+#endif /* (__MIPSEB__) */
+
+/* Now for the ext2 filesystem bit operations and helper routines. */
+
+#ifdef __MIPSEB__
+static __inline__ int ext2_set_bit(int nr, void * addr)
+{
+	int		mask, retval, flags;
+	unsigned char	*ADDR = (unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	save_and_cli(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR |= mask;
+	restore_flags(flags);
+	return retval;
+}
+
+static __inline__ int ext2_clear_bit(int nr, void * addr)
+{
+	int		mask, retval, flags;
+	unsigned char	*ADDR = (unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	save_and_cli(flags);
+	retval = (mask & *ADDR) != 0;
+	*ADDR &= ~mask;
+	restore_flags(flags);
+	return retval;
+}
+
+static __inline__ int ext2_test_bit(int nr, const void * addr)
+{
+	int			mask;
+	const unsigned char	*ADDR = (const unsigned char *) addr;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	return ((mask & *ADDR) != 0);
+}
+
+#define ext2_find_first_zero_bit(addr, size) \
+	ext2_find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
+{
+	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
+	unsigned long result = offset & ~31UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if(offset) {
+		/* We hold the little endian value in tmp, but then the
+		 * shift is illegal. So we could keep a big endian value
+		 * in tmp, like this:
+		 *
+		 * tmp = __swab32(*(p++));
+		 * tmp |= ~0UL >> (32-offset);
+		 *
+		 * but this would decrease preformance, so we change the
+		 * shift:
+		 */
+		tmp = *(p++);
+		tmp |= __swab32(~0UL >> (32-offset));
+		if(size < 32)
+			goto found_first;
+		if(~tmp)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while(size & ~31UL) {
+		if(~(tmp = *(p++)))
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if(!size)
+		return result;
+	tmp = *p;
+
+found_first:
+	/* tmp is little endian, so we would have to swab the shift,
+	 * see above. But then we have to swab tmp below for ffz, so
+	 * we might as well do this here.
+	 */
+	return result + ffz(__swab32(tmp) | (~0UL << size));
+found_middle:
+	return result + ffz(__swab32(tmp));
+}
+#else /* !(__MIPSEB__) */
+
+/* Native ext2 byte ordering, just collapse using defines. */
+#define ext2_set_bit(nr, addr) test_and_set_bit((nr), (addr))
+#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr), (addr))
+#define ext2_test_bit(nr, addr) test_bit((nr), (addr))
+#define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size))
+#define ext2_find_next_zero_bit(addr, size, offset) \
+		find_next_zero_bit((addr), (size), (offset))
+
+#endif /* !(__MIPSEB__) */
+
+/*
+ * Bitmap functions for the minix filesystem.
+ * FIXME: These assume that Minix uses the native byte/bitorder.
+ * This limits the Minix filesystem's value for data exchange very much.
+ */
+#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
+
+#endif /* _ASM_BITOPS_H */
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
new file mode 100644
index 0000000..eef17b8
--- /dev/null
+++ b/arch/mips/include/asm/byteorder.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
+ */
+#ifndef _ASM_BYTEORDER_H
+#define _ASM_BYTEORDER_H
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+#ifdef CONFIG_CPU_MIPSR2
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
+{
+	__asm__(
+	"	wsbh	%0, %1			\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+#define __arch__swab16(x)	___arch__swab16(x)
+
+static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
+{
+	__asm__(
+	"	wsbh	%0, %1			\n"
+	"	rotr	%0, %0, 16		\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+#define __arch__swab32(x)	___arch__swab32(x)
+
+#ifdef CONFIG_CPU_MIPS64_R2
+
+static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+{
+	__asm__(
+	"	dsbh	%0, %1			\n"
+	"	dshd	%0, %0			\n"
+	"	drotr	%0, %0, 32		\n"
+	: "=r" (x)
+	: "r" (x));
+
+	return x;
+}
+
+#define __arch__swab64(x)	___arch__swab64(x)
+
+#endif /* CONFIG_CPU_MIPS64_R2 */
+
+#endif /* CONFIG_CPU_MIPSR2 */
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __GNUC__ */
+
+#if defined(__MIPSEB__)
+#  include <linux/byteorder/big_endian.h>
+#elif defined(__MIPSEL__)
+#  include <linux/byteorder/little_endian.h>
+#else
+#  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
+#endif
+
+#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
new file mode 100644
index 0000000..00696e6
--- /dev/null
+++ b/arch/mips/include/asm/cache.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __MIPS_CACHE_H__
+#define __MIPS_CACHE_H__
+
+#define L1_CACHE_SHIFT		CONFIG_MIPS_L1_CACHE_SHIFT
+#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
+
+#define ARCH_DMA_MINALIGN	(L1_CACHE_BYTES)
+
+/*
+ * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
+ * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
+ * of ARCH_DMA_MINALIGN for now.
+ */
+#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+
+#ifndef __ASSEMBLY__
+/**
+ * mips_cache_probe() - Probe the properties of the caches
+ *
+ * Call this to probe the properties such as line sizes of the caches
+ * present in the system, if any. This must be done before cache maintenance
+ * functions such as flush_cache may be called.
+ */
+void mips_cache_probe(void);
+#endif
+
+#endif /* __MIPS_CACHE_H__ */
diff --git a/arch/mips/include/asm/cachectl.h b/arch/mips/include/asm/cachectl.h
new file mode 100644
index 0000000..805da6f
--- /dev/null
+++ b/arch/mips/include/asm/cachectl.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ */
+#ifndef	_ASM_CACHECTL
+#define	_ASM_CACHECTL
+
+/*
+ * Options for cacheflush system call
+ */
+#define	ICACHE	(1<<0)		/* flush instruction cache        */
+#define	DCACHE	(1<<1)		/* writeback and flush data cache */
+#define	BCACHE	(ICACHE|DCACHE)	/* flush both caches              */
+
+/*
+ * Caching modes for the cachectl(2) call
+ *
+ * cachectl(2) is currently not supported and returns ENOSYS.
+ */
+#define CACHEABLE	0	/* make pages cacheable */
+#define UNCACHEABLE	1	/* make pages uncacheable */
+
+#endif	/* _ASM_CACHECTL */
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
new file mode 100644
index 0000000..98b67cc
--- /dev/null
+++ b/arch/mips/include/asm/cacheops.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Cache operations for the cache instruction.
+ *
+ * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
+ * (C) Copyright 1999 Silicon Graphics, Inc.
+ */
+#ifndef	__ASM_CACHEOPS_H
+#define	__ASM_CACHEOPS_H
+
+#ifndef __ASSEMBLY__
+
+static inline void mips_cache(int op, const volatile void *addr)
+{
+#ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
+	__builtin_mips_cache(op, addr);
+#else
+	__asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
+#endif
+}
+
+#define MIPS32_WHICH_ICACHE                    0x0
+#define MIPS32_FETCH_AND_LOCK                  0x7
+
+#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
+
+/* Prefetch and lock instructions into cache */
+static inline void icache_lock(void *func, size_t len)
+{
+	int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
+
+	for (i = 0; i < lines; i++) {
+		asm volatile (" cache %0, %1(%2)"
+			      : /* No Output */
+			      : "I" ICACHE_LOAD_LOCK,
+				"n" (i * ARCH_DMA_MINALIGN),
+				"r" (func)
+			      : /* No Clobbers */);
+	}
+}
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Cache Operations available on all MIPS processors with R4000-style caches
+ */
+#define INDEX_INVALIDATE_I      0x00
+#define INDEX_WRITEBACK_INV_D   0x01
+#define INDEX_LOAD_TAG_I	0x04
+#define INDEX_LOAD_TAG_D	0x05
+#define INDEX_STORE_TAG_I	0x08
+#define INDEX_STORE_TAG_D	0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define HIT_INVALIDATE_I	0x00
+#else
+#define HIT_INVALIDATE_I	0x10
+#endif
+#define HIT_INVALIDATE_D	0x11
+#define HIT_WRITEBACK_INV_D	0x15
+
+/*
+ * R4000-specific cacheops
+ */
+#define CREATE_DIRTY_EXCL_D	0x0d
+#define FILL			0x14
+#define HIT_WRITEBACK_I		0x18
+#define HIT_WRITEBACK_D		0x19
+
+/*
+ * R4000SC and R4400SC-specific cacheops
+ */
+#define INDEX_INVALIDATE_SI     0x02
+#define INDEX_WRITEBACK_INV_SD  0x03
+#define INDEX_LOAD_TAG_SI	0x06
+#define INDEX_LOAD_TAG_SD	0x07
+#define INDEX_STORE_TAG_SI	0x0A
+#define INDEX_STORE_TAG_SD	0x0B
+#define CREATE_DIRTY_EXCL_SD	0x0f
+#define HIT_INVALIDATE_SI	0x12
+#define HIT_INVALIDATE_SD	0x13
+#define HIT_WRITEBACK_INV_SD	0x17
+#define HIT_WRITEBACK_SD	0x1b
+#define HIT_SET_VIRTUAL_SI	0x1e
+#define HIT_SET_VIRTUAL_SD	0x1f
+
+/*
+ * R5000-specific cacheops
+ */
+#define R5K_PAGE_INVALIDATE_S	0x17
+
+/*
+ * RM7000-specific cacheops
+ */
+#define PAGE_INVALIDATE_T	0x16
+
+/*
+ * R10000-specific cacheops
+ *
+ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
+ * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
+ */
+#define INDEX_WRITEBACK_INV_S	0x03
+#define INDEX_LOAD_TAG_S	0x07
+#define INDEX_STORE_TAG_S	0x0B
+#define HIT_INVALIDATE_S	0x13
+#define CACHE_BARRIER		0x14
+#define HIT_WRITEBACK_INV_S	0x17
+#define INDEX_LOAD_DATA_I	0x18
+#define INDEX_LOAD_DATA_D	0x19
+#define INDEX_LOAD_DATA_S	0x1b
+#define INDEX_STORE_DATA_I	0x1c
+#define INDEX_STORE_DATA_D	0x1d
+#define INDEX_STORE_DATA_S	0x1f
+
+#endif	/* __ASM_CACHEOPS_H */
diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h
new file mode 100644
index 0000000..8f37471
--- /dev/null
+++ b/arch/mips/include/asm/cm.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MIPS Coherence Manager (CM) Register Definitions
+ *
+ * Copyright (c) 2016 Imagination Technologies Ltd.
+ */
+#ifndef __MIPS_ASM_CM_H__
+#define __MIPS_ASM_CM_H__
+
+/* Global Control Register (GCR) offsets */
+#define GCR_BASE			0x0008
+#define GCR_BASE_UPPER			0x000c
+#define GCR_REV				0x0030
+#define GCR_L2_CONFIG			0x0130
+#define GCR_L2_TAG_ADDR			0x0600
+#define GCR_L2_TAG_ADDR_UPPER		0x0604
+#define GCR_L2_TAG_STATE		0x0608
+#define GCR_L2_TAG_STATE_UPPER		0x060c
+#define GCR_L2_DATA			0x0610
+#define GCR_L2_DATA_UPPER		0x0614
+#define GCR_Cx_COHERENCE		0x2008
+
+/* GCR_REV CM versions */
+#define GCR_REV_CM3			0x0800
+
+/* GCR_L2_CONFIG fields */
+#define GCR_L2_CONFIG_ASSOC_SHIFT	0
+#define GCR_L2_CONFIG_ASSOC_BITS	8
+#define GCR_L2_CONFIG_LINESZ_SHIFT	8
+#define GCR_L2_CONFIG_LINESZ_BITS	4
+#define GCR_L2_CONFIG_SETSZ_SHIFT	12
+#define GCR_L2_CONFIG_SETSZ_BITS	4
+#define GCR_L2_CONFIG_BYPASS		(1 << 20)
+
+/* GCR_Cx_COHERENCE */
+#define GCR_Cx_COHERENCE_DOM_EN		(0xff << 0)
+#define GCR_Cx_COHERENCE_EN		(0x1 << 0)
+
+#ifndef __ASSEMBLY__
+
+#include <asm/io.h>
+
+static inline void *mips_cm_base(void)
+{
+	return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
+}
+
+static inline unsigned long mips_cm_l2_line_size(void)
+{
+	unsigned long l2conf, line_sz;
+
+	l2conf = __raw_readl(mips_cm_base() + GCR_L2_CONFIG);
+
+	line_sz = l2conf >> GCR_L2_CONFIG_LINESZ_SHIFT;
+	line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
+	return line_sz ? (2 << line_sz) : 0;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __MIPS_ASM_CM_H__ */
diff --git a/arch/mips/include/asm/config.h b/arch/mips/include/asm/config.h
new file mode 100644
index 0000000..7ea4436
--- /dev/null
+++ b/arch/mips/include/asm/config.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#endif
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
new file mode 100644
index 0000000..11a577c
--- /dev/null
+++ b/arch/mips/include/asm/cpu-features.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004  Maciej W. Rozycki
+ */
+#ifndef __ASM_CPU_FEATURES_H
+#define __ASM_CPU_FEATURES_H
+
+#include <cpu-feature-overrides.h>
+
+#ifdef CONFIG_32BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits			0
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses	0
+# endif
+#endif
+
+#ifdef CONFIG_64BIT
+# ifndef cpu_has_64bits
+# define cpu_has_64bits			1
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses	1
+# endif
+#endif
+
+#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
new file mode 100644
index 0000000..7b4ad08
--- /dev/null
+++ b/arch/mips/include/asm/global_data.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include <asm/regdef.h>
+
+/* Architecture-specific global data */
+struct arch_global_data {
+#ifdef CONFIG_DYNAMIC_IO_PORT_BASE
+	unsigned long io_port_base;
+#endif
+#ifdef CONFIG_ARCH_ATH79
+	unsigned long id;
+	unsigned long soc;
+	unsigned long rev;
+	unsigned long ver;
+#endif
+#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
+	unsigned short l1i_line_size;
+	unsigned short l1d_line_size;
+#endif
+#ifdef CONFIG_MIPS_L2_CACHE
+	unsigned short l2_line_size;
+#endif
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("k0")
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/mips/include/asm/gpio.h b/arch/mips/include/asm/gpio.h
new file mode 100644
index 0000000..306ab4c
--- /dev/null
+++ b/arch/mips/include/asm/gpio.h
@@ -0,0 +1 @@
+#include <asm-generic/gpio.h>
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
new file mode 100644
index 0000000..7c40e41
--- /dev/null
+++ b/arch/mips/include/asm/io.h
@@ -0,0 +1,585 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1994, 1995 Waldorf GmbH
+ * Copyright (C) 1994 - 2000, 06 Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
+ *	Author: Maciej W. Rozycki <macro@mips.com>
+ */
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+#include <linux/bug.h>
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#include <asm/addrspace.h>
+#include <asm/byteorder.h>
+#include <asm/cpu-features.h>
+#include <asm/pgtable-bits.h>
+#include <asm/processor.h>
+#include <asm/string.h>
+
+#include <ioremap.h>
+#include <mangle-port.h>
+#include <spaces.h>
+
+/*
+ * Raw operations are never swapped in software.  OTOH values that raw
+ * operations are working on may or may not have been swapped by the bus
+ * hardware.  An example use would be for flash memory that's used for
+ * execute in place.
+ */
+# define __raw_ioswabb(a, x)	(x)
+# define __raw_ioswabw(a, x)	(x)
+# define __raw_ioswabl(a, x)	(x)
+# define __raw_ioswabq(a, x)	(x)
+# define ____raw_ioswabq(a, x)	(x)
+
+/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
+
+#define IO_SPACE_LIMIT 0xffff
+
+#ifdef CONFIG_DYNAMIC_IO_PORT_BASE
+
+static inline ulong mips_io_port_base(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	return gd->arch.io_port_base;
+}
+
+static inline void set_io_port_base(unsigned long base)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->arch.io_port_base = base;
+	barrier();
+}
+
+#else /* !CONFIG_DYNAMIC_IO_PORT_BASE */
+
+static inline ulong mips_io_port_base(void)
+{
+	return 0;
+}
+
+static inline void set_io_port_base(unsigned long base)
+{
+	BUG_ON(base);
+}
+
+#endif /* !CONFIG_DYNAMIC_IO_PORT_BASE */
+
+/*
+ *     virt_to_phys    -       map virtual addresses to physical
+ *     @address: address to remap
+ *
+ *     The returned physical address is the physical (CPU) mapping for
+ *     the memory address given. It is only valid to use this function on
+ *     addresses directly mapped or allocated via kmalloc.
+ *
+ *     This function does not give bus mappings for DMA transfers. In
+ *     almost all conceivable cases a device driver should not be using
+ *     this function
+ */
+static inline unsigned long virt_to_phys(volatile const void *address)
+{
+	unsigned long addr = (unsigned long)address;
+
+	/* this corresponds to kernel implementation of __pa() */
+#ifdef CONFIG_64BIT
+	if (addr < CKSEG0)
+		return XPHYSADDR(addr);
+#endif
+	return CPHYSADDR(addr);
+}
+#define virt_to_phys virt_to_phys
+
+/*
+ *     phys_to_virt    -       map physical address to virtual
+ *     @address: address to remap
+ *
+ *     The returned virtual address is a current CPU mapping for
+ *     the memory address given. It is only valid to use this function on
+ *     addresses that have a kernel mapping
+ *
+ *     This function does not handle bus mappings for DMA transfers. In
+ *     almost all conceivable cases a device driver should not be using
+ *     this function
+ */
+static inline void *phys_to_virt(unsigned long address)
+{
+	return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
+}
+#define phys_to_virt phys_to_virt
+
+/*
+ * ISA I/O bus memory addresses are 1:1 with the physical address.
+ */
+static inline unsigned long isa_virt_to_bus(volatile void *address)
+{
+	return (unsigned long)address - PAGE_OFFSET;
+}
+
+static inline void *isa_bus_to_virt(unsigned long address)
+{
+	return (void *)(address + PAGE_OFFSET);
+}
+
+#define isa_page_to_bus page_to_phys
+
+/*
+ * However PCI ones are not necessarily 1:1 and therefore these interfaces
+ * are forbidden in portable PCI drivers.
+ *
+ * Allow them for x86 for legacy drivers, though.
+ */
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
+
+static inline void __iomem *__ioremap_mode(phys_addr_t offset, unsigned long size,
+	unsigned long flags)
+{
+	void __iomem *addr;
+	phys_addr_t phys_addr;
+
+	addr = plat_ioremap(offset, size, flags);
+	if (addr)
+		return addr;
+
+	phys_addr = fixup_bigphys_addr(offset, size);
+	return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr);
+}
+
+/*
+ * ioremap     -   map bus memory into CPU space
+ * @offset:    bus address of the memory
+ * @size:      size of the resource to map
+ *
+ * ioremap performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ */
+#define ioremap(offset, size)						\
+	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
+
+/*
+ * ioremap_nocache     -   map bus memory into CPU space
+ * @offset:    bus address of the memory
+ * @size:      size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked uncachable
+ * on the CPU as well as honouring existing caching rules from things like
+ * the PCI bus. Note that there are other caches and buffers on many
+ * busses. In particular driver authors should read up on PCI writes
+ *
+ * It's useful if some control registers are in such an area and
+ * write combining or read caching is not desirable:
+ */
+#define ioremap_nocache(offset, size)					\
+	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
+#define ioremap_uc ioremap_nocache
+
+/*
+ * ioremap_cachable -	map bus memory into CPU space
+ * @offset:	    bus address of the memory
+ * @size:	    size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked cachable by
+ * the CPU.  Also enables full write-combining.	 Useful for some
+ * memory-like regions on I/O busses.
+ */
+#define ioremap_cachable(offset, size)					\
+	__ioremap_mode((offset), (size), _page_cachable_default)
+
+/*
+ * These two are MIPS specific ioremap variant.	 ioremap_cacheable_cow
+ * requests a cachable mapping, ioremap_uncached_accelerated requests a
+ * mapping using the uncached accelerated mode which isn't supported on
+ * all processors.
+ */
+#define ioremap_cacheable_cow(offset, size)				\
+	__ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
+#define ioremap_uncached_accelerated(offset, size)			\
+	__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
+
+static inline void iounmap(const volatile void __iomem *addr)
+{
+	plat_iounmap(addr);
+}
+
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define war_octeon_io_reorder_wmb()		wmb()
+#else
+#define war_octeon_io_reorder_wmb()		do { } while (0)
+#endif
+
+#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)			\
+									\
+static inline void pfx##write##bwlq(type val,				\
+				    volatile void __iomem *mem)		\
+{									\
+	volatile type *__mem;						\
+	type __val;							\
+									\
+	war_octeon_io_reorder_wmb();					\
+									\
+	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
+									\
+	__val = pfx##ioswab##bwlq(__mem, val);				\
+									\
+	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+		*__mem = __val;						\
+	else if (cpu_has_64bits) {					\
+		type __tmp;						\
+									\
+		__asm__ __volatile__(					\
+			".set	arch=r4000"	"\t\t# __writeq""\n\t"	\
+			"dsll32 %L0, %L0, 0"			"\n\t"	\
+			"dsrl32 %L0, %L0, 0"			"\n\t"	\
+			"dsll32 %M0, %M0, 0"			"\n\t"	\
+			"or	%L0, %L0, %M0"			"\n\t"	\
+			"sd	%L0, %2"			"\n\t"	\
+			".set	mips0"				"\n"	\
+			: "=r" (__tmp)					\
+			: "0" (__val), "m" (*__mem));			\
+	} else								\
+		BUG();							\
+}									\
+									\
+static inline type pfx##read##bwlq(const volatile void __iomem *mem)	\
+{									\
+	volatile type *__mem;						\
+	type __val;							\
+									\
+	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
+									\
+	if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+		__val = *__mem;						\
+	else if (cpu_has_64bits) {					\
+		__asm__ __volatile__(					\
+			".set	arch=r4000"	"\t\t# __readq" "\n\t"	\
+			"ld	%L0, %1"			"\n\t"	\
+			"dsra32 %M0, %L0, 0"			"\n\t"	\
+			"sll	%L0, %L0, 0"			"\n\t"	\
+			".set	mips0"				"\n"	\
+			: "=r" (__val)					\
+			: "m" (*__mem));				\
+	} else {							\
+		__val = 0;						\
+		BUG();							\
+	}								\
+									\
+	return pfx##ioswab##bwlq(__mem, __val);				\
+}
+
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p)			\
+									\
+static inline void pfx##out##bwlq##p(type val, unsigned long port)	\
+{									\
+	volatile type *__addr;						\
+	type __val;							\
+									\
+	war_octeon_io_reorder_wmb();					\
+									\
+	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base() + port); \
+									\
+	__val = pfx##ioswab##bwlq(__addr, val);				\
+									\
+	/* Really, we want this to be atomic */				\
+	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
+									\
+	*__addr = __val;						\
+}									\
+									\
+static inline type pfx##in##bwlq##p(unsigned long port)			\
+{									\
+	volatile type *__addr;						\
+	type __val;							\
+									\
+	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base() + port); \
+									\
+	BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));		\
+									\
+	__val = *__addr;						\
+									\
+	return pfx##ioswab##bwlq(__addr, __val);			\
+}
+
+#define __BUILD_MEMORY_PFX(bus, bwlq, type)				\
+									\
+__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
+
+#define BUILDIO_MEM(bwlq, type)						\
+									\
+__BUILD_MEMORY_PFX(__raw_, bwlq, type)					\
+__BUILD_MEMORY_PFX(, bwlq, type)					\
+__BUILD_MEMORY_PFX(__mem_, bwlq, type)					\
+
+BUILDIO_MEM(b, u8)
+BUILDIO_MEM(w, u16)
+BUILDIO_MEM(l, u32)
+BUILDIO_MEM(q, u64)
+
+#define __BUILD_IOPORT_PFX(bus, bwlq, type)				\
+	__BUILD_IOPORT_SINGLE(bus, bwlq, type, )			\
+	__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p)
+
+#define BUILDIO_IOPORT(bwlq, type)					\
+	__BUILD_IOPORT_PFX(, bwlq, type)				\
+	__BUILD_IOPORT_PFX(__mem_, bwlq, type)
+
+BUILDIO_IOPORT(b, u8)
+BUILDIO_IOPORT(w, u16)
+BUILDIO_IOPORT(l, u32)
+#ifdef CONFIG_64BIT
+BUILDIO_IOPORT(q, u64)
+#endif
+
+#define __BUILDIO(bwlq, type)						\
+									\
+__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
+
+__BUILDIO(q, u64)
+
+#define readb_relaxed			readb
+#define readw_relaxed			readw
+#define readl_relaxed			readl
+#define readq_relaxed			readq
+
+#define writeb_relaxed			writeb
+#define writew_relaxed			writew
+#define writel_relaxed			writel
+#define writeq_relaxed			writeq
+
+#define readb_be(addr)							\
+	__raw_readb((__force unsigned *)(addr))
+#define readw_be(addr)							\
+	be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
+#define readl_be(addr)							\
+	be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
+#define readq_be(addr)							\
+	be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
+
+#define writeb_be(val, addr)						\
+	__raw_writeb((val), (__force unsigned *)(addr))
+#define writew_be(val, addr)						\
+	__raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
+#define writel_be(val, addr)						\
+	__raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
+#define writeq_be(val, addr)						\
+	__raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
+
+/*
+ * Some code tests for these symbols
+ */
+#define readq				readq
+#define writeq				writeq
+
+#define __BUILD_MEMORY_STRING(bwlq, type)				\
+									\
+static inline void writes##bwlq(volatile void __iomem *mem,		\
+				const void *addr, unsigned int count)	\
+{									\
+	const volatile type *__addr = addr;				\
+									\
+	while (count--) {						\
+		__mem_write##bwlq(*__addr, mem);			\
+		__addr++;						\
+	}								\
+}									\
+									\
+static inline void reads##bwlq(volatile void __iomem *mem, void *addr,	\
+			       unsigned int count)			\
+{									\
+	volatile type *__addr = addr;					\
+									\
+	while (count--) {						\
+		*__addr = __mem_read##bwlq(mem);			\
+		__addr++;						\
+	}								\
+}
+
+#define __BUILD_IOPORT_STRING(bwlq, type)				\
+									\
+static inline void outs##bwlq(unsigned long port, const void *addr,	\
+			      unsigned int count)			\
+{									\
+	const volatile type *__addr = addr;				\
+									\
+	while (count--) {						\
+		__mem_out##bwlq(*__addr, port);				\
+		__addr++;						\
+	}								\
+}									\
+									\
+static inline void ins##bwlq(unsigned long port, void *addr,		\
+			     unsigned int count)			\
+{									\
+	volatile type *__addr = addr;					\
+									\
+	while (count--) {						\
+		*__addr = __mem_in##bwlq(port);				\
+		__addr++;						\
+	}								\
+}
+
+#define BUILDSTRING(bwlq, type)						\
+									\
+__BUILD_MEMORY_STRING(bwlq, type)					\
+__BUILD_IOPORT_STRING(bwlq, type)
+
+BUILDSTRING(b, u8)
+BUILDSTRING(w, u16)
+BUILDSTRING(l, u32)
+#ifdef CONFIG_64BIT
+BUILDSTRING(q, u64)
+#endif
+
+
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define mmiowb() wmb()
+#else
+/* Depends on MIPS II instruction set */
+#define mmiowb() asm volatile ("sync" ::: "memory")
+#endif
+
+static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
+{
+	memset((void __force *)addr, val, count);
+}
+static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
+{
+	memcpy(dst, (void __force *)src, count);
+}
+static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
+{
+	memcpy((void __force *)dst, src, count);
+}
+
+/*
+ * Read a 32-bit register that requires a 64-bit read cycle on the bus.
+ * Avoid interrupt mucking, just adjust the address for 4-byte access.
+ * Assume the addresses are 8-byte aligned.
+ */
+#ifdef __MIPSEB__
+#define __CSR_32_ADJUST 4
+#else
+#define __CSR_32_ADJUST 0
+#endif
+
+#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
+#define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
+
+/*
+ * U-Boot specific
+ */
+#define sync()		mmiowb()
+
+#define MAP_NOCACHE	1
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	if (flags == MAP_NOCACHE)
+		return ioremap(paddr, len);
+
+	return (void *)CKSEG0ADDR(paddr);
+}
+#define map_physmem map_physmem
+
+#define __BUILD_CLRBITS(bwlq, sfx, end, type)				\
+									\
+static inline void clrbits_##sfx(volatile void __iomem *mem, type clr)	\
+{									\
+	type __val = __raw_read##bwlq(mem);				\
+	__val = end##_to_cpu(__val);					\
+	__val &= ~clr;							\
+	__val = cpu_to_##end(__val);					\
+	__raw_write##bwlq(__val, mem);					\
+}
+
+#define __BUILD_SETBITS(bwlq, sfx, end, type)				\
+									\
+static inline void setbits_##sfx(volatile void __iomem *mem, type set)	\
+{									\
+	type __val = __raw_read##bwlq(mem);				\
+	__val = end##_to_cpu(__val);					\
+	__val |= set;							\
+	__val = cpu_to_##end(__val);					\
+	__raw_write##bwlq(__val, mem);					\
+}
+
+#define __BUILD_CLRSETBITS(bwlq, sfx, end, type)			\
+									\
+static inline void clrsetbits_##sfx(volatile void __iomem *mem,		\
+					type clr, type set)		\
+{									\
+	type __val = __raw_read##bwlq(mem);				\
+	__val = end##_to_cpu(__val);					\
+	__val &= ~clr;							\
+	__val |= set;							\
+	__val = cpu_to_##end(__val);					\
+	__raw_write##bwlq(__val, mem);					\
+}
+
+#define BUILD_CLRSETBITS(bwlq, sfx, end, type)				\
+									\
+__BUILD_CLRBITS(bwlq, sfx, end, type)					\
+__BUILD_SETBITS(bwlq, sfx, end, type)					\
+__BUILD_CLRSETBITS(bwlq, sfx, end, type)
+
+#define __to_cpu(v)		(v)
+#define cpu_to__(v)		(v)
+
+#define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v),a)
+#define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))
+
+#define out_le64(a, v)	out_arch(q, le64, a, v)
+#define out_le32(a, v)	out_arch(l, le32, a, v)
+#define out_le16(a, v)	out_arch(w, le16, a, v)
+
+#define in_le64(a)	in_arch(q, le64, a)
+#define in_le32(a)	in_arch(l, le32, a)
+#define in_le16(a)	in_arch(w, le16, a)
+
+#define out_be64(a, v)	out_arch(q, be64, a, v)
+#define out_be32(a, v)	out_arch(l, be32, a, v)
+#define out_be16(a, v)	out_arch(w, be16, a, v)
+
+#define in_be64(a)	in_arch(q, be64, a)
+#define in_be32(a)	in_arch(l, be32, a)
+#define in_be16(a)	in_arch(w, be16, a)
+
+#define out_8(a, v)	__raw_writeb(v, a)
+#define in_8(a)		__raw_readb(a)
+
+BUILD_CLRSETBITS(b, 8, _, u8)
+BUILD_CLRSETBITS(w, le16, le16, u16)
+BUILD_CLRSETBITS(w, be16, be16, u16)
+BUILD_CLRSETBITS(w, 16, _, u16)
+BUILD_CLRSETBITS(l, le32, le32, u32)
+BUILD_CLRSETBITS(l, be32, be32, u32)
+BUILD_CLRSETBITS(l, 32, _, u32)
+BUILD_CLRSETBITS(q, le64, le64, u64)
+BUILD_CLRSETBITS(q, be64, be64, u64)
+BUILD_CLRSETBITS(q, 64, _, u64)
+
+#include <asm-generic/io.h>
+
+#endif /* _ASM_IO_H */
diff --git a/arch/mips/include/asm/isadep.h b/arch/mips/include/asm/isadep.h
new file mode 100644
index 0000000..d168320
--- /dev/null
+++ b/arch/mips/include/asm/isadep.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Various ISA level dependent constants.
+ * Most of the following constants reflect the different layout
+ * of Coprocessor 0 registers.
+ *
+ * Copyright (c) 1998 Harald Koerfgen
+ */
+
+#ifndef __ASM_ISADEP_H
+#define __ASM_ISADEP_H
+
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+/*
+ * R2000 or R3000
+ */
+
+/*
+ * kernel or user mode? (CP0_STATUS)
+ */
+#define KU_MASK 0x08
+#define KU_USER 0x08
+#define KU_KERN 0x00
+
+#else
+/*
+ * kernel or user mode?
+ */
+#define KU_MASK 0x18
+#define KU_USER 0x10
+#define KU_KERN 0x00
+
+#endif
+
+#endif /* __ASM_ISADEP_H */
diff --git a/arch/mips/include/asm/linkage.h b/arch/mips/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/mips/include/asm/linkage.h
diff --git a/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
new file mode 100644
index 0000000..38f2302
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
+
+/* Intentionally empty file ...	 */
+
+#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-generic/ioremap.h b/arch/mips/include/asm/mach-generic/ioremap.h
new file mode 100644
index 0000000..d6258f5
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/ioremap.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_MACH_GENERIC_IOREMAP_H
+#define __ASM_MACH_GENERIC_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
+						phys_addr_t size)
+{
+	return phys_addr;
+}
+
+static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+						unsigned long flags)
+{
+	return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+	return 0;
+}
+
+#define _page_cachable_default	_CACHE_CACHABLE_NONCOHERENT
+
+#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-generic/mangle-port.h b/arch/mips/include/asm/mach-generic/mangle-port.h
new file mode 100644
index 0000000..3f95bbc
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/mangle-port.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
+#define __ASM_MACH_GENERIC_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)	(port)
+#define __swizzle_addr_w(port)	(port)
+#define __swizzle_addr_l(port)	(port)
+#define __swizzle_addr_q(port)	(port)
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time.  Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses.  The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		le16_to_cpu(x)
+# define __mem_ioswabw(a, x)	(x)
+# define ioswabl(a, x)		le32_to_cpu(x)
+# define __mem_ioswabl(a, x)	(x)
+# define ioswabq(a, x)		le64_to_cpu(x)
+# define __mem_ioswabq(a, x)	(x)
+
+#else
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		(x)
+# define __mem_ioswabw(a, x)	cpu_to_le16(x)
+# define ioswabl(a, x)		(x)
+# define __mem_ioswabl(a, x)	cpu_to_le32(x)
+# define ioswabq(a, x)		(x)
+# define __mem_ioswabq(a, x)	cpu_to_le32(x)
+
+#endif
+
+#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
new file mode 100644
index 0000000..539d0a5
--- /dev/null
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_GENERIC_SPACES_H
+#define _ASM_MACH_GENERIC_SPACES_H
+
+#include <linux/const.h>
+
+/*
+ * This gives the physical RAM offset.
+ */
+#ifndef PHYS_OFFSET
+#define PHYS_OFFSET		_AC(0, UL)
+#endif
+
+#ifdef CONFIG_32BIT
+#ifdef CONFIG_KVM_GUEST
+#define CAC_BASE		_AC(0x40000000, UL)
+#else
+#define CAC_BASE		_AC(0x80000000, UL)
+#endif
+#ifndef IO_BASE
+#define IO_BASE			_AC(0xa0000000, UL)
+#endif
+#ifndef UNCAC_BASE
+#define UNCAC_BASE		_AC(0xa0000000, UL)
+#endif
+
+#ifndef MAP_BASE
+#ifdef CONFIG_KVM_GUEST
+#define MAP_BASE		_AC(0x60000000, UL)
+#else
+#define MAP_BASE		_AC(0xc0000000, UL)
+#endif
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START		_AC(0x20000000, UL)
+#endif
+
+#endif /* CONFIG_32BIT */
+
+#ifdef CONFIG_64BIT
+
+#ifndef CAC_BASE
+#ifdef CONFIG_DMA_NONCOHERENT
+#define CAC_BASE		_AC(0x9800000000000000, UL)
+#else
+#define CAC_BASE		_AC(0xa800000000000000, UL)
+#endif
+#endif
+
+#ifndef IO_BASE
+#define IO_BASE			_AC(0x9000000000000000, UL)
+#endif
+
+#ifndef UNCAC_BASE
+#define UNCAC_BASE		_AC(0x9000000000000000, UL)
+#endif
+
+#ifndef MAP_BASE
+#define MAP_BASE		_AC(0xc000000000000000, UL)
+#endif
+
+/*
+ * Memory above this physical address will be considered highmem.
+ * Fixme: 59 bits is a fictive number and makes assumptions about processors
+ * in the distant future.  Nobody will care for a few years :-)
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START		(_AC(1, UL) << _AC(59, UL))
+#endif
+
+#define TO_PHYS(x)		(	      ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)		(CAC_BASE   | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)		(UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
+#endif /* CONFIG_64BIT */
+
+/*
+ * This handles the memory map.
+ */
+#ifndef PAGE_OFFSET
+#define PAGE_OFFSET		(CAC_BASE + PHYS_OFFSET)
+#endif
+
+#ifndef FIXADDR_TOP
+#ifdef CONFIG_KVM_GUEST
+#define FIXADDR_TOP		((unsigned long)(long)(int)0x7ffe0000)
+#else
+#define FIXADDR_TOP		((unsigned long)(long)(int)0xfffe0000)
+#endif
+#endif
+
+#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h
new file mode 100644
index 0000000..5c56539
--- /dev/null
+++ b/arch/mips/include/asm/malta.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 Imagination Technologies
+ */
+
+#ifndef _MIPS_ASM_MALTA_H
+#define _MIPS_ASM_MALTA_H
+
+#define MALTA_GT_BASE			0x1be00000
+#define MALTA_GT_PCIIO_BASE		0x18000000
+#define MALTA_GT_UART0_BASE		(MALTA_GT_PCIIO_BASE + 0x3f8)
+
+#define MALTA_MSC01_BIU_BASE		0x1bc80000
+#define MALTA_MSC01_PCI_BASE		0x1bd00000
+#define MALTA_MSC01_PBC_BASE		0x1bd40000
+#define MALTA_MSC01_IP1_BASE		0x1bc00000
+#define MALTA_MSC01_IP1_SIZE		0x00400000
+#define MALTA_MSC01_IP2_BASE1		0x10000000
+#define MALTA_MSC01_IP2_SIZE1		0x08000000
+#define MALTA_MSC01_IP2_BASE2		0x18000000
+#define MALTA_MSC01_IP2_SIZE2		0x04000000
+#define MALTA_MSC01_IP3_BASE		0x1c000000
+#define MALTA_MSC01_IP3_SIZE		0x04000000
+#define MALTA_MSC01_PCIMEM_BASE		0x10000000
+#define MALTA_MSC01_PCIMEM_SIZE		0x10000000
+#define MALTA_MSC01_PCIMEM_MAP		0x10000000
+#define MALTA_MSC01_PCIIO_BASE		0x1b000000
+#define MALTA_MSC01_PCIIO_SIZE		0x00800000
+#define MALTA_MSC01_PCIIO_MAP		0x00000000
+#define MALTA_MSC01_UART0_BASE		(MALTA_MSC01_PCIIO_BASE + 0x3f8)
+
+#define MALTA_ASCIIWORD			0x1f000410
+#define MALTA_ASCIIPOS0			0x1f000418
+#define MALTA_ASCIIPOS1			0x1f000420
+#define MALTA_ASCIIPOS2			0x1f000428
+#define MALTA_ASCIIPOS3			0x1f000430
+#define MALTA_ASCIIPOS4			0x1f000438
+#define MALTA_ASCIIPOS5			0x1f000440
+#define MALTA_ASCIIPOS6			0x1f000448
+#define MALTA_ASCIIPOS7			0x1f000450
+
+#define MALTA_RESET_BASE		0x1f000500
+#define GORESET				0x42
+
+#define MALTA_FLASH_BASE		0x1e000000
+
+#define MALTA_REVISION			0x1fc00010
+#define MALTA_REVISION_CORID_SHF	10
+#define MALTA_REVISION_CORID_MSK	(0x3f << MALTA_REVISION_CORID_SHF)
+#define MALTA_REVISION_CORID_CORE_LV		1
+#define MALTA_REVISION_CORID_CORE_FPGA6		14
+
+#define PCI_CFG_PIIX4_PIRQRCA		0x60
+#define PCI_CFG_PIIX4_PIRQRCB		0x61
+#define PCI_CFG_PIIX4_PIRQRCC		0x62
+#define PCI_CFG_PIIX4_PIRQRCD		0x63
+#define PCI_CFG_PIIX4_SERIRQC		0x64
+#define PCI_CFG_PIIX4_GENCFG		0xb0
+
+#define PCI_CFG_PIIX4_SERIRQC_EN	(1 << 7)
+#define PCI_CFG_PIIX4_SERIRQC_CONT	(1 << 6)
+
+#define PCI_CFG_PIIX4_GENCFG_SERIRQ	(1 << 16)
+
+#define PCI_CFG_PIIX4_IDETIM_PRI	0x40
+#define PCI_CFG_PIIX4_IDETIM_SEC	0x42
+
+#define PCI_CFG_PIIX4_IDETIM_IDE	(1 << 15)
+
+#endif /* _MIPS_ASM_MALTA_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
new file mode 100644
index 0000000..f80311e
--- /dev/null
+++ b/arch/mips/include/asm/mipsregs.h
@@ -0,0 +1,2014 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Modified for further R[236]000 support by Paul M. Antoine, 1996.
+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000, 07 MIPS Technologies, Inc.
+ * Copyright (C) 2003, 2004  Maciej W. Rozycki
+ */
+#ifndef _ASM_MIPSREGS_H
+#define _ASM_MIPSREGS_H
+
+/*
+ * The following macros are especially useful for __asm__
+ * inline assembler.
+ */
+#ifndef __STR
+#define __STR(x) #x
+#endif
+#ifndef STR
+#define STR(x) __STR(x)
+#endif
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ULCAST_
+#else
+#define _ULCAST_ (unsigned long)
+#endif
+
+/*
+ * Coprocessor 0 register names
+ */
+#define CP0_INDEX $0
+#define CP0_RANDOM $1
+#define CP0_ENTRYLO0 $2
+#define CP0_ENTRYLO1 $3
+#define CP0_CONF $3
+#define CP0_GLOBALNUMBER $3, 1
+#define CP0_CONTEXT $4
+#define CP0_PAGEMASK $5
+#define CP0_WIRED $6
+#define CP0_INFO $7
+#define CP0_HWRENA $7, 0
+#define CP0_BADVADDR $8
+#define CP0_BADINSTR $8, 1
+#define CP0_COUNT $9
+#define CP0_ENTRYHI $10
+#define CP0_COMPARE $11
+#define CP0_STATUS $12
+#define CP0_CAUSE $13
+#define CP0_EPC $14
+#define CP0_PRID $15
+#define CP0_EBASE $15, 1
+#define CP0_CMGCRBASE $15, 3
+#define CP0_CONFIG $16
+#define CP0_CONFIG3 $16, 3
+#define CP0_CONFIG5 $16, 5
+#define CP0_LLADDR $17
+#define CP0_WATCHLO $18
+#define CP0_WATCHHI $19
+#define CP0_XCONTEXT $20
+#define CP0_FRAMEMASK $21
+#define CP0_DIAGNOSTIC $22
+#define CP0_DEBUG $23
+#define CP0_DEPC $24
+#define CP0_PERFORMANCE $25
+#define CP0_ECC $26
+#define CP0_CACHEERR $27
+#define CP0_TAGLO $28
+#define CP0_TAGHI $29
+#define CP0_ERROREPC $30
+#define CP0_DESAVE $31
+
+/*
+ * R4640/R4650 cp0 register names.  These registers are listed
+ * here only for completeness; without MMU these CPUs are not useable
+ * by Linux.  A future ELKS port might take make Linux run on them
+ * though ...
+ */
+#define CP0_IBASE $0
+#define CP0_IBOUND $1
+#define CP0_DBASE $2
+#define CP0_DBOUND $3
+#define CP0_CALG $17
+#define CP0_IWATCH $18
+#define CP0_DWATCH $19
+
+/*
+ * Coprocessor 0 Set 1 register names
+ */
+#define CP0_S1_DERRADDR0  $26
+#define CP0_S1_DERRADDR1  $27
+#define CP0_S1_INTCONTROL $20
+
+/*
+ * Coprocessor 0 Set 2 register names
+ */
+#define CP0_S2_SRSCTL	  $12	/* MIPSR2 */
+
+/*
+ * Coprocessor 0 Set 3 register names
+ */
+#define CP0_S3_SRSMAP	  $12	/* MIPSR2 */
+
+/*
+ *  TX39 Series
+ */
+#define CP0_TX39_CACHE	$7
+
+
+/* Generic EntryLo bit definitions */
+#define ENTRYLO_G		(_ULCAST_(1) << 0)
+#define ENTRYLO_V		(_ULCAST_(1) << 1)
+#define ENTRYLO_D		(_ULCAST_(1) << 2)
+#define ENTRYLO_C_SHIFT		3
+#define ENTRYLO_C		(_ULCAST_(7) << ENTRYLO_C_SHIFT)
+
+/* R3000 EntryLo bit definitions */
+#define R3K_ENTRYLO_G		(_ULCAST_(1) << 8)
+#define R3K_ENTRYLO_V		(_ULCAST_(1) << 9)
+#define R3K_ENTRYLO_D		(_ULCAST_(1) << 10)
+#define R3K_ENTRYLO_N		(_ULCAST_(1) << 11)
+
+/* MIPS32/64 EntryLo bit definitions */
+#define MIPS_ENTRYLO_PFN_SHIFT	6
+#define MIPS_ENTRYLO_XI		(_ULCAST_(1) << (BITS_PER_LONG - 2))
+#define MIPS_ENTRYLO_RI		(_ULCAST_(1) << (BITS_PER_LONG - 1))
+
+/*
+ * Values for PageMask register
+ */
+#ifdef CONFIG_CPU_VR41XX
+
+/* Why doesn't stupidity hurt ... */
+
+#define PM_1K		0x00000000
+#define PM_4K		0x00001800
+#define PM_16K		0x00007800
+#define PM_64K		0x0001f800
+#define PM_256K		0x0007f800
+
+#else
+
+#define PM_4K		0x00000000
+#define PM_8K		0x00002000
+#define PM_16K		0x00006000
+#define PM_32K		0x0000e000
+#define PM_64K		0x0001e000
+#define PM_128K		0x0003e000
+#define PM_256K		0x0007e000
+#define PM_512K		0x000fe000
+#define PM_1M		0x001fe000
+#define PM_2M		0x003fe000
+#define PM_4M		0x007fe000
+#define PM_8M		0x00ffe000
+#define PM_16M		0x01ffe000
+#define PM_32M		0x03ffe000
+#define PM_64M		0x07ffe000
+#define PM_256M		0x1fffe000
+#define PM_1G		0x7fffe000
+
+#endif
+
+/*
+ * Values used for computation of new tlb entries
+ */
+#define PL_4K		12
+#define PL_16K		14
+#define PL_64K		16
+#define PL_256K		18
+#define PL_1M		20
+#define PL_4M		22
+#define PL_16M		24
+#define PL_64M		26
+#define PL_256M		28
+
+/*
+ * PageGrain bits
+ */
+#define PG_RIE		(_ULCAST_(1) <<	 31)
+#define PG_XIE		(_ULCAST_(1) <<	 30)
+#define PG_ELPA		(_ULCAST_(1) <<	 29)
+#define PG_ESP		(_ULCAST_(1) <<	 28)
+#define PG_IEC		(_ULCAST_(1) <<  27)
+
+/* MIPS32/64 EntryHI bit definitions */
+#define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
+
+/*
+ * R4x00 interrupt enable / cause bits
+ */
+#define IE_SW0		(_ULCAST_(1) <<	 8)
+#define IE_SW1		(_ULCAST_(1) <<	 9)
+#define IE_IRQ0		(_ULCAST_(1) << 10)
+#define IE_IRQ1		(_ULCAST_(1) << 11)
+#define IE_IRQ2		(_ULCAST_(1) << 12)
+#define IE_IRQ3		(_ULCAST_(1) << 13)
+#define IE_IRQ4		(_ULCAST_(1) << 14)
+#define IE_IRQ5		(_ULCAST_(1) << 15)
+
+/*
+ * R4x00 interrupt cause bits
+ */
+#define C_SW0		(_ULCAST_(1) <<	 8)
+#define C_SW1		(_ULCAST_(1) <<	 9)
+#define C_IRQ0		(_ULCAST_(1) << 10)
+#define C_IRQ1		(_ULCAST_(1) << 11)
+#define C_IRQ2		(_ULCAST_(1) << 12)
+#define C_IRQ3		(_ULCAST_(1) << 13)
+#define C_IRQ4		(_ULCAST_(1) << 14)
+#define C_IRQ5		(_ULCAST_(1) << 15)
+
+/*
+ * Bitfields in the R4xx0 cp0 status register
+ */
+#define ST0_IE			0x00000001
+#define ST0_EXL			0x00000002
+#define ST0_ERL			0x00000004
+#define ST0_KSU			0x00000018
+#  define KSU_USER		0x00000010
+#  define KSU_SUPERVISOR	0x00000008
+#  define KSU_KERNEL		0x00000000
+#define ST0_UX			0x00000020
+#define ST0_SX			0x00000040
+#define ST0_KX			0x00000080
+#define ST0_DE			0x00010000
+#define ST0_CE			0x00020000
+
+/*
+ * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
+ * cacheops in userspace.  This bit exists only on RM7000 and RM9000
+ * processors.
+ */
+#define ST0_CO			0x08000000
+
+/*
+ * Bitfields in the R[23]000 cp0 status register.
+ */
+#define ST0_IEC			0x00000001
+#define ST0_KUC			0x00000002
+#define ST0_IEP			0x00000004
+#define ST0_KUP			0x00000008
+#define ST0_IEO			0x00000010
+#define ST0_KUO			0x00000020
+/* bits 6 & 7 are reserved on R[23]000 */
+#define ST0_ISC			0x00010000
+#define ST0_SWC			0x00020000
+#define ST0_CM			0x00080000
+
+/*
+ * Bits specific to the R4640/R4650
+ */
+#define ST0_UM			(_ULCAST_(1) <<	 4)
+#define ST0_IL			(_ULCAST_(1) << 23)
+#define ST0_DL			(_ULCAST_(1) << 24)
+
+/*
+ * Enable the MIPS MDMX and DSP ASEs
+ */
+#define ST0_MX			0x01000000
+
+/*
+ * Status register bits available in all MIPS CPUs.
+ */
+#define ST0_IM			0x0000ff00
+#define	 STATUSB_IP0		8
+#define	 STATUSF_IP0		(_ULCAST_(1) <<	 8)
+#define	 STATUSB_IP1		9
+#define	 STATUSF_IP1		(_ULCAST_(1) <<	 9)
+#define	 STATUSB_IP2		10
+#define	 STATUSF_IP2		(_ULCAST_(1) << 10)
+#define	 STATUSB_IP3		11
+#define	 STATUSF_IP3		(_ULCAST_(1) << 11)
+#define	 STATUSB_IP4		12
+#define	 STATUSF_IP4		(_ULCAST_(1) << 12)
+#define	 STATUSB_IP5		13
+#define	 STATUSF_IP5		(_ULCAST_(1) << 13)
+#define	 STATUSB_IP6		14
+#define	 STATUSF_IP6		(_ULCAST_(1) << 14)
+#define	 STATUSB_IP7		15
+#define	 STATUSF_IP7		(_ULCAST_(1) << 15)
+#define	 STATUSB_IP8		0
+#define	 STATUSF_IP8		(_ULCAST_(1) <<	 0)
+#define	 STATUSB_IP9		1
+#define	 STATUSF_IP9		(_ULCAST_(1) <<	 1)
+#define	 STATUSB_IP10		2
+#define	 STATUSF_IP10		(_ULCAST_(1) <<	 2)
+#define	 STATUSB_IP11		3
+#define	 STATUSF_IP11		(_ULCAST_(1) <<	 3)
+#define	 STATUSB_IP12		4
+#define	 STATUSF_IP12		(_ULCAST_(1) <<	 4)
+#define	 STATUSB_IP13		5
+#define	 STATUSF_IP13		(_ULCAST_(1) <<	 5)
+#define	 STATUSB_IP14		6
+#define	 STATUSF_IP14		(_ULCAST_(1) <<	 6)
+#define	 STATUSB_IP15		7
+#define	 STATUSF_IP15		(_ULCAST_(1) <<	 7)
+#define ST0_IMPL		(_ULCAST_(3) <<	 16)
+#define ST0_CH			0x00040000
+#define ST0_NMI			0x00080000
+#define ST0_SR			0x00100000
+#define ST0_TS			0x00200000
+#define ST0_BEV			0x00400000
+#define ST0_RE			0x02000000
+#define ST0_FR			0x04000000
+#define ST0_CU			0xf0000000
+#define ST0_CU0			0x10000000
+#define ST0_CU1			0x20000000
+#define ST0_CU2			0x40000000
+#define ST0_CU3			0x80000000
+#define ST0_XX			0x80000000	/* MIPS IV naming */
+
+/*
+ * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
+ */
+#define INTCTLB_IPFDC		23
+#define INTCTLF_IPFDC		(_ULCAST_(7) << INTCTLB_IPFDC)
+#define INTCTLB_IPPCI		26
+#define INTCTLF_IPPCI		(_ULCAST_(7) << INTCTLB_IPPCI)
+#define INTCTLB_IPTI		29
+#define INTCTLF_IPTI		(_ULCAST_(7) << INTCTLB_IPTI)
+
+/*
+ * Bitfields and bit numbers in the coprocessor 0 cause register.
+ *
+ * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
+ */
+#define CAUSEB_EXCCODE		2
+#define CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
+#define CAUSEB_IP		8
+#define CAUSEF_IP		(_ULCAST_(255) <<  8)
+#define	 CAUSEB_IP0		8
+#define	 CAUSEF_IP0		(_ULCAST_(1)   <<  8)
+#define	 CAUSEB_IP1		9
+#define	 CAUSEF_IP1		(_ULCAST_(1)   <<  9)
+#define	 CAUSEB_IP2		10
+#define	 CAUSEF_IP2		(_ULCAST_(1)   << 10)
+#define	 CAUSEB_IP3		11
+#define	 CAUSEF_IP3		(_ULCAST_(1)   << 11)
+#define	 CAUSEB_IP4		12
+#define	 CAUSEF_IP4		(_ULCAST_(1)   << 12)
+#define	 CAUSEB_IP5		13
+#define	 CAUSEF_IP5		(_ULCAST_(1)   << 13)
+#define	 CAUSEB_IP6		14
+#define	 CAUSEF_IP6		(_ULCAST_(1)   << 14)
+#define	 CAUSEB_IP7		15
+#define	 CAUSEF_IP7		(_ULCAST_(1)   << 15)
+#define CAUSEB_FDCI		21
+#define CAUSEF_FDCI		(_ULCAST_(1)   << 21)
+#define CAUSEB_IV		23
+#define CAUSEF_IV		(_ULCAST_(1)   << 23)
+#define CAUSEB_PCI		26
+#define CAUSEF_PCI		(_ULCAST_(1)   << 26)
+#define CAUSEB_CE		28
+#define CAUSEF_CE		(_ULCAST_(3)   << 28)
+#define CAUSEB_TI		30
+#define CAUSEF_TI		(_ULCAST_(1)   << 30)
+#define CAUSEB_BD		31
+#define CAUSEF_BD		(_ULCAST_(1)   << 31)
+
+/*
+ * Bits in the coprocessor 0 EBase register.
+ */
+#define EBASE_CPUNUM		0x3ff
+
+/*
+ * Bits in the coprocessor 0 config register.
+ */
+/* Generic bits.  */
+#define CONF_CM_CACHABLE_NO_WA		0
+#define CONF_CM_CACHABLE_WA		1
+#define CONF_CM_UNCACHED		2
+#define CONF_CM_CACHABLE_NONCOHERENT	3
+#define CONF_CM_CACHABLE_CE		4
+#define CONF_CM_CACHABLE_COW		5
+#define CONF_CM_CACHABLE_CUW		6
+#define CONF_CM_CACHABLE_ACCELERATED	7
+#define CONF_CM_CMASK			7
+#define CONF_BE			(_ULCAST_(1) << 15)
+
+/* Bits common to various processors.  */
+#define CONF_CU			(_ULCAST_(1) <<	 3)
+#define CONF_DB			(_ULCAST_(1) <<	 4)
+#define CONF_IB			(_ULCAST_(1) <<	 5)
+#define CONF_DC			(_ULCAST_(7) <<	 6)
+#define CONF_IC			(_ULCAST_(7) <<	 9)
+#define CONF_EB			(_ULCAST_(1) << 13)
+#define CONF_EM			(_ULCAST_(1) << 14)
+#define CONF_SM			(_ULCAST_(1) << 16)
+#define CONF_SC			(_ULCAST_(1) << 17)
+#define CONF_EW			(_ULCAST_(3) << 18)
+#define CONF_EP			(_ULCAST_(15) << 24)
+#define CONF_EC			(_ULCAST_(7) << 28)
+#define CONF_CM			(_ULCAST_(1) << 31)
+
+/* Bits specific to the R4xx0.	*/
+#define R4K_CONF_SW		(_ULCAST_(1) << 20)
+#define R4K_CONF_SS		(_ULCAST_(1) << 21)
+#define R4K_CONF_SB		(_ULCAST_(3) << 22)
+
+/* Bits specific to the R5000.	*/
+#define R5K_CONF_SE		(_ULCAST_(1) << 12)
+#define R5K_CONF_SS		(_ULCAST_(3) << 20)
+
+/* Bits specific to the RM7000.	 */
+#define RM7K_CONF_SE		(_ULCAST_(1) <<	 3)
+#define RM7K_CONF_TE		(_ULCAST_(1) << 12)
+#define RM7K_CONF_CLK		(_ULCAST_(1) << 16)
+#define RM7K_CONF_TC		(_ULCAST_(1) << 17)
+#define RM7K_CONF_SI		(_ULCAST_(3) << 20)
+#define RM7K_CONF_SC		(_ULCAST_(1) << 31)
+
+/* Bits specific to the R10000.	 */
+#define R10K_CONF_DN		(_ULCAST_(3) <<	 3)
+#define R10K_CONF_CT		(_ULCAST_(1) <<	 5)
+#define R10K_CONF_PE		(_ULCAST_(1) <<	 6)
+#define R10K_CONF_PM		(_ULCAST_(3) <<	 7)
+#define R10K_CONF_EC		(_ULCAST_(15) << 9)
+#define R10K_CONF_SB		(_ULCAST_(1) << 13)
+#define R10K_CONF_SK		(_ULCAST_(1) << 14)
+#define R10K_CONF_SS		(_ULCAST_(7) << 16)
+#define R10K_CONF_SC		(_ULCAST_(7) << 19)
+#define R10K_CONF_DC		(_ULCAST_(7) << 26)
+#define R10K_CONF_IC		(_ULCAST_(7) << 29)
+
+/* Bits specific to the VR41xx.	 */
+#define VR41_CONF_CS		(_ULCAST_(1) << 12)
+#define VR41_CONF_P4K		(_ULCAST_(1) << 13)
+#define VR41_CONF_BP		(_ULCAST_(1) << 16)
+#define VR41_CONF_M16		(_ULCAST_(1) << 20)
+#define VR41_CONF_AD		(_ULCAST_(1) << 23)
+
+/* Bits specific to the R30xx.	*/
+#define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
+#define R30XX_CONF_REV		(_ULCAST_(1) << 22)
+#define R30XX_CONF_AC		(_ULCAST_(1) << 23)
+#define R30XX_CONF_RF		(_ULCAST_(1) << 24)
+#define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
+#define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
+#define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
+#define R30XX_CONF_SB		(_ULCAST_(1) << 30)
+#define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
+
+/* Bits specific to the TX49.  */
+#define TX49_CONF_DC		(_ULCAST_(1) << 16)
+#define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
+#define TX49_CONF_HALT		(_ULCAST_(1) << 18)
+#define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
+
+/* Bits specific to the MIPS32/64 PRA.	*/
+#define MIPS_CONF_MT		(_ULCAST_(7) <<	 7)
+#define MIPS_CONF_MT_TLB	(_ULCAST_(1) <<  7)
+#define MIPS_CONF_MT_FTLB	(_ULCAST_(4) <<  7)
+#define MIPS_CONF_AR		(_ULCAST_(7) << 10)
+#define MIPS_CONF_AT		(_ULCAST_(3) << 13)
+#define MIPS_CONF_IMPL		(_ULCAST_(0x1ff) << 16)
+#define MIPS_CONF_M		(_ULCAST_(1) << 31)
+
+/*
+ * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
+ */
+#define MIPS_CONF1_FP		(_ULCAST_(1) <<	 0)
+#define MIPS_CONF1_EP		(_ULCAST_(1) <<	 1)
+#define MIPS_CONF1_CA		(_ULCAST_(1) <<	 2)
+#define MIPS_CONF1_WR		(_ULCAST_(1) <<	 3)
+#define MIPS_CONF1_PC		(_ULCAST_(1) <<	 4)
+#define MIPS_CONF1_MD		(_ULCAST_(1) <<	 5)
+#define MIPS_CONF1_C2		(_ULCAST_(1) <<	 6)
+#define MIPS_CONF1_DA_SHF	7
+#define MIPS_CONF1_DA_SZ	3
+#define MIPS_CONF1_DA		(_ULCAST_(7) <<	 7)
+#define MIPS_CONF1_DL_SHF	10
+#define MIPS_CONF1_DL_SZ	3
+#define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
+#define MIPS_CONF1_DS_SHF	13
+#define MIPS_CONF1_DS_SZ	3
+#define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
+#define MIPS_CONF1_IA_SHF	16
+#define MIPS_CONF1_IA_SZ	3
+#define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
+#define MIPS_CONF1_IL_SHF	19
+#define MIPS_CONF1_IL_SZ	3
+#define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
+#define MIPS_CONF1_IS_SHF	22
+#define MIPS_CONF1_IS_SZ	3
+#define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
+#define MIPS_CONF1_TLBS_SHIFT   (25)
+#define MIPS_CONF1_TLBS_SIZE    (6)
+#define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
+
+#define MIPS_CONF2_SA_SHF	0
+#define MIPS_CONF2_SA		(_ULCAST_(15) << 0)
+#define MIPS_CONF2_SL_SHF	4
+#define MIPS_CONF2_SL		(_ULCAST_(15) << 4)
+#define MIPS_CONF2_SS_SHF	8
+#define MIPS_CONF2_SS		(_ULCAST_(15) << 8)
+#define MIPS_CONF2_L2B		(_ULCAST_(1) << 12)
+#define MIPS_CONF2_SU		(_ULCAST_(15) << 12)
+#define MIPS_CONF2_TA		(_ULCAST_(15) << 16)
+#define MIPS_CONF2_TL		(_ULCAST_(15) << 20)
+#define MIPS_CONF2_TS		(_ULCAST_(15) << 24)
+#define MIPS_CONF2_TU		(_ULCAST_(7) << 28)
+
+#define MIPS_CONF3_TL		(_ULCAST_(1) <<	 0)
+#define MIPS_CONF3_SM		(_ULCAST_(1) <<	 1)
+#define MIPS_CONF3_MT		(_ULCAST_(1) <<	 2)
+#define MIPS_CONF3_CDMM		(_ULCAST_(1) <<	 3)
+#define MIPS_CONF3_SP		(_ULCAST_(1) <<	 4)
+#define MIPS_CONF3_VINT		(_ULCAST_(1) <<	 5)
+#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<	 6)
+#define MIPS_CONF3_LPA		(_ULCAST_(1) <<	 7)
+#define MIPS_CONF3_ITL		(_ULCAST_(1) <<	 8)
+#define MIPS_CONF3_CTXTC	(_ULCAST_(1) <<	 9)
+#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
+#define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)
+#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
+#define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
+#define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
+#define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
+#define MIPS_CONF3_MCU		(_ULCAST_(1) << 17)
+#define MIPS_CONF3_MMAR		(_ULCAST_(7) << 18)
+#define MIPS_CONF3_IPLW		(_ULCAST_(3) << 21)
+#define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)
+#define MIPS_CONF3_PW		(_ULCAST_(1) << 24)
+#define MIPS_CONF3_SC		(_ULCAST_(1) << 25)
+#define MIPS_CONF3_BI		(_ULCAST_(1) << 26)
+#define MIPS_CONF3_BP		(_ULCAST_(1) << 27)
+#define MIPS_CONF3_MSA		(_ULCAST_(1) << 28)
+#define MIPS_CONF3_CMGCR	(_ULCAST_(1) << 29)
+#define MIPS_CONF3_BPG		(_ULCAST_(1) << 30)
+
+#define MIPS_CONF4_MMUSIZEEXT_SHIFT	(0)
+#define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
+#define MIPS_CONF4_FTLBSETS_SHIFT	(0)
+#define MIPS_CONF4_FTLBSETS	(_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
+#define MIPS_CONF4_FTLBWAYS_SHIFT	(4)
+#define MIPS_CONF4_FTLBWAYS	(_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
+#define MIPS_CONF4_FTLBPAGESIZE_SHIFT	(8)
+/* bits 10:8 in FTLB-only configurations */
+#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
+/* bits 12:8 in VTLB-FTLB only configurations */
+#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
+#define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)
+#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
+#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT	(_ULCAST_(2) << 14)
+#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT	(_ULCAST_(3) << 14)
+#define MIPS_CONF4_KSCREXIST	(_ULCAST_(255) << 16)
+#define MIPS_CONF4_VTLBSIZEEXT_SHIFT	(24)
+#define MIPS_CONF4_VTLBSIZEEXT	(_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
+#define MIPS_CONF4_AE		(_ULCAST_(1) << 28)
+#define MIPS_CONF4_IE		(_ULCAST_(3) << 29)
+#define MIPS_CONF4_TLBINV	(_ULCAST_(2) << 29)
+
+#define MIPS_CONF5_NF		(_ULCAST_(1) << 0)
+#define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)
+#define MIPS_CONF5_MRP		(_ULCAST_(1) << 3)
+#define MIPS_CONF5_LLB		(_ULCAST_(1) << 4)
+#define MIPS_CONF5_MVH		(_ULCAST_(1) << 5)
+#define MIPS_CONF5_VP		(_ULCAST_(1) << 7)
+#define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
+#define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
+#define MIPS_CONF5_L2C		(_ULCAST_(1) << 10)
+#define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
+#define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
+#define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
+#define MIPS_CONF5_K		(_ULCAST_(1) << 30)
+
+#define MIPS_CONF6_SYND		(_ULCAST_(1) << 13)
+/* proAptiv FTLB on/off bit */
+#define MIPS_CONF6_FTLBEN	(_ULCAST_(1) << 15)
+/* FTLB probability bits */
+#define MIPS_CONF6_FTLBP_SHIFT	(16)
+
+#define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
+
+#define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
+
+#define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
+#define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
+/* FTLB probability bits for R6 */
+#define MIPS_CONF7_FTLBP_SHIFT	(18)
+
+/* MAAR bit definitions */
+#define MIPS_MAAR_ADDR		((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
+#define MIPS_MAAR_ADDR_SHIFT	12
+#define MIPS_MAAR_S		(_ULCAST_(1) << 1)
+#define MIPS_MAAR_V		(_ULCAST_(1) << 0)
+
+/* CMGCRBase bit definitions */
+#define MIPS_CMGCRB_BASE	11
+#define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
+
+/*
+ * Bits in the MIPS32 Memory Segmentation registers.
+ */
+#define MIPS_SEGCFG_PA_SHIFT	9
+#define MIPS_SEGCFG_PA		(_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
+#define MIPS_SEGCFG_AM_SHIFT	4
+#define MIPS_SEGCFG_AM		(_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
+#define MIPS_SEGCFG_EU_SHIFT	3
+#define MIPS_SEGCFG_EU		(_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
+#define MIPS_SEGCFG_C_SHIFT	0
+#define MIPS_SEGCFG_C		(_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
+
+#define MIPS_SEGCFG_UUSK	_ULCAST_(7)
+#define MIPS_SEGCFG_USK		_ULCAST_(5)
+#define MIPS_SEGCFG_MUSUK	_ULCAST_(4)
+#define MIPS_SEGCFG_MUSK	_ULCAST_(3)
+#define MIPS_SEGCFG_MSK		_ULCAST_(2)
+#define MIPS_SEGCFG_MK		_ULCAST_(1)
+#define MIPS_SEGCFG_UK		_ULCAST_(0)
+
+#define MIPS_PWFIELD_GDI_SHIFT	24
+#define MIPS_PWFIELD_GDI_MASK	0x3f000000
+#define MIPS_PWFIELD_UDI_SHIFT	18
+#define MIPS_PWFIELD_UDI_MASK	0x00fc0000
+#define MIPS_PWFIELD_MDI_SHIFT	12
+#define MIPS_PWFIELD_MDI_MASK	0x0003f000
+#define MIPS_PWFIELD_PTI_SHIFT	6
+#define MIPS_PWFIELD_PTI_MASK	0x00000fc0
+#define MIPS_PWFIELD_PTEI_SHIFT	0
+#define MIPS_PWFIELD_PTEI_MASK	0x0000003f
+
+#define MIPS_PWSIZE_GDW_SHIFT	24
+#define MIPS_PWSIZE_GDW_MASK	0x3f000000
+#define MIPS_PWSIZE_UDW_SHIFT	18
+#define MIPS_PWSIZE_UDW_MASK	0x00fc0000
+#define MIPS_PWSIZE_MDW_SHIFT	12
+#define MIPS_PWSIZE_MDW_MASK	0x0003f000
+#define MIPS_PWSIZE_PTW_SHIFT	6
+#define MIPS_PWSIZE_PTW_MASK	0x00000fc0
+#define MIPS_PWSIZE_PTEW_SHIFT	0
+#define MIPS_PWSIZE_PTEW_MASK	0x0000003f
+
+#define MIPS_PWCTL_PWEN_SHIFT	31
+#define MIPS_PWCTL_PWEN_MASK	0x80000000
+#define MIPS_PWCTL_DPH_SHIFT	7
+#define MIPS_PWCTL_DPH_MASK	0x00000080
+#define MIPS_PWCTL_HUGEPG_SHIFT	6
+#define MIPS_PWCTL_HUGEPG_MASK	0x00000060
+#define MIPS_PWCTL_PSN_SHIFT	0
+#define MIPS_PWCTL_PSN_MASK	0x0000003f
+
+/* CDMMBase register bit definitions */
+#define MIPS_CDMMBASE_SIZE_SHIFT 0
+#define MIPS_CDMMBASE_SIZE	(_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
+#define MIPS_CDMMBASE_CI	(_ULCAST_(1) << 9)
+#define MIPS_CDMMBASE_EN	(_ULCAST_(1) << 10)
+#define MIPS_CDMMBASE_ADDR_SHIFT 11
+#define MIPS_CDMMBASE_ADDR_START 15
+
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT	19
+#define TX39_CONF_ICS_MASK	0x00380000
+#define TX39_CONF_ICS_1KB	0x00000000
+#define TX39_CONF_ICS_2KB	0x00080000
+#define TX39_CONF_ICS_4KB	0x00100000
+#define TX39_CONF_ICS_8KB	0x00180000
+#define TX39_CONF_ICS_16KB	0x00200000
+
+#define TX39_CONF_DCS_SHIFT	16
+#define TX39_CONF_DCS_MASK	0x00070000
+#define TX39_CONF_DCS_1KB	0x00000000
+#define TX39_CONF_DCS_2KB	0x00010000
+#define TX39_CONF_DCS_4KB	0x00020000
+#define TX39_CONF_DCS_8KB	0x00030000
+#define TX39_CONF_DCS_16KB	0x00040000
+
+#define TX39_CONF_CWFON		0x00004000
+#define TX39_CONF_WBON		0x00002000
+#define TX39_CONF_RF_SHIFT	10
+#define TX39_CONF_RF_MASK	0x00000c00
+#define TX39_CONF_DOZE		0x00000200
+#define TX39_CONF_HALT		0x00000100
+#define TX39_CONF_LOCK		0x00000080
+#define TX39_CONF_ICE		0x00000020
+#define TX39_CONF_DCE		0x00000010
+#define TX39_CONF_IRSIZE_SHIFT	2
+#define TX39_CONF_IRSIZE_MASK	0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT	0
+#define TX39_CONF_DRSIZE_MASK	0x00000003
+
+/*
+ * Interesting Bits in the R10K CP0 Branch Diagnostic Register
+ */
+/* Disable Branch Target Address Cache */
+#define R10K_DIAG_D_BTAC	(_ULCAST_(1) << 27)
+/* Enable Branch Prediction Global History */
+#define R10K_DIAG_E_GHIST	(_ULCAST_(1) << 26)
+/* Disable Branch Return Cache */
+#define R10K_DIAG_D_BRC		(_ULCAST_(1) << 22)
+
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION	$0
+#define CP1_UFR		$1
+#define CP1_UNFR	$4
+#define CP1_FCCR	$25
+#define CP1_FEXR	$26
+#define CP1_FENR	$28
+#define CP1_STATUS	$31
+
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
+ */
+#define MIPS_FPIR_S		(_ULCAST_(1) << 16)
+#define MIPS_FPIR_D		(_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
+#define MIPS_FPIR_W		(_ULCAST_(1) << 20)
+#define MIPS_FPIR_L		(_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
+#define MIPS_FPIR_HAS2008	(_ULCAST_(1) << 23)
+#define MIPS_FPIR_UFRP		(_ULCAST_(1) << 28)
+#define MIPS_FPIR_FREP		(_ULCAST_(1) << 29)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
+ */
+#define MIPS_FCCR_CONDX_S	0
+#define MIPS_FCCR_CONDX		(_ULCAST_(255) << MIPS_FCCR_CONDX_S)
+#define MIPS_FCCR_COND0_S	0
+#define MIPS_FCCR_COND0		(_ULCAST_(1) << MIPS_FCCR_COND0_S)
+#define MIPS_FCCR_COND1_S	1
+#define MIPS_FCCR_COND1		(_ULCAST_(1) << MIPS_FCCR_COND1_S)
+#define MIPS_FCCR_COND2_S	2
+#define MIPS_FCCR_COND2		(_ULCAST_(1) << MIPS_FCCR_COND2_S)
+#define MIPS_FCCR_COND3_S	3
+#define MIPS_FCCR_COND3		(_ULCAST_(1) << MIPS_FCCR_COND3_S)
+#define MIPS_FCCR_COND4_S	4
+#define MIPS_FCCR_COND4		(_ULCAST_(1) << MIPS_FCCR_COND4_S)
+#define MIPS_FCCR_COND5_S	5
+#define MIPS_FCCR_COND5		(_ULCAST_(1) << MIPS_FCCR_COND5_S)
+#define MIPS_FCCR_COND6_S	6
+#define MIPS_FCCR_COND6		(_ULCAST_(1) << MIPS_FCCR_COND6_S)
+#define MIPS_FCCR_COND7_S	7
+#define MIPS_FCCR_COND7		(_ULCAST_(1) << MIPS_FCCR_COND7_S)
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
+ */
+#define MIPS_FENR_FS_S		2
+#define MIPS_FENR_FS		(_ULCAST_(1) << MIPS_FENR_FS_S)
+
+/*
+ * FPU Status Register Values
+ */
+#define FPU_CSR_COND_S	23					/* $fcc0 */
+#define FPU_CSR_COND	(_ULCAST_(1) << FPU_CSR_COND_S)
+
+#define FPU_CSR_FS_S	24		/* flush denormalised results to 0 */
+#define FPU_CSR_FS	(_ULCAST_(1) << FPU_CSR_FS_S)
+
+#define FPU_CSR_CONDX_S	25					/* $fcc[7:1] */
+#define FPU_CSR_CONDX	(_ULCAST_(127) << FPU_CSR_CONDX_S)
+#define FPU_CSR_COND1_S	25					/* $fcc1 */
+#define FPU_CSR_COND1	(_ULCAST_(1) << FPU_CSR_COND1_S)
+#define FPU_CSR_COND2_S	26					/* $fcc2 */
+#define FPU_CSR_COND2	(_ULCAST_(1) << FPU_CSR_COND2_S)
+#define FPU_CSR_COND3_S	27					/* $fcc3 */
+#define FPU_CSR_COND3	(_ULCAST_(1) << FPU_CSR_COND3_S)
+#define FPU_CSR_COND4_S	28					/* $fcc4 */
+#define FPU_CSR_COND4	(_ULCAST_(1) << FPU_CSR_COND4_S)
+#define FPU_CSR_COND5_S	29					/* $fcc5 */
+#define FPU_CSR_COND5	(_ULCAST_(1) << FPU_CSR_COND5_S)
+#define FPU_CSR_COND6_S	30					/* $fcc6 */
+#define FPU_CSR_COND6	(_ULCAST_(1) << FPU_CSR_COND6_S)
+#define FPU_CSR_COND7_S	31					/* $fcc7 */
+#define FPU_CSR_COND7	(_ULCAST_(1) << FPU_CSR_COND7_S)
+
+/*
+ * Bits 22:20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ */
+#define FPU_CSR_RSVD	(_ULCAST_(7) << 20)
+
+#define FPU_CSR_ABS2008	(_ULCAST_(1) << 19)
+#define FPU_CSR_NAN2008	(_ULCAST_(1) << 18)
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X	0x0003f000
+#define FPU_CSR_UNI_X	0x00020000
+#define FPU_CSR_INV_X	0x00010000
+#define FPU_CSR_DIV_X	0x00008000
+#define FPU_CSR_OVF_X	0x00004000
+#define FPU_CSR_UDF_X	0x00002000
+#define FPU_CSR_INE_X	0x00001000
+
+#define FPU_CSR_ALL_E	0x00000f80
+#define FPU_CSR_INV_E	0x00000800
+#define FPU_CSR_DIV_E	0x00000400
+#define FPU_CSR_OVF_E	0x00000200
+#define FPU_CSR_UDF_E	0x00000100
+#define FPU_CSR_INE_E	0x00000080
+
+#define FPU_CSR_ALL_S	0x0000007c
+#define FPU_CSR_INV_S	0x00000040
+#define FPU_CSR_DIV_S	0x00000020
+#define FPU_CSR_OVF_S	0x00000010
+#define FPU_CSR_UDF_S	0x00000008
+#define FPU_CSR_INE_S	0x00000004
+
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM	0x00000003
+#define FPU_CSR_RN	0x0	/* nearest */
+#define FPU_CSR_RZ	0x1	/* towards zero */
+#define FPU_CSR_RU	0x2	/* towards +Infinity */
+#define FPU_CSR_RD	0x3	/* towards -Infinity */
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
+ */
+#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
+	defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
+#define get_isa16_mode(x)		((x) & 0x1)
+#define msk_isa16_mode(x)		((x) & ~0x1)
+#define set_isa16_mode(x)		do { (x) |= 0x1; } while (0)
+#else
+#define get_isa16_mode(x)		0
+#define msk_isa16_mode(x)		(x)
+#define set_isa16_mode(x)		do { } while (0)
+#endif
+
+/*
+ * microMIPS instructions can be 16-bit or 32-bit in length. This
+ * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
+ */
+static inline int mm_insn_16bit(u16 insn)
+{
+	u16 opcode = (insn >> 10) & 0x7;
+
+	return (opcode >= 1 && opcode <= 3) ? 1 : 0;
+}
+
+/*
+ * TLB Invalidate Flush
+ */
+static inline void tlbinvf(void)
+{
+	__asm__ __volatile__(
+		".set push\n\t"
+		".set noreorder\n\t"
+		".word 0x42000004\n\t" /* tlbinvf */
+		".set pop");
+}
+
+
+/*
+ * Functions to access the R10000 performance counters.	 These are basically
+ * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
+ * performance counter number encoded into bits 1 ... 5 of the instruction.
+ * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
+ * disassembler these will look like an access to sel 0 or 1.
+ */
+#define read_r10k_perf_cntr(counter)				\
+({								\
+	unsigned int __res;					\
+	__asm__ __volatile__(					\
+	"mfpc\t%0, %1"						\
+	: "=r" (__res)						\
+	: "i" (counter));					\
+								\
+	__res;							\
+})
+
+#define write_r10k_perf_cntr(counter,val)			\
+do {								\
+	__asm__ __volatile__(					\
+	"mtpc\t%0, %1"						\
+	:							\
+	: "r" (val), "i" (counter));				\
+} while (0)
+
+#define read_r10k_perf_event(counter)				\
+({								\
+	unsigned int __res;					\
+	__asm__ __volatile__(					\
+	"mfps\t%0, %1"						\
+	: "=r" (__res)						\
+	: "i" (counter));					\
+								\
+	__res;							\
+})
+
+#define write_r10k_perf_cntl(counter,val)			\
+do {								\
+	__asm__ __volatile__(					\
+	"mtps\t%0, %1"						\
+	:							\
+	: "r" (val), "i" (counter));				\
+} while (0)
+
+
+/*
+ * Macros to access the system control coprocessor
+ */
+
+#define __read_32bit_c0_register(source, sel)				\
+({ unsigned int __res;							\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			"mfc0\t%0, " #source "\n\t"			\
+			: "=r" (__res));				\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips32\n\t"				\
+			"mfc0\t%0, " #source ", " #sel "\n\t"		\
+			".set\tmips0\n\t"				\
+			: "=r" (__res));				\
+	__res;								\
+})
+
+#define __read_64bit_c0_register(source, sel)				\
+({ unsigned long long __res;						\
+	if (sizeof(unsigned long) == 4)					\
+		__res = __read_64bit_c0_split(source, sel);		\
+	else if (sel == 0)						\
+		__asm__ __volatile__(					\
+			".set\tmips3\n\t"				\
+			"dmfc0\t%0, " #source "\n\t"			\
+			".set\tmips0"					\
+			: "=r" (__res));				\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
+			".set\tmips0"					\
+			: "=r" (__res));				\
+	__res;								\
+})
+
+#define __write_32bit_c0_register(register, sel, value)			\
+do {									\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			"mtc0\t%z0, " #register "\n\t"			\
+			: : "Jr" ((unsigned int)(value)));		\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips32\n\t"				\
+			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
+			".set\tmips0"					\
+			: : "Jr" ((unsigned int)(value)));		\
+} while (0)
+
+#define __write_64bit_c0_register(register, sel, value)			\
+do {									\
+	if (sizeof(unsigned long) == 4)					\
+		__write_64bit_c0_split(register, sel, value);		\
+	else if (sel == 0)						\
+		__asm__ __volatile__(					\
+			".set\tmips3\n\t"				\
+			"dmtc0\t%z0, " #register "\n\t"			\
+			".set\tmips0"					\
+			: : "Jr" (value));				\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
+			".set\tmips0"					\
+			: : "Jr" (value));				\
+} while (0)
+
+#define __read_ulong_c0_register(reg, sel)				\
+	((sizeof(unsigned long) == 4) ?					\
+	(unsigned long) __read_32bit_c0_register(reg, sel) :		\
+	(unsigned long) __read_64bit_c0_register(reg, sel))
+
+#define __write_ulong_c0_register(reg, sel, val)			\
+do {									\
+	if (sizeof(unsigned long) == 4)					\
+		__write_32bit_c0_register(reg, sel, val);		\
+	else								\
+		__write_64bit_c0_register(reg, sel, val);		\
+} while (0)
+
+/*
+ * On RM7000/RM9000 these are uses to access cop0 set 1 registers
+ */
+#define __read_32bit_c0_ctrl_register(source)				\
+({ unsigned int __res;							\
+	__asm__ __volatile__(						\
+		"cfc0\t%0, " #source "\n\t"				\
+		: "=r" (__res));					\
+	__res;								\
+})
+
+#define __write_32bit_c0_ctrl_register(register, value)			\
+do {									\
+	__asm__ __volatile__(						\
+		"ctc0\t%z0, " #register "\n\t"				\
+		: : "Jr" ((unsigned int)(value)));			\
+} while (0)
+
+/*
+ * These versions are only needed for systems with more than 38 bits of
+ * physical address space running the 32-bit kernel.  That's none atm :-)
+ */
+#define __read_64bit_c0_split(source, sel)				\
+({									\
+	unsigned long long __val;					\
+									\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dmfc0\t%M0, " #source "\n\t"			\
+			"dsll\t%L0, %M0, 32\n\t"			\
+			"dsra\t%M0, %M0, 32\n\t"			\
+			"dsra\t%L0, %L0, 32\n\t"			\
+			".set\tmips0"					\
+			: "=r" (__val));				\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dmfc0\t%M0, " #source ", " #sel "\n\t"		\
+			"dsll\t%L0, %M0, 32\n\t"			\
+			"dsra\t%M0, %M0, 32\n\t"			\
+			"dsra\t%L0, %L0, 32\n\t"			\
+			".set\tmips0"					\
+			: "=r" (__val));				\
+									\
+	__val;								\
+})
+
+#define __write_64bit_c0_split(source, sel, val)			\
+do {									\
+	if (sel == 0)							\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dsll\t%L0, %L0, 32\n\t"			\
+			"dsrl\t%L0, %L0, 32\n\t"			\
+			"dsll\t%M0, %M0, 32\n\t"			\
+			"or\t%L0, %L0, %M0\n\t"				\
+			"dmtc0\t%L0, " #source "\n\t"			\
+			".set\tmips0"					\
+			: : "r" (val));					\
+	else								\
+		__asm__ __volatile__(					\
+			".set\tmips64\n\t"				\
+			"dsll\t%L0, %L0, 32\n\t"			\
+			"dsrl\t%L0, %L0, 32\n\t"			\
+			"dsll\t%M0, %M0, 32\n\t"			\
+			"or\t%L0, %L0, %M0\n\t"				\
+			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
+			".set\tmips0"					\
+			: : "r" (val));					\
+} while (0)
+
+#define __readx_32bit_c0_register(source)				\
+({									\
+	unsigned int __res;						\
+									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noat					\n"	\
+	"	.set	mips32r2				\n"	\
+	"	.insn						\n"	\
+	"	# mfhc0 $1, %1					\n"	\
+	"	.word	(0x40410000 | ((%1 & 0x1f) << 11))	\n"	\
+	"	move	%0, $1					\n"	\
+	"	.set	pop					\n"	\
+	: "=r" (__res)							\
+	: "i" (source));						\
+	__res;								\
+})
+
+#define __writex_32bit_c0_register(register, value)			\
+({									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noat					\n"	\
+	"	.set	mips32r2				\n"	\
+	"	move	$1, %0					\n"	\
+	"	# mthc0 $1, %1					\n"	\
+	"	.insn						\n"	\
+	"	.word	(0x40c10000 | ((%1 & 0x1f) << 11))	\n"	\
+	"	.set	pop					\n"	\
+	:								\
+	: "r" (value), "i" (register));					\
+})
+
+#define read_c0_index()		__read_32bit_c0_register($0, 0)
+#define write_c0_index(val)	__write_32bit_c0_register($0, 0, val)
+
+#define read_c0_random()	__read_32bit_c0_register($1, 0)
+#define write_c0_random(val)	__write_32bit_c0_register($1, 0, val)
+
+#define read_c0_entrylo0()	__read_ulong_c0_register($2, 0)
+#define write_c0_entrylo0(val)	__write_ulong_c0_register($2, 0, val)
+
+#define readx_c0_entrylo0()	__readx_32bit_c0_register(2)
+#define writex_c0_entrylo0(val)	__writex_32bit_c0_register(2, val)
+
+#define read_c0_entrylo1()	__read_ulong_c0_register($3, 0)
+#define write_c0_entrylo1(val)	__write_ulong_c0_register($3, 0, val)
+
+#define readx_c0_entrylo1()	__readx_32bit_c0_register(3)
+#define writex_c0_entrylo1(val)	__writex_32bit_c0_register(3, val)
+
+#define read_c0_conf()		__read_32bit_c0_register($3, 0)
+#define write_c0_conf(val)	__write_32bit_c0_register($3, 0, val)
+
+#define read_c0_context()	__read_ulong_c0_register($4, 0)
+#define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)
+
+#define read_c0_userlocal()	__read_ulong_c0_register($4, 2)
+#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
+
+#define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
+
+#define read_c0_pagegrain()	__read_32bit_c0_register($5, 1)
+#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
+
+#define read_c0_wired()		__read_32bit_c0_register($6, 0)
+#define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)
+
+#define read_c0_info()		__read_32bit_c0_register($7, 0)
+
+#define read_c0_cache()		__read_32bit_c0_register($7, 0) /* TX39xx */
+#define write_c0_cache(val)	__write_32bit_c0_register($7, 0, val)
+
+#define read_c0_badvaddr()	__read_ulong_c0_register($8, 0)
+#define write_c0_badvaddr(val)	__write_ulong_c0_register($8, 0, val)
+
+#define read_c0_count()		__read_32bit_c0_register($9, 0)
+#define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)
+
+#define read_c0_count2()	__read_32bit_c0_register($9, 6) /* pnx8550 */
+#define write_c0_count2(val)	__write_32bit_c0_register($9, 6, val)
+
+#define read_c0_count3()	__read_32bit_c0_register($9, 7) /* pnx8550 */
+#define write_c0_count3(val)	__write_32bit_c0_register($9, 7, val)
+
+#define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
+#define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)
+
+#define read_c0_compare()	__read_32bit_c0_register($11, 0)
+#define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
+
+#define read_c0_compare2()	__read_32bit_c0_register($11, 6) /* pnx8550 */
+#define write_c0_compare2(val)	__write_32bit_c0_register($11, 6, val)
+
+#define read_c0_compare3()	__read_32bit_c0_register($11, 7) /* pnx8550 */
+#define write_c0_compare3(val)	__write_32bit_c0_register($11, 7, val)
+
+#define read_c0_status()	__read_32bit_c0_register($12, 0)
+
+#define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
+
+#define read_c0_cause()		__read_32bit_c0_register($13, 0)
+#define write_c0_cause(val)	__write_32bit_c0_register($13, 0, val)
+
+#define read_c0_epc()		__read_ulong_c0_register($14, 0)
+#define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)
+
+#define read_c0_prid()		__read_32bit_c0_register($15, 0)
+
+#define read_c0_cmgcrbase()	__read_ulong_c0_register($15, 3)
+
+#define read_c0_config()	__read_32bit_c0_register($16, 0)
+#define read_c0_config1()	__read_32bit_c0_register($16, 1)
+#define read_c0_config2()	__read_32bit_c0_register($16, 2)
+#define read_c0_config3()	__read_32bit_c0_register($16, 3)
+#define read_c0_config4()	__read_32bit_c0_register($16, 4)
+#define read_c0_config5()	__read_32bit_c0_register($16, 5)
+#define read_c0_config6()	__read_32bit_c0_register($16, 6)
+#define read_c0_config7()	__read_32bit_c0_register($16, 7)
+#define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
+#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
+#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
+#define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
+#define write_c0_config4(val)	__write_32bit_c0_register($16, 4, val)
+#define write_c0_config5(val)	__write_32bit_c0_register($16, 5, val)
+#define write_c0_config6(val)	__write_32bit_c0_register($16, 6, val)
+#define write_c0_config7(val)	__write_32bit_c0_register($16, 7, val)
+
+#define read_c0_lladdr()	__read_ulong_c0_register($17, 0)
+#define write_c0_lladdr(val)	__write_ulong_c0_register($17, 0, val)
+#define read_c0_maar()		__read_ulong_c0_register($17, 1)
+#define write_c0_maar(val)	__write_ulong_c0_register($17, 1, val)
+#define read_c0_maari()		__read_32bit_c0_register($17, 2)
+#define write_c0_maari(val)	__write_32bit_c0_register($17, 2, val)
+
+/*
+ * The WatchLo register.  There may be up to 8 of them.
+ */
+#define read_c0_watchlo0()	__read_ulong_c0_register($18, 0)
+#define read_c0_watchlo1()	__read_ulong_c0_register($18, 1)
+#define read_c0_watchlo2()	__read_ulong_c0_register($18, 2)
+#define read_c0_watchlo3()	__read_ulong_c0_register($18, 3)
+#define read_c0_watchlo4()	__read_ulong_c0_register($18, 4)
+#define read_c0_watchlo5()	__read_ulong_c0_register($18, 5)
+#define read_c0_watchlo6()	__read_ulong_c0_register($18, 6)
+#define read_c0_watchlo7()	__read_ulong_c0_register($18, 7)
+#define write_c0_watchlo0(val)	__write_ulong_c0_register($18, 0, val)
+#define write_c0_watchlo1(val)	__write_ulong_c0_register($18, 1, val)
+#define write_c0_watchlo2(val)	__write_ulong_c0_register($18, 2, val)
+#define write_c0_watchlo3(val)	__write_ulong_c0_register($18, 3, val)
+#define write_c0_watchlo4(val)	__write_ulong_c0_register($18, 4, val)
+#define write_c0_watchlo5(val)	__write_ulong_c0_register($18, 5, val)
+#define write_c0_watchlo6(val)	__write_ulong_c0_register($18, 6, val)
+#define write_c0_watchlo7(val)	__write_ulong_c0_register($18, 7, val)
+
+/*
+ * The WatchHi register.  There may be up to 8 of them.
+ */
+#define read_c0_watchhi0()	__read_32bit_c0_register($19, 0)
+#define read_c0_watchhi1()	__read_32bit_c0_register($19, 1)
+#define read_c0_watchhi2()	__read_32bit_c0_register($19, 2)
+#define read_c0_watchhi3()	__read_32bit_c0_register($19, 3)
+#define read_c0_watchhi4()	__read_32bit_c0_register($19, 4)
+#define read_c0_watchhi5()	__read_32bit_c0_register($19, 5)
+#define read_c0_watchhi6()	__read_32bit_c0_register($19, 6)
+#define read_c0_watchhi7()	__read_32bit_c0_register($19, 7)
+
+#define write_c0_watchhi0(val)	__write_32bit_c0_register($19, 0, val)
+#define write_c0_watchhi1(val)	__write_32bit_c0_register($19, 1, val)
+#define write_c0_watchhi2(val)	__write_32bit_c0_register($19, 2, val)
+#define write_c0_watchhi3(val)	__write_32bit_c0_register($19, 3, val)
+#define write_c0_watchhi4(val)	__write_32bit_c0_register($19, 4, val)
+#define write_c0_watchhi5(val)	__write_32bit_c0_register($19, 5, val)
+#define write_c0_watchhi6(val)	__write_32bit_c0_register($19, 6, val)
+#define write_c0_watchhi7(val)	__write_32bit_c0_register($19, 7, val)
+
+#define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
+#define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)
+
+#define read_c0_intcontrol()	__read_32bit_c0_ctrl_register($20)
+#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
+
+#define read_c0_framemask()	__read_32bit_c0_register($21, 0)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
+
+#define read_c0_diag()		__read_32bit_c0_register($22, 0)
+#define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)
+
+/* R10K CP0 Branch Diagnostic register is 64bits wide */
+#define read_c0_r10k_diag()	__read_64bit_c0_register($22, 0)
+#define write_c0_r10k_diag(val)	__write_64bit_c0_register($22, 0, val)
+
+#define read_c0_diag1()		__read_32bit_c0_register($22, 1)
+#define write_c0_diag1(val)	__write_32bit_c0_register($22, 1, val)
+
+#define read_c0_diag2()		__read_32bit_c0_register($22, 2)
+#define write_c0_diag2(val)	__write_32bit_c0_register($22, 2, val)
+
+#define read_c0_diag3()		__read_32bit_c0_register($22, 3)
+#define write_c0_diag3(val)	__write_32bit_c0_register($22, 3, val)
+
+#define read_c0_diag4()		__read_32bit_c0_register($22, 4)
+#define write_c0_diag4(val)	__write_32bit_c0_register($22, 4, val)
+
+#define read_c0_diag5()		__read_32bit_c0_register($22, 5)
+#define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
+
+#define read_c0_debug()		__read_32bit_c0_register($23, 0)
+#define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
+
+#define read_c0_depc()		__read_ulong_c0_register($24, 0)
+#define write_c0_depc(val)	__write_ulong_c0_register($24, 0, val)
+
+/*
+ * MIPS32 / MIPS64 performance counters
+ */
+#define read_c0_perfctrl0()	__read_32bit_c0_register($25, 0)
+#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
+#define read_c0_perfcntr0()	__read_32bit_c0_register($25, 1)
+#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define read_c0_perfcntr0_64()	__read_64bit_c0_register($25, 1)
+#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
+#define read_c0_perfctrl1()	__read_32bit_c0_register($25, 2)
+#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
+#define read_c0_perfcntr1()	__read_32bit_c0_register($25, 3)
+#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define read_c0_perfcntr1_64()	__read_64bit_c0_register($25, 3)
+#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
+#define read_c0_perfctrl2()	__read_32bit_c0_register($25, 4)
+#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
+#define read_c0_perfcntr2()	__read_32bit_c0_register($25, 5)
+#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define read_c0_perfcntr2_64()	__read_64bit_c0_register($25, 5)
+#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
+#define read_c0_perfctrl3()	__read_32bit_c0_register($25, 6)
+#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
+#define read_c0_perfcntr3()	__read_32bit_c0_register($25, 7)
+#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
+#define read_c0_perfcntr3_64()	__read_64bit_c0_register($25, 7)
+#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
+
+#define read_c0_ecc()		__read_32bit_c0_register($26, 0)
+#define write_c0_ecc(val)	__write_32bit_c0_register($26, 0, val)
+
+#define read_c0_derraddr0()	__read_ulong_c0_register($26, 1)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
+
+#define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)
+
+#define read_c0_derraddr1()	__read_ulong_c0_register($27, 1)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
+
+#define read_c0_taglo()		__read_32bit_c0_register($28, 0)
+#define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)
+
+#define read_c0_dtaglo()	__read_32bit_c0_register($28, 2)
+#define write_c0_dtaglo(val)	__write_32bit_c0_register($28, 2, val)
+
+#define read_c0_ddatalo()	__read_32bit_c0_register($28, 3)
+#define write_c0_ddatalo(val)	__write_32bit_c0_register($28, 3, val)
+
+#define read_c0_staglo()	__read_32bit_c0_register($28, 4)
+#define write_c0_staglo(val)	__write_32bit_c0_register($28, 4, val)
+
+#define read_c0_taghi()		__read_32bit_c0_register($29, 0)
+#define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)
+
+#define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
+#define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)
+
+/* MIPSR2 */
+#define read_c0_hwrena()	__read_32bit_c0_register($7, 0)
+#define write_c0_hwrena(val)	__write_32bit_c0_register($7, 0, val)
+
+#define read_c0_intctl()	__read_32bit_c0_register($12, 1)
+#define write_c0_intctl(val)	__write_32bit_c0_register($12, 1, val)
+
+#define read_c0_srsctl()	__read_32bit_c0_register($12, 2)
+#define write_c0_srsctl(val)	__write_32bit_c0_register($12, 2, val)
+
+#define read_c0_srsmap()	__read_32bit_c0_register($12, 3)
+#define write_c0_srsmap(val)	__write_32bit_c0_register($12, 3, val)
+
+#define read_c0_ebase()		__read_32bit_c0_register($15, 1)
+#define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
+
+#define read_c0_cdmmbase()	__read_ulong_c0_register($15, 2)
+#define write_c0_cdmmbase(val)	__write_ulong_c0_register($15, 2, val)
+
+/* MIPSR3 */
+#define read_c0_segctl0()	__read_32bit_c0_register($5, 2)
+#define write_c0_segctl0(val)	__write_32bit_c0_register($5, 2, val)
+
+#define read_c0_segctl1()	__read_32bit_c0_register($5, 3)
+#define write_c0_segctl1(val)	__write_32bit_c0_register($5, 3, val)
+
+#define read_c0_segctl2()	__read_32bit_c0_register($5, 4)
+#define write_c0_segctl2(val)	__write_32bit_c0_register($5, 4, val)
+
+/* Hardware Page Table Walker */
+#define read_c0_pwbase()	__read_ulong_c0_register($5, 5)
+#define write_c0_pwbase(val)	__write_ulong_c0_register($5, 5, val)
+
+#define read_c0_pwfield()	__read_ulong_c0_register($5, 6)
+#define write_c0_pwfield(val)	__write_ulong_c0_register($5, 6, val)
+
+#define read_c0_pwsize()	__read_ulong_c0_register($5, 7)
+#define write_c0_pwsize(val)	__write_ulong_c0_register($5, 7, val)
+
+#define read_c0_pwctl()		__read_32bit_c0_register($6, 6)
+#define write_c0_pwctl(val)	__write_32bit_c0_register($6, 6, val)
+
+/* Cavium OCTEON (cnMIPS) */
+#define read_c0_cvmcount()	__read_ulong_c0_register($9, 6)
+#define write_c0_cvmcount(val)	__write_ulong_c0_register($9, 6, val)
+
+#define read_c0_cvmctl()	__read_64bit_c0_register($9, 7)
+#define write_c0_cvmctl(val)	__write_64bit_c0_register($9, 7, val)
+
+#define read_c0_cvmmemctl()	__read_64bit_c0_register($11, 7)
+#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
+/*
+ * The cacheerr registers are not standardized.	 On OCTEON, they are
+ * 64 bits wide.
+ */
+#define read_octeon_c0_icacheerr()	__read_64bit_c0_register($27, 0)
+#define write_octeon_c0_icacheerr(val)	__write_64bit_c0_register($27, 0, val)
+
+#define read_octeon_c0_dcacheerr()	__read_64bit_c0_register($27, 1)
+#define write_octeon_c0_dcacheerr(val)	__write_64bit_c0_register($27, 1, val)
+
+/* BMIPS3300 */
+#define read_c0_brcm_config_0()		__read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config_0(val)	__write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_bus_pll()		__read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bus_pll(val)	__write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_reset()		__read_32bit_c0_register($22, 5)
+#define write_c0_brcm_reset(val)	__write_32bit_c0_register($22, 5, val)
+
+/* BMIPS43xx */
+#define read_c0_brcm_cmt_intr()		__read_32bit_c0_register($22, 1)
+#define write_c0_brcm_cmt_intr(val)	__write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_cmt_ctrl()		__read_32bit_c0_register($22, 2)
+#define write_c0_brcm_cmt_ctrl(val)	__write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_cmt_local()	__read_32bit_c0_register($22, 3)
+#define write_c0_brcm_cmt_local(val)	__write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_config_1()		__read_32bit_c0_register($22, 5)
+#define write_c0_brcm_config_1(val)	__write_32bit_c0_register($22, 5, val)
+
+#define read_c0_brcm_cbr()		__read_32bit_c0_register($22, 6)
+#define write_c0_brcm_cbr(val)		__write_32bit_c0_register($22, 6, val)
+
+/* BMIPS5000 */
+#define read_c0_brcm_config()		__read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config(val)	__write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_mode()		__read_32bit_c0_register($22, 1)
+#define write_c0_brcm_mode(val)		__write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_action()		__read_32bit_c0_register($22, 2)
+#define write_c0_brcm_action(val)	__write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_edsp()		__read_32bit_c0_register($22, 3)
+#define write_c0_brcm_edsp(val)		__write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_bootvec()		__read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bootvec(val)	__write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_sleepcount()	__read_32bit_c0_register($22, 7)
+#define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)
+
+/*
+ * Macros to access the floating point coprocessor control registers
+ */
+#define _read_32bit_cp1_register(source, gas_hardfloat)			\
+({									\
+	unsigned int __res;						\
+									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	reorder					\n"	\
+	"	# gas fails to assemble cfc1 for some archs,	\n"	\
+	"	# like Octeon.					\n"	\
+	"	.set	mips1					\n"	\
+	"	"STR(gas_hardfloat)"				\n"	\
+	"	cfc1	%0,"STR(source)"			\n"	\
+	"	.set	pop					\n"	\
+	: "=r" (__res));						\
+	__res;								\
+})
+
+#define _write_32bit_cp1_register(dest, val, gas_hardfloat)		\
+({									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	reorder					\n"	\
+	"	"STR(gas_hardfloat)"				\n"	\
+	"	ctc1	%0,"STR(dest)"				\n"	\
+	"	.set	pop					\n"	\
+	: : "r" (val));							\
+})
+
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, .set hardfloat)
+#define write_32bit_cp1_register(dest, val)				\
+	_write_32bit_cp1_register(dest, val, .set hardfloat)
+#else
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, )
+#define write_32bit_cp1_register(dest, val)				\
+	_write_32bit_cp1_register(dest, val, )
+#endif
+
+#ifdef HAVE_AS_DSP
+#define rddsp(mask)							\
+({									\
+	unsigned int __dspctl;						\
+									\
+	__asm__ __volatile__(						\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	rddsp	%0, %x1					\n"	\
+	"	.set pop					\n"	\
+	: "=r" (__dspctl)						\
+	: "i" (mask));							\
+	__dspctl;							\
+})
+
+#define wrdsp(val, mask)						\
+({									\
+	__asm__ __volatile__(						\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	wrdsp	%0, %x1					\n"	\
+	"	.set pop					\n"	\
+	:								\
+	: "r" (val), "i" (mask));					\
+})
+
+#define mflo0()								\
+({									\
+	long mflo0;							\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mflo %0, $ac0					\n"	\
+	"	.set pop					\n"	\
+	: "=r" (mflo0));						\
+	mflo0;								\
+})
+
+#define mflo1()								\
+({									\
+	long mflo1;							\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mflo %0, $ac1					\n"	\
+	"	.set pop					\n"	\
+	: "=r" (mflo1));						\
+	mflo1;								\
+})
+
+#define mflo2()								\
+({									\
+	long mflo2;							\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mflo %0, $ac2					\n"	\
+	"	.set pop					\n"	\
+	: "=r" (mflo2));						\
+	mflo2;								\
+})
+
+#define mflo3()								\
+({									\
+	long mflo3;							\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mflo %0, $ac3					\n"	\
+	"	.set pop					\n"	\
+	: "=r" (mflo3));						\
+	mflo3;								\
+})
+
+#define mfhi0()								\
+({									\
+	long mfhi0;							\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mfhi %0, $ac0					\n"	\
+	"	.set pop					\n"	\
+	: "=r" (mfhi0));						\
+	mfhi0;								\
+})
+
+#define mfhi1()								\
+({									\
+	long mfhi1;							\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mfhi %0, $ac1					\n"	\
+	"	.set pop					\n"	\
+	: "=r" (mfhi1));						\
+	mfhi1;								\
+})
+
+#define mfhi2()								\
+({									\
+	long mfhi2;							\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mfhi %0, $ac2					\n"	\
+	"	.set pop					\n"	\
+	: "=r" (mfhi2));						\
+	mfhi2;								\
+})
+
+#define mfhi3()								\
+({									\
+	long mfhi3;							\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mfhi %0, $ac3					\n"	\
+	"	.set pop					\n"	\
+	: "=r" (mfhi3));						\
+	mfhi3;								\
+})
+
+
+#define mtlo0(x)							\
+({									\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mtlo %0, $ac0					\n"	\
+	"	.set pop					\n"	\
+	:								\
+	: "r" (x));							\
+})
+
+#define mtlo1(x)							\
+({									\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mtlo %0, $ac1					\n"	\
+	"	.set pop					\n"	\
+	:								\
+	: "r" (x));							\
+})
+
+#define mtlo2(x)							\
+({									\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mtlo %0, $ac2					\n"	\
+	"	.set pop					\n"	\
+	:								\
+	: "r" (x));							\
+})
+
+#define mtlo3(x)							\
+({									\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mtlo %0, $ac3					\n"	\
+	"	.set pop					\n"	\
+	:								\
+	: "r" (x));							\
+})
+
+#define mthi0(x)							\
+({									\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mthi %0, $ac0					\n"	\
+	"	.set pop					\n"	\
+	:								\
+	: "r" (x));							\
+})
+
+#define mthi1(x)							\
+({									\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mthi %0, $ac1					\n"	\
+	"	.set pop					\n"	\
+	:								\
+	: "r" (x));							\
+})
+
+#define mthi2(x)							\
+({									\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mthi %0, $ac2					\n"	\
+	"	.set pop					\n"	\
+	:								\
+	: "r" (x));							\
+})
+
+#define mthi3(x)							\
+({									\
+	__asm__(							\
+	"	.set push					\n"	\
+	"	.set dsp					\n"	\
+	"	mthi %0, $ac3					\n"	\
+	"	.set pop					\n"	\
+	:								\
+	: "r" (x));							\
+})
+
+#else
+
+#ifdef CONFIG_CPU_MICROMIPS
+#define rddsp(mask)							\
+({									\
+	unsigned int __res;						\
+									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noat					\n"	\
+	"	# rddsp $1, %x1					\n"	\
+	"	.hword	((0x0020067c | (%x1 << 14)) >> 16)	\n"	\
+	"	.hword	((0x0020067c | (%x1 << 14)) & 0xffff)	\n"	\
+	"	move	%0, $1					\n"	\
+	"	.set	pop					\n"	\
+	: "=r" (__res)							\
+	: "i" (mask));							\
+	__res;								\
+})
+
+#define wrdsp(val, mask)						\
+({									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noat					\n"	\
+	"	move	$1, %0					\n"	\
+	"	# wrdsp $1, %x1					\n"	\
+	"	.hword	((0x0020167c | (%x1 << 14)) >> 16)	\n"	\
+	"	.hword	((0x0020167c | (%x1 << 14)) & 0xffff)	\n"	\
+	"	.set	pop					\n"	\
+	:								\
+	: "r" (val), "i" (mask));					\
+})
+
+#define _umips_dsp_mfxxx(ins)						\
+({									\
+	unsigned long __treg;						\
+									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noat					\n"	\
+	"	.hword	0x0001					\n"	\
+	"	.hword	%x1					\n"	\
+	"	move	%0, $1					\n"	\
+	"	.set	pop					\n"	\
+	: "=r" (__treg)							\
+	: "i" (ins));							\
+	__treg;								\
+})
+
+#define _umips_dsp_mtxxx(val, ins)					\
+({									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noat					\n"	\
+	"	move	$1, %0					\n"	\
+	"	.hword	0x0001					\n"	\
+	"	.hword	%x1					\n"	\
+	"	.set	pop					\n"	\
+	:								\
+	: "r" (val), "i" (ins));					\
+})
+
+#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
+#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
+
+#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
+#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
+
+#define mflo0() _umips_dsp_mflo(0)
+#define mflo1() _umips_dsp_mflo(1)
+#define mflo2() _umips_dsp_mflo(2)
+#define mflo3() _umips_dsp_mflo(3)
+
+#define mfhi0() _umips_dsp_mfhi(0)
+#define mfhi1() _umips_dsp_mfhi(1)
+#define mfhi2() _umips_dsp_mfhi(2)
+#define mfhi3() _umips_dsp_mfhi(3)
+
+#define mtlo0(x) _umips_dsp_mtlo(x, 0)
+#define mtlo1(x) _umips_dsp_mtlo(x, 1)
+#define mtlo2(x) _umips_dsp_mtlo(x, 2)
+#define mtlo3(x) _umips_dsp_mtlo(x, 3)
+
+#define mthi0(x) _umips_dsp_mthi(x, 0)
+#define mthi1(x) _umips_dsp_mthi(x, 1)
+#define mthi2(x) _umips_dsp_mthi(x, 2)
+#define mthi3(x) _umips_dsp_mthi(x, 3)
+
+#else  /* !CONFIG_CPU_MICROMIPS */
+#define rddsp(mask)							\
+({									\
+	unsigned int __res;						\
+									\
+	__asm__ __volatile__(						\
+	"	.set	push				\n"		\
+	"	.set	noat				\n"		\
+	"	# rddsp $1, %x1				\n"		\
+	"	.word	0x7c000cb8 | (%x1 << 16)	\n"		\
+	"	move	%0, $1				\n"		\
+	"	.set	pop				\n"		\
+	: "=r" (__res)							\
+	: "i" (mask));							\
+	__res;								\
+})
+
+#define wrdsp(val, mask)						\
+({									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noat					\n"	\
+	"	move	$1, %0					\n"	\
+	"	# wrdsp $1, %x1					\n"	\
+	"	.word	0x7c2004f8 | (%x1 << 11)		\n"	\
+	"	.set	pop					\n"	\
+	:								\
+	: "r" (val), "i" (mask));					\
+})
+
+#define _dsp_mfxxx(ins)							\
+({									\
+	unsigned long __treg;						\
+									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noat					\n"	\
+	"	.word	(0x00000810 | %1)			\n"	\
+	"	move	%0, $1					\n"	\
+	"	.set	pop					\n"	\
+	: "=r" (__treg)							\
+	: "i" (ins));							\
+	__treg;								\
+})
+
+#define _dsp_mtxxx(val, ins)						\
+({									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noat					\n"	\
+	"	move	$1, %0					\n"	\
+	"	.word	(0x00200011 | %1)			\n"	\
+	"	.set	pop					\n"	\
+	:								\
+	: "r" (val), "i" (ins));					\
+})
+
+#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
+#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
+
+#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
+#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
+
+#define mflo0() _dsp_mflo(0)
+#define mflo1() _dsp_mflo(1)
+#define mflo2() _dsp_mflo(2)
+#define mflo3() _dsp_mflo(3)
+
+#define mfhi0() _dsp_mfhi(0)
+#define mfhi1() _dsp_mfhi(1)
+#define mfhi2() _dsp_mfhi(2)
+#define mfhi3() _dsp_mfhi(3)
+
+#define mtlo0(x) _dsp_mtlo(x, 0)
+#define mtlo1(x) _dsp_mtlo(x, 1)
+#define mtlo2(x) _dsp_mtlo(x, 2)
+#define mtlo3(x) _dsp_mtlo(x, 3)
+
+#define mthi0(x) _dsp_mthi(x, 0)
+#define mthi1(x) _dsp_mthi(x, 1)
+#define mthi2(x) _dsp_mthi(x, 2)
+#define mthi3(x) _dsp_mthi(x, 3)
+
+#endif /* CONFIG_CPU_MICROMIPS */
+#endif
+
+/*
+ * TLB operations.
+ *
+ * It is responsibility of the caller to take care of any TLB hazards.
+ */
+static inline void tlb_probe(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbp\n\t"
+		".set reorder");
+}
+
+static inline void tlb_read(void)
+{
+#if MIPS34K_MISSED_ITLB_WAR
+	int res = 0;
+
+	__asm__ __volatile__(
+	"	.set	push					\n"
+	"	.set	noreorder				\n"
+	"	.set	noat					\n"
+	"	.set	mips32r2				\n"
+	"	.word	0x41610001		# dvpe $1	\n"
+	"	move	%0, $1					\n"
+	"	ehb						\n"
+	"	.set	pop					\n"
+	: "=r" (res));
+
+	instruction_hazard();
+#endif
+
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbr\n\t"
+		".set reorder");
+
+#if MIPS34K_MISSED_ITLB_WAR
+	if ((res & _ULCAST_(1)))
+		__asm__ __volatile__(
+		"	.set	push				\n"
+		"	.set	noreorder			\n"
+		"	.set	noat				\n"
+		"	.set	mips32r2			\n"
+		"	.word	0x41600021	# evpe		\n"
+		"	ehb					\n"
+		"	.set	pop				\n");
+#endif
+}
+
+static inline void tlb_write_indexed(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbwi\n\t"
+		".set reorder");
+}
+
+static inline void tlb_write_random(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n\t"
+		"tlbwr\n\t"
+		".set reorder");
+}
+
+/*
+ * Manipulate bits in a c0 register.
+ */
+#define __BUILD_SET_C0(name)					\
+static inline unsigned int					\
+set_c0_##name(unsigned int set)					\
+{								\
+	unsigned int res, new;					\
+								\
+	res = read_c0_##name();					\
+	new = res | set;					\
+	write_c0_##name(new);					\
+								\
+	return res;						\
+}								\
+								\
+static inline unsigned int					\
+clear_c0_##name(unsigned int clear)				\
+{								\
+	unsigned int res, new;					\
+								\
+	res = read_c0_##name();					\
+	new = res & ~clear;					\
+	write_c0_##name(new);					\
+								\
+	return res;						\
+}								\
+								\
+static inline unsigned int					\
+change_c0_##name(unsigned int change, unsigned int val)		\
+{								\
+	unsigned int res, new;					\
+								\
+	res = read_c0_##name();					\
+	new = res & ~change;					\
+	new |= (val & change);					\
+	write_c0_##name(new);					\
+								\
+	return res;						\
+}
+
+__BUILD_SET_C0(status)
+__BUILD_SET_C0(cause)
+__BUILD_SET_C0(config)
+__BUILD_SET_C0(config5)
+__BUILD_SET_C0(intcontrol)
+__BUILD_SET_C0(intctl)
+__BUILD_SET_C0(srsmap)
+__BUILD_SET_C0(pagegrain)
+__BUILD_SET_C0(brcm_config_0)
+__BUILD_SET_C0(brcm_bus_pll)
+__BUILD_SET_C0(brcm_reset)
+__BUILD_SET_C0(brcm_cmt_intr)
+__BUILD_SET_C0(brcm_cmt_ctrl)
+__BUILD_SET_C0(brcm_config)
+__BUILD_SET_C0(brcm_mode)
+
+/*
+ * Return low 10 bits of ebase.
+ * Note that under KVM (MIPSVZ) this returns vcpu id.
+ */
+static inline unsigned int get_ebase_cpunum(void)
+{
+	return read_c0_ebase() & 0x3ff;
+}
+
+static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
+				 u32 low1)
+{
+	write_c0_entrylo0(low0);
+	write_c0_pagemask(pagemask);
+	write_c0_entrylo1(low1);
+	write_c0_entryhi(hi);
+	write_c0_index(index);
+	tlb_write_indexed();
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_MIPSREGS_H */
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
new file mode 100644
index 0000000..481d2ef
--- /dev/null
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -0,0 +1,282 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1994 - 2002 by Ralf Baechle
+ * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
+ */
+#ifndef _ASM_PGTABLE_BITS_H
+#define _ASM_PGTABLE_BITS_H
+
+
+/*
+ * Note that we shift the lower 32bits of each EntryLo[01] entry
+ * 6 bits to the left. That way we can convert the PFN into the
+ * physical address by a single 'and' operation and gain 6 additional
+ * bits for storing information which isn't present in a normal
+ * MIPS page table.
+ *
+ * Similar to the Alpha port, we need to keep track of the ref
+ * and mod bits in software.  We have a software "yeah you can read
+ * from this page" bit, and a hardware one which actually lets the
+ * process read from the page.	On the same token we have a software
+ * writable bit and the real hardware one which actually lets the
+ * process write to the page, this keeps a mod bit via the hardware
+ * dirty bit.
+ *
+ * Certain revisions of the R4000 and R5000 have a bug where if a
+ * certain sequence occurs in the last 3 instructions of an executable
+ * page, and the following page is not mapped, the cpu can do
+ * unpredictable things.  The code (when it is written) to deal with
+ * this problem will be in the update_mmu_cache() code for the r4k.
+ */
+#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
+
+/*
+ * The following bits are implemented by the TLB hardware
+ */
+#define _PAGE_NO_EXEC_SHIFT	0
+#define _PAGE_NO_EXEC		(1 << _PAGE_NO_EXEC_SHIFT)
+#define _PAGE_NO_READ_SHIFT	(_PAGE_NO_EXEC_SHIFT + 1)
+#define _PAGE_NO_READ		(1 << _PAGE_NO_READ_SHIFT)
+#define _PAGE_GLOBAL_SHIFT	(_PAGE_NO_READ_SHIFT + 1)
+#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)
+#define _PAGE_VALID_SHIFT	(_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT	(_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_SHIFT		(_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_MASK		(7 << _CACHE_SHIFT)
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT	(24)
+#define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)
+#define _PAGE_READ_SHIFT	(_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ		(1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT	(_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
+#define _PAGE_ACCESSED_SHIFT	(_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED		(1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT	(_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED		(1 << _PAGE_MODIFIED_SHIFT)
+
+#define _PFN_SHIFT		(PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
+
+/*
+ * Bits for extended EntryLo0/EntryLo1 registers
+ */
+#define _PFNX_MASK		0xffffff
+
+#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT	(0)
+#define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)
+#define _PAGE_READ_SHIFT	(_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ		(1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT	(_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
+#define _PAGE_ACCESSED_SHIFT	(_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED		(1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT	(_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED		(1 << _PAGE_MODIFIED_SHIFT)
+
+/*
+ * The following bits are implemented by the TLB hardware
+ */
+#define _PAGE_GLOBAL_SHIFT	(_PAGE_MODIFIED_SHIFT + 4)
+#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)
+#define _PAGE_VALID_SHIFT	(_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT	(_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_UNCACHED_SHIFT	(_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_UNCACHED		(1 << _CACHE_UNCACHED_SHIFT)
+#define _CACHE_MASK		_CACHE_UNCACHED
+
+#define _PFN_SHIFT		PAGE_SHIFT
+
+#else
+/*
+ * Below are the "Normal" R4K cases
+ */
+
+/*
+ * The following bits are implemented in software
+ */
+#define _PAGE_PRESENT_SHIFT	0
+#define _PAGE_PRESENT		(1 << _PAGE_PRESENT_SHIFT)
+/* R2 or later cores check for RI/XI support to determine _PAGE_READ */
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+#define _PAGE_WRITE_SHIFT	(_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
+#else
+#define _PAGE_READ_SHIFT	(_PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ		(1 << _PAGE_READ_SHIFT)
+#define _PAGE_WRITE_SHIFT	(_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
+#endif
+#define _PAGE_ACCESSED_SHIFT	(_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED		(1 << _PAGE_ACCESSED_SHIFT)
+#define _PAGE_MODIFIED_SHIFT	(_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED		(1 << _PAGE_MODIFIED_SHIFT)
+
+#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
+/* Huge TLB page */
+#define _PAGE_HUGE_SHIFT	(_PAGE_MODIFIED_SHIFT + 1)
+#define _PAGE_HUGE		(1 << _PAGE_HUGE_SHIFT)
+#define _PAGE_SPLITTING_SHIFT	(_PAGE_HUGE_SHIFT + 1)
+#define _PAGE_SPLITTING		(1 << _PAGE_SPLITTING_SHIFT)
+#endif	/* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
+
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+/* XI - page cannot be executed */
+#ifdef _PAGE_SPLITTING_SHIFT
+#define _PAGE_NO_EXEC_SHIFT	(_PAGE_SPLITTING_SHIFT + 1)
+#else
+#define _PAGE_NO_EXEC_SHIFT	(_PAGE_MODIFIED_SHIFT + 1)
+#endif
+#define _PAGE_NO_EXEC		(cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
+
+/* RI - page cannot be read */
+#define _PAGE_READ_SHIFT	(_PAGE_NO_EXEC_SHIFT + 1)
+#define _PAGE_READ		(cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
+#define _PAGE_NO_READ_SHIFT	_PAGE_READ_SHIFT
+#define _PAGE_NO_READ		(cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
+#endif	/* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */
+
+#if defined(_PAGE_NO_READ_SHIFT)
+#define _PAGE_GLOBAL_SHIFT	(_PAGE_NO_READ_SHIFT + 1)
+#elif defined(_PAGE_SPLITTING_SHIFT)
+#define _PAGE_GLOBAL_SHIFT	(_PAGE_SPLITTING_SHIFT + 1)
+#else
+#define _PAGE_GLOBAL_SHIFT	(_PAGE_MODIFIED_SHIFT + 1)
+#endif
+#define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)
+
+#define _PAGE_VALID_SHIFT	(_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
+#define _PAGE_DIRTY_SHIFT	(_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)
+#define _CACHE_SHIFT		(_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_MASK		(7 << _CACHE_SHIFT)
+
+#define _PFN_SHIFT		(PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
+
+#endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
+
+#ifndef _PAGE_NO_EXEC
+#define _PAGE_NO_EXEC		0
+#endif
+#ifndef _PAGE_NO_READ
+#define _PAGE_NO_READ		0
+#endif
+
+#define _PAGE_SILENT_READ	_PAGE_VALID
+#define _PAGE_SILENT_WRITE	_PAGE_DIRTY
+
+#define _PFN_MASK		(~((1 << (_PFN_SHIFT)) - 1))
+
+/*
+ * The final layouts of the PTE bits are:
+ *
+ *   64-bit, R1 or earlier:     CCC D V G [S H] M A W R P
+ *   32-bit, R1 or earler:      CCC D V G M A W R P
+ *   64-bit, R2 or later:       CCC D V G RI/R XI [S H] M A W P
+ *   32-bit, R2 or later:       CCC D V G RI/R XI M A W P
+ */
+
+
+#ifndef __ASSEMBLY__
+/*
+ * pte_to_entrylo converts a page table entry (PTE) into a Mips
+ * entrylo0/1 value.
+ */
+static inline uint64_t pte_to_entrylo(unsigned long pte_val)
+{
+#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+	if (cpu_has_rixi) {
+		int sa;
+#ifdef CONFIG_32BIT
+		sa = 31 - _PAGE_NO_READ_SHIFT;
+#else
+		sa = 63 - _PAGE_NO_READ_SHIFT;
+#endif
+		/*
+		 * C has no way to express that this is a DSRL
+		 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2.  Luckily
+		 * in the fast path this is done in assembly
+		 */
+		return (pte_val >> _PAGE_GLOBAL_SHIFT) |
+			((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
+	}
+#endif
+
+	return pte_val >> _PAGE_GLOBAL_SHIFT;
+}
+#endif
+
+/*
+ * Cache attributes
+ */
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+
+#define _CACHE_CACHABLE_NONCOHERENT 0
+#define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
+
+#elif defined(CONFIG_CPU_SB1)
+
+/* No penalty for being coherent on the SB1, so just
+   use it for "noncoherent" spaces, too.  Shouldn't hurt. */
+
+#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
+
+#elif defined(CONFIG_CPU_LOONGSON3)
+
+/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
+
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
+#define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
+
+#elif defined(CONFIG_MACH_INGENIC)
+
+/* Ingenic uses the WA bit to achieve write-combine memory writes */
+#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
+
+#endif
+
+#ifndef _CACHE_CACHABLE_NO_WA
+#define _CACHE_CACHABLE_NO_WA		(0<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_WA
+#define _CACHE_CACHABLE_WA		(1<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED
+#define _CACHE_UNCACHED			(2<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_NONCOHERENT
+#define _CACHE_CACHABLE_NONCOHERENT	(3<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CE
+#define _CACHE_CACHABLE_CE		(4<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_COW
+#define _CACHE_CACHABLE_COW		(5<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_CACHABLE_CUW
+#define _CACHE_CACHABLE_CUW		(6<<_CACHE_SHIFT)
+#endif
+#ifndef _CACHE_UNCACHED_ACCELERATED
+#define _CACHE_UNCACHED_ACCELERATED	(7<<_CACHE_SHIFT)
+#endif
+
+#define __READABLE	(_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
+#define __WRITEABLE	(_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
+
+#define _PAGE_CHG_MASK	(_PAGE_ACCESSED | _PAGE_MODIFIED |	\
+			 _PFN_MASK | _CACHE_MASK)
+
+#endif /* _ASM_PGTABLE_BITS_H */
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
new file mode 100644
index 0000000..ec5d338
--- /dev/null
+++ b/arch/mips/include/asm/posix_types.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1996, 1997, 1998, 2000 by Ralf Baechle
+ */
+#ifndef _ASM_POSIX_TYPES_H
+#define _ASM_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned int	__kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned int	__kernel_mode_t;
+typedef int		__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef int		__kernel_ipc_pid_t;
+typedef int		__kernel_uid_t;
+typedef int		__kernel_gid_t;
+#if _MIPS_SZLONG != 64
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+#else
+typedef unsigned long	__kernel_size_t;
+typedef long		__kernel_ssize_t;
+typedef long		__kernel_ptrdiff_t;
+#endif
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef long		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef int		__kernel_uid32_t;
+typedef int		__kernel_gid32_t;
+typedef __kernel_uid_t	__kernel_old_uid_t;
+typedef __kernel_gid_t	__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long      __kernel_loff_t;
+#endif
+
+typedef struct {
+	long    val[2];
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+	unsigned long *__tmp = __p->fds_bits;
+	int __i;
+
+	if (__builtin_constant_p(__FDSET_LONGS)) {
+		switch (__FDSET_LONGS) {
+		case 16:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			__tmp[ 8] = 0; __tmp[ 9] = 0;
+			__tmp[10] = 0; __tmp[11] = 0;
+			__tmp[12] = 0; __tmp[13] = 0;
+			__tmp[14] = 0; __tmp[15] = 0;
+			return;
+
+		case 8:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			return;
+
+		case 4:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			return;
+		}
+	}
+	__i = __FDSET_LONGS;
+	while (__i) {
+		__i--;
+		*__tmp = 0;
+		__tmp++;
+	}
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* _ASM_POSIX_TYPES_H */
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
new file mode 100644
index 0000000..39a4f43
--- /dev/null
+++ b/arch/mips/include/asm/processor.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PROCESSOR_H
+#define _ASM_PROCESSOR_H
+
+#include <asm/isadep.h>
+
+#include <asm/cachectl.h>
+#include <asm/mipsregs.h>
+#include <asm/reg.h>
+#include <asm/system.h>
+
+/*
+ * Return current * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+/*
+ * System setup and hardware flags..
+ */
+extern void (*cpu_wait)(void);
+
+extern unsigned int vced_count, vcei_count;
+
+#define NUM_FPU_REGS	32
+
+typedef __u64 fpureg_t;
+
+/*
+ * It would be nice to add some more fields for emulator statistics, but there
+ * are a number of fixed offsets in offset.h and elsewhere that would have to
+ * be recalculated by hand.  So the additional information will be private to
+ * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
+ */
+
+struct mips_fpu_struct {
+	fpureg_t	fpr[NUM_FPU_REGS];
+	unsigned int	fcr31;
+};
+
+#define NUM_DSP_REGS   6
+
+typedef __u32 dspreg_t;
+
+struct mips_dsp_state {
+	dspreg_t        dspr[NUM_DSP_REGS];
+	unsigned int    dspcontrol;
+};
+
+typedef struct {
+	unsigned long seg;
+} mm_segment_t;
+
+#define ARCH_MIN_TASKALIGN	8
+
+struct mips_abi;
+
+/*
+ * If you change thread_struct remember to change the #defines below too!
+ */
+struct thread_struct {
+	/* Saved main processor registers. */
+	unsigned long reg16;
+	unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
+	unsigned long reg29, reg30, reg31;
+
+	/* Saved cp0 stuff. */
+	unsigned long cp0_status;
+
+	/* Saved fpu/fpu emulator stuff. */
+	struct mips_fpu_struct fpu;
+#ifdef CONFIG_MIPS_MT_FPAFF
+	/* Emulated instruction count */
+	unsigned long emulated_fp;
+	/* Saved per-thread scheduler affinity mask */
+	cpumask_t user_cpus_allowed;
+#endif /* CONFIG_MIPS_MT_FPAFF */
+
+	/* Saved state of the DSP ASE, if available. */
+	struct mips_dsp_state dsp;
+
+	/* Other stuff associated with the thread. */
+	unsigned long cp0_badvaddr;	/* Last user fault */
+	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
+	unsigned long error_code;
+	unsigned long trap_no;
+	unsigned long irix_trampoline;  /* Wheee... */
+	unsigned long irix_oldctx;
+	struct mips_abi *abi;
+};
+
+struct task_struct;
+
+/* Free all resources held by a thread. */
+#define release_thread(thread) do { } while(0)
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)	do { } while (0)
+
+#define cpu_relax()	barrier()
+
+/*
+ * Return_address is a replacement for __builtin_return_address(count)
+ * which on certain architectures cannot reasonably be implemented in GCC
+ * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
+ * Note that __builtin_return_address(x>=1) is forbidden because GCC
+ * aborts compilation on some CPUs.  It's simply not possible to unwind
+ * some CPU's stackframes.
+ *
+ * __builtin_return_address works only for non-leaf functions.  We avoid the
+ * overhead of a function call by forcing the compiler to save the return
+ * address register on the stack.
+ */
+#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
+
+#ifdef CONFIG_CPU_HAS_PREFETCH
+
+#define ARCH_HAS_PREFETCH
+
+static inline void prefetch(const void *addr)
+{
+	__asm__ __volatile__(
+	"	.set	mips4		\n"
+	"	pref	%0, (%1)	\n"
+	"	.set	mips0		\n"
+	:
+	: "i" (Pref_Load), "r" (addr));
+}
+
+#endif
+
+#endif /* _ASM_PROCESSOR_H */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
new file mode 100644
index 0000000..cb88d6d
--- /dev/null
+++ b/arch/mips/include/asm/ptrace.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PTRACE_H
+#define _ASM_PTRACE_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/isadep.h>
+
+/*
+ * This struct defines the way the registers are stored on the stack during a
+ * system call/exception. As usual the registers k0/k1 aren't being saved.
+ *
+ * If you add a register here, also add it to regoffset_table[] in
+ * arch/mips/kernel/ptrace.c.
+ */
+struct pt_regs {
+#ifdef CONFIG_32BIT
+	/* Pad bytes for argument save space on the stack. */
+	unsigned long pad0[8];
+#endif
+
+	/* Saved main processor registers. */
+	unsigned long regs[32];
+
+	/* Saved special registers. */
+	unsigned long cp0_status;
+	unsigned long hi;
+	unsigned long lo;
+#ifdef CONFIG_CPU_HAS_SMARTMIPS
+	unsigned long acx;
+#endif
+	unsigned long cp0_badvaddr;
+	unsigned long cp0_cause;
+	unsigned long cp0_epc;
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+	unsigned long long mpl[6];        /* MTM{0-5} */
+	unsigned long long mtp[6];        /* MTP{0-5} */
+#endif
+	unsigned long __last[0];
+} __aligned(8);
+
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+	return regs->regs[31];
+}
+
+/*
+ * Don't use asm-generic/ptrace.h it defines FP accessors that don't make
+ * sense on MIPS.  We rather want an error if they get invoked.
+ */
+
+static inline void instruction_pointer_set(struct pt_regs *regs,
+						unsigned long val)
+{
+	regs->cp0_epc = val;
+}
+
+/* Query offset/name of register from its name/offset */
+extern int regs_query_register_offset(const char *name);
+#define MAX_REG_OFFSET (offsetof(struct pt_regs, __last))
+
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs:       pt_regs from which register value is gotten.
+ * @offset:     offset number of the register.
+ *
+ * regs_get_register returns the value of a register. The @offset is the
+ * offset of the register in struct pt_regs address which specified by @regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+						unsigned int offset)
+{
+	if (unlikely(offset > MAX_REG_OFFSET))
+		return 0;
+
+	return *(unsigned long *)((unsigned long)regs + offset);
+}
+
+/*
+ * Does the process account for user or for system time?
+ */
+#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
+
+#define instruction_pointer(regs) ((regs)->cp0_epc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+/* Helpers for working with the user stack pointer */
+
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+	return regs->regs[29];
+}
+
+static inline void user_stack_pointer_set(struct pt_regs *regs,
+						unsigned long val)
+{
+	regs->regs[29] = val;
+}
+
+#endif /* _ASM_PTRACE_H */
diff --git a/arch/mips/include/asm/reboot.h b/arch/mips/include/asm/reboot.h
new file mode 100644
index 0000000..e75adcf
--- /dev/null
+++ b/arch/mips/include/asm/reboot.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_REBOOT_H
+#define _ASM_REBOOT_H
+
+extern void _machine_restart(void);
+
+#endif /* _ASM_REBOOT_H */
diff --git a/arch/mips/include/asm/reg.h b/arch/mips/include/asm/reg.h
new file mode 100644
index 0000000..3ae5619
--- /dev/null
+++ b/arch/mips/include/asm/reg.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Various register offset definitions for debuggers, core file
+ * examiners and whatnot.
+ *
+ * Copyright (C) 1995, 1999 by Ralf Baechle
+ * Copyright (C) 1995, 1999 Silicon Graphics
+ */
+#ifndef __ASM_MIPS_REG_H
+#define __ASM_MIPS_REG_H
+
+#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
+
+#define EF_R0			6
+#define EF_R1			7
+#define EF_R2			8
+#define EF_R3			9
+#define EF_R4			10
+#define EF_R5			11
+#define EF_R6			12
+#define EF_R7			13
+#define EF_R8			14
+#define EF_R9			15
+#define EF_R10			16
+#define EF_R11			17
+#define EF_R12			18
+#define EF_R13			19
+#define EF_R14			20
+#define EF_R15			21
+#define EF_R16			22
+#define EF_R17			23
+#define EF_R18			24
+#define EF_R19			25
+#define EF_R20			26
+#define EF_R21			27
+#define EF_R22			28
+#define EF_R23			29
+#define EF_R24			30
+#define EF_R25			31
+
+/*
+ * k0/k1 unsaved
+ */
+#define EF_R26			32
+#define EF_R27			33
+
+#define EF_R28			34
+#define EF_R29			35
+#define EF_R30			36
+#define EF_R31			37
+
+/*
+ * Saved special registers
+ */
+#define EF_LO			38
+#define EF_HI			39
+
+#define EF_CP0_EPC		40
+#define EF_CP0_BADVADDR		41
+#define EF_CP0_STATUS		42
+#define EF_CP0_CAUSE		43
+#define EF_UNUSED0		44
+
+#define EF_SIZE			180
+
+#endif
+
+#ifdef CONFIG_64BIT
+
+#define EF_R0			 0
+#define EF_R1			 1
+#define EF_R2			 2
+#define EF_R3			 3
+#define EF_R4			 4
+#define EF_R5			 5
+#define EF_R6			 6
+#define EF_R7			 7
+#define EF_R8			 8
+#define EF_R9			 9
+#define EF_R10			10
+#define EF_R11			11
+#define EF_R12			12
+#define EF_R13			13
+#define EF_R14			14
+#define EF_R15			15
+#define EF_R16			16
+#define EF_R17			17
+#define EF_R18			18
+#define EF_R19			19
+#define EF_R20			20
+#define EF_R21			21
+#define EF_R22			22
+#define EF_R23			23
+#define EF_R24			24
+#define EF_R25			25
+
+/*
+ * k0/k1 unsaved
+ */
+#define EF_R26			26
+#define EF_R27			27
+
+#define EF_R28			28
+#define EF_R29			29
+#define EF_R30			30
+#define EF_R31			31
+
+/*
+ * Saved special registers
+ */
+#define EF_LO			32
+#define EF_HI			33
+
+#define EF_CP0_EPC		34
+#define EF_CP0_BADVADDR		35
+#define EF_CP0_STATUS		36
+#define EF_CP0_CAUSE		37
+
+#define EF_SIZE			304	/* size in bytes */
+
+#endif /* CONFIG_64BIT */
+
+#endif /* __ASM_MIPS_REG_H */
diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
new file mode 100644
index 0000000..e713749
--- /dev/null
+++ b/arch/mips/include/asm/regdef.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1985 MIPS Computer Systems, Inc.
+ * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2011 Wind River Systems,
+ *   written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef _ASM_REGDEF_H
+#define _ASM_REGDEF_H
+
+#include <asm/sgidefs.h>
+
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+
+/*
+ * Symbolic register names for 32 bit ABI
+ */
+#define zero	$0	/* wired zero */
+#define AT	$1	/* assembler temp  - uppercase because of ".set at" */
+#define v0	$2	/* return value */
+#define v1	$3
+#define a0	$4	/* argument registers */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8	/* caller saved */
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define ta0	$12
+#define t5	$13
+#define ta1	$13
+#define t6	$14
+#define ta2	$14
+#define t7	$15
+#define ta3	$15
+#define s0	$16	/* callee saved */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24	/* caller saved */
+#define t9	$25
+#define jp	$25	/* PIC jump register */
+#define k0	$26	/* kernel scratch */
+#define k1	$27
+#define gp	$28	/* global pointer */
+#define sp	$29	/* stack pointer */
+#define fp	$30	/* frame pointer */
+#define s8	$30	/* same like fp! */
+#define ra	$31	/* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
+
+#define zero	$0	/* wired zero */
+#define AT	$at	/* assembler temp - uppercase because of ".set at" */
+#define v0	$2	/* return value - caller saved */
+#define v1	$3
+#define a0	$4	/* argument registers */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define a4	$8	/* arg reg 64 bit; caller saved in 32 bit */
+#define ta0	$8
+#define a5	$9
+#define ta1	$9
+#define a6	$10
+#define ta2	$10
+#define a7	$11
+#define ta3	$11
+#define t0	$12	/* caller saved */
+#define t1	$13
+#define t2	$14
+#define t3	$15
+#define s0	$16	/* callee saved */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24	/* caller saved */
+#define t9	$25	/* callee address for PIC/temp */
+#define jp	$25	/* PIC jump register */
+#define k0	$26	/* kernel temporary */
+#define k1	$27
+#define gp	$28	/* global pointer - caller saved for PIC */
+#define sp	$29	/* stack pointer */
+#define fp	$30	/* frame pointer */
+#define s8	$30	/* callee saved */
+#define ra	$31	/* return address */
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
+
+#endif /* _ASM_REGDEF_H */
diff --git a/arch/mips/include/asm/relocs.h b/arch/mips/include/asm/relocs.h
new file mode 100644
index 0000000..0987c4b
--- /dev/null
+++ b/arch/mips/include/asm/relocs.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MIPS Relocations
+ *
+ * Copyright (c) 2017 Imagination Technologies Ltd.
+ */
+
+#ifndef __ASM_MIPS_RELOCS_H__
+#define __ASM_MIPS_RELOCS_H__
+
+#define R_MIPS_NONE		0
+#define R_MIPS_32		2
+#define R_MIPS_26		4
+#define R_MIPS_HI16		5
+#define R_MIPS_LO16		6
+#define R_MIPS_PC16		10
+#define R_MIPS_64		18
+#define R_MIPS_HIGHER		28
+#define R_MIPS_HIGHEST		29
+#define R_MIPS_PC21_S2		60
+#define R_MIPS_PC26_S2		61
+
+#endif /* __ASM_MIPS_RELOCS_H__ */
diff --git a/arch/mips/include/asm/sections.h b/arch/mips/include/asm/sections.h
new file mode 100644
index 0000000..93c30e9
--- /dev/null
+++ b/arch/mips/include/asm/sections.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_MIPS_SECTIONS_H
+#define __ASM_MIPS_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+/**
+ * __rel_start: Relocation data generated by the mips-relocs tool
+ *
+ * See arch/mips/lib/reloc.c for details on the format & use of this data.
+ */
+extern uint8_t __rel_start[];
+
+#endif
diff --git a/arch/mips/include/asm/sgidefs.h b/arch/mips/include/asm/sgidefs.h
new file mode 100644
index 0000000..1c7a6c2
--- /dev/null
+++ b/arch/mips/include/asm/sgidefs.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1996, 1999, 2001 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef __ASM_SGIDEFS_H
+#define __ASM_SGIDEFS_H
+
+/*
+ * Using a Linux compiler for building Linux seems logic but not to
+ * everybody.
+ */
+#if 0 /* ndef __linux__ */
+#error Use a Linux compiler or give up.
+#endif
+
+/*
+ * Definitions for the ISA levels
+ *
+ * With the introduction of MIPS32 / MIPS64 instruction sets definitions
+ * MIPS ISAs are no longer subsets of each other.  Therefore comparisons
+ * on these symbols except with == may result in unexpected results and
+ * are forbidden!
+ */
+#define _MIPS_ISA_MIPS1		1
+#define _MIPS_ISA_MIPS2		2
+#define _MIPS_ISA_MIPS3		3
+#define _MIPS_ISA_MIPS4		4
+#define _MIPS_ISA_MIPS5		5
+#define _MIPS_ISA_MIPS32	6
+#define _MIPS_ISA_MIPS64	7
+
+/*
+ * Subprogram calling convention
+ */
+#define _MIPS_SIM_ABI32		1
+#define _MIPS_SIM_NABI32	2
+#define _MIPS_SIM_ABI64		3
+
+#endif /* __ASM_SGIDEFS_H */
diff --git a/arch/mips/include/asm/spl.h b/arch/mips/include/asm/spl.h
new file mode 100644
index 0000000..0a847ed
--- /dev/null
+++ b/arch/mips/include/asm/spl.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef	_ASM_SPL_H_
+#define	_ASM_SPL_H_
+
+enum {
+	BOOT_DEVICE_RAM,
+	BOOT_DEVICE_MMC1,
+	BOOT_DEVICE_MMC2,
+	BOOT_DEVICE_MMC2_2,
+	BOOT_DEVICE_NAND,
+	BOOT_DEVICE_ONENAND,
+	BOOT_DEVICE_NOR,
+	BOOT_DEVICE_UART,
+	BOOT_DEVICE_SPI,
+	BOOT_DEVICE_USB,
+	BOOT_DEVICE_SATA,
+	BOOT_DEVICE_I2C,
+	BOOT_DEVICE_BOARD,
+	BOOT_DEVICE_DFU,
+	BOOT_DEVICE_XIP,
+	BOOT_DEVICE_BOOTROM,
+	BOOT_DEVICE_NONE
+};
+
+#ifndef CONFIG_DM
+extern gd_t gdata;
+#endif
+
+#endif
diff --git a/arch/mips/include/asm/string.h b/arch/mips/include/asm/string.h
new file mode 100644
index 0000000..faceaf9
--- /dev/null
+++ b/arch/mips/include/asm/string.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
+ * Copyright (c) 2000 by Silicon Graphics, Inc.
+ * Copyright (c) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_STRING_H
+#define _ASM_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRCPY
+extern char *strcpy(char *__dest, __const__ char *__src);
+
+#undef __HAVE_ARCH_STRNCPY
+extern char *strncpy(char *__dest, __const__ char *__src, __kernel_size_t __n);
+
+#undef __HAVE_ARCH_STRCMP
+extern int strcmp(__const__ char *__cs, __const__ char *__ct);
+
+#undef __HAVE_ARCH_STRNCMP
+extern int strncmp(__const__ char *__cs, __const__ char *__ct, __kernel_size_t __count);
+
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, __kernel_size_t __count);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, __kernel_size_t __n);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, __kernel_size_t __n);
+
+#endif /* _ASM_STRING_H */
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
new file mode 100644
index 0000000..79e6388
--- /dev/null
+++ b/arch/mips/include/asm/system.h
@@ -0,0 +1,285 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1994 - 1999 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1994 - 1999 by Ralf Baechle
+ *
+ * Changed set_except_vector declaration to allow return of previous
+ * vector address value - necessary for "borrowing" vectors.
+ *
+ * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_SYSTEM_H
+#define _ASM_SYSTEM_H
+
+#include <asm/asm.h>
+#include <asm/sgidefs.h>
+#include <asm/ptrace.h>
+#include <linux/stringify.h>
+#if 0
+#include <linux/kernel.h>
+#endif
+
+static __inline__ void
+__sti(void)
+{
+	__asm__ __volatile__(
+		".set\tpush\n\t"
+		".set\treorder\n\t"
+		".set\tnoat\n\t"
+		"mfc0\t$1,$12\n\t"
+		"ori\t$1,0x1f\n\t"
+		"xori\t$1,0x1e\n\t"
+		"mtc0\t$1,$12\n\t"
+		".set\tpop\n\t"
+		: /* no outputs */
+		: /* no inputs */
+		: "$1", "memory");
+}
+
+/*
+ * For cli() we have to insert nops to make shure that the new value
+ * has actually arrived in the status register before the end of this
+ * macro.
+ * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
+ * no nops at all.
+ */
+static __inline__ void
+__cli(void)
+{
+	__asm__ __volatile__(
+		".set\tpush\n\t"
+		".set\treorder\n\t"
+		".set\tnoat\n\t"
+		"mfc0\t$1,$12\n\t"
+		"ori\t$1,1\n\t"
+		"xori\t$1,1\n\t"
+		".set\tnoreorder\n\t"
+		"mtc0\t$1,$12\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		"nop\n\t"
+		".set\tpop\n\t"
+		: /* no outputs */
+		: /* no inputs */
+		: "$1", "memory");
+}
+
+#define __save_flags(x)							\
+__asm__ __volatile__(							\
+	".set\tpush\n\t"						\
+	".set\treorder\n\t"						\
+	"mfc0\t%0,$12\n\t"						\
+	".set\tpop\n\t"							\
+	: "=r" (x))
+
+#define __save_and_cli(x)						\
+__asm__ __volatile__(							\
+	".set\tpush\n\t"						\
+	".set\treorder\n\t"						\
+	".set\tnoat\n\t"						\
+	"mfc0\t%0,$12\n\t"						\
+	"ori\t$1,%0,1\n\t"						\
+	"xori\t$1,1\n\t"						\
+	".set\tnoreorder\n\t"						\
+	"mtc0\t$1,$12\n\t"						\
+	"nop\n\t"							\
+	"nop\n\t"							\
+	"nop\n\t"							\
+	".set\tpop\n\t"							\
+	: "=r" (x)							\
+	: /* no inputs */						\
+	: "$1", "memory")
+
+#define __restore_flags(flags)						\
+do {									\
+	unsigned long __tmp1;						\
+									\
+	__asm__ __volatile__(						\
+		".set\tnoreorder\t\t\t# __restore_flags\n\t"		\
+		".set\tnoat\n\t"					\
+		"mfc0\t$1, $12\n\t"					\
+		"andi\t%0, 1\n\t"					\
+		"ori\t$1, 1\n\t"					\
+		"xori\t$1, 1\n\t"					\
+		"or\t%0, $1\n\t"					\
+		"mtc0\t%0, $12\n\t"					\
+		"nop\n\t"						\
+		"nop\n\t"						\
+		"nop\n\t"						\
+		".set\tat\n\t"						\
+		".set\treorder"						\
+		: "=r" (__tmp1)						\
+		: "0" (flags)						\
+		: "$1", "memory");					\
+} while(0)
+
+#ifdef CONFIG_SMP
+
+extern void __global_sti(void);
+extern void __global_cli(void);
+extern unsigned long __global_save_flags(void);
+extern void __global_restore_flags(unsigned long);
+#  define sti() __global_sti()
+#  define cli() __global_cli()
+#  define save_flags(x) do { x = __global_save_flags(); } while (0)
+#  define restore_flags(x) __global_restore_flags(x)
+#  define save_and_cli(x) do { save_flags(x); cli(); } while(0)
+
+#else /* Single processor */
+
+#  define sti() __sti()
+#  define cli() __cli()
+#  define save_flags(x) __save_flags(x)
+#  define save_and_cli(x) __save_and_cli(x)
+#  define restore_flags(x) __restore_flags(x)
+
+#endif /* SMP */
+
+/* For spinlocks etc */
+#define local_irq_save(x)	__save_and_cli(x);
+#define local_irq_restore(x)	__restore_flags(x);
+#define local_irq_disable()	__cli();
+#define local_irq_enable()	__sti();
+
+/*
+ * These are probably defined overly paranoid ...
+ */
+#ifdef CONFIG_CPU_HAS_WB
+
+#include <asm/wbflush.h>
+#define rmb()	do { } while(0)
+#define wmb()	wbflush()
+#define mb()	wbflush()
+
+#else /* CONFIG_CPU_HAS_WB  */
+
+#define mb()						\
+__asm__ __volatile__(					\
+	"# prevent instructions being moved around\n\t"	\
+	".set\tnoreorder\n\t"				\
+	"# 8 nops to fool the R4400 pipeline\n\t"	\
+	"nop;nop;nop;nop;nop;nop;nop;nop\n\t"		\
+	".set\treorder"					\
+	: /* no output */				\
+	: /* no input */				\
+	: "memory")
+#define rmb() mb()
+#define wmb() mb()
+
+#endif /* CONFIG_CPU_HAS_WB  */
+
+#ifdef CONFIG_SMP
+#define smp_mb()	mb()
+#define smp_rmb()	rmb()
+#define smp_wmb()	wmb()
+#else
+#define smp_mb()	barrier()
+#define smp_rmb()	barrier()
+#define smp_wmb()	barrier()
+#endif
+
+#define set_mb(var, value) \
+do { var = value; mb(); } while (0)
+
+#define set_wmb(var, value) \
+do { var = value; wmb(); } while (0)
+
+#if !defined (_LANGUAGE_ASSEMBLY)
+/*
+ * switch_to(n) should switch tasks to task nr n, first
+ * checking that n isn't the current task, in which case it does nothing.
+ */
+#if 0
+extern asmlinkage void *resume(void *last, void *next);
+#endif
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
+
+#define prepare_to_switch()	do { } while(0)
+#define switch_to(prev,next,last) \
+do { \
+	(last) = resume(prev, next); \
+} while(0)
+
+/*
+ * For 32 and 64 bit operands we can take advantage of ll and sc.
+ * FIXME: This doesn't work for R3000 machines.
+ */
+static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
+{
+#ifdef CONFIG_CPU_HAS_LLSC
+	unsigned long dummy;
+
+	__asm__ __volatile__(
+		".set\tnoreorder\t\t\t# xchg_u32\n\t"
+		".set\tnoat\n\t"
+		"ll\t%0, %3\n"
+		"1:\tmove\t$1, %2\n\t"
+		"sc\t$1, %1\n\t"
+		"beqzl\t$1, 1b\n\t"
+		" ll\t%0, %3\n\t"
+		".set\tat\n\t"
+		".set\treorder"
+		: "=r" (val), "=o" (*m), "=r" (dummy)
+		: "o" (*m), "2" (val)
+		: "memory");
+
+	return val;
+#else
+	unsigned long flags, retval;
+
+	save_flags(flags);
+	cli();
+	retval = *m;
+	*m = val;
+	restore_flags(flags);
+	return retval;
+#endif /* Processor-dependent optimization */
+}
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+#define tas(ptr) (xchg((ptr),1))
+
+static __inline__ unsigned long
+__xchg(unsigned long x, volatile void * ptr, int size)
+{
+	switch (size) {
+		case 4:
+			return xchg_u32(ptr, x);
+	}
+	return x;
+}
+
+extern void *set_except_vector(int n, void *addr);
+
+extern void __die(const char *, struct pt_regs *, const char *where,
+	unsigned long line) __attribute__((noreturn));
+extern void __die_if_kernel(const char *, struct pt_regs *, const char *where,
+	unsigned long line);
+
+#define die(msg, regs)							\
+	__die(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
+#define die_if_kernel(msg, regs)					\
+	__die_if_kernel(msg, regs, __FILE__ ":"__FUNCTION__, __LINE__)
+
+static inline void execution_hazard_barrier(void)
+{
+	__asm__ __volatile__(
+		".set noreorder\n"
+		"ehb\n"
+		".set reorder");
+}
+
+static inline void instruction_hazard_barrier(void)
+{
+	unsigned long tmp;
+
+	asm volatile(
+	__stringify(PTR_LA) "\t%0, 1f\n"
+	"	jr.hb	%0\n"
+	"1:	.insn"
+	: "=&r"(tmp));
+}
+
+#endif /* _ASM_SYSTEM_H */
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
new file mode 100644
index 0000000..925d7ef
--- /dev/null
+++ b/arch/mips/include/asm/types.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_TYPES_H
+#define _ASM_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG _MIPS_SZLONG
+
+#ifndef __ASSEMBLY__
+
+#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
+    || defined(CONFIG_64BIT)
+typedef u64 dma_addr_t;
+
+typedef u64 phys_addr_t;
+typedef u64 phys_size_t;
+
+#else
+typedef u32 dma_addr_t;
+
+typedef u32 phys_addr_t;
+typedef u32 phys_size_t;
+
+#endif
+typedef u64 dma64_addr_t;
+
+/*
+ * Don't use phys_t.  You've been warned.
+ */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+typedef unsigned long long phys_t;
+#else
+typedef unsigned long phys_t;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_TYPES_H */
diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h
new file mode 100644
index 0000000..88438b9
--- /dev/null
+++ b/arch/mips/include/asm/u-boot-mips.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _U_BOOT_MIPS_H_
+#define _U_BOOT_MIPS_H_
+
+void exc_handler(void);
+void except_vec3_generic(void);
+void except_vec_ejtag_debug(void);
+
+int arch_misc_init(void);
+
+#endif /* _U_BOOT_MIPS_H_ */
diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h
new file mode 100644
index 0000000..4a9bbaf
--- /dev/null
+++ b/arch/mips/include/asm/u-boot.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#include <asm/u-boot-mips.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_MIPS
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h
new file mode 100644
index 0000000..debb9cf
--- /dev/null
+++ b/arch/mips/include/asm/unaligned.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef _ASM_MIPS_UNALIGNED_H
+#define _ASM_MIPS_UNALIGNED_H
+
+#include <linux/compiler.h>
+#if defined(__MIPSEB__)
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+#elif defined(__MIPSEL__)
+#define get_unaligned	__get_unaligned_le
+#define put_unaligned	__put_unaligned_le
+#else
+#error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
+#endif
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+#endif /* _ASM_MIPS_UNALIGNED_H */
diff --git a/arch/nds32/include/asm/arch-ae3xx/ae3xx.h b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h
new file mode 100644
index 0000000..c283cfa
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#ifndef __AE3XX_H
+#define __AE3XX_H
+
+/* Hardware register bases */
+
+/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSMC020_BASE		0xe0400000
+/* DMA Controller */
+#define CONFIG_FTDMAC020_BASE		0xf0c00000
+/* AHB-to-APB Bridge */
+#define CONFIG_FTAPBBRG020S_01_BASE	0xf0000000
+/* Reserved */
+#define CONFIG_RESERVED_01_BASE		0xe0500000
+/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0xf0800000
+/* Reserved */
+#define CONFIG_RESERVED_03_BASE		0xf0900000
+/* Ethernet */
+#define CONFIG_FTMAC100_BASE		0xe0100000
+/* Reserved */
+#define CONFIG_RESERVED_04_BASE		0xf1000000
+
+/* APB Device definitions */
+
+/* UART1 */
+#define CONFIG_FTUART010_01_BASE	0xf0200000
+/* UART2 */
+#define CONFIG_FTUART010_02_BASE	0xf0300000
+/* Counter/Timers */
+#define CONFIG_FTTMR010_BASE		0xf0400000
+/* Watchdog Timer */
+#define CONFIG_FTWDT010_BASE		0xf0500000
+/* Real Time Clock */
+#define CONFIG_FTRTC010_BASE		0xf0600000
+/* GPIO */
+#define CONFIG_FTGPIO010_BASE		0xf0700000
+/* I2C */
+#define CONFIG_FTIIC010_BASE		0xf0a00000
+
+/* The following address was not defined in Linux */
+
+/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_FTSSP010_01_BASE		0xf0d00000
+#endif	/* __AE3XX_H */
diff --git a/arch/nds32/include/asm/arch-ag101/ag101.h b/arch/nds32/include/asm/arch-ag101/ag101.h
new file mode 100644
index 0000000..23908f8
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag101/ag101.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#ifndef __AG101_H
+#define __AG101_H
+
+/* Hardware register bases */
+
+/* AHB Controller */
+#define CONFIG_FTAHBC020S_BASE		0x90100000
+/* Static Memory Controller (SRAM) */
+#define CONFIG_FTSMC020_BASE		0x90200000
+/* FTSDMC021 SDRAM Controller */
+#define CONFIG_FTSDMC021_BASE		0x90300000
+/* DMA Controller */
+#define CONFIG_FTDMAC020_BASE		0x90400000
+/* AHB-to-APB Bridge */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90500000
+/* LCD Controller */
+#define CONFIG_FTLCDC100_BASE		0x90600000
+/* Reserved */
+#define CONFIG_RESERVED_01_BASE		0x90700000
+/* Reserved */
+#define CONFIG_RESERVED_02_BASE		0x90800000
+/* Ethernet */
+#define CONFIG_FTMAC100_BASE		0x90900000
+/* External USB host */
+#define CONFIG_EXT_USB_HOST_BASE	0x90A00000
+/* USB Device */
+#define CONFIG_USB_DEV_BASE		0x90B00000
+/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
+#define CONFIG_EXT_AHBPCIBRG_BASE	0x90C00000
+/* Reserved */
+#define CONFIG_RESERVED_03_BASE		0x90D00000
+/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
+#define CONFIG_EXT_AHBAPBBRG_BASE	0x90E00000
+/* External AHB slave1 (LCD) */
+#define CONFIG_EXT_AHBSLAVE01_BASE	0x90F00000
+/* External AHB slave2 (FUSBH200) */
+#define CONFIG_EXT_AHBSLAVE02_BASE	0x92000000
+
+/* DEBUG LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC
+
+/* APB Device definitions */
+
+/* Power Management Unit */
+#define CONFIG_FTPMU010_BASE		0x98100000
+/* BT UART 2/IrDA (UART 01 in Linux) */
+#define CONFIG_FTUART010_01_BASE	0x98300000
+/* Counter/Timers */
+#define CONFIG_FTTMR010_BASE		0x98400000
+/* Watchdog Timer */
+#define CONFIG_FTWDT010_BASE		0x98500000
+/* Real Time Clock */
+#define CONFIG_FTRTC010_BASE		0x98600000
+/* GPIO */
+#define CONFIG_FTGPIO010_BASE		0x98700000
+/* Interrupt Controller */
+#define CONFIG_FTINTC010_BASE		0x98800000
+/* I2C */
+#define CONFIG_FTIIC010_BASE		0x98A00000
+/* Reserved */
+#define CONFIG_RESERVED_04_BASE		0x98C00000
+/* Compat Flash Controller */
+#define CONFIG_FTCFC010_BASE		0x98D00000
+
+/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
+#define CONFIG_FTSSP010_02_BASE		0x99400000
+/* ST UART ? SSP 02 (UART 02 in Linux) */
+#define CONFIG_FTUART010_02_BASE	0x99600000
+
+/* The following address was not defined in Linux */
+
+/* FF UART 3 */
+#define CONFIG_FTUART010_03_BASE	0x98200000
+/* Synchronous Serial Port Controller (SSP) 01 */
+#define CONFIG_FTSSP010_01_BASE		0x98B00000
+/* IrDA */
+#define CONFIG_IRDA_BASE		0x98900000
+/* PWM - Pulse Width Modulator Controller */
+#define CONFIG_PMW_BASE			0x99100000
+
+#endif	/* __AG101_H */
diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h b/arch/nds32/include/asm/arch-ag102/ag102.h
new file mode 100644
index 0000000..d1f4b02
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag102/ag102.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#ifndef __AG102_H
+#define __AG102_H
+
+/*
+ * Hardware register bases
+ */
+
+/* PCI Controller */
+#define CONFIG_FTPCI100_BASE		0x90000000
+/* LPC Controller */
+#define CONFIG_LPC_IO_BASE		0x90100000
+/* LPC Controller */
+#define CONFIG_LPC_BASE			0x90200000
+
+/* NDS32 Data Local Memory 01 */
+#define CONFIG_NDS_DLM1_BASE		0x90300000
+/* NDS32 Data Local Memory 02 */
+#define CONFIG_NDS_DLM2_BASE		0x90400000
+
+/* Synopsys DWC DDR2/1 Controller */
+#define CONFIG_DWCDDR21MCTL_BASE	0x90500000
+/* DMA Controller */
+#define CONFIG_FTDMAC020_BASE		0x90600000
+/* FTIDE020_S IDE (ATA) Controller */
+#define CONFIG_FTIDE020S_BASE		0x90700000
+/* USB OTG Controller */
+#define CONFIG_FZOTG266HD0A_BASE	0x90800000
+/* Andes L2 Cache Controller */
+#define CONFIG_NCEL2C100_BASE		0x90900000
+/* XGI XG22 GPU */
+#define CONFIG_XGI_XG22_BASE		0x90A00000
+/* GMAC Ethernet Controller */
+#define CONFIG_FTGMAC100_BASE		0x90B00000
+/* AHB Controller */
+#define CONFIG_FTAHBC020S_BASE		0x90C00000
+/* AHB-to-APB Bridge Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE	0x90D00000
+/* External AHB2AHB Controller */
+#define CONFIG_EXT_AHB2AHB_BASE		0x90E00000
+/* Andes Multi-core Interrupt Controller */
+#define CONFIG_NCEMIC100_BASE		0x90F00000
+
+/*
+ * APB Device definitions
+ */
+/* Compat Flash Controller */
+#define CONFIG_FTCFC010_BASE		0x94000000
+/* APB - SSP (SPI) (without AC97) Controller */
+#define CONFIG_FTSSP010_01_BASE		0x94100000
+/* UART1 - APB STUART Controller (UART0 in Linux) */
+#define CONFIG_FTUART010_01_BASE	0x94200000
+/* APB - SSP with HDA/AC97 Controller */
+#define CONFIG_FTSSP010_02_BASE		0x94500000
+/* UART2 - APB STUART Controller (UART1 in Linux) */
+#define CONFIG_FTUART010_02_BASE	0x94600000
+/* PCU Controller */
+#define CONFIG_ANDES_PCU_BASE		0x94800000
+/* FTTMR010 Timer */
+#define CONFIG_FTTMR010_BASE		0x94900000
+/* Watch Dog Controller */
+#define CONFIG_FTWDT010_BASE		0x94A00000
+/* FTRTC010 Real Time Clock */
+#define CONFIG_FTRTC010_BASE		0x98B00000
+/* GPIO Controller */
+#define CONFIG_FTGPIO010_BASE		0x94C00000
+/* I2C Controller */
+#define CONFIG_FTIIC010_BASE		0x94E00000
+/* PWM - Pulse Width Modulator Controller */
+#define CONFIG_FTPWM010_BASE		0x94F00000
+
+/* Debug LED */
+#define CONFIG_DEBUG_LED		0x902FFFFC
+/* Power Management Unit */
+#define CONFIG_FTPMU010_BASE		0x98100000
+
+#endif	/* __AG102_H */
diff --git a/arch/nds32/include/asm/bitops.h b/arch/nds32/include/asm/bitops.h
new file mode 100644
index 0000000..f1cdcf3
--- /dev/null
+++ b/arch/nds32/include/asm/bitops.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_NDS_BITOPS_H
+#define __ASM_NDS_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, void *addr);
+
+static inline void __set_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+#define PLATFORM__SET_BIT
+
+extern void clear_bit(int nr, void *addr);
+
+static inline void __clear_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+#define PLATFORM__CLEAR_BIT
+
+extern void change_bit(int nr, void *addr);
+
+static inline void __change_bit(int nr, void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+extern int test_and_set_bit(int nr, void *addr);
+
+static inline int __test_and_set_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+extern int test_and_clear_bit(int nr, void *addr);
+
+static inline int __test_and_clear_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+extern int test_and_change_bit(int nr, void *addr);
+
+static inline int __test_and_change_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NDS_BITOPS_H */
diff --git a/arch/nds32/include/asm/bootm.h b/arch/nds32/include/asm/bootm.h
new file mode 100644
index 0000000..804f858
--- /dev/null
+++ b/arch/nds32/include/asm/bootm.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ */
+#ifndef NDS32_BOOTM_H
+#define NDS32_BOOTM_H
+
+#include <asm/setup.h>
+
+extern void udc_disconnect(void);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+		defined(CONFIG_CMDLINE_TAG) || \
+		defined(CONFIG_INITRD_TAG) || \
+		defined(CONFIG_SERIAL_TAG) || \
+		defined(CONFIG_REVISION_TAG)
+# define BOOTM_ENABLE_TAGS		1
+#else
+# define BOOTM_ENABLE_TAGS		0
+#endif
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+# define BOOTM_ENABLE_MEMORY_TAGS	1
+#else
+# define BOOTM_ENABLE_MEMORY_TAGS	0
+#endif
+
+#ifdef CONFIG_CMDLINE_TAG
+ #define BOOTM_ENABLE_CMDLINE_TAG	1
+#else
+ #define BOOTM_ENABLE_CMDLINE_TAG	0
+#endif
+
+#ifdef CONFIG_INITRD_TAG
+ #define BOOTM_ENABLE_INITRD_TAG	1
+#else
+ #define BOOTM_ENABLE_INITRD_TAG	0
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+ #define BOOTM_ENABLE_SERIAL_TAG	1
+void get_board_serial(struct tag_serialnr *serialnr);
+#else
+ #define BOOTM_ENABLE_SERIAL_TAG	0
+static inline void get_board_serial(struct tag_serialnr *serialnr)
+{
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+ #define BOOTM_ENABLE_REVISION_TAG	1
+u32 get_board_rev(void);
+#else
+ #define BOOTM_ENABLE_REVISION_TAG	0
+static inline u32 get_board_rev(void)
+{
+	return 0;
+}
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/byteorder.h b/arch/nds32/include/asm/byteorder.h
new file mode 100644
index 0000000..39fd9ed
--- /dev/null
+++ b/arch/nds32/include/asm/byteorder.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_NDS_BYTEORDER_H
+#define __ASM_NDS_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __NDSEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
new file mode 100644
index 0000000..6c72b2b
--- /dev/null
+++ b/arch/nds32/include/asm/cache.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+/* cache */
+int	icache_status(void);
+void	icache_enable(void);
+void	icache_disable(void);
+int	dcache_status(void);
+void	dcache_enable(void);
+void	dcache_disable(void);
+void cache_flush(void);
+
+#define DEFINE_GET_SYS_REG(reg) \
+	static inline unsigned long GET_##reg(void)		\
+	{							\
+		unsigned long val;				\
+		__asm__ volatile (				\
+		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
+		);						\
+		return val;					\
+	}
+
+enum cache_t {ICACHE, DCACHE};
+DEFINE_GET_SYS_REG(ICM_CFG);
+DEFINE_GET_SYS_REG(DCM_CFG);
+/* I-cache sets (# of cache lines) per way */
+#define ICM_CFG_OFF_ISET	0
+/* I-cache ways */
+#define ICM_CFG_OFF_IWAY	3
+#define ICM_CFG_MSK_ISET	(0x7 << ICM_CFG_OFF_ISET)
+#define ICM_CFG_MSK_IWAY	(0x7 << ICM_CFG_OFF_IWAY)
+/* D-cache sets (# of cache lines) per way */
+#define DCM_CFG_OFF_DSET	0
+/* D-cache ways */
+#define DCM_CFG_OFF_DWAY	3
+#define DCM_CFG_MSK_DSET	(0x7 << DCM_CFG_OFF_DSET)
+#define DCM_CFG_MSK_DWAY	(0x7 << DCM_CFG_OFF_DWAY)
+/* I-cache line size */
+#define ICM_CFG_OFF_ISZ	6
+#define ICM_CFG_MSK_ISZ		(0x7UL << ICM_CFG_OFF_ISZ)
+/* D-cache line size */
+#define DCM_CFG_OFF_DSZ	6
+#define DCM_CFG_MSK_DSZ		(0x7UL << DCM_CFG_OFF_DSZ)
+
+/*
+ * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	32
+#endif
+
+#endif /* _ASM_CACHE_H */
diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h
new file mode 100644
index 0000000..8964a58
--- /dev/null
+++ b/arch/nds32/include/asm/config.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+#define CONFIG_LMB
+
+#endif
diff --git a/arch/nds32/include/asm/dma-mapping.h b/arch/nds32/include/asm/dma-mapping.h
new file mode 100644
index 0000000..e6808dc
--- /dev/null
+++ b/arch/nds32/include/asm/dma-mapping.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Andes Technology Corporation
+ * Ken Kuo, Andes Technology Corporation <ken_kuo@andestech.com>
+ */
+#ifndef __ASM_NDS_DMA_MAPPING_H
+#define __ASM_NDS_DMA_MAPPING_H
+
+#include <linux/dma-direction.h>
+
+static void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+	return (void *)*handle;
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+					   enum dma_data_direction dir)
+{
+	return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+				    unsigned long paddr)
+{
+}
+
+#endif /* __ASM_NDS_DMA_MAPPING_H */
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
new file mode 100644
index 0000000..be04a18
--- /dev/null
+++ b/arch/nds32/include/asm/global_data.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far no one uses the macros defined in this head file.
+ **************************************************************/
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+/* Architecture-specific global data */
+struct arch_global_data {
+};
+
+#include <asm-generic/global_data.h>
+
+#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
+extern volatile gd_t g_gd;
+#define DECLARE_GLOBAL_DATA_PTR		static volatile gd_t *gd = &g_gd
+#else
+#define DECLARE_GLOBAL_DATA_PTR		register volatile gd_t *gd asm ("$r10")
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h
new file mode 100644
index 0000000..fdfc574
--- /dev/null
+++ b/arch/nds32/include/asm/io.h
@@ -0,0 +1,457 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  linux/include/asm-nds/io.h
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_NDS_IO_H
+#define __ASM_NDS_IO_H
+
+/*
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
+ *     iinclude asm/io.h
+ */
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+}
+
+#ifdef CONFIG_ARCH_MAP_SYSMEM
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+	if(paddr <PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE)
+	paddr = paddr | 0x40000000;
+	return (void *)(uintptr_t)paddr;
+}
+
+static inline void *unmap_sysmem(const void *vaddr)
+{
+	phys_addr_t paddr = (phys_addr_t)vaddr;
+	paddr = paddr & ~0x40000000;
+	return (void *)(uintptr_t)paddr;
+}
+
+static inline phys_addr_t map_to_sysmem(const void *ptr)
+{
+	return (phys_addr_t)(uintptr_t)ptr;
+}
+#endif
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(unsigned char *)(a))
+#define __arch_getw(a)			(*(unsigned short *)(a))
+#define __arch_getl(a)			(*(unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+/*
+ * TODO: The kernel offers some more advanced versions of barriers, it might
+ * have some advantages to use them instead of the simple one here.
+ */
+#define dmb()		__asm__ __volatile__ ("" : : : "memory")
+#define __iormb()	dmb()
+#define __iowmb()	dmb()
+
+static inline void writeb(u8 val, volatile void __iomem *addr)
+{
+	__iowmb();
+	__arch_putb(val, addr);
+}
+
+static inline void writew(u16 val, volatile void __iomem *addr)
+{
+	__iowmb();
+	__arch_putw(val, addr);
+
+}
+
+static inline void writel(u32 val, volatile void __iomem *addr)
+{
+	__iowmb();
+	__arch_putl(val, addr);
+}
+
+static inline u8 readb(const volatile void __iomem *addr)
+{
+	u8	val;
+
+	val = __arch_getb(addr);
+	__iormb();
+	return val;
+}
+
+static inline u16 readw(const volatile void __iomem *addr)
+{
+	u16	val;
+
+	val = __arch_getw(addr);
+	__iormb();
+	return val;
+}
+
+static inline u32 readl(const volatile void __iomem *addr)
+{
+	u32	val;
+
+	val = __arch_getl(addr);
+	__iormb();
+	return val;
+}
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+#define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v)			out_arch(l, le32, a, v)
+#define out_le16(a, v)			out_arch(w, le16, a, v)
+
+#define in_le32(a)			in_arch(l, le32, a)
+#define in_le16(a)			in_arch(w, le16, a)
+
+#define out_be32(a, v)			out_arch(l, be32, a, v)
+#define out_be16(a, v)			out_arch(w, be16, a, v)
+
+#define in_be32(a)			in_arch(l, be32, a)
+#define in_be16(a)			in_arch(w, be16, a)
+
+#define out_8(a, v)			__raw_writeb(v, a)
+#define in_8(a)				__raw_readb(a)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+static inline void writesb(unsigned int *addr, const void * data, int bytelen)
+{
+	unsigned char *ptr = (unsigned char *)addr;
+	unsigned char *ptr2 = (unsigned char *)data;
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+static inline void writesw(unsigned int *addr, const void * data, int wordlen)
+{
+	unsigned short *ptr = (unsigned short *)addr;
+	unsigned short *ptr2 = (unsigned short *)data;
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+static inline void writesl(unsigned int *addr, const void * data, int longlen)
+{
+	unsigned int *ptr = (unsigned int *)addr;
+	unsigned int *ptr2 = (unsigned int *)data;
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = \
+			__raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = \
+			le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = \
+			le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(unsigned long io_addr, const unsigned char *signature,
+			int length)
+{
+	int retval = 0;
+	do {
+		if (isa_readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+
+#include <asm-generic/io.h>
+
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_NDS_IO_H */
diff --git a/arch/nds32/include/asm/linkage.h b/arch/nds32/include/asm/linkage.h
new file mode 100644
index 0000000..0c8822b
--- /dev/null
+++ b/arch/nds32/include/asm/linkage.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * U-Boot - linkage.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ */
+
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#endif
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
new file mode 100644
index 0000000..99904f9
--- /dev/null
+++ b/arch/nds32/include/asm/mach-types.h
@@ -0,0 +1,30 @@
+/*
+ * This was automagically generated from arch/nds/tools/mach-types!
+ * Do NOT edit
+ */
+
+#ifndef __ASM_NDS32_MACH_TYPE_H
+#define __ASM_NDS32_MACH_TYPE_H
+
+#ifndef __ASSEMBLY__
+/* The type of machine we're running on */
+extern unsigned int __machine_arch_type;
+#endif
+
+/* see arch/arm/kernel/arch.c for a description of these */
+#define MACH_TYPE_ADPAG101P            1
+#define MACH_TYPE_ADPAE3XX	2
+
+#ifdef CONFIG_ARCH_ADPAG101P
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADPAG101P
+# endif
+# define machine_is_adpag101p()	(machine_arch_type == MACH_TYPE_ADPAG101P)
+#else
+# define machine_is_adpag101p()	(1)
+#endif
+
+#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/arch/nds32/include/asm/macro.h b/arch/nds32/include/asm/macro.h
new file mode 100644
index 0000000..4e11947
--- /dev/null
+++ b/arch/nds32/include/asm/macro.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/asm-nds32/macro.h
+ *
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#ifndef __ASM_NDS_MACRO_H
+#define __ASM_NDS_MACRO_H
+#ifdef __ASSEMBLY__
+
+/*
+ * These macros provide a convenient way to write 8, 16 and 32 bit data
+ * to an "immediate address (address used by periphal)" only.
+ * Registers r4 and r5 are used, any data in these registers are
+ * overwritten by the macros.
+ * The macros are valid for any NDS32 architecture, they do not implement
+ * any memory barriers so caution is recommended when using these when the
+ * caches are enabled or on a multi-core system.
+ */
+
+.macro	write32, addr, data
+	li	$r4, \addr
+	li	$r5, \data
+	swi	$r5, [$r4]
+.endm
+
+.macro	write16, addr, data
+	li	$r4, \addr
+	li	$r5, \data
+	shi	$r5, [$r4]
+.endm
+
+.macro	write8, addr, data
+	li	$r4, \addr
+	li	$r5, \data
+	sbi	$r5, [$r4]
+.endm
+
+/*
+ * This macro read a value from a register, then do OR operation
+ * (set bit fields) to the value, and then store it back to the register.
+ * Note: Instruction 'ori' supports immediate value up to 15 bits.
+ */
+.macro	setbf32, addr, data
+	li	$r4, \addr
+	lwi	$r5, [$r4]
+	li	$r6, \data
+	or	$r5, $r5, $r6
+	swi	$r5, [$r4]
+.endm
+
+.macro	setbf15, addr, data
+	li	$r4, \addr
+	lwi	$r5, [$r4]
+	ori	$r5, $r5, \data
+	swi	$r5, [$r4]
+.endm
+
+/*
+ * This macro generates a loop that can be used for delays in the code.
+ * Register r4 is used, any data in this register is overwritten by the
+ * macro.
+ * The macro is valid for any NDS32 architeture. The actual time spent in the
+ * loop will vary from CPU to CPU though.
+ */
+
+.macro	wait_timer, time
+	li	$r4, \time
+1:
+	nop
+	addi	$r4, $r4, -1
+	bnez    $r4, 1b
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARM_MACRO_H */
diff --git a/arch/nds32/include/asm/posix_types.h b/arch/nds32/include/asm/posix_types.h
new file mode 100644
index 0000000..e6c591d
--- /dev/null
+++ b/arch/nds32/include/asm/posix_types.h
@@ -0,0 +1,88 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   05-03-2010	Modified for arch NDS32
+ */
+#ifndef __ARCH_NDS_POSIX_TYPES_H
+#define __ARCH_NDS_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+#ifdef __GNUC__
+typedef __SIZE_TYPE__		__kernel_size_t;
+#else
+typedef unsigned int		__kernel_size_t;
+#endif
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+		(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+		((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+		(memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
+
+#endif
+
+#endif /* __ARCH_NDS_POSIX_TYPES_H */
diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h
new file mode 100644
index 0000000..e5d186c
--- /dev/null
+++ b/arch/nds32/include/asm/processor.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_NDS_PROCESSOR_H
+#define __ASM_NDS_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for NDS32 Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
new file mode 100644
index 0000000..ee181b2
--- /dev/null
+++ b/arch/nds32/include/asm/ptrace.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_NDS_PTRACE_H
+#define __ASM_NDS_PTRACE_H
+
+#define USR_MODE	0x00
+#define SU_MODE		0x01
+#define HV_MODE		0x10
+#define MODE_MASK	(0x03<<3)
+#define GIE_BIT		0x01
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+#define NDS32_REG long
+
+struct pt_regs {
+	NDS32_REG ir0;
+	NDS32_REG ipsw;
+	NDS32_REG ipc;
+	NDS32_REG sp;
+	NDS32_REG orig_r0;
+	NDS32_REG pipsw;
+	NDS32_REG pipc;
+	NDS32_REG pp0;
+	NDS32_REG pp1;
+	NDS32_REG d0hi;
+	NDS32_REG d0lo;
+	NDS32_REG d1hi;
+	NDS32_REG d1lo;
+	NDS32_REG r[26];	/* r0 - r25 */
+	NDS32_REG p0;		/* r26 - used by OS */
+	NDS32_REG p1;		/* r27 - used by OS */
+	NDS32_REG fp;		/* r28 */
+	NDS32_REG gp;		/* r29 */
+	NDS32_REG lp;		/* r30 */
+	NDS32_REG fucop_ctl;
+	NDS32_REG osp;
+};
+
+#define processor_mode(regs) \
+	(((regs)->ipsw & MODE_MASK) >> 3)
+
+#define interrupts_enabled(regs) \
+	((regs)->ipsw & GIE_BIT)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+
+#endif	/* __ASSEMBLY__ */
+
+#endif /* __ASM_NDS_PTRACE_H */
diff --git a/arch/nds32/include/asm/sections.h b/arch/nds32/include/asm/sections.h
new file mode 100644
index 0000000..aba9d97
--- /dev/null
+++ b/arch/nds32/include/asm/sections.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_NDS32_SECTIONS_H
+#define __ASM_NDS32_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/nds32/include/asm/setup.h b/arch/nds32/include/asm/setup.h
new file mode 100644
index 0000000..8217bbf
--- /dev/null
+++ b/arch/nds32/include/asm/setup.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  linux/arch/nds32/include/asm/setup.h
+ *
+ *  Copyright (C) 1997-1999 Russell King
+ *  Copyright (C) 2008 Andes Technology Corporation
+ *	Copyright (C) 2013 Ken Kuo (ken_kuo@andestech.com)
+ *
+ *  Structure passed to kernel to tell it about the
+ *  hardware it's running on.  See Documentation/arm/Setup
+ *  for more info.
+ */
+#ifndef __ASMNDS32_SETUP_H
+#define __ASMNDS32_SETUP_H
+
+#define COMMAND_LINE_SIZE 256
+
+/* The list ends with an ATAG_NONE node. */
+#define ATAG_NONE	0x00000000
+
+struct tag_header {
+	u32 size;
+	u32 tag;
+};
+
+/* The list must start with an ATAG_CORE node */
+#define ATAG_CORE	0x54410001
+
+struct tag_core {
+	u32 flags;		/* bit 0 = read-only */
+	u32 pagesize;
+	u32 rootdev;
+};
+
+/* it is allowed to have multiple ATAG_MEM nodes */
+#define ATAG_MEM	0x54410002
+
+struct tag_mem32 {
+	u32	size;
+	u32	start;	/* physical start address */
+};
+
+/* VGA text type displays */
+#define ATAG_VIDEOTEXT	0x54410003
+
+struct tag_videotext {
+	u8		x;
+	u8		y;
+	u16		video_page;
+	u8		video_mode;
+	u8		video_cols;
+	u16		video_ega_bx;
+	u8		video_lines;
+	u8		video_isvga;
+	u16		video_points;
+};
+
+/* describes how the ramdisk will be used in kernel */
+#define ATAG_RAMDISK	0x54410004
+
+struct tag_ramdisk {
+	u32 flags;	/* bit 0 = load, bit 1 = prompt */
+	u32 size;	/* decompressed ramdisk size in _kilo_ bytes */
+	u32 start;	/* starting block of floppy-based RAM disk image */
+};
+
+/*
+ * this one accidentally used virtual addresses - as such,
+ * it's deprecated.
+ * describes where the compressed ramdisk image lives (virtual address)
+ */
+#define ATAG_INITRD		0x54410005
+
+/* describes where the compressed ramdisk image lives (physical address) */
+#define ATAG_INITRD2	0x54420005
+
+struct tag_initrd {
+	u32 start;	/* physical start address */
+	u32 size;	/* size of compressed ramdisk image in bytes */
+};
+
+/* board serial number. "64 bits should be enough for everybody" */
+#define ATAG_SERIAL		0x54410006
+
+struct tag_serialnr {
+	u32 low;
+	u32 high;
+};
+
+/* board revision */
+#define ATAG_REVISION	0x54410007
+
+struct tag_revision {
+	u32 rev;
+};
+
+/* initial values for vesafb-type framebuffers. see struct screen_info
+ * in include/linux/tty.h
+ */
+#define ATAG_VIDEOLFB	0x54410008
+
+struct tag_videolfb {
+	u16		lfb_width;
+	u16		lfb_height;
+	u16		lfb_depth;
+	u16		lfb_linelength;
+	u32		lfb_base;
+	u32		lfb_size;
+	u8		red_size;
+	u8		red_pos;
+	u8		green_size;
+	u8		green_pos;
+	u8		blue_size;
+	u8		blue_pos;
+	u8		rsvd_size;
+	u8		rsvd_pos;
+};
+
+/* command line: \0 terminated string */
+#define ATAG_CMDLINE	0x54410009
+
+struct tag_cmdline {
+	char	cmdline[COMMAND_LINE_SIZE];
+};
+
+struct tag {
+	struct tag_header hdr;
+	union {
+		struct tag_core		core;
+		struct tag_mem32	mem;
+		struct tag_videotext	videotext;
+		struct tag_ramdisk	ramdisk;
+		struct tag_initrd	initrd;
+		struct tag_serialnr	serialnr;
+		struct tag_revision	revision;
+		struct tag_videolfb	videolfb;
+		struct tag_cmdline	cmdline;
+	} u;
+};
+
+struct tagtable {
+	u32 tag;
+	int (*parse)(const struct tag *);
+};
+
+#define tag_member_present(tag, member)				\
+	((unsigned long)(&((struct tag *)0L)->member + 1)	\
+		<= (tag)->hdr.size * 4)
+
+#define tag_next(t)	((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_size(type)	((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
+
+#define for_each_tag(t, base) \
+	for (t = base; t->hdr.size; t = tag_next(t))
+
+#ifdef __KERNEL__
+
+#define __tag __used __attribute__((__section__(".taglist")))
+#define __tagtable(tag, fn) \
+static struct tagtable __tagtable_##fn __tag = { tag, fn }
+
+/*
+ * Memory map description
+ */
+#define NR_BANKS 8
+
+struct meminfo {
+	int nr_banks;
+	struct {
+		unsigned long start;
+		unsigned long size;
+		int           node;
+	} bank[NR_BANKS];
+};
+
+/*
+ * Early command line parameters.
+ */
+struct early_params {
+	const char *arg;
+	void (*fn)(char **p);
+};
+
+#define __early_param(name, fn)					\
+static struct early_params __early_##fn __used	\
+__attribute__((__section__("__early_param"))) = { name, fn }
+
+#endif
+#endif
diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h
new file mode 100644
index 0000000..610aa9e
--- /dev/null
+++ b/arch/nds32/include/asm/string.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_STRING_H
+#define __ASM_NDS_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#ifdef CONFIG_MARCO_MEMSET
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p, v, n)							\
+	({								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
+#else
+extern void memzero(void *ptr, __kernel_size_t n);
+#endif
+
+#endif /* __ASM_NDS_STRING_H */
diff --git a/arch/nds32/include/asm/system.h b/arch/nds32/include/asm/system.h
new file mode 100644
index 0000000..5453a9b
--- /dev/null
+++ b/arch/nds32/include/asm/system.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#ifndef __ASM_NDS_SYSTEM_H
+#define __ASM_NDS_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern int irq_flags;
+
+#define local_irq_enable() \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		: \
+		: "r" (irq_flags) \
+	)
+
+#define local_irq_disable() \
+	do { \
+		int __tmp_dummy; \
+		__asm__ __volatile__ ( \
+			"mfsr	%0, $psw\n\t" \
+			"andi	%0, %0, 0x1\n\t" \
+			"setgie.d\n\t" \
+			"dsb\n\t" \
+			: "=r" (__tmp_dummy) \
+		); \
+	} while (0)
+
+#define local_irq_save(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.d\n\t" \
+		"dsb\n\t" \
+		: "=&r" (x) \
+	)
+
+#define local_save_flags(x) \
+	__asm__ __volatile__ ( \
+		"mfsr	%0, $psw\n\t" \
+		"andi	%0, %0, 0x1\n\t" \
+		"setgie.e\n\t" \
+		"setgie.d\n\t" \
+		: "=r" (x) \
+	)
+
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+
+#define local_irq_restore(x) \
+	do { \
+		if (irqs_enabled_from_flags(x)) \
+			local_irq_enable(); \
+	} while (0)
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()			asm volatile ("nop;\n\t" : : )
+#define mb()			asm volatile (""   : : : "memory")
+#define rmb()			asm volatile (""   : : : "memory")
+#define wmb()			asm volatile (""   : : : "memory")
+
+#endif	/* __ASM_NDS_SYSTEM_H */
diff --git a/arch/nds32/include/asm/types.h b/arch/nds32/include/asm/types.h
new file mode 100644
index 0000000..d2444da
--- /dev/null
+++ b/arch/nds32/include/asm/types.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_NDS_TYPES_H
+#define __ASM_NDS_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+typedef unsigned short umode_t;
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h
new file mode 100644
index 0000000..7d39320
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot-nds32.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#ifndef _U_BOOT_NDS32_H_
+#define _U_BOOT_NDS32_H_	1
+
+/* for the following variables, see start.S */
+extern ulong IRQ_STACK_START;	/* top of IRQ stack */
+extern ulong FIQ_STACK_START;	/* top of FIQ stack */
+
+/* cpu/.../cpu.c */
+int	cleanup_before_linux(void);
+
+/* board/.../... */
+int	board_init(void);
+
+/* cpu/.../interrupt.c */
+void	reset_timer_masked(void);
+
+#endif	/* _U_BOOT_NDS32_H_ */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
new file mode 100644
index 0000000..8c949e7
--- /dev/null
+++ b/arch/nds32/include/asm/u-boot.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <asm/u-boot-nds32.h>
+
+
+typedef struct bd_info {
+	unsigned long	bi_arch_number;	/* unique id for this board */
+	unsigned long	bi_boot_params;	/* where this board expects params */
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned char	bi_enetaddr[6];
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_NDS32
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/nds32/include/asm/unaligned.h b/arch/nds32/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/nds32/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
diff --git a/arch/nios2/include/asm/bitops.h b/arch/nios2/include/asm/bitops.h
new file mode 100644
index 0000000..289da18
--- /dev/null
+++ b/arch/nios2/include/asm/bitops.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#ifndef __ASM_NIOS2_BITOPS_H_
+#define __ASM_NIOS2_BITOPS_H_
+
+/* copied from linux-2.6/include/asm-generic/bitops */
+#include <asm/bitops/atomic.h>
+#include <asm/bitops/non-atomic.h>
+#include <asm/bitops/ffs.h>
+
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+#endif /* __ASM_NIOS2_BITOPS_H */
diff --git a/arch/nios2/include/asm/bitops/atomic.h b/arch/nios2/include/asm/bitops/atomic.h
new file mode 100644
index 0000000..c894646
--- /dev/null
+++ b/arch/nios2/include/asm/bitops/atomic.h
@@ -0,0 +1,189 @@
+#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_
+#define _ASM_GENERIC_BITOPS_ATOMIC_H_
+
+#include <asm/types.h>
+#include <asm/system.h>
+
+#ifdef CONFIG_SMP
+#include <asm/spinlock.h>
+#include <asm/cache.h>		/* we use L1_CACHE_BYTES */
+
+/* Use an array of spinlocks for our atomic_ts.
+ * Hash function to index into a different SPINLOCK.
+ * Since "a" is usually an address, use one spinlock per cacheline.
+ */
+#  define ATOMIC_HASH_SIZE 4
+#  define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))
+
+extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;
+
+/* Can't use raw_spin_lock_irq because of #include problems, so
+ * this is the substitute */
+#define _atomic_spin_lock_irqsave(l,f) do {	\
+	raw_spinlock_t *s = ATOMIC_HASH(l);	\
+	local_irq_save(f);			\
+	__raw_spin_lock(s);			\
+} while(0)
+
+#define _atomic_spin_unlock_irqrestore(l,f) do {	\
+	raw_spinlock_t *s = ATOMIC_HASH(l);		\
+	__raw_spin_unlock(s);				\
+	local_irq_restore(f);				\
+} while(0)
+
+
+#else
+#  define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
+#  define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
+#endif
+
+/*
+ * NMI events can occur at any time, including when interrupts have been
+ * disabled by *_irqsave().  So you can get NMI events occurring while a
+ * *_bit function is holding a spin lock.  If the NMI handler also wants
+ * to do bit manipulation (and they do) then you can get a deadlock
+ * between the original caller of *_bit() and the NMI handler.
+ *
+ * by Keith Owens
+ */
+
+/**
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered.  See __set_bit()
+ * if you do not require the atomic guarantees.
+ *
+ * Note: there are no guarantees that this function will not be reordered
+ * on non x86 architectures, so if you are writing portable code,
+ * make sure not to rely on its reordering guarantees.
+ *
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void set_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long flags;
+
+	_atomic_spin_lock_irqsave(p, flags);
+	*p  |= mask;
+	_atomic_spin_unlock_irqrestore(p, flags);
+}
+
+/**
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+static inline void clear_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long flags;
+
+	_atomic_spin_lock_irqsave(p, flags);
+	*p &= ~mask;
+	_atomic_spin_unlock_irqrestore(p, flags);
+}
+
+/**
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to change
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered. It may be
+ * reordered on other architectures than x86.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static inline void change_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long flags;
+
+	_atomic_spin_lock_irqsave(p, flags);
+	*p ^= mask;
+	_atomic_spin_unlock_irqrestore(p, flags);
+}
+
+/**
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It may be reordered on other architectures than x86.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old;
+	unsigned long flags;
+
+	_atomic_spin_lock_irqsave(p, flags);
+	old = *p;
+	*p = old | mask;
+	_atomic_spin_unlock_irqrestore(p, flags);
+
+	return (old & mask) != 0;
+}
+
+/**
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It can be reorderdered on other architectures other than x86.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old;
+	unsigned long flags;
+
+	_atomic_spin_lock_irqsave(p, flags);
+	old = *p;
+	*p = old & ~mask;
+	_atomic_spin_unlock_irqrestore(p, flags);
+
+	return (old & mask) != 0;
+}
+
+/**
+ * test_and_change_bit - Change a bit and return its old value
+ * @nr: Bit to change
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old;
+	unsigned long flags;
+
+	_atomic_spin_lock_irqsave(p, flags);
+	old = *p;
+	*p = old ^ mask;
+	_atomic_spin_unlock_irqrestore(p, flags);
+
+	return (old & mask) != 0;
+}
+
+#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */
diff --git a/arch/nios2/include/asm/bitops/ffs.h b/arch/nios2/include/asm/bitops/ffs.h
new file mode 100644
index 0000000..fbbb43a
--- /dev/null
+++ b/arch/nios2/include/asm/bitops/ffs.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_GENERIC_BITOPS_FFS_H_
+#define _ASM_GENERIC_BITOPS_FFS_H_
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static inline int ffs(int x)
+{
+	int r = 1;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff)) {
+		x >>= 16;
+		r += 16;
+	}
+	if (!(x & 0xff)) {
+		x >>= 8;
+		r += 8;
+	}
+	if (!(x & 0xf)) {
+		x >>= 4;
+		r += 4;
+	}
+	if (!(x & 3)) {
+		x >>= 2;
+		r += 2;
+	}
+	if (!(x & 1)) {
+		x >>= 1;
+		r += 1;
+	}
+	return r;
+}
+
+#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */
diff --git a/arch/nios2/include/asm/bitops/non-atomic.h b/arch/nios2/include/asm/bitops/non-atomic.h
new file mode 100644
index 0000000..f746819
--- /dev/null
+++ b/arch/nios2/include/asm/bitops/non-atomic.h
@@ -0,0 +1,112 @@
+#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
+#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_
+
+#include <asm/types.h>
+
+/**
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __set_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p  |= mask;
+}
+
+#define PLATFORM__SET_BIT
+
+static inline void __clear_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p &= ~mask;
+}
+
+#define PLATFORM__CLEAR_BIT
+
+/**
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to change
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void __change_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p ^= mask;
+}
+
+/**
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old | mask;
+	return (old & mask) != 0;
+}
+
+/**
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to clear
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old & ~mask;
+	return (old & mask) != 0;
+}
+
+/* WARNING: non atomic and it can be reordered! */
+static inline int __test_and_change_bit(int nr,
+					    volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old ^ mask;
+	return (old & mask) != 0;
+}
+
+/**
+ * test_bit - Determine whether a bit is set
+ * @nr: bit number to test
+ * @addr: Address to start counting from
+ */
+static inline int test_bit(int nr, const volatile unsigned long *addr)
+{
+	return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
+}
+
+#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */
diff --git a/arch/nios2/include/asm/byteorder.h b/arch/nios2/include/asm/byteorder.h
new file mode 100644
index 0000000..5d96b31
--- /dev/null
+++ b/arch/nios2/include/asm/byteorder.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#ifndef __ASM_NIOS2_BYTEORDER_H_
+#define __ASM_NIOS2_BYTEORDER_H_
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#include <linux/byteorder/little_endian.h>
+
+#endif /* __ASM_NIOS2_BYTEORDER_H_ */
diff --git a/arch/nios2/include/asm/cache.h b/arch/nios2/include/asm/cache.h
new file mode 100644
index 0000000..5784884
--- /dev/null
+++ b/arch/nios2/include/asm/cache.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#ifndef __ASM_NIOS2_CACHE_H_
+#define __ASM_NIOS2_CACHE_H_
+
+/*
+ * Valid L1 data cache line sizes for the NIOS2 architecture are 4,
+ * 16, and 32 bytes. We default to the largest of these values for
+ * alignment of DMA buffers.
+ */
+#define ARCH_DMA_MINALIGN	32
+
+#endif /* __ASM_NIOS2_CACHE_H_ */
diff --git a/arch/nios2/include/asm/config.h b/arch/nios2/include/asm/config.h
new file mode 100644
index 0000000..bad0026
--- /dev/null
+++ b/arch/nios2/include/asm/config.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#endif
diff --git a/arch/nios2/include/asm/dma-mapping.h b/arch/nios2/include/asm/dma-mapping.h
new file mode 100644
index 0000000..65f67bc
--- /dev/null
+++ b/arch/nios2/include/asm/dma-mapping.h
@@ -0,0 +1,24 @@
+#ifndef __ASM_NIOS2_DMA_MAPPING_H
+#define __ASM_NIOS2_DMA_MAPPING_H
+
+#include <memalign.h>
+#include <asm/io.h>
+
+/*
+ * dma_alloc_coherent() return cache-line aligned allocation which is mapped
+ * to uncached io region.
+ */
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+	unsigned long addr = (unsigned long)malloc_cache_aligned(len);
+
+	if (!addr)
+		return NULL;
+
+	invalidate_dcache_range(addr, addr + len);
+	if (handle)
+		*handle = addr;
+
+	return map_physmem(addr, len, MAP_NOCACHE);
+}
+#endif /* __ASM_NIOS2_DMA_MAPPING_H */
diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h
new file mode 100644
index 0000000..1a0e7d2
--- /dev/null
+++ b/arch/nios2/include/asm/global_data.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+#ifndef	__ASM_NIOS2_GLOBALDATA_H_
+#define __ASM_NIOS2_GLOBALDATA_H_
+
+/* Architecture-specific global data */
+struct arch_global_data {
+	u32 dcache_line_size;
+	u32 icache_line_size;
+	u32 dcache_size;
+	u32 icache_size;
+	u32 reset_addr;
+	u32 exception_addr;
+	int has_initda;
+	int has_mmu;
+	u32 io_region_base;
+	u32 mem_region_base;
+	u32 physaddr_mask;
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR     register gd_t *gd asm ("gp")
+
+#endif /* __ASM_NIOS2_GLOBALDATA_H_ */
diff --git a/arch/nios2/include/asm/gpio.h b/arch/nios2/include/asm/gpio.h
new file mode 100644
index 0000000..306ab4c
--- /dev/null
+++ b/arch/nios2/include/asm/gpio.h
@@ -0,0 +1 @@
+#include <asm-generic/gpio.h>
diff --git a/arch/nios2/include/asm/io.h b/arch/nios2/include/asm/io.h
new file mode 100644
index 0000000..41e6bd4
--- /dev/null
+++ b/arch/nios2/include/asm/io.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#ifndef __ASM_NIOS2_IO_H_
+#define __ASM_NIOS2_IO_H_
+
+static inline void sync(void)
+{
+	__asm__ __volatile__ ("sync" : : : "memory");
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	1
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	if (flags)
+		return (void *)(paddr | gd->arch.io_region_base);
+	else
+		return (void *)(paddr | gd->arch.mem_region_base);
+}
+#define map_physmem map_physmem
+
+static inline void *phys_to_virt(phys_addr_t paddr)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	return (void *)(paddr | gd->arch.mem_region_base);
+}
+#define phys_to_virt phys_to_virt
+
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	return (phys_addr_t)vaddr & gd->arch.physaddr_mask;
+}
+#define virt_to_phys virt_to_phys
+
+#define __raw_writeb(v,a)       (*(volatile unsigned char  *)(a) = (v))
+#define __raw_writew(v,a)       (*(volatile unsigned short *)(a) = (v))
+#define __raw_writel(v,a)       (*(volatile unsigned int   *)(a) = (v))
+
+#define __raw_readb(a)          (*(volatile unsigned char  *)(a))
+#define __raw_readw(a)          (*(volatile unsigned short *)(a))
+#define __raw_readl(a)          (*(volatile unsigned int   *)(a))
+
+#define readb(addr)\
+	({unsigned char val;\
+	 asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
+#define readw(addr)\
+	({unsigned short val;\
+	 asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
+#define readl(addr)\
+	({unsigned long val;\
+	 asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
+
+#define writeb(val,addr)\
+	asm volatile ("stbio %0, 0(%1)" : : "r" (val), "r" (addr))
+#define writew(val,addr)\
+	asm volatile ("sthio %0, 0(%1)" : : "r" (val), "r" (addr))
+#define writel(val,addr)\
+	asm volatile ("stwio %0, 0(%1)" : : "r" (val), "r" (addr))
+
+#define inb(addr)	readb(addr)
+#define inw(addr)	readw(addr)
+#define inl(addr)	readl(addr)
+#define outb(val, addr)	writeb(val,addr)
+#define outw(val, addr)	writew(val,addr)
+#define outl(val, addr)	writel(val,addr)
+
+static inline void insb (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned char *p = dst;
+	while (count--) *p++ = inb (port);
+}
+static inline void insw (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned short *p = dst;
+	while (count--) *p++ = inw (port);
+}
+static inline void insl (unsigned long port, void *dst, unsigned long count)
+{
+	unsigned long *p = dst;
+	while (count--) *p++ = inl (port);
+}
+
+static inline void outsb (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned char *p = src;
+	while (count--) outb (*p++, port);
+}
+
+static inline void outsw (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned short *p = src;
+	while (count--) outw (*p++, port);
+}
+static inline void outsl (unsigned long port, const void *src, unsigned long count)
+{
+	const unsigned long *p = src;
+	while (count--) outl (*p++, port);
+}
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define out_arch(type,endian,a,v)	__raw_write##type(cpu_to_##endian(v),a)
+#define in_arch(type,endian,a)		endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a,v)	out_arch(l,le32,a,v)
+#define out_le16(a,v)	out_arch(w,le16,a,v)
+
+#define in_le32(a)	in_arch(l,le32,a)
+#define in_le16(a)	in_arch(w,le16,a)
+
+#define out_be32(a,v)	out_arch(l,be32,a,v)
+#define out_be16(a,v)	out_arch(w,be16,a,v)
+
+#define in_be32(a)	in_arch(l,be32,a)
+#define in_be16(a)	in_arch(w,be16,a)
+
+#define out_8(a,v)	__raw_writeb(v,a)
+#define in_8(a)		__raw_readb(a)
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+#define memset_io(a, b, c)		memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)		memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)		memcpy((void *)(a), (b), (c))
+
+#include <asm-generic/io.h>
+
+#endif /* __ASM_NIOS2_IO_H_ */
diff --git a/arch/nios2/include/asm/linkage.h b/arch/nios2/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/nios2/include/asm/linkage.h
diff --git a/arch/nios2/include/asm/nios2.h b/arch/nios2/include/asm/nios2.h
new file mode 100644
index 0000000..0872dd6
--- /dev/null
+++ b/arch/nios2/include/asm/nios2.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#ifndef __ASM_NIOS2_H__
+#define __ASM_NIOS2_H__
+
+/*------------------------------------------------------------------------
+ * Control registers -- use with wrctl() & rdctl()
+ *----------------------------------------------------------------------*/
+#define CTL_STATUS	0		/* Processor status reg		*/
+#define CTL_ESTATUS	1		/* Exception status reg		*/
+#define CTL_BSTATUS	2		/* Break status reg		*/
+#define CTL_IENABLE	3		/* Interrut enable reg		*/
+#define CTL_IPENDING	4		/* Interrut pending reg		*/
+
+/*------------------------------------------------------------------------
+ * Access to control regs
+ *----------------------------------------------------------------------*/
+
+#define rdctl(reg) __builtin_rdctl(reg)
+#define wrctl(reg, val) __builtin_wrctl(reg, val)
+
+/*------------------------------------------------------------------------
+ * Control reg bit masks
+ *----------------------------------------------------------------------*/
+#define STATUS_IE	(1<<0)		/* Interrupt enable		*/
+#define STATUS_U	(1<<1)		/* User-mode			*/
+
+/*------------------------------------------------------------------------
+ * Bit-31 Cache bypass -- only valid for data access. When data cache
+ * is not implemented, bit 31 is ignored for compatibility.
+ *----------------------------------------------------------------------*/
+#define CACHE_BYPASS(a) ((a) | 0x80000000)
+#define CACHE_NO_BYPASS(a) ((a) & ~0x80000000)
+
+#endif /* __ASM_NIOS2_H__ */
diff --git a/arch/nios2/include/asm/opcodes.h b/arch/nios2/include/asm/opcodes.h
new file mode 100644
index 0000000..346cefa
--- /dev/null
+++ b/arch/nios2/include/asm/opcodes.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#ifndef __ASM_NIOS2_OPCODES_H_
+#define __ASM_NIOS2_OPCODES_H_
+
+#define OPCODE_OP(inst)	((inst) & 0x3f)
+#define OPCODE_OPX(inst) (((inst)>>11) & 0x3f)
+#define OPCODE_RA(inst) (((inst)>>27) & 01f)
+#define OPCODE_RB(inst) (((inst)>>22) & 01f)
+#define OPCODE_RC(inst) (((inst)>>17) & 01f)
+
+/* I-TYPE (immediate) and J-TYPE (jump) opcodes
+ */
+#define OPCODE_CALL	0x00
+#define OPCODE_LDBU	0x03
+#define OPCODE_ADDI	0x04
+#define OPCODE_STB	0x05
+#define OPCODE_BR	0x06
+#define OPCODE_LDB	0x07
+#define OPCODE_CMPGEI	0x08
+#define OPCODE_LDHU	0x0B
+#define OPCODE_ANDI	0x0C
+#define OPCODE_STH	0x0D
+#define OPCODE_BGE	0x0E
+#define OPCODE_LDH	0x0F
+#define OPCODE_CMPLTI	0x10
+#define OPCODE_XORI	0x1C
+#define OPCODE_ORI	0x14
+#define OPCODE_STW	0x15
+#define OPCODE_BLT	0x16
+#define OPCODE_LDW	0x17
+#define OPCODE_CMPNEI	0x18
+#define OPCODE_BNE	0x1E
+#define OPCODE_CMPEQI	0x20
+#define OPCODE_LDBUIO	0x23
+#define OPCODE_MULI	0x24
+#define OPCODE_STBIO	0x25
+#define OPCODE_BEQ	0x26
+#define OPCODE_LDBIO	0x27
+#define OPCODE_CMPGEUI	0x28
+#define OPCODE_ANDHI	0x2C
+#define OPCODE_STHIO	0x2D
+#define OPCODE_BGEU	0x2E
+#define OPCODE_LDHIO	0x2F
+#define OPCODE_CMPLTUI	0x30
+#define OPCODE_CUSTOM	0x32
+#define OPCODE_INITD	0x33
+#define OPCODE_ORHI	0x34
+#define OPCODE_STWIO	0x35
+#define OPCODE_BLTU	0x36
+#define OPCODE_LDWIO	0x37
+#define OPCODE_RTYPE	0x3A
+#define OPCODE_LDHUIO	0x2B
+#define OPCODE_FLUSHD	0x3B
+#define OPCODE_XORHI	0x3C
+
+/* R-Type (register) OPX field encodings
+ */
+#define OPCODE_ERET	0x01
+#define OPCODE_ROLI	0x02
+#define OPCODE_ROL	0x03
+#define OPCODE_FLUSHP	0x04
+#define OPCODE_RET	0x05
+#define OPCODE_NOR	0x06
+#define OPCODE_MULXUU	0x07
+#define OPCODE_CMPGE	0x08
+#define OPCODE_BRET	0x09
+#define OPCODE_ROR	0x0B
+#define OPCODE_FLUSHI	0x0C
+#define OPCODE_JMP	0x0D
+#define OPCODE_AND	0x0E
+
+#define OPCODE_CMPLT	0x10
+#define OPCODE_SLLI	0x12
+#define OPCODE_SLL	0x13
+#define OPCODE_OR	0x16
+#define OPCODE_MULXSU	0x17
+#define OPCODE_CMPNE	0x18
+#define OPCODE_SRLI	0x1A
+#define OPCODE_SRL	0x1B
+#define OPCODE_NEXTPC	0x1C
+#define OPCODE_CALLR	0x1D
+#define OPCODE_XOR	0x1E
+#define OPCODE_MULXSS	0x1F
+
+#define OPCODE_CMPEQ	0x20
+#define OPCODE_CMPLTU	0x30
+#define OPCODE_ADD	0x31
+#define OPCODE_DIVU	0x24
+#define OPCODE_DIV	0x25
+#define OPCODE_RDCTL	0x26
+#define OPCODE_MUL	0x27
+#define OPCODE_CMPGEU	0x28
+#define OPCODE_TRAP	0x2D
+#define OPCODE_WRCTL	0x2E
+
+#define OPCODE_BREAK	0x34
+#define OPCODE_SYNC	0x36
+#define OPCODE_INITI	0x29
+#define OPCODE_SUB	0x39
+#define OPCODE_SRAI	0x3A
+#define OPCODE_SRA	0x3B
+
+/*Full instruction encodings for R-Type, without the R's ;-)
+ *
+ * TODO: BREAK, BRET, ERET, RET, SYNC (as needed)
+ */
+#define OPC_TRAP	0x003b683a
+
+#endif /* __ASM_NIOS2_OPCODES_H_ */
diff --git a/arch/nios2/include/asm/posix_types.h b/arch/nios2/include/asm/posix_types.h
new file mode 100644
index 0000000..6b6c39b
--- /dev/null
+++ b/arch/nios2/include/asm/posix_types.h
@@ -0,0 +1,67 @@
+#ifndef __ASM_NIOS2_POSIX_TYPES_H_
+#define __ASM_NIOS2_POSIX_TYPES_H_
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short	__kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned short	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid_t;
+typedef unsigned short	__kernel_gid_t;
+#ifdef __GNUC__
+typedef __SIZE_TYPE__	__kernel_size_t;
+#else
+typedef unsigned long	__kernel_size_t;
+#endif
+typedef long		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+
+#undef	__FD_CLR
+#define	__FD_CLR(d, set)	((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+
+#undef	__FD_ISSET
+#define	__FD_ISSET(d, set)	((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __ASM_NIOS2_POSIX_TYPES_H_ */
diff --git a/arch/nios2/include/asm/processor.h b/arch/nios2/include/asm/processor.h
new file mode 100644
index 0000000..2ac4a4b
--- /dev/null
+++ b/arch/nios2/include/asm/processor.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#ifndef __ASM_NIOS2_PROCESSOR_H_
+#define __ASM_NIOS2_PROCESSOR_H_
+#endif /* __ASM_NIOS2_PROCESSOR_H_ */
diff --git a/arch/nios2/include/asm/ptrace.h b/arch/nios2/include/asm/ptrace.h
new file mode 100644
index 0000000..317d8ae
--- /dev/null
+++ b/arch/nios2/include/asm/ptrace.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+
+#ifndef __ASM_NIOS2_PTRACE_H_
+#define __ASM_NIOS2_PTRACE_H_
+
+struct pt_regs {
+	unsigned reg[32];
+	unsigned status;
+};
+
+
+#endif /* __ASM_NIOS2_PTRACE_H_ */
diff --git a/arch/nios2/include/asm/sections.h b/arch/nios2/include/asm/sections.h
new file mode 100644
index 0000000..2b8c516
--- /dev/null
+++ b/arch/nios2/include/asm/sections.h
@@ -0,0 +1 @@
+#include <asm-generic/sections.h>
diff --git a/arch/nios2/include/asm/string.h b/arch/nios2/include/asm/string.h
new file mode 100644
index 0000000..69f4921
--- /dev/null
+++ b/arch/nios2/include/asm/string.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+#ifndef __ASM_NIOS2_STRING_H_
+#define __ASM_NIOS2_STRING_H_
+
+#undef __HAVE_ARCH_STRRCHR
+extern char * strrchr(const char * s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char * strchr(const char * s, int c);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void * memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMSET
+extern void * memset(void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+extern void memzero(void *ptr, __kernel_size_t n);
+
+#endif /* __ASM_NIOS2_STRING_H_ */
diff --git a/arch/nios2/include/asm/system.h b/arch/nios2/include/asm/system.h
new file mode 100644
index 0000000..33614d5
--- /dev/null
+++ b/arch/nios2/include/asm/system.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ */
+#ifndef __ASM_NIOS2_SYSTEM_H_
+#define __ASM_NIOS2_SYSTEM_H_
+
+#define local_irq_enable() __asm__ __volatile__ (  \
+	"rdctl	r8, status\n"			   \
+	"ori	r8, r8, 1\n"			   \
+	"wrctl	status, r8\n"			   \
+	: : : "r8")
+
+#define local_irq_disable() __asm__ __volatile__ ( \
+	"rdctl	r8, status\n"			   \
+	"andi	r8, r8, 0xfffe\n"		   \
+	"wrctl	status, r8\n"			   \
+	: : : "r8")
+
+#define local_save_flags(x) __asm__ __volatile__ (	\
+	"rdctl	r8, status\n"				\
+	"mov	%0, r8\n"				\
+	: "=r" (x) : : "r8", "memory")
+
+#define local_irq_restore(x) __asm__ __volatile__ (	\
+	"mov	r8, %0\n"				\
+	"wrctl	status, r8\n"				\
+	: : "r" (x) : "r8", "memory")
+
+/* For spinlocks etc */
+#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } \
+	while (0)
+
+#define	irqs_disabled()					\
+({							\
+	unsigned long flags;				\
+	local_save_flags(flags);			\
+	((flags & NIOS2_STATUS_PIE_MSK) == 0x0);	\
+})
+
+/* indirect call to go beyond 256MB limitation of toolchain */
+#define nios2_callr(addr) __asm__ __volatile__ (	\
+	"callr	%0"					\
+	: : "r" (addr))
+
+void display_sysid(void);
+
+#endif /* __ASM_NIOS2_SYSTEM_H */
diff --git a/arch/nios2/include/asm/types.h b/arch/nios2/include/asm/types.h
new file mode 100644
index 0000000..ea859c0
--- /dev/null
+++ b/arch/nios2/include/asm/types.h
@@ -0,0 +1,60 @@
+#ifndef __ASM_NIOS2_TYPES_H_
+#define __ASM_NIOS2_TYPES_H_
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_NIOS2_TYPES_H */
diff --git a/arch/nios2/include/asm/u-boot.h b/arch/nios2/include/asm/u-boot.h
new file mode 100644
index 0000000..f050067
--- /dev/null
+++ b/arch/nios2/include/asm/u-boot.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __ASM_NIOS2_U_BOOT_H_
+#define __ASM_NIOS2_U_BOOT_H_
+
+#include <asm-generic/u-boot.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_NIOS2
+
+#endif	/* __ASM_NIOS2_U_BOOT_H_ */
diff --git a/arch/nios2/include/asm/unaligned.h b/arch/nios2/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/nios2/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/clock.h b/arch/powerpc/include/asm/arch-mpc83xx/clock.h
new file mode 100644
index 0000000..d57e93c
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc83xx/clock.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_POWERPC_CLOCK_H
+#define __ASM_POWERPC_CLOCK_H
+
+/* Make fsl_esdhc driver happy */
+enum mxc_clock {
+	MXC_ESDHC_CLK,
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+uint mxc_get_clock(int clk)
+{
+	return gd->arch.sdhc_clk;
+}
+#endif /* __ASM_POWERPC_CLOCK_H */
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
new file mode 100644
index 0000000..385d651
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _MPC83XX_GPIO_H_
+#define _MPC83XX_GPIO_H_
+
+/*
+ * The MCP83xx's 1-2 GPIO controllers each with 32 bits.
+ */
+#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
+	defined(CONFIG_ARCH_MPC8315)
+#define MPC83XX_GPIO_CTRLRS 1
+#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+#define MPC83XX_GPIO_CTRLRS 2
+#else
+#define MPC83XX_GPIO_CTRLRS 0
+#endif
+
+#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS)
+
+struct mpc8xxx_gpio_plat {
+       ulong addr;
+       unsigned long size;
+       uint ngpios;
+};
+
+#ifndef DM_GPIO
+void mpc83xx_gpio_init_f(void);
+void mpc83xx_gpio_init_r(void);
+#endif	/* DM_GPIO */
+
+#endif	/* MPC83XX_GPIO_H_ */
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/soc.h b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
new file mode 100644
index 0000000..39bf7d5
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef _MPC83XX_SOC_H_
+#define _MPC83XX_SOC_H_
+
+enum soc_type {
+	SOC_MPC8308,
+	SOC_MPC8309,
+	SOC_MPC8313,
+	SOC_MPC8315,
+	SOC_MPC832X,
+	SOC_MPC8349,
+	SOC_MPC8360,
+	SOC_MPC8379,
+};
+
+bool mpc83xx_has_sdhc(int type)
+{
+	return (type == SOC_MPC8308) ||
+	       (type == SOC_MPC8309) ||
+	       (type == SOC_MPC8379);
+}
+
+bool mpc83xx_has_tsec(int type)
+{
+	return (type == SOC_MPC8308) ||
+	       (type == SOC_MPC8313) ||
+	       (type == SOC_MPC8315) ||
+	       (type == SOC_MPC8349) ||
+	       (type == SOC_MPC8379);
+}
+
+bool mpc83xx_has_pcie1(int type)
+{
+	return (type == SOC_MPC8308) ||
+	       (type == SOC_MPC8315) ||
+	       (type == SOC_MPC8379);
+}
+
+bool mpc83xx_has_pcie2(int type)
+{
+	return (type == SOC_MPC8315) ||
+	       (type == SOC_MPC8379);
+}
+
+bool mpc83xx_has_sata(int type)
+{
+	return (type == SOC_MPC8315) ||
+	       (type == SOC_MPC8379);
+}
+
+bool mpc83xx_has_pci(int type)
+{
+	return type != SOC_MPC8308;
+}
+
+bool mpc83xx_has_second_i2c(int type)
+{
+	return (type != SOC_MPC8315) &&
+	       (type != SOC_MPC832X);
+}
+
+bool mpc83xx_has_quicc_engine(int type)
+{
+	return (type == SOC_MPC8309) ||
+	       (type == SOC_MPC832X) ||
+	       (type == SOC_MPC8360);
+}
+
+#endif /* _MPC83XX_SOC_H_ */
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
new file mode 100644
index 0000000..c7086a8
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_MX85XX_GPIO_H
+#define __ASM_ARCH_MX85XX_GPIO_H
+
+#ifndef CONFIG_MPC85XX_GPIO
+#include <asm/mpc85xx_gpio.h>
+#endif
+
+struct mpc8xxx_gpio_plat {
+	ulong addr;
+	unsigned long size;
+	uint ngpios;
+};
+
+#endif
diff --git a/arch/powerpc/include/asm/arch-ppc4xx/gpio.h b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h
new file mode 100644
index 0000000..e74a2e1
--- /dev/null
+++ b/arch/powerpc/include/asm/arch-ppc4xx/gpio.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 Google, Inc
+ */
+
+/* This is empty for now as we don't support the generic GPIO interface */
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
new file mode 100644
index 0000000..87efcca
--- /dev/null
+++ b/arch/powerpc/include/asm/atomic.h
@@ -0,0 +1,93 @@
+/*
+ * PowerPC atomic operations
+ */
+
+#ifndef _ASM_PPC_ATOMIC_H_
+#define _ASM_PPC_ATOMIC_H_
+
+#ifdef CONFIG_SMP
+typedef struct { volatile int counter; } atomic_t;
+#else
+typedef struct { int counter; } atomic_t;
+#endif
+
+#define ATOMIC_INIT(i)	{ (i) }
+
+#define atomic_read(v)		((v)->counter)
+#define atomic_set(v,i)		(((v)->counter) = (i))
+
+extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
+extern void atomic_set_mask(unsigned long mask, unsigned long *addr);
+
+static __inline__ int atomic_add_return(int a, atomic_t *v)
+{
+	int t;
+
+	__asm__ __volatile__("\n\
+1:	lwarx	%0,0,%3\n\
+	add	%0,%2,%0\n\
+	stwcx.	%0,0,%3\n\
+	bne-	1b"
+	: "=&r" (t), "=m" (*v)
+	: "r" (a), "r" (v), "m" (*v)
+	: "cc");
+
+	return t;
+}
+
+static __inline__ int atomic_sub_return(int a, atomic_t *v)
+{
+	int t;
+
+	__asm__ __volatile__("\n\
+1:	lwarx	%0,0,%3\n\
+	subf	%0,%2,%0\n\
+	stwcx.	%0,0,%3\n\
+	bne-	1b"
+	: "=&r" (t), "=m" (*v)
+	: "r" (a), "r" (v), "m" (*v)
+	: "cc");
+
+	return t;
+}
+
+static __inline__ int atomic_inc_return(atomic_t *v)
+{
+	int t;
+
+	__asm__ __volatile__("\n\
+1:	lwarx	%0,0,%2\n\
+	addic	%0,%0,1\n\
+	stwcx.	%0,0,%2\n\
+	bne-	1b"
+	: "=&r" (t), "=m" (*v)
+	: "r" (v), "m" (*v)
+	: "cc");
+
+	return t;
+}
+
+static __inline__ int atomic_dec_return(atomic_t *v)
+{
+	int t;
+
+	__asm__ __volatile__("\n\
+1:	lwarx	%0,0,%2\n\
+	addic	%0,%0,-1\n\
+	stwcx.	%0,0,%2\n\
+	bne	1b"
+	: "=&r" (t), "=m" (*v)
+	: "r" (v), "m" (*v)
+	: "cc");
+
+	return t;
+}
+
+#define atomic_add(a, v)		((void) atomic_add_return((a), (v)))
+#define atomic_sub(a, v)		((void) atomic_sub_return((a), (v)))
+#define atomic_sub_and_test(a, v)	(atomic_sub_return((a), (v)) == 0)
+#define atomic_inc(v)			((void) atomic_inc_return((v)))
+#define atomic_dec(v)			((void) atomic_dec_return((v)))
+#define atomic_dec_and_test(v)		(atomic_dec_return((v)) == 0)
+
+#endif /* _ASM_PPC_ATOMIC_H_ */
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
new file mode 100644
index 0000000..96491b6
--- /dev/null
+++ b/arch/powerpc/include/asm/bitops.h
@@ -0,0 +1,370 @@
+/*
+ * bitops.h: Bit string operations on the ppc
+ */
+
+#ifndef _PPC_BITOPS_H
+#define _PPC_BITOPS_H
+
+#include <asm/byteorder.h>
+#include <asm-generic/bitops/__ffs.h>
+
+/*
+ * Arguably these bit operations don't imply any memory barrier or
+ * SMP ordering, but in fact a lot of drivers expect them to imply
+ * both, since they do on x86 cpus.
+ */
+#ifdef CONFIG_SMP
+#define SMP_WMB		"eieio\n"
+#define SMP_MB		"\nsync"
+#else
+#define SMP_WMB
+#define SMP_MB
+#endif /* CONFIG_SMP */
+
+#define __INLINE_BITOPS	1
+
+#if __INLINE_BITOPS
+/*
+ * These used to be if'd out here because using : "cc" as a constraint
+ * resulted in errors from egcs.  Things may be OK with gcc-2.95.
+ */
+static __inline__ void set_bit(int nr, volatile void * addr)
+{
+	unsigned long old;
+	unsigned long mask = 1 << (nr & 0x1f);
+	unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%3\n\
+	or	%0,%0,%2\n\
+	stwcx.	%0,0,%3\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc" );
+}
+
+static __inline__ void clear_bit(int nr, volatile void *addr)
+{
+	unsigned long old;
+	unsigned long mask = 1 << (nr & 0x1f);
+	unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%3\n\
+	andc	%0,%0,%2\n\
+	stwcx.	%0,0,%3\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc");
+}
+
+static __inline__ void change_bit(int nr, volatile void *addr)
+{
+	unsigned long old;
+	unsigned long mask = 1 << (nr & 0x1f);
+	unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%3\n\
+	xor	%0,%0,%2\n\
+	stwcx.	%0,0,%3\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc");
+}
+
+static __inline__ int test_and_set_bit(int nr, volatile void *addr)
+{
+	unsigned int old, t;
+	unsigned int mask = 1 << (nr & 0x1f);
+	volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%4\n\
+	or	%1,%0,%3\n\
+	stwcx.	%1,0,%4\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=&r" (t), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc");
+
+	return (old & mask) != 0;
+}
+
+static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
+{
+	unsigned int old, t;
+	unsigned int mask = 1 << (nr & 0x1f);
+	volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%4\n\
+	andc	%1,%0,%3\n\
+	stwcx.	%1,0,%4\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=&r" (t), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc");
+
+	return (old & mask) != 0;
+}
+
+static __inline__ int test_and_change_bit(int nr, volatile void *addr)
+{
+	unsigned int old, t;
+	unsigned int mask = 1 << (nr & 0x1f);
+	volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
+
+	__asm__ __volatile__(SMP_WMB "\
+1:	lwarx	%0,0,%4\n\
+	xor	%1,%0,%3\n\
+	stwcx.	%1,0,%4\n\
+	bne	1b"
+	SMP_MB
+	: "=&r" (old), "=&r" (t), "=m" (*p)
+	: "r" (mask), "r" (p), "m" (*p)
+	: "cc");
+
+	return (old & mask) != 0;
+}
+#endif /* __INLINE_BITOPS */
+
+static __inline__ int test_bit(int nr, __const__ volatile void *addr)
+{
+	__const__ unsigned int *p = (__const__ unsigned int *) addr;
+
+	return ((p[nr >> 5] >> (nr & 0x1f)) & 1) != 0;
+}
+
+/* Return the bit position of the most significant 1 bit in a word */
+/* - the result is undefined when x == 0 */
+static __inline__ int __ilog2(unsigned int x)
+{
+	int lz;
+
+	asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
+	return 31 - lz;
+}
+
+static __inline__ int ffz(unsigned int x)
+{
+	if ((x = ~x) == 0)
+		return 32;
+	return __ilog2(x & -x);
+}
+
+/*
+ * fls: find last (most-significant) bit set.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ *
+ * On powerpc, __ilog2(0) returns -1, but this is not safe in general
+ */
+static __inline__ int fls(unsigned int x)
+{
+	return __ilog2(x) + 1;
+}
+#define PLATFORM_FLS
+
+/**
+ * fls64 - find last set bit in a 64-bit word
+ * @x: the word to search
+ *
+ * This is defined in a similar way as the libc and compiler builtin
+ * ffsll, but returns the position of the most significant set bit.
+ *
+ * fls64(value) returns 0 if value is 0 or the position of the last
+ * set bit if value is nonzero. The last (most significant) bit is
+ * at position 64.
+ */
+#if BITS_PER_LONG == 32
+static inline int fls64(__u64 x)
+{
+	__u32 h = x >> 32;
+	if (h)
+		return fls(h) + 32;
+	return fls(x);
+}
+#elif BITS_PER_LONG == 64
+static inline int fls64(__u64 x)
+{
+	if (x == 0)
+		return 0;
+	return __ilog2(x) + 1;
+}
+#else
+#error BITS_PER_LONG not 32 or 64
+#endif
+
+#ifdef __KERNEL__
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static __inline__ int ffs(int x)
+{
+	return __ilog2(x & -x) + 1;
+}
+#define PLATFORM_FFS
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+/*
+ * This implementation of find_{first,next}_zero_bit was stolen from
+ * Linus' asm-alpha/bitops.h.
+ */
+#define find_first_zero_bit(addr, size) \
+	find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long find_next_zero_bit(void * addr,
+	unsigned long size, unsigned long offset)
+{
+	unsigned int * p = ((unsigned int *) addr) + (offset >> 5);
+	unsigned int result = offset & ~31UL;
+	unsigned int tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = *p++;
+		tmp |= ~0UL >> (32-offset);
+		if (size < 32)
+			goto found_first;
+		if (tmp != ~0U)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size >= 32) {
+		if ((tmp = *p++) != ~0U)
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+found_first:
+	tmp |= ~0UL << size;
+found_middle:
+	return result + ffz(tmp);
+}
+
+
+#define _EXT2_HAVE_ASM_BITOPS_
+
+#ifdef __KERNEL__
+/*
+ * test_and_{set,clear}_bit guarantee atomicity without
+ * disabling interrupts.
+ */
+#define ext2_set_bit(nr, addr)		test_and_set_bit((nr) ^ 0x18, addr)
+#define ext2_clear_bit(nr, addr)	test_and_clear_bit((nr) ^ 0x18, addr)
+
+#else
+static __inline__ int ext2_set_bit(int nr, void * addr)
+{
+	int		mask;
+	unsigned char	*ADDR = (unsigned char *) addr;
+	int oldbit;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	oldbit = (*ADDR & mask) ? 1 : 0;
+	*ADDR |= mask;
+	return oldbit;
+}
+
+static __inline__ int ext2_clear_bit(int nr, void * addr)
+{
+	int		mask;
+	unsigned char	*ADDR = (unsigned char *) addr;
+	int oldbit;
+
+	ADDR += nr >> 3;
+	mask = 1 << (nr & 0x07);
+	oldbit = (*ADDR & mask) ? 1 : 0;
+	*ADDR = *ADDR & ~mask;
+	return oldbit;
+}
+#endif	/* __KERNEL__ */
+
+static __inline__ int ext2_test_bit(int nr, __const__ void * addr)
+{
+	__const__ unsigned char	*ADDR = (__const__ unsigned char *) addr;
+
+	return (ADDR[nr >> 3] >> (nr & 7)) & 1;
+}
+
+/*
+ * This implementation of ext2_find_{first,next}_zero_bit was stolen from
+ * Linus' asm-alpha/bitops.h and modified for a big-endian machine.
+ */
+
+#define ext2_find_first_zero_bit(addr, size) \
+	ext2_find_next_zero_bit((addr), (size), 0)
+
+static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
+	unsigned long size, unsigned long offset)
+{
+	unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
+	unsigned int result = offset & ~31UL;
+	unsigned int tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 31UL;
+	if (offset) {
+		tmp = cpu_to_le32p(p++);
+		tmp |= ~0UL >> (32-offset);
+		if (size < 32)
+			goto found_first;
+		if (tmp != ~0U)
+			goto found_middle;
+		size -= 32;
+		result += 32;
+	}
+	while (size >= 32) {
+		if ((tmp = cpu_to_le32p(p++)) != ~0U)
+			goto found_middle;
+		result += 32;
+		size -= 32;
+	}
+	if (!size)
+		return result;
+	tmp = cpu_to_le32p(p);
+found_first:
+	tmp |= ~0U << size;
+found_middle:
+	return result + ffz(tmp);
+}
+
+/* Bitmap functions for the minix filesystem.  */
+#define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr))
+#define minix_test_and_clear_bit(nr,addr) ext2_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) ext2_test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size)
+
+#endif /* _PPC_BITOPS_H */
diff --git a/arch/powerpc/include/asm/byteorder.h b/arch/powerpc/include/asm/byteorder.h
new file mode 100644
index 0000000..f731d18
--- /dev/null
+++ b/arch/powerpc/include/asm/byteorder.h
@@ -0,0 +1,84 @@
+#ifndef _PPC_BYTEORDER_H
+#define _PPC_BYTEORDER_H
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+static __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+{
+	unsigned val;
+
+	__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
+	return val;
+}
+
+static __inline__ void st_le16(volatile unsigned short *addr, const unsigned val)
+{
+	__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
+}
+
+static __inline__ unsigned ld_le32(const volatile unsigned *addr)
+{
+	unsigned val;
+
+	__asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
+	return val;
+}
+
+static __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+{
+	__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
+}
+
+/* alas, egcs sounds like it has a bug in this code that doesn't use the
+   inline asm correctly, and can cause file corruption. Until I hear that
+   it's fixed, I can live without the extra speed. I hope. */
+#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
+#if 0
+#  define __arch_swab16(x) ld_le16(&x)
+#  define __arch_swab32(x) ld_le32(&x)
+#else
+static __inline__ __attribute__((const)) __u16 ___arch__swab16(__u16 value)
+{
+	__u16 result;
+
+	__asm__("rlwimi %0,%1,8,16,23"
+	    : "=r" (result)
+	    : "r" (value), "0" (value >> 8));
+	return result;
+}
+
+static __inline__ __attribute__((const)) __u32 ___arch__swab32(__u32 value)
+{
+	__u32 result;
+
+	__asm__("rlwimi %0,%1,24,16,23\n\t"
+	    "rlwimi %0,%1,8,8,15\n\t"
+	    "rlwimi %0,%1,24,0,7"
+	    : "=r" (result)
+	    : "r" (value), "0" (value >> 24));
+	return result;
+}
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+#endif /* 0 */
+
+#endif
+
+/* The same, but returns converted value from the location pointer by addr. */
+#define __arch__swab16p(addr) ld_le16(addr)
+#define __arch__swab32p(addr) ld_le32(addr)
+
+/* The same, but do the conversion in situ, ie. put the value back to addr. */
+#define __arch__swab16s(addr) st_le16(addr,*addr)
+#define __arch__swab32s(addr) st_le32(addr,*addr)
+
+#endif /* __GNUC__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#define __BYTEORDER_HAS_U64__
+#endif
+#include <linux/byteorder/big_endian.h>
+
+#endif /* _PPC_BYTEORDER_H */
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
new file mode 100644
index 0000000..445a366
--- /dev/null
+++ b/arch/powerpc/include/asm/cache.h
@@ -0,0 +1,144 @@
+/*
+ * include/asm-ppc/cache.h
+ */
+#ifndef __ARCH_PPC_CACHE_H
+#define __ARCH_PPC_CACHE_H
+
+#include <asm/processor.h>
+
+/* bytes per L1 cache line */
+#if defined(CONFIG_MPC8xx)
+#define	L1_CACHE_SHIFT	4
+#elif defined(CONFIG_PPC64BRIDGE)
+#define L1_CACHE_SHIFT	7
+#elif defined(CONFIG_E500MC)
+#define L1_CACHE_SHIFT	6
+#else
+#define	L1_CACHE_SHIFT	5
+#endif
+
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
+
+/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on PowerPC.
+ */
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+
+/*
+ * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
+ */
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE	L1_CACHE_BYTES
+#endif
+
+#define	L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
+#define	L1_CACHE_PAGES		8
+
+#define	SMP_CACHE_BYTES L1_CACHE_BYTES
+
+#ifdef MODULE
+#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
+#else
+#define __cacheline_aligned					\
+  __attribute__((__aligned__(L1_CACHE_BYTES),			\
+		 __section__(".data.cacheline_aligned")))
+#endif
+
+#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+extern void flush_dcache_range(unsigned long start, unsigned long stop);
+extern void clean_dcache_range(unsigned long start, unsigned long stop);
+extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
+extern void flush_dcache(void);
+extern void invalidate_dcache(void);
+extern void invalidate_icache(void);
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
+extern void unlock_ram_in_cache(void);
+#endif /* CONFIG_SYS_INIT_RAM_LOCK */
+#endif /* __ASSEMBLY__ */
+
+#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+int l2cache_init(void);
+void enable_cpc(void);
+void disable_cpc_sram(void);
+#endif
+
+/* prep registers for L2 */
+#define CACHECRBA       0x80000823      /* Cache configuration register address */
+#define L2CACHE_MASK	0x03	/* Mask for 2 L2 Cache bits */
+#define L2CACHE_512KB	0x00	/* 512KB */
+#define L2CACHE_256KB	0x01	/* 256KB */
+#define L2CACHE_1MB	0x02	/* 1MB */
+#define L2CACHE_NONE	0x03	/* NONE */
+#define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
+
+#ifdef CONFIG_MPC8xx
+/* Cache control on the MPC8xx is provided through some additional
+ * special purpose registers.
+ */
+#define IC_CST		560	/* Instruction cache control/status */
+#define IC_ADR		561	/* Address needed for some commands */
+#define IC_DAT		562	/* Read-only data register */
+#define DC_CST		568	/* Data cache control/status */
+#define DC_ADR		569	/* Address needed for some commands */
+#define DC_DAT		570	/* Read-only data register */
+
+/* Commands.  Only the first few are available to the instruction cache.
+*/
+#define	IDC_ENABLE	0x02000000	/* Cache enable */
+#define IDC_DISABLE	0x04000000	/* Cache disable */
+#define IDC_LDLCK	0x06000000	/* Load and lock */
+#define IDC_UNLINE	0x08000000	/* Unlock line */
+#define IDC_UNALL	0x0a000000	/* Unlock all */
+#define IDC_INVALL	0x0c000000	/* Invalidate all */
+
+#define DC_FLINE	0x0e000000	/* Flush data cache line */
+#define DC_SFWT		0x01000000	/* Set forced writethrough mode */
+#define DC_CFWT		0x03000000	/* Clear forced writethrough mode */
+#define DC_SLES		0x05000000	/* Set little endian swap mode */
+#define DC_CLES		0x07000000	/* Clear little endian swap mode */
+
+/* Status.
+*/
+#define IDC_ENABLED	0x80000000	/* Cache is enabled */
+#define IDC_CERR1	0x00200000	/* Cache error 1 */
+#define IDC_CERR2	0x00100000	/* Cache error 2 */
+#define IDC_CERR3	0x00080000	/* Cache error 3 */
+
+#define DC_DFWT		0x40000000	/* Data cache is forced write through */
+#define DC_LES		0x20000000	/* Caches are little endian mode */
+
+#if !defined(__ASSEMBLY__)
+static inline uint rd_ic_cst(void)
+{
+	return mfspr(IC_CST);
+}
+
+static inline void wr_ic_cst(uint val)
+{
+	mtspr(IC_CST, val);
+}
+
+static inline void wr_ic_adr(uint val)
+{
+	mtspr(IC_ADR, val);
+}
+
+static inline uint rd_dc_cst(void)
+{
+	return mfspr(DC_CST);
+}
+
+static inline void wr_dc_cst(uint val)
+{
+	mtspr(DC_CST, val);
+}
+
+static inline void wr_dc_adr(uint val)
+{
+	mtspr(DC_ADR, val);
+}
+#endif
+#endif /* CONFIG_MPC8xx */
+
+#endif
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
new file mode 100644
index 0000000..c9c9964
--- /dev/null
+++ b/arch/powerpc/include/asm/config.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#ifdef CONFIG_MPC85xx
+#include <asm/config_mpc85xx.h>
+#endif
+
+#ifdef CONFIG_MPC86xx
+#include <asm/config_mpc86xx.h>
+#endif
+
+#ifndef HWCONFIG_BUFFER_SIZE
+  #define HWCONFIG_BUFFER_SIZE 256
+#endif
+
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#ifndef CONFIG_MAX_MEM_MAPPED
+#if	defined(CONFIG_E500)		|| \
+	defined(CONFIG_MPC86xx)		|| \
+	defined(CONFIG_E300)
+#define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
+#else
+#define CONFIG_MAX_MEM_MAPPED	(256 << 20)
+#endif
+#endif
+
+/* Check if boards need to enable FSL DMA engine for SDRAM init */
+#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
+#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
+	((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
+	!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
+#define CONFIG_FSL_DMA
+#endif
+#endif
+
+/*
+ * Provide a default boot page translation virtual address that lines up with
+ * Freescale's default e500 reset page.
+ */
+#if (defined(CONFIG_E500) && defined(CONFIG_MP))
+#ifndef CONFIG_BPTR_VIRT_ADDR
+#define CONFIG_BPTR_VIRT_ADDR	0xfffff000
+#endif
+#endif
+
+/* Since so many PPC SOCs have a semi-common LBC, define this here */
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_MPC83xx)
+#if !defined(CONFIG_FSL_IFC)
+#define CONFIG_FSL_LBC
+#endif
+#endif
+
+/* The TSEC driver uses the PHYLIB infrastructure */
+#if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
+#include <config_phylib_all_drivers.h>
+#endif /* TSEC_ENET */
+
+/* The FMAN driver uses the PHYLIB infrastructure */
+
+/* All PPC boards must swap IDE bytes */
+#define CONFIG_IDE_SWAP_IO
+
+#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
+/*
+ * TODO: Convert this to a clock driver exists that can give us the UART
+ * clock here.
+ */
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#endif
+
+#endif /* _ASM_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
new file mode 100644
index 0000000..946e74a
--- /dev/null
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -0,0 +1,434 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_MPC85xx_CONFIG_H_
+#define _ASM_MPC85xx_CONFIG_H_
+
+/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
+
+/*
+ * This macro should be removed when we no longer care about backwards
+ * compatibility with older operating systems.
+ */
+#define CONFIG_PPC_SPINTABLE_COMPATIBLE
+
+#include <fsl_ddrc_version.h>
+
+/* IP endianness */
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SEC_MON_BE
+
+#if defined(CONFIG_ARCH_MPC8548)
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+
+#elif defined(CONFIG_ARCH_MPC8568)
+#define QE_MURAM_SIZE			0x10000UL
+#define MAX_QE_RISC			2
+#define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+
+#elif defined(CONFIG_ARCH_MPC8569)
+#define QE_MURAM_SIZE			0x20000UL
+#define MAX_QE_RISC			4
+#define QE_NUM_OF_SNUM			46
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	1
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+
+#elif defined(CONFIG_ARCH_P1010)
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_ESDHC_HC_BLK_ADDR
+
+/* P1011 is single core version of P1020 */
+#elif defined(CONFIG_ARCH_P1011)
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+
+#elif defined(CONFIG_ARCH_P1020)
+#define CONFIG_TSECV2
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#endif
+
+#elif defined(CONFIG_ARCH_P1021)
+#define CONFIG_TSECV2
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+
+#elif defined(CONFIG_ARCH_P1022)
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+
+#elif defined(CONFIG_ARCH_P1023)
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#define CONFIG_SYS_QMAN_NUM_PORTALS	3
+#define CONFIG_SYS_BMAN_NUM_PORTALS	3
+#define CONFIG_SYS_FM_MURAM_SIZE	0x10000
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+
+/* P1024 is lower end variant of P1020 */
+#elif defined(CONFIG_ARCH_P1024)
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+
+/* P1025 is lower end variant of P1021 */
+#elif defined(CONFIG_ARCH_P1025)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#define CONFIG_TSECV2
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
+
+#elif defined(CONFIG_ARCH_P2020)
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+
+#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+
+#elif defined(CONFIG_ARCH_P3041)
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+
+#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_NUM_FM1_DTSEC	4
+#define CONFIG_SYS_NUM_FM2_DTSEC	4
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_SYS_NUM_FM2_10GEC	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,p4080-pcie"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_RMU
+#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
+
+#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	32
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
+
+#elif defined(CONFIG_ARCH_P5040)
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	3
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_SYS_NUM_FM2_DTSEC	5
+#define CONFIG_SYS_NUM_FM2_10GEC	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+
+#elif defined(CONFIG_ARCH_BSC9131)
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_ESDHC_HC_BLK_ADDR
+
+#elif defined(CONFIG_ARCH_BSC9132)
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_TSECV2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#define CONFIG_SYS_FSL_DSP_DDR_ADDR	0x40000000
+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR	0xb0000000
+#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR	0xc0000000
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT	0xff600000
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
+#define CONFIG_ESDHC_HC_BLK_ADDR
+
+#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
+#define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#ifdef CONFIG_ARCH_T4240
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
+#define CONFIG_SYS_NUM_FM1_DTSEC	8
+#define CONFIG_SYS_NUM_FM1_10GEC	2
+#define CONFIG_SYS_NUM_FM2_DTSEC	8
+#define CONFIG_SYS_NUM_FM2_10GEC	2
+#else
+#define CONFIG_SYS_NUM_FM1_DTSEC	6
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_SYS_NUM_FM2_DTSEC	8
+#define CONFIG_SYS_NUM_FM2_10GEC	1
+#if defined(CONFIG_ARCH_T4160)
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 1 }
+#endif
+#endif
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	5
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_FSL_SRDS_3
+#define CONFIG_SYS_FSL_SRDS_4
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_SYS_PME_CLK		0
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM1_CLK		3
+#define CONFIG_SYS_FM2_CLK		3
+#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_SRIO_LIODN
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_PCI_VER_3_X
+
+#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#define CONFIG_HETROGENOUS_CLUSTERS     /* DSP/SC3900 core clusters */
+#define CONFIG_PPC_CLUSTER_START	0 /*Start index of ppc clusters*/
+#define CONFIG_DSP_CLUSTER_START	1 /*Start index of dsp clusters*/
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_MAPLE
+#define CONFIG_SYS_CPRI
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	5
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#define CONFIG_SYS_FM1_CLK		0
+#define CONFIG_SYS_CPRI_CLK		3
+#define CONFIG_SYS_ULB_CLK		4
+#define CONFIG_SYS_ETVPE_CLK		1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+
+#ifdef CONFIG_ARCH_B4860
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
+#define CONFIG_MAX_DSP_CPUS		12
+#define CONFIG_NUM_DSP_CPUS		6
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS	2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
+#define CONFIG_SYS_NUM_FM1_DTSEC	6
+#define CONFIG_SYS_NUM_FM1_10GEC	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_SRIO_LIODN
+#else
+#define CONFIG_MAX_DSP_CPUS		2
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS	1
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4 }
+#define CONFIG_SYS_NUM_FM1_DTSEC	4
+#define CONFIG_SYS_NUM_FM1_10GEC	0
+#endif
+
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
+#define CONFIG_E5500
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
+#define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_PME_PLAT_CLK_DIV		2
+#define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_FM_PLAT_CLK_DIV	1
+#define CONFIG_SYS_FM1_CLK		CONFIG_FM_PLAT_CLK_DIV
+#define CONFIG_SYS_SDHC_CLK		0/* Select SDHC CLK begining from PLL1
+					    per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL	/* Select SDHC CLK from 2 PLLs */
+#define CONFIG_SYS_FM_MURAM_SIZE	0x30000
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#define CONFIG_E5500
+#define CONFIG_FSL_CORENET	     /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
+#define CONFIG_SYS_FSL_QMAN_V3	 /* QMAN version 3 */
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FSL_NUM_CC_PLL	2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	4
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
+#define CONFIG_SYS_FM1_CLK		0
+#define CONFIG_SYS_SDHC_CLK		0/* Select SDHC CLK begining from PLL1
+					    per rcw field value */
+#define CONFIG_QBMAN_CLK_DIV		1
+#define CONFIG_SYS_FM_MURAM_SIZE	0x30000
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define QE_MURAM_SIZE			0x6000UL
+#define MAX_QE_RISC			1
+#define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+
+#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	2
+#define CONFIG_SYS_FSL_QMAN_V3
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCI_VER_3_X
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_SYS_NUM_FM1_DTSEC	8
+#define CONFIG_SYS_NUM_FM1_10GEC	4
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_FSL_SRIO_LIODN
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#elif defined(CONFIG_ARCH_T2081)
+#define CONFIG_SYS_NUM_FM1_DTSEC	6
+#define CONFIG_SYS_NUM_FM1_10GEC	2
+#endif
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_PME_PLAT_CLK_DIV		1
+#define CONFIG_SYS_PME_CLK		CONFIG_PME_PLAT_CLK_DIV
+#define CONFIG_SYS_FM1_CLK		0
+#define CONFIG_SYS_SDHC_CLK		1/* Select SDHC CLK begining from PLL2
+					    per rcw field value */
+#define CONFIG_SYS_SDHC_CLK_2_PLL	/* Select SDHC CLK from 2 PLLs */
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+#define CONFIG_SYS_FSL_ISBC_VER		2
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define CONFIG_SYS_FSL_SFP_VER_3_0
+
+
+#elif defined(CONFIG_ARCH_C29X)
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_TSECV2_1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	3
+#define CONFIG_SYS_FSL_SEC_IDX_OFFSET	0x20000
+
+#endif
+
+#if !defined(CONFIG_ARCH_C29X)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
+#endif
+
+#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
new file mode 100644
index 0000000..f19ff7a
--- /dev/null
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_MPC86xx_CONFIG_H_
+#define _ASM_MPC86xx_CONFIG_H_
+
+#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h
new file mode 100644
index 0000000..b46e20e
--- /dev/null
+++ b/arch/powerpc/include/asm/cpm_85xx.h
@@ -0,0 +1,829 @@
+/*
+ * MPC85xx Communication Processor Module
+ * Copyright (c) 2003,Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * MPC8260 Communication Processor Module.
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ *
+ * This file contains structures and information for the communication
+ * processor channels found in the dual port RAM or parameter RAM.
+ * All CPM control and status is available through the MPC8260 internal
+ * memory map.  See immap.h for details.
+ */
+#ifndef __CPM_85XX__
+#define __CPM_85XX__
+
+#include <asm/immap_85xx.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST	((uint)0x80000000)
+#define CPM_CR_PAGE	((uint)0x7c000000)
+#define CPM_CR_SBLOCK	((uint)0x03e00000)
+#define CPM_CR_FLG	((uint)0x00010000)
+#define CPM_CR_MCN	((uint)0x00003fc0)
+#define CPM_CR_OPCODE	((uint)0x0000000f)
+
+/* Device sub-block and page codes.
+*/
+#define CPM_CR_SCC1_SBLOCK	(0x04)
+#define CPM_CR_SCC2_SBLOCK	(0x05)
+#define CPM_CR_SCC3_SBLOCK	(0x06)
+#define CPM_CR_SCC4_SBLOCK	(0x07)
+#define CPM_CR_SMC1_SBLOCK	(0x08)
+#define CPM_CR_SMC2_SBLOCK	(0x09)
+#define CPM_CR_SPI_SBLOCK	(0x0a)
+#define CPM_CR_I2C_SBLOCK	(0x0b)
+#define CPM_CR_TIMER_SBLOCK	(0x0f)
+#define CPM_CR_RAND_SBLOCK	(0x0e)
+#define CPM_CR_FCC1_SBLOCK	(0x10)
+#define CPM_CR_FCC2_SBLOCK	(0x11)
+#define CPM_CR_FCC3_SBLOCK	(0x12)
+#define CPM_CR_MCC1_SBLOCK	(0x1c)
+
+#define CPM_CR_SCC1_PAGE	(0x00)
+#define CPM_CR_SCC2_PAGE	(0x01)
+#define CPM_CR_SCC3_PAGE	(0x02)
+#define CPM_CR_SCC4_PAGE	(0x03)
+#define CPM_CR_SPI_PAGE		(0x09)
+#define CPM_CR_I2C_PAGE		(0x0a)
+#define CPM_CR_TIMER_PAGE	(0x0a)
+#define CPM_CR_RAND_PAGE	(0x0a)
+#define CPM_CR_FCC1_PAGE	(0x04)
+#define CPM_CR_FCC2_PAGE	(0x05)
+#define CPM_CR_FCC3_PAGE	(0x06)
+#define CPM_CR_MCC1_PAGE	(0x07)
+#define CPM_CR_MCC2_PAGE	(0x08)
+
+/* Some opcodes (there are more...later)
+*/
+#define CPM_CR_INIT_TRX		((ushort)0x0000)
+#define CPM_CR_INIT_RX		((ushort)0x0001)
+#define CPM_CR_INIT_TX		((ushort)0x0002)
+#define CPM_CR_HUNT_MODE	((ushort)0x0003)
+#define CPM_CR_STOP_TX		((ushort)0x0004)
+#define CPM_CR_RESTART_TX	((ushort)0x0006)
+#define CPM_CR_SET_GADDR	((ushort)0x0008)
+
+#define mk_cr_cmd(PG, SBC, MCN, OP) \
+	((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
+
+/* Dual Port RAM addresses.  The first 16K is available for almost
+ * any CPM use, so we put the BDs there.  The first 128 bytes are
+ * used for SMC1 and SMC2 parameter RAM, so we start allocating
+ * BDs above that.  All of this must change when we start
+ * downloading RAM microcode.
+ */
+#define CPM_DATAONLY_BASE	((uint)128)
+#define CPM_DP_NOSPACE		((uint)0x7FFFFFFF)
+#if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
+#define CPM_FCC_SPECIAL_BASE	((uint)0x00009000)
+#define CPM_DATAONLY_SIZE	((uint)(8 * 1024) - CPM_DATAONLY_BASE)
+#else	/* MPC8540, MPC8560 */
+#define CPM_FCC_SPECIAL_BASE	((uint)0x0000B000)
+#define CPM_DATAONLY_SIZE	((uint)(16 * 1024) - CPM_DATAONLY_BASE)
+#endif
+
+/* The number of pages of host memory we allocate for CPM.  This is
+ * done early in kernel initialization to get physically contiguous
+ * pages.
+ */
+#define NUM_CPM_HOST_PAGES	2
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+/*extern	cpm8560_t	*cpmp;	 Pointer to comm processor */
+uint		m8560_cpm_dpalloc(uint size, uint align);
+uint		m8560_cpm_hostalloc(uint size, uint align);
+void		m8560_cpm_setbrg(uint brg, uint rate);
+void		m8560_cpm_fastbrg(uint brg, uint rate, int div16);
+void		m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+	ushort	cbd_sc;		/* Status and Control */
+	ushort	cbd_datlen;	/* Data length in buffer */
+	uint	cbd_bufaddr;	/* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
+#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
+#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
+#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
+#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
+#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
+#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
+#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
+#define BD_SC_BR	((ushort)0x0020)	/* Break received */
+#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
+#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
+#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
+#define BD_SC_CD	((ushort)0x0001)	/* ?? */
+
+/* Function code bits, usually generic to devices.
+*/
+#define CPMFCR_GBL	((u_char)0x20)	/* Set memory snooping */
+#define CPMFCR_EB	((u_char)0x10)	/* Set big endian byte order */
+#define CPMFCR_TC2	((u_char)0x04)	/* Transfer code 2 value */
+#define CPMFCR_DTB	((u_char)0x02)	/* Use local bus for data when set */
+#define CPMFCR_BDB	((u_char)0x01)	/* Use local bus for BD when set */
+
+/* Parameter RAM offsets from the base.
+*/
+#define CPM_POST_WORD_ADDR      0x80FC	/* steal a long at the end of SCC1 */
+#define PROFF_SCC1		((uint)0x8000)
+#define PROFF_SCC2		((uint)0x8100)
+#define PROFF_SCC3		((uint)0x8200)
+#define PROFF_SCC4		((uint)0x8300)
+#define PROFF_FCC1		((uint)0x8400)
+#define PROFF_FCC2		((uint)0x8500)
+#define PROFF_FCC3		((uint)0x8600)
+#define PROFF_MCC1		((uint)0x8700)
+#define PROFF_MCC2		((uint)0x8800)
+#define PROFF_SPI_BASE		((uint)0x89fc)
+#define PROFF_TIMERS		((uint)0x8ae0)
+#define PROFF_REVNUM		((uint)0x8af0)
+#define PROFF_RAND		((uint)0x8af8)
+#define PROFF_I2C_BASE		((uint)0x8afc)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST		((uint)0x00020000)
+#define CPM_BRG_EN		((uint)0x00010000)
+#define CPM_BRG_EXTC_INT	((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK3_9	((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK5_15	((uint)0x00008000)
+#define CPM_BRG_ATB		((uint)0x00002000)
+#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
+#define CPM_BRG_DIV16		((uint)0x00000001)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP		((uint)0x00040000)
+#define SCC_GSMRH_GDE		((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
+#define SCC_GSMRH_REVD		((uint)0x00002000)
+#define SCC_GSMRH_TRX		((uint)0x00001000)
+#define SCC_GSMRH_TTX		((uint)0x00000800)
+#define SCC_GSMRH_CDP		((uint)0x00000400)
+#define SCC_GSMRH_CTSP		((uint)0x00000200)
+#define SCC_GSMRH_CDS		((uint)0x00000100)
+#define SCC_GSMRH_CTSS		((uint)0x00000080)
+#define SCC_GSMRH_TFL		((uint)0x00000040)
+#define SCC_GSMRH_RFW		((uint)0x00000020)
+#define SCC_GSMRH_TXSY		((uint)0x00000010)
+#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8		((uint)0x00000008)
+#define SCC_GSMRH_SYNL4		((uint)0x00000004)
+#define SCC_GSMRH_RTSM		((uint)0x00000002)
+#define SCC_GSMRH_RSYN		((uint)0x00000001)
+
+#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
+#define SCC_GSMRL_TCI		((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
+#define SCC_GSMRL_RINV		((uint)0x02000000)
+#define SCC_GSMRL_TINV		((uint)0x01000000)
+#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48	((uint)0x00800000)
+#define SCC_GSMRL_TPL_32	((uint)0x00600000)
+#define SCC_GSMRL_TPL_16	((uint)0x00400000)
+#define SCC_GSMRL_TPL_8		((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
+#define SCC_GSMRL_TPP_01	((uint)0x00100000)
+#define SCC_GSMRL_TPP_10	((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
+#define SCC_GSMRL_TEND		((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
+#define SCC_GSMRL_ENR		((uint)0x00000020)
+#define SCC_GSMRL_ENT		((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
+
+#define SCC_TODR_TOD		((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define	SCCM_TXE	((unsigned char)0x10)
+#define	SCCM_BSY	((unsigned char)0x04)
+#define	SCCM_TX		((unsigned char)0x02)
+#define	SCCM_RX		((unsigned char)0x01)
+
+typedef struct scc_param {
+	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	scc_rfcr;	/* Rx function code */
+	u_char	scc_tfcr;	/* Tx function code */
+	ushort	scc_mrblr;	/* Max receive buffer length */
+	uint	scc_rstate;	/* Internal */
+	uint	scc_idp;	/* Internal */
+	ushort	scc_rbptr;	/* Internal */
+	ushort	scc_ibc;	/* Internal */
+	uint	scc_rxtmp;	/* Internal */
+	uint	scc_tstate;	/* Internal */
+	uint	scc_tdp;	/* Internal */
+	ushort	scc_tbptr;	/* Internal */
+	ushort	scc_tbc;	/* Internal */
+	uint	scc_txtmp;	/* Internal */
+	uint	scc_rcrc;	/* Internal */
+	uint	scc_tcrc;	/* Internal */
+} sccp_t;
+
+/* CPM Ethernet through SCC1.
+ */
+typedef struct scc_enet {
+	sccp_t	sen_genscc;
+	uint	sen_cpres;	/* Preset CRC */
+	uint	sen_cmask;	/* Constant mask for CRC */
+	uint	sen_crcec;	/* CRC Error counter */
+	uint	sen_alec;	/* alignment error counter */
+	uint	sen_disfc;	/* discard frame counter */
+	ushort	sen_pads;	/* Tx short frame pad character */
+	ushort	sen_retlim;	/* Retry limit threshold */
+	ushort	sen_retcnt;	/* Retry limit counter */
+	ushort	sen_maxflr;	/* maximum frame length register */
+	ushort	sen_minflr;	/* minimum frame length register */
+	ushort	sen_maxd1;	/* maximum DMA1 length */
+	ushort	sen_maxd2;	/* maximum DMA2 length */
+	ushort	sen_maxd;	/* Rx max DMA */
+	ushort	sen_dmacnt;	/* Rx DMA counter */
+	ushort	sen_maxb;	/* Max BD byte count */
+	ushort	sen_gaddr1;	/* Group address filter */
+	ushort	sen_gaddr2;
+	ushort	sen_gaddr3;
+	ushort	sen_gaddr4;
+	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf0rba;	/* Internal */
+	uint	sen_tbuf0crc;	/* Internal */
+	ushort	sen_tbuf0bcnt;	/* Internal */
+	ushort	sen_paddrh;	/* physical address (MSB) */
+	ushort	sen_paddrm;
+	ushort	sen_paddrl;	/* physical address (LSB) */
+	ushort	sen_pper;	/* persistence */
+	ushort	sen_rfbdptr;	/* Rx first BD pointer */
+	ushort	sen_tfbdptr;	/* Tx first BD pointer */
+	ushort	sen_tlbdptr;	/* Tx last BD pointer */
+	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf1rba;	/* Internal */
+	uint	sen_tbuf1crc;	/* Internal */
+	ushort	sen_tbuf1bcnt;	/* Internal */
+	ushort	sen_txlen;	/* Tx Frame length counter */
+	ushort	sen_iaddr1;	/* Individual address filter */
+	ushort	sen_iaddr2;
+	ushort	sen_iaddr3;
+	ushort	sen_iaddr4;
+	ushort	sen_boffcnt;	/* Backoff counter */
+
+	/* NOTE: Some versions of the manual have the following items
+	 * incorrectly documented.  Below is the proper order.
+	 */
+	ushort	sen_taddrh;	/* temp address (MSB) */
+	ushort	sen_taddrm;
+	ushort	sen_taddrl;	/* temp address (LSB) */
+} scc_enet_t;
+
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
+#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
+#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
+#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
+#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
+#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
+#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
+#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
+#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
+#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
+#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
+#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
+#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
+#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
+#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
+#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
+#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
+#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_WRAP		((ushort)0x2000)
+#define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_LAST		((ushort)0x0800)
+#define BD_ENET_RX_FIRST	((ushort)0x0400)
+#define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_BC		((ushort)0x0080)	/* FCC Only */
+#define BD_ENET_RX_MC		((ushort)0x0040)	/* FCC Only */
+#define BD_ENET_RX_LG		((ushort)0x0020)
+#define BD_ENET_RX_NO		((ushort)0x0010)
+#define BD_ENET_RX_SH		((ushort)0x0008)
+#define BD_ENET_RX_CR		((ushort)0x0004)
+#define BD_ENET_RX_OV		((ushort)0x0002)
+#define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_STATS	((ushort)0x01ff)	/* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_TX_READY	((ushort)0x8000)
+#define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_WRAP		((ushort)0x2000)
+#define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_LAST		((ushort)0x0800)
+#define BD_ENET_TX_TC		((ushort)0x0400)
+#define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_HB		((ushort)0x0100)
+#define BD_ENET_TX_LC		((ushort)0x0080)
+#define BD_ENET_TX_RL		((ushort)0x0040)
+#define BD_ENET_TX_RCMASK	((ushort)0x003c)
+#define BD_ENET_TX_UN		((ushort)0x0002)
+#define BD_ENET_TX_CSL		((ushort)0x0001)
+#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+	sccp_t	scc_genscc;
+	uint	scc_res1;	/* Reserved */
+	uint	scc_res2;	/* Reserved */
+	ushort	scc_maxidl;	/* Maximum idle chars */
+	ushort	scc_idlc;	/* temp idle counter */
+	ushort	scc_brkcr;	/* Break count register */
+	ushort	scc_parec;	/* receive parity error counter */
+	ushort	scc_frmec;	/* receive framing error counter */
+	ushort	scc_nosec;	/* receive noise counter */
+	ushort	scc_brkec;	/* receive break condition counter */
+	ushort	scc_brkln;	/* last received break length */
+	ushort	scc_uaddr1;	/* UART address character 1 */
+	ushort	scc_uaddr2;	/* UART address character 2 */
+	ushort	scc_rtemp;	/* Temp storage */
+	ushort	scc_toseq;	/* Transmit out of sequence char */
+	ushort	scc_char1;	/* control character 1 */
+	ushort	scc_char2;	/* control character 2 */
+	ushort	scc_char3;	/* control character 3 */
+	ushort	scc_char4;	/* control character 4 */
+	ushort	scc_char5;	/* control character 5 */
+	ushort	scc_char6;	/* control character 6 */
+	ushort	scc_char7;	/* control character 7 */
+	ushort	scc_char8;	/* control character 8 */
+	ushort	scc_rccm;	/* receive control character mask */
+	ushort	scc_rccr;	/* receive control character register */
+	ushort	scc_rlbc;	/* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR		((ushort)0x1000)
+#define UART_SCCM_GLT		((ushort)0x0800)
+#define UART_SCCM_AB		((ushort)0x0200)
+#define UART_SCCM_IDL		((ushort)0x0100)
+#define UART_SCCM_GRA		((ushort)0x0080)
+#define UART_SCCM_BRKE		((ushort)0x0040)
+#define UART_SCCM_BRKS		((ushort)0x0020)
+#define UART_SCCM_CCR		((ushort)0x0008)
+#define UART_SCCM_BSY		((ushort)0x0004)
+#define UART_SCCM_TX		((ushort)0x0002)
+#define UART_SCCM_RX		((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC		((ushort)0x8000)
+#define SCU_PSMR_SL		((ushort)0x4000)
+#define SCU_PSMR_CL		((ushort)0x3000)
+#define SCU_PSMR_UM		((ushort)0x0c00)
+#define SCU_PSMR_FRZ		((ushort)0x0200)
+#define SCU_PSMR_RZS		((ushort)0x0100)
+#define SCU_PSMR_SYN		((ushort)0x0080)
+#define SCU_PSMR_DRT		((ushort)0x0040)
+#define SCU_PSMR_PEN		((ushort)0x0010)
+#define SCU_PSMR_RPM		((ushort)0x000c)
+#define SCU_PSMR_REVP		((ushort)0x0008)
+#define SCU_PSMR_TPM		((ushort)0x0003)
+#define SCU_PSMR_TEVP		((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+	sccp_t	st_genscc;
+	uint	st_cpres;	/* Preset CRC */
+	uint	st_cmask;	/* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST		((ushort)0x0800)
+
+/* How about some FCCs.....
+*/
+#define FCC_GFMR_DIAG_NORM	((uint)0x00000000)
+#define FCC_GFMR_DIAG_LE	((uint)0x40000000)
+#define FCC_GFMR_DIAG_AE	((uint)0x80000000)
+#define FCC_GFMR_DIAG_ALE	((uint)0xc0000000)
+#define FCC_GFMR_TCI		((uint)0x20000000)
+#define FCC_GFMR_TRX		((uint)0x10000000)
+#define FCC_GFMR_TTX		((uint)0x08000000)
+#define FCC_GFMR_TTX		((uint)0x08000000)
+#define FCC_GFMR_CDP		((uint)0x04000000)
+#define FCC_GFMR_CTSP		((uint)0x02000000)
+#define FCC_GFMR_CDS		((uint)0x01000000)
+#define FCC_GFMR_CTSS		((uint)0x00800000)
+#define FCC_GFMR_SYNL_NONE	((uint)0x00000000)
+#define FCC_GFMR_SYNL_AUTO	((uint)0x00004000)
+#define FCC_GFMR_SYNL_8		((uint)0x00008000)
+#define FCC_GFMR_SYNL_16	((uint)0x0000c000)
+#define FCC_GFMR_RTSM		((uint)0x00002000)
+#define FCC_GFMR_RENC_NRZ	((uint)0x00000000)
+#define FCC_GFMR_RENC_NRZI	((uint)0x00000800)
+#define FCC_GFMR_REVD		((uint)0x00000400)
+#define FCC_GFMR_TENC_NRZ	((uint)0x00000000)
+#define FCC_GFMR_TENC_NRZI	((uint)0x00000100)
+#define FCC_GFMR_TCRC_16	((uint)0x00000000)
+#define FCC_GFMR_TCRC_32	((uint)0x00000080)
+#define FCC_GFMR_ENR		((uint)0x00000020)
+#define FCC_GFMR_ENT		((uint)0x00000010)
+#define FCC_GFMR_MODE_ENET	((uint)0x0000000c)
+#define FCC_GFMR_MODE_ATM	((uint)0x0000000a)
+#define FCC_GFMR_MODE_HDLC	((uint)0x00000000)
+
+/* Generic FCC parameter ram.
+*/
+typedef struct fcc_param {
+	ushort	fcc_riptr;	/* Rx Internal temp pointer */
+	ushort	fcc_tiptr;	/* Tx Internal temp pointer */
+	ushort	fcc_res1;
+	ushort	fcc_mrblr;	/* Max receive buffer length, mod 32 bytes */
+	uint	fcc_rstate;	/* Upper byte is Func code, must be set */
+	uint	fcc_rbase;	/* Receive BD base */
+	ushort	fcc_rbdstat;	/* RxBD status */
+	ushort	fcc_rbdlen;	/* RxBD down counter */
+	uint	fcc_rdptr;	/* RxBD internal data pointer */
+	uint	fcc_tstate;	/* Upper byte is Func code, must be set */
+	uint	fcc_tbase;	/* Transmit BD base */
+	ushort	fcc_tbdstat;	/* TxBD status */
+	ushort	fcc_tbdlen;	/* TxBD down counter */
+	uint	fcc_tdptr;	/* TxBD internal data pointer */
+	uint	fcc_rbptr;	/* Rx BD Internal buf pointer */
+	uint	fcc_tbptr;	/* Tx BD Internal buf pointer */
+	uint	fcc_rcrc;	/* Rx temp CRC */
+	uint	fcc_res2;
+	uint	fcc_tcrc;	/* Tx temp CRC */
+} fccp_t;
+
+
+/* Ethernet controller through FCC.
+*/
+typedef struct fcc_enet {
+	fccp_t	fen_genfcc;
+	uint	fen_statbuf;	/* Internal status buffer */
+	uint	fen_camptr;	/* CAM address */
+	uint	fen_cmask;	/* Constant mask for CRC */
+	uint	fen_cpres;	/* Preset CRC */
+	uint	fen_crcec;	/* CRC Error counter */
+	uint	fen_alec;	/* alignment error counter */
+	uint	fen_disfc;	/* discard frame counter */
+	ushort	fen_retlim;	/* Retry limit */
+	ushort	fen_retcnt;	/* Retry counter */
+	ushort	fen_pper;	/* Persistence */
+	ushort	fen_boffcnt;	/* backoff counter */
+	uint	fen_gaddrh;	/* Group address filter, high 32-bits */
+	uint	fen_gaddrl;	/* Group address filter, low 32-bits */
+	ushort	fen_tfcstat;	/* out of sequence TxBD */
+	ushort	fen_tfclen;
+	uint	fen_tfcptr;
+	ushort	fen_mflr;	/* Maximum frame length (1518) */
+	ushort	fen_paddrh;	/* MAC address */
+	ushort	fen_paddrm;
+	ushort	fen_paddrl;
+	ushort	fen_ibdcount;	/* Internal BD counter */
+	ushort	fen_ibdstart;	/* Internal BD start pointer */
+	ushort	fen_ibdend;	/* Internal BD end pointer */
+	ushort	fen_txlen;	/* Internal Tx frame length counter */
+	uint	fen_ibdbase[8]; /* Internal use */
+	uint	fen_iaddrh;	/* Individual address filter */
+	uint	fen_iaddrl;
+	ushort	fen_minflr;	/* Minimum frame length (64) */
+	ushort	fen_taddrh;	/* Filter transfer MAC address */
+	ushort	fen_taddrm;
+	ushort	fen_taddrl;
+	ushort	fen_padptr;	/* Pointer to pad byte buffer */
+	ushort	fen_cftype;	/* control frame type */
+	ushort	fen_cfrange;	/* control frame range */
+	ushort	fen_maxb;	/* maximum BD count */
+	ushort	fen_maxd1;	/* Max DMA1 length (1520) */
+	ushort	fen_maxd2;	/* Max DMA2 length (1520) */
+	ushort	fen_maxd;	/* internal max DMA count */
+	ushort	fen_dmacnt;	/* internal DMA counter */
+	uint	fen_octc;	/* Total octect counter */
+	uint	fen_colc;	/* Total collision counter */
+	uint	fen_broc;	/* Total broadcast packet counter */
+	uint	fen_mulc;	/* Total multicast packet count */
+	uint	fen_uspc;	/* Total packets < 64 bytes */
+	uint	fen_frgc;	/* Total packets < 64 bytes with errors */
+	uint	fen_ospc;	/* Total packets > 1518 */
+	uint	fen_jbrc;	/* Total packets > 1518 with errors */
+	uint	fen_p64c;	/* Total packets == 64 bytes */
+	uint	fen_p65c;	/* Total packets 64 < bytes <= 127 */
+	uint	fen_p128c;	/* Total packets 127 < bytes <= 255 */
+	uint	fen_p256c;	/* Total packets 256 < bytes <= 511 */
+	uint	fen_p512c;	/* Total packets 512 < bytes <= 1023 */
+	uint	fen_p1024c;	/* Total packets 1024 < bytes <= 1518 */
+	uint	fen_cambuf;	/* Internal CAM buffer poiner */
+	ushort	fen_rfthr;	/* Received frames threshold */
+	ushort	fen_rfcnt;	/* Received frames count */
+} fcc_enet_t;
+
+/* FCC Event/Mask register as used by Ethernet.
+*/
+#define FCC_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
+#define FCC_ENET_RXC	((ushort)0x0040)	/* Control Frame Received */
+#define FCC_ENET_TXC	((ushort)0x0020)	/* Out of seq. Tx sent */
+#define FCC_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
+#define FCC_ENET_RXF	((ushort)0x0008)	/* Full frame received */
+#define FCC_ENET_BSY	((ushort)0x0004)	/* Busy.  Rx Frame dropped */
+#define FCC_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
+#define FCC_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
+
+/* FCC Mode Register (FPSMR) as used by Ethernet.
+*/
+#define FCC_PSMR_HBC	((uint)0x80000000)	/* Enable heartbeat */
+#define FCC_PSMR_FC	((uint)0x40000000)	/* Force Collision */
+#define FCC_PSMR_SBT	((uint)0x20000000)	/* Stop backoff timer */
+#define FCC_PSMR_LPB	((uint)0x10000000)	/* Local protect. 1 = FDX */
+#define FCC_PSMR_LCW	((uint)0x08000000)	/* Late collision select */
+#define FCC_PSMR_FDE	((uint)0x04000000)	/* Full Duplex Enable */
+#define FCC_PSMR_MON	((uint)0x02000000)	/* RMON Enable */
+#define FCC_PSMR_PRO	((uint)0x00400000)	/* Promiscuous Enable */
+#define FCC_PSMR_FCE	((uint)0x00200000)	/* Flow Control Enable */
+#define FCC_PSMR_RSH	((uint)0x00100000)	/* Receive Short Frames */
+#define FCC_PSMR_CAM	((uint)0x00000400)	/* CAM enable */
+#define FCC_PSMR_BRO	((uint)0x00000200)	/* Broadcast pkt discard */
+#define FCC_PSMR_ENCRC	((uint)0x00000080)	/* Use 32-bit CRC */
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
+	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
+	u_char	iic_rfcr;	/* Rx function code */
+	u_char	iic_tfcr;	/* Tx function code */
+	ushort	iic_mrblr;	/* Max receive buffer length */
+	uint	iic_rstate;	/* Internal */
+	uint	iic_rdp;	/* Internal */
+	ushort	iic_rbptr;	/* Internal */
+	ushort	iic_rbc;	/* Internal */
+	uint	iic_rxtmp;	/* Internal */
+	uint	iic_tstate;	/* Internal */
+	uint	iic_tdp;	/* Internal */
+	ushort	iic_tbptr;	/* Internal */
+	ushort	iic_tbc;	/* Internal */
+	uint	iic_txtmp;	/* Internal */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
+	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
+	u_char	spi_rfcr;	/* Rx function code */
+	u_char	spi_tfcr;	/* Tx function code */
+	ushort	spi_mrblr;	/* Max receive buffer length */
+	uint	spi_rstate;	/* Internal */
+	uint	spi_rdp;	/* Internal */
+	ushort	spi_rbptr;	/* Internal */
+	ushort	spi_rbc;	/* Internal */
+	uint	spi_rxtmp;	/* Internal */
+	uint	spi_tstate;	/* Internal */
+	uint	spi_tdp;	/* Internal */
+	ushort	spi_tbptr;	/* Internal */
+	ushort	spi_tbc;	/* Internal */
+	uint	spi_txtmp;	/* Internal */
+	uint	spi_res;	/* Tx temp. */
+	uint	spi_res1[4];	/* SDMA temp. */
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
+#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
+#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
+#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
+#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
+#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
+#define SPMODE_EN	((ushort)0x0100)	/* Enable */
+#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
+#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
+
+#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
+#define SPMODE_PM(x)	((x) &0xF)
+
+#define SPI_EB		((u_char)0x10)		/* big endian byte order */
+
+#define BD_IIC_START	((ushort)0x0400)
+
+/*-----------------------------------------------------------------------
+ * CMXFCR - CMX FCC Clock Route Register                                15-12
+ */
+#define CMXFCR_FC1         0x40000000   /* FCC1 connection              */
+#define CMXFCR_RF1CS_MSK   0x38000000   /* Receive FCC1 Clock Source Mask */
+#define CMXFCR_TF1CS_MSK   0x07000000   /* Transmit FCC1 Clock Source Mask */
+#define CMXFCR_FC2         0x00400000   /* FCC2 connection              */
+#define CMXFCR_RF2CS_MSK   0x00380000   /* Receive FCC2 Clock Source Mask */
+#define CMXFCR_TF2CS_MSK   0x00070000   /* Transmit FCC2 Clock Source Mask */
+#define CMXFCR_FC3         0x00004000   /* FCC3 connection              */
+#define CMXFCR_RF3CS_MSK   0x00003800   /* Receive FCC3 Clock Source Mask */
+#define CMXFCR_TF3CS_MSK   0x00000700   /* Transmit FCC3 Clock Source Mask */
+
+#define CMXFCR_RF1CS_BRG5  0x00000000   /* Receive FCC1 Clock Source is BRG5 */
+#define CMXFCR_RF1CS_BRG6  0x08000000   /* Receive FCC1 Clock Source is BRG6 */
+#define CMXFCR_RF1CS_BRG7  0x10000000   /* Receive FCC1 Clock Source is BRG7 */
+#define CMXFCR_RF1CS_BRG8  0x18000000   /* Receive FCC1 Clock Source is BRG8 */
+#define CMXFCR_RF1CS_CLK9  0x20000000   /* Receive FCC1 Clock Source is CLK9 */
+#define CMXFCR_RF1CS_CLK10 0x28000000   /* Receive FCC1 Clock Source is CLK10 */
+#define CMXFCR_RF1CS_CLK11 0x30000000   /* Receive FCC1 Clock Source is CLK11 */
+#define CMXFCR_RF1CS_CLK12 0x38000000   /* Receive FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_TF1CS_BRG5  0x00000000   /* Transmit FCC1 Clock Source is BRG5 */
+#define CMXFCR_TF1CS_BRG6  0x01000000   /* Transmit FCC1 Clock Source is BRG6 */
+#define CMXFCR_TF1CS_BRG7  0x02000000   /* Transmit FCC1 Clock Source is BRG7 */
+#define CMXFCR_TF1CS_BRG8  0x03000000   /* Transmit FCC1 Clock Source is BRG8 */
+#define CMXFCR_TF1CS_CLK9  0x04000000   /* Transmit FCC1 Clock Source is CLK9 */
+#define CMXFCR_TF1CS_CLK10 0x05000000   /* Transmit FCC1 Clock Source is CLK10 */
+#define CMXFCR_TF1CS_CLK11 0x06000000   /* Transmit FCC1 Clock Source is CLK11 */
+#define CMXFCR_TF1CS_CLK12 0x07000000   /* Transmit FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_RF2CS_BRG5  0x00000000   /* Receive FCC2 Clock Source is BRG5 */
+#define CMXFCR_RF2CS_BRG6  0x00080000   /* Receive FCC2 Clock Source is BRG6 */
+#define CMXFCR_RF2CS_BRG7  0x00100000   /* Receive FCC2 Clock Source is BRG7 */
+#define CMXFCR_RF2CS_BRG8  0x00180000   /* Receive FCC2 Clock Source is BRG8 */
+#define CMXFCR_RF2CS_CLK13 0x00200000   /* Receive FCC2 Clock Source is CLK13 */
+#define CMXFCR_RF2CS_CLK14 0x00280000   /* Receive FCC2 Clock Source is CLK14 */
+#define CMXFCR_RF2CS_CLK15 0x00300000   /* Receive FCC2 Clock Source is CLK15 */
+#define CMXFCR_RF2CS_CLK16 0x00380000   /* Receive FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_TF2CS_BRG5  0x00000000   /* Transmit FCC2 Clock Source is BRG5 */
+#define CMXFCR_TF2CS_BRG6  0x00010000   /* Transmit FCC2 Clock Source is BRG6 */
+#define CMXFCR_TF2CS_BRG7  0x00020000   /* Transmit FCC2 Clock Source is BRG7 */
+#define CMXFCR_TF2CS_BRG8  0x00030000   /* Transmit FCC2 Clock Source is BRG8 */
+#define CMXFCR_TF2CS_CLK13 0x00040000   /* Transmit FCC2 Clock Source is CLK13 */
+#define CMXFCR_TF2CS_CLK14 0x00050000   /* Transmit FCC2 Clock Source is CLK14 */
+#define CMXFCR_TF2CS_CLK15 0x00060000   /* Transmit FCC2 Clock Source is CLK15 */
+#define CMXFCR_TF2CS_CLK16 0x00070000   /* Transmit FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_RF3CS_BRG5  0x00000000   /* Receive FCC3 Clock Source is BRG5 */
+#define CMXFCR_RF3CS_BRG6  0x00000800   /* Receive FCC3 Clock Source is BRG6 */
+#define CMXFCR_RF3CS_BRG7  0x00001000   /* Receive FCC3 Clock Source is BRG7 */
+#define CMXFCR_RF3CS_BRG8  0x00001800   /* Receive FCC3 Clock Source is BRG8 */
+#define CMXFCR_RF3CS_CLK13 0x00002000   /* Receive FCC3 Clock Source is CLK13 */
+#define CMXFCR_RF3CS_CLK14 0x00002800   /* Receive FCC3 Clock Source is CLK14 */
+#define CMXFCR_RF3CS_CLK15 0x00003000   /* Receive FCC3 Clock Source is CLK15 */
+#define CMXFCR_RF3CS_CLK16 0x00003800   /* Receive FCC3 Clock Source is CLK16 */
+
+#define CMXFCR_TF3CS_BRG5  0x00000000   /* Transmit FCC3 Clock Source is BRG5 */
+#define CMXFCR_TF3CS_BRG6  0x00000100   /* Transmit FCC3 Clock Source is BRG6 */
+#define CMXFCR_TF3CS_BRG7  0x00000200   /* Transmit FCC3 Clock Source is BRG7 */
+#define CMXFCR_TF3CS_BRG8  0x00000300   /* Transmit FCC3 Clock Source is BRG8 */
+#define CMXFCR_TF3CS_CLK13 0x00000400   /* Transmit FCC3 Clock Source is CLK13 */
+#define CMXFCR_TF3CS_CLK14 0x00000500   /* Transmit FCC3 Clock Source is CLK14 */
+#define CMXFCR_TF3CS_CLK15 0x00000600   /* Transmit FCC3 Clock Source is CLK15 */
+#define CMXFCR_TF3CS_CLK16 0x00000700   /* Transmit FCC3 Clock Source is CLK16 */
+
+/*-----------------------------------------------------------------------
+ * CMXSCR - CMX SCC Clock Route Register                                15-14
+ */
+#define CMXSCR_GR1         0x80000000   /* Grant Support of SCC1        */
+#define CMXSCR_SC1         0x40000000   /* SCC1 connection              */
+#define CMXSCR_RS1CS_MSK   0x38000000   /* Receive SCC1 Clock Source Mask */
+#define CMXSCR_TS1CS_MSK   0x07000000   /* Transmit SCC1 Clock Source Mask */
+#define CMXSCR_GR2         0x00800000   /* Grant Support of SCC2        */
+#define CMXSCR_SC2         0x00400000   /* SCC2 connection              */
+#define CMXSCR_RS2CS_MSK   0x00380000   /* Receive SCC2 Clock Source Mask */
+#define CMXSCR_TS2CS_MSK   0x00070000   /* Transmit SCC2 Clock Source Mask */
+#define CMXSCR_GR3         0x00008000   /* Grant Support of SCC3        */
+#define CMXSCR_SC3         0x00004000   /* SCC3 connection              */
+#define CMXSCR_RS3CS_MSK   0x00003800   /* Receive SCC3 Clock Source Mask */
+#define CMXSCR_TS3CS_MSK   0x00000700   /* Transmit SCC3 Clock Source Mask */
+#define CMXSCR_GR4         0x00000080   /* Grant Support of SCC4        */
+#define CMXSCR_SC4         0x00000040   /* SCC4 connection              */
+#define CMXSCR_RS4CS_MSK   0x00000038   /* Receive SCC4 Clock Source Mask */
+#define CMXSCR_TS4CS_MSK   0x00000007   /* Transmit SCC4 Clock Source Mask */
+
+#define CMXSCR_RS1CS_BRG1  0x00000000   /* SCC1 Rx Clock Source is BRG1 */
+#define CMXSCR_RS1CS_BRG2  0x08000000   /* SCC1 Rx Clock Source is BRG2 */
+#define CMXSCR_RS1CS_BRG3  0x10000000   /* SCC1 Rx Clock Source is BRG3 */
+#define CMXSCR_RS1CS_BRG4  0x18000000   /* SCC1 Rx Clock Source is BRG4 */
+#define CMXSCR_RS1CS_CLK11 0x20000000   /* SCC1 Rx Clock Source is CLK11 */
+#define CMXSCR_RS1CS_CLK12 0x28000000   /* SCC1 Rx Clock Source is CLK12 */
+#define CMXSCR_RS1CS_CLK3  0x30000000   /* SCC1 Rx Clock Source is CLK3 */
+#define CMXSCR_RS1CS_CLK4  0x38000000   /* SCC1 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS1CS_BRG1  0x00000000   /* SCC1 Tx Clock Source is BRG1 */
+#define CMXSCR_TS1CS_BRG2  0x01000000   /* SCC1 Tx Clock Source is BRG2 */
+#define CMXSCR_TS1CS_BRG3  0x02000000   /* SCC1 Tx Clock Source is BRG3 */
+#define CMXSCR_TS1CS_BRG4  0x03000000   /* SCC1 Tx Clock Source is BRG4 */
+#define CMXSCR_TS1CS_CLK11 0x04000000   /* SCC1 Tx Clock Source is CLK11 */
+#define CMXSCR_TS1CS_CLK12 0x05000000   /* SCC1 Tx Clock Source is CLK12 */
+#define CMXSCR_TS1CS_CLK3  0x06000000   /* SCC1 Tx Clock Source is CLK3 */
+#define CMXSCR_TS1CS_CLK4  0x07000000   /* SCC1 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS2CS_BRG1  0x00000000   /* SCC2 Rx Clock Source is BRG1 */
+#define CMXSCR_RS2CS_BRG2  0x00080000   /* SCC2 Rx Clock Source is BRG2 */
+#define CMXSCR_RS2CS_BRG3  0x00100000   /* SCC2 Rx Clock Source is BRG3 */
+#define CMXSCR_RS2CS_BRG4  0x00180000   /* SCC2 Rx Clock Source is BRG4 */
+#define CMXSCR_RS2CS_CLK11 0x00200000   /* SCC2 Rx Clock Source is CLK11 */
+#define CMXSCR_RS2CS_CLK12 0x00280000   /* SCC2 Rx Clock Source is CLK12 */
+#define CMXSCR_RS2CS_CLK3  0x00300000   /* SCC2 Rx Clock Source is CLK3 */
+#define CMXSCR_RS2CS_CLK4  0x00380000   /* SCC2 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS2CS_BRG1  0x00000000   /* SCC2 Tx Clock Source is BRG1 */
+#define CMXSCR_TS2CS_BRG2  0x00010000   /* SCC2 Tx Clock Source is BRG2 */
+#define CMXSCR_TS2CS_BRG3  0x00020000   /* SCC2 Tx Clock Source is BRG3 */
+#define CMXSCR_TS2CS_BRG4  0x00030000   /* SCC2 Tx Clock Source is BRG4 */
+#define CMXSCR_TS2CS_CLK11 0x00040000   /* SCC2 Tx Clock Source is CLK11 */
+#define CMXSCR_TS2CS_CLK12 0x00050000   /* SCC2 Tx Clock Source is CLK12 */
+#define CMXSCR_TS2CS_CLK3  0x00060000   /* SCC2 Tx Clock Source is CLK3 */
+#define CMXSCR_TS2CS_CLK4  0x00070000   /* SCC2 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS3CS_BRG1  0x00000000   /* SCC3 Rx Clock Source is BRG1 */
+#define CMXSCR_RS3CS_BRG2  0x00000800   /* SCC3 Rx Clock Source is BRG2 */
+#define CMXSCR_RS3CS_BRG3  0x00001000   /* SCC3 Rx Clock Source is BRG3 */
+#define CMXSCR_RS3CS_BRG4  0x00001800   /* SCC3 Rx Clock Source is BRG4 */
+#define CMXSCR_RS3CS_CLK5  0x00002000   /* SCC3 Rx Clock Source is CLK5 */
+#define CMXSCR_RS3CS_CLK6  0x00002800   /* SCC3 Rx Clock Source is CLK6 */
+#define CMXSCR_RS3CS_CLK7  0x00003000   /* SCC3 Rx Clock Source is CLK7 */
+#define CMXSCR_RS3CS_CLK8  0x00003800   /* SCC3 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS3CS_BRG1  0x00000000   /* SCC3 Tx Clock Source is BRG1 */
+#define CMXSCR_TS3CS_BRG2  0x00000100   /* SCC3 Tx Clock Source is BRG2 */
+#define CMXSCR_TS3CS_BRG3  0x00000200   /* SCC3 Tx Clock Source is BRG3 */
+#define CMXSCR_TS3CS_BRG4  0x00000300   /* SCC3 Tx Clock Source is BRG4 */
+#define CMXSCR_TS3CS_CLK5  0x00000400   /* SCC3 Tx Clock Source is CLK5 */
+#define CMXSCR_TS3CS_CLK6  0x00000500   /* SCC3 Tx Clock Source is CLK6 */
+#define CMXSCR_TS3CS_CLK7  0x00000600   /* SCC3 Tx Clock Source is CLK7 */
+#define CMXSCR_TS3CS_CLK8  0x00000700   /* SCC3 Tx Clock Source is CLK8 */
+
+#define CMXSCR_RS4CS_BRG1  0x00000000   /* SCC4 Rx Clock Source is BRG1 */
+#define CMXSCR_RS4CS_BRG2  0x00000008   /* SCC4 Rx Clock Source is BRG2 */
+#define CMXSCR_RS4CS_BRG3  0x00000010   /* SCC4 Rx Clock Source is BRG3 */
+#define CMXSCR_RS4CS_BRG4  0x00000018   /* SCC4 Rx Clock Source is BRG4 */
+#define CMXSCR_RS4CS_CLK5  0x00000020   /* SCC4 Rx Clock Source is CLK5 */
+#define CMXSCR_RS4CS_CLK6  0x00000028   /* SCC4 Rx Clock Source is CLK6 */
+#define CMXSCR_RS4CS_CLK7  0x00000030   /* SCC4 Rx Clock Source is CLK7 */
+#define CMXSCR_RS4CS_CLK8  0x00000038   /* SCC4 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS4CS_BRG1  0x00000000   /* SCC4 Tx Clock Source is BRG1 */
+#define CMXSCR_TS4CS_BRG2  0x00000001   /* SCC4 Tx Clock Source is BRG2 */
+#define CMXSCR_TS4CS_BRG3  0x00000002   /* SCC4 Tx Clock Source is BRG3 */
+#define CMXSCR_TS4CS_BRG4  0x00000003   /* SCC4 Tx Clock Source is BRG4 */
+#define CMXSCR_TS4CS_CLK5  0x00000004   /* SCC4 Tx Clock Source is CLK5 */
+#define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
+#define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
+#define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
+
+#endif /* __CPM_85XX__ */
diff --git a/arch/powerpc/include/asm/cpm_8xx.h b/arch/powerpc/include/asm/cpm_8xx.h
new file mode 100644
index 0000000..85903d2
--- /dev/null
+++ b/arch/powerpc/include/asm/cpm_8xx.h
@@ -0,0 +1,687 @@
+/*
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file contains structures and information for the communication
+ * processor channels.  Some CPM control and status is available
+ * through the MPC8xx internal memory map.  See immap.h for details.
+ * This file only contains what I need for the moment, not the total
+ * CPM capabilities.  I (or someone else) will add definitions as they
+ * are needed.  -- Dan
+ *
+ */
+#ifndef __CPM_8XX__
+#define __CPM_8XX__
+
+#include <asm/immap_8xx.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST		((ushort)0x8000)
+#define CPM_CR_OPCODE		((ushort)0x0f00)
+#define CPM_CR_CHAN		((ushort)0x00f0)
+#define CPM_CR_FLG		((ushort)0x0001)
+
+/* Some commands (there are more...later)
+*/
+#define CPM_CR_INIT_TRX		((ushort)0x0000)
+#define CPM_CR_INIT_RX		((ushort)0x0001)
+#define CPM_CR_INIT_TX		((ushort)0x0002)
+#define CPM_CR_HUNT_MODE	((ushort)0x0003)
+#define CPM_CR_STOP_TX		((ushort)0x0004)
+#define CPM_CR_RESTART_TX	((ushort)0x0006)
+#define CPM_CR_SET_GADDR	((ushort)0x0008)
+
+/* Channel numbers.
+*/
+#define CPM_CR_CH_SCC1		((ushort)0x0000)
+#define CPM_CR_CH_I2C		((ushort)0x0001)    /* I2C and IDMA1 */
+#define CPM_CR_CH_SCC2		((ushort)0x0004)
+#define CPM_CR_CH_SPI		((ushort)0x0005)    /* SPI/IDMA2/Timers */
+#define CPM_CR_CH_SCC3		((ushort)0x0008)
+#define CPM_CR_CH_SMC1		((ushort)0x0009)    /* SMC1 / DSP1 */
+#define CPM_CR_CH_SCC4		((ushort)0x000c)
+#define CPM_CR_CH_SMC2		((ushort)0x000d)    /* SMC2 / DSP2 */
+
+#define mk_cr_cmd(CH, CMD)	((CMD << 8) | (CH << 4))
+
+/*
+ * DPRAM defines and allocation functions
+ */
+#define CPM_SERIAL_BASE		0x1800
+#define CPM_I2C_BASE		0x1820
+#define CPM_SPI_BASE		0x1840
+#define CPM_FEC_BASE		0x1860
+#define CPM_SERIAL2_BASE	0x18e0
+#define CPM_SCC_BASE		0x1900
+#define CPM_POST_BASE		0x1980
+#define CPM_WLKBD_BASE		0x1a00
+
+#define BD_IIC_START	((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+extern	cpm8xx_t	*cpmp;		/* Pointer to comm processor */
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+	ushort	cbd_sc;		/* Status and Control */
+	ushort	cbd_datlen;	/* Data length in buffer */
+	uint	cbd_bufaddr;	/* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
+#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
+#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
+#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
+#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
+#define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
+#define BD_SC_CM	((ushort)0x0200)	/* Continuous mode */
+#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
+#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
+#define BD_SC_BR	((ushort)0x0020)	/* Break received */
+#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
+#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
+#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
+#define BD_SC_CD	((ushort)0x0001)	/* Carrier Detect lost */
+
+/* Parameter RAM offsets.
+*/
+#define PROFF_SCC1	((uint)0x0000)
+#define PROFF_IIC	((uint)0x0080)
+#define PROFF_REVNUM	((uint)0x00b0)
+#define PROFF_SCC2	((uint)0x0100)
+#define PROFF_SPI	((uint)0x0180)
+#define PROFF_SCC3	((uint)0x0200)
+#define PROFF_SMC1	((uint)0x0280)
+#define PROFF_SCC4	((uint)0x0300)
+#define PROFF_SMC2	((uint)0x0380)
+
+/* Define enough so I can at least use the serial port as a UART.
+ */
+typedef struct smc_uart {
+	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	smc_rfcr;	/* Rx function code */
+	u_char	smc_tfcr;	/* Tx function code */
+	ushort	smc_mrblr;	/* Max receive buffer length */
+	uint	smc_rstate;	/* Internal */
+	uint	smc_idp;	/* Internal */
+	ushort	smc_rbptr;	/* Internal */
+	ushort	smc_ibc;	/* Internal */
+	uint	smc_rxtmp;	/* Internal */
+	uint	smc_tstate;	/* Internal */
+	uint	smc_tdp;	/* Internal */
+	ushort	smc_tbptr;	/* Internal */
+	ushort	smc_tbc;	/* Internal */
+	uint	smc_txtmp;	/* Internal */
+	ushort	smc_maxidl;	/* Maximum idle characters */
+	ushort	smc_tmpidl;	/* Temporary idle counter */
+	ushort	smc_brklen;	/* Last received break length */
+	ushort	smc_brkec;	/* rcv'd break condition counter */
+	ushort	smc_brkcr;	/* xmt break count register */
+	ushort	smc_rmask;	/* Temporary bit mask */
+	u_char	res1[8];
+	ushort	smc_rpbase;	/* Relocation pointer */
+} smc_uart_t;
+
+/* Function code bits.
+*/
+#define SMC_EB	((u_char)0x10)	/* Set big endian byte order */
+
+/* SMC uart mode register.
+*/
+#define	SMCMR_REN	((ushort)0x0001)
+#define SMCMR_TEN	((ushort)0x0002)
+#define SMCMR_DM	((ushort)0x000c)
+#define SMCMR_SM_GCI	((ushort)0x0000)
+#define SMCMR_SM_UART	((ushort)0x0020)
+#define SMCMR_SM_TRANS	((ushort)0x0030)
+#define SMCMR_SM_MASK	((ushort)0x0030)
+#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
+#define SMCMR_REVD	SMCMR_PM_EVEN
+#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
+#define SMCMR_BS	SMCMR_PEN
+#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
+#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
+#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC2 as Centronics parallel printer.  It is half duplex, in that
+ * it can only receive or transmit.  The parameter ram values for
+ * each direction are either unique or properly overlap, so we can
+ * include them in one structure.
+ */
+typedef struct smc_centronics {
+	ushort	scent_rbase;
+	ushort	scent_tbase;
+	u_char	scent_cfcr;
+	u_char	scent_smask;
+	ushort	scent_mrblr;
+	uint	scent_rstate;
+	uint	scent_r_ptr;
+	ushort	scent_rbptr;
+	ushort	scent_r_cnt;
+	uint	scent_rtemp;
+	uint	scent_tstate;
+	uint	scent_t_ptr;
+	ushort	scent_tbptr;
+	ushort	scent_t_cnt;
+	uint	scent_ttemp;
+	ushort	scent_max_sl;
+	ushort	scent_sl_cnt;
+	ushort	scent_character1;
+	ushort	scent_character2;
+	ushort	scent_character3;
+	ushort	scent_character4;
+	ushort	scent_character5;
+	ushort	scent_character6;
+	ushort	scent_character7;
+	ushort	scent_character8;
+	ushort	scent_rccm;
+	ushort	scent_rccr;
+} smc_cent_t;
+
+/* Centronics Status Mask Register.
+*/
+#define SMC_CENT_F	((u_char)0x08)
+#define SMC_CENT_PE	((u_char)0x04)
+#define SMC_CENT_S	((u_char)0x02)
+
+/* SMC Event and Mask register.
+*/
+#define	SMCM_BRKE	((unsigned char)0x40)	/* When in UART Mode */
+#define	SMCM_BRK	((unsigned char)0x10)	/* When in UART Mode */
+#define	SMCM_TXE	((unsigned char)0x10)	/* When in Transparent Mode */
+#define	SMCM_BSY	((unsigned char)0x04)
+#define	SMCM_TX		((unsigned char)0x02)
+#define	SMCM_RX		((unsigned char)0x01)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST		((uint)0x00020000)
+#define CPM_BRG_EN		((uint)0x00010000)
+#define CPM_BRG_EXTC_INT	((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK2	((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK6	((uint)0x00008000)
+#define CPM_BRG_ATB		((uint)0x00002000)
+#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
+#define CPM_BRG_DIV16		((uint)0x00000001)
+
+/* SI Clock Route Register
+*/
+#define SICR_RCLK_SCC1_BRG1	((uint)0x00000000)
+#define SICR_TCLK_SCC1_BRG1	((uint)0x00000000)
+#define SICR_RCLK_SCC2_BRG2	((uint)0x00000800)
+#define SICR_TCLK_SCC2_BRG2	((uint)0x00000100)
+#define SICR_RCLK_SCC3_BRG3	((uint)0x00100000)
+#define SICR_TCLK_SCC3_BRG3	((uint)0x00020000)
+#define SICR_RCLK_SCC4_BRG4	((uint)0x18000000)
+#define SICR_TCLK_SCC4_BRG4	((uint)0x03000000)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP		((uint)0x00040000)
+#define SCC_GSMRH_GDE		((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
+#define SCC_GSMRH_REVD		((uint)0x00002000)
+#define SCC_GSMRH_TRX		((uint)0x00001000)
+#define SCC_GSMRH_TTX		((uint)0x00000800)
+#define SCC_GSMRH_CDP		((uint)0x00000400)
+#define SCC_GSMRH_CTSP		((uint)0x00000200)
+#define SCC_GSMRH_CDS		((uint)0x00000100)
+#define SCC_GSMRH_CTSS		((uint)0x00000080)
+#define SCC_GSMRH_TFL		((uint)0x00000040)
+#define SCC_GSMRH_RFW		((uint)0x00000020)
+#define SCC_GSMRH_TXSY		((uint)0x00000010)
+#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8		((uint)0x00000008)
+#define SCC_GSMRH_SYNL4		((uint)0x00000004)
+#define SCC_GSMRH_RTSM		((uint)0x00000002)
+#define SCC_GSMRH_RSYN		((uint)0x00000001)
+
+#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
+#define SCC_GSMRL_TCI		((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
+#define SCC_GSMRL_RINV		((uint)0x02000000)
+#define SCC_GSMRL_TINV		((uint)0x01000000)
+#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48	((uint)0x00800000)
+#define SCC_GSMRL_TPL_32	((uint)0x00600000)
+#define SCC_GSMRL_TPL_16	((uint)0x00400000)
+#define SCC_GSMRL_TPL_8		((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
+#define SCC_GSMRL_TPP_01	((uint)0x00100000)
+#define SCC_GSMRL_TPP_10	((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
+#define SCC_GSMRL_TEND		((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
+#define SCC_GSMRL_ENR		((uint)0x00000020)
+#define SCC_GSMRL_ENT		((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
+
+#define SCC_TODR_TOD		((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define	SCCM_TXE	((unsigned char)0x10)
+#define	SCCM_BSY	((unsigned char)0x04)
+#define	SCCM_TX		((unsigned char)0x02)
+#define	SCCM_RX		((unsigned char)0x01)
+
+typedef struct scc_param {
+	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	scc_rfcr;	/* Rx function code */
+	u_char	scc_tfcr;	/* Tx function code */
+	ushort	scc_mrblr;	/* Max receive buffer length */
+	uint	scc_rstate;	/* Internal */
+	uint	scc_idp;	/* Internal */
+	ushort	scc_rbptr;	/* Internal */
+	ushort	scc_ibc;	/* Internal */
+	uint	scc_rxtmp;	/* Internal */
+	uint	scc_tstate;	/* Internal */
+	uint	scc_tdp;	/* Internal */
+	ushort	scc_tbptr;	/* Internal */
+	ushort	scc_tbc;	/* Internal */
+	uint	scc_txtmp;	/* Internal */
+	uint	scc_rcrc;	/* Internal */
+	uint	scc_tcrc;	/* Internal */
+} sccp_t;
+
+/* Function code bits.
+*/
+#define SCC_EB	((u_char)0x10)	/* Set big endian byte order */
+
+/* CPM Ethernet through SCCx.
+ */
+typedef struct scc_enet {
+	sccp_t	sen_genscc;
+	uint	sen_cpres;	/* Preset CRC */
+	uint	sen_cmask;	/* Constant mask for CRC */
+	uint	sen_crcec;	/* CRC Error counter */
+	uint	sen_alec;	/* alignment error counter */
+	uint	sen_disfc;	/* discard frame counter */
+	ushort	sen_pads;	/* Tx short frame pad character */
+	ushort	sen_retlim;	/* Retry limit threshold */
+	ushort	sen_retcnt;	/* Retry limit counter */
+	ushort	sen_maxflr;	/* maximum frame length register */
+	ushort	sen_minflr;	/* minimum frame length register */
+	ushort	sen_maxd1;	/* maximum DMA1 length */
+	ushort	sen_maxd2;	/* maximum DMA2 length */
+	ushort	sen_maxd;	/* Rx max DMA */
+	ushort	sen_dmacnt;	/* Rx DMA counter */
+	ushort	sen_maxb;	/* Max BD byte count */
+	ushort	sen_gaddr1;	/* Group address filter */
+	ushort	sen_gaddr2;
+	ushort	sen_gaddr3;
+	ushort	sen_gaddr4;
+	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf0rba;	/* Internal */
+	uint	sen_tbuf0crc;	/* Internal */
+	ushort	sen_tbuf0bcnt;	/* Internal */
+	ushort	sen_paddrh;	/* physical address (MSB) */
+	ushort	sen_paddrm;
+	ushort	sen_paddrl;	/* physical address (LSB) */
+	ushort	sen_pper;	/* persistence */
+	ushort	sen_rfbdptr;	/* Rx first BD pointer */
+	ushort	sen_tfbdptr;	/* Tx first BD pointer */
+	ushort	sen_tlbdptr;	/* Tx last BD pointer */
+	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf1rba;	/* Internal */
+	uint	sen_tbuf1crc;	/* Internal */
+	ushort	sen_tbuf1bcnt;	/* Internal */
+	ushort	sen_txlen;	/* Tx Frame length counter */
+	ushort	sen_iaddr1;	/* Individual address filter */
+	ushort	sen_iaddr2;
+	ushort	sen_iaddr3;
+	ushort	sen_iaddr4;
+	ushort	sen_boffcnt;	/* Backoff counter */
+
+	/* NOTE: Some versions of the manual have the following items
+	 * incorrectly documented.  Below is the proper order.
+	 */
+	ushort	sen_taddrh;	/* temp address (MSB) */
+	ushort	sen_taddrm;
+	ushort	sen_taddrl;	/* temp address (LSB) */
+} scc_enet_t;
+
+/*********************************************************************/
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
+#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
+#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
+#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
+#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
+#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
+#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
+#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
+#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
+#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
+#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
+#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
+#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
+#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
+#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
+#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
+#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
+#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_WRAP		((ushort)0x2000)
+#define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_LAST		((ushort)0x0800)
+#define BD_ENET_RX_FIRST	((ushort)0x0400)
+#define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_LG		((ushort)0x0020)
+#define BD_ENET_RX_NO		((ushort)0x0010)
+#define BD_ENET_RX_SH		((ushort)0x0008)
+#define BD_ENET_RX_CR		((ushort)0x0004)
+#define BD_ENET_RX_OV		((ushort)0x0002)
+#define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY	((ushort)0x8000)
+#define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_WRAP		((ushort)0x2000)
+#define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_LAST		((ushort)0x0800)
+#define BD_ENET_TX_TC		((ushort)0x0400)
+#define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_HB		((ushort)0x0100)
+#define BD_ENET_TX_LC		((ushort)0x0080)
+#define BD_ENET_TX_RL		((ushort)0x0040)
+#define BD_ENET_TX_RCMASK	((ushort)0x003c)
+#define BD_ENET_TX_UN		((ushort)0x0002)
+#define BD_ENET_TX_CSL		((ushort)0x0001)
+#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+	sccp_t	scc_genscc;
+	uint	scc_res1;	/* Reserved */
+	uint	scc_res2;	/* Reserved */
+	ushort	scc_maxidl;	/* Maximum idle chars */
+	ushort	scc_idlc;	/* temp idle counter */
+	ushort	scc_brkcr;	/* Break count register */
+	ushort	scc_parec;	/* receive parity error counter */
+	ushort	scc_frmec;	/* receive framing error counter */
+	ushort	scc_nosec;	/* receive noise counter */
+	ushort	scc_brkec;	/* receive break condition counter */
+	ushort	scc_brkln;	/* last received break length */
+	ushort	scc_uaddr1;	/* UART address character 1 */
+	ushort	scc_uaddr2;	/* UART address character 2 */
+	ushort	scc_rtemp;	/* Temp storage */
+	ushort	scc_toseq;	/* Transmit out of sequence char */
+	ushort	scc_char1;	/* control character 1 */
+	ushort	scc_char2;	/* control character 2 */
+	ushort	scc_char3;	/* control character 3 */
+	ushort	scc_char4;	/* control character 4 */
+	ushort	scc_char5;	/* control character 5 */
+	ushort	scc_char6;	/* control character 6 */
+	ushort	scc_char7;	/* control character 7 */
+	ushort	scc_char8;	/* control character 8 */
+	ushort	scc_rccm;	/* receive control character mask */
+	ushort	scc_rccr;	/* receive control character register */
+	ushort	scc_rlbc;	/* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR		((ushort)0x1000)
+#define UART_SCCM_GLT		((ushort)0x0800)
+#define UART_SCCM_AB		((ushort)0x0200)
+#define UART_SCCM_IDL		((ushort)0x0100)
+#define UART_SCCM_GRA		((ushort)0x0080)
+#define UART_SCCM_BRKE		((ushort)0x0040)
+#define UART_SCCM_BRKS		((ushort)0x0020)
+#define UART_SCCM_CCR		((ushort)0x0008)
+#define UART_SCCM_BSY		((ushort)0x0004)
+#define UART_SCCM_TX		((ushort)0x0002)
+#define UART_SCCM_RX		((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC		((ushort)0x8000)
+#define SCU_PSMR_SL		((ushort)0x4000)
+#define SCU_PSMR_CL		((ushort)0x3000)
+#define SCU_PSMR_UM		((ushort)0x0c00)
+#define SCU_PSMR_FRZ		((ushort)0x0200)
+#define SCU_PSMR_RZS		((ushort)0x0100)
+#define SCU_PSMR_SYN		((ushort)0x0080)
+#define SCU_PSMR_DRT		((ushort)0x0040)
+#define SCU_PSMR_PEN		((ushort)0x0010)
+#define SCU_PSMR_RPM		((ushort)0x000c)
+#define SCU_PSMR_REVP		((ushort)0x0008)
+#define SCU_PSMR_TPM		((ushort)0x0003)
+#define SCU_PSMR_TEVP		((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+	sccp_t	st_genscc;
+	uint	st_cpres;	/* Preset CRC */
+	uint	st_cmask;	/* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST		((ushort)0x0800)
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
+	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
+	u_char	iic_rfcr;	/* Rx function code */
+	u_char	iic_tfcr;	/* Tx function code */
+	ushort	iic_mrblr;	/* Max receive buffer length */
+	uint	iic_rstate;	/* Internal */
+	uint	iic_rdp;	/* Internal */
+	ushort	iic_rbptr;	/* Internal */
+	ushort	iic_rbc;	/* Internal */
+	uint	iic_rxtmp;	/* Internal */
+	uint	iic_tstate;	/* Internal */
+	uint	iic_tdp;	/* Internal */
+	ushort	iic_tbptr;	/* Internal */
+	ushort	iic_tbc;	/* Internal */
+	uint	iic_txtmp;	/* Internal */
+	uint	iic_res;	/* reserved */
+	ushort	iic_rpbase;	/* Relocation pointer */
+	ushort	iic_res2;	/* reserved */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
+	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
+	u_char	spi_rfcr;	/* Rx function code */
+	u_char	spi_tfcr;	/* Tx function code */
+	ushort	spi_mrblr;	/* Max receive buffer length */
+	uint	spi_rstate;	/* Internal */
+	uint	spi_rdp;	/* Internal */
+	ushort	spi_rbptr;	/* Internal */
+	ushort	spi_rbc;	/* Internal */
+	uint	spi_rxtmp;	/* Internal */
+	uint	spi_tstate;	/* Internal */
+	uint	spi_tdp;	/* Internal */
+	ushort	spi_tbptr;	/* Internal */
+	ushort	spi_tbc;	/* Internal */
+	uint	spi_txtmp;	/* Internal */
+	uint	spi_res;
+	ushort	spi_rpbase;	/* Relocation pointer */
+	ushort	spi_res2;
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
+#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
+#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
+#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
+#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
+#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
+#define SPMODE_EN	((ushort)0x0100)	/* Enable */
+#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
+#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
+
+#define SPMODE_LEN(x)	((((x) - 1) & 0xF) << 4)
+#define SPMODE_PM(x)	((x) & 0xF)
+
+/* HDLC parameter RAM.
+*/
+
+typedef struct hdlc_pram_s {
+	/*
+	 * SCC parameter RAM
+	 */
+	ushort	rbase;		/* Rx Buffer descriptor base address */
+	ushort	tbase;		/* Tx Buffer descriptor base address */
+	uchar	rfcr;		/* Rx function code */
+	uchar	tfcr;		/* Tx function code */
+	ushort	mrblr;		/* Rx buffer length */
+	ulong	rstate;		/* Rx internal state */
+	ulong	rptr;		/* Rx internal data pointer */
+	ushort	rbptr;		/* rb BD Pointer */
+	ushort	rcount;		/* Rx internal byte count */
+	ulong	rtemp;		/* Rx temp */
+	ulong	tstate;		/* Tx internal state */
+	ulong	tptr;		/* Tx internal data pointer */
+	ushort	tbptr;		/* Tx BD pointer */
+	ushort	tcount;		/* Tx byte count */
+	ulong	ttemp;		/* Tx temp */
+	ulong	rcrc;		/* temp receive CRC */
+	ulong	tcrc;		/* temp transmit CRC */
+	/*
+	 * HDLC specific parameter RAM
+	 */
+	uchar	res[4];		/* reserved */
+	ulong	c_mask;		/* CRC constant */
+	ulong	c_pres;		/* CRC preset */
+	ushort	disfc;		/* discarded frame counter */
+	ushort	crcec;		/* CRC error counter */
+	ushort	abtsc;		/* abort sequence counter */
+	ushort	nmarc;		/* nonmatching address rx cnt */
+	ushort	retrc;		/* frame retransmission cnt */
+	ushort	mflr;		/* maximum frame length reg */
+	ushort	max_cnt;	/* maximum length counter */
+	ushort	rfthr;		/* received frames threshold */
+	ushort	rfcnt;		/* received frames count */
+	ushort	hmask;		/* user defined frm addr mask */
+	ushort	haddr1;		/* user defined frm address 1 */
+	ushort	haddr2;		/* user defined frm address 2 */
+	ushort	haddr3;		/* user defined frm address 3 */
+	ushort	haddr4;		/* user defined frm address 4 */
+	ushort	tmp;		/* temp */
+	ushort	tmp_mb;		/* temp */
+} hdlc_pram_t;
+
+/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
+ * channels or devices.  All of these are presented to the PPC core
+ * as a single interrupt.  The CPM interrupt handler dispatches its
+ * own handlers, in a similar fashion to the PPC core handler.  We
+ * use the table as defined in the manuals (i.e. no special high
+ * priority and SCC1 == SCCa, etc...).
+ */
+#define CPMVEC_NR		32
+#define CPMVEC_OFFSET           0x00010000
+#define CPMVEC_PIO_PC15		((ushort)0x1f | CPMVEC_OFFSET)
+#define CPMVEC_SCC1		((ushort)0x1e | CPMVEC_OFFSET)
+#define CPMVEC_SCC2		((ushort)0x1d | CPMVEC_OFFSET)
+#define CPMVEC_SCC3		((ushort)0x1c | CPMVEC_OFFSET)
+#define CPMVEC_SCC4		((ushort)0x1b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC14		((ushort)0x1a | CPMVEC_OFFSET)
+#define CPMVEC_TIMER1		((ushort)0x19 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC13		((ushort)0x18 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC12		((ushort)0x17 | CPMVEC_OFFSET)
+#define CPMVEC_SDMA_CB_ERR	((ushort)0x16 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA1		((ushort)0x15 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA2		((ushort)0x14 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER2		((ushort)0x12 | CPMVEC_OFFSET)
+#define CPMVEC_RISCTIMER	((ushort)0x11 | CPMVEC_OFFSET)
+#define CPMVEC_I2C		((ushort)0x10 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC11		((ushort)0x0f | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC10		((ushort)0x0e | CPMVEC_OFFSET)
+#define CPMVEC_TIMER3		((ushort)0x0c | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC9		((ushort)0x0b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC8		((ushort)0x0a | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC7		((ushort)0x09 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER4		((ushort)0x07 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC6		((ushort)0x06 | CPMVEC_OFFSET)
+#define CPMVEC_SPI		((ushort)0x05 | CPMVEC_OFFSET)
+#define CPMVEC_SMC1		((ushort)0x04 | CPMVEC_OFFSET)
+#define CPMVEC_SMC2		((ushort)0x03 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC5		((ushort)0x02 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC4		((ushort)0x01 | CPMVEC_OFFSET)
+#define CPMVEC_ERROR		((ushort)0x00 | CPMVEC_OFFSET)
+
+void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
+
+/* CPM interrupt configuration vector.
+*/
+#define	CICR_SCD_SCC4		((uint)0x00c00000)	/* SCC4 @ SCCd */
+#define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
+#define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
+#define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
+#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrupt */
+#define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
+#define CICR_IEN		((uint)0x00000080)	/* Int. enable */
+#define CICR_SPS		((uint)0x00000001)	/* SCC Spread */
+#endif /* __CPM_8XX__ */
diff --git a/arch/powerpc/include/asm/e300.h b/arch/powerpc/include/asm/e300.h
new file mode 100644
index 0000000..bfef4df
--- /dev/null
+++ b/arch/powerpc/include/asm/e300.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ * Liberty Eran (liberty@freescale.com)
+ */
+
+#ifndef	__E300_H__
+#define __E300_H__
+
+#define PVR_E300C1	0x80830000
+#define PVR_E300C2	0x80840000
+#define PVR_E300C3	0x80850000
+#define PVR_E300C4	0x80860000
+
+/*
+ * Hardware Implementation-Dependent Register 0 (HID0)
+ */
+
+/* #define HID0 1008 already defined in processor.h */
+#define HID0_MASK_MACHINE_CHECK		     0x00000000
+#define HID0_ENABLE_MACHINE_CHECK	     0x80000000
+
+#define HID0_DISABLE_CACHE_PARITY	     0x00000000
+#define HID0_ENABLE_CACHE_PARITY	     0x40000000
+
+#define HID0_DISABLE_ADDRESS_PARITY	     0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_ADDRESS_PARITY	     0x20000000
+
+#define HID0_DISABLE_DATA_PARITY	     0x00000000 /* on mpc8349ads must be disabled */
+#define HID0_ENABLE_DATE_PARITY		     0x10000000
+
+#define HID0_CORE_CLK_OUT		     0x00000000
+#define HID0_CORE_CLK_OUT_DIV_2		     0x08000000
+
+#define HID0_ENABLE_ARTRY_OUT_PRECHARGE      0x00000000 /* on mpc8349ads must be enabled */
+#define HID0_DISABLE_ARTRY_OUT_PRECHARGE     0x01000000
+
+#define HID0_DISABLE_DOSE_MODE		     0x00000000
+#define HID0_ENABLE_DOSE_MODE		     0x00800000
+
+#define HID0_DISABLE_NAP_MODE		     0x00000000
+#define HID0_ENABLE_NAP_MODE		     0x00400000
+
+#define HID0_DISABLE_SLEEP_MODE		     0x00000000
+#define HID0_ENABLE_SLEEP_MODE		     0x00200000
+
+#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000
+#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT  0x00100000
+
+#define HID0_SOFT_RESET			     0x00010000
+
+#define HID0_DISABLE_INSTRUCTION_CACHE	     0x00000000
+#define HID0_ENABLE_INSTRUCTION_CACHE	     0x00008000
+
+#define HID0_DISABLE_DATA_CACHE		     0x00000000
+#define HID0_ENABLE_DATA_CACHE		     0x00004000
+
+#define HID0_LOCK_INSTRUCTION_CACHE	     0x00002000
+
+#define HID0_LOCK_DATA_CACHE		     0x00001000
+
+#define HID0_INVALIDATE_INSTRUCTION_CACHE    0x00000800
+
+#define HID0_INVALIDATE_DATA_CACHE	     0x00000400
+
+#define HID0_DISABLE_M_BIT		     0x00000000
+#define HID0_ENABLE_M_BIT		     0x00000080
+
+#define HID0_FBIOB			     0x00000010
+
+#define HID0_DISABLE_ADDRESS_BROADCAST	     0x00000000
+#define HID0_ENABLE_ADDRESS_BROADCAST	     0x00000008
+
+#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION  0x00000000
+#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001
+
+/*
+ * Hardware Implementation-Dependent Register 2 (HID2)
+ */
+#define HID2		1011
+
+#define HID2_LET       0x08000000
+#define HID2_HBE       0x00040000
+#define HID2_IWLCK_000 0x00000000 /* no ways locked */
+#define HID2_IWLCK_001 0x00002000 /* way 0 locked */
+#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
+#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
+#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
+#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
+#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
+
+#endif	/* __E300_H__ */
diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h
new file mode 100644
index 0000000..727f4a7
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_dma.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Freescale DMA Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_FSL_DMA_H_
+#define _ASM_FSL_DMA_H_
+
+#include <asm/types.h>
+
+#ifdef CONFIG_MPC83xx
+typedef struct fsl_dma {
+	uint	mr;		/* DMA mode register */
+#define FSL_DMA_MR_CS		0x00000001	/* Channel start */
+#define FSL_DMA_MR_CC		0x00000002	/* Channel continue */
+#define FSL_DMA_MR_CTM		0x00000004	/* Channel xfer mode */
+#define FSL_DMA_MR_CTM_DIRECT	0x00000004	/* Direct channel xfer mode */
+#define FSL_DMA_MR_EOTIE	0x00000080	/* End-of-transfer interrupt en */
+#define FSL_DMA_MR_PRC_MASK	0x00000c00	/* PCI read command */
+#define FSL_DMA_MR_SAHE		0x00001000	/* Source addr hold enable */
+#define FSL_DMA_MR_DAHE		0x00002000	/* Dest addr hold enable */
+#define FSL_DMA_MR_SAHTS_MASK	0x0000c000	/* Source addr hold xfer size */
+#define FSL_DMA_MR_DAHTS_MASK	0x00030000	/* Dest addr hold xfer size */
+#define FSL_DMA_MR_EMS_EN	0x00040000	/* Ext master start en */
+#define FSL_DMA_MR_IRQS		0x00080000	/* Interrupt steer */
+#define FSL_DMA_MR_DMSEN	0x00100000	/* Direct mode snooping en */
+#define FSL_DMA_MR_BWC_MASK	0x00e00000	/* Bandwidth/pause ctl */
+#define FSL_DMA_MR_DRCNT	0x0f000000	/* DMA request count */
+	uint	sr;		/* DMA status register */
+#define FSL_DMA_SR_EOCDI	0x00000001	/* End-of-chain/direct interrupt */
+#define FSL_DMA_SR_EOSI		0x00000002	/* End-of-segment interrupt */
+#define FSL_DMA_SR_CB		0x00000004	/* Channel busy */
+#define FSL_DMA_SR_TE		0x00000080	/* Transfer error */
+	uint	cdar;		/* DMA current descriptor address register */
+	char	res0[4];
+	uint	sar;		/* DMA source address register */
+	char	res1[4];
+	uint	dar;		/* DMA destination address register */
+	char	res2[4];
+	uint	bcr;		/* DMA byte count register */
+	uint	ndar;		/* DMA next descriptor address register */
+	uint	gsr;		/* DMA general status register (DMA3 ONLY!) */
+	char	res3[84];
+} fsl_dma_t;
+#else
+typedef struct fsl_dma {
+	uint	mr;		/* DMA mode register */
+#define FSL_DMA_MR_CS		0x00000001	/* Channel start */
+#define FSL_DMA_MR_CC		0x00000002	/* Channel continue */
+#define FSL_DMA_MR_CTM		0x00000004	/* Channel xfer mode */
+#define FSL_DMA_MR_CTM_DIRECT	0x00000004	/* Direct channel xfer mode */
+#define FSL_DMA_MR_CA		0x00000008	/* Channel abort */
+#define FSL_DMA_MR_CDSM		0x00000010
+#define FSL_DMA_MR_XFE		0x00000020	/* Extended features en */
+#define FSL_DMA_MR_EIE		0x00000040	/* Error interrupt en */
+#define FSL_DMA_MR_EOLSIE	0x00000080	/* End-of-lists interrupt en */
+#define FSL_DMA_MR_EOLNIE	0x00000100	/* End-of-links interrupt en */
+#define FSL_DMA_MR_EOSIE	0x00000200	/* End-of-seg interrupt en */
+#define FSL_DMA_MR_SRW		0x00000400	/* Single register write */
+#define FSL_DMA_MR_SAHE		0x00001000	/* Source addr hold enable */
+#define FSL_DMA_MR_DAHE		0x00002000	/* Dest addr hold enable */
+#define FSL_DMA_MR_SAHTS_MASK	0x0000c000	/* Source addr hold xfer size */
+#define FSL_DMA_MR_DAHTS_MASK	0x00030000	/* Dest addr hold xfer size */
+#define FSL_DMA_MR_EMS_EN	0x00040000	/* Ext master start en */
+#define FSL_DMA_MR_EMP_EN	0x00200000	/* Ext master pause en */
+#define FSL_DMA_MR_BWC_MASK	0x0f000000	/* Bandwidth/pause ctl */
+#define FSL_DMA_MR_BWC_DIS	0x0f000000	/* Bandwidth/pause ctl disable */
+	uint	sr;		/* DMA status register */
+#define FSL_DMA_SR_EOLSI	0x00000001	/* End-of-list interrupt */
+#define FSL_DMA_SR_EOSI		0x00000002	/* End-of-segment interrupt */
+#define FSL_DMA_SR_CB		0x00000004	/* Channel busy */
+#define FSL_DMA_SR_EOLNI	0x00000008	/* End-of-links interrupt */
+#define FSL_DMA_SR_PE		0x00000010	/* Programming error */
+#define FSL_DMA_SR_CH		0x00000020	/* Channel halted */
+#define FSL_DMA_SR_TE		0x00000080	/* Transfer error */
+	char	res0[4];
+	uint	clndar;		/* DMA current link descriptor address register */
+	uint	satr;		/* DMA source attributes register */
+#define FSL_DMA_SATR_ESAD_MASK		0x000001ff	/* Extended source addr */
+#define FSL_DMA_SATR_SREAD_NO_SNOOP	0x00040000	/* Read, don't snoop */
+#define FSL_DMA_SATR_SREAD_SNOOP	0x00050000	/* Read, snoop */
+#define FSL_DMA_SATR_SREAD_UNLOCK	0x00070000	/* Read, unlock l2 */
+#define FSL_DMA_SATR_STRAN_MASK		0x00f00000	/* Source interface  */
+#define FSL_DMA_SATR_SSME		0x01000000	/* Source stride en */
+#define FSL_DMA_SATR_SPCIORDER		0x02000000	/* PCI transaction order */
+#define FSL_DMA_SATR_STFLOWLVL_MASK	0x0c000000	/* RIO flow level */
+#define FSL_DMA_SATR_SBPATRMU		0x20000000	/* Bypass ATMU */
+	uint	sar;		/* DMA source address register */
+	uint	datr;		/* DMA destination attributes register */
+#define FSL_DMA_DATR_EDAD_MASK		0x000001ff	/* Extended dest addr */
+#define FSL_DMA_DATR_DWRITE_NO_SNOOP	0x00040000	/* Write, don't snoop */
+#define FSL_DMA_DATR_DWRITE_SNOOP	0x00050000	/* Write, snoop */
+#define FSL_DMA_DATR_DWRITE_ALLOC	0x00060000	/* Write, alloc l2 */
+#define FSL_DMA_DATR_DWRITE_LOCK	0x00070000	/* Write, lock l2 */
+#define FSL_DMA_DATR_DTRAN_MASK		0x00f00000	/* Dest interface  */
+#define FSL_DMA_DATR_DSME		0x01000000	/* Dest stride en */
+#define FSL_DMA_DATR_DPCIORDER		0x02000000	/* PCI transaction order */
+#define FSL_DMA_DATR_DTFLOWLVL_MASK	0x0c000000	/* RIO flow level */
+#define FSL_DMA_DATR_DBPATRMU		0x20000000	/* Bypass ATMU */
+	uint	dar;		/* DMA destination address register */
+	uint	bcr;		/* DMA byte count register */
+	char	res1[4];
+	uint	nlndar;		/* DMA next link descriptor address register */
+	char	res2[8];
+	uint	clabdar;	/* DMA current List - alternate base descriptor address Register */
+	char	res3[4];
+	uint	nlsdar;		/* DMA next list descriptor address register */
+	uint	ssr;		/* DMA source stride register */
+	uint	dsr;		/* DMA destination stride register */
+	char	res4[56];
+} fsl_dma_t;
+#endif /* !CONFIG_MPC83xx */
+
+#ifdef CONFIG_FSL_DMA
+void dma_init(void);
+int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
+#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
+void dma_meminit(uint val, uint size);
+#endif
+#endif
+
+#endif	/* _ASM_DMA_H_ */
diff --git a/arch/powerpc/include/asm/fsl_fdt.h b/arch/powerpc/include/asm/fsl_fdt.h
new file mode 100644
index 0000000..57bddf2
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_fdt.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+#ifndef _FSL_FDT_H_
+#define _FSL_FDT_H_
+
+void fdt_del_diu(void *blob);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_i2c.h b/arch/powerpc/include/asm/fsl_i2c.h
new file mode 100644
index 0000000..fbf32b9
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_i2c.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Freescale I2C Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
+ * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
+ * and Jeff Brown.
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
+ */
+
+#ifndef _ASM_FSL_I2C_H_
+#define _ASM_FSL_I2C_H_
+
+#include <asm/types.h>
+
+typedef struct fsl_i2c_base {
+
+	u8 adr;		/* I2C slave address */
+	u8 res0[3];
+#define I2C_ADR		0xFE
+#define I2C_ADR_SHIFT	1
+#define I2C_ADR_RES	~(I2C_ADR)
+
+	u8 fdr;		/* I2C frequency divider register */
+	u8 res1[3];
+#define IC2_FDR		0x3F
+#define IC2_FDR_SHIFT	0
+#define IC2_FDR_RES	~(IC2_FDR)
+
+	u8 cr;		/* I2C control redister	*/
+	u8 res2[3];
+#define I2C_CR_MEN	0x80
+#define I2C_CR_MIEN	0x40
+#define I2C_CR_MSTA	0x20
+#define I2C_CR_MTX	0x10
+#define I2C_CR_TXAK	0x08
+#define I2C_CR_RSTA	0x04
+#define I2C_CR_BIT6	0x02	/* required for workaround A004447 */
+#define I2C_CR_BCST	0x01
+
+	u8 sr;		/* I2C status register */
+	u8 res3[3];
+#define I2C_SR_MCF	0x80
+#define I2C_SR_MAAS	0x40
+#define I2C_SR_MBB	0x20
+#define I2C_SR_MAL	0x10
+#define I2C_SR_BCSTM	0x08
+#define I2C_SR_SRW	0x04
+#define I2C_SR_MIF	0x02
+#define I2C_SR_RXAK	0x01
+
+	u8 dr;		/* I2C data register */
+	u8 res4[3];
+#define I2C_DR		0xFF
+#define I2C_DR_SHIFT	0
+#define I2C_DR_RES	~(I2C_DR)
+
+	u8 dfsrr;	/* I2C digital filter sampling rate register */
+	u8 res5[3];
+#define I2C_DFSRR	0x3F
+#define I2C_DFSRR_SHIFT	0
+#define I2C_DFSRR_RES	~(I2C_DR)
+
+	/* Fill out the reserved block */
+	u8 res6[0xE8];
+} fsl_i2c_t;
+
+#ifdef CONFIG_DM_I2C
+struct fsl_i2c_dev {
+	struct fsl_i2c_base __iomem *base;      /* register base */
+	u32 i2c_clk;
+	u32 index;
+	u8 slaveadd;
+	uint speed;
+};
+#endif
+
+#endif	/* _ASM_I2C_H_ */
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
new file mode 100644
index 0000000..888640d
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_LAW_H_
+#define _FSL_LAW_H_
+
+#include <asm/io.h>
+#include <linux/log2.h>
+
+#define LAW_EN	0x80000000
+
+#define SET_LAW_ENTRY(idx, a, sz, trgt) \
+	{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
+
+#define SET_LAW(a, sz, trgt) \
+	{ .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
+
+enum law_size {
+	LAW_SIZE_4K = 0xb,
+	LAW_SIZE_8K,
+	LAW_SIZE_16K,
+	LAW_SIZE_32K,
+	LAW_SIZE_64K,
+	LAW_SIZE_128K,
+	LAW_SIZE_256K,
+	LAW_SIZE_512K,
+	LAW_SIZE_1M,
+	LAW_SIZE_2M,
+	LAW_SIZE_4M,
+	LAW_SIZE_8M,
+	LAW_SIZE_16M,
+	LAW_SIZE_32M,
+	LAW_SIZE_64M,
+	LAW_SIZE_128M,
+	LAW_SIZE_256M,
+	LAW_SIZE_512M,
+	LAW_SIZE_1G,
+	LAW_SIZE_2G,
+	LAW_SIZE_4G,
+	LAW_SIZE_8G,
+	LAW_SIZE_16G,
+	LAW_SIZE_32G,
+};
+
+#define law_size_bits(sz)	(__ilog2_u64(sz) - 1)
+#define lawar_size(x)	(1ULL << ((x & 0x3f) + 1))
+
+#ifdef CONFIG_FSL_CORENET
+enum law_trgt_if {
+	LAW_TRGT_IF_PCIE_1 = 0x00,
+	LAW_TRGT_IF_PCIE_2 = 0x01,
+	LAW_TRGT_IF_PCIE_3 = 0x02,
+	LAW_TRGT_IF_PCIE_4 = 0x03,
+	LAW_TRGT_IF_RIO_1 = 0x08,
+	LAW_TRGT_IF_RIO_2 = 0x09,
+
+	LAW_TRGT_IF_DDR_1 = 0x10,
+	LAW_TRGT_IF_DDR_2 = 0x11,	/* 2nd controller */
+	LAW_TRGT_IF_DDR_3 = 0x12,
+	LAW_TRGT_IF_DDR_4 = 0x13,
+	LAW_TRGT_IF_DDR_INTRLV = 0x14,
+	LAW_TRGT_IF_DDR_INTLV_34 = 0x15,
+	LAW_TRGT_IF_DDR_INTLV_123 = 0x17,
+	LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
+	LAW_TRGT_IF_BMAN = 0x18,
+	LAW_TRGT_IF_DCSR = 0x1d,
+	LAW_TRGT_IF_CCSR = 0x1e,
+	LAW_TRGT_IF_LBC = 0x1f,
+	LAW_TRGT_IF_QMAN = 0x3c,
+
+	LAW_TRGT_IF_MAPLE = 0x50,
+};
+#define LAW_TRGT_IF_DDR		LAW_TRGT_IF_DDR_1
+#define LAW_TRGT_IF_IFC		LAW_TRGT_IF_LBC
+#else
+enum law_trgt_if {
+	LAW_TRGT_IF_PCI = 0x00,
+	LAW_TRGT_IF_PCI_2 = 0x01,
+#ifndef CONFIG_ARCH_MPC8641
+	LAW_TRGT_IF_PCIE_1 = 0x02,
+#endif
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+	LAW_TRGT_IF_OCN_DSP = 0x03,
+#else
+#if !defined(CONFIG_ARCH_MPC8572) && !defined(CONFIG_ARCH_P2020)
+	LAW_TRGT_IF_PCIE_3 = 0x03,
+#endif
+#endif
+	LAW_TRGT_IF_LBC = 0x04,
+	LAW_TRGT_IF_CCSR = 0x08,
+	LAW_TRGT_IF_DSP_CCSR = 0x09,
+	LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
+	LAW_TRGT_IF_DDR_INTRLV = 0x0b,
+	LAW_TRGT_IF_RIO = 0x0c,
+#if defined(CONFIG_ARCH_BSC9132)
+	LAW_TRGT_IF_CLASS_DSP = 0x0d,
+#else
+	LAW_TRGT_IF_RIO_2 = 0x0d,
+#endif
+	LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
+	LAW_TRGT_IF_DDR = 0x0f,
+	LAW_TRGT_IF_DDR_2 = 0x16,	/* 2nd controller */
+	/* place holder for 3-way and 4-way interleaving */
+	LAW_TRGT_IF_DDR_3,
+	LAW_TRGT_IF_DDR_4,
+	LAW_TRGT_IF_DDR_INTLV_34,
+	LAW_TRGT_IF_DDR_INTLV_123,
+	LAW_TRGT_IF_DDR_INTLV_1234,
+};
+#define LAW_TRGT_IF_DDR_1	LAW_TRGT_IF_DDR
+#define LAW_TRGT_IF_PCI_1	LAW_TRGT_IF_PCI
+#define LAW_TRGT_IF_PCIX	LAW_TRGT_IF_PCI
+#define LAW_TRGT_IF_PCIE_2	LAW_TRGT_IF_PCI_2
+#define LAW_TRGT_IF_RIO_1	LAW_TRGT_IF_RIO
+#define LAW_TRGT_IF_IFC		LAW_TRGT_IF_LBC
+
+#ifdef CONFIG_ARCH_MPC8641
+#define LAW_TRGT_IF_PCIE_1	LAW_TRGT_IF_PCI
+#endif
+
+#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
+#define LAW_TRGT_IF_PCIE_3	LAW_TRGT_IF_PCI
+#endif
+#endif /* CONFIG_FSL_CORENET */
+
+struct law_entry {
+	int index;
+	phys_addr_t addr;
+	enum law_size size;
+	enum law_trgt_if trgt_id;
+};
+
+extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
+extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
+extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
+extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
+extern struct law_entry find_law(phys_addr_t addr);
+extern void disable_law(u8 idx);
+extern void init_laws(void);
+extern void print_laws(void);
+
+/* define in board code */
+extern struct law_entry law_table[];
+extern int num_law_entries;
+#endif
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
new file mode 100644
index 0000000..bf352d9
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -0,0 +1,535 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ASM_PPC_FSL_LBC_H
+#define __ASM_PPC_FSL_LBC_H
+
+#include <config.h>
+#include <common.h>
+
+#ifdef CONFIG_MPC85xx
+void lbc_sdram_init(void);
+#endif
+
+/* BR - Base Registers
+ */
+#define BR0				0x5000		/* Register offset to immr */
+#define BR1				0x5008
+#define BR2				0x5010
+#define BR3				0x5018
+#define BR4				0x5020
+#define BR5				0x5028
+#define BR6				0x5030
+#define BR7				0x5038
+
+#define BR_BA				0xFFFF8000
+#define BR_BA_SHIFT			15
+#define BR_XBA				0x00006000
+#define BR_XBA_SHIFT			13
+#define BR_PS				0x00001800
+#define BR_PS_SHIFT			11
+#define BR_PS_8				0x00000800	/* Port Size 8 bit */
+#define BR_PS_16			0x00001000	/* Port Size 16 bit */
+#define BR_PS_32			0x00001800	/* Port Size 32 bit */
+#define BR_DECC				0x00000600
+#define BR_DECC_SHIFT			9
+#define BR_DECC_OFF			0x00000000
+#define BR_DECC_CHK			0x00000200
+#define BR_DECC_CHK_GEN			0x00000400
+#define BR_WP				0x00000100
+#define BR_WP_SHIFT			8
+#define BR_MSEL				0x000000E0
+#define BR_MSEL_SHIFT			5
+#define BR_MS_GPCM			0x00000000	/* GPCM */
+#if !defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_ARCH_MPC8360)
+#define BR_MS_FCM			0x00000020	/* FCM */
+#endif
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8360)
+#define BR_MS_SDRAM			0x00000060	/* SDRAM */
+#elif defined(CONFIG_MPC85xx)
+#define BR_MS_SDRAM			0x00000000	/* SDRAM */
+#endif
+#define BR_MS_UPMA			0x00000080	/* UPMA */
+#define BR_MS_UPMB			0x000000A0	/* UPMB */
+#define BR_MS_UPMC			0x000000C0	/* UPMC */
+#if !defined(CONFIG_ARCH_MPC834X)
+#define BR_ATOM				0x0000000C
+#define BR_ATOM_SHIFT			2
+#endif
+#define BR_V				0x00000001
+#define BR_V_SHIFT			0
+
+#define BR_UPMx_TO_MSEL(x)		((x + 4) << BR_MSEL_SHIFT)
+
+#define UPMA			0
+#define UPMB			1
+#define UPMC			2
+
+#if defined(CONFIG_ARCH_MPC834X)
+#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
+#else
+#define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
+#endif
+
+/* Convert an address into the right format for the BR registers */
+#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
+#define BR_PHYS_ADDR(x)	\
+	((u32)(((x) & 0x0ffff8000ULL) | (((x) & 0x300000000ULL) >> 19)))
+#else
+#define BR_PHYS_ADDR(x) ((u32)(x) & 0xffff8000)
+#endif
+
+/* OR - Option Registers
+ */
+#define OR0				0x5004		/* Register offset to immr */
+#define OR1				0x500C
+#define OR2				0x5014
+#define OR3				0x501C
+#define OR4				0x5024
+#define OR5				0x502C
+#define OR6				0x5034
+#define OR7				0x503C
+
+#define OR_GPCM_AM			0xFFFF8000
+#define OR_GPCM_AM_SHIFT		15
+#define OR_GPCM_XAM			0x00006000
+#define OR_GPCM_XAM_SHIFT		13
+#define OR_GPCM_BCTLD			0x00001000
+#define OR_GPCM_BCTLD_SHIFT		12
+#define OR_GPCM_CSNT			0x00000800
+#define OR_GPCM_CSNT_SHIFT		11
+#define OR_GPCM_ACS			0x00000600
+#define OR_GPCM_ACS_SHIFT		9
+#define OR_GPCM_ACS_DIV2		0x00000600
+#define OR_GPCM_ACS_DIV4		0x00000400
+#define OR_GPCM_XACS			0x00000100
+#define OR_GPCM_XACS_SHIFT		8
+#define OR_GPCM_SCY			0x000000F0
+#define OR_GPCM_SCY_SHIFT		4
+#define OR_GPCM_SCY_1			0x00000010
+#define OR_GPCM_SCY_2			0x00000020
+#define OR_GPCM_SCY_3			0x00000030
+#define OR_GPCM_SCY_4			0x00000040
+#define OR_GPCM_SCY_5			0x00000050
+#define OR_GPCM_SCY_6			0x00000060
+#define OR_GPCM_SCY_7			0x00000070
+#define OR_GPCM_SCY_8			0x00000080
+#define OR_GPCM_SCY_9			0x00000090
+#define OR_GPCM_SCY_10			0x000000a0
+#define OR_GPCM_SCY_11			0x000000b0
+#define OR_GPCM_SCY_12			0x000000c0
+#define OR_GPCM_SCY_13			0x000000d0
+#define OR_GPCM_SCY_14			0x000000e0
+#define OR_GPCM_SCY_15			0x000000f0
+#define OR_GPCM_SETA			0x00000008
+#define OR_GPCM_SETA_SHIFT		3
+#define OR_GPCM_TRLX			0x00000004
+#define OR_GPCM_TRLX_SHIFT		2
+#define OR_GPCM_TRLX_CLEAR		0x00000000
+#define OR_GPCM_TRLX_SET		0x00000004
+#define OR_GPCM_EHTR			0x00000002
+#define OR_GPCM_EHTR_SHIFT		1
+#define OR_GPCM_EHTR_CLEAR		0x00000000
+#define OR_GPCM_EHTR_SET		0x00000002
+#if !defined(CONFIG_ARCH_MPC8308)
+#define OR_GPCM_EAD			0x00000001
+#define OR_GPCM_EAD_SHIFT		0
+#endif
+
+/* helpers to convert values into an OR address mask (GPCM mode) */
+#define P2SZ_TO_AM(s)	((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
+#define MEG_TO_AM(m)	P2SZ_TO_AM((m) << 20)
+
+#define OR_FCM_AM			0xFFFF8000
+#define OR_FCM_AM_SHIFT				15
+#define OR_FCM_XAM			0x00006000
+#define OR_FCM_XAM_SHIFT		13
+#define OR_FCM_BCTLD			0x00001000
+#define OR_FCM_BCTLD_SHIFT			12
+#define OR_FCM_PGS			0x00000400
+#define OR_FCM_PGS_SHIFT			10
+#define OR_FCM_CSCT			0x00000200
+#define OR_FCM_CSCT_SHIFT			 9
+#define OR_FCM_CST			0x00000100
+#define OR_FCM_CST_SHIFT			 8
+#define OR_FCM_CHT			0x00000080
+#define OR_FCM_CHT_SHIFT			 7
+#define OR_FCM_SCY			0x00000070
+#define OR_FCM_SCY_SHIFT			 4
+#define OR_FCM_SCY_1			0x00000010
+#define OR_FCM_SCY_2			0x00000020
+#define OR_FCM_SCY_3			0x00000030
+#define OR_FCM_SCY_4			0x00000040
+#define OR_FCM_SCY_5			0x00000050
+#define OR_FCM_SCY_6			0x00000060
+#define OR_FCM_SCY_7			0x00000070
+#define OR_FCM_RST			0x00000008
+#define OR_FCM_RST_SHIFT			 3
+#define OR_FCM_TRLX			0x00000004
+#define OR_FCM_TRLX_SHIFT			 2
+#define OR_FCM_EHTR			0x00000002
+#define OR_FCM_EHTR_SHIFT			 1
+
+#define OR_UPM_AM			0xFFFF8000
+#define OR_UPM_AM_SHIFT			15
+#define OR_UPM_XAM			0x00006000
+#define OR_UPM_XAM_SHIFT		13
+#define OR_UPM_BCTLD			0x00001000
+#define OR_UPM_BCTLD_SHIFT		12
+#define OR_UPM_BI			0x00000100
+#define OR_UPM_BI_SHIFT			8
+#define OR_UPM_TRLX			0x00000004
+#define OR_UPM_TRLX_SHIFT		2
+#define OR_UPM_EHTR			0x00000002
+#define OR_UPM_EHTR_SHIFT		1
+#define OR_UPM_EAD			0x00000001
+#define OR_UPM_EAD_SHIFT		0
+
+#define OR_SDRAM_AM			0xFFFF8000
+#define OR_SDRAM_AM_SHIFT		15
+#define OR_SDRAM_XAM			0x00006000
+#define OR_SDRAM_XAM_SHIFT		13
+#define OR_SDRAM_COLS			0x00001C00
+#define OR_SDRAM_COLS_SHIFT		10
+#define OR_SDRAM_MIN_COLS		7
+#define OR_SDRAM_ROWS			0x000001C0
+#define OR_SDRAM_ROWS_SHIFT		6
+#define OR_SDRAM_MIN_ROWS		9
+#define OR_SDRAM_PMSEL			0x00000020
+#define OR_SDRAM_PMSEL_SHIFT		5
+#define OR_SDRAM_EAD			0x00000001
+#define OR_SDRAM_EAD_SHIFT		0
+
+#define OR_AM_32KB			0xFFFF8000
+#define OR_AM_64KB			0xFFFF0000
+#define OR_AM_128KB			0xFFFE0000
+#define OR_AM_256KB			0xFFFC0000
+#define OR_AM_512KB			0xFFF80000
+#define OR_AM_1MB			0xFFF00000
+#define OR_AM_2MB			0xFFE00000
+#define OR_AM_4MB			0xFFC00000
+#define OR_AM_8MB			0xFF800000
+#define OR_AM_16MB			0xFF000000
+#define OR_AM_32MB			0xFE000000
+#define OR_AM_64MB			0xFC000000
+#define OR_AM_128MB			0xF8000000
+#define OR_AM_256MB			0xF0000000
+#define OR_AM_512MB			0xE0000000
+#define OR_AM_1GB			0xC0000000
+#define OR_AM_2GB			0x80000000
+#define OR_AM_4GB			0x00000000
+
+/* MxMR - UPM Machine A/B/C Mode Registers
+ */
+#define MxMR_MAD_MSK		0x0000003f /* Machine Address Mask	   */
+#define MxMR_TLFx_MSK		0x000003c0 /* Refresh Loop Field Mask	   */
+#define MxMR_WLFx_MSK		0x00003c00 /* Write Loop Field Mask	   */
+#define MxMR_WLFx_1X		0x00000400 /*	executed 1 time		   */
+#define MxMR_WLFx_2X		0x00000800 /*	executed 2 times	   */
+#define MxMR_WLFx_3X		0x00000c00 /*	executed 3 times	   */
+#define MxMR_WLFx_4X		0x00001000 /*	executed 4 times	   */
+#define MxMR_WLFx_5X		0x00001400 /*	executed 5 times	   */
+#define MxMR_WLFx_6X		0x00001800 /*	executed 6 times	   */
+#define MxMR_WLFx_7X		0x00001c00 /*	executed 7 times	   */
+#define MxMR_WLFx_8X		0x00002000 /*	executed 8 times	   */
+#define MxMR_WLFx_9X		0x00002400 /*	executed 9 times	   */
+#define MxMR_WLFx_10X		0x00002800 /*	executed 10 times	   */
+#define MxMR_WLFx_11X		0x00002c00 /*	executed 11 times	   */
+#define MxMR_WLFx_12X		0x00003000 /*	executed 12 times	   */
+#define MxMR_WLFx_13X		0x00003400 /*	executed 13 times	   */
+#define MxMR_WLFx_14X		0x00003800 /*	executed 14 times	   */
+#define MxMR_WLFx_15X		0x00003c00 /*	executed 15 times	   */
+#define MxMR_WLFx_16X		0x00000000 /*	executed 16 times	   */
+#define MxMR_RLFx_MSK		0x0003c000 /* Read Loop Field Mask	   */
+#define MxMR_GPL_x4DIS		0x00040000 /* GPL_A4 Ouput Line Disable	   */
+#define MxMR_G0CLx_MSK		0x00380000 /* General Line 0 Control Mask  */
+#define MxMR_DSx_1_CYCL		0x00000000 /* 1 cycle Disable Period	   */
+#define MxMR_DSx_2_CYCL		0x00400000 /* 2 cycle Disable Period	   */
+#define MxMR_DSx_3_CYCL		0x00800000 /* 3 cycle Disable Period	   */
+#define MxMR_DSx_4_CYCL		0x00c00000 /* 4 cycle Disable Period	   */
+#define MxMR_DSx_MSK		0x00c00000 /* Disable Timer Period Mask	   */
+#define MxMR_AMx_MSK		0x07000000 /* Addess Multiplex Size Mask   */
+#define MxMR_UWPL		0x08000000 /* LUPWAIT Polarity Mask	   */
+#define MxMR_OP_NORM		0x00000000 /* Normal Operation		   */
+#define MxMR_OP_WARR		0x10000000 /* Write to Array		   */
+#define MxMR_OP_RARR		0x20000000 /* Read from Array		   */
+#define MxMR_OP_RUNP		0x30000000 /* Run Pattern		   */
+#define MxMR_OP_MSK		0x30000000 /* Command Opcode Mask	   */
+#define MxMR_RFEN		0x40000000 /* Refresh Enable		   */
+#define MxMR_BSEL		0x80000000 /* Bus Select		   */
+
+#define LBLAWAR_EN			0x80000000
+#define LBLAWAR_4KB			0x0000000B
+#define LBLAWAR_8KB			0x0000000C
+#define LBLAWAR_16KB			0x0000000D
+#define LBLAWAR_32KB			0x0000000E
+#define LBLAWAR_64KB			0x0000000F
+#define LBLAWAR_128KB			0x00000010
+#define LBLAWAR_256KB			0x00000011
+#define LBLAWAR_512KB			0x00000012
+#define LBLAWAR_1MB			0x00000013
+#define LBLAWAR_2MB			0x00000014
+#define LBLAWAR_4MB			0x00000015
+#define LBLAWAR_8MB			0x00000016
+#define LBLAWAR_16MB			0x00000017
+#define LBLAWAR_32MB			0x00000018
+#define LBLAWAR_64MB			0x00000019
+#define LBLAWAR_128MB			0x0000001A
+#define LBLAWAR_256MB			0x0000001B
+#define LBLAWAR_512MB			0x0000001C
+#define LBLAWAR_1GB			0x0000001D
+#define LBLAWAR_2GB			0x0000001E
+
+/* LBCR - Local Bus Configuration Register
+ */
+#define LBCR_LDIS			0x80000000
+#define LBCR_LDIS_SHIFT			31
+#define LBCR_BCTLC			0x00C00000
+#define LBCR_BCTLC_SHIFT		22
+#define LBCR_LPBSE			0x00020000
+#define LBCR_LPBSE_SHIFT		17
+#define LBCR_EPAR			0x00010000
+#define LBCR_EPAR_SHIFT			16
+#define LBCR_BMT			0x0000FF00
+#define LBCR_BMT_SHIFT			8
+#define LBCR_BMTPS	 		0x0000000F
+#define LBCR_BMTPS_SHIFT 		0
+
+/* LCRR - Clock Ratio Register
+ */
+#define LCRR_DBYP			0x80000000
+#define LCRR_DBYP_SHIFT			31
+#define LCRR_BUFCMDC			0x30000000
+#define LCRR_BUFCMDC_SHIFT		28
+#define LCRR_BUFCMDC_1			0x10000000
+#define LCRR_BUFCMDC_2			0x20000000
+#define LCRR_BUFCMDC_3			0x30000000
+#define LCRR_BUFCMDC_4			0x00000000
+#define LCRR_ECL			0x03000000
+#define LCRR_ECL_SHIFT			24
+#define LCRR_ECL_4			0x00000000
+#define LCRR_ECL_5			0x01000000
+#define LCRR_ECL_6			0x02000000
+#define LCRR_ECL_7			0x03000000
+#define LCRR_EADC			0x00030000
+#define LCRR_EADC_SHIFT			16
+#define LCRR_EADC_1			0x00010000
+#define LCRR_EADC_2			0x00020000
+#define LCRR_EADC_3			0x00030000
+#define LCRR_EADC_4			0x00000000
+/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
+ * should always be zero on older parts that have a four bit CLKDIV.
+ */
+#define LCRR_CLKDIV			0x0000001F
+#define LCRR_CLKDIV_SHIFT		0
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
+	defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
+	defined(CONFIG_ARCH_MPC8560)
+#define LCRR_CLKDIV_2			0x00000002
+#define LCRR_CLKDIV_4			0x00000004
+#define LCRR_CLKDIV_8			0x00000008
+#elif defined(CONFIG_FSL_CORENET)
+#define LCRR_CLKDIV_8			0x00000002
+#define LCRR_CLKDIV_16			0x00000004
+#define LCRR_CLKDIV_32			0x00000008
+#else
+#define LCRR_CLKDIV_4			0x00000002
+#define LCRR_CLKDIV_8			0x00000004
+#define LCRR_CLKDIV_16			0x00000008
+#endif
+
+/* LTEDR - Transfer Error Check Disable Register
+ */
+#define LTEDR_BMD	0x80000000 /* Bus monitor disable				*/
+#define LTEDR_PARD	0x20000000 /* Parity error checking disabled			*/
+#define LTEDR_WPD	0x04000000 /* Write protect error checking diable		*/
+#define LTEDR_WARA	0x00800000 /* Write-after-read-atomic error checking diable	*/
+#define LTEDR_RAWA	0x00400000 /* Read-after-write-atomic error checking disable	*/
+#define LTEDR_CSD	0x00080000 /* Chip select error checking disable		*/
+
+/* FMR - Flash Mode Register
+ */
+#define FMR_CWTO               0x0000F000
+#define FMR_CWTO_SHIFT         12
+#define FMR_BOOT               0x00000800
+#define FMR_ECCM               0x00000100
+#define FMR_AL                 0x00000030
+#define FMR_AL_SHIFT           4
+#define FMR_OP                 0x00000003
+#define FMR_OP_SHIFT           0
+
+/* FIR - Flash Instruction Register
+ */
+#define FIR_OP0                        0xF0000000
+#define FIR_OP0_SHIFT          28
+#define FIR_OP1                        0x0F000000
+#define FIR_OP1_SHIFT          24
+#define FIR_OP2                        0x00F00000
+#define FIR_OP2_SHIFT          20
+#define FIR_OP3                        0x000F0000
+#define FIR_OP3_SHIFT          16
+#define FIR_OP4                        0x0000F000
+#define FIR_OP4_SHIFT          12
+#define FIR_OP5                        0x00000F00
+#define FIR_OP5_SHIFT          8
+#define FIR_OP6                        0x000000F0
+#define FIR_OP6_SHIFT          4
+#define FIR_OP7                        0x0000000F
+#define FIR_OP7_SHIFT          0
+#define FIR_OP_NOP             0x0 /* No operation and end of sequence */
+#define FIR_OP_CA              0x1 /* Issue current column address */
+#define FIR_OP_PA              0x2 /* Issue current block+page address */
+#define FIR_OP_UA              0x3 /* Issue user defined address */
+#define FIR_OP_CM0             0x4 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1             0x5 /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2             0x6 /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3             0x7 /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB              0x8 /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS              0x9 /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB              0xA /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS              0xB /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0             0xC /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1             0xD /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW             0xE /* Wait then read FBCR bytes */
+#define FIR_OP_RSW             0xF /* Wait then read 1 or 2 bytes */
+
+/* FCR - Flash Command Register
+ */
+#define FCR_CMD0               0xFF000000
+#define FCR_CMD0_SHIFT         24
+#define FCR_CMD1               0x00FF0000
+#define FCR_CMD1_SHIFT         16
+#define FCR_CMD2               0x0000FF00
+#define FCR_CMD2_SHIFT         8
+#define FCR_CMD3               0x000000FF
+#define FCR_CMD3_SHIFT         0
+/* FBAR - Flash Block Address Register
+ */
+#define FBAR_BLK               0x00FFFFFF
+
+/* FPAR - Flash Page Address Register
+ */
+#define FPAR_SP_PI             0x00007C00
+#define FPAR_SP_PI_SHIFT       10
+#define FPAR_SP_MS             0x00000200
+#define FPAR_SP_CI             0x000001FF
+#define FPAR_SP_CI_SHIFT       0
+#define FPAR_LP_PI             0x0003F000
+#define FPAR_LP_PI_SHIFT       12
+#define FPAR_LP_MS             0x00000800
+#define FPAR_LP_CI             0x000007FF
+#define FPAR_LP_CI_SHIFT       0
+
+/* LSDMR - SDRAM Machine Mode Register
+ */
+#define LSDMR_RFEN	(1 << (31 -  1))
+#define LSDMR_BSMA1516	(3 << (31 - 10))
+#define LSDMR_BSMA1617	(4 << (31 - 10))
+#define LSDMR_RFCR5	(3 << (31 - 16))
+#define LSDMR_RFCR8     (5 << (31 - 16))
+#define LSDMR_RFCR16	(7 << (31 - 16))
+#define LSDMR_PRETOACT3 (3 << (31 - 19))
+#define LSDMR_PRETOACT6 (5 << (31 - 19))
+#define LSDMR_PRETOACT7	(7 << (31 - 19))
+#define LSDMR_ACTTORW3	(3 << (31 - 22))
+#define LSDMR_ACTTORW7	(7 << (31 - 22))
+#define LSDMR_ACTTORW6	(6 << (31 - 22))
+#define LSDMR_BL8	(1 << (31 - 23))
+#define LSDMR_WRC2	(2 << (31 - 27))
+#define LSDMR_WRC3      (3 << (31 - 27))
+#define LSDMR_WRC4	(0 << (31 - 27))
+#define LSDMR_BUFCMD	(1 << (31 - 29))
+#define LSDMR_CL3	(3 << (31 - 31))
+
+#define LSDMR_OP_NORMAL	(0 << (31 - 4))
+#define LSDMR_OP_ARFRSH	(1 << (31 - 4))
+#define LSDMR_OP_SRFRSH	(2 << (31 - 4))
+#define LSDMR_OP_MRW	(3 << (31 - 4))
+#define LSDMR_OP_PRECH	(4 << (31 - 4))
+#define LSDMR_OP_PCHALL	(5 << (31 - 4))
+#define LSDMR_OP_ACTBNK	(6 << (31 - 4))
+#define LSDMR_OP_RWINV	(7 << (31 - 4))
+
+/* LTESR - Transfer Error Status Register
+ */
+#define LTESR_BM               0x80000000
+#define LTESR_FCT              0x40000000
+#define LTESR_PAR              0x20000000
+#define LTESR_WP               0x04000000
+#define LTESR_ATMW             0x00800000
+#define LTESR_ATMR             0x00400000
+#define LTESR_CS               0x00080000
+#define LTESR_CC               0x00000001
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+
+extern void print_lbc_regs(void);
+extern void init_early_memctl_regs(void);
+extern void upmconfig(uint upm, uint *table, uint size);
+
+#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
+#define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
+#define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr))
+#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
+#define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
+#define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
+#define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
+
+typedef struct lbc_bank {
+	u32     br;
+	u32     or;
+} lbc_bank_t;
+
+/* Local Bus Controller Registers */
+typedef struct fsl_lbc {
+	lbc_bank_t      bank[8];
+	u8	res1[40];
+	u32     mar;            /* LBC UPM Addr */
+	u8      res2[4];
+	u32     mamr;           /* LBC UPMA Mode */
+	u32     mbmr;           /* LBC UPMB Mode */
+	u32     mcmr;           /* LBC UPMC Mode */
+	u8      res3[8];
+	u32     mrtpr;          /* LBC Memory Refresh Timer Prescaler */
+	u32     mdr;            /* LBC UPM Data */
+#ifdef CONFIG_FSL_ELBC
+	u8      res4[4];
+	u32     lsor;
+	u8      res5[12];
+	u32     lurt;           /* LBC UPM Refresh Timer */
+	u8	res6[4];
+#else
+	u8	res4[8];
+	u32     lsdmr;          /* LBC SDRAM Mode */
+	u8	res5[8];
+	u32     lurt;           /* LBC UPM Refresh Timer */
+	u32     lsrt;           /* LBC SDRAM Refresh Timer */
+#endif
+	u8      res7[8];
+	u32     ltesr;          /* LBC Transfer Error Status */
+	u32     ltedr;          /* LBC Transfer Error Disable */
+	u32     lteir;          /* LBC Transfer Error IRQ */
+	u32     lteatr;         /* LBC Transfer Error Attrs */
+	u32     ltear;          /* LBC Transfer Error Addr */
+	u8      res8[12];
+	u32     lbcr;           /* LBC Configuration */
+	u32     lcrr;           /* LBC Clock Ratio */
+#ifdef CONFIG_NAND_FSL_ELBC
+	u8	res9[0x8];
+	u32     fmr;            /* Flash Mode Register */
+	u32     fir;            /* Flash Instruction Register */
+	u32     fcr;            /* Flash Command Register */
+	u32     fbar;           /* Flash Block Addr Register */
+	u32     fpar;           /* Flash Page Addr Register */
+	u32     fbcr;           /* Flash Byte Count Register */
+	u8      res10[0xF08];
+#else
+	u8      res9[0xF28];
+#endif
+} fsl_lbc_t;
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_PPC_FSL_LBC_H */
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
new file mode 100644
index 0000000..7ced50c
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_LIODN_H_
+#define _FSL_LIODN_H_
+
+#include <asm/types.h>
+#include <fsl_qbman.h>
+
+struct srio_liodn_id_table {
+	u32 id[2];
+	unsigned long reg_offset[2];
+	u8 num_ids;
+	u8 portid;
+};
+#define SET_SRIO_LIODN_1(port, idA) \
+	{ .id = { idA }, .num_ids = 1, .portid = port, \
+	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
+		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+	}
+
+#define SET_SRIO_LIODN_2(port, idA, idB) \
+	{ .id = { idA, idB }, .num_ids = 2, .portid = port, \
+	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
+		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+	  .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
+		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
+	}
+
+#define SET_SRIO_LIODN_BASE(port, id_a) \
+	{ .id = { id_a }, .num_ids = 1, .portid = port, \
+	  .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
+		+ (port - 1) * 0x200 \
+		+ CONFIG_SYS_FSL_SRIO_ADDR, \
+	}
+
+struct liodn_id_table {
+	const char * compat;
+	u32 id[2];
+	u8 num_ids;
+	phys_addr_t compat_offset;
+	unsigned long reg_offset;
+};
+
+struct fman_liodn_id_table {
+	/* Freescale FMan Device Tree binding was updated for FMan.
+	 * We need to support both new and old compatibles in order not to
+	 * break backward compatibility.
+	 */
+	const char *compat[2];
+	u32 id[2];
+	u8 num_ids;
+	phys_addr_t compat_offset;
+	unsigned long reg_offset;
+};
+
+extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid);
+extern void set_liodns(void);
+extern void fdt_fixup_liodn(void *blob);
+
+#define SET_LIODN_BASE_1(idA) \
+	{ .id = { idA }, .num_ids = 1, }
+
+#define SET_LIODN_BASE_2(idA, idB) \
+	{ .id = { idA, idB }, .num_ids = 2 }
+
+#define SET_FMAN_LIODN_ENTRY(name1, name2, idA, off, compatoff)\
+	{ .compat[0] = name1, \
+	  .compat[1] = name2, \
+	  .id = { idA }, .num_ids = 1, \
+	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
+	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	}
+
+#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
+	{ .compat = name, \
+	  .id = { idA }, .num_ids = 1, \
+	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
+	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	}
+
+#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
+	{ .compat = name, \
+	  .id = { idA, idB }, .num_ids = 2, \
+	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
+	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
+	}
+
+#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
+	SET_LIODN_ENTRY_1(compat, liodn, \
+		offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \
+		compatoff)
+
+#define SET_USB_LIODN(usbNum, compat, liodn) \
+	SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
+		CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
+
+#define SET_SATA_LIODN(sataNum, liodn) \
+	SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
+		CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
+
+#define SET_PCI_LIODN(compat, pciNum, liodn) \
+	SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
+		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
+#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
+	SET_LIODN_ENTRY_1(compat, liodn,\
+		offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
+/* reg nodes for DMA start @ 0x300 */
+#define SET_DMA_LIODN(dmaNum, compat, liodn) \
+	SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
+		CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
+
+#define SET_SDHC_LIODN(sdhcNum, liodn) \
+	SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
+		CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+
+#define SET_QE_LIODN(liodn) \
+	SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
+		CONFIG_SYS_MPC85xx_QE_OFFSET)
+
+#define SET_TDM_LIODN(liodn) \
+	SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
+		CONFIG_SYS_MPC85xx_TDM_OFFSET)
+
+#define SET_QMAN_LIODN(liodn) \
+	SET_LIODN_ENTRY_1("fsl,qman", liodn, \
+		offsetof(struct ccsr_qman, liodnr) + \
+		CONFIG_SYS_FSL_QMAN_OFFSET, \
+		CONFIG_SYS_FSL_QMAN_OFFSET)
+
+#define SET_BMAN_LIODN(liodn) \
+	SET_LIODN_ENTRY_1("fsl,bman", liodn, \
+		offsetof(struct ccsr_bman, liodnr) + \
+		CONFIG_SYS_FSL_BMAN_OFFSET, \
+		CONFIG_SYS_FSL_BMAN_OFFSET)
+
+#define SET_PME_LIODN(liodn) \
+	SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
+		CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
+		CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+
+#define SET_PMAN_LIODN(num, liodn) \
+	SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
+		offsetof(struct ccsr_pman, ppa1) + \
+		CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
+		CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
+
+/* -1 from portID due to how immap has the registers */
+#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
+	CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
+	offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
+
+#ifdef CONFIG_SYS_FMAN_V3
+/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
+#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
+	SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
+		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
+		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+
+/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
+#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
+	SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
+		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
+		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+
+/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
+#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
+	SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
+		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
+		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+#else
+/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
+#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
+	SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \
+		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
+		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+
+/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
+#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
+	SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \
+		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
+		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+#endif
+/*
+ * handle both old and new versioned SEC properties:
+ * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
+ */
+#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
+	SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
+		offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
+	SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
+		offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
+
+/* This is a bit evil since we treat rtic param as both a string & hex value */
+#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
+	SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
+		liodnA,	\
+		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+	SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
+		liodnA,	\
+		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, \
+		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+
+#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
+	SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
+		offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
+		CONFIG_SYS_FSL_SEC_OFFSET, 0)
+
+#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
+	SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
+	liodnA, \
+	offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
+	CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \
+	offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
+	CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
+
+#define SET_RMAN_LIODN(ibNum, liodn) \
+	SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
+		offsetof(struct ccsr_rman, mmitdr) + \
+		CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \
+		CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
+
+extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
+extern struct liodn_id_table raide_liodn_tbl[];
+extern struct fman_liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
+#ifdef CONFIG_SYS_SRIO
+extern struct srio_liodn_id_table srio_liodn_tbl[];
+extern int srio_liodn_tbl_sz;
+#endif
+extern struct liodn_id_table rman_liodn_tbl[];
+extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
+extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
+extern int rman_liodn_tbl_sz;
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h b/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h
new file mode 100644
index 0000000..a02b599
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_mpc83xx_serdes.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_MPC83XX_SERDES_H
+#define __FSL_MPC83XX_SERDES_H
+
+#ifndef CONFIG_MPC83XX_SERDES
+
+#include <config.h>
+
+#define FSL_SERDES_CLK_100		(0 << 28)
+#define FSL_SERDES_CLK_125		(1 << 28)
+#define FSL_SERDES_CLK_150		(3 << 28)
+#define FSL_SERDES_PROTO_SATA		0
+#define FSL_SERDES_PROTO_PEX		1
+#define FSL_SERDES_PROTO_PEX_X2		2
+#define FSL_SERDES_PROTO_SGMII		3
+#define FSL_SERDES_VDD_1V		1
+
+extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
+
+#endif /* !CONFIG_MPC83XX_SERDES */
+
+#endif /* __FSL_MPC83XX_SERDES_H */
diff --git a/arch/powerpc/include/asm/fsl_pamu.h b/arch/powerpc/include/asm/fsl_pamu.h
new file mode 100644
index 0000000..07e822b
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_pamu.h
@@ -0,0 +1,168 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __PAMU_H
+#define __PAMU_H
+
+#define CONFIG_NUM_PAMU		16
+#define NUM_PPAACT_ENTRIES	512
+#define NUM_SPAACT_ENTRIES	256
+
+/* PAMU_OFFSET to the next pamu space in ccsr */
+#define PAMU_OFFSET 0x1000
+
+#define PAMU_TABLE_ALIGNMENT 0x00001000
+
+#define PAMU_PAGE_SHIFT 12
+#define PAMU_PAGE_SIZE  4096U
+
+#define PAACE_M_COHERENCE_REQ   0x01
+
+#define PAACE_DA_HOST_CR                0x80
+#define PAACE_DA_HOST_CR_SHIFT          7
+
+#define PAACE_AF_PT                     0x00000002
+#define PAACE_AF_PT_SHIFT               1
+
+#define PAACE_PT_PRIMARY       0x0
+#define PAACE_PT_SECONDARY     0x1
+
+#define PPAACE_AF_WBAL			0xfffff000
+#define PPAACE_AF_WBAL_SHIFT		12
+
+#define	OME_NUMBER_ENTRIES      16   /* based on P4080 2.0 silicon plan */
+
+#define PAACE_IA_CID			0x00FF0000
+#define PAACE_IA_CID_SHIFT		16
+#define PAACE_IA_WCE			0x000000F0
+#define PAACE_IA_WCE_SHIFT		4
+#define PAACE_IA_ATM			0x0000000C
+#define PAACE_IA_ATM_SHIFT		2
+#define PAACE_IA_OTM			0x00000003
+#define PAACE_IA_OTM_SHIFT		0
+
+#define PAACE_OTM_NO_XLATE      0x00
+#define PAACE_OTM_IMMEDIATE     0x01
+#define PAACE_OTM_INDEXED       0x02
+#define PAACE_OTM_RESERVED      0x03
+#define PAACE_ATM_NO_XLATE      0x00
+#define PAACE_ATM_WINDOW_XLATE  0x01
+#define PAACE_ATM_PAGE_XLATE    0x02
+#define PAACE_ATM_WIN_PG_XLATE  \
+	(PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
+#define PAACE_WIN_TWBAL			0xfffff000
+#define PAACE_WIN_TWBAL_SHIFT		12
+#define PAACE_WIN_SWSE			0x00000fc0
+#define PAACE_WIN_SWSE_SHIFT		6
+
+#define PAACE_AF_AP			0x00000018
+#define PAACE_AF_AP_SHIFT		3
+#define PAACE_AF_DD			0x00000004
+#define PAACE_AF_DD_SHIFT		2
+#define PAACE_AF_PT			0x00000002
+#define PAACE_AF_PT_SHIFT		1
+#define PAACE_AF_V			0x00000001
+#define PAACE_AF_V_SHIFT		0
+#define PPAACE_AF_WSE			0x00000fc0
+#define PPAACE_AF_WSE_SHIFT		6
+#define PPAACE_AF_MW			0x00000020
+#define PPAACE_AF_MW_SHIFT		5
+
+#define PAACE_AP_PERMS_DENIED  0x0
+#define PAACE_AP_PERMS_QUERY   0x1
+#define PAACE_AP_PERMS_UPDATE  0x2
+#define PAACE_AP_PERMS_ALL     0x3
+
+#define SPAACE_AF_LIODN			0xffff0000
+#define SPAACE_AF_LIODN_SHIFT		16
+#define PAACE_V_VALID          0x1
+
+#define set_bf(v, m, x)             (v = ((v) & ~(m)) | (((x) << \
+					(m##_SHIFT)) & (m)))
+#define get_bf(v, m)            (((v) & (m)) >> (m##_SHIFT))
+
+#define DEFAULT_NUM_SUBWINDOWS		128
+#define PAMU_PCR_OFFSET 0xc10
+#define PAMU_PCR_PE	0x40000000
+
+struct pamu_addr_tbl {
+	phys_addr_t start_addr[10];
+	phys_addr_t end_addr[10];
+	phys_size_t size[10];
+};
+
+struct paace {
+	/* PAACE Offset 0x00 */
+	uint32_t wbah;			/* only valid for Primary PAACE */
+	uint32_t addr_bitfields;	/* See P/S PAACE_AF_* */
+
+	/* PAACE Offset 0x08 */
+	/* Interpretation of first 32 bits dependent on DD above */
+	union {
+		struct {
+			/* Destination ID, see PAACE_DID_* defines */
+			uint8_t did;
+			/* Partition ID */
+			uint8_t pid;
+			/* Snoop ID */
+			uint8_t snpid;
+			/* coherency_required : 1 reserved : 7 */
+			uint8_t coherency_required; /* See PAACE_DA_* */
+		} to_host;
+		struct {
+			/* Destination ID, see PAACE_DID_* defines */
+			uint8_t  did;
+			uint8_t  reserved1;
+			uint16_t reserved2;
+		} to_io;
+	} domain_attr;
+
+	/* Implementation attributes + window count + address & operation
+	 * translation modes
+	 */
+	uint32_t impl_attr;			/* See PAACE_IA_* */
+
+	/* PAACE Offset 0x10 */
+	/* Translated window base address */
+	uint32_t twbah;
+	uint32_t win_bitfields;			/* See PAACE_WIN_* */
+
+	/* PAACE Offset 0x18 */
+	/* first secondary paace entry */
+	uint32_t fspi;			/* only valid for Primary PAACE */
+	union {
+		struct {
+			uint8_t ioea;
+			uint8_t moea;
+			uint8_t ioeb;
+			uint8_t moeb;
+		} immed_ot;
+		struct {
+			uint16_t reserved;
+			uint16_t omi;
+		} index_ot;
+	} op_encode;
+
+	/* PAACE Offset 0x20 */
+	uint32_t reserved1[2];			/* not currently implemented */
+
+	/* PAACE Offset 0x28 */
+	uint32_t reserved2[2];			/* not currently implemented */
+
+	/* PAACE Offset 0x30 */
+	uint32_t reserved3[2];			/* not currently implemented */
+
+	/* PAACE Offset 0x38 */
+	uint32_t reserved4[2];			/* not currently implemented */
+
+};
+
+int pamu_init(void);
+void pamu_enable(void);
+void pamu_disable(void);
+int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn);
+int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
new file mode 100644
index 0000000..5088348
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -0,0 +1,273 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_PCI_H_
+#define __FSL_PCI_H_
+
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <pci.h>
+
+#define PEX_IP_BLK_REV_2_2	0x02080202
+#define PEX_IP_BLK_REV_2_3	0x02080203
+#define PEX_IP_BLK_REV_3_0	0x02080300
+
+/* Freescale-specific PCI config registers */
+#define FSL_PCI_PBFR		0x44
+
+#define FSL_PCIE_CFG_RDY	0x4b0
+#define FSL_PCIE_V3_CFG_RDY	0x1
+#define FSL_PROG_IF_AGENT	0x1
+
+#define PCI_LTSSM	0x404   /* PCIe Link Training, Status State Machine */
+#define  PCI_LTSSM_L0	0x16    /* L0 state */
+
+int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
+int fsl_is_pci_agent(struct pci_controller *hose);
+void fsl_pci_config_unlock(struct pci_controller *hose);
+void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
+
+/*
+ * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
+ */
+
+/*
+ * PCI Translation Registers
+ */
+typedef struct pci_outbound_window {
+	u32	potar;		/* 0x00 - Address */
+	u32	potear;		/* 0x04 - Address Extended */
+	u32	powbar;		/* 0x08 - Window Base Address */
+	u32	res1;
+	u32	powar;		/* 0x10 - Window Attributes */
+#define POWAR_EN	0x80000000
+#define POWAR_IO_READ	0x00080000
+#define POWAR_MEM_READ	0x00040000
+#define POWAR_IO_WRITE	0x00008000
+#define POWAR_MEM_WRITE	0x00004000
+	u32	res2[3];
+} pot_t;
+
+typedef struct pci_inbound_window {
+	u32	pitar;		/* 0x00 - Address */
+	u32	res1;
+	u32	piwbar;		/* 0x08 - Window Base Address */
+	u32	piwbear;	/* 0x0c - Window Base Address Extended */
+	u32	piwar;		/* 0x10 - Window Attributes */
+#define PIWAR_EN		0x80000000
+#define PIWAR_PF		0x20000000
+#define PIWAR_LOCAL		0x00f00000
+#define PIWAR_READ_SNOOP	0x00050000
+#define PIWAR_WRITE_SNOOP	0x00005000
+	u32	res2[3];
+} pit_t;
+
+/* PCI/PCI Express Registers */
+typedef struct ccsr_pci {
+	u32	cfg_addr;	/* 0x000 - PCI Configuration Address Register */
+	u32	cfg_data;	/* 0x004 - PCI Configuration Data Register */
+	u32	int_ack;	/* 0x008 - PCI Interrupt Acknowledge Register */
+	u32	out_comp_to;	/* 0x00C - PCI Outbound Completion Timeout Register */
+	u32	out_conf_to;	/* 0x010 - PCI Configuration Timeout Register */
+	u32	config;		/* 0x014 - PCIE CONFIG Register */
+	u32	int_status;	/* 0x018 - PCIE interrupt status register */
+	char	res2[4];
+	u32	pme_msg_det;	/* 0x020 - PCIE PME & message detect register */
+	u32	pme_msg_dis;	/* 0x024 - PCIE PME & message disable register */
+	u32	pme_msg_int_en;	/* 0x028 - PCIE PME & message interrupt enable register */
+	u32	pm_command;	/* 0x02c - PCIE PM Command register */
+	char	res3[2188];	/*     (0x8bc - 0x30 = 2188) */
+	u32	dbi_ro_wr_en;	/* 0x8bc - DBI read only write enable reg */
+	char	res4[824];	/*     (0xbf8 - 0x8c0 = 824) */
+	u32	block_rev1;	/* 0xbf8 - PCIE Block Revision register 1 */
+	u32	block_rev2;	/* 0xbfc - PCIE Block Revision register 2 */
+
+	pot_t	pot[5];		/* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
+	u32	res5[24];
+	pit_t	pmit;		/* 0xd00 - 0xd9c Inbound ATMU's MSI */
+	u32	res6[24];
+	pit_t	pit[4];		/* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
+
+#define PIT3 0
+#define PIT2 1
+#define PIT1 2
+
+#if 0
+	u32	potar0;		/* 0xc00 - PCI Outbound Transaction Address Register 0 */
+	u32	potear0;	/* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
+	char	res5[8];
+	u32	powar0;		/* 0xc10 - PCI Outbound Window Attributes Register 0 */
+	char	res6[12];
+	u32	potar1;		/* 0xc20 - PCI Outbound Transaction Address Register 1 */
+	u32	potear1;	/* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
+	u32	powbar1;	/* 0xc28 - PCI Outbound Window Base Address Register 1 */
+	char	res7[4];
+	u32	powar1;		/* 0xc30 - PCI Outbound Window Attributes Register 1 */
+	char	res8[12];
+	u32	potar2;		/* 0xc40 - PCI Outbound Transaction Address Register 2 */
+	u32	potear2;	/* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
+	u32	powbar2;	/* 0xc48 - PCI Outbound Window Base Address Register 2 */
+	char	res9[4];
+	u32	powar2;		/* 0xc50 - PCI Outbound Window Attributes Register 2 */
+	char	res10[12];
+	u32	potar3;		/* 0xc60 - PCI Outbound Transaction Address Register 3 */
+	u32	potear3;	/* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
+	u32	powbar3;	/* 0xc68 - PCI Outbound Window Base Address Register 3 */
+	char	res11[4];
+	u32	powar3;		/* 0xc70 - PCI Outbound Window Attributes Register 3 */
+	char	res12[12];
+	u32	potar4;		/* 0xc80 - PCI Outbound Transaction Address Register 4 */
+	u32	potear4;	/* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
+	u32	powbar4;	/* 0xc88 - PCI Outbound Window Base Address Register 4 */
+	char	res13[4];
+	u32	powar4;		/* 0xc90 - PCI Outbound Window Attributes Register 4 */
+	char	res14[268];
+	u32	pitar3;		/* 0xda0 - PCI Inbound Translation Address Register 3 */
+	char	res15[4];
+	u32	piwbar3;	/* 0xda8 - PCI Inbound Window Base Address Register 3 */
+	u32	piwbear3;	/* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
+	u32	piwar3;		/* 0xdb0 - PCI Inbound Window Attributes Register 3 */
+	char	res16[12];
+	u32	pitar2;		/* 0xdc0 - PCI Inbound Translation Address Register 2 */
+	char	res17[4];
+	u32	piwbar2;	/* 0xdc8 - PCI Inbound Window Base Address Register 2 */
+	u32	piwbear2;	/* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
+	u32	piwar2;		/* 0xdd0 - PCI Inbound Window Attributes Register 2 */
+	char	res18[12];
+	u32	pitar1;		/* 0xde0 - PCI Inbound Translation Address Register 1 */
+	char	res19[4];
+	u32	piwbar1;	/* 0xde8 - PCI Inbound Window Base Address Register 1 */
+	char	res20[4];
+	u32	piwar1;		/* 0xdf0 - PCI Inbound Window Attributes Register 1 */
+	char	res21[12];
+#endif
+	u32	pedr;		/* 0xe00 - PCI Error Detect Register */
+	u32	pecdr;		/* 0xe04 - PCI Error Capture Disable Register */
+	u32	peer;		/* 0xe08 - PCI Error Interrupt Enable Register */
+	u32	peattrcr;	/* 0xe0c - PCI Error Attributes Capture Register */
+	u32	peaddrcr;	/* 0xe10 - PCI Error Address Capture Register */
+/*	u32	perr_disr	 * 0xe10 - PCIE Erorr Disable Register */
+	u32	peextaddrcr;	/* 0xe14 - PCI	Error Extended Address Capture Register */
+	u32	pedlcr;		/* 0xe18 - PCI Error Data Low Capture Register */
+	u32	pedhcr;		/* 0xe1c - PCI Error Error Data High Capture Register */
+	u32	gas_timr;	/* 0xe20 - PCI Gasket Timer Register */
+/*	u32	perr_cap_stat;	 * 0xe20 - PCIE Error Capture Status Register */
+	char	res22[4];
+	u32	perr_cap0;	/* 0xe28 - PCIE Error Capture Register 0 */
+	u32	perr_cap1;	/* 0xe2c - PCIE Error Capture Register 1 */
+	u32	perr_cap2;	/* 0xe30 - PCIE Error Capture Register 2 */
+	u32	perr_cap3;	/* 0xe34 - PCIE Error Capture Register 3 */
+	char	res23[200];
+	u32	pdb_stat;	/* 0xf00 - PCIE Debug Status */
+	char	res24[16];
+	u32	pex_csr0;	/* 0xf14 - PEX Control/Status register 0*/
+	u32	pex_csr1;	/* 0xf18 - PEX Control/Status register 1*/
+	char	res25[228];
+} ccsr_fsl_pci_t;
+#define PCIE_CONFIG_PC	0x00020000
+#define PCIE_CONFIG_OB_CK	0x00002000
+#define PCIE_CONFIG_SAC	0x00000010
+#define PCIE_CONFIG_SP	0x80000002
+#define PCIE_CONFIG_SCC	0x80000001
+
+struct fsl_pci_info {
+	unsigned long regs;
+	pci_addr_t mem_bus;
+	phys_size_t mem_phys;
+	pci_size_t mem_size;
+	pci_addr_t io_bus;
+	phys_size_t io_phys;
+	pci_size_t io_size;
+	enum law_trgt_if law;
+	int pci_num;
+};
+
+void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info);
+int fsl_pci_init_port(struct fsl_pci_info *pci_info,
+				struct pci_controller *hose, int busno);
+int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
+			struct fsl_pci_info *pci_info);
+int fsl_pcie_init_board(int busno);
+
+#define SET_STD_PCI_INFO(x, num) \
+{			\
+	x.regs = CONFIG_SYS_PCI##num##_ADDR;	\
+	x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
+	x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
+	x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
+	x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
+	x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
+	x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
+	x.law = LAW_TRGT_IF_PCI_##num; \
+	x.pci_num = num; \
+}
+
+#define SET_STD_PCIE_INFO(x, num) \
+{			\
+	x.regs = CONFIG_SYS_PCIE##num##_ADDR;	\
+	x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
+	x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
+	x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
+	x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
+	x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
+	x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+	x.law = LAW_TRGT_IF_PCIE_##num; \
+	x.pci_num = num; \
+}
+
+#define __FT_FSL_PCI_SETUP(blob, compat, num) \
+	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
+
+#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
+	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
+
+#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
+#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
+
+#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
+#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
+#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
+#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
+
+#if !defined(CONFIG_PCI)
+#define FT_FSL_PCI_SETUP
+#elif defined(CONFIG_FSL_CORENET)
+#define FSL_PCIE_COMPAT	CONFIG_SYS_FSL_PCIE_COMPAT
+#define FT_FSL_PCI_SETUP \
+	FT_FSL_PCIE1_SETUP; \
+	FT_FSL_PCIE2_SETUP; \
+	FT_FSL_PCIE3_SETUP; \
+	FT_FSL_PCIE4_SETUP;
+#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
+#elif defined(CONFIG_MPC85xx)
+#define FSL_PCI_COMPAT	"fsl,mpc8540-pci"
+#ifdef CONFIG_SYS_FSL_PCIE_COMPAT
+#define FSL_PCIE_COMPAT	CONFIG_SYS_FSL_PCIE_COMPAT
+#else
+#define FSL_PCIE_COMPAT	"fsl,mpc8548-pcie"
+#endif
+#define FT_FSL_PCI_SETUP \
+	FT_FSL_PCI1_SETUP; \
+	FT_FSL_PCI2_SETUP; \
+	FT_FSL_PCIE1_SETUP; \
+	FT_FSL_PCIE2_SETUP; \
+	FT_FSL_PCIE3_SETUP;
+#define FT_FSL_PCIE_SETUP \
+	FT_FSL_PCIE1_SETUP; \
+	FT_FSL_PCIE2_SETUP; \
+	FT_FSL_PCIE3_SETUP;
+#elif defined(CONFIG_MPC86xx)
+#define FSL_PCI_COMPAT	"fsl,mpc8610-pci"
+#define FSL_PCIE_COMPAT	"fsl,mpc8641-pcie"
+#define FT_FSL_PCI_SETUP \
+	FT_FSL_PCI1_SETUP; \
+	FT_FSL_PCIE1_SETUP; \
+	FT_FSL_PCIE2_SETUP;
+#else
+#error FT_FSL_PCI_SETUP not defined
+#endif
+
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
new file mode 100644
index 0000000..b1fd6bd
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_PORTALS_H_
+#define _FSL_PORTALS_H_
+
+/* entries must be in order and contiguous */
+enum fsl_dpaa_dev {
+	FSL_HW_PORTAL_SEC,
+#ifdef CONFIG_SYS_DPAA_FMAN
+	FSL_HW_PORTAL_FMAN1,
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	FSL_HW_PORTAL_FMAN2,
+#endif
+#endif
+	FSL_HW_PORTAL_PME,
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+	FSL_HW_PORTAL_RAID_ENGINE,
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+	FSL_HW_PORTAL_RMAN,
+#endif
+#ifdef CONFIG_SYS_DPAA_DCE
+	FSL_HW_PORTAL_DCE,
+#endif
+
+};
+
+struct qportal_info {
+	u16	dliodn;	/* DQRR LIODN */
+	u16	fliodn;	/* frame data LIODN */
+	u16	liodn_offset;
+	u8	sdest;
+};
+
+#define SET_QP_INFO(dqrr, fdata, off, dest) \
+	{ .dliodn = dqrr, .fliodn = fdata, .liodn_offset = off, .sdest = dest }
+
+extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
+			  u32 *liodns, int liodn_offset);
+extern struct qportal_info qp_info[];
+extern void fdt_portal(void *blob, const char *compat, const char *container,
+			u64 addr, u32 size);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
new file mode 100644
index 0000000..64c1007
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_SECURE_BOOT_H
+#define __FSL_SECURE_BOOT_H
+#include <asm/config_mpc85xx.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#if defined(CONFIG_FSL_CORENET)
+#define CONFIG_SYS_PBI_FLASH_BASE		0xc0000000
+#elif defined(CONFIG_TARGET_BSC9132QDS)
+#define CONFIG_SYS_PBI_FLASH_BASE		0xc8000000
+#elif defined(CONFIG_TARGET_C29XPCIE)
+#define CONFIG_SYS_PBI_FLASH_BASE		0xcc000000
+#else
+#define CONFIG_SYS_PBI_FLASH_BASE		0xce000000
+#endif
+#define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
+
+#if defined(CONFIG_TARGET_B4860QDS) || \
+	defined(CONFIG_TARGET_B4420QDS) || \
+	defined(CONFIG_TARGET_T4160QDS) || \
+	defined(CONFIG_TARGET_T4240QDS) || \
+	defined(CONFIG_TARGET_T2080QDS) || \
+	defined(CONFIG_TARGET_T2080RDB) || \
+	defined(CONFIG_TARGET_T1040QDS) || \
+	defined(CONFIG_TARGET_T1040RDB) || \
+	defined(CONFIG_TARGET_T1040D4RDB) || \
+	defined(CONFIG_TARGET_T1042RDB) || \
+	defined(CONFIG_TARGET_T1042D4RDB) || \
+	defined(CONFIG_TARGET_T1042RDB_PI) || \
+	defined(CONFIG_ARCH_T1023) || \
+	defined(CONFIG_ARCH_T1024)
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_CPC_REINIT_F
+#endif
+#define CONFIG_KEY_REVOCATION
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#undef CONFIG_SYS_INIT_L3_ADDR
+#ifdef CONFIG_SYS_INIT_L3_VADDR
+#define CONFIG_SYS_INIT_L3_ADDR	\
+			(CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
+					0xbff00000
+#else
+#define CONFIG_SYS_INIT_L3_ADDR		0xbff00000
+#endif
+#endif
+
+#if defined(CONFIG_TARGET_C29XPCIE)
+#define CONFIG_KEY_REVOCATION
+#endif
+
+#if defined(CONFIG_ARCH_P3041)	||	\
+	defined(CONFIG_ARCH_P4080) ||	\
+	defined(CONFIG_ARCH_P5020) ||	\
+	defined(CONFIG_ARCH_P5040) ||	\
+	defined(CONFIG_ARCH_P2041)
+	#define	CONFIG_FSL_TRUST_ARCH_v1
+#endif
+
+#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
+/* The key used for verification of next level images
+ * is picked up from an Extension Table which has
+ * been verified by the ISBC (Internal Secure boot Code)
+ * in boot ROM of the SoC.
+ * The feature is only applicable in case of NOR boot and is
+ * not applicable in case of RAMBOOT (NAND, SD, SPI).
+ */
+#define CONFIG_FSL_ISBC_KEY_EXT
+#endif
+#endif /* #ifdef CONFIG_SECURE_BOOT */
+
+#ifdef CONFIG_CHAIN_OF_TRUST
+#ifdef CONFIG_SPL_BUILD
+/*
+ * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
+ * due to space crunch on CPC and thus malloc will not work.
+ */
+#define CONFIG_SPL_PPAACT_ADDR		0x2e000000
+#define CONFIG_SPL_SPAACT_ADDR		0x2f000000
+#define CONFIG_SPL_JR0_LIODN_S		454
+#define CONFIG_SPL_JR0_LIODN_NS		458
+/*
+ * Define the key hash for U-Boot here if public/private key pair used to
+ * sign U-boot are different from the SRK hash put in the fuse
+ * Example of defining KEY_HASH is
+ * #define CONFIG_SPL_UBOOT_KEY_HASH \
+ *      "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ * else leave it defined as NULL
+ */
+
+#define CONFIG_SPL_UBOOT_KEY_HASH	NULL
+#endif /* ifdef CONFIG_SPL_BUILD */
+
+#define CONFIG_FSL_SEC_MON
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * fsl_setenv_chain_of_trust() must be called from
+ * board_late_init()
+ */
+
+/* If Boot Script is not on NOR and is required to be copied on RAM */
+#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
+#define CONFIG_BS_HDR_ADDR_RAM		0x00010000
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x00800000
+#define CONFIG_BS_HDR_SIZE		0x00002000
+#define CONFIG_BS_ADDR_RAM		0x00012000
+#define CONFIG_BS_ADDR_DEVICE		0x00802000
+#define CONFIG_BS_SIZE			0x00001000
+
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
+#else
+
+/* The bootscript header address is different for B4860 because the NOR
+ * mapping is different on B4 due to reduced NOR size.
+ */
+#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xecc00000
+#elif defined(CONFIG_FSL_CORENET)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xe8e00000
+#elif defined(CONFIG_TARGET_BSC9132QDS)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0x88020000
+#elif defined(CONFIG_TARGET_C29XPCIE)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xec020000
+#else
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xee020000
+#endif
+
+#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
+
+#include <config_fsl_chain_trust.h>
+#endif /* #ifndef CONFIG_SPL_BUILD */
+#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
+#endif
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
new file mode 100644
index 0000000..ddde4f8
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_SERDES_H
+#define __FSL_SERDES_H
+
+#include <config.h>
+
+enum srds_prtcl {
+	/*
+	 * Nobody will check whether the device 'NONE' has been configured,
+	 * So use it to indicate if the serdes_prtcl_map has been initialized.
+	 */
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	PCIE3,
+	PCIE4,
+	SATA1,
+	SATA2,
+	SRIO1,
+	SRIO2,
+	SGMII_FM1_DTSEC1,
+	SGMII_FM1_DTSEC2,
+	SGMII_FM1_DTSEC3,
+	SGMII_FM1_DTSEC4,
+	SGMII_FM1_DTSEC5,
+	SGMII_FM1_DTSEC6,
+	SGMII_FM1_DTSEC9,
+	SGMII_FM1_DTSEC10,
+	SGMII_FM2_DTSEC1,
+	SGMII_FM2_DTSEC2,
+	SGMII_FM2_DTSEC3,
+	SGMII_FM2_DTSEC4,
+	SGMII_FM2_DTSEC5,
+	SGMII_FM2_DTSEC6,
+	SGMII_FM2_DTSEC9,
+	SGMII_FM2_DTSEC10,
+	SGMII_TSEC1,
+	SGMII_TSEC2,
+	SGMII_TSEC3,
+	SGMII_TSEC4,
+	XAUI_FM1,
+	XAUI_FM2,
+	AURORA,
+	CPRI1,
+	CPRI2,
+	CPRI3,
+	CPRI4,
+	CPRI5,
+	CPRI6,
+	CPRI7,
+	CPRI8,
+	XAUI_FM1_MAC9,
+	XAUI_FM1_MAC10,
+	XAUI_FM2_MAC9,
+	XAUI_FM2_MAC10,
+	HIGIG_FM1_MAC9,
+	HIGIG_FM1_MAC10,
+	HIGIG_FM2_MAC9,
+	HIGIG_FM2_MAC10,
+	QSGMII_FM1_A,		/* A indicates MACs 1-4 */
+	QSGMII_FM1_B,		/* B indicates MACs 5,6,9,10 */
+	QSGMII_FM2_A,
+	QSGMII_FM2_B,
+	XFI_FM1_MAC1,
+	XFI_FM1_MAC2,
+	XFI_FM1_MAC9,
+	XFI_FM1_MAC10,
+	XFI_FM2_MAC9,
+	XFI_FM2_MAC10,
+	INTERLAKEN,
+	QSGMII_SW1_A,		/* Indicates ports on L2 Switch */
+	QSGMII_SW1_B,
+	SGMII_2500_FM1_DTSEC1,
+	SGMII_2500_FM1_DTSEC2,
+	SGMII_2500_FM1_DTSEC3,
+	SGMII_2500_FM1_DTSEC4,
+	SGMII_2500_FM1_DTSEC5,
+	SGMII_2500_FM1_DTSEC6,
+	SGMII_2500_FM1_DTSEC9,
+	SGMII_2500_FM1_DTSEC10,
+	SGMII_2500_FM2_DTSEC1,
+	SGMII_2500_FM2_DTSEC2,
+	SGMII_2500_FM2_DTSEC3,
+	SGMII_2500_FM2_DTSEC4,
+	SGMII_2500_FM2_DTSEC5,
+	SGMII_2500_FM2_DTSEC6,
+	SGMII_2500_FM2_DTSEC9,
+	SGMII_2500_FM2_DTSEC10,
+	SGMII_SW1_MAC1,
+	SGMII_SW1_MAC2,
+	SGMII_SW1_MAC3,
+	SGMII_SW1_MAC4,
+	SGMII_SW1_MAC5,
+	SGMII_SW1_MAC6,
+	SERDES_PRCTL_COUNT	/* Keep this item the last one */
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+	FSL_SRDS_3  = 2,
+	FSL_SRDS_4  = 3,
+};
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+const char *serdes_clock_to_string(u32 clock);
+
+#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+#else
+int serdes_get_first_lane(enum srds_prtcl device);
+#endif
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
+void serdes_reset_rx(enum srds_prtcl device);
+#endif
+#endif
+
+#endif /* __FSL_SERDES_H */
diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h
new file mode 100644
index 0000000..9429233
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_srio.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_SRIO_H_
+#define _FSL_SRIO_H_
+
+#include <linux/log2.h>
+
+enum atmu_size {
+	ATMU_SIZE_4K = 0xb,
+	ATMU_SIZE_8K,
+	ATMU_SIZE_16K,
+	ATMU_SIZE_32K,
+	ATMU_SIZE_64K,
+	ATMU_SIZE_128K,
+	ATMU_SIZE_256K,
+	ATMU_SIZE_512K,
+	ATMU_SIZE_1M,
+	ATMU_SIZE_2M,
+	ATMU_SIZE_4M,
+	ATMU_SIZE_8M,
+	ATMU_SIZE_16M,
+	ATMU_SIZE_32M,
+	ATMU_SIZE_64M,
+	ATMU_SIZE_128M,
+	ATMU_SIZE_256M,
+	ATMU_SIZE_512M,
+	ATMU_SIZE_1G,
+	ATMU_SIZE_2G,
+	ATMU_SIZE_4G,
+	ATMU_SIZE_8G,
+	ATMU_SIZE_16G,
+	ATMU_SIZE_32G,
+	ATMU_SIZE_64G,
+};
+
+#define atmu_size_mask(sz)	(__ilog2_u64(sz) - 1)
+#define atmu_size_bytes(x)	(1ULL << ((x & 0x3f) + 1))
+
+extern void srio_init(void);
+#ifdef CONFIG_FSL_CORENET
+extern void srio_boot_master(int port);
+extern void srio_boot_master_release_slave(int port);
+#endif
+#endif
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
new file mode 100644
index 0000000..b6e4dd6
--- /dev/null
+++ b/arch/powerpc/include/asm/global_data.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include "config.h"
+#include "asm/types.h"
+
+/* Architecture-specific global data */
+struct arch_global_data {
+#if defined(CONFIG_FSL_ESDHC)
+	u32 sdhc_clk;
+#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT)
+	u8 sdhc_adapter;
+#endif
+#endif
+#if defined(CONFIG_MPC8xx)
+	unsigned long brg_clk;
+#endif
+#if defined(CONFIG_CPM2)
+	/* There are many clocks on the MPC8260 - see page 9-5 */
+	unsigned long vco_out;
+	unsigned long cpm_clk;
+	unsigned long scc_clk;
+	unsigned long brg_clk;
+#endif
+	/* TODO: sjg@chromium.org: Should these be unslgned long? */
+#if defined(CONFIG_MPC83xx)
+#ifdef CONFIG_CLK_MPC83XX
+	u32 core_clk;
+#else
+	/* There are other clocks in the MPC83XX */
+	u32 csb_clk;
+# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
+	u32 tsec1_clk;
+	u32 tsec2_clk;
+	u32 usbdr_clk;
+# elif defined(CONFIG_ARCH_MPC8309)
+	u32 usbdr_clk;
+# endif
+# if defined(CONFIG_ARCH_MPC834X)
+	u32 usbmph_clk;
+# endif /* CONFIG_ARCH_MPC834X */
+# if defined(CONFIG_ARCH_MPC8315)
+	u32 tdm_clk;
+# endif
+	u32 core_clk;
+	u32 enc_clk;
+	u32 lbiu_clk;
+	u32 lclk_clk;
+# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC837X)
+	u32 pciexp1_clk;
+	u32 pciexp2_clk;
+# endif
+# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
+	u32 sata_clk;
+# endif
+# if defined(CONFIG_ARCH_MPC8360)
+	u32 mem_sec_clk;
+# endif /* CONFIG_ARCH_MPC8360 */
+#endif
+#endif
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+	u32 lbc_clk;
+	void *cpu;
+#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+		defined(CONFIG_MPC86xx)
+	u32 i2c1_clk;
+	u32 i2c2_clk;
+#endif
+#if defined(CONFIG_QE)
+	u32 qe_clk;
+	u32 brg_clk;
+	uint mp_alloc_base;
+	uint mp_alloc_top;
+#endif /* CONFIG_QE */
+#if defined(CONFIG_FSL_LAW)
+	u32 used_laws;
+#endif
+#if defined(CONFIG_E500)
+	u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
+#endif
+	unsigned long reset_status;	/* reset status register at boot */
+#if defined(CONFIG_MPC83xx)
+	unsigned long arbiter_event_attributes;
+	unsigned long arbiter_event_address;
+#endif
+#if defined(CONFIG_CPM2)
+	unsigned int dp_alloc_base;
+	unsigned int dp_alloc_top;
+#endif
+#ifdef CONFIG_SYS_FPGA_COUNT
+	unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
+#endif
+#if defined(CONFIG_WD_MAX_RATE)
+	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
+#endif
+#if defined(CONFIG_LWMON5)
+	unsigned long kbd_status;
+#endif
+};
+
+#include <asm-generic/global_data.h>
+
+#if 1
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r2")
+#else /* We could use plain global data, but the resulting code is bigger */
+#define XTRN_DECLARE_GLOBAL_DATA_PTR	extern
+#define DECLARE_GLOBAL_DATA_PTR     XTRN_DECLARE_GLOBAL_DATA_PTR \
+				    gd_t *gd
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h
new file mode 100644
index 0000000..d49ad08
--- /dev/null
+++ b/arch/powerpc/include/asm/gpio.h
@@ -0,0 +1,2 @@
+#include <asm/arch/gpio.h>
+#include <asm-generic/gpio.h>
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
new file mode 100644
index 0000000..d02da64
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -0,0 +1,996 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2004-2011 Freescale Semiconductor, Inc.
+ *
+ * MPC83xx Internal Memory Map
+ *
+ * Contributors:
+ *	Dave Liu <daveliu@freescale.com>
+ *	Tanya Jiang <tanya.jiang@freescale.com>
+ *	Mandy Lavi <mandy.lavi@freescale.com>
+ *	Eran Liberty <liberty@freescale.com>
+ */
+#ifndef __IMMAP_83xx__
+#define __IMMAP_83xx__
+
+#include <fsl_immap.h>
+#include <asm/types.h>
+#include <asm/fsl_i2c.h>
+#include <asm/mpc8xxx_spi.h>
+#include <asm/fsl_lbc.h>
+#include <asm/fsl_dma.h>
+
+/*
+ * Local Access Window
+ */
+typedef struct law83xx {
+	u32 bar;		/* LBIU local access window base address register */
+	u32 ar;			/* LBIU local access window attribute register */
+} law83xx_t;
+
+/*
+ * System configuration registers
+ */
+typedef struct sysconf83xx {
+	u32 immrbar;		/* Internal memory map base address register */
+	u8 res0[0x04];
+	u32 altcbar;		/* Alternate configuration base address register */
+	u8 res1[0x14];
+	law83xx_t lblaw[4];	/* LBIU local access window */
+	u8 res2[0x20];
+	law83xx_t pcilaw[2];	/* PCI local access window */
+	u8 res3[0x10];
+	law83xx_t pcielaw[2];	/* PCI Express local access window */
+	u8 res4[0x10];
+	law83xx_t ddrlaw[2];	/* DDR local access window */
+	u8 res5[0x50];
+	u32 sgprl;		/* System General Purpose Register Low */
+	u32 sgprh;		/* System General Purpose Register High */
+	u32 spridr;		/* System Part and Revision ID Register */
+	u8 res6[0x04];
+	u32 spcr;		/* System Priority Configuration Register */
+	u32 sicrl;		/* System I/O Configuration Register Low */
+	u32 sicrh;		/* System I/O Configuration Register High */
+	u8 res7[0x04];
+	u32 sidcr0;		/* System I/O Delay Configuration Register 0 */
+	u32 sidcr1;		/* System I/O Delay Configuration Register 1 */
+	u32 ddrcdr;		/* DDR Control Driver Register */
+	u32 ddrdsr;		/* DDR Debug Status Register */
+	u32 obir;		/* Output Buffer Impedance Register */
+	u8 res8[0xC];
+	u32 pecr1;		/* PCI Express control register 1 */
+#if defined(CONFIG_ARCH_MPC830X)
+	u32 sdhccr;		/* eSDHC Control Registers for MPC830x */
+#else
+	u32 pecr2;		/* PCI Express control register 2 */
+#endif
+#if defined(CONFIG_ARCH_MPC8309)
+	u32 can_dbg_ctrl;
+	u32 res9a;
+	u32 gpr1;
+	u8 res9b[0xAC];
+#else
+	u8 res9[0xB8];
+#endif
+} sysconf83xx_t;
+
+/*
+ * Watch Dog Timer (WDT) Registers
+ */
+typedef struct wdt83xx {
+	u8 res0[4];
+	u32 swcrr;		/* System watchdog control register */
+	u32 swcnr;		/* System watchdog count register */
+	u8 res1[2];
+	u16 swsrr;		/* System watchdog service register */
+	u8 res2[0xF0];
+} wdt83xx_t;
+
+/*
+ * RTC/PIT Module Registers
+ */
+typedef struct rtclk83xx {
+	u32 cnr;		/* control register */
+	u32 ldr;		/* load register */
+	u32 psr;		/* prescale register */
+	u32 ctr;		/* counter value field register */
+	u32 evr;		/* event register */
+	u32 alr;		/* alarm register */
+	u8 res0[0xE8];
+} rtclk83xx_t;
+
+/*
+ * Global timer module
+ */
+typedef struct gtm83xx {
+	u8 cfr1;		/* Timer1/2 Configuration */
+	u8 res0[3];
+	u8 cfr2;		/* Timer3/4 Configuration */
+	u8 res1[11];
+	u16 mdr1;		/* Timer1 Mode Register */
+	u16 mdr2;		/* Timer2 Mode Register */
+	u16 rfr1;		/* Timer1 Reference Register */
+	u16 rfr2;		/* Timer2 Reference Register */
+	u16 cpr1;		/* Timer1 Capture Register */
+	u16 cpr2;		/* Timer2 Capture Register */
+	u16 cnr1;		/* Timer1 Counter Register */
+	u16 cnr2;		/* Timer2 Counter Register */
+	u16 mdr3;		/* Timer3 Mode Register */
+	u16 mdr4;		/* Timer4 Mode Register */
+	u16 rfr3;		/* Timer3 Reference Register */
+	u16 rfr4;		/* Timer4 Reference Register */
+	u16 cpr3;		/* Timer3 Capture Register */
+	u16 cpr4;		/* Timer4 Capture Register */
+	u16 cnr3;		/* Timer3 Counter Register */
+	u16 cnr4;		/* Timer4 Counter Register */
+	u16 evr1;		/* Timer1 Event Register */
+	u16 evr2;		/* Timer2 Event Register */
+	u16 evr3;		/* Timer3 Event Register */
+	u16 evr4;		/* Timer4 Event Register */
+	u16 psr1;		/* Timer1 Prescaler Register */
+	u16 psr2;		/* Timer2 Prescaler Register */
+	u16 psr3;		/* Timer3 Prescaler Register */
+	u16 psr4;		/* Timer4 Prescaler Register */
+	u8 res[0xC0];
+} gtm83xx_t;
+
+/*
+ * Integrated Programmable Interrupt Controller
+ */
+typedef struct ipic83xx {
+	u32 sicfr;		/* System Global Interrupt Configuration Register */
+	u32 sivcr;		/* System Global Interrupt Vector Register */
+	u32 sipnr_h;		/* System Internal Interrupt Pending Register - High */
+	u32 sipnr_l;		/* System Internal Interrupt Pending Register - Low */
+	u32 siprr_a;		/* System Internal Interrupt Group A Priority Register */
+	u32 siprr_b;		/* System Internal Interrupt Group B Priority Register */
+	u32 siprr_c;		/* System Internal Interrupt Group C Priority Register */
+	u32 siprr_d;		/* System Internal Interrupt Group D Priority Register */
+	u32 simsr_h;		/* System Internal Interrupt Mask Register - High */
+	u32 simsr_l;		/* System Internal Interrupt Mask Register - Low */
+	u32 sicnr;		/* System Internal Interrupt Control Register */
+	u32 sepnr;		/* System External Interrupt Pending Register */
+	u32 smprr_a;		/* System Mixed Interrupt Group A Priority Register */
+	u32 smprr_b;		/* System Mixed Interrupt Group B Priority Register */
+	u32 semsr;		/* System External Interrupt Mask Register */
+	u32 secnr;		/* System External Interrupt Control Register */
+	u32 sersr;		/* System Error Status Register */
+	u32 sermr;		/* System Error Mask Register */
+	u32 sercr;		/* System Error Control Register */
+	u32 sepcr;		/* System External Interrupt Polarity Control Register */
+	u32 sifcr_h;		/* System Internal Interrupt Force Register - High */
+	u32 sifcr_l;		/* System Internal Interrupt Force Register - Low */
+	u32 sefcr;		/* System External Interrupt Force Register */
+	u32 serfr;		/* System Error Force Register */
+	u32 scvcr;		/* System Critical Interrupt Vector Register */
+	u32 smvcr;		/* System Management Interrupt Vector Register */
+	u8 res[0x98];
+} ipic83xx_t;
+
+/*
+ * System Arbiter Registers
+ */
+typedef struct arbiter83xx {
+	u32 acr;		/* Arbiter Configuration Register */
+	u32 atr;		/* Arbiter Timers Register */
+	u8 res[4];
+	u32 aer;		/* Arbiter Event Register */
+	u32 aidr;		/* Arbiter Interrupt Definition Register */
+	u32 amr;		/* Arbiter Mask Register */
+	u32 aeatr;		/* Arbiter Event Attributes Register */
+	u32 aeadr;		/* Arbiter Event Address Register */
+	u32 aerr;		/* Arbiter Event Response Register */
+	u8 res1[0xDC];
+} arbiter83xx_t;
+
+/*
+ * Reset Module
+ */
+typedef struct reset83xx {
+	u32 rcwl;		/* Reset Configuration Word Low Register */
+	u32 rcwh;		/* Reset Configuration Word High Register */
+	u8 res0[8];
+	u32 rsr;		/* Reset Status Register */
+	u32 rmr;		/* Reset Mode Register */
+	u32 rpr;		/* Reset protection Register */
+	u32 rcr;		/* Reset Control Register */
+	u32 rcer;		/* Reset Control Enable Register */
+	u8 res1[0xDC];
+} reset83xx_t;
+
+/*
+ * Clock Module
+ */
+typedef struct clk83xx {
+	u32 spmr;		/* system PLL mode Register */
+	u32 occr;		/* output clock control Register */
+	u32 sccr;		/* system clock control Register */
+	u8 res0[0xF4];
+} clk83xx_t;
+
+/*
+ * Power Management Control Module
+ */
+typedef struct pmc83xx {
+	u32 pmccr;		/* PMC Configuration Register */
+	u32 pmcer;		/* PMC Event Register */
+	u32 pmcmr;		/* PMC Mask Register */
+	u32 pmccr1;		/* PMC Configuration Register 1 */
+	u32 pmccr2;		/* PMC Configuration Register 2 */
+	u8 res0[0xEC];
+} pmc83xx_t;
+
+/*
+ * General purpose I/O module
+ */
+typedef struct gpio83xx {
+	u32 dir;		/* direction register */
+	u32 odr;		/* open drain register */
+	u32 dat;		/* data register */
+	u32 ier;		/* interrupt event register */
+	u32 imr;		/* interrupt mask register */
+	u32 icr;		/* external interrupt control register */
+	u8 res0[0xE8];
+} gpio83xx_t;
+
+/*
+ * QE Ports Interrupts Registers
+ */
+typedef struct qepi83xx {
+	u8 res0[0xC];
+	u32 qepier;		/* QE Ports Interrupt Event Register */
+	u32 qepimr;		/* QE Ports Interrupt Mask Register */
+	u32 qepicr;		/* QE Ports Interrupt Control Register */
+	u8 res1[0xE8];
+} qepi83xx_t;
+
+/*
+ * QE Parallel I/O Ports
+ */
+typedef struct gpio_n {
+	u32 podr;		/* Open Drain Register */
+	u32 pdat;		/* Data Register */
+	u32 dir1;		/* direction register 1 */
+	u32 dir2;		/* direction register 2 */
+	u32 ppar1;		/* Pin Assignment Register 1 */
+	u32 ppar2;		/* Pin Assignment Register 2 */
+} gpio_n_t;
+
+typedef struct qegpio83xx {
+	gpio_n_t ioport[0x7];
+	u8 res0[0x358];
+} qepio83xx_t;
+
+/*
+ * QE Secondary Bus Access Windows
+ */
+typedef struct qesba83xx {
+	u32 lbmcsar;		/* Local bus memory controller start address */
+	u32 sdmcsar;		/* Secondary DDR memory controller start address */
+	u8 res0[0x38];
+	u32 lbmcear;		/* Local bus memory controller end address */
+	u32 sdmcear;		/* Secondary DDR memory controller end address */
+	u8 res1[0x38];
+	u32 lbmcar;		/* Local bus memory controller attributes */
+	u32 sdmcar;		/* Secondary DDR memory controller attributes */
+	u8 res2[0x378];
+} qesba83xx_t;
+
+/*
+ * DDR Memory Controller Memory Map for DDR1
+ * The structure of DDR2, or DDR3 is defined in fsl_immap.h
+ */
+#if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3)
+typedef struct ddr_cs_bnds {
+	u32 csbnds;
+	u8 res0[4];
+} ddr_cs_bnds_t;
+
+typedef struct ddr83xx {
+	ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
+	u8 res0[0x60];
+	u32 cs_config[4];	/* Chip Select x Configuration */
+	u8 res1[0x70];
+	u32 timing_cfg_3;	/* SDRAM Timing Configuration 3 */
+	u32 timing_cfg_0;	/* SDRAM Timing Configuration 0 */
+	u32 timing_cfg_1;	/* SDRAM Timing Configuration 1 */
+	u32 timing_cfg_2;	/* SDRAM Timing Configuration 2 */
+	u32 sdram_cfg;		/* SDRAM Control Configuration */
+	u32 sdram_cfg2;		/* SDRAM Control Configuration 2 */
+	u32 sdram_mode;		/* SDRAM Mode Configuration */
+	u32 sdram_mode2;	/* SDRAM Mode Configuration 2 */
+	u32 sdram_md_cntl;	/* SDRAM Mode Control */
+	u32 sdram_interval;	/* SDRAM Interval Configuration */
+	u32 ddr_data_init;	/* SDRAM Data Initialization */
+	u8 res2[4];
+	u32 sdram_clk_cntl;	/* SDRAM Clock Control */
+	u8 res3[0x14];
+	u32 ddr_init_addr;	/* DDR training initialization address */
+	u32 ddr_init_ext_addr;	/* DDR training initialization extended address */
+	u8 res4[0xAA8];
+	u32 ddr_ip_rev1;	/* DDR IP block revision 1 */
+	u32 ddr_ip_rev2;	/* DDR IP block revision 2 */
+	u8 res5[0x200];
+	u32 data_err_inject_hi;	/* Memory Data Path Error Injection Mask High */
+	u32 data_err_inject_lo;	/* Memory Data Path Error Injection Mask Low */
+	u32 ecc_err_inject;	/* Memory Data Path Error Injection Mask ECC */
+	u8 res6[0x14];
+	u32 capture_data_hi;	/* Memory Data Path Read Capture High */
+	u32 capture_data_lo;	/* Memory Data Path Read Capture Low */
+	u32 capture_ecc;	/* Memory Data Path Read Capture ECC */
+	u8 res7[0x14];
+	u32 err_detect;		/* Memory Error Detect */
+	u32 err_disable;	/* Memory Error Disable */
+	u32 err_int_en;		/* Memory Error Interrupt Enable */
+	u32 capture_attributes;	/* Memory Error Attributes Capture */
+	u32 capture_address;	/* Memory Error Address Capture */
+	u32 capture_ext_address;/* Memory Error Extended Address Capture */
+	u32 err_sbe;		/* Memory Single-Bit ECC Error Management */
+	u8 res8[0xA4];
+	u32 debug_reg;
+	u8 res9[0xFC];
+} ddr83xx_t;
+#endif
+
+/*
+ * DUART
+ */
+typedef struct duart83xx {
+	u8 urbr_ulcr_udlb;	/* combined register for URBR, UTHR and UDLB */
+	u8 uier_udmb;		/* combined register for UIER and UDMB */
+	u8 uiir_ufcr_uafr;	/* combined register for UIIR, UFCR and UAFR */
+	u8 ulcr;		/* line control register */
+	u8 umcr;		/* MODEM control register */
+	u8 ulsr;		/* line status register */
+	u8 umsr;		/* MODEM status register */
+	u8 uscr;		/* scratch register */
+	u8 res0[8];
+	u8 udsr;		/* DMA status register */
+	u8 res1[3];
+	u8 res2[0xEC];
+} duart83xx_t;
+
+/*
+ * DMA/Messaging Unit
+ */
+typedef struct dma83xx {
+	u32 res0[0xC];		/* 0x0-0x29 reseverd */
+	u32 omisr;		/* 0x30 Outbound message interrupt status register */
+	u32 omimr;		/* 0x34 Outbound message interrupt mask register */
+	u32 res1[0x6];		/* 0x38-0x49 reserved */
+	u32 imr0;		/* 0x50 Inbound message register 0 */
+	u32 imr1;		/* 0x54 Inbound message register 1 */
+	u32 omr0;		/* 0x58 Outbound message register 0 */
+	u32 omr1;		/* 0x5C Outbound message register 1 */
+	u32 odr;		/* 0x60 Outbound doorbell register */
+	u32 res2;		/* 0x64-0x67 reserved */
+	u32 idr;		/* 0x68 Inbound doorbell register */
+	u32 res3[0x5];		/* 0x6C-0x79 reserved */
+	u32 imisr;		/* 0x80 Inbound message interrupt status register */
+	u32 imimr;		/* 0x84 Inbound message interrupt mask register */
+	u32 res4[0x1E];		/* 0x88-0x99 reserved */
+	struct fsl_dma dma[4];
+} dma83xx_t;
+
+/*
+ * PCI Software Configuration Registers
+ */
+typedef struct pciconf83xx {
+	u32 config_address;
+	u32 config_data;
+	u32 int_ack;
+	u8 res[116];
+} pciconf83xx_t;
+
+/*
+ * PCI Outbound Translation Register
+ */
+typedef struct pci_outbound_window {
+	u32 potar;
+	u8 res0[4];
+	u32 pobar;
+	u8 res1[4];
+	u32 pocmr;
+	u8 res2[4];
+} pot83xx_t;
+
+/*
+ * Sequencer
+ */
+typedef struct ios83xx {
+	pot83xx_t pot[6];
+	u8 res0[0x60];
+	u32 pmcr;
+	u8 res1[4];
+	u32 dtcr;
+	u8 res2[4];
+} ios83xx_t;
+
+/*
+ * PCI Controller Control and Status Registers
+ */
+typedef struct pcictrl83xx {
+	u32 esr;
+	u32 ecdr;
+	u32 eer;
+	u32 eatcr;
+	u32 eacr;
+	u32 eeacr;
+	u32 edlcr;
+	u32 edhcr;
+	u32 gcr;
+	u32 ecr;
+	u32 gsr;
+	u8 res0[12];
+	u32 pitar2;
+	u8 res1[4];
+	u32 pibar2;
+	u32 piebar2;
+	u32 piwar2;
+	u8 res2[4];
+	u32 pitar1;
+	u8 res3[4];
+	u32 pibar1;
+	u32 piebar1;
+	u32 piwar1;
+	u8 res4[4];
+	u32 pitar0;
+	u8 res5[4];
+	u32 pibar0;
+	u8 res6[4];
+	u32 piwar0;
+	u8 res7[132];
+} pcictrl83xx_t;
+
+/*
+ * USB
+ */
+typedef struct usb83xx {
+	u8 fixme[0x1000];
+} usb83xx_t;
+
+/*
+ * TSEC
+ */
+typedef struct tsec83xx {
+	u8 fixme[0x1000];
+} tsec83xx_t;
+
+/*
+ * Security
+ */
+typedef struct security83xx {
+	u8 fixme[0x10000];
+} security83xx_t;
+
+/*
+ *  PCI Express
+ */
+struct pex_inbound_window {
+	u32 ar;
+	u32 tar;
+	u32 barl;
+	u32 barh;
+};
+
+struct pex_outbound_window {
+	u32 ar;
+	u32 bar;
+	u32 tarl;
+	u32 tarh;
+};
+
+struct pex_csb_bridge {
+	u32 pex_csb_ver;
+	u32 pex_csb_cab;
+	u32 pex_csb_ctrl;
+	u8 res0[8];
+	u32 pex_dms_dstmr;
+	u8 res1[4];
+	u32 pex_cbs_stat;
+	u8 res2[0x20];
+	u32 pex_csb_obctrl;
+	u32 pex_csb_obstat;
+	u8 res3[0x98];
+	u32 pex_csb_ibctrl;
+	u32 pex_csb_ibstat;
+	u8 res4[0xb8];
+	u32 pex_wdma_ctrl;
+	u32 pex_wdma_addr;
+	u32 pex_wdma_stat;
+	u8 res5[0x94];
+	u32 pex_rdma_ctrl;
+	u32 pex_rdma_addr;
+	u32 pex_rdma_stat;
+	u8 res6[0xd4];
+	u32 pex_ombcr;
+	u32 pex_ombdr;
+	u8 res7[0x38];
+	u32 pex_imbcr;
+	u32 pex_imbdr;
+	u8 res8[0x38];
+	u32 pex_int_enb;
+	u32 pex_int_stat;
+	u32 pex_int_apio_vec1;
+	u32 pex_int_apio_vec2;
+	u8 res9[0x10];
+	u32 pex_int_ppio_vec1;
+	u32 pex_int_ppio_vec2;
+	u32 pex_int_wdma_vec1;
+	u32 pex_int_wdma_vec2;
+	u32 pex_int_rdma_vec1;
+	u32 pex_int_rdma_vec2;
+	u32 pex_int_misc_vec;
+	u8 res10[4];
+	u32 pex_int_axi_pio_enb;
+	u32 pex_int_axi_wdma_enb;
+	u32 pex_int_axi_rdma_enb;
+	u32 pex_int_axi_misc_enb;
+	u32 pex_int_axi_pio_stat;
+	u32 pex_int_axi_wdma_stat;
+	u32 pex_int_axi_rdma_stat;
+	u32 pex_int_axi_misc_stat;
+	u8 res11[0xa0];
+	struct pex_outbound_window pex_outbound_win[4];
+	u8 res12[0x100];
+	u32 pex_epiwtar0;
+	u32 pex_epiwtar1;
+	u32 pex_epiwtar2;
+	u32 pex_epiwtar3;
+	u8 res13[0x70];
+	struct pex_inbound_window pex_inbound_win[4];
+};
+
+typedef struct pex83xx {
+	u8 pex_cfg_header[0x404];
+	u32 pex_ltssm_stat;
+	u8 res0[0x30];
+	u32 pex_ack_replay_timeout;
+	u8 res1[4];
+	u32 pex_gclk_ratio;
+	u8 res2[0xc];
+	u32 pex_pm_timer;
+	u32 pex_pme_timeout;
+	u8 res3[4];
+	u32 pex_aspm_req_timer;
+	u8 res4[0x18];
+	u32 pex_ssvid_update;
+	u8 res5[0x34];
+	u32 pex_cfg_ready;
+	u8 res6[0x24];
+	u32 pex_bar_sizel;
+	u8 res7[4];
+	u32 pex_bar_sel;
+	u8 res8[0x20];
+	u32 pex_bar_pf;
+	u8 res9[0x88];
+	u32 pex_pme_to_ack_tor;
+	u8 res10[0xc];
+	u32 pex_ss_intr_mask;
+	u8 res11[0x25c];
+	struct pex_csb_bridge bridge;
+	u8 res12[0x160];
+} pex83xx_t;
+
+/*
+ * SATA
+ */
+typedef struct sata83xx {
+	u8 fixme[0x1000];
+} sata83xx_t;
+
+/*
+ * eSDHC
+ */
+typedef struct sdhc83xx {
+	u8 fixme[0x1000];
+} sdhc83xx_t;
+
+/*
+ * SerDes
+ */
+typedef struct serdes83xx {
+	u32 srdscr0;
+	u32 srdscr1;
+	u32 srdscr2;
+	u32 srdscr3;
+	u32 srdscr4;
+	u8 res0[0xc];
+	u32 srdsrstctl;
+	u8 res1[0xdc];
+} serdes83xx_t;
+
+/*
+ * On Chip ROM
+ */
+typedef struct rom83xx {
+#if defined(CONFIG_ARCH_MPC8309)
+	u8 mem[0x8000];
+#else
+	u8 mem[0x10000];
+#endif
+} rom83xx_t;
+
+/*
+ * TDM
+ */
+typedef struct tdm83xx {
+	u8 fixme[0x200];
+} tdm83xx_t;
+
+/*
+ * TDM DMAC
+ */
+typedef struct tdmdmac83xx {
+	u8 fixme[0x2000];
+} tdmdmac83xx_t;
+
+#if defined(CONFIG_ARCH_MPC834X)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[2];	/* General purpose I/O module */
+	u8			res0[0x200];
+	u8			dll_ddr[0x100];
+	u8			dll_lbc[0x100];
+	u8			res1[0xE00];
+#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
+	struct ccsr_ddr		ddr;	/* DDR Memory Controller Memory */
+#else
+	ddr83xx_t		ddr;	/* DDR Memory Controller Memory */
+#endif
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res2[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res3[0x900];
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
+	u8			res4[0x1000];
+	spi8xxx_t		spi;		/* Serial Peripheral Interface */
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[2];	/* PCI Software Configuration Registers */
+	ios83xx_t		ios;		/* Sequencer */
+	pcictrl83xx_t		pci_ctrl[2];	/* PCI Controller Control and Status Registers */
+	u8			res5[0x19900];
+	usb83xx_t		usb[2];
+	tsec83xx_t		tsec[2];
+	u8			res6[0xA000];
+	security83xx_t		security;
+	u8			res7[0xC0000];
+} immap_t;
+
+#ifndef	CONFIG_ARCH_MPC834X
+#ifdef CONFIG_HAS_FSL_MPH_USB
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET  0x22000	/* use the MPH controller */
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET	0
+#else
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET	0
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET  0x23000	/* use the DR controller */
+#endif
+#else
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET	0x22000
+#define CONFIG_SYS_MPC83xx_USB2_OFFSET  0x23000
+#endif
+
+#elif defined(CONFIG_ARCH_MPC8313)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[1];	/* General purpose I/O module */
+	u8			res0[0x1300];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res1[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res2[0x900];
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
+	u8			res3[0x1000];
+	spi8xxx_t		spi;		/* Serial Peripheral Interface */
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res4[0x80];
+	ios83xx_t		ios;		/* Sequencer */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res5[0x1aa00];
+	usb83xx_t		usb[1];
+	tsec83xx_t		tsec[2];
+	u8			res6[0xA000];
+	security83xx_t		security;
+	u8			res7[0xC0000];
+} immap_t;
+
+#elif defined(CONFIG_ARCH_MPC8315)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[1];	/* General purpose I/O module */
+	u8			res0[0x1300];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[1];		/* I2C Controllers */
+	u8			res1[0x1400];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res2[0x900];
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
+	u8			res3[0x1000];
+	spi8xxx_t		spi;		/* Serial Peripheral Interface */
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res4[0x80];
+	ios83xx_t		ios;		/* Sequencer */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res5[0xa00];
+	pex83xx_t		pciexp[2];	/* PCI Express Controller */
+	u8			res6[0xb000];
+	tdm83xx_t		tdm;		/* TDM Controller */
+	u8			res7[0x1e00];
+	sata83xx_t		sata[2];	/* SATA Controller */
+	u8			res8[0x9000];
+	usb83xx_t		usb[1];		/* USB DR Controller */
+	tsec83xx_t		tsec[2];
+	u8			res9[0x6000];
+	tdmdmac83xx_t		tdmdmac;	/* TDM DMAC */
+	u8			res10[0x2000];
+	security83xx_t		security;
+	u8			res11[0xA3000];
+	serdes83xx_t		serdes[1];	/* SerDes Registers */
+	u8			res12[0x1CF00];
+} immap_t;
+
+#elif defined(CONFIG_ARCH_MPC8308)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[1];		/* Global Timers Module */
+	u8			res0[0x100];
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[1];	/* General purpose I/O module */
+	u8			res1[0x1300];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res2[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res3[0x900];
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
+	u8			res4[0x1000];
+	spi8xxx_t		spi;		/* Serial Peripheral Interface */
+	u8			res5[0x1000];
+	pex83xx_t		pciexp[1];	/* PCI Express Controller */
+	u8			res6[0x19000];
+	usb83xx_t		usb[1];		/* USB DR Controller */
+	tsec83xx_t		tsec[2];
+	u8			res7[0x6000];
+	tdmdmac83xx_t		tdmdmac;	/* TDM DMAC */
+	sdhc83xx_t		sdhc;		/* SDHC Controller */
+	u8			res8[0xb4000];
+	serdes83xx_t		serdes[1];	/* SerDes Registers */
+	u8			res9[0x1CF00];
+} immap_t;
+
+#elif defined(CONFIG_ARCH_MPC837X)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[2];	/* General purpose I/O module */
+	u8			res0[0x1200];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res1[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res2[0x900];
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
+	u8			res3[0x1000];
+	spi8xxx_t		spi;		/* Serial Peripheral Interface */
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res4[0x80];
+	ios83xx_t		ios;		/* Sequencer */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res5[0xa00];
+	pex83xx_t		pciexp[2];	/* PCI Express Controller */
+	u8			res6[0xd000];
+	sata83xx_t		sata[4];	/* SATA Controller */
+	u8			res7[0x7000];
+	usb83xx_t		usb[1];		/* USB DR Controller */
+	tsec83xx_t		tsec[2];
+	u8			res8[0x8000];
+	sdhc83xx_t		sdhc;		/* SDHC Controller */
+	u8			res9[0x1000];
+	security83xx_t		security;
+	u8			res10[0xA3000];
+	serdes83xx_t		serdes[2];	/* SerDes Registers */
+	u8			res11[0xCE00];
+	rom83xx_t		rom;		/* On Chip ROM */
+} immap_t;
+
+#elif defined(CONFIG_ARCH_MPC8360)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	u8			res0[0x200];
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
+	u8			res1[0x300];
+	u8			dll_ddr[0x100];
+	u8			dll_lbc[0x100];
+	u8			res2[0x200];
+	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
+	qesba83xx_t		qesba;		/* QE Secondary Bus Access Windows */
+	u8			res3[0x400];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res4[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res5[0x900];
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
+	u8			res6[0x2000];
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res7[128];
+	ios83xx_t		ios;		/* Sequencer (IOS) */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res8[0x4A00];
+	ddr83xx_t		ddr_secondary;	/* Secondary DDR Memory Controller Memory Map */
+	u8			res9[0x22000];
+	security83xx_t		security;
+	u8			res10[0xC0000];
+	u8			qe[0x100000];	/* QE block */
+} immap_t;
+
+#elif defined(CONFIG_ARCH_MPC832X)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
+	u8			res0[0x300];
+	u8			dll_ddr[0x100];
+	u8			dll_lbc[0x100];
+	u8			res1[0x200];
+	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
+	u8			res2[0x800];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res3[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res4[0x900];
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
+	u8			res5[0x2000];
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Software Configuration Registers */
+	u8			res6[128];
+	ios83xx_t		ios;		/* Sequencer (IOS) */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
+	u8			res7[0x27A00];
+	security83xx_t		security;
+	u8			res8[0xC0000];
+	u8			qe[0x100000];	/* QE block */
+} immap_t;
+#elif defined(CONFIG_ARCH_MPC8309)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[2];	/* General purpose I/O module */
+	u8			res0[0x500];	/* res0 1.25 KBytes added for 8309 */
+	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
+	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
+	u8			res1[0x800];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res2[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res3[0x200];
+	duart83xx_t		duart1[2];	/* DUART */
+	u8			res4[0x500];
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
+	u8			res5[0x1000];
+	u8			spi[0x100];
+	u8			res6[0xf00];
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Configuration Registers */
+	u8			res7[0x80];
+	ios83xx_t		ios;		/* Sequencer (IOS) */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Control & Status Registers */
+	u8			res8[0x13A00];
+	u8			can1[0x1000];	/* Flexcan 1 */
+	u8			can2[0x1000];	/* Flexcan 2 */
+	u8			res9[0x5000];
+	usb83xx_t		usb;
+	u8			res10[0x5000];
+	u8			can3[0x1000];	/* Flexcan 3 */
+	u8			can4[0x1000];	/* Flexcan 4 */
+	u8			res11[0x1000];
+	u8			dma1[0x2000];	/* DMA */
+	sdhc83xx_t		sdhc;		/* SDHC Controller */
+	u8			res12[0xC1000];
+	rom83xx_t		rom;		/* On Chip ROM */
+	u8			res13[0x8000];
+	u8			qe[0x100000];	/* QE block */
+	u8			res14[0xE00000];/* Added for 8309 */
+} immap_t;
+#endif
+
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET	(0x2000)
+#define CONFIG_SYS_FSL_DDR_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+#define CONFIG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
+#define CONFIG_SYS_MPC83xx_DMA_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
+#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
+
+#ifndef CONFIG_SYS_MPC83xx_USB1_OFFSET
+#define CONFIG_SYS_MPC83xx_USB1_OFFSET  0x23000
+#endif
+#define CONFIG_SYS_MPC83xx_USB1_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB1_OFFSET)
+#if defined(CONFIG_ARCH_MPC834X)
+#define CONFIG_SYS_MPC83xx_USB2_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB2_OFFSET)
+#endif
+#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
+
+#define CONFIG_SYS_TSEC1_OFFSET		0x24000
+#define CONFIG_SYS_MDIO1_OFFSET		0x24000
+
+#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#endif				/* __IMMAP_83xx__ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
new file mode 100644
index 0000000..bfa601e
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -0,0 +1,3141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MPC85xx Internal Memory Map
+ *
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
+ *
+ * Copyright(c) 2002,2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ */
+
+#ifndef __IMMAP_85xx__
+#define __IMMAP_85xx__
+
+#include <asm/types.h>
+#include <asm/fsl_dma.h>
+#include <asm/fsl_i2c.h>
+#include <fsl_ifc.h>
+#include <fsl_sec.h>
+#include <fsl_sfp.h>
+#include <asm/fsl_lbc.h>
+#include <fsl_fman.h>
+#include <fsl_immap.h>
+
+typedef struct ccsr_local {
+	u32	ccsrbarh;	/* CCSR Base Addr High */
+	u32	ccsrbarl;	/* CCSR Base Addr Low */
+	u32	ccsrar;		/* CCSR Attr */
+#define CCSRAR_C	0x80000000	/* Commit */
+	u8	res1[4];
+	u32	altcbarh;	/* Alternate Configuration Base Addr High */
+	u32	altcbarl;	/* Alternate Configuration Base Addr Low */
+	u32	altcar;		/* Alternate Configuration Attr */
+	u8	res2[4];
+	u32	bstrh;		/* Boot space translation high */
+	u32	bstrl;		/* Boot space translation Low */
+	u32	bstrar;		/* Boot space translation attributes */
+	u8	res3[0xbd4];
+	struct {
+		u32	lawbarh;	/* LAWn base addr high */
+		u32	lawbarl;	/* LAWn base addr low */
+		u32	lawar;		/* LAWn attributes */
+		u8	res4[4];
+	} law[32];
+	u8	res35[0x204];
+} ccsr_local_t;
+
+/* Local-Access Registers & ECM Registers */
+typedef struct ccsr_local_ecm {
+	u32	ccsrbar;	/* CCSR Base Addr */
+	u8	res1[4];
+	u32	altcbar;	/* Alternate Configuration Base Addr */
+	u8	res2[4];
+	u32	altcar;		/* Alternate Configuration Attr */
+	u8	res3[12];
+	u32	bptr;		/* Boot Page Translation */
+	u8	res4[3044];
+	u32	lawbar0;	/* Local Access Window 0 Base Addr */
+	u8	res5[4];
+	u32	lawar0;		/* Local Access Window 0 Attrs */
+	u8	res6[20];
+	u32	lawbar1;	/* Local Access Window 1 Base Addr */
+	u8	res7[4];
+	u32	lawar1;		/* Local Access Window 1 Attrs */
+	u8	res8[20];
+	u32	lawbar2;	/* Local Access Window 2 Base Addr */
+	u8	res9[4];
+	u32	lawar2;		/* Local Access Window 2 Attrs */
+	u8	res10[20];
+	u32	lawbar3;	/* Local Access Window 3 Base Addr */
+	u8	res11[4];
+	u32	lawar3;		/* Local Access Window 3 Attrs */
+	u8	res12[20];
+	u32	lawbar4;	/* Local Access Window 4 Base Addr */
+	u8	res13[4];
+	u32	lawar4;		/* Local Access Window 4 Attrs */
+	u8	res14[20];
+	u32	lawbar5;	/* Local Access Window 5 Base Addr */
+	u8	res15[4];
+	u32	lawar5;		/* Local Access Window 5 Attrs */
+	u8	res16[20];
+	u32	lawbar6;	/* Local Access Window 6 Base Addr */
+	u8	res17[4];
+	u32	lawar6;		/* Local Access Window 6 Attrs */
+	u8	res18[20];
+	u32	lawbar7;	/* Local Access Window 7 Base Addr */
+	u8	res19[4];
+	u32	lawar7;		/* Local Access Window 7 Attrs */
+	u8	res19_8a[20];
+	u32	lawbar8;	/* Local Access Window 8 Base Addr */
+	u8	res19_8b[4];
+	u32	lawar8;		/* Local Access Window 8 Attrs */
+	u8	res19_9a[20];
+	u32	lawbar9;	/* Local Access Window 9 Base Addr */
+	u8	res19_9b[4];
+	u32	lawar9;		/* Local Access Window 9 Attrs */
+	u8	res19_10a[20];
+	u32	lawbar10;	/* Local Access Window 10 Base Addr */
+	u8	res19_10b[4];
+	u32	lawar10;	/* Local Access Window 10 Attrs */
+	u8	res19_11a[20];
+	u32	lawbar11;	/* Local Access Window 11 Base Addr */
+	u8	res19_11b[4];
+	u32	lawar11;	/* Local Access Window 11 Attrs */
+	u8	res20[652];
+	u32	eebacr;		/* ECM CCB Addr Configuration */
+	u8	res21[12];
+	u32	eebpcr;		/* ECM CCB Port Configuration */
+	u8	res22[3564];
+	u32	eedr;		/* ECM Error Detect */
+	u8	res23[4];
+	u32	eeer;		/* ECM Error Enable */
+	u32	eeatr;		/* ECM Error Attrs Capture */
+	u32	eeadr;		/* ECM Error Addr Capture */
+	u8	res24[492];
+} ccsr_local_ecm_t;
+
+#define DDR_EOR_RD_BDW_OPT_DIS	0x80000000 /* Read BDW Opt. disable */
+#define DDR_EOR_ADDR_HASH_EN	0x40000000 /* Address hash enabled */
+
+/* I2C Registers */
+typedef struct ccsr_i2c {
+	struct fsl_i2c_base	i2c[1];
+	u8	res[4096 - 1 * sizeof(struct fsl_i2c_base)];
+} ccsr_i2c_t;
+
+#if defined(CONFIG_ARCH_MPC8540) || \
+	defined(CONFIG_ARCH_MPC8541) || \
+	defined(CONFIG_ARCH_MPC8548) || \
+	defined(CONFIG_ARCH_MPC8555)
+/* DUART Registers */
+typedef struct ccsr_duart {
+	u8	res1[1280];
+/* URBR1, UTHR1, UDLB1 with the same addr */
+	u8	urbr1_uthr1_udlb1;
+/* UIER1, UDMB1 with the same addr01 */
+	u8	uier1_udmb1;
+/* UIIR1, UFCR1, UAFR1 with the same addr */
+	u8	uiir1_ufcr1_uafr1;
+	u8	ulcr1;		/* UART1 Line Control */
+	u8	umcr1;		/* UART1 Modem Control */
+	u8	ulsr1;		/* UART1 Line Status */
+	u8	umsr1;		/* UART1 Modem Status */
+	u8	uscr1;		/* UART1 Scratch */
+	u8	res2[8];
+	u8	udsr1;		/* UART1 DMA Status */
+	u8	res3[239];
+/* URBR2, UTHR2, UDLB2 with the same addr */
+	u8	urbr2_uthr2_udlb2;
+/* UIER2, UDMB2 with the same addr */
+	u8	uier2_udmb2;
+/* UIIR2, UFCR2, UAFR2 with the same addr */
+	u8	uiir2_ufcr2_uafr2;
+	u8	ulcr2;		/* UART2 Line Control */
+	u8	umcr2;		/* UART2 Modem Control */
+	u8	ulsr2;		/* UART2 Line Status */
+	u8	umsr2;		/* UART2 Modem Status */
+	u8	uscr2;		/* UART2 Scratch */
+	u8	res4[8];
+	u8	udsr2;		/* UART2 DMA Status */
+	u8	res5[2543];
+} ccsr_duart_t;
+#else /* MPC8560 uses UART on its CPM */
+typedef struct ccsr_duart {
+	u8 res[4096];
+} ccsr_duart_t;
+#endif
+
+/* eSPI Registers */
+typedef struct ccsr_espi {
+	u32	mode;		/* eSPI mode */
+	u32	event;		/* eSPI event */
+	u32	mask;		/* eSPI mask */
+	u32	com;		/* eSPI command */
+	u32	tx;		/* eSPI transmit FIFO access */
+	u32	rx;		/* eSPI receive FIFO access */
+	u8	res1[8];	/* reserved */
+	u32	csmode[4];	/* 0x2c: sSPI CS0/1/2/3 mode */
+	u8	res2[4048];	/* fill up to 0x1000 */
+} ccsr_espi_t;
+
+/* PCI Registers */
+typedef struct ccsr_pcix {
+	u32	cfg_addr;	/* PCIX Configuration Addr */
+	u32	cfg_data;	/* PCIX Configuration Data */
+	u32	int_ack;	/* PCIX IRQ Acknowledge */
+	u8	res000c[52];
+	u32	liodn_base;	/* PCIX LIODN base register */
+	u8	res0044[2996];
+	u32	ipver1;		/* PCIX IP block revision register 1 */
+	u32	ipver2;		/* PCIX IP block revision register 2 */
+	u32	potar0;		/* PCIX Outbound Transaction Addr 0 */
+	u32	potear0;	/* PCIX Outbound Translation Extended Addr 0 */
+	u32	powbar0;	/* PCIX Outbound Window Base Addr 0 */
+	u32	powbear0;	/* PCIX Outbound Window Base Extended Addr 0 */
+	u32	powar0;		/* PCIX Outbound Window Attrs 0 */
+	u8	res2[12];
+	u32	potar1;		/* PCIX Outbound Transaction Addr 1 */
+	u32	potear1;	/* PCIX Outbound Translation Extended Addr 1 */
+	u32	powbar1;	/* PCIX Outbound Window Base Addr 1 */
+	u32	powbear1;	/* PCIX Outbound Window Base Extended Addr 1 */
+	u32	powar1;		/* PCIX Outbound Window Attrs 1 */
+	u8	res3[12];
+	u32	potar2;		/* PCIX Outbound Transaction Addr 2 */
+	u32	potear2;	/* PCIX Outbound Translation Extended Addr 2 */
+	u32	powbar2;	/* PCIX Outbound Window Base Addr 2 */
+	u32	powbear2;	/* PCIX Outbound Window Base Extended Addr 2 */
+	u32	powar2;		/* PCIX Outbound Window Attrs 2 */
+	u8	res4[12];
+	u32	potar3;		/* PCIX Outbound Transaction Addr 3 */
+	u32	potear3;	/* PCIX Outbound Translation Extended Addr 3 */
+	u32	powbar3;	/* PCIX Outbound Window Base Addr 3 */
+	u32	powbear3;	/* PCIX Outbound Window Base Extended Addr 3 */
+	u32	powar3;		/* PCIX Outbound Window Attrs 3 */
+	u8	res5[12];
+	u32	potar4;		/* PCIX Outbound Transaction Addr 4 */
+	u32	potear4;	/* PCIX Outbound Translation Extended Addr 4 */
+	u32	powbar4;	/* PCIX Outbound Window Base Addr 4 */
+	u32	powbear4;	/* PCIX Outbound Window Base Extended Addr 4 */
+	u32	powar4;		/* PCIX Outbound Window Attrs 4 */
+	u8	res6[268];
+	u32	pitar3;		/* PCIX Inbound Translation Addr 3 */
+	u32	pitear3;	/* PCIX Inbound Translation Extended Addr 3 */
+	u32	piwbar3;	/* PCIX Inbound Window Base Addr 3 */
+	u32	piwbear3;	/* PCIX Inbound Window Base Extended Addr 3 */
+	u32	piwar3;		/* PCIX Inbound Window Attrs 3 */
+	u8	res7[12];
+	u32	pitar2;		/* PCIX Inbound Translation Addr 2 */
+	u32	pitear2;	/* PCIX Inbound Translation Extended Addr 2 */
+	u32	piwbar2;	/* PCIX Inbound Window Base Addr 2 */
+	u32	piwbear2;	/* PCIX Inbound Window Base Extended Addr 2 */
+	u32	piwar2;		/* PCIX Inbound Window Attrs 2 */
+	u8	res8[12];
+	u32	pitar1;		/* PCIX Inbound Translation Addr 1 */
+	u32	pitear1;	/* PCIX Inbound Translation Extended Addr 1 */
+	u32	piwbar1;	/* PCIX Inbound Window Base Addr 1 */
+	u8	res9[4];
+	u32	piwar1;		/* PCIX Inbound Window Attrs 1 */
+	u8	res10[12];
+	u32	pedr;		/* PCIX Error Detect */
+	u32	pecdr;		/* PCIX Error Capture Disable */
+	u32	peer;		/* PCIX Error Enable */
+	u32	peattrcr;	/* PCIX Error Attrs Capture */
+	u32	peaddrcr;	/* PCIX Error Addr Capture */
+	u32	peextaddrcr;	/* PCIX Error Extended Addr Capture */
+	u32	pedlcr;		/* PCIX Error Data Low Capture */
+	u32	pedhcr;		/* PCIX Error Error Data High Capture */
+	u32	gas_timr;	/* PCIX Gasket Timer */
+	u8	res11[476];
+} ccsr_pcix_t;
+
+#define PCIX_COMMAND	0x62
+#define POWAR_EN	0x80000000
+#define POWAR_IO_READ	0x00080000
+#define POWAR_MEM_READ	0x00040000
+#define POWAR_IO_WRITE	0x00008000
+#define POWAR_MEM_WRITE	0x00004000
+#define POWAR_MEM_512M	0x0000001c
+#define POWAR_IO_1M	0x00000013
+
+#define PIWAR_EN	0x80000000
+#define PIWAR_PF	0x20000000
+#define PIWAR_LOCAL	0x00f00000
+#define PIWAR_READ_SNOOP	0x00050000
+#define PIWAR_WRITE_SNOOP	0x00005000
+#define PIWAR_MEM_2G		0x0000001e
+
+#ifndef CONFIG_MPC85XX_GPIO
+typedef struct ccsr_gpio {
+	u32	gpdir;
+	u32	gpodr;
+	u32	gpdat;
+	u32	gpier;
+	u32	gpimr;
+	u32	gpicr;
+} ccsr_gpio_t;
+#endif
+
+/* L2 Cache Registers */
+typedef struct ccsr_l2cache {
+	u32	l2ctl;		/* L2 configuration 0 */
+	u8	res1[12];
+	u32	l2cewar0;	/* L2 cache external write addr 0 */
+	u8	res2[4];
+	u32	l2cewcr0;	/* L2 cache external write control 0 */
+	u8	res3[4];
+	u32	l2cewar1;	/* L2 cache external write addr 1 */
+	u8	res4[4];
+	u32	l2cewcr1;	/* L2 cache external write control 1 */
+	u8	res5[4];
+	u32	l2cewar2;	/* L2 cache external write addr 2 */
+	u8	res6[4];
+	u32	l2cewcr2;	/* L2 cache external write control 2 */
+	u8	res7[4];
+	u32	l2cewar3;	/* L2 cache external write addr 3 */
+	u8	res8[4];
+	u32	l2cewcr3;	/* L2 cache external write control 3 */
+	u8	res9[180];
+	u32	l2srbar0;	/* L2 memory-mapped SRAM base addr 0 */
+	u8	res10[4];
+	u32	l2srbar1;	/* L2 memory-mapped SRAM base addr 1 */
+	u8	res11[3316];
+	u32	l2errinjhi;	/* L2 error injection mask high */
+	u32	l2errinjlo;	/* L2 error injection mask low */
+	u32	l2errinjctl;	/* L2 error injection tag/ECC control */
+	u8	res12[20];
+	u32	l2captdatahi;	/* L2 error data high capture */
+	u32	l2captdatalo;	/* L2 error data low capture */
+	u32	l2captecc;	/* L2 error ECC capture */
+	u8	res13[20];
+	u32	l2errdet;	/* L2 error detect */
+	u32	l2errdis;	/* L2 error disable */
+	u32	l2errinten;	/* L2 error interrupt enable */
+	u32	l2errattr;	/* L2 error attributes capture */
+	u32	l2erraddr;	/* L2 error addr capture */
+	u8	res14[4];
+	u32	l2errctl;	/* L2 error control */
+	u8	res15[420];
+} ccsr_l2cache_t;
+
+#define MPC85xx_L2CTL_L2E			0x80000000
+#define MPC85xx_L2CTL_L2SRAM_ENTIRE		0x00010000
+#define MPC85xx_L2ERRDIS_MBECC			0x00000008
+#define MPC85xx_L2ERRDIS_SBECC			0x00000004
+
+/* DMA Registers */
+typedef struct ccsr_dma {
+	u8	res1[256];
+	struct fsl_dma dma[4];
+	u32	dgsr;		/* DMA General Status */
+	u8	res2[11516];
+} ccsr_dma_t;
+
+/* tsec */
+typedef struct ccsr_tsec {
+	u8	res1[16];
+	u32	ievent;		/* IRQ Event */
+	u32	imask;		/* IRQ Mask */
+	u32	edis;		/* Error Disabled */
+	u8	res2[4];
+	u32	ecntrl;		/* Ethernet Control */
+	u32	minflr;		/* Minimum Frame Len */
+	u32	ptv;		/* Pause Time Value */
+	u32	dmactrl;	/* DMA Control */
+	u32	tbipa;		/* TBI PHY Addr */
+	u8	res3[88];
+	u32	fifo_tx_thr;		/* FIFO transmit threshold */
+	u8	res4[8];
+	u32	fifo_tx_starve;		/* FIFO transmit starve */
+	u32	fifo_tx_starve_shutoff;	/* FIFO transmit starve shutoff */
+	u8	res5[96];
+	u32	tctrl;		/* TX Control */
+	u32	tstat;		/* TX Status */
+	u8	res6[4];
+	u32	tbdlen;		/* TX Buffer Desc Data Len */
+	u8	res7[16];
+	u32	ctbptrh;	/* Current TX Buffer Desc Ptr High */
+	u32	ctbptr;		/* Current TX Buffer Desc Ptr */
+	u8	res8[88];
+	u32	tbptrh;		/* TX Buffer Desc Ptr High */
+	u32	tbptr;		/* TX Buffer Desc Ptr Low */
+	u8	res9[120];
+	u32	tbaseh;		/* TX Desc Base Addr High */
+	u32	tbase;		/* TX Desc Base Addr */
+	u8	res10[168];
+	u32	ostbd;		/* Out-of-Sequence(OOS) TX Buffer Desc */
+	u32	ostbdp;		/* OOS TX Data Buffer Ptr */
+	u32	os32tbdp;	/* OOS 32 Bytes TX Data Buffer Ptr Low */
+	u32	os32iptrh;	/* OOS 32 Bytes TX Insert Ptr High */
+	u32	os32iptrl;	/* OOS 32 Bytes TX Insert Ptr Low */
+	u32	os32tbdr;	/* OOS 32 Bytes TX Reserved */
+	u32	os32iil;	/* OOS 32 Bytes TX Insert Idx/Len */
+	u8	res11[52];
+	u32	rctrl;		/* RX Control */
+	u32	rstat;		/* RX Status */
+	u8	res12[4];
+	u32	rbdlen;		/* RxBD Data Len */
+	u8	res13[16];
+	u32	crbptrh;	/* Current RX Buffer Desc Ptr High */
+	u32	crbptr;		/* Current RX Buffer Desc Ptr */
+	u8	res14[24];
+	u32	mrblr;		/* Maximum RX Buffer Len */
+	u32	mrblr2r3;	/* Maximum RX Buffer Len R2R3 */
+	u8	res15[56];
+	u32	rbptrh;		/* RX Buffer Desc Ptr High 0 */
+	u32	rbptr;		/* RX Buffer Desc Ptr */
+	u32	rbptrh1;	/* RX Buffer Desc Ptr High 1 */
+	u32	rbptrl1;	/* RX Buffer Desc Ptr Low 1 */
+	u32	rbptrh2;	/* RX Buffer Desc Ptr High 2 */
+	u32	rbptrl2;	/* RX Buffer Desc Ptr Low 2 */
+	u32	rbptrh3;	/* RX Buffer Desc Ptr High 3 */
+	u32	rbptrl3;	/* RX Buffer Desc Ptr Low 3 */
+	u8	res16[96];
+	u32	rbaseh;		/* RX Desc Base Addr High 0 */
+	u32	rbase;		/* RX Desc Base Addr */
+	u32	rbaseh1;	/* RX Desc Base Addr High 1 */
+	u32	rbasel1;	/* RX Desc Base Addr Low 1 */
+	u32	rbaseh2;	/* RX Desc Base Addr High 2 */
+	u32	rbasel2;	/* RX Desc Base Addr Low 2 */
+	u32	rbaseh3;	/* RX Desc Base Addr High 3 */
+	u32	rbasel3;	/* RX Desc Base Addr Low 3 */
+	u8	res17[224];
+	u32	maccfg1;	/* MAC Configuration 1 */
+	u32	maccfg2;	/* MAC Configuration 2 */
+	u32	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
+	u32	hafdup;		/* Half Duplex */
+	u32	maxfrm;		/* Maximum Frame Len */
+	u8	res18[12];
+	u32	miimcfg;	/* MII Management Configuration */
+	u32	miimcom;	/* MII Management Cmd */
+	u32	miimadd;	/* MII Management Addr */
+	u32	miimcon;	/* MII Management Control */
+	u32	miimstat;	/* MII Management Status */
+	u32	miimind;	/* MII Management Indicator */
+	u8	res19[4];
+	u32	ifstat;		/* Interface Status */
+	u32	macstnaddr1;	/* Station Addr Part 1 */
+	u32	macstnaddr2;	/* Station Addr Part 2 */
+	u8	res20[312];
+	u32	tr64;		/* TX & RX 64-byte Frame Counter */
+	u32	tr127;		/* TX & RX 65-127 byte Frame Counter */
+	u32	tr255;		/* TX & RX 128-255 byte Frame Counter */
+	u32	tr511;		/* TX & RX 256-511 byte Frame Counter */
+	u32	tr1k;		/* TX & RX 512-1023 byte Frame Counter */
+	u32	trmax;		/* TX & RX 1024-1518 byte Frame Counter */
+	u32	trmgv;		/* TX & RX 1519-1522 byte Good VLAN Frame */
+	u32	rbyt;		/* RX Byte Counter */
+	u32	rpkt;		/* RX Packet Counter */
+	u32	rfcs;		/* RX FCS Error Counter */
+	u32	rmca;		/* RX Multicast Packet Counter */
+	u32	rbca;		/* RX Broadcast Packet Counter */
+	u32	rxcf;		/* RX Control Frame Packet Counter */
+	u32	rxpf;		/* RX Pause Frame Packet Counter */
+	u32	rxuo;		/* RX Unknown OP Code Counter */
+	u32	raln;		/* RX Alignment Error Counter */
+	u32	rflr;		/* RX Frame Len Error Counter */
+	u32	rcde;		/* RX Code Error Counter */
+	u32	rcse;		/* RX Carrier Sense Error Counter */
+	u32	rund;		/* RX Undersize Packet Counter */
+	u32	rovr;		/* RX Oversize Packet Counter */
+	u32	rfrg;		/* RX Fragments Counter */
+	u32	rjbr;		/* RX Jabber Counter */
+	u32	rdrp;		/* RX Drop Counter */
+	u32	tbyt;		/* TX Byte Counter Counter */
+	u32	tpkt;		/* TX Packet Counter */
+	u32	tmca;		/* TX Multicast Packet Counter */
+	u32	tbca;		/* TX Broadcast Packet Counter */
+	u32	txpf;		/* TX Pause Control Frame Counter */
+	u32	tdfr;		/* TX Deferral Packet Counter */
+	u32	tedf;		/* TX Excessive Deferral Packet Counter */
+	u32	tscl;		/* TX Single Collision Packet Counter */
+	u32	tmcl;		/* TX Multiple Collision Packet Counter */
+	u32	tlcl;		/* TX Late Collision Packet Counter */
+	u32	txcl;		/* TX Excessive Collision Packet Counter */
+	u32	tncl;		/* TX Total Collision Counter */
+	u8	res21[4];
+	u32	tdrp;		/* TX Drop Frame Counter */
+	u32	tjbr;		/* TX Jabber Frame Counter */
+	u32	tfcs;		/* TX FCS Error Counter */
+	u32	txcf;		/* TX Control Frame Counter */
+	u32	tovr;		/* TX Oversize Frame Counter */
+	u32	tund;		/* TX Undersize Frame Counter */
+	u32	tfrg;		/* TX Fragments Frame Counter */
+	u32	car1;		/* Carry One */
+	u32	car2;		/* Carry Two */
+	u32	cam1;		/* Carry Mask One */
+	u32	cam2;		/* Carry Mask Two */
+	u8	res22[192];
+	u32	iaddr0;		/* Indivdual addr 0 */
+	u32	iaddr1;		/* Indivdual addr 1 */
+	u32	iaddr2;		/* Indivdual addr 2 */
+	u32	iaddr3;		/* Indivdual addr 3 */
+	u32	iaddr4;		/* Indivdual addr 4 */
+	u32	iaddr5;		/* Indivdual addr 5 */
+	u32	iaddr6;		/* Indivdual addr 6 */
+	u32	iaddr7;		/* Indivdual addr 7 */
+	u8	res23[96];
+	u32	gaddr0;		/* Global addr 0 */
+	u32	gaddr1;		/* Global addr 1 */
+	u32	gaddr2;		/* Global addr 2 */
+	u32	gaddr3;		/* Global addr 3 */
+	u32	gaddr4;		/* Global addr 4 */
+	u32	gaddr5;		/* Global addr 5 */
+	u32	gaddr6;		/* Global addr 6 */
+	u32	gaddr7;		/* Global addr 7 */
+	u8	res24[96];
+	u32	pmd0;		/* Pattern Match Data */
+	u8	res25[4];
+	u32	pmask0;		/* Pattern Mask */
+	u8	res26[4];
+	u32	pcntrl0;	/* Pattern Match Control */
+	u8	res27[4];
+	u32	pattrb0;	/* Pattern Match Attrs */
+	u32	pattrbeli0;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd1;		/* Pattern Match Data */
+	u8	res28[4];
+	u32	pmask1;		/* Pattern Mask */
+	u8	res29[4];
+	u32	pcntrl1;	/* Pattern Match Control */
+	u8	res30[4];
+	u32	pattrb1;	/* Pattern Match Attrs */
+	u32	pattrbeli1;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd2;		/* Pattern Match Data */
+	u8	res31[4];
+	u32	pmask2;		/* Pattern Mask */
+	u8	res32[4];
+	u32	pcntrl2;	/* Pattern Match Control */
+	u8	res33[4];
+	u32	pattrb2;	/* Pattern Match Attrs */
+	u32	pattrbeli2;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd3;		/* Pattern Match Data */
+	u8	res34[4];
+	u32	pmask3;		/* Pattern Mask */
+	u8	res35[4];
+	u32	pcntrl3;	/* Pattern Match Control */
+	u8	res36[4];
+	u32	pattrb3;	/* Pattern Match Attrs */
+	u32	pattrbeli3;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd4;		/* Pattern Match Data */
+	u8	res37[4];
+	u32	pmask4;		/* Pattern Mask */
+	u8	res38[4];
+	u32	pcntrl4;	/* Pattern Match Control */
+	u8	res39[4];
+	u32	pattrb4;	/* Pattern Match Attrs */
+	u32	pattrbeli4;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd5;		/* Pattern Match Data */
+	u8	res40[4];
+	u32	pmask5;		/* Pattern Mask */
+	u8	res41[4];
+	u32	pcntrl5;	/* Pattern Match Control */
+	u8	res42[4];
+	u32	pattrb5;	/* Pattern Match Attrs */
+	u32	pattrbeli5;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd6;		/* Pattern Match Data */
+	u8	res43[4];
+	u32	pmask6;		/* Pattern Mask */
+	u8	res44[4];
+	u32	pcntrl6;	/* Pattern Match Control */
+	u8	res45[4];
+	u32	pattrb6;	/* Pattern Match Attrs */
+	u32	pattrbeli6;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd7;		/* Pattern Match Data */
+	u8	res46[4];
+	u32	pmask7;		/* Pattern Mask */
+	u8	res47[4];
+	u32	pcntrl7;	/* Pattern Match Control */
+	u8	res48[4];
+	u32	pattrb7;	/* Pattern Match Attrs */
+	u32	pattrbeli7;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd8;		/* Pattern Match Data */
+	u8	res49[4];
+	u32	pmask8;		/* Pattern Mask */
+	u8	res50[4];
+	u32	pcntrl8;	/* Pattern Match Control */
+	u8	res51[4];
+	u32	pattrb8;	/* Pattern Match Attrs */
+	u32	pattrbeli8;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd9;		/* Pattern Match Data */
+	u8	res52[4];
+	u32	pmask9;		/* Pattern Mask */
+	u8	res53[4];
+	u32	pcntrl9;	/* Pattern Match Control */
+	u8	res54[4];
+	u32	pattrb9;	/* Pattern Match Attrs */
+	u32	pattrbeli9;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd10;		/* Pattern Match Data */
+	u8	res55[4];
+	u32	pmask10;	/* Pattern Mask */
+	u8	res56[4];
+	u32	pcntrl10;	/* Pattern Match Control */
+	u8	res57[4];
+	u32	pattrb10;	/* Pattern Match Attrs */
+	u32	pattrbeli10;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd11;		/* Pattern Match Data */
+	u8	res58[4];
+	u32	pmask11;	/* Pattern Mask */
+	u8	res59[4];
+	u32	pcntrl11;	/* Pattern Match Control */
+	u8	res60[4];
+	u32	pattrb11;	/* Pattern Match Attrs */
+	u32	pattrbeli11;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd12;		/* Pattern Match Data */
+	u8	res61[4];
+	u32	pmask12;	/* Pattern Mask */
+	u8	res62[4];
+	u32	pcntrl12;	/* Pattern Match Control */
+	u8	res63[4];
+	u32	pattrb12;	/* Pattern Match Attrs */
+	u32	pattrbeli12;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd13;		/* Pattern Match Data */
+	u8	res64[4];
+	u32	pmask13;	/* Pattern Mask */
+	u8	res65[4];
+	u32	pcntrl13;	/* Pattern Match Control */
+	u8	res66[4];
+	u32	pattrb13;	/* Pattern Match Attrs */
+	u32	pattrbeli13;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd14;		/* Pattern Match Data */
+	u8	res67[4];
+	u32	pmask14;	/* Pattern Mask */
+	u8	res68[4];
+	u32	pcntrl14;	/* Pattern Match Control */
+	u8	res69[4];
+	u32	pattrb14;	/* Pattern Match Attrs */
+	u32	pattrbeli14;	/* Pattern Match Attrs Extract Len & Idx */
+	u32	pmd15;		/* Pattern Match Data */
+	u8	res70[4];
+	u32	pmask15;	/* Pattern Mask */
+	u8	res71[4];
+	u32	pcntrl15;	/* Pattern Match Control */
+	u8	res72[4];
+	u32	pattrb15;	/* Pattern Match Attrs */
+	u32	pattrbeli15;	/* Pattern Match Attrs Extract Len & Idx */
+	u8	res73[248];
+	u32	attr;		/* Attrs */
+	u32	attreli;	/* Attrs Extract Len & Idx */
+	u8	res74[1024];
+} ccsr_tsec_t;
+
+/* PIC Registers */
+typedef struct ccsr_pic {
+	u8	res1[64];
+	u32	ipidr0;		/* Interprocessor IRQ Dispatch 0 */
+	u8	res2[12];
+	u32	ipidr1;		/* Interprocessor IRQ Dispatch 1 */
+	u8	res3[12];
+	u32	ipidr2;		/* Interprocessor IRQ Dispatch 2 */
+	u8	res4[12];
+	u32	ipidr3;		/* Interprocessor IRQ Dispatch 3 */
+	u8	res5[12];
+	u32	ctpr;		/* Current Task Priority */
+	u8	res6[12];
+	u32	whoami;		/* Who Am I */
+	u8	res7[12];
+	u32	iack;		/* IRQ Acknowledge */
+	u8	res8[12];
+	u32	eoi;		/* End Of IRQ */
+	u8	res9[3916];
+	u32	frr;		/* Feature Reporting */
+	u8	res10[28];
+	u32	gcr;		/* Global Configuration */
+#define MPC85xx_PICGCR_RST	0x80000000
+#define MPC85xx_PICGCR_M	0x20000000
+	u8	res11[92];
+	u32	vir;		/* Vendor Identification */
+	u8	res12[12];
+	u32	pir;		/* Processor Initialization */
+	u8	res13[12];
+	u32	ipivpr0;	/* IPI Vector/Priority 0 */
+	u8	res14[12];
+	u32	ipivpr1;	/* IPI Vector/Priority 1 */
+	u8	res15[12];
+	u32	ipivpr2;	/* IPI Vector/Priority 2 */
+	u8	res16[12];
+	u32	ipivpr3;	/* IPI Vector/Priority 3 */
+	u8	res17[12];
+	u32	svr;		/* Spurious Vector */
+	u8	res18[12];
+	u32	tfrr;		/* Timer Frequency Reporting */
+	u8	res19[12];
+	u32	gtccr0;		/* Global Timer Current Count 0 */
+	u8	res20[12];
+	u32	gtbcr0;		/* Global Timer Base Count 0 */
+	u8	res21[12];
+	u32	gtvpr0;		/* Global Timer Vector/Priority 0 */
+	u8	res22[12];
+	u32	gtdr0;		/* Global Timer Destination 0 */
+	u8	res23[12];
+	u32	gtccr1;		/* Global Timer Current Count 1 */
+	u8	res24[12];
+	u32	gtbcr1;		/* Global Timer Base Count 1 */
+	u8	res25[12];
+	u32	gtvpr1;		/* Global Timer Vector/Priority 1 */
+	u8	res26[12];
+	u32	gtdr1;		/* Global Timer Destination 1 */
+	u8	res27[12];
+	u32	gtccr2;		/* Global Timer Current Count 2 */
+	u8	res28[12];
+	u32	gtbcr2;		/* Global Timer Base Count 2 */
+	u8	res29[12];
+	u32	gtvpr2;		/* Global Timer Vector/Priority 2 */
+	u8	res30[12];
+	u32	gtdr2;		/* Global Timer Destination 2 */
+	u8	res31[12];
+	u32	gtccr3;		/* Global Timer Current Count 3 */
+	u8	res32[12];
+	u32	gtbcr3;		/* Global Timer Base Count 3 */
+	u8	res33[12];
+	u32	gtvpr3;		/* Global Timer Vector/Priority 3 */
+	u8	res34[12];
+	u32	gtdr3;		/* Global Timer Destination 3 */
+	u8	res35[268];
+	u32	tcr;		/* Timer Control */
+	u8	res36[12];
+	u32	irqsr0;		/* IRQ_OUT Summary 0 */
+	u8	res37[12];
+	u32	irqsr1;		/* IRQ_OUT Summary 1 */
+	u8	res38[12];
+	u32	cisr0;		/* Critical IRQ Summary 0 */
+	u8	res39[12];
+	u32	cisr1;		/* Critical IRQ Summary 1 */
+	u8	res40[188];
+	u32	msgr0;		/* Message 0 */
+	u8	res41[12];
+	u32	msgr1;		/* Message 1 */
+	u8	res42[12];
+	u32	msgr2;		/* Message 2 */
+	u8	res43[12];
+	u32	msgr3;		/* Message 3 */
+	u8	res44[204];
+	u32	mer;		/* Message Enable */
+	u8	res45[12];
+	u32	msr;		/* Message Status */
+	u8	res46[60140];
+	u32	eivpr0;		/* External IRQ Vector/Priority 0 */
+	u8	res47[12];
+	u32	eidr0;		/* External IRQ Destination 0 */
+	u8	res48[12];
+	u32	eivpr1;		/* External IRQ Vector/Priority 1 */
+	u8	res49[12];
+	u32	eidr1;		/* External IRQ Destination 1 */
+	u8	res50[12];
+	u32	eivpr2;		/* External IRQ Vector/Priority 2 */
+	u8	res51[12];
+	u32	eidr2;		/* External IRQ Destination 2 */
+	u8	res52[12];
+	u32	eivpr3;		/* External IRQ Vector/Priority 3 */
+	u8	res53[12];
+	u32	eidr3;		/* External IRQ Destination 3 */
+	u8	res54[12];
+	u32	eivpr4;		/* External IRQ Vector/Priority 4 */
+	u8	res55[12];
+	u32	eidr4;		/* External IRQ Destination 4 */
+	u8	res56[12];
+	u32	eivpr5;		/* External IRQ Vector/Priority 5 */
+	u8	res57[12];
+	u32	eidr5;		/* External IRQ Destination 5 */
+	u8	res58[12];
+	u32	eivpr6;		/* External IRQ Vector/Priority 6 */
+	u8	res59[12];
+	u32	eidr6;		/* External IRQ Destination 6 */
+	u8	res60[12];
+	u32	eivpr7;		/* External IRQ Vector/Priority 7 */
+	u8	res61[12];
+	u32	eidr7;		/* External IRQ Destination 7 */
+	u8	res62[12];
+	u32	eivpr8;		/* External IRQ Vector/Priority 8 */
+	u8	res63[12];
+	u32	eidr8;		/* External IRQ Destination 8 */
+	u8	res64[12];
+	u32	eivpr9;		/* External IRQ Vector/Priority 9 */
+	u8	res65[12];
+	u32	eidr9;		/* External IRQ Destination 9 */
+	u8	res66[12];
+	u32	eivpr10;	/* External IRQ Vector/Priority 10 */
+	u8	res67[12];
+	u32	eidr10;		/* External IRQ Destination 10 */
+	u8	res68[12];
+	u32	eivpr11;	/* External IRQ Vector/Priority 11 */
+	u8	res69[12];
+	u32	eidr11;		/* External IRQ Destination 11 */
+	u8	res70[140];
+	u32	iivpr0;		/* Internal IRQ Vector/Priority 0 */
+	u8	res71[12];
+	u32	iidr0;		/* Internal IRQ Destination 0 */
+	u8	res72[12];
+	u32	iivpr1;		/* Internal IRQ Vector/Priority 1 */
+	u8	res73[12];
+	u32	iidr1;		/* Internal IRQ Destination 1 */
+	u8	res74[12];
+	u32	iivpr2;		/* Internal IRQ Vector/Priority 2 */
+	u8	res75[12];
+	u32	iidr2;		/* Internal IRQ Destination 2 */
+	u8	res76[12];
+	u32	iivpr3;		/* Internal IRQ Vector/Priority 3 */
+	u8	res77[12];
+	u32	iidr3;		/* Internal IRQ Destination 3 */
+	u8	res78[12];
+	u32	iivpr4;		/* Internal IRQ Vector/Priority 4 */
+	u8	res79[12];
+	u32	iidr4;		/* Internal IRQ Destination 4 */
+	u8	res80[12];
+	u32	iivpr5;		/* Internal IRQ Vector/Priority 5 */
+	u8	res81[12];
+	u32	iidr5;		/* Internal IRQ Destination 5 */
+	u8	res82[12];
+	u32	iivpr6;		/* Internal IRQ Vector/Priority 6 */
+	u8	res83[12];
+	u32	iidr6;		/* Internal IRQ Destination 6 */
+	u8	res84[12];
+	u32	iivpr7;		/* Internal IRQ Vector/Priority 7 */
+	u8	res85[12];
+	u32	iidr7;		/* Internal IRQ Destination 7 */
+	u8	res86[12];
+	u32	iivpr8;		/* Internal IRQ Vector/Priority 8 */
+	u8	res87[12];
+	u32	iidr8;		/* Internal IRQ Destination 8 */
+	u8	res88[12];
+	u32	iivpr9;		/* Internal IRQ Vector/Priority 9 */
+	u8	res89[12];
+	u32	iidr9;		/* Internal IRQ Destination 9 */
+	u8	res90[12];
+	u32	iivpr10;	/* Internal IRQ Vector/Priority 10 */
+	u8	res91[12];
+	u32	iidr10;		/* Internal IRQ Destination 10 */
+	u8	res92[12];
+	u32	iivpr11;	/* Internal IRQ Vector/Priority 11 */
+	u8	res93[12];
+	u32	iidr11;		/* Internal IRQ Destination 11 */
+	u8	res94[12];
+	u32	iivpr12;	/* Internal IRQ Vector/Priority 12 */
+	u8	res95[12];
+	u32	iidr12;		/* Internal IRQ Destination 12 */
+	u8	res96[12];
+	u32	iivpr13;	/* Internal IRQ Vector/Priority 13 */
+	u8	res97[12];
+	u32	iidr13;		/* Internal IRQ Destination 13 */
+	u8	res98[12];
+	u32	iivpr14;	/* Internal IRQ Vector/Priority 14 */
+	u8	res99[12];
+	u32	iidr14;		/* Internal IRQ Destination 14 */
+	u8	res100[12];
+	u32	iivpr15;	/* Internal IRQ Vector/Priority 15 */
+	u8	res101[12];
+	u32	iidr15;		/* Internal IRQ Destination 15 */
+	u8	res102[12];
+	u32	iivpr16;	/* Internal IRQ Vector/Priority 16 */
+	u8	res103[12];
+	u32	iidr16;		/* Internal IRQ Destination 16 */
+	u8	res104[12];
+	u32	iivpr17;	/* Internal IRQ Vector/Priority 17 */
+	u8	res105[12];
+	u32	iidr17;		/* Internal IRQ Destination 17 */
+	u8	res106[12];
+	u32	iivpr18;	/* Internal IRQ Vector/Priority 18 */
+	u8	res107[12];
+	u32	iidr18;		/* Internal IRQ Destination 18 */
+	u8	res108[12];
+	u32	iivpr19;	/* Internal IRQ Vector/Priority 19 */
+	u8	res109[12];
+	u32	iidr19;		/* Internal IRQ Destination 19 */
+	u8	res110[12];
+	u32	iivpr20;	/* Internal IRQ Vector/Priority 20 */
+	u8	res111[12];
+	u32	iidr20;		/* Internal IRQ Destination 20 */
+	u8	res112[12];
+	u32	iivpr21;	/* Internal IRQ Vector/Priority 21 */
+	u8	res113[12];
+	u32	iidr21;		/* Internal IRQ Destination 21 */
+	u8	res114[12];
+	u32	iivpr22;	/* Internal IRQ Vector/Priority 22 */
+	u8	res115[12];
+	u32	iidr22;		/* Internal IRQ Destination 22 */
+	u8	res116[12];
+	u32	iivpr23;	/* Internal IRQ Vector/Priority 23 */
+	u8	res117[12];
+	u32	iidr23;		/* Internal IRQ Destination 23 */
+	u8	res118[12];
+	u32	iivpr24;	/* Internal IRQ Vector/Priority 24 */
+	u8	res119[12];
+	u32	iidr24;		/* Internal IRQ Destination 24 */
+	u8	res120[12];
+	u32	iivpr25;	/* Internal IRQ Vector/Priority 25 */
+	u8	res121[12];
+	u32	iidr25;		/* Internal IRQ Destination 25 */
+	u8	res122[12];
+	u32	iivpr26;	/* Internal IRQ Vector/Priority 26 */
+	u8	res123[12];
+	u32	iidr26;		/* Internal IRQ Destination 26 */
+	u8	res124[12];
+	u32	iivpr27;	/* Internal IRQ Vector/Priority 27 */
+	u8	res125[12];
+	u32	iidr27;		/* Internal IRQ Destination 27 */
+	u8	res126[12];
+	u32	iivpr28;	/* Internal IRQ Vector/Priority 28 */
+	u8	res127[12];
+	u32	iidr28;		/* Internal IRQ Destination 28 */
+	u8	res128[12];
+	u32	iivpr29;	/* Internal IRQ Vector/Priority 29 */
+	u8	res129[12];
+	u32	iidr29;		/* Internal IRQ Destination 29 */
+	u8	res130[12];
+	u32	iivpr30;	/* Internal IRQ Vector/Priority 30 */
+	u8	res131[12];
+	u32	iidr30;		/* Internal IRQ Destination 30 */
+	u8	res132[12];
+	u32	iivpr31;	/* Internal IRQ Vector/Priority 31 */
+	u8	res133[12];
+	u32	iidr31;		/* Internal IRQ Destination 31 */
+	u8	res134[4108];
+	u32	mivpr0;		/* Messaging IRQ Vector/Priority 0 */
+	u8	res135[12];
+	u32	midr0;		/* Messaging IRQ Destination 0 */
+	u8	res136[12];
+	u32	mivpr1;		/* Messaging IRQ Vector/Priority 1 */
+	u8	res137[12];
+	u32	midr1;		/* Messaging IRQ Destination 1 */
+	u8	res138[12];
+	u32	mivpr2;		/* Messaging IRQ Vector/Priority 2 */
+	u8	res139[12];
+	u32	midr2;		/* Messaging IRQ Destination 2 */
+	u8	res140[12];
+	u32	mivpr3;		/* Messaging IRQ Vector/Priority 3 */
+	u8	res141[12];
+	u32	midr3;		/* Messaging IRQ Destination 3 */
+	u8	res142[59852];
+	u32	ipi0dr0;	/* Processor 0 Interprocessor IRQ Dispatch 0 */
+	u8	res143[12];
+	u32	ipi0dr1;	/* Processor 0 Interprocessor IRQ Dispatch 1 */
+	u8	res144[12];
+	u32	ipi0dr2;	/* Processor 0 Interprocessor IRQ Dispatch 2 */
+	u8	res145[12];
+	u32	ipi0dr3;	/* Processor 0 Interprocessor IRQ Dispatch 3 */
+	u8	res146[12];
+	u32	ctpr0;		/* Current Task Priority for Processor 0 */
+	u8	res147[12];
+	u32	whoami0;	/* Who Am I for Processor 0 */
+	u8	res148[12];
+	u32	iack0;		/* IRQ Acknowledge for Processor 0 */
+	u8	res149[12];
+	u32	eoi0;		/* End Of IRQ for Processor 0 */
+	u8	res150[130892];
+} ccsr_pic_t;
+
+/* CPM Block */
+#ifndef CONFIG_CPM2
+typedef struct ccsr_cpm {
+	u8 res[262144];
+} ccsr_cpm_t;
+#else
+/*
+ * DPARM
+ * General SIU
+ */
+typedef struct ccsr_cpm_siu {
+	u8	res1[80];
+	u32	smaer;
+	u32	smser;
+	u32	smevr;
+	u8	res2[4];
+	u32	lmaer;
+	u32	lmser;
+	u32	lmevr;
+	u8	res3[2964];
+} ccsr_cpm_siu_t;
+
+/* IRQ Controller */
+typedef struct ccsr_cpm_intctl {
+	u16	sicr;
+	u8	res1[2];
+	u32	sivec;
+	u32	sipnrh;
+	u32	sipnrl;
+	u32	siprr;
+	u32	scprrh;
+	u32	scprrl;
+	u32	simrh;
+	u32	simrl;
+	u32	siexr;
+	u8	res2[88];
+	u32	sccr;
+	u8	res3[124];
+} ccsr_cpm_intctl_t;
+
+/* input/output port */
+typedef struct ccsr_cpm_iop {
+	u32	pdira;
+	u32	ppara;
+	u32	psora;
+	u32	podra;
+	u32	pdata;
+	u8	res1[12];
+	u32	pdirb;
+	u32	pparb;
+	u32	psorb;
+	u32	podrb;
+	u32	pdatb;
+	u8	res2[12];
+	u32	pdirc;
+	u32	pparc;
+	u32	psorc;
+	u32	podrc;
+	u32	pdatc;
+	u8	res3[12];
+	u32	pdird;
+	u32	ppard;
+	u32	psord;
+	u32	podrd;
+	u32	pdatd;
+	u8	res4[12];
+} ccsr_cpm_iop_t;
+
+/* CPM timers */
+typedef struct ccsr_cpm_timer {
+	u8	tgcr1;
+	u8	res1[3];
+	u8	tgcr2;
+	u8	res2[11];
+	u16	tmr1;
+	u16	tmr2;
+	u16	trr1;
+	u16	trr2;
+	u16	tcr1;
+	u16	tcr2;
+	u16	tcn1;
+	u16	tcn2;
+	u16	tmr3;
+	u16	tmr4;
+	u16	trr3;
+	u16	trr4;
+	u16	tcr3;
+	u16	tcr4;
+	u16	tcn3;
+	u16	tcn4;
+	u16	ter1;
+	u16	ter2;
+	u16	ter3;
+	u16	ter4;
+	u8	res3[608];
+} ccsr_cpm_timer_t;
+
+/* SDMA */
+typedef struct ccsr_cpm_sdma {
+	u8	sdsr;
+	u8	res1[3];
+	u8	sdmr;
+	u8	res2[739];
+} ccsr_cpm_sdma_t;
+
+/* FCC1 */
+typedef struct ccsr_cpm_fcc1 {
+	u32	gfmr;
+	u32	fpsmr;
+	u16	ftodr;
+	u8	res1[2];
+	u16	fdsr;
+	u8	res2[2];
+	u16	fcce;
+	u8	res3[2];
+	u16	fccm;
+	u8	res4[2];
+	u8	fccs;
+	u8	res5[3];
+	u8	ftirr_phy[4];
+} ccsr_cpm_fcc1_t;
+
+/* FCC2 */
+typedef struct ccsr_cpm_fcc2 {
+	u32	gfmr;
+	u32	fpsmr;
+	u16	ftodr;
+	u8	res1[2];
+	u16	fdsr;
+	u8	res2[2];
+	u16	fcce;
+	u8	res3[2];
+	u16	fccm;
+	u8	res4[2];
+	u8	fccs;
+	u8	res5[3];
+	u8	ftirr_phy[4];
+} ccsr_cpm_fcc2_t;
+
+/* FCC3 */
+typedef struct ccsr_cpm_fcc3 {
+	u32	gfmr;
+	u32	fpsmr;
+	u16	ftodr;
+	u8	res1[2];
+	u16	fdsr;
+	u8	res2[2];
+	u16	fcce;
+	u8	res3[2];
+	u16	fccm;
+	u8	res4[2];
+	u8	fccs;
+	u8	res5[3];
+	u8	res[36];
+} ccsr_cpm_fcc3_t;
+
+/* FCC1 extended */
+typedef struct ccsr_cpm_fcc1_ext {
+	u32	firper;
+	u32	firer;
+	u32	firsr_h;
+	u32	firsr_l;
+	u8	gfemr;
+	u8	res[15];
+
+} ccsr_cpm_fcc1_ext_t;
+
+/* FCC2 extended */
+typedef struct ccsr_cpm_fcc2_ext {
+	u32	firper;
+	u32	firer;
+	u32	firsr_h;
+	u32	firsr_l;
+	u8	gfemr;
+	u8	res[31];
+} ccsr_cpm_fcc2_ext_t;
+
+/* FCC3 extended */
+typedef struct ccsr_cpm_fcc3_ext {
+	u8	gfemr;
+	u8	res[47];
+} ccsr_cpm_fcc3_ext_t;
+
+/* TC layers */
+typedef struct ccsr_cpm_tmp1 {
+	u8	res[496];
+} ccsr_cpm_tmp1_t;
+
+/* BRGs:5,6,7,8 */
+typedef struct ccsr_cpm_brg2 {
+	u32	brgc5;
+	u32	brgc6;
+	u32	brgc7;
+	u32	brgc8;
+	u8	res[608];
+} ccsr_cpm_brg2_t;
+
+/* I2C */
+typedef struct ccsr_cpm_i2c {
+	u8	i2mod;
+	u8	res1[3];
+	u8	i2add;
+	u8	res2[3];
+	u8	i2brg;
+	u8	res3[3];
+	u8	i2com;
+	u8	res4[3];
+	u8	i2cer;
+	u8	res5[3];
+	u8	i2cmr;
+	u8	res6[331];
+} ccsr_cpm_i2c_t;
+
+/* CPM core */
+typedef struct ccsr_cpm_cp {
+	u32	cpcr;
+	u32	rccr;
+	u8	res1[14];
+	u16	rter;
+	u8	res2[2];
+	u16	rtmr;
+	u16	rtscr;
+	u8	res3[2];
+	u32	rtsr;
+	u8	res4[12];
+} ccsr_cpm_cp_t;
+
+/* BRGs:1,2,3,4 */
+typedef struct ccsr_cpm_brg1 {
+	u32	brgc1;
+	u32	brgc2;
+	u32	brgc3;
+	u32	brgc4;
+} ccsr_cpm_brg1_t;
+
+/* SCC1-SCC4 */
+typedef struct ccsr_cpm_scc {
+	u32	gsmrl;
+	u32	gsmrh;
+	u16	psmr;
+	u8	res1[2];
+	u16	todr;
+	u16	dsr;
+	u16	scce;
+	u8	res2[2];
+	u16	sccm;
+	u8	res3;
+	u8	sccs;
+	u8	res4[8];
+} ccsr_cpm_scc_t;
+
+typedef struct ccsr_cpm_tmp2 {
+	u8	res[32];
+} ccsr_cpm_tmp2_t;
+
+/* SPI */
+typedef struct ccsr_cpm_spi {
+	u16	spmode;
+	u8	res1[4];
+	u8	spie;
+	u8	res2[3];
+	u8	spim;
+	u8	res3[2];
+	u8	spcom;
+	u8	res4[82];
+} ccsr_cpm_spi_t;
+
+/* CPM MUX */
+typedef struct ccsr_cpm_mux {
+	u8	cmxsi1cr;
+	u8	res1;
+	u8	cmxsi2cr;
+	u8	res2;
+	u32	cmxfcr;
+	u32	cmxscr;
+	u8	res3[2];
+	u16	cmxuar;
+	u8	res4[16];
+} ccsr_cpm_mux_t;
+
+/* SI,MCC,etc */
+typedef struct ccsr_cpm_tmp3 {
+	u8 res[58592];
+} ccsr_cpm_tmp3_t;
+
+typedef struct ccsr_cpm_iram {
+	u32	iram[8192];
+	u8	res[98304];
+} ccsr_cpm_iram_t;
+
+typedef struct ccsr_cpm {
+	/* Some references are into the unique & known dpram spaces,
+	 * others are from the generic base.
+	 */
+#define im_dprambase		im_dpram1
+	u8			im_dpram1[16*1024];
+	u8			res1[16*1024];
+	u8			im_dpram2[16*1024];
+	u8			res2[16*1024];
+	ccsr_cpm_siu_t		im_cpm_siu; /* SIU Configuration */
+	ccsr_cpm_intctl_t	im_cpm_intctl; /* IRQ Controller */
+	ccsr_cpm_iop_t		im_cpm_iop; /* IO Port control/status */
+	ccsr_cpm_timer_t	im_cpm_timer; /* CPM timers */
+	ccsr_cpm_sdma_t		im_cpm_sdma; /* SDMA control/status */
+	ccsr_cpm_fcc1_t		im_cpm_fcc1;
+	ccsr_cpm_fcc2_t		im_cpm_fcc2;
+	ccsr_cpm_fcc3_t		im_cpm_fcc3;
+	ccsr_cpm_fcc1_ext_t	im_cpm_fcc1_ext;
+	ccsr_cpm_fcc2_ext_t	im_cpm_fcc2_ext;
+	ccsr_cpm_fcc3_ext_t	im_cpm_fcc3_ext;
+	ccsr_cpm_tmp1_t		im_cpm_tmp1;
+	ccsr_cpm_brg2_t		im_cpm_brg2;
+	ccsr_cpm_i2c_t		im_cpm_i2c;
+	ccsr_cpm_cp_t		im_cpm_cp;
+	ccsr_cpm_brg1_t		im_cpm_brg1;
+	ccsr_cpm_scc_t		im_cpm_scc[4];
+	ccsr_cpm_tmp2_t		im_cpm_tmp2;
+	ccsr_cpm_spi_t		im_cpm_spi;
+	ccsr_cpm_mux_t		im_cpm_mux;
+	ccsr_cpm_tmp3_t		im_cpm_tmp3;
+	ccsr_cpm_iram_t		im_cpm_iram;
+} ccsr_cpm_t;
+#endif
+
+#ifdef CONFIG_SYS_SRIO
+/* Architectural regsiters */
+struct rio_arch {
+	u32	didcar;	/* Device Identity CAR */
+	u32	dicar;	/* Device Information CAR */
+	u32	aidcar;	/* Assembly Identity CAR */
+	u32	aicar;	/* Assembly Information CAR */
+	u32	pefcar;	/* Processing Element Features CAR */
+	u8	res0[4];
+	u32	socar;	/* Source Operations CAR */
+	u32	docar;	/* Destination Operations CAR */
+	u8	res1[32];
+	u32	mcsr;	/* Mailbox CSR */
+	u32	pwdcsr;	/* Port-Write and Doorbell CSR */
+	u8	res2[4];
+	u32	pellccsr;	/* Processing Element Logic Layer CCSR */
+	u8	res3[12];
+	u32	lcsbacsr;	/* Local Configuration Space BACSR */
+	u32	bdidcsr;	/* Base Device ID CSR */
+	u8	res4[4];
+	u32	hbdidlcsr;	/* Host Base Device ID Lock CSR */
+	u32	ctcsr;	/* Component Tag CSR */
+};
+
+/* Extended Features Space: 1x/4x LP-Serial Port registers */
+struct rio_lp_serial_port {
+	u32	plmreqcsr;	/* Port Link Maintenance Request CSR */
+	u32	plmrespcsr;	/* Port Link Maintenance Response CS */
+	u32	plascsr;	/* Port Local Ackid Status CSR */
+	u8	res0[12];
+	u32	pescsr;	/* Port Error and Status CSR */
+	u32	pccsr;	/* Port Control CSR */
+};
+
+/* Extended Features Space: 1x/4x LP-Serial registers */
+struct rio_lp_serial {
+	u32	pmbh0csr;	/* Port Maintenance Block Header 0 CSR */
+	u8	res0[28];
+	u32	pltoccsr;	/* Port Link Time-out CCSR */
+	u32	prtoccsr;	/* Port Response Time-out CCSR */
+	u8	res1[20];
+	u32	pgccsr;	/* Port General CSR */
+	struct rio_lp_serial_port	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Logical error reporting registers */
+struct rio_logical_err {
+	u32	erbh;	/* Error Reporting Block Header Register */
+	u8	res0[4];
+	u32	ltledcsr;	/* Logical/Transport layer error DCSR */
+	u32	ltleecsr;	/* Logical/Transport layer error ECSR */
+	u8	res1[4];
+	u32	ltlaccsr;	/* Logical/Transport layer ACCSR */
+	u32	ltldidccsr;	/* Logical/Transport layer DID CCSR */
+	u32	ltlcccsr;	/* Logical/Transport layer control CCSR */
+};
+
+/* Physical error reporting port registers */
+struct rio_phys_err_port {
+	u32	edcsr;	/* Port error detect CSR */
+	u32	erecsr;	/* Port error rate enable CSR */
+	u32	ecacsr;	/* Port error capture attributes CSR */
+	u32	pcseccsr0;	/* Port packet/control symbol ECCSR 0 */
+	u32	peccsr[3];	/* Port error capture CSR */
+	u8	res0[12];
+	u32	ercsr;	/* Port error rate CSR */
+	u32	ertcsr;	/* Port error rate threshold CSR */
+	u8	res1[16];
+};
+
+/* Physical error reporting registers */
+struct rio_phys_err {
+	struct rio_phys_err_port	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Implementation Space: General Port-Common */
+struct rio_impl_common {
+	u8	res0[4];
+	u32	llcr;	/* Logical Layer Configuration Register */
+	u8	res1[8];
+	u32	epwisr;	/* Error / Port-Write Interrupt SR */
+	u8	res2[12];
+	u32	lretcr;	/* Logical Retry Error Threshold CR */
+	u8	res3[92];
+	u32	pretcr;	/* Physical Retry Erorr Threshold CR */
+	u8	res4[124];
+};
+
+/* Implementation Space: Port Specific */
+struct rio_impl_port_spec {
+	u32	adidcsr;	/* Port Alt. Device ID CSR */
+	u8	res0[28];
+	u32	ptaacr;	/* Port Pass-Through/Accept-All CR */
+	u32	lopttlcr;
+	u8	res1[8];
+	u32	iecsr;	/* Port Implementation Error CSR */
+	u8	res2[12];
+	u32	pcr;		/* Port Phsyical Configuration Register */
+	u8	res3[20];
+	u32	slcsr;	/* Port Serial Link CSR */
+	u8	res4[4];
+	u32	sleicr;	/* Port Serial Link Error Injection */
+	u32	a0txcr;	/* Port Arbitration 0 Tx CR */
+	u32	a1txcr;	/* Port Arbitration 1 Tx CR */
+	u32	a2txcr;	/* Port Arbitration 2 Tx CR */
+	u32	mreqtxbacr[3];	/* Port Request Tx Buffer ACR */
+	u32	mrspfctxbacr;	/* Port Response/Flow Control Tx Buffer ACR */
+};
+
+/* Implementation Space: register */
+struct rio_implement {
+	struct rio_impl_common	com;
+	struct rio_impl_port_spec	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+/* Revision Control Register */
+struct rio_rev_ctrl {
+	u32	ipbrr[2];	/* IP Block Revision Register */
+};
+
+struct rio_atmu_row {
+	u32	rowtar; /* RapidIO Outbound Window TAR */
+	u32	rowtear; /* RapidIO Outbound Window TEAR */
+	u32	rowbar;
+	u8	res0[4];
+	u32	rowar; /* RapidIO Outbound Attributes Register */
+	u32	rowsr[3]; /* Port RapidIO outbound window segment register */
+};
+
+struct rio_atmu_riw {
+	u32	riwtar; /* RapidIO Inbound Window Translation AR */
+	u8	res0[4];
+	u32	riwbar; /* RapidIO Inbound Window Base AR */
+	u8	res1[4];
+	u32	riwar; /* RapidIO Inbound Attributes Register */
+	u8	res2[12];
+};
+
+/* ATMU window registers */
+struct rio_atmu_win {
+	struct rio_atmu_row	outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
+	u8	res0[64];
+	struct rio_atmu_riw	inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
+};
+
+struct rio_atmu {
+	struct rio_atmu_win	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+};
+
+#ifdef CONFIG_SYS_FSL_RMU
+struct rio_msg {
+	u32	omr; /* Outbound Mode Register */
+	u32	osr; /* Outbound Status Register */
+	u32	eodqdpar; /* Extended Outbound DQ DPAR */
+	u32	odqdpar; /* Outbound Descriptor Queue DPAR */
+	u32	eosar; /* Extended Outbound Unit Source AR */
+	u32	osar; /* Outbound Unit Source AR */
+	u32	odpr; /* Outbound Destination Port Register */
+	u32	odatr; /* Outbound Destination Attributes Register */
+	u32	odcr; /* Outbound Doubleword Count Register */
+	u32	eodqepar; /* Extended Outbound DQ EPAR */
+	u32	odqepar; /* Outbound Descriptor Queue EPAR */
+	u32	oretr; /* Outbound Retry Error Threshold Register */
+	u32	omgr; /* Outbound Multicast Group Register */
+	u32	omlr; /* Outbound Multicast List Register */
+	u8	res0[40];
+	u32	imr;	 /* Outbound Mode Register */
+	u32	isr; /* Inbound Status Register */
+	u32	eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
+	u32	idqdpar; /* Inbound Descriptor Queue DPAR */
+	u32	eifqepar; /* Extended Inbound Frame Queue EPAR */
+	u32	ifqepar; /* Inbound Frame Queue EPAR */
+	u32	imirir; /* Inbound Maximum Interrutp RIR */
+	u8	res1[4];
+	u32 eihqepar; /* Extended inbound message header queue EPAR */
+	u32 ihqepar; /* Inbound message header queue EPAR */
+	u8	res2[120];
+};
+
+struct rio_dbell {
+	u32	odmr; /* Outbound Doorbell Mode Register */
+	u32	odsr; /* Outbound Doorbell Status Register */
+	u8	res0[16];
+	u32	oddpr; /* Outbound Doorbell Destination Port */
+	u32	oddatr; /* Outbound Doorbell Destination AR */
+	u8	res1[12];
+	u32	oddretr; /* Outbound Doorbell Retry Threshold CR */
+	u8	res2[48];
+	u32	idmr; /* Inbound Doorbell Mode Register */
+	u32	idsr;	 /* Inbound Doorbell Status Register */
+	u32	iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
+	u32	iqdpar; /* Inbound Doorbell Queue DPAR */
+	u32	iedqepar; /* Extended Inbound Doorbell Queue EPAR */
+	u32	idqepar; /* Inbound Doorbell Queue EPAR */
+	u32	idmirir; /* Inbound Doorbell Max Interrupt RIR */
+};
+
+struct rio_pw {
+	u32	pwmr; /* Port-Write Mode Register */
+	u32	pwsr; /* Port-Write Status Register */
+	u32	epwqbar; /* Extended Port-Write Queue BAR */
+	u32	pwqbar; /* Port-Write Queue Base Address Register */
+};
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+struct rio_liodn {
+	u32	plbr;
+	u8	res0[28];
+	u32	plaor;
+	u8	res1[12];
+	u32	pludr;
+	u32	plldr;
+	u8	res2[456];
+};
+#endif
+
+/* RapidIO Registers */
+struct ccsr_rio {
+	struct rio_arch	arch;
+	u8	res0[144];
+	struct rio_lp_serial	lp_serial;
+	u8	res1[1152];
+	struct rio_logical_err	logical_err;
+	u8	res2[32];
+	struct rio_phys_err	phys_err;
+	u8	res3[63808];
+	struct rio_implement	impl;
+	u8	res4[2552];
+	struct rio_rev_ctrl	rev;
+	struct rio_atmu	atmu;
+#ifdef CONFIG_SYS_FSL_RMU
+	u8	res5[8192];
+	struct rio_msg	msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
+	u8	res6[512];
+	struct rio_dbell	dbell;
+	u8	res7[100];
+	struct rio_pw	pw;
+#endif
+#ifdef CONFIG_SYS_FSL_SRIO_LIODN
+	u8	res5[8192];
+	struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+#endif
+};
+#endif
+
+/* Quick Engine Block Pin Muxing Registers */
+typedef struct par_io {
+	u32	cpodr;
+	u32	cpdat;
+	u32	cpdir1;
+	u32	cpdir2;
+	u32	cppar1;
+	u32	cppar2;
+	u8	res[8];
+} par_io_t;
+
+#ifdef CONFIG_SYS_FSL_CPC
+/*
+ * Define a single offset that is the start of all the CPC register
+ * blocks - if there is more than one CPC, we expect these to be
+ * contiguous 4k regions
+ */
+
+typedef struct cpc_corenet {
+	u32 	cpccsr0;	/* Config/status reg */
+	u32	res1;
+	u32	cpccfg0;	/* Configuration register */
+	u32	res2;
+	u32	cpcewcr0;	/* External Write reg 0 */
+	u32	cpcewabr0;	/* External write base reg 0 */
+	u32	res3[2];
+	u32	cpcewcr1;	/* External Write reg 1 */
+	u32	cpcewabr1;	/* External write base reg 1 */
+	u32	res4[54];
+	u32	cpcsrcr1;	/* SRAM control reg 1 */
+	u32	cpcsrcr0;	/* SRAM control reg 0 */
+	u32	res5[62];
+	struct {
+		u32	id;	/* partition ID */
+		u32	res;
+		u32	alloc;	/* partition allocation */
+		u32	way;	/* partition way */
+	} partition_regs[16];
+	u32	res6[704];
+	u32	cpcerrinjhi;	/* Error injection high */
+	u32	cpcerrinjlo;	/* Error injection lo */
+	u32	cpcerrinjctl;	/* Error injection control */
+	u32	res7[5];
+	u32	cpccaptdatahi;	/* capture data high */
+	u32	cpccaptdatalo;	/* capture data low */
+	u32	cpcaptecc;	/* capture ECC */
+	u32	res8[5];
+	u32	cpcerrdet;	/* error detect */
+	u32	cpcerrdis;	/* error disable */
+	u32	cpcerrinten;	/* errir interrupt enable */
+	u32	cpcerrattr;	/* error attribute */
+	u32	cpcerreaddr;	/* error extended address */
+	u32	cpcerraddr;	/* error address */
+	u32	cpcerrctl;	/* error control */
+	u32	res9[41];	/* pad out to 4k */
+	u32	cpchdbcr0;	/* hardware debug control register 0 */
+	u32	res10[63];	/* pad out to 4k */
+} cpc_corenet_t;
+
+#define CPC_CSR0_CE	0x80000000	/* Cache Enable */
+#define CPC_CSR0_PE	0x40000000	/* Enable ECC */
+#define CPC_CSR0_FI	0x00200000	/* Cache Flash Invalidate */
+#define CPC_CSR0_WT	0x00080000	/* Write-through mode */
+#define CPC_CSR0_FL	0x00000800	/* Hardware cache flush */
+#define CPC_CSR0_LFC	0x00000400	/* Cache Lock Flash Clear */
+#define CPC_CFG0_SZ_MASK	0x00003fff
+#define CPC_CFG0_SZ_K(x)	((x & CPC_CFG0_SZ_MASK) << 6)
+#define CPC_CFG0_NUM_WAYS(x)	(((x >> 14) & 0x1f) + 1)
+#define CPC_CFG0_LINE_SZ(x)	((((x >> 23) & 0x3) + 1) * 32)
+#define CPC_SRCR1_SRBARU_MASK	0x0000ffff
+#define CPC_SRCR1_SRBARU(x)	(((unsigned long long)x >> 32) \
+				 & CPC_SRCR1_SRBARU_MASK)
+#define	CPC_SRCR0_SRBARL_MASK	0xffff8000
+#define CPC_SRCR0_SRBARL(x)	(x & CPC_SRCR0_SRBARL_MASK)
+#define CPC_SRCR0_INTLVEN	0x00000100
+#define CPC_SRCR0_SRAMSZ_1_WAY	0x00000000
+#define CPC_SRCR0_SRAMSZ_2_WAY	0x00000002
+#define CPC_SRCR0_SRAMSZ_4_WAY	0x00000004
+#define CPC_SRCR0_SRAMSZ_8_WAY	0x00000006
+#define CPC_SRCR0_SRAMSZ_16_WAY	0x00000008
+#define CPC_SRCR0_SRAMSZ_32_WAY	0x0000000a
+#define CPC_SRCR0_SRAMEN	0x00000001
+#define	CPC_ERRDIS_TMHITDIS  	0x00000080	/* multi-way hit disable */
+#define CPC_HDBCR0_CDQ_SPEC_DIS	0x08000000
+#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS	0x01000000
+#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS	0x00400000
+#define CPC_HDBCR0_SPLRU_LEVEL_EN	0x001e0000
+#endif /* CONFIG_SYS_FSL_CPC */
+
+/* Global Utilities Block */
+#ifdef CONFIG_FSL_CORENET
+typedef struct ccsr_gur {
+	u32	porsr1;		/* POR status 1 */
+	u32	porsr2;		/* POR status 2 */
+#ifdef	CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define	FSL_DCFG_PORSR1_SYSCLK_SHIFT	15
+#define	FSL_DCFG_PORSR1_SYSCLK_MASK	0x1
+#define	FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED	0x1
+#define	FSL_DCFG_PORSR1_SYSCLK_DIFF	0x0
+#endif
+	u8	res_008[0x20-0x8];
+	u32	gpporcr1;	/* General-purpose POR configuration */
+	u32	gpporcr2;	/* General-purpose POR configuration 2 */
+	u32	dcfg_fusesr;	/* Fuse status register */
+#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT	25
+#define FSL_CORENET_DCFG_FUSESR_VID_MASK	0x1F
+#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT	20
+#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK	0x1F
+	u8	res_02c[0x70-0x2c];
+	u32	devdisr;	/* Device disable control */
+	u32	devdisr2;	/* Device disable control 2 */
+	u32	devdisr3;	/* Device disable control 3 */
+	u32	devdisr4;	/* Device disable control 4 */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	u32	devdisr5;	/* Device disable control 5 */
+#define FSL_CORENET_DEVDISR_PBL	0x80000000
+#define FSL_CORENET_DEVDISR_PMAN	0x40000000
+#define FSL_CORENET_DEVDISR_ESDHC	0x20000000
+#define FSL_CORENET_DEVDISR_DMA1	0x00800000
+#define FSL_CORENET_DEVDISR_DMA2	0x00400000
+#define FSL_CORENET_DEVDISR_USB1	0x00080000
+#define FSL_CORENET_DEVDISR_USB2	0x00040000
+#define FSL_CORENET_DEVDISR_SATA1	0x00008000
+#define FSL_CORENET_DEVDISR_SATA2	0x00004000
+#define FSL_CORENET_DEVDISR_PME	0x00000800
+#define FSL_CORENET_DEVDISR_SEC	0x00000200
+#define FSL_CORENET_DEVDISR_RMU	0x00000080
+#define FSL_CORENET_DEVDISR_DCE	0x00000040
+#define FSL_CORENET_DEVDISR2_DTSEC1_1	0x80000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2	0x40000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3	0x20000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4	0x10000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5	0x08000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_6	0x04000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_9	0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_10	0x00400000
+#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+#define FSL_CORENET_DEVDISR2_10GEC1_1   0x80000000
+#define FSL_CORENET_DEVDISR2_10GEC1_2   0x40000000
+#else
+#define FSL_CORENET_DEVDISR2_10GEC1_1	0x00800000
+#define FSL_CORENET_DEVDISR2_10GEC1_2	0x00400000
+#define FSL_CORENET_DEVDISR2_10GEC1_3	0x80000000
+#define FSL_CORENET_DEVDISR2_10GEC1_4	0x40000000
+#endif
+#define FSL_CORENET_DEVDISR2_DTSEC2_1	0x00080000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00040000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00020000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5	0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_6	0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_9	0x00000800
+#define FSL_CORENET_DEVDISR2_DTSEC2_10	0x00000400
+#define FSL_CORENET_DEVDISR2_10GEC2_1	0x00000800
+#define FSL_CORENET_DEVDISR2_10GEC2_2	0x00000400
+#define FSL_CORENET_DEVDISR2_FM1	0x00000080
+#define FSL_CORENET_DEVDISR2_FM2	0x00000040
+#define FSL_CORENET_DEVDISR2_CPRI	0x00000008
+#define FSL_CORENET_DEVDISR3_PCIE1	0x80000000
+#define FSL_CORENET_DEVDISR3_PCIE2	0x40000000
+#define FSL_CORENET_DEVDISR3_PCIE3	0x20000000
+#define FSL_CORENET_DEVDISR3_PCIE4	0x10000000
+#define FSL_CORENET_DEVDISR3_SRIO1	0x08000000
+#define FSL_CORENET_DEVDISR3_SRIO2	0x04000000
+#define FSL_CORENET_DEVDISR3_QMAN	0x00080000
+#define FSL_CORENET_DEVDISR3_BMAN	0x00040000
+#define FSL_CORENET_DEVDISR3_LA1	0x00008000
+#define FSL_CORENET_DEVDISR3_MAPLE1	0x00000800
+#define FSL_CORENET_DEVDISR3_MAPLE2	0x00000400
+#define FSL_CORENET_DEVDISR3_MAPLE3	0x00000200
+#define FSL_CORENET_DEVDISR4_I2C1	0x80000000
+#define FSL_CORENET_DEVDISR4_I2C2	0x40000000
+#define FSL_CORENET_DEVDISR4_DUART1	0x20000000
+#define FSL_CORENET_DEVDISR4_DUART2	0x10000000
+#define FSL_CORENET_DEVDISR4_ESPI	0x08000000
+#define FSL_CORENET_DEVDISR5_DDR1	0x80000000
+#define FSL_CORENET_DEVDISR5_DDR2	0x40000000
+#define FSL_CORENET_DEVDISR5_DDR3	0x20000000
+#define FSL_CORENET_DEVDISR5_CPC1	0x08000000
+#define FSL_CORENET_DEVDISR5_CPC2	0x04000000
+#define FSL_CORENET_DEVDISR5_CPC3	0x02000000
+#define FSL_CORENET_DEVDISR5_IFC	0x00800000
+#define FSL_CORENET_DEVDISR5_GPIO	0x00400000
+#define FSL_CORENET_DEVDISR5_DBG	0x00200000
+#define FSL_CORENET_DEVDISR5_NAL	0x00100000
+#define FSL_CORENET_DEVDISR5_TIMERS	0x00020000
+#define FSL_CORENET_NUM_DEVDISR		5
+#else
+#define FSL_CORENET_DEVDISR_PCIE1	0x80000000
+#define FSL_CORENET_DEVDISR_PCIE2	0x40000000
+#define FSL_CORENET_DEVDISR_PCIE3	0x20000000
+#define FSL_CORENET_DEVDISR_PCIE4	0x10000000
+#define FSL_CORENET_DEVDISR_RMU		0x08000000
+#define FSL_CORENET_DEVDISR_SRIO1	0x04000000
+#define FSL_CORENET_DEVDISR_SRIO2	0x02000000
+#define FSL_CORENET_DEVDISR_DMA1	0x00400000
+#define FSL_CORENET_DEVDISR_DMA2	0x00200000
+#define FSL_CORENET_DEVDISR_DDR1	0x00100000
+#define FSL_CORENET_DEVDISR_DDR2	0x00080000
+#define FSL_CORENET_DEVDISR_DBG		0x00010000
+#define FSL_CORENET_DEVDISR_NAL		0x00008000
+#define FSL_CORENET_DEVDISR_SATA1	0x00004000
+#define FSL_CORENET_DEVDISR_SATA2	0x00002000
+#define FSL_CORENET_DEVDISR_ELBC	0x00001000
+#define FSL_CORENET_DEVDISR_USB1	0x00000800
+#define FSL_CORENET_DEVDISR_USB2	0x00000400
+#define FSL_CORENET_DEVDISR_ESDHC	0x00000100
+#define FSL_CORENET_DEVDISR_GPIO	0x00000080
+#define FSL_CORENET_DEVDISR_ESPI	0x00000040
+#define FSL_CORENET_DEVDISR_I2C1	0x00000020
+#define FSL_CORENET_DEVDISR_I2C2	0x00000010
+#define FSL_CORENET_DEVDISR_DUART1	0x00000002
+#define FSL_CORENET_DEVDISR_DUART2	0x00000001
+#define FSL_CORENET_DEVDISR2_PME	0x80000000
+#define FSL_CORENET_DEVDISR2_SEC	0x40000000
+#define FSL_CORENET_DEVDISR2_QMBM	0x08000000
+#define FSL_CORENET_DEVDISR2_FM1	0x02000000
+#define FSL_CORENET_DEVDISR2_10GEC1	0x01000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_1	0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2	0x00400000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3	0x00200000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4	0x00100000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5	0x00080000
+#define FSL_CORENET_DEVDISR2_FM2	0x00020000
+#define FSL_CORENET_DEVDISR2_10GEC2	0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_1	0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00002000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00001000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5	0x00000800
+#define FSL_CORENET_NUM_DEVDISR		2
+	u32	powmgtcsr;	/* Power management status & control */
+#endif
+	u8	res8[12];
+	u32	coredisru;	/* uppper portion for support of 64 cores */
+	u32	coredisrl;	/* lower portion for support of 64 cores */
+	u8	res9[8];
+	u32	pvr;		/* Processor version */
+	u32	svr;		/* System version */
+	u8	res10[8];
+	u32	rstcr;		/* Reset control */
+	u32	rstrqpblsr;	/* Reset request preboot loader status */
+	u8	res11[8];
+	u32	rstrqmr1;	/* Reset request mask */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK      0x00000800
+#endif
+	u8	res12[4];
+	u32	rstrqsr1;	/* Reset request status */
+	u8	res13[4];
+	u8	res14[4];
+	u32	rstrqwdtmrl;	/* Reset request WDT mask */
+	u8	res15[4];
+	u32	rstrqwdtsrl;	/* Reset request WDT status */
+	u8	res16[4];
+	u32	brrl;		/* Boot release */
+	u8	res17[24];
+	u32	rcwsr[16];	/* Reset control word status */
+#define RCW_SB_EN_REG_INDEX	7
+#define RCW_SB_EN_MASK		0x00200000
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	16
+/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT	8
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x3f
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xfc000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	26
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00fe0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL		0x0000f800
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT	11
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL		0x000000f8
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT	3
+#define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
+#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xfe000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	25
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
+#define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
+#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xff000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00fe0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
+#define FSL_CORENET_RCWSR13_EC1	0x30000000 /* bits 418..419 */
+#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO	0x10000000
+#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII	0x20000000
+#define FSL_CORENET_RCWSR13_EC2	0x0c000000 /* bits 420..421 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO	0x04000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL	0x00000080
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH	0x00000000
+#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT	0x00000080
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET	0x28
+#define PXCKEN_MASK	0x80000000
+#define PXCK_MASK	0x00FF0000
+#define PXCK_BITS_START	16
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xff800000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	23
+#define FSL_CORENET_RCWSR6_BOOT_LOC		0x0f800000
+#define FSL_CORENET_RCWSR13_EC1			0x30000000 /* bits 418..419 */
+#define FSL_CORENET_RCWSR13_EC1_RGMII		0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO		0x10000000
+#define FSL_CORENET_RCWSR13_EC2			0x0c000000
+#define FSL_CORENET_RCWSR13_EC2_RGMII		0x08000000
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET	0x28
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET	0xd00
+#define PXCKEN_MASK				0x80000000
+#define PXCK_MASK				0x00FF0000
+#define PXCK_BITS_START				16
+#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xff000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
+#define FSL_CORENET_RCWSR6_BOOT_LOC		0x0f800000
+#endif
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1	0x00800000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2	0x00400000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1	0x00200000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2	0x00100000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1	0x00080000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2	0x00040000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1	0x00020000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2	0x00010000
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK	0x00000011
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK	1
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x1f
+#define FSL_CORENET_RCWSR4_SRDS_PRTCL		0xfc000000
+#define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
+#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7
+#define FSL_CORENET_RCWSR5_SRDS_EN		0x00002000
+#define FSL_CORENET_RCWSR5_SRDS2_EN		0x00001000
+#define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
+#define FSL_CORENET_RCWSRn_SRDS_LPD_B2		0x3c000000 /* bits 162..165 */
+#define FSL_CORENET_RCWSRn_SRDS_LPD_B3		0x003c0000 /* bits 170..173 */
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT	0x00400000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B1		0x00e00000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B2		0x00100000
+#define FSL_CORENET_RCWSR11_EC1			0x00c00000 /* bits 360..361 */
+#ifdef CONFIG_ARCH_P4080
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1		0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_USB1		0x00800000
+#define FSL_CORENET_RCWSR11_EC2			0x001c0000 /* bits 363..365 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1		0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2		0x00080000
+#define FSL_CORENET_RCWSR11_EC2_USB2			0x00100000
+#endif
+#if defined(CONFIG_ARCH_P2041) || \
+	defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII	0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII		0x00800000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE		0x00c00000
+#define FSL_CORENET_RCWSR11_EC2			0x00180000 /* bits 363..364 */
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII	0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII		0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE		0x00180000
+#endif
+#if defined(CONFIG_ARCH_P5040)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII        0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII          0x00800000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE         0x00c00000
+#define FSL_CORENET_RCWSR11_EC2                 0x00180000 /* bits 363..364 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII        0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
+#endif
+#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
+#define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO		0x40000000
+#define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII	0x08000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO		0x10000000
+#endif
+#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO		0x40000000
+#define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII	0x08000000
+#define FSL_CORENET_RCWSR13_EC2_GPIO		0x10000000
+#endif
+	u8	res18[192];
+	u32	scratchrw[4];	/* Scratch Read/Write */
+	u8	res19[240];
+	u32	scratchw1r[4];	/* Scratch Read (Write once) */
+	u8	res20[240];
+	u32	scrtsr[8];	/* Core reset status */
+	u8	res21[224];
+	u32	pex1liodnr;	/* PCI Express 1 LIODN */
+	u32	pex2liodnr;	/* PCI Express 2 LIODN */
+	u32	pex3liodnr;	/* PCI Express 3 LIODN */
+	u32	pex4liodnr;	/* PCI Express 4 LIODN */
+	u32	rio1liodnr;	/* RIO 1 LIODN */
+	u32	rio2liodnr;	/* RIO 2 LIODN */
+	u32	rio3liodnr;	/* RIO 3 LIODN */
+	u32	rio4liodnr;	/* RIO 4 LIODN */
+	u32	usb1liodnr;	/* USB 1 LIODN */
+	u32	usb2liodnr;	/* USB 2 LIODN */
+	u32	usb3liodnr;	/* USB 3 LIODN */
+	u32	usb4liodnr;	/* USB 4 LIODN */
+	u32	sdmmc1liodnr;	/* SD/MMC 1 LIODN */
+	u32	sdmmc2liodnr;	/* SD/MMC 2 LIODN */
+	u32	sdmmc3liodnr;	/* SD/MMC 3 LIODN */
+	u32	sdmmc4liodnr;	/* SD/MMC 4 LIODN */
+	u32	rio1maintliodnr;/* RIO 1 Maintenance LIODN */
+	u32	rio2maintliodnr;/* RIO 2 Maintenance LIODN */
+	u32	rio3maintliodnr;/* RIO 3 Maintenance LIODN */
+	u32	rio4maintliodnr;/* RIO 4 Maintenance LIODN */
+	u32	sata1liodnr;	/* SATA 1 LIODN */
+	u32	sata2liodnr;	/* SATA 2 LIODN */
+	u32	sata3liodnr;	/* SATA 3 LIODN */
+	u32	sata4liodnr;	/* SATA 4 LIODN */
+	u8	res22[20];
+	u32	tdmliodnr;	/* TDM LIODN */
+	u32     qeliodnr;       /* QE LIODN */
+	u8      res_57c[4];
+	u32	dma1liodnr;	/* DMA 1 LIODN */
+	u32	dma2liodnr;	/* DMA 2 LIODN */
+	u32	dma3liodnr;	/* DMA 3 LIODN */
+	u32	dma4liodnr;	/* DMA 4 LIODN */
+	u8	res23[48];
+	u8	res24[64];
+	u32	pblsr;		/* Preboot loader status */
+	u32	pamubypenr;	/* PAMU bypass enable */
+	u32	dmacr1;		/* DMA control */
+	u8	res25[4];
+	u32	gensr1;		/* General status */
+	u8	res26[12];
+	u32	gencr1;		/* General control */
+	u8	res27[12];
+	u8	res28[4];
+	u32	cgensrl;	/* Core general status */
+	u8	res29[8];
+	u8	res30[4];
+	u32	cgencrl;	/* Core general control */
+	u8	res31[184];
+	u32	sriopstecr;	/* SRIO prescaler timer enable control */
+	u32	dcsrcr;		/* DCSR Control register */
+	u8	res31a[56];
+	u32	tp_ityp[64];	/* Topology Initiator Type Register */
+	struct {
+		u32	upper;
+		u32	lower;
+	} tp_cluster[16];	/* Core Cluster n Topology Register */
+	u8	res32[1344];
+	u32	pmuxcr;		/* Pin multiplexing control */
+	u8	res33[60];
+	u32	iovselsr;	/* I/O voltage selection status */
+	u8	res34[28];
+	u32	ddrclkdr;	/* DDR clock disable */
+	u8	res35;
+	u32	elbcclkdr;	/* eLBC clock disable */
+	u8	res36[20];
+	u32	sdhcpcr;	/* eSDHC polarity configuration */
+	u8	res37[380];
+} ccsr_gur_t;
+
+#define TP_ITYP_AV	0x00000001		/* Initiator available */
+#define TP_ITYP_TYPE(x)	(((x) & 0x6) >> 1)	/* Initiator Type */
+#define TP_ITYP_TYPE_OTHER	0x0
+#define TP_ITYP_TYPE_PPC	0x1	/* PowerPC */
+#define TP_ITYP_TYPE_SC		0x2	/* StarCore DSP */
+#define TP_ITYP_TYPE_HA		0x3	/* HW Accelerator */
+#define TP_ITYP_THDS(x)	(((x) & 0x18) >> 3)	/* # threads */
+#define TP_ITYP_VER(x)	(((x) & 0xe0) >> 5)	/* Initiator Version */
+
+#define TP_CLUSTER_EOC		0x80000000	/* end of clusters */
+#define TP_CLUSTER_INIT_MASK	0x0000003f	/* initiator mask */
+#define TP_INIT_PER_CLUSTER	4
+
+#define FSL_CORENET_DCSR_SZ_MASK	0x00000003
+#define FSL_CORENET_DCSR_SZ_4M		0x0
+#define FSL_CORENET_DCSR_SZ_1G		0x3
+
+/*
+ * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
+ * everything after has RMan thus msg unit LIODN is used for maintenance
+ */
+#define rmuliodnr rio1maintliodnr
+
+typedef struct ccsr_clk {
+	struct {
+		u32 clkcncsr;	/* core cluster n clock control status */
+		u8  res_004[0x0c];
+		u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
+		u8  res_014[0x0c];
+	} clkcsr[12];
+	u8	res_100[0x680]; /* 0x100 */
+	struct {
+		u32 pllcngsr;
+		u8 res10[0x1c];
+	} pllcgsr[12];
+	u8	res21[0x280];
+	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
+	u8	res16[0x1c];
+	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
+	u8	res17[0x3dc];
+} ccsr_clk_t;
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+typedef struct ccsr_rcpm {
+	u8	res_00[12];
+	u32	tph10sr0;	/* Thread PH10 Status Register */
+	u8	res_10[12];
+	u32	tph10setr0;	/* Thread PH10 Set Control Register */
+	u8	res_20[12];
+	u32	tph10clrr0;	/* Thread PH10 Clear Control Register */
+	u8	res_30[12];
+	u32	tph10psr0;	/* Thread PH10 Previous Status Register */
+	u8	res_40[12];
+	u32	twaitsr0;	/* Thread Wait Status Register */
+	u8	res_50[96];
+	u32	pcph15sr;	/* Physical Core PH15 Status Register */
+	u32	pcph15setr;	/* Physical Core PH15 Set Control Register */
+	u32	pcph15clrr;	/* Physical Core PH15 Clear Control Register */
+	u32	pcph15psr;	/* Physical Core PH15 Prev Status Register */
+	u8	res_c0[16];
+	u32	pcph20sr;	/* Physical Core PH20 Status Register */
+	u32	pcph20setr;	/* Physical Core PH20 Set Control Register */
+	u32	pcph20clrr;	/* Physical Core PH20 Clear Control Register */
+	u32	pcph20psr;	/* Physical Core PH20 Prev Status Register */
+	u32	pcpw20sr;	/* Physical Core PW20 Status Register */
+	u8	res_e0[12];
+	u32	pcph30sr;	/* Physical Core PH30 Status Register */
+	u32	pcph30setr;	/* Physical Core PH30 Set Control Register */
+	u32	pcph30clrr;	/* Physical Core PH30 Clear Control Register */
+	u32	pcph30psr;	/* Physical Core PH30 Prev Status Register */
+	u8	res_100[32];
+	u32	ippwrgatecr;	/* IP Power Gating Control Register */
+	u8	res_124[12];
+	u32	powmgtcsr;	/* Power Management Control & Status Reg */
+	u8	res_134[12];
+	u32	ippdexpcr[4];	/* IP Powerdown Exception Control Reg */
+	u8	res_150[12];
+	u32	tpmimr0;	/* Thread PM Interrupt Mask Reg */
+	u8	res_160[12];
+	u32	tpmcimr0;	/* Thread PM Crit Interrupt Mask Reg */
+	u8	res_170[12];
+	u32	tpmmcmr0;	/* Thread PM Machine Check Interrupt Mask Reg */
+	u8	res_180[12];
+	u32	tpmnmimr0;	/* Thread PM NMI Mask Reg */
+	u8	res_190[12];
+	u32	tmcpmaskcr0;	/* Thread Machine Check Mask Control Reg */
+	u32	pctbenr;	/* Physical Core Time Base Enable Reg */
+	u32	pctbclkselr;	/* Physical Core Time Base Clock Select */
+	u32	tbclkdivr;	/* Time Base Clock Divider Register */
+	u8	res_1ac[4];
+	u32	ttbhltcr[4];	/* Thread Time Base Halt Control Register */
+	u32	clpcl10sr;	/* Cluster PCL10 Status Register */
+	u32	clpcl10setr;	/* Cluster PCL30 Set Control Register */
+	u32	clpcl10clrr;	/* Cluster PCL30 Clear Control Register */
+	u32	clpcl10psr;	/* Cluster PCL30 Prev Status Register */
+	u32	cddslpsetr;	/* Core Domain Deep Sleep Set Register */
+	u32	cddslpclrr;	/* Core Domain Deep Sleep Clear Register */
+	u32	cdpwroksetr;	/* Core Domain Power OK Set Register */
+	u32	cdpwrokclrr;	/* Core Domain Power OK Clear Register */
+	u32	cdpwrensr;	/* Core Domain Power Enable Status Register */
+	u32	cddslsr;	/* Core Domain Deep Sleep Status Register */
+	u8	res_1e8[8];
+	u32	dslpcntcr[8];	/* Deep Sleep Counter Cfg Register */
+	u8	res_300[3568];
+} ccsr_rcpm_t;
+
+#define ctbenrl pctbenr
+
+#else
+typedef struct ccsr_rcpm {
+	u8	res1[4];
+	u32	cdozsrl;	/* Core Doze Status */
+	u8	res2[4];
+	u32	cdozcrl;	/* Core Doze Control */
+	u8	res3[4];
+	u32	cnapsrl;	/* Core Nap Status */
+	u8	res4[4];
+	u32	cnapcrl;	/* Core Nap Control */
+	u8	res5[4];
+	u32	cdozpsrl;	/* Core Doze Previous Status */
+	u8	res6[4];
+	u32	cdozpcrl;	/* Core Doze Previous Control */
+	u8	res7[4];
+	u32	cwaitsrl;	/* Core Wait Status */
+	u8	res8[8];
+	u32	powmgtcsr;	/* Power Mangement Control & Status */
+	u8	res9[12];
+	u32	ippdexpcr0;	/* IP Powerdown Exception Control 0 */
+	u8	res10[12];
+	u8	res11[4];
+	u32	cpmimrl;	/* Core PM IRQ Masking */
+	u8	res12[4];
+	u32	cpmcimrl;	/* Core PM Critical IRQ Masking */
+	u8	res13[4];
+	u32	cpmmcimrl;	/* Core PM Machine Check IRQ Masking */
+	u8	res14[4];
+	u32	cpmnmimrl;	/* Core PM NMI Masking */
+	u8	res15[4];
+	u32	ctbenrl;	/* Core Time Base Enable */
+	u8	res16[4];
+	u32	ctbclkselrl;	/* Core Time Base Clock Select */
+	u8	res17[4];
+	u32	ctbhltcrl;	/* Core Time Base Halt Control */
+	u8	res18[0xf68];
+} ccsr_rcpm_t;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#else
+typedef struct ccsr_gur {
+	u32	porpllsr;	/* POR PLL ratio status */
+#ifdef CONFIG_ARCH_MPC8536
+#define MPC85xx_PORPLLSR_DDR_RATIO	0x3e000000
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	25
+#elif defined(CONFIG_ARCH_C29X)
+#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	(9 - ((gur->pordevsr2 \
+					& MPC85xx_PORDEVSR2_DDR_SPD_0) \
+					>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
+#else
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
+#else
+#define MPC85xx_PORPLLSR_DDR_RATIO	0x00003e00
+#endif
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	9
+#endif
+#define MPC85xx_PORPLLSR_QE_RATIO	0x3e000000
+#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT		25
+#define MPC85xx_PORPLLSR_PLAT_RATIO	0x0000003e
+#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT	1
+	u32	porbmsr;	/* POR boot mode status */
+#define MPC85xx_PORBMSR_HA		0x00070000
+#define MPC85xx_PORBMSR_HA_SHIFT	16
+#define MPC85xx_PORBMSR_ROMLOC_SHIFT	24
+#define PORBMSR_ROMLOC_SPI	0x6
+#define PORBMSR_ROMLOC_SDHC	0x7
+#define PORBMSR_ROMLOC_NAND_2K	0x9
+#define PORBMSR_ROMLOC_NOR	0xf
+	u32	porimpscr;	/* POR I/O impedance status & control */
+	u32	pordevsr;	/* POR I/O device status regsiter */
+#if defined(CONFIG_ARCH_P1023)
+#define MPC85xx_PORDEVSR_SGMII1_DIS	0x10000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS	0x08000000
+#define MPC85xx_PORDEVSR_TSEC1_PRTC	0x02000000
+#else
+#define MPC85xx_PORDEVSR_SGMII1_DIS	0x20000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS	0x10000000
+#endif
+#define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
+#define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
+#define MPC85xx_PORDEVSR_SRDS2_IO_SEL	0x38000000
+#define MPC85xx_PORDEVSR_PCI1		0x00800000
+#if defined(CONFIG_ARCH_P1022)
+#define MPC85xx_PORDEVSR_IO_SEL		0x007c0000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	18
+#elif defined(CONFIG_ARCH_P1023)
+#define MPC85xx_PORDEVSR_IO_SEL		0x00600000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
+#else
+#if defined(CONFIG_ARCH_P1010)
+#define MPC85xx_PORDEVSR_IO_SEL		0x00600000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
+#elif defined(CONFIG_ARCH_BSC9132)
+#define MPC85xx_PORDEVSR_IO_SEL		0x00FE0000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	17
+#elif defined(CONFIG_ARCH_C29X)
+#define MPC85xx_PORDEVSR_IO_SEL		0x00e00000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
+#else
+#define MPC85xx_PORDEVSR_IO_SEL		0x00780000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	19
+#endif /* if defined(CONFIG_ARCH_P1010) */
+#endif
+#define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
+#define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000
+#define MPC85xx_PORDEVSR_PCI1_PCI32	0x00010000
+#define MPC85xx_PORDEVSR_PCI1_SPD	0x00008000
+#define MPC85xx_PORDEVSR_PCI2_SPD	0x00004000
+#define MPC85xx_PORDEVSR_DRAM_RTYPE	0x00000060
+#define MPC85xx_PORDEVSR_RIO_CTLS	0x00000008
+#define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
+	u32	pordbgmsr;	/* POR debug mode status */
+	u32	pordevsr2;	/* POR I/O device status 2 */
+#if defined(CONFIG_ARCH_C29X)
+#define MPC85xx_PORDEVSR2_DDR_SPD_0	0x00000008
+#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT	3
+#endif
+#define MPC85xx_PORDEVSR2_SBC_MASK	0x10000000
+/* The 8544 RM says this is bit 26, but it's really bit 24 */
+#define MPC85xx_PORDEVSR2_SEC_CFG	0x00000080
+	u8	res1[8];
+	u32	gpporcr;	/* General-purpose POR configuration */
+	u8	res2[12];
+#if defined(CONFIG_ARCH_MPC8536)
+	u32	gencfgr;	/* General Configuration Register */
+#define MPC85xx_GENCFGR_SDHC_WP_INV	0x20000000
+#else
+	u32	gpiocr;		/* GPIO control */
+#endif
+	u8	res3[12];
+#if defined(CONFIG_ARCH_MPC8569)
+	u32	plppar1;	/* Platform port pin assignment 1 */
+	u32	plppar2;	/* Platform port pin assignment 2 */
+	u32	plpdir1;	/* Platform port pin direction 1 */
+	u32	plpdir2;	/* Platform port pin direction 2 */
+#else
+	u32	gpoutdr;	/* General-purpose output data */
+	u8	res4[12];
+#endif
+	u32	gpindr;		/* General-purpose input data */
+	u8	res5[12];
+	u32	pmuxcr;		/* Alt. function signal multiplex control */
+#if defined(CONFIG_ARCH_P1010)
+#define MPC85xx_PMUXCR_TSEC1_0_1588		0x40000000
+#define MPC85xx_PMUXCR_TSEC1_0_RES		0xC0000000
+#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG	0x10000000
+#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12		0x20000000
+#define MPC85xx_PMUXCR_TSEC1_1_RES		0x30000000
+#define MPC85xx_PMUXCR_TSEC1_2_DMA		0x04000000
+#define MPC85xx_PMUXCR_TSEC1_2_GPIO		0x08000000
+#define MPC85xx_PMUXCR_TSEC1_2_RES		0x0C000000
+#define MPC85xx_PMUXCR_TSEC1_3_RES		0x01000000
+#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15		0x02000000
+#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC		0x00400000
+#define MPC85xx_PMUXCR_IFC_ADDR16_USB		0x00800000
+#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2	0x00C00000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC	0x00100000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB	0x00200000
+#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA	0x00300000
+#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA	0x00040000
+#define MPC85xx_PMUXCR_IFC_ADDR19_USB		0x00080000
+#define MPC85xx_PMUXCR_IFC_ADDR19_DMA		0x000C0000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA	0x00010000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB	0x00020000
+#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES	0x00030000
+#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC		0x00004000
+#define MPC85xx_PMUXCR_IFC_ADDR22_USB		0x00008000
+#define MPC85xx_PMUXCR_IFC_ADDR22_RES		0x0000C000
+#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC		0x00001000
+#define MPC85xx_PMUXCR_IFC_ADDR23_USB		0x00002000
+#define MPC85xx_PMUXCR_IFC_ADDR23_RES		0x00003000
+#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC		0x00000400
+#define MPC85xx_PMUXCR_IFC_ADDR24_USB		0x00000800
+#define MPC85xx_PMUXCR_IFC_ADDR24_RES		0x00000C00
+#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES		0x00000300
+#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB		0x00000200
+#define MPC85xx_PMUXCR_LCLK_RES			0x00000040
+#define MPC85xx_PMUXCR_LCLK_USB			0x00000080
+#define MPC85xx_PMUXCR_LCLK_IFC_CS3		0x000000C0
+#define MPC85xx_PMUXCR_SPI_RES			0x00000030
+#define MPC85xx_PMUXCR_SPI_GPIO			0x00000020
+#define MPC85xx_PMUXCR_CAN1_UART		0x00000004
+#define MPC85xx_PMUXCR_CAN1_TDM			0x00000008
+#define MPC85xx_PMUXCR_CAN1_RES			0x0000000C
+#define MPC85xx_PMUXCR_CAN2_UART		0x00000001
+#define MPC85xx_PMUXCR_CAN2_TDM			0x00000002
+#define MPC85xx_PMUXCR_CAN2_RES			0x00000003
+#endif
+#if defined(CONFIG_ARCH_P1023)
+#define MPC85xx_PMUXCR_TSEC1_1		0x10000000
+#else
+#define MPC85xx_PMUXCR_SD_DATA		0x80000000
+#define MPC85xx_PMUXCR_SDHC_CD		0x40000000
+#define MPC85xx_PMUXCR_SDHC_WP		0x20000000
+#define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON	0x01000000
+#define MPC85xx_PMUXCR_TDM_ENA		0x00800000
+#define MPC85xx_PMUXCR_QE0		0x00008000
+#define MPC85xx_PMUXCR_QE1		0x00004000
+#define MPC85xx_PMUXCR_QE2		0x00002000
+#define MPC85xx_PMUXCR_QE3		0x00001000
+#define MPC85xx_PMUXCR_QE4		0x00000800
+#define MPC85xx_PMUXCR_QE5		0x00000400
+#define MPC85xx_PMUXCR_QE6		0x00000200
+#define MPC85xx_PMUXCR_QE7		0x00000100
+#define MPC85xx_PMUXCR_QE8		0x00000080
+#define MPC85xx_PMUXCR_QE9		0x00000040
+#define MPC85xx_PMUXCR_QE10		0x00000020
+#define MPC85xx_PMUXCR_QE11		0x00000010
+#define MPC85xx_PMUXCR_QE12		0x00000008
+#endif
+#if defined(CONFIG_ARCH_P1022)
+#define MPC85xx_PMUXCR_TDM_MASK		0x0001cc00
+#define MPC85xx_PMUXCR_TDM		0x00014800
+#define MPC85xx_PMUXCR_SPI_MASK		0x00600000
+#define MPC85xx_PMUXCR_SPI		0x00000000
+#endif
+#if defined(CONFIG_ARCH_BSC9131)
+#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ	0x40000000
+#define MPC85xx_PMUXCR_TSEC2_USB		0xC0000000
+#define MPC85xx_PMUXCR_TSEC2_1588_PPS		0x10000000
+#define MPC85xx_PMUXCR_TSEC2_1588_RSVD		0x30000000
+#define MPC85xx_PMUXCR_IFC_AD_GPIO		0x04000000
+#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK		0x0C000000
+#define MPC85xx_PMUXCR_IFC_AD15_GPIO		0x01000000
+#define MPC85xx_PMUXCR_IFC_AD15_TIMER2		0x02000000
+#define MPC85xx_PMUXCR_IFC_AD16_GPO8		0x00400000
+#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0		0x00800000
+#define MPC85xx_PMUXCR_IFC_AD17_GPO		0x00100000
+#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK	0x00300000
+#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP	0x00200000
+#define MPC85xx_PMUXCR_IFC_CS2_GPO65		0x00040000
+#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI		0x00080000
+#define MPC85xx_PMUXCR_SDHC_USIM		0x00010000
+#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK		0x00020000
+#define MPC85xx_PMUXCR_SDHC_GPIO77		0x00030000
+#define MPC85xx_PMUXCR_SDHC_RESV		0x00004000
+#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD		0x00008000
+#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4		0x0000C000
+#define MPC85xx_PMUXCR_USB_CLK_UART_SIN		0x00001000
+#define MPC85xx_PMUXCR_USB_CLK_GPIO69		0x00002000
+#define MPC85xx_PMUXCR_USB_CLK_TIMER3		0x00003000
+#define MPC85xx_PMUXCR_USB_UART_GPIO0		0x00000400
+#define MPC85xx_PMUXCR_USB_RSVD			0x00000C00
+#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN	0x00000800
+#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL	0x00000100
+#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72	0x00000200
+#define MPC85xx_PMUXCR_USB_D1_2_RSVD		0x00000300
+#define MPC85xx_PMUXCR_USB_DIR_GPIO2		0x00000040
+#define MPC85xx_PMUXCR_USB_DIR_TIMER1		0x00000080
+#define MPC85xx_PMUXCR_USB_DIR_MCP_B		0x000000C0
+#define MPC85xx_PMUXCR_SPI1_UART3		0x00000010
+#define MPC85xx_PMUXCR_SPI1_SIM			0x00000020
+#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74	0x00000030
+#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B	0x00000004
+#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen	0x00000008
+#define MPC85xx_PMUXCR_SPI1_CS2_GPO75		0x0000000C
+#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM	0x00000001
+#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen	0x00000002
+#define MPC85xx_PMUXCR_SPI1_CS3_GPO76		0x00000003
+#endif
+#ifdef CONFIG_ARCH_BSC9132
+#define MPC85xx_PMUXCR0_SIM_SEL_MASK	0x0003b000
+#define MPC85xx_PMUXCR0_SIM_SEL		0x00014000
+#endif
+#if defined(CONFIG_ARCH_C29X)
+#define MPC85xx_PMUXCR_SPI_MASK			0x00000300
+#define MPC85xx_PMUXCR_SPI			0x00000000
+#define MPC85xx_PMUXCR_SPI_GPIO			0x00000100
+#endif
+	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
+#if defined(CONFIG_ARCH_P1010)
+#define MPC85xx_PMUXCR2_UART_GPIO		0x40000000
+#define MPC85xx_PMUXCR2_UART_TDM		0x80000000
+#define MPC85xx_PMUXCR2_UART_RES		0xC0000000
+#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN		0x10000000
+#define MPC85xx_PMUXCR2_IRQ2_RES		0x30000000
+#define MPC85xx_PMUXCR2_IRQ3_SRESET		0x04000000
+#define MPC85xx_PMUXCR2_IRQ3_RES		0x0C000000
+#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS		0x01000000
+#define MPC85xx_PMUXCR2_GPIO01_RES		0x03000000
+#define MPC85xx_PMUXCR2_GPIO23_CKSTP		0x00400000
+#define MPC85xx_PMUXCR2_GPIO23_RES		0x00800000
+#define MPC85xx_PMUXCR2_GPIO23_USB		0x00C00000
+#define MPC85xx_PMUXCR2_GPIO4_MCP		0x00100000
+#define MPC85xx_PMUXCR2_GPIO4_RES		0x00200000
+#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT		0x00300000
+#define MPC85xx_PMUXCR2_GPIO5_UDE		0x00040000
+#define MPC85xx_PMUXCR2_GPIO5_RES		0x00080000
+#define MPC85xx_PMUXCR2_READY_ASLEEP		0x00020000
+#define MPC85xx_PMUXCR2_DDR_ECC_MUX		0x00010000
+#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE	0x00008000
+#define MPC85xx_PMUXCR2_POST_EXPOSE		0x00004000
+#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY	0x00002000
+#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE		0x00001000
+#endif
+#if defined(CONFIG_ARCH_P1022)
+#define MPC85xx_PMUXCR2_ETSECUSB_MASK	0x001f8000
+#define MPC85xx_PMUXCR2_USB		0x00150000
+#endif
+#if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
+#if defined(CONFIG_ARCH_BSC9131)
+#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD		0X40000000
+#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS		0X80000000
+#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42		0xC0000000
+#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2		0x10000000
+#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK		0x20000000
+#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43		0x30000000
+#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD		0x04000000
+#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B		0x08000000
+#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44		0x0C000000
+#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED		0x01000000
+#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD		0x02000000
+#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45		0x03000000
+#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP			0x00400000
+#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B		0x00800000
+#define MPC85xx_PMUXCR2_ANT1_TIMER5			0x00100000
+#define MPC85xx_PMUXCR2_ANT1_TSEC_1588			0x00200000
+#define MPC85xx_PMUXCR2_ANT1_GPIO95_19			0x00300000
+#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK	0x00040000
+#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD		0x00080000
+#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20	0x000C0000
+#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0		0x00010000
+#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3		0x00020000
+#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84		0x00030000
+#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4		0x00004000
+#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7		0x00008000
+#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88		0x0000C000
+#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK		0x00001000
+#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9		0x00002000
+#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22		0x00003000
+#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7		0x00000400
+#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11	0x00000800
+#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24		0x00000C00
+#define MPC85xx_PMUXCR2_ANT2_RSVD			0x00000100
+#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA		0x00000300
+#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB		0x00000040
+#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO	0x000000C0
+#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD			0x00000010
+#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8		0x00000020
+#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61		0x00000030
+#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53			0x00000004
+#define MPC85xx_PMUXCR2_ANT3_DO_TDM			0x00000001
+#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49		0x00000002
+#endif
+	u32	pmuxcr3;
+#if defined(CONFIG_ARCH_BSC9131)
+#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM			0x40000000
+#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51		0x80000000
+#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B	0x10000000
+#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53		0x20000000
+#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B			0x04000000
+#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54			0x08000000
+#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT	0x01000000
+#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56		0x02000000
+#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT		0x00400000
+#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57		0x00800000
+#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93			0x00100000
+#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94			0x00040000
+#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD			0x00010000
+#define MPC85xx_PMUXCR3_ANT2_GPO89			0x00030000
+#endif
+#ifdef CONFIG_ARCH_BSC9132
+#define MPC85xx_PMUXCR3_USB_SEL_MASK	0x0000ff00
+#define MPC85xx_PMUXCR3_UART2_SEL	0x00005000
+#define MPC85xx_PMUXCR3_UART3_SEL_MASK	0xc0000000
+#define MPC85xx_PMUXCR3_UART3_SEL	0x40000000
+#endif
+	u32 pmuxcr4;
+#else
+	u8	res6[8];
+#endif
+	u32	devdisr;	/* Device disable control */
+#define MPC85xx_DEVDISR_PCI1		0x80000000
+#define MPC85xx_DEVDISR_PCI2		0x40000000
+#define MPC85xx_DEVDISR_PCIE		0x20000000
+#define MPC85xx_DEVDISR_LBC		0x08000000
+#define MPC85xx_DEVDISR_PCIE2		0x04000000
+#define MPC85xx_DEVDISR_PCIE3		0x02000000
+#define MPC85xx_DEVDISR_SEC		0x01000000
+#define MPC85xx_DEVDISR_SRIO		0x00080000
+#define MPC85xx_DEVDISR_RMSG		0x00040000
+#define MPC85xx_DEVDISR_DDR		0x00010000
+#define MPC85xx_DEVDISR_CPU		0x00008000
+#define MPC85xx_DEVDISR_CPU0		MPC85xx_DEVDISR_CPU
+#define MPC85xx_DEVDISR_TB		0x00004000
+#define MPC85xx_DEVDISR_TB0		MPC85xx_DEVDISR_TB
+#define MPC85xx_DEVDISR_CPU1		0x00002000
+#define MPC85xx_DEVDISR_TB1		0x00001000
+#define MPC85xx_DEVDISR_DMA		0x00000400
+#define MPC85xx_DEVDISR_TSEC1		0x00000080
+#define MPC85xx_DEVDISR_TSEC2		0x00000040
+#define MPC85xx_DEVDISR_TSEC3		0x00000020
+#define MPC85xx_DEVDISR_TSEC4		0x00000010
+#define MPC85xx_DEVDISR_I2C		0x00000004
+#define MPC85xx_DEVDISR_DUART		0x00000002
+	u8	res7[12];
+	u32	powmgtcsr;	/* Power management status & control */
+	u8	res8[12];
+	u32	mcpsumr;	/* Machine check summary */
+	u8	res9[12];
+	u32	pvr;		/* Processor version */
+	u32	svr;		/* System version */
+	u8	res10[8];
+	u32	rstcr;		/* Reset control */
+#if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
+	u8	res11a[76];
+	par_io_t qe_par_io[7];
+	u8	res11b[1600];
+#elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
+	u8      res11a[12];
+	u32     iovselsr;
+	u8      res11b[60];
+	par_io_t qe_par_io[3];
+	u8      res11c[1496];
+#else
+	u8	res11a[1868];
+#endif
+	u32	clkdvdr;	/* Clock Divide register */
+	u8	res12[1532];
+	u32	clkocr;		/* Clock out select */
+	u8	res13[12];
+	u32	ddrdllcr;	/* DDR DLL control */
+	u8	res14[12];
+	u32	lbcdllcr;	/* LBC DLL control */
+#if defined(CONFIG_ARCH_BSC9131)
+	u8	res15[12];
+	u32	halt_req_mask;
+#define HALTED_TO_HALT_REQ_MASK_0	0x80000000
+	u8	res18[232];
+#else
+	u8	res15[248];
+#endif
+	u32	lbiuiplldcr0;	/* LBIU PLL Debug Reg 0 */
+	u32	lbiuiplldcr1;	/* LBIU PLL Debug Reg 1 */
+	u32	ddrioovcr;	/* DDR IO Override Control */
+	u32	tsec12ioovcr;	/* eTSEC 1/2 IO override control */
+	u32	tsec34ioovcr;	/* eTSEC 3/4 IO override control */
+	u8      res16[52];
+	u32	sdhcdcr;	/* SDHC debug control register */
+	u8      res17[61592];
+} ccsr_gur_t;
+#endif
+
+#define SDHCDCR_CD_INV		0x80000000 /* invert SDHC card detect */
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define MAX_SERDES 4
+#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
+#define SRDS_MAX_LANES 4
+#else
+#define SRDS_MAX_LANES 8
+#endif
+#define SRDS_MAX_BANK 2
+typedef struct serdes_corenet {
+	struct {
+		u32	rstctl;	/* Reset Control Register */
+#define SRDS_RSTCTL_RST		0x80000000
+#define SRDS_RSTCTL_RSTDONE	0x40000000
+#define SRDS_RSTCTL_RSTERR	0x20000000
+#define SRDS_RSTCTL_SWRST	0x10000000
+#define SRDS_RSTCTL_SDEN	0x00000020
+#define SRDS_RSTCTL_SDRST_B	0x00000040
+#define SRDS_RSTCTL_PLLRST_B	0x00000080
+#define SRDS_RSTCTL_RSTERR_SHIFT  29
+		u32	pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF		0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_PLL_LCK		0x00800000
+#define SRDS_PLLCR0_DCBIAS_OUT_EN      0x02000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_4_9152	0x00030000
+#define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_125	0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3_0	0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_072	0x000c0000
+#define SRDS_PLLCR0_DCBIAS_OVRD		0x000000F0
+#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT	4
+		u32	pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_BCAP_EN		0x20000000
+#define SRDS_PLLCR1_BCAP_OVD		0x10000000
+#define SRDS_PLLCR1_PLL_FCAP		0x001F8000
+#define SRDS_PLLCR1_PLL_FCAP_SHIFT	15
+#define SRDS_PLLCR1_PLL_BWSEL		0x08000000
+#define SRDS_PLLCR1_BYP_CAL		0x02000000
+		u32	pllsr2;	/* At 0x00c, PLL Status Register 2 */
+#define SRDS_PLLSR2_BCAP_EN		0x00800000
+#define SRDS_PLLSR2_BCAP_EN_SHIFT	23
+#define SRDS_PLLSR2_FCAP		0x003F0000
+#define SRDS_PLLSR2_FCAP_SHIFT		16
+#define SRDS_PLLSR2_DCBIAS		0x000F0000
+#define SRDS_PLLSR2_DCBIAS_SHIFT	16
+		u32	pllcr3;
+		u32	pllcr4;
+		u8	res_18[0x20-0x18];
+	} bank[2];
+	u8	res_40[0x90-0x40];
+	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
+	u8	res_94[0xa0-0x94];
+	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
+	u8	res_a4[0xb0-0xa4];
+	u32	srdsgr0;	/* 0xb0 General Register 0 */
+	u8	res_b4[0xe0-0xb4];
+	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
+	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
+	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
+	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
+	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
+	u8	res_f4[0x100-0xf4];
+	struct {
+		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
+		u8	res_104[0x120-0x104];
+	} srdslnpssr[8];
+	u8	res_200[0x800-0x200];
+	struct {
+		u32	gcr0;	/* 0x800 General Control Register 0 */
+		u32	gcr1;	/* 0x804 General Control Register 1 */
+		u32	gcr2;	/* 0x808 General Control Register 2 */
+		u32	res_80c;
+		u32	recr0;	/* 0x810 Receive Equalization Control */
+		u32	res_814;
+		u32	tecr0;	/* 0x818 Transmit Equalization Control */
+		u32	res_81c;
+		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
+		u8	res_824[0x840-0x824];
+	} lane[8];	/* Lane A, B, C, D, E, F, G, H */
+	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
+} serdes_corenet_t;
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define SRDS_MAX_LANES		18
+#define SRDS_MAX_BANK		3
+typedef struct serdes_corenet {
+	struct {
+		u32	rstctl;	/* Reset Control Register */
+#define SRDS_RSTCTL_RST		0x80000000
+#define SRDS_RSTCTL_RSTDONE	0x40000000
+#define SRDS_RSTCTL_RSTERR	0x20000000
+#define SRDS_RSTCTL_SDPD	0x00000020
+		u32	pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
+#define SRDS_PLLCR0_PVCOCNT_EN		0x02000000
+#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK	0x00030000
+#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_6_25	0x00010000
+		u32	pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL	0x08000000
+		u32	res[5];
+	} bank[3];
+	u32	res1[12];
+	u32	srdstcalcr;	/* TX Calibration Control */
+	u32	res2[3];
+	u32	srdsrcalcr;	/* RX Calibration Control */
+	u32	res3[3];
+	u32	srdsgr0;	/* General Register 0 */
+	u32	res4[11];
+	u32	srdspccr0;	/* Protocol Converter Config 0 */
+	u32	srdspccr1;	/* Protocol Converter Config 1 */
+	u32	srdspccr2;	/* Protocol Converter Config 2 */
+#define SRDS_PCCR2_RST_XGMII1		0x00800000
+#define SRDS_PCCR2_RST_XGMII2		0x00400000
+	u32	res5[197];
+	struct serdes_lane {
+		u32	gcr0;	/* General Control Register 0 */
+#define SRDS_GCR0_RRST			0x00400000
+#define SRDS_GCR0_1STLANE		0x00010000
+#define SRDS_GCR0_UOTHL			0x00100000
+		u32	gcr1;	/* General Control Register 1 */
+#define SRDS_GCR1_REIDL_CTL_MASK	0x001f0000
+#define SRDS_GCR1_REIDL_CTL_PCIE	0x00100000
+#define SRDS_GCR1_REIDL_CTL_SRIO	0x00000000
+#define SRDS_GCR1_REIDL_CTL_SGMII	0x00040000
+#define SRDS_GCR1_OPAD_CTL		0x04000000
+		u32	res1[4];
+		u32	tecr0;	/* TX Equalization Control Reg 0 */
+#define SRDS_TECR0_TEQ_TYPE_MASK	0x30000000
+#define SRDS_TECR0_TEQ_TYPE_2LVL	0x10000000
+		u32	res3;
+		u32	ttlcr0;	/* Transition Tracking Loop Ctrl 0 */
+#define SRDS_TTLCR0_FLT_SEL_MASK	0x3f000000
+#define SRDS_TTLCR0_FLT_SEL_KFR_26	0x10000000
+#define SRDS_TTLCR0_FLT_SEL_KPH_28	0x08000000
+#define SRDS_TTLCR0_FLT_SEL_750PPM	0x03000000
+#define SRDS_TTLCR0_PM_DIS		0x00004000
+#define SRDS_TTLCR0_FREQOVD_EN		0x00000001
+		u32	res4[7];
+	} lane[24];
+	u32 res6[384];
+} serdes_corenet_t;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+enum {
+	FSL_SRDS_B1_LANE_A = 0,
+	FSL_SRDS_B1_LANE_B = 1,
+	FSL_SRDS_B1_LANE_C = 2,
+	FSL_SRDS_B1_LANE_D = 3,
+	FSL_SRDS_B1_LANE_E = 4,
+	FSL_SRDS_B1_LANE_F = 5,
+	FSL_SRDS_B1_LANE_G = 6,
+	FSL_SRDS_B1_LANE_H = 7,
+	FSL_SRDS_B1_LANE_I = 8,
+	FSL_SRDS_B1_LANE_J = 9,
+	FSL_SRDS_B2_LANE_A = 16,
+	FSL_SRDS_B2_LANE_B = 17,
+	FSL_SRDS_B2_LANE_C = 18,
+	FSL_SRDS_B2_LANE_D = 19,
+	FSL_SRDS_B3_LANE_A = 20,
+	FSL_SRDS_B3_LANE_B = 21,
+	FSL_SRDS_B3_LANE_C = 22,
+	FSL_SRDS_B3_LANE_D = 23,
+};
+
+typedef struct ccsr_pme {
+	u8	res0[0x804];
+	u32	liodnbr;	/* LIODN Base Register */
+	u8	res1[0x1f8];
+	u32	srcidr;		/* Source ID Register */
+	u8	res2[8];
+	u32	liodnr;		/* LIODN Register */
+	u8	res3[0x1e8];
+	u32	pm_ip_rev_1;	/* PME IP Block Revision Reg 1*/
+	u32	pm_ip_rev_2;	/* PME IP Block Revision Reg 1*/
+	u8	res4[0x400];
+} ccsr_pme_t;
+
+struct ccsr_pamu {
+	u32 ppbah;
+	u32 ppbal;
+	u32 pplah;
+	u32 pplal;
+	u32 spbah;
+	u32 spbal;
+	u32 splah;
+	u32 splal;
+	u32 obah;
+	u32 obal;
+	u32 olah;
+	u32 olal;
+};
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+struct ccsr_raide {
+	u8	res0[0x543];
+	u32	liodnbr;			/* LIODN Base Register */
+	u8	res1[0xab8];
+	struct {
+		struct {
+			u32	cfg0;		/* cfg register 0 */
+			u32	cfg1;		/* cfg register 1 */
+			u8	res1[0x3f8];
+		} ring[2];
+		u8	res[0x800];
+	} jq[2];
+};
+#endif
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct ccsr_rman {
+	u8	res0[0xf64];
+	u32	mmliodnbr;	/* Message Manager LIODN Base Register */
+	u32	mmitar;		/* RMAN Inbound Translation Address Register */
+	u32	mmitdr;		/* RMAN Inbound Translation Data Register */
+	u8	res4[0x1f090];
+};
+#endif
+
+#ifdef CONFIG_SYS_PMAN
+struct ccsr_pman {
+	u8	res_00[0x40];
+	u32	poes1;		/* PMAN Operation Error Status Register 1 */
+	u32	poes2;		/* PMAN Operation Error Status Register 2 */
+	u32	poeah;		/* PMAN Operation Error Address High */
+	u32	poeal;		/* PMAN Operation Error Address Low */
+	u8	res_50[0x50];
+	u32	pr1;		/* PMAN Revision Register 1 */
+	u32	pr2;		/* PMAN Revision Register 2 */
+	u8	res_a8[0x8];
+	u32	pcap;		/* PMAN Capabilities Register */
+	u8	res_b4[0xc];
+	u32	pc1;		/* PMAN Control Register 1 */
+	u32	pc2;		/* PMAN Control Register 2 */
+	u32	pc3;		/* PMAN Control Register 3 */
+	u32	pc4;		/* PMAN Control Register 4 */
+	u32	pc5;		/* PMAN Control Register 5 */
+	u32	pc6;		/* PMAN Control Register 6 */
+	u8	res_d8[0x8];
+	u32	ppa1;		/* PMAN Prefetch Attributes Register 1 */
+	u32	ppa2;		/* PMAN Prefetch Attributes Register 2 */
+	u8	res_e8[0x8];
+	u32	pics;		/* PMAN Interrupt Control and Status */
+	u8	res_f4[0xf0c];
+};
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
+#ifdef CONFIG_SYS_PMAN
+#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET	0x4000
+#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET	0x5000
+#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET	0x6000
+#endif
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET		0x8000
+#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET		0x9000
+#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET		0xA000
+#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
+#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+/* In SFPv3, OSPR register is now at offset 0x200.
+ *  * So directly mapping sfp register map to this address */
+#define CONFIG_SYS_OSPR_OFFSET                  0x200
+#define CONFIG_SYS_SFP_OFFSET            (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
+#else
+#define CONFIG_SYS_SFP_OFFSET                   0xE8000
+#endif
+#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
+#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
+#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET	0xEC000
+#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET	0xED000
+#define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
+#define CONFIG_SYS_FSL_SCFG_OFFSET		0xFC000
+#define CONFIG_SYS_FSL_PAMU_OFFSET		0x20000
+#define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
+#define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
+#define CONFIG_SYS_MPC85xx_DMA3_OFFSET		0x102000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET		CONFIG_SYS_MPC85xx_DMA1_OFFSET
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x110000
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x124000
+#define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
+#define CONFIG_SYS_MPC85xx_TDM_OFFSET		0x185000
+#define CONFIG_SYS_MPC85xx_QE_OFFSET		0x140000
+#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
+	!defined(CONFIG_ARCH_B4420)
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x260000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x270000
+#else
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x200000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x201000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x202000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x203000
+#endif
+#define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x210000
+#define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x211000
+#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
+#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x220000
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x221000
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x301000
+#define CONFIG_SYS_SEC_MON_OFFSET		0x314000
+#define CONFIG_SYS_FSL_CORENET_PME_OFFSET	0x316000
+#define CONFIG_SYS_FSL_QMAN_OFFSET		0x318000
+#define CONFIG_SYS_FSL_BMAN_OFFSET		0x31a000
+#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET	0x320000
+#define CONFIG_SYS_FSL_FM1_OFFSET		0x400000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x488000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x489000
+#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0x48a000
+#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0x48b000
+#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0x48c000
+#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET	0x48d000
+#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET	0x490000
+#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET	0x491000
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x4e0000
+#define CONFIG_SYS_FSL_FM2_OFFSET		0x500000
+#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET	0x588000
+#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET	0x589000
+#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET	0x58a000
+#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET	0x58b000
+#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET	0x58c000
+#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET	0x58d000
+#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET	0x590000
+#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET	0x591000
+#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET	0xC20000
+#else
+#define CONFIG_SYS_MPC85xx_ECM_OFFSET		0x0000
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET		0x2000
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x5000
+#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET		0x6000
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x7000
+#define CONFIG_SYS_MPC85xx_PCI1_OFFSET		0x8000
+#define CONFIG_SYS_MPC85xx_PCIX_OFFSET		0x8000
+#define CONFIG_SYS_MPC85xx_PCI2_OFFSET		0x9000
+#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET		0x9000
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET         0xa000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET         0x9000
+#if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0x8000
+#else
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0xb000
+#endif
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0xF000
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x18000
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x19000
+#define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x1e000
+#define CONFIG_SYS_MPC85xx_L2_OFFSET		0x20000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x21000
+#define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x22000
+#define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
+#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
+#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
+#ifdef CONFIG_TSECV2
+#define CONFIG_SYS_TSEC1_OFFSET			0xB0000
+#elif defined(CONFIG_TSECV2_1)
+#define CONFIG_SYS_TSEC1_OFFSET			0x10000
+#else
+#define CONFIG_SYS_TSEC1_OFFSET			0x24000
+#endif
+#define CONFIG_SYS_MDIO1_OFFSET			0x24000
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
+#if defined(CONFIG_ARCH_C29X)
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x80000
+#define CONFIG_SYS_FSL_JR0_OFFSET               0x81000
+#else
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
+#define CONFIG_SYS_FSL_JR0_OFFSET               0x31000
+#endif
+#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
+#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
+#define CONFIG_SYS_SEC_MON_OFFSET		0xE6000
+#define CONFIG_SYS_SFP_OFFSET			0xE7000
+#define CONFIG_SYS_MPC85xx_CPM_OFFSET		0x80000
+#define CONFIG_SYS_FSL_QMAN_OFFSET		0x88000
+#define CONFIG_SYS_FSL_BMAN_OFFSET		0x8a000
+#define CONFIG_SYS_FSL_FM1_OFFSET		0x100000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x188000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x189000
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x1e0000
+#endif
+
+#define CONFIG_SYS_MPC85xx_PIC_OFFSET		0x40000
+#define CONFIG_SYS_MPC85xx_GUTS_OFFSET		0xE0000
+#define CONFIG_SYS_FSL_SRIO_OFFSET		0xC0000
+
+#if defined(CONFIG_ARCH_BSC9132)
+#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET	0x10000
+#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
+	(CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
+#endif
+
+#define CONFIG_SYS_FSL_CPC_ADDR	\
+	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_ADDR	\
+	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR	\
+	(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
+	(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
+#define CONFIG_SYS_FSL_QMAN_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
+#define CONFIG_SYS_FSL_BMAN_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
+#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
+#define CONFIG_SYS_MPC85xx_ECM_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
+#define CONFIG_SYS_FSL_DDR_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+#define CONFIG_SYS_FSL_DDR2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+#define CONFIG_SYS_FSL_DDR3_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
+#define CONFIG_SYS_LBC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+#define CONFIG_SYS_IFC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
+#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
+#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
+#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CONFIG_SYS_MPC85xx_GPIO_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
+#define CONFIG_SYS_MPC85xx_SATA1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
+#define CONFIG_SYS_MPC85xx_SATA2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
+#define CONFIG_SYS_MPC85xx_L2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
+#define CONFIG_SYS_MPC85xx_DMA_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
+#define CONFIG_SYS_MPC85xx_CPM_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
+#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
+#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
+#define CONFIG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_FM1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
+#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CONFIG_SYS_FSL_FM2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
+#define CONFIG_SYS_FSL_SRIO_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
+#define CONFIG_SYS_PAMU_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
+
+#define CONFIG_SYS_PCI1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
+#define CONFIG_SYS_PCI2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
+#define CONFIG_SYS_PCIE1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
+#define CONFIG_SYS_PCIE2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
+#define CONFIG_SYS_PCIE3_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
+#define CONFIG_SYS_PCIE4_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
+
+#define CONFIG_SYS_SFP_ADDR  \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+
+#define CONFIG_SYS_SEC_MON_ADDR  \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
+
+#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+struct ccsr_cluster_l2 {
+	u32 l2csr0;	/* 0x000 L2 cache control and status register 0 */
+	u32 l2csr1;	/* 0x004 L2 cache control and status register 1 */
+	u32 l2cfg0;	/* 0x008 L2 cache configuration register 0 */
+	u8  res_0c[500];/* 0x00c - 0x1ff */
+	u32 l2pir0;	/* 0x200 L2 cache partitioning ID register 0 */
+	u8  res_204[4];
+	u32 l2par0;	/* 0x208 L2 cache partitioning allocation register 0 */
+	u32 l2pwr0;	/* 0x20c L2 cache partitioning way register 0 */
+	u32 l2pir1;	/* 0x210 L2 cache partitioning ID register 1 */
+	u8  res_214[4];
+	u32 l2par1;	/* 0x218 L2 cache partitioning allocation register 1 */
+	u32 l2pwr1;	/* 0x21c L2 cache partitioning way register 1 */
+	u32 u2pir2;	/* 0x220 L2 cache partitioning ID register 2 */
+	u8  res_224[4];
+	u32 l2par2;	/* 0x228 L2 cache partitioning allocation register 2 */
+	u32 l2pwr2;	/* 0x22c L2 cache partitioning way register 2 */
+	u32 l2pir3;	/* 0x230 L2 cache partitioning ID register 3 */
+	u8  res_234[4];
+	u32 l2par3;	/* 0x238 L2 cache partitining allocation register 3 */
+	u32 l2pwr3;	/* 0x23c L2 cache partitining way register 3 */
+	u32 l2pir4;	/* 0x240 L2 cache partitioning ID register 3 */
+	u8  res244[4];
+	u32 l2par4;	/* 0x248 L2 cache partitioning allocation register 3 */
+	u32 l2pwr4;	/* 0x24c L2 cache partitioning way register 3 */
+	u32 l2pir5;	/* 0x250 L2 cache partitioning ID register 3 */
+	u8  res_254[4];
+	u32 l2par5;	/* 0x258 L2 cache partitioning allocation register 3 */
+	u32 l2pwr5;	/* 0x25c L2 cache partitioning way register 3 */
+	u32 l2pir6;	/* 0x260 L2 cache partitioning ID register 3 */
+	u8  res_264[4];
+	u32 l2par6;	/* 0x268 L2 cache partitioning allocation register 3 */
+	u32 l2pwr6;	/* 0x26c L2 cache partitioning way register 3 */
+	u32 l2pir7;	/* 0x270 L2 cache partitioning ID register 3 */
+	u8  res274[4];
+	u32 l2par7;	/* 0x278 L2 cache partitioning allocation register 3 */
+	u32 l2pwr7;	/* 0x27c L2 cache partitioning way register 3 */
+	u8  res_280[0xb80]; /* 0x280 - 0xdff */
+	u32 l2errinjhi;	/* 0xe00 L2 cache error injection mask high */
+	u32 l2errinjlo;	/* 0xe04 L2 cache error injection mask low */
+	u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
+	u8  res_e0c[20];	/* 0xe0c - 0x01f */
+	u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
+	u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
+	u32 l2captecc;	/* 0xe28 L2 cache error capture ECC syndrome */
+	u8  res_e2c[20];	/* 0xe2c - 0xe3f */
+	u32 l2errdet;	/* 0xe40 L2 cache error detect */
+	u32 l2errdis;	/* 0xe44 L2 cache error disable */
+	u32 l2errinten;	/* 0xe48 L2 cache error interrupt enable */
+	u32 l2errattr;	/* 0xe4c L2 cache error attribute */
+	u32 l2erreaddr;	/* 0xe50 L2 cache error extended address */
+	u32 l2erraddr;	/* 0xe54 L2 cache error address */
+	u32 l2errctl;	/* 0xe58 L2 cache error control */
+};
+#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define	CONFIG_SYS_DCSR_DCFG_OFFSET	0X20000
+struct dcsr_dcfg_regs {
+	u8  res_0[0x520];
+	u32 ecccr1;
+#define	DCSR_DCFG_ECC_DISABLE_USB1	0x00008000
+#define	DCSR_DCFG_ECC_DISABLE_USB2	0x00004000
+	u8  res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
+};
+
+#define CONFIG_SYS_MPC85xx_SCFG \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
+#define CONFIG_SYS_MPC85xx_SCFG_OFFSET	0xfc000
+/* The supplement configuration unit register */
+struct ccsr_scfg {
+	u32 dpslpcr;	/* 0x000 Deep Sleep Control register */
+	u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
+	u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
+	u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
+	u32 res1[4];
+	u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
+	u32 res2;
+	u32 pixclkcr;	/* 0x028 Pixel Clock Control register */
+	u32 res3[245];
+	u32 qeioclkcr;	/* 0x400 QUICC Engine IO Clock Control register */
+	u32 emiiocr;	/* 0x404 EMI MDIO Control Register */
+	u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
+	u32 qmifrstcr;	/* 0x40c QMAN Interface Reset Control register */
+	u32 res4[60];
+	u32 sparecr[8];	/* 0x500 Spare Control register(0-7) */
+};
+#endif /*__IMMAP_85xx__*/
diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
new file mode 100644
index 0000000..1fbc63a
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -0,0 +1,1221 @@
+/*
+ * MPC86xx Internal Memory Map
+ *
+ * Copyright 2004, 2011 Freescale Semiconductor
+ * Jeff Brown (Jeffrey@freescale.com)
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ */
+
+#ifndef __IMMAP_86xx__
+#define __IMMAP_86xx__
+
+#include <fsl_immap.h>
+#include <asm/types.h>
+#include <asm/fsl_dma.h>
+#include <asm/fsl_lbc.h>
+#include <asm/fsl_i2c.h>
+
+/* Local-Access Registers and MCM Registers(0x0000-0x2000) */
+typedef struct ccsr_local_mcm {
+	uint	ccsrbar;	/* 0x0 - Control Configuration Status Registers Base Address Register */
+	char	res1[4];
+	uint	altcbar;	/* 0x8 - Alternate Configuration Base Address Register */
+	char	res2[4];
+	uint	altcar;		/* 0x10 - Alternate Configuration Attribute Register */
+	char	res3[12];
+	uint	bptr;		/* 0x20 - Boot Page Translation Register */
+	char	res4[3044];
+	uint	lawbar0;	/* 0xc08 - Local Access Window 0 Base Address Register */
+	char	res5[4];
+	uint	lawar0;		/* 0xc10 - Local Access Window 0 Attributes Register */
+	char	res6[20];
+	uint	lawbar1;	/* 0xc28 - Local Access Window 1 Base Address Register */
+	char	res7[4];
+	uint	lawar1;		/* 0xc30 - Local Access Window 1 Attributes Register */
+	char	res8[20];
+	uint	lawbar2;	/* 0xc48 - Local Access Window 2 Base Address Register */
+	char	res9[4];
+	uint	lawar2;		/* 0xc50 - Local Access Window 2 Attributes Register */
+	char	res10[20];
+	uint	lawbar3;	/* 0xc68 - Local Access Window 3 Base Address Register */
+	char	res11[4];
+	uint	lawar3;		/* 0xc70 - Local Access Window 3 Attributes Register */
+	char	res12[20];
+	uint	lawbar4;	/* 0xc88 - Local Access Window 4 Base Address Register */
+	char	res13[4];
+	uint	lawar4;		/* 0xc90 - Local Access Window 4 Attributes Register */
+	char	res14[20];
+	uint	lawbar5;	/* 0xca8 - Local Access Window 5 Base Address Register */
+	char	res15[4];
+	uint	lawar5;		/* 0xcb0 - Local Access Window 5 Attributes Register */
+	char	res16[20];
+	uint	lawbar6;	/* 0xcc8 - Local Access Window 6 Base Address Register */
+	char	res17[4];
+	uint	lawar6;		/* 0xcd0 - Local Access Window 6 Attributes Register */
+	char	res18[20];
+	uint	lawbar7;	/* 0xce8 - Local Access Window 7 Base Address Register */
+	char	res19[4];
+	uint	lawar7;		/* 0xcf0 - Local Access Window 7 Attributes Register */
+	char	res20[20];
+	uint	lawbar8;	/* 0xd08 - Local Access Window 8 Base Address Register */
+	char	res21[4];
+	uint	lawar8;		/* 0xd10 - Local Access Window 8 Attributes Register */
+	char	res22[20];
+	uint	lawbar9;	/* 0xd28 - Local Access Window 9 Base Address Register */
+	char	res23[4];
+	uint	lawar9;		/* 0xd30 - Local Access Window 9 Attributes Register */
+	char	res24[716];
+	uint	abcr;		/* 0x1000 - MCM CCB Address Configuration Register */
+	char	res25[4];
+	uint    dbcr;           /* 0x1008 - MCM MPX data bus Configuration Register */
+	char	res26[4];
+	uint	pcr;		/* 0x1010 - MCM CCB Port Configuration Register */
+	char	res27[44];
+	uint	hpmr0;		/* 0x1040 - MCM HPM Threshold Count Register 0 */
+	uint	hpmr1;		/* 0x1044 - MCM HPM Threshold Count Register 1 */
+	uint	hpmr2;		/* 0x1048 - MCM HPM Threshold Count Register 2 */
+	uint	hpmr3;		/* 0x104c - MCM HPM Threshold Count Register 3 */
+	char	res28[16];
+	uint	hpmr4;		/* 0x1060 - MCM HPM Threshold Count Register 4 */
+	uint	hpmr5;		/* 0x1064 - MCM HPM Threshold Count Register 5 */
+	uint	hpmccr;		/* 0x1068 - MCM HPM Cycle Count Register */
+	char	res29[3476];
+	uint	edr;		/* 0x1e00 - MCM Error Detect Register */
+	char	res30[4];
+	uint	eer;		/* 0x1e08 - MCM Error Enable Register */
+	uint	eatr;		/* 0x1e0c - MCM Error Attributes Capture Register */
+	uint	eladr;		/* 0x1e10 - MCM Error Low Address Capture Register */
+	uint	ehadr;		/* 0x1e14 - MCM Error High Address Capture Register */
+	char	res31[488];
+} ccsr_local_mcm_t;
+
+/* Daul I2C Registers(0x3000-0x4000) */
+typedef struct ccsr_i2c {
+	struct fsl_i2c_base	i2c[2];
+	u8	res[4096 - 2 * sizeof(struct fsl_i2c_base)];
+} ccsr_i2c_t;
+
+/* DUART Registers(0x4000-0x5000) */
+typedef struct ccsr_duart {
+	char	res1[1280];
+	u_char	urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
+	u_char	uier1_udmb1;	/* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
+	u_char	uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
+	u_char	ulcr1;		/* 0x4503 - UART1 Line Control Register */
+	u_char	umcr1;		/* 0x4504 - UART1 Modem Control Register */
+	u_char	ulsr1;		/* 0x4505 - UART1 Line Status Register */
+	u_char	umsr1;		/* 0x4506 - UART1 Modem Status Register */
+	u_char	uscr1;		/* 0x4507 - UART1 Scratch Register */
+	char	res2[8];
+	u_char	udsr1;		/* 0x4510 - UART1 DMA Status Register */
+	char	res3[239];
+	u_char	urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
+	u_char	uier2_udmb2;	/* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
+	u_char	uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
+	u_char	ulcr2;		/* 0x4603 - UART2 Line Control Register */
+	u_char	umcr2;		/* 0x4604 - UART2 Modem Control Register */
+	u_char	ulsr2;		/* 0x4605 - UART2 Line Status Register */
+	u_char	umsr2;		/* 0x4606 - UART2 Modem Status Register */
+	u_char	uscr2;		/* 0x4607 - UART2 Scratch Register */
+	char	res4[8];
+	u_char	udsr2;		/* 0x4610 - UART2 DMA Status Register */
+	char	res5[2543];
+} ccsr_duart_t;
+
+/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
+typedef struct ccsr_pex {
+	uint	cfg_addr;	/* 0x8000 - PEX Configuration Address Register */
+	uint	cfg_data;	/* 0x8004 - PEX Configuration Data Register */
+	char	res1[4];
+	uint	out_comp_to;	/* 0x800C - PEX Outbound Completion Timeout Register */
+	char	res2[16];
+	uint	pme_msg_det;	/* 0x8020 - PEX PME & message detect register */
+	uint    pme_msg_int_en;	/* 0x8024 - PEX PME & message interrupt enable register */
+	uint    pme_msg_dis;	/* 0x8028 - PEX PME & message disable register */
+	uint    pm_command;	/* 0x802c - PEX PM Command register */
+	char	res3[3016];
+	uint    block_rev1;	/* 0x8bf8 - PEX Block Revision register 1 */
+	uint    block_rev2;	/* 0x8bfc - PEX Block Revision register 2 */
+	uint	potar0;	        /* 0x8c00 - PEX Outbound Transaction Address Register 0 */
+	uint	potear0;	/* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */
+	char	res4[8];
+	uint	powar0;	        /* 0x8c10 - PEX Outbound Window Attributes Register 0 */
+	char	res5[12];
+	uint	potar1;	        /* 0x8c20 - PEX Outbound Transaction Address Register 1 */
+	uint	potear1;	/* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */
+	uint	powbar1;	/* 0x8c28 - PEX Outbound Window Base Address Register 1 */
+	char	res6[4];
+	uint	powar1;	        /* 0x8c30 - PEX Outbound Window Attributes Register 1 */
+	char	res7[12];
+	uint	potar2;	        /* 0x8c40 - PEX Outbound Transaction Address Register 2 */
+	uint	potear2;	/* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */
+	uint	powbar2;	/* 0x8c48 - PEX Outbound Window Base Address Register 2 */
+	char	res8[4];
+	uint	powar2;	        /* 0x8c50 - PEX Outbound Window Attributes Register 2 */
+	char	res9[12];
+	uint	potar3;	        /* 0x8c60 - PEX Outbound Transaction Address Register 3 */
+	uint	potear3;	/* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */
+	uint	powbar3;	/* 0x8c68 - PEX Outbound Window Base Address Register 3 */
+	char	res10[4];
+	uint	powar3;	        /* 0x8c70 - PEX Outbound Window Attributes Register 3 */
+	char	res11[12];
+	uint	potar4;	        /* 0x8c80 - PEX Outbound Transaction Address Register 4 */
+	uint	potear4;	/* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */
+	uint	powbar4;	/* 0x8c88 - PEX Outbound Window Base Address Register 4 */
+	char	res12[4];
+	uint	powar4;	        /* 0x8c90 - PEX Outbound Window Attributes Register 4 */
+	char	res13[12];
+	char	res14[256];
+	uint	pitar3;	        /* 0x8da0 - PEX Inbound Translation Address Register 3  */
+	char	res15[4];
+	uint	piwbar3;	/* 0x8da8 - PEX Inbound Window Base Address Register 3 */
+	uint	piwbear3;	/* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */
+	uint	piwar3;	        /* 0x8db0 - PEX Inbound Window Attributes Register 3 */
+	char	res16[12];
+	uint	pitar2;	        /* 0x8dc0 - PEX Inbound Translation Address Register 2  */
+	char	res17[4];
+	uint	piwbar2;	/* 0x8dc8 - PEX Inbound Window Base Address Register 2 */
+	uint	piwbear2;	/* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */
+	uint	piwar2;	        /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */
+	char	res18[12];
+	uint	pitar1;	        /* 0x8de0 - PEX Inbound Translation Address Register 1  */
+	char	res19[4];
+	uint	piwbar1;	/* 0x8de8 - PEX Inbound Window Base Address Register 1 */
+	uint	piwbear1;
+	uint	piwar1;	        /* 0x8df0 - PEX Inbound Window Attributes Register 1 */
+	char	res20[12];
+	uint	pedr;		/* 0x8e00 - PEX Error Detect Register */
+	char    res21[4];
+	uint	peer;		/* 0x8e08 - PEX Error Interrupt Enable Register */
+	char    res22[4];
+	uint	pecdr;		/* 0x8e10 - PEX Error Disable Register */
+	char    res23[12];
+	uint	peer_stat;	/* 0x8e20 - PEX Error Capture Status Register */
+	char    res24[4];
+	uint	perr_cap0;	/* 0x8e28 - PEX Error Capture Register 0 */
+	uint	perr_cap1;	/* 0x8e2c - PEX Error Capture Register 1 */
+	uint	perr_cap2;	/* 0x8e30 - PEX Error Capture Register 2 */
+	uint	perr_cap3;	/* 0x8e34 - PEX Error Capture Register 3 */
+	char	res25[452];
+	char    res26[4];
+} ccsr_pex_t;
+
+/* Hyper Transport Register Block (0xA000-0xB000) */
+typedef struct ccsr_ht {
+	uint    hcfg_addr;      /* 0xa000 - HT Configuration Address register */
+	uint    hcfg_data;      /* 0xa004 - HT Configuration Data register */
+	char	res1[3064];
+	uint    howtar0;        /* 0xac00 - HT Outbound Window 0 Translation register */
+	char	res2[12];
+	uint    howar0;         /* 0xac10 - HT Outbound Window 0 Attributes register */
+	char	res3[12];
+	uint    howtar1;        /* 0xac20 - HT Outbound Window 1 Translation register */
+	char	res4[4];
+	uint    howbar1;        /* 0xac28 - HT Outbound Window 1 Base Address register */
+	char	res5[4];
+	uint    howar1;         /* 0xac30 - HT Outbound Window 1 Attributes register */
+	char	res6[12];
+	uint    howtar2;        /* 0xac40 - HT Outbound Window 2 Translation register */
+	char	res7[4];
+	uint    howbar2;        /* 0xac48 - HT Outbound Window 2 Base Address register */
+	char	res8[4];
+	uint    howar2;         /* 0xac50 - HT Outbound Window 2 Attributes register */
+	char	res9[12];
+	uint    howtar3;        /* 0xac60 - HT Outbound Window 3 Translation register */
+	char	res10[4];
+	uint    howbar3;        /* 0xac68 - HT Outbound Window 3 Base Address register */
+	char	res11[4];
+	uint    howar3;         /* 0xac70 - HT Outbound Window 3 Attributes  register */
+	char	res12[12];
+	uint    howtar4;        /* 0xac80 - HT Outbound Window 4 Translation register */
+	char	res13[4];
+	uint    howbar4;        /* 0xac88 - HT Outbound Window 4 Base Address register */
+	char	res14[4];
+	uint    howar4;         /* 0xac90 - HT Outbound Window 4 Attributes register */
+	char	res15[236];
+	uint    hiwtar4;        /* 0xad80 - HT Inbound Window 4 Translation register */
+	char	res16[4];
+	uint    hiwbar4;        /* 0xad88 - HT Inbound Window 4 Base Address register */
+	char	res17[4];
+	uint    hiwar4;         /* 0xad90 - HT Inbound Window 4 Attributes register */
+	char	res18[12];
+	uint    hiwtar3;        /* 0xada0 - HT Inbound Window 3 Translation register */
+	char	res19[4];
+	uint    hiwbar3;        /* 0xada8 - HT Inbound Window 3 Base Address register */
+	char	res20[4];
+	uint    hiwar3;         /* 0xadb0 - HT Inbound Window 3 Attributes register */
+	char	res21[12];
+	uint    hiwtar2;        /* 0xadc0 - HT Inbound Window 2 Translation register */
+	char	res22[4];
+	uint    hiwbar2;        /* 0xadc8 - HT Inbound Window 2 Base Address register */
+	char	res23[4];
+	uint    hiwar2;         /* 0xadd0 - HT Inbound Window 2 Attributes register */
+	char	res24[12];
+	uint    hiwtar1;        /* 0xade0 - HT Inbound Window 1 Translation register */
+	char	res25[4];
+	uint    hiwbar1;        /* 0xade8 - HT Inbound Window 1 Base Address register */
+	char	res26[4];
+	uint    hiwar1;         /* 0xadf0 - HT Inbound Window 1 Attributes register */
+	char	res27[12];
+	uint    hedr;           /* 0xae00 - HT Error Detect register */
+	char	res28[4];
+	uint    heier;          /* 0xae08 - HT Error Interrupt Enable register */
+	char	res29[4];
+	uint    hecdr;          /* 0xae10 - HT Error Capture Disbale register */
+	char	res30[12];
+	uint    hecsr;          /* 0xae20 - HT Error Capture Status register */
+	char	res31[4];
+	uint    hec0;           /* 0xae28 - HT Error Capture 0 register */
+	uint    hec1;           /* 0xae2c - HT Error Capture 1 register */
+	uint    hec2;           /* 0xae30 - HT Error Capture 2 register */
+	char    res32[460];
+} ccsr_ht_t;
+
+/* DMA Registers(0x2_1000-0x2_2000) */
+typedef struct ccsr_dma {
+	char	res1[256];
+	struct fsl_dma dma[4];
+	uint	dgsr;		/* 0x21300 - DMA General Status Register */
+	char	res2[3324];
+} ccsr_dma_t;
+
+/* tsec1-4: 24000-28000 */
+typedef struct ccsr_tsec {
+	uint    id;		/* 0x24000 - Controller ID Register */
+	char	res1[12];
+	uint	ievent;		/* 0x24010 - Interrupt Event Register */
+	uint	imask;		/* 0x24014 - Interrupt Mask Register */
+	uint	edis;		/* 0x24018 - Error Disabled Register */
+	char	res2[4];
+	uint	ecntrl;		/* 0x24020 - Ethernet Control Register */
+	char    res2_1[4];
+	uint	ptv;		/* 0x24028 - Pause Time Value Register */
+	uint	dmactrl;	/* 0x2402c - DMA Control Register */
+	uint	tbipa;		/* 0x24030 - TBI PHY Address Register */
+	char	res3[88];
+	uint	fifo_tx_thr;	/* 0x2408c - FIFO transmit threshold register */
+	char	res4[8];
+	uint	fifo_tx_starve;	/* 0x24098 - FIFO transmit starve register */
+	uint	fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */
+	char    res4_1[4];
+	uint    fifo_rx_pause;  /* 0x240a4 - FIFO receive pause threshold register */
+	uint    fifo_rx_alarm;  /* 0x240a8 - FIFO receive alarm threshold register */
+	char	res5[84];
+	uint	tctrl;		/* 0x24100 - Transmit Control Register */
+	uint	tstat;		/* 0x24104 - Transmit Status Register */
+	uint    dfvlan;		/* 0x24108 - Default VLAN control word */
+	char    res6[4];
+	uint    txic;		/* 0x24110 - Transmit interrupt coalescing Register */
+	uint    tqueue;         /* 0x24114 - Transmit Queue Control Register */
+	char	res7[40];
+	uint    tr03wt;         /* 0x24140 - TxBD Rings 0-3 round-robin weightings */
+	uint    tw47wt;         /* 0x24144 - TxBD Rings 4-7 round-robin weightings */
+	char    res8[52];
+	uint	tbdbph;	        /* 0x2417c - Transmit Data Buffer Pointer High Register */
+	char    res9[4];
+	uint    tbptr0;         /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */
+	char    res10[4];
+	uint    tbptr1;         /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */
+	char    res11[4];
+	uint    tbptr2;         /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */
+	char    res12[4];
+	uint    tbptr3;         /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */
+	char    res13[4];
+	uint    tbptr4;         /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */
+	char    res14[4];
+	uint    tbptr5;         /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */
+	char    res15[4];
+	uint    tbptr6;         /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */
+	char    res16[4];
+	uint    tbptr7;         /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */
+	char    res17[64];
+	uint	tbaseh;		/* 0x24200 - Transmit Descriptor Base Address High Register */
+	uint	tbase0;		/* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */
+	char    res18[4];
+	uint    tbase1;         /* 0x2420C - Transmit Descriptor base address of Ring 1 */
+	char    res19[4];
+	uint    tbase2;         /* 0x24214 - Transmit Descriptor base address of Ring 2 */
+	char    res20[4];
+	uint    tbase3;         /* 0x2421C - Transmit Descriptor base address of Ring 3 */
+	char    res21[4];
+	uint    tbase4;         /* 0x24224 - Transmit Descriptor base address of Ring 4 */
+	char    res22[4];
+	uint    tbase5;         /* 0x2422C - Transmit Descriptor base address of Ring 5 */
+	char    res23[4];
+	uint    tbase6;         /* 0x24234 - Transmit Descriptor base address of Ring 6 */
+	char    res24[4];
+	uint    tbase7;         /* 0x2423C - Transmit Descriptor base address of Ring 7 */
+	char    res25[192];
+	uint	rctrl;		/* 0x24300 - Receive Control Register */
+	uint	rstat;		/* 0x24304 - Receive Status Register */
+	char	res26[8];
+	uint    rxic;           /* 0x24310 - Receive Interrupt Coalecing Register */
+	uint    rqueue;         /* 0x24314 - Receive queue control register */
+	char	res27[24];
+	uint    rbifx;		/* 0x24330 - Receive bit field extract control Register */
+	uint    rqfar;		/* 0x24334 - Receive queue filing table address Register */
+	uint    rqfcr;		/* 0x24338 - Receive queue filing table control Register */
+	uint    rqfpr;		/* 0x2433c - Receive queue filing table property Register */
+	uint	mrblr;		/* 0x24340 - Maximum Receive Buffer Length Register */
+	char	res28[56];
+	uint    rbdbph;		/* 0x2437C - Receive Data Buffer Pointer High */
+	char    res29[4];
+	uint	rbptr0;		/* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */
+	char    res30[4];
+	uint	rbptr1;		/* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */
+	char    res31[4];
+	uint	rbptr2;		/* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */
+	char    res32[4];
+	uint	rbptr3;		/* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */
+	char    res33[4];
+	uint	rbptr4;		/* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */
+	char    res34[4];
+	uint	rbptr5;		/* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */
+	char    res35[4];
+	uint	rbptr6;		/* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */
+	char    res36[4];
+	uint	rbptr7;		/* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */
+	char    res37[64];
+	uint	rbaseh;		/* 0x24400 - Receive Descriptor Base Address High 0 */
+	uint	rbase0;		/* 0x24404 - Receive Descriptor Base Address of Ring 0 */
+	char    res38[4];
+	uint	rbase1;		/* 0x2440C - Receive Descriptor Base Address of Ring 1 */
+	char    res39[4];
+	uint	rbase2;		/* 0x24414 - Receive Descriptor Base Address of Ring 2 */
+	char    res40[4];
+	uint	rbase3;		/* 0x2441C - Receive Descriptor Base Address of Ring 3 */
+	char    res41[4];
+	uint	rbase4;		/* 0x24424 - Receive Descriptor Base Address of Ring 4 */
+	char    res42[4];
+	uint	rbase5;		/* 0x2442C - Receive Descriptor Base Address of Ring 5 */
+	char    res43[4];
+	uint	rbase6;		/* 0x24434 - Receive Descriptor Base Address of Ring 6 */
+	char    res44[4];
+	uint	rbase7;		/* 0x2443C - Receive Descriptor Base Address of Ring 7 */
+	char    res45[192];
+	uint	maccfg1;	/* 0x24500 - MAC Configuration 1 Register */
+	uint	maccfg2;	/* 0x24504 - MAC Configuration 2 Register */
+	uint	ipgifg;		/* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
+	uint	hafdup;		/* 0x2450c - Half Duplex Register */
+	uint	maxfrm;		/* 0x24510 - Maximum Frame Length Register */
+	char	res46[12];
+	uint	miimcfg;	/* 0x24520 - MII Management Configuration Register */
+	uint	miimcom;	/* 0x24524 - MII Management Command Register */
+	uint	miimadd;	/* 0x24528 - MII Management Address Register */
+	uint	miimcon;	/* 0x2452c - MII Management Control Register */
+	uint	miimstat;	/* 0x24530 - MII Management Status Register */
+	uint	miimind;	/* 0x24534 - MII Management Indicator Register */
+	uint    ifctrl;		/* 0x24538 - Interface Contrl Register */
+	uint	ifstat;		/* 0x2453c - Interface Status Register */
+	uint	macstnaddr1;	/* 0x24540 - Station Address Part 1 Register */
+	uint	macstnaddr2;	/* 0x24544 - Station Address Part 2 Register */
+	uint    mac01addr1;     /* 0x24548 - MAC exact match address 1, part 1 */
+	uint    mac01addr2;     /* 0x2454C - MAC exact match address 1, part 2 */
+	uint    mac02addr1;     /* 0x24550 - MAC exact match address 2, part 1 */
+	uint    mac02addr2;     /* 0x24554 - MAC exact match address 2, part 2 */
+	uint    mac03addr1;     /* 0x24558 - MAC exact match address 3, part 1 */
+	uint    mac03addr2;     /* 0x2455C - MAC exact match address 3, part 2 */
+	uint    mac04addr1;     /* 0x24560 - MAC exact match address 4, part 1 */
+	uint    mac04addr2;     /* 0x24564 - MAC exact match address 4, part 2 */
+	uint    mac05addr1;     /* 0x24568 - MAC exact match address 5, part 1 */
+	uint    mac05addr2;     /* 0x2456C - MAC exact match address 5, part 2 */
+	uint    mac06addr1;     /* 0x24570 - MAC exact match address 6, part 1 */
+	uint    mac06addr2;     /* 0x24574 - MAC exact match address 6, part 2 */
+	uint    mac07addr1;     /* 0x24578 - MAC exact match address 7, part 1 */
+	uint    mac07addr2;     /* 0x2457C - MAC exact match address 7, part 2 */
+	uint    mac08addr1;     /* 0x24580 - MAC exact match address 8, part 1 */
+	uint    mac08addr2;     /* 0x24584 - MAC exact match address 8, part 2 */
+	uint    mac09addr1;     /* 0x24588 - MAC exact match address 9, part 1 */
+	uint    mac09addr2;     /* 0x2458C - MAC exact match address 9, part 2 */
+	uint    mac10addr1;     /* 0x24590 - MAC exact match address 10, part 1 */
+	uint    mac10addr2;     /* 0x24594 - MAC exact match address 10, part 2 */
+	uint    mac11addr1;     /* 0x24598 - MAC exact match address 11, part 1 */
+	uint    mac11addr2;     /* 0x2459C - MAC exact match address 11, part 2 */
+	uint    mac12addr1;     /* 0x245A0 - MAC exact match address 12, part 1 */
+	uint    mac12addr2;     /* 0x245A4 - MAC exact match address 12, part 2 */
+	uint    mac13addr1;     /* 0x245A8 - MAC exact match address 13, part 1 */
+	uint    mac13addr2;     /* 0x245AC - MAC exact match address 13, part 2 */
+	uint    mac14addr1;     /* 0x245B0 - MAC exact match address 14, part 1 */
+	uint    mac14addr2;     /* 0x245B4 - MAC exact match address 14, part 2 */
+	uint    mac15addr1;     /* 0x245B8 - MAC exact match address 15, part 1 */
+	uint    mac15addr2;     /* 0x245BC - MAC exact match address 15, part 2 */
+	char	res48[192];
+	uint	tr64;		/* 0x24680 - Transmit and Receive 64-byte Frame Counter */
+	uint	tr127;		/* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
+	uint	tr255;		/* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
+	uint	tr511;		/* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
+	uint	tr1k;		/* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
+	uint	trmax;		/* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
+	uint	trmgv;		/* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
+	uint	rbyt;		/* 0x2469c - Receive Byte Counter */
+	uint	rpkt;		/* 0x246a0 - Receive Packet Counter */
+	uint	rfcs;		/* 0x246a4 - Receive FCS Error Counter */
+	uint	rmca;		/* 0x246a8 - Receive Multicast Packet Counter */
+	uint	rbca;		/* 0x246ac - Receive Broadcast Packet Counter */
+	uint	rxcf;		/* 0x246b0 - Receive Control Frame Packet Counter */
+	uint	rxpf;		/* 0x246b4 - Receive Pause Frame Packet Counter */
+	uint	rxuo;		/* 0x246b8 - Receive Unknown OP Code Counter */
+	uint	raln;		/* 0x246bc - Receive Alignment Error Counter */
+	uint	rflr;		/* 0x246c0 - Receive Frame Length Error Counter */
+	uint	rcde;		/* 0x246c4 - Receive Code Error Counter */
+	uint	rcse;		/* 0x246c8 - Receive Carrier Sense Error Counter */
+	uint	rund;		/* 0x246cc - Receive Undersize Packet Counter */
+	uint	rovr;		/* 0x246d0 - Receive Oversize Packet Counter */
+	uint	rfrg;		/* 0x246d4 - Receive Fragments Counter */
+	uint	rjbr;		/* 0x246d8 - Receive Jabber Counter */
+	uint	rdrp;		/* 0x246dc - Receive Drop Counter */
+	uint	tbyt;		/* 0x246e0 - Transmit Byte Counter Counter */
+	uint	tpkt;		/* 0x246e4 - Transmit Packet Counter */
+	uint	tmca;		/* 0x246e8 - Transmit Multicast Packet Counter */
+	uint	tbca;		/* 0x246ec - Transmit Broadcast Packet Counter */
+	uint	txpf;		/* 0x246f0 - Transmit Pause Control Frame Counter */
+	uint	tdfr;		/* 0x246f4 - Transmit Deferral Packet Counter */
+	uint	tedf;		/* 0x246f8 - Transmit Excessive Deferral Packet Counter */
+	uint	tscl;		/* 0x246fc - Transmit Single Collision Packet Counter */
+	uint	tmcl;		/* 0x24700 - Transmit Multiple Collision Packet Counter */
+	uint	tlcl;		/* 0x24704 - Transmit Late Collision Packet Counter */
+	uint	txcl;		/* 0x24708 - Transmit Excessive Collision Packet Counter */
+	uint	tncl;		/* 0x2470c - Transmit Total Collision Counter */
+	char	res49[4];
+	uint	tdrp;		/* 0x24714 - Transmit Drop Frame Counter */
+	uint	tjbr;		/* 0x24718 - Transmit Jabber Frame Counter */
+	uint	tfcs;		/* 0x2471c - Transmit FCS Error Counter */
+	uint	txcf;		/* 0x24720 - Transmit Control Frame Counter */
+	uint	tovr;		/* 0x24724 - Transmit Oversize Frame Counter */
+	uint	tund;		/* 0x24728 - Transmit Undersize Frame Counter */
+	uint	tfrg;		/* 0x2472c - Transmit Fragments Frame Counter */
+	uint	car1;		/* 0x24730 - Carry Register One */
+	uint	car2;		/* 0x24734 - Carry Register Two */
+	uint	cam1;		/* 0x24738 - Carry Mask Register One */
+	uint	cam2;		/* 0x2473c - Carry Mask Register Two */
+	uint    rrej;	        /* 0x24740 - Receive filer rejected packet counter */
+	char	res50[188];
+	uint	iaddr0;		/* 0x24800 - Indivdual address register 0 */
+	uint	iaddr1;		/* 0x24804 - Indivdual address register 1 */
+	uint	iaddr2;		/* 0x24808 - Indivdual address register 2 */
+	uint	iaddr3;		/* 0x2480c - Indivdual address register 3 */
+	uint	iaddr4;		/* 0x24810 - Indivdual address register 4 */
+	uint	iaddr5;		/* 0x24814 - Indivdual address register 5 */
+	uint	iaddr6;		/* 0x24818 - Indivdual address register 6 */
+	uint	iaddr7;		/* 0x2481c - Indivdual address register 7 */
+	char	res51[96];
+	uint	gaddr0;		/* 0x24880 - Global address register 0 */
+	uint	gaddr1;		/* 0x24884 - Global address register 1 */
+	uint	gaddr2;		/* 0x24888 - Global address register 2 */
+	uint	gaddr3;		/* 0x2488c - Global address register 3 */
+	uint	gaddr4;		/* 0x24890 - Global address register 4 */
+	uint	gaddr5;		/* 0x24894 - Global address register 5 */
+	uint	gaddr6;		/* 0x24898 - Global address register 6 */
+	uint	gaddr7;		/* 0x2489c - Global address register 7 */
+	char	res52[352];
+	uint    fifocfg;        /* 0x24A00 - FIFO interface configuration register */
+	char    res53[500];
+	uint    attr;           /* 0x24BF8 - DMA Attribute register */
+	uint    attreli;        /* 0x24BFC - DMA Attribute extract length and index register */
+	char    res54[1024];
+} ccsr_tsec_t;
+
+/* PIC Registers(0x4_0000-0x6_1000) */
+
+typedef struct ccsr_pic {
+	char	res1[64];
+	uint	ipidr0;		/* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
+	char	res2[12];
+	uint	ipidr1;		/* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
+	char	res3[12];
+	uint	ipidr2;		/* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
+	char	res4[12];
+	uint	ipidr3;		/* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
+	char	res5[12];
+	uint	ctpr;		/* 0x40080 - Current Task Priority Register */
+	char	res6[12];
+	uint	whoami;		/* 0x40090 - Who Am I Register */
+	char	res7[12];
+	uint	iack;		/* 0x400a0 - Interrupt Acknowledge Register */
+	char	res8[12];
+	uint	eoi;		/* 0x400b0 - End Of Interrupt Register */
+	char	res9[3916];
+	uint	frr;		/* 0x41000 - Feature Reporting Register */
+	char	res10[28];
+	uint	gcr;		/* 0x41020 - Global Configuration Register */
+#define MPC86xx_PICGCR_RST	0x80000000
+#define MPC86xx_PICGCR_MODE	0x20000000
+	char	res11[92];
+	uint	vir;		/* 0x41080 - Vendor Identification Register */
+	char	res12[12];
+	uint	pir;		/* 0x41090 - Processor Initialization Register */
+	char	res13[12];
+	uint	ipivpr0;	/* 0x410a0 - IPI Vector/Priority Register 0 */
+	char	res14[12];
+	uint	ipivpr1;	/* 0x410b0 - IPI Vector/Priority Register 1 */
+	char	res15[12];
+	uint	ipivpr2;	/* 0x410c0 - IPI Vector/Priority Register 2 */
+	char	res16[12];
+	uint	ipivpr3;	/* 0x410d0 - IPI Vector/Priority Register 3 */
+	char	res17[12];
+	uint	svr;		/* 0x410e0 - Spurious Vector Register */
+	char	res18[12];
+	uint	tfrr;		/* 0x410f0 - Timer Frequency Reporting Register */
+	char	res19[12];
+	uint	gtccr0;		/* 0x41100 - Global Timer Current Count Register 0 */
+	char	res20[12];
+	uint	gtbcr0;		/* 0x41110 - Global Timer Base Count Register 0 */
+	char	res21[12];
+	uint	gtvpr0;		/* 0x41120 - Global Timer Vector/Priority Register 0 */
+	char	res22[12];
+	uint	gtdr0;		/* 0x41130 - Global Timer Destination Register 0 */
+	char	res23[12];
+	uint	gtccr1;		/* 0x41140 - Global Timer Current Count Register 1 */
+	char	res24[12];
+	uint	gtbcr1;		/* 0x41150 - Global Timer Base Count Register 1 */
+	char	res25[12];
+	uint	gtvpr1;		/* 0x41160 - Global Timer Vector/Priority Register 1 */
+	char	res26[12];
+	uint	gtdr1;		/* 0x41170 - Global Timer Destination Register 1 */
+	char	res27[12];
+	uint	gtccr2;		/* 0x41180 - Global Timer Current Count Register 2 */
+	char	res28[12];
+	uint	gtbcr2;		/* 0x41190 - Global Timer Base Count Register 2 */
+	char	res29[12];
+	uint	gtvpr2;		/* 0x411a0 - Global Timer Vector/Priority Register 2 */
+	char	res30[12];
+	uint	gtdr2;		/* 0x411b0 - Global Timer Destination Register 2 */
+	char	res31[12];
+	uint	gtccr3;		/* 0x411c0 - Global Timer Current Count Register 3 */
+	char	res32[12];
+	uint	gtbcr3;		/* 0x411d0 - Global Timer Base Count Register 3 */
+	char	res33[12];
+	uint	gtvpr3;		/* 0x411e0 - Global Timer Vector/Priority Register 3 */
+	char	res34[12];
+	uint	gtdr3;		/* 0x411f0 - Global Timer Destination Register 3 */
+	char	res35[268];
+	uint	tcr;		/* 0x41300 - Timer Control Register */
+	char	res36[12];
+	uint	irqsr0;		/* 0x41310 - IRQ_OUT Summary Register 0 */
+	char	res37[12];
+	uint	irqsr1;		/* 0x41320 - IRQ_OUT Summary Register 1 */
+	char	res38[12];
+	uint	cisr0;		/* 0x41330 - Critical Interrupt Summary Register 0 */
+	char	res39[12];
+	uint	cisr1;		/* 0x41340 - Critical Interrupt Summary Register 1 */
+	char	res40[12];
+	uint	pm0mr0;		/* 0x41350 - Performance monitor 0 mask register 0  */
+	char	res41[12];
+	uint	pm0mr1;		/* 0x41360 - Performance monitor 0 mask register 1  */
+	char	res42[12];
+	uint	pm1mr0;		/* 0x41370 - Performance monitor 1 mask register 0  */
+	char	res43[12];
+	uint	pm1mr1;		/* 0x41380 - Performance monitor 1 mask register 1  */
+	char	res44[12];
+	uint	pm2mr0;		/* 0x41390 - Performance monitor 2 mask register 0  */
+	char	res45[12];
+	uint	pm2mr1;		/* 0x413A0 - Performance monitor 2 mask register 1  */
+	char	res46[12];
+	uint	pm3mr0;		/* 0x413B0 - Performance monitor 3 mask register 0  */
+	char	res47[12];
+	uint	pm3mr1;		/* 0x413C0 - Performance monitor 3 mask register 1  */
+	char	res48[60];
+	uint	msgr0;		/* 0x41400 - Message Register 0 */
+	char	res49[12];
+	uint	msgr1;		/* 0x41410 - Message Register 1 */
+	char	res50[12];
+	uint	msgr2;		/* 0x41420 - Message Register 2 */
+	char	res51[12];
+	uint	msgr3;		/* 0x41430 - Message Register 3 */
+	char	res52[204];
+	uint	mer;		/* 0x41500 - Message Enable Register */
+	char	res53[12];
+	uint	msr;		/* 0x41510 - Message Status Register */
+	char	res54[60140];
+	uint	eivpr0;		/* 0x50000 - External Interrupt Vector/Priority Register 0 */
+	char	res55[12];
+	uint	eidr0;		/* 0x50010 - External Interrupt Destination Register 0 */
+	char	res56[12];
+	uint	eivpr1;		/* 0x50020 - External Interrupt Vector/Priority Register 1 */
+	char	res57[12];
+	uint	eidr1;		/* 0x50030 - External Interrupt Destination Register 1 */
+	char	res58[12];
+	uint	eivpr2;		/* 0x50040 - External Interrupt Vector/Priority Register 2 */
+	char	res59[12];
+	uint	eidr2;		/* 0x50050 - External Interrupt Destination Register 2 */
+	char	res60[12];
+	uint	eivpr3;		/* 0x50060 - External Interrupt Vector/Priority Register 3 */
+	char	res61[12];
+	uint	eidr3;		/* 0x50070 - External Interrupt Destination Register 3 */
+	char	res62[12];
+	uint	eivpr4;		/* 0x50080 - External Interrupt Vector/Priority Register 4 */
+	char	res63[12];
+	uint	eidr4;		/* 0x50090 - External Interrupt Destination Register 4 */
+	char	res64[12];
+	uint	eivpr5;		/* 0x500a0 - External Interrupt Vector/Priority Register 5 */
+	char	res65[12];
+	uint	eidr5;		/* 0x500b0 - External Interrupt Destination Register 5 */
+	char	res66[12];
+	uint	eivpr6;		/* 0x500c0 - External Interrupt Vector/Priority Register 6 */
+	char	res67[12];
+	uint	eidr6;		/* 0x500d0 - External Interrupt Destination Register 6 */
+	char	res68[12];
+	uint	eivpr7;		/* 0x500e0 - External Interrupt Vector/Priority Register 7 */
+	char	res69[12];
+	uint	eidr7;		/* 0x500f0 - External Interrupt Destination Register 7 */
+	char	res70[12];
+	uint	eivpr8;		/* 0x50100 - External Interrupt Vector/Priority Register 8 */
+	char	res71[12];
+	uint	eidr8;		/* 0x50110 - External Interrupt Destination Register 8 */
+	char	res72[12];
+	uint	eivpr9;		/* 0x50120 - External Interrupt Vector/Priority Register 9 */
+	char	res73[12];
+	uint	eidr9;		/* 0x50130 - External Interrupt Destination Register 9 */
+	char	res74[12];
+	uint	eivpr10;	/* 0x50140 - External Interrupt Vector/Priority Register 10 */
+	char	res75[12];
+	uint	eidr10;		/* 0x50150 - External Interrupt Destination Register 10 */
+	char	res76[12];
+	uint	eivpr11;	/* 0x50160 - External Interrupt Vector/Priority Register 11 */
+	char	res77[12];
+	uint	eidr11;		/* 0x50170 - External Interrupt Destination Register 11 */
+	char	res78[140];
+	uint	iivpr0;		/* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
+	char	res79[12];
+	uint	iidr0;		/* 0x50210 - Internal Interrupt Destination Register 0 */
+	char	res80[12];
+	uint	iivpr1;		/* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
+	char	res81[12];
+	uint	iidr1;		/* 0x50230 - Internal Interrupt Destination Register 1 */
+	char	res82[12];
+	uint	iivpr2;		/* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
+	char	res83[12];
+	uint	iidr2;		/* 0x50250 - Internal Interrupt Destination Register 2 */
+	char	res84[12];
+	uint	iivpr3;		/* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
+	char	res85[12];
+	uint	iidr3;		/* 0x50270 - Internal Interrupt Destination Register 3 */
+	char	res86[12];
+	uint	iivpr4;		/* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
+	char	res87[12];
+	uint	iidr4;		/* 0x50290 - Internal Interrupt Destination Register 4 */
+	char	res88[12];
+	uint	iivpr5;		/* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
+	char	res89[12];
+	uint	iidr5;		/* 0x502b0 - Internal Interrupt Destination Register 5 */
+	char	res90[12];
+	uint	iivpr6;		/* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
+	char	res91[12];
+	uint	iidr6;		/* 0x502d0 - Internal Interrupt Destination Register 6 */
+	char	res92[12];
+	uint	iivpr7;		/* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
+	char	res93[12];
+	uint	iidr7;		/* 0x502f0 - Internal Interrupt Destination Register 7 */
+	char	res94[12];
+	uint	iivpr8;		/* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
+	char	res95[12];
+	uint	iidr8;		/* 0x50310 - Internal Interrupt Destination Register 8 */
+	char	res96[12];
+	uint	iivpr9;		/* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
+	char	res97[12];
+	uint	iidr9;		/* 0x50330 - Internal Interrupt Destination Register 9 */
+	char	res98[12];
+	uint	iivpr10;	/* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
+	char	res99[12];
+	uint	iidr10;		/* 0x50350 - Internal Interrupt Destination Register 10 */
+	char	res100[12];
+	uint	iivpr11;	/* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
+	char	res101[12];
+	uint	iidr11;		/* 0x50370 - Internal Interrupt Destination Register 11 */
+	char	res102[12];
+	uint	iivpr12;	/* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
+	char	res103[12];
+	uint	iidr12;		/* 0x50390 - Internal Interrupt Destination Register 12 */
+	char	res104[12];
+	uint	iivpr13;	/* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
+	char	res105[12];
+	uint	iidr13;		/* 0x503b0 - Internal Interrupt Destination Register 13 */
+	char	res106[12];
+	uint	iivpr14;	/* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
+	char	res107[12];
+	uint	iidr14;		/* 0x503d0 - Internal Interrupt Destination Register 14 */
+	char	res108[12];
+	uint	iivpr15;	/* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
+	char	res109[12];
+	uint	iidr15;		/* 0x503f0 - Internal Interrupt Destination Register 15 */
+	char	res110[12];
+	uint	iivpr16;	/* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
+	char	res111[12];
+	uint	iidr16;		/* 0x50410 - Internal Interrupt Destination Register 16 */
+	char	res112[12];
+	uint	iivpr17;	/* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
+	char	res113[12];
+	uint	iidr17;		/* 0x50430 - Internal Interrupt Destination Register 17 */
+	char	res114[12];
+	uint	iivpr18;	/* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
+	char	res115[12];
+	uint	iidr18;		/* 0x50450 - Internal Interrupt Destination Register 18 */
+	char	res116[12];
+	uint	iivpr19;	/* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
+	char	res117[12];
+	uint	iidr19;		/* 0x50470 - Internal Interrupt Destination Register 19 */
+	char	res118[12];
+	uint	iivpr20;	/* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
+	char	res119[12];
+	uint	iidr20;		/* 0x50490 - Internal Interrupt Destination Register 20 */
+	char	res120[12];
+	uint	iivpr21;	/* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
+	char	res121[12];
+	uint	iidr21;		/* 0x504b0 - Internal Interrupt Destination Register 21 */
+	char	res122[12];
+	uint	iivpr22;	/* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
+	char	res123[12];
+	uint	iidr22;		/* 0x504d0 - Internal Interrupt Destination Register 22 */
+	char	res124[12];
+	uint	iivpr23;	/* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
+	char	res125[12];
+	uint	iidr23;		/* 0x504f0 - Internal Interrupt Destination Register 23 */
+	char	res126[12];
+	uint	iivpr24;	/* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
+	char	res127[12];
+	uint	iidr24;		/* 0x50510 - Internal Interrupt Destination Register 24 */
+	char	res128[12];
+	uint	iivpr25;	/* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
+	char	res129[12];
+	uint	iidr25;		/* 0x50530 - Internal Interrupt Destination Register 25 */
+	char	res130[12];
+	uint	iivpr26;	/* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
+	char	res131[12];
+	uint	iidr26;		/* 0x50550 - Internal Interrupt Destination Register 26 */
+	char	res132[12];
+	uint	iivpr27;	/* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
+	char	res133[12];
+	uint	iidr27;		/* 0x50570 - Internal Interrupt Destination Register 27 */
+	char	res134[12];
+	uint	iivpr28;	/* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
+	char	res135[12];
+	uint	iidr28;		/* 0x50590 - Internal Interrupt Destination Register 28 */
+	char	res136[12];
+	uint	iivpr29;	/* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
+	char	res137[12];
+	uint	iidr29;		/* 0x505b0 - Internal Interrupt Destination Register 29 */
+	char	res138[12];
+	uint	iivpr30;	/* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
+	char	res139[12];
+	uint	iidr30;		/* 0x505d0 - Internal Interrupt Destination Register 30 */
+	char	res140[12];
+	uint	iivpr31;	/* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
+	char	res141[12];
+	uint	iidr31;		/* 0x505f0 - Internal Interrupt Destination Register 31 */
+	char	res142[4108];
+	uint	mivpr0;		/* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
+	char	res143[12];
+	uint	midr0;		/* 0x51610 - Messaging Interrupt Destination Register 0 */
+	char	res144[12];
+	uint	mivpr1;		/* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
+	char	res145[12];
+	uint	midr1;		/* 0x51630 - Messaging Interrupt Destination Register 1 */
+	char	res146[12];
+	uint	mivpr2;		/* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
+	char	res147[12];
+	uint	midr2;		/* 0x51650 - Messaging Interrupt Destination Register 2 */
+	char	res148[12];
+	uint	mivpr3;		/* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
+	char	res149[12];
+	uint	midr3;		/* 0x51670 - Messaging Interrupt Destination Register 3 */
+	char	res150[59852];
+	uint	ipi0dr0;	/* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
+	char	res151[12];
+	uint	ipi0dr1;	/* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
+	char	res152[12];
+	uint	ipi0dr2;	/* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
+	char	res153[12];
+	uint	ipi0dr3;	/* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
+	char	res154[12];
+	uint	ctpr0;		/* 0x60080 - Current Task Priority Register for Processor 0 */
+	char	res155[12];
+	uint	whoami0;	/* 0x60090 - Who Am I Register for Processor 0 */
+	char	res156[12];
+	uint	iack0;		/* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
+	char	res157[12];
+	uint	eoi0;		/* 0x600b0 - End Of Interrupt Register for Processor 0 */
+	char	res158[3916];
+} ccsr_pic_t;
+
+/* RapidIO Registers(0xc_0000-0xe_0000) */
+
+typedef struct ccsr_rio {
+	uint	didcar;		/* 0xc0000 - Device Identity Capability Register */
+	uint	dicar;		/* 0xc0004 - Device Information Capability Register */
+	uint	aidcar;		/* 0xc0008 - Assembly Identity Capability Register */
+	uint	aicar;		/* 0xc000c - Assembly Information Capability Register */
+	uint	pefcar;		/* 0xc0010 - Processing Element Features Capability Register */
+	uint	spicar;		/* 0xc0014 - Switch Port Information Capability Register */
+	uint	socar;		/* 0xc0018 - Source Operations Capability Register */
+	uint	docar;		/* 0xc001c - Destination Operations Capability Register */
+	char	res1[32];
+	uint	msr;		/* 0xc0040 - Mailbox Command And Status Register */
+	uint	pwdcsr;		/* 0xc0044 - Port-Write and Doorbell Command And Status Register */
+	char	res2[4];
+	uint	pellccsr;	/* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
+	char	res3[12];
+	uint	lcsbacsr;	/* 0xc005c - Local Configuration Space Base Address Command and Status Register */
+	uint	bdidcsr;	/* 0xc0060 - Base Device ID Command and Status Register */
+	char	res4[4];
+	uint	hbdidlcsr;	/* 0xc0068 - Host Base Device ID Lock Command and Status Register */
+	uint	ctcsr;		/* 0xc006c - Component Tag Command and Status Register */
+	char	res5[144];
+	uint	pmbh0csr;	/* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
+	char	res6[28];
+	uint	pltoccsr;	/* 0xc0120 - Port Link Time-out Control Command and Status Register */
+	uint	prtoccsr;	/* 0xc0124 - Port Response Time-out Control Command and Status Register */
+	char	res7[20];
+	uint	pgccsr;		/* 0xc013c - Port General Command and Status Register */
+	uint	plmreqcsr;	/* 0xc0140 - Port Link Maintenance Request Command and Status Register */
+	uint	plmrespcsr;	/* 0xc0144 - Port Link Maintenance Response Command and Status Register */
+	uint	plascsr;	/* 0xc0148 - Port Local Ackid Status Command and Status Register */
+	char	res8[12];
+	uint	pescsr;		/* 0xc0158 - Port Error and Status Command and Status Register */
+	uint	pccsr;		/* 0xc015c - Port Control Command and Status Register */
+	char	res9[1184];
+	uint	erbh;		/* 0xc0600 - Error Reporting Block Header Register */
+	char	res10[4];
+	uint	ltledcsr;	/* 0xc0608 - Logical/Transport layer error detect status register */
+	uint	ltleecsr;	/* 0xc060c - Logical/Transport layer error enable register */
+	char	res11[4];
+	uint	ltlaccsr;	/* 0xc0614 - Logical/Transport layer addresss capture register */
+	uint	ltldidccsr;	/* 0xc0618 - Logical/Transport layer device ID capture register */
+	uint	ltlcccsr;	/* 0xc061c - Logical/Transport layer control capture register */
+	char	res12[32];
+	uint	edcsr;	        /* 0xc0640 - Port 0 error detect status register */
+	uint	erecsr;	        /* 0xc0644 - Port 0 error rate enable status register */
+	uint	ecacsr;	        /* 0xc0648 - Port 0 error capture attributes register */
+	uint	pcseccsr0;	/* 0xc064c - Port 0 packet/control symbol error capture register 0 */
+	uint	peccsr1;	/* 0xc0650 - Port 0 error capture command and status register 1 */
+	uint	peccsr2;	/* 0xc0654 - Port 0 error capture command and status register 2 */
+	uint	peccsr3;	/* 0xc0658 - Port 0 error capture command and status register 3 */
+	char	res13[12];
+	uint	ercsr;	        /* 0xc0668 - Port 0 error rate command and status register */
+	uint	ertcsr;	        /* 0xc066C - Port 0 error rate threshold status register*/
+	char	res14[63892];
+	uint	llcr;		/* 0xd0004 - Logical Layer Configuration Register */
+	char	res15[12];
+	uint	epwisr;		/* 0xd0010 - Error / Port-Write Interrupt Status Register */
+	char	res16[12];
+	uint	lretcr;		/* 0xd0020 - Logical Retry Error Threshold Configuration Register */
+	char	res17[92];
+	uint	pretcr;		/* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */
+	char	res18[124];
+	uint	adidcsr;	/* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */
+	char	res19[28];
+	uint	ptaacr;	        /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */
+	char	res20[12];
+	uint	iecsr;	        /* 0xd0130 - Port 0 Implementation Error Status Register */
+	char	res21[12];
+	uint	pcr;		/* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */
+	char	res22[20];
+	uint	slcsr;	        /* 0xd0158 - Port 0 Serial Link Command and Status Register */
+	char	res23[4];
+	uint	sleir;	        /* 0xd0160 - Port 0 Serial Link Error Injection Register */
+	char	res24[2716];
+	uint	rowtar0;	/* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
+	uint	rowtear0;	/* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */
+	char	res25[8];
+	uint	rowar0;		/* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
+	char	res26[12];
+	uint	rowtar1;	/* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
+	uint	rowtear1;	/* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */
+	uint	rowbar1;	/* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
+	char	res27[4];
+	uint	rowar1;		/* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
+	uint	rows1r1;	/* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */
+	uint	rows2r1;	/* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */
+	uint	rows3r1;	/* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */
+	uint	rowtar2;	/* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
+	uint	rowtear2;	/* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */
+	uint	rowbar2;	/* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
+	char	res28[4];
+	uint	rowar2;		/* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
+	uint	rows1r2;	/* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */
+	uint	rows2r2;	/* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */
+	uint	rows3r2;	/* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */
+	uint	rowtar3;	/* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
+	uint	rowtear3;	/* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */
+	uint	rowbar3;	/* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
+	char	res29[4];
+	uint	rowar3;		/* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
+	uint	rows1r3;	/* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */
+	uint	rows2r3;	/* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */
+	uint	rows3r3;	/* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */
+	uint	rowtar4;	/* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
+	uint	rowtear4;	/* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */
+	uint	rowbar4;	/* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
+	char	res30[4];
+	uint	rowar4;		/* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
+	uint	rows1r4;	/* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */
+	uint	rows2r4;	/* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */
+	uint	rows3r4;	/* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */
+	uint	rowtar5;	/* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
+	uint	rowtear5;	/* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */
+	uint	rowbar5;	/* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
+	char	res31[4];
+	uint	rowar5;		/* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
+	uint	rows1r5;	/* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */
+	uint	rows2r5;	/* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */
+	uint	rows3r5;	/* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */
+	uint	rowtar6;	/* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
+	uint	rowtear6;	/* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */
+	uint	rowbar6;	/* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
+	char	res32[4];
+	uint	rowar6;		/* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
+	uint	rows1r6;	/* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */
+	uint	rows2r6;	/* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */
+	uint	rows3r6;	/* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */
+	uint	rowtar7;	/* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
+	uint	rowtear7;	/* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */
+	uint	rowbar7;	/* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
+	char	res33[4];
+	uint	rowar7;		/* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
+	uint	rows1r7;	/* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */
+	uint	rows2r7;	/* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */
+	uint	rows3r7;	/* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */
+	uint	rowtar8;	/* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
+	uint	rowtear8;	/* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */
+	uint	rowbar8;	/* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
+	char	res34[4];
+	uint	rowar8;		/* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
+	uint	rows1r8;	/* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */
+	uint	rows2r8;	/* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */
+	uint	rows3r8;	/* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */
+	char	res35[64];
+	uint	riwtar4;	/* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
+	uint	riwbar4;	/* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
+	char	res36[4];
+	uint	riwar4;		/* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
+	char	res37[12];
+	uint	riwtar3;	/* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
+	char	res38[4];
+	uint	riwbar3;	/* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
+	char	res39[4];
+	uint	riwar3;		/* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
+	char	res40[12];
+	uint	riwtar2;	/* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
+	char	res41[4];
+	uint	riwbar2;	/* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
+	char	res42[4];
+	uint	riwar2;		/* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
+	char	res43[12];
+	uint	riwtar1;	/* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
+	char	res44[4];
+	uint	riwbar1;	/* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
+	char	res45[4];
+	uint	riwar1;		/* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
+	char	res46[12];
+	uint	riwtar0;	/* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
+	char	res47[12];
+	uint	riwar0;		/* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
+	char	res48[12];
+	uint	pnfedr;		/* 0xd0e00 - Port Notification/Fatal Error Detect Register */
+	uint	pnfedir;	/* 0xd0e04 - Port Notification/Fatal Error Detect Register */
+	uint	pnfeier;	/* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
+	uint	pecr;		/* 0xd0e0c - Port Error Control Register */
+	uint	pepcsr0;	/* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
+	uint	pepr1;		/* 0xd0e14 - Port Error Packet Register 1 */
+	uint	pepr2;		/* 0xd0e18 - Port Error Packet Register 2 */
+	char	res49[4];
+	uint	predr;		/* 0xd0e20 - Port Recoverable Error Detect Register */
+	char	res50[4];
+	uint	pertr;		/* 0xd0e28 - Port Error Recovery Threshold Register */
+	uint	prtr;		/* 0xd0e2c - Port Retry Threshold Register */
+	char	res51[8656];
+	uint	omr;		/* 0xd3000 - Outbound Mode Register */
+	uint	osr;		/* 0xd3004 - Outbound Status Register */
+	uint	eodqtpar;	/* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
+	uint	odqtpar;	/* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */
+	uint	eosar;		/* 0xd3010 - Extended Outbound Unit Source Address Register */
+	uint	osar;		/* 0xd3014 - Outbound Unit Source Address Register */
+	uint	odpr;		/* 0xd3018 - Outbound Destination Port Register */
+	uint	odatr;		/* 0xd301c - Outbound Destination Attributes Register */
+	uint	odcr;		/* 0xd3020 - Outbound Doubleword Count Register */
+	uint	eodqhpar;	/* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
+	uint	odqhpar;	/* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */
+	uint	oretr;	        /* 0xd302C - Outbound Retry Error Threshold Register */
+	uint	omgr;	        /* 0xd3030 - Outbound Multicast Group Register */
+	uint	omlr;	        /* 0xd3034 - Outbound Multicast List Register */
+	char	res52[40];
+	uint	imr;		/* 0xd3060 - Outbound Mode Register */
+	uint	isr;		/* 0xd3064 - Inbound Status Register */
+	uint	eidqtpar;	/* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
+	uint	idqtpar;	/* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */
+	uint	eifqhpar;	/* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */
+	uint	ifqhpar;	/* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */
+	uint	imirir;	        /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */
+	char	res53[900];
+	uint	oddmr;		/* 0xd3400 - Outbound Doorbell Mode Register */
+	uint	oddsr;		/* 0xd3404 - Outbound Doorbell Status Register */
+	char	res54[16];
+	uint	oddpr;		/* 0xd3418 - Outbound Doorbell Destination Port Register */
+	uint	oddatr;		/* 0xd341C - Outbound Doorbell Destination Attributes Register */
+	char	res55[12];
+	uint	oddretr;	/* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */
+	char	res56[48];
+	uint	idmr;		/* 0xd3460 - Inbound Doorbell Mode Register */
+	uint	idsr;		/* 0xd3464 - Inbound Doorbell Status Register */
+	uint	iedqtpar;	/* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */
+	uint	iqtpar;	        /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */
+	uint	iedqhpar;	/* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */
+	uint	idqhpar;	/* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */
+	uint	idmirir;	/* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */
+	char	res57[100];
+	uint	pwmr;		/* 0xd34e0 - Port-Write Mode Register */
+	uint	pwsr;		/* 0xd34e4 - Port-Write Status Register */
+	uint	epwqbar;	/* 0xd34e8 - Extended Port-Write Queue Base Address Register */
+	uint	pwqbar;		/* 0xd34ec - Port-Write Queue Base Address Register */
+	char	res58[51984];
+} ccsr_rio_t;
+
+/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
+typedef struct ccsr_gur {
+	uint	porpllsr;	/* 0xe0000 - POR PLL ratio status register */
+	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
+	uint	porimpscr;	/* 0xe0008 - POR I/O impedance status and control register */
+	uint	pordevsr;	/* 0xe000c - POR I/O device status regsiter */
+	uint	pordbgmsr;	/* 0xe0010 - POR debug mode status register */
+	char	res1[12];
+	uint	gpporcr;	/* 0xe0020 - General-purpose POR configuration register */
+	char	res2[12];
+	uint	gpiocr;		/* 0xe0030 - GPIO control register */
+	char	res3[12];
+	uint	gpoutdr;	/* 0xe0040 - General-purpose output data register */
+	char	res4[12];
+	uint	gpindr;		/* 0xe0050 - General-purpose input data register */
+	char	res5[12];
+	uint	pmuxcr;		/* 0xe0060 - Alternate function signal multiplex control */
+	char	res6[12];
+	uint	devdisr;	/* 0xe0070 - Device disable control */
+	char	res7[12];
+	uint	powmgtcsr;	/* 0xe0080 - Power management status and control register */
+	char	res8[12];
+	uint	mcpsumr;	/* 0xe0090 - Machine check summary register */
+	uint	rstrscr;	/* 0xe0094 - Reset request status and control register */
+	char	res9[8];
+	uint	pvr;		/* 0xe00a0 - Processor version register */
+	uint	svr;		/* 0xe00a4 - System version register */
+	char	res10a[8];
+	uint	rstcr;		/* 0xe00b0 - Reset control register */
+	char	res10b[1868];
+	uint	clkdvdr;	/* 0xe0800 - Clock Divide register */
+	char	res10c[796];
+	uint	ddr1clkdr;	/* 0xe0b20 - DDRC1 Clock Disable register */
+	char	res10d[4];
+	uint	ddr2clkdr;	/* 0xe0b28 - DDRC2 Clock Disable register */
+	char	res10e[724];
+	uint	clkocr;		/* 0xe0e00 - Clock out select register */
+	char	res11[12];
+	uint	ddrdllcr;	/* 0xe0e10 - DDR DLL control register */
+	char	res12[12];
+	uint	lbcdllcr;	/* 0xe0e20 - LBC DLL control register */
+	char	res13a[224];
+	uint	srds1cr0;	/* 0xe0f04 - SerDes1 control register 0 */
+	char	res13b[4];
+	uint	srds1cr1;	/* 0xe0f08 - SerDes1 control register 1 */
+	char	res14[24];
+	uint	ddrioovcr;	/* 0xe0f24 - DDR IO Overdrive Control register */
+	char	res15a[24];
+	uint	srds2cr0;	/* 0xe0f40 - SerDes2 control register 0 */
+	uint	srds2cr1;	/* 0xe0f44 - SerDes2 control register 1 */
+	char	res16[184];
+} ccsr_gur_t;
+
+#define MPC8610_PORBMSR_HA      0x00070000
+#define MPC8610_PORBMSR_HA_SHIFT	16
+#define MPC8641_PORBMSR_HA      0x00060000
+#define MPC8641_PORBMSR_HA_SHIFT	17
+#define MPC8610_PORDEVSR_IO_SEL		0x00380000
+#define MPC8610_PORDEVSR_IO_SEL_SHIFT		19
+#define MPC8641_PORDEVSR_IO_SEL		0x000F0000
+#define MPC8641_PORDEVSR_IO_SEL_SHIFT		16
+#define MPC86xx_PORDEVSR_CORE1TE	0x00000080 /* ASMP (Core1 addr trans) */
+#define MPC86xx_DEVDISR_PCIEX1	0x80000000
+#define MPC86xx_DEVDISR_PCIEX2	0x40000000
+#define MPC86xx_DEVDISR_PCI1	0x80000000
+#define MPC86xx_DEVDISR_PCIE1	0x40000000
+#define MPC86xx_DEVDISR_PCIE2	0x20000000
+#define MPC86xx_DEVDISR_SRIO	0x00080000
+#define MPC86xx_DEVDISR_RMSG	0x00040000
+#define MPC86xx_DEVDISR_CPU0	0x00008000
+#define MPC86xx_DEVDISR_CPU1	0x00004000
+#define MPC86xx_RSTCR_HRST_REQ	0x00000002
+
+/*
+ * Watchdog register block(0xe_4000-0xe_4fff)
+ */
+typedef struct ccsr_wdt {
+	uint	res0;
+	uint	swcrr; /* System watchdog control register */
+	uint	swcnr; /* System watchdog count register */
+	char	res1[2];
+	ushort	swsrr; /* System watchdog service register */
+	char	res2[4080];
+} ccsr_wdt_t;
+
+typedef struct immap {
+	ccsr_local_mcm_t	im_local_mcm;
+	struct ccsr_ddr		im_ddr1;
+	ccsr_i2c_t		im_i2c;
+	ccsr_duart_t		im_duart;
+	fsl_lbc_t		im_lbc;
+	struct ccsr_ddr		im_ddr2;
+	char                    res1[4096];
+	ccsr_pex_t		im_pex1;
+	ccsr_pex_t		im_pex2;
+	ccsr_ht_t               im_ht;
+	char                    res2[90112];
+	ccsr_dma_t		im_dma;
+	char                    res3[8192];
+	ccsr_tsec_t		im_tsec1;
+	ccsr_tsec_t		im_tsec2;
+	ccsr_tsec_t             im_tsec3;
+	ccsr_tsec_t             im_tsec4;
+	char                    res4[98304];
+	ccsr_pic_t		im_pic;
+	char                    res5[389120];
+	ccsr_rio_t		im_rio;
+	ccsr_gur_t		im_gur;
+	char			res6[12288];
+	ccsr_wdt_t		im_wdt;
+} immap_t;
+
+extern immap_t  *immr;
+
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET	0x2000
+#define CONFIG_SYS_FSL_DDR_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET	0x6000
+#define CONFIG_SYS_FSL_DDR2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC86xx_DMA_OFFSET	0x21000
+#define CONFIG_SYS_MPC86xx_DMA_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC86xx_PIC_OFFSET	0x40000
+#define CONFIG_SYS_MPC8xxx_PIC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET)
+
+
+#define CONFIG_SYS_MPC86xx_PCI1_OFFSET		0x8000
+#ifdef CONFIG_ARCH_MPC8610
+#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET         0xa000
+#else
+#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET         0x8000
+#endif
+#define CONFIG_SYS_MPC86xx_PCIE2_OFFSET         0x9000
+
+#define CONFIG_SYS_PCI1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI1_OFFSET)
+#define CONFIG_SYS_PCI2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI2_OFFSET)
+#define CONFIG_SYS_PCIE1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE1_OFFSET)
+#define CONFIG_SYS_PCIE2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE2_OFFSET)
+
+#define CONFIG_SYS_TSEC1_OFFSET		0x24000
+#define CONFIG_SYS_MDIO1_OFFSET		0x24000
+#define CONFIG_SYS_LBC_ADDR		(&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
+
+#define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+
+#endif /*__IMMAP_86xx__*/
diff --git a/arch/powerpc/include/asm/immap_8xx.h b/arch/powerpc/include/asm/immap_8xx.h
new file mode 100644
index 0000000..3999a02
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_8xx.h
@@ -0,0 +1,468 @@
+/*
+ * MPC8xx Internal Memory Map
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * The I/O on the MPC860 is comprised of blocks of special registers
+ * and the dual port ram for the Communication Processor Module.
+ * Within this space are functional units such as the SIU, memory
+ * controller, system timers, and other control functions.  It is
+ * a combination that I found difficult to separate into logical
+ * functional files.....but anyone else is welcome to try.  -- Dan
+ */
+#ifndef __IMMAP_8XX__
+#define __IMMAP_8XX__
+
+/* System configuration registers.
+*/
+typedef	struct sys_conf {
+	uint	sc_siumcr;
+	uint	sc_sypcr;
+	uint	sc_swt;
+	char	res1[2];
+	ushort	sc_swsr;
+	uint	sc_sipend;
+	uint	sc_simask;
+	uint	sc_siel;
+	uint	sc_sivec;
+	uint	sc_tesr;
+	char	res2[0xc];
+	uint	sc_sdcr;
+	char	res3[0x4c];
+} sysconf8xx_t;
+
+/* PCMCIA configuration registers.
+*/
+typedef struct pcmcia_conf {
+	uint	pcmc_pbr0;
+	uint	pcmc_por0;
+	uint	pcmc_pbr1;
+	uint	pcmc_por1;
+	uint	pcmc_pbr2;
+	uint	pcmc_por2;
+	uint	pcmc_pbr3;
+	uint	pcmc_por3;
+	uint	pcmc_pbr4;
+	uint	pcmc_por4;
+	uint	pcmc_pbr5;
+	uint	pcmc_por5;
+	uint	pcmc_pbr6;
+	uint	pcmc_por6;
+	uint	pcmc_pbr7;
+	uint	pcmc_por7;
+	char	res1[0x20];
+	uint	pcmc_pgcra;
+	uint	pcmc_pgcrb;
+	uint	pcmc_pscr;
+	char	res2[4];
+	uint	pcmc_pipr;
+	char	res3[4];
+	uint	pcmc_per;
+	char	res4[4];
+} pcmconf8xx_t;
+
+/* Memory controller registers.
+*/
+typedef struct	mem_ctlr {
+	uint	memc_br0;
+	uint	memc_or0;
+	uint	memc_br1;
+	uint	memc_or1;
+	uint	memc_br2;
+	uint	memc_or2;
+	uint	memc_br3;
+	uint	memc_or3;
+	uint	memc_br4;
+	uint	memc_or4;
+	uint	memc_br5;
+	uint	memc_or5;
+	uint	memc_br6;
+	uint	memc_or6;
+	uint	memc_br7;
+	uint	memc_or7;
+	char	res1[0x24];
+	uint	memc_mar;
+	uint	memc_mcr;
+	char	res2[4];
+	uint	memc_mamr;
+	uint	memc_mbmr;
+	ushort	memc_mstat;
+	ushort	memc_mptpr;
+	uint	memc_mdr;
+	char	res3[0x80];
+} memctl8xx_t;
+
+/* System Integration Timers.
+*/
+typedef struct	sys_int_timers {
+	ushort	sit_tbscr;
+	char	res0[0x02];
+	uint	sit_tbreff0;
+	uint	sit_tbreff1;
+	char	res1[0x14];
+	ushort	sit_rtcsc;
+	char	res2[0x02];
+	uint	sit_rtc;
+	uint	sit_rtsec;
+	uint	sit_rtcal;
+	char	res3[0x10];
+	ushort	sit_piscr;
+	char	res4[2];
+	uint	sit_pitc;
+	uint	sit_pitr;
+	char	res5[0x34];
+} sit8xx_t;
+
+#define TBSCR_TBIRQ_MASK	((ushort)0xff00)
+#define TBSCR_REFA		((ushort)0x0080)
+#define TBSCR_REFB		((ushort)0x0040)
+#define TBSCR_REFAE		((ushort)0x0008)
+#define TBSCR_REFBE		((ushort)0x0004)
+#define TBSCR_TBF		((ushort)0x0002)
+#define TBSCR_TBE		((ushort)0x0001)
+
+#define RTCSC_RTCIRQ_MASK	((ushort)0xff00)
+#define RTCSC_SEC		((ushort)0x0080)
+#define RTCSC_ALR		((ushort)0x0040)
+#define RTCSC_38K		((ushort)0x0010)
+#define RTCSC_SIE		((ushort)0x0008)
+#define RTCSC_ALE		((ushort)0x0004)
+#define RTCSC_RTF		((ushort)0x0002)
+#define RTCSC_RTE		((ushort)0x0001)
+
+#define PISCR_PIRQ_MASK		((ushort)0xff00)
+#define PISCR_PS		((ushort)0x0080)
+#define PISCR_PIE		((ushort)0x0004)
+#define PISCR_PTF		((ushort)0x0002)
+#define PISCR_PTE		((ushort)0x0001)
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+	uint	car_sccr;
+	uint	car_plprcr;
+	uint	car_rsr;
+	char	res[0x74];        /* Reserved area                  */
+} car8xx_t;
+
+/* System Integration Timers keys.
+*/
+typedef struct sitk {
+	uint	sitk_tbscrk;
+	uint	sitk_tbreff0k;
+	uint	sitk_tbreff1k;
+	uint	sitk_tbk;
+	char	res1[0x10];
+	uint	sitk_rtcsck;
+	uint	sitk_rtck;
+	uint	sitk_rtseck;
+	uint	sitk_rtcalk;
+	char	res2[0x10];
+	uint	sitk_piscrk;
+	uint	sitk_pitck;
+	char	res3[0x38];
+} sitk8xx_t;
+
+/* Clocks and reset keys.
+*/
+typedef struct cark {
+	uint	cark_sccrk;
+	uint	cark_plprcrk;
+	uint	cark_rsrk;
+	char	res[0x474];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY	((unsigned int)0x55ccaa33)
+
+/* I2C
+*/
+typedef struct i2c {
+	u_char	i2c_i2mod;
+	char	res1[3];
+	u_char	i2c_i2add;
+	char	res2[3];
+	u_char	i2c_i2brg;
+	char	res3[3];
+	u_char	i2c_i2com;
+	char	res4[3];
+	u_char	i2c_i2cer;
+	char	res5[3];
+	u_char	i2c_i2cmr;
+	char	res6[0x8b];
+} i2c8xx_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+	char	res1[4];
+	uint	sdma_sdar;
+	u_char	sdma_sdsr;
+	char	res3[3];
+	u_char	sdma_sdmr;
+	char	res4[3];
+	u_char	sdma_idsr1;
+	char	res5[3];
+	u_char	sdma_idmr1;
+	char	res6[3];
+	u_char	sdma_idsr2;
+	char	res7[3];
+	u_char	sdma_idmr2;
+	char	res8[0x13];
+} sdma8xx_t;
+
+/* Communication Processor Module Interrupt Controller.
+*/
+typedef struct cpm_ic {
+	ushort	cpic_civr;
+	char	res[0xe];
+	uint	cpic_cicr;
+	uint	cpic_cipr;
+	uint	cpic_cimr;
+	uint	cpic_cisr;
+} cpic8xx_t;
+
+/* Input/Output Port control/status registers.
+*/
+typedef struct io_port {
+	ushort	iop_padir;
+	ushort	iop_papar;
+	ushort	iop_paodr;
+	ushort	iop_padat;
+	char	res1[8];
+	ushort	iop_pcdir;
+	ushort	iop_pcpar;
+	ushort	iop_pcso;
+	ushort	iop_pcdat;
+	ushort	iop_pcint;
+	char	res2[6];
+	ushort	iop_pddir;
+	ushort	iop_pdpar;
+	char	res3[2];
+	ushort	iop_pddat;
+	uint	utmode;
+	char	res4[4];
+} iop8xx_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+	ushort	cpmt_tgcr;
+	char	res1[0xe];
+	ushort	cpmt_tmr1;
+	ushort	cpmt_tmr2;
+	ushort	cpmt_trr1;
+	ushort	cpmt_trr2;
+	ushort	cpmt_tcr1;
+	ushort	cpmt_tcr2;
+	ushort	cpmt_tcn1;
+	ushort	cpmt_tcn2;
+	ushort	cpmt_tmr3;
+	ushort	cpmt_tmr4;
+	ushort	cpmt_trr3;
+	ushort	cpmt_trr4;
+	ushort	cpmt_tcr3;
+	ushort	cpmt_tcr4;
+	ushort	cpmt_tcn3;
+	ushort	cpmt_tcn4;
+	ushort	cpmt_ter1;
+	ushort	cpmt_ter2;
+	ushort	cpmt_ter3;
+	ushort	cpmt_ter4;
+	char	res2[8];
+} cpmtimer8xx_t;
+
+/* Finally, the Communication Processor stuff.....
+*/
+typedef struct scc {		/* Serial communication channels */
+	uint	scc_gsmrl;
+	uint	scc_gsmrh;
+	ushort	scc_psmr;
+	char	res1[2];
+	ushort	scc_todr;
+	ushort	scc_dsr;
+	ushort	scc_scce;
+	char	res2[2];
+	ushort	scc_sccm;
+	char	res3;
+	u_char	scc_sccs;
+	char	res4[8];
+} scc_t;
+
+typedef struct smc {		/* Serial management channels */
+	char	res1[2];
+	ushort	smc_smcmr;
+	char	res2[2];
+	u_char	smc_smce;
+	char	res3[3];
+	u_char	smc_smcm;
+	char	res4[5];
+} smc_t;
+
+/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
+ * it fits within the address space.
+ */
+
+typedef struct fec {
+	uint	fec_addr_low;		/* lower 32 bits of station address	*/
+	ushort	fec_addr_high;		/* upper 16 bits of station address	*/
+	ushort	res1;			/* reserved				*/
+	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
+	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
+	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
+	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
+	uint	fec_r_buff_size;	/* Rx buffer size			*/
+	uint	res2[9];		/* reserved				*/
+	uint	fec_ecntrl;		/* ethernet control register		*/
+	uint	fec_ievent;		/* interrupt event register		*/
+	uint	fec_imask;		/* interrupt mask register		*/
+	uint	fec_ivec;		/* interrupt level and vector status	*/
+	uint	fec_r_des_active;	/* Rx ring updated flag			*/
+	uint	fec_x_des_active;	/* Tx ring updated flag			*/
+	uint	res3[10];		/* reserved				*/
+	uint	fec_mii_data;		/* MII data register			*/
+	uint	fec_mii_speed;		/* MII speed control register		*/
+	uint	res4[17];		/* reserved				*/
+	uint	fec_r_bound;		/* end of RAM (read-only)		*/
+	uint	fec_r_fstart;		/* Rx FIFO start address		*/
+	uint	res5[6];		/* reserved				*/
+	uint	fec_x_fstart;		/* Tx FIFO start address		*/
+	uint	res6[17];		/* reserved				*/
+	uint	fec_fun_code;		/* fec SDMA function code		*/
+	uint	res7[3];		/* reserved				*/
+	uint	fec_r_cntrl;		/* Rx control register			*/
+	uint	fec_r_hash;		/* Rx hash register			*/
+	uint	res8[14];		/* reserved				*/
+	uint	fec_x_cntrl;		/* Tx control register			*/
+	uint	res9[0x1e];		/* reserved				*/
+} fec_t;
+
+typedef struct comm_proc {
+	/* General control and status registers.
+	*/
+	ushort	cp_cpcr;
+	u_char	res1[2];
+	ushort	cp_rccr;
+	u_char	res2;
+	u_char	cp_rmds;
+	u_char	res3[4];
+	ushort	cp_cpmcr1;
+	ushort	cp_cpmcr2;
+	ushort	cp_cpmcr3;
+	ushort	cp_cpmcr4;
+	u_char	res4[2];
+	ushort	cp_rter;
+	u_char	res5[2];
+	ushort	cp_rtmr;
+	u_char	res6[0x14];
+
+	/* Baud rate generators.
+	*/
+	uint	cp_brgc1;
+	uint	cp_brgc2;
+	uint	cp_brgc3;
+	uint	cp_brgc4;
+
+	/* Serial Communication Channels.
+	*/
+	scc_t	cp_scc[4];
+
+	/* Serial Management Channels.
+	*/
+	smc_t	cp_smc[2];
+
+	/* Serial Peripheral Interface.
+	*/
+	ushort	cp_spmode;
+	u_char	res7[4];
+	u_char	cp_spie;
+	u_char	res8[3];
+	u_char	cp_spim;
+	u_char	res9[2];
+	u_char	cp_spcom;
+	u_char	res10[2];
+
+	/* Parallel Interface Port.
+	*/
+	u_char	res11[2];
+	ushort	cp_pipc;
+	u_char	res12[2];
+	ushort	cp_ptpr;
+	uint	cp_pbdir;
+	uint	cp_pbpar;
+	u_char	res13[2];
+	ushort	cp_pbodr;
+	uint	cp_pbdat;
+
+	/* Port E - MPC87x/88x only.
+	 */
+	uint	cp_pedir;
+	uint	cp_pepar;
+	uint	cp_peso;
+	uint	cp_peodr;
+	uint	cp_pedat;
+
+	/* Communications Processor Timing Register -
+	   Contains RMII Timing for the FECs on MPC87x/88x only.
+	*/
+	uint	cp_cptr;
+
+	/* Serial Interface and Time Slot Assignment.
+	*/
+	uint	cp_simode;
+	u_char	cp_sigmr;
+	u_char	res15;
+	u_char	cp_sistr;
+	u_char	cp_sicmr;
+	u_char	res16[4];
+	uint	cp_sicr;
+	uint	cp_sirp;
+	u_char	res17[0xc];
+
+	u_char	res19[0x100];
+	u_char	cp_siram[0x200];
+
+	/* The fast ethernet controller is not really part of the CPM,
+	 * but it resides in the address space.
+	 */
+	fec_t	cp_fec;
+	char	res18[0xE00];
+
+	/* The MPC885 family has a second FEC here */
+	fec_t	cp_fec2;
+#define cp_fec1	cp_fec	/* consistency macro */
+
+	/* Dual Ported RAM follows.
+	 * There are many different formats for this memory area
+	 * depending upon the devices used and options chosen.
+	 * Some processors don't have all of it populated.
+	 */
+	u_char	cp_dpmem[0x1C00];	/* BD / Data / ucode */
+
+	/* Parameter RAM */
+	union {
+		u_char	cp_dparam[0x400];
+		u16	cp_dparam16[0x200];
+	};
+} cpm8xx_t;
+
+/* Internal memory map.
+*/
+typedef struct immap {
+	sysconf8xx_t	im_siu_conf;	/* SIU Configuration */
+	pcmconf8xx_t	im_pcmcia;	/* PCMCIA Configuration */
+	memctl8xx_t	im_memctl;	/* Memory Controller */
+	sit8xx_t	im_sit;		/* System integration timers */
+	car8xx_t	im_clkrst;	/* Clocks and reset */
+	sitk8xx_t	im_sitk;	/* Sys int timer keys */
+	cark8xx_t	im_clkrstk;	/* Clocks and reset keys */
+	char		res[96];
+	i2c8xx_t	im_i2c;		/* I2C control/status */
+	sdma8xx_t	im_sdma;	/* SDMA control/status */
+	cpic8xx_t	im_cpic;	/* CPM Interrupt Controller */
+	iop8xx_t	im_ioport;	/* IO Port control/status */
+	cpmtimer8xx_t	im_cpmtimer;	/* CPM timers */
+	cpm8xx_t	im_cpm;		/* Communication processor */
+} immap_t;
+
+#endif /* __IMMAP_8XX__ */
diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h
new file mode 100644
index 0000000..cda21a2
--- /dev/null
+++ b/arch/powerpc/include/asm/interrupt.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
+ */
+#ifndef INTERRUPT_H
+#define INTERRUPT_H
+
+void external_interrupt(struct pt_regs *regs);
+
+#endif
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
new file mode 100644
index 0000000..6d76e3e
--- /dev/null
+++ b/arch/powerpc/include/asm/io.h
@@ -0,0 +1,325 @@
+/* originally from linux source.
+ * removed the dependencies on CONFIG_ values
+ * removed virt_to_phys stuff (and in fact everything surrounded by #if __KERNEL__)
+ * Modified By Rob Taylor, Flying Pig Systems, 2000
+ */
+
+#ifndef _PPC_IO_H
+#define _PPC_IO_H
+
+#include <asm/byteorder.h>
+
+#ifdef CONFIG_ADDR_MAP
+#include <addr_map.h>
+#endif
+
+#define SIO_CONFIG_RA   0x398
+#define SIO_CONFIG_RD   0x399
+
+#ifndef _IO_BASE
+#define _IO_BASE 0
+#endif
+
+#define readb(addr) in_8((volatile u8 *)(addr))
+#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
+#if !defined(__BIG_ENDIAN)
+#define readw(addr) (*(volatile u16 *) (addr))
+#define readl(addr) (*(volatile u32 *) (addr))
+#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
+#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+#else
+#define readw(addr) in_le16((volatile u16 *)(addr))
+#define readl(addr) in_le32((volatile u32 *)(addr))
+#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
+#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
+#endif
+
+/*
+ * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * They are only used in practice for transferring buffers which
+ * are arrays of bytes, and byte-swapping is not appropriate in
+ * that case.  - paulus
+ */
+#define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define outsb(port, buf, ns)    _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns)    _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl(port, buf, nl)    _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define inb(port)       in_8((u8 *)((port)+_IO_BASE))
+#define outb(val, port)     out_8((u8 *)((port)+_IO_BASE), (val))
+#if !defined(__BIG_ENDIAN)
+#define inw(port)       in_be16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)     out_be16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)       in_be32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)     out_be32((u32 *)((port)+_IO_BASE), (val))
+#else
+#define inw(port)       in_le16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)     out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)       in_le32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)     out_le32((u32 *)((port)+_IO_BASE), (val))
+#endif
+
+#define inb_p(port)     in_8((u8 *)((port)+_IO_BASE))
+#define outb_p(val, port)   out_8((u8 *)((port)+_IO_BASE), (val))
+#define inw_p(port)     in_le16((u16 *)((port)+_IO_BASE))
+#define outw_p(val, port)   out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl_p(port)     in_le32((u32 *)((port)+_IO_BASE))
+#define outl_p(val, port)   out_le32((u32 *)((port)+_IO_BASE), (val))
+
+extern void _insb(volatile u8 *port, void *buf, int ns);
+extern void _outsb(volatile u8 *port, const void *buf, int ns);
+extern void _insw(volatile u16 *port, void *buf, int ns);
+extern void _outsw(volatile u16 *port, const void *buf, int ns);
+extern void _insl(volatile u32 *port, void *buf, int nl);
+extern void _outsl(volatile u32 *port, const void *buf, int nl);
+extern void _insw_ns(volatile u16 *port, void *buf, int ns);
+extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
+extern void _insl_ns(volatile u32 *port, void *buf, int nl);
+extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
+
+/*
+ * The *_ns versions below don't do byte-swapping.
+ * Neither do the standard versions now, these are just here
+ * for older code.
+ */
+#define insw_ns(port, buf, ns)  _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl_ns(port, buf, nl)  _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+
+#define IO_SPACE_LIMIT ~0
+
+#define memset_io(a,b,c)       memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)   memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)  memcpy((void *)(a),(b),(c))
+
+/*
+ * Enforce In-order Execution of I/O:
+ * Acts as a barrier to ensure all previous I/O accesses have
+ * completed before any further ones are issued.
+ */
+static inline void eieio(void)
+{
+	__asm__ __volatile__ ("eieio" : : : "memory");
+}
+
+static inline void sync(void)
+{
+	__asm__ __volatile__ ("sync" : : : "memory");
+}
+
+static inline void isync(void)
+{
+	__asm__ __volatile__ ("isync" : : : "memory");
+}
+
+/* Enforce in-order execution of data I/O.
+ * No distinction between read/write on PPC; use eieio for all three.
+ */
+#define iobarrier_rw() eieio()
+#define iobarrier_r()  eieio()
+#define iobarrier_w()  eieio()
+
+#define mb()	sync()
+#define isb()	isync()
+
+/*
+ * Non ordered and non-swapping "raw" accessors
+ */
+#define PCI_FIX_ADDR(addr)	(addr)
+
+static inline unsigned char __raw_readb(const volatile void __iomem *addr)
+{
+	return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
+}
+static inline unsigned short __raw_readw(const volatile void __iomem *addr)
+{
+	return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
+}
+static inline unsigned int __raw_readl(const volatile void __iomem *addr)
+{
+	return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
+}
+static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
+{
+	*(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
+}
+static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
+{
+	*(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
+}
+static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
+{
+	*(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
+}
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ *
+ * Read operations have additional twi & isync to make sure the read
+ * is actually performed (i.e. the data has come back) before we start
+ * executing any following instructions.
+ */
+static inline u8 in_8(const volatile unsigned char __iomem *addr)
+{
+	u8 ret;
+
+	__asm__ __volatile__(
+		"sync; lbz%U1%X1 %0,%1;\n"
+		"twi 0,%0,0;\n"
+		"isync" : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+static inline void out_8(volatile unsigned char __iomem *addr, u8 val)
+{
+	__asm__ __volatile__("sync;\n"
+			     "stb%U0%X0 %1,%0;\n"
+			     : "=m" (*addr)
+			     : "r" (val));
+}
+
+static inline u16 in_le16(const volatile unsigned short __iomem *addr)
+{
+	u16 ret;
+
+	__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) :
+			      "r" (addr), "m" (*addr));
+	return ret;
+}
+
+static inline u16 in_be16(const volatile unsigned short __iomem *addr)
+{
+	u16 ret;
+
+	__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+static inline void out_le16(volatile unsigned short __iomem *addr, u16 val)
+{
+	__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
+			      "r" (val), "r" (addr));
+}
+
+static inline void out_be16(volatile unsigned short __iomem *addr, u16 val)
+{
+	__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
+}
+
+static inline u32 in_le32(const volatile unsigned __iomem *addr)
+{
+	u32 ret;
+
+	__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) :
+			     "r" (addr), "m" (*addr));
+	return ret;
+}
+
+static inline u32 in_be32(const volatile unsigned __iomem *addr)
+{
+	u32 ret;
+
+	__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) : "m" (*addr));
+	return ret;
+}
+
+static inline void out_le32(volatile unsigned __iomem *addr, u32 val)
+{
+	__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
+			     "r" (val), "r" (addr));
+}
+
+static inline void out_be32(volatile unsigned __iomem *addr, u32 val)
+{
+	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
+}
+
+/* Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+#define readb_be(addr)							\
+	__raw_readb((__force unsigned *)(addr))
+#define readw_be(addr)							\
+	be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
+#define readl_be(addr)							\
+	be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
+#define readq_be(addr)							\
+	be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
+
+#define writeb_be(val, addr)						\
+	__raw_writeb((val), (__force unsigned *)(addr))
+#define writew_be(val, addr)						\
+	__raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
+#define writel_be(val, addr)						\
+	__raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
+#define writeq_be(val, addr)						\
+	__raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
+
+static inline void *phys_to_virt(phys_addr_t paddr)
+{
+#ifdef CONFIG_ADDR_MAP
+	return addrmap_phys_to_virt(paddr);
+#else
+	return (void *)((unsigned long)paddr);
+#endif
+}
+#define phys_to_virt phys_to_virt
+
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+#ifdef CONFIG_ADDR_MAP
+	return addrmap_virt_to_phys(vaddr);
+#else
+	return (phys_addr_t)((unsigned long)vaddr);
+#endif
+}
+#define virt_to_phys virt_to_phys
+
+#include <asm-generic/io.h>
+
+#endif
diff --git a/arch/powerpc/include/asm/iopin_8xx.h b/arch/powerpc/include/asm/iopin_8xx.h
new file mode 100644
index 0000000..a41b332
--- /dev/null
+++ b/arch/powerpc/include/asm/iopin_8xx.h
@@ -0,0 +1,466 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * MPC8xx I/O port pin manipulation functions
+ * Roughly based on iopin_8260.h
+ */
+
+#ifndef _ASM_IOPIN_8XX_H_
+#define _ASM_IOPIN_8XX_H_
+
+#include <linux/types.h>
+#include <asm/immap_8xx.h>
+#include <asm/io.h>
+
+#ifdef __KERNEL__
+
+typedef struct {
+	u_char port:2;	/* port number (A=0, B=1, C=2, D=3) */
+	u_char pin:5;	/* port pin (0-31) */
+	u_char flag:1;	/* for whatever */
+} iopin_t;
+
+#define IOPIN_PORTA	0
+#define IOPIN_PORTB	1
+#define IOPIN_PORTC	2
+#define IOPIN_PORTD	3
+
+static inline void iopin_set_high(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+		setbits_be16(datp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+		setbits_be32(datp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+		setbits_be16(datp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+		setbits_be16(datp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_low(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+		clrbits_be16(datp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+		clrbits_be32(datp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+		clrbits_be16(datp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+		clrbits_be16(datp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_high(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+		return (in_be16(datp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+		return (in_be32(datp) >> (31 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+		return (in_be16(datp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+		return (in_be16(datp) >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_low(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+		return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+		return ((in_be32(datp) >> (31 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+		return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+		return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+static inline void iopin_set_out(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+		setbits_be16(dirp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+		setbits_be32(dirp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+		setbits_be16(dirp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+		setbits_be16(dirp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_in(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+		clrbits_be16(dirp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+		clrbits_be32(dirp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+		clrbits_be16(dirp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+		clrbits_be16(dirp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_out(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+		return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+		return (in_be32(dirp) >> (31 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+		return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+		return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_in(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+		return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+		return ((in_be32(dirp) >> (31 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+		return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+		return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+static inline void iopin_set_odr(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+		setbits_be16(odrp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+		setbits_be16(odrp, 1 << (31 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_act(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+		clrbits_be16(odrp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+		clrbits_be16(odrp, 1 << (31 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_odr(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+		return (in_be16(odrp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+		return (in_be16(odrp) >> (31 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_act(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+		return ((in_be16(odrp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+		return ((in_be16(odrp) >> (31 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+static inline void iopin_set_ded(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+		setbits_be16(parp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+		setbits_be32(parp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+		setbits_be16(parp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+		setbits_be16(parp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_gen(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+		clrbits_be16(parp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+		clrbits_be32(parp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+		clrbits_be16(parp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+		clrbits_be16(parp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_ded(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+		return (in_be16(parp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+		return (in_be32(parp) >> (31 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+		return (in_be16(parp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+		return (in_be16(parp) >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_gen(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+		return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+		return ((in_be32(parp) >> (31 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+		return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+		return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+static inline void iopin_set_opt2(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+		setbits_be16(sorp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_opt1(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+		clrbits_be16(sorp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_opt2(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+		return (in_be16(sorp) >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_opt1(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+		return ((in_be16(sorp) >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+static inline void iopin_set_falledge(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+		setbits_be16(intp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_anyedge(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+		clrbits_be16(intp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_falledge(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+		return (in_be16(intp) >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_anyedge(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+		return ((in_be16(intp) >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IOPIN_8XX_H_ */
diff --git a/arch/powerpc/include/asm/linkage.h b/arch/powerpc/include/asm/linkage.h
new file mode 100644
index 0000000..f9b036e
--- /dev/null
+++ b/arch/powerpc/include/asm/linkage.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc
+ */
+
+/* We don't need anything here at present */
diff --git a/arch/powerpc/include/asm/mc146818rtc.h b/arch/powerpc/include/asm/mc146818rtc.h
new file mode 100644
index 0000000..5f806c4
--- /dev/null
+++ b/arch/powerpc/include/asm/mc146818rtc.h
@@ -0,0 +1,27 @@
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef __ASM_PPC_MC146818RTC_H
+#define __ASM_PPC_MC146818RTC_H
+
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+#define RTC_PORT(x) (0x70 + (x))
+#define RTC_ALWAYS_BCD  1   /* RTC operates in binary mode */
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+inb_p(RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+outb_p((val),RTC_PORT(1)); \
+})
+
+#endif /* __ASM_PPC_MC146818RTC_H */
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
new file mode 100644
index 0000000..82e5f9f
--- /dev/null
+++ b/arch/powerpc/include/asm/mmu.h
@@ -0,0 +1,588 @@
+/*
+ * PowerPC memory management structures
+ */
+
+#ifndef _PPC_MMU_H_
+#define _PPC_MMU_H_
+
+#ifndef __ASSEMBLY__
+/* Hardware Page Table Entry */
+typedef struct _PTE {
+#ifdef CONFIG_PPC64BRIDGE
+	unsigned long long vsid:52;
+	unsigned long api:5;
+	unsigned long :5;
+	unsigned long h:1;
+	unsigned long v:1;
+	unsigned long long rpn:52;
+#else /* CONFIG_PPC64BRIDGE */
+	unsigned long v:1;	/* Entry is valid */
+	unsigned long vsid:24;	/* Virtual segment identifier */
+	unsigned long h:1;	/* Hash algorithm indicator */
+	unsigned long api:6;	/* Abbreviated page index */
+	unsigned long rpn:20;	/* Real (physical) page number */
+#endif /* CONFIG_PPC64BRIDGE */
+	unsigned long    :3;	/* Unused */
+	unsigned long r:1;	/* Referenced */
+	unsigned long c:1;	/* Changed */
+	unsigned long w:1;	/* Write-thru cache mode */
+	unsigned long i:1;	/* Cache inhibited */
+	unsigned long m:1;	/* Memory coherence */
+	unsigned long g:1;	/* Guarded */
+	unsigned long  :1;	/* Unused */
+	unsigned long pp:2;	/* Page protection */
+} PTE;
+
+/* Values for PP (assumes Ks=0, Kp=1) */
+#define PP_RWXX	0	/* Supervisor read/write, User none */
+#define PP_RWRX 1	/* Supervisor read/write, User read */
+#define PP_RWRW 2	/* Supervisor read/write, User read/write */
+#define PP_RXRX 3	/* Supervisor read,       User read */
+
+/* Segment Register */
+typedef struct _SEGREG {
+	unsigned long t:1;	/* Normal or I/O  type */
+	unsigned long ks:1;	/* Supervisor 'key' (normally 0) */
+	unsigned long kp:1;	/* User 'key' (normally 1) */
+	unsigned long n:1;	/* No-execute */
+	unsigned long :4;	/* Unused */
+	unsigned long vsid:24;	/* Virtual Segment Identifier */
+} SEGREG;
+
+/* Block Address Translation (BAT) Registers */
+typedef struct _P601_BATU {	/* Upper part of BAT for 601 processor */
+	unsigned long bepi:15;	/* Effective page index (virtual address) */
+	unsigned long :8;	/* unused */
+	unsigned long w:1;
+	unsigned long i:1;	/* Cache inhibit */
+	unsigned long m:1;	/* Memory coherence */
+	unsigned long ks:1;	/* Supervisor key (normally 0) */
+	unsigned long kp:1;	/* User key (normally 1) */
+	unsigned long pp:2;	/* Page access protections */
+} P601_BATU;
+
+typedef struct _BATU {		/* Upper part of BAT (all except 601) */
+#ifdef CONFIG_PPC64BRIDGE
+	unsigned long long bepi:47;
+#else /* CONFIG_PPC64BRIDGE */
+	unsigned long bepi:15;	/* Effective page index (virtual address) */
+#endif /* CONFIG_PPC64BRIDGE */
+	unsigned long :4;	/* Unused */
+	unsigned long bl:11;	/* Block size mask */
+	unsigned long vs:1;	/* Supervisor valid */
+	unsigned long vp:1;	/* User valid */
+} BATU;
+
+typedef struct _P601_BATL {	/* Lower part of BAT for 601 processor */
+	unsigned long brpn:15;	/* Real page index (physical address) */
+	unsigned long :10;	/* Unused */
+	unsigned long v:1;	/* Valid bit */
+	unsigned long bl:6;	/* Block size mask */
+} P601_BATL;
+
+typedef struct _BATL {		/* Lower part of BAT (all except 601) */
+#ifdef CONFIG_PPC64BRIDGE
+	unsigned long long brpn:47;
+#else /* CONFIG_PPC64BRIDGE */
+	unsigned long brpn:15;	/* Real page index (physical address) */
+#endif /* CONFIG_PPC64BRIDGE */
+	unsigned long :10;	/* Unused */
+	unsigned long w:1;	/* Write-thru cache */
+	unsigned long i:1;	/* Cache inhibit */
+	unsigned long m:1;	/* Memory coherence */
+	unsigned long g:1;	/* Guarded (MBZ in IBAT) */
+	unsigned long :1;	/* Unused */
+	unsigned long pp:2;	/* Page access protections */
+} BATL;
+
+typedef struct _BAT {
+	BATU batu;		/* Upper register */
+	BATL batl;		/* Lower register */
+} BAT;
+
+typedef struct _P601_BAT {
+	P601_BATU batu;		/* Upper register */
+	P601_BATL batl;		/* Lower register */
+} P601_BAT;
+
+/*
+ * Simulated two-level MMU.  This structure is used by the kernel
+ * to keep track of MMU mappings and is used to update/maintain
+ * the hardware HASH table which is really a cache of mappings.
+ *
+ * The simulated structures mimic the hardware available on other
+ * platforms, notably the 80x86 and 680x0.
+ */
+
+typedef struct _pte {
+	unsigned long page_num:20;
+	unsigned long flags:12;		/* Page flags (some unused bits) */
+} pte;
+
+#define PD_SHIFT (10+12)		/* Page directory */
+#define PD_MASK  0x02FF
+#define PT_SHIFT (12)			/* Page Table */
+#define PT_MASK  0x02FF
+#define PG_SHIFT (12)			/* Page Entry */
+
+
+/* MMU context */
+
+typedef struct _MMU_context {
+	SEGREG	segs[16];	/* Segment registers */
+	pte	**pmap;		/* Two-level page-map structure */
+} MMU_context;
+
+extern void _tlbie(unsigned long va);	/* invalidate a TLB entry */
+extern void _tlbia(void);		/* invalidate all TLB entries */
+
+#ifdef CONFIG_ADDR_MAP
+extern void init_addr_map(void);
+#endif
+
+typedef enum {
+	IBAT0 = 0, IBAT1, IBAT2, IBAT3,
+	DBAT0, DBAT1, DBAT2, DBAT3,
+#ifdef CONFIG_HIGH_BATS
+	IBAT4, IBAT5, IBAT6, IBAT7,
+	DBAT4, DBAT5, DBAT6, DBAT7
+#endif
+} ppc_bat_t;
+
+extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
+extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
+extern void print_bats(void);
+
+#endif /* __ASSEMBLY__ */
+
+#define BATU_VS                 0x00000002
+#define BATU_VP                 0x00000001
+#define BATU_INVALID            0x00000000
+
+#define BATL_WRITETHROUGH       0x00000040
+#define BATL_CACHEINHIBIT       0x00000020
+#define BATL_MEMCOHERENCE	0x00000010
+#define BATL_GUARDEDSTORAGE     0x00000008
+#define BATL_NO_ACCESS		0x00000000
+
+#define BATL_PP_MSK		0x00000003
+#define BATL_PP_00		0x00000000 /* No access */
+#define BATL_PP_01		0x00000001 /* Read-only */
+#define BATL_PP_10		0x00000002 /* Read-write */
+#define BATL_PP_11		0x00000003
+
+#define BATL_PP_NO_ACCESS	BATL_PP_00
+#define BATL_PP_RO		BATL_PP_01
+#define BATL_PP_RW		BATL_PP_10
+
+/* BAT Block size values */
+#define BATU_BL_128K            0x00000000
+#define BATU_BL_256K            0x00000004
+#define BATU_BL_512K            0x0000000c
+#define BATU_BL_1M              0x0000001c
+#define BATU_BL_2M              0x0000003c
+#define BATU_BL_4M              0x0000007c
+#define BATU_BL_8M              0x000000fc
+#define BATU_BL_16M             0x000001fc
+#define BATU_BL_32M             0x000003fc
+#define BATU_BL_64M             0x000007fc
+#define BATU_BL_128M            0x00000ffc
+#define BATU_BL_256M            0x00001ffc
+
+/* Block lengths for processors that support extended block length */
+#ifdef HID0_XBSEN
+#define BATU_BL_512M            0x00003ffc
+#define BATU_BL_1G              0x00007ffc
+#define BATU_BL_2G              0x0000fffc
+#define BATU_BL_4G              0x0001fffc
+#define BATU_BL_MAX		BATU_BL_4G
+#else
+#define BATU_BL_MAX		BATU_BL_256M
+#endif
+
+/* BAT Access Protection */
+#define BPP_XX	0x00		/* No access */
+#define BPP_RX	0x01		/* Read only */
+#define BPP_RW	0x02		/* Read/write */
+
+/* Macros to get values from BATs, once data is in the BAT register format */
+#define BATU_VALID(x) (x & 0x3)
+#define BATU_VADDR(x) (x & 0xfffe0000)
+#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000)		\
+				     | ((x & 0x0e00ULL) << 24)	\
+				     | ((x & 0x04ULL) << 30)))
+#define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17))
+
+/* bytes into BATU_BL */
+#define TO_BATU_BL(x) \
+	(u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4)
+
+/* Used to set up SDR1 register */
+#define HASH_TABLE_SIZE_64K	0x00010000
+#define HASH_TABLE_SIZE_128K	0x00020000
+#define HASH_TABLE_SIZE_256K	0x00040000
+#define HASH_TABLE_SIZE_512K	0x00080000
+#define HASH_TABLE_SIZE_1M	0x00100000
+#define HASH_TABLE_SIZE_2M	0x00200000
+#define HASH_TABLE_SIZE_4M	0x00400000
+#define HASH_TABLE_MASK_64K	0x000
+#define HASH_TABLE_MASK_128K	0x001
+#define HASH_TABLE_MASK_256K	0x003
+#define HASH_TABLE_MASK_512K	0x007
+#define HASH_TABLE_MASK_1M	0x00F
+#define HASH_TABLE_MASK_2M	0x01F
+#define HASH_TABLE_MASK_4M	0x03F
+
+/* Control/status registers for the MPC8xx.
+ * A write operation to these registers causes serialized access.
+ * During software tablewalk, the registers used perform mask/shift-add
+ * operations when written/read.  A TLB entry is created when the Mx_RPN
+ * is written, and the contents of several registers are used to
+ * create the entry.
+ */
+#define MI_CTR		784	/* Instruction TLB control register */
+#define MI_GPM		0x80000000	/* Set domain manager mode */
+#define MI_PPM		0x40000000	/* Set subpage protection */
+#define MI_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
+#define MI_RSV4I	0x08000000	/* Reserve 4 TLB entries */
+#define MI_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
+#define MI_IDXMASK	0x00001f00	/* TLB index to be loaded */
+#define MI_RESETVAL	0x00000000	/* Value of register at reset */
+
+/* These are the Ks and Kp from the PowerPC books.  For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define MI_AP		786
+#define MI_Ks		0x80000000	/* Should not be set */
+#define MI_Kp		0x40000000	/* Should always be set */
+
+/* The effective page number register.  When read, contains the information
+ * about the last instruction TLB miss.  When MI_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define MI_EPN		787
+#define MI_EPNMASK	0xfffff000	/* Effective page number for entry */
+#define MI_EVALID	0x00000200	/* Entry is valid */
+#define MI_ASIDMASK	0x0000000f	/* ASID match value */
+					/* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the instruction TLB, it contains bits that get loaded into the
+ * TLB entry when the MI_RPN is written.
+ */
+#define MI_TWC		789
+#define MI_APG		0x000001e0	/* Access protection group (0) */
+#define MI_GUARDED	0x00000010	/* Guarded storage */
+#define MI_PSMASK	0x0000000c	/* Mask of page size bits */
+#define MI_PS8MEG	0x0000000c	/* 8M page size */
+#define MI_PS512K	0x00000004	/* 512K page size */
+#define MI_PS4K_16K	0x00000000	/* 4K or 16K page size */
+#define MI_SVALID	0x00000001	/* Segment entry is valid */
+					/* Reset value is undefined */
+
+/* Real page number.  Defined by the pte.  Writing this register
+ * causes a TLB entry to be created for the instruction TLB, using
+ * additional information from the MI_EPN, and MI_TWC registers.
+ */
+#define MI_RPN		790
+
+/* Define an RPN value for mapping kernel memory to large virtual
+ * pages for boot initialization.  This has real page number of 0,
+ * large page size, shared page, cache enabled, and valid.
+ * Also mark all subpages valid and write access.
+ */
+#define MI_BOOTINIT	0x000001fd
+
+#define MD_CTR		792	/* Data TLB control register */
+#define MD_GPM		0x80000000	/* Set domain manager mode */
+#define MD_PPM		0x40000000	/* Set subpage protection */
+#define MD_CIDEF	0x20000000	/* Set cache inhibit when MMU dis */
+#define MD_WTDEF	0x10000000	/* Set writethrough when MMU dis */
+#define MD_RSV4I	0x08000000	/* Reserve 4 TLB entries */
+#define MD_TWAM		0x04000000	/* Use 4K page hardware assist */
+#define MD_PPCS		0x02000000	/* Use MI_RPN prob/priv state */
+#define MD_IDXMASK	0x00001f00	/* TLB index to be loaded */
+#define MD_RESETVAL	0x04000000	/* Value of register at reset */
+
+#define M_CASID		793	/* Address space ID (context) to match */
+#define MC_ASIDMASK	0x0000000f	/* Bits used for ASID value */
+
+
+/* These are the Ks and Kp from the PowerPC books.  For proper operation,
+ * Ks = 0, Kp = 1.
+ */
+#define MD_AP		794
+#define MD_Ks		0x80000000	/* Should not be set */
+#define MD_Kp		0x40000000	/* Should always be set */
+
+/* The effective page number register.  When read, contains the information
+ * about the last instruction TLB miss.  When MD_RPN is written, bits in
+ * this register are used to create the TLB entry.
+ */
+#define MD_EPN		795
+#define MD_EPNMASK	0xfffff000	/* Effective page number for entry */
+#define MD_EVALID	0x00000200	/* Entry is valid */
+#define MD_ASIDMASK	0x0000000f	/* ASID match value */
+					/* Reset value is undefined */
+
+/* The pointer to the base address of the first level page table.
+ * During a software tablewalk, reading this register provides the address
+ * of the entry associated with MD_EPN.
+ */
+#define M_TWB		796
+#define	M_L1TB		0xfffff000	/* Level 1 table base address */
+#define M_L1INDX	0x00000ffc	/* Level 1 index, when read */
+					/* Reset value is undefined */
+
+/* A "level 1" or "segment" or whatever you want to call it register.
+ * For the data TLB, it contains bits that get loaded into the TLB entry
+ * when the MD_RPN is written.  It is also provides the hardware assist
+ * for finding the PTE address during software tablewalk.
+ */
+#define MD_TWC		797
+#define MD_L2TB		0xfffff000	/* Level 2 table base address */
+#define MD_L2INDX	0xfffffe00	/* Level 2 index (*pte), when read */
+#define MD_APG		0x000001e0	/* Access protection group (0) */
+#define MD_GUARDED	0x00000010	/* Guarded storage */
+#define MD_PSMASK	0x0000000c	/* Mask of page size bits */
+#define MD_PS8MEG	0x0000000c	/* 8M page size */
+#define MD_PS512K	0x00000004	/* 512K page size */
+#define MD_PS4K_16K	0x00000000	/* 4K or 16K page size */
+#define MD_WT		0x00000002	/* Use writethrough page attribute */
+#define MD_SVALID	0x00000001	/* Segment entry is valid */
+					/* Reset value is undefined */
+
+
+/* Real page number.  Defined by the pte.  Writing this register
+ * causes a TLB entry to be created for the data TLB, using
+ * additional information from the MD_EPN, and MD_TWC registers.
+ */
+#define MD_RPN		798
+
+/* This is a temporary storage register that could be used to save
+ * a processor working register during a tablewalk.
+ */
+#define M_TW		799
+
+/*
+ * At present, all PowerPC 400-class processors share a similar TLB
+ * architecture. The instruction and data sides share a unified,
+ * 64-entry, fully-associative TLB which is maintained totally under
+ * software control. In addition, the instruction side has a
+ * hardware-managed, 4-entry, fully- associative TLB which serves as a
+ * first level to the shared TLB. These two TLBs are known as the UTLB
+ * and ITLB, respectively.
+ */
+
+#define        PPC4XX_TLB_SIZE 64
+
+/*
+ * TLB entries are defined by a "high" tag portion and a "low" data
+ * portion.  On all architectures, the data portion is 32-bits.
+ *
+ * TLB entries are managed entirely under software control by reading,
+ * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
+ * instructions.
+ */
+
+/*
+ * FSL Book-E support
+ */
+
+#define MAS0_TLBSEL_MSK	0x30000000
+#define MAS0_TLBSEL(x)	(((x) << 28) & MAS0_TLBSEL_MSK)
+#define MAS0_ESEL_MSK	0x0FFF0000
+#define MAS0_ESEL(x)	(((x) << 16) & MAS0_ESEL_MSK)
+#define MAS0_NV(x)	((x) & 0x00000FFF)
+
+#define MAS1_VALID	0x80000000
+#define MAS1_IPROT	0x40000000
+#define MAS1_TID(x)	(((x) << 16) & 0x3FFF0000)
+#define MAS1_TS		0x00001000
+#define MAS1_TSIZE(x)	(((x) << 7) & 0x00000F80)
+#define TSIZE_TO_BYTES(x) (1ULL << ((x) + 10))
+
+#define MAS2_EPN	0xFFFFF000
+#define MAS2_X0		0x00000040
+#define MAS2_X1		0x00000020
+#define MAS2_W		0x00000010
+#define MAS2_I		0x00000008
+#define MAS2_M		0x00000004
+#define MAS2_G		0x00000002
+#define MAS2_E		0x00000001
+
+#define MAS3_RPN	0xFFFFF000
+#define MAS3_U0		0x00000200
+#define MAS3_U1		0x00000100
+#define MAS3_U2		0x00000080
+#define MAS3_U3		0x00000040
+#define MAS3_UX		0x00000020
+#define MAS3_SX		0x00000010
+#define MAS3_UW		0x00000008
+#define MAS3_SW		0x00000004
+#define MAS3_UR		0x00000002
+#define MAS3_SR		0x00000001
+
+#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
+#define MAS4_TIDDSEL	0x000F0000
+#define MAS4_TSIZED(x)	MAS1_TSIZE(x)
+#define MAS4_X0D	0x00000040
+#define MAS4_X1D	0x00000020
+#define MAS4_WD		0x00000010
+#define MAS4_ID		0x00000008
+#define MAS4_MD		0x00000004
+#define MAS4_GD		0x00000002
+#define MAS4_ED		0x00000001
+
+#define MAS6_SPID0	0x3FFF0000
+#define MAS6_SPID1	0x00007FFE
+#define MAS6_SAS	0x00000001
+#define MAS6_SPID	MAS6_SPID0
+
+#define MAS7_RPN	0xFFFFFFFF
+
+#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
+		(MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
+#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
+		((((v) << 31) & MAS1_VALID)             |\
+		(((iprot) << 30) & MAS1_IPROT)          |\
+		(MAS1_TID(tid))				|\
+		(((ts) << 12) & MAS1_TS)                |\
+		(MAS1_TSIZE(tsize)))
+#define FSL_BOOKE_MAS2(epn, wimge) \
+		(((epn) & MAS3_RPN) | (wimge))
+#define FSL_BOOKE_MAS3(rpn, user, perms) \
+		(((rpn) & MAS3_RPN) | (user) | (perms))
+#define FSL_BOOKE_MAS7(rpn) \
+		(((u64)(rpn)) >> 32)
+
+#define BOOKE_PAGESZ_1K		0
+#define BOOKE_PAGESZ_2K		1
+#define BOOKE_PAGESZ_4K		2
+#define BOOKE_PAGESZ_8K		3
+#define BOOKE_PAGESZ_16K	4
+#define BOOKE_PAGESZ_32K	5
+#define BOOKE_PAGESZ_64K	6
+#define BOOKE_PAGESZ_128K	7
+#define BOOKE_PAGESZ_256K	8
+#define BOOKE_PAGESZ_512K	9
+#define BOOKE_PAGESZ_1M		10
+#define BOOKE_PAGESZ_2M		11
+#define BOOKE_PAGESZ_4M		12
+#define BOOKE_PAGESZ_8M		13
+#define BOOKE_PAGESZ_16M	14
+#define BOOKE_PAGESZ_32M	15
+#define BOOKE_PAGESZ_64M	16
+#define BOOKE_PAGESZ_128M	17
+#define BOOKE_PAGESZ_256M	18
+#define BOOKE_PAGESZ_512M	19
+#define BOOKE_PAGESZ_1G		20
+#define BOOKE_PAGESZ_2G		21
+#define BOOKE_PAGESZ_4G		22
+#define BOOKE_PAGESZ_8G		23
+#define BOOKE_PAGESZ_16GB	24
+#define BOOKE_PAGESZ_32GB	25
+#define BOOKE_PAGESZ_64GB	26
+#define BOOKE_PAGESZ_128GB	27
+#define BOOKE_PAGESZ_256GB	28
+#define BOOKE_PAGESZ_512GB	29
+#define BOOKE_PAGESZ_1TB	30
+#define BOOKE_PAGESZ_2TB	31
+
+#define TLBIVAX_ALL		4
+#define TLBIVAX_TLB0		0
+#define TLBIVAX_TLB1		8
+
+#ifdef CONFIG_E500
+#ifndef __ASSEMBLY__
+extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
+		    u8 perms, u8 wimge,
+		    u8 ts, u8 esel, u8 tsize, u8 iprot);
+extern void disable_tlb(u8 esel);
+extern void invalidate_tlb(u8 tlb);
+extern void init_tlbs(void);
+extern int find_tlb_idx(void *addr, u8 tlbsel);
+extern void init_used_tlb_cams(void);
+extern int find_free_tlbcam(void);
+extern void print_tlbcam(void);
+
+extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
+extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
+
+enum tlb_map_type {
+	TLB_MAP_RAM,
+	TLB_MAP_IO,
+};
+
+extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
+			      enum tlb_map_type map_type);
+
+extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
+
+#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
+	{ .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \
+	  .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \
+	  .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \
+	  .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \
+	  .mas7 = FSL_BOOKE_MAS7(_rpn), }
+
+struct fsl_e_tlb_entry {
+	u32	mas0;
+	u32	mas1;
+	u32	mas2;
+	u32	mas3;
+	u32	mas7;
+};
+
+extern struct fsl_e_tlb_entry tlb_table[];
+extern int num_tlb_entries;
+#endif
+#endif
+
+#ifdef CONFIG_E300
+#define LAWAR_EN		0x80000000
+#define LAWAR_SIZE		0x0000003F
+
+#define LAWAR_TRGT_IF_PCI	0x00000000
+#define LAWAR_TRGT_IF_PCI1	0x00000000
+#define LAWAR_TRGT_IF_PCIX	0x00000000
+#define LAWAR_TRGT_IF_PCI2	0x00100000
+#define LAWAR_TRGT_IF_PCIE1	0x00200000
+#define LAWAR_TRGT_IF_PCIE2	0x00100000
+#define LAWAR_TRGT_IF_PCIE3	0x00300000
+#define LAWAR_TRGT_IF_LBC	0x00400000
+#define LAWAR_TRGT_IF_CCSR	0x00800000
+#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
+#define LAWAR_TRGT_IF_RIO	0x00c00000
+#define LAWAR_TRGT_IF_DDR	0x00f00000
+#define LAWAR_TRGT_IF_DDR1	0x00f00000
+#define LAWAR_TRGT_IF_DDR2	0x01600000
+
+#define LAWAR_SIZE_BASE		0xa
+#define LAWAR_SIZE_4K		(LAWAR_SIZE_BASE+1)
+#define LAWAR_SIZE_8K		(LAWAR_SIZE_BASE+2)
+#define LAWAR_SIZE_16K		(LAWAR_SIZE_BASE+3)
+#define LAWAR_SIZE_32K		(LAWAR_SIZE_BASE+4)
+#define LAWAR_SIZE_64K		(LAWAR_SIZE_BASE+5)
+#define LAWAR_SIZE_128K		(LAWAR_SIZE_BASE+6)
+#define LAWAR_SIZE_256K		(LAWAR_SIZE_BASE+7)
+#define LAWAR_SIZE_512K		(LAWAR_SIZE_BASE+8)
+#define LAWAR_SIZE_1M		(LAWAR_SIZE_BASE+9)
+#define LAWAR_SIZE_2M		(LAWAR_SIZE_BASE+10)
+#define LAWAR_SIZE_4M		(LAWAR_SIZE_BASE+11)
+#define LAWAR_SIZE_8M		(LAWAR_SIZE_BASE+12)
+#define LAWAR_SIZE_16M		(LAWAR_SIZE_BASE+13)
+#define LAWAR_SIZE_32M		(LAWAR_SIZE_BASE+14)
+#define LAWAR_SIZE_64M		(LAWAR_SIZE_BASE+15)
+#define LAWAR_SIZE_128M		(LAWAR_SIZE_BASE+16)
+#define LAWAR_SIZE_256M		(LAWAR_SIZE_BASE+17)
+#define LAWAR_SIZE_512M		(LAWAR_SIZE_BASE+18)
+#define LAWAR_SIZE_1G		(LAWAR_SIZE_BASE+19)
+#define LAWAR_SIZE_2G		(LAWAR_SIZE_BASE+20)
+#define LAWAR_SIZE_4G		(LAWAR_SIZE_BASE+21)
+#define LAWAR_SIZE_8G		(LAWAR_SIZE_BASE+22)
+#define LAWAR_SIZE_16G		(LAWAR_SIZE_BASE+23)
+#define LAWAR_SIZE_32G		(LAWAR_SIZE_BASE+24)
+#endif
+
+#endif /* _PPC_MMU_H_ */
diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h
new file mode 100644
index 0000000..8dacd27
--- /dev/null
+++ b/arch/powerpc/include/asm/mp.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_MP_H_
+#define _ASM_MP_H_
+
+#include <lmb.h>
+
+void setup_mp(void);
+void cpu_mp_lmb_reserve(struct lmb *lmb);
+u32 determine_mp_bootpg(unsigned int *pagesize);
+int is_core_disabled(int nr);
+
+#ifdef CONFIG_E6500
+#define thread_to_core(x) (x >> 1)
+#else
+#define thread_to_core(x) (x)
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/mpc8349_pci.h b/arch/powerpc/include/asm/mpc8349_pci.h
new file mode 100644
index 0000000..7a1adba
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc8349_pci.h
@@ -0,0 +1,168 @@
+#ifndef _PPC_KERNEL_MPC8349_PCI_H
+#define _PPC_KERNEL_MPC8349_PCI_H
+
+
+#define M8265_PCIBR0	0x101ac
+#define M8265_PCIBR1	0x101b0
+#define M8265_PCIMSK0	0x101c4
+#define M8265_PCIMSK1	0x101c8
+
+/* Bit definitions for PCIBR registers */
+
+#define PCIBR_ENABLE        0x00000001
+
+/* Bit definitions for PCIMSK registers */
+
+#define PCIMSK_32KB         0xFFFF8000  /* Size of window, smallest */
+#define PCIMSK_64KB         0xFFFF0000
+#define PCIMSK_128KB        0xFFFE0000
+#define PCIMSK_256KB        0xFFFC0000
+#define PCIMSK_512KB        0xFFF80000
+#define PCIMSK_1MB          0xFFF00000
+#define PCIMSK_2MB          0xFFE00000
+#define PCIMSK_4MB          0xFFC00000
+#define PCIMSK_8MB          0xFF800000
+#define PCIMSK_16MB         0xFF000000
+#define PCIMSK_32MB         0xFE000000
+#define PCIMSK_64MB         0xFC000000
+#define PCIMSK_128MB        0xF8000000
+#define PCIMSK_256MB        0xF0000000
+#define PCIMSK_512MB        0xE0000000
+#define PCIMSK_1GB          0xC0000000  /* Size of window, largest */
+
+
+#define M826X_SCCR_PCI_MODE_EN 0x100
+
+
+/*
+ * Outbound ATU registers (3 sets). These registers control how 60x bus
+ * (local) addresses are translated to PCI addresses when the MPC826x is
+ * a PCI bus master (initiator).
+ */
+
+#define POTAR_REG0          0x10800     /* PCI Outbound Translation Addr registers */
+#define POTAR_REG1          0x10818
+#define POTAR_REG2          0x10830
+
+#define POBAR_REG0          0x10808     /* PCI Outbound Base Addr registers */
+#define POBAR_REG1          0x10820
+#define POBAR_REG2          0x10838
+
+#define POCMR_REG0          0x10810     /* PCI Outbound Comparison Mask registers */
+#define POCMR_REG1          0x10828
+#define POCMR_REG2          0x10840
+
+/* Bit definitions for POMCR registers */
+
+#define POCMR_MASK_4KB      0x000FFFFF
+#define POCMR_MASK_8KB      0x000FFFFE
+#define POCMR_MASK_16KB     0x000FFFFC
+#define POCMR_MASK_32KB     0x000FFFF8
+#define POCMR_MASK_64KB     0x000FFFF0
+#define POCMR_MASK_128KB    0x000FFFE0
+#define POCMR_MASK_256KB    0x000FFFC0
+#define POCMR_MASK_512KB    0x000FFF80
+#define POCMR_MASK_1MB      0x000FFF00
+#define POCMR_MASK_2MB      0x000FFE00
+#define POCMR_MASK_4MB      0x000FFC00
+#define POCMR_MASK_8MB      0x000FF800
+#define POCMR_MASK_16MB     0x000FF000
+#define POCMR_MASK_32MB     0x000FE000
+#define POCMR_MASK_64MB     0x000FC000
+#define POCMR_MASK_128MB    0x000F8000
+#define POCMR_MASK_256MB    0x000F0000
+#define POCMR_MASK_512MB    0x000E0000
+#define POCMR_MASK_1GB      0x000C0000
+
+#define POCMR_ENABLE        0x80000000
+#define POCMR_PCI_IO        0x40000000
+#define POCMR_PREFETCH_EN   0x20000000
+#define POCMR_PCI2          0x10000000
+
+/* Soft PCI reset */
+
+#define PCI_GCR_REG         0x10880
+
+/* Bit definitions for PCI_GCR registers */
+
+#define PCIGCR_PCI_BUS_EN   0x1
+
+/*
+ * Inbound ATU registers (2 sets). These registers control how PCI
+ * addresses are translated to 60x bus (local) addresses when the
+ * MPC826x is a PCI bus target.
+ */
+
+#define PITAR_REG1          0x108D0
+#define PIBAR_REG1          0x108D8
+#define PICMR_REG1          0x108E0
+#define PITAR_REG0          0x108E8
+#define PIBAR_REG0          0x108F0
+#define PICMR_REG0          0x108F8
+
+/* Bit definitions for PCI Inbound Comparison Mask registers */
+
+#define PICMR_MASK_4KB       0x000FFFFF
+#define PICMR_MASK_8KB       0x000FFFFE
+#define PICMR_MASK_16KB      0x000FFFFC
+#define PICMR_MASK_32KB      0x000FFFF8
+#define PICMR_MASK_64KB      0x000FFFF0
+#define PICMR_MASK_128KB     0x000FFFE0
+#define PICMR_MASK_256KB     0x000FFFC0
+#define PICMR_MASK_512KB     0x000FFF80
+#define PICMR_MASK_1MB       0x000FFF00
+#define PICMR_MASK_2MB       0x000FFE00
+#define PICMR_MASK_4MB       0x000FFC00
+#define PICMR_MASK_8MB       0x000FF800
+#define PICMR_MASK_16MB      0x000FF000
+#define PICMR_MASK_32MB      0x000FE000
+#define PICMR_MASK_64MB      0x000FC000
+#define PICMR_MASK_128MB     0x000F8000
+#define PICMR_MASK_256MB     0x000F0000
+#define PICMR_MASK_512MB     0x000E0000
+#define PICMR_MASK_1GB       0x000C0000
+
+#define PICMR_ENABLE         0x80000000
+#define PICMR_NO_SNOOP_EN    0x40000000
+#define PICMR_PREFETCH_EN    0x20000000
+
+/* PCI error Registers */
+
+#define	PCI_ERROR_STATUS_REG		0x10884
+#define	PCI_ERROR_MASK_REG		0x10888
+#define	PCI_ERROR_CONTROL_REG		0x1088C
+#define PCI_ERROR_ADRS_CAPTURE_REG      0x10890
+#define PCI_ERROR_DATA_CAPTURE_REG      0x10898
+#define PCI_ERROR_CTRL_CAPTURE_REG      0x108A0
+
+/* PCI error Register bit defines */
+
+#define	PCI_ERROR_PCI_ADDR_PAR			0x00000001
+#define	PCI_ERROR_PCI_DATA_PAR_WR		0x00000002
+#define	PCI_ERROR_PCI_DATA_PAR_RD		0x00000004
+#define	PCI_ERROR_PCI_NO_RSP			0x00000008
+#define	PCI_ERROR_PCI_TAR_ABT			0x00000010
+#define	PCI_ERROR_PCI_SERR			0x00000020
+#define	PCI_ERROR_PCI_PERR_RD			0x00000040
+#define	PCI_ERROR_PCI_PERR_WR			0x00000080
+#define	PCI_ERROR_I2O_OFQO			0x00000100
+#define	PCI_ERROR_I2O_IPQO			0x00000200
+#define	PCI_ERROR_IRA				0x00000400
+#define	PCI_ERROR_NMI				0x00000800
+#define	PCI_ERROR_I2O_DBMC			0x00001000
+
+/*
+ * Register pair used to generate configuration cycles on the PCI bus
+ * and access the MPC826x's own PCI configuration registers.
+ */
+
+#define PCI_CFG_ADDR_REG     0x10900
+#define PCI_CFG_DATA_REG     0x10904
+
+/* Bus parking decides where the bus control sits when idle */
+/* If modifying memory controllers for PCI park on the core */
+
+#define PPC_ACR_BUS_PARK_CORE 0x6
+#define PPC_ACR_BUS_PARK_PCI  0x3
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
new file mode 100644
index 0000000..1b332f0
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010 eXMeritus, A Boeing Company
+ */
+
+#ifndef POWERPC_ASM_MPC85XX_GPIO_H_
+#define POWERPC_ASM_MPC85XX_GPIO_H_
+
+# include <asm/immap_85xx.h>
+
+/*
+ * The following internal functions are an MPC85XX-specific GPIO API which
+ * allows setting and querying multiple GPIOs in a single operation.
+ *
+ * All of these look relatively large, but the arguments are almost always
+ * constants, so they compile down to just a few instructions and a
+ * memory-mapped IO operation or two.
+ */
+static inline void mpc85xx_gpio_set(unsigned int mask,
+		unsigned int dir, unsigned int val)
+{
+	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+
+	/* First mask off the unwanted parts of "dir" and "val" */
+	dir &= mask;
+	val &= mask;
+
+	/* Now read in the values we're supposed to preserve */
+	dir |= (in_be32(&gpio->gpdir) & ~mask);
+	val |= (in_be32(&gpio->gpdat) & ~mask);
+
+	/*
+	 * Poke the new output values first, then set the direction.  This
+	 * helps to avoid transient data when switching from input to output
+	 * and vice versa.
+	 */
+	out_be32(&gpio->gpdat, val);
+	out_be32(&gpio->gpdir, dir);
+}
+
+static inline void mpc85xx_gpio_set_in(unsigned int gpios)
+{
+	mpc85xx_gpio_set(gpios, 0x00000000, 0x00000000);
+}
+
+static inline void mpc85xx_gpio_set_low(unsigned int gpios)
+{
+	mpc85xx_gpio_set(gpios, 0xFFFFFFFF, 0x00000000);
+}
+
+static inline void mpc85xx_gpio_set_high(unsigned int gpios)
+{
+	mpc85xx_gpio_set(gpios, 0xFFFFFFFF, 0xFFFFFFFF);
+}
+
+static inline unsigned int mpc85xx_gpio_get(unsigned int mask)
+{
+	ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+
+	/* Read the requested values */
+	return in_be32(&gpio->gpdat) & mask;
+}
+
+/*
+ * These implement the generic Linux GPIO API on top of the other functions
+ * in this header.
+ */
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+	/* Compatibility shim */
+	return 0;
+}
+
+static inline int gpio_free(unsigned gpio)
+{
+	/* Compatibility shim */
+	return 0;
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+	mpc85xx_gpio_set_in(1U << gpio);
+	return 0;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+	if (value)
+		mpc85xx_gpio_set_high(1U << gpio);
+	else
+		mpc85xx_gpio_set_low(1U << gpio);
+	return 0;
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+	return !!mpc85xx_gpio_get(1U << gpio);
+}
+
+static inline int gpio_set_value(unsigned gpio, int value)
+{
+	if (value)
+		mpc85xx_gpio_set_high(1U << gpio);
+	else
+		mpc85xx_gpio_set_low(1U << gpio);
+	return 0;
+}
+
+static inline int gpio_is_valid(int gpio)
+{
+	return (gpio >= 0) && (gpio < 32);
+}
+
+#endif /* not POWERPC_ASM_MPC85XX_GPIO_H_ */
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
new file mode 100644
index 0000000..b583a32
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Freescale non-CPM SPI Controller
+ *
+ * Copyright 2008 Qstreams Networks, Inc.
+ */
+
+#ifndef _ASM_MPC8XXX_SPI_H_
+#define _ASM_MPC8XXX_SPI_H_
+
+#include <asm/types.h>
+
+#if defined(CONFIG_ARCH_MPC8308) || \
+	defined(CONFIG_ARCH_MPC8313) || \
+	defined(CONFIG_ARCH_MPC8315) || \
+	defined(CONFIG_ARCH_MPC834X) || \
+	defined(CONFIG_ARCH_MPC837X)
+
+typedef struct spi8xxx {
+	u8 res0[0x20];	/* 0x0-0x01f reserved */
+	u32 mode;	/* mode register  */
+	u32 event;	/* event register */
+	u32 mask;	/* mask register  */
+	u32 com;	/* command register */
+	u32 tx;		/* transmit register */
+	u32 rx;		/* receive register */
+	u8 res1[0xFC8];	/* fill up to 0x1000 */
+} spi8xxx_t;
+
+#endif
+
+#endif	/* _ASM_MPC8XXX_SPI_H_ */
diff --git a/arch/powerpc/include/asm/pci_io.h b/arch/powerpc/include/asm/pci_io.h
new file mode 100644
index 0000000..9b738c3
--- /dev/null
+++ b/arch/powerpc/include/asm/pci_io.h
@@ -0,0 +1,43 @@
+/* originally from linux source (asm-ppc/io.h).
+ * Sanity added by Rob Taylor, Flying Pig Systems, 2000
+ */
+#ifndef _PCI_IO_H_
+#define _PCI_IO_H_
+
+#include "io.h"
+
+
+#define pci_read_le16(addr, dest) \
+    __asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \
+		  "r" (addr), "m" (*addr));
+
+#define pci_write_le16(addr, val) \
+    __asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \
+		  "r" (val), "r" (addr));
+
+
+#define pci_read_le32(addr, dest) \
+    __asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \
+		 "r" (addr), "m" (*addr));
+
+#define pci_write_le32(addr, val) \
+__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \
+		 "r" (val), "r" (addr));
+
+#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr))
+#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
+
+#if !defined(__BIG_ENDIAN)
+#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr))
+#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr))
+#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
+#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
+#else
+#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b))
+#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b))
+#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b))
+#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b))
+#endif
+
+
+#endif /* _PCI_IO_H_ */
diff --git a/arch/powerpc/include/asm/posix_types.h b/arch/powerpc/include/asm/posix_types.h
new file mode 100644
index 0000000..9170728
--- /dev/null
+++ b/arch/powerpc/include/asm/posix_types.h
@@ -0,0 +1,109 @@
+#ifndef _PPC_POSIX_TYPES_H
+#define _PPC_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned int	__kernel_dev_t;
+typedef unsigned int	__kernel_ino_t;
+typedef unsigned int	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned int	__kernel_uid_t;
+typedef unsigned int	__kernel_gid_t;
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef long		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef short             __kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned int	__kernel_old_uid_t;
+typedef unsigned int	__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+	int	val[2];
+} __kernel_fsid_t;
+
+#ifndef __GNUC__
+
+#define	__FD_SET(d, set)	((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+#define	__FD_CLR(d, set)	((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+#define	__FD_ISSET(d, set)	((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+#define	__FD_ZERO(set)	\
+  ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
+
+#else /* __GNUC__ */
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
+    || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
+/* With GNU C, use inline functions instead so args are evaluated only once: */
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
+{
+	unsigned long _tmp = fd / __NFDBITS;
+	unsigned long _rem = fd % __NFDBITS;
+	return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *p)
+{
+	unsigned int *tmp = (unsigned int *)p->fds_bits;
+	int i;
+
+	if (__builtin_constant_p(__FDSET_LONGS)) {
+		switch (__FDSET_LONGS) {
+			case 8:
+				tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
+				tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
+				return;
+		}
+	}
+	i = __FDSET_LONGS;
+	while (i) {
+		i--;
+		*tmp = 0;
+		tmp++;
+	}
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* __GNUC__ */
+#endif /* _PPC_POSIX_TYPES_H */
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
new file mode 100644
index 0000000..5765f6b
--- /dev/null
+++ b/arch/powerpc/include/asm/ppc.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Ugly header containing required header files. This could  be adjusted
+ * so that including asm/arch/hardware includes the correct file.
+ *
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __ASM_PPC_H
+#define __ASM_PPC_H
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_MPC8xx)
+#include <asm/immap_8xx.h>
+#endif
+#ifdef CONFIG_MPC86xx
+#include <mpc86xx.h>
+#include <asm/immap_86xx.h>
+#endif
+#ifdef CONFIG_MPC85xx
+#include <mpc85xx.h>
+#include <asm/immap_85xx.h>
+#endif
+#ifdef CONFIG_MPC83xx
+#include <mpc83xx.h>
+#include <asm/immap_83xx.h>
+#endif
+#ifdef CONFIG_SOC_DA8XX
+#include <asm/arch/hardware.h>
+#endif
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/immap_lsch3.h>
+#endif
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#endif
+
+#include <asm/processor.h>
+
+static inline uint get_immr(void)
+{
+	return mfspr(SPRN_IMMR);
+}
+
+static inline uint get_pvr(void)
+{
+	return mfspr(PVR);
+}
+
+static inline uint get_svr(void)
+{
+	return mfspr(SVR);
+}
+
+#if defined(CONFIG_MPC85xx)	|| \
+	defined(CONFIG_MPC86xx)	|| \
+	defined(CONFIG_MPC83xx)
+unsigned char	in8(unsigned int);
+void		out8(unsigned int, unsigned char);
+unsigned short	in16(unsigned int);
+unsigned short	in16r(unsigned int);
+void		out16(unsigned int, unsigned short value);
+void		out16r(unsigned int, unsigned short value);
+unsigned long	in32(unsigned int);
+unsigned long	in32r(unsigned int);
+void		out32(unsigned int, unsigned long value);
+void		out32r(unsigned int, unsigned long value);
+void		ppcDcbf(unsigned long value);
+void		ppcDcbi(unsigned long value);
+void		ppcSync(void);
+void		ppcDcbz(unsigned long value);
+#endif
+#if defined(CONFIG_MPC83xx)
+void		ppcDWload(unsigned int *addr, unsigned int *ret);
+void		ppcDWstore(unsigned int *addr, unsigned int *value);
+void disable_addr_trans(void);
+void enable_addr_trans(void);
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+#endif
+
+#if defined(CONFIG_MPC85xx)
+typedef MPC85xx_SYS_INFO sys_info_t;
+void get_sys_info(sys_info_t *);
+void ft_fixup_cpu(void *, u64);
+void ft_fixup_num_cores(void *);
+#endif
+#if defined(CONFIG_MPC86xx)
+ulong get_bus_freq(ulong);
+typedef MPC86xx_SYS_INFO sys_info_t;
+void   get_sys_info(sys_info_t *);
+static inline ulong get_ddr_freq(ulong dummy)
+{
+	return get_bus_freq(dummy);
+}
+#else
+ulong get_ddr_freq(ulong);
+#endif
+
+static inline unsigned long get_msr(void)
+{
+	unsigned long msr;
+
+	asm volatile ("mfmsr %0" : "=r" (msr) : );
+
+	return msr;
+}
+
+static inline void set_msr(unsigned long msr)
+{
+	asm volatile ("mtmsr %0" : : "r" (msr));
+}
+
+#ifdef CONFIG_CMD_REGINFO
+void print_reginfo(void);
+#endif
+
+void interrupt_init_cpu(unsigned *);
+void timer_interrupt_cpu(struct pt_regs *);
+unsigned long search_exception_table(unsigned long addr);
+
+#endif /* !__ASSEMBLY__ */
+
+#ifdef CONFIG_PPC
+/*
+ * Has to be included outside of the #ifndef __ASSEMBLY__ section.
+ * Otherwise might lead to compilation errors in assembler files.
+ */
+#include <asm/cache.h>
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
new file mode 100644
index 0000000..e03ab21
--- /dev/null
+++ b/arch/powerpc/include/asm/processor.h
@@ -0,0 +1,1220 @@
+#ifndef __ASM_PPC_PROCESSOR_H
+#define __ASM_PPC_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+
+/* Machine State Register (MSR) Fields */
+
+#ifdef CONFIG_PPC64BRIDGE
+#define MSR_SF		(1<<63)
+#define MSR_ISF		(1<<61)
+#endif /* CONFIG_PPC64BRIDGE */
+#define MSR_UCLE	(1<<26)		/* User-mode cache lock enable (e500) */
+#define MSR_VEC		(1<<25)		/* Enable AltiVec(74xx) */
+#define MSR_SPE		(1<<25)		/* Enable SPE(e500) */
+#define MSR_POW		(1<<18)		/* Enable Power Management */
+#define MSR_WE		(1<<18)		/* Wait State Enable */
+#define MSR_TGPR	(1<<17)		/* TLB Update registers in use */
+#define MSR_CE		(1<<17)		/* Critical Interrupt Enable */
+#define MSR_ILE		(1<<16)		/* Interrupt Little Endian */
+#define MSR_EE		(1<<15)		/* External Interrupt Enable */
+#define MSR_PR		(1<<14)		/* Problem State / Privilege Level */
+#define MSR_FP		(1<<13)		/* Floating Point enable */
+#define MSR_ME		(1<<12)		/* Machine Check Enable */
+#define MSR_FE0		(1<<11)		/* Floating Exception mode 0 */
+#define MSR_SE		(1<<10)		/* Single Step */
+#define MSR_DWE		(1<<10)		/* Debug Wait Enable (4xx) */
+#define MSR_UBLE	(1<<10)		/* BTB lock enable (e500) */
+#define MSR_BE		(1<<9)		/* Branch Trace */
+#define MSR_DE		(1<<9)		/* Debug Exception Enable */
+#define MSR_FE1		(1<<8)		/* Floating Exception mode 1 */
+#define MSR_IP		(1<<6)		/* Exception prefix 0x000/0xFFF */
+#define MSR_IR		(1<<5)		/* Instruction Relocate */
+#define MSR_IS		(1<<5)		/* Book E Instruction space */
+#define MSR_DR		(1<<4)		/* Data Relocate */
+#define MSR_DS		(1<<4)		/* Book E Data space */
+#define MSR_PE		(1<<3)		/* Protection Enable */
+#define MSR_PX		(1<<2)		/* Protection Exclusive Mode */
+#define MSR_PMM		(1<<2)		/* Performance monitor mark bit (e500) */
+#define MSR_RI		(1<<1)		/* Recoverable Exception */
+#define MSR_LE		(1<<0)		/* Little Endian */
+
+#ifdef CONFIG_APUS_FAST_EXCEPT
+#define MSR_		MSR_ME|MSR_IP|MSR_RI
+#else
+#define MSR_		MSR_ME|MSR_RI
+#endif
+#ifndef CONFIG_E500
+#define MSR_KERNEL	MSR_|MSR_IR|MSR_DR
+#else
+#define MSR_KERNEL	MSR_ME
+#endif
+
+/* Floating Point Status and Control Register (FPSCR) Fields */
+
+#define FPSCR_FX	0x80000000	/* FPU exception summary */
+#define FPSCR_FEX	0x40000000	/* FPU enabled exception summary */
+#define FPSCR_VX	0x20000000	/* Invalid operation summary */
+#define FPSCR_OX	0x10000000	/* Overflow exception summary */
+#define FPSCR_UX	0x08000000	/* Underflow exception summary */
+#define FPSCR_ZX	0x04000000	/* Zero-devide exception summary */
+#define FPSCR_XX	0x02000000	/* Inexact exception summary */
+#define FPSCR_VXSNAN	0x01000000	/* Invalid op for SNaN */
+#define FPSCR_VXISI	0x00800000	/* Invalid op for Inv - Inv */
+#define FPSCR_VXIDI	0x00400000	/* Invalid op for Inv / Inv */
+#define FPSCR_VXZDZ	0x00200000	/* Invalid op for Zero / Zero */
+#define FPSCR_VXIMZ	0x00100000	/* Invalid op for Inv * Zero */
+#define FPSCR_VXVC	0x00080000	/* Invalid op for Compare */
+#define FPSCR_FR	0x00040000	/* Fraction rounded */
+#define FPSCR_FI	0x00020000	/* Fraction inexact */
+#define FPSCR_FPRF	0x0001f000	/* FPU Result Flags */
+#define FPSCR_FPCC	0x0000f000	/* FPU Condition Codes */
+#define FPSCR_VXSOFT	0x00000400	/* Invalid op for software request */
+#define FPSCR_VXSQRT	0x00000200	/* Invalid op for square root */
+#define FPSCR_VXCVI	0x00000100	/* Invalid op for integer convert */
+#define FPSCR_VE	0x00000080	/* Invalid op exception enable */
+#define FPSCR_OE	0x00000040	/* IEEE overflow exception enable */
+#define FPSCR_UE	0x00000020	/* IEEE underflow exception enable */
+#define FPSCR_ZE	0x00000010	/* IEEE zero divide exception enable */
+#define FPSCR_XE	0x00000008	/* FP inexact exception enable */
+#define FPSCR_NI	0x00000004	/* FPU non IEEE-Mode */
+#define FPSCR_RN	0x00000003	/* FPU rounding control */
+
+/* Special Purpose Registers (SPRNs)*/
+
+#define SPRN_CCR0	0x3B3	/* Core Configuration Register 0 */
+#ifdef CONFIG_BOOKE
+#define SPRN_CCR1	0x378	/* Core Configuration Register for 440 only */
+#endif
+#define SPRN_CDBCR	0x3D7	/* Cache Debug Control Register */
+#define SPRN_CTR	0x009	/* Count Register */
+#define SPRN_DABR	0x3F5	/* Data Address Breakpoint Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_DAC1	0x3F6	/* Data Address Compare 1 */
+#define SPRN_DAC2	0x3F7	/* Data Address Compare 2 */
+#else
+#define SPRN_DAC1	0x13C	/* Book E Data Address Compare 1 */
+#define SPRN_DAC2	0x13D	/* Book E Data Address Compare 2 */
+#endif	/* CONFIG_BOOKE */
+#define SPRN_DAR	0x013	/* Data Address Register */
+#define SPRN_DBAT0L	0x219	/* Data BAT 0 Lower Register */
+#define SPRN_DBAT0U	0x218	/* Data BAT 0 Upper Register */
+#define SPRN_DBAT1L	0x21B	/* Data BAT 1 Lower Register */
+#define SPRN_DBAT1U	0x21A	/* Data BAT 1 Upper Register */
+#define SPRN_DBAT2L	0x21D	/* Data BAT 2 Lower Register */
+#define SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
+#define SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
+#define SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
+#define SPRN_DBAT4L	0x239	/* Data BAT 4 Lower Register */
+#define SPRN_DBAT4U	0x238	/* Data BAT 4 Upper Register */
+#define SPRN_DBAT5L	0x23B	/* Data BAT 5 Lower Register */
+#define SPRN_DBAT5U	0x23A	/* Data BAT 5 Upper Register */
+#define SPRN_DBAT6L	0x23D	/* Data BAT 6 Lower Register */
+#define SPRN_DBAT6U	0x23C	/* Data BAT 6 Upper Register */
+#define SPRN_DBAT7L	0x23F	/* Data BAT 7 Lower Register */
+#define SPRN_DBAT7U	0x23E	/* Data BAT 7 Lower Register */
+#define SPRN_DBCR	0x3F2	/* Debug Control Regsiter */
+#define   DBCR_EDM	0x80000000
+#define   DBCR_IDM	0x40000000
+#define   DBCR_RST(x)	(((x) & 0x3) << 28)
+#define     DBCR_RST_NONE		0
+#define     DBCR_RST_CORE		1
+#define     DBCR_RST_CHIP		2
+#define     DBCR_RST_SYSTEM		3
+#define   DBCR_IC	0x08000000	/* Instruction Completion Debug Evnt */
+#define   DBCR_BT	0x04000000	/* Branch Taken Debug Event */
+#define   DBCR_EDE	0x02000000	/* Exception Debug Event */
+#define   DBCR_TDE	0x01000000	/* TRAP Debug Event */
+#define   DBCR_FER	0x00F80000	/* First Events Remaining Mask */
+#define   DBCR_FT	0x00040000	/* Freeze Timers on Debug Event */
+#define   DBCR_IA1	0x00020000	/* Instr. Addr. Compare 1 Enable */
+#define   DBCR_IA2	0x00010000	/* Instr. Addr. Compare 2 Enable */
+#define   DBCR_D1R	0x00008000	/* Data Addr. Compare 1 Read Enable */
+#define   DBCR_D1W	0x00004000	/* Data Addr. Compare 1 Write Enable */
+#define   DBCR_D1S(x)	(((x) & 0x3) << 12)	/* Data Adrr. Compare 1 Size */
+#define     DAC_BYTE	0
+#define     DAC_HALF	1
+#define     DAC_WORD	2
+#define     DAC_QUAD	3
+#define   DBCR_D2R	0x00000800	/* Data Addr. Compare 2 Read Enable */
+#define   DBCR_D2W	0x00000400	/* Data Addr. Compare 2 Write Enable */
+#define   DBCR_D2S(x)	(((x) & 0x3) << 8)	/* Data Addr. Compare 2 Size */
+#define   DBCR_SBT	0x00000040	/* Second Branch Taken Debug Event */
+#define   DBCR_SED	0x00000020	/* Second Exception Debug Event */
+#define   DBCR_STD	0x00000010	/* Second Trap Debug Event */
+#define   DBCR_SIA	0x00000008	/* Second IAC Enable */
+#define   DBCR_SDA	0x00000004	/* Second DAC Enable */
+#define   DBCR_JOI	0x00000002	/* JTAG Serial Outbound Int. Enable */
+#define   DBCR_JII	0x00000001	/* JTAG Serial Inbound Int. Enable */
+#ifndef CONFIG_BOOKE
+#define SPRN_DBCR0	0x3F2		/* Debug Control Register 0 */
+#else
+#define SPRN_DBCR0	0x134		/* Book E Debug Control Register 0 */
+#endif /* CONFIG_BOOKE */
+#ifndef CONFIG_BOOKE
+#define SPRN_DBCR1	0x3BD	/* Debug Control Register 1 */
+#define SPRN_DBSR	0x3F0	/* Debug Status Register */
+#else
+#define SPRN_DBCR1	0x135		/* Book E Debug Control Register 1 */
+#ifdef CONFIG_BOOKE
+#define	SPRN_DBDR	0x3f3		/* Debug Data Register */
+#endif
+#define SPRN_DBSR	0x130		/* Book E Debug Status Register */
+#define   DBSR_IC	    0x08000000	/* Book E Instruction Completion  */
+#define   DBSR_TIE	    0x01000000	/* Book E Trap Instruction Event */
+#endif /* CONFIG_BOOKE */
+#define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
+#define   DCCR_NOCACHE		0	/* Noncacheable */
+#define   DCCR_CACHE		1	/* Cacheable */
+#ifndef CONFIG_BOOKE
+#define	SPRN_DCDBTRL	0x39c	/* Data Cache Debug Tag Register Low */
+#define	SPRN_DCDBTRH	0x39d	/* Data Cache Debug Tag Register High */
+#endif
+#define SPRN_DCMP	0x3D1	/* Data TLB Compare Register */
+#define SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */
+#define   DCWR_COPY		0	/* Copy-back */
+#define   DCWR_WRITE		1	/* Write-through */
+#ifndef CONFIG_BOOKE
+#define SPRN_DEAR	0x3D5	/* Data Error Address Register */
+#else
+#define SPRN_DEAR	0x03D	/* Book E Data Error Address Register */
+#endif /* CONFIG_BOOKE */
+#define SPRN_DEC	0x016	/* Decrement Register */
+#define SPRN_DMISS	0x3D0	/* Data TLB Miss Register */
+#ifdef CONFIG_BOOKE
+#define	SPRN_DNV0	0x390	/* Data Cache Normal Victim 0 */
+#define	SPRN_DNV1	0x391	/* Data Cache Normal Victim 1 */
+#define	SPRN_DNV2	0x392	/* Data Cache Normal Victim 2 */
+#define	SPRN_DNV3	0x393	/* Data Cache Normal Victim 3 */
+#endif
+#define SPRN_DSISR	0x012	/* Data Storage Interrupt Status Register */
+#ifdef CONFIG_BOOKE
+#define	SPRN_DTV0	0x394	/* Data Cache Transient Victim 0 */
+#define	SPRN_DTV1	0x395	/* Data Cache Transient Victim 1 */
+#define	SPRN_DTV2	0x396	/* Data Cache Transient Victim 2 */
+#define	SPRN_DTV3	0x397	/* Data Cache Transient Victim 3 */
+#define	SPRN_DVLIM	0x398	/* Data Cache Victim Limit */
+#endif
+#define SPRN_EAR	0x11A	/* External Address Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_ESR	0x3D4	/* Exception Syndrome Register */
+#else
+#define SPRN_ESR	0x03E		/* Book E Exception Syndrome Register */
+#endif /* CONFIG_BOOKE */
+#define   ESR_IMCP	0x80000000	/* Instr. Machine Check - Protection */
+#define   ESR_IMCN	0x40000000	/* Instr. Machine Check - Non-config */
+#define   ESR_IMCB	0x20000000	/* Instr. Machine Check - Bus error */
+#define   ESR_IMCT	0x10000000	/* Instr. Machine Check - Timeout */
+#define   ESR_PIL	0x08000000	/* Program Exception - Illegal */
+#define   ESR_PPR	0x04000000	/* Program Exception - Priveleged */
+#define   ESR_PTR	0x02000000	/* Program Exception - Trap */
+#define   ESR_DST	0x00800000	/* Storage Exception - Data miss */
+#define   ESR_DIZ	0x00400000	/* Storage Exception - Zone fault */
+#define SPRN_EVPR	0x3D6	/* Exception Vector Prefix Register */
+#define SPRN_HASH1	0x3D2	/* Primary Hash Address Register */
+#define SPRN_HASH2	0x3D3	/* Secondary Hash Address Resgister */
+#define SPRN_HID0	0x3F0	/* Hardware Implementation Register 0 */
+
+#define HID0_ICE_SHIFT		15
+#define HID0_DCE_SHIFT		14
+#define HID0_DLOCK_SHIFT	12
+
+#define   HID0_EMCP	(1<<31)		/* Enable Machine Check pin */
+#define   HID0_EBA	(1<<29)		/* Enable Bus Address Parity */
+#define   HID0_EBD	(1<<28)		/* Enable Bus Data Parity */
+#define   HID0_SBCLK	(1<<27)
+#define   HID0_EICE	(1<<26)
+#define   HID0_ECLK	(1<<25)
+#define   HID0_PAR	(1<<24)
+#define   HID0_DOZE	(1<<23)
+#define   HID0_NAP	(1<<22)
+#define   HID0_SLEEP	(1<<21)
+#define   HID0_DPM	(1<<20)
+#define   HID0_ICE	(1<<HID0_ICE_SHIFT)	/* Instruction Cache Enable */
+#define   HID0_DCE	(1<<HID0_DCE_SHIFT)	/* Data Cache Enable */
+#define   HID0_TBEN	(1<<14)		/* Time Base Enable */
+#define   HID0_ILOCK	(1<<13)		/* Instruction Cache Lock */
+#define   HID0_DLOCK	(1<<HID0_DLOCK_SHIFT)	/* Data Cache Lock */
+#define   HID0_ICFI	(1<<11)		/* Instr. Cache Flash Invalidate */
+#define   HID0_DCFI	(1<<10)		/* Data Cache Flash Invalidate */
+#define   HID0_DCI	HID0_DCFI
+#define   HID0_SPD	(1<<9)		/* Speculative disable */
+#define   HID0_ENMAS7	(1<<7)		/* Enable MAS7 Update for 36-bit phys */
+#define   HID0_SGE	(1<<7)		/* Store Gathering Enable */
+#define   HID0_SIED	HID_SGE		/* Serial Instr. Execution [Disable] */
+#define   HID0_DCFA	(1<<6)		/* Data Cache Flush Assist */
+#define   HID0_BTIC	(1<<5)		/* Branch Target Instruction Cache Enable */
+#define   HID0_ABE	(1<<3)		/* Address Broadcast Enable */
+#define   HID0_BHTE	(1<<2)		/* Branch History Table Enable */
+#define   HID0_BTCD	(1<<1)		/* Branch target cache disable */
+#define SPRN_HID1	0x3F1	/* Hardware Implementation Register 1 */
+#define	  HID1_RFXE	(1<<17)		/* Read Fault Exception Enable */
+#define	  HID1_ASTME	(1<<13)		/* Address bus streaming mode */
+#define	  HID1_ABE	(1<<12)		/* Address broadcast enable */
+#define	  HID1_MBDD	(1<<6)		/* optimized sync instruction */
+#define SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_IAC1	0x3F4	/* Instruction Address Compare 1 */
+#define SPRN_IAC2	0x3F5	/* Instruction Address Compare 2 */
+#else
+#define SPRN_IAC1	0x138	/* Book E Instruction Address Compare 1 */
+#define SPRN_IAC2	0x139	/* Book E Instruction Address Compare 2 */
+#endif /* CONFIG_BOOKE */
+#define SPRN_IBAT0L	0x211	/* Instruction BAT 0 Lower Register */
+#define SPRN_IBAT0U	0x210	/* Instruction BAT 0 Upper Register */
+#define SPRN_IBAT1L	0x213	/* Instruction BAT 1 Lower Register */
+#define SPRN_IBAT1U	0x212	/* Instruction BAT 1 Upper Register */
+#define SPRN_IBAT2L	0x215	/* Instruction BAT 2 Lower Register */
+#define SPRN_IBAT2U	0x214	/* Instruction BAT 2 Upper Register */
+#define SPRN_IBAT3L	0x217	/* Instruction BAT 3 Lower Register */
+#define SPRN_IBAT3U	0x216	/* Instruction BAT 3 Upper Register */
+#define SPRN_IBAT4L	0x231	/* Instruction BAT 4 Lower Register */
+#define SPRN_IBAT4U	0x230	/* Instruction BAT 4 Upper Register */
+#define SPRN_IBAT5L	0x233	/* Instruction BAT 5 Lower Register */
+#define SPRN_IBAT5U	0x232	/* Instruction BAT 5 Upper Register */
+#define SPRN_IBAT6L	0x235	/* Instruction BAT 6 Lower Register */
+#define SPRN_IBAT6U	0x234	/* Instruction BAT 6 Upper Register */
+#define SPRN_IBAT7L	0x237	/* Instruction BAT 7 Lower Register */
+#define SPRN_IBAT7U	0x236	/* Instruction BAT 7 Upper Register */
+#define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
+#define   ICCR_NOCACHE		0	/* Noncacheable */
+#define   ICCR_CACHE		1	/* Cacheable */
+#define SPRN_ICDBDR	0x3D3	/* Instruction Cache Debug Data Register */
+#ifdef CONFIG_BOOKE
+#define SPRN_ICDBTRL	0x39e	/* instruction cache debug tag register low */
+#define	SPRN_ICDBTRH	0x39f	/* instruction cache debug tag register high */
+#endif
+#define SPRN_ICMP	0x3D5	/* Instruction TLB Compare Register */
+#define SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */
+#define SPRN_IMISS	0x3D4	/* Instruction TLB Miss Register */
+#define SPRN_IMMR	0x27E	/* Internal Memory Map Register */
+#ifdef CONFIG_BOOKE
+#define	SPRN_INV0	0x370	/* Instruction Cache Normal Victim 0 */
+#define	SPRN_INV1	0x371	/* Instruction Cache Normal Victim 1 */
+#define	SPRN_INV2	0x372	/* Instruction Cache Normal Victim 2 */
+#define	SPRN_INV3	0x373	/* Instruction Cache Normal Victim 3 */
+#define	SPRN_ITV0	0x374	/* Instruction Cache Transient Victim 0 */
+#define	SPRN_ITV1	0x375	/* Instruction Cache Transient Victim 1 */
+#define	SPRN_ITV2	0x376	/* Instruction Cache Transient Victim 2 */
+#define	SPRN_ITV3	0x377	/* Instruction Cache Transient Victim 3 */
+#define	SPRN_IVLIM	0x399	/* Instruction Cache Victim Limit */
+#endif
+#define SPRN_LDSTCR	0x3F8	/* Load/Store Control Register */
+#define SPRN_L2CR	0x3F9	/* Level 2 Cache Control Regsiter */
+#define SPRN_LR		0x008	/* Link Register */
+#define SPRN_MBAR	0x137	/* System memory base address */
+#define SPRN_MMCR0	0x3B8	/* Monitor Mode Control Register 0 */
+#define SPRN_MMCR1	0x3BC	/* Monitor Mode Control Register 1 */
+#ifdef CONFIG_BOOKE
+#define	SPRN_MMUCR	0x3b2	/* MMU Control Register */
+#endif
+#define SPRN_PBL1	0x3FC	/* Protection Bound Lower 1 */
+#define SPRN_PBL2	0x3FE	/* Protection Bound Lower 2 */
+#define SPRN_PBU1	0x3FD	/* Protection Bound Upper 1 */
+#define SPRN_PBU2	0x3FF	/* Protection Bound Upper 2 */
+#ifndef CONFIG_BOOKE
+#define SPRN_PID	0x3B1	/* Process ID */
+#define SPRN_PIR	0x3FF	/* Processor Identification Register */
+#else
+#define SPRN_PID	0x030	/* Book E Process ID */
+#define SPRN_PIR	0x11E	/* Book E Processor Identification Register */
+#endif /* CONFIG_BOOKE */
+#define SPRN_PIT	0x3DB	/* Programmable Interval Timer */
+#define SPRN_PMC1	0x3B9	/* Performance Counter Register 1 */
+#define SPRN_PMC2	0x3BA	/* Performance Counter Register 2 */
+#define SPRN_PMC3	0x3BD	/* Performance Counter Register 3 */
+#define SPRN_PMC4	0x3BE	/* Performance Counter Register 4 */
+#define SPRN_PVR	0x11F	/* Processor Version Register */
+#define SPRN_RPA	0x3D6	/* Required Physical Address Register */
+#ifdef CONFIG_BOOKE
+#define	SPRN_RSTCFG	0x39b	/* Reset Configuration */
+#endif
+#define SPRN_SDA	0x3BF	/* Sampled Data Address Register */
+#define SPRN_SDR1	0x019	/* MMU Hash Base Register */
+#define SPRN_SGR	0x3B9	/* Storage Guarded Register */
+#define   SGR_NORMAL		0
+#define   SGR_GUARDED		1
+#define SPRN_SIA	0x3BB	/* Sampled Instruction Address Register */
+#define SPRN_SPRG0	0x110	/* Special Purpose Register General 0 */
+#define SPRN_SPRG1	0x111	/* Special Purpose Register General 1 */
+#define SPRN_SPRG2	0x112	/* Special Purpose Register General 2 */
+#define SPRN_SPRG3	0x113	/* Special Purpose Register General 3 */
+#define SPRN_SPRG4	0x114	/* Special Purpose Register General 4 */
+#define SPRN_SPRG5	0x115	/* Special Purpose Register General 5 */
+#define SPRN_SPRG6	0x116	/* Special Purpose Register General 6 */
+#define SPRN_SPRG7	0x117	/* Special Purpose Register General 7 */
+#define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
+#define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
+#define SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
+#define SPRN_SRR3	0x3DF	/* Save/Restore Register 3 */
+
+#ifdef CONFIG_BOOKE
+#define SPRN_SVR	0x3FF	/* System Version Register */
+#else
+#define SPRN_SVR	0x11E	/* System Version Register */
+#endif
+#define SPRN_TBHI	0x3DC	/* Time Base High */
+#define SPRN_TBHU	0x3CC	/* Time Base High User-mode */
+#define SPRN_TBLO	0x3DD	/* Time Base Low */
+#define SPRN_TBLU	0x3CD	/* Time Base Low User-mode */
+#define SPRN_TBRL	0x10C	/* Time Base Read Lower Register */
+#define SPRN_TBRU	0x10D	/* Time Base Read Upper Register */
+#define SPRN_TBWL	0x11C	/* Time Base Write Lower Register */
+#define SPRN_TBWU	0x11D	/* Time Base Write Upper Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_TCR	0x3DA	/* Timer Control Register */
+#else
+#define SPRN_TCR	0x154	/* Book E Timer Control Register */
+#endif /* CONFIG_BOOKE */
+#ifdef CONFIG_E500MC
+#define  TCR_WP(x)		(((64-x)&0x3)<<30)| \
+				(((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/
+#else
+#define   TCR_WP(x)		(((x)&0x3)<<30)	/* WDT Period */
+#define     WP_2_17		0		/* 2^17 clocks */
+#define     WP_2_21		1		/* 2^21 clocks */
+#define     WP_2_25		2		/* 2^25 clocks */
+#define     WP_2_29		3		/* 2^29 clocks */
+#endif /* CONFIG_E500 */
+#define   TCR_WRC(x)		(((x)&0x3)<<28)	/* WDT Reset Control */
+#define     WRC_NONE		0		/* No reset will occur */
+#define     WRC_CORE		1		/* Core reset will occur */
+#define     WRC_CHIP		2		/* Chip reset will occur */
+#define     WRC_SYSTEM		3		/* System reset will occur */
+#define   TCR_WIE		0x08000000	/* WDT Interrupt Enable */
+#define   TCR_PIE		0x04000000	/* PIT Interrupt Enable */
+#define   TCR_FP(x)		(((x)&0x3)<<24)	/* FIT Period */
+#define     FP_2_9		0		/* 2^9 clocks */
+#define     FP_2_13		1		/* 2^13 clocks */
+#define     FP_2_17		2		/* 2^17 clocks */
+#define     FP_2_21		3		/* 2^21 clocks */
+#define   TCR_FIE		0x00800000	/* FIT Interrupt Enable */
+#define   TCR_ARE		0x00400000	/* Auto Reload Enable */
+#define SPRN_THRM1	0x3FC	/* Thermal Management Register 1 */
+#define   THRM1_TIN		(1<<0)
+#define   THRM1_TIV		(1<<1)
+#define   THRM1_THRES		(0x7f<<2)
+#define   THRM1_TID		(1<<29)
+#define   THRM1_TIE		(1<<30)
+#define   THRM1_V		(1<<31)
+#define SPRN_THRM2	0x3FD	/* Thermal Management Register 2 */
+#define SPRN_THRM3	0x3FE	/* Thermal Management Register 3 */
+#define   THRM3_E		(1<<31)
+#define SPRN_TLBMISS	0x3D4	/* 980 7450 TLB Miss Register */
+#ifndef CONFIG_BOOKE
+#define SPRN_TSR	0x3D8	/* Timer Status Register */
+#else
+#define SPRN_TSR	0x150	/* Book E Timer Status Register */
+#endif /* CONFIG_BOOKE */
+#define   TSR_ENW		0x80000000	/* Enable Next Watchdog */
+#define   TSR_WIS		0x40000000	/* WDT Interrupt Status */
+#define   TSR_WRS(x)		(((x)&0x3)<<28)	/* WDT Reset Status */
+#define     WRS_NONE		0		/* No WDT reset occurred */
+#define     WRS_CORE		1		/* WDT forced core reset */
+#define     WRS_CHIP		2		/* WDT forced chip reset */
+#define     WRS_SYSTEM		3		/* WDT forced system reset */
+#define   TSR_PIS		0x08000000	/* PIT Interrupt Status */
+#define   TSR_FIS		0x04000000	/* FIT Interrupt Status */
+#define SPRN_UMMCR0	0x3A8	/* User Monitor Mode Control Register 0 */
+#define SPRN_UMMCR1	0x3AC	/* User Monitor Mode Control Register 0 */
+#define SPRN_UPMC1	0x3A9	/* User Performance Counter Register 1 */
+#define SPRN_UPMC2	0x3AA	/* User Performance Counter Register 2 */
+#define SPRN_UPMC3	0x3AD	/* User Performance Counter Register 3 */
+#define SPRN_UPMC4	0x3AE	/* User Performance Counter Register 4 */
+#define SPRN_USIA	0x3AB	/* User Sampled Instruction Address Register */
+#define SPRN_XER	0x001	/* Fixed Point Exception Register */
+#define SPRN_ZPR	0x3B0	/* Zone Protection Register */
+
+/* Book E definitions */
+#define SPRN_DECAR	0x036	/* Decrementer Auto Reload Register */
+#define SPRN_CSRR0	0x03A	/* Critical SRR0 */
+#define SPRN_CSRR1	0x03B	/* Critical SRR0 */
+#define SPRN_IVPR	0x03F	/* Interrupt Vector Prefix Register */
+#define SPRN_USPRG0	0x100	/* User Special Purpose Register General 0 */
+#define SPRN_SPRG4R	0x104	/* Special Purpose Register General 4 Read */
+#define SPRN_SPRG5R	0x105	/* Special Purpose Register General 5 Read */
+#define SPRN_SPRG6R	0x106	/* Special Purpose Register General 6 Read */
+#define SPRN_SPRG7R	0x107	/* Special Purpose Register General 7 Read */
+#define SPRN_SPRG4W	0x114	/* Special Purpose Register General 4 Write */
+#define SPRN_SPRG5W	0x115	/* Special Purpose Register General 5 Write */
+#define SPRN_SPRG6W	0x116	/* Special Purpose Register General 6 Write */
+#define SPRN_SPRG7W	0x117	/* Special Purpose Register General 7 Write */
+#define SPRN_DBCR2	0x136	/* Debug Control Register 2 */
+#define SPRN_IAC3	0x13A	/* Instruction Address Compare 3 */
+#define SPRN_IAC4	0x13B	/* Instruction Address Compare 4 */
+#define SPRN_DVC1	0x13E	/* Data Value Compare Register 1 */
+#define SPRN_DVC2	0x13F	/* Data Value Compare Register 2 */
+#define SPRN_IVOR0	0x190	/* Interrupt Vector Offset Register 0 */
+#define SPRN_IVOR1	0x191	/* Interrupt Vector Offset Register 1 */
+#define SPRN_IVOR2	0x192	/* Interrupt Vector Offset Register 2 */
+#define SPRN_IVOR3	0x193	/* Interrupt Vector Offset Register 3 */
+#define SPRN_IVOR4	0x194	/* Interrupt Vector Offset Register 4 */
+#define SPRN_IVOR5	0x195	/* Interrupt Vector Offset Register 5 */
+#define SPRN_IVOR6	0x196	/* Interrupt Vector Offset Register 6 */
+#define SPRN_IVOR7	0x197	/* Interrupt Vector Offset Register 7 */
+#define SPRN_IVOR8	0x198	/* Interrupt Vector Offset Register 8 */
+#define SPRN_IVOR9	0x199	/* Interrupt Vector Offset Register 9 */
+#define SPRN_IVOR10	0x19a	/* Interrupt Vector Offset Register 10 */
+#define SPRN_IVOR11	0x19b	/* Interrupt Vector Offset Register 11 */
+#define SPRN_IVOR12	0x19c	/* Interrupt Vector Offset Register 12 */
+#define SPRN_IVOR13	0x19d	/* Interrupt Vector Offset Register 13 */
+#define SPRN_IVOR14	0x19e	/* Interrupt Vector Offset Register 14 */
+#define SPRN_IVOR15	0x19f	/* Interrupt Vector Offset Register 15 */
+#define SPRN_IVOR38	0x1b0	/* Interrupt Vector Offset Register 38 */
+#define SPRN_IVOR39	0x1b1	/* Interrupt Vector Offset Register 39 */
+#define SPRN_IVOR40	0x1b2	/* Interrupt Vector Offset Register 40 */
+#define SPRN_IVOR41	0x1b3	/* Interrupt Vector Offset Register 41 */
+#define SPRN_GIVOR2	0x1b8	/* Guest Interrupt Vector Offset Register 2 */
+#define SPRN_GIVOR3	0x1b9	/* Guest Interrupt Vector Offset Register 3 */
+#define SPRN_GIVOR4	0x1ba	/* Guest Interrupt Vector Offset Register 4 */
+#define SPRN_GIVOR8	0x1bb	/* Guest Interrupt Vector Offset Register 8 */
+#define SPRN_GIVOR13	0x1bc	/* Guest Interrupt Vector Offset Register 13 */
+#define SPRN_GIVOR14	0x1bd	/* Guest Interrupt Vector Offset Register 14 */
+
+/* e500 definitions */
+#define SPRN_L1CFG0	0x203	/* L1 Cache Configuration Register 0 */
+#define SPRN_L1CFG1	0x204	/* L1 Cache Configuration Register 1 */
+#define SPRN_L2CFG0	0x207	/* L2 Cache Configuration Register 0 */
+#define SPRN_L1CSR0	0x3f2	/* L1 Data Cache Control and Status Register 0 */
+#define   L1CSR0_CPE		0x00010000	/* Data Cache Parity Enable */
+#define   L1CSR0_CUL		0x00000400	/* (D-)Cache Unable to Lock */
+#define   L1CSR0_DCLFR		0x00000100	/* D-Cache Lock Flash Reset */
+#define   L1CSR0_DCFI		0x00000002	/* Data Cache Flash Invalidate */
+#define   L1CSR0_DCE		0x00000001	/* Data Cache Enable */
+#define SPRN_L1CSR1	0x3f3	/* L1 Instruction Cache Control and Status Register 1 */
+#define   L1CSR1_CPE		0x00010000	/* Instruction Cache Parity Enable */
+#define   L1CSR1_ICUL		0x00000400	/* I-Cache Unable to Lock */
+#define   L1CSR1_ICLFR		0x00000100	/* I-Cache Lock Flash Reset */
+#define   L1CSR1_ICFI		0x00000002	/* Instruction Cache Flash Invalidate */
+#define   L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
+#define SPRN_L1CSR2	0x25e	/* L1 Data Cache Control and Status Register 2 */
+#define   L1CSR2_DCWS		0x40000000	/* Data Cache Write Shadow */
+#define   L1CSR2_DCSTASHID  0x000003ff	/* Data Cache Stash ID */
+#define SPRN_L2CSR0	0x3f9	/* L2 Data Cache Control and Status Register 0 */
+#define   L2CSR0_L2E		0x80000000	/* L2 Cache Enable */
+#define   L2CSR0_L2PE		0x40000000	/* L2 Cache Parity/ECC Enable */
+#define   L2CSR0_L2WP		0x1c000000	/* L2 I/D Way Partioning */
+#define   L2CSR0_L2CM		0x03000000	/* L2 Cache Coherency Mode */
+#define   L2CSR0_L2FI		0x00200000	/* L2 Cache Flash Invalidate */
+#define   L2CSR0_L2IO		0x00100000	/* L2 Cache Instruction Only */
+#define   L2CSR0_L2DO		0x00010000	/* L2 Cache Data Only */
+#define   L2CSR0_L2REP		0x00003000	/* L2 Line Replacement Algo */
+
+/* e6500 */
+#define   L2CSR0_L2REP_SPLRUAGE	0x00000000	/* L2REP Streaming PLRU with Aging */
+#define   L2CSR0_L2REP_FIFO	0x00001000	/* L2REP FIFO */
+#define   L2CSR0_L2REP_SPLRU	0x00002000	/* L2REP Streaming PLRU */
+#define   L2CSR0_L2REP_PLRU	0x00003000	/* L2REP PLRU */
+
+#define   L2CSR0_L2REP_MODE	L2CSR0_L2REP_SPLRUAGE
+
+#define   L2CSR0_L2FL		0x00000800	/* L2 Cache Flush */
+#define   L2CSR0_L2LFC		0x00000400	/* L2 Cache Lock Flash Clear */
+#define   L2CSR0_L2LOA		0x00000080	/* L2 Cache Lock Overflow Allocate */
+#define   L2CSR0_L2LO		0x00000020	/* L2 Cache Lock Overflow */
+#define SPRN_L2CSR1	0x3fa	/* L2 Data Cache Control and Status Register 1 */
+
+#define SPRN_TLB0CFG	0x2B0	/* TLB 0 Config Register */
+#define SPRN_TLB1CFG	0x2B1	/* TLB 1 Config Register */
+#define   TLBnCFG_NENTRY_MASK	0x00000fff
+#define SPRN_TLB0PS	0x158	/* TLB 0 Page Size Register */
+#define SPRN_TLB1PS	0x159	/* TLB 1 Page Size Register */
+#define SPRN_MMUCSR0	0x3f4	/* MMU control and status register 0 */
+#define SPRN_MMUCFG	0x3F7	/* MMU Configuration Register */
+#define MMUCFG_MAVN	0x00000003	/* MMU Architecture Version Number */
+#define MMUCFG_MAVN_V1	0x00000000	/* v1.0 */
+#define MMUCFG_MAVN_V2	0x00000001	/* v2.0 */
+#define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
+#define SPRN_MAS1	0x271	/* MMU Assist Register 1 */
+#define SPRN_MAS2	0x272	/* MMU Assist Register 2 */
+#define SPRN_MAS3	0x273	/* MMU Assist Register 3 */
+#define SPRN_MAS4	0x274	/* MMU Assist Register 4 */
+#define SPRN_MAS5	0x275	/* MMU Assist Register 5 */
+#define SPRN_MAS6	0x276	/* MMU Assist Register 6 */
+#define SPRN_MAS7	0x3B0	/* MMU Assist Register 7 */
+#define SPRN_MAS8	0x155	/* MMU Assist Register 8 */
+
+#define SPRN_IVOR32	0x210	/* Interrupt Vector Offset Register 32 */
+#define SPRN_IVOR33	0x211	/* Interrupt Vector Offset Register 33 */
+#define SPRN_IVOR34	0x212	/* Interrupt Vector Offset Register 34 */
+#define SPRN_IVOR35	0x213	/* Interrupt Vector Offset Register 35 */
+#define SPRN_IVOR36	0x214	/* Interrupt Vector Offset Register 36 */
+#define SPRN_IVOR37	0x215	/* Interrupt Vector Offset Register 37 */
+#define SPRN_SPEFSCR	0x200	/* SPE & Embedded FP Status & Control */
+
+#define SPRN_MCSRR0	0x23a	/* Machine Check Save and Restore Register 0 */
+#define SPRN_MCSRR1	0x23b	/* Machine Check Save and Restore Register 1 */
+#define SPRN_BUCSR	0x3f5	/* Branch Control and Status Register */
+#define	  BUCSR_STAC_EN	0x01000000	/* Segment target addr cache enable */
+#define	  BUCSR_LS_EN	0x00400000	/* Link stack enable */
+#define	  BUCSR_BBFI	0x00000200	/* Branch buffer flash invalidate */
+#define	  BUCSR_BPEN	0x00000001	/* Branch prediction enable */
+#define   BUCSR_ENABLE (BUCSR_STAC_EN|BUCSR_LS_EN|BUCSR_BBFI|BUCSR_BPEN)
+#define SPRN_BBEAR	0x201	/* Branch Buffer Entry Address Register */
+#define SPRN_BBTAR	0x202	/* Branch Buffer Target Address Register */
+#define SPRN_PID1	0x279	/* Process ID Register 1 */
+#define SPRN_PID2	0x27a	/* Process ID Register 2 */
+#define SPRN_MCSR	0x23c	/* Machine Check Syndrome register */
+#define SPRN_MCAR	0x23d	/* Machine Check Address register */
+#define MCSR_MCS	0x80000000	/* Machine Check Summary */
+#define MCSR_IB		0x40000000	/* Instruction PLB Error */
+#define MCSR_DB		0x20000000	/* Data PLB Error */
+#define MCSR_TLBP	0x08000000	/* TLB Parity Error */
+#define MCSR_ICP	0x04000000	/* I-Cache Parity Error */
+#define MCSR_DCSP	0x02000000	/* D-Cache Search Parity Error */
+#define MCSR_DCFP	0x01000000	/* D-Cache Flush Parity Error */
+#define MCSR_IMPE	0x00800000	/* Imprecise Machine Check Exception */
+#define ESR_ST		0x00800000	/* Store Operation */
+
+#if defined(CONFIG_MPC86xx)
+#define SPRN_MSSCR0	0x3f6
+#define SPRN_MSSSR0	0x3f7
+#endif
+
+#define SPRN_HDBCR0	0x3d0
+#define SPRN_HDBCR1	0x3d1
+#define SPRN_HDBCR2	0x3d2
+#define SPRN_HDBCR3	0x3d3
+#define SPRN_HDBCR4	0x3d4
+#define SPRN_HDBCR5	0x3d5
+#define SPRN_HDBCR6	0x3d6
+#define SPRN_HDBCR7	0x277
+#define SPRN_HDBCR8	0x278
+
+/* Short-hand versions for a number of the above SPRNs */
+
+#define CTR	SPRN_CTR	/* Counter Register */
+#define DAR	SPRN_DAR	/* Data Address Register */
+#define DABR	SPRN_DABR	/* Data Address Breakpoint Register */
+#define DAC1	SPRN_DAC1	/* Data Address Register 1 */
+#define DAC2	SPRN_DAC2	/* Data Address Register 2 */
+#define DBAT0L	SPRN_DBAT0L	/* Data BAT 0 Lower Register */
+#define DBAT0U	SPRN_DBAT0U	/* Data BAT 0 Upper Register */
+#define DBAT1L	SPRN_DBAT1L	/* Data BAT 1 Lower Register */
+#define DBAT1U	SPRN_DBAT1U	/* Data BAT 1 Upper Register */
+#define DBAT2L	SPRN_DBAT2L	/* Data BAT 2 Lower Register */
+#define DBAT2U	SPRN_DBAT2U	/* Data BAT 2 Upper Register */
+#define DBAT3L	SPRN_DBAT3L	/* Data BAT 3 Lower Register */
+#define DBAT3U	SPRN_DBAT3U	/* Data BAT 3 Upper Register */
+#define DBAT4L	SPRN_DBAT4L	/* Data BAT 4 Lower Register */
+#define DBAT4U	SPRN_DBAT4U	/* Data BAT 4 Upper Register */
+#define DBAT5L	SPRN_DBAT5L	/* Data BAT 5 Lower Register */
+#define DBAT5U	SPRN_DBAT5U	/* Data BAT 5 Upper Register */
+#define DBAT6L	SPRN_DBAT6L	/* Data BAT 6 Lower Register */
+#define DBAT6U	SPRN_DBAT6U	/* Data BAT 6 Upper Register */
+#define DBAT7L	SPRN_DBAT7L	/* Data BAT 7 Lower Register */
+#define DBAT7U	SPRN_DBAT7U	/* Data BAT 7 Upper Register */
+#define DBCR0	SPRN_DBCR0	/* Debug Control Register 0 */
+#define DBCR1	SPRN_DBCR1	/* Debug Control Register 1 */
+#define DBSR	SPRN_DBSR	/* Debug Status Register */
+#define DCMP	SPRN_DCMP	/* Data TLB Compare Register */
+#define DEC	SPRN_DEC	/* Decrement Register */
+#define DMISS	SPRN_DMISS	/* Data TLB Miss Register */
+#define DSISR	SPRN_DSISR	/* Data Storage Interrupt Status Register */
+#define EAR	SPRN_EAR	/* External Address Register */
+#define ESR	SPRN_ESR	/* Exception Syndrome Register */
+#define HASH1	SPRN_HASH1	/* Primary Hash Address Register */
+#define HASH2	SPRN_HASH2	/* Secondary Hash Address Register */
+#define HID0	SPRN_HID0	/* Hardware Implementation Register 0 */
+#define HID1	SPRN_HID1	/* Hardware Implementation Register 1 */
+#define IABR	SPRN_IABR	/* Instruction Address Breakpoint Register */
+#define IAC1	SPRN_IAC1	/* Instruction Address Register 1 */
+#define IAC2	SPRN_IAC2	/* Instruction Address Register 2 */
+#define IBAT0L	SPRN_IBAT0L	/* Instruction BAT 0 Lower Register */
+#define IBAT0U	SPRN_IBAT0U	/* Instruction BAT 0 Upper Register */
+#define IBAT1L	SPRN_IBAT1L	/* Instruction BAT 1 Lower Register */
+#define IBAT1U	SPRN_IBAT1U	/* Instruction BAT 1 Upper Register */
+#define IBAT2L	SPRN_IBAT2L	/* Instruction BAT 2 Lower Register */
+#define IBAT2U	SPRN_IBAT2U	/* Instruction BAT 2 Upper Register */
+#define IBAT3L	SPRN_IBAT3L	/* Instruction BAT 3 Lower Register */
+#define IBAT3U	SPRN_IBAT3U	/* Instruction BAT 3 Upper Register */
+#define IBAT4L	SPRN_IBAT4L	/* Instruction BAT 4 Lower Register */
+#define IBAT4U	SPRN_IBAT4U	/* Instruction BAT 4 Upper Register */
+#define IBAT5L	SPRN_IBAT5L	/* Instruction BAT 5 Lower Register */
+#define IBAT5U	SPRN_IBAT5U	/* Instruction BAT 5 Upper Register */
+#define IBAT6L	SPRN_IBAT6L	/* Instruction BAT 6 Lower Register */
+#define IBAT6U	SPRN_IBAT6U	/* Instruction BAT 6 Upper Register */
+#define IBAT7L	SPRN_IBAT7L	/* Instruction BAT 7 Lower Register */
+#define IBAT7U	SPRN_IBAT7U	/* Instruction BAT 7 Lower Register */
+#define ICMP	SPRN_ICMP	/* Instruction TLB Compare Register */
+#define IMISS	SPRN_IMISS	/* Instruction TLB Miss Register */
+#define IMMR	SPRN_IMMR	/* PPC 860/821 Internal Memory Map Register */
+#define LDSTCR	SPRN_LDSTCR	/* Load/Store Control Register */
+#define L2CR	SPRN_L2CR	/* PPC 750 L2 control register */
+#define LR	SPRN_LR
+#define MBAR	SPRN_MBAR	/* System memory base address */
+#if defined(CONFIG_MPC86xx)
+#define MSSCR0	SPRN_MSSCR0
+#endif
+#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#define PIR	SPRN_PIR
+#endif
+#define SVR	SPRN_SVR	/* System-On-Chip Version Register */
+#define PVR	SPRN_PVR	/* Processor Version */
+#define RPA	SPRN_RPA	/* Required Physical Address Register */
+#define SDR1	SPRN_SDR1	/* MMU hash base register */
+#define SPR0	SPRN_SPRG0	/* Supervisor Private Registers */
+#define SPR1	SPRN_SPRG1
+#define SPR2	SPRN_SPRG2
+#define SPR3	SPRN_SPRG3
+#define SPRG0	SPRN_SPRG0
+#define SPRG1	SPRN_SPRG1
+#define SPRG2	SPRN_SPRG2
+#define SPRG3	SPRN_SPRG3
+#define SPRG4	SPRN_SPRG4
+#define SPRG5	SPRN_SPRG5
+#define SPRG6	SPRN_SPRG6
+#define SPRG7	SPRN_SPRG7
+#define SRR0	SPRN_SRR0	/* Save and Restore Register 0 */
+#define SRR1	SPRN_SRR1	/* Save and Restore Register 1 */
+#define SRR2	SPRN_SRR2	/* Save and Restore Register 2 */
+#define SRR3	SPRN_SRR3	/* Save and Restore Register 3 */
+#define SVR	SPRN_SVR	/* System Version Register */
+#define TBRL	SPRN_TBRL	/* Time Base Read Lower Register */
+#define TBRU	SPRN_TBRU	/* Time Base Read Upper Register */
+#define TBWL	SPRN_TBWL	/* Time Base Write Lower Register */
+#define TBWU	SPRN_TBWU	/* Time Base Write Upper Register */
+#define TCR	SPRN_TCR	/* Timer Control Register */
+#define TSR	SPRN_TSR	/* Timer Status Register */
+#define ICTC	1019
+#define THRM1	SPRN_THRM1	/* Thermal Management Register 1 */
+#define THRM2	SPRN_THRM2	/* Thermal Management Register 2 */
+#define THRM3	SPRN_THRM3	/* Thermal Management Register 3 */
+#define XER	SPRN_XER
+
+#define DECAR	SPRN_DECAR
+#define CSRR0	SPRN_CSRR0
+#define CSRR1	SPRN_CSRR1
+#define IVPR	SPRN_IVPR
+#define USPRG0	SPRN_USPRG
+#define SPRG4R	SPRN_SPRG4R
+#define SPRG5R	SPRN_SPRG5R
+#define SPRG6R	SPRN_SPRG6R
+#define SPRG7R	SPRN_SPRG7R
+#define SPRG4W	SPRN_SPRG4W
+#define SPRG5W	SPRN_SPRG5W
+#define SPRG6W	SPRN_SPRG6W
+#define SPRG7W	SPRN_SPRG7W
+#define DEAR	SPRN_DEAR
+#define DBCR2	SPRN_DBCR2
+#define IAC3	SPRN_IAC3
+#define IAC4	SPRN_IAC4
+#define DVC1	SPRN_DVC1
+#define DVC2	SPRN_DVC2
+#define IVOR0	SPRN_IVOR0
+#define IVOR1	SPRN_IVOR1
+#define IVOR2	SPRN_IVOR2
+#define IVOR3	SPRN_IVOR3
+#define IVOR4	SPRN_IVOR4
+#define IVOR5	SPRN_IVOR5
+#define IVOR6	SPRN_IVOR6
+#define IVOR7	SPRN_IVOR7
+#define IVOR8	SPRN_IVOR8
+#define IVOR9	SPRN_IVOR9
+#define IVOR10	SPRN_IVOR10
+#define IVOR11	SPRN_IVOR11
+#define IVOR12	SPRN_IVOR12
+#define IVOR13	SPRN_IVOR13
+#define IVOR14	SPRN_IVOR14
+#define IVOR15	SPRN_IVOR15
+#define IVOR32	SPRN_IVOR32
+#define IVOR33	SPRN_IVOR33
+#define IVOR34	SPRN_IVOR34
+#define IVOR35	SPRN_IVOR35
+#define MCSRR0	SPRN_MCSRR0
+#define MCSRR1	SPRN_MCSRR1
+#define L1CSR0	SPRN_L1CSR0
+#define L1CSR1	SPRN_L1CSR1
+#define L1CSR2	SPRN_L1CSR2
+#define L1CFG0	SPRN_L1CFG0
+#define L1CFG1	SPRN_L1CFG1
+#define L2CFG0	SPRN_L2CFG0
+#define L2CSR0	SPRN_L2CSR0
+#define L2CSR1	SPRN_L2CSR1
+#define MCSR	SPRN_MCSR
+#define MMUCSR0	SPRN_MMUCSR0
+#define BUCSR	SPRN_BUCSR
+#define PID0	SPRN_PID
+#define PID1	SPRN_PID1
+#define PID2	SPRN_PID2
+#define MAS0	SPRN_MAS0
+#define MAS1	SPRN_MAS1
+#define MAS2	SPRN_MAS2
+#define MAS3	SPRN_MAS3
+#define MAS4	SPRN_MAS4
+#define MAS5	SPRN_MAS5
+#define MAS6	SPRN_MAS6
+#define MAS7	SPRN_MAS7
+#define MAS8 	SPRN_MAS8
+
+#if defined(CONFIG_MPC85xx)
+#define DAR_DEAR DEAR
+#else
+#define DAR_DEAR DAR
+#endif
+
+/* Device Control Registers */
+
+#define DCRN_BEAR	0x090	/* Bus Error Address Register */
+#define DCRN_BESR	0x091	/* Bus Error Syndrome Register */
+#define   BESR_DSES	0x80000000	/* Data-Side Error Status */
+#define   BESR_DMES	0x40000000	/* DMA Error Status */
+#define   BESR_RWS	0x20000000	/* Read/Write Status */
+#define   BESR_ETMASK	0x1C000000	/* Error Type */
+#define     ET_PROT	0
+#define     ET_PARITY	1
+#define     ET_NCFG	2
+#define     ET_BUSERR	4
+#define     ET_BUSTO	6
+#define DCRN_DMACC0	0x0C4	/* DMA Chained Count Register 0 */
+#define DCRN_DMACC1	0x0CC	/* DMA Chained Count Register 1 */
+#define DCRN_DMACC2	0x0D4	/* DMA Chained Count Register 2 */
+#define DCRN_DMACC3	0x0DC	 /* DMA Chained Count Register 3 */
+#define DCRN_DMACR0	0x0C0	 /* DMA Channel Control Register 0 */
+#define DCRN_DMACR1	0x0C8	 /* DMA Channel Control Register 1 */
+#define DCRN_DMACR2	0x0D0	 /* DMA Channel Control Register 2 */
+#define DCRN_DMACR3	0x0D8	 /* DMA Channel Control Register 3 */
+#define DCRN_DMACT0	0x0C1	 /* DMA Count Register 0 */
+#define DCRN_DMACT1	0x0C9	 /* DMA Count Register 1 */
+#define DCRN_DMACT2	0x0D1	 /* DMA Count Register 2 */
+#define DCRN_DMACT3	0x0D9	 /* DMA Count Register 3 */
+#define DCRN_DMADA0	0x0C2	 /* DMA Destination Address Register 0 */
+#define DCRN_DMADA1	0x0CA	 /* DMA Destination Address Register 1 */
+#define DCRN_DMADA2	0x0D2	 /* DMA Destination Address Register 2 */
+#define DCRN_DMADA3	0x0DA	 /* DMA Destination Address Register 3 */
+#define DCRN_DMASA0	0x0C3	 /* DMA Source Address Register 0 */
+#define DCRN_DMASA1	0x0CB	 /* DMA Source Address Register 1 */
+#define DCRN_DMASA2	0x0D3	 /* DMA Source Address Register 2 */
+#define DCRN_DMASA3	0x0DB	 /* DMA Source Address Register 3 */
+#define DCRN_DMASR	0x0E0	 /* DMA Status Register */
+#define DCRN_EXIER	0x042	 /* External Interrupt Enable Register */
+#define   EXIER_CIE	0x80000000	/* Critical Interrupt Enable */
+#define   EXIER_SRIE	0x08000000	/* Serial Port Rx Int. Enable */
+#define   EXIER_STIE	0x04000000	/* Serial Port Tx Int. Enable */
+#define   EXIER_JRIE	0x02000000	/* JTAG Serial Port Rx Int. Enable */
+#define   EXIER_JTIE	0x01000000	/* JTAG Serial Port Tx Int. Enable */
+#define   EXIER_D0IE	0x00800000	/* DMA Channel 0 Interrupt Enable */
+#define   EXIER_D1IE	0x00400000	/* DMA Channel 1 Interrupt Enable */
+#define   EXIER_D2IE	0x00200000	/* DMA Channel 2 Interrupt Enable */
+#define   EXIER_D3IE	0x00100000	/* DMA Channel 3 Interrupt Enable */
+#define   EXIER_E0IE	0x00000010	/* External Interrupt 0 Enable */
+#define   EXIER_E1IE	0x00000008	/* External Interrupt 1 Enable */
+#define   EXIER_E2IE	0x00000004	/* External Interrupt 2 Enable */
+#define   EXIER_E3IE	0x00000002	/* External Interrupt 3 Enable */
+#define   EXIER_E4IE	0x00000001	/* External Interrupt 4 Enable */
+#define DCRN_EXISR	0x040	 /* External Interrupt Status Register */
+#define DCRN_IOCR	0x0A0	 /* Input/Output Configuration Register */
+#define   IOCR_E0TE	0x80000000
+#define   IOCR_E0LP	0x40000000
+#define   IOCR_E1TE	0x20000000
+#define   IOCR_E1LP	0x10000000
+#define   IOCR_E2TE	0x08000000
+#define   IOCR_E2LP	0x04000000
+#define   IOCR_E3TE	0x02000000
+#define   IOCR_E3LP	0x01000000
+#define   IOCR_E4TE	0x00800000
+#define   IOCR_E4LP	0x00400000
+#define   IOCR_EDT	0x00080000
+#define   IOCR_SOR	0x00040000
+#define   IOCR_EDO	0x00008000
+#define   IOCR_2XC	0x00004000
+#define   IOCR_ATC	0x00002000
+#define   IOCR_SPD	0x00001000
+#define   IOCR_BEM	0x00000800
+#define   IOCR_PTD	0x00000400
+#define   IOCR_ARE	0x00000080
+#define   IOCR_DRC	0x00000020
+#define   IOCR_RDM(x)	(((x) & 0x3) << 3)
+#define   IOCR_TCS	0x00000004
+#define   IOCR_SCS	0x00000002
+#define   IOCR_SPC	0x00000001
+
+/* System-On-Chip Version Register */
+
+/* System-On-Chip Version Register (SVR) field extraction */
+
+#define SVR_VER(svr)	(((svr) >> 16) & 0xFFFF) /* Version field */
+#define SVR_REV(svr)	(((svr) >>  0) & 0xFF)	 /* Revision field */
+
+#define SVR_CID(svr)	(((svr) >> 28) & 0x0F)	 /* Company or manufacturer ID */
+#define SVR_SOCOP(svr)	(((svr) >> 22) & 0x3F)	 /* SOC integration options */
+#define SVR_SID(svr)	(((svr) >> 16) & 0x3F)	 /* SOC ID */
+#define SVR_PROC(svr)	(((svr) >> 12) & 0x0F)	 /* Process revision field */
+#define SVR_MFG(svr)	(((svr) >>  8) & 0x0F)	 /* Manufacturing revision */
+#define SVR_MJREV(svr)	(((svr) >>  4) & 0x0F)	 /* Major SOC design revision indicator */
+#define SVR_MNREV(svr)	(((svr) >>  0) & 0x0F)	 /* Minor SOC design revision indicator */
+
+/* Processor Version Register */
+
+/* Processor Version Register (PVR) field extraction */
+
+#define PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF)	/* Version field */
+#define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF)	/* Revison field */
+
+/*
+ * AMCC has further subdivided the standard PowerPC 16-bit version and
+ * revision subfields of the PVR for the PowerPC 403s into the following:
+ */
+
+#define PVR_FAM(pvr)	(((pvr) >> 20) & 0xFFF)	/* Family field */
+#define PVR_MEM(pvr)	(((pvr) >> 16) & 0xF)	/* Member field */
+#define PVR_CORE(pvr)	(((pvr) >> 12) & 0xF)	/* Core field */
+#define PVR_CFG(pvr)	(((pvr) >>  8) & 0xF)	/* Configuration field */
+#define PVR_MAJ(pvr)	(((pvr) >>  4) & 0xF)	/* Major revision field */
+#define PVR_MIN(pvr)	(((pvr) >>  0) & 0xF)	/* Minor revision field */
+
+/* e600 core PVR fields */
+
+#define PVR_E600_VER(pvr)	(((pvr) >> 15) & 0xFFFF) /* Version/type */
+#define PVR_E600_TECH(pvr)	(((pvr) >> 12) & 0xF)	 /* Technology */
+#define PVR_E600_MAJ(pvr)	(((pvr) >> 8) & 0xF)	 /* Major revision */
+#define PVR_E600_MIN(pvr)	(((pvr) >> 0) & 0xFF)	 /* Minor revision */
+
+/* Processor Version Numbers */
+
+#define PVR_403GA	0x00200000
+#define PVR_403GB	0x00200100
+#define PVR_403GC	0x00200200
+#define PVR_403GCX	0x00201400
+#define PVR_405GP	0x40110000
+#define PVR_405GP_RB	0x40110040
+#define PVR_405GP_RC	0x40110082
+#define PVR_405GP_RD	0x401100C4
+#define PVR_405GP_RE	0x40110145  /* same as pc405cr rev c */
+#define PVR_405EP_RA	0x51210950
+#define PVR_405GPR_RB	0x50910951
+#define PVR_405EZ_RA	0x41511460
+#define PVR_405EXR2_RA	0x12911471 /* 405EXr rev A/B without Security */
+#define PVR_405EX1_RA	0x12911477 /* 405EX rev A/B with Security */
+#define PVR_405EXR1_RC	0x1291147B /* 405EXr rev C with Security */
+#define PVR_405EXR2_RC	0x12911479 /* 405EXr rev C without Security */
+#define PVR_405EX1_RC	0x1291147F /* 405EX rev C with Security */
+#define PVR_405EX2_RC	0x1291147D /* 405EX rev C without Security */
+#define PVR_405EXR1_RD	0x12911472 /* 405EXr rev D with Security */
+#define PVR_405EXR2_RD	0x12911470 /* 405EXr rev D without Security */
+#define PVR_405EX1_RD	0x12911475 /* 405EX rev D with Security */
+#define PVR_405EX2_RD	0x12911473 /* 405EX rev D without Security */
+#define PVR_440GP_RB	0x40120440
+#define PVR_440GP_RC	0x40120481
+#define PVR_440EP_RA	0x42221850
+#define PVR_440EP_RB	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440EP_RC	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440GR_RA	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440GR_RB	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440EPX1_RA	0x216218D0 /* 440EPX rev A with Security / Kasumi */
+#define PVR_440EPX2_RA	0x216218D4 /* 440EPX rev A without Security / Kasumi */
+#define PVR_440GRX1_RA	0x216218D0 /* 440GRX rev A with Security / Kasumi */
+#define PVR_440GRX2_RA	0x216218D4 /* 440GRX rev A without Security / Kasumi */
+#define PVR_440GX_RA	0x51B21850
+#define PVR_440GX_RB	0x51B21851
+#define PVR_440GX_RC	0x51B21892
+#define PVR_440GX_RF	0x51B21894
+#define PVR_405EP_RB	0x51210950
+#define PVR_440SP_6_RAB	0x53221850 /* 440SP rev A&B with RAID 6 support enabled	*/
+#define PVR_440SP_RAB	0x53321850 /* 440SP rev A&B without RAID 6 support	*/
+#define PVR_440SP_6_RC	0x53221891 /* 440SP rev C with RAID 6 support enabled	*/
+#define PVR_440SP_RC	0x53321891 /* 440SP rev C without RAID 6 support	*/
+#define PVR_440SPe_6_RA	0x53421890 /* 440SPe rev A with RAID 6 support enabled	*/
+#define PVR_440SPe_RA	0x53521890 /* 440SPe rev A without RAID 6 support	*/
+#define PVR_440SPe_6_RB	0x53421891 /* 440SPe rev B with RAID 6 support enabled	*/
+#define PVR_440SPe_RB	0x53521891 /* 440SPe rev B without RAID 6 support	*/
+#define PVR_460EX_SE_RA	0x130218A2 /* 460EX rev A with Security Engine	  */
+#define PVR_460EX_RA	0x130218A3 /* 460EX rev A without Security Engine */
+#define PVR_460EX_RB	0x130218A4 /* 460EX rev B with and without Sec Eng*/
+#define PVR_460GT_SE_RA	0x130218A0 /* 460GT rev A with Security Engine	  */
+#define PVR_460GT_RA	0x130218A1 /* 460GT rev A without Security Engine */
+#define PVR_460GT_RB	0x130218A5 /* 460GT rev B with and without Sec Eng*/
+#define PVR_460SX_RA    0x13541800 /* 460SX rev A                   */
+#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
+#define PVR_460GX_RA    0x13541802 /* 460GX rev A                   */
+#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
+#define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */
+#define PVR_601		0x00010000
+#define PVR_602		0x00050000
+#define PVR_603		0x00030000
+#define PVR_603e	0x00060000
+#define PVR_603ev	0x00070000
+#define PVR_603r	0x00071000
+#define PVR_604		0x00040000
+#define PVR_604e	0x00090000
+#define PVR_604r	0x000A0000
+#define PVR_620		0x00140000
+#define PVR_740		0x00080000
+#define PVR_750		PVR_740
+#define PVR_740P	0x10080000
+#define PVR_750P	PVR_740P
+#define PVR_7400	0x000C0000
+#define PVR_7410	0x800C0000
+#define PVR_7450	0x80000000
+
+#define PVR_85xx	0x80200000
+#define PVR_85xx_REV1	(PVR_85xx | 0x0010)
+#define PVR_85xx_REV2	(PVR_85xx | 0x0020)
+#define PVR_VER_E500_V1	0x8020
+#define PVR_VER_E500_V2	0x8021
+#define PVR_VER_E500MC	0x8023
+#define PVR_VER_E5500	0x8024
+#define PVR_VER_E6500	0x8040
+
+#define PVR_86xx	0x80040000
+
+#define PVR_VIRTEX5     0x7ff21912
+
+/*
+ * For the 8xx processors, all of them report the same PVR family for
+ * the PowerPC core. The various versions of these processors must be
+ * differentiated by the version number in the Communication Processor
+ * Module (CPM).
+ */
+#define PVR_8xx		0x00500000
+
+#define PVR_7400	0x000C0000
+
+/*
+ * MPC 52xx
+ */
+#define PVR_5200	0x80822011
+#define PVR_5200B	0x80822014
+
+/*
+ * 405EX/EXr CHIP_21 Errata
+ */
+#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
+#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EX1_RC
+#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EX1_RD
+#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x0
+#endif
+
+#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
+#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EX2_RC
+#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EX2_RD
+#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x1
+#endif
+
+#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
+#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EXR1_RC
+#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EXR1_RD
+#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x2
+#endif
+
+#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
+#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EXR2_RC
+#define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EXR2_RD
+#define CONFIG_405EX_CHIP21_ECID3_REV_D	0x3
+#endif
+
+/*
+ * System Version Register
+ */
+
+/* System Version Register (SVR) field extraction */
+
+#define SVR_SUBVER(svr)	(((svr) >>  8) & 0xFF)	/* Process/MFG sub-version */
+
+#define SVR_FAM(svr)	(((svr) >> 20) & 0xFFF)	/* Family field */
+#define SVR_MEM(svr)	(((svr) >> 16) & 0xF)	/* Member field */
+
+#ifdef CONFIG_ARCH_MPC8536
+#define SVR_MAJ(svr)	(((svr) >>  4) & 0x7)	/* Major revision field*/
+#else
+#define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
+#endif
+#define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
+
+/* Some parts define SVR[0:23] as the SOC version */
+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/
+
+/* whether MPC8xxxE (i.e. has SEC) */
+#if defined(CONFIG_MPC85xx)
+#define IS_E_PROCESSOR(svr)	(svr & 0x80000)
+#else
+#if defined(CONFIG_MPC83xx)
+#define IS_E_PROCESSOR(spridr)	(!(spridr & 0x00010000))
+#endif
+#endif
+
+#define IS_SVR_REV(svr, maj, min) \
+	((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
+
+/*
+ * SVR_SOC_VER() Version Values
+ */
+
+#define SVR_8533	0x803400
+#define SVR_8535	0x803701
+#define SVR_8536	0x803700
+#define SVR_8540	0x803000
+#define SVR_8541	0x807200
+#define SVR_8543	0x803200
+#define SVR_8544	0x803401
+#define SVR_8545	0x803102
+#define SVR_8547	0x803101
+#define SVR_8548	0x803100
+#define SVR_8555	0x807100
+#define SVR_8560	0x807000
+#define SVR_8567	0x807501
+#define SVR_8568	0x807500
+#define SVR_8569	0x808000
+#define SVR_8572	0x80E000
+#define SVR_P1010	0x80F100
+#define SVR_P1011	0x80E500
+#define SVR_P1012	0x80E501
+#define SVR_P1013	0x80E700
+#define SVR_P1014	0x80F101
+#define SVR_P1017	0x80F700
+#define SVR_P1020	0x80E400
+#define SVR_P1021	0x80E401
+#define SVR_P1022	0x80E600
+#define SVR_P1023	0x80F600
+#define SVR_P1024	0x80E402
+#define SVR_P1025	0x80E403
+#define SVR_P2010	0x80E300
+#define SVR_P2020	0x80E200
+#define SVR_P2040	0x821000
+#define SVR_P2041	0x821001
+#define SVR_P3041	0x821103
+#define SVR_P4040	0x820100
+#define SVR_P4080	0x820000
+#define SVR_P5010	0x822100
+#define SVR_P5020	0x822000
+#define SVR_P5021	0X820500
+#define SVR_P5040	0x820400
+#define SVR_T4240	0x824000
+#define SVR_T4120	0x824001
+#define SVR_T4160	0x824100
+#define SVR_T4080	0x824102
+#define SVR_C291	0x850000
+#define SVR_C292	0x850020
+#define SVR_C293	0x850030
+#define SVR_B4860	0X868000
+#define SVR_G4860	0x868001
+#define SVR_B4460	0x868003
+#define SVR_B4440	0x868100
+#define SVR_G4440	0x868101
+#define SVR_B4420	0x868102
+#define SVR_B4220	0x868103
+#define SVR_T1040	0x852000
+#define SVR_T1041	0x852001
+#define SVR_T1042	0x852002
+#define SVR_T1020	0x852100
+#define SVR_T1021	0x852101
+#define SVR_T1022	0x852102
+#define SVR_T1024	0x854000
+#define SVR_T1023	0x854100
+#define SVR_T1014	0x854400
+#define SVR_T1013	0x854500
+#define SVR_T2080	0x853000
+#define SVR_T2081	0x853100
+
+#define SVR_8610	0x80A000
+#define SVR_8641	0x809000
+#define SVR_8641D	0x809001
+
+#define SVR_9130	0x860001
+#define SVR_9131	0x860000
+#define SVR_9132	0x861000
+#define SVR_9232	0x861400
+
+#define SVR_Unknown	0xFFFFFF
+
+#define _GLOBAL(n)\
+	.globl n;\
+n:
+
+/* Macros for setting and retrieving special purpose registers */
+
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+#define mfdcr(rn)	({unsigned int rval; \
+			asm volatile("mfdcr %0," stringify(rn) \
+				     : "=r" (rval)); rval;})
+#define mtdcr(rn, v)	asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
+
+#define mfmsr()		({unsigned int rval; \
+			asm volatile("mfmsr %0" : "=r" (rval)); rval;})
+#define mtmsr(v)	asm volatile("mtmsr %0" : : "r" (v))
+
+#define mfspr(rn)	({unsigned int rval; \
+			asm volatile("mfspr %0," stringify(rn) \
+				     : "=r" (rval)); rval;})
+#define mtspr(rn, v)	asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
+
+#define tlbie(v)	asm volatile("tlbie %0 \n sync" : : "r" (v))
+
+/* Segment Registers */
+
+#define SR0	0
+#define SR1	1
+#define SR2	2
+#define SR3	3
+#define SR4	4
+#define SR5	5
+#define SR6	6
+#define SR7	7
+#define SR8	8
+#define SR9	9
+#define SR10	10
+#define SR11	11
+#define SR12	12
+#define SR13	13
+#define SR14	14
+#define SR15	15
+
+#ifndef __ASSEMBLY__
+
+struct cpu_type {
+	char name[15];
+	u32 soc_ver;
+	u32 num_cores;
+	u32 mask;	/* which cpu(s) actually exist */
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+	u32 dsp_num_cores;
+	u32 dsp_mask;	/* which DSP cpu(s) actually exist */
+#endif
+};
+
+struct cpu_type *identify_cpu(u32 ver);
+int fixup_cpu(void);
+
+int fsl_qoriq_core_to_cluster(unsigned int core);
+int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
+
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#define CPU_TYPE_ENTRY(n, v, nc) \
+	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
+	  .mask = (1 << (nc)) - 1 }
+#define CPU_TYPE_ENTRY_MASK(n, v, nc, m) \
+	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), .mask = (m) }
+#else
+#if defined(CONFIG_MPC83xx)
+#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
+#endif
+#endif
+
+struct task_struct;
+
+#ifndef CONFIG_CPU_MPC83XX
+int prt_83xx_rsr(void);
+#endif
+
+#endif /* ndef ASSEMBLY*/
+
+#if defined(CONFIG_MPC85xx)
+ #define EPAPR_MAGIC	(0x45504150)
+#else
+ #define EPAPR_MAGIC	(0x65504150)
+#endif
+
+#endif /* __ASM_PPC_PROCESSOR_H */
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
new file mode 100644
index 0000000..2d56de6
--- /dev/null
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -0,0 +1,105 @@
+#ifndef _PPC_PTRACE_H
+#define _PPC_PTRACE_H
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ *
+ * this should only contain volatile regs
+ * since we can keep non-volatile in the thread_struct
+ * should set this up when only volatiles are saved
+ * by intr code.
+ *
+ * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
+ * that the overall structure is a multiple of 16 bytes in length.
+ *
+ * Note that the offsets of the fields in this struct correspond with
+ * the PT_* values below.  This simplifies arch/powerpc/kernel/ptrace.c.
+ */
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_PPC64BRIDGE
+#define PPC_REG unsigned long /*long*/
+#else
+#define PPC_REG unsigned long
+#endif
+struct pt_regs {
+	PPC_REG gpr[32];
+	PPC_REG nip;
+	PPC_REG msr;
+	PPC_REG orig_gpr3;	/* Used for restarting system calls */
+	PPC_REG ctr;
+	PPC_REG link;
+	PPC_REG xer;
+	PPC_REG ccr;
+	PPC_REG mq;		/* 601 only (not used at present) */
+				/* Used on APUS to hold IPL value. */
+	PPC_REG trap;		/* Reason for being here */
+	PPC_REG dar;		/* Fault registers */
+	PPC_REG dsisr;
+	PPC_REG result;		/* Result of a system call */
+};
+#endif
+
+#define STACK_FRAME_OVERHEAD	16	/* size of minimum stack frame */
+
+/* Size of stack frame allocated when calling signal handler. */
+#define __SIGNAL_FRAMESIZE	64
+
+#define instruction_pointer(regs) ((regs)->nip)
+#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ * These can't be changed without breaking binary compatibility
+ * with MkLinux, etc.
+ */
+#define PT_R0	0
+#define PT_R1	1
+#define PT_R2	2
+#define PT_R3	3
+#define PT_R4	4
+#define PT_R5	5
+#define PT_R6	6
+#define PT_R7	7
+#define PT_R8	8
+#define PT_R9	9
+#define PT_R10	10
+#define PT_R11	11
+#define PT_R12	12
+#define PT_R13	13
+#define PT_R14	14
+#define PT_R15	15
+#define PT_R16	16
+#define PT_R17	17
+#define PT_R18	18
+#define PT_R19	19
+#define PT_R20	20
+#define PT_R21	21
+#define PT_R22	22
+#define PT_R23	23
+#define PT_R24	24
+#define PT_R25	25
+#define PT_R26	26
+#define PT_R27	27
+#define PT_R28	28
+#define PT_R29	29
+#define PT_R30	30
+#define PT_R31	31
+
+#define PT_NIP	32
+#define PT_MSR	33
+#ifdef __KERNEL__
+#define PT_ORIG_R3 34
+#endif
+#define PT_CTR	35
+#define PT_LNK	36
+#define PT_XER	37
+#define PT_CCR	38
+#define PT_MQ	39
+
+#define PT_FPR0	48	/* each FP reg occupies 2 slots in this space */
+#define PT_FPR31 (PT_FPR0 + 2*31)
+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
+
+#endif
diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h
new file mode 100644
index 0000000..ccd28ac
--- /dev/null
+++ b/arch/powerpc/include/asm/sections.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_POWERPC_SECTIONS_H
+#define __ASM_POWERPC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/powerpc/include/asm/sigcontext.h b/arch/powerpc/include/asm/sigcontext.h
new file mode 100644
index 0000000..715c868
--- /dev/null
+++ b/arch/powerpc/include/asm/sigcontext.h
@@ -0,0 +1,15 @@
+#ifndef _ASM_PPC_SIGCONTEXT_H
+#define _ASM_PPC_SIGCONTEXT_H
+
+#include <asm/ptrace.h>
+
+
+struct sigcontext_struct {
+	unsigned long	_unused[4];
+	int		signal;
+	unsigned long	handler;
+	unsigned long	oldmask;
+	struct pt_regs	*regs;
+};
+
+#endif
diff --git a/arch/powerpc/include/asm/signal.h b/arch/powerpc/include/asm/signal.h
new file mode 100644
index 0000000..b11a28e
--- /dev/null
+++ b/arch/powerpc/include/asm/signal.h
@@ -0,0 +1,154 @@
+#ifndef _ASMPPC_SIGNAL_H
+#define _ASMPPC_SIGNAL_H
+
+#include <linux/types.h>
+
+/* Avoid too many header ordering problems.  */
+struct siginfo;
+
+/* Most things should be clean enough to redefine this at will, if care
+   is taken to make libc match.  */
+
+#define _NSIG		64
+#define _NSIG_BPW	32
+#define _NSIG_WORDS	(_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t;		/* at least 32 bits */
+
+typedef struct {
+	unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#define SIGHUP		 1
+#define SIGINT		 2
+#define SIGQUIT		 3
+#define SIGILL		 4
+#define SIGTRAP		 5
+#define SIGABRT		 6
+#define SIGIOT		 6
+#define SIGBUS		 7
+#define SIGFPE		 8
+#define SIGKILL		 9
+#define SIGUSR1		10
+#define SIGSEGV		11
+#define SIGUSR2		12
+#define SIGPIPE		13
+#define SIGALRM		14
+#define SIGTERM		15
+#define SIGSTKFLT	16
+#define SIGCHLD		17
+#define SIGCONT		18
+#define SIGSTOP		19
+#define SIGTSTP		20
+#define SIGTTIN		21
+#define SIGTTOU		22
+#define SIGURG		23
+#define SIGXCPU		24
+#define SIGXFSZ		25
+#define SIGVTALRM	26
+#define SIGPROF		27
+#define SIGWINCH	28
+#define SIGIO		29
+#define SIGPOLL		SIGIO
+/*
+#define SIGLOST		29
+*/
+#define SIGPWR		30
+#define SIGSYS		31
+#define	SIGUNUSED	31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN	32
+#define SIGRTMAX	(_NSIG-1)
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
+ * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP	0x00000001
+#define SA_NOCLDWAIT	0x00000002 /* not supported yet */
+#define SA_SIGINFO	0x00000004
+#define SA_ONSTACK	0x08000000
+#define SA_RESTART	0x10000000
+#define SA_NODEFER	0x40000000
+#define SA_RESETHAND	0x80000000
+
+#define SA_NOMASK	SA_NODEFER
+#define SA_ONESHOT	SA_RESETHAND
+#define SA_INTERRUPT	0x20000000 /* dummy -- ignored */
+
+#define SA_RESTORER	0x04000000
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK	1
+#define SS_DISABLE	2
+
+#define MINSIGSTKSZ	2048
+#define SIGSTKSZ	8192
+#ifdef __KERNEL__
+
+/*
+ * These values of sa_flags are used only by the kernel as part of the
+ * irq handling routines.
+ *
+ * SA_INTERRUPT is also used by the irq handling routines.
+ * SA_SHIRQ is for shared interrupt support on PCI and EISA.
+ */
+#define SA_PROBE		SA_ONESHOT
+#define SA_SAMPLE_RANDOM	SA_RESTART
+#define SA_SHIRQ		0x04000000
+#endif
+
+#define SIG_BLOCK          0	/* for blocking signals */
+#define SIG_UNBLOCK        1	/* for unblocking signals */
+#define SIG_SETMASK        2	/* for setting the signal mask */
+
+/* Type of a signal handler.  */
+typedef void (*__sighandler_t)(int);
+
+#define SIG_DFL	((__sighandler_t)0)	/* default signal handling */
+#define SIG_IGN	((__sighandler_t)1)	/* ignore signal */
+#define SIG_ERR	((__sighandler_t)-1)	/* error return from signal */
+
+struct old_sigaction {
+	__sighandler_t sa_handler;
+	old_sigset_t sa_mask;
+	unsigned long sa_flags;
+	void (*sa_restorer)(void);
+};
+
+struct sigaction {
+	__sighandler_t sa_handler;
+	unsigned long sa_flags;
+	void (*sa_restorer)(void);
+	sigset_t sa_mask;		/* mask last for extensibility */
+};
+
+struct k_sigaction {
+	struct sigaction sa;
+};
+
+typedef struct sigaltstack {
+	void *ss_sp;
+	int ss_flags;
+	size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/spl.h b/arch/powerpc/include/asm/spl.h
new file mode 100644
index 0000000..60a7d37
--- /dev/null
+++ b/arch/powerpc/include/asm/spl.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef	_ASM_SPL_H_
+#define	_ASM_SPL_H_
+
+#define BOOT_DEVICE_NOR		1
+
+#endif
diff --git a/arch/powerpc/include/asm/string.h b/arch/powerpc/include/asm/string.h
new file mode 100644
index 0000000..036805e
--- /dev/null
+++ b/arch/powerpc/include/asm/string.h
@@ -0,0 +1,29 @@
+#ifndef _PPC_STRING_H_
+#define _PPC_STRING_H_
+
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRNCPY
+#define __HAVE_ARCH_STRLEN
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRCAT
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_BCOPY
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMMOVE
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_MEMCHR
+
+extern int strcasecmp(const char *, const char *);
+extern int strncasecmp(const char *, const char *, __kernel_size_t);
+extern char * strcpy(char *,const char *);
+extern char * strncpy(char *,const char *, __kernel_size_t);
+extern __kernel_size_t strlen(const char *);
+extern int strcmp(const char *,const char *);
+extern char * strcat(char *, const char *);
+extern void * memset(void *,int,__kernel_size_t);
+extern void * memcpy(void *,const void *,__kernel_size_t);
+extern void * memmove(void *,const void *,__kernel_size_t);
+extern int memcmp(const void *,const void *,__kernel_size_t);
+extern void * memchr(const void *,int,__kernel_size_t);
+
+#endif
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
new file mode 100644
index 0000000..cc8d123
--- /dev/null
+++ b/arch/powerpc/include/asm/types.h
@@ -0,0 +1,36 @@
+#ifndef _PPC_TYPES_H
+#define _PPC_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+typedef struct {
+	__u32 u[4];
+} __attribute__((aligned(16))) vector128;
+
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long dma_addr_t;
+#else
+/* DMA addresses are 32-bits wide */
+typedef u32 dma_addr_t;
+#endif
+
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+#else
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
new file mode 100644
index 0000000..1841565
--- /dev/null
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000 - 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __U_BOOT_H__
+#define __U_BOOT_H__
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_PPC
+
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#include <asm/ppc.h>
+
+#endif	/* __U_BOOT_H__ */
diff --git a/arch/powerpc/include/asm/unaligned.h b/arch/powerpc/include/asm/unaligned.h
new file mode 100644
index 0000000..5f1b1e3
--- /dev/null
+++ b/arch/powerpc/include/asm/unaligned.h
@@ -0,0 +1,16 @@
+#ifndef _ASM_POWERPC_UNALIGNED_H
+#define _ASM_POWERPC_UNALIGNED_H
+
+#ifdef __KERNEL__
+
+/*
+ * The PowerPC can do unaligned accesses itself in big endian mode.
+ */
+#include <linux/unaligned/access_ok.h>
+#include <linux/unaligned/generic.h>
+
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+
+#endif	/* __KERNEL__ */
+#endif	/* _ASM_POWERPC_UNALIGNED_H */
diff --git a/arch/riscv/include/asm/arch-generic/clk.h b/arch/riscv/include/asm/arch-generic/clk.h
new file mode 100644
index 0000000..1631f5f
--- /dev/null
+++ b/arch/riscv/include/asm/arch-generic/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __ASM_RISCV_ARCH_CLK_H
+#define __ASM_RISCV_ARCH_CLK_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/arch/riscv/include/asm/arch-generic/gpio.h b/arch/riscv/include/asm/arch-generic/gpio.h
new file mode 100644
index 0000000..dfcb753
--- /dev/null
+++ b/arch/riscv/include/asm/arch-generic/gpio.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 SiFive, Inc.
+ */
+
+#ifndef _GPIO_SIFIVE_H
+#define _GPIO_SIFIVE_H
+
+#define GPIO_INPUT_VAL	0x00
+#define GPIO_INPUT_EN	0x04
+#define GPIO_OUTPUT_EN	0x08
+#define GPIO_OUTPUT_VAL	0x0C
+#define GPIO_RISE_IE	0x18
+#define GPIO_RISE_IP	0x1C
+#define GPIO_FALL_IE	0x20
+#define GPIO_FALL_IP	0x24
+#define GPIO_HIGH_IE	0x28
+#define GPIO_HIGH_IP	0x2C
+#define GPIO_LOW_IE	0x30
+#define GPIO_LOW_IP	0x34
+#define GPIO_OUTPUT_XOR	0x40
+
+#define NR_GPIOS	16
+
+enum gpio_state {
+	LOW,
+	HIGH
+};
+
+/* Details about a GPIO bank */
+struct sifive_gpio_platdata {
+	void *base;     /* address of registers in physical memory */
+};
+
+#endif /* _GPIO_SIFIVE_H */
diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
new file mode 100644
index 0000000..5a02b7d
--- /dev/null
+++ b/arch/riscv/include/asm/asm.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ */
+
+#ifndef _ASM_RISCV_ASM_H
+#define _ASM_RISCV_ASM_H
+
+#ifdef __ASSEMBLY__
+#define __ASM_STR(x)	x
+#else
+#define __ASM_STR(x)	#x
+#endif
+
+#if __riscv_xlen == 64
+#define __REG_SEL(a, b)	__ASM_STR(a)
+#elif __riscv_xlen == 32
+#define __REG_SEL(a, b)	__ASM_STR(b)
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+
+#define REG_L		__REG_SEL(ld, lw)
+#define REG_S		__REG_SEL(sd, sw)
+#define SZREG		__REG_SEL(8, 4)
+#define LGREG		__REG_SEL(3, 2)
+
+#if __SIZEOF_POINTER__ == 8
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.dword
+#define RISCV_SZPTR		8
+#define RISCV_LGPTR		3
+#else
+#define RISCV_PTR		".dword"
+#define RISCV_SZPTR		"8"
+#define RISCV_LGPTR		"3"
+#endif
+#elif __SIZEOF_POINTER__ == 4
+#ifdef __ASSEMBLY__
+#define RISCV_PTR		.word
+#define RISCV_SZPTR		4
+#define RISCV_LGPTR		2
+#else
+#define RISCV_PTR		".word"
+#define RISCV_SZPTR		"4"
+#define RISCV_LGPTR		"2"
+#endif
+#else
+#error "Unexpected __SIZEOF_POINTER__"
+#endif
+
+#if (__SIZEOF_INT__ == 4)
+#define RISCV_INT		__ASM_STR(.word)
+#define RISCV_SZINT		__ASM_STR(4)
+#define RISCV_LGINT		__ASM_STR(2)
+#else
+#error "Unexpected __SIZEOF_INT__"
+#endif
+
+#if (__SIZEOF_SHORT__ == 2)
+#define RISCV_SHORT		__ASM_STR(.half)
+#define RISCV_SZSHORT		__ASM_STR(2)
+#define RISCV_LGSHORT		__ASM_STR(1)
+#else
+#error "Unexpected __SIZEOF_SHORT__"
+#endif
+
+#endif /* _ASM_RISCV_ASM_H */
diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
new file mode 100644
index 0000000..a3f60a8
--- /dev/null
+++ b/arch/riscv/include/asm/barrier.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2012 ARM Ltd.
+ * Copyright (C) 2013 Regents of the University of California
+ * Copyright (C) 2017 SiFive
+ *
+ * Taken from Linux arch/riscv/include/asm/barrier.h, which is based on
+ * arch/arm/include/asm/barrier.h
+ */
+
+#ifndef _ASM_RISCV_BARRIER_H
+#define _ASM_RISCV_BARRIER_H
+
+#ifndef __ASSEMBLY__
+
+#define nop()		__asm__ __volatile__ ("nop")
+
+#define RISCV_FENCE(p, s) \
+	__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
+
+/* These barriers need to enforce ordering on both devices or memory. */
+#define mb()		RISCV_FENCE(iorw,iorw)
+#define rmb()		RISCV_FENCE(ir,ir)
+#define wmb()		RISCV_FENCE(ow,ow)
+
+/* These barriers do not need to enforce ordering on devices, just memory. */
+#define __smp_mb()	RISCV_FENCE(rw,rw)
+#define __smp_rmb()	RISCV_FENCE(r,r)
+#define __smp_wmb()	RISCV_FENCE(w,w)
+
+#define __smp_store_release(p, v)					\
+do {									\
+	compiletime_assert_atomic_type(*p);				\
+	RISCV_FENCE(rw,w);						\
+	WRITE_ONCE(*p, v);						\
+} while (0)
+
+#define __smp_load_acquire(p)						\
+({									\
+	typeof(*p) ___p1 = READ_ONCE(*p);				\
+	compiletime_assert_atomic_type(*p);				\
+	RISCV_FENCE(r,rw);						\
+	___p1;								\
+})
+
+/*
+ * This is a very specific barrier: it's currently only used in two places in
+ * the kernel, both in the scheduler.  See include/linux/spinlock.h for the two
+ * orderings it guarantees, but the "critical section is RCsc" guarantee
+ * mandates a barrier on RISC-V.  The sequence looks like:
+ *
+ *    lr.aq lock
+ *    sc    lock <= LOCKED
+ *    smp_mb__after_spinlock()
+ *    // critical section
+ *    lr    lock
+ *    sc.rl lock <= UNLOCKED
+ *
+ * The AQ/RL pair provides a RCpc critical section, but there's not really any
+ * way we can take advantage of that here because the ordering is only enforced
+ * on that one lock.  Thus, we're just doing a full fence.
+ */
+#define smp_mb__after_spinlock()	RISCV_FENCE(rw,rw)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_RISCV_BARRIER_H */
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h
new file mode 100644
index 0000000..536629b
--- /dev/null
+++ b/arch/riscv/include/asm/bitops.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ * Linus Torvalds (test_bit).
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_RISCV_BITOPS_H
+#define __ASM_RISCV_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+static inline void __set_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a |= mask;
+}
+
+#define PLATFORM__SET_BIT
+
+static inline void __clear_bit(int nr, void *addr)
+{
+	int *a = (int *)addr;
+	int mask;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	*a &= ~mask;
+}
+
+#define PLATFORM__CLEAR_BIT
+
+static inline void __change_bit(int nr, void *addr)
+{
+	int mask;
+	unsigned long *ADDR = (unsigned long *)addr;
+
+	ADDR += nr >> 5;
+	mask = 1 << (nr & 31);
+	*ADDR ^= mask;
+}
+
+static inline int __test_and_set_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	return retval;
+}
+
+static inline int __test_and_clear_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	return retval;
+}
+
+static inline int __test_and_change_bit(int nr, void *addr)
+{
+	int mask, retval;
+	unsigned int *a = (unsigned int *)addr;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	return retval;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *)addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+
+	return k;
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+/*
+ * redefined in include/linux/bitops.h
+ * #define ffs(x) generic_ffs(x)
+ */
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_RISCV_BITOPS_H */
diff --git a/arch/riscv/include/asm/byteorder.h b/arch/riscv/include/asm/byteorder.h
new file mode 100644
index 0000000..d26ac56
--- /dev/null
+++ b/arch/riscv/include/asm/byteorder.h
@@ -0,0 +1,35 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+
+#ifndef __ASM_RISCV_BYTEORDER_H
+#define __ASM_RISCV_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __RISCVEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
new file mode 100644
index 0000000..ec8fe20
--- /dev/null
+++ b/arch/riscv/include/asm/cache.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#ifndef _ASM_RISCV_CACHE_H
+#define _ASM_RISCV_CACHE_H
+
+/* cache */
+void	cache_flush(void);
+
+/*
+ * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	32
+#endif
+
+#endif /* _ASM_RISCV_CACHE_H */
diff --git a/arch/riscv/include/asm/config.h b/arch/riscv/include/asm/config.h
new file mode 100644
index 0000000..156cb94
--- /dev/null
+++ b/arch/riscv/include/asm/config.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#endif
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
new file mode 100644
index 0000000..d152074
--- /dev/null
+++ b/arch/riscv/include/asm/csr.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ *
+ * Taken from Linux arch/riscv/include/asm/csr.h
+ */
+
+#ifndef _ASM_RISCV_CSR_H
+#define _ASM_RISCV_CSR_H
+
+#include <asm/asm.h>
+#include <linux/const.h>
+
+/* Status register flags */
+#define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
+#define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
+#define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
+#define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */
+
+#define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
+#define SR_FS_OFF	_AC(0x00000000, UL)
+#define SR_FS_INITIAL	_AC(0x00002000, UL)
+#define SR_FS_CLEAN	_AC(0x00004000, UL)
+#define SR_FS_DIRTY	_AC(0x00006000, UL)
+
+#define SR_XS		_AC(0x00018000, UL) /* Extension Status */
+#define SR_XS_OFF	_AC(0x00000000, UL)
+#define SR_XS_INITIAL	_AC(0x00008000, UL)
+#define SR_XS_CLEAN	_AC(0x00010000, UL)
+#define SR_XS_DIRTY	_AC(0x00018000, UL)
+
+#ifndef CONFIG_64BIT
+#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
+#else
+#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
+#endif
+
+/* SATP flags */
+#ifndef CONFIG_64BIT
+#define SATP_PPN	_AC(0x003FFFFF, UL)
+#define SATP_MODE_32	_AC(0x80000000, UL)
+#define SATP_MODE	SATP_MODE_32
+#else
+#define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
+#define SATP_MODE_39	_AC(0x8000000000000000, UL)
+#define SATP_MODE	SATP_MODE_39
+#endif
+
+/* SCAUSE */
+#define SCAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
+
+#define IRQ_U_SOFT		0
+#define IRQ_S_SOFT		1
+#define IRQ_M_SOFT		3
+#define IRQ_U_TIMER		4
+#define IRQ_S_TIMER		5
+#define IRQ_M_TIMER		7
+#define IRQ_U_EXT		8
+#define IRQ_S_EXT		9
+#define IRQ_M_EXT		11
+
+#define EXC_INST_MISALIGNED	0
+#define EXC_INST_ACCESS		1
+#define EXC_BREAKPOINT		3
+#define EXC_LOAD_ACCESS		5
+#define EXC_STORE_ACCESS	7
+#define EXC_SYSCALL		8
+#define EXC_INST_PAGE_FAULT	12
+#define EXC_LOAD_PAGE_FAULT	13
+#define EXC_STORE_PAGE_FAULT	15
+
+/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
+#define MIE_MSIE		(_AC(0x1, UL) << IRQ_M_SOFT)
+#define SIE_SSIE		(_AC(0x1, UL) << IRQ_S_SOFT)
+#define SIE_STIE		(_AC(0x1, UL) << IRQ_S_TIMER)
+#define SIE_SEIE		(_AC(0x1, UL) << IRQ_S_EXT)
+
+#define CSR_FCSR		0x003
+#define CSR_CYCLE		0xc00
+#define CSR_TIME		0xc01
+#define CSR_INSTRET		0xc02
+#define CSR_SSTATUS		0x100
+#define CSR_SIE			0x104
+#define CSR_STVEC		0x105
+#define CSR_SCOUNTEREN		0x106
+#define CSR_SSCRATCH		0x140
+#define CSR_SEPC		0x141
+#define CSR_SCAUSE		0x142
+#define CSR_STVAL		0x143
+#define CSR_SIP			0x144
+#define CSR_SATP		0x180
+#define CSR_MSTATUS		0x300
+#define CSR_MISA		0x301
+#define CSR_MIE			0x304
+#define CSR_MTVEC		0x305
+#define CSR_MCOUNTEREN		0x306
+#define CSR_MSCRATCH		0x340
+#define CSR_MEPC		0x341
+#define CSR_MCAUSE		0x342
+#define CSR_MTVAL		0x343
+#define CSR_MIP			0x344
+#define CSR_CYCLEH		0xc80
+#define CSR_TIMEH		0xc81
+#define CSR_INSTRETH		0xc82
+#define CSR_MHARTID		0xf14
+
+#ifndef __ASSEMBLY__
+
+#define csr_swap(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_read(csr)						\
+({								\
+	register unsigned long __v;				\
+	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
+			      : "=r" (__v) :			\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_write(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#define csr_read_set(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_set(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#define csr_read_clear(csr, val)				\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
+			      : "=r" (__v) : "rK" (__v)		\
+			      : "memory");			\
+	__v;							\
+})
+
+#define csr_clear(csr, val)					\
+({								\
+	unsigned long __v = (unsigned long)(val);		\
+	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
+			      : : "rK" (__v)			\
+			      : "memory");			\
+})
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_RISCV_CSR_H */
diff --git a/arch/riscv/include/asm/dma-mapping.h b/arch/riscv/include/asm/dma-mapping.h
new file mode 100644
index 0000000..3d930c9
--- /dev/null
+++ b/arch/riscv/include/asm/dma-mapping.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __ASM_RISCV_DMA_MAPPING_H
+#define __ASM_RISCV_DMA_MAPPING_H
+
+#include <linux/dma-direction.h>
+
+#define dma_mapping_error(x, y)	0
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+	return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+	free(addr);
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+					   enum dma_data_direction dir)
+{
+	return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+				    unsigned long paddr)
+{
+}
+
+#endif /* __ASM_RISCV_DMA_MAPPING_H */
diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
new file mode 100644
index 0000000..a0695da
--- /dev/null
+++ b/arch/riscv/include/asm/encoding.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+ */
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#include <asm/csr.h>
+
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
+#define MODE_PREFIX(__suffix)	s##__suffix
+#else
+#define MODE_PREFIX(__suffix)	m##__suffix
+#endif
+
+#define MSTATUS_UIE	0x00000001
+#define MSTATUS_SIE	0x00000002
+#define MSTATUS_HIE	0x00000004
+#define MSTATUS_MIE	0x00000008
+#define MSTATUS_UPIE	0x00000010
+#define MSTATUS_SPIE	0x00000020
+#define MSTATUS_HPIE	0x00000040
+#define MSTATUS_MPIE	0x00000080
+#define MSTATUS_SPP	0x00000100
+#define MSTATUS_HPP	0x00000600
+#define MSTATUS_MPP	0x00001800
+#define MSTATUS_FS	0x00006000
+#define MSTATUS_XS	0x00018000
+#define MSTATUS_MPRV	0x00020000
+#define MSTATUS_PUM	0x00040000
+#define MSTATUS_VM	0x1F000000
+#define MSTATUS32_SD	0x80000000
+#define MSTATUS64_SD	0x8000000000000000
+
+#define MCAUSE32_CAUSE	0x7FFFFFFF
+#define MCAUSE64_CAUSE	0x7FFFFFFFFFFFFFFF
+#define MCAUSE32_INT	0x80000000
+#define MCAUSE64_INT	0x8000000000000000
+
+#define SSTATUS_UIE	0x00000001
+#define SSTATUS_SIE	0x00000002
+#define SSTATUS_UPIE	0x00000010
+#define SSTATUS_SPIE	0x00000020
+#define SSTATUS_SPP	0x00000100
+#define SSTATUS_FS	0x00006000
+#define SSTATUS_XS	0x00018000
+#define SSTATUS_PUM	0x00040000
+#define SSTATUS32_SD	0x80000000
+#define SSTATUS64_SD	0x8000000000000000
+
+#define MIP_SSIP	BIT(IRQ_S_SOFT)
+#define MIP_MSIP	BIT(IRQ_M_SOFT)
+#define MIP_STIP	BIT(IRQ_S_TIMER)
+#define MIP_MTIP	BIT(IRQ_M_TIMER)
+#define MIP_SEIP	BIT(IRQ_S_EXT)
+#define MIP_MEIP	BIT(IRQ_M_EXT)
+
+#define SIP_SSIP	MIP_SSIP
+#define SIP_STIP	MIP_STIP
+
+#define PRV_U	0
+#define PRV_S	1
+#define PRV_H	2
+#define PRV_M	3
+
+#define VM_MBARE	0
+#define VM_MBB		1
+#define VM_MBBID	2
+#define VM_SV32		8
+#define VM_SV39		9
+#define VM_SV48		10
+
+#define CAUSE_MISALIGNED_FETCH		0
+#define CAUSE_FETCH_ACCESS		1
+#define CAUSE_ILLEGAL_INSTRUCTION	2
+#define CAUSE_BREAKPOINT		3
+#define CAUSE_MISALIGNED_LOAD		4
+#define CAUSE_LOAD_ACCESS		5
+#define CAUSE_MISALIGNED_STORE		6
+#define CAUSE_STORE_ACCESS		7
+#define CAUSE_USER_ECALL		8
+#define CAUSE_SUPERVISOR_ECALL		9
+#define CAUSE_MACHINE_ECALL		11
+#define CAUSE_FETCH_PAGE_FAULT		12
+#define CAUSE_LOAD_PAGE_FAULT		13
+#define CAUSE_STORE_PAGE_FAULT		15
+
+#define DEFAULT_RSTVEC		0x00001000
+#define DEFAULT_NMIVEC		0x00001004
+#define DEFAULT_MTVEC		0x00001010
+#define CONFIG_STRING_ADDR	0x0000100C
+#define EXT_IO_BASE		0x40000000
+#define DRAM_BASE		0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V		0x001 // Valid
+#define PTE_TYPE	0x01E // Type
+#define PTE_R		0x020 // Referenced
+#define PTE_D		0x040 // Dirty
+#define PTE_SOFT	0x380 // Reserved for Software
+
+#define PTE_TYPE_TABLE		0x00
+#define PTE_TYPE_TABLE_GLOBAL	0x02
+#define PTE_TYPE_URX_SR		0x04
+#define PTE_TYPE_URWX_SRW	0x06
+#define PTE_TYPE_UR_SR		0x08
+#define PTE_TYPE_URW_SRW	0x0A
+#define PTE_TYPE_URX_SRX	0x0C
+#define PTE_TYPE_URWX_SRWX0x0E
+#define PTE_TYPE_SR		0x10
+#define PTE_TYPE_SRW		0x12
+#define PTE_TYPE_SRX		0x14
+#define PTE_TYPE_SRWX		0x16
+#define PTE_TYPE_SR_GLOBAL	0x18
+#define PTE_TYPE_SRW_GLOBAL	0x1A
+#define PTE_TYPE_SRX_GLOBAL	0x1C
+#define PTE_TYPE_SRWX_GLOBAL	0x1E
+
+#define PTE_PPN_SHIFT	10
+
+#define PTE_TABLE(PTE)	((0x0000000AU >> ((PTE) & 0x1F)) & 1)
+#define PTE_UR(PTE)	((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_UW(PTE)	((0x00008880U >> ((PTE) & 0x1F)) & 1)
+#define PTE_UX(PTE)	((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SR(PTE)	((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SW(PTE)	((0x88888880U >> ((PTE) & 0x1F)) & 1)
+#define PTE_SX(PTE)	((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
+
+#define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
+	typeof(_PTE) (PTE) = (_PTE); \
+	typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \
+	((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
+	(FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
+	((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
+
+#ifdef __riscv
+
+#ifdef CONFIG_64BIT
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define MCAUSE_INT MCAUSE64_INT
+# define MCAUSE_CAUSE MCAUSE64_CAUSE
+# define RISCV_PGLEVEL_BITS 9
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+# define MCAUSE_INT MCAUSE32_INT
+# define MCAUSE_CAUSE MCAUSE32_CAUSE
+#endif
+
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
+
+#endif /* __riscv */
+
+#endif /* RISCV_CSR_ENCODING_H */
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
new file mode 100644
index 0000000..b74bd7e
--- /dev/null
+++ b/arch/riscv/include/asm/global_data.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#include <asm/smp.h>
+
+/* Architecture-specific global data */
+struct arch_global_data {
+	long boot_hart;		/* boot hart id */
+#ifdef CONFIG_SIFIVE_CLINT
+	void __iomem *clint;	/* clint base address */
+#endif
+#ifdef CONFIG_ANDES_PLIC
+	void __iomem *plic;	/* plic base address */
+#endif
+#ifdef CONFIG_ANDES_PLMT
+	void __iomem *plmt;	/* plmt base address */
+#endif
+#ifdef CONFIG_SMP
+	struct ipi_data ipi[CONFIG_NR_CPUS];
+#endif
+#ifndef CONFIG_XIP
+	ulong available_harts;
+#endif
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/riscv/include/asm/gpio.h b/arch/riscv/include/asm/gpio.h
new file mode 100644
index 0000000..008d756
--- /dev/null
+++ b/arch/riscv/include/asm/gpio.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 SiFive, Inc.
+ */
+
+#include <asm-generic/gpio.h>
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
new file mode 100644
index 0000000..acf5a96
--- /dev/null
+++ b/arch/riscv/include/asm/io.h
@@ -0,0 +1,462 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ */
+#ifndef __ASM_RISCV_IO_H
+#define __ASM_RISCV_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/barrier.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+}
+
+#ifdef CONFIG_ARCH_MAP_SYSMEM
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+	if (paddr < PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE)
+		paddr = paddr | 0x40000000;
+	return (void *)(uintptr_t)paddr;
+}
+
+static inline void *unmap_sysmem(const void *vaddr)
+{
+	phys_addr_t paddr = (phys_addr_t)vaddr;
+
+	paddr = paddr & ~0x40000000;
+	return (void *)(uintptr_t)paddr;
+}
+
+static inline phys_addr_t map_to_sysmem(const void *ptr)
+{
+	return (phys_addr_t)(uintptr_t)ptr;
+}
+#endif
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(unsigned char *)(a))
+#define __arch_getw(a)			(*(unsigned short *)(a))
+#define __arch_getl(a)			(*(unsigned int *)(a))
+#define __arch_getq(a)			(*(unsigned long long *)(a))
+
+#define __arch_putb(v, a)		(*(unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(unsigned int *)(a) = (v))
+#define __arch_putq(v, a)		(*(unsigned long long *)(a) = (v))
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+#define __raw_writeq(v, a)		__arch_putq(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+#define __raw_readq(a)			__arch_getq(a)
+
+#define dmb()		mb()
+#define __iormb()	rmb()
+#define __iowmb()	wmb()
+
+static inline void writeb(u8 val, volatile void __iomem *addr)
+{
+	__iowmb();
+	__arch_putb(val, addr);
+}
+
+static inline void writew(u16 val, volatile void __iomem *addr)
+{
+	__iowmb();
+	__arch_putw(val, addr);
+}
+
+static inline void writel(u32 val, volatile void __iomem *addr)
+{
+	__iowmb();
+	__arch_putl(val, addr);
+}
+
+static inline void writeq(u64 val, volatile void __iomem *addr)
+{
+	__iowmb();
+	__arch_putq(val, addr);
+}
+
+static inline u8 readb(const volatile void __iomem *addr)
+{
+	u8	val;
+
+	val = __arch_getb(addr);
+	__iormb();
+	return val;
+}
+
+static inline u16 readw(const volatile void __iomem *addr)
+{
+	u16	val;
+
+	val = __arch_getw(addr);
+	__iormb();
+	return val;
+}
+
+static inline u32 readl(const volatile void __iomem *addr)
+{
+	u32	val;
+
+	val = __arch_getl(addr);
+	__iormb();
+	return val;
+}
+
+static inline u64 readq(const volatile void __iomem *addr)
+{
+	u64	val;
+
+	val = __arch_getq(addr);
+	__iormb();
+	return val;
+}
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+#define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v)			out_arch(l, le32, a, v)
+#define out_le16(a, v)			out_arch(w, le16, a, v)
+
+#define in_le32(a)			in_arch(l, le32, a)
+#define in_le16(a)			in_arch(w, le16, a)
+
+#define out_be32(a, v)			out_arch(l, be32, a, v)
+#define out_be16(a, v)			out_arch(w, be16, a, v)
+
+#define in_be32(a)			in_arch(l, be32, a)
+#define in_be16(a)			in_arch(w, be16, a)
+
+#define out_8(a, v)			__raw_writeb(v, a)
+#define in_8(a)				__raw_readb(a)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ * #include <asm/arch/io.h>
+ */
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The NDS32 doesn't have special IO access instructions just like ARM;
+ * all IO is memory mapped.
+ * Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v, p)			__raw_writeb(v, __io(p))
+#define outw(v, p)			__raw_writew(cpu_to_le16(v), __io(p))
+#define outl(v, p)			__raw_writel(cpu_to_le32(v), __io(p))
+
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p, d, l)			writesb(__io(p), d, l)
+#define outsw(p, d, l)			writesw(__io(p), d, l)
+#define outsl(p, d, l)			writesl(__io(p), d, l)
+
+#define insb(p, d, l)			readsb(__io(p), d, l)
+#define insw(p, d, l)			readsw(__io(p), d, l)
+#define insl(p, d, l)			readsl(__io(p), d, l)
+
+static inline void readsb(unsigned int *addr, void *data, int bytelen)
+{
+	unsigned char *ptr;
+	unsigned char *ptr2;
+
+	ptr = (unsigned char *)addr;
+	ptr2 = (unsigned char *)data;
+
+	while (bytelen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void readsw(unsigned int *addr, void *data, int wordlen)
+{
+	unsigned short *ptr;
+	unsigned short *ptr2;
+
+	ptr = (unsigned short *)addr;
+	ptr2 = (unsigned short *)data;
+
+	while (wordlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void readsl(unsigned int *addr, void *data, int longlen)
+{
+	unsigned int *ptr;
+	unsigned int *ptr2;
+
+	ptr = (unsigned int *)addr;
+	ptr2 = (unsigned int *)data;
+
+	while (longlen) {
+		*ptr2 = *ptr;
+		ptr2++;
+		longlen--;
+	}
+}
+
+static inline void writesb(unsigned int *addr, const void *data, int bytelen)
+{
+	unsigned char *ptr;
+	unsigned char *ptr2;
+
+	ptr = (unsigned char *)addr;
+	ptr2 = (unsigned char *)data;
+
+	while (bytelen) {
+		*ptr = *ptr2;
+		ptr2++;
+		bytelen--;
+	}
+}
+
+static inline void writesw(unsigned int *addr, const void *data, int wordlen)
+{
+	unsigned short *ptr;
+	unsigned short *ptr2;
+
+	ptr = (unsigned short *)addr;
+	ptr2 = (unsigned short *)data;
+
+	while (wordlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		wordlen--;
+	}
+}
+
+static inline void writesl(unsigned int *addr, const void *data, int longlen)
+{
+	unsigned int *ptr;
+	unsigned int *ptr2;
+
+	ptr = (unsigned int *)addr;
+	ptr2 = (unsigned int *)data;
+
+	while (longlen) {
+		*ptr = *ptr2;
+		ptr2++;
+		longlen--;
+	}
+}
+#endif
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)	outsb(port, from, len)
+#define outsw_p(port, from, len)	outsw(port, from, len)
+#define outsl_p(port, from, len)	outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+
+/*
+ * String version of IO memory access ops:
+ */
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = \
+			__raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = \
+			le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = \
+			le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)	_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+	eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int check_signature(ulong io_addr, const uchar *s, int len)
+{
+	int retval = 0;
+
+	do {
+		if (readb(io_addr) != *s)
+			goto out;
+		io_addr++;
+		s++;
+		len--;
+	} while (len);
+	retval = 1;
+out:
+	return retval;
+}
+#endif	/* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)			__raw_readb(__mem_isa(addr))
+#define isa_readw(addr)			__raw_readw(__mem_isa(addr))
+#define isa_readl(addr)			__raw_readl(__mem_isa(addr))
+#define isa_writeb(val, addr)		__raw_writeb(val, __mem_isa(addr))
+#define isa_writew(val, addr)		__raw_writew(val, __mem_isa(addr))
+#define isa_writel(val, addr)		__raw_writel(val, __mem_isa(addr))
+#define isa_memset_io(a, b, c)		_memset_io(__mem_isa(a), (b), (c))
+#define isa_memcpy_fromio(a, b, c)	_memcpy_fromio((a), __mem_isa(b), (c))
+#define isa_memcpy_toio(a, b, c)	_memcpy_toio(__mem_isa((a)), (b), (c))
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	eth_copy_and_sum((a), __mem_isa(b), (c), (d))
+
+static inline int
+isa_check_signature(ulong io_addr, const uchar *s, int len)
+{
+	int retval = 0;
+
+	do {
+		if (isa_readb(io_addr) != *s)
+			goto out;
+		io_addr++;
+		s++;
+		len--;
+	} while (len);
+	retval = 1;
+out:
+	return retval;
+}
+
+#else	/* __mem_isa */
+
+#define isa_readb(addr)			(__readwrite_bug("isa_readb"), 0)
+#define isa_readw(addr)			(__readwrite_bug("isa_readw"), 0)
+#define isa_readl(addr)			(__readwrite_bug("isa_readl"), 0)
+#define isa_writeb(val, addr)		__readwrite_bug("isa_writeb")
+#define isa_writew(val, addr)		__readwrite_bug("isa_writew")
+#define isa_writel(val, addr)		__readwrite_bug("isa_writel")
+#define isa_memset_io(a, b, c)		__readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a, b, c)	__readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a, b, c)	__readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a, b, c, d) \
+	__readwrite_bug("isa_eth_io_copy_and_sum")
+
+#define isa_check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_isa */
+#endif	/* __KERNEL__ */
+
+#include <asm-generic/io.h>
+
+#endif	/* __ASM_RISCV_IO_H */
diff --git a/arch/riscv/include/asm/linkage.h b/arch/riscv/include/asm/linkage.h
new file mode 100644
index 0000000..0c8822b
--- /dev/null
+++ b/arch/riscv/include/asm/linkage.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * U-Boot - linkage.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ */
+
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#endif
diff --git a/arch/riscv/include/asm/posix_types.h b/arch/riscv/include/asm/posix_types.h
new file mode 100644
index 0000000..0fc0520
--- /dev/null
+++ b/arch/riscv/include/asm/posix_types.h
@@ -0,0 +1,93 @@
+/*
+ * linux/include/asm-arm/posix_types.h
+ *
+ * Copyright (C) 1996-1998 Russell King.
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ *   25-10-2017	Modified for arch RISCV
+ */
+#ifndef __ARCH_RISCV_POSIX_TYPES_H
+#define __ARCH_RISCV_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+#ifdef __GNUC__
+typedef __SIZE_TYPE__		__kernel_size_t;
+#else
+typedef unsigned long		__kernel_size_t;
+#endif
+typedef long			__kernel_ssize_t;
+typedef long			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(_fd, fdsetp) \
+	typeof(_fd) (fd) = (_fd); \
+	(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1 << (fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(_fd, fdsetp) \
+	typeof(_fd) (fd) = (_fd); \
+	(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1 << (fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(_fd, fdsetp) \
+	typeof(_fd) (fd) = (_fd); \
+	((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1 << (fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(_fdsetp) \
+	typeof(_fdsetp) (fd) = (_fdsetp); \
+	(memset(fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif
+
+#endif /* __ARCH_RISCV_POSIX_TYPES_H */
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
new file mode 100644
index 0000000..fe35752
--- /dev/null
+++ b/arch/riscv/include/asm/processor.h
@@ -0,0 +1,26 @@
+/*
+ * linux/include/asm-arm/processor.h
+ *
+ * Copyright (C) 1995-2002 Russell King
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_RISCV_PROCESSOR_H
+#define __ASM_RISCV_PROCESSOR_H
+
+/**************************************************************
+ * CAUTION:
+ *   - do not implement for RISCV Arch yet.
+ *   - so far some files include /asm/processor.h, but
+ *     no one uses the macros defined in this head file.
+ **************************************************************/
+
+#endif /* __ASM_RISCV_PROCESSOR_H */
diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h
new file mode 100644
index 0000000..651078f
--- /dev/null
+++ b/arch/riscv/include/asm/ptrace.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_RISCV_PTRACE_H
+#define __ASM_RISCV_PTRACE_H
+
+struct pt_regs {
+	unsigned long sepc;
+	unsigned long ra;
+	unsigned long sp;
+	unsigned long gp;
+	unsigned long tp;
+	unsigned long t0;
+	unsigned long t1;
+	unsigned long t2;
+	unsigned long s0;
+	unsigned long s1;
+	unsigned long a0;
+	unsigned long a1;
+	unsigned long a2;
+	unsigned long a3;
+	unsigned long a4;
+	unsigned long a5;
+	unsigned long a6;
+	unsigned long a7;
+	unsigned long s2;
+	unsigned long s3;
+	unsigned long s4;
+	unsigned long s5;
+	unsigned long s6;
+	unsigned long s7;
+	unsigned long s8;
+	unsigned long s9;
+	unsigned long s10;
+	unsigned long s11;
+	unsigned long t3;
+	unsigned long t4;
+	unsigned long t5;
+	unsigned long t6;
+	/* Supervisor CSRs */
+	unsigned long sstatus;
+	unsigned long sbadaddr;
+	unsigned long scause;
+};
+
+#ifdef CONFIG_64BIT
+#define REG_FMT "%016lx"
+#else
+#define REG_FMT "%08lx"
+#endif
+
+#define user_mode(regs) (((regs)->sstatus & SR_PS) == 0)
+
+/* Helpers for working with the instruction pointer */
+#define GET_IP(regs) ((regs)->sepc)
+#define SET_IP(regs, val) (GET_IP(regs) = (val))
+
+static inline unsigned long instruction_pointer(struct pt_regs *regs)
+{
+	return GET_IP(regs);
+}
+
+static inline void instruction_pointer_set(struct pt_regs *regs, ulong val)
+{
+	SET_IP(regs, val);
+}
+
+#define profile_pc(regs) instruction_pointer(regs)
+
+/* Helpers for working with the user stack pointer */
+#define GET_USP(regs) ((regs)->sp)
+#define SET_USP(regs, val) (GET_USP(regs) = (val))
+
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+	return GET_USP(regs);
+}
+
+static inline void user_stack_pointer_set(struct pt_regs *regs, ulong val)
+{
+	SET_USP(regs, val);
+}
+
+/* Helpers for working with the frame pointer */
+#define GET_FP(regs) ((regs)->s0)
+#define SET_FP(regs, val) (GET_FP(regs) = (val))
+
+static inline unsigned long frame_pointer(struct pt_regs *regs)
+{
+	return GET_FP(regs);
+}
+
+static inline void frame_pointer_set(struct pt_regs *regs, ulong val)
+{
+	SET_FP(regs, val);
+}
+
+#endif /* __ASM_RISCV_PTRACE_H */
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
new file mode 100644
index 0000000..ced57de
--- /dev/null
+++ b/arch/riscv/include/asm/sbi.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Regents of the University of California
+ *
+ * Taken from Linux arch/riscv/include/asm/sbi.h
+ */
+
+#ifndef _ASM_RISCV_SBI_H
+#define _ASM_RISCV_SBI_H
+
+#include <linux/types.h>
+
+#define SBI_SET_TIMER 0
+#define SBI_CONSOLE_PUTCHAR 1
+#define SBI_CONSOLE_GETCHAR 2
+#define SBI_CLEAR_IPI 3
+#define SBI_SEND_IPI 4
+#define SBI_REMOTE_FENCE_I 5
+#define SBI_REMOTE_SFENCE_VMA 6
+#define SBI_REMOTE_SFENCE_VMA_ASID 7
+#define SBI_SHUTDOWN 8
+
+#define SBI_CALL(which, arg0, arg1, arg2) ({			\
+	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);	\
+	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);	\
+	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);	\
+	register uintptr_t a7 asm ("a7") = (uintptr_t)(which);	\
+	asm volatile ("ecall"					\
+		      : "+r" (a0)				\
+		      : "r" (a1), "r" (a2), "r" (a7)		\
+		      : "memory");				\
+	a0;							\
+})
+
+/* Lazy implementations until SBI is finalized */
+#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0)
+#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0)
+#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)
+
+static inline void sbi_console_putchar(int ch)
+{
+	SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
+}
+
+static inline int sbi_console_getchar(void)
+{
+	return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
+}
+
+static inline void sbi_set_timer(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+	SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
+#else
+	SBI_CALL_1(SBI_SET_TIMER, stime_value);
+#endif
+}
+
+static inline void sbi_shutdown(void)
+{
+	SBI_CALL_0(SBI_SHUTDOWN);
+}
+
+static inline void sbi_clear_ipi(void)
+{
+	SBI_CALL_0(SBI_CLEAR_IPI);
+}
+
+static inline void sbi_send_ipi(const unsigned long *hart_mask)
+{
+	SBI_CALL_1(SBI_SEND_IPI, hart_mask);
+}
+
+static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
+{
+	SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+					 unsigned long start,
+					 unsigned long size)
+{
+	SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask);
+}
+
+static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+					      unsigned long start,
+					      unsigned long size,
+					      unsigned long asid)
+{
+	SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask);
+}
+
+#endif
diff --git a/arch/riscv/include/asm/sections.h b/arch/riscv/include/asm/sections.h
new file mode 100644
index 0000000..9dd36dd
--- /dev/null
+++ b/arch/riscv/include/asm/sections.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_RISCV_SECTIONS_H
+#define __ASM_RISCV_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/riscv/include/asm/setjmp.h b/arch/riscv/include/asm/setjmp.h
new file mode 100644
index 0000000..72383d4
--- /dev/null
+++ b/arch/riscv/include/asm/setjmp.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Alexander Graf <agraf@suse.de>
+ */
+
+#ifndef _SETJMP_H_
+#define _SETJMP_H_	1
+
+/*
+ * This really should be opaque, but the EFI implementation wrongly
+ * assumes that a 'struct jmp_buf_data' is defined.
+ */
+struct jmp_buf_data {
+	/* x2, x8, x9, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, sp */
+	unsigned long s_regs[12];	/* s0 - s11 */
+	unsigned long ra;
+	unsigned long sp;
+};
+
+typedef struct jmp_buf_data jmp_buf[1];
+
+int setjmp(jmp_buf jmp);
+void longjmp(jmp_buf jmp, int ret);
+
+#endif /* _SETJMP_H_ */
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
new file mode 100644
index 0000000..bc863fd
--- /dev/null
+++ b/arch/riscv/include/asm/smp.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Fraunhofer AISEC,
+ * Lukas Auer <lukas.auer@aisec.fraunhofer.de>
+ */
+
+#ifndef _ASM_RISCV_SMP_H
+#define _ASM_RISCV_SMP_H
+
+/**
+ * struct ipi_data - Inter-processor interrupt (IPI) data structure
+ *
+ * IPIs are used for SMP support to communicate to other harts what function to
+ * call. Functions are in the form
+ * void (*addr)(ulong hart, ulong arg0, ulong arg1).
+ *
+ * The function address and the two arguments, arg0 and arg1, are stored in the
+ * IPI data structure. The hart ID is inserted by the hart handling the IPI and
+ * calling the function.
+ *
+ * @addr: Address of function
+ * @arg0: First argument of function
+ * @arg1: Second argument of function
+ */
+struct ipi_data {
+	ulong addr;
+	ulong arg0;
+	ulong arg1;
+};
+
+/**
+ * handle_ipi() - interrupt handler for software interrupts
+ *
+ * The IPI interrupt handler must be called to handle software interrupts. It
+ * calls the function specified in the hart's IPI data structure.
+ *
+ * @hart: Hart ID of the current hart
+ */
+void handle_ipi(ulong hart);
+
+/**
+ * smp_call_function() - Call a function on all other harts
+ *
+ * Send IPIs with the specified function call to all harts.
+ *
+ * @addr: Address of function
+ * @arg0: First argument of function
+ * @arg1: Second argument of function
+ * @return 0 if OK, -ve on error
+ */
+int smp_call_function(ulong addr, ulong arg0, ulong arg1);
+
+#endif
diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h
new file mode 100644
index 0000000..45c03fb
--- /dev/null
+++ b/arch/riscv/include/asm/spl.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on arch/mips/include/asm/spl.h.
+ *
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef _ASM_RISCV_SPL_H_
+#define _ASM_RISCV_SPL_H_
+
+enum {
+	BOOT_DEVICE_RAM,
+	BOOT_DEVICE_MMC1,
+	BOOT_DEVICE_MMC2,
+	BOOT_DEVICE_MMC2_2,
+	BOOT_DEVICE_NAND,
+	BOOT_DEVICE_ONENAND,
+	BOOT_DEVICE_NOR,
+	BOOT_DEVICE_UART,
+	BOOT_DEVICE_SPI,
+	BOOT_DEVICE_USB,
+	BOOT_DEVICE_SATA,
+	BOOT_DEVICE_I2C,
+	BOOT_DEVICE_BOARD,
+	BOOT_DEVICE_DFU,
+	BOOT_DEVICE_XIP,
+	BOOT_DEVICE_BOOTROM,
+	BOOT_DEVICE_NONE
+};
+
+#endif
diff --git a/arch/riscv/include/asm/string.h b/arch/riscv/include/asm/string.h
new file mode 100644
index 0000000..0fc3424
--- /dev/null
+++ b/arch/riscv/include/asm/string.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_RISCV_STRING_H
+#define __ASM_RISCV_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#undef __HAVE_ARCH_STRRCHR
+#undef __HAVE_ARCH_STRCHR
+#undef __HAVE_ARCH_MEMCPY
+#undef __HAVE_ARCH_MEMMOVE
+#undef __HAVE_ARCH_MEMCHR
+#undef __HAVE_ARCH_MEMZERO
+#undef __HAVE_ARCH_MEMSET
+
+#ifdef CONFIG_MARCO_MEMSET
+#define memset(_p, _v, _n)	\
+	(typeof(_p) (p) = (_p); \
+	 typeof(_v) (v) = (_v); \
+	 typeof(_n) (n) = (_n); \
+	 {								\
+		if ((n) != 0) {						\
+			if (__builtin_constant_p((v)) && (v) == 0)	\
+				__memzero((p), (n));			\
+			else						\
+				memset((p), (v), (n));			\
+		}							\
+		(p);							\
+	})
+
+#define memzero(_p, _n) \
+	(typeof(_p) (p) = (_p); \
+	 typeof(_n) (n) = (_n); \
+	 { if ((n) != 0) __memzero((p), (n)); (p); })
+#endif
+
+#endif /* __ASM_RISCV_STRING_H */
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
new file mode 100644
index 0000000..26a008c
--- /dev/null
+++ b/arch/riscv/include/asm/syscon.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _ASM_SYSCON_H
+#define _ASM_SYSCON_H
+
+/*
+ * System controllers in a RISC-V system
+ */
+enum {
+	RISCV_NONE,
+	RISCV_SYSCON_CLINT,	/* Core Local Interruptor (CLINT) */
+	RISCV_SYSCON_PLIC,	/* Platform Level Interrupt Controller (PLIC) */
+	RISCV_SYSCON_PLMT,	/* Platform Level Machine Timer (PLMT) */
+};
+
+#endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
new file mode 100644
index 0000000..a340475
--- /dev/null
+++ b/arch/riscv/include/asm/system.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#ifndef __ASM_RISCV_SYSTEM_H
+#define __ASM_RISCV_SYSTEM_H
+
+/*
+ * Interrupt configuring macros.
+ *
+ * TODO
+ *
+ */
+
+#endif	/* __ASM_RISCV_SYSTEM_H */
diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h
new file mode 100644
index 0000000..403cf9a
--- /dev/null
+++ b/arch/riscv/include/asm/types.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
+ * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
+ * Copyright (C) 2017 Rick Chen (rick@andestech.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_RISCV_TYPES_H
+#define __ASM_RISCV_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+typedef unsigned short umode_t;
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#ifdef CONFIG_ARCH_RV64I
+#define BITS_PER_LONG 64
+#else
+#define BITS_PER_LONG 32
+#endif
+
+#include <stddef.h>
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/riscv/include/asm/u-boot-riscv.h b/arch/riscv/include/asm/u-boot-riscv.h
new file mode 100644
index 0000000..49febd5
--- /dev/null
+++ b/arch/riscv/include/asm/u-boot-riscv.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#ifndef _U_BOOT_RISCV_H_
+#define _U_BOOT_RISCV_H_	1
+
+/* cpu/.../cpu.c */
+int cleanup_before_linux(void);
+
+/* board/.../... */
+int board_init(void);
+void board_quiesce_devices(void);
+
+#endif	/* _U_BOOT_RISCV_H_ */
diff --git a/arch/riscv/include/asm/u-boot.h b/arch/riscv/include/asm/u-boot.h
new file mode 100644
index 0000000..5ba8e77
--- /dev/null
+++ b/arch/riscv/include/asm/u-boot.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+#include <asm/u-boot-riscv.h>
+
+
+typedef struct bd_info {
+	unsigned long	bi_boot_params;	/* where this board expects params */
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	unsigned long	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned char	bi_enetaddr[6];
+
+	struct				/* RAM configuration */
+	{
+		unsigned long start;
+		unsigned long size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+} bd_t;
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_RISCV
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/riscv/include/asm/unaligned.h b/arch/riscv/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/riscv/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
diff --git a/arch/sandbox/include/asm/axi.h b/arch/sandbox/include/asm/axi.h
new file mode 100644
index 0000000..d483f7b
--- /dev/null
+++ b/arch/sandbox/include/asm/axi.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef __asm_axi_h
+#define __asm_axi_h
+
+#define axi_emul_get_ops(dev)	((struct axi_emul_ops *)(dev)->driver->ops)
+
+/**
+ * axi_sandbox_get_emul() - Retrieve a pointer to a AXI emulation device
+ * @bus:     The AXI bus from which to retrieve a emulation device
+ * @address: The address of a transfer that should be handled by a emulation
+ *	     device
+ * @length:  The data width of a transfer that should be handled by a emulation
+ *	     device
+ * @emulp:   Pointer to a buffer receiving the emulation device that handles
+ *	     the transfer specified by the address and length parameters
+ *
+ * To test the AXI uclass, we implement a simple AXI emulation device, which is
+ * a virtual device on a AXI bus that exposes a simple storage interface: When
+ * reading and writing from the device, the addresses are translated to offsets
+ * within the device's storage. For write accesses the data is written to the
+ * specified storage offset, and for read accesses the data is read from the
+ * specified storage offset.
+ *
+ * A DTS entry might look like this:
+ *
+ * axi: axi@0 {
+ *	compatible = "sandbox,axi";
+ *	#address-cells = <0x1>;
+ *	#size-cells = <0x1>;
+ *	store@0 {
+ *		compatible = "sandbox,sandbox_store";
+ *		reg = <0x0 0x400>;
+ *	};
+ * };
+ *
+ * This function may then be used to retrieve the pointer to the sandbox_store
+ * emulation device given the AXI bus device, and the data (address, data
+ * width) of a AXI transfer which should be handled by a emulation device.
+ *
+ * Return: 0 of OK, -ENODEV if no device capable of handling the specified
+ *	   transfer exists or the device could not be retrieved
+ */
+int axi_sandbox_get_emul(struct udevice *bus, ulong address, uint length,
+			 struct udevice **emulp);
+/**
+ * axi_get_store() - Get address of internal storage of a emulated AXI device
+ * @dev:	Emulated AXI device to get the pointer of the internal storage
+ *		for.
+ * @storep:	Pointer to the internal storage of the emulated AXI device.
+ *
+ * To preset or read back the contents internal storage of the emulated AXI
+ * device, this function returns the pointer to the storage. Changes to the
+ * contents of the storage are reflected when using the AXI read/write API
+ * methods, and vice versa, so by using this method expected read data can be
+ * set up in advance, and written data can be checked in unit tests.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int axi_get_store(struct udevice *dev, u8 **storep);
+
+#endif /* __asm_axi_h */
diff --git a/arch/sandbox/include/asm/bitops.h b/arch/sandbox/include/asm/bitops.h
new file mode 100644
index 0000000..f27d5e9
--- /dev/null
+++ b/arch/sandbox/include/asm/bitops.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * Modified from Linux arch/arm/include/asm/bitops.h
+ *
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require priviledged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_SANDBOX_BITOPS_H
+#define __ASM_SANDBOX_BITOPS_H
+
+#include <linux/compiler.h>
+#include <asm/system.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+#ifdef __KERNEL__
+
+#define smp_mb__before_clear_bit()	do { } while (0)
+#define smp_mb__after_clear_bit()	do { } while (0)
+
+/*
+ * Function prototypes to keep gcc -Wall happy.
+ */
+extern void set_bit(int nr, void *addr);
+
+extern void clear_bit(int nr, void *addr);
+
+extern void change_bit(int nr, void *addr);
+
+static inline void __change_bit(int nr, void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p ^= mask;
+}
+
+static inline int __test_and_set_bit(int nr, void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old | mask;
+	return (old & mask) != 0;
+}
+
+static inline int test_and_set_bit(int nr, void *addr)
+{
+	unsigned long __always_unused flags;
+	int out;
+
+	local_irq_save(flags);
+	out = __test_and_set_bit(nr, addr);
+	local_irq_restore(flags);
+
+	return out;
+}
+
+static inline int __test_and_clear_bit(int nr, void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old & ~mask;
+	return (old & mask) != 0;
+}
+
+static inline int test_and_clear_bit(int nr, void *addr)
+{
+	unsigned long __always_unused flags;
+	int out;
+
+	local_irq_save(flags);
+	out = __test_and_clear_bit(nr, addr);
+	local_irq_restore(flags);
+
+	return out;
+}
+
+extern int test_and_change_bit(int nr, void *addr);
+
+static inline int __test_and_change_bit(int nr, void *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
+
+	*p = old ^ mask;
+	return (old & mask) != 0;
+}
+
+extern int find_first_zero_bit(void *addr, unsigned size);
+extern int find_next_zero_bit(void *addr, int size, int offset);
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+	int k;
+
+	word = ~word;
+	k = 31;
+	if (word & 0x0000ffff) {
+		k -= 16; word <<= 16;
+	}
+	if (word & 0x00ff0000) {
+		k -= 8;  word <<= 8;
+	}
+	if (word & 0x0f000000) {
+		k -= 4;  word <<= 4;
+	}
+	if (word & 0x30000000) {
+		k -= 2;  word <<= 2;
+	}
+	if (word & 0x40000000)
+		k -= 1;
+	return k;
+}
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#define ext2_set_bit			test_and_set_bit
+#define ext2_clear_bit			test_and_clear_bit
+#define ext2_test_bit			test_bit
+#define ext2_find_first_zero_bit	find_first_zero_bit
+#define ext2_find_next_zero_bit		find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem. */
+#define minix_test_and_set_bit(nr, addr)	test_and_set_bit(nr, addr)
+#define minix_set_bit(nr, addr)			set_bit(nr, addr)
+#define minix_test_and_clear_bit(nr, addr)	test_and_clear_bit(nr, addr)
+#define minix_test_bit(nr, addr)		test_bit(nr, addr)
+#define minix_find_first_zero_bit(addr, size)	find_first_zero_bit(addr, size)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ARM_BITOPS_H */
diff --git a/arch/sandbox/include/asm/byteorder.h b/arch/sandbox/include/asm/byteorder.h
new file mode 100644
index 0000000..70b4c07
--- /dev/null
+++ b/arch/sandbox/include/asm/byteorder.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_SANDBOX_BYTEORDER_H
+#define __ASM_SANDBOX_BYTEORDER_H
+
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef CONFIG_SANDBOX_BIG_ENDIAN
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
diff --git a/arch/sandbox/include/asm/cache.h b/arch/sandbox/include/asm/cache.h
new file mode 100644
index 0000000..9348a13
--- /dev/null
+++ b/arch/sandbox/include/asm/cache.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __SANDBOX_CACHE_H__
+#define __SANDBOX_CACHE_H__
+
+/*
+ * For native compilation of the sandbox we should still align
+ * the contents of stack buffers to something reasonable.  The
+ * GCC macro __BIGGEST_ALIGNMENT__ is defined to be the maximum
+ * required alignment for any basic type.  This seems reasonable.
+ * This is however GCC specific so if we don't have that available
+ * assume that 16 is large enough.
+ */
+#ifdef __BIGGEST_ALIGNMENT__
+#define ARCH_DMA_MINALIGN	__BIGGEST_ALIGNMENT__
+#else
+#define ARCH_DMA_MINALIGN	16
+#endif
+#define CONFIG_SYS_CACHELINE_SIZE	ARCH_DMA_MINALIGN
+
+#endif /* __SANDBOX_CACHE_H__ */
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
new file mode 100644
index 0000000..2b1c49f
--- /dev/null
+++ b/arch/sandbox/include/asm/clk.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef __SANDBOX_CLK_H
+#define __SANDBOX_CLK_H
+
+#include <common.h>
+
+struct udevice;
+
+/**
+ * enum sandbox_clk_id - Identity of clocks implemented by the sandbox clock
+ * provider.
+ *
+ * These IDs are within/relative-to the clock provider.
+ */
+enum sandbox_clk_id {
+	SANDBOX_CLK_ID_SPI,
+	SANDBOX_CLK_ID_I2C,
+
+	SANDBOX_CLK_ID_COUNT,
+};
+
+/**
+ * enum sandbox_clk_test_id - Identity of the clocks consumed by the sandbox
+ * clock test device.
+ *
+ * These are the IDs the clock consumer knows the clocks as.
+ */
+enum sandbox_clk_test_id {
+	SANDBOX_CLK_TEST_ID_FIXED,
+	SANDBOX_CLK_TEST_ID_SPI,
+	SANDBOX_CLK_TEST_ID_I2C,
+
+	SANDBOX_CLK_TEST_ID_COUNT,
+};
+
+/**
+ * sandbox_clk_query_rate - Query the current rate of a sandbox clock.
+ *
+ * @dev:	The sandbox clock provider device.
+ * @id:		The clock to query.
+ * @return:	The rate of the clock.
+ */
+ulong sandbox_clk_query_rate(struct udevice *dev, int id);
+/**
+ * sandbox_clk_query_enable - Query the enable state of a sandbox clock.
+ *
+ * @dev:	The sandbox clock provider device.
+ * @id:		The clock to query.
+ * @return:	The rate of the clock.
+ */
+int sandbox_clk_query_enable(struct udevice *dev, int id);
+
+/**
+ * sandbox_clk_test_get - Ask the sandbox clock test device to request its
+ * clocks.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_get(struct udevice *dev);
+/**
+ * sandbox_clk_test_get_bulk - Ask the sandbox clock test device to request its
+ * clocks with the bulk clk API.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_get_bulk(struct udevice *dev);
+/**
+ * sandbox_clk_test_get_rate - Ask the sandbox clock test device to query a
+ * clock's rate.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @id:		The test device's clock ID to query.
+ * @return:	The rate of the clock.
+ */
+ulong sandbox_clk_test_get_rate(struct udevice *dev, int id);
+/**
+ * sandbox_clk_test_set_rate - Ask the sandbox clock test device to set a
+ * clock's rate.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @id:		The test device's clock ID to configure.
+ * @return:	The new rate of the clock.
+ */
+ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate);
+/**
+ * sandbox_clk_test_enable - Ask the sandbox clock test device to enable a
+ * clock.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @id:		The test device's clock ID to configure.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_enable(struct udevice *dev, int id);
+/**
+ * sandbox_clk_test_enable_bulk - Ask the sandbox clock test device to enable
+ * all clocks in it's clock bulk struct.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_enable_bulk(struct udevice *dev);
+/**
+ * sandbox_clk_test_disable - Ask the sandbox clock test device to disable a
+ * clock.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @id:		The test device's clock ID to configure.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_disable(struct udevice *dev, int id);
+/**
+ * sandbox_clk_test_disable_bulk - Ask the sandbox clock test device to disable
+ * all clocks in it's clock bulk struct.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_disable_bulk(struct udevice *dev);
+/**
+ * sandbox_clk_test_free - Ask the sandbox clock test device to free its
+ * clocks.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_free(struct udevice *dev);
+/**
+ * sandbox_clk_test_release_bulk - Ask the sandbox clock test device to release
+ * all clocks in it's clock bulk struct.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_release_bulk(struct udevice *dev);
+/**
+ * sandbox_clk_test_valid - Ask the sandbox clock test device to check its
+ * clocks are valid.
+ *
+ * @dev:	The sandbox clock test (client) devivce.
+ * @return:	0 if OK, or a negative error code.
+ */
+int sandbox_clk_test_valid(struct udevice *dev);
+
+#endif
diff --git a/arch/sandbox/include/asm/config.h b/arch/sandbox/include/asm/config.h
new file mode 100644
index 0000000..50215b3
--- /dev/null
+++ b/arch/sandbox/include/asm/config.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_SANDBOX_ARCH
+
+/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */
+#ifndef CONFIG_SANDBOX_SPI_MAX_BUS
+#define CONFIG_SANDBOX_SPI_MAX_BUS 1
+#endif
+#ifndef CONFIG_SANDBOX_SPI_MAX_CS
+#define CONFIG_SANDBOX_SPI_MAX_CS 10
+#endif
+
+#endif
diff --git a/arch/sandbox/include/asm/eth-raw-os.h b/arch/sandbox/include/asm/eth-raw-os.h
new file mode 100644
index 0000000..0b511db
--- /dev/null
+++ b/arch/sandbox/include/asm/eth-raw-os.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015 National Instruments
+ *
+ * (C) Copyright 2015
+ * Joe Hershberger <joe.hershberger@ni.com>
+ */
+
+#ifndef __ETH_RAW_OS_H
+#define __ETH_RAW_OS_H
+
+#define	IFNAMSIZ	16
+
+/**
+ * struct eth_sandbox_raw_priv - raw socket session
+ *
+ * sd: socket descriptor - the open socket during a session
+ * host_ifname: interface name on the host to use for sending our packets
+ * host_ifindex: interface index number on the host
+ * device: struct sockaddr_ll - the host interface packets move to/from
+ * local: 1 or 0 to select the local interface ('lo') or not
+ * local_bindsd: socket descriptor to prevent the kernel from sending
+ *		 a message to the server claiming the port is
+ *		 unreachable
+ * local_bind_udp_port: The UDP port number that we bound to
+ */
+struct eth_sandbox_raw_priv {
+	int sd;
+	char host_ifname[IFNAMSIZ];
+	unsigned int host_ifindex;
+	void *device;
+	int local;
+	int local_bind_sd;
+	unsigned short local_bind_udp_port;
+};
+
+/* A struct to mimic if_nameindex but that does not depend on Linux headers */
+struct sandbox_eth_raw_if_nameindex {
+	unsigned int if_index; /* Index of interface (1, 2, ...) */
+	char        *if_name;  /* Null-terminated name ("eth0", etc.) */
+};
+
+/* Enumerate host network interfaces */
+struct sandbox_eth_raw_if_nameindex *sandbox_eth_raw_if_nameindex(void);
+/* Free the data structure of enumerated network interfaces */
+void sandbox_eth_raw_if_freenameindex(struct sandbox_eth_raw_if_nameindex *ptr);
+
+/*
+ * Check if the interface named "ifname" is a localhost interface or not.
+ * ifname - the interface name on the host to check
+ *
+ * returns - 0 if real interface, 1 if local, negative if error
+ */
+int sandbox_eth_raw_os_is_local(const char *ifname);
+
+/*
+ * Look up the name of the interface based on the ifindex populated in priv.
+ *
+ * Overwrite the host_ifname member in priv based on looking up host_ifindex
+ *
+ * returns - 0 if success, negative if error
+ */
+int sandbox_eth_raw_os_idx_to_name(struct eth_sandbox_raw_priv *priv);
+
+int sandbox_eth_raw_os_start(struct eth_sandbox_raw_priv *priv,
+			     unsigned char *ethmac);
+int sandbox_eth_raw_os_send(void *packet, int length,
+			    struct eth_sandbox_raw_priv *priv);
+int sandbox_eth_raw_os_recv(void *packet, int *length,
+			    const struct eth_sandbox_raw_priv *priv);
+void sandbox_eth_raw_os_stop(struct eth_sandbox_raw_priv *priv);
+
+#endif /* __ETH_RAW_OS_H */
diff --git a/arch/sandbox/include/asm/eth.h b/arch/sandbox/include/asm/eth.h
new file mode 100644
index 0000000..477fa00
--- /dev/null
+++ b/arch/sandbox/include/asm/eth.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015 National Instruments
+ *
+ * (C) Copyright 2015
+ * Joe Hershberger <joe.hershberger@ni.com>
+ */
+
+#ifndef __ETH_H
+#define __ETH_H
+
+void sandbox_eth_disable_response(int index, bool disable);
+
+void sandbox_eth_skip_timeout(void);
+
+/*
+ * sandbox_eth_arp_req_to_reply()
+ *
+ * Check for an arp request to be sent. If so, inject a reply
+ *
+ * @dev: device that received the packet
+ * @packet: pointer to the received pacaket buffer
+ * @len: length of received packet
+ * @return 0 if injected, -EAGAIN if not
+ */
+int sandbox_eth_arp_req_to_reply(struct udevice *dev, void *packet,
+				 unsigned int len);
+
+/*
+ * sandbox_eth_ping_req_to_reply()
+ *
+ * Check for a ping request to be sent. If so, inject a reply
+ *
+ * @dev: device that received the packet
+ * @packet: pointer to the received pacaket buffer
+ * @len: length of received packet
+ * @return 0 if injected, -EAGAIN if not
+ */
+int sandbox_eth_ping_req_to_reply(struct udevice *dev, void *packet,
+				  unsigned int len);
+
+/*
+ * sandbox_eth_recv_arp_req()
+ *
+ * Inject an ARP request for this target
+ *
+ * @dev: device that received the packet
+ * @return 0 if injected, -EOVERFLOW if not
+ */
+int sandbox_eth_recv_arp_req(struct udevice *dev);
+
+/*
+ * sandbox_eth_recv_ping_req()
+ *
+ * Inject a ping request for this target
+ *
+ * @dev: device that received the packet
+ * @return 0 if injected, -EOVERFLOW if not
+ */
+int sandbox_eth_recv_ping_req(struct udevice *dev);
+
+/**
+ * A packet handler
+ *
+ * dev - device pointer
+ * pkt - pointer to the "sent" packet
+ * len - packet length
+ */
+typedef int sandbox_eth_tx_hand_f(struct udevice *dev, void *pkt,
+				   unsigned int len);
+
+/**
+ * struct eth_sandbox_priv - memory for sandbox mock driver
+ *
+ * fake_host_hwaddr - MAC address of mocked machine
+ * fake_host_ipaddr - IP address of mocked machine
+ * disabled - Will not respond
+ * recv_packet_buffer - buffers of the packet returned as received
+ * recv_packet_length - lengths of the packet returned as received
+ * recv_packets - number of packets returned
+ * tx_handler - function to generate responses to sent packets
+ * priv - a pointer to some structure a test may want to keep track of
+ */
+struct eth_sandbox_priv {
+	uchar fake_host_hwaddr[ARP_HLEN];
+	struct in_addr fake_host_ipaddr;
+	bool disabled;
+	uchar * recv_packet_buffer[PKTBUFSRX];
+	int recv_packet_length[PKTBUFSRX];
+	int recv_packets;
+	sandbox_eth_tx_hand_f *tx_handler;
+	void *priv;
+};
+
+/*
+ * Set packet handler
+ *
+ * handler - The func ptr to call on send. If NULL, set to default handler
+ */
+void sandbox_eth_set_tx_handler(int index, sandbox_eth_tx_hand_f *handler);
+
+/*
+ * Set priv ptr
+ *
+ * priv - priv void ptr to store in the device
+ */
+void sandbox_eth_set_priv(int index, void *priv);
+
+#endif /* __ETH_H */
diff --git a/arch/sandbox/include/asm/getopt.h b/arch/sandbox/include/asm/getopt.h
new file mode 100644
index 0000000..3048c2c
--- /dev/null
+++ b/arch/sandbox/include/asm/getopt.h
@@ -0,0 +1,72 @@
+/*
+ * Code for setting up command line flags like `./u-boot --help`
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __SANDBOX_GETOPT_H
+#define __SANDBOX_GETOPT_H
+
+struct sandbox_state;
+
+/*
+ * Internal structure for storing details about the flag.
+ * Most people should not have to dig around in this as
+ * it only gets parsed by the core sandbox code.  End
+ * consumer code should focus on the macros below and
+ * the callback function.
+ */
+struct sandbox_cmdline_option {
+	/* The long flag name: "help" for "--help" */
+	const char *flag;
+	/* The (optional) short flag name: "h" for "-h" */
+	int flag_short;
+	/* The help string shown to the user when processing --help */
+	const char *help;
+	/* Whether this flag takes an argument */
+	int has_arg;
+	/* Callback into the end consumer code with the option */
+	int (*callback)(struct sandbox_state *state, const char *opt);
+};
+
+/*
+ * Internal macro to expand the lower macros into the necessary
+ * magic junk that makes this all work.
+ */
+#define _SANDBOX_CMDLINE_OPT(f, s, ha, h) \
+	static struct sandbox_cmdline_option sandbox_cmdline_option_##f = { \
+		.flag = #f, \
+		.flag_short = s, \
+		.help = h, \
+		.has_arg = ha, \
+		.callback = sandbox_cmdline_cb_##f, \
+	}; \
+	/* Ppointer to the struct in a special section for the linker script */ \
+	static __attribute__((section(".u_boot_sandbox_getopt"), used)) \
+		struct sandbox_cmdline_option \
+			*sandbox_cmdline_option_##f##_ptr = \
+			&sandbox_cmdline_option_##f
+
+/**
+ * Macros for end code to declare new command line flags.
+ *
+ * @param f   The long flag name e.g. help
+ * @param ha  Does the flag have an argument e.g. 0/1
+ * @param h   The help string displayed when showing --help
+ *
+ * This invocation:
+ *   SANDBOX_CMDLINE_OPT(foo, 0, "The foo arg");
+ * Will create a new flag named "--foo" (no short option) that takes
+ * no argument.  If the user specifies "--foo", then the callback func
+ * sandbox_cmdline_cb_foo() will automatically be called.
+ */
+#define SANDBOX_CMDLINE_OPT(f, ha, h) _SANDBOX_CMDLINE_OPT(f, 0, ha, h)
+/*
+ * Same as above, but @s is used to specify a short flag e.g.
+ *   SANDBOX_CMDLINE_OPT(foo, 'f', 0, "The foo arg");
+ */
+#define SANDBOX_CMDLINE_OPT_SHORT(f, s, ha, h) _SANDBOX_CMDLINE_OPT(f, s, ha, h)
+
+#endif
diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h
new file mode 100644
index 0000000..f4ce72d
--- /dev/null
+++ b/arch/sandbox/include/asm/global_data.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+/* Architecture-specific global data */
+struct arch_global_data {
+	uint8_t		*ram_buf;	/* emulated RAM buffer */
+	void		*text_base;	/* pointer to base of text region */
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR     extern gd_t *gd
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h
new file mode 100644
index 0000000..de8ac37
--- /dev/null
+++ b/arch/sandbox/include/asm/gpio.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This is the interface to the sandbox GPIO driver for test code which
+ * wants to change the GPIO values reported to U-Boot.
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_SANDBOX_GPIO_H
+#define __ASM_SANDBOX_GPIO_H
+
+/*
+ * We use the generic interface, and add a back-channel.
+ *
+ * The back-channel functions are declared in this file. They should not be used
+ * except in test code.
+ *
+ * Test code can, for example, call sandbox_gpio_set_value() to set the value of
+ * a simulated GPIO. From then on, normal code in U-Boot will see this new
+ * value when it calls gpio_get_value().
+ *
+ * NOTE: DO NOT use the functions in this file except in test code!
+ */
+#include <asm-generic/gpio.h>
+
+/**
+ * Return the simulated value of a GPIO (used only in sandbox test code)
+ *
+ * @param dev		device to use
+ * @param offset	GPIO offset within bank
+ * @return -1 on error, 0 if GPIO is low, >0 if high
+ */
+int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset);
+
+/**
+ * Set the simulated value of a GPIO (used only in sandbox test code)
+ *
+ * @param dev		device to use
+ * @param offset	GPIO offset within bank
+ * @param value		value to set (0 for low, non-zero for high)
+ * @return -1 on error, 0 if ok
+ */
+int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value);
+
+/**
+ * Set or reset the simulated open drain mode of a GPIO (used only in sandbox
+ * test code)
+ *
+ * @param gp	GPIO number
+ * @param value	value to set (0 for enabled open drain mode, non-zero for
+ * 		disabled)
+ * @return -1 on error, 0 if ok
+ */
+int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value);
+
+/**
+ * Return the state of the simulated open drain mode of a GPIO (used only in
+ * sandbox test code)
+ *
+ * @param gp	GPIO number
+ * @return -1 on error, 0 if GPIO is input, >0 if output
+ */
+int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset);
+
+/**
+ * Return the simulated direction of a GPIO (used only in sandbox test code)
+ *
+ * @param dev		device to use
+ * @param offset	GPIO offset within bank
+ * @return -1 on error, 0 if GPIO is input, >0 if output
+ */
+int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset);
+
+/**
+ * Set the simulated direction of a GPIO (used only in sandbox test code)
+ *
+ * @param dev		device to use
+ * @param offset	GPIO offset within bank
+ * @param output 	0 to set as input, 1 to set as output
+ * @return -1 on error, 0 if ok
+ */
+int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset,
+			       int output);
+
+#endif
diff --git a/arch/sandbox/include/asm/handoff.h b/arch/sandbox/include/asm/handoff.h
new file mode 100644
index 0000000..be4e7b0
--- /dev/null
+++ b/arch/sandbox/include/asm/handoff.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Architecture-specific SPL handoff information for sandbox
+ *
+ * Copyright 2018 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __handoff_h
+#define __handoff_h
+
+#define TEST_HANDOFF_MAGIC	0x14f93c7b
+
+struct arch_spl_handoff {
+	ulong	magic;		/* Used for testing */
+};
+
+#endif
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
new file mode 100644
index 0000000..4a35c41
--- /dev/null
+++ b/arch/sandbox/include/asm/io.h
@@ -0,0 +1,234 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __SANDBOX_ASM_IO_H
+#define __SANDBOX_ASM_IO_H
+
+enum sandboxio_size_t {
+	SB_SIZE_8,
+	SB_SIZE_16,
+	SB_SIZE_32,
+	SB_SIZE_64,
+};
+
+void *phys_to_virt(phys_addr_t paddr);
+#define phys_to_virt phys_to_virt
+
+phys_addr_t virt_to_phys(void *vaddr);
+#define virt_to_phys virt_to_phys
+
+void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags);
+#define map_physmem map_physmem
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+void unmap_physmem(const void *vaddr, unsigned long flags);
+#define unmap_physmem unmap_physmem
+
+#include <asm-generic/io.h>
+
+/* For sandbox, we want addresses to point into our RAM buffer */
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+	return map_physmem(paddr, len, MAP_WRBACK);
+}
+
+/* Remove a previous mapping */
+static inline void unmap_sysmem(const void *vaddr)
+{
+	unmap_physmem(vaddr, MAP_WRBACK);
+}
+
+/* Map from a pointer to our RAM buffer */
+phys_addr_t map_to_sysmem(const void *ptr);
+
+unsigned int sandbox_read(const void *addr, enum sandboxio_size_t size);
+void sandbox_write(const void *addr, unsigned int val,
+		   enum sandboxio_size_t size);
+
+#define readb(addr) sandbox_read((const void *)addr, SB_SIZE_8)
+#define readw(addr) sandbox_read((const void *)addr, SB_SIZE_16)
+#define readl(addr) sandbox_read((const void *)addr, SB_SIZE_32)
+#ifdef CONFIG_SANDBOX64
+#define readq(addr) sandbox_read((const void *)addr, SB_SIZE_64)
+#endif
+#define writeb(v, addr) sandbox_write((const void *)addr, v, SB_SIZE_8)
+#define writew(v, addr) sandbox_write((const void *)addr, v, SB_SIZE_16)
+#define writel(v, addr) sandbox_write((const void *)addr, v, SB_SIZE_32)
+#ifdef CONFIG_SANDBOX64
+#define writeq(v, addr) sandbox_write((const void *)addr, v, SB_SIZE_64)
+#endif
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define out_arch(type,endian,a,v)	write##type(cpu_to_##endian(v),a)
+#define in_arch(type,endian,a)		endian##_to_cpu(read##type(a))
+
+#define out_le64(a,v)	out_arch(q,le64,a,v)
+#define out_le32(a,v)	out_arch(l,le32,a,v)
+#define out_le16(a,v)	out_arch(w,le16,a,v)
+
+#define in_le64(a)	in_arch(q,le64,a)
+#define in_le32(a)	in_arch(l,le32,a)
+#define in_le16(a)	in_arch(w,le16,a)
+
+#define out_be32(a,v)	out_arch(l,be32,a,v)
+#define out_be16(a,v)	out_arch(w,be16,a,v)
+
+#define in_be32(a)	in_arch(l,be32,a)
+#define in_be16(a)	in_arch(w,be16,a)
+
+#define out_8(a,v)	writeb(v,a)
+#define in_8(a)		readb(a)
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+/* I/O access functions */
+int _inl(unsigned int addr);
+int _inw(unsigned int addr);
+int _inb(unsigned int addr);
+
+void _outl(unsigned int value, unsigned int addr);
+void _outw(unsigned int value, unsigned int addr);
+void _outb(unsigned int value, unsigned int addr);
+
+#define inb(port)	_inb((uintptr_t)(port))
+#define inw(port)	_inw((uintptr_t)(port))
+#define inl(port)	_inl((uintptr_t)(port))
+
+#define outb(val, port)	_outb(val, (uintptr_t)(port))
+#define outw(val, port)	_outw(val, (uintptr_t)(port))
+#define outl(val, port)	_outl(val, (uintptr_t)(port))
+
+#define out_arch(type,endian,a,v)	write##type(cpu_to_##endian(v),a)
+#define in_arch(type,endian,a)		endian##_to_cpu(read##type(a))
+
+#define out_le32(a,v)	out_arch(l,le32,a,v)
+#define out_le16(a,v)	out_arch(w,le16,a,v)
+
+#define in_le32(a)	in_arch(l,le32,a)
+#define in_le16(a)	in_arch(w,le16,a)
+
+#define out_be32(a,v)	out_arch(l,be32,a,v)
+#define out_be16(a,v)	out_arch(w,be16,a,v)
+
+#define in_be32(a)	in_arch(l,be32,a)
+#define in_be16(a)	in_arch(w,be16,a)
+
+#define out_8(a,v)	writeb(v,a)
+#define in_8(a)		readb(a)
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+static inline void _insw(volatile u16 *port, void *buf, int ns)
+{
+}
+
+static inline void _outsw(volatile u16 *port, const void *buf, int ns)
+{
+}
+
+static inline void memset_io(volatile void *addr, unsigned char val, int count)
+{
+}
+
+static inline void memcpy_fromio(void *dst, const volatile void *src, int count)
+{
+}
+
+static inline void memcpy_toio(volatile void *dst, const void *src, int count)
+{
+}
+
+#define insw(port, buf, ns)		_insw((u16 *)port, buf, ns)
+#define outsw(port, buf, ns)		_outsw((u16 *)port, buf, ns)
+
+/* IO space accessors */
+#define clrio(type, addr, clear) \
+	out##type(in##type(addr) & ~(clear), (addr))
+
+#define setio(type, addr, set) \
+	out##type(in##type(addr) | (set), (addr))
+
+#define clrsetio(type, addr, clear, set) \
+	out##type((in##type(addr) & ~(clear)) | (set), (addr))
+
+#define clrio_32(addr, clear) clrio(l, addr, clear)
+#define clrio_16(addr, clear) clrio(w, addr, clear)
+#define clrio_8(addr, clear) clrio(b, addr, clear)
+
+#define setio_32(addr, set) setio(l, addr, set)
+#define setio_16(addr, set) setio(w, addr, set)
+#define setio_8(addr, set) setio(b, addr, set)
+
+#define clrsetio_32(addr, clear, set) clrsetio(l, addr, clear, set)
+#define clrsetio_16(addr, clear, set) clrsetio(w, addr, clear, set)
+#define clrsetio_8(addr, clear, set) clrsetio(b, addr, clear, set)
+
+#include <iotrace.h>
+#include <asm/types.h>
+
+#endif
diff --git a/arch/sandbox/include/asm/linkage.h b/arch/sandbox/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/sandbox/include/asm/linkage.h
diff --git a/arch/sandbox/include/asm/mbox.h b/arch/sandbox/include/asm/mbox.h
new file mode 100644
index 0000000..70f36d7
--- /dev/null
+++ b/arch/sandbox/include/asm/mbox.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef __SANDBOX_MBOX_H
+#define __SANDBOX_MBOX_H
+
+#include <common.h>
+
+#define SANDBOX_MBOX_PING_XOR 0x12345678
+
+struct udevice;
+
+int sandbox_mbox_test_get(struct udevice *dev);
+int sandbox_mbox_test_send(struct udevice *dev, uint32_t msg);
+int sandbox_mbox_test_recv(struct udevice *dev, uint32_t *msg);
+int sandbox_mbox_test_free(struct udevice *dev);
+
+#endif
diff --git a/arch/sandbox/include/asm/posix_types.h b/arch/sandbox/include/asm/posix_types.h
new file mode 100644
index 0000000..ec18ed7
--- /dev/null
+++ b/arch/sandbox/include/asm/posix_types.h
@@ -0,0 +1,57 @@
+/*
+ *  linux/include/asm-arm/posix_types.h
+ *
+ *  Copyright (C) 1996-1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996	RMK	Created
+ */
+#ifndef __ARCH_ARM_POSIX_TYPES_H
+#define __ARCH_ARM_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+#if CONFIG_SANDBOX_BITS_PER_LONG == 32
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+#else
+typedef unsigned long		__kernel_size_t;
+typedef long			__kernel_ssize_t;
+typedef long			__kernel_ptrdiff_t;
+#endif
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char			*__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+#endif
diff --git a/arch/sandbox/include/asm/power-domain.h b/arch/sandbox/include/asm/power-domain.h
new file mode 100644
index 0000000..1845bc8
--- /dev/null
+++ b/arch/sandbox/include/asm/power-domain.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef __SANDBOX_POWER_DOMAIN_H
+#define __SANDBOX_POWER_DOMAIN_H
+
+#include <common.h>
+
+struct udevice;
+
+int sandbox_power_domain_query(struct udevice *dev, unsigned long id);
+
+int sandbox_power_domain_test_get(struct udevice *dev);
+int sandbox_power_domain_test_on(struct udevice *dev);
+int sandbox_power_domain_test_off(struct udevice *dev);
+int sandbox_power_domain_test_free(struct udevice *dev);
+
+#endif
diff --git a/arch/sandbox/include/asm/processor.h b/arch/sandbox/include/asm/processor.h
new file mode 100644
index 0000000..8dced60
--- /dev/null
+++ b/arch/sandbox/include/asm/processor.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc
+ */
+
+#ifndef _ASM_PROCESSOR_H
+#define _ASM_PROCESSOR_H
+
+/* This file is required for PCI */
+
+#endif
diff --git a/arch/sandbox/include/asm/ptrace.h b/arch/sandbox/include/asm/ptrace.h
new file mode 100644
index 0000000..78e5817
--- /dev/null
+++ b/arch/sandbox/include/asm/ptrace.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_SANDBOX_PTRACE_H
+#define __ASM_SANDBOX_PTRACE_H
+
+#ifndef __ASSEMBLY__
+/* This is not used in the sandbox architecture, but required by U-Boot */
+struct pt_regs {
+};
+
+#ifdef __KERNEL__
+extern void show_regs(struct pt_regs *);
+
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h
new file mode 100644
index 0000000..c4205ea
--- /dev/null
+++ b/arch/sandbox/include/asm/reset.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef __SANDBOX_RESET_H
+#define __SANDBOX_RESET_H
+
+#include <common.h>
+
+struct udevice;
+
+int sandbox_reset_query(struct udevice *dev, unsigned long id);
+
+int sandbox_reset_test_get(struct udevice *dev);
+int sandbox_reset_test_get_bulk(struct udevice *dev);
+int sandbox_reset_test_assert(struct udevice *dev);
+int sandbox_reset_test_assert_bulk(struct udevice *dev);
+int sandbox_reset_test_deassert(struct udevice *dev);
+int sandbox_reset_test_deassert_bulk(struct udevice *dev);
+int sandbox_reset_test_free(struct udevice *dev);
+int sandbox_reset_test_release_bulk(struct udevice *dev);
+
+#endif
diff --git a/arch/sandbox/include/asm/rtc.h b/arch/sandbox/include/asm/rtc.h
new file mode 100644
index 0000000..1fbfea7
--- /dev/null
+++ b/arch/sandbox/include/asm/rtc.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Simulate an I2C real time clock
+ *
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __asm_rtc_h
+#define __asm_rtc_h
+
+/* Register numbers in the sandbox RTC */
+enum {
+	REG_SEC		= 5,
+	REG_MIN,
+	REG_HOUR,
+	REG_MDAY,
+	REG_MON,
+	REG_YEAR,
+	REG_WDAY,
+
+	REG_RESET	= 0x20,
+
+	REG_COUNT	= 0x80,
+};
+
+#endif
diff --git a/arch/sandbox/include/asm/sdl.h b/arch/sandbox/include/asm/sdl.h
new file mode 100644
index 0000000..c45dbdd
--- /dev/null
+++ b/arch/sandbox/include/asm/sdl.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ */
+
+#ifndef __SANDBOX_SDL_H
+#define __SANDBOX_SDL_H
+
+#include <errno.h>
+
+#ifdef CONFIG_SANDBOX_SDL
+
+/**
+ * sandbox_sdl_init_display() - Set up SDL video ready for use
+ *
+ * @width:	Window width in pixels
+ * @height	Window height in pixels
+ * @log2_bpp:	Log to base 2 of the number of bits per pixel. So a 32bpp
+ *		display will pass 5, since 2*5 = 32
+ * @return 0 if OK, -ENODEV if no device, -EIO if SDL failed to initialize
+ *		and -EPERM if the video failed to come up.
+ */
+int sandbox_sdl_init_display(int width, int height, int log2_bpp);
+
+/**
+ * sandbox_sdl_sync() - Sync current U-Boot LCD frame buffer to SDL
+ *
+ * This must be called periodically to update the screen for SDL so that the
+ * user can see it.
+ *
+ * @lcd_base: Base of frame buffer
+ * @return 0 if screen was updated, -ENODEV is there is no screen.
+ */
+int sandbox_sdl_sync(void *lcd_base);
+
+/**
+ * sandbox_sdl_scan_keys() - scan for pressed keys
+ *
+ * Works out which keys are pressed and returns a list
+ *
+ * @key:	Array to receive keycodes
+ * @max_keys:	Size of array
+ * @return number of keycodes found, 0 if none, -ENODEV if no keyboard
+ */
+int sandbox_sdl_scan_keys(int key[], int max_keys);
+
+/**
+ * sandbox_sdl_key_pressed() - check if a particular key is pressed
+ *
+ * @keycode:	Keycode to check (KEY_... - see include/linux/input.h
+ * @return 0 if pressed, -ENOENT if not pressed. -ENODEV if keybord not
+ * available,
+ */
+int sandbox_sdl_key_pressed(int keycode);
+
+/**
+ * sandbox_sdl_sound_play() - Play a sound
+ *
+ * @data:	Data to play (typically 16-bit)
+ * @count:	Number of bytes in data
+ */
+int sandbox_sdl_sound_play(const void *data, uint count);
+
+/**
+ * sandbox_sdl_sound_stop() - stop playing a sound
+ *
+ * @return 0 if OK, -ENODEV if no sound is available
+ */
+int sandbox_sdl_sound_stop(void);
+
+/**
+ * sandbox_sdl_sound_init() - set up the sound system
+ *
+ * @rate:	Sample rate to use
+ * @channels:	Number of channels to use (1=mono, 2=stereo)
+ * @return 0 if OK, -ENODEV if no sound is available
+ */
+int sandbox_sdl_sound_init(int rate, int channels);
+
+#else
+static inline int sandbox_sdl_init_display(int width, int height,
+					    int log2_bpp)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_sync(void *lcd_base)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_scan_keys(int key[], int max_keys)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_key_pressed(int keycode)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_sound_start(uint frequency)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_sound_play(const void *data, uint count)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_sound_stop(void)
+{
+	return -ENODEV;
+}
+
+static inline int sandbox_sdl_sound_init(int rate, int channels)
+{
+	return -ENODEV;
+}
+
+#endif
+
+#endif
diff --git a/arch/sandbox/include/asm/sections.h b/arch/sandbox/include/asm/sections.h
new file mode 100644
index 0000000..fbc1bd1
--- /dev/null
+++ b/arch/sandbox/include/asm/sections.h
@@ -0,0 +1,24 @@
+/*
+ * decls for symbols defined in the linker script
+ *
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __SANDBOX_SECTIONS_H
+#define __SANDBOX_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+struct sandbox_cmdline_option;
+
+extern struct sandbox_cmdline_option *__u_boot_sandbox_option_start[],
+	*__u_boot_sandbox_option_end[];
+
+static inline size_t __u_boot_sandbox_option_count(void)
+{
+	return __u_boot_sandbox_option_end - __u_boot_sandbox_option_start;
+}
+
+#endif
diff --git a/arch/sandbox/include/asm/setjmp.h b/arch/sandbox/include/asm/setjmp.h
new file mode 100644
index 0000000..001c7ea
--- /dev/null
+++ b/arch/sandbox/include/asm/setjmp.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) 2018 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _SETJMP_H_
+#define _SETJMP_H_
+
+struct jmp_buf_data {
+	/*
+	 * We're not sure how long this should be:
+	 *
+	 *   amd64: 200 bytes
+	 *   arm64: 392 bytes
+	 *   armhf: 392 bytes
+	 *
+	 * So allow space for all of those, plus some extra.
+	 * We don't need to worry about 16-byte alignment, since this does not
+	 * run on Windows.
+	 */
+	ulong data[128];
+};
+
+typedef struct jmp_buf_data jmp_buf[1];
+
+/*
+ * We have to directly link with the system versions of
+ * setjmp/longjmp, because setjmp must not return as otherwise
+ * the stack may become invalid.
+ */
+int setjmp(jmp_buf jmp);
+__noreturn void longjmp(jmp_buf jmp, int ret);
+
+#endif /* _SETJMP_H_ */
diff --git a/arch/sandbox/include/asm/spi.h b/arch/sandbox/include/asm/spi.h
new file mode 100644
index 0000000..98e1826
--- /dev/null
+++ b/arch/sandbox/include/asm/spi.h
@@ -0,0 +1,45 @@
+/*
+ * Simulate a SPI port and clients (see doc/arch/sandbox.rst for details)
+ *
+ * Copyright (c) 2011-2013 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_SPI_H__
+#define __ASM_SPI_H__
+
+#include <linux/types.h>
+
+/*
+ * The interface between the SPI bus and the SPI client.  The bus will
+ * instantiate a client, and that then call into it via these entry
+ * points.  These should be enough for the client to emulate the SPI
+ * device just like the real hardware.
+ */
+struct sandbox_spi_emu_ops {
+	/* The bus wants to instantiate a new client, so setup everything */
+	int (*setup)(void **priv, const char *spec);
+	/* The bus is done with us, so break things down */
+	void (*free)(void *priv);
+	/* The CS has been "activated" -- we won't worry about low/high */
+	void (*cs_activate)(void *priv);
+	/* The CS has been "deactivated" -- we won't worry about low/high */
+	void (*cs_deactivate)(void *priv);
+	/* The client is rx-ing bytes from the bus, so it should tx some */
+	int (*xfer)(void *priv, const u8 *rx, u8 *tx, uint bytes);
+};
+
+/*
+ * Extract the bus/cs from the spi spec and return the start of the spi
+ * client spec.  If the bus/cs are invalid for the current config, then
+ * it returns NULL.
+ *
+ * Example: arg="0:1:foo" will set bus to 0, cs to 1, and return "foo"
+ */
+const char *sandbox_spi_parse_spec(const char *arg, unsigned long *bus,
+				   unsigned long *cs);
+
+#endif
diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h
new file mode 100644
index 0000000..51e9d95
--- /dev/null
+++ b/arch/sandbox/include/asm/spl.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __asm_spl_h
+#define __asm_spl_h
+
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+
+enum {
+	BOOT_DEVICE_BOARD,
+};
+
+#endif
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
new file mode 100644
index 0000000..ad3e94b
--- /dev/null
+++ b/arch/sandbox/include/asm/state.h
@@ -0,0 +1,277 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011-2012 The Chromium OS Authors.
+ */
+
+#ifndef __SANDBOX_STATE_H
+#define __SANDBOX_STATE_H
+
+#include <config.h>
+#include <sysreset.h>
+#include <stdbool.h>
+#include <linux/list.h>
+#include <linux/stringify.h>
+
+/**
+ * Selects the behavior of the serial terminal.
+ *
+ * If Ctrl-C is processed by U-Boot, then the only way to quit sandbox is with
+ * the 'reset' command, or equivalent.
+ *
+ * If the terminal is cooked, then Ctrl-C will terminate U-Boot, and the
+ * command line will not be quite such a faithful emulation.
+ *
+ * Options are:
+ *
+ *	raw-with-sigs		- Raw, but allow signals (Ctrl-C will quit)
+ *	raw			- Terminal is always raw
+ *	cooked			- Terminal is always cooked
+ */
+enum state_terminal_raw {
+	STATE_TERM_RAW_WITH_SIGS,	/* Default */
+	STATE_TERM_RAW,
+	STATE_TERM_COOKED,
+
+	STATE_TERM_COUNT,
+};
+
+struct sandbox_spi_info {
+	struct udevice *emul;
+};
+
+struct sandbox_wdt_info {
+	unsigned long long counter;
+	uint reset_count;
+	bool running;
+};
+
+/**
+ * struct sandbox_mapmem_entry - maps pointers to/from U-Boot addresses
+ *
+ * When map_to_sysmem() is called with an address outside sandbox's emulated
+ * RAM, a record is created with a tag that can be used to reference that
+ * pointer. When map_sysmem() is called later with that tag, the pointer will
+ * be returned, just as it would for a normal sandbox address.
+ *
+ * @tag: Address tag (a value which U-Boot uses to refer to the address)
+ * @ptr: Associated pointer for that tag
+ */
+struct sandbox_mapmem_entry {
+	ulong tag;
+	void *ptr;
+	struct list_head sibling_node;
+};
+
+/* The complete state of the test system */
+struct sandbox_state {
+	const char *cmd;		/* Command to execute */
+	bool interactive;		/* Enable cmdline after execute */
+	bool run_distro_boot;		/* Automatically run distro bootcommands */
+	const char *fdt_fname;		/* Filename of FDT binary */
+	const char *parse_err;		/* Error to report from parsing */
+	int argc;			/* Program arguments */
+	char **argv;			/* Command line arguments */
+	const char *jumped_fname;	/* Jumped from previous U_Boot */
+	uint8_t *ram_buf;		/* Emulated RAM buffer */
+	unsigned int ram_size;		/* Size of RAM buffer */
+	const char *ram_buf_fname;	/* Filename to use for RAM buffer */
+	bool ram_buf_rm;		/* Remove RAM buffer file after read */
+	bool write_ram_buf;		/* Write RAM buffer on exit */
+	const char *state_fname;	/* File containing sandbox state */
+	void *state_fdt;		/* Holds saved state for sandbox */
+	bool read_state;		/* Read sandbox state on startup */
+	bool write_state;		/* Write sandbox state on exit */
+	bool ignore_missing_state_on_read;	/* No error if state missing */
+	bool show_lcd;			/* Show LCD on start-up */
+	enum sysreset_t last_sysreset;	/* Last system reset type */
+	bool sysreset_allowed[SYSRESET_COUNT];	/* Allowed system reset types */
+	enum state_terminal_raw term_raw;	/* Terminal raw/cooked */
+	bool skip_delays;		/* Ignore any time delays (for test) */
+	bool show_test_output;		/* Don't suppress stdout in tests */
+	int default_log_level;		/* Default log level for sandbox */
+	bool show_of_platdata;		/* Show of-platdata in SPL */
+	bool ram_buf_read;		/* true if we read the RAM buffer */
+
+	/* Pointer to information for each SPI bus/cs */
+	struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
+					[CONFIG_SANDBOX_SPI_MAX_CS];
+
+	/* Information about Watchdog */
+	struct sandbox_wdt_info wdt;
+
+	ulong next_tag;			/* Next address tag to allocate */
+	struct list_head mapmem_head;	/* struct sandbox_mapmem_entry */
+	bool hwspinlock;		/* Hardware Spinlock status */
+	bool allow_memio;		/* Allow readl() etc. to work */
+
+	/*
+	 * This struct is getting large.
+	 *
+	 * Consider putting test data in driver-private structs, like
+	 * sandbox_pch.c.
+	 *
+	 * If you add new members, please put them above this comment.
+	 */
+};
+
+/* Minimum space we guarantee in the state FDT when calling read/write*/
+#define SANDBOX_STATE_MIN_SPACE		0x1000
+
+/**
+ * struct sandbox_state_io - methods to saved/restore sandbox state
+ * @name: Name of of the device tree node, also the name of the variable
+ *	holding this data so it should be an identifier (use underscore
+ *	instead of minus)
+ * @compat: Compatible string for the node containing this state
+ *
+ * @read: Function to read state from FDT
+ *	If data is available, then blob and node will provide access to it. If
+ *	not (blob == NULL and node == -1) this function should set up an empty
+ *	data set for start-of-day.
+ *	@param blob: Pointer to device tree blob, or NULL if no data to read
+ *	@param node: Node offset to read from
+ *	@return 0 if OK, -ve on error
+ *
+ * @write: Function to write state to FDT
+ *	The caller will ensure that there is a node ready for the state. The
+ *	node may already contain the old state, in which case it should be
+ *	overridden. There is guaranteed to be SANDBOX_STATE_MIN_SPACE bytes
+ *	of free space, so error checking is not required for fdt_setprop...()
+ *	calls which add up to less than this much space.
+ *
+ *	For adding larger properties, use state_setprop().
+ *
+ * @param blob: Device tree blob holding state
+ * @param node: Node to write our state into
+ *
+ * Note that it is possible to save data as large blobs or as individual
+ * hierarchical properties. However, unless you intend to keep state files
+ * around for a long time and be able to run an old state file on a new
+ * sandbox, it might not be worth using individual properties for everything.
+ * This is certainly supported, it is just a matter of the effort you wish
+ * to put into the state read/write feature.
+ */
+struct sandbox_state_io {
+	const char *name;
+	const char *compat;
+	int (*write)(void *blob, int node);
+	int (*read)(const void *blob, int node);
+};
+
+/**
+ * SANDBOX_STATE_IO - Declare sandbox state to read/write
+ *
+ * Sandbox permits saving state from one run and restoring it in another. This
+ * allows the test system to retain state between runs and thus better
+ * emulate a real system. Examples of state that might be useful to save are
+ * the emulated GPIOs pin settings, flash memory contents and TPM private
+ * data. U-Boot memory contents is dealth with separately since it is large
+ * and it is not normally useful to save it (since a normal system does not
+ * preserve DRAM between runs). See the '-m' option for this.
+ *
+ * See struct sandbox_state_io above for member documentation.
+ */
+#define SANDBOX_STATE_IO(_name, _compat, _read, _write) \
+	ll_entry_declare(struct sandbox_state_io, _name, state_io) = { \
+		.name = __stringify(_name), \
+		.read = _read, \
+		.write = _write, \
+		.compat = _compat, \
+	}
+
+/**
+ * Gets a pointer to the current state.
+ *
+ * @return pointer to state
+ */
+struct sandbox_state *state_get_current(void);
+
+/**
+ * Read the sandbox state from the supplied device tree file
+ *
+ * This calls all registered state handlers to read in the sandbox state
+ * from a previous test run.
+ *
+ * @param state		Sandbox state to update
+ * @param fname		Filename of device tree file to read from
+ * @return 0 if OK, -ve on error
+ */
+int sandbox_read_state(struct sandbox_state *state, const char *fname);
+
+/**
+ * Write the sandbox state to the supplied device tree file
+ *
+ * This calls all registered state handlers to write out the sandbox state
+ * so that it can be preserved for a future test run.
+ *
+ * If the file exists it is overwritten.
+ *
+ * @param state		Sandbox state to update
+ * @param fname		Filename of device tree file to write to
+ * @return 0 if OK, -ve on error
+ */
+int sandbox_write_state(struct sandbox_state *state, const char *fname);
+
+/**
+ * Add a property to a sandbox state node
+ *
+ * This is equivalent to fdt_setprop except that it automatically enlarges
+ * the device tree if necessary. That means it is safe to write any amount
+ * of data here.
+ *
+ * This function can only be called from within struct sandbox_state_io's
+ * ->write method, i.e. within state I/O drivers.
+ *
+ * @param node		Device tree node to write to
+ * @param prop_name	Property to write
+ * @param data		Data to write into property
+ * @param size		Size of data to write into property
+ */
+int state_setprop(int node, const char *prop_name, const void *data, int size);
+
+/**
+ * Control skipping of time delays
+ *
+ * Some tests have unnecessay time delays (e.g. USB). Allow these to be
+ * skipped to speed up testing
+ *
+ * @param skip_delays	true to skip delays from now on, false to honour delay
+ *			requests
+ */
+void state_set_skip_delays(bool skip_delays);
+
+/**
+ * See if delays should be skipped
+ *
+ * @return true if delays should be skipped, false if they should be honoured
+ */
+bool state_get_skip_delays(void);
+
+/**
+ * state_reset_for_test() - Reset ready to re-run tests
+ *
+ * This clears out any test state ready for another test run.
+ */
+void state_reset_for_test(struct sandbox_state *state);
+
+/**
+ * state_show() - Show information about the sandbox state
+ *
+ * @param state		Sandbox state to show
+ */
+void state_show(struct sandbox_state *state);
+
+/**
+ * Initialize the test system state
+ */
+int state_init(void);
+
+/**
+ * Uninitialize the test system state, writing out state if configured to
+ * do so.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int state_uninit(void);
+
+#endif
diff --git a/arch/sandbox/include/asm/string.h b/arch/sandbox/include/asm/string.h
new file mode 100644
index 0000000..32685b3
--- /dev/null
+++ b/arch/sandbox/include/asm/string.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#include <linux/string.h>
diff --git a/arch/sandbox/include/asm/system.h b/arch/sandbox/include/asm/system.h
new file mode 100644
index 0000000..7933b62
--- /dev/null
+++ b/arch/sandbox/include/asm/system.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_SANDBOX_SYSTEM_H
+#define __ASM_SANDBOX_SYSTEM_H
+
+/* Define this as nops for sandbox architecture */
+#define local_irq_save(x)
+#define local_irq_enable()
+#define local_irq_disable()
+#define local_save_flags(x)
+#define local_irq_restore(x)
+
+#endif
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
new file mode 100644
index 0000000..cd2b9e3
--- /dev/null
+++ b/arch/sandbox/include/asm/test.h
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Test-related constants for sandbox
+ *
+ * Copyright (c) 2014 Google, Inc
+ */
+
+#ifndef __ASM_TEST_H
+#define __ASM_TEST_H
+
+/* The sandbox driver always permits an I2C device with this address */
+#define SANDBOX_I2C_TEST_ADDR		0x59
+
+#define SANDBOX_PCI_VENDOR_ID		0x1234
+#define SANDBOX_PCI_SWAP_CASE_EMUL_ID	0x5678
+#define SANDBOX_PCI_CLASS_CODE		PCI_CLASS_CODE_COMM
+#define SANDBOX_PCI_CLASS_SUB_CODE	PCI_CLASS_SUB_CODE_COMM_SERIAL
+
+#define PCI_CAP_ID_PM_OFFSET		0x50
+#define PCI_CAP_ID_EXP_OFFSET		0x60
+#define PCI_CAP_ID_MSIX_OFFSET		0x70
+#define PCI_CAP_ID_EA_OFFSET		0x80
+
+#define PCI_EXT_CAP_ID_ERR_OFFSET	0x100
+#define PCI_EXT_CAP_ID_VC_OFFSET	0x200
+#define PCI_EXT_CAP_ID_DSN_OFFSET	0x300
+
+/* Useful for PCI_VDEVICE() macro */
+#define PCI_VENDOR_ID_SANDBOX		SANDBOX_PCI_VENDOR_ID
+#define SWAP_CASE_DRV_DATA		0x55aa
+
+#define SANDBOX_CLK_RATE		32768
+
+/* Macros used to test PCI EA capability structure */
+#define PCI_CAP_EA_BASE_LO0		0x00100000
+#define PCI_CAP_EA_BASE_LO1		0x00110000
+#define PCI_CAP_EA_BASE_LO2		0x00120000
+#define PCI_CAP_EA_BASE_LO4		0x00140000
+#define PCI_CAP_EA_BASE_HI2		0x00020000ULL
+#define PCI_CAP_EA_BASE_HI4		0x00040000ULL
+#define PCI_CAP_EA_SIZE_LO		0x0000ffff
+#define PCI_CAP_EA_SIZE_HI		0x00000010ULL
+#define PCI_EA_BAR2_MAGIC		0x72727272
+#define PCI_EA_BAR4_MAGIC		0x74747474
+
+/* System controller driver data */
+enum {
+	SYSCON0		= 32,
+	SYSCON1,
+
+	SYSCON_COUNT
+};
+
+/**
+ * sandbox_i2c_set_test_mode() - set test mode for running unit tests
+ *
+ * See sandbox_i2c_xfer() for the behaviour changes.
+ *
+ * @bus:	sandbox I2C bus to adjust
+ * @test_mode:	true to select test mode, false to run normally
+ */
+void sandbox_i2c_set_test_mode(struct udevice *bus, bool test_mode);
+
+enum sandbox_i2c_eeprom_test_mode {
+	SIE_TEST_MODE_NONE,
+	/* Permits read/write of only one byte per I2C transaction */
+	SIE_TEST_MODE_SINGLE_BYTE,
+};
+
+void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
+				      enum sandbox_i2c_eeprom_test_mode mode);
+
+void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
+
+/**
+ * sandbox_i2c_rtc_set_offset() - set the time offset from system/base time
+ *
+ * @dev:		RTC device to adjust
+ * @use_system_time:	true to use system time, false to use @base_time
+ * @offset:		RTC offset from current system/base time (-1 for no
+ *			change)
+ * @return old value of RTC offset
+ */
+long sandbox_i2c_rtc_set_offset(struct udevice *dev, bool use_system_time,
+				int offset);
+
+/**
+ * sandbox_i2c_rtc_get_set_base_time() - get and set the base time
+ *
+ * @dev:		RTC device to adjust
+ * @base_time:		New base system time (set to -1 for no change)
+ * @return old base time
+ */
+long sandbox_i2c_rtc_get_set_base_time(struct udevice *dev, long base_time);
+
+int sandbox_usb_keyb_add_string(struct udevice *dev, const char *str);
+
+/**
+ * sandbox_osd_get_mem() - get the internal memory of a sandbox OSD
+ *
+ * @dev:	OSD device for which to access the internal memory for
+ * @buf:	pointer to buffer to receive the OSD memory data
+ * @buflen:	length of buffer in bytes
+ */
+int sandbox_osd_get_mem(struct udevice *dev, u8 *buf, size_t buflen);
+
+/**
+ * sandbox_pwm_get_config() - get the PWM config for a channel
+ *
+ * @dev: Device to check
+ * @channel: Channel number to check
+ * @period_ns: Period of the PWM in nanoseconds
+ * @duty_ns: Current duty cycle of the PWM in nanoseconds
+ * @enable: true if the PWM is enabled
+ * @polarity: true if the PWM polarity is active high
+ * @return 0 if OK, -ENOSPC if the PWM number is invalid
+ */
+int sandbox_pwm_get_config(struct udevice *dev, uint channel, uint *period_nsp,
+			   uint *duty_nsp, bool *enablep, bool *polarityp);
+
+/**
+ * sandbox_sf_set_block_protect() - Set the BP bits of the status register
+ *
+ * @dev: Device to update
+ * @bp_mask: BP bits to set (bits 2:0, so a value of 0 to 7)
+ */
+void sandbox_sf_set_block_protect(struct udevice *dev, int bp_mask);
+
+/**
+ * sandbox_get_codec_params() - Read back codec parameters
+ *
+ * This reads back the parameters set by audio_codec_set_params() for the
+ * sandbox audio driver. Arguments are as for that function.
+ */
+void sandbox_get_codec_params(struct udevice *dev, int *interfacep, int *ratep,
+			      int *mclk_freqp, int *bits_per_samplep,
+			      uint *channelsp);
+
+/**
+ * sandbox_get_i2s_sum() - Read back the sum of the audio data so far
+ *
+ * This data is provided to the sandbox driver by the I2S tx_data() method.
+ *
+ * @dev: Device to check
+ * @return sum of audio data
+ */
+int sandbox_get_i2s_sum(struct udevice *dev);
+
+/**
+ * sandbox_get_setup_called() - Returns the number of times setup(*) was called
+ *
+ * This is used in the sound test
+ *
+ * @dev: Device to check
+ * @return call count for the setup() method
+ */
+int sandbox_get_setup_called(struct udevice *dev);
+
+/**
+ * sandbox_get_sound_sum() - Read back the sum of the sound data so far
+ *
+ * This data is provided to the sandbox driver by the sound play() method.
+ *
+ * @dev: Device to check
+ * @return sum of audio data
+ */
+int sandbox_get_sound_sum(struct udevice *dev);
+
+/**
+ * sandbox_set_allow_beep() - Set whether the 'beep' interface is supported
+ *
+ * @dev: Device to update
+ * @allow: true to allow the start_beep() method, false to disallow it
+ */
+void sandbox_set_allow_beep(struct udevice *dev, bool allow);
+
+/**
+ * sandbox_get_beep_frequency() - Get the frequency of the current beep
+ *
+ * @dev: Device to check
+ * @return frequency of beep, if there is an active beep, else 0
+ */
+int sandbox_get_beep_frequency(struct udevice *dev);
+
+/**
+ * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status
+ *
+ * @dev: Device to check
+ * @return 0 if not protected, 1 if protected
+ */
+int sandbox_get_pch_spi_protect(struct udevice *dev);
+
+/**
+ * sandbox_get_pci_ep_irq_count() - Get the PCI EP IRQ count
+ *
+ * @dev: Device to check
+ * @return irq count
+ */
+int sandbox_get_pci_ep_irq_count(struct udevice *dev);
+
+/**
+ * sandbox_pci_read_bar() - Read the BAR value for a read_config operation
+ *
+ * This is used in PCI emulators to read a base address reset. This has special
+ * rules because when the register is set to 0xffffffff it can be used to
+ * discover the type and size of the BAR.
+ *
+ * @barval: Current value of the BAR
+ * @type: Type of BAR (PCI_BASE_ADDRESS_SPACE_IO or
+ *		PCI_BASE_ADDRESS_MEM_TYPE_32)
+ * @size: Size of BAR in bytes
+ * @return BAR value to return from emulator
+ */
+uint sandbox_pci_read_bar(u32 barval, int type, uint size);
+
+#endif
diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h
new file mode 100644
index 0000000..c1a5d2a
--- /dev/null
+++ b/arch/sandbox/include/asm/types.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_SANDBOX_TYPES_H
+#define __ASM_SANDBOX_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+typedef unsigned short umode_t;
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+/*
+ * Number of bits in a C 'long' on this architecture.
+ */
+#ifdef	CONFIG_PHYS_64BIT
+#define BITS_PER_LONG 64
+#else	/* CONFIG_PHYS_64BIT */
+#define BITS_PER_LONG 32
+#endif	/* CONFIG_PHYS_64BIT */
+
+#ifdef	CONFIG_PHYS_64BIT
+typedef unsigned long long dma_addr_t;
+typedef u64 phys_addr_t;
+typedef u64 phys_size_t;
+#else	/* CONFIG_PHYS_64BIT */
+typedef unsigned long dma_addr_t;
+typedef u32 phys_addr_t;
+typedef u32 phys_size_t;
+#endif	/* CONFIG_PHYS_64BIT */
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/sandbox/include/asm/u-boot-sandbox.h b/arch/sandbox/include/asm/u-boot-sandbox.h
new file mode 100644
index 0000000..798d003
--- /dev/null
+++ b/arch/sandbox/include/asm/u-boot-sandbox.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ */
+
+#ifndef _U_BOOT_SANDBOX_H_
+#define _U_BOOT_SANDBOX_H_
+
+/* board/.../... */
+int board_init(void);
+
+/* start.c */
+int sandbox_early_getopt_check(void);
+int sandbox_main_loop_init(void);
+
+int cleanup_before_linux(void);
+
+/* drivers/video/sandbox_sdl.c */
+int sandbox_lcd_sdl_early_init(void);
+
+struct udevice;
+
+/**
+ * pci_map_physmem() - map a PCI device into memory
+ *
+ * This is used on sandbox to map a device into memory so that it can be
+ * used with normal memory access. After this call, some part of the device's
+ * internal structure becomes visible.
+ *
+ * This function is normally called from sandbox's map_sysmem() automatically.
+ *
+ * @paddr:	Physical memory address, normally corresponding to a PCI BAR
+ * @lenp:	On entry, the size of the area to map, On exit it is updated
+ *		to the size actually mapped, which may be less if the device
+ *		has less space
+ * @devp:	Returns the device which mapped into this space
+ * @ptrp:	Returns a pointer to the mapped address. The device's space
+ *		can be accessed as @lenp bytes starting here
+ * @return 0 if OK, -ve on error
+ */
+int pci_map_physmem(phys_addr_t paddr, unsigned long *lenp,
+		    struct udevice **devp, void **ptrp);
+
+/**
+ * pci_unmap_physmem() - undo a memory mapping
+ *
+ * This must be called after pci_map_physmem() to undo the mapping.
+ *
+ * @paddr:	Physical memory address, as passed to pci_map_physmem()
+ * @len:	Size of area mapped, as returned by pci_map_physmem()
+ * @dev:	Device to unmap, as returned by pci_map_physmem()
+ * @return 0 if OK, -ve on error
+ */
+int pci_unmap_physmem(const void *addr, unsigned long len,
+		      struct udevice *dev);
+
+/**
+ * sandbox_set_enable_pci_map() - Enable / disable PCI address mapping
+ *
+ * Since address mapping involves calling every driver, provide a way to
+ * enable and disable this. It can be handled automatically by the emulator
+ * uclass, which knows if any emulators are currently active.
+ *
+ * If this is disabled, pci_map_physmem() will not be called from
+ * map_sysmem().
+ *
+ * @enable: 0 to disable, 1 to enable
+ */
+void sandbox_set_enable_pci_map(int enable);
+
+/**
+ * sandbox_read_fdt_from_file() - Read a device tree from a file
+ *
+ * Read a device tree file from a host file and set it up for use as the
+ * control FDT.
+ */
+int sandbox_read_fdt_from_file(void);
+
+/* Exit sandbox (quit U-Boot) */
+void sandbox_exit(void);
+
+#endif	/* _U_BOOT_SANDBOX_H_ */
diff --git a/arch/sandbox/include/asm/u-boot.h b/arch/sandbox/include/asm/u-boot.h
new file mode 100644
index 0000000..34fcb71
--- /dev/null
+++ b/arch/sandbox/include/asm/u-boot.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#include <asm/u-boot-sandbox.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_SANDBOX
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/sandbox/include/asm/unaligned.h b/arch/sandbox/include/asm/unaligned.h
new file mode 100644
index 0000000..2cb2a17
--- /dev/null
+++ b/arch/sandbox/include/asm/unaligned.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#include <asm-generic/unaligned.h>
diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h
new file mode 100644
index 0000000..765f28f
--- /dev/null
+++ b/arch/sh/include/asm/bitops.h
@@ -0,0 +1,162 @@
+#ifndef __ASM_SH_BITOPS_H
+#define __ASM_SH_BITOPS_H
+
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+#ifdef __KERNEL__
+#include <asm/irqflags.h>
+/* For __swab32 */
+#include <asm/byteorder.h>
+
+static inline void set_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a |= mask;
+	local_irq_restore(flags);
+}
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+static inline void clear_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a &= ~mask;
+	local_irq_restore(flags);
+}
+
+static inline void change_bit(int nr, volatile void * addr)
+{
+	int	mask;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	*a ^= mask;
+	local_irq_restore(flags);
+}
+
+static inline int test_and_set_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a |= mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a &= ~mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static inline int test_and_change_bit(int nr, volatile void * addr)
+{
+	int	mask, retval;
+	volatile unsigned int *a = addr;
+	unsigned long flags;
+
+	a += nr >> 5;
+	mask = 1 << (nr & 0x1f);
+	local_irq_save(flags);
+	retval = (mask & *a) != 0;
+	*a ^= mask;
+	local_irq_restore(flags);
+
+	return retval;
+}
+
+static inline unsigned long ffz(unsigned long word)
+{
+	unsigned long result;
+
+	__asm__("1:\n\t"
+		"shlr	%1\n\t"
+		"bt/s	1b\n\t"
+		" add	#1, %0"
+		: "=r" (result), "=r" (word)
+		: "0" (~0L), "1" (word)
+		: "t");
+	return result;
+}
+
+/**
+ * ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline int ffs (int x)
+{
+	int r = 1;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff)) {
+		x >>= 16;
+		r += 16;
+	}
+	if (!(x & 0xff)) {
+		x >>= 8;
+		r += 8;
+	}
+	if (!(x & 0xf)) {
+		x >>= 4;
+		r += 4;
+	}
+	if (!(x & 3)) {
+		x >>= 2;
+		r += 2;
+	}
+	if (!(x & 1)) {
+		x >>= 1;
+		r += 1;
+	}
+	return r;
+}
+#define PLATFORM_FFS
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_BITOPS_H */
diff --git a/arch/sh/include/asm/byteorder.h b/arch/sh/include/asm/byteorder.h
new file mode 100644
index 0000000..b5dfe4e
--- /dev/null
+++ b/arch/sh/include/asm/byteorder.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASM_SH_BYTEORDER_H_
+#define __ASM_SH_BYTEORDER_H_
+
+#include <config.h>
+#include <asm/types.h>
+
+#ifdef __LITTLE_ENDIAN__
+#include <linux/byteorder/little_endian.h>
+#else
+#include <linux/byteorder/big_endian.h>
+#endif
+
+#endif
diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h
new file mode 100644
index 0000000..b548a35
--- /dev/null
+++ b/arch/sh/include/asm/cache.h
@@ -0,0 +1,29 @@
+#ifndef __ASM_SH_CACHE_H
+#define __ASM_SH_CACHE_H
+
+#if defined(CONFIG_CPU_SH4)
+
+#define L1_CACHE_BYTES 32
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct *)(x))
+
+#else
+
+/*
+ * 32-bytes is the largest L1 data cache line size for SH the architecture.  So
+ * it is a safe default for DMA alignment.
+ */
+#define ARCH_DMA_MINALIGN	32
+
+#endif /* CONFIG_CPU_SH4 */
+
+/*
+ * Use the L1 data cache line size value for the minimum DMA buffer alignment
+ * on SH.
+ */
+#ifndef ARCH_DMA_MINALIGN
+#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
+#endif
+
+#endif	/* __ASM_SH_CACHE_H */
diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h
new file mode 100644
index 0000000..e1cd322
--- /dev/null
+++ b/arch/sh/include/asm/config.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#include <asm/processor.h>
+
+#define CONFIG_LMB
+
+/* Timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE		(CONFIG_SYS_CLK_FREQ / 4)
+
+#endif
diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h
new file mode 100644
index 0000000..5fc9c96
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh4.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#ifndef _ASM_CPU_SH4_H_
+#define _ASM_CPU_SH4_H_
+
+/* cache control */
+#define CCR_CACHE_STOP   0x00000808
+#define CCR_CACHE_ENABLE 0x00000101
+#define CCR_CACHE_ICI    0x00000800
+
+#define CACHE_OC_ADDRESS_ARRAY	0xf4000000
+
+#if defined (CONFIG_CPU_SH7750) || \
+	defined(CONFIG_CPU_SH7751)
+#define CACHE_OC_WAY_SHIFT	14
+#define CACHE_OC_NUM_ENTRIES	512
+#else
+#define CACHE_OC_WAY_SHIFT	13
+#define CACHE_OC_NUM_ENTRIES	256
+#endif
+#define CACHE_OC_ENTRY_SHIFT	5
+
+#if defined (CONFIG_CPU_SH7750) || \
+	defined(CONFIG_CPU_SH7751)
+# include <asm/cpu_sh7750.h>
+#elif defined (CONFIG_CPU_SH7722)
+# include <asm/cpu_sh7722.h>
+#elif defined (CONFIG_CPU_SH7723)
+# include <asm/cpu_sh7723.h>
+#elif defined (CONFIG_CPU_SH7734)
+# include <asm/cpu_sh7734.h>
+#elif defined (CONFIG_CPU_SH7752)
+# include <asm/cpu_sh7752.h>
+#elif defined (CONFIG_CPU_SH7753)
+# include <asm/cpu_sh7753.h>
+#elif defined (CONFIG_CPU_SH7757)
+# include <asm/cpu_sh7757.h>
+#elif defined (CONFIG_CPU_SH7763)
+# include <asm/cpu_sh7763.h>
+#elif defined (CONFIG_CPU_SH7780)
+# include <asm/cpu_sh7780.h>
+#else
+# error "Unknown SH4 variant"
+#endif
+
+#if defined(CONFIG_SH_32BIT)
+#define PMB_ADDR_ARRAY		0xf6100000
+#define PMB_ADDR_ENTRY		8
+#define PMB_VPN			24
+
+#define PMB_DATA_ARRAY		0xf7100000
+#define PMB_DATA_ENTRY		8
+#define PMB_PPN			24
+#define PMB_UB			9		/* Buffered write */
+#define PMB_V			8		/* Valid */
+#define PMB_SZ1			7		/* Page size (upper bit) */
+#define PMB_SZ0			4		/* Page size (lower bit) */
+#define PMB_C			3		/* Cacheability */
+#define PMB_WT			0		/* Write-through */
+
+#define PMB_ADDR_BASE(entry)	(PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
+#define PMB_DATA_BASE(entry)	(PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
+#define mk_pmb_addr_val(vpn)	((vpn << PMB_VPN))
+#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt)	\
+				((ppn << PMB_PPN) | (ub << PMB_UB) | \
+				 (v << PMB_V) | (sz1 << PMB_SZ1) | \
+				 (sz0 << PMB_SZ0) | (c << PMB_C) | \
+				 (wt << PMB_WT))
+#endif
+
+#endif	/* _ASM_CPU_SH4_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7722.h b/arch/sh/include/asm/cpu_sh7722.h
new file mode 100644
index 0000000..9f1f6a0
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7722.h
@@ -0,0 +1,1277 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SH7722 Internal I/O register
+ */
+
+#ifndef _ASM_CPU_SH7722_H_
+#define _ASM_CPU_SH7722_H_
+
+#define CACHE_OC_NUM_WAYS	4
+#define CCR_CACHE_INIT	0x0000090d
+
+/*	EXP	*/
+#define TRA		0xFF000020
+#define EXPEVT		0xFF000024
+#define INTEVT		0xFF000028
+
+/*	MMU	*/
+#define PTEH		0xFF000000
+#define PTEL		0xFF000004
+#define TTB		0xFF000008
+#define TEA		0xFF00000C
+#define MMUCR		0xFF000010
+#define PASCR		0xFF000070
+#define IRMCR		0xFF000078
+
+/*	CACHE	*/
+#define CCR		0xFF00001C
+#define RAMCR		0xFF000074
+
+/*	XY MEMORY	*/
+#define XSA		0xFF000050
+#define YSA		0xFF000054
+#define XDA		0xFF000058
+#define YDA		0xFF00005C
+#define XPR		0xFF000060
+#define YPR		0xFF000064
+#define XEA		0xFF000068
+#define YEA		0xFF00006C
+
+/*	INTC	*/
+#define ICR0		0xA4140000
+#define ICR1		0xA414001C
+#define INTPRI0		0xA4140010
+#define INTREQ0		0xA4140024
+#define INTMSK0		0xA4140044
+#define INTMSKCLR0	0xA4140064
+#define NMIFCR		0xA41400C0
+#define USERIMASK	0xA4700000
+#define IPRA		0xA4080000
+#define IPRB		0xA4080004
+#define IPRC		0xA4080008
+#define IPRD		0xA408000C
+#define IPRE		0xA4080010
+#define IPRF		0xA4080014
+#define IPRG		0xA4080018
+#define IPRH		0xA408001C
+#define IPRI		0xA4080020
+#define IPRJ		0xA4080024
+#define IPRK		0xA4080028
+#define IPRL		0xA408002C
+#define IMR0		0xA4080080
+#define IMR1		0xA4080084
+#define IMR2		0xA4080088
+#define IMR3		0xA408008C
+#define IMR4		0xA4080090
+#define IMR5		0xA4080094
+#define IMR6		0xA4080098
+#define IMR7		0xA408009C
+#define IMR8		0xA40800A0
+#define IMR9		0xA40800A4
+#define IMR10		0xA40800A8
+#define IMR11		0xA40800AC
+#define IMCR0		0xA40800C0
+#define IMCR1		0xA40800C4
+#define IMCR2		0xA40800C8
+#define IMCR3		0xA40800CC
+#define IMCR4		0xA40800D0
+#define IMCR5		0xA40800D4
+#define IMCR6		0xA40800D8
+#define IMCR7		0xA40800DC
+#define IMCR8		0xA40800E0
+#define IMCR9		0xA40800E4
+#define IMCR10		0xA40800E8
+#define IMCR11		0xA40800EC
+#define MFI_IPRA	0xA40B0000
+#define MFI_IPRB	0xA40B0004
+#define MFI_IPRC	0xA40B0008
+#define MFI_IPRD	0xA40B000C
+#define MFI_IPRE	0xA40B0010
+#define MFI_IPRF	0xA40B0014
+#define MFI_IPRG	0xA40B0018
+#define MFI_IPRH	0xA40B001C
+#define MFI_IPRI	0xA40B0020
+#define MFI_IPRJ	0xA40B0024
+#define MFI_IPRK	0xA40B0028
+#define MFI_IPRL	0xA40B002C
+#define MFI_IMR0	0xA40B0080
+#define MFI_IMR1	0xA40B0084
+#define MFI_IMR2	0xA40B0088
+#define MFI_IMR3	0xA40B008C
+#define MFI_IMR4	0xA40B0090
+#define MFI_IMR5	0xA40B0094
+#define MFI_IMR6	0xA40B0098
+#define MFI_IMR7	0xA40B009C
+#define MFI_IMR8	0xA40B00A0
+#define MFI_IMR9	0xA40B00A4
+#define MFI_IMR10	0xA40B00A8
+#define MFI_IMR11	0xA40B00AC
+#define MFI_IMCR0	0xA40B00C0
+#define MFI_IMCR1	0xA40B00C4
+#define MFI_IMCR2	0xA40B00C8
+#define MFI_IMCR3	0xA40B00CC
+#define MFI_IMCR4	0xA40B00D0
+#define MFI_IMCR5	0xA40B00D4
+#define MFI_IMCR6	0xA40B00D8
+#define MFI_IMCR7	0xA40B00DC
+#define MFI_IMCR8	0xA40B00E0
+#define MFI_IMCR9	0xA40B00E4
+#define MFI_IMCR10	0xA40B00E8
+#define MFI_IMCR11	0xA40B00EC
+
+/*	BSC	*/
+#define CMNCR	    0xFEC10000
+#define	CS0BCR	    0xFEC10004
+#define CS2BCR      0xFEC10008
+#define CS4BCR      0xFEC10010
+#define CS5ABCR     0xFEC10014
+#define CS5BBCR     0xFEC10018
+#define CS6ABCR     0xFEC1001C
+#define CS6BBCR     0xFEC10020
+#define CS0WCR      0xFEC10024
+#define CS2WCR      0xFEC10028
+#define CS4WCR      0xFEC10030
+#define CS5AWCR     0xFEC10034
+#define CS5BWCR     0xFEC10038
+#define CS6AWCR     0xFEC1003C
+#define CS6BWCR     0xFEC10040
+#define RBWTCNT     0xFEC10054
+
+/*	SBSC	*/
+#define SBSC_SDCR   0xFE400008
+#define SBSC_SDWCR  0xFE40000C
+#define SBSC_SDPCR  0xFE400010
+#define SBSC_RTCSR  0xFE400014
+#define SBSC_RTCNT  0xFE400018
+#define SBSC_RTCOR  0xFE40001C
+#define SBSC_RFCR   0xFE400020
+
+/*	DMAC	*/
+#define SAR_0       0xFE008020
+#define DAR_0       0xFE008024
+#define TCR_0       0xFE008028
+#define CHCR_0      0xFE00802C
+#define SAR_1       0xFE008030
+#define DAR_1       0xFE008034
+#define TCR_1       0xFE008038
+#define CHCR_1      0xFE00803C
+#define SAR_2       0xFE008040
+#define DAR_2       0xFE008044
+#define TCR_2       0xFE008048
+#define CHCR_2      0xFE00804C
+#define SAR_3       0xFE008050
+#define DAR_3       0xFE008054
+#define TCR_3       0xFE008058
+#define CHCR_3      0xFE00805C
+#define SAR_4       0xFE008070
+#define DAR_4       0xFE008074
+#define TCR_4       0xFE008078
+#define CHCR_4      0xFE00807C
+#define SAR_5       0xFE008080
+#define DAR_5       0xFE008084
+#define TCR_5       0xFE008088
+#define CHCR_5      0xFE00808C
+#define SARB_0      0xFE008120
+#define DARB_0      0xFE008124
+#define TCRB_0      0xFE008128
+#define SARB_1      0xFE008130
+#define DARB_1      0xFE008134
+#define TCRB_1      0xFE008138
+#define SARB_2      0xFE008140
+#define DARB_2      0xFE008144
+#define TCRB_2      0xFE008148
+#define SARB_3      0xFE008150
+#define DARB_3      0xFE008154
+#define TCRB_3      0xFE008158
+#define DMAOR       0xFE008060
+#define DMARS_0     0xFE009000
+#define DMARS_1     0xFE009004
+#define DMARS_2     0xFE009008
+
+/*	CPG	*/
+#define FRQCR       0xA4150000
+#define VCLKCR      0xA4150004
+#define SCLKACR     0xA4150008
+#define SCLKBCR     0xA415000C
+#define PLLCR       0xA4150024
+#define DLLFRQ      0xA4150050
+
+/*	LOW POWER MODE	*/
+#define STBCR       0xA4150020
+#define MSTPCR0     0xA4150030
+#define MSTPCR1     0xA4150034
+#define MSTPCR2     0xA4150038
+#define BAR         0xA4150040
+
+/*	RWDT	*/
+#define RWTCNT      0xA4520000
+#define RWTCSR      0xA4520004
+#define WTCNT	RWTCNT
+
+
+/*	TMU	*/
+#define TMU_BASE	0xFFD80000
+
+/*	TPU	*/
+#define TPU_TSTR    0xA4C90000
+#define TPU_TCR0    0xA4C90010
+#define TPU_TMDR0   0xA4C90014
+#define TPU_TIOR0   0xA4C90018
+#define TPU_TIER0   0xA4C9001C
+#define TPU_TSR0    0xA4C90020
+#define TPU_TCNT0   0xA4C90024
+#define TPU_TGR0A   0xA4C90028
+#define TPU_TGR0B   0xA4C9002C
+#define TPU_TGR0C   0xA4C90030
+#define TPU_TGR0D   0xA4C90034
+#define TPU_TCR1    0xA4C90050
+#define TPU_TMDR1   0xA4C90054
+#define TPU_TIER1   0xA4C9005C
+#define TPU_TSR1    0xA4C90060
+#define TPU_TCNT1   0xA4C90064
+#define TPU_TGR1A   0xA4C90068
+#define TPU_TGR1B   0xA4C9006C
+#define TPU_TGR1C   0xA4C90070
+#define TPU_TGR1D   0xA4C90074
+#define TPU_TCR2    0xA4C90090
+#define TPU_TMDR2   0xA4C90094
+#define TPU_TIER2   0xA4C9009C
+#define TPU_TSR2    0xA4C900A0
+#define TPU_TCNT2   0xA4C900A4
+#define TPU_TGR2A   0xA4C900A8
+#define TPU_TGR2B   0xA4C900AC
+#define TPU_TGR2C   0xA4C900B0
+#define TPU_TGR2D   0xA4C900B4
+#define TPU_TCR3    0xA4C900D0
+#define TPU_TMDR3   0xA4C900D4
+#define TPU_TIER3   0xA4C900DC
+#define TPU_TSR3    0xA4C900E0
+#define TPU_TCNT3   0xA4C900E4
+#define TPU_TGR3A   0xA4C900E8
+#define TPU_TGR3B   0xA4C900EC
+#define TPU_TGR3C   0xA4C900F0
+#define TPU_TGR3D   0xA4C900F4
+
+/*	CMT	*/
+#define CMSTR       0xA44A0000
+#define CMCSR       0xA44A0060
+#define CMCNT       0xA44A0064
+#define CMCOR       0xA44A0068
+
+/*	SIO	*/
+#define SIOMDR      0xA4500000
+#define SIOCTR      0xA4500004
+#define SIOSTBCR0   0xA4500008
+#define SIOSTBCR1   0xA450000C
+#define SIOTDR      0xA4500014
+#define SIORDR      0xA4500018
+#define SIOSTR      0xA450001C
+#define SIOIER      0xA4500020
+#define SIOSCR      0xA4500024
+
+/*	SIOF	*/
+#define SIMDR0      0xA4410000
+#define SISCR0      0xA4410002
+#define SITDAR0     0xA4410004
+#define SIRDAR0     0xA4410006
+#define SICDAR0     0xA4410008
+#define SICTR0      0xA441000C
+#define SIFCTR0     0xA4410010
+#define SISTR0      0xA4410014
+#define SIIER0      0xA4410016
+#define SITDR0      0xA4410020
+#define SIRDR0      0xA4410024
+#define SITCR0      0xA4410028
+#define SIRCR0      0xA441002C
+#define SPICR0      0xA4410030
+#define SIMDR1      0xA4420000
+#define SISCR1      0xA4420002
+#define SITDAR1     0xA4420004
+#define SIRDAR1     0xA4420006
+#define SICDAR1     0xA4420008
+#define SICTR1      0xA442000C
+#define SIFCTR1     0xA4420010
+#define SISTR1      0xA4420014
+#define SIIER1      0xA4420016
+#define SITDR1      0xA4420020
+#define SIRDR1      0xA4420024
+#define SITCR1      0xA4420028
+#define SIRCR1      0xA442002C
+#define SPICR1      0xA4420030
+
+/*	SCIF	*/
+#define SCIF0_BASE  0xFFE00000
+
+/*	SIM	*/
+#define SIM_SCSMR       0xA4490000
+#define SIM_SCBRR       0xA4490002
+#define SIM_SCSCR       0xA4490004
+#define SIM_SCTDR       0xA4490006
+#define SIM_SCSSR       0xA4490008
+#define SIM_SCRDR       0xA449000A
+#define SIM_SCSCMR      0xA449000C
+#define SIM_SCSC2R      0xA449000E
+#define SIM_SCWAIT      0xA4490010
+#define SIM_SCGRD       0xA4490012
+#define SIM_SCSMPL      0xA4490014
+#define SIM_SCDMAEN     0xA4490016
+
+/*	IrDA	*/
+#define IRIF_INIT1      0xA45D0012
+#define IRIF_INIT2      0xA45D0014
+#define IRIF_RINTCLR    0xA45D0016
+#define IRIF_TINTCLR    0xA45D0018
+#define IRIF_SIR0       0xA45D0020
+#define IRIF_SIR1       0xA45D0022
+#define IRIF_SIR2       0xA45D0024
+#define IRIF_SIR3       0xA45D0026
+#define IRIF_SIR_FRM    0xA45D0028
+#define IRIF_SIR_EOF    0xA45D002A
+#define IRIF_SIR_FLG    0xA45D002C
+#define IRIF_SIR_STS2   0xA45D002E
+#define IRIF_UART0      0xA45D0030
+#define IRIF_UART1      0xA45D0032
+#define IRIF_UART2      0xA45D0034
+#define IRIF_UART3      0xA45D0036
+#define IRIF_UART4      0xA45D0038
+#define IRIF_UART5      0xA45D003A
+#define IRIF_UART6      0xA45D003C
+#define IRIF_UART7      0xA45D003E
+#define IRIF_CRC0       0xA45D0040
+#define IRIF_CRC1       0xA45D0042
+#define IRIF_CRC2       0xA45D0044
+#define IRIF_CRC3       0xA45D0046
+#define IRIF_CRC4       0xA45D0048
+
+/*	IIC	*/
+#define ICDR0       0xA4470000
+#define ICCR0       0xA4470004
+#define ICSR0       0xA4470008
+#define ICIC0       0xA447000C
+#define ICCL0       0xA4470010
+#define ICCH0       0xA4470014
+#define ICDR1       0xA4750000
+#define ICCR1       0xA4750004
+#define ICSR1       0xA4750008
+#define ICIC1       0xA475000C
+#define ICCL1       0xA4750010
+#define ICCH1       0xA4750014
+
+/*	FLCTL	*/
+#define FLCMNCR     0xA4530000
+#define FLCMDCR     0xA4530004
+#define FLCMCDR     0xA4530008
+#define FLADR       0xA453000C
+#define FLDATAR     0xA4530010
+#define FLDTCNTR    0xA4530014
+#define FLINTDMACR  0xA4530018
+#define FLBSYTMR    0xA453001C
+#define FLBSYCNT    0xA4530020
+#define FLDTFIFO    0xA4530024
+#define FLECFIFO    0xA4530028
+#define FLTRCR      0xA453002C
+#define FLADR2      0xA453003C
+
+/*	MFI	*/
+#define MFIIDX      0xA4C10000
+#define MFIGSR      0xA4C10004
+#define MFISCR      0xA4C10008
+#define MFIMCR      0xA4C1000C
+#define MFIIICR     0xA4C10010
+#define MFIEICR     0xA4C10014
+#define MFIADR      0xA4C10018
+#define MFIDATA     0xA4C1001C
+#define MFIRCR      0xA4C10020
+#define MFIINTEVT   0xA4C1002C
+#define MFIIMASK    0xA4C10030
+#define MFIBCR      0xA4C10040
+#define MFIADRW     0xA4C10044
+#define MFIADRR     0xA4C10048
+#define MFIDATAW    0xA4C1004C
+#define MFIDATAR    0xA4C10050
+#define MFIMCRW     0xA4C10054
+#define MFIMCRR     0xA4C10058
+#define MFIDNRW     0xA4C1005C
+#define MFIDNRR     0xA4C10060
+#define MFISIZEW    0xA4C10064
+#define MFISIZER    0xA4C10068
+#define MFIDEVCR    0xA4C10038
+#define MFISM4      0xA4C10080
+
+/*	VPU	*/
+#define VP4_CTRL        0xFE900000
+#define VP4_VOL_CTRL    0xFE900004
+#define VP4_IMAGE_SIZE  0xFE900008
+#define VP4_MB_NUM      0xFE90000C
+#define VP4_DWY_ADDR    0xFE900010
+#define VP4_DWC_ADDR    0xFE900014
+#define VP4_D2WY_ADDR   0xFE900018
+#define VP4_D2WC_ADDR   0xFE90001C
+#define VP4_DP1_ADDR    0xFE900020
+#define VP4_DP2_ADDR    0xFE900024
+#define VP4_STRS_ADDR   0xFE900028
+#define VP4_STRE_ADDR   0xFE90002C
+#define VP4_VOP_CTRL    0xFE900030
+#define VP4_VOP_TIME    0xFE900034
+#define VP4_263_CTRL    0xFE900038
+#define VP4_264_CTRL    0xFE90003C
+#define VP4_VLC_CTRL    0xFE900040
+#define VP4_ENDIAN      0xFE900044
+#define VP4_CMD         0xFE900048
+#define VP4_ME_TH1      0xFE90004C
+#define VP4_ME_TH2      0xFE900050
+#define VP4_ME_COSTMB   0xFE900054
+#define VP4_ME_SKIP     0xFE900058
+#define VP4_ME_CTRL     0xFE90005C
+#define VP4_MBRF_CTRL   0xFE900060
+#define VP4_MC_CTRL     0xFE900064
+#define VP4_PRED_CTRL   0xFE900068
+#define VP4_SLC_SIZE    0xFE90006C
+#define VP4_VOP_MINBIT  0xFE900070
+#define VP4_MB_MAXBIT   0xFE900074
+#define VP4_MB_TBIT     0xFE900078
+#define VP4_RCQNT       0xFE90007C
+#define VP4_RCRP        0xFE900080
+#define VP4_RCDJ        0xFE900084
+#define VP4_RCWQ        0xFE900088
+#define VP4_FWD_TIME    0xFE900094
+#define VP4_BWD_TIME    0xFE900098
+#define VP4_PST_TIME    0xFE90009C
+#define VP4_ILTFRAME    0xFE9000A0
+#define VP4_EC_REF      0xFE9000A4
+#define VP4_STATUS      0xFE900100
+#define VP4_IRQ_ENB     0xFE900104
+#define VP4_IRQ_STA     0xFE900108
+#define VP4_VOP_BIT     0xFE90010C
+#define VP4_PRV_BIT     0xFE900110
+#define VP4_SLC_MB      0xFE900114
+#define VP4_QSUM        0xFE900118
+#define VP4_DEC_ERR     0xFE90011C
+#define VP4_ERR_AREA    0xFE900120
+#define VP4_NEXT_CODE   0xFE900124
+#define VP4_MB_ATTR     0xFE900128
+#define VP4_DBMON       0xFE90012C
+#define VP4_DEBUG       0xFE900130
+#define VP4_ERR_DET     0xFE900134
+#define VP4_CLK_STOP    0xFE900138
+#define VP4_MB_SADA     0xFE90013C
+#define VP4_MB_SADR     0xFE900140
+#define VP4_MAT_RAM     0xFE901000
+#define VP4_NC_RAM      0xFE902000
+#define WT              0xFE9020CC
+#define VP4_CPY_ADDR    0xFE902264
+#define VP4_CPC_ADDR    0xFE902268
+#define VP4_R0Y_ADDR    0xFE90226C
+#define VP4_R0C_ADDR    0xFE902270
+#define VP4_R1Y_ADDR    0xFE902274
+#define VP4_R1C_ADDR    0xFE902278
+#define VP4_R2Y_ADDR    0xFE90227C
+#define VP4_R2C_ADDR    0xFE902280
+#define VP4_R3Y_ADDR    0xFE902284
+#define VP4_R3C_ADDR    0xFE902288
+#define VP4_R4Y_ADDR    0xFE90228C
+#define VP4_R4C_ADDR    0xFE902290
+#define VP4_R5Y_ADDR    0xFE902294
+#define VP4_R5C_ADDR    0xFE902298
+#define VP4_R6Y_ADDR    0xFE90229C
+#define VP4_R6C_ADDR    0xFE9022A0
+#define VP4_R7Y_ADDR    0xFE9022A4
+#define VP4_R7C_ADDR    0xFE9022A8
+#define VP4_R8Y_ADDR    0xFE9022AC
+#define VP4_R8C_ADDR    0xFE9022B0
+#define VP4_R9Y_ADDR    0xFE9022B4
+#define VP4_R9C_ADDR    0xFE9022B8
+#define VP4_RAY_ADDR    0xFE9022BC
+#define VP4_RAC_ADDR    0xFE9022C0
+#define VP4_RBY_ADDR    0xFE9022C4
+#define VP4_RBC_ADDR    0xFE9022C8
+#define VP4_RCY_ADDR    0xFE9022CC
+#define VP4_RCC_ADDR    0xFE9022D0
+#define VP4_RDY_ADDR    0xFE9022D4
+#define VP4_RDC_ADDR    0xFE9022D8
+#define VP4_REY_ADDR    0xFE9022DC
+#define VP4_REC_ADDR    0xFE9022E0
+#define VP4_RFY_ADDR    0xFE9022E4
+#define VP4_RFC_ADDR    0xFE9022E8
+
+/*	VIO(CEU)	*/
+#define CAPSR       0xFE910000
+#define CAPCR       0xFE910004
+#define CAMCR       0xFE910008
+#define CMCYR       0xFE91000C
+#define CAMOR       0xFE910010
+#define CAPWR       0xFE910014
+#define CAIFR       0xFE910018
+#define CSTCR       0xFE910020
+#define CSECR       0xFE910024
+#define CRCNTR      0xFE910028
+#define CRCMPR      0xFE91002C
+#define CFLCR       0xFE910030
+#define CFSZR       0xFE910034
+#define CDWDR       0xFE910038
+#define CDAYR       0xFE91003C
+#define CDACR       0xFE910040
+#define CDBYR       0xFE910044
+#define CDBCR       0xFE910048
+#define CBDSR       0xFE91004C
+#define CLFCR       0xFE910060
+#define CDOCR       0xFE910064
+#define CDDCR       0xFE910068
+#define CDDAR       0xFE91006C
+#define CEIER       0xFE910070
+#define CETCR       0xFE910074
+#define CSTSR       0xFE91007C
+#define CSRTR       0xFE910080
+#define CDAYR2      0xFE910090
+#define CDACR2      0xFE910094
+#define CDBYR2      0xFE910098
+#define CDBCR2      0xFE91009C
+
+/*	VIO(VEU)	*/
+#define VESTR       0xFE920000
+#define VESWR       0xFE920010
+#define VESSR       0xFE920014
+#define VSAYR       0xFE920018
+#define VSACR       0xFE92001C
+#define VBSSR       0xFE920020
+#define VEDWR       0xFE920030
+#define VDAYR       0xFE920034
+#define VDACR       0xFE920038
+#define VTRCR       0xFE920050
+#define VRFCR       0xFE920054
+#define VRFSR       0xFE920058
+#define VENHR       0xFE92005C
+#define VFMCR       0xFE920070
+#define VVTCR       0xFE920074
+#define VHTCR       0xFE920078
+#define VAPCR       0xFE920080
+#define VECCR       0xFE920084
+#define VAFXR       0xFE920090
+#define VSWPR       0xFE920094
+#define VEIER       0xFE9200A0
+#define VEVTR       0xFE9200A4
+#define VSTAR       0xFE9200B0
+#define VBSRR       0xFE9200B4
+
+/*	VIO(BEU)	*/
+#define BESTR       0xFE930000
+#define BSMWR1      0xFE930010
+#define BSSZR1      0xFE930014
+#define BSAYR1      0xFE930018
+#define BSACR1      0xFE93001C
+#define BSAAR1      0xFE930020
+#define BSIFR1      0xFE930024
+#define BSMWR2      0xFE930028
+#define BSSZR2      0xFE93002C
+#define BSAYR2      0xFE930030
+#define BSACR2      0xFE930034
+#define BSAAR2      0xFE930038
+#define BSIFR2      0xFE93003C
+#define BSMWR3      0xFE930040
+#define BSSZR3      0xFE930044
+#define BSAYR3      0xFE930048
+#define BSACR3      0xFE93004C
+#define BSAAR3      0xFE930050
+#define BSIFR3      0xFE930054
+#define BTPSR       0xFE930058
+#define BMSMWR1     0xFE930070
+#define BMSSZR1     0xFE930074
+#define BMSAYR1     0xFE930078
+#define BMSACR1     0xFE93007C
+#define BMSMWR2     0xFE930080
+#define BMSSZR2     0xFE930084
+#define BMSAYR2     0xFE930088
+#define BMSACR2     0xFE93008C
+#define BMSMWR3     0xFE930090
+#define BMSSZR3     0xFE930094
+#define BMSAYR3     0xFE930098
+#define BMSACR3     0xFE93009C
+#define BMSMWR4     0xFE9300A0
+#define BMSSZR4     0xFE9300A4
+#define BMSAYR4     0xFE9300A8
+#define BMSACR4     0xFE9300AC
+#define BMSIFR      0xFE9300F0
+#define BBLCR0      0xFE930100
+#define BBLCR1      0xFE930104
+#define BPROCR      0xFE930108
+#define BMWCR0      0xFE93010C
+#define BLOCR1      0xFE930114
+#define BLOCR2      0xFE930118
+#define BLOCR3      0xFE93011C
+#define BMLOCR1     0xFE930120
+#define BMLOCR2     0xFE930124
+#define BMLOCR3     0xFE930128
+#define BMLOCR4     0xFE93012C
+#define BMPCCR1     0xFE930130
+#define BMPCCR2     0xFE930134
+#define BPKFR       0xFE930140
+#define BPCCR0      0xFE930144
+#define BPCCR11     0xFE930148
+#define BPCCR12     0xFE93014C
+#define BPCCR21     0xFE930150
+#define BPCCR22     0xFE930154
+#define BPCCR31     0xFE930158
+#define BPCCR32     0xFE93015C
+#define BDMWR       0xFE930160
+#define BDAYR       0xFE930164
+#define BDACR       0xFE930168
+#define BAFXR       0xFE930180
+#define BSWPR       0xFE930184
+#define BEIER       0xFE930188
+#define BEVTR       0xFE93018C
+#define BRCNTR      0xFE930194
+#define BSTAR       0xFE930198
+#define BBRSTR      0xFE93019C
+#define BRCHR       0xFE9301A0
+#define CLUT        0xFE933000
+
+/*	JPU	*/
+#define JCMOD       0xFEA00000
+#define JCCMD       0xFEA00004
+#define JCSTS       0xFEA00008
+#define JCQTN       0xFEA0000C
+#define JCHTN       0xFEA00010
+#define JCDRIU      0xFEA00014
+#define JCDRID      0xFEA00018
+#define JCVSZU      0xFEA0001C
+#define JCVSZD      0xFEA00020
+#define JCHSZU      0xFEA00024
+#define JCHSZD      0xFEA00028
+#define JCDTCU      0xFEA0002C
+#define JCDTCM      0xFEA00030
+#define JCDTCD      0xFEA00034
+#define JINTE       0xFEA00038
+#define JINTS       0xFEA0003C
+#define JCDERR      0xFEA00040
+#define JCRST       0xFEA00044
+#define JIFCNT      0xFEA00060
+#define JIFECNT     0xFEA00070
+#define JIFESYA1    0xFEA00074
+#define JIFESCA1    0xFEA00078
+#define JIFESYA2    0xFEA0007C
+#define JIFESCA2    0xFEA00080
+#define JIFESMW     0xFEA00084
+#define JIFESVSZ    0xFEA00088
+#define JIFESHSZ    0xFEA0008C
+#define JIFEDA1     0xFEA00090
+#define JIFEDA2     0xFEA00094
+#define JIFEDRSZ    0xFEA00098
+#define JIFDCNT     0xFEA000A0
+#define JIFDSA1     0xFEA000A4
+#define JIFDSA2     0xFEA000A8
+#define JIFDDRSZ    0xFEA000AC
+#define JIFDDMW     0xFEA000B0
+#define JIFDDVSZ    0xFEA000B4
+#define JIFDDHSZ    0xFEA000B8
+#define JIFDDYA1    0xFEA000BC
+#define JIFDDCA1    0xFEA000C0
+#define JIFDDYA2    0xFEA000C4
+#define JIFDDCA2    0xFEA000C8
+#define JCQTBL0     0xFEA10000
+#define JCQTBL1     0xFEA10040
+#define JCQTBL2     0xFEA10080
+#define JCQTBL3     0xFEA100C0
+#define JCHTBD0     0xFEA10100
+#define JCHTBA0     0xFEA10120
+#define JCHTBD1     0xFEA10200
+#define JCHTBA1     0xFEA10220
+
+/*	LCDC	*/
+#define MLDDCKPAT1R 0xFE940400
+#define MLDDCKPAT2R 0xFE940404
+#define SLDDCKPAT1R 0xFE940408
+#define SLDDCKPAT2R 0xFE94040C
+#define LDDCKR      0xFE940410
+#define LDDCKSTPR   0xFE940414
+#define MLDMT1R     0xFE940418
+#define MLDMT2R     0xFE94041C
+#define MLDMT3R     0xFE940420
+#define MLDDFR      0xFE940424
+#define MLDSM1R     0xFE940428
+#define MLDSM2R     0xFE94042C
+#define MLDSA1R     0xFE940430
+#define MLDSA2R     0xFE940434
+#define MLDMLSR     0xFE940438
+#define MLDWBFR     0xFE94043C
+#define MLDWBCNTR   0xFE940440
+#define MLDWBAR     0xFE940444
+#define MLDHCNR     0xFE940448
+#define MLDHSYNR    0xFE94044C
+#define MLDVLNR     0xFE940450
+#define MLDVSYNR    0xFE940454
+#define MLDHPDR     0xFE940458
+#define MLDVPDR     0xFE94045C
+#define MLDPMR      0xFE940460
+#define LDPALCR     0xFE940464
+#define LDINTR      0xFE940468
+#define LDSR        0xFE94046C
+#define LDCNT1R     0xFE940470
+#define LDCNT2R     0xFE940474
+#define LDRCNTR     0xFE940478
+#define LDDDSR      0xFE94047C
+#define LDRCR       0xFE940484
+#define LDCMRKRGBR  0xFE9404C4
+#define LDCMRKCMYR  0xFE9404C8
+#define LDCMRK1R    0xFE9404CC
+#define LDCMRK2R    0xFE9404D0
+#define LDCMGKRGBR  0xFE9404D4
+#define LDCMGKCMYR  0xFE9404D8
+#define LDCMGK1R    0xFE9404DC
+#define LDCMGK2R    0xFE9404E0
+#define LDCMBKRGBR  0xFE9404E4
+#define LDCMBKCMYR  0xFE9404E8
+#define LDCMBK1R    0xFE9404EC
+#define LDCMBK2R    0xFE9404F0
+#define LDCMHKPR    0xFE9404F4
+#define LDCMHKQR    0xFE9404F8
+#define LDCMSELR    0xFE9404FC
+#define LDCMTVR     0xFE940500
+#define LDCMTVSELR  0xFE940504
+#define LDCMDTHR    0xFE940508
+#define LDCMCNTR    0xFE94050C
+#define SLDMT1R     0xFE940600
+#define SLDMT2R     0xFE940604
+#define SLDMT3R     0xFE940608
+#define SLDDFR      0xFE94060C
+#define SLDSM1R     0xFE940610
+#define SLDSM2R     0xFE940614
+#define SLDSA1R     0xFE940618
+#define SLDSA2R     0xFE94061C
+#define SLDMLSR     0xFE940620
+#define SLDHCNR     0xFE940624
+#define SLDHSYNR    0xFE940628
+#define SLDVLNR     0xFE94062C
+#define SLDVSYNR    0xFE940630
+#define SLDHPDR     0xFE940634
+#define SLDVPDR     0xFE940638
+#define SLDPMR      0xFE94063C
+#define LDDWD0R     0xFE940800
+#define LDDWD1R     0xFE940804
+#define LDDWD2R     0xFE940808
+#define LDDWD3R     0xFE94080C
+#define LDDWD4R     0xFE940810
+#define LDDWD5R     0xFE940814
+#define LDDWD6R     0xFE940818
+#define LDDWD7R     0xFE94081C
+#define LDDWD8R     0xFE940820
+#define LDDWD9R     0xFE940824
+#define LDDWDAR     0xFE940828
+#define LDDWDBR     0xFE94082C
+#define LDDWDCR     0xFE940830
+#define LDDWDDR     0xFE940834
+#define LDDWDER     0xFE940838
+#define LDDWDFR     0xFE94083C
+#define LDDRDR      0xFE940840
+#define LDDWAR      0xFE940900
+#define LDDRAR      0xFE940904
+#define LDPR00      0xFE940000
+
+/*	VOU	*/
+#define VOUER       0xFE960000
+#define VOUCR       0xFE960004
+#define VOUSTR      0xFE960008
+#define VOUVCR      0xFE96000C
+#define VOUISR      0xFE960010
+#define VOUBCR      0xFE960014
+#define VOUDPR      0xFE960018
+#define VOUDSR      0xFE96001C
+#define VOUVPR      0xFE960020
+#define VOUIR       0xFE960024
+#define VOUSRR      0xFE960028
+#define VOUMSR      0xFE96002C
+#define VOUHIR      0xFE960030
+#define VOUDFR      0xFE960034
+#define VOUAD1R     0xFE960038
+#define VOUAD2R     0xFE96003C
+#define VOUAIR      0xFE960040
+#define VOUSWR      0xFE960044
+#define VOURCR      0xFE960048
+#define VOURPR      0xFE960050
+
+/*	TSIF	*/
+#define TSCTLR      0xA4C80000
+#define TSPIDR      0xA4C80004
+#define TSCMDR      0xA4C80008
+#define TSSTR       0xA4C8000C
+#define TSTSDR      0xA4C80010
+#define TSBUFCLRR   0xA4C80014
+#define TSINTER     0xA4C80018
+#define TSPSCALER   0xA4C80020
+#define TSPSCALERR  0xA4C80024
+#define TSPCRADCMDR 0xA4C80028
+#define TSPCRADCR   0xA4C8002C
+#define TSTRPCRADCR 0xA4C80030
+#define TSDPCRADCR  0xA4C80034
+
+/*	SIU	*/
+#define IFCTL       0xA454C000
+#define SRCTL       0xA454C004
+#define SFORM       0xA454C008
+#define CKCTL       0xA454C00C
+#define TRDAT       0xA454C010
+#define STFIFO      0xA454C014
+#define DPAK        0xA454C01C
+#define CKREV       0xA454C020
+#define EVNTC       0xA454C028
+#define SBCTL       0xA454C040
+#define SBPSET      0xA454C044
+#define SBBUS       0xA454C048
+#define SBWFLG      0xA454C058
+#define SBRFLG      0xA454C05C
+#define SBWDAT      0xA454C060
+#define SBRDAT      0xA454C064
+#define SBFSTS      0xA454C068
+#define SBDVCA      0xA454C06C
+#define SBDVCB      0xA454C070
+#define SBACTIV     0xA454C074
+#define DMAIA       0xA454C090
+#define DMAIB       0xA454C094
+#define DMAOA       0xA454C098
+#define DMAOB       0xA454C09C
+#define SPLRI       0xA454C0B8
+#define SPRRI       0xA454C0BC
+#define SPURI       0xA454C0C4
+#define SPTIS       0xA454C0C8
+#define SPSTS       0xA454C0CC
+#define SPCTL       0xA454C0D0
+#define SPIRI       0xA454C0D4
+#define SPQCF       0xA454C0D8
+#define SPQCS       0xA454C0DC
+#define SPQCT       0xA454C0E0
+#define DPEAK       0xA454C0F0
+#define DSLPD       0xA454C0F4
+#define DSLLV       0xA454C0F8
+#define BRGASEL     0xA454C100
+#define BRRA        0xA454C104
+#define BRGBSEL     0xA454C108
+#define BRRB        0xA454C10C
+
+/*	USB	*/
+#define IFR0        0xA4480000
+#define ISR0        0xA4480010
+#define IER0        0xA4480020
+#define EPDR0I      0xA4480030
+#define EPDR0O      0xA4480034
+#define EPDR0S      0xA4480038
+#define EPDR1       0xA448003C
+#define EPDR2       0xA4480040
+#define EPDR3       0xA4480044
+#define EPDR4       0xA4480048
+#define EPDR5       0xA448004C
+#define EPDR6       0xA4480050
+#define EPDR7       0xA4480054
+#define EPDR8       0xA4480058
+#define EPDR9       0xA448005C
+#define EPSZ0O      0xA4480080
+#define EPSZ3       0xA4480084
+#define EPSZ6       0xA4480088
+#define EPSZ9       0xA448008C
+#define TRG         0xA44800A0
+#define DASTS       0xA44800A4
+#define FCLR        0xA44800AA
+#define DMA         0xA44800AC
+#define EPSTL       0xA44800B2
+#define CVR         0xA44800B4
+#define TSR         0xA44800B8
+#define CTLR        0xA44800BC
+#define EPIR        0xA44800C0
+#define XVERCR      0xA44800D0
+#define STLMR       0xA44800D4
+
+/*	KEYSC	*/
+#define KYCR1       0xA44B0000
+#define KYCR2       0xA44B0004
+#define KYINDR      0xA44B0008
+#define KYOUTDR     0xA44B000C
+
+/*	MMCIF	*/
+#define CMDR0       0xA4448000
+#define CMDR1       0xA4448001
+#define CMDR2       0xA4448002
+#define CMDR3       0xA4448003
+#define CMDR4       0xA4448004
+#define CMDR5       0xA4448005
+#define CMDSTRT     0xA4448006
+#define OPCR        0xA444800A
+#define CSTR        0xA444800B
+#define INTCR0      0xA444800C
+#define INTCR1      0xA444800D
+#define INTSTR0     0xA444800E
+#define INTSTR1     0xA444800F
+#define CLKON       0xA4448010
+#define CTOCR       0xA4448011
+#define VDCNT       0xA4448012
+#define TBCR        0xA4448014
+#define MODER       0xA4448016
+#define CMDTYR      0xA4448018
+#define RSPTYR      0xA4448019
+#define TBNCR       0xA444801A
+#define RSPR0       0xA4448020
+#define RSPR1       0xA4448021
+#define RSPR2       0xA4448022
+#define RSPR3       0xA4448023
+#define RSPR4       0xA4448024
+#define RSPR5       0xA4448025
+#define RSPR6       0xA4448026
+#define RSPR7       0xA4448027
+#define RSPR8       0xA4448028
+#define RSPR9       0xA4448029
+#define RSPR10      0xA444802A
+#define RSPR11      0xA444802B
+#define RSPR12      0xA444802C
+#define RSPR13      0xA444802D
+#define RSPR14      0xA444802E
+#define RSPR15      0xA444802F
+#define RSPR16      0xA4448030
+#define RSPRD       0xA4448031
+#define DTOUTR      0xA4448032
+#define DR          0xA4448040
+#define FIFOCLR     0xA4448042
+#define DMACR       0xA4448044
+#define INTCR2      0xA4448046
+#define INTSTR2     0xA4448048
+
+/*	Z3D3	*/
+#define DLBI        0xFD980000
+#define DLBD0       0xFD980080
+#define DLBD1       0xFD980100
+#define GEWM        0xFD984000
+#define ICD0        0xFD988000
+#define ICD1        0xFD989000
+#define ICT         0xFD98A000
+#define ILM         0xFD98C000
+#define FLM0        0xFD98C800
+#define FLM1        0xFD98D000
+#define FLUT        0xFD98D800
+#define Z3D_PC      0xFD98E400
+#define Z3D_PCSP    0xFD98E404
+#define Z3D_PAR     0xFD98E408
+#define Z3D_IMADR   0xFD98E40C
+#define Z3D_BTR0    0xFD98E410
+#define Z3D_BTR1    0xFD98E414
+#define Z3D_BTR2    0xFD98E418
+#define Z3D_BTR3    0xFD98E41C
+#define Z3D_LC0     0xFD98E420
+#define Z3D_LC1     0xFD98E424
+#define Z3D_LC2     0xFD98E428
+#define Z3D_LC3     0xFD98E42C
+#define Z3D_FR0     0xFD98E430
+#define Z3D_FR1     0xFD98E434
+#define Z3D_FR2     0xFD98E438
+#define Z3D_SR      0xFD98E440
+#define Z3D_SMDR    0xFD98E444
+#define Z3D_PBIR    0xFD98E448
+#define Z3D_DMDR    0xFD98E44C
+#define Z3D_IREG    0xFD98E460
+#define Z3D_AR00    0xFD98E480
+#define Z3D_AR01    0xFD98E484
+#define Z3D_AR02    0xFD98E488
+#define Z3D_AR03    0xFD98E48C
+#define Z3D_BR00    0xFD98E490
+#define Z3D_BR01    0xFD98E494
+#define Z3D_IXR00   0xFD98E4A0
+#define Z3D_IXR01   0xFD98E4A4
+#define Z3D_IXR02   0xFD98E4A8
+#define Z3D_IXR03   0xFD98E4AC
+#define Z3D_AR10    0xFD98E4C0
+#define Z3D_AR11    0xFD98E4C4
+#define Z3D_AR12    0xFD98E4C8
+#define Z3D_AR13    0xFD98E4CC
+#define Z3D_BR10    0xFD98E4D0
+#define Z3D_BR11    0xFD98E4D4
+#define Z3D_IXR10   0xFD98E4E0
+#define Z3D_IXR11   0xFD98E4E4
+#define Z3D_IXR12   0xFD98E4E8
+#define Z3D_IXR13   0xFD98E4EC
+#define Z3D_AR20    0xFD98E500
+#define Z3D_AR21    0xFD98E504
+#define Z3D_AR22    0xFD98E508
+#define Z3D_AR23    0xFD98E50C
+#define Z3D_BR20    0xFD98E510
+#define Z3D_BR21    0xFD98E514
+#define Z3D_IXR20   0xFD98E520
+#define Z3D_IXR21   0xFD98E524
+#define Z3D_IXR22   0xFD98E528
+#define Z3D_IXR23   0xFD98E52C
+#define Z3D_MR0     0xFD98E540
+#define Z3D_MR1     0xFD98E544
+#define Z3D_MR2     0xFD98E548
+#define Z3D_MR3     0xFD98E54C
+#define Z3D_WORKRST 0xFD98E558
+#define Z3D_WORKWST 0xFD98E55C
+#define Z3D_DBADR   0xFD98E560
+#define Z3D_DLBPRST 0xFD98E564
+#define Z3D_DLBRST  0xFD98E568
+#define Z3D_DLBWST  0xFD98E56C
+#define Z3D_UDR0    0xFD98E570
+#define Z3D_UDR1    0xFD98E574
+#define Z3D_UDR2    0xFD98E578
+#define Z3D_UDR3    0xFD98E57C
+#define Z3D_CCR0    0xFD98E580
+#define Z3D_CCR1    0xFD98E584
+#define Z3D_EXPR    0xFD98E588
+#define Z3D_V0_X    0xFD9A0000
+#define Z3D_V0_Y    0xFD9A0004
+#define Z3D_V0_Z    0xFD9A0008
+#define Z3D_V0_W    0xFD9A000C
+#define Z3D_V0_A    0xFD9A0010
+#define Z3D_V0_R    0xFD9A0014
+#define Z3D_V0_G    0xFD9A0018
+#define Z3D_V0_B    0xFD9A001C
+#define Z3D_V0_F    0xFD9A0020
+#define Z3D_V0_SR   0xFD9A0024
+#define Z3D_V0_SG   0xFD9A0028
+#define Z3D_V0_SB   0xFD9A002C
+#define Z3D_V0_U0   0xFD9A0030
+#define Z3D_V0_V0   0xFD9A0034
+#define Z3D_V0_U1   0xFD9A0038
+#define Z3D_V0_V1   0xFD9A003C
+#define Z3D_V1_X    0xFD9A0080
+#define Z3D_V1_Y    0xFD9A0084
+#define Z3D_V1_Z    0xFD9A0088
+#define Z3D_V1_W    0xFD9A008C
+#define Z3D_V1_A    0xFD9A0090
+#define Z3D_V1_R    0xFD9A0094
+#define Z3D_V1_G    0xFD9A0098
+#define Z3D_V1_B    0xFD9A009C
+#define Z3D_V1_F    0xFD9A00A0
+#define Z3D_V1_SR   0xFD9A00A4
+#define Z3D_V1_SG   0xFD9A00A8
+#define Z3D_V1_SB   0xFD9A00AC
+#define Z3D_V1_U0   0xFD9A00B0
+#define Z3D_V1_V0   0xFD9A00B4
+#define Z3D_V1_U1   0xFD9A00B8
+#define Z3D_V1_V1   0xFD9A00BC
+#define Z3D_V2_X    0xFD9A0100
+#define Z3D_V2_Y    0xFD9A0104
+#define Z3D_V2_Z    0xFD9A0108
+#define Z3D_V2_W    0xFD9A010C
+#define Z3D_V2_A    0xFD9A0110
+#define Z3D_V2_R    0xFD9A0114
+#define Z3D_V2_G    0xFD9A0118
+#define Z3D_V2_B    0xFD9A011C
+#define Z3D_V2_F    0xFD9A0120
+#define Z3D_V2_SR   0xFD9A0124
+#define Z3D_V2_SG   0xFD9A0128
+#define Z3D_V2_SB   0xFD9A012C
+#define Z3D_V2_U0   0xFD9A0130
+#define Z3D_V2_V0   0xFD9A0134
+#define Z3D_V2_U1   0xFD9A0138
+#define Z3D_V2_V1   0xFD9A013C
+#define Z3D_RENDER              0xFD9A0180
+#define Z3D_POLYGON_OFFSET      0xFD9A0184
+#define Z3D_VERTEX_CONTROL      0xFD9A0200
+#define Z3D_STATE_MODE          0xFD9A0204
+#define Z3D_FPU_MODE            0xFD9A0318
+#define Z3D_SCISSOR_MIN         0xFD9A0400
+#define Z3D_SCISSOR_MAX         0xFD9A0404
+#define Z3D_TEXTURE_MODE_A      0xFD9A0408
+#define Z3D_TEXTURE_MODE_B      0xFD9A040C
+#define Z3D_TEXTURE_BASE_HI_A   0xFD9A0418
+#define Z3D_TEXTURE_BASE_LO_A   0xFD9A041C
+#define Z3D_TEXTURE_BASE_HI_B   0xFD9A0420
+#define Z3D_TEXTURE_BASE_LO_B   0xFD9A0424
+#define Z3D_TEXTURE_ALPHA_A0    0xFD9A0438
+#define Z3D_TEXTURE_ALPHA_A1    0xFD9A043C
+#define Z3D_TEXTURE_ALPHA_A2    0xFD9A0440
+#define Z3D_TEXTURE_ALPHA_A3    0xFD9A0444
+#define Z3D_TEXTURE_ALPHA_A4    0xFD9A0448
+#define Z3D_TEXTURE_ALPHA_A5    0xFD9A044C
+#define Z3D_TEXTURE_ALPHA_B0    0xFD9A0450
+#define Z3D_TEXTURE_ALPHA_B1    0xFD9A0454
+#define Z3D_TEXTURE_ALPHA_B2    0xFD9A0458
+#define Z3D_TEXTURE_ALPHA_B3    0xFD9A045C
+#define Z3D_TEXTURE_ALPHA_B4    0xFD9A0460
+#define Z3D_TEXTURE_ALPHA_B5    0xFD9A0464
+#define Z3D_TEXTURE_FLUSH       0xFD9A0498
+#define Z3D_GAMMA_TABLE0        0xFD9A049C
+#define Z3D_GAMMA_TABLE1        0xFD9A04A0
+#define Z3D_GAMMA_TABLE2        0xFD9A04A4
+#define Z3D_ALPHA_TEST              0xFD9A0800
+#define Z3D_STENCIL_TEST            0xFD9A0804
+#define Z3D_DEPTH_ROP_BLEND_DITHER  0xFD9A0808
+#define Z3D_MASK                    0xFD9A080C
+#define Z3D_FBUS_MODE               0xFD9A0810
+#define Z3D_GNT_SET                 0xFD9A0814
+#define Z3D_BETWEEN_TEST            0xFD9A0818
+#define Z3D_FB_BASE                 0xFD9A081C
+#define Z3D_LCD_SIZE                0xFD9A0820
+#define Z3D_FB_FLUSH                0xFD9A0824
+#define Z3D_CACHE_INVALID           0xFD9A0828
+#define Z3D_SC_MODE         0xFD9A0830
+#define Z3D_SC0_MIN         0xFD9A0834
+#define Z3D_SC0_MAX         0xFD9A0838
+#define Z3D_SC1_MIN         0xFD9A083C
+#define Z3D_SC1_MAX         0xFD9A0840
+#define Z3D_SC2_MIN         0xFD9A0844
+#define Z3D_SC2_MAX         0xFD9A0848
+#define Z3D_SC3_MIN         0xFD9A084C
+#define Z3D_SC3_MAX         0xFD9A0850
+#define Z3D_READRESET       0xFD9A0854
+#define Z3D_DET_MIN         0xFD9A0858
+#define Z3D_DET_MAX         0xFD9A085C
+#define Z3D_FB_BASE_SR      0xFD9A0860
+#define Z3D_LCD_SIZE_SR     0xFD9A0864
+#define Z3D_2D_CTRL_STATUS          0xFD9A0C00
+#define Z3D_2D_SIZE                 0xFD9A0C04
+#define Z3D_2D_SRCLOC               0xFD9A0C08
+#define Z3D_2D_DSTLOC               0xFD9A0C0C
+#define Z3D_2D_DMAPORT              0xFD9A0C10
+#define Z3D_2D_CONSTANT_SOURCE0     0xFD9A0C14
+#define Z3D_2D_CONSTANT_SOURCE1     0xFD9A0C18
+#define Z3D_2D_STPCOLOR0            0xFD9A0C1C
+#define Z3D_2D_STPCOLOR1            0xFD9A0C20
+#define Z3D_2D_STPPARAMETER_SET0    0xFD9A0C24
+#define Z3D_2D_STPPARAMETER_SET1    0xFD9A0C28
+#define Z3D_2D_STPPAT_0     0xFD9A0C40
+#define Z3D_2D_STPPAT_1     0xFD9A0C44
+#define Z3D_2D_STPPAT_2     0xFD9A0C48
+#define Z3D_2D_STPPAT_3     0xFD9A0C4C
+#define Z3D_2D_STPPAT_4     0xFD9A0C50
+#define Z3D_2D_STPPAT_5     0xFD9A0C54
+#define Z3D_2D_STPPAT_6     0xFD9A0C58
+#define Z3D_2D_STPPAT_7     0xFD9A0C5C
+#define Z3D_2D_STPPAT_8     0xFD9A0C60
+#define Z3D_2D_STPPAT_9     0xFD9A0C64
+#define Z3D_2D_STPPAT_10    0xFD9A0C68
+#define Z3D_2D_STPPAT_11    0xFD9A0C6C
+#define Z3D_2D_STPPAT_12    0xFD9A0C70
+#define Z3D_2D_STPPAT_13    0xFD9A0C74
+#define Z3D_2D_STPPAT_14    0xFD9A0C78
+#define Z3D_2D_STPPAT_15    0xFD9A0C7C
+#define Z3D_2D_STPPAT_16    0xFD9A0C80
+#define Z3D_2D_STPPAT_17    0xFD9A0C84
+#define Z3D_2D_STPPAT_18    0xFD9A0C88
+#define Z3D_2D_STPPAT_19    0xFD9A0C8C
+#define Z3D_2D_STPPAT_20    0xFD9A0C90
+#define Z3D_2D_STPPAT_21    0xFD9A0C94
+#define Z3D_2D_STPPAT_22    0xFD9A0C98
+#define Z3D_2D_STPPAT_23    0xFD9A0C9C
+#define Z3D_2D_STPPAT_24    0xFD9A0CA0
+#define Z3D_2D_STPPAT_25    0xFD9A0CA4
+#define Z3D_2D_STPPAT_26    0xFD9A0CA8
+#define Z3D_2D_STPPAT_27    0xFD9A0CAC
+#define Z3D_2D_STPPAT_28    0xFD9A0CB0
+#define Z3D_2D_STPPAT_29    0xFD9A0CB4
+#define Z3D_2D_STPPAT_30    0xFD9A0CB8
+#define Z3D_2D_STPPAT_31    0xFD9A0CBC
+#define Z3D_WR_CTRL         0xFD9A1000
+#define Z3D_WR_P0           0xFD9A1004
+#define Z3D_WR_P1           0xFD9A1008
+#define Z3D_WR_P2           0xFD9A100C
+#define Z3D_WR_FGC          0xFD9A1010
+#define Z3D_WR_BGC          0xFD9A1014
+#define Z3D_WR_SZ           0xFD9A1018
+#define Z3D_WR_PATPARAM     0xFD9A101C
+#define Z3D_WR_PAT          0xFD9A1020
+#define Z3D_SYS_STATUS      0xFD9A1400
+#define Z3D_SYS_RESET       0xFD9A1404
+#define Z3D_SYS_CLK         0xFD9A1408
+#define Z3D_SYS_CONF        0xFD9A140C
+#define Z3D_SYS_VERSION     0xFD9A1410
+#define Z3D_SYS_DBINV       0xFD9A1418
+#define Z3D_SYS_I2F_FMT     0xFD9A1420
+#define Z3D_SYS_I2F_SRC     0xFD9A1424
+#define Z3D_SYS_I2F_DST     0xFD9A1428
+#define Z3D_SYS_GBCNT       0xFD9A1430
+#define Z3D_SYS_BSYCNT      0xFD9A1434
+#define Z3D_SYS_INT_STATUS  0xFD9A1450
+#define Z3D_SYS_INT_MASK    0xFD9A1454
+#define Z3D_SYS_INT_CLEAR   0xFD9A1458
+#define TCD0        0xFD9C0000
+#define TCD1        0xFD9C0400
+#define TCD2        0xFD9C0800
+#define TCD3        0xFD9C0C00
+#define TCT0        0xFD9C1000
+#define TCT1        0xFD9C1400
+#define TCT2        0xFD9C1800
+#define TCT3        0xFD9C1C00
+
+/*	PFC	*/
+#define PACR        0xA4050100
+#define PBCR        0xA4050102
+#define PCCR        0xA4050104
+#define PDCR        0xA4050106
+#define PECR        0xA4050108
+#define PFCR        0xA405010A
+#define PGCR        0xA405010C
+#define PHCR        0xA405010E
+#define PJCR        0xA4050110
+#define PKCR        0xA4050112
+#define PLCR        0xA4050114
+#define PMCR        0xA4050116
+#define PNCR        0xA4050118
+#define PQCR        0xA405011A
+#define PRCR        0xA405011C
+#define PSCR        0xA405011E
+#define PTCR        0xA4050140
+#define PUCR        0xA4050142
+#define PVCR        0xA4050144
+#define PWCR        0xA4050146
+#define PXCR        0xA4050148
+#define PYCR        0xA405014A
+#define PZCR        0xA405014C
+#define PSELA       0xA405014E
+#define PSELB       0xA4050150
+#define PSELC       0xA4050152
+#define PSELD       0xA4050154
+#define PSELE       0xA4050156
+#define HIZCRA      0xA4050158
+#define HIZCRB      0xA405015A
+#define HIZCRC      0xA405015C
+#define HIZCRC		0xA405015C
+#define MSELCRA		0xA4050180
+#define MSELCRB		0xA4050182
+#define PULCR		0xA4050184
+#define SBSCR		0xA4050186
+#define DRVCR		0xA405018A
+
+/*	I/O Port	*/
+#define PADR        0xA4050120
+#define PBDR        0xA4050122
+#define PCDR        0xA4050124
+#define PDDR        0xA4050126
+#define PEDR        0xA4050128
+#define PFDR        0xA405012A
+#define PGDR        0xA405012C
+#define PHDR        0xA405012E
+#define PJDR        0xA4050130
+#define PKDR        0xA4050132
+#define PLDR        0xA4050134
+#define PMDR        0xA4050136
+#define PNDR        0xA4050138
+#define PQDR        0xA405013A
+#define PRDR        0xA405013C
+#define PSDR        0xA405013E
+#define PTDR        0xA4050160
+#define PUDR        0xA4050162
+#define PVDR        0xA4050164
+#define PWDR        0xA4050166
+#define PXDR        0xA4050168
+#define PYDR        0xA405016A
+#define PZDR        0xA405016C
+
+/*	UBC	*/
+#define CBR0        0xFF200000
+#define CRR0        0xFF200004
+#define CAR0        0xFF200008
+#define CAMR0       0xFF20000C
+#define CBR1        0xFF200020
+#define CRR1        0xFF200024
+#define CAR1        0xFF200028
+#define CAMR1       0xFF20002C
+#define CDR1        0xFF200030
+#define CDMR1       0xFF200034
+#define CETR1       0xFF200038
+#define CCMFR       0xFF200600
+#define CBCR        0xFF200620
+
+/*	H-UDI	*/
+#define SDIR        0xFC110000
+#define SDDRH       0xFC110008
+#define SDDRL       0xFC11000A
+#define SDINT       0xFC110018
+
+#endif /* _ASM_CPU_SH7722_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7723.h b/arch/sh/include/asm/cpu_sh7723.h
new file mode 100644
index 0000000..59116cf
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7723.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008 Renesas Solutions Corp.
+ *
+ * SH7723 Internal I/O register
+ */
+
+#ifndef _ASM_CPU_SH7723_H_
+#define _ASM_CPU_SH7723_H_
+
+#define CACHE_OC_NUM_WAYS	4
+#define CCR_CACHE_INIT	0x0000090d
+
+/* EXP */
+#define TRA		0xFF000020
+#define EXPEVT	0xFF000024
+#define INTEVT	0xFF000028
+
+/* MMU */
+#define PTEH	0xFF000000
+#define PTEL	0xFF000004
+#define TTB		0xFF000008
+#define TEA		0xFF00000C
+#define MMUCR	0xFF000010
+#define PASCR	0xFF000070
+#define IRMCR	0xFF000078
+
+/* CACHE */
+#define CCR		0xFF00001C
+#define RAMCR	0xFF000074
+
+/* INTC */
+
+/* BSC */
+#define CMNCR		0xFEC10000
+#define	CS0BCR		0xFEC10004
+#define CS2BCR		0xFEC10008
+#define CS4BCR		0xFEC10010
+#define CS5ABCR		0xFEC10014
+#define CS5BBCR		0xFEC10018
+#define CS6ABCR		0xFEC1001C
+#define CS6BBCR		0xFEC10020
+#define CS0WCR		0xFEC10024
+#define CS2WCR		0xFEC10028
+#define CS4WCR		0xFEC10030
+#define CS5AWCR		0xFEC10034
+#define CS5BWCR		0xFEC10038
+#define CS6AWCR		0xFEC1003C
+#define CS6BWCR		0xFEC10040
+#define RBWTCNT		0xFEC10054
+
+/* SBSC */
+#define SBSC_SDCR	0xFE400008
+#define SBSC_SDWCR	0xFE40000C
+#define SBSC_SDPCR	0xFE400010
+#define SBSC_RTCSR	0xFE400014
+#define SBSC_RTCNT	0xFE400018
+#define SBSC_RTCOR	0xFE40001C
+#define SBSC_RFCR	0xFE400020
+
+/* DMAC */
+
+/* CPG */
+#define FRQCR       0xA4150000
+#define VCLKCR      0xA4150004
+#define SCLKACR     0xA4150008
+#define SCLKBCR     0xA415000C
+#define IRDACLKCR   0xA4150018
+#define PLLCR       0xA4150024
+#define DLLFRQ      0xA4150050
+
+/* LOW POWER MODE */
+#define STBCR       0xA4150020
+#define MSTPCR0     0xA4150030
+#define MSTPCR1     0xA4150034
+#define MSTPCR2     0xA4150038
+
+/* RWDT */
+#define RWTCNT      0xA4520000
+#define RWTCSR      0xA4520004
+#define WTCNT		RWTCNT
+
+/* TMU */
+#define TMU_BASE	0xFFD80000
+
+/* TPU */
+
+/* CMT */
+#define CMSTR       0xA44A0000
+#define CMCSR       0xA44A0060
+#define CMCNT       0xA44A0064
+#define CMCOR       0xA44A0068
+
+/* MSIOF */
+
+/* SCIF */
+#define SCIF0_BASE  0xFFE00000
+#define SCIF1_BASE  0xFFE10000
+#define SCIF2_BASE  0xFFE20000
+#define SCIF3_BASE  0xa4e30000
+#define SCIF4_BASE  0xa4e40000
+#define SCIF5_BASE  0xa4e50000
+
+/* RTC */
+/* IrDA */
+/* KEYSC */
+/* USB */
+/* IIC */
+/* FLCTL */
+/* VPU */
+/* VIO(CEU) */
+/* VIO(VEU) */
+/* VIO(BEU) */
+/* 2DG */
+/* LCDC */
+/* VOU */
+/* TSIF */
+/* SIU */
+/* ATAPI */
+
+/* PFC */
+#define PACR        0xA4050100
+#define PBCR        0xA4050102
+#define PCCR        0xA4050104
+#define PDCR        0xA4050106
+#define PECR        0xA4050108
+#define PFCR        0xA405010A
+#define PGCR        0xA405010C
+#define PHCR        0xA405010E
+#define PJCR        0xA4050110
+#define PKCR        0xA4050112
+#define PLCR        0xA4050114
+#define PMCR        0xA4050116
+#define PNCR        0xA4050118
+#define PQCR        0xA405011A
+#define PRCR        0xA405011C
+#define PSCR        0xA405011E
+#define PTCR        0xA4050140
+#define PUCR        0xA4050142
+#define PVCR        0xA4050144
+#define PWCR        0xA4050146
+#define PXCR        0xA4050148
+#define PYCR        0xA405014A
+#define PZCR        0xA405014C
+#define PSELA       0xA405014E
+#define PSELB       0xA4050150
+#define PSELC       0xA4050152
+#define PSELD       0xA4050154
+#define HIZCRA      0xA4050158
+#define HIZCRB      0xA405015A
+#define HIZCRC      0xA405015C
+#define HIZCRD      0xA405015E
+#define MSELCRA     0xA4050180
+#define MSELCRB     0xA4050182
+#define PULCR       0xA4050184
+#define DRVCRA      0xA405018A
+#define DRVCRB      0xA405018C
+
+/* I/O Port */
+#define PADR        0xA4050120
+#define PBDR        0xA4050122
+#define PCDR        0xA4050124
+#define PDDR        0xA4050126
+#define PEDR        0xA4050128
+#define PFDR        0xA405012A
+#define PGDR        0xA405012C
+#define PHDR        0xA405012E
+#define PJDR        0xA4050130
+#define PKDR        0xA4050132
+#define PLDR        0xA4050134
+#define PMDR        0xA4050136
+#define PNDR        0xA4050138
+#define PQDR        0xA405013A
+#define PRDR        0xA405013C
+#define PSDR        0xA405013E
+#define PTDR        0xA4050160
+#define PUDR        0xA4050162
+#define PVDR        0xA4050164
+#define PWDR        0xA4050166
+#define PXDR        0xA4050168
+#define PYDR        0xA405016A
+#define PZDR        0xA405016C
+
+/* UBC */
+/* H-UDI */
+
+#endif /* _ASM_CPU_SH7723_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7734.h b/arch/sh/include/asm/cpu_sh7734.h
new file mode 100644
index 0000000..546f4ff
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7734.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008, 2011 Renesas Solutions Corp.
+ *
+ * SH7734 Internal I/O register
+ */
+
+#ifndef _ASM_CPU_SH7734_H_
+#define _ASM_CPU_SH7734_H_
+
+#define CCR 0xFF00001C
+
+#define CACHE_OC_NUM_WAYS	4
+#define CCR_CACHE_INIT	0x0000090d
+
+/* SCIF */
+#define SCIF0_BASE  0xFFE40000
+#define SCIF1_BASE  0xFFE41000
+#define SCIF2_BASE  0xFFE42000
+#define SCIF3_BASE  0xFFE43000
+#define SCIF4_BASE  0xFFE44000
+#define SCIF5_BASE  0xFFE45000
+
+/* Timer */
+#define TMU_BASE 0xFFD80000
+
+/* PFC */
+#define PMMR    (0xFFFC0000)
+#define MODESEL0    (0xFFFC004C)
+#define MODESEL2    (MODESEL0 + 0x4)
+#define MODESEL2_INIT   (0x00003000)
+
+#define IPSR0	(0xFFFC001C)
+#define IPSR1	(IPSR0 + 0x4)
+#define IPSR2	(IPSR0 + 0x8)
+#define IPSR3	(IPSR0 + 0xC)
+#define IPSR4	(IPSR0 + 0x10)
+#define IPSR5	(IPSR0 + 0x14)
+#define IPSR6	(IPSR0 + 0x18)
+#define IPSR7	(IPSR0 + 0x1C)
+#define IPSR8	(IPSR0 + 0x20)
+#define IPSR9	(IPSR0 + 0x24)
+#define IPSR10	(IPSR0 + 0x28)
+#define IPSR11	(IPSR0 + 0x2C)
+
+#define GPSR0	(0xFFFC0004)
+#define GPSR1	(GPSR0 + 0x4)
+#define GPSR2	(GPSR0 + 0x8)
+#define GPSR3	(GPSR0 + 0xC)
+#define GPSR4	(GPSR0 + 0x10)
+#define GPSR5	(GPSR0 + 0x14)
+
+
+#endif /* _ASM_CPU_SH7734_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7750.h b/arch/sh/include/asm/cpu_sh7750.h
new file mode 100644
index 0000000..e0cafbd
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7750.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SH7750/SH7750S/SH7750R/SH7751/SH7751R
+ *  Internal I/O register
+ */
+
+#ifndef _ASM_CPU_SH7750_H_
+#define _ASM_CPU_SH7750_H_
+
+#ifdef CONFIG_CPU_TYPE_R
+#define CACHE_OC_NUM_WAYS     2
+#define CCR_CACHE_INIT   0x8000090D     /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
+#else
+#define CACHE_OC_NUM_WAYS     1
+#define CCR_CACHE_INIT   0x0000090B
+#endif
+
+/*      OCN     */
+#define PTEH	0xFF000000
+#define PTEL	0xFF000004
+#define TTB	0xFF000008
+#define TEA	0xFF00000C
+#define MMUCR	0xFF000010
+#define BASRA	0xFF000014
+#define BASRB	0xFF000018
+#define CCR	0xFF00001C
+#define TRA	0xFF000020
+#define EXPEVT	0xFF000024
+#define INTEVT	0xFF000028
+#define PTEA	0xFF000034
+#define QACR0	0xFF000038
+#define QACR1	0xFF00003C
+
+/*      UBC     */
+#define BARA	0xFF200000
+#define BAMRA	0xFF200004
+#define BBRA	0xFF200008
+#define BARB	0xFF20000C
+#define BAMRB	0xFF200010
+#define BBRB	0xFF200014
+#define BDRB	0xFF200018
+#define BDMRB	0xFF20001C
+#define BRCR	0xFF200020
+
+/*      BSC     */
+#define BCR1	0xFF800000
+#define BCR2	0xFF800004
+#define BCR3	0xFF800050
+#define BCR4	0xFE0A00F0
+#define WCR1	0xFF800008
+#define WCR2	0xFF80000C
+#define WCR3	0xFF800010
+#define MCR	0xFF800014
+#define PCR	0xFF800018
+#define RTCSR	0xFF80001C
+#define RTCNT	0xFF800020
+#define RTCOR	0xFF800024
+#define RFCR	0xFF800028
+#define PCTRA	0xFF80002C
+#define PDTRA	0xFF800030
+#define PCTRB	0xFF800040
+#define PDTRB	0xFF800044
+#define GPIOIC	0xFF800048
+
+/*      DMAC    */
+#define SAR0	0xFFA00000
+#define DAR0	0xFFA00004
+#define DMATCR0 0xFFA00008
+#define CHCR0	0xFFA0000C
+#define SAR1	0xFFA00010
+#define DAR1	0xFFA00014
+#define DMATCR1 0xFFA00018
+#define CHCR1	0xFFA0001C
+#define SAR2	0xFFA00020
+#define DAR2	0xFFA00024
+#define DMATCR2 0xFFA00028
+#define CHCR2	0xFFA0002C
+#define SAR3	0xFFA00030
+#define DAR3	0xFFA00034
+#define DMATCR3 0xFFA00038
+#define CHCR3	0xFFA0003C
+#define DMAOR	0xFFA00040
+#define SAR4	0xFFA00050
+#define DAR4	0xFFA00054
+#define DMATCR4 0xFFA00058
+
+/*      CPG     */
+#define FRQCR	0xFFC00000
+#define STBCR	0xFFC00004
+#define WTCNT	0xFFC00008
+#define WTCSR	0xFFC0000C
+#define STBCR2	0xFFC00010
+
+/*      RTC     */
+#define R64CNT	0xFFC80000
+#define RSECCNT 0xFFC80004
+#define RMINCNT 0xFFC80008
+#define RHRCNT	0xFFC8000C
+#define RWKCNT	0xFFC80010
+#define RDAYCNT 0xFFC80014
+#define RMONCNT 0xFFC80018
+#define RYRCNT	0xFFC8001C
+#define RSECAR	0xFFC80020
+#define RMINAR	0xFFC80024
+#define RHRAR	0xFFC80028
+#define RWKAR	0xFFC8002C
+#define RDAYAR	0xFFC80030
+#define RMONAR	0xFFC80034
+#define RCR1	0xFFC80038
+#define RCR2	0xFFC8003C
+#define RCR3	0xFFC80050
+#define RYRAR	0xFFC80054
+
+/*      ICR     */
+#define ICR	0xFFD00000
+#define IPRA	0xFFD00004
+#define IPRB	0xFFD00008
+#define IPRC	0xFFD0000C
+#define IPRD	0xFFD00010
+#define INTPRI	0xFE080000
+#define INTREQ	0xFE080020
+#define INTMSK	0xFE080040
+#define INTMSKCL	0xFE080060
+
+/*      CPG     */
+#define CLKSTP		0xFE0A0000
+#define CLKSTPCLR	0xFE0A0008
+
+/*      TMU     */
+#define TMU_BASE	0xFFD80000
+
+/*      SCI     */
+#define SCSMR1	0xFFE00000
+#define SCF0_BASE	SCSMR1
+
+/*      SCIF    */
+#define SCSMR2	0xFFE80000
+#define SCIF1_BASE	SCSMR2
+
+/*      H-UDI   */
+#define SDIR	0xFFF00000
+#define SDDR	0xFFF00008
+#define SDINT	0xFFF00014
+
+#endif	/* _ASM_CPU_SH7750_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7752.h b/arch/sh/include/asm/cpu_sh7752.h
new file mode 100644
index 0000000..e024423
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7752.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ */
+
+#ifndef _ASM_CPU_SH7752_H_
+#define _ASM_CPU_SH7752_H_
+
+#define CCR		0xFF00001C
+#define WTCNT		0xFFCC0000
+#define CCR_CACHE_INIT	0x0000090b
+#define CACHE_OC_NUM_WAYS	1
+
+#ifndef __ASSEMBLY__		/* put C only stuff in this section */
+/* MMU */
+struct mmu_regs {
+	unsigned int	reserved[4];
+	unsigned int	mmucr;
+};
+#define MMU_BASE	((struct mmu_regs *)0xff000000)
+
+/* Watchdog */
+#define WTCSR0		0xffcc0002
+#define WRSTCSR_R	0xffcc0003
+#define WRSTCSR_W	0xffcc0002
+#define WTCSR_PREFIX		0xa500
+#define WRSTCSR_PREFIX		0x6900
+#define WRSTCSR_WOVF_PREFIX	0x9600
+
+/* SCIF */
+#define SCIF0_BASE	0xfe4b0000	/* The real name is SCIF2 */
+#define SCIF1_BASE	0xfe4c0000	/* The real name is SCIF3 */
+#define SCIF2_BASE	0xfe4d0000	/* The real name is SCIF4 */
+
+/* TMU0 */
+#define TMU_BASE	 0xFE430000
+
+/* ETHER, GETHER MAC address */
+struct ether_mac_regs {
+	unsigned int	reserved[114];
+	unsigned int	mahr;
+	unsigned int	reserved2;
+	unsigned int	malr;
+};
+#define GETHER0_MAC_BASE	((struct ether_mac_regs *)0xfee0400)
+#define GETHER1_MAC_BASE	((struct ether_mac_regs *)0xfee0c00)
+#define ETHER0_MAC_BASE		((struct ether_mac_regs *)0xfef0000)
+#define ETHER1_MAC_BASE		((struct ether_mac_regs *)0xfef0800)
+
+/* GETHER */
+struct gether_control_regs {
+	unsigned int	gbecont;
+};
+#define GETHER_CONTROL_BASE	((struct gether_control_regs *)0xffc10100)
+#define GBECONT_RMII1		0x00020000
+#define GBECONT_RMII0		0x00010000
+
+/* SerMux */
+struct sermux_regs {
+	unsigned char	smr0;
+	unsigned char	smr1;
+	unsigned char	smr2;
+	unsigned char	smr3;
+	unsigned char	smr4;
+	unsigned char	smr5;
+};
+#define SERMUX_BASE	((struct sermux_regs *)0xfe470000)
+
+
+/* USB0/1 */
+struct usb_common_regs {
+	unsigned short	reserved[129];
+	unsigned short	suspmode;
+};
+#define USB0_COMMON_BASE	((struct usb_common_regs *)0xfe450000)
+#define USB1_COMMON_BASE	((struct usb_common_regs *)0xfe4f0000)
+
+struct usb0_phy_regs {
+	unsigned short	reset;
+	unsigned short	reserved[4];
+	unsigned short	portsel;
+};
+#define USB0_PHY_BASE		((struct usb0_phy_regs *)0xfe5f0000)
+
+struct usb1_port_regs {
+	unsigned int	port1sel;
+	unsigned int	reserved;
+	unsigned int	usb1intsts;
+};
+#define USB1_PORT_BASE		((struct usb1_port_regs *)0xfe4f2000)
+
+struct usb1_alignment_regs {
+	unsigned int	ehcidatac;	/* 0xfe4fe018 */
+	unsigned int	reserved[63];
+	unsigned int	ohcidatac;
+};
+#define USB1_ALIGNMENT_BASE	((struct usb1_alignment_regs *)0xfe4fe018)
+
+/* GPIO */
+struct gpio_regs {
+	unsigned short	pacr;
+	unsigned short	pbcr;
+	unsigned short	pccr;
+	unsigned short	pdcr;
+	unsigned short	pecr;
+	unsigned short	pfcr;
+	unsigned short	pgcr;
+	unsigned short	phcr;
+	unsigned short	picr;
+	unsigned short	pjcr;
+	unsigned short	pkcr;
+	unsigned short	plcr;
+	unsigned short	pmcr;
+	unsigned short	pncr;
+	unsigned short	pocr;
+	unsigned short	reserved;
+	unsigned short	pqcr;
+	unsigned short	prcr;
+	unsigned short	pscr;
+	unsigned short	ptcr;
+	unsigned short	pucr;
+	unsigned short	pvcr;
+	unsigned short	pwcr;
+	unsigned short	pxcr;
+	unsigned short	pycr;
+	unsigned short	pzcr;
+	unsigned char	padr;
+	unsigned char	reserved_a;
+	unsigned char	pbdr;
+	unsigned char	reserved_b;
+	unsigned char	pcdr;
+	unsigned char	reserved_c;
+	unsigned char	pddr;
+	unsigned char	reserved_d;
+	unsigned char	pedr;
+	unsigned char	reserved_e;
+	unsigned char	pfdr;
+	unsigned char	reserved_f;
+	unsigned char	pgdr;
+	unsigned char	reserved_g;
+	unsigned char	phdr;
+	unsigned char	reserved_h;
+	unsigned char	pidr;
+	unsigned char	reserved_i;
+	unsigned char	pjdr;
+	unsigned char	reserved_j;
+	unsigned char	pkdr;
+	unsigned char	reserved_k;
+	unsigned char	pldr;
+	unsigned char	reserved_l;
+	unsigned char	pmdr;
+	unsigned char	reserved_m;
+	unsigned char	pndr;
+	unsigned char	reserved_n;
+	unsigned char	podr;
+	unsigned char	reserved_o;
+	unsigned char	ppdr;
+	unsigned char	reserved_p;
+	unsigned char	pqdr;
+	unsigned char	reserved_q;
+	unsigned char	prdr;
+	unsigned char	reserved_r;
+	unsigned char	psdr;
+	unsigned char	reserved_s;
+	unsigned char	ptdr;
+	unsigned char	reserved_t;
+	unsigned char	pudr;
+	unsigned char	reserved_u;
+	unsigned char	pvdr;
+	unsigned char	reserved_v;
+	unsigned char	pwdr;
+	unsigned char	reserved_w;
+	unsigned char	pxdr;
+	unsigned char	reserved_x;
+	unsigned char	pydr;
+	unsigned char	reserved_y;
+	unsigned char	pzdr;
+	unsigned char	reserved_z;
+	unsigned short	ncer;
+	unsigned short	ncmcr;
+	unsigned short	nccsr;
+	unsigned char	reserved2[2];
+	unsigned short	psel0;		/* +0x70 */
+	unsigned short	psel1;
+	unsigned short	psel2;
+	unsigned short	psel3;
+	unsigned short	psel4;
+	unsigned short	psel5;
+	unsigned short	psel6;
+	unsigned short	reserved3[2];
+	unsigned short	psel7;
+};
+#define GPIO_BASE	((struct gpio_regs *)0xffec0000)
+
+#endif	/* ifndef __ASSEMBLY__ */
+#endif	/* _ASM_CPU_SH7752_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7753.h b/arch/sh/include/asm/cpu_sh7753.h
new file mode 100644
index 0000000..2f779b1
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7753.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ */
+
+#ifndef _ASM_CPU_SH7753_H_
+#define _ASM_CPU_SH7753_H_
+
+#define CCR		0xFF00001C
+#define WTCNT		0xFFCC0000
+#define CCR_CACHE_INIT	0x0000090b
+#define CACHE_OC_NUM_WAYS	1
+
+#ifndef __ASSEMBLY__		/* put C only stuff in this section */
+/* MMU */
+struct mmu_regs {
+	unsigned int	reserved[4];
+	unsigned int	mmucr;
+};
+#define MMU_BASE	((struct mmu_regs *)0xff000000)
+
+/* Watchdog */
+#define WTCSR0		0xffcc0002
+#define WRSTCSR_R	0xffcc0003
+#define WRSTCSR_W	0xffcc0002
+#define WTCSR_PREFIX		0xa500
+#define WRSTCSR_PREFIX		0x6900
+#define WRSTCSR_WOVF_PREFIX	0x9600
+
+/* SCIF */
+#define SCIF0_BASE	0xfe4b0000	/* The real name is SCIF2 */
+#define SCIF1_BASE	0xfe4c0000	/* The real name is SCIF3 */
+#define SCIF2_BASE	0xfe4d0000	/* The real name is SCIF4 */
+
+/* TMU0 */
+#define TMU_BASE	 0xFE430000
+
+/* ETHER, GETHER MAC address */
+struct ether_mac_regs {
+	unsigned int	reserved[114];
+	unsigned int	mahr;
+	unsigned int	reserved2;
+	unsigned int	malr;
+};
+#define GETHER0_MAC_BASE	((struct ether_mac_regs *)0xfee0400)
+#define GETHER1_MAC_BASE	((struct ether_mac_regs *)0xfee0c00)
+#define ETHER0_MAC_BASE		((struct ether_mac_regs *)0xfef0000)
+#define ETHER1_MAC_BASE		((struct ether_mac_regs *)0xfef0800)
+
+/* GETHER */
+struct gether_control_regs {
+	unsigned int	gbecont;
+};
+#define GETHER_CONTROL_BASE	((struct gether_control_regs *)0xffc10100)
+#define GBECONT_RMII1		0x00020000
+#define GBECONT_RMII0		0x00010000
+
+/* SerMux */
+struct sermux_regs {
+	unsigned char	smr0;
+	unsigned char	smr1;
+	unsigned char	smr2;
+	unsigned char	smr3;
+	unsigned char	smr4;
+	unsigned char	smr5;
+};
+#define SERMUX_BASE	((struct sermux_regs *)0xfe470000)
+
+
+/* USB0/1 */
+struct usb_common_regs {
+	unsigned short	reserved[129];
+	unsigned short	suspmode;
+};
+#define USB0_COMMON_BASE	((struct usb_common_regs *)0xfe450000)
+#define USB1_COMMON_BASE	((struct usb_common_regs *)0xfe4f0000)
+
+struct usb0_phy_regs {
+	unsigned short	reset;
+	unsigned short	reserved[4];
+	unsigned short	portsel;
+};
+#define USB0_PHY_BASE		((struct usb0_phy_regs *)0xfe5f0000)
+
+struct usb1_port_regs {
+	unsigned int	port1sel;
+	unsigned int	reserved;
+	unsigned int	usb1intsts;
+};
+#define USB1_PORT_BASE		((struct usb1_port_regs *)0xfe4f2000)
+
+struct usb1_alignment_regs {
+	unsigned int	ehcidatac;	/* 0xfe4fe018 */
+	unsigned int	reserved[63];
+	unsigned int	ohcidatac;
+};
+#define USB1_ALIGNMENT_BASE	((struct usb1_alignment_regs *)0xfe4fe018)
+
+/* GPIO */
+struct gpio_regs {
+	unsigned short	pacr;
+	unsigned short	pbcr;
+	unsigned short	pccr;
+	unsigned short	pdcr;
+	unsigned short	pecr;
+	unsigned short	pfcr;
+	unsigned short	pgcr;
+	unsigned short	phcr;
+	unsigned short	picr;
+	unsigned short	pjcr;
+	unsigned short	pkcr;
+	unsigned short	plcr;
+	unsigned short	pmcr;
+	unsigned short	pncr;
+	unsigned short	pocr;
+	unsigned short	reserved;
+	unsigned short	pqcr;
+	unsigned short	prcr;
+	unsigned short	pscr;
+	unsigned short	ptcr;
+	unsigned short	pucr;
+	unsigned short	pvcr;
+	unsigned short	pwcr;
+	unsigned short	pxcr;
+	unsigned short	pycr;
+	unsigned short	pzcr;
+	unsigned char	padr;
+	unsigned char	reserved_a;
+	unsigned char	pbdr;
+	unsigned char	reserved_b;
+	unsigned char	pcdr;
+	unsigned char	reserved_c;
+	unsigned char	pddr;
+	unsigned char	reserved_d;
+	unsigned char	pedr;
+	unsigned char	reserved_e;
+	unsigned char	pfdr;
+	unsigned char	reserved_f;
+	unsigned char	pgdr;
+	unsigned char	reserved_g;
+	unsigned char	phdr;
+	unsigned char	reserved_h;
+	unsigned char	pidr;
+	unsigned char	reserved_i;
+	unsigned char	pjdr;
+	unsigned char	reserved_j;
+	unsigned char	pkdr;
+	unsigned char	reserved_k;
+	unsigned char	pldr;
+	unsigned char	reserved_l;
+	unsigned char	pmdr;
+	unsigned char	reserved_m;
+	unsigned char	pndr;
+	unsigned char	reserved_n;
+	unsigned char	podr;
+	unsigned char	reserved_o;
+	unsigned char	ppdr;
+	unsigned char	reserved_p;
+	unsigned char	pqdr;
+	unsigned char	reserved_q;
+	unsigned char	prdr;
+	unsigned char	reserved_r;
+	unsigned char	psdr;
+	unsigned char	reserved_s;
+	unsigned char	ptdr;
+	unsigned char	reserved_t;
+	unsigned char	pudr;
+	unsigned char	reserved_u;
+	unsigned char	pvdr;
+	unsigned char	reserved_v;
+	unsigned char	pwdr;
+	unsigned char	reserved_w;
+	unsigned char	pxdr;
+	unsigned char	reserved_x;
+	unsigned char	pydr;
+	unsigned char	reserved_y;
+	unsigned char	pzdr;
+	unsigned char	reserved_z;
+	unsigned short	ncer;
+	unsigned short	ncmcr;
+	unsigned short	nccsr;
+	unsigned char	reserved2[2];
+	unsigned short	psel0;		/* +0x70 */
+	unsigned short	psel1;
+	unsigned short	psel2;
+	unsigned short	psel3;
+	unsigned short	psel4;
+	unsigned short	psel5;
+	unsigned short	psel6;
+	unsigned short	reserved3[2];
+	unsigned short	psel7;
+};
+#define GPIO_BASE	((struct gpio_regs *)0xffec0000)
+
+#endif	/* ifndef __ASSEMBLY__ */
+#endif	/* _ASM_CPU_SH7753_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7757.h b/arch/sh/include/asm/cpu_sh7757.h
new file mode 100644
index 0000000..b3aaec2
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7757.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ */
+
+#ifndef _ASM_CPU_SH7757_H_
+#define _ASM_CPU_SH7757_H_
+
+#define CCR		0xFF00001C
+#define WTCNT		0xFFCC0000
+#define CCR_CACHE_INIT	0x0000090b
+#define CACHE_OC_NUM_WAYS	1
+
+#ifndef __ASSEMBLY__		/* put C only stuff in this section */
+/* MMU */
+struct mmu_regs {
+	unsigned int	reserved[4];
+	unsigned int	mmucr;
+};
+#define MMU_BASE	((struct mmu_regs *)0xff000000)
+
+/* Watchdog */
+#define WTCSR0		0xffcc0002
+#define WRSTCSR_R	0xffcc0003
+#define WRSTCSR_W	0xffcc0002
+#define WTCSR_PREFIX		0xa500
+#define WRSTCSR_PREFIX		0x6900
+#define WRSTCSR_WOVF_PREFIX	0x9600
+
+/* SCIF */
+#define SCIF0_BASE	0xfe4b0000	/* The real name is SCIF2 */
+#define SCIF1_BASE	0xfe4c0000	/* The real name is SCIF3 */
+#define SCIF2_BASE	0xfe4d0000	/* The real name is SCIF4 */
+
+/* SerMux */
+#define SMR0		0xfe470000
+
+/* TMU0 */
+#define TMU_BASE    0xFE430000
+
+/* ETHER, GETHER MAC address */
+struct ether_mac_regs {
+	unsigned int	reserved[114];
+	unsigned int	mahr;
+	unsigned int	reserved2;
+	unsigned int	malr;
+};
+#define GETHER0_MAC_BASE	((struct ether_mac_regs *)0xfee0400)
+#define GETHER1_MAC_BASE	((struct ether_mac_regs *)0xfee0c00)
+#define ETHER0_MAC_BASE		((struct ether_mac_regs *)0xfef0000)
+#define ETHER1_MAC_BASE		((struct ether_mac_regs *)0xfef0800)
+
+/* GETHER */
+struct gether_control_regs {
+	unsigned int	gbecont;
+};
+#define GETHER_CONTROL_BASE	((struct gether_control_regs *)0xffc10100)
+#define GBECONT_RMII1		0x00020000
+#define GBECONT_RMII0		0x00010000
+
+/* USB0/1 */
+struct usb_common_regs {
+	unsigned short	reserved[129];
+	unsigned short	suspmode;
+};
+#define USB0_COMMON_BASE	((struct usb_common_regs *)0xfe450000)
+#define USB1_COMMON_BASE	((struct usb_common_regs *)0xfe4f0000)
+
+struct usb0_phy_regs {
+	unsigned short	reset;
+	unsigned short	reserved[4];
+	unsigned short	portsel;
+};
+#define USB0_PHY_BASE		((struct usb0_phy_regs *)0xfe5f0000)
+
+struct usb1_port_regs {
+	unsigned int	port1sel;
+	unsigned int	reserved;
+	unsigned int	usb1intsts;
+};
+#define USB1_PORT_BASE		((struct usb1_port_regs *)0xfe4f2000)
+
+struct usb1_alignment_regs {
+	unsigned int	ehcidatac;	/* 0xfe4fe018 */
+	unsigned int	reserved[63];
+	unsigned int	ohcidatac;
+};
+#define USB1_ALIGNMENT_BASE	((struct usb1_alignment_regs *)0xfe4fe018)
+
+/* GCTRL, GRA */
+struct gctrl_regs {
+	unsigned int	wprotect;
+	unsigned int	gplldiv;
+	unsigned int	gracr2;		/* GRA */
+	unsigned int	gracr3;		/* GRA */
+	unsigned int	reserved[4];
+	unsigned int	fcntcr1;
+	unsigned int	fcntcr2;
+	unsigned int	reserved2[2];
+	unsigned int	gpll1div;
+	unsigned int	vcompsel;
+	unsigned int	reserved3[62];
+	unsigned int	fdlmon;
+	unsigned int	reserved4[2];
+	unsigned int	flcrmon;
+	unsigned int	reserved5[944];
+	unsigned int	spibootcan;
+};
+#define GCTRL_BASE		((struct gctrl_regs *)0xffc10000)
+
+/* PCIe setup */
+struct pcie_setup_regs {
+	unsigned int	pbictl0;
+	unsigned int	gradevctl;
+	unsigned int	reserved[2];
+	unsigned int	bmcinf[6];
+	unsigned int	reserved2[118];
+	unsigned int	idset[2];
+	unsigned int	subidset;
+	unsigned int	reserved3[2];
+	unsigned int	linkconfset[4];
+	unsigned int	trsid;
+	unsigned int	reserved4[6];
+	unsigned int	toutset;
+	unsigned int	reserved5[7];
+	unsigned int	lad0;
+	unsigned int	ladmsk0;
+	unsigned int	lad1;
+	unsigned int	ladmsk1;
+	unsigned int	lad2;
+	unsigned int	ladmsk2;
+	unsigned int	lad3;
+	unsigned int	ladmsk3;
+	unsigned int	lad4;
+	unsigned int	ladmsk4;
+	unsigned int	lad5;
+	unsigned int	ladmsk5;
+	unsigned int	reserved6[94];
+	unsigned int	vdmrxvid[2];
+	unsigned int	reserved7;
+	unsigned int	pbiintfr;
+	unsigned int	pbiinten;
+	unsigned int	msimap;
+	unsigned int	barmap;
+	unsigned int	baracsize;
+	unsigned int	advserest;
+	unsigned int	pbictl3;
+	unsigned int	reserved8[8];
+	unsigned int	pbictl1;
+	unsigned int	scratch0;
+	unsigned int	reserved9[6];
+	unsigned int	pbictl2;
+	unsigned int	reserved10;
+	unsigned int	pbirev;
+};
+#define PCIE_SETUP_BASE		((struct pcie_setup_regs *)0xffca1000)
+
+struct pcie_system_bus_regs {
+	unsigned int	reserved[3];
+	unsigned int	endictl0;
+	unsigned int	endictl1;
+};
+#define PCIE_SYSTEM_BUS_BASE	((struct pcie_system_bus_regs *)0xffca1600)
+
+
+/* PCIe-Bridge */
+struct pciebrg_regs {
+	unsigned short	ctrl_h8s;
+	unsigned short	reserved[7];
+	unsigned short	cp_addr;
+	unsigned short	reserved2;
+	unsigned short	cp_data;
+	unsigned short	reserved3;
+	unsigned short	cp_ctrl;
+};
+#define PCIEBRG_BASE		((struct pciebrg_regs *)0xffd60000)
+
+/* CPU version */
+#define CCN_PRR			0xff000044
+#define prr_mask(_val)		((_val >> 4) & 0xff)
+#define PRR_SH7757_B0		0x10
+#define PRR_SH7757_C0		0x11
+
+#define is_sh7757_b0(_val)						\
+({									\
+	int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0;	\
+	__ret;								\
+})
+#endif	/* ifndef __ASSEMBLY__ */
+
+#endif	/* _ASM_CPU_SH7757_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7763.h b/arch/sh/include/asm/cpu_sh7763.h
new file mode 100644
index 0000000..e56d135
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7763.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+ */
+#ifndef _ASM_CPU_SH7763_H_
+#define _ASM_CPU_SH7763_H_
+
+/* CACHE */
+#define CACHE_OC_NUM_WAYS	1
+#define CCR				0xFF00001C
+#define CCR_CACHE_INIT	0x0000090b
+
+/* SCIF */
+/* SCIF0 */
+#define SCIF0_BASE	SCSMR0
+#define SCSMR0		0xFFE00000
+
+/* SCIF1 */
+#define SCIF1_BASE	SCSMR1
+#define SCSMR1		0xFFE08000
+
+/* SCIF2 */
+#define SCIF2_BASE	SCSMR2
+#define SCSMR2		0xFFE10000
+
+/* Watchdog Timer */
+#define WTCNT		WDTST
+#define WDTST		0xFFCC0000
+
+/* TMU */
+#define TMU_BASE	0xFFD80000
+
+#endif /* _ASM_CPU_SH7763_H_ */
diff --git a/arch/sh/include/asm/cpu_sh7780.h b/arch/sh/include/asm/cpu_sh7780.h
new file mode 100644
index 0000000..2ac3e93
--- /dev/null
+++ b/arch/sh/include/asm/cpu_sh7780.h
@@ -0,0 +1,447 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef	_ASM_CPU_SH7780_H_
+#define	_ASM_CPU_SH7780_H_
+
+/*
+ * Copyright (c) 2007,2008 Nobuhiro Iwamatsu
+ * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ */
+
+#define	CACHE_OC_NUM_WAYS	1
+#define	CCR_CACHE_INIT		0x0000090b
+
+/*	Exceptions	*/
+#define	TRA		0xFF000020
+#define	EXPEVT	0xFF000024
+#define	INTEVT	0xFF000028
+
+/* Memory Management Unit */
+#define	PTEH	0xFF000000
+#define	PTEL	0xFF000004
+#define	TTB		0xFF000008
+#define	TEA		0xFF00000C
+#define	MMUCR	0xFF000010
+#define	PASCR	0xFF000070
+#define	IRMCR	0xFF000078
+
+/* Cache Controller */
+#define	CCR		0xFF00001C
+#define	QACR0	0xFF000038
+#define	QACR1	0xFF00003C
+#define	RAMCR	0xFF000074
+
+/* L Memory	*/
+#define	RAMCR	0xFF000074
+#define	LSA0	0xFF000050
+#define	LSA1	0xFF000054
+#define	LDA0	0xFF000058
+#define	LDA1	0xFF00005C
+
+/* Interrupt Controller */
+#define	ICR0		0xFFD00000
+#define	ICR1		0xFFD0001C
+#define	INTPRI		0xFFD00010
+#define	INTREQ		0xFFD00024
+#define	INTMSK0		0xFFD00044
+#define	INTMSK1		0xFFD00048
+#define	INTMSK2		0xFFD40080
+#define	INTMSKCLR0	0xFFD00064
+#define	INTMSKCLR1	0xFFD00068
+#define	INTMSKCLR2	0xFFD40084
+#define	NMIFCR		0xFFD000C0
+#define	USERIMASK	0xFFD30000
+#define	INT2PRI0	0xFFD40000
+#define	INT2PRI1	0xFFD40004
+#define	INT2PRI2	0xFFD40008
+#define	INT2PRI3	0xFFD4000C
+#define	INT2PRI4	0xFFD40010
+#define	INT2PRI5	0xFFD40014
+#define	INT2PRI6	0xFFD40018
+#define	INT2PRI7	0xFFD4001C
+#define	INT2A0		0xFFD40030
+#define	INT2A1		0xFFD40034
+#define	INT2MSKR	0xFFD40038
+#define	INT2MSKCR	0xFFD4003C
+#define	INT2B0		0xFFD40040
+#define	INT2B1		0xFFD40044
+#define	INT2B2		0xFFD40048
+#define	INT2B3		0xFFD4004C
+#define	INT2B4		0xFFD40050
+#define	INT2B5		0xFFD40054
+#define	INT2B6		0xFFD40058
+#define	INT2B7		0xFFD4005C
+#define	INT2GPIC	0xFFD40090
+
+/* local Bus State Controller */
+#define	MMSELR		0xFF400020
+#define	BCR			0xFF801000
+#define	CS0BCR		0xFF802000
+#define	CS1BCR		0xFF802010
+#define	CS2BCR		0xFF802020
+#define	CS4BCR		0xFF802040
+#define	CS5BCR		0xFF802050
+#define	CS6BCR		0xFF802060
+#define	CS0WCR		0xFF802008
+#define	CS1WCR		0xFF802018
+#define	CS2WCR		0xFF802028
+#define	CS4WCR		0xFF802048
+#define	CS5WCR		0xFF802058
+#define	CS6WCR		0xFF802068
+#define	CS5PCR		0xFF802070
+#define	CS6PCR		0xFF802080
+
+/* DDR-SDRAM I/F */
+#define	MIM_1		0xFE800008
+#define	MIM_2		0xFE80000C
+#define	SCR_1		0xFE800010
+#define	SCR_2		0xFE800014
+#define	STR_1		0xFE800018
+#define	STR_2		0xFE80001C
+#define	SDR_1		0xFE800030
+#define	SDR_2		0xFE800034
+#define	DBK_1		0xFE800400
+#define	DBK_2		0xFE800404
+
+/* PCI	Controller */
+#define	SH7780_PCIECR		0xFE000008
+#define	SH7780_PCIVID		0xFE040000
+#define	SH7780_PCIDID		0xFE040002
+#define	SH7780_PCICMD		0xFE040004
+#define	SH7780_PCISTATUS	0xFE040006
+#define	SH7780_PCIRID		0xFE040008
+#define	SH7780_PCIPIF		0xFE040009
+#define	SH7780_PCISUB		0xFE04000A
+#define	SH7780_PCIBCC		0xFE04000B
+#define	SH7780_PCICLS		0xFE04000C
+#define	SH7780_PCILTM		0xFE04000D
+#define	SH7780_PCIHDR		0xFE04000E
+#define	SH7780_PCIBIST		0xFE04000F
+#define	SH7780_PCIIBAR		0xFE040010
+#define	SH7780_PCIMBAR0		0xFE040014
+#define	SH7780_PCIMBAR1		0xFE040018
+#define	SH7780_PCISVID		0xFE04002C
+#define	SH7780_PCISID		0xFE04002E
+#define	SH7780_PCICP		0xFE040034
+#define	SH7780_PCIINTLINE	0xFE04003C
+#define	SH7780_PCIINTPIN	0xFE04003D
+#define	SH7780_PCIMINGNT	0xFE04003E
+#define	SH7780_PCIMAXLAT	0xFE04003F
+#define	SH7780_PCICID		0xFE040040
+#define	SH7780_PCINIP		0xFE040041
+#define	SH7780_PCIPMC		0xFE040042
+#define	SH7780_PCIPMCSR		0xFE040044
+#define	SH7780_PCIPMCSRBSE	0xFE040046
+#define	SH7780_PCI_CDD		0xFE040047
+#define	SH7780_PCICR		0xFE040100
+#define	SH7780_PCILSR0		0xFE040104
+#define	SH7780_PCILSR1		0xFE040108
+#define	SH7780_PCILAR0		0xFE04010C
+#define	SH7780_PCILAR1		0xFE040110
+#define	SH7780_PCIIR		0xFE040114
+#define	SH7780_PCIIMR		0xFE040118
+#define	SH7780_PCIAIR		0xFE04011C
+#define	SH7780_PCICIR		0xFE040120
+#define	SH7780_PCIAINT		0xFE040130
+#define	SH7780_PCIAINTM		0xFE040134
+#define	SH7780_PCIBMIR		0xFE040138
+#define	SH7780_PCIPAR		0xFE0401C0
+#define	SH7780_PCIPINT		0xFE0401CC
+#define	SH7780_PCIPINTM		0xFE0401D0
+#define	SH7780_PCIMBR0		0xFE0401E0
+#define	SH7780_PCIMBMR0		0xFE0401E4
+#define	SH7780_PCIMBR1		0xFE0401E8
+#define	SH7780_PCIMBMR1		0xFE0401EC
+#define	SH7780_PCIMBR2		0xFE0401F0
+#define	SH7780_PCIMBMR2		0xFE0401F4
+#define	SH7780_PCIIOBR		0xFE0401F8
+#define	SH7780_PCIIOBMR		0xFE0401FC
+#define	SH7780_PCICSCR0		0xFE040210
+#define	SH7780_PCICSCR1		0xFE040214
+#define	SH7780_PCICSAR0		0xFE040218
+#define	SH7780_PCICSAR1		0xFE04021C
+#define	SH7780_PCIPDR		0xFE040220
+
+/* DMAC */
+#define	DMAC_SAR0	0xFC808020
+#define	DMAC_DAR0	0xFC808024
+#define	DMAC_TCR0	0xFC808028
+#define	DMAC_CHCR0	0xFC80802C
+#define	DMAC_SAR1	0xFC808030
+#define	DMAC_DAR1	0xFC808034
+#define	DMAC_TCR1	0xFC808038
+#define	DMAC_CHCR1	0xFC80803C
+#define	DMAC_SAR2	0xFC808040
+#define	DMAC_DAR2	0xFC808044
+#define	DMAC_TCR2	0xFC808048
+#define	DMAC_CHCR2	0xFC80804C
+#define	DMAC_SAR3	0xFC808050
+#define	DMAC_DAR3	0xFC808054
+#define	DMAC_TCR3	0xFC808058
+#define	DMAC_CHCR3	0xFC80805C
+#define	DMAC_DMAOR0	0xFC808060
+#define	DMAC_SAR4	0xFC808070
+#define	DMAC_DAR4	0xFC808074
+#define	DMAC_TCR4	0xFC808078
+#define	DMAC_CHCR4	0xFC80807C
+#define	DMAC_SAR5	0xFC808080
+#define	DMAC_DAR5	0xFC808084
+#define	DMAC_TCR5	0xFC808088
+#define	DMAC_CHCR5	0xFC80808C
+#define	DMAC_SARB0	0xFC808120
+#define	DMAC_DARB0	0xFC808124
+#define	DMAC_TCRB0	0xFC808128
+#define	DMAC_SARB1	0xFC808130
+#define	DMAC_DARB1	0xFC808134
+#define	DMAC_TCRB1	0xFC808138
+#define	DMAC_SARB2	0xFC808140
+#define	DMAC_DARB2	0xFC808144
+#define	DMAC_TCRB2	0xFC808148
+#define	DMAC_SARB3	0xFC808150
+#define	DMAC_DARB3	0xFC808154
+#define	DMAC_TCRB3	0xFC808158
+#define	DMAC_DMARS0	0xFC809000
+#define	DMAC_DMARS1	0xFC809004
+#define	DMAC_DMARS2	0xFC809008
+#define	DMAC_SAR6	0xFC818020
+#define	DMAC_DAR6	0xFC818024
+#define	DMAC_TCR6	0xFC818028
+#define	DMAC_CHCR6	0xFC81802C
+#define	DMAC_SAR7	0xFC818030
+#define	DMAC_DAR7	0xFC818034
+#define	DMAC_TCR7	0xFC818038
+#define	DMAC_CHCR7	0xFC81803C
+#define	DMAC_SAR8	0xFC818040
+#define	DMAC_DAR8	0xFC818044
+#define	DMAC_TCR8	0xFC818048
+#define	DMAC_CHCR8	0xFC81804C
+#define	DMAC_SAR9	0xFC818050
+#define	DMAC_DAR9	0xFC818054
+#define	DMAC_TCR9	0xFC818058
+#define	DMAC_CHCR9	0xFC81805C
+#define	DMAC_DMAOR1	0xFC818060
+#define	DMAC_SAR10	0xFC818070
+#define	DMAC_DAR10	0xFC818074
+#define	DMAC_TCR10	0xFC818078
+#define	DMAC_CHCR10	0xFC81807C
+#define	DMAC_SAR11	0xFC818080
+#define	DMAC_DAR11	0xFC818084
+#define	DMAC_TCR11	0xFC818088
+#define	DMAC_CHCR11	0xFC81808C
+#define	DMAC_SARB6	0xFC818120
+#define	DMAC_DARB6	0xFC818124
+#define	DMAC_TCRB6	0xFC818128
+#define	DMAC_SARB7	0xFC818130
+#define	DMAC_DARB7	0xFC818134
+#define	DMAC_TCRB7	0xFC818138
+#define	DMAC_SARB8	0xFC818140
+#define	DMAC_DARB8	0xFC818144
+#define	DMAC_TCRB8	0xFC818148
+#define	DMAC_SARB9	0xFC818150
+#define	DMAC_DARB9	0xFC818154
+#define	DMAC_TCRB9	0xFC818158
+
+/* Clock Pulse Generator */
+#define	FRQCR	0xFFC80000
+#define	PLLCR	0xFFC80024
+#define	MSTPCR	0xFFC80030
+
+/* Watchdog Timer and Reset */
+#define	WTCNT	WDTCNT
+#define	WDTST	0xFFCC0000
+#define	WDTCSR	0xFFCC0004
+#define	WDTBST	0xFFCC0008
+#define	WDTCNT	0xFFCC0010
+#define	WDTBCNT	0xFFCC0018
+
+/* System Control */
+#define	MSTPCR	0xFFC80030
+
+/* Timer Unit */
+#define TMU_BASE    0xFFD80000
+
+/* Timer/Counter */
+#define	CMTCFG	0xFFE30000
+#define	CMTFRT	0xFFE30004
+#define	CMTCTL	0xFFE30008
+#define	CMTIRQS	0xFFE3000C
+#define	CMTCH0T	0xFFE30010
+#define	CMTCH0ST	0xFFE30020
+#define	CMTCH0C	0xFFE30030
+#define	CMTCH1T	0xFFE30014
+#define	CMTCH1ST	0xFFE30024
+#define	CMTCH1C	0xFFE30034
+#define	CMTCH2T	0xFFE30018
+#define	CMTCH2C	0xFFE30038
+#define	CMTCH3T	0xFFE3001C
+#define	CMTCH3C	0xFFE3003C
+
+/* Realtime Clock */
+#define	R64CNT	0xFFE80000
+#define	RSECCNT	0xFFE80004
+#define	RMINCNT	0xFFE80008
+#define	RHRCNT	0xFFE8000C
+#define	RWKCNT	0xFFE80010
+#define	RDAYCNT	0xFFE80014
+#define	RMONCNT	0xFFE80018
+#define	RYRCNT	0xFFE8001C
+#define	RSECAR	0xFFE80020
+#define	RMINAR	0xFFE80024
+#define	RHRAR	0xFFE80028
+#define	RWKAR	0xFFE8002C
+#define	RDAYAR	0xFFE80030
+#define	RMONAR	0xFFE80034
+#define	RCR1	0xFFE80038
+#define	RCR2	0xFFE8003C
+#define	RCR3	0xFFE80050
+#define	RYRAR	0xFFE80054
+
+/* Serial Communication	Interface with FIFO */
+#define	SCSMR0	0xFFE00000
+#define	SCIF0_BASE SCSMR0
+
+/* Serial I/O with FIFO */
+#define	SIMDR	0xFFE20000
+#define	SISCR	0xFFE20002
+#define	SITDAR	0xFFE20004
+#define	SIRDAR	0xFFE20006
+#define	SICDAR	0xFFE20008
+#define	SICTR	0xFFE2000C
+#define	SIFCTR	0xFFE20010
+#define	SISTR	0xFFE20014
+#define	SIIER	0xFFE20016
+#define	SITCR	0xFFE20028
+#define	SIRCR	0xFFE2002C
+#define	SPICR	0xFFE20030
+
+/* Serial Protocol Interface */
+#define	SPCR	0xFFE50000
+#define	SPSR	0xFFE50004
+#define	SPSCR	0xFFE50008
+#define	SPTBR	0xFFE5000C
+#define	SPRBR	0xFFE50010
+
+/* Multimedia Card Interface */
+#define	CMDR0	0xFFE60000
+#define	CMDR1	0xFFE60001
+#define	CMDR2	0xFFE60002
+#define	CMDR3	0xFFE60003
+#define	CMDR4	0xFFE60004
+#define	CMDR5	0xFFE60005
+#define	CMDSTRT	0xFFE60006
+#define	OPCR	0xFFE6000A
+#define	CSTR	0xFFE6000B
+#define	INTCR0	0xFFE6000C
+#define	INTCR1	0xFFE6000D
+#define	INTSTR0	0xFFE6000E
+#define	INTSTR1	0xFFE6000F
+#define	CLKON	0xFFE60010
+#define	CTOCR	0xFFE60011
+#define	TBCR	0xFFE60014
+#define	MODER	0xFFE60016
+#define	CMDTYR	0xFFE60018
+#define	RSPTYR	0xFFE60019
+#define	TBNCR	0xFFE6001A
+#define	RSPR0	0xFFE60020
+#define	RSPR1	0xFFE60021
+#define	RSPR2	0xFFE60022
+#define	RSPR3	0xFFE60023
+#define	RSPR4	0xFFE60024
+#define	RSPR5	0xFFE60025
+#define	RSPR6	0xFFE60026
+#define	RSPR7	0xFFE60027
+#define	RSPR8	0xFFE60028
+#define	RSPR9	0xFFE60029
+#define	RSPR10	0xFFE6002A
+#define	RSPR11	0xFFE6002B
+#define	RSPR12	0xFFE6002C
+#define	RSPR13	0xFFE6002D
+#define	RSPR14	0xFFE6002E
+#define	RSPR15	0xFFE6002F
+#define	RSPR16	0xFFE60030
+#define	RSPRD	0xFFE60031
+#define	DTOUTR	0xFFE60032
+#define	DR		0xFFE60040
+#define	DMACR	0xFFE60044
+#define	INTCR2	0xFFE60046
+#define	INTSTR2	0xFFE60048
+
+/* Audio Codec Interface */
+#define	HACCR	0xFFE40008
+#define	HACCSAR	0xFFE40020
+#define	HACCSDR	0xFFE40024
+#define	HACPCML	0xFFE40028
+#define	HACPCMR	0xFFE4002C
+#define	HACTIER	0xFFE40050
+#define	HACTSR	0xFFE40054
+#define	HACRIER	0xFFE40058
+#define	HACRSR	0xFFE4005C
+#define	HACACR	0xFFE40060
+
+/* Serial Sound Interface */
+#define	SSICR	0xFFE70000
+#define	SSISR	0xFFE70004
+#define	SSITDR	0xFFE70008
+#define	SSIRDR	0xFFE7000C
+
+/* Flash memory Controller */
+#define	FLCMNCR	0xFFE90000
+#define	FLCMDCR	0xFFE90004
+#define	FLCMCDR	0xFFE90008
+#define	FLADR	0xFFE9000C
+#define	FLDATAR	0xFFE90010
+#define	FLDTCNTR	0xFFE90014
+#define	FLINTDMACR	0xFFE90018
+#define	FLBSYTMR	0xFFE9001C
+#define	FLBSYCNT	0xFFE90020
+#define	FLTRCR	0xFFE9002C
+
+/* General	Purpose	I/O */
+#define	PACR	0xFFEA0000
+#define	PBCR	0xFFEA0002
+#define	PCCR	0xFFEA0004
+#define	PDCR	0xFFEA0006
+#define	PECR	0xFFEA0008
+#define	PFCR	0xFFEA000A
+#define	PGCR	0xFFEA000C
+#define	PHCR	0xFFEA000E
+#define	PJCR	0xFFEA0010
+#define	PKCR	0xFFEA0012
+#define	PLCR	0xFFEA0014
+#define	PMCR	0xFFEA0016
+#define	PADR	0xFFEA0020
+#define	PBDR	0xFFEA0022
+#define	PCDR	0xFFEA0024
+#define	PDDR	0xFFEA0026
+#define	PEDR	0xFFEA0028
+#define	PFDR	0xFFEA002A
+#define	PGDR	0xFFEA002C
+#define	PHDR	0xFFEA002E
+#define	PJDR	0xFFEA0030
+#define	PKDR	0xFFEA0032
+#define	PLDR	0xFFEA0034
+#define	PMDR	0xFFEA0036
+#define	PEPUPR	0xFFEA0048
+#define	PHPUPR	0xFFEA004E
+#define	PJPUPR	0xFFEA0050
+#define	PKPUPR	0xFFEA0052
+#define	PMPUPR	0xFFEA0056
+#define	PPUPR1	0xFFEA0060
+#define	PPUPR2	0xFFEA0062
+#define	PMSELR	0xFFEA0080
+
+/* User	Break Controller */
+#define	CBR0	0xFF200000
+#define	CRR0	0xFF200004
+#define	CAR0	0xFF200008
+#define	CAMR0	0xFF20000C
+#define	CBR1	0xFF200020
+#define	CRR1	0xFF200024
+#define	CAR1	0xFF200028
+#define	CAMR1	0xFF20002C
+#define	CDR1	0xFF200030
+#define	CDMR1	0xFF200034
+#define	CETR1	0xFF200038
+#define	CCMFR	0xFF200600
+#define	CBCR	0xFF200620
+
+#endif	/* _ASM_CPU_SH7780_H_ */
diff --git a/arch/sh/include/asm/global_data.h b/arch/sh/include/asm/global_data.h
new file mode 100644
index 0000000..bd946ff
--- /dev/null
+++ b/arch/sh/include/asm/global_data.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#ifndef	__ASM_SH_GLOBALDATA_H_
+#define __ASM_SH_GLOBALDATA_H_
+
+/* Architecture-specific global data */
+struct arch_global_data {
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR	register gd_t *gd asm ("r13")
+
+#endif /* __ASM_SH_GLOBALDATA_H_ */
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
new file mode 100644
index 0000000..be1ff4a
--- /dev/null
+++ b/arch/sh/include/asm/io.h
@@ -0,0 +1,237 @@
+/*
+ *  linux/include/asm-sh/io.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
+ *			constant addresses and variable addresses.
+ *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
+ *			specific IO header files.
+ *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
+ *  04-Apr-1999	PJB	Added check_signature.
+ *  12-Dec-1999	RMK	More cleanups
+ *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_SH_IO_H
+#define __ASM_SH_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+/*
+ * Generic virtual read/write.  Note that we don't support half-word
+ * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
+ * to the architecture specific code.
+ */
+#define __arch_getb(a)			(*(volatile unsigned char *)(a))
+#define __arch_getw(a)			(*(volatile unsigned short *)(a))
+#define __arch_getl(a)			(*(volatile unsigned int *)(a))
+
+#define __arch_putb(v, a)		(*(volatile unsigned char *)(a) = (v))
+#define __arch_putw(v, a)		(*(volatile unsigned short *)(a) = (v))
+#define __arch_putl(v, a)		(*(volatile unsigned int *)(a) = (v))
+
+extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
+extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
+extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+
+extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
+extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
+extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+
+#define __raw_writeb(v, a)		__arch_putb(v, a)
+#define __raw_writew(v, a)		__arch_putw(v, a)
+#define __raw_writel(v, a)		__arch_putl(v, a)
+
+#define __raw_readb(a)			__arch_getb(a)
+#define __raw_readw(a)			__arch_getw(a)
+#define __raw_readl(a)			__arch_getl(a)
+
+/*
+ * The compiler seems to be incapable of optimising constants
+ * properly.  Spell it out to the compiler in some cases.
+ * These are only valid for small values of "off" (< 1<<12)
+ */
+#define __raw_base_writeb(val, base, off)	__arch_base_putb(val, base, off)
+#define __raw_base_writew(val, base, off)	__arch_base_putw(val, base, off)
+#define __raw_base_writel(val, base, off)	__arch_base_putl(val, base, off)
+
+#define __raw_base_readb(base, off)	__arch_base_getb(base, off)
+#define __raw_base_readw(base, off)	__arch_base_getw(base, off)
+#define __raw_base_readl(base, off)	__arch_base_getl(base, off)
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The SH doesn't have special IO access instructions; all IO is memory
+ * mapped.  Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#define outb(v, p)               __raw_writeb(v, p)
+#define outw(v, p)               __raw_writew(cpu_to_le16(v), p)
+#define outl(v, p)               __raw_writel(cpu_to_le32(v), p)
+
+#define inb(p)  ({ unsigned int __v = __raw_readb(p); __v; })
+#define inw(p)  ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
+#define inl(p)  ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
+
+#define outsb(p, d, l)			__raw_writesb(p, d, l)
+#define outsw(p, d, l)			__raw_writesw(p, d, l)
+#define outsl(p, d, l)			__raw_writesl(p, d, l)
+
+#define insb(p, d, l)			__raw_readsb(p, d, l)
+#define insw(p, d, l)			__raw_readsw(p, d, l)
+#define insl(p, d, l)			__raw_readsl(p, d, l)
+
+#define outb_p(val, port)		outb((val), (port))
+#define outw_p(val, port)		outw((val), (port))
+#define outl_p(val, port)		outl((val), (port))
+#define inb_p(port)			inb((port))
+#define inw_p(port)			inw((port))
+#define inl_p(port)			inl((port))
+
+#define outsb_p(port, from, len)		outsb(port, from, len)
+#define outsw_p(port, from, len)		outsw(port, from, len)
+#define outsl_p(port, from, len)		outsl(port, from, len)
+#define insb_p(port, to, len)		insb(port, to, len)
+#define insw_p(port, to, len)		insw(port, to, len)
+#define insl_p(port, to, len)		insl(port, to, len)
+
+/* for U-Boot PCI */
+#define out_8(port, val)	outb(val, port)
+#define out_le16(port, val)	outw(val, port)
+#define out_le32(port, val)	outl(val, port)
+#define in_8(port)			inb(port)
+#define in_le16(port)		inw(port)
+#define in_le32(port)		inl(port)
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, unsigned long, size_t);
+extern void _memcpy_toio(unsigned long, const void *, size_t);
+extern void _memset_io(unsigned long, int, size_t);
+
+/*
+ * If this architecture has PCI memory IO, then define the read/write
+ * macros.  These should only be used with the cookie passed from
+ * ioremap.
+ */
+#ifdef __mem_pci
+
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c)\
+	({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c)\
+	({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+
+#define writeb(v, c)		__raw_writeb(v, __mem_pci(c))
+#define writew(v, c)		__raw_writew(cpu_to_le16(v), __mem_pci(c))
+#define writel(v, c)		__raw_writel(cpu_to_le32(v), __mem_pci(c))
+
+#define memset_io(c, v, l)		_memset_io(__mem_pci(c), (v), (l))
+#define memcpy_fromio(a, c, l)	_memcpy_fromio((a), __mem_pci(c), (l))
+#define memcpy_toio(c, a, l)	_memcpy_toio(__mem_pci(c), (a), (l))
+
+#define eth_io_copy_and_sum(s, c, l, b) \
+				eth_copy_and_sum((s), __mem_pci(c), (l), (b))
+
+static inline int
+check_signature(unsigned long io_addr, const unsigned char *signature,
+		int length)
+{
+	int retval = 0;
+	do {
+		if (readb(io_addr) != *signature)
+			goto out;
+		io_addr++;
+		signature++;
+		length--;
+	} while (length);
+	retval = 1;
+out:
+	return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(addr)	__raw_readb(addr)
+#define readw(addr)	__raw_readw(addr)
+#define readl(addr)	__raw_readl(addr)
+#define writeb(v, addr)	__raw_writeb(v, addr)
+#define writew(v, addr)	__raw_writew(v, addr)
+#define writel(v, addr)	__raw_writel(v, addr)
+
+#define check_signature(io, sig, len)	(0)
+
+#endif	/* __mem_pci */
+
+static inline void sync(void)
+{
+}
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+		out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+		out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+		out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+#include <asm-generic/io.h>
+
+#endif	/* __KERNEL__ */
+#endif	/* __ASM_SH_IO_H */
diff --git a/arch/sh/include/asm/irqflags.h b/arch/sh/include/asm/irqflags.h
new file mode 100644
index 0000000..830e548
--- /dev/null
+++ b/arch/sh/include/asm/irqflags.h
@@ -0,0 +1,126 @@
+#ifndef __ASM_SH_IRQFLAGS_H
+#define __ASM_SH_IRQFLAGS_H
+
+static inline void raw_local_irq_enable(void)
+{
+	unsigned long __dummy0, __dummy1;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"and	%1, %0\n\t"
+#ifdef CONFIG_CPU_HAS_SR_RB
+		"stc	r6_bank, %1\n\t"
+		"or	%1, %0\n\t"
+#endif
+		"ldc	%0, sr\n\t"
+		: "=&r" (__dummy0), "=r" (__dummy1)
+		: "1" (~0x000000f0)
+		: "memory"
+	);
+}
+
+static inline void raw_local_irq_disable(void)
+{
+	unsigned long flags;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"or	#0xf0, %0\n\t"
+		"ldc	%0, sr\n\t"
+		: "=&z" (flags)
+		: /* no inputs */
+		: "memory"
+	);
+}
+
+static inline void set_bl_bit(void)
+{
+	unsigned long __dummy0, __dummy1;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"or	%2, %0\n\t"
+		"and	%3, %0\n\t"
+		"ldc	%0, sr\n\t"
+		: "=&r" (__dummy0), "=r" (__dummy1)
+		: "r" (0x10000000), "r" (0xffffff0f)
+		: "memory"
+	);
+}
+
+static inline void clear_bl_bit(void)
+{
+	unsigned long __dummy0, __dummy1;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"and	%2, %0\n\t"
+		"ldc	%0, sr\n\t"
+		: "=&r" (__dummy0), "=r" (__dummy1)
+		: "1" (~0x10000000)
+		: "memory"
+	);
+}
+
+static inline unsigned long __raw_local_save_flags(void)
+{
+	unsigned long flags;
+
+	__asm__ __volatile__ (
+		"stc	sr, %0\n\t"
+		"and	#0xf0, %0\n\t"
+		: "=&z" (flags)
+		: /* no inputs */
+		: "memory"
+	);
+
+	return flags;
+}
+
+#define raw_local_save_flags(flags) \
+		do { (flags) = __raw_local_save_flags(); } while (0)
+
+static inline int raw_irqs_disabled_flags(unsigned long flags)
+{
+	return (flags != 0);
+}
+
+static inline int raw_irqs_disabled(void)
+{
+	unsigned long flags = __raw_local_save_flags();
+
+	return raw_irqs_disabled_flags(flags);
+}
+
+static inline unsigned long __raw_local_irq_save(void)
+{
+	unsigned long flags, __dummy;
+
+	__asm__ __volatile__ (
+		"stc	sr, %1\n\t"
+		"mov	%1, %0\n\t"
+		"or	#0xf0, %0\n\t"
+		"ldc	%0, sr\n\t"
+		"mov	%1, %0\n\t"
+		"and	#0xf0, %0\n\t"
+		: "=&z" (flags), "=&r" (__dummy)
+		: /* no inputs */
+		: "memory"
+	);
+
+	return flags;
+}
+
+#define raw_local_irq_save(flags) \
+		do { (flags) = __raw_local_irq_save(); } while (0)
+
+#define local_irq_save raw_local_irq_save
+
+static inline void raw_local_irq_restore(unsigned long flags)
+{
+	if ((flags & 0xf0) != 0xf0)
+		raw_local_irq_enable();
+}
+#define local_irq_restore raw_local_irq_restore
+
+#endif /* __ASM_SH_IRQFLAGS_H */
diff --git a/arch/sh/include/asm/linkage.h b/arch/sh/include/asm/linkage.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/sh/include/asm/linkage.h
diff --git a/arch/sh/include/asm/macro.h b/arch/sh/include/asm/macro.h
new file mode 100644
index 0000000..e15ec0a
--- /dev/null
+++ b/arch/sh/include/asm/macro.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ */
+
+#ifndef __MACRO_H__
+#define __MACRO_H__
+#ifdef __ASSEMBLY__
+
+.macro	write32, addr, data
+	mov.l \addr ,r1
+	mov.l \data ,r0
+	mov.l r0, @r1
+.endm
+
+.macro	write16, addr, data
+	mov.l \addr ,r1
+	mov.w \data ,r0
+	mov.w r0, @r1
+.endm
+
+.macro	write8, addr, data
+	mov.l \addr ,r1
+	mov.l \data ,r0
+	mov.b r0, @r1
+.endm
+
+.macro	wait_timer, time
+	mov.l	\time ,r3
+1:
+	nop
+	tst	r3, r3
+	bf/s	1b
+	dt	r3
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __MACRO_H__ */
diff --git a/arch/sh/include/asm/mmc.h b/arch/sh/include/asm/mmc.h
new file mode 100644
index 0000000..5732b2b
--- /dev/null
+++ b/arch/sh/include/asm/mmc.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Renesas SuperH MMCIF driver.
+ *
+ * Copyright (C)  2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C)  2012 Renesas Solutions Corp.
+ *
+ */
+#ifndef _SH_MMC_H_
+#define _SH_MMC_H_
+
+int mmcif_mmc_init(void);
+
+#endif /* _SH_MMC_H_ */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
new file mode 100644
index 0000000..5d79d0e
--- /dev/null
+++ b/arch/sh/include/asm/pci.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * SH4 PCI Controller (PCIC) for U-Boot.
+ * (C) Dustin McIntire (dustin@sensoria.com)
+ * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * u-boot/include/asm-sh/pci.h
+ */
+#ifndef _ASM_PCI_H_
+#define _ASM_PCI_H_
+
+#include <pci.h>
+#if defined(CONFIG_SH7751_PCI)
+int pci_sh7751_init(struct pci_controller *hose);
+#elif defined(CONFIG_SH7780_PCI)
+int pci_sh7780_init(struct pci_controller *hose);
+#else
+#error "Not support PCI."
+#endif
+
+int pci_sh4_init(struct pci_controller *hose);
+/* PCI dword read for sh4 */
+int pci_sh4_read_config_dword(struct pci_controller *hose,
+		pci_dev_t dev, int offset, u32 *value);
+
+/* PCI dword write for sh4 */
+int pci_sh4_write_config_dword(struct pci_controller *hose,
+		pci_dev_t dev, int offset, u32 value);
+
+#endif	/* _ASM_PCI_H_ */
diff --git a/arch/sh/include/asm/posix_types.h b/arch/sh/include/asm/posix_types.h
new file mode 100644
index 0000000..c9d9fb8
--- /dev/null
+++ b/arch/sh/include/asm/posix_types.h
@@ -0,0 +1,123 @@
+#ifndef __ASM_SH_POSIX_TYPES_H
+#define __ASM_SH_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short  __kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned short	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid_t;
+typedef unsigned short	__kernel_gid_t;
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_timer_t;
+typedef int		__kernel_clockid_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+typedef unsigned short	__kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef	__FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef	__FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+	unsigned long __tmp = __fd / __NFDBITS;
+	unsigned long __rem = __fd % __NFDBITS;
+	return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef	__FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+	unsigned long *__tmp = __p->fds_bits;
+	int __i;
+
+	if (__builtin_constant_p(__FDSET_LONGS)) {
+		switch (__FDSET_LONGS) {
+		case 16:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			__tmp[ 8] = 0; __tmp[ 9] = 0;
+			__tmp[10] = 0; __tmp[11] = 0;
+			__tmp[12] = 0; __tmp[13] = 0;
+			__tmp[14] = 0; __tmp[15] = 0;
+			return;
+
+		case 8:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			__tmp[ 4] = 0; __tmp[ 5] = 0;
+			__tmp[ 6] = 0; __tmp[ 7] = 0;
+			return;
+
+		case 4:
+			__tmp[ 0] = 0; __tmp[ 1] = 0;
+			__tmp[ 2] = 0; __tmp[ 3] = 0;
+			return;
+		}
+	}
+	__i = __FDSET_LONGS;
+	while (__i) {
+		__i--;
+		*__tmp = 0;
+		__tmp++;
+	}
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* __ASM_SH_POSIX_TYPES_H */
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
new file mode 100644
index 0000000..09de94a
--- /dev/null
+++ b/arch/sh/include/asm/processor.h
@@ -0,0 +1,4 @@
+#ifndef _ASM_SH_PROCESSOR_H_
+#define _ASM_SH_PROCESSOR_H_
+# include <asm/cpu_sh4.h>
+#endif
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
new file mode 100644
index 0000000..16252cc
--- /dev/null
+++ b/arch/sh/include/asm/ptrace.h
@@ -0,0 +1,112 @@
+#ifndef __ASM_SH_PTRACE_H
+#define __ASM_SH_PTRACE_H
+
+/*
+ * Copyright (C) 1999, 2000  Niibe Yutaka
+ * from linux kernel code.
+ */
+
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ *	 0 - 15 are integer registers
+ *	17 - 22 are control/special registers
+ *	24 - 39 fp registers
+ *	40 - 47 xd registers
+ *	48 -    fpscr register
+ * -----------------------------
+ *
+ * We follows above, except:
+ *	16 --- program counter (PC)
+ *	22 --- syscall #
+ *	23 --- floating point communication register
+ */
+#define REG_REG0	 0
+#define REG_REG15	15
+
+#define REG_PC		16
+
+#define REG_PR		17
+#define REG_SR		18
+#define REG_GBR		19
+#define REG_MACH	20
+#define REG_MACL	21
+
+#define REG_SYSCALL	22
+
+#define REG_FPREG0	23
+#define REG_FPREG15	38
+#define REG_XFREG0	39
+#define REG_XFREG15	54
+
+#define REG_FPSCR	55
+#define REG_FPUL	56
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD     0x00000001
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_regs {
+	unsigned long regs[16];
+	unsigned long pc;
+	unsigned long pr;
+	unsigned long sr;
+	unsigned long gbr;
+	unsigned long mach;
+	unsigned long macl;
+	long tra;
+};
+
+/*
+ * This struct defines the way the DSP registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_dspregs {
+	unsigned long	a1;
+	unsigned long	a0g;
+	unsigned long	a1g;
+	unsigned long	m0;
+	unsigned long	m1;
+	unsigned long	a0;
+	unsigned long	x0;
+	unsigned long	x1;
+	unsigned long	y0;
+	unsigned long	y1;
+	unsigned long	dsr;
+	unsigned long	rs;
+	unsigned long	re;
+	unsigned long	mod;
+};
+
+#define	PTRACE_GETDSPREGS	55
+#define	PTRACE_SETDSPREGS	56
+
+#ifdef __KERNEL__
+#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
+#define instruction_pointer(regs) ((regs)->pc)
+extern void show_regs(struct pt_regs *);
+
+#ifdef CONFIG_SH_DSP
+#define task_pt_regs(task) \
+	((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+		 - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
+#else
+#define task_pt_regs(task) \
+	((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
+		 - sizeof(unsigned long)) - 1)
+#endif
+
+static inline unsigned long profile_pc(struct pt_regs *regs)
+{
+	unsigned long pc = instruction_pointer(regs);
+
+	if (pc >= 0xa0000000UL && pc < 0xc0000000UL)
+		pc -= 0x20000000;
+	return pc;
+}
+#endif
+
+#endif /* __ASM_SH_PTRACE_H */
diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
new file mode 100644
index 0000000..85859e5
--- /dev/null
+++ b/arch/sh/include/asm/sections.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_SH_SECTIONS_H
+#define __ASM_SH_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/sh/include/asm/string.h b/arch/sh/include/asm/string.h
new file mode 100644
index 0000000..999febc
--- /dev/null
+++ b/arch/sh/include/asm/string.h
@@ -0,0 +1,133 @@
+#ifndef __ASM_SH_STRING_H
+#define __ASM_SH_STRING_H
+
+/*
+ * Copyright (C) 1999 Niibe Yutaka
+ * But consider these trivial functions to be public domain.
+ *
+ * from linux kernel code.
+ */
+
+#ifdef __KERNEL__               /* only set these up for kernel code */
+
+#define __HAVE_ARCH_STRCPY
+static inline char *strcpy(char *__dest, const char *__src)
+{
+	register char *__xdest = __dest;
+	unsigned long __dummy;
+
+	__asm__ __volatile__("1:\n\t"
+			     "mov.b	@%1+, %2\n\t"
+			     "mov.b	%2, @%0\n\t"
+			     "cmp/eq	#0, %2\n\t"
+			     "bf/s	1b\n\t"
+			     " add	#1, %0\n\t"
+			     : "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+			     : "0" (__dest), "1" (__src)
+			     : "memory", "t");
+
+	return __xdest;
+}
+
+#define __HAVE_ARCH_STRNCPY
+static inline char *strncpy(char *__dest, const char *__src, size_t __n)
+{
+	register char *__xdest = __dest;
+	unsigned long __dummy;
+
+	if (__n == 0)
+		return __xdest;
+
+	__asm__ __volatile__(
+		"1:\n"
+		"mov.b	@%1+, %2\n\t"
+		"mov.b	%2, @%0\n\t"
+		"cmp/eq	#0, %2\n\t"
+		"bt/s	2f\n\t"
+		" cmp/eq	%5,%1\n\t"
+		"bf/s	1b\n\t"
+		" add	#1, %0\n"
+		"2:"
+		: "=r" (__dest), "=r" (__src), "=&z" (__dummy)
+		: "0" (__dest), "1" (__src), "r" (__src+__n)
+		: "memory", "t");
+
+	return __xdest;
+}
+
+#define __HAVE_ARCH_STRCMP
+static inline int strcmp(const char *__cs, const char *__ct)
+{
+	register int __res;
+	unsigned long __dummy;
+
+	__asm__ __volatile__(
+		"mov.b	@%1+, %3\n"
+		"1:\n\t"
+		"mov.b	@%0+, %2\n\t"
+		"cmp/eq #0, %3\n\t"
+		"bt	2f\n\t"
+		"cmp/eq %2, %3\n\t"
+		"bt/s	1b\n\t"
+		" mov.b	@%1+, %3\n\t"
+		"add	#-2, %1\n\t"
+		"mov.b	@%1, %3\n\t"
+		"sub	%3, %2\n"
+		"2:"
+		: "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
+		: "0" (__cs), "1" (__ct)
+		: "t");
+
+	return __res;
+}
+
+#undef __HAVE_ARCH_STRNCMP
+extern int strncmp(const char *__cs, const char *__ct, size_t __n);
+
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *__s, int __c, size_t __count);
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *__s, int __c, size_t __n);
+
+#undef __HAVE_ARCH_STRLEN
+extern size_t strlen(const char *);
+
+/* arch/sh/lib/strcasecmp.c */
+extern int strcasecmp(const char *, const char *);
+
+#else                           /* KERNEL */
+
+/*
+ * let user libraries deal with these,
+ * IMHO the kernel has no place defining these functions for user apps
+ */
+
+#define __HAVE_ARCH_STRCPY      1
+#define __HAVE_ARCH_STRNCPY     1
+#define __HAVE_ARCH_STRCAT      1
+#define __HAVE_ARCH_STRNCAT     1
+#define __HAVE_ARCH_STRCMP      1
+#define __HAVE_ARCH_STRNCMP     1
+#define __HAVE_ARCH_STRNICMP    1
+#define __HAVE_ARCH_STRCHR      1
+#define __HAVE_ARCH_STRRCHR     1
+#define __HAVE_ARCH_STRSTR      1
+#define __HAVE_ARCH_STRLEN      1
+#define __HAVE_ARCH_STRNLEN     1
+#define __HAVE_ARCH_MEMSET      1
+#define __HAVE_ARCH_MEMCPY      1
+#define __HAVE_ARCH_MEMMOVE     1
+#define __HAVE_ARCH_MEMSCAN     1
+#define __HAVE_ARCH_MEMCMP      1
+#define __HAVE_ARCH_MEMCHR      1
+#define __HAVE_ARCH_STRTOK      1
+
+#endif /* KERNEL */
+#endif /* __ASM_SH_STRING_H */
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
new file mode 100644
index 0000000..24b5ce8
--- /dev/null
+++ b/arch/sh/include/asm/system.h
@@ -0,0 +1,285 @@
+#ifndef __ASM_SH_SYSTEM_H
+#define __ASM_SH_SYSTEM_H
+
+/*
+ * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
+ * Copyright (C) 2002 Paul Mundt
+ *
+ * from linux kernel code.
+ */
+
+#include <asm/irqflags.h>
+#include <asm/types.h>
+
+/*
+ *	switch_to() should switch tasks to task nr n, first
+ */
+
+#define switch_to(prev, next, last) do {				\
+ struct task_struct *__last;						\
+ register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp;	\
+ register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc;	\
+ register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev;	\
+ register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next;	\
+ register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp;	\
+ register unsigned long __ts7 __asm__ ("r7") = next->thread.pc;		\
+ __asm__ __volatile__ (".balign 4\n\t"					\
+		       "stc.l	gbr, @-r15\n\t"				\
+		       "sts.l	pr, @-r15\n\t"				\
+		       "mov.l	r8, @-r15\n\t"				\
+		       "mov.l	r9, @-r15\n\t"				\
+		       "mov.l	r10, @-r15\n\t"				\
+		       "mov.l	r11, @-r15\n\t"				\
+		       "mov.l	r12, @-r15\n\t"				\
+		       "mov.l	r13, @-r15\n\t"				\
+		       "mov.l	r14, @-r15\n\t"				\
+		       "mov.l	r15, @r1	! save SP\n\t"		\
+		       "mov.l	@r6, r15	! change to new stack\n\t" \
+		       "mova	1f, %0\n\t"				\
+		       "mov.l	%0, @r2		! save PC\n\t"		\
+		       "mov.l	2f, %0\n\t"				\
+		       "jmp	@%0		! call __switch_to\n\t" \
+		       " lds	r7, pr		!  with return to new PC\n\t" \
+		       ".balign	4\n"					\
+		       "2:\n\t"						\
+		       ".long	__switch_to\n"				\
+		       "1:\n\t"						\
+		       "mov.l	@r15+, r14\n\t"				\
+		       "mov.l	@r15+, r13\n\t"				\
+		       "mov.l	@r15+, r12\n\t"				\
+		       "mov.l	@r15+, r11\n\t"				\
+		       "mov.l	@r15+, r10\n\t"				\
+		       "mov.l	@r15+, r9\n\t"				\
+		       "mov.l	@r15+, r8\n\t"				\
+		       "lds.l	@r15+, pr\n\t"				\
+		       "ldc.l	@r15+, gbr\n\t"				\
+		       : "=z" (__last)					\
+		       : "r" (__ts1), "r" (__ts2), "r" (__ts4),		\
+			 "r" (__ts5), "r" (__ts6), "r" (__ts7)		\
+		       : "r3", "t");					\
+	last = __last;							\
+} while (0)
+
+/*
+ * On SMP systems, when the scheduler does migration-cost autodetection,
+ * it needs a way to flush as much of the CPU's caches as possible.
+ *
+ * TODO: fill this in!
+ */
+static inline void sched_cacheflush(void)
+{
+}
+
+#ifdef CONFIG_CPU_SH4A
+#define __icbi()			\
+{					\
+	unsigned long __addr;		\
+	__addr = 0xa8000000;		\
+	__asm__ __volatile__(		\
+		"icbi   %0\n\t"		\
+		: /* no output */	\
+		: "m" (__m(__addr)));	\
+}
+#endif
+
+static inline unsigned long tas(volatile int *m)
+{
+	unsigned long retval;
+
+	__asm__ __volatile__ ("tas.b	@%1\n\t"
+			      "movt	%0"
+			      : "=r" (retval): "r" (m): "t", "memory");
+	return retval;
+}
+
+/*
+ * A brief note on ctrl_barrier(), the control register write barrier.
+ *
+ * Legacy SH cores typically require a sequence of 8 nops after
+ * modification of a control register in order for the changes to take
+ * effect. On newer cores (like the sh4a and sh5) this is accomplished
+ * with icbi.
+ *
+ * Also note that on sh4a in the icbi case we can forego a synco for the
+ * write barrier, as it's not necessary for control registers.
+ *
+ * Historically we have only done this type of barrier for the MMUCR, but
+ * it's also necessary for the CCR, so we make it generic here instead.
+ */
+#ifdef CONFIG_CPU_SH4A
+#define mb()		__asm__ __volatile__ ("synco": : :"memory")
+#define rmb()		mb()
+#define wmb()		__asm__ __volatile__ ("synco": : :"memory")
+#define ctrl_barrier()	__icbi()
+#define read_barrier_depends()	do { } while(0)
+#else
+#define mb()		__asm__ __volatile__ ("": : :"memory")
+#define rmb()		mb()
+#define wmb()		__asm__ __volatile__ ("": : :"memory")
+#define ctrl_barrier()	__asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
+#define read_barrier_depends()	do { } while(0)
+#endif
+
+#ifdef CONFIG_SMP
+#define smp_mb()	mb()
+#define smp_rmb()	rmb()
+#define smp_wmb()	wmb()
+#define smp_read_barrier_depends()	read_barrier_depends()
+#else
+#define smp_mb()	barrier()
+#define smp_rmb()	barrier()
+#define smp_wmb()	barrier()
+#define smp_read_barrier_depends()	do { } while(0)
+#endif
+
+#define set_mb(var, value) do { xchg(&var, value); } while (0)
+
+/*
+ * Jump to P2 area.
+ * When handling TLB or caches, we need to do it from P2 area.
+ */
+#define jump_to_P2()			\
+do {					\
+	unsigned long __dummy;		\
+	__asm__ __volatile__(		\
+		"mov.l	1f, %0\n\t"	\
+		"or	%1, %0\n\t"	\
+		"jmp	@%0\n\t"	\
+		" nop\n\t"		\
+		".balign 4\n"		\
+		"1:	.long 2f\n"	\
+		"2:"			\
+		: "=&r" (__dummy)	\
+		: "r" (0x20000000));	\
+} while (0)
+
+/*
+ * Back to P1 area.
+ */
+#define back_to_P1()					\
+do {							\
+	unsigned long __dummy;				\
+	ctrl_barrier();					\
+	__asm__ __volatile__(				\
+		"mov.l	1f, %0\n\t"			\
+		"jmp	@%0\n\t"			\
+		" nop\n\t"				\
+		".balign 4\n"				\
+		"1:	.long 2f\n"			\
+		"2:"					\
+		: "=&r" (__dummy));			\
+} while (0)
+
+static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
+{
+	unsigned long flags, retval;
+
+	local_irq_save(flags);
+	retval = *m;
+	*m = val;
+	local_irq_restore(flags);
+	return retval;
+}
+
+static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
+{
+	unsigned long flags, retval;
+
+	local_irq_save(flags);
+	retval = *m;
+	*m = val & 0xff;
+	local_irq_restore(flags);
+	return retval;
+}
+
+extern void __xchg_called_with_bad_pointer(void);
+
+#define __xchg(ptr, x, size)				\
+({							\
+	unsigned long __xchg__res;			\
+	volatile void *__xchg_ptr = (ptr);		\
+	switch (size) {					\
+	case 4:						\
+		__xchg__res = xchg_u32(__xchg_ptr, x);	\
+		break;					\
+	case 1:						\
+		__xchg__res = xchg_u8(__xchg_ptr, x);	\
+		break;					\
+	default:					\
+		__xchg_called_with_bad_pointer();	\
+		__xchg__res = x;			\
+		break;					\
+	}						\
+							\
+	__xchg__res;					\
+})
+
+#define xchg(ptr,x)	\
+	((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
+
+static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
+	unsigned long new)
+{
+	__u32 retval;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	retval = *m;
+	if (retval == old)
+		*m = new;
+	local_irq_restore(flags);       /* implies memory barrier  */
+	return retval;
+}
+
+/* This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg(). */
+extern void __cmpxchg_called_with_bad_pointer(void);
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
+		unsigned long new, int size)
+{
+	switch (size) {
+	case 4:
+		return __cmpxchg_u32(ptr, old, new);
+	}
+	__cmpxchg_called_with_bad_pointer();
+	return old;
+}
+
+#define cmpxchg(ptr,o,n)						 \
+  ({									 \
+     __typeof__(*(ptr)) _o_ = (o);					 \
+     __typeof__(*(ptr)) _n_ = (n);					 \
+     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,		 \
+				    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
+extern void *set_exception_table_vec(unsigned int vec, void *handler);
+
+static inline void *set_exception_table_evt(unsigned int evt, void *handler)
+{
+	return set_exception_table_vec(evt >> 5, handler);
+}
+
+/* XXX
+ * disable hlt during certain critical i/o operations
+ */
+#define HAVE_DISABLE_HLT
+void disable_hlt(void);
+void enable_hlt(void);
+
+#define arch_align_stack(x) (x)
+
+static inline void trigger_address_error(void)
+{
+	set_bl_bit();
+	__asm__ __volatile__ (
+		"mov.l @%1, %0"
+		:
+		: "r" (0x10000000), "r" (0x80000001)
+	);
+}
+
+#endif
diff --git a/arch/sh/include/asm/types.h b/arch/sh/include/asm/types.h
new file mode 100644
index 0000000..c5ddbbd
--- /dev/null
+++ b/arch/sh/include/asm/types.h
@@ -0,0 +1,32 @@
+#ifndef __ASM_SH_TYPES_H
+#define __ASM_SH_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_TYPES_H */
diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h
new file mode 100644
index 0000000..d1eb1ab
--- /dev/null
+++ b/arch/sh/include/asm/u-boot.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __ASM_SH_U_BOOT_H_
+#define __ASM_SH_U_BOOT_H_
+
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_SH
+
+#endif
diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h
new file mode 100644
index 0000000..9f4dd25
--- /dev/null
+++ b/arch/sh/include/asm/unaligned-sh4a.h
@@ -0,0 +1,258 @@
+#ifndef __ASM_SH_UNALIGNED_SH4A_H
+#define __ASM_SH_UNALIGNED_SH4A_H
+
+/*
+ * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
+ * Support for 64-bit accesses are done through shifting and masking
+ * relative to the endianness. Unaligned stores are not supported by the
+ * instruction encoding, so these continue to use the packed
+ * struct.
+ *
+ * The same note as with the movli.l/movco.l pair applies here, as long
+ * as the load is gauranteed to be inlined, nothing else will hook in to
+ * r0 and we get the return value for free.
+ *
+ * NOTE: Due to the fact we require r0 encoding, care should be taken to
+ * avoid mixing these heavily with other r0 consumers, such as the atomic
+ * ops. Failure to adhere to this can result in the compiler running out
+ * of spill registers and blowing up when building at low optimization
+ * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777.
+ */
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static __always_inline u32 __get_unaligned_cpu32(const u8 *p)
+{
+	unsigned long unaligned;
+
+	__asm__ __volatile__ (
+		"movua.l	@%1, %0\n\t"
+		 : "=z" (unaligned)
+		 : "r" (p)
+	);
+
+	return unaligned;
+}
+
+struct __una_u16 { u16 x __attribute__((packed)); };
+struct __una_u32 { u32 x __attribute__((packed)); };
+struct __una_u64 { u64 x __attribute__((packed)); };
+
+static inline u16 __get_unaligned_cpu16(const u8 *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return p[0] | p[1] << 8;
+#else
+	return p[0] << 8 | p[1];
+#endif
+}
+
+/*
+ * Even though movua.l supports auto-increment on the read side, it can
+ * only store to r0 due to instruction encoding constraints, so just let
+ * the compiler sort it out on its own.
+ */
+static inline u64 __get_unaligned_cpu64(const u8 *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (u64)__get_unaligned_cpu32(p + 4) << 32 |
+		    __get_unaligned_cpu32(p);
+#else
+	return (u64)__get_unaligned_cpu32(p) << 32 |
+		    __get_unaligned_cpu32(p + 4);
+#endif
+}
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+	return le16_to_cpu(__get_unaligned_cpu16(p));
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+	return le32_to_cpu(__get_unaligned_cpu32(p));
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+	return le64_to_cpu(__get_unaligned_cpu64(p));
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+	return be16_to_cpu(__get_unaligned_cpu16(p));
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+	return be32_to_cpu(__get_unaligned_cpu32(p));
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+	return be64_to_cpu(__get_unaligned_cpu64(p));
+}
+
+static inline void __put_le16_noalign(u8 *p, u16 val)
+{
+	*p++ = val;
+	*p++ = val >> 8;
+}
+
+static inline void __put_le32_noalign(u8 *p, u32 val)
+{
+	__put_le16_noalign(p, val);
+	__put_le16_noalign(p + 2, val >> 16);
+}
+
+static inline void __put_le64_noalign(u8 *p, u64 val)
+{
+	__put_le32_noalign(p, val);
+	__put_le32_noalign(p + 4, val >> 32);
+}
+
+static inline void __put_be16_noalign(u8 *p, u16 val)
+{
+	*p++ = val >> 8;
+	*p++ = val;
+}
+
+static inline void __put_be32_noalign(u8 *p, u32 val)
+{
+	__put_be16_noalign(p, val >> 16);
+	__put_be16_noalign(p + 2, val);
+}
+
+static inline void __put_be64_noalign(u8 *p, u64 val)
+{
+	__put_be32_noalign(p, val >> 32);
+	__put_be32_noalign(p + 4, val);
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+#ifdef __LITTLE_ENDIAN
+	((struct __una_u16 *)p)->x = val;
+#else
+	__put_le16_noalign(p, val);
+#endif
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+#ifdef __LITTLE_ENDIAN
+	((struct __una_u32 *)p)->x = val;
+#else
+	__put_le32_noalign(p, val);
+#endif
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+#ifdef __LITTLE_ENDIAN
+	((struct __una_u64 *)p)->x = val;
+#else
+	__put_le64_noalign(p, val);
+#endif
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+#ifdef __BIG_ENDIAN
+	((struct __una_u16 *)p)->x = val;
+#else
+	__put_be16_noalign(p, val);
+#endif
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+#ifdef __BIG_ENDIAN
+	((struct __una_u32 *)p)->x = val;
+#else
+	__put_be32_noalign(p, val);
+#endif
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+#ifdef __BIG_ENDIAN
+	((struct __una_u64 *)p)->x = val;
+#else
+	__put_be64_noalign(p, val);
+#endif
+}
+
+/*
+ * Cause a link-time error if we try an unaligned access other than
+ * 1,2,4 or 8 bytes long
+ */
+extern void __bad_unaligned_access_size(void);
+
+#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)),	\
+	__bad_unaligned_access_size()))));					\
+	}))
+
+#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)),	\
+	__bad_unaligned_access_size()))));					\
+	}))
+
+#define __put_unaligned_le(val, ptr) ({					\
+	void *__gu_p = (ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		*(u8 *)__gu_p = (__force u8)(val);			\
+		break;							\
+	case 2:								\
+		put_unaligned_le16((__force u16)(val), __gu_p);		\
+		break;							\
+	case 4:								\
+		put_unaligned_le32((__force u32)(val), __gu_p);		\
+		break;							\
+	case 8:								\
+		put_unaligned_le64((__force u64)(val), __gu_p);		\
+		break;							\
+	default:							\
+		__bad_unaligned_access_size();				\
+		break;							\
+	}								\
+	(void)0; })
+
+#define __put_unaligned_be(val, ptr) ({					\
+	void *__gu_p = (ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		*(u8 *)__gu_p = (__force u8)(val);			\
+		break;							\
+	case 2:								\
+		put_unaligned_be16((__force u16)(val), __gu_p);		\
+		break;							\
+	case 4:								\
+		put_unaligned_be32((__force u32)(val), __gu_p);		\
+		break;							\
+	case 8:								\
+		put_unaligned_be64((__force u64)(val), __gu_p);		\
+		break;							\
+	default:							\
+		__bad_unaligned_access_size();				\
+		break;							\
+	}								\
+	(void)0; })
+
+#ifdef __LITTLE_ENDIAN
+# define get_unaligned __get_unaligned_le
+# define put_unaligned __put_unaligned_le
+#else
+# define get_unaligned __get_unaligned_be
+# define put_unaligned __put_unaligned_be
+#endif
+
+#endif /* __ASM_SH_UNALIGNED_SH4A_H */
diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h
new file mode 100644
index 0000000..06096ee
--- /dev/null
+++ b/arch/sh/include/asm/unaligned.h
@@ -0,0 +1,25 @@
+#ifndef _ASM_SH_UNALIGNED_H
+#define _ASM_SH_UNALIGNED_H
+
+/* Copy from linux-kernel. */
+
+#ifdef CONFIG_CPU_SH4A
+/* SH-4A can handle unaligned loads in a relatively neutered fashion. */
+#include <asm/unaligned-sh4a.h>
+#else
+/* Otherwise, SH can't handle unaligned accesses. */
+#include <linux/compiler.h>
+#if defined(__BIG_ENDIAN__)
+#define get_unaligned   __get_unaligned_be
+#define put_unaligned   __put_unaligned_be
+#elif defined(__LITTLE_ENDIAN__)
+#define get_unaligned   __get_unaligned_le
+#define put_unaligned   __put_unaligned_le
+#endif
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+#endif
+
+#endif /* _ASM_SH_UNALIGNED_H */
diff --git a/arch/sh/include/asm/zimage.h b/arch/sh/include/asm/zimage.h
new file mode 100644
index 0000000..23be23d
--- /dev/null
+++ b/arch/sh/include/asm/zimage.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ *   Renesas Solutions Corp.
+ *   Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ */
+
+#ifndef _ASM_ZIMAGE_H_
+#define _ASM_ZIMAGE_H_
+
+#define MOUNT_ROOT_RDONLY	0x000
+#define RAMDISK_FLAGS		0x004
+#define ORIG_ROOT_DEV		0x008
+#define LOADER_TYPE			0x00c
+#define INITRD_START		0x010
+#define INITRD_SIZE			0x014
+#define COMMAND_LINE		0x100
+
+#define RD_PROMPT			(1<<15)
+#define RD_DOLOAD			(1<<14)
+#define CMD_ARG_RD_PROMPT	"prompt_ramdisk="
+#define CMD_ARG_RD_DOLOAD	"load_ramdisk="
+
+#endif
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
new file mode 100644
index 0000000..4475d04
--- /dev/null
+++ b/arch/x86/include/asm/acpi.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __ASM_ACPI_H__
+#define __ASM_ACPI_H__
+
+struct acpi_fadt;
+
+/**
+ * acpi_find_fadt() - find ACPI FADT table in the system memory
+ *
+ * This routine parses the ACPI table to locate the ACPI FADT table.
+ *
+ * @return:	a pointer to the ACPI FADT table in the system memory
+ */
+struct acpi_fadt *acpi_find_fadt(void);
+
+/**
+ * acpi_find_wakeup_vector() - find OS installed wake up vector address
+ *
+ * This routine parses the ACPI table to locate the wake up vector installed
+ * by the OS previously.
+ *
+ * @fadt:	a pointer to the ACPI FADT table in the system memory
+ * @return:	wake up vector address installed by the OS
+ */
+void *acpi_find_wakeup_vector(struct acpi_fadt *fadt);
+
+/**
+ * enter_acpi_mode() - enter into ACPI mode
+ *
+ * This programs the ACPI-defined PM1_CNT register to enable SCI interrupt
+ * so that the whole system swiches to ACPI mode.
+ *
+ * @pm1_cnt:	PM1_CNT register I/O address
+ */
+void enter_acpi_mode(int pm1_cnt);
+
+#endif /* __ASM_ACPI_H__ */
diff --git a/arch/x86/include/asm/acpi/debug.asl b/arch/x86/include/asm/acpi/debug.asl
new file mode 100644
index 0000000..6025507
--- /dev/null
+++ b/arch/x86/include/asm/acpi/debug.asl
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/debug.asl
+ */
+
+/* POST register region */
+OperationRegion(X80, SystemIO, 0x80, 1)
+Field(X80, ByteAcc, NoLock, Preserve)
+{
+	P80, 8
+}
+
+/* Legacy serial port register region */
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+Field(CREG, ByteAcc, NoLock, Preserve)
+{
+	CDAT, 8,
+	CDLM, 8,
+	    , 8,
+	CLCR, 8,
+	CMCR, 8,
+	CLSR, 8
+}
+
+/* DINI - Initialize the serial port to 115200 8-N-1 */
+Method(DINI)
+{
+	Store(0x83, CLCR)
+	Store(0x01, CDAT)	/* 115200 baud (low) */
+	Store(0x00, CDLM)	/* 115200 baud (high) */
+	Store(0x03, CLCR)	/* word=8 stop=1 parity=none */
+	Store(0x03, CMCR)	/* DTR=1 RTS=1 out1/2=Off loop=Off */
+	Store(0x00, CDLM)	/* turn off interrupts */
+}
+
+/* THRE - Wait for serial port transmitter holding register to go empty */
+Method(THRE)
+{
+	And(CLSR, 0x20, Local0)
+	While (LEqual(Local0, Zero)) {
+		And(CLSR, 0x20, Local0)
+	}
+}
+
+/* OUTX - Send a single raw character */
+Method(OUTX, 1)
+{
+	THRE()
+	Store(Arg0, CDAT)
+}
+
+/* OUTC - Send a single character, expanding LF into CR/LF */
+Method(OUTC, 1)
+{
+	If (LEqual(Arg0, 0x0a)) {
+		OUTX(0x0d)
+	}
+	OUTX(Arg0)
+}
+
+/* DBGN - Send a single hex nibble */
+Method(DBGN, 1)
+{
+	And(Arg0, 0x0f, Local0)
+	If (LLess(Local0, 10)) {
+		Add(Local0, 0x30, Local0)
+	} Else {
+		Add(Local0, 0x37, Local0)
+	}
+	OUTC(Local0)
+}
+
+/* DBGB - Send a hex byte */
+Method(DBGB, 1)
+{
+	ShiftRight(Arg0, 4, Local0)
+	DBGN(Local0)
+	DBGN(Arg0)
+}
+
+/* DBGW - Send a hex word */
+Method(DBGW, 1)
+{
+	ShiftRight(Arg0, 8, Local0)
+	DBGB(Local0)
+	DBGB(Arg0)
+}
+
+/* DBGD - Send a hex dword */
+Method(DBGD, 1)
+{
+	ShiftRight(Arg0, 16, Local0)
+	DBGW(Local0)
+	DBGW(Arg0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+	CreateByteField(Arg0, Arg1, DBGC)
+	Return (DBGC)
+}
+
+/* DBGO - Send either a string or an integer */
+Method(DBGO, 1, Serialized)
+{
+	If (LEqual(ObjectType(Arg0), 1)) {
+		If (LGreater(Arg0, 0xffff)) {
+			DBGD(Arg0)
+		} Else {
+			If (LGreater(Arg0, 0xff)) {
+				DBGW(Arg0)
+			} Else {
+				DBGB(Arg0)
+			}
+		}
+	} Else {
+		Name(BDBG, Buffer(80) {})
+		Store(Arg0, BDBG)
+		Store(0, Local1)
+		While (One) {
+			Store(GETC(BDBG, Local1), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (Zero)
+			}
+			OUTC(Local0)
+			Increment(Local1)
+		}
+	}
+
+	Return (Zero)
+}
diff --git a/arch/x86/include/asm/acpi/global_nvs.h b/arch/x86/include/asm/acpi/global_nvs.h
new file mode 100644
index 0000000..d56d35c
--- /dev/null
+++ b/arch/x86/include/asm/acpi/global_nvs.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _ACPI_GNVS_H_
+#define _ACPI_GNVS_H_
+
+/*
+ * This file provides two ACPI global NVS macros: ACPI_GNVS_ADDR and
+ * ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file
+ * to declare the GNVS OperationRegion, as well as write_acpi_tables()
+ * for the GNVS address runtime fix up.
+ */
+#define ACPI_GNVS_ADDR	0xdeadbeef
+#define ACPI_GNVS_SIZE	0x100
+
+#endif /* _ACPI_GNVS_H_ */
diff --git a/arch/x86/include/asm/acpi/globutil.asl b/arch/x86/include/asm/acpi/globutil.asl
new file mode 100644
index 0000000..5d50ef3
--- /dev/null
+++ b/arch/x86/include/asm/acpi/globutil.asl
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/globutil.asl
+ */
+
+Method(MIN, 2)
+{
+	If (LLess(Arg0, Arg1)) {
+		Return (Arg0)
+	} Else {
+		Return (Arg1)
+	}
+}
+
+Method(SLEN, 1)
+{
+	Store(Arg0, Local0)
+	Return (Sizeof(Local0))
+}
+
+Method(S2BF, 1, Serialized)
+{
+	Add(SLEN(Arg0), One, Local0)
+	Name(BUFF, Buffer(Local0) {})
+	Store(Arg0, BUFF)
+	Return (BUFF)
+}
+
+/*
+ * SCMP - Strong string compare
+ *
+ * Checks both length and content
+ */
+Method(SCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	Store(Zero, Local4)
+	Store(SLEN(Arg0), Local5)
+	Store(SLEN(Arg1), Local6)
+	Store(MIN(Local5, Local6), Local7)
+
+	While (LLess(Local4, Local7)) {
+		Store(Derefof(Index(Local0, Local4)), Local2)
+		Store(Derefof(Index(Local1, Local4)), Local3)
+		If (LGreater(Local2, Local3)) {
+			Return (One)
+		} Else {
+			If (LLess(Local2, Local3)) {
+				Return (Ones)
+			}
+		}
+		Increment(Local4)
+	}
+
+	If (LLess(Local4, Local5)) {
+		Return (One)
+	} Else {
+		If (LLess(Local4, Local6)) {
+			Return (Ones)
+		} Else {
+			Return (Zero)
+		}
+	}
+}
+
+/*
+ * WCMP - Weak string compare
+ *
+ * Checks to find Arg1 at beginning of Arg0.
+ * Fails if length(Arg0) < length(Arg1).
+ * Returns 0 on fail, 1 on pass.
+ */
+Method(WCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	If (LLess(SLEN(Arg0), SLEN(Arg1))) {
+		Return (Zero)
+	}
+	Store(Zero, Local2)
+	Store(SLEN(Arg1), Local3)
+
+	While (LLess(Local2, Local3)) {
+		If (LNotEqual(Derefof(Index(Local0, Local2)),
+			Derefof(Index(Local1, Local2)))) {
+			Return (Zero)
+		}
+		Increment(Local2)
+	}
+
+	Return (One)
+}
+
+/*
+ * I2BM - Returns Bit Map
+ *
+ * Arg0 = IRQ Number (0-15)
+ */
+Method(I2BM, 1)
+{
+	Store(0, Local0)
+	If (LNotEqual(Arg0, 0)) {
+		Store(1, Local1)
+		ShiftLeft(Local1, Arg0, Local0)
+	}
+
+	Return (Local0)
+}
diff --git a/arch/x86/include/asm/acpi/irq_helper.h b/arch/x86/include/asm/acpi/irq_helper.h
new file mode 100644
index 0000000..6e404f4
--- /dev/null
+++ b/arch/x86/include/asm/acpi/irq_helper.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
+ */
+
+/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+/*
+ * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
+ * routing for the platform being compiled.
+ *
+ * This method uses #defines in irqroute.h along with the macros contained
+ * in this file to generate an IRQ routing for each PCI device in the system.
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef PCI_DEV_PIRQ_ROUTE
+#undef ACPI_DEV_IRQ
+#undef PCIE_BRIDGE_DEV
+#undef RP_IRQ_ROUTES
+#undef ROOTPORT_METHODS
+#undef ROOTPORT_IRQ_ROUTES
+#undef RP_METHOD
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## P, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+/* define as blank so ROOTPORT_METHODS only gets inserted once */
+#define ROOTPORT_METHODS(prefix_, dev_)
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## A, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+#define ROOTPORT_METHODS(prefix_, dev_) \
+	RP_METHOD(prefix_, dev_, 0) \
+	RP_METHOD(prefix_, dev_, 1) \
+	RP_METHOD(prefix_, dev_, 2) \
+	RP_METHOD(prefix_, dev_, 3) \
+	RP_METHOD(prefix_, dev_, 4) \
+	RP_METHOD(prefix_, dev_, 5) \
+	RP_METHOD(prefix_, dev_, 6) \
+	RP_METHOD(prefix_, dev_, 7)
+
+#endif /* defined(PIC_MODE) */
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+	ACPI_DEV_IRQ(dev_, 0, a_), \
+	ACPI_DEV_IRQ(dev_, 1, b_), \
+	ACPI_DEV_IRQ(dev_, 2, c_), \
+	ACPI_DEV_IRQ(dev_, 3, d_)
+
+#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
+	ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	ROOTPORT_METHODS(prefix_, dev_)
+
+#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
+	RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
+
+#define RP_METHOD(prefix_, dev_, func_)\
+Device (prefix_ ## 0 ## func_) \
+{ \
+	Name(_ADR, dev_ ## 000 ## func_) \
+	Name(_PRW, Package() { 0, 0 }) \
+	Method(_PRT) { \
+		If (PICM) { \
+			Return (prefix_ ## func_ ## A) \
+		} Else { \
+			Return (prefix_ ## func_ ## P) \
+		} \
+	} \
+}
+
+/* SoC specific PIRQ route configuration */
+#include <asm/arch/acpi/irqroute.h>
diff --git a/arch/x86/include/asm/acpi/irqlinks.asl b/arch/x86/include/asm/acpi/irqlinks.asl
new file mode 100644
index 0000000..9fc83a5
--- /dev/null
+++ b/arch/x86/include/asm/acpi/irqlinks.asl
@@ -0,0 +1,485 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
+ */
+
+/*
+ * Intel chipset PIRQ routing control ASL description
+ *
+ * The programming interface is common to most Intel chipsets. But the PRTx
+ * registers may be mapped to different blocks. Some chipsets map them to LPC
+ * device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while
+ * some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy
+ * Block (ILB) memory space.
+ *
+ * This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines
+ * PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be
+ * defined somewhere else in the platform's ASL files.
+ */
+
+Device (LNKA)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 1)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTA)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLA, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLA, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTA */
+		ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+		Return (RTLA)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTA)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTA, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKB)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 2)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTB)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLB, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLB, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTB */
+		ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+		Return (RTLB)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTB)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTB, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKC)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 3)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTC)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLC, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLC, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTC */
+		ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+		Return (RTLC)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTC)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTC, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKD)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 4)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTD)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLD, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLD, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTD */
+		ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+		Return (RTLD)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTD)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTD, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKE)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 5)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTE)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLE, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLE, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTE */
+		ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+		Return (RTLE)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTE)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTE, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKF)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 6)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTF)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLF, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLF, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTF */
+		ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+		Return (RTLF)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTF)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTF, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKG)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 7)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTG)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLG, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLG, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTG */
+		ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+		Return (RTLG)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTG)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTG, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKH)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 8)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTH)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLH, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLH, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTH */
+		ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+		Return (RTLH)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTH)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTH, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/acpi/irqroute.asl b/arch/x86/include/asm/acpi/irqroute.asl
new file mode 100644
index 0000000..0ed7efd
--- /dev/null
+++ b/arch/x86/include/asm/acpi/irqroute.asl
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
+ */
+
+Name(\PICM, 0)
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local APIC/IOAPIC configuration.
+ */
+Method(\_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice */
+	Store(Arg0, PICM)
+}
+
+/* PCI interrupt routing */
+Method(_PRT) {
+	If (PICM) {
+		Return (Package() {
+			#undef PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	} Else {
+		Return (Package() {
+			#define PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	}
+
+}
+
+/* PCIe downstream ports interrupt routing */
+PCIE_BRIDGE_IRQ_ROUTES
+#undef PIC_MODE
+#include "irq_helper.h"
+PCIE_BRIDGE_IRQ_ROUTES
diff --git a/arch/x86/include/asm/acpi/sleepstates.asl b/arch/x86/include/asm/acpi/sleepstates.asl
new file mode 100644
index 0000000..32e16a2
--- /dev/null
+++ b/arch/x86/include/asm/acpi/sleepstates.asl
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+#ifdef CONFIG_HAVE_ACPI_RESUME
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+#endif
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/acpi/statdef.asl b/arch/x86/include/asm/acpi/statdef.asl
new file mode 100644
index 0000000..6697bc4
--- /dev/null
+++ b/arch/x86/include/asm/acpi/statdef.asl
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/statdef.asl
+ */
+
+/* Status and notification definitions */
+
+#define STA_MISSING		0x00
+#define STA_PRESENT		0x01
+#define STA_ENABLED		0x03
+#define STA_DISABLED		0x09
+#define STA_INVISIBLE		0x0b
+#define STA_UNAVAILABLE		0x0d
+#define STA_VISIBLE		0x0f
+
+/* SMBus status codes */
+#define SMB_OK			0x00
+#define SMB_UNKNOWN_FAIL	0x07
+#define SMB_DEV_ADDR_NAK	0x10
+#define SMB_DEVICE_ERROR	0x11
+#define SMB_DEV_CMD_DENIED	0x12
+#define SMB_UNKNOWN_ERR		0x13
+#define SMB_DEV_ACC_DENIED	0x17
+#define SMB_TIMEOUT		0x18
+#define SMB_HST_UNSUPP_PROTOCOL	0x19
+#define SMB_BUSY		0x1a
+#define SMB_PKT_CHK_ERROR	0x1f
+
+/* Device Object Notification Values */
+#define NOTIFY_BUS_CHECK	0x00
+#define NOTIFY_DEVICE_CHECK	0x01
+#define NOTIFY_DEVICE_WAKE	0x02
+#define NOTIFY_EJECT_REQUEST	0x03
+#define NOTIFY_DEVICE_CHECK_JR	0x04
+#define NOTIFY_FREQUENCY_ERROR	0x05
+#define NOTIFY_BUS_MODE		0x06
+#define NOTIFY_POWER_FAULT	0x07
+#define NOTIFY_CAPABILITIES	0x08
+#define NOTIFY_PLD_CHECK	0x09
+#define NOTIFY_SLIT_UPDATE	0x0b
+#define NOTIFY_SRA_UPDATE	0x0d
+
+/* Battery Device Notification Values */
+#define NOTIFY_BAT_STATUSCHG	0x80
+#define NOTIFY_BAT_INFOCHG	0x81
+#define NOTIFY_BAT_MAINTDATA	0x82
+
+/* Power Source Object Notification Values */
+#define NOTIFY_PWR_STATUSCHG	0x80
+#define NOTIFY_PWR_INFOCHG	0x81
+
+/* Thermal Zone Object Notification Values */
+#define NOTIFY_TZ_STATUSCHG	0x80
+#define NOTIFY_TZ_TRIPPTCHG	0x81
+#define NOTIFY_TZ_DEVLISTCHG	0x82
+#define NOTIFY_TZ_RELTBLCHG	0x83
+
+/* Power Button Notification Values */
+#define NOTIFY_POWER_BUTTON	0x80
+
+/* Sleep Button Notification Values */
+#define NOTIFY_SLEEP_BUTTON	0x80
+
+/* Lid Notification Values */
+#define NOTIFY_LID_STATUSCHG	0x80
+
+/* Processor Device Notification Values */
+#define NOTIFY_CPU_PPCCHG	0x80
+#define NOTIFY_CPU_CSTATECHG	0x81
+#define NOTIFY_CPU_THROTLCHG	0x82
+
+/* User Presence Device Notification Values */
+#define NOTIFY_USR_PRESNCECHG	0x80
+
+/* Ambient Light Sensor Notification Values */
+#define NOTIFY_ALS_ILLUMCHG	0x80
+#define NOTIFY_ALS_COLORTMPCHG	0x81
+#define NOTIFY_ALS_RESPCHG	0x82
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
new file mode 100644
index 0000000..7588913
--- /dev/null
+++ b/arch/x86/include/asm/acpi_table.h
@@ -0,0 +1,417 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on acpi.c from coreboot
+ *
+ * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __ASM_ACPI_TABLE_H__
+#define __ASM_ACPI_TABLE_H__
+
+#define RSDP_SIG		"RSD PTR "	/* RSDP pointer signature */
+#define OEM_ID			"U-BOOT"	/* U-Boot */
+#define OEM_TABLE_ID		"U-BOOTBL"	/* U-Boot Table */
+#define ASLC_ID			"INTL"		/* Intel ASL Compiler */
+
+#define ACPI_RSDP_REV_ACPI_1_0	0
+#define ACPI_RSDP_REV_ACPI_2_0	2
+
+/*
+ * RSDP (Root System Description Pointer)
+ * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
+ */
+struct acpi_rsdp {
+	char signature[8];	/* RSDP signature */
+	u8 checksum;		/* Checksum of the first 20 bytes */
+	char oem_id[6];		/* OEM ID */
+	u8 revision;		/* 0 for ACPI 1.0, others 2 */
+	u32 rsdt_address;	/* Physical address of RSDT (32 bits) */
+	u32 length;		/* Total RSDP length (incl. extended part) */
+	u64 xsdt_address;	/* Physical address of XSDT (64 bits) */
+	u8 ext_checksum;	/* Checksum of the whole table */
+	u8 reserved[3];
+};
+
+/* Generic ACPI header, provided by (almost) all tables */
+struct __packed acpi_table_header {
+	char signature[4];	/* ACPI signature (4 ASCII characters) */
+	u32 length;		/* Table length in bytes (incl. header) */
+	u8 revision;		/* Table version (not ACPI version!) */
+	volatile u8 checksum;	/* To make sum of entire table == 0 */
+	char oem_id[6];		/* OEM identification */
+	char oem_table_id[8];	/* OEM table identification */
+	u32 oem_revision;	/* OEM revision number */
+	char aslc_id[4];	/* ASL compiler vendor ID */
+	u32 aslc_revision;	/* ASL compiler revision number */
+};
+
+/* A maximum number of 32 ACPI tables ought to be enough for now */
+#define MAX_ACPI_TABLES		32
+
+/* RSDT (Root System Description Table) */
+struct acpi_rsdt {
+	struct acpi_table_header header;
+	u32 entry[MAX_ACPI_TABLES];
+};
+
+/* XSDT (Extended System Description Table) */
+struct acpi_xsdt {
+	struct acpi_table_header header;
+	u64 entry[MAX_ACPI_TABLES];
+};
+
+/* FADT Preferred Power Management Profile */
+enum acpi_pm_profile {
+	ACPI_PM_UNSPECIFIED = 0,
+	ACPI_PM_DESKTOP,
+	ACPI_PM_MOBILE,
+	ACPI_PM_WORKSTATION,
+	ACPI_PM_ENTERPRISE_SERVER,
+	ACPI_PM_SOHO_SERVER,
+	ACPI_PM_APPLIANCE_PC,
+	ACPI_PM_PERFORMANCE_SERVER,
+	ACPI_PM_TABLET
+};
+
+/* FADT flags for p_lvl2_lat and p_lvl3_lat */
+#define ACPI_FADT_C2_NOT_SUPPORTED	101
+#define ACPI_FADT_C3_NOT_SUPPORTED	1001
+
+/* FADT Boot Architecture Flags */
+#define ACPI_FADT_LEGACY_FREE		0x00
+#define ACPI_FADT_LEGACY_DEVICES	(1 << 0)
+#define ACPI_FADT_8042			(1 << 1)
+#define ACPI_FADT_VGA_NOT_PRESENT	(1 << 2)
+#define ACPI_FADT_MSI_NOT_SUPPORTED	(1 << 3)
+#define ACPI_FADT_NO_PCIE_ASPM_CONTROL	(1 << 4)
+
+/* FADT Feature Flags */
+#define ACPI_FADT_WBINVD		(1 << 0)
+#define ACPI_FADT_WBINVD_FLUSH		(1 << 1)
+#define ACPI_FADT_C1_SUPPORTED		(1 << 2)
+#define ACPI_FADT_C2_MP_SUPPORTED	(1 << 3)
+#define ACPI_FADT_POWER_BUTTON		(1 << 4)
+#define ACPI_FADT_SLEEP_BUTTON		(1 << 5)
+#define ACPI_FADT_FIXED_RTC		(1 << 6)
+#define ACPI_FADT_S4_RTC_WAKE		(1 << 7)
+#define ACPI_FADT_32BIT_TIMER		(1 << 8)
+#define ACPI_FADT_DOCKING_SUPPORTED	(1 << 9)
+#define ACPI_FADT_RESET_REGISTER	(1 << 10)
+#define ACPI_FADT_SEALED_CASE		(1 << 11)
+#define ACPI_FADT_HEADLESS		(1 << 12)
+#define ACPI_FADT_SLEEP_TYPE		(1 << 13)
+#define ACPI_FADT_PCI_EXPRESS_WAKE	(1 << 14)
+#define ACPI_FADT_PLATFORM_CLOCK	(1 << 15)
+#define ACPI_FADT_S4_RTC_VALID		(1 << 16)
+#define ACPI_FADT_REMOTE_POWER_ON	(1 << 17)
+#define ACPI_FADT_APIC_CLUSTER		(1 << 18)
+#define ACPI_FADT_APIC_PHYSICAL		(1 << 19)
+#define ACPI_FADT_HW_REDUCED_ACPI	(1 << 20)
+#define ACPI_FADT_LOW_PWR_IDLE_S0	(1 << 21)
+
+enum acpi_address_space_type {
+	ACPI_ADDRESS_SPACE_MEMORY = 0,	/* System memory */
+	ACPI_ADDRESS_SPACE_IO,		/* System I/O */
+	ACPI_ADDRESS_SPACE_PCI,		/* PCI config space */
+	ACPI_ADDRESS_SPACE_EC,		/* Embedded controller */
+	ACPI_ADDRESS_SPACE_SMBUS,	/* SMBus */
+	ACPI_ADDRESS_SPACE_PCC = 0x0a,	/* Platform Comm. Channel */
+	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
+};
+
+enum acpi_address_space_size {
+	ACPI_ACCESS_SIZE_UNDEFINED = 0,
+	ACPI_ACCESS_SIZE_BYTE_ACCESS,
+	ACPI_ACCESS_SIZE_WORD_ACCESS,
+	ACPI_ACCESS_SIZE_DWORD_ACCESS,
+	ACPI_ACCESS_SIZE_QWORD_ACCESS
+};
+
+struct acpi_gen_regaddr {
+	u8 space_id;	/* Address space ID */
+	u8 bit_width;	/* Register size in bits */
+	u8 bit_offset;	/* Register bit offset */
+	u8 access_size;	/* Access size */
+	u32 addrl;	/* Register address, low 32 bits */
+	u32 addrh;	/* Register address, high 32 bits */
+};
+
+/* FADT (Fixed ACPI Description Table) */
+struct __packed acpi_fadt {
+	struct acpi_table_header header;
+	u32 firmware_ctrl;
+	u32 dsdt;
+	u8 res1;
+	u8 preferred_pm_profile;
+	u16 sci_int;
+	u32 smi_cmd;
+	u8 acpi_enable;
+	u8 acpi_disable;
+	u8 s4bios_req;
+	u8 pstate_cnt;
+	u32 pm1a_evt_blk;
+	u32 pm1b_evt_blk;
+	u32 pm1a_cnt_blk;
+	u32 pm1b_cnt_blk;
+	u32 pm2_cnt_blk;
+	u32 pm_tmr_blk;
+	u32 gpe0_blk;
+	u32 gpe1_blk;
+	u8 pm1_evt_len;
+	u8 pm1_cnt_len;
+	u8 pm2_cnt_len;
+	u8 pm_tmr_len;
+	u8 gpe0_blk_len;
+	u8 gpe1_blk_len;
+	u8 gpe1_base;
+	u8 cst_cnt;
+	u16 p_lvl2_lat;
+	u16 p_lvl3_lat;
+	u16 flush_size;
+	u16 flush_stride;
+	u8 duty_offset;
+	u8 duty_width;
+	u8 day_alrm;
+	u8 mon_alrm;
+	u8 century;
+	u16 iapc_boot_arch;
+	u8 res2;
+	u32 flags;
+	struct acpi_gen_regaddr reset_reg;
+	u8 reset_value;
+	u16 arm_boot_arch;
+	u8 minor_revision;
+	u32 x_firmware_ctl_l;
+	u32 x_firmware_ctl_h;
+	u32 x_dsdt_l;
+	u32 x_dsdt_h;
+	struct acpi_gen_regaddr x_pm1a_evt_blk;
+	struct acpi_gen_regaddr x_pm1b_evt_blk;
+	struct acpi_gen_regaddr x_pm1a_cnt_blk;
+	struct acpi_gen_regaddr x_pm1b_cnt_blk;
+	struct acpi_gen_regaddr x_pm2_cnt_blk;
+	struct acpi_gen_regaddr x_pm_tmr_blk;
+	struct acpi_gen_regaddr x_gpe0_blk;
+	struct acpi_gen_regaddr x_gpe1_blk;
+};
+
+/* FACS flags */
+#define ACPI_FACS_S4BIOS_F	(1 << 0)
+#define ACPI_FACS_64BIT_WAKE_F	(1 << 1)
+
+/* FACS (Firmware ACPI Control Structure) */
+struct acpi_facs {
+	char signature[4];		/* "FACS" */
+	u32 length;			/* Length in bytes (>= 64) */
+	u32 hardware_signature;		/* Hardware signature */
+	u32 firmware_waking_vector;	/* Firmware waking vector */
+	u32 global_lock;		/* Global lock */
+	u32 flags;			/* FACS flags */
+	u32 x_firmware_waking_vector_l;	/* X FW waking vector, low */
+	u32 x_firmware_waking_vector_h;	/* X FW waking vector, high */
+	u8 version;			/* Version 2 */
+	u8 res1[3];
+	u32 ospm_flags;			/* OSPM enabled flags */
+	u8 res2[24];
+};
+
+/* MADT flags */
+#define ACPI_MADT_PCAT_COMPAT	(1 << 0)
+
+/* MADT (Multiple APIC Description Table) */
+struct acpi_madt {
+	struct acpi_table_header header;
+	u32 lapic_addr;			/* Local APIC address */
+	u32 flags;			/* Multiple APIC flags */
+};
+
+/* MADT: APIC Structure Type*/
+enum acpi_apic_types {
+	ACPI_APIC_LAPIC	= 0,		/* Processor local APIC */
+	ACPI_APIC_IOAPIC,		/* I/O APIC */
+	ACPI_APIC_IRQ_SRC_OVERRIDE,	/* Interrupt source override */
+	ACPI_APIC_NMI_SRC,		/* NMI source */
+	ACPI_APIC_LAPIC_NMI,		/* Local APIC NMI */
+	ACPI_APIC_LAPIC_ADDR_OVERRIDE,	/* Local APIC address override */
+	ACPI_APIC_IOSAPIC,		/* I/O SAPIC */
+	ACPI_APIC_LSAPIC,		/* Local SAPIC */
+	ACPI_APIC_PLATFORM_IRQ_SRC,	/* Platform interrupt sources */
+	ACPI_APIC_LX2APIC,		/* Processor local x2APIC */
+	ACPI_APIC_LX2APIC_NMI,		/* Local x2APIC NMI */
+};
+
+/* MADT: Processor Local APIC Structure */
+
+#define LOCAL_APIC_FLAG_ENABLED	(1 << 0)
+
+struct acpi_madt_lapic {
+	u8 type;		/* Type (0) */
+	u8 length;		/* Length in bytes (8) */
+	u8 processor_id;	/* ACPI processor ID */
+	u8 apic_id;		/* Local APIC ID */
+	u32 flags;		/* Local APIC flags */
+};
+
+/* MADT: I/O APIC Structure */
+struct acpi_madt_ioapic {
+	u8 type;		/* Type (1) */
+	u8 length;		/* Length in bytes (12) */
+	u8 ioapic_id;		/* I/O APIC ID */
+	u8 reserved;
+	u32 ioapic_addr;	/* I/O APIC address */
+	u32 gsi_base;		/* Global system interrupt base */
+};
+
+/* MADT: Interrupt Source Override Structure */
+struct __packed acpi_madt_irqoverride {
+	u8 type;		/* Type (2) */
+	u8 length;		/* Length in bytes (10) */
+	u8 bus;			/* ISA (0) */
+	u8 source;		/* Bus-relative int. source (IRQ) */
+	u32 gsirq;		/* Global system interrupt */
+	u16 flags;		/* MPS INTI flags */
+};
+
+/* MADT: Local APIC NMI Structure */
+struct __packed acpi_madt_lapic_nmi {
+	u8 type;		/* Type (4) */
+	u8 length;		/* Length in bytes (6) */
+	u8 processor_id;	/* ACPI processor ID */
+	u16 flags;		/* MPS INTI flags */
+	u8 lint;		/* Local APIC LINT# */
+};
+
+/* MCFG (PCI Express MMIO config space BAR description table) */
+struct acpi_mcfg {
+	struct acpi_table_header header;
+	u8 reserved[8];
+};
+
+struct acpi_mcfg_mmconfig {
+	u32 base_address_l;
+	u32 base_address_h;
+	u16 pci_segment_group_number;
+	u8 start_bus_number;
+	u8 end_bus_number;
+	u8 reserved[4];
+};
+
+/* PM1_CNT bit defines */
+#define PM1_CNT_SCI_EN		(1 << 0)
+
+/* ACPI global NVS structure */
+struct acpi_global_nvs;
+
+/* CSRT (Core System Resource Table) */
+struct acpi_csrt {
+	struct acpi_table_header header;
+};
+
+struct acpi_csrt_group {
+	u32 length;
+	u32 vendor_id;
+	u32 subvendor_id;
+	u16 device_id;
+	u16 subdevice_id;
+	u16 revision;
+	u16 reserved;
+	u32 shared_info_length;
+};
+
+struct acpi_csrt_shared_info {
+	u16 major_version;
+	u16 minor_version;
+	u32 mmio_base_low;
+	u32 mmio_base_high;
+	u32 gsi_interrupt;
+	u8 interrupt_polarity;
+	u8 interrupt_mode;
+	u8 num_channels;
+	u8 dma_address_width;
+	u16 base_request_line;
+	u16 num_handshake_signals;
+	u32 max_block_size;
+};
+
+/* DBG2 definitions are partially used for SPCR interface_type */
+
+/* Types for port_type field */
+
+#define ACPI_DBG2_SERIAL_PORT		0x8000
+#define ACPI_DBG2_1394_PORT		0x8001
+#define ACPI_DBG2_USB_PORT		0x8002
+#define ACPI_DBG2_NET_PORT		0x8003
+
+/* Subtypes for port_subtype field */
+
+#define ACPI_DBG2_16550_COMPATIBLE	0x0000
+#define ACPI_DBG2_16550_SUBSET		0x0001
+#define ACPI_DBG2_ARM_PL011		0x0003
+#define ACPI_DBG2_ARM_SBSA_32BIT	0x000D
+#define ACPI_DBG2_ARM_SBSA_GENERIC	0x000E
+#define ACPI_DBG2_ARM_DCC		0x000F
+#define ACPI_DBG2_BCM2835		0x0010
+
+#define ACPI_DBG2_1394_STANDARD		0x0000
+
+#define ACPI_DBG2_USB_XHCI		0x0000
+#define ACPI_DBG2_USB_EHCI		0x0001
+
+#define ACPI_DBG2_UNKNOWN		0x00FF
+
+/* SPCR (Serial Port Console Redirection table) */
+struct __packed acpi_spcr {
+	struct acpi_table_header header;
+	u8 interface_type;
+	u8 reserved[3];
+	struct acpi_gen_regaddr serial_port;
+	u8 interrupt_type;
+	u8 pc_interrupt;
+	u32 interrupt;		/* Global system interrupt */
+	u8 baud_rate;
+	u8 parity;
+	u8 stop_bits;
+	u8 flow_control;
+	u8 terminal_type;
+	u8 reserved1;
+	u16 pci_device_id;	/* Must be 0xffff if not PCI device */
+	u16 pci_vendor_id;	/* Must be 0xffff if not PCI device */
+	u8 pci_bus;
+	u8 pci_device;
+	u8 pci_function;
+	u32 pci_flags;
+	u8 pci_segment;
+	u32 reserved2;
+};
+
+/* These can be used by the target port */
+
+void acpi_fill_header(struct acpi_table_header *header, char *signature);
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt);
+int acpi_create_madt_lapics(u32 current);
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+			    u32 addr, u32 gsi_base);
+int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
+				 u8 bus, u8 source, u32 gsirq, u16 flags);
+int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
+			       u8 cpu, u16 flags, u8 lint);
+u32 acpi_fill_madt(u32 current);
+int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base,
+			      u16 seg_nr, u8 start, u8 end);
+u32 acpi_fill_mcfg(u32 current);
+u32 acpi_fill_csrt(u32 current);
+void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
+ulong write_acpi_tables(ulong start);
+
+/**
+ * acpi_get_rsdp_addr() - get ACPI RSDP table address
+ *
+ * This routine returns the ACPI RSDP table address in the system memory.
+ *
+ * @return:	ACPI RSDP table address
+ */
+ulong acpi_get_rsdp_addr(void);
+
+#endif /* __ASM_ACPI_TABLE_H__ */
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl
new file mode 100644
index 0000000..aaf87f4
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <asm/acpi/global_nvs.h>
+
+OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
+Field(GNVS, ByteAcc, NoLock, Preserve)
+{
+	PCNT, 8,	/* processor count */
+	IURE, 8,	/* internal UART enabled */
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
new file mode 100644
index 0000000..abe3756
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
+ */
+
+/* SouthCluster GPIO */
+Device (GPSC)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 1)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_SC_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
+
+/* NorthCluster GPIO */
+Device (GPNC)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 2)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_NC_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
+
+/* SUS GPIO */
+Device (GPSS)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 3)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_SUS_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
new file mode 100644
index 0000000..57921f2
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(EMMC_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SDIO_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SD_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(LPE_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(MMC45_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO1_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(HDA_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(PCIE_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(EHCI_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO2_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,	A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+	PCIE_BRIDGE_DEV(RP, PCIE_DEV,	A, B, C, D)
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
new file mode 100644
index 0000000..08b2f53
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -0,0 +1,198 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Scope (\)
+{
+	/* Intel Legacy Block */
+	OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+	Field(ILBS, AnyAcc, NoLock, Preserve) {
+		Offset (0x8),
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+		Offset (0x88),
+		    , 3,
+		UI3E, 1,
+		UI4E, 1
+	}
+}
+
+Device (LPCB)
+{
+	Name(_ADR, 0x001f0000)
+
+	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+	Field(LPC0, AnyAcc, NoLock, Preserve) {
+		Offset(0x08),
+		SRID, 8,
+		Offset(0x80),
+		C1EN, 1,
+		Offset(0x84)
+	}
+
+	#include <asm/acpi/irqlinks.asl>
+
+	/* Firmware Hub */
+	Device (FWH)
+	{
+		Name(_HID, EISAID("INT0800"))
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	/* 8259 Interrupt Controller */
+	Device (PIC)
+	{
+		Name(_HID, EISAID("PNP0000"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	/* 8254 timer */
+	Device (TIMR)
+	{
+		Name(_HID, EISAID("PNP0100"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() { 0 }
+		})
+	}
+
+	/* HPET */
+	Device (HPET)
+	{
+		Name(_HID, EISAID("PNP0103"))
+		Name(_CID, 0x010CD041)
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+		})
+
+		Method(_STA)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+
+	/* Internal UART */
+	Device (IURT)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+
+		Method(_STA, 0, Serialized)
+		{
+			If (LEqual(IURE, 1)) {
+				Store(1, UI3E)
+				Store(1, UI4E)
+				Store(1, C1EN)
+				Return (STA_VISIBLE)
+			} Else {
+				Return (STA_MISSING)
+			}
+
+		}
+
+		Method(_DIS, 0, Serialized)
+		{
+			Store(0, UI3E)
+			Store(0, UI4E)
+			Store(0, C1EN)
+		}
+
+		Method(_CRS, 0, Serialized)
+		{
+			Name(BUF0, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 3 }
+			})
+
+			Name(BUF1, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 4 }
+			})
+
+			If (LLessEqual(SRID, 0x04)) {
+				Return (BUF0)
+			} Else {
+				Return (BUF1)
+			}
+		}
+	}
+
+	/* Real Time Clock */
+	Device (RTC)
+	{
+		Name(_HID, EISAID("PNP0B00"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x70, 0x70, 1, 8)
+			/*
+			 * Disable as Windows doesn't like it, and systems
+			 * don't seem to use it
+			 */
+			/* IRQNoFlags() { 8 } */
+		})
+	}
+
+	/* LPC device: Resource consumption */
+	Device (LDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 2)
+
+		Name(RBUF, ResourceTemplate()
+		{
+			IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+			IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+			IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+		})
+
+		Method(_CRS, 0, NotSerialized)
+		{
+			Return (RBUF)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
new file mode 100644
index 0000000..5186fe0
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+	Return (Package() {0, 0})
+}
+
+/* ACPI global NVS */
+#include "global_nvs.asl"
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+	#include "southcluster.asl"
+
+	/* ACPI devices */
+	#include "gpio.asl"
+}
+
+/* Chipset specific sleep states */
+#include <asm/acpi/sleepstates.asl>
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
new file mode 100644
index 0000000..2a1c31c
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
+ */
+
+Device (PCI0)
+{
+	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
+	Name(_CID, EISAID("PNP0A03"))	/* PCI */
+
+	Name(_ADR, 0)
+	Name(_BBN, 0)
+
+	Name(MCRS, ResourceTemplate()
+	{
+		/* Bus Numbers */
+		WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+		/* IO Region 0 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+		/* PCI Config Space */
+		IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		/* IO Region 1 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+		/* VGA memory (0xa0000-0xbffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000, , , ASEG)
+
+		/* OPROM reserved (0xc0000-0xc3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000, , , OPR0)
+
+		/* OPROM reserved (0xc4000-0xc7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000, , , OPR1)
+
+		/* OPROM reserved (0xc8000-0xcbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000, , , OPR2)
+
+		/* OPROM reserved (0xcc000-0xcffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000, , , OPR3)
+
+		/* OPROM reserved (0xd0000-0xd3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000, , , OPR4)
+
+		/* OPROM reserved (0xd4000-0xd7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000, , , OPR5)
+
+		/* OPROM reserved (0xd8000-0xdbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000, , , OPR6)
+
+		/* OPROM reserved (0xdc000-0xdffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000, , , OPR7)
+
+		/* BIOS Extension (0xe0000-0xe3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000, , , ESG0)
+
+		/* BIOS Extension (0xe4000-0xe7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000, , , ESG1)
+
+		/* BIOS Extension (0xe8000-0xebfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000, , , ESG2)
+
+		/* BIOS Extension (0xec000-0xeffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000, , , ESG3)
+
+		/* System BIOS (0xf0000-0xfffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000, , , FSEG)
+
+		/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , PMEM)
+
+		/* High PCI Memory Region */
+		QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , UMEM)
+	})
+
+	Method(_CRS, 0, Serialized)
+	{
+		/* Update PCI resource area */
+		CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+		CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+		CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+		/*
+		 * Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
+		 *
+		 * TODO: for generic usage, read TOLM value from register, or
+		 * from global NVS (not implemented by U-Boot yet).
+		 */
+		Store(0x80000000, PMIN)
+		Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+		Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+		/* Update High PCI resource area */
+		CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
+		CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
+		CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
+
+		/* Set base address to 16GB and allocate 48GB for PCI space */
+		Store(0x400000000, UMIN)
+		Store(0xc00000000, ULEN)
+		Add(UMIN, Subtract(ULEN, 1), UMAX)
+
+		Return (MCRS)
+	}
+
+	/* Device Resource Consumption */
+	Device (PDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 1)
+
+		Name(PDRS, ResourceTemplate() {
+			Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+			Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+			Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
+			Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
+			Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
+			Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+			Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+			Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0, Serialized)
+		{
+			Return (PDRS)
+		}
+	}
+
+	Method(_OSC, 4)
+	{
+		/* Check for proper GUID */
+		If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+			/* Let OS control everything */
+			Return (Arg3)
+		} Else {
+			/* Unrecognized UUID */
+			CreateDWordField(Arg3, 0, CDW1)
+			Or(CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+	}
+
+	/* LPC Bridge 0:1f.0 */
+	#include "lpc.asl"
+
+	/* USB EHCI 0:1d.0 */
+	#include "usb.asl"
+
+	/* USB XHCI 0:14.0 */
+	#include "xhci.asl"
+
+	/* IRQ routing for each PCI device */
+	#include <asm/acpi/irqroute.asl>
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/usb.asl b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
new file mode 100644
index 0000000..78a7952
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl
+ */
+
+/* EHCI Controller 0:1d.0 */
+
+Device (EHC1)
+{
+	Name(_ADR, 0x001d0000)
+
+	/* Power Resources for Wake */
+	Name(_PRW, Package() { 13, 4 })
+
+	/* Highest D state in S3 state */
+	Name(_S3D, 2)
+
+	/* Highest D state in S4 state */
+	Name(_S4D, 2)
+
+	Device (HUB7)
+	{
+		Name(_ADR, 0x00000000)
+
+		Device(PRT1) { Name(_ADR, 1) }	/* USB Port 0 */
+		Device(PRT2) { Name(_ADR, 2) }	/* USB Port 1 */
+		Device(PRT3) { Name(_ADR, 3) }	/* USB Port 2 */
+		Device(PRT4) { Name(_ADR, 4) }	/* USB Port 3 */
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
new file mode 100644
index 0000000..13cb429
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl
+ */
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+	Name(_ADR, 0x00140000)
+
+	/* Power Resources for Wake */
+	Name(_PRW, Package() { 13, 3 })
+
+	/* Highest D state in S3 state */
+	Name(_S3D, 3)
+
+	Device (RHUB)
+	{
+		Name(_ADR, 0x00000000)
+
+		Device (PRT1) { Name(_ADR, 1) }	/* USB Port 0 */
+		Device (PRT2) { Name(_ADR, 2) }	/* USB Port 1 */
+		Device (PRT3) { Name(_ADR, 3) }	/* USB Port 2 */
+		Device (PRT4) { Name(_ADR, 4) }	/* USB Port 3 */
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/device.h b/arch/x86/include/asm/arch-baytrail/device.h
new file mode 100644
index 0000000..a3872cf
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/device.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
+ */
+
+#ifndef _DEVICE_H_
+#define _DEVICE_H_
+
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
+
+/* SoC transaction router */
+#define SOC_DEV		0x00
+
+/* Graphics and Display */
+#define GFX_DEV		0x02
+
+/* MIPI */
+#define MIPI_DEV	0x03
+
+/* EMMC Port */
+#define EMMC_DEV	0x10
+
+/* SDIO Port */
+#define SDIO_DEV	0x11
+
+/* SD Port */
+#define SD_DEV		0x12
+
+/* SATA */
+#define SATA_DEV	0x13
+
+/* xHCI */
+#define XHCI_DEV	0x14
+
+/* LPE Audio */
+#define LPE_DEV		0x15
+
+/* OTG */
+#define OTG_DEV		0x16
+
+/* MMC45 Port */
+#define MMC45_DEV	0x17
+
+/* Serial IO 1 */
+#define SIO1_DEV	0x18
+
+/* Trusted Execution Engine */
+#define TXE_DEV		0x1a
+
+/* HD Audio */
+#define HDA_DEV		0x1b
+
+/* PCIe Ports */
+#define PCIE_DEV	0x1c
+
+/* EHCI */
+#define EHCI_DEV	0x1d
+
+/* Serial IO 2 */
+#define SIO2_DEV	0x1e
+
+/* Platform Controller Unit */
+#define PCU_DEV		0x1f
+
+#endif /* _DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
new file mode 100644
index 0000000..cd48705
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+#ifndef __ASSEMBLY__
+struct fsp_config_data {
+	struct fsp_cfg_common	common;
+	struct upd_region	fsp_upd;
+};
+
+struct fspinit_rtbuf {
+	struct common_buf	common;	/* FSP common runtime data structure */
+};
+#endif
+
+/* FSP user configuration settings */
+
+#define MRC_INIT_TSEG_SIZE_1MB		1
+#define MRC_INIT_TSEG_SIZE_2MB		2
+#define MRC_INIT_TSEG_SIZE_4MB		4
+#define MRC_INIT_TSEG_SIZE_8MB		8
+
+#define MRC_INIT_MMIO_SIZE_1024MB	0x400
+#define MRC_INIT_MMIO_SIZE_1536MB	0x600
+#define MRC_INIT_MMIO_SIZE_2048MB	0x800
+
+#define EMMC_BOOT_MODE_DISABLED		0
+#define EMMC_BOOT_MODE_AUTO		1
+#define EMMC_BOOT_MODE_EMMC41		2
+#define EMMC_BOOT_MODE_EMCC45		3
+
+#define SATA_MODE_IDE			0
+#define SATA_MODE_AHCI			1
+
+#define IGD_DVMT50_PRE_ALLOC_32MB	0x01
+#define IGD_DVMT50_PRE_ALLOC_64MB	0x02
+#define IGD_DVMT50_PRE_ALLOC_96MB	0x03
+#define IGD_DVMT50_PRE_ALLOC_128MB	0x04
+#define IGD_DVMT50_PRE_ALLOC_160MB	0x05
+#define IGD_DVMT50_PRE_ALLOC_192MB	0x06
+#define IGD_DVMT50_PRE_ALLOC_224MB	0x07
+#define IGD_DVMT50_PRE_ALLOC_256MB	0x08
+#define IGD_DVMT50_PRE_ALLOC_288MB	0x09
+#define IGD_DVMT50_PRE_ALLOC_320MB	0x0a
+#define IGD_DVMT50_PRE_ALLOC_352MB	0x0b
+#define IGD_DVMT50_PRE_ALLOC_384MB	0x0c
+#define IGD_DVMT50_PRE_ALLOC_416MB	0x0d
+#define IGD_DVMT50_PRE_ALLOC_448MB	0x0e
+#define IGD_DVMT50_PRE_ALLOC_480MB	0x0f
+#define IGD_DVMT50_PRE_ALLOC_512MB	0x10
+
+#define APERTURE_SIZE_128MB		1
+#define APERTURE_SIZE_256MB		2
+#define APERTURE_SIZE_512MB		3
+
+#define GTT_SIZE_1MB			1
+#define GTT_SIZE_2MB			2
+
+#define OS_SELECTION_ANDROID		1
+#define OS_SELECTION_LINUX		4
+
+#define DRAM_SPEED_800MTS		0
+#define DRAM_SPEED_1066MTS		1
+#define DRAM_SPEED_1333MTS		2
+#define DRAM_SPEED_1600MTS		3
+
+#define DRAM_TYPE_DDR3			0
+#define DRAM_TYPE_DDR3L			1
+#define DRAM_TYPE_DDR3ECC		2
+#define DRAM_TYPE_LPDDR2		4
+#define DRAM_TYPE_LPDDR3		5
+#define DRAM_TYPE_DDR4			6
+
+#define DIMM_WIDTH_X8			0
+#define DIMM_WIDTH_X16			1
+#define DIMM_WIDTH_X32			2
+
+#define DIMM_DENSITY_1GBIT		0
+#define DIMM_DENSITY_2GBIT		1
+#define DIMM_DENSITY_4GBIT		2
+#define DIMM_DENSITY_8GBIT		3
+
+#define DIMM_BUS_WIDTH_8BITS		0
+#define DIMM_BUS_WIDTH_16BITS		1
+#define DIMM_BUS_WIDTH_32BITS		2
+#define DIMM_BUS_WIDTH_64BITS		3
+
+#define DIMM_SIDES_1RANKS		0
+#define DIMM_SIDES_2RANKS		1
+
+#define LPE_MODE_DISABLED		0
+#define LPE_MODE_PCI			1
+#define LPE_MODE_ACPI			2
+
+#define LPSS_SIO_MODE_ACPI		0
+#define LPSS_SIO_MODE_PCI		1
+
+#define SCC_MODE_ACPI			0
+#define SCC_MODE_PCI			1
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
new file mode 100644
index 0000000..c6544ea
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015 Google, Inc
+ */
+
+#ifndef __FSP_VPD_H
+#define __FSP_VPD_H
+
+struct memory_down_data {
+	uint8_t enable_memory_down;
+	uint8_t dram_speed;
+	uint8_t dram_type;
+	uint8_t dimm_0_enable;
+	uint8_t dimm_1_enable;
+	uint8_t dimm_width;
+	uint8_t dimm_density;
+	uint8_t dimm_bus_width;
+	uint8_t dimm_sides;			/* Ranks Per dimm_ */
+	uint8_t dimm_tcl;			/* tCL */
+	/* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
+	uint8_t dimm_trpt_rcd;
+	uint8_t dimm_twr;			/* tWR in DRAM clk  */
+	uint8_t dimm_twtr;			/* tWTR in DRAM clk */
+	uint8_t dimm_trrd;			/* tRRD in DRAM clk */
+	uint8_t dimm_trtp;			/* tRTP in DRAM clk */
+	uint8_t dimm_tfaw;			/* tFAW in DRAM clk */
+};
+
+struct __packed upd_region {
+	uint64_t signature;			/* Offset 0x0000 */
+	uint8_t reserved0[24];			/* Offset 0x0008 */
+	uint16_t mrc_init_tseg_size;		/* Offset 0x0020 */
+	uint16_t mrc_init_mmio_size;		/* Offset 0x0022 */
+	uint8_t mrc_init_spd_addr1;		/* Offset 0x0024 */
+	uint8_t mrc_init_spd_addr2;		/* Offset 0x0025 */
+	uint8_t emmc_boot_mode;			/* Offset 0x0026 */
+	uint8_t enable_sdio;			/* Offset 0x0027 */
+	uint8_t enable_sdcard;			/* Offset 0x0028 */
+	uint8_t enable_hsuart0;			/* Offset 0x0029 */
+	uint8_t enable_hsuart1;			/* Offset 0x002a */
+	uint8_t enable_spi;			/* Offset 0x002b */
+	uint8_t reserved1;			/* Offset 0x002c */
+	uint8_t enable_sata;			/* Offset 0x002d */
+	uint8_t sata_mode;			/* Offset 0x002e */
+	uint8_t enable_azalia;			/* Offset 0x002f */
+	struct azalia_config *azalia_cfg_ptr;	/* Offset 0x0030 */
+	uint8_t enable_xhci;			/* Offset 0x0034 */
+	uint8_t lpe_mode;			/* Offset 0x0035 */
+	uint8_t lpss_sio_mode;			/* Offset 0x0036 */
+	uint8_t enable_dma0;			/* Offset 0x0037 */
+	uint8_t enable_dma1;			/* Offset 0x0038 */
+	uint8_t enable_i2_c0;			/* Offset 0x0039 */
+	uint8_t enable_i2_c1;			/* Offset 0x003a */
+	uint8_t enable_i2_c2;			/* Offset 0x003b */
+	uint8_t enable_i2_c3;			/* Offset 0x003c */
+	uint8_t enable_i2_c4;			/* Offset 0x003d */
+	uint8_t enable_i2_c5;			/* Offset 0x003e */
+	uint8_t enable_i2_c6;			/* Offset 0x003f */
+	uint8_t enable_pwm0;			/* Offset 0x0040 */
+	uint8_t enable_pwm1;			/* Offset 0x0041 */
+	uint8_t enable_hsi;			/* Offset 0x0042 */
+	uint8_t igd_dvmt50_pre_alloc;		/* Offset 0x0043 */
+	uint8_t aperture_size;			/* Offset 0x0044 */
+	uint8_t gtt_size;			/* Offset 0x0045 */
+	uint8_t reserved2[5];			/* Offset 0x0046 */
+	uint8_t mrc_debug_msg;			/* Offset 0x004b */
+	uint8_t isp_enable;			/* Offset 0x004c */
+	uint8_t scc_mode;			/* Offset 0x004d */
+	uint8_t igd_render_standby;		/* Offset 0x004e */
+	uint8_t txe_uma_enable;			/* Offset 0x004f */
+	uint8_t os_selection;			/* Offset 0x0050 */
+	uint8_t emmc45_ddr50_enabled;		/* Offset 0x0051 */
+	uint8_t emmc45_hs200_enabled;		/* Offset 0x0052 */
+	uint8_t emmc45_retune_timer_value;	/* Offset 0x0053 */
+	uint8_t enable_igd;			/* Offset 0x0054 */
+	uint8_t unused_upd_space1[155];		/* Offset 0x0055 */
+	struct memory_down_data memory_params;	/* Offset 0x00f0 */
+	uint16_t terminator;			/* Offset 0x0100 */
+};
+
+#define VPD_IMAGE_ID		0x3157454956594C56	/* 'VLYVIEW1' */
+
+struct __packed vpd_region {
+	uint64_t sign;				/* Offset 0x0000 */
+	uint32_t img_rev;			/* Offset 0x0008 */
+	uint32_t upd_offset;			/* Offset 0x000c */
+	uint8_t unused[16];			/* Offset 0x0010 */
+	uint32_t fsp_res_memlen;		/* Offset 0x0020 */
+	uint8_t platform_type;			/* Offset 0x0024 */
+	uint8_t enable_secure_boot;		/* Offset 0x0025 */
+};
+#endif
diff --git a/arch/x86/include/asm/arch-baytrail/global_nvs.h b/arch/x86/include/asm/arch-baytrail/global_nvs.h
new file mode 100644
index 0000000..1072e3d
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/global_nvs.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _GLOBAL_NVS_H_
+#define _GLOBAL_NVS_H_
+
+struct __packed acpi_global_nvs {
+	u8	pcnt;		/* processor count */
+	u8	iuart_en;	/* internal UART enabled */
+
+	/*
+	 * Add padding so sizeof(struct acpi_global_nvs) == 0x100.
+	 * This must match the size defined in the global_nvs.asl.
+	 */
+	u8	rsvd[254];
+};
+
+#endif /* _GLOBAL_NVS_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h
new file mode 100644
index 0000000..752dae0
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/iomap.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
+ */
+
+#ifndef _BAYTRAIL_IOMAP_H_
+#define _BAYTRAIL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS		CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE			0x10000000
+
+/* Temporary Base Address */
+#define TEMP_BASE_ADDRESS		0xfd000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS		0xfeb00000
+#define ABORT_BASE_SIZE			0x00100000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS		0xfed00000
+#define HPET_BASE_SIZE			0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS		0xfed01000
+#define SPI_BASE_SIZE			0x400
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS		0xfed03000
+#define PMC_BASE_SIZE			0x400
+
+#define GEN_PMCON1			0x20
+#define  UART_EN			(1 << 24)
+#define  DISB				(1 << 23)
+#define  MEM_SR				(1 << 21)
+#define  SRS				(1 << 20)
+#define  CTS				(1 << 19)
+#define  MS4V				(1 << 18)
+#define  PWR_FLR			(1 << 16)
+#define  PME_B0_S5_DIS			(1 << 15)
+#define  SUS_PWR_FLR			(1 << 14)
+#define  WOL_EN_OVRD			(1 << 13)
+#define  DIS_SLP_X_STRCH_SUS_UP		(1 << 12)
+#define  GEN_RST_STS			(1 <<  9)
+#define  RPS				(1 <<  2)
+#define  AFTERG3_EN			(1 <<  0)
+#define GEN_PMCON2			0x24
+#define  SLPSX_STR_POL_LOCK		(1 << 18)
+#define  BIOS_PCI_EXP_EN		(1 << 10)
+#define  PWRBTN_LVL			(1 <<  9)
+#define  SMI_LOCK			(1 <<  4)
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS		0xfed05000
+#define PUNIT_BASE_SIZE			0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS		0xfed08000
+#define ILB_BASE_SIZE			0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS			0xfed0c000
+#define  IO_BASE_OFFSET_GPSCORE		0x0000
+#define  IO_BASE_OFFSET_GPNCORE		0x1000
+#define  IO_BASE_OFFSET_GPSSUS		0x2000
+#define IO_BASE_SIZE			0x4000
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS		0xfed1c000
+#define RCBA_BASE_SIZE			0x400
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS		0xfef00000
+#define MPHY_BASE_SIZE			0x100000
+
+/* IO Port bases */
+#define ACPI_BASE_ADDRESS		0x0400
+#define ACPI_BASE_SIZE			0x80
+
+#define PM1_STS				0x00
+#define PM1_CNT				0x04
+
+#define GPIO_BASE_ADDRESS		0x0500
+#define GPIO_BASE_SIZE			0x100
+
+#define SMBUS_BASE_ADDRESS		0xefa0
+
+#endif /* _BAYTRAIL_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/irq.h b/arch/x86/include/asm/arch-baytrail/irq.h
new file mode 100644
index 0000000..fda3f59
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/irq.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
+ */
+
+#ifndef _BAYTRAIL_IRQ_H_
+#define _BAYTRAIL_IRQ_H_
+
+#define PIRQA_APIC_IRQ			16
+#define PIRQB_APIC_IRQ			17
+#define PIRQC_APIC_IRQ			18
+#define PIRQD_APIC_IRQ			19
+#define PIRQE_APIC_IRQ			20
+#define PIRQF_APIC_IRQ			21
+#define PIRQG_APIC_IRQ			22
+#define PIRQH_APIC_IRQ			23
+
+/* The below IRQs are for when devices are in ACPI mode */
+#define LPE_DMA0_IRQ			24
+#define LPE_DMA1_IRQ			25
+#define LPE_SSP0_IRQ			26
+#define LPE_SSP1_IRQ			27
+#define LPE_SSP2_IRQ			28
+#define LPE_IPC2HOST_IRQ		29
+#define LPSS_I2C1_IRQ			32
+#define LPSS_I2C2_IRQ			33
+#define LPSS_I2C3_IRQ			34
+#define LPSS_I2C4_IRQ			35
+#define LPSS_I2C5_IRQ			36
+#define LPSS_I2C6_IRQ			37
+#define LPSS_I2C7_IRQ			38
+#define LPSS_HSUART1_IRQ		39
+#define LPSS_HSUART2_IRQ		40
+#define LPSS_SPI_IRQ			41
+#define LPSS_DMA1_IRQ			42
+#define LPSS_DMA2_IRQ			43
+#define SCC_EMMC_IRQ			44
+#define SCC_SDIO_IRQ			46
+#define SCC_SD_IRQ			47
+#define GPIO_NC_IRQ			48
+#define GPIO_SC_IRQ			49
+#define GPIO_SUS_IRQ			50
+/* GPIO direct / dedicated IRQs */
+#define GPIO_S0_DED_IRQ_0		51
+#define GPIO_S0_DED_IRQ_1		52
+#define GPIO_S0_DED_IRQ_2		53
+#define GPIO_S0_DED_IRQ_3		54
+#define GPIO_S0_DED_IRQ_4		55
+#define GPIO_S0_DED_IRQ_5		56
+#define GPIO_S0_DED_IRQ_6		57
+#define GPIO_S0_DED_IRQ_7		58
+#define GPIO_S0_DED_IRQ_8		59
+#define GPIO_S0_DED_IRQ_9		60
+#define GPIO_S0_DED_IRQ_10		61
+#define GPIO_S0_DED_IRQ_11		62
+#define GPIO_S0_DED_IRQ_12		63
+#define GPIO_S0_DED_IRQ_13		64
+#define GPIO_S0_DED_IRQ_14		65
+#define GPIO_S0_DED_IRQ_15		66
+#define GPIO_S5_DED_IRQ_0		67
+#define GPIO_S5_DED_IRQ_1		68
+#define GPIO_S5_DED_IRQ_2		69
+#define GPIO_S5_DED_IRQ_3		70
+#define GPIO_S5_DED_IRQ_4		71
+#define GPIO_S5_DED_IRQ_5		72
+#define GPIO_S5_DED_IRQ_6		73
+#define GPIO_S5_DED_IRQ_7		74
+#define GPIO_S5_DED_IRQ_8		75
+#define GPIO_S5_DED_IRQ_9		76
+#define GPIO_S5_DED_IRQ_10		77
+#define GPIO_S5_DED_IRQ_11		78
+#define GPIO_S5_DED_IRQ_12		79
+#define GPIO_S5_DED_IRQ_13		80
+#define GPIO_S5_DED_IRQ_14		81
+#define GPIO_S5_DED_IRQ_15		82
+/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
+#define _GPIO_S0_DED_IRQ(slot)		GPIO_S0_DED_IRQ_##slot
+#define _GPIO_S5_DED_IRQ(slot)		GPIO_S5_DED_IRQ_##slot
+#define GPIO_S0_DED_IRQ(slot)		_GPIO_S0_DED_IRQ(slot)
+#define GPIO_S5_DED_IRQ(slot)		_GPIO_S5_DED_IRQ(slot)
+
+#endif /* _BAYTRAIL_IRQ_H_ */
diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
new file mode 100644
index 0000000..4425dcb
--- /dev/null
+++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+#ifndef __ASSEMBLY__
+struct fsp_config_data {
+	struct fsp_cfg_common	common;
+	struct upd_region	fsp_upd;
+};
+
+struct fspinit_rtbuf {
+	struct common_buf	common;	/* FSP common runtime data structure */
+};
+#endif
+
+/* FSP user configuration settings */
+
+#define MRC_INIT_TSEG_SIZE_1MB		1
+#define MRC_INIT_TSEG_SIZE_2MB		2
+#define MRC_INIT_TSEG_SIZE_4MB		4
+#define MRC_INIT_TSEG_SIZE_8MB		8
+
+#define MRC_INIT_MMIO_SIZE_1024MB	0x400
+#define MRC_INIT_MMIO_SIZE_1536MB	0x600
+#define MRC_INIT_MMIO_SIZE_2048MB	0x800
+
+#define IGD_DVMT50_PRE_ALLOC_32MB	0x01
+#define IGD_DVMT50_PRE_ALLOC_64MB	0x02
+#define IGD_DVMT50_PRE_ALLOC_96MB	0x03
+#define IGD_DVMT50_PRE_ALLOC_128MB	0x04
+#define IGD_DVMT50_PRE_ALLOC_160MB	0x05
+#define IGD_DVMT50_PRE_ALLOC_192MB	0x06
+#define IGD_DVMT50_PRE_ALLOC_224MB	0x07
+#define IGD_DVMT50_PRE_ALLOC_256MB	0x08
+#define IGD_DVMT50_PRE_ALLOC_288MB	0x09
+#define IGD_DVMT50_PRE_ALLOC_320MB	0x0a
+#define IGD_DVMT50_PRE_ALLOC_352MB	0x0b
+#define IGD_DVMT50_PRE_ALLOC_384MB	0x0c
+#define IGD_DVMT50_PRE_ALLOC_416MB	0x0d
+#define IGD_DVMT50_PRE_ALLOC_448MB	0x0e
+#define IGD_DVMT50_PRE_ALLOC_480MB	0x0f
+#define IGD_DVMT50_PRE_ALLOC_512MB	0x10
+
+#define APERTURE_SIZE_128MB		1
+#define APERTURE_SIZE_256MB		2
+#define APERTURE_SIZE_512MB		3
+
+#define GTT_SIZE_1MB			1
+#define GTT_SIZE_2MB			2
+
+#define DRAM_TYPE_DDR3			0
+#define DRAM_TYPE_LPDDR3		1
+
+#define SDCARD_MODE_DISABLED		0
+#define SDCARD_MODE_PCI			1
+#define SDCARD_MODE_ACPI		2
+
+#define LPE_MODE_DISABLED		0
+#define LPE_MODE_PCI			1
+#define LPE_MODE_ACPI			2
+
+#define CHV_SVID_CONFIG_0		0
+#define CHV_SVID_CONFIG_1		1
+#define CHV_SVID_CONFIG_2		2
+#define CHV_SVID_CONFIG_3		3
+
+#define EMMC_MODE_DISABLED		0
+#define EMMC_MODE_PCI			1
+#define EMMC_MODE_ACPI			2
+
+#define SATA_SPEED_GEN1			1
+#define SATA_SPEED_GEN2			2
+#define SATA_SPEED_GEN3			3
+
+#define ISP_PCI_DEV_CONFIG_1		1
+#define ISP_PCI_DEV_CONFIG_2		2
+#define ISP_PCI_DEV_CONFIG_3		3
+
+#define PNP_SETTING_DISABLED		0
+#define PNP_SETTING_POWER		1
+#define PNP_SETTING_PERF		2
+#define PNP_SETTING_POWER_AND_PERF	3
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
new file mode 100644
index 0000000..a3bde3d
--- /dev/null
+++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2015, Intel Corporation
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_VPD_H__
+#define __FSP_VPD_H__
+
+struct __packed memory_upd {
+	u64 signature;				/* Offset 0x0020 */
+	u8 revision;				/* Offset 0x0028 */
+	u8 unused2[7];				/* Offset 0x0029 */
+	u16 mrc_init_tseg_size;			/* Offset 0x0030 */
+	u16 mrc_init_mmio_size;			/* Offset 0x0032 */
+	u8 mrc_init_spd_addr1;			/* Offset 0x0034 */
+	u8 mrc_init_spd_addr2;			/* Offset 0x0035 */
+	u8 mem_ch0_config;			/* Offset 0x0036 */
+	u8 mem_ch1_config;			/* Offset 0x0037 */
+	u32 memory_spd_ptr;			/* Offset 0x0038 */
+	u8 igd_dvmt50_pre_alloc;		/* Offset 0x003c */
+	u8 aperture_size;			/* Offset 0x003d */
+	u8 gtt_size;				/* Offset 0x003e */
+	u8 legacy_seg_decode;			/* Offset 0x003f */
+	u8 enable_dvfs;				/* Offset 0x0040 */
+	u8 memory_type;				/* Offset 0x0041 */
+	u8 enable_ca_mirror;			/* Offset 0x0042 */
+	u8 reserved[189];			/* Offset 0x0043 */
+};
+
+struct gpio_family {
+	u32 confg;
+	u32 confg_changes;
+	u32 misc;
+	u32 mmio_addr;
+	wchar_t *name;
+};
+
+struct gpio_pad {
+	u32 confg0;
+	u32 confg0_changes;
+	u32 confg1;
+	u32 confg1_changes;
+	u32 community;
+	u32 mmio_addr;
+	wchar_t *name;
+	u32 misc;
+};
+
+struct __packed silicon_upd {
+	u64 signature;				/* Offset 0x0100 */
+	u8 revision;				/* Offset 0x0108 */
+	u8 unused3[7];				/* Offset 0x0109 */
+	u8 sdcard_mode;				/* Offset 0x0110 */
+	u8 enable_hsuart0;			/* Offset 0x0111 */
+	u8 enable_hsuart1;			/* Offset 0x0112 */
+	u8 enable_azalia;			/* Offset 0x0113 */
+	struct azalia_config *azalia_cfg_ptr;	/* Offset 0x0114 */
+	u8 enable_sata;				/* Offset 0x0118 */
+	u8 enable_xhci;				/* Offset 0x0119 */
+	u8 lpe_mode;				/* Offset 0x011a */
+	u8 enable_dma0;				/* Offset 0x011b */
+	u8 enable_dma1;				/* Offset 0x011c */
+	u8 enable_i2c0;				/* Offset 0x011d */
+	u8 enable_i2c1;				/* Offset 0x011e */
+	u8 enable_i2c2;				/* Offset 0x011f */
+	u8 enable_i2c3;				/* Offset 0x0120 */
+	u8 enable_i2c4;				/* Offset 0x0121 */
+	u8 enable_i2c5;				/* Offset 0x0122 */
+	u8 enable_i2c6;				/* Offset 0x0123 */
+	u32 graphics_config_ptr;		/* Offset 0x0124 */
+	struct gpio_family *gpio_familiy_ptr;	/* Offset 0x0128 */
+	struct gpio_pad *gpio_pad_ptr;		/* Offset 0x012c */
+	u8 disable_punit_pwr_config;		/* Offset 0x0130 */
+	u8 chv_svid_config;			/* Offset 0x0131 */
+	u8 disable_dptf;			/* Offset 0x0132 */
+	u8 emmc_mode;				/* Offset 0x0133 */
+	u8 usb3_clk_ssc;			/* Offset 0x0134 */
+	u8 disp_clk_ssc;			/* Offset 0x0135 */
+	u8 sata_clk_ssc;			/* Offset 0x0136 */
+	u8 usb2_port0_pe_txi_set;		/* Offset 0x0137 */
+	u8 usb2_port0_txi_set;			/* Offset 0x0138 */
+	u8 usb2_port0_tx_emphasis_en;		/* Offset 0x0139 */
+	u8 usb2_port0_tx_pe_half;		/* Offset 0x013a */
+	u8 usb2_port1_pe_txi_set;		/* Offset 0x013b */
+	u8 usb2_port1_txi_set;			/* Offset 0x013c */
+	u8 usb2_port1_tx_emphasis_en;		/* Offset 0x013d */
+	u8 usb2_port1_tx_pe_half;		/* Offset 0x013e */
+	u8 usb2_port2_pe_txi_set;		/* Offset 0x013f */
+	u8 usb2_port2_txi_set;			/* Offset 0x0140 */
+	u8 usb2_port2_tx_emphasis_en;		/* Offset 0x0141 */
+	u8 usb2_port2_tx_pe_half;		/* Offset 0x0142 */
+	u8 usb2_port3_pe_txi_set;		/* Offset 0x0143 */
+	u8 usb2_port3_txi_set;			/* Offset 0x0144 */
+	u8 usb2_port3_tx_emphasis_en;		/* Offset 0x0145 */
+	u8 usb2_port3_tx_pe_half;		/* Offset 0x0146 */
+	u8 usb2_port4_pe_txi_set;		/* Offset 0x0147 */
+	u8 usb2_port4_txi_set;			/* Offset 0x0148 */
+	u8 usb2_port4_tx_emphasis_en;		/* Offset 0x0149 */
+	u8 usb2_port4_tx_pe_half;		/* Offset 0x014a */
+	u8 usb3_lane0_ow2tap_gen2_deemph3p5;	/* Offset 0x014b */
+	u8 usb3_lane1_ow2tap_gen2_deemph3p5;	/* Offset 0x014c */
+	u8 usb3_lane2_ow2tap_gen2_deemph3p5;	/* Offset 0x014d */
+	u8 usb3_lane3_ow2tap_gen2_deemph3p5;	/* Offset 0x014e */
+	u8 sata_speed;				/* Offset 0x014f */
+	u8 usb_ssic_port;			/* Offset 0x0150 */
+	u8 usb_hsic_port;			/* Offset 0x0151 */
+	u8 pcie_rootport_speed;			/* Offset 0x0152 */
+	u8 enable_ssic;				/* Offset 0x0153 */
+	u32 logo_ptr;				/* Offset 0x0154 */
+	u32 logo_size;				/* Offset 0x0158 */
+	u8 rtc_lock;				/* Offset 0x015c */
+	u8 pmic_i2c_bus;			/* Offset 0x015d */
+	u8 enable_isp;				/* Offset 0x015e */
+	u8 isp_pci_dev_config;			/* Offset 0x015f */
+	u8 turbo_mode;				/* Offset 0x0160 */
+	u8 pnp_settings;			/* Offset 0x0161 */
+	u8 sd_detect_chk;			/* Offset 0x0162 */
+	u8 reserved[411];			/* Offset 0x0163 */
+};
+
+#define MEMORY_UPD_ID	0x244450554d454d24	/* '$MEMUPD$' */
+#define SILICON_UPD_ID	0x244450555f495324	/* '$SI_UPD$' */
+
+struct __packed upd_region {
+	u64 signature;				/* Offset 0x0000 */
+	u8 revision;				/* Offset 0x0008 */
+	u8 unused0[7];				/* Offset 0x0009 */
+	u32 memory_upd_offset;			/* Offset 0x0010 */
+	u32 silicon_upd_offset;			/* Offset 0x0014 */
+	u64 unused1;				/* Offset 0x0018 */
+	struct memory_upd memory_upd;		/* Offset 0x0020 */
+	struct silicon_upd silicon_upd;		/* Offset 0x0100 */
+	u16 terminator;				/* Offset 0x02fe */
+};
+
+#define VPD_IMAGE_ID	0x2450534657534224	/* '$BSWFSP$' */
+
+struct __packed vpd_region {
+	u64 sign;				/* Offset 0x0000 */
+	u32 img_rev;				/* Offset 0x0008 */
+	u32 upd_offset;				/* Offset 0x000c */
+};
+
+#endif /* __FSP_VPD_H__ */
diff --git a/arch/x86/include/asm/arch-braswell/gpio.h b/arch/x86/include/asm/arch-braswell/gpio.h
new file mode 100644
index 0000000..e8389e5
--- /dev/null
+++ b/arch/x86/include/asm/arch-braswell/gpio.h
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * From coreboot src/soc/intel/braswell/include/soc/gpio.h
+ */
+
+#ifndef _BRASWELL_GPIO_H_
+#define _BRASWELL_GPIO_H_
+
+#include <asm/arch/iomap.h>
+
+enum mode_list {
+	M0,
+	M1,
+	M2,
+	M3,
+	M4,
+	M5,
+	M6,
+	M7,
+	M8,
+	M9,
+	M10,
+	M11,
+	M12,
+	M13,
+};
+
+enum int_select {
+	L0,
+	L1,
+	L2,
+	L3,
+	L4,
+	L5,
+	L6,
+	L7,
+	L8,
+	L9,
+	L10,
+	L11,
+	L12,
+	L13,
+	L14,
+	L15,
+};
+
+enum gpio_en {
+	NATIVE = 0xff,
+	GPIO = 0,	/* Native, no need to set PAD_VALUE */
+	GPO = 1,	/* GPO, output only in PAD_VALUE */
+	GPI = 2,	/* GPI, input only in PAD_VALUE */
+	HI_Z = 3,
+	NA_GPO = 0,
+};
+
+enum gpio_state {
+	LOW,
+	HIGH,
+};
+
+enum en_dis {
+	DISABLE,	/* Disable */
+	ENABLE,		/* Enable */
+};
+
+enum int_type {
+	INT_DIS,
+	TRIG_EDGE_LOW,
+	TRIG_EDGE_HIGH,
+	TRIG_EDGE_BOTH,
+	TRIG_LEVEL,
+};
+
+enum mask {
+	MASKABLE,
+	NON_MASKABLE,
+};
+
+enum glitch_cfg {
+	GLITCH_DISABLE,
+	EN_EDGE_DETECT,
+	EN_RX_DATA,
+	EN_EDGE_RX_DATA,
+};
+
+enum inv_rx_tx {
+	NO_INVERSION = 0,
+	INV_RX_ENABLE = 1,
+	INV_TX_ENABLE = 2,
+	INV_RX_TX_ENABLE = 3,
+	INV_RX_DATA = 4,
+	INV_TX_DATA = 8,
+};
+
+enum voltage {
+	VOLT_3_3,	/* Working on 3.3 Volts */
+	VOLT_1_8,	/* Working on 1.8 Volts */
+};
+
+enum hs_mode {
+	DISABLE_HS,	/* Disable high speed mode */
+	ENABLE_HS,	/* Enable high speed mode */
+};
+
+enum odt_up_dn {
+	PULL_UP,	/* On Die Termination Up */
+	PULL_DOWN,	/* On Die Termination Down */
+};
+
+enum odt_en {
+	DISABLE_OD,	/* On Die Termination Disable */
+	ENABLE_OD,	/* On Die Termination Enable */
+};
+
+enum pull_type {
+	P_NONE  = 0,	/* Pull None */
+	P_20K_L = 1,	/* Pull Down 20K */
+	P_5K_L  = 2,	/* Pull Down  5K */
+	P_1K_L  = 4,	/* Pull Down  1K */
+	P_20K_H = 9,	/* Pull Up 20K */
+	P_5K_H  = 10,	/* Pull Up  5K */
+	P_1K_H  = 12	/* Pull Up  1K */
+};
+
+enum bit {
+	ONE_BIT = 1,
+	TWO_BIT = 3,
+	THREE_BIT = 7,
+	FOUR_BIT = 15,
+	FIVE_BIT = 31,
+	SIX_BIT = 63,
+	SEVEN_BIT = 127,
+	EIGHT_BIT = 255
+};
+
+enum gpe_config {
+	GPE,
+	SMI,
+	SCI,
+};
+
+enum community {
+	SOUTHWEST = 0x0000,
+	NORTH = 0x8000,
+	EAST = 0x10000,
+	SOUTHEAST = 0x18000,
+	VIRTUAL = 0x20000,
+};
+
+#define NA		0xff
+#define TERMINATOR	0xffffffff
+
+#define GPIO_FAMILY_CONF(family_name, park_mode, hysctl, vp18_mode, hs_mode, \
+	odt_up_dn, odt_en, curr_src_str, rcomp, family_no, community_offset) { \
+	.confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \
+		  (((hysctl) != NA) ? hysctl << 24 : 0) | \
+		  (((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \
+		  (((hs_mode) != NA) ? hs_mode << 19 : 0) | \
+		  (((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \
+		  (((odt_en) != NA) ? odt_en << 17 : 0) | \
+		  (curr_src_str)), \
+	.confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \
+			  (((hysctl) != NA) ? TWO_BIT << 24 : 0) | \
+			  (((vp18_mode) != NA) ? ONE_BIT  << 21 : 0) | \
+			  (((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \
+			  (((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \
+			  (((odt_en) != NA) ? ONE_BIT << 17 : 0) | \
+			  (THREE_BIT)), \
+	.misc = ((rcomp == ENABLE) ? 1 : 0) , \
+	.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
+		     ((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\
+		     (0x80 * family_no) + 0x1080) : 0) , \
+	.name = 0 \
+}
+
+#define GPIO_PAD_CONF(pad_name, mode_select, mode, gpio_config, gpio_state, \
+	gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\
+	int_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \
+	mmio_offset, community_offset) { \
+	.confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \
+		   (((glitch) != NA) ? (glitch << 26) : 0) | \
+		   (((term) != NA) ? (term << 20) : 0) | \
+		   (((mode_select) == GPIO) ? ((mode << 16) | (1 << 15)) : \
+		    ((mode << 16))) | \
+		   (((gpio_config) != NA) ? (gpio_config << 8) : 0) | \
+		   (((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \
+		   (((gpio_state) == HIGH) ? 2 : 0)), \
+	.confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \
+			   (((glitch) != NA) ? (TWO_BIT << 26) : 0) | \
+			   (((term) != NA) ? (FOUR_BIT << 20) : 0) | \
+			   (FIVE_BIT << 15) | \
+			   (((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \
+			   (((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \
+			   (((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \
+	.confg1  = ((((current_source) != NA) ? (current_source << 27) : 0) | \
+		    (((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \
+		    (((open_drain) != NA) ? open_drain << 3 : 0) | \
+		    (((int_type) != NA) ? int_type : 0)), \
+	.confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \
+			   (((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \
+			   (((open_drain) != NA) ? ONE_BIT << 3 : 0) | \
+			   (((int_type) != NA) ? THREE_BIT : 0)), \
+	.community = community_offset, \
+	.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \
+		     ((mmio_offset != NA) ? (IO_BASE_ADDRESS + \
+		      community_offset + mmio_offset) : 0), \
+	.name = 0, \
+	.misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \
+		 (((wake_mask) != NA) ? (wake_mask << 2) : 0) | \
+		 (((int_mask) != NA) ? (int_mask << 3) : 0)) | \
+		 (((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \
+}
+
+#endif /* _BRASWELL_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-braswell/iomap.h b/arch/x86/include/asm/arch-braswell/iomap.h
new file mode 100644
index 0000000..873d331
--- /dev/null
+++ b/arch/x86/include/asm/arch-braswell/iomap.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _BRASWELL_IOMAP_H_
+#define _BRASWELL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS	0xfed03000
+#define PMC_BASE_SIZE		0x400
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS	0xfed05000
+#define PUNIT_BASE_SIZE		0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS	0xfed08000
+#define ILB_BASE_SIZE		0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS	0xfed01000
+#define SPI_BASE_SIZE		0x400
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS	0xfed1c000
+#define RCBA_BASE_SIZE		0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS		0xfed80000
+#define IO_BASE_SIZE		0x4000
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS	0xfef00000
+#define MPHY_BASE_SIZE		0x100000
+
+/* IO Port bases */
+
+#define ACPI_BASE_ADDRESS	0x400
+#define ACPI_BASE_SIZE		0x80
+
+#define GPIO_BASE_ADDRESS	0x500
+#define GPIO_BASE_SIZE		0x100
+
+#define SMBUS_BASE_ADDRESS	0xefa0
+
+#endif /* _BRASWELL_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-broadwell/adsp.h b/arch/x86/include/asm/arch-broadwell/adsp.h
new file mode 100644
index 0000000..eb825ce
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/adsp.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Support for Intel Application Digital Signal Processor
+ *
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot file of the same name
+ */
+
+#ifndef __ASM_ARCH_BROADWELL_ADSP_H
+#define __ASM_ARCH_BROADWELL_ADSP_H
+
+#define ADSP_PCI_IRQ			23
+#define ADSP_ACPI_IRQ			3
+#define  ADSP_ACPI_IRQEN		BIT(3)
+
+#define ADSP_SHIM_BASE_LPT		0xe7000
+#define ADSP_SHIM_BASE_WPT		0xfb000
+#define  ADSP_SHIM_LTRC			0xe0
+#define   ADSP_SHIM_LTRC_VALUE		0x3003
+#define  ADSP_SHIM_IMC			0x28
+#define  ADSP_SHIM_IPCD			0x40
+
+#define ADSP_PCI_VDRTCTL0		0xa0
+#define  ADSP_VDRTCTL0_D3PGD_LPT	BIT(1)
+#define  ADSP_VDRTCTL0_D3PGD_WPT	BIT(0)
+#define  ADSP_VDRTCTL0_D3SRAMPGD_LPT	BIT(2)
+#define  ADSP_VDRTCTL0_D3SRAMPGD_WPT	BIT(1)
+#define ADSP_PCI_VDRTCTL1		0xa4
+#define ADSP_PCI_VDRTCTL2		0xa8
+#define  ADSP_VDRTCTL2_VALUE		0x00000fff
+
+#define ADSP_IOBP_VDLDAT1		0xd7000624
+#define  ADSP_VDLDAT1_VALUE		0x00040100
+#define ADSP_IOBP_VDLDAT2		0xd7000628
+#define  ADSP_IOBP_ACPI_IRQ3		0xd9d8
+#define  ADSP_IOBP_ACPI_IRQ3I		0xd8d9
+#define  ADSP_IOBP_ACPI_IRQ4		0xdbda
+#define ADSP_IOBP_PMCTL			0xd70001e0
+#define  ADSP_PMCTL_VALUE		0x3f
+#define ADSP_IOBP_PCICFGCTL		0xd7000500
+#define  ADSP_PCICFGCTL_PCICD		BIT(0)
+#define  ADSP_PCICFGCTL_ACPIIE		BIT(1)
+#define  ADSP_PCICFGCTL_SPCBAD		BIT(7)
+
+#endif /* __ASM_ARCH_BROADWELL_ADSP_H */
diff --git a/arch/x86/include/asm/arch-broadwell/cpu.h b/arch/x86/include/asm/arch-broadwell/cpu.h
new file mode 100644
index 0000000..3bc3bd6
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/cpu.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __asm_arch_cpu_h
+#define __asm_arch_cpu_h
+
+/* CPU types */
+#define HASWELL_FAMILY_ULT	0x40650
+#define BROADWELL_FAMILY_ULT	0x306d0
+
+/* Supported CPUIDs */
+#define CPUID_HASWELL_A0	0x306c1
+#define CPUID_HASWELL_B0	0x306c2
+#define CPUID_HASWELL_C0	0x306c3
+#define CPUID_HASWELL_ULT_B0	0x40650
+#define CPUID_HASWELL_ULT	0x40651
+#define CPUID_HASWELL_HALO	0x40661
+#define CPUID_BROADWELL_C0	0x306d2
+#define CPUID_BROADWELL_D0	0x306d3
+#define CPUID_BROADWELL_E0	0x306d4
+
+#define BROADWELL_FAMILY_ULT	0x306d0
+
+#define CORE_THREAD_COUNT_MSR		0x35
+
+#define MSR_VR_CURRENT_CONFIG		0x601
+#define MSR_VR_MISC_CONFIG		0x603
+#define MSR_PKG_POWER_SKU		0x614
+#define MSR_DDR_RAPL_LIMIT		0x618
+#define MSR_VR_MISC_CONFIG2		0x636
+
+/* Latency times in units of 1024ns. */
+#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
+#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
+#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
+#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
+#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
+#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
+
+void cpu_set_power_limits(int power_limit_1_time);
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/gpio.h b/arch/x86/include/asm/arch-broadwell/gpio.h
new file mode 100644
index 0000000..a32e2db
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/gpio.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From Coreboot src/soc/intel/broadwell/include/soc/gpio.h
+ */
+
+#ifndef __ASM_ARCH_GPIO
+#define __ASM_ARCH_GPIO
+
+#define GPIO_PER_BANK	32
+#define GPIO_BANKS	3
+
+struct broadwell_bank_platdata {
+	uint16_t base_addr;
+	const char *bank_name;
+	int bank;
+};
+
+/* PCH-LP GPIOBASE Registers */
+struct pch_lp_gpio_regs {
+	u32 own[GPIO_BANKS];
+	u32 reserved0;
+
+	u16 pirq_to_ioxapic;
+	u16 reserved1[3];
+	u32 blink;
+	u32 ser_blink;
+
+	u32 ser_blink_cmdsts;
+	u32 ser_blink_data;
+	u16 gpi_nmi_en;
+	u16 gpi_nmi_sts;
+	u32 reserved2;
+
+	u32 gpi_route[GPIO_BANKS];
+	u32 reserved3;
+
+	u32 reserved4[4];
+
+	u32 alt_gpi_smi_sts;
+	u32 alt_gpi_smi_en;
+	u32 reserved5[2];
+
+	u32 rst_sel[GPIO_BANKS];
+	u32 reserved6;
+
+	u32 reserved9[3];
+	u32 gpio_gc;
+
+	u32 gpi_is[GPIO_BANKS];
+	u32 reserved10;
+
+	u32 gpi_ie[GPIO_BANKS];
+	u32 reserved11;
+
+	u32 reserved12[24];
+
+	struct {
+		u32 conf_a;
+		u32 conf_b;
+	} config[GPIO_BANKS * GPIO_PER_BANK];
+};
+check_member(pch_lp_gpio_regs, gpi_ie[0], 0x90);
+check_member(pch_lp_gpio_regs, config[0], 0x100);
+
+enum {
+	CONFA_MODE_SHIFT	= 0,
+	CONFA_MODE_GPIO		= 1 << CONFA_MODE_SHIFT,
+
+	CONFA_DIR_SHIFT		= 2,
+	CONFA_DIR_INPUT		= 1 << CONFA_DIR_SHIFT,
+
+	CONFA_INVERT_SHIFT	= 3,
+	CONFA_INVERT		= 1 << CONFA_INVERT_SHIFT,
+
+	CONFA_TRIGGER_SHIFT	= 4,
+	CONFA_TRIGGER_LEVEL	= 1 << CONFA_TRIGGER_SHIFT,
+
+	CONFA_LEVEL_SHIFT	= 30,
+	CONFA_LEVEL_HIGH	= 1UL << CONFA_LEVEL_SHIFT,
+
+	CONFA_OUTPUT_SHIFT	= 31,
+	CONFA_OUTPUT_HIGH	= 1UL << CONFA_OUTPUT_SHIFT,
+
+	CONFB_SENSE_SHIFT	= 2,
+	CONFB_SENSE_DISABLE	= 1 << CONFB_SENSE_SHIFT,
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/iomap.h b/arch/x86/include/asm/arch-broadwell/iomap.h
new file mode 100644
index 0000000..de7f6e5
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/iomap.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * From Coreboot soc/intel/broadwell/include/soc/iomap.h
+ *
+ * Copyright (C) 2016 Google Inc.
+ */
+
+#ifndef __asm_arch_iomap_h
+#define __asm_arch_iomap_h
+
+#define MCFG_BASE_ADDRESS	0xf0000000
+#define MCFG_BASE_SIZE		0x4000000
+
+#define HPET_BASE_ADDRESS	0xfed00000
+
+#define MCH_BASE_ADDRESS	0xfed10000
+#define MCH_BASE_SIZE		0x8000
+
+#define DMI_BASE_ADDRESS	0xfed18000
+#define DMI_BASE_SIZE		0x1000
+
+#define EP_BASE_ADDRESS		0xfed19000
+#define EP_BASE_SIZE		0x1000
+
+#define EDRAM_BASE_ADDRESS	0xfed80000
+#define EDRAM_BASE_SIZE		0x4000
+
+#define GDXC_BASE_ADDRESS	0xfed84000
+#define GDXC_BASE_SIZE		0x1000
+
+#define RCBA_BASE_ADDRESS	0xfed1c000
+#define RCBA_BASE_SIZE		0x4000
+
+#define HPET_BASE_ADDRESS	0xfed00000
+
+#define ACPI_BASE_ADDRESS	0x1000
+#define ACPI_BASE_SIZE		0x100
+
+#define GPIO_BASE_ADDRESS	0x1400
+#define GPIO_BASE_SIZE		0x400
+
+#define SMBUS_BASE_ADDRESS	0x0400
+#define SMBUS_BASE_SIZE		0x10
+
+/* Temporary addresses used before relocation */
+#define EARLY_GTT_BAR		0xe0000000
+#define EARLY_XHCI_BAR		0xd7000000
+#define EARLY_EHCI_BAR		0xd8000000
+#define EARLY_UART_BAR		0x3f8
+#define EARLY_TEMP_MMIO		0xfed08000
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/lpc.h b/arch/x86/include/asm/arch-broadwell/lpc.h
new file mode 100644
index 0000000..98f928a
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/lpc.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * From coreboot soc/intel/broadwell/include/soc/lpc.h
+ *
+ * Copyright (C) 2016 Google Inc.
+ */
+
+#ifndef _ASM_ARCH_LPC_H
+#define _ASM_ARCH_LPC_H
+
+#define GEN_PMCON_1		0xa0
+#define  SMI_LOCK		(1 << 4)
+#define GEN_PMCON_2		0xa2
+#define  SYSTEM_RESET_STS	(1 << 4)
+#define  THERMTRIP_STS		(1 << 3)
+#define  SYSPWR_FLR		(1 << 1)
+#define  PWROK_FLR		(1 << 0)
+#define GEN_PMCON_3		0xa4
+#define  SUS_PWR_FLR		(1 << 14)
+#define  GEN_RST_STS		(1 << 9)
+#define  RTC_BATTERY_DEAD	(1 << 2)
+#define  PWR_FLR		(1 << 1)
+#define  SLEEP_AFTER_POWER_FAIL	(1 << 0)
+#define GEN_PMCON_LOCK		0xa6
+#define  SLP_STR_POL_LOCK	(1 << 2)
+#define  ACPI_BASE_LOCK		(1 << 1)
+#define PMIR			0xac
+#define  PMIR_CF9LOCK		(1 << 31)
+#define  PMIR_CF9GR		(1 << 20)
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/me.h b/arch/x86/include/asm/arch-broadwell/me.h
new file mode 100644
index 0000000..58f16ba
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/me.h
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * From coreboot soc/intel/broadwell/include/soc/me.h
+ *
+ * Copyright (C) 2014 Google Inc.
+ */
+
+#ifndef _asm_arch_me_h
+#define _asm_arch_me_h
+
+#include <asm/me_common.h>
+
+#define  ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
+
+#define ME_HSIO_MESSAGE		(7 << 28)
+#define ME_HSIO_CMD_GETHSIOVER	1
+#define ME_HSIO_CMD_CLOSE	0
+
+/*
+ * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
+ * to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature.
+ */
+#define PCI_ME_HFS2		0x48
+/* Infrastructure Progress Values */
+#define  ME_HFS2_PHASE_ROM		0
+#define  ME_HFS2_PHASE_BUP		1
+#define  ME_HFS2_PHASE_UKERNEL		2
+#define  ME_HFS2_PHASE_POLICY		3
+#define  ME_HFS2_PHASE_MODULE_LOAD	4
+#define  ME_HFS2_PHASE_UNKNOWN		5
+#define  ME_HFS2_PHASE_HOST_COMM	6
+/* Current State - Based on Infra Progress values. */
+/*       ROM State */
+#define  ME_HFS2_STATE_ROM_BEGIN 0
+#define  ME_HFS2_STATE_ROM_DISABLE 6
+/*       BUP State */
+#define  ME_HFS2_STATE_BUP_INIT 0
+#define  ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
+#define  ME_HFS2_STATE_BUP_FLOW_DET 4
+#define  ME_HFS2_STATE_BUP_VSCC_ERR 8
+#define  ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
+#define  ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
+#define  ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
+#define  ME_HFS2_STATE_BUP_M3 0x11
+#define  ME_HFS2_STATE_BUP_M0 0x12
+#define  ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
+#define  ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
+#define  ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
+#define  ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
+#define  ME_HFS2_STATE_BUP_T32_MISSING 0x1c
+#define  ME_HFS2_STATE_BUP_WAIT_DID 0x1f
+#define  ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
+#define  ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
+#define  ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
+#define  ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
+#define  ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
+#define  ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
+#define  ME_HFS2_STATE_BUP_M0_CLK 0x26
+#define  ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
+#define  ME_HFS2_STATE_BUP_TEMP_DIS 0x28
+#define  ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
+/*       Policy Module State */
+#define  ME_HFS2_STATE_POLICY_ENTRY 0
+#define  ME_HFS2_STATE_POLICY_RCVD_S3 3
+#define  ME_HFS2_STATE_POLICY_RCVD_S4 4
+#define  ME_HFS2_STATE_POLICY_RCVD_S5 5
+#define  ME_HFS2_STATE_POLICY_RCVD_UPD 6
+#define  ME_HFS2_STATE_POLICY_RCVD_PCR 7
+#define  ME_HFS2_STATE_POLICY_RCVD_NPCR 8
+#define  ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
+#define  ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
+#define  ME_HFS2_STATE_POLICY_RCVD_DID 0xb
+#define  ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
+#define  ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
+#define  ME_HFS2_STATE_POLICY_FPB_ERR 0xe
+#define  ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
+#define  ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
+/* Current PM Event Values */
+#define  ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
+#define  ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
+#define  ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
+#define  ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
+#define  ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
+#define  ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
+#define  ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
+#define  ME_HFS2_PMEVENT_S0MO_SXM3 7
+#define  ME_HFS2_PMEVENT_SXM3_S0M0 8
+#define  ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
+#define  ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
+#define  ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
+#define  ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
+
+struct me_hfs2 {
+	u32 bist_in_progress:1;
+	u32 reserved1:2;
+	u32 invoke_mebx:1;
+	u32 cpu_replaced_sts:1;
+	u32 mbp_rdy:1;
+	u32 mfs_failure:1;
+	u32 warm_reset_request:1;
+	u32 cpu_replaced_valid:1;
+	u32 reserved2:4;
+	u32 mbp_cleared:1;
+	u32 reserved3:2;
+	u32 current_state:8;
+	u32 current_pmevent:4;
+	u32 progress_code:4;
+} __packed;
+
+#define PCI_ME_HFS5		0x68
+
+#define PCI_ME_H_GS2		0x70
+#define   PCI_ME_MBP_GIVE_UP	0x01
+
+/* ICC Messages */
+#define ICC_SET_CLOCK_ENABLES		0x3
+#define ICC_API_VERSION_LYNXPOINT	0x00030000
+
+struct icc_header {
+	u32 api_version;
+	u32 icc_command;
+	u32 icc_status;
+	u32 length;
+	u32 reserved;
+} __packed;
+
+struct icc_clock_enables_msg {
+	u32 clock_enables;
+	u32 clock_mask;
+	u32 no_response:1;
+	u32 reserved:31;
+} __packed;
+
+/*
+ * ME to BIOS Payload Datastructures and definitions. The ordering of the
+ * structures follows the ordering in the ME9 BWG.
+ */
+
+#define MBP_APPID_KERNEL 1
+#define MBP_APPID_INTEL_AT 3
+#define MBP_APPID_HWA 4
+#define MBP_APPID_ICC 5
+#define MBP_APPID_NFC 6
+/* Kernel items: */
+#define MBP_KERNEL_FW_VER_ITEM 1
+#define MBP_KERNEL_FW_CAP_ITEM 2
+#define MBP_KERNEL_ROM_BIST_ITEM 3
+#define MBP_KERNEL_PLAT_KEY_ITEM 4
+#define MBP_KERNEL_FW_TYPE_ITEM 5
+#define MBP_KERNEL_MFS_FAILURE_ITEM 6
+#define MBP_KERNEL_PLAT_TIME_ITEM 7
+/* Intel AT items: */
+#define MBP_INTEL_AT_STATE_ITEM 1
+/* ICC Items: */
+#define MBP_ICC_PROFILE_ITEM 1
+/* HWA Items: */
+#define MBP_HWA_REQUEST_ITEM 1
+/* NFC Items: */
+#define MBP_NFC_SUPPORT_DATA_ITEM 1
+
+#define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item)
+#define MBP_IDENT(appid, item) \
+	MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM)
+
+struct mbp_fw_version_name {
+	u32	major_version:16;
+	u32	minor_version:16;
+	u32	hotfix_version:16;
+	u32	build_version:16;
+} __packed;
+
+struct icc_address_mask {
+	u16 icc_start_address;
+	u16 mask;
+} __packed;
+
+struct mbp_icc_profile {
+	u8	num_icc_profiles;
+	u8	icc_profile_soft_strap;
+	u8	icc_profile_index;
+	u8	reserved;
+	u32	icc_reg_bundles;
+	struct icc_address_mask icc_address_mask[0];
+} __packed;
+
+struct me_bios_payload {
+	struct mbp_fw_version_name	*fw_version_name;
+	struct mbp_mefwcaps	*fw_capabilities;
+	struct mbp_rom_bist_data *rom_bist_data;
+	struct mbp_platform_key *platform_key;
+	struct mbp_plat_type	*fw_plat_type;
+	struct mbp_icc_profile	*icc_profile;
+	struct mbp_at_state	*at_state;
+	u32		*mfsintegrity;
+	struct mbp_plat_time	*plat_time;
+	struct mbp_nfc_data	*nfc_data;
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/pch.h b/arch/x86/include/asm/arch-broadwell/pch.h
new file mode 100644
index 0000000..ecdf6d1
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/pch.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __ASM_ARCH_PCH_H
+#define __ASM_ARCH_PCH_H
+
+#define PMBASE			0x40
+#define ACPI_CNTL		0x44
+#define  ACPI_EN		(1 << 7)
+
+#define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
+#define  GPIO_EN		(1 << 4)
+
+#define PCIEXBAR	0x60
+
+#define  PCH_DEV_LPC		PCI_BDF(0, 0x1f, 0)
+
+/* RCB registers */
+#define OIC		0x31fe	/* 16bit */
+#define HPTC		0x3404	/* 32bit */
+#define FD		0x3418	/* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS	(1 << 0)
+
+/* PM registers */
+#define TCO1_CNT		0x60
+#define  TCO_TMR_HLT		(1 << 11)
+
+
+/* Device 0:0.0 PCI configuration space */
+
+#define EPBAR		0x40
+#define MCHBAR		0x48
+#define PCIEXBAR	0x60
+#define DMIBAR		0x68
+#define GGC		0x50	/* GMCH Graphics Control */
+#define DEVEN		0x54	/* Device Enable */
+#define  DEVEN_D7EN	(1 << 14)
+#define  DEVEN_D4EN	(1 << 7)
+#define  DEVEN_D3EN	(1 << 5)
+#define  DEVEN_D2EN	(1 << 4)
+#define  DEVEN_D1F0EN	(1 << 3)
+#define  DEVEN_D1F1EN	(1 << 2)
+#define  DEVEN_D1F2EN	(1 << 1)
+#define  DEVEN_D0EN	(1 << 0)
+#define DPR		0x5c
+#define  DPR_EPM	(1 << 2)
+#define  DPR_PRS	(1 << 1)
+#define  DPR_SIZE_MASK	0xff0
+
+#define MCHBAR_PEI_VERSION	0x5034
+#define BIOS_RESET_CPL		0x5da8
+#define EDRAMBAR		0x5408
+#define MCH_PAIR		0x5418
+#define GDXCBAR			0x5420
+
+#define PAM0		0x80
+#define PAM1		0x81
+#define PAM2		0x82
+#define PAM3		0x83
+#define PAM4		0x84
+#define PAM5		0x85
+#define PAM6		0x86
+
+/* PCODE MMIO communications live in the MCHBAR. */
+#define BIOS_MAILBOX_INTERFACE			0x5da4
+#define  MAILBOX_RUN_BUSY			(1 << 31)
+#define  MAILBOX_BIOS_CMD_READ_PCS		1
+#define  MAILBOX_BIOS_CMD_WRITE_PCS		2
+#define  MAILBOX_BIOS_CMD_READ_CALIBRATION	0x509
+#define  MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL	0x909
+#define  MAILBOX_BIOS_CMD_READ_PCH_POWER	0xa
+#define  MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT	0xb
+#define  MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE	0x26
+#define  MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE	0x27
+/* Errors are returned back in bits 7:0. */
+#define  MAILBOX_BIOS_ERROR_NONE		0
+#define  MAILBOX_BIOS_ERROR_INVALID_COMMAND	1
+#define  MAILBOX_BIOS_ERROR_TIMEOUT		2
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_DATA	3
+#define  MAILBOX_BIOS_ERROR_RESERVED		4
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID	5
+#define  MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED	6
+#define  MAILBOX_BIOS_ERROR_VR_ERROR		7
+/* Data is passed through bits 31:0 of the data register. */
+#define BIOS_MAILBOX_DATA			0x5da0
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0_SECRT88	0xea002688
+#define SATA_IOBP_SP1_SECRT88	0xea002488
+
+#define SATA_SECRT88_VADJ_MASK	0xff
+#define SATA_SECRT88_VADJ_SHIFT	16
+
+#define SATA_IOBP_SP0DTLE_DATA	0xea002550
+#define SATA_IOBP_SP0DTLE_EDGE	0xea002554
+#define SATA_IOBP_SP1DTLE_DATA	0xea002750
+#define SATA_IOBP_SP1DTLE_EDGE	0xea002754
+
+#define SATA_DTLE_MASK		0xF
+#define SATA_DTLE_DATA_SHIFT	24
+#define SATA_DTLE_EDGE_SHIFT	16
+
+/* Power Management */
+#define PCH_PCS			0x84
+#define  PCH_PCS_PS_D3HOT	3
+
+#define GEN_PMCON_1		0xa0
+#define  SMI_LOCK		(1 << 4)
+#define GEN_PMCON_2		0xa2
+#define  SYSTEM_RESET_STS	(1 << 4)
+#define  THERMTRIP_STS		(1 << 3)
+#define  SYSPWR_FLR		(1 << 1)
+#define  PWROK_FLR		(1 << 0)
+#define GEN_PMCON_3		0xa4
+#define  SUS_PWR_FLR		(1 << 14)
+#define  GEN_RST_STS		(1 << 9)
+#define  RTC_BATTERY_DEAD	(1 << 2)
+#define  PWR_FLR		(1 << 1)
+#define  SLEEP_AFTER_POWER_FAIL	(1 << 0)
+#define GEN_PMCON_LOCK		0xa6
+#define  SLP_STR_POL_LOCK	(1 << 2)
+#define  ACPI_BASE_LOCK		(1 << 1)
+#define PMIR			0xac
+#define  PMIR_CF9LOCK		(1 << 31)
+#define  PMIR_CF9GR		(1 << 20)
+
+/* Broadwell PCH (Wildcat Point) */
+#define PCH_WPT_HSW_U_SAMPLE	0x9cc1
+#define PCH_WPT_BDW_U_SAMPLE	0x9cc2
+#define PCH_WPT_BDW_U_PREMIUM	0x9cc3
+#define PCH_WPT_BDW_U_BASE	0x9cc5
+#define PCH_WPT_BDW_Y_SAMPLE	0x9cc6
+#define PCH_WPT_BDW_Y_PREMIUM	0x9cc7
+#define PCH_WPT_BDW_Y_BASE	0x9cc9
+#define PCH_WPT_BDW_H		0x9ccb
+
+#define SA_IGD_OPROM_VENDEV	0x80860406
+
+/* Dynamically determine if the part is ULT */
+bool cpu_is_ult(void);
+
+u32 pch_iobp_read(u32 address);
+int pch_iobp_write(u32 address, u32 data);
+int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+int  pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp);
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/pei_data.h b/arch/x86/include/asm/arch-broadwell/pei_data.h
new file mode 100644
index 0000000..4442bea
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/pei_data.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * From Coreboot soc/intel/broadwell/include/soc/pei_data.h
+ *
+ * Copyright (C) 2014 Google Inc.
+ */
+
+#ifndef ASM_ARCH_PEI_DATA_H
+#define ASM_ARCH_PEI_DATA_H
+
+#include <linux/linkage.h>
+
+#define PEI_VERSION 22
+
+typedef void asmlinkage (*tx_byte_func)(unsigned char byte);
+
+enum board_type {
+	BOARD_TYPE_CRB_MOBILE = 0,	/* CRB Mobile */
+	BOARD_TYPE_CRB_DESKTOP,		/* CRB Desktop */
+	BOARD_TYPE_USER1,		/* SV mobile */
+	BOARD_TYPE_USER2,		/* SV desktop */
+	BOARD_TYPE_USER3,		/* SV server */
+	BOARD_TYPE_ULT,			/* ULT */
+	BOARD_TYPE_CRB_EMBDEDDED,	/* CRB Embedded */
+	BOARD_TYPE_UNKNOWN,
+};
+
+#define MAX_USB2_PORTS 14
+#define MAX_USB3_PORTS 6
+#define USB_OC_PIN_SKIP 8
+
+enum usb2_port_location {
+	USB_PORT_BACK_PANEL = 0,
+	USB_PORT_FRONT_PANEL,
+	USB_PORT_DOCK,
+	USB_PORT_MINI_PCIE,
+	USB_PORT_FLEX,
+	USB_PORT_INTERNAL,
+	USB_PORT_SKIP,
+	USB_PORT_NGFF_DEVICE_DOWN,
+};
+
+struct usb2_port_setting {
+	/*
+	 * Usb Port Length:
+	 * [16:4] = length in inches in octal format
+	 * [3:0]  = decimal point
+	 */
+	uint16_t length;
+	uint8_t enable;
+	uint8_t oc_pin;
+	uint8_t location;
+} __packed;
+
+struct usb3_port_setting {
+	uint8_t enable;
+	uint8_t oc_pin;
+	/*
+	 * Set to 0 if trace length is > 5 inches
+	 * Set to 1 if trace length is <= 5 inches
+	 */
+	uint8_t fixed_eq;
+} __packed;
+
+
+struct pei_data {
+	uint32_t pei_version;
+
+	enum board_type board_type;
+	int boot_mode;
+	int ec_present;
+	int usbdebug;
+
+	/* Base addresses */
+	uint32_t pciexbar;
+	uint16_t smbusbar;
+	uint32_t xhcibar;
+	uint32_t ehcibar;
+	uint32_t gttbar;
+	uint32_t rcba;
+	uint32_t pmbase;
+	uint32_t gpiobase;
+	uint32_t temp_mmio_base;
+	uint32_t tseg_size;
+
+	/*
+	 * 0 = leave channel enabled
+	 * 1 = disable dimm 0 on channel
+	 * 2 = disable dimm 1 on channel
+	 * 3 = disable dimm 0+1 on channel
+	 */
+	int dimm_channel0_disabled;
+	int dimm_channel1_disabled;
+	/* Set to 0 for memory down */
+	uint8_t spd_addresses[4];
+	/* Enable 2x Refresh Mode */
+	int ddr_refresh_2x;
+	/* DQ pins are interleaved on board */
+	int dq_pins_interleaved;
+	/* Limit DDR3 frequency */
+	int max_ddr3_freq;
+	/* Disable self refresh */
+	int disable_self_refresh;
+	/* Disable cmd power/CKEPD */
+	int disable_cmd_pwr;
+
+	/* USB port configuration */
+	struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
+	struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
+
+	/*
+	 * USB3 board specific PHY tuning
+	 */
+
+	/* Valid range: 0x69 - 0x80 */
+	uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS];
+	/* Valid range: 0x80 - 0x9c */
+	uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS];
+	/* Valid range: 0x39 - 0x80 */
+	uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS];
+	/* Valid range: 0x3d - 0x4a */
+	uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS];
+
+	/* Console output function */
+	tx_byte_func tx_byte;
+
+	/*
+	 * DIMM SPD data for memory down configurations
+	 * [CHANNEL][SLOT][SPD]
+	 */
+	uint8_t spd_data[2][2][512];
+
+	/*
+	 * LPDDR3 DQ byte map
+	 * [CHANNEL][ITERATION][2]
+	 *
+	 * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
+	 * DQByteMap[0] - ClkDQByteMap:
+	 * - If clock is per rank, program to [0xFF, 0xFF]
+	 * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+	 * - If clock is shared by 2 ranks but does not go to all bytes,
+	 *   Entry[i] defines which DQ bytes Group i services
+	 * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
+	 * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
+	 * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
+	 *                For DDR, DQByteMap[3:1] = [0xFF, 0]
+	 * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
+	 *                since we have 1 CTL / rank
+	 * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
+	 *                since we have 1 CA Vref
+	 */
+	uint8_t dq_map[2][6][2];
+
+	/*
+	 * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
+	 * [CHANNEL][MAX_BYTES]
+	 */
+	uint8_t dqs_map[2][8];
+
+	/* Data read from flash and passed into MRC */
+	const void *saved_data;
+	int saved_data_size;
+
+	/* Disable use of saved data (can be set by mainboard) */
+	int disable_saved_data;
+
+	/* Data from MRC that should be saved to flash */
+	void *data_to_save;
+	int data_to_save_size;
+	struct pei_memory_info meminfo;
+} __packed;
+
+void mainboard_fill_pei_data(struct pei_data *pei_data);
+void broadwell_fill_pei_data(struct pei_data *pei_data);
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/pm.h b/arch/x86/include/asm/arch-broadwell/pm.h
new file mode 100644
index 0000000..df35080
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/pm.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * From coreboot src/soc/intel/broadwell/include/soc/pm.h
+ *
+ * Copyright (C) 2016 Google, Inc.
+ */
+
+#ifndef __ASM_ARCH_PM_H
+#define __ASM_ARCH_PM_H
+
+#define PM1_STS			0x00
+#define  WAK_STS		(1 << 15)
+#define  PCIEXPWAK_STS		(1 << 14)
+#define  PRBTNOR_STS		(1 << 11)
+#define  RTC_STS		(1 << 10)
+#define  PWRBTN_STS		(1 << 8)
+#define  GBL_STS		(1 << 5)
+#define  BM_STS			(1 << 4)
+#define  TMROF_STS		(1 << 0)
+#define PM1_EN			0x02
+#define  PCIEXPWAK_DIS		(1 << 14)
+#define  RTC_EN			(1 << 10)
+#define  PWRBTN_EN		(1 << 8)
+#define  GBL_EN			(1 << 5)
+#define  TMROF_EN		(1 << 0)
+#define PM1_CNT			0x04
+#define  SLP_EN			(1 << 13)
+#define  SLP_TYP		(7 << 10)
+#define   SLP_TYP_SHIFT         10
+#define   SLP_TYP_S0		0
+#define   SLP_TYP_S1		1
+#define   SLP_TYP_S3		5
+#define   SLP_TYP_S4		6
+#define   SLP_TYP_S5		7
+#define  GBL_RLS		(1 << 2)
+#define  BM_RLD			(1 << 1)
+#define  SCI_EN			(1 << 0)
+#define PM1_TMR			0x08
+#define SMI_EN			0x30
+#define  XHCI_SMI_EN		(1 << 31)
+#define  ME_SMI_EN		(1 << 30)
+#define  GPIO_UNLOCK_SMI_EN	(1 << 27)
+#define  INTEL_USB2_EN		(1 << 18)
+#define  LEGACY_USB2_EN		(1 << 17)
+#define  PERIODIC_EN		(1 << 14)
+#define  TCO_EN			(1 << 13)
+#define  MCSMI_EN		(1 << 11)
+#define  BIOS_RLS		(1 <<  7)
+#define  SWSMI_TMR_EN		(1 <<  6)
+#define  APMC_EN		(1 <<  5)
+#define  SLP_SMI_EN		(1 <<  4)
+#define  LEGACY_USB_EN		(1 <<  3)
+#define  BIOS_EN		(1 <<  2)
+#define  EOS			(1 <<  1)
+#define  GBL_SMI_EN		(1 <<  0)
+#define SMI_STS			0x34
+#define UPWRC			0x3c
+#define  UPWRC_WS		(1 << 8)
+#define  UPWRC_WE		(1 << 1)
+#define  UPWRC_SMI		(1 << 0)
+#define GPE_CNTL		0x42
+#define  SWGPE_CTRL		(1 << 1)
+#define DEVACT_STS		0x44
+#define PM2_CNT			0x50
+#define TCO1_CNT		0x60
+#define  TCO_TMR_HLT		(1 << 11)
+#define TCO1_STS		0x64
+#define  DMISCI_STS		(1 << 9)
+#define TCO2_STS		0x66
+#define  TCO2_STS_SECOND_TO	(1 << 1)
+
+#define GPE0_REG_MAX		4
+#define GPE0_REG_SIZE		32
+#define GPE0_STS(x)		(0x80 + (x * 4))
+#define  GPE_31_0		0	/* 0x80/0x90 = GPE[31:0] */
+#define  GPE_63_32		1	/* 0x84/0x94 = GPE[63:32] */
+#define  GPE_94_64		2	/* 0x88/0x98 = GPE[94:64] */
+#define  GPE_STD		3	/* 0x8c/0x9c = Standard GPE */
+#define   WADT_STS		(1 << 18)
+#define   GP27_STS		(1 << 16)
+#define   PME_B0_STS		(1 << 13)
+#define   ME_SCI_STS		(1 << 12)
+#define   PME_STS		(1 << 11)
+#define   BATLOW_STS		(1 << 10)
+#define   PCI_EXP_STS		(1 << 9)
+#define   SMB_WAK_STS		(1 << 7)
+#define   TCOSCI_STS		(1 << 6)
+#define   SWGPE_STS		(1 << 2)
+#define   HOT_PLUG_STS		(1 << 1)
+#define GPE0_EN(x)		(0x90 + (x * 4))
+#define   WADT_en		(1 << 18)
+#define   GP27_EN		(1 << 16)
+#define   PME_B0_EN		(1 << 13)
+#define   ME_SCI_EN		(1 << 12)
+#define   PME_EN		(1 << 11)
+#define   BATLOW_EN		(1 << 10)
+#define   PCI_EXP_EN		(1 << 9)
+#define   TCOSCI_EN		(1 << 6)
+#define   SWGPE_EN		(1 << 2)
+#define   HOT_PLUG_EN		(1 << 1)
+
+#define MAINBOARD_POWER_OFF	0
+#define MAINBOARD_POWER_ON	1
+#define MAINBOARD_POWER_KEEP	2
+
+#define SLEEP_STATE_S0		0
+#define SLEEP_STATE_S3		3
+#define SLEEP_STATE_S5		5
+
+struct chipset_power_state {
+	uint16_t pm1_sts;
+	uint16_t pm1_en;
+	uint32_t pm1_cnt;
+	uint16_t tco1_sts;
+	uint16_t tco2_sts;
+	uint32_t gpe0_sts[4];
+	uint32_t gpe0_en[4];
+	uint16_t gen_pmcon1;
+	uint16_t gen_pmcon2;
+	uint16_t gen_pmcon3;
+	int prev_sleep_state;
+	uint16_t hsio_version;
+	uint16_t hsio_checksum;
+};
+
+void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps);
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/rcb.h b/arch/x86/include/asm/arch-broadwell/rcb.h
new file mode 100644
index 0000000..b7ce874
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/rcb.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __asm_arch_rcba_h
+#define __asm_arch_rcba_h
+
+#define ACPIIRQEN	0x31e0	/* 32bit */
+
+#define PMSYNC_CONFIG	0x33c4	/* 32bit */
+#define PMSYNC_CONFIG2	0x33cc	/* 32bit */
+
+#define DEEP_S3_POL	0x3328	/* 32bit */
+#define  DEEP_S3_EN_AC		(1 << 0)
+#define  DEEP_S3_EN_DC		(1 << 1)
+#define DEEP_S5_POL	0x3330	/* 32bit */
+#define  DEEP_S5_EN_AC		(1 << 14)
+#define  DEEP_S5_EN_DC		(1 << 15)
+#define DEEP_SX_CONFIG	0x3334	/* 32bit */
+#define  DEEP_SX_WAKE_PIN_EN	(1 << 2)
+#define  DEEP_SX_ACPRESENT_PD	(1 << 1)
+#define  DEEP_SX_GP27_PIN_EN	(1 << 0)
+#define PMSYNC_CONFIG	0x33c4	/* 32bit */
+#define PMSYNC_CONFIG2	0x33cc	/* 32bit */
+
+#define RC		0x3400	/* 32bit */
+#define HPTC		0x3404	/* 32bit */
+#define GCS		0x3410	/* 32bit */
+#define BUC		0x3414	/* 32bit */
+#define PCH_DISABLE_GBE		(1 << 5)
+#define FD		0x3418	/* 32bit */
+#define FDSW		0x3420	/* 8bit */
+#define DISPBDF		0x3424  /* 16bit */
+#define FD2		0x3428	/* 32bit */
+#define CG		0x341c	/* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS	(1 << 0)
+#define PCH_DISABLE_ADSPD	(1 << 1)
+#define PCH_DISABLE_SATA1	(1 << 2)
+#define PCH_DISABLE_SMBUS	(1 << 3)
+#define PCH_DISABLE_HD_AUDIO	(1 << 4)
+#define PCH_DISABLE_EHCI2	(1 << 13)
+#define PCH_DISABLE_LPC		(1 << 14)
+#define PCH_DISABLE_EHCI1	(1 << 15)
+#define PCH_DISABLE_PCIE(x)	(1 << (16 + x))
+#define PCH_DISABLE_THERMAL	(1 << 24)
+#define PCH_DISABLE_SATA2	(1 << 25)
+#define PCH_DISABLE_XHCI	(1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT		(1 << 4)
+#define PCH_DISABLE_IDER	(1 << 3)
+#define PCH_DISABLE_MEI2	(1 << 2)
+#define PCH_DISABLE_MEI1	(1 << 1)
+#define PCH_ENABLE_DBDF		(1 << 0)
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/serialio.h b/arch/x86/include/asm/arch-broadwell/serialio.h
new file mode 100644
index 0000000..5e98eaf
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/serialio.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Serial IO defintiions (taken from coreboot file of same name)
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __ARCH_BROADWELL_SERIALIO_H_
+#define __ARCH_BROADWELL_SERIALIO_H_
+
+/* Serial IO IOBP Registers */
+#define SIO_IOBP_PORTCTRL0	0xcb000000	/* SDIO D23:F0 */
+#define  SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN		BIT(5)
+#define  SIO_IOBP_PORTCTRL0_PCI_CONF_DIS	BIT(4)
+#define SIO_IOBP_PORTCTRL1	0xcb000014	/* SDIO D23:F0 */
+#define  SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x)	(((x) & 3) << 13)
+#define SIO_IOBP_GPIODF		0xcb000154
+#define  SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN	BIT(4)
+#define  SIO_IOBP_GPIODF_DMA_IDLE_DET_EN	BIT(3)
+#define  SIO_IOBP_GPIODF_UART_IDLE_DET_EN	BIT(2)
+#define  SIO_IOBP_GPIODF_I2C_IDLE_DET_EN	BIT(1)
+#define  SIO_IOBP_GPIODF_SPI_IDLE_DET_EN	BIT(0)
+#define  SIO_IOBP_GPIODF_UART0_BYTE_ACCESS	BIT(10)
+#define  SIO_IOBP_GPIODF_UART1_BYTE_ACCESS	BIT(11)
+#define SIO_IOBP_PORTCTRL2	0xcb000240	/* DMA D21:F0 */
+#define SIO_IOBP_PORTCTRL3	0xcb000248	/* I2C0 D21:F1 */
+#define SIO_IOBP_PORTCTRL4	0xcb000250	/* I2C1 D21:F2 */
+#define SIO_IOBP_PORTCTRL5	0xcb000258	/* SPI0 D21:F3 */
+#define SIO_IOBP_PORTCTRL6	0xcb000260	/* SPI1 D21:F4 */
+#define SIO_IOBP_PORTCTRL7	0xcb000268	/* UART0 D21:F5 */
+#define SIO_IOBP_PORTCTRL8	0xcb000270	/* UART1 D21:F6 */
+#define SIO_IOBP_PORTCTRLX(x)	(0xcb000240 + ((x) * 8))
+/* PORTCTRL 2-8 have the same layout */
+#define  SIO_IOBP_PORTCTRL_ACPI_IRQ_EN		BIT(21)
+#define  SIO_IOBP_PORTCTRL_PCI_CONF_DIS		BIT(20)
+#define  SIO_IOBP_PORTCTRL_SNOOP_SELECT(x)	(((x) & 3) << 18)
+#define  SIO_IOBP_PORTCTRL_INT_PIN(x)		(((x) & 0xf) << 2)
+#define  SIO_IOBP_PORTCTRL_PM_CAP_PRSNT		BIT(1)
+#define SIO_IOBP_FUNCDIS0	0xce00aa07	/* DMA D21:F0 */
+#define SIO_IOBP_FUNCDIS1	0xce00aa47	/* I2C0 D21:F1 */
+#define SIO_IOBP_FUNCDIS2	0xce00aa87	/* I2C1 D21:F2 */
+#define SIO_IOBP_FUNCDIS3	0xce00aac7	/* SPI0 D21:F3 */
+#define SIO_IOBP_FUNCDIS4	0xce00ab07	/* SPI1 D21:F4 */
+#define SIO_IOBP_FUNCDIS5	0xce00ab47	/* UART0 D21:F5 */
+#define SIO_IOBP_FUNCDIS6	0xce00ab87	/* UART1 D21:F6 */
+#define SIO_IOBP_FUNCDIS7	0xce00ae07	/* SDIO D23:F0 */
+#define  SIO_IOBP_FUNCDIS_DIS			BIT(8)
+
+/* Serial IO Devices */
+#define SIO_ID_SDMA		0 /* D21:F0 */
+#define SIO_ID_I2C0		1 /* D21:F1 */
+#define SIO_ID_I2C1		2 /* D21:F2 */
+#define SIO_ID_SPI0		3 /* D21:F3 */
+#define SIO_ID_SPI1		4 /* D21:F4 */
+#define SIO_ID_UART0		5 /* D21:F5 */
+#define SIO_ID_UART1		6 /* D21:F6 */
+#define SIO_ID_SDIO		7 /* D23:F0 */
+
+#define SIO_REG_PPR_CLOCK		0x800
+#define  SIO_REG_PPR_CLOCK_EN		 BIT(0)
+#define  SIO_REG_PPR_CLOCK_UPDATE	 BIT(31)
+#define  SIO_REG_PPR_CLOCK_M_DIV	 0x25a
+#define  SIO_REG_PPR_CLOCK_N_DIV	 0x7fff
+#define SIO_REG_PPR_RST			0x804
+#define  SIO_REG_PPR_RST_ASSERT		 0x3
+#define SIO_REG_PPR_GEN			0x808
+#define  SIO_REG_PPR_GEN_LTR_MODE_MASK	 BIT(2)
+#define  SIO_REG_PPR_GEN_VOLTAGE_MASK	 BIT(3)
+#define  SIO_REG_PPR_GEN_VOLTAGE(x)	 ((x & 1) << 3)
+#define SIO_REG_AUTO_LTR		0x814
+
+#define SIO_REG_SDIO_PPR_GEN		0x1008
+#define SIO_REG_SDIO_PPR_SW_LTR		0x1010
+#define SIO_REG_SDIO_PPR_CMD12		0x3c
+#define  SIO_REG_SDIO_PPR_CMD12_B30	 BIT(30)
+
+#define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */
+#define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */
+#define SIO_PIN_INTC 3 /* IRQ7 in ACPI mode */
+#define SIO_PIN_INTD 4 /* IRQ13 in ACPI mode */
+
+#endif /* __ARCH_BROADWELL_SERIALIO_H_ */
diff --git a/arch/x86/include/asm/arch-broadwell/spi.h b/arch/x86/include/asm/arch-broadwell/spi.h
new file mode 100644
index 0000000..7820998
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/spi.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This file is from coreboot soc/intel/broadwell/include/soc/spi.h
+ */
+
+#ifndef _BROADWELL_SPI_H_
+#define _BROADWELL_SPI_H_
+
+/*
+ * SPI Opcode Menu setup for SPIBAR lockdown
+ * should support most common flash chips.
+ */
+
+#define SPIBAR_OFFSET		0x3800
+#define SPI_REG(x)		(RCB_REG(SPIBAR_OFFSET + (x)))
+
+/* Reigsters within the SPIBAR */
+#define SPIBAR_SSFC		0x91
+#define SPIBAR_FDOC		0xb0
+#define SPIBAR_FDOD		0xb4
+
+#define SPIBAR_PREOP		0x94
+#define SPIBAR_OPTYPE		0x96
+#define SPIBAR_OPMENU_LOWER	0x98
+#define SPIBAR_OPMENU_UPPER	0x9c
+
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+			  (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+			  (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
+
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) |  \
+		    (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) |	  \
+		    (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+
+#define SPIBAR_HSFS                 0x04   /* SPI hardware sequence status */
+#define  SPIBAR_HSFS_FLOCKDN        (1 << 15)/* Flash Configuration Lock-Down */
+#define  SPIBAR_HSFS_SCIP           (1 << 5) /* SPI Cycle In Progress */
+#define  SPIBAR_HSFS_AEL            (1 << 2) /* SPI Access Error Log */
+#define  SPIBAR_HSFS_FCERR          (1 << 1) /* SPI Flash Cycle Error */
+#define  SPIBAR_HSFS_FDONE          (1 << 0) /* SPI Flash Cycle Done */
+#define SPIBAR_HSFC                 0x06   /* SPI hardware sequence control */
+#define  SPIBAR_HSFC_BYTE_COUNT(c)  (((c - 1) & 0x3f) << 8)
+#define  SPIBAR_HSFC_CYCLE_READ     (0 << 1) /* Read cycle */
+#define  SPIBAR_HSFC_CYCLE_WRITE    (2 << 1) /* Write cycle */
+#define  SPIBAR_HSFC_CYCLE_ERASE    (3 << 1) /* Erase cycle */
+#define  SPIBAR_HSFC_GO             (1 << 0) /* GO: start SPI transaction */
+#define SPIBAR_FADDR                0x08   /* SPI flash address */
+#define SPIBAR_FDATA(n)             (0x10 + (4 * n)) /* SPI flash data */
+#define SPIBAR_SSFS                 0x90
+#define  SPIBAR_SSFS_ERROR          (1 << 3)
+#define  SPIBAR_SSFS_DONE           (1 << 2)
+#define SPIBAR_SSFC                 0x91
+#define  SPIBAR_SSFC_DATA           (1 << 14)
+#define  SPIBAR_SSFC_GO             (1 << 1)
+
+#endif
diff --git a/arch/x86/include/asm/arch-coreboot/sysinfo.h b/arch/x86/include/asm/arch-coreboot/sysinfo.h
new file mode 100644
index 0000000..dd8d1cb
--- /dev/null
+++ b/arch/x86/include/asm/arch-coreboot/sysinfo.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ */
+
+#ifndef _COREBOOT_SYSINFO_H
+#define _COREBOOT_SYSINFO_H
+
+#include <asm/coreboot_tables.h>
+
+/* Maximum number of memory range definitions */
+#define SYSINFO_MAX_MEM_RANGES	32
+/* Allow a maximum of 8 GPIOs */
+#define SYSINFO_MAX_GPIOS	8
+
+struct sysinfo_t {
+	int n_memranges;
+	struct memrange {
+		unsigned long long base;
+		unsigned long long size;
+		unsigned int type;
+	} memrange[SYSINFO_MAX_MEM_RANGES];
+
+	u32 cmos_range_start;
+	u32 cmos_range_end;
+	u32 cmos_checksum_location;
+	u32 vbnv_start;
+	u32 vbnv_size;
+
+	char *version;
+	char *extra_version;
+	char *build;
+	char *compile_time;
+	char *compile_by;
+	char *compile_host;
+	char *compile_domain;
+	char *compiler;
+	char *linker;
+	char *assembler;
+
+	struct cb_framebuffer *framebuffer;
+
+	int num_gpios;
+	struct cb_gpio gpios[SYSINFO_MAX_GPIOS];
+
+	void	*vdat_addr;
+	u32	vdat_size;
+	void	*tstamp_table;
+	void	*cbmem_cons;
+
+	struct cb_serial *serial;
+};
+
+extern struct sysinfo_t lib_sysinfo;
+
+int get_coreboot_info(struct sysinfo_t *info);
+
+#endif
diff --git a/arch/x86/include/asm/arch-coreboot/timestamp.h b/arch/x86/include/asm/arch-coreboot/timestamp.h
new file mode 100644
index 0000000..9320afb
--- /dev/null
+++ b/arch/x86/include/asm/arch-coreboot/timestamp.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ */
+
+#ifndef __COREBOOT_TIMESTAMP_H__
+#define __COREBOOT_TIMESTAMP_H__
+
+enum timestamp_id {
+	/* coreboot specific timestamp IDs */
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_CBMEM_POST = 75,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
+
+	/* U-Boot entry IDs start at 1000 */
+	TS_U_BOOT_INITTED = 1000, /* This is where u-boot starts */
+	TS_U_BOOT_START_KERNEL = 1100, /* Right before jumping to kernel. */
+};
+
+void timestamp_init(void);
+void timestamp_add(enum timestamp_id id, uint64_t ts_time);
+void timestamp_add_now(enum timestamp_id id);
+
+/**
+ * timestamp_add_to_bootstage - Add important coreboot timestamps to bootstage
+ *
+ * @return 0 if ok, -1 if no timestamps were found
+ */
+int timestamp_add_to_bootstage(void);
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
new file mode 100644
index 0000000..ae9105b
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct platform_config {
+	u8 enable_ht;
+	u8 enable_turbo;
+	u8 enable_memory_down;
+	u8 enable_fast_boot;
+};
+
+/*
+ * Dummy structure for now as currently only SPD is verified in U-Boot.
+ *
+ * We can add the missing parameters when adding support on a board with
+ * memory down configuration.
+ */
+struct memory_config {
+	u8 dummy;
+};
+
+struct fsp_config_data {
+	struct fsp_cfg_common common;
+	struct platform_config plat_config;
+	struct memory_config mem_config;
+};
+
+struct fspinit_rtbuf {
+	u32 stack_top;
+	u32 boot_mode;
+	struct platform_config *plat_config;
+	struct memory_config *mem_config;
+};
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
new file mode 100644
index 0000000..4b0f23a
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_VPD_H__
+#define __FSP_VPD_H__
+
+/* IvyBridge FSP does not support VPD/UPD */
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h
new file mode 100644
index 0000000..518c308
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/me.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/me.h
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ */
+
+#ifndef _ASM_INTEL_ME_H
+#define _ASM_INTEL_ME_H
+
+#include <asm/me_common.h>
+
+struct __packed mbp_fw_version_name {
+	u32 major_version:16;
+	u32 minor_version:16;
+	u32 hotfix_version:16;
+	u32 build_version:16;
+};
+
+struct __packed mbp_icc_profile {
+	u8 num_icc_profiles;
+	u8 icc_profile_soft_strap;
+	u8 icc_profile_index;
+	u8 reserved;
+	u32 register_lock_mask[3];
+};
+
+struct __packed platform_type_rule_data {
+	u32 platform_target_usage_type:4;
+	u32 platform_target_market_type:2;
+	u32 super_sku:1;
+	u32 reserved:1;
+	u32 intel_me_fw_image_type:4;
+	u32 platform_brand:4;
+	u32 reserved_1:16;
+};
+
+struct __packed mbp_fw_caps {
+	struct mefwcaps_sku fw_capabilities;
+	u8 available;
+};
+
+struct __packed mbp_plat_type {
+	struct platform_type_rule_data rule_data;
+	u8 available;
+};
+
+struct __packed me_bios_payload {
+	struct mbp_fw_version_name fw_version_name;
+	struct mbp_fw_caps fw_caps_sku;
+	struct mbp_rom_bist_data rom_bist_data;
+	struct mbp_platform_key platform_key;
+	struct mbp_plat_type fw_plat_type;
+	struct mbp_icc_profile icc_profile;
+	struct tdt_state_info at_state;
+	u32 mfsintegrity;
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
new file mode 100644
index 0000000..4839ebc
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.
+ */
+
+#ifndef _ASM_ARCH_MODEL_206AX_H
+#define _ASM_ARCH_MODEL_206AX_H
+
+#define  CPUID_VMX			(1 << 5)
+#define  CPUID_SMX			(1 << 6)
+#define MSR_FEATURE_CONFIG		0x13c
+#define IA32_PLATFORM_DCA_CAP		0x1f8
+#define IA32_MISC_ENABLE		0x1a0
+#define MSR_TEMPERATURE_TARGET		0x1a2
+#define IA32_THERM_INTERRUPT		0x19b
+#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
+#define  ENERGY_POLICY_PERFORMANCE	0
+#define  ENERGY_POLICY_NORMAL		6
+#define  ENERGY_POLICY_POWERSAVE	15
+#define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
+#define MSR_LT_LOCK_MEMORY		0x2e7
+#define IA32_MC0_STATUS		0x401
+
+#define MSR_MISC_PWR_MGMT		0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
+
+#define MSR_PKGC3_IRTL			0x60a
+#define MSR_PKGC6_IRTL			0x60b
+#define MSR_PKGC7_IRTL			0x60c
+#define  IRTL_VALID			(1 << 15)
+#define  IRTL_1_NS			(0 << 10)
+#define  IRTL_32_NS			(1 << 10)
+#define  IRTL_1024_NS			(2 << 10)
+#define  IRTL_32768_NS			(3 << 10)
+#define  IRTL_1048576_NS		(4 << 10)
+#define  IRTL_33554432_NS		(5 << 10)
+#define  IRTL_RESPONSE_MASK		(0x3ff)
+
+#define MSR_PP0_CURRENT_CONFIG		0x601
+#define  PP0_CURRENT_LIMIT		(112 << 3) /* 112 A */
+#define MSR_PP1_CURRENT_CONFIG		0x602
+#define  PP1_CURRENT_LIMIT_SNB		(35 << 3) /* 35 A */
+#define  PP1_CURRENT_LIMIT_IVB		(50 << 3) /* 50 A */
+#define MSR_PKG_POWER_SKU		0x614
+
+#define IVB_CONFIG_TDP_MIN_CPUID	0x306a2
+#define MSR_CONFIG_TDP_LEVEL1		0x649
+#define MSR_CONFIG_TDP_LEVEL2		0x64a
+#define MSR_CONFIG_TDP_CONTROL		0x64b
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES			8
+#define PSS_RATIO_STEP			2
+#define PSS_LATENCY_TRANSITION		10
+#define PSS_LATENCY_BUSMASTER		10
+
+/* Configure power limits for turbo mode */
+void set_power_limits(u8 power_limit_1_time);
+bool cpu_ivybridge_config_tdp_levels(void);
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
new file mode 100644
index 0000000..8018bc0
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -0,0 +1,398 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot src/southbridge/intel/bd82x6x/pch.h
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors.  All rights reserved.
+ */
+
+#ifndef _ASM_ARCH_PCH_H
+#define _ASM_ARCH_PCH_H
+
+#include <pci.h>
+
+/* PCH types */
+#define PCH_TYPE_CPT	0x1c /* CougarPoint */
+#define PCH_TYPE_PPT	0x1e /* IvyBridge */
+
+/* PCH stepping values for LPC device */
+#define PCH_STEP_A0	0
+#define PCH_STEP_A1	1
+#define PCH_STEP_B0	2
+#define PCH_STEP_B1	3
+#define PCH_STEP_B2	4
+#define PCH_STEP_B3	5
+#define DEFAULT_GPIOBASE	0x0480
+#define DEFAULT_PMBASE		0x0500
+
+#define SMBUS_IO_BASE		0x0400
+
+#define MAINBOARD_POWER_OFF	0
+#define MAINBOARD_POWER_ON	1
+#define MAINBOARD_POWER_KEEP	2
+
+/* PCI Configuration Space (D30:F0): PCI2PCI */
+#define PSTS	0x06
+#define SMLT	0x1b
+#define SECSTS	0x1e
+#define INTR	0x3c
+#define BCTRL	0x3e
+#define   SBR	(1 << 6)
+#define   SEE	(1 << 1)
+#define   PERE	(1 << 0)
+
+#define PCH_EHCI1_DEV		PCI_BDF(0, 0x1d, 0)
+#define PCH_EHCI2_DEV		PCI_BDF(0, 0x1a, 0)
+#define PCH_XHCI_DEV		PCI_BDF(0, 0x14, 0)
+#define PCH_ME_DEV		PCI_BDF(0, 0x16, 0)
+#define PCH_PCIE_DEV_SLOT	28
+
+#define PCH_DEV			PCI_BDF(0, 0, 0)
+#define PCH_VIDEO_DEV		PCI_BDF(0, 2, 0)
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEV		PCI_BDF(0, 0x1f, 0)
+#define SERIRQ_CNTL		0x64
+
+#define GEN_PMCON_1		0xa0
+#define GEN_PMCON_2		0xa2
+#define GEN_PMCON_3		0xa4
+#define ETR3			0xac
+#define  ETR3_CWORWRE		(1 << 18)
+#define  ETR3_CF9GR		(1 << 20)
+
+/* GEN_PMCON_3 bits */
+#define RTC_BATTERY_DEAD	(1 << 2)
+#define RTC_POWER_FAILED	(1 << 1)
+#define SLEEP_AFTER_POWER_FAIL	(1 << 0)
+
+#define BIOS_CNTL		0xDC
+#define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
+#define GPIO_ROUT		0xb8
+
+#define PIRQA_ROUT		0x60
+#define PIRQB_ROUT		0x61
+#define PIRQC_ROUT		0x62
+#define PIRQD_ROUT		0x63
+#define PIRQE_ROUT		0x68
+#define PIRQF_ROUT		0x69
+#define PIRQG_ROUT		0x6A
+#define PIRQH_ROUT		0x6B
+
+#define GEN_PMCON_1		0xa0
+#define GEN_PMCON_2		0xa2
+#define GEN_PMCON_3		0xa4
+#define ETR3			0xac
+#define  ETR3_CWORWRE		(1 << 18)
+#define  ETR3_CF9GR		(1 << 20)
+
+#define PMBASE			0x40
+#define ACPI_CNTL		0x44
+#define BIOS_CNTL		0xDC
+#define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
+#define GPIO_ROUT		0xb8
+
+/* PCI Configuration Space (D31:F1): IDE */
+#define PCH_IDE_DEV		PCI_BDF(0, 0x1f, 1)
+#define PCH_SATA_DEV		PCI_BDF(0, 0x1f, 2)
+#define PCH_SATA2_DEV		PCI_BDF(0, 0x1f, 5)
+
+#define IDE_SDMA_CNT		0x48	/* Synchronous DMA control */
+#define   IDE_SSDE1		(1 <<  3)
+#define   IDE_SSDE0		(1 <<  2)
+#define   IDE_PSDE1		(1 <<  1)
+#define   IDE_PSDE0		(1 <<  0)
+
+#define IDE_SDMA_TIM		0x4a
+
+#define IDE_CONFIG		0x54	/* IDE I/O Configuration Register */
+#define   SIG_MODE_SEC_NORMAL	(0 << 18)
+#define   SIG_MODE_SEC_TRISTATE	(1 << 18)
+#define   SIG_MODE_SEC_DRIVELOW	(2 << 18)
+#define   SIG_MODE_PRI_NORMAL	(0 << 16)
+#define   SIG_MODE_PRI_TRISTATE	(1 << 16)
+#define   SIG_MODE_PRI_DRIVELOW	(2 << 16)
+#define   FAST_SCB1		(1 << 15)
+#define   FAST_SCB0		(1 << 14)
+#define   FAST_PCB1		(1 << 13)
+#define   FAST_PCB0		(1 << 12)
+#define   SCB1			(1 <<  3)
+#define   SCB0			(1 <<  2)
+#define   PCB1			(1 <<  1)
+#define   PCB0			(1 <<  0)
+
+#define SATA_SIRI		0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD		0xa4 /* SATA Indexed Register Data */
+#define SATA_SP			0xd0 /* Scratchpad */
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0G3IR	0xea000151
+#define SATA_IOBP_SP1G3IR	0xea000051
+
+#define VCH		0x0000	/* 32bit */
+#define VCAP1		0x0004	/* 32bit */
+#define VCAP2		0x0008	/* 32bit */
+#define PVC		0x000c	/* 16bit */
+#define PVS		0x000e	/* 16bit */
+
+#define V0CAP		0x0010	/* 32bit */
+#define V0CTL		0x0014	/* 32bit */
+#define V0STS		0x001a	/* 16bit */
+
+#define V1CAP		0x001c	/* 32bit */
+#define V1CTL		0x0020	/* 32bit */
+#define V1STS		0x0026	/* 16bit */
+
+#define RCTCL		0x0100	/* 32bit */
+#define ESD		0x0104	/* 32bit */
+#define ULD		0x0110	/* 32bit */
+#define ULBA		0x0118	/* 64bit */
+
+#define RP1D		0x0120	/* 32bit */
+#define RP1BA		0x0128	/* 64bit */
+#define RP2D		0x0130	/* 32bit */
+#define RP2BA		0x0138	/* 64bit */
+#define RP3D		0x0140	/* 32bit */
+#define RP3BA		0x0148	/* 64bit */
+#define RP4D		0x0150	/* 32bit */
+#define RP4BA		0x0158	/* 64bit */
+#define HDD		0x0160	/* 32bit */
+#define HDBA		0x0168	/* 64bit */
+#define RP5D		0x0170	/* 32bit */
+#define RP5BA		0x0178	/* 64bit */
+#define RP6D		0x0180	/* 32bit */
+#define RP6BA		0x0188	/* 64bit */
+
+#define RPC		0x0400	/* 32bit */
+#define RPFN		0x0404	/* 32bit */
+
+#define TRSR		0x1e00	/*  8bit */
+#define TRCR		0x1e10	/* 64bit */
+#define TWDR		0x1e18	/* 64bit */
+
+#define IOTR0		0x1e80	/* 64bit */
+#define IOTR1		0x1e88	/* 64bit */
+#define IOTR2		0x1e90	/* 64bit */
+#define IOTR3		0x1e98	/* 64bit */
+
+#define TCTL		0x3000	/*  8bit */
+
+#define NOINT		0
+#define INTA		1
+#define INTB		2
+#define INTC		3
+#define INTD		4
+
+#define DIR_IDR		12	/* Interrupt D Pin Offset */
+#define DIR_ICR		8	/* Interrupt C Pin Offset */
+#define DIR_IBR		4	/* Interrupt B Pin Offset */
+#define DIR_IAR		0	/* Interrupt A Pin Offset */
+
+#define PIRQA		0
+#define PIRQB		1
+#define PIRQC		2
+#define PIRQD		3
+#define PIRQE		4
+#define PIRQF		5
+#define PIRQG		6
+#define PIRQH		7
+
+/* IO Buffer Programming */
+#define IOBPIRI		0x2330
+#define IOBPD		0x2334
+#define IOBPS		0x2338
+#define  IOBPS_RW_BX    ((1 << 9)|(1 << 10))
+#define  IOBPS_WRITE_AX	((1 << 9)|(1 << 10))
+#define  IOBPS_READ_AX	((1 << 8)|(1 << 9)|(1 << 10))
+
+#define D31IP		0x3100	/* 32bit */
+#define D31IP_TTIP	24	/* Thermal Throttle Pin */
+#define D31IP_SIP2	20	/* SATA Pin 2 */
+#define D31IP_SMIP	12	/* SMBUS Pin */
+#define D31IP_SIP	8	/* SATA Pin */
+#define D30IP		0x3104	/* 32bit */
+#define D30IP_PIP	0	/* PCI Bridge Pin */
+#define D29IP		0x3108	/* 32bit */
+#define D29IP_E1P	0	/* EHCI #1 Pin */
+#define D28IP		0x310c	/* 32bit */
+#define D28IP_P8IP	28	/* PCI Express Port 8 */
+#define D28IP_P7IP	24	/* PCI Express Port 7 */
+#define D28IP_P6IP	20	/* PCI Express Port 6 */
+#define D28IP_P5IP	16	/* PCI Express Port 5 */
+#define D28IP_P4IP	12	/* PCI Express Port 4 */
+#define D28IP_P3IP	8	/* PCI Express Port 3 */
+#define D28IP_P2IP	4	/* PCI Express Port 2 */
+#define D28IP_P1IP	0	/* PCI Express Port 1 */
+#define D27IP		0x3110	/* 32bit */
+#define D27IP_ZIP	0	/* HD Audio Pin */
+#define D26IP		0x3114	/* 32bit */
+#define D26IP_E2P	0	/* EHCI #2 Pin */
+#define D25IP		0x3118	/* 32bit */
+#define D25IP_LIP	0	/* GbE LAN Pin */
+#define D22IP		0x3124	/* 32bit */
+#define D22IP_KTIP	12	/* KT Pin */
+#define D22IP_IDERIP	8	/* IDE-R Pin */
+#define D22IP_MEI2IP	4	/* MEI #2 Pin */
+#define D22IP_MEI1IP	0	/* MEI #1 Pin */
+#define D20IP		0x3128  /* 32bit */
+#define D20IP_XHCIIP	0
+#define D31IR		0x3140	/* 16bit */
+#define D30IR		0x3142	/* 16bit */
+#define D29IR		0x3144	/* 16bit */
+#define D28IR		0x3146	/* 16bit */
+#define D27IR		0x3148	/* 16bit */
+#define D26IR		0x314c	/* 16bit */
+#define D25IR		0x3150	/* 16bit */
+#define D22IR		0x315c	/* 16bit */
+#define D20IR		0x3160	/* 16bit */
+#define OIC		0x31fe	/* 16bit */
+
+#define SPI_FREQ_SWSEQ	0x3893
+#define SPI_DESC_COMP0	0x38b0
+#define SPI_FREQ_WR_ERA	0x38b4
+
+#define DIR_ROUTE(a, b, c, d) \
+		(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+			((b) << DIR_IBR) | ((a) << DIR_IAR))
+
+#define HPTC		0x3404	/* 32bit */
+#define BUC		0x3414	/* 32bit */
+#define PCH_DISABLE_GBE		(1 << 5)
+#define FD		0x3418	/* 32bit */
+#define DISPBDF		0x3424  /* 16bit */
+#define FD2		0x3428	/* 32bit */
+#define CG		0x341c	/* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS	((1 << 0)|(1 << 26))
+#define PCH_DISABLE_P2P		(1 << 1)
+#define PCH_DISABLE_SATA1	(1 << 2)
+#define PCH_DISABLE_SMBUS	(1 << 3)
+#define PCH_DISABLE_HD_AUDIO	(1 << 4)
+#define PCH_DISABLE_EHCI2	(1 << 13)
+#define PCH_DISABLE_LPC		(1 << 14)
+#define PCH_DISABLE_EHCI1	(1 << 15)
+#define PCH_DISABLE_PCIE(x)	(1 << (16 + x))
+#define PCH_DISABLE_THERMAL	(1 << 24)
+#define PCH_DISABLE_SATA2	(1 << 25)
+#define PCH_DISABLE_XHCI	(1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT		(1 << 4)
+#define PCH_DISABLE_IDER	(1 << 3)
+#define PCH_DISABLE_MEI2	(1 << 2)
+#define PCH_DISABLE_MEI1	(1 << 1)
+#define PCH_ENABLE_DBDF		(1 << 0)
+
+/* ICH7 GPIOBASE */
+#define GPIO_USE_SEL	0x00
+#define GP_IO_SEL	0x04
+#define GP_LVL		0x0c
+#define GPO_BLINK	0x18
+#define GPI_INV		0x2c
+#define GPIO_USE_SEL2	0x30
+#define GP_IO_SEL2	0x34
+#define GP_LVL2		0x38
+#define GPIO_USE_SEL3	0x40
+#define GP_IO_SEL3	0x44
+#define GP_LVL3		0x48
+#define GP_RST_SEL1	0x60
+#define GP_RST_SEL2	0x64
+#define GP_RST_SEL3	0x68
+
+/* ICH7 PMBASE */
+#define PM1_STS		0x00
+#define   WAK_STS	(1 << 15)
+#define   PCIEXPWAK_STS	(1 << 14)
+#define   PRBTNOR_STS	(1 << 11)
+#define   RTC_STS	(1 << 10)
+#define   PWRBTN_STS	(1 << 8)
+#define   GBL_STS	(1 << 5)
+#define   BM_STS	(1 << 4)
+#define   TMROF_STS	(1 << 0)
+#define PM1_EN		0x02
+#define   PCIEXPWAK_DIS	(1 << 14)
+#define   RTC_EN	(1 << 10)
+#define   PWRBTN_EN	(1 << 8)
+#define   GBL_EN	(1 << 5)
+#define   TMROF_EN	(1 << 0)
+#define PM1_CNT		0x04
+#define   SLP_EN	(1 << 13)
+#define   SLP_TYP	(7 << 10)
+#define    SLP_TYP_S0	0
+#define    SLP_TYP_S1	1
+#define    SLP_TYP_S3	5
+#define    SLP_TYP_S4	6
+#define    SLP_TYP_S5	7
+#define   GBL_RLS	(1 << 2)
+#define   BM_RLD	(1 << 1)
+#define   SCI_EN	(1 << 0)
+#define PM1_TMR		0x08
+#define PROC_CNT	0x10
+#define LV2		0x14
+#define LV3		0x15
+#define LV4		0x16
+#define PM2_CNT		0x50 /* mobile only */
+#define GPE0_STS	0x20
+#define   PME_B0_STS	(1 << 13)
+#define   PME_STS	(1 << 11)
+#define   BATLOW_STS	(1 << 10)
+#define   PCI_EXP_STS	(1 << 9)
+#define   RI_STS	(1 << 8)
+#define   SMB_WAK_STS	(1 << 7)
+#define   TCOSCI_STS	(1 << 6)
+#define   SWGPE_STS	(1 << 2)
+#define   HOT_PLUG_STS	(1 << 1)
+#define GPE0_EN		0x28
+#define   PME_B0_EN	(1 << 13)
+#define   PME_EN	(1 << 11)
+#define   TCOSCI_EN	(1 << 6)
+#define SMI_EN		0x30
+#define   INTEL_USB2_EN	 (1 << 18) /* Intel-Specific USB2 SMI logic */
+#define   LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
+#define   PERIODIC_EN	 (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
+#define   TCO_EN	 (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
+#define   MCSMI_EN	 (1 << 11) /* Trap microcontroller range access */
+#define   BIOS_RLS	 (1 <<  7) /* asserts SCI on bit set */
+#define   SWSMI_TMR_EN	 (1 <<  6) /* start software smi timer on bit set */
+#define   APMC_EN	 (1 <<  5) /* Writes to APM_CNT cause SMI# */
+#define   SLP_SMI_EN	 (1 <<  4) /* Write SLP_EN in PM1_CNT asserts SMI# */
+#define   LEGACY_USB_EN  (1 <<  3) /* Legacy USB circuit SMI logic */
+#define   BIOS_EN	 (1 <<  2) /* Assert SMI# on setting GBL_RLS bit */
+#define   EOS		 (1 <<  1) /* End of SMI (deassert SMI#) */
+#define   GBL_SMI_EN	 (1 <<  0) /* SMI# generation at all? */
+#define SMI_STS		0x34
+#define ALT_GP_SMI_EN	0x38
+#define ALT_GP_SMI_STS	0x3a
+#define GPE_CNTL	0x42
+#define DEVACT_STS	0x44
+#define SS_CNT		0x50
+#define C3_RES		0x54
+#define TCO1_STS	0x64
+#define   DMISCI_STS	(1 << 9)
+#define TCO2_STS	0x66
+
+/**
+ * pch_silicon_revision() - Read silicon device ID from the PCH
+ *
+ * @dev:	PCH device
+ * @return silicon device ID
+ */
+int pch_silicon_type(struct udevice *dev);
+
+/**
+ * pch_pch_iobp_update() - Update a pch register
+ *
+ * @dev:	PCH device
+ * @address:	Address to update
+ * @andvalue:	Value to AND with existing value
+ * @orvalue:	Value to OR with existing value
+ */
+void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
+			     u32 orvalue);
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/pei_data.h b/arch/x86/include/asm/arch-ivybridge/pei_data.h
new file mode 100644
index 0000000..b8da21b
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/pei_data.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2011, Google Inc.
+ */
+
+#ifndef ASM_ARCH_PEI_DATA_H
+#define ASM_ARCH_PEI_DATA_H
+
+#include <linux/linkage.h>
+
+struct pch_usb3_controller_settings {
+	/* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */
+	uint16_t mode;
+	/* 4 bit mask, 1: switchable, 0: not switchable */
+	uint16_t hs_port_switch_mask;
+	/* 0: No xHCI preOS driver, 1: xHCI preOS driver */
+	uint16_t preboot_support;
+	/* 0: Disable, 1: Enable */
+	uint16_t xhci_streams;
+};
+
+typedef asmlinkage void (*tx_byte_func)(unsigned char byte);
+
+#define PEI_VERSION 6
+
+struct __packed pei_data {
+	uint32_t pei_version;
+	uint32_t mchbar;
+	uint32_t dmibar;
+	uint32_t epbar;
+	uint32_t pciexbar;
+	uint16_t smbusbar;
+	uint32_t wdbbar;
+	uint32_t wdbsize;
+	uint32_t hpet_address;
+	uint32_t rcba;
+	uint32_t pmbase;
+	uint32_t gpiobase;
+	uint32_t thermalbase;
+	uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */
+	uint32_t tseg_size;
+	uint8_t spd_addresses[4];
+	uint8_t ts_addresses[4];
+	int boot_mode;
+	int ec_present;
+	int gbe_enable;
+	/*
+	 * 0 = leave channel enabled
+	 * 1 = disable dimm 0 on channel
+	 * 2 = disable dimm 1 on channel
+	 * 3 = disable dimm 0+1 on channel
+	 */
+	int dimm_channel0_disabled;
+	int dimm_channel1_disabled;
+	/* Seed values saved in CMOS */
+	uint32_t scrambler_seed;
+	uint32_t scrambler_seed_s3;
+	/* Data read from flash and passed into MRC */
+	unsigned char *mrc_input;
+	unsigned int mrc_input_len;
+	/* Data from MRC that should be saved to flash */
+	unsigned char *mrc_output;
+	unsigned int mrc_output_len;
+	/*
+	 * Max frequency DDR3 could be ran at. Could be one of four values:
+	 * 800, 1067, 1333, 1600
+	 */
+	uint32_t max_ddr3_freq;
+	/*
+	 * USB Port Configuration:
+	 *  [0] = enable
+	 *  [1] = overcurrent pin
+	 *  [2] = length
+	 *
+	 * Ports 0-7 can be mapped to OC0-OC3
+	 * Ports 8-13 can be mapped to OC4-OC7
+	 *
+	 * Port Length
+	 *  MOBILE:
+	 *   < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
+	 *   < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude)
+	 *  DESKTOP:
+	 *   < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude)
+	 *   < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude)
+	 *   < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
+	 */
+	uint16_t usb_port_config[16][3];
+	/* See the usb3 struct above for details */
+	struct pch_usb3_controller_settings usb3;
+	/*
+	 * SPD data array for onboard RAM. Specify address 0xf0,
+	 * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
+	 * spd_address for a given "DIMM".
+	 */
+	uint8_t spd_data[4][256];
+	tx_byte_func tx_byte;
+	int ddr3lv_support;
+	/*
+	 * pcie_init needs to be set to 1 to have the system agent initialise
+	 * PCIe. Note: This should only be required if your system has Gen3
+	 * devices and it will increase your boot time by at least 100ms.
+	 */
+	int pcie_init;
+	/*
+	 * N mode functionality. Leave this setting at 0.
+	 * 0 Auto
+	 * 1 1N
+	 * 2 2N
+	 */
+	int nmode;
+	/*
+	 * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows
+	 * for DIMM SPD data to specify whether double-rate is required for
+	 * extended operating temperature range.
+	 * 0 Enable double rate based upon temperature thresholds
+	 * 1 Normal rate
+	 * 2 Always enable double rate
+	 */
+	int ddr_refresh_rate_config;
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
new file mode 100644
index 0000000..a3a507f
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot file of the same name
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ */
+
+#ifndef _ACH_ASM_SANDYBRIDGE_H
+#define _ACH_ASM_SANDYBRIDGE_H
+
+/* Chipset types */
+#define SANDYBRIDGE_MOBILE	0
+#define SANDYBRIDGE_DESKTOP	1
+#define SANDYBRIDGE_SERVER	2
+
+/* Device ID for SandyBridge and IvyBridge */
+#define BASE_REV_SNB	0x00
+#define BASE_REV_IVB	0x50
+#define BASE_REV_MASK	0x50
+
+/* SandyBridge CPU stepping */
+#define SNB_STEP_D0	(BASE_REV_SNB + 5) /* Also J0 */
+#define SNB_STEP_D1	(BASE_REV_SNB + 6)
+#define SNB_STEP_D2	(BASE_REV_SNB + 7) /* Also J1/Q0 */
+
+/* IvyBridge CPU stepping */
+#define IVB_STEP_A0	(BASE_REV_IVB + 0)
+#define IVB_STEP_B0	(BASE_REV_IVB + 2)
+#define IVB_STEP_C0	(BASE_REV_IVB + 4)
+#define IVB_STEP_K0	(BASE_REV_IVB + 5)
+#define IVB_STEP_D0	(BASE_REV_IVB + 6)
+
+/* Intel Enhanced Debug region must be 4MB */
+#define IED_SIZE	0x400000
+
+/* Northbridge BARs */
+#define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
+#define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
+#define DEFAULT_RCBABASE	0xfed1c000
+/* 4 KB per PCIe device */
+#define DEFAULT_PCIEXBAR	CONFIG_PCIE_ECAM_BASE
+
+#define IOMMU_BASE1		0xfed90000ULL
+#define IOMMU_BASE2		0xfed91000ULL
+
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+#define EPBAR		0x40
+#define MCHBAR		0x48
+#define PCIEXBAR	0x60
+#define DMIBAR		0x68
+#define X60BAR		0x60
+
+#define GGC		0x50			/* GMCH Graphics Control */
+
+#define DEVEN		0x54			/* Device Enable */
+#define  DEVEN_PEG60	(1 << 13)
+#define  DEVEN_IGD	(1 << 4)
+#define  DEVEN_PEG10	(1 << 3)
+#define  DEVEN_PEG11	(1 << 2)
+#define  DEVEN_PEG12	(1 << 1)
+#define  DEVEN_HOST	(1 << 0)
+
+#define PAM0		0x80
+#define PAM1		0x81
+#define PAM2		0x82
+#define PAM3		0x83
+#define PAM4		0x84
+#define PAM5		0x85
+#define PAM6		0x86
+
+#define LAC		0x87	/* Legacy Access Control */
+#define SMRAM		0x88	/* System Management RAM Control */
+#define  D_OPEN		(1 << 6)
+#define  D_CLS		(1 << 5)
+#define  D_LCK		(1 << 4)
+#define  G_SMRAME	(1 << 3)
+#define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+
+#define TOM		0xa0
+#define TOUUD		0xa8	/* Top of Upper Usable DRAM */
+#define TSEG		0xb8	/* TSEG base */
+#define TOLUD		0xbc	/* Top of Low Used Memory */
+
+#define SKPAD		0xdc	/* Scratchpad Data */
+
+/* Device 0:1.0 PCI configuration space (PCI Express) */
+#define BCTRL1		0x3e	/* 16bit */
+
+/* Device 0:2.0 PCI configuration space (Graphics Device) */
+
+#define MSAC		0x62	/* Multi Size Aperture Control */
+#define SWSCI		0xe8	/* SWSCI  enable */
+#define ASLS		0xfc	/* OpRegion Base */
+
+/*
+ * MCHBAR
+ */
+#define SSKPD		0x5d14	/* 16bit (scratchpad) */
+#define BIOS_RESET_CPL	0x5da8	/* 8bit */
+
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR_REG(x)	(DEFAULT_DMIBAR + x)
+
+/**
+ * bridge_silicon_revision() - Get the Northbridge revision
+ *
+ * @dev:	Northbridge device
+ * @return revision ID (bits 3:0) and bridge ID (bits 7:4)
+ */
+int bridge_silicon_revision(struct udevice *dev);
+
+#endif
diff --git a/arch/x86/include/asm/arch-qemu/device.h b/arch/x86/include/asm/arch-qemu/device.h
new file mode 100644
index 0000000..daafd5d
--- /dev/null
+++ b/arch/x86/include/asm/arch-qemu/device.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _QEMU_DEVICE_H_
+#define _QEMU_DEVICE_H_
+
+#include <pci.h>
+
+#define QEMU_I440FX	PCI_BDF(0, 0, 0)
+#define PIIX_ISA	PCI_BDF(0, 1, 0)
+#define PIIX_IDE	PCI_BDF(0, 1, 1)
+#define PIIX_USB	PCI_BDF(0, 1, 2)
+#define PIIX_PM	PCI_BDF(0, 1, 3)
+#define ICH9_PM	PCI_BDF(0, 0x1f, 0)
+#define I440FX_VGA	PCI_BDF(0, 2, 0)
+
+#define QEMU_Q35	PCI_BDF(0, 0, 0)
+#define Q35_VGA		PCI_BDF(0, 1, 0)
+
+#endif /* _QEMU_DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-qemu/qemu.h b/arch/x86/include/asm/arch-qemu/qemu.h
new file mode 100644
index 0000000..061735b
--- /dev/null
+++ b/arch/x86/include/asm/arch-qemu/qemu.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _ARCH_QEMU_H_
+#define _ARCH_QEMU_H_
+
+/* Programmable Attribute Map (PAM) Registers */
+#define I440FX_PAM		0x59
+#define Q35_PAM			0x90
+#define PAM_NUM			7
+#define PAM_RW			0x33
+
+/* X-Bus Chip Select Register */
+#define XBCS			0x4e
+#define APIC_EN			(1 << 8)
+
+/* IDE Timing Register */
+#define IDE0_TIM		0x40
+#define IDE1_TIM		0x42
+#define IDE_DECODE_EN		(1 << 15)
+
+/* PCIe ECAM Base Address Register */
+#define PCIEX_BAR		0x60
+#define BAR_EN			(1 << 0)
+
+/* I/O Ports */
+#define CMOS_ADDR_PORT		0x70
+#define CMOS_DATA_PORT		0x71
+
+#define LOW_RAM_ADDR		0x34
+#define HIGH_RAM_ADDR		0x35
+
+#define LOW_HIGHRAM_ADDR	0x5b
+#define MID_HIGHRAM_ADDR	0x5c
+#define HIGH_HIGHRAM_ADDR	0x5d
+
+/* PM registers */
+#define PMBA		0x40
+#define PMREGMISC	0x80
+#define PMIOSE		(1 << 0)
+
+/**
+ * qemu_get_low_memory_size() - Get low memory size
+ *
+ * @return:	size of memory below 4GiB
+ */
+u32 qemu_get_low_memory_size(void);
+
+/**
+ * qemu_get_high_memory_size() - Get high memory size
+ *
+ * @return:	size of memory above 4GiB
+ */
+u64 qemu_get_high_memory_size(void);
+
+#endif /* _ARCH_QEMU_H_ */
diff --git a/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl
new file mode 100644
index 0000000..6160217
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <asm/acpi/global_nvs.h>
+
+OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
+Field(GNVS, ByteAcc, NoLock, Preserve)
+{
+	PCNT, 8,	/* processor count */
+}
diff --git a/arch/x86/include/asm/arch-quark/acpi/irqroute.h b/arch/x86/include/asm/arch-quark/acpi/irqroute.h
new file mode 100644
index 0000000..879b67d
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/irqroute.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+	PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D)
diff --git a/arch/x86/include/asm/arch-quark/acpi/lpc.asl b/arch/x86/include/asm/arch-quark/acpi/lpc.asl
new file mode 100644
index 0000000..fc30e0a
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/lpc.asl
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+	Name(_ADR, 0x001f0000)
+
+	OperationRegion(PRTX, PCI_Config, 0x60, 8)
+	Field(PRTX, AnyAcc, NoLock, Preserve) {
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+	}
+
+	#include <asm/acpi/irqlinks.asl>
+
+	/* Firmware Hub */
+	Device (FWH)
+	{
+		Name(_HID, EISAID("INT0800"))
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	/* 8259 Interrupt Controller */
+	Device (PIC)
+	{
+		Name(_HID, EISAID("PNP0000"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	/* 8254 timer */
+	Device (TIMR)
+	{
+		Name(_HID, EISAID("PNP0100"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() { 0 }
+		})
+	}
+
+	/* HPET */
+	Device (HPET)
+	{
+		Name(_HID, EISAID("PNP0103"))
+		Name(_CID, 0x010CD041)
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+		})
+
+		Method(_STA)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+
+	/* Real Time Clock */
+	Device (RTC)
+	{
+		Name(_HID, EISAID("PNP0B00"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x70, 0x70, 1, 8)
+			IRQNoFlags() { 8 }
+		})
+	}
+
+	/* LPC device: Resource consumption */
+	Device (LDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 2)
+
+		Name(RBUF, ResourceTemplate()
+		{
+			IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+			IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+			IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+		})
+
+		Method(_CRS, 0, NotSerialized)
+		{
+			Return (RBUF)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl
new file mode 100644
index 0000000..5b3e4a5
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+	Return (Package() {0, 0})
+}
+
+/* ACPI global NVS */
+#include "global_nvs.asl"
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+	#include "southcluster.asl"
+}
+
+/* Chipset specific sleep states */
+#include <asm/acpi/sleepstates.asl>
diff --git a/arch/x86/include/asm/arch-quark/acpi/southcluster.asl b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl
new file mode 100644
index 0000000..fe9edc1
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+Device (PCI0)
+{
+	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
+	Name(_CID, EISAID("PNP0A03"))	/* PCI */
+
+	Name(_ADR, 0)
+	Name(_BBN, 0)
+
+	Name(MCRS, ResourceTemplate()
+	{
+		/* Bus Numbers */
+		WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+		/* IO Region 0 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+		/* PCI Config Space */
+		IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		/* IO Region 1 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+		/* VGA memory (0xa0000-0xbffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000, , , ASEG)
+
+		/* OPROM reserved (0xc0000-0xc3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000, , , OPR0)
+
+		/* OPROM reserved (0xc4000-0xc7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000, , , OPR1)
+
+		/* OPROM reserved (0xc8000-0xcbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000, , , OPR2)
+
+		/* OPROM reserved (0xcc000-0xcffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000, , , OPR3)
+
+		/* OPROM reserved (0xd0000-0xd3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000, , , OPR4)
+
+		/* OPROM reserved (0xd4000-0xd7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000, , , OPR5)
+
+		/* OPROM reserved (0xd8000-0xdbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000, , , OPR6)
+
+		/* OPROM reserved (0xdc000-0xdffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000, , , OPR7)
+
+		/* BIOS Extension (0xe0000-0xe3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000, , , ESG0)
+
+		/* BIOS Extension (0xe4000-0xe7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000, , , ESG1)
+
+		/* BIOS Extension (0xe8000-0xebfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000, , , ESG2)
+
+		/* BIOS Extension (0xec000-0xeffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000, , , ESG3)
+
+		/* System BIOS (0xf0000-0xfffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000, , , FSEG)
+
+		/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , PMEM)
+	})
+
+	Method(_CRS, 0, Serialized)
+	{
+		/* Update PCI resource area */
+		CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+		CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+		CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+		/*
+		 * Hardcode TOLM to 2GB for now (see DRAM_MAX_SIZE in quark.h)
+		 *
+		 * TODO: for generic usage, read TOLM value from register, or
+		 * from global NVS (not implemented by U-Boot yet).
+		 */
+		Store(0x80000000, PMIN)
+		Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+		Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+		Return (MCRS)
+	}
+
+	/* Device Resource Consumption */
+	Device (PDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 1)
+
+		Name(PDRS, ResourceTemplate() {
+			Memory32Fixed(ReadWrite, CONFIG_ESRAM_BASE, 0x80000)
+			Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+			Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+			IO(Decode16, SPI_DMA_BASE_ADDRESS, SPI_DMA_BASE_ADDRESS, 0x0010, SPI_DMA_BASE_SIZE)
+			IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE)
+			IO(Decode16, WDT_BASE_ADDRESS, WDT_BASE_ADDRESS, 0x0040, WDT_BASE_SIZE)
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0, Serialized)
+		{
+			Return (PDRS)
+		}
+	}
+
+	Method(_OSC, 4)
+	{
+		/* Check for proper GUID */
+		If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+			/* Let OS control everything */
+			Return (Arg3)
+		} Else {
+			/* Unrecognized UUID */
+			CreateDWordField(Arg3, 0, CDW1)
+			Or(CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+	}
+
+	/* LPC Bridge 0:1f.0 */
+	#include "lpc.asl"
+
+	/* IRQ routing for each PCI device */
+	#include <asm/acpi/irqroute.asl>
+}
diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h
new file mode 100644
index 0000000..0c43916
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/device.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _QUARK_DEVICE_H_
+#define _QUARK_DEVICE_H_
+
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
+
+#define QUARK_HOST_BRIDGE_DEV	0x00
+#define QUARK_HOST_BRIDGE_FUNC	0
+
+#define QUARK_DEV_20		0x14
+#define QUARK_MMC_SDIO_FUNC	0
+#define QUARK_UART0_FUNC	1
+#define QUARK_USB_DEVICE_FUNC	2
+#define QUARK_USB_EHCI_FUNC	3
+#define QUARK_USB_OHCI_FUNC	4
+#define QUARK_UART1_FUNC	5
+#define QUARK_EMAC0_FUNC	6
+#define QUARK_EMAC1_FUNC	7
+
+#define QUARK_DEV_21		0x15
+#define QUARK_SPI0_FUNC		0
+#define QUARK_SPI1_FUNC		1
+#define QUARK_I2C_GPIO_FUNC	2
+
+#define QUARK_DEV_23		0x17
+#define QUARK_PCIE0_FUNC	0
+#define QUARK_PCIE1_FUNC	1
+
+#define QUARK_LGC_BRIDGE_DEV	0x1f
+#define QUARK_LGC_BRIDGE_FUNC	0
+
+#ifndef __ASSEMBLY__
+#include <pci.h>
+
+#define QUARK_HOST_BRIDGE	\
+	PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC)
+#define QUARK_MMC_SDIO		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_MMC_SDIO_FUNC)
+#define QUARK_UART0		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_UART0_FUNC)
+#define QUARK_USB_DEVICE	\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_USB_DEVICE_FUNC)
+#define QUARK_USB_EHCI		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_USB_EHCI_FUNC)
+#define QUARK_USB_OHCI		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_USB_OHCI_FUNC)
+#define QUARK_UART1		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_UART1_FUNC)
+#define QUARK_EMAC0		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC0_FUNC)
+#define QUARK_EMAC1		\
+	PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC1_FUNC)
+#define QUARK_SPI0		\
+	PCI_BDF(0, QUARK_DEV_21, QUARK_SPI0_FUNC)
+#define QUARK_SPI1		\
+	PCI_BDF(0, QUARK_DEV_21, QUARK_SPI1_FUNC)
+#define QUARK_I2C_GPIO		\
+	PCI_BDF(0, QUARK_DEV_21, QUARK_I2C_GPIO_FUNC)
+#define QUARK_PCIE0		\
+	PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE0_FUNC)
+#define QUARK_PCIE1		\
+	PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC)
+#define QUARK_LEGACY_BRIDGE	\
+	PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC)
+#endif /* __ASSEMBLY__ */
+
+#endif /* _QUARK_DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-quark/global_nvs.h b/arch/x86/include/asm/arch-quark/global_nvs.h
new file mode 100644
index 0000000..6e99e67
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/global_nvs.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _GLOBAL_NVS_H_
+#define _GLOBAL_NVS_H_
+
+struct __packed acpi_global_nvs {
+	u8	pcnt;		/* processor count */
+
+	/*
+	 * Add padding so sizeof(struct acpi_global_nvs) == 0x100.
+	 * This must match the size defined in the global_nvs.asl.
+	 */
+	u8	rsvd[255];
+};
+
+#endif /* _GLOBAL_NVS_H_ */
diff --git a/arch/x86/include/asm/arch-quark/iomap.h b/arch/x86/include/asm/arch-quark/iomap.h
new file mode 100644
index 0000000..e233252
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/iomap.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _QUARK_IOMAP_H_
+#define _QUARK_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* ESRAM */
+#define ESRAM_BASE_ADDRESS		CONFIG_ESRAM_BASE
+#define ESRAM_BASE_SIZE			ESRAM_SIZE
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS		CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE			0x10000000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS		0xfed00000
+#define HPET_BASE_SIZE			0x400
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS		CONFIG_RCBA_BASE
+#define RCBA_BASE_SIZE			0x4000
+
+/* IO Port bases */
+#define ACPI_PM1_BASE_ADDRESS		CONFIG_ACPI_PM1_BASE
+#define ACPI_PM1_BASE_SIZE		0x10
+
+#define ACPI_PBLK_BASE_ADDRESS		CONFIG_ACPI_PBLK_BASE
+#define ACPI_PBLK_BASE_SIZE		0x10
+
+#define SPI_DMA_BASE_ADDRESS		CONFIG_SPI_DMA_BASE
+#define SPI_DMA_BASE_SIZE		0x10
+
+#define GPIO_BASE_ADDRESS		CONFIG_GPIO_BASE
+#define GPIO_BASE_SIZE			0x80
+
+#define ACPI_GPE0_BASE_ADDRESS		CONFIG_ACPI_GPE0_BASE
+#define ACPI_GPE0_BASE_SIZE		0x40
+
+#define WDT_BASE_ADDRESS		CONFIG_WDT_BASE
+#define WDT_BASE_SIZE			0x40
+
+#endif /* _QUARK_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-quark/irq.h b/arch/x86/include/asm/arch-quark/irq.h
new file mode 100644
index 0000000..2aaa728
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/irq.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _QUARK_IRQ_H_
+#define _QUARK_IRQ_H_
+
+#define PIRQA_APIC_IRQ	16
+#define PIRQB_APIC_IRQ	17
+#define PIRQC_APIC_IRQ	18
+#define PIRQD_APIC_IRQ	19
+#define PIRQE_APIC_IRQ	20
+#define PIRQF_APIC_IRQ	21
+#define PIRQG_APIC_IRQ	22
+#define PIRQH_APIC_IRQ	23
+
+#endif /* _QUARK_IRQ_H_ */
diff --git a/arch/x86/include/asm/arch-quark/mrc.h b/arch/x86/include/asm/arch-quark/mrc.h
new file mode 100644
index 0000000..2353426
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/mrc.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Ported from Intel released Quark UEFI BIOS
+ * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
+ */
+
+#ifndef _MRC_H_
+#define _MRC_H_
+
+#define MRC_VERSION	0x0111
+
+/* architectural definitions */
+#define NUM_CHANNELS	1	/* number of channels */
+#define NUM_RANKS	2	/* number of ranks per channel */
+#define NUM_BYTE_LANES	4	/* number of byte lanes per channel */
+
+/* software limitations */
+#define MAX_CHANNELS	1
+#define MAX_RANKS	2
+#define MAX_BYTE_LANES	4
+
+#define MAX_SOCKETS	1
+#define MAX_SIDES	1
+#define MAX_ROWS	(MAX_SIDES * MAX_SOCKETS)
+
+/* Specify DRAM and channel width */
+enum {
+	X8,	/* DRAM width */
+	X16,	/* DRAM width & Channel Width */
+	X32	/* Channel Width */
+};
+
+/* Specify DRAM speed */
+enum {
+	DDRFREQ_800,
+	DDRFREQ_1066
+};
+
+/* Specify DRAM type */
+enum {
+	DDR3,
+	DDR3L
+};
+
+/*
+ * density: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb
+ * cl: DRAM CAS Latency in clocks
+ * ras: ACT to PRE command period
+ * wtr: Delay from start of internal write transaction to internal read command
+ * rrd: ACT to ACT command period (JESD79 specific to page size 1K/2K)
+ * faw: Four activate window (JESD79 specific to page size 1K/2K)
+ *
+ * ras/wtr/rrd/faw timings are in picoseconds
+ *
+ * Refer to JEDEC spec (or DRAM datasheet) when changing these values.
+ */
+struct dram_params {
+	uint8_t density;
+	uint8_t cl;
+	uint32_t ras;
+	uint32_t wtr;
+	uint32_t rrd;
+	uint32_t faw;
+};
+
+/*
+ * Delay configuration for individual signals
+ * Vref setting
+ * Scrambler seed
+ */
+struct mrc_timings {
+	uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
+	uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
+	uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
+	uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES];
+	uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES];
+	uint32_t wctl[NUM_CHANNELS][NUM_RANKS];
+	uint32_t wcmd[NUM_CHANNELS];
+	uint32_t scrambler_seed;
+	/* need to save for the case of frequency change */
+	uint8_t ddr_speed;
+};
+
+/* Boot mode defined as bit mask (1<<n) */
+enum {
+	BM_UNKNOWN,
+	BM_COLD = 1,	/* full training */
+	BM_FAST = 2,	/* restore timing parameters */
+	BM_S3   = 4,	/* resume from S3 */
+	BM_WARM = 8
+};
+
+/* MRC execution status */
+#define MRC_SUCCESS	0	/* initialization ok */
+#define MRC_E_MEMTEST	1	/* memtest failed */
+
+/*
+ * Memory Reference Code parameters
+ *
+ * It includes 3 parts:
+ * - input parameters like boot mode and DRAM parameters
+ * - context parameters for MRC internal state
+ * - output parameters like initialization result and memory size
+ */
+struct mrc_params {
+	/* Input parameters */
+	uint32_t boot_mode;		/* BM_COLD, BM_FAST, BM_WARM, BM_S3 */
+	/* DRAM parameters */
+	uint8_t dram_width;		/* x8, x16 */
+	uint8_t ddr_speed;		/* DDRFREQ_800, DDRFREQ_1066 */
+	uint8_t ddr_type;		/* DDR3, DDR3L */
+	uint8_t ecc_enables;		/* 0, 1 (memory size reduced to 7/8) */
+	uint8_t scrambling_enables;	/* 0, 1 */
+	/* 1, 3 (1'st rank has to be populated if 2'nd rank present) */
+	uint32_t rank_enables;
+	uint32_t channel_enables;	/* 1 only */
+	uint32_t channel_width;		/* x16 only */
+	/* 0, 1, 2 (mode 2 forced if ecc enabled) */
+	uint32_t address_mode;
+	/* REFRESH_RATE: 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED */
+	uint8_t refresh_rate;
+	/* SR_TEMP_RANGE: 0=normal, 1=extended, others=RESERVED */
+	uint8_t sr_temp_range;
+	/*
+	 * RON_VALUE: 0=34ohm, 1=40ohm, others=RESERVED
+	 * (select MRS1.DIC driver impedance control)
+	 */
+	uint8_t ron_value;
+	/* RTT_NOM_VALUE: 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */
+	uint8_t rtt_nom_value;
+	/* RD_ODT_VALUE: 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
+	uint8_t rd_odt_value;
+	struct dram_params params;
+	/* Internally used context parameters */
+	uint32_t board_id;	/* board layout (use x8 or x16 memory) */
+	uint32_t hte_setup;	/* when set hte reconfiguration requested */
+	uint32_t menu_after_mrc;
+	uint32_t power_down_disable;
+	uint32_t tune_rcvn;
+	uint32_t channel_size[NUM_CHANNELS];
+	uint32_t column_bits[NUM_CHANNELS];
+	uint32_t row_bits[NUM_CHANNELS];
+	uint32_t mrs1;		/* register content saved during training */
+	uint8_t first_run;
+	/* Output parameters */
+	/* initialization result (non zero specifies error code) */
+	uint32_t status;
+	/* total memory size in bytes (excludes ECC banks) */
+	uint32_t mem_size;
+	/* training results (also used on input) */
+	struct mrc_timings timings;
+};
+
+/*
+ * MRC memory initialization structure
+ *
+ * post_code: a 16-bit post code of a specific initialization routine
+ * boot_path: bitwise or of BM_COLD, BM_FAST, BM_WARM and BM_S3
+ * init_fn: real memory initialization routine
+ */
+struct mem_init {
+	uint16_t post_code;
+	uint16_t boot_path;
+	void (*init_fn)(struct mrc_params *mrc_params);
+};
+
+/* MRC platform data flags */
+#define MRC_FLAG_ECC_EN		0x00000001
+#define MRC_FLAG_SCRAMBLE_EN	0x00000002
+#define MRC_FLAG_MEMTEST_EN	0x00000004
+/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
+#define MRC_FLAG_TOP_TREE_EN	0x00000008
+/* If set ODR signal is asserted to DRAM devices on writes */
+#define MRC_FLAG_WR_ODT_EN	0x00000010
+
+/**
+ * mrc_init - Memory Reference Code initialization entry routine
+ *
+ * @mrc_params: parameters for MRC
+ */
+void mrc_init(struct mrc_params *mrc_params);
+
+#endif /* _MRC_H_ */
diff --git a/arch/x86/include/asm/arch-quark/msg_port.h b/arch/x86/include/asm/arch-quark/msg_port.h
new file mode 100644
index 0000000..9527fda
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/msg_port.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _QUARK_MSG_PORT_H_
+#define _QUARK_MSG_PORT_H_
+
+/*
+ * In the Quark SoC, some chipset commands are accomplished by utilizing
+ * the internal message network within the host bridge (D0:F0). Accesses
+ * to this network are accomplished by populating the message control
+ * register (MCR), Message Control Register eXtension (MCRX) and the
+ * message data register (MDR).
+ */
+#define MSG_CTRL_REG		0xd0	/* Message Control Register */
+#define MSG_DATA_REG		0xd4	/* Message Data Register */
+#define MSG_CTRL_EXT_REG	0xd8	/* Message Control Register EXT */
+
+/* Normal Read/Write OpCodes */
+#define MSG_OP_READ		0x10
+#define MSG_OP_WRITE		0x11
+
+/* Alternative Read/Write OpCodes */
+#define MSG_OP_ALT_READ		0x06
+#define MSG_OP_ALT_WRITE	0x07
+
+/* IO Read/Write OpCodes */
+#define MSG_OP_IO_READ		0x02
+#define MSG_OP_IO_WRITE		0x03
+
+/* All byte enables */
+#define MSG_BYTE_ENABLE		0xf0
+
+#ifndef __ASSEMBLY__
+
+/**
+ * msg_port_setup - set up the message port control register
+ *
+ * @op:     message bus access opcode
+ * @port:   port number on the message bus
+ * @reg:    register number within a port
+ */
+void msg_port_setup(int op, int port, int reg);
+
+/**
+ * msg_port_read - read a message port register using normal opcode
+ *
+ * @port:   port number on the message bus
+ * @reg:    register number within a port
+ *
+ * @return: message port register value
+ */
+u32 msg_port_read(u8 port, u32 reg);
+
+/**
+ * msg_port_write - write a message port register using normal opcode
+ *
+ * @port:   port number on the message bus
+ * @reg:    register number within a port
+ * @value:  register value to write
+ */
+void msg_port_write(u8 port, u32 reg, u32 value);
+
+/**
+ * msg_port_alt_read - read a message port register using alternative opcode
+ *
+ * @port:   port number on the message bus
+ * @reg:    register number within a port
+ *
+ * @return: message port register value
+ */
+u32 msg_port_alt_read(u8 port, u32 reg);
+
+/**
+ * msg_port_alt_write - write a message port register using alternative opcode
+ *
+ * @port:   port number on the message bus
+ * @reg:    register number within a port
+ * @value:  register value to write
+ */
+void msg_port_alt_write(u8 port, u32 reg, u32 value);
+
+/**
+ * msg_port_io_read - read a message port register using I/O opcode
+ *
+ * @port:   port number on the message bus
+ * @reg:    register number within a port
+ *
+ * @return: message port register value
+ */
+u32 msg_port_io_read(u8 port, u32 reg);
+
+/**
+ * msg_port_io_write - write a message port register using I/O opcode
+ *
+ * @port:   port number on the message bus
+ * @reg:    register number within a port
+ * @value:  register value to write
+ */
+void msg_port_io_write(u8 port, u32 reg, u32 value);
+
+/* clrbits, setbits, clrsetbits macros for message port access */
+
+#define msg_port_normal_read	msg_port_read
+#define msg_port_normal_write	msg_port_write
+
+#define msg_port_generic_clrsetbits(type, port, reg, clr, set)		\
+	msg_port_##type##_write(port, reg,				\
+				(msg_port_##type##_read(port, reg)	\
+				& ~(clr)) | (set))
+
+#define msg_port_clrbits(port, reg, clr)		\
+	msg_port_generic_clrsetbits(normal, port, reg, clr, 0)
+#define msg_port_setbits(port, reg, set)		\
+	msg_port_generic_clrsetbits(normal, port, reg, 0, set)
+#define msg_port_clrsetbits(port, reg, clr, set)	\
+	msg_port_generic_clrsetbits(normal, port, reg, clr, set)
+
+#define msg_port_alt_clrbits(port, reg, clr)		\
+	msg_port_generic_clrsetbits(alt, port, reg, clr, 0)
+#define msg_port_alt_setbits(port, reg, set)		\
+	msg_port_generic_clrsetbits(alt, port, reg, 0, set)
+#define msg_port_alt_clrsetbits(port, reg, clr, set)	\
+	msg_port_generic_clrsetbits(alt, port, reg, clr, set)
+
+#define msg_port_io_clrbits(port, reg, clr)		\
+	msg_port_generic_clrsetbits(io, port, reg, clr, 0)
+#define msg_port_io_setbits(port, reg, set)		\
+	msg_port_generic_clrsetbits(io, port, reg, 0, set)
+#define msg_port_io_clrsetbits(port, reg, clr, set)	\
+	msg_port_generic_clrsetbits(io, port, reg, clr, set)
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _QUARK_MSG_PORT_H_ */
diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h
new file mode 100644
index 0000000..feca198
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/quark.h
@@ -0,0 +1,259 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _QUARK_H_
+#define _QUARK_H_
+
+/* Message Bus Ports */
+#define MSG_PORT_MEM_ARBITER	0x00
+#define MSG_PORT_HOST_BRIDGE	0x03
+#define MSG_PORT_RMU		0x04
+#define MSG_PORT_MEM_MGR	0x05
+#define MSG_PORT_USB_AFE	0x14
+#define MSG_PORT_PCIE_AFE	0x16
+#define MSG_PORT_SOC_UNIT	0x31
+
+/* Port 0x00: Memory Arbiter Message Port Registers */
+
+/* Enhanced Configuration Space */
+#define AEC_CTRL		0x00
+
+/* Port 0x03: Host Bridge Message Port Registers */
+
+/* Host Miscellaneous Controls 2 */
+#define HMISC2			0x03
+
+#define HMISC2_SEGE		0x00000002
+#define HMISC2_SEGF		0x00000004
+#define HMISC2_SEGAB		0x00000010
+
+/* Host Memory I/O Boundary */
+#define HM_BOUND		0x08
+#define HM_BOUND_LOCK		0x00000001
+
+/* Extended Configuration Space */
+#define HEC_REG			0x09
+
+/* MTRR Registers */
+#define MTRR_CAP		0x40
+#define MTRR_DEF_TYPE		0x41
+
+#define MTRR_FIX_64K_00000	0x42
+#define MTRR_FIX_64K_40000	0x43
+#define MTRR_FIX_16K_80000	0x44
+#define MTRR_FIX_16K_90000	0x45
+#define MTRR_FIX_16K_A0000	0x46
+#define MTRR_FIX_16K_B0000	0x47
+#define MTRR_FIX_4K_C0000	0x48
+#define MTRR_FIX_4K_C4000	0x49
+#define MTRR_FIX_4K_C8000	0x4a
+#define MTRR_FIX_4K_CC000	0x4b
+#define MTRR_FIX_4K_D0000	0x4c
+#define MTRR_FIX_4K_D4000	0x4d
+#define MTRR_FIX_4K_D8000	0x4e
+#define MTRR_FIX_4K_DC000	0x4f
+#define MTRR_FIX_4K_E0000	0x50
+#define MTRR_FIX_4K_E4000	0x51
+#define MTRR_FIX_4K_E8000	0x52
+#define MTRR_FIX_4K_EC000	0x53
+#define MTRR_FIX_4K_F0000	0x54
+#define MTRR_FIX_4K_F4000	0x55
+#define MTRR_FIX_4K_F8000	0x56
+#define MTRR_FIX_4K_FC000	0x57
+
+#define MTRR_SMRR_PHYBASE	0x58
+#define MTRR_SMRR_PHYMASK	0x59
+
+#define MTRR_VAR_PHYBASE(n)	(0x5a + 2 * (n))
+#define MTRR_VAR_PHYMASK(n)	(0x5b + 2 * (n))
+
+#ifndef __ASSEMBLY__
+
+/* variable range MTRR usage */
+enum {
+	MTRR_VAR_ROM,
+	MTRR_VAR_ESRAM,
+	MTRR_VAR_RAM
+};
+
+#endif /* __ASSEMBLY__ */
+
+/* Port 0x04: Remote Management Unit Message Port Registers */
+
+/* ACPI PBLK Base Address Register */
+#define PBLK_BA			0x70
+
+/* Control Register */
+#define RMU_CTRL		0x71
+
+/* SPI DMA Base Address Register */
+#define SPI_DMA_BA		0x7a
+
+/* Thermal Sensor Register */
+#define TS_MODE			0xb0
+#define TS_TEMP			0xb1
+#define TS_TRIP			0xb2
+
+/* Port 0x05: Memory Manager Message Port Registers */
+
+/* eSRAM Block Page Control */
+#define ESRAM_BLK_CTRL		0x82
+#define ESRAM_BLOCK_MODE	0x10000000
+
+/* Port 0x14: USB2 AFE Unit Port Registers */
+
+#define USB2_GLOBAL_PORT	0x4001
+#define USB2_PLL1		0x7f02
+#define USB2_PLL2		0x7f03
+#define USB2_COMPBG		0x7f04
+
+/* Port 0x16: PCIe AFE Unit Port Registers */
+
+#define PCIE_RXPICTRL0_L0	0x2080
+#define PCIE_RXPICTRL0_L1	0x2180
+
+/* Port 0x31: SoC Unit Port Registers */
+
+/* Thermal Sensor Config */
+#define TS_CFG1			0x31
+#define TS_CFG2			0x32
+#define TS_CFG3			0x33
+#define TS_CFG4			0x34
+
+/* PCIe Controller Config */
+#define PCIE_CFG		0x36
+#define PCIE_CTLR_PRI_RST	0x00010000
+#define PCIE_PHY_SB_RST		0x00020000
+#define PCIE_CTLR_SB_RST	0x00040000
+#define PCIE_PHY_LANE_RST	0x00090000
+#define PCIE_CTLR_MAIN_RST	0x00100000
+
+/* DRAM */
+#define DRAM_BASE		0x00000000
+#define DRAM_MAX_SIZE		0x80000000
+
+/* eSRAM */
+#define ESRAM_SIZE		0x80000
+
+/* Memory BAR Enable */
+#define MEM_BAR_EN		0x00000001
+
+/* I/O BAR Enable */
+#define IO_BAR_EN		0x80000000
+
+/* 64KiB of RMU binary in flash */
+#define RMU_BINARY_SIZE		0x10000
+
+/* PCIe Root Port Configuration Registers */
+
+#define PCIE_RP_CCFG		0xd0
+#define CCFG_UPRS		(1 << 14)
+#define CCFG_UNRS		(1 << 15)
+#define CCFG_UNSD		(1 << 23)
+#define CCFG_UPSD		(1 << 24)
+
+#define PCIE_RP_MPC2		0xd4
+#define MPC2_IPF		(1 << 11)
+
+#define PCIE_RP_MBC		0xf4
+#define MBC_SBIC		(3 << 16)
+
+/* Legacy Bridge PCI Configuration Registers */
+#define LB_GBA			0x44
+#define LB_PM1BLK		0x48
+#define LB_GPE0BLK		0x4c
+#define LB_ACTL			0x58
+#define LB_PABCDRC		0x60
+#define LB_PEFGHRC		0x64
+#define LB_WDTBA		0x84
+#define LB_BCE			0xd4
+#define LB_BC			0xd8
+#define LB_RCBA			0xf0
+
+/* USB EHCI memory-mapped registers */
+#define EHCI_INSNREG01		0x94
+
+/* USB device memory-mapped registers */
+#define USBD_INT_MASK		0x410
+#define USBD_EP_INT_STS		0x414
+#define USBD_EP_INT_MASK	0x418
+
+#ifndef __ASSEMBLY__
+
+/* Root Complex Register Block */
+struct quark_rcba {
+	u32	rctl;
+	u32	esd;
+	u32	rsvd1[3150];
+	u16	rmu_ir;
+	u16	d23_ir;
+	u16	core_ir;
+	u16	d20d21_ir;
+};
+
+#include <asm/io.h>
+#include <asm/pci.h>
+
+/**
+ * qrk_pci_read_config_dword() - Read a configuration value
+ *
+ * @dev:	PCI device address: bus, device and function
+ * @offset:	Dword offset within the device's configuration space
+ * @valuep:	Place to put the returned value
+ *
+ * Note: This routine is inlined to provide better performance on Quark
+ */
+static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset,
+					     u32 *valuep)
+{
+	outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
+	*valuep = inl(PCI_REG_DATA);
+}
+
+/**
+ * qrk_pci_write_config_dword() - Write a PCI configuration value
+ *
+ * @dev:	PCI device address: bus, device and function
+ * @offset:	Dword offset within the device's configuration space
+ * @value:	Value to write
+ *
+ * Note: This routine is inlined to provide better performance on Quark
+ */
+static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset,
+					      u32 value)
+{
+	outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
+	outl(value, PCI_REG_DATA);
+}
+
+/**
+ * board_assert_perst() - Assert the PERST# pin
+ *
+ * The CPU interface to the PERST# signal on Quark is platform dependent.
+ * Board-specific codes need supply this routine to assert PCIe slot reset.
+ *
+ * The tricky part in this routine is that any APIs that may trigger PCI
+ * enumeration process are strictly forbidden, as any access to PCIe root
+ * port's configuration registers will cause system hang while it is held
+ * in reset.
+ */
+void board_assert_perst(void);
+
+/**
+ * board_deassert_perst() - De-assert the PERST# pin
+ *
+ * The CPU interface to the PERST# signal on Quark is platform dependent.
+ * Board-specific codes need supply this routine to de-assert PCIe slot reset.
+ *
+ * The tricky part in this routine is that any APIs that may trigger PCI
+ * enumeration process are strictly forbidden, as any access to PCIe root
+ * port's configuration registers will cause system hang while it is held
+ * in reset.
+ */
+void board_deassert_perst(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _QUARK_H_ */
diff --git a/arch/x86/include/asm/arch-queensbay/device.h b/arch/x86/include/asm/arch-queensbay/device.h
new file mode 100644
index 0000000..15857bf
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/device.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _QUEENSBAY_DEVICE_H_
+#define _QUEENSBAY_DEVICE_H_
+
+#include <pci.h>
+
+/* TunnelCreek PCI Devices */
+#define TNC_HOST_BRIDGE_DEV	0
+#define TNC_HOST_BRIDGE_FUNC	0
+#define TNC_IGD_DEV		2
+#define TNC_IGD_FUNC		0
+#define TNC_SDVO_DEV		3
+#define TNC_SDVO_FUNC		0
+#define TNC_PCIE0_DEV		23
+#define TNC_PCIE0_FUNC		0
+#define TNC_PCIE1_DEV		24
+#define TNC_PCIE1_FUNC		0
+#define TNC_PCIE2_DEV		25
+#define TNC_PCIE2_FUNC		0
+#define TNC_PCIE3_DEV		26
+#define TNC_PCIE3_FUNC		0
+#define TNC_HDA_DEV		27
+#define TNC_HDA_FUNC		0
+#define TNC_LPC_DEV		31
+#define TNC_LPC_FUNC		0
+
+#define TNC_HOST_BRIDGE		\
+	PCI_BDF(0, TNC_HOST_BRIDGE_DEV, TNC_HOST_BRIDGE_FUNC)
+#define TNC_IGD			\
+	PCI_BDF(0, TNC_IGD_DEV, TNC_IGD_FUNC)
+#define TNC_SDVO		\
+	PCI_BDF(0, TNC_SDVO_DEV, TNC_SDVO_FUNC)
+#define TNC_PCIE0		\
+	PCI_BDF(0, TNC_PCIE0_DEV, TNC_PCIE0_FUNC)
+#define TNC_PCIE1		\
+	PCI_BDF(0, TNC_PCIE1_DEV, TNC_PCIE1_FUNC)
+#define TNC_PCIE2		\
+	PCI_BDF(0, TNC_PCIE2_DEV, TNC_PCIE2_FUNC)
+#define TNC_PCIE3		\
+	PCI_BDF(0, TNC_PCIE3_DEV, TNC_PCIE3_FUNC)
+#define TNC_HDA			\
+	PCI_BDF(0, TNC_HDA_DEV, TNC_HDA_FUNC)
+#define TNC_LPC			\
+	PCI_BDF(0, TNC_LPC_DEV, TNC_LPC_FUNC)
+
+/* Topcliff IOH PCI Devices */
+#define TCF_PCIE_PORT_DEV	0
+#define TCF_PCIE_PORT_FUNC	0
+
+#define TCF_DEV_0		0
+#define TCF_PKT_HUB_FUNC	0
+#define TCF_GBE_FUNC		1
+#define TCF_GPIO_FUNC		2
+
+#define TCF_DEV_2		2
+#define TCF_USB1_OHCI0_FUNC	0
+#define TCF_USB1_OHCI1_FUNC	1
+#define TCF_USB1_OHCI2_FUNC	2
+#define TCF_USB1_EHCI_FUNC	3
+#define TCF_USB_DEVICE_FUNC	4
+
+#define TCF_DEV_4		4
+#define TCF_SDIO0_FUNC		0
+#define TCF_SDIO1_FUNC		1
+
+#define TCF_DEV_6		6
+#define TCF_SATA_FUNC		0
+
+#define TCF_DEV_8		8
+#define TCF_USB2_OHCI0_FUNC	0
+#define TCF_USB2_OHCI1_FUNC	1
+#define TCF_USB2_OHCI2_FUNC	2
+#define TCF_USB2_EHCI_FUNC	3
+
+#define TCF_DEV_10		10
+#define TCF_DMA1_FUNC		0
+#define TCF_UART0_FUNC		1
+#define TCF_UART1_FUNC		2
+#define TCF_UART2_FUNC		3
+#define TCF_UART3_FUNC		4
+
+#define TCF_DEV_12		12
+#define TCF_DMA2_FUNC		0
+#define TCF_SPI_FUNC		1
+#define TCF_I2C_FUNC		2
+#define TCF_CAN_FUNC		3
+#define TCF_1588_FUNC		4
+
+#endif /* _QUEENSBAY_DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h
new file mode 100644
index 0000000..979121c
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_configs.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_CONFIGS_H__
+#define __FSP_CONFIGS_H__
+
+struct fsp_config_data {
+	struct fsp_cfg_common	common;
+	struct upd_region	fsp_upd;
+};
+
+struct fspinit_rtbuf {
+	struct common_buf	common;	/* FSP common runtime data structure */
+};
+
+#endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
new file mode 100644
index 0000000..7572fc7
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * This file is automatically generated. Please do NOT modify !!!
+ */
+
+#ifndef __VPDHEADER_H__
+#define __VPDHEADER_H__
+
+struct __packed upd_region {
+	u64	sign;			/* Offset 0x0000 */
+	u64	reserved;		/* Offset 0x0008 */
+	u8	dummy[240];		/* Offset 0x0010 */
+	u8	hda_verb_header[12];	/* Offset 0x0100 */
+	u32	hda_verb_length;	/* Offset 0x010C */
+	u8	hda_verb_data0[16];	/* Offset 0x0110 */
+	u8	hda_verb_data1[16];	/* Offset 0x0120 */
+	u8	hda_verb_data2[16];	/* Offset 0x0130 */
+	u8	hda_verb_data3[16];	/* Offset 0x0140 */
+	u8	hda_verb_data4[16];	/* Offset 0x0150 */
+	u8	hda_verb_data5[16];	/* Offset 0x0160 */
+	u8	hda_verb_data6[16];	/* Offset 0x0170 */
+	u8	hda_verb_data7[16];	/* Offset 0x0180 */
+	u8	hda_verb_data8[16];	/* Offset 0x0190 */
+	u8	hda_verb_data9[16];	/* Offset 0x01A0 */
+	u8	hda_verb_data10[16];	/* Offset 0x01B0 */
+	u8	hda_verb_data11[16];	/* Offset 0x01C0 */
+	u8	hda_verb_data12[16];	/* Offset 0x01D0 */
+	u8	hda_verb_data13[16];	/* Offset 0x01E0 */
+	u8	hda_verb_pad[47];	/* Offset 0x01F0 */
+	u16	terminator;		/* Offset 0x021F */
+};
+
+#define VPD_IMAGE_ID	0x445056574F4E4E4D	/* 'MNNOWVPD' */
+
+struct __packed vpd_region {
+	u64	sign;			/* Offset 0x0000 */
+	u32	img_rev;		/* Offset 0x0008 */
+	u32	upd_offset;		/* Offset 0x000C */
+	u8	unused[16];		/* Offset 0x0010 */
+	u32	fsp_res_memlen;		/* Offset 0x0020 */
+	u8	disable_pcie1;		/* Offset 0x0024 */
+	u8	disable_pcie2;		/* Offset 0x0025 */
+	u8	disable_pcie3;		/* Offset 0x0026 */
+	u8	enable_azalia;		/* Offset 0x0027 */
+	u8	legacy_seg_decode;	/* Offset 0x0028 */
+	u8	pcie_port_ioh;		/* Offset 0x0029 */
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h
new file mode 100644
index 0000000..8d15150
--- /dev/null
+++ b/arch/x86/include/asm/arch-queensbay/tnc.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _X86_ARCH_TNC_H_
+#define _X86_ARCH_TNC_H_
+
+/* IGD Function Disable Register */
+#define IGD_FD		0xc4
+#define FUNC_DISABLE	0x00000001
+
+/* Memory BAR Enable */
+#define MEM_BAR_EN	0x00000001
+
+/* LPC PCI Configuration Registers */
+#define LPC_RCBA	0xf0
+
+/* Root Complex Register Block */
+struct tnc_rcba {
+	u32	rctl;
+	u32	esd;
+	u32	rsvd1[2];
+	u32	hdd;
+	u32	rsvd2;
+	u32	hdba;
+	u32	rsvd3[3129];
+	u32	d31ip;
+	u32	rsvd4[3];
+	u32	d27ip;
+	u32	rsvd5;
+	u32	d02ip;
+	u32	rsvd6;
+	u32	d26ip;
+	u32	d25ip;
+	u32	d24ip;
+	u32	d23ip;
+	u32	d03ip;
+	u32	rsvd7[3];
+	u16	d31ir;
+	u16	rsvd8[3];
+	u16	d27ir;
+	u16	d26ir;
+	u16	d25ir;
+	u16	d24ir;
+	u16	d23ir;
+	u16	rsvd9[7];
+	u16	d02ir;
+	u16	d03ir;
+};
+
+#endif /* _X86_ARCH_TNC_H_ */
diff --git a/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
new file mode 100644
index 0000000..05dd1b2
--- /dev/null
+++ b/arch/x86/include/asm/arch-slimbootloader/slimbootloader.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef __SLIMBOOTLOADER_ARCH_H__
+#define __SLIMBOOTLOADER_ARCH_H__
+
+#include <common.h>
+#include <asm/hob.h>
+
+/**
+ * A GUID to get MemoryMap info hob which is provided by Slim Bootloader
+ */
+#define SBL_MEMORY_MAP_INFO_GUID \
+	EFI_GUID(0xa1ff7424, 0x7a1a, 0x478e, \
+		0xa9, 0xe4, 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32)
+
+/**
+ * A GUID to get SerialPort info hob which is provided by Slim Bootloader
+ */
+#define SBL_SERIAL_PORT_INFO_GUID \
+	EFI_GUID(0x6c6872fe, 0x56a9, 0x4403, \
+		0xbb, 0x98, 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1)
+
+/**
+ * A GUID to get boot performance info hob which is provided by Slim Bootloader
+ */
+#define SBL_PERFORMANCE_INFO_GUID \
+	EFI_GUID(0x868204be, 0x23d0, 0x4ff9, \
+		0xac, 0x34, 0xb9, 0x95, 0xac, 0x04, 0xb1, 0xb9)
+
+/**
+ * A single entry of memory map information
+ *
+ * @addr: start address of a memory map entry
+ * @size: size of a memory map entry
+ * @type: usable:1, reserved:2, acpi:3, nvs:4, unusable:5
+ * @flag: only used in Slim Bootloader
+ * @rsvd: padding for alignment
+ */
+struct sbl_memory_map_entry {
+	u64	addr;
+	u64	size;
+	u8	type;
+	u8	flag;
+	u8	rsvd[6];
+};
+
+/**
+ * This includes all memory map entries which is sorted based on physical start
+ * address, from low to high, and carved out reserved, acpi nvs, acpi reclaim
+ * and usable memory.
+ *
+ * @rev  : revision of memory_map_info structure. currently 1.
+ * @rsvd : padding for alignment
+ * @count: the number of memory map entries
+ * @entry: array of all memory map entries
+ */
+struct sbl_memory_map_info {
+	u8	rev;
+	u8	rsvd[3];
+	u32	count;
+	struct sbl_memory_map_entry	entry[0];
+};
+
+/**
+ * This includes serial port info which has already been initialized in previous
+ * Slim Bootloader stage.
+ * The Slim Bootloader initializes serial port regardless of debug/release build
+ * modes, and it passes the information to a payload thru hob. So, a payload can
+ * re-use the serial information without re-initializing serial port.
+ *
+ * @rev   : revision of serial_port_info structure. currently 1.
+ * @rsvd  : padding for alignment
+ * @type  : port io: 1, mmio: 2
+ * @base  : io base address. ex) 0x3f8, 0x80001000
+ * @baud  : uart baud rate
+ * @stride: register stride in Bytes
+ * @clk   : uart frequency in Hz
+ * @rsvd1 : reserved
+ */
+struct sbl_serial_port_info {
+	u8      rev;
+	u8      rsvd[3];
+	u32     type;
+	u32     base;
+	u32     baud;
+	u32     stride;
+	u32     clk;
+	u32     rsvd1;
+};
+
+/**
+ * This includes timestamp data which has been collected in Slim Bootloader
+ * stages from the reset vector. In addition, this has TSC frequency in KHz to
+ * calculate each timestamp.
+ *
+ * @rev   : revision of performance_info structure. currently 1.
+ * @rsvd  : padding for alignment
+ * @count : the number of collected timestamp data
+ * @flags : only used in Slim Bootloader
+ * @frequency: tsc frequency in KHz
+ * @timestamp: the array of timestamp data which has 64-bit tsc value
+ */
+struct sbl_performance_info {
+	u8      rev;
+	u8      rsvd[3];
+	u16     count;
+	u16     flags;
+	u32     frequency;
+	u64     timestamp[0];
+};
+
+#endif /* __SLIMBOOTLOADER_ARCH_H__ */
diff --git a/arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl b/arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl
new file mode 100644
index 0000000..895b807
--- /dev/null
+++ b/arch/x86/include/asm/arch-tangier/acpi/global_nvs.asl
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * Partially based on global_nvs.asl for other x86 platforms
+ */
+
+#include <asm/acpi/global_nvs.h>
+
+OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
+Field(GNVS, ByteAcc, NoLock, Preserve)
+{
+    PCNT, 8,    /* processor count */
+}
diff --git a/arch/x86/include/asm/arch-tangier/acpi/platform.asl b/arch/x86/include/asm/arch-tangier/acpi/platform.asl
new file mode 100644
index 0000000..cf75ca7
--- /dev/null
+++ b/arch/x86/include/asm/arch-tangier/acpi/platform.asl
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * Partially based on platform.asl for other x86 platforms
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+    Return (Package() { Zero, Zero })
+}
+
+Scope (_SB)
+{
+    /* Real Time Clock */
+    Device (RTC0)
+    {
+        Name (_HID, EisaId ("PNP0B00"))
+        Name (_CRS, ResourceTemplate()
+        {
+            IO(Decode16, 0x70, 0x70, 0x01, 0x08)
+        })
+    }
+}
+
+/* ACPI global NVS */
+#include "global_nvs.asl"
+
+Scope (\_SB)
+{
+    #include "southcluster.asl"
+}
diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
new file mode 100644
index 0000000..c622783
--- /dev/null
+++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl
@@ -0,0 +1,491 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * Partially based on southcluster.asl for other x86 platforms
+ */
+
+Device (PCI0)
+{
+    Name (_HID, EISAID("PNP0A08"))    /* PCIe */
+    Name (_CID, EISAID("PNP0A03"))    /* PCI */
+
+    Name (_ADR, Zero)
+    Name (_BBN, Zero)
+
+    Name (MCRS, ResourceTemplate()
+    {
+        /* Bus Numbers */
+        WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+        /* IO Region 0 */
+        WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+        /* PCI Config Space */
+        IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+        /* IO Region 1 */
+        WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+        /* GPIO Low Memory Region */
+        DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                Cacheable, ReadWrite,
+                0x00000000, 0x000ddcc0, 0x000ddccf, 0x00000000,
+                0x00000010, , , GP00)
+
+        /* PSH Memory Region 0 */
+        DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                Cacheable, ReadWrite,
+                0x00000000, 0x04819000, 0x04898fff, 0x00000000,
+                0x00080000, , , PSH0)
+
+        /* PSH Memory Region 1 */
+        DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                Cacheable, ReadWrite,
+                0x00000000, 0x04919000, 0x04920fff, 0x00000000,
+                0x00008000, , , PSH1)
+
+        /* SST Memory Region */
+        DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                Cacheable, ReadWrite,
+                0x00000000, 0x05e00000, 0x05ffffff, 0x00000000,
+                0x00200000, , , SST0)
+
+        /* PCI Memory Region */
+        DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+                Cacheable, ReadWrite,
+                0x00000000, 0x80000000, 0xffffffff, 0x00000000,
+                0x80000000, , , PMEM)
+    })
+
+    Method (_CRS, 0, Serialized)
+    {
+        Return (MCRS)
+    }
+
+    /* Device Resource Consumption */
+    Device (PDRC)
+    {
+        Name (_HID, EISAID("PNP0C02"))
+        Name (_UID, One)
+
+        Name (PDRS, ResourceTemplate()
+        {
+            Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+        })
+
+        Method (_CRS, 0, Serialized)
+        {
+            Return (PDRS)
+        }
+    }
+
+    Method (_OSC, 4)
+    {
+        /* Check for proper GUID */
+        If (LEqual(Arg0, ToUUID("33db4d5b-1ff7-401c-9657-7441c03dd766"))) {
+            /* Let OS control everything */
+            Return (Arg3)
+        } Else {
+            /* Unrecognized UUID */
+            CreateDWordField(Arg3, 0, CDW1)
+            Or(CDW1, 4, CDW1)
+            Return (Arg3)
+        }
+    }
+
+    Device (SDHC)
+    {
+        Name (_ADR, 0x00010003)
+        Name (_DEP, Package (0x01)
+        {
+            GPIO
+        })
+        Name (PSTS, Zero)
+
+        Method (_STA)
+        {
+            Return (STA_VISIBLE)
+        }
+
+        Method (_PS3, 0, NotSerialized)
+        {
+        }
+
+        Method (_PS0, 0, NotSerialized)
+        {
+            If (PSTS == Zero)
+            {
+                If (^^GPIO.AVBL == One)
+                {
+                    ^^GPIO.WFD3 = One
+                    PSTS = One
+                }
+            }
+        }
+
+        /* BCM43340 */
+        Device (BRC1)
+        {
+            Name (_ADR, 0x01)
+            Name (_DEP, Package (0x01)
+            {
+                GPIO
+            })
+
+            Method (_STA)
+            {
+                Return (STA_VISIBLE)
+            }
+
+            Method (_RMV, 0, NotSerialized)
+            {
+                Return (Zero)
+            }
+
+            Method (_PS3, 0, NotSerialized)
+            {
+                If (^^^GPIO.AVBL == One)
+                {
+                    ^^^GPIO.WFD3 = Zero
+                    PSTS = Zero
+                }
+            }
+
+            Method (_PS0, 0, NotSerialized)
+            {
+                If (PSTS == Zero)
+                {
+                    If (^^^GPIO.AVBL == One)
+                    {
+                        ^^^GPIO.WFD3 = One
+                        PSTS = One
+                    }
+                }
+            }
+        }
+
+        Device (BRC2)
+        {
+            Name (_ADR, 0x02)
+            Method (_STA, 0, NotSerialized)
+            {
+                Return (STA_VISIBLE)
+            }
+
+            Method (_RMV, 0, NotSerialized)
+            {
+                Return (Zero)
+            }
+        }
+    }
+
+    Device (SPI5)
+    {
+        Name (_ADR, 0x00070001)
+        Name (RBUF, ResourceTemplate()
+        {
+            GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
+                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 110 }
+            GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
+                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 111 }
+            GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
+                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 112 }
+            GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly,
+                "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 113 }
+
+            FixedDMA(0x000d, 0x0002, Width32bit, )
+            FixedDMA(0x000c, 0x0003, Width32bit, )
+        })
+
+        Method (_CRS, 0, NotSerialized)
+        {
+            Return (RBUF)
+        }
+
+        /*
+         * See
+         * http://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt
+         * for more information about GPIO bindings.
+         */
+        Name (_DSD, Package () {
+            ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {
+                    "cs-gpios", Package () {
+                        ^SPI5, 0, 0, 0,
+                        ^SPI5, 1, 0, 0,
+                        ^SPI5, 2, 0, 0,
+                        ^SPI5, 3, 0, 0,
+                    },
+                },
+            }
+        })
+
+        Method (_STA, 0, NotSerialized)
+        {
+            Return (STA_VISIBLE)
+        }
+    }
+
+    Device (I2C1)
+    {
+        Name (_ADR, 0x00080000)
+
+        Method (_STA, 0, NotSerialized)
+        {
+            Return (STA_VISIBLE)
+        }
+
+        Name (RBUF, ResourceTemplate()
+        {
+            FixedDMA(0x0009, 0x0000, Width32bit, )
+            FixedDMA(0x0008, 0x0001, Width32bit, )
+        })
+
+        Method (_CRS, 0, NotSerialized)
+        {
+            Return (RBUF)
+        }
+    }
+
+    Device (I2C6)
+    {
+        Name (_ADR, 0x00090001)
+
+        Method (_STA, 0, NotSerialized)
+        {
+            Return (STA_VISIBLE)
+        }
+    }
+
+    Device (GPIO)
+    {
+        Name (_ADR, 0x000c0000)
+
+        Method (_STA)
+        {
+            Return (STA_VISIBLE)
+        }
+
+        Name (AVBL, Zero)
+        Method (_REG, 2, NotSerialized)
+        {
+            If (Arg0 == 0x08)
+            {
+                AVBL = Arg1
+            }
+        }
+
+        OperationRegion (GPOP, GeneralPurposeIo, 0, 1)
+        Field (GPOP, ByteAcc, NoLock, Preserve)
+        {
+            Connection (
+                GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
+                    "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 96 }
+            ),
+            WFD3, 1,
+        }
+    }
+
+    Device (PWM0)
+    {
+        Name (_ADR, 0x00170000)
+
+        Method (_STA, 0, NotSerialized)
+        {
+            Return (STA_VISIBLE)
+        }
+    }
+
+    Device (HSU0)
+    {
+        Name (_ADR, 0x00040001)
+
+        Method (_STA, 0, NotSerialized)
+        {
+            Return (STA_VISIBLE)
+        }
+
+        Device (BTH0)
+        {
+            Name (_HID, "BCM2E95")
+            Name (_DEP, Package ()
+            {
+                GPIO,
+                HSU0
+            })
+
+            Method (_STA, 0, NotSerialized)
+            {
+                Return (STA_VISIBLE)
+            }
+
+            Method (_CRS, 0, Serialized)
+            {
+                Name (RBUF, ResourceTemplate()
+                {
+                    UartSerialBus(0x0001C200, DataBitsEight, StopBitsOne,
+                        0xFC, LittleEndian, ParityTypeNone, FlowControlHardware,
+                        0x20, 0x20, "\\_SB.PCI0.HSU0", 0, ResourceConsumer, , )
+                    GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0,
+                        "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 185 }
+                    GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
+                        "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 184 }
+                    GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly,
+                        "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 71 }
+                })
+                Return (RBUF)
+            }
+
+            Name (_DSD, Package () {
+                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+                Package () {
+                    Package () { "host-wakeup-gpios", Package () { ^BTH0, 0, 0, 0 } },
+                    Package () { "device-wakeup-gpios", Package () { ^BTH0, 1, 0, 0 } },
+                    Package () { "shutdown-gpios", Package () { ^BTH0, 2, 0, 0 } },
+                }
+            })
+        }
+    }
+
+    Device (IPC1)
+    {
+        Name (_ADR, 0x00130000)
+
+        Method (_STA, 0, NotSerialized)
+        {
+            Return (STA_VISIBLE)
+        }
+
+        Device (PMIC)
+        {
+            Name (_ADR, Zero)
+            Name (_HID, "INTC100E")
+            Name (_CID, "INTC100E")
+            Name (_DDN, "Basin Cove PMIC")
+            Name (_DEP, Package ()
+            {
+                IPC1
+            })
+
+            Method (_STA, 0, NotSerialized)
+            {
+                Return (STA_VISIBLE)
+            }
+
+            Method (_CRS, 0, Serialized)
+            {
+                Name (RBUF, ResourceTemplate()
+                {
+                    /*
+                     * Shadow registers in SRAM for PMIC:
+                     *   SRAM    PMIC register
+                     *   --------------------
+                     *   0x00-    Unknown
+                     *   0x03    THRMIRQ (0x04)
+                     *   0x04    BCUIRQ (0x05)
+                     *   0x05    ADCIRQ (0x06)
+                     *   0x06    CHGRIRQ0 (0x07)
+                     *   0x07    CHGRIRQ1 (0x08)
+                     *   0x08-    Unknown
+                     *   0x0a    PBSTATUS (0x27)
+                     *   0x0b-    Unknown
+                     */
+                    Memory32Fixed(ReadWrite, 0xFFFFF610, 0x00000010)
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 30 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 23 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 52 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 51 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 50 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 27 }
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 49 }
+                })
+                Return (RBUF)
+            }
+
+            OperationRegion (PMOP, 0x8D, Zero, 0x0100)
+            Field (PMOP, DWordAcc, NoLock, Preserve)
+            {
+                SEL1,   32,
+                SEL2,   32,
+                VCCL,   32,
+                VNNL,   32,
+                AONL,   32,
+                CNTC,   32,
+                CNTN,   32,
+                AONN,   32,
+                CNT1,   32,
+                CNT2,   32,
+                CNT3,   32,
+                FLEX,   32,
+                PRG1,   32,
+                PRG2,   32,
+                PRG3,   32,
+                VLDO,   32,
+            }
+
+            Name (AVBL, Zero)
+            Method (_REG, 2, NotSerialized)
+            {
+                If ((Arg0 == 0x8D))
+                {
+                    AVBL = Arg1
+                }
+            }
+        }
+    }
+
+    Device (GDMA)
+    {
+        Name (_ADR, 0x00150000)
+        Name (_HID, "808611A2")
+        Name (_UID, Zero)
+
+        Method (_STA, 0, NotSerialized)
+        {
+            Return (STA_VISIBLE)
+        }
+
+        Method (_CRS, 0, Serialized)
+        {
+            Name (RBUF, ResourceTemplate ()
+            {
+                    Memory32Fixed(ReadWrite, 0xFF192000, 0x00001000)
+                    Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 32 }
+            })
+            Return (RBUF)
+        }
+    }
+}
+
+Device (FLIS)
+{
+    Name (_HID, "INTC1002")
+    Name (_DDN, "Intel Merrifield Family-Level Interface Shim")
+    Name (RBUF, ResourceTemplate()
+    {
+        Memory32Fixed(ReadWrite, 0xFF0C0000, 0x00008000)
+        PinGroup("spi5", ResourceProducer, ) { 90, 91, 92, 93, 94, 95, 96 }
+        PinGroup("uart0", ResourceProducer, ) { 115, 116, 117, 118 }
+        PinGroup("uart1", ResourceProducer, ) { 119, 120, 121, 122 }
+        PinGroup("uart2", ResourceProducer, ) { 123, 124, 125, 126 }
+        PinGroup("pwm0", ResourceProducer, ) { 144 }
+        PinGroup("pwm1", ResourceProducer, ) { 145 }
+        PinGroup("pwm2", ResourceProducer, ) { 132 }
+        PinGroup("pwm3", ResourceProducer, ) { 133 }
+    })
+
+    Method (_CRS, 0, NotSerialized)
+    {
+        Return (RBUF)
+    }
+
+    Method (_STA, 0, NotSerialized)
+    {
+        Return (STA_VISIBLE)
+    }
+}
diff --git a/arch/x86/include/asm/arch-tangier/global_nvs.h b/arch/x86/include/asm/arch-tangier/global_nvs.h
new file mode 100644
index 0000000..a7811a3
--- /dev/null
+++ b/arch/x86/include/asm/arch-tangier/global_nvs.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * Partially based on global_nvs.h for other x86 platforms
+ */
+
+#ifndef _GLOBAL_NVS_H_
+#define _GLOBAL_NVS_H_
+
+struct __packed acpi_global_nvs {
+	u8	pcnt;		/* processor count */
+
+	/*
+	 * Add padding so sizeof(struct acpi_global_nvs) == 0x100.
+	 * This must match the size defined in the global_nvs.asl.
+	 */
+	u8	rsvd[255];
+};
+
+#endif /* _GLOBAL_NVS_H_ */
diff --git a/arch/x86/include/asm/arch-tangier/iomap.h b/arch/x86/include/asm/arch-tangier/iomap.h
new file mode 100644
index 0000000..b0fc03e
--- /dev/null
+++ b/arch/x86/include/asm/arch-tangier/iomap.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Copyright (c) 2019 Intel Corporation */
+
+#ifndef _TANGIER_IOMAP_H
+#define _TANGIER_IOMAP_H
+
+#define MCFG_BASE_ADDRESS	0x3f500000
+#define MCFG_BASE_SIZE		0x00100000
+
+#endif	/* _TANGIER_IOMAP_H */
diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h
new file mode 100644
index 0000000..806f787
--- /dev/null
+++ b/arch/x86/include/asm/atomic.h
@@ -0,0 +1,115 @@
+#ifndef _ASM_X86_ATOMIC_H
+#define _ASM_X86_ATOMIC_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/processor.h>
+
+typedef struct { volatile int counter; } atomic_t;
+
+/*
+ * Atomic operations that C can't guarantee us.  Useful for
+ * resource counting etc..
+ */
+
+#define ATOMIC_INIT(i)	{ (i) }
+
+/**
+ * atomic_read - read atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically reads the value of @v.
+ */
+static inline int atomic_read(const atomic_t *v)
+{
+	return ACCESS_ONCE((v)->counter);
+}
+
+/**
+ * atomic_set - set atomic variable
+ * @v: pointer of type atomic_t
+ * @i: required value
+ *
+ * Atomically sets the value of @v to @i.
+ */
+static inline void atomic_set(atomic_t *v, int i)
+{
+	v->counter = i;
+}
+
+/**
+ * atomic_add - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v.
+ */
+static inline void atomic_add(int i, atomic_t *v)
+{
+	asm volatile(LOCK_PREFIX "addl %1,%0"
+		     : "+m" (v->counter)
+		     : "ir" (i));
+}
+
+/**
+ * atomic_sub - subtract integer from atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v.
+ */
+static inline void atomic_sub(int i, atomic_t *v)
+{
+	asm volatile(LOCK_PREFIX "subl %1,%0"
+		     : "+m" (v->counter)
+		     : "ir" (i));
+}
+
+/**
+ * atomic_inc - increment atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1.
+ */
+static inline void atomic_inc(atomic_t *v)
+{
+	asm volatile(LOCK_PREFIX "incl %0"
+		     : "+m" (v->counter));
+}
+
+/**
+ * atomic_dec - decrement atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1.
+ */
+static inline void atomic_dec(atomic_t *v)
+{
+	asm volatile(LOCK_PREFIX "decl %0"
+		     : "+m" (v->counter));
+}
+
+/**
+ * atomic_inc_short - increment of a short integer
+ * @v: pointer to type int
+ *
+ * Atomically adds 1 to @v
+ * Returns the new value of @u
+ */
+static inline short int atomic_inc_short(short int *v)
+{
+	asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v));
+	return *v;
+}
+
+/* These are x86-specific, used by some header files */
+#define atomic_clear_mask(mask, addr)				\
+	asm volatile(LOCK_PREFIX "andl %0,%1"			\
+		     : : "r" (~(mask)), "m" (*(addr)) : "memory")
+
+#define atomic_set_mask(mask, addr)				\
+	asm volatile(LOCK_PREFIX "orl %0,%1"			\
+		     : : "r" ((unsigned)(mask)), "m" (*(addr))	\
+		     : "memory")
+
+#endif /* _ASM_X86_ATOMIC_H */
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
new file mode 100644
index 0000000..196fcf9
--- /dev/null
+++ b/arch/x86/include/asm/bitops.h
@@ -0,0 +1,410 @@
+#ifndef _I386_BITOPS_H
+#define _I386_BITOPS_H
+
+/*
+ * Copyright 1992, Linus Torvalds.
+ */
+
+
+/*
+ * These have to be done with inline assembly: that way the bit-setting
+ * is guaranteed to be atomic. All bit operations return 0 if the bit
+ * was cleared before the operation and != 0 if it was not.
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ */
+
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+
+#ifdef CONFIG_SMP
+#define LOCK_PREFIX "lock ; "
+#else
+#define LOCK_PREFIX ""
+#endif
+
+#define ADDR (*(volatile long *) addr)
+
+/**
+ * set_bit - Atomically set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * This function is atomic and may not be reordered.  See __set_bit()
+ * if you do not require the atomic guarantees.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static __inline__ void set_bit(int nr, volatile void * addr)
+{
+	__asm__ __volatile__( LOCK_PREFIX
+		"btsl %1,%0"
+		:"=m" (ADDR)
+		:"Ir" (nr));
+}
+
+/**
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static __inline__ void __set_bit(int nr, volatile void * addr)
+{
+	__asm__(
+		"btsl %1,%0"
+		:"=m" (ADDR)
+		:"Ir" (nr));
+}
+
+#define PLATFORM__SET_BIT
+
+/**
+ * clear_bit - Clears a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * clear_bit() is atomic and may not be reordered.  However, it does
+ * not contain a memory barrier, so if it is used for locking purposes,
+ * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
+ * in order to ensure changes are visible on other processors.
+ */
+static __inline__ void clear_bit(int nr, volatile void * addr)
+{
+	__asm__ __volatile__( LOCK_PREFIX
+		"btrl %1,%0"
+		:"=m" (ADDR)
+		:"Ir" (nr));
+}
+#define smp_mb__before_clear_bit()	barrier()
+#define smp_mb__after_clear_bit()	barrier()
+
+/**
+ * __change_bit - Toggle a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike change_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static __inline__ void __change_bit(int nr, volatile void * addr)
+{
+	__asm__ __volatile__(
+		"btcl %1,%0"
+		:"=m" (ADDR)
+		:"Ir" (nr));
+}
+
+/**
+ * change_bit - Toggle a bit in memory
+ * @nr: Bit to clear
+ * @addr: Address to start counting from
+ *
+ * change_bit() is atomic and may not be reordered.
+ * Note that @nr may be almost arbitrarily large; this function is not
+ * restricted to acting on a single-word quantity.
+ */
+static __inline__ void change_bit(int nr, volatile void * addr)
+{
+	__asm__ __volatile__( LOCK_PREFIX
+		"btcl %1,%0"
+		:"=m" (ADDR)
+		:"Ir" (nr));
+}
+
+/**
+ * test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int test_and_set_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__ __volatile__( LOCK_PREFIX
+		"btsl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr) : "memory");
+	return oldbit;
+}
+
+/**
+ * __test_and_set_bit - Set a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__(
+		"btsl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr));
+	return oldbit;
+}
+
+/**
+ * test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__ __volatile__( LOCK_PREFIX
+		"btrl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr) : "memory");
+	return oldbit;
+}
+
+/**
+ * __test_and_clear_bit - Clear a bit and return its old value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is non-atomic and can be reordered.
+ * If two examples of this operation race, one can appear to succeed
+ * but actually fail.  You must protect multiple accesses with a lock.
+ */
+static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__(
+		"btrl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr));
+	return oldbit;
+}
+
+/* WARNING: non atomic and it can be reordered! */
+static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__ __volatile__(
+		"btcl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr) : "memory");
+	return oldbit;
+}
+
+/**
+ * test_and_change_bit - Change a bit and return its new value
+ * @nr: Bit to set
+ * @addr: Address to count from
+ *
+ * This operation is atomic and cannot be reordered.
+ * It also implies a memory barrier.
+ */
+static __inline__ int test_and_change_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__ __volatile__( LOCK_PREFIX
+		"btcl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit),"=m" (ADDR)
+		:"Ir" (nr) : "memory");
+	return oldbit;
+}
+
+#if 0 /* Fool kernel-doc since it doesn't do macros yet */
+/**
+ * test_bit - Determine whether a bit is set
+ * @nr: bit number to test
+ * @addr: Address to start counting from
+ */
+static int test_bit(int nr, const volatile void * addr);
+#endif
+
+static __inline__ int constant_test_bit(int nr, const volatile void * addr)
+{
+	return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
+}
+
+static __inline__ int variable_test_bit(int nr, volatile void * addr)
+{
+	int oldbit;
+
+	__asm__ __volatile__(
+		"btl %2,%1\n\tsbbl %0,%0"
+		:"=r" (oldbit)
+		:"m" (ADDR),"Ir" (nr));
+	return oldbit;
+}
+
+#define test_bit(nr,addr) \
+(__builtin_constant_p(nr) ? \
+ constant_test_bit((nr),(addr)) : \
+ variable_test_bit((nr),(addr)))
+
+/**
+ * find_first_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to start the search at
+ * @size: The maximum size to search
+ *
+ * Returns the bit-number of the first zero bit, not the number of the byte
+ * containing a bit.
+ */
+static __inline__ int find_first_zero_bit(void * addr, unsigned size)
+{
+	int d0, d1, d2;
+	int res;
+
+	if (!size)
+		return 0;
+	/* This looks at memory. Mark it volatile to tell gcc not to move it around */
+	__asm__ __volatile__(
+		"movl $-1,%%eax\n\t"
+		"xorl %%edx,%%edx\n\t"
+		"repe; scasl\n\t"
+		"je 1f\n\t"
+		"xorl -4(%%edi),%%eax\n\t"
+		"subl $4,%%edi\n\t"
+		"bsfl %%eax,%%edx\n"
+		"1:\tsubl %%ebx,%%edi\n\t"
+		"shll $3,%%edi\n\t"
+		"addl %%edi,%%edx"
+		:"=d" (res), "=&c" (d0), "=&D" (d1), "=&a" (d2)
+		:"1" ((size + 31) >> 5), "2" (addr), "b" (addr));
+	return res;
+}
+
+/**
+ * find_next_zero_bit - find the first zero bit in a memory region
+ * @addr: The address to base the search on
+ * @offset: The bitnumber to start searching at
+ * @size: The maximum size to search
+ */
+static __inline__ int find_next_zero_bit (void * addr, int size, int offset)
+{
+	unsigned long * p = ((unsigned long *) addr) + (offset >> 5);
+	int set = 0, bit = offset & 31, res;
+
+	if (bit) {
+		/*
+		 * Look for zero in first byte
+		 */
+		__asm__("bsfl %1,%0\n\t"
+			"jne 1f\n\t"
+			"movl $32, %0\n"
+			"1:"
+			: "=r" (set)
+			: "r" (~(*p >> bit)));
+		if (set < (32 - bit))
+			return set + offset;
+		set = 32 - bit;
+		p++;
+	}
+	/*
+	 * No zero yet, search remaining full bytes for a zero
+	 */
+	res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr));
+	return (offset + set + res);
+}
+
+/**
+ * ffz - find first zero in word.
+ * @word: The word to search
+ *
+ * Undefined if no zero exists, so code should check against ~0UL first.
+ */
+static __inline__ unsigned long ffz(unsigned long word)
+{
+	__asm__("bsfl %1,%0"
+		:"=r" (word)
+		:"r" (~word));
+	return word;
+}
+
+#ifdef __KERNEL__
+
+/**
+ * __ffs - find first set bit in word
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static inline unsigned long __ffs(unsigned long word)
+{
+	__asm__("rep; bsf %1,%0"
+		: "=r" (word)
+		: "rm" (word));
+	return word;
+}
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static __inline__ int ffs(int x)
+{
+	int r;
+
+	__asm__("bsfl %1,%0\n\t"
+		"jnz 1f\n\t"
+		"movl $-1,%0\n"
+		"1:" : "=r" (r) : "rm" (x));
+
+	return r+1;
+}
+#define PLATFORM_FFS
+
+static inline int __ilog2(unsigned int x)
+{
+	return generic_fls(x) - 1;
+}
+
+/**
+ * hweightN - returns the hamming weight of a N-bit word
+ * @x: the word to weigh
+ *
+ * The Hamming Weight of a number is the total number of bits set in it.
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __KERNEL__ */
+
+#ifdef __KERNEL__
+
+#define ext2_set_bit                 __test_and_set_bit
+#define ext2_clear_bit               __test_and_clear_bit
+#define ext2_test_bit                test_bit
+#define ext2_find_first_zero_bit     find_first_zero_bit
+#define ext2_find_next_zero_bit      find_next_zero_bit
+
+/* Bitmap functions for the minix filesystem.  */
+#define minix_test_and_set_bit(nr,addr) __test_and_set_bit(nr,addr)
+#define minix_set_bit(nr,addr) __set_bit(nr,addr)
+#define minix_test_and_clear_bit(nr,addr) __test_and_clear_bit(nr,addr)
+#define minix_test_bit(nr,addr) test_bit(nr,addr)
+#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
+
+#endif /* __KERNEL__ */
+
+#endif /* _I386_BITOPS_H */
diff --git a/arch/x86/include/asm/bootm.h b/arch/x86/include/asm/bootm.h
new file mode 100644
index 0000000..bd8ce55
--- /dev/null
+++ b/arch/x86/include/asm/bootm.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013, Google Inc.
+ */
+
+#ifndef ARM_BOOTM_H
+#define ARM_BOOTM_H
+
+void bootm_announce_and_cleanup(void);
+
+/**
+ * boot_linux_kernel() - boot a linux kernel
+ *
+ * This boots a kernel image, either 32-bit or 64-bit. It will also work with
+ * a self-extracting kernel, if you set @image_64bit to false.
+ *
+ * @setup_base:		Pointer to the setup.bin information for the kernel
+ * @load_address:	Pointer to the start of the kernel image
+ * @image_64bit:	true if the image is a raw 64-bit kernel, false if it
+ *			is raw 32-bit or any type of self-extracting kernel
+ *			such as a bzImage.
+ * @return -ve error code. This function does not return if the kernel was
+ * booted successfully.
+ */
+int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit);
+
+#endif
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
new file mode 100644
index 0000000..d961ddd
--- /dev/null
+++ b/arch/x86/include/asm/bootparam.h
@@ -0,0 +1,128 @@
+#ifndef _ASM_X86_BOOTPARAM_H
+#define _ASM_X86_BOOTPARAM_H
+
+#include <linux/types.h>
+#include <linux/screen_info.h>
+#include <linux/apm_bios.h>
+#include <linux/edd.h>
+#include <asm/e820.h>
+#include <asm/ist.h>
+#include <asm/video/edid.h>
+
+/* setup data types */
+enum {
+	SETUP_NONE = 0,
+	SETUP_E820_EXT,
+	SETUP_DTB,
+};
+
+/* extensible setup data list node */
+struct setup_data {
+	__u64 next;
+	__u32 type;
+	__u32 len;
+	__u8 data[0];
+};
+
+struct setup_header {
+	__u8	setup_sects;
+	__u16	root_flags;
+	__u32	syssize;
+	__u16	ram_size;
+#define RAMDISK_IMAGE_START_MASK	0x07FF
+#define RAMDISK_PROMPT_FLAG		0x8000
+#define RAMDISK_LOAD_FLAG		0x4000
+	__u16	vid_mode;
+	__u16	root_dev;
+	__u16	boot_flag;
+	__u16	jump;
+	__u32	header;
+	__u16	version;
+	__u32	realmode_swtch;
+	__u16	start_sys;
+	__u16	kernel_version;
+	__u8	type_of_loader;
+	__u8	loadflags;
+#define LOADED_HIGH	(1<<0)
+#define QUIET_FLAG	(1<<5)
+#define KEEP_SEGMENTS	(1<<6)
+#define CAN_USE_HEAP	(1<<7)
+	__u16	setup_move_size;
+	__u32	code32_start;
+	__u32	ramdisk_image;
+	__u32	ramdisk_size;
+	__u32	bootsect_kludge;
+	__u16	heap_end_ptr;
+	__u8	ext_loader_ver;
+	__u8	ext_loader_type;
+	__u32	cmd_line_ptr;
+	__u32	initrd_addr_max;
+	__u32	kernel_alignment;
+	__u8	relocatable_kernel;
+	__u8	_pad2[3];
+	__u32	cmdline_size;
+	__u32	hardware_subarch;
+	__u64	hardware_subarch_data;
+	__u32	payload_offset;
+	__u32	payload_length;
+	__u64	setup_data;
+	__u64	pref_address;
+	__u32	init_size;
+	__u32	handover_offset;
+} __attribute__((packed));
+
+struct sys_desc_table {
+	__u16 length;
+	__u8  table[14];
+};
+
+struct efi_info {
+	__u32 efi_loader_signature;
+	__u32 efi_systab;
+	__u32 efi_memdesc_size;
+	__u32 efi_memdesc_version;
+	__u32 efi_memmap;
+	__u32 efi_memmap_size;
+	__u32 efi_systab_hi;
+	__u32 efi_memmap_hi;
+};
+
+/* The so-called "zeropage" */
+struct boot_params {
+	struct screen_info screen_info;			/* 0x000 */
+	struct apm_bios_info apm_bios_info;		/* 0x040 */
+	__u8  _pad2[4];					/* 0x054 */
+	__u64  tboot_addr;				/* 0x058 */
+	struct ist_info ist_info;			/* 0x060 */
+	__u64 acpi_rsdp_addr;				/* 0x070 */
+	__u8  _pad3[8];					/* 0x078 */
+	__u8  hd0_info[16];	/* obsolete! */		/* 0x080 */
+	__u8  hd1_info[16];	/* obsolete! */		/* 0x090 */
+	struct sys_desc_table sys_desc_table;		/* 0x0a0 */
+	__u8  _pad4[144];				/* 0x0b0 */
+	struct edid_info edid_info;			/* 0x140 */
+	struct efi_info efi_info;			/* 0x1c0 */
+	__u32 alt_mem_k;				/* 0x1e0 */
+	__u32 scratch;		/* Scratch field! */	/* 0x1e4 */
+	__u8  e820_entries;				/* 0x1e8 */
+	__u8  eddbuf_entries;				/* 0x1e9 */
+	__u8  edd_mbr_sig_buf_entries;			/* 0x1ea */
+	__u8  _pad6[6];					/* 0x1eb */
+	struct setup_header hdr;    /* setup header */	/* 0x1f1 */
+	__u8  _pad7[0x290-0x1f1-sizeof(struct setup_header)];
+	__u32 edd_mbr_sig_buffer[EDD_MBR_SIG_MAX];	/* 0x290 */
+	struct e820_entry e820_map[E820MAX];		/* 0x2d0 */
+	__u8  _pad8[48];				/* 0xcd0 */
+	struct edd_info eddbuf[EDDMAXNR];		/* 0xd00 */
+	__u8  _pad9[276];				/* 0xeec */
+} __attribute__((packed));
+
+enum {
+	X86_SUBARCH_PC = 0,
+	X86_SUBARCH_LGUEST,
+	X86_SUBARCH_XEN,
+	X86_SUBARCH_INTEL_MID,
+	X86_SUBARCH_CE4100,
+	X86_NR_SUBARCHS,
+};
+#endif /* _ASM_X86_BOOTPARAM_H */
diff --git a/arch/x86/include/asm/byteorder.h b/arch/x86/include/asm/byteorder.h
new file mode 100644
index 0000000..a2d1fd8
--- /dev/null
+++ b/arch/x86/include/asm/byteorder.h
@@ -0,0 +1,44 @@
+#ifndef _I386_BYTEORDER_H
+#define _I386_BYTEORDER_H
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+
+static __inline__ __u32 ___arch__swab32(__u32 x)
+{
+	__asm__("bswap %0" : "=r" (x) : "0" (x));
+
+	return x;
+}
+
+#define _constant_swab16(x) ((__u16)(				\
+	(((__u16)(x) & (__u16)0x00ffU) << 8) |			\
+	(((__u16)(x) & (__u16)0xff00U) >> 8)))
+
+static __inline__ __u16 ___arch__swab16(__u16 x)
+{
+#if CONFIG_IS_ENABLED(X86_64)
+	return _constant_swab16(x);
+#else
+	__asm__("xchgb %b0,%h0"		/* swap bytes		*/ \
+		: "=q" (x) \
+		:  "0" (x)); \
+		return x;
+#endif
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __GNUC__ */
+
+#include <linux/byteorder/little_endian.h>
+
+#endif /* _I386_BYTEORDER_H */
diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h
new file mode 100644
index 0000000..145b878
--- /dev/null
+++ b/arch/x86/include/asm/cache.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __X86_CACHE_H__
+#define __X86_CACHE_H__
+
+/*
+ * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
+ * use 64-bytes, a safe default for x86.
+ */
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#endif
+
+#define ARCH_DMA_MINALIGN		CONFIG_SYS_CACHELINE_SIZE
+
+static inline void wbinvd(void)
+{
+	asm volatile ("wbinvd" : : : "memory");
+}
+
+static inline void invd(void)
+{
+	asm volatile("invd" : : : "memory");
+}
+
+/* Enable caches and write buffer */
+void enable_caches(void);
+
+/* Disable caches and write buffer */
+void disable_caches(void);
+
+#endif /* __X86_CACHE_H__ */
diff --git a/arch/x86/include/asm/cmos_layout.h b/arch/x86/include/asm/cmos_layout.h
new file mode 100644
index 0000000..e2f6d18
--- /dev/null
+++ b/arch/x86/include/asm/cmos_layout.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __CMOS_LAYOUT_H
+#define __CMOS_LAYOUT_H
+
+/*
+ * The RTC internal registers and RAM is organized as two banks of 128 bytes
+ * each, called the standard and extended banks. The first 14 bytes of the
+ * standard bank contain the RTC time and date information along with four
+ * registers, A - D, that are used for configuration of the RTC. The extended
+ * bank contains a full 128 bytes of battery backed SRAM.
+ *
+ * For simplicity in U-Boot we only support CMOS in the standard bank, and
+ * its base address starts from offset 0x10, which leaves us 112 bytes space.
+ */
+#define CMOS_BASE		0x10
+
+/*
+ * The file records all offsets off CMOS_BASE that is currently used by
+ * U-Boot for various reasons. It is put in such a unified place in order
+ * to be consistent across platforms.
+ */
+
+/* stack address for S3 boot in a FSP configuration, 4 bytes */
+#define CMOS_FSP_STACK_ADDR	CMOS_BASE
+
+#endif /* __CMOS_LAYOUT_H */
diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h
new file mode 100644
index 0000000..7ea4436
--- /dev/null
+++ b/arch/x86/include/asm/config.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#endif
diff --git a/arch/x86/include/asm/control_regs.h b/arch/x86/include/asm/control_regs.h
new file mode 100644
index 0000000..44b8ba2
--- /dev/null
+++ b/arch/x86/include/asm/control_regs.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * (C) Copyright 2008-2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * Portions of this file are derived from the Linux kernel source
+ *  Copyright (C) 1991, 1992  Linus Torvalds
+ */
+
+#ifndef __X86_CONTROL_REGS_H
+#define __X86_CONTROL_REGS_H
+
+/*
+ * The memory clobber prevents the GCC from reordering the read/write order
+ * of CR0
+*/
+static inline unsigned long read_cr0(void)
+{
+	unsigned long val;
+
+	asm volatile ("movl %%cr0, %0" : "=r" (val) : : "memory");
+	return val;
+}
+
+static inline void write_cr0(unsigned long val)
+{
+	asm volatile ("movl %0, %%cr0" : : "r" (val) : "memory");
+}
+
+static inline unsigned long read_cr2(void)
+{
+	unsigned long val;
+
+	asm volatile("mov %%cr2,%0\n\t" : "=r" (val) : : "memory");
+	return val;
+}
+
+static inline unsigned long read_cr3(void)
+{
+	unsigned long val;
+
+	asm volatile("mov %%cr3,%0\n\t" : "=r" (val) : : "memory");
+	return val;
+}
+
+static inline unsigned long read_cr4(void)
+{
+	unsigned long val;
+
+	asm volatile("mov %%cr4,%0\n\t" : "=r" (val) : : "memory");
+	return val;
+}
+
+static inline unsigned long get_debugreg(int regno)
+{
+	unsigned long val = 0;  /* Damn you, gcc! */
+
+	switch (regno) {
+	case 0:
+		asm("mov %%db0, %0" : "=r" (val));
+		break;
+	case 1:
+		asm("mov %%db1, %0" : "=r" (val));
+		break;
+	case 2:
+		asm("mov %%db2, %0" : "=r" (val));
+		break;
+	case 3:
+		asm("mov %%db3, %0" : "=r" (val));
+		break;
+	case 6:
+		asm("mov %%db6, %0" : "=r" (val));
+		break;
+	case 7:
+		asm("mov %%db7, %0" : "=r" (val));
+		break;
+	default:
+		val = 0;
+	}
+	return val;
+}
+
+#endif
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
new file mode 100644
index 0000000..2c54e24
--- /dev/null
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -0,0 +1,327 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ */
+
+#ifndef _COREBOOT_TABLES_H
+#define _COREBOOT_TABLES_H
+
+struct memory_area;
+
+struct cbuint64 {
+	u32 lo;
+	u32 hi;
+};
+
+struct cb_header {
+	u8 signature[4];
+	u32 header_bytes;
+	u32 header_checksum;
+	u32 table_bytes;
+	u32 table_checksum;
+	u32 table_entries;
+};
+
+struct cb_record {
+	u32 tag;
+	u32 size;
+};
+
+#define CB_TAG_UNUSED			0x0000
+#define CB_TAG_MEMORY			0x0001
+
+struct cb_memory_range {
+	struct cbuint64 start;
+	struct cbuint64 size;
+	u32 type;
+};
+
+#define CB_MEM_RAM			1
+#define CB_MEM_RESERVED			2
+#define CB_MEM_ACPI			3
+#define CB_MEM_NVS			4
+#define CB_MEM_UNUSABLE			5
+#define CB_MEM_VENDOR_RSVD		6
+#define CB_MEM_TABLE			16
+
+struct cb_memory {
+	u32 tag;
+	u32 size;
+	struct cb_memory_range map[0];
+};
+
+#define CB_TAG_HWRPB			0x0002
+
+struct cb_hwrpb {
+	u32 tag;
+	u32 size;
+	u64 hwrpb;
+};
+
+#define CB_TAG_MAINBOARD		0x0003
+
+struct cb_mainboard {
+	u32 tag;
+	u32 size;
+	u8 vendor_idx;
+	u8 part_number_idx;
+	u8 strings[0];
+};
+
+#define CB_TAG_VERSION			0x0004
+#define CB_TAG_EXTRA_VERSION		0x0005
+#define CB_TAG_BUILD			0x0006
+#define CB_TAG_COMPILE_TIME		0x0007
+#define CB_TAG_COMPILE_BY		0x0008
+#define CB_TAG_COMPILE_HOST		0x0009
+#define CB_TAG_COMPILE_DOMAIN		0x000a
+#define CB_TAG_COMPILER			0x000b
+#define CB_TAG_LINKER			0x000c
+#define CB_TAG_ASSEMBLER		0x000d
+
+struct cb_string {
+	u32 tag;
+	u32 size;
+	u8 string[0];
+};
+
+#define CB_TAG_SERIAL			0x000f
+
+struct cb_serial {
+	u32 tag;
+	u32 size;
+#define CB_SERIAL_TYPE_IO_MAPPED	1
+#define CB_SERIAL_TYPE_MEMORY_MAPPED	2
+	u32 type;
+	u32 baseaddr;
+	u32 baud;
+};
+
+#define CB_TAG_CONSOLE			0x0010
+
+struct cb_console {
+	u32 tag;
+	u32 size;
+	u16 type;
+};
+
+#define CB_TAG_CONSOLE_SERIAL8250	0
+#define CB_TAG_CONSOLE_VGA		1 /* OBSOLETE */
+#define CB_TAG_CONSOLE_BTEXT		2 /* OBSOLETE */
+#define CB_TAG_CONSOLE_LOGBUF		3
+#define CB_TAG_CONSOLE_SROM		4 /* OBSOLETE */
+#define CB_TAG_CONSOLE_EHCI		5
+
+#define CB_TAG_FORWARD			0x0011
+
+struct cb_forward {
+	u32 tag;
+	u32 size;
+	u64 forward;
+};
+
+#define CB_TAG_FRAMEBUFFER		0x0012
+
+struct cb_framebuffer {
+	u32 tag;
+	u32 size;
+	u64 physical_address;
+	u32 x_resolution;
+	u32 y_resolution;
+	u32 bytes_per_line;
+	u8 bits_per_pixel;
+	u8 red_mask_pos;
+	u8 red_mask_size;
+	u8 green_mask_pos;
+	u8 green_mask_size;
+	u8 blue_mask_pos;
+	u8 blue_mask_size;
+	u8 reserved_mask_pos;
+	u8 reserved_mask_size;
+};
+
+#define CB_TAG_GPIO			0x0013
+#define GPIO_MAX_NAME_LENGTH		16
+
+struct cb_gpio {
+	u32 port;
+	u32 polarity;
+	u32 value;
+	u8 name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct cb_gpios {
+	u32 tag;
+	u32 size;
+	u32 count;
+	struct cb_gpio gpios[0];
+};
+
+#define CB_TAG_FDT			0x0014
+
+struct cb_fdt {
+	uint32_t tag;
+	uint32_t size;	/* size of the entire entry */
+	/* the actual FDT gets placed here */
+};
+
+#define CB_TAG_VDAT			0x0015
+
+struct cb_vdat {
+	uint32_t tag;
+	uint32_t size;	/* size of the entire entry */
+	void *vdat_addr;
+	uint32_t vdat_size;
+};
+
+#define CB_TAG_TIMESTAMPS		0x0016
+#define CB_TAG_CBMEM_CONSOLE		0x0017
+#define CB_TAG_MRC_CACHE		0x0018
+
+struct cb_cbmem_tab {
+	uint32_t tag;
+	uint32_t size;
+	void *cbmem_tab;
+};
+
+#define CB_TAG_VBNV			0x0019
+
+struct cb_vbnv {
+	uint32_t tag;
+	uint32_t size;
+	uint32_t vbnv_start;
+	uint32_t vbnv_size;
+};
+
+#define CB_TAG_CMOS_OPTION_TABLE	0x00c8
+
+struct cb_cmos_option_table {
+	u32 tag;
+	u32 size;
+	u32 header_length;
+};
+
+#define CB_TAG_OPTION			0x00c9
+
+#define CMOS_MAX_NAME_LENGTH		32
+
+struct cb_cmos_entries {
+	u32 tag;
+	u32 size;
+	u32 bit;
+	u32 length;
+	u32 config;
+	u32 config_id;
+	u8 name[CMOS_MAX_NAME_LENGTH];
+};
+
+#define CB_TAG_OPTION_ENUM		0x00ca
+#define CMOS_MAX_TEXT_LENGTH		32
+
+struct cb_cmos_enums {
+	u32 tag;
+	u32 size;
+	u32 config_id;
+	u32 value;
+	u8 text[CMOS_MAX_TEXT_LENGTH];
+};
+
+#define CB_TAG_OPTION_DEFAULTS		0x00cb
+#define CMOS_IMAGE_BUFFER_SIZE		128
+
+struct cb_cmos_defaults {
+	u32 tag;
+	u32 size;
+	u32 name_length;
+	u8 name[CMOS_MAX_NAME_LENGTH];
+	u8 default_set[CMOS_IMAGE_BUFFER_SIZE];
+};
+
+#define CB_TAG_OPTION_CHECKSUM		0x00cc
+#define CHECKSUM_NONE			0
+#define CHECKSUM_PCBIOS			1
+
+struct	cb_cmos_checksum {
+	u32 tag;
+	u32 size;
+	u32 range_start;
+	u32 range_end;
+	u32 location;
+	u32 type;
+};
+
+/* Helpful macros */
+
+#define MEM_RANGE_COUNT(_rec) \
+	(((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
+
+#define MEM_RANGE_PTR(_rec, _idx) \
+	(((u8 *) (_rec)) + sizeof(*(_rec)) \
+	+ (sizeof((_rec)->map[0]) * (_idx)))
+
+#define MB_VENDOR_STRING(_mb) \
+	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
+
+#define MB_PART_STRING(_mb) \
+	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
+
+#define UNPACK_CB64(_in) \
+	((((u64) _in.hi) << 32) | _in.lo)
+
+#define CBMEM_TOC_RESERVED		512
+#define MAX_CBMEM_ENTRIES		16
+#define CBMEM_MAGIC			0x434f5245
+
+struct cbmem_entry {
+	u32 magic;
+	u32 id;
+	u64 base;
+	u64 size;
+} __packed;
+
+#define CBMEM_ID_FREESPACE		0x46524545
+#define CBMEM_ID_GDT			0x4c474454
+#define CBMEM_ID_ACPI			0x41435049
+#define CBMEM_ID_CBTABLE		0x43425442
+#define CBMEM_ID_PIRQ			0x49525154
+#define CBMEM_ID_MPTABLE		0x534d5054
+#define CBMEM_ID_RESUME			0x5245534d
+#define CBMEM_ID_RESUME_SCRATCH		0x52455343
+#define CBMEM_ID_SMBIOS			0x534d4254
+#define CBMEM_ID_TIMESTAMP		0x54494d45
+#define CBMEM_ID_MRCDATA		0x4d524344
+#define CBMEM_ID_CONSOLE		0x434f4e53
+#define CBMEM_ID_NONE			0x00000000
+
+/**
+ * high_table_reserve() - reserve configuration table in high memory
+ *
+ * This reserves configuration table in high memory.
+ *
+ * @return:	always 0
+ */
+int high_table_reserve(void);
+
+/**
+ * high_table_malloc() - allocate configuration table in high memory
+ *
+ * This allocates configuration table in high memory.
+ *
+ * @bytes:	size of configuration table to be allocated
+ * @return:	pointer to configuration table in high memory
+ */
+void *high_table_malloc(size_t bytes);
+
+/**
+ * write_coreboot_table() - write coreboot table
+ *
+ * This writes coreboot table at a given address.
+ *
+ * @addr:	start address to write coreboot table
+ * @cfg_tables:	pointer to configuration table memory area
+ */
+void write_coreboot_table(u32 addr, struct memory_area *cfg_tables);
+
+#endif
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
new file mode 100644
index 0000000..feee0f9
--- /dev/null
+++ b/arch/x86/include/asm/cpu.h
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 The Chromium OS Authors.
+ *
+ * Part of this file is adapted from coreboot
+ * src/arch/x86/include/arch/cpu.h and
+ * src/arch/x86/lib/cpu.c
+ */
+
+#ifndef _ASM_CPU_H
+#define _ASM_CPU_H
+
+enum {
+	X86_VENDOR_INVALID = 0,
+	X86_VENDOR_INTEL,
+	X86_VENDOR_CYRIX,
+	X86_VENDOR_AMD,
+	X86_VENDOR_UMC,
+	X86_VENDOR_NEXGEN,
+	X86_VENDOR_CENTAUR,
+	X86_VENDOR_RISE,
+	X86_VENDOR_TRANSMETA,
+	X86_VENDOR_NSC,
+	X86_VENDOR_SIS,
+	X86_VENDOR_ANY = 0xfe,
+	X86_VENDOR_UNKNOWN = 0xff
+};
+
+/* Global descriptor table (GDT) bits */
+enum {
+	GDT_4KB			= 1ULL << 55,
+	GDT_32BIT		= 1ULL << 54,
+	GDT_LONG		= 1ULL << 53,
+	GDT_PRESENT		= 1ULL << 47,
+	GDT_NOTSYS		= 1ULL << 44,
+	GDT_CODE		= 1ULL << 43,
+	GDT_LIMIT_LOW_SHIFT	= 0,
+	GDT_LIMIT_LOW_MASK	= 0xffff,
+	GDT_LIMIT_HIGH_SHIFT	= 48,
+	GDT_LIMIT_HIGH_MASK	= 0xf,
+	GDT_BASE_LOW_SHIFT	= 16,
+	GDT_BASE_LOW_MASK	= 0xffff,
+	GDT_BASE_HIGH_SHIFT	= 56,
+	GDT_BASE_HIGH_MASK	= 0xf,
+};
+
+/*
+ * System controllers in an x86 system. We mostly need to just find these and
+ * use them on PCI. At some point these might have their own uclass (e.g.
+ * UCLASS_VIDEO for the GMA device).
+ */
+enum {
+	X86_NONE,
+	X86_SYSCON_ME,		/* Intel Management Engine */
+	X86_SYSCON_PINCONF,	/* Intel x86 pin configuration */
+	X86_SYSCON_PMU,		/* Power Management Unit */
+	X86_SYSCON_SCU,		/* System Controller Unit */
+};
+
+struct cpuid_result {
+	uint32_t eax;
+	uint32_t ebx;
+	uint32_t ecx;
+	uint32_t edx;
+};
+
+/*
+ * Generic CPUID function
+ */
+static inline struct cpuid_result cpuid(int op)
+{
+	struct cpuid_result result;
+	asm volatile(
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
+		: "=a" (result.eax),
+		  "=S" (result.ebx),
+		  "=c" (result.ecx),
+		  "=d" (result.edx)
+		: "0" (op)
+		: "edi");
+	return result;
+}
+
+/*
+ * Generic Extended CPUID function
+ */
+static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
+{
+	struct cpuid_result result;
+	asm volatile(
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
+		: "=a" (result.eax),
+		  "=S" (result.ebx),
+		  "=c" (result.ecx),
+		  "=d" (result.edx)
+		: "0" (op), "2" (ecx)
+		: "edi");
+	return result;
+}
+
+/*
+ * CPUID functions returning a single datum
+ */
+static inline unsigned int cpuid_eax(unsigned int op)
+{
+	unsigned int eax;
+
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
+		: "=a" (eax)
+		: "0" (op)
+		: "ecx", "edx", "edi");
+	return eax;
+}
+
+static inline unsigned int cpuid_ebx(unsigned int op)
+{
+	unsigned int eax, ebx;
+
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
+		: "=a" (eax), "=S" (ebx)
+		: "0" (op)
+		: "ecx", "edx", "edi");
+	return ebx;
+}
+
+static inline unsigned int cpuid_ecx(unsigned int op)
+{
+	unsigned int eax, ecx;
+
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
+		: "=a" (eax), "=c" (ecx)
+		: "0" (op)
+		: "edx", "edi");
+	return ecx;
+}
+
+static inline unsigned int cpuid_edx(unsigned int op)
+{
+	unsigned int eax, edx;
+
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
+		: "=a" (eax), "=d" (edx)
+		: "0" (op)
+		: "ecx", "edi");
+	return edx;
+}
+
+#if !CONFIG_IS_ENABLED(X86_64)
+
+/* Standard macro to see if a specific flag is changeable */
+static inline int flag_is_changeable_p(uint32_t flag)
+{
+	uint32_t f1, f2;
+
+	asm(
+		"pushfl\n\t"
+		"pushfl\n\t"
+		"popl %0\n\t"
+		"movl %0,%1\n\t"
+		"xorl %2,%0\n\t"
+		"pushl %0\n\t"
+		"popfl\n\t"
+		"pushfl\n\t"
+		"popl %0\n\t"
+		"popfl\n\t"
+		: "=&r" (f1), "=&r" (f2)
+		: "ir" (flag));
+	return ((f1^f2) & flag) != 0;
+}
+#endif
+
+static inline void mfence(void)
+{
+	__asm__ __volatile__("mfence" : : : "memory");
+}
+
+/**
+ * cpu_enable_paging_pae() - Enable PAE-paging
+ *
+ * @cr3:	Value to set in cr3 (PDPT or PML4T)
+ */
+void cpu_enable_paging_pae(ulong cr3);
+
+/**
+ * cpu_disable_paging_pae() - Disable paging and PAE
+ */
+void cpu_disable_paging_pae(void);
+
+/**
+ * cpu_has_64bit() - Check if the CPU has 64-bit support
+ *
+ * @return 1 if this CPU supports long mode (64-bit), 0 if not
+ */
+int cpu_has_64bit(void);
+
+/**
+ * cpu_vendor_name() - Get CPU vendor name
+ *
+ * @vendor:	CPU vendor enumeration number
+ *
+ * @return:	Address to hold the CPU vendor name string
+ */
+const char *cpu_vendor_name(int vendor);
+
+#define CPU_MAX_NAME_LEN	49
+
+/**
+ * cpu_get_name() - Get the name of the current cpu
+ *
+ * @name: Place to put name, which must be CPU_MAX_NAME_LEN bytes including
+ * @return pointer to name, which will likely be a few bytes after the start
+ * of @name
+ * \0 terminator
+ */
+char *cpu_get_name(char *name);
+
+/**
+ * cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * This function is used internally - see cpu_jump_to_64bit() for a more
+ * useful function.
+ *
+ * @pgtable:	Address of 24KB area containing the page table
+ * @setup_base:	Pointer to the setup.bin information for the kernel
+ * @target:	Pointer to the start of the kernel image
+ */
+void cpu_call64(ulong pgtable, ulong setup_base, ulong target);
+
+/**
+ * cpu_call32() - Jump to a 32-bit entry point
+ *
+ * @code_seg32:	32-bit code segment to use (GDT offset, e.g. 0x20)
+ * @target:	Pointer to the start of the 32-bit U-Boot image/entry point
+ * @table:	Pointer to start of info table to pass to U-Boot
+ */
+void cpu_call32(ulong code_seg32, ulong target, ulong table);
+
+/**
+ * cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * @setup_base:	Pointer to the setup.bin information for the kernel
+ * @target:	Pointer to the start of the kernel image
+ */
+int cpu_jump_to_64bit(ulong setup_base, ulong target);
+
+/**
+ * cpu_jump_to_64bit_uboot() - special function to jump from SPL to U-Boot
+ *
+ * This handles calling from 32-bit SPL to 64-bit U-Boot.
+ *
+ * @target:	Address of U-Boot in RAM
+ */
+int cpu_jump_to_64bit_uboot(ulong target);
+
+/**
+ * cpu_get_family_model() - Get the family and model for the CPU
+ *
+ * @return the CPU ID masked with 0x0fff0ff0
+ */
+u32 cpu_get_family_model(void);
+
+/**
+ * cpu_get_stepping() - Get the stepping value for the CPU
+ *
+ * @return the CPU ID masked with 0xf
+ */
+u32 cpu_get_stepping(void);
+
+#endif
diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h
new file mode 100644
index 0000000..cdd99a9
--- /dev/null
+++ b/arch/x86/include/asm/cpu_common.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Common code for Intel CPUs
+ *
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __ASM_CPU_COMMON_H
+#define __ASM_CPU_COMMON_H
+
+/* Standard Intel bus clock is fixed at 100MHz */
+enum {
+	INTEL_BCLK_MHZ		= 100
+};
+
+struct cpu_info;
+
+/**
+ * cpu_common_init() - Set up common CPU init
+ *
+ * This reports BIST failure, enables the LAPIC, updates microcode, enables
+ * the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int cpu_common_init(void);
+
+/**
+ * cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate
+ *
+ * If a change is needed, this function will do a soft reset so it takes
+ * effect.
+ *
+ * Some details are available here:
+ * http://forum.hwbot.org/showthread.php?t=76092
+ *
+ * @return 0 if OK, -ve on error
+ */
+int cpu_set_flex_ratio_to_tdp_nominal(void);
+
+/**
+ * cpu_intel_get_info() - Obtain CPU info for Intel CPUs
+ *
+ * Most Intel CPUs use the same MSR to obtain the clock speed, and use the same
+ * features. This function fills in these values, given the value of the base
+ * clock in MHz (typically this should be set to 100).
+ *
+ * @info:	cpu_info struct to fill in
+ * @bclk_mz:	the base clock in MHz
+ *
+ * @return 0 always
+ */
+int cpu_intel_get_info(struct cpu_info *info, int bclk_mz);
+
+/**
+ * cpu_configure_thermal_target() - Set the thermal target for a CPU
+ *
+ * This looks up the tcc-offset property and uses it to set the
+ * MSR_TEMPERATURE_TARGET value.
+ *
+ * @dev: CPU device
+ * @return 0 if OK, -ENOENT if no target is given in device tree
+ */
+int cpu_configure_thermal_target(struct udevice *dev);
+
+/**
+ * cpu_set_perf_control() - Set the nominal CPU clock speed
+ *
+ * This sets the clock speed as a multiplier of BCLK
+ *
+ * @clk_ratio: Ratio to use
+ */
+void cpu_set_perf_control(uint clk_ratio);
+
+/**
+ * cpu_config_tdp_levels() - Check for configurable TDP option
+ *
+ * @return true if the CPU has configurable TDP (Thermal-design power)
+ */
+bool cpu_config_tdp_levels(void);
+
+/** enum burst_mode_t - Burst-mode states */
+enum burst_mode_t {
+	BURST_MODE_UNKNOWN,
+	BURST_MODE_UNAVAILABLE,
+	BURST_MODE_DISABLED,
+	BURST_MODE_ENABLED
+};
+
+/*
+ * cpu_get_burst_mode_state() - Get the Burst/Turbo Mode State
+ *
+ * This reads MSR IA32_MISC_ENABLE 0x1A0
+ * Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED.
+ * Also checks cpuid 0x6 to see whether burst mode is supported.
+ *
+ * @return current burst mode status
+ */
+enum burst_mode_t cpu_get_burst_mode_state(void);
+
+/**
+ * cpu_set_burst_mode() - Set CPU burst mode
+ *
+ * @burst_mode: true to enable burst mode, false to disable
+ */
+void cpu_set_burst_mode(bool burst_mode);
+
+/**
+ * cpu_set_eist() - Enable Enhanced Intel Speed Step Technology
+ *
+ * @eist_status: true to enable EIST, false to disable
+ */
+void cpu_set_eist(bool eist_status);
+
+/**
+ * cpu_set_p_state_to_turbo_ratio() - Set turbo ratio
+ *
+ * TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the
+ * factory configured values for of 1-core, 2-core, 3-core
+ * and 4-core turbo ratio limits for all processors.
+ *
+ * 7:0 -	MAX_TURBO_1_CORE
+ * 15:8 -	MAX_TURBO_2_CORES
+ * 23:16 -	MAX_TURBO_3_CORES
+ * 31:24 -	MAX_TURBO_4_CORES
+ *
+ * Set PERF_CTL MSR (0x199) P_Req with that value.
+ */
+void cpu_set_p_state_to_turbo_ratio(void);
+
+#endif
diff --git a/arch/x86/include/asm/cpu_x86.h b/arch/x86/include/asm/cpu_x86.h
new file mode 100644
index 0000000..19223f2
--- /dev/null
+++ b/arch/x86/include/asm/cpu_x86.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _ASM_CPU_X86_H
+#define _ASM_CPU_X86_H
+
+/**
+ * cpu_x86_bind() - Bind an x86 CPU with the driver
+ *
+ * This updates cpu device's platform data with information from device tree,
+ * like the processor local apic id.
+ *
+ * @dev:	Device to check (UCLASS_CPU)
+ * @return	0 always
+ */
+int cpu_x86_bind(struct udevice *dev);
+
+/**
+ * cpu_x86_get_desc() - Get a description string for an x86 CPU
+ *
+ * This uses cpu_get_name() and is suitable to use as the get_desc() method for
+ * the CPU uclass.
+ *
+ * @dev:	Device to check (UCLASS_CPU)
+ * @buf:	Buffer to place string
+ * @size:	Size of string space
+ * @return:	0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+int cpu_x86_get_desc(struct udevice *dev, char *buf, int size);
+
+/**
+ * cpu_x86_get_vendor() - Get a vendor string for an x86 CPU
+ *
+ * This uses cpu_vendor_name() and is suitable to use as the get_vendor()
+ * method for the CPU uclass.
+ *
+ * @dev:	Device to check (UCLASS_CPU)
+ * @buf:	Buffer to place string
+ * @size:	Size of string space
+ * @return:	0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+int cpu_x86_get_vendor(struct udevice *dev, char *buf, int size);
+
+#endif /* _ASM_CPU_X86_H */
diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h
new file mode 100644
index 0000000..b353ff0
--- /dev/null
+++ b/arch/x86/include/asm/dma-mapping.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+#ifndef __ASM_X86_DMA_MAPPING_H
+#define __ASM_X86_DMA_MAPPING_H
+
+#include <linux/dma-direction.h>
+
+#define	dma_mapping_error(x, y)	0
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+	return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+	free(addr);
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+					   enum dma_data_direction dir)
+{
+	return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+				    unsigned long paddr)
+{
+}
+
+#endif /* __ASM_X86_DMA_MAPPING_H */
diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h
new file mode 100644
index 0000000..9d29f82
--- /dev/null
+++ b/arch/x86/include/asm/e820.h
@@ -0,0 +1,30 @@
+#ifndef _ASM_X86_E820_H
+#define _ASM_X86_E820_H
+
+#define E820MAX		128	/* number of entries in E820MAP */
+
+#define E820_RAM	1
+#define E820_RESERVED	2
+#define E820_ACPI	3
+#define E820_NVS	4
+#define E820_UNUSABLE	5
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
+struct e820_entry {
+	__u64 addr;	/* start of memory segment */
+	__u64 size;	/* size of memory segment */
+	__u32 type;	/* type of memory segment */
+} __attribute__((packed));
+
+#define ISA_START_ADDRESS	0xa0000
+#define ISA_END_ADDRESS		0x100000
+
+#endif /* __ASSEMBLY__ */
+
+/* Implementation defined function to install an e820 map */
+unsigned int install_e820_map(unsigned int max_entries,
+			      struct e820_entry *);
+
+#endif /* _ASM_X86_E820_H */
diff --git a/arch/x86/include/asm/early_cmos.h b/arch/x86/include/asm/early_cmos.h
new file mode 100644
index 0000000..543a9e6
--- /dev/null
+++ b/arch/x86/include/asm/early_cmos.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __EARLY_CMOS_H
+#define __EARLY_CMOS_H
+
+/* CMOS actually resides in the RTC SRAM */
+#define CMOS_IO_PORT	0x70
+
+/**
+ * cmos_read8() - Get 8-bit data stored at the given address
+ *
+ * This reads from CMOS for the 8-bit data stored at the given address.
+ *
+ * @addr:	RTC SRAM address
+ * @return:	8-bit data stored at the given address
+ */
+u8 cmos_read8(u8 addr);
+
+/**
+ * cmos_read16() - Get 16-bit data stored at the given address
+ *
+ * This reads from CMOS for the 16-bit data stored at the given address.
+ *
+ * @addr:	RTC SRAM address
+ * @return:	16-bit data stored at the given address
+ */
+u16 cmos_read16(u8 addr);
+
+/**
+ * cmos_read32() - Get 32-bit data stored at the given address
+ *
+ * This reads from CMOS for the 32-bit data stored at the given address.
+ *
+ * @addr:	RTC SRAM address
+ * @return:	32-bit data stored at the given address
+ */
+u32 cmos_read32(u8 addr);
+
+#endif /* __EARLY_CMOS_H */
diff --git a/arch/x86/include/asm/fsp/fsp_azalia.h b/arch/x86/include/asm/fsp/fsp_azalia.h
new file mode 100644
index 0000000..e59180b
--- /dev/null
+++ b/arch/x86/include/asm/fsp/fsp_azalia.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2015, Google, Inc
+ */
+
+#ifndef _FSP_AZALIA_H_
+#define _FSP_AZALIA_H_
+
+struct __packed azalia_verb_table_header {
+	u32 vendor_device_id;
+	u16 sub_system_id;
+	u8 revision_id;		/* 0xff applies to all steppings */
+	u8 front_panel_support;
+	u16 number_of_rear_jacks;
+	u16 number_of_front_jacks;
+};
+
+struct __packed azalia_verb_table {
+	struct azalia_verb_table_header header;
+	const u32 *data;
+};
+
+struct __packed azalia_config {
+	u8 pme_enable:1;
+	u8 docking_supported:1;
+	u8 docking_attached:1;
+	u8 hdmi_codec_enable:1;
+	u8 azalia_v_ci_enable:1;
+	u8 rsvdbits:3;
+	/* number of verb tables provided by platform */
+	u8 verb_table_num;
+	const struct azalia_verb_table *verb_table;
+	/* delay timer after azalia reset */
+	u16 reset_wait_timer_ms;
+};
+
+#endif
diff --git a/arch/x86/include/asm/fsp/fsp_bootmode.h b/arch/x86/include/asm/fsp/fsp_bootmode.h
new file mode 100644
index 0000000..bc96ec3
--- /dev/null
+++ b/arch/x86/include/asm/fsp/fsp_bootmode.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_BOOT_MODE_H__
+#define __FSP_BOOT_MODE_H__
+
+/* 0x21 - 0xf..f are reserved */
+#define BOOT_FULL_CONFIG		0x00
+#define BOOT_MINIMAL_CONFIG		0x01
+#define BOOT_NO_CONFIG_CHANGES		0x02
+#define BOOT_FULL_CONFIG_PLUS_DIAG	0x03
+#define BOOT_DEFAULT_SETTINGS		0x04
+#define BOOT_ON_S4_RESUME		0x05
+#define BOOT_ON_S5_RESUME		0x06
+#define BOOT_ON_S2_RESUME		0x10
+#define BOOT_ON_S3_RESUME		0x11
+#define BOOT_ON_FLASH_UPDATE		0x12
+#define BOOT_IN_RECOVERY_MODE		0x20
+
+#endif
diff --git a/arch/x86/include/asm/fsp/fsp_fv.h b/arch/x86/include/asm/fsp/fsp_fv.h
new file mode 100644
index 0000000..511dfb7
--- /dev/null
+++ b/arch/x86/include/asm/fsp/fsp_fv.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_FV___
+#define __FSP_FV___
+
+/* Value of EFI_FV_FILE_ATTRIBUTES */
+#define EFI_FV_FILE_ATTR_ALIGNMENT	0x0000001F
+#define EFI_FV_FILE_ATTR_FIXED		0x00000100
+#define EFI_FV_FILE_ATTR_MEMORY_MAPPED	0x00000200
+
+/* Attributes bit definitions */
+#define EFI_FVB2_READ_DISABLED_CAP	0x00000001
+#define EFI_FVB2_READ_ENABLED_CAP	0x00000002
+#define EFI_FVB2_READ_STATUS		0x00000004
+#define EFI_FVB2_WRITE_DISABLED_CAP	0x00000008
+#define EFI_FVB2_WRITE_ENABLED_CAP	0x00000010
+#define EFI_FVB2_WRITE_STATUS		0x00000020
+#define EFI_FVB2_LOCK_CAP		0x00000040
+#define EFI_FVB2_LOCK_STATUS		0x00000080
+#define EFI_FVB2_STICKY_WRITE		0x00000200
+#define EFI_FVB2_MEMORY_MAPPED		0x00000400
+#define EFI_FVB2_ERASE_POLARITY		0x00000800
+#define EFI_FVB2_READ_LOCK_CAP		0x00001000
+#define EFI_FVB2_READ_LOCK_STATUS	0x00002000
+#define EFI_FVB2_WRITE_LOCK_CAP		0x00004000
+#define EFI_FVB2_WRITE_LOCK_STATUS	0x00008000
+#define EFI_FVB2_ALIGNMENT		0x001F0000
+#define EFI_FVB2_ALIGNMENT_1		0x00000000
+#define EFI_FVB2_ALIGNMENT_2		0x00010000
+#define EFI_FVB2_ALIGNMENT_4		0x00020000
+#define EFI_FVB2_ALIGNMENT_8		0x00030000
+#define EFI_FVB2_ALIGNMENT_16		0x00040000
+#define EFI_FVB2_ALIGNMENT_32		0x00050000
+#define EFI_FVB2_ALIGNMENT_64		0x00060000
+#define EFI_FVB2_ALIGNMENT_128		0x00070000
+#define EFI_FVB2_ALIGNMENT_256		0x00080000
+#define EFI_FVB2_ALIGNMENT_512		0x00090000
+#define EFI_FVB2_ALIGNMENT_1K		0x000A0000
+#define EFI_FVB2_ALIGNMENT_2K		0x000B0000
+#define EFI_FVB2_ALIGNMENT_4K		0x000C0000
+#define EFI_FVB2_ALIGNMENT_8K		0x000D0000
+#define EFI_FVB2_ALIGNMENT_16K		0x000E0000
+#define EFI_FVB2_ALIGNMENT_32K		0x000F0000
+#define EFI_FVB2_ALIGNMENT_64K		0x00100000
+#define EFI_FVB2_ALIGNMENT_128K		0x00110000
+#define EFI_FVB2_ALIGNMENT_256K		0x00120000
+#define EFI_FVB2_ALIGNMENT_512K		0x00130000
+#define EFI_FVB2_ALIGNMENT_1M		0x00140000
+#define EFI_FVB2_ALIGNMENT_2M		0x00150000
+#define EFI_FVB2_ALIGNMENT_4M		0x00160000
+#define EFI_FVB2_ALIGNMENT_8M		0x00170000
+#define EFI_FVB2_ALIGNMENT_16M		0x00180000
+#define EFI_FVB2_ALIGNMENT_32M		0x00190000
+#define EFI_FVB2_ALIGNMENT_64M		0x001A0000
+#define EFI_FVB2_ALIGNMENT_128M		0x001B0000
+#define EFI_FVB2_ALIGNMENT_256M		0x001C0000
+#define EFI_FVB2_ALIGNMENT_512M		0x001D0000
+#define EFI_FVB2_ALIGNMENT_1G		0x001E0000
+#define EFI_FVB2_ALIGNMENT_2G		0x001F0000
+
+struct fv_blkmap_entry {
+	/* The number of sequential blocks which are of the same size */
+	u32	num_blocks;
+	/* The size of the blocks */
+	u32	length;
+};
+
+/* Describes the features and layout of the firmware volume */
+struct fv_header {
+	/*
+	 * The first 16 bytes are reserved to allow for the reset vector of
+	 * processors whose reset vector is at address 0.
+	 */
+	u8			zero_vec[16];
+	/*
+	 * Declares the file system with which the firmware volume
+	 * is formatted.
+	 */
+	efi_guid_t		fs_guid;
+	/*
+	 * Length in bytes of the complete firmware volume, including
+	 * the header.
+	 */
+	u64			fv_len;
+	/* Set to EFI_FVH_SIGNATURE */
+	u32			sign;
+	/*
+	 * Declares capabilities and power-on defaults for the firmware
+	 * volume.
+	 */
+	u32			attr;
+	/* Length in bytes of the complete firmware volume header */
+	u16			hdr_len;
+	/*
+	 * A 16-bit checksum of the firmware volume header.
+	 * A valid header sums to zero.
+	 */
+	u16			checksum;
+	/*
+	 * Offset, relative to the start of the header, of the extended
+	 * header (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is
+	 * no extended header.
+	 */
+	u16			ext_hdr_off;
+	/* This field must always be set to zero */
+	u8			reserved[1];
+	/*
+	 * Set to 2. Future versions of this specification may define new
+	 * header fields and will increment the Revision field accordingly.
+	 */
+	u8			rev;
+	/*
+	 * An array of run-length encoded FvBlockMapEntry structures.
+	 * The array is terminated with an entry of {0,0}.
+	 */
+	struct fv_blkmap_entry	block_map[1];
+};
+
+#define EFI_FVH_SIGNATURE	SIGNATURE_32('_', 'F', 'V', 'H')
+
+/* Firmware Volume Header Revision definition */
+#define EFI_FVH_REVISION	0x02
+
+/* Extension header pointed by ExtHeaderOffset of volume header */
+struct fv_ext_header {
+	/* firmware volume name */
+	efi_guid_t		fv_name;
+	/* Size of the rest of the extension header including this structure */
+	u32			ext_hdr_size;
+};
+
+#endif
diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h
new file mode 100644
index 0000000..d248520
--- /dev/null
+++ b/arch/x86/include/asm/fsp/fsp_hob.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_HOB_H__
+#define __FSP_HOB_H__
+
+#include <asm/hob.h>
+
+enum pixel_format {
+	pixel_rgbx_8bpc,	/* RGB 8 bit per color */
+	pixel_bgrx_8bpc,	/* BGR 8 bit per color */
+	pixel_bitmask,
+};
+
+struct __packed hob_graphics_info {
+	phys_addr_t fb_base;	/* framebuffer base address */
+	u32 fb_size;		/* framebuffer size */
+	u32 version;
+	u32 width;
+	u32 height;
+	enum pixel_format pixel_format;
+	u32 red_mask;
+	u32 green_mask;
+	u32 blue_mask;
+	u32 reserved_mask;
+	u32 pixels_per_scanline;
+};
+
+/* FSP specific GUID HOB definitions */
+#define FSP_GUID_DATA1		0x912740be
+#define FSP_GUID_DATA2		0x2284
+#define FSP_GUID_DATA3		0x4734
+#define FSP_GUID_DATA4_0	0xb9
+#define FSP_GUID_DATA4_1	0x71
+#define FSP_GUID_DATA4_2	0x84
+#define FSP_GUID_DATA4_3	0xb0
+#define FSP_GUID_DATA4_4	0x27
+#define FSP_GUID_DATA4_5	0x35
+#define FSP_GUID_DATA4_6	0x3f
+#define FSP_GUID_DATA4_7	0x0c
+
+#define FSP_GUID_BYTE0		0xbe
+#define FSP_GUID_BYTE1		0x40
+#define FSP_GUID_BYTE2		0x27
+#define FSP_GUID_BYTE3		0x91
+#define FSP_GUID_BYTE4		0x84
+#define FSP_GUID_BYTE5		0x22
+#define FSP_GUID_BYTE6		0x34
+#define FSP_GUID_BYTE7		0x47
+#define FSP_GUID_BYTE8		FSP_GUID_DATA4_0
+#define FSP_GUID_BYTE9		FSP_GUID_DATA4_1
+#define FSP_GUID_BYTE10		FSP_GUID_DATA4_2
+#define FSP_GUID_BYTE11		FSP_GUID_DATA4_3
+#define FSP_GUID_BYTE12		FSP_GUID_DATA4_4
+#define FSP_GUID_BYTE13		FSP_GUID_DATA4_5
+#define FSP_GUID_BYTE14		FSP_GUID_DATA4_6
+#define FSP_GUID_BYTE15		FSP_GUID_DATA4_7
+
+#define FSP_HEADER_GUID \
+	EFI_GUID(FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \
+		FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \
+		FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \
+		FSP_GUID_DATA4_6, FSP_GUID_DATA4_7)
+
+#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
+	EFI_GUID(0x721acf02, 0x4d77, 0x4c2a, \
+		0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0)
+
+#define FSP_VARIABLE_NV_DATA_HOB_GUID \
+	EFI_GUID(0xa034147d, 0x690c, 0x4154, \
+		0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42)
+
+#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \
+	EFI_GUID(0xbbcff46c, 0xc8d3, 0x4113, \
+		0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e)
+
+#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \
+	EFI_GUID(0x69a79759, 0x1373, 0x4367, \
+		0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e)
+
+#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
+	EFI_GUID(0xd038747c, 0xd00c, 0x4980, \
+		0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55)
+
+#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \
+	EFI_GUID(0x9c7c3aa7, 0x5332, 0x4917, \
+		0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07)
+
+/* The following GUIDs are newly introduced in FSP spec 1.1 */
+
+#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \
+	EFI_GUID(0x73ff4f56, 0xaa8e, 0x4451, \
+		0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44)
+
+#define FSP_GRAPHICS_INFO_HOB_GUID \
+	EFI_GUID(0x39f62cce, 0x6825, 0x4669, \
+		0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07)
+
+#endif
diff --git a/arch/x86/include/asm/fsp/fsp_infoheader.h b/arch/x86/include/asm/fsp/fsp_infoheader.h
new file mode 100644
index 0000000..e72c052
--- /dev/null
+++ b/arch/x86/include/asm/fsp/fsp_infoheader.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _FSP_HEADER_H_
+#define _FSP_HEADER_H_
+
+#define FSP_HEADER_OFF	0x94	/* Fixed FSP header offset in the FSP image */
+
+struct __packed fsp_header {
+	u32	sign;			/* 'FSPH' */
+	u32	hdr_len;		/* header length */
+	u8	reserved1[3];
+	u8	hdr_rev;		/* header rev */
+	u32	img_rev;		/* image rev */
+	char	img_id[8];		/* signature string */
+	u32	img_size;		/* image size */
+	u32	img_base;		/* image base */
+	u32	img_attr;		/* image attribute */
+	u32	cfg_region_off;		/* configuration region offset */
+	u32	cfg_region_size;	/* configuration region size */
+	u32	api_num;		/* number of API entries */
+	u32	fsp_tempram_init;	/* tempram_init offset */
+	u32	fsp_init;		/* fsp_init offset */
+	u32	fsp_notify;		/* fsp_notify offset */
+	u32	fsp_mem_init;		/* fsp_mem_init offset */
+	u32	fsp_tempram_exit;	/* fsp_tempram_exit offset */
+	u32	fsp_silicon_init;	/* fsp_silicon_init offset */
+};
+
+#define FSP_HEADER_REVISION_1		1
+#define FSP_HEADER_REVISION_2		2
+
+enum fsp_type {
+	FSP_ATTR_COMP_TYPE_FSP_T	= 1,
+	FSP_ATTR_COMP_TYPE_FSP_M	= 2,
+	FSP_ATTR_COMP_TYPE_FSP_S	= 3,
+};
+
+enum {
+	FSP_ATTR_GRAPHICS_SUPPORT	= 1 << 0,
+	FSP_ATTR_COMP_TYPE_SHIFT	= 28,
+	FSP_ATTR_COMP_TYPE_MASK		= 0xfU << FSP_ATTR_COMP_TYPE_SHIFT,
+
+};
+
+#define EFI_FSPH_SIGNATURE		SIGNATURE_32('F', 'S', 'P', 'H')
+
+#endif
diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h
new file mode 100644
index 0000000..4ac27d2
--- /dev/null
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_SUPPORT_H__
+#define __FSP_SUPPORT_H__
+
+#include <asm/fsp/fsp_bootmode.h>
+#include <asm/fsp/fsp_fv.h>
+#include <asm/fsp/fsp_hob.h>
+#include <asm/fsp/fsp_infoheader.h>
+#include <asm/fsp/fsp_types.h>
+#include <asm/fsp_arch.h>
+#include <asm/fsp/fsp_azalia.h>
+
+#define FSP_LOWMEM_BASE		0x100000UL
+#define FSP_HIGHMEM_BASE	0x100000000ULL
+#define UPD_TERMINATOR		0x55AA
+
+/**
+ * fsp_find_header() - Find FSP header offset in FSP image
+ *
+ * @return the offset of FSP header. If signature is invalid, returns 0.
+ */
+struct fsp_header *fsp_find_header(void);
+
+/**
+ * fsp_notify() - FSP notification wrapper function
+ *
+ * @fsp_hdr: Pointer to FSP information header
+ * @phase:   FSP initialization phase defined in enum fsp_phase
+ *
+ * @return compatible status code with EFI_STATUS defined in PI spec
+ */
+u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
+
+/**
+ * fsp_get_usable_lowmem_top() - retrieves the top of usable low memory
+ *
+ * @hob_list: A HOB list pointer.
+ *
+ * @return Usable low memory top.
+ */
+u32 fsp_get_usable_lowmem_top(const void *hob_list);
+
+/**
+ * fsp_get_usable_highmem_top() - retrieves the top of usable high memory
+ *
+ * @hob_list: A HOB list pointer.
+ *
+ * @return Usable high memory top.
+ */
+u64 fsp_get_usable_highmem_top(const void *hob_list);
+
+/**
+ * fsp_get_reserved_mem_from_guid() - retrieves a special reserved memory region
+ *
+ * @hob_list: A HOB list pointer.
+ * @len:      A pointer to the GUID HOB data buffer length.
+ *            If the GUID HOB is located, the length will be updated.
+ * @guid:     A pointer to the owner guild.
+ *
+ * @return Reserved region start address.
+ *            0 if this region does not exist.
+ */
+u64 fsp_get_reserved_mem_from_guid(const void *hob_list,
+				   u64 *len, const efi_guid_t *guid);
+
+/**
+ * fsp_get_fsp_reserved_mem() - retrieves the FSP reserved normal memory
+ *
+ * @hob_list: A HOB list pointer.
+ * @len:      A pointer to the FSP reserved memory length buffer.
+ *            If the GUID HOB is located, the length will be updated.
+ * @return FSP reserved memory base
+ *            0 if this region does not exist.
+ */
+u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len);
+
+/**
+ * fsp_get_tseg_reserved_mem() - retrieves the TSEG reserved normal memory
+ *
+ * @hob_list:      A HOB list pointer.
+ * @len:           A pointer to the TSEG reserved memory length buffer.
+ *                 If the GUID HOB is located, the length will be updated.
+ *
+ * @return NULL:   Failed to find the TSEG reserved memory.
+ * @return others: TSEG reserved memory base.
+ */
+u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len);
+
+/**
+ * fsp_get_nvs_data() - retrieves FSP Non-volatile Storage HOB buffer and size
+ *
+ * @hob_list:      A HOB list pointer.
+ * @len:           A pointer to the NVS data buffer length.
+ *                 If the HOB is located, the length will be updated.
+ *
+ * @return NULL:   Failed to find the NVS HOB.
+ * @return others: FSP NVS data buffer pointer.
+ */
+void *fsp_get_nvs_data(const void *hob_list, u32 *len);
+
+/**
+ * fsp_get_var_nvs_data() - get FSP variable Non-volatile Storage HOB buffer
+ *
+ * @hob_list:      A HOB list pointer.
+ * @len:           A pointer to the NVS data buffer length.
+ *                 If the HOB is located, the length will be updated.
+ *
+ * @return NULL:   Failed to find the NVS HOB.
+ * @return others: FSP NVS data buffer pointer.
+ */
+void *fsp_get_var_nvs_data(const void *hob_list, u32 *len);
+
+/**
+ * fsp_get_graphics_info() - retrieves graphics information.
+ *
+ * @hob_list:      A HOB list pointer.
+ * @len:           A pointer to the graphics info HOB length.
+ *                 If the HOB is located, the length will be updated.
+ *
+ * @return NULL:   Failed to find the graphics info HOB.
+ * @return others: A pointer to struct hob_graphics_info.
+ */
+void *fsp_get_graphics_info(const void *hob_list, u32 *len);
+
+/**
+ * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init
+ *
+ * @return 0 if OK, -EPERM if the FSP gave an error.
+ */
+int fsp_init_phase_pci(void);
+
+/**
+ * fsp_scan_for_ram_size() - Scan the HOB list to find the RAM size
+ *
+ * This sets gd->ram_size based on what it finds.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int fsp_scan_for_ram_size(void);
+
+/**
+ * fsp_prepare_mrc_cache() - Find the DRAM training data from the MRC cache
+ *
+ * @return pointer to data, or NULL if no cache or no data found in the cache
+ */
+void *fsp_prepare_mrc_cache(void);
+
+/**
+ * fsp_notify() - FSP notification wrapper function
+ *
+ * @fsp_hdr: Pointer to FSP information header
+ * @phase:   FSP initialization phase defined in enum fsp_phase
+ *
+ * @return compatible status code with EFI_STATUS defined in PI spec
+ */
+u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
+
+#endif
diff --git a/arch/x86/include/asm/fsp/fsp_types.h b/arch/x86/include/asm/fsp/fsp_types.h
new file mode 100644
index 0000000..3d5b17e
--- /dev/null
+++ b/arch/x86/include/asm/fsp/fsp_types.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_TYPES_H__
+#define __FSP_TYPES_H__
+
+/**
+ * Returns a 16-bit signature built from 2 ASCII characters.
+ *
+ * This macro returns a 16-bit value built from the two ASCII characters
+ * specified by A and B.
+ *
+ * @A: The first ASCII character.
+ * @B: The second ASCII character.
+ *
+ * @return: A 16-bit value built from the two ASCII characters specified by
+ *          A and B.
+ */
+#define SIGNATURE_16(A, B)	((A) | (B << 8))
+
+/**
+ * Returns a 32-bit signature built from 4 ASCII characters.
+ *
+ * This macro returns a 32-bit value built from the four ASCII characters
+ * specified by A, B, C, and D.
+ *
+ * @A: The first ASCII character.
+ * @B: The second ASCII character.
+ * @C: The third ASCII character.
+ * @D: The fourth ASCII character.
+ *
+ * @return: A 32-bit value built from the two ASCII characters specified by
+ *          A, B, C and D.
+ */
+#define SIGNATURE_32(A, B, C, D)	\
+	(SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
+
+/**
+ * Returns a 64-bit signature built from 8 ASCII characters.
+ *
+ * This macro returns a 64-bit value built from the eight ASCII characters
+ * specified by A, B, C, D, E, F, G,and H.
+ *
+ * @A: The first ASCII character.
+ * @B: The second ASCII character.
+ * @C: The third ASCII character.
+ * @D: The fourth ASCII character.
+ * @E: The fifth ASCII character.
+ * @F: The sixth ASCII character.
+ * @G: The seventh ASCII character.
+ * @H: The eighth ASCII character.
+ *
+ * @return: A 64-bit value built from the two ASCII characters specified by
+ *          A, B, C, D, E, F, G and H.
+ */
+#define SIGNATURE_64(A, B, C, D, E, F, G, H)	\
+	(SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
+
+#endif
diff --git a/arch/x86/include/asm/fsp1/fsp_api.h b/arch/x86/include/asm/fsp1/fsp_api.h
new file mode 100644
index 0000000..f2d7079
--- /dev/null
+++ b/arch/x86/include/asm/fsp1/fsp_api.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_API_H__
+#define __FSP_API_H__
+
+#include <linux/linkage.h>
+
+/*
+ * FSP common configuration structure.
+ * This needs to be included in the platform-specific struct fsp_config_data.
+ */
+struct fsp_cfg_common {
+	struct fsp_header	*fsp_hdr;
+	u32			stack_top;
+	u32			boot_mode;
+};
+
+/*
+ * FspInit continuation function prototype.
+ * Control will be returned to this callback function after FspInit API call.
+ */
+typedef void (*fsp_continuation_f)(u32 status, void *hob_list);
+
+struct fsp_init_params {
+	/* Non-volatile storage buffer pointer */
+	void			*nvs_buf;
+	/* Runtime buffer pointer */
+	void			*rt_buf;
+	/* Continuation function address */
+	fsp_continuation_f	continuation;
+};
+
+struct common_buf {
+	/*
+	 * Stack top pointer used by the bootloader. The new stack frame will be
+	 * set up at this location after FspInit API call.
+	 */
+	u32	stack_top;
+	u32	boot_mode;	/* Current system boot mode */
+	void	*upd_data;	/* User platform configuraiton data region */
+	u32	tolum_size;	/* Top of low usable memory size (FSP 1.1) */
+	u32	reserved[6];	/* Reserved */
+};
+
+enum fsp_phase {
+	/* Notification code for post PCI enuermation */
+	INIT_PHASE_PCI	= 0x20,
+	/* Notification code before transfering control to the payload */
+	INIT_PHASE_BOOT	= 0x40
+};
+
+struct fsp_notify_params {
+	/* Notification phase used for NotifyPhase API */
+	enum fsp_phase	phase;
+};
+
+/* FspInit API function prototype */
+typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params);
+
+/* FspNotify API function prototype */
+typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params);
+
+#endif
diff --git a/arch/x86/include/asm/fsp1/fsp_ffs.h b/arch/x86/include/asm/fsp1/fsp_ffs.h
new file mode 100644
index 0000000..b7558e5
--- /dev/null
+++ b/arch/x86/include/asm/fsp1/fsp_ffs.h
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP_FFS_H__
+#define __FSP_FFS_H__
+
+/* Used to verify the integrity of the file */
+union __packed ffs_integrity {
+	struct {
+		/*
+		 * The IntegrityCheck.checksum.header field is an 8-bit
+		 * checksum of the file header. The State and
+		 * IntegrityCheck.checksum.file fields are assumed to be zero
+		 * and the checksum is calculated such that the entire header
+		 * sums to zero.
+		 */
+		u8	header;
+		/*
+		 * If the FFS_ATTRIB_CHECKSUM (see definition below) bit of
+		 * the Attributes field is set to one, the
+		 * IntegrityCheck.checksum.file field is an 8-bit checksum of
+		 * the file data. If the FFS_ATTRIB_CHECKSUM bit of the
+		 * Attributes field is cleared to zero, the
+		 * IntegrityCheck.checksum.file field must be initialized with
+		 * a value of 0xAA. The IntegrityCheck.checksum.file field is
+		 * valid any time the EFI_FILE_DATA_VALID bit is set in the
+		 * State field.
+		 */
+		u8	file;
+	} checksum;
+
+	/* This is the full 16 bits of the IntegrityCheck field */
+	u16	checksum16;
+};
+
+/*
+ * Each file begins with the header that describe the
+ * contents and state of the files.
+ */
+struct __packed ffs_file_header {
+	/*
+	 * This GUID is the file name.
+	 * It is used to uniquely identify the file.
+	 */
+	efi_guid_t		name;
+	/* Used to verify the integrity of the file */
+	union ffs_integrity	integrity;
+	/* Identifies the type of file */
+	u8			type;
+	/* Declares various file attribute bits */
+	u8			attr;
+	/* The length of the file in bytes, including the FFS header */
+	u8			size[3];
+	/*
+	 * Used to track the state of the file throughout the life of
+	 * the file from creation to deletion.
+	 */
+	u8			state;
+};
+
+struct __packed ffs_file_header2 {
+	/*
+	 * This GUID is the file name. It is used to uniquely identify the file.
+	 * There may be only one instance of a file with the file name GUID of
+	 * Name in any given firmware volume, except if the file type is
+	 * EFI_FV_FILE_TYPE_FFS_PAD.
+	 */
+	efi_guid_t		name;
+	/* Used to verify the integrity of the file */
+	union ffs_integrity	integrity;
+	/* Identifies the type of file */
+	u8			type;
+	/* Declares various file attribute bits */
+	u8			attr;
+	/*
+	 * The length of the file in bytes, including the FFS header.
+	 * The length of the file data is either
+	 * (size - sizeof(struct ffs_file_header)). This calculation means a
+	 * zero-length file has a size of 24 bytes, which is
+	 * sizeof(struct ffs_file_header). Size is not required to be a
+	 * multiple of 8 bytes. Given a file F, the next file header is located
+	 * at the next 8-byte aligned firmware volume offset following the last
+	 * byte of the file F.
+	 */
+	u8			size[3];
+	/*
+	 * Used to track the state of the file throughout the life of
+	 * the file from creation to deletion.
+	 */
+	u8			state;
+	/*
+	 * If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists
+	 * and size must be set to zero.
+	 * If FFS_ATTRIB_LARGE_FILE is not set then
+	 * struct ffs_file_header is used.
+	 */
+	u32			ext_size;
+};
+
+/*
+ * Pseudo type. It is used as a wild card when retrieving sections.
+ * The section type EFI_SECTION_ALL matches all section types.
+ */
+#define EFI_SECTION_ALL				0x00
+
+/* Encapsulation section Type values */
+#define EFI_SECTION_COMPRESSION			0x01
+#define EFI_SECTION_GUID_DEFINED		0x02
+#define EFI_SECTION_DISPOSABLE			0x03
+
+/* Leaf section Type values */
+#define EFI_SECTION_PE32			0x10
+#define EFI_SECTION_PIC				0x11
+#define EFI_SECTION_TE				0x12
+#define EFI_SECTION_DXE_DEPEX			0x13
+#define EFI_SECTION_VERSION			0x14
+#define EFI_SECTION_USER_INTERFACE		0x15
+#define EFI_SECTION_COMPATIBILITY16		0x16
+#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE	0x17
+#define EFI_SECTION_FREEFORM_SUBTYPE_GUID	0x18
+#define EFI_SECTION_RAW				0x19
+#define EFI_SECTION_PEI_DEPEX			0x1B
+#define EFI_SECTION_SMM_DEPEX			0x1C
+
+/* Common section header */
+struct __packed raw_section {
+	/*
+	 * A 24-bit unsigned integer that contains the total size of
+	 * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
+	 */
+	u8	size[3];
+	u8	type;
+};
+
+struct __packed raw_section2 {
+	/*
+	 * A 24-bit unsigned integer that contains the total size of
+	 * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
+	 */
+	u8	size[3];
+	u8	type;
+	/*
+	 * If size is 0xFFFFFF, then ext_size contains the size of
+	 * the section. If size is not equal to 0xFFFFFF, then this
+	 * field does not exist.
+	 */
+	u32	ext_size;
+};
+
+#endif
diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h
new file mode 100644
index 0000000..a44a550
--- /dev/null
+++ b/arch/x86/include/asm/fsp1/fsp_support.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __FSP1_SUPPORT_H__
+#define __FSP1_SUPPORT_H__
+
+#include <asm/fsp/fsp_support.h>
+#include "fsp_ffs.h"
+
+/**
+ * fsp_asm_continuation() - FSP Continuation assembly helper routine
+ *
+ * This routine jumps to the C version of FSP continuation function
+ */
+void fsp_asm_continuation(void);
+
+/**
+ * fsp_init_done() - FSP initialization complete
+ *
+ * This is the function that indicates FSP initialization is complete and jumps
+ * back to the bootloader with HOB list pointer as the parameter.
+ *
+ * @hob_list:    HOB list pointer
+ */
+void fsp_init_done(void *hob_list);
+
+/**
+ * fsp_continue() - FSP Continuation function
+ *
+ * @status:      Always 0
+ * @hob_list:    HOB list pointer
+ *
+ * @return Never returns
+ */
+void fsp_continue(u32 status, void *hob_list);
+
+/**
+ * fsp_init() - FSP initialization wrapper function
+ *
+ * @stack_top: bootloader stack top address
+ * @boot_mode: boot mode defined in fsp_bootmode.h
+ * @nvs_buf:   Non-volatile memory buffer pointer
+ */
+void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf);
+
+/**
+ * fsp_get_bootloader_tmp_mem() - retrieves temporary stack buffer and size
+ *
+ * @hob_list:      A HOB list pointer.
+ * @len:           A pointer to the bootloader temporary stack length.
+ *                 If the HOB is located, the length will be updated.
+ *
+ * @return NULL:   Failed to find the bootloader temporary stack HOB.
+ * @return others: Bootloader temporary stackbuffer pointer.
+ */
+void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
+
+/**
+ * fsp_update_configs() - overrides the default configurations of FSP
+ *
+ * @config:  A pointer to the FSP configuration data structure
+ * @rt_buf:  A pointer to the FSP runtime buffer data structure
+ *
+ * @return None
+ */
+void fsp_update_configs(struct fsp_config_data *config,
+			struct fspinit_rtbuf *rt_buf);
+
+#endif
diff --git a/arch/x86/include/asm/fsp_arch.h b/arch/x86/include/asm/fsp_arch.h
new file mode 100644
index 0000000..3b2077b
--- /dev/null
+++ b/arch/x86/include/asm/fsp_arch.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * Architecture-specific definitions (FSP config and VPD/UPD)
+ */
+
+#ifndef __FSP_ARCH_H__
+#define __FSP_ARCH_H__
+
+/*
+ * Note: use #ifndef __ASSEMBLY__ around any struct definitions or other C code
+ * since this file can be included from assembly.
+ */
+
+#include <asm/fsp1/fsp_api.h>
+#include <asm/fsp1/fsp_ffs.h>
+#include <asm/arch/fsp/fsp_vpd.h>
+#include <asm/arch/fsp/fsp_configs.h>
+
+#endif
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
new file mode 100644
index 0000000..17a4d34
--- /dev/null
+++ b/arch/x86/include/asm/global_data.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef	__ASM_GBL_DATA_H
+#define __ASM_GBL_DATA_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/processor.h>
+
+enum pei_boot_mode_t {
+	PEI_BOOT_NONE = 0,
+	PEI_BOOT_SOFT_RESET,
+	PEI_BOOT_RESUME,
+
+};
+
+struct dimm_info {
+	uint32_t dimm_size;
+	uint16_t ddr_type;
+	uint16_t ddr_frequency;
+	uint8_t rank_per_dimm;
+	uint8_t channel_num;
+	uint8_t dimm_num;
+	uint8_t bank_locator;
+	/* The 5th byte is '\0' for the end of string */
+	uint8_t serial[5];
+	/* The 19th byte is '\0' for the end of string */
+	uint8_t module_part_number[19];
+	uint16_t mod_id;
+	uint8_t mod_type;
+	uint8_t bus_width;
+} __packed;
+
+struct pei_memory_info {
+	uint8_t dimm_cnt;
+	/* Maximum num of dimm is 8 */
+	struct dimm_info dimm[8];
+} __packed;
+
+struct memory_area {
+	uint64_t start;
+	uint64_t size;
+};
+
+struct memory_info {
+	int num_areas;
+	uint64_t total_memory;
+	uint64_t total_32bit_memory;
+	struct memory_area area[CONFIG_NR_DRAM_BANKS];
+};
+
+#define MAX_MTRR_REQUESTS	8
+
+/**
+ * A request for a memory region to be set up in a particular way. These
+ * requests are processed before board_init_r() is called. They are generally
+ * optional and can be ignored with some performance impact.
+ */
+struct mtrr_request {
+	int type;		/* MTRR_TYPE_... */
+	uint64_t start;
+	uint64_t size;
+};
+
+/* Architecture-specific global data */
+struct arch_global_data {
+	u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16);
+	struct global_data *gd_addr;	/* Location of Global Data */
+	uint8_t x86;			/* CPU family */
+	uint8_t x86_vendor;		/* CPU vendor */
+	uint8_t x86_model;
+	uint8_t x86_mask;
+	uint32_t x86_device;
+	uint64_t tsc_base;		/* Initial value returned by rdtsc() */
+	unsigned long clock_rate;	/* Clock rate of timer in Hz */
+	void *new_fdt;			/* Relocated FDT */
+	uint32_t bist;			/* Built-in self test value */
+	enum pei_boot_mode_t pei_boot_mode;
+	const struct pch_gpio_map *gpio_map;	/* board GPIO map */
+	struct memory_info meminfo;	/* Memory information */
+	struct pei_memory_info pei_meminfo;	/* PEI memory information */
+#ifdef CONFIG_USE_HOB
+	void *hob_list;			/* FSP HOB list */
+#endif
+	struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
+	int mtrr_req_count;
+	int has_mtrr;
+	/* MRC training data to save for the next boot */
+	char *mrc_output;
+	unsigned int mrc_output_len;
+	ulong table;			/* Table pointer from previous loader */
+	int turbo_state;		/* Current turbo state */
+	struct irq_routing_table *pirq_routing_table;
+#ifdef CONFIG_SEABIOS
+	u32 high_table_ptr;
+	u32 high_table_limit;
+#endif
+#ifdef CONFIG_HAVE_ACPI_RESUME
+	int prev_sleep_state;		/* Previous sleep state ACPI_S0/1../5 */
+	ulong backup_mem;		/* Backup memory address for S3 */
+#endif
+};
+
+#endif
+
+#include <asm-generic/global_data.h>
+
+#ifndef __ASSEMBLY__
+# if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64)
+
+/* TODO(sjg@chromium.org): Consider using a fixed register for gd on x86_64 */
+#define gd global_data_ptr
+
+#define DECLARE_GLOBAL_DATA_PTR   extern struct global_data *global_data_ptr
+# else
+static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void)
+{
+	gd_t *gd_ptr;
+
+#if CONFIG_IS_ENABLED(X86_64)
+	asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr));
+#else
+	asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
+#endif
+
+	return gd_ptr;
+}
+
+#define gd	get_fs_gd_ptr()
+
+#define DECLARE_GLOBAL_DATA_PTR
+# endif
+
+#endif
+
+#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
new file mode 100644
index 0000000..58e4d7b
--- /dev/null
+++ b/arch/x86/include/asm/gpio.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2012, Google Inc. All rights reserved.
+ */
+
+#ifndef _X86_GPIO_H_
+#define _X86_GPIO_H_
+
+#include <asm-generic/gpio.h>
+
+struct ich6_bank_platdata {
+	uint16_t base_addr;
+	const char *bank_name;
+	int offset;
+};
+
+#endif /* _X86_GPIO_H_ */
diff --git a/arch/x86/include/asm/handoff.h b/arch/x86/include/asm/handoff.h
new file mode 100644
index 0000000..aec49b9
--- /dev/null
+++ b/arch/x86/include/asm/handoff.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Architecture-specific SPL handoff information for x86
+ *
+ * Copyright 2018 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __x86_asm_handoff_h
+#define __x86_asm_handoff_h
+
+/**
+ * struct arch_spl_handoff - architecture-specific handoff info
+ *
+ * @usable_ram_top: Value returned by board_get_usable_ram_top() in SPL
+ * @hob_list: Start of FSP hand-off blocks (HOBs)
+ */
+struct arch_spl_handoff {
+	ulong usable_ram_top;
+	void *hob_list;
+};
+
+#endif
diff --git a/arch/x86/include/asm/hob.h b/arch/x86/include/asm/hob.h
new file mode 100644
index 0000000..56e11db
--- /dev/null
+++ b/arch/x86/include/asm/hob.h
@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Copyright (C) 2013, Intel Corporation
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __HOB_H__
+#define __HOB_H__
+
+#include <efi.h>
+#include <efi_loader.h>
+
+/* Type of HOB Header */
+#define HOB_TYPE_MEM_ALLOC	0x0002
+#define HOB_TYPE_RES_DESC	0x0003
+#define HOB_TYPE_GUID_EXT	0x0004
+#define HOB_TYPE_UNUSED		0xFFFE
+#define HOB_TYPE_EOH		0xFFFF
+
+/* Value of ResourceType in HOB_RES_DESC */
+#define RES_SYS_MEM		0x00000000
+#define RES_MMAP_IO		0x00000001
+#define RES_IO			0x00000002
+#define RES_FW_DEVICE		0x00000003
+#define RES_MMAP_IO_PORT	0x00000004
+#define RES_MEM_RESERVED	0x00000005
+#define RES_IO_RESERVED		0x00000006
+#define RES_MAX_MEM_TYPE	0x00000007
+
+/*
+ * These types can be ORed together as needed.
+ *
+ * The first three enumerations describe settings
+ * The rest of the settings describe capabilities
+ */
+#define RES_ATTR_PRESENT			0x00000001
+#define RES_ATTR_INITIALIZED			0x00000002
+#define RES_ATTR_TESTED				0x00000004
+#define RES_ATTR_SINGLE_BIT_ECC			0x00000008
+#define RES_ATTR_MULTIPLE_BIT_ECC		0x00000010
+#define RES_ATTR_ECC_RESERVED_1			0x00000020
+#define RES_ATTR_ECC_RESERVED_2			0x00000040
+#define RES_ATTR_READ_PROTECTED			0x00000080
+#define RES_ATTR_WRITE_PROTECTED		0x00000100
+#define RES_ATTR_EXECUTION_PROTECTED		0x00000200
+#define RES_ATTR_UNCACHEABLE			0x00000400
+#define RES_ATTR_WRITE_COMBINEABLE		0x00000800
+#define RES_ATTR_WRITE_THROUGH_CACHEABLE	0x00001000
+#define RES_ATTR_WRITE_BACK_CACHEABLE		0x00002000
+#define RES_ATTR_16_BIT_IO			0x00004000
+#define RES_ATTR_32_BIT_IO			0x00008000
+#define RES_ATTR_64_BIT_IO			0x00010000
+#define RES_ATTR_UNCACHED_EXPORTED		0x00020000
+
+/*
+ * Describes the format and size of the data inside the HOB.
+ * All HOBs must contain this generic HOB header.
+ */
+struct hob_header {
+	u16	type;		/* HOB type */
+	u16	len;		/* HOB length */
+	u32	reserved;	/* always zero */
+};
+
+/*
+ * Describes all memory ranges used during the HOB producer phase that
+ * exist outside the HOB list. This HOB type describes how memory is used,
+ * not the physical attributes of memory.
+ */
+struct hob_mem_alloc {
+	struct hob_header	hdr;
+	/*
+	 * A GUID that defines the memory allocation region's type and purpose,
+	 * as well as other fields within the memory allocation HOB. This GUID
+	 * is used to define the additional data within the HOB that may be
+	 * present for the memory allocation HOB. Type efi_guid_t is defined in
+	 * InstallProtocolInterface() in the UEFI 2.0 specification.
+	 */
+	efi_guid_t		name;
+	/*
+	 * The base address of memory allocated by this HOB.
+	 * Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0
+	 * specification.
+	 */
+	phys_addr_t		mem_base;
+	/* The length in bytes of memory allocated by this HOB */
+	phys_size_t		mem_len;
+	/*
+	 * Defines the type of memory allocated by this HOB.
+	 * The memory type definition follows the EFI_MEMORY_TYPE definition.
+	 * Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0
+	 * specification.
+	 */
+	enum efi_mem_type	mem_type;
+	/* padding */
+	u8			reserved[4];
+};
+
+/*
+ * Describes the resource properties of all fixed, nonrelocatable resource
+ * ranges found on the processor host bus during the HOB producer phase.
+ */
+struct hob_res_desc {
+	struct hob_header	hdr;
+	/*
+	 * A GUID representing the owner of the resource. This GUID is
+	 * used by HOB consumer phase components to correlate device
+	 * ownership of a resource.
+	 */
+	efi_guid_t		owner;
+	u32			type;
+	u32			attr;
+	/* The physical start address of the resource region */
+	phys_addr_t		phys_start;
+	/* The number of bytes of the resource region */
+	phys_size_t		len;
+};
+
+/*
+ * Allows writers of executable content in the HOB producer phase to
+ * maintain and manage HOBs with specific GUID.
+ */
+struct hob_guid {
+	struct hob_header	hdr;
+	/* A GUID that defines the contents of this HOB */
+	efi_guid_t		name;
+	/* GUID specific data goes here */
+};
+
+/**
+ * get_next_hob() - return a pointer to the next HOB in the HOB list
+ *
+ * This macro returns a pointer to HOB that follows the HOB specified by hob
+ * in the HOB List.
+ *
+ * @hdr:    A pointer to a HOB.
+ *
+ * @return A pointer to the next HOB in the HOB list.
+ */
+static inline const struct hob_header *get_next_hob(const struct hob_header
+						    *hdr)
+{
+	return (const struct hob_header *)((uintptr_t)hdr + hdr->len);
+}
+
+/**
+ * end_of_hob() - determine if a HOB is the last HOB in the HOB list
+ *
+ * This macro determine if the HOB specified by hob is the last HOB in the
+ * HOB list.  If hob is last HOB in the HOB list, then true is returned.
+ * Otherwise, false is returned.
+ *
+ * @hdr:          A pointer to a HOB.
+ *
+ * @return true:  The HOB specified by hdr is the last HOB in the HOB list.
+ * @return false: The HOB specified by hdr is not the last HOB in the HOB list.
+ */
+static inline bool end_of_hob(const struct hob_header *hdr)
+{
+	return hdr->type == HOB_TYPE_EOH;
+}
+
+/**
+ * get_guid_hob_data() - return a pointer to data buffer from a HOB of
+ *                       type HOB_TYPE_GUID_EXT
+ *
+ * This macro returns a pointer to the data buffer in a HOB specified by hob.
+ * hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
+ *
+ * @hdr:    A pointer to a HOB.
+ *
+ * @return A pointer to the data buffer in a HOB.
+ */
+static inline void *get_guid_hob_data(const struct hob_header *hdr)
+{
+	return (void *)((uintptr_t)hdr + sizeof(struct hob_guid));
+}
+
+/**
+ * get_guid_hob_data_size() - return the size of the data buffer from a HOB
+ *                            of type HOB_TYPE_GUID_EXT
+ *
+ * This macro returns the size, in bytes, of the data buffer in a HOB
+ * specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
+ *
+ * @hdr:    A pointer to a HOB.
+ *
+ * @return The size of the data buffer.
+ */
+static inline u16 get_guid_hob_data_size(const struct hob_header *hdr)
+{
+	return hdr->len - sizeof(struct hob_guid);
+}
+
+/**
+ * Returns the next instance of a HOB type from the starting HOB.
+ *
+ * @type:     HOB type to search
+ * @hob_list: A pointer to the HOB list
+ *
+ * @return A HOB object with matching type; Otherwise NULL.
+ */
+const struct hob_header *hob_get_next_hob(uint type, const void *hob_list);
+
+/**
+ * Returns the next instance of the matched GUID HOB from the starting HOB.
+ *
+ * @guid:     GUID to search
+ * @hob_list: A pointer to the HOB list
+ *
+ * @return A HOB object with matching GUID; Otherwise NULL.
+ */
+const struct hob_header *hob_get_next_guid_hob(const efi_guid_t *guid,
+					       const void *hob_list);
+
+/**
+ * This function retrieves a GUID HOB data buffer and size.
+ *
+ * @hob_list:      A HOB list pointer.
+ * @len:           A pointer to the GUID HOB data buffer length.
+ *                 If the GUID HOB is located, the length will be updated.
+ * @guid           A pointer to HOB GUID.
+ *
+ * @return NULL:   Failed to find the GUID HOB.
+ * @return others: GUID HOB data buffer pointer.
+ */
+void *hob_get_guid_hob_data(const void *hob_list, u32 *len,
+			    const efi_guid_t *guid);
+
+#endif /* __HOB_H__ */
diff --git a/arch/x86/include/asm/i8254.h b/arch/x86/include/asm/i8254.h
new file mode 100644
index 0000000..d769daf
--- /dev/null
+++ b/arch/x86/include/asm/i8254.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ */
+
+/* i8254.h Intel 8254 PIT registers */
+
+#ifndef _ASMI386_I8254_H_
+#define _ASMI386_I8954_H_
+
+#define PIT_T0		0x00	/* PIT channel 0 count/status */
+#define PIT_T1		0x01	/* PIT channel 1 count/status */
+#define PIT_T2		0x02	/* PIT channel 2 count/status */
+#define PIT_COMMAND	0x03	/* PIT mode control, latch and read back */
+
+/* PIT Command Register Bit Definitions */
+
+#define PIT_CMD_CTR0	0x00	/* Select PIT counter 0 */
+#define PIT_CMD_CTR1	0x40	/* Select PIT counter 1 */
+#define PIT_CMD_CTR2	0x80	/* Select PIT counter 2 */
+
+#define PIT_CMD_LATCH	0x00	/* Counter Latch Command */
+#define PIT_CMD_LOW	0x10	/* Access counter bits 7-0 */
+#define PIT_CMD_HIGH	0x20	/* Access counter bits 15-8 */
+#define PIT_CMD_BOTH	0x30	/* Access counter bits 15-0 in two accesses */
+
+#define PIT_CMD_MODE0	0x00	/* Select mode 0 */
+#define PIT_CMD_MODE1	0x02	/* Select mode 1 */
+#define PIT_CMD_MODE2	0x04	/* Select mode 2 */
+#define PIT_CMD_MODE3	0x06	/* Select mode 3 */
+#define PIT_CMD_MODE4	0x08	/* Select mode 4 */
+#define PIT_CMD_MODE5	0x0a	/* Select mode 5 */
+
+/* The clock frequency of the i8253/i8254 PIT */
+#define PIT_TICK_RATE	1193182
+
+/**
+ * i8254_enable_beep() - Start a beep using the PCAT timer
+ *
+ * This starts beeping using the legacy i8254 timer. The beep may be silenced
+ * after a delay with i8254_disable_beep().
+ *
+ * @frequency_hz: Frequency of beep in Hz
+ * @return 0 if OK, -EINVAL if frequency_hz is 0
+ */
+int i8254_enable_beep(uint frequency_hz);
+
+/**
+ * i8254_disable_beep() - Disable the bepper
+ *
+ * This stops any existing beep
+ */
+void i8254_disable_beep(void);
+
+#endif /* _ASMI386_I8954_H_ */
diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h
new file mode 100644
index 0000000..b73052a
--- /dev/null
+++ b/arch/x86/include/asm/i8259.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ */
+
+/* i8259.h i8259 PIC Registers */
+
+#ifndef _ASMI386_I8259_H_
+#define _ASMI386_I8959_H_
+
+/* PIC I/O mapped registers */
+#define IRR		0x0	/* Interrupt Request Register */
+#define ISR		0x0	/* In-Service Register */
+#define ICW1		0x0	/* Initialization Control Word 1 */
+#define OCW2		0x0	/* Operation Control Word 2 */
+#define OCW3		0x0	/* Operation Control Word 3 */
+#define ICW2		0x1	/* Initialization Control Word 2 */
+#define ICW3		0x1	/* Initialization Control Word 3 */
+#define ICW4		0x1	/* Initialization Control Word 4 */
+#define IMR		0x1	/* Interrupt Mask Register */
+
+/* IRR, IMR, ISR and ICW3 bits */
+#define	IR7		0x80	/* IR7 */
+#define	IR6		0x40	/* IR6 */
+#define	IR5		0x20	/* IR5 */
+#define	IR4		0x10	/* IR4 */
+#define	IR3		0x08	/* IR3 */
+#define	IR2		0x04	/* IR2 */
+#define	IR1		0x02	/* IR1 */
+#define	IR0		0x01	/* IR0 */
+
+/* SEOI bits */
+#define	SEOI_IR7	0x07	/* IR7 */
+#define	SEOI_IR6	0x06	/* IR6 */
+#define	SEOI_IR5	0x05	/* IR5 */
+#define	SEOI_IR4	0x04	/* IR4 */
+#define	SEOI_IR3	0x03	/* IR3 */
+#define	SEOI_IR2	0x02	/* IR2 */
+#define	SEOI_IR1	0x01	/* IR1 */
+#define	SEOI_IR0	0x00	/* IR0 */
+
+/* OCW2 bits */
+#define OCW2_RCLR	0x00	/* Rotate/clear */
+#define OCW2_NEOI	0x20	/* Non specific EOI */
+#define OCW2_NOP	0x40	/* NOP */
+#define OCW2_SEOI	0x60	/* Specific EOI */
+#define OCW2_RSET	0x80	/* Rotate/set */
+#define OCW2_REOI	0xa0	/* Rotate on non specific EOI */
+#define OCW2_PSET	0xc0	/* Priority Set Command */
+#define OCW2_RSEOI	0xe0	/* Rotate on specific EOI */
+
+/* ICW1 bits */
+#define ICW1_SEL	0x10	/* Select ICW1 */
+#define ICW1_LTIM	0x08	/* Level-Triggered Interrupt Mode */
+#define ICW1_ADI	0x04	/* Address Interval */
+#define ICW1_SNGL	0x02	/* Single PIC */
+#define ICW1_EICW4	0x01	/* Expect initilization ICW4 */
+
+/*
+ * ICW2 is the starting vector number
+ *
+ * ICW2 is bit-mask of present slaves for a master device,
+ * or the slave ID for a slave device
+ */
+
+/* ICW4 bits */
+#define ICW4_AEOI	0x02	/* Automatic EOI Mode */
+#define ICW4_PM		0x01	/* Microprocessor Mode */
+
+#define ELCR1		0x4d0
+#define ELCR2		0x4d1
+
+int i8259_init(void);
+
+#endif /* _ASMI386_I8959_H_ */
diff --git a/arch/x86/include/asm/ibmpc.h b/arch/x86/include/asm/ibmpc.h
new file mode 100644
index 0000000..4368b6e
--- /dev/null
+++ b/arch/x86/include/asm/ibmpc.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ */
+
+#ifndef __ASM_IBMPC_H_
+#define __ASM_IBMPC_H_ 1
+
+/* misc ports in an ibm compatible pc */
+
+#define MASTER_PIC      0x20
+#define PIT_BASE	0x40
+#define KBDDATA         0x60
+#define SYSCTLB         0x62
+#define KBDCMD          0x64
+#define SYSCTLA         0x92
+#define SLAVE_PIC       0xa0
+
+#define UART0_BASE	0x3f8
+#define UART1_BASE	0x2f8
+
+#define UART0_IRQ	4
+#define UART1_IRQ	3
+
+#define KBD_IRQ		1
+#define MSE_IRQ		12
+
+#endif
diff --git a/arch/x86/include/asm/intel_regs.h b/arch/x86/include/asm/intel_regs.h
new file mode 100644
index 0000000..4e01722
--- /dev/null
+++ b/arch/x86/include/asm/intel_regs.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __ASM_INTEL_REGS_H
+#define __ASM_INTEL_REGS_H
+
+/* Access the memory-controller hub */
+#define MCH_BASE_ADDRESS	0xfed10000
+#define MCH_BASE_SIZE		0x8000
+#define MCHBAR_REG(reg)		(MCH_BASE_ADDRESS + (reg))
+
+#define MCHBAR_PEI_VERSION	0x5034
+#define MCH_PKG_POWER_LIMIT_LO	0x59a0
+#define MCH_PKG_POWER_LIMIT_HI	0x59a4
+#define MCH_DDR_POWER_LIMIT_LO	0x58e0
+#define MCH_DDR_POWER_LIMIT_HI	0x58e4
+
+/* Access the Root Complex Register Block */
+#define RCB_BASE_ADDRESS	0xfed1c000
+#define RCB_REG(reg)		(RCB_BASE_ADDRESS + (reg))
+
+#define SOFT_RESET_CTRL		0x38f4
+#define SOFT_RESET_DATA		0x38f8
+
+#endif
diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h
new file mode 100644
index 0000000..fdeb857
--- /dev/null
+++ b/arch/x86/include/asm/interrupt.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Graeme Russ, graeme.russ@gmail.com
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ */
+
+#ifndef __ASM_INTERRUPT_H_
+#define __ASM_INTERRUPT_H_ 1
+
+#include <asm/types.h>
+
+#define SYS_NUM_IRQS	16
+
+/* Architecture defined exceptions */
+enum x86_exception {
+	EXC_DE = 0,
+	EXC_DB,
+	EXC_NMI,
+	EXC_BP,
+	EXC_OF,
+	EXC_BR,
+	EXC_UD,
+	EXC_NM,
+	EXC_DF,
+	EXC_CSO,
+	EXC_TS,
+	EXC_NP,
+	EXC_SS,
+	EXC_GP,
+	EXC_PF,
+	EXC_MF = 16,
+	EXC_AC,
+	EXC_MC,
+	EXC_XM,
+	EXC_VE
+};
+
+/* arch/x86/cpu/interrupts.c */
+void set_vector(u8 intnum, void *routine);
+
+/* Architecture specific functions */
+void mask_irq(int irq);
+void unmask_irq(int irq);
+void specific_eoi(int irq);
+
+extern char exception_stack[];
+
+/**
+ * configure_irq_trigger() - Configure IRQ triggering
+ *
+ * Switch the given interrupt to be level / edge triggered
+ *
+ * @param int_num legacy interrupt number (3-7, 9-15)
+ * @param is_level_triggered true for level triggered interrupt, false for
+ *	edge triggered interrupt
+ */
+void configure_irq_trigger(int int_num, bool is_level_triggered);
+
+void *x86_get_idt(void);
+
+#endif
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
new file mode 100644
index 0000000..cf6c33c
--- /dev/null
+++ b/arch/x86/include/asm/io.h
@@ -0,0 +1,312 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+#include <linux/compiler.h>
+
+/*
+ * This file contains the definitions for the x86 IO instructions
+ * inb/inw/inl/outb/outw/outl and the "string versions" of the same
+ * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
+ * versions of the single-IO instructions (inb_p/inw_p/..).
+ *
+ * This file is not meant to be obfuscating: it's just complicated
+ * to (a) handle it all in a way that makes gcc able to optimize it
+ * as well as possible and (b) trying to avoid writing the same thing
+ * over and over again with slight variations and possibly making a
+ * mistake somewhere.
+ */
+
+/*
+ * Thanks to James van Artsdalen for a better timing-fix than
+ * the two short jumps: using outb's to a nonexistent port seems
+ * to guarantee better timings even on fast machines.
+ *
+ * On the other hand, I'd like to be sure of a non-existent port:
+ * I feel a bit unsafe about using 0x80 (should be safe, though)
+ *
+ *		Linus
+ */
+
+ /*
+  *  Bit simplified and optimized by Jan Hubicka
+  *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
+  *
+  *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
+  *  isa_read[wl] and isa_write[wl] fixed
+  *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
+  */
+
+#define IO_SPACE_LIMIT 0xffff
+
+#include <asm/types.h>
+
+
+#ifdef __KERNEL__
+
+
+/*
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the x86 architecture, we just read/write the
+ * memory location directly.
+ */
+
+#define readb(addr) (*(volatile u8 *)(uintptr_t)(addr))
+#define readw(addr) (*(volatile u16 *)(uintptr_t)(addr))
+#define readl(addr) (*(volatile u32 *)(uintptr_t)(addr))
+#define readq(addr) (*(volatile u64 *)(uintptr_t)(addr))
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_readq readq
+
+#define writeb(b, addr) (*(volatile u8 *)(addr) = (b))
+#define writew(b, addr) (*(volatile u16 *)(addr) = (b))
+#define writel(b, addr) (*(volatile u32 *)(addr) = (b))
+#define writeq(b, addr) (*(volatile u64 *)(addr) = (b))
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+#define __raw_writeq writeq
+
+#define memset_io(a,b,c)	memset((a),(b),(c))
+#define memcpy_fromio(a,b,c)	memcpy((a),(b),(c))
+#define memcpy_toio(a,b,c)	memcpy((a),(b),(c))
+
+#define out_arch(type, endian, a, v)	__raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a)	endian##_to_cpu(__raw_read##type(a))
+
+#define out_le64(a, v)	out_arch(q, le64, a, v)
+#define out_le32(a, v)	out_arch(l, le32, a, v)
+#define out_le16(a, v)	out_arch(w, le16, a, v)
+
+#define in_le64(a)	in_arch(q, le64, a)
+#define in_le32(a)	in_arch(l, le32, a)
+#define in_le16(a)	in_arch(w, le16, a)
+
+#define out_be32(a, v)	out_arch(l, be32, a, v)
+#define out_be16(a, v)	out_arch(w, be16, a, v)
+
+#define in_be32(a)	in_arch(l, be32, a)
+#define in_be16(a)	in_arch(w, be16, a)
+
+#define out_8(a, v)	__raw_writeb(v, a)
+#define in_8(a)		__raw_readb(a)
+
+#define clrbits(type, addr, clear) \
+	out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+	out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+	out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+#endif /* __KERNEL__ */
+
+#ifdef SLOW_IO_BY_JUMPING
+#define __SLOW_DOWN_IO "\njmp 1f\n1:\tjmp 1f\n1:"
+#else
+#define __SLOW_DOWN_IO "\noutb %%al,$0xed"
+#endif
+
+#ifdef REALLY_SLOW_IO
+#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO
+#else
+#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO
+#endif
+
+
+/*
+ * Talk about misusing macros..
+ */
+#define __OUT1(s,x) \
+static inline void _out##s(unsigned x value, unsigned short port) {
+
+#define __OUT2(s,s1,s2) \
+__asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
+
+
+#define __OUT(s,s1,x) \
+__OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \
+__OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));}
+
+#define __IN1(s) \
+static inline RETURN_TYPE _in##s(unsigned short port) { RETURN_TYPE _v;
+
+#define __IN2(s,s1,s2) \
+__asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
+
+#define __IN(s,s1,i...) \
+__IN1(s) __IN2(s,s1,"w") : "=a" (_v) : "Nd" (port) ,##i ); return _v; } \
+__IN1(s##_p) __IN2(s,s1,"w") __FULL_SLOW_DOWN_IO : "=a" (_v) : "Nd" (port) ,##i ); return _v; }
+
+#define __INS(s) \
+static inline void ins##s(unsigned short port, void * addr, unsigned long count) \
+{ __asm__ __volatile__ ("rep ; ins" #s \
+: "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
+
+#define __OUTS(s) \
+static inline void outs##s(unsigned short port, const void * addr, unsigned long count) \
+{ __asm__ __volatile__ ("rep ; outs" #s \
+: "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
+
+#define RETURN_TYPE unsigned char
+__IN(b,"")
+#undef RETURN_TYPE
+#define RETURN_TYPE unsigned short
+__IN(w,"")
+#undef RETURN_TYPE
+#define RETURN_TYPE unsigned int
+__IN(l,"")
+#undef RETURN_TYPE
+
+#define inb(port)	_inb((uintptr_t)(port))
+#define inw(port)	_inw((uintptr_t)(port))
+#define inl(port)	_inl((uintptr_t)(port))
+
+__OUT(b,"b",char)
+__OUT(w,"w",short)
+__OUT(l,,int)
+
+#define outb(val, port)	_outb(val, (uintptr_t)(port))
+#define outw(val, port)	_outw(val, (uintptr_t)(port))
+#define outl(val, port)	_outl(val, (uintptr_t)(port))
+
+__INS(b)
+__INS(w)
+__INS(l)
+
+__OUTS(b)
+__OUTS(w)
+__OUTS(l)
+
+/* IO space accessors */
+#define clrio(type, addr, clear) \
+	out##type(in##type(addr) & ~(clear), (addr))
+
+#define setio(type, addr, set) \
+	out##type(in##type(addr) | (set), (addr))
+
+#define clrsetio(type, addr, clear, set) \
+	out##type((in##type(addr) & ~(clear)) | (set), (addr))
+
+#define clrio_32(addr, clear) clrio(l, addr, clear)
+#define clrio_16(addr, clear) clrio(w, addr, clear)
+#define clrio_8(addr, clear) clrio(b, addr, clear)
+
+#define setio_32(addr, set) setio(l, addr, set)
+#define setio_16(addr, set) setio(w, addr, set)
+#define setio_8(addr, set) setio(b, addr, set)
+
+#define clrsetio_32(addr, clear, set) clrsetio(l, addr, clear, set)
+#define clrsetio_16(addr, clear, set) clrsetio(w, addr, clear, set)
+#define clrsetio_8(addr, clear, set) clrsetio(b, addr, clear, set)
+
+static inline void sync(void)
+{
+}
+
+/*
+ * TODO: The kernel offers some more advanced versions of barriers, it might
+ * have some advantages to use them instead of the simple one here.
+ */
+#define dmb()		__asm__ __volatile__ ("" : : : "memory")
+#define __iormb()	dmb()
+#define __iowmb()	dmb()
+
+/*
+ * Read/write from/to an (offsettable) iomem cookie. It might be a PIO
+ * access or a MMIO access, these functions don't care. The info is
+ * encoded in the hardware mapping set up by the mapping functions
+ * (or the cookie itself, depending on implementation and hw).
+ *
+ * The generic routines don't assume any hardware mappings, and just
+ * encode the PIO/MMIO as part of the cookie. They coldly assume that
+ * the MMIO IO mappings are not in the low address range.
+ *
+ * Architectures for which this is not true can't use this generic
+ * implementation and should do their own copy.
+ */
+
+/*
+ * We assume that all the low physical PIO addresses (0-0xffff) always
+ * PIO. That means we can do some sanity checks on the low bits, and
+ * don't need to just take things for granted.
+ */
+#define PIO_RESERVED	0x10000UL
+
+/*
+ * Ugly macros are a way of life.
+ */
+#define IO_COND(addr, is_pio, is_mmio) do {			\
+	unsigned long port = (unsigned long __force)addr;	\
+	if (port >= PIO_RESERVED) {				\
+		is_mmio;					\
+	} else {						\
+		is_pio;						\
+	}							\
+} while (0)
+
+static inline u8 ioread8(const volatile void __iomem *addr)
+{
+	IO_COND(addr, return inb(port), return readb(addr));
+	return 0xff;
+}
+
+static inline u16 ioread16(const volatile void __iomem *addr)
+{
+	IO_COND(addr, return inw(port), return readw(addr));
+	return 0xffff;
+}
+
+static inline u32 ioread32(const volatile void __iomem *addr)
+{
+	IO_COND(addr, return inl(port), return readl(addr));
+	return 0xffffffff;
+}
+
+static inline void iowrite8(u8 value, volatile void __iomem *addr)
+{
+	IO_COND(addr, outb(value, port), writeb(value, addr));
+}
+
+static inline void iowrite16(u16 value, volatile void __iomem *addr)
+{
+	IO_COND(addr, outw(value, port), writew(value, addr));
+}
+
+static inline void iowrite32(u32 value, volatile void __iomem *addr)
+{
+	IO_COND(addr, outl(value, port), writel(value, addr));
+}
+
+#include <asm-generic/io.h>
+
+#endif /* _ASM_IO_H */
diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h
new file mode 100644
index 0000000..9e004e9
--- /dev/null
+++ b/arch/x86/include/asm/ioapic.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * From coreboot file of the same name
+ *
+ * Copyright (C) 2010 coresystems GmbH
+ */
+
+#ifndef __ASM_IOAPIC_H
+#define __ASM_IOAPIC_H
+
+#define IO_APIC_ADDR		0xfec00000
+
+/* Direct addressed register */
+#define IO_APIC_INDEX		(IO_APIC_ADDR + 0x00)
+#define IO_APIC_DATA		(IO_APIC_ADDR + 0x10)
+
+/* Indirect addressed register offset */
+#define IO_APIC_ID		0x00
+#define IO_APIC_VER		0x01
+
+/**
+ * io_apic_read() - Read I/O APIC register
+ *
+ * This routine reads I/O APIC indirect addressed register.
+ *
+ * @reg:	address of indirect addressed register
+ * @return:	register value to read
+ */
+u32 io_apic_read(u32 reg);
+
+/**
+ * io_apic_write() - Write I/O APIC register
+ *
+ * This routine writes I/O APIC indirect addressed register.
+ *
+ * @reg:	address of indirect addressed register
+ * @val:	register value to write
+ */
+void io_apic_write(u32 reg, u32 val);
+
+void io_apic_set_id(int ioapic_id);
+
+#endif
diff --git a/arch/x86/include/asm/ioctl.h b/arch/x86/include/asm/ioctl.h
new file mode 100644
index 0000000..b279fe0
--- /dev/null
+++ b/arch/x86/include/asm/ioctl.h
@@ -0,0 +1 @@
+#include <asm-generic/ioctl.h>
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
new file mode 100644
index 0000000..e5c9160
--- /dev/null
+++ b/arch/x86/include/asm/irq.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _ARCH_IRQ_H_
+#define _ARCH_IRQ_H_
+
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/**
+ * Intel interrupt router configuration mechanism
+ *
+ * There are two known ways of Intel interrupt router configuration mechanism
+ * so far. On most cases, the IRQ routing configuraiton is controlled by PCI
+ * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
+ * On some newer platforms like BayTrail and Braswell, the IRQ routing is now
+ * in the IBASE register block where IBASE is memory-mapped.
+ */
+enum pirq_config {
+	PIRQ_VIA_PCI,
+	PIRQ_VIA_IBASE
+};
+
+struct pirq_regmap {
+	int link;
+	int offset;
+};
+
+/**
+ * Intel interrupt router control block
+ *
+ * Its members' value will be filled in based on device tree's input.
+ *
+ * @config:	PIRQ_VIA_PCI or PIRQ_VIA_IBASE
+ * @link_base:	link value base number
+ * @link_num:	number of PIRQ links supported
+ * @has_regmap:	has mapping table between PIRQ link and routing register offset
+ * @irq_mask:	IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
+ *		IRQ N is available to be routed
+ * @lb_bdf:	irq router's PCI bus/device/function number encoding
+ * @ibase:	IBASE register block base address
+ * @actl_8bit:	ACTL register width is 8-bit (for ICH series chipset)
+ * @actl_addr:	ACTL register offset
+ */
+struct irq_router {
+	int config;
+	u32 link_base;
+	int link_num;
+	bool has_regmap;
+	struct pirq_regmap *regmap;
+	u16 irq_mask;
+	u32 bdf;
+	u32 ibase;
+	bool actl_8bit;
+	int actl_addr;
+};
+
+struct pirq_routing {
+	int bdf;
+	int pin;
+	int pirq;
+};
+
+#define PIRQ_BITMAP		0xdef8
+
+#endif /* _ARCH_IRQ_H_ */
diff --git a/arch/x86/include/asm/ist.h b/arch/x86/include/asm/ist.h
new file mode 100644
index 0000000..80b8597
--- /dev/null
+++ b/arch/x86/include/asm/ist.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _ASM_X86_IST_H
+#define _ASM_X86_IST_H
+
+/*
+ * Include file for the interface to IST BIOS
+ * Copyright 2002 Andy Grover <andrew.grover@intel.com>
+ */
+
+
+#include <linux/types.h>
+
+struct ist_info {
+	__u32 signature;
+	__u32 command;
+	__u32 event;
+	__u32 perf_level;
+};
+
+#ifdef __KERNEL__
+
+extern struct ist_info ist_info;
+
+#endif	/* __KERNEL__ */
+#endif /* _ASM_X86_IST_H */
diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h
new file mode 100644
index 0000000..78eef6a
--- /dev/null
+++ b/arch/x86/include/asm/lapic.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * From coreboot file of same name
+ *
+ * Copyright (C) 2014 Google, Inc
+ */
+
+#ifndef _ARCH_ASM_LAPIC_H
+#define _ARCH_ASM_LAPIC_H
+
+#define LAPIC_DEFAULT_BASE		0xfee00000
+
+#define LAPIC_ID			0x020
+#define LAPIC_LVR			0x030
+
+#define LAPIC_TASKPRI			0x080
+#define LAPIC_TPRI_MASK			0xff
+
+#define LAPIC_RRR			0x0c0
+
+#define LAPIC_SPIV			0x0f0
+#define LAPIC_SPIV_ENABLE		0x100
+
+#define LAPIC_ICR			0x300
+#define LAPIC_DEST_SELF			0x40000
+#define LAPIC_DEST_ALLINC		0x80000
+#define LAPIC_DEST_ALLBUT		0xc0000
+#define LAPIC_ICR_RR_MASK		0x30000
+#define LAPIC_ICR_RR_INVALID		0x00000
+#define LAPIC_ICR_RR_INPROG		0x10000
+#define LAPIC_ICR_RR_VALID		0x20000
+#define LAPIC_INT_LEVELTRIG		0x08000
+#define LAPIC_INT_ASSERT		0x04000
+#define LAPIC_ICR_BUSY			0x01000
+#define LAPIC_DEST_LOGICAL		0x00800
+#define LAPIC_DM_FIXED			0x00000
+#define LAPIC_DM_LOWEST			0x00100
+#define LAPIC_DM_SMI			0x00200
+#define LAPIC_DM_REMRD			0x00300
+#define LAPIC_DM_NMI			0x00400
+#define LAPIC_DM_INIT			0x00500
+#define LAPIC_DM_STARTUP		0x00600
+#define LAPIC_DM_EXTINT			0x00700
+#define LAPIC_VECTOR_MASK		0x000ff
+
+#define LAPIC_ICR2			0x310
+#define GET_LAPIC_DEST_FIELD(x)		(((x) >> 24) & 0xff)
+#define SET_LAPIC_DEST_FIELD(x)		((x) << 24)
+
+#define LAPIC_LVT0			0x350
+#define LAPIC_LVT1			0x360
+#define LAPIC_LVT_MASKED		(1 << 16)
+#define LAPIC_LVT_LEVEL_TRIGGER		(1 << 15)
+#define LAPIC_LVT_REMOTE_IRR		(1 << 14)
+#define LAPIC_INPUT_POLARITY		(1 << 13)
+#define LAPIC_SEND_PENDING		(1 << 12)
+#define LAPIC_LVT_RESERVED_1		(1 << 11)
+#define LAPIC_DELIVERY_MODE_MASK	(7 << 8)
+#define LAPIC_DELIVERY_MODE_FIXED	(0 << 8)
+#define LAPIC_DELIVERY_MODE_NMI		(4 << 8)
+#define LAPIC_DELIVERY_MODE_EXTINT	(7 << 8)
+
+unsigned long lapic_read(unsigned long reg);
+
+void lapic_write(unsigned long reg, unsigned long v);
+
+void enable_lapic(void);
+
+void disable_lapic(void);
+
+unsigned long lapicid(void);
+
+int lapic_remote_read(int apicid, int reg, unsigned long *pvalue);
+
+void lapic_setup(void);
+
+#endif
diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h
new file mode 100644
index 0000000..bdca72e
--- /dev/null
+++ b/arch/x86/include/asm/linkage.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_X86_LINKAGE_H
+#define _ASM_X86_LINKAGE_H
+
+#define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0)))
+
+#endif /* _ASM_X86_LINKAGE_H */
diff --git a/arch/x86/include/asm/lpc_common.h b/arch/x86/include/asm/lpc_common.h
new file mode 100644
index 0000000..d462c2e
--- /dev/null
+++ b/arch/x86/include/asm/lpc_common.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __ASM_LPC_COMMON_H
+#define __ASM_LPC_COMMON_H
+
+#define PCH_RCBA_BASE		0xf0
+
+#define RC		0x3400	/* 32bit */
+#define GCS		0x3410	/* 32bit */
+
+#define PMBASE			0x40
+#define ACPI_CNTL		0x44
+
+#define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
+#define  COMB_DEC_RANGE		(1 << 4)  /* 0x2f8-0x2ff (COM2) */
+#define  COMA_DEC_RANGE		(0 << 0)  /* 0x3f8-0x3ff (COM1) */
+#define LPC_EN			0x82 /* LPC IF Enables Register */
+#define  CNF2_LPC_EN		(1 << 13) /* 0x4e/0x4f */
+#define  CNF1_LPC_EN		(1 << 12) /* 0x2e/0x2f */
+#define  MC_LPC_EN		(1 << 11) /* 0x62/0x66 */
+#define  KBC_LPC_EN		(1 << 10) /* 0x60/0x64 */
+#define  GAMEH_LPC_EN		(1 << 9)  /* 0x208/0x20f */
+#define  GAMEL_LPC_EN		(1 << 8)  /* 0x200/0x207 */
+#define  FDD_LPC_EN		(1 << 3)  /* LPC_IO_DEC[12] */
+#define  LPT_LPC_EN		(1 << 2)  /* LPC_IO_DEC[9:8] */
+#define  COMB_LPC_EN		(1 << 1)  /* LPC_IO_DEC[6:4] */
+#define  COMA_LPC_EN		(1 << 0)  /* LPC_IO_DEC[3:2] */
+#define LPC_GEN1_DEC		0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC		0x88 /* LPC IF Generic Decode Range 2 */
+#define LPC_GEN3_DEC		0x8c /* LPC IF Generic Decode Range 3 */
+#define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
+#define LPC_GENX_DEC(x)		(0x84 + 4 * (x))
+#define  GEN_DEC_RANGE_256B	0xfc0000  /* 256 Bytes */
+#define  GEN_DEC_RANGE_128B	0x7c0000  /* 128 Bytes */
+#define  GEN_DEC_RANGE_64B	0x3c0000  /* 64 Bytes */
+#define  GEN_DEC_RANGE_32B	0x1c0000  /* 32 Bytes */
+#define  GEN_DEC_RANGE_16B	0x0c0000  /* 16 Bytes */
+#define  GEN_DEC_RANGE_8B	0x040000  /* 8 Bytes */
+#define  GEN_DEC_RANGE_4B	0x000000  /* 4 Bytes */
+#define  GEN_DEC_RANGE_EN	(1 << 0)  /* Range Enable */
+
+/**
+ * lpc_common_early_init() - Set up common LPC init
+ *
+ * This sets up the legacy decode areas, GEN_DEC, SPI prefetch and Port80. It
+ * also puts the RCB in the correct place so that RCB_REG() works.
+ *
+ * @dev:	LPC device (a child of the PCH)
+ * @return 0 on success, -ve on error
+ */
+int lpc_common_early_init(struct udevice *dev);
+
+int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect);
+
+#endif
diff --git a/arch/x86/include/asm/me_common.h b/arch/x86/include/asm/me_common.h
new file mode 100644
index 0000000..49d8862
--- /dev/null
+++ b/arch/x86/include/asm/me_common.h
@@ -0,0 +1,372 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/me.h
+ *
+ * Coreboot copies lots of code around. Here we are trying to keep the common
+ * code in a separate file to reduce code duplication and hopefully make it
+ * easier to add new platform.
+ *
+ * Copyright (C) 2016 Google, Inc
+ */
+
+#ifndef __ASM_ME_COMMON_H
+#define __ASM_ME_COMMON_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <pci.h>
+
+#define MCHBAR_PEI_VERSION	0x5034
+
+#define ME_RETRY		100000	/* 1 second */
+#define ME_DELAY		10	/* 10 us */
+
+/*
+ * Management Engine PCI registers
+ */
+
+#define PCI_CPU_MEBASE_L	0x70	/* Set by MRC */
+#define PCI_CPU_MEBASE_H	0x74	/* Set by MRC */
+
+#define PCI_ME_HFS		0x40
+#define  ME_HFS_CWS_RESET	0
+#define  ME_HFS_CWS_INIT	1
+#define  ME_HFS_CWS_REC		2
+#define  ME_HFS_CWS_NORMAL	5
+#define  ME_HFS_CWS_WAIT	6
+#define  ME_HFS_CWS_TRANS	7
+#define  ME_HFS_CWS_INVALID	8
+#define  ME_HFS_STATE_PREBOOT	0
+#define  ME_HFS_STATE_M0_UMA	1
+#define  ME_HFS_STATE_M3	4
+#define  ME_HFS_STATE_M0	5
+#define  ME_HFS_STATE_BRINGUP	6
+#define  ME_HFS_STATE_ERROR	7
+#define  ME_HFS_ERROR_NONE	0
+#define  ME_HFS_ERROR_UNCAT	1
+#define  ME_HFS_ERROR_IMAGE	3
+#define  ME_HFS_ERROR_DEBUG	4
+#define  ME_HFS_MODE_NORMAL	0
+#define  ME_HFS_MODE_DEBUG	2
+#define  ME_HFS_MODE_DIS	3
+#define  ME_HFS_MODE_OVER_JMPR	4
+#define  ME_HFS_MODE_OVER_MEI	5
+#define  ME_HFS_BIOS_DRAM_ACK	1
+#define  ME_HFS_ACK_NO_DID	0
+#define  ME_HFS_ACK_RESET	1
+#define  ME_HFS_ACK_PWR_CYCLE	2
+#define  ME_HFS_ACK_S3		3
+#define  ME_HFS_ACK_S4		4
+#define  ME_HFS_ACK_S5		5
+#define  ME_HFS_ACK_GBL_RESET	6
+#define  ME_HFS_ACK_CONTINUE	7
+
+struct me_hfs {
+	u32 working_state:4;
+	u32 mfg_mode:1;
+	u32 fpt_bad:1;
+	u32 operation_state:3;
+	u32 fw_init_complete:1;
+	u32 ft_bup_ld_flr:1;
+	u32 update_in_progress:1;
+	u32 error_code:4;
+	u32 operation_mode:4;
+	u32 reserved:4;
+	u32 boot_options_present:1;
+	u32 ack_data:3;
+	u32 bios_msg_ack:4;
+} __packed;
+
+#define PCI_ME_UMA		0x44
+
+struct me_uma {
+	u32 size:6;
+	u32 reserved_1:10;
+	u32 valid:1;
+	u32 reserved_0:14;
+	u32 set_to_one:1;
+} __packed;
+
+#define PCI_ME_H_GS		0x4c
+#define  ME_INIT_DONE		1
+#define  ME_INIT_STATUS_SUCCESS	0
+#define  ME_INIT_STATUS_NOMEM	1
+#define  ME_INIT_STATUS_ERROR	2
+
+struct me_did {
+	u32 uma_base:16;
+	u32 reserved:7;
+	u32 rapid_start:1;	/* Broadwell only */
+	u32 status:4;
+	u32 init_done:4;
+} __packed;
+
+#define PCI_ME_GMES		0x48
+#define  ME_GMES_PHASE_ROM	0
+#define  ME_GMES_PHASE_BUP	1
+#define  ME_GMES_PHASE_UKERNEL	2
+#define  ME_GMES_PHASE_POLICY	3
+#define  ME_GMES_PHASE_MODULE	4
+#define  ME_GMES_PHASE_UNKNOWN	5
+#define  ME_GMES_PHASE_HOST	6
+
+struct me_gmes {
+	u32 bist_in_prog:1;
+	u32 icc_prog_sts:2;
+	u32 invoke_mebx:1;
+	u32 cpu_replaced_sts:1;
+	u32 mbp_rdy:1;
+	u32 mfs_failure:1;
+	u32 warm_rst_req_for_df:1;
+	u32 cpu_replaced_valid:1;
+	u32 reserved_1:2;
+	u32 fw_upd_ipu:1;
+	u32 reserved_2:4;
+	u32 current_state:8;
+	u32 current_pmevent:4;
+	u32 progress_code:4;
+} __packed;
+
+#define PCI_ME_HERES		0xbc
+#define  PCI_ME_EXT_SHA1	0x00
+#define  PCI_ME_EXT_SHA256	0x02
+#define PCI_ME_HER(x)		(0xc0+(4*(x)))
+
+struct me_heres {
+	u32 extend_reg_algorithm:4;
+	u32 reserved:26;
+	u32 extend_feature_present:1;
+	u32 extend_reg_valid:1;
+} __packed;
+
+/*
+ * Management Engine MEI registers
+ */
+
+#define MEI_H_CB_WW		0x00
+#define MEI_H_CSR		0x04
+#define MEI_ME_CB_RW		0x08
+#define MEI_ME_CSR_HA		0x0c
+
+struct mei_csr {
+	u32 interrupt_enable:1;
+	u32 interrupt_status:1;
+	u32 interrupt_generate:1;
+	u32 ready:1;
+	u32 reset:1;
+	u32 reserved:3;
+	u32 buffer_read_ptr:8;
+	u32 buffer_write_ptr:8;
+	u32 buffer_depth:8;
+} __packed;
+
+#define MEI_ADDRESS_CORE	0x01
+#define MEI_ADDRESS_AMT		0x02
+#define MEI_ADDRESS_RESERVED	0x03
+#define MEI_ADDRESS_WDT		0x04
+#define MEI_ADDRESS_MKHI	0x07
+#define MEI_ADDRESS_ICC		0x08
+#define MEI_ADDRESS_THERMAL	0x09
+
+#define MEI_HOST_ADDRESS	0
+
+struct mei_header {
+	u32 client_address:8;
+	u32 host_address:8;
+	u32 length:9;
+	u32 reserved:6;
+	u32 is_complete:1;
+} __packed;
+
+#define MKHI_GROUP_ID_CBM	0x00
+#define MKHI_GROUP_ID_FWCAPS	0x03
+#define MKHI_GROUP_ID_MDES	0x08
+#define MKHI_GROUP_ID_GEN	0xff
+
+#define MKHI_GET_FW_VERSION	0x02
+#define MKHI_END_OF_POST	0x0c
+#define MKHI_FEATURE_OVERRIDE	0x14
+
+/* Ivybridge only: */
+#define MKHI_GLOBAL_RESET	0x0b
+#define MKHI_FWCAPS_GET_RULE	0x02
+#define MKHI_MDES_ENABLE	0x09
+
+/* Broadwell only: */
+#define MKHI_GLOBAL_RESET	0x0b
+#define MKHI_FWCAPS_GET_RULE	0x02
+#define MKHI_GROUP_ID_HMRFPO	0x05
+#define MKHI_HMRFPO_LOCK	0x02
+#define MKHI_HMRFPO_LOCK_NOACK	0x05
+#define MKHI_MDES_ENABLE	0x09
+#define MKHI_END_OF_POST_NOACK	0x1a
+
+struct mkhi_header {
+	u32 group_id:8;
+	u32 command:7;
+	u32 is_response:1;
+	u32 reserved:8;
+	u32 result:8;
+} __packed;
+
+struct me_fw_version {
+	u16 code_minor;
+	u16 code_major;
+	u16 code_build_number;
+	u16 code_hot_fix;
+	u16 recovery_minor;
+	u16 recovery_major;
+	u16 recovery_build_number;
+	u16 recovery_hot_fix;
+} __packed;
+
+
+#define HECI_EOP_STATUS_SUCCESS       0x0
+#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
+
+#define CBM_RR_GLOBAL_RESET	0x01
+
+#define GLOBAL_RESET_BIOS_MRC	0x01
+#define GLOBAL_RESET_BIOS_POST	0x02
+#define GLOBAL_RESET_MEBX	0x03
+
+struct me_global_reset {
+	u8 request_origin;
+	u8 reset_type;
+} __packed;
+
+enum me_bios_path {
+	ME_NORMAL_BIOS_PATH,
+	ME_S3WAKE_BIOS_PATH,
+	ME_ERROR_BIOS_PATH,
+	ME_RECOVERY_BIOS_PATH,
+	ME_DISABLE_BIOS_PATH,
+	ME_FIRMWARE_UPDATE_BIOS_PATH,
+};
+
+struct __packed mefwcaps_sku {
+	u32 full_net:1;
+	u32 std_net:1;
+	u32 manageability:1;
+	u32 small_business:1;
+	u32 l3manageability:1;
+	u32 intel_at:1;
+	u32 intel_cls:1;
+	u32 reserved:3;
+	u32 intel_mpc:1;
+	u32 icc_over_clocking:1;
+	u32 pavp:1;
+	u32 reserved_1:4;
+	u32 ipv6:1;
+	u32 kvm:1;
+	u32 och:1;
+	u32 vlan:1;
+	u32 tls:1;
+	u32 reserved_4:1;
+	u32 wlan:1;
+	u32 reserved_5:8;
+};
+
+struct __packed tdt_state_flag {
+	u16 lock_state:1;
+	u16 authenticate_module:1;
+	u16 s3authentication:1;
+	u16 flash_wear_out:1;
+	u16 flash_variable_security:1;
+	u16 wwan3gpresent:1;	/* ivybridge only */
+	u16 wwan3goob:1;	/* ivybridge only */
+	u16 reserved:9;
+};
+
+struct __packed tdt_state_info {
+	u8 state;
+	u8 last_theft_trigger;
+	struct tdt_state_flag flags;
+};
+
+struct __packed mbp_rom_bist_data {
+	u16 device_id;
+	u16 fuse_test_flags;
+	u32 umchid[4];
+};
+
+struct __packed mbp_platform_key {
+	u32 key[8];
+};
+
+struct __packed mbp_header {
+	u32 mbp_size:8;
+	u32 num_entries:8;
+	u32 rsvd:16;
+};
+
+struct __packed mbp_item_header {
+	u32 app_id:8;
+	u32 item_id:8;
+	u32 length:8;
+	u32 rsvd:8;
+};
+
+struct __packed me_fwcaps {
+	u32 id;
+	u8 length;
+	struct mefwcaps_sku caps_sku;
+	u8 reserved[3];
+};
+
+/**
+ * intel_me_status() - Check Intel Management Engine status
+ *
+ * @me_dev:	Management engine PCI device
+ */
+void intel_me_status(struct udevice *me_dev);
+
+/**
+ * intel_early_me_init() - Early Intel Management Engine init
+ *
+ * @me_dev:	Management engine PCI device
+ * @return 0 if OK, -ve on error
+ */
+int intel_early_me_init(struct udevice *me_dev);
+
+/**
+ * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine
+ *
+ * @me_dev:	Management engine PCI device
+ * @return UMA size if OK, -EINVAL on error
+ */
+int intel_early_me_uma_size(struct udevice *me_dev);
+
+/**
+ * intel_early_me_init_done() - Complete Intel Management Engine init
+ *
+ * @dev:	Northbridge device
+ * @me_dev:	Management engine PCI device
+ * @status:	Status result (ME_INIT_...)
+ * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT
+ * if ME did not respond
+ */
+int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
+			     uint status);
+
+int intel_me_hsio_version(struct udevice *dev, uint16_t *version,
+			  uint16_t *checksum);
+
+static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
+				      int offset)
+{
+	u32 dword;
+
+	dm_pci_read_config32(me_dev, offset, &dword);
+	memcpy(ptr, &dword, sizeof(dword));
+}
+
+static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
+				       int offset)
+{
+	u32 dword = 0;
+
+	memcpy(&dword, ptr, sizeof(dword));
+	dm_pci_write_config32(me_dev, offset, dword);
+}
+#endif
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
new file mode 100644
index 0000000..4ab7504
--- /dev/null
+++ b/arch/x86/include/asm/microcode.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#ifndef __ASM_ARCH_MICROCODE_H
+#define __ASM_ARCH_MICROCODE_H
+
+#ifndef __ASSEMBLY__
+
+/* This is a declaration for ucode_base in start.S */
+extern u32 ucode_base;
+extern u32 ucode_size;
+
+/**
+ * microcode_update_intel() - Apply microcode updates
+ *
+ * Applies any microcode updates in the device tree.
+ *
+ * @return 0 if OK, -EEXIST if the updates were already applied, -ENOENT if
+ * not updates were found, -EINVAL if an update was invalid
+ */
+int microcode_update_intel(void);
+
+/**
+ * microcode_read_rev() - Read the microcode version
+ *
+ * This reads the microcode version of the currently running CPU
+ *
+ * @return microcode version number
+ */
+int microcode_read_rev(void);
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h
new file mode 100644
index 0000000..fb59e2f
--- /dev/null
+++ b/arch/x86/include/asm/mp.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef _X86_MP_H_
+#define _X86_MP_H_
+
+#include <asm/atomic.h>
+
+typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);
+
+/*
+ * A mp_flight_record details a sequence of calls for the APs to perform
+ * along with the BSP to coordinate sequencing. Each flight record either
+ * provides a barrier for each AP before calling the callback or the APs
+ * are allowed to perform the callback without waiting. Regardless, each
+ * record has the cpus_entered field incremented for each record. When
+ * the BSP observes that the cpus_entered matches the number of APs
+ * the bsp_call is called with bsp_arg and upon returning releases the
+ * barrier allowing the APs to make further progress.
+ *
+ * Note that ap_call() and bsp_call() can be NULL. In the NULL case the
+ * callback will just not be called.
+ */
+struct mp_flight_record {
+	atomic_t barrier;
+	atomic_t cpus_entered;
+	mp_callback_t ap_call;
+	void *ap_arg;
+	mp_callback_t bsp_call;
+	void *bsp_arg;
+} __attribute__((aligned(ARCH_DMA_MINALIGN)));
+
+#define MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
+	{							\
+		.barrier = ATOMIC_INIT(barrier_),		\
+		.cpus_entered = ATOMIC_INIT(0),			\
+		.ap_call = ap_func_,				\
+		.ap_arg = ap_arg_,				\
+		.bsp_call = bsp_func_,				\
+		.bsp_arg = bsp_arg_,				\
+	}
+
+#define MP_FR_BLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
+	MP_FLIGHT_RECORD(0, ap_func, ap_arg, bsp_func, bsp_arg)
+
+#define MP_FR_NOBLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
+	MP_FLIGHT_RECORD(1, ap_func, ap_arg, bsp_func, bsp_arg)
+
+/*
+ * The mp_params structure provides the arguments to the mp subsystem
+ * for bringing up APs.
+ *
+ * At present this is overkill for U-Boot, but it may make it easier to add
+ * SMM support.
+ */
+struct mp_params {
+	int parallel_microcode_load;
+	const void *microcode_pointer;
+	/* Flight plan  for APs and BSP */
+	struct mp_flight_record *flight_plan;
+	int num_records;
+};
+
+/*
+ * mp_init() will set up the SIPI vector and bring up the APs according to
+ * mp_params. Each flight record will be executed according to the plan. Note
+ * that the MP infrastructure uses SMM default area without saving it. It's
+ * up to the chipset or mainboard to either e820 reserve this area or save this
+ * region prior to calling mp_init() and restoring it after mp_init returns.
+ *
+ * At the time mp_init() is called the MTRR MSRs are mirrored into APs then
+ * caching is enabled before running the flight plan.
+ *
+ * The MP init has the following properties:
+ * 1. APs are brought up in parallel.
+ * 2. The ordering of cpu number and APIC ids is not deterministic.
+ *    Therefore, one cannot rely on this property or the order of devices in
+ *    the device tree unless the chipset or mainboard know the APIC ids
+ *    a priori.
+ *
+ * mp_init() returns < 0 on error, 0 on success.
+ */
+int mp_init(struct mp_params *params);
+
+/* Probes the CPU device */
+int mp_init_cpu(struct udevice *cpu, void *unused);
+
+/* Set up additional CPUs */
+int x86_mp_init(void);
+
+#endif /* _X86_MP_H_ */
diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
new file mode 100644
index 0000000..a25f8f0
--- /dev/null
+++ b/arch/x86/include/asm/mpspec.h
@@ -0,0 +1,460 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Adapted from coreboot src/arch/x86/include/arch/smp/mpspec.h
+ */
+
+#ifndef __ASM_MPSPEC_H
+#define __ASM_MPSPEC_H
+
+/*
+ * Structure definitions for SMP machines following the
+ * Intel MultiProcessor Specification 1.4
+ */
+
+#define MPSPEC_V14	4
+
+#define MPF_SIGNATURE	"_MP_"
+
+struct mp_floating_table {
+	char mpf_signature[4];	/* "_MP_" */
+	u32 mpf_physptr;	/* Configuration table address */
+	u8 mpf_length;		/* Our length (paragraphs) */
+	u8 mpf_spec;		/* Specification version */
+	u8 mpf_checksum;	/* Checksum (makes sum 0) */
+	u8 mpf_feature1;	/* Predefined or Unique configuration? */
+	u8 mpf_feature2;	/* Bit7 set for IMCR/PIC */
+	u8 mpf_feature3;	/* Unused (0) */
+	u8 mpf_feature4;	/* Unused (0) */
+	u8 mpf_feature5;	/* Unused (0) */
+};
+
+#define MPC_SIGNATURE	"PCMP"
+
+struct mp_config_table {
+	char mpc_signature[4];	/* "PCMP" */
+	u16 mpc_length;		/* Size of table */
+	u8 mpc_spec;		/* Specification version */
+	u8 mpc_checksum;	/* Checksum (makes sum 0) */
+	char mpc_oem[8];	/* OEM ID */
+	char mpc_product[12];	/* Product ID */
+	u32 mpc_oemptr;		/* OEM table address */
+	u16 mpc_oemsize;	/* OEM table size */
+	u16 mpc_entry_count;	/* Number of entries in the table */
+	u32 mpc_lapic;		/* Local APIC address */
+	u16 mpe_length;		/* Extended table size */
+	u8 mpe_checksum;	/* Extended table checksum */
+	u8 reserved;
+};
+
+/* Base MP configuration table entry types */
+
+enum mp_base_config_entry_type {
+	MP_PROCESSOR,
+	MP_BUS,
+	MP_IOAPIC,
+	MP_INTSRC,
+	MP_LINTSRC
+};
+
+#define MPC_CPU_EN	(1 << 0)
+#define MPC_CPU_BP	(1 << 1)
+
+struct mpc_config_processor {
+	u8 mpc_type;
+	u8 mpc_apicid;
+	u8 mpc_apicver;
+	u8 mpc_cpuflag;
+	u32 mpc_cpusignature;
+	u32 mpc_cpufeature;
+	u32 mpc_reserved[2];
+};
+
+#define BUSTYPE_CBUS	"CBUS  "
+#define BUSTYPE_CBUSII	"CBUSII"
+#define BUSTYPE_EISA	"EISA  "
+#define BUSTYPE_FUTURE	"FUTURE"
+#define BUSTYPE_INTERN	"INTERN"
+#define BUSTYPE_ISA	"ISA   "
+#define BUSTYPE_MBI	"MBI   "
+#define BUSTYPE_MBII	"MBII  "
+#define BUSTYPE_MCA	"MCA   "
+#define BUSTYPE_MPI	"MPI   "
+#define BUSTYPE_MPSA	"MPSA  "
+#define BUSTYPE_NUBUS	"NUBUS "
+#define BUSTYPE_PCI	"PCI   "
+#define BUSTYPE_PCMCIA	"PCMCIA"
+#define BUSTYPE_TC	"TC    "
+#define BUSTYPE_VL	"VL    "
+#define BUSTYPE_VME	"VME   "
+#define BUSTYPE_XPRESS	"XPRESS"
+
+struct mpc_config_bus {
+	u8 mpc_type;
+	u8 mpc_busid;
+	u8 mpc_bustype[6];
+};
+
+#define MPC_APIC_USABLE	(1 << 0)
+
+struct mpc_config_ioapic {
+	u8 mpc_type;
+	u8 mpc_apicid;
+	u8 mpc_apicver;
+	u8 mpc_flags;
+	u32 mpc_apicaddr;
+};
+
+enum mp_irq_source_types {
+	MP_INT,
+	MP_NMI,
+	MP_SMI,
+	MP_EXTINT
+};
+
+#define MP_IRQ_POLARITY_DEFAULT	0x0
+#define MP_IRQ_POLARITY_HIGH	0x1
+#define MP_IRQ_POLARITY_LOW	0x3
+#define MP_IRQ_POLARITY_MASK	0x3
+#define MP_IRQ_TRIGGER_DEFAULT	0x0
+#define MP_IRQ_TRIGGER_EDGE	0x4
+#define MP_IRQ_TRIGGER_LEVEL	0xc
+#define MP_IRQ_TRIGGER_MASK	0xc
+
+#define MP_APIC_ALL		0xff
+
+struct mpc_config_intsrc {
+	u8 mpc_type;
+	u8 mpc_irqtype;
+	u16 mpc_irqflag;
+	u8 mpc_srcbus;
+	u8 mpc_srcbusirq;
+	u8 mpc_dstapic;
+	u8 mpc_dstirq;
+};
+
+struct mpc_config_lintsrc {
+	u8 mpc_type;
+	u8 mpc_irqtype;
+	u16 mpc_irqflag;
+	u8 mpc_srcbusid;
+	u8 mpc_srcbusirq;
+	u8 mpc_destapic;
+	u8 mpc_destlint;
+};
+
+/* Extended MP configuration table entry types */
+
+enum mp_ext_config_entry_type {
+	MPE_SYSTEM_ADDRESS_SPACE = 128,
+	MPE_BUS_HIERARCHY,
+	MPE_COMPAT_ADDRESS_SPACE
+};
+
+struct mp_ext_config {
+	u8 mpe_type;
+	u8 mpe_length;
+};
+
+#define ADDRESS_TYPE_IO		0
+#define ADDRESS_TYPE_MEM	1
+#define ADDRESS_TYPE_PREFETCH	2
+
+struct mp_ext_system_address_space {
+	u8 mpe_type;
+	u8 mpe_length;
+	u8 mpe_busid;
+	u8 mpe_addr_type;
+	u32 mpe_addr_base_low;
+	u32 mpe_addr_base_high;
+	u32 mpe_addr_length_low;
+	u32 mpe_addr_length_high;
+};
+
+#define BUS_SUBTRACTIVE_DECODE	(1 << 0)
+
+struct mp_ext_bus_hierarchy {
+	u8 mpe_type;
+	u8 mpe_length;
+	u8 mpe_busid;
+	u8 mpe_bus_info;
+	u8 mpe_parent_busid;
+	u8 reserved[3];
+};
+
+#define ADDRESS_RANGE_ADD	0
+#define ADDRESS_RANGE_SUBTRACT	1
+
+/*
+ * X100 - X3FF
+ * X500 - X7FF
+ * X900 - XBFF
+ * XD00 - XFFF
+ */
+#define RANGE_LIST_IO_ISA	0
+/*
+ * X3B0 - X3BB
+ * X3C0 - X3DF
+ * X7B0 - X7BB
+ * X7C0 - X7DF
+ * XBB0 - XBBB
+ * XBC0 - XBDF
+ * XFB0 - XFBB
+ * XFC0 - XCDF
+ */
+#define RANGE_LIST_IO_VGA	1
+
+struct mp_ext_compat_address_space {
+	u8 mpe_type;
+	u8 mpe_length;
+	u8 mpe_busid;
+	u8 mpe_addr_modifier;
+	u32 mpe_range_list;
+};
+
+/**
+ * mp_next_mpc_entry() - Compute MP configuration table end to be used as
+ *                       next base table entry start address
+ *
+ * This computes the end address of current MP configuration table, without
+ * counting any extended configuration table entry.
+ *
+ * @mc:		configuration table header address
+ * @return:	configuration table end address
+ */
+static inline ulong mp_next_mpc_entry(struct mp_config_table *mc)
+{
+	return (ulong)mc + mc->mpc_length;
+}
+
+/**
+ * mp_add_mpc_entry() - Add a base MP configuration table entry
+ *
+ * This adds the base MP configuration table entry size with
+ * added base table entry length and increases entry count by 1.
+ *
+ * @mc:		configuration table header address
+ * @length:	length of the added table entry
+ */
+static inline void mp_add_mpc_entry(struct mp_config_table *mc, uint length)
+{
+	mc->mpc_length += length;
+	mc->mpc_entry_count++;
+}
+
+/**
+ * mp_next_mpe_entry() - Compute MP configuration table end to be used as
+ *                       next extended table entry start address
+ *
+ * This computes the end address of current MP configuration table,
+ * including any extended configuration table entry.
+ *
+ * @mc:		configuration table header address
+ * @return:	configuration table end address
+ */
+static inline ulong mp_next_mpe_entry(struct mp_config_table *mc)
+{
+	return (ulong)mc + mc->mpc_length + mc->mpe_length;
+}
+
+/**
+ * mp_add_mpe_entry() - Add an extended MP configuration table entry
+ *
+ * This adds the extended MP configuration table entry size with
+ * added extended table entry length.
+ *
+ * @mc:		configuration table header address
+ * @mpe:	extended table entry base address
+ */
+static inline void mp_add_mpe_entry(struct mp_config_table *mc,
+				    struct mp_ext_config *mpe)
+{
+	mc->mpe_length += mpe->mpe_length;
+}
+
+/**
+ * mp_write_floating_table() - Write the MP floating table
+ *
+ * This writes the MP floating table, and points MP configuration table
+ * to its end address so that MP configuration table follows immediately
+ * after the floating table.
+ *
+ * @mf:		MP floating table base address
+ * @return:	MP configuration table header address
+ */
+struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf);
+
+/**
+ * mp_config_table_init() - Initialize the MP configuration table header
+ *
+ * This populates the MP configuration table header with valid bits.
+ *
+ * @mc:		MP configuration table header address
+ */
+void mp_config_table_init(struct mp_config_table *mc);
+
+/**
+ * mp_write_processor() - Write a processor entry
+ *
+ * This writes a processor entry to the configuration table.
+ *
+ * @mc:		MP configuration table header address
+ */
+void mp_write_processor(struct mp_config_table *mc);
+
+/**
+ * mp_write_bus() - Write a bus entry
+ *
+ * This writes a bus entry to the configuration table.
+ *
+ * @mc:		MP configuration table header address
+ * @id:		bus id
+ * @bustype:	bus type name
+ */
+void mp_write_bus(struct mp_config_table *mc, int id, const char *bustype);
+
+/**
+ * mp_write_ioapic() - Write an I/O APIC entry
+ *
+ * This writes an I/O APIC entry to the configuration table.
+ *
+ * @mc:		MP configuration table header address
+ * @id:		I/O APIC id
+ * @ver:	I/O APIC version
+ * @apicaddr:	I/O APIC address
+ */
+void mp_write_ioapic(struct mp_config_table *mc, int id, int ver, u32 apicaddr);
+
+/**
+ * mp_write_intsrc() - Write an I/O interrupt assignment entry
+ *
+ * This writes an I/O interrupt assignment entry to the configuration table.
+ *
+ * @mc:		MP configuration table header address
+ * @irqtype:	IRQ type (INT/NMI/SMI/ExtINT)
+ * @irqflag:	IRQ flag (level/trigger)
+ * @srcbus:	source bus id where the interrupt comes from
+ * @srcbusirq:	IRQ number mapped on the source bus
+ * @dstapic:	destination I/O APIC id where the interrupt goes to
+ * @dstirq:	destination I/O APIC pin where the interrupt goes to
+ */
+void mp_write_intsrc(struct mp_config_table *mc, int irqtype, int irqflag,
+		     int srcbus, int srcbusirq, int dstapic, int dstirq);
+
+/**
+ * mp_write_pci_intsrc() - Write a PCI interrupt assignment entry
+ *
+ * This writes a PCI interrupt assignment entry to the configuration table.
+ *
+ * @mc:		MP configuration table header address
+ * @irqtype:	IRQ type (INT/NMI/SMI/ExtINT)
+ * @srcbus:	PCI bus number where the interrupt comes from
+ * @dev:	device number on the PCI bus
+ * @pin:	PCI interrupt pin (INT A/B/C/D)
+ * @dstapic:	destination I/O APIC id where the interrupt goes to
+ * @dstirq:	destination I/O APIC pin where the interrupt goes to
+ */
+void mp_write_pci_intsrc(struct mp_config_table *mc, int irqtype,
+			 int srcbus, int dev, int pin, int dstapic, int dstirq);
+
+/**
+ * mp_write_lintsrc() - Write a local interrupt assignment entry
+ *
+ * This writes a local interrupt assignment entry to the configuration table.
+ *
+ * @mc:		MP configuration table header address
+ * @irqtype:	IRQ type (INT/NMI/SMI/ExtINT)
+ * @irqflag:	IRQ flag (level/trigger)
+ * @srcbus:	PCI bus number where the interrupt comes from
+ * @srcbusirq:	IRQ number mapped on the source bus
+ * @dstapic:	destination local APIC id where the interrupt goes to
+ * @destlint:	destination local APIC pin where the interrupt goes to
+ */
+void mp_write_lintsrc(struct mp_config_table *mc, int irqtype, int irqflag,
+		      int srcbus, int srcbusirq, int destapic, int destlint);
+
+
+/**
+ * mp_write_address_space() - Write a system address space entry
+ *
+ * This writes a system address space entry to the configuration table.
+ *
+ * @mc:			MP configuration table header address
+ * @busid:		bus id for the bus where system address space is mapped
+ * @addr_type:		system address type
+ * @addr_base_low:	starting address low
+ * @addr_base_high:	starting address high
+ * @addr_length_low:	address length low
+ * @addr_length_high:	address length high
+ */
+void mp_write_address_space(struct mp_config_table *mc,
+			    int busid, int addr_type,
+			    u32 addr_base_low, u32 addr_base_high,
+			    u32 addr_length_low, u32 addr_length_high);
+
+/**
+ * mp_write_bus_hierarchy() - Write a bus hierarchy descriptor entry
+ *
+ * This writes a bus hierarchy descriptor entry to the configuration table.
+ *
+ * @mc:			MP configuration table header address
+ * @busid:		bus id
+ * @bus_info:		bit0 indicates if the bus is a subtractive decode bus
+ * @parent_busid:	parent bus id
+ */
+void mp_write_bus_hierarchy(struct mp_config_table *mc,
+			    int busid, int bus_info, int parent_busid);
+
+/**
+ * mp_write_compat_address_space() - Write a compat bus address space entry
+ *
+ * This writes a compatibility bus address space modifier entry to the
+ * configuration table.
+ *
+ * @mc:			MP configuration table header address
+ * @busid:		bus id
+ * @addr_modifier:	add or subtract to predefined address range list
+ * @range_list:		list of predefined address space ranges
+ */
+void mp_write_compat_address_space(struct mp_config_table *mc, int busid,
+				   int addr_modifier, u32 range_list);
+
+/**
+ * mptable_finalize() - Finalize the MP table
+ *
+ * This finalizes the MP table by calculating required checksums.
+ *
+ * @mc:		MP configuration table header address
+ * @return:	MP table end address
+ */
+u32 mptable_finalize(struct mp_config_table *mc);
+
+/**
+ * mp_determine_pci_dstirq() - Determine PCI device's int pin on the I/O APIC
+ *
+ * This determines a PCI device's interrupt pin number on the I/O APIC.
+ *
+ * This can be implemented by platform codes to handle specifal cases, which
+ * do not conform to the normal chipset/board design where PIRQ[A-H] are mapped
+ * directly to I/O APIC INTPIN#16-23.
+ *
+ * @bus:	bus number of the pci device
+ * @dev:	device number of the pci device
+ * @func:	function number of the pci device
+ * @pirq:	PIRQ number the PCI device's interrupt pin is routed to
+ * @return:	interrupt pin number on the I/O APIC
+ */
+int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq);
+
+/**
+ * write_mp_table() - Write MP table
+ *
+ * This writes MP table at a given address.
+ *
+ * @addr:	start address to write MP table
+ * @return:	end address of MP table
+ */
+ulong write_mp_table(ulong addr);
+
+#endif /* __ASM_MPSPEC_H */
diff --git a/arch/x86/include/asm/mrc_common.h b/arch/x86/include/asm/mrc_common.h
new file mode 100644
index 0000000..d4e56bf
--- /dev/null
+++ b/arch/x86/include/asm/mrc_common.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __ASM_MRC_COMMON_H
+#define __ASM_MRC_COMMON_H
+
+#include <linux/linkage.h>
+
+/**
+ * mrc_common_init() - Set up SDRAM
+ *
+ * This calls the memory reference code (MRC) to set up SDRAM
+ *
+ * @dev:	Northbridge device
+ * @pei_data:	Platform-specific data required by the MRC
+ * @use_asm_linkage: true if the call to MRC requires asmlinkage, false if it
+ * uses normal U-Boot calling
+ * @return 0 if OK, -ve on error
+ */
+int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage);
+
+asmlinkage void sdram_console_tx_byte(unsigned char byte);
+
+int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap);
+
+void report_memory_config(void);
+
+/**
+ * mrc_add_memory_area() - Add a new usable memory area to our list
+ *
+ * Note: @start and @end must not span the first 4GB boundary
+ *
+ * @info:	Place to store memory info
+ * @start:	Start of this memory area
+ * @end:	End of this memory area + 1
+ */
+int mrc_add_memory_area(struct memory_info *info, uint64_t start,
+			  uint64_t end);
+
+/*
+ * This function looks for the highest region of memory lower than 4GB which
+ * has enough space for U-Boot where U-Boot is aligned on a page boundary.
+ * It overrides the default implementation found elsewhere which simply
+ * picks the end of ram, wherever that may be. The location of the stack,
+ * the relocation address, and how far U-Boot is moved by relocation are
+ * set in the global data structure.
+ */
+ulong mrc_common_board_get_usable_ram_top(ulong total_size);
+
+void mrc_common_dram_init_banksize(void);
+
+#endif
diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h
new file mode 100644
index 0000000..40fda85
--- /dev/null
+++ b/arch/x86/include/asm/mrccache.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Google, Inc
+ * Copyright (C) 2015 Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _ASM_MRCCACHE_H
+#define _ASM_MRCCACHE_H
+
+#define MRC_DATA_ALIGN		0x1000
+#define MRC_DATA_SIGNATURE	(('M' << 0) | ('R' << 8) | \
+				 ('C' << 16) | ('D'<<24))
+
+#define MRC_DATA_HEADER_SIZE	32
+
+struct __packed mrc_data_container {
+	u32	signature;	/* "MRCD" */
+	u32	data_size;	/* Size of the 'data' field */
+	u32	checksum;	/* IP style checksum */
+	u32	reserved;	/* For header alignment */
+	u8	data[0];	/* Variable size, platform/run time dependent */
+};
+
+struct mrc_region {
+	u32	base;
+	u32	offset;
+	u32	length;
+};
+
+struct udevice;
+
+/**
+ * mrccache_find_current() - find the latest MRC cache record
+ *
+ * This searches the MRC cache region looking for the latest record to use
+ * for setting up SDRAM
+ *
+ * @entry:	Position and size of MRC cache in SPI flash
+ * @return pointer to latest record, or NULL if none
+ */
+struct mrc_data_container *mrccache_find_current(struct mrc_region *entry);
+
+/**
+ * mrccache_update() - update the MRC cache with a new record
+ *
+ * This writes a new record to the end of the MRC cache region. If the new
+ * record is the same as the latest record then the write is skipped
+ *
+ * @sf:		SPI flash to write to
+ * @entry:	Position and size of MRC cache in SPI flash
+ * @cur:	Record to write
+ * @return 0 if updated, -EEXIST if the record is the same as the latest
+ * record, -EINVAL if the record is not valid, other error if SPI write failed
+ */
+int mrccache_update(struct udevice *sf, struct mrc_region *entry,
+		    struct mrc_data_container *cur);
+
+/**
+ * mrccache_reserve() - reserve MRC data on the stack
+ *
+ * This copies MRC data pointed by gd->arch.mrc_output to a new place on the
+ * stack with length gd->arch.mrc_output_len, and updates gd->arch.mrc_output
+ * to point to the new place once the migration is done.
+ *
+ * This routine should be called by reserve_arch() before U-Boot is relocated
+ * when MRC cache is enabled.
+ *
+ * @return 0 always
+ */
+int mrccache_reserve(void);
+
+/**
+ * mrccache_get_region() - get MRC region on the SPI flash
+ *
+ * This gets MRC region whose offset and size are described in the device tree
+ * as a subnode to the SPI flash. If a non-NULL device pointer is supplied,
+ * this also probes the SPI flash device and returns its device pointer for
+ * the caller to use later.
+ *
+ * Be careful when calling this routine with a non-NULL device pointer:
+ * - driver model initialization must be complete
+ * - calling in the pre-relocation phase may bring some side effects during
+ *   the SPI flash device probe (eg: for SPI controllers on a PCI bus, it
+ *   triggers PCI bus enumeration during which insufficient memory issue
+ *   might be exposed and it causes subsequent SPI flash probe fails).
+ *
+ * @devp:	Returns pointer to the SPI flash device
+ * @entry:	Position and size of MRC cache in SPI flash
+ * @return 0 if success, -ENOENT if SPI flash node does not exist in the
+ * device tree, -EPERM if MRC region subnode does not exist in the device
+ * tree, -EINVAL if MRC region properties format is incorrect, other error
+ * if SPI flash probe failed.
+ */
+int mrccache_get_region(struct udevice **devp, struct mrc_region *entry);
+
+/**
+ * mrccache_save() - save MRC data to the SPI flash
+ *
+ * This saves MRC data stored previously by gd->arch.mrc_output to a proper
+ * place within the MRC region on the SPI flash.
+ *
+ * @return 0 if saved to SPI flash successfully, other error if failed
+ */
+int mrccache_save(void);
+
+/**
+ * mrccache_spl_save() - Save to the MRC region from SPL
+ *
+ * When SPL is used to set up the memory controller we want to save the MRC
+ * data in SPL to avoid needing to pass it up to U-Boot proper to save. This
+ * function handles that.
+ *
+ * @return 0 if saved to SPI flash successfully, other error if failed
+ */
+int mrccache_spl_save(void);
+
+#endif /* _ASM_MRCCACHE_H */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
new file mode 100644
index 0000000..5bc8b6c
--- /dev/null
+++ b/arch/x86/include/asm/msr-index.h
@@ -0,0 +1,621 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Taken from the linux kernel file of the same name
+ *
+ * (C) Copyright 2012
+ * Graeme Russ, <graeme.russ@gmail.com>
+ */
+
+#ifndef _ASM_X86_MSR_INDEX_H
+#define _ASM_X86_MSR_INDEX_H
+
+/* CPU model specific register (MSR) numbers */
+
+/* x86-64 specific MSRs */
+#define MSR_EFER		0xc0000080 /* extended feature register */
+#define MSR_STAR		0xc0000081 /* legacy mode SYSCALL target */
+#define MSR_LSTAR		0xc0000082 /* long mode SYSCALL target */
+#define MSR_CSTAR		0xc0000083 /* compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK	0xc0000084 /* EFLAGS mask for syscall */
+#define MSR_FS_BASE		0xc0000100 /* 64bit FS base */
+#define MSR_GS_BASE		0xc0000101 /* 64bit GS base */
+#define MSR_KERNEL_GS_BASE	0xc0000102 /* SwapGS GS shadow */
+#define MSR_TSC_AUX		0xc0000103 /* Auxiliary TSC */
+
+/* EFER bits: */
+#define _EFER_SCE		0  /* SYSCALL/SYSRET */
+#define _EFER_LME		8  /* Long mode enable */
+#define _EFER_LMA		10 /* Long mode active (read-only) */
+#define _EFER_NX		11 /* No execute enable */
+#define _EFER_SVME		12 /* Enable virtualization */
+#define _EFER_LMSLE		13 /* Long Mode Segment Limit Enable */
+#define _EFER_FFXSR		14 /* Enable Fast FXSAVE/FXRSTOR */
+
+#define EFER_SCE		(1<<_EFER_SCE)
+#define EFER_LME		(1<<_EFER_LME)
+#define EFER_LMA		(1<<_EFER_LMA)
+#define EFER_NX			(1<<_EFER_NX)
+#define EFER_SVME		(1<<_EFER_SVME)
+#define EFER_LMSLE		(1<<_EFER_LMSLE)
+#define EFER_FFXSR		(1<<_EFER_FFXSR)
+
+/* Intel MSRs. Some also available on other CPUs */
+#define MSR_PIC_MSG_CONTROL		0x2e
+#define  PLATFORM_INFO_SET_TDP		(1 << 29)
+
+#define MSR_MTRR_CAP_MSR		0x0fe
+#define MSR_MTRR_CAP_SMRR		(1 << 11)
+#define MSR_MTRR_CAP_WC			(1 << 10)
+#define MSR_MTRR_CAP_FIX		(1 << 8)
+#define MSR_MTRR_CAP_VCNT		0xff
+
+#define MSR_IA32_PERFCTR0		0x000000c1
+#define MSR_IA32_PERFCTR1		0x000000c2
+#define MSR_FSB_FREQ			0x000000cd
+#define MSR_NHM_PLATFORM_INFO		0x000000ce
+
+#define MSR_NHM_SNB_PKG_CST_CFG_CTL	0x000000e2
+#define NHM_C3_AUTO_DEMOTE		(1UL << 25)
+#define NHM_C1_AUTO_DEMOTE		(1UL << 26)
+#define ATM_LNC_C6_AUTO_DEMOTE		(1UL << 25)
+#define SNB_C1_AUTO_UNDEMOTE		(1UL << 27)
+#define SNB_C3_AUTO_UNDEMOTE		(1UL << 28)
+
+#define MSR_BSEL_CR_OVERCLOCK_CONTROL	0x000000cd
+#define MSR_PLATFORM_INFO		0x000000ce
+#define MSR_PMG_CST_CONFIG_CONTROL	0x000000e2
+#define SINGLE_PCTL			(1 << 11)
+
+#define MSR_MTRRcap			0x000000fe
+#define MSR_IA32_BBL_CR_CTL		0x00000119
+#define MSR_IA32_BBL_CR_CTL3		0x0000011e
+#define MSR_POWER_MISC			0x00000120
+#define ENABLE_ULFM_AUTOCM_MASK		(1 << 2)
+#define ENABLE_INDP_AUTOCM_MASK		(1 << 3)
+
+#define MSR_EMULATE_PM_TIMER		0x121
+#define  EMULATE_DELAY_OFFSET_VALUE	20
+#define  EMULATE_PM_TMR_EN		(1 << 16)
+#define  EMULATE_DELAY_VALUE		0x13
+
+#define MSR_IA32_SYSENTER_CS		0x00000174
+#define MSR_IA32_SYSENTER_ESP		0x00000175
+#define MSR_IA32_SYSENTER_EIP		0x00000176
+
+#define MSR_IA32_MCG_CAP		0x00000179
+#define MSR_IA32_MCG_STATUS		0x0000017a
+#define MSR_IA32_MCG_CTL		0x0000017b
+
+#define MSR_FLEX_RATIO			0x194
+#define  FLEX_RATIO_LOCK		(1 << 20)
+#define  FLEX_RATIO_EN			(1 << 16)
+/* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */
+#define BURST_MODE_DISABLE		(1 << 6)
+
+#define MSR_IA32_MISC_ENABLE		0x000001a0
+
+/* MISC_ENABLE bits: architectural */
+#define MISC_ENABLE_FAST_STRING		BIT_ULL(0)
+#define MISC_ENABLE_TCC			BIT_ULL(1)
+#define MISC_DISABLE_TURBO		BIT_ULL(6)
+#define MISC_ENABLE_EMON		BIT_ULL(7)
+#define MISC_ENABLE_BTS_UNAVAIL		BIT_ULL(11)
+#define MISC_ENABLE_PEBS_UNAVAIL	BIT_ULL(12)
+#define MISC_ENABLE_ENHANCED_SPEEDSTEP	BIT_ULL(16)
+#define MISC_ENABLE_MWAIT		BIT_ULL(18)
+#define MISC_ENABLE_LIMIT_CPUID		BIT_ULL(22)
+#define MISC_ENABLE_XTPR_DISABLE	BIT_ULL(23)
+#define MISC_ENABLE_XD_DISABLE		BIT_ULL(34)
+
+/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
+#define MISC_ENABLE_X87_COMPAT		BIT_ULL(2)
+#define MISC_ENABLE_TM1			BIT_ULL(3)
+#define MISC_ENABLE_SPLIT_LOCK_DISABLE	BIT_ULL(4)
+#define MISC_ENABLE_L3CACHE_DISABLE	BIT_ULL(6)
+#define MISC_ENABLE_SUPPRESS_LOCK	BIT_ULL(8)
+#define MISC_ENABLE_PREFETCH_DISABLE	BIT_ULL(9)
+#define MISC_ENABLE_FERR		BIT_ULL(10)
+#define MISC_ENABLE_FERR_MULTIPLEX	BIT_ULL(10)
+#define MISC_ENABLE_TM2			BIT_ULL(13)
+#define MISC_ENABLE_ADJ_PREF_DISABLE	BIT_ULL(19)
+#define MISC_ENABLE_SPEEDSTEP_LOCK	BIT_ULL(20)
+#define MISC_ENABLE_L1D_CONTEXT		BIT_ULL(24)
+#define MISC_ENABLE_DCU_PREF_DISABLE	BIT_ULL(37)
+#define MISC_ENABLE_TURBO_DISABLE	BIT_ULL(38)
+#define MISC_ENABLE_IP_PREF_DISABLE	BIT_ULL(39)
+
+#define MSR_TEMPERATURE_TARGET		0x1a2
+#define MSR_PREFETCH_CTL		0x1a4
+#define  PREFETCH_L1_DISABLE		(1 << 0)
+#define  PREFETCH_L2_DISABLE		(1 << 2)
+#define MSR_OFFCORE_RSP_0		0x000001a6
+#define MSR_OFFCORE_RSP_1		0x000001a7
+#define MSR_MISC_PWR_MGMT		0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
+#define MSR_TURBO_RATIO_LIMIT		0x000001ad
+
+#define MSR_IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
+#define  ENERGY_POLICY_PERFORMANCE	0
+#define  ENERGY_POLICY_NORMAL		6
+#define  ENERGY_POLICY_POWERSAVE	15
+
+#define MSR_IA32_PACKAGE_THERM_STATUS		0x000001b1
+
+#define PACKAGE_THERM_STATUS_PROCHOT		BIT(0)
+#define PACKAGE_THERM_STATUS_POWER_LIMIT	BIT(10)
+
+#define MSR_IA32_PACKAGE_THERM_INTERRUPT	0x000001b2
+
+#define PACKAGE_THERM_INT_HIGH_ENABLE		BIT(0)
+#define PACKAGE_THERM_INT_LOW_ENABLE		BIT(1)
+#define PACKAGE_THERM_INT_PLN_ENABLE		BIT(24)
+
+#define MSR_LBR_SELECT			0x000001c8
+#define MSR_LBR_TOS			0x000001c9
+#define MSR_IA32_PLATFORM_DCA_CAP	0x1f8
+#define MSR_POWER_CTL			0x000001fc
+#define MSR_LBR_NHM_FROM		0x00000680
+#define MSR_LBR_NHM_TO			0x000006c0
+#define MSR_LBR_CORE_FROM		0x00000040
+#define MSR_LBR_CORE_TO			0x00000060
+
+#define MSR_IA32_PEBS_ENABLE		0x000003f1
+#define MSR_IA32_DS_AREA		0x00000600
+#define MSR_IA32_PERF_CAPABILITIES	0x00000345
+#define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
+
+#define MSR_MTRRfix64K_00000		0x00000250
+#define MSR_MTRRfix16K_80000		0x00000258
+#define MSR_MTRRfix16K_A0000		0x00000259
+#define MSR_MTRRfix4K_C0000		0x00000268
+#define MSR_MTRRfix4K_C8000		0x00000269
+#define MSR_MTRRfix4K_D0000		0x0000026a
+#define MSR_MTRRfix4K_D8000		0x0000026b
+#define MSR_MTRRfix4K_E0000		0x0000026c
+#define MSR_MTRRfix4K_E8000		0x0000026d
+#define MSR_MTRRfix4K_F0000		0x0000026e
+#define MSR_MTRRfix4K_F8000		0x0000026f
+#define MSR_MTRRdefType			0x000002ff
+
+#define MSR_IA32_CR_PAT			0x00000277
+
+#define MSR_IA32_DEBUGCTLMSR		0x000001d9
+#define MSR_IA32_LASTBRANCHFROMIP	0x000001db
+#define MSR_IA32_LASTBRANCHTOIP		0x000001dc
+#define MSR_IA32_LASTINTFROMIP		0x000001dd
+#define MSR_IA32_LASTINTTOIP		0x000001de
+
+/* DEBUGCTLMSR bits (others vary by model): */
+#define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */
+/* single-step on branches */
+#define DEBUGCTLMSR_BTF			(1UL <<  1)
+#define DEBUGCTLMSR_TR			(1UL <<  6)
+#define DEBUGCTLMSR_BTS			(1UL <<  7)
+#define DEBUGCTLMSR_BTINT		(1UL <<  8)
+#define DEBUGCTLMSR_BTS_OFF_OS		(1UL <<  9)
+#define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)
+#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)
+
+#define MSR_IA32_POWER_CTL		0x000001fc
+
+#define MSR_IA32_MC0_CTL		0x00000400
+#define MSR_IA32_MC0_STATUS		0x00000401
+#define MSR_IA32_MC0_ADDR		0x00000402
+#define MSR_IA32_MC0_MISC		0x00000403
+
+/* C-state Residency Counters */
+#define MSR_PKG_C3_RESIDENCY		0x000003f8
+#define MSR_PKG_C6_RESIDENCY		0x000003f9
+#define MSR_PKG_C7_RESIDENCY		0x000003fa
+#define MSR_CORE_C3_RESIDENCY		0x000003fc
+#define MSR_CORE_C6_RESIDENCY		0x000003fd
+#define MSR_CORE_C7_RESIDENCY		0x000003fe
+#define MSR_PKG_C2_RESIDENCY		0x0000060d
+#define MSR_PKG_C8_RESIDENCY		0x00000630
+#define MSR_PKG_C9_RESIDENCY		0x00000631
+#define MSR_PKG_C10_RESIDENCY		0x00000632
+
+/* Run Time Average Power Limiting (RAPL) Interface */
+
+#define MSR_PKG_POWER_SKU_UNIT		0x00000606
+
+#define MSR_C_STATE_LATENCY_CONTROL_0	0x60a
+#define MSR_C_STATE_LATENCY_CONTROL_1	0x60b
+#define MSR_C_STATE_LATENCY_CONTROL_2	0x60c
+#define MSR_C_STATE_LATENCY_CONTROL_3	0x633
+#define MSR_C_STATE_LATENCY_CONTROL_4	0x634
+#define MSR_C_STATE_LATENCY_CONTROL_5	0x635
+#define  IRTL_VALID			(1 << 15)
+#define  IRTL_1_NS			(0 << 10)
+#define  IRTL_32_NS			(1 << 10)
+#define  IRTL_1024_NS			(2 << 10)
+#define  IRTL_32768_NS			(3 << 10)
+#define  IRTL_1048576_NS		(4 << 10)
+#define  IRTL_33554432_NS		(5 << 10)
+#define  IRTL_RESPONSE_MASK		(0x3ff)
+
+#define MSR_PKG_POWER_LIMIT		0x00000610
+/* long duration in low dword, short duration in high dword */
+#define  PKG_POWER_LIMIT_MASK		0x7fff
+#define  PKG_POWER_LIMIT_EN		(1 << 15)
+#define  PKG_POWER_LIMIT_CLAMP		(1 << 16)
+#define  PKG_POWER_LIMIT_TIME_SHIFT	17
+#define  PKG_POWER_LIMIT_TIME_MASK	0x7f
+
+#define MSR_PKG_ENERGY_STATUS		0x00000611
+#define MSR_PKG_PERF_STATUS		0x00000613
+#define MSR_PKG_POWER_INFO		0x00000614
+
+#define MSR_DRAM_POWER_LIMIT		0x00000618
+#define MSR_DRAM_ENERGY_STATUS		0x00000619
+#define MSR_DRAM_PERF_STATUS		0x0000061b
+#define MSR_DRAM_POWER_INFO		0x0000061c
+
+#define MSR_PP0_POWER_LIMIT		0x00000638
+#define MSR_PP0_ENERGY_STATUS		0x00000639
+#define MSR_PP0_POLICY			0x0000063a
+#define MSR_PP0_PERF_STATUS		0x0000063b
+
+#define MSR_PP1_POWER_LIMIT		0x00000640
+#define MSR_PP1_ENERGY_STATUS		0x00000641
+#define MSR_PP1_POLICY			0x00000642
+#define MSR_CONFIG_TDP_NOMINAL		0x00000648
+#define MSR_TURBO_ACTIVATION_RATIO	0x0000064c
+#define MSR_CORE_C1_RES			0x00000660
+#define MSR_IACORE_RATIOS		0x0000066a
+#define MSR_IACORE_TURBO_RATIOS		0x0000066c
+#define MSR_IACORE_VIDS			0x0000066b
+#define MSR_IACORE_TURBO_VIDS		0x0000066d
+#define MSR_PKG_TURBO_CFG1		0x00000670
+#define MSR_CPU_TURBO_WKLD_CFG1		0x00000671
+#define MSR_CPU_TURBO_WKLD_CFG2		0x00000672
+#define MSR_CPU_THERM_CFG1		0x00000673
+#define MSR_CPU_THERM_CFG2		0x00000674
+#define MSR_CPU_THERM_SENS_CFG		0x00000675
+
+#define MSR_AMD64_MC0_MASK		0xc0010044
+
+#define MSR_IA32_MCx_CTL(x)		(MSR_IA32_MC0_CTL + 4*(x))
+#define MSR_IA32_MCx_STATUS(x)		(MSR_IA32_MC0_STATUS + 4*(x))
+#define MSR_IA32_MCx_ADDR(x)		(MSR_IA32_MC0_ADDR + 4*(x))
+#define MSR_IA32_MCx_MISC(x)		(MSR_IA32_MC0_MISC + 4*(x))
+
+#define MSR_AMD64_MCx_MASK(x)		(MSR_AMD64_MC0_MASK + (x))
+
+/* These are consecutive and not in the normal 4er MCE bank block */
+#define MSR_IA32_MC0_CTL2		0x00000280
+#define MSR_IA32_MCx_CTL2(x)		(MSR_IA32_MC0_CTL2 + (x))
+
+#define MSR_P6_PERFCTR0			0x000000c1
+#define MSR_P6_PERFCTR1			0x000000c2
+#define MSR_P6_EVNTSEL0			0x00000186
+#define MSR_P6_EVNTSEL1			0x00000187
+
+#define MSR_KNC_PERFCTR0               0x00000020
+#define MSR_KNC_PERFCTR1               0x00000021
+#define MSR_KNC_EVNTSEL0               0x00000028
+#define MSR_KNC_EVNTSEL1               0x00000029
+
+/* Alternative perfctr range with full access. */
+#define MSR_IA32_PMC0			0x000004c1
+
+/* AMD64 MSRs. Not complete. See the architecture manual for a more
+   complete list. */
+
+#define MSR_AMD64_PATCH_LEVEL		0x0000008b
+#define MSR_AMD64_TSC_RATIO		0xc0000104
+#define MSR_AMD64_NB_CFG		0xc001001f
+#define MSR_AMD64_PATCH_LOADER		0xc0010020
+#define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140
+#define MSR_AMD64_OSVW_STATUS		0xc0010141
+#define MSR_AMD64_LS_CFG		0xc0011020
+#define MSR_AMD64_DC_CFG		0xc0011022
+#define MSR_AMD64_BU_CFG2		0xc001102a
+#define MSR_AMD64_IBSFETCHCTL		0xc0011030
+#define MSR_AMD64_IBSFETCHLINAD		0xc0011031
+#define MSR_AMD64_IBSFETCHPHYSAD	0xc0011032
+#define MSR_AMD64_IBSFETCH_REG_COUNT	3
+#define MSR_AMD64_IBSFETCH_REG_MASK	((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
+#define MSR_AMD64_IBSOPCTL		0xc0011033
+#define MSR_AMD64_IBSOPRIP		0xc0011034
+#define MSR_AMD64_IBSOPDATA		0xc0011035
+#define MSR_AMD64_IBSOPDATA2		0xc0011036
+#define MSR_AMD64_IBSOPDATA3		0xc0011037
+#define MSR_AMD64_IBSDCLINAD		0xc0011038
+#define MSR_AMD64_IBSDCPHYSAD		0xc0011039
+#define MSR_AMD64_IBSOP_REG_COUNT	7
+#define MSR_AMD64_IBSOP_REG_MASK	((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
+#define MSR_AMD64_IBSCTL		0xc001103a
+#define MSR_AMD64_IBSBRTARGET		0xc001103b
+#define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
+
+/* Fam 16h MSRs */
+#define MSR_F16H_L2I_PERF_CTL		0xc0010230
+#define MSR_F16H_L2I_PERF_CTR		0xc0010231
+
+/* Fam 15h MSRs */
+#define MSR_F15H_PERF_CTL		0xc0010200
+#define MSR_F15H_PERF_CTR		0xc0010201
+#define MSR_F15H_NB_PERF_CTL		0xc0010240
+#define MSR_F15H_NB_PERF_CTR		0xc0010241
+
+/* Fam 10h MSRs */
+#define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058
+#define FAM10H_MMIO_CONF_ENABLE		(1<<0)
+#define FAM10H_MMIO_CONF_BUSRANGE_MASK	0xf
+#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
+#define FAM10H_MMIO_CONF_BASE_MASK	0xfffffffULL
+#define FAM10H_MMIO_CONF_BASE_SHIFT	20
+#define MSR_FAM10H_NODE_ID		0xc001100c
+
+/* K8 MSRs */
+#define MSR_K8_TOP_MEM1			0xc001001a
+#define MSR_K8_TOP_MEM2			0xc001001d
+#define MSR_K8_SYSCFG			0xc0010010
+#define MSR_K8_INT_PENDING_MSG		0xc0010055
+/* C1E active bits in int pending message */
+#define K8_INTP_C1E_ACTIVE_MASK		0x18000000
+#define MSR_K8_TSEG_ADDR		0xc0010112
+#define K8_MTRRFIXRANGE_DRAM_ENABLE	0x00040000 /* MtrrFixDramEn bit    */
+#define K8_MTRRFIXRANGE_DRAM_MODIFY	0x00080000 /* MtrrFixDramModEn bit */
+#define K8_MTRR_RDMEM_WRMEM_MASK	0x18181818 /* Mask: RdMem|WrMem    */
+
+/* K7 MSRs */
+#define MSR_K7_EVNTSEL0			0xc0010000
+#define MSR_K7_PERFCTR0			0xc0010004
+#define MSR_K7_EVNTSEL1			0xc0010001
+#define MSR_K7_PERFCTR1			0xc0010005
+#define MSR_K7_EVNTSEL2			0xc0010002
+#define MSR_K7_PERFCTR2			0xc0010006
+#define MSR_K7_EVNTSEL3			0xc0010003
+#define MSR_K7_PERFCTR3			0xc0010007
+#define MSR_K7_CLK_CTL			0xc001001b
+#define MSR_K7_HWCR			0xc0010015
+#define MSR_K7_FID_VID_CTL		0xc0010041
+#define MSR_K7_FID_VID_STATUS		0xc0010042
+
+/* K6 MSRs */
+#define MSR_K6_WHCR			0xc0000082
+#define MSR_K6_UWCCR			0xc0000085
+#define MSR_K6_EPMR			0xc0000086
+#define MSR_K6_PSOR			0xc0000087
+#define MSR_K6_PFIR			0xc0000088
+
+/* Centaur-Hauls/IDT defined MSRs. */
+#define MSR_IDT_FCR1			0x00000107
+#define MSR_IDT_FCR2			0x00000108
+#define MSR_IDT_FCR3			0x00000109
+#define MSR_IDT_FCR4			0x0000010a
+
+#define MSR_IDT_MCR0			0x00000110
+#define MSR_IDT_MCR1			0x00000111
+#define MSR_IDT_MCR2			0x00000112
+#define MSR_IDT_MCR3			0x00000113
+#define MSR_IDT_MCR4			0x00000114
+#define MSR_IDT_MCR5			0x00000115
+#define MSR_IDT_MCR6			0x00000116
+#define MSR_IDT_MCR7			0x00000117
+#define MSR_IDT_MCR_CTRL		0x00000120
+
+/* VIA Cyrix defined MSRs*/
+#define MSR_VIA_FCR			0x00001107
+#define MSR_VIA_LONGHAUL		0x0000110a
+#define MSR_VIA_RNG			0x0000110b
+#define MSR_VIA_BCR2			0x00001147
+
+/* Transmeta defined MSRs */
+#define MSR_TMTA_LONGRUN_CTRL		0x80868010
+#define MSR_TMTA_LONGRUN_FLAGS		0x80868011
+#define MSR_TMTA_LRTI_READOUT		0x80868018
+#define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a
+
+/* Intel defined MSRs. */
+#define MSR_IA32_P5_MC_ADDR		0x00000000
+#define MSR_IA32_P5_MC_TYPE		0x00000001
+#define MSR_IA32_TSC			0x00000010
+#define MSR_IA32_PLATFORM_ID		0x00000017
+#define MSR_IA32_EBL_CR_POWERON		0x0000002a
+#define MSR_EBC_FREQUENCY_ID		0x0000002c
+#define MSR_SMI_COUNT			0x00000034
+#define MSR_IA32_FEATURE_CONTROL        0x0000003a
+#define MSR_IA32_TSC_ADJUST             0x0000003b
+
+#define FEATURE_CONTROL_LOCKED				(1<<0)
+#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)
+#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)
+
+#define MSR_IA32_APICBASE		0x0000001b
+#define MSR_IA32_APICBASE_BSP		(1<<8)
+#define MSR_IA32_APICBASE_ENABLE	(1<<11)
+#define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
+
+#define MSR_IA32_TSCDEADLINE		0x000006e0
+
+#define MSR_IA32_UCODE_WRITE		0x00000079
+#define MSR_IA32_UCODE_REV		0x0000008b
+
+#define MSR_IA32_PERF_STATUS		0x00000198
+#define MSR_IA32_PERF_CTL		0x00000199
+#define MSR_AMD_PSTATE_DEF_BASE		0xc0010064
+#define MSR_AMD_PERF_STATUS		0xc0010063
+#define MSR_AMD_PERF_CTL		0xc0010062
+
+#define MSR_PMG_CST_CONFIG_CTL		0x000000e2
+#define MSR_PMG_IO_CAPTURE_ADR		0x000000e4
+#define MSR_IA32_MPERF			0x000000e7
+#define MSR_IA32_APERF			0x000000e8
+
+#define MSR_IA32_THERM_CONTROL		0x0000019a
+#define MSR_IA32_THERM_INTERRUPT	0x0000019b
+
+#define THERM_INT_HIGH_ENABLE		(1 << 0)
+#define THERM_INT_LOW_ENABLE		(1 << 1)
+#define THERM_INT_PLN_ENABLE		(1 << 24)
+
+#define MSR_IA32_THERM_STATUS		0x0000019c
+
+#define THERM_STATUS_PROCHOT		(1 << 0)
+#define THERM_STATUS_POWER_LIMIT	(1 << 10)
+
+#define MSR_THERM2_CTL			0x0000019d
+
+#define MSR_THERM2_CTL_TM_SELECT	(1ULL << 16)
+
+#define MSR_IA32_TSC_DEADLINE		0x000006E0
+
+/* P4/Xeon+ specific */
+#define MSR_IA32_MCG_EAX		0x00000180
+#define MSR_IA32_MCG_EBX		0x00000181
+#define MSR_IA32_MCG_ECX		0x00000182
+#define MSR_IA32_MCG_EDX		0x00000183
+#define MSR_IA32_MCG_ESI		0x00000184
+#define MSR_IA32_MCG_EDI		0x00000185
+#define MSR_IA32_MCG_EBP		0x00000186
+#define MSR_IA32_MCG_ESP		0x00000187
+#define MSR_IA32_MCG_EFLAGS		0x00000188
+#define MSR_IA32_MCG_EIP		0x00000189
+#define MSR_IA32_MCG_RESERVED		0x0000018a
+
+/* Pentium IV performance counter MSRs */
+#define MSR_P4_BPU_PERFCTR0		0x00000300
+#define MSR_P4_BPU_PERFCTR1		0x00000301
+#define MSR_P4_BPU_PERFCTR2		0x00000302
+#define MSR_P4_BPU_PERFCTR3		0x00000303
+#define MSR_P4_MS_PERFCTR0		0x00000304
+#define MSR_P4_MS_PERFCTR1		0x00000305
+#define MSR_P4_MS_PERFCTR2		0x00000306
+#define MSR_P4_MS_PERFCTR3		0x00000307
+#define MSR_P4_FLAME_PERFCTR0		0x00000308
+#define MSR_P4_FLAME_PERFCTR1		0x00000309
+#define MSR_P4_FLAME_PERFCTR2		0x0000030a
+#define MSR_P4_FLAME_PERFCTR3		0x0000030b
+#define MSR_P4_IQ_PERFCTR0		0x0000030c
+#define MSR_P4_IQ_PERFCTR1		0x0000030d
+#define MSR_P4_IQ_PERFCTR2		0x0000030e
+#define MSR_P4_IQ_PERFCTR3		0x0000030f
+#define MSR_P4_IQ_PERFCTR4		0x00000310
+#define MSR_P4_IQ_PERFCTR5		0x00000311
+#define MSR_P4_BPU_CCCR0		0x00000360
+#define MSR_P4_BPU_CCCR1		0x00000361
+#define MSR_P4_BPU_CCCR2		0x00000362
+#define MSR_P4_BPU_CCCR3		0x00000363
+#define MSR_P4_MS_CCCR0			0x00000364
+#define MSR_P4_MS_CCCR1			0x00000365
+#define MSR_P4_MS_CCCR2			0x00000366
+#define MSR_P4_MS_CCCR3			0x00000367
+#define MSR_P4_FLAME_CCCR0		0x00000368
+#define MSR_P4_FLAME_CCCR1		0x00000369
+#define MSR_P4_FLAME_CCCR2		0x0000036a
+#define MSR_P4_FLAME_CCCR3		0x0000036b
+#define MSR_P4_IQ_CCCR0			0x0000036c
+#define MSR_P4_IQ_CCCR1			0x0000036d
+#define MSR_P4_IQ_CCCR2			0x0000036e
+#define MSR_P4_IQ_CCCR3			0x0000036f
+#define MSR_P4_IQ_CCCR4			0x00000370
+#define MSR_P4_IQ_CCCR5			0x00000371
+#define MSR_P4_ALF_ESCR0		0x000003ca
+#define MSR_P4_ALF_ESCR1		0x000003cb
+#define MSR_P4_BPU_ESCR0		0x000003b2
+#define MSR_P4_BPU_ESCR1		0x000003b3
+#define MSR_P4_BSU_ESCR0		0x000003a0
+#define MSR_P4_BSU_ESCR1		0x000003a1
+#define MSR_P4_CRU_ESCR0		0x000003b8
+#define MSR_P4_CRU_ESCR1		0x000003b9
+#define MSR_P4_CRU_ESCR2		0x000003cc
+#define MSR_P4_CRU_ESCR3		0x000003cd
+#define MSR_P4_CRU_ESCR4		0x000003e0
+#define MSR_P4_CRU_ESCR5		0x000003e1
+#define MSR_P4_DAC_ESCR0		0x000003a8
+#define MSR_P4_DAC_ESCR1		0x000003a9
+#define MSR_P4_FIRM_ESCR0		0x000003a4
+#define MSR_P4_FIRM_ESCR1		0x000003a5
+#define MSR_P4_FLAME_ESCR0		0x000003a6
+#define MSR_P4_FLAME_ESCR1		0x000003a7
+#define MSR_P4_FSB_ESCR0		0x000003a2
+#define MSR_P4_FSB_ESCR1		0x000003a3
+#define MSR_P4_IQ_ESCR0			0x000003ba
+#define MSR_P4_IQ_ESCR1			0x000003bb
+#define MSR_P4_IS_ESCR0			0x000003b4
+#define MSR_P4_IS_ESCR1			0x000003b5
+#define MSR_P4_ITLB_ESCR0		0x000003b6
+#define MSR_P4_ITLB_ESCR1		0x000003b7
+#define MSR_P4_IX_ESCR0			0x000003c8
+#define MSR_P4_IX_ESCR1			0x000003c9
+#define MSR_P4_MOB_ESCR0		0x000003aa
+#define MSR_P4_MOB_ESCR1		0x000003ab
+#define MSR_P4_MS_ESCR0			0x000003c0
+#define MSR_P4_MS_ESCR1			0x000003c1
+#define MSR_P4_PMH_ESCR0		0x000003ac
+#define MSR_P4_PMH_ESCR1		0x000003ad
+#define MSR_P4_RAT_ESCR0		0x000003bc
+#define MSR_P4_RAT_ESCR1		0x000003bd
+#define MSR_P4_SAAT_ESCR0		0x000003ae
+#define MSR_P4_SAAT_ESCR1		0x000003af
+#define MSR_P4_SSU_ESCR0		0x000003be
+#define MSR_P4_SSU_ESCR1		0x000003bf /* guess: not in manual */
+
+#define MSR_P4_TBPU_ESCR0		0x000003c2
+#define MSR_P4_TBPU_ESCR1		0x000003c3
+#define MSR_P4_TC_ESCR0			0x000003c4
+#define MSR_P4_TC_ESCR1			0x000003c5
+#define MSR_P4_U2L_ESCR0		0x000003b0
+#define MSR_P4_U2L_ESCR1		0x000003b1
+
+#define MSR_P4_PEBS_MATRIX_VERT		0x000003f2
+
+/* Intel Core-based CPU performance counters */
+#define MSR_CORE_PERF_FIXED_CTR0	0x00000309
+#define MSR_CORE_PERF_FIXED_CTR1	0x0000030a
+#define MSR_CORE_PERF_FIXED_CTR2	0x0000030b
+#define MSR_CORE_PERF_FIXED_CTR_CTRL	0x0000038d
+#define MSR_CORE_PERF_GLOBAL_STATUS	0x0000038e
+#define MSR_CORE_PERF_GLOBAL_CTRL	0x0000038f
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x00000390
+
+/* Geode defined MSRs */
+#define MSR_GEODE_BUSCONT_CONF0		0x00001900
+
+/* Intel VT MSRs */
+#define MSR_IA32_VMX_BASIC              0x00000480
+#define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
+#define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
+#define MSR_IA32_VMX_EXIT_CTLS          0x00000483
+#define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
+#define MSR_IA32_VMX_MISC               0x00000485
+#define MSR_IA32_VMX_CR0_FIXED0         0x00000486
+#define MSR_IA32_VMX_CR0_FIXED1         0x00000487
+#define MSR_IA32_VMX_CR4_FIXED0         0x00000488
+#define MSR_IA32_VMX_CR4_FIXED1         0x00000489
+#define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
+#define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
+#define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
+#define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
+#define MSR_IA32_VMX_VMFUNC             0x00000491
+
+#define MSR_IA32_PQR_ASSOC		0xc8f
+/* MSR bits 33:32 encode slot number 0-3 */
+#define MSR_IA32_PQR_ASSOC_MASK		(1 << 0 | 1 << 1)
+
+#define MSR_L2_QOS_MASK(reg)		(0xd10 + (reg))
+
+/* VMX_BASIC bits and bitmasks */
+#define VMX_BASIC_VMCS_SIZE_SHIFT	32
+#define VMX_BASIC_64		0x0001000000000000LLU
+#define VMX_BASIC_MEM_TYPE_SHIFT	50
+#define VMX_BASIC_MEM_TYPE_MASK	0x003c000000000000LLU
+#define VMX_BASIC_MEM_TYPE_WB	6LLU
+#define VMX_BASIC_INOUT		0x0040000000000000LLU
+
+/* MSR_IA32_VMX_MISC bits */
+#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
+#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE   0x1F
+/* AMD-V MSRs */
+
+#define MSR_VM_CR                       0xc0010114
+#define MSR_VM_IGNNE                    0xc0010115
+#define MSR_VM_HSAVE_PA                 0xc0010117
+
+#endif /* _ASM_X86_MSR_INDEX_H */
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
new file mode 100644
index 0000000..3e613de
--- /dev/null
+++ b/arch/x86/include/asm/msr.h
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Taken from the linux kernel file of the same name
+ *
+ * (C) Copyright 2012
+ * Graeme Russ, <graeme.russ@gmail.com>
+ */
+
+#ifndef _ASM_X86_MSR_H
+#define _ASM_X86_MSR_H
+
+#include <asm/msr-index.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+#define X86_IOC_RDMSR_REGS	_IOWR('c', 0xA0, __u32[8])
+#define X86_IOC_WRMSR_REGS	_IOWR('c', 0xA1, __u32[8])
+
+#ifdef __KERNEL__
+
+#include <linux/errno.h>
+
+struct msr {
+	union {
+		struct {
+			u32 l;
+			u32 h;
+		};
+		u64 q;
+	};
+};
+
+struct msr_info {
+	u32 msr_no;
+	struct msr reg;
+	struct msr *msrs;
+	int err;
+};
+
+struct msr_regs_info {
+	u32 *regs;
+	int err;
+};
+
+static inline unsigned long long native_read_tscp(unsigned int *aux)
+{
+	unsigned long low, high;
+	asm volatile(".byte 0x0f,0x01,0xf9"
+		     : "=a" (low), "=d" (high), "=c" (*aux));
+	return low | ((u64)high << 32);
+}
+
+/*
+ * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
+ * constraint has different meanings. For i386, "A" means exactly
+ * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead,
+ * it means rax *or* rdx.
+ */
+#ifdef CONFIG_X86_64
+#define DECLARE_ARGS(val, low, high)	unsigned low, high
+#define EAX_EDX_VAL(val, low, high)	((low) | ((u64)(high) << 32))
+#define EAX_EDX_ARGS(val, low, high)	"a" (low), "d" (high)
+#define EAX_EDX_RET(val, low, high)	"=a" (low), "=d" (high)
+#else
+#define DECLARE_ARGS(val, low, high)	unsigned long long val
+#define EAX_EDX_VAL(val, low, high)	(val)
+#define EAX_EDX_ARGS(val, low, high)	"A" (val)
+#define EAX_EDX_RET(val, low, high)	"=A" (val)
+#endif
+
+static inline __attribute__((no_instrument_function))
+	unsigned long long native_read_msr(unsigned int msr)
+{
+	DECLARE_ARGS(val, low, high);
+
+	asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
+	return EAX_EDX_VAL(val, low, high);
+}
+
+static inline void native_write_msr(unsigned int msr,
+				    unsigned low, unsigned high)
+{
+	asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory");
+}
+
+extern unsigned long long native_read_tsc(void);
+
+extern int native_rdmsr_safe_regs(u32 regs[8]);
+extern int native_wrmsr_safe_regs(u32 regs[8]);
+
+static inline unsigned long long native_read_pmc(int counter)
+{
+	DECLARE_ARGS(val, low, high);
+
+	asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
+	return EAX_EDX_VAL(val, low, high);
+}
+
+#ifdef CONFIG_PARAVIRT
+#include <asm/paravirt.h>
+#else
+#include <errno.h>
+/*
+ * Access to machine-specific registers (available on 586 and better only)
+ * Note: the rd* operations modify the parameters directly (without using
+ * pointer indirection), this allows gcc to optimize better
+ */
+
+#define rdmsr(msr, val1, val2)					\
+do {								\
+	u64 __val = native_read_msr((msr));			\
+	(void)((val1) = (u32)__val);				\
+	(void)((val2) = (u32)(__val >> 32));			\
+} while (0)
+
+static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
+{
+	native_write_msr(msr, low, high);
+}
+
+#define rdmsrl(msr, val)			\
+	((val) = native_read_msr((msr)))
+
+#define wrmsrl(msr, val)						\
+	native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
+
+static inline void msr_clrsetbits_64(unsigned msr, u64 clear, u64 set)
+{
+	u64 val;
+
+	val = native_read_msr(msr);
+	val &= ~clear;
+	val |= set;
+	wrmsrl(msr, val);
+}
+
+static inline void msr_setbits_64(unsigned msr, u64 set)
+{
+	u64 val;
+
+	val = native_read_msr(msr);
+	val |= set;
+	wrmsrl(msr, val);
+}
+
+static inline void msr_clrbits_64(unsigned msr, u64 clear)
+{
+	u64 val;
+
+	val = native_read_msr(msr);
+	val &= ~clear;
+	wrmsrl(msr, val);
+}
+
+/* rdmsr with exception handling */
+#define rdmsr_safe(msr, p1, p2)					\
+({								\
+	int __err;						\
+	u64 __val = native_read_msr_safe((msr), &__err);	\
+	(*p1) = (u32)__val;					\
+	(*p2) = (u32)(__val >> 32);				\
+	__err;							\
+})
+
+static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
+{
+	u32 gprs[8] = { 0 };
+	int err;
+
+	gprs[1] = msr;
+	gprs[7] = 0x9c5a203a;
+
+	err = native_rdmsr_safe_regs(gprs);
+
+	*p = gprs[0] | ((u64)gprs[2] << 32);
+
+	return err;
+}
+
+static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
+{
+	u32 gprs[8] = { 0 };
+
+	gprs[0] = (u32)val;
+	gprs[1] = msr;
+	gprs[2] = val >> 32;
+	gprs[7] = 0x9c5a203a;
+
+	return native_wrmsr_safe_regs(gprs);
+}
+
+static inline int rdmsr_safe_regs(u32 regs[8])
+{
+	return native_rdmsr_safe_regs(regs);
+}
+
+static inline int wrmsr_safe_regs(u32 regs[8])
+{
+	return native_wrmsr_safe_regs(regs);
+}
+
+typedef struct msr_t {
+	uint32_t lo;
+	uint32_t hi;
+} msr_t;
+
+static inline struct msr_t msr_read(unsigned msr_num)
+{
+	struct msr_t msr;
+
+	rdmsr(msr_num, msr.lo, msr.hi);
+
+	return msr;
+}
+
+static inline void msr_write(unsigned msr_num, msr_t msr)
+{
+	wrmsr(msr_num, msr.lo, msr.hi);
+}
+
+#define rdtscl(low)						\
+	((low) = (u32)__native_read_tsc())
+
+#define rdtscll(val)						\
+	((val) = __native_read_tsc())
+
+#define rdpmc(counter, low, high)			\
+do {							\
+	u64 _l = native_read_pmc((counter));		\
+	(low)  = (u32)_l;				\
+	(high) = (u32)(_l >> 32);			\
+} while (0)
+
+#define rdtscp(low, high, aux)					\
+do {                                                            \
+	unsigned long long _val = native_read_tscp(&(aux));     \
+	(low) = (u32)_val;                                      \
+	(high) = (u32)(_val >> 32);                             \
+} while (0)
+
+#define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
+
+#endif	/* !CONFIG_PARAVIRT */
+
+
+#define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val),		\
+					     (u32)((val) >> 32))
+
+#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))
+
+#define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0)
+
+struct msr *msrs_alloc(void);
+void msrs_free(struct msr *msrs);
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_X86_MSR_H */
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
new file mode 100644
index 0000000..6726172
--- /dev/null
+++ b/arch/x86/include/asm/mtrr.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot file of the same name
+ */
+
+#ifndef _ASM_MTRR_H
+#define _ASM_MTRR_H
+
+/* MTRR region types */
+#define MTRR_TYPE_UNCACHEABLE	0
+#define MTRR_TYPE_WRCOMB	1
+#define MTRR_TYPE_WRTHROUGH	4
+#define MTRR_TYPE_WRPROT	5
+#define MTRR_TYPE_WRBACK	6
+
+#define MTRR_TYPE_COUNT		7
+
+#define MTRR_CAP_MSR		0x0fe
+#define MTRR_DEF_TYPE_MSR	0x2ff
+
+#define MTRR_CAP_SMRR		(1 << 11)
+#define MTRR_CAP_WC		(1 << 10)
+#define MTRR_CAP_FIX		(1 << 8)
+#define MTRR_CAP_VCNT_MASK	0xff
+
+#define MTRR_DEF_TYPE_MASK	0xff
+#define MTRR_DEF_TYPE_EN	(1 << 11)
+#define MTRR_DEF_TYPE_FIX_EN	(1 << 10)
+
+#define MTRR_PHYS_BASE_MSR(reg)	(0x200 + 2 * (reg))
+#define MTRR_PHYS_MASK_MSR(reg)	(0x200 + 2 * (reg) + 1)
+
+#define MTRR_PHYS_MASK_VALID	(1 << 11)
+
+#define MTRR_BASE_TYPE_MASK	0x7
+
+/* Number of MTRRs supported */
+#define MTRR_COUNT		8
+
+#define NUM_FIXED_MTRRS		11
+#define RANGES_PER_FIXED_MTRR	8
+#define NUM_FIXED_RANGES	(NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR)
+
+#define MTRR_FIX_64K_00000_MSR	0x250
+#define MTRR_FIX_16K_80000_MSR	0x258
+#define MTRR_FIX_16K_A0000_MSR	0x259
+#define MTRR_FIX_4K_C0000_MSR	0x268
+#define MTRR_FIX_4K_C8000_MSR	0x269
+#define MTRR_FIX_4K_D0000_MSR	0x26a
+#define MTRR_FIX_4K_D8000_MSR	0x26b
+#define MTRR_FIX_4K_E0000_MSR	0x26c
+#define MTRR_FIX_4K_E8000_MSR	0x26d
+#define MTRR_FIX_4K_F0000_MSR	0x26e
+#define MTRR_FIX_4K_F8000_MSR	0x26f
+
+#define MTRR_FIX_TYPE(t)	((t << 24) | (t << 16) | (t << 8) | t)
+
+#if !defined(__ASSEMBLER__)
+
+/**
+ * Information about the previous MTRR state, set up by mtrr_open()
+ *
+ * @deftype:		Previous value of MTRR_DEF_TYPE_MSR
+ * @enable_cache:	true if cache was enabled
+ */
+struct mtrr_state {
+	uint64_t deftype;
+	bool enable_cache;
+};
+
+/**
+ * mtrr_open() - Prepare to adjust MTRRs
+ *
+ * Use mtrr_open() passing in a structure - this function will init it. Then
+ * when done, pass the same structure to mtrr_close() to re-enable MTRRs and
+ * possibly the cache.
+ *
+ * @state:	Empty structure to pass in to hold settings
+ * @do_caches:	true to disable caches before opening
+ */
+void mtrr_open(struct mtrr_state *state, bool do_caches);
+
+/**
+ * mtrr_open() - Clean up after adjusting MTRRs, and enable them
+ *
+ * This uses the structure containing information returned from mtrr_open().
+ *
+ * @state:	Structure from mtrr_open()
+ * @state:	true to restore cache state to that before mtrr_open()
+ */
+void mtrr_close(struct mtrr_state *state, bool do_caches);
+
+/**
+ * mtrr_add_request() - Add a new MTRR request
+ *
+ * This adds a request for a memory region to be set up in a particular way.
+ *
+ * @type:	Requested type (MTRR_TYPE_)
+ * @start:	Start address
+ * @size:	Size
+ *
+ * @return:	0 on success, non-zero on failure
+ */
+int mtrr_add_request(int type, uint64_t start, uint64_t size);
+
+/**
+ * mtrr_commit() - set up the MTRR registers based on current requests
+ *
+ * This sets up MTRRs for the available DRAM and the requests received so far.
+ * It must be called with caches disabled.
+ *
+ * @do_caches:	true if caches are currently on
+ *
+ * @return:	0 on success, non-zero on failure
+ */
+int mtrr_commit(bool do_caches);
+
+/**
+ * mtrr_set_next_var() - set up a variable MTRR
+ *
+ * This finds the first free variable MTRR and sets to the given area
+ *
+ * @type:	Requested type (MTRR_TYPE_)
+ * @start:	Start address
+ * @size:	Size
+ * @return 0 on success, -ENOSPC if there are no more MTRRs
+ */
+int mtrr_set_next_var(uint type, uint64_t base, uint64_t size);
+
+#endif
+
+#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
+# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
+#endif
+
+#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0)
+# error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
+#endif
+
+#define CACHE_ROM_BASE	(((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)
+
+#endif
diff --git a/arch/x86/include/asm/pch_common.h b/arch/x86/include/asm/pch_common.h
new file mode 100644
index 0000000..c4614d3
--- /dev/null
+++ b/arch/x86/include/asm/pch_common.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __asm_pch_common_h
+#define __asm_pch_common_h
+
+/* Common Intel SATA registers */
+#define SATA_SIRI		0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD		0xa4 /* SATA Indexed Register Data */
+#define SATA_SP			0xd0 /* Scratchpad */
+
+#define INTR_LN			0x3c
+#define IDE_TIM_PRI		0x40	/* IDE timings, primary */
+#define   IDE_DECODE_ENABLE	(1 << 15)
+#define   IDE_SITRE		(1 << 14)
+#define   IDE_ISP_5_CLOCKS	(0 << 12)
+#define   IDE_ISP_4_CLOCKS	(1 << 12)
+#define   IDE_ISP_3_CLOCKS	(2 << 12)
+#define   IDE_RCT_4_CLOCKS	(0 <<  8)
+#define   IDE_RCT_3_CLOCKS	(1 <<  8)
+#define   IDE_RCT_2_CLOCKS	(2 <<  8)
+#define   IDE_RCT_1_CLOCKS	(3 <<  8)
+#define   IDE_DTE1		(1 <<  7)
+#define   IDE_PPE1		(1 <<  6)
+#define   IDE_IE1		(1 <<  5)
+#define   IDE_TIME1		(1 <<  4)
+#define   IDE_DTE0		(1 <<  3)
+#define   IDE_PPE0		(1 <<  2)
+#define   IDE_IE0		(1 <<  1)
+#define   IDE_TIME0		(1 <<  0)
+#define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
+
+#define SERIRQ_CNTL		0x64
+
+/**
+ * pch_common_sir_read() - Read from a SATA indexed register
+ *
+ * @dev:	SATA device
+ * @idx:	Register index to read
+ * @return value read from register
+ */
+u32 pch_common_sir_read(struct udevice *dev, int idx);
+
+/**
+ * pch_common_sir_write() - Write to a SATA indexed register
+ *
+ * @dev:	SATA device
+ * @idx:	Register index to write
+ * @value:	Value to write
+ */
+void pch_common_sir_write(struct udevice *dev, int idx, u32 value);
+
+#endif
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
new file mode 100644
index 0000000..2a72073
--- /dev/null
+++ b/arch/x86/include/asm/pci.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ */
+
+#ifndef _PCI_I386_H_
+#define _PCI_I386_H_
+
+#include <pci.h>
+
+/* bus mapping constants (used for PCI core initialization) */
+#define PCI_REG_ADDR	0xcf8
+#define PCI_REG_DATA	0xcfc
+
+#define PCI_CFG_EN	0x80000000
+
+#ifndef __ASSEMBLY__
+
+/**
+ * pci_x86_read_config() - Read a configuration value from a device
+ *
+ * This function can be called before PCI is set up in driver model.
+ *
+ * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:	Register offset to read
+ * @valuep:	Place to put the returned value
+ * @size:	Access size
+ * @return 0 if OK, -ve on error
+ */
+int pci_x86_read_config(pci_dev_t bdf, uint offset, ulong *valuep,
+			enum pci_size_t size);
+
+/**
+ * pci_bus_write_config() - Write a configuration value to a device
+ *
+ * This function can be called before PCI is set up in driver model.
+ *
+ * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:	Register offset to write
+ * @value:	Value to write
+ * @size:	Access size
+ * @return 0 if OK, -ve on error
+ */
+int pci_x86_write_config(pci_dev_t bdf, uint offset, ulong value,
+			 enum pci_size_t size);
+
+/**
+ * pci_bus_clrset_config32() - Update a configuration value for a device
+ *
+ * The register at @offset is updated to (oldvalue & ~clr) | set. This function
+ * can be called before PCI is set up in driver model.
+ *
+ * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:	Register offset to update
+ * @clr:	Bits to clear
+ * @set:	Bits to set
+ * @return 0 if OK, -ve on error
+ */
+int pci_x86_clrset_config(pci_dev_t bdf, uint offset, ulong clr, ulong set,
+			  enum pci_size_t size);
+
+/**
+ * Assign IRQ number to a PCI device
+ *
+ * This function assigns IRQ for a PCI device. If the device does not exist
+ * or does not require interrupts then this function has no effect.
+ *
+ * @bus:	PCI bus number
+ * @device:	PCI device number
+ * @irq:	An array of IRQ numbers that are assigned to INTA through
+ *		INTD of this PCI device.
+ */
+void pci_assign_irqs(int bus, int device, u8 irq[4]);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _PCI_I386_H_ */
diff --git a/arch/x86/include/asm/pirq_routing.h b/arch/x86/include/asm/pirq_routing.h
new file mode 100644
index 0000000..67e5c44
--- /dev/null
+++ b/arch/x86/include/asm/pirq_routing.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Ported from coreboot src/arch/x86/include/arch/pirq_routing.h
+ */
+
+#ifndef _PIRQ_ROUTING_H_
+#define _PIRQ_ROUTING_H_
+
+/*
+ * This is the maximum number on interrupt entries that a PCI device may have.
+ *   This is NOT the number of slots or devices in the system
+ *   This is NOT the number of entries in the PIRQ table
+ *
+ * This tells us that in the PIRQ table, we are going to have 4 link-bitmap
+ * entries per PCI device which is fixed at 4: INTA, INTB, INTC, and INTD.
+ *
+ * CAUTION: If you change this, PIRQ routing will not work correctly.
+ */
+#define MAX_INTX_ENTRIES	4
+
+#define PIRQ_SIGNATURE		\
+	(('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
+#define PIRQ_VERSION		0x0100
+
+struct __packed irq_info {
+	u8 bus;			/* Bus number */
+	u8 devfn;		/* Device and function number */
+	struct __packed {
+		u8 link;	/* IRQ line ID, 0=not routed */
+		u16 bitmap;	/* Available IRQs */
+	} irq[MAX_INTX_ENTRIES];
+	u8 slot;		/* Slot number, 0=onboard */
+	u8 rfu;
+};
+
+struct __packed irq_routing_table {
+	u32 signature;		/* PIRQ_SIGNATURE */
+	u16 version;		/* PIRQ_VERSION */
+	u16 size;		/* Table size in bytes */
+	u8 rtr_bus;		/* busno of the interrupt router */
+	u8 rtr_devfn;		/* devfn of the interrupt router */
+	u16 exclusive_irqs;	/* IRQs devoted exclusively to PCI usage */
+	u16 rtr_vendor;		/* Vendor ID of the interrupt router */
+	u16 rtr_device;		/* Device ID of the interrupt router */
+	u32 miniport_data;
+	u8 rfu[11];
+	u8 checksum;		/* Modulo 256 checksum must give zero */
+	struct irq_info slots[CONFIG_IRQ_SLOT_COUNT];
+};
+
+/**
+ * get_irq_slot_count() - Get the number of entries in the irq_info table
+ *
+ * This calculates the number of entries for the irq_info table.
+ *
+ * @rt:		pointer to the base address of the struct irq_info
+ * @return:	number of entries
+ */
+static inline int get_irq_slot_count(struct irq_routing_table *rt)
+{
+	return (rt->size - 32) / sizeof(struct irq_info);
+}
+
+/**
+ * pirq_check_irq_routed() - Check whether an IRQ is routed to 8259 PIC
+ *
+ * This function checks whether an IRQ is routed to 8259 PIC for a given link.
+ *
+ * Note: this function should be provided by the platform codes, as the
+ * implementation of interrupt router may be different.
+ *
+ * @dev:	irq router's udevice
+ * @link:	link number which represents a PIRQ
+ * @irq:	the 8259 IRQ number
+ * @return:	true if the irq is already routed to 8259 for a given link,
+ *		false elsewise
+ */
+bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq);
+
+/**
+ * pirq_translate_link() - Translate a link value
+ *
+ * This function translates a platform-specific link value to a link number.
+ * On Intel platforms, the link value is normally a offset into the PCI
+ * configuration space into the legacy bridge.
+ *
+ * Note: this function should be provided by the platform codes, as the
+ * implementation of interrupt router may be different.
+ *
+ * @dev:	irq router's udevice
+ * @link:	platform-specific link value
+ * @return:	link number which represents a PIRQ
+ */
+int pirq_translate_link(struct udevice *dev, int link);
+
+/**
+ * pirq_assign_irq() - Assign an IRQ to a PIRQ link
+ *
+ * This function assigns the IRQ to a PIRQ link so that the PIRQ is routed to
+ * the 8259 PIC.
+ *
+ * Note: this function should be provided by the platform codes, as the
+ * implementation of interrupt router may be different.
+ *
+ * @dev:	irq router's udevice
+ * @link:	link number which represents a PIRQ
+ * @irq:	IRQ to which the PIRQ is routed
+ */
+void pirq_assign_irq(struct udevice *dev, int link, u8 irq);
+
+/**
+ * pirq_route_irqs() - Route PIRQs to 8259 PIC
+ *
+ * This function configures all PCI devices' interrupt pins and maps them to
+ * PIRQs and finally 8259 PIC. The routed irq number is written to interrupt
+ * line register in the configuration space of the PCI device for OS to use.
+ * The configuration source is taken from a struct irq_info table, the format
+ * of which is defined in PIRQ routing table spec and PCI BIOS spec.
+ *
+ * @dev:	irq router's udevice
+ * @irq:	pointer to the base address of the struct irq_info
+ * @num:	number of entries in the struct irq_info
+ */
+void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num);
+
+/**
+ * copy_pirq_routing_table() - Copy a PIRQ routing table
+ *
+ * This helper function copies the given PIRQ routing table to a given address.
+ * Before copying, it does several sanity tests against the PIRQ routing table.
+ * It also fixes up the table checksum and align the given address to a 16 byte
+ * boundary to meet the PIRQ routing table spec requirements.
+ *
+ * @addr:	address to store the copied PIRQ routing table
+ * @rt:		pointer to the PIRQ routing table to copy from
+ * @return:	end address of the copied PIRQ routing table
+ */
+u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt);
+
+#endif /* _PIRQ_ROUTING_H_ */
diff --git a/arch/x86/include/asm/pmu.h b/arch/x86/include/asm/pmu.h
new file mode 100644
index 0000000..b76bdf6
--- /dev/null
+++ b/arch/x86/include/asm/pmu.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Intel Corporation
+ */
+#ifndef _X86_ASM_PMU_IPC_H_
+#define _X86_ASM_PMU_IPC_H_
+
+int pmu_turn_power(unsigned int lss, bool on);
+
+#endif	/* _X86_ASM_PMU_IPC_H_ */
diff --git a/arch/x86/include/asm/pnp_def.h b/arch/x86/include/asm/pnp_def.h
new file mode 100644
index 0000000..0345d19
--- /dev/null
+++ b/arch/x86/include/asm/pnp_def.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Adapted from coreboot src/include/device/pnp_def.h
+ * and arch/x86/include/arch/io.h
+ */
+
+#ifndef _ASM_PNP_DEF_H_
+#define _ASM_PNP_DEF_H_
+
+#include <asm/io.h>
+
+#define PNP_IDX_EN   0x30
+#define PNP_IDX_IO0  0x60
+#define PNP_IDX_IO1  0x62
+#define PNP_IDX_IO2  0x64
+#define PNP_IDX_IO3  0x66
+#define PNP_IDX_IRQ0 0x70
+#define PNP_IDX_IRQ1 0x72
+#define PNP_IDX_DRQ0 0x74
+#define PNP_IDX_DRQ1 0x75
+#define PNP_IDX_MSC0 0xf0
+#define PNP_IDX_MSC1 0xf1
+
+/* Generic functions for pnp devices */
+
+/*
+ * pnp device is a 16-bit integer composed of its i/o port address at high byte
+ * and logic function number at low byte.
+ */
+#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
+
+static inline void pnp_write_config(uint16_t dev, uint8_t reg, uint8_t value)
+{
+	uint8_t port = dev >> 8;
+
+	outb(reg, port);
+	outb(value, port + 1);
+}
+
+static inline uint8_t pnp_read_config(uint16_t dev, uint8_t reg)
+{
+	uint8_t port = dev >> 8;
+
+	outb(reg, port);
+	return inb(port + 1);
+}
+
+static inline void pnp_set_logical_device(uint16_t dev)
+{
+	uint8_t device = dev & 0xff;
+
+	pnp_write_config(dev, 0x07, device);
+}
+
+static inline void pnp_set_enable(uint16_t dev, int enable)
+{
+	pnp_write_config(dev, PNP_IDX_EN, enable ? 1 : 0);
+}
+
+static inline int pnp_read_enable(uint16_t dev)
+{
+	return !!pnp_read_config(dev, PNP_IDX_EN);
+}
+
+static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase)
+{
+	pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
+	pnp_write_config(dev, index + 1, iobase & 0xff);
+}
+
+static inline uint16_t pnp_read_iobase(uint16_t dev, uint8_t index)
+{
+	return ((uint16_t)(pnp_read_config(dev, index)) << 8) |
+		pnp_read_config(dev, index + 1);
+}
+
+static inline void pnp_set_irq(uint16_t dev, uint8_t index, unsigned irq)
+{
+	pnp_write_config(dev, index, irq);
+}
+
+static inline void pnp_set_drq(uint16_t dev, uint8_t index, unsigned drq)
+{
+	pnp_write_config(dev, index, drq & 0xff);
+}
+
+#endif /* _ASM_PNP_DEF_H_ */
diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h
new file mode 100644
index 0000000..dbcea7f
--- /dev/null
+++ b/arch/x86/include/asm/posix_types.h
@@ -0,0 +1,86 @@
+#ifndef __ARCH_I386_POSIX_TYPES_H
+#define __ARCH_I386_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short	__kernel_dev_t;
+typedef unsigned long	__kernel_ino_t;
+typedef unsigned short	__kernel_mode_t;
+typedef unsigned short	__kernel_nlink_t;
+typedef long		__kernel_off_t;
+typedef int		__kernel_pid_t;
+typedef unsigned short	__kernel_ipc_pid_t;
+typedef unsigned short	__kernel_uid_t;
+typedef unsigned short	__kernel_gid_t;
+/* checking against __x86_64__ covers both 64-bit EFI stub and 64-bit U-Boot */
+#if defined(__x86_64__)
+typedef unsigned long	__kernel_size_t;
+typedef long		__kernel_ssize_t;
+#else
+typedef unsigned int	__kernel_size_t;
+typedef int		__kernel_ssize_t;
+#endif
+typedef int		__kernel_ptrdiff_t;
+typedef long		__kernel_time_t;
+typedef long		__kernel_suseconds_t;
+typedef long		__kernel_clock_t;
+typedef int		__kernel_daddr_t;
+typedef char *		__kernel_caddr_t;
+typedef unsigned short	__kernel_uid16_t;
+typedef unsigned short	__kernel_gid16_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
+
+typedef unsigned short	__kernel_old_uid_t;
+typedef unsigned short	__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long	__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd,fdsetp) \
+		__asm__ __volatile__("btsl %1,%0": \
+			"=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd,fdsetp) \
+		__asm__ __volatile__("btrl %1,%0": \
+			"=m" (*(__kernel_fd_set *) (fdsetp)):"r" ((int) (fd)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd,fdsetp) (__extension__ ({ \
+		unsigned char __result; \
+		__asm__ __volatile__("btl %1,%2 ; setb %0" \
+			:"=q" (__result) :"r" ((int) (fd)), \
+			"m" (*(__kernel_fd_set *) (fdsetp))); \
+		__result; }))
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+do { \
+	int __d0, __d1; \
+	__asm__ __volatile__("cld ; rep ; stosl" \
+			:"=m" (*(__kernel_fd_set *) (fdsetp)), \
+			  "=&c" (__d0), "=&D" (__d1) \
+			:"a" (0), "1" (__FDSET_LONGS), \
+			"2" ((__kernel_fd_set *) (fdsetp)) : "memory"); \
+} while (0)
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif
diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
new file mode 100644
index 0000000..939b6fa
--- /dev/null
+++ b/arch/x86/include/asm/post.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc
+ */
+
+#ifndef _post_h
+#define _post_h
+
+/* port to use for post codes */
+#define POST_PORT		0x80
+
+/* post codes which represent various stages of init */
+#define POST_START		0x1e
+#define POST_CAR_START		0x1f
+#define POST_CAR_SIPI		0x20
+#define POST_CAR_MTRR		0x21
+#define POST_CAR_UNCACHEABLE	0x22
+#define POST_CAR_BASE_ADDRESS	0x23
+#define POST_CAR_MASK		0x24
+#define POST_CAR_FILL		0x25
+#define POST_CAR_ROM_CACHE	0x26
+#define POST_CAR_MRC_CACHE	0x27
+#define POST_CAR_CPU_CACHE	0x28
+#define POST_START_STACK	0x29
+#define POST_START_DONE		0x2a
+#define POST_CPU_INIT		0x2b
+#define POST_EARLY_INIT		0x2c
+#define POST_CPU_INFO		0x2d
+#define POST_PRE_MRC		0x2e
+#define POST_MRC		0x2f
+#define POST_DRAM		0x30
+#define POST_LAPIC		0x31
+#define POST_OS_RESUME		0x40
+
+#define POST_RAM_FAILURE	0xea
+#define POST_BIST_FAILURE	0xeb
+#define POST_CAR_FAILURE	0xec
+#define POST_RESUME_FAILURE	0xed
+
+/* Output a post code using al - value must be 0 to 0xff */
+#ifdef __ASSEMBLY__
+#define post_code(value) \
+	movb	$value, %al; \
+	outb	%al, $POST_PORT
+#else
+#include <asm/io.h>
+
+static inline void post_code(int code)
+{
+	outb(code, POST_PORT);
+}
+#endif
+
+#endif
diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h
new file mode 100644
index 0000000..7a3e836
--- /dev/null
+++ b/arch/x86/include/asm/processor-flags.h
@@ -0,0 +1,100 @@
+#ifndef _ASM_X86_PROCESSOR_FLAGS_H
+#define _ASM_X86_PROCESSOR_FLAGS_H
+/* Various flags defined: can be included from assembler. */
+
+/*
+ * EFLAGS bits
+ */
+#define X86_EFLAGS_CF	0x00000001 /* Carry Flag */
+#define X86_EFLAGS_PF	0x00000004 /* Parity Flag */
+#define X86_EFLAGS_AF	0x00000010 /* Auxillary carry Flag */
+#define X86_EFLAGS_ZF	0x00000040 /* Zero Flag */
+#define X86_EFLAGS_SF	0x00000080 /* Sign Flag */
+#define X86_EFLAGS_TF	0x00000100 /* Trap Flag */
+#define X86_EFLAGS_IF	0x00000200 /* Interrupt Flag */
+#define X86_EFLAGS_DF	0x00000400 /* Direction Flag */
+#define X86_EFLAGS_OF	0x00000800 /* Overflow Flag */
+#define X86_EFLAGS_IOPL	0x00003000 /* IOPL mask */
+#define X86_EFLAGS_NT	0x00004000 /* Nested Task */
+#define X86_EFLAGS_RF	0x00010000 /* Resume Flag */
+#define X86_EFLAGS_VM	0x00020000 /* Virtual Mode */
+#define X86_EFLAGS_AC	0x00040000 /* Alignment Check */
+#define X86_EFLAGS_VIF	0x00080000 /* Virtual Interrupt Flag */
+#define X86_EFLAGS_VIP	0x00100000 /* Virtual Interrupt Pending */
+#define X86_EFLAGS_ID	0x00200000 /* CPUID detection flag */
+
+/*
+ * Basic CPU control in CR0
+ */
+#define X86_CR0_PE	0x00000001 /* Protection Enable */
+#define X86_CR0_MP	0x00000002 /* Monitor Coprocessor */
+#define X86_CR0_EM	0x00000004 /* Emulation */
+#define X86_CR0_TS	0x00000008 /* Task Switched */
+#define X86_CR0_ET	0x00000010 /* Extension Type */
+#define X86_CR0_NE	0x00000020 /* Numeric Error */
+#define X86_CR0_WP	0x00010000 /* Write Protect */
+#define X86_CR0_AM	0x00040000 /* Alignment Mask */
+#define X86_CR0_NW	0x20000000 /* Not Write-through */
+#define X86_CR0_CD	0x40000000 /* Cache Disable */
+#define X86_CR0_PG	0x80000000 /* Paging */
+
+/*
+ * Paging options in CR3
+ */
+#define X86_CR3_PWT	0x00000008 /* Page Write Through */
+#define X86_CR3_PCD	0x00000010 /* Page Cache Disable */
+
+/*
+ * Intel CPU features in CR4
+ */
+#define X86_CR4_VME	0x00000001 /* enable vm86 extensions */
+#define X86_CR4_PVI	0x00000002 /* virtual interrupts flag enable */
+#define X86_CR4_TSD	0x00000004 /* disable time stamp at ipl 3 */
+#define X86_CR4_DE	0x00000008 /* enable debugging extensions */
+#define X86_CR4_PSE	0x00000010 /* enable page size extensions */
+#define X86_CR4_PAE	0x00000020 /* enable physical address extensions */
+#define X86_CR4_MCE	0x00000040 /* Machine check enable */
+#define X86_CR4_PGE	0x00000080 /* enable global pages */
+#define X86_CR4_PCE	0x00000100 /* enable performance counters at ipl 3 */
+#define X86_CR4_OSFXSR	0x00000200 /* enable fast FPU save and restore */
+#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+#define X86_CR4_VMXE	0x00002000 /* enable VMX virtualization */
+#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
+
+/*
+ * x86-64 Task Priority Register, CR8
+ */
+#define X86_CR8_TPR	0x0000000F /* task priority register */
+
+/*
+ * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
+ */
+
+/*
+ *      NSC/Cyrix CPU configuration register indexes
+ */
+#define CX86_PCR0	0x20
+#define CX86_GCR	0xb8
+#define CX86_CCR0	0xc0
+#define CX86_CCR1	0xc1
+#define CX86_CCR2	0xc2
+#define CX86_CCR3	0xc3
+#define CX86_CCR4	0xe8
+#define CX86_CCR5	0xe9
+#define CX86_CCR6	0xea
+#define CX86_CCR7	0xeb
+#define CX86_PCR1	0xf0
+#define CX86_DIR0	0xfe
+#define CX86_DIR1	0xff
+#define CX86_ARR_BASE	0xc4
+#define CX86_RCR_BASE	0xdc
+
+#ifdef __KERNEL__
+#ifdef CONFIG_VM86
+#define X86_VM_MASK	X86_EFLAGS_VM
+#else
+#define X86_VM_MASK	0 /* No VM86 support */
+#endif
+#endif
+
+#endif /* _ASM_X86_PROCESSOR_FLAGS_H */
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
new file mode 100644
index 0000000..f1d9977
--- /dev/null
+++ b/arch/x86/include/asm/processor.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ */
+
+#ifndef __ASM_PROCESSOR_H_
+#define __ASM_PROCESSOR_H_ 1
+
+#define X86_GDT_ENTRY_SIZE		8
+
+#define X86_GDT_ENTRY_NULL		0
+#define X86_GDT_ENTRY_UNUSED		1
+#define X86_GDT_ENTRY_32BIT_CS		2
+#define X86_GDT_ENTRY_32BIT_DS		3
+#define X86_GDT_ENTRY_32BIT_FS		4
+#define X86_GDT_ENTRY_16BIT_CS		5
+#define X86_GDT_ENTRY_16BIT_DS		6
+#define X86_GDT_ENTRY_16BIT_FLAT_CS	7
+#define X86_GDT_ENTRY_16BIT_FLAT_DS	8
+#define X86_GDT_NUM_ENTRIES		9
+
+#define X86_GDT_SIZE		(X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
+
+/* Length of the public header on Intel microcode blobs */
+#define UCODE_HEADER_LEN	0x30
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This register is documented in (for example) the Intel Atom Processor E3800
+ * Product Family Datasheet in "PCU - Power Management Controller (PMC)".
+ *
+ * RST_CNT: Reset Control Register (RST_CNT) Offset cf9.
+ *
+ * The naming follows Intel's naming.
+ */
+#define IO_PORT_RESET		0xcf9
+
+enum {
+	SYS_RST		= 1 << 1,	/* 0 for soft reset, 1 for hard reset */
+	RST_CPU		= 1 << 2,	/* initiate reset */
+	FULL_RST	= 1 << 3,	/* full power cycle */
+};
+
+static inline __attribute__((always_inline)) void cpu_hlt(void)
+{
+	asm("hlt");
+}
+
+static inline ulong cpu_get_sp(void)
+{
+	ulong result;
+
+	asm volatile(
+		"mov %%esp, %%eax"
+		: "=a" (result));
+	return result;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
new file mode 100644
index 0000000..3849bc0
--- /dev/null
+++ b/arch/x86/include/asm/ptrace.h
@@ -0,0 +1,100 @@
+#ifndef _I386_PTRACE_H
+#define _I386_PTRACE_H
+
+#include <asm/types.h>
+
+#define EBX 0
+#define ECX 1
+#define EDX 2
+#define ESI 3
+#define EDI 4
+#define EBP 5
+#define EAX 6
+#define DS 7
+#define ES 8
+#define FS 9
+#define GS 10
+#define ORIG_EAX 11
+#define EIP 12
+#define CS  13
+#define EFL 14
+#define UESP 15
+#define SS   16
+#define FRAME_SIZE 17
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+struct pt_regs {
+	long ebx;
+	long ecx;
+	long edx;
+	long esi;
+	long edi;
+	long ebp;
+	long eax;
+	int  xds;
+	int  xes;
+	int  xfs;
+	int  xgs;
+	long orig_eax;
+	long eip;
+	int  xcs;
+	long eflags;
+	long esp;
+	int  xss;
+}  __attribute__ ((packed));
+
+struct irq_regs {
+	/* Pushed by irq_common_entry */
+	long ebx;
+	long ecx;
+	long edx;
+	long esi;
+	long edi;
+	long ebp;
+	long esp;
+	long eax;
+	long xds;
+	long xes;
+	long xfs;
+	long xgs;
+	long xss;
+	/* Pushed by vector handler (irq_<num>) */
+	long irq_id;
+	/* Pushed by cpu in response to interrupt */
+	union {
+		struct {
+			long eip;
+			long xcs;
+			long eflags;
+		} ctx1;
+		struct {
+			long err;
+			long eip;
+			long xcs;
+			long eflags;
+		} ctx2;
+	} context;
+}  __attribute__ ((packed));
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS            12
+#define PTRACE_SETREGS            13
+#define PTRACE_GETFPREGS          14
+#define PTRACE_SETFPREGS          15
+#define PTRACE_GETFPXREGS         18
+#define PTRACE_SETFPXREGS         19
+
+#define PTRACE_SETOPTIONS         21
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD     0x00000001
+
+#ifdef __KERNEL__
+#define user_mode(regs) ((VM_MASK & (regs)->eflags) || (3 & (regs)->xcs))
+#define instruction_pointer(regs) ((regs)->eip)
+extern void show_regs(struct pt_regs *);
+#endif
+
+#endif
diff --git a/arch/x86/include/asm/report_platform.h b/arch/x86/include/asm/report_platform.h
new file mode 100644
index 0000000..26e70f1
--- /dev/null
+++ b/arch/x86/include/asm/report_platform.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __ARCH_REPORT_PLATFORM_H
+#define __ARCH_REPORT_PLATFORM_H
+
+/**
+ * report_platform_info() - Report platform information
+ *
+ * This reports information about the CPU and chipset.
+ *
+ * @dev:	Northbridge device
+ */
+void report_platform_info(struct udevice *dev);
+
+#endif
diff --git a/arch/x86/include/asm/scu.h b/arch/x86/include/asm/scu.h
new file mode 100644
index 0000000..f5ec5a1
--- /dev/null
+++ b/arch/x86/include/asm/scu.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Intel Corporation
+ */
+#ifndef _X86_ASM_SCU_IPC_H_
+#define _X86_ASM_SCU_IPC_H_
+
+/* IPC defines the following message types */
+#define IPCMSG_INDIRECT_READ	0x02
+#define IPCMSG_INDIRECT_WRITE	0x05
+#define IPCMSG_WARM_RESET	0xf0
+#define IPCMSG_COLD_RESET	0xf1
+#define IPCMSG_SOFT_RESET	0xf2
+#define IPCMSG_COLD_BOOT	0xf3
+#define IPCMSG_GET_FW_REVISION	0xf4
+#define IPCMSG_WATCHDOG_TIMER	0xf8	/* Set Kernel Watchdog Threshold */
+
+struct ipc_ifwi_version {
+	u16	minor;
+	u8	major;
+	u8	hardware_id;
+	u32	reserved[3];
+};
+
+/* Issue commands to the SCU with or without data */
+int scu_ipc_simple_command(u32 cmd, u32 sub);
+int scu_ipc_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out, int outlen);
+int scu_ipc_raw_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out,
+			int outlen, u32 dptr, u32 sptr);
+
+#endif	/* _X86_ASM_SCU_IPC_H_ */
diff --git a/arch/x86/include/asm/sections.h b/arch/x86/include/asm/sections.h
new file mode 100644
index 0000000..a6be360
--- /dev/null
+++ b/arch/x86/include/asm/sections.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_X86_SECTIONS_H
+#define __ASM_X86_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/x86/include/asm/setjmp.h b/arch/x86/include/asm/setjmp.h
new file mode 100644
index 0000000..49c36c1
--- /dev/null
+++ b/arch/x86/include/asm/setjmp.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Written by H. Peter Anvin <hpa@zytor.com>
+ * Brought in from Linux v4.4 and modified for U-Boot
+ * From Linux arch/um/sys-i386/setjmp.S
+ */
+
+#ifndef __setjmp_h
+#define __setjmp_h
+
+#ifdef CONFIG_X86_64
+
+struct jmp_buf_data {
+	unsigned long __rip;
+	unsigned long __rsp;
+	unsigned long __rbp;
+	unsigned long __rbx;
+	unsigned long __r12;
+	unsigned long __r13;
+	unsigned long __r14;
+	unsigned long __r15;
+};
+
+#else
+
+struct jmp_buf_data {
+	unsigned int __ebx;
+	unsigned int __esp;
+	unsigned int __ebp;
+	unsigned int __esi;
+	unsigned int __edi;
+	unsigned int __eip;
+};
+
+#endif
+
+int setjmp(struct jmp_buf_data *jmp_buf);
+void longjmp(struct jmp_buf_data *jmp_buf, int val);
+
+#endif
diff --git a/arch/x86/include/asm/sfi.h b/arch/x86/include/asm/sfi.h
new file mode 100644
index 0000000..09d4700
--- /dev/null
+++ b/arch/x86/include/asm/sfi.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright(c) 2009 Intel Corporation. All rights reserved.
+ */
+
+#ifndef _LINUX_SFI_H
+#define _LINUX_SFI_H
+
+#include <errno.h>
+#include <linux/types.h>
+
+/* Table signatures reserved by the SFI specification */
+#define SFI_SIG_SYST		"SYST"
+#define SFI_SIG_FREQ		"FREQ"
+#define SFI_SIG_CPUS		"CPUS"
+#define SFI_SIG_MTMR		"MTMR"
+#define SFI_SIG_MRTC		"MRTC"
+#define SFI_SIG_MMAP		"MMAP"
+#define SFI_SIG_APIC		"APIC"
+#define SFI_SIG_XSDT		"XSDT"
+#define SFI_SIG_WAKE		"WAKE"
+#define SFI_SIG_DEVS		"DEVS"
+#define SFI_SIG_GPIO		"GPIO"
+
+#define SFI_SIGNATURE_SIZE	4
+#define SFI_OEM_ID_SIZE		6
+#define SFI_OEM_TABLE_ID_SIZE	8
+
+#define SFI_NAME_LEN		16
+#define SFI_TABLE_MAX_ENTRIES	16
+
+#define SFI_GET_NUM_ENTRIES(ptable, entry_type) \
+	((ptable->header.len - sizeof(struct sfi_table_header)) / \
+	(sizeof(entry_type)))
+/*
+ * Table structures must be byte-packed to match the SFI specification,
+ * as they are provided by the BIOS.
+ */
+struct __packed sfi_table_header {
+	char	sig[SFI_SIGNATURE_SIZE];
+	u32	len;
+	u8	rev;
+	u8	csum;
+	char	oem_id[SFI_OEM_ID_SIZE];
+	char	oem_table_id[SFI_OEM_TABLE_ID_SIZE];
+};
+
+struct __packed sfi_table_simple {
+	struct sfi_table_header		header;
+	u64				pentry[1];
+};
+
+/* Comply with UEFI spec 2.1 */
+struct __packed sfi_mem_entry {
+	u32	type;
+	u64	phys_start;
+	u64	virt_start;
+	u64	pages;
+	u64	attrib;
+};
+
+/* Memory type definitions */
+enum sfi_mem_type {
+	SFI_MEM_RESERVED,
+	SFI_LOADER_CODE,
+	SFI_LOADER_DATA,
+	SFI_BOOT_SERVICE_CODE,
+	SFI_BOOT_SERVICE_DATA,
+	SFI_RUNTIME_SERVICE_CODE,
+	SFI_RUNTIME_SERVICE_DATA,
+	SFI_MEM_CONV,
+	SFI_MEM_UNUSABLE,
+	SFI_ACPI_RECLAIM,
+	SFI_ACPI_NVS,
+	SFI_MEM_MMIO,
+	SFI_MEM_IOPORT,
+	SFI_PAL_CODE,
+	SFI_MEM_TYPEMAX,
+};
+
+struct __packed sfi_cpu_table_entry {
+	u32	apic_id;
+};
+
+struct __packed sfi_cstate_table_entry {
+	u32	hint;		/* MWAIT hint */
+	u32	latency;	/* latency in ms */
+};
+
+struct __packed sfi_apic_table_entry {
+	u64	phys_addr;	/* phy base addr for APIC reg */
+};
+
+struct __packed sfi_freq_table_entry {
+	u32	freq_mhz;	/* in MHZ */
+	u32	latency;	/* transition latency in ms */
+	u32	ctrl_val;	/* value to write to PERF_CTL */
+};
+
+struct __packed sfi_wake_table_entry {
+	u64	phys_addr;	/* pointer to where the wake vector locates */
+};
+
+struct __packed sfi_timer_table_entry {
+	u64	phys_addr;	/* phy base addr for the timer */
+	u32	freq_hz;	/* in HZ */
+	u32	irq;
+};
+
+struct __packed sfi_rtc_table_entry {
+	u64	phys_addr;	/* phy base addr for the RTC */
+	u32	irq;
+};
+
+struct __packed sfi_device_table_entry {
+	u8	type;		/* bus type, I2C, SPI or ...*/
+	u8	host_num;	/* attached to host 0, 1...*/
+	u16	addr;
+	u8	irq;
+	u32	max_freq;
+	char	name[SFI_NAME_LEN];
+};
+
+enum {
+	SFI_DEV_TYPE_SPI	= 0,
+	SFI_DEV_TYPE_I2C,
+	SFI_DEV_TYPE_UART,
+	SFI_DEV_TYPE_HSI,
+	SFI_DEV_TYPE_IPC,
+	SFI_DEV_TYPE_SD,
+};
+
+struct __packed sfi_gpio_table_entry {
+	char	controller_name[SFI_NAME_LEN];
+	u16	pin_no;
+	char	pin_name[SFI_NAME_LEN];
+};
+
+struct sfi_xsdt_header {
+	uint32_t oem_revision;
+	uint32_t creator_id;
+	uint32_t creator_revision;
+};
+
+typedef int (*sfi_table_handler) (struct sfi_table_header *table);
+
+/**
+ * write_sfi_table() - Write Simple Firmware Interface tables
+ *
+ * @base:	Address to write table to
+ * @return address to use for the next table
+ */
+ulong write_sfi_table(ulong base);
+
+#endif /*_LINUX_SFI_H */
diff --git a/arch/x86/include/asm/sipi.h b/arch/x86/include/asm/sipi.h
new file mode 100644
index 0000000..1ab6c28
--- /dev/null
+++ b/arch/x86/include/asm/sipi.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Gooogle, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _ASM_SIPI_H
+#define _ASM_SIPI_H
+
+#define AP_DEFAULT_BASE 0x30000
+#define AP_DEFAULT_SIZE 0x10000
+
+#ifndef __ASSEMBLER__
+
+/**
+ * struct sipi_params_16bit - 16-bit SIPI entry-point parameters
+ *
+ * These are set up in the same space as the SIPI 16-bit code so that each AP
+ * can access the parameters when it boots.
+ *
+ * Each of these must be set up for the AP to boot, except @segment which is
+ * set in the assembly code.
+ *
+ * @ap_start:		32-bit SIPI entry point for U-Boot
+ * @segment:		Code segment for U-Boot
+ * @pad:		Padding (not used)
+ * @gdt_limit:		U-Boot GDT limit (X86_GDT_SIZE - 1)
+ * @gdt:		U-Boot GDT (gd->arch.gdt)
+ * @unused:		Not used
+ */
+struct __packed sipi_params_16bit {
+	u32 ap_start;
+	u16 segment;
+	u16 pad;
+	u16 gdt_limit;
+	u32 gdt;
+	u16 unused;
+};
+
+/**
+ * struct sipi_params - 32-bit SIP entry-point parameters
+ *
+ * These are used by the AP init code and must be set up before the APs start.
+ * The members must match with the sipi_params layout in sipi_vector.S.
+ *
+ * The stack area extends down from @stack_top, with @stack_size allocated
+ * for each AP.
+ *
+ * @idt_ptr:		Interrupt descriptor table pointer
+ * @stack_top:		Top of the AP stack area
+ * @stack_size:		Size of each AP's stack
+ * @microcode_lock:	Used to ensure only one AP loads microcode at once
+ *			0xffffffff enables parallel loading.
+ * @microcode_ptr:	Pointer to microcode, or 0 if none
+ * @msr_table_ptr:	Pointer to saved MSRs, a list of struct saved_msr
+ * @msr_count:		Number of saved MSRs
+ * @c_handler:		C function to call once early init is complete
+ * @ap_count:		Shared atomic value to allocate CPU indexes
+ */
+struct sipi_params {
+	u32 idt_ptr;
+	u32 stack_top;
+	u32 stack_size;
+	u32 microcode_lock;
+	u32 microcode_ptr;
+	u32 msr_table_ptr;
+	u32 msr_count;
+	u32 c_handler;
+	atomic_t ap_count;
+};
+
+/* 16-bit AP entry point */
+void ap_start16(void);
+
+/* end of 16-bit code/data, marks the region to be copied to SIP vector */
+void ap_start16_code_end(void);
+
+/* 32-bit AP entry point */
+void ap_start(void);
+
+extern char sipi_params_16bit[];
+extern char sipi_params[];
+
+#endif /* __ASSEMBLER__ */
+
+#endif
diff --git a/arch/x86/include/asm/speedstep.h b/arch/x86/include/asm/speedstep.h
new file mode 100644
index 0000000..43bfabf
--- /dev/null
+++ b/arch/x86/include/asm/speedstep.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * From Coreboot file of same name
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *               2012 secunet Security Networks AG
+ */
+
+#ifndef _ASM_SPEEDSTEP_H
+#define _ASM_SPEEDSTEP_H
+
+/* Magic value used to locate speedstep configuration in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+/* MWAIT coordination I/O base address. This must match
+ * the \_PR_.CPU0 PM base address.
+ */
+#define PMB0_BASE 0x510
+
+/* PMB1: I/O port that triggers SMI once cores are in the same state.
+ * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
+ */
+#define PMB1_BASE 0x800
+
+struct sst_state {
+	uint8_t dynfsb:1; /* whether this is SLFM */
+	uint8_t nonint:1; /* add .5 to ratio */
+	uint8_t ratio:6;
+	uint8_t vid;
+	uint8_t is_turbo;
+	uint8_t is_slfm;
+	uint32_t power;
+};
+#define SPEEDSTEP_RATIO_SHIFT		8
+#define SPEEDSTEP_RATIO_DYNFSB_SHIFT	(7 + SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_RATIO_DYNFSB		(1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT)
+#define SPEEDSTEP_RATIO_NONINT_SHIFT	(6 + SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_RATIO_NONINT		(1 << SPEEDSTEP_RATIO_NONINT_SHIFT)
+#define SPEEDSTEP_RATIO_VALUE_MASK	(0x1f << SPEEDSTEP_RATIO_SHIFT)
+#define SPEEDSTEP_VID_MASK		0x3f
+#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((struct sst_state){	\
+		0, /* dynfsb won't be read. */				\
+		((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0,	\
+		(((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK)		\
+					>> SPEEDSTEP_RATIO_SHIFT),	\
+		(val & mask) & SPEEDSTEP_VID_MASK,			\
+		0, /* not turbo by default */				\
+		0, /* not slfm by default */				\
+		0  /* power is hardcoded in software. */		\
+	})
+#define SPEEDSTEP_ENCODE_STATE(state)	(				\
+	((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) |	\
+	((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) |	\
+	((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) |		\
+	((uint16_t)(state).vid & SPEEDSTEP_VID_MASK))
+#define SPEEDSTEP_DOUBLE_RATIO(state)	(				\
+	((uint8_t)(state).ratio * 2) + (state).nonint)
+
+struct sst_params {
+	struct sst_state slfm;
+	struct sst_state min;
+	struct sst_state max;
+	struct sst_state turbo;
+};
+
+/* Looking at core2's spec, the highest normal bus ratio for an eist enabled
+   processor is 14, the lowest is always 6. This makes 5 states with the
+   minimal step width of 2. With turbo mode and super LFM we have at most 7. */
+#define SPEEDSTEP_MAX_NORMAL_STATES	5
+#define SPEEDSTEP_MAX_STATES		(SPEEDSTEP_MAX_NORMAL_STATES + 2)
+struct sst_table {
+	/* Table of p-states for EMTTM and ACPI by decreasing performance. */
+	struct sst_state states[SPEEDSTEP_MAX_STATES];
+	int num_states;
+};
+
+void speedstep_gen_pstates(struct sst_table *);
+
+#define SPEEDSTEP_MAX_POWER_YONAH	31000
+#define SPEEDSTEP_MIN_POWER_YONAH	13100
+#define SPEEDSTEP_MAX_POWER_MEROM	35000
+#define SPEEDSTEP_MIN_POWER_MEROM	25000
+#define SPEEDSTEP_SLFM_POWER_MEROM	12000
+#define SPEEDSTEP_MAX_POWER_PENRYN	35000
+#define SPEEDSTEP_MIN_POWER_PENRYN	15000
+#define SPEEDSTEP_SLFM_POWER_PENRYN	12000
+
+#endif
diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h
new file mode 100644
index 0000000..1bef487
--- /dev/null
+++ b/arch/x86/include/asm/spl.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __asm_spl_h
+#define __asm_spl_h
+
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+
+enum {
+	BOOT_DEVICE_SPI_MMAP	= 10,
+	BOOT_DEVICE_CROS_VBOOT,
+};
+
+void jump_to_spl(ulong entry);
+
+#endif
diff --git a/arch/x86/include/asm/string.h b/arch/x86/include/asm/string.h
new file mode 100644
index 0000000..c15b264
--- /dev/null
+++ b/arch/x86/include/asm/string.h
@@ -0,0 +1,47 @@
+#ifndef __ASM_I386_STRING_H
+#define __ASM_I386_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+#undef __HAVE_ARCH_STRNCPY
+extern char *strncpy(char *__dest, __const__ char *__src, __kernel_size_t __n);
+
+#undef __HAVE_ARCH_STRRCHR
+extern char *strrchr(const char *s, int c);
+
+#undef __HAVE_ARCH_STRCHR
+extern char *strchr(const char *s, int c);
+
+#ifdef CONFIG_X86_64
+
+#undef __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#else
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#endif /* CONFIG_X86_64 */
+
+#undef __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *, int, __kernel_size_t);
+
+#undef __HAVE_ARCH_MEMZERO
+extern void memzero(void *ptr, __kernel_size_t n);
+
+#endif
diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h
new file mode 100644
index 0000000..f7c72ed
--- /dev/null
+++ b/arch/x86/include/asm/tables.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _X86_TABLES_H_
+#define _X86_TABLES_H_
+
+#include <tables_csum.h>
+
+#define ROM_TABLE_ADDR	CONFIG_ROM_TABLE_ADDR
+#define ROM_TABLE_END	(CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1)
+
+#define ROM_TABLE_ALIGN	1024
+
+/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
+#define CB_TABLE_ADDR	0x800
+
+/**
+ * table_compute_checksum() - Compute a table checksum
+ *
+ * This computes an 8-bit checksum for the configuration table.
+ * All bytes in the configuration table, including checksum itself and
+ * reserved bytes must add up to zero.
+ *
+ * @v:		configuration table base address
+ * @len:	configuration table size
+ * @return:	the 8-bit checksum
+ */
+u8 table_compute_checksum(void *v, int len);
+
+/**
+ * table_fill_string() - Fill a string with pad in the configuration table
+ *
+ * This fills a string in the configuration table. It copies number of bytes
+ * from the source string, and if source string length is shorter than the
+ * required size to copy, pad the table string with the given pad character.
+ *
+ * @dest:	where to fill a string
+ * @src:	where to copy from
+ * @n:		number of bytes to copy
+ * @pad:	character to pad the remaining bytes
+ */
+void table_fill_string(char *dest, const char *src, size_t n, char pad);
+
+/**
+ * write_tables() - Write x86 configuration tables
+ *
+ * This writes x86 configuration tables, including PIRQ routing table,
+ * Multi-Processor table and ACPI table. Whether a specific type of
+ * configuration table is written is controlled by a Kconfig option.
+ */
+void write_tables(void);
+
+/**
+ * write_pirq_routing_table() - Write PIRQ routing table
+ *
+ * This writes PIRQ routing table at a given address.
+ *
+ * @start:	start address to write PIRQ routing table
+ * @return:	end address of PIRQ routing table
+ */
+ulong write_pirq_routing_table(ulong start);
+
+#endif /* _X86_TABLES_H_ */
diff --git a/arch/x86/include/asm/turbo.h b/arch/x86/include/asm/turbo.h
new file mode 100644
index 0000000..94a6353
--- /dev/null
+++ b/arch/x86/include/asm/turbo.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * From coreboot file of the same name
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ */
+
+#ifndef _ASM_TURBO_H
+#define _ASM_TURBO_H
+
+#define CPUID_LEAF_PM		6
+#define PM_CAP_TURBO_MODE	(1 << 1)
+
+enum {
+	TURBO_UNKNOWN,
+	TURBO_UNAVAILABLE,
+	TURBO_DISABLED,
+	TURBO_ENABLED,
+};
+
+/* Return current turbo state */
+int turbo_get_state(void);
+
+/* Enable turbo */
+void turbo_enable(void);
+
+#endif
diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h
new file mode 100644
index 0000000..ba50001
--- /dev/null
+++ b/arch/x86/include/asm/types.h
@@ -0,0 +1,28 @@
+#ifndef __ASM_I386_TYPES_H
+#define __ASM_I386_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+typedef unsigned short umode_t;
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#if CONFIG_IS_ENABLED(X86_64)
+#define BITS_PER_LONG 64
+#else
+#define BITS_PER_LONG 32
+#endif
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
new file mode 100644
index 0000000..2466ad2
--- /dev/null
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ */
+
+#ifndef _U_BOOT_I386_H_
+#define _U_BOOT_I386_H_	1
+
+struct global_data;
+
+extern char gdt_rom[];
+
+/* cpu/.../cpu.c */
+int arch_cpu_init(void);
+
+/**
+ * x86_cpu_init_f() - Set up basic features of the x86 CPU
+ *
+ * 0 on success, -ve on error
+ */
+int x86_cpu_init_f(void);
+
+/**
+ * x86_cpu_reinit_f() - Set up the CPU a second time
+ *
+ * Once cpu_init_f() has been called (e.g. in SPL) we should not call it
+ * again (e.g. in U-Boot proper) since it sets up the state from scratch.
+ * Call this function in later phases of U-Boot instead. It reads the CPU
+ * identify so that CPU functions can be used correctly, but does not change
+ * anything.
+ *
+ * @return 0 (indicating success, to mimic cpu_init_f())
+ */
+int x86_cpu_reinit_f(void);
+
+int cpu_init_f(void);
+void setup_gdt(struct global_data *id, u64 *gdt_addr);
+/*
+ * Setup FSP execution environment GDT to use the one we used in
+ * arch/x86/cpu/start16.S and reload the segment registers.
+ */
+void setup_fsp_gdt(void);
+int init_cache(void);
+int cleanup_before_linux(void);
+
+/* cpu/.../timer.c */
+void timer_isr(void *);
+typedef void (timer_fnc_t) (void);
+int register_timer_isr (timer_fnc_t *isr_func);
+unsigned long get_tbclk_mhz(void);
+void timer_set_base(uint64_t base);
+int i8254_init(void);
+
+/* cpu/.../interrupts.c */
+int cpu_init_interrupts(void);
+
+int cleanup_before_linux(void);
+int x86_cleanup_before_linux(void);
+void x86_enable_caches(void);
+void x86_disable_caches(void);
+int x86_init_cache(void);
+ulong board_get_usable_ram_top(ulong total_size);
+int default_print_cpuinfo(void);
+
+/* Set up a UART which can be used with printch(), printhex8(), etc. */
+int setup_internal_uart(int enable);
+
+void setup_pcat_compatibility(void);
+
+void isa_unmap_rom(u32 addr);
+u32 isa_map_rom(u32 bus_addr, int size);
+
+/* arch/x86/lib/... */
+int video_bios_init(void);
+
+/* arch/x86/lib/fsp1,2/... */
+
+/**
+ * fsp_save_s3_stack() - save stack address to CMOS for next S3 boot
+ *
+ * At the end of pre-relocation phase, save the new stack address
+ * to CMOS and use it as the stack on next S3 boot for fsp_init()
+ * continuation function.
+ *
+ * @return:	0 if OK, -ve on error
+ */
+int fsp_save_s3_stack(void);
+
+void	board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
+void	board_init_f_r(void) __attribute__ ((noreturn));
+
+int arch_misc_init(void);
+
+/* Read the time stamp counter */
+static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
+{
+	uint32_t high, low;
+	__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
+	return (((uint64_t)high) << 32) | low;
+}
+
+/* board/... */
+void timer_set_tsc_base(uint64_t new_base);
+uint64_t timer_get_tsc(void);
+
+void quick_ram_check(void);
+
+#define PCI_VGA_RAM_IMAGE_START		0xc0000
+
+#endif	/* _U_BOOT_I386_H_ */
diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h
new file mode 100644
index 0000000..432eb35
--- /dev/null
+++ b/arch/x86/include/asm/u-boot.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _U_BOOT_H_
+#define _U_BOOT_H_	1
+
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+#include <asm/u-boot-x86.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_I386
+
+#endif	/* _U_BOOT_H_ */
diff --git a/arch/x86/include/asm/unaligned.h b/arch/x86/include/asm/unaligned.h
new file mode 100644
index 0000000..6cecbbb
--- /dev/null
+++ b/arch/x86/include/asm/unaligned.h
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
diff --git a/arch/x86/include/asm/video/edid.h b/arch/x86/include/asm/video/edid.h
new file mode 100644
index 0000000..928c342
--- /dev/null
+++ b/arch/x86/include/asm/video/edid.h
@@ -0,0 +1,16 @@
+#ifndef __linux_video_edid_h__
+#define __linux_video_edid_h__
+
+#if !defined(__KERNEL__) || defined(CONFIG_X86)
+
+struct edid_info {
+	unsigned char dummy[128];
+};
+
+#ifdef __KERNEL__
+extern struct edid_info edid_info;
+#endif /* __KERNEL__ */
+
+#endif
+
+#endif /* __linux_video_edid_h__ */
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
new file mode 100644
index 0000000..80e128c
--- /dev/null
+++ b/arch/x86/include/asm/zimage.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ */
+
+#ifndef _ASM_ZIMAGE_H_
+#define _ASM_ZIMAGE_H_
+
+#include <asm/bootparam.h>
+#include <asm/e820.h>
+
+/* linux i386 zImage/bzImage header. Offsets relative to
+ * the start of the image */
+
+#define HEAP_FLAG           0x80
+#define BIG_KERNEL_FLAG     0x01
+
+/* magic numbers */
+#define KERNEL_MAGIC        0xaa55
+#define KERNEL_V2_MAGIC     0x53726448
+#define COMMAND_LINE_MAGIC  0xA33F
+
+/* limits */
+#define BZIMAGE_MAX_SIZE   15*1024*1024     /* 15MB */
+#define ZIMAGE_MAX_SIZE    512*1024         /* 512k */
+#define SETUP_MAX_SIZE     32768
+
+#define SETUP_START_OFFSET 0x200
+#define BZIMAGE_LOAD_ADDR  0x100000
+#define ZIMAGE_LOAD_ADDR   0x10000
+
+struct boot_params *load_zimage(char *image, unsigned long kernel_size,
+				ulong *load_addressp);
+int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
+		 unsigned long initrd_addr, unsigned long initrd_size);
+void setup_video(struct screen_info *screen_info);
+void setup_efi_info(struct efi_info *efi_info);
+
+#endif
diff --git a/arch/xtensa/include/asm/addrspace.h b/arch/xtensa/include/asm/addrspace.h
new file mode 100644
index 0000000..3b27f93
--- /dev/null
+++ b/arch/xtensa/include/asm/addrspace.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2008-2013 Tensilica Inc.
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _XTENSA_ADDRSPACE_H
+#define _XTENSA_ADDRSPACE_H
+
+#include <asm/arch/core.h>
+
+/*
+ * MMU Memory Map
+ *
+ * noMMU and v3 MMU have identity mapped address space on reset.
+ * V2 MMU:
+ *   IO (uncached)	f0000000..ffffffff	-> f000000
+ *   IO (cached)	e0000000..efffffff	-> f000000
+ *   MEM (uncached)	d8000000..dfffffff	-> 0000000
+ *   MEM (cached)	d0000000..d7ffffff	-> 0000000
+ *
+ * The actual location of memory and IO is the board property.
+ */
+
+#define IOADDR(x)		(CONFIG_SYS_IO_BASE + (x))
+#define MEMADDR(x)		(CONFIG_SYS_MEMORY_BASE + (x))
+#define PHYSADDR(x)		((x) - XCHAL_VECBASE_RESET_VADDR + \
+				 XCHAL_VECBASE_RESET_PADDR)
+
+#endif	/* _XTENSA_ADDRSPACE_H */
diff --git a/arch/xtensa/include/asm/arch-dc232b/core.h b/arch/xtensa/include/asm/arch-dc232b/core.h
new file mode 100644
index 0000000..c50a358
--- /dev/null
+++ b/arch/xtensa/include/asm/arch-dc232b/core.h
@@ -0,0 +1,422 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Xtensa processor core configuration information.
+ * This file is autogenerated, please do not edit.
+ *
+ * Copyright (C) 1999-2007 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+
+/****************************************************************************
+	    Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ *  configured, and a value of 0 otherwise.  These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+				ISA
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
+#define XCHAL_NUM_AREGS			32	/* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2		5	/* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG		1	/* debug option */
+#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
+#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
+#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R			1	/* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS	1	/* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
+#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
+#define XCHAL_HAVE_ABS			1	/* ABS instruction */
+/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
+/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION		0	/* speculation */
+#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS		1	/* */
+#define XCHAL_NUM_MISC_REGS		2	/* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID			1	/* processor ID register */
+#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS		0	/* boolean registers */
+#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG			8	/* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16		1	/* MAC16 package */
+#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
+#define XCHAL_HAVE_FP			0	/* floating point pkg */
+#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
+#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
+#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
+
+
+/*----------------------------------------------------------------------
+				MISC
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES	8	/* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH		4	/* data width in bytes */
+/*  In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
+
+#define XCHAL_SW_VERSION		701001	/* sw version of this header */
+
+#define XCHAL_CORE_ID			"dc232b"	/* alphanum core name
+						   (CoreID) set in the Xtensa
+						   Processor Generator */
+
+#define XCHAL_CORE_DESCRIPTION		"Diamond 232L Standard Core Rev.B (LE)"
+#define XCHAL_BUILD_UNIQUE_ID		0x0000BEEF	/* 22-bit sw build ID */
+
+/*
+ *  These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0		0xC56307FE	/* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1		0x0D40BEEF	/* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME		"LX2.1.1"	/* full version name */
+#define XCHAL_HW_VERSION_MAJOR		2210	/* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR		1	/* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION		221001	/* major*100+minor */
+#define XCHAL_HW_REL_LX2		1
+#define XCHAL_HW_REL_LX2_1		1
+#define XCHAL_HW_REL_LX2_1_1		1
+#define XCHAL_HW_CONFIGID_RELIABLE	1
+/*  If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR	2210	/* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR	1	/* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION		221001	/* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR	2210	/* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR	1	/* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION		221001	/* latest targeted hw */
+
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE		32	/* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE		32	/* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH		5	/* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH		5	/* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE		16384	/* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE		16384	/* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
+
+
+
+
+/****************************************************************************
+    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
+
+/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
+
+/*  Number of cache sets in log2(lines per way):  */
+#define XCHAL_ICACHE_SETWIDTH		7
+#define XCHAL_DCACHE_SETWIDTH		7
+
+/*  Cache set associativity (number of ways):  */
+#define XCHAL_ICACHE_WAYS		4
+#define XCHAL_DCACHE_WAYS		4
+
+/*  Cache features:  */
+#define XCHAL_ICACHE_LINE_LOCKABLE	1
+#define XCHAL_DCACHE_LINE_LOCKABLE	1
+#define XCHAL_ICACHE_ECC_PARITY		0
+#define XCHAL_DCACHE_ECC_PARITY		0
+
+/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
+#define XCHAL_CA_BITS			4
+
+
+/*----------------------------------------------------------------------
+			INTERNAL I/D RAM/ROMs and XLMI
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM		0	/* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
+#define XCHAL_NUM_DATARAM		0	/* number of core data RAMs */
+#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
+
+
+/*----------------------------------------------------------------------
+			INTERRUPTS and TIMERS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS		22	/* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS		17	/* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
+						   (not including level zero) */
+#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
+	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/*  Masks of interrupts at each interrupt level:  */
+#define XCHAL_INTLEVEL1_MASK		0x001F80FF
+#define XCHAL_INTLEVEL2_MASK		0x00000100
+#define XCHAL_INTLEVEL3_MASK		0x00200E00
+#define XCHAL_INTLEVEL4_MASK		0x00001000
+#define XCHAL_INTLEVEL5_MASK		0x00002000
+#define XCHAL_INTLEVEL6_MASK		0x00000000
+#define XCHAL_INTLEVEL7_MASK		0x00004000
+
+/*  Masks of interrupts at each range 1..n of interrupt levels:  */
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x001F80FF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x001F81FF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x003F8FFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x003F9FFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x003FBFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x003FBFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x003FFFFF
+
+/*  Level of each interrupt:  */
+#define XCHAL_INT0_LEVEL		1
+#define XCHAL_INT1_LEVEL		1
+#define XCHAL_INT2_LEVEL		1
+#define XCHAL_INT3_LEVEL		1
+#define XCHAL_INT4_LEVEL		1
+#define XCHAL_INT5_LEVEL		1
+#define XCHAL_INT6_LEVEL		1
+#define XCHAL_INT7_LEVEL		1
+#define XCHAL_INT8_LEVEL		2
+#define XCHAL_INT9_LEVEL		3
+#define XCHAL_INT10_LEVEL		3
+#define XCHAL_INT11_LEVEL		3
+#define XCHAL_INT12_LEVEL		4
+#define XCHAL_INT13_LEVEL		5
+#define XCHAL_INT14_LEVEL		7
+#define XCHAL_INT15_LEVEL		1
+#define XCHAL_INT16_LEVEL		1
+#define XCHAL_INT17_LEVEL		1
+#define XCHAL_INT18_LEVEL		1
+#define XCHAL_INT19_LEVEL		1
+#define XCHAL_INT20_LEVEL		1
+#define XCHAL_INT21_LEVEL		3
+#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
+#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
+						   EXCSAVE/EPS/EPC_n, RFI n) */
+
+/*  Type of each interrupt:  */
+#define XCHAL_INT0_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE		XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE		XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE		XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE	XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE	XTHAL_INTTYPE_EXTERN_EDGE
+
+/*  Masks of interrupts for each type of interrupt:  */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFC00000
+#define XCHAL_INTTYPE_MASK_SOFTWARE	0x00000880
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x003F8000
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x0000133F
+#define XCHAL_INTTYPE_MASK_TIMER	0x00002440
+#define XCHAL_INTTYPE_MASK_NMI		0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
+
+/*  Interrupt numbers assigned to specific interrupt sources:  */
+#define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT		10	/* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT		13	/* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
+
+/*  Interrupt numbers for levels at which only one interrupt is configured:  */
+#define XCHAL_INTLEVEL2_NUM		8
+#define XCHAL_INTLEVEL4_NUM		12
+#define XCHAL_INTLEVEL5_NUM		13
+#define XCHAL_INTLEVEL7_NUM		14
+/*  (There are many interrupts each at level(s) 1, 3.)  */
+
+
+/*
+ *  External interrupt vectors/levels.
+ *  These macros describe how Xtensa processor interrupt numbers
+ *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ *  map to external BInterrupt<n> pins, for those interrupts
+ *  configured as external (level-triggered, edge-triggered, or NMI).
+ *  See the Xtensa processor databook for more details.
+ */
+
+/*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
+#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM		8	/* (intlevel 2) */
+#define XCHAL_EXTINT7_NUM		9	/* (intlevel 3) */
+#define XCHAL_EXTINT8_NUM		12	/* (intlevel 4) */
+#define XCHAL_EXTINT9_NUM		14	/* (intlevel 7) */
+#define XCHAL_EXTINT10_NUM		15	/* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM		16	/* (intlevel 1) */
+#define XCHAL_EXTINT12_NUM		17	/* (intlevel 1) */
+#define XCHAL_EXTINT13_NUM		18	/* (intlevel 1) */
+#define XCHAL_EXTINT14_NUM		19	/* (intlevel 1) */
+#define XCHAL_EXTINT15_NUM		20	/* (intlevel 1) */
+#define XCHAL_EXTINT16_NUM		21	/* (intlevel 3) */
+
+
+/*----------------------------------------------------------------------
+			EXCEPTIONS and VECTORS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
+						   number: 1 == XEA1 (old)
+							   2 == XEA2 (new)
+							   0 == XEAX (extern) */
+#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
+#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
+#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR	0xD0000000  /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR	0x00000000
+#define XCHAL_RESET_VECBASE_OVERLAP	0
+
+#define XCHAL_RESET_VECTOR0_VADDR	0xFE000000
+#define XCHAL_RESET_VECTOR0_PADDR	0xFE000000
+#define XCHAL_RESET_VECTOR1_VADDR	0xD8000500
+#define XCHAL_RESET_VECTOR1_PADDR	0x00000500
+#define XCHAL_RESET_VECTOR_VADDR	0xFE000000
+#define XCHAL_RESET_VECTOR_PADDR	0xFE000000
+#define XCHAL_USER_VECOFS		0x00000340
+#define XCHAL_USER_VECTOR_VADDR		0xD0000340
+#define XCHAL_USER_VECTOR_PADDR		0x00000340
+#define XCHAL_KERNEL_VECOFS		0x00000300
+#define XCHAL_KERNEL_VECTOR_VADDR	0xD0000300
+#define XCHAL_KERNEL_VECTOR_PADDR	0x00000300
+#define XCHAL_DOUBLEEXC_VECOFS		0x000003C0
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0xD00003C0
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x000003C0
+#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
+#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
+#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
+#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
+#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
+#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
+#define XCHAL_WINDOW_VECTORS_VADDR	0xD0000000
+#define XCHAL_WINDOW_VECTORS_PADDR	0x00000000
+#define XCHAL_INTLEVEL2_VECOFS		0x00000180
+#define XCHAL_INTLEVEL2_VECTOR_VADDR	0xD0000180
+#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x00000180
+#define XCHAL_INTLEVEL3_VECOFS		0x000001C0
+#define XCHAL_INTLEVEL3_VECTOR_VADDR	0xD00001C0
+#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x000001C0
+#define XCHAL_INTLEVEL4_VECOFS		0x00000200
+#define XCHAL_INTLEVEL4_VECTOR_VADDR	0xD0000200
+#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x00000200
+#define XCHAL_INTLEVEL5_VECOFS		0x00000240
+#define XCHAL_INTLEVEL5_VECTOR_VADDR	0xD0000240
+#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x00000240
+#define XCHAL_INTLEVEL6_VECOFS		0x00000280
+#define XCHAL_INTLEVEL6_VECTOR_VADDR	0xD0000280
+#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x00000280
+#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS		0x000002C0
+#define XCHAL_NMI_VECTOR_VADDR		0xD00002C0
+#define XCHAL_NMI_VECTOR_PADDR		0x000002C0
+#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
+
+
+/*----------------------------------------------------------------------
+				DEBUG
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
+#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY	1	/* faster OCD option */
+
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*  See core-matmap.h header file for more details.  */
+
+#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY		0	/* one way maps I+D 4GB vaddr */
+#define XCHAL_HAVE_IDENTITY_MAP		0	/* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU		1	/* full MMU (with page table
+						   [autorefill] and protection)
+						   usable for an MMU-based OS */
+/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
+#define XCHAL_ITLB_ARF_ENTRIES_LOG2	2	/* log2(autorefill way size) */
+#define XCHAL_DTLB_ARF_ENTRIES_LOG2	2	/* log2(autorefill way size) */
+
+#define XCHAL_MMU_ASID_BITS		8	/* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS			4	/* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS		2	/* num of bits in RING field */
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
+
diff --git a/arch/xtensa/include/asm/arch-dc232b/tie-asm.h b/arch/xtensa/include/asm/arch-dc232b/tie-asm.h
new file mode 100644
index 0000000..05ce110
--- /dev/null
+++ b/arch/xtensa/include/asm/arch-dc232b/tie-asm.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header file contains assembly-language definitions (assembly
+ * macros, etc.) for this specific Xtensa processor's TIE extensions
+ * and options.  It is customized to this Xtensa processor configuration.
+ * This file is autogenerated, please do not edit.
+ *
+ * Copyright (C) 1999-2007 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CORE_TIE_ASM_H
+#define _XTENSA_CORE_TIE_ASM_H
+
+/*  Selection parameter values for save-area save/restore macros:  */
+/*  Option vs. TIE:  */
+#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
+#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
+/*  Whether used automatically by compiler:  */
+#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
+#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
+/*  ABI handling across function calls:  */
+#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
+#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
+#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
+/*  Misc  */
+#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
+
+
+
+/* Macro to save all non-coprocessor (extra) custom TIE and optional state
+ * (not including zero-overhead loop registers).
+ * Save area ptr (clobbered):  ptr  (1 byte aligned)
+ * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_NCP_NUM_ATMPS needed)
+ */
+	.macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
+	xchal_sa_start	\continue, \ofs
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-8, 4, 4
+	rsr	\at1, ACCLO		// MAC16 accumulator
+	rsr	\at2, ACCHI
+	s32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	s32i	\at2, \ptr, .Lxchal_ofs_ + 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-16, 4, 4
+	rsr	\at1, M0		// MAC16 registers
+	rsr	\at2, M1
+	s32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	s32i	\at2, \ptr, .Lxchal_ofs_ + 4
+	rsr	\at1, M2
+	rsr	\at2, M3
+	s32i	\at1, \ptr, .Lxchal_ofs_ + 8
+	s32i	\at2, \ptr, .Lxchal_ofs_ + 12
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 16
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-4, 4, 4
+	rsr	\at1, SCOMPARE1		// conditional store option
+	s32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-4, 4, 4
+	rur	\at1, THREADPTR		// threadptr option
+	s32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	.endm	// xchal_ncp_store
+
+/* Macro to save all non-coprocessor (extra) custom TIE and optional state
+ * (not including zero-overhead loop registers).
+ * Save area ptr (clobbered):  ptr  (1 byte aligned)
+ * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_NCP_NUM_ATMPS needed)
+ */
+	.macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
+	xchal_sa_start	\continue, \ofs
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-8, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	l32i	\at2, \ptr, .Lxchal_ofs_ + 4
+	wsr	\at1, ACCLO		// MAC16 accumulator
+	wsr	\at2, ACCHI
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-16, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	l32i	\at2, \ptr, .Lxchal_ofs_ + 4
+	wsr	\at1, M0		// MAC16 registers
+	wsr	\at2, M1
+	l32i	\at1, \ptr, .Lxchal_ofs_ + 8
+	l32i	\at2, \ptr, .Lxchal_ofs_ + 12
+	wsr	\at1, M2
+	wsr	\at2, M3
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 16
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-4, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	wsr	\at1, SCOMPARE1		// conditional store option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
+	xchal_sa_align	\ptr, 0, 1024-4, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_ + 0
+	wur	\at1, THREADPTR		// threadptr option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	.endm	// xchal_ncp_load
+
+
+
+#define XCHAL_NCP_NUM_ATMPS	2
+
+
+#define XCHAL_SA_NUM_ATMPS	2
+
+#endif /*_XTENSA_CORE_TIE_ASM_H*/
+
diff --git a/arch/xtensa/include/asm/arch-dc232b/tie.h b/arch/xtensa/include/asm/arch-dc232b/tie.h
new file mode 100644
index 0000000..2e70311
--- /dev/null
+++ b/arch/xtensa/include/asm/arch-dc232b/tie.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header file describes this specific Xtensa processor's TIE extensions
+ * that extend basic Xtensa core functionality.  It is customized to this
+ * Xtensa processor configuration.
+ * This file is autogenerated, please do not edit.
+ *
+ * Copyright (C) 1999-2007 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CORE_TIE_H
+#define _XTENSA_CORE_TIE_H
+
+#define XCHAL_CP_NUM			1	/* number of coprocessors */
+#define XCHAL_CP_MAX			8	/* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK			0x80	/* bitmask of all CPs by ID */
+#define XCHAL_CP_PORT_MASK		0x80	/* bitmask of only port CPs */
+
+/*  Basic parameters of each coprocessor:  */
+#define XCHAL_CP7_NAME			"XTIOP"
+#define XCHAL_CP7_IDENT			XTIOP
+#define XCHAL_CP7_SA_SIZE		0	/* size of state save area */
+#define XCHAL_CP7_SA_ALIGN		1	/* min alignment of save area */
+#define XCHAL_CP_ID_XTIOP		7	/* coprocessor ID (0..7) */
+
+/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
+#define XCHAL_CP0_SA_SIZE		0
+#define XCHAL_CP0_SA_ALIGN		1
+#define XCHAL_CP1_SA_SIZE		0
+#define XCHAL_CP1_SA_ALIGN		1
+#define XCHAL_CP2_SA_SIZE		0
+#define XCHAL_CP2_SA_ALIGN		1
+#define XCHAL_CP3_SA_SIZE		0
+#define XCHAL_CP3_SA_ALIGN		1
+#define XCHAL_CP4_SA_SIZE		0
+#define XCHAL_CP4_SA_ALIGN		1
+#define XCHAL_CP5_SA_SIZE		0
+#define XCHAL_CP5_SA_ALIGN		1
+#define XCHAL_CP6_SA_SIZE		0
+#define XCHAL_CP6_SA_ALIGN		1
+
+/*  Save area for non-coprocessor optional and custom (TIE) state:  */
+#define XCHAL_NCP_SA_SIZE		32
+#define XCHAL_NCP_SA_ALIGN		4
+
+/*  Total save area for optional and custom state (NCP + CPn):  */
+#define XCHAL_TOTAL_SA_SIZE		32	/* with 16-byte align padding */
+#define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */
+
+/*
+ * Detailed contents of save areas.
+ * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
+ * before expanding the XCHAL_xxx_SA_LIST() macros.
+ *
+ * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
+ *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
+ *
+ *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
+ *	ccused = set if used by compiler without special options or code
+ *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
+ *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
+ *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
+ *	name = lowercase reg name (no quotes)
+ *	galign = group byte alignment (power of 2) (galign >= align)
+ *	align = register byte alignment (power of 2)
+ *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
+ *	  (not including any pad bytes required to galign this or next reg)
+ *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
+ *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
+ *	regnum = reg index in regfile, or special/TIE-user reg number
+ *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
+ *	gapsz = intervening bits, if bitsz bits not stored contiguously
+ *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
+ *	reset = register reset value (or 0 if undefined at reset)
+ *	x = reserved for future use (0 until then)
+ *
+ *  To filter out certain registers, e.g. to expand only the non-global
+ *  registers used by the compiler, you can do something like this:
+ *
+ *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
+ *  #define SELCC0(p...)
+ *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
+ *  #define SELAK0(p...)		REG(p)
+ *  #define SELAK1(p...)		REG(p)
+ *  #define SELAK2(p...)
+ *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
+ *		...what you want to expand...
+ */
+
+#define XCHAL_NCP_SA_NUM	8
+#define XCHAL_NCP_SA_LIST(s)	\
+ XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
+ XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0) \
+ XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0)
+
+#define XCHAL_CP0_SA_NUM	0
+#define XCHAL_CP0_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP1_SA_NUM	0
+#define XCHAL_CP1_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP2_SA_NUM	0
+#define XCHAL_CP2_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP3_SA_NUM	0
+#define XCHAL_CP3_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP4_SA_NUM	0
+#define XCHAL_CP4_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP5_SA_NUM	0
+#define XCHAL_CP5_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP6_SA_NUM	0
+#define XCHAL_CP6_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP7_SA_NUM	0
+#define XCHAL_CP7_SA_LIST(s)	/* empty */
+
+/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
+#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
+
+#endif /*_XTENSA_CORE_TIE_H*/
+
diff --git a/arch/xtensa/include/asm/arch-dc233c/core.h b/arch/xtensa/include/asm/arch-dc233c/core.h
new file mode 100644
index 0000000..8a73455
--- /dev/null
+++ b/arch/xtensa/include/asm/arch-dc233c/core.h
@@ -0,0 +1,453 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Xtensa processor core configuration information.
+ * This file is autogenerated, please do not edit.
+ *
+ * Copyright (C) 1999-2010 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+
+/****************************************************************************
+	    Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ *  configured, and a value of 0 otherwise.  These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+				ISA
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
+#define XCHAL_NUM_AREGS			32	/* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2		5	/* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG		1	/* debug option */
+#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
+#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
+#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R			1	/* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS	1	/* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
+#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
+#define XCHAL_HAVE_ABS			1	/* ABS instruction */
+/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
+/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION		0	/* speculation */
+#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS		1	/* */
+#define XCHAL_NUM_MISC_REGS		2	/* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID			1	/* processor ID register */
+#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
+#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
+#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
+#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS		0	/* boolean registers */
+#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG			8	/* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16		1	/* MAC16 package */
+#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
+#define XCHAL_HAVE_FP			0	/* floating point pkg */
+#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
+#define XCHAL_HAVE_DFP_accel		0	/* double precision FP acceleration pkg */
+#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
+#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
+#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2EP	0	/* HiFi2EP */
+#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
+#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
+#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
+#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
+#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
+#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
+#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
+#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
+#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
+#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
+
+
+/*----------------------------------------------------------------------
+				MISC
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES	8	/* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH		4	/* data width in bytes */
+/*  In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
+#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
+#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
+
+#define XCHAL_SW_VERSION		900001	/* sw version of this header */
+
+#define XCHAL_CORE_ID			"dc233c"	/* alphanum core name
+						   (CoreID) set in the Xtensa
+						   Processor Generator */
+
+#define XCHAL_CORE_DESCRIPTION		"dc233c"
+#define XCHAL_BUILD_UNIQUE_ID		0x00004B21	/* 22-bit sw build ID */
+
+/*
+ *  These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0		0xC56707FE	/* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1		0x14404B21	/* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME		"LX4.0.1"	/* full version name */
+#define XCHAL_HW_VERSION_MAJOR		2400	/* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR		1	/* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION		240001	/* major*100+minor */
+#define XCHAL_HW_REL_LX4		1
+#define XCHAL_HW_REL_LX4_0		1
+#define XCHAL_HW_REL_LX4_0_1		1
+#define XCHAL_HW_CONFIGID_RELIABLE	1
+/*  If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR	2400	/* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR	1	/* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION		240001	/* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR	2400	/* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR	1	/* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION		240001	/* latest targeted hw */
+
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE		32	/* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE		32	/* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH		5	/* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH		5	/* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE		16384	/* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE		16384	/* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
+#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
+
+#define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
+
+
+
+
+/****************************************************************************
+    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
+
+/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
+
+/*  Number of cache sets in log2(lines per way):  */
+#define XCHAL_ICACHE_SETWIDTH		7
+#define XCHAL_DCACHE_SETWIDTH		7
+
+/*  Cache set associativity (number of ways):  */
+#define XCHAL_ICACHE_WAYS		4
+#define XCHAL_DCACHE_WAYS		4
+
+/*  Cache features:  */
+#define XCHAL_ICACHE_LINE_LOCKABLE	1
+#define XCHAL_DCACHE_LINE_LOCKABLE	1
+#define XCHAL_ICACHE_ECC_PARITY		0
+#define XCHAL_DCACHE_ECC_PARITY		0
+
+/*  Cache access size in bytes (affects operation of SICW instruction):  */
+#define XCHAL_ICACHE_ACCESS_SIZE	4
+#define XCHAL_DCACHE_ACCESS_SIZE	4
+
+/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
+#define XCHAL_CA_BITS			4
+
+
+/*----------------------------------------------------------------------
+			INTERNAL I/D RAM/ROMs and XLMI
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM		0	/* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
+#define XCHAL_NUM_DATARAM		0	/* number of core data RAMs */
+#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
+
+#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
+
+
+/*----------------------------------------------------------------------
+			INTERRUPTS and TIMERS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS		22	/* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS		17	/* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
+						   (not including level zero) */
+#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
+	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/*  Masks of interrupts at each interrupt level:  */
+#define XCHAL_INTLEVEL1_MASK		0x001F80FF
+#define XCHAL_INTLEVEL2_MASK		0x00000100
+#define XCHAL_INTLEVEL3_MASK		0x00200E00
+#define XCHAL_INTLEVEL4_MASK		0x00001000
+#define XCHAL_INTLEVEL5_MASK		0x00002000
+#define XCHAL_INTLEVEL6_MASK		0x00000000
+#define XCHAL_INTLEVEL7_MASK		0x00004000
+
+/*  Masks of interrupts at each range 1..n of interrupt levels:  */
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x001F80FF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x001F81FF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x003F8FFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x003F9FFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x003FBFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x003FBFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x003FFFFF
+
+/*  Level of each interrupt:  */
+#define XCHAL_INT0_LEVEL		1
+#define XCHAL_INT1_LEVEL		1
+#define XCHAL_INT2_LEVEL		1
+#define XCHAL_INT3_LEVEL		1
+#define XCHAL_INT4_LEVEL		1
+#define XCHAL_INT5_LEVEL		1
+#define XCHAL_INT6_LEVEL		1
+#define XCHAL_INT7_LEVEL		1
+#define XCHAL_INT8_LEVEL		2
+#define XCHAL_INT9_LEVEL		3
+#define XCHAL_INT10_LEVEL		3
+#define XCHAL_INT11_LEVEL		3
+#define XCHAL_INT12_LEVEL		4
+#define XCHAL_INT13_LEVEL		5
+#define XCHAL_INT14_LEVEL		7
+#define XCHAL_INT15_LEVEL		1
+#define XCHAL_INT16_LEVEL		1
+#define XCHAL_INT17_LEVEL		1
+#define XCHAL_INT18_LEVEL		1
+#define XCHAL_INT19_LEVEL		1
+#define XCHAL_INT20_LEVEL		1
+#define XCHAL_INT21_LEVEL		3
+#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
+#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
+						   EXCSAVE/EPS/EPC_n, RFI n) */
+
+/*  Type of each interrupt:  */
+#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+
+/*  Masks of interrupts for each type of interrupt:  */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFC00000
+#define XCHAL_INTTYPE_MASK_SOFTWARE	0x00000880
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x003F8000
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x0000133F
+#define XCHAL_INTTYPE_MASK_TIMER	0x00002440
+#define XCHAL_INTTYPE_MASK_NMI		0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
+
+/*  Interrupt numbers assigned to specific interrupt sources:  */
+#define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT		10	/* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT		13	/* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
+
+/*  Interrupt numbers for levels at which only one interrupt is configured:  */
+#define XCHAL_INTLEVEL2_NUM		8
+#define XCHAL_INTLEVEL4_NUM		12
+#define XCHAL_INTLEVEL5_NUM		13
+#define XCHAL_INTLEVEL7_NUM		14
+/*  (There are many interrupts each at level(s) 1, 3.)  */
+
+
+/*
+ *  External interrupt vectors/levels.
+ *  These macros describe how Xtensa processor interrupt numbers
+ *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ *  map to external BInterrupt<n> pins, for those interrupts
+ *  configured as external (level-triggered, edge-triggered, or NMI).
+ *  See the Xtensa processor databook for more details.
+ */
+
+/*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
+#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM		8	/* (intlevel 2) */
+#define XCHAL_EXTINT7_NUM		9	/* (intlevel 3) */
+#define XCHAL_EXTINT8_NUM		12	/* (intlevel 4) */
+#define XCHAL_EXTINT9_NUM		14	/* (intlevel 7) */
+#define XCHAL_EXTINT10_NUM		15	/* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM		16	/* (intlevel 1) */
+#define XCHAL_EXTINT12_NUM		17	/* (intlevel 1) */
+#define XCHAL_EXTINT13_NUM		18	/* (intlevel 1) */
+#define XCHAL_EXTINT14_NUM		19	/* (intlevel 1) */
+#define XCHAL_EXTINT15_NUM		20	/* (intlevel 1) */
+#define XCHAL_EXTINT16_NUM		21	/* (intlevel 3) */
+
+
+/*----------------------------------------------------------------------
+			EXCEPTIONS and VECTORS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
+						   number: 1 == XEA1 (old)
+							   2 == XEA2 (new)
+							   0 == XEAX (extern) or TX */
+#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
+#define XCHAL_HAVE_HALT			0	/* halt architecture option */
+#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
+#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
+#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR	0x00002000  /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR	0x00002000
+#define XCHAL_RESET_VECBASE_OVERLAP	0
+
+#define XCHAL_RESET_VECTOR0_VADDR	0xFE000000
+#define XCHAL_RESET_VECTOR0_PADDR	0xFE000000
+#define XCHAL_RESET_VECTOR1_VADDR	0x00001000
+#define XCHAL_RESET_VECTOR1_PADDR	0x00001000
+#define XCHAL_RESET_VECTOR_VADDR	0xFE000000
+#define XCHAL_RESET_VECTOR_PADDR	0xFE000000
+#define XCHAL_USER_VECOFS		0x00000340
+#define XCHAL_USER_VECTOR_VADDR		0x00002340
+#define XCHAL_USER_VECTOR_PADDR		0x00002340
+#define XCHAL_KERNEL_VECOFS		0x00000300
+#define XCHAL_KERNEL_VECTOR_VADDR	0x00002300
+#define XCHAL_KERNEL_VECTOR_PADDR	0x00002300
+#define XCHAL_DOUBLEEXC_VECOFS		0x000003C0
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x000023C0
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x000023C0
+#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
+#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
+#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
+#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
+#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
+#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
+#define XCHAL_WINDOW_VECTORS_VADDR	0x00002000
+#define XCHAL_WINDOW_VECTORS_PADDR	0x00002000
+#define XCHAL_INTLEVEL2_VECOFS		0x00000180
+#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x00002180
+#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x00002180
+#define XCHAL_INTLEVEL3_VECOFS		0x000001C0
+#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x000021C0
+#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x000021C0
+#define XCHAL_INTLEVEL4_VECOFS		0x00000200
+#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x00002200
+#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x00002200
+#define XCHAL_INTLEVEL5_VECOFS		0x00000240
+#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x00002240
+#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x00002240
+#define XCHAL_INTLEVEL6_VECOFS		0x00000280
+#define XCHAL_INTLEVEL6_VECTOR_VADDR	0x00002280
+#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x00002280
+#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS		0x000002C0
+#define XCHAL_NMI_VECTOR_VADDR		0x000022C0
+#define XCHAL_NMI_VECTOR_PADDR		0x000022C0
+#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
+
+
+/*----------------------------------------------------------------------
+				DEBUG
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
+#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY	1	/* faster OCD option */
+
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*  See core-matmap.h header file for more details.  */
+
+#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
+#define XCHAL_SPANNING_WAY		6	/* TLB spanning way number */
+#define XCHAL_HAVE_IDENTITY_MAP		0	/* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR	0	/* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU		1	/* full MMU (with page table
+						   [autorefill] and protection)
+						   usable for an MMU-based OS */
+/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
+#define XCHAL_ITLB_ARF_ENTRIES_LOG2	2	/* log2(autorefill way size) */
+#define XCHAL_DTLB_ARF_ENTRIES_LOG2	2	/* log2(autorefill way size) */
+
+#define XCHAL_MMU_ASID_BITS		8	/* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS			4	/* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS		2	/* num of bits in RING field */
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
+
diff --git a/arch/xtensa/include/asm/arch-dc233c/tie-asm.h b/arch/xtensa/include/asm/arch-dc233c/tie-asm.h
new file mode 100644
index 0000000..53a1e42
--- /dev/null
+++ b/arch/xtensa/include/asm/arch-dc233c/tie-asm.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header file contains assembly-language definitions (assembly
+ * macros, etc.) for this specific Xtensa processor's TIE extensions
+ * and options.  It is customized to this Xtensa processor configuration.
+ * This file is autogenerated, please do not edit.
+ *
+ * Copyright (C) 1999-2010 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CORE_TIE_ASM_H
+#define _XTENSA_CORE_TIE_ASM_H
+
+/*  Selection parameter values for save-area save/restore macros:  */
+/*  Option vs. TIE:  */
+#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
+#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
+#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
+/*  Whether used automatically by compiler:  */
+#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
+#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
+#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
+/*  ABI handling across function calls:  */
+#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
+#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
+#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
+#define XTHAL_SAS_ANYABI 0x0070	/* all of the above three */
+/*  Misc  */
+#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
+#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
+					| ((ccuse) & XTHAL_SAS_ANYCC)  \
+					| ((abi)   & XTHAL_SAS_ANYABI) )
+
+
+
+    /*
+     *  Macro to save all non-coprocessor (extra) custom TIE and optional state
+     *  (not including zero-overhead loop registers).
+     *  Required parameters:
+     *      ptr		Save area pointer address register (clobbered)
+     *			(register must contain a 4 byte aligned address).
+     *      at1..at4	Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+     *			registers are clobbered, the remaining are unused).
+     *  Optional parameters:
+     *      continue	If macro invoked as part of a larger store sequence, set to 1
+     *			if this is not the first in the sequence.  Defaults to 0.
+     *      ofs		Offset from start of larger sequence (from value of first ptr
+     *			in sequence) at which to store.  Defaults to next available space
+     *			(or 0 if <continue> is 0).
+     *      select	Select what category(ies) of registers to store, as a bitmask
+     *			(see XTHAL_SAS_xxx constants).  Defaults to all registers.
+     *      alloc	Select what category(ies) of registers to allocate; if any
+     *			category is selected here that is not in <select>, space for
+     *			the corresponding registers is skipped without doing any store.
+     */
+    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+	xchal_sa_start	\continue, \ofs
+	// Optional global register used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1020, 4, 4
+	rur.THREADPTR	\at1		// threadptr option
+	s32i	\at1, \ptr, .Lxchal_ofs_+0
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1020, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	// Optional caller-saved registers used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	rsr	\at1, ACCLO			// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+0
+	rsr	\at1, ACCHI			// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.endif
+	// Optional caller-saved registers not used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1004, 4, 4
+	rsr	\at1, M0			// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+0
+	rsr	\at1, M1			// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+4
+	rsr	\at1, M2			// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+8
+	rsr	\at1, M3			// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+12
+	rsr	\at1, SCOMPARE1			// conditional store option
+	s32i	\at1, \ptr, .Lxchal_ofs_+16
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 20
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1004, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 20
+	.endif
+    .endm	// xchal_ncp_store
+
+    /*
+     *  Macro to restore all non-coprocessor (extra) custom TIE and optional state
+     *  (not including zero-overhead loop registers).
+     *  Required parameters:
+     *      ptr		Save area pointer address register (clobbered)
+     *			(register must contain a 4 byte aligned address).
+     *      at1..at4	Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+     *			registers are clobbered, the remaining are unused).
+     *  Optional parameters:
+     *      continue	If macro invoked as part of a larger load sequence, set to 1
+     *			if this is not the first in the sequence.  Defaults to 0.
+     *      ofs		Offset from start of larger sequence (from value of first ptr
+     *			in sequence) at which to load.  Defaults to next available space
+     *			(or 0 if <continue> is 0).
+     *      select	Select what category(ies) of registers to load, as a bitmask
+     *			(see XTHAL_SAS_xxx constants).  Defaults to all registers.
+     *      alloc	Select what category(ies) of registers to allocate; if any
+     *			category is selected here that is not in <select>, space for
+     *			the corresponding registers is skipped without doing any load.
+     */
+    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+	xchal_sa_start	\continue, \ofs
+	// Optional global register used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1020, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_+0
+	wur.THREADPTR	\at1		// threadptr option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1020, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	// Optional caller-saved registers used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_+0
+	wsr	\at1, ACCLO			// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+4
+	wsr	\at1, ACCHI			// MAC16 option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.endif
+	// Optional caller-saved registers not used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1004, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_+0
+	wsr	\at1, M0			// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+4
+	wsr	\at1, M1			// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+8
+	wsr	\at1, M2			// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+12
+	wsr	\at1, M3			// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+16
+	wsr	\at1, SCOMPARE1			// conditional store option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 20
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1004, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 20
+	.endif
+    .endm	// xchal_ncp_load
+
+
+#define XCHAL_NCP_NUM_ATMPS	1
+
+
+
+#define XCHAL_SA_NUM_ATMPS	1
+
+#endif /*_XTENSA_CORE_TIE_ASM_H*/
+
diff --git a/arch/xtensa/include/asm/arch-dc233c/tie.h b/arch/xtensa/include/asm/arch-dc233c/tie.h
new file mode 100644
index 0000000..ddee4ad
--- /dev/null
+++ b/arch/xtensa/include/asm/arch-dc233c/tie.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header file describes this specific Xtensa processor's TIE extensions
+ * that extend basic Xtensa core functionality.  It is customized to this
+ * Xtensa processor configuration.
+ * This file is autogenerated, please do not edit.
+ *
+ * Copyright (C) 1999-2010 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CORE_TIE_H
+#define _XTENSA_CORE_TIE_H
+
+#define XCHAL_CP_NUM			1	/* number of coprocessors */
+#define XCHAL_CP_MAX			8	/* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK			0x80	/* bitmask of all CPs by ID */
+#define XCHAL_CP_PORT_MASK		0x80	/* bitmask of only port CPs */
+
+/*  Basic parameters of each coprocessor:  */
+#define XCHAL_CP7_NAME			"XTIOP"
+#define XCHAL_CP7_IDENT			XTIOP
+#define XCHAL_CP7_SA_SIZE		0	/* size of state save area */
+#define XCHAL_CP7_SA_ALIGN		1	/* min alignment of save area */
+#define XCHAL_CP_ID_XTIOP		7	/* coprocessor ID (0..7) */
+
+/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
+#define XCHAL_CP0_SA_SIZE		0
+#define XCHAL_CP0_SA_ALIGN		1
+#define XCHAL_CP1_SA_SIZE		0
+#define XCHAL_CP1_SA_ALIGN		1
+#define XCHAL_CP2_SA_SIZE		0
+#define XCHAL_CP2_SA_ALIGN		1
+#define XCHAL_CP3_SA_SIZE		0
+#define XCHAL_CP3_SA_ALIGN		1
+#define XCHAL_CP4_SA_SIZE		0
+#define XCHAL_CP4_SA_ALIGN		1
+#define XCHAL_CP5_SA_SIZE		0
+#define XCHAL_CP5_SA_ALIGN		1
+#define XCHAL_CP6_SA_SIZE		0
+#define XCHAL_CP6_SA_ALIGN		1
+
+/*  Save area for non-coprocessor optional and custom (TIE) state:  */
+#define XCHAL_NCP_SA_SIZE		32
+#define XCHAL_NCP_SA_ALIGN		4
+
+/*  Total save area for optional and custom state (NCP + CPn):  */
+#define XCHAL_TOTAL_SA_SIZE		32	/* with 16-byte align padding */
+#define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */
+
+/*
+ * Detailed contents of save areas.
+ * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
+ * before expanding the XCHAL_xxx_SA_LIST() macros.
+ *
+ * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
+ *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
+ *
+ *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
+ *	ccused = set if used by compiler without special options or code
+ *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
+ *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
+ *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
+ *	name = lowercase reg name (no quotes)
+ *	galign = group byte alignment (power of 2) (galign >= align)
+ *	align = register byte alignment (power of 2)
+ *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
+ *	  (not including any pad bytes required to galign this or next reg)
+ *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
+ *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
+ *	regnum = reg index in regfile, or special/TIE-user reg number
+ *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
+ *	gapsz = intervening bits, if bitsz bits not stored contiguously
+ *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
+ *	reset = register reset value (or 0 if undefined at reset)
+ *	x = reserved for future use (0 until then)
+ *
+ *  To filter out certain registers, e.g. to expand only the non-global
+ *  registers used by the compiler, you can do something like this:
+ *
+ *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
+ *  #define SELCC0(p...)
+ *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
+ *  #define SELAK0(p...)		REG(p)
+ *  #define SELAK1(p...)		REG(p)
+ *  #define SELAK2(p...)
+ *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
+ *		...what you want to expand...
+ */
+
+#define XCHAL_NCP_SA_NUM	8
+#define XCHAL_NCP_SA_LIST(s)	\
+ XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \
+ XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
+ XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0)
+
+#define XCHAL_CP0_SA_NUM	0
+#define XCHAL_CP0_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP1_SA_NUM	0
+#define XCHAL_CP1_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP2_SA_NUM	0
+#define XCHAL_CP2_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP3_SA_NUM	0
+#define XCHAL_CP3_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP4_SA_NUM	0
+#define XCHAL_CP4_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP5_SA_NUM	0
+#define XCHAL_CP5_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP6_SA_NUM	0
+#define XCHAL_CP6_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP7_SA_NUM	0
+#define XCHAL_CP7_SA_LIST(s)	/* empty */
+
+/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
+#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
+
+#endif /*_XTENSA_CORE_TIE_H*/
+
diff --git a/arch/xtensa/include/asm/arch-de212/core.h b/arch/xtensa/include/asm/arch-de212/core.h
new file mode 100644
index 0000000..7e94339
--- /dev/null
+++ b/arch/xtensa/include/asm/arch-de212/core.h
@@ -0,0 +1,572 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Xtensa processor core configuration information.
+ * This file is autogenerated, please do not edit.
+ *
+ * Copyright (C) 1999-2015 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+
+/****************************************************************************
+	    Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ *  configured, and a value of 0 otherwise.  These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+				ISA
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
+#define XCHAL_NUM_AREGS			32	/* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2		5	/* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG		1	/* debug option */
+#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
+#define XCHAL_LOOP_BUFFER_SIZE		0	/* zero-ov. loop instr buffer size */
+#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
+#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
+#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R			1	/* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
+#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
+#define XCHAL_HAVE_ABS			1	/* ABS instruction */
+/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
+/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION		0	/* speculation */
+#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS		1	/* */
+#define XCHAL_NUM_MISC_REGS		2	/* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID			1	/* processor ID register */
+#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
+#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
+#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
+#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
+#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
+#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
+#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
+#define XCHAL_HAVE_THREADPTR		0	/* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS		0	/* boolean registers */
+#define XCHAL_HAVE_CP			0	/* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG			0	/* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16		1	/* MAC16 package */
+
+#define XCHAL_HAVE_FUSION		 0	/* Fusion*/
+#define XCHAL_HAVE_FUSION_FP	 0	        /* Fusion FP option */
+#define XCHAL_HAVE_FUSION_LOW_POWER 0	/* Fusion Low Power option */
+#define XCHAL_HAVE_FUSION_AES	 0	        /* Fusion BLE/Wifi AES-128 CCM option */
+#define XCHAL_HAVE_FUSION_CONVENC	 0       /* Fusion Conv Encode option */
+#define XCHAL_HAVE_FUSION_LFSR_CRC	 0	/* Fusion LFSR-CRC option */
+#define XCHAL_HAVE_FUSION_BITOPS	 0	/* Fusion Bit Operations Support option */
+#define XCHAL_HAVE_FUSION_AVS	 0	/* Fusion AVS option */
+#define XCHAL_HAVE_FUSION_16BIT_BASEBAND	 0	/* Fusion 16-bit Baseband option */
+#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4_VFPU		0	/* HiFi4 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3		0	/* HiFi3 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
+#define XCHAL_HAVE_HIFI_MINI		0	
+
+
+#define XCHAL_HAVE_VECTORFPU2005	0	/* vector or user floating-point pkg */
+#define XCHAL_HAVE_USER_DPFPU         0       /* user DP floating-point pkg */
+#define XCHAL_HAVE_USER_SPFPU         0       /* user DP floating-point pkg */
+#define XCHAL_HAVE_FP                 0      /* single prec floating point */
+#define XCHAL_HAVE_FP_DIV             0  /* FP with DIV instructions */
+#define XCHAL_HAVE_FP_RECIP           0        /* FP with RECIP instructions */
+#define XCHAL_HAVE_FP_SQRT            0 /* FP with SQRT instructions */
+#define XCHAL_HAVE_FP_RSQRT           0        /* FP with RSQRT instructions */
+#define XCHAL_HAVE_DFP                        0     /* double precision FP pkg */
+#define XCHAL_HAVE_DFP_DIV            0 /* DFP with DIV instructions */
+#define XCHAL_HAVE_DFP_RECIP          0       /* DFP with RECIP instructions*/
+#define XCHAL_HAVE_DFP_SQRT           0        /* DFP with SQRT instructions */
+#define XCHAL_HAVE_DFP_RSQRT          0       /* DFP with RSQRT instructions*/
+#define XCHAL_HAVE_DFP_ACCEL		0	/* double precision FP acceleration pkg */
+#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL				/* for backward compatibility */
+
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY    0                 	/* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE  0               	/* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
+#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
+#define XCHAL_HAVE_PDX4		        0	/* PDX4 */
+#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
+#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
+#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
+#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
+#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
+#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
+#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
+#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
+#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
+#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
+#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
+#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
+#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
+#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
+#define XCHAL_HAVE_GRIVPEP              0   /*  GRIVPEP is General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0   /* Histogram option on GRIVPEP */
+
+
+/*----------------------------------------------------------------------
+				MISC
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_LOADSTORE_UNITS	1	/* load/store units */
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES	8	/* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH		4	/* data width in bytes */
+#define XCHAL_DATA_PIPE_DELAY		1	/* d-side pipeline delay
+						   (1 = 5-stage, 2 = 7-stage) */
+#define XCHAL_CLOCK_GATING_GLOBAL	0	/* global clock gating */
+#define XCHAL_CLOCK_GATING_FUNCUNIT	0	/* funct. unit clock gating */
+/*  In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
+#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
+#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
+
+#define XCHAL_SW_VERSION		1100002	/* sw version of this header */
+
+#define XCHAL_CORE_ID			"de212"	/* alphanum core name
+						   (CoreID) set in the Xtensa
+						   Processor Generator */
+
+#define XCHAL_BUILD_UNIQUE_ID		0x0005A985	/* 22-bit sw build ID */
+
+/*
+ *  These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0		0xC283DFFE	/* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1		0x1C85A985	/* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME		"LX6.0.2"	/* full version name */
+#define XCHAL_HW_VERSION_MAJOR		2600	/* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR		2	/* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION		260002	/* major*100+minor */
+#define XCHAL_HW_REL_LX6		1
+#define XCHAL_HW_REL_LX6_0		1
+#define XCHAL_HW_REL_LX6_0_2		1
+#define XCHAL_HW_CONFIGID_RELIABLE	1
+/*  If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR	2600	/* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR	2	/* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION		260002	/* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR	2600	/* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR	2	/* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION		260002	/* latest targeted hw */
+
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE		32	/* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE		32	/* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH		5	/* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH		5	/* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE		8192	/* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE		8192	/* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
+#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
+
+#define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
+#define XCHAL_HAVE_PREFETCH_L1		0	/* prefetch to L1 dcache */
+#define XCHAL_PREFETCH_CASTOUT_LINES	0	/* dcache pref. castout bufsz */
+#define XCHAL_PREFETCH_ENTRIES		0	/* cache prefetch entries */
+#define XCHAL_PREFETCH_BLOCK_ENTRIES	0	/* prefetch block streams */
+#define XCHAL_HAVE_CACHE_BLOCKOPS	0	/* block prefetch for caches */
+#define XCHAL_HAVE_ICACHE_TEST		1	/* Icache test instructions */
+#define XCHAL_HAVE_DCACHE_TEST		1	/* Dcache test instructions */
+#define XCHAL_HAVE_ICACHE_DYN_WAYS	0	/* Icache dynamic way support */
+#define XCHAL_HAVE_DCACHE_DYN_WAYS	0	/* Dcache dynamic way support */
+
+
+
+
+/****************************************************************************
+    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
+
+/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
+
+/*  Number of cache sets in log2(lines per way):  */
+#define XCHAL_ICACHE_SETWIDTH		7
+#define XCHAL_DCACHE_SETWIDTH		7
+
+/*  Cache set associativity (number of ways):  */
+#define XCHAL_ICACHE_WAYS		2
+#define XCHAL_DCACHE_WAYS		2
+
+/*  Cache features:  */
+#define XCHAL_ICACHE_LINE_LOCKABLE	1
+#define XCHAL_DCACHE_LINE_LOCKABLE	1
+#define XCHAL_ICACHE_ECC_PARITY		0
+#define XCHAL_DCACHE_ECC_PARITY		0
+
+/*  Cache access size in bytes (affects operation of SICW instruction):  */
+#define XCHAL_ICACHE_ACCESS_SIZE	4
+#define XCHAL_DCACHE_ACCESS_SIZE	4
+
+#define XCHAL_DCACHE_BANKS		1	/* number of banks */
+
+/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
+#define XCHAL_CA_BITS			4
+
+/*  Whether MEMCTL register has anything useful  */
+#define XCHAL_USE_MEMCTL		(((XCHAL_LOOP_BUFFER_SIZE > 0)	||	\
+					   XCHAL_DCACHE_IS_COHERENT	||	\
+					   XCHAL_HAVE_ICACHE_DYN_WAYS	||	\
+					   XCHAL_HAVE_DCACHE_DYN_WAYS)	&&	\
+					   (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
+
+
+/*----------------------------------------------------------------------
+			INTERNAL I/D RAM/ROMs and XLMI
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_INSTROM		0	/* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM		1	/* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM		0	/* number of core data ROMs */
+#define XCHAL_NUM_DATARAM		1	/* number of core data RAMs */
+#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI			1	/* number of core XLMI ports */
+
+/*  Instruction RAM 0:  */
+#define XCHAL_INSTRAM0_VADDR		0x40000000	/* virtual address */
+#define XCHAL_INSTRAM0_PADDR		0x40000000	/* physical address */
+#define XCHAL_INSTRAM0_SIZE		131072	/* size in bytes */
+#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+/*  Data RAM 0:  */
+#define XCHAL_DATARAM0_VADDR		0x3FFE0000	/* virtual address */
+#define XCHAL_DATARAM0_PADDR		0x3FFE0000	/* physical address */
+#define XCHAL_DATARAM0_SIZE		131072	/* size in bytes */
+#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_DATARAM0_BANKS		1	/* number of banks */
+
+/*  XLMI Port 0:  */
+#define XCHAL_XLMI0_VADDR		0x3FFC0000	/* virtual address */
+#define XCHAL_XLMI0_PADDR		0x3FFC0000	/* physical address */
+#define XCHAL_XLMI0_SIZE		131072	/* size in bytes */
+#define XCHAL_XLMI0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
+
+
+/*----------------------------------------------------------------------
+			INTERRUPTS and TIMERS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS		22	/* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS		17	/* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
+						   (not including level zero) */
+#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
+	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/*  Masks of interrupts at each interrupt level:  */
+#define XCHAL_INTLEVEL1_MASK		0x001F80FF
+#define XCHAL_INTLEVEL2_MASK		0x00000100
+#define XCHAL_INTLEVEL3_MASK		0x00200E00
+#define XCHAL_INTLEVEL4_MASK		0x00001000
+#define XCHAL_INTLEVEL5_MASK		0x00002000
+#define XCHAL_INTLEVEL6_MASK		0x00000000
+#define XCHAL_INTLEVEL7_MASK		0x00004000
+
+/*  Masks of interrupts at each range 1..n of interrupt levels:  */
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x001F80FF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x001F81FF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x003F8FFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x003F9FFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x003FBFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x003FBFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x003FFFFF
+
+/*  Level of each interrupt:  */
+#define XCHAL_INT0_LEVEL		1
+#define XCHAL_INT1_LEVEL		1
+#define XCHAL_INT2_LEVEL		1
+#define XCHAL_INT3_LEVEL		1
+#define XCHAL_INT4_LEVEL		1
+#define XCHAL_INT5_LEVEL		1
+#define XCHAL_INT6_LEVEL		1
+#define XCHAL_INT7_LEVEL		1
+#define XCHAL_INT8_LEVEL		2
+#define XCHAL_INT9_LEVEL		3
+#define XCHAL_INT10_LEVEL		3
+#define XCHAL_INT11_LEVEL		3
+#define XCHAL_INT12_LEVEL		4
+#define XCHAL_INT13_LEVEL		5
+#define XCHAL_INT14_LEVEL		7
+#define XCHAL_INT15_LEVEL		1
+#define XCHAL_INT16_LEVEL		1
+#define XCHAL_INT17_LEVEL		1
+#define XCHAL_INT18_LEVEL		1
+#define XCHAL_INT19_LEVEL		1
+#define XCHAL_INT20_LEVEL		1
+#define XCHAL_INT21_LEVEL		3
+#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
+#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
+						   EXCSAVE/EPS/EPC_n, RFI n) */
+
+/*  Type of each interrupt:  */
+#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+
+/*  Masks of interrupts for each type of interrupt:  */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFC00000
+#define XCHAL_INTTYPE_MASK_SOFTWARE	0x00000880
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x003F8000
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x0000133F
+#define XCHAL_INTTYPE_MASK_TIMER	0x00002440
+#define XCHAL_INTTYPE_MASK_NMI		0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
+#define XCHAL_INTTYPE_MASK_PROFILING	0x00000000
+
+/*  Interrupt numbers assigned to specific interrupt sources:  */
+#define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT		10	/* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT		13	/* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
+
+/*  Interrupt numbers for levels at which only one interrupt is configured:  */
+#define XCHAL_INTLEVEL2_NUM		8
+#define XCHAL_INTLEVEL4_NUM		12
+#define XCHAL_INTLEVEL5_NUM		13
+#define XCHAL_INTLEVEL7_NUM		14
+/*  (There are many interrupts each at level(s) 1, 3.)  */
+
+
+/*
+ *  External interrupt mapping.
+ *  These macros describe how Xtensa processor interrupt numbers
+ *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ *  map to external BInterrupt<n> pins, for those interrupts
+ *  configured as external (level-triggered, edge-triggered, or NMI).
+ *  See the Xtensa processor databook for more details.
+ */
+
+/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
+#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM		8	/* (intlevel 2) */
+#define XCHAL_EXTINT7_NUM		9	/* (intlevel 3) */
+#define XCHAL_EXTINT8_NUM		12	/* (intlevel 4) */
+#define XCHAL_EXTINT9_NUM		14	/* (intlevel 7) */
+#define XCHAL_EXTINT10_NUM		15	/* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM		16	/* (intlevel 1) */
+#define XCHAL_EXTINT12_NUM		17	/* (intlevel 1) */
+#define XCHAL_EXTINT13_NUM		18	/* (intlevel 1) */
+#define XCHAL_EXTINT14_NUM		19	/* (intlevel 1) */
+#define XCHAL_EXTINT15_NUM		20	/* (intlevel 1) */
+#define XCHAL_EXTINT16_NUM		21	/* (intlevel 3) */
+/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
+#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
+#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
+#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
+#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
+#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
+#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
+#define XCHAL_INT8_EXTNUM		6	/* (intlevel 2) */
+#define XCHAL_INT9_EXTNUM		7	/* (intlevel 3) */
+#define XCHAL_INT12_EXTNUM		8	/* (intlevel 4) */
+#define XCHAL_INT14_EXTNUM		9	/* (intlevel 7) */
+#define XCHAL_INT15_EXTNUM		10	/* (intlevel 1) */
+#define XCHAL_INT16_EXTNUM		11	/* (intlevel 1) */
+#define XCHAL_INT17_EXTNUM		12	/* (intlevel 1) */
+#define XCHAL_INT18_EXTNUM		13	/* (intlevel 1) */
+#define XCHAL_INT19_EXTNUM		14	/* (intlevel 1) */
+#define XCHAL_INT20_EXTNUM		15	/* (intlevel 1) */
+#define XCHAL_INT21_EXTNUM		16	/* (intlevel 3) */
+
+
+/*----------------------------------------------------------------------
+			EXCEPTIONS and VECTORS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
+						   number: 1 == XEA1 (old)
+							   2 == XEA2 (new)
+							   0 == XEAX (extern) or TX */
+#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
+#define XCHAL_HAVE_HALT			0	/* halt architecture option */
+#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
+#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
+#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR	0x60000000  /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR	0x60000000
+#define XCHAL_RESET_VECBASE_OVERLAP	0
+
+#define XCHAL_RESET_VECTOR0_VADDR	0x50000000
+#define XCHAL_RESET_VECTOR0_PADDR	0x50000000
+#define XCHAL_RESET_VECTOR1_VADDR	0x40000400
+#define XCHAL_RESET_VECTOR1_PADDR	0x40000400
+#define XCHAL_RESET_VECTOR_VADDR	0x50000000
+#define XCHAL_RESET_VECTOR_PADDR	0x50000000
+#define XCHAL_USER_VECOFS		0x00000340
+#define XCHAL_USER_VECTOR_VADDR		0x60000340
+#define XCHAL_USER_VECTOR_PADDR		0x60000340
+#define XCHAL_KERNEL_VECOFS		0x00000300
+#define XCHAL_KERNEL_VECTOR_VADDR	0x60000300
+#define XCHAL_KERNEL_VECTOR_PADDR	0x60000300
+#define XCHAL_DOUBLEEXC_VECOFS		0x000003C0
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x600003C0
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x600003C0
+#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
+#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
+#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
+#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
+#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
+#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
+#define XCHAL_WINDOW_VECTORS_VADDR	0x60000000
+#define XCHAL_WINDOW_VECTORS_PADDR	0x60000000
+#define XCHAL_INTLEVEL2_VECOFS		0x00000180
+#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x60000180
+#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x60000180
+#define XCHAL_INTLEVEL3_VECOFS		0x000001C0
+#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x600001C0
+#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x600001C0
+#define XCHAL_INTLEVEL4_VECOFS		0x00000200
+#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x60000200
+#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x60000200
+#define XCHAL_INTLEVEL5_VECOFS		0x00000240
+#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x60000240
+#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x60000240
+#define XCHAL_INTLEVEL6_VECOFS		0x00000280
+#define XCHAL_INTLEVEL6_VECTOR_VADDR	0x60000280
+#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x60000280
+#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS		0x000002C0
+#define XCHAL_NMI_VECTOR_VADDR		0x600002C0
+#define XCHAL_NMI_VECTOR_PADDR		0x600002C0
+#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
+
+
+/*----------------------------------------------------------------------
+				DEBUG MODULE
+  ----------------------------------------------------------------------*/
+
+/*  Misc  */
+#define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
+#define XCHAL_HAVE_DEBUG_APB		0	/* APB to debug module */
+#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
+
+/*  On-Chip Debug (OCD)  */
+#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
+#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
+#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
+
+/*  TRAX (in core)  */
+#define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
+#define XCHAL_TRAX_MEM_SIZE		262144	/* TRAX memory size in bytes */
+#define XCHAL_TRAX_MEM_SHAREABLE	0	/* start/end regs; ready sig. */
+#define XCHAL_TRAX_ATB_WIDTH		0	/* ATB width (bits), 0=no ATB */
+#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
+
+/*  Perf counters  */
+#define XCHAL_NUM_PERF_COUNTERS		0	/* performance counters */
+
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*  See core-matmap.h header file for more details.  */
+
+#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
+#define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
+#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR	1	/* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
+						   [autorefill] and protection)
+						   usable for an MMU-based OS */
+/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
+
+#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
+
diff --git a/arch/xtensa/include/asm/arch-de212/tie-asm.h b/arch/xtensa/include/asm/arch-de212/tie-asm.h
new file mode 100644
index 0000000..988aa2b
--- /dev/null
+++ b/arch/xtensa/include/asm/arch-de212/tie-asm.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header file contains assembly-language definitions (assembly
+ * macros, etc.) for this specific Xtensa processor's TIE extensions
+ * and options.  It is customized to this Xtensa processor configuration.
+ * This file is autogenerated, please do not edit.
+ *
+ * Copyright (C) 1999-2015 Cadence Design Systems Inc.
+ */
+
+#ifndef _XTENSA_CORE_TIE_ASM_H
+#define _XTENSA_CORE_TIE_ASM_H
+
+/*  Selection parameter values for save-area save/restore macros:  */
+/*  Option vs. TIE:  */
+#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
+#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
+#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
+/*  Whether used automatically by compiler:  */
+#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
+#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
+#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
+/*  ABI handling across function calls:  */
+#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
+#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
+#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
+#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
+/*  Misc  */
+#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
+#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
+					| ((ccuse) & XTHAL_SAS_ANYCC)  \
+					| ((abi)   & XTHAL_SAS_ANYABI) )
+
+
+    /*
+      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
+      *  (not including zero-overhead loop registers).
+      *  Required parameters:
+      *      ptr         Save area pointer address register (clobbered)
+      *                  (register must contain a 4 byte aligned address).
+      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+      *                  registers are clobbered, the remaining are unused).
+      *  Optional parameters:
+      *      continue    If macro invoked as part of a larger store sequence, set to 1
+      *                  if this is not the first in the sequence.  Defaults to 0.
+      *      ofs         Offset from start of larger sequence (from value of first ptr
+      *                  in sequence) at which to store.  Defaults to next available space
+      *                  (or 0 if <continue> is 0).
+      *      select      Select what category(ies) of registers to store, as a bitmask
+      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
+      *      alloc       Select what category(ies) of registers to allocate; if any
+      *                  category is selected here that is not in <select>, space for
+      *                  the corresponding registers is skipped without doing any store.
+      */
+    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+	xchal_sa_start	\continue, \ofs
+	// Optional caller-saved registers used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	rsr.ACCLO	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+0
+	rsr.ACCHI	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.endif
+	// Optional caller-saved registers not used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1004, 4, 4
+	rsr.SCOMPARE1	\at1		// conditional store option
+	s32i	\at1, \ptr, .Lxchal_ofs_+0
+	rsr.M0	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+4
+	rsr.M1	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+8
+	rsr.M2	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+12
+	rsr.M3	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+16
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 20
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1004, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 20
+	.endif
+    .endm	// xchal_ncp_store
+
+    /*
+      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
+      *  (not including zero-overhead loop registers).
+      *  Required parameters:
+      *      ptr         Save area pointer address register (clobbered)
+      *                  (register must contain a 4 byte aligned address).
+      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+      *                  registers are clobbered, the remaining are unused).
+      *  Optional parameters:
+      *      continue    If macro invoked as part of a larger load sequence, set to 1
+      *                  if this is not the first in the sequence.  Defaults to 0.
+      *      ofs         Offset from start of larger sequence (from value of first ptr
+      *                  in sequence) at which to load.  Defaults to next available space
+      *                  (or 0 if <continue> is 0).
+      *      select      Select what category(ies) of registers to load, as a bitmask
+      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
+      *      alloc       Select what category(ies) of registers to allocate; if any
+      *                  category is selected here that is not in <select>, space for
+      *                  the corresponding registers is skipped without doing any load.
+      */
+    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+	xchal_sa_start	\continue, \ofs
+	// Optional caller-saved registers used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_+0
+	wsr.ACCLO	\at1		// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+4
+	wsr.ACCHI	\at1		// MAC16 option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.endif
+	// Optional caller-saved registers not used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1004, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_+0
+	wsr.SCOMPARE1	\at1		// conditional store option
+	l32i	\at1, \ptr, .Lxchal_ofs_+4
+	wsr.M0	\at1		// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+8
+	wsr.M1	\at1		// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+12
+	wsr.M2	\at1		// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+16
+	wsr.M3	\at1		// MAC16 option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 20
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1004, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 20
+	.endif
+    .endm	// xchal_ncp_load
+
+
+#define XCHAL_NCP_NUM_ATMPS	1
+
+#define XCHAL_SA_NUM_ATMPS	1
+
+#endif /*_XTENSA_CORE_TIE_ASM_H*/
+
diff --git a/arch/xtensa/include/asm/arch-de212/tie.h b/arch/xtensa/include/asm/arch-de212/tie.h
new file mode 100644
index 0000000..2f36493
--- /dev/null
+++ b/arch/xtensa/include/asm/arch-de212/tie.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header file describes this specific Xtensa processor's TIE extensions
+ * that extend basic Xtensa core functionality.  It is customized to this
+ * Xtensa processor configuration.
+ * This file is autogenerated, please do not edit.
+ *
+ * Copyright (C) 1999-2015 Cadence Design Systems Inc.
+ */
+
+#ifndef _XTENSA_CORE_TIE_H
+#define _XTENSA_CORE_TIE_H
+
+#define XCHAL_CP_NUM			0	/* number of coprocessors */
+#define XCHAL_CP_MAX			0	/* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK			0x00	/* bitmask of all CPs by ID */
+#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
+
+/*  Save area for non-coprocessor optional and custom (TIE) state:  */
+#define XCHAL_NCP_SA_SIZE		28
+#define XCHAL_NCP_SA_ALIGN		4
+
+/*  Total save area for optional and custom state (NCP + CPn):  */
+#define XCHAL_TOTAL_SA_SIZE		32	/* with 16-byte align padding */
+#define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */
+
+/*
+ * Detailed contents of save areas.
+ * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
+ * before expanding the XCHAL_xxx_SA_LIST() macros.
+ *
+ * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
+ *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
+ *
+ *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
+ *	ccused = set if used by compiler without special options or code
+ *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
+ *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
+ *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
+ *	name = lowercase reg name (no quotes)
+ *	galign = group byte alignment (power of 2) (galign >= align)
+ *	align = register byte alignment (power of 2)
+ *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
+ *	  (not including any pad bytes required to galign this or next reg)
+ *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
+ *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
+ *	regnum = reg index in regfile, or special/TIE-user reg number
+ *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
+ *	gapsz = intervening bits, if bitsz bits not stored contiguously
+ *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
+ *	reset = register reset value (or 0 if undefined at reset)
+ *	x = reserved for future use (0 until then)
+ *
+ *  To filter out certain registers, e.g. to expand only the non-global
+ *  registers used by the compiler, you can do something like this:
+ *
+ *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
+ *  #define SELCC0(p...)
+ *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
+ *  #define SELAK0(p...)		REG(p)
+ *  #define SELAK1(p...)		REG(p)
+ *  #define SELAK2(p...)
+ *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
+ *		...what you want to expand...
+ */
+
+#define XCHAL_NCP_SA_NUM	7
+#define XCHAL_NCP_SA_LIST(s)	\
+ XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
+ XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0)
+
+#define XCHAL_CP0_SA_NUM	0
+#define XCHAL_CP0_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP1_SA_NUM	0
+#define XCHAL_CP1_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP2_SA_NUM	0
+#define XCHAL_CP2_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP3_SA_NUM	0
+#define XCHAL_CP3_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP4_SA_NUM	0
+#define XCHAL_CP4_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP5_SA_NUM	0
+#define XCHAL_CP5_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP6_SA_NUM	0
+#define XCHAL_CP6_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP7_SA_NUM	0
+#define XCHAL_CP7_SA_LIST(s)	/* empty */
+
+/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
+#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
+/* Byte length of instruction from its first byte, per FLIX.  */
+#define XCHAL_BYTE0_FORMAT_LENGTHS	\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
+
+#endif /*_XTENSA_CORE_TIE_H*/
+
diff --git a/arch/xtensa/include/asm/asmmacro.h b/arch/xtensa/include/asm/asmmacro.h
new file mode 100644
index 0000000..78613fc
--- /dev/null
+++ b/arch/xtensa/include/asm/asmmacro.h
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2005 - 2013 Tensilica Inc.
+ * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _XTENSA_ASMMACRO_H
+#define _XTENSA_ASMMACRO_H
+
+#include <asm/arch/core.h>
+
+/*
+ * Function entry and return macros for supported ABIs.
+ */
+
+#if defined(__XTENSA_WINDOWED_ABI__)
+#define abi_entry	entry	sp, 16
+#define abi_ret		retw
+#elif defined(__XTENSA_CALL0_ABI__)
+#define abi_entry
+#define abi_ret		ret
+#else
+#error Unsupported Xtensa ABI
+#endif
+
+/*
+ * Some little helpers for loops. Use zero-overhead-loops
+ * where applicable and if supported by the processor.
+ *
+ * __loopi ar, at, size, inc
+ *         ar	register initialized with the start address
+ *	   at	scratch register used by macro
+ *	   size	size immediate value
+ *	   inc	increment
+ *
+ * __loops ar, as, at, inc_log2[, mask_log2][, cond][, ncond]
+ *	   ar	register initialized with the start address
+ *	   as	register initialized with the size
+ *	   at	scratch register use by macro
+ *	   inc_log2	increment [in log2]
+ *	   mask_log2	mask [in log2]
+ *	   cond		true condition (used in loop'cond')
+ *	   ncond	false condition (used in b'ncond')
+ *
+ * __loop  as
+ *	   restart loop. 'as' register must not have been modified!
+ *
+ * __endla ar, as, incr
+ *	   ar	start address (modified)
+ *	   as	scratch register used by __loops/__loopi macros or
+ *		end address used by __loopt macro
+ *	   inc	increment
+ */
+
+#if XCHAL_HAVE_LOOPS
+
+.macro	__loopi ar, at, size, incr
+	movi	\at, ((\size + \incr - 1) / (\incr))
+	loop	\at, 99f
+.endm
+
+
+.macro	__loops	ar, as, at, incr_log2, mask_log2, cond, ncond
+	.ifgt \incr_log2 - 1
+		addi	\at, \as, (1 << \incr_log2) - 1
+		.ifnc \mask_log2,
+			extui	\at, \at, \incr_log2, \mask_log2
+		.else
+			srli	\at, \at, \incr_log2
+		.endif
+	.endif
+	loop\cond	\at, 99f
+.endm
+
+
+.macro	__loopt	ar, as, at, incr_log2
+	sub	\at, \as, \ar
+	.ifgt	\incr_log2 - 1
+		addi	\at, \at, (1 << \incr_log2) - 1
+		srli	\at, \at, \incr_log2
+	.endif
+	loop	\at, 99f
+.endm
+
+
+.macro	__loop	as
+	loop	\as, 99f
+.endm
+
+
+.macro	__endl	ar, as
+99:
+.endm
+
+
+#else
+
+.macro	__loopi ar, at, size, incr
+	movi	\at, ((\size + \incr - 1) / (\incr))
+	addi	\at, \ar, \size
+98:
+.endm
+
+
+.macro	__loops	ar, as, at, incr_log2, mask_log2, cond, ncond
+	.ifnc \mask_log2,
+		extui	\at, \as, \incr_log2, \mask_log2
+	.else
+		.ifnc \ncond,
+			srli	\at, \as, \incr_log2
+		.endif
+	.endif
+	.ifnc \ncond,
+		b\ncond	\at, 99f
+
+	.endif
+	.ifnc \mask_log2,
+		slli	\at, \at, \incr_log2
+		add	\at, \ar, \at
+	.else
+		add	\at, \ar, \as
+	.endif
+98:
+.endm
+
+.macro	__loopt	ar, as, at, incr_log2
+98:
+.endm
+
+
+.macro	__loop	as
+98:
+.endm
+
+
+.macro	__endl	ar, as
+	bltu	\ar, \as, 98b
+99:
+.endm
+
+
+#endif
+
+
+.macro	__endla	ar, as, incr
+	addi	\ar, \ar, \incr
+	__endl	\ar \as
+.endm
+
+
+#endif /* _XTENSA_ASMMACRO_H */
diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h
new file mode 100644
index 0000000..4e3ad56
--- /dev/null
+++ b/arch/xtensa/include/asm/atomic.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _XTENSA_ATOMIC_H
+#define _XTENSA_ATOMIC_H
+
+#include <asm/system.h>
+#include <asm-generic/atomic.h>
+
+#endif
diff --git a/arch/xtensa/include/asm/bitops.h b/arch/xtensa/include/asm/bitops.h
new file mode 100644
index 0000000..48a3e1f
--- /dev/null
+++ b/arch/xtensa/include/asm/bitops.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2001 - 2012 Tensilica Inc.
+ * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _XTENSA_BITOPS_H
+#define _XTENSA_BITOPS_H
+
+#include <asm/system.h>
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/__fls.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/__ffs.h>
+
+static inline int test_bit(int nr, const void *addr)
+{
+	return ((unsigned char *)addr)[nr >> 3] & (1u << (nr & 7));
+}
+
+static inline int test_and_set_bit(int nr, volatile void *addr)
+{
+	unsigned long flags;
+	unsigned char tmp;
+	unsigned char mask = 1u << (nr & 7);
+
+	local_irq_save(flags);
+	tmp = ((unsigned char *)addr)[nr >> 3];
+	((unsigned char *)addr)[nr >> 3] |= mask;
+	local_irq_restore(flags);
+
+	return tmp & mask;
+}
+
+#endif	/* _XTENSA_BITOPS_H */
diff --git a/arch/xtensa/include/asm/bootparam.h b/arch/xtensa/include/asm/bootparam.h
new file mode 100644
index 0000000..d756256
--- /dev/null
+++ b/arch/xtensa/include/asm/bootparam.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Definition of the Linux/Xtensa boot parameter structure
+ *
+ * Copyright (C) 2001 - 2009  Tensilica Inc.
+ *
+ * (Concept borrowed from the 68K port)
+ */
+
+#ifndef _XTENSA_BOOTPARAM_H
+#define _XTENSA_BOOTPARAM_H
+
+#define BP_VERSION 0x0001
+
+#define BP_TAG_COMMAND_LINE	0x1001	/* command line (0-terminated string)*/
+#define BP_TAG_INITRD		0x1002	/* ramdisk addr and size (bp_meminfo) */
+#define BP_TAG_MEMORY		0x1003	/* memory addr and size (bp_meminfo) */
+#define BP_TAG_SERIAL_BAUDRATE	0x1004	/* baud rate of current console */
+#define BP_TAG_SERIAL_PORT	0x1005	/* serial device of current console */
+#define BP_TAG_FDT		0x1006	/* flat device tree */
+
+#define BP_TAG_FIRST		0x7B0B  /* first tag with a version number */
+#define BP_TAG_LAST		0x7E0B	/* last tag */
+
+#ifndef __ASSEMBLY__
+
+/* All records are aligned to 4 bytes */
+
+struct bp_tag {
+	unsigned short id;	/* tag id */
+	unsigned short size;	/* size of this record excluding the structure*/
+	unsigned long data[0];	/* data */
+};
+
+#define bp_tag_next(tag)						\
+	((struct bp_tag *)((unsigned long)((tag) + 1) + (tag)->size))
+
+struct meminfo {
+	unsigned long type;
+	unsigned long start;
+	unsigned long end;
+};
+
+#define MEMORY_TYPE_CONVENTIONAL     0x1000
+#define MEMORY_TYPE_NONE             0x2000
+
+struct sysmem_info {
+	int nr_banks;
+	struct meminfo bank[0];
+};
+
+#endif
+#endif
diff --git a/arch/xtensa/include/asm/byteorder.h b/arch/xtensa/include/asm/byteorder.h
new file mode 100644
index 0000000..2137dcf
--- /dev/null
+++ b/arch/xtensa/include/asm/byteorder.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on Linux/Xtensa kernel version
+ *
+ * Copyright (C) 2001 - 2007 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_BYTEORDER_H
+#define _XTENSA_BYTEORDER_H
+
+#include <asm/types.h>
+
+static inline __attribute__((const)) __u32 ___arch__swab32(__u32 x)
+{
+	__u32 res;
+
+	/* instruction sequence from Xtensa ISA release 2/2000 */
+	__asm__("ssai     8\n\t"
+		"srli     %0, %1, 16\n\t"
+		"src      %0, %0, %1\n\t"
+		"src      %0, %0, %0\n\t"
+		"src      %0, %1, %0\n"
+		: "=&a" (res)
+		: "a" (x)
+		);
+	return res;
+}
+
+static inline __attribute__((const)) __u16 ___arch__swab16(__u16 x)
+{
+	/*
+	 * Given that 'short' values are signed (i.e., can be negative),
+	 * we cannot assume that the upper 16-bits of the register are
+	 * zero.  We are careful to mask values after shifting.
+	 */
+
+	/*
+	 * There exists an anomaly between xt-gcc and xt-xcc.  xt-gcc
+	 * inserts an extui instruction after putting this function inline
+	 * to ensure that it uses only the least-significant 16 bits of
+	 * the result.  xt-xcc doesn't use an extui, but assumes the
+	 * __asm__ macro follows convention that the upper 16 bits of an
+	 * 'unsigned short' result are still zero.  This macro doesn't
+	 * follow convention; indeed, it leaves garbage in the upport 16
+	 * bits of the register.
+	 *
+	 * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
+	 * types while the return type of the function is a 16-bit type
+	 * forces both compilers to insert exactly one extui instruction
+	 * (or equivalent) to mask off the upper 16 bits.
+	 */
+
+	__u32 res;
+	__u32 tmp;
+
+	__asm__("extui    %1, %2, 8, 8\n\t"
+		"slli     %0, %2, 8\n\t"
+		"or       %0, %0, %1\n"
+		: "=&a" (res), "=&a" (tmp)
+		: "a" (x)
+		);
+
+	return res;
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __XTENSA_EL__
+# include <linux/byteorder/little_endian.h>
+#elif defined(__XTENSA_EB__)
+# include <linux/byteorder/big_endian.h>
+#else
+# error processor byte order undefined!
+#endif
+
+#endif /* _XTENSA_BYTEORDER_H */
diff --git a/arch/xtensa/include/asm/cache.h b/arch/xtensa/include/asm/cache.h
new file mode 100644
index 0000000..68b8330
--- /dev/null
+++ b/arch/xtensa/include/asm/cache.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009 Tensilica Inc.
+ */
+#ifndef _XTENSA_CACHE_H
+#define _XTENSA_CACHE_H
+
+#include <asm/arch/core.h>
+
+#define ARCH_DMA_MINALIGN	XCHAL_DCACHE_LINESIZE
+
+#ifndef __ASSEMBLY__
+
+void __flush_dcache_all(void);
+void __flush_invalidate_dcache_range(unsigned long addr, unsigned long size);
+void __invalidate_dcache_all(void);
+void __invalidate_dcache_range(unsigned long addr, unsigned long size);
+
+void __invalidate_icache_all(void);
+void __invalidate_icache_range(unsigned long addr, unsigned long size);
+
+#endif
+
+#endif	/* _XTENSA_CACHE_H */
diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h
new file mode 100644
index 0000000..6d321f8
--- /dev/null
+++ b/arch/xtensa/include/asm/cacheasm.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Tensilica Inc.
+ * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _XTENSA_CACHEASM_H
+#define _XTENSA_CACHEASM_H
+
+#include <asm/cache.h>
+#include <asm/asmmacro.h>
+#include <linux/stringify.h>
+
+#define PAGE_SIZE 4096
+#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
+#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
+#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
+#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
+
+/*
+ * Define cache functions as macros here so that they can be used
+ * by the kernel and boot loader. We should consider moving them to a
+ * library that can be linked by both.
+ *
+ * Locking
+ *
+ *   ___unlock_dcache_all
+ *   ___unlock_icache_all
+ *
+ * Flush and invaldating
+ *
+ *   ___flush_invalidate_dcache_{all|range|page}
+ *   ___flush_dcache_{all|range|page}
+ *   ___invalidate_dcache_{all|range|page}
+ *   ___invalidate_icache_{all|range|page}
+ *
+ */
+
+	.macro	__loop_cache_all ar at insn size line_width
+
+	movi	\ar, 0
+
+	__loopi	\ar, \at, \size, (4 << (\line_width))
+
+	\insn	\ar, 0 << (\line_width)
+	\insn	\ar, 1 << (\line_width)
+	\insn	\ar, 2 << (\line_width)
+	\insn	\ar, 3 << (\line_width)
+
+	__endla	\ar, \at, 4 << (\line_width)
+
+	.endm
+
+
+	.macro	__loop_cache_range ar as at insn line_width
+
+	extui	\at, \ar, 0, \line_width
+	add	\as, \as, \at
+
+	__loops	\ar, \as, \at, \line_width
+	\insn	\ar, 0
+	__endla	\ar, \at, (1 << (\line_width))
+
+	.endm
+
+
+	.macro	__loop_cache_page ar at insn line_width
+
+	__loopi	\ar, \at, PAGE_SIZE, 4 << (\line_width)
+
+	\insn	\ar, 0 << (\line_width)
+	\insn	\ar, 1 << (\line_width)
+	\insn	\ar, 2 << (\line_width)
+	\insn	\ar, 3 << (\line_width)
+
+	__endla	\ar, \at, 4 << (\line_width)
+
+	.endm
+
+
+	.macro	___unlock_dcache_all ar at
+
+#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
+	__loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+	.macro	___unlock_icache_all ar at
+
+#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
+	__loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+	.macro	___flush_invalidate_dcache_all ar at
+
+#if XCHAL_DCACHE_SIZE
+	__loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+	.macro	___flush_dcache_all ar at
+
+#if XCHAL_DCACHE_SIZE
+	__loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+	.macro	___invalidate_dcache_all ar at
+
+#if XCHAL_DCACHE_SIZE
+	__loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
+			 XCHAL_DCACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+	.macro	___invalidate_icache_all ar at
+
+#if XCHAL_ICACHE_SIZE
+	__loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
+			 XCHAL_ICACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+
+	.macro	___flush_invalidate_dcache_range ar as at
+
+#if XCHAL_DCACHE_SIZE
+	__loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+	.macro	___flush_dcache_range ar as at
+
+#if XCHAL_DCACHE_SIZE
+	__loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+	.macro	___invalidate_dcache_range ar as at
+
+#if XCHAL_DCACHE_SIZE
+	__loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+	.macro	___invalidate_icache_range ar as at
+
+#if XCHAL_ICACHE_SIZE
+	__loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+
+	.macro	___flush_invalidate_dcache_page ar as
+
+#if XCHAL_DCACHE_SIZE
+	__loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+	.macro ___flush_dcache_page ar as
+
+#if XCHAL_DCACHE_SIZE
+	__loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+	.macro	___invalidate_dcache_page ar as
+
+#if XCHAL_DCACHE_SIZE
+	__loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
+#endif
+
+	.endm
+
+
+	.macro	___invalidate_icache_page ar as
+
+#if XCHAL_ICACHE_SIZE
+	__loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
+#endif
+
+	.endm
+
+#endif	/* _XTENSA_CACHEASM_H */
diff --git a/arch/xtensa/include/asm/config.h b/arch/xtensa/include/asm/config.h
new file mode 100644
index 0000000..5a95fc9
--- /dev/null
+++ b/arch/xtensa/include/asm/config.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009 Tensilica Inc.
+ * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#include <asm/arch/core.h>
+
+#define CONFIG_LMB
+
+/*
+ * Make boot parameters available in the MMUv2 virtual memory layout by
+ * restricting used physical memory to the first 128MB.
+ */
+#if XCHAL_HAVE_PTP_MMU
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED (128 << 20)
+#endif
+
+#endif
diff --git a/arch/xtensa/include/asm/global_data.h b/arch/xtensa/include/asm/global_data.h
new file mode 100644
index 0000000..1157978
--- /dev/null
+++ b/arch/xtensa/include/asm/global_data.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007, Tensilica Inc.
+ */
+
+#ifndef	_XTENSA_GBL_DATA_H
+#define _XTENSA_GBL_DATA_H
+
+/* Architecture-specific global data */
+
+struct arch_global_data {
+	unsigned long cpu_clk;
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR     extern gd_t *gd
+
+#endif	/* _XTENSA_GBL_DATA_H */
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
new file mode 100644
index 0000000..76a646e
--- /dev/null
+++ b/arch/xtensa/include/asm/io.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * IO header file
+ *
+ * Copyright (C) 2001-2007 Tensilica Inc.
+ * Based on the Linux/Xtensa version of this header.
+ */
+
+#ifndef _XTENSA_IO_H
+#define _XTENSA_IO_H
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+/*
+ * swap functions to change byte order from little-endian to big-endian and
+ * vice versa.
+ */
+
+static inline unsigned short _swapw(unsigned short v)
+{
+	return (v << 8) | (v >> 8);
+}
+
+static inline unsigned int _swapl(unsigned int v)
+{
+	return (v << 24) | ((v & 0xff00) << 8) |
+		((v >> 8) & 0xff00) | (v >> 24);
+}
+
+/*
+ * Generic I/O
+ */
+
+#define readb(addr) \
+	({ unsigned char __v = (*(volatile unsigned char *)(addr)); __v; })
+#define readw(addr) \
+	({ unsigned short __v = (*(volatile unsigned short *)(addr)); __v; })
+#define readl(addr) \
+	({ unsigned int __v = (*(volatile unsigned int *)(addr)); __v; })
+#define writeb(b, addr) (void)((*(volatile unsigned char *)(addr)) = (b))
+#define writew(b, addr) (void)((*(volatile unsigned short *)(addr)) = (b))
+#define writel(b, addr) (void)((*(volatile unsigned int *)(addr)) = (b))
+
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+
+/* These are the definitions for the x86 IO instructions
+ * inb/inw/inl/outb/outw/outl, the "string" versions
+ * insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions
+ * inb_p/inw_p/...
+ * The macros don't do byte-swapping.
+ */
+
+#define inb(port)		readb((u8 *)((port)))
+#define outb(val, port)		writeb((val), (u8 *)((unsigned long)(port)))
+#define inw(port)		readw((u16 *)((port)))
+#define outw(val, port)		writew((val), (u16 *)((unsigned long)(port)))
+#define inl(port)		readl((u32 *)((port)))
+#define outl(val, port)		writel((val), (u32 *)((unsigned long)(port)))
+
+#define inb_p(port)		inb((port))
+#define outb_p(val, port)	outb((val), (port))
+#define inw_p(port)		inw((port))
+#define outw_p(val, port)	outw((val), (port))
+#define inl_p(port)		inl((port))
+#define outl_p(val, port)	outl((val), (port))
+
+void insb(unsigned long port, void *dst, unsigned long count);
+void insw(unsigned long port, void *dst, unsigned long count);
+void insl(unsigned long port, void *dst, unsigned long count);
+void outsb(unsigned long port, const void *src, unsigned long count);
+void outsw(unsigned long port, const void *src, unsigned long count);
+void outsl(unsigned long port, const void *src, unsigned long count);
+
+#define IO_SPACE_LIMIT ~0
+
+#define memset_io(a, b, c)	memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)	memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)	memcpy((void *)(a), (b), (c))
+
+/* At this point the Xtensa doesn't provide byte swap instructions */
+
+#ifdef __XTENSA_EB__
+# define in_8(addr) (*(u8 *)(addr))
+# define in_le16(addr) _swapw(*(u16 *)(addr))
+# define in_le32(addr) _swapl(*(u32 *)(addr))
+# define out_8(b, addr) *(u8 *)(addr) = (b)
+# define out_le16(b, addr) *(u16 *)(addr) = _swapw(b)
+# define out_le32(b, addr) *(u32 *)(addr) = _swapl(b)
+#elif defined(__XTENSA_EL__)
+# define in_8(addr)  (*(u8 *)(addr))
+# define in_le16(addr) (*(u16 *)(addr))
+# define in_le32(addr) (*(u32 *)(addr))
+# define out_8(b, addr) *(u8 *)(addr) = (b)
+# define out_le16(b, addr) *(u16 *)(addr) = (b)
+# define out_le32(b, addr) *(u32 *)(addr) = (b)
+#else
+# error processor byte order undefined!
+#endif
+
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+/*
+ * Dummy function to keep U-Boot's cfi_flash.c driver happy.
+ */
+static inline void sync(void)
+{
+}
+
+#include <asm-generic/io.h>
+
+#endif	/* _XTENSA_IO_H */
diff --git a/arch/xtensa/include/asm/ldscript.h b/arch/xtensa/include/asm/ldscript.h
new file mode 100644
index 0000000..08f5d01
--- /dev/null
+++ b/arch/xtensa/include/asm/ldscript.h
@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007 Tensilica, Inc.
+ * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _XTENSA_LDSCRIPT_H
+#define _XTENSA_LDSCRIPT_H
+
+/*
+ * This linker script is pre-processed with CPP to avoid hard-coding
+ * addresses that depend on the Xtensa core configuration, because
+ * this FPGA board can be used with a huge variety of Xtensa cores.
+ */
+
+#include <asm/arch/core.h>
+#include <asm/addrspace.h>
+
+#define ALIGN_LMA	4
+#define LMA_EQ_VMA
+#define FORCE_OUTPUT	. = .
+#define FOLLOWING(sec)							\
+	AT(((LOADADDR(sec) + SIZEOF(sec) + ALIGN_LMA-1)) & ~(ALIGN_LMA-1))
+
+/*
+ * Specify an output section that will be added to the ROM store table
+ * (PACKED_SECTION) or one that will be resident in ROM (RESIDENT_SECTION).
+ * 'symname' is a base name for section boundary symbols *_start & *_end.
+ * 'lma' is the load address at which a section will be packed in ROM.
+ * 'region' is the basename identifying a memory region and program header.
+ * 'keep' prevents removal of empty sections (must be 'KEEP' or 'NOKEEP').
+ */
+
+#define RELOCATE1(_sec_)						\
+	LONG(_##_sec_##_start);						\
+	LONG(_##_sec_##_end);						\
+	LONG(LOADADDR(.##_sec_));
+
+#define RELOCATE2(_sym_, _sec_)						\
+	LONG(_##_sym_##_##_sec_##_start);				\
+	LONG(_##_sym_##_##_sec_##_end);					\
+	LONG(LOADADDR(.##_sym_##.##_sec_));
+
+#define SECTION_VECTOR(_sym_, _sec_, _vma_, _lma_)			\
+.##_sym_##.##_sec_ _vma_ : _lma_					\
+{									\
+	. = ALIGN(4);							\
+	_##_sym_##_##_sec_##_start = ABSOLUTE(.);			\
+	KEEP(*(.##_sym_##.##_sec_))					\
+	_##_sym_##_##_sec_##_end = ABSOLUTE(.);				\
+}
+
+/* In MMU configs there are two aliases of SYSROM, cached and uncached.
+ * For various reasons it is simpler to use the uncached mapping for load
+ * addresses, so ROM sections end up contiguous with the reset vector and
+ * we get a compact binary image. However we can gain performance by doing
+ * the unpacking from the cached ROM mapping. So we adjust all the load
+ * addresses in the ROM store table with an offset to the cached mapping,
+ * including the symbols referring to the ROM store table itself.
+ */
+
+#define SECTION_ResetVector(_vma_, _lma_)				\
+	.ResetVector.text _vma_ : _lma_					\
+	{								\
+		FORCE_OUTPUT;						\
+		KEEP(*(.ResetVector.text));				\
+		KEEP(*(.reset.literal .reset.text))			\
+	}
+
+#define SECTION_text(_vma_, _lma_)					\
+	.text _vma_ : _lma_						\
+	{								\
+		_text_start = ABSOLUTE(.);				\
+		*(.literal .text)					\
+		*(.literal.* .text.* .stub)				\
+		*(.gnu.warning .gnu.linkonce.literal.*)			\
+		*(.gnu.linkonce.t.*.literal .gnu.linkonce.t.*)		\
+		*(.fini.literal)					\
+		*(.fini)						\
+		*(.gnu.version)						\
+		_text_end = ABSOLUTE(.);				\
+	}
+
+#define SECTION_rodata(_vma_, _lma_)					\
+	.rodata _vma_ : _lma_						\
+	{								\
+		_rodata_start = ABSOLUTE(.);				\
+		*(.rodata)						\
+		*(.rodata.*)						\
+		*(.dtb.init.rodata)					\
+		*(.gnu.linkonce.r.*)					\
+		*(.rodata1)						\
+		__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);			\
+		*(.xt_except_table)					\
+		*(.gcc_except_table)					\
+		*(.gnu.linkonce.e.*)					\
+		*(.gnu.version_r)					\
+		. = ALIGN(16);						\
+		 _rodata_end = ABSOLUTE(.);				\
+	}
+
+#define SECTION_u_boot_list(_vma_, _lma_)				\
+	.u_boot_list _vma_ : _lma_					\
+	{								\
+		_u_boot_list_start = ABSOLUTE(.);			\
+		KEEP(*(SORT(.u_boot_list*)));				\
+		_u_boot_list_end = ABSOLUTE(.);				\
+	}
+
+#define SECTION_data(_vma_, _lma_)					\
+	.data _vma_ : _lma_						\
+	{								\
+		_data_start = ABSOLUTE(.);				\
+		*(.data)						\
+		*(.data.*)						\
+		*(.gnu.linkonce.d.*)					\
+		*(.data1)						\
+		*(.sdata)						\
+		*(.sdata.*)						\
+		*(.gnu.linkonce.s.*)					\
+		*(.sdata2)						\
+		*(.sdata2.*)						\
+		*(.gnu.linkonce.s2.*)					\
+		*(.jcr)							\
+		*(.eh_frame)						\
+		*(.dynamic)						\
+		*(.gnu.version_d)					\
+		_data_end = ABSOLUTE(.);				\
+	}
+
+#define SECTION_lit4(_vma_, _lma_)					\
+	.lit4 _vma_ : _lma_						\
+	{								\
+		_lit4_start = ABSOLUTE(.);				\
+		*(*.lit4)						\
+		*(.gnu.linkonce.lit4.*)					\
+		_lit4_end = ABSOLUTE(.);				\
+	}
+
+#define SECTION_bss(_vma_, _lma_)					\
+	.bss _vma_ : _lma_						\
+	{								\
+		. = ALIGN(8);						\
+		_bss_start = ABSOLUTE(.);				\
+		__bss_start = ABSOLUTE(.);				\
+		*(.dynsbss)						\
+		*(.sbss)						\
+		*(.sbss.*)						\
+		*(.gnu.linkonce.sb.*)					\
+		*(.scommon)						\
+		*(.sbss2)						\
+		*(.sbss2.*)						\
+		*(.gnu.linkonce.sb2.*)					\
+		*(.dynbss)						\
+		*(.bss)							\
+		*(.bss.*)						\
+		*(.gnu.linkonce.b.*)					\
+		*(COMMON)						\
+		*(.sram.bss)						\
+		. = ALIGN(8);						\
+		_bss_end = ABSOLUTE(.);					\
+		__bss_end = ABSOLUTE(.);				\
+		_end = ALIGN(0x8);					\
+		PROVIDE(end = ALIGN(0x8));				\
+		_stack_sentry = ALIGN(0x8);				\
+	}
+
+#define SECTION_debug							\
+	.debug           0 :  { *(.debug) }				\
+	.line            0 :  { *(.line) }				\
+	.debug_srcinfo   0 :  { *(.debug_srcinfo) }			\
+	.debug_sfnames   0 :  { *(.debug_sfnames) }			\
+	.debug_aranges   0 :  { *(.debug_aranges) }			\
+	.debug_pubnames  0 :  { *(.debug_pubnames) }			\
+	.debug_info      0 :  { *(.debug_info) }			\
+	.debug_abbrev    0 :  { *(.debug_abbrev) }			\
+	.debug_line      0 :  { *(.debug_line) }			\
+	.debug_frame     0 :  { *(.debug_frame) }			\
+	.debug_str       0 :  { *(.debug_str) }				\
+	.debug_loc       0 :  { *(.debug_loc) }				\
+	.debug_macinfo   0 :  { *(.debug_macinfo) }			\
+	.debug_weaknames 0 :  { *(.debug_weaknames) }			\
+	.debug_funcnames 0 :  { *(.debug_funcnames) }			\
+	.debug_typenames 0 :  { *(.debug_typenames) }			\
+	.debug_varnames  0 :  { *(.debug_varnames) }
+
+#define SECTION_xtensa							\
+	.xt.insn 0 :							\
+	{								\
+		KEEP (*(.xt.insn))					\
+		KEEP (*(.gnu.linkonce.x.*))				\
+	}								\
+	.xt.prop 0 :							\
+	{								\
+		KEEP (*(.xt.prop))					\
+		KEEP (*(.xt.prop.*))					\
+		KEEP (*(.gnu.linkonce.prop.*))				\
+	}								\
+	.xt.lit 0 :							\
+	{								\
+		KEEP (*(.xt.lit))					\
+		KEEP (*(.xt.lit.*))					\
+		KEEP (*(.gnu.linkonce.p.*))				\
+	}								\
+	.xt.profile_range 0 :						\
+	{								\
+		KEEP (*(.xt.profile_range))				\
+		KEEP (*(.gnu.linkonce.profile_range.*))			\
+	}								\
+	.xt.profile_ranges 0 :						\
+	{								\
+		KEEP (*(.xt.profile_ranges))				\
+		KEEP (*(.gnu.linkonce.xt.profile_ranges.*))		\
+	}								\
+	.xt.profile_files 0 :						\
+	{								\
+		KEEP (*(.xt.profile_files))				\
+		KEEP (*(.gnu.linkonce.xt.profile_files.*))		\
+	}
+
+#endif	/* _XTENSA_LDSCRIPT_H */
diff --git a/arch/xtensa/include/asm/linkage.h b/arch/xtensa/include/asm/linkage.h
new file mode 100644
index 0000000..3f46161
--- /dev/null
+++ b/arch/xtensa/include/asm/linkage.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#endif
diff --git a/arch/xtensa/include/asm/misc.h b/arch/xtensa/include/asm/misc.h
new file mode 100644
index 0000000..3ed9fcb
--- /dev/null
+++ b/arch/xtensa/include/asm/misc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008, Tensilica Inc.
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _XTENSA_MISC_H
+#define _XTENSA_MISC_H
+
+/* Used in cpu/xtensa/cpu.c */
+void board_reset(void);
+
+#endif	/* _XTENSA_MISC_H */
diff --git a/arch/xtensa/include/asm/posix_types.h b/arch/xtensa/include/asm/posix_types.h
new file mode 100644
index 0000000..7fb65ea
--- /dev/null
+++ b/arch/xtensa/include/asm/posix_types.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2007, Tensilica Inc.
+ *
+ * Based on the ARM version: Copyright (C) 1996-1998 Russell King.
+ */
+#ifndef _XTENSA_POSIX_TYPES_H
+#define _XTENSA_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned short		__kernel_dev_t;
+typedef unsigned long		__kernel_ino_t;
+typedef unsigned short		__kernel_mode_t;
+typedef unsigned short		__kernel_nlink_t;
+typedef long			__kernel_off_t;
+typedef int			__kernel_pid_t;
+typedef unsigned short		__kernel_ipc_pid_t;
+typedef unsigned short		__kernel_uid_t;
+typedef unsigned short		__kernel_gid_t;
+typedef unsigned int		__kernel_size_t;
+typedef int			__kernel_ssize_t;
+typedef int			__kernel_ptrdiff_t;
+typedef long			__kernel_time_t;
+typedef long			__kernel_suseconds_t;
+typedef long			__kernel_clock_t;
+typedef int			__kernel_daddr_t;
+typedef char *			__kernel_caddr_t;
+typedef unsigned short		__kernel_uid16_t;
+typedef unsigned short		__kernel_gid16_t;
+typedef unsigned int		__kernel_uid32_t;
+typedef unsigned int		__kernel_gid32_t;
+
+typedef unsigned short		__kernel_old_uid_t;
+typedef unsigned short		__kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long		__kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+	int	val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+	int	__val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef	__FD_SET
+#define __FD_SET(fd, fdsetp) \
+	(((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
+
+#undef	__FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+	(((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
+
+#undef	__FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+	((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
+
+#undef	__FD_ZERO
+#define __FD_ZERO(fdsetp) \
+	(memset(fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif
+
+#endif	/* _XTENSA_POSIX_TYPES_H */
diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h
new file mode 100644
index 0000000..22203c9
--- /dev/null
+++ b/arch/xtensa/include/asm/processor.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 1997 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PROCESSOR_H
+#define _XTENSA_PROCESSOR_H
+
+
+#endif /* _XTENSA_PROCESSOR_H */
diff --git a/arch/xtensa/include/asm/ptrace.h b/arch/xtensa/include/asm/ptrace.h
new file mode 100644
index 0000000..7717016
--- /dev/null
+++ b/arch/xtensa/include/asm/ptrace.h
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2001 - 2007 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_PTRACE_H
+#define _XTENSA_PTRACE_H
+
+#include <compiler.h>
+
+/*
+ * Kernel stack
+ *
+ *		+-----------------------+  -------- STACK_SIZE
+ *		|     register file     |  |
+ *		+-----------------------+  |
+ *		|    struct pt_regs     |  |
+ *		+-----------------------+  | ------ PT_REGS_OFFSET
+ * double	:  16 bytes spill area  :  |  ^
+ * exception	:- - - - - - - - - - - -:  |  |
+ * frame	:    struct pt_regs     :  |  |
+ *		:- - - - - - - - - - - -:  |  |
+ *		|                       |  |  |
+ *		|     memory stack      |  |  |
+ *		|                       |  |  |
+ *		~                       ~  ~  ~
+ *		~                       ~  ~  ~
+ *		|                       |  |  |
+ *		|                       |  |  |
+ *		+-----------------------+  |  | --- STACK_BIAS
+ *		|  struct task_struct   |  |  |  ^
+ *  current --> +-----------------------+  |  |  |
+ *		|  struct thread_info   |  |  |  |
+ *		+-----------------------+ --------
+ */
+
+#define KERNEL_STACK_SIZE (2 * PAGE_SIZE)
+
+/*  Offsets for exception_handlers[] (3 x 64-entries x 4-byte tables) */
+
+#define EXC_TABLE_KSTK		0x004	/* Kernel Stack */
+#define EXC_TABLE_DOUBLE_SAVE	0x008	/* Double exception save area for a0 */
+#define EXC_TABLE_FIXUP		0x00c	/* Fixup handler */
+#define EXC_TABLE_PARAM		0x010	/* For passing a parameter to fixup */
+#define EXC_TABLE_SYSCALL_SAVE	0x014	/* For fast syscall handler */
+#define EXC_TABLE_FAST_USER	0x100	/* Fast user exception handler */
+#define EXC_TABLE_FAST_KERNEL	0x200	/* Fast kernel exception handler */
+#define EXC_TABLE_DEFAULT	0x300	/* Default C-Handler */
+#define EXC_TABLE_SIZE		0x400
+
+/* Registers used by strace */
+
+#define REG_A_BASE	0xfc000000
+#define REG_AR_BASE	0x04000000
+#define REG_PC		0x14000000
+#define REG_PS		0x080000e6
+#define REG_WB		0x08000048
+#define REG_WS		0x08000049
+#define REG_LBEG	0x08000000
+#define REG_LEND	0x08000001
+#define REG_LCOUNT	0x08000002
+#define REG_SAR		0x08000003
+#define REG_DEPC	0x080000c0
+#define REG_EXCCAUSE	0x080000e8
+#define REG_EXCVADDR	0x080000ee
+#define SYSCALL_NR	0x1
+
+#define AR_REGNO_TO_A_REGNO(ar, wb) (ar - wb*4) & ~(XCHAL_NUM_AREGS - 1)
+
+/* Other PTRACE_ values defined in <linux/ptrace.h> using values 0-9,16,17,24 */
+
+#define PTRACE_GETREGS            12
+#define PTRACE_SETREGS            13
+#define PTRACE_GETFPREGS          14
+#define PTRACE_SETFPREGS          15
+#define PTRACE_GETFPREGSIZE       18
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_regs {
+	unsigned long pc;		/*   4 */
+	unsigned long ps;		/*   8 */
+	unsigned long depc;		/*  12 */
+	unsigned long exccause;		/*  16 */
+	unsigned long excvaddr;		/*  20 */
+	unsigned long debugcause;	/*  24 */
+	unsigned long wmask;		/*  28 */
+	unsigned long lbeg;		/*  32 */
+	unsigned long lend;		/*  36 */
+	unsigned long lcount;		/*  40 */
+	unsigned long sar;		/*  44 */
+	unsigned long windowbase;	/*  48 */
+	unsigned long windowstart;	/*  52 */
+	unsigned long syscall;		/*  56 */
+	unsigned long icountlevel;	/*  60 */
+	int reserved[1];		/*  64 */
+
+	/* Make sure the areg field is 16 bytes aligned */
+	int align[0] __aligned(16);
+
+	/* current register frame.
+	 * Note: The ESF for kernel exceptions ends after 16 registers!
+	 */
+	unsigned long areg[16];		/* 128 (64) */
+};
+
+#ifdef __KERNEL__
+
+# define task_pt_regs(tsk) ((struct pt_regs *) \
+	(task_stack_page(tsk) + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4) - 1)
+# define user_mode(regs) (((regs)->ps & 0x00000020) != 0)
+# define instruction_pointer(regs) ((regs)->pc)
+void show_regs(struct pt_regs *);
+
+# ifndef CONFIG_SMP
+#  define profile_pc(regs) instruction_pointer(regs)
+# endif
+#endif /* __KERNEL__ */
+
+#else	/* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+# include <asm/asm-offsets.h>
+#define PT_REGS_OFFSET	  (KERNEL_STACK_SIZE - PT_USER_SIZE)
+#endif
+
+#endif	/* !__ASSEMBLY__ */
+#endif	/* _XTENSA_PTRACE_H */
diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h
new file mode 100644
index 0000000..32b50f9
--- /dev/null
+++ b/arch/xtensa/include/asm/regs.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2006 Tensilica, Inc.  All Rights Reserved.
+ */
+
+#ifndef _XTENSA_REGS_H
+#define _XTENSA_REGS_H
+
+/*  Special registers  */
+
+#define IBREAKA		128
+#define DBREAKA		144
+#define DBREAKC		160
+
+/*  Special names for read-only and write-only interrupt registers  */
+
+#define INTREAD		226
+#define INTSET		226
+#define INTCLEAR	227
+
+/*  EXCCAUSE register fields  */
+
+#define EXCCAUSE_EXCCAUSE_SHIFT	0
+#define EXCCAUSE_EXCCAUSE_MASK	0x3F
+
+#define EXCCAUSE_ILLEGAL_INSTRUCTION		0
+#define EXCCAUSE_SYSTEM_CALL			1
+#define EXCCAUSE_INSTRUCTION_FETCH_ERROR	2
+#define EXCCAUSE_LOAD_STORE_ERROR		3
+#define EXCCAUSE_LEVEL1_INTERRUPT		4
+#define EXCCAUSE_ALLOCA				5
+#define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO		6
+#define EXCCAUSE_SPECULATION			7
+#define EXCCAUSE_PRIVILEGED			8
+#define EXCCAUSE_UNALIGNED			9
+#define EXCCAUSE_INSTR_DATA_ERROR		12
+#define EXCCAUSE_LOAD_STORE_DATA_ERROR		13
+#define EXCCAUSE_INSTR_ADDR_ERROR		14
+#define EXCCAUSE_LOAD_STORE_ADDR_ERROR		15
+#define EXCCAUSE_ITLB_MISS			16
+#define EXCCAUSE_ITLB_MULTIHIT			17
+#define EXCCAUSE_ITLB_PRIVILEGE			18
+#define EXCCAUSE_ITLB_SIZE_RESTRICTION		19
+#define EXCCAUSE_FETCH_CACHE_ATTRIBUTE		20
+#define EXCCAUSE_DTLB_MISS			24
+#define EXCCAUSE_DTLB_MULTIHIT			25
+#define EXCCAUSE_DTLB_PRIVILEGE			26
+#define EXCCAUSE_DTLB_SIZE_RESTRICTION		27
+#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE		28
+#define EXCCAUSE_STORE_CACHE_ATTRIBUTE		29
+#define EXCCAUSE_COPROCESSOR0_DISABLED		32
+#define EXCCAUSE_COPROCESSOR1_DISABLED		33
+#define EXCCAUSE_COPROCESSOR2_DISABLED		34
+#define EXCCAUSE_COPROCESSOR3_DISABLED		35
+#define EXCCAUSE_COPROCESSOR4_DISABLED		36
+#define EXCCAUSE_COPROCESSOR5_DISABLED		37
+#define EXCCAUSE_COPROCESSOR6_DISABLED		38
+#define EXCCAUSE_COPROCESSOR7_DISABLED		39
+#define EXCCAUSE_LAST				63
+
+/*  PS register fields  */
+
+#define PS_WOE_BIT		18
+#define PS_CALLINC_SHIFT	16
+#define PS_CALLINC_MASK		0x00030000
+#define PS_OWB_SHIFT		8
+#define PS_OWB_MASK		0x00000F00
+#define PS_RING_SHIFT		6
+#define PS_RING_MASK		0x000000C0
+#define PS_UM_BIT		5
+#define PS_EXCM_BIT		4
+#define PS_INTLEVEL_SHIFT	0
+#define PS_INTLEVEL_MASK	0x0000000F
+
+/*  DBREAKCn register fields  */
+
+#define DBREAKC_MASK_BIT		0
+#define DBREAKC_MASK_MASK		0x0000003F
+#define DBREAKC_LOAD_BIT		30
+#define DBREAKC_LOAD_MASK		0x40000000
+#define DBREAKC_STOR_BIT		31
+#define DBREAKC_STOR_MASK		0x80000000
+
+/*  DEBUGCAUSE register fields  */
+
+#define DEBUGCAUSE_DEBUGINT_BIT		5	/* External debug interrupt */
+#define DEBUGCAUSE_BREAKN_BIT		4	/* BREAK.N instruction */
+#define DEBUGCAUSE_BREAK_BIT		3	/* BREAK instruction */
+#define DEBUGCAUSE_DBREAK_BIT		2	/* DBREAK match */
+#define DEBUGCAUSE_IBREAK_BIT		1	/* IBREAK match */
+#define DEBUGCAUSE_ICOUNT_BIT		0	/* ICOUNT would incr. to zero */
+
+#endif /* _XTENSA_SPECREG_H */
+
diff --git a/arch/xtensa/include/asm/sections.h b/arch/xtensa/include/asm/sections.h
new file mode 100644
index 0000000..af2c177
--- /dev/null
+++ b/arch/xtensa/include/asm/sections.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __ASM_XTENSA_SECTIONS_H
+#define __ASM_XTENSA_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/arch/xtensa/include/asm/string.h b/arch/xtensa/include/asm/string.h
new file mode 100644
index 0000000..65a3601
--- /dev/null
+++ b/arch/xtensa/include/asm/string.h
@@ -0,0 +1,10 @@
+#ifndef _XTENSA_STRING_H
+#define _XTENSA_STRING_H
+
+/*
+ * Use the generic string functions in U-Boot's lib_generic.
+ * In the boot loader we care about compactness more than performance.
+ * Prototypes will be taken from <linux/string.h>
+ */
+
+#endif	/* _XTENSA_STRING_H */
diff --git a/arch/xtensa/include/asm/system.h b/arch/xtensa/include/asm/system.h
new file mode 100644
index 0000000..a241568
--- /dev/null
+++ b/arch/xtensa/include/asm/system.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _XTENSA_SYSTEM_H
+#define _XTENSA_SYSTEM_H
+
+#include <asm/arch/core.h>
+
+#if XCHAL_HAVE_INTERRUPTS
+#define local_irq_save(flags) \
+	__asm__ __volatile__ ("rsil %0, %1" \
+			      : "=a"(flags) \
+			      : "I"(XCHAL_EXCM_LEVEL) \
+			      : "memory")
+#define local_irq_restore(flags) \
+	__asm__ __volatile__ ("wsr %0, ps\n\t" \
+			      "rsync" \
+			      :: "a"(flags) : "memory")
+#else
+#define local_irq_save(flags) ((void)(flags))
+#define local_irq_restore(flags) ((void)(flags))
+#endif
+
+#endif
diff --git a/arch/xtensa/include/asm/types.h b/arch/xtensa/include/asm/types.h
new file mode 100644
index 0000000..2c5b543
--- /dev/null
+++ b/arch/xtensa/include/asm/types.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 1997 Tensilica Inc.
+ */
+
+#ifndef _XTENSA_TYPES_H
+#define _XTENSA_TYPES_H
+
+#include <asm-generic/int-ll64.h>
+
+typedef unsigned short umode_t;
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+
+#endif /* __KERNEL__ */
+
+#endif /* _XTENSA_TYPES_H */
diff --git a/arch/xtensa/include/asm/u-boot.h b/arch/xtensa/include/asm/u-boot.h
new file mode 100644
index 0000000..24c4fce
--- /dev/null
+++ b/arch/xtensa/include/asm/u-boot.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007, Tensilica Inc.
+ *
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef _XTENSA_U_BOOT_H
+#define _XTENSA_U_BOOT_H
+
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_XTENSA
+
+#endif	/* _XTENSA_U_BOOT_H */
diff --git a/arch/xtensa/include/asm/unaligned.h b/arch/xtensa/include/asm/unaligned.h
new file mode 100644
index 0000000..536f364
--- /dev/null
+++ b/arch/xtensa/include/asm/unaligned.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_XTENSA_UNALIGNED_H
+#define _ASM_XTENSA_UNALIGNED_H
+
+#include <asm-generic/unaligned.h>
+
+#endif /* _ASM_XTENSA_UNALIGNED_H */
diff --git a/crc16.c b/crc16.c
new file mode 100644
index 0000000..3afb34d
--- /dev/null
+++ b/crc16.c
@@ -0,0 +1,62 @@
+/*
+ *      crc16.c
+ *
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <linux/stat.h>
+#include "crc16.h"
+
+/** CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1) */
+static __u16 const crc16_table[256] = {
+	0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
+	0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
+	0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
+	0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
+	0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
+	0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
+	0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
+	0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
+	0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
+	0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
+	0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
+	0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
+	0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
+	0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
+	0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
+	0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
+	0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
+	0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
+	0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
+	0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
+	0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
+	0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
+	0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
+	0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
+	0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
+	0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
+	0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
+	0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
+	0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
+	0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
+	0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
+	0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
+};
+
+/**
+ * Compute the CRC-16 for the data buffer
+*/
+
+unsigned int ext2fs_crc16(unsigned int crc,
+	const void *buffer, unsigned int len)
+{
+	const unsigned char *cp = buffer;
+
+	while (len--)
+		crc = (((crc >> 8) & 0xffU) ^
+		       crc16_table[(crc ^ *cp++) & 0xffU]) & 0x0000ffffU;
+	return crc;
+}
diff --git a/crc16.h b/crc16.h
new file mode 100644
index 0000000..5fd113a
--- /dev/null
+++ b/crc16.h
@@ -0,0 +1,16 @@
+/*
+ * crc16.h - CRC-16 routine
+ * Implements the standard CRC-16:
+ *  Width 16
+ *  Poly  0x8005 (x16 + x15 + x2 + 1)
+ *  Init  0
+ *
+ * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com>
+ * This source code is licensed under the GNU General Public License,
+ * Version 2. See the file COPYING for more details.
+ */
+#ifndef __CRC16_H
+#define __CRC16_H
+extern unsigned int ext2fs_crc16(unsigned int crc,
+	const void *buffer, unsigned int len);
+#endif
diff --git a/dev.c b/dev.c
new file mode 100644
index 0000000..2907688
--- /dev/null
+++ b/dev.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * made from existing ext2/dev.c file of Uboot
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code of fs/reiserfs/dev.c by
+ *
+ * (C) Copyright 2003 - 2004
+ * Sysgo AG, <www.elinos.com>, Pavel Bartusek <pba@sysgo.com>
+ */
+
+/*
+ * Changelog:
+ *	0.1 - Newly created file for ext4fs support. Taken from
+ *		fs/ext2/dev.c file in uboot.
+ */
+
+#include <common.h>
+#include <blk.h>
+#include <config.h>
+#include <fs_internal.h>
+#include <ext4fs.h>
+#include <ext_common.h>
+#include "ext4_common.h"
+
+lbaint_t part_offset;
+
+static struct blk_desc *ext4fs_blk_desc;
+static disk_partition_t *part_info;
+
+void ext4fs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info)
+{
+	assert(rbdd->blksz == (1 << rbdd->log2blksz));
+	ext4fs_blk_desc = rbdd;
+	get_fs()->dev_desc = rbdd;
+	part_info = info;
+	part_offset = info->start;
+	get_fs()->total_sect = ((uint64_t)info->size * info->blksz) >>
+		get_fs()->dev_desc->log2blksz;
+}
+
+int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len,
+		   char *buffer)
+{
+	return fs_devread(get_fs()->dev_desc, part_info, sector, byte_offset,
+			  byte_len, buffer);
+}
+
+int ext4_read_superblock(char *buffer)
+{
+	struct ext_filesystem *fs = get_fs();
+	int sect = SUPERBLOCK_START >> fs->dev_desc->log2blksz;
+	int off = SUPERBLOCK_START % fs->dev_desc->blksz;
+
+	return ext4fs_devread(sect, off, SUPERBLOCK_SIZE,
+				buffer);
+}
diff --git a/ext4_common.c b/ext4_common.c
new file mode 100644
index 0000000..5bf78b5
--- /dev/null
+++ b/ext4_common.c
@@ -0,0 +1,2421 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * ext4ls and ext4load : Based on ext2 ls load support in Uboot.
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB  --  GRand Unified Bootloader
+ * Copyright (C) 2003, 2004  Free Software Foundation, Inc.
+ *
+ * ext4write : Based on generic ext4 protocol.
+ */
+
+#include <common.h>
+#include <ext_common.h>
+#include <ext4fs.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <stddef.h>
+#include <linux/stat.h>
+#include <linux/time.h>
+#include <asm/byteorder.h>
+#include "ext4_common.h"
+
+struct ext2_data *ext4fs_root;
+struct ext2fs_node *ext4fs_file;
+__le32 *ext4fs_indir1_block;
+int ext4fs_indir1_size;
+int ext4fs_indir1_blkno = -1;
+__le32 *ext4fs_indir2_block;
+int ext4fs_indir2_size;
+int ext4fs_indir2_blkno = -1;
+
+__le32 *ext4fs_indir3_block;
+int ext4fs_indir3_size;
+int ext4fs_indir3_blkno = -1;
+struct ext2_inode *g_parent_inode;
+static int symlinknest;
+
+#if defined(CONFIG_EXT4_WRITE)
+struct ext2_block_group *ext4fs_get_group_descriptor
+	(const struct ext_filesystem *fs, uint32_t bg_idx)
+{
+	return (struct ext2_block_group *)(fs->gdtable + (bg_idx * fs->gdsize));
+}
+
+static inline void ext4fs_sb_free_inodes_dec(struct ext2_sblock *sb)
+{
+	sb->free_inodes = cpu_to_le32(le32_to_cpu(sb->free_inodes) - 1);
+}
+
+static inline void ext4fs_sb_free_blocks_dec(struct ext2_sblock *sb)
+{
+	uint64_t free_blocks = le32_to_cpu(sb->free_blocks);
+	free_blocks += (uint64_t)le32_to_cpu(sb->free_blocks_high) << 32;
+	free_blocks--;
+
+	sb->free_blocks = cpu_to_le32(free_blocks & 0xffffffff);
+	sb->free_blocks_high = cpu_to_le16(free_blocks >> 32);
+}
+
+static inline void ext4fs_bg_free_inodes_dec
+	(struct ext2_block_group *bg, const struct ext_filesystem *fs)
+{
+	uint32_t free_inodes = le16_to_cpu(bg->free_inodes);
+	if (fs->gdsize == 64)
+		free_inodes += le16_to_cpu(bg->free_inodes_high) << 16;
+	free_inodes--;
+
+	bg->free_inodes = cpu_to_le16(free_inodes & 0xffff);
+	if (fs->gdsize == 64)
+		bg->free_inodes_high = cpu_to_le16(free_inodes >> 16);
+}
+
+static inline void ext4fs_bg_free_blocks_dec
+	(struct ext2_block_group *bg, const struct ext_filesystem *fs)
+{
+	uint32_t free_blocks = le16_to_cpu(bg->free_blocks);
+	if (fs->gdsize == 64)
+		free_blocks += le16_to_cpu(bg->free_blocks_high) << 16;
+	free_blocks--;
+
+	bg->free_blocks = cpu_to_le16(free_blocks & 0xffff);
+	if (fs->gdsize == 64)
+		bg->free_blocks_high = cpu_to_le16(free_blocks >> 16);
+}
+
+static inline void ext4fs_bg_itable_unused_dec
+	(struct ext2_block_group *bg, const struct ext_filesystem *fs)
+{
+	uint32_t free_inodes = le16_to_cpu(bg->bg_itable_unused);
+	if (fs->gdsize == 64)
+		free_inodes += le16_to_cpu(bg->bg_itable_unused_high) << 16;
+	free_inodes--;
+
+	bg->bg_itable_unused = cpu_to_le16(free_inodes & 0xffff);
+	if (fs->gdsize == 64)
+		bg->bg_itable_unused_high = cpu_to_le16(free_inodes >> 16);
+}
+
+uint64_t ext4fs_sb_get_free_blocks(const struct ext2_sblock *sb)
+{
+	uint64_t free_blocks = le32_to_cpu(sb->free_blocks);
+	free_blocks += (uint64_t)le32_to_cpu(sb->free_blocks_high) << 32;
+	return free_blocks;
+}
+
+void ext4fs_sb_set_free_blocks(struct ext2_sblock *sb, uint64_t free_blocks)
+{
+	sb->free_blocks = cpu_to_le32(free_blocks & 0xffffffff);
+	sb->free_blocks_high = cpu_to_le16(free_blocks >> 32);
+}
+
+uint32_t ext4fs_bg_get_free_blocks(const struct ext2_block_group *bg,
+				   const struct ext_filesystem *fs)
+{
+	uint32_t free_blocks = le16_to_cpu(bg->free_blocks);
+	if (fs->gdsize == 64)
+		free_blocks += le16_to_cpu(bg->free_blocks_high) << 16;
+	return free_blocks;
+}
+
+static inline
+uint32_t ext4fs_bg_get_free_inodes(const struct ext2_block_group *bg,
+				   const struct ext_filesystem *fs)
+{
+	uint32_t free_inodes = le16_to_cpu(bg->free_inodes);
+	if (fs->gdsize == 64)
+		free_inodes += le16_to_cpu(bg->free_inodes_high) << 16;
+	return free_inodes;
+}
+
+static inline uint16_t ext4fs_bg_get_flags(const struct ext2_block_group *bg)
+{
+	return le16_to_cpu(bg->bg_flags);
+}
+
+static inline void ext4fs_bg_set_flags(struct ext2_block_group *bg,
+				       uint16_t flags)
+{
+	bg->bg_flags = cpu_to_le16(flags);
+}
+
+/* Block number of the block bitmap */
+uint64_t ext4fs_bg_get_block_id(const struct ext2_block_group *bg,
+				const struct ext_filesystem *fs)
+{
+	uint64_t block_nr = le32_to_cpu(bg->block_id);
+	if (fs->gdsize == 64)
+		block_nr += (uint64_t)le32_to_cpu(bg->block_id_high) << 32;
+	return block_nr;
+}
+
+/* Block number of the inode bitmap */
+uint64_t ext4fs_bg_get_inode_id(const struct ext2_block_group *bg,
+				const struct ext_filesystem *fs)
+{
+	uint64_t block_nr = le32_to_cpu(bg->inode_id);
+	if (fs->gdsize == 64)
+		block_nr += (uint64_t)le32_to_cpu(bg->inode_id_high) << 32;
+	return block_nr;
+}
+#endif
+
+/* Block number of the inode table */
+uint64_t ext4fs_bg_get_inode_table_id(const struct ext2_block_group *bg,
+				      const struct ext_filesystem *fs)
+{
+	uint64_t block_nr = le32_to_cpu(bg->inode_table_id);
+	if (fs->gdsize == 64)
+		block_nr +=
+			(uint64_t)le32_to_cpu(bg->inode_table_id_high) << 32;
+	return block_nr;
+}
+
+#if defined(CONFIG_EXT4_WRITE)
+uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n)
+{
+	uint32_t res = size / n;
+	if (res * n != size)
+		res++;
+
+	return res;
+}
+
+void put_ext4(uint64_t off, const void *buf, uint32_t size)
+{
+	uint64_t startblock;
+	uint64_t remainder;
+	unsigned char *temp_ptr = NULL;
+	struct ext_filesystem *fs = get_fs();
+	int log2blksz = fs->dev_desc->log2blksz;
+	ALLOC_CACHE_ALIGN_BUFFER(unsigned char, sec_buf, fs->dev_desc->blksz);
+
+	startblock = off >> log2blksz;
+	startblock += part_offset;
+	remainder = off & (uint64_t)(fs->dev_desc->blksz - 1);
+
+	if (fs->dev_desc == NULL)
+		return;
+
+	if ((startblock + (size >> log2blksz)) >
+	    (part_offset + fs->total_sect)) {
+		printf("part_offset is " LBAFU "\n", part_offset);
+		printf("total_sector is %llu\n", fs->total_sect);
+		printf("error: overflow occurs\n");
+		return;
+	}
+
+	if (remainder) {
+		blk_dread(fs->dev_desc, startblock, 1, sec_buf);
+		temp_ptr = sec_buf;
+		memcpy((temp_ptr + remainder), (unsigned char *)buf, size);
+		blk_dwrite(fs->dev_desc, startblock, 1, sec_buf);
+	} else {
+		if (size >> log2blksz != 0) {
+			blk_dwrite(fs->dev_desc, startblock, size >> log2blksz,
+				   (unsigned long *)buf);
+		} else {
+			blk_dread(fs->dev_desc, startblock, 1, sec_buf);
+			temp_ptr = sec_buf;
+			memcpy(temp_ptr, buf, size);
+			blk_dwrite(fs->dev_desc, startblock, 1,
+				   (unsigned long *)sec_buf);
+		}
+	}
+}
+
+static int _get_new_inode_no(unsigned char *buffer)
+{
+	struct ext_filesystem *fs = get_fs();
+	unsigned char input;
+	int operand, status;
+	int count = 1;
+	int j = 0;
+
+	/* get the blocksize of the filesystem */
+	unsigned char *ptr = buffer;
+	while (*ptr == 255) {
+		ptr++;
+		count += 8;
+		if (count > le32_to_cpu(ext4fs_root->sblock.inodes_per_group))
+			return -1;
+	}
+
+	for (j = 0; j < fs->blksz; j++) {
+		input = *ptr;
+		int i = 0;
+		while (i <= 7) {
+			operand = 1 << i;
+			status = input & operand;
+			if (status) {
+				i++;
+				count++;
+			} else {
+				*ptr |= operand;
+				return count;
+			}
+		}
+		ptr = ptr + 1;
+	}
+
+	return -1;
+}
+
+static int _get_new_blk_no(unsigned char *buffer)
+{
+	int operand;
+	int count = 0;
+	int i;
+	unsigned char *ptr = buffer;
+	struct ext_filesystem *fs = get_fs();
+
+	while (*ptr == 255) {
+		ptr++;
+		count += 8;
+		if (count == (fs->blksz * 8))
+			return -1;
+	}
+
+	if (fs->blksz == 1024)
+		count += 1;
+
+	for (i = 0; i <= 7; i++) {
+		operand = 1 << i;
+		if (*ptr & operand) {
+			count++;
+		} else {
+			*ptr |= operand;
+			return count;
+		}
+	}
+
+	return -1;
+}
+
+int ext4fs_set_block_bmap(long int blockno, unsigned char *buffer, int index)
+{
+	int i, remainder, status;
+	unsigned char *ptr = buffer;
+	unsigned char operand;
+	i = blockno / 8;
+	remainder = blockno % 8;
+	int blocksize = EXT2_BLOCK_SIZE(ext4fs_root);
+
+	i = i - (index * blocksize);
+	if (blocksize != 1024) {
+		ptr = ptr + i;
+		operand = 1 << remainder;
+		status = *ptr & operand;
+		if (status)
+			return -1;
+
+		*ptr = *ptr | operand;
+		return 0;
+	} else {
+		if (remainder == 0) {
+			ptr = ptr + i - 1;
+			operand = (1 << 7);
+		} else {
+			ptr = ptr + i;
+			operand = (1 << (remainder - 1));
+		}
+		status = *ptr & operand;
+		if (status)
+			return -1;
+
+		*ptr = *ptr | operand;
+		return 0;
+	}
+}
+
+void ext4fs_reset_block_bmap(long int blockno, unsigned char *buffer, int index)
+{
+	int i, remainder, status;
+	unsigned char *ptr = buffer;
+	unsigned char operand;
+	i = blockno / 8;
+	remainder = blockno % 8;
+	int blocksize = EXT2_BLOCK_SIZE(ext4fs_root);
+
+	i = i - (index * blocksize);
+	if (blocksize != 1024) {
+		ptr = ptr + i;
+		operand = (1 << remainder);
+		status = *ptr & operand;
+		if (status)
+			*ptr = *ptr & ~(operand);
+	} else {
+		if (remainder == 0) {
+			ptr = ptr + i - 1;
+			operand = (1 << 7);
+		} else {
+			ptr = ptr + i;
+			operand = (1 << (remainder - 1));
+		}
+		status = *ptr & operand;
+		if (status)
+			*ptr = *ptr & ~(operand);
+	}
+}
+
+int ext4fs_set_inode_bmap(int inode_no, unsigned char *buffer, int index)
+{
+	int i, remainder, status;
+	unsigned char *ptr = buffer;
+	unsigned char operand;
+
+	inode_no -= (index * le32_to_cpu(ext4fs_root->sblock.inodes_per_group));
+	i = inode_no / 8;
+	remainder = inode_no % 8;
+	if (remainder == 0) {
+		ptr = ptr + i - 1;
+		operand = (1 << 7);
+	} else {
+		ptr = ptr + i;
+		operand = (1 << (remainder - 1));
+	}
+	status = *ptr & operand;
+	if (status)
+		return -1;
+
+	*ptr = *ptr | operand;
+
+	return 0;
+}
+
+void ext4fs_reset_inode_bmap(int inode_no, unsigned char *buffer, int index)
+{
+	int i, remainder, status;
+	unsigned char *ptr = buffer;
+	unsigned char operand;
+
+	inode_no -= (index * le32_to_cpu(ext4fs_root->sblock.inodes_per_group));
+	i = inode_no / 8;
+	remainder = inode_no % 8;
+	if (remainder == 0) {
+		ptr = ptr + i - 1;
+		operand = (1 << 7);
+	} else {
+		ptr = ptr + i;
+		operand = (1 << (remainder - 1));
+	}
+	status = *ptr & operand;
+	if (status)
+		*ptr = *ptr & ~(operand);
+}
+
+uint16_t ext4fs_checksum_update(uint32_t i)
+{
+	struct ext2_block_group *desc;
+	struct ext_filesystem *fs = get_fs();
+	uint16_t crc = 0;
+	__le32 le32_i = cpu_to_le32(i);
+
+	desc = ext4fs_get_group_descriptor(fs, i);
+	if (le32_to_cpu(fs->sb->feature_ro_compat) & EXT4_FEATURE_RO_COMPAT_GDT_CSUM) {
+		int offset = offsetof(struct ext2_block_group, bg_checksum);
+
+		crc = ext2fs_crc16(~0, fs->sb->unique_id,
+				   sizeof(fs->sb->unique_id));
+		crc = ext2fs_crc16(crc, &le32_i, sizeof(le32_i));
+		crc = ext2fs_crc16(crc, desc, offset);
+		offset += sizeof(desc->bg_checksum);	/* skip checksum */
+		assert(offset == sizeof(*desc));
+		if (offset < fs->gdsize) {
+			crc = ext2fs_crc16(crc, (__u8 *)desc + offset,
+					   fs->gdsize - offset);
+		}
+	}
+
+	return crc;
+}
+
+static int check_void_in_dentry(struct ext2_dirent *dir, char *filename)
+{
+	int dentry_length;
+	int sizeof_void_space;
+	int new_entry_byte_reqd;
+	short padding_factor = 0;
+
+	if (dir->namelen % 4 != 0)
+		padding_factor = 4 - (dir->namelen % 4);
+
+	dentry_length = sizeof(struct ext2_dirent) +
+			dir->namelen + padding_factor;
+	sizeof_void_space = le16_to_cpu(dir->direntlen) - dentry_length;
+	if (sizeof_void_space == 0)
+		return 0;
+
+	padding_factor = 0;
+	if (strlen(filename) % 4 != 0)
+		padding_factor = 4 - (strlen(filename) % 4);
+
+	new_entry_byte_reqd = strlen(filename) +
+	    sizeof(struct ext2_dirent) + padding_factor;
+	if (sizeof_void_space >= new_entry_byte_reqd) {
+		dir->direntlen = cpu_to_le16(dentry_length);
+		return sizeof_void_space;
+	}
+
+	return 0;
+}
+
+int ext4fs_update_parent_dentry(char *filename, int file_type)
+{
+	unsigned int *zero_buffer = NULL;
+	char *root_first_block_buffer = NULL;
+	int blk_idx;
+	long int first_block_no_of_root = 0;
+	int totalbytes = 0;
+	unsigned int new_entry_byte_reqd;
+	int sizeof_void_space = 0;
+	int templength = 0;
+	int inodeno = -1;
+	int status;
+	struct ext_filesystem *fs = get_fs();
+	/* directory entry */
+	struct ext2_dirent *dir;
+	char *temp_dir = NULL;
+	uint32_t new_blk_no;
+	uint32_t new_size;
+	uint32_t new_blockcnt;
+	uint32_t directory_blocks;
+
+	zero_buffer = zalloc(fs->blksz);
+	if (!zero_buffer) {
+		printf("No Memory\n");
+		return -1;
+	}
+	root_first_block_buffer = zalloc(fs->blksz);
+	if (!root_first_block_buffer) {
+		free(zero_buffer);
+		printf("No Memory\n");
+		return -1;
+	}
+	new_entry_byte_reqd = ROUND(strlen(filename) +
+				    sizeof(struct ext2_dirent), 4);
+restart:
+	directory_blocks = le32_to_cpu(g_parent_inode->size) >>
+		LOG2_BLOCK_SIZE(ext4fs_root);
+	blk_idx = directory_blocks - 1;
+
+restart_read:
+	/* read the block no allocated to a file */
+	first_block_no_of_root = read_allocated_block(g_parent_inode, blk_idx,
+						      NULL);
+	if (first_block_no_of_root <= 0)
+		goto fail;
+
+	status = ext4fs_devread((lbaint_t)first_block_no_of_root
+				* fs->sect_perblk,
+				0, fs->blksz, root_first_block_buffer);
+	if (status == 0)
+		goto fail;
+
+	if (ext4fs_log_journal(root_first_block_buffer, first_block_no_of_root))
+		goto fail;
+	dir = (struct ext2_dirent *)root_first_block_buffer;
+	totalbytes = 0;
+
+	while (le16_to_cpu(dir->direntlen) > 0) {
+		unsigned short used_len = ROUND(dir->namelen +
+		    sizeof(struct ext2_dirent), 4);
+
+		/* last entry of block */
+		if (fs->blksz - totalbytes == le16_to_cpu(dir->direntlen)) {
+
+			/* check if new entry fits */
+			if ((used_len + new_entry_byte_reqd) <=
+			    le16_to_cpu(dir->direntlen)) {
+				dir->direntlen = cpu_to_le16(used_len);
+				break;
+			} else {
+				if (blk_idx > 0) {
+					printf("Block full, trying previous\n");
+					blk_idx--;
+					goto restart_read;
+				}
+				printf("All blocks full: Allocate new\n");
+
+				if (le32_to_cpu(g_parent_inode->flags) &
+						EXT4_EXTENTS_FL) {
+					printf("Directory uses extents\n");
+					goto fail;
+				}
+				if (directory_blocks >= INDIRECT_BLOCKS) {
+					printf("Directory exceeds limit\n");
+					goto fail;
+				}
+				new_blk_no = ext4fs_get_new_blk_no();
+				if (new_blk_no == -1) {
+					printf("no block left to assign\n");
+					goto fail;
+				}
+				put_ext4((uint64_t)new_blk_no * fs->blksz, zero_buffer, fs->blksz);
+				g_parent_inode->b.blocks.
+					dir_blocks[directory_blocks] =
+					cpu_to_le32(new_blk_no);
+
+				new_size = le32_to_cpu(g_parent_inode->size);
+				new_size += fs->blksz;
+				g_parent_inode->size = cpu_to_le32(new_size);
+
+				new_blockcnt = le32_to_cpu(g_parent_inode->blockcnt);
+				new_blockcnt += fs->blksz >> LOG2_SECTOR_SIZE;
+				g_parent_inode->blockcnt = cpu_to_le32(new_blockcnt);
+
+				if (ext4fs_put_metadata
+				    (root_first_block_buffer,
+				     first_block_no_of_root))
+					goto fail;
+				goto restart;
+			}
+		}
+
+		templength = le16_to_cpu(dir->direntlen);
+		totalbytes = totalbytes + templength;
+		sizeof_void_space = check_void_in_dentry(dir, filename);
+		if (sizeof_void_space)
+			break;
+
+		dir = (struct ext2_dirent *)((char *)dir + templength);
+	}
+
+	/* make a pointer ready for creating next directory entry */
+	templength = le16_to_cpu(dir->direntlen);
+	totalbytes = totalbytes + templength;
+	dir = (struct ext2_dirent *)((char *)dir + templength);
+
+	/* get the next available inode number */
+	inodeno = ext4fs_get_new_inode_no();
+	if (inodeno == -1) {
+		printf("no inode left to assign\n");
+		goto fail;
+	}
+	dir->inode = cpu_to_le32(inodeno);
+	if (sizeof_void_space)
+		dir->direntlen = cpu_to_le16(sizeof_void_space);
+	else
+		dir->direntlen = cpu_to_le16(fs->blksz - totalbytes);
+
+	dir->namelen = strlen(filename);
+	dir->filetype = file_type;
+	temp_dir = (char *)dir;
+	temp_dir = temp_dir + sizeof(struct ext2_dirent);
+	memcpy(temp_dir, filename, strlen(filename));
+
+	/* update or write  the 1st block of root inode */
+	if (ext4fs_put_metadata(root_first_block_buffer,
+				first_block_no_of_root))
+		goto fail;
+
+fail:
+	free(zero_buffer);
+	free(root_first_block_buffer);
+
+	return inodeno;
+}
+
+static int search_dir(struct ext2_inode *parent_inode, char *dirname)
+{
+	int status;
+	int inodeno = 0;
+	int offset;
+	int blk_idx;
+	long int blknr;
+	char *block_buffer = NULL;
+	struct ext2_dirent *dir = NULL;
+	struct ext_filesystem *fs = get_fs();
+	uint32_t directory_blocks;
+	char *direntname;
+
+	directory_blocks = le32_to_cpu(parent_inode->size) >>
+		LOG2_BLOCK_SIZE(ext4fs_root);
+
+	block_buffer = zalloc(fs->blksz);
+	if (!block_buffer)
+		goto fail;
+
+	/* get the block no allocated to a file */
+	for (blk_idx = 0; blk_idx < directory_blocks; blk_idx++) {
+		blknr = read_allocated_block(parent_inode, blk_idx, NULL);
+		if (blknr <= 0)
+			goto fail;
+
+		/* read the directory block */
+		status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk,
+					0, fs->blksz, (char *)block_buffer);
+		if (status == 0)
+			goto fail;
+
+		offset = 0;
+		do {
+			if (offset & 3) {
+				printf("Badly aligned ext2_dirent\n");
+				break;
+			}
+
+			dir = (struct ext2_dirent *)(block_buffer + offset);
+			direntname = (char*)(dir) + sizeof(struct ext2_dirent);
+
+			int direntlen = le16_to_cpu(dir->direntlen);
+			if (direntlen < sizeof(struct ext2_dirent))
+				break;
+
+			if (dir->inode && (strlen(dirname) == dir->namelen) &&
+			    (strncmp(dirname, direntname, dir->namelen) == 0)) {
+				inodeno = le32_to_cpu(dir->inode);
+				break;
+			}
+
+			offset += direntlen;
+
+		} while (offset < fs->blksz);
+
+		if (inodeno > 0) {
+			free(block_buffer);
+			return inodeno;
+		}
+	}
+
+fail:
+	free(block_buffer);
+
+	return -1;
+}
+
+static int find_dir_depth(char *dirname)
+{
+	char *token = strtok(dirname, "/");
+	int count = 0;
+	while (token != NULL) {
+		token = strtok(NULL, "/");
+		count++;
+	}
+	return count + 1 + 1;
+	/*
+	 * for example  for string /home/temp
+	 * depth=home(1)+temp(1)+1 extra for NULL;
+	 * so count is 4;
+	 */
+}
+
+static int parse_path(char **arr, char *dirname)
+{
+	char *token = strtok(dirname, "/");
+	int i = 0;
+
+	/* add root */
+	arr[i] = zalloc(strlen("/") + 1);
+	if (!arr[i])
+		return -ENOMEM;
+	memcpy(arr[i++], "/", strlen("/"));
+
+	/* add each path entry after root */
+	while (token != NULL) {
+		arr[i] = zalloc(strlen(token) + 1);
+		if (!arr[i])
+			return -ENOMEM;
+		memcpy(arr[i++], token, strlen(token));
+		token = strtok(NULL, "/");
+	}
+	arr[i] = NULL;
+
+	return 0;
+}
+
+int ext4fs_iget(int inode_no, struct ext2_inode *inode)
+{
+	if (ext4fs_read_inode(ext4fs_root, inode_no, inode) == 0)
+		return -1;
+
+	return 0;
+}
+
+/*
+ * Function: ext4fs_get_parent_inode_num
+ * Return Value: inode Number of the parent directory of  file/Directory to be
+ * created
+ * dirname : Input parmater, input path name of the file/directory to be created
+ * dname : Output parameter, to be filled with the name of the directory
+ * extracted from dirname
+ */
+int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags)
+{
+	int i;
+	int depth = 0;
+	int matched_inode_no;
+	int result_inode_no = -1;
+	char **ptr = NULL;
+	char *depth_dirname = NULL;
+	char *parse_dirname = NULL;
+	struct ext2_inode *parent_inode = NULL;
+	struct ext2_inode *first_inode = NULL;
+	struct ext2_inode temp_inode;
+
+	if (*dirname != '/') {
+		printf("Please supply Absolute path\n");
+		return -1;
+	}
+
+	/* TODO: input validation make equivalent to linux */
+	depth_dirname = zalloc(strlen(dirname) + 1);
+	if (!depth_dirname)
+		return -ENOMEM;
+
+	memcpy(depth_dirname, dirname, strlen(dirname));
+	depth = find_dir_depth(depth_dirname);
+	parse_dirname = zalloc(strlen(dirname) + 1);
+	if (!parse_dirname)
+		goto fail;
+	memcpy(parse_dirname, dirname, strlen(dirname));
+
+	/* allocate memory for each directory level */
+	ptr = zalloc((depth) * sizeof(char *));
+	if (!ptr)
+		goto fail;
+	if (parse_path(ptr, parse_dirname))
+		goto fail;
+	parent_inode = zalloc(sizeof(struct ext2_inode));
+	if (!parent_inode)
+		goto fail;
+	first_inode = zalloc(sizeof(struct ext2_inode));
+	if (!first_inode)
+		goto fail;
+	memcpy(parent_inode, ext4fs_root->inode, sizeof(struct ext2_inode));
+	memcpy(first_inode, parent_inode, sizeof(struct ext2_inode));
+	if (flags & F_FILE)
+		result_inode_no = EXT2_ROOT_INO;
+	for (i = 1; i < depth; i++) {
+		matched_inode_no = search_dir(parent_inode, ptr[i]);
+		if (matched_inode_no == -1) {
+			if (ptr[i + 1] == NULL && i == 1) {
+				result_inode_no = EXT2_ROOT_INO;
+				goto end;
+			} else {
+				if (ptr[i + 1] == NULL)
+					break;
+				printf("Invalid path\n");
+				result_inode_no = -1;
+				goto fail;
+			}
+		} else {
+			if (ptr[i + 1] != NULL) {
+				memset(parent_inode, '\0',
+				       sizeof(struct ext2_inode));
+				if (ext4fs_iget(matched_inode_no,
+						parent_inode)) {
+					result_inode_no = -1;
+					goto fail;
+				}
+				result_inode_no = matched_inode_no;
+			} else {
+				break;
+			}
+		}
+	}
+
+end:
+	if (i == 1)
+		matched_inode_no = search_dir(first_inode, ptr[i]);
+	else
+		matched_inode_no = search_dir(parent_inode, ptr[i]);
+
+	if (matched_inode_no != -1) {
+		ext4fs_iget(matched_inode_no, &temp_inode);
+		if (le16_to_cpu(temp_inode.mode) & S_IFDIR) {
+			printf("It is a Directory\n");
+			result_inode_no = -1;
+			goto fail;
+		}
+	}
+
+	if (strlen(ptr[i]) > 256) {
+		result_inode_no = -1;
+		goto fail;
+	}
+	memcpy(dname, ptr[i], strlen(ptr[i]));
+
+fail:
+	free(depth_dirname);
+	free(parse_dirname);
+	for (i = 0; i < depth; i++) {
+		if (!ptr[i])
+			break;
+		free(ptr[i]);
+	}
+	free(ptr);
+	free(parent_inode);
+	free(first_inode);
+
+	return result_inode_no;
+}
+
+static int unlink_filename(char *filename, unsigned int blknr)
+{
+	int status;
+	int inodeno = 0;
+	int offset;
+	char *block_buffer = NULL;
+	struct ext2_dirent *dir = NULL;
+	struct ext2_dirent *previous_dir;
+	struct ext_filesystem *fs = get_fs();
+	int ret = -1;
+	char *direntname;
+
+	block_buffer = zalloc(fs->blksz);
+	if (!block_buffer)
+		return -ENOMEM;
+
+	/* read the directory block */
+	status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0,
+				fs->blksz, block_buffer);
+	if (status == 0)
+		goto fail;
+
+	offset = 0;
+	do {
+		if (offset & 3) {
+			printf("Badly aligned ext2_dirent\n");
+			break;
+		}
+
+		previous_dir = dir;
+		dir = (struct ext2_dirent *)(block_buffer + offset);
+		direntname = (char *)(dir) + sizeof(struct ext2_dirent);
+
+		int direntlen = le16_to_cpu(dir->direntlen);
+		if (direntlen < sizeof(struct ext2_dirent))
+			break;
+
+		if (dir->inode && (strlen(filename) == dir->namelen) &&
+		    (strncmp(direntname, filename, dir->namelen) == 0)) {
+			inodeno = le32_to_cpu(dir->inode);
+			break;
+		}
+
+		offset += direntlen;
+
+	} while (offset < fs->blksz);
+
+	if (inodeno > 0) {
+		printf("file found, deleting\n");
+		if (ext4fs_log_journal(block_buffer, blknr))
+			goto fail;
+
+		if (previous_dir) {
+			/* merge dir entry with predecessor */
+			uint16_t new_len;
+			new_len = le16_to_cpu(previous_dir->direntlen);
+			new_len += le16_to_cpu(dir->direntlen);
+			previous_dir->direntlen = cpu_to_le16(new_len);
+		} else {
+			/* invalidate dir entry */
+			dir->inode = 0;
+		}
+		if (ext4fs_put_metadata(block_buffer, blknr))
+			goto fail;
+		ret = inodeno;
+	}
+fail:
+	free(block_buffer);
+
+	return ret;
+}
+
+int ext4fs_filename_unlink(char *filename)
+{
+	int blk_idx;
+	long int blknr = -1;
+	int inodeno = -1;
+	uint32_t directory_blocks;
+
+	directory_blocks = le32_to_cpu(g_parent_inode->size) >>
+		LOG2_BLOCK_SIZE(ext4fs_root);
+
+	/* read the block no allocated to a file */
+	for (blk_idx = 0; blk_idx < directory_blocks; blk_idx++) {
+		blknr = read_allocated_block(g_parent_inode, blk_idx, NULL);
+		if (blknr <= 0)
+			break;
+		inodeno = unlink_filename(filename, blknr);
+		if (inodeno != -1)
+			return inodeno;
+	}
+
+	return -1;
+}
+
+uint32_t ext4fs_get_new_blk_no(void)
+{
+	short i;
+	short status;
+	int remainder;
+	unsigned int bg_idx;
+	static int prev_bg_bitmap_index = -1;
+	unsigned int blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group);
+	struct ext_filesystem *fs = get_fs();
+	char *journal_buffer = zalloc(fs->blksz);
+	char *zero_buffer = zalloc(fs->blksz);
+	if (!journal_buffer || !zero_buffer)
+		goto fail;
+
+	if (fs->first_pass_bbmap == 0) {
+		for (i = 0; i < fs->no_blkgrp; i++) {
+			struct ext2_block_group *bgd = NULL;
+			bgd = ext4fs_get_group_descriptor(fs, i);
+			if (ext4fs_bg_get_free_blocks(bgd, fs)) {
+				uint16_t bg_flags = ext4fs_bg_get_flags(bgd);
+				uint64_t b_bitmap_blk =
+					ext4fs_bg_get_block_id(bgd, fs);
+				if (bg_flags & EXT4_BG_BLOCK_UNINIT) {
+					memcpy(fs->blk_bmaps[i], zero_buffer,
+					       fs->blksz);
+					put_ext4(b_bitmap_blk * fs->blksz,
+						 fs->blk_bmaps[i], fs->blksz);
+					bg_flags &= ~EXT4_BG_BLOCK_UNINIT;
+					ext4fs_bg_set_flags(bgd, bg_flags);
+				}
+				fs->curr_blkno =
+				    _get_new_blk_no(fs->blk_bmaps[i]);
+				if (fs->curr_blkno == -1)
+					/* block bitmap is completely filled */
+					continue;
+				fs->curr_blkno = fs->curr_blkno +
+						(i * fs->blksz * 8);
+				fs->first_pass_bbmap++;
+				ext4fs_bg_free_blocks_dec(bgd, fs);
+				ext4fs_sb_free_blocks_dec(fs->sb);
+				status = ext4fs_devread(b_bitmap_blk *
+							fs->sect_perblk,
+							0, fs->blksz,
+							journal_buffer);
+				if (status == 0)
+					goto fail;
+				if (ext4fs_log_journal(journal_buffer,
+						       b_bitmap_blk))
+					goto fail;
+				goto success;
+			} else {
+				debug("no space left on block group %d\n", i);
+			}
+		}
+
+		goto fail;
+	} else {
+		fs->curr_blkno++;
+restart:
+		/* get the blockbitmap index respective to blockno */
+		bg_idx = fs->curr_blkno / blk_per_grp;
+		if (fs->blksz == 1024) {
+			remainder = fs->curr_blkno % blk_per_grp;
+			if (!remainder)
+				bg_idx--;
+		}
+
+		/*
+		 * To skip completely filled block group bitmaps
+		 * Optimize the block allocation
+		 */
+		if (bg_idx >= fs->no_blkgrp)
+			goto fail;
+
+		struct ext2_block_group *bgd = NULL;
+		bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+		if (ext4fs_bg_get_free_blocks(bgd, fs) == 0) {
+			debug("block group %u is full. Skipping\n", bg_idx);
+			fs->curr_blkno = (bg_idx + 1) * blk_per_grp;
+			if (fs->blksz == 1024)
+				fs->curr_blkno += 1;
+			goto restart;
+		}
+
+		uint16_t bg_flags = ext4fs_bg_get_flags(bgd);
+		uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+		if (bg_flags & EXT4_BG_BLOCK_UNINIT) {
+			memcpy(fs->blk_bmaps[bg_idx], zero_buffer, fs->blksz);
+			put_ext4(b_bitmap_blk * fs->blksz,
+				 zero_buffer, fs->blksz);
+			bg_flags &= ~EXT4_BG_BLOCK_UNINIT;
+			ext4fs_bg_set_flags(bgd, bg_flags);
+		}
+
+		if (ext4fs_set_block_bmap(fs->curr_blkno, fs->blk_bmaps[bg_idx],
+				   bg_idx) != 0) {
+			debug("going for restart for the block no %ld %u\n",
+			      fs->curr_blkno, bg_idx);
+			fs->curr_blkno++;
+			goto restart;
+		}
+
+		/* journal backup */
+		if (prev_bg_bitmap_index != bg_idx) {
+			status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk,
+						0, fs->blksz, journal_buffer);
+			if (status == 0)
+				goto fail;
+			if (ext4fs_log_journal(journal_buffer, b_bitmap_blk))
+				goto fail;
+
+			prev_bg_bitmap_index = bg_idx;
+		}
+		ext4fs_bg_free_blocks_dec(bgd, fs);
+		ext4fs_sb_free_blocks_dec(fs->sb);
+		goto success;
+	}
+success:
+	free(journal_buffer);
+	free(zero_buffer);
+
+	return fs->curr_blkno;
+fail:
+	free(journal_buffer);
+	free(zero_buffer);
+
+	return -1;
+}
+
+int ext4fs_get_new_inode_no(void)
+{
+	short i;
+	short status;
+	unsigned int ibmap_idx;
+	static int prev_inode_bitmap_index = -1;
+	unsigned int inodes_per_grp = le32_to_cpu(ext4fs_root->sblock.inodes_per_group);
+	struct ext_filesystem *fs = get_fs();
+	char *journal_buffer = zalloc(fs->blksz);
+	char *zero_buffer = zalloc(fs->blksz);
+	if (!journal_buffer || !zero_buffer)
+		goto fail;
+	int has_gdt_chksum = le32_to_cpu(fs->sb->feature_ro_compat) &
+		EXT4_FEATURE_RO_COMPAT_GDT_CSUM ? 1 : 0;
+
+	if (fs->first_pass_ibmap == 0) {
+		for (i = 0; i < fs->no_blkgrp; i++) {
+			uint32_t free_inodes;
+			struct ext2_block_group *bgd = NULL;
+			bgd = ext4fs_get_group_descriptor(fs, i);
+			free_inodes = ext4fs_bg_get_free_inodes(bgd, fs);
+			if (free_inodes) {
+				uint16_t bg_flags = ext4fs_bg_get_flags(bgd);
+				uint64_t i_bitmap_blk =
+					ext4fs_bg_get_inode_id(bgd, fs);
+				if (has_gdt_chksum)
+					bgd->bg_itable_unused = free_inodes;
+				if (bg_flags & EXT4_BG_INODE_UNINIT) {
+					put_ext4(i_bitmap_blk * fs->blksz,
+						 zero_buffer, fs->blksz);
+					bg_flags &= ~EXT4_BG_INODE_UNINIT;
+					ext4fs_bg_set_flags(bgd, bg_flags);
+					memcpy(fs->inode_bmaps[i],
+					       zero_buffer, fs->blksz);
+				}
+				fs->curr_inode_no =
+				    _get_new_inode_no(fs->inode_bmaps[i]);
+				if (fs->curr_inode_no == -1)
+					/* inode bitmap is completely filled */
+					continue;
+				fs->curr_inode_no = fs->curr_inode_no +
+							(i * inodes_per_grp);
+				fs->first_pass_ibmap++;
+				ext4fs_bg_free_inodes_dec(bgd, fs);
+				if (has_gdt_chksum)
+					ext4fs_bg_itable_unused_dec(bgd, fs);
+				ext4fs_sb_free_inodes_dec(fs->sb);
+				status = ext4fs_devread(i_bitmap_blk *
+							fs->sect_perblk,
+							0, fs->blksz,
+							journal_buffer);
+				if (status == 0)
+					goto fail;
+				if (ext4fs_log_journal(journal_buffer,
+						       i_bitmap_blk))
+					goto fail;
+				goto success;
+			} else
+				debug("no inode left on block group %d\n", i);
+		}
+		goto fail;
+	} else {
+restart:
+		fs->curr_inode_no++;
+		/* get the blockbitmap index respective to blockno */
+		ibmap_idx = fs->curr_inode_no / inodes_per_grp;
+		struct ext2_block_group *bgd =
+			ext4fs_get_group_descriptor(fs, ibmap_idx);
+		uint16_t bg_flags = ext4fs_bg_get_flags(bgd);
+		uint64_t i_bitmap_blk = ext4fs_bg_get_inode_id(bgd, fs);
+
+		if (bg_flags & EXT4_BG_INODE_UNINIT) {
+			put_ext4(i_bitmap_blk * fs->blksz,
+				 zero_buffer, fs->blksz);
+			bg_flags &= ~EXT4_BG_INODE_UNINIT;
+			ext4fs_bg_set_flags(bgd, bg_flags);
+			memcpy(fs->inode_bmaps[ibmap_idx], zero_buffer,
+				fs->blksz);
+		}
+
+		if (ext4fs_set_inode_bmap(fs->curr_inode_no,
+					  fs->inode_bmaps[ibmap_idx],
+					  ibmap_idx) != 0) {
+			debug("going for restart for the block no %d %u\n",
+			      fs->curr_inode_no, ibmap_idx);
+			goto restart;
+		}
+
+		/* journal backup */
+		if (prev_inode_bitmap_index != ibmap_idx) {
+			status = ext4fs_devread(i_bitmap_blk * fs->sect_perblk,
+						0, fs->blksz, journal_buffer);
+			if (status == 0)
+				goto fail;
+			if (ext4fs_log_journal(journal_buffer,
+						le32_to_cpu(bgd->inode_id)))
+				goto fail;
+			prev_inode_bitmap_index = ibmap_idx;
+		}
+		ext4fs_bg_free_inodes_dec(bgd, fs);
+		if (has_gdt_chksum)
+			bgd->bg_itable_unused = bgd->free_inodes;
+		ext4fs_sb_free_inodes_dec(fs->sb);
+		goto success;
+	}
+
+success:
+	free(journal_buffer);
+	free(zero_buffer);
+
+	return fs->curr_inode_no;
+fail:
+	free(journal_buffer);
+	free(zero_buffer);
+
+	return -1;
+
+}
+
+
+static void alloc_single_indirect_block(struct ext2_inode *file_inode,
+					unsigned int *total_remaining_blocks,
+					unsigned int *no_blks_reqd)
+{
+	short i;
+	short status;
+	long int actual_block_no;
+	long int si_blockno;
+	/* si :single indirect */
+	__le32 *si_buffer = NULL;
+	__le32 *si_start_addr = NULL;
+	struct ext_filesystem *fs = get_fs();
+
+	if (*total_remaining_blocks != 0) {
+		si_buffer = zalloc(fs->blksz);
+		if (!si_buffer) {
+			printf("No Memory\n");
+			return;
+		}
+		si_start_addr = si_buffer;
+		si_blockno = ext4fs_get_new_blk_no();
+		if (si_blockno == -1) {
+			printf("no block left to assign\n");
+			goto fail;
+		}
+		(*no_blks_reqd)++;
+		debug("SIPB %ld: %u\n", si_blockno, *total_remaining_blocks);
+
+		status = ext4fs_devread((lbaint_t)si_blockno * fs->sect_perblk,
+					0, fs->blksz, (char *)si_buffer);
+		memset(si_buffer, '\0', fs->blksz);
+		if (status == 0)
+			goto fail;
+
+		for (i = 0; i < (fs->blksz / sizeof(int)); i++) {
+			actual_block_no = ext4fs_get_new_blk_no();
+			if (actual_block_no == -1) {
+				printf("no block left to assign\n");
+				goto fail;
+			}
+			*si_buffer = cpu_to_le32(actual_block_no);
+			debug("SIAB %u: %u\n", *si_buffer,
+				*total_remaining_blocks);
+
+			si_buffer++;
+			(*total_remaining_blocks)--;
+			if (*total_remaining_blocks == 0)
+				break;
+		}
+
+		/* write the block to disk */
+		put_ext4(((uint64_t) ((uint64_t)si_blockno * (uint64_t)fs->blksz)),
+			 si_start_addr, fs->blksz);
+		file_inode->b.blocks.indir_block = cpu_to_le32(si_blockno);
+	}
+fail:
+	free(si_start_addr);
+}
+
+static void alloc_double_indirect_block(struct ext2_inode *file_inode,
+					unsigned int *total_remaining_blocks,
+					unsigned int *no_blks_reqd)
+{
+	short i;
+	short j;
+	short status;
+	long int actual_block_no;
+	/* di:double indirect */
+	long int di_blockno_parent;
+	long int di_blockno_child;
+	__le32 *di_parent_buffer = NULL;
+	__le32 *di_child_buff = NULL;
+	__le32 *di_block_start_addr = NULL;
+	__le32 *di_child_buff_start = NULL;
+	struct ext_filesystem *fs = get_fs();
+
+	if (*total_remaining_blocks != 0) {
+		/* double indirect parent block connecting to inode */
+		di_blockno_parent = ext4fs_get_new_blk_no();
+		if (di_blockno_parent == -1) {
+			printf("no block left to assign\n");
+			goto fail;
+		}
+		di_parent_buffer = zalloc(fs->blksz);
+		if (!di_parent_buffer)
+			goto fail;
+
+		di_block_start_addr = di_parent_buffer;
+		(*no_blks_reqd)++;
+		debug("DIPB %ld: %u\n", di_blockno_parent,
+		      *total_remaining_blocks);
+
+		status = ext4fs_devread((lbaint_t)di_blockno_parent *
+					fs->sect_perblk, 0,
+					fs->blksz, (char *)di_parent_buffer);
+
+		if (!status) {
+			printf("%s: Device read error!\n", __func__);
+			goto fail;
+		}
+		memset(di_parent_buffer, '\0', fs->blksz);
+
+		/*
+		 * start:for each double indirect parent
+		 * block create one more block
+		 */
+		for (i = 0; i < (fs->blksz / sizeof(int)); i++) {
+			di_blockno_child = ext4fs_get_new_blk_no();
+			if (di_blockno_child == -1) {
+				printf("no block left to assign\n");
+				goto fail;
+			}
+			di_child_buff = zalloc(fs->blksz);
+			if (!di_child_buff)
+				goto fail;
+
+			di_child_buff_start = di_child_buff;
+			*di_parent_buffer = cpu_to_le32(di_blockno_child);
+			di_parent_buffer++;
+			(*no_blks_reqd)++;
+			debug("DICB %ld: %u\n", di_blockno_child,
+			      *total_remaining_blocks);
+
+			status = ext4fs_devread((lbaint_t)di_blockno_child *
+						fs->sect_perblk, 0,
+						fs->blksz,
+						(char *)di_child_buff);
+
+			if (!status) {
+				printf("%s: Device read error!\n", __func__);
+				goto fail;
+			}
+			memset(di_child_buff, '\0', fs->blksz);
+			/* filling of actual datablocks for each child */
+			for (j = 0; j < (fs->blksz / sizeof(int)); j++) {
+				actual_block_no = ext4fs_get_new_blk_no();
+				if (actual_block_no == -1) {
+					printf("no block left to assign\n");
+					goto fail;
+				}
+				*di_child_buff = cpu_to_le32(actual_block_no);
+				debug("DIAB %ld: %u\n", actual_block_no,
+				      *total_remaining_blocks);
+
+				di_child_buff++;
+				(*total_remaining_blocks)--;
+				if (*total_remaining_blocks == 0)
+					break;
+			}
+			/* write the block  table */
+			put_ext4(((uint64_t) ((uint64_t)di_blockno_child * (uint64_t)fs->blksz)),
+				 di_child_buff_start, fs->blksz);
+			free(di_child_buff_start);
+			di_child_buff_start = NULL;
+
+			if (*total_remaining_blocks == 0)
+				break;
+		}
+		put_ext4(((uint64_t) ((uint64_t)di_blockno_parent * (uint64_t)fs->blksz)),
+			 di_block_start_addr, fs->blksz);
+		file_inode->b.blocks.double_indir_block = cpu_to_le32(di_blockno_parent);
+	}
+fail:
+	free(di_block_start_addr);
+}
+
+static void alloc_triple_indirect_block(struct ext2_inode *file_inode,
+					unsigned int *total_remaining_blocks,
+					unsigned int *no_blks_reqd)
+{
+	short i;
+	short j;
+	short k;
+	long int actual_block_no;
+	/* ti: Triple Indirect */
+	long int ti_gp_blockno;
+	long int ti_parent_blockno;
+	long int ti_child_blockno;
+	__le32 *ti_gp_buff = NULL;
+	__le32 *ti_parent_buff = NULL;
+	__le32 *ti_child_buff = NULL;
+	__le32 *ti_gp_buff_start_addr = NULL;
+	__le32 *ti_pbuff_start_addr = NULL;
+	__le32 *ti_cbuff_start_addr = NULL;
+	struct ext_filesystem *fs = get_fs();
+	if (*total_remaining_blocks != 0) {
+		/* triple indirect grand parent block connecting to inode */
+		ti_gp_blockno = ext4fs_get_new_blk_no();
+		if (ti_gp_blockno == -1) {
+			printf("no block left to assign\n");
+			return;
+		}
+		ti_gp_buff = zalloc(fs->blksz);
+		if (!ti_gp_buff)
+			return;
+
+		ti_gp_buff_start_addr = ti_gp_buff;
+		(*no_blks_reqd)++;
+		debug("TIGPB %ld: %u\n", ti_gp_blockno,
+		      *total_remaining_blocks);
+
+		/* for each 4 byte grand parent entry create one more block */
+		for (i = 0; i < (fs->blksz / sizeof(int)); i++) {
+			ti_parent_blockno = ext4fs_get_new_blk_no();
+			if (ti_parent_blockno == -1) {
+				printf("no block left to assign\n");
+				goto fail;
+			}
+			ti_parent_buff = zalloc(fs->blksz);
+			if (!ti_parent_buff)
+				goto fail;
+
+			ti_pbuff_start_addr = ti_parent_buff;
+			*ti_gp_buff = cpu_to_le32(ti_parent_blockno);
+			ti_gp_buff++;
+			(*no_blks_reqd)++;
+			debug("TIPB %ld: %u\n", ti_parent_blockno,
+			      *total_remaining_blocks);
+
+			/* for each 4 byte entry parent create one more block */
+			for (j = 0; j < (fs->blksz / sizeof(int)); j++) {
+				ti_child_blockno = ext4fs_get_new_blk_no();
+				if (ti_child_blockno == -1) {
+					printf("no block left assign\n");
+					goto fail1;
+				}
+				ti_child_buff = zalloc(fs->blksz);
+				if (!ti_child_buff)
+					goto fail1;
+
+				ti_cbuff_start_addr = ti_child_buff;
+				*ti_parent_buff = cpu_to_le32(ti_child_blockno);
+				ti_parent_buff++;
+				(*no_blks_reqd)++;
+				debug("TICB %ld: %u\n", ti_parent_blockno,
+				      *total_remaining_blocks);
+
+				/* fill actual datablocks for each child */
+				for (k = 0; k < (fs->blksz / sizeof(int));
+					k++) {
+					actual_block_no =
+					    ext4fs_get_new_blk_no();
+					if (actual_block_no == -1) {
+						printf("no block left\n");
+						free(ti_cbuff_start_addr);
+						goto fail1;
+					}
+					*ti_child_buff = cpu_to_le32(actual_block_no);
+					debug("TIAB %ld: %u\n", actual_block_no,
+					      *total_remaining_blocks);
+
+					ti_child_buff++;
+					(*total_remaining_blocks)--;
+					if (*total_remaining_blocks == 0)
+						break;
+				}
+				/* write the child block */
+				put_ext4(((uint64_t) ((uint64_t)ti_child_blockno *
+						      (uint64_t)fs->blksz)),
+					 ti_cbuff_start_addr, fs->blksz);
+				free(ti_cbuff_start_addr);
+
+				if (*total_remaining_blocks == 0)
+					break;
+			}
+			/* write the parent block */
+			put_ext4(((uint64_t) ((uint64_t)ti_parent_blockno * (uint64_t)fs->blksz)),
+				 ti_pbuff_start_addr, fs->blksz);
+			free(ti_pbuff_start_addr);
+
+			if (*total_remaining_blocks == 0)
+				break;
+		}
+		/* write the grand parent block */
+		put_ext4(((uint64_t) ((uint64_t)ti_gp_blockno * (uint64_t)fs->blksz)),
+			 ti_gp_buff_start_addr, fs->blksz);
+		file_inode->b.blocks.triple_indir_block = cpu_to_le32(ti_gp_blockno);
+		free(ti_gp_buff_start_addr);
+		return;
+	}
+fail1:
+	free(ti_pbuff_start_addr);
+fail:
+	free(ti_gp_buff_start_addr);
+}
+
+void ext4fs_allocate_blocks(struct ext2_inode *file_inode,
+				unsigned int total_remaining_blocks,
+				unsigned int *total_no_of_block)
+{
+	short i;
+	long int direct_blockno;
+	unsigned int no_blks_reqd = 0;
+
+	/* allocation of direct blocks */
+	for (i = 0; total_remaining_blocks && i < INDIRECT_BLOCKS; i++) {
+		direct_blockno = ext4fs_get_new_blk_no();
+		if (direct_blockno == -1) {
+			printf("no block left to assign\n");
+			return;
+		}
+		file_inode->b.blocks.dir_blocks[i] = cpu_to_le32(direct_blockno);
+		debug("DB %ld: %u\n", direct_blockno, total_remaining_blocks);
+
+		total_remaining_blocks--;
+	}
+
+	alloc_single_indirect_block(file_inode, &total_remaining_blocks,
+				    &no_blks_reqd);
+	alloc_double_indirect_block(file_inode, &total_remaining_blocks,
+				    &no_blks_reqd);
+	alloc_triple_indirect_block(file_inode, &total_remaining_blocks,
+				    &no_blks_reqd);
+	*total_no_of_block += no_blks_reqd;
+}
+
+#endif
+
+static struct ext4_extent_header *ext4fs_get_extent_block
+	(struct ext2_data *data, struct ext_block_cache *cache,
+		struct ext4_extent_header *ext_block,
+		uint32_t fileblock, int log2_blksz)
+{
+	struct ext4_extent_idx *index;
+	unsigned long long block;
+	int blksz = EXT2_BLOCK_SIZE(data);
+	int i;
+
+	while (1) {
+		index = (struct ext4_extent_idx *)(ext_block + 1);
+
+		if (le16_to_cpu(ext_block->eh_magic) != EXT4_EXT_MAGIC)
+			return NULL;
+
+		if (ext_block->eh_depth == 0)
+			return ext_block;
+		i = -1;
+		do {
+			i++;
+			if (i >= le16_to_cpu(ext_block->eh_entries))
+				break;
+		} while (fileblock >= le32_to_cpu(index[i].ei_block));
+
+		/*
+		 * If first logical block number is higher than requested fileblock,
+		 * it is a sparse file. This is handled on upper layer.
+		 */
+		if (i > 0)
+			i--;
+
+		block = le16_to_cpu(index[i].ei_leaf_hi);
+		block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo);
+		block <<= log2_blksz;
+		if (!ext_cache_read(cache, (lbaint_t)block, blksz))
+			return NULL;
+		ext_block = (struct ext4_extent_header *)cache->buf;
+	}
+}
+
+static int ext4fs_blockgroup
+	(struct ext2_data *data, int group, struct ext2_block_group *blkgrp)
+{
+	long int blkno;
+	unsigned int blkoff, desc_per_blk;
+	int log2blksz = get_fs()->dev_desc->log2blksz;
+	int desc_size = get_fs()->gdsize;
+
+	if (desc_size == 0)
+		return 0;
+	desc_per_blk = EXT2_BLOCK_SIZE(data) / desc_size;
+
+	if (desc_per_blk == 0)
+		return 0;
+	blkno = le32_to_cpu(data->sblock.first_data_block) + 1 +
+			group / desc_per_blk;
+	blkoff = (group % desc_per_blk) * desc_size;
+
+	debug("ext4fs read %d group descriptor (blkno %ld blkoff %u)\n",
+	      group, blkno, blkoff);
+
+	return ext4fs_devread((lbaint_t)blkno <<
+			      (LOG2_BLOCK_SIZE(data) - log2blksz),
+			      blkoff, desc_size, (char *)blkgrp);
+}
+
+int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode *inode)
+{
+	struct ext2_block_group *blkgrp;
+	struct ext2_sblock *sblock = &data->sblock;
+	struct ext_filesystem *fs = get_fs();
+	int log2blksz = get_fs()->dev_desc->log2blksz;
+	int inodes_per_block, status;
+	long int blkno;
+	unsigned int blkoff;
+
+	/* Allocate blkgrp based on gdsize (for 64-bit support). */
+	blkgrp = zalloc(get_fs()->gdsize);
+	if (!blkgrp)
+		return 0;
+
+	/* It is easier to calculate if the first inode is 0. */
+	ino--;
+	if ( le32_to_cpu(sblock->inodes_per_group) == 0 || fs->inodesz == 0) {
+		free(blkgrp);
+		return 0;
+	}
+	status = ext4fs_blockgroup(data, ino / le32_to_cpu
+				   (sblock->inodes_per_group), blkgrp);
+	if (status == 0) {
+		free(blkgrp);
+		return 0;
+	}
+
+	inodes_per_block = EXT2_BLOCK_SIZE(data) / fs->inodesz;
+	if ( inodes_per_block == 0 ) {
+		free(blkgrp);
+		return 0;
+	}
+	blkno = ext4fs_bg_get_inode_table_id(blkgrp, fs) +
+	    (ino % le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
+	blkoff = (ino % inodes_per_block) * fs->inodesz;
+
+	/* Free blkgrp as it is no longer required. */
+	free(blkgrp);
+
+	/* Read the inode. */
+	status = ext4fs_devread((lbaint_t)blkno << (LOG2_BLOCK_SIZE(data) -
+				log2blksz), blkoff,
+				sizeof(struct ext2_inode), (char *)inode);
+	if (status == 0)
+		return 0;
+
+	return 1;
+}
+
+long int read_allocated_block(struct ext2_inode *inode, int fileblock,
+			      struct ext_block_cache *cache)
+{
+	long int blknr;
+	int blksz;
+	int log2_blksz;
+	int status;
+	long int rblock;
+	long int perblock_parent;
+	long int perblock_child;
+	unsigned long long start;
+	/* get the blocksize of the filesystem */
+	blksz = EXT2_BLOCK_SIZE(ext4fs_root);
+	log2_blksz = LOG2_BLOCK_SIZE(ext4fs_root)
+		- get_fs()->dev_desc->log2blksz;
+
+	if (le32_to_cpu(inode->flags) & EXT4_EXTENTS_FL) {
+		long int startblock, endblock;
+		struct ext_block_cache *c, cd;
+		struct ext4_extent_header *ext_block;
+		struct ext4_extent *extent;
+		int i;
+
+		if (cache) {
+			c = cache;
+		} else {
+			c = &cd;
+			ext_cache_init(c);
+		}
+		ext_block =
+			ext4fs_get_extent_block(ext4fs_root, c,
+						(struct ext4_extent_header *)
+						inode->b.blocks.dir_blocks,
+						fileblock, log2_blksz);
+		if (!ext_block) {
+			printf("invalid extent block\n");
+			if (!cache)
+				ext_cache_fini(c);
+			return -EINVAL;
+		}
+
+		extent = (struct ext4_extent *)(ext_block + 1);
+
+		for (i = 0; i < le16_to_cpu(ext_block->eh_entries); i++) {
+			startblock = le32_to_cpu(extent[i].ee_block);
+			endblock = startblock + le16_to_cpu(extent[i].ee_len);
+
+			if (startblock > fileblock) {
+				/* Sparse file */
+				if (!cache)
+					ext_cache_fini(c);
+				return 0;
+
+			} else if (fileblock < endblock) {
+				start = le16_to_cpu(extent[i].ee_start_hi);
+				start = (start << 32) +
+					le32_to_cpu(extent[i].ee_start_lo);
+				if (!cache)
+					ext_cache_fini(c);
+				return (fileblock - startblock) + start;
+			}
+		}
+
+		if (!cache)
+			ext_cache_fini(c);
+		return 0;
+	}
+
+	/* Direct blocks. */
+	if (fileblock < INDIRECT_BLOCKS)
+		blknr = le32_to_cpu(inode->b.blocks.dir_blocks[fileblock]);
+
+	/* Indirect. */
+	else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4))) {
+		if (ext4fs_indir1_block == NULL) {
+			ext4fs_indir1_block = zalloc(blksz);
+			if (ext4fs_indir1_block == NULL) {
+				printf("** SI ext2fs read block (indir 1)"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir1_size = blksz;
+			ext4fs_indir1_blkno = -1;
+		}
+		if (blksz != ext4fs_indir1_size) {
+			free(ext4fs_indir1_block);
+			ext4fs_indir1_block = NULL;
+			ext4fs_indir1_size = 0;
+			ext4fs_indir1_blkno = -1;
+			ext4fs_indir1_block = zalloc(blksz);
+			if (ext4fs_indir1_block == NULL) {
+				printf("** SI ext2fs read block (indir 1):"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir1_size = blksz;
+		}
+		if ((le32_to_cpu(inode->b.blocks.indir_block) <<
+		     log2_blksz) != ext4fs_indir1_blkno) {
+			status =
+			    ext4fs_devread((lbaint_t)le32_to_cpu
+					   (inode->b.blocks.
+					    indir_block) << log2_blksz, 0,
+					   blksz, (char *)ext4fs_indir1_block);
+			if (status == 0) {
+				printf("** SI ext2fs read block (indir 1)"
+					"failed. **\n");
+				return -1;
+			}
+			ext4fs_indir1_blkno =
+				le32_to_cpu(inode->b.blocks.
+					       indir_block) << log2_blksz;
+		}
+		blknr = le32_to_cpu(ext4fs_indir1_block
+				      [fileblock - INDIRECT_BLOCKS]);
+	}
+	/* Double indirect. */
+	else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4 *
+					(blksz / 4 + 1)))) {
+
+		long int perblock = blksz / 4;
+		long int rblock = fileblock - (INDIRECT_BLOCKS + blksz / 4);
+
+		if (ext4fs_indir1_block == NULL) {
+			ext4fs_indir1_block = zalloc(blksz);
+			if (ext4fs_indir1_block == NULL) {
+				printf("** DI ext2fs read block (indir 2 1)"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir1_size = blksz;
+			ext4fs_indir1_blkno = -1;
+		}
+		if (blksz != ext4fs_indir1_size) {
+			free(ext4fs_indir1_block);
+			ext4fs_indir1_block = NULL;
+			ext4fs_indir1_size = 0;
+			ext4fs_indir1_blkno = -1;
+			ext4fs_indir1_block = zalloc(blksz);
+			if (ext4fs_indir1_block == NULL) {
+				printf("** DI ext2fs read block (indir 2 1)"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir1_size = blksz;
+		}
+		if ((le32_to_cpu(inode->b.blocks.double_indir_block) <<
+		     log2_blksz) != ext4fs_indir1_blkno) {
+			status =
+			    ext4fs_devread((lbaint_t)le32_to_cpu
+					   (inode->b.blocks.
+					    double_indir_block) << log2_blksz,
+					   0, blksz,
+					   (char *)ext4fs_indir1_block);
+			if (status == 0) {
+				printf("** DI ext2fs read block (indir 2 1)"
+					"failed. **\n");
+				return -1;
+			}
+			ext4fs_indir1_blkno =
+			    le32_to_cpu(inode->b.blocks.double_indir_block) <<
+			    log2_blksz;
+		}
+
+		if (ext4fs_indir2_block == NULL) {
+			ext4fs_indir2_block = zalloc(blksz);
+			if (ext4fs_indir2_block == NULL) {
+				printf("** DI ext2fs read block (indir 2 2)"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir2_size = blksz;
+			ext4fs_indir2_blkno = -1;
+		}
+		if (blksz != ext4fs_indir2_size) {
+			free(ext4fs_indir2_block);
+			ext4fs_indir2_block = NULL;
+			ext4fs_indir2_size = 0;
+			ext4fs_indir2_blkno = -1;
+			ext4fs_indir2_block = zalloc(blksz);
+			if (ext4fs_indir2_block == NULL) {
+				printf("** DI ext2fs read block (indir 2 2)"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir2_size = blksz;
+		}
+		if ((le32_to_cpu(ext4fs_indir1_block[rblock / perblock]) <<
+		     log2_blksz) != ext4fs_indir2_blkno) {
+			status = ext4fs_devread((lbaint_t)le32_to_cpu
+						(ext4fs_indir1_block
+						 [rblock /
+						  perblock]) << log2_blksz, 0,
+						blksz,
+						(char *)ext4fs_indir2_block);
+			if (status == 0) {
+				printf("** DI ext2fs read block (indir 2 2)"
+					"failed. **\n");
+				return -1;
+			}
+			ext4fs_indir2_blkno =
+			    le32_to_cpu(ext4fs_indir1_block[rblock
+							      /
+							      perblock]) <<
+			    log2_blksz;
+		}
+		blknr = le32_to_cpu(ext4fs_indir2_block[rblock % perblock]);
+	}
+	/* Tripple indirect. */
+	else {
+		rblock = fileblock - (INDIRECT_BLOCKS + blksz / 4 +
+				      (blksz / 4 * blksz / 4));
+		perblock_child = blksz / 4;
+		perblock_parent = ((blksz / 4) * (blksz / 4));
+
+		if (ext4fs_indir1_block == NULL) {
+			ext4fs_indir1_block = zalloc(blksz);
+			if (ext4fs_indir1_block == NULL) {
+				printf("** TI ext2fs read block (indir 2 1)"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir1_size = blksz;
+			ext4fs_indir1_blkno = -1;
+		}
+		if (blksz != ext4fs_indir1_size) {
+			free(ext4fs_indir1_block);
+			ext4fs_indir1_block = NULL;
+			ext4fs_indir1_size = 0;
+			ext4fs_indir1_blkno = -1;
+			ext4fs_indir1_block = zalloc(blksz);
+			if (ext4fs_indir1_block == NULL) {
+				printf("** TI ext2fs read block (indir 2 1)"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir1_size = blksz;
+		}
+		if ((le32_to_cpu(inode->b.blocks.triple_indir_block) <<
+		     log2_blksz) != ext4fs_indir1_blkno) {
+			status = ext4fs_devread
+			    ((lbaint_t)
+			     le32_to_cpu(inode->b.blocks.triple_indir_block)
+			     << log2_blksz, 0, blksz,
+			     (char *)ext4fs_indir1_block);
+			if (status == 0) {
+				printf("** TI ext2fs read block (indir 2 1)"
+					"failed. **\n");
+				return -1;
+			}
+			ext4fs_indir1_blkno =
+			    le32_to_cpu(inode->b.blocks.triple_indir_block) <<
+			    log2_blksz;
+		}
+
+		if (ext4fs_indir2_block == NULL) {
+			ext4fs_indir2_block = zalloc(blksz);
+			if (ext4fs_indir2_block == NULL) {
+				printf("** TI ext2fs read block (indir 2 2)"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir2_size = blksz;
+			ext4fs_indir2_blkno = -1;
+		}
+		if (blksz != ext4fs_indir2_size) {
+			free(ext4fs_indir2_block);
+			ext4fs_indir2_block = NULL;
+			ext4fs_indir2_size = 0;
+			ext4fs_indir2_blkno = -1;
+			ext4fs_indir2_block = zalloc(blksz);
+			if (ext4fs_indir2_block == NULL) {
+				printf("** TI ext2fs read block (indir 2 2)"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir2_size = blksz;
+		}
+		if ((le32_to_cpu(ext4fs_indir1_block[rblock /
+						       perblock_parent]) <<
+		     log2_blksz)
+		    != ext4fs_indir2_blkno) {
+			status = ext4fs_devread((lbaint_t)le32_to_cpu
+						(ext4fs_indir1_block
+						 [rblock /
+						  perblock_parent]) <<
+						log2_blksz, 0, blksz,
+						(char *)ext4fs_indir2_block);
+			if (status == 0) {
+				printf("** TI ext2fs read block (indir 2 2)"
+					"failed. **\n");
+				return -1;
+			}
+			ext4fs_indir2_blkno =
+			    le32_to_cpu(ext4fs_indir1_block[rblock /
+							      perblock_parent])
+			    << log2_blksz;
+		}
+
+		if (ext4fs_indir3_block == NULL) {
+			ext4fs_indir3_block = zalloc(blksz);
+			if (ext4fs_indir3_block == NULL) {
+				printf("** TI ext2fs read block (indir 2 2)"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir3_size = blksz;
+			ext4fs_indir3_blkno = -1;
+		}
+		if (blksz != ext4fs_indir3_size) {
+			free(ext4fs_indir3_block);
+			ext4fs_indir3_block = NULL;
+			ext4fs_indir3_size = 0;
+			ext4fs_indir3_blkno = -1;
+			ext4fs_indir3_block = zalloc(blksz);
+			if (ext4fs_indir3_block == NULL) {
+				printf("** TI ext2fs read block (indir 2 2)"
+					"malloc failed. **\n");
+				return -1;
+			}
+			ext4fs_indir3_size = blksz;
+		}
+		if ((le32_to_cpu(ext4fs_indir2_block[rblock
+						       /
+						       perblock_child]) <<
+		     log2_blksz) != ext4fs_indir3_blkno) {
+			status =
+			    ext4fs_devread((lbaint_t)le32_to_cpu
+					   (ext4fs_indir2_block
+					    [(rblock / perblock_child)
+					     % (blksz / 4)]) << log2_blksz, 0,
+					   blksz, (char *)ext4fs_indir3_block);
+			if (status == 0) {
+				printf("** TI ext2fs read block (indir 2 2)"
+				       "failed. **\n");
+				return -1;
+			}
+			ext4fs_indir3_blkno =
+			    le32_to_cpu(ext4fs_indir2_block[(rblock /
+							       perblock_child) %
+							      (blksz /
+							       4)]) <<
+			    log2_blksz;
+		}
+
+		blknr = le32_to_cpu(ext4fs_indir3_block
+				      [rblock % perblock_child]);
+	}
+	debug("read_allocated_block %ld\n", blknr);
+
+	return blknr;
+}
+
+/**
+ * ext4fs_reinit_global() - Reinitialize values of ext4 write implementation's
+ *			    global pointers
+ *
+ * This function assures that for a file with the same name but different size
+ * the sequential store on the ext4 filesystem will be correct.
+ *
+ * In this function the global data, responsible for internal representation
+ * of the ext4 data are initialized to the reset state. Without this, during
+ * replacement of the smaller file with the bigger truncation of new file was
+ * performed.
+ */
+void ext4fs_reinit_global(void)
+{
+	if (ext4fs_indir1_block != NULL) {
+		free(ext4fs_indir1_block);
+		ext4fs_indir1_block = NULL;
+		ext4fs_indir1_size = 0;
+		ext4fs_indir1_blkno = -1;
+	}
+	if (ext4fs_indir2_block != NULL) {
+		free(ext4fs_indir2_block);
+		ext4fs_indir2_block = NULL;
+		ext4fs_indir2_size = 0;
+		ext4fs_indir2_blkno = -1;
+	}
+	if (ext4fs_indir3_block != NULL) {
+		free(ext4fs_indir3_block);
+		ext4fs_indir3_block = NULL;
+		ext4fs_indir3_size = 0;
+		ext4fs_indir3_blkno = -1;
+	}
+}
+void ext4fs_close(void)
+{
+	if ((ext4fs_file != NULL) && (ext4fs_root != NULL)) {
+		ext4fs_free_node(ext4fs_file, &ext4fs_root->diropen);
+		ext4fs_file = NULL;
+	}
+	if (ext4fs_root != NULL) {
+		free(ext4fs_root);
+		ext4fs_root = NULL;
+	}
+
+	ext4fs_reinit_global();
+}
+
+int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name,
+				struct ext2fs_node **fnode, int *ftype)
+{
+	unsigned int fpos = 0;
+	int status;
+	loff_t actread;
+	struct ext2fs_node *diro = (struct ext2fs_node *) dir;
+
+#ifdef DEBUG
+	if (name != NULL)
+		printf("Iterate dir %s\n", name);
+#endif /* of DEBUG */
+	if (!diro->inode_read) {
+		status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode);
+		if (status == 0)
+			return 0;
+	}
+	/* Search the file.  */
+	while (fpos < le32_to_cpu(diro->inode.size)) {
+		struct ext2_dirent dirent;
+
+		status = ext4fs_read_file(diro, fpos,
+					   sizeof(struct ext2_dirent),
+					   (char *)&dirent, &actread);
+		if (status < 0)
+			return 0;
+
+		if (dirent.direntlen == 0) {
+			printf("Failed to iterate over directory %s\n", name);
+			return 0;
+		}
+
+		if (dirent.namelen != 0) {
+			char filename[dirent.namelen + 1];
+			struct ext2fs_node *fdiro;
+			int type = FILETYPE_UNKNOWN;
+
+			status = ext4fs_read_file(diro,
+						  fpos +
+						  sizeof(struct ext2_dirent),
+						  dirent.namelen, filename,
+						  &actread);
+			if (status < 0)
+				return 0;
+
+			fdiro = zalloc(sizeof(struct ext2fs_node));
+			if (!fdiro)
+				return 0;
+
+			fdiro->data = diro->data;
+			fdiro->ino = le32_to_cpu(dirent.inode);
+
+			filename[dirent.namelen] = '\0';
+
+			if (dirent.filetype != FILETYPE_UNKNOWN) {
+				fdiro->inode_read = 0;
+
+				if (dirent.filetype == FILETYPE_DIRECTORY)
+					type = FILETYPE_DIRECTORY;
+				else if (dirent.filetype == FILETYPE_SYMLINK)
+					type = FILETYPE_SYMLINK;
+				else if (dirent.filetype == FILETYPE_REG)
+					type = FILETYPE_REG;
+			} else {
+				status = ext4fs_read_inode(diro->data,
+							   le32_to_cpu
+							   (dirent.inode),
+							   &fdiro->inode);
+				if (status == 0) {
+					free(fdiro);
+					return 0;
+				}
+				fdiro->inode_read = 1;
+
+				if ((le16_to_cpu(fdiro->inode.mode) &
+				     FILETYPE_INO_MASK) ==
+				    FILETYPE_INO_DIRECTORY) {
+					type = FILETYPE_DIRECTORY;
+				} else if ((le16_to_cpu(fdiro->inode.mode)
+					    & FILETYPE_INO_MASK) ==
+					   FILETYPE_INO_SYMLINK) {
+					type = FILETYPE_SYMLINK;
+				} else if ((le16_to_cpu(fdiro->inode.mode)
+					    & FILETYPE_INO_MASK) ==
+					   FILETYPE_INO_REG) {
+					type = FILETYPE_REG;
+				}
+			}
+#ifdef DEBUG
+			printf("iterate >%s<\n", filename);
+#endif /* of DEBUG */
+			if ((name != NULL) && (fnode != NULL)
+			    && (ftype != NULL)) {
+				if (strcmp(filename, name) == 0) {
+					*ftype = type;
+					*fnode = fdiro;
+					return 1;
+				}
+			} else {
+				if (fdiro->inode_read == 0) {
+					status = ext4fs_read_inode(diro->data,
+								 le32_to_cpu(
+								 dirent.inode),
+								 &fdiro->inode);
+					if (status == 0) {
+						free(fdiro);
+						return 0;
+					}
+					fdiro->inode_read = 1;
+				}
+				switch (type) {
+				case FILETYPE_DIRECTORY:
+					printf("<DIR> ");
+					break;
+				case FILETYPE_SYMLINK:
+					printf("<SYM> ");
+					break;
+				case FILETYPE_REG:
+					printf("      ");
+					break;
+				default:
+					printf("< ? > ");
+					break;
+				}
+				printf("%10u %s\n",
+				       le32_to_cpu(fdiro->inode.size),
+					filename);
+			}
+			free(fdiro);
+		}
+		fpos += le16_to_cpu(dirent.direntlen);
+	}
+	return 0;
+}
+
+static char *ext4fs_read_symlink(struct ext2fs_node *node)
+{
+	char *symlink;
+	struct ext2fs_node *diro = node;
+	int status;
+	loff_t actread;
+
+	if (!diro->inode_read) {
+		status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode);
+		if (status == 0)
+			return NULL;
+	}
+	symlink = zalloc(le32_to_cpu(diro->inode.size) + 1);
+	if (!symlink)
+		return NULL;
+
+	if (le32_to_cpu(diro->inode.size) < sizeof(diro->inode.b.symlink)) {
+		strncpy(symlink, diro->inode.b.symlink,
+			 le32_to_cpu(diro->inode.size));
+	} else {
+		status = ext4fs_read_file(diro, 0,
+					   le32_to_cpu(diro->inode.size),
+					   symlink, &actread);
+		if ((status < 0) || (actread == 0)) {
+			free(symlink);
+			return NULL;
+		}
+	}
+	symlink[le32_to_cpu(diro->inode.size)] = '\0';
+	return symlink;
+}
+
+static int ext4fs_find_file1(const char *currpath,
+			     struct ext2fs_node *currroot,
+			     struct ext2fs_node **currfound, int *foundtype)
+{
+	char fpath[strlen(currpath) + 1];
+	char *name = fpath;
+	char *next;
+	int status;
+	int type = FILETYPE_DIRECTORY;
+	struct ext2fs_node *currnode = currroot;
+	struct ext2fs_node *oldnode = currroot;
+
+	strncpy(fpath, currpath, strlen(currpath) + 1);
+
+	/* Remove all leading slashes. */
+	while (*name == '/')
+		name++;
+
+	if (!*name) {
+		*currfound = currnode;
+		return 1;
+	}
+
+	for (;;) {
+		int found;
+
+		/* Extract the actual part from the pathname. */
+		next = strchr(name, '/');
+		if (next) {
+			/* Remove all leading slashes. */
+			while (*next == '/')
+				*(next++) = '\0';
+		}
+
+		if (type != FILETYPE_DIRECTORY) {
+			ext4fs_free_node(currnode, currroot);
+			return 0;
+		}
+
+		oldnode = currnode;
+
+		/* Iterate over the directory. */
+		found = ext4fs_iterate_dir(currnode, name, &currnode, &type);
+		if (found == 0)
+			return 0;
+
+		if (found == -1)
+			break;
+
+		/* Read in the symlink and follow it. */
+		if (type == FILETYPE_SYMLINK) {
+			char *symlink;
+
+			/* Test if the symlink does not loop. */
+			if (++symlinknest == 8) {
+				ext4fs_free_node(currnode, currroot);
+				ext4fs_free_node(oldnode, currroot);
+				return 0;
+			}
+
+			symlink = ext4fs_read_symlink(currnode);
+			ext4fs_free_node(currnode, currroot);
+
+			if (!symlink) {
+				ext4fs_free_node(oldnode, currroot);
+				return 0;
+			}
+
+			debug("Got symlink >%s<\n", symlink);
+
+			if (symlink[0] == '/') {
+				ext4fs_free_node(oldnode, currroot);
+				oldnode = &ext4fs_root->diropen;
+			}
+
+			/* Lookup the node the symlink points to. */
+			status = ext4fs_find_file1(symlink, oldnode,
+						    &currnode, &type);
+
+			free(symlink);
+
+			if (status == 0) {
+				ext4fs_free_node(oldnode, currroot);
+				return 0;
+			}
+		}
+
+		ext4fs_free_node(oldnode, currroot);
+
+		/* Found the node! */
+		if (!next || *next == '\0') {
+			*currfound = currnode;
+			*foundtype = type;
+			return 1;
+		}
+		name = next;
+	}
+	return -1;
+}
+
+int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode,
+	struct ext2fs_node **foundnode, int expecttype)
+{
+	int status;
+	int foundtype = FILETYPE_DIRECTORY;
+
+	symlinknest = 0;
+	if (!path)
+		return 0;
+
+	status = ext4fs_find_file1(path, rootnode, foundnode, &foundtype);
+	if (status == 0)
+		return 0;
+
+	/* Check if the node that was found was of the expected type. */
+	if ((expecttype == FILETYPE_REG) && (foundtype != expecttype))
+		return 0;
+	else if ((expecttype == FILETYPE_DIRECTORY)
+		   && (foundtype != expecttype))
+		return 0;
+
+	return 1;
+}
+
+int ext4fs_open(const char *filename, loff_t *len)
+{
+	struct ext2fs_node *fdiro = NULL;
+	int status;
+
+	if (ext4fs_root == NULL)
+		return -1;
+
+	ext4fs_file = NULL;
+	status = ext4fs_find_file(filename, &ext4fs_root->diropen, &fdiro,
+				  FILETYPE_REG);
+	if (status == 0)
+		goto fail;
+
+	if (!fdiro->inode_read) {
+		status = ext4fs_read_inode(fdiro->data, fdiro->ino,
+				&fdiro->inode);
+		if (status == 0)
+			goto fail;
+	}
+	*len = le32_to_cpu(fdiro->inode.size);
+	ext4fs_file = fdiro;
+
+	return 0;
+fail:
+	ext4fs_free_node(fdiro, &ext4fs_root->diropen);
+
+	return -1;
+}
+
+int ext4fs_mount(unsigned part_length)
+{
+	struct ext2_data *data;
+	int status;
+	struct ext_filesystem *fs = get_fs();
+	data = zalloc(SUPERBLOCK_SIZE);
+	if (!data)
+		return 0;
+
+	/* Read the superblock. */
+	status = ext4_read_superblock((char *)&data->sblock);
+
+	if (status == 0)
+		goto fail;
+
+	/* Make sure this is an ext2 filesystem. */
+	if (le16_to_cpu(data->sblock.magic) != EXT2_MAGIC)
+		goto fail_noerr;
+
+
+	if (le32_to_cpu(data->sblock.revision_level) == 0) {
+		fs->inodesz = 128;
+		fs->gdsize = 32;
+	} else {
+		debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: %08x\n",
+		      __le32_to_cpu(data->sblock.feature_compatibility),
+		      __le32_to_cpu(data->sblock.feature_incompat),
+		      __le32_to_cpu(data->sblock.feature_ro_compat));
+
+		fs->inodesz = le16_to_cpu(data->sblock.inode_size);
+		fs->gdsize = le32_to_cpu(data->sblock.feature_incompat) &
+			EXT4_FEATURE_INCOMPAT_64BIT ?
+			le16_to_cpu(data->sblock.descriptor_size) : 32;
+	}
+
+	debug("EXT2 rev %d, inode_size %d, descriptor size %d\n",
+	      le32_to_cpu(data->sblock.revision_level),
+	      fs->inodesz, fs->gdsize);
+
+	data->diropen.data = data;
+	data->diropen.ino = 2;
+	data->diropen.inode_read = 1;
+	data->inode = &data->diropen.inode;
+
+	status = ext4fs_read_inode(data, 2, data->inode);
+	if (status == 0)
+		goto fail;
+
+	ext4fs_root = data;
+
+	return 1;
+fail:
+	printf("Failed to mount ext2 filesystem...\n");
+fail_noerr:
+	free(data);
+	ext4fs_root = NULL;
+
+	return 0;
+}
diff --git a/ext4_common.h b/ext4_common.h
new file mode 100644
index 0000000..145b0da
--- /dev/null
+++ b/ext4_common.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * ext4ls and ext4load :  based on ext2 ls load support in Uboot.
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB  --  GRand Unified Bootloader
+ * Copyright (C) 2003, 2004  Free Software Foundation, Inc.
+ *
+ * ext4write : Based on generic ext4 protocol.
+ */
+
+#ifndef __EXT4_COMMON__
+#define __EXT4_COMMON__
+#include <ext_common.h>
+#include <ext4fs.h>
+#include <malloc.h>
+#include <linux/errno.h>
+#if defined(CONFIG_EXT4_WRITE)
+#include "ext4_journal.h"
+#include "crc16.h"
+#endif
+
+#define YES		1
+#define NO		0
+#define RECOVER	1
+#define SCAN		0
+
+#define S_IFLNK		0120000		/* symbolic link */
+#define BLOCK_NO_ONE		1
+#define SUPERBLOCK_START	(2 * 512)
+#define SUPERBLOCK_SIZE	1024
+#define F_FILE			1
+
+#define ARCH_DMA_MINALIGN 64 /* should be ok for all architectures */
+
+static inline void *zalloc(size_t size)
+{
+	void *p = memalign(ARCH_DMA_MINALIGN, size);
+	memset(p, 0, size);
+	return p;
+}
+
+int ext4fs_read_inode(struct ext2_data *data, int ino,
+		      struct ext2_inode *inode);
+int ext4fs_read_file(struct ext2fs_node *node, loff_t pos, loff_t len,
+		     char *buf, loff_t *actread);
+int ext4fs_find_file(const char *path, struct ext2fs_node *rootnode,
+			struct ext2fs_node **foundnode, int expecttype);
+int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name,
+			struct ext2fs_node **fnode, int *ftype);
+
+#if defined(CONFIG_EXT4_WRITE)
+uint32_t ext4fs_div_roundup(uint32_t size, uint32_t n);
+uint16_t ext4fs_checksum_update(unsigned int i);
+int ext4fs_get_parent_inode_num(const char *dirname, char *dname, int flags);
+int ext4fs_update_parent_dentry(char *filename, int file_type);
+uint32_t ext4fs_get_new_blk_no(void);
+int ext4fs_get_new_inode_no(void);
+void ext4fs_reset_block_bmap(long int blockno, unsigned char *buffer,
+					int index);
+int ext4fs_set_block_bmap(long int blockno, unsigned char *buffer, int index);
+int ext4fs_set_inode_bmap(int inode_no, unsigned char *buffer, int index);
+void ext4fs_reset_inode_bmap(int inode_no, unsigned char *buffer, int index);
+int ext4fs_iget(int inode_no, struct ext2_inode *inode);
+void ext4fs_allocate_blocks(struct ext2_inode *file_inode,
+				unsigned int total_remaining_blocks,
+				unsigned int *total_no_of_block);
+void put_ext4(uint64_t off, const void *buf, uint32_t size);
+struct ext2_block_group *ext4fs_get_group_descriptor
+	(const struct ext_filesystem *fs, uint32_t bg_idx);
+uint64_t ext4fs_bg_get_block_id(const struct ext2_block_group *bg,
+	const struct ext_filesystem *fs);
+uint64_t ext4fs_bg_get_inode_id(const struct ext2_block_group *bg,
+	const struct ext_filesystem *fs);
+uint64_t ext4fs_bg_get_inode_table_id(const struct ext2_block_group *bg,
+	const struct ext_filesystem *fs);
+uint64_t ext4fs_sb_get_free_blocks(const struct ext2_sblock *sb);
+void ext4fs_sb_set_free_blocks(struct ext2_sblock *sb, uint64_t free_blocks);
+uint32_t ext4fs_bg_get_free_blocks(const struct ext2_block_group *bg,
+	const struct ext_filesystem *fs);
+#endif
+#endif
diff --git a/ext4_journal.c b/ext4_journal.c
new file mode 100644
index 0000000..3559daf
--- /dev/null
+++ b/ext4_journal.c
@@ -0,0 +1,666 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Journal data structures and headers for Journaling feature of ext4
+ * have been referred from JBD2 (Journaling Block device 2)
+ * implementation in Linux Kernel.
+ * Written by Stephen C. Tweedie <sct@redhat.com>
+ *
+ * Copyright 1998-2000 Red Hat, Inc --- All Rights Reserved
+ */
+
+#include <common.h>
+#include <ext4fs.h>
+#include <malloc.h>
+#include <ext_common.h>
+#include "ext4_common.h"
+
+static struct revoke_blk_list *revk_blk_list;
+static struct revoke_blk_list *prev_node;
+static int first_node = true;
+
+int gindex;
+int gd_index;
+int jrnl_blk_idx;
+struct journal_log *journal_ptr[MAX_JOURNAL_ENTRIES];
+struct dirty_blocks *dirty_block_ptr[MAX_JOURNAL_ENTRIES];
+
+int ext4fs_init_journal(void)
+{
+	int i;
+	char *temp = NULL;
+	struct ext_filesystem *fs = get_fs();
+
+	/* init globals */
+	revk_blk_list = NULL;
+	prev_node = NULL;
+	gindex = 0;
+	gd_index = 0;
+	jrnl_blk_idx = 1;
+
+	for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+		journal_ptr[i] = zalloc(sizeof(struct journal_log));
+		if (!journal_ptr[i])
+			goto fail;
+		dirty_block_ptr[i] = zalloc(sizeof(struct dirty_blocks));
+		if (!dirty_block_ptr[i])
+			goto fail;
+		journal_ptr[i]->buf = NULL;
+		journal_ptr[i]->blknr = -1;
+
+		dirty_block_ptr[i]->buf = NULL;
+		dirty_block_ptr[i]->blknr = -1;
+	}
+
+	if (fs->blksz == 4096) {
+		temp = zalloc(fs->blksz);
+		if (!temp)
+			goto fail;
+		journal_ptr[gindex]->buf = zalloc(fs->blksz);
+		if (!journal_ptr[gindex]->buf)
+			goto fail;
+		ext4fs_devread(0, 0, fs->blksz, temp);
+		memcpy(temp + SUPERBLOCK_SIZE, fs->sb, SUPERBLOCK_SIZE);
+		memcpy(journal_ptr[gindex]->buf, temp, fs->blksz);
+		journal_ptr[gindex++]->blknr = 0;
+		free(temp);
+	} else {
+		journal_ptr[gindex]->buf = zalloc(fs->blksz);
+		if (!journal_ptr[gindex]->buf)
+			goto fail;
+		memcpy(journal_ptr[gindex]->buf, fs->sb, SUPERBLOCK_SIZE);
+		journal_ptr[gindex++]->blknr = 1;
+	}
+
+	/* Check the file system state using journal super block */
+	if (ext4fs_check_journal_state(SCAN))
+		goto fail;
+	/* Check the file system state using journal super block */
+	if (ext4fs_check_journal_state(RECOVER))
+		goto fail;
+
+	return 0;
+fail:
+	return -1;
+}
+
+void ext4fs_dump_metadata(void)
+{
+	struct ext_filesystem *fs = get_fs();
+	int i;
+	for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+		if (dirty_block_ptr[i]->blknr == -1)
+			break;
+		put_ext4((uint64_t) ((uint64_t)dirty_block_ptr[i]->blknr *
+				(uint64_t)fs->blksz), dirty_block_ptr[i]->buf,
+								fs->blksz);
+	}
+}
+
+void ext4fs_free_journal(void)
+{
+	int i;
+	for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+		if (dirty_block_ptr[i]->blknr == -1)
+			break;
+		if (dirty_block_ptr[i]->buf)
+			free(dirty_block_ptr[i]->buf);
+	}
+
+	for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+		if (journal_ptr[i]->blknr == -1)
+			break;
+		if (journal_ptr[i]->buf)
+			free(journal_ptr[i]->buf);
+	}
+
+	for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+		if (journal_ptr[i])
+			free(journal_ptr[i]);
+		if (dirty_block_ptr[i])
+			free(dirty_block_ptr[i]);
+	}
+	gindex = 0;
+	gd_index = 0;
+	jrnl_blk_idx = 1;
+}
+
+int ext4fs_log_gdt(char *gd_table)
+{
+	struct ext_filesystem *fs = get_fs();
+	short i;
+	long int var = fs->gdtable_blkno;
+	for (i = 0; i < fs->no_blk_pergdt; i++) {
+		journal_ptr[gindex]->buf = zalloc(fs->blksz);
+		if (!journal_ptr[gindex]->buf)
+			return -ENOMEM;
+		memcpy(journal_ptr[gindex]->buf, gd_table, fs->blksz);
+		gd_table += fs->blksz;
+		journal_ptr[gindex++]->blknr = var++;
+	}
+
+	return 0;
+}
+
+/*
+ * This function stores the backup copy of meta data in RAM
+ * journal_buffer -- Buffer containing meta data
+ * blknr -- Block number on disk of the meta data buffer
+ */
+int ext4fs_log_journal(char *journal_buffer, uint32_t blknr)
+{
+	struct ext_filesystem *fs = get_fs();
+	short i;
+
+	if (!journal_buffer) {
+		printf("Invalid input arguments %s\n", __func__);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+		if (journal_ptr[i]->blknr == -1)
+			break;
+		if (journal_ptr[i]->blknr == blknr)
+			return 0;
+	}
+
+	journal_ptr[gindex]->buf = zalloc(fs->blksz);
+	if (!journal_ptr[gindex]->buf)
+		return -ENOMEM;
+
+	memcpy(journal_ptr[gindex]->buf, journal_buffer, fs->blksz);
+	journal_ptr[gindex++]->blknr = blknr;
+
+	return 0;
+}
+
+/*
+ * This function stores the modified meta data in RAM
+ * metadata_buffer -- Buffer containing meta data
+ * blknr -- Block number on disk of the meta data buffer
+ */
+int ext4fs_put_metadata(char *metadata_buffer, uint32_t blknr)
+{
+	struct ext_filesystem *fs = get_fs();
+	if (!metadata_buffer) {
+		printf("Invalid input arguments %s\n", __func__);
+		return -EINVAL;
+	}
+	if (dirty_block_ptr[gd_index]->buf)
+		assert(dirty_block_ptr[gd_index]->blknr == blknr);
+	else
+		dirty_block_ptr[gd_index]->buf = zalloc(fs->blksz);
+
+	if (!dirty_block_ptr[gd_index]->buf)
+		return -ENOMEM;
+	memcpy(dirty_block_ptr[gd_index]->buf, metadata_buffer, fs->blksz);
+	dirty_block_ptr[gd_index++]->blknr = blknr;
+
+	return 0;
+}
+
+void print_revoke_blks(char *revk_blk)
+{
+	int offset;
+	int max;
+	long int blocknr;
+	struct journal_revoke_header_t *header;
+
+	if (revk_blk == NULL)
+		return;
+
+	header = (struct journal_revoke_header_t *) revk_blk;
+	offset = sizeof(struct journal_revoke_header_t);
+	max = be32_to_cpu(header->r_count);
+	printf("total bytes %d\n", max);
+
+	while (offset < max) {
+		blocknr = be32_to_cpu(*((__be32 *)(revk_blk + offset)));
+		printf("revoke blknr is %ld\n", blocknr);
+		offset += 4;
+	}
+}
+
+static struct revoke_blk_list *_get_node(void)
+{
+	struct revoke_blk_list *tmp_node;
+	tmp_node = zalloc(sizeof(struct revoke_blk_list));
+	if (tmp_node == NULL)
+		return NULL;
+	tmp_node->content = NULL;
+	tmp_node->next = NULL;
+
+	return tmp_node;
+}
+
+void ext4fs_push_revoke_blk(char *buffer)
+{
+	struct revoke_blk_list *node = NULL;
+	struct ext_filesystem *fs = get_fs();
+	if (buffer == NULL) {
+		printf("buffer ptr is NULL\n");
+		return;
+	}
+	node = _get_node();
+	if (!node) {
+		printf("_get_node: malloc failed\n");
+		return;
+	}
+
+	node->content = zalloc(fs->blksz);
+	if (node->content == NULL)
+		return;
+	memcpy(node->content, buffer, fs->blksz);
+
+	if (first_node == true) {
+		revk_blk_list = node;
+		prev_node = node;
+		 first_node = false;
+	} else {
+		prev_node->next = node;
+		prev_node = node;
+	}
+}
+
+void ext4fs_free_revoke_blks(void)
+{
+	struct revoke_blk_list *tmp_node = revk_blk_list;
+	struct revoke_blk_list *next_node = NULL;
+
+	while (tmp_node != NULL) {
+		if (tmp_node->content)
+			free(tmp_node->content);
+		tmp_node = tmp_node->next;
+	}
+
+	tmp_node = revk_blk_list;
+	while (tmp_node != NULL) {
+		next_node = tmp_node->next;
+		free(tmp_node);
+		tmp_node = next_node;
+	}
+
+	revk_blk_list = NULL;
+	prev_node = NULL;
+	first_node = true;
+}
+
+int check_blknr_for_revoke(long int blknr, int sequence_no)
+{
+	struct journal_revoke_header_t *header;
+	int offset;
+	int max;
+	long int blocknr;
+	char *revk_blk;
+	struct revoke_blk_list *tmp_revk_node = revk_blk_list;
+	while (tmp_revk_node != NULL) {
+		revk_blk = tmp_revk_node->content;
+
+		header = (struct journal_revoke_header_t *) revk_blk;
+		if (sequence_no < be32_to_cpu(header->r_header.h_sequence)) {
+			offset = sizeof(struct journal_revoke_header_t);
+			max = be32_to_cpu(header->r_count);
+
+			while (offset < max) {
+				blocknr = be32_to_cpu(*((__be32 *)
+						  (revk_blk + offset)));
+				if (blocknr == blknr)
+					goto found;
+				offset += 4;
+			}
+		}
+		tmp_revk_node = tmp_revk_node->next;
+	}
+
+	return -1;
+
+found:
+	return 0;
+}
+
+/*
+ * This function parses the journal blocks and replays the
+ * suceessful transactions. A transaction is successfull
+ * if commit block is found for a descriptor block
+ * The tags in descriptor block contain the disk block
+ * numbers of the metadata  to be replayed
+ */
+void recover_transaction(int prev_desc_logical_no)
+{
+	struct ext2_inode inode_journal;
+	struct ext_filesystem *fs = get_fs();
+	struct journal_header_t *jdb;
+	long int blknr;
+	char *p_jdb;
+	int ofs, flags;
+	int i;
+	struct ext3_journal_block_tag *tag;
+	char *temp_buff = zalloc(fs->blksz);
+	char *metadata_buff = zalloc(fs->blksz);
+	if (!temp_buff || !metadata_buff)
+		goto fail;
+	i = prev_desc_logical_no;
+	ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO,
+			  (struct ext2_inode *)&inode_journal);
+	blknr = read_allocated_block((struct ext2_inode *)
+				     &inode_journal, i, NULL);
+	ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz,
+		       temp_buff);
+	p_jdb = (char *)temp_buff;
+	jdb = (struct journal_header_t *) temp_buff;
+	ofs = sizeof(struct journal_header_t);
+
+	do {
+		tag = (struct ext3_journal_block_tag *)(p_jdb + ofs);
+		ofs += sizeof(struct ext3_journal_block_tag);
+
+		if (ofs > fs->blksz)
+			break;
+
+		flags = be32_to_cpu(tag->flags);
+		if (!(flags & EXT3_JOURNAL_FLAG_SAME_UUID))
+			ofs += 16;
+
+		i++;
+		debug("\t\ttag %u\n", be32_to_cpu(tag->block));
+		if (revk_blk_list != NULL) {
+			if (check_blknr_for_revoke(be32_to_cpu(tag->block),
+				be32_to_cpu(jdb->h_sequence)) == 0)
+				continue;
+		}
+		blknr = read_allocated_block(&inode_journal, i, NULL);
+		ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0,
+			       fs->blksz, metadata_buff);
+		put_ext4((uint64_t)((uint64_t)be32_to_cpu(tag->block) * (uint64_t)fs->blksz),
+			 metadata_buff, (uint32_t) fs->blksz);
+	} while (!(flags & EXT3_JOURNAL_FLAG_LAST_TAG));
+fail:
+	free(temp_buff);
+	free(metadata_buff);
+}
+
+void print_jrnl_status(int recovery_flag)
+{
+	if (recovery_flag == RECOVER)
+		printf("Journal Recovery Completed\n");
+	else
+		printf("Journal Scan Completed\n");
+}
+
+int ext4fs_check_journal_state(int recovery_flag)
+{
+	int i;
+	int DB_FOUND = NO;
+	long int blknr;
+	int transaction_state = TRANSACTION_COMPLETE;
+	int prev_desc_logical_no = 0;
+	int curr_desc_logical_no = 0;
+	int ofs, flags;
+	struct ext2_inode inode_journal;
+	struct journal_superblock_t *jsb = NULL;
+	struct journal_header_t *jdb = NULL;
+	char *p_jdb = NULL;
+	struct ext3_journal_block_tag *tag = NULL;
+	char *temp_buff = NULL;
+	char *temp_buff1 = NULL;
+	struct ext_filesystem *fs = get_fs();
+
+	temp_buff = zalloc(fs->blksz);
+	if (!temp_buff)
+		return -ENOMEM;
+	temp_buff1 = zalloc(fs->blksz);
+	if (!temp_buff1) {
+		free(temp_buff);
+		return -ENOMEM;
+	}
+
+	ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
+	blknr = read_allocated_block(&inode_journal, EXT2_JOURNAL_SUPERBLOCK,
+				     NULL);
+	ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz,
+		       temp_buff);
+	jsb = (struct journal_superblock_t *) temp_buff;
+
+	if (le32_to_cpu(fs->sb->feature_incompat) & EXT3_FEATURE_INCOMPAT_RECOVER) {
+		if (recovery_flag == RECOVER)
+			printf("Recovery required\n");
+	} else {
+		if (recovery_flag == RECOVER)
+			printf("File System is consistent\n");
+		goto end;
+	}
+
+	if (be32_to_cpu(jsb->s_start) == 0)
+		goto end;
+
+	if (!(jsb->s_feature_compat &
+				cpu_to_be32(JBD2_FEATURE_COMPAT_CHECKSUM)))
+		jsb->s_feature_compat |=
+				cpu_to_be32(JBD2_FEATURE_COMPAT_CHECKSUM);
+
+	i = be32_to_cpu(jsb->s_first);
+	while (1) {
+		blknr = read_allocated_block(&inode_journal, i, NULL);
+		memset(temp_buff1, '\0', fs->blksz);
+		ext4fs_devread((lbaint_t)blknr * fs->sect_perblk,
+			       0, fs->blksz, temp_buff1);
+		jdb = (struct journal_header_t *) temp_buff1;
+
+		if (be32_to_cpu(jdb->h_blocktype) ==
+		    EXT3_JOURNAL_DESCRIPTOR_BLOCK) {
+			if (be32_to_cpu(jdb->h_sequence) !=
+			    be32_to_cpu(jsb->s_sequence)) {
+				print_jrnl_status(recovery_flag);
+				break;
+			}
+
+			curr_desc_logical_no = i;
+			if (transaction_state == TRANSACTION_COMPLETE)
+				transaction_state = TRANSACTION_RUNNING;
+			else
+				return -1;
+			p_jdb = (char *)temp_buff1;
+			ofs = sizeof(struct journal_header_t);
+			do {
+				tag = (struct ext3_journal_block_tag *)
+				    (p_jdb + ofs);
+				ofs += sizeof(struct ext3_journal_block_tag);
+				if (ofs > fs->blksz)
+					break;
+				flags = be32_to_cpu(tag->flags);
+				if (!(flags & EXT3_JOURNAL_FLAG_SAME_UUID))
+					ofs += 16;
+				i++;
+				debug("\t\ttag %u\n", be32_to_cpu(tag->block));
+			} while (!(flags & EXT3_JOURNAL_FLAG_LAST_TAG));
+			i++;
+			DB_FOUND = YES;
+		} else if (be32_to_cpu(jdb->h_blocktype) ==
+				EXT3_JOURNAL_COMMIT_BLOCK) {
+			if (be32_to_cpu(jdb->h_sequence) !=
+			     be32_to_cpu(jsb->s_sequence)) {
+				print_jrnl_status(recovery_flag);
+				break;
+			}
+
+			if (transaction_state == TRANSACTION_RUNNING ||
+					(DB_FOUND == NO)) {
+				transaction_state = TRANSACTION_COMPLETE;
+				i++;
+				jsb->s_sequence =
+					cpu_to_be32(be32_to_cpu(
+						jsb->s_sequence) + 1);
+			}
+			prev_desc_logical_no = curr_desc_logical_no;
+			if ((recovery_flag == RECOVER) && (DB_FOUND == YES))
+				recover_transaction(prev_desc_logical_no);
+
+			DB_FOUND = NO;
+		} else if (be32_to_cpu(jdb->h_blocktype) ==
+				EXT3_JOURNAL_REVOKE_BLOCK) {
+			if (be32_to_cpu(jdb->h_sequence) !=
+			    be32_to_cpu(jsb->s_sequence)) {
+				print_jrnl_status(recovery_flag);
+				break;
+			}
+			if (recovery_flag == SCAN)
+				ext4fs_push_revoke_blk((char *)jdb);
+			i++;
+		} else {
+			debug("Else Case\n");
+			if (be32_to_cpu(jdb->h_sequence) !=
+			    be32_to_cpu(jsb->s_sequence)) {
+				print_jrnl_status(recovery_flag);
+				break;
+			}
+		}
+	}
+
+end:
+	if (recovery_flag == RECOVER) {
+		uint32_t new_feature_incompat;
+		jsb->s_start = cpu_to_be32(1);
+		jsb->s_sequence = cpu_to_be32(be32_to_cpu(jsb->s_sequence) + 1);
+		/* get the superblock */
+		ext4_read_superblock((char *)fs->sb);
+		new_feature_incompat = le32_to_cpu(fs->sb->feature_incompat);
+		new_feature_incompat |= EXT3_FEATURE_INCOMPAT_RECOVER;
+		fs->sb->feature_incompat = cpu_to_le32(new_feature_incompat);
+
+		/* Update the super block */
+		put_ext4((uint64_t) (SUPERBLOCK_SIZE),
+			 (struct ext2_sblock *)fs->sb,
+			 (uint32_t) SUPERBLOCK_SIZE);
+		ext4_read_superblock((char *)fs->sb);
+
+		blknr = read_allocated_block(&inode_journal,
+					 EXT2_JOURNAL_SUPERBLOCK, NULL);
+		put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
+			 (struct journal_superblock_t *)temp_buff,
+			 (uint32_t) fs->blksz);
+		ext4fs_free_revoke_blks();
+	}
+	free(temp_buff);
+	free(temp_buff1);
+
+	return 0;
+}
+
+static void update_descriptor_block(long int blknr)
+{
+	int i;
+	long int jsb_blknr;
+	struct journal_header_t jdb;
+	struct ext3_journal_block_tag tag;
+	struct ext2_inode inode_journal;
+	struct journal_superblock_t *jsb = NULL;
+	char *buf = NULL;
+	char *temp = NULL;
+	struct ext_filesystem *fs = get_fs();
+	char *temp_buff = zalloc(fs->blksz);
+	if (!temp_buff)
+		return;
+
+	ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
+	jsb_blknr = read_allocated_block(&inode_journal,
+					 EXT2_JOURNAL_SUPERBLOCK, NULL);
+	ext4fs_devread((lbaint_t)jsb_blknr * fs->sect_perblk, 0, fs->blksz,
+		       temp_buff);
+	jsb = (struct journal_superblock_t *) temp_buff;
+
+	jdb.h_blocktype = cpu_to_be32(EXT3_JOURNAL_DESCRIPTOR_BLOCK);
+	jdb.h_magic = cpu_to_be32(EXT3_JOURNAL_MAGIC_NUMBER);
+	jdb.h_sequence = jsb->s_sequence;
+	buf = zalloc(fs->blksz);
+	if (!buf) {
+		free(temp_buff);
+		return;
+	}
+	temp = buf;
+	memcpy(buf, &jdb, sizeof(struct journal_header_t));
+	temp += sizeof(struct journal_header_t);
+
+	for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+		if (journal_ptr[i]->blknr == -1)
+			break;
+
+		tag.block = cpu_to_be32(journal_ptr[i]->blknr);
+		tag.flags = cpu_to_be32(EXT3_JOURNAL_FLAG_SAME_UUID);
+		memcpy(temp, &tag, sizeof(struct ext3_journal_block_tag));
+		temp = temp + sizeof(struct ext3_journal_block_tag);
+	}
+
+	tag.block = cpu_to_be32(journal_ptr[--i]->blknr);
+	tag.flags = cpu_to_be32(EXT3_JOURNAL_FLAG_LAST_TAG);
+	memcpy(temp - sizeof(struct ext3_journal_block_tag), &tag,
+	       sizeof(struct ext3_journal_block_tag));
+	put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), buf, (uint32_t) fs->blksz);
+
+	free(temp_buff);
+	free(buf);
+}
+
+static void update_commit_block(long int blknr)
+{
+	struct journal_header_t jdb;
+	struct ext_filesystem *fs = get_fs();
+	char *buf = NULL;
+	struct ext2_inode inode_journal;
+	struct journal_superblock_t *jsb;
+	long int jsb_blknr;
+	char *temp_buff = zalloc(fs->blksz);
+	if (!temp_buff)
+		return;
+
+	ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO,
+			  &inode_journal);
+	jsb_blknr = read_allocated_block(&inode_journal,
+					 EXT2_JOURNAL_SUPERBLOCK, NULL);
+	ext4fs_devread((lbaint_t)jsb_blknr * fs->sect_perblk, 0, fs->blksz,
+		       temp_buff);
+	jsb = (struct journal_superblock_t *) temp_buff;
+
+	jdb.h_blocktype = cpu_to_be32(EXT3_JOURNAL_COMMIT_BLOCK);
+	jdb.h_magic = cpu_to_be32(EXT3_JOURNAL_MAGIC_NUMBER);
+	jdb.h_sequence = jsb->s_sequence;
+	buf = zalloc(fs->blksz);
+	if (!buf) {
+		free(temp_buff);
+		return;
+	}
+	memcpy(buf, &jdb, sizeof(struct journal_header_t));
+	put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz), buf, (uint32_t) fs->blksz);
+
+	free(temp_buff);
+	free(buf);
+}
+
+void ext4fs_update_journal(void)
+{
+	struct ext2_inode inode_journal;
+	struct ext_filesystem *fs = get_fs();
+	long int blknr;
+	int i;
+
+	if (!(fs->sb->feature_compatibility & EXT4_FEATURE_COMPAT_HAS_JOURNAL))
+		return;
+
+	ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
+	blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++, NULL);
+	update_descriptor_block(blknr);
+	for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
+		if (journal_ptr[i]->blknr == -1)
+			break;
+		blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++,
+					     NULL);
+		put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
+			 journal_ptr[i]->buf, fs->blksz);
+	}
+	blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++, NULL);
+	update_commit_block(blknr);
+	printf("update journal finished\n");
+}
diff --git a/ext4_journal.h b/ext4_journal.h
new file mode 100644
index 0000000..43fb8e7
--- /dev/null
+++ b/ext4_journal.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Journal data structures and headers for Journaling feature of ext4
+ * have been referred from JBD2 (Journaling Block device 2)
+ * implementation in Linux Kernel.
+ *
+ * Written by Stephen C. Tweedie <sct@redhat.com>
+ *
+ * Copyright 1998-2000 Red Hat, Inc --- All Rights Reserved
+ */
+
+#ifndef __EXT4_JRNL__
+#define __EXT4_JRNL__
+
+#define EXT4_FEATURE_COMPAT_HAS_JOURNAL		0x0004
+
+#define EXT2_JOURNAL_INO		8	/* Journal inode */
+#define EXT2_JOURNAL_SUPERBLOCK	0	/* Journal  Superblock number */
+
+#define JBD2_FEATURE_COMPAT_CHECKSUM	0x00000001
+#define EXT3_JOURNAL_MAGIC_NUMBER	0xc03b3998U
+#define TRANSACTION_RUNNING		1
+#define TRANSACTION_COMPLETE		0
+#define EXT3_FEATURE_INCOMPAT_RECOVER	0x0004	/* Needs recovery */
+#define EXT3_JOURNAL_DESCRIPTOR_BLOCK	1
+#define EXT3_JOURNAL_COMMIT_BLOCK	2
+#define EXT3_JOURNAL_SUPERBLOCK_V1	3
+#define EXT3_JOURNAL_SUPERBLOCK_V2	4
+#define EXT3_JOURNAL_REVOKE_BLOCK	5
+#define EXT3_JOURNAL_FLAG_ESCAPE	1
+#define EXT3_JOURNAL_FLAG_SAME_UUID	2
+#define EXT3_JOURNAL_FLAG_DELETED	4
+#define EXT3_JOURNAL_FLAG_LAST_TAG	8
+
+/* Maximum entries in 1 journal transaction */
+#define MAX_JOURNAL_ENTRIES 100
+struct journal_log {
+	char *buf;
+	int blknr;
+};
+
+struct dirty_blocks {
+	char *buf;
+	int blknr;
+};
+
+/* Standard header for all descriptor blocks: */
+struct journal_header_t {
+	__be32 h_magic;
+	__be32 h_blocktype;
+	__be32 h_sequence;
+};
+
+/* The journal superblock.  All fields are in big-endian byte order. */
+struct journal_superblock_t {
+	/* 0x0000 */
+	struct journal_header_t s_header;
+
+	/* Static information describing the journal */
+	__be32 s_blocksize;	/* journal device blocksize */
+	__be32 s_maxlen;		/* total blocks in journal file */
+	__be32 s_first;		/* first block of log information */
+
+	/* Dynamic information describing the current state of the log */
+	__be32 s_sequence;	/* first commit ID expected in log */
+	__be32 s_start;		/* blocknr of start of log */
+
+	/* Error value, as set by journal_abort(). */
+	__be32 s_errno;
+
+	/* Remaining fields are only valid in a version-2 superblock */
+	__be32 s_feature_compat;	/* compatible feature set */
+	__be32 s_feature_incompat;	/* incompatible feature set */
+	__be32 s_feature_ro_compat;	/* readonly-compatible feature set */
+	/* 0x0030 */
+	__u8 s_uuid[16];	/* 128-bit uuid for journal */
+
+	/* 0x0040 */
+	__be32 s_nr_users;	/* Nr of filesystems sharing log */
+
+	__be32 s_dynsuper;	/* Blocknr of dynamic superblock copy */
+
+	/* 0x0048 */
+	__be32 s_max_transaction;	/* Limit of journal blocks per trans. */
+	__be32 s_max_trans_data;	/* Limit of data blocks per trans. */
+
+	/* 0x0050 */
+	__be32 s_padding[44];
+
+	/* 0x0100 */
+	__u8 s_users[16 * 48];	/* ids of all fs'es sharing the log */
+	/* 0x0400 */
+} ;
+
+struct ext3_journal_block_tag {
+	__be32 block;
+	__be32 flags;
+};
+
+struct journal_revoke_header_t {
+	struct journal_header_t r_header;
+	__be32 r_count;		/* Count of bytes used in the block */
+};
+
+struct revoke_blk_list {
+	char *content;		/* revoke block itself */
+	struct revoke_blk_list *next;
+};
+
+extern struct ext2_data *ext4fs_root;
+
+int ext4fs_init_journal(void);
+int ext4fs_log_gdt(char *gd_table);
+int ext4fs_check_journal_state(int recovery_flag);
+int ext4fs_log_journal(char *journal_buffer, uint32_t blknr);
+int ext4fs_put_metadata(char *metadata_buffer, uint32_t blknr);
+void ext4fs_update_journal(void);
+void ext4fs_dump_metadata(void);
+void ext4fs_push_revoke_blk(char *buffer);
+void ext4fs_free_journal(void);
+void ext4fs_free_revoke_blks(void);
+#endif
diff --git a/ext4_write.c b/ext4_write.c
new file mode 100644
index 0000000..3368bd8
--- /dev/null
+++ b/ext4_write.c
@@ -0,0 +1,1065 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * ext4ls and ext4load : Based on ext2 ls and load support in Uboot.
+ *		       Ext4 read optimization taken from Open-Moko
+ *		       Qi bootloader
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB  --  GRand Unified Bootloader
+ * Copyright (C) 2003, 2004  Free Software Foundation, Inc.
+ *
+ * ext4write : Based on generic ext4 protocol.
+ */
+
+
+#include <common.h>
+#include <memalign.h>
+#include <linux/stat.h>
+#include <div64.h>
+#include "ext4_common.h"
+
+static inline void ext4fs_sb_free_inodes_inc(struct ext2_sblock *sb)
+{
+	sb->free_inodes = cpu_to_le32(le32_to_cpu(sb->free_inodes) + 1);
+}
+
+static inline void ext4fs_sb_free_blocks_inc(struct ext2_sblock *sb)
+{
+	sb->free_blocks = cpu_to_le32(le32_to_cpu(sb->free_blocks) + 1);
+}
+
+static inline void ext4fs_bg_free_inodes_inc
+	(struct ext2_block_group *bg, const struct ext_filesystem *fs)
+{
+	uint32_t free_inodes = le16_to_cpu(bg->free_inodes);
+	if (fs->gdsize == 64)
+		free_inodes += le16_to_cpu(bg->free_inodes_high) << 16;
+	free_inodes++;
+
+	bg->free_inodes = cpu_to_le16(free_inodes & 0xffff);
+	if (fs->gdsize == 64)
+		bg->free_inodes_high = cpu_to_le16(free_inodes >> 16);
+}
+
+static inline void ext4fs_bg_free_blocks_inc
+	(struct ext2_block_group *bg, const struct ext_filesystem *fs)
+{
+	uint32_t free_blocks = le16_to_cpu(bg->free_blocks);
+	if (fs->gdsize == 64)
+		free_blocks += le16_to_cpu(bg->free_blocks_high) << 16;
+	free_blocks++;
+
+	bg->free_blocks = cpu_to_le16(free_blocks & 0xffff);
+	if (fs->gdsize == 64)
+		bg->free_blocks_high = cpu_to_le16(free_blocks >> 16);
+}
+
+static void ext4fs_update(void)
+{
+	short i;
+	ext4fs_update_journal();
+	struct ext_filesystem *fs = get_fs();
+	struct ext2_block_group *bgd = NULL;
+
+	/* update  super block */
+	put_ext4((uint64_t)(SUPERBLOCK_SIZE),
+		 (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE);
+
+	/* update block bitmaps */
+	for (i = 0; i < fs->no_blkgrp; i++) {
+		bgd = ext4fs_get_group_descriptor(fs, i);
+		bgd->bg_checksum = cpu_to_le16(ext4fs_checksum_update(i));
+		uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+		put_ext4(b_bitmap_blk * fs->blksz,
+			 fs->blk_bmaps[i], fs->blksz);
+	}
+
+	/* update inode bitmaps */
+	for (i = 0; i < fs->no_blkgrp; i++) {
+		bgd = ext4fs_get_group_descriptor(fs, i);
+		uint64_t i_bitmap_blk = ext4fs_bg_get_inode_id(bgd, fs);
+		put_ext4(i_bitmap_blk * fs->blksz,
+			 fs->inode_bmaps[i], fs->blksz);
+	}
+
+	/* update the block group descriptor table */
+	put_ext4((uint64_t)((uint64_t)fs->gdtable_blkno * (uint64_t)fs->blksz),
+		 (struct ext2_block_group *)fs->gdtable,
+		 (fs->blksz * fs->no_blk_pergdt));
+
+	ext4fs_dump_metadata();
+
+	gindex = 0;
+	gd_index = 0;
+}
+
+int ext4fs_get_bgdtable(void)
+{
+	int status;
+	struct ext_filesystem *fs = get_fs();
+	int gdsize_total = ROUND(fs->no_blkgrp * fs->gdsize, fs->blksz);
+	fs->no_blk_pergdt = gdsize_total / fs->blksz;
+
+	/* allocate memory for gdtable */
+	fs->gdtable = zalloc(gdsize_total);
+	if (!fs->gdtable)
+		return -ENOMEM;
+	/* read the group descriptor table */
+	status = ext4fs_devread((lbaint_t)fs->gdtable_blkno * fs->sect_perblk,
+				0, fs->blksz * fs->no_blk_pergdt, fs->gdtable);
+	if (status == 0)
+		goto fail;
+
+	if (ext4fs_log_gdt(fs->gdtable)) {
+		printf("Error in ext4fs_log_gdt\n");
+		return -1;
+	}
+
+	return 0;
+fail:
+	free(fs->gdtable);
+	fs->gdtable = NULL;
+
+	return -1;
+}
+
+static void delete_single_indirect_block(struct ext2_inode *inode)
+{
+	struct ext2_block_group *bgd = NULL;
+	static int prev_bg_bmap_idx = -1;
+	uint32_t blknr;
+	int remainder;
+	int bg_idx;
+	int status;
+	uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group);
+	struct ext_filesystem *fs = get_fs();
+	char *journal_buffer = zalloc(fs->blksz);
+	if (!journal_buffer) {
+		printf("No memory\n");
+		return;
+	}
+
+	/* deleting the single indirect block associated with inode */
+	if (inode->b.blocks.indir_block != 0) {
+		blknr = le32_to_cpu(inode->b.blocks.indir_block);
+		debug("SIPB releasing %u\n", blknr);
+		bg_idx = blknr / blk_per_grp;
+		if (fs->blksz == 1024) {
+			remainder = blknr % blk_per_grp;
+			if (!remainder)
+				bg_idx--;
+		}
+		ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+		/* get  block group descriptor table */
+		bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+		ext4fs_bg_free_blocks_inc(bgd, fs);
+		ext4fs_sb_free_blocks_inc(fs->sb);
+		/* journal backup */
+		if (prev_bg_bmap_idx != bg_idx) {
+			uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+			status = ext4fs_devread(
+					   b_bitmap_blk * fs->sect_perblk,
+					   0, fs->blksz, journal_buffer);
+			if (status == 0)
+				goto fail;
+			if (ext4fs_log_journal(journal_buffer, b_bitmap_blk))
+				goto fail;
+			prev_bg_bmap_idx = bg_idx;
+		}
+	}
+fail:
+	free(journal_buffer);
+}
+
+static void delete_double_indirect_block(struct ext2_inode *inode)
+{
+	int i;
+	short status;
+	static int prev_bg_bmap_idx = -1;
+	uint32_t blknr;
+	int remainder;
+	int bg_idx;
+	uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group);
+	__le32 *di_buffer = NULL;
+	void *dib_start_addr = NULL;
+	struct ext2_block_group *bgd = NULL;
+	struct ext_filesystem *fs = get_fs();
+	char *journal_buffer = zalloc(fs->blksz);
+	if (!journal_buffer) {
+		printf("No memory\n");
+		return;
+	}
+
+	if (inode->b.blocks.double_indir_block != 0) {
+		di_buffer = zalloc(fs->blksz);
+		if (!di_buffer) {
+			printf("No memory\n");
+			return;
+		}
+		dib_start_addr = di_buffer;
+		blknr = le32_to_cpu(inode->b.blocks.double_indir_block);
+		status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0,
+					fs->blksz, (char *)di_buffer);
+		for (i = 0; i < fs->blksz / sizeof(int); i++) {
+			if (*di_buffer == 0)
+				break;
+
+			debug("DICB releasing %u\n", *di_buffer);
+			bg_idx = le32_to_cpu(*di_buffer) / blk_per_grp;
+			if (fs->blksz == 1024) {
+				remainder = le32_to_cpu(*di_buffer) % blk_per_grp;
+				if (!remainder)
+					bg_idx--;
+			}
+			/* get  block group descriptor table */
+			bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+			ext4fs_reset_block_bmap(le32_to_cpu(*di_buffer),
+					fs->blk_bmaps[bg_idx], bg_idx);
+			di_buffer++;
+			ext4fs_bg_free_blocks_inc(bgd, fs);
+			ext4fs_sb_free_blocks_inc(fs->sb);
+			/* journal backup */
+			if (prev_bg_bmap_idx != bg_idx) {
+				uint64_t b_bitmap_blk =
+					ext4fs_bg_get_block_id(bgd, fs);
+				status = ext4fs_devread(b_bitmap_blk
+							* fs->sect_perblk, 0,
+							fs->blksz,
+							journal_buffer);
+				if (status == 0)
+					goto fail;
+
+				if (ext4fs_log_journal(journal_buffer,
+						       b_bitmap_blk))
+					goto fail;
+				prev_bg_bmap_idx = bg_idx;
+			}
+		}
+
+		/* removing the parent double indirect block */
+		blknr = le32_to_cpu(inode->b.blocks.double_indir_block);
+		bg_idx = blknr / blk_per_grp;
+		if (fs->blksz == 1024) {
+			remainder = blknr % blk_per_grp;
+			if (!remainder)
+				bg_idx--;
+		}
+		/* get  block group descriptor table */
+		bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+		ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+		ext4fs_bg_free_blocks_inc(bgd, fs);
+		ext4fs_sb_free_blocks_inc(fs->sb);
+		/* journal backup */
+		if (prev_bg_bmap_idx != bg_idx) {
+			uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+			status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk,
+						0, fs->blksz, journal_buffer);
+			if (status == 0)
+				goto fail;
+
+			if (ext4fs_log_journal(journal_buffer, b_bitmap_blk))
+				goto fail;
+			prev_bg_bmap_idx = bg_idx;
+		}
+		debug("DIPB releasing %d\n", blknr);
+	}
+fail:
+	free(dib_start_addr);
+	free(journal_buffer);
+}
+
+static void delete_triple_indirect_block(struct ext2_inode *inode)
+{
+	int i, j;
+	short status;
+	static int prev_bg_bmap_idx = -1;
+	uint32_t blknr;
+	int remainder;
+	int bg_idx;
+	uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group);
+	__le32 *tigp_buffer = NULL;
+	void *tib_start_addr = NULL;
+	__le32 *tip_buffer = NULL;
+	void *tipb_start_addr = NULL;
+	struct ext2_block_group *bgd = NULL;
+	struct ext_filesystem *fs = get_fs();
+	char *journal_buffer = zalloc(fs->blksz);
+	if (!journal_buffer) {
+		printf("No memory\n");
+		return;
+	}
+
+	if (inode->b.blocks.triple_indir_block != 0) {
+		tigp_buffer = zalloc(fs->blksz);
+		if (!tigp_buffer) {
+			printf("No memory\n");
+			return;
+		}
+		tib_start_addr = tigp_buffer;
+		blknr = le32_to_cpu(inode->b.blocks.triple_indir_block);
+		status = ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0,
+					fs->blksz, (char *)tigp_buffer);
+		for (i = 0; i < fs->blksz / sizeof(int); i++) {
+			if (*tigp_buffer == 0)
+				break;
+			debug("tigp buffer releasing %u\n", *tigp_buffer);
+
+			tip_buffer = zalloc(fs->blksz);
+			if (!tip_buffer)
+				goto fail;
+			tipb_start_addr = tip_buffer;
+			status = ext4fs_devread((lbaint_t)le32_to_cpu(*tigp_buffer) *
+						fs->sect_perblk, 0, fs->blksz,
+						(char *)tip_buffer);
+			for (j = 0; j < fs->blksz / sizeof(int); j++) {
+				if (le32_to_cpu(*tip_buffer) == 0)
+					break;
+				bg_idx = le32_to_cpu(*tip_buffer) / blk_per_grp;
+				if (fs->blksz == 1024) {
+					remainder = le32_to_cpu(*tip_buffer) % blk_per_grp;
+					if (!remainder)
+						bg_idx--;
+				}
+
+				ext4fs_reset_block_bmap(le32_to_cpu(*tip_buffer),
+							fs->blk_bmaps[bg_idx],
+							bg_idx);
+
+				tip_buffer++;
+				/* get  block group descriptor table */
+				bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+				ext4fs_bg_free_blocks_inc(bgd, fs);
+				ext4fs_sb_free_blocks_inc(fs->sb);
+				/* journal backup */
+				if (prev_bg_bmap_idx != bg_idx) {
+					uint64_t b_bitmap_blk =
+						ext4fs_bg_get_block_id(bgd, fs);
+					status =
+					    ext4fs_devread(
+							b_bitmap_blk *
+							fs->sect_perblk, 0,
+							fs->blksz,
+							journal_buffer);
+					if (status == 0)
+						goto fail;
+
+					if (ext4fs_log_journal(journal_buffer,
+							       b_bitmap_blk))
+						goto fail;
+					prev_bg_bmap_idx = bg_idx;
+				}
+			}
+			free(tipb_start_addr);
+			tipb_start_addr = NULL;
+
+			/*
+			 * removing the grand parent blocks
+			 * which is connected to inode
+			 */
+			bg_idx = le32_to_cpu(*tigp_buffer) / blk_per_grp;
+			if (fs->blksz == 1024) {
+				remainder = le32_to_cpu(*tigp_buffer) % blk_per_grp;
+				if (!remainder)
+					bg_idx--;
+			}
+			ext4fs_reset_block_bmap(le32_to_cpu(*tigp_buffer),
+						fs->blk_bmaps[bg_idx], bg_idx);
+
+			tigp_buffer++;
+			/* get  block group descriptor table */
+			bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+			ext4fs_bg_free_blocks_inc(bgd, fs);
+			ext4fs_sb_free_blocks_inc(fs->sb);
+			/* journal backup */
+			if (prev_bg_bmap_idx != bg_idx) {
+				uint64_t b_bitmap_blk =
+					ext4fs_bg_get_block_id(bgd, fs);
+				memset(journal_buffer, '\0', fs->blksz);
+				status = ext4fs_devread(b_bitmap_blk *
+							fs->sect_perblk, 0,
+							fs->blksz,
+							journal_buffer);
+				if (status == 0)
+					goto fail;
+
+				if (ext4fs_log_journal(journal_buffer,
+						       b_bitmap_blk))
+					goto fail;
+				prev_bg_bmap_idx = bg_idx;
+			}
+		}
+
+		/* removing the grand parent triple indirect block */
+		blknr = le32_to_cpu(inode->b.blocks.triple_indir_block);
+		bg_idx = blknr / blk_per_grp;
+		if (fs->blksz == 1024) {
+			remainder = blknr % blk_per_grp;
+			if (!remainder)
+				bg_idx--;
+		}
+		ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+		/* get  block group descriptor table */
+		bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+		ext4fs_bg_free_blocks_inc(bgd, fs);
+		ext4fs_sb_free_blocks_inc(fs->sb);
+		/* journal backup */
+		if (prev_bg_bmap_idx != bg_idx) {
+			uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+			status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk,
+						0, fs->blksz, journal_buffer);
+			if (status == 0)
+				goto fail;
+
+			if (ext4fs_log_journal(journal_buffer, b_bitmap_blk))
+				goto fail;
+			prev_bg_bmap_idx = bg_idx;
+		}
+		debug("tigp buffer itself releasing %d\n", blknr);
+	}
+fail:
+	free(tib_start_addr);
+	free(tipb_start_addr);
+	free(journal_buffer);
+}
+
+static int ext4fs_delete_file(int inodeno)
+{
+	struct ext2_inode inode;
+	short status;
+	int i;
+	int remainder;
+	long int blknr;
+	int bg_idx;
+	int ibmap_idx;
+	char *read_buffer = NULL;
+	char *start_block_address = NULL;
+	uint32_t no_blocks;
+
+	static int prev_bg_bmap_idx = -1;
+	unsigned int inodes_per_block;
+	uint32_t blkno;
+	unsigned int blkoff;
+	uint32_t blk_per_grp = le32_to_cpu(ext4fs_root->sblock.blocks_per_group);
+	uint32_t inode_per_grp = le32_to_cpu(ext4fs_root->sblock.inodes_per_group);
+	struct ext2_inode *inode_buffer = NULL;
+	struct ext2_block_group *bgd = NULL;
+	struct ext_filesystem *fs = get_fs();
+	char *journal_buffer = zalloc(fs->blksz);
+	if (!journal_buffer)
+		return -ENOMEM;
+	status = ext4fs_read_inode(ext4fs_root, inodeno, &inode);
+	if (status == 0)
+		goto fail;
+
+	/* read the block no allocated to a file */
+	no_blocks = le32_to_cpu(inode.size) / fs->blksz;
+	if (le32_to_cpu(inode.size) % fs->blksz)
+		no_blocks++;
+
+	/*
+	 * special case for symlinks whose target are small enough that
+	 *it fits in struct ext2_inode.b.symlink: no block had been allocated
+	 */
+	if ((le16_to_cpu(inode.mode) & S_IFLNK) &&
+	    le32_to_cpu(inode.size) <= sizeof(inode.b.symlink)) {
+		no_blocks = 0;
+	}
+
+	if (le32_to_cpu(inode.flags) & EXT4_EXTENTS_FL) {
+		/* FIXME delete extent index blocks, i.e. eh_depth >= 1 */
+		struct ext4_extent_header *eh =
+			(struct ext4_extent_header *)
+				inode.b.blocks.dir_blocks;
+		debug("del: dep=%d entries=%d\n", eh->eh_depth, eh->eh_entries);
+	} else {
+		delete_single_indirect_block(&inode);
+		delete_double_indirect_block(&inode);
+		delete_triple_indirect_block(&inode);
+	}
+
+	/* release data blocks */
+	for (i = 0; i < no_blocks; i++) {
+		blknr = read_allocated_block(&inode, i, NULL);
+		if (blknr == 0)
+			continue;
+		if (blknr < 0)
+			goto fail;
+		bg_idx = blknr / blk_per_grp;
+		if (fs->blksz == 1024) {
+			remainder = blknr % blk_per_grp;
+			if (!remainder)
+				bg_idx--;
+		}
+		ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx],
+					bg_idx);
+		debug("EXT4 Block releasing %ld: %d\n", blknr, bg_idx);
+
+		/* get  block group descriptor table */
+		bgd = ext4fs_get_group_descriptor(fs, bg_idx);
+		ext4fs_bg_free_blocks_inc(bgd, fs);
+		ext4fs_sb_free_blocks_inc(fs->sb);
+		/* journal backup */
+		if (prev_bg_bmap_idx != bg_idx) {
+			uint64_t b_bitmap_blk = ext4fs_bg_get_block_id(bgd, fs);
+			status = ext4fs_devread(b_bitmap_blk * fs->sect_perblk,
+						0, fs->blksz,
+						journal_buffer);
+			if (status == 0)
+				goto fail;
+			if (ext4fs_log_journal(journal_buffer, b_bitmap_blk))
+				goto fail;
+			prev_bg_bmap_idx = bg_idx;
+		}
+	}
+
+	/* release inode */
+	/* from the inode no to blockno */
+	inodes_per_block = fs->blksz / fs->inodesz;
+	ibmap_idx = inodeno / inode_per_grp;
+
+	/* get the block no */
+	inodeno--;
+	/* get  block group descriptor table */
+	bgd = ext4fs_get_group_descriptor(fs, ibmap_idx);
+	blkno = ext4fs_bg_get_inode_table_id(bgd, fs) +
+		(inodeno % inode_per_grp) / inodes_per_block;
+
+	/* get the offset of the inode */
+	blkoff = ((inodeno) % inodes_per_block) * fs->inodesz;
+
+	/* read the block no containing the inode */
+	read_buffer = zalloc(fs->blksz);
+	if (!read_buffer)
+		goto fail;
+	start_block_address = read_buffer;
+	status = ext4fs_devread((lbaint_t)blkno * fs->sect_perblk,
+				0, fs->blksz, read_buffer);
+	if (status == 0)
+		goto fail;
+
+	if (ext4fs_log_journal(read_buffer, blkno))
+		goto fail;
+
+	read_buffer = read_buffer + blkoff;
+	inode_buffer = (struct ext2_inode *)read_buffer;
+	memset(inode_buffer, '\0', fs->inodesz);
+
+	/* write the inode to original position in inode table */
+	if (ext4fs_put_metadata(start_block_address, blkno))
+		goto fail;
+
+	/* update the respective inode bitmaps */
+	inodeno++;
+	ext4fs_reset_inode_bmap(inodeno, fs->inode_bmaps[ibmap_idx], ibmap_idx);
+	ext4fs_bg_free_inodes_inc(bgd, fs);
+	ext4fs_sb_free_inodes_inc(fs->sb);
+	/* journal backup */
+	memset(journal_buffer, '\0', fs->blksz);
+	status = ext4fs_devread(ext4fs_bg_get_inode_id(bgd, fs) *
+				fs->sect_perblk, 0, fs->blksz, journal_buffer);
+	if (status == 0)
+		goto fail;
+	if (ext4fs_log_journal(journal_buffer, ext4fs_bg_get_inode_id(bgd, fs)))
+		goto fail;
+
+	ext4fs_update();
+	ext4fs_deinit();
+	ext4fs_reinit_global();
+
+	if (ext4fs_init() != 0) {
+		printf("error in File System init\n");
+		goto fail;
+	}
+
+	free(start_block_address);
+	free(journal_buffer);
+
+	return 0;
+fail:
+	free(start_block_address);
+	free(journal_buffer);
+
+	return -1;
+}
+
+int ext4fs_init(void)
+{
+	short status;
+	int i;
+	uint32_t real_free_blocks = 0;
+	struct ext_filesystem *fs = get_fs();
+
+	/* populate fs */
+	fs->blksz = EXT2_BLOCK_SIZE(ext4fs_root);
+	fs->sect_perblk = fs->blksz >> fs->dev_desc->log2blksz;
+
+	/* get the superblock */
+	fs->sb = zalloc(SUPERBLOCK_SIZE);
+	if (!fs->sb)
+		return -ENOMEM;
+	if (!ext4_read_superblock((char *)fs->sb))
+		goto fail;
+
+	/* init journal */
+	if (ext4fs_init_journal())
+		goto fail;
+
+	/* get total no of blockgroups */
+	fs->no_blkgrp = (uint32_t)ext4fs_div_roundup(
+			le32_to_cpu(ext4fs_root->sblock.total_blocks)
+			- le32_to_cpu(ext4fs_root->sblock.first_data_block),
+			le32_to_cpu(ext4fs_root->sblock.blocks_per_group));
+
+	/* get the block group descriptor table */
+	fs->gdtable_blkno = ((EXT2_MIN_BLOCK_SIZE == fs->blksz) + 1);
+	if (ext4fs_get_bgdtable() == -1) {
+		printf("Error in getting the block group descriptor table\n");
+		goto fail;
+	}
+
+	/* load all the available bitmap block of the partition */
+	fs->blk_bmaps = zalloc(fs->no_blkgrp * sizeof(char *));
+	if (!fs->blk_bmaps)
+		goto fail;
+	for (i = 0; i < fs->no_blkgrp; i++) {
+		fs->blk_bmaps[i] = zalloc(fs->blksz);
+		if (!fs->blk_bmaps[i])
+			goto fail;
+	}
+
+	for (i = 0; i < fs->no_blkgrp; i++) {
+		struct ext2_block_group *bgd =
+			ext4fs_get_group_descriptor(fs, i);
+		status = ext4fs_devread(ext4fs_bg_get_block_id(bgd, fs) *
+				   fs->sect_perblk, 0,
+				   fs->blksz, (char *)fs->blk_bmaps[i]);
+		if (status == 0)
+			goto fail;
+	}
+
+	/* load all the available inode bitmap of the partition */
+	fs->inode_bmaps = zalloc(fs->no_blkgrp * sizeof(unsigned char *));
+	if (!fs->inode_bmaps)
+		goto fail;
+	for (i = 0; i < fs->no_blkgrp; i++) {
+		fs->inode_bmaps[i] = zalloc(fs->blksz);
+		if (!fs->inode_bmaps[i])
+			goto fail;
+	}
+
+	for (i = 0; i < fs->no_blkgrp; i++) {
+		struct ext2_block_group *bgd =
+			ext4fs_get_group_descriptor(fs, i);
+		status = ext4fs_devread(ext4fs_bg_get_inode_id(bgd, fs) *
+					fs->sect_perblk,
+					0, fs->blksz,
+					(char *)fs->inode_bmaps[i]);
+		if (status == 0)
+			goto fail;
+	}
+
+	/*
+	 * check filesystem consistency with free blocks of file system
+	 * some time we observed that superblock freeblocks does not match
+	 * with the  blockgroups freeblocks when improper
+	 * reboot of a linux kernel
+	 */
+	for (i = 0; i < fs->no_blkgrp; i++) {
+		struct ext2_block_group *bgd =
+			ext4fs_get_group_descriptor(fs, i);
+		real_free_blocks = real_free_blocks +
+			ext4fs_bg_get_free_blocks(bgd, fs);
+	}
+	if (real_free_blocks != ext4fs_sb_get_free_blocks(fs->sb))
+		ext4fs_sb_set_free_blocks(fs->sb, real_free_blocks);
+
+	return 0;
+fail:
+	ext4fs_deinit();
+
+	return -1;
+}
+
+void ext4fs_deinit(void)
+{
+	int i;
+	struct ext2_inode inode_journal;
+	struct journal_superblock_t *jsb;
+	uint32_t blknr;
+	struct ext_filesystem *fs = get_fs();
+	uint32_t new_feature_incompat;
+
+	/* free journal */
+	char *temp_buff = zalloc(fs->blksz);
+	if (temp_buff) {
+		ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO,
+				  &inode_journal);
+		blknr = read_allocated_block(&inode_journal,
+					EXT2_JOURNAL_SUPERBLOCK, NULL);
+		ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz,
+			       temp_buff);
+		jsb = (struct journal_superblock_t *)temp_buff;
+		jsb->s_start = 0;
+		put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
+			 (struct journal_superblock_t *)temp_buff, fs->blksz);
+		free(temp_buff);
+	}
+	ext4fs_free_journal();
+
+	/* get the superblock */
+	ext4_read_superblock((char *)fs->sb);
+	new_feature_incompat = le32_to_cpu(fs->sb->feature_incompat);
+	new_feature_incompat &= ~EXT3_FEATURE_INCOMPAT_RECOVER;
+	fs->sb->feature_incompat = cpu_to_le32(new_feature_incompat);
+	put_ext4((uint64_t)(SUPERBLOCK_SIZE),
+		 (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE);
+	free(fs->sb);
+	fs->sb = NULL;
+
+	if (fs->blk_bmaps) {
+		for (i = 0; i < fs->no_blkgrp; i++) {
+			free(fs->blk_bmaps[i]);
+			fs->blk_bmaps[i] = NULL;
+		}
+		free(fs->blk_bmaps);
+		fs->blk_bmaps = NULL;
+	}
+
+	if (fs->inode_bmaps) {
+		for (i = 0; i < fs->no_blkgrp; i++) {
+			free(fs->inode_bmaps[i]);
+			fs->inode_bmaps[i] = NULL;
+		}
+		free(fs->inode_bmaps);
+		fs->inode_bmaps = NULL;
+	}
+
+
+	free(fs->gdtable);
+	fs->gdtable = NULL;
+	/*
+	 * reinitiliazed the global inode and
+	 * block bitmap first execution check variables
+	 */
+	fs->first_pass_ibmap = 0;
+	fs->first_pass_bbmap = 0;
+	fs->curr_inode_no = 0;
+	fs->curr_blkno = 0;
+}
+
+/*
+ * Write data to filesystem blocks. Uses same optimization for
+ * contigous sectors as ext4fs_read_file
+ */
+static int ext4fs_write_file(struct ext2_inode *file_inode,
+			     int pos, unsigned int len, const char *buf)
+{
+	int i;
+	int blockcnt;
+	uint32_t filesize = le32_to_cpu(file_inode->size);
+	struct ext_filesystem *fs = get_fs();
+	int log2blksz = fs->dev_desc->log2blksz;
+	int log2_fs_blocksize = LOG2_BLOCK_SIZE(ext4fs_root) - log2blksz;
+	int previous_block_number = -1;
+	int delayed_start = 0;
+	int delayed_extent = 0;
+	int delayed_next = 0;
+	const char *delayed_buf = NULL;
+
+	/* Adjust len so it we can't read past the end of the file. */
+	if (len > filesize)
+		len = filesize;
+
+	blockcnt = ((len + pos) + fs->blksz - 1) / fs->blksz;
+
+	for (i = pos / fs->blksz; i < blockcnt; i++) {
+		long int blknr;
+		int blockend = fs->blksz;
+		int skipfirst = 0;
+		blknr = read_allocated_block(file_inode, i, NULL);
+		if (blknr <= 0)
+			return -1;
+
+		blknr = blknr << log2_fs_blocksize;
+
+		if (blknr) {
+			if (previous_block_number != -1) {
+				if (delayed_next == blknr) {
+					delayed_extent += blockend;
+					delayed_next += blockend >> log2blksz;
+				} else {	/* spill */
+					put_ext4((uint64_t)
+						 ((uint64_t)delayed_start << log2blksz),
+						 delayed_buf,
+						 (uint32_t) delayed_extent);
+					previous_block_number = blknr;
+					delayed_start = blknr;
+					delayed_extent = blockend;
+					delayed_buf = buf;
+					delayed_next = blknr +
+					    (blockend >> log2blksz);
+				}
+			} else {
+				previous_block_number = blknr;
+				delayed_start = blknr;
+				delayed_extent = blockend;
+				delayed_buf = buf;
+				delayed_next = blknr +
+				    (blockend >> log2blksz);
+			}
+		} else {
+			if (previous_block_number != -1) {
+				/* spill */
+				put_ext4((uint64_t) ((uint64_t)delayed_start <<
+						     log2blksz),
+					 delayed_buf,
+					 (uint32_t) delayed_extent);
+				previous_block_number = -1;
+			}
+		}
+		buf += fs->blksz - skipfirst;
+	}
+	if (previous_block_number != -1) {
+		/* spill */
+		put_ext4((uint64_t) ((uint64_t)delayed_start << log2blksz),
+			 delayed_buf, (uint32_t) delayed_extent);
+		previous_block_number = -1;
+	}
+
+	return len;
+}
+
+int ext4fs_write(const char *fname, const char *buffer,
+		 unsigned long sizebytes, int type)
+{
+	int ret = 0;
+	struct ext2_inode *file_inode = NULL;
+	unsigned char *inode_buffer = NULL;
+	int parent_inodeno;
+	int inodeno;
+	time_t timestamp = 0;
+
+	uint64_t bytes_reqd_for_file;
+	unsigned int blks_reqd_for_file;
+	unsigned int blocks_remaining;
+	int existing_file_inodeno;
+	char *temp_ptr = NULL;
+	long int itable_blkno;
+	long int parent_itable_blkno;
+	long int blkoff;
+	struct ext2_sblock *sblock = &(ext4fs_root->sblock);
+	unsigned int inodes_per_block;
+	unsigned int ibmap_idx;
+	struct ext2_block_group *bgd = NULL;
+	struct ext_filesystem *fs = get_fs();
+	ALLOC_CACHE_ALIGN_BUFFER(char, filename, 256);
+	bool store_link_in_inode = false;
+	memset(filename, 0x00, 256);
+
+	if (type != FILETYPE_REG && type != FILETYPE_SYMLINK)
+		return -1;
+
+	g_parent_inode = zalloc(fs->inodesz);
+	if (!g_parent_inode)
+		goto fail;
+
+	if (ext4fs_init() != 0) {
+		printf("error in File System init\n");
+		return -1;
+	}
+
+	if (le32_to_cpu(fs->sb->feature_ro_compat) & EXT4_FEATURE_RO_COMPAT_METADATA_CSUM) {
+		printf("Unsupported feature metadata_csum found, not writing.\n");
+		return -1;
+	}
+
+	inodes_per_block = fs->blksz / fs->inodesz;
+	parent_inodeno = ext4fs_get_parent_inode_num(fname, filename, F_FILE);
+	if (parent_inodeno == -1)
+		goto fail;
+	if (ext4fs_iget(parent_inodeno, g_parent_inode))
+		goto fail;
+	/* do not mess up a directory using hash trees */
+	if (le32_to_cpu(g_parent_inode->flags) & EXT4_INDEX_FL) {
+		printf("hash tree directory\n");
+		goto fail;
+	}
+	/* check if the filename is already present in root */
+	existing_file_inodeno = ext4fs_filename_unlink(filename);
+	if (existing_file_inodeno != -1) {
+		ret = ext4fs_delete_file(existing_file_inodeno);
+		fs->first_pass_bbmap = 0;
+		fs->curr_blkno = 0;
+
+		fs->first_pass_ibmap = 0;
+		fs->curr_inode_no = 0;
+		if (ret)
+			goto fail;
+	}
+
+	/* calculate how many blocks required */
+	if (type == FILETYPE_SYMLINK &&
+	    sizebytes <= sizeof(file_inode->b.symlink)) {
+		store_link_in_inode = true;
+		bytes_reqd_for_file = 0;
+	} else {
+		bytes_reqd_for_file = sizebytes;
+	}
+
+	blks_reqd_for_file = lldiv(bytes_reqd_for_file, fs->blksz);
+	if (do_div(bytes_reqd_for_file, fs->blksz) != 0) {
+		blks_reqd_for_file++;
+		debug("total bytes for a file %u\n", blks_reqd_for_file);
+	}
+	blocks_remaining = blks_reqd_for_file;
+	/* test for available space in partition */
+	if (le32_to_cpu(fs->sb->free_blocks) < blks_reqd_for_file) {
+		printf("Not enough space on partition !!!\n");
+		goto fail;
+	}
+
+	inodeno = ext4fs_update_parent_dentry(filename, type);
+	if (inodeno == -1)
+		goto fail;
+	/* prepare file inode */
+	inode_buffer = zalloc(fs->inodesz);
+	if (!inode_buffer)
+		goto fail;
+	file_inode = (struct ext2_inode *)inode_buffer;
+	file_inode->size = cpu_to_le32(sizebytes);
+	if (type == FILETYPE_SYMLINK) {
+		file_inode->mode = cpu_to_le16(S_IFLNK | S_IRWXU | S_IRWXG |
+					       S_IRWXO);
+		if (store_link_in_inode) {
+			strncpy(file_inode->b.symlink, buffer, sizebytes);
+			sizebytes = 0;
+		}
+	} else {
+		file_inode->mode = cpu_to_le16(S_IFREG | S_IRWXU | S_IRGRP |
+					       S_IROTH | S_IXGRP | S_IXOTH);
+	}
+	/* ToDo: Update correct time */
+	file_inode->mtime = cpu_to_le32(timestamp);
+	file_inode->atime = cpu_to_le32(timestamp);
+	file_inode->ctime = cpu_to_le32(timestamp);
+	file_inode->nlinks = cpu_to_le16(1);
+
+	/* Allocate data blocks */
+	ext4fs_allocate_blocks(file_inode, blocks_remaining,
+			       &blks_reqd_for_file);
+	file_inode->blockcnt = cpu_to_le32((blks_reqd_for_file * fs->blksz) >>
+					   LOG2_SECTOR_SIZE);
+
+	temp_ptr = zalloc(fs->blksz);
+	if (!temp_ptr)
+		goto fail;
+	ibmap_idx = inodeno / le32_to_cpu(ext4fs_root->sblock.inodes_per_group);
+	inodeno--;
+	bgd = ext4fs_get_group_descriptor(fs, ibmap_idx);
+	itable_blkno = ext4fs_bg_get_inode_table_id(bgd, fs) +
+			(inodeno % le32_to_cpu(sblock->inodes_per_group)) /
+			inodes_per_block;
+	blkoff = (inodeno % inodes_per_block) * fs->inodesz;
+	ext4fs_devread((lbaint_t)itable_blkno * fs->sect_perblk, 0, fs->blksz,
+		       temp_ptr);
+	if (ext4fs_log_journal(temp_ptr, itable_blkno))
+		goto fail;
+
+	memcpy(temp_ptr + blkoff, inode_buffer, fs->inodesz);
+	if (ext4fs_put_metadata(temp_ptr, itable_blkno))
+		goto fail;
+	/* copy the file content into data blocks */
+	if (ext4fs_write_file(file_inode, 0, sizebytes, buffer) == -1) {
+		printf("Error in copying content\n");
+		/* FIXME: Deallocate data blocks */
+		goto fail;
+	}
+	ibmap_idx = parent_inodeno / le32_to_cpu(ext4fs_root->sblock.inodes_per_group);
+	parent_inodeno--;
+	bgd = ext4fs_get_group_descriptor(fs, ibmap_idx);
+	parent_itable_blkno = ext4fs_bg_get_inode_table_id(bgd, fs) +
+	    (parent_inodeno %
+	     le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
+	blkoff = (parent_inodeno % inodes_per_block) * fs->inodesz;
+	if (parent_itable_blkno != itable_blkno) {
+		memset(temp_ptr, '\0', fs->blksz);
+		ext4fs_devread((lbaint_t)parent_itable_blkno * fs->sect_perblk,
+			       0, fs->blksz, temp_ptr);
+		if (ext4fs_log_journal(temp_ptr, parent_itable_blkno))
+			goto fail;
+
+		memcpy(temp_ptr + blkoff, g_parent_inode, fs->inodesz);
+		if (ext4fs_put_metadata(temp_ptr, parent_itable_blkno))
+			goto fail;
+	} else {
+		/*
+		 * If parent and child fall in same inode table block
+		 * both should be kept in 1 buffer
+		 */
+		memcpy(temp_ptr + blkoff, g_parent_inode, fs->inodesz);
+		gd_index--;
+		if (ext4fs_put_metadata(temp_ptr, itable_blkno))
+			goto fail;
+	}
+	ext4fs_update();
+	ext4fs_deinit();
+
+	fs->first_pass_bbmap = 0;
+	fs->curr_blkno = 0;
+	fs->first_pass_ibmap = 0;
+	fs->curr_inode_no = 0;
+	free(inode_buffer);
+	free(g_parent_inode);
+	free(temp_ptr);
+	g_parent_inode = NULL;
+
+	return 0;
+fail:
+	ext4fs_deinit();
+	free(inode_buffer);
+	free(g_parent_inode);
+	free(temp_ptr);
+	g_parent_inode = NULL;
+
+	return -1;
+}
+
+int ext4_write_file(const char *filename, void *buf, loff_t offset,
+		    loff_t len, loff_t *actwrite)
+{
+	int ret;
+
+	if (offset != 0) {
+		printf("** Cannot support non-zero offset **\n");
+		return -1;
+	}
+
+	ret = ext4fs_write(filename, buf, len, FILETYPE_REG);
+	if (ret) {
+		printf("** Error ext4fs_write() **\n");
+		goto fail;
+	}
+
+	*actwrite = len;
+
+	return 0;
+
+fail:
+	*actwrite = 0;
+
+	return -1;
+}
+
+int ext4fs_create_link(const char *target, const char *fname)
+{
+	return ext4fs_write(fname, target, strlen(target), FILETYPE_SYMLINK);
+}
diff --git a/ext4fs.c b/ext4fs.c
new file mode 100644
index 0000000..37b31d9
--- /dev/null
+++ b/ext4fs.c
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * ext4ls and ext4load : Based on ext2 ls and load support in Uboot.
+ *		       Ext4 read optimization taken from Open-Moko
+ *		       Qi bootloader
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB  --  GRand Unified Bootloader
+ * Copyright (C) 2003, 2004  Free Software Foundation, Inc.
+ *
+ * ext4write : Based on generic ext4 protocol.
+ */
+
+#include <common.h>
+#include <ext_common.h>
+#include <ext4fs.h>
+#include "ext4_common.h"
+#include <div64.h>
+
+int ext4fs_symlinknest;
+struct ext_filesystem ext_fs;
+
+struct ext_filesystem *get_fs(void)
+{
+	return &ext_fs;
+}
+
+void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot)
+{
+	if ((node != &ext4fs_root->diropen) && (node != currroot))
+		free(node);
+}
+
+/*
+ * Taken from openmoko-kernel mailing list: By Andy green
+ * Optimized read file API : collects and defers contiguous sector
+ * reads into one potentially more efficient larger sequential read action
+ */
+int ext4fs_read_file(struct ext2fs_node *node, loff_t pos,
+		loff_t len, char *buf, loff_t *actread)
+{
+	struct ext_filesystem *fs = get_fs();
+	int i;
+	lbaint_t blockcnt;
+	int log2blksz = fs->dev_desc->log2blksz;
+	int log2_fs_blocksize = LOG2_BLOCK_SIZE(node->data) - log2blksz;
+	int blocksize = (1 << (log2_fs_blocksize + log2blksz));
+	unsigned int filesize = le32_to_cpu(node->inode.size);
+	lbaint_t previous_block_number = -1;
+	lbaint_t delayed_start = 0;
+	lbaint_t delayed_extent = 0;
+	lbaint_t delayed_skipfirst = 0;
+	lbaint_t delayed_next = 0;
+	char *delayed_buf = NULL;
+	char *start_buf = buf;
+	short status;
+	struct ext_block_cache cache;
+
+	ext_cache_init(&cache);
+
+	/* Adjust len so it we can't read past the end of the file. */
+	if (len + pos > filesize)
+		len = (filesize - pos);
+
+	if (blocksize <= 0 || len <= 0) {
+		ext_cache_fini(&cache);
+		return -1;
+	}
+
+	blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize);
+
+	for (i = lldiv(pos, blocksize); i < blockcnt; i++) {
+		long int blknr;
+		int blockoff = pos - (blocksize * i);
+		int blockend = blocksize;
+		int skipfirst = 0;
+		blknr = read_allocated_block(&node->inode, i, &cache);
+		if (blknr < 0) {
+			ext_cache_fini(&cache);
+			return -1;
+		}
+
+		blknr = blknr << log2_fs_blocksize;
+
+		/* Last block.  */
+		if (i == blockcnt - 1) {
+			blockend = (len + pos) - (blocksize * i);
+
+			/* The last portion is exactly blocksize. */
+			if (!blockend)
+				blockend = blocksize;
+		}
+
+		/* First block. */
+		if (i == lldiv(pos, blocksize)) {
+			skipfirst = blockoff;
+			blockend -= skipfirst;
+		}
+		if (blknr) {
+			int status;
+
+			if (previous_block_number != -1) {
+				if (delayed_next == blknr) {
+					delayed_extent += blockend;
+					delayed_next += blockend >> log2blksz;
+				} else {	/* spill */
+					status = ext4fs_devread(delayed_start,
+							delayed_skipfirst,
+							delayed_extent,
+							delayed_buf);
+					if (status == 0) {
+						ext_cache_fini(&cache);
+						return -1;
+					}
+					previous_block_number = blknr;
+					delayed_start = blknr;
+					delayed_extent = blockend;
+					delayed_skipfirst = skipfirst;
+					delayed_buf = buf;
+					delayed_next = blknr +
+						(blockend >> log2blksz);
+				}
+			} else {
+				previous_block_number = blknr;
+				delayed_start = blknr;
+				delayed_extent = blockend;
+				delayed_skipfirst = skipfirst;
+				delayed_buf = buf;
+				delayed_next = blknr +
+					(blockend >> log2blksz);
+			}
+		} else {
+			int n;
+			int n_left;
+			if (previous_block_number != -1) {
+				/* spill */
+				status = ext4fs_devread(delayed_start,
+							delayed_skipfirst,
+							delayed_extent,
+							delayed_buf);
+				if (status == 0) {
+					ext_cache_fini(&cache);
+					return -1;
+				}
+				previous_block_number = -1;
+			}
+			/* Zero no more than `len' bytes. */
+			n = blocksize - skipfirst;
+			n_left = len - ( buf - start_buf );
+			if (n > n_left)
+				n = n_left;
+			memset(buf, 0, n);
+		}
+		buf += blocksize - skipfirst;
+	}
+	if (previous_block_number != -1) {
+		/* spill */
+		status = ext4fs_devread(delayed_start,
+					delayed_skipfirst, delayed_extent,
+					delayed_buf);
+		if (status == 0) {
+			ext_cache_fini(&cache);
+			return -1;
+		}
+		previous_block_number = -1;
+	}
+
+	*actread  = len;
+	ext_cache_fini(&cache);
+	return 0;
+}
+
+int ext4fs_ls(const char *dirname)
+{
+	struct ext2fs_node *dirnode = NULL;
+	int status;
+
+	if (dirname == NULL)
+		return 0;
+
+	status = ext4fs_find_file(dirname, &ext4fs_root->diropen, &dirnode,
+				  FILETYPE_DIRECTORY);
+	if (status != 1) {
+		printf("** Can not find directory. **\n");
+		if (dirnode)
+			ext4fs_free_node(dirnode, &ext4fs_root->diropen);
+		return 1;
+	}
+
+	ext4fs_iterate_dir(dirnode, NULL, NULL, NULL);
+	ext4fs_free_node(dirnode, &ext4fs_root->diropen);
+
+	return 0;
+}
+
+int ext4fs_exists(const char *filename)
+{
+	loff_t file_len;
+	int ret;
+
+	ret = ext4fs_open(filename, &file_len);
+	return ret == 0;
+}
+
+int ext4fs_size(const char *filename, loff_t *size)
+{
+	return ext4fs_open(filename, size);
+}
+
+int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread)
+{
+	if (ext4fs_root == NULL || ext4fs_file == NULL)
+		return -1;
+
+	return ext4fs_read_file(ext4fs_file, offset, len, buf, actread);
+}
+
+int ext4fs_probe(struct blk_desc *fs_dev_desc,
+		 disk_partition_t *fs_partition)
+{
+	ext4fs_set_blk_dev(fs_dev_desc, fs_partition);
+
+	if (!ext4fs_mount(fs_partition->size)) {
+		ext4fs_close();
+		return -1;
+	}
+
+	return 0;
+}
+
+int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
+		   loff_t *len_read)
+{
+	loff_t file_len;
+	int ret;
+
+	ret = ext4fs_open(filename, &file_len);
+	if (ret < 0) {
+		printf("** File not found %s **\n", filename);
+		return -1;
+	}
+
+	if (len == 0)
+		len = file_len;
+
+	return ext4fs_read(buf, offset, len, len_read);
+}
+
+int ext4fs_uuid(char *uuid_str)
+{
+	if (ext4fs_root == NULL)
+		return -1;
+
+#ifdef CONFIG_LIB_UUID
+	uuid_bin_to_str((unsigned char *)ext4fs_root->sblock.unique_id,
+			uuid_str, UUID_STR_FORMAT_STD);
+
+	return 0;
+#else
+	return -ENOSYS;
+#endif
+}
+
+void ext_cache_init(struct ext_block_cache *cache)
+{
+	memset(cache, 0, sizeof(*cache));
+}
+
+void ext_cache_fini(struct ext_block_cache *cache)
+{
+	free(cache->buf);
+	ext_cache_init(cache);
+}
+
+int ext_cache_read(struct ext_block_cache *cache, lbaint_t block, int size)
+{
+	/* This could be more lenient, but this is simple and enough for now */
+	if (cache->buf && cache->block == block && cache->size == size)
+		return 1;
+	ext_cache_fini(cache);
+	cache->buf = malloc(size);
+	if (!cache->buf)
+		return 0;
+	if (!ext4fs_devread(block, 0, size, cache->buf)) {
+		ext_cache_fini(cache);
+		return 0;
+	}
+	cache->block = block;
+	cache->size = size;
+	return 1;
+}
diff --git a/include/.gitignore b/include/.gitignore
new file mode 100644
index 0000000..8e41a95
--- /dev/null
+++ b/include/.gitignore
@@ -0,0 +1,4 @@
+/autoconf.mk*
+/bmp_logo.h
+/bmp_logo_data.h
+/config.h
diff --git a/include/ACEX1K.h b/include/ACEX1K.h
new file mode 100644
index 0000000..7c5253c
--- /dev/null
+++ b/include/ACEX1K.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2003
+ * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
+ *
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ */
+
+#ifndef _ACEX1K_H_
+#define _ACEX1K_H_
+
+#include <altera.h>
+
+extern int ACEX1K_load(Altera_desc *desc, const void *image, size_t size);
+extern int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int ACEX1K_info(Altera_desc *desc);
+
+extern int CYC2_load(Altera_desc *desc, const void *image, size_t size);
+extern int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int CYC2_info(Altera_desc *desc);
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	Altera_pre_fn		pre;
+	Altera_config_fn	config;
+	Altera_clk_fn		clk;
+	Altera_status_fn	status;
+	Altera_done_fn		done;
+	Altera_data_fn		data;
+	Altera_abort_fn		abort;
+	Altera_post_fn		post;
+} Altera_ACEX1K_Passive_Serial_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	Altera_pre_fn		pre;
+	Altera_config_fn	config;
+	Altera_status_fn	status;
+	Altera_done_fn		done;
+	Altera_write_fn		write;
+	Altera_abort_fn		abort;
+	Altera_post_fn		post;
+} Altera_CYC2_Passive_Serial_fns;
+
+/* Device Image Sizes
+ *********************************************************************/
+/* ACEX1K */
+/* FIXME: Which size do we mean?
+ * Datasheet says 1337000/8=167125Bytes,
+ * Filesize of an *.rbf file is 166965 Bytes
+ */
+#if 0
+#define Altera_EP1K100_SIZE	1337000/8	/* 167125 Bytes */
+#endif
+#define Altera_EP1K100_SIZE	(166965*8)
+
+#define Altera_EP2C8_SIZE	247942
+#define Altera_EP2C20_SIZE	586562
+#define Altera_EP2C35_SIZE	883905
+#define Altera_EP3C5_SIZE	368011		/* .rbf size in bytes */
+
+#define ALTERA_EP4CE6_SIZE	368011		/* 2944088 Bits */
+#define ALTERA_EP4CE10_SIZE	368011		/* 2944088 Bits */
+#define ALTERA_EP4CE15_SIZE	510856		/* 4086848 Bits */
+#define ALTERA_EP4CE22_SIZE	718569		/* 5748552 Bits */
+#define ALTERA_EP4CE30_SIZE	1191788		/* 9534304 Bits */
+#define ALTERA_EP4CE40_SIZE	1191788		/* 9534304 Bits */
+#define ALTERA_EP4CE55_SIZE	1861195		/* 14889560 Bits */
+#define ALTERA_EP4CE75_SIZE	2495719		/* 19965752 Bits */
+#define ALTERA_EP4CE115_SIZE	3571462		/* 28571696 Bits */
+
+/* Descriptor Macros
+ *********************************************************************/
+/* ACEX1K devices */
+#define Altera_EP1K100_DESC(iface, fn_table, cookie) \
+{ Altera_ACEX1K, iface, Altera_EP1K100_SIZE, fn_table, cookie }
+
+#endif /* _ACEX1K_H_ */
diff --git a/include/MCD_dma.h b/include/MCD_dma.h
new file mode 100644
index 0000000..2f16c89
--- /dev/null
+++ b/include/MCD_dma.h
@@ -0,0 +1,369 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _MCD_API_H
+#define _MCD_API_H
+
+/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
+#undef MCD_INCLUDE_EU
+
+/* Number of DMA channels */
+#define NCHANNELS	16
+
+/* Total number of variants */
+#ifdef MCD_INCLUDE_EU
+#define NUMOFVARIANTS	6
+#else
+#define NUMOFVARIANTS	4
+#endif
+
+/* Define sizes of the various tables */
+#define TASK_TABLE_SIZE		(NCHANNELS*32)
+#define VAR_TAB_SIZE		(128)
+#define CONTEXT_SAVE_SIZE	(128)
+#define FUNCDESC_TAB_SIZE	(256)
+
+#ifdef MCD_INCLUDE_EU
+#define FUNCDESC_TAB_NUM	16
+#else
+#define FUNCDESC_TAB_NUM	1
+#endif
+
+#ifndef DEFINESONLY
+
+/* Portability typedefs */
+#if 1
+#include "common.h"
+#else
+#ifndef s32
+typedef int s32;
+#endif
+#ifndef u32
+typedef unsigned int u32;
+#endif
+#ifndef s16
+typedef short s16;
+#endif
+#ifndef u16
+typedef unsigned short u16;
+#endif
+#ifndef s8
+typedef char s8;
+#endif
+#ifndef u8
+typedef unsigned char u8;
+#endif
+#endif
+
+/*
+ * These structures represent the internal registers of the
+ * multi-channel DMA
+ */
+struct dmaRegs_s {
+	u32 taskbar;		/* task table base address */
+	u32 currPtr;
+	u32 endPtr;
+	u32 varTablePtr;
+	u16 dma_rsvd0;
+	u16 ptdControl;		/* ptd control */
+	u32 intPending;		/* interrupt pending */
+	u32 intMask;		/* interrupt mask */
+	u16 taskControl[16];	/* task control */
+	u8 priority[32];	/* priority */
+	u32 initiatorMux;	/* initiator mux control */
+	u32 taskSize0;		/* task size control 0. */
+	u32 taskSize1;		/* task size control 1. */
+	u32 dma_rsvd1;		/* reserved */
+	u32 dma_rsvd2;		/* reserved */
+	u32 debugComp1;		/* debug comparator 1 */
+	u32 debugComp2;		/* debug comparator 2 */
+	u32 debugControl;	/* debug control */
+	u32 debugStatus;	/* debug status */
+	u32 ptdDebug;		/* priority task decode debug */
+	u32 dma_rsvd3[31];	/* reserved */
+};
+typedef volatile struct dmaRegs_s dmaRegs;
+
+#endif
+
+/* PTD contrl reg bits */
+#define PTD_CTL_TSK_PRI		0x8000
+#define PTD_CTL_COMM_PREFETCH	0x0001
+
+/* Task Control reg bits and field masks */
+#define TASK_CTL_EN		0x8000
+#define TASK_CTL_VALID		0x4000
+#define TASK_CTL_ALWAYS		0x2000
+#define TASK_CTL_INIT_MASK	0x1f00
+#define TASK_CTL_ASTRT		0x0080
+#define TASK_CTL_HIPRITSKEN	0x0040
+#define TASK_CTL_HLDINITNUM	0x0020
+#define TASK_CTL_ASTSKNUM_MASK	0x000f
+
+/* Priority reg bits and field masks */
+#define PRIORITY_HLD		0x80
+#define PRIORITY_PRI_MASK	0x07
+
+/* Debug Control reg bits and field masks */
+#define DBG_CTL_BLOCK_TASKS_MASK	0xffff0000
+#define DBG_CTL_AUTO_ARM		0x00008000
+#define DBG_CTL_BREAK			0x00004000
+#define DBG_CTL_COMP1_TYP_MASK		0x00003800
+#define DBG_CTL_COMP2_TYP_MASK		0x00000070
+#define DBG_CTL_EXT_BREAK		0x00000004
+#define DBG_CTL_INT_BREAK		0x00000002
+
+/*
+ * PTD Debug reg selector addresses
+ * This reg must be written with a value to show the contents of
+ * one of the desired internal register.
+ */
+#define PTD_DBG_REQ		0x00	/* shows the state of 31 initiators */
+#define PTD_DBG_TSK_VLD_INIT	0x01	/* shows which 16 tasks are valid and
+					   have initiators asserted */
+
+/* General return values */
+#define MCD_OK			0
+#define MCD_ERROR		-1
+#define MCD_TABLE_UNALIGNED	-2
+#define MCD_CHANNEL_INVALID	-3
+
+/* MCD_initDma input flags */
+#define MCD_RELOC_TASKS		0x00000001
+#define MCD_NO_RELOC_TASKS	0x00000000
+#define MCD_COMM_PREFETCH_EN	0x00000002	/* MCF547x/548x ONLY */
+
+/*
+ * MCD_dmaStatus Status Values for each channel:
+ * MCD_NO_DMA	- No DMA has been requested since reset
+ * MCD_IDLE	- DMA active, but the initiator is currently inactive
+ * MCD_RUNNING	- DMA active, and the initiator is currently active
+ * MCD_PAUSED	- DMA active but it is currently paused
+ * MCD_HALTED	- the most recent DMA has been killed with MCD_killTask()
+ * MCD_DONE	- the most recent DMA has completed
+ */
+#define MCD_NO_DMA		1
+#define MCD_IDLE		2
+#define MCD_RUNNING		3
+#define MCD_PAUSED		4
+#define MCD_HALTED		5
+#define MCD_DONE		6
+
+/* MCD_startDma parameter defines */
+
+/* Constants for the funcDesc parameter */
+/*
+ * MCD_NO_BYTE_SWAP	- to disable byte swapping
+ * MCD_BYTE_REVERSE	- to reverse the bytes of each u32 of the DMAed data
+ * MCD_U16_REVERSE	- to reverse the 16-bit halves of each 32-bit data
+ *			  value being DMAed
+ * MCD_U16_BYTE_REVERSE	- to reverse the byte halves of each 16-bit half of
+ *			  each 32-bit data value DMAed
+ * MCD_NO_BIT_REV	- do not reverse the bits of each byte DMAed
+ * MCD_BIT_REV		- reverse the bits of each byte DMAed
+ * MCD_CRC16		- to perform CRC-16 on DMAed data
+ * MCD_CRCCCITT		- to perform CRC-CCITT on DMAed data
+ * MCD_CRC32		- to perform CRC-32 on DMAed data
+ * MCD_CSUMINET		- to perform internet checksums on DMAed data
+ * MCD_NO_CSUM		- to perform no checksumming
+ */
+#define MCD_NO_BYTE_SWAP	0x00045670
+#define MCD_BYTE_REVERSE	0x00076540
+#define MCD_U16_REVERSE		0x00067450
+#define MCD_U16_BYTE_REVERSE	0x00054760
+#define MCD_NO_BIT_REV		0x00000000
+#define MCD_BIT_REV		0x00088880
+/* CRCing: */
+#define MCD_CRC16		0xc0100000
+#define MCD_CRCCCITT		0xc0200000
+#define MCD_CRC32		0xc0300000
+#define MCD_CSUMINET		0xc0400000
+#define MCD_NO_CSUM		0xa0000000
+
+#define MCD_FUNC_NOEU1		(MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
+				 MCD_NO_CSUM)
+#define MCD_FUNC_NOEU2		(MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
+
+/* Constants for the flags parameter */
+#define MCD_TT_FLAGS_RL		0x00000001	/* Read line */
+#define MCD_TT_FLAGS_CW		0x00000002	/* Combine Writes */
+#define MCD_TT_FLAGS_SP		0x00000004	/* MCF547x/548x ONLY  */
+#define MCD_TT_FLAGS_MASK	0x000000ff
+#define MCD_TT_FLAGS_DEF	(MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
+
+#define MCD_SINGLE_DMA		0x00000100	/* Unchained DMA */
+#define MCD_CHAIN_DMA		/* TBD */
+#define MCD_EU_DMA		/* TBD */
+#define MCD_FECTX_DMA		0x00001000	/* FEC TX ring DMA */
+#define MCD_FECRX_DMA		0x00002000	/* FEC RX ring DMA */
+
+/* these flags are valid for MCD_startDma and the chained buffer descriptors */
+/*
+ * MCD_BUF_READY	- indicates that this buf is now under the DMA's ctrl
+ * MCD_WRAP		- to tell the FEC Dmas to wrap to the first BD
+ * MCD_INTERRUPT	- to generate an interrupt after completion of the DMA
+ * MCD_END_FRAME	- tell the DMA to end the frame when transferring
+ *			  last byte of data in buffer
+ * MCD_CRC_RESTART	- to empty out the accumulated checksum prior to
+ *			  performing the DMA
+ */
+#define MCD_BUF_READY		0x80000000
+#define MCD_WRAP		0x20000000
+#define MCD_INTERRUPT		0x10000000
+#define MCD_END_FRAME		0x08000000
+#define MCD_CRC_RESTART		0x40000000
+
+/* Defines for the FEC buffer descriptor control/status word*/
+#define MCD_FEC_BUF_READY	0x8000
+#define MCD_FEC_WRAP		0x2000
+#define MCD_FEC_INTERRUPT	0x1000
+#define MCD_FEC_END_FRAME	0x0800
+
+/* Defines for general intuitiveness */
+
+#define MCD_TRUE		1
+#define MCD_FALSE		0
+
+/* Three different cases for destination and source. */
+#define MINUS1			-1
+#define ZERO			0
+#define PLUS1			1
+
+#ifndef DEFINESONLY
+
+/* Task Table Entry struct*/
+typedef struct {
+	u32 TDTstart;		/* task descriptor table start */
+	u32 TDTend;		/* task descriptor table end */
+	u32 varTab;		/* variable table start */
+	u32 FDTandFlags;	/* function descriptor table start & flags */
+	volatile u32 descAddrAndStatus;
+	volatile u32 modifiedVarTab;
+	u32 contextSaveSpace;	/* context save space start */
+	u32 literalBases;
+} TaskTableEntry;
+
+/* Chained buffer descriptor:
+ * flags	- flags describing the DMA
+ * csumResult	- checksum performed since last checksum reset
+ * srcAddr	- the address to move data from
+ * destAddr	- the address to move data to
+ * lastDestAddr	- the last address written to
+ * dmaSize	- the no of bytes to xfer independent of the xfer sz
+ * next		- next buffer descriptor in chain
+ * info		- private info about this descriptor;  DMA does not affect it
+ */
+typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
+struct MCD_bufDesc_struct {
+	u32 flags;
+	u32 csumResult;
+	s8 *srcAddr;
+	s8 *destAddr;
+	s8 *lastDestAddr;
+	u32 dmaSize;
+	MCD_bufDesc *next;
+	u32 info;
+};
+
+/* Progress Query struct:
+ * lastSrcAddr	- the most-recent or last, post-increment source address
+ * lastDestAddr	- the most-recent or last, post-increment destination address
+ * dmaSize	- the amount of data transferred for the current buffer
+ * currBufDesc	- pointer to the current buffer descriptor being DMAed
+ */
+
+typedef volatile struct MCD_XferProg_struct {
+	s8 *lastSrcAddr;
+	s8 *lastDestAddr;
+	u32 dmaSize;
+	MCD_bufDesc *currBufDesc;
+} MCD_XferProg;
+
+/* FEC buffer descriptor */
+typedef volatile struct MCD_bufDescFec_struct {
+	u16 statCtrl;
+	u16 length;
+	u32 dataPointer;
+} MCD_bufDescFec;
+
+/*************************************************************************/
+/* API function Prototypes  - see MCD_dmaApi.c for further notes */
+
+/* MCD_startDma starts a particular kind of DMA:
+ * srcAddr	- the channel on which to run the DMA
+ * srcIncr	- the address to move data from, or buffer-descriptor address
+ * destAddr	- the amount to increment the source address per transfer
+ * destIncr	- the address to move data to
+ * dmaSize	- the amount to increment the destination address per transfer
+ * xferSize	- the number bytes in of each data movement (1, 2, or 4)
+ * initiator	- what device initiates the DMA
+ * priority	- priority of the DMA
+ * flags	- flags describing the DMA
+ * funcDesc	- description of byte swapping, bit swapping, and CRC actions
+ */
+int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
+		 s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
+		 int priority, u32 flags, u32 funcDesc);
+
+/*
+ * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
+ * registers, relocating and creating the appropriate task structures, and
+ * setting up some global settings
+ */
+int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
+
+/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
+int MCD_dmaStatus(int channel);
+
+/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
+int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
+
+/*
+ * MCD_killDma() halts the DMA on the requested channel, without any
+ * intention of resuming the DMA.
+ */
+int MCD_killDma(int channel);
+
+/*
+ * MCD_continDma() continues a DMA which as stopped due to encountering an
+ * unready buffer descriptor.
+ */
+int MCD_continDma(int channel);
+
+/*
+ * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
+ * running on that channel).
+ */
+int MCD_pauseDma(int channel);
+
+/*
+ * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
+ * running on that channel).
+ */
+int MCD_resumeDma(int channel);
+
+/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
+int MCD_csumQuery(int channel, u32 * csum);
+
+/*
+ * MCD_getCodeSize provides the packed size required by the microcoded task
+ * and structures.
+ */
+int MCD_getCodeSize(void);
+
+/*
+ * MCD_getVersion provides a pointer to a version string and returns a
+ * version number.
+ */
+int MCD_getVersion(char **longVersion);
+
+/* macro for setting a location in the variable table */
+#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
+/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
+   so I'm avoiding surrounding it with "do {} while(0)" */
+
+#endif				/* DEFINESONLY */
+
+#endif				/* _MCD_API_H */
diff --git a/include/MCD_progCheck.h b/include/MCD_progCheck.h
new file mode 100644
index 0000000..1ec8fbf
--- /dev/null
+++ b/include/MCD_progCheck.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ */
+
+ /* This file is autogenerated. Do not change */
+#define CURRBD		4
+#define DCOUNT		6
+#define DESTPTR		5
+#define SRCPTR		7
diff --git a/include/MCD_tasksInit.h b/include/MCD_tasksInit.h
new file mode 100644
index 0000000..9f582be
--- /dev/null
+++ b/include/MCD_tasksInit.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ */
+
+#ifndef MCD_TSK_INIT_H
+#define MCD_TSK_INIT_H 1
+
+/*
+ * Do not edit!
+ */
+
+/* Task 0 */
+void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
+			   int xferSize, short xferSizeIncr, int *cSave,
+			   volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 1 */
+void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
+			    short destIncr, int dmaSize, short xferSizeIncr,
+			    int flags, int *currBD, int *cSave,
+			    volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 2 */
+void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
+			 int xferSize, short xferSizeIncr, int *cSave,
+			 volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 3 */
+void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
+			  short destIncr, int dmaSize, short xferSizeIncr,
+			  int flags, int *currBD, int *cSave,
+			  volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 4 */
+void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
+			 volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 5 */
+void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
+			  volatile TaskTableEntry * taskTable, int channel);
+
+#endif				/* MCD_TSK_INIT_H */
diff --git a/include/SA-1100.h b/include/SA-1100.h
new file mode 100644
index 0000000..7589df2
--- /dev/null
+++ b/include/SA-1100.h
@@ -0,0 +1,2833 @@
+/*
+ *	FILE		SA-1100.h
+ *
+ *	Version		1.2
+ *	Author		Copyright (c) Marc A. Viredaz, 1998
+ *			DEC Western Research Laboratory, Palo Alto, CA
+ *	Date		January 1998 (April 1997)
+ *	System		StrongARM SA-1100
+ *	Language	C or ARM Assembly
+ *	Purpose		Definition of constants related to the StrongARM
+ *			SA-1100 microprocessor (Advanced RISC Machine (ARM)
+ *			architecture version 4). This file is based on the
+ *			StrongARM SA-1100 data sheet version 2.2.
+ *
+ *			Language-specific definitions are selected by the
+ *			macro "LANGUAGE", which should be defined as either
+ *			"C" (default) or "Assembly".
+ */
+
+
+#ifndef LANGUAGE
+# ifdef __ASSEMBLY__
+#  define LANGUAGE Assembly
+# else
+#  define LANGUAGE C
+# endif
+#endif
+
+#ifndef io_p2v
+#define io_p2v(PhAdd)	(PhAdd)
+#endif
+
+#include <asm/arch-sa1100/bitfield.h>
+
+#define C		0
+#define Assembly	1
+
+
+#if LANGUAGE == C
+typedef unsigned short	Word16 ;
+typedef unsigned int	Word32 ;
+typedef Word32		Word ;
+typedef Word		Quad [4] ;
+typedef void		*Address ;
+typedef void		(*ExcpHndlr) (void) ;
+#endif /* LANGUAGE == C */
+
+
+/*
+ * Memory
+ */
+
+#define MemBnkSp	0x08000000	/* Memory Bank Space [byte]	   */
+
+#define StMemBnkSp	MemBnkSp	/* Static Memory Bank Space [byte] */
+#define StMemBnk0Sp	StMemBnkSp	/* Static Memory Bank 0 Space	   */
+					/* [byte]			   */
+#define StMemBnk1Sp	StMemBnkSp	/* Static Memory Bank 1 Space	   */
+					/* [byte]			   */
+#define StMemBnk2Sp	StMemBnkSp	/* Static Memory Bank 2 Space	   */
+					/* [byte]			   */
+#define StMemBnk3Sp	StMemBnkSp	/* Static Memory Bank 3 Space	   */
+					/* [byte]			   */
+
+#define DRAMBnkSp	MemBnkSp	/* DRAM Bank Space [byte]	   */
+#define DRAMBnk0Sp	DRAMBnkSp	/* DRAM Bank 0 Space [byte]	   */
+#define DRAMBnk1Sp	DRAMBnkSp	/* DRAM Bank 1 Space [byte]	   */
+#define DRAMBnk2Sp	DRAMBnkSp	/* DRAM Bank 2 Space [byte]	   */
+#define DRAMBnk3Sp	DRAMBnkSp	/* DRAM Bank 3 Space [byte]	   */
+
+#define ZeroMemSp	MemBnkSp	/* Zero Memory bank Space [byte]   */
+
+#define _StMemBnk(Nb)			/* Static Memory Bank [0..3]	   */ \
+			(0x00000000 + (Nb)*StMemBnkSp)
+#define _StMemBnk0	_StMemBnk (0)	/* Static Memory Bank 0		   */
+#define _StMemBnk1	_StMemBnk (1)	/* Static Memory Bank 1		   */
+#define _StMemBnk2	_StMemBnk (2)	/* Static Memory Bank 2		   */
+#define _StMemBnk3	_StMemBnk (3)	/* Static Memory Bank 3		   */
+
+#if LANGUAGE == C
+typedef Quad		StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
+#define StMemBnk			/* Static Memory Bank [0..3]	   */ \
+			((StMemBnkType *) io_p2v (_StMemBnk (0)))
+#define StMemBnk0	(StMemBnk [0])	/* Static Memory Bank 0		   */
+#define StMemBnk1	(StMemBnk [1])	/* Static Memory Bank 1		   */
+#define StMemBnk2	(StMemBnk [2])	/* Static Memory Bank 2		   */
+#define StMemBnk3	(StMemBnk [3])	/* Static Memory Bank 3		   */
+#endif /* LANGUAGE == C */
+
+#define _DRAMBnk(Nb)			/* DRAM Bank [0..3]		   */ \
+			(0xC0000000 + (Nb)*DRAMBnkSp)
+#define _DRAMBnk0	_DRAMBnk (0)	/* DRAM Bank 0			   */
+#define _DRAMBnk1	_DRAMBnk (1)	/* DRAM Bank 1			   */
+#define _DRAMBnk2	_DRAMBnk (2)	/* DRAM Bank 2			   */
+#define _DRAMBnk3	_DRAMBnk (3)	/* DRAM Bank 3			   */
+
+#if LANGUAGE == C
+typedef Quad		DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
+#define DRAMBnk				/* DRAM Bank [0..3]		   */ \
+			((DRAMBnkType *) io_p2v (_DRAMBnk (0)))
+#define DRAMBnk0	(DRAMBnk [0])	/* DRAM Bank 0			   */
+#define DRAMBnk1	(DRAMBnk [1])	/* DRAM Bank 1			   */
+#define DRAMBnk2	(DRAMBnk [2])	/* DRAM Bank 2			   */
+#define DRAMBnk3	(DRAMBnk [3])	/* DRAM Bank 3			   */
+#endif /* LANGUAGE == C */
+
+#define _ZeroMem	0xE0000000	/* Zero Memory bank		   */
+
+#if LANGUAGE == C
+typedef Quad		ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
+#define ZeroMem				/* Zero Memory bank		   */ \
+			(*((ZeroMemType *) io_p2v (_ZeroMem)))
+#endif /* LANGUAGE == C */
+
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) sockets
+ */
+
+#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
+#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]		   */
+#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]	   */
+#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
+#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]	   */
+
+#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]	   */
+#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]	   */
+#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
+#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */
+
+#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]	   */
+#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]	   */
+#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
+#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */
+
+#define _PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
+			(0x20000000 + (Nb)*PCMCIASp)
+#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]		   */
+#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]	   */ \
+			(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
+#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]		   */ \
+			(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
+
+#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0			   */
+#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O			   */
+#define _PCMCIA0Attr	_PCMCIAAttr (0)	/* PCMCIA 0 Attribute		   */
+#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory		   */
+
+#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1			   */
+#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O			   */
+#define _PCMCIA1Attr	_PCMCIAAttr (1)	/* PCMCIA 1 Attribute		   */
+#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory		   */
+
+#if LANGUAGE == C
+
+typedef Quad		PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
+typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
+
+#define PCMCIA0				/* PCMCIA 0			   */ \
+			(*((PCMCIAType *) io_p2v (_PCMCIA0)))
+#define PCMCIA0IO			/* PCMCIA 0 I/O			   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO)))
+#define PCMCIA0Attr			/* PCMCIA 0 Attribute		   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr)))
+#define PCMCIA0Mem			/* PCMCIA 0 Memory		   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem)))
+
+#define PCMCIA1				/* PCMCIA 1			   */ \
+			(*((PCMCIAType *) io_p2v (_PCMCIA1)))
+#define PCMCIA1IO			/* PCMCIA 1 I/O			   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO)))
+#define PCMCIA1Attr			/* PCMCIA 1 Attribute		   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr)))
+#define PCMCIA1Mem			/* PCMCIA 1 Memory		   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem)))
+
+#endif /* LANGUAGE == C */
+
+
+/*
+ * Universal Serial Bus (USB) Device Controller (UDC) control registers
+ *
+ * Registers
+ *    Ser0UDCCR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Control Register (read/write).
+ *    Ser0UDCAR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Address Register (read/write).
+ *    Ser0UDCOMP	Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Output Maximum Packet size register
+ *			(read/write).
+ *    Ser0UDCIMP	Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Input Maximum Packet size register
+ *			(read/write).
+ *    Ser0UDCCS0	Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Control/Status register end-point 0
+ *			(read/write).
+ *    Ser0UDCCS1	Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Control/Status register end-point 1
+ *			(output, read/write).
+ *    Ser0UDCCS2	Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Control/Status register end-point 2
+ *			(input, read/write).
+ *    Ser0UDCD0		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Data register end-point 0
+ *			(read/write).
+ *    Ser0UDCWC		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Write Count register end-point 0
+ *			(read).
+ *    Ser0UDCDR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Data Register (read/write).
+ *    Ser0UDCSR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Status Register (read/write).
+ */
+
+#define _Ser0UDCCR	0x80000000	/* Ser. port 0 UDC Control Reg.    */
+#define _Ser0UDCAR	0x80000004	/* Ser. port 0 UDC Address Reg.    */
+#define _Ser0UDCOMP	0x80000008	/* Ser. port 0 UDC Output Maximum  */
+					/* Packet size reg.		   */
+#define _Ser0UDCIMP	0x8000000C	/* Ser. port 0 UDC Input Maximum   */
+					/* Packet size reg.		   */
+#define _Ser0UDCCS0	0x80000010	/* Ser. port 0 UDC Control/Status  */
+					/* reg. end-point 0		   */
+#define _Ser0UDCCS1	0x80000014	/* Ser. port 0 UDC Control/Status  */
+					/* reg. end-point 1 (output)	   */
+#define _Ser0UDCCS2	0x80000018	/* Ser. port 0 UDC Control/Status  */
+					/* reg. end-point 2 (input)	   */
+#define _Ser0UDCD0	0x8000001C	/* Ser. port 0 UDC Data reg.	   */
+					/* end-point 0			   */
+#define _Ser0UDCWC	0x80000020	/* Ser. port 0 UDC Write Count	   */
+					/* reg. end-point 0		   */
+#define _Ser0UDCDR	0x80000028	/* Ser. port 0 UDC Data Reg.	   */
+#define _Ser0UDCSR	0x80000030	/* Ser. port 0 UDC Status Reg.	   */
+
+#if LANGUAGE == C
+#define Ser0UDCCR			/* Ser. port 0 UDC Control Reg.    */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCR)))
+#define Ser0UDCAR			/* Ser. port 0 UDC Address Reg.    */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCAR)))
+#define Ser0UDCOMP			/* Ser. port 0 UDC Output Maximum  */ \
+					/* Packet size reg.		   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCOMP)))
+#define Ser0UDCIMP			/* Ser. port 0 UDC Input Maximum   */ \
+					/* Packet size reg.		   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCIMP)))
+#define Ser0UDCCS0			/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 0		   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCS0)))
+#define Ser0UDCCS1			/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 1 (output)	   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCS1)))
+#define Ser0UDCCS2			/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 2 (input)	   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCS2)))
+#define Ser0UDCD0			/* Ser. port 0 UDC Data reg.	   */ \
+					/* end-point 0			   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCD0)))
+#define Ser0UDCWC			/* Ser. port 0 UDC Write Count	   */ \
+					/* reg. end-point 0		   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCWC)))
+#define Ser0UDCDR			/* Ser. port 0 UDC Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCDR)))
+#define Ser0UDCSR			/* Ser. port 0 UDC Status Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCSR)))
+#endif /* LANGUAGE == C */
+
+#define UDCCR_UDD	0x00000001	/* UDC Disable			   */
+#define UDCCR_UDA	0x00000002	/* UDC Active (read)		   */
+#define UDCCR_RESIM	0x00000004	/* Resume Interrupt Mask, per errata */
+#define UDCCR_EIM	0x00000008	/* End-point 0 Interrupt Mask	   */
+					/* (disable)			   */
+#define UDCCR_RIM	0x00000010	/* Receive Interrupt Mask	   */
+					/* (disable)			   */
+#define UDCCR_TIM	0x00000020	/* Transmit Interrupt Mask	   */
+					/* (disable)			   */
+#define UDCCR_SRM	0x00000040	/* Suspend/Resume interrupt Mask   */
+					/* (disable)			   */
+#define UDCCR_SUSIM	UDCCR_SRM	/* Per errata, SRM just masks suspend */
+#define UDCCR_REM	0x00000080	/* REset interrupt Mask (disable)  */
+
+#define UDCAR_ADD	Fld (7, 0)	/* function ADDress		   */
+
+#define UDCOMP_OUTMAXP	Fld (8, 0)	/* OUTput MAXimum Packet size - 1  */
+					/* [byte]			   */
+#define UDCOMP_OutMaxPkt(Size)		/* Output Maximum Packet size	   */ \
+					/* [1..256 byte]		   */ \
+			(((Size) - 1) << FShft (UDCOMP_OUTMAXP))
+
+#define UDCIMP_INMAXP	Fld (8, 0)	/* INput MAXimum Packet size - 1   */
+					/* [byte]			   */
+#define UDCIMP_InMaxPkt(Size)		/* Input Maximum Packet size	   */ \
+					/* [1..256 byte]		   */ \
+			(((Size) - 1) << FShft (UDCIMP_INMAXP))
+
+#define UDCCS0_OPR	0x00000001	/* Output Packet Ready (read)	   */
+#define UDCCS0_IPR	0x00000002	/* Input Packet Ready		   */
+#define UDCCS0_SST	0x00000004	/* Sent STall			   */
+#define UDCCS0_FST	0x00000008	/* Force STall			   */
+#define UDCCS0_DE	0x00000010	/* Data End			   */
+#define UDCCS0_SE	0x00000020	/* Setup End (read)		   */
+#define UDCCS0_SO	0x00000040	/* Serviced Output packet ready    */
+					/* (write)			   */
+#define UDCCS0_SSE	0x00000080	/* Serviced Setup End (write)	   */
+
+#define UDCCS1_RFS	0x00000001	/* Receive FIFO 12-bytes or more   */
+					/* Service request (read)	   */
+#define UDCCS1_RPC	0x00000002	/* Receive Packet Complete	   */
+#define UDCCS1_RPE	0x00000004	/* Receive Packet Error (read)	   */
+#define UDCCS1_SST	0x00000008	/* Sent STall			   */
+#define UDCCS1_FST	0x00000010	/* Force STall			   */
+#define UDCCS1_RNE	0x00000020	/* Receive FIFO Not Empty (read)   */
+
+#define UDCCS2_TFS	0x00000001	/* Transmit FIFO 8-bytes or less   */
+					/* Service request (read)	   */
+#define UDCCS2_TPC	0x00000002	/* Transmit Packet Complete	   */
+#define UDCCS2_TPE	0x00000004	/* Transmit Packet Error (read)    */
+#define UDCCS2_TUR	0x00000008	/* Transmit FIFO Under-Run	   */
+#define UDCCS2_SST	0x00000010	/* Sent STall			   */
+#define UDCCS2_FST	0x00000020	/* Force STall			   */
+
+#define UDCD0_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+
+#define UDCWC_WC	Fld (4, 0)	/* Write Count			   */
+
+#define UDCDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+
+#define UDCSR_EIR	0x00000001	/* End-point 0 Interrupt Request   */
+#define UDCSR_RIR	0x00000002	/* Receive Interrupt Request	   */
+#define UDCSR_TIR	0x00000004	/* Transmit Interrupt Request	   */
+#define UDCSR_SUSIR	0x00000008	/* SUSpend Interrupt Request	   */
+#define UDCSR_RESIR	0x00000010	/* RESume Interrupt Request	   */
+#define UDCSR_RSTIR	0x00000020	/* ReSeT Interrupt Request	   */
+
+
+/*
+ * Universal Asynchronous Receiver/Transmitter (UART) control registers
+ *
+ * Registers
+ *    Ser1UTCR0		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 0
+ *			(read/write).
+ *    Ser1UTCR1		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 1
+ *			(read/write).
+ *    Ser1UTCR2		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 2
+ *			(read/write).
+ *    Ser1UTCR3		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 3
+ *			(read/write).
+ *    Ser1UTDR		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Data Register
+ *			(read/write).
+ *    Ser1UTSR0		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 0
+ *			(read/write).
+ *    Ser1UTSR1		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ *    Ser2UTCR0		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 0
+ *			(read/write).
+ *    Ser2UTCR1		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 1
+ *			(read/write).
+ *    Ser2UTCR2		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 2
+ *			(read/write).
+ *    Ser2UTCR3		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 3
+ *			(read/write).
+ *    Ser2UTCR4		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 4
+ *			(read/write).
+ *    Ser2UTDR		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Data Register
+ *			(read/write).
+ *    Ser2UTSR0		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 0
+ *			(read/write).
+ *    Ser2UTSR1		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ *    Ser3UTCR0		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 0
+ *			(read/write).
+ *    Ser3UTCR1		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 1
+ *			(read/write).
+ *    Ser3UTCR2		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 2
+ *			(read/write).
+ *    Ser3UTCR3		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 3
+ *			(read/write).
+ *    Ser3UTDR		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Data Register
+ *			(read/write).
+ *    Ser3UTSR0		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 0
+ *			(read/write).
+ *    Ser3UTSR1		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *			or 3.5795 MHz).
+ *    fua, Tua		Frequency, period of the UART communication.
+ */
+
+#define _UTCR0(Nb)			/* UART Control Reg. 0 [1..3]	   */ \
+			(0x80010000 + ((Nb) - 1)*0x00020000)
+#define _UTCR1(Nb)			/* UART Control Reg. 1 [1..3]	   */ \
+			(0x80010004 + ((Nb) - 1)*0x00020000)
+#define _UTCR2(Nb)			/* UART Control Reg. 2 [1..3]	   */ \
+			(0x80010008 + ((Nb) - 1)*0x00020000)
+#define _UTCR3(Nb)			/* UART Control Reg. 3 [1..3]	   */ \
+			(0x8001000C + ((Nb) - 1)*0x00020000)
+#define _UTCR4(Nb)			/* UART Control Reg. 4 [2]	   */ \
+			(0x80010010 + ((Nb) - 1)*0x00020000)
+#define _UTDR(Nb)			/* UART Data Reg. [1..3]	   */ \
+			(0x80010014 + ((Nb) - 1)*0x00020000)
+#define _UTSR0(Nb)			/* UART Status Reg. 0 [1..3]	   */ \
+			(0x8001001C + ((Nb) - 1)*0x00020000)
+#define _UTSR1(Nb)			/* UART Status Reg. 1 [1..3]	   */ \
+			(0x80010020 + ((Nb) - 1)*0x00020000)
+
+#define _Ser1UTCR0	_UTCR0 (1)	/* Ser. port 1 UART Control Reg. 0 */
+#define _Ser1UTCR1	_UTCR1 (1)	/* Ser. port 1 UART Control Reg. 1 */
+#define _Ser1UTCR2	_UTCR2 (1)	/* Ser. port 1 UART Control Reg. 2 */
+#define _Ser1UTCR3	_UTCR3 (1)	/* Ser. port 1 UART Control Reg. 3 */
+#define _Ser1UTDR	_UTDR (1)	/* Ser. port 1 UART Data Reg.	   */
+#define _Ser1UTSR0	_UTSR0 (1)	/* Ser. port 1 UART Status Reg. 0  */
+#define _Ser1UTSR1	_UTSR1 (1)	/* Ser. port 1 UART Status Reg. 1  */
+
+#define _Ser2UTCR0	_UTCR0 (2)	/* Ser. port 2 UART Control Reg. 0 */
+#define _Ser2UTCR1	_UTCR1 (2)	/* Ser. port 2 UART Control Reg. 1 */
+#define _Ser2UTCR2	_UTCR2 (2)	/* Ser. port 2 UART Control Reg. 2 */
+#define _Ser2UTCR3	_UTCR3 (2)	/* Ser. port 2 UART Control Reg. 3 */
+#define _Ser2UTCR4	_UTCR4 (2)	/* Ser. port 2 UART Control Reg. 4 */
+#define _Ser2UTDR	_UTDR (2)	/* Ser. port 2 UART Data Reg.	   */
+#define _Ser2UTSR0	_UTSR0 (2)	/* Ser. port 2 UART Status Reg. 0  */
+#define _Ser2UTSR1	_UTSR1 (2)	/* Ser. port 2 UART Status Reg. 1  */
+
+#define _Ser3UTCR0	_UTCR0 (3)	/* Ser. port 3 UART Control Reg. 0 */
+#define _Ser3UTCR1	_UTCR1 (3)	/* Ser. port 3 UART Control Reg. 1 */
+#define _Ser3UTCR2	_UTCR2 (3)	/* Ser. port 3 UART Control Reg. 2 */
+#define _Ser3UTCR3	_UTCR3 (3)	/* Ser. port 3 UART Control Reg. 3 */
+#define _Ser3UTDR	_UTDR (3)	/* Ser. port 3 UART Data Reg.	   */
+#define _Ser3UTSR0	_UTSR0 (3)	/* Ser. port 3 UART Status Reg. 0  */
+#define _Ser3UTSR1	_UTSR1 (3)	/* Ser. port 3 UART Status Reg. 1  */
+
+#if LANGUAGE == C
+
+#define Ser1UTCR0			/* Ser. port 1 UART Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR0)))
+#define Ser1UTCR1			/* Ser. port 1 UART Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR1)))
+#define Ser1UTCR2			/* Ser. port 1 UART Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR2)))
+#define Ser1UTCR3			/* Ser. port 1 UART Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR3)))
+#define Ser1UTDR			/* Ser. port 1 UART Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser1UTDR)))
+#define Ser1UTSR0			/* Ser. port 1 UART Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser1UTSR0)))
+#define Ser1UTSR1			/* Ser. port 1 UART Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser1UTSR1)))
+
+#define Ser2UTCR0			/* Ser. port 2 UART Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR0)))
+#define Ser2UTCR1			/* Ser. port 2 UART Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR1)))
+#define Ser2UTCR2			/* Ser. port 2 UART Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR2)))
+#define Ser2UTCR3			/* Ser. port 2 UART Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR3)))
+#define Ser2UTCR4			/* Ser. port 2 UART Control Reg. 4 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR4)))
+#define Ser2UTDR			/* Ser. port 2 UART Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser2UTDR)))
+#define Ser2UTSR0			/* Ser. port 2 UART Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser2UTSR0)))
+#define Ser2UTSR1			/* Ser. port 2 UART Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser2UTSR1)))
+
+#define Ser3UTCR0			/* Ser. port 3 UART Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR0)))
+#define Ser3UTCR1			/* Ser. port 3 UART Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR1)))
+#define Ser3UTCR2			/* Ser. port 3 UART Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR2)))
+#define Ser3UTCR3			/* Ser. port 3 UART Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR3)))
+#define Ser3UTDR			/* Ser. port 3 UART Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser3UTDR)))
+#define Ser3UTSR0			/* Ser. port 3 UART Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser3UTSR0)))
+#define Ser3UTSR1			/* Ser. port 3 UART Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser3UTSR1)))
+
+#elif LANGUAGE == Assembly
+#define Ser1UTCR0	( io_p2v (_Ser1UTCR0))
+#define Ser1UTCR1	( io_p2v (_Ser1UTCR1))
+#define Ser1UTCR2	( io_p2v (_Ser1UTCR2))
+#define Ser1UTCR3	( io_p2v (_Ser1UTCR3))
+#define Ser1UTDR	( io_p2v (_Ser1UTDR))
+#define Ser1UTSR0	( io_p2v (_Ser1UTSR0))
+#define Ser1UTSR1	( io_p2v (_Ser1UTSR1))
+
+#define Ser2UTCR0	( io_p2v (_Ser2UTCR0))
+#define Ser2UTCR1	( io_p2v (_Ser2UTCR1))
+#define Ser2UTCR2	( io_p2v (_Ser2UTCR2))
+#define Ser2UTCR3	( io_p2v (_Ser2UTCR3))
+#define Ser2UTCR4	( io_p2v (_Ser2UTCR4))
+#define Ser2UTDR	( io_p2v (_Ser2UTDR))
+#define Ser2UTSR0	( io_p2v (_Ser2UTSR0))
+#define Ser2UTSR1	( io_p2v (_Ser2UTSR1))
+
+#define Ser3UTCR0	( io_p2v (_Ser3UTCR0))
+#define Ser3UTCR1	( io_p2v (_Ser3UTCR1))
+#define Ser3UTCR2	( io_p2v (_Ser3UTCR2))
+#define Ser3UTCR3	( io_p2v (_Ser3UTCR3))
+#define Ser3UTDR	( io_p2v (_Ser3UTDR))
+#define Ser3UTSR0	( io_p2v (_Ser3UTSR0))
+#define Ser3UTSR1	( io_p2v (_Ser3UTSR1))
+
+#endif /* LANGUAGE == C */
+
+#define UTCR0_PE	0x00000001	/* Parity Enable		   */
+#define UTCR0_OES	0x00000002	/* Odd/Even parity Select	   */
+#define UTCR0_OddPar	(UTCR0_OES*0)	/*  Odd Parity			   */
+#define UTCR0_EvenPar	(UTCR0_OES*1)	/*  Even Parity			   */
+#define UTCR0_SBS	0x00000004	/* Stop Bit Select		   */
+#define UTCR0_1StpBit	(UTCR0_SBS*0)	/*  1 Stop Bit per frame	   */
+#define UTCR0_2StpBit	(UTCR0_SBS*1)	/*  2 Stop Bits per frame	   */
+#define UTCR0_DSS	0x00000008	/* Data Size Select		   */
+#define UTCR0_7BitData	(UTCR0_DSS*0)	/*  7-Bit Data			   */
+#define UTCR0_8BitData	(UTCR0_DSS*1)	/*  8-Bit Data			   */
+#define UTCR0_SCE	0x00000010	/* Sample Clock Enable		   */
+					/* (ser. port 1: GPIO [18],	   */
+					/* ser. port 3: GPIO [20])	   */
+#define UTCR0_RCE	0x00000020	/* Receive Clock Edge select	   */
+#define UTCR0_RcRsEdg	(UTCR0_RCE*0)	/*  Receive clock Rising-Edge	   */
+#define UTCR0_RcFlEdg	(UTCR0_RCE*1)	/*  Receive clock Falling-Edge	   */
+#define UTCR0_TCE	0x00000040	/* Transmit Clock Edge select	   */
+#define UTCR0_TrRsEdg	(UTCR0_TCE*0)	/*  Transmit clock Rising-Edge	   */
+#define UTCR0_TrFlEdg	(UTCR0_TCE*1)	/*  Transmit clock Falling-Edge    */
+#define UTCR0_Ser2IrDA			/* Ser. port 2 IrDA settings	   */ \
+			(UTCR0_1StpBit + UTCR0_8BitData)
+
+#define UTCR1_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
+#define UTCR2_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
+					/* fua = fxtl/(16*(BRD[11:0] + 1)) */
+					/* Tua = 16*(BRD [11:0] + 1)*Txtl  */
+#define UTCR1_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
+			 FShft (UTCR1_BRD))
+#define UTCR2_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
+			 FShft (UTCR2_BRD))
+					/*  fua = fxtl/(16*Floor (Div/16)) */
+					/*  Tua = 16*Floor (Div/16)*Txtl   */
+#define UTCR1_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
+			 FShft (UTCR1_BRD))
+#define UTCR2_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
+			 FShft (UTCR2_BRD))
+					/*  fua = fxtl/(16*Ceil (Div/16))  */
+					/*  Tua = 16*Ceil (Div/16)*Txtl    */
+
+#define UTCR3_RXE	0x00000001	/* Receive Enable		   */
+#define UTCR3_TXE	0x00000002	/* Transmit Enable		   */
+#define UTCR3_BRK	0x00000004	/* BReaK mode			   */
+#define UTCR3_RIE	0x00000008	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Interrupt Enable	   */
+#define UTCR3_TIE	0x00000010	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable		   */
+#define UTCR3_LBM	0x00000020	/* Look-Back Mode		   */
+#define UTCR3_Ser2IrDA			/* Ser. port 2 IrDA settings (RIE, */ \
+					/* TIE, LBM can be set or cleared) */ \
+			(UTCR3_RXE + UTCR3_TXE)
+
+#define UTCR4_HSE	0x00000001	/* Hewlett-Packard Serial InfraRed */
+					/* (HP-SIR) modulation Enable	   */
+#define UTCR4_NRZ	(UTCR4_HSE*0)	/*  Non-Return to Zero modulation  */
+#define UTCR4_HPSIR	(UTCR4_HSE*1)	/*  HP-SIR modulation		   */
+#define UTCR4_LPM	0x00000002	/* Low-Power Mode		   */
+#define UTCR4_Z3_16Bit	(UTCR4_LPM*0)	/*  Zero pulse = 3/16 Bit time	   */
+#define UTCR4_Z1_6us	(UTCR4_LPM*1)	/*  Zero pulse = 1.6 us		   */
+
+#define UTDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+#if 0					/* Hidden receive FIFO bits	   */
+#define UTDR_PRE	0x00000100	/*  receive PaRity Error (read)    */
+#define UTDR_FRE	0x00000200	/*  receive FRaming Error (read)   */
+#define UTDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define UTSR0_TFS	0x00000001	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)	   */
+#define UTSR0_RFS	0x00000002	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Service request (read)	   */
+#define UTSR0_RID	0x00000004	/* Receiver IDle		   */
+#define UTSR0_RBB	0x00000008	/* Receive Beginning of Break	   */
+#define UTSR0_REB	0x00000010	/* Receive End of Break		   */
+#define UTSR0_EIF	0x00000020	/* Error In FIFO (read)		   */
+
+#define UTSR1_TBY	0x00000001	/* Transmitter BusY (read)	   */
+#define UTSR1_RNE	0x00000002	/* Receive FIFO Not Empty (read)   */
+#define UTSR1_TNF	0x00000004	/* Transmit FIFO Not Full (read)   */
+#define UTSR1_PRE	0x00000008	/* receive PaRity Error (read)	   */
+#define UTSR1_FRE	0x00000010	/* receive FRaming Error (read)    */
+#define UTSR1_ROR	0x00000020	/* Receive FIFO Over-Run (read)    */
+
+
+/*
+ * Synchronous Data Link Controller (SDLC) control registers
+ *
+ * Registers
+ *    Ser1SDCR0		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 0 (read/write).
+ *    Ser1SDCR1		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 1 (read/write).
+ *    Ser1SDCR2		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 2 (read/write).
+ *    Ser1SDCR3		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 3 (read/write).
+ *    Ser1SDCR4		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 4 (read/write).
+ *    Ser1SDDR		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Data Register (read/write).
+ *    Ser1SDSR0		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Status Register 0 (read/write).
+ *    Ser1SDSR1		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Status Register 1 (read/write).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *			or 3.5795 MHz).
+ *    fsd, Tsd		Frequency, period of the SDLC communication.
+ */
+
+#define _Ser1SDCR0	0x80020060	/* Ser. port 1 SDLC Control Reg. 0 */
+#define _Ser1SDCR1	0x80020064	/* Ser. port 1 SDLC Control Reg. 1 */
+#define _Ser1SDCR2	0x80020068	/* Ser. port 1 SDLC Control Reg. 2 */
+#define _Ser1SDCR3	0x8002006C	/* Ser. port 1 SDLC Control Reg. 3 */
+#define _Ser1SDCR4	0x80020070	/* Ser. port 1 SDLC Control Reg. 4 */
+#define _Ser1SDDR	0x80020078	/* Ser. port 1 SDLC Data Reg.	   */
+#define _Ser1SDSR0	0x80020080	/* Ser. port 1 SDLC Status Reg. 0  */
+#define _Ser1SDSR1	0x80020084	/* Ser. port 1 SDLC Status Reg. 1  */
+
+#if LANGUAGE == C
+#define Ser1SDCR0			/* Ser. port 1 SDLC Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR0)))
+#define Ser1SDCR1			/* Ser. port 1 SDLC Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR1)))
+#define Ser1SDCR2			/* Ser. port 1 SDLC Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR2)))
+#define Ser1SDCR3			/* Ser. port 1 SDLC Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR3)))
+#define Ser1SDCR4			/* Ser. port 1 SDLC Control Reg. 4 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR4)))
+#define Ser1SDDR			/* Ser. port 1 SDLC Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser1SDDR)))
+#define Ser1SDSR0			/* Ser. port 1 SDLC Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser1SDSR0)))
+#define Ser1SDSR1			/* Ser. port 1 SDLC Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser1SDSR1)))
+#endif /* LANGUAGE == C */
+
+#define SDCR0_SUS	0x00000001	/* SDLC/UART Select		   */
+#define SDCR0_SDLC	(SDCR0_SUS*0)	/*  SDLC mode (TXD1 & RXD1)	   */
+#define SDCR0_UART	(SDCR0_SUS*1)	/*  UART mode (TXD1 & RXD1)	   */
+#define SDCR0_SDF	0x00000002	/* Single/Double start Flag select */
+#define SDCR0_SglFlg	(SDCR0_SDF*0)	/*  Single start Flag		   */
+#define SDCR0_DblFlg	(SDCR0_SDF*1)	/*  Double start Flag		   */
+#define SDCR0_LBM	0x00000004	/* Look-Back Mode		   */
+#define SDCR0_BMS	0x00000008	/* Bit Modulation Select	   */
+#define SDCR0_FM0	(SDCR0_BMS*0)	/*  Freq. Modulation zero (0)	   */
+#define SDCR0_NRZ	(SDCR0_BMS*1)	/*  Non-Return to Zero modulation  */
+#define SDCR0_SCE	0x00000010	/* Sample Clock Enable (GPIO [16]) */
+#define SDCR0_SCD	0x00000020	/* Sample Clock Direction select   */
+					/* (GPIO [16])			   */
+#define SDCR0_SClkIn	(SDCR0_SCD*0)	/*  Sample Clock Input		   */
+#define SDCR0_SClkOut	(SDCR0_SCD*1)	/*  Sample Clock Output		   */
+#define SDCR0_RCE	0x00000040	/* Receive Clock Edge select	   */
+#define SDCR0_RcRsEdg	(SDCR0_RCE*0)	/*  Receive clock Rising-Edge	   */
+#define SDCR0_RcFlEdg	(SDCR0_RCE*1)	/*  Receive clock Falling-Edge	   */
+#define SDCR0_TCE	0x00000080	/* Transmit Clock Edge select	   */
+#define SDCR0_TrRsEdg	(SDCR0_TCE*0)	/*  Transmit clock Rising-Edge	   */
+#define SDCR0_TrFlEdg	(SDCR0_TCE*1)	/*  Transmit clock Falling-Edge    */
+
+#define SDCR1_AAF	0x00000001	/* Abort After Frame enable	   */
+					/* (GPIO [17])			   */
+#define SDCR1_TXE	0x00000002	/* Transmit Enable		   */
+#define SDCR1_RXE	0x00000004	/* Receive Enable		   */
+#define SDCR1_RIE	0x00000008	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Interrupt Enable	   */
+#define SDCR1_TIE	0x00000010	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable		   */
+#define SDCR1_AME	0x00000020	/* Address Match Enable		   */
+#define SDCR1_TUS	0x00000040	/* Transmit FIFO Under-run Select  */
+#define SDCR1_EFrmURn	(SDCR1_TUS*0)	/*  End Frame on Under-Run	   */
+#define SDCR1_AbortURn	(SDCR1_TUS*1)	/*  Abort on Under-Run		   */
+#define SDCR1_RAE	0x00000080	/* Receive Abort interrupt Enable  */
+
+#define SDCR2_AMV	Fld (8, 0)	/* Address Match Value		   */
+
+#define SDCR3_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
+#define SDCR4_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
+					/* fsd = fxtl/(16*(BRD[11:0] + 1)) */
+					/* Tsd = 16*(BRD[11:0] + 1)*Txtl   */
+#define SDCR3_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
+			 FShft (SDCR3_BRD))
+#define SDCR4_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
+			 FShft (SDCR4_BRD))
+					/*  fsd = fxtl/(16*Floor (Div/16)) */
+					/*  Tsd = 16*Floor (Div/16)*Txtl   */
+#define SDCR3_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
+			 FShft (SDCR3_BRD))
+#define SDCR4_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
+			 FShft (SDCR4_BRD))
+					/*  fsd = fxtl/(16*Ceil (Div/16))  */
+					/*  Tsd = 16*Ceil (Div/16)*Txtl    */
+
+#define SDDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+#if 0					/* Hidden receive FIFO bits	   */
+#define SDDR_EOF	0x00000100	/*  receive End-Of-Frame (read)    */
+#define SDDR_CRE	0x00000200	/*  receive CRC Error (read)	   */
+#define SDDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define SDSR0_EIF	0x00000001	/* Error In FIFO (read)		   */
+#define SDSR0_TUR	0x00000002	/* Transmit FIFO Under-Run	   */
+#define SDSR0_RAB	0x00000004	/* Receive ABort		   */
+#define SDSR0_TFS	0x00000008	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)	   */
+#define SDSR0_RFS	0x00000010	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Service request (read)	   */
+
+#define SDSR1_RSY	0x00000001	/* Receiver SYnchronized (read)    */
+#define SDSR1_TBY	0x00000002	/* Transmitter BusY (read)	   */
+#define SDSR1_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
+#define SDSR1_TNF	0x00000008	/* Transmit FIFO Not Full (read)   */
+#define SDSR1_RTD	0x00000010	/* Receive Transition Detected	   */
+#define SDSR1_EOF	0x00000020	/* receive End-Of-Frame (read)	   */
+#define SDSR1_CRE	0x00000040	/* receive CRC Error (read)	   */
+#define SDSR1_ROR	0x00000080	/* Receive FIFO Over-Run (read)    */
+
+
+/*
+ * High-Speed Serial to Parallel controller (HSSP) control registers
+ *
+ * Registers
+ *    Ser2HSCR0		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Control Register 0 (read/write).
+ *    Ser2HSCR1		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Control Register 1 (read/write).
+ *    Ser2HSDR		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Data Register (read/write).
+ *    Ser2HSSR0		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Status Register 0 (read/write).
+ *    Ser2HSSR1		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Status Register 1 (read).
+ *    Ser2HSCR2		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Control Register 2 (read/write).
+ *			[The HSCR2 register is only implemented in
+ *			versions 2.0 (rev. = 8) and higher of the StrongARM
+ *			SA-1100.]
+ */
+
+#define _Ser2HSCR0	0x80040060	/* Ser. port 2 HSSP Control Reg. 0 */
+#define _Ser2HSCR1	0x80040064	/* Ser. port 2 HSSP Control Reg. 1 */
+#define _Ser2HSDR	0x8004006C	/* Ser. port 2 HSSP Data Reg.	   */
+#define _Ser2HSSR0	0x80040074	/* Ser. port 2 HSSP Status Reg. 0  */
+#define _Ser2HSSR1	0x80040078	/* Ser. port 2 HSSP Status Reg. 1  */
+#define _Ser2HSCR2	0x90060028	/* Ser. port 2 HSSP Control Reg. 2 */
+
+#if LANGUAGE == C
+#define Ser2HSCR0			/* Ser. port 2 HSSP Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser2HSCR0)))
+#define Ser2HSCR1			/* Ser. port 2 HSSP Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser2HSCR1)))
+#define Ser2HSDR			/* Ser. port 2 HSSP Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser2HSDR)))
+#define Ser2HSSR0			/* Ser. port 2 HSSP Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser2HSSR0)))
+#define Ser2HSSR1			/* Ser. port 2 HSSP Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser2HSSR1)))
+#define Ser2HSCR2			/* Ser. port 2 HSSP Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser2HSCR2)))
+#endif /* LANGUAGE == C */
+
+#define HSCR0_ITR	0x00000001	/* IrDA Transmission Rate	   */
+#define HSCR0_UART	(HSCR0_ITR*0)	/*  UART mode (115.2 kb/s if IrDA) */
+#define HSCR0_HSSP	(HSCR0_ITR*1)	/*  HSSP mode (4 Mb/s)		   */
+#define HSCR0_LBM	0x00000002	/* Look-Back Mode		   */
+#define HSCR0_TUS	0x00000004	/* Transmit FIFO Under-run Select  */
+#define HSCR0_EFrmURn	(HSCR0_TUS*0)	/*  End Frame on Under-Run	   */
+#define HSCR0_AbortURn	(HSCR0_TUS*1)	/*  Abort on Under-Run		   */
+#define HSCR0_TXE	0x00000008	/* Transmit Enable		   */
+#define HSCR0_RXE	0x00000010	/* Receive Enable		   */
+#define HSCR0_RIE	0x00000020	/* Receive FIFO 2/5-to-3/5-full or */
+					/* more Interrupt Enable	   */
+#define HSCR0_TIE	0x00000040	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable		   */
+#define HSCR0_AME	0x00000080	/* Address Match Enable		   */
+
+#define HSCR1_AMV	Fld (8, 0)	/* Address Match Value		   */
+
+#define HSDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+#if 0					/* Hidden receive FIFO bits	   */
+#define HSDR_EOF	0x00000100	/*  receive End-Of-Frame (read)    */
+#define HSDR_CRE	0x00000200	/*  receive CRC Error (read)	   */
+#define HSDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define HSSR0_EIF	0x00000001	/* Error In FIFO (read)		   */
+#define HSSR0_TUR	0x00000002	/* Transmit FIFO Under-Run	   */
+#define HSSR0_RAB	0x00000004	/* Receive ABort		   */
+#define HSSR0_TFS	0x00000008	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)	   */
+#define HSSR0_RFS	0x00000010	/* Receive FIFO 2/5-to-3/5-full or */
+					/* more Service request (read)	   */
+#define HSSR0_FRE	0x00000020	/* receive FRaming Error	   */
+
+#define HSSR1_RSY	0x00000001	/* Receiver SYnchronized (read)    */
+#define HSSR1_TBY	0x00000002	/* Transmitter BusY (read)	   */
+#define HSSR1_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
+#define HSSR1_TNF	0x00000008	/* Transmit FIFO Not Full (read)   */
+#define HSSR1_EOF	0x00000010	/* receive End-Of-Frame (read)	   */
+#define HSSR1_CRE	0x00000020	/* receive CRC Error (read)	   */
+#define HSSR1_ROR	0x00000040	/* Receive FIFO Over-Run (read)    */
+
+#define HSCR2_TXP	0x00040000	/* Transmit data Polarity (TXD_2)  */
+#define HSCR2_TrDataL	(HSCR2_TXP*0)	/*  Transmit Data active Low	   */
+					/*  (inverted)			   */
+#define HSCR2_TrDataH	(HSCR2_TXP*1)	/*  Transmit Data active High	   */
+					/*  (non-inverted)		   */
+#define HSCR2_RXP	0x00080000	/* Receive data Polarity (RXD_2)   */
+#define HSCR2_RcDataL	(HSCR2_RXP*0)	/*  Receive Data active Low	   */
+					/*  (inverted)			   */
+#define HSCR2_RcDataH	(HSCR2_RXP*1)	/*  Receive Data active High	   */
+					/*  (non-inverted)		   */
+
+
+/*
+ * Multi-media Communications Port (MCP) control registers
+ *
+ * Registers
+ *    Ser4MCCR0		Serial port 4 Multi-media Communications Port (MCP)
+ *			Control Register 0 (read/write).
+ *    Ser4MCDR0		Serial port 4 Multi-media Communications Port (MCP)
+ *			Data Register 0 (audio, read/write).
+ *    Ser4MCDR1		Serial port 4 Multi-media Communications Port (MCP)
+ *			Data Register 1 (telecom, read/write).
+ *    Ser4MCDR2		Serial port 4 Multi-media Communications Port (MCP)
+ *			Data Register 2 (CODEC registers, read/write).
+ *    Ser4MCSR		Serial port 4 Multi-media Communications Port (MCP)
+ *			Status Register (read/write).
+ *    Ser4MCCR1		Serial port 4 Multi-media Communications Port (MCP)
+ *			Control Register 1 (read/write).
+ *			[The MCCR1 register is only implemented in
+ *			versions 2.0 (rev. = 8) and higher of the StrongARM
+ *			SA-1100.]
+ *
+ * Clocks
+ *    fmc, Tmc		Frequency, period of the MCP communication (10 MHz,
+ *			12 MHz, or GPIO [21]).
+ *    faud, Taud	Frequency, period of the audio sampling.
+ *    ftcm, Ttcm	Frequency, period of the telecom sampling.
+ */
+
+#define _Ser4MCCR0	0x80060000	/* Ser. port 4 MCP Control Reg. 0  */
+#define _Ser4MCDR0	0x80060008	/* Ser. port 4 MCP Data Reg. 0	   */
+					/* (audio)			   */
+#define _Ser4MCDR1	0x8006000C	/* Ser. port 4 MCP Data Reg. 1	   */
+					/* (telecom)			   */
+#define _Ser4MCDR2	0x80060010	/* Ser. port 4 MCP Data Reg. 2	   */
+					/* (CODEC reg.)			   */
+#define _Ser4MCSR	0x80060018	/* Ser. port 4 MCP Status Reg.	   */
+#define _Ser4MCCR1	0x90060030	/* Ser. port 4 MCP Control Reg. 1  */
+
+#if LANGUAGE == C
+#define Ser4MCCR0			/* Ser. port 4 MCP Control Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser4MCCR0)))
+#define Ser4MCDR0			/* Ser. port 4 MCP Data Reg. 0	   */ \
+					/* (audio)			   */ \
+			(*((volatile Word *) io_p2v (_Ser4MCDR0)))
+#define Ser4MCDR1			/* Ser. port 4 MCP Data Reg. 1	   */ \
+					/* (telecom)			   */ \
+			(*((volatile Word *) io_p2v (_Ser4MCDR1)))
+#define Ser4MCDR2			/* Ser. port 4 MCP Data Reg. 2	   */ \
+					/* (CODEC reg.)			   */ \
+			(*((volatile Word *) io_p2v (_Ser4MCDR2)))
+#define Ser4MCSR			/* Ser. port 4 MCP Status Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser4MCSR)))
+#define Ser4MCCR1			/* Ser. port 4 MCP Control Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser4MCCR1)))
+#endif /* LANGUAGE == C */
+
+#define MCCR0_ASD	Fld (7, 0)	/* Audio Sampling rate Divisor/32  */
+					/* [6..127]			   */
+					/* faud = fmc/(32*ASD)		   */
+					/* Taud = 32*ASD*Tmc		   */
+#define MCCR0_AudSmpDiv(Div)		/*  Audio Sampling rate Divisor    */ \
+					/*  [192..4064]			   */ \
+			((Div)/32 << FShft (MCCR0_ASD))
+					/*  faud = fmc/(32*Floor (Div/32)) */
+					/*  Taud = 32*Floor (Div/32)*Tmc   */
+#define MCCR0_CeilAudSmpDiv(Div)	/*  Ceil. of AudSmpDiv [192..4064] */ \
+			(((Div) + 31)/32 << FShft (MCCR0_ASD))
+					/*  faud = fmc/(32*Ceil (Div/32))  */
+					/*  Taud = 32*Ceil (Div/32)*Tmc    */
+#define MCCR0_TSD	Fld (7, 8)	/* Telecom Sampling rate	   */
+					/* Divisor/32 [16..127]		   */
+					/* ftcm = fmc/(32*TSD)		   */
+					/* Ttcm = 32*TSD*Tmc		   */
+#define MCCR0_TcmSmpDiv(Div)		/*  Telecom Sampling rate Divisor  */ \
+					/*  [512..4064]			   */ \
+			((Div)/32 << FShft (MCCR0_TSD))
+					/*  ftcm = fmc/(32*Floor (Div/32)) */
+					/*  Ttcm = 32*Floor (Div/32)*Tmc   */
+#define MCCR0_CeilTcmSmpDiv(Div)	/*  Ceil. of TcmSmpDiv [512..4064] */ \
+			(((Div) + 31)/32 << FShft (MCCR0_TSD))
+					/*  ftcm = fmc/(32*Ceil (Div/32))  */
+					/*  Ttcm = 32*Ceil (Div/32)*Tmc    */
+#define MCCR0_MCE	0x00010000	/* MCP Enable			   */
+#define MCCR0_ECS	0x00020000	/* External Clock Select	   */
+#define MCCR0_IntClk	(MCCR0_ECS*0)	/*  Internal Clock (10 or 12 MHz)  */
+#define MCCR0_ExtClk	(MCCR0_ECS*1)	/*  External Clock (GPIO [21])	   */
+#define MCCR0_ADM	0x00040000	/* A/D (audio/telecom) data	   */
+					/* sampling/storing Mode	   */
+#define MCCR0_VldBit	(MCCR0_ADM*0)	/*  Valid Bit storing mode	   */
+#define MCCR0_SmpCnt	(MCCR0_ADM*1)	/*  Sampling Counter storing mode  */
+#define MCCR0_TTE	0x00080000	/* Telecom Transmit FIFO 1/2-full  */
+					/* or less interrupt Enable	   */
+#define MCCR0_TRE	0x00100000	/* Telecom Receive FIFO 1/2-full   */
+					/* or more interrupt Enable	   */
+#define MCCR0_ATE	0x00200000	/* Audio Transmit FIFO 1/2-full    */
+					/* or less interrupt Enable	   */
+#define MCCR0_ARE	0x00400000	/* Audio Receive FIFO 1/2-full or  */
+					/* more interrupt Enable	   */
+#define MCCR0_LBM	0x00800000	/* Look-Back Mode		   */
+#define MCCR0_ECP	Fld (2, 24)	/* External Clock Prescaler - 1    */
+#define MCCR0_ExtClkDiv(Div)		/*  External Clock Divisor [1..4]  */ \
+			(((Div) - 1) << FShft (MCCR0_ECP))
+
+#define MCDR0_DATA	Fld (12, 4)	/* receive/transmit audio DATA	   */
+					/* FIFOs			   */
+
+#define MCDR1_DATA	Fld (14, 2)	/* receive/transmit telecom DATA   */
+					/* FIFOs			   */
+
+					/* receive/transmit CODEC reg.	   */
+					/* FIFOs:			   */
+#define MCDR2_DATA	Fld (16, 0)	/*  reg. DATA			   */
+#define MCDR2_RW	0x00010000	/*  reg. Read/Write (transmit)	   */
+#define MCDR2_Rd	(MCDR2_RW*0)	/*   reg. Read			   */
+#define MCDR2_Wr	(MCDR2_RW*1)	/*   reg. Write			   */
+#define MCDR2_ADD	Fld (4, 17)	/*  reg. ADDress		   */
+
+#define MCSR_ATS	0x00000001	/* Audio Transmit FIFO 1/2-full    */
+					/* or less Service request (read)  */
+#define MCSR_ARS	0x00000002	/* Audio Receive FIFO 1/2-full or  */
+					/* more Service request (read)	   */
+#define MCSR_TTS	0x00000004	/* Telecom Transmit FIFO 1/2-full  */
+					/* or less Service request (read)  */
+#define MCSR_TRS	0x00000008	/* Telecom Receive FIFO 1/2-full   */
+					/* or more Service request (read)  */
+#define MCSR_ATU	0x00000010	/* Audio Transmit FIFO Under-run   */
+#define MCSR_ARO	0x00000020	/* Audio Receive FIFO Over-run	   */
+#define MCSR_TTU	0x00000040	/* Telecom Transmit FIFO Under-run */
+#define MCSR_TRO	0x00000080	/* Telecom Receive FIFO Over-run   */
+#define MCSR_ANF	0x00000100	/* Audio transmit FIFO Not Full    */
+					/* (read)			   */
+#define MCSR_ANE	0x00000200	/* Audio receive FIFO Not Empty    */
+					/* (read)			   */
+#define MCSR_TNF	0x00000400	/* Telecom transmit FIFO Not Full  */
+					/* (read)			   */
+#define MCSR_TNE	0x00000800	/* Telecom receive FIFO Not Empty  */
+					/* (read)			   */
+#define MCSR_CWC	0x00001000	/* CODEC register Write Completed  */
+					/* (read)			   */
+#define MCSR_CRC	0x00002000	/* CODEC register Read Completed   */
+					/* (read)			   */
+#define MCSR_ACE	0x00004000	/* Audio CODEC Enabled (read)	   */
+#define MCSR_TCE	0x00008000	/* Telecom CODEC Enabled (read)    */
+
+#define MCCR1_CFS	0x00100000	/* Clock Freq. Select		   */
+#define MCCR1_F12MHz	(MCCR1_CFS*0)	/*  Freq. (fmc) = ~ 12 MHz	   */
+					/*  (11.981 MHz)		   */
+#define MCCR1_F10MHz	(MCCR1_CFS*1)	/*  Freq. (fmc) = ~ 10 MHz	   */
+					/*  (9.585 MHz)			   */
+
+
+/*
+ * Synchronous Serial Port (SSP) control registers
+ *
+ * Registers
+ *    Ser4SSCR0		Serial port 4 Synchronous Serial Port (SSP) Control
+ *			Register 0 (read/write).
+ *    Ser4SSCR1		Serial port 4 Synchronous Serial Port (SSP) Control
+ *			Register 1 (read/write).
+ *			[Bits SPO and SP are only implemented in versions 2.0
+ *			(rev. = 8) and higher of the StrongARM SA-1100.]
+ *    Ser4SSDR		Serial port 4 Synchronous Serial Port (SSP) Data
+ *			Register (read/write).
+ *    Ser4SSSR		Serial port 4 Synchronous Serial Port (SSP) Status
+ *			Register (read/write).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *			or 3.5795 MHz).
+ *    fss, Tss		Frequency, period of the SSP communication.
+ */
+
+#define _Ser4SSCR0	0x80070060	/* Ser. port 4 SSP Control Reg. 0  */
+#define _Ser4SSCR1	0x80070064	/* Ser. port 4 SSP Control Reg. 1  */
+#define _Ser4SSDR	0x8007006C	/* Ser. port 4 SSP Data Reg.	   */
+#define _Ser4SSSR	0x80070074	/* Ser. port 4 SSP Status Reg.	   */
+
+#if LANGUAGE == C
+#define Ser4SSCR0			/* Ser. port 4 SSP Control Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser4SSCR0)))
+#define Ser4SSCR1			/* Ser. port 4 SSP Control Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser4SSCR1)))
+#define Ser4SSDR			/* Ser. port 4 SSP Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser4SSDR)))
+#define Ser4SSSR			/* Ser. port 4 SSP Status Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser4SSSR)))
+#endif /* LANGUAGE == C */
+
+#define SSCR0_DSS	Fld (4, 0)	/* Data Size - 1 Select [3..15]    */
+#define SSCR0_DataSize(Size)		/*  Data Size Select [4..16]	   */ \
+			(((Size) - 1) << FShft (SSCR0_DSS))
+#define SSCR0_FRF	Fld (2, 4)	/* FRame Format			   */
+#define SSCR0_Motorola			/*  Motorola Serial Peripheral	   */ \
+					/*  Interface (SPI) format	   */ \
+			(0 << FShft (SSCR0_FRF))
+#define SSCR0_TI			/*  Texas Instruments Synchronous  */ \
+					/*  Serial format		   */ \
+			(1 << FShft (SSCR0_FRF))
+#define SSCR0_National			/*  National Microwire format	   */ \
+			(2 << FShft (SSCR0_FRF))
+#define SSCR0_SSE	0x00000080	/* SSP Enable			   */
+#define SSCR0_SCR	Fld (8, 8)	/* Serial Clock Rate divisor/2 - 1 */
+					/* fss = fxtl/(2*(SCR + 1))	   */
+					/* Tss = 2*(SCR + 1)*Txtl	   */
+#define SSCR0_SerClkDiv(Div)		/*  Serial Clock Divisor [2..512]  */ \
+			(((Div) - 2)/2 << FShft (SSCR0_SCR))
+					/*  fss = fxtl/(2*Floor (Div/2))   */
+					/*  Tss = 2*Floor (Div/2)*Txtl	   */
+#define SSCR0_CeilSerClkDiv(Div)	/*  Ceil. of SerClkDiv [2..512]    */ \
+			(((Div) - 1)/2 << FShft (SSCR0_SCR))
+					/*  fss = fxtl/(2*Ceil (Div/2))    */
+					/*  Tss = 2*Ceil (Div/2)*Txtl	   */
+
+#define SSCR1_RIE	0x00000001	/* Receive FIFO 1/2-full or more   */
+					/* Interrupt Enable		   */
+#define SSCR1_TIE	0x00000002	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable		   */
+#define SSCR1_LBM	0x00000004	/* Look-Back Mode		   */
+#define SSCR1_SPO	0x00000008	/* Sample clock (SCLK) POlarity    */
+#define SSCR1_SClkIactL	(SSCR1_SPO*0)	/*  Sample Clock Inactive Low	   */
+#define SSCR1_SClkIactH	(SSCR1_SPO*1)	/*  Sample Clock Inactive High	   */
+#define SSCR1_SP	0x00000010	/* Sample clock (SCLK) Phase	   */
+#define SSCR1_SClk1P	(SSCR1_SP*0)	/*  Sample Clock active 1 Period   */
+					/*  after frame (SFRM, 1st edge)   */
+#define SSCR1_SClk1_2P	(SSCR1_SP*1)	/*  Sample Clock active 1/2 Period */
+					/*  after frame (SFRM, 1st edge)   */
+#define SSCR1_ECS	0x00000020	/* External Clock Select	   */
+#define SSCR1_IntClk	(SSCR1_ECS*0)	/*  Internal Clock		   */
+#define SSCR1_ExtClk	(SSCR1_ECS*1)	/*  External Clock (GPIO [19])	   */
+
+#define SSDR_DATA	Fld (16, 0)	/* receive/transmit DATA FIFOs	   */
+
+#define SSSR_TNF	0x00000002	/* Transmit FIFO Not Full (read)   */
+#define SSSR_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
+#define SSSR_BSY	0x00000008	/* SSP BuSY (read)		   */
+#define SSSR_TFS	0x00000010	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)	   */
+#define SSSR_RFS	0x00000020	/* Receive FIFO 1/2-full or more   */
+					/* Service request (read)	   */
+#define SSSR_ROR	0x00000040	/* Receive FIFO Over-Run	   */
+
+
+/*
+ * Operating System (OS) timer control registers
+ *
+ * Registers
+ *    OSMR0		Operating System (OS) timer Match Register 0
+ *			(read/write).
+ *    OSMR1		Operating System (OS) timer Match Register 1
+ *			(read/write).
+ *    OSMR2		Operating System (OS) timer Match Register 2
+ *			(read/write).
+ *    OSMR3		Operating System (OS) timer Match Register 3
+ *			(read/write).
+ *    OSCR		Operating System (OS) timer Counter Register
+ *			(read/write).
+ *    OSSR		Operating System (OS) timer Status Register
+ *			(read/write).
+ *    OWER		Operating System (OS) timer Watch-dog Enable Register
+ *			(read/write).
+ *    OIER		Operating System (OS) timer Interrupt Enable Register
+ *			(read/write).
+ */
+
+#define _OSMR(Nb)			/* OS timer Match Reg. [0..3]	   */ \
+			(0x90000000 + (Nb)*4)
+#define _OSMR0		_OSMR (0)	/* OS timer Match Reg. 0	   */
+#define _OSMR1		_OSMR (1)	/* OS timer Match Reg. 1	   */
+#define _OSMR2		_OSMR (2)	/* OS timer Match Reg. 2	   */
+#define _OSMR3		_OSMR (3)	/* OS timer Match Reg. 3	   */
+#define _OSCR		0x90000010	/* OS timer Counter Reg.	   */
+#define _OSSR		0x90000014	/* OS timer Status Reg.		   */
+#define _OWER		0x90000018	/* OS timer Watch-dog Enable Reg.  */
+#define _OIER		0x9000001C	/* OS timer Interrupt Enable Reg.  */
+
+#if LANGUAGE == C
+#define OSMR				/* OS timer Match Reg. [0..3]	   */ \
+			((volatile Word *) io_p2v (_OSMR (0)))
+#define OSMR0		(OSMR [0])	/* OS timer Match Reg. 0	   */
+#define OSMR1		(OSMR [1])	/* OS timer Match Reg. 1	   */
+#define OSMR2		(OSMR [2])	/* OS timer Match Reg. 2	   */
+#define OSMR3		(OSMR [3])	/* OS timer Match Reg. 3	   */
+#define OSCR				/* OS timer Counter Reg.	   */ \
+			(*((volatile Word *) io_p2v (_OSCR)))
+#define OSSR				/* OS timer Status Reg.		   */ \
+			(*((volatile Word *) io_p2v (_OSSR)))
+#define OWER				/* OS timer Watch-dog Enable Reg.  */ \
+			(*((volatile Word *) io_p2v (_OWER)))
+#define OIER				/* OS timer Interrupt Enable Reg.  */ \
+			(*((volatile Word *) io_p2v (_OIER)))
+#endif /* LANGUAGE == C */
+
+#define OSSR_M(Nb)			/* Match detected [0..3]	   */ \
+			(0x00000001 << (Nb))
+#define OSSR_M0		OSSR_M (0)	/* Match detected 0		   */
+#define OSSR_M1		OSSR_M (1)	/* Match detected 1		   */
+#define OSSR_M2		OSSR_M (2)	/* Match detected 2		   */
+#define OSSR_M3		OSSR_M (3)	/* Match detected 3		   */
+
+#define OWER_WME	0x00000001	/* Watch-dog Match Enable	   */
+					/* (set only)			   */
+
+#define OIER_E(Nb)			/* match interrupt Enable [0..3]   */ \
+			(0x00000001 << (Nb))
+#define OIER_E0		OIER_E (0)	/* match interrupt Enable 0	   */
+#define OIER_E1		OIER_E (1)	/* match interrupt Enable 1	   */
+#define OIER_E2		OIER_E (2)	/* match interrupt Enable 2	   */
+#define OIER_E3		OIER_E (3)	/* match interrupt Enable 3	   */
+
+
+/*
+ * Real-Time Clock (RTC) control registers
+ *
+ * Registers
+ *    RTAR		Real-Time Clock (RTC) Alarm Register (read/write).
+ *    RCNR		Real-Time Clock (RTC) CouNt Register (read/write).
+ *    RTTR		Real-Time Clock (RTC) Trim Register (read/write).
+ *    RTSR		Real-Time Clock (RTC) Status Register (read/write).
+ *
+ * Clocks
+ *    frtx, Trtx	Frequency, period of the real-time clock crystal
+ *			(32.768 kHz nominal).
+ *    frtc, Trtc	Frequency, period of the real-time clock counter
+ *			(1 Hz nominal).
+ */
+
+#define _RTAR		0x90010000	/* RTC Alarm Reg.		   */
+#define _RCNR		0x90010004	/* RTC CouNt Reg.		   */
+#define _RTTR		0x90010008	/* RTC Trim Reg.		   */
+#define _RTSR		0x90010010	/* RTC Status Reg.		   */
+
+#if LANGUAGE == C
+#define RTAR				/* RTC Alarm Reg.		   */ \
+			(*((volatile Word *) io_p2v (_RTAR)))
+#define RCNR				/* RTC CouNt Reg.		   */ \
+			(*((volatile Word *) io_p2v (_RCNR)))
+#define RTTR				/* RTC Trim Reg.		   */ \
+			(*((volatile Word *) io_p2v (_RTTR)))
+#define RTSR				/* RTC Status Reg.		   */ \
+			(*((volatile Word *) io_p2v (_RTSR)))
+#endif /* LANGUAGE == C */
+
+#define RTTR_C		Fld (16, 0)	/* clock divider Count - 1	   */
+#define RTTR_D		Fld (10, 16)	/* trim Delete count		   */
+					/* frtc = (1023*(C + 1) - D)*frtx/ */
+					/*	  (1023*(C + 1)^2)	   */
+					/* Trtc = (1023*(C + 1)^2)*Trtx/   */
+					/*	  (1023*(C + 1) - D)	   */
+
+#define RTSR_AL		0x00000001	/* ALarm detected		   */
+#define RTSR_HZ		0x00000002	/* 1 Hz clock detected		   */
+#define RTSR_ALE	0x00000004	/* ALarm interrupt Enable	   */
+#define RTSR_HZE	0x00000008	/* 1 Hz clock interrupt Enable	   */
+
+
+/*
+ * Power Manager (PM) control registers
+ *
+ * Registers
+ *    PMCR		Power Manager (PM) Control Register (read/write).
+ *    PSSR		Power Manager (PM) Sleep Status Register (read/write).
+ *    PSPR		Power Manager (PM) Scratch-Pad Register (read/write).
+ *    PWER		Power Manager (PM) Wake-up Enable Register
+ *			(read/write).
+ *    PCFR		Power Manager (PM) general ConFiguration Register
+ *			(read/write).
+ *    PPCR		Power Manager (PM) Phase-Locked Loop (PLL)
+ *			Configuration Register (read/write).
+ *    PGSR		Power Manager (PM) General-Purpose Input/Output (GPIO)
+ *			Sleep state Register (read/write, see GPIO pins).
+ *    POSR		Power Manager (PM) Oscillator Status Register (read).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *			or 3.5795 MHz).
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ */
+
+#define _PMCR		0x90020000	/* PM Control Reg.		   */
+#define _PSSR		0x90020004	/* PM Sleep Status Reg.		   */
+#define _PSPR		0x90020008	/* PM Scratch-Pad Reg.		   */
+#define _PWER		0x9002000C	/* PM Wake-up Enable Reg.	   */
+#define _PCFR		0x90020010	/* PM general ConFiguration Reg.   */
+#define _PPCR		0x90020014	/* PM PLL Configuration Reg.	   */
+#define _PGSR		0x90020018	/* PM GPIO Sleep state Reg.	   */
+#define _POSR		0x9002001C	/* PM Oscillator Status Reg.	   */
+
+#if LANGUAGE == C
+#define PMCR				/* PM Control Reg.		   */ \
+			(*((volatile Word *) io_p2v (_PMCR)))
+#define PSSR				/* PM Sleep Status Reg.		   */ \
+			(*((volatile Word *) io_p2v (_PSSR)))
+#define PSPR				/* PM Scratch-Pad Reg.		   */ \
+			(*((volatile Word *) io_p2v (_PSPR)))
+#define PWER				/* PM Wake-up Enable Reg.	   */ \
+			(*((volatile Word *) io_p2v (_PWER)))
+#define PCFR				/* PM general ConFiguration Reg.   */ \
+			(*((volatile Word *) io_p2v (_PCFR)))
+#define PPCR				/* PM PLL Configuration Reg.	   */ \
+			(*((volatile Word *) io_p2v (_PPCR)))
+#define PGSR				/* PM GPIO Sleep state Reg.	   */ \
+			(*((volatile Word *) io_p2v (_PGSR)))
+#define POSR				/* PM Oscillator Status Reg.	   */ \
+			(*((volatile Word *) io_p2v (_POSR)))
+
+#elif LANGUAGE == Assembly
+#define PMCR		(io_p2v (_PMCR))
+#define PSSR		(io_p2v (_PSSR))
+#define PSPR		(io_p2v (_PSPR))
+#define PWER		(io_p2v (_PWER))
+#define PCFR		(io_p2v (_PCFR))
+#define PPCR		(io_p2v (_PPCR))
+#define PGSR		(io_p2v (_PGSR))
+#define POSR		(io_p2v (_POSR))
+
+#endif /* LANGUAGE == C */
+
+#define PMCR_SF		0x00000001	/* Sleep Force (set only)	   */
+
+#define PSSR_SS		0x00000001	/* Software Sleep		   */
+#define PSSR_BFS	0x00000002	/* Battery Fault Status		   */
+					/* (BATT_FAULT)			   */
+#define PSSR_VFS	0x00000004	/* Vdd Fault Status (VDD_FAULT)    */
+#define PSSR_DH		0x00000008	/* DRAM control Hold		   */
+#define PSSR_PH		0x00000010	/* Peripheral control Hold	   */
+
+#define PWER_GPIO(Nb)	GPIO_GPIO (Nb)	/* GPIO [0..27] wake-up enable	   */
+#define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable	   */
+#define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable	   */
+#define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable	   */
+#define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable	   */
+#define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable	   */
+#define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable	   */
+#define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable	   */
+#define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable	   */
+#define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable	   */
+#define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable	   */
+#define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable	   */
+#define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable	   */
+#define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable	   */
+#define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable	   */
+#define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable	   */
+#define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable	   */
+#define PWER_GPIO16	PWER_GPIO (16)	/* GPIO [16] wake-up enable	   */
+#define PWER_GPIO17	PWER_GPIO (17)	/* GPIO [17] wake-up enable	   */
+#define PWER_GPIO18	PWER_GPIO (18)	/* GPIO [18] wake-up enable	   */
+#define PWER_GPIO19	PWER_GPIO (19)	/* GPIO [19] wake-up enable	   */
+#define PWER_GPIO20	PWER_GPIO (20)	/* GPIO [20] wake-up enable	   */
+#define PWER_GPIO21	PWER_GPIO (21)	/* GPIO [21] wake-up enable	   */
+#define PWER_GPIO22	PWER_GPIO (22)	/* GPIO [22] wake-up enable	   */
+#define PWER_GPIO23	PWER_GPIO (23)	/* GPIO [23] wake-up enable	   */
+#define PWER_GPIO24	PWER_GPIO (24)	/* GPIO [24] wake-up enable	   */
+#define PWER_GPIO25	PWER_GPIO (25)	/* GPIO [25] wake-up enable	   */
+#define PWER_GPIO26	PWER_GPIO (26)	/* GPIO [26] wake-up enable	   */
+#define PWER_GPIO27	PWER_GPIO (27)	/* GPIO [27] wake-up enable	   */
+#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable	   */
+
+#define PCFR_OPDE	0x00000001	/* Oscillator Power-Down Enable    */
+#define PCFR_ClkRun	(PCFR_OPDE*0)	/*  Clock Running in sleep mode    */
+#define PCFR_ClkStp	(PCFR_OPDE*1)	/*  Clock Stopped in sleep mode    */
+#define PCFR_FP		0x00000002	/* Float PCMCIA pins		   */
+#define PCFR_PCMCIANeg	(PCFR_FP*0)	/*  PCMCIA pins Negated (1)	   */
+#define PCFR_PCMCIAFlt	(PCFR_FP*1)	/*  PCMCIA pins Floating	   */
+#define PCFR_FS		0x00000004	/* Float Static memory pins	   */
+#define PCFR_StMemNeg	(PCFR_FS*0)	/*  Static Memory pins Negated (1) */
+#define PCFR_StMemFlt	(PCFR_FS*1)	/*  Static Memory pins Floating    */
+#define PCFR_FO		0x00000008	/* Force RTC oscillator		   */
+					/* (32.768 kHz) enable On	   */
+
+#define PPCR_CCF	Fld (5, 0)	/* CPU core Clock (CCLK) Freq.	   */
+#define PPCR_Fx16			/*  Freq. x 16 (fcpu = 16*fxtl)    */ \
+			(0x00 << FShft (PPCR_CCF))
+#define PPCR_Fx20			/*  Freq. x 20 (fcpu = 20*fxtl)    */ \
+			(0x01 << FShft (PPCR_CCF))
+#define PPCR_Fx24			/*  Freq. x 24 (fcpu = 24*fxtl)    */ \
+			(0x02 << FShft (PPCR_CCF))
+#define PPCR_Fx28			/*  Freq. x 28 (fcpu = 28*fxtl)    */ \
+			(0x03 << FShft (PPCR_CCF))
+#define PPCR_Fx32			/*  Freq. x 32 (fcpu = 32*fxtl)    */ \
+			(0x04 << FShft (PPCR_CCF))
+#define PPCR_Fx36			/*  Freq. x 36 (fcpu = 36*fxtl)    */ \
+			(0x05 << FShft (PPCR_CCF))
+#define PPCR_Fx40			/*  Freq. x 40 (fcpu = 40*fxtl)    */ \
+			(0x06 << FShft (PPCR_CCF))
+#define PPCR_Fx44			/*  Freq. x 44 (fcpu = 44*fxtl)    */ \
+			(0x07 << FShft (PPCR_CCF))
+#define PPCR_Fx48			/*  Freq. x 48 (fcpu = 48*fxtl)    */ \
+			(0x08 << FShft (PPCR_CCF))
+#define PPCR_Fx52			/*  Freq. x 52 (fcpu = 52*fxtl)    */ \
+			(0x09 << FShft (PPCR_CCF))
+#define PPCR_Fx56			/*  Freq. x 56 (fcpu = 56*fxtl)    */ \
+			(0x0A << FShft (PPCR_CCF))
+#define PPCR_Fx60			/*  Freq. x 60 (fcpu = 60*fxtl)    */ \
+			(0x0B << FShft (PPCR_CCF))
+#define PPCR_Fx64			/*  Freq. x 64 (fcpu = 64*fxtl)    */ \
+			(0x0C << FShft (PPCR_CCF))
+#define PPCR_Fx68			/*  Freq. x 68 (fcpu = 68*fxtl)    */ \
+			(0x0D << FShft (PPCR_CCF))
+#define PPCR_Fx72			/*  Freq. x 72 (fcpu = 72*fxtl)    */ \
+			(0x0E << FShft (PPCR_CCF))
+#define PPCR_Fx76			/*  Freq. x 76 (fcpu = 76*fxtl)    */ \
+			(0x0F << FShft (PPCR_CCF))
+					/*  3.6864 MHz crystal (fxtl):	   */
+#define PPCR_F59_0MHz	PPCR_Fx16	/*   Freq. (fcpu) =  59.0 MHz	   */
+#define PPCR_F73_7MHz	PPCR_Fx20	/*   Freq. (fcpu) =  73.7 MHz	   */
+#define PPCR_F88_5MHz	PPCR_Fx24	/*   Freq. (fcpu) =  88.5 MHz	   */
+#define PPCR_F103_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 103.2 MHz	   */
+#define PPCR_F118_0MHz	PPCR_Fx32	/*   Freq. (fcpu) = 118.0 MHz	   */
+#define PPCR_F132_7MHz	PPCR_Fx36	/*   Freq. (fcpu) = 132.7 MHz	   */
+#define PPCR_F147_5MHz	PPCR_Fx40	/*   Freq. (fcpu) = 147.5 MHz	   */
+#define PPCR_F162_2MHz	PPCR_Fx44	/*   Freq. (fcpu) = 162.2 MHz	   */
+#define PPCR_F176_9MHz	PPCR_Fx48	/*   Freq. (fcpu) = 176.9 MHz	   */
+#define PPCR_F191_7MHz	PPCR_Fx52	/*   Freq. (fcpu) = 191.7 MHz	   */
+#define PPCR_F206_4MHz	PPCR_Fx56	/*   Freq. (fcpu) = 206.4 MHz	   */
+#define PPCR_F221_2MHz	PPCR_Fx60	/*   Freq. (fcpu) = 221.2 MHz	   */
+#define PPCR_F239_6MHz	PPCR_Fx64	/*   Freq. (fcpu) = 239.6 MHz	   */
+#define PPCR_F250_7MHz	PPCR_Fx68	/*   Freq. (fcpu) = 250.7 MHz	   */
+#define PPCR_F265_4MHz	PPCR_Fx72	/*   Freq. (fcpu) = 265.4 MHz	   */
+#define PPCR_F280_2MHz	PPCR_Fx76	/*   Freq. (fcpu) = 280.2 MHz	   */
+					/*  3.5795 MHz crystal (fxtl):	   */
+#define PPCR_F57_3MHz	PPCR_Fx16	/*   Freq. (fcpu) =  57.3 MHz	   */
+#define PPCR_F71_6MHz	PPCR_Fx20	/*   Freq. (fcpu) =  71.6 MHz	   */
+#define PPCR_F85_9MHz	PPCR_Fx24	/*   Freq. (fcpu) =  85.9 MHz	   */
+#define PPCR_F100_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 100.2 MHz	   */
+#define PPCR_F114_5MHz	PPCR_Fx32	/*   Freq. (fcpu) = 114.5 MHz	   */
+#define PPCR_F128_9MHz	PPCR_Fx36	/*   Freq. (fcpu) = 128.9 MHz	   */
+#define PPCR_F143_2MHz	PPCR_Fx40	/*   Freq. (fcpu) = 143.2 MHz	   */
+#define PPCR_F157_5MHz	PPCR_Fx44	/*   Freq. (fcpu) = 157.5 MHz	   */
+#define PPCR_F171_8MHz	PPCR_Fx48	/*   Freq. (fcpu) = 171.8 MHz	   */
+#define PPCR_F186_1MHz	PPCR_Fx52	/*   Freq. (fcpu) = 186.1 MHz	   */
+#define PPCR_F200_5MHz	PPCR_Fx56	/*   Freq. (fcpu) = 200.5 MHz	   */
+#define PPCR_F214_8MHz	PPCR_Fx60	/*   Freq. (fcpu) = 214.8 MHz	   */
+#define PPCR_F229_1MHz	PPCR_Fx64	/*   Freq. (fcpu) = 229.1 MHz	   */
+#define PPCR_F243_4MHz	PPCR_Fx68	/*   Freq. (fcpu) = 243.4 MHz	   */
+#define PPCR_F257_7MHz	PPCR_Fx72	/*   Freq. (fcpu) = 257.7 MHz	   */
+#define PPCR_F272_0MHz	PPCR_Fx76	/*   Freq. (fcpu) = 272.0 MHz	   */
+
+#define POSR_OOK	0x00000001	/* RTC Oscillator (32.768 kHz) OK  */
+
+
+/*
+ * Reset Controller (RC) control registers
+ *
+ * Registers
+ *    RSRR		Reset Controller (RC) Software Reset Register
+ *			(read/write).
+ *    RCSR		Reset Controller (RC) Status Register (read/write).
+ */
+
+#define _RSRR		0x90030000	/* RC Software Reset Reg.	   */
+#define _RCSR		0x90030004	/* RC Status Reg.		   */
+
+#if LANGUAGE == C
+#define RSRR				/* RC Software Reset Reg.	   */ \
+			(*((volatile Word *) io_p2v (_RSRR)))
+#define RCSR				/* RC Status Reg.		   */ \
+			(*((volatile Word *) io_p2v (_RCSR)))
+#endif /* LANGUAGE == C */
+
+#define RSRR_SWR	0x00000001	/* SoftWare Reset (set only)	   */
+
+#define RCSR_HWR	0x00000001	/* HardWare Reset		   */
+#define RCSR_SWR	0x00000002	/* SoftWare Reset		   */
+#define RCSR_WDR	0x00000004	/* Watch-Dog Reset		   */
+#define RCSR_SMR	0x00000008	/* Sleep-Mode Reset		   */
+
+
+/*
+ * Test unit control registers
+ *
+ * Registers
+ *    TUCR		Test Unit Control Register (read/write).
+ */
+
+#define _TUCR		0x90030008	/* Test Unit Control Reg.	   */
+
+#if LANGUAGE == C
+#define TUCR				/* Test Unit Control Reg.	   */ \
+			(*((volatile Word *) io_p2v (_TUCR)))
+#endif /* LANGUAGE == C */
+
+#define TUCR_TIC	0x00000040	/* TIC mode			   */
+#define TUCR_TTST	0x00000080	/* Trim TeST mode		   */
+#define TUCR_RCRC	0x00000100	/* Richard's Cyclic Redundancy	   */
+					/* Check			   */
+#define TUCR_PMD	0x00000200	/* Power Management Disable	   */
+#define TUCR_MR		0x00000400	/* Memory Request mode		   */
+#define TUCR_NoMB	(TUCR_MR*0)	/*  No Memory Bus request & grant  */
+#define TUCR_MBGPIO	(TUCR_MR*1)	/*  Memory Bus request (MBREQ) &   */
+					/*  grant (MBGNT) on GPIO [22:21]  */
+#define TUCR_CTB	Fld (3, 20)	/* Clock Test Bits		   */
+#define TUCR_FDC	0x00800000	/* RTC Force Delete Count	   */
+#define TUCR_FMC	0x01000000	/* Force Michelle's Control mode   */
+#define TUCR_TMC	0x02000000	/* RTC Trimmer Multiplexer Control */
+#define TUCR_DPS	0x04000000	/* Disallow Pad Sleep		   */
+#define TUCR_TSEL	Fld (3, 29)	/* clock Test SELect on GPIO [27]  */
+#define TUCR_32_768kHz			/*  32.768 kHz osc. on GPIO [27]   */ \
+			(0 << FShft (TUCR_TSEL))
+#define TUCR_3_6864MHz			/*  3.6864 MHz osc. on GPIO [27]   */ \
+			(1 << FShft (TUCR_TSEL))
+#define TUCR_VDD			/*  VDD ring osc./16 on GPIO [27]  */ \
+			(2 << FShft (TUCR_TSEL))
+#define TUCR_96MHzPLL			/*  96 MHz PLL/4 on GPIO [27]	   */ \
+			(3 << FShft (TUCR_TSEL))
+#define TUCR_Clock			/*  internal (fcpu/2) & 32.768 kHz */ \
+					/*  Clocks on GPIO [26:27]	   */ \
+			(4 << FShft (TUCR_TSEL))
+#define TUCR_3_6864MHzA			/*  3.6864 MHz osc. on GPIO [27]   */ \
+					/*  (Alternative)		   */ \
+			(5 << FShft (TUCR_TSEL))
+#define TUCR_MainPLL			/*  Main PLL/16 on GPIO [27]	   */ \
+			(6 << FShft (TUCR_TSEL))
+#define TUCR_VDDL			/*  VDDL ring osc./4 on GPIO [27]  */ \
+			(7 << FShft (TUCR_TSEL))
+
+
+/*
+ * General-Purpose Input/Output (GPIO) control registers
+ *
+ * Registers
+ *    GPLR		General-Purpose Input/Output (GPIO) Pin Level
+ *			Register (read).
+ *    GPDR		General-Purpose Input/Output (GPIO) Pin Direction
+ *			Register (read/write).
+ *    GPSR		General-Purpose Input/Output (GPIO) Pin output Set
+ *			Register (write).
+ *    GPCR		General-Purpose Input/Output (GPIO) Pin output Clear
+ *			Register (write).
+ *    GRER		General-Purpose Input/Output (GPIO) Rising-Edge
+ *			detect Register (read/write).
+ *    GFER		General-Purpose Input/Output (GPIO) Falling-Edge
+ *			detect Register (read/write).
+ *    GEDR		General-Purpose Input/Output (GPIO) Edge Detect
+ *			status Register (read/write).
+ *    GAFR		General-Purpose Input/Output (GPIO) Alternate
+ *			Function Register (read/write).
+ *
+ * Clock
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ */
+
+#define _GPLR		0x90040000	/* GPIO Pin Level Reg.		   */
+#define _GPDR		0x90040004	/* GPIO Pin Direction Reg.	   */
+#define _GPSR		0x90040008	/* GPIO Pin output Set Reg.	   */
+#define _GPCR		0x9004000C	/* GPIO Pin output Clear Reg.	   */
+#define _GRER		0x90040010	/* GPIO Rising-Edge detect Reg.    */
+#define _GFER		0x90040014	/* GPIO Falling-Edge detect Reg.   */
+#define _GEDR		0x90040018	/* GPIO Edge Detect status Reg.    */
+#define _GAFR		0x9004001C	/* GPIO Alternate Function Reg.    */
+
+#if LANGUAGE == C
+#define GPLR				/* GPIO Pin Level Reg.		   */ \
+			(*((volatile Word *) io_p2v (_GPLR)))
+#define GPDR				/* GPIO Pin Direction Reg.	   */ \
+			(*((volatile Word *) io_p2v (_GPDR)))
+#define GPSR				/* GPIO Pin output Set Reg.	   */ \
+			(*((volatile Word *) io_p2v (_GPSR)))
+#define GPCR				/* GPIO Pin output Clear Reg.	   */ \
+			(*((volatile Word *) io_p2v (_GPCR)))
+#define GRER				/* GPIO Rising-Edge detect Reg.    */ \
+			(*((volatile Word *) io_p2v (_GRER)))
+#define GFER				/* GPIO Falling-Edge detect Reg.   */ \
+			(*((volatile Word *) io_p2v (_GFER)))
+#define GEDR				/* GPIO Edge Detect status Reg.    */ \
+			(*((volatile Word *) io_p2v (_GEDR)))
+#define GAFR				/* GPIO Alternate Function Reg.    */ \
+			(*((volatile Word *) io_p2v (_GAFR)))
+#elif LANGUAGE == Assembly
+
+#define GPLR  (io_p2v (_GPLR))
+#define GPDR  (io_p2v (_GPDR))
+#define GPSR  (io_p2v (_GPSR))
+#define GPCR  (io_p2v (_GPCR))
+#define GRER  (io_p2v (_GRER))
+#define GFER  (io_p2v (_GFER))
+#define GEDR  (io_p2v (_GEDR))
+#define GAFR  (io_p2v (_GAFR))
+
+#endif /* LANGUAGE == C */
+
+#define GPIO_MIN	(0)
+#define GPIO_MAX	(27)
+
+#define GPIO_GPIO(Nb)			/* GPIO [0..27]			   */ \
+			(0x00000001 << (Nb))
+#define GPIO_GPIO0	GPIO_GPIO (0)	/* GPIO  [0]			   */
+#define GPIO_GPIO1	GPIO_GPIO (1)	/* GPIO  [1]			   */
+#define GPIO_GPIO2	GPIO_GPIO (2)	/* GPIO  [2]			   */
+#define GPIO_GPIO3	GPIO_GPIO (3)	/* GPIO  [3]			   */
+#define GPIO_GPIO4	GPIO_GPIO (4)	/* GPIO  [4]			   */
+#define GPIO_GPIO5	GPIO_GPIO (5)	/* GPIO  [5]			   */
+#define GPIO_GPIO6	GPIO_GPIO (6)	/* GPIO  [6]			   */
+#define GPIO_GPIO7	GPIO_GPIO (7)	/* GPIO  [7]			   */
+#define GPIO_GPIO8	GPIO_GPIO (8)	/* GPIO  [8]			   */
+#define GPIO_GPIO9	GPIO_GPIO (9)	/* GPIO  [9]			   */
+#define GPIO_GPIO10	GPIO_GPIO (10)	/* GPIO [10]			   */
+#define GPIO_GPIO11	GPIO_GPIO (11)	/* GPIO [11]			   */
+#define GPIO_GPIO12	GPIO_GPIO (12)	/* GPIO [12]			   */
+#define GPIO_GPIO13	GPIO_GPIO (13)	/* GPIO [13]			   */
+#define GPIO_GPIO14	GPIO_GPIO (14)	/* GPIO [14]			   */
+#define GPIO_GPIO15	GPIO_GPIO (15)	/* GPIO [15]			   */
+#define GPIO_GPIO16	GPIO_GPIO (16)	/* GPIO [16]			   */
+#define GPIO_GPIO17	GPIO_GPIO (17)	/* GPIO [17]			   */
+#define GPIO_GPIO18	GPIO_GPIO (18)	/* GPIO [18]			   */
+#define GPIO_GPIO19	GPIO_GPIO (19)	/* GPIO [19]			   */
+#define GPIO_GPIO20	GPIO_GPIO (20)	/* GPIO [20]			   */
+#define GPIO_GPIO21	GPIO_GPIO (21)	/* GPIO [21]			   */
+#define GPIO_GPIO22	GPIO_GPIO (22)	/* GPIO [22]			   */
+#define GPIO_GPIO23	GPIO_GPIO (23)	/* GPIO [23]			   */
+#define GPIO_GPIO24	GPIO_GPIO (24)	/* GPIO [24]			   */
+#define GPIO_GPIO25	GPIO_GPIO (25)	/* GPIO [25]			   */
+#define GPIO_GPIO26	GPIO_GPIO (26)	/* GPIO [26]			   */
+#define GPIO_GPIO27	GPIO_GPIO (27)	/* GPIO [27]			   */
+
+#define GPIO_LDD(Nb)			/* LCD Data [8..15] (O)		   */ \
+			GPIO_GPIO ((Nb) - 6)
+#define GPIO_LDD8	GPIO_LDD (8)	/* LCD Data  [8] (O)		   */
+#define GPIO_LDD9	GPIO_LDD (9)	/* LCD Data  [9] (O)		   */
+#define GPIO_LDD10	GPIO_LDD (10)	/* LCD Data [10] (O)		   */
+#define GPIO_LDD11	GPIO_LDD (11)	/* LCD Data [11] (O)		   */
+#define GPIO_LDD12	GPIO_LDD (12)	/* LCD Data [12] (O)		   */
+#define GPIO_LDD13	GPIO_LDD (13)	/* LCD Data [13] (O)		   */
+#define GPIO_LDD14	GPIO_LDD (14)	/* LCD Data [14] (O)		   */
+#define GPIO_LDD15	GPIO_LDD (15)	/* LCD Data [15] (O)		   */
+					/* ser. port 4:			   */
+#define GPIO_SSP_TXD	GPIO_GPIO (10)	/*  SSP Transmit Data (O)	   */
+#define GPIO_SSP_RXD	GPIO_GPIO (11)	/*  SSP Receive Data (I)	   */
+#define GPIO_SSP_SCLK	GPIO_GPIO (12)	/*  SSP Sample CLocK (O)	   */
+#define GPIO_SSP_SFRM	GPIO_GPIO (13)	/*  SSP Sample FRaMe (O)	   */
+					/* ser. port 1:			   */
+#define GPIO_UART_TXD	GPIO_GPIO (14)	/*  UART Transmit Data (O)	   */
+#define GPIO_UART_RXD	GPIO_GPIO (15)	/*  UART Receive Data (I)	   */
+#define GPIO_SDLC_SCLK	GPIO_GPIO (16)	/*  SDLC Sample CLocK (I/O)	   */
+#define GPIO_SDLC_AAF	GPIO_GPIO (17)	/*  SDLC Abort After Frame (O)	   */
+#define GPIO_UART_SCLK1	GPIO_GPIO (18)	/*  UART Sample CLocK 1 (I)	   */
+					/* ser. port 4:			   */
+#define GPIO_SSP_CLK	GPIO_GPIO (19)	/*  SSP external CLocK (I)	   */
+					/* ser. port 3:			   */
+#define GPIO_UART_SCLK3	GPIO_GPIO (20)	/*  UART Sample CLocK 3 (I)	   */
+					/* ser. port 4:			   */
+#define GPIO_MCP_CLK	GPIO_GPIO (21)	/*  MCP CLocK (I)		   */
+					/* test controller:		   */
+#define GPIO_TIC_ACK	GPIO_GPIO (21)	/*  TIC ACKnowledge (O)		   */
+#define GPIO_MBGNT	GPIO_GPIO (21)	/*  Memory Bus GraNT (O)	   */
+#define GPIO_TREQA	GPIO_GPIO (22)	/*  TIC REQuest A (I)		   */
+#define GPIO_MBREQ	GPIO_GPIO (22)	/*  Memory Bus REQuest (I)	   */
+#define GPIO_TREQB	GPIO_GPIO (23)	/*  TIC REQuest B (I)		   */
+#define GPIO_1Hz	GPIO_GPIO (25)	/* 1 Hz clock (O)		   */
+#define GPIO_RCLK	GPIO_GPIO (26)	/* internal (R) CLocK (O, fcpu/2)  */
+#define GPIO_32_768kHz	GPIO_GPIO (27)	/* 32.768 kHz clock (O, RTC)	   */
+
+#define GPDR_In		0		/* Input			   */
+#define GPDR_Out	1		/* Output			   */
+
+
+/*
+ * Interrupt Controller (IC) control registers
+ *
+ * Registers
+ *    ICIP		Interrupt Controller (IC) Interrupt ReQuest (IRQ)
+ *			Pending register (read).
+ *    ICMR		Interrupt Controller (IC) Mask Register (read/write).
+ *    ICLR		Interrupt Controller (IC) Level Register (read/write).
+ *    ICCR		Interrupt Controller (IC) Control Register
+ *			(read/write).
+ *			[The ICCR register is only implemented in versions 2.0
+ *			(rev. = 8) and higher of the StrongARM SA-1100.]
+ *    ICFP		Interrupt Controller (IC) Fast Interrupt reQuest
+ *			(FIQ) Pending register (read).
+ *    ICPR		Interrupt Controller (IC) Pending Register (read).
+ *			[The ICPR register is active low (inverted) in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it is active high (non-inverted) in
+ *			versions 2.0 (rev. = 8) and higher.]
+ */
+
+#define _ICIP		0x90050000	/* IC IRQ Pending reg.		   */
+#define _ICMR		0x90050004	/* IC Mask Reg.			   */
+#define _ICLR		0x90050008	/* IC Level Reg.		   */
+#define _ICCR		0x9005000C	/* IC Control Reg.		   */
+#define _ICFP		0x90050010	/* IC FIQ Pending reg.		   */
+#define _ICPR		0x90050020	/* IC Pending Reg.		   */
+
+#if LANGUAGE == C
+#define ICIP				/* IC IRQ Pending reg.		   */ \
+			(*((volatile Word *) io_p2v (_ICIP)))
+#define ICMR				/* IC Mask Reg.			   */ \
+			(*((volatile Word *) io_p2v (_ICMR)))
+#define ICLR				/* IC Level Reg.		   */ \
+			(*((volatile Word *) io_p2v (_ICLR)))
+#define ICCR				/* IC Control Reg.		   */ \
+			(*((volatile Word *) io_p2v (_ICCR)))
+#define ICFP				/* IC FIQ Pending reg.		   */ \
+			(*((volatile Word *) io_p2v (_ICFP)))
+#define ICPR				/* IC Pending Reg.		   */ \
+			(*((volatile Word *) io_p2v (_ICPR)))
+#endif /* LANGUAGE == C */
+
+#define IC_GPIO(Nb)			/* GPIO [0..10]			   */ \
+			(0x00000001 << (Nb))
+#define IC_GPIO0	IC_GPIO (0)	/* GPIO  [0]			   */
+#define IC_GPIO1	IC_GPIO (1)	/* GPIO  [1]			   */
+#define IC_GPIO2	IC_GPIO (2)	/* GPIO  [2]			   */
+#define IC_GPIO3	IC_GPIO (3)	/* GPIO  [3]			   */
+#define IC_GPIO4	IC_GPIO (4)	/* GPIO  [4]			   */
+#define IC_GPIO5	IC_GPIO (5)	/* GPIO  [5]			   */
+#define IC_GPIO6	IC_GPIO (6)	/* GPIO  [6]			   */
+#define IC_GPIO7	IC_GPIO (7)	/* GPIO  [7]			   */
+#define IC_GPIO8	IC_GPIO (8)	/* GPIO  [8]			   */
+#define IC_GPIO9	IC_GPIO (9)	/* GPIO  [9]			   */
+#define IC_GPIO10	IC_GPIO (10)	/* GPIO [10]			   */
+#define IC_GPIO11_27	0x00000800	/* GPIO [11:27] (ORed)		   */
+#define IC_LCD		0x00001000	/* LCD controller		   */
+#define IC_Ser0UDC	0x00002000	/* Ser. port 0 UDC		   */
+#define IC_Ser1SDLC	0x00004000	/* Ser. port 1 SDLC		   */
+#define IC_Ser1UART	0x00008000	/* Ser. port 1 UART		   */
+#define IC_Ser2ICP	0x00010000	/* Ser. port 2 ICP		   */
+#define IC_Ser3UART	0x00020000	/* Ser. port 3 UART		   */
+#define IC_Ser4MCP	0x00040000	/* Ser. port 4 MCP		   */
+#define IC_Ser4SSP	0x00080000	/* Ser. port 4 SSP		   */
+#define IC_DMA(Nb)			/* DMA controller channel [0..5]   */ \
+			(0x00100000 << (Nb))
+#define IC_DMA0		IC_DMA (0)	/* DMA controller channel 0	   */
+#define IC_DMA1		IC_DMA (1)	/* DMA controller channel 1	   */
+#define IC_DMA2		IC_DMA (2)	/* DMA controller channel 2	   */
+#define IC_DMA3		IC_DMA (3)	/* DMA controller channel 3	   */
+#define IC_DMA4		IC_DMA (4)	/* DMA controller channel 4	   */
+#define IC_DMA5		IC_DMA (5)	/* DMA controller channel 5	   */
+#define IC_OST(Nb)			/* OS Timer match [0..3]	   */ \
+			(0x04000000 << (Nb))
+#define IC_OST0		IC_OST (0)	/* OS Timer match 0		   */
+#define IC_OST1		IC_OST (1)	/* OS Timer match 1		   */
+#define IC_OST2		IC_OST (2)	/* OS Timer match 2		   */
+#define IC_OST3		IC_OST (3)	/* OS Timer match 3		   */
+#define IC_RTC1Hz	0x40000000	/* RTC 1 Hz clock		   */
+#define IC_RTCAlrm	0x80000000	/* RTC Alarm			   */
+
+#define ICLR_IRQ	0		/* Interrupt ReQuest		   */
+#define ICLR_FIQ	1		/* Fast Interrupt reQuest	   */
+
+#define ICCR_DIM	0x00000001	/* Disable Idle-mode interrupt	   */
+					/* Mask				   */
+#define ICCR_IdleAllInt	(ICCR_DIM*0)	/*  Idle-mode All Interrupt enable */
+					/*  (ICMR ignored)		   */
+#define ICCR_IdleMskInt	(ICCR_DIM*1)	/*  Idle-mode non-Masked Interrupt */
+					/*  enable (ICMR used)		   */
+
+
+/*
+ * Peripheral Pin Controller (PPC) control registers
+ *
+ * Registers
+ *    PPDR		Peripheral Pin Controller (PPC) Pin Direction
+ *			Register (read/write).
+ *    PPSR		Peripheral Pin Controller (PPC) Pin State Register
+ *			(read/write).
+ *    PPAR		Peripheral Pin Controller (PPC) Pin Assignment
+ *			Register (read/write).
+ *    PSDR		Peripheral Pin Controller (PPC) Sleep-mode pin
+ *			Direction Register (read/write).
+ *    PPFR		Peripheral Pin Controller (PPC) Pin Flag Register
+ *			(read).
+ */
+
+#define _PPDR		0x90060000	/* PPC Pin Direction Reg.	   */
+#define _PPSR		0x90060004	/* PPC Pin State Reg.		   */
+#define _PPAR		0x90060008	/* PPC Pin Assignment Reg.	   */
+#define _PSDR		0x9006000C	/* PPC Sleep-mode pin Direction    */
+					/* Reg.				   */
+#define _PPFR		0x90060010	/* PPC Pin Flag Reg.		   */
+
+#if LANGUAGE == C
+#define PPDR				/* PPC Pin Direction Reg.	   */ \
+			(*((volatile Word *) io_p2v (_PPDR)))
+#define PPSR				/* PPC Pin State Reg.		   */ \
+			(*((volatile Word *) io_p2v (_PPSR)))
+#define PPAR				/* PPC Pin Assignment Reg.	   */ \
+			(*((volatile Word *) io_p2v (_PPAR)))
+#define PSDR				/* PPC Sleep-mode pin Direction    */ \
+					/* Reg.				   */ \
+			(*((volatile Word *) io_p2v (_PSDR)))
+#define PPFR				/* PPC Pin Flag Reg.		   */ \
+			(*((volatile Word *) io_p2v (_PPFR)))
+#endif /* LANGUAGE == C */
+
+#define PPC_LDD(Nb)			/* LCD Data [0..7]		   */ \
+			(0x00000001 << (Nb))
+#define PPC_LDD0	PPC_LDD (0)	/* LCD Data [0]			   */
+#define PPC_LDD1	PPC_LDD (1)	/* LCD Data [1]			   */
+#define PPC_LDD2	PPC_LDD (2)	/* LCD Data [2]			   */
+#define PPC_LDD3	PPC_LDD (3)	/* LCD Data [3]			   */
+#define PPC_LDD4	PPC_LDD (4)	/* LCD Data [4]			   */
+#define PPC_LDD5	PPC_LDD (5)	/* LCD Data [5]			   */
+#define PPC_LDD6	PPC_LDD (6)	/* LCD Data [6]			   */
+#define PPC_LDD7	PPC_LDD (7)	/* LCD Data [7]			   */
+#define PPC_L_PCLK	0x00000100	/* LCD Pixel CLocK		   */
+#define PPC_L_LCLK	0x00000200	/* LCD Line CLocK		   */
+#define PPC_L_FCLK	0x00000400	/* LCD Frame CLocK		   */
+#define PPC_L_BIAS	0x00000800	/* LCD AC BIAS			   */
+					/* ser. port 1:			   */
+#define PPC_TXD1	0x00001000	/*  SDLC/UART Transmit Data 1	   */
+#define PPC_RXD1	0x00002000	/*  SDLC/UART Receive Data 1	   */
+					/* ser. port 2:			   */
+#define PPC_TXD2	0x00004000	/*  IPC Transmit Data 2		   */
+#define PPC_RXD2	0x00008000	/*  IPC Receive Data 2		   */
+					/* ser. port 3:			   */
+#define PPC_TXD3	0x00010000	/*  UART Transmit Data 3	   */
+#define PPC_RXD3	0x00020000	/*  UART Receive Data 3		   */
+					/* ser. port 4:			   */
+#define PPC_TXD4	0x00040000	/*  MCP/SSP Transmit Data 4	   */
+#define PPC_RXD4	0x00080000	/*  MCP/SSP Receive Data 4	   */
+#define PPC_SCLK	0x00100000	/*  MCP/SSP Sample CLocK	   */
+#define PPC_SFRM	0x00200000	/*  MCP/SSP Sample FRaMe	   */
+
+#define PPDR_In		0		/* Input			   */
+#define PPDR_Out	1		/* Output			   */
+
+					/* ser. port 1:			   */
+#define PPAR_UPR	0x00001000	/*  UART Pin Reassignment	   */
+#define PPAR_UARTTR	(PPAR_UPR*0)	/*   UART on TXD_1 & RXD_1	   */
+#define PPAR_UARTGPIO	(PPAR_UPR*1)	/*   UART on GPIO [14:15]	   */
+					/* ser. port 4:			   */
+#define PPAR_SPR	0x00040000	/*  SSP Pin Reassignment	   */
+#define PPAR_SSPTRSS	(PPAR_SPR*0)	/*   SSP on TXD_C, RXD_C, SCLK_C,  */
+					/*   & SFRM_C			   */
+#define PPAR_SSPGPIO	(PPAR_SPR*1)	/*   SSP on GPIO [10:13]	   */
+
+#define PSDR_OutL	0		/* Output Low in sleep mode	   */
+#define PSDR_Flt	1		/* Floating (input) in sleep mode  */
+
+#define PPFR_LCD	0x00000001	/* LCD controller		   */
+#define PPFR_SP1TX	0x00001000	/* Ser. Port 1 SDLC/UART Transmit  */
+#define PPFR_SP1RX	0x00002000	/* Ser. Port 1 SDLC/UART Receive   */
+#define PPFR_SP2TX	0x00004000	/* Ser. Port 2 ICP Transmit	   */
+#define PPFR_SP2RX	0x00008000	/* Ser. Port 2 ICP Receive	   */
+#define PPFR_SP3TX	0x00010000	/* Ser. Port 3 UART Transmit	   */
+#define PPFR_SP3RX	0x00020000	/* Ser. Port 3 UART Receive	   */
+#define PPFR_SP4	0x00040000	/* Ser. Port 4 MCP/SSP		   */
+#define PPFR_PerEn	0		/* Peripheral Enabled		   */
+#define PPFR_PPCEn	1		/* PPC Enabled			   */
+
+
+/*
+ * Dynamic Random-Access Memory (DRAM) control registers
+ *
+ * Registers
+ *    MDCNFG		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			CoNFiGuration register (read/write).
+ *    MDCAS0		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			Column Address Strobe (CAS) shift register 0
+ *			(read/write).
+ *    MDCAS1		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			Column Address Strobe (CAS) shift register 1
+ *			(read/write).
+ *    MDCAS2		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			Column Address Strobe (CAS) shift register 2
+ *			(read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fcas, Tcas	Frequency, period of the DRAM CAS shift registers.
+ */
+
+					/* Memory system:		   */
+#define _MDCNFG		0xA0000000	/*  DRAM CoNFiGuration reg.	   */
+#define _MDCAS(Nb)			/*  DRAM CAS shift reg. [0..3]	   */ \
+			(0xA0000004 + (Nb)*4)
+#define _MDCAS0		_MDCAS (0)	/*  DRAM CAS shift reg. 0	   */
+#define _MDCAS1		_MDCAS (1)	/*  DRAM CAS shift reg. 1	   */
+#define _MDCAS2		_MDCAS (2)	/*  DRAM CAS shift reg. 2	   */
+
+#if LANGUAGE == C
+					/* Memory system:		   */
+#define MDCNFG				/*  DRAM CoNFiGuration reg.	   */ \
+			(*((volatile Word *) io_p2v (_MDCNFG)))
+#define MDCAS				/*  DRAM CAS shift reg. [0..3]	   */ \
+			((volatile Word *) io_p2v (_MDCAS (0)))
+#define MDCAS0		(MDCAS [0])	/*  DRAM CAS shift reg. 0	   */
+#define MDCAS1		(MDCAS [1])	/*  DRAM CAS shift reg. 1	   */
+#define MDCAS2		(MDCAS [2])	/*  DRAM CAS shift reg. 2	   */
+
+#elif LANGUAGE == Assembly
+
+#define MDCNFG		(io_p2v(_MDCNFG))
+
+#endif /* LANGUAGE == C */
+
+/* SA1100 MDCNFG values */
+#define MDCNFG_DE(Nb)			/* DRAM Enable bank [0..3]	   */ \
+			(0x00000001 << (Nb))
+#define MDCNFG_DE0	MDCNFG_DE (0)	/* DRAM Enable bank 0		   */
+#define MDCNFG_DE1	MDCNFG_DE (1)	/* DRAM Enable bank 1		   */
+#define MDCNFG_DE2	MDCNFG_DE (2)	/* DRAM Enable bank 2		   */
+#define MDCNFG_DE3	MDCNFG_DE (3)	/* DRAM Enable bank 3		   */
+#define MDCNFG_DRAC	Fld (2, 4)	/* DRAM Row Address Count - 9	   */
+#define MDCNFG_RowAdd(Add)		/*  Row Address count [9..12]	   */ \
+			(((Add) - 9) << FShft (MDCNFG_DRAC))
+#define MDCNFG_CDB2	0x00000040	/* shift reg. Clock Divide By 2    */
+					/* (fcas = fcpu/2)		   */
+#define MDCNFG_TRP	Fld (4, 7)	/* Time RAS Pre-charge - 1 [Tmem]  */
+#define MDCNFG_PrChrg(Tcpu)		/*  Pre-Charge time [2..32 Tcpu]   */ \
+			(((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
+#define MDCNFG_CeilPrChrg(Tcpu)		/*  Ceil. of PrChrg [2..32 Tcpu]   */ \
+			(((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
+#define MDCNFG_TRASR	Fld (4, 11)	/* Time RAS Refresh - 1 [Tmem]	   */
+#define MDCNFG_Ref(Tcpu)		/*  Refresh time [2..32 Tcpu]	   */ \
+			(((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
+#define MDCNFG_CeilRef(Tcpu)		/*  Ceil. of Ref [2..32 Tcpu]	   */ \
+			(((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
+#define MDCNFG_TDL	Fld (2, 15)	/* Time Data Latch [Tcpu]	   */
+#define MDCNFG_DataLtch(Tcpu)		/*  Data Latch delay [0..3 Tcpu]   */ \
+			((Tcpu) << FShft (MDCNFG_TDL))
+#define MDCNFG_DRI	Fld (15, 17)	/* min. DRAM Refresh Interval/4    */
+					/* [Tmem]			   */
+#define MDCNFG_RefInt(Tcpu)		/*  min. Refresh Interval	   */ \
+					/*  [0..262136 Tcpu]		   */ \
+			((Tcpu)/8 << FShft (MDCNFG_DRI))
+
+/* SA1110 MDCNFG values */
+#define MDCNFG_SA1110_DE0	0x00000001	/* DRAM Enable bank 0	     */
+#define MDCNFG_SA1110_DE1	0x00000002	/* DRAM Enable bank 1	     */
+#define MDCNFG_SA1110_DTIM0	0x00000004	/* DRAM timing type 0/1      */
+#define MDCNFG_SA1110_DWID0	0x00000008	/* DRAM bus width 0/1	     */
+#define MDCNFG_SA1110_DRAC0	Fld(3, 4)	/* DRAM row addr bit count   */
+						/* bank 0/1		     */
+#define MDCNFG_SA1110_CDB20	0x00000080	/* Mem Clock divide by 2 0/1 */
+#define MDCNFG_SA1110_TRP0	Fld(3, 8)	/* RAS precharge 0/1	     */
+#define MDCNFG_SA1110_TDL0	Fld(2, 12)	/* Data input latch after CAS*/
+						/* deassertion 0/1	     */
+#define MDCNFG_SA1110_TWR0	Fld(2, 14)	/* SDRAM write recovery 0/1  */
+#define MDCNFG_SA1110_DE2	0x00010000	/* DRAM Enable bank 0	     */
+#define MDCNFG_SA1110_DE3	0x00020000	/* DRAM Enable bank 1	     */
+#define MDCNFG_SA1110_DTIM2	0x00040000	/* DRAM timing type 0/1      */
+#define MDCNFG_SA1110_DWID2	0x00080000	/* DRAM bus width 0/1	     */
+#define MDCNFG_SA1110_DRAC2	Fld(3, 20)	/* DRAM row addr bit count   */
+						/* bank 0/1		     */
+#define MDCNFG_SA1110_CDB22	0x00800000	/* Mem Clock divide by 2 0/1 */
+#define MDCNFG_SA1110_TRP2	Fld(3, 24)	/* RAS precharge 0/1	     */
+#define MDCNFG_SA1110_TDL2	Fld(2, 28)	/* Data input latch after CAS*/
+						/* deassertion 0/1	     */
+#define MDCNFG_SA1110_TWR2	Fld(2, 30)	/* SDRAM write recovery 0/1  */
+
+
+/*
+ * Static memory control registers
+ *
+ * Registers
+ *    MSC0		Memory system: Static memory Control register 0
+ *			(read/write).
+ *    MSC1		Memory system: Static memory Control register 1
+ *			(read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ */
+
+					/* Memory system:		   */
+#define _MSC(Nb)			/*  Static memory Control reg.	   */ \
+					/*  [0..1]			   */ \
+			(0xA0000010 + (Nb)*4)
+#define _MSC0		_MSC (0)	/*  Static memory Control reg. 0   */
+#define _MSC1		_MSC (1)	/*  Static memory Control reg. 1   */
+#define _MSC2		0xA000002C	/*  Static memory Control reg. 2, not contiguous   */
+
+#if LANGUAGE == C
+					/* Memory system:		   */
+#define MSC				/*  Static memory Control reg.	   */ \
+					/*  [0..1]			   */ \
+			((volatile Word *) io_p2v (_MSC (0)))
+#define MSC0		(MSC [0])	/*  Static memory Control reg. 0   */
+#define MSC1		(MSC [1])	/*  Static memory Control reg. 1   */
+#define MSC2		(*(volatile Word *) io_p2v (_MSC2))	/*  Static memory Control reg. 2   */
+
+#elif LANGUAGE == Assembly
+
+#define MSC0		io_p2v(0xa0000010)
+#define MSC1		io_p2v(0xa0000014)
+#define MSC2		io_p2v(0xa000002c)
+
+#endif /* LANGUAGE == C */
+
+#define MSC_Bnk(Nb)			/* static memory Bank [0..3]	   */ \
+			Fld (16, ((Nb) Modulo 2)*16)
+#define MSC0_Bnk0	MSC_Bnk (0)	/* static memory Bank 0		   */
+#define MSC0_Bnk1	MSC_Bnk (1)	/* static memory Bank 1		   */
+#define MSC1_Bnk2	MSC_Bnk (2)	/* static memory Bank 2		   */
+#define MSC1_Bnk3	MSC_Bnk (3)	/* static memory Bank 3		   */
+
+#define MSC_RT		Fld (2, 0)	/* ROM/static memory Type	   */
+#define MSC_NonBrst			/*  Non-Burst static memory	   */ \
+			(0 << FShft (MSC_RT))
+#define MSC_SRAM			/*  32-bit byte-writable SRAM	   */ \
+			(1 << FShft (MSC_RT))
+#define MSC_Brst4			/*  Burst-of-4 static memory	   */ \
+			(2 << FShft (MSC_RT))
+#define MSC_Brst8			/*  Burst-of-8 static memory	   */ \
+			(3 << FShft (MSC_RT))
+#define MSC_RBW		0x0004		/* ROM/static memory Bus Width	   */
+#define MSC_32BitStMem	(MSC_RBW*0)	/*  32-Bit Static Memory	   */
+#define MSC_16BitStMem	(MSC_RBW*1)	/*  16-Bit Static Memory	   */
+#define MSC_RDF		Fld (5, 3)	/* ROM/static memory read Delay    */
+					/* First access - 1(.5) [Tmem]	   */
+#define MSC_1stRdAcc(Tcpu)		/*  1st Read Access time (burst    */ \
+					/*  static memory) [3..65 Tcpu]    */ \
+			((((Tcpu) - 3)/2) << FShft (MSC_RDF))
+#define MSC_Ceil1stRdAcc(Tcpu)		/*  Ceil. of 1stRdAcc [3..65 Tcpu] */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDF))
+#define MSC_RdAcc(Tcpu)			/*  Read Access time (non-burst    */ \
+					/*  static memory) [2..64 Tcpu]    */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDF))
+#define MSC_CeilRdAcc(Tcpu)		/*  Ceil. of RdAcc [2..64 Tcpu]    */ \
+			((((Tcpu) - 1)/2) << FShft (MSC_RDF))
+#define MSC_RDN		Fld (5, 8)	/* ROM/static memory read Delay    */
+					/* Next access - 1 [Tmem]	   */
+#define MSC_NxtRdAcc(Tcpu)		/*  Next Read Access time (burst   */ \
+					/*  static memory) [2..64 Tcpu]    */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDN))
+#define MSC_CeilNxtRdAcc(Tcpu)		/*  Ceil. of NxtRdAcc [2..64 Tcpu] */ \
+			((((Tcpu) - 1)/2) << FShft (MSC_RDN))
+#define MSC_WrAcc(Tcpu)			/*  Write Access time (non-burst   */ \
+					/*  static memory) [2..64 Tcpu]    */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDN))
+#define MSC_CeilWrAcc(Tcpu)		/*  Ceil. of WrAcc [2..64 Tcpu]    */ \
+			((((Tcpu) - 1)/2) << FShft (MSC_RDN))
+#define MSC_RRR		Fld (3, 13)	/* ROM/static memory RecoveRy	   */
+					/* time/2 [Tmem]		   */
+#define MSC_Rec(Tcpu)			/*  Recovery time [0..28 Tcpu]	   */ \
+			(((Tcpu)/4) << FShft (MSC_RRR))
+#define MSC_CeilRec(Tcpu)		/*  Ceil. of Rec [0..28 Tcpu]	   */ \
+			((((Tcpu) + 3)/4) << FShft (MSC_RRR))
+
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) control
+ * register
+ *
+ * Register
+ *    MECR		Memory system: Expansion memory bus (PCMCIA)
+ *			Configuration Register (read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fbclk, Tbclk	Frequency, period of the PCMCIA clock (BCLK).
+ */
+
+					/* Memory system:		   */
+#define _MECR		0xA0000018	/*  Expansion memory bus (PCMCIA)  */
+					/*  Configuration Reg.		   */
+
+#if LANGUAGE == C
+					/* Memory system:		   */
+#define MECR				/*  Expansion memory bus (PCMCIA)  */ \
+					/*  Configuration Reg.		   */ \
+			(*((volatile Word *) io_p2v (_MECR)))
+#endif /* LANGUAGE == C */
+
+#define MECR_PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
+			Fld (15, (Nb)*16)
+#define MECR_PCMCIA0	MECR_PCMCIA (0)	/* PCMCIA 0			   */
+#define MECR_PCMCIA1	MECR_PCMCIA (1)	/* PCMCIA 1			   */
+
+#define MECR_BSIO	Fld (5, 0)	/* BCLK Select I/O - 1 [Tmem]	   */
+#define MECR_IOClk(Tcpu)		/*  I/O Clock [2..64 Tcpu]	   */ \
+			((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
+#define MECR_CeilIOClk(Tcpu)		/*  Ceil. of IOClk [2..64 Tcpu]    */ \
+			((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
+#define MECR_BSA	Fld (5, 5)	/* BCLK Select Attribute - 1	   */
+					/* [Tmem]			   */
+#define MECR_AttrClk(Tcpu)		/*  Attribute Clock [2..64 Tcpu]   */ \
+			((((Tcpu) - 2)/2) << FShft (MECR_BSA))
+#define MECR_CeilAttrClk(Tcpu)		/*  Ceil. of AttrClk [2..64 Tcpu]  */ \
+			((((Tcpu) - 1)/2) << FShft (MECR_BSA))
+#define MECR_BSM	Fld (5, 10)	/* BCLK Select Memory - 1 [Tmem]   */
+#define MECR_MemClk(Tcpu)		/*  Memory Clock [2..64 Tcpu]	   */ \
+			((((Tcpu) - 2)/2) << FShft (MECR_BSM))
+#define MECR_CeilMemClk(Tcpu)		/*  Ceil. of MemClk [2..64 Tcpu]   */ \
+			((((Tcpu) - 1)/2) << FShft (MECR_BSM))
+
+/*
+ * On SA1110 only
+ */
+
+#define _MDREFR		0xA000001C
+
+#if LANGUAGE == C
+					/* Memory system:		   */
+#define MDREFR \
+			(*((volatile Word *) io_p2v (_MDREFR)))
+
+#elif LANGUAGE == Assembly
+
+#define MDREFR		(io_p2v(_MDREFR))
+
+#endif /* LANGUAGE == C */
+
+#define MDREFR_TRASR		Fld (4, 0)
+#define MDREFR_DRI		Fld (12, 4)
+#define MDREFR_E0PIN		(1 << 16)
+#define MDREFR_K0RUN		(1 << 17)
+#define MDREFR_K0DB2		(1 << 18)
+#define MDREFR_E1PIN		(1 << 20)
+#define MDREFR_K1RUN		(1 << 21)
+#define MDREFR_K1DB2		(1 << 22)
+#define MDREFR_K2RUN		(1 << 25)
+#define MDREFR_K2DB2		(1 << 26)
+#define MDREFR_EAPD		(1 << 28)
+#define MDREFR_KAPD		(1 << 29)
+#define MDREFR_SLFRSH		(1 << 31)
+
+
+/*
+ * Direct Memory Access (DMA) control registers
+ *
+ * Registers
+ *    DDAR0		Direct Memory Access (DMA) Device Address Register
+ *			channel 0 (read/write).
+ *    DCSR0		Direct Memory Access (DMA) Control and Status
+ *			Register channel 0 (read/write).
+ *    DBSA0		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 0 (read/write).
+ *    DBTA0		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 0 (read/write).
+ *    DBSB0		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 0 (read/write).
+ *    DBTB0		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 0 (read/write).
+ *
+ *    DDAR1		Direct Memory Access (DMA) Device Address Register
+ *			channel 1 (read/write).
+ *    DCSR1		Direct Memory Access (DMA) Control and Status
+ *			Register channel 1 (read/write).
+ *    DBSA1		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 1 (read/write).
+ *    DBTA1		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 1 (read/write).
+ *    DBSB1		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 1 (read/write).
+ *    DBTB1		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 1 (read/write).
+ *
+ *    DDAR2		Direct Memory Access (DMA) Device Address Register
+ *			channel 2 (read/write).
+ *    DCSR2		Direct Memory Access (DMA) Control and Status
+ *			Register channel 2 (read/write).
+ *    DBSA2		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 2 (read/write).
+ *    DBTA2		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 2 (read/write).
+ *    DBSB2		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 2 (read/write).
+ *    DBTB2		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 2 (read/write).
+ *
+ *    DDAR3		Direct Memory Access (DMA) Device Address Register
+ *			channel 3 (read/write).
+ *    DCSR3		Direct Memory Access (DMA) Control and Status
+ *			Register channel 3 (read/write).
+ *    DBSA3		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 3 (read/write).
+ *    DBTA3		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 3 (read/write).
+ *    DBSB3		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 3 (read/write).
+ *    DBTB3		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 3 (read/write).
+ *
+ *    DDAR4		Direct Memory Access (DMA) Device Address Register
+ *			channel 4 (read/write).
+ *    DCSR4		Direct Memory Access (DMA) Control and Status
+ *			Register channel 4 (read/write).
+ *    DBSA4		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 4 (read/write).
+ *    DBTA4		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 4 (read/write).
+ *    DBSB4		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 4 (read/write).
+ *    DBTB4		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 4 (read/write).
+ *
+ *    DDAR5		Direct Memory Access (DMA) Device Address Register
+ *			channel 5 (read/write).
+ *    DCSR5		Direct Memory Access (DMA) Control and Status
+ *			Register channel 5 (read/write).
+ *    DBSA5		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 5 (read/write).
+ *    DBTA5		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 5 (read/write).
+ *    DBSB5		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 5 (read/write).
+ *    DBTB5		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 5 (read/write).
+ */
+
+#define DMASp		0x00000020	/* DMA control reg. Space [byte]   */
+
+#define _DDAR(Nb)			/* DMA Device Address Reg.	   */ \
+					/* channel [0..5]		   */ \
+			(0xB0000000 + (Nb)*DMASp)
+#define _SetDCSR(Nb)			/* Set DMA Control & Status Reg.   */ \
+					/* channel [0..5] (write)	   */ \
+			(0xB0000004 + (Nb)*DMASp)
+#define _ClrDCSR(Nb)			/* Clear DMA Control & Status Reg. */ \
+					/* channel [0..5] (write)	   */ \
+			(0xB0000008 + (Nb)*DMASp)
+#define _RdDCSR(Nb)			/* Read DMA Control & Status Reg.  */ \
+					/* channel [0..5] (read)	   */ \
+			(0xB000000C + (Nb)*DMASp)
+#define _DBSA(Nb)			/* DMA Buffer Start address reg. A */ \
+					/* channel [0..5]		   */ \
+			(0xB0000010 + (Nb)*DMASp)
+#define _DBTA(Nb)			/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel [0..5]	   */ \
+			(0xB0000014 + (Nb)*DMASp)
+#define _DBSB(Nb)			/* DMA Buffer Start address reg. B */ \
+					/* channel [0..5]		   */ \
+			(0xB0000018 + (Nb)*DMASp)
+#define _DBTB(Nb)			/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel [0..5]	   */ \
+			(0xB000001C + (Nb)*DMASp)
+
+#define _DDAR0		_DDAR (0)	/* DMA Device Address Reg.	   */
+					/* channel 0			   */
+#define _SetDCSR0	_SetDCSR (0)	/* Set DMA Control & Status Reg.   */
+					/* channel 0 (write)		   */
+#define _ClrDCSR0	_ClrDCSR (0)	/* Clear DMA Control & Status Reg. */
+					/* channel 0 (write)		   */
+#define _RdDCSR0	_RdDCSR (0)	/* Read DMA Control & Status Reg.  */
+					/* channel 0 (read)		   */
+#define _DBSA0		_DBSA (0)	/* DMA Buffer Start address reg. A */
+					/* channel 0			   */
+#define _DBTA0		_DBTA (0)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 0		   */
+#define _DBSB0		_DBSB (0)	/* DMA Buffer Start address reg. B */
+					/* channel 0			   */
+#define _DBTB0		_DBTB (0)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 0		   */
+
+#define _DDAR1		_DDAR (1)	/* DMA Device Address Reg.	   */
+					/* channel 1			   */
+#define _SetDCSR1	_SetDCSR (1)	/* Set DMA Control & Status Reg.   */
+					/* channel 1 (write)		   */
+#define _ClrDCSR1	_ClrDCSR (1)	/* Clear DMA Control & Status Reg. */
+					/* channel 1 (write)		   */
+#define _RdDCSR1	_RdDCSR (1)	/* Read DMA Control & Status Reg.  */
+					/* channel 1 (read)		   */
+#define _DBSA1		_DBSA (1)	/* DMA Buffer Start address reg. A */
+					/* channel 1			   */
+#define _DBTA1		_DBTA (1)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 1		   */
+#define _DBSB1		_DBSB (1)	/* DMA Buffer Start address reg. B */
+					/* channel 1			   */
+#define _DBTB1		_DBTB (1)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 1		   */
+
+#define _DDAR2		_DDAR (2)	/* DMA Device Address Reg.	   */
+					/* channel 2			   */
+#define _SetDCSR2	_SetDCSR (2)	/* Set DMA Control & Status Reg.   */
+					/* channel 2 (write)		   */
+#define _ClrDCSR2	_ClrDCSR (2)	/* Clear DMA Control & Status Reg. */
+					/* channel 2 (write)		   */
+#define _RdDCSR2	_RdDCSR (2)	/* Read DMA Control & Status Reg.  */
+					/* channel 2 (read)		   */
+#define _DBSA2		_DBSA (2)	/* DMA Buffer Start address reg. A */
+					/* channel 2			   */
+#define _DBTA2		_DBTA (2)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 2		   */
+#define _DBSB2		_DBSB (2)	/* DMA Buffer Start address reg. B */
+					/* channel 2			   */
+#define _DBTB2		_DBTB (2)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 2		   */
+
+#define _DDAR3		_DDAR (3)	/* DMA Device Address Reg.	   */
+					/* channel 3			   */
+#define _SetDCSR3	_SetDCSR (3)	/* Set DMA Control & Status Reg.   */
+					/* channel 3 (write)		   */
+#define _ClrDCSR3	_ClrDCSR (3)	/* Clear DMA Control & Status Reg. */
+					/* channel 3 (write)		   */
+#define _RdDCSR3	_RdDCSR (3)	/* Read DMA Control & Status Reg.  */
+					/* channel 3 (read)		   */
+#define _DBSA3		_DBSA (3)	/* DMA Buffer Start address reg. A */
+					/* channel 3			   */
+#define _DBTA3		_DBTA (3)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 3		   */
+#define _DBSB3		_DBSB (3)	/* DMA Buffer Start address reg. B */
+					/* channel 3			   */
+#define _DBTB3		_DBTB (3)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 3		   */
+
+#define _DDAR4		_DDAR (4)	/* DMA Device Address Reg.	   */
+					/* channel 4			   */
+#define _SetDCSR4	_SetDCSR (4)	/* Set DMA Control & Status Reg.   */
+					/* channel 4 (write)		   */
+#define _ClrDCSR4	_ClrDCSR (4)	/* Clear DMA Control & Status Reg. */
+					/* channel 4 (write)		   */
+#define _RdDCSR4	_RdDCSR (4)	/* Read DMA Control & Status Reg.  */
+					/* channel 4 (read)		   */
+#define _DBSA4		_DBSA (4)	/* DMA Buffer Start address reg. A */
+					/* channel 4			   */
+#define _DBTA4		_DBTA (4)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 4		   */
+#define _DBSB4		_DBSB (4)	/* DMA Buffer Start address reg. B */
+					/* channel 4			   */
+#define _DBTB4		_DBTB (4)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 4		   */
+
+#define _DDAR5		_DDAR (5)	/* DMA Device Address Reg.	   */
+					/* channel 5			   */
+#define _SetDCSR5	_SetDCSR (5)	/* Set DMA Control & Status Reg.   */
+					/* channel 5 (write)		   */
+#define _ClrDCSR5	_ClrDCSR (5)	/* Clear DMA Control & Status Reg. */
+					/* channel 5 (write)		   */
+#define _RdDCSR5	_RdDCSR (5)	/* Read DMA Control & Status Reg.  */
+					/* channel 5 (read)		   */
+#define _DBSA5		_DBSA (5)	/* DMA Buffer Start address reg. A */
+					/* channel 5			   */
+#define _DBTA5		_DBTA (5)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 5		   */
+#define _DBSB5		_DBSB (5)	/* DMA Buffer Start address reg. B */
+					/* channel 5			   */
+#define _DBTB5		_DBTB (5)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 5		   */
+
+#if LANGUAGE == C
+
+#define DDAR0				/* DMA Device Address Reg.	   */ \
+					/* channel 0			   */ \
+			(*((volatile Word *) io_p2v (_DDAR0)))
+#define SetDCSR0			/* Set DMA Control & Status Reg.   */ \
+					/* channel 0 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR0)))
+#define ClrDCSR0			/* Clear DMA Control & Status Reg. */ \
+					/* channel 0 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR0)))
+#define RdDCSR0				/* Read DMA Control & Status Reg.  */ \
+					/* channel 0 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR0)))
+#define DBSA0				/* DMA Buffer Start address reg. A */ \
+					/* channel 0			   */ \
+			(*((volatile Address *) io_p2v (_DBSA0)))
+#define DBTA0				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 0		   */ \
+			(*((volatile Word *) io_p2v (_DBTA0)))
+#define DBSB0				/* DMA Buffer Start address reg. B */ \
+					/* channel 0			   */ \
+			(*((volatile Address *) io_p2v (_DBSB0)))
+#define DBTB0				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 0		   */ \
+			(*((volatile Word *) io_p2v (_DBTB0)))
+
+#define DDAR1				/* DMA Device Address Reg.	   */ \
+					/* channel 1			   */ \
+			(*((volatile Word *) io_p2v (_DDAR1)))
+#define SetDCSR1			/* Set DMA Control & Status Reg.   */ \
+					/* channel 1 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR1)))
+#define ClrDCSR1			/* Clear DMA Control & Status Reg. */ \
+					/* channel 1 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR1)))
+#define RdDCSR1				/* Read DMA Control & Status Reg.  */ \
+					/* channel 1 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR1)))
+#define DBSA1				/* DMA Buffer Start address reg. A */ \
+					/* channel 1			   */ \
+			(*((volatile Address *) io_p2v (_DBSA1)))
+#define DBTA1				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 1		   */ \
+			(*((volatile Word *) io_p2v (_DBTA1)))
+#define DBSB1				/* DMA Buffer Start address reg. B */ \
+					/* channel 1			   */ \
+			(*((volatile Address *) io_p2v (_DBSB1)))
+#define DBTB1				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 1		   */ \
+			(*((volatile Word *) io_p2v (_DBTB1)))
+
+#define DDAR2				/* DMA Device Address Reg.	   */ \
+					/* channel 2			   */ \
+			(*((volatile Word *) io_p2v (_DDAR2)))
+#define SetDCSR2			/* Set DMA Control & Status Reg.   */ \
+					/* channel 2 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR2)))
+#define ClrDCSR2			/* Clear DMA Control & Status Reg. */ \
+					/* channel 2 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR2)))
+#define RdDCSR2				/* Read DMA Control & Status Reg.  */ \
+					/* channel 2 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR2)))
+#define DBSA2				/* DMA Buffer Start address reg. A */ \
+					/* channel 2			   */ \
+			(*((volatile Address *) io_p2v (_DBSA2)))
+#define DBTA2				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 2		   */ \
+			(*((volatile Word *) io_p2v (_DBTA2)))
+#define DBSB2				/* DMA Buffer Start address reg. B */ \
+					/* channel 2			   */ \
+			(*((volatile Address *) io_p2v (_DBSB2)))
+#define DBTB2				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 2		   */ \
+			(*((volatile Word *) io_p2v (_DBTB2)))
+
+#define DDAR3				/* DMA Device Address Reg.	   */ \
+					/* channel 3			   */ \
+			(*((volatile Word *) io_p2v (_DDAR3)))
+#define SetDCSR3			/* Set DMA Control & Status Reg.   */ \
+					/* channel 3 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR3)))
+#define ClrDCSR3			/* Clear DMA Control & Status Reg. */ \
+					/* channel 3 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR3)))
+#define RdDCSR3				/* Read DMA Control & Status Reg.  */ \
+					/* channel 3 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR3)))
+#define DBSA3				/* DMA Buffer Start address reg. A */ \
+					/* channel 3			   */ \
+			(*((volatile Address *) io_p2v (_DBSA3)))
+#define DBTA3				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 3		   */ \
+			(*((volatile Word *) io_p2v (_DBTA3)))
+#define DBSB3				/* DMA Buffer Start address reg. B */ \
+					/* channel 3			   */ \
+			(*((volatile Address *) io_p2v (_DBSB3)))
+#define DBTB3				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 3		   */ \
+			(*((volatile Word *) io_p2v (_DBTB3)))
+
+#define DDAR4				/* DMA Device Address Reg.	   */ \
+					/* channel 4			   */ \
+			(*((volatile Word *) io_p2v (_DDAR4)))
+#define SetDCSR4			/* Set DMA Control & Status Reg.   */ \
+					/* channel 4 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR4)))
+#define ClrDCSR4			/* Clear DMA Control & Status Reg. */ \
+					/* channel 4 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR4)))
+#define RdDCSR4				/* Read DMA Control & Status Reg.  */ \
+					/* channel 4 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR4)))
+#define DBSA4				/* DMA Buffer Start address reg. A */ \
+					/* channel 4			   */ \
+			(*((volatile Address *) io_p2v (_DBSA4)))
+#define DBTA4				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 4		   */ \
+			(*((volatile Word *) io_p2v (_DBTA4)))
+#define DBSB4				/* DMA Buffer Start address reg. B */ \
+					/* channel 4			   */ \
+			(*((volatile Address *) io_p2v (_DBSB4)))
+#define DBTB4				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 4		   */ \
+			(*((volatile Word *) io_p2v (_DBTB4)))
+
+#define DDAR5				/* DMA Device Address Reg.	   */ \
+					/* channel 5			   */ \
+			(*((volatile Word *) io_p2v (_DDAR5)))
+#define SetDCSR5			/* Set DMA Control & Status Reg.   */ \
+					/* channel 5 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR5)))
+#define ClrDCSR5			/* Clear DMA Control & Status Reg. */ \
+					/* channel 5 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR5)))
+#define RdDCSR5				/* Read DMA Control & Status Reg.  */ \
+					/* channel 5 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR5)))
+#define DBSA5				/* DMA Buffer Start address reg. A */ \
+					/* channel 5			   */ \
+			(*((volatile Address *) io_p2v (_DBSA5)))
+#define DBTA5				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 5		   */ \
+			(*((volatile Word *) io_p2v (_DBTA5)))
+#define DBSB5				/* DMA Buffer Start address reg. B */ \
+					/* channel 5			   */ \
+			(*((volatile Address *) io_p2v (_DBSB5)))
+#define DBTB5				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 5		   */ \
+			(*((volatile Word *) io_p2v (_DBTB5)))
+
+#endif /* LANGUAGE == C */
+
+#define DDAR_RW		0x00000001	/* device data Read/Write	   */
+#define DDAR_DevWr	(DDAR_RW*0)	/*  Device data Write		   */
+					/*  (memory -> device)		   */
+#define DDAR_DevRd	(DDAR_RW*1)	/*  Device data Read		   */
+					/*  (device -> memory)		   */
+#define DDAR_E		0x00000002	/* big/little Endian device	   */
+#define DDAR_LtlEnd	(DDAR_E*0)	/*  Little Endian device	   */
+#define DDAR_BigEnd	(DDAR_E*1)	/*  Big Endian device		   */
+#define DDAR_BS		0x00000004	/* device Burst Size		   */
+#define DDAR_Brst4	(DDAR_BS*0)	/*  Burst-of-4 device		   */
+#define DDAR_Brst8	(DDAR_BS*1)	/*  Burst-of-8 device		   */
+#define DDAR_DW		0x00000008	/* device Data Width		   */
+#define DDAR_8BitDev	(DDAR_DW*0)	/*  8-Bit Device		   */
+#define DDAR_16BitDev	(DDAR_DW*1)	/*  16-Bit Device		   */
+#define DDAR_DS		Fld (4, 4)	/* Device Select		   */
+#define DDAR_Ser0UDCTr			/*  Ser. port 0 UDC Transmit	   */ \
+			(0x0 << FShft (DDAR_DS))
+#define DDAR_Ser0UDCRc			/*  Ser. port 0 UDC Receive	   */ \
+			(0x1 << FShft (DDAR_DS))
+#define DDAR_Ser1SDLCTr			/*  Ser. port 1 SDLC Transmit	   */ \
+			(0x2 << FShft (DDAR_DS))
+#define DDAR_Ser1SDLCRc			/*  Ser. port 1 SDLC Receive	   */ \
+			(0x3 << FShft (DDAR_DS))
+#define DDAR_Ser1UARTTr			/*  Ser. port 1 UART Transmit	   */ \
+			(0x4 << FShft (DDAR_DS))
+#define DDAR_Ser1UARTRc			/*  Ser. port 1 UART Receive	   */ \
+			(0x5 << FShft (DDAR_DS))
+#define DDAR_Ser2ICPTr			/*  Ser. port 2 ICP Transmit	   */ \
+			(0x6 << FShft (DDAR_DS))
+#define DDAR_Ser2ICPRc			/*  Ser. port 2 ICP Receive	   */ \
+			(0x7 << FShft (DDAR_DS))
+#define DDAR_Ser3UARTTr			/*  Ser. port 3 UART Transmit	   */ \
+			(0x8 << FShft (DDAR_DS))
+#define DDAR_Ser3UARTRc			/*  Ser. port 3 UART Receive	   */ \
+			(0x9 << FShft (DDAR_DS))
+#define DDAR_Ser4MCP0Tr			/*  Ser. port 4 MCP 0 Transmit	   */ \
+					/*  (audio)			   */ \
+			(0xA << FShft (DDAR_DS))
+#define DDAR_Ser4MCP0Rc			/*  Ser. port 4 MCP 0 Receive	   */ \
+					/*  (audio)			   */ \
+			(0xB << FShft (DDAR_DS))
+#define DDAR_Ser4MCP1Tr			/*  Ser. port 4 MCP 1 Transmit	   */ \
+					/*  (telecom)			   */ \
+			(0xC << FShft (DDAR_DS))
+#define DDAR_Ser4MCP1Rc			/*  Ser. port 4 MCP 1 Receive	   */ \
+					/*  (telecom)			   */ \
+			(0xD << FShft (DDAR_DS))
+#define DDAR_Ser4SSPTr			/*  Ser. port 4 SSP Transmit	   */ \
+			(0xE << FShft (DDAR_DS))
+#define DDAR_Ser4SSPRc			/*  Ser. port 4 SSP Receive	   */ \
+			(0xF << FShft (DDAR_DS))
+#define DDAR_DA		Fld (24, 8)	/* Device Address		   */
+#define DDAR_DevAdd(Add)		/*  Device Address		   */ \
+			(((Add) & 0xF0000000) | \
+			 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
+#define DDAR_Ser0UDCWr			/* Ser. port 0 UDC Write	   */ \
+			(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR))
+#define DDAR_Ser0UDCRd			/* Ser. port 0 UDC Read		   */ \
+			(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR))
+#define DDAR_Ser1UARTWr			/* Ser. port 1 UART Write	   */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR))
+#define DDAR_Ser1UARTRd			/* Ser. port 1 UART Read	   */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR))
+#define DDAR_Ser1SDLCWr			/* Ser. port 1 SDLC Write	   */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR))
+#define DDAR_Ser1SDLCRd			/* Ser. port 1 SDLC Read	   */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR))
+#define DDAR_Ser2UARTWr			/* Ser. port 2 UART Write	   */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR))
+#define DDAR_Ser2UARTRd			/* Ser. port 2 UART Read	   */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR))
+#define DDAR_Ser2HSSPWr			/* Ser. port 2 HSSP Write	   */ \
+			(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR))
+#define DDAR_Ser2HSSPRd			/* Ser. port 2 HSSP Read	   */ \
+			(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR))
+#define DDAR_Ser3UARTWr			/* Ser. port 3 UART Write	   */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR))
+#define DDAR_Ser3UARTRd			/* Ser. port 3 UART Read	   */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR))
+#define DDAR_Ser4MCP0Wr			/* Ser. port 4 MCP 0 Write (audio) */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0))
+#define DDAR_Ser4MCP0Rd			/* Ser. port 4 MCP 0 Read (audio)  */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0))
+#define DDAR_Ser4MCP1Wr			/* Ser. port 4 MCP 1 Write	   */ \
+					/* (telecom)			   */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1))
+#define DDAR_Ser4MCP1Rd			/* Ser. port 4 MCP 1 Read	   */ \
+					/* (telecom)			   */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1))
+#define DDAR_Ser4SSPWr			/* Ser. port 4 SSP Write (16 bits) */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR))
+#define DDAR_Ser4SSPRd			/* Ser. port 4 SSP Read (16 bits)  */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR))
+
+#define DCSR_RUN	0x00000001	/* DMA RUNing			   */
+#define DCSR_IE		0x00000002	/* DMA Interrupt Enable		   */
+#define DCSR_ERROR	0x00000004	/* DMA ERROR			   */
+#define DCSR_DONEA	0x00000008	/* DONE DMA transfer buffer A	   */
+#define DCSR_STRTA	0x00000010	/* STaRTed DMA transfer buffer A   */
+#define DCSR_DONEB	0x00000020	/* DONE DMA transfer buffer B	   */
+#define DCSR_STRTB	0x00000040	/* STaRTed DMA transfer buffer B   */
+#define DCSR_BIU	0x00000080	/* DMA Buffer In Use		   */
+#define DCSR_BufA	(DCSR_BIU*0)	/*  DMA Buffer A in use		   */
+#define DCSR_BufB	(DCSR_BIU*1)	/*  DMA Buffer B in use		   */
+
+#define DBT_TC		Fld (13, 0)	/* Transfer Count		   */
+#define DBTA_TCA	DBT_TC		/* Transfer Count buffer A	   */
+#define DBTB_TCB	DBT_TC		/* Transfer Count buffer B	   */
+
+
+/*
+ * Liquid Crystal Display (LCD) control registers
+ *
+ * Registers
+ *    LCCR0		Liquid Crystal Display (LCD) Control Register 0
+ *			(read/write).
+ *			[Bits LDM, BAM, and ERM are only implemented in
+ *			versions 2.0 (rev. = 8) and higher of the StrongARM
+ *			SA-1100.]
+ *    LCSR		Liquid Crystal Display (LCD) Status Register
+ *			(read/write).
+ *			[Bit LDD can be only read in versions 1.0 (rev. = 1)
+ *			and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
+ *			read and written (cleared) in versions 2.0 (rev. = 8)
+ *			and higher.]
+ *    DBAR1		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Base Address Register channel 1 (read/write).
+ *    DCAR1		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Current Address Register channel 1 (read).
+ *    DBAR2		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Base Address Register channel 2 (read/write).
+ *    DCAR2		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Current Address Register channel 2 (read).
+ *    LCCR1		Liquid Crystal Display (LCD) Control Register 1
+ *			(read/write).
+ *			[The LCCR1 register can be only written in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it can be written and read in
+ *			versions 2.0 (rev. = 8) and higher.]
+ *    LCCR2		Liquid Crystal Display (LCD) Control Register 2
+ *			(read/write).
+ *			[The LCCR1 register can be only written in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it can be written and read in
+ *			versions 2.0 (rev. = 8) and higher.]
+ *    LCCR3		Liquid Crystal Display (LCD) Control Register 3
+ *			(read/write).
+ *			[The LCCR1 register can be only written in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it can be written and read in
+ *			versions 2.0 (rev. = 8) and higher. Bit PCP is only
+ *			implemented in versions 2.0 (rev. = 8) and higher of
+ *			the StrongARM SA-1100.]
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fpix, Tpix	Frequency, period of the pixel clock.
+ *    fln, Tln		Frequency, period of the line clock.
+ *    fac, Tac		Frequency, period of the AC bias clock.
+ */
+
+#define LCD_PEntrySp	2		/* LCD Palette Entry Space [byte]  */
+#define LCD_4BitPSp			/* LCD 4-Bit pixel Palette Space   */ \
+					/* [byte]			   */ \
+			(16*LCD_PEntrySp)
+#define LCD_8BitPSp			/* LCD 8-Bit pixel Palette Space   */ \
+					/* [byte]			   */ \
+			(256*LCD_PEntrySp)
+#define LCD_12_16BitPSp			/* LCD 12/16-Bit pixel		   */ \
+					/* dummy-Palette Space [byte]	   */ \
+			(16*LCD_PEntrySp)
+
+#define LCD_PGrey	Fld (4, 0)	/* LCD Palette entry Grey value    */
+#define LCD_PBlue	Fld (4, 0)	/* LCD Palette entry Blue value    */
+#define LCD_PGreen	Fld (4, 4)	/* LCD Palette entry Green value   */
+#define LCD_PRed	Fld (4, 8)	/* LCD Palette entry Red value	   */
+#define LCD_PBS		Fld (2, 12)	/* LCD Pixel Bit Size		   */
+#define LCD_4Bit			/*  LCD 4-Bit pixel mode	   */ \
+			(0 << FShft (LCD_PBS))
+#define LCD_8Bit			/*  LCD 8-Bit pixel mode	   */ \
+			(1 << FShft (LCD_PBS))
+#define LCD_12_16Bit			/*  LCD 12/16-Bit pixel mode	   */ \
+			(2 << FShft (LCD_PBS))
+
+#define LCD_Int0_0	0x0		/* LCD Intensity =   0.0% =  0	   */
+#define LCD_Int11_1	0x1		/* LCD Intensity =  11.1% =  1/9   */
+#define LCD_Int20_0	0x2		/* LCD Intensity =  20.0% =  1/5   */
+#define LCD_Int26_7	0x3		/* LCD Intensity =  26.7% =  4/15  */
+#define LCD_Int33_3	0x4		/* LCD Intensity =  33.3% =  3/9   */
+#define LCD_Int40_0	0x5		/* LCD Intensity =  40.0% =  2/5   */
+#define LCD_Int44_4	0x6		/* LCD Intensity =  44.4% =  4/9   */
+#define LCD_Int50_0	0x7		/* LCD Intensity =  50.0% =  1/2   */
+#define LCD_Int55_6	0x8		/* LCD Intensity =  55.6% =  5/9   */
+#define LCD_Int60_0	0x9		/* LCD Intensity =  60.0% =  3/5   */
+#define LCD_Int66_7	0xA		/* LCD Intensity =  66.7% =  6/9   */
+#define LCD_Int73_3	0xB		/* LCD Intensity =  73.3% = 11/15  */
+#define LCD_Int80_0	0xC		/* LCD Intensity =  80.0% =  4/5   */
+#define LCD_Int88_9	0xD		/* LCD Intensity =  88.9% =  8/9   */
+#define LCD_Int100_0	0xE		/* LCD Intensity = 100.0% =  1	   */
+#define LCD_Int100_0A	0xF		/* LCD Intensity = 100.0% =  1	   */
+					/* (Alternative)		   */
+
+#define _LCCR0		0xB0100000	/* LCD Control Reg. 0		   */
+#define _LCSR		0xB0100004	/* LCD Status Reg.		   */
+#define _DBAR1		0xB0100010	/* LCD DMA Base Address Reg.	   */
+					/* channel 1			   */
+#define _DCAR1		0xB0100014	/* LCD DMA Current Address Reg.    */
+					/* channel 1			   */
+#define _DBAR2		0xB0100018	/* LCD DMA Base Address Reg.	   */
+					/* channel 2			   */
+#define _DCAR2		0xB010001C	/* LCD DMA Current Address Reg.    */
+					/* channel 2			   */
+#define _LCCR1		0xB0100020	/* LCD Control Reg. 1		   */
+#define _LCCR2		0xB0100024	/* LCD Control Reg. 2		   */
+#define _LCCR3		0xB0100028	/* LCD Control Reg. 3		   */
+
+#if LANGUAGE == C
+#define LCCR0				/* LCD Control Reg. 0		   */ \
+			(*((volatile Word *) io_p2v (_LCCR0)))
+#define LCSR				/* LCD Status Reg.		   */ \
+			(*((volatile Word *) io_p2v (_LCSR)))
+#define DBAR1				/* LCD DMA Base Address Reg.	   */ \
+					/* channel 1			   */ \
+			(*((volatile Address *) io_p2v (_DBAR1)))
+#define DCAR1				/* LCD DMA Current Address Reg.    */ \
+					/* channel 1			   */ \
+			(*((volatile Address *) io_p2v (_DCAR1)))
+#define DBAR2				/* LCD DMA Base Address Reg.	   */ \
+					/* channel 2			   */ \
+			(*((volatile Address *) io_p2v (_DBAR2)))
+#define DCAR2				/* LCD DMA Current Address Reg.    */ \
+					/* channel 2			   */ \
+			(*((volatile Address *) io_p2v (_DCAR2)))
+#define LCCR1				/* LCD Control Reg. 1		   */ \
+			(*((volatile Word *) io_p2v (_LCCR1)))
+#define LCCR2				/* LCD Control Reg. 2		   */ \
+			(*((volatile Word *) io_p2v (_LCCR2)))
+#define LCCR3				/* LCD Control Reg. 3		   */ \
+			(*((volatile Word *) io_p2v (_LCCR3)))
+#endif /* LANGUAGE == C */
+
+#define LCCR0_LEN	0x00000001	/* LCD ENable			   */
+#define LCCR0_CMS	0x00000002	/* Color/Monochrome display Select */
+#define LCCR0_Color	(LCCR0_CMS*0)	/*  Color display		   */
+#define LCCR0_Mono	(LCCR0_CMS*1)	/*  Monochrome display		   */
+#define LCCR0_SDS	0x00000004	/* Single/Dual panel display	   */
+					/* Select			   */
+#define LCCR0_Sngl	(LCCR0_SDS*0)	/*  Single panel display	   */
+#define LCCR0_Dual	(LCCR0_SDS*1)	/*  Dual panel display		   */
+#define LCCR0_LDM	0x00000008	/* LCD Disable done (LDD)	   */
+					/* interrupt Mask (disable)	   */
+#define LCCR0_BAM	0x00000010	/* Base Address update (BAU)	   */
+					/* interrupt Mask (disable)	   */
+#define LCCR0_ERM	0x00000020	/* LCD ERror (BER, IOL, IUL, IOU,  */
+					/* IUU, OOL, OUL, OOU, and OUU)    */
+					/* interrupt Mask (disable)	   */
+#define LCCR0_PAS	0x00000080	/* Passive/Active display Select   */
+#define LCCR0_Pas	(LCCR0_PAS*0)	/*  Passive display (STN)	   */
+#define LCCR0_Act	(LCCR0_PAS*1)	/*  Active display (TFT)	   */
+#define LCCR0_BLE	0x00000100	/* Big/Little Endian select	   */
+#define LCCR0_LtlEnd	(LCCR0_BLE*0)	/*  Little Endian frame buffer	   */
+#define LCCR0_BigEnd	(LCCR0_BLE*1)	/*  Big Endian frame buffer	   */
+#define LCCR0_DPD	0x00000200	/* Double Pixel Data (monochrome   */
+					/* display mode)		   */
+#define LCCR0_4PixMono	(LCCR0_DPD*0)	/*  4-Pixel/clock Monochrome	   */
+					/*  display			   */
+#define LCCR0_8PixMono	(LCCR0_DPD*1)	/*  8-Pixel/clock Monochrome	   */
+					/*  display			   */
+#define LCCR0_PDD	Fld (8, 12)	/* Palette DMA request Delay	   */
+					/* [Tmem]			   */
+#define LCCR0_DMADel(Tcpu)		/*  palette DMA request Delay	   */ \
+					/*  [0..510 Tcpu]		   */ \
+			((Tcpu)/2 << FShft (LCCR0_PDD))
+
+#define LCSR_LDD	0x00000001	/* LCD Disable Done		   */
+#define LCSR_BAU	0x00000002	/* Base Address Update (read)	   */
+#define LCSR_BER	0x00000004	/* Bus ERror			   */
+#define LCSR_ABC	0x00000008	/* AC Bias clock Count		   */
+#define LCSR_IOL	0x00000010	/* Input FIFO Over-run Lower	   */
+					/* panel			   */
+#define LCSR_IUL	0x00000020	/* Input FIFO Under-run Lower	   */
+					/* panel			   */
+#define LCSR_IOU	0x00000040	/* Input FIFO Over-run Upper	   */
+					/* panel			   */
+#define LCSR_IUU	0x00000080	/* Input FIFO Under-run Upper	   */
+					/* panel			   */
+#define LCSR_OOL	0x00000100	/* Output FIFO Over-run Lower	   */
+					/* panel			   */
+#define LCSR_OUL	0x00000200	/* Output FIFO Under-run Lower	   */
+					/* panel			   */
+#define LCSR_OOU	0x00000400	/* Output FIFO Over-run Upper	   */
+					/* panel			   */
+#define LCSR_OUU	0x00000800	/* Output FIFO Under-run Upper	   */
+					/* panel			   */
+
+#define LCCR1_PPL	Fld (6, 4)	/* Pixels Per Line/16 - 1	   */
+#define LCCR1_DisWdth(Pixel)		/*  Display Width [16..1024 pix.]  */ \
+			(((Pixel) - 16)/16 << FShft (LCCR1_PPL))
+#define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization	   */
+					/* pulse Width - 2 [Tpix] (L_LCLK) */
+#define LCCR1_HorSnchWdth(Tpix)		/*  Horizontal Synchronization	   */ \
+					/*  pulse Width [2..65 Tpix]	   */ \
+			(((Tpix) - 2) << FShft (LCCR1_HSW))
+#define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait    */
+					/* count - 1 [Tpix]		   */
+#define LCCR1_EndLnDel(Tpix)		/*  End-of-Line Delay		   */ \
+					/*  [1..256 Tpix]		   */ \
+			(((Tpix) - 1) << FShft (LCCR1_ELW))
+#define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock   */
+					/* Wait count - 1 [Tpix]	   */
+#define LCCR1_BegLnDel(Tpix)		/*  Beginning-of-Line Delay	   */ \
+					/*  [1..256 Tpix]		   */ \
+			(((Tpix) - 1) << FShft (LCCR1_BLW))
+
+#define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1		   */
+#define LCCR2_DisHght(Line)		/*  Display Height [1..1024 lines] */ \
+			(((Line) - 1) << FShft (LCCR2_LPP))
+#define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse  */
+					/* Width - 1 [Tln] (L_FCLK)	   */
+#define LCCR2_VrtSnchWdth(Tln)		/*  Vertical Synchronization pulse */ \
+					/*  Width [1..64 Tln]		   */ \
+			(((Tln) - 1) << FShft (LCCR2_VSW))
+#define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait    */
+					/* count [Tln]			   */
+#define LCCR2_EndFrmDel(Tln)		/*  End-of-Frame Delay		   */ \
+					/*  [0..255 Tln]		   */ \
+			((Tln) << FShft (LCCR2_EFW))
+#define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock   */
+					/* Wait count [Tln]		   */
+#define LCCR2_BegFrmDel(Tln)		/*  Beginning-of-Frame Delay	   */ \
+					/*  [0..255 Tln]		   */ \
+			((Tln) << FShft (LCCR2_BFW))
+
+#define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor/2 - 2	   */
+					/* [1..255] (L_PCLK)		   */
+					/* fpix = fcpu/(2*(PCD + 2))	   */
+					/* Tpix = 2*(PCD + 2)*Tcpu	   */
+#define LCCR3_PixClkDiv(Div)		/*  Pixel Clock Divisor [6..514]   */ \
+			(((Div) - 4)/2 << FShft (LCCR3_PCD))
+					/*  fpix = fcpu/(2*Floor (Div/2))  */
+					/*  Tpix = 2*Floor (Div/2)*Tcpu    */
+#define LCCR3_CeilPixClkDiv(Div)	/*  Ceil. of PixClkDiv [6..514]    */ \
+			(((Div) - 3)/2 << FShft (LCCR3_PCD))
+					/*  fpix = fcpu/(2*Ceil (Div/2))   */
+					/*  Tpix = 2*Ceil (Div/2)*Tcpu	   */
+#define LCCR3_ACB	Fld (8, 8)	/* AC Bias clock half period - 1   */
+					/* [Tln] (L_BIAS)		   */
+#define LCCR3_ACBsDiv(Div)		/*  AC Bias clock Divisor [2..512] */ \
+			(((Div) - 2)/2 << FShft (LCCR3_ACB))
+					/*  fac = fln/(2*Floor (Div/2))    */
+					/*  Tac = 2*Floor (Div/2)*Tln	   */
+#define LCCR3_CeilACBsDiv(Div)		/*  Ceil. of ACBsDiv [2..512]	   */ \
+			(((Div) - 1)/2 << FShft (LCCR3_ACB))
+					/*  fac = fln/(2*Ceil (Div/2))	   */
+					/*  Tac = 2*Ceil (Div/2)*Tln	   */
+#define LCCR3_API	Fld (4, 16)	/* AC bias Pin transitions per	   */
+					/* Interrupt			   */
+#define LCCR3_ACBsCntOff		/*  AC Bias clock transition Count */ \
+					/*  Off				   */ \
+			(0 << FShft (LCCR3_API))
+#define LCCR3_ACBsCnt(Trans)		/*  AC Bias clock transition Count */ \
+					/*  [1..15]			   */ \
+			((Trans) << FShft (LCCR3_API))
+#define LCCR3_VSP	0x00100000	/* Vertical Synchronization pulse  */
+					/* Polarity (L_FCLK)		   */
+#define LCCR3_VrtSnchH	(LCCR3_VSP*0)	/*  Vertical Synchronization pulse */
+					/*  active High			   */
+#define LCCR3_VrtSnchL	(LCCR3_VSP*1)	/*  Vertical Synchronization pulse */
+					/*  active Low			   */
+#define LCCR3_HSP	0x00200000	/* Horizontal Synchronization	   */
+					/* pulse Polarity (L_LCLK)	   */
+#define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  Horizontal Synchronization	   */
+					/*  pulse active High		   */
+#define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  Horizontal Synchronization	   */
+					/*  pulse active Low		   */
+#define LCCR3_PCP	0x00400000	/* Pixel Clock Polarity (L_PCLK)   */
+#define LCCR3_PixRsEdg	(LCCR3_PCP*0)	/*  Pixel clock Rising-Edge	   */
+#define LCCR3_PixFlEdg	(LCCR3_PCP*1)	/*  Pixel clock Falling-Edge	   */
+#define LCCR3_OEP	0x00800000	/* Output Enable Polarity (L_BIAS, */
+					/* active display mode)		   */
+#define LCCR3_OutEnH	(LCCR3_OEP*0)	/*  Output Enable active High	   */
+#define LCCR3_OutEnL	(LCCR3_OEP*1)	/*  Output Enable active Low	   */
+
+
+#undef C
+#undef Assembly
diff --git a/include/_exports.h b/include/_exports.h
new file mode 100644
index 0000000..0dee05f
--- /dev/null
+++ b/include/_exports.h
@@ -0,0 +1,86 @@
+/*
+ * You need to use #ifdef around functions that may not exist
+ * in the final configuration (such as i2c).
+ * use a dummyfunction as first parameter to EXPORT_FUNC.
+ * As an example see the CONFIG_CMD_I2C section below
+ */
+#ifndef EXPORT_FUNC
+#define EXPORT_FUNC(a, b, c, ...)
+#endif
+	EXPORT_FUNC(get_version, unsigned long, get_version, void)
+	EXPORT_FUNC(getc, int, getc, void)
+	EXPORT_FUNC(tstc, int, tstc, void)
+	EXPORT_FUNC(putc, void, putc, const char)
+	EXPORT_FUNC(puts, void, puts, const char *)
+	EXPORT_FUNC(printf, int, printf, const char*, ...)
+#if (defined(CONFIG_X86) && !defined(CONFIG_X86_64)) || defined(CONFIG_PPC)
+	EXPORT_FUNC(irq_install_handler, void, install_hdlr,
+		    int, interrupt_handler_t, void*)
+
+	EXPORT_FUNC(irq_free_handler, void, free_hdlr, int)
+#else
+	EXPORT_FUNC(dummy, void, install_hdlr, void)
+	EXPORT_FUNC(dummy, void, free_hdlr, void)
+#endif
+	EXPORT_FUNC(malloc, void *, malloc, size_t)
+#if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE)
+	EXPORT_FUNC(free, void, free, void *)
+#endif
+	EXPORT_FUNC(udelay, void, udelay, unsigned long)
+	EXPORT_FUNC(get_timer, unsigned long, get_timer, unsigned long)
+	EXPORT_FUNC(vprintf, int, vprintf, const char *, va_list)
+	EXPORT_FUNC(do_reset, int, do_reset, cmd_tbl_t *,
+		    int , int , char * const [])
+	EXPORT_FUNC(env_get, char  *, env_get, const char*)
+	EXPORT_FUNC(env_set, int, env_set, const char *, const char *)
+	EXPORT_FUNC(simple_strtoul, unsigned long, simple_strtoul,
+		    const char *, char **, unsigned int)
+	EXPORT_FUNC(strict_strtoul, int, strict_strtoul,
+		    const char *, unsigned int , unsigned long *)
+	EXPORT_FUNC(simple_strtol, long, simple_strtol,
+		    const char *, char **, unsigned int)
+	EXPORT_FUNC(strcmp, int, strcmp, const char *cs, const char *ct)
+#if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C)
+	EXPORT_FUNC(i2c_write, int, i2c_write, uchar, uint, int , uchar * , int)
+	EXPORT_FUNC(i2c_read, int, i2c_read, uchar, uint, int , uchar * , int)
+#else
+	EXPORT_FUNC(dummy, void, i2c_write, void)
+	EXPORT_FUNC(dummy, void, i2c_read, void)
+#endif
+
+#if !defined(CONFIG_CMD_SPI) || defined(CONFIG_DM_SPI)
+	EXPORT_FUNC(dummy, void, spi_setup_slave, void)
+	EXPORT_FUNC(dummy, void, spi_free_slave, void)
+#else
+	EXPORT_FUNC(spi_setup_slave, struct spi_slave *, spi_setup_slave,
+		    unsigned int, unsigned int, unsigned int, unsigned int)
+	EXPORT_FUNC(spi_free_slave, void, spi_free_slave, struct spi_slave *)
+#endif
+#ifndef CONFIG_CMD_SPI
+	EXPORT_FUNC(dummy, void, spi_claim_bus, void)
+	EXPORT_FUNC(dummy, void, spi_release_bus, void)
+	EXPORT_FUNC(dummy, void, spi_xfer, void)
+#else
+	EXPORT_FUNC(spi_claim_bus, int, spi_claim_bus, struct spi_slave *)
+	EXPORT_FUNC(spi_release_bus, void, spi_release_bus, struct spi_slave *)
+	EXPORT_FUNC(spi_xfer, int, spi_xfer, struct spi_slave *,
+		    unsigned int, const void *, void *, unsigned long)
+#endif
+	EXPORT_FUNC(ustrtoul, unsigned long, ustrtoul,
+		    const char *, char **, unsigned int)
+	EXPORT_FUNC(ustrtoull, unsigned long long, ustrtoull,
+		    const char *, char **, unsigned int)
+	EXPORT_FUNC(strcpy, char *, strcpy, char *dest, const char *src)
+	EXPORT_FUNC(mdelay, void, mdelay, unsigned long msec)
+	EXPORT_FUNC(memset, void *, memset, void *, int, size_t)
+#ifdef CONFIG_PHY_AQUANTIA
+	EXPORT_FUNC(mdio_get_current_dev, struct mii_dev *,
+		    mdio_get_current_dev, void)
+	EXPORT_FUNC(phy_find_by_mask, struct phy_device *, phy_find_by_mask,
+		    struct mii_dev *bus, unsigned phy_mask,
+		    phy_interface_t interface)
+	EXPORT_FUNC(mdio_phydev_for_ethname, struct phy_device *,
+		    mdio_phydev_for_ethname, const char *ethname)
+	EXPORT_FUNC(miiphy_set_current_dev, int, miiphy_set_current_dev,
+		    const char *devname)
+#endif
diff --git a/include/acpi_s3.h b/include/acpi_s3.h
new file mode 100644
index 0000000..baa848d
--- /dev/null
+++ b/include/acpi_s3.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __ASM_ACPI_S3_H__
+#define __ASM_ACPI_S3_H__
+
+#define WAKEUP_BASE	0x600
+
+/* PM1_STATUS register */
+#define WAK_STS		(1 << 15)
+#define PCIEXPWAK_STS	(1 << 14)
+#define RTC_STS		(1 << 10)
+#define SLPBTN_STS	(1 << 9)
+#define PWRBTN_STS	(1 << 8)
+#define GBL_STS		(1 << 5)
+#define BM_STS		(1 << 4)
+#define TMR_STS		(1 << 0)
+
+/* PM1_CNT register */
+#define SLP_EN		(1 << 13)
+#define SLP_TYP_SHIFT	10
+#define SLP_TYP		(7 << SLP_TYP_SHIFT)
+#define SLP_TYP_S0	0
+#define SLP_TYP_S1	1
+#define SLP_TYP_S3	5
+#define SLP_TYP_S4	6
+#define SLP_TYP_S5	7
+
+/* Memory size reserved for S3 resume */
+#define S3_RESERVE_SIZE	0x1000
+
+#ifndef __ASSEMBLY__
+
+extern char __wakeup[];
+extern int __wakeup_size;
+
+enum acpi_sleep_state {
+	ACPI_S0,
+	ACPI_S1,
+	ACPI_S2,
+	ACPI_S3,
+	ACPI_S4,
+	ACPI_S5,
+};
+
+/**
+ * acpi_ss_string() - get ACPI-defined sleep state string
+ *
+ * @pm1_cnt:	ACPI-defined sleep state
+ * @return:	a pointer to the sleep state string.
+ */
+static inline char *acpi_ss_string(enum acpi_sleep_state state)
+{
+	char *ss_string[] = { "S0", "S1", "S2", "S3", "S4", "S5"};
+
+	return ss_string[state];
+}
+
+/**
+ * acpi_sleep_from_pm1() - get ACPI-defined sleep state from PM1_CNT register
+ *
+ * @pm1_cnt:	PM1_CNT register value
+ * @return:	ACPI-defined sleep state if given valid PM1_CNT register value,
+ *		-EINVAL otherwise.
+ */
+static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt)
+{
+	switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
+	case SLP_TYP_S0:
+		return ACPI_S0;
+	case SLP_TYP_S1:
+		return ACPI_S1;
+	case SLP_TYP_S3:
+		return ACPI_S3;
+	case SLP_TYP_S4:
+		return ACPI_S4;
+	case SLP_TYP_S5:
+		return ACPI_S5;
+	}
+
+	return -EINVAL;
+}
+
+/**
+ * chipset_prev_sleep_state() - Get chipset previous sleep state
+ *
+ * This returns chipset previous sleep state from ACPI registers.
+ * Platform codes must supply this routine in order to support ACPI S3.
+ *
+ * @return ACPI_S0/S1/S2/S3/S4/S5.
+ */
+enum acpi_sleep_state chipset_prev_sleep_state(void);
+
+/**
+ * chipset_clear_sleep_state() - Clear chipset sleep state
+ *
+ * This clears chipset sleep state in ACPI registers.
+ * Platform codes must supply this routine in order to support ACPI S3.
+ */
+void chipset_clear_sleep_state(void);
+
+struct acpi_fadt;
+/**
+ * acpi_resume() - Do ACPI S3 resume
+ *
+ * This calls U-Boot wake up assembly stub and jumps to OS's wake up vector.
+ *
+ * @fadt:	FADT table pointer in the ACPI table
+ * @return:	Never returns
+ */
+void acpi_resume(struct acpi_fadt *fadt);
+
+/**
+ * acpi_s3_reserve() - Reserve memory for ACPI S3 resume
+ *
+ * This copies memory where real mode interrupt handler stubs reside to the
+ * reserved place on the stack.
+ *
+ * This routine should be called by reserve_arch() before U-Boot is relocated
+ * when ACPI S3 resume is enabled.
+ *
+ * @return:	0 always
+ */
+int acpi_s3_reserve(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ACPI_S3_H__ */
diff --git a/include/adc.h b/include/adc.h
new file mode 100644
index 0000000..5841dfb
--- /dev/null
+++ b/include/adc.h
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ */
+
+#ifndef _ADC_H_
+#define _ADC_H_
+
+/* ADC_CHANNEL() - ADC channel bit mask, to select only required channels */
+#define ADC_CHANNEL(x)		(1 << x)
+
+/* The last possible selected channel with 32-bit mask */
+#define ADC_MAX_CHANNEL		31
+
+/**
+ * adc_data_format: define the ADC output data format, can be useful when
+ * the device's input Voltage range is bipolar.
+ * - ADC_DATA_FORMAT_BIN - binary offset
+ * - ADC_DATA_FORMAT_2S  - two's complement
+ *
+ * Note: Device's driver should fill the 'data_format' field of its uclass's
+ * platform data using one of the above data format types.
+ */
+enum adc_data_format {
+	ADC_DATA_FORMAT_BIN,
+	ADC_DATA_FORMAT_2S,
+};
+
+/**
+ * struct adc_channel - structure to hold channel conversion data.
+ * Useful to keep the result of a multi-channel conversion output.
+ *
+ * @id   - channel id
+ * @data - channel conversion data
+ */
+struct adc_channel {
+	int id;
+	unsigned int data;
+};
+
+/**
+ * struct adc_uclass_platdata - basic ADC info
+ *
+ * Note: The positive/negative reference Voltage is only a name and it doesn't
+ * provide an information about the value polarity. It is possible, for both
+ * values to be a negative or positive. For this purpose the uclass's platform
+ * data provides a bool fields: 'vdd/vss_supply_is_negative'. This is useful,
+ * since the regulator API returns only a positive Voltage values.
+ *
+ * To get the reference Voltage values with polarity, use functions:
+ * - adc_vdd_value()
+ * - adc_vss_value()
+ * Those are useful for some cases of ADC's references, e.g.:
+ * * Vdd: +3.3V; Vss: -3.3V -> 6.6 Vdiff
+ * * Vdd: +3.3V; Vss: +0.3V -> 3.0 Vdiff
+ * * Vdd: +3.3V; Vss:  0.0V -> 3.3 Vdiff
+ * The last one is usually standard and doesn't require the fdt polarity info.
+ *
+ * For more informations read binding info:
+ * - doc/device-tree-bindings/adc/adc.txt
+ *
+ * @data_mask              - conversion output data mask
+ * @data_timeout_us        - single channel conversion timeout
+ * @multidata_timeout_us   - multi channel conversion timeout
+ * @channel_mask           - bit mask of available channels [0:31]
+ * @vdd_supply             - positive reference Voltage supply (regulator)
+ * @vss_supply             - negative reference Voltage supply (regulator)
+ * @vdd_polarity_negative  - positive reference Voltage has negative polarity
+ * @vss_polarity_negative  - negative reference Voltage has negative polarity
+ * @vdd_microvolts         - positive reference Voltage value
+ * @vss_microvolts         - negative reference Voltage value
+ */
+struct adc_uclass_platdata {
+	int data_format;
+	unsigned int data_mask;
+	unsigned int data_timeout_us;
+	unsigned int multidata_timeout_us;
+	unsigned int channel_mask;
+	struct udevice *vdd_supply;
+	struct udevice *vss_supply;
+	bool vdd_polarity_negative;
+	bool vss_polarity_negative;
+	int vdd_microvolts;
+	int vss_microvolts;
+};
+
+/**
+ * struct adc_ops - ADC device operations for single/multi-channel operation.
+ */
+struct adc_ops {
+	/**
+	 * start_channel() - start conversion with its default parameters
+	 *                   for the given channel number.
+	 *
+	 * @dev:          ADC device to init
+	 * @channel:      analog channel number
+	 * @return:       0 if OK, -ve on error
+	 */
+	int (*start_channel)(struct udevice *dev, int channel);
+
+	/**
+	 * start_channels() - start conversion with its default parameters
+	 *                    for the channel numbers selected by the bit mask.
+	 *
+	 * This is optional, useful when the hardware supports multichannel
+	 * conversion by the single software trigger.
+	 *
+	 * @dev:          ADC device to init
+	 * @channel_mask: bit mask of selected analog channels
+	 * @return:       0 if OK, -ve on error
+	 */
+	int (*start_channels)(struct udevice *dev, unsigned int channel_mask);
+
+	/**
+	 * channel_data() - get conversion output data for the given channel.
+	 *
+	 * Note: The implementation of this function should only check, that
+	 * the conversion data is available at the call time. If the hardware
+	 * requires some delay to get the data, then this function should
+	 * return with -EBUSY value. The ADC API will call it in a loop,
+	 * until the data is available or the timeout expires. The maximum
+	 * timeout for this operation is defined by the field 'data_timeout_us'
+	 * in ADC uclasses platform data structure.
+	 *
+	 * @dev:          ADC device to trigger
+	 * @channel:      selected analog channel number
+	 * @data:         returned pointer to selected channel's output data
+	 * @return:       0 if OK, -EBUSY if busy, and other negative on error
+	 */
+	int (*channel_data)(struct udevice *dev, int channel,
+			    unsigned int *data);
+
+	/**
+	 * channels_data() - get conversion data for the selected channels.
+	 *
+	 * This is optional, useful when multichannel conversion is supported
+	 * by the hardware, by the single software trigger.
+	 *
+	 * For the proper implementation, please look at the 'Note' for the
+	 * above method. The only difference is in used timeout value, which
+	 * is defined by field 'multidata_timeout_us'.
+	 *
+	 * @dev:          ADC device to trigger
+	 * @channel_mask: bit mask of selected analog channels
+	 * @channels:     returned pointer to array of output data for channels
+	 *                selected by the given mask
+	 * @return:       0 if OK, -ve on error
+	 */
+	int (*channels_data)(struct udevice *dev, unsigned int channel_mask,
+			     struct adc_channel *channels);
+
+	/**
+	 * stop() - stop conversion of the given ADC device
+	 *
+	 * @dev:          ADC device to stop
+	 * @return:       0 if OK, -ve on error
+	 */
+	int (*stop)(struct udevice *dev);
+};
+
+/**
+ * adc_start_channel() - start conversion for given device/channel and exit.
+ *
+ * @dev:     ADC device
+ * @channel: analog channel number
+ * @return:  0 if OK, -ve on error
+ */
+int adc_start_channel(struct udevice *dev, int channel);
+
+/**
+ * adc_start_channels() - start conversion for given device/channels and exit.
+ *
+ * Note:
+ * To use this function, device must implement method: start_channels().
+ *
+ * @dev:          ADC device to start
+ * @channel_mask: channel selection - a bit mask
+ * @channel_mask: bit mask of analog channels
+ * @return:       0 if OK, -ve on error
+ */
+int adc_start_channels(struct udevice *dev, unsigned int channel_mask);
+
+/**
+ * adc_channel_data() - get conversion data for the given device channel number.
+ *
+ * @dev:     ADC device to read
+ * @channel: analog channel number
+ * @data:    pointer to returned channel's data
+ * @return:  0 if OK, -ve on error
+ */
+int adc_channel_data(struct udevice *dev, int channel, unsigned int *data);
+
+/**
+ * adc_channels_data() - get conversion data for the channels selected by mask
+ *
+ * Note:
+ * To use this function, device must implement methods:
+ * - start_channels()
+ * - channels_data()
+ *
+ * @dev:          ADC device to read
+ * @channel_mask: channel selection - a bit mask
+ * @channels:     pointer to structure array of returned data for each channel
+ * @return:       0 if OK, -ve on error
+ */
+int adc_channels_data(struct udevice *dev, unsigned int channel_mask,
+		      struct adc_channel *channels);
+
+/**
+ * adc_data_mask() - get data mask (ADC resolution bitmask) for given ADC device
+ *
+ * This can be used if adc uclass platform data is filled.
+ *
+ * @dev:       ADC device to check
+ * @data_mask: pointer to the returned data bitmask
+ * @return: 0 if OK, -ve on error
+ */
+int adc_data_mask(struct udevice *dev, unsigned int *data_mask);
+
+/**
+ * adc_channel_mask() - get channel mask for given ADC device
+ *
+ * This can be used if adc uclass platform data is filled.
+ *
+ * @dev:       ADC device to check
+ * @channel_mask: pointer to the returned channel bitmask
+ * @return: 0 if OK, -ve on error
+ */
+int adc_channel_mask(struct udevice *dev, unsigned int *channel_mask);
+
+/**
+ * adc_channel_single_shot() - get output data of conversion for the ADC
+ * device's channel. This function searches for the device with the given name,
+ * starts the given channel conversion and returns the output data.
+ *
+ * Note: To use this function, device must implement metods:
+ * - start_channel()
+ * - channel_data()
+ *
+ * @name:    device's name to search
+ * @channel: device's input channel to init
+ * @data:    pointer to conversion output data
+ * @return:  0 if OK, -ve on error
+ */
+int adc_channel_single_shot(const char *name, int channel, unsigned int *data);
+
+/**
+ * adc_channels_single_shot() - get ADC conversion output data for the selected
+ * device's channels. This function searches for the device by the given name,
+ * starts the selected channels conversion and returns the output data as array
+ * of type 'struct adc_channel'.
+ *
+ * Note: This function can be used if device implements one of ADC's single
+ * or multi-channel operation API. If multi-channel operation is not supported,
+ * then each selected channel is triggered by the sequence start/data in a loop.
+ *
+ * @name:         device's name to search
+ * @channel_mask: channel selection - a bit mask
+ * @channels:     pointer to conversion output data for the selected channels
+ * @return:       0 if OK, -ve on error
+ */
+int adc_channels_single_shot(const char *name, unsigned int channel_mask,
+			     struct adc_channel *channels);
+
+/**
+ * adc_vdd_value() - get the ADC device's positive reference Voltage value
+ *
+ * Note: Depending on bool value 'vdd_supply_is_negative' of platform data,
+ * the returned uV value can be negative, and it's not an error.
+ *
+ * @dev:     ADC device to check
+ * @uV:      Voltage value with polarization sign (uV)
+ * @return:  0 on success or -ve on error
+*/
+int adc_vdd_value(struct udevice *dev, int *uV);
+
+/**
+ * adc_vss_value() - get the ADC device's negative reference Voltage value
+ *
+ * Note: Depending on bool value 'vdd_supply_is_negative' of platform data,
+ * the returned uV value can be negative, and it's not an error.
+ *
+ * @dev:     ADC device to check
+ * @uV:      Voltage value with polarization sign (uV)
+ * @return:  0 on success or -ve on error
+*/
+int adc_vss_value(struct udevice *dev, int *uV);
+
+/**
+ * adc_stop() - stop operation for given ADC device.
+ *
+ * @dev:     ADC device to stop
+ * @return:  0 if OK, -ve on error
+ */
+int adc_stop(struct udevice *dev);
+
+/**
+ * adc_raw_to_uV() - converts raw value to microvolts for given ADC device.
+ *
+ * @dev:     ADC device used from conversion
+ * @raw:     raw value to convert
+ * @uV:	     converted value in microvolts
+ * @return:  0 on success or -ve on error
+ */
+int adc_raw_to_uV(struct udevice *dev, unsigned int raw, int *uV);
+
+#endif
diff --git a/include/addr_map.h b/include/addr_map.h
new file mode 100644
index 0000000..d322dd2
--- /dev/null
+++ b/include/addr_map.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ADDR_MAP_H
+#define __ADDR_MAP_H
+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ */
+
+#include <asm/types.h>
+
+extern phys_addr_t addrmap_virt_to_phys(void *vaddr);
+extern void *addrmap_phys_to_virt(phys_addr_t paddr);
+extern void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,
+				phys_size_t size, int idx);
+
+#endif
diff --git a/include/ahci.h b/include/ahci.h
new file mode 100644
index 0000000..fb96dd8
--- /dev/null
+++ b/include/ahci.h
@@ -0,0 +1,288 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ * Author: Jason Jin<Jason.jin@freescale.com>
+ *         Zhang Wei<wei.zhang@freescale.com>
+ */
+#ifndef _AHCI_H_
+#define _AHCI_H_
+
+#include <pci.h>
+
+#define AHCI_PCI_BAR		0x24
+#define AHCI_MAX_SG		56 /* hardware max is 64K */
+#define AHCI_CMD_SLOT_SZ	32
+#define AHCI_MAX_CMD_SLOT	32
+#define AHCI_RX_FIS_SZ		256
+#define AHCI_CMD_TBL_HDR	0x80
+#define AHCI_CMD_TBL_CDB	0x40
+#define AHCI_CMD_TBL_SZ		AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
+#define AHCI_PORT_PRIV_DMA_SZ	(AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
+				AHCI_CMD_TBL_SZ	+ AHCI_RX_FIS_SZ)
+#define AHCI_CMD_ATAPI		(1 << 5)
+#define AHCI_CMD_WRITE		(1 << 6)
+#define AHCI_CMD_PREFETCH	(1 << 7)
+#define AHCI_CMD_RESET		(1 << 8)
+#define AHCI_CMD_CLR_BUSY	(1 << 10)
+
+#define RX_FIS_D2H_REG		0x40	/* offset of D2H Register FIS data */
+
+/* Global controller registers */
+#define HOST_CAP		0x00 /* host capabilities */
+#define HOST_CTL		0x04 /* global host control */
+#define HOST_IRQ_STAT		0x08 /* interrupt status */
+#define HOST_PORTS_IMPL		0x0c /* bitmap of implemented ports */
+#define HOST_VERSION		0x10 /* AHCI spec. version compliancy */
+#define HOST_CAP2		0x24 /* host capabilities, extended */
+
+/* HOST_CTL bits */
+#define HOST_RESET		(1 << 0)  /* reset controller; self-clear */
+#define HOST_IRQ_EN		(1 << 1)  /* global IRQ enable */
+#define HOST_AHCI_EN		(1 << 31) /* AHCI enabled */
+
+/* Registers for each SATA port */
+#define PORT_LST_ADDR		0x00 /* command list DMA addr */
+#define PORT_LST_ADDR_HI	0x04 /* command list DMA addr hi */
+#define PORT_FIS_ADDR		0x08 /* FIS rx buf addr */
+#define PORT_FIS_ADDR_HI	0x0c /* FIS rx buf addr hi */
+#define PORT_IRQ_STAT		0x10 /* interrupt status */
+#define PORT_IRQ_MASK		0x14 /* interrupt enable/disable mask */
+#define PORT_CMD		0x18 /* port command */
+#define PORT_TFDATA		0x20 /* taskfile data */
+#define PORT_SIG		0x24 /* device TF signature */
+#define PORT_CMD_ISSUE		0x38 /* command issue */
+#define PORT_SCR		0x28 /* SATA phy register block */
+#define PORT_SCR_STAT		0x28 /* SATA phy register: SStatus */
+#define PORT_SCR_CTL		0x2c /* SATA phy register: SControl */
+#define PORT_SCR_ERR		0x30 /* SATA phy register: SError */
+#define PORT_SCR_ACT		0x34 /* SATA phy register: SActive */
+
+#ifdef CONFIG_SUNXI_AHCI
+#define PORT_P0DMACR		0x70 /* SUNXI specific "DMA register" */
+#endif
+
+/* PORT_IRQ_{STAT,MASK} bits */
+#define PORT_IRQ_COLD_PRES	(1 << 31) /* cold presence detect */
+#define PORT_IRQ_TF_ERR		(1 << 30) /* task file error */
+#define PORT_IRQ_HBUS_ERR	(1 << 29) /* host bus fatal error */
+#define PORT_IRQ_HBUS_DATA_ERR	(1 << 28) /* host bus data error */
+#define PORT_IRQ_IF_ERR		(1 << 27) /* interface fatal error */
+#define PORT_IRQ_IF_NONFATAL	(1 << 26) /* interface non-fatal error */
+#define PORT_IRQ_OVERFLOW	(1 << 24) /* xfer exhausted available S/G */
+#define PORT_IRQ_BAD_PMP	(1 << 23) /* incorrect port multiplier */
+
+#define PORT_IRQ_PHYRDY		(1 << 22) /* PhyRdy changed */
+#define PORT_IRQ_DEV_ILCK	(1 << 7) /* device interlock */
+#define PORT_IRQ_CONNECT	(1 << 6) /* port connect change status */
+#define PORT_IRQ_SG_DONE	(1 << 5) /* descriptor processed */
+#define PORT_IRQ_UNK_FIS	(1 << 4) /* unknown FIS rx'd */
+#define PORT_IRQ_SDB_FIS	(1 << 3) /* Set Device Bits FIS rx'd */
+#define PORT_IRQ_DMAS_FIS	(1 << 2) /* DMA Setup FIS rx'd */
+#define PORT_IRQ_PIOS_FIS	(1 << 1) /* PIO Setup FIS rx'd */
+#define PORT_IRQ_D2H_REG_FIS	(1 << 0) /* D2H Register FIS rx'd */
+
+#define PORT_IRQ_FATAL		PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR	\
+				| PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
+
+#define DEF_PORT_IRQ		PORT_IRQ_FATAL | PORT_IRQ_PHYRDY	\
+				| PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE	\
+				| PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS	\
+				| PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS	\
+				| PORT_IRQ_D2H_REG_FIS
+
+/* PORT_SCR_STAT bits */
+#define PORT_SCR_STAT_DET_MASK	0x3
+#define PORT_SCR_STAT_DET_COMINIT 0x1
+#define PORT_SCR_STAT_DET_PHYRDY 0x3
+
+/* PORT_CMD bits */
+#define PORT_CMD_ATAPI		(1 << 24) /* Device is ATAPI */
+#define PORT_CMD_LIST_ON	(1 << 15) /* cmd list DMA engine running */
+#define PORT_CMD_FIS_ON		(1 << 14) /* FIS DMA engine running */
+#define PORT_CMD_FIS_RX		(1 << 4) /* Enable FIS receive DMA engine */
+#define PORT_CMD_CLO		(1 << 3) /* Command list override */
+#define PORT_CMD_POWER_ON	(1 << 2) /* Power up device */
+#define PORT_CMD_SPIN_UP	(1 << 1) /* Spin up device */
+#define PORT_CMD_START		(1 << 0) /* Enable port DMA engine */
+
+#define PORT_CMD_ICC_ACTIVE	(0x1 << 28) /* Put i/f in active state */
+#define PORT_CMD_ICC_PARTIAL	(0x2 << 28) /* Put i/f in partial state */
+#define PORT_CMD_ICC_SLUMBER	(0x6 << 28) /* Put i/f in slumber state */
+
+#define AHCI_MAX_PORTS		32
+
+#define ATA_FLAG_SATA		(1 << 3)
+#define ATA_FLAG_NO_LEGACY	(1 << 4) /* no legacy mode check */
+#define ATA_FLAG_MMIO		(1 << 6) /* use MMIO, not PIO */
+#define ATA_FLAG_SATA_RESET	(1 << 7) /* (obsolete) use COMRESET */
+#define ATA_FLAG_PIO_DMA	(1 << 8) /* PIO cmds via DMA */
+#define ATA_FLAG_NO_ATAPI	(1 << 11) /* No ATAPI support */
+
+struct ahci_cmd_hdr {
+	u32	opts;
+	u32	status;
+	u32	tbl_addr;
+	u32	tbl_addr_hi;
+	u32	reserved[4];
+};
+
+struct ahci_sg {
+	u32	addr;
+	u32	addr_hi;
+	u32	reserved;
+	u32	flags_size;
+};
+
+struct ahci_ioports {
+	void __iomem	*port_mmio;
+	struct ahci_cmd_hdr	*cmd_slot;
+	struct ahci_sg		*cmd_tbl_sg;
+	ulong	cmd_tbl;
+	u32	rx_fis;
+};
+
+/**
+ * struct ahci_uc_priv - information about an AHCI controller
+ *
+ * When driver model is used, this is accessible using dev_get_uclass_priv(dev)
+ * where dev is the controller (although at present it sometimes stands alone).
+ */
+struct ahci_uc_priv {
+#if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
+	/*
+	 * TODO(sjg@chromium.org): Drop this once this structure is only used
+	 * in a driver-model context (i.e. attached to a device with
+	 * dev_get_uclass_priv()
+	 */
+	struct udevice *dev;
+#else
+	pci_dev_t	dev;
+#endif
+	struct ahci_ioports	port[AHCI_MAX_PORTS];
+	u16 *ataid[AHCI_MAX_PORTS];
+	u32	n_ports;
+	u32	hard_port_no;
+	u32	host_flags;
+	u32	host_set_flags;
+	void __iomem *mmio_base;
+	u32     pio_mask;
+	u32	udma_mask;
+	u32	flags;
+	u32	cap;	/* cache of HOST_CAP register */
+	u32	port_map; /* cache of HOST_PORTS_IMPL reg */
+	u32	link_port_map; /*linkup port map*/
+};
+
+struct ahci_ops {
+	/**
+	 * reset() - reset the controller
+	 *
+	 * @dev:	Controller to reset
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*reset)(struct udevice *dev);
+
+	/**
+	 * port_status() - get the status of a SATA port
+	 *
+	 * @dev:	Controller to reset
+	 * @port:	Port number to check (0 for first)
+	 * @return 0 if detected, -ENXIO if nothing on port, other -ve on error
+	 */
+	int (*port_status)(struct udevice *dev, int port);
+
+	/**
+	 * scan() - scan SATA ports
+	 *
+	 * @dev:	Controller to scan
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*scan)(struct udevice *dev);
+};
+
+#define ahci_get_ops(dev)        ((struct ahci_ops *)(dev)->driver->ops)
+
+/**
+ * sata_reset() - reset the controller
+ *
+ * @dev:	Controller to reset
+ * @return 0 if OK, -ve on error
+ */
+int sata_reset(struct udevice *dev);
+
+/**
+ * sata_port_status() - get the status of a SATA port
+ *
+ * @dev:	Controller to reset
+ * @port:	Port number to check (0 for first)
+ * @return 0 if detected, -ENXIO if nothin on port, other -ve on error
+ */
+int sata_dm_port_status(struct udevice *dev, int port);
+
+/**
+ * sata_scan() - scan SATA ports
+ *
+ * @dev:	Controller to scan
+ * @return 0 if OK, -ve on error
+ */
+int sata_scan(struct udevice *dev);
+
+int ahci_init(void __iomem *base);
+int ahci_reset(void __iomem *base);
+
+/**
+ * ahci_init_one_dm() - set up a single AHCI port
+ *
+ * @dev: Controller to init
+ */
+int ahci_init_one_dm(struct udevice *dev);
+
+/**
+ * ahci_start_ports_dm() - start all AHCI ports for a controller
+ *
+ * @dev: Controller containing ports to start
+ */
+int ahci_start_ports_dm(struct udevice *dev);
+
+/**
+ * ahci_init_dm() - init AHCI for a controller, finding all ports
+ *
+ * @dev: Device to init
+ */
+int ahci_init_dm(struct udevice *dev, void __iomem *base);
+
+/**
+ * ahci_bind_scsi() - bind a new SCSI bus as a child
+ *
+ * Note that the SCSI bus device will itself bind block devices
+ *
+ * @ahci_dev: AHCI parent device
+ * @devp: Returns new SCSI bus device
+ * @return 0 if OK, -ve on error
+ */
+int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp);
+
+/**
+ * ahci_probe_scsi() - probe and scan the attached SCSI bus
+ *
+ * Note that the SCSI device will itself bind block devices for any storage
+ * devices it finds.
+ *
+ * @ahci_dev: AHCI parent device
+ * @base: Base address of AHCI port
+ * @return 0 if OK, -ve on error
+ */
+int ahci_probe_scsi(struct udevice *ahci_dev, ulong base);
+
+/**
+ * ahci_probe_scsi_pci() - probe and scan the attached SCSI bus on PCI
+ *
+ * Note that the SCSI device will itself bind block devices for any storage
+ * devices it finds.
+ *
+ * @ahci_dev: AHCI parent device
+ * @return 0 if OK, -ve on error
+ */
+int ahci_probe_scsi_pci(struct udevice *ahci_dev);
+
+#endif
diff --git a/include/ali512x.h b/include/ali512x.h
new file mode 100644
index 0000000..6bb6700
--- /dev/null
+++ b/include/ali512x.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ */
+
+#ifndef __ASM_IC_ALI512X_H_
+#define __ASM_IC_ALI512X_H_
+
+# define ALI_INDEX    0x3f0
+# define ALI_DATA     0x3f1
+
+# define ALI_ENABLED  1
+# define ALI_DISABLED 0
+
+# define ALI_UART1    0
+# define ALI_UART2    1
+
+/* setup functions */
+void ali512x_init(void);
+void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel);
+void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel);
+void ali512x_set_uart(int enabled, int index, u16 io, u8 irq);
+void ali512x_set_rtc(int enabled, u16 io, u8 irq);
+void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq);
+void ali512x_set_cio(int enabled);
+
+
+/* common I/O functions */
+void ali512x_cio_function(int pin, int special, int inv, int input);
+void ali512x_cio_out(int pin, int value);
+int ali512x_cio_in(int pin);
+
+/* misc features */
+void ali512x_set_uart2_irda(int enabled);
+
+#endif
diff --git a/include/altera.h b/include/altera.h
new file mode 100644
index 0000000..22d55cf
--- /dev/null
+++ b/include/altera.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ */
+
+#include <fpga.h>
+
+#ifndef _ALTERA_H_
+#define _ALTERA_H_
+
+/*
+ * For the StratixV FPGA programming via SPI, the following
+ * information is coded in the 32bit cookie:
+ * Bit 31 ... Bit 0
+ * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
+ */
+#define FPGA_COOKIE(bus, dev, config, done)			\
+	(((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done))
+#define COOKIE2SPI_BUS(c)	(((c) >> 24) & 0xff)
+#define COOKIE2SPI_DEV(c)	(((c) >> 16) & 0xff)
+#define COOKIE2CONFIG(c)	(((c) >> 8) & 0xff)
+#define COOKIE2DONE(c)		((c) & 0xff)
+
+enum altera_iface {
+	/* insert all new types after this */
+	min_altera_iface_type,
+	/* serial data and external clock */
+	passive_serial,
+	/* parallel data */
+	passive_parallel_synchronous,
+	/* parallel data */
+	passive_parallel_asynchronous,
+	/* serial data w/ internal clock (not used) */
+	passive_serial_asynchronous,
+	/* jtag/tap serial (not used ) */
+	altera_jtag_mode,
+	/* fast passive parallel (FPP) */
+	fast_passive_parallel,
+	/* fast passive parallel with security (FPPS) */
+	fast_passive_parallel_security,
+	/* secure device manager (SDM) mailbox */
+	secure_device_manager_mailbox,
+	/* insert all new types before this */
+	max_altera_iface_type,
+};
+
+enum altera_family {
+	/* insert all new types after this */
+	min_altera_type,
+	/* ACEX1K Family */
+	Altera_ACEX1K,
+	/* CYCLONII Family */
+	Altera_CYC2,
+	/* StratixII Family */
+	Altera_StratixII,
+	/* StratixV Family */
+	Altera_StratixV,
+	/* Stratix10 Family */
+	Intel_FPGA_Stratix10,
+	/* SoCFPGA Family */
+	Altera_SoCFPGA,
+
+	/* Add new models here */
+
+	/* insert all new types before this */
+	max_altera_type,
+};
+
+typedef struct {
+	/* part type */
+	enum altera_family	family;
+	/* interface type */
+	enum altera_iface	iface;
+	/* bytes of data part can accept */
+	size_t			size;
+	/* interface function table */
+	void			*iface_fns;
+	/* base interface address */
+	void			*base;
+	/* implementation specific cookie */
+	int			cookie;
+} Altera_desc;
+
+/* Generic Altera Functions
+ *********************************************************************/
+extern int altera_load(Altera_desc *desc, const void *image, size_t size);
+extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int altera_info(Altera_desc *desc);
+
+/* Board specific implementation specific function types
+ *********************************************************************/
+typedef int (*Altera_pre_fn)( int cookie );
+typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
+typedef int (*Altera_status_fn)( int cookie );
+typedef int (*Altera_done_fn)( int cookie );
+typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
+typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
+typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie);
+typedef int (*Altera_abort_fn)( int cookie );
+typedef int (*Altera_post_fn)( int cookie );
+
+typedef struct {
+	Altera_pre_fn pre;
+	Altera_config_fn config;
+	Altera_status_fn status;
+	Altera_done_fn done;
+	Altera_clk_fn clk;
+	Altera_data_fn data;
+	Altera_write_fn write;
+	Altera_abort_fn abort;
+	Altera_post_fn post;
+} altera_board_specific_func;
+
+#ifdef CONFIG_FPGA_SOCFPGA
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+#endif
+
+#ifdef CONFIG_FPGA_STRATIX_V
+int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+#endif
+
+#ifdef CONFIG_FPGA_STRATIX10
+int stratix10_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+#endif
+
+#endif /* _ALTERA_H_ */
diff --git a/include/ansi.h b/include/ansi.h
new file mode 100644
index 0000000..e90a697
--- /dev/null
+++ b/include/ansi.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ */
+
+/*
+ * ANSI terminal
+ */
+
+#define ANSI_CURSOR_UP			"\e[%dA"
+#define ANSI_CURSOR_DOWN		"\e[%dB"
+#define ANSI_CURSOR_FORWARD		"\e[%dC"
+#define ANSI_CURSOR_BACK		"\e[%dD"
+#define ANSI_CURSOR_NEXTLINE		"\e[%dE"
+#define ANSI_CURSOR_PREVIOUSLINE	"\e[%dF"
+#define ANSI_CURSOR_COLUMN		"\e[%dG"
+#define ANSI_CURSOR_POSITION		"\e[%d;%dH"
+#define ANSI_CURSOR_SHOW		"\e[?25h"
+#define ANSI_CURSOR_HIDE		"\e[?25l"
+#define ANSI_CLEAR_CONSOLE		"\e[2J"
+#define ANSI_CLEAR_LINE_TO_END		"\e[0K"
+#define ANSI_CLEAR_LINE			"\e[2K"
+#define ANSI_COLOR_RESET		"\e[0m"
+#define ANSI_COLOR_REVERSE		"\e[7m"
diff --git a/include/api.h b/include/api.h
new file mode 100644
index 0000000..84d81dc
--- /dev/null
+++ b/include/api.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __API_H
+#define __API_H
+
+void api_init(void);
+
+#endif
diff --git a/include/api_public.h b/include/api_public.h
new file mode 100644
index 0000000..def103c
--- /dev/null
+++ b/include/api_public.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-2-Clause */
+/*
+ * (C) Copyright 2007-2008 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ */
+
+#ifndef _API_PUBLIC_H_
+#define _API_PUBLIC_H_
+
+#define API_EINVAL		1	/* invalid argument(s)	*/
+#define API_ENODEV		2	/* no device		*/
+#define API_ENOMEM		3	/* no memory		*/
+#define API_EBUSY		4	/* busy, occupied etc.	*/
+#define API_EIO			5	/* I/O error		*/
+#define API_ESYSC		6	/* syscall error	*/
+
+typedef	int (*scp_t)(int, int *, ...);
+
+#define API_SIG_VERSION	1
+#define API_SIG_MAGIC	"UBootAPI"
+#define API_SIG_MAGLEN	8
+
+struct api_signature {
+	char		magic[API_SIG_MAGLEN];	/* magic string */
+	uint16_t	version;		/* API version */
+	uint32_t	checksum;		/* checksum of this sig struct */
+	scp_t		syscall;		/* entry point to the API */
+};
+
+enum {
+	API_RSVD = 0,
+	API_GETC,
+	API_PUTC,
+	API_TSTC,
+	API_PUTS,
+	API_RESET,
+	API_GET_SYS_INFO,
+	API_UDELAY,
+	API_GET_TIMER,
+	API_DEV_ENUM,
+	API_DEV_OPEN,
+	API_DEV_CLOSE,
+	API_DEV_READ,
+	API_DEV_WRITE,
+	API_ENV_ENUM,
+	API_ENV_GET,
+	API_ENV_SET,
+	API_DISPLAY_GET_INFO,
+	API_DISPLAY_DRAW_BITMAP,
+	API_DISPLAY_CLEAR,
+	API_MAXCALL
+};
+
+#define MR_ATTR_FLASH	0x0001
+#define MR_ATTR_DRAM	0x0002
+#define MR_ATTR_SRAM	0x0003
+
+struct mem_region {
+	unsigned long	start;
+	unsigned long	size;
+	int		flags;
+};
+
+struct sys_info {
+	unsigned long		clk_bus;
+	unsigned long		clk_cpu;
+	unsigned long		bar;
+	struct mem_region	*mr;
+	int			mr_no;	/* number of memory regions */
+};
+
+#undef CONFIG_SYS_64BIT_LBA
+#ifdef CONFIG_SYS_64BIT_LBA
+typedef	u_int64_t lbasize_t;
+#else
+typedef unsigned long lbasize_t;
+#endif
+typedef unsigned long lbastart_t;
+
+#define DEV_TYP_NONE	0x0000
+#define DEV_TYP_NET	0x0001
+
+#define DEV_TYP_STOR	0x0002
+#define DT_STOR_IDE	0x0010
+#define DT_STOR_SCSI	0x0020
+#define DT_STOR_USB	0x0040
+#define DT_STOR_MMC	0x0080
+#define DT_STOR_SATA	0x0100
+
+#define DEV_STA_CLOSED	0x0000		/* invalid, closed */
+#define DEV_STA_OPEN	0x0001		/* open i.e. active */
+
+struct device_info {
+	int	type;
+	void	*cookie;
+
+	union {
+		struct {
+			lbasize_t	block_count;	/* no of blocks */
+			unsigned long	block_size;	/* size of one block */
+		} storage;
+
+		struct {
+			unsigned char	hwaddr[6];
+		} net;
+	} info;
+#define di_stor info.storage
+#define di_net info.net
+
+	int	state;
+};
+
+#define DISPLAY_TYPE_LCD	0x0001
+#define DISPLAY_TYPE_VIDEO	0x0002
+
+struct display_info {
+	int type;
+	/* screen size in pixels */
+	int pixel_width;
+	int pixel_height;
+	/* screen size in rows and columns of text */
+	int screen_rows;
+	int screen_cols;
+};
+
+#endif /* _API_PUBLIC_H_ */
diff --git a/include/asm-generic/atomic-long.h b/include/asm-generic/atomic-long.h
new file mode 100644
index 0000000..32f288b
--- /dev/null
+++ b/include/asm-generic/atomic-long.h
@@ -0,0 +1,262 @@
+#ifndef _ASM_GENERIC_ATOMIC_LONG_H
+#define _ASM_GENERIC_ATOMIC_LONG_H
+/*
+ * Copyright (C) 2005 Silicon Graphics, Inc.
+ *	Christoph Lameter
+ *
+ * Allows to provide arch independent atomic definitions without the need to
+ * edit all arch specific atomic.h files.
+ */
+
+#include <asm/types.h>
+
+/*
+ * Suppport for atomic_long_t
+ *
+ * Casts for parameters are avoided for existing atomic functions in order to
+ * avoid issues with cast-as-lval under gcc 4.x and other limitations that the
+ * macros of a platform may have.
+ */
+
+#if BITS_PER_LONG == 64
+
+typedef atomic64_t atomic_long_t;
+
+#define ATOMIC_LONG_INIT(i)	ATOMIC64_INIT(i)
+
+static inline long atomic_long_read(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_read(v);
+}
+
+static inline void atomic_long_set(atomic_long_t *l, long i)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	atomic64_set(v, i);
+}
+
+static inline void atomic_long_inc(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	atomic64_inc(v);
+}
+
+static inline void atomic_long_dec(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	atomic64_dec(v);
+}
+
+static inline void atomic_long_add(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	atomic64_add(i, v);
+}
+
+static inline void atomic_long_sub(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	atomic64_sub(i, v);
+}
+
+#ifndef __UBOOT__
+static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return atomic64_sub_and_test(i, v);
+}
+
+static inline int atomic_long_dec_and_test(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return atomic64_dec_and_test(v);
+}
+
+static inline int atomic_long_inc_and_test(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return atomic64_inc_and_test(v);
+}
+
+static inline int atomic_long_add_negative(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return atomic64_add_negative(i, v);
+}
+
+static inline long atomic_long_add_return(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_add_return(i, v);
+}
+
+static inline long atomic_long_sub_return(long i, atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_sub_return(i, v);
+}
+
+static inline long atomic_long_inc_return(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_inc_return(v);
+}
+
+static inline long atomic_long_dec_return(atomic_long_t *l)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_dec_return(v);
+}
+
+static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
+{
+	atomic64_t *v = (atomic64_t *)l;
+
+	return (long)atomic64_add_unless(v, a, u);
+}
+
+#define atomic_long_inc_not_zero(l) atomic64_inc_not_zero((atomic64_t *)(l))
+
+#define atomic_long_cmpxchg(l, old, new) \
+	(atomic64_cmpxchg((atomic64_t *)(l), (old), (new)))
+#define atomic_long_xchg(v, new) \
+	(atomic64_xchg((atomic64_t *)(v), (new)))
+#endif  /*  __UBOOT__ */
+
+#else  /*  BITS_PER_LONG == 64  */
+
+typedef atomic_t atomic_long_t;
+
+#define ATOMIC_LONG_INIT(i)	ATOMIC_INIT(i)
+static inline long atomic_long_read(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_read(v);
+}
+
+static inline void atomic_long_set(atomic_long_t *l, long i)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	atomic_set(v, i);
+}
+
+static inline void atomic_long_inc(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	atomic_inc(v);
+}
+
+static inline void atomic_long_dec(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	atomic_dec(v);
+}
+
+static inline void atomic_long_add(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	atomic_add(i, v);
+}
+
+static inline void atomic_long_sub(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	atomic_sub(i, v);
+}
+
+#ifndef __UBOOT__
+static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return atomic_sub_and_test(i, v);
+}
+
+static inline int atomic_long_dec_and_test(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return atomic_dec_and_test(v);
+}
+
+static inline int atomic_long_inc_and_test(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return atomic_inc_and_test(v);
+}
+
+static inline int atomic_long_add_negative(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return atomic_add_negative(i, v);
+}
+
+static inline long atomic_long_add_return(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_add_return(i, v);
+}
+
+static inline long atomic_long_sub_return(long i, atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_sub_return(i, v);
+}
+
+static inline long atomic_long_inc_return(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_inc_return(v);
+}
+
+static inline long atomic_long_dec_return(atomic_long_t *l)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_dec_return(v);
+}
+
+static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
+{
+	atomic_t *v = (atomic_t *)l;
+
+	return (long)atomic_add_unless(v, a, u);
+}
+
+#define atomic_long_inc_not_zero(l) atomic_inc_not_zero((atomic_t *)(l))
+
+#define atomic_long_cmpxchg(l, old, new) \
+	(atomic_cmpxchg((atomic_t *)(l), (old), (new)))
+#define atomic_long_xchg(v, new) \
+	(atomic_xchg((atomic_t *)(v), (new)))
+#endif  /*  __UBOOT__ */
+
+#endif  /*  BITS_PER_LONG == 64  */
+
+#endif  /*  _ASM_GENERIC_ATOMIC_LONG_H  */
diff --git a/include/asm-generic/atomic.h b/include/asm-generic/atomic.h
new file mode 100644
index 0000000..94d0747
--- /dev/null
+++ b/include/asm-generic/atomic.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _ASM_GENERIC_ATOMIC_H
+#define _ASM_GENERIC_ATOMIC_H
+
+typedef struct { volatile int counter; } atomic_t;
+#if BITS_PER_LONG == 32
+typedef struct { volatile long long counter; } atomic64_t;
+#else /* BIT_PER_LONG == 32 */
+typedef struct { volatile long counter; } atomic64_t;
+#endif
+
+#define ATOMIC_INIT(i)	{ (i) }
+
+#define atomic_read(v)		((v)->counter)
+#define atomic_set(v, i)	((v)->counter = (i))
+#define atomic64_read(v)	atomic_read(v)
+#define atomic64_set(v, i)	atomic_set(v, i)
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+	v->counter += i;
+	local_irq_restore(flags);
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+	v->counter -= i;
+	local_irq_restore(flags);
+}
+
+static inline void atomic_inc(atomic_t *v)
+{
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+	++v->counter;
+	local_irq_restore(flags);
+}
+
+static inline void atomic_dec(atomic_t *v)
+{
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+	--v->counter;
+	local_irq_restore(flags);
+}
+
+static inline int atomic_dec_and_test(volatile atomic_t *v)
+{
+	unsigned long flags = 0;
+	int val;
+
+	local_irq_save(flags);
+	val = v->counter;
+	v->counter = val -= 1;
+	local_irq_restore(flags);
+
+	return val == 0;
+}
+
+static inline int atomic_add_negative(int i, volatile atomic_t *v)
+{
+	unsigned long flags = 0;
+	int val;
+
+	local_irq_save(flags);
+	val = v->counter;
+	v->counter = val += i;
+	local_irq_restore(flags);
+
+	return val < 0;
+}
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+{
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+	*addr &= ~mask;
+	local_irq_restore(flags);
+}
+
+#if BITS_PER_LONG == 32
+
+static inline void atomic64_add(long long i, volatile atomic64_t *v)
+{
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+	v->counter += i;
+	local_irq_restore(flags);
+}
+
+static inline void atomic64_sub(long long i, volatile atomic64_t *v)
+{
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+	v->counter -= i;
+	local_irq_restore(flags);
+}
+
+#else /* BIT_PER_LONG == 32 */
+
+static inline void atomic64_add(long i, volatile atomic64_t *v)
+{
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+	v->counter += i;
+	local_irq_restore(flags);
+}
+
+static inline void atomic64_sub(long i, volatile atomic64_t *v)
+{
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+	v->counter -= i;
+	local_irq_restore(flags);
+}
+#endif
+
+static inline void atomic64_inc(volatile atomic64_t *v)
+{
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+	v->counter += 1;
+	local_irq_restore(flags);
+}
+
+static inline void atomic64_dec(volatile atomic64_t *v)
+{
+	unsigned long flags = 0;
+
+	local_irq_save(flags);
+	v->counter -= 1;
+	local_irq_restore(flags);
+}
+
+#endif
diff --git a/include/asm-generic/bitops/__ffs.h b/include/asm-generic/bitops/__ffs.h
new file mode 100644
index 0000000..937d7c4
--- /dev/null
+++ b/include/asm-generic/bitops/__ffs.h
@@ -0,0 +1,43 @@
+#ifndef _ASM_GENERIC_BITOPS___FFS_H_
+#define _ASM_GENERIC_BITOPS___FFS_H_
+
+#include <asm/types.h>
+
+/**
+ * __ffs - find first bit in word.
+ * @word: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static __always_inline unsigned long __ffs(unsigned long word)
+{
+	int num = 0;
+
+#if BITS_PER_LONG == 64
+	if ((word & 0xffffffff) == 0) {
+		num += 32;
+		word >>= 32;
+	}
+#endif
+	if ((word & 0xffff) == 0) {
+		num += 16;
+		word >>= 16;
+	}
+	if ((word & 0xff) == 0) {
+		num += 8;
+		word >>= 8;
+	}
+	if ((word & 0xf) == 0) {
+		num += 4;
+		word >>= 4;
+	}
+	if ((word & 0x3) == 0) {
+		num += 2;
+		word >>= 2;
+	}
+	if ((word & 0x1) == 0)
+		num += 1;
+	return num;
+}
+
+#endif /* _ASM_GENERIC_BITOPS___FFS_H_ */
diff --git a/include/asm-generic/bitops/__fls.h b/include/asm-generic/bitops/__fls.h
new file mode 100644
index 0000000..a60a7cc
--- /dev/null
+++ b/include/asm-generic/bitops/__fls.h
@@ -0,0 +1,43 @@
+#ifndef _ASM_GENERIC_BITOPS___FLS_H_
+#define _ASM_GENERIC_BITOPS___FLS_H_
+
+#include <asm/types.h>
+
+/**
+ * __fls - find last (most-significant) set bit in a long word
+ * @word: the word to search
+ *
+ * Undefined if no set bit exists, so code should check against 0 first.
+ */
+static __always_inline unsigned long __fls(unsigned long word)
+{
+	int num = BITS_PER_LONG - 1;
+
+#if BITS_PER_LONG == 64
+	if (!(word & (~0ul << 32))) {
+		num -= 32;
+		word <<= 32;
+	}
+#endif
+	if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
+		num -= 16;
+		word <<= 16;
+	}
+	if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
+		num -= 8;
+		word <<= 8;
+	}
+	if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
+		num -= 4;
+		word <<= 4;
+	}
+	if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
+		num -= 2;
+		word <<= 2;
+	}
+	if (!(word & (~0ul << (BITS_PER_LONG-1))))
+		num -= 1;
+	return num;
+}
+
+#endif /* _ASM_GENERIC_BITOPS___FLS_H_ */
diff --git a/include/asm-generic/bitops/fls.h b/include/asm-generic/bitops/fls.h
new file mode 100644
index 0000000..0576d1f
--- /dev/null
+++ b/include/asm-generic/bitops/fls.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_GENERIC_BITOPS_FLS_H_
+#define _ASM_GENERIC_BITOPS_FLS_H_
+
+/**
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+
+static __always_inline int fls(int x)
+{
+	int r = 32;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff0000u)) {
+		x <<= 16;
+		r -= 16;
+	}
+	if (!(x & 0xff000000u)) {
+		x <<= 8;
+		r -= 8;
+	}
+	if (!(x & 0xf0000000u)) {
+		x <<= 4;
+		r -= 4;
+	}
+	if (!(x & 0xc0000000u)) {
+		x <<= 2;
+		r -= 2;
+	}
+	if (!(x & 0x80000000u)) {
+		x <<= 1;
+		r -= 1;
+	}
+	return r;
+}
+
+#endif /* _ASM_GENERIC_BITOPS_FLS_H_ */
diff --git a/include/asm-generic/bitops/fls64.h b/include/asm-generic/bitops/fls64.h
new file mode 100644
index 0000000..b097cf8
--- /dev/null
+++ b/include/asm-generic/bitops/fls64.h
@@ -0,0 +1,36 @@
+#ifndef _ASM_GENERIC_BITOPS_FLS64_H_
+#define _ASM_GENERIC_BITOPS_FLS64_H_
+
+#include <asm/types.h>
+
+/**
+ * fls64 - find last set bit in a 64-bit word
+ * @x: the word to search
+ *
+ * This is defined in a similar way as the libc and compiler builtin
+ * ffsll, but returns the position of the most significant set bit.
+ *
+ * fls64(value) returns 0 if value is 0 or the position of the last
+ * set bit if value is nonzero. The last (most significant) bit is
+ * at position 64.
+ */
+#if BITS_PER_LONG == 32
+static __always_inline int fls64(__u64 x)
+{
+	__u32 h = x >> 32;
+	if (h)
+		return fls(h) + 32;
+	return fls(x);
+}
+#elif BITS_PER_LONG == 64
+static __always_inline int fls64(__u64 x)
+{
+	if (x == 0)
+		return 0;
+	return __fls(x) + 1;
+}
+#else
+#error BITS_PER_LONG not 32 or 64
+#endif
+
+#endif /* _ASM_GENERIC_BITOPS_FLS64_H_ */
diff --git a/include/asm-generic/bitsperlong.h b/include/asm-generic/bitsperlong.h
new file mode 100644
index 0000000..75ee21e
--- /dev/null
+++ b/include/asm-generic/bitsperlong.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_GENERIC_BITS_PER_LONG
+#define __ASM_GENERIC_BITS_PER_LONG
+
+#ifndef BITS_PER_LONG_LONG
+#define BITS_PER_LONG_LONG 64
+#endif
+
+#endif /* __ASM_GENERIC_BITS_PER_LONG */
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
new file mode 100644
index 0000000..7587ba2
--- /dev/null
+++ b/include/asm-generic/global_data.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __ASM_GENERIC_GBL_DATA_H
+#define __ASM_GENERIC_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory which is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
+ *
+ * Each architecture has its own private fields. For now all are private
+ */
+
+#ifndef __ASSEMBLY__
+#include <fdtdec.h>
+#include <membuff.h>
+#include <linux/list.h>
+
+typedef struct global_data {
+	bd_t *bd;
+	unsigned long flags;
+	unsigned int baudrate;
+	unsigned long cpu_clk;		/* CPU clock in Hz!		*/
+	unsigned long bus_clk;
+	/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
+	unsigned long pci_clk;
+	unsigned long mem_clk;
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
+	unsigned long fb_base;		/* Base address of framebuffer mem */
+#endif
+#if defined(CONFIG_POST)
+	unsigned long post_log_word;	/* Record POST activities */
+	unsigned long post_log_res;	/* success of POST test */
+	unsigned long post_init_f_time;	/* When post_init_f started */
+#endif
+#ifdef CONFIG_BOARD_TYPES
+	unsigned long board_type;
+#endif
+	unsigned long have_console;	/* serial_init() was called */
+#if CONFIG_IS_ENABLED(PRE_CONSOLE_BUFFER)
+	unsigned long precon_buf_idx;	/* Pre-Console buffer index */
+#endif
+	unsigned long env_addr;		/* Address  of Environment struct */
+	unsigned long env_valid;	/* Environment valid? enum env_valid */
+	unsigned long env_has_init;	/* Bitmask of boolean of struct env_location offsets */
+	int env_load_prio;		/* Priority of the loaded environment */
+
+	unsigned long ram_base;		/* Base address of RAM used by U-Boot */
+	unsigned long ram_top;		/* Top address of RAM used by U-Boot */
+	unsigned long relocaddr;	/* Start address of U-Boot in RAM */
+	phys_size_t ram_size;		/* RAM size */
+	unsigned long mon_len;		/* monitor len */
+	unsigned long irq_sp;		/* irq stack pointer */
+	unsigned long start_addr_sp;	/* start_addr_stackpointer */
+	unsigned long reloc_off;
+	struct global_data *new_gd;	/* relocated global data */
+
+#ifdef CONFIG_DM
+	struct udevice	*dm_root;	/* Root instance for Driver Model */
+	struct udevice	*dm_root_f;	/* Pre-relocation root instance */
+	struct list_head uclass_root;	/* Head of core tree */
+#endif
+#ifdef CONFIG_TIMER
+	struct udevice	*timer;		/* Timer instance for Driver Model */
+#endif
+
+	const void *fdt_blob;		/* Our device tree, NULL if none */
+	void *new_fdt;			/* Relocated FDT */
+	unsigned long fdt_size;		/* Space reserved for relocated FDT */
+#ifdef CONFIG_OF_LIVE
+	struct device_node *of_root;
+#endif
+
+#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
+	const void *multi_dtb_fit;	/* uncompressed multi-dtb FIT image */
+#endif
+	struct jt_funcs *jt;		/* jump table */
+	char env_buf[32];		/* buffer for env_get() before reloc. */
+#ifdef CONFIG_TRACE
+	void		*trace_buff;	/* The trace buffer */
+#endif
+#if defined(CONFIG_SYS_I2C)
+	int		cur_i2c_bus;	/* current used i2c bus */
+#endif
+#ifdef CONFIG_SYS_I2C_MXC
+	void *srdata[10];
+#endif
+	unsigned int timebase_h;
+	unsigned int timebase_l;
+#if CONFIG_VAL(SYS_MALLOC_F_LEN)
+	unsigned long malloc_base;	/* base address of early malloc() */
+	unsigned long malloc_limit;	/* limit address */
+	unsigned long malloc_ptr;	/* current address */
+#endif
+#ifdef CONFIG_PCI
+	struct pci_controller *hose;	/* PCI hose for early use */
+	phys_addr_t pci_ram_top;	/* top of region accessible to PCI */
+#endif
+#ifdef CONFIG_PCI_BOOTDELAY
+	int pcidelay_done;
+#endif
+	struct udevice *cur_serial_dev;	/* current serial device */
+	struct arch_global_data arch;	/* architecture-specific data */
+#ifdef CONFIG_CONSOLE_RECORD
+	struct membuff console_out;	/* console output */
+	struct membuff console_in;	/* console input */
+#endif
+#ifdef CONFIG_DM_VIDEO
+	ulong video_top;		/* Top of video frame buffer area */
+	ulong video_bottom;		/* Bottom of video frame buffer area */
+#endif
+#ifdef CONFIG_BOOTSTAGE
+	struct bootstage_data *bootstage;	/* Bootstage information */
+	struct bootstage_data *new_bootstage;	/* Relocated bootstage info */
+#endif
+#ifdef CONFIG_LOG
+	int log_drop_count;		/* Number of dropped log messages */
+	int default_log_level;		/* For devices with no filters */
+	struct list_head log_head;	/* List of struct log_device */
+	int log_fmt;			/* Mask containing log format info */
+#endif
+#if CONFIG_IS_ENABLED(BLOBLIST)
+	struct bloblist_hdr *bloblist;	/* Bloblist information */
+	struct bloblist_hdr *new_bloblist;	/* Relocated blolist info */
+# ifdef CONFIG_SPL
+	struct spl_handoff *spl_handoff;
+# endif
+#endif
+#if defined(CONFIG_TRANSLATION_OFFSET)
+	fdt_addr_t translation_offset;	/* optional translation offset */
+#endif
+#if CONFIG_IS_ENABLED(WDT)
+	struct udevice *watchdog_dev;
+#endif
+} gd_t;
+#endif
+
+#ifdef CONFIG_BOARD_TYPES
+#define gd_board_type()		gd->board_type
+#else
+#define gd_board_type()		0
+#endif
+
+/*
+ * Global Data Flags
+ */
+#define GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	   */
+#define GD_FLG_DEVINIT		0x00002	/* Devices have been initialized   */
+#define GD_FLG_SILENT		0x00004	/* Silent mode			   */
+#define GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	   */
+#define GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	   */
+#define GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	   */
+#define GD_FLG_ENV_READY	0x00080	/* Env. imported into hash table   */
+#define GD_FLG_SERIAL_READY	0x00100	/* Pre-reloc serial console ready  */
+#define GD_FLG_FULL_MALLOC_INIT	0x00200	/* Full malloc() is ready	   */
+#define GD_FLG_SPL_INIT		0x00400	/* spl_init() has been called	   */
+#define GD_FLG_SKIP_RELOC	0x00800	/* Don't relocate		   */
+#define GD_FLG_RECORD		0x01000	/* Record console		   */
+#define GD_FLG_ENV_DEFAULT	0x02000 /* Default variable flag	   */
+#define GD_FLG_SPL_EARLY_INIT	0x04000 /* Early SPL init is done	   */
+#define GD_FLG_LOG_READY	0x08000 /* Log system is ready for use	   */
+#define GD_FLG_WDT_READY	0x10000 /* Watchdog is ready for use	   */
+
+#endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
new file mode 100644
index 0000000..d6cf187
--- /dev/null
+++ b/include/asm-generic/gpio.h
@@ -0,0 +1,660 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2011, NVIDIA Corp. All rights reserved.
+ */
+
+#ifndef _ASM_GENERIC_GPIO_H_
+#define _ASM_GENERIC_GPIO_H_
+
+#include <dm/ofnode.h>
+
+struct ofnode_phandle_args;
+
+/*
+ * Generic GPIO API for U-Boot
+ *
+ * --
+ * NB: This is deprecated. Please use the driver model functions instead:
+ *
+ *    - gpio_request_by_name()
+ *    - dm_gpio_get_value() etc.
+ *
+ * For now we need a dm_ prefix on some functions to avoid name collision.
+ * --
+ *
+ * GPIOs are numbered from 0 to GPIO_COUNT-1 which value is defined
+ * by the SOC/architecture.
+ *
+ * Each GPIO can be an input or output. If an input then its value can
+ * be read as 0 or 1. If an output then its value can be set to 0 or 1.
+ * If you try to write an input then the value is undefined. If you try
+ * to read an output, barring something very unusual,  you will get
+ * back the value of the output that you previously set.
+ *
+ * In some cases the operation may fail, for example if the GPIO number
+ * is out of range, or the GPIO is not available because its pin is
+ * being used by another function. In that case, functions may return
+ * an error value of -1.
+ */
+
+/**
+ * @deprecated	Please use driver model instead
+ * Request a GPIO. This should be called before any of the other functions
+ * are used on this GPIO.
+ *
+ * Note: With driver model, the label is allocated so there is no need for
+ * the caller to preserve it.
+ *
+ * @param gpio	GPIO number
+ * @param label	User label for this GPIO
+ * @return 0 if ok, -1 on error
+ */
+int gpio_request(unsigned gpio, const char *label);
+
+/**
+ * @deprecated	Please use driver model instead
+ * Stop using the GPIO.  This function should not alter pin configuration.
+ *
+ * @param gpio	GPIO number
+ * @return 0 if ok, -1 on error
+ */
+int gpio_free(unsigned gpio);
+
+/**
+ * @deprecated	Please use driver model instead
+ * Make a GPIO an input.
+ *
+ * @param gpio	GPIO number
+ * @return 0 if ok, -1 on error
+ */
+int gpio_direction_input(unsigned gpio);
+
+/**
+ * @deprecated	Please use driver model instead
+ * Make a GPIO an output, and set its value.
+ *
+ * @param gpio	GPIO number
+ * @param value	GPIO value (0 for low or 1 for high)
+ * @return 0 if ok, -1 on error
+ */
+int gpio_direction_output(unsigned gpio, int value);
+
+/**
+ * @deprecated	Please use driver model instead
+ * Get a GPIO's value. This will work whether the GPIO is an input
+ * or an output.
+ *
+ * @param gpio	GPIO number
+ * @return 0 if low, 1 if high, -1 on error
+ */
+int gpio_get_value(unsigned gpio);
+
+/**
+ * @deprecated	Please use driver model instead
+ * Set an output GPIO's value. The GPIO must already be an output or
+ * this function may have no effect.
+ *
+ * @param gpio	GPIO number
+ * @param value	GPIO value (0 for low or 1 for high)
+ * @return 0 if ok, -1 on error
+ */
+int gpio_set_value(unsigned gpio, int value);
+
+/* State of a GPIO, as reported by get_function() */
+enum gpio_func_t {
+	GPIOF_INPUT = 0,
+	GPIOF_OUTPUT,
+	GPIOF_UNUSED,		/* Not claimed */
+	GPIOF_UNKNOWN,		/* Not known */
+	GPIOF_FUNC,		/* Not used as a GPIO */
+
+	GPIOF_COUNT,
+};
+
+struct udevice;
+
+struct gpio_desc {
+	struct udevice *dev;	/* Device, NULL for invalid GPIO */
+	unsigned long flags;
+#define GPIOD_REQUESTED		(1 << 0)	/* Requested/claimed */
+#define GPIOD_IS_OUT		(1 << 1)	/* GPIO is an output */
+#define GPIOD_IS_IN		(1 << 2)	/* GPIO is an input */
+#define GPIOD_ACTIVE_LOW	(1 << 3)	/* value has active low */
+#define GPIOD_IS_OUT_ACTIVE	(1 << 4)	/* set output active */
+
+	uint offset;		/* GPIO offset within the device */
+	/*
+	 * We could consider adding the GPIO label in here. Possibly we could
+	 * use this structure for internal GPIO information.
+	 */
+};
+
+/**
+ * dm_gpio_is_valid() - Check if a GPIO is valid
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return true if valid, false if not
+ */
+static inline bool dm_gpio_is_valid(const struct gpio_desc *desc)
+{
+	return desc->dev != NULL;
+}
+
+/**
+ * gpio_get_status() - get the current GPIO status as a string
+ *
+ * Obtain the current GPIO status as a string which can be presented to the
+ * user. A typical string is:
+ *
+ * "b4:  in: 1 [x] sdmmc_cd"
+ *
+ * which means this is GPIO bank b, offset 4, currently set to input, current
+ * value 1, [x] means that it is requested and the owner is 'sdmmc_cd'
+ *
+ * TODO(sjg@chromium.org): This should use struct gpio_desc
+ *
+ * @dev:	Device to check
+ * @offset:	Offset of device GPIO to check
+ * @buf:	Place to put string
+ * @buffsize:	Size of string including \0
+ */
+int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize);
+
+/**
+ * gpio_get_function() - get the current function for a GPIO pin
+ *
+ * Note this returns GPIOF_UNUSED if the GPIO is not requested.
+ *
+ * TODO(sjg@chromium.org): This should use struct gpio_desc
+ *
+ * @dev:	Device to check
+ * @offset:	Offset of device GPIO to check
+ * @namep:	If non-NULL, this is set to the name given when the GPIO
+ *		was requested, or -1 if it has not been requested
+ * @return  -ENODATA if the driver returned an unknown function,
+ * -ENODEV if the device is not active, -EINVAL if the offset is invalid.
+ * GPIOF_UNUSED if the GPIO has not been requested. Otherwise returns the
+ * function from enum gpio_func_t.
+ */
+int gpio_get_function(struct udevice *dev, int offset, const char **namep);
+
+/**
+ * gpio_get_raw_function() - get the current raw function for a GPIO pin
+ *
+ * Note this does not return GPIOF_UNUSED - it will always return the GPIO
+ * driver's view of a pin function, even if it is not correctly set up.
+ *
+ * TODO(sjg@chromium.org): This should use struct gpio_desc
+ *
+ * @dev:	Device to check
+ * @offset:	Offset of device GPIO to check
+ * @namep:	If non-NULL, this is set to the name given when the GPIO
+ *		was requested, or -1 if it has not been requested
+ * @return  -ENODATA if the driver returned an unknown function,
+ * -ENODEV if the device is not active, -EINVAL if the offset is invalid.
+ * Otherwise returns the function from enum gpio_func_t.
+ */
+int gpio_get_raw_function(struct udevice *dev, int offset, const char **namep);
+
+/**
+ * gpio_requestf() - request a GPIO using a format string for the owner
+ *
+ * This is a helper function for gpio_request(). It allows you to provide
+ * a printf()-format string for the GPIO owner. It calls gpio_request() with
+ * the string that is created
+ */
+int gpio_requestf(unsigned gpio, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 2, 3)));
+
+struct fdtdec_phandle_args;
+
+/**
+ * gpio_xlate_offs_flags() - implementation for common use of dm_gpio_ops.xlate
+ *
+ * This routine sets the offset field to args[0] and the flags field to
+ * GPIOD_ACTIVE_LOW if the GPIO_ACTIVE_LOW flag is present in args[1].
+ */
+int gpio_xlate_offs_flags(struct udevice *dev, struct gpio_desc *desc,
+			  struct ofnode_phandle_args *args);
+
+/**
+ * struct struct dm_gpio_ops - Driver model GPIO operations
+ *
+ * Refer to functions above for description. These function largely copy
+ * the old API.
+ *
+ * This is trying to be close to Linux GPIO API. Once the U-Boot uses the
+ * new DM GPIO API, this should be really easy to flip over to the Linux
+ * GPIO API-alike interface.
+ *
+ * Also it would be useful to standardise additional functions like
+ * pullup, slew rate and drive strength.
+ *
+ * gpio_request() and gpio_free() are optional - if NULL then they will
+ * not be called.
+ *
+ * Note that @offset is the offset from the base GPIO of the device. So
+ * offset 0 is the device's first GPIO and offset o-1 is the last GPIO,
+ * where o is the number of GPIO lines controlled by the device. A device
+ * is typically used to control a single bank of GPIOs. Within complex
+ * SoCs there may be many banks and therefore many devices all referring
+ * to the different IO addresses within the SoC.
+ *
+ * The uclass combines all GPIO devices together to provide a consistent
+ * numbering from 0 to n-1, where n is the number of GPIOs in total across
+ * all devices. Be careful not to confuse offset with gpio in the parameters.
+ */
+struct dm_gpio_ops {
+	int (*request)(struct udevice *dev, unsigned offset, const char *label);
+	int (*free)(struct udevice *dev, unsigned offset);
+	int (*direction_input)(struct udevice *dev, unsigned offset);
+	int (*direction_output)(struct udevice *dev, unsigned offset,
+				int value);
+	int (*get_value)(struct udevice *dev, unsigned offset);
+	int (*set_value)(struct udevice *dev, unsigned offset, int value);
+	int (*get_open_drain)(struct udevice *dev, unsigned offset);
+	int (*set_open_drain)(struct udevice *dev, unsigned offset, int value);
+	/**
+	 * get_function() Get the GPIO function
+	 *
+	 * @dev:     Device to check
+	 * @offset:  GPIO offset within that device
+	 * @return current function - GPIOF_...
+	 */
+	int (*get_function)(struct udevice *dev, unsigned offset);
+
+	/**
+	 * xlate() - Translate phandle arguments into a GPIO description
+	 *
+	 * This function should set up the fields in desc according to the
+	 * information in the arguments. The uclass will have set up:
+	 *
+	 *   @desc->dev to @dev
+	 *   @desc->flags to 0
+	 *   @desc->offset to 0
+	 *
+	 * This method is optional and defaults to gpio_xlate_offs_flags,
+	 * which will parse offset and the GPIO_ACTIVE_LOW flag in the first
+	 * two arguments.
+	 *
+	 * Note that @dev is passed in as a parameter to follow driver model
+	 * uclass conventions, even though it is already available as
+	 * desc->dev.
+	 *
+	 * @dev:	GPIO device
+	 * @desc:	Place to put GPIO description
+	 * @args:	Arguments provided in description
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*xlate)(struct udevice *dev, struct gpio_desc *desc,
+		     struct ofnode_phandle_args *args);
+};
+
+/**
+ * struct gpio_dev_priv - information about a device used by the uclass
+ *
+ * The uclass combines all active GPIO devices into a unified numbering
+ * scheme. To do this it maintains some private information about each
+ * device.
+ *
+ * To implement driver model support in your GPIO driver, add a probe
+ * handler, and set @gpio_count and @bank_name correctly in that handler.
+ * This tells the uclass the name of the GPIO bank and the number of GPIOs
+ * it contains.
+ *
+ * @bank_name: Name of the GPIO device (e.g 'a' means GPIOs will be called
+ * 'A0', 'A1', etc.
+ * @gpio_count: Number of GPIOs in this device
+ * @gpio_base: Base GPIO number for this device. For the first active device
+ * this will be 0; the numbering for others will follow sequentially so that
+ * @gpio_base for device 1 will equal the number of GPIOs in device 0.
+ * @name: Array of pointers to the name for each GPIO in this bank. The
+ * value of the pointer will be NULL if the GPIO has not been claimed.
+ */
+struct gpio_dev_priv {
+	const char *bank_name;
+	unsigned gpio_count;
+	unsigned gpio_base;
+	char **name;
+};
+
+/* Access the GPIO operations for a device */
+#define gpio_get_ops(dev)	((struct dm_gpio_ops *)(dev)->driver->ops)
+
+/**
+ * gpio_get_bank_info - Return information about a GPIO bank/device
+ *
+ * This looks up a device and returns both its GPIO base name and the number
+ * of GPIOs it controls.
+ *
+ * @dev: Device to look up
+ * @offset_count: Returns number of GPIOs within this bank
+ * @return bank name of this device
+ */
+const char *gpio_get_bank_info(struct udevice *dev, int *offset_count);
+
+/**
+ * dm_gpio_lookup_name() - Look up a named GPIO and return its description
+ *
+ * The name of a GPIO is typically its bank name followed by a number from 0.
+ * For example A0 is the first GPIO in bank A. Each bank is a separate driver
+ * model device.
+ *
+ * @name:	Name to look up
+ * @desc:	Returns description, on success
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_lookup_name(const char *name, struct gpio_desc *desc);
+
+/**
+ * gpio_hog_lookup_name() - Look up a named GPIO and return the gpio descr.
+ *
+ * @name:	Name to look up
+ * @desc:	Returns GPIO description, on success, else NULL
+ * @return:	Returns 0 if OK, else -ENODEV
+ */
+int gpio_hog_lookup_name(const char *name, struct gpio_desc **desc);
+
+/**
+ * gpio_hog_probe_all() - probe all gpio devices with
+ * gpio-hog subnodes.
+ *
+ * @return:	Returns return value from device_probe()
+ */
+int gpio_hog_probe_all(void);
+
+/**
+ * gpio_lookup_name - Look up a GPIO name and return its details
+ *
+ * This is used to convert a named GPIO into a device, offset and GPIO
+ * number.
+ *
+ * @name: GPIO name to look up
+ * @devp: Returns pointer to device which contains this GPIO
+ * @offsetp: Returns the offset number within this device
+ * @gpiop: Returns the absolute GPIO number, numbered from 0
+ */
+int gpio_lookup_name(const char *name, struct udevice **devp,
+		     unsigned int *offsetp, unsigned int *gpiop);
+
+/**
+ * gpio_get_values_as_int() - Turn the values of a list of GPIOs into an int
+ *
+ * This puts the value of the first GPIO into bit 0, the second into bit 1,
+ * etc. then returns the resulting integer.
+ *
+ * @gpio_list: List of GPIOs to collect
+ * @return resulting integer value, or -ve on error
+ */
+int gpio_get_values_as_int(const int *gpio_list);
+
+/**
+ * dm_gpio_get_values_as_int() - Turn the values of a list of GPIOs into an int
+ *
+ * This puts the value of the first GPIO into bit 0, the second into bit 1,
+ * etc. then returns the resulting integer.
+ *
+ * @desc_list: List of GPIOs to collect
+ * @count: Number of GPIOs
+ * @return resulting integer value, or -ve on error
+ */
+int dm_gpio_get_values_as_int(const struct gpio_desc *desc_list, int count);
+
+/**
+ * gpio_claim_vector() - claim a number of GPIOs for input
+ *
+ * @gpio_num_array:	array of gpios to claim, terminated by -1
+ * @fmt:		format string for GPIO names, e.g. "board_id%d"
+ * @return 0 if OK, -ve on error
+ */
+int gpio_claim_vector(const int *gpio_num_array, const char *fmt);
+
+/**
+ * gpio_request_by_name() - Locate and request a GPIO by name
+ *
+ * This operates by looking up the given list name in the device (device
+ * tree property) and requesting the GPIO for use. The property must exist
+ * in @dev's node.
+ *
+ * Use @flags to specify whether the GPIO should be an input or output. In
+ * principle this can also come from the device tree binding but most
+ * bindings don't provide this information. Specifically, when the GPIO uclass
+ * calls the xlate() method, it can return default flags, which are then
+ * ORed with this @flags.
+ *
+ * If we find that requesting the GPIO is not always needed we could add a
+ * new function or a new GPIOD_NO_REQUEST flag.
+ *
+ * At present driver model has no reference counting so if one device
+ * requests a GPIO which subsequently is unbound, the @desc->dev pointer
+ * will be invalid. However this will only happen if the GPIO device is
+ * unbound, not if it is removed, so this seems like a reasonable limitation
+ * for now. There is no real use case for unbinding drivers in normal
+ * operation.
+ *
+ * The device tree binding is doc/device-tree-bindings/gpio/gpio.txt in
+ * generate terms and each specific device may add additional details in
+ * a binding file in the same directory.
+ *
+ * @dev:	Device requesting the GPIO
+ * @list_name:	Name of GPIO list (e.g. "board-id-gpios")
+ * @index:	Index number of the GPIO in that list use request (0=first)
+ * @desc:	Returns GPIO description information. If there is no such
+ *		GPIO, dev->dev will be NULL.
+ * @flags:	Indicates the GPIO input/output settings (GPIOD_...)
+ * @return 0 if OK, -ENOENT if the GPIO does not exist, -EINVAL if there is
+ * something wrong with the list, or other -ve for another error (e.g.
+ * -EBUSY if a GPIO was already requested)
+ */
+int gpio_request_by_name(struct udevice *dev, const char *list_name,
+			 int index, struct gpio_desc *desc, int flags);
+
+/**
+ * gpio_request_list_by_name() - Request a list of GPIOs
+ *
+ * Reads all the GPIOs from a list and requests them. See
+ * gpio_request_by_name() for additional details. Lists should not be
+ * misused to hold unrelated or optional GPIOs. They should only be used
+ * for things like parallel data lines. A zero phandle terminates the list
+ * the list.
+ *
+ * This function will either succeed, and request all GPIOs in the list, or
+ * fail and request none (it will free already-requested GPIOs in case of
+ * an error part-way through).
+ *
+ * @dev:	Device requesting the GPIO
+ * @list_name:	Name of GPIO list (e.g. "board-id-gpios")
+ * @desc_list:	Returns a list of GPIO description information
+ * @max_count:	Maximum number of GPIOs to return (@desc_list must be at least
+ *		this big)
+ * @flags:	Indicates the GPIO input/output settings (GPIOD_...)
+ * @return number of GPIOs requested, or -ve on error
+ */
+int gpio_request_list_by_name(struct udevice *dev, const char *list_name,
+			      struct gpio_desc *desc_list, int max_count,
+			      int flags);
+
+/**
+ * dm_gpio_request() - manually request a GPIO
+ *
+ * Note: This function should only be used for testing / debugging. Instead.
+ * use gpio_request_by_name() to pull GPIOs from the device tree.
+ *
+ * @desc:	GPIO description of GPIO to request (see dm_gpio_lookup_name())
+ * @label:	Label to attach to the GPIO while claimed
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_request(struct gpio_desc *desc, const char *label);
+
+/**
+ * gpio_get_list_count() - Returns the number of GPIOs in a list
+ *
+ * Counts the GPIOs in a list. See gpio_request_by_name() for additional
+ * details.
+ *
+ * @dev:	Device requesting the GPIO
+ * @list_name:	Name of GPIO list (e.g. "board-id-gpios")
+ * @return number of GPIOs (0 for an empty property) or -ENOENT if the list
+ * does not exist
+ */
+int gpio_get_list_count(struct udevice *dev, const char *list_name);
+
+/**
+ * gpio_request_by_name_nodev() - request GPIOs without a device
+ *
+ * This is a version of gpio_request_list_by_name() that does not use a
+ * device. Avoid it unless the caller is not yet using driver model
+ */
+int gpio_request_by_name_nodev(ofnode node, const char *list_name, int index,
+			       struct gpio_desc *desc, int flags);
+
+/**
+ * gpio_request_list_by_name_nodev() - request GPIOs without a device
+ *
+ * This is a version of gpio_request_list_by_name() that does not use a
+ * device. Avoid it unless the caller is not yet using driver model
+ */
+int gpio_request_list_by_name_nodev(ofnode node, const char *list_name,
+				    struct gpio_desc *desc_list, int max_count,
+				    int flags);
+
+/**
+ * gpio_dev_request_index() - request single GPIO from gpio device
+ *
+ * @dev:	GPIO device
+ * @nodename:	Name of node for which gpio gets requested, used
+ *		for the gpio label name
+ * @list_name:	Name of GPIO list (e.g. "board-id-gpios")
+ * @index:	Index number of the GPIO in that list use request (0=first)
+ * @flags:	GPIOD_* flags
+ * @dtflags:	GPIO flags read from DT defined see GPIOD_*
+ * @desc:	returns GPIO descriptor filled from this function
+ * @return:	return value from gpio_request_tail()
+ */
+int gpio_dev_request_index(struct udevice *dev, const char *nodename,
+			   char *list_name, int index, int flags,
+			   int dtflags, struct gpio_desc *desc);
+
+/**
+ * dm_gpio_free() - Free a single GPIO
+ *
+ * This frees a single GPIOs previously returned from gpio_request_by_name().
+ *
+ * @dev:	Device which requested the GPIO
+ * @desc:	GPIO to free
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc);
+
+/**
+ * gpio_free_list() - Free a list of GPIOs
+ *
+ * This frees a list of GPIOs previously returned from
+ * gpio_request_list_by_name().
+ *
+ * @dev:	Device which requested the GPIOs
+ * @desc:	List of GPIOs to free
+ * @count:	Number of GPIOs in the list
+ * @return 0 if OK, -ve on error
+ */
+int gpio_free_list(struct udevice *dev, struct gpio_desc *desc, int count);
+
+/**
+ * gpio_free_list_nodev() - free GPIOs without a device
+ *
+ * This is a version of gpio_free_list() that does not use a
+ * device. Avoid it unless the caller is not yet using driver model
+ */
+int gpio_free_list_nodev(struct gpio_desc *desc, int count);
+
+/**
+ * dm_gpio_get_value() - Get the value of a GPIO
+ *
+ * This is the driver model version of the existing gpio_get_value() function
+ * and should be used instead of that.
+ *
+ * For now, these functions have a dm_ prefix since they conflict with
+ * existing names.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return GPIO value (0 for inactive, 1 for active) or -ve on error
+ */
+int dm_gpio_get_value(const struct gpio_desc *desc);
+
+int dm_gpio_set_value(const struct gpio_desc *desc, int value);
+
+/**
+ * dm_gpio_get_open_drain() - Check if open-drain-mode of a GPIO is active
+ *
+ * This checks if open-drain-mode for a GPIO is enabled or not. This method is
+ * optional.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return Value of open drain mode for GPIO (0 for inactive, 1 for active) or
+ *	   -ve on error
+ */
+int dm_gpio_get_open_drain(struct gpio_desc *desc);
+
+/**
+ * dm_gpio_set_open_drain() - Switch open-drain-mode of a GPIO on or off
+ *
+ * This enables or disables open-drain mode for a GPIO. This method is
+ * optional; if the driver does not support it, nothing happens when the method
+ * is called.
+ *
+ * In open-drain mode, instead of actively driving the output (Push-pull
+ * output), the GPIO's pin is connected to the collector (for a NPN transistor)
+ * or the drain (for a MOSFET) of a transistor, respectively. The pin then
+ * either forms an open circuit or a connection to ground, depending on the
+ * state of the transistor.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_set_open_drain(struct gpio_desc *desc, int value);
+
+/**
+ * dm_gpio_set_dir() - Set the direction for a GPIO
+ *
+ * This sets up the direction according tot the provided flags. It will do
+ * nothing unless the direction is actually specified.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_set_dir(struct gpio_desc *desc);
+
+/**
+ * dm_gpio_set_dir_flags() - Set direction using specific flags
+ *
+ * This is like dm_gpio_set_dir() except that the flags value is provided
+ * instead of being used from desc->flags. This is needed because in many
+ * cases the GPIO description does not include direction information.
+ * Note that desc->flags is updated by this function.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @flags:	New flags to use
+ * @return 0 if OK, -ve on error, in which case desc->flags is not updated
+ */
+int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags);
+
+/**
+ * gpio_get_number() - Get the global GPIO number of a GPIO
+ *
+ * This should only be used for debugging or interest. It returns the number
+ * that should be used for gpio_get_value() etc. to access this GPIO.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return GPIO number, or -ve if not found
+ */
+int gpio_get_number(const struct gpio_desc *desc);
+
+#endif	/* _ASM_GENERIC_GPIO_H_ */
diff --git a/include/asm-generic/int-ll64.h b/include/asm-generic/int-ll64.h
new file mode 100644
index 0000000..7451718
--- /dev/null
+++ b/include/asm-generic/int-ll64.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * asm-generic/int-ll64.h
+ *
+ * Integer declarations for architectures which use "long long"
+ * for 64-bit types.
+ */
+
+#ifndef _ASM_GENERIC_INT_LL64_H
+#define _ASM_GENERIC_INT_LL64_H
+
+#ifndef __ASSEMBLY__
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#ifdef __GNUC__
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#else
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+typedef __s8  s8;
+typedef __u8  u8;
+typedef __s16 s16;
+typedef __u16 u16;
+typedef __s32 s32;
+typedef __u32 u32;
+typedef __s64 s64;
+typedef __u64 u64;
+
+#endif /* __ASSEMBLY__ */
+
+
+#endif /* _ASM_GENERIC_INT_LL64_H */
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
new file mode 100644
index 0000000..7a2f0db
--- /dev/null
+++ b/include/asm-generic/io.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Generic I/O functions.
+ *
+ * Copyright (c) 2016 Imagination Technologies Ltd.
+ */
+
+#ifndef __ASM_GENERIC_IO_H__
+#define __ASM_GENERIC_IO_H__
+
+/*
+ * This file should be included at the end of each architecture-specific
+ * asm/io.h such that we may provide generic implementations without
+ * conflicting with architecture-specific code.
+ */
+
+#ifndef __ASSEMBLY__
+
+/**
+ * phys_to_virt() - Return a virtual address mapped to a given physical address
+ * @paddr: the physical address
+ *
+ * Returns a virtual address which the CPU can access that maps to the physical
+ * address @paddr. This should only be used where it is known that no dynamic
+ * mapping is required. In general, map_physmem should be used instead.
+ *
+ * Returns: a virtual address which maps to @paddr
+ */
+#ifndef phys_to_virt
+static inline void *phys_to_virt(phys_addr_t paddr)
+{
+	return (void *)(unsigned long)paddr;
+}
+#endif
+
+/**
+ * virt_to_phys() - Return the physical address that a virtual address maps to
+ * @vaddr: the virtual address
+ *
+ * Returns the physical address which the CPU-accessible virtual address @vaddr
+ * maps to.
+ *
+ * Returns: the physical address which @vaddr maps to
+ */
+#ifndef virt_to_phys
+static inline phys_addr_t virt_to_phys(void *vaddr)
+{
+	return (phys_addr_t)((unsigned long)vaddr);
+}
+#endif
+
+/*
+ * Flags for use with map_physmem() & unmap_physmem(). Architectures need not
+ * support all of these, in which case they will be defined as zero here &
+ * ignored. Callers that may run on multiple architectures should therefore
+ * treat them as hints rather than requirements.
+ */
+#ifndef MAP_NOCACHE
+# define MAP_NOCACHE	0	/* Produce an uncached mapping */
+#endif
+#ifndef MAP_WRCOMBINE
+# define MAP_WRCOMBINE	0	/* Allow write-combining on the mapping */
+#endif
+#ifndef MAP_WRBACK
+# define MAP_WRBACK	0	/* Map using write-back caching */
+#endif
+#ifndef MAP_WRTHROUGH
+# define MAP_WRTHROUGH	0	/* Map using write-through caching */
+#endif
+
+/**
+ * map_physmem() - Return a virtual address mapped to a given physical address
+ * @paddr: the physical address
+ * @len: the length of the required mapping
+ * @flags: flags affecting the type of mapping
+ *
+ * Return a virtual address through which the CPU may access the memory at
+ * physical address @paddr. The mapping will be valid for at least @len bytes,
+ * and may be affected by flags passed to the @flags argument. This function
+ * may create new mappings, so should generally be paired with a matching call
+ * to unmap_physmem once the caller is finished with the memory in question.
+ *
+ * Returns: a virtual address suitably mapped to @paddr
+ */
+#ifndef map_physmem
+static inline void *map_physmem(phys_addr_t paddr, unsigned long len,
+				unsigned long flags)
+{
+	return phys_to_virt(paddr);
+}
+#endif
+
+/**
+ * unmap_physmem() - Remove mappings created by a prior call to map_physmem()
+ * @vaddr: the virtual address which map_physmem() previously returned
+ * @flags: flags matching those originally passed to map_physmem()
+ *
+ * Unmap memory which was previously mapped by a call to map_physmem(). If
+ * map_physmem() dynamically created a mapping for the memory in question then
+ * unmap_physmem() will remove that mapping.
+ */
+#ifndef unmap_physmem
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+}
+#endif
+
+#endif /* !__ASSEMBLY__ */
+#endif /* __ASM_GENERIC_IO_H__ */
diff --git a/include/asm-generic/ioctl.h b/include/asm-generic/ioctl.h
new file mode 100644
index 0000000..15828b2
--- /dev/null
+++ b/include/asm-generic/ioctl.h
@@ -0,0 +1,105 @@
+#ifndef _ASM_GENERIC_IOCTL_H
+#define _ASM_GENERIC_IOCTL_H
+
+/* ioctl command encoding: 32 bits total, command in lower 16 bits,
+ * size of the parameter structure in the lower 14 bits of the
+ * upper 16 bits.
+ * Encoding the size of the parameter structure in the ioctl request
+ * is useful for catching programs compiled with old versions
+ * and to avoid overwriting user space outside the user buffer area.
+ * The highest 2 bits are reserved for indicating the ``access mode''.
+ * NOTE: This limits the max parameter size to 16kB -1 !
+ */
+
+/*
+ * The following is for compatibility across the various Linux
+ * platforms.  The generic ioctl numbering scheme doesn't really enforce
+ * a type field.  De facto, however, the top 8 bits of the lower 16
+ * bits are indeed used as a type field, so we might just as well make
+ * this explicit here.  Please be sure to use the decoding macros
+ * below from now on.
+ */
+#define _IOC_NRBITS	8
+#define _IOC_TYPEBITS	8
+
+/*
+ * Let any architecture override either of the following before
+ * including this file.
+ */
+
+#ifndef _IOC_SIZEBITS
+# define _IOC_SIZEBITS	14
+#endif
+
+#ifndef _IOC_DIRBITS
+# define _IOC_DIRBITS	2
+#endif
+
+#define _IOC_NRMASK	((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK	((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK	((1 << _IOC_SIZEBITS)-1)
+#define _IOC_DIRMASK	((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT	0
+#define _IOC_TYPESHIFT	(_IOC_NRSHIFT+_IOC_NRBITS)
+#define _IOC_SIZESHIFT	(_IOC_TYPESHIFT+_IOC_TYPEBITS)
+#define _IOC_DIRSHIFT	(_IOC_SIZESHIFT+_IOC_SIZEBITS)
+
+/*
+ * Direction bits, which any architecture can choose to override
+ * before including this file.
+ */
+
+#ifndef _IOC_NONE
+# define _IOC_NONE	0U
+#endif
+
+#ifndef _IOC_WRITE
+# define _IOC_WRITE	1U
+#endif
+
+#ifndef _IOC_READ
+# define _IOC_READ	2U
+#endif
+
+#define _IOC(dir,type,nr,size) \
+	(((dir)  << _IOC_DIRSHIFT) | \
+	 ((type) << _IOC_TYPESHIFT) | \
+	 ((nr)   << _IOC_NRSHIFT) | \
+	 ((size) << _IOC_SIZESHIFT))
+
+#ifdef __KERNEL__
+/* provoke compile error for invalid uses of size argument */
+extern unsigned int __invalid_size_argument_for_IOC;
+#define _IOC_TYPECHECK(t) \
+	((sizeof(t) == sizeof(t[1]) && \
+	  sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
+	  sizeof(t) : __invalid_size_argument_for_IOC)
+#else
+#define _IOC_TYPECHECK(t) (sizeof(t))
+#endif
+
+/* used to create numbers */
+#define _IO(type,nr)		_IOC(_IOC_NONE,(type),(nr),0)
+#define _IOR(type,nr,size)	_IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOW(type,nr,size)	_IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOWR(type,nr,size)	_IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOR_BAD(type,nr,size)	_IOC(_IOC_READ,(type),(nr),sizeof(size))
+#define _IOW_BAD(type,nr,size)	_IOC(_IOC_WRITE,(type),(nr),sizeof(size))
+#define _IOWR_BAD(type,nr,size)	_IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
+
+/* used to decode ioctl numbers.. */
+#define _IOC_DIR(nr)		(((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
+#define _IOC_TYPE(nr)		(((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr)		(((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr)		(((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
+
+/* ...and for the drivers/sound files... */
+
+#define IOC_IN		(_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT		(_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT	((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK	(_IOC_SIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT	(_IOC_SIZESHIFT)
+
+#endif /* _ASM_GENERIC_IOCTL_H */
diff --git a/include/asm-generic/pe.h b/include/asm-generic/pe.h
new file mode 100644
index 0000000..b247519
--- /dev/null
+++ b/include/asm-generic/pe.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Portable Executable and Common Object Constants
+ *
+ *  Copyright (c) 2018 Heinrich Schuchardt
+ *
+ *  based on the "Microsoft Portable Executable and Common Object File Format
+ *  Specification", revision 11, 2017-01-23
+ */
+
+#ifndef _ASM_PE_H
+#define _ASM_PE_H
+
+/* Characteristics */
+#define IMAGE_FILE_RELOCS_STRIPPED		0x0001
+#define IMAGE_FILE_EXECUTABLE_IMAGE		0x0002
+#define IMAGE_FILE_LINE_NUMS_STRIPPED		0x0004
+#define IMAGE_FILE_LOCAL_SYMS_STRIPPED		0x0008
+#define IMAGE_FILE_AGGRESSIVE_WS_TRIM		0x0010
+#define IMAGE_FILE_LARGE_ADDRESS_AWARE		0x0020
+/* Reserved					0x0040 */
+#define IMAGE_FILE_BYTES_REVERSED_LO		0x0080
+#define IMAGE_FILE_32BIT_MACHINE		0x0100
+#define IMAGE_FILE_DEBUG_STRIPPED		0x0200
+#define IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP	0x0400
+#define IMAGE_FILE_NET_RUN_FROM_SWAP		0x0800
+#define IMAGE_FILE_SYSTEM			0x1000
+#define IMAGE_FILE_DLL				0x2000
+#define IMAGE_FILE_UP_SYSTEM_ONLY		0x4000
+#define IMAGE_FILE_BYTES_REVERSED_HI		0x8000
+
+/* Machine types */
+#define IMAGE_FILE_MACHINE_I386			0x014c
+#define IMAGE_FILE_MACHINE_ARM			0x01c0
+#define IMAGE_FILE_MACHINE_THUMB		0x01c2
+#define IMAGE_FILE_MACHINE_ARMNT		0x01c4
+#define IMAGE_FILE_MACHINE_AMD64		0x8664
+#define IMAGE_FILE_MACHINE_ARM64		0xaa64
+#define IMAGE_FILE_MACHINE_RISCV32		0x5032
+#define IMAGE_FILE_MACHINE_RISCV64		0x5064
+
+/* Header magic constants */
+#define IMAGE_NT_OPTIONAL_HDR32_MAGIC		0x010b
+#define IMAGE_NT_OPTIONAL_HDR64_MAGIC		0x020b
+#define IMAGE_DOS_SIGNATURE			0x5a4d     /* MZ   */
+#define IMAGE_NT_SIGNATURE			0x00004550 /* PE00 */
+
+/* Subsystem type */
+#define IMAGE_SUBSYSTEM_EFI_APPLICATION		10
+#define IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER	11
+#define IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER	12
+#define IMAGE_SUBSYSTEM_EFI_ROM			13
+
+#endif /* _ASM_PE_H */
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
new file mode 100644
index 0000000..296c0cf
--- /dev/null
+++ b/include/asm-generic/sections.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+/* Taken from Linux kernel, commit f56c3196 */
+
+#ifndef _ASM_GENERIC_SECTIONS_H_
+#define _ASM_GENERIC_SECTIONS_H_
+
+/* References to section boundaries */
+
+extern char _text[], _stext[], _etext[];
+extern char _data[], _sdata[], _edata[];
+extern char __bss_start[], __bss_stop[];
+extern char __init_begin[], __init_end[];
+extern char _sinittext[], _einittext[];
+extern char _end[], _init[];
+extern char __per_cpu_load[], __per_cpu_start[], __per_cpu_end[];
+extern char __kprobes_text_start[], __kprobes_text_end[];
+extern char __entry_text_start[], __entry_text_end[];
+extern char __initdata_begin[], __initdata_end[];
+extern char __start_rodata[], __end_rodata[];
+extern char __efi_helloworld_begin[];
+extern char __efi_helloworld_end[];
+
+/* Start and end of .ctors section - used for constructor calls. */
+extern char __ctors_start[], __ctors_end[];
+
+/* function descriptor handling (if any).  Override
+ * in asm/sections.h */
+#ifndef dereference_function_descriptor
+#define dereference_function_descriptor(p) (p)
+#endif
+
+/* random extra sections (if any).  Override
+ * in asm/sections.h */
+#ifndef arch_is_kernel_text
+static inline int arch_is_kernel_text(unsigned long addr)
+{
+	return 0;
+}
+#endif
+
+#ifndef arch_is_kernel_data
+static inline int arch_is_kernel_data(unsigned long addr)
+{
+	return 0;
+}
+#endif
+
+/* U-Boot-specific things begin here */
+
+/* Start of U-Boot text region */
+extern char __text_start[];
+
+/* This marks the end of the text region which must be relocated */
+extern char __image_copy_end[];
+
+/*
+ * This is the U-Boot entry point - prior to relocation it should be same
+ * as __text_start
+ */
+extern void _start(void);
+
+/*
+ * ARM defines its symbols as char[]. Other arches define them as ulongs.
+ */
+#ifdef CONFIG_ARM
+
+extern char __bss_start[];
+extern char __bss_end[];
+extern char __image_copy_start[];
+extern char __image_copy_end[];
+extern char _image_binary_end[];
+extern char __rel_dyn_start[];
+extern char __rel_dyn_end[];
+
+#else /* don't use offsets: */
+
+/* Exports from the Linker Script */
+extern ulong __data_end;
+extern ulong __rel_dyn_start;
+extern ulong __rel_dyn_end;
+extern ulong __bss_end;
+extern ulong _image_binary_end;
+
+extern ulong _TEXT_BASE;	/* code start */
+
+#endif
+
+#endif /* _ASM_GENERIC_SECTIONS_H_ */
diff --git a/include/asm-generic/signal.h b/include/asm-generic/signal.h
new file mode 100644
index 0000000..af93947
--- /dev/null
+++ b/include/asm-generic/signal.h
@@ -0,0 +1,101 @@
+#ifndef __ASM_GENERIC_SIGNAL_H
+#define __ASM_GENERIC_SIGNAL_H
+
+#include <linux/types.h>
+
+#define _NSIG		64
+#define _NSIG_BPW	BITS_PER_LONG
+#define _NSIG_WORDS	(_NSIG / _NSIG_BPW)
+
+#define SIGHUP		 1
+#define SIGINT		 2
+#define SIGQUIT		 3
+#define SIGILL		 4
+#define SIGTRAP		 5
+#define SIGABRT		 6
+#define SIGIOT		 6
+#define SIGBUS		 7
+#define SIGFPE		 8
+#define SIGKILL		 9
+#define SIGUSR1		10
+#define SIGSEGV		11
+#define SIGUSR2		12
+#define SIGPIPE		13
+#define SIGALRM		14
+#define SIGTERM		15
+#define SIGSTKFLT	16
+#define SIGCHLD		17
+#define SIGCONT		18
+#define SIGSTOP		19
+#define SIGTSTP		20
+#define SIGTTIN		21
+#define SIGTTOU		22
+#define SIGURG		23
+#define SIGXCPU		24
+#define SIGXFSZ		25
+#define SIGVTALRM	26
+#define SIGPROF		27
+#define SIGWINCH	28
+#define SIGIO		29
+#define SIGPOLL		SIGIO
+/*
+#define SIGLOST		29
+*/
+#define SIGPWR		30
+#define SIGSYS		31
+#define	SIGUNUSED	31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN	32
+#ifndef SIGRTMAX
+#define SIGRTMAX	_NSIG
+#endif
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP	0x00000001
+#define SA_NOCLDWAIT	0x00000002
+#define SA_SIGINFO	0x00000004
+#define SA_ONSTACK	0x08000000
+#define SA_RESTART	0x10000000
+#define SA_NODEFER	0x40000000
+#define SA_RESETHAND	0x80000000
+
+#define SA_NOMASK	SA_NODEFER
+#define SA_ONESHOT	SA_RESETHAND
+
+/*
+ * New architectures should not define the obsolete
+ *	SA_RESTORER	0x04000000
+ */
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK	1
+#define SS_DISABLE	2
+
+#define MINSIGSTKSZ	2048
+#define SIGSTKSZ	8192
+
+#ifndef __ASSEMBLY__
+typedef struct {
+	unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+/* not actually used, but required for linux/syscalls.h */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_GENERIC_SIGNAL_H */
diff --git a/include/asm-generic/types.h b/include/asm-generic/types.h
new file mode 100644
index 0000000..7c076c5
--- /dev/null
+++ b/include/asm-generic/types.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_GENERIC_TYPES_H
+#define _ASM_GENERIC_TYPES_H
+/*
+ * int-ll64 is used everywhere now.
+ */
+#include <asm-generic/int-ll64.h>
+
+#endif /* _ASM_GENERIC_TYPES_H */
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
new file mode 100644
index 0000000..eee84f4
--- /dev/null
+++ b/include/asm-generic/u-boot.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * (C) Copyright 2000 - 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __ASM_GENERIC_U_BOOT_H__
+#define __ASM_GENERIC_U_BOOT_H__
+
+/*
+ * Board information passed to Linux kernel from U-Boot
+ *
+ * include/asm-ppc/u-boot.h
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef struct bd_info {
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	phys_size_t	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long	bi_sramstart;	/* start of SRAM memory */
+	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
+#ifdef CONFIG_ARM
+	unsigned long	bi_arm_freq; /* arm frequency */
+	unsigned long	bi_dsp_freq; /* dsp core frequency */
+	unsigned long	bi_ddr_freq; /* ddr frequency */
+#endif
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+	unsigned long	bi_immr_base;	/* base of IMMR register */
+#endif
+#if defined(CONFIG_M68K)
+	unsigned long	bi_mbar_base;	/* base of internal registers */
+#endif
+#if defined(CONFIG_MPC83xx)
+	unsigned long	bi_immrbar;
+#endif
+	unsigned long	bi_bootflags;	/* boot / reboot flag (Unused) */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6];	/* OLD: see README.enetaddr */
+	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
+	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
+	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
+#if defined(CONFIG_CPM2)
+	unsigned long	bi_cpmfreq;	/* CPM_CLK Freq, in MHz */
+	unsigned long	bi_brgfreq;	/* BRG_CLK Freq, in MHz */
+	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
+	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
+#endif
+#if defined(CONFIG_M68K)
+	unsigned long	bi_ipbfreq;	/* IPB Bus Freq, in MHz */
+	unsigned long	bi_pcifreq;	/* PCI Bus Freq, in MHz */
+#endif
+#if defined(CONFIG_EXTRA_CLOCK)
+	unsigned long bi_inpfreq;	/* input Freq in MHz */
+	unsigned long bi_vcofreq;	/* vco Freq in MHz */
+	unsigned long bi_flbfreq;	/* Flexbus Freq in MHz */
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+	unsigned char   bi_enet1addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH2
+	unsigned char	bi_enet2addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH3
+	unsigned char   bi_enet3addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH4
+	unsigned char   bi_enet4addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH5
+	unsigned char   bi_enet5addr[6];	/* OLD: see README.enetaddr */
+#endif
+
+	ulong	        bi_arch_number;	/* unique id for this board */
+	ulong	        bi_boot_params;	/* where this board expects params */
+#ifdef CONFIG_NR_DRAM_BANKS
+	struct {			/* RAM configuration */
+		phys_addr_t start;
+		phys_size_t size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+#endif /* CONFIG_NR_DRAM_BANKS */
+} bd_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif	/* __ASM_GENERIC_U_BOOT_H__ */
diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h
new file mode 100644
index 0000000..3d33a5a
--- /dev/null
+++ b/include/asm-generic/unaligned.h
@@ -0,0 +1,26 @@
+#ifndef _GENERIC_UNALIGNED_H
+#define _GENERIC_UNALIGNED_H
+
+#include <asm/byteorder.h>
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+/*
+ * Select endianness
+ */
+#if defined(__LITTLE_ENDIAN)
+#define get_unaligned	__get_unaligned_le
+#define put_unaligned	__put_unaligned_le
+#elif defined(__BIG_ENDIAN)
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+#else
+#error invalid endian
+#endif
+
+/* Allow unaligned memory access */
+void allow_unaligned(void);
+
+#endif
diff --git a/include/asm-offsets.h b/include/asm-offsets.h
new file mode 100644
index 0000000..ad3bf1f
--- /dev/null
+++ b/include/asm-offsets.h
@@ -0,0 +1,6 @@
+#ifndef	DO_DEPS_ONLY
+
+#include <generated/generic-asm-offsets.h>
+/* #include <generated/asm-offsets.h> */
+
+#endif
diff --git a/include/ata.h b/include/ata.h
new file mode 100644
index 0000000..3f4e4a0
--- /dev/null
+++ b/include/ata.h
@@ -0,0 +1,250 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * Most of the following information was derived from the document
+ * "Information Technology - AT Attachment-3 Interface (ATA-3)"
+ * which can be found at:
+ * http://www.dt.wdc.com/ata/ata-3/ata3r5v.zip
+ * ftp://poctok.iae.nsk.su/pub/asm/Documents/IDE/ATA3R5V.ZIP
+ * ftp://ftp.fee.vutbr.cz/pub/doc/io/ata/ata-3/ata3r5v.zip
+ */
+
+#ifndef	_ATA_H
+#define _ATA_H
+
+#include <libata.h>
+
+/* Register addressing depends on the hardware design; for instance,
+ * 8-bit (register) and 16-bit (data) accesses might use different
+ * address spaces. This is implemented by the following definitions.
+ */
+#ifndef CONFIG_SYS_ATA_STRIDE
+#define CONFIG_SYS_ATA_STRIDE	1
+#endif
+
+#define ATA_IO_DATA(x)	(CONFIG_SYS_ATA_DATA_OFFSET+((x) * CONFIG_SYS_ATA_STRIDE))
+#define ATA_IO_REG(x)	(CONFIG_SYS_ATA_REG_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
+#define ATA_IO_ALT(x)	(CONFIG_SYS_ATA_ALT_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
+
+/*
+ * I/O Register Descriptions
+ */
+#define ATA_DATA_REG	ATA_IO_DATA(0)
+#define ATA_ERROR_REG	ATA_IO_REG(1)
+#define ATA_SECT_CNT	ATA_IO_REG(2)
+#define ATA_SECT_NUM	ATA_IO_REG(3)
+#define ATA_CYL_LOW	ATA_IO_REG(4)
+#define ATA_CYL_HIGH	ATA_IO_REG(5)
+#define ATA_DEV_HD	ATA_IO_REG(6)
+#define ATA_COMMAND	ATA_IO_REG(7)
+#define ATA_DATA_EVEN	ATA_IO_REG(8)
+#define ATA_DATA_ODD	ATA_IO_REG(9)
+#define ATA_STATUS	ATA_COMMAND
+#define ATA_DEV_CTL	ATA_IO_ALT(6)
+#define ATA_LBA_LOW	ATA_SECT_NUM
+#define ATA_LBA_MID	ATA_CYL_LOW
+#define ATA_LBA_HIGH	ATA_CYL_HIGH
+#define ATA_LBA_SEL	ATA_DEV_CTL
+
+/*
+ * Status register bits
+ */
+#define ATA_STAT_BUSY	0x80	/* Device Busy			*/
+#define ATA_STAT_READY	0x40	/* Device Ready			*/
+#define ATA_STAT_FAULT	0x20	/* Device Fault			*/
+#define ATA_STAT_SEEK	0x10	/* Device Seek Complete		*/
+#define ATA_STAT_DRQ	0x08	/* Data Request (ready)		*/
+#define ATA_STAT_CORR	0x04	/* Corrected Data Error		*/
+#define ATA_STAT_INDEX	0x02	/* Vendor specific		*/
+#define ATA_STAT_ERR	0x01	/* Error			*/
+
+/*
+ * Device / Head Register Bits
+ */
+#ifndef ATA_DEVICE
+#define ATA_DEVICE(x)	((x & 1)<<4)
+#endif /* ATA_DEVICE */
+#define ATA_LBA		0xE0
+
+/*
+ * ATA Commands (only mandatory commands listed here)
+ */
+#define ATA_CMD_READ	0x20	/* Read Sectors (with retries)	*/
+#define ATA_CMD_READN	0x21	/* Read Sectors ( no  retries)	*/
+#define ATA_CMD_WRITE	0x30	/* Write Sectores (with retries)*/
+#define ATA_CMD_WRITEN	0x31	/* Write Sectors  ( no  retries)*/
+#define ATA_CMD_VRFY	0x40	/* Read Verify  (with retries)	*/
+#define ATA_CMD_VRFYN	0x41	/* Read verify  ( no  retries)	*/
+#define ATA_CMD_SEEK	0x70	/* Seek				*/
+#define ATA_CMD_DIAG	0x90	/* Execute Device Diagnostic	*/
+#define ATA_CMD_INIT	0x91	/* Initialize Device Parameters	*/
+#define ATA_CMD_RD_MULT	0xC4	/* Read Multiple		*/
+#define ATA_CMD_WR_MULT	0xC5	/* Write Multiple		*/
+#define ATA_CMD_SETMULT	0xC6	/* Set Multiple Mode		*/
+#define ATA_CMD_RD_DMA	0xC8	/* Read DMA (with retries)	*/
+#define ATA_CMD_RD_DMAN	0xC9	/* Read DMS ( no  retries)	*/
+#define ATA_CMD_WR_DMA	0xCA	/* Write DMA (with retries)	*/
+#define ATA_CMD_WR_DMAN	0xCB	/* Write DMA ( no  retires)	*/
+#define ATA_CMD_IDENT	0xEC	/* Identify Device		*/
+#define ATA_CMD_SETF	0xEF	/* Set Features			*/
+#define ATA_CMD_CHK_PWR	0xE5	/* Check Power Mode		*/
+
+#define ATA_CMD_READ_EXT 0x24	/* Read Sectors (with retries)	with 48bit addressing */
+#define ATA_CMD_WRITE_EXT	0x34	/* Write Sectores (with retries) with 48bit addressing */
+#define ATA_CMD_VRFY_EXT	0x42	/* Read Verify	(with retries)	with 48bit addressing */
+
+#define ATA_CMD_FLUSH 0xE7 /* Flush drive cache */
+#define ATA_CMD_FLUSH_EXT 0xEA /* Flush drive cache, with 48bit addressing */
+
+/*
+ * ATAPI Commands
+ */
+#define ATAPI_CMD_IDENT 0xA1 /* Identify AT Atachment Packed Interface Device */
+#define ATAPI_CMD_PACKET 0xA0 /* Packed Command */
+
+
+#define ATAPI_CMD_INQUIRY 0x12
+#define ATAPI_CMD_REQ_SENSE 0x03
+#define ATAPI_CMD_READ_CAP 0x25
+#define ATAPI_CMD_START_STOP 0x1B
+#define ATAPI_CMD_READ_12 0xA8
+
+
+#define ATA_GET_ERR()	inb(ATA_STATUS)
+#define ATA_GET_STAT()	inb(ATA_STATUS)
+#define ATA_OK_STAT(stat,good,bad)	(((stat)&((good)|(bad)))==(good))
+#define ATA_BAD_R_STAT	(ATA_STAT_BUSY	| ATA_STAT_ERR)
+#define ATA_BAD_W_STAT	(ATA_BAD_R_STAT	| ATA_STAT_FAULT)
+#define ATA_BAD_STAT	(ATA_BAD_R_STAT	| ATA_STAT_DRQ)
+#define ATA_DRIVE_READY	(ATA_READY_STAT	| ATA_STAT_SEEK)
+#define ATA_DATA_READY	(ATA_STAT_DRQ)
+
+#define ATA_BLOCKSIZE	512	/* bytes */
+#define ATA_BLOCKSHIFT	9	/* 2 ^ ATA_BLOCKSIZESHIFT = 512 */
+#define ATA_SECTORWORDS	(512 / sizeof(uint32_t))
+
+#ifndef ATA_RESET_TIME
+#define ATA_RESET_TIME	60	/* spec allows up to 31 seconds */
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * structure returned by ATA_CMD_IDENT, as per ANSI ATA2 rev.2f spec
+ */
+typedef struct hd_driveid {
+	unsigned short	config;		/* lots of obsolete bit flags */
+	unsigned short	cyls;		/* "physical" cyls */
+	unsigned short	reserved2;	/* reserved (word 2) */
+	unsigned short	heads;		/* "physical" heads */
+	unsigned short	track_bytes;	/* unformatted bytes per track */
+	unsigned short	sector_bytes;	/* unformatted bytes per sector */
+	unsigned short	sectors;	/* "physical" sectors per track */
+	unsigned short	vendor0;	/* vendor unique */
+	unsigned short	vendor1;	/* vendor unique */
+	unsigned short	vendor2;	/* vendor unique */
+	unsigned char	serial_no[20];	/* 0 = not_specified */
+	unsigned short	buf_type;
+	unsigned short	buf_size;	/* 512 byte increments; 0 = not_specified */
+	unsigned short	ecc_bytes;	/* for r/w long cmds; 0 = not_specified */
+	unsigned char	fw_rev[8];	/* 0 = not_specified */
+	unsigned char	model[40];	/* 0 = not_specified */
+	unsigned char	max_multsect;	/* 0=not_implemented */
+	unsigned char	vendor3;	/* vendor unique */
+	unsigned short	dword_io;	/* 0=not_implemented; 1=implemented */
+	unsigned char	vendor4;	/* vendor unique */
+	unsigned char	capability;	/* bits 0:DMA 1:LBA 2:IORDYsw 3:IORDYsup*/
+	unsigned short	reserved50;	/* reserved (word 50) */
+	unsigned char	vendor5;	/* vendor unique */
+	unsigned char	tPIO;		/* 0=slow, 1=medium, 2=fast */
+	unsigned char	vendor6;	/* vendor unique */
+	unsigned char	tDMA;		/* 0=slow, 1=medium, 2=fast */
+	unsigned short	field_valid;	/* bits 0:cur_ok 1:eide_ok */
+	unsigned short	cur_cyls;	/* logical cylinders */
+	unsigned short	cur_heads;	/* logical heads */
+	unsigned short	cur_sectors;	/* logical sectors per track */
+	unsigned short	cur_capacity0;	/* logical total sectors on drive */
+	unsigned short	cur_capacity1;	/*  (2 words, misaligned int)     */
+	unsigned char	multsect;	/* current multiple sector count */
+	unsigned char	multsect_valid;	/* when (bit0==1) multsect is ok */
+	unsigned int	lba_capacity;	/* total number of sectors */
+	unsigned short	dma_1word;	/* single-word dma info */
+	unsigned short	dma_mword;	/* multiple-word dma info */
+	unsigned short  eide_pio_modes; /* bits 0:mode3 1:mode4 */
+	unsigned short  eide_dma_min;	/* min mword dma cycle time (ns) */
+	unsigned short  eide_dma_time;	/* recommended mword dma cycle time (ns) */
+	unsigned short  eide_pio;       /* min cycle time (ns), no IORDY  */
+	unsigned short  eide_pio_iordy; /* min cycle time (ns), with IORDY */
+	unsigned short	words69_70[2];	/* reserved words 69-70 */
+	unsigned short	words71_74[4];	/* reserved words 71-74 */
+	unsigned short  queue_depth;	/*  */
+	unsigned short  words76_79[4];	/* reserved words 76-79 */
+	unsigned short  major_rev_num;	/*  */
+	unsigned short  minor_rev_num;	/*  */
+	unsigned short  command_set_1;	/* bits 0:Smart 1:Security 2:Removable 3:PM */
+	unsigned short	command_set_2;	/* bits 14:Smart Enabled 13:0 zero 10:lba48 support*/
+	unsigned short  cfsse;		/* command set-feature supported extensions */
+	unsigned short  cfs_enable_1;	/* command set-feature enabled */
+	unsigned short  cfs_enable_2;	/* command set-feature enabled */
+	unsigned short  csf_default;	/* command set-feature default */
+	unsigned short  dma_ultra;	/*  */
+	unsigned short	word89;		/* reserved (word 89) */
+	unsigned short	word90;		/* reserved (word 90) */
+	unsigned short	CurAPMvalues;	/* current APM values */
+	unsigned short	word92;		/* reserved (word 92) */
+	unsigned short	hw_config;	/* hardware config */
+	unsigned short	words94_99[6];/* reserved words 94-99 */
+	/*unsigned long long  lba48_capacity; /--* 4 16bit values containing lba 48 total number of sectors */
+	unsigned short	lba48_capacity[4]; /* 4 16bit values containing lba 48 total number of sectors */
+	unsigned short	words104_125[22];/* reserved words 104-125 */
+	unsigned short	last_lun;	/* reserved (word 126) */
+	unsigned short	word127;	/* reserved (word 127) */
+	unsigned short	dlf;		/* device lock function
+					 * 15:9	reserved
+					 * 8	security level 1:max 0:high
+					 * 7:6	reserved
+					 * 5	enhanced erase
+					 * 4	expire
+					 * 3	frozen
+					 * 2	locked
+					 * 1	en/disabled
+					 * 0	capability
+					 */
+	unsigned short  csfo;		/* current set features options
+					 * 15:4	reserved
+					 * 3	auto reassign
+					 * 2	reverting
+					 * 1	read-look-ahead
+					 * 0	write cache
+					 */
+	unsigned short	words130_155[26];/* reserved vendor words 130-155 */
+	unsigned short	word156;
+	unsigned short	words157_159[3];/* reserved vendor words 157-159 */
+	unsigned short	words160_162[3];/* reserved words 160-162 */
+	unsigned short	cf_advanced_caps;
+	unsigned short	words164_255[92];/* reserved words 164-255 */
+} hd_driveid_t;
+
+
+/*
+ * PIO Mode Configuration
+ *
+ * See ATA-3 (AT Attachment-3 Interface) documentation, Figure 14 / Table 21
+ */
+
+typedef struct {
+	unsigned int	t_setup;	/* Setup  Time in [ns] or clocks	*/
+	unsigned int	t_length;	/* Length Time in [ns] or clocks	*/
+	unsigned int	t_hold;		/* Hold   Time in [ns] or clocks	*/
+}
+pio_config_t;
+
+#define	IDE_MAX_PIO_MODE	4	/* max suppurted PIO mode		*/
+
+/* ------------------------------------------------------------------------- */
+
+#endif /* _ATA_H */
diff --git a/include/atf_common.h b/include/atf_common.h
new file mode 100644
index 0000000..3a7d40e
--- /dev/null
+++ b/include/atf_common.h
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * This is from the ARM TF Project,
+ * Repository: https://github.com/ARM-software/arm-trusted-firmware.git
+ * File: include/common/bl_common.h
+ * Portions copyright (c) 2013-2016, ARM Limited and Contributors. All rights
+ * reserved.
+ * Copyright (C) 2016-2017 Rockchip Electronic Co.,Ltd
+ */
+
+#ifndef __BL_COMMON_H__
+#define __BL_COMMON_H__
+
+#define ATF_PARAM_EP		0x01
+#define ATF_PARAM_IMAGE_BINARY	0x02
+#define ATF_PARAM_BL31		0x03
+
+#define ATF_VERSION_1	0x01
+
+#define ATF_EP_SECURE	0x0
+#define ATF_EP_NON_SECURE	0x1
+
+#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \
+	(_p)->h.type = (uint8_t)(_type); \
+	(_p)->h.version = (uint8_t)(_ver); \
+	(_p)->h.size = (uint16_t)sizeof(*_p); \
+	(_p)->h.attr = (uint32_t)(_attr) ; \
+	} while (0)
+
+#define MODE_RW_SHIFT	0x4
+#define MODE_RW_MASK	0x1
+#define MODE_RW_64	0x0
+#define MODE_RW_32	0x1
+
+#define MODE_EL_SHIFT	0x2
+#define MODE_EL_MASK	0x3
+#define MODE_EL3	0x3
+#define MODE_EL2	0x2
+#define MODE_EL1	0x1
+#define MODE_EL0	0x0
+
+#define MODE_SP_SHIFT	0x0
+#define MODE_SP_MASK	0x1
+#define MODE_SP_EL0	0x0
+#define MODE_SP_ELX	0x1
+
+#define SPSR_DAIF_SHIFT	6
+#define SPSR_DAIF_MASK	0x0f
+
+#define SPSR_64(el, sp, daif)		\
+	(MODE_RW_64 << MODE_RW_SHIFT |	\
+	 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT |	\
+	 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT |	\
+	 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
+
+#define SPSR_FIQ             (1 << 6)
+#define SPSR_IRQ             (1 << 7)
+#define SPSR_SERROR          (1 << 8)
+#define SPSR_DEBUG           (1 << 9)
+#define SPSR_EXCEPTION_MASK  (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG)
+
+#define DAIF_FIQ_BIT (1<<0)
+#define DAIF_IRQ_BIT (1<<1)
+#define DAIF_ABT_BIT (1<<2)
+#define DAIF_DBG_BIT (1<<3)
+#define DISABLE_ALL_EXECPTIONS	\
+	(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
+
+#ifndef __ASSEMBLY__
+
+/*******************************************************************************
+ * Structure used for telling the next BL how much of a particular type of
+ * memory is available for its use and how much is already used.
+ ******************************************************************************/
+struct aapcs64_params {
+	unsigned long arg0;
+	unsigned long arg1;
+	unsigned long arg2;
+	unsigned long arg3;
+	unsigned long arg4;
+	unsigned long arg5;
+	unsigned long arg6;
+	unsigned long arg7;
+};
+
+/***************************************************************************
+ * This structure provides version information and the size of the
+ * structure, attributes for the structure it represents
+ ***************************************************************************/
+struct param_header {
+	uint8_t type;		/* type of the structure */
+	uint8_t version;    /* version of this structure */
+	uint16_t size;      /* size of this structure in bytes */
+	uint32_t attr;      /* attributes: unused bits SBZ */
+};
+
+/*****************************************************************************
+ * This structure represents the superset of information needed while
+ * switching exception levels. The only two mechanisms to do so are
+ * ERET & SMC. Security state is indicated using bit zero of header
+ * attribute
+ * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
+ * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
+ * processing SMC to jump to BL31.
+ *****************************************************************************/
+struct entry_point_info {
+	struct param_header h;
+	uintptr_t pc;
+	uint32_t spsr;
+	struct aapcs64_params args;
+};
+
+/*****************************************************************************
+ * Image info binary provides information from the image loader that
+ * can be used by the firmware to manage available trusted RAM.
+ * More advanced firmware image formats can provide additional
+ * information that enables optimization or greater flexibility in the
+ * common firmware code
+ *****************************************************************************/
+struct atf_image_info {
+	struct param_header h;
+	uintptr_t image_base;   /* physical address of base of image */
+	uint32_t image_size;    /* bytes read from image file */
+};
+
+/*****************************************************************************
+ * The image descriptor struct definition.
+ *****************************************************************************/
+struct image_desc {
+	/* Contains unique image id for the image. */
+	unsigned int image_id;
+	/*
+	 * This member contains Image state information.
+	 * Refer IMAGE_STATE_XXX defined above.
+	 */
+	unsigned int state;
+	uint32_t copied_size;	/* image size copied in blocks */
+	struct atf_image_info atf_image_info;
+	struct entry_point_info ep_info;
+};
+
+/*******************************************************************************
+ * This structure represents the superset of information that can be passed to
+ * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
+ * populated only if BL2 detects its presence. A pointer to a structure of this
+ * type should be passed in X0 to BL31's cold boot entrypoint.
+ *
+ * Use of this structure and the X0 parameter is not mandatory: the BL31
+ * platform code can use other mechanisms to provide the necessary information
+ * about BL32 and BL33 to the common and SPD code.
+ *
+ * BL31 image information is mandatory if this structure is used. If either of
+ * the optional BL32 and BL33 image information is not provided, this is
+ * indicated by the respective image_info pointers being zero.
+ ******************************************************************************/
+struct bl31_params {
+	struct param_header h;
+	struct atf_image_info *bl31_image_info;
+	struct entry_point_info *bl32_ep_info;
+	struct atf_image_info *bl32_image_info;
+	struct entry_point_info *bl33_ep_info;
+	struct atf_image_info *bl33_image_info;
+};
+
+/*******************************************************************************
+ * This structure represents the superset of information that is passed to
+ * BL31, e.g. while passing control to it from BL2, bl31_params
+ * and other platform specific params
+ ******************************************************************************/
+struct bl2_to_bl31_params_mem {
+	struct bl31_params bl31_params;
+	struct atf_image_info bl31_image_info;
+	struct atf_image_info bl32_image_info;
+	struct atf_image_info bl33_image_info;
+	struct entry_point_info bl33_ep_info;
+	struct entry_point_info bl32_ep_info;
+	struct entry_point_info bl31_ep_info;
+};
+
+#endif /*__ASSEMBLY__*/
+
+#endif /* __BL_COMMON_H__ */
diff --git a/include/atmel_hlcdc.h b/include/atmel_hlcdc.h
new file mode 100644
index 0000000..5e339f5
--- /dev/null
+++ b/include/atmel_hlcdc.h
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Header file for AT91/AT32 MULTI LAYER LCD Controller
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2012 Atmel Corporation
+ */
+#ifndef __ATMEL_HLCDC_H__
+#define __ATMEL_HLCDC_H__
+
+/* Atmel multi layer lcdc hardware registers */
+struct atmel_hlcd_regs {
+	u32	lcdc_lcdcfg0;
+	u32	lcdc_lcdcfg1;
+	u32	lcdc_lcdcfg2;
+	u32	lcdc_lcdcfg3;
+	u32	lcdc_lcdcfg4;
+	u32	lcdc_lcdcfg5;
+	u32	lcdc_lcdcfg6;
+	u32	res1;
+	u32	lcdc_lcden;
+	u32	lcdc_lcddis;
+	u32	lcdc_lcdsr;
+	u32	res2;
+	u32	lcdc_lcdidr;
+	u32	res3[3];
+	u32	lcdc_basecher;
+	u32	res4[3];
+	u32	lcdc_baseidr;
+	u32	res5[3];
+	u32	lcdc_baseaddr;
+	u32	lcdc_basectrl;
+	u32	lcdc_basenext;
+	u32	lcdc_basecfg0;
+	u32	lcdc_basecfg1;
+	u32	lcdc_basecfg2;
+	u32	lcdc_basecfg3;
+	u32	lcdc_basecfg4;
+};
+
+#define LCDC_LCDCFG0_CLKPOL	(0x1 << 0)
+#define LCDC_LCDCFG0_CLKSEL	(0x1 << 2)
+#define LCDC_LCDCFG0_CLKPWMSEL	(0x1 << 3)
+#define LCDC_LCDCFG0_CGDISBASE	(0x1 << 8)
+#define LCDC_LCDCFG0_CGDISOVR1	(0x1 << 9)
+#define LCDC_LCDCFG0_CGDISHEO	(0x1 << 11)
+#define LCDC_LCDCFG0_CGDISHCR	(0x1 << 12)
+#define LCDC_LCDCFG0_CLKDIV_Pos	16
+#define LCDC_LCDCFG0_CLKDIV_Msk	(0xff << LCDC_LCDCFG0_CLKDIV_Pos)
+#define LCDC_LCDCFG0_CLKDIV(value) \
+	((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
+
+#define LCDC_LCDCFG1_HSPW_Pos	0
+#define LCDC_LCDCFG1_HSPW_Msk	(0x3f << LCDC_LCDCFG1_HSPW_Pos)
+#define LCDC_LCDCFG1_HSPW(value) \
+	((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
+#define LCDC_LCDCFG1_VSPW_Pos	16
+#define LCDC_LCDCFG1_VSPW_Msk	(0x3f << LCDC_LCDCFG1_VSPW_Pos)
+#define LCDC_LCDCFG1_VSPW(value) \
+	((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
+
+#define LCDC_LCDCFG2_VFPW_Pos	0
+#define LCDC_LCDCFG2_VFPW_Msk	(0x3f << LCDC_LCDCFG2_VFPW_Pos)
+#define LCDC_LCDCFG2_VFPW(value) \
+	((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
+#define LCDC_LCDCFG2_VBPW_Pos	16
+#define LCDC_LCDCFG2_VBPW_Msk	(0x3f << LCDC_LCDCFG2_VBPW_Pos)
+#define LCDC_LCDCFG2_VBPW(value) \
+	((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
+
+#define LCDC_LCDCFG3_HFPW_Pos	0
+#define LCDC_LCDCFG3_HFPW_Msk	(0xff << LCDC_LCDCFG3_HFPW_Pos)
+#define LCDC_LCDCFG3_HFPW(value) \
+	((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
+#define LCDC_LCDCFG3_HBPW_Pos	16
+#define LCDC_LCDCFG3_HBPW_Msk	(0xff << LCDC_LCDCFG3_HBPW_Pos)
+#define LCDC_LCDCFG3_HBPW(value) \
+	((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
+
+#define LCDC_LCDCFG4_PPL_Pos	0
+#define LCDC_LCDCFG4_PPL_Msk	(0x7ff << LCDC_LCDCFG4_PPL_Pos)
+#define LCDC_LCDCFG4_PPL(value) \
+	((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
+#define LCDC_LCDCFG4_RPF_Pos	16
+#define LCDC_LCDCFG4_RPF_Msk	(0x7ff << LCDC_LCDCFG4_RPF_Pos)
+#define LCDC_LCDCFG4_RPF(value) \
+	((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
+
+#define LCDC_LCDCFG5_HSPOL	(0x1 << 0)
+#define LCDC_LCDCFG5_VSPOL	(0x1 << 1)
+#define LCDC_LCDCFG5_VSPDLYS	(0x1 << 2)
+#define LCDC_LCDCFG5_VSPDLYE	(0x1 << 3)
+#define LCDC_LCDCFG5_DISPPOL	(0x1 << 4)
+#define LCDC_LCDCFG5_SERIAL	(0x1 << 5)
+#define LCDC_LCDCFG5_DITHER	(0x1 << 6)
+#define LCDC_LCDCFG5_DISPDLY	(0x1 << 7)
+#define LCDC_LCDCFG5_MODE_Pos	8
+#define LCDC_LCDCFG5_MODE_Msk	(0x3 << LCDC_LCDCFG5_MODE_Pos)
+#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP	(0x0 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP	(0x1 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP	(0x2 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP	(0x3 << 8)
+#define LCDC_LCDCFG5_VSPSU		(0x1 << 12)
+#define LCDC_LCDCFG5_VSPHO		(0x1 << 13)
+#define LCDC_LCDCFG5_GUARDTIME_Pos	16
+#define LCDC_LCDCFG5_GUARDTIME_Msk	(0x1f << LCDC_LCDCFG5_GUARDTIME_Pos)
+#define LCDC_LCDCFG5_GUARDTIME(value) \
+	((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
+
+#define LCDC_LCDCFG6_PWMPS_Pos		0
+#define LCDC_LCDCFG6_PWMPS_Msk		(0x7 << LCDC_LCDCFG6_PWMPS_Pos)
+#define LCDC_LCDCFG6_PWMPS(value) \
+	((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
+#define LCDC_LCDCFG6_PWMPOL		(0x1 << 4)
+#define LCDC_LCDCFG6_PWMCVAL_Pos	8
+#define LCDC_LCDCFG6_PWMCVAL_Msk	(0xff << LCDC_LCDCFG6_PWMCVAL_Pos)
+#define LCDC_LCDCFG6_PWMCVAL(value) \
+	((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
+
+#define LCDC_LCDEN_CLKEN	(0x1 << 0)
+#define LCDC_LCDEN_SYNCEN	(0x1 << 1)
+#define LCDC_LCDEN_DISPEN	(0x1 << 2)
+#define LCDC_LCDEN_PWMEN	(0x1 << 3)
+
+#define LCDC_LCDDIS_CLKDIS	(0x1 << 0)
+#define LCDC_LCDDIS_SYNCDIS	(0x1 << 1)
+#define LCDC_LCDDIS_DISPDIS	(0x1 << 2)
+#define LCDC_LCDDIS_PWMDIS	(0x1 << 3)
+#define LCDC_LCDDIS_CLKRST	(0x1 << 8)
+#define LCDC_LCDDIS_SYNCRST	(0x1 << 9)
+#define LCDC_LCDDIS_DISPRST	(0x1 << 10)
+#define LCDC_LCDDIS_PWMRST	(0x1 << 11)
+
+#define LCDC_LCDSR_CLKSTS	(0x1 << 0)
+#define LCDC_LCDSR_LCDSTS	(0x1 << 1)
+#define LCDC_LCDSR_DISPSTS	(0x1 << 2)
+#define LCDC_LCDSR_PWMSTS	(0x1 << 3)
+#define LCDC_LCDSR_SIPSTS	(0x1 << 4)
+
+#define LCDC_LCDIDR_SOFID	(0x1 << 0)
+#define LCDC_LCDIDR_DISID	(0x1 << 1)
+#define LCDC_LCDIDR_DISPID	(0x1 << 2)
+#define LCDC_LCDIDR_FIFOERRID	(0x1 << 4)
+#define LCDC_LCDIDR_BASEID	(0x1 << 8)
+#define LCDC_LCDIDR_OVR1ID	(0x1 << 9)
+#define LCDC_LCDIDR_HEOID	(0x1 << 11)
+#define LCDC_LCDIDR_HCRID	(0x1 << 12)
+
+#define LCDC_BASECHER_CHEN	(0x1 << 0)
+#define LCDC_BASECHER_UPDATEEN	(0x1 << 1)
+#define LCDC_BASECHER_A2QEN	(0x1 << 2)
+
+#define LCDC_BASEIDR_DMA	(0x1 << 2)
+#define LCDC_BASEIDR_DSCR	(0x1 << 3)
+#define LCDC_BASEIDR_ADD	(0x1 << 4)
+#define LCDC_BASEIDR_DONE	(0x1 << 5)
+#define LCDC_BASEIDR_OVR	(0x1 << 6)
+
+#define LCDC_BASECTRL_DFETCH	(0x1 << 0)
+#define LCDC_BASECTRL_LFETCH	(0x1 << 1)
+#define LCDC_BASECTRL_DMAIEN	(0x1 << 2)
+#define LCDC_BASECTRL_DSCRIEN	(0x1 << 3)
+#define LCDC_BASECTRL_ADDIEN	(0x1 << 4)
+#define LCDC_BASECTRL_DONEIEN	(0x1 << 5)
+
+#define LCDC_BASECFG0_BLEN_Pos		4
+#define LCDC_BASECFG0_BLEN_AHB_SINGLE	(0x0 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR4	(0x1 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR8	(0x2 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR16	(0x3 << 4)
+#define LCDC_BASECFG0_DLBO		(0x1 << 8)
+
+#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444		(0x0 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444		(0x1 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444		(0x2 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565		(0x3 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555		(0x4 << 4)
+#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666		(0x5 << 4)
+#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
+#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666		(0x7 << 4)
+#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED		(0x8 << 4)
+#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888		(0x9 << 4)
+#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
+#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888		(0xB << 4)
+#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888		(0xC << 4)
+#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888		(0xD << 4)
+
+#define LCDC_BASECFG2_XSTRIDE_Pos 0
+#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos)
+#define LCDC_BASECFG2_XSTRIDE(value) \
+	((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
+
+#define LCDC_BASECFG3_BDEF_Pos	0
+#define LCDC_BASECFG3_BDEF_Msk	(0xff << LCDC_BASECFG3_BDEF_Pos)
+#define LCDC_BASECFG3_BDEF(value) \
+	((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
+#define LCDC_BASECFG3_GDEF_Pos	8
+#define LCDC_BASECFG3_GDEF_Msk	(0xff << LCDC_BASECFG3_GDEF_Pos)
+#define LCDC_BASECFG3_GDEF(value) \
+	((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
+#define LCDC_BASECFG3_RDEF_Pos	16
+#define LCDC_BASECFG3_RDEF_Msk	(0xff << LCDC_BASECFG3_RDEF_Pos)
+#define LCDC_BASECFG3_RDEF(value) \
+	((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
+
+#define LCDC_BASECLUT_BCLUT_Pos 0
+#define LCDC_BASECLUT_BCLUT_Msk (0xff << LCDC_BASECLUT_BCLUT_Pos)
+#define LCDC_BASECLUT_GCLUT_Pos 8
+#define LCDC_BASECLUT_GCLUT_Msk (0xff << LCDC_BASECLUT_GCLUT_Pos)
+#define LCDC_BASECLUT_RCLUT_Pos 16
+#define LCDC_BASECLUT_RCLUT_Msk (0xff << LCDC_BASECLUT_RCLUT_Pos)
+
+#define LCDC_BASECFG4_DMA	(0x1 << 8)
+#define LCDC_BASECFG4_REP	(0x1 << 9)
+
+struct lcd_dma_desc {
+	u32	address;
+	u32	control;
+	u32	next;
+};
+
+#define ATMEL_LCDC_LUT(n)	(0x0400 + ((n)*4))
+
+#endif /* __ATMEL_HLCDC_H__ */
diff --git a/include/atmel_lcd.h b/include/atmel_lcd.h
new file mode 100644
index 0000000..4aa955b
--- /dev/null
+++ b/include/atmel_lcd.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * atmel_lcd.h - Atmel LCD Controller structures
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef _ATMEL_LCD_H_
+#define _ATMEL_LCD_H_
+
+/**
+ * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model
+ *
+ * @timing_index:	Index of LCD timing to use in device tree node
+ */
+struct atmel_lcd_platdata {
+	int timing_index;
+};
+
+typedef struct vidinfo {
+	ushort vl_col;		/* Number of columns (i.e. 640) */
+	ushort vl_row;		/* Number of rows (i.e. 480) */
+	ushort vl_rot;		/* Rotation of Display (0, 1, 2, 3) */
+	u_long vl_clk;		/* pixel clock in ps    */
+
+	/* LCD configuration register */
+	u_long vl_sync;		/* Horizontal / vertical sync */
+	u_long vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
+	u_long vl_tft;		/* 0 = passive, 1 = TFT */
+	u_long vl_cont_pol_low;	/* contrast polarity is low */
+	u_long vl_clk_pol;	/* clock polarity */
+
+	/* Horizontal control register. */
+	u_long vl_hsync_len;	/* Length of horizontal sync */
+	u_long vl_left_margin;	/* Time from sync to picture */
+	u_long vl_right_margin;	/* Time from picture to sync */
+
+	/* Vertical control register. */
+	u_long vl_vsync_len;	/* Length of vertical sync */
+	u_long vl_upper_margin;	/* Time from sync to picture */
+	u_long vl_lower_margin;	/* Time from picture to sync */
+
+	u_long	mmio;		/* Memory mapped registers */
+
+	u_int logo_width;
+	u_int logo_height;
+	int logo_x_offset;
+	int logo_y_offset;
+	u_long logo_addr;
+} vidinfo_t;
+
+void atmel_logo_info(vidinfo_t *info);
+void microchip_logo_info(vidinfo_t *info);
+
+#endif
diff --git a/include/atmel_lcdc.h b/include/atmel_lcdc.h
new file mode 100644
index 0000000..759f8da
--- /dev/null
+++ b/include/atmel_lcdc.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Header file for AT91/AT32 LCD Controller
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ */
+#ifndef __ATMEL_LCDC_H__
+#define __ATMEL_LCDC_H__
+
+#define ATMEL_LCDC_DMABADDR1	0x00
+#define ATMEL_LCDC_DMABADDR2	0x04
+#define ATMEL_LCDC_DMAFRMPT1	0x08
+#define ATMEL_LCDC_DMAFRMPT2	0x0c
+#define ATMEL_LCDC_DMAFRMADD1	0x10
+#define ATMEL_LCDC_DMAFRMADD2	0x14
+
+#define ATMEL_LCDC_DMAFRMCFG	0x18
+#define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
+#define	ATMEL_LCDC_BLENGTH_OFFSET	24
+#define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
+
+#define ATMEL_LCDC_DMACON	0x1c
+#define	ATMEL_LCDC_DMAEN	(0x1 << 0)
+#define	ATMEL_LCDC_DMARST	(0x1 << 1)
+#define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
+#define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
+#define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
+
+#define ATMEL_LCDC_DMA2DCFG	0x20
+#define		ATMEL_LCDC_ADDRINC_OFFSET	0
+#define		ATMEL_LCDC_ADDRINC		(0xffff)
+#define		ATMEL_LCDC_PIXELOFF_OFFSET	24
+#define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
+
+#define ATMEL_LCDC_LCDCON1	0x0800
+#define	ATMEL_LCDC_BYPASS	(1     <<  0)
+#define	ATMEL_LCDC_CLKVAL_OFFSET	12
+#define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
+#define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
+
+#define ATMEL_LCDC_LCDCON2	0x0804
+#define	ATMEL_LCDC_DISTYPE	(3 << 0)
+#define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
+#define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
+#define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
+#define	ATMEL_LCDC_SCANMOD	(1 << 2)
+#define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
+#define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
+#define	ATMEL_LCDC_IFWIDTH	(3 << 3)
+#define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
+#define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
+#define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
+#define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
+#define	ATMEL_LCDC_INVVD	(1 << 8)
+#define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
+#define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
+#define	ATMEL_LCDC_INVFRAME	(1 << 9 )
+#define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
+#define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
+#define	ATMEL_LCDC_INVLINE	(1 << 10)
+#define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
+#define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
+#define	ATMEL_LCDC_INVCLK	(1 << 11)
+#define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
+#define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
+#define	ATMEL_LCDC_INVDVAL	(1 << 12)
+#define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
+#define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
+#define	ATMEL_LCDC_CLKMOD	(1 << 15)
+#define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
+#define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
+#define	ATMEL_LCDC_MEMOR	(1 << 31)
+#define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
+#define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
+
+#define ATMEL_LCDC_TIM1		0x0808
+#define	ATMEL_LCDC_VFP		(0xffU <<  0)
+#define	ATMEL_LCDC_VBP_OFFSET		8
+#define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
+#define	ATMEL_LCDC_VPW_OFFSET		16
+#define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
+#define	ATMEL_LCDC_VHDLY_OFFSET		24
+#define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
+
+#define ATMEL_LCDC_TIM2		0x080c
+#define	ATMEL_LCDC_HBP		(0xffU  <<  0)
+#define	ATMEL_LCDC_HPW_OFFSET		8
+#define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
+#define	ATMEL_LCDC_HFP_OFFSET		21
+#define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
+
+#define ATMEL_LCDC_LCDFRMCFG	0x0810
+#define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
+#define	ATMEL_LCDC_HOZVAL_OFFSET	21
+#define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
+
+#define ATMEL_LCDC_FIFO		0x0814
+#define	ATMEL_LCDC_FIFOTH	(0xffff)
+
+#define ATMEL_LCDC_MVAL		0x0818
+
+#define ATMEL_LCDC_DP1_2	0x081c
+#define ATMEL_LCDC_DP4_7	0x0820
+#define ATMEL_LCDC_DP3_5	0x0824
+#define ATMEL_LCDC_DP2_3	0x0828
+#define ATMEL_LCDC_DP5_7	0x082c
+#define ATMEL_LCDC_DP3_4	0x0830
+#define ATMEL_LCDC_DP4_5	0x0834
+#define ATMEL_LCDC_DP6_7	0x0838
+#define	ATMEL_LCDC_DP1_2_VAL	(0xff)
+#define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
+#define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
+#define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
+#define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
+#define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
+#define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
+#define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
+
+#define ATMEL_LCDC_PWRCON	0x083c
+#define	ATMEL_LCDC_PWR		(1    <<  0)
+#define	ATMEL_LCDC_GUARDT_OFFSET	1
+#define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
+#define	ATMEL_LCDC_BUSY		(1    << 31)
+
+#define ATMEL_LCDC_CONTRAST_CTR	0x0840
+#define	ATMEL_LCDC_PS		(3 << 0)
+#define		ATMEL_LCDC_PS_DIV1		(0 << 0)
+#define		ATMEL_LCDC_PS_DIV2		(1 << 0)
+#define		ATMEL_LCDC_PS_DIV4		(2 << 0)
+#define		ATMEL_LCDC_PS_DIV8		(3 << 0)
+#define	ATMEL_LCDC_POL		(1 << 2)
+#define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
+#define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
+#define	ATMEL_LCDC_ENA		(1 << 3)
+#define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
+#define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
+
+#define ATMEL_LCDC_CONTRAST_VAL	0x0844
+#define	ATMEL_LCDC_CVAL	(0xff)
+
+#define ATMEL_LCDC_IER		0x0848
+#define ATMEL_LCDC_IDR		0x084c
+#define ATMEL_LCDC_IMR		0x0850
+#define ATMEL_LCDC_ISR		0x0854
+#define ATMEL_LCDC_ICR		0x0858
+#define	ATMEL_LCDC_LNI		(1 << 0)
+#define	ATMEL_LCDC_LSTLNI	(1 << 1)
+#define	ATMEL_LCDC_EOFI		(1 << 2)
+#define	ATMEL_LCDC_UFLWI	(1 << 4)
+#define	ATMEL_LCDC_OWRI		(1 << 5)
+#define	ATMEL_LCDC_MERI		(1 << 6)
+
+#define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
+
+#endif /* __ATMEL_LCDC_H__ */
diff --git a/include/atmel_mci.h b/include/atmel_mci.h
new file mode 100644
index 0000000..c759116
--- /dev/null
+++ b/include/atmel_mci.h
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ */
+#ifndef __ATMEL_MCI_H__
+#define __ATMEL_MCI_H__
+
+int atmel_mci_init(void *regs);
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Structure for struct SoC access.
+ * Names starting with '_' are fillers.
+ */
+typedef struct atmel_mci {
+	/*	reg	Offset */
+	u32	cr;	/* 0x00 */
+	u32	mr;	/* 0x04 */
+	u32	dtor;	/* 0x08 */
+	u32	sdcr;	/* 0x0c */
+	u32	argr;	/* 0x10 */
+	u32	cmdr;	/* 0x14 */
+	u32	blkr;	/* 0x18 */
+	u32	_1c;	/* 0x1c */
+	u32	rspr;	/* 0x20 */
+	u32	rspr1;	/* 0x24 */
+	u32	rspr2;	/* 0x28 */
+	u32	rspr3;	/* 0x2c */
+	u32	rdr;	/* 0x30 */
+	u32	tdr;	/* 0x34 */
+	u32	_38;	/* 0x38 */
+	u32	_3c;	/* 0x3c */
+	u32	sr;	/* 0x40 */
+	u32	ier;	/* 0x44 */
+	u32	idr;	/* 0x48 */
+	u32	imr;	/* 0x4c */
+	u32	dma;	/* 0x50 */
+	u32	cfg;	/* 0x54 */
+	u32	reserved[41];
+	u32	version;
+} atmel_mci_t;
+
+#endif /* __ASSEMBLY__ */
+
+/* Bitfields in CR */
+#define MMCI_MCIEN_OFFSET			0
+#define MMCI_MCIEN_SIZE				1
+#define MMCI_MCIDIS_OFFSET			1
+#define MMCI_MCIDIS_SIZE			1
+#define MMCI_PWSEN_OFFSET			2
+#define MMCI_PWSEN_SIZE				1
+#define MMCI_PWSDIS_OFFSET			3
+#define MMCI_PWSDIS_SIZE			1
+#define MMCI_SWRST_OFFSET			7
+#define MMCI_SWRST_SIZE				1
+
+/* Bitfields in MR */
+#define MMCI_CLKDIV_OFFSET			0
+#define MMCI_CLKDIV_SIZE			8
+#define MMCI_PWSDIV_OFFSET			8
+#define MMCI_PWSDIV_SIZE			3
+#define MMCI_RDPROOF_OFFSET			11
+#define MMCI_RDPROOF_SIZE			1
+#define MMCI_WRPROOF_OFFSET			12
+#define MMCI_WRPROOF_SIZE			1
+#define MMCI_PDCPADV_OFFSET			14
+#define MMCI_PDCPADV_SIZE			1
+#define MMCI_PDCMODE_OFFSET			15
+#define MMCI_PDCMODE_SIZE			1
+/* MCI IP version >= 0x500, MR bit 16 used for CLKODD */
+#define MMCI_CLKODD_OFFSET			16
+#define MMCI_CLKODD_SIZE			1
+/* MCI IP version < 0x200, MR higher 16bits for BLKLEN */
+#define MMCI_BLKLEN_OFFSET			16
+#define MMCI_BLKLEN_SIZE			16
+
+/* Bitfields in DTOR */
+#define MMCI_DTOCYC_OFFSET			0
+#define MMCI_DTOCYC_SIZE			4
+#define MMCI_DTOMUL_OFFSET			4
+#define MMCI_DTOMUL_SIZE			3
+
+/* Bitfields in SDCR */
+#define MMCI_SCDSEL_OFFSET			0
+#define MMCI_SCDSEL_SIZE			4
+#define MMCI_SCDBUS_OFFSET			7
+#define MMCI_SCDBUS_SIZE			1
+
+/* Bitfields in ARGR */
+#define MMCI_ARG_OFFSET				0
+#define MMCI_ARG_SIZE				32
+
+/* Bitfields in CMDR */
+#define MMCI_CMDNB_OFFSET			0
+#define MMCI_CMDNB_SIZE				6
+#define MMCI_RSPTYP_OFFSET			6
+#define MMCI_RSPTYP_SIZE			2
+#define MMCI_SPCMD_OFFSET			8
+#define MMCI_SPCMD_SIZE				3
+#define MMCI_OPDCMD_OFFSET			11
+#define MMCI_OPDCMD_SIZE			1
+#define MMCI_MAXLAT_OFFSET			12
+#define MMCI_MAXLAT_SIZE			1
+#define MMCI_TRCMD_OFFSET			16
+#define MMCI_TRCMD_SIZE				2
+#define MMCI_TRDIR_OFFSET			18
+#define MMCI_TRDIR_SIZE				1
+#define MMCI_TRTYP_OFFSET			19
+#define MMCI_TRTYP_SIZE				2
+
+/* Bitfields in BLKR */
+/* MMCI_BLKLEN_OFFSET/SIZE already defined in MR */
+#define MMCI_BCNT_OFFSET			0
+#define MMCI_BCNT_SIZE			16
+
+/* Bitfields in RSPRx */
+#define MMCI_RSP_OFFSET				0
+#define MMCI_RSP_SIZE				32
+
+/* Bitfields in SR/IER/IDR/IMR */
+#define MMCI_CMDRDY_OFFSET			0
+#define MMCI_CMDRDY_SIZE			1
+#define MMCI_RXRDY_OFFSET			1
+#define MMCI_RXRDY_SIZE				1
+#define MMCI_TXRDY_OFFSET			2
+#define MMCI_TXRDY_SIZE				1
+#define MMCI_BLKE_OFFSET			3
+#define MMCI_BLKE_SIZE				1
+#define MMCI_DTIP_OFFSET			4
+#define MMCI_DTIP_SIZE				1
+#define MMCI_NOTBUSY_OFFSET			5
+#define MMCI_NOTBUSY_SIZE			1
+#define MMCI_ENDRX_OFFSET			6
+#define MMCI_ENDRX_SIZE				1
+#define MMCI_ENDTX_OFFSET			7
+#define MMCI_ENDTX_SIZE				1
+#define MMCI_RXBUFF_OFFSET			14
+#define MMCI_RXBUFF_SIZE			1
+#define MMCI_TXBUFE_OFFSET			15
+#define MMCI_TXBUFE_SIZE			1
+#define MMCI_RINDE_OFFSET			16
+#define MMCI_RINDE_SIZE				1
+#define MMCI_RDIRE_OFFSET			17
+#define MMCI_RDIRE_SIZE				1
+#define MMCI_RCRCE_OFFSET			18
+#define MMCI_RCRCE_SIZE				1
+#define MMCI_RENDE_OFFSET			19
+#define MMCI_RENDE_SIZE				1
+#define MMCI_RTOE_OFFSET			20
+#define MMCI_RTOE_SIZE				1
+#define MMCI_DCRCE_OFFSET			21
+#define MMCI_DCRCE_SIZE				1
+#define MMCI_DTOE_OFFSET			22
+#define MMCI_DTOE_SIZE				1
+#define MMCI_OVRE_OFFSET			30
+#define MMCI_OVRE_SIZE				1
+#define MMCI_UNRE_OFFSET			31
+#define MMCI_UNRE_SIZE				1
+
+/* Constants for DTOMUL */
+#define MMCI_DTOMUL_1_CYCLE			0
+#define MMCI_DTOMUL_16_CYCLES			1
+#define MMCI_DTOMUL_128_CYCLES			2
+#define MMCI_DTOMUL_256_CYCLES			3
+#define MMCI_DTOMUL_1024_CYCLES			4
+#define MMCI_DTOMUL_4096_CYCLES			5
+#define MMCI_DTOMUL_65536_CYCLES		6
+#define MMCI_DTOMUL_1048576_CYCLES		7
+
+/* Constants for RSPTYP */
+#define MMCI_RSPTYP_NO_RESP			0
+#define MMCI_RSPTYP_48_BIT_RESP			1
+#define MMCI_RSPTYP_136_BIT_RESP		2
+
+/* Constants for SPCMD */
+#define MMCI_SPCMD_NO_SPEC_CMD			0
+#define MMCI_SPCMD_INIT_CMD			1
+#define MMCI_SPCMD_SYNC_CMD			2
+#define MMCI_SPCMD_INT_CMD			4
+#define MMCI_SPCMD_INT_RESP			5
+
+/* Constants for TRCMD */
+#define MMCI_TRCMD_NO_TRANS			0
+#define MMCI_TRCMD_START_TRANS			1
+#define MMCI_TRCMD_STOP_TRANS			2
+
+/* Constants for TRTYP */
+#define MMCI_TRTYP_BLOCK			0
+#define MMCI_TRTYP_MULTI_BLOCK			1
+#define MMCI_TRTYP_STREAM			2
+
+/* Bitfields in CFG */
+#define MMCI_FIFOMODE_OFFSET			0
+#define MMCI_FIFOMODE_SIZE			1
+#define MMCI_FERRCTRL_OFFSET			4
+#define MMCI_FERRCTRL_SIZE			1
+#define MMCI_HSMODE_OFFSET			8
+#define MMCI_HSMODE_SIZE			1
+#define MMCI_LSYNC_OFFSET			12
+#define MMCI_LSYNC_SIZE				1
+
+/* Bit manipulation macros */
+#define MMCI_BIT(name)					\
+	(1 << MMCI_##name##_OFFSET)
+#define MMCI_BF(name,value)				\
+	(((value) & ((1 << MMCI_##name##_SIZE) - 1))	\
+	 << MMCI_##name##_OFFSET)
+#define MMCI_BFEXT(name,value)				\
+	(((value) >> MMCI_##name##_OFFSET)\
+	 & ((1 << MMCI_##name##_SIZE) - 1))
+#define MMCI_BFINS(name,value,old)			\
+	(((old) & ~(((1 << MMCI_##name##_SIZE) - 1)	\
+		    << MMCI_##name##_OFFSET))		\
+	 | MMCI_BF(name,value))
+
+#endif /* __ATMEL_MCI_H__ */
diff --git a/include/atsha204a-i2c.h b/include/atsha204a-i2c.h
new file mode 100644
index 0000000..344fd8a
--- /dev/null
+++ b/include/atsha204a-i2c.h
@@ -0,0 +1,69 @@
+/*
+ * I2C Driver for Atmel ATSHA204 over I2C
+ *
+ * Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com
+ * 		 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com
+ * 		 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ATSHA204_I2C_H_
+#define _ATSHA204_I2C_H_
+
+enum atsha204a_zone
+{
+	ATSHA204A_ZONE_CONFIG	= 0,
+	ATSHA204A_ZONE_OTP	= 1,
+	ATSHA204A_ZONE_DATA	= 2,
+};
+
+enum atsha204a_status
+{
+	ATSHA204A_STATUS_SUCCESS	= 0x00,
+	ATSHA204A_STATUS_MISCOMPARE	= 0x01,
+	ATSHA204A_STATUS_PARSE_ERROR	= 0x03,
+	ATSHA204A_STATUS_EXEC_ERROR	= 0x0F,
+	ATSHA204A_STATUS_AFTER_WAKE	= 0x11,
+	ATSHA204A_STATUS_CRC_ERROR	= 0xFF,
+};
+
+enum atsha204a_func
+{
+	ATSHA204A_FUNC_RESET	= 0x00,
+	ATSHA204A_FUNC_SLEEP	= 0x01,
+	ATSHA204A_FUNC_IDLE	= 0x02,
+	ATSHA204A_FUNC_COMMAND	= 0x03,
+};
+
+enum atsha204a_cmd
+{
+	ATSHA204A_CMD_READ	= 0x02,
+	ATSHA204A_CMD_RANDOM	= 0x1B,
+};
+
+struct atsha204a_resp
+{
+	u8 length;
+	u8 code;
+	u8 data[82];
+} __attribute__ ((packed));
+
+struct atsha204a_req
+{
+	u8 function;
+	u8 length;
+	u8 command;
+	u8 param1;
+	u16 param2;
+	u8 data[78];
+} __attribute__ ((packed));
+
+int atsha204a_wakeup(struct udevice *);
+int atsha204a_idle(struct udevice *);
+int atsha204a_sleep(struct udevice *);
+int atsha204a_read(struct udevice *, enum atsha204a_zone, bool, u16, u8 *);
+int atsha204a_get_random(struct udevice *, u8 *, size_t);
+
+#endif /* _ATSHA204_I2C_H_ */
diff --git a/include/audio_codec.h b/include/audio_codec.h
new file mode 100644
index 0000000..2587099
--- /dev/null
+++ b/include/audio_codec.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __AUDIO_CODEC_H__
+#define __AUDIO_CODEC_H__
+
+/*
+ * An audio codec turns digital data into sound with various parameters to
+ * control its operation.
+ */
+
+/* Operations for sound */
+struct audio_codec_ops {
+	/**
+	 * set_params() - Set audio codec parameters
+	 *
+	 * @dev: Sound device
+	 * @inteface: Interface number to use on codec
+	 * @rate: Sampling rate in Hz
+	 * @mclk_freq: Codec clock frequency in Hz
+	 * @bits_per_sample: Must be 16 or 24
+	 * @channels: Number of channels to use (1=mono, 2=stereo)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_params)(struct udevice *dev, int interface, int rate,
+			  int mclk_freq, int bits_per_sample, uint channels);
+};
+
+#define audio_codec_get_ops(dev) ((struct audio_codec_ops *)(dev)->driver->ops)
+
+/**
+ * audio_codec_set_params() - Set audio codec parameters
+ *
+ * @dev: Sound device
+ * @inteface: Interface number to use on codec
+ * @rate: Sampling rate in Hz
+ * @mclk_freq: Codec clock frequency in Hz
+ * @bits_per_sample: Must be 16 or 24
+ * @channels: Number of channels to use (1=mono, 2=stereo)
+ * @return 0 if OK, -ve on error
+ */
+int audio_codec_set_params(struct udevice *dev, int interface, int rate,
+			   int mclk_freq, int bits_per_sample, uint channels);
+
+#endif  /* __AUDIO_CODEC_H__ */
diff --git a/include/autoboot.h b/include/autoboot.h
new file mode 100644
index 0000000..ac8157e
--- /dev/null
+++ b/include/autoboot.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Add to readline cmdline-editing by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ */
+
+#ifndef __AUTOBOOT_H
+#define __AUTOBOOT_H
+
+#ifdef CONFIG_AUTOBOOT
+/**
+ * bootdelay_process() - process the bootd delay
+ *
+ * Process the boot delay, boot limit, then get the value of either
+ * bootcmd, failbootcmd or altbootcmd depending on the current state.
+ * Return this command so it can be executed.
+ *
+ * @return command to executed
+ */
+const char *bootdelay_process(void);
+
+/**
+ * autoboot_command() - run the autoboot command
+ *
+ * If enabled, run the autoboot command returned from bootdelay_process().
+ * Also do the CONFIG_AUTOBOOT_MENUKEY processing if enabled.
+ *
+ * @cmd: Command to run
+ */
+void autoboot_command(const char *cmd);
+#else
+static inline const char *bootdelay_process(void)
+{
+	return NULL;
+}
+
+static inline void autoboot_command(const char *s)
+{
+}
+#endif
+
+#endif
diff --git a/include/avb_verify.h b/include/avb_verify.h
new file mode 100644
index 0000000..18278f8
--- /dev/null
+++ b/include/avb_verify.h
@@ -0,0 +1,101 @@
+
+/*
+ * (C) Copyright 2018, Linaro Limited
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_AVB_VERIFY_H
+#define _AVB_VERIFY_H
+
+#include <../lib/libavb/libavb.h>
+#include <mapmem.h>
+#include <mmc.h>
+
+#define AVB_MAX_ARGS			1024
+#define VERITY_TABLE_OPT_RESTART	"restart_on_corruption"
+#define VERITY_TABLE_OPT_LOGGING	"ignore_corruption"
+#define ALLOWED_BUF_ALIGN		8
+
+enum avb_boot_state {
+	AVB_GREEN,
+	AVB_YELLOW,
+	AVB_ORANGE,
+	AVB_RED,
+};
+
+struct AvbOpsData {
+	struct AvbOps ops;
+	int mmc_dev;
+	enum avb_boot_state boot_state;
+#ifdef CONFIG_OPTEE_TA_AVB
+	struct udevice *tee;
+	u32 session;
+#endif
+};
+
+struct mmc_part {
+	int dev_num;
+	struct mmc *mmc;
+	struct blk_desc *mmc_blk;
+	disk_partition_t info;
+};
+
+enum mmc_io_type {
+	IO_READ,
+	IO_WRITE
+};
+
+AvbOps *avb_ops_alloc(int boot_device);
+void avb_ops_free(AvbOps *ops);
+
+char *avb_set_state(AvbOps *ops, enum avb_boot_state boot_state);
+char *avb_set_enforce_verity(const char *cmdline);
+char *avb_set_ignore_corruption(const char *cmdline);
+
+char *append_cmd_line(char *cmdline_orig, char *cmdline_new);
+
+/**
+ * ============================================================================
+ * I/O helper inline functions
+ * ============================================================================
+ */
+static inline uint64_t calc_offset(struct mmc_part *part, int64_t offset)
+{
+	u64 part_size = part->info.size * part->info.blksz;
+
+	if (offset < 0)
+		return part_size + offset;
+
+	return offset;
+}
+
+static inline size_t get_sector_buf_size(void)
+{
+	return (size_t)CONFIG_FASTBOOT_BUF_SIZE;
+}
+
+static inline void *get_sector_buf(void)
+{
+	return map_sysmem(CONFIG_FASTBOOT_BUF_ADDR, CONFIG_FASTBOOT_BUF_SIZE);
+}
+
+static inline bool is_buf_unaligned(void *buffer)
+{
+	return (bool)((uintptr_t)buffer % ALLOWED_BUF_ALIGN);
+}
+
+static inline int get_boot_device(AvbOps *ops)
+{
+	struct AvbOpsData *data;
+
+	if (ops) {
+		data = ops->user_data;
+		if (data)
+			return data->mmc_dev;
+	}
+
+	return -1;
+}
+
+#endif /* _AVB_VERIFY_H */
diff --git a/include/axi.h b/include/axi.h
new file mode 100644
index 0000000..3e40692
--- /dev/null
+++ b/include/axi.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017, 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef _AXI_H_
+#define _AXI_H_
+
+/**
+ * enum axi_size_t - Determine size of AXI transfer
+ * @AXI_SIZE_8:  AXI sransfer is 8-bit wide
+ * @AXI_SIZE_16: AXI sransfer is 16-bit wide
+ * @AXI_SIZE_32: AXI sransfer is 32-bit wide
+ */
+enum axi_size_t {
+	AXI_SIZE_8,
+	AXI_SIZE_16,
+	AXI_SIZE_32,
+};
+
+struct axi_ops {
+	/**
+	 * read() - Read a single value from a specified address on a AXI bus
+	 * @dev:	AXI bus to read from.
+	 * @address:	The address to read from.
+	 * @data:	Pointer to a variable that takes the data value read
+	 *		from the address on the AXI bus.
+	 * @size:	The size of the data to be read.
+	 *
+	 * Return: 0 if OK, -ve on error.
+	 */
+	int (*read)(struct udevice *dev, ulong address, void *data,
+		    enum axi_size_t size);
+
+	/**
+	 * write() - Write a single value to a specified address on a AXI bus
+	 * @dev:	AXI bus to write to.
+	 * @address:	The address to write to.
+	 * @data:	Pointer to the data value to be written to the address
+	 *		on the AXI bus.
+	 * @size:	The size of the data to write.
+	 *
+	 * Return 0 if OK, -ve on error.
+	 */
+	int (*write)(struct udevice *dev, ulong address, void *data,
+		     enum axi_size_t size);
+};
+
+#define axi_get_ops(dev)	((struct axi_ops *)(dev)->driver->ops)
+
+/**
+ * axi_read() - Read a single value from a specified address on a AXI bus
+ * @dev:	AXI bus to read from.
+ * @address:	The address to read from.
+ * @data:	Pointer to a variable that takes the data value read from the
+ *              address on the AXI bus.
+ * @size:	The size of the data to write.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int axi_read(struct udevice *dev, ulong address, void *data,
+	     enum axi_size_t size);
+
+/**
+ * axi_write() - Write a single value to a specified address on a AXI bus
+ * @dev:	AXI bus to write to.
+ * @address:	The address to write to.
+ * @data:	Pointer to the data value to be written to the address on the
+ *		AXI bus.
+ * @size:	The size of the data to write.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int axi_write(struct udevice *dev, ulong address, void *data,
+	      enum axi_size_t size);
+
+struct axi_emul_ops {
+	/**
+	 * read() - Read a single value from a specified address on a AXI bus
+	 * @dev:	AXI bus to read from.
+	 * @address:	The address to read from.
+	 * @data:	Pointer to a variable that takes the data value read
+	 *		from the address on the AXI bus.
+	 * @size:	The size of the data to be read.
+	 *
+	 * Return: 0 if OK, -ve on error.
+	 */
+	int (*read)(struct udevice *dev, ulong address, void *data,
+		    enum axi_size_t size);
+
+	/**
+	 * write() - Write a single value to a specified address on a AXI bus
+	 * @dev:	AXI bus to write to.
+	 * @address:	The address to write to.
+	 * @data:	Pointer to the data value to be written to the address
+	 *		on the AXI bus.
+	 * @size:	The size of the data to write.
+	 *
+	 * Return: 0 if OK, -ve on error.
+	 */
+	int (*write)(struct udevice *dev, ulong address, void *data,
+		     enum axi_size_t size);
+
+	/**
+	 * get_store() - Get address of internal storage of a emulated AXI
+	 *		 device
+	 * @dev:	Emulated AXI device to get the pointer of the internal
+	 *		storage for.
+	 * @storep:	Pointer to the internal storage of the emulated AXI
+	 *		device.
+	 *
+	 * Return: 0 if OK, -ve on error.
+	 */
+	int (*get_store)(struct udevice *dev, u8 **storep);
+};
+
+#endif
diff --git a/include/axp152.h b/include/axp152.h
new file mode 100644
index 0000000..c81f172
--- /dev/null
+++ b/include/axp152.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ */
+
+enum axp152_reg {
+	AXP152_CHIP_VERSION = 0x3,
+	AXP152_DCDC2_VOLTAGE = 0x23,
+	AXP152_DCDC3_VOLTAGE = 0x27,
+	AXP152_DCDC4_VOLTAGE = 0x2B,
+	AXP152_LDO2_VOLTAGE = 0x2A,
+	AXP152_SHUTDOWN = 0x32,
+};
+
+#define AXP152_POWEROFF			(1 << 7)
+
+/* For axp_gpio.c */
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x91
+#define AXP_GPIO2_CTRL			0x92
+#define AXP_GPIO3_CTRL			0x93
+#define AXP_GPIO_CTRL_OUTPUT_LOW		0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH		0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT			0x02 /* Input */
+#define AXP_GPIO_STATE			0x97
+#define AXP_GPIO_STATE_OFFSET			0
diff --git a/include/axp209.h b/include/axp209.h
new file mode 100644
index 0000000..f4f1b2f
--- /dev/null
+++ b/include/axp209.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ */
+
+#include <linux/bitops.h>
+
+enum axp209_reg {
+	AXP209_POWER_STATUS = 0x00,
+	AXP209_CHIP_VERSION = 0x03,
+	AXP209_OUTPUT_CTRL = 0x12,
+	AXP209_DCDC2_VOLTAGE = 0x23,
+	AXP209_VRC_DCDC2_LDO3 = 0x25,
+	AXP209_DCDC3_VOLTAGE = 0x27,
+	AXP209_LDO24_VOLTAGE = 0x28,
+	AXP209_LDO3_VOLTAGE = 0x29,
+	AXP209_IRQ_ENABLE1 = 0x40,
+	AXP209_IRQ_ENABLE2 = 0x41,
+	AXP209_IRQ_ENABLE3 = 0x42,
+	AXP209_IRQ_ENABLE4 = 0x43,
+	AXP209_IRQ_ENABLE5 = 0x44,
+	AXP209_IRQ_STATUS5 = 0x4c,
+	AXP209_SHUTDOWN = 0x32,
+};
+
+#define AXP209_POWER_STATUS_ON_BY_DC	BIT(0)
+#define AXP209_POWER_STATUS_VBUS_USABLE	BIT(4)
+
+#define AXP209_CHIP_VERSION_MASK	0x0f
+
+#define AXP209_OUTPUT_CTRL_EXTEN	BIT(0)
+#define AXP209_OUTPUT_CTRL_DCDC3	BIT(1)
+#define AXP209_OUTPUT_CTRL_LDO2		BIT(2)
+#define AXP209_OUTPUT_CTRL_LDO4		BIT(3)
+#define AXP209_OUTPUT_CTRL_DCDC2	BIT(4)
+#define AXP209_OUTPUT_CTRL_LDO3		BIT(6)
+
+/*
+ * AXP209 datasheet contains wrong information about LDO3 VRC:
+ * - VRC is actually enabled when BIT(1) is True
+ * - VRC is actually not enabled by default (BIT(3) = 0 after reset)
+ */
+#define AXP209_VRC_LDO3_EN		BIT(3)
+#define AXP209_VRC_DCDC2_EN		BIT(2)
+#define AXP209_VRC_LDO3_800uV_uS	(BIT(1) | AXP209_VRC_LDO3_EN)
+#define AXP209_VRC_LDO3_1600uV_uS	AXP209_VRC_LDO3_EN
+#define AXP209_VRC_DCDC2_800uV_uS	(BIT(0) | AXP209_VRC_DCDC2_EN)
+#define AXP209_VRC_DCDC2_1600uV_uS	AXP209_VRC_DCDC2_EN
+#define AXP209_VRC_LDO3_MASK		0xa
+#define AXP209_VRC_DCDC2_MASK		0x5
+#define AXP209_VRC_DCDC2_SLOPE_SET(reg, cfg) \
+	(((reg) & ~AXP209_VRC_DCDC2_MASK) | \
+	((cfg) & AXP209_VRC_DCDC2_MASK))
+#define AXP209_VRC_LDO3_SLOPE_SET(reg, cfg) \
+	(((reg) & ~AXP209_VRC_LDO3_MASK) | \
+	((cfg) & AXP209_VRC_LDO3_MASK))
+
+#define AXP209_LDO24_LDO2_MASK		0xf0
+#define AXP209_LDO24_LDO4_MASK		0x0f
+#define AXP209_LDO24_LDO2_SET(reg, cfg)	\
+	(((reg) & ~AXP209_LDO24_LDO2_MASK) | \
+	(((cfg) << 4) & AXP209_LDO24_LDO2_MASK))
+#define AXP209_LDO24_LDO4_SET(reg, cfg)	\
+	(((reg) & ~AXP209_LDO24_LDO4_MASK) | \
+	(((cfg) << 0) & AXP209_LDO24_LDO4_MASK))
+
+#define AXP209_LDO3_VOLTAGE_FROM_LDO3IN	BIT(7)
+#define AXP209_LDO3_VOLTAGE_MASK	0x7f
+#define AXP209_LDO3_VOLTAGE_SET(x)	((x) & AXP209_LDO3_VOLTAGE_MASK)
+
+#define AXP209_IRQ5_PEK_UP		BIT(6)
+#define AXP209_IRQ5_PEK_DOWN		BIT(5)
+
+#define AXP209_POWEROFF			BIT(7)
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT	BIT(5)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO2_CTRL			0x93
+#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET		4
diff --git a/include/axp221.h b/include/axp221.h
new file mode 100644
index 0000000..caffb91
--- /dev/null
+++ b/include/axp221.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ *
+ * X-Powers AXP221 Power Management IC driver
+ */
+
+/* Page 0 addresses */
+#define AXP221_CHIP_ID		0x03
+#define AXP221_OUTPUT_CTRL1	0x10
+#define AXP221_OUTPUT_CTRL1_DCDC0_EN	(1 << 0)
+#define AXP221_OUTPUT_CTRL1_DCDC1_EN	(1 << 1)
+#define AXP221_OUTPUT_CTRL1_DCDC2_EN	(1 << 2)
+#define AXP221_OUTPUT_CTRL1_DCDC3_EN	(1 << 3)
+#define AXP221_OUTPUT_CTRL1_DCDC4_EN	(1 << 4)
+#define AXP221_OUTPUT_CTRL1_DCDC5_EN	(1 << 5)
+#define AXP221_OUTPUT_CTRL1_ALDO1_EN	(1 << 6)
+#define AXP221_OUTPUT_CTRL1_ALDO2_EN	(1 << 7)
+#define AXP221_OUTPUT_CTRL2	0x12
+#define AXP221_OUTPUT_CTRL2_ELDO1_EN	(1 << 0)
+#define AXP221_OUTPUT_CTRL2_ELDO2_EN	(1 << 1)
+#define AXP221_OUTPUT_CTRL2_ELDO3_EN	(1 << 2)
+#define AXP221_OUTPUT_CTRL2_DLDO1_EN	(1 << 3)
+#define AXP221_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
+#define AXP221_OUTPUT_CTRL2_DLDO3_EN	(1 << 5)
+#define AXP221_OUTPUT_CTRL2_DLDO4_EN	(1 << 6)
+#define AXP221_OUTPUT_CTRL2_DCDC1SW_EN	(1 << 7)
+#define AXP221_OUTPUT_CTRL3	0x13
+#define AXP221_OUTPUT_CTRL3_ALDO3_EN	(1 << 7)
+#define AXP221_DLDO1_CTRL	0x15
+#define AXP221_DLDO2_CTRL	0x16
+#define AXP221_DLDO3_CTRL	0x17
+#define AXP221_DLDO4_CTRL	0x18
+#define AXP221_ELDO1_CTRL	0x19
+#define AXP221_ELDO2_CTRL	0x1a
+#define AXP221_ELDO3_CTRL	0x1b
+#define AXP221_DCDC1_CTRL	0x21
+#define AXP221_DCDC2_CTRL	0x22
+#define AXP221_DCDC3_CTRL	0x23
+#define AXP221_DCDC4_CTRL	0x24
+#define AXP221_DCDC5_CTRL	0x25
+#define AXP221_ALDO1_CTRL	0x28
+#define AXP221_ALDO2_CTRL	0x29
+#define AXP221_ALDO3_CTRL	0x2a
+#define AXP221_SHUTDOWN		0x32
+#define AXP221_SHUTDOWN_POWEROFF	(1 << 7)
+#define AXP221_PAGE		0xff
+
+/* Page 1 addresses */
+#define AXP221_SID		0x20
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
+#define AXP_VBUS_IPSOUT			0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+#define AXP_MISC_CTRL			0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW		0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH		0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT			0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET			0
diff --git a/include/axp809.h b/include/axp809.h
new file mode 100644
index 0000000..86b2925
--- /dev/null
+++ b/include/axp809.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * X-Powers AXP809 Power Management IC driver
+ */
+
+#define AXP809_CHIP_ID		0x03
+
+#define AXP809_OUTPUT_CTRL1	0x10
+#define AXP809_OUTPUT_CTRL1_DC5LDO_EN	(1 << 0)
+#define AXP809_OUTPUT_CTRL1_DCDC1_EN	(1 << 1)
+#define AXP809_OUTPUT_CTRL1_DCDC2_EN	(1 << 2)
+#define AXP809_OUTPUT_CTRL1_DCDC3_EN	(1 << 3)
+#define AXP809_OUTPUT_CTRL1_DCDC4_EN	(1 << 4)
+#define AXP809_OUTPUT_CTRL1_DCDC5_EN	(1 << 5)
+#define AXP809_OUTPUT_CTRL1_ALDO1_EN	(1 << 6)
+#define AXP809_OUTPUT_CTRL1_ALDO2_EN	(1 << 7)
+#define AXP809_OUTPUT_CTRL2	0x12
+#define AXP809_OUTPUT_CTRL2_ELDO1_EN	(1 << 0)
+#define AXP809_OUTPUT_CTRL2_ELDO2_EN	(1 << 1)
+#define AXP809_OUTPUT_CTRL2_ELDO3_EN	(1 << 2)
+#define AXP809_OUTPUT_CTRL2_DLDO1_EN	(1 << 3)
+#define AXP809_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
+#define AXP809_OUTPUT_CTRL2_ALDO3_EN	(1 << 5)
+#define AXP809_OUTPUT_CTRL2_SWOUT_EN	(1 << 6)
+#define AXP809_OUTPUT_CTRL2_DC1SW_EN	(1 << 7)
+
+#define AXP809_DLDO1_CTRL	0x15
+#define AXP809_DLDO2_CTRL	0x16
+#define AXP809_ELDO1_CTRL	0x19
+#define AXP809_ELDO2_CTRL	0x1a
+#define AXP809_ELDO3_CTRL	0x1b
+#define AXP809_DC5LDO_CTRL	0x1c
+#define AXP809_DCDC1_CTRL	0x21
+#define AXP809_DCDC2_CTRL	0x22
+#define AXP809_DCDC3_CTRL	0x23
+#define AXP809_DCDC4_CTRL	0x24
+#define AXP809_DCDC5_CTRL	0x25
+#define AXP809_ALDO1_CTRL	0x28
+#define AXP809_ALDO2_CTRL	0x29
+#define AXP809_ALDO3_CTRL	0x2a
+#define AXP809_SHUTDOWN		0x32
+#define AXP809_SHUTDOWN_POWEROFF	(1 << 7)
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
+#define AXP_VBUS_IPSOUT			0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+#define AXP_MISC_CTRL			0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET		0
diff --git a/include/axp818.h b/include/axp818.h
new file mode 100644
index 0000000..b16fe0b
--- /dev/null
+++ b/include/axp818.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * X-Powers AXP818 Power Management IC driver
+ */
+
+#define AXP818_CHIP_ID		0x03
+
+#define AXP818_OUTPUT_CTRL1	0x10
+#define AXP818_OUTPUT_CTRL1_DCDC1_EN	(1 << 0)
+#define AXP818_OUTPUT_CTRL1_DCDC2_EN	(1 << 1)
+#define AXP818_OUTPUT_CTRL1_DCDC3_EN	(1 << 2)
+#define AXP818_OUTPUT_CTRL1_DCDC4_EN	(1 << 3)
+#define AXP818_OUTPUT_CTRL1_DCDC5_EN	(1 << 4)
+#define AXP818_OUTPUT_CTRL1_DCDC6_EN	(1 << 5)
+#define AXP818_OUTPUT_CTRL1_DCDC7_EN	(1 << 6)
+#define AXP818_OUTPUT_CTRL2	0x12
+#define AXP818_OUTPUT_CTRL2_ELDO1_EN	(1 << 0)
+#define AXP818_OUTPUT_CTRL2_ELDO2_EN	(1 << 1)
+#define AXP818_OUTPUT_CTRL2_ELDO3_EN	(1 << 2)
+#define AXP818_OUTPUT_CTRL2_DLDO1_EN	(1 << 3)
+#define AXP818_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
+#define AXP818_OUTPUT_CTRL2_DLDO3_EN	(1 << 5)
+#define AXP818_OUTPUT_CTRL2_DLDO4_EN	(1 << 6)
+#define AXP818_OUTPUT_CTRL2_SW_EN	(1 << 7)
+#define AXP818_OUTPUT_CTRL3	0x13
+#define AXP818_OUTPUT_CTRL3_FLDO1_EN	(1 << 2)
+#define AXP818_OUTPUT_CTRL3_FLDO2_EN	(1 << 3)
+#define AXP818_OUTPUT_CTRL3_FLDO3_EN	(1 << 4)
+#define AXP818_OUTPUT_CTRL3_ALDO1_EN	(1 << 5)
+#define AXP818_OUTPUT_CTRL3_ALDO2_EN	(1 << 6)
+#define AXP818_OUTPUT_CTRL3_ALDO3_EN	(1 << 7)
+
+#define AXP818_DLDO1_CTRL	0x15
+#define AXP818_DLDO2_CTRL	0x16
+#define AXP818_DLDO3_CTRL	0x17
+#define AXP818_DLDO4_CTRL	0x18
+#define AXP818_ELDO1_CTRL	0x19
+#define AXP818_ELDO2_CTRL	0x1a
+#define AXP818_ELDO3_CTRL	0x1b
+#define AXP818_FLDO1_CTRL	0x1c
+#define AXP818_FLDO2_3_CTRL	0x1d
+#define AXP818_FLDO2_3_CTRL_FLDO3_VOL	(1 << 4)
+#define AXP818_DCDC1_CTRL	0x20
+#define AXP818_DCDC2_CTRL	0x21
+#define AXP818_DCDC3_CTRL	0x22
+#define AXP818_DCDC4_CTRL	0x23
+#define AXP818_DCDC5_CTRL	0x24
+#define AXP818_DCDC6_CTRL	0x25
+#define AXP818_DCDC7_CTRL	0x26
+
+#define AXP818_ALDO1_CTRL	0x28
+#define AXP818_ALDO2_CTRL	0x29
+#define AXP818_ALDO3_CTRL	0x2a
+
+#define AXP818_SHUTDOWN		0x32
+#define AXP818_SHUTDOWN_POWEROFF	(1 << 7)
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
+#define AXP_VBUS_IPSOUT			0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+#define AXP_MISC_CTRL			0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET		0
diff --git a/include/axp_pmic.h b/include/axp_pmic.h
new file mode 100644
index 0000000..10091d0
--- /dev/null
+++ b/include/axp_pmic.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * X-Powers AX Power Management IC support header
+ */
+#ifndef _AXP_PMIC_H_
+
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#endif
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
+#ifdef CONFIG_AXP221_POWER
+#include <axp221.h>
+#endif
+#ifdef CONFIG_AXP809_POWER
+#include <axp809.h>
+#endif
+#ifdef CONFIG_AXP818_POWER
+#include <axp818.h>
+#endif
+
+int axp_set_dcdc1(unsigned int mvolt);
+int axp_set_dcdc2(unsigned int mvolt);
+int axp_set_dcdc3(unsigned int mvolt);
+int axp_set_dcdc4(unsigned int mvolt);
+int axp_set_dcdc5(unsigned int mvolt);
+int axp_set_aldo1(unsigned int mvolt);
+int axp_set_aldo2(unsigned int mvolt);
+int axp_set_aldo3(unsigned int mvolt);
+int axp_set_aldo4(unsigned int mvolt);
+int axp_set_dldo(int dldo_num, unsigned int mvolt);
+int axp_set_eldo(int eldo_num, unsigned int mvolt);
+int axp_set_fldo(int fldo_num, unsigned int mvolt);
+int axp_set_sw(bool on);
+int axp_init(void);
+int axp_get_sid(unsigned int *sid);
+
+#endif
diff --git a/include/backlight.h b/include/backlight.h
new file mode 100644
index 0000000..ac59eb2
--- /dev/null
+++ b/include/backlight.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _BACKLIGHT_H
+#define _BACKLIGHT_H
+
+enum {
+	BACKLIGHT_MAX		= 100,
+	BACKLIGHT_MIN		= 0,
+	BACKLIGHT_OFF		= -1,
+	BACKLIGHT_DEFAULT	= -2,
+};
+
+struct backlight_ops {
+	/**
+	 * enable() - Enable a backlight
+	 *
+	 * @dev:	Backlight device to enable
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*enable)(struct udevice *dev);
+
+	/**
+	 * set_brightness - Set brightness
+	 *
+	 * @dev:	Backlight device to update
+	 * @percent:	Brightness value (0 to 100, or BACKLIGHT_... value)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_brightness)(struct udevice *dev, int percent);
+};
+
+#define backlight_get_ops(dev)	((struct backlight_ops *)(dev)->driver->ops)
+
+/**
+ * backlight_enable() - Enable a backlight
+ *
+ * @dev:	Backlight device to enable
+ * @return 0 if OK, -ve on error
+ */
+int backlight_enable(struct udevice *dev);
+
+/**
+ * backlight_set_brightness - Set brightness
+ *
+ * @dev:	Backlight device to update
+ * @percent:	Brightness value (0 to 100, or BACKLIGHT_... value)
+ * @return 0 if OK, -ve on error
+ */
+int backlight_set_brightness(struct udevice *dev, int percent);
+
+#endif
diff --git a/include/bcd.h b/include/bcd.h
new file mode 100644
index 0000000..9ecd328
--- /dev/null
+++ b/include/bcd.h
@@ -0,0 +1,23 @@
+/* Permission is hereby granted to copy, modify and redistribute this code
+ * in terms of the GNU Library General Public License, Version 2 or later,
+ * at your option.
+ */
+
+/* inline functions to translate to/from binary and binary-coded decimal
+ * (frequently found in RTC chips).
+ */
+
+#ifndef _BCD_H
+#define _BCD_H
+
+static inline unsigned int bcd2bin(unsigned int val)
+{
+	return ((val) & 0x0f) + ((val & 0xff) >> 4) * 10;
+}
+
+static inline unsigned int bin2bcd(unsigned int val)
+{
+	return (((val / 10) << 4) | (val % 10));
+}
+
+#endif /* _BCD_H */
diff --git a/include/bedbug/bedbug.h b/include/bedbug/bedbug.h
new file mode 100644
index 0000000..0c5d687
--- /dev/null
+++ b/include/bedbug/bedbug.h
@@ -0,0 +1,40 @@
+/* $Id$ */
+
+#ifndef _BEDBUG_H
+#define _BEDBUG_H
+
+#ifndef NULL
+#define NULL	0
+#endif
+
+#define _USE_PROTOTYPES
+
+#ifndef isblank
+#define isblank(c) isspace((int)(c))
+#endif
+
+#ifndef __P
+#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus))
+#define __P(protos)	protos		/* full-blown ANSI C */
+#else
+#define __P(protos)	()		/* traditional C preprocessor */
+#endif
+#endif
+
+#endif /* _BEDBUG_H */
+
+
+/*
+ * Copyright (c) 2001 William L. Pitts
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h
new file mode 100644
index 0000000..76d86fd
--- /dev/null
+++ b/include/bedbug/ppc.h
@@ -0,0 +1,408 @@
+/* $Id$ */
+
+#ifndef _PPC_H
+#define _PPC_H
+
+/*======================================================================
+ *
+ *  OPERANDS
+ *
+ *======================================================================*/
+
+enum OP_FIELD {
+  O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD,
+  O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD,
+  O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr,
+  O_cr2 };
+
+struct operand {
+  enum OP_FIELD	field;		/* The operand identifier from the
+				   enum above */
+
+  char *	name;		/* Symbolic name of this operand */
+
+  unsigned int	bits;		/* The number of bits used by this
+				   operand */
+
+  unsigned int	shift;		/* How far to the right the operand
+				   should be shifted so that it is
+				   aligned at the beginning of the
+				   word */
+
+  unsigned int	hint;		/* A bitwise-inclusive-OR of the
+				   values shown below.  These are used
+				   tell the disassembler how to print
+				   this operand */
+};
+
+/* Values for operand hint */
+#define OH_SILENT	0x01	/* dont print this operand */
+#define OH_ADDR		0x02	/* this operand is an address */
+#define OH_REG		0x04	/* this operand is a register */
+#define OH_SPR		0x08	/* this operand is an SPR */
+#define OH_TBR		0x10	/* this operand is a TBR */
+#define OH_OFFSET	0x20	/* this operand is an offset */
+#define OH_LITERAL      0x40    /* a literal string */
+
+
+/*======================================================================
+ *
+ *  OPCODES
+ *
+ *======================================================================*/
+
+/* From the MPCxxx instruction set documentation, all instructions are
+ * 32 bits long and word aligned.  Bits 0-5 always specify the primary
+ * opcode.  Many instructions also have an extended opcode.
+ */
+
+#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f)
+#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26)
+
+/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the
+ * instruction forms
+ */
+
+
+/*-------------------------------------------------
+ *              I-Form Instructions:
+ * bX
+ *-------------------------------------------------
+ * OPCD |           LI                       |AA|LK
+ *-------------------------------------------------*/
+
+#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
+#define I_MASK I_OPCODE(0x3f,0x1,0x1)
+
+
+/*-------------------------------------------------
+ *              B-Form Instructions:
+ * bcX
+ *-------------------------------------------------
+ * OPCD |    BO   |  BI  |   BD              |AA|LK
+ *-------------------------------------------------*/
+
+#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
+#define B_MASK B_OPCODE(0x3f,0x1,0x1)
+
+
+/*-------------------------------------------------
+ *             SC-Form Instructions:
+ * sc
+ *-------------------------------------------------
+ * OPCD | 00000 | 00000 | 00000000000000       |1|0
+ *-------------------------------------------------*/
+
+#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2)
+#define SC_MASK SC_OPCODE(0x3f)
+
+
+/*-------------------------------------------------
+ *             D-Form Instructions:
+ * addi addic addic. addis andi. andis. cmpi cmpli
+ * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli
+ * ori oris stb stbu sth sthu stmw stw stwu subfic
+ * twi xori xoris
+ *-------------------------------------------------
+ * OPCD |   D    |   A   |            d
+ * OPCD |   D    |   A   |           SIMM
+ * OPCD |   S    |   A   |            d
+ * OPCD |   S    |   A   |           UIMM
+ * OPCD |crfD|0|L|   A   |           SIMM
+ * OPCD |crfD|0|L|   A   |           UIMM
+ * OPCD |   TO   |   A   |           SIMM
+ *-------------------------------------------------*/
+
+#define D_OPCODE(i) MAKE_OPCODE(i)
+#define D_MASK MAKE_OPCODE(0x3f)
+
+
+/*-------------------------------------------------
+ *            DS-Form Instructions:
+ * (none supported by MPC860)
+ *-------------------------------------------------
+ * OPCD |   D    |   A   |          ds          |XO
+ * OPCD |   S    |   A   |          ds          |XO
+ *-------------------------------------------------*/
+
+#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3))
+#define DS_MASK DS_OPCODE(0x3f,0x1)
+
+
+/*---------------------------------------------------
+ *            X-Form Instructions:
+ * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt
+ * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX
+ * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi
+ * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr
+ * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX
+ * orX orcX slwX srawX srawiX srwX stbux stbx
+ * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux
+ * stwx sync tlbie tlbld tlbli tlbsync tw xorX
+ *---------------------------------------------------
+ * OPCD |   D    |    A   |    B   |      XO      |0
+ * OPCD |   D    |    A   |   NB   |      XO      |0
+ * OPCD |   D    |  00000 |    B   |      XO      |0
+ * OPCD |   D    |  00000 |  00000 |      XO      |0
+ * OPCD |   D    |0|  SR  |  00000 |      XO      |0
+ * OPCD |   S    |    A   |    B   |      XO      |Rc
+ * OPCD |   S    |    A   |    B   |      XO      |1
+ * OPCD |   S    |    A   |    B   |      XO      |0
+ * OPCD |   S    |    A   |   NB   |      XO      |0
+ * OPCD |   S    |    A   |  00000 |      XO      |Rc
+ * OPCD |   S    |  00000 |    B   |      XO      |0
+ * OPCD |   S    |  00000 |  00000 |      XO      |0
+ * OPCD |   S    |0|  SR  |  00000 |      XO      |0
+ * OPCD |   S    |    A   |   SH   |      XO      |Rc
+ * OPCD |crfD|0|L|    A   |   SH   |      XO      |0
+ * OPCD |crfD |00|    A   |    B   |      XO      |0
+ * OPCD |crfD |00|crfS |00|  00000 |      XO      |0
+ * OPCD |crfD |00|  00000 |  00000 |      XO      |0
+ * OPCD |crfD |00|  00000 | IMM  |0|      XO      |Rc
+ * OPCD |   TO   |    A   |    B   |      XO      |0
+ * OPCD |   D    |  00000 |    B   |      XO      |Rc
+ * OPCD |   D    |  00000 |  00000 |      XO      |Rc
+ * OPCD |  crbD  |  00000 |  00000 |      XO      |Rc
+ * OPCD |  00000 |    A   |    B   |      XO      |0
+ * OPCD |  00000 |  00000 |    B   |      XO      |0
+ * OPCD |  00000 |  00000 |  00000 |      XO      |0
+ *---------------------------------------------------*/
+
+#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			   ((rc) & 0x1))
+#define X_MASK X_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XL-Form Instructions:
+ * bcctrX bclrX crand crandc creqv crnand crnor cror
+ * croc crxorisync mcrf rfi
+ *---------------------------------------------------
+ * OPCD |   BO   |  BI    |  00000 |      XO      |LK
+ * OPCD |  crbD  | crbA   |  crbB  |      XO      |0
+ * OPCD |crfD |00|crfS |00|  00000 |      XO      |0
+ * OPCD |  00000 |  00000 |  00000 |      XO      |0
+ *---------------------------------------------------*/
+
+#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			    ((lk) & 0x1))
+#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XFX-Form Instructions:
+ * mfspr mftb mtcrf mtspr
+ *---------------------------------------------------
+ * OPCD |   D    |      spr        |      XO       |0
+ * OPCD |   D    |0|    CRM      |0|      XO       |0
+ * OPCD |   S    |      spr        |      XO       |0
+ * OPCD |   D    |      tbr        |      XO       |0
+ *---------------------------------------------------*/
+
+#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			     ((rc) & 0x1))
+#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XFL-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |0|      FM     |0|   B    |      XO       |0
+ *---------------------------------------------------*/
+
+#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			     ((rc) & 0x1))
+#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XS-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |   sh   |      XO   |sh|LK
+ *---------------------------------------------------*/
+
+#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \
+			     ((rc) & 0x1))
+#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XO-Form Instructions:
+ * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX
+ * mulhwuX mullwX negX subfX subfcX subfeX subfmeX
+ * subfzeX
+ *---------------------------------------------------
+ * OPCD |    D   |   A    |    B   |OE|     XO    |Rc
+ * OPCD |    D   |   A    |    B   |0 |     XO    |Rc
+ * OPCD |    D   |   A    |  00000 |OE|     XO    |Rc
+ *---------------------------------------------------*/
+
+#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \
+			       (((xo) & 0x1ff) << 1) | ((rc) & 0x1))
+#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1)
+
+
+/*---------------------------------------------------
+ *            A-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    D   |   A    |    B   |00000|  XO    |Rc
+ * OPCD |    D   |   A    |    B   |  C  |  XO    |Rc
+ * OPCD |    D   |   A    |  00000 |  C  |  XO    |Rc
+ * OPCD |    D   |  00000 |    B   |00000|  XO    |Rc
+ *---------------------------------------------------*/
+
+#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \
+			   ((rc) & 0x1))
+#define A_MASK A_OPCODE(0x3f,0x1f,0x1)
+
+
+/*---------------------------------------------------
+ *            M-Form Instructions:
+ * rlwimiX rlwinmX rlwnmX
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    SH   |  MB |  ME   |Rc
+ * OPCD |    S   |   A    |     B   |  MB |  ME   |Rc
+ *---------------------------------------------------*/
+
+#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1))
+#define M_MASK M_OPCODE(0x3f,0x1)
+
+
+/*---------------------------------------------------
+ *            MD-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    sh   |  mb | XO |sh|Rc
+ * OPCD |    S   |   A    |    sh   |  me | XO |sh|Rc
+ *---------------------------------------------------*/
+
+#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \
+			   ((rc) & 0x1))
+#define MD_MASK MD_OPCODE(0x3f,0x7,0x1)
+
+
+/*---------------------------------------------------
+ *            MDS-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    B    |  mb | XO    |Rc
+ * OPCD |    S   |   A    |    B    |  me | XO    |Rc
+ *---------------------------------------------------*/
+
+#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \
+			   ((rc) & 0x1))
+#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1)
+
+#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr))
+
+#define MAX_OPERANDS  8
+
+struct ppc_ctx;
+
+struct opcode {
+  unsigned long	opcode;		/* The complete opcode as produced by
+				   one of the XXX_OPCODE macros above */
+
+  unsigned long	mask;		/* The mask to use on an instruction
+				   before comparing with the opcode
+				   field to see if it matches */
+
+  enum OP_FIELD	fields[MAX_OPERANDS];
+				/* An array defining the operands for
+				   this opcode.  The values of the
+				   array are the operand identifiers */
+
+  int (*hfunc)(struct ppc_ctx *);
+				/* Address of a function to handle the given
+				   mnemonic */
+
+  char *	name;		/* The symbolic name of this opcode */
+
+  unsigned int	hint;		/* A bitwise-inclusive-OR of the
+				   values shown below.  These are used
+				   tell the disassembler how to print
+				   some operands for this opcode */
+};
+
+/* values for opcode hints */
+#define H_RELATIVE	0x1	/* The address operand is relative */
+#define H_IMM_HIGH	0x2	/* [U|S]IMM field shifted high */
+#define H_RA0_IS_0	0x4	/* If rA = 0 then treat as literal 0 */
+
+struct ppc_ctx {
+  struct opcode *	op;
+  unsigned long		instr;
+  unsigned int		flags;
+  int			datalen;
+  char			data[ 256 ];
+  char			radix_fmt[ 8 ];
+  unsigned char *	virtual;
+};
+
+
+/*======================================================================
+ *
+ *  FUNCTIONS
+ *
+ *======================================================================*/
+
+/* Values for flags as passed to various ppc routines */
+#define F_RADOCTAL	0x1	/* output radix = unsigned octal */
+#define F_RADUDECIMAL	0x2	/* output radix = unsigned decimal */
+#define F_RADSDECIMAL	0x4	/* output radix = signed decimal */
+#define F_RADHEX	0x8	/* output radix = unsigned hex */
+#define F_SIMPLE	0x10	/* use simplified mnemonics */
+#define F_SYMBOL	0x20	/* use symbol lookups for addresses */
+#define F_INSTR		0x40	/* output the raw instruction */
+#define F_LOCALMEM	0x80	/* retrieve opcodes from local memory
+				   rather than from the HMI */
+#define F_LINENO	0x100	/* show line number info if available */
+#define F_VALIDONLY	0x200	/* cache: valid entries only */
+
+/* Values for assembler error codes */
+#define E_ASM_BAD_OPCODE	1
+#define E_ASM_NUM_OPERANDS	2
+#define E_ASM_BAD_REGISTER	3
+#define E_ASM_BAD_SPR		4
+#define E_ASM_BAD_TBR		5
+
+extern int disppc __P((unsigned char *,unsigned char *,int,
+		       int (*)(const char *), unsigned long));
+extern int print_source_line __P((char *,char *,int,
+				  int (*pfunc)(const char *)));
+extern int find_next_address __P((unsigned char *,int,struct pt_regs *));
+extern int handle_bc __P((struct ppc_ctx *));
+extern unsigned long asmppc __P((unsigned long,char*,int*));
+extern char *asm_error_str __P((int));
+
+/*======================================================================
+ *
+ *  GLOBAL VARIABLES
+ *
+ *======================================================================*/
+
+extern struct operand operands[];
+extern const unsigned int n_operands;
+extern struct opcode opcodes[];
+extern const unsigned int n_opcodes;
+
+#endif /* _PPC_H */
+
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/include/bedbug/regs.h b/include/bedbug/regs.h
new file mode 100644
index 0000000..304a336
--- /dev/null
+++ b/include/bedbug/regs.h
@@ -0,0 +1,400 @@
+/* $Id$ */
+
+#ifndef _REGS_H
+#define _REGS_H
+
+/* Special Purpose Registers */
+
+#define SPR_CR		-1
+#define SPR_MSR		-2
+
+#define SPR_XER		1
+#define SPR_LR		8
+#define SPR_CTR		9
+#define SPR_DSISR	18
+#define SPR_DAR		19
+#define SPR_DEC		22
+#define SPR_SRR0	26
+#define SPR_SRR1	27
+#define SPR_EIE		80
+#define SPR_EID		81
+#define SPR_CMPA	144
+#define SPR_CMPB	145
+#define SPR_CMPC	146
+#define SPR_CMPD	147
+#define SPR_ICR		148
+#define SPR_DER		149
+#define SPR_COUNTA	150
+#define SPR_COUNTB	151
+#define SPR_CMPE	152
+#define SPR_CMPF	153
+#define SPR_CMPG	154
+#define SPR_CMPH	155
+#define SPR_LCTRL1	156
+#define SPR_LCTRL2	157
+#define SPR_ICTRL	158
+#define SPR_BAR		159
+#define SPR_USPRG0      256
+#define SPR_SPRG4_RO    260
+#define SPR_SPRG5_RO    261
+#define SPR_SPRG6_RO    262
+#define SPR_SPRG7_RO    263
+#define SPR_SPRG0	272
+#define SPR_SPRG1	273
+#define SPR_SPRG2	274
+#define SPR_SPRG3	275
+#define SPR_SPRG4       276
+#define SPR_SPRG5       277
+#define SPR_SPRG6       278
+#define SPR_SPRG7       279
+#define SPR_EAR         282	/* MPC603e core */
+#define SPR_TBL         284
+#define SPR_TBU         285
+#define SPR_PVR		287
+#define SPR_IC_CST	560
+#define SPR_IC_ADR	561
+#define SPR_IC_DAT	562
+#define SPR_DC_CST	568
+#define SPR_DC_ADR	569
+#define SPR_DC_DAT	570
+#define SPR_DPDR	630
+#define SPR_IMMR	638
+#define SPR_MI_CTR	784
+#define SPR_MI_AP	786
+#define SPR_MI_EPN	787
+#define SPR_MI_TWC	789
+#define SPR_MI_RPN	790
+#define SPR_MD_CTR	792
+#define SPR_M_CASID	793
+#define SPR_MD_AP	794
+#define SPR_MD_EPN	795
+#define SPR_M_TWB	796
+#define SPR_MD_TWC	797
+#define SPR_MD_RPN	798
+#define SPR_M_TW	799
+#define SPR_MI_DBCAM	816
+#define SPR_MI_DBRAM0	817
+#define SPR_MI_DBRAM1	818
+#define SPR_MD_DBCAM	824
+#define SPR_MD_DBRAM0	825
+#define SPR_MD_DBRAM1	826
+#define SPR_ZPR         944
+#define SPR_PID         945
+#define SPR_CCR0        947
+#define SPR_IAC3        948
+#define SPR_IAC4        949
+#define SPR_DVC1        950
+#define SPR_DVC2        951
+#define SPR_SGR         953
+#define SPR_DCWR        954
+#define SPR_SLER        955
+#define SPR_SU0R        956
+#define SPR_DBCR1       957
+#define SPR_ICDBDR      979
+#define SPR_ESR         980
+#define SPR_DEAR        981
+#define SPR_EVPR        982
+#define SPR_TSR         984
+#define SPR_TCR         986
+#define SPR_PIT         987
+#define SPR_SRR2        990
+#define SPR_SRR3        991
+#define SPR_DBSR        1008
+#define SPR_DBCR0       1010
+#define SPR_IABR        1010	/* MPC603e core */
+#define SPR_IAC1        1012
+#define SPR_IAC2        1013
+#define SPR_DAC1        1014
+#define SPR_DAC2        1015
+#define SPR_DCCR        1018
+#define SPR_ICCR        1019
+
+/* Bits for the DBCR0 register */
+#define DBCR0_EDM	0x80000000
+#define DBCR0_IDM	0x40000000
+#define DBCR0_RST	0x30000000
+#define DBCR0_IC	0x08000000
+#define DBCR0_BT	0x04000000
+#define DBCR0_EDE	0x02000000
+#define DBCR0_TDE	0x01000000
+#define DBCR0_IA1	0x00800000
+#define DBCR0_IA2	0x00400000
+#define DBCR0_IA12	0x00200000
+#define DBCR0_IA12X	0x00100000
+#define DBCR0_IA3	0x00080000
+#define DBCR0_IA4	0x00040000
+#define DBCR0_IA34	0x00020000
+#define DBCR0_IA34X	0x00010000
+#define DBCR0_IA12T	0x00008000
+#define DBCR0_IA34T	0x00004000
+#define DBCR0_FT	0x00000001
+
+/* Bits for the DBCR1 register */
+#define DBCR1_D1R	0x80000000
+#define DBCR1_D2R	0x40000000
+#define DBCR1_D1W	0x20000000
+#define DBCR1_D2W	0x10000000
+#define DBCR1_D1S	0x0C000000
+#define DBCR1_D2S	0x03000000
+#define DBCR1_DA12	0x00800000
+#define DBCR1_DA12X	0x00400000
+#define DBCR1_DV1M	0x000C0000
+#define DBCR1_DV2M	0x00030000
+#define DBCR1_DV1BE	0x0000F000
+#define DBCR1_DV2BE	0x00000F00
+
+/*
+ * DBSR bits which have conflicting definitions on true Book E versus PPC40x
+ */
+#ifdef CONFIG_BOOKE
+#define DBSR_IA1	0x00800000	/* Instr Address Compare 1 Event */
+#define DBSR_IA2	0x00400000	/* Instr Address Compare 2 Event */
+#define DBSR_IA3	0x00200000	/* Instr Address Compare 3 Event */
+#define DBSR_IA4	0x00100000	/* Instr Address Compare 4 Event */
+#endif
+#define DBSR_IA1	0x04000000	/* Instr Address Compare 1 Event */
+#define DBSR_IA2	0x02000000	/* Instr Address Compare 2 Event */
+#define DBSR_IA3	0x00080000	/* Instr Address Compare 3 Event */
+#define DBSR_IA4	0x00040000	/* Instr Address Compare 4 Event */
+
+struct spr_info {
+  int  spr_val;
+  char spr_name[ 10 ];
+};
+
+extern struct spr_info spr_map[];
+extern const unsigned int n_sprs;
+
+
+#define SET_REGISTER( str, val ) \
+({ unsigned long __value = (val); \
+  asm volatile( str : : "r" (__value)); \
+  __value; })
+
+#define	GET_REGISTER( str ) \
+({ unsigned long __value; \
+  asm volatile( str : "=r" (__value) : ); \
+  __value; })
+
+#define	 GET_CR()	     GET_REGISTER( "mfcr %0" )
+#define	 SET_CR(val)	     SET_REGISTER( "mtcr %0", val )
+#define	 GET_MSR()	     GET_REGISTER( "mfmsr %0" )
+#define	 SET_MSR(val)	     SET_REGISTER( "mtmsr %0", val )
+#define	 GET_XER()	     GET_REGISTER( "mfspr %0,1" )
+#define	 SET_XER(val)	     SET_REGISTER( "mtspr 1,%0", val )
+#define	 GET_LR()	     GET_REGISTER( "mfspr %0,8" )
+#define	 SET_LR(val)	     SET_REGISTER( "mtspr 8,%0", val )
+#define	 GET_CTR()	     GET_REGISTER( "mfspr %0,9" )
+#define	 SET_CTR(val)	     SET_REGISTER( "mtspr 9,%0", val )
+#define	 GET_DSISR()	     GET_REGISTER( "mfspr %0,18" )
+#define	 SET_DSISR(val)	     SET_REGISTER( "mtspr 18,%0", val )
+#define	 GET_DAR()	     GET_REGISTER( "mfspr %0,19" )
+#define	 SET_DAR(val)	     SET_REGISTER( "mtspr 19,%0", val )
+#define	 GET_DEC()	     GET_REGISTER( "mfspr %0,22" )
+#define	 SET_DEC(val)	     SET_REGISTER( "mtspr 22,%0", val )
+#define	 GET_SRR0()	     GET_REGISTER( "mfspr %0,26" )
+#define	 SET_SRR0(val)       SET_REGISTER( "mtspr 26,%0", val )
+#define	 GET_SRR1()	     GET_REGISTER( "mfspr %0,27" )
+#define	 SET_SRR1(val)	     SET_REGISTER( "mtspr 27,%0", val )
+#define	 GET_EIE()	     GET_REGISTER( "mfspr %0,80" )
+#define	 SET_EIE(val)	     SET_REGISTER( "mtspr 80,%0", val )
+#define	 GET_EID()	     GET_REGISTER( "mfspr %0,81" )
+#define	 SET_EID(val)	     SET_REGISTER( "mtspr 81,%0", val )
+#define	 GET_CMPA()	     GET_REGISTER( "mfspr %0,144" )
+#define	 SET_CMPA(val)	     SET_REGISTER( "mtspr 144,%0", val )
+#define	 GET_CMPB()	     GET_REGISTER( "mfspr %0,145" )
+#define	 SET_CMPB(val)	     SET_REGISTER( "mtspr 145,%0", val )
+#define	 GET_CMPC()	     GET_REGISTER( "mfspr %0,146" )
+#define	 SET_CMPC(val)	     SET_REGISTER( "mtspr 146,%0", val )
+#define	 GET_CMPD()	     GET_REGISTER( "mfspr %0,147" )
+#define	 SET_CMPD(val)	     SET_REGISTER( "mtspr 147,%0", val )
+#define	 GET_ICR()	     GET_REGISTER( "mfspr %0,148" )
+#define	 SET_ICR(val)	     SET_REGISTER( "mtspr 148,%0", val )
+#define	 GET_DER()	     GET_REGISTER( "mfspr %0,149" )
+#define	 SET_DER(val)	     SET_REGISTER( "mtspr 149,%0", val )
+#define	 GET_COUNTA()	     GET_REGISTER( "mfspr %0,150" )
+#define	 SET_COUNTA(val)     SET_REGISTER( "mtspr 150,%0", val )
+#define	 GET_COUNTB()	     GET_REGISTER( "mfspr %0,151" )
+#define	 SET_COUNTB(val)     SET_REGISTER( "mtspr 151,%0", val )
+#define	 GET_CMPE()	     GET_REGISTER( "mfspr %0,152" )
+#define	 SET_CMPE(val)	     SET_REGISTER( "mtspr 152,%0", val )
+#define	 GET_CMPF()	     GET_REGISTER( "mfspr %0,153" )
+#define	 SET_CMPF(val)	     SET_REGISTER( "mtspr 153,%0", val )
+#define	 GET_CMPG()	     GET_REGISTER( "mfspr %0,154" )
+#define	 SET_CMPG(val)	     SET_REGISTER( "mtspr 154,%0", val )
+#define	 GET_CMPH()	     GET_REGISTER( "mfspr %0,155" )
+#define	 SET_CMPH(val)	     SET_REGISTER( "mtspr 155,%0", val )
+#define  GET_LCTRL1()	     GET_REGISTER( "mfspr %0,156" )
+#define	 SET_LCTRL1(val)     SET_REGISTER( "mtspr 156,%0", val )
+#define  GET_LCTRL2()	     GET_REGISTER( "mfspr %0,157" )
+#define	 SET_LCTRL2(val)     SET_REGISTER( "mtspr 157,%0", val )
+#define  GET_ICTRL()	     GET_REGISTER( "mfspr %0,158" )
+#define	 SET_ICTRL(val)	     SET_REGISTER( "mtspr 158,%0", val )
+#define  GET_BAR()	     GET_REGISTER( "mfspr %0,159" )
+#define	 SET_BAR(val)	     SET_REGISTER( "mtspr 159,%0", val )
+#define  GET_USPRG0()	     GET_REGISTER( "mfspr %0,256" )
+#define	 SET_USPRG0(val)     SET_REGISTER( "mtspr 256,%0", val )
+#define  GET_SPRG4_RO()	     GET_REGISTER( "mfspr %0,260" )
+#define	 SET_SPRG4_RO(val)   SET_REGISTER( "mtspr 260,%0", val )
+#define  GET_SPRG5_RO()	     GET_REGISTER( "mfspr %0,261" )
+#define	 SET_SPRG5_RO(val)   SET_REGISTER( "mtspr 261,%0", val )
+#define  GET_SPRG6_RO()	     GET_REGISTER( "mfspr %0,262" )
+#define	 SET_SPRG6_RO(val)   SET_REGISTER( "mtspr 262,%0", val )
+#define  GET_SPRG7_RO()	     GET_REGISTER( "mfspr %0,263" )
+#define	 SET_SPRG7_RO(val)   SET_REGISTER( "mtspr 263,%0", val )
+#define  GET_SPRG0()	     GET_REGISTER( "mfspr %0,272" )
+#define	 SET_SPRG0(val)	     SET_REGISTER( "mtspr 272,%0", val )
+#define  GET_SPRG1()	     GET_REGISTER( "mfspr %0,273" )
+#define	 SET_SPRG1(val)	     SET_REGISTER( "mtspr 273,%0", val )
+#define  GET_SPRG2()	     GET_REGISTER( "mfspr %0,274" )
+#define	 SET_SPRG2(val)	     SET_REGISTER( "mtspr 274,%0", val )
+#define  GET_SPRG3()	     GET_REGISTER( "mfspr %0,275" )
+#define	 SET_SPRG3(val)	     SET_REGISTER( "mtspr 275,%0", val )
+#define  GET_SPRG4()	     GET_REGISTER( "mfspr %0,276" )
+#define	 SET_SPRG4(val)      SET_REGISTER( "mtspr 276,%0", val )
+#define  GET_SPRG5()	     GET_REGISTER( "mfspr %0,277" )
+#define	 SET_SPRG5(val)	     SET_REGISTER( "mtspr 277,%0", val )
+#define  GET_SPRG6()	     GET_REGISTER( "mfspr %0,278" )
+#define	 SET_SPRG6(val)	     SET_REGISTER( "mtspr 278,%0", val )
+#define  GET_SPRG7()	     GET_REGISTER( "mfspr %0,279" )
+#define	 SET_SPRG7(val)	     SET_REGISTER( "mtspr 279,%0", val )
+#define  GET_EAR()	     GET_REGISTER( "mfspr %0,282" )
+#define	 SET_EAR(val)	     SET_REGISTER( "mtspr 282,%0", val )
+#define  GET_TBL()	     GET_REGISTER( "mfspr %0,284" )
+#define	 SET_TBL(val)	     SET_REGISTER( "mtspr 284,%0", val )
+#define  GET_TBU()	     GET_REGISTER( "mfspr %0,285" )
+#define	 SET_TBU(val)	     SET_REGISTER( "mtspr 285,%0", val )
+#define  GET_PVR()	     GET_REGISTER( "mfspr %0,287" )
+#define	 SET_PVR(val)	     SET_REGISTER( "mtspr 287,%0", val )
+#define  GET_IC_CST()	     GET_REGISTER( "mfspr %0,560" )
+#define	 SET_IC_CST(val)     SET_REGISTER( "mtspr 560,%0", val )
+#define  GET_IC_ADR()	     GET_REGISTER( "mfspr %0,561" )
+#define	 SET_IC_ADR(val)     SET_REGISTER( "mtspr 561,%0", val )
+#define  GET_IC_DAT()	     GET_REGISTER( "mfspr %0,562" )
+#define	 SET_IC_DAT(val)     SET_REGISTER( "mtspr 562,%0", val )
+#define  GET_DC_CST()	     GET_REGISTER( "mfspr %0,568" )
+#define	 SET_DC_CST(val)     SET_REGISTER( "mtspr 568,%0", val )
+#define  GET_DC_ADR()	     GET_REGISTER( "mfspr %0,569" )
+#define	 SET_DC_ADR(val)     SET_REGISTER( "mtspr 569,%0", val )
+#define  GET_DC_DAT()	     GET_REGISTER( "mfspr %0,570" )
+#define	 SET_DC_DAT(val)     SET_REGISTER( "mtspr 570,%0", val )
+#define  GET_DPDR()	     GET_REGISTER( "mfspr %0,630" )
+#define	 SET_DPDR(val)	     SET_REGISTER( "mtspr 630,%0", val )
+#define  GET_IMMR()	     GET_REGISTER( "mfspr %0,638" )
+#define	 SET_IMMR(val)	     SET_REGISTER( "mtspr 638,%0", val )
+#define  GET_MI_CTR()	     GET_REGISTER( "mfspr %0,784" )
+#define	 SET_MI_CTR(val)     SET_REGISTER( "mtspr 784,%0", val )
+#define  GET_MI_AP()	     GET_REGISTER( "mfspr %0,786" )
+#define	 SET_MI_AP(val)	     SET_REGISTER( "mtspr 786,%0", val )
+#define  GET_MI_EPN()	     GET_REGISTER( "mfspr %0,787" )
+#define	 SET_MI_EPN(val)     SET_REGISTER( "mtspr 787,%0", val )
+#define  GET_MI_TWC()	     GET_REGISTER( "mfspr %0,789" )
+#define	 SET_MI_TWC(val)     SET_REGISTER( "mtspr 789,%0", val )
+#define  GET_MI_RPN()	     GET_REGISTER( "mfspr %0,790" )
+#define	 SET_MI_RPN(val)     SET_REGISTER( "mtspr 790,%0", val )
+#define  GET_MD_CTR()	     GET_REGISTER( "mfspr %0,792" )
+#define	 SET_MD_CTR(val)     SET_REGISTER( "mtspr 792,%0", val )
+#define  GET_M_CASID()	     GET_REGISTER( "mfspr %0,793" )
+#define	 SET_M_CASID(val)    SET_REGISTER( "mtspr 793,%0", val )
+#define  GET_MD_AP()	     GET_REGISTER( "mfspr %0,794" )
+#define	 SET_MD_AP(val)	     SET_REGISTER( "mtspr ,794%0", val )
+#define  GET_MD_EPN()	     GET_REGISTER( "mfspr %0,795" )
+#define	 SET_MD_EPN(val)     SET_REGISTER( "mtspr 795,%0", val )
+#define  GET_M_TWB()	     GET_REGISTER( "mfspr %0,796" )
+#define	 SET_M_TWB(val)	     SET_REGISTER( "mtspr 796,%0", val )
+#define  GET_MD_TWC()	     GET_REGISTER( "mfspr %0,797" )
+#define	 SET_MD_TWC(val)     SET_REGISTER( "mtspr 797,%0", val )
+#define  GET_MD_RPN()	     GET_REGISTER( "mfspr %0,798" )
+#define	 SET_MD_RPN(val)     SET_REGISTER( "mtspr 798,%0", val )
+#define  GET_M_TW()	     GET_REGISTER( "mfspr %0,799" )
+#define	 SET_M_TW(val)	     SET_REGISTER( "mtspr 799,%0", val )
+#define  GET_MI_DBCAM()      GET_REGISTER( "mfspr %0,816" )
+#define	 SET_MI_DBCAM(val)   SET_REGISTER( "mtspr 816,%0", val )
+#define  GET_MI_DBRAM0()     GET_REGISTER( "mfspr %0,817" )
+#define	 SET_MI_DBRAM0(val)  SET_REGISTER( "mtspr 817,%0", val )
+#define  GET_MI_DBRAM1()     GET_REGISTER( "mfspr %0,818" )
+#define	 SET_MI_DBRAM1(val)  SET_REGISTER( "mtspr 818,%0", val )
+#define  GET_MD_DBCAM()      GET_REGISTER( "mfspr %0,824" )
+#define	 SET_MD_DBCA(val)    SET_REGISTER( "mtspr 824,%0", val )
+#define  GET_MD_DBRAM0()     GET_REGISTER( "mfspr %0,825" )
+#define	 SET_MD_DBRAM0(val)  SET_REGISTER( "mtspr 825,%0", val )
+#define  GET_MD_DBRAM1()     GET_REGISTER( "mfspr %0,826" )
+#define	 SET_MD_DBRAM1(val)  SET_REGISTER( "mtspr 826,%0", val )
+#define  GET_ZPR()           GET_REGISTER( "mfspr %0,944" )
+#define	 SET_ZPR(val)        SET_REGISTER( "mtspr 944,%0", val )
+#define  GET_PID()	     GET_REGISTER( "mfspr %0,945" )
+#define	 SET_PID(val)	     SET_REGISTER( "mtspr 945,%0", val )
+#define  GET_CCR0()	     GET_REGISTER( "mfspr %0,947" )
+#define	 SET_CCR0(val)	     SET_REGISTER( "mtspr 947,%0", val )
+#define	 GET_IAC3()	     GET_REGISTER( "mfspr %0,948" )
+#define	 SET_IAC3(val)	     SET_REGISTER( "mtspr 948,%0", val )
+#define	 GET_IAC4()	     GET_REGISTER( "mfspr %0,949" )
+#define	 SET_IAC4(val)	     SET_REGISTER( "mtspr 949,%0", val )
+#define	 GET_DVC1()	     GET_REGISTER( "mfspr %0,950" )
+#define	 SET_DVC1(val)	     SET_REGISTER( "mtspr 950,%0", val )
+#define	 GET_DVC2()	     GET_REGISTER( "mfspr %0,951" )
+#define	 SET_DVC2(val)	     SET_REGISTER( "mtspr 951,%0", val )
+#define	 GET_SGR()	     GET_REGISTER( "mfspr %0,953" )
+#define	 SET_SGR(val)	     SET_REGISTER( "mtspr 953,%0", val )
+#define	 GET_DCWR()	     GET_REGISTER( "mfspr %0,954" )
+#define	 SET_DCWR(val)	     SET_REGISTER( "mtspr 954,%0", val )
+#define	 GET_SLER()	     GET_REGISTER( "mfspr %0,955" )
+#define	 SET_SLER(val)	     SET_REGISTER( "mtspr 955,%0", val )
+#define	 GET_SU0R()	     GET_REGISTER( "mfspr %0,956" )
+#define	 SET_SU0R(val)	     SET_REGISTER( "mtspr 956,%0", val )
+#define	 GET_DBCR1()	     GET_REGISTER( "mfspr %0,957" )
+#define	 SET_DBCR1(val)	     SET_REGISTER( "mtspr 957,%0", val )
+#define	 GET_ICDBDR()	     GET_REGISTER( "mfspr %0,979" )
+#define	 SET_ICDBDR(val)     SET_REGISTER( "mtspr 979,%0", val )
+#define	 GET_ESR()	     GET_REGISTER( "mfspr %0,980" )
+#define	 SET_ESR(val)	     SET_REGISTER( "mtspr 980,%0", val )
+#define	 GET_DEAR()	     GET_REGISTER( "mfspr %0,981" )
+#define	 SET_DEAR(val)	     SET_REGISTER( "mtspr 981,%0", val )
+#define	 GET_EVPR()	     GET_REGISTER( "mfspr %0,982" )
+#define	 SET_EVPR(val)	     SET_REGISTER( "mtspr 982,%0", val )
+#define	 GET_TSR()	     GET_REGISTER( "mfspr %0,984" )
+#define	 SET_TSR(val)	     SET_REGISTER( "mtspr 984,%0", val )
+#define	 GET_TCR()	     GET_REGISTER( "mfspr %0,986" )
+#define	 SET_TCR(val)	     SET_REGISTER( "mtspr 986,%0", val )
+#define	 GET_PIT()	     GET_REGISTER( "mfspr %0,987" )
+#define	 SET_PIT(val)	     SET_REGISTER( "mtspr 987,%0", val )
+#define	 GET_SRR2()	     GET_REGISTER( "mfspr %0,990" )
+#define	 SET_SRR2(val)	     SET_REGISTER( "mtspr 990,%0", val )
+#define	 GET_SRR3()	     GET_REGISTER( "mfspr %0,991" )
+#define	 SET_SRR3(val)	     SET_REGISTER( "mtspr 991,%0", val )
+#define	 GET_DBSR()	     GET_REGISTER( "mfspr %0,1008" )
+#define	 SET_DBSR(val)	     SET_REGISTER( "mtspr 1008,%0", val )
+#define	 GET_DBCR0()	     GET_REGISTER( "mfspr %0,1010" )
+#define	 SET_DBCR0(val)	     SET_REGISTER( "mtspr 1010,%0", val )
+#define	 GET_IABR()	     GET_REGISTER( "mfspr %0,1010" )
+#define	 SET_IABR(val)	     SET_REGISTER( "mtspr 1010,%0", val )
+#define	 GET_IAC1()	     GET_REGISTER( "mfspr %0,1012" )
+#define	 SET_IAC1(val)	     SET_REGISTER( "mtspr 1012,%0", val )
+#define	 GET_IAC2()	     GET_REGISTER( "mfspr %0,1013" )
+#define	 SET_IAC2(val)	     SET_REGISTER( "mtspr 1013,%0", val )
+#define	 GET_DAC1()	     GET_REGISTER( "mfspr %0,1014" )
+#define	 SET_DAC1(val)	     SET_REGISTER( "mtspr 1014,%0", val )
+#define	 GET_DAC2()	     GET_REGISTER( "mfspr %0,1015" )
+#define	 SET_DAC2(val)	     SET_REGISTER( "mtspr 1015,%0", val )
+#define	 GET_DCCR()	     GET_REGISTER( "mfspr %0,1018" )
+#define	 SET_DCCR(val)	     SET_REGISTER( "mtspr 1018,%0", val )
+#define	 GET_ICCR()	     GET_REGISTER( "mfspr %0,1019" )
+#define	 SET_ICCR(val)	     SET_REGISTER( "mtspr 1019,%0", val )
+
+#endif /* _REGS_H */
+
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/include/bedbug/tables.h b/include/bedbug/tables.h
new file mode 100644
index 0000000..e675de3
--- /dev/null
+++ b/include/bedbug/tables.h
@@ -0,0 +1,601 @@
+/* $Id$ */
+
+#ifndef TABLES_H
+#define TABLES_H
+
+/* This is only included by common/bedbug.c, and depends on the following
+ * files to already be included
+ *   common.h
+ *   bedbug/bedbug.h
+ *   bedbug/ppc.h
+ *   bedbug/regs.h
+ */
+
+struct operand operands[] = {
+  /*Field    Name     Bits  Shift  Hint			   Position	*/
+  /*-----    ------   ----- -----  ----			   ------------ */
+  { O_AA,    "O_AA",	1,     1,  OH_SILENT },		/*   30		*/
+  { O_BD,    "O_BD",   14,     2,  OH_ADDR },		/* 16-29	*/
+  { O_BI,    "O_BI",	5,    16,  0 },			/* 11-15	*/
+  { O_BO,    "O_BO",	5,    21,  0 },			/*  6-10	*/
+  { O_crbD,  "O_crbD",	5,    21,  0 },			/*  6-10	*/
+  { O_crbA,  "O_crbA",	5,    16,  0 },			/* 11-15	*/
+  { O_crbB,  "O_crbB",	5,    11,  0 },			/* 16-20	*/
+  { O_CRM,   "O_CRM",	8,    12,  0 },			/* 12-19	*/
+  { O_d,     "O_d",    15,     0,  OH_OFFSET },		/* 16-31	*/
+  { O_frC,   "O_frC",	5,     6,  0 },			/* 21-25	*/
+  { O_frD,   "O_frD",	5,    21,  0 },			/*  6-10	*/
+  { O_frS,   "O_frS",	5,    21,  0 },			/*  6-10	*/
+  { O_IMM,   "O_IMM",	4,    12,  0 },			/* 16-19	*/
+  { O_LI,    "O_LI",   24,     2,  OH_ADDR },		/*  6-29	*/
+  { O_LK,    "O_LK",	1,     0,  OH_SILENT },		/*   31		*/
+  { O_MB,    "O_MB",	5,     6,  0 },			/* 21-25	*/
+  { O_ME,    "O_ME",	5,     1,  0 },			/* 26-30	*/
+  { O_NB,    "O_NB",	5,    11,  0 },			/* 16-20	*/
+  { O_OE,    "O_OE",	1,    10,  OH_SILENT },		/*   21		*/
+  { O_rA,    "O_rA",	5,    16,  OH_REG },		/* 11-15	*/
+  { O_rB,    "O_rB",	5,    11,  OH_REG },		/* 16-20	*/
+  { O_Rc,    "O_Rc",	1,     0,  OH_SILENT },		/*   31		*/
+  { O_rD,    "O_rD",	5,    21,  OH_REG },		/*  6-10	*/
+  { O_rS,    "O_rS",	5,    21,  OH_REG },		/*  6-10	*/
+  { O_SH,    "O_SH",	5,    11,  0 },			/* 16-20	*/
+  { O_SIMM,  "O_SIMM", 16,     0,  0 },			/* 16-31	*/
+  { O_SR,    "O_SR",	4,    16,  0 },			/* 12-15	*/
+  { O_TO,    "O_TO",	5,    21,  0 },			/*  6-10	*/
+  { O_UIMM,  "O_UIMM", 16,     0,  0 },			/* 16-31	*/
+  { O_crfD,  "O_crfD",	3,    23,  0 },			/*  6- 8	*/
+  { O_crfS,  "O_crfS",	3,    18,  0 },			/* 11-13	*/
+  { O_L,     "O_L",	1,    21,  0 },			/*   10		*/
+  { O_spr,   "O_spr",  10,    11,  OH_SPR },		/* 11-20	*/
+  { O_tbr,   "O_tbr",  10,    11,  OH_TBR },		/* 11-20	*/
+  { O_cr2,   "O_cr2",	0,     0,  OH_LITERAL },	/* "cr2"	*/
+};
+
+const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
+
+/* A note about the fields array in the opcodes structure:
+   The operands are listed in the order they appear in the output.
+
+   This table is arranged in numeric order of the opcode.  Note that some
+   opcodes have defined bits in odd places so not all forms of a command
+   will be in the same place.  This is done so that a binary search can be
+   done to find the opcodes.  Note that table D.2 in the MPC860 User's
+   Manual "Instructions Sorted by Opcode" does not account for these
+   bit locations */
+
+struct opcode opcodes[] = {
+  { D_OPCODE(3),	   D_MASK,   {O_TO, O_rA, O_SIMM, 0},
+    0,		     "twi",	     0 },
+  { D_OPCODE(7),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "mulli",	     0 },
+  { D_OPCODE(8),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "subfic",	     0 },
+  { D_OPCODE(10),	   D_MASK,   {O_crfD, O_L, O_rA, O_UIMM, 0},
+    0,		     "cmpli",	     0 },
+  { D_OPCODE(11),	   D_MASK,   {O_crfD, O_L, O_rA, O_SIMM, 0},
+    0,		     "cmpi",	     0 },
+  { D_OPCODE(12),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addic",	     0 },
+  { D_OPCODE(13),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addic.",	     0 },
+  { D_OPCODE(14),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addi",	     H_RA0_IS_0 },
+  { D_OPCODE(15),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addis",	     H_RA0_IS_0|H_IMM_HIGH },
+  { B_OPCODE(16,0,0),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    handle_bc,	     "bc",	     H_RELATIVE },
+  { B_OPCODE(16,0,1),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bcl",	     H_RELATIVE },
+  { B_OPCODE(16,1,0),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bca",	     0 },
+  { B_OPCODE(16,1,1),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bcla",	     0 },
+  { SC_OPCODE(17),	   SC_MASK,  {0},
+    0,		     "sc",	     0 },
+  { I_OPCODE(18,0,0),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "b",	     H_RELATIVE },
+  { I_OPCODE(18,0,1),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "bl",	     H_RELATIVE },
+  { I_OPCODE(18,1,0),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "ba",	     0 },
+  { I_OPCODE(18,1,1),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "bla",	     0 },
+  { XL_OPCODE(19,0,0),	   XL_MASK,  {O_crfD, O_crfS},
+    0,		     "mcrf",	     0 },
+  { XL_OPCODE(19,16,0),    XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bclr",	     0 },
+  { XL_OPCODE(19,16,1),    XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bclrl",	     0 },
+  { XL_OPCODE(19,33,0),    XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crnor",	     0 },
+  { XL_OPCODE(19,50,0),    XL_MASK,  {0},
+    0,		     "rfi",	     0 },
+  { XL_OPCODE(19,129,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crandc",	     0 },
+  { XL_OPCODE(19,150,0),   XL_MASK,  {0},
+    0,		     "isync",	     0 },
+  { XL_OPCODE(19,193,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crxor",	     0 },
+  { XL_OPCODE(19,225,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crnand",	     0 },
+  { XL_OPCODE(19,257,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crand",	     0 },
+  { XL_OPCODE(19,289,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "creqv",	     0 },
+  { XL_OPCODE(19,417,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crorc",	     0 },
+  { XL_OPCODE(19,449,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "cror",	     0 },
+  { XL_OPCODE(19,528,0),   XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bcctr",	     0 },
+  { XL_OPCODE(19,528,1),   XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bcctrl",	     0 },
+  { M_OPCODE(20,0),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwimi",	     0 },
+  { M_OPCODE(20,1),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwimi.",      0 },
+  { M_OPCODE(21,0),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwinm",	     0 },
+  { M_OPCODE(21,1),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwinm.",      0 },
+  { M_OPCODE(23,0),	   M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwnm",	     0 },
+  { M_OPCODE(23,1),	   M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwnm.",	     0 },
+  { D_OPCODE(24),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "ori",	     0 },
+  { D_OPCODE(25),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "oris",	     H_IMM_HIGH },
+  { D_OPCODE(26),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "xori",	     0 },
+  { D_OPCODE(27),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "xoris",	     H_IMM_HIGH },
+  { D_OPCODE(28),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "andi.",	     0 },
+  { D_OPCODE(29),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "andis.",	     H_IMM_HIGH },
+  { X_OPCODE(31,0,0),	   X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
+    0,		     "cmp",	     0 },
+  { X_OPCODE(31,4,0),	   X_MASK,   {O_TO, O_rA, O_rB, 0},
+    0,		     "tw",	     0 },
+  { XO_OPCODE(31,8,0,0),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfc",	     0 },
+  { XO_OPCODE(31,8,0,1),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfc.",	     0 },
+  { XO_OPCODE(31,10,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addc",	     0 },
+  { XO_OPCODE(31,10,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addc.",	     0 },
+  { XO_OPCODE(31,11,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhwu",	     0 },
+  { XO_OPCODE(31,11,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhwu.",      0 },
+  { X_OPCODE(31,19,0),	   X_MASK,   {O_rD, 0},
+    0,		     "mfcr",	     0 },
+  { X_OPCODE(31,20,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwarx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,23,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwzx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,24,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "slw",	     0 },
+  { X_OPCODE(31,24,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "slw.",	     0 },
+  { X_OPCODE(31,26,0),	   X_MASK,   {O_rA, O_rS, O_Rc, 0 },
+    0,		     "cntlzw",	     0 },
+  { X_OPCODE(31,26,1),	   X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "cntlzw.",      0 },
+  { X_OPCODE(31,28,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "and",	     0 },
+  { X_OPCODE(31,28,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "and.",	     0 },
+  { X_OPCODE(31,32,0),	   X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
+    0,		     "cmpl",	     0 },
+  { XO_OPCODE(31,40,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subf",	     0 },
+  { XO_OPCODE(31,40,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subf.",	     0 },
+  { X_OPCODE(31,54,0),	   X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbst",	     H_RA0_IS_0 },
+  { X_OPCODE(31,55,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwzux",	     0 },
+  { X_OPCODE(31,60,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "andc",	     0 },
+  { X_OPCODE(31,60,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "andc.",	     0 },
+  { XO_OPCODE(31,75,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhw",	     0 },
+  { XO_OPCODE(31,75,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhw.",	     0 },
+  { X_OPCODE(31,83,0),	   X_MASK,   {O_rD, 0},
+    0,		     "mfmsr",	     0 },
+  { X_OPCODE(31,86,0),	   X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbf",	     H_RA0_IS_0 },
+  { X_OPCODE(31,87,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lbzx",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,104,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "neg",	     0 },
+  { XO_OPCODE(31,104,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "neg.",	     0 },
+  { X_OPCODE(31,119,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lbzux",	     0 },
+  { X_OPCODE(31,124,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "nor",	     0 },
+  { X_OPCODE(31,124,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "nor.",	     0 },
+  { XO_OPCODE(31,136,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfe",	     0 },
+  { XO_OPCODE(31,136,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfe.",	     0 },
+  { XO_OPCODE(31,138,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "adde",	     0 },
+  { XO_OPCODE(31,138,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "adde.",	     0 },
+  { XFX_OPCODE(31,144,0),  XFX_MASK, {O_CRM, O_rS, 0},
+    0,		     "mtcrf",	     0 },
+  { X_OPCODE(31,146,0),    X_MASK,   {O_rS, 0},
+    0,		     "mtmsr",	     0 },
+  { X_OPCODE(31,150,1),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwcx.",	     0 },
+  { X_OPCODE(31,151,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwx",	     0 },
+  { X_OPCODE(31,183,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwux",	     0 },
+  { XO_OPCODE(31,200,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfze",	     0 },
+  { XO_OPCODE(31,200,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfze.",      0 },
+  { XO_OPCODE(31,202,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addze",	     0 },
+  { XO_OPCODE(31,202,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addze.",	     0 },
+  { X_OPCODE(31,210,0),    X_MASK,   {O_SR, O_rS, 0},
+    0,		     "mtsr",	     0 },
+  { X_OPCODE(31,215,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stbx",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,232,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfme",	     0 },
+  { XO_OPCODE(31,232,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfme.",      0 },
+  { XO_OPCODE(31,234,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addme",	     0 },
+  { XO_OPCODE(31,234,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addme.",	     0 },
+  { XO_OPCODE(31,235,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullw",	     0 },
+  { XO_OPCODE(31,235,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullw.",	     0 },
+  { X_OPCODE(31,242,0),    X_MASK,   {O_rS, O_rB, 0},
+    0,		     "mtsrin",	     0 },
+  { X_OPCODE(31,246,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbtst",	     H_RA0_IS_0 },
+  { X_OPCODE(31,247,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stbux",	     0 },
+  { XO_OPCODE(31,266,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "add",	     0 },
+  { XO_OPCODE(31,266,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "add.",	     0 },
+  { X_OPCODE(31,278,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbt",	     H_RA0_IS_0 },
+  { X_OPCODE(31,279,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhzx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,284,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "eqv",	     0 },
+  { X_OPCODE(31,284,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "eqv.",	     0 },
+  { X_OPCODE(31,306,0),    X_MASK,   {O_rB, 0},
+    0,		     "tlbie",	     0 },
+  { X_OPCODE(31,310,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "eciwx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,311,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhzux",	     0 },
+  { X_OPCODE(31,316,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "xor",	     0 },
+  { X_OPCODE(31,316,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "xor.",	     0 },
+  { XFX_OPCODE(31,339,0),  XFX_MASK, {O_rD, O_spr, 0},
+    0,		     "mfspr",	     0 },
+  { X_OPCODE(31,343,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhax",	     H_RA0_IS_0 },
+  { X_OPCODE(31,370,0),    X_MASK,   {0},
+    0,		     "tlbia",	     0 },
+  { XFX_OPCODE(31,371,0),  XFX_MASK, {O_rD, O_tbr, 0},
+    0,		     "mftb",	     0 },
+  { X_OPCODE(31,375,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhaux",	     0 },
+  { X_OPCODE(31,407,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "sthx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,412,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "orc",	     0 },
+  { X_OPCODE(31,412,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "orc.",	     0 },
+  { X_OPCODE(31,438,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "ecowx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,439,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "sthux",	     0 },
+  { X_OPCODE(31,444,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "or",	     0 },
+  { X_OPCODE(31,444,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "or.",	     0 },
+  { XO_OPCODE(31,459,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwu",	     0 },
+  { XO_OPCODE(31,459,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwu.",	     0 },
+  { XFX_OPCODE(31,467,0),  XFX_MASK, {O_spr, O_rS, 0},
+    0,		     "mtspr",	     0 },
+  { X_OPCODE(31,470,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbi",	     H_RA0_IS_0 },
+  { X_OPCODE(31,476,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "nand",	     0 },
+  { X_OPCODE(31,476,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc,0},
+    0,		     "nand.",	     0 },
+  { XO_OPCODE(31,491,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divw",	     0 },
+  { XO_OPCODE(31,491,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divw.",	     0 },
+  { X_OPCODE(31,512,0),    X_MASK,   {O_crfD, 0},
+    0,		     "mcrxr",	     0 },
+  { XO_OPCODE(31,8,1,0),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfco",	     0 },
+  { XO_OPCODE(31,8,1,1),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfco.",      0 },
+  { XO_OPCODE(31,10,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addco",	     0 },
+  { XO_OPCODE(31,10,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addco.",	     0 },
+  { X_OPCODE(31,533,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lswx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,534,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwbrx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,536,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "srw",	     0 },
+  { X_OPCODE(31,536,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "srw.",	     0 },
+  { XO_OPCODE(31,40,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfo",	     0 },
+  { XO_OPCODE(31,40,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfo.",	     0 },
+  { X_OPCODE(31,566,0),    X_MASK,   {0},
+    0,		     "tlbsync",      0 },
+  { X_OPCODE(31,595,0),    X_MASK,   {O_rD, O_SR, 0},
+    0,		     "mfsr",	     0 },
+  { X_OPCODE(31,597,0),    X_MASK,   {O_rD, O_rA, O_NB, 0},
+    0,		     "lswi",	     H_RA0_IS_0 },
+  { X_OPCODE(31,598,0),    X_MASK,   {0},
+    0,		     "sync",	     0 },
+  { XO_OPCODE(31,104,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "nego",	     0 },
+  { XO_OPCODE(31,104,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "nego.",	     0 },
+  { XO_OPCODE(31,136,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfeo",	     0 },
+  { XO_OPCODE(31,136,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfeo.",      0 },
+  { XO_OPCODE(31,138,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addeo",	     0 },
+  { XO_OPCODE(31,138,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addeo.",	     0 },
+  { X_OPCODE(31,659,0),    X_MASK,   {O_rD, O_rB, 0},
+    0,		     "mfsrin",	     0 },
+  { X_OPCODE(31,661,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stswx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,662,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwbrx",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,200,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfzeo",      0 },
+  { XO_OPCODE(31,200,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfzeo.",     0 },
+  { XO_OPCODE(31,202,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addzeo",	     0 },
+  { XO_OPCODE(31,202,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addzeo.",      0 },
+  { X_OPCODE(31,725,0),    X_MASK,   {O_rS, O_rA, O_NB, 0},
+    0,		     "stswi",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,232,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfmeo",      0 },
+  { XO_OPCODE(31,232,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfmeo.",     0 },
+  { XO_OPCODE(31,234,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addmeo",	     0 },
+  { XO_OPCODE(31,234,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addmeo.",      0 },
+  { XO_OPCODE(31,235,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullwo",	     0 },
+  { XO_OPCODE(31,235,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullwo.",      0 },
+  { XO_OPCODE(31,266,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addo",	     0 },
+  { XO_OPCODE(31,266,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addo.",	     0 },
+  { X_OPCODE(31,790,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhbrx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,792,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "sraw",	     0 },
+  { X_OPCODE(31,792,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "sraw.",	     0 },
+  { X_OPCODE(31,824,0),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
+    0,		     "srawi",	     0 },
+  { X_OPCODE(31,824,1),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
+    0,		     "srawi.",	     0 },
+  { X_OPCODE(31,854,0),    X_MASK,   {0},
+    0,		     "eieio",	     0 },
+  { X_OPCODE(31,918,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "sthbrx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,922,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsh",	     0 },
+  { X_OPCODE(31,922,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsh.",	     0 },
+  { X_OPCODE(31,954,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsb",	     0 },
+  { X_OPCODE(31,954,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsb.",	     0 },
+  { XO_OPCODE(31,459,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwuo",	     0 },
+  { XO_OPCODE(31,459,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwuo.",      0 },
+  { X_OPCODE(31,978,0),    X_MASK,   {O_rB, 0},
+    0,		     "tlbld",	     0 },
+  { X_OPCODE(31,982,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "icbi",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,491,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwo",	     0 },
+  { XO_OPCODE(31,491,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwo.",	     0 },
+  { X_OPCODE(31,1010,0),   X_MASK,   {O_rB, 0},
+    0,		     "tlbli",	     0 },
+  { X_OPCODE(31,1014,0),   X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbz",	     H_RA0_IS_0 },
+  { D_OPCODE(32),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lwz",	     H_RA0_IS_0 },
+  { D_OPCODE(33),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lwzu",	     0 },
+  { D_OPCODE(34),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lbz",	     H_RA0_IS_0 },
+  { D_OPCODE(35),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lbzu",	     0 },
+  { D_OPCODE(36),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stw",	     H_RA0_IS_0 },
+  { D_OPCODE(37),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stwu",	     0 },
+  { D_OPCODE(38),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stb",	     H_RA0_IS_0 },
+  { D_OPCODE(39),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stbu",	     0 },
+  { D_OPCODE(40),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhz",	     H_RA0_IS_0 },
+  { D_OPCODE(41),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhzu",	     0 },
+  { D_OPCODE(42),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lha",	     H_RA0_IS_0 },
+  { D_OPCODE(43),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhau",	     0 },
+  { D_OPCODE(44),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "sth",	     H_RA0_IS_0 },
+  { D_OPCODE(45),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "sthu",	     0 },
+  { D_OPCODE(46),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lmw",	     H_RA0_IS_0 },
+  { D_OPCODE(47),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stmw",	     H_RA0_IS_0 },
+};
+
+const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);
+
+struct spr_info spr_map[] = {
+  { SPR_XER,	"XER" },
+  { SPR_LR,	"LR" },
+  { SPR_CTR,	"CTR" },
+  { SPR_DSISR,	"DSISR" },
+  { SPR_DAR,	"DAR" },
+  { SPR_DEC,	"DEC" },
+  { SPR_SRR0,	"SRR0" },
+  { SPR_SRR1,	"SRR1" },
+  { SPR_EIE,	"EIE" },
+  { SPR_EID,	"EID" },
+  { SPR_CMPA,	"CMPA" },
+  { SPR_CMPB,	"CMPB" },
+  { SPR_CMPC,	"CMPC" },
+  { SPR_CMPD,	"CMPD" },
+  { SPR_ICR,	"ICR" },
+  { SPR_DER,	"DER" },
+  { SPR_COUNTA,	"COUNTA" },
+  { SPR_COUNTB,	"COUNTB" },
+  { SPR_CMPE,	"CMPE" },
+  { SPR_CMPF,	"CMPF" },
+  { SPR_CMPG,	"CMPG" },
+  { SPR_CMPH,	"CMPH" },
+  { SPR_LCTRL1,	"LCTRL1" },
+  { SPR_LCTRL2,	"LCTRL2" },
+  { SPR_ICTRL,	"ICTRL" },
+  { SPR_BAR,	"BAR" },
+  { SPR_USPRG0,	"USPRG0" },
+  { SPR_SPRG4_RO,	"SPRG4_RO" },
+  { SPR_SPRG5_RO,	"SPRG5_RO" },
+  { SPR_SPRG6_RO,	"SPRG6_RO" },
+  { SPR_SPRG7_RO,	"SPRG7_RO" },
+  { SPR_SPRG0,	"SPRG0" },
+  { SPR_SPRG1,	"SPRG1" },
+  { SPR_SPRG2,	"SPRG2" },
+  { SPR_SPRG3,	"SPRG3" },
+  { SPR_SPRG4,	"SPRG4" },
+  { SPR_SPRG5,	"SPRG5" },
+  { SPR_SPRG6,	"SPRG6" },
+  { SPR_SPRG7,	"SPRG7" },
+  { SPR_EAR,	"EAR" },
+  { SPR_TBL,	"TBL" },
+  { SPR_TBU,	"TBU" },
+  { SPR_IC_CST,	"IC_CST" },
+  { SPR_IC_ADR,	"IC_ADR" },
+  { SPR_IC_DAT,	"IC_DAT" },
+  { SPR_DC_CST,	"DC_CST" },
+  { SPR_DC_ADR,	"DC_ADR" },
+  { SPR_DC_DAT,	"DC_DAT" },
+  { SPR_DPDR,	"DPDR" },
+  { SPR_IMMR,	"IMMR" },
+  { SPR_MI_CTR,	"MI_CTR" },
+  { SPR_MI_AP,	"MI_AP" },
+  { SPR_MI_EPN,	"MI_EPN" },
+  { SPR_MI_TWC,	"MI_TWC" },
+  { SPR_MI_RPN,	"MI_RPN" },
+  { SPR_MD_CTR,	"MD_CTR" },
+  { SPR_M_CASID,	"M_CASID" },
+  { SPR_MD_AP,	"MD_AP" },
+  { SPR_MD_EPN,	"MD_EPN" },
+  { SPR_M_TWB,	"M_TWB" },
+  { SPR_MD_TWC,	"MD_TWC" },
+  { SPR_MD_RPN,	"MD_RPN" },
+  { SPR_M_TW,	"M_TW" },
+  { SPR_MI_DBCAM,	"MI_DBCAM" },
+  { SPR_MI_DBRAM0,	"MI_DBRAM0" },
+  { SPR_MI_DBRAM1,	"MI_DBRAM1" },
+  { SPR_MD_DBCAM,	"MD_DBCAM" },
+  { SPR_MD_DBRAM0,	"MD_DBRAM0" },
+  { SPR_MD_DBRAM1,	"MD_DBRAM1" },
+  { SPR_ZPR,	"ZPR" },
+  { SPR_PID,	"PID" },
+  { SPR_CCR0,	"CCR0" },
+  { SPR_IAC3,	"IAC3" },
+  { SPR_IAC4,	"IAC4" },
+  { SPR_DVC1,	"DVC1" },
+  { SPR_DVC2,	"DVC2" },
+  { SPR_SGR,	"SGR" },
+  { SPR_DCWR,	"DCWR" },
+  { SPR_SLER,	"SLER" },
+  { SPR_SU0R,	"SU0R" },
+  { SPR_DBCR1,	"DBCR1" },
+  { SPR_ICDBDR,	"ICDBDR" },
+  { SPR_ESR,	"ESR" },
+  { SPR_DEAR,	"DEAR" },
+  { SPR_EVPR,	"EVPR" },
+  { SPR_TSR,	"TSR" },
+  { SPR_TCR,	"TCR" },
+  { SPR_PIT,	"PIT" },
+  { SPR_SRR2,	"SRR2" },
+  { SPR_SRR3,	"SRR3" },
+  { SPR_DBSR,	"DBSR" },
+  { SPR_DBCR0,	"DBCR0" },
+  { SPR_IAC1,	"IAC1" },
+  { SPR_IAC2,	"IAC2" },
+  { SPR_DAC1,	"DAC1" },
+  { SPR_DAC2,	"DAC2" },
+  { SPR_DCCR,	"DCCR" },
+  { SPR_ICCR,	"ICCR" },
+};
+
+const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]);
+
+#endif
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/include/bedbug/type.h b/include/bedbug/type.h
new file mode 100644
index 0000000..b7b447b
--- /dev/null
+++ b/include/bedbug/type.h
@@ -0,0 +1,26 @@
+#ifndef _TYPE_BEDBUG_H
+#define _TYPE_BEDBUG_H
+
+/* Supporting routines */
+int bedbug_puts (const char *);
+void bedbug_init (void);
+void bedbug860_init (void);
+void do_bedbug_breakpoint (struct pt_regs *);
+void bedbug_main_loop (unsigned long, struct pt_regs *);
+
+
+typedef struct {
+	int hw_debug_enabled;
+	int stopped;
+	int current_bp;
+	struct pt_regs *regs;
+
+	void (*do_break) (cmd_tbl_t *, int, int, char * const []);
+	void (*break_isr) (struct pt_regs *);
+	int (*find_empty) (void);
+	int (*set) (int, unsigned long);
+	int (*clear) (int);
+} CPU_DEBUG_CTX;
+
+
+#endif /* _TYPE_BEDBUG_H  */
diff --git a/include/binman_sym.h b/include/binman_sym.h
new file mode 100644
index 0000000..ffb7c15
--- /dev/null
+++ b/include/binman_sym.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Symbol access for symbols set up by binman as part of the build.
+ *
+ * This allows C code to access the position of a particular part of the image
+ * assembled by binman.
+ *
+ * Copyright (c) 2017 Google, Inc
+ */
+
+#ifndef __BINMAN_SYM_H
+#define __BINMAN_SYM_H
+
+#define BINMAN_SYM_MISSING	(-1UL)
+
+#ifdef CONFIG_BINMAN
+
+/**
+ * binman_symname() - Internal fnuction to get a binman symbol name
+ *
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ * @returns name of the symbol for that entry and property
+ */
+#define binman_symname(_entry_name, _prop_name) \
+	_binman_ ## _entry_name ## _prop_ ## _prop_name
+
+/**
+ * binman_sym_declare() - Declare a symbol that will be used at run-time
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ */
+#define binman_sym_declare(_type, _entry_name, _prop_name) \
+	_type binman_symname(_entry_name, _prop_name) \
+		__attribute__((aligned(4), unused, section(".binman_sym")))
+
+/**
+ * binman_sym_extern() - Declare a extern symbol that will be used at run-time
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ */
+#define binman_sym_extern(_type, _entry_name, _prop_name) \
+	extern _type binman_symname(_entry_name, _prop_name) \
+		__attribute__((aligned(4), unused, section(".binman_sym")))
+
+/**
+ * binman_sym_declare_optional() - Declare an optional symbol
+ *
+ * If this symbol cannot be provided by binman, an error will not be generated.
+ * Instead the image will be assigned the value BINMAN_SYM_MISSING.
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ */
+#define binman_sym_declare_optional(_type, _entry_name, _prop_name) \
+	_type binman_symname(_entry_name, _prop_name) \
+		__attribute__((aligned(4), weak, unused, \
+		section(".binman_sym")))
+
+/**
+ * binman_sym() - Access a previously declared symbol
+ *
+ * This is used to get the value of a symbol. E.g.:
+ *
+ *    ulong address = binman_sym(ulong, u_boot_spl, pos);
+ *
+ * @_type: Type f the symbol (e.g. unsigned long)
+ * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
+ * @_prop_name: Property value to get from that entry (e.g. 'pos')
+ * @returns value of that property (filled in by binman)
+ */
+#define binman_sym(_type, _entry_name, _prop_name) \
+	(*(_type *)&binman_symname(_entry_name, _prop_name))
+
+#else /* !BINMAN */
+
+#define binman_sym_declare(_type, _entry_name, _prop_name)
+
+#define binman_sym_declare_optional(_type, _entry_name, _prop_name)
+
+#define binman_sym_extern(_type, _entry_name, _prop_name)
+
+#define binman_sym(_type, _entry_name, _prop_name) BINMAN_SYM_MISSING
+
+#endif /* BINMAN */
+
+#endif
diff --git a/include/bios_emul.h b/include/bios_emul.h
new file mode 100644
index 0000000..158e0f2
--- /dev/null
+++ b/include/bios_emul.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 1996-1999 SciTech Software, Inc.
+ */
+
+#ifndef _BIOS_EMUL_H
+#define _BIOS_EMUL_H
+
+/* Include the register header directly here */
+#include "../drivers/bios_emulator/include/x86emu/regs.h"
+#include <pci.h>
+
+/****************************************************************************
+REMARKS:
+Data structure used to describe the details for the BIOS emulator system
+environment as used by the X86 emulator library.
+
+HEADER:
+biosemu.h
+
+MEMBERS:
+vgaInfo         - VGA BIOS information structure
+biosmem_base    - Base of the BIOS image
+biosmem_limit   - Limit of the BIOS image
+busmem_base     - Base of the VGA bus memory
+****************************************************************************/
+typedef struct {
+	int function;
+	int device;
+	int bus;
+	u32 VendorID;
+	u32 DeviceID;
+#ifdef CONFIG_DM_PCI
+	struct udevice *pcidev;
+#else
+	pci_dev_t pcidev;
+#endif
+	void *BIOSImage;
+	u32 BIOSImageLen;
+	u8 LowMem[1536];
+} BE_VGAInfo;
+
+struct vbe_mode_info;
+
+#ifdef CONFIG_DM_PCI
+int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
+		      int clean_up);
+#else
+int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up);
+#endif
+
+/* Run a BIOS ROM natively (only supported on x86 machines) */
+void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
+		     struct vbe_mode_info *mode_info);
+
+/**
+ * bios_set_interrupt_handler() - Install an interrupt handler for the BIOS
+ *
+ * This installs an interrupt handler that the BIOS will call when needed.
+ *
+ * @intnum:		Interrupt number to install a handler for
+ * @int_handler_func:	Function to call to handle interrupt
+ */
+void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void));
+
+void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void));
+
+#ifdef CONFIG_DM_PCI
+int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **pVGAInfo);
+
+int biosemu_run(struct udevice *dev, uchar *bios_rom, int bios_len,
+		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+		struct vbe_mode_info *mode_info);
+#else
+int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo);
+
+int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
+		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
+		struct vbe_mode_info *mode_info);
+#endif
+
+#endif
diff --git a/include/bitfield.h b/include/bitfield.h
new file mode 100644
index 0000000..579a69c
--- /dev/null
+++ b/include/bitfield.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+/*
+ * Bitfield operations
+ *
+ * These are generic bitfield operations which allow manipulation of variable
+ * width bitfields within a word. One use of this would be to use data tables
+ * to determine how to reprogram fields within R/W hardware registers.
+ *
+ * Example:
+ *
+ *            old_reg_val
+ * +--------+----+---+--+-----+----------+
+ * |        |    |   |  | old |          |
+ * +--------+----+---+--+-----+----------+
+ *
+ *            new_reg_val
+ * +--------+----+---+--+-----+----------+
+ * |        |    |   |  | new |          |
+ * +--------+----+---+--+-----+----------+
+ *
+ * mask = bitfield_mask(10, 5);
+ * old = bitfield_extract(old_reg_val, 10, 5);
+ * new_reg_val = bitfield_replace(old_reg_val, 10, 5, new);
+ *
+ * or
+ *
+ * mask = bitfield_mask(10, 5);
+ * old = bitfield_extract_by_mask(old_reg_val, mask);
+ * new_reg_val = bitfield_replace_by_mask(old_reg_val, mask, new);
+ *
+ * The numbers 10 and 5 could for example come from data
+ * tables which describe all bitfields in all registers.
+ */
+
+#include <linux/types.h>
+
+/* Produces a mask of set bits covering a range of a uint value */
+static inline uint bitfield_mask(uint shift, uint width)
+{
+	return ((1 << width) - 1) << shift;
+}
+
+/* Extract the value of a bitfield found within a given register value */
+static inline uint bitfield_extract(uint reg_val, uint shift, uint width)
+{
+	return (reg_val & bitfield_mask(shift, width)) >> shift;
+}
+
+/*
+ * Replace the value of a bitfield found within a given register value
+ * Returns the newly modified uint value with the replaced field.
+ */
+static inline uint bitfield_replace(uint reg_val, uint shift, uint width,
+				    uint bitfield_val)
+{
+	uint mask = bitfield_mask(shift, width);
+
+	return (reg_val & ~mask) | ((bitfield_val << shift) & mask);
+}
+
+/* Produces a shift of the bitfield given a mask */
+static inline uint bitfield_shift(uint mask)
+{
+	return mask ? ffs(mask) - 1 : 0;
+}
+
+/* Extract the value of a bitfield found within a given register value */
+static inline uint bitfield_extract_by_mask(uint reg_val, uint mask)
+{
+	uint shift = bitfield_shift(mask);
+
+	return (reg_val & mask) >> shift;
+}
+
+/*
+ * Replace the value of a bitfield found within a given register value
+ * Returns the newly modified uint value with the replaced field.
+ */
+static inline uint bitfield_replace_by_mask(uint reg_val, uint mask,
+					    uint bitfield_val)
+{
+	uint shift = bitfield_shift(mask);
+
+	return (reg_val & ~mask) | ((bitfield_val << shift) & mask);
+}
diff --git a/include/blk.h b/include/blk.h
new file mode 100644
index 0000000..d0c033a
--- /dev/null
+++ b/include/blk.h
@@ -0,0 +1,679 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef BLK_H
+#define BLK_H
+
+#include <efi.h>
+
+#ifdef CONFIG_SYS_64BIT_LBA
+typedef uint64_t lbaint_t;
+#define LBAFlength "ll"
+#else
+typedef ulong lbaint_t;
+#define LBAFlength "l"
+#endif
+#define LBAF "%" LBAFlength "x"
+#define LBAFU "%" LBAFlength "u"
+
+/* Interface types: */
+enum if_type {
+	IF_TYPE_UNKNOWN = 0,
+	IF_TYPE_IDE,
+	IF_TYPE_SCSI,
+	IF_TYPE_ATAPI,
+	IF_TYPE_USB,
+	IF_TYPE_DOC,
+	IF_TYPE_MMC,
+	IF_TYPE_SD,
+	IF_TYPE_SATA,
+	IF_TYPE_HOST,
+	IF_TYPE_NVME,
+	IF_TYPE_EFI,
+	IF_TYPE_VIRTIO,
+
+	IF_TYPE_COUNT,			/* Number of interface types */
+};
+
+#define BLK_VEN_SIZE		40
+#define BLK_PRD_SIZE		20
+#define BLK_REV_SIZE		8
+
+/*
+ * Identifies the partition table type (ie. MBR vs GPT GUID) signature
+ */
+enum sig_type {
+	SIG_TYPE_NONE,
+	SIG_TYPE_MBR,
+	SIG_TYPE_GUID,
+
+	SIG_TYPE_COUNT			/* Number of signature types */
+};
+
+/*
+ * With driver model (CONFIG_BLK) this is uclass platform data, accessible
+ * with dev_get_uclass_platdata(dev)
+ */
+struct blk_desc {
+	/*
+	 * TODO: With driver model we should be able to use the parent
+	 * device's uclass instead.
+	 */
+	enum if_type	if_type;	/* type of the interface */
+	int		devnum;		/* device number */
+	unsigned char	part_type;	/* partition type */
+	unsigned char	target;		/* target SCSI ID */
+	unsigned char	lun;		/* target LUN */
+	unsigned char	hwpart;		/* HW partition, e.g. for eMMC */
+	unsigned char	type;		/* device type */
+	unsigned char	removable;	/* removable device */
+#ifdef CONFIG_LBA48
+	/* device can use 48bit addr (ATA/ATAPI v7) */
+	unsigned char	lba48;
+#endif
+	lbaint_t	lba;		/* number of blocks */
+	unsigned long	blksz;		/* block size */
+	int		log2blksz;	/* for convenience: log2(blksz) */
+	char		vendor[BLK_VEN_SIZE + 1]; /* device vendor string */
+	char		product[BLK_PRD_SIZE + 1]; /* device product number */
+	char		revision[BLK_REV_SIZE + 1]; /* firmware revision */
+	enum sig_type	sig_type;	/* Partition table signature type */
+	union {
+		uint32_t mbr_sig;	/* MBR integer signature */
+		efi_guid_t guid_sig;	/* GPT GUID Signature */
+	};
+#if CONFIG_IS_ENABLED(BLK)
+	/*
+	 * For now we have a few functions which take struct blk_desc as a
+	 * parameter. This field allows them to look up the associated
+	 * device. Once these functions are removed we can drop this field.
+	 */
+	struct udevice *bdev;
+#else
+	unsigned long	(*block_read)(struct blk_desc *block_dev,
+				      lbaint_t start,
+				      lbaint_t blkcnt,
+				      void *buffer);
+	unsigned long	(*block_write)(struct blk_desc *block_dev,
+				       lbaint_t start,
+				       lbaint_t blkcnt,
+				       const void *buffer);
+	unsigned long	(*block_erase)(struct blk_desc *block_dev,
+				       lbaint_t start,
+				       lbaint_t blkcnt);
+	void		*priv;		/* driver private struct pointer */
+#endif
+};
+
+#define BLOCK_CNT(size, blk_desc) (PAD_COUNT(size, blk_desc->blksz))
+#define PAD_TO_BLOCKSIZE(size, blk_desc) \
+	(PAD_SIZE(size, blk_desc->blksz))
+
+#if CONFIG_IS_ENABLED(BLOCK_CACHE)
+/**
+ * blkcache_read() - attempt to read a set of blocks from cache
+ *
+ * @param iftype - IF_TYPE_x for type of device
+ * @param dev - device index of particular type
+ * @param start - starting block number
+ * @param blkcnt - number of blocks to read
+ * @param blksz - size in bytes of each block
+ * @param buf - buffer to contain cached data
+ *
+ * @return - '1' if block returned from cache, '0' otherwise.
+ */
+int blkcache_read(int iftype, int dev,
+		  lbaint_t start, lbaint_t blkcnt,
+		  unsigned long blksz, void *buffer);
+
+/**
+ * blkcache_fill() - make data read from a block device available
+ * to the block cache
+ *
+ * @param iftype - IF_TYPE_x for type of device
+ * @param dev - device index of particular type
+ * @param start - starting block number
+ * @param blkcnt - number of blocks available
+ * @param blksz - size in bytes of each block
+ * @param buf - buffer containing data to cache
+ *
+ */
+void blkcache_fill(int iftype, int dev,
+		   lbaint_t start, lbaint_t blkcnt,
+		   unsigned long blksz, void const *buffer);
+
+/**
+ * blkcache_invalidate() - discard the cache for a set of blocks
+ * because of a write or device (re)initialization.
+ *
+ * @param iftype - IF_TYPE_x for type of device
+ * @param dev - device index of particular type
+ */
+void blkcache_invalidate(int iftype, int dev);
+
+/**
+ * blkcache_configure() - configure block cache
+ *
+ * @param blocks - maximum blocks per entry
+ * @param entries - maximum entries in cache
+ */
+void blkcache_configure(unsigned blocks, unsigned entries);
+
+/*
+ * statistics of the block cache
+ */
+struct block_cache_stats {
+	unsigned hits;
+	unsigned misses;
+	unsigned entries; /* current entry count */
+	unsigned max_blocks_per_entry;
+	unsigned max_entries;
+};
+
+/**
+ * get_blkcache_stats() - return statistics and reset
+ *
+ * @param stats - statistics are copied here
+ */
+void blkcache_stats(struct block_cache_stats *stats);
+
+#else
+
+static inline int blkcache_read(int iftype, int dev,
+				lbaint_t start, lbaint_t blkcnt,
+				unsigned long blksz, void *buffer)
+{
+	return 0;
+}
+
+static inline void blkcache_fill(int iftype, int dev,
+				 lbaint_t start, lbaint_t blkcnt,
+				 unsigned long blksz, void const *buffer) {}
+
+static inline void blkcache_invalidate(int iftype, int dev) {}
+
+#endif
+
+#if CONFIG_IS_ENABLED(BLK)
+struct udevice;
+
+/* Operations on block devices */
+struct blk_ops {
+	/**
+	 * read() - read from a block device
+	 *
+	 * @dev:	Device to read from
+	 * @start:	Start block number to read (0=first)
+	 * @blkcnt:	Number of blocks to read
+	 * @buffer:	Destination buffer for data read
+	 * @return number of blocks read, or -ve error number (see the
+	 * IS_ERR_VALUE() macro
+	 */
+	unsigned long (*read)(struct udevice *dev, lbaint_t start,
+			      lbaint_t blkcnt, void *buffer);
+
+	/**
+	 * write() - write to a block device
+	 *
+	 * @dev:	Device to write to
+	 * @start:	Start block number to write (0=first)
+	 * @blkcnt:	Number of blocks to write
+	 * @buffer:	Source buffer for data to write
+	 * @return number of blocks written, or -ve error number (see the
+	 * IS_ERR_VALUE() macro
+	 */
+	unsigned long (*write)(struct udevice *dev, lbaint_t start,
+			       lbaint_t blkcnt, const void *buffer);
+
+	/**
+	 * erase() - erase a section of a block device
+	 *
+	 * @dev:	Device to (partially) erase
+	 * @start:	Start block number to erase (0=first)
+	 * @blkcnt:	Number of blocks to erase
+	 * @return number of blocks erased, or -ve error number (see the
+	 * IS_ERR_VALUE() macro
+	 */
+	unsigned long (*erase)(struct udevice *dev, lbaint_t start,
+			       lbaint_t blkcnt);
+
+	/**
+	 * select_hwpart() - select a particular hardware partition
+	 *
+	 * Some devices (e.g. MMC) can support partitioning at the hardware
+	 * level. This is quite separate from the normal idea of
+	 * software-based partitions. MMC hardware partitions must be
+	 * explicitly selected. Once selected only the region of the device
+	 * covered by that partition is accessible.
+	 *
+	 * The MMC standard provides for two boot partitions (numbered 1 and 2),
+	 * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
+	 *
+	 * @desc:	Block device to update
+	 * @hwpart:	Hardware partition number to select. 0 means the raw
+	 *		device, 1 is the first partition, 2 is the second, etc.
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*select_hwpart)(struct udevice *dev, int hwpart);
+};
+
+#define blk_get_ops(dev)	((struct blk_ops *)(dev)->driver->ops)
+
+/*
+ * These functions should take struct udevice instead of struct blk_desc,
+ * but this is convenient for migration to driver model. Add a 'd' prefix
+ * to the function operations, so that blk_read(), etc. can be reserved for
+ * functions with the correct arguments.
+ */
+unsigned long blk_dread(struct blk_desc *block_dev, lbaint_t start,
+			lbaint_t blkcnt, void *buffer);
+unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start,
+			 lbaint_t blkcnt, const void *buffer);
+unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start,
+			 lbaint_t blkcnt);
+
+/**
+ * blk_find_device() - Find a block device
+ *
+ * This function does not activate the device. The device will be returned
+ * whether or not it is activated.
+ *
+ * @if_type:	Interface type (enum if_type_t)
+ * @devnum:	Device number (specific to each interface type)
+ * @devp:	the device, if found
+ * @return 0 if found, -ENODEV if no device found, or other -ve error value
+ */
+int blk_find_device(int if_type, int devnum, struct udevice **devp);
+
+/**
+ * blk_get_device() - Find and probe a block device ready for use
+ *
+ * @if_type:	Interface type (enum if_type_t)
+ * @devnum:	Device number (specific to each interface type)
+ * @devp:	the device, if found
+ * @return 0 if found, -ENODEV if no device found, or other -ve error value
+ */
+int blk_get_device(int if_type, int devnum, struct udevice **devp);
+
+/**
+ * blk_first_device() - Find the first device for a given interface
+ *
+ * The device is probed ready for use
+ *
+ * @devnum:	Device number (specific to each interface type)
+ * @devp:	the device, if found
+ * @return 0 if found, -ENODEV if no device, or other -ve error value
+ */
+int blk_first_device(int if_type, struct udevice **devp);
+
+/**
+ * blk_next_device() - Find the next device for a given interface
+ *
+ * This can be called repeatedly after blk_first_device() to iterate through
+ * all devices of the given interface type.
+ *
+ * The device is probed ready for use
+ *
+ * @devp:	On entry, the previous device returned. On exit, the next
+ *		device, if found
+ * @return 0 if found, -ENODEV if no device, or other -ve error value
+ */
+int blk_next_device(struct udevice **devp);
+
+/**
+ * blk_create_device() - Create a new block device
+ *
+ * @parent:	Parent of the new device
+ * @drv_name:	Driver name to use for the block device
+ * @name:	Name for the device
+ * @if_type:	Interface type (enum if_type_t)
+ * @devnum:	Device number, specific to the interface type, or -1 to
+ *		allocate the next available number
+ * @blksz:	Block size of the device in bytes (typically 512)
+ * @lba:	Total number of blocks of the device
+ * @devp:	the new device (which has not been probed)
+ */
+int blk_create_device(struct udevice *parent, const char *drv_name,
+		      const char *name, int if_type, int devnum, int blksz,
+		      lbaint_t lba, struct udevice **devp);
+
+/**
+ * blk_create_devicef() - Create a new named block device
+ *
+ * @parent:	Parent of the new device
+ * @drv_name:	Driver name to use for the block device
+ * @name:	Name for the device (parent name is prepended)
+ * @if_type:	Interface type (enum if_type_t)
+ * @devnum:	Device number, specific to the interface type, or -1 to
+ *		allocate the next available number
+ * @blksz:	Block size of the device in bytes (typically 512)
+ * @lba:	Total number of blocks of the device
+ * @devp:	the new device (which has not been probed)
+ */
+int blk_create_devicef(struct udevice *parent, const char *drv_name,
+		       const char *name, int if_type, int devnum, int blksz,
+		       lbaint_t lba, struct udevice **devp);
+
+/**
+ * blk_unbind_all() - Unbind all device of the given interface type
+ *
+ * The devices are removed and then unbound.
+ *
+ * @if_type:	Interface type to unbind
+ * @return 0 if OK, -ve on error
+ */
+int blk_unbind_all(int if_type);
+
+/**
+ * blk_find_max_devnum() - find the maximum device number for an interface type
+ *
+ * Finds the last allocated device number for an interface type @if_type. The
+ * next number is safe to use for a newly allocated device.
+ *
+ * @if_type:	Interface type to scan
+ * @return maximum device number found, or -ENODEV if none, or other -ve on
+ * error
+ */
+int blk_find_max_devnum(enum if_type if_type);
+
+/**
+ * blk_next_free_devnum() - get the next device number for an interface type
+ *
+ * Finds the next number that is safe to use for a newly allocated device for
+ * an interface type @if_type.
+ *
+ * @if_type:	Interface type to scan
+ * @return next device number safe to use, or -ve on error
+ */
+int blk_next_free_devnum(enum if_type if_type);
+
+/**
+ * blk_select_hwpart() - select a hardware partition
+ *
+ * Select a hardware partition if the device supports it (typically MMC does)
+ *
+ * @dev:	Device to update
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_select_hwpart(struct udevice *dev, int hwpart);
+
+/**
+ * blk_get_from_parent() - obtain a block device by looking up its parent
+ *
+ * All devices with
+ */
+int blk_get_from_parent(struct udevice *parent, struct udevice **devp);
+
+/**
+ * blk_get_by_device() - Get the block device descriptor for the given device
+ * @dev:	Instance of a storage device
+ *
+ * Return: With block device descriptor on success , NULL if there is no such
+ *	   block device.
+ */
+struct blk_desc *blk_get_by_device(struct udevice *dev);
+
+#else
+#include <errno.h>
+/*
+ * These functions should take struct udevice instead of struct blk_desc,
+ * but this is convenient for migration to driver model. Add a 'd' prefix
+ * to the function operations, so that blk_read(), etc. can be reserved for
+ * functions with the correct arguments.
+ */
+static inline ulong blk_dread(struct blk_desc *block_dev, lbaint_t start,
+			      lbaint_t blkcnt, void *buffer)
+{
+	ulong blks_read;
+	if (blkcache_read(block_dev->if_type, block_dev->devnum,
+			  start, blkcnt, block_dev->blksz, buffer))
+		return blkcnt;
+
+	/*
+	 * We could check if block_read is NULL and return -ENOSYS. But this
+	 * bloats the code slightly (cause some board to fail to build), and
+	 * it would be an error to try an operation that does not exist.
+	 */
+	blks_read = block_dev->block_read(block_dev, start, blkcnt, buffer);
+	if (blks_read == blkcnt)
+		blkcache_fill(block_dev->if_type, block_dev->devnum,
+			      start, blkcnt, block_dev->blksz, buffer);
+
+	return blks_read;
+}
+
+static inline ulong blk_dwrite(struct blk_desc *block_dev, lbaint_t start,
+			       lbaint_t blkcnt, const void *buffer)
+{
+	blkcache_invalidate(block_dev->if_type, block_dev->devnum);
+	return block_dev->block_write(block_dev, start, blkcnt, buffer);
+}
+
+static inline ulong blk_derase(struct blk_desc *block_dev, lbaint_t start,
+			       lbaint_t blkcnt)
+{
+	blkcache_invalidate(block_dev->if_type, block_dev->devnum);
+	return block_dev->block_erase(block_dev, start, blkcnt);
+}
+
+/**
+ * struct blk_driver - Driver for block interface types
+ *
+ * This provides access to the block devices for each interface type. One
+ * driver should be provided using U_BOOT_LEGACY_BLK() for each interface
+ * type that is to be supported.
+ *
+ * @if_typename:	Interface type name
+ * @if_type:		Interface type
+ * @max_devs:		Maximum number of devices supported
+ * @desc:		Pointer to list of devices for this interface type,
+ *			or NULL to use @get_dev() instead
+ */
+struct blk_driver {
+	const char *if_typename;
+	enum if_type if_type;
+	int max_devs;
+	struct blk_desc *desc;
+	/**
+	 * get_dev() - get a pointer to a block device given its number
+	 *
+	 * Each interface allocates its own devices and typically
+	 * struct blk_desc is contained with the interface's data structure.
+	 * There is no global numbering for block devices. This method allows
+	 * the device for an interface type to be obtained when @desc is NULL.
+	 *
+	 * @devnum:	Device number (0 for first device on that interface,
+	 *		1 for second, etc.
+	 * @descp:	Returns pointer to the block device on success
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_dev)(int devnum, struct blk_desc **descp);
+
+	/**
+	 * select_hwpart() - Select a hardware partition
+	 *
+	 * Some devices (e.g. MMC) can support partitioning at the hardware
+	 * level. This is quite separate from the normal idea of
+	 * software-based partitions. MMC hardware partitions must be
+	 * explicitly selected. Once selected only the region of the device
+	 * covered by that partition is accessible.
+	 *
+	 * The MMC standard provides for two boot partitions (numbered 1 and 2),
+	 * rpmb (3), and up to 4 addition general-purpose partitions (4-7).
+	 * Partition 0 is the main user-data partition.
+	 *
+	 * @desc:	Block device descriptor
+	 * @hwpart:	Hardware partition number to select. 0 means the main
+	 *		user-data partition, 1 is the first partition, 2 is
+	 *		the second, etc.
+	 * @return 0 if OK, other value for an error
+	 */
+	int (*select_hwpart)(struct blk_desc *desc, int hwpart);
+};
+
+/*
+ * Declare a new U-Boot legacy block driver. New drivers should use driver
+ * model (UCLASS_BLK).
+ */
+#define U_BOOT_LEGACY_BLK(__name)					\
+	ll_entry_declare(struct blk_driver, __name, blk_driver)
+
+struct blk_driver *blk_driver_lookup_type(int if_type);
+
+#endif /* !CONFIG_BLK */
+
+/**
+ * blk_get_devnum_by_typename() - Get a block device by type and number
+ *
+ * This looks through the available block devices of the given type, returning
+ * the one with the given @devnum.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return point to block device descriptor, or NULL if not found
+ */
+struct blk_desc *blk_get_devnum_by_type(enum if_type if_type, int devnum);
+
+/**
+ * blk_get_devnum_by_type() - Get a block device by type name, and number
+ *
+ * This looks up the block device type based on @if_typename, then calls
+ * blk_get_devnum_by_type().
+ *
+ * @if_typename:	Block device type name
+ * @devnum:		Device number
+ * @return point to block device descriptor, or NULL if not found
+ */
+struct blk_desc *blk_get_devnum_by_typename(const char *if_typename,
+					    int devnum);
+
+/**
+ * blk_dselect_hwpart() - select a hardware partition
+ *
+ * This selects a hardware partition (such as is supported by MMC). The block
+ * device size may change as this effectively points the block device to a
+ * partition at the hardware level. See the select_hwpart() method above.
+ *
+ * @desc:	Block device descriptor for the device to select
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_dselect_hwpart(struct blk_desc *desc, int hwpart);
+
+/**
+ * blk_list_part() - list the partitions for block devices of a given type
+ *
+ * This looks up the partition type for each block device of type @if_type,
+ * then displays a list of partitions.
+ *
+ * @if_type:	Block device type
+ * @return 0 if OK, -ENODEV if there is none of that type
+ */
+int blk_list_part(enum if_type if_type);
+
+/**
+ * blk_list_devices() - list the block devices of a given type
+ *
+ * This lists each block device of the type @if_type, showing the capacity
+ * as well as type-specific information.
+ *
+ * @if_type:	Block device type
+ */
+void blk_list_devices(enum if_type if_type);
+
+/**
+ * blk_show_device() - show information about a given block device
+ *
+ * This shows the block device capacity as well as type-specific information.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENODEV for invalid device number
+ */
+int blk_show_device(enum if_type if_type, int devnum);
+
+/**
+ * blk_print_device_num() - show information about a given block device
+ *
+ * This is similar to blk_show_device() but returns an error if the block
+ * device type is unknown.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENODEV for invalid device number, -ENOENT if the block
+ * device is not connected
+ */
+int blk_print_device_num(enum if_type if_type, int devnum);
+
+/**
+ * blk_print_part_devnum() - print the partition information for a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @return 0 if OK, -ENOENT if the block device is not connected, -ENOSYS if
+ * the interface type is not supported, other -ve on other error
+ */
+int blk_print_part_devnum(enum if_type if_type, int devnum);
+
+/**
+ * blk_read_devnum() - read blocks from a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @blkcnt:	Number of blocks to read
+ * @buffer:	Address to write data to
+ * @return number of blocks read, or -ve error number on error
+ */
+ulong blk_read_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		      lbaint_t blkcnt, void *buffer);
+
+/**
+ * blk_write_devnum() - write blocks to a device
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @blkcnt:	Number of blocks to write
+ * @buffer:	Address to read data from
+ * @return number of blocks written, or -ve error number on error
+ */
+ulong blk_write_devnum(enum if_type if_type, int devnum, lbaint_t start,
+		       lbaint_t blkcnt, const void *buffer);
+
+/**
+ * blk_select_hwpart_devnum() - select a hardware partition
+ *
+ * This is similar to blk_dselect_hwpart() but it looks up the interface and
+ * device number.
+ *
+ * @if_type:	Block device type
+ * @devnum:	Device number
+ * @hwpart:	Partition number to select
+ * @return 0 if OK, -ve on error
+ */
+int blk_select_hwpart_devnum(enum if_type if_type, int devnum, int hwpart);
+
+/**
+ * blk_get_if_type_name() - Get the name of an interface type
+ *
+ * @if_type: Interface type to check
+ * @return name of interface, or NULL if none
+ */
+const char *blk_get_if_type_name(enum if_type if_type);
+
+/**
+ * blk_common_cmd() - handle common commands with block devices
+ *
+ * @args: Number of arguments to the command (argv[0] is the command itself)
+ * @argv: Command arguments
+ * @if_type: Interface type
+ * @cur_devnump: Current device number for this interface type
+ * @return 0 if OK, CMD_RET_ERROR on error
+ */
+int blk_common_cmd(int argc, char * const argv[], enum if_type if_type,
+		   int *cur_devnump);
+
+#endif
diff --git a/include/bloblist.h b/include/bloblist.h
new file mode 100644
index 0000000..8514401
--- /dev/null
+++ b/include/bloblist.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This provides a standard way of passing information between boot phases
+ * (TPL -> SPL -> U-Boot proper.)
+ *
+ * A list of blobs of data, tagged with their owner. The list resides in memory
+ * and can be updated by SPL, U-Boot, etc.
+ *
+ * Copyright 2018 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __BLOBLIST_H
+#define __BLOBLIST_H
+
+enum {
+	BLOBLIST_VERSION	= 0,
+	BLOBLIST_MAGIC		= 0xb00757a3,
+	BLOBLIST_ALIGN		= 16,
+};
+
+enum bloblist_tag_t {
+	BLOBLISTT_NONE = 0,
+
+	/* Vendor-specific tags are permitted here */
+	BLOBLISTT_EC_HOSTEVENT,		/* Chromium OS EC host-event mask */
+	BLOBLISTT_SPL_HANDOFF,		/* Hand-off info from SPL */
+	BLOBLISTT_VBOOT_CTX,		/* Chromium OS verified boot context */
+	BLOBLISTT_VBOOT_HANDOFF,	/* Chromium OS internal handoff info */
+};
+
+/**
+ * struct bloblist_hdr - header for the bloblist
+ *
+ * This is stored at the start of the bloblist which is always on a 16-byte
+ * boundary. Records follow this header. The bloblist normally stays in the
+ * same place in memory as SPL and U-Boot execute, but it can be safely moved
+ * around.
+ *
+ * None of the bloblist structures contain pointers but it is possible to put
+ * pointers inside a bloblist record if desired. This is not encouraged,
+ * since it can make part of the bloblist inaccessible if the pointer is
+ * no-longer valid. It is better to just store all the data inside a bloblist
+ * record.
+ *
+ * Each bloblist record is aligned to a 16-byte boundary and follows immediately
+ * from the last.
+ *
+ * @version: BLOBLIST_VERSION
+ * @hdr_size: Size of this header, normally sizeof(struct bloblist_hdr). The
+ *	first bloblist_rec starts at this offset from the start of the header
+ * @flags: Space for BLOBLISTF_... flags (none yet)
+ * @magic: BLOBLIST_MAGIC
+ * @size: Total size of all records (non-zero if valid) including this header.
+ *	The bloblist extends for this many bytes from the start of this header.
+ * @alloced: Total size allocated for this bloblist. When adding new records,
+ *	the bloblist can grow up to this size. This starts out as
+ *	sizeof(bloblist_hdr) since we need at least that much space to store a
+ *	valid bloblist
+ * @spare: Space space
+ * @chksum: CRC32 for the entire bloblist allocated area. Since any of the
+ *	blobs can be altered after being created, this checksum is only valid
+ *	when the bloblist is finalised before jumping to the next stage of boot.
+ *	Note: @chksum is last to make it easier to exclude it from the checksum
+ *	calculation.
+ */
+struct bloblist_hdr {
+	u32 version;
+	u32 hdr_size;
+	u32 flags;
+	u32 magic;
+
+	u32 size;
+	u32 alloced;
+	u32 spare;
+	u32 chksum;
+};
+
+/**
+ * struct bloblist_rec - record for the bloblist
+ *
+ * NOTE: Only exported for testing purposes. Do not use this struct.
+ *
+ * The bloblist contains a number of records each consisting of this record
+ * structure followed by the data contained. Each records is 16-byte aligned.
+ *
+ * @tag: Tag indicating what the record contains
+ * @hdr_size: Size of this header, normally sizeof(struct bloblist_rec). The
+ *	record's data starts at this offset from the start of the record
+ * @size: Size of record in bytes, excluding the header size. This does not
+ *	need to be aligned (e.g. 3 is OK).
+ * @spare: Spare space for other things
+ */
+struct bloblist_rec {
+	u32 tag;
+	u32 hdr_size;
+	u32 size;
+	u32 spare;
+};
+
+/**
+ * bloblist_find() - Find a blob
+ *
+ * Searches the bloblist and returns the blob with the matching tag
+ *
+ * @tag:	Tag to search for (enum bloblist_tag_t)
+ * @size:	Expected size of the blob
+ * @return pointer to blob if found, or NULL if not found, or a blob was found
+ *	but it is the wrong size
+ */
+void *bloblist_find(uint tag, int size);
+
+/**
+ * bloblist_add() - Add a new blob
+ *
+ * Add a new blob to the bloblist
+ *
+ * This should only be called if you konw there is no existing blob for a
+ * particular tag. It is typically safe to call in the first phase of U-Boot
+ * (e.g. TPL or SPL). After that, bloblist_ensure() should be used instead.
+ *
+ * @tag:	Tag to add (enum bloblist_tag_t)
+ * @size:	Size of the blob
+ * @return pointer to the newly added block, or NULL if there is not enough
+ *	space for the blob
+ */
+void *bloblist_add(uint tag, int size);
+
+/**
+ * bloblist_ensure_size() - Find or add a blob
+ *
+ * Find an existing blob, or add a new one if not found
+ *
+ * @tag:	Tag to add (enum bloblist_tag_t)
+ * @size:	Size of the blob
+ * @blobp:	Returns a pointer to blob on success
+ * @return 0 if OK, -ENOSPC if it is missing and could not be added due to lack
+ *	of space, or -ESPIPE it exists but has the wrong size
+ */
+int bloblist_ensure_size(uint tag, int size, void **blobp);
+
+/**
+ * bloblist_ensure() - Find or add a blob
+ *
+ * Find an existing blob, or add a new one if not found
+ *
+ * @tag:	Tag to add (enum bloblist_tag_t)
+ * @size:	Size of the blob
+ * @return pointer to blob, or NULL if it is missing and could not be added due
+ *	to lack of space, or it exists but has the wrong size
+ */
+void *bloblist_ensure(uint tag, int size);
+
+/**
+ * bloblist_new() - Create a new, empty bloblist of a given size
+ *
+ * @addr: Address of bloblist
+ * @size: Initial size for bloblist
+ * @flags: Flags to use for bloblist
+ * @return 0 if OK, -EFAULT if addr is not aligned correctly, -ENOSPC is the
+ *	area is not large enough
+ */
+int bloblist_new(ulong addr, uint size, uint flags);
+
+/**
+ * bloblist_check() - Check if a bloblist exists
+ *
+ * @addr: Address of bloblist
+ * @size: Expected size of blobsize, or 0 to detect the size
+ * @return 0 if OK, -ENOENT if the magic number doesn't match (indicating that
+ *	there problem is no bloblist at the given address), -EPROTONOSUPPORT
+ *	if the version does not match, -EIO if the checksum does not match,
+ *	-EFBIG if the expected size does not match the detected size
+ */
+int bloblist_check(ulong addr, uint size);
+
+/**
+ * bloblist_finish() - Set up the bloblist for the next U-Boot part
+ *
+ * This sets the correct checksum for the bloblist. This ensures that the
+ * bloblist will be detected correctly by the next phase of U-Boot.
+ *
+ * @return 0
+ */
+int bloblist_finish(void);
+
+/**
+ * bloblist_init() - Init the bloblist system with a single bloblist
+ *
+ * This uses CONFIG_BLOBLIST_ADDR and CONFIG_BLOBLIST_SIZE to set up a bloblist
+ * for use by U-Boot.
+ */
+int bloblist_init(void);
+
+#endif /* __BLOBLIST_H */
diff --git a/include/bmp_layout.h b/include/bmp_layout.h
new file mode 100644
index 0000000..a5c9498
--- /dev/null
+++ b/include/bmp_layout.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* (C) Copyright 2002
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ */
+
+/************************************************************************/
+/* ** Layout of a bmp file						*/
+/************************************************************************/
+
+#ifndef _BMP_H_
+#define _BMP_H_
+
+struct __packed bmp_color_table_entry {
+	__u8	blue;
+	__u8	green;
+	__u8	red;
+	__u8	reserved;
+};
+
+/* When accessing these fields, remember that they are stored in little
+   endian format, so use linux macros, e.g. le32_to_cpu(width)          */
+
+struct __packed bmp_header {
+	/* Header */
+	char signature[2];
+	__u32	file_size;
+	__u32	reserved;
+	__u32	data_offset;
+	/* InfoHeader */
+	__u32	size;
+	__u32	width;
+	__u32	height;
+	__u16	planes;
+	__u16	bit_count;
+	__u32	compression;
+	__u32	image_size;
+	__u32	x_pixels_per_m;
+	__u32	y_pixels_per_m;
+	__u32	colors_used;
+	__u32	colors_important;
+	/* ColorTable */
+};
+
+struct bmp_image {
+	struct bmp_header header;
+	/* We use a zero sized array just as a placeholder for variable
+	   sized array */
+	struct bmp_color_table_entry color_table[0];
+};
+
+/* Data in the bmp_image is aligned to this length */
+#define BMP_DATA_ALIGN	4
+
+/* Constants for the compression field */
+#define BMP_BI_RGB	0
+#define BMP_BI_RLE8	1
+#define BMP_BI_RLE4	2
+
+#endif							/* _BMP_H_ */
diff --git a/include/board.h b/include/board.h
new file mode 100644
index 0000000..9dc7868
--- /dev/null
+++ b/include/board.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017
+ * Mario Six,  Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+/*
+ * This uclass encapsulates hardware methods to gather information about a
+ * board or a specific device such as hard-wired GPIOs on GPIO expanders,
+ * read-only data in flash ICs, or similar.
+ *
+ * The interface offers functions to read the usual standard data types (bool,
+ * int, string) from the device, each of which is identified by a static
+ * numeric ID (which will usually be defined as a enum in a header file).
+ *
+ * If for example the board had a read-only serial number flash IC, we could
+ * call
+ *
+ * ret = board_detect(dev);
+ * if (ret) {
+ *	debug("board device not found.");
+ *	return ret;
+ * }
+ *
+ * ret = board_get_int(dev, ID_SERIAL_NUMBER, &serial);
+ * if (ret) {
+ *	debug("Error when reading serial number from device.");
+ *	return ret;
+ * }
+ *
+ * to read the serial number.
+ */
+
+struct board_ops {
+	/**
+	 * detect() - Run the hardware info detection procedure for this
+	 *	      device.
+	 * @dev:      The device containing the information
+	 *
+	 * This operation might take a long time (e.g. read from EEPROM,
+	 * check the presence of a device on a bus etc.), hence this is not
+	 * done in the probe() method, but later during operation in this
+	 * dedicated method.
+	 *
+	 * Return: 0 if OK, -ve on error.
+	 */
+	int (*detect)(struct udevice *dev);
+
+	/**
+	 * get_bool() - Read a specific bool data value that describes the
+	 *		hardware setup.
+	 * @dev:	The board instance to gather the data.
+	 * @id:		A unique identifier for the bool value to be read.
+	 * @val:	Pointer to a buffer that receives the value read.
+	 *
+	 * Return: 0 if OK, -ve on error.
+	 */
+	int (*get_bool)(struct udevice *dev, int id, bool *val);
+
+	/**
+	 * get_int() - Read a specific int data value that describes the
+	 *	       hardware setup.
+	 * @dev:       The board instance to gather the data.
+	 * @id:        A unique identifier for the int value to be read.
+	 * @val:       Pointer to a buffer that receives the value read.
+	 *
+	 * Return: 0 if OK, -ve on error.
+	 */
+	int (*get_int)(struct udevice *dev, int id, int *val);
+
+	/**
+	 * get_str() - Read a specific string data value that describes the
+	 *	       hardware setup.
+	 * @dev:	The board instance to gather the data.
+	 * @id:		A unique identifier for the string value to be read.
+	 * @size:	The size of the buffer to receive the string data.
+	 * @val:	Pointer to a buffer that receives the value read.
+	 *
+	 * Return: 0 if OK, -ve on error.
+	 */
+	int (*get_str)(struct udevice *dev, int id, size_t size, char *val);
+};
+
+#define board_get_ops(dev)	((struct board_ops *)(dev)->driver->ops)
+
+/**
+ * board_detect() - Run the hardware info detection procedure for this device.
+ *
+ * @dev:	The device containing the information
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int board_detect(struct udevice *dev);
+
+/**
+ * board_get_bool() - Read a specific bool data value that describes the
+ *		      hardware setup.
+ * @dev:	The board instance to gather the data.
+ * @id:		A unique identifier for the bool value to be read.
+ * @val:	Pointer to a buffer that receives the value read.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int board_get_bool(struct udevice *dev, int id, bool *val);
+
+/**
+ * board_get_int() - Read a specific int data value that describes the
+ *		     hardware setup.
+ * @dev:	The board instance to gather the data.
+ * @id:		A unique identifier for the int value to be read.
+ * @val:	Pointer to a buffer that receives the value read.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int board_get_int(struct udevice *dev, int id, int *val);
+
+/**
+ * board_get_str() - Read a specific string data value that describes the
+ *		     hardware setup.
+ * @dev:	The board instance to gather the data.
+ * @id:		A unique identifier for the string value to be read.
+ * @size:	The size of the buffer to receive the string data.
+ * @val:	Pointer to a buffer that receives the value read.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int board_get_str(struct udevice *dev, int id, size_t size, char *val);
+
+/**
+ * board_get() - Return the board device for the board in question.
+ * @devp: Pointer to structure to receive the board device.
+ *
+ * Since there can only be at most one board instance, the API can supply a
+ * function that returns the unique device. This is especially useful for use
+ * in board files.
+ *
+ * Return: 0 if OK, -ve on error.
+ */
+int board_get(struct udevice **devp);
diff --git a/include/boot_fit.h b/include/boot_fit.h
new file mode 100644
index 0000000..f75fed6
--- /dev/null
+++ b/include/boot_fit.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Texas Instruments
+ * Written by Franklin Cooper Jr. <fcooper@ti.com>
+ */
+
+/**
+ * locate_dtb_in_fit - Find a DTB matching the board in a FIT image
+ * @fit:	pointer to the FIT image
+ *
+ * @return a pointer to a matching DTB blob if found, NULL otherwise
+ */
+void *locate_dtb_in_fit(const void *fit);
diff --git a/include/bootcount.h b/include/bootcount.h
new file mode 100644
index 0000000..8fa8cf8
--- /dev/null
+++ b/include/bootcount.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ */
+#ifndef _BOOTCOUNT_H__
+#define _BOOTCOUNT_H__
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <env.h>
+
+#ifdef CONFIG_DM_BOOTCOUNT
+
+struct bootcount_ops {
+	/**
+	 * get() - get the current bootcount value
+	 *
+	 * Returns the current counter value of the bootcount backing
+	 * store.
+	 *
+	 * @dev:	Device to read from
+	 * @bootcount:	Address to put the current bootcount value
+	 */
+	int (*get)(struct udevice *dev, u32 *bootcount);
+
+	/**
+	 * set() - set a bootcount value (e.g. to reset or increment)
+	 *
+	 * Sets the value in the bootcount backing store.
+	 *
+	 * @dev:	Device to read from
+	 * @bootcount:	New bootcount value to store
+	 */
+	int (*set)(struct udevice *dev, const u32 bootcount);
+};
+
+/* Access the operations for a bootcount device */
+#define bootcount_get_ops(dev)	((struct bootcount_ops *)(dev)->driver->ops)
+
+/**
+ * dm_bootcount_get() - Read the current value from a bootcount storage
+ *
+ * @dev:	Device to read from
+ * @bootcount:	Place to put the current bootcount
+ * @return 0 if OK, -ve on error
+ */
+int dm_bootcount_get(struct udevice *dev, u32 *bootcount);
+
+/**
+ * dm_bootcount_set() - Write a value to a bootcount storage
+ *
+ * @dev:	Device to read from
+ * @bootcount:  Value to be written to the backing storage
+ * @return 0 if OK, -ve on error
+ */
+int dm_bootcount_set(struct udevice *dev, u32 bootcount);
+
+#endif
+
+#if defined(CONFIG_SPL_BOOTCOUNT_LIMIT) || defined(CONFIG_BOOTCOUNT_LIMIT)
+
+#if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE)
+# if __BYTE_ORDER == __LITTLE_ENDIAN
+#  define CONFIG_SYS_BOOTCOUNT_LE
+# else
+#  define CONFIG_SYS_BOOTCOUNT_BE
+# endif
+#endif
+
+#ifdef CONFIG_SYS_BOOTCOUNT_LE
+static inline void raw_bootcount_store(volatile u32 *addr, u32 data)
+{
+	out_le32(addr, data);
+}
+
+static inline u32 raw_bootcount_load(volatile u32 *addr)
+{
+	return in_le32(addr);
+}
+#else
+static inline void raw_bootcount_store(volatile u32 *addr, u32 data)
+{
+	out_be32(addr, data);
+}
+
+static inline u32 raw_bootcount_load(volatile u32 *addr)
+{
+	return in_be32(addr);
+}
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+static inline int bootcount_error(void)
+{
+	unsigned long bootcount = bootcount_load();
+	unsigned long bootlimit = env_get_ulong("bootlimit", 10, 0);
+
+	if (bootlimit && bootcount > bootlimit) {
+		printf("Warning: Bootlimit (%lu) exceeded.", bootlimit);
+		if (!(gd->flags & GD_FLG_SPL_INIT))
+			printf(" Using altbootcmd.");
+		printf("\n");
+
+		return 1;
+	}
+
+	return 0;
+}
+
+static inline void bootcount_inc(void)
+{
+	unsigned long bootcount = bootcount_load();
+
+	if (gd->flags & GD_FLG_SPL_INIT) {
+		bootcount_store(++bootcount);
+		return;
+	}
+
+#ifndef CONFIG_SPL_BUILD
+	/* Only increment bootcount when no bootcount support in SPL */
+#ifndef CONFIG_SPL_BOOTCOUNT_LIMIT
+	bootcount_store(++bootcount);
+#endif
+	env_set_ulong("bootcount", bootcount);
+#endif /* !CONFIG_SPL_BUILD */
+}
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_BOOTCOUNT_LIMIT)
+void bootcount_store(ulong a) {};
+ulong bootcount_load(void) { return 0; }
+#endif /* CONFIG_SPL_BUILD && !CONFIG_SPL_BOOTCOUNT_LIMIT */
+#else
+static inline int bootcount_error(void) { return 0; }
+static inline void bootcount_inc(void) {}
+#endif /* CONFIG_SPL_BOOTCOUNT_LIMIT || CONFIG_BOOTCOUNT_LIMIT */
+#endif /* _BOOTCOUNT_H__ */
diff --git a/include/bootm.h b/include/bootm.h
new file mode 100644
index 0000000..edeeacb
--- /dev/null
+++ b/include/bootm.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef _BOOTM_H
+#define _BOOTM_H
+
+#include <command.h>
+#include <image.h>
+
+#define BOOTM_ERR_RESET		(-1)
+#define BOOTM_ERR_OVERLAP		(-2)
+#define BOOTM_ERR_UNIMPLEMENTED	(-3)
+
+/*
+ *  Continue booting an OS image; caller already has:
+ *  - copied image header to global variable `header'
+ *  - checked header magic number, checksums (both header & image),
+ *  - verified image architecture (PPC) and type (KERNEL or MULTI),
+ *  - loaded (first part of) image to header load address,
+ *  - disabled interrupts.
+ *
+ * @flag: Flags indicating what to do (BOOTM_STATE_...)
+ * @argc: Number of arguments. Note that the arguments are shifted down
+ *	 so that 0 is the first argument not processed by U-Boot, and
+ *	 argc is adjusted accordingly. This avoids confusion as to how
+ *	 many arguments are available for the OS.
+ * @images: Pointers to os/initrd/fdt
+ * @return 1 on error. On success the OS boots so this function does
+ * not return.
+ */
+typedef int boot_os_fn(int flag, int argc, char * const argv[],
+			bootm_headers_t *images);
+
+extern boot_os_fn do_bootm_linux;
+extern boot_os_fn do_bootm_vxworks;
+
+int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void lynxkdi_boot(image_header_t *hdr);
+
+boot_os_fn *bootm_os_get_boot_func(int os);
+
+#if defined(CONFIG_FIT_SIGNATURE)
+int bootm_host_load_images(const void *fit, int cfg_noffset);
+#endif
+
+int boot_selected_os(int argc, char * const argv[], int state,
+		     bootm_headers_t *images, boot_os_fn *boot_fn);
+
+ulong bootm_disable_interrupts(void);
+
+/* This is a special function used by booti/bootz */
+int bootm_find_images(int flag, int argc, char * const argv[]);
+
+int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		    int states, bootm_headers_t *images, int boot_progress);
+
+void arch_preboot_os(void);
+
+/*
+ * boards should define this to disable devices when EFI exits from boot
+ * services.
+ *
+ * TODO(sjg@chromium.org>): Update this to use driver model's device_remove().
+ */
+void board_quiesce_devices(void);
+
+/**
+ * switch_to_non_secure_mode() - switch to non-secure mode
+ */
+void switch_to_non_secure_mode(void);
+
+#endif
diff --git a/include/bootretry.h b/include/bootretry.h
new file mode 100644
index 0000000..0cedd30
--- /dev/null
+++ b/include/bootretry.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __BOOTRETRY_H
+#define __BOOTRETRY_H
+
+#ifdef CONFIG_BOOT_RETRY_TIME
+/**
+ * bootretry_tstc_timeout() - ensure we get a keypress before timeout
+ *
+ * Check for a keypress repeatedly, resetting the watchdog each time. If a
+ * keypress is not received within the command timeout, return an error.
+ *
+ * @return 0 if a key is received in time, -ETIMEDOUT if not
+ */
+int bootretry_tstc_timeout(void);
+
+/**
+ * bootretry_init_cmd_timeout() - set up command timeout
+ *
+ * Get the required command timeout from the environment.
+ */
+void bootretry_init_cmd_timeout(void);
+
+/**
+ * bootretry_reset_cmd_timeout() - reset command timeout
+ *
+ * Reset the command timeout so that the user has a fresh start. This is
+ * typically used when input is received from the user.
+ */
+void bootretry_reset_cmd_timeout(void);
+
+/** bootretry_dont_retry() - Indicate that we should not retry the boot */
+void bootretry_dont_retry(void);
+#else
+static inline int bootretry_tstc_timeout(void)
+{
+	return 0;
+}
+
+static inline void bootretry_init_cmd_timeout(void)
+{
+}
+
+static inline void bootretry_reset_cmd_timeout(void)
+{
+}
+
+static inline void bootretry_dont_retry(void)
+{
+}
+
+#endif
+
+#endif
diff --git a/include/bootstage.h b/include/bootstage.h
new file mode 100644
index 0000000..5e7e242
--- /dev/null
+++ b/include/bootstage.h
@@ -0,0 +1,433 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This file implements recording of each stage of the boot process. It is
+ * intended to implement timing of each stage, reporting this information
+ * to the user and passing it to the OS for logging / further analysis.
+ * Note that it requires timer_get_boot_us() to be defined by the board
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef _BOOTSTAGE_H
+#define _BOOTSTAGE_H
+
+/* Flags for each bootstage record */
+enum bootstage_flags {
+	BOOTSTAGEF_ERROR	= 1 << 0,	/* Error record */
+	BOOTSTAGEF_ALLOC	= 1 << 1,	/* Allocate an id */
+};
+
+/* bootstate sub-IDs used for kernel and ramdisk ranges */
+enum {
+	BOOTSTAGE_SUB_FORMAT,
+	BOOTSTAGE_SUB_FORMAT_OK,
+	BOOTSTAGE_SUB_NO_UNIT_NAME,
+	BOOTSTAGE_SUB_UNIT_NAME,
+	BOOTSTAGE_SUB_SUBNODE,
+
+	BOOTSTAGE_SUB_CHECK,
+	BOOTSTAGE_SUB_HASH = 5,
+	BOOTSTAGE_SUB_CHECK_ARCH = 5,
+	BOOTSTAGE_SUB_CHECK_ALL,
+	BOOTSTAGE_SUB_GET_DATA,
+	BOOTSTAGE_SUB_CHECK_ALL_OK = 7,
+	BOOTSTAGE_SUB_GET_DATA_OK,
+	BOOTSTAGE_SUB_LOAD,
+};
+
+/*
+ * A list of boot stages that we know about. Each of these indicates the
+ * state that we are at, and the action that we are about to perform. For
+ * errors, we issue an error for an item when it fails. Therefore the
+ * normal sequence is:
+ *
+ * progress action1
+ * progress action2
+ * progress action3
+ *
+ * and an error condition where action 3 failed would be:
+ *
+ * progress action1
+ * progress action2
+ * progress action3
+ * error on action3
+ */
+enum bootstage_id {
+	BOOTSTAGE_ID_START = 0,
+	BOOTSTAGE_ID_CHECK_MAGIC,	/* Checking image magic */
+	BOOTSTAGE_ID_CHECK_HEADER,	/* Checking image header */
+	BOOTSTAGE_ID_CHECK_CHECKSUM,	/* Checking image checksum */
+	BOOTSTAGE_ID_CHECK_ARCH,	/* Checking architecture */
+
+	BOOTSTAGE_ID_CHECK_IMAGETYPE = 5,/* Checking image type */
+	BOOTSTAGE_ID_DECOMP_IMAGE,	/* Decompressing image */
+	BOOTSTAGE_ID_KERNEL_LOADED,	/* Kernel has been loaded */
+	BOOTSTAGE_ID_DECOMP_UNIMPL = 7,	/* Odd decompression algorithm */
+	BOOTSTAGE_ID_CHECK_BOOT_OS,	/* Calling OS-specific boot function */
+	BOOTSTAGE_ID_BOOT_OS_RETURNED,	/* Tried to boot OS, but it returned */
+	BOOTSTAGE_ID_CHECK_RAMDISK = 9,	/* Checking ram disk */
+
+	BOOTSTAGE_ID_RD_MAGIC,		/* Checking ram disk magic */
+	BOOTSTAGE_ID_RD_HDR_CHECKSUM,	/* Checking ram disk heder checksum */
+	BOOTSTAGE_ID_RD_CHECKSUM,	/* Checking ram disk checksum */
+	BOOTSTAGE_ID_COPY_RAMDISK = 12,	/* Copying ram disk into place */
+	BOOTSTAGE_ID_RAMDISK,		/* Checking for valid ramdisk */
+	BOOTSTAGE_ID_NO_RAMDISK,	/* No ram disk found (not an error) */
+
+	BOOTSTAGE_ID_RUN_OS	= 15,	/* Exiting U-Boot, entering OS */
+
+	BOOTSTAGE_ID_NEED_RESET = 30,
+	BOOTSTAGE_ID_POST_FAIL,		/* Post failure */
+	BOOTSTAGE_ID_POST_FAIL_R,	/* Post failure reported after reloc */
+
+	/*
+	 * This set is reported only by x86, and the meaning is different. In
+	 * this case we are reporting completion of a particular stage.
+	 * This should probably change in the x86 code (which doesn't report
+	 * errors in any case), but discussion this can perhaps wait until we
+	 * have a generic board implementation.
+	 */
+	BOOTSTAGE_ID_BOARD_INIT_R,	/* We have relocated */
+	BOOTSTAGE_ID_BOARD_GLOBAL_DATA,	/* Global data is set up */
+
+	BOOTSTAGE_ID_BOARD_INIT_SEQ,	/* We completed the init sequence */
+	BOOTSTAGE_ID_BOARD_FLASH,	/* We have configured flash banks */
+	BOOTSTAGE_ID_BOARD_FLASH_37,	/* In case you didn't hear... */
+	BOOTSTAGE_ID_BOARD_ENV,		/* Environment is relocated & ready */
+	BOOTSTAGE_ID_BOARD_PCI,		/* PCI is up */
+
+	BOOTSTAGE_ID_BOARD_INTERRUPTS,	/* Exceptions / interrupts ready */
+	BOOTSTAGE_ID_BOARD_DONE,	/* Board init done, off to main loop */
+	/* ^^^ here ends the x86 sequence */
+
+	/* Boot stages related to loading a kernel from an IDE device */
+	BOOTSTAGE_ID_IDE_START = 41,
+	BOOTSTAGE_ID_IDE_ADDR,
+	BOOTSTAGE_ID_IDE_BOOT_DEVICE,
+	BOOTSTAGE_ID_IDE_TYPE,
+
+	BOOTSTAGE_ID_IDE_PART,
+	BOOTSTAGE_ID_IDE_PART_INFO,
+	BOOTSTAGE_ID_IDE_PART_TYPE,
+	BOOTSTAGE_ID_IDE_PART_READ,
+	BOOTSTAGE_ID_IDE_FORMAT,
+
+	BOOTSTAGE_ID_IDE_CHECKSUM,	/* 50 */
+	BOOTSTAGE_ID_IDE_READ,
+
+	/* Boot stages related to loading a kernel from an NAND device */
+	BOOTSTAGE_ID_NAND_PART,
+	BOOTSTAGE_ID_NAND_SUFFIX,
+	BOOTSTAGE_ID_NAND_BOOT_DEVICE,
+	BOOTSTAGE_ID_NAND_HDR_READ = 55,
+	BOOTSTAGE_ID_NAND_AVAILABLE = 55,
+	BOOTSTAGE_ID_NAND_TYPE = 57,
+	BOOTSTAGE_ID_NAND_READ,
+
+	/* Boot stages related to loading a kernel from an network device */
+	BOOTSTAGE_ID_NET_CHECKSUM = 60,
+	BOOTSTAGE_ID_NET_ETH_START = 64,
+	BOOTSTAGE_ID_NET_ETH_INIT,
+
+	BOOTSTAGE_ID_NET_START = 80,
+	BOOTSTAGE_ID_NET_NETLOOP_OK,
+	BOOTSTAGE_ID_NET_LOADED,
+	BOOTSTAGE_ID_NET_DONE_ERR,
+	BOOTSTAGE_ID_NET_DONE,
+
+	BOOTSTAGE_ID_FIT_FDT_START = 90,
+	/*
+	 * Boot stages related to loading a FIT image. Some of these are a
+	 * bit wonky.
+	 */
+	BOOTSTAGE_ID_FIT_KERNEL_START = 100,
+
+	BOOTSTAGE_ID_FIT_CONFIG = 110,
+	BOOTSTAGE_ID_FIT_TYPE,
+	BOOTSTAGE_ID_FIT_KERNEL_INFO,
+
+	BOOTSTAGE_ID_FIT_COMPRESSION,
+	BOOTSTAGE_ID_FIT_OS,
+	BOOTSTAGE_ID_FIT_LOADADDR,
+	BOOTSTAGE_ID_OVERWRITTEN,
+
+	/* Next 10 IDs used by BOOTSTAGE_SUB_... */
+	BOOTSTAGE_ID_FIT_RD_START = 120,	/* Ramdisk stages */
+
+	/* Next 10 IDs used by BOOTSTAGE_SUB_... */
+	BOOTSTAGE_ID_FIT_SETUP_START = 130,	/* x86 setup stages */
+
+	BOOTSTAGE_ID_IDE_FIT_READ = 140,
+	BOOTSTAGE_ID_IDE_FIT_READ_OK,
+
+	BOOTSTAGE_ID_NAND_FIT_READ = 150,
+	BOOTSTAGE_ID_NAND_FIT_READ_OK,
+
+	BOOTSTAGE_ID_FIT_LOADABLE_START = 160,	/* for Loadable Images */
+	/*
+	 * These boot stages are new, higher level, and not directly related
+	 * to the old boot progress numbers. They are useful for recording
+	 * rough boot timing information.
+	 */
+	BOOTSTAGE_ID_AWAKE,
+	BOOTSTAGE_ID_START_SPL,
+	BOOTSTAGE_ID_END_SPL,
+	BOOTSTAGE_ID_START_UBOOT_F,
+	BOOTSTAGE_ID_START_UBOOT_R,
+	BOOTSTAGE_ID_USB_START,
+	BOOTSTAGE_ID_ETH_START,
+	BOOTSTAGE_ID_BOOTP_START,
+	BOOTSTAGE_ID_BOOTP_STOP,
+	BOOTSTAGE_ID_BOOTM_START,
+	BOOTSTAGE_ID_BOOTM_HANDOFF,
+	BOOTSTAGE_ID_MAIN_LOOP,
+	BOOTSTAGE_ID_ENTER_CLI_LOOP,
+	BOOTSTAGE_KERNELREAD_START,
+	BOOTSTAGE_KERNELREAD_STOP,
+	BOOTSTAGE_ID_BOARD_INIT,
+	BOOTSTAGE_ID_BOARD_INIT_DONE,
+
+	BOOTSTAGE_ID_CPU_AWAKE,
+	BOOTSTAGE_ID_MAIN_CPU_AWAKE,
+	BOOTSTAGE_ID_MAIN_CPU_READY,
+
+	BOOTSTAGE_ID_ACCUM_LCD,
+	BOOTSTAGE_ID_ACCUM_SCSI,
+	BOOTSTAGE_ID_ACCUM_SPI,
+	BOOTSTAGE_ID_ACCUM_DECOMP,
+	BOOTSTAGE_ID_ACCUM_OF_LIVE,
+	BOOTSTAGE_ID_FPGA_INIT,
+	BOOTSTATE_ID_ACCUM_DM_SPL,
+	BOOTSTATE_ID_ACCUM_DM_F,
+	BOOTSTATE_ID_ACCUM_DM_R,
+
+	/* a few spare for the user, from here */
+	BOOTSTAGE_ID_USER,
+	BOOTSTAGE_ID_ALLOC,
+};
+
+/*
+ * Return the time since boot in microseconds, This is needed for bootstage
+ * and should be defined in CPU- or board-specific code. If undefined then
+ * you will get a link error.
+ */
+ulong timer_get_boot_us(void);
+
+#if defined(USE_HOSTCC)
+#define show_boot_progress(val) do {} while (0)
+#else
+/**
+ * Board code can implement show_boot_progress() if needed.
+ *
+ * @param val	Progress state (enum bootstage_id), or -id if an error
+ *		has occurred.
+ */
+void show_boot_progress(int val);
+#endif
+
+#if !defined(USE_HOSTCC)
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
+#define ENABLE_BOOTSTAGE
+#endif
+#endif
+
+#ifdef ENABLE_BOOTSTAGE
+
+/* This is the full bootstage implementation */
+
+/**
+ * Relocate existing bootstage records
+ *
+ * Call this after relocation has happened and after malloc has been initted.
+ * We need to copy any pointers in bootstage records that were added pre-
+ * relocation, since memory can be overwritten later.
+ * @return Always returns 0, to indicate success
+ */
+int bootstage_relocate(void);
+
+/**
+ * Add a new bootstage record
+ *
+ * @param id	Bootstage ID to use (ignored if flags & BOOTSTAGEF_ALLOC)
+ * @param name	Name of record, or NULL for none
+ * @param flags	Flags (BOOTSTAGEF_...)
+ * @param mark	Time to record in this record, in microseconds
+ */
+ulong bootstage_add_record(enum bootstage_id id, const char *name,
+			   int flags, ulong mark);
+
+/**
+ * Mark a time stamp for the current boot stage.
+ */
+ulong bootstage_mark(enum bootstage_id id);
+
+ulong bootstage_error(enum bootstage_id id);
+
+ulong bootstage_mark_name(enum bootstage_id id, const char *name);
+
+/**
+ * Mark a time stamp in the given function and line number
+ *
+ * See BOOTSTAGE_MARKER() for a convenient macro.
+ *
+ * @param file		Filename to record (NULL if none)
+ * @param func		Function name to record
+ * @param linenum	Line number to record
+ * @return recorded time stamp
+ */
+ulong bootstage_mark_code(const char *file, const char *func,
+			  int linenum);
+
+/**
+ * Mark the start of a bootstage activity. The end will be marked later with
+ * bootstage_accum() and at that point we accumulate the time taken. Calling
+ * this function turns the given id into a accumulator rather than and
+ * absolute mark in time. Accumulators record the total amount of time spent
+ * in an activty during boot.
+ *
+ * @param id	Bootstage id to record this timestamp against
+ * @param name	Textual name to display for this id in the report (maybe NULL)
+ * @return start timestamp in microseconds
+ */
+uint32_t bootstage_start(enum bootstage_id id, const char *name);
+
+/**
+ * Mark the end of a bootstage activity
+ *
+ * After previously marking the start of an activity with bootstage_start(),
+ * call this function to mark the end. You can call these functions in pairs
+ * as many times as you like.
+ *
+ * @param id	Bootstage id to record this timestamp against
+ * @return time spent in this iteration of the activity (i.e. the time now
+ *		less the start time recorded in the last bootstage_start() call
+ *		with this id.
+ */
+uint32_t bootstage_accum(enum bootstage_id id);
+
+/* Print a report about boot time */
+void bootstage_report(void);
+
+/**
+ * Add bootstage information to the device tree
+ *
+ * @return 0 if ok, -ve on error
+ */
+int bootstage_fdt_add_report(void);
+
+/**
+ * Stash bootstage data into memory
+ *
+ * @param base	Base address of memory buffer
+ * @param size	Size of memory buffer
+ * @return 0 if stashed ok, -1 if out of space
+ */
+int bootstage_stash(void *base, int size);
+
+/**
+ * Read bootstage data from memory
+ *
+ * Bootstage data is read from memory and placed in the bootstage table
+ * in the user records.
+ *
+ * @param base	Base address of memory buffer
+ * @param size	Size of memory buffer (-1 if unknown)
+ * @return 0 if unstashed ok, -ENOENT if bootstage info not found, -ENOSPC if
+ *	there is not space for read the stacked data, or other error if
+ *	something else went wrong
+ */
+int bootstage_unstash(const void *base, int size);
+
+/**
+ * bootstage_get_size() - Get the size of the bootstage data
+ *
+ * @return size of boostage data in bytes
+ */
+int bootstage_get_size(void);
+
+/**
+ * bootstage_init() - Prepare bootstage for use
+ *
+ * @first: true if this is the first time bootstage is set up. This causes it
+ *	to add a 'reset' record with a time of 0.
+ */
+int bootstage_init(bool first);
+
+#else
+static inline ulong bootstage_add_record(enum bootstage_id id,
+		const char *name, int flags, ulong mark)
+{
+	return 0;
+}
+
+/*
+ * This is a dummy implementation which just calls show_boot_progress(),
+ * and won't even do that unless CONFIG_SHOW_BOOT_PROGRESS is defined
+ */
+
+static inline int bootstage_relocate(void)
+{
+	return 0;
+}
+
+static inline ulong bootstage_mark(enum bootstage_id id)
+{
+	show_boot_progress(id);
+	return 0;
+}
+
+static inline ulong bootstage_error(enum bootstage_id id)
+{
+	show_boot_progress(-id);
+	return 0;
+}
+
+static inline ulong bootstage_mark_name(enum bootstage_id id, const char *name)
+{
+	show_boot_progress(id);
+	return 0;
+}
+
+static inline ulong bootstage_mark_code(const char *file, const char *func,
+					int linenum)
+{
+	return 0;
+}
+
+static inline uint32_t bootstage_start(enum bootstage_id id, const char *name)
+{
+	return 0;
+}
+
+static inline uint32_t bootstage_accum(enum bootstage_id id)
+{
+	return 0;
+}
+
+static inline int bootstage_stash(void *base, int size)
+{
+	return 0;	/* Pretend to succeed */
+}
+
+static inline int bootstage_unstash(const void *base, int size)
+{
+	return 0;	/* Pretend to succeed */
+}
+
+static inline int bootstage_get_size(void)
+{
+	return 0;
+}
+
+static inline int bootstage_init(bool first)
+{
+	return 0;
+}
+
+#endif /* ENABLE_BOOTSTAGE */
+
+/* Helper macro for adding a bootstage to a line of code */
+#define BOOTSTAGE_MARKER()	\
+		bootstage_mark_code(__FILE__, __func__, __LINE__)
+
+#endif
diff --git a/include/bouncebuf.h b/include/bouncebuf.h
new file mode 100644
index 0000000..fd9b0f3
--- /dev/null
+++ b/include/bouncebuf.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Generic bounce buffer implementation
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __INCLUDE_BOUNCEBUF_H__
+#define __INCLUDE_BOUNCEBUF_H__
+
+#include <linux/types.h>
+
+/*
+ * GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware.
+ * The source buffer is copied into the bounce buffer (if unaligned, otherwise
+ * the source buffer is used directly) upon start() call, then the operation
+ * requiring the aligned transfer happens, then the bounce buffer is lost upon
+ * stop() call.
+ */
+#define GEN_BB_READ	(1 << 0)
+/*
+ * GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware.
+ * The source buffer starts in an undefined state upon start() call, then the
+ * operation requiring the aligned transfer happens, then the bounce buffer is
+ * copied into the destination buffer (if unaligned, otherwise destination
+ * buffer is used directly) upon stop() call.
+ */
+#define GEN_BB_WRITE	(1 << 1)
+/*
+ * GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware.
+ * The source buffer is copied into the bounce buffer (if unaligned, otherwise
+ * the source buffer is used directly) upon start() call, then the  operation
+ * requiring the aligned transfer happens, then the bounce buffer is  copied
+ * into the destination buffer (if unaligned, otherwise destination buffer is
+ * used directly) upon stop() call.
+ */
+#define GEN_BB_RW	(GEN_BB_READ | GEN_BB_WRITE)
+
+struct bounce_buffer {
+	/* Copy of data parameter passed to start() */
+	void *user_buffer;
+	/*
+	 * DMA-aligned buffer. This field is always set to the value that
+	 * should be used for DMA; either equal to .user_buffer, or to a
+	 * freshly allocated aligned buffer.
+	 */
+	void *bounce_buffer;
+	/* Copy of len parameter passed to start() */
+	size_t len;
+	/* DMA-aligned buffer length */
+	size_t len_aligned;
+	/* Copy of flags parameter passed to start() */
+	unsigned int flags;
+};
+
+/**
+ * bounce_buffer_start() -- Start the bounce buffer session
+ * state:	stores state passed between bounce_buffer_{start,stop}
+ * data:	pointer to buffer to be aligned
+ * len:		length of the buffer
+ * flags:	flags describing the transaction, see above.
+ */
+int bounce_buffer_start(struct bounce_buffer *state, void *data,
+			size_t len, unsigned int flags);
+/**
+ * bounce_buffer_stop() -- Finish the bounce buffer session
+ * state:	stores state passed between bounce_buffer_{start,stop}
+ */
+int bounce_buffer_stop(struct bounce_buffer *state);
+
+#endif
diff --git a/include/btrfs.h b/include/btrfs.h
new file mode 100644
index 0000000..5be61e3
--- /dev/null
+++ b/include/btrfs.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * BTRFS filesystem implementation for U-Boot
+ *
+ * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
+ */
+
+#ifndef __U_BOOT_BTRFS_H__
+#define __U_BOOT_BTRFS_H__
+
+int btrfs_probe(struct blk_desc *, disk_partition_t *);
+int btrfs_ls(const char *);
+int btrfs_exists(const char *);
+int btrfs_size(const char *, loff_t *);
+int btrfs_read(const char *, void *, loff_t, loff_t, loff_t *);
+void btrfs_close(void);
+int btrfs_uuid(char *);
+void btrfs_list_subvols(void);
+
+#endif /* __U_BOOT_BTRFS_H__ */
diff --git a/include/bus_vcxk.h b/include/bus_vcxk.h
new file mode 100644
index 0000000..eecba40
--- /dev/null
+++ b/include/bus_vcxk.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2005-2009
+ * Jens Scharsig @ BuS Elektronik GmbH & Co. KG, <esw@bus-elektronik.de>
+ */
+
+#ifndef __BUS_VCXK_H_
+#define __BUS_VCXK_H_
+
+extern int vcxk_init(unsigned long width, unsigned long height);
+extern void vcxk_setpixel(int x, int y, unsigned long color);
+extern int vcxk_acknowledge_wait(void);
+extern int vcxk_request(void);
+extern void vcxk_loadimage(ulong source);
+extern int vcxk_display_bitmap(ulong addr, int x, int y);
+extern void vcxk_setbrightness(unsigned int side, short brightness);
+extern int video_display_bitmap(ulong addr, int x, int y);
+
+#endif
diff --git a/include/bzlib.h b/include/bzlib.h
new file mode 100644
index 0000000..19314f8
--- /dev/null
+++ b/include/bzlib.h
@@ -0,0 +1,332 @@
+/*
+ * This file is a modified version of bzlib.h from the bzip2-1.0.2
+ * distribution which can be found at http://sources.redhat.com/bzip2/
+ */
+
+/*-------------------------------------------------------------*/
+/*--- Public header file for the library.                   ---*/
+/*---                                               bzlib.h ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+  This file is a part of bzip2 and/or libbzip2, a program and
+  library for lossless, block-sorting data compression.
+
+  Copyright (C) 1996-2002 Julian R Seward.  All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+  1. Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+  2. The origin of this software must not be misrepresented; you must
+     not claim that you wrote the original software.  If you use this
+     software in a product, an acknowledgment in the product
+     documentation would be appreciated but is not required.
+
+  3. Altered source versions must be plainly marked as such, and must
+     not be misrepresented as being the original software.
+
+  4. The name of the author may not be used to endorse or promote
+     products derived from this software without specific prior written
+     permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  Julian Seward, Cambridge, UK.
+  jseward@acm.org
+  bzip2/libbzip2 version 1.0 of 21 March 2000
+
+  This program is based on (at least) the work of:
+     Mike Burrows
+     David Wheeler
+     Peter Fenwick
+     Alistair Moffat
+     Radford Neal
+     Ian H. Witten
+     Robert Sedgewick
+     Jon L. Bentley
+
+  For more information on these sources, see the manual.
+--*/
+
+
+#ifndef _BZLIB_H
+#define _BZLIB_H
+
+/* Configure for U-Boot environment */
+#define BZ_NO_STDIO
+
+#ifndef CONFIG_SANDBOX
+#define BZ_NO_COMPRESS
+#endif
+/* End of configuration for U-Boot environment */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BZ_RUN               0
+#define BZ_FLUSH             1
+#define BZ_FINISH            2
+
+#define BZ_OK                0
+#define BZ_RUN_OK            1
+#define BZ_FLUSH_OK          2
+#define BZ_FINISH_OK         3
+#define BZ_STREAM_END        4
+#define BZ_SEQUENCE_ERROR    (-1)
+#define BZ_PARAM_ERROR       (-2)
+#define BZ_MEM_ERROR         (-3)
+#define BZ_DATA_ERROR        (-4)
+#define BZ_DATA_ERROR_MAGIC  (-5)
+#define BZ_IO_ERROR          (-6)
+#define BZ_UNEXPECTED_EOF    (-7)
+#define BZ_OUTBUFF_FULL      (-8)
+#define BZ_CONFIG_ERROR      (-9)
+
+typedef
+   struct {
+      char *next_in;
+      unsigned int avail_in;
+      unsigned int total_in_lo32;
+      unsigned int total_in_hi32;
+
+      char *next_out;
+      unsigned int avail_out;
+      unsigned int total_out_lo32;
+      unsigned int total_out_hi32;
+
+      void *state;
+
+      void *(*bzalloc)(void *,int,int);
+      void (*bzfree)(void *,void *);
+      void *opaque;
+   }
+   bz_stream;
+
+
+#ifndef BZ_IMPORT
+#define BZ_EXPORT
+#endif
+
+#ifdef _WIN32
+#   include <windows.h>
+#   ifdef small
+      /* windows.h define small to char */
+#      undef small
+#   endif
+#   ifdef BZ_EXPORT
+#   define BZ_API(func) WINAPI func
+#   define BZ_EXTERN extern
+#   else
+   /* import windows dll dynamically */
+#   define BZ_API(func) (WINAPI * func)
+#   define BZ_EXTERN
+#   endif
+#else
+#   define BZ_API(func) func
+#   define BZ_EXTERN extern
+#endif
+
+
+/*-- Core (low-level) library functions --*/
+
+BZ_EXTERN int BZ_API(BZ2_bzCompressInit) (
+      bz_stream* strm,
+      int        blockSize100k,
+      int        verbosity,
+      int        workFactor
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzCompress) (
+      bz_stream* strm,
+      int action
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzCompressEnd) (
+      bz_stream* strm
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompressInit) (
+      bz_stream *strm,
+      int       verbosity,
+      int       small
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompress) (
+      bz_stream* strm
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) (
+      bz_stream *strm
+   );
+
+
+/*-- High(er) level library functions --*/
+
+#ifndef BZ_NO_STDIO
+#define BZ_MAX_UNUSED 5000
+
+/* Need a definitition for FILE */
+#include <stdio.h>
+
+typedef void BZFILE;
+
+BZ_EXTERN BZFILE* BZ_API(BZ2_bzReadOpen) (
+      int*  bzerror,
+      FILE* f,
+      int   verbosity,
+      int   small,
+      void* unused,
+      int   nUnused
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzReadClose) (
+      int*    bzerror,
+      BZFILE* b
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzReadGetUnused) (
+      int*    bzerror,
+      BZFILE* b,
+      void**  unused,
+      int*    nUnused
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzRead) (
+      int*    bzerror,
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN BZFILE* BZ_API(BZ2_bzWriteOpen) (
+      int*  bzerror,
+      FILE* f,
+      int   blockSize100k,
+      int   verbosity,
+      int   workFactor
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWrite) (
+      int*    bzerror,
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWriteClose) (
+      int*          bzerror,
+      BZFILE*       b,
+      int           abandon,
+      unsigned int* nbytes_in,
+      unsigned int* nbytes_out
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWriteClose64) (
+      int*          bzerror,
+      BZFILE*       b,
+      int           abandon,
+      unsigned int* nbytes_in_lo32,
+      unsigned int* nbytes_in_hi32,
+      unsigned int* nbytes_out_lo32,
+      unsigned int* nbytes_out_hi32
+   );
+#endif
+
+
+/*-- Utility functions --*/
+
+BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffCompress) (
+      char*         dest,
+      unsigned int* destLen,
+      char*         source,
+      unsigned int  sourceLen,
+      int           blockSize100k,
+      int           verbosity,
+      int           workFactor
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffDecompress) (
+      char*         dest,
+      unsigned int* destLen,
+      char*         source,
+      unsigned int  sourceLen,
+      int           small,
+      int           verbosity
+   );
+
+
+/*--
+   Code contributed by Yoshioka Tsuneo
+   (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp),
+   to support better zlib compatibility.
+   This code is not _officially_ part of libbzip2 (yet);
+   I haven't tested it, documented it, or considered the
+   threading-safeness of it.
+   If this code breaks, please contact both Yoshioka and me.
+--*/
+
+BZ_EXTERN const char * BZ_API(BZ2_bzlibVersion) (
+      void
+   );
+
+#ifndef BZ_NO_STDIO
+BZ_EXTERN BZFILE * BZ_API(BZ2_bzopen) (
+      const char *path,
+      const char *mode
+   );
+
+BZ_EXTERN BZFILE * BZ_API(BZ2_bzdopen) (
+      int        fd,
+      const char *mode
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzread) (
+      BZFILE* b,
+      void* buf,
+      int len
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzwrite) (
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzflush) (
+      BZFILE* b
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzclose) (
+      BZFILE* b
+   );
+
+BZ_EXTERN const char * BZ_API(BZ2_bzerror) (
+      BZFILE *b,
+      int    *errnum
+   );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*-------------------------------------------------------------*/
+/*--- end                                           bzlib.h ---*/
+/*-------------------------------------------------------------*/
diff --git a/include/cache.h b/include/cache.h
new file mode 100644
index 0000000..32f59fd
--- /dev/null
+++ b/include/cache.h
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+/*
+ * Structure for the cache controller
+ */
+struct cache_info {
+	phys_addr_t base; /* Base physical address of cache device. */
+};
+
+struct cache_ops {
+	/**
+	 * get_info() - Get basic cache info
+	 *
+	 * @dev:	Device to check (UCLASS_CACHE)
+	 * @info:	Place to put info
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_info)(struct udevice *dev, struct cache_info *info);
+
+	/**
+	 * enable() - Enable cache
+	 *
+	 * @dev:	Device to check (UCLASS_CACHE)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*enable)(struct udevice *dev);
+
+	/**
+	 * disable() - Flush and disable cache
+	 *
+	 * @dev:	Device to check (UCLASS_CACHE)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*disable)(struct udevice *dev);
+};
+
+#define cache_get_ops(dev)	((struct cache_ops *)(dev)->driver->ops)
+
+/**
+ * cache_get_info() - Get information about a cache controller
+ *
+ * @dev:	Device to check (UCLASS_CACHE)
+ * @info:	Returns cache info
+ * @return 0 if OK, -ve on error
+ */
+int cache_get_info(struct udevice *dev, struct cache_info *info);
+
+/**
+ * cache_enable() - Enable cache
+ *
+ * @dev:	Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_enable(struct udevice *dev);
+
+/**
+ * cache_disable() - Flush and disable cache
+ *
+ * @dev:	Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_disable(struct udevice *dev);
+#endif
diff --git a/include/capitalization.h b/include/capitalization.h
new file mode 100644
index 0000000..9d7e8d2
--- /dev/null
+++ b/include/capitalization.h
@@ -0,0 +1,2028 @@
+/* SPDX-License-Identifier: Unicode-DFS-2016 */
+/*
+ * Capitalization tables
+ */
+
+struct capitalization_table {
+	u16 upper;
+	u16 lower;
+};
+
+/*
+ * Correspondence table for small and capital Unicode letters in the range of
+ * 0x0000 - 0xffff based on http://www.unicode.org/Public/UCA/11.0.0/allkeys.txt
+ */
+#define UNICODE_CAPITALIZATION_TABLE { \
+	{ 0x0531, /* ARMENIAN CAPITAL LETTER AYB */ \
+	  0x0561, /* ARMENIAN SMALL LETTER AYB */ }, \
+	{ 0x0532, /* ARMENIAN CAPITAL LETTER BEN */ \
+	  0x0562, /* ARMENIAN SMALL LETTER BEN */ }, \
+	{ 0x053E, /* ARMENIAN CAPITAL LETTER CA */ \
+	  0x056E, /* ARMENIAN SMALL LETTER CA */ }, \
+	{ 0x0549, /* ARMENIAN CAPITAL LETTER CHA */ \
+	  0x0579, /* ARMENIAN SMALL LETTER CHA */ }, \
+	{ 0x0543, /* ARMENIAN CAPITAL LETTER CHEH */ \
+	  0x0573, /* ARMENIAN SMALL LETTER CHEH */ }, \
+	{ 0x0551, /* ARMENIAN CAPITAL LETTER CO */ \
+	  0x0581, /* ARMENIAN SMALL LETTER CO */ }, \
+	{ 0x0534, /* ARMENIAN CAPITAL LETTER DA */ \
+	  0x0564, /* ARMENIAN SMALL LETTER DA */ }, \
+	{ 0x0535, /* ARMENIAN CAPITAL LETTER ECH */ \
+	  0x0565, /* ARMENIAN SMALL LETTER ECH */ }, \
+	{ 0x0537, /* ARMENIAN CAPITAL LETTER EH */ \
+	  0x0567, /* ARMENIAN SMALL LETTER EH */ }, \
+	{ 0x0538, /* ARMENIAN CAPITAL LETTER ET */ \
+	  0x0568, /* ARMENIAN SMALL LETTER ET */ }, \
+	{ 0x0556, /* ARMENIAN CAPITAL LETTER FEH */ \
+	  0x0586, /* ARMENIAN SMALL LETTER FEH */ }, \
+	{ 0x0542, /* ARMENIAN CAPITAL LETTER GHAD */ \
+	  0x0572, /* ARMENIAN SMALL LETTER GHAD */ }, \
+	{ 0x0533, /* ARMENIAN CAPITAL LETTER GIM */ \
+	  0x0563, /* ARMENIAN SMALL LETTER GIM */ }, \
+	{ 0x0540, /* ARMENIAN CAPITAL LETTER HO */ \
+	  0x0570, /* ARMENIAN SMALL LETTER HO */ }, \
+	{ 0x053B, /* ARMENIAN CAPITAL LETTER INI */ \
+	  0x056B, /* ARMENIAN SMALL LETTER INI */ }, \
+	{ 0x0541, /* ARMENIAN CAPITAL LETTER JA */ \
+	  0x0571, /* ARMENIAN SMALL LETTER JA */ }, \
+	{ 0x054B, /* ARMENIAN CAPITAL LETTER JHEH */ \
+	  0x057B, /* ARMENIAN SMALL LETTER JHEH */ }, \
+	{ 0x0554, /* ARMENIAN CAPITAL LETTER KEH */ \
+	  0x0584, /* ARMENIAN SMALL LETTER KEH */ }, \
+	{ 0x053F, /* ARMENIAN CAPITAL LETTER KEN */ \
+	  0x056F, /* ARMENIAN SMALL LETTER KEN */ }, \
+	{ 0x053C, /* ARMENIAN CAPITAL LETTER LIWN */ \
+	  0x056C, /* ARMENIAN SMALL LETTER LIWN */ }, \
+	{ 0x0544, /* ARMENIAN CAPITAL LETTER MEN */ \
+	  0x0574, /* ARMENIAN SMALL LETTER MEN */ }, \
+	{ 0x0546, /* ARMENIAN CAPITAL LETTER NOW */ \
+	  0x0576, /* ARMENIAN SMALL LETTER NOW */ }, \
+	{ 0x0555, /* ARMENIAN CAPITAL LETTER OH */ \
+	  0x0585, /* ARMENIAN SMALL LETTER OH */ }, \
+	{ 0x054A, /* ARMENIAN CAPITAL LETTER PEH */ \
+	  0x057A, /* ARMENIAN SMALL LETTER PEH */ }, \
+	{ 0x0553, /* ARMENIAN CAPITAL LETTER PIWR */ \
+	  0x0583, /* ARMENIAN SMALL LETTER PIWR */ }, \
+	{ 0x054C, /* ARMENIAN CAPITAL LETTER RA */ \
+	  0x057C, /* ARMENIAN SMALL LETTER RA */ }, \
+	{ 0x0550, /* ARMENIAN CAPITAL LETTER REH */ \
+	  0x0580, /* ARMENIAN SMALL LETTER REH */ }, \
+	{ 0x054D, /* ARMENIAN CAPITAL LETTER SEH */ \
+	  0x057D, /* ARMENIAN SMALL LETTER SEH */ }, \
+	{ 0x0547, /* ARMENIAN CAPITAL LETTER SHA */ \
+	  0x0577, /* ARMENIAN SMALL LETTER SHA */ }, \
+	{ 0x054F, /* ARMENIAN CAPITAL LETTER TIWN */ \
+	  0x057F, /* ARMENIAN SMALL LETTER TIWN */ }, \
+	{ 0x0539, /* ARMENIAN CAPITAL LETTER TO */ \
+	  0x0569, /* ARMENIAN SMALL LETTER TO */ }, \
+	{ 0x054E, /* ARMENIAN CAPITAL LETTER VEW */ \
+	  0x057E, /* ARMENIAN SMALL LETTER VEW */ }, \
+	{ 0x0548, /* ARMENIAN CAPITAL LETTER VO */ \
+	  0x0578, /* ARMENIAN SMALL LETTER VO */ }, \
+	{ 0x053D, /* ARMENIAN CAPITAL LETTER XEH */ \
+	  0x056D, /* ARMENIAN SMALL LETTER XEH */ }, \
+	{ 0x0545, /* ARMENIAN CAPITAL LETTER YI */ \
+	  0x0575, /* ARMENIAN SMALL LETTER YI */ }, \
+	{ 0x0552, /* ARMENIAN CAPITAL LETTER YIWN */ \
+	  0x0582, /* ARMENIAN SMALL LETTER YIWN */ }, \
+	{ 0x0536, /* ARMENIAN CAPITAL LETTER ZA */ \
+	  0x0566, /* ARMENIAN SMALL LETTER ZA */ }, \
+	{ 0x053A, /* ARMENIAN CAPITAL LETTER ZHE */ \
+	  0x056A, /* ARMENIAN SMALL LETTER ZHE */ }, \
+	{ 0x24B6, /* CIRCLED LATIN CAPITAL LETTER A */ \
+	  0x24D0, /* CIRCLED LATIN SMALL LETTER A */ }, \
+	{ 0x24B7, /* CIRCLED LATIN CAPITAL LETTER B */ \
+	  0x24D1, /* CIRCLED LATIN SMALL LETTER B */ }, \
+	{ 0x24B8, /* CIRCLED LATIN CAPITAL LETTER C */ \
+	  0x24D2, /* CIRCLED LATIN SMALL LETTER C */ }, \
+	{ 0x24B9, /* CIRCLED LATIN CAPITAL LETTER D */ \
+	  0x24D3, /* CIRCLED LATIN SMALL LETTER D */ }, \
+	{ 0x24BA, /* CIRCLED LATIN CAPITAL LETTER E */ \
+	  0x24D4, /* CIRCLED LATIN SMALL LETTER E */ }, \
+	{ 0x24BB, /* CIRCLED LATIN CAPITAL LETTER F */ \
+	  0x24D5, /* CIRCLED LATIN SMALL LETTER F */ }, \
+	{ 0x24BC, /* CIRCLED LATIN CAPITAL LETTER G */ \
+	  0x24D6, /* CIRCLED LATIN SMALL LETTER G */ }, \
+	{ 0x24BD, /* CIRCLED LATIN CAPITAL LETTER H */ \
+	  0x24D7, /* CIRCLED LATIN SMALL LETTER H */ }, \
+	{ 0x24BE, /* CIRCLED LATIN CAPITAL LETTER I */ \
+	  0x24D8, /* CIRCLED LATIN SMALL LETTER I */ }, \
+	{ 0x24BF, /* CIRCLED LATIN CAPITAL LETTER J */ \
+	  0x24D9, /* CIRCLED LATIN SMALL LETTER J */ }, \
+	{ 0x24C0, /* CIRCLED LATIN CAPITAL LETTER K */ \
+	  0x24DA, /* CIRCLED LATIN SMALL LETTER K */ }, \
+	{ 0x24C1, /* CIRCLED LATIN CAPITAL LETTER L */ \
+	  0x24DB, /* CIRCLED LATIN SMALL LETTER L */ }, \
+	{ 0x24C2, /* CIRCLED LATIN CAPITAL LETTER M */ \
+	  0x24DC, /* CIRCLED LATIN SMALL LETTER M */ }, \
+	{ 0x24C3, /* CIRCLED LATIN CAPITAL LETTER N */ \
+	  0x24DD, /* CIRCLED LATIN SMALL LETTER N */ }, \
+	{ 0x24C4, /* CIRCLED LATIN CAPITAL LETTER O */ \
+	  0x24DE, /* CIRCLED LATIN SMALL LETTER O */ }, \
+	{ 0x24C5, /* CIRCLED LATIN CAPITAL LETTER P */ \
+	  0x24DF, /* CIRCLED LATIN SMALL LETTER P */ }, \
+	{ 0x24C6, /* CIRCLED LATIN CAPITAL LETTER Q */ \
+	  0x24E0, /* CIRCLED LATIN SMALL LETTER Q */ }, \
+	{ 0x24C7, /* CIRCLED LATIN CAPITAL LETTER R */ \
+	  0x24E1, /* CIRCLED LATIN SMALL LETTER R */ }, \
+	{ 0x24C8, /* CIRCLED LATIN CAPITAL LETTER S */ \
+	  0x24E2, /* CIRCLED LATIN SMALL LETTER S */ }, \
+	{ 0x24C9, /* CIRCLED LATIN CAPITAL LETTER T */ \
+	  0x24E3, /* CIRCLED LATIN SMALL LETTER T */ }, \
+	{ 0x24CA, /* CIRCLED LATIN CAPITAL LETTER U */ \
+	  0x24E4, /* CIRCLED LATIN SMALL LETTER U */ }, \
+	{ 0x24CB, /* CIRCLED LATIN CAPITAL LETTER V */ \
+	  0x24E5, /* CIRCLED LATIN SMALL LETTER V */ }, \
+	{ 0x24CC, /* CIRCLED LATIN CAPITAL LETTER W */ \
+	  0x24E6, /* CIRCLED LATIN SMALL LETTER W */ }, \
+	{ 0x24CD, /* CIRCLED LATIN CAPITAL LETTER X */ \
+	  0x24E7, /* CIRCLED LATIN SMALL LETTER X */ }, \
+	{ 0x24CE, /* CIRCLED LATIN CAPITAL LETTER Y */ \
+	  0x24E8, /* CIRCLED LATIN SMALL LETTER Y */ }, \
+	{ 0x24CF, /* CIRCLED LATIN CAPITAL LETTER Z */ \
+	  0x24E9, /* CIRCLED LATIN SMALL LETTER Z */ }, \
+	{ 0x2CC8, /* COPTIC CAPITAL LETTER AKHMIMIC KHEI */ \
+	  0x2CC9, /* COPTIC SMALL LETTER AKHMIMIC KHEI */ }, \
+	{ 0x2C80, /* COPTIC CAPITAL LETTER ALFA */ \
+	  0x2C81, /* COPTIC SMALL LETTER ALFA */ }, \
+	{ 0x2CF2, /* COPTIC CAPITAL LETTER BOHAIRIC KHEI */ \
+	  0x2CF3, /* COPTIC SMALL LETTER BOHAIRIC KHEI */ }, \
+	{ 0x2CC2, /* COPTIC CAPITAL LETTER CROSSED SHEI */ \
+	  0x2CC3, /* COPTIC SMALL LETTER CROSSED SHEI */ }, \
+	{ 0x2CB6, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC EIE */ \
+	  0x2CB7, /* COPTIC SMALL LETTER CRYPTOGRAMMIC EIE */ }, \
+	{ 0x2CED, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC GANGIA */ \
+	  0x2CEE, /* COPTIC SMALL LETTER CRYPTOGRAMMIC GANGIA */ }, \
+	{ 0x2CBC, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC NI */ \
+	  0x2CBD, /* COPTIC SMALL LETTER CRYPTOGRAMMIC NI */ }, \
+	{ 0x2CEB, /* COPTIC CAPITAL LETTER CRYPTOGRAMMIC SHEI */ \
+	  0x2CEC, /* COPTIC SMALL LETTER CRYPTOGRAMMIC SHEI */ }, \
+	{ 0x2C86, /* COPTIC CAPITAL LETTER DALDA */ \
+	  0x2C87, /* COPTIC SMALL LETTER DALDA */ }, \
+	{ 0x03EE, /* COPTIC CAPITAL LETTER DEI */ \
+	  0x03EF, /* COPTIC SMALL LETTER DEI */ }, \
+	{ 0x2CB2, /* COPTIC CAPITAL LETTER DIALECT-P ALEF */ \
+	  0x2CB3, /* COPTIC SMALL LETTER DIALECT-P ALEF */ }, \
+	{ 0x2CCA, /* COPTIC CAPITAL LETTER DIALECT-P HORI */ \
+	  0x2CCB, /* COPTIC SMALL LETTER DIALECT-P HORI */ }, \
+	{ 0x2CB8, /* COPTIC CAPITAL LETTER DIALECT-P KAPA */ \
+	  0x2CB9, /* COPTIC SMALL LETTER DIALECT-P KAPA */ }, \
+	{ 0x2CBA, /* COPTIC CAPITAL LETTER DIALECT-P NI */ \
+	  0x2CBB, /* COPTIC SMALL LETTER DIALECT-P NI */ }, \
+	{ 0x2C88, /* COPTIC CAPITAL LETTER EIE */ \
+	  0x2C89, /* COPTIC SMALL LETTER EIE */ }, \
+	{ 0x03E4, /* COPTIC CAPITAL LETTER FEI */ \
+	  0x03E5, /* COPTIC SMALL LETTER FEI */ }, \
+	{ 0x2CAA, /* COPTIC CAPITAL LETTER FI */ \
+	  0x2CAB, /* COPTIC SMALL LETTER FI */ }, \
+	{ 0x2C84, /* COPTIC CAPITAL LETTER GAMMA */ \
+	  0x2C85, /* COPTIC SMALL LETTER GAMMA */ }, \
+	{ 0x03EA, /* COPTIC CAPITAL LETTER GANGIA */ \
+	  0x03EB, /* COPTIC SMALL LETTER GANGIA */ }, \
+	{ 0x2C8E, /* COPTIC CAPITAL LETTER HATE */ \
+	  0x2C8F, /* COPTIC SMALL LETTER HATE */ }, \
+	{ 0x03E8, /* COPTIC CAPITAL LETTER HORI */ \
+	  0x03E9, /* COPTIC SMALL LETTER HORI */ }, \
+	{ 0x2C92, /* COPTIC CAPITAL LETTER IAUDA */ \
+	  0x2C93, /* COPTIC SMALL LETTER IAUDA */ }, \
+	{ 0x2C94, /* COPTIC CAPITAL LETTER KAPA */ \
+	  0x2C95, /* COPTIC SMALL LETTER KAPA */ }, \
+	{ 0x03E6, /* COPTIC CAPITAL LETTER KHEI */ \
+	  0x03E7, /* COPTIC SMALL LETTER KHEI */ }, \
+	{ 0x2CAC, /* COPTIC CAPITAL LETTER KHI */ \
+	  0x2CAD, /* COPTIC SMALL LETTER KHI */ }, \
+	{ 0x2C9C, /* COPTIC CAPITAL LETTER KSI */ \
+	  0x2C9D, /* COPTIC SMALL LETTER KSI */ }, \
+	{ 0x2C96, /* COPTIC CAPITAL LETTER LAULA */ \
+	  0x2C97, /* COPTIC SMALL LETTER LAULA */ }, \
+	{ 0x2CD0, /* COPTIC CAPITAL LETTER L-SHAPED HA */ \
+	  0x2CD1, /* COPTIC SMALL LETTER L-SHAPED HA */ }, \
+	{ 0x2C98, /* COPTIC CAPITAL LETTER MI */ \
+	  0x2C99, /* COPTIC SMALL LETTER MI */ }, \
+	{ 0x2C9A, /* COPTIC CAPITAL LETTER NI */ \
+	  0x2C9B, /* COPTIC SMALL LETTER NI */ }, \
+	{ 0x2C9E, /* COPTIC CAPITAL LETTER O */ \
+	  0x2C9F, /* COPTIC SMALL LETTER O */ }, \
+	{ 0x2CB4, /* COPTIC CAPITAL LETTER OLD COPTIC AIN */ \
+	  0x2CB5, /* COPTIC SMALL LETTER OLD COPTIC AIN */ }, \
+	{ 0x2CD8, /* COPTIC CAPITAL LETTER OLD COPTIC DJA */ \
+	  0x2CD9, /* COPTIC SMALL LETTER OLD COPTIC DJA */ }, \
+	{ 0x2CC6, /* COPTIC CAPITAL LETTER OLD COPTIC ESH */ \
+	  0x2CC7, /* COPTIC SMALL LETTER OLD COPTIC ESH */ }, \
+	{ 0x2CD6, /* COPTIC CAPITAL LETTER OLD COPTIC GANGIA */ \
+	  0x2CD7, /* COPTIC SMALL LETTER OLD COPTIC GANGIA */ }, \
+	{ 0x2CCE, /* COPTIC CAPITAL LETTER OLD COPTIC HA */ \
+	  0x2CCF, /* COPTIC SMALL LETTER OLD COPTIC HA */ }, \
+	{ 0x2CD4, /* COPTIC CAPITAL LETTER OLD COPTIC HAT */ \
+	  0x2CD5, /* COPTIC SMALL LETTER OLD COPTIC HAT */ }, \
+	{ 0x2CD2, /* COPTIC CAPITAL LETTER OLD COPTIC HEI */ \
+	  0x2CD3, /* COPTIC SMALL LETTER OLD COPTIC HEI */ }, \
+	{ 0x2CCC, /* COPTIC CAPITAL LETTER OLD COPTIC HORI */ \
+	  0x2CCD, /* COPTIC SMALL LETTER OLD COPTIC HORI */ }, \
+	{ 0x2CBE, /* COPTIC CAPITAL LETTER OLD COPTIC OOU */ \
+	  0x2CBF, /* COPTIC SMALL LETTER OLD COPTIC OOU */ }, \
+	{ 0x2CC4, /* COPTIC CAPITAL LETTER OLD COPTIC SHEI */ \
+	  0x2CC5, /* COPTIC SMALL LETTER OLD COPTIC SHEI */ }, \
+	{ 0x2CDA, /* COPTIC CAPITAL LETTER OLD COPTIC SHIMA */ \
+	  0x2CDB, /* COPTIC SMALL LETTER OLD COPTIC SHIMA */ }, \
+	{ 0x2CDE, /* COPTIC CAPITAL LETTER OLD NUBIAN NGI */ \
+	  0x2CDF, /* COPTIC SMALL LETTER OLD NUBIAN NGI */ }, \
+	{ 0x2CE0, /* COPTIC CAPITAL LETTER OLD NUBIAN NYI */ \
+	  0x2CE1, /* COPTIC SMALL LETTER OLD NUBIAN NYI */ }, \
+	{ 0x2CDC, /* COPTIC CAPITAL LETTER OLD NUBIAN SHIMA */ \
+	  0x2CDD, /* COPTIC SMALL LETTER OLD NUBIAN SHIMA */ }, \
+	{ 0x2CE2, /* COPTIC CAPITAL LETTER OLD NUBIAN WAU */ \
+	  0x2CE3, /* COPTIC SMALL LETTER OLD NUBIAN WAU */ }, \
+	{ 0x2CB0, /* COPTIC CAPITAL LETTER OOU */ \
+	  0x2CB1, /* COPTIC SMALL LETTER OOU */ }, \
+	{ 0x2CA0, /* COPTIC CAPITAL LETTER PI */ \
+	  0x2CA1, /* COPTIC SMALL LETTER PI */ }, \
+	{ 0x2CAE, /* COPTIC CAPITAL LETTER PSI */ \
+	  0x2CAF, /* COPTIC SMALL LETTER PSI */ }, \
+	{ 0x2CA2, /* COPTIC CAPITAL LETTER RO */ \
+	  0x2CA3, /* COPTIC SMALL LETTER RO */ }, \
+	{ 0x2CC0, /* COPTIC CAPITAL LETTER SAMPI */ \
+	  0x2CC1, /* COPTIC SMALL LETTER SAMPI */ }, \
+	{ 0x03E2, /* COPTIC CAPITAL LETTER SHEI */ \
+	  0x03E3, /* COPTIC SMALL LETTER SHEI */ }, \
+	{ 0x03EC, /* COPTIC CAPITAL LETTER SHIMA */ \
+	  0x03ED, /* COPTIC SMALL LETTER SHIMA */ }, \
+	{ 0x2CA4, /* COPTIC CAPITAL LETTER SIMA */ \
+	  0x2CA5, /* COPTIC SMALL LETTER SIMA */ }, \
+	{ 0x2C8A, /* COPTIC CAPITAL LETTER SOU */ \
+	  0x2C8B, /* COPTIC SMALL LETTER SOU */ }, \
+	{ 0x2CA6, /* COPTIC CAPITAL LETTER TAU */ \
+	  0x2CA7, /* COPTIC SMALL LETTER TAU */ }, \
+	{ 0x2C90, /* COPTIC CAPITAL LETTER THETHE */ \
+	  0x2C91, /* COPTIC SMALL LETTER THETHE */ }, \
+	{ 0x2CA8, /* COPTIC CAPITAL LETTER UA */ \
+	  0x2CA9, /* COPTIC SMALL LETTER UA */ }, \
+	{ 0x2C82, /* COPTIC CAPITAL LETTER VIDA */ \
+	  0x2C83, /* COPTIC SMALL LETTER VIDA */ }, \
+	{ 0x2C8C, /* COPTIC CAPITAL LETTER ZATA */ \
+	  0x2C8D, /* COPTIC SMALL LETTER ZATA */ }, \
+	{ 0x0410, /* CYRILLIC CAPITAL LETTER A */ \
+	  0x0430, /* CYRILLIC SMALL LETTER A */ }, \
+	{ 0x04D0, /* CYRILLIC CAPITAL LETTER A WITH BREVE */ \
+	  0x04D1, /* CYRILLIC SMALL LETTER A WITH BREVE */ }, \
+	{ 0x04D2, /* CYRILLIC CAPITAL LETTER A WITH DIAERESIS */ \
+	  0x04D3, /* CYRILLIC SMALL LETTER A WITH DIAERESIS */ }, \
+	{ 0x04BC, /* CYRILLIC CAPITAL LETTER ABKHASIAN CHE */ \
+	  0x04BD, /* CYRILLIC SMALL LETTER ABKHASIAN CHE */ }, \
+	{ 0x04BE, /* CYRILLIC CAPITAL LETTER ABKHASIAN CHE WITH DESCENDER */ \
+	  0x04BF, /* CYRILLIC SMALL LETTER ABKHASIAN CHE WITH DESCENDER */ }, \
+	{ 0x04E0, /* CYRILLIC CAPITAL LETTER ABKHASIAN DZE */ \
+	  0x04E1, /* CYRILLIC SMALL LETTER ABKHASIAN DZE */ }, \
+	{ 0x04A8, /* CYRILLIC CAPITAL LETTER ABKHASIAN HA */ \
+	  0x04A9, /* CYRILLIC SMALL LETTER ABKHASIAN HA */ }, \
+	{ 0x051E, /* CYRILLIC CAPITAL LETTER ALEUT KA */ \
+	  0x051F, /* CYRILLIC SMALL LETTER ALEUT KA */ }, \
+	{ 0x04E8, /* CYRILLIC CAPITAL LETTER BARRED O */ \
+	  0x04E9, /* CYRILLIC SMALL LETTER BARRED O */ }, \
+	{ 0x04EA, /* CYRILLIC CAPITAL LETTER BARRED O WITH DIAERESIS */ \
+	  0x04EB, /* CYRILLIC SMALL LETTER BARRED O WITH DIAERESIS */ }, \
+	{ 0x04A0, /* CYRILLIC CAPITAL LETTER BASHKIR KA */ \
+	  0x04A1, /* CYRILLIC SMALL LETTER BASHKIR KA */ }, \
+	{ 0x0411, /* CYRILLIC CAPITAL LETTER BE */ \
+	  0x0431, /* CYRILLIC SMALL LETTER BE */ }, \
+	{ 0x046A, /* CYRILLIC CAPITAL LETTER BIG YUS */ \
+	  0x046B, /* CYRILLIC SMALL LETTER BIG YUS */ }, \
+	{ 0xA66A, /* CYRILLIC CAPITAL LETTER BINOCULAR O */ \
+	  0xA66B, /* CYRILLIC SMALL LETTER BINOCULAR O */ }, \
+	{ 0xA65A, /* CYRILLIC CAPITAL LETTER BLENDED YUS */ \
+	  0xA65B, /* CYRILLIC SMALL LETTER BLENDED YUS */ }, \
+	{ 0xA64C, /* CYRILLIC CAPITAL LETTER BROAD OMEGA */ \
+	  0xA64D, /* CYRILLIC SMALL LETTER BROAD OMEGA */ }, \
+	{ 0x0406, /* CYRILLIC CAPITAL LETTER BYELORUSSIAN-UKRAINIAN I */ \
+	  0x0456, /* CYRILLIC SMALL LETTER BYELORUSSIAN-UKRAINIAN I */ }, \
+	{ 0xA686, /* CYRILLIC CAPITAL LETTER CCHE */ \
+	  0xA687, /* CYRILLIC SMALL LETTER CCHE */ }, \
+	{ 0x0427, /* CYRILLIC CAPITAL LETTER CHE */ \
+	  0x0447, /* CYRILLIC SMALL LETTER CHE */ }, \
+	{ 0x04B6, /* CYRILLIC CAPITAL LETTER CHE WITH DESCENDER */ \
+	  0x04B7, /* CYRILLIC SMALL LETTER CHE WITH DESCENDER */ }, \
+	{ 0x04F4, /* CYRILLIC CAPITAL LETTER CHE WITH DIAERESIS */ \
+	  0x04F5, /* CYRILLIC SMALL LETTER CHE WITH DIAERESIS */ }, \
+	{ 0x04B8, /* CYRILLIC CAPITAL LETTER CHE WITH VERTICAL STROKE */ \
+	  0x04B9, /* CYRILLIC SMALL LETTER CHE WITH VERTICAL STROKE */ }, \
+	{ 0xA658, /* CYRILLIC CAPITAL LETTER CLOSED LITTLE YUS */ \
+	  0xA659, /* CYRILLIC SMALL LETTER CLOSED LITTLE YUS */ }, \
+	{ 0xA69A, /* CYRILLIC CAPITAL LETTER CROSSED O */ \
+	  0xA69B, /* CYRILLIC SMALL LETTER CROSSED O */ }, \
+	{ 0x052C, /* CYRILLIC CAPITAL LETTER DCHE */ \
+	  0x052D, /* CYRILLIC SMALL LETTER DCHE */ }, \
+	{ 0x0414, /* CYRILLIC CAPITAL LETTER DE */ \
+	  0x0434, /* CYRILLIC SMALL LETTER DE */ }, \
+	{ 0x0402, /* CYRILLIC CAPITAL LETTER DJE */ \
+	  0x0452, /* CYRILLIC SMALL LETTER DJE */ }, \
+	{ 0xA648, /* CYRILLIC CAPITAL LETTER DJERV */ \
+	  0xA649, /* CYRILLIC SMALL LETTER DJERV */ }, \
+	{ 0xA66C, /* CYRILLIC CAPITAL LETTER DOUBLE MONOCULAR O */ \
+	  0xA66D, /* CYRILLIC SMALL LETTER DOUBLE MONOCULAR O */ }, \
+	{ 0xA698, /* CYRILLIC CAPITAL LETTER DOUBLE O */ \
+	  0xA699, /* CYRILLIC SMALL LETTER DOUBLE O */ }, \
+	{ 0xA680, /* CYRILLIC CAPITAL LETTER DWE */ \
+	  0xA681, /* CYRILLIC SMALL LETTER DWE */ }, \
+	{ 0x0405, /* CYRILLIC CAPITAL LETTER DZE */ \
+	  0x0455, /* CYRILLIC SMALL LETTER DZE */ }, \
+	{ 0xA642, /* CYRILLIC CAPITAL LETTER DZELO */ \
+	  0xA643, /* CYRILLIC SMALL LETTER DZELO */ }, \
+	{ 0x040F, /* CYRILLIC CAPITAL LETTER DZHE */ \
+	  0x045F, /* CYRILLIC SMALL LETTER DZHE */ }, \
+	{ 0xA682, /* CYRILLIC CAPITAL LETTER DZWE */ \
+	  0xA683, /* CYRILLIC SMALL LETTER DZWE */ }, \
+	{ 0xA688, /* CYRILLIC CAPITAL LETTER DZZE */ \
+	  0xA689, /* CYRILLIC SMALL LETTER DZZE */ }, \
+	{ 0x052A, /* CYRILLIC CAPITAL LETTER DZZHE */ \
+	  0x052B, /* CYRILLIC SMALL LETTER DZZHE */ }, \
+	{ 0x042D, /* CYRILLIC CAPITAL LETTER E */ \
+	  0x044D, /* CYRILLIC SMALL LETTER E */ }, \
+	{ 0x04EC, /* CYRILLIC CAPITAL LETTER E WITH DIAERESIS */ \
+	  0x04ED, /* CYRILLIC SMALL LETTER E WITH DIAERESIS */ }, \
+	{ 0x0424, /* CYRILLIC CAPITAL LETTER EF */ \
+	  0x0444, /* CYRILLIC SMALL LETTER EF */ }, \
+	{ 0x041B, /* CYRILLIC CAPITAL LETTER EL */ \
+	  0x043B, /* CYRILLIC SMALL LETTER EL */ }, \
+	{ 0x052E, /* CYRILLIC CAPITAL LETTER EL WITH DESCENDER */ \
+	  0x052F, /* CYRILLIC SMALL LETTER EL WITH DESCENDER */ }, \
+	{ 0x0512, /* CYRILLIC CAPITAL LETTER EL WITH HOOK */ \
+	  0x0513, /* CYRILLIC SMALL LETTER EL WITH HOOK */ }, \
+	{ 0x0520, /* CYRILLIC CAPITAL LETTER EL WITH MIDDLE HOOK */ \
+	  0x0521, /* CYRILLIC SMALL LETTER EL WITH MIDDLE HOOK */ }, \
+	{ 0x04C5, /* CYRILLIC CAPITAL LETTER EL WITH TAIL */ \
+	  0x04C6, /* CYRILLIC SMALL LETTER EL WITH TAIL */ }, \
+	{ 0x041C, /* CYRILLIC CAPITAL LETTER EM */ \
+	  0x043C, /* CYRILLIC SMALL LETTER EM */ }, \
+	{ 0x04CD, /* CYRILLIC CAPITAL LETTER EM WITH TAIL */ \
+	  0x04CE, /* CYRILLIC SMALL LETTER EM WITH TAIL */ }, \
+	{ 0x041D, /* CYRILLIC CAPITAL LETTER EN */ \
+	  0x043D, /* CYRILLIC SMALL LETTER EN */ }, \
+	{ 0x04A2, /* CYRILLIC CAPITAL LETTER EN WITH DESCENDER */ \
+	  0x04A3, /* CYRILLIC SMALL LETTER EN WITH DESCENDER */ }, \
+	{ 0x04C7, /* CYRILLIC CAPITAL LETTER EN WITH HOOK */ \
+	  0x04C8, /* CYRILLIC SMALL LETTER EN WITH HOOK */ }, \
+	{ 0x0528, /* CYRILLIC CAPITAL LETTER EN WITH LEFT HOOK */ \
+	  0x0529, /* CYRILLIC SMALL LETTER EN WITH LEFT HOOK */ }, \
+	{ 0x0522, /* CYRILLIC CAPITAL LETTER EN WITH MIDDLE HOOK */ \
+	  0x0523, /* CYRILLIC SMALL LETTER EN WITH MIDDLE HOOK */ }, \
+	{ 0x04C9, /* CYRILLIC CAPITAL LETTER EN WITH TAIL */ \
+	  0x04CA, /* CYRILLIC SMALL LETTER EN WITH TAIL */ }, \
+	{ 0x0420, /* CYRILLIC CAPITAL LETTER ER */ \
+	  0x0440, /* CYRILLIC SMALL LETTER ER */ }, \
+	{ 0x048E, /* CYRILLIC CAPITAL LETTER ER WITH TICK */ \
+	  0x048F, /* CYRILLIC SMALL LETTER ER WITH TICK */ }, \
+	{ 0x0421, /* CYRILLIC CAPITAL LETTER ES */ \
+	  0x0441, /* CYRILLIC SMALL LETTER ES */ }, \
+	{ 0x04AA, /* CYRILLIC CAPITAL LETTER ES WITH DESCENDER */ \
+	  0x04AB, /* CYRILLIC SMALL LETTER ES WITH DESCENDER */ }, \
+	{ 0x0472, /* CYRILLIC CAPITAL LETTER FITA */ \
+	  0x0473, /* CYRILLIC SMALL LETTER FITA */ }, \
+	{ 0x0413, /* CYRILLIC CAPITAL LETTER GHE */ \
+	  0x0433, /* CYRILLIC SMALL LETTER GHE */ }, \
+	{ 0x04F6, /* CYRILLIC CAPITAL LETTER GHE WITH DESCENDER */ \
+	  0x04F7, /* CYRILLIC SMALL LETTER GHE WITH DESCENDER */ }, \
+	{ 0x0494, /* CYRILLIC CAPITAL LETTER GHE WITH MIDDLE HOOK */ \
+	  0x0495, /* CYRILLIC SMALL LETTER GHE WITH MIDDLE HOOK */ }, \
+	{ 0x0492, /* CYRILLIC CAPITAL LETTER GHE WITH STROKE */ \
+	  0x0493, /* CYRILLIC SMALL LETTER GHE WITH STROKE */ }, \
+	{ 0x04FA, /* CYRILLIC CAPITAL LETTER GHE WITH STROKE AND HOOK */ \
+	  0x04FB, /* CYRILLIC SMALL LETTER GHE WITH STROKE AND HOOK */ }, \
+	{ 0x0490, /* CYRILLIC CAPITAL LETTER GHE WITH UPTURN */ \
+	  0x0491, /* CYRILLIC SMALL LETTER GHE WITH UPTURN */ }, \
+	{ 0x0403, /* CYRILLIC CAPITAL LETTER GJE */ \
+	  0x0453, /* CYRILLIC SMALL LETTER GJE */ }, \
+	{ 0x0425, /* CYRILLIC CAPITAL LETTER HA */ \
+	  0x0445, /* CYRILLIC SMALL LETTER HA */ }, \
+	{ 0x04B2, /* CYRILLIC CAPITAL LETTER HA WITH DESCENDER */ \
+	  0x04B3, /* CYRILLIC SMALL LETTER HA WITH DESCENDER */ }, \
+	{ 0x04FC, /* CYRILLIC CAPITAL LETTER HA WITH HOOK */ \
+	  0x04FD, /* CYRILLIC SMALL LETTER HA WITH HOOK */ }, \
+	{ 0x04FE, /* CYRILLIC CAPITAL LETTER HA WITH STROKE */ \
+	  0x04FF, /* CYRILLIC SMALL LETTER HA WITH STROKE */ }, \
+	{ 0x042A, /* CYRILLIC CAPITAL LETTER HARD SIGN */ \
+	  0x044A, /* CYRILLIC SMALL LETTER HARD SIGN */ }, \
+	{ 0xA694, /* CYRILLIC CAPITAL LETTER HWE */ \
+	  0xA695, /* CYRILLIC SMALL LETTER HWE */ }, \
+	{ 0x0418, /* CYRILLIC CAPITAL LETTER I */ \
+	  0x0438, /* CYRILLIC SMALL LETTER I */ }, \
+	{ 0x04E4, /* CYRILLIC CAPITAL LETTER I WITH DIAERESIS */ \
+	  0x04E5, /* CYRILLIC SMALL LETTER I WITH DIAERESIS */ }, \
+	{ 0x040D, /* CYRILLIC CAPITAL LETTER I WITH GRAVE */ \
+	  0x045D, /* CYRILLIC SMALL LETTER I WITH GRAVE */ }, \
+	{ 0x04E2, /* CYRILLIC CAPITAL LETTER I WITH MACRON */ \
+	  0x04E3, /* CYRILLIC SMALL LETTER I WITH MACRON */ }, \
+	{ 0x0415, /* CYRILLIC CAPITAL LETTER IE */ \
+	  0x0435, /* CYRILLIC SMALL LETTER IE */ }, \
+	{ 0x04D6, /* CYRILLIC CAPITAL LETTER IE WITH BREVE */ \
+	  0x04D7, /* CYRILLIC SMALL LETTER IE WITH BREVE */ }, \
+	{ 0x0400, /* CYRILLIC CAPITAL LETTER IE WITH GRAVE */ \
+	  0x0450, /* CYRILLIC SMALL LETTER IE WITH GRAVE */ }, \
+	{ 0x0401, /* CYRILLIC CAPITAL LETTER IO */ \
+	  0x0451, /* CYRILLIC SMALL LETTER IO */ }, \
+	{ 0xA646, /* CYRILLIC CAPITAL LETTER IOTA */ \
+	  0xA647, /* CYRILLIC SMALL LETTER IOTA */ }, \
+	{ 0xA656, /* CYRILLIC CAPITAL LETTER IOTIFIED A */ \
+	  0xA657, /* CYRILLIC SMALL LETTER IOTIFIED A */ }, \
+	{ 0x046C, /* CYRILLIC CAPITAL LETTER IOTIFIED BIG YUS */ \
+	  0x046D, /* CYRILLIC SMALL LETTER IOTIFIED BIG YUS */ }, \
+	{ 0xA65C, /* CYRILLIC CAPITAL LETTER IOTIFIED CLOSED LITTLE YUS */ \
+	  0xA65D, /* CYRILLIC SMALL LETTER IOTIFIED CLOSED LITTLE YUS */ }, \
+	{ 0x0464, /* CYRILLIC CAPITAL LETTER IOTIFIED E */ \
+	  0x0465, /* CYRILLIC SMALL LETTER IOTIFIED E */ }, \
+	{ 0x0468, /* CYRILLIC CAPITAL LETTER IOTIFIED LITTLE YUS */ \
+	  0x0469, /* CYRILLIC SMALL LETTER IOTIFIED LITTLE YUS */ }, \
+	{ 0xA652, /* CYRILLIC CAPITAL LETTER IOTIFIED YAT */ \
+	  0xA653, /* CYRILLIC SMALL LETTER IOTIFIED YAT */ }, \
+	{ 0x0474, /* CYRILLIC CAPITAL LETTER IZHITSA */ \
+	  0x0475, /* CYRILLIC SMALL LETTER IZHITSA */ }, \
+	{ 0x0476, /* CYRILLIC CAPITAL LETTER IZHITSA WITH DOUBLE GRAVE ACCENT */ \
+	  0x0477, /* CYRILLIC SMALL LETTER IZHITSA WITH DOUBLE GRAVE ACCENT */ }, \
+	{ 0x0408, /* CYRILLIC CAPITAL LETTER JE */ \
+	  0x0458, /* CYRILLIC SMALL LETTER JE */ }, \
+	{ 0x041A, /* CYRILLIC CAPITAL LETTER KA */ \
+	  0x043A, /* CYRILLIC SMALL LETTER KA */ }, \
+	{ 0x049A, /* CYRILLIC CAPITAL LETTER KA WITH DESCENDER */ \
+	  0x049B, /* CYRILLIC SMALL LETTER KA WITH DESCENDER */ }, \
+	{ 0x04C3, /* CYRILLIC CAPITAL LETTER KA WITH HOOK */ \
+	  0x04C4, /* CYRILLIC SMALL LETTER KA WITH HOOK */ }, \
+	{ 0x049E, /* CYRILLIC CAPITAL LETTER KA WITH STROKE */ \
+	  0x049F, /* CYRILLIC SMALL LETTER KA WITH STROKE */ }, \
+	{ 0x049C, /* CYRILLIC CAPITAL LETTER KA WITH VERTICAL STROKE */ \
+	  0x049D, /* CYRILLIC SMALL LETTER KA WITH VERTICAL STROKE */ }, \
+	{ 0x04CB, /* CYRILLIC CAPITAL LETTER KHAKASSIAN CHE */ \
+	  0x04CC, /* CYRILLIC SMALL LETTER KHAKASSIAN CHE */ }, \
+	{ 0x040C, /* CYRILLIC CAPITAL LETTER KJE */ \
+	  0x045C, /* CYRILLIC SMALL LETTER KJE */ }, \
+	{ 0x0500, /* CYRILLIC CAPITAL LETTER KOMI DE */ \
+	  0x0501, /* CYRILLIC SMALL LETTER KOMI DE */ }, \
+	{ 0x0502, /* CYRILLIC CAPITAL LETTER KOMI DJE */ \
+	  0x0503, /* CYRILLIC SMALL LETTER KOMI DJE */ }, \
+	{ 0x0506, /* CYRILLIC CAPITAL LETTER KOMI DZJE */ \
+	  0x0507, /* CYRILLIC SMALL LETTER KOMI DZJE */ }, \
+	{ 0x0508, /* CYRILLIC CAPITAL LETTER KOMI LJE */ \
+	  0x0509, /* CYRILLIC SMALL LETTER KOMI LJE */ }, \
+	{ 0x050A, /* CYRILLIC CAPITAL LETTER KOMI NJE */ \
+	  0x050B, /* CYRILLIC SMALL LETTER KOMI NJE */ }, \
+	{ 0x050C, /* CYRILLIC CAPITAL LETTER KOMI SJE */ \
+	  0x050D, /* CYRILLIC SMALL LETTER KOMI SJE */ }, \
+	{ 0x050E, /* CYRILLIC CAPITAL LETTER KOMI TJE */ \
+	  0x050F, /* CYRILLIC SMALL LETTER KOMI TJE */ }, \
+	{ 0x0504, /* CYRILLIC CAPITAL LETTER KOMI ZJE */ \
+	  0x0505, /* CYRILLIC SMALL LETTER KOMI ZJE */ }, \
+	{ 0x0480, /* CYRILLIC CAPITAL LETTER KOPPA */ \
+	  0x0481, /* CYRILLIC SMALL LETTER KOPPA */ }, \
+	{ 0x046E, /* CYRILLIC CAPITAL LETTER KSI */ \
+	  0x046F, /* CYRILLIC SMALL LETTER KSI */ }, \
+	{ 0x0514, /* CYRILLIC CAPITAL LETTER LHA */ \
+	  0x0515, /* CYRILLIC SMALL LETTER LHA */ }, \
+	{ 0x0466, /* CYRILLIC CAPITAL LETTER LITTLE YUS */ \
+	  0x0467, /* CYRILLIC SMALL LETTER LITTLE YUS */ }, \
+	{ 0x0409, /* CYRILLIC CAPITAL LETTER LJE */ \
+	  0x0459, /* CYRILLIC SMALL LETTER LJE */ }, \
+	{ 0xA668, /* CYRILLIC CAPITAL LETTER MONOCULAR O */ \
+	  0xA669, /* CYRILLIC SMALL LETTER MONOCULAR O */ }, \
+	{ 0xA64A, /* CYRILLIC CAPITAL LETTER MONOGRAPH UK */ \
+	  0xA64B, /* CYRILLIC SMALL LETTER MONOGRAPH UK */ }, \
+	{ 0xA64E, /* CYRILLIC CAPITAL LETTER NEUTRAL YER */ \
+	  0xA64F, /* CYRILLIC SMALL LETTER NEUTRAL YER */ }, \
+	{ 0x040A, /* CYRILLIC CAPITAL LETTER NJE */ \
+	  0x045A, /* CYRILLIC SMALL LETTER NJE */ }, \
+	{ 0x041E, /* CYRILLIC CAPITAL LETTER O */ \
+	  0x043E, /* CYRILLIC SMALL LETTER O */ }, \
+	{ 0x04E6, /* CYRILLIC CAPITAL LETTER O WITH DIAERESIS */ \
+	  0x04E7, /* CYRILLIC SMALL LETTER O WITH DIAERESIS */ }, \
+	{ 0x0460, /* CYRILLIC CAPITAL LETTER OMEGA */ \
+	  0x0461, /* CYRILLIC SMALL LETTER OMEGA */ }, \
+	{ 0x047C, /* CYRILLIC CAPITAL LETTER OMEGA WITH TITLO */ \
+	  0x047D, /* CYRILLIC SMALL LETTER OMEGA WITH TITLO */ }, \
+	{ 0x047E, /* CYRILLIC CAPITAL LETTER OT */ \
+	  0x047F, /* CYRILLIC SMALL LETTER OT */ }, \
+	{ 0x041F, /* CYRILLIC CAPITAL LETTER PE */ \
+	  0x043F, /* CYRILLIC SMALL LETTER PE */ }, \
+	{ 0x0524, /* CYRILLIC CAPITAL LETTER PE WITH DESCENDER */ \
+	  0x0525, /* CYRILLIC SMALL LETTER PE WITH DESCENDER */ }, \
+	{ 0x04A6, /* CYRILLIC CAPITAL LETTER PE WITH MIDDLE HOOK */ \
+	  0x04A7, /* CYRILLIC SMALL LETTER PE WITH MIDDLE HOOK */ }, \
+	{ 0x0470, /* CYRILLIC CAPITAL LETTER PSI */ \
+	  0x0471, /* CYRILLIC SMALL LETTER PSI */ }, \
+	{ 0x051A, /* CYRILLIC CAPITAL LETTER QA */ \
+	  0x051B, /* CYRILLIC SMALL LETTER QA */ }, \
+	{ 0xA644, /* CYRILLIC CAPITAL LETTER REVERSED DZE */ \
+	  0xA645, /* CYRILLIC SMALL LETTER REVERSED DZE */ }, \
+	{ 0xA660, /* CYRILLIC CAPITAL LETTER REVERSED TSE */ \
+	  0xA661, /* CYRILLIC SMALL LETTER REVERSED TSE */ }, \
+	{ 0xA654, /* CYRILLIC CAPITAL LETTER REVERSED YU */ \
+	  0xA655, /* CYRILLIC SMALL LETTER REVERSED YU */ }, \
+	{ 0x0510, /* CYRILLIC CAPITAL LETTER REVERSED ZE */ \
+	  0x0511, /* CYRILLIC SMALL LETTER REVERSED ZE */ }, \
+	{ 0x0516, /* CYRILLIC CAPITAL LETTER RHA */ \
+	  0x0517, /* CYRILLIC SMALL LETTER RHA */ }, \
+	{ 0x047A, /* CYRILLIC CAPITAL LETTER ROUND OMEGA */ \
+	  0x047B, /* CYRILLIC SMALL LETTER ROUND OMEGA */ }, \
+	{ 0x04D8, /* CYRILLIC CAPITAL LETTER SCHWA */ \
+	  0x04D9, /* CYRILLIC SMALL LETTER SCHWA */ }, \
+	{ 0x04DA, /* CYRILLIC CAPITAL LETTER SCHWA WITH DIAERESIS */ \
+	  0x04DB, /* CYRILLIC SMALL LETTER SCHWA WITH DIAERESIS */ }, \
+	{ 0x048C, /* CYRILLIC CAPITAL LETTER SEMISOFT SIGN */ \
+	  0x048D, /* CYRILLIC SMALL LETTER SEMISOFT SIGN */ }, \
+	{ 0x0428, /* CYRILLIC CAPITAL LETTER SHA */ \
+	  0x0448, /* CYRILLIC SMALL LETTER SHA */ }, \
+	{ 0x0429, /* CYRILLIC CAPITAL LETTER SHCHA */ \
+	  0x0449, /* CYRILLIC SMALL LETTER SHCHA */ }, \
+	{ 0x04BA, /* CYRILLIC CAPITAL LETTER SHHA */ \
+	  0x04BB, /* CYRILLIC SMALL LETTER SHHA */ }, \
+	{ 0x0526, /* CYRILLIC CAPITAL LETTER SHHA WITH DESCENDER */ \
+	  0x0527, /* CYRILLIC SMALL LETTER SHHA WITH DESCENDER */ }, \
+	{ 0x048A, /* CYRILLIC CAPITAL LETTER SHORT I WITH TAIL */ \
+	  0x048B, /* CYRILLIC SMALL LETTER SHORT I WITH TAIL */ }, \
+	{ 0x040E, /* CYRILLIC CAPITAL LETTER SHORT U */ \
+	  0x045E, /* CYRILLIC SMALL LETTER SHORT U */ }, \
+	{ 0xA696, /* CYRILLIC CAPITAL LETTER SHWE */ \
+	  0xA697, /* CYRILLIC SMALL LETTER SHWE */ }, \
+	{ 0xA662, /* CYRILLIC CAPITAL LETTER SOFT DE */ \
+	  0xA663, /* CYRILLIC SMALL LETTER SOFT DE */ }, \
+	{ 0xA664, /* CYRILLIC CAPITAL LETTER SOFT EL */ \
+	  0xA665, /* CYRILLIC SMALL LETTER SOFT EL */ }, \
+	{ 0xA666, /* CYRILLIC CAPITAL LETTER SOFT EM */ \
+	  0xA667, /* CYRILLIC SMALL LETTER SOFT EM */ }, \
+	{ 0x042C, /* CYRILLIC CAPITAL LETTER SOFT SIGN */ \
+	  0x044C, /* CYRILLIC SMALL LETTER SOFT SIGN */ }, \
+	{ 0x04AE, /* CYRILLIC CAPITAL LETTER STRAIGHT U */ \
+	  0x04AF, /* CYRILLIC SMALL LETTER STRAIGHT U */ }, \
+	{ 0x04B0, /* CYRILLIC CAPITAL LETTER STRAIGHT U WITH STROKE */ \
+	  0x04B1, /* CYRILLIC SMALL LETTER STRAIGHT U WITH STROKE */ }, \
+	{ 0xA692, /* CYRILLIC CAPITAL LETTER TCHE */ \
+	  0xA693, /* CYRILLIC SMALL LETTER TCHE */ }, \
+	{ 0x0422, /* CYRILLIC CAPITAL LETTER TE */ \
+	  0x0442, /* CYRILLIC SMALL LETTER TE */ }, \
+	{ 0x04AC, /* CYRILLIC CAPITAL LETTER TE WITH DESCENDER */ \
+	  0x04AD, /* CYRILLIC SMALL LETTER TE WITH DESCENDER */ }, \
+	{ 0xA68A, /* CYRILLIC CAPITAL LETTER TE WITH MIDDLE HOOK */ \
+	  0xA68B, /* CYRILLIC SMALL LETTER TE WITH MIDDLE HOOK */ }, \
+	{ 0x0426, /* CYRILLIC CAPITAL LETTER TSE */ \
+	  0x0446, /* CYRILLIC SMALL LETTER TSE */ }, \
+	{ 0x040B, /* CYRILLIC CAPITAL LETTER TSHE */ \
+	  0x045B, /* CYRILLIC SMALL LETTER TSHE */ }, \
+	{ 0xA690, /* CYRILLIC CAPITAL LETTER TSSE */ \
+	  0xA691, /* CYRILLIC SMALL LETTER TSSE */ }, \
+	{ 0xA68E, /* CYRILLIC CAPITAL LETTER TSWE */ \
+	  0xA68F, /* CYRILLIC SMALL LETTER TSWE */ }, \
+	{ 0xA68C, /* CYRILLIC CAPITAL LETTER TWE */ \
+	  0xA68D, /* CYRILLIC SMALL LETTER TWE */ }, \
+	{ 0x0423, /* CYRILLIC CAPITAL LETTER U */ \
+	  0x0443, /* CYRILLIC SMALL LETTER U */ }, \
+	{ 0x04F0, /* CYRILLIC CAPITAL LETTER U WITH DIAERESIS */ \
+	  0x04F1, /* CYRILLIC SMALL LETTER U WITH DIAERESIS */ }, \
+	{ 0x04F2, /* CYRILLIC CAPITAL LETTER U WITH DOUBLE ACUTE */ \
+	  0x04F3, /* CYRILLIC SMALL LETTER U WITH DOUBLE ACUTE */ }, \
+	{ 0x04EE, /* CYRILLIC CAPITAL LETTER U WITH MACRON */ \
+	  0x04EF, /* CYRILLIC SMALL LETTER U WITH MACRON */ }, \
+	{ 0x0478, /* CYRILLIC CAPITAL LETTER UK */ \
+	  0x0479, /* CYRILLIC SMALL LETTER UK */ }, \
+	{ 0x0404, /* CYRILLIC CAPITAL LETTER UKRAINIAN IE */ \
+	  0x0454, /* CYRILLIC SMALL LETTER UKRAINIAN IE */ }, \
+	{ 0x0412, /* CYRILLIC CAPITAL LETTER VE */ \
+	  0x0432, /* CYRILLIC SMALL LETTER VE */ }, \
+	{ 0x051C, /* CYRILLIC CAPITAL LETTER WE */ \
+	  0x051D, /* CYRILLIC SMALL LETTER WE */ }, \
+	{ 0x042F, /* CYRILLIC CAPITAL LETTER YA */ \
+	  0x044F, /* CYRILLIC SMALL LETTER YA */ }, \
+	{ 0x0518, /* CYRILLIC CAPITAL LETTER YAE */ \
+	  0x0519, /* CYRILLIC SMALL LETTER YAE */ }, \
+	{ 0x0462, /* CYRILLIC CAPITAL LETTER YAT */ \
+	  0x0463, /* CYRILLIC SMALL LETTER YAT */ }, \
+	{ 0x042B, /* CYRILLIC CAPITAL LETTER YERU */ \
+	  0x044B, /* CYRILLIC SMALL LETTER YERU */ }, \
+	{ 0xA650, /* CYRILLIC CAPITAL LETTER YERU WITH BACK YER */ \
+	  0xA651, /* CYRILLIC SMALL LETTER YERU WITH BACK YER */ }, \
+	{ 0x04F8, /* CYRILLIC CAPITAL LETTER YERU WITH DIAERESIS */ \
+	  0x04F9, /* CYRILLIC SMALL LETTER YERU WITH DIAERESIS */ }, \
+	{ 0x0407, /* CYRILLIC CAPITAL LETTER YI */ \
+	  0x0457, /* CYRILLIC SMALL LETTER YI */ }, \
+	{ 0xA65E, /* CYRILLIC CAPITAL LETTER YN */ \
+	  0xA65F, /* CYRILLIC SMALL LETTER YN */ }, \
+	{ 0x042E, /* CYRILLIC CAPITAL LETTER YU */ \
+	  0x044E, /* CYRILLIC SMALL LETTER YU */ }, \
+	{ 0x0417, /* CYRILLIC CAPITAL LETTER ZE */ \
+	  0x0437, /* CYRILLIC SMALL LETTER ZE */ }, \
+	{ 0x0498, /* CYRILLIC CAPITAL LETTER ZE WITH DESCENDER */ \
+	  0x0499, /* CYRILLIC SMALL LETTER ZE WITH DESCENDER */ }, \
+	{ 0x04DE, /* CYRILLIC CAPITAL LETTER ZE WITH DIAERESIS */ \
+	  0x04DF, /* CYRILLIC SMALL LETTER ZE WITH DIAERESIS */ }, \
+	{ 0xA640, /* CYRILLIC CAPITAL LETTER ZEMLYA */ \
+	  0xA641, /* CYRILLIC SMALL LETTER ZEMLYA */ }, \
+	{ 0x0416, /* CYRILLIC CAPITAL LETTER ZHE */ \
+	  0x0436, /* CYRILLIC SMALL LETTER ZHE */ }, \
+	{ 0x04C1, /* CYRILLIC CAPITAL LETTER ZHE WITH BREVE */ \
+	  0x04C2, /* CYRILLIC SMALL LETTER ZHE WITH BREVE */ }, \
+	{ 0x0496, /* CYRILLIC CAPITAL LETTER ZHE WITH DESCENDER */ \
+	  0x0497, /* CYRILLIC SMALL LETTER ZHE WITH DESCENDER */ }, \
+	{ 0x04DC, /* CYRILLIC CAPITAL LETTER ZHE WITH DIAERESIS */ \
+	  0x04DD, /* CYRILLIC SMALL LETTER ZHE WITH DIAERESIS */ }, \
+	{ 0xA684, /* CYRILLIC CAPITAL LETTER ZHWE */ \
+	  0xA685, /* CYRILLIC SMALL LETTER ZHWE */ }, \
+	{ 0xFF21, /* FULLWIDTH LATIN CAPITAL LETTER A */ \
+	  0xFF41, /* FULLWIDTH LATIN SMALL LETTER A */ }, \
+	{ 0xFF22, /* FULLWIDTH LATIN CAPITAL LETTER B */ \
+	  0xFF42, /* FULLWIDTH LATIN SMALL LETTER B */ }, \
+	{ 0xFF23, /* FULLWIDTH LATIN CAPITAL LETTER C */ \
+	  0xFF43, /* FULLWIDTH LATIN SMALL LETTER C */ }, \
+	{ 0xFF24, /* FULLWIDTH LATIN CAPITAL LETTER D */ \
+	  0xFF44, /* FULLWIDTH LATIN SMALL LETTER D */ }, \
+	{ 0xFF25, /* FULLWIDTH LATIN CAPITAL LETTER E */ \
+	  0xFF45, /* FULLWIDTH LATIN SMALL LETTER E */ }, \
+	{ 0xFF26, /* FULLWIDTH LATIN CAPITAL LETTER F */ \
+	  0xFF46, /* FULLWIDTH LATIN SMALL LETTER F */ }, \
+	{ 0xFF27, /* FULLWIDTH LATIN CAPITAL LETTER G */ \
+	  0xFF47, /* FULLWIDTH LATIN SMALL LETTER G */ }, \
+	{ 0xFF28, /* FULLWIDTH LATIN CAPITAL LETTER H */ \
+	  0xFF48, /* FULLWIDTH LATIN SMALL LETTER H */ }, \
+	{ 0xFF29, /* FULLWIDTH LATIN CAPITAL LETTER I */ \
+	  0xFF49, /* FULLWIDTH LATIN SMALL LETTER I */ }, \
+	{ 0xFF2A, /* FULLWIDTH LATIN CAPITAL LETTER J */ \
+	  0xFF4A, /* FULLWIDTH LATIN SMALL LETTER J */ }, \
+	{ 0xFF2B, /* FULLWIDTH LATIN CAPITAL LETTER K */ \
+	  0xFF4B, /* FULLWIDTH LATIN SMALL LETTER K */ }, \
+	{ 0xFF2C, /* FULLWIDTH LATIN CAPITAL LETTER L */ \
+	  0xFF4C, /* FULLWIDTH LATIN SMALL LETTER L */ }, \
+	{ 0xFF2D, /* FULLWIDTH LATIN CAPITAL LETTER M */ \
+	  0xFF4D, /* FULLWIDTH LATIN SMALL LETTER M */ }, \
+	{ 0xFF2E, /* FULLWIDTH LATIN CAPITAL LETTER N */ \
+	  0xFF4E, /* FULLWIDTH LATIN SMALL LETTER N */ }, \
+	{ 0xFF2F, /* FULLWIDTH LATIN CAPITAL LETTER O */ \
+	  0xFF4F, /* FULLWIDTH LATIN SMALL LETTER O */ }, \
+	{ 0xFF30, /* FULLWIDTH LATIN CAPITAL LETTER P */ \
+	  0xFF50, /* FULLWIDTH LATIN SMALL LETTER P */ }, \
+	{ 0xFF31, /* FULLWIDTH LATIN CAPITAL LETTER Q */ \
+	  0xFF51, /* FULLWIDTH LATIN SMALL LETTER Q */ }, \
+	{ 0xFF32, /* FULLWIDTH LATIN CAPITAL LETTER R */ \
+	  0xFF52, /* FULLWIDTH LATIN SMALL LETTER R */ }, \
+	{ 0xFF33, /* FULLWIDTH LATIN CAPITAL LETTER S */ \
+	  0xFF53, /* FULLWIDTH LATIN SMALL LETTER S */ }, \
+	{ 0xFF34, /* FULLWIDTH LATIN CAPITAL LETTER T */ \
+	  0xFF54, /* FULLWIDTH LATIN SMALL LETTER T */ }, \
+	{ 0xFF35, /* FULLWIDTH LATIN CAPITAL LETTER U */ \
+	  0xFF55, /* FULLWIDTH LATIN SMALL LETTER U */ }, \
+	{ 0xFF36, /* FULLWIDTH LATIN CAPITAL LETTER V */ \
+	  0xFF56, /* FULLWIDTH LATIN SMALL LETTER V */ }, \
+	{ 0xFF37, /* FULLWIDTH LATIN CAPITAL LETTER W */ \
+	  0xFF57, /* FULLWIDTH LATIN SMALL LETTER W */ }, \
+	{ 0xFF38, /* FULLWIDTH LATIN CAPITAL LETTER X */ \
+	  0xFF58, /* FULLWIDTH LATIN SMALL LETTER X */ }, \
+	{ 0xFF39, /* FULLWIDTH LATIN CAPITAL LETTER Y */ \
+	  0xFF59, /* FULLWIDTH LATIN SMALL LETTER Y */ }, \
+	{ 0xFF3A, /* FULLWIDTH LATIN CAPITAL LETTER Z */ \
+	  0xFF5A, /* FULLWIDTH LATIN SMALL LETTER Z */ }, \
+	{ 0x10CD, /* GEORGIAN CAPITAL LETTER AEN */ \
+	  0x2D2D, /* GEORGIAN SMALL LETTER AEN */ }, \
+	{ 0x10A0, /* GEORGIAN CAPITAL LETTER AN */ \
+	  0x2D00, /* GEORGIAN SMALL LETTER AN */ }, \
+	{ 0x10A1, /* GEORGIAN CAPITAL LETTER BAN */ \
+	  0x2D01, /* GEORGIAN SMALL LETTER BAN */ }, \
+	{ 0x10BA, /* GEORGIAN CAPITAL LETTER CAN */ \
+	  0x2D1A, /* GEORGIAN SMALL LETTER CAN */ }, \
+	{ 0x10BD, /* GEORGIAN CAPITAL LETTER CHAR */ \
+	  0x2D1D, /* GEORGIAN SMALL LETTER CHAR */ }, \
+	{ 0x10B9, /* GEORGIAN CAPITAL LETTER CHIN */ \
+	  0x2D19, /* GEORGIAN SMALL LETTER CHIN */ }, \
+	{ 0x10BC, /* GEORGIAN CAPITAL LETTER CIL */ \
+	  0x2D1C, /* GEORGIAN SMALL LETTER CIL */ }, \
+	{ 0x10A3, /* GEORGIAN CAPITAL LETTER DON */ \
+	  0x2D03, /* GEORGIAN SMALL LETTER DON */ }, \
+	{ 0x10A4, /* GEORGIAN CAPITAL LETTER EN */ \
+	  0x2D04, /* GEORGIAN SMALL LETTER EN */ }, \
+	{ 0x10A2, /* GEORGIAN CAPITAL LETTER GAN */ \
+	  0x2D02, /* GEORGIAN SMALL LETTER GAN */ }, \
+	{ 0x10B6, /* GEORGIAN CAPITAL LETTER GHAN */ \
+	  0x2D16, /* GEORGIAN SMALL LETTER GHAN */ }, \
+	{ 0x10C0, /* GEORGIAN CAPITAL LETTER HAE */ \
+	  0x2D20, /* GEORGIAN SMALL LETTER HAE */ }, \
+	{ 0x10C4, /* GEORGIAN CAPITAL LETTER HAR */ \
+	  0x2D24, /* GEORGIAN SMALL LETTER HAR */ }, \
+	{ 0x10C1, /* GEORGIAN CAPITAL LETTER HE */ \
+	  0x2D21, /* GEORGIAN SMALL LETTER HE */ }, \
+	{ 0x10C2, /* GEORGIAN CAPITAL LETTER HIE */ \
+	  0x2D22, /* GEORGIAN SMALL LETTER HIE */ }, \
+	{ 0x10C5, /* GEORGIAN CAPITAL LETTER HOE */ \
+	  0x2D25, /* GEORGIAN SMALL LETTER HOE */ }, \
+	{ 0x10A8, /* GEORGIAN CAPITAL LETTER IN */ \
+	  0x2D08, /* GEORGIAN SMALL LETTER IN */ }, \
+	{ 0x10BF, /* GEORGIAN CAPITAL LETTER JHAN */ \
+	  0x2D1F, /* GEORGIAN SMALL LETTER JHAN */ }, \
+	{ 0x10BB, /* GEORGIAN CAPITAL LETTER JIL */ \
+	  0x2D1B, /* GEORGIAN SMALL LETTER JIL */ }, \
+	{ 0x10A9, /* GEORGIAN CAPITAL LETTER KAN */ \
+	  0x2D09, /* GEORGIAN SMALL LETTER KAN */ }, \
+	{ 0x10B5, /* GEORGIAN CAPITAL LETTER KHAR */ \
+	  0x2D15, /* GEORGIAN SMALL LETTER KHAR */ }, \
+	{ 0x10AA, /* GEORGIAN CAPITAL LETTER LAS */ \
+	  0x2D0A, /* GEORGIAN SMALL LETTER LAS */ }, \
+	{ 0x10AB, /* GEORGIAN CAPITAL LETTER MAN */ \
+	  0x2D0B, /* GEORGIAN SMALL LETTER MAN */ }, \
+	{ 0x10AC, /* GEORGIAN CAPITAL LETTER NAR */ \
+	  0x2D0C, /* GEORGIAN SMALL LETTER NAR */ }, \
+	{ 0x10AD, /* GEORGIAN CAPITAL LETTER ON */ \
+	  0x2D0D, /* GEORGIAN SMALL LETTER ON */ }, \
+	{ 0x10AE, /* GEORGIAN CAPITAL LETTER PAR */ \
+	  0x2D0E, /* GEORGIAN SMALL LETTER PAR */ }, \
+	{ 0x10B4, /* GEORGIAN CAPITAL LETTER PHAR */ \
+	  0x2D14, /* GEORGIAN SMALL LETTER PHAR */ }, \
+	{ 0x10B7, /* GEORGIAN CAPITAL LETTER QAR */ \
+	  0x2D17, /* GEORGIAN SMALL LETTER QAR */ }, \
+	{ 0x10B0, /* GEORGIAN CAPITAL LETTER RAE */ \
+	  0x2D10, /* GEORGIAN SMALL LETTER RAE */ }, \
+	{ 0x10B1, /* GEORGIAN CAPITAL LETTER SAN */ \
+	  0x2D11, /* GEORGIAN SMALL LETTER SAN */ }, \
+	{ 0x10B8, /* GEORGIAN CAPITAL LETTER SHIN */ \
+	  0x2D18, /* GEORGIAN SMALL LETTER SHIN */ }, \
+	{ 0x10A7, /* GEORGIAN CAPITAL LETTER TAN */ \
+	  0x2D07, /* GEORGIAN SMALL LETTER TAN */ }, \
+	{ 0x10B2, /* GEORGIAN CAPITAL LETTER TAR */ \
+	  0x2D12, /* GEORGIAN SMALL LETTER TAR */ }, \
+	{ 0x10B3, /* GEORGIAN CAPITAL LETTER UN */ \
+	  0x2D13, /* GEORGIAN SMALL LETTER UN */ }, \
+	{ 0x10A5, /* GEORGIAN CAPITAL LETTER VIN */ \
+	  0x2D05, /* GEORGIAN SMALL LETTER VIN */ }, \
+	{ 0x10C3, /* GEORGIAN CAPITAL LETTER WE */ \
+	  0x2D23, /* GEORGIAN SMALL LETTER WE */ }, \
+	{ 0x10BE, /* GEORGIAN CAPITAL LETTER XAN */ \
+	  0x2D1E, /* GEORGIAN SMALL LETTER XAN */ }, \
+	{ 0x10C7, /* GEORGIAN CAPITAL LETTER YN */ \
+	  0x2D27, /* GEORGIAN SMALL LETTER YN */ }, \
+	{ 0x10A6, /* GEORGIAN CAPITAL LETTER ZEN */ \
+	  0x2D06, /* GEORGIAN SMALL LETTER ZEN */ }, \
+	{ 0x10AF, /* GEORGIAN CAPITAL LETTER ZHAR */ \
+	  0x2D0F, /* GEORGIAN SMALL LETTER ZHAR */ }, \
+	{ 0x2C00, /* GLAGOLITIC CAPITAL LETTER AZU */ \
+	  0x2C30, /* GLAGOLITIC SMALL LETTER AZU */ }, \
+	{ 0x2C28, /* GLAGOLITIC CAPITAL LETTER BIG YUS */ \
+	  0x2C58, /* GLAGOLITIC SMALL LETTER BIG YUS */ }, \
+	{ 0x2C01, /* GLAGOLITIC CAPITAL LETTER BUKY */ \
+	  0x2C31, /* GLAGOLITIC SMALL LETTER BUKY */ }, \
+	{ 0x2C1D, /* GLAGOLITIC CAPITAL LETTER CHRIVI */ \
+	  0x2C4D, /* GLAGOLITIC SMALL LETTER CHRIVI */ }, \
+	{ 0x2C0C, /* GLAGOLITIC CAPITAL LETTER DJERVI */ \
+	  0x2C3C, /* GLAGOLITIC SMALL LETTER DJERVI */ }, \
+	{ 0x2C04, /* GLAGOLITIC CAPITAL LETTER DOBRO */ \
+	  0x2C34, /* GLAGOLITIC SMALL LETTER DOBRO */ }, \
+	{ 0x2C07, /* GLAGOLITIC CAPITAL LETTER DZELO */ \
+	  0x2C37, /* GLAGOLITIC SMALL LETTER DZELO */ }, \
+	{ 0x2C2A, /* GLAGOLITIC CAPITAL LETTER FITA */ \
+	  0x2C5A, /* GLAGOLITIC SMALL LETTER FITA */ }, \
+	{ 0x2C17, /* GLAGOLITIC CAPITAL LETTER FRITU */ \
+	  0x2C47, /* GLAGOLITIC SMALL LETTER FRITU */ }, \
+	{ 0x2C03, /* GLAGOLITIC CAPITAL LETTER GLAGOLI */ \
+	  0x2C33, /* GLAGOLITIC SMALL LETTER GLAGOLI */ }, \
+	{ 0x2C18, /* GLAGOLITIC CAPITAL LETTER HERU */ \
+	  0x2C48, /* GLAGOLITIC SMALL LETTER HERU */ }, \
+	{ 0x2C0B, /* GLAGOLITIC CAPITAL LETTER I */ \
+	  0x2C3B, /* GLAGOLITIC SMALL LETTER I */ }, \
+	{ 0x2C0A, /* GLAGOLITIC CAPITAL LETTER INITIAL IZHE */ \
+	  0x2C3A, /* GLAGOLITIC SMALL LETTER INITIAL IZHE */ }, \
+	{ 0x2C29, /* GLAGOLITIC CAPITAL LETTER IOTATED BIG YUS */ \
+	  0x2C59, /* GLAGOLITIC SMALL LETTER IOTATED BIG YUS */ }, \
+	{ 0x2C27, /* GLAGOLITIC CAPITAL LETTER IOTATED SMALL YUS */ \
+	  0x2C57, /* GLAGOLITIC SMALL LETTER IOTATED SMALL YUS */ }, \
+	{ 0x2C09, /* GLAGOLITIC CAPITAL LETTER IZHE */ \
+	  0x2C39, /* GLAGOLITIC SMALL LETTER IZHE */ }, \
+	{ 0x2C2B, /* GLAGOLITIC CAPITAL LETTER IZHITSA */ \
+	  0x2C5B, /* GLAGOLITIC SMALL LETTER IZHITSA */ }, \
+	{ 0x2C0D, /* GLAGOLITIC CAPITAL LETTER KAKO */ \
+	  0x2C3D, /* GLAGOLITIC SMALL LETTER KAKO */ }, \
+	{ 0x2C2E, /* GLAGOLITIC CAPITAL LETTER LATINATE MYSLITE */ \
+	  0x2C5E, /* GLAGOLITIC SMALL LETTER LATINATE MYSLITE */ }, \
+	{ 0x2C0E, /* GLAGOLITIC CAPITAL LETTER LJUDIJE */ \
+	  0x2C3E, /* GLAGOLITIC SMALL LETTER LJUDIJE */ }, \
+	{ 0x2C0F, /* GLAGOLITIC CAPITAL LETTER MYSLITE */ \
+	  0x2C3F, /* GLAGOLITIC SMALL LETTER MYSLITE */ }, \
+	{ 0x2C10, /* GLAGOLITIC CAPITAL LETTER NASHI */ \
+	  0x2C40, /* GLAGOLITIC SMALL LETTER NASHI */ }, \
+	{ 0x2C11, /* GLAGOLITIC CAPITAL LETTER ONU */ \
+	  0x2C41, /* GLAGOLITIC SMALL LETTER ONU */ }, \
+	{ 0x2C19, /* GLAGOLITIC CAPITAL LETTER OTU */ \
+	  0x2C49, /* GLAGOLITIC SMALL LETTER OTU */ }, \
+	{ 0x2C1A, /* GLAGOLITIC CAPITAL LETTER PE */ \
+	  0x2C4A, /* GLAGOLITIC SMALL LETTER PE */ }, \
+	{ 0x2C12, /* GLAGOLITIC CAPITAL LETTER POKOJI */ \
+	  0x2C42, /* GLAGOLITIC SMALL LETTER POKOJI */ }, \
+	{ 0x2C13, /* GLAGOLITIC CAPITAL LETTER RITSI */ \
+	  0x2C43, /* GLAGOLITIC SMALL LETTER RITSI */ }, \
+	{ 0x2C1E, /* GLAGOLITIC CAPITAL LETTER SHA */ \
+	  0x2C4E, /* GLAGOLITIC SMALL LETTER SHA */ }, \
+	{ 0x2C1B, /* GLAGOLITIC CAPITAL LETTER SHTA */ \
+	  0x2C4B, /* GLAGOLITIC SMALL LETTER SHTA */ }, \
+	{ 0x2C2C, /* GLAGOLITIC CAPITAL LETTER SHTAPIC */ \
+	  0x2C5C, /* GLAGOLITIC SMALL LETTER SHTAPIC */ }, \
+	{ 0x2C14, /* GLAGOLITIC CAPITAL LETTER SLOVO */ \
+	  0x2C44, /* GLAGOLITIC SMALL LETTER SLOVO */ }, \
+	{ 0x2C24, /* GLAGOLITIC CAPITAL LETTER SMALL YUS */ \
+	  0x2C54, /* GLAGOLITIC SMALL LETTER SMALL YUS */ }, \
+	{ 0x2C25, /* GLAGOLITIC CAPITAL LETTER SMALL YUS WITH TAIL */ \
+	  0x2C55, /* GLAGOLITIC SMALL LETTER SMALL YUS WITH TAIL */ }, \
+	{ 0x2C22, /* GLAGOLITIC CAPITAL LETTER SPIDERY HA */ \
+	  0x2C52, /* GLAGOLITIC SMALL LETTER SPIDERY HA */ }, \
+	{ 0x2C2D, /* GLAGOLITIC CAPITAL LETTER TROKUTASTI A */ \
+	  0x2C5D, /* GLAGOLITIC SMALL LETTER TROKUTASTI A */ }, \
+	{ 0x2C1C, /* GLAGOLITIC CAPITAL LETTER TSI */ \
+	  0x2C4C, /* GLAGOLITIC SMALL LETTER TSI */ }, \
+	{ 0x2C15, /* GLAGOLITIC CAPITAL LETTER TVRIDO */ \
+	  0x2C45, /* GLAGOLITIC SMALL LETTER TVRIDO */ }, \
+	{ 0x2C16, /* GLAGOLITIC CAPITAL LETTER UKU */ \
+	  0x2C46, /* GLAGOLITIC SMALL LETTER UKU */ }, \
+	{ 0x2C02, /* GLAGOLITIC CAPITAL LETTER VEDE */ \
+	  0x2C32, /* GLAGOLITIC SMALL LETTER VEDE */ }, \
+	{ 0x2C21, /* GLAGOLITIC CAPITAL LETTER YATI */ \
+	  0x2C51, /* GLAGOLITIC SMALL LETTER YATI */ }, \
+	{ 0x2C20, /* GLAGOLITIC CAPITAL LETTER YERI */ \
+	  0x2C50, /* GLAGOLITIC SMALL LETTER YERI */ }, \
+	{ 0x2C1F, /* GLAGOLITIC CAPITAL LETTER YERU */ \
+	  0x2C4F, /* GLAGOLITIC SMALL LETTER YERU */ }, \
+	{ 0x2C05, /* GLAGOLITIC CAPITAL LETTER YESTU */ \
+	  0x2C35, /* GLAGOLITIC SMALL LETTER YESTU */ }, \
+	{ 0x2C26, /* GLAGOLITIC CAPITAL LETTER YO */ \
+	  0x2C56, /* GLAGOLITIC SMALL LETTER YO */ }, \
+	{ 0x2C23, /* GLAGOLITIC CAPITAL LETTER YU */ \
+	  0x2C53, /* GLAGOLITIC SMALL LETTER YU */ }, \
+	{ 0x2C08, /* GLAGOLITIC CAPITAL LETTER ZEMLJA */ \
+	  0x2C38, /* GLAGOLITIC SMALL LETTER ZEMLJA */ }, \
+	{ 0x2C06, /* GLAGOLITIC CAPITAL LETTER ZHIVETE */ \
+	  0x2C36, /* GLAGOLITIC SMALL LETTER ZHIVETE */ }, \
+	{ 0x0391, /* GREEK CAPITAL LETTER ALPHA */ \
+	  0x03B1, /* GREEK SMALL LETTER ALPHA */ }, \
+	{ 0x1F09, /* GREEK CAPITAL LETTER ALPHA WITH DASIA */ \
+	  0x1F01, /* GREEK SMALL LETTER ALPHA WITH DASIA */ }, \
+	{ 0x1F0D, /* GREEK CAPITAL LETTER ALPHA WITH DASIA AND OXIA */ \
+	  0x1F05, /* GREEK SMALL LETTER ALPHA WITH DASIA AND OXIA */ }, \
+	{ 0x1F0F, /* GREEK CAPITAL LETTER ALPHA WITH DASIA AND PERISPOMENI */ \
+	  0x1F07, /* GREEK SMALL LETTER ALPHA WITH DASIA AND PERISPOMENI */ }, \
+	{ 0x1F0B, /* GREEK CAPITAL LETTER ALPHA WITH DASIA AND VARIA */ \
+	  0x1F03, /* GREEK SMALL LETTER ALPHA WITH DASIA AND VARIA */ }, \
+	{ 0x1FB9, /* GREEK CAPITAL LETTER ALPHA WITH MACRON */ \
+	  0x1FB1, /* GREEK SMALL LETTER ALPHA WITH MACRON */ }, \
+	{ 0x1FBB, /* GREEK CAPITAL LETTER ALPHA WITH OXIA */ \
+	  0x1F71, /* GREEK SMALL LETTER ALPHA WITH OXIA */ }, \
+	{ 0x1F08, /* GREEK CAPITAL LETTER ALPHA WITH PSILI */ \
+	  0x1F00, /* GREEK SMALL LETTER ALPHA WITH PSILI */ }, \
+	{ 0x1F0C, /* GREEK CAPITAL LETTER ALPHA WITH PSILI AND OXIA */ \
+	  0x1F04, /* GREEK SMALL LETTER ALPHA WITH PSILI AND OXIA */ }, \
+	{ 0x1F0E, /* GREEK CAPITAL LETTER ALPHA WITH PSILI AND PERISPOMENI */ \
+	  0x1F06, /* GREEK SMALL LETTER ALPHA WITH PSILI AND PERISPOMENI */ }, \
+	{ 0x1F0A, /* GREEK CAPITAL LETTER ALPHA WITH PSILI AND VARIA */ \
+	  0x1F02, /* GREEK SMALL LETTER ALPHA WITH PSILI AND VARIA */ }, \
+	{ 0x0386, /* GREEK CAPITAL LETTER ALPHA WITH TONOS */ \
+	  0x03AC, /* GREEK SMALL LETTER ALPHA WITH TONOS */ }, \
+	{ 0x1FBA, /* GREEK CAPITAL LETTER ALPHA WITH VARIA */ \
+	  0x1F70, /* GREEK SMALL LETTER ALPHA WITH VARIA */ }, \
+	{ 0x1FB8, /* GREEK CAPITAL LETTER ALPHA WITH VRACHY */ \
+	  0x1FB0, /* GREEK SMALL LETTER ALPHA WITH VRACHY */ }, \
+	{ 0x0372, /* GREEK CAPITAL LETTER ARCHAIC SAMPI */ \
+	  0x0373, /* GREEK SMALL LETTER ARCHAIC SAMPI */ }, \
+	{ 0x0392, /* GREEK CAPITAL LETTER BETA */ \
+	  0x03B2, /* GREEK SMALL LETTER BETA */ }, \
+	{ 0x03A7, /* GREEK CAPITAL LETTER CHI */ \
+	  0x03C7, /* GREEK SMALL LETTER CHI */ }, \
+	{ 0x0394, /* GREEK CAPITAL LETTER DELTA */ \
+	  0x03B4, /* GREEK SMALL LETTER DELTA */ }, \
+	{ 0x0395, /* GREEK CAPITAL LETTER EPSILON */ \
+	  0x03B5, /* GREEK SMALL LETTER EPSILON */ }, \
+	{ 0x1F19, /* GREEK CAPITAL LETTER EPSILON WITH DASIA */ \
+	  0x1F11, /* GREEK SMALL LETTER EPSILON WITH DASIA */ }, \
+	{ 0x1F1D, /* GREEK CAPITAL LETTER EPSILON WITH DASIA AND OXIA */ \
+	  0x1F15, /* GREEK SMALL LETTER EPSILON WITH DASIA AND OXIA */ }, \
+	{ 0x1F1B, /* GREEK CAPITAL LETTER EPSILON WITH DASIA AND VARIA */ \
+	  0x1F13, /* GREEK SMALL LETTER EPSILON WITH DASIA AND VARIA */ }, \
+	{ 0x1FC9, /* GREEK CAPITAL LETTER EPSILON WITH OXIA */ \
+	  0x1F73, /* GREEK SMALL LETTER EPSILON WITH OXIA */ }, \
+	{ 0x1F18, /* GREEK CAPITAL LETTER EPSILON WITH PSILI */ \
+	  0x1F10, /* GREEK SMALL LETTER EPSILON WITH PSILI */ }, \
+	{ 0x1F1C, /* GREEK CAPITAL LETTER EPSILON WITH PSILI AND OXIA */ \
+	  0x1F14, /* GREEK SMALL LETTER EPSILON WITH PSILI AND OXIA */ }, \
+	{ 0x1F1A, /* GREEK CAPITAL LETTER EPSILON WITH PSILI AND VARIA */ \
+	  0x1F12, /* GREEK SMALL LETTER EPSILON WITH PSILI AND VARIA */ }, \
+	{ 0x0388, /* GREEK CAPITAL LETTER EPSILON WITH TONOS */ \
+	  0x03AD, /* GREEK SMALL LETTER EPSILON WITH TONOS */ }, \
+	{ 0x1FC8, /* GREEK CAPITAL LETTER EPSILON WITH VARIA */ \
+	  0x1F72, /* GREEK SMALL LETTER EPSILON WITH VARIA */ }, \
+	{ 0x0397, /* GREEK CAPITAL LETTER ETA */ \
+	  0x03B7, /* GREEK SMALL LETTER ETA */ }, \
+	{ 0x1F29, /* GREEK CAPITAL LETTER ETA WITH DASIA */ \
+	  0x1F21, /* GREEK SMALL LETTER ETA WITH DASIA */ }, \
+	{ 0x1F2D, /* GREEK CAPITAL LETTER ETA WITH DASIA AND OXIA */ \
+	  0x1F25, /* GREEK SMALL LETTER ETA WITH DASIA AND OXIA */ }, \
+	{ 0x1F2F, /* GREEK CAPITAL LETTER ETA WITH DASIA AND PERISPOMENI */ \
+	  0x1F27, /* GREEK SMALL LETTER ETA WITH DASIA AND PERISPOMENI */ }, \
+	{ 0x1F2B, /* GREEK CAPITAL LETTER ETA WITH DASIA AND VARIA */ \
+	  0x1F23, /* GREEK SMALL LETTER ETA WITH DASIA AND VARIA */ }, \
+	{ 0x1FCB, /* GREEK CAPITAL LETTER ETA WITH OXIA */ \
+	  0x1F75, /* GREEK SMALL LETTER ETA WITH OXIA */ }, \
+	{ 0x1F28, /* GREEK CAPITAL LETTER ETA WITH PSILI */ \
+	  0x1F20, /* GREEK SMALL LETTER ETA WITH PSILI */ }, \
+	{ 0x1F2C, /* GREEK CAPITAL LETTER ETA WITH PSILI AND OXIA */ \
+	  0x1F24, /* GREEK SMALL LETTER ETA WITH PSILI AND OXIA */ }, \
+	{ 0x1F2E, /* GREEK CAPITAL LETTER ETA WITH PSILI AND PERISPOMENI */ \
+	  0x1F26, /* GREEK SMALL LETTER ETA WITH PSILI AND PERISPOMENI */ }, \
+	{ 0x1F2A, /* GREEK CAPITAL LETTER ETA WITH PSILI AND VARIA */ \
+	  0x1F22, /* GREEK SMALL LETTER ETA WITH PSILI AND VARIA */ }, \
+	{ 0x0389, /* GREEK CAPITAL LETTER ETA WITH TONOS */ \
+	  0x03AE, /* GREEK SMALL LETTER ETA WITH TONOS */ }, \
+	{ 0x1FCA, /* GREEK CAPITAL LETTER ETA WITH VARIA */ \
+	  0x1F74, /* GREEK SMALL LETTER ETA WITH VARIA */ }, \
+	{ 0x0393, /* GREEK CAPITAL LETTER GAMMA */ \
+	  0x03B3, /* GREEK SMALL LETTER GAMMA */ }, \
+	{ 0x0370, /* GREEK CAPITAL LETTER HETA */ \
+	  0x0371, /* GREEK SMALL LETTER HETA */ }, \
+	{ 0x0399, /* GREEK CAPITAL LETTER IOTA */ \
+	  0x03B9, /* GREEK SMALL LETTER IOTA */ }, \
+	{ 0x1F39, /* GREEK CAPITAL LETTER IOTA WITH DASIA */ \
+	  0x1F31, /* GREEK SMALL LETTER IOTA WITH DASIA */ }, \
+	{ 0x1F3D, /* GREEK CAPITAL LETTER IOTA WITH DASIA AND OXIA */ \
+	  0x1F35, /* GREEK SMALL LETTER IOTA WITH DASIA AND OXIA */ }, \
+	{ 0x1F3F, /* GREEK CAPITAL LETTER IOTA WITH DASIA AND PERISPOMENI */ \
+	  0x1F37, /* GREEK SMALL LETTER IOTA WITH DASIA AND PERISPOMENI */ }, \
+	{ 0x1F3B, /* GREEK CAPITAL LETTER IOTA WITH DASIA AND VARIA */ \
+	  0x1F33, /* GREEK SMALL LETTER IOTA WITH DASIA AND VARIA */ }, \
+	{ 0x03AA, /* GREEK CAPITAL LETTER IOTA WITH DIALYTIKA */ \
+	  0x03CA, /* GREEK SMALL LETTER IOTA WITH DIALYTIKA */ }, \
+	{ 0x1FD9, /* GREEK CAPITAL LETTER IOTA WITH MACRON */ \
+	  0x1FD1, /* GREEK SMALL LETTER IOTA WITH MACRON */ }, \
+	{ 0x1FDB, /* GREEK CAPITAL LETTER IOTA WITH OXIA */ \
+	  0x1F77, /* GREEK SMALL LETTER IOTA WITH OXIA */ }, \
+	{ 0x1F38, /* GREEK CAPITAL LETTER IOTA WITH PSILI */ \
+	  0x1F30, /* GREEK SMALL LETTER IOTA WITH PSILI */ }, \
+	{ 0x1F3C, /* GREEK CAPITAL LETTER IOTA WITH PSILI AND OXIA */ \
+	  0x1F34, /* GREEK SMALL LETTER IOTA WITH PSILI AND OXIA */ }, \
+	{ 0x1F3E, /* GREEK CAPITAL LETTER IOTA WITH PSILI AND PERISPOMENI */ \
+	  0x1F36, /* GREEK SMALL LETTER IOTA WITH PSILI AND PERISPOMENI */ }, \
+	{ 0x1F3A, /* GREEK CAPITAL LETTER IOTA WITH PSILI AND VARIA */ \
+	  0x1F32, /* GREEK SMALL LETTER IOTA WITH PSILI AND VARIA */ }, \
+	{ 0x038A, /* GREEK CAPITAL LETTER IOTA WITH TONOS */ \
+	  0x03AF, /* GREEK SMALL LETTER IOTA WITH TONOS */ }, \
+	{ 0x1FDA, /* GREEK CAPITAL LETTER IOTA WITH VARIA */ \
+	  0x1F76, /* GREEK SMALL LETTER IOTA WITH VARIA */ }, \
+	{ 0x1FD8, /* GREEK CAPITAL LETTER IOTA WITH VRACHY */ \
+	  0x1FD0, /* GREEK SMALL LETTER IOTA WITH VRACHY */ }, \
+	{ 0x039A, /* GREEK CAPITAL LETTER KAPPA */ \
+	  0x03BA, /* GREEK SMALL LETTER KAPPA */ }, \
+	{ 0x039B, /* GREEK CAPITAL LETTER LAMDA */ \
+	  0x03BB, /* GREEK SMALL LETTER LAMDA */ }, \
+	{ 0x039C, /* GREEK CAPITAL LETTER MU */ \
+	  0x03BC, /* GREEK SMALL LETTER MU */ }, \
+	{ 0x039D, /* GREEK CAPITAL LETTER NU */ \
+	  0x03BD, /* GREEK SMALL LETTER NU */ }, \
+	{ 0x03A9, /* GREEK CAPITAL LETTER OMEGA */ \
+	  0x03C9, /* GREEK SMALL LETTER OMEGA */ }, \
+	{ 0x1F69, /* GREEK CAPITAL LETTER OMEGA WITH DASIA */ \
+	  0x1F61, /* GREEK SMALL LETTER OMEGA WITH DASIA */ }, \
+	{ 0x1F6D, /* GREEK CAPITAL LETTER OMEGA WITH DASIA AND OXIA */ \
+	  0x1F65, /* GREEK SMALL LETTER OMEGA WITH DASIA AND OXIA */ }, \
+	{ 0x1F6F, /* GREEK CAPITAL LETTER OMEGA WITH DASIA AND PERISPOMENI */ \
+	  0x1F67, /* GREEK SMALL LETTER OMEGA WITH DASIA AND PERISPOMENI */ }, \
+	{ 0x1F6B, /* GREEK CAPITAL LETTER OMEGA WITH DASIA AND VARIA */ \
+	  0x1F63, /* GREEK SMALL LETTER OMEGA WITH DASIA AND VARIA */ }, \
+	{ 0x1FFB, /* GREEK CAPITAL LETTER OMEGA WITH OXIA */ \
+	  0x1F7D, /* GREEK SMALL LETTER OMEGA WITH OXIA */ }, \
+	{ 0x1F68, /* GREEK CAPITAL LETTER OMEGA WITH PSILI */ \
+	  0x1F60, /* GREEK SMALL LETTER OMEGA WITH PSILI */ }, \
+	{ 0x1F6C, /* GREEK CAPITAL LETTER OMEGA WITH PSILI AND OXIA */ \
+	  0x1F64, /* GREEK SMALL LETTER OMEGA WITH PSILI AND OXIA */ }, \
+	{ 0x1F6E, /* GREEK CAPITAL LETTER OMEGA WITH PSILI AND PERISPOMENI */ \
+	  0x1F66, /* GREEK SMALL LETTER OMEGA WITH PSILI AND PERISPOMENI */ }, \
+	{ 0x1F6A, /* GREEK CAPITAL LETTER OMEGA WITH PSILI AND VARIA */ \
+	  0x1F62, /* GREEK SMALL LETTER OMEGA WITH PSILI AND VARIA */ }, \
+	{ 0x038F, /* GREEK CAPITAL LETTER OMEGA WITH TONOS */ \
+	  0x03CE, /* GREEK SMALL LETTER OMEGA WITH TONOS */ }, \
+	{ 0x1FFA, /* GREEK CAPITAL LETTER OMEGA WITH VARIA */ \
+	  0x1F7C, /* GREEK SMALL LETTER OMEGA WITH VARIA */ }, \
+	{ 0x039F, /* GREEK CAPITAL LETTER OMICRON */ \
+	  0x03BF, /* GREEK SMALL LETTER OMICRON */ }, \
+	{ 0x1F49, /* GREEK CAPITAL LETTER OMICRON WITH DASIA */ \
+	  0x1F41, /* GREEK SMALL LETTER OMICRON WITH DASIA */ }, \
+	{ 0x1F4D, /* GREEK CAPITAL LETTER OMICRON WITH DASIA AND OXIA */ \
+	  0x1F45, /* GREEK SMALL LETTER OMICRON WITH DASIA AND OXIA */ }, \
+	{ 0x1F4B, /* GREEK CAPITAL LETTER OMICRON WITH DASIA AND VARIA */ \
+	  0x1F43, /* GREEK SMALL LETTER OMICRON WITH DASIA AND VARIA */ }, \
+	{ 0x1FF9, /* GREEK CAPITAL LETTER OMICRON WITH OXIA */ \
+	  0x1F79, /* GREEK SMALL LETTER OMICRON WITH OXIA */ }, \
+	{ 0x1F48, /* GREEK CAPITAL LETTER OMICRON WITH PSILI */ \
+	  0x1F40, /* GREEK SMALL LETTER OMICRON WITH PSILI */ }, \
+	{ 0x1F4C, /* GREEK CAPITAL LETTER OMICRON WITH PSILI AND OXIA */ \
+	  0x1F44, /* GREEK SMALL LETTER OMICRON WITH PSILI AND OXIA */ }, \
+	{ 0x1F4A, /* GREEK CAPITAL LETTER OMICRON WITH PSILI AND VARIA */ \
+	  0x1F42, /* GREEK SMALL LETTER OMICRON WITH PSILI AND VARIA */ }, \
+	{ 0x038C, /* GREEK CAPITAL LETTER OMICRON WITH TONOS */ \
+	  0x03CC, /* GREEK SMALL LETTER OMICRON WITH TONOS */ }, \
+	{ 0x1FF8, /* GREEK CAPITAL LETTER OMICRON WITH VARIA */ \
+	  0x1F78, /* GREEK SMALL LETTER OMICRON WITH VARIA */ }, \
+	{ 0x0376, /* GREEK CAPITAL LETTER PAMPHYLIAN DIGAMMA */ \
+	  0x0377, /* GREEK SMALL LETTER PAMPHYLIAN DIGAMMA */ }, \
+	{ 0x03A6, /* GREEK CAPITAL LETTER PHI */ \
+	  0x03C6, /* GREEK SMALL LETTER PHI */ }, \
+	{ 0x03A0, /* GREEK CAPITAL LETTER PI */ \
+	  0x03C0, /* GREEK SMALL LETTER PI */ }, \
+	{ 0x03A8, /* GREEK CAPITAL LETTER PSI */ \
+	  0x03C8, /* GREEK SMALL LETTER PSI */ }, \
+	{ 0x03A1, /* GREEK CAPITAL LETTER RHO */ \
+	  0x03C1, /* GREEK SMALL LETTER RHO */ }, \
+	{ 0x1FEC, /* GREEK CAPITAL LETTER RHO WITH DASIA */ \
+	  0x1FE5, /* GREEK SMALL LETTER RHO WITH DASIA */ }, \
+	{ 0x03FA, /* GREEK CAPITAL LETTER SAN */ \
+	  0x03FB, /* GREEK SMALL LETTER SAN */ }, \
+	{ 0x03F7, /* GREEK CAPITAL LETTER SHO */ \
+	  0x03F8, /* GREEK SMALL LETTER SHO */ }, \
+	{ 0x03A3, /* GREEK CAPITAL LETTER SIGMA */ \
+	  0x03C3, /* GREEK SMALL LETTER SIGMA */ }, \
+	{ 0x03A4, /* GREEK CAPITAL LETTER TAU */ \
+	  0x03C4, /* GREEK SMALL LETTER TAU */ }, \
+	{ 0x0398, /* GREEK CAPITAL LETTER THETA */ \
+	  0x03B8, /* GREEK SMALL LETTER THETA */ }, \
+	{ 0x03A5, /* GREEK CAPITAL LETTER UPSILON */ \
+	  0x03C5, /* GREEK SMALL LETTER UPSILON */ }, \
+	{ 0x1F59, /* GREEK CAPITAL LETTER UPSILON WITH DASIA */ \
+	  0x1F51, /* GREEK SMALL LETTER UPSILON WITH DASIA */ }, \
+	{ 0x1F5D, /* GREEK CAPITAL LETTER UPSILON WITH DASIA AND OXIA */ \
+	  0x1F55, /* GREEK SMALL LETTER UPSILON WITH DASIA AND OXIA */ }, \
+	{ 0x1F5F, /* GREEK CAPITAL LETTER UPSILON WITH DASIA AND PERISPOMENI */ \
+	  0x1F57, /* GREEK SMALL LETTER UPSILON WITH DASIA AND PERISPOMENI */ }, \
+	{ 0x1F5B, /* GREEK CAPITAL LETTER UPSILON WITH DASIA AND VARIA */ \
+	  0x1F53, /* GREEK SMALL LETTER UPSILON WITH DASIA AND VARIA */ }, \
+	{ 0x03AB, /* GREEK CAPITAL LETTER UPSILON WITH DIALYTIKA */ \
+	  0x03CB, /* GREEK SMALL LETTER UPSILON WITH DIALYTIKA */ }, \
+	{ 0x1FE9, /* GREEK CAPITAL LETTER UPSILON WITH MACRON */ \
+	  0x1FE1, /* GREEK SMALL LETTER UPSILON WITH MACRON */ }, \
+	{ 0x1FEB, /* GREEK CAPITAL LETTER UPSILON WITH OXIA */ \
+	  0x1F7B, /* GREEK SMALL LETTER UPSILON WITH OXIA */ }, \
+	{ 0x038E, /* GREEK CAPITAL LETTER UPSILON WITH TONOS */ \
+	  0x03CD, /* GREEK SMALL LETTER UPSILON WITH TONOS */ }, \
+	{ 0x1FEA, /* GREEK CAPITAL LETTER UPSILON WITH VARIA */ \
+	  0x1F7A, /* GREEK SMALL LETTER UPSILON WITH VARIA */ }, \
+	{ 0x1FE8, /* GREEK CAPITAL LETTER UPSILON WITH VRACHY */ \
+	  0x1FE0, /* GREEK SMALL LETTER UPSILON WITH VRACHY */ }, \
+	{ 0x039E, /* GREEK CAPITAL LETTER XI */ \
+	  0x03BE, /* GREEK SMALL LETTER XI */ }, \
+	{ 0x0396, /* GREEK CAPITAL LETTER ZETA */ \
+	  0x03B6, /* GREEK SMALL LETTER ZETA */ }, \
+	{ 0x0041, /* LATIN CAPITAL LETTER A */ \
+	  0x0061, /* LATIN SMALL LETTER A */ }, \
+	{ 0x00C1, /* LATIN CAPITAL LETTER A WITH ACUTE */ \
+	  0x00E1, /* LATIN SMALL LETTER A WITH ACUTE */ }, \
+	{ 0x0102, /* LATIN CAPITAL LETTER A WITH BREVE */ \
+	  0x0103, /* LATIN SMALL LETTER A WITH BREVE */ }, \
+	{ 0x1EAE, /* LATIN CAPITAL LETTER A WITH BREVE AND ACUTE */ \
+	  0x1EAF, /* LATIN SMALL LETTER A WITH BREVE AND ACUTE */ }, \
+	{ 0x1EB6, /* LATIN CAPITAL LETTER A WITH BREVE AND DOT BELOW */ \
+	  0x1EB7, /* LATIN SMALL LETTER A WITH BREVE AND DOT BELOW */ }, \
+	{ 0x1EB0, /* LATIN CAPITAL LETTER A WITH BREVE AND GRAVE */ \
+	  0x1EB1, /* LATIN SMALL LETTER A WITH BREVE AND GRAVE */ }, \
+	{ 0x1EB2, /* LATIN CAPITAL LETTER A WITH BREVE AND HOOK ABOVE */ \
+	  0x1EB3, /* LATIN SMALL LETTER A WITH BREVE AND HOOK ABOVE */ }, \
+	{ 0x1EB4, /* LATIN CAPITAL LETTER A WITH BREVE AND TILDE */ \
+	  0x1EB5, /* LATIN SMALL LETTER A WITH BREVE AND TILDE */ }, \
+	{ 0x01CD, /* LATIN CAPITAL LETTER A WITH CARON */ \
+	  0x01CE, /* LATIN SMALL LETTER A WITH CARON */ }, \
+	{ 0x00C2, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX */ \
+	  0x00E2, /* LATIN SMALL LETTER A WITH CIRCUMFLEX */ }, \
+	{ 0x1EA4, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND ACUTE */ \
+	  0x1EA5, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND ACUTE */ }, \
+	{ 0x1EAC, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND DOT BELOW */ \
+	  0x1EAD, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND DOT BELOW */ }, \
+	{ 0x1EA6, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND GRAVE */ \
+	  0x1EA7, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND GRAVE */ }, \
+	{ 0x1EA8, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND HOOK ABOVE */ \
+	  0x1EA9, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND HOOK ABOVE */ }, \
+	{ 0x1EAA, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND TILDE */ \
+	  0x1EAB, /* LATIN SMALL LETTER A WITH CIRCUMFLEX AND TILDE */ }, \
+	{ 0x00C4, /* LATIN CAPITAL LETTER A WITH DIAERESIS */ \
+	  0x00E4, /* LATIN SMALL LETTER A WITH DIAERESIS */ }, \
+	{ 0x01DE, /* LATIN CAPITAL LETTER A WITH DIAERESIS AND MACRON */ \
+	  0x01DF, /* LATIN SMALL LETTER A WITH DIAERESIS AND MACRON */ }, \
+	{ 0x0226, /* LATIN CAPITAL LETTER A WITH DOT ABOVE */ \
+	  0x0227, /* LATIN SMALL LETTER A WITH DOT ABOVE */ }, \
+	{ 0x01E0, /* LATIN CAPITAL LETTER A WITH DOT ABOVE AND MACRON */ \
+	  0x01E1, /* LATIN SMALL LETTER A WITH DOT ABOVE AND MACRON */ }, \
+	{ 0x1EA0, /* LATIN CAPITAL LETTER A WITH DOT BELOW */ \
+	  0x1EA1, /* LATIN SMALL LETTER A WITH DOT BELOW */ }, \
+	{ 0x0200, /* LATIN CAPITAL LETTER A WITH DOUBLE GRAVE */ \
+	  0x0201, /* LATIN SMALL LETTER A WITH DOUBLE GRAVE */ }, \
+	{ 0x00C0, /* LATIN CAPITAL LETTER A WITH GRAVE */ \
+	  0x00E0, /* LATIN SMALL LETTER A WITH GRAVE */ }, \
+	{ 0x1EA2, /* LATIN CAPITAL LETTER A WITH HOOK ABOVE */ \
+	  0x1EA3, /* LATIN SMALL LETTER A WITH HOOK ABOVE */ }, \
+	{ 0x0202, /* LATIN CAPITAL LETTER A WITH INVERTED BREVE */ \
+	  0x0203, /* LATIN SMALL LETTER A WITH INVERTED BREVE */ }, \
+	{ 0x0100, /* LATIN CAPITAL LETTER A WITH MACRON */ \
+	  0x0101, /* LATIN SMALL LETTER A WITH MACRON */ }, \
+	{ 0x0104, /* LATIN CAPITAL LETTER A WITH OGONEK */ \
+	  0x0105, /* LATIN SMALL LETTER A WITH OGONEK */ }, \
+	{ 0x00C5, /* LATIN CAPITAL LETTER A WITH RING ABOVE */ \
+	  0x00E5, /* LATIN SMALL LETTER A WITH RING ABOVE */ }, \
+	{ 0x01FA, /* LATIN CAPITAL LETTER A WITH RING ABOVE AND ACUTE */ \
+	  0x01FB, /* LATIN SMALL LETTER A WITH RING ABOVE AND ACUTE */ }, \
+	{ 0x1E00, /* LATIN CAPITAL LETTER A WITH RING BELOW */ \
+	  0x1E01, /* LATIN SMALL LETTER A WITH RING BELOW */ }, \
+	{ 0x023A, /* LATIN CAPITAL LETTER A WITH STROKE */ \
+	  0x2C65, /* LATIN SMALL LETTER A WITH STROKE */ }, \
+	{ 0x00C3, /* LATIN CAPITAL LETTER A WITH TILDE */ \
+	  0x00E3, /* LATIN SMALL LETTER A WITH TILDE */ }, \
+	{ 0xA732, /* LATIN CAPITAL LETTER AA */ \
+	  0xA733, /* LATIN SMALL LETTER AA */ }, \
+	{ 0x00C6, /* LATIN CAPITAL LETTER AE */ \
+	  0x00E6, /* LATIN SMALL LETTER AE */ }, \
+	{ 0x01FC, /* LATIN CAPITAL LETTER AE WITH ACUTE */ \
+	  0x01FD, /* LATIN SMALL LETTER AE WITH ACUTE */ }, \
+	{ 0x01E2, /* LATIN CAPITAL LETTER AE WITH MACRON */ \
+	  0x01E3, /* LATIN SMALL LETTER AE WITH MACRON */ }, \
+	{ 0x2C6D, /* LATIN CAPITAL LETTER ALPHA */ \
+	  0x0251, /* LATIN SMALL LETTER ALPHA */ }, \
+	{ 0xA734, /* LATIN CAPITAL LETTER AO */ \
+	  0xA735, /* LATIN SMALL LETTER AO */ }, \
+	{ 0xA736, /* LATIN CAPITAL LETTER AU */ \
+	  0xA737, /* LATIN SMALL LETTER AU */ }, \
+	{ 0xA738, /* LATIN CAPITAL LETTER AV */ \
+	  0xA739, /* LATIN SMALL LETTER AV */ }, \
+	{ 0xA73A, /* LATIN CAPITAL LETTER AV WITH HORIZONTAL BAR */ \
+	  0xA73B, /* LATIN SMALL LETTER AV WITH HORIZONTAL BAR */ }, \
+	{ 0xA73C, /* LATIN CAPITAL LETTER AY */ \
+	  0xA73D, /* LATIN SMALL LETTER AY */ }, \
+	{ 0x0042, /* LATIN CAPITAL LETTER B */ \
+	  0x0062, /* LATIN SMALL LETTER B */ }, \
+	{ 0x1E02, /* LATIN CAPITAL LETTER B WITH DOT ABOVE */ \
+	  0x1E03, /* LATIN SMALL LETTER B WITH DOT ABOVE */ }, \
+	{ 0x1E04, /* LATIN CAPITAL LETTER B WITH DOT BELOW */ \
+	  0x1E05, /* LATIN SMALL LETTER B WITH DOT BELOW */ }, \
+	{ 0xA796, /* LATIN CAPITAL LETTER B WITH FLOURISH */ \
+	  0xA797, /* LATIN SMALL LETTER B WITH FLOURISH */ }, \
+	{ 0x0181, /* LATIN CAPITAL LETTER B WITH HOOK */ \
+	  0x0253, /* LATIN SMALL LETTER B WITH HOOK */ }, \
+	{ 0x1E06, /* LATIN CAPITAL LETTER B WITH LINE BELOW */ \
+	  0x1E07, /* LATIN SMALL LETTER B WITH LINE BELOW */ }, \
+	{ 0x0243, /* LATIN CAPITAL LETTER B WITH STROKE */ \
+	  0x0180, /* LATIN SMALL LETTER B WITH STROKE */ }, \
+	{ 0x0182, /* LATIN CAPITAL LETTER B WITH TOPBAR */ \
+	  0x0183, /* LATIN SMALL LETTER B WITH TOPBAR */ }, \
+	{ 0xA7B4, /* LATIN CAPITAL LETTER BETA */ \
+	  0xA7B5, /* LATIN SMALL LETTER BETA */ }, \
+	{ 0xA746, /* LATIN CAPITAL LETTER BROKEN L */ \
+	  0xA747, /* LATIN SMALL LETTER BROKEN L */ }, \
+	{ 0x0043, /* LATIN CAPITAL LETTER C */ \
+	  0x0063, /* LATIN SMALL LETTER C */ }, \
+	{ 0x0106, /* LATIN CAPITAL LETTER C WITH ACUTE */ \
+	  0x0107, /* LATIN SMALL LETTER C WITH ACUTE */ }, \
+	{ 0xA792, /* LATIN CAPITAL LETTER C WITH BAR */ \
+	  0xA793, /* LATIN SMALL LETTER C WITH BAR */ }, \
+	{ 0x010C, /* LATIN CAPITAL LETTER C WITH CARON */ \
+	  0x010D, /* LATIN SMALL LETTER C WITH CARON */ }, \
+	{ 0x00C7, /* LATIN CAPITAL LETTER C WITH CEDILLA */ \
+	  0x00E7, /* LATIN SMALL LETTER C WITH CEDILLA */ }, \
+	{ 0x1E08, /* LATIN CAPITAL LETTER C WITH CEDILLA AND ACUTE */ \
+	  0x1E09, /* LATIN SMALL LETTER C WITH CEDILLA AND ACUTE */ }, \
+	{ 0x0108, /* LATIN CAPITAL LETTER C WITH CIRCUMFLEX */ \
+	  0x0109, /* LATIN SMALL LETTER C WITH CIRCUMFLEX */ }, \
+	{ 0x010A, /* LATIN CAPITAL LETTER C WITH DOT ABOVE */ \
+	  0x010B, /* LATIN SMALL LETTER C WITH DOT ABOVE */ }, \
+	{ 0x0187, /* LATIN CAPITAL LETTER C WITH HOOK */ \
+	  0x0188, /* LATIN SMALL LETTER C WITH HOOK */ }, \
+	{ 0x023B, /* LATIN CAPITAL LETTER C WITH STROKE */ \
+	  0x023C, /* LATIN SMALL LETTER C WITH STROKE */ }, \
+	{ 0xA7B3, /* LATIN CAPITAL LETTER CHI */ \
+	  0xAB53, /* LATIN SMALL LETTER CHI */ }, \
+	{ 0xA76E, /* LATIN CAPITAL LETTER CON */ \
+	  0xA76F, /* LATIN SMALL LETTER CON */ }, \
+	{ 0xA72C, /* LATIN CAPITAL LETTER CUATRILLO */ \
+	  0xA72D, /* LATIN SMALL LETTER CUATRILLO */ }, \
+	{ 0xA72E, /* LATIN CAPITAL LETTER CUATRILLO WITH COMMA */ \
+	  0xA72F, /* LATIN SMALL LETTER CUATRILLO WITH COMMA */ }, \
+	{ 0x0044, /* LATIN CAPITAL LETTER D */ \
+	  0x0064, /* LATIN SMALL LETTER D */ }, \
+	{ 0x010E, /* LATIN CAPITAL LETTER D WITH CARON */ \
+	  0x010F, /* LATIN SMALL LETTER D WITH CARON */ }, \
+	{ 0x1E10, /* LATIN CAPITAL LETTER D WITH CEDILLA */ \
+	  0x1E11, /* LATIN SMALL LETTER D WITH CEDILLA */ }, \
+	{ 0x1E12, /* LATIN CAPITAL LETTER D WITH CIRCUMFLEX BELOW */ \
+	  0x1E13, /* LATIN SMALL LETTER D WITH CIRCUMFLEX BELOW */ }, \
+	{ 0x1E0A, /* LATIN CAPITAL LETTER D WITH DOT ABOVE */ \
+	  0x1E0B, /* LATIN SMALL LETTER D WITH DOT ABOVE */ }, \
+	{ 0x1E0C, /* LATIN CAPITAL LETTER D WITH DOT BELOW */ \
+	  0x1E0D, /* LATIN SMALL LETTER D WITH DOT BELOW */ }, \
+	{ 0x018A, /* LATIN CAPITAL LETTER D WITH HOOK */ \
+	  0x0257, /* LATIN SMALL LETTER D WITH HOOK */ }, \
+	{ 0x1E0E, /* LATIN CAPITAL LETTER D WITH LINE BELOW */ \
+	  0x1E0F, /* LATIN SMALL LETTER D WITH LINE BELOW */ }, \
+	{ 0x0110, /* LATIN CAPITAL LETTER D WITH STROKE */ \
+	  0x0111, /* LATIN SMALL LETTER D WITH STROKE */ }, \
+	{ 0x018B, /* LATIN CAPITAL LETTER D WITH TOPBAR */ \
+	  0x018C, /* LATIN SMALL LETTER D WITH TOPBAR */ }, \
+	{ 0x01F1, /* LATIN CAPITAL LETTER DZ */ \
+	  0x01F3, /* LATIN SMALL LETTER DZ */ }, \
+	{ 0x01C4, /* LATIN CAPITAL LETTER DZ WITH CARON */ \
+	  0x01C6, /* LATIN SMALL LETTER DZ WITH CARON */ }, \
+	{ 0x0045, /* LATIN CAPITAL LETTER E */ \
+	  0x0065, /* LATIN SMALL LETTER E */ }, \
+	{ 0x00C9, /* LATIN CAPITAL LETTER E WITH ACUTE */ \
+	  0x00E9, /* LATIN SMALL LETTER E WITH ACUTE */ }, \
+	{ 0x0114, /* LATIN CAPITAL LETTER E WITH BREVE */ \
+	  0x0115, /* LATIN SMALL LETTER E WITH BREVE */ }, \
+	{ 0x011A, /* LATIN CAPITAL LETTER E WITH CARON */ \
+	  0x011B, /* LATIN SMALL LETTER E WITH CARON */ }, \
+	{ 0x0228, /* LATIN CAPITAL LETTER E WITH CEDILLA */ \
+	  0x0229, /* LATIN SMALL LETTER E WITH CEDILLA */ }, \
+	{ 0x1E1C, /* LATIN CAPITAL LETTER E WITH CEDILLA AND BREVE */ \
+	  0x1E1D, /* LATIN SMALL LETTER E WITH CEDILLA AND BREVE */ }, \
+	{ 0x00CA, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX */ \
+	  0x00EA, /* LATIN SMALL LETTER E WITH CIRCUMFLEX */ }, \
+	{ 0x1EBE, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND ACUTE */ \
+	  0x1EBF, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND ACUTE */ }, \
+	{ 0x1EC6, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND DOT BELOW */ \
+	  0x1EC7, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND DOT BELOW */ }, \
+	{ 0x1EC0, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND GRAVE */ \
+	  0x1EC1, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND GRAVE */ }, \
+	{ 0x1EC2, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND HOOK ABOVE */ \
+	  0x1EC3, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND HOOK ABOVE */ }, \
+	{ 0x1EC4, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND TILDE */ \
+	  0x1EC5, /* LATIN SMALL LETTER E WITH CIRCUMFLEX AND TILDE */ }, \
+	{ 0x1E18, /* LATIN CAPITAL LETTER E WITH CIRCUMFLEX BELOW */ \
+	  0x1E19, /* LATIN SMALL LETTER E WITH CIRCUMFLEX BELOW */ }, \
+	{ 0x00CB, /* LATIN CAPITAL LETTER E WITH DIAERESIS */ \
+	  0x00EB, /* LATIN SMALL LETTER E WITH DIAERESIS */ }, \
+	{ 0x0116, /* LATIN CAPITAL LETTER E WITH DOT ABOVE */ \
+	  0x0117, /* LATIN SMALL LETTER E WITH DOT ABOVE */ }, \
+	{ 0x1EB8, /* LATIN CAPITAL LETTER E WITH DOT BELOW */ \
+	  0x1EB9, /* LATIN SMALL LETTER E WITH DOT BELOW */ }, \
+	{ 0x0204, /* LATIN CAPITAL LETTER E WITH DOUBLE GRAVE */ \
+	  0x0205, /* LATIN SMALL LETTER E WITH DOUBLE GRAVE */ }, \
+	{ 0x00C8, /* LATIN CAPITAL LETTER E WITH GRAVE */ \
+	  0x00E8, /* LATIN SMALL LETTER E WITH GRAVE */ }, \
+	{ 0x1EBA, /* LATIN CAPITAL LETTER E WITH HOOK ABOVE */ \
+	  0x1EBB, /* LATIN SMALL LETTER E WITH HOOK ABOVE */ }, \
+	{ 0x0206, /* LATIN CAPITAL LETTER E WITH INVERTED BREVE */ \
+	  0x0207, /* LATIN SMALL LETTER E WITH INVERTED BREVE */ }, \
+	{ 0x0112, /* LATIN CAPITAL LETTER E WITH MACRON */ \
+	  0x0113, /* LATIN SMALL LETTER E WITH MACRON */ }, \
+	{ 0x1E16, /* LATIN CAPITAL LETTER E WITH MACRON AND ACUTE */ \
+	  0x1E17, /* LATIN SMALL LETTER E WITH MACRON AND ACUTE */ }, \
+	{ 0x1E14, /* LATIN CAPITAL LETTER E WITH MACRON AND GRAVE */ \
+	  0x1E15, /* LATIN SMALL LETTER E WITH MACRON AND GRAVE */ }, \
+	{ 0x0118, /* LATIN CAPITAL LETTER E WITH OGONEK */ \
+	  0x0119, /* LATIN SMALL LETTER E WITH OGONEK */ }, \
+	{ 0x0246, /* LATIN CAPITAL LETTER E WITH STROKE */ \
+	  0x0247, /* LATIN SMALL LETTER E WITH STROKE */ }, \
+	{ 0x1EBC, /* LATIN CAPITAL LETTER E WITH TILDE */ \
+	  0x1EBD, /* LATIN SMALL LETTER E WITH TILDE */ }, \
+	{ 0x1E1A, /* LATIN CAPITAL LETTER E WITH TILDE BELOW */ \
+	  0x1E1B, /* LATIN SMALL LETTER E WITH TILDE BELOW */ }, \
+	{ 0xA724, /* LATIN CAPITAL LETTER EGYPTOLOGICAL AIN */ \
+	  0xA725, /* LATIN SMALL LETTER EGYPTOLOGICAL AIN */ }, \
+	{ 0xA722, /* LATIN CAPITAL LETTER EGYPTOLOGICAL ALEF */ \
+	  0xA723, /* LATIN SMALL LETTER EGYPTOLOGICAL ALEF */ }, \
+	{ 0x014A, /* LATIN CAPITAL LETTER ENG */ \
+	  0x014B, /* LATIN SMALL LETTER ENG */ }, \
+	{ 0x01A9, /* LATIN CAPITAL LETTER ESH */ \
+	  0x0283, /* LATIN SMALL LETTER ESH */ }, \
+	{ 0xA76A, /* LATIN CAPITAL LETTER ET */ \
+	  0xA76B, /* LATIN SMALL LETTER ET */ }, \
+	{ 0x00D0, /* LATIN CAPITAL LETTER ETH */ \
+	  0x00F0, /* LATIN SMALL LETTER ETH */ }, \
+	{ 0x01B7, /* LATIN CAPITAL LETTER EZH */ \
+	  0x0292, /* LATIN SMALL LETTER EZH */ }, \
+	{ 0x01B8, /* LATIN CAPITAL LETTER EZH REVERSED */ \
+	  0x01B9, /* LATIN SMALL LETTER EZH REVERSED */ }, \
+	{ 0x01EE, /* LATIN CAPITAL LETTER EZH WITH CARON */ \
+	  0x01EF, /* LATIN SMALL LETTER EZH WITH CARON */ }, \
+	{ 0x0046, /* LATIN CAPITAL LETTER F */ \
+	  0x0066, /* LATIN SMALL LETTER F */ }, \
+	{ 0x1E1E, /* LATIN CAPITAL LETTER F WITH DOT ABOVE */ \
+	  0x1E1F, /* LATIN SMALL LETTER F WITH DOT ABOVE */ }, \
+	{ 0x0191, /* LATIN CAPITAL LETTER F WITH HOOK */ \
+	  0x0192, /* LATIN SMALL LETTER F WITH HOOK */ }, \
+	{ 0xA798, /* LATIN CAPITAL LETTER F WITH STROKE */ \
+	  0xA799, /* LATIN SMALL LETTER F WITH STROKE */ }, \
+	{ 0x0047, /* LATIN CAPITAL LETTER G */ \
+	  0x0067, /* LATIN SMALL LETTER G */ }, \
+	{ 0x01F4, /* LATIN CAPITAL LETTER G WITH ACUTE */ \
+	  0x01F5, /* LATIN SMALL LETTER G WITH ACUTE */ }, \
+	{ 0x011E, /* LATIN CAPITAL LETTER G WITH BREVE */ \
+	  0x011F, /* LATIN SMALL LETTER G WITH BREVE */ }, \
+	{ 0x01E6, /* LATIN CAPITAL LETTER G WITH CARON */ \
+	  0x01E7, /* LATIN SMALL LETTER G WITH CARON */ }, \
+	{ 0x0122, /* LATIN CAPITAL LETTER G WITH CEDILLA */ \
+	  0x0123, /* LATIN SMALL LETTER G WITH CEDILLA */ }, \
+	{ 0x011C, /* LATIN CAPITAL LETTER G WITH CIRCUMFLEX */ \
+	  0x011D, /* LATIN SMALL LETTER G WITH CIRCUMFLEX */ }, \
+	{ 0x0120, /* LATIN CAPITAL LETTER G WITH DOT ABOVE */ \
+	  0x0121, /* LATIN SMALL LETTER G WITH DOT ABOVE */ }, \
+	{ 0x0193, /* LATIN CAPITAL LETTER G WITH HOOK */ \
+	  0x0260, /* LATIN SMALL LETTER G WITH HOOK */ }, \
+	{ 0x1E20, /* LATIN CAPITAL LETTER G WITH MACRON */ \
+	  0x1E21, /* LATIN SMALL LETTER G WITH MACRON */ }, \
+	{ 0xA7A0, /* LATIN CAPITAL LETTER G WITH OBLIQUE STROKE */ \
+	  0xA7A1, /* LATIN SMALL LETTER G WITH OBLIQUE STROKE */ }, \
+	{ 0x01E4, /* LATIN CAPITAL LETTER G WITH STROKE */ \
+	  0x01E5, /* LATIN SMALL LETTER G WITH STROKE */ }, \
+	{ 0x0194, /* LATIN CAPITAL LETTER GAMMA */ \
+	  0x0263, /* LATIN SMALL LETTER GAMMA */ }, \
+	{ 0x0241, /* LATIN CAPITAL LETTER GLOTTAL STOP */ \
+	  0x0242, /* LATIN SMALL LETTER GLOTTAL STOP */ }, \
+	{ 0x0048, /* LATIN CAPITAL LETTER H */ \
+	  0x0068, /* LATIN SMALL LETTER H */ }, \
+	{ 0x1E2A, /* LATIN CAPITAL LETTER H WITH BREVE BELOW */ \
+	  0x1E2B, /* LATIN SMALL LETTER H WITH BREVE BELOW */ }, \
+	{ 0x021E, /* LATIN CAPITAL LETTER H WITH CARON */ \
+	  0x021F, /* LATIN SMALL LETTER H WITH CARON */ }, \
+	{ 0x1E28, /* LATIN CAPITAL LETTER H WITH CEDILLA */ \
+	  0x1E29, /* LATIN SMALL LETTER H WITH CEDILLA */ }, \
+	{ 0x0124, /* LATIN CAPITAL LETTER H WITH CIRCUMFLEX */ \
+	  0x0125, /* LATIN SMALL LETTER H WITH CIRCUMFLEX */ }, \
+	{ 0x2C67, /* LATIN CAPITAL LETTER H WITH DESCENDER */ \
+	  0x2C68, /* LATIN SMALL LETTER H WITH DESCENDER */ }, \
+	{ 0x1E26, /* LATIN CAPITAL LETTER H WITH DIAERESIS */ \
+	  0x1E27, /* LATIN SMALL LETTER H WITH DIAERESIS */ }, \
+	{ 0x1E22, /* LATIN CAPITAL LETTER H WITH DOT ABOVE */ \
+	  0x1E23, /* LATIN SMALL LETTER H WITH DOT ABOVE */ }, \
+	{ 0x1E24, /* LATIN CAPITAL LETTER H WITH DOT BELOW */ \
+	  0x1E25, /* LATIN SMALL LETTER H WITH DOT BELOW */ }, \
+	{ 0xA7AA, /* LATIN CAPITAL LETTER H WITH HOOK */ \
+	  0x0266, /* LATIN SMALL LETTER H WITH HOOK */ }, \
+	{ 0x0126, /* LATIN CAPITAL LETTER H WITH STROKE */ \
+	  0x0127, /* LATIN SMALL LETTER H WITH STROKE */ }, \
+	{ 0x2C75, /* LATIN CAPITAL LETTER HALF H */ \
+	  0x2C76, /* LATIN SMALL LETTER HALF H */ }, \
+	{ 0xA726, /* LATIN CAPITAL LETTER HENG */ \
+	  0xA727, /* LATIN SMALL LETTER HENG */ }, \
+	{ 0x0049, /* LATIN CAPITAL LETTER I */ \
+	  0x0069, /* LATIN SMALL LETTER I */ }, \
+	{ 0x00CD, /* LATIN CAPITAL LETTER I WITH ACUTE */ \
+	  0x00ED, /* LATIN SMALL LETTER I WITH ACUTE */ }, \
+	{ 0x012C, /* LATIN CAPITAL LETTER I WITH BREVE */ \
+	  0x012D, /* LATIN SMALL LETTER I WITH BREVE */ }, \
+	{ 0x01CF, /* LATIN CAPITAL LETTER I WITH CARON */ \
+	  0x01D0, /* LATIN SMALL LETTER I WITH CARON */ }, \
+	{ 0x00CE, /* LATIN CAPITAL LETTER I WITH CIRCUMFLEX */ \
+	  0x00EE, /* LATIN SMALL LETTER I WITH CIRCUMFLEX */ }, \
+	{ 0x00CF, /* LATIN CAPITAL LETTER I WITH DIAERESIS */ \
+	  0x00EF, /* LATIN SMALL LETTER I WITH DIAERESIS */ }, \
+	{ 0x1E2E, /* LATIN CAPITAL LETTER I WITH DIAERESIS AND ACUTE */ \
+	  0x1E2F, /* LATIN SMALL LETTER I WITH DIAERESIS AND ACUTE */ }, \
+	{ 0x1ECA, /* LATIN CAPITAL LETTER I WITH DOT BELOW */ \
+	  0x1ECB, /* LATIN SMALL LETTER I WITH DOT BELOW */ }, \
+	{ 0x0208, /* LATIN CAPITAL LETTER I WITH DOUBLE GRAVE */ \
+	  0x0209, /* LATIN SMALL LETTER I WITH DOUBLE GRAVE */ }, \
+	{ 0x00CC, /* LATIN CAPITAL LETTER I WITH GRAVE */ \
+	  0x00EC, /* LATIN SMALL LETTER I WITH GRAVE */ }, \
+	{ 0x1EC8, /* LATIN CAPITAL LETTER I WITH HOOK ABOVE */ \
+	  0x1EC9, /* LATIN SMALL LETTER I WITH HOOK ABOVE */ }, \
+	{ 0x020A, /* LATIN CAPITAL LETTER I WITH INVERTED BREVE */ \
+	  0x020B, /* LATIN SMALL LETTER I WITH INVERTED BREVE */ }, \
+	{ 0x012A, /* LATIN CAPITAL LETTER I WITH MACRON */ \
+	  0x012B, /* LATIN SMALL LETTER I WITH MACRON */ }, \
+	{ 0x012E, /* LATIN CAPITAL LETTER I WITH OGONEK */ \
+	  0x012F, /* LATIN SMALL LETTER I WITH OGONEK */ }, \
+	{ 0x0197, /* LATIN CAPITAL LETTER I WITH STROKE */ \
+	  0x0268, /* LATIN SMALL LETTER I WITH STROKE */ }, \
+	{ 0x0128, /* LATIN CAPITAL LETTER I WITH TILDE */ \
+	  0x0129, /* LATIN SMALL LETTER I WITH TILDE */ }, \
+	{ 0x1E2C, /* LATIN CAPITAL LETTER I WITH TILDE BELOW */ \
+	  0x1E2D, /* LATIN SMALL LETTER I WITH TILDE BELOW */ }, \
+	{ 0xA779, /* LATIN CAPITAL LETTER INSULAR D */ \
+	  0xA77A, /* LATIN SMALL LETTER INSULAR D */ }, \
+	{ 0xA77B, /* LATIN CAPITAL LETTER INSULAR F */ \
+	  0xA77C, /* LATIN SMALL LETTER INSULAR F */ }, \
+	{ 0xA77D, /* LATIN CAPITAL LETTER INSULAR G */ \
+	  0x1D79, /* LATIN SMALL LETTER INSULAR G */ }, \
+	{ 0xA782, /* LATIN CAPITAL LETTER INSULAR R */ \
+	  0xA783, /* LATIN SMALL LETTER INSULAR R */ }, \
+	{ 0xA784, /* LATIN CAPITAL LETTER INSULAR S */ \
+	  0xA785, /* LATIN SMALL LETTER INSULAR S */ }, \
+	{ 0xA786, /* LATIN CAPITAL LETTER INSULAR T */ \
+	  0xA787, /* LATIN SMALL LETTER INSULAR T */ }, \
+	{ 0x0196, /* LATIN CAPITAL LETTER IOTA */ \
+	  0x0269, /* LATIN SMALL LETTER IOTA */ }, \
+	{ 0xA76C, /* LATIN CAPITAL LETTER IS */ \
+	  0xA76D, /* LATIN SMALL LETTER IS */ }, \
+	{ 0x004A, /* LATIN CAPITAL LETTER J */ \
+	  0x006A, /* LATIN SMALL LETTER J */ }, \
+	{ 0x0134, /* LATIN CAPITAL LETTER J WITH CIRCUMFLEX */ \
+	  0x0135, /* LATIN SMALL LETTER J WITH CIRCUMFLEX */ }, \
+	{ 0xA7B2, /* LATIN CAPITAL LETTER J WITH CROSSED-TAIL */ \
+	  0x029D, /* LATIN SMALL LETTER J WITH CROSSED-TAIL */ }, \
+	{ 0x0248, /* LATIN CAPITAL LETTER J WITH STROKE */ \
+	  0x0249, /* LATIN SMALL LETTER J WITH STROKE */ }, \
+	{ 0x004B, /* LATIN CAPITAL LETTER K */ \
+	  0x006B, /* LATIN SMALL LETTER K */ }, \
+	{ 0x1E30, /* LATIN CAPITAL LETTER K WITH ACUTE */ \
+	  0x1E31, /* LATIN SMALL LETTER K WITH ACUTE */ }, \
+	{ 0x01E8, /* LATIN CAPITAL LETTER K WITH CARON */ \
+	  0x01E9, /* LATIN SMALL LETTER K WITH CARON */ }, \
+	{ 0x0136, /* LATIN CAPITAL LETTER K WITH CEDILLA */ \
+	  0x0137, /* LATIN SMALL LETTER K WITH CEDILLA */ }, \
+	{ 0x2C69, /* LATIN CAPITAL LETTER K WITH DESCENDER */ \
+	  0x2C6A, /* LATIN SMALL LETTER K WITH DESCENDER */ }, \
+	{ 0xA742, /* LATIN CAPITAL LETTER K WITH DIAGONAL STROKE */ \
+	  0xA743, /* LATIN SMALL LETTER K WITH DIAGONAL STROKE */ }, \
+	{ 0x1E32, /* LATIN CAPITAL LETTER K WITH DOT BELOW */ \
+	  0x1E33, /* LATIN SMALL LETTER K WITH DOT BELOW */ }, \
+	{ 0x0198, /* LATIN CAPITAL LETTER K WITH HOOK */ \
+	  0x0199, /* LATIN SMALL LETTER K WITH HOOK */ }, \
+	{ 0x1E34, /* LATIN CAPITAL LETTER K WITH LINE BELOW */ \
+	  0x1E35, /* LATIN SMALL LETTER K WITH LINE BELOW */ }, \
+	{ 0xA7A2, /* LATIN CAPITAL LETTER K WITH OBLIQUE STROKE */ \
+	  0xA7A3, /* LATIN SMALL LETTER K WITH OBLIQUE STROKE */ }, \
+	{ 0xA740, /* LATIN CAPITAL LETTER K WITH STROKE */ \
+	  0xA741, /* LATIN SMALL LETTER K WITH STROKE */ }, \
+	{ 0xA744, /* LATIN CAPITAL LETTER K WITH STROKE AND DIAGONAL STROKE */ \
+	  0xA745, /* LATIN SMALL LETTER K WITH STROKE AND DIAGONAL STROKE */ }, \
+	{ 0x004C, /* LATIN CAPITAL LETTER L */ \
+	  0x006C, /* LATIN SMALL LETTER L */ }, \
+	{ 0x0139, /* LATIN CAPITAL LETTER L WITH ACUTE */ \
+	  0x013A, /* LATIN SMALL LETTER L WITH ACUTE */ }, \
+	{ 0x023D, /* LATIN CAPITAL LETTER L WITH BAR */ \
+	  0x019A, /* LATIN SMALL LETTER L WITH BAR */ }, \
+	{ 0xA7AD, /* LATIN CAPITAL LETTER L WITH BELT */ \
+	  0x026C, /* LATIN SMALL LETTER L WITH BELT */ }, \
+	{ 0x013D, /* LATIN CAPITAL LETTER L WITH CARON */ \
+	  0x013E, /* LATIN SMALL LETTER L WITH CARON */ }, \
+	{ 0x013B, /* LATIN CAPITAL LETTER L WITH CEDILLA */ \
+	  0x013C, /* LATIN SMALL LETTER L WITH CEDILLA */ }, \
+	{ 0x1E3C, /* LATIN CAPITAL LETTER L WITH CIRCUMFLEX BELOW */ \
+	  0x1E3D, /* LATIN SMALL LETTER L WITH CIRCUMFLEX BELOW */ }, \
+	{ 0x1E36, /* LATIN CAPITAL LETTER L WITH DOT BELOW */ \
+	  0x1E37, /* LATIN SMALL LETTER L WITH DOT BELOW */ }, \
+	{ 0x1E38, /* LATIN CAPITAL LETTER L WITH DOT BELOW AND MACRON */ \
+	  0x1E39, /* LATIN SMALL LETTER L WITH DOT BELOW AND MACRON */ }, \
+	{ 0x2C60, /* LATIN CAPITAL LETTER L WITH DOUBLE BAR */ \
+	  0x2C61, /* LATIN SMALL LETTER L WITH DOUBLE BAR */ }, \
+	{ 0xA748, /* LATIN CAPITAL LETTER L WITH HIGH STROKE */ \
+	  0xA749, /* LATIN SMALL LETTER L WITH HIGH STROKE */ }, \
+	{ 0x1E3A, /* LATIN CAPITAL LETTER L WITH LINE BELOW */ \
+	  0x1E3B, /* LATIN SMALL LETTER L WITH LINE BELOW */ }, \
+	{ 0x013F, /* LATIN CAPITAL LETTER L WITH MIDDLE DOT */ \
+	  0x0140, /* LATIN SMALL LETTER L WITH MIDDLE DOT */ }, \
+	{ 0x2C62, /* LATIN CAPITAL LETTER L WITH MIDDLE TILDE */ \
+	  0x026B, /* LATIN SMALL LETTER L WITH MIDDLE TILDE */ }, \
+	{ 0x0141, /* LATIN CAPITAL LETTER L WITH STROKE */ \
+	  0x0142, /* LATIN SMALL LETTER L WITH STROKE */ }, \
+	{ 0x01C7, /* LATIN CAPITAL LETTER LJ */ \
+	  0x01C9, /* LATIN SMALL LETTER LJ */ }, \
+	{ 0x004D, /* LATIN CAPITAL LETTER M */ \
+	  0x006D, /* LATIN SMALL LETTER M */ }, \
+	{ 0x1E3E, /* LATIN CAPITAL LETTER M WITH ACUTE */ \
+	  0x1E3F, /* LATIN SMALL LETTER M WITH ACUTE */ }, \
+	{ 0x1E40, /* LATIN CAPITAL LETTER M WITH DOT ABOVE */ \
+	  0x1E41, /* LATIN SMALL LETTER M WITH DOT ABOVE */ }, \
+	{ 0x1E42, /* LATIN CAPITAL LETTER M WITH DOT BELOW */ \
+	  0x1E43, /* LATIN SMALL LETTER M WITH DOT BELOW */ }, \
+	{ 0x2C6E, /* LATIN CAPITAL LETTER M WITH HOOK */ \
+	  0x0271, /* LATIN SMALL LETTER M WITH HOOK */ }, \
+	{ 0x1EFA, /* LATIN CAPITAL LETTER MIDDLE-WELSH LL */ \
+	  0x1EFB, /* LATIN SMALL LETTER MIDDLE-WELSH LL */ }, \
+	{ 0x1EFC, /* LATIN CAPITAL LETTER MIDDLE-WELSH V */ \
+	  0x1EFD, /* LATIN SMALL LETTER MIDDLE-WELSH V */ }, \
+	{ 0x004E, /* LATIN CAPITAL LETTER N */ \
+	  0x006E, /* LATIN SMALL LETTER N */ }, \
+	{ 0x0143, /* LATIN CAPITAL LETTER N WITH ACUTE */ \
+	  0x0144, /* LATIN SMALL LETTER N WITH ACUTE */ }, \
+	{ 0x0147, /* LATIN CAPITAL LETTER N WITH CARON */ \
+	  0x0148, /* LATIN SMALL LETTER N WITH CARON */ }, \
+	{ 0x0145, /* LATIN CAPITAL LETTER N WITH CEDILLA */ \
+	  0x0146, /* LATIN SMALL LETTER N WITH CEDILLA */ }, \
+	{ 0x1E4A, /* LATIN CAPITAL LETTER N WITH CIRCUMFLEX BELOW */ \
+	  0x1E4B, /* LATIN SMALL LETTER N WITH CIRCUMFLEX BELOW */ }, \
+	{ 0xA790, /* LATIN CAPITAL LETTER N WITH DESCENDER */ \
+	  0xA791, /* LATIN SMALL LETTER N WITH DESCENDER */ }, \
+	{ 0x1E44, /* LATIN CAPITAL LETTER N WITH DOT ABOVE */ \
+	  0x1E45, /* LATIN SMALL LETTER N WITH DOT ABOVE */ }, \
+	{ 0x1E46, /* LATIN CAPITAL LETTER N WITH DOT BELOW */ \
+	  0x1E47, /* LATIN SMALL LETTER N WITH DOT BELOW */ }, \
+	{ 0x01F8, /* LATIN CAPITAL LETTER N WITH GRAVE */ \
+	  0x01F9, /* LATIN SMALL LETTER N WITH GRAVE */ }, \
+	{ 0x019D, /* LATIN CAPITAL LETTER N WITH LEFT HOOK */ \
+	  0x0272, /* LATIN SMALL LETTER N WITH LEFT HOOK */ }, \
+	{ 0x1E48, /* LATIN CAPITAL LETTER N WITH LINE BELOW */ \
+	  0x1E49, /* LATIN SMALL LETTER N WITH LINE BELOW */ }, \
+	{ 0x0220, /* LATIN CAPITAL LETTER N WITH LONG RIGHT LEG */ \
+	  0x019E, /* LATIN SMALL LETTER N WITH LONG RIGHT LEG */ }, \
+	{ 0xA7A4, /* LATIN CAPITAL LETTER N WITH OBLIQUE STROKE */ \
+	  0xA7A5, /* LATIN SMALL LETTER N WITH OBLIQUE STROKE */ }, \
+	{ 0x00D1, /* LATIN CAPITAL LETTER N WITH TILDE */ \
+	  0x00F1, /* LATIN SMALL LETTER N WITH TILDE */ }, \
+	{ 0x01CA, /* LATIN CAPITAL LETTER NJ */ \
+	  0x01CC, /* LATIN SMALL LETTER NJ */ }, \
+	{ 0x004F, /* LATIN CAPITAL LETTER O */ \
+	  0x006F, /* LATIN SMALL LETTER O */ }, \
+	{ 0x00D3, /* LATIN CAPITAL LETTER O WITH ACUTE */ \
+	  0x00F3, /* LATIN SMALL LETTER O WITH ACUTE */ }, \
+	{ 0x014E, /* LATIN CAPITAL LETTER O WITH BREVE */ \
+	  0x014F, /* LATIN SMALL LETTER O WITH BREVE */ }, \
+	{ 0x01D1, /* LATIN CAPITAL LETTER O WITH CARON */ \
+	  0x01D2, /* LATIN SMALL LETTER O WITH CARON */ }, \
+	{ 0x00D4, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX */ \
+	  0x00F4, /* LATIN SMALL LETTER O WITH CIRCUMFLEX */ }, \
+	{ 0x1ED0, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND ACUTE */ \
+	  0x1ED1, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND ACUTE */ }, \
+	{ 0x1ED8, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND DOT BELOW */ \
+	  0x1ED9, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND DOT BELOW */ }, \
+	{ 0x1ED2, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND GRAVE */ \
+	  0x1ED3, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND GRAVE */ }, \
+	{ 0x1ED4, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND HOOK ABOVE */ \
+	  0x1ED5, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND HOOK ABOVE */ }, \
+	{ 0x1ED6, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND TILDE */ \
+	  0x1ED7, /* LATIN SMALL LETTER O WITH CIRCUMFLEX AND TILDE */ }, \
+	{ 0x00D6, /* LATIN CAPITAL LETTER O WITH DIAERESIS */ \
+	  0x00F6, /* LATIN SMALL LETTER O WITH DIAERESIS */ }, \
+	{ 0x022A, /* LATIN CAPITAL LETTER O WITH DIAERESIS AND MACRON */ \
+	  0x022B, /* LATIN SMALL LETTER O WITH DIAERESIS AND MACRON */ }, \
+	{ 0x022E, /* LATIN CAPITAL LETTER O WITH DOT ABOVE */ \
+	  0x022F, /* LATIN SMALL LETTER O WITH DOT ABOVE */ }, \
+	{ 0x0230, /* LATIN CAPITAL LETTER O WITH DOT ABOVE AND MACRON */ \
+	  0x0231, /* LATIN SMALL LETTER O WITH DOT ABOVE AND MACRON */ }, \
+	{ 0x1ECC, /* LATIN CAPITAL LETTER O WITH DOT BELOW */ \
+	  0x1ECD, /* LATIN SMALL LETTER O WITH DOT BELOW */ }, \
+	{ 0x0150, /* LATIN CAPITAL LETTER O WITH DOUBLE ACUTE */ \
+	  0x0151, /* LATIN SMALL LETTER O WITH DOUBLE ACUTE */ }, \
+	{ 0x020C, /* LATIN CAPITAL LETTER O WITH DOUBLE GRAVE */ \
+	  0x020D, /* LATIN SMALL LETTER O WITH DOUBLE GRAVE */ }, \
+	{ 0x00D2, /* LATIN CAPITAL LETTER O WITH GRAVE */ \
+	  0x00F2, /* LATIN SMALL LETTER O WITH GRAVE */ }, \
+	{ 0x1ECE, /* LATIN CAPITAL LETTER O WITH HOOK ABOVE */ \
+	  0x1ECF, /* LATIN SMALL LETTER O WITH HOOK ABOVE */ }, \
+	{ 0x01A0, /* LATIN CAPITAL LETTER O WITH HORN */ \
+	  0x01A1, /* LATIN SMALL LETTER O WITH HORN */ }, \
+	{ 0x1EDA, /* LATIN CAPITAL LETTER O WITH HORN AND ACUTE */ \
+	  0x1EDB, /* LATIN SMALL LETTER O WITH HORN AND ACUTE */ }, \
+	{ 0x1EE2, /* LATIN CAPITAL LETTER O WITH HORN AND DOT BELOW */ \
+	  0x1EE3, /* LATIN SMALL LETTER O WITH HORN AND DOT BELOW */ }, \
+	{ 0x1EDC, /* LATIN CAPITAL LETTER O WITH HORN AND GRAVE */ \
+	  0x1EDD, /* LATIN SMALL LETTER O WITH HORN AND GRAVE */ }, \
+	{ 0x1EDE, /* LATIN CAPITAL LETTER O WITH HORN AND HOOK ABOVE */ \
+	  0x1EDF, /* LATIN SMALL LETTER O WITH HORN AND HOOK ABOVE */ }, \
+	{ 0x1EE0, /* LATIN CAPITAL LETTER O WITH HORN AND TILDE */ \
+	  0x1EE1, /* LATIN SMALL LETTER O WITH HORN AND TILDE */ }, \
+	{ 0x020E, /* LATIN CAPITAL LETTER O WITH INVERTED BREVE */ \
+	  0x020F, /* LATIN SMALL LETTER O WITH INVERTED BREVE */ }, \
+	{ 0xA74A, /* LATIN CAPITAL LETTER O WITH LONG STROKE OVERLAY */ \
+	  0xA74B, /* LATIN SMALL LETTER O WITH LONG STROKE OVERLAY */ }, \
+	{ 0xA74C, /* LATIN CAPITAL LETTER O WITH LOOP */ \
+	  0xA74D, /* LATIN SMALL LETTER O WITH LOOP */ }, \
+	{ 0x014C, /* LATIN CAPITAL LETTER O WITH MACRON */ \
+	  0x014D, /* LATIN SMALL LETTER O WITH MACRON */ }, \
+	{ 0x1E52, /* LATIN CAPITAL LETTER O WITH MACRON AND ACUTE */ \
+	  0x1E53, /* LATIN SMALL LETTER O WITH MACRON AND ACUTE */ }, \
+	{ 0x1E50, /* LATIN CAPITAL LETTER O WITH MACRON AND GRAVE */ \
+	  0x1E51, /* LATIN SMALL LETTER O WITH MACRON AND GRAVE */ }, \
+	{ 0x01EA, /* LATIN CAPITAL LETTER O WITH OGONEK */ \
+	  0x01EB, /* LATIN SMALL LETTER O WITH OGONEK */ }, \
+	{ 0x01EC, /* LATIN CAPITAL LETTER O WITH OGONEK AND MACRON */ \
+	  0x01ED, /* LATIN SMALL LETTER O WITH OGONEK AND MACRON */ }, \
+	{ 0x00D8, /* LATIN CAPITAL LETTER O WITH STROKE */ \
+	  0x00F8, /* LATIN SMALL LETTER O WITH STROKE */ }, \
+	{ 0x01FE, /* LATIN CAPITAL LETTER O WITH STROKE AND ACUTE */ \
+	  0x01FF, /* LATIN SMALL LETTER O WITH STROKE AND ACUTE */ }, \
+	{ 0x00D5, /* LATIN CAPITAL LETTER O WITH TILDE */ \
+	  0x00F5, /* LATIN SMALL LETTER O WITH TILDE */ }, \
+	{ 0x1E4C, /* LATIN CAPITAL LETTER O WITH TILDE AND ACUTE */ \
+	  0x1E4D, /* LATIN SMALL LETTER O WITH TILDE AND ACUTE */ }, \
+	{ 0x1E4E, /* LATIN CAPITAL LETTER O WITH TILDE AND DIAERESIS */ \
+	  0x1E4F, /* LATIN SMALL LETTER O WITH TILDE AND DIAERESIS */ }, \
+	{ 0x022C, /* LATIN CAPITAL LETTER O WITH TILDE AND MACRON */ \
+	  0x022D, /* LATIN SMALL LETTER O WITH TILDE AND MACRON */ }, \
+	{ 0x01A2, /* LATIN CAPITAL LETTER OI */ \
+	  0x01A3, /* LATIN SMALL LETTER OI */ }, \
+	{ 0xA7B6, /* LATIN CAPITAL LETTER OMEGA */ \
+	  0xA7B7, /* LATIN SMALL LETTER OMEGA */ }, \
+	{ 0xA74E, /* LATIN CAPITAL LETTER OO */ \
+	  0xA74F, /* LATIN SMALL LETTER OO */ }, \
+	{ 0x0190, /* LATIN CAPITAL LETTER OPEN E */ \
+	  0x025B, /* LATIN SMALL LETTER OPEN E */ }, \
+	{ 0x0186, /* LATIN CAPITAL LETTER OPEN O */ \
+	  0x0254, /* LATIN SMALL LETTER OPEN O */ }, \
+	{ 0x0222, /* LATIN CAPITAL LETTER OU */ \
+	  0x0223, /* LATIN SMALL LETTER OU */ }, \
+	{ 0x0050, /* LATIN CAPITAL LETTER P */ \
+	  0x0070, /* LATIN SMALL LETTER P */ }, \
+	{ 0x1E54, /* LATIN CAPITAL LETTER P WITH ACUTE */ \
+	  0x1E55, /* LATIN SMALL LETTER P WITH ACUTE */ }, \
+	{ 0x1E56, /* LATIN CAPITAL LETTER P WITH DOT ABOVE */ \
+	  0x1E57, /* LATIN SMALL LETTER P WITH DOT ABOVE */ }, \
+	{ 0xA752, /* LATIN CAPITAL LETTER P WITH FLOURISH */ \
+	  0xA753, /* LATIN SMALL LETTER P WITH FLOURISH */ }, \
+	{ 0x01A4, /* LATIN CAPITAL LETTER P WITH HOOK */ \
+	  0x01A5, /* LATIN SMALL LETTER P WITH HOOK */ }, \
+	{ 0xA754, /* LATIN CAPITAL LETTER P WITH SQUIRREL TAIL */ \
+	  0xA755, /* LATIN SMALL LETTER P WITH SQUIRREL TAIL */ }, \
+	{ 0x2C63, /* LATIN CAPITAL LETTER P WITH STROKE */ \
+	  0x1D7D, /* LATIN SMALL LETTER P WITH STROKE */ }, \
+	{ 0xA750, /* LATIN CAPITAL LETTER P WITH STROKE THROUGH DESCENDER */ \
+	  0xA751, /* LATIN SMALL LETTER P WITH STROKE THROUGH DESCENDER */ }, \
+	{ 0x0051, /* LATIN CAPITAL LETTER Q */ \
+	  0x0071, /* LATIN SMALL LETTER Q */ }, \
+	{ 0xA758, /* LATIN CAPITAL LETTER Q WITH DIAGONAL STROKE */ \
+	  0xA759, /* LATIN SMALL LETTER Q WITH DIAGONAL STROKE */ }, \
+	{ 0xA756, /* LATIN CAPITAL LETTER Q WITH STROKE THROUGH DESCENDER */ \
+	  0xA757, /* LATIN SMALL LETTER Q WITH STROKE THROUGH DESCENDER */ }, \
+	{ 0x0052, /* LATIN CAPITAL LETTER R */ \
+	  0x0072, /* LATIN SMALL LETTER R */ }, \
+	{ 0xA75A, /* LATIN CAPITAL LETTER R ROTUNDA */ \
+	  0xA75B, /* LATIN SMALL LETTER R ROTUNDA */ }, \
+	{ 0x0154, /* LATIN CAPITAL LETTER R WITH ACUTE */ \
+	  0x0155, /* LATIN SMALL LETTER R WITH ACUTE */ }, \
+	{ 0x0158, /* LATIN CAPITAL LETTER R WITH CARON */ \
+	  0x0159, /* LATIN SMALL LETTER R WITH CARON */ }, \
+	{ 0x0156, /* LATIN CAPITAL LETTER R WITH CEDILLA */ \
+	  0x0157, /* LATIN SMALL LETTER R WITH CEDILLA */ }, \
+	{ 0x1E58, /* LATIN CAPITAL LETTER R WITH DOT ABOVE */ \
+	  0x1E59, /* LATIN SMALL LETTER R WITH DOT ABOVE */ }, \
+	{ 0x1E5A, /* LATIN CAPITAL LETTER R WITH DOT BELOW */ \
+	  0x1E5B, /* LATIN SMALL LETTER R WITH DOT BELOW */ }, \
+	{ 0x1E5C, /* LATIN CAPITAL LETTER R WITH DOT BELOW AND MACRON */ \
+	  0x1E5D, /* LATIN SMALL LETTER R WITH DOT BELOW AND MACRON */ }, \
+	{ 0x0210, /* LATIN CAPITAL LETTER R WITH DOUBLE GRAVE */ \
+	  0x0211, /* LATIN SMALL LETTER R WITH DOUBLE GRAVE */ }, \
+	{ 0x0212, /* LATIN CAPITAL LETTER R WITH INVERTED BREVE */ \
+	  0x0213, /* LATIN SMALL LETTER R WITH INVERTED BREVE */ }, \
+	{ 0x1E5E, /* LATIN CAPITAL LETTER R WITH LINE BELOW */ \
+	  0x1E5F, /* LATIN SMALL LETTER R WITH LINE BELOW */ }, \
+	{ 0xA7A6, /* LATIN CAPITAL LETTER R WITH OBLIQUE STROKE */ \
+	  0xA7A7, /* LATIN SMALL LETTER R WITH OBLIQUE STROKE */ }, \
+	{ 0x024C, /* LATIN CAPITAL LETTER R WITH STROKE */ \
+	  0x024D, /* LATIN SMALL LETTER R WITH STROKE */ }, \
+	{ 0x2C64, /* LATIN CAPITAL LETTER R WITH TAIL */ \
+	  0x027D, /* LATIN SMALL LETTER R WITH TAIL */ }, \
+	{ 0xA73E, /* LATIN CAPITAL LETTER REVERSED C WITH DOT */ \
+	  0xA73F, /* LATIN SMALL LETTER REVERSED C WITH DOT */ }, \
+	{ 0x018E, /* LATIN CAPITAL LETTER REVERSED E */ \
+	  0x0258, /* LATIN SMALL LETTER REVERSED E */ }, \
+	{ 0xA7AB, /* LATIN CAPITAL LETTER REVERSED OPEN E */ \
+	  0x025C, /* LATIN SMALL LETTER REVERSED OPEN E */ }, \
+	{ 0xA75C, /* LATIN CAPITAL LETTER RUM ROTUNDA */ \
+	  0xA75D, /* LATIN SMALL LETTER RUM ROTUNDA */ }, \
+	{ 0x0053, /* LATIN CAPITAL LETTER S */ \
+	  0x0073, /* LATIN SMALL LETTER S */ }, \
+	{ 0x015A, /* LATIN CAPITAL LETTER S WITH ACUTE */ \
+	  0x015B, /* LATIN SMALL LETTER S WITH ACUTE */ }, \
+	{ 0x1E64, /* LATIN CAPITAL LETTER S WITH ACUTE AND DOT ABOVE */ \
+	  0x1E65, /* LATIN SMALL LETTER S WITH ACUTE AND DOT ABOVE */ }, \
+	{ 0x0160, /* LATIN CAPITAL LETTER S WITH CARON */ \
+	  0x0161, /* LATIN SMALL LETTER S WITH CARON */ }, \
+	{ 0x1E66, /* LATIN CAPITAL LETTER S WITH CARON AND DOT ABOVE */ \
+	  0x1E67, /* LATIN SMALL LETTER S WITH CARON AND DOT ABOVE */ }, \
+	{ 0x015E, /* LATIN CAPITAL LETTER S WITH CEDILLA */ \
+	  0x015F, /* LATIN SMALL LETTER S WITH CEDILLA */ }, \
+	{ 0x015C, /* LATIN CAPITAL LETTER S WITH CIRCUMFLEX */ \
+	  0x015D, /* LATIN SMALL LETTER S WITH CIRCUMFLEX */ }, \
+	{ 0x0218, /* LATIN CAPITAL LETTER S WITH COMMA BELOW */ \
+	  0x0219, /* LATIN SMALL LETTER S WITH COMMA BELOW */ }, \
+	{ 0x1E60, /* LATIN CAPITAL LETTER S WITH DOT ABOVE */ \
+	  0x1E61, /* LATIN SMALL LETTER S WITH DOT ABOVE */ }, \
+	{ 0x1E62, /* LATIN CAPITAL LETTER S WITH DOT BELOW */ \
+	  0x1E63, /* LATIN SMALL LETTER S WITH DOT BELOW */ }, \
+	{ 0x1E68, /* LATIN CAPITAL LETTER S WITH DOT BELOW AND DOT ABOVE */ \
+	  0x1E69, /* LATIN SMALL LETTER S WITH DOT BELOW AND DOT ABOVE */ }, \
+	{ 0xA7A8, /* LATIN CAPITAL LETTER S WITH OBLIQUE STROKE */ \
+	  0xA7A9, /* LATIN SMALL LETTER S WITH OBLIQUE STROKE */ }, \
+	{ 0x2C7E, /* LATIN CAPITAL LETTER S WITH SWASH TAIL */ \
+	  0x023F, /* LATIN SMALL LETTER S WITH SWASH TAIL */ }, \
+	{ 0xA78B, /* LATIN CAPITAL LETTER SALTILLO */ \
+	  0xA78C, /* LATIN SMALL LETTER SALTILLO */ }, \
+	{ 0x018F, /* LATIN CAPITAL LETTER SCHWA */ \
+	  0x0259, /* LATIN SMALL LETTER SCHWA */ }, \
+	{ 0xA7AC, /* LATIN CAPITAL LETTER SCRIPT G */ \
+	  0x0261, /* LATIN SMALL LETTER SCRIPT G */ }, \
+	{ 0x1E9E, /* LATIN CAPITAL LETTER SHARP S */ \
+	  0x00DF, /* LATIN SMALL LETTER SHARP S */ }, \
+	{ 0x0054, /* LATIN CAPITAL LETTER T */ \
+	  0x0074, /* LATIN SMALL LETTER T */ }, \
+	{ 0x0164, /* LATIN CAPITAL LETTER T WITH CARON */ \
+	  0x0165, /* LATIN SMALL LETTER T WITH CARON */ }, \
+	{ 0x0162, /* LATIN CAPITAL LETTER T WITH CEDILLA */ \
+	  0x0163, /* LATIN SMALL LETTER T WITH CEDILLA */ }, \
+	{ 0x1E70, /* LATIN CAPITAL LETTER T WITH CIRCUMFLEX BELOW */ \
+	  0x1E71, /* LATIN SMALL LETTER T WITH CIRCUMFLEX BELOW */ }, \
+	{ 0x021A, /* LATIN CAPITAL LETTER T WITH COMMA BELOW */ \
+	  0x021B, /* LATIN SMALL LETTER T WITH COMMA BELOW */ }, \
+	{ 0x023E, /* LATIN CAPITAL LETTER T WITH DIAGONAL STROKE */ \
+	  0x2C66, /* LATIN SMALL LETTER T WITH DIAGONAL STROKE */ }, \
+	{ 0x1E6A, /* LATIN CAPITAL LETTER T WITH DOT ABOVE */ \
+	  0x1E6B, /* LATIN SMALL LETTER T WITH DOT ABOVE */ }, \
+	{ 0x1E6C, /* LATIN CAPITAL LETTER T WITH DOT BELOW */ \
+	  0x1E6D, /* LATIN SMALL LETTER T WITH DOT BELOW */ }, \
+	{ 0x01AC, /* LATIN CAPITAL LETTER T WITH HOOK */ \
+	  0x01AD, /* LATIN SMALL LETTER T WITH HOOK */ }, \
+	{ 0x1E6E, /* LATIN CAPITAL LETTER T WITH LINE BELOW */ \
+	  0x1E6F, /* LATIN SMALL LETTER T WITH LINE BELOW */ }, \
+	{ 0x01AE, /* LATIN CAPITAL LETTER T WITH RETROFLEX HOOK */ \
+	  0x0288, /* LATIN SMALL LETTER T WITH RETROFLEX HOOK */ }, \
+	{ 0x0166, /* LATIN CAPITAL LETTER T WITH STROKE */ \
+	  0x0167, /* LATIN SMALL LETTER T WITH STROKE */ }, \
+	{ 0x00DE, /* LATIN CAPITAL LETTER THORN */ \
+	  0x00FE, /* LATIN SMALL LETTER THORN */ }, \
+	{ 0xA764, /* LATIN CAPITAL LETTER THORN WITH STROKE */ \
+	  0xA765, /* LATIN SMALL LETTER THORN WITH STROKE */ }, \
+	{ 0xA766, /* LATIN CAPITAL LETTER THORN WITH STROKE THROUGH DESCENDER */ \
+	  0xA767, /* LATIN SMALL LETTER THORN WITH STROKE THROUGH DESCENDER */ }, \
+	{ 0x01BC, /* LATIN CAPITAL LETTER TONE FIVE */ \
+	  0x01BD, /* LATIN SMALL LETTER TONE FIVE */ }, \
+	{ 0x0184, /* LATIN CAPITAL LETTER TONE SIX */ \
+	  0x0185, /* LATIN SMALL LETTER TONE SIX */ }, \
+	{ 0x01A7, /* LATIN CAPITAL LETTER TONE TWO */ \
+	  0x01A8, /* LATIN SMALL LETTER TONE TWO */ }, \
+	{ 0xA72A, /* LATIN CAPITAL LETTER TRESILLO */ \
+	  0xA72B, /* LATIN SMALL LETTER TRESILLO */ }, \
+	{ 0x2C6F, /* LATIN CAPITAL LETTER TURNED A */ \
+	  0x0250, /* LATIN SMALL LETTER TURNED A */ }, \
+	{ 0x2C70, /* LATIN CAPITAL LETTER TURNED ALPHA */ \
+	  0x0252, /* LATIN SMALL LETTER TURNED ALPHA */ }, \
+	{ 0xA78D, /* LATIN CAPITAL LETTER TURNED H */ \
+	  0x0265, /* LATIN SMALL LETTER TURNED H */ }, \
+	{ 0xA77E, /* LATIN CAPITAL LETTER TURNED INSULAR G */ \
+	  0xA77F, /* LATIN SMALL LETTER TURNED INSULAR G */ }, \
+	{ 0xA7B0, /* LATIN CAPITAL LETTER TURNED K */ \
+	  0x029E, /* LATIN SMALL LETTER TURNED K */ }, \
+	{ 0xA780, /* LATIN CAPITAL LETTER TURNED L */ \
+	  0xA781, /* LATIN SMALL LETTER TURNED L */ }, \
+	{ 0x019C, /* LATIN CAPITAL LETTER TURNED M */ \
+	  0x026F, /* LATIN SMALL LETTER TURNED M */ }, \
+	{ 0xA7B1, /* LATIN CAPITAL LETTER TURNED T */ \
+	  0x0287, /* LATIN SMALL LETTER TURNED T */ }, \
+	{ 0x0245, /* LATIN CAPITAL LETTER TURNED V */ \
+	  0x028C, /* LATIN SMALL LETTER TURNED V */ }, \
+	{ 0xA728, /* LATIN CAPITAL LETTER TZ */ \
+	  0xA729, /* LATIN SMALL LETTER TZ */ }, \
+	{ 0x0055, /* LATIN CAPITAL LETTER U */ \
+	  0x0075, /* LATIN SMALL LETTER U */ }, \
+	{ 0x0244, /* LATIN CAPITAL LETTER U BAR */ \
+	  0x0289, /* LATIN SMALL LETTER U BAR */ }, \
+	{ 0x00DA, /* LATIN CAPITAL LETTER U WITH ACUTE */ \
+	  0x00FA, /* LATIN SMALL LETTER U WITH ACUTE */ }, \
+	{ 0x016C, /* LATIN CAPITAL LETTER U WITH BREVE */ \
+	  0x016D, /* LATIN SMALL LETTER U WITH BREVE */ }, \
+	{ 0x01D3, /* LATIN CAPITAL LETTER U WITH CARON */ \
+	  0x01D4, /* LATIN SMALL LETTER U WITH CARON */ }, \
+	{ 0x00DB, /* LATIN CAPITAL LETTER U WITH CIRCUMFLEX */ \
+	  0x00FB, /* LATIN SMALL LETTER U WITH CIRCUMFLEX */ }, \
+	{ 0x1E76, /* LATIN CAPITAL LETTER U WITH CIRCUMFLEX BELOW */ \
+	  0x1E77, /* LATIN SMALL LETTER U WITH CIRCUMFLEX BELOW */ }, \
+	{ 0x00DC, /* LATIN CAPITAL LETTER U WITH DIAERESIS */ \
+	  0x00FC, /* LATIN SMALL LETTER U WITH DIAERESIS */ }, \
+	{ 0x01D7, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND ACUTE */ \
+	  0x01D8, /* LATIN SMALL LETTER U WITH DIAERESIS AND ACUTE */ }, \
+	{ 0x01D9, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND CARON */ \
+	  0x01DA, /* LATIN SMALL LETTER U WITH DIAERESIS AND CARON */ }, \
+	{ 0x01DB, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND GRAVE */ \
+	  0x01DC, /* LATIN SMALL LETTER U WITH DIAERESIS AND GRAVE */ }, \
+	{ 0x01D5, /* LATIN CAPITAL LETTER U WITH DIAERESIS AND MACRON */ \
+	  0x01D6, /* LATIN SMALL LETTER U WITH DIAERESIS AND MACRON */ }, \
+	{ 0x1E72, /* LATIN CAPITAL LETTER U WITH DIAERESIS BELOW */ \
+	  0x1E73, /* LATIN SMALL LETTER U WITH DIAERESIS BELOW */ }, \
+	{ 0x1EE4, /* LATIN CAPITAL LETTER U WITH DOT BELOW */ \
+	  0x1EE5, /* LATIN SMALL LETTER U WITH DOT BELOW */ }, \
+	{ 0x0170, /* LATIN CAPITAL LETTER U WITH DOUBLE ACUTE */ \
+	  0x0171, /* LATIN SMALL LETTER U WITH DOUBLE ACUTE */ }, \
+	{ 0x0214, /* LATIN CAPITAL LETTER U WITH DOUBLE GRAVE */ \
+	  0x0215, /* LATIN SMALL LETTER U WITH DOUBLE GRAVE */ }, \
+	{ 0x00D9, /* LATIN CAPITAL LETTER U WITH GRAVE */ \
+	  0x00F9, /* LATIN SMALL LETTER U WITH GRAVE */ }, \
+	{ 0x1EE6, /* LATIN CAPITAL LETTER U WITH HOOK ABOVE */ \
+	  0x1EE7, /* LATIN SMALL LETTER U WITH HOOK ABOVE */ }, \
+	{ 0x01AF, /* LATIN CAPITAL LETTER U WITH HORN */ \
+	  0x01B0, /* LATIN SMALL LETTER U WITH HORN */ }, \
+	{ 0x1EE8, /* LATIN CAPITAL LETTER U WITH HORN AND ACUTE */ \
+	  0x1EE9, /* LATIN SMALL LETTER U WITH HORN AND ACUTE */ }, \
+	{ 0x1EF0, /* LATIN CAPITAL LETTER U WITH HORN AND DOT BELOW */ \
+	  0x1EF1, /* LATIN SMALL LETTER U WITH HORN AND DOT BELOW */ }, \
+	{ 0x1EEA, /* LATIN CAPITAL LETTER U WITH HORN AND GRAVE */ \
+	  0x1EEB, /* LATIN SMALL LETTER U WITH HORN AND GRAVE */ }, \
+	{ 0x1EEC, /* LATIN CAPITAL LETTER U WITH HORN AND HOOK ABOVE */ \
+	  0x1EED, /* LATIN SMALL LETTER U WITH HORN AND HOOK ABOVE */ }, \
+	{ 0x1EEE, /* LATIN CAPITAL LETTER U WITH HORN AND TILDE */ \
+	  0x1EEF, /* LATIN SMALL LETTER U WITH HORN AND TILDE */ }, \
+	{ 0x0216, /* LATIN CAPITAL LETTER U WITH INVERTED BREVE */ \
+	  0x0217, /* LATIN SMALL LETTER U WITH INVERTED BREVE */ }, \
+	{ 0x016A, /* LATIN CAPITAL LETTER U WITH MACRON */ \
+	  0x016B, /* LATIN SMALL LETTER U WITH MACRON */ }, \
+	{ 0x1E7A, /* LATIN CAPITAL LETTER U WITH MACRON AND DIAERESIS */ \
+	  0x1E7B, /* LATIN SMALL LETTER U WITH MACRON AND DIAERESIS */ }, \
+	{ 0x0172, /* LATIN CAPITAL LETTER U WITH OGONEK */ \
+	  0x0173, /* LATIN SMALL LETTER U WITH OGONEK */ }, \
+	{ 0x016E, /* LATIN CAPITAL LETTER U WITH RING ABOVE */ \
+	  0x016F, /* LATIN SMALL LETTER U WITH RING ABOVE */ }, \
+	{ 0xA7B8, /* LATIN CAPITAL LETTER U WITH STROKE */ \
+	  0xA7B9, /* LATIN SMALL LETTER U WITH STROKE */ }, \
+	{ 0x0168, /* LATIN CAPITAL LETTER U WITH TILDE */ \
+	  0x0169, /* LATIN SMALL LETTER U WITH TILDE */ }, \
+	{ 0x1E78, /* LATIN CAPITAL LETTER U WITH TILDE AND ACUTE */ \
+	  0x1E79, /* LATIN SMALL LETTER U WITH TILDE AND ACUTE */ }, \
+	{ 0x1E74, /* LATIN CAPITAL LETTER U WITH TILDE BELOW */ \
+	  0x1E75, /* LATIN SMALL LETTER U WITH TILDE BELOW */ }, \
+	{ 0x01B1, /* LATIN CAPITAL LETTER UPSILON */ \
+	  0x028A, /* LATIN SMALL LETTER UPSILON */ }, \
+	{ 0x0056, /* LATIN CAPITAL LETTER V */ \
+	  0x0076, /* LATIN SMALL LETTER V */ }, \
+	{ 0xA75E, /* LATIN CAPITAL LETTER V WITH DIAGONAL STROKE */ \
+	  0xA75F, /* LATIN SMALL LETTER V WITH DIAGONAL STROKE */ }, \
+	{ 0x1E7E, /* LATIN CAPITAL LETTER V WITH DOT BELOW */ \
+	  0x1E7F, /* LATIN SMALL LETTER V WITH DOT BELOW */ }, \
+	{ 0x01B2, /* LATIN CAPITAL LETTER V WITH HOOK */ \
+	  0x028B, /* LATIN SMALL LETTER V WITH HOOK */ }, \
+	{ 0x1E7C, /* LATIN CAPITAL LETTER V WITH TILDE */ \
+	  0x1E7D, /* LATIN SMALL LETTER V WITH TILDE */ }, \
+	{ 0xA768, /* LATIN CAPITAL LETTER VEND */ \
+	  0xA769, /* LATIN SMALL LETTER VEND */ }, \
+	{ 0xA762, /* LATIN CAPITAL LETTER VISIGOTHIC Z */ \
+	  0xA763, /* LATIN SMALL LETTER VISIGOTHIC Z */ }, \
+	{ 0xA79A, /* LATIN CAPITAL LETTER VOLAPUK AE */ \
+	  0xA79B, /* LATIN SMALL LETTER VOLAPUK AE */ }, \
+	{ 0xA79C, /* LATIN CAPITAL LETTER VOLAPUK OE */ \
+	  0xA79D, /* LATIN SMALL LETTER VOLAPUK OE */ }, \
+	{ 0xA79E, /* LATIN CAPITAL LETTER VOLAPUK UE */ \
+	  0xA79F, /* LATIN SMALL LETTER VOLAPUK UE */ }, \
+	{ 0xA760, /* LATIN CAPITAL LETTER VY */ \
+	  0xA761, /* LATIN SMALL LETTER VY */ }, \
+	{ 0x0057, /* LATIN CAPITAL LETTER W */ \
+	  0x0077, /* LATIN SMALL LETTER W */ }, \
+	{ 0x1E82, /* LATIN CAPITAL LETTER W WITH ACUTE */ \
+	  0x1E83, /* LATIN SMALL LETTER W WITH ACUTE */ }, \
+	{ 0x0174, /* LATIN CAPITAL LETTER W WITH CIRCUMFLEX */ \
+	  0x0175, /* LATIN SMALL LETTER W WITH CIRCUMFLEX */ }, \
+	{ 0x1E84, /* LATIN CAPITAL LETTER W WITH DIAERESIS */ \
+	  0x1E85, /* LATIN SMALL LETTER W WITH DIAERESIS */ }, \
+	{ 0x1E86, /* LATIN CAPITAL LETTER W WITH DOT ABOVE */ \
+	  0x1E87, /* LATIN SMALL LETTER W WITH DOT ABOVE */ }, \
+	{ 0x1E88, /* LATIN CAPITAL LETTER W WITH DOT BELOW */ \
+	  0x1E89, /* LATIN SMALL LETTER W WITH DOT BELOW */ }, \
+	{ 0x1E80, /* LATIN CAPITAL LETTER W WITH GRAVE */ \
+	  0x1E81, /* LATIN SMALL LETTER W WITH GRAVE */ }, \
+	{ 0x2C72, /* LATIN CAPITAL LETTER W WITH HOOK */ \
+	  0x2C73, /* LATIN SMALL LETTER W WITH HOOK */ }, \
+	{ 0x0058, /* LATIN CAPITAL LETTER X */ \
+	  0x0078, /* LATIN SMALL LETTER X */ }, \
+	{ 0x1E8C, /* LATIN CAPITAL LETTER X WITH DIAERESIS */ \
+	  0x1E8D, /* LATIN SMALL LETTER X WITH DIAERESIS */ }, \
+	{ 0x1E8A, /* LATIN CAPITAL LETTER X WITH DOT ABOVE */ \
+	  0x1E8B, /* LATIN SMALL LETTER X WITH DOT ABOVE */ }, \
+	{ 0x0059, /* LATIN CAPITAL LETTER Y */ \
+	  0x0079, /* LATIN SMALL LETTER Y */ }, \
+	{ 0x00DD, /* LATIN CAPITAL LETTER Y WITH ACUTE */ \
+	  0x00FD, /* LATIN SMALL LETTER Y WITH ACUTE */ }, \
+	{ 0x0176, /* LATIN CAPITAL LETTER Y WITH CIRCUMFLEX */ \
+	  0x0177, /* LATIN SMALL LETTER Y WITH CIRCUMFLEX */ }, \
+	{ 0x0178, /* LATIN CAPITAL LETTER Y WITH DIAERESIS */ \
+	  0x00FF, /* LATIN SMALL LETTER Y WITH DIAERESIS */ }, \
+	{ 0x1E8E, /* LATIN CAPITAL LETTER Y WITH DOT ABOVE */ \
+	  0x1E8F, /* LATIN SMALL LETTER Y WITH DOT ABOVE */ }, \
+	{ 0x1EF4, /* LATIN CAPITAL LETTER Y WITH DOT BELOW */ \
+	  0x1EF5, /* LATIN SMALL LETTER Y WITH DOT BELOW */ }, \
+	{ 0x1EF2, /* LATIN CAPITAL LETTER Y WITH GRAVE */ \
+	  0x1EF3, /* LATIN SMALL LETTER Y WITH GRAVE */ }, \
+	{ 0x01B3, /* LATIN CAPITAL LETTER Y WITH HOOK */ \
+	  0x01B4, /* LATIN SMALL LETTER Y WITH HOOK */ }, \
+	{ 0x1EF6, /* LATIN CAPITAL LETTER Y WITH HOOK ABOVE */ \
+	  0x1EF7, /* LATIN SMALL LETTER Y WITH HOOK ABOVE */ }, \
+	{ 0x1EFE, /* LATIN CAPITAL LETTER Y WITH LOOP */ \
+	  0x1EFF, /* LATIN SMALL LETTER Y WITH LOOP */ }, \
+	{ 0x0232, /* LATIN CAPITAL LETTER Y WITH MACRON */ \
+	  0x0233, /* LATIN SMALL LETTER Y WITH MACRON */ }, \
+	{ 0x024E, /* LATIN CAPITAL LETTER Y WITH STROKE */ \
+	  0x024F, /* LATIN SMALL LETTER Y WITH STROKE */ }, \
+	{ 0x1EF8, /* LATIN CAPITAL LETTER Y WITH TILDE */ \
+	  0x1EF9, /* LATIN SMALL LETTER Y WITH TILDE */ }, \
+	{ 0x021C, /* LATIN CAPITAL LETTER YOGH */ \
+	  0x021D, /* LATIN SMALL LETTER YOGH */ }, \
+	{ 0x005A, /* LATIN CAPITAL LETTER Z */ \
+	  0x007A, /* LATIN SMALL LETTER Z */ }, \
+	{ 0x0179, /* LATIN CAPITAL LETTER Z WITH ACUTE */ \
+	  0x017A, /* LATIN SMALL LETTER Z WITH ACUTE */ }, \
+	{ 0x017D, /* LATIN CAPITAL LETTER Z WITH CARON */ \
+	  0x017E, /* LATIN SMALL LETTER Z WITH CARON */ }, \
+	{ 0x1E90, /* LATIN CAPITAL LETTER Z WITH CIRCUMFLEX */ \
+	  0x1E91, /* LATIN SMALL LETTER Z WITH CIRCUMFLEX */ }, \
+	{ 0x2C6B, /* LATIN CAPITAL LETTER Z WITH DESCENDER */ \
+	  0x2C6C, /* LATIN SMALL LETTER Z WITH DESCENDER */ }, \
+	{ 0x017B, /* LATIN CAPITAL LETTER Z WITH DOT ABOVE */ \
+	  0x017C, /* LATIN SMALL LETTER Z WITH DOT ABOVE */ }, \
+	{ 0x1E92, /* LATIN CAPITAL LETTER Z WITH DOT BELOW */ \
+	  0x1E93, /* LATIN SMALL LETTER Z WITH DOT BELOW */ }, \
+	{ 0x0224, /* LATIN CAPITAL LETTER Z WITH HOOK */ \
+	  0x0225, /* LATIN SMALL LETTER Z WITH HOOK */ }, \
+	{ 0x1E94, /* LATIN CAPITAL LETTER Z WITH LINE BELOW */ \
+	  0x1E95, /* LATIN SMALL LETTER Z WITH LINE BELOW */ }, \
+	{ 0x01B5, /* LATIN CAPITAL LETTER Z WITH STROKE */ \
+	  0x01B6, /* LATIN SMALL LETTER Z WITH STROKE */ }, \
+	{ 0x2C7F, /* LATIN CAPITAL LETTER Z WITH SWASH TAIL */ \
+	  0x0240, /* LATIN SMALL LETTER Z WITH SWASH TAIL */ }, \
+	{ 0x0000, /* END OF LIST CAPITAL LETTERS */ \
+	  0x0000, /* END OF LIST SMALL LETTERS */ }, \
+}
+
+/*
+ * Correspondence table for small and capital letters of codepage 437.
+ * Letters A-Z are handled in code.
+ */
+#define CP437_CAPITALIZATION_TABLE { \
+	{ 0x00C4, /* LATIN CAPITAL LETTER A WITH DIAERESIS */ \
+	  0x00E4, /* LATIN SMALL LETTER A WITH DIAERESIS */ }, \
+	{ 0x00C5, /* LATIN CAPITAL LETTER A WITH RING ABOVE */ \
+	  0x00E5, /* LATIN SMALL LETTER A WITH RING ABOVE */ }, \
+	{ 0x00C6, /* LATIN CAPITAL LETTER AE */ \
+	  0x00E6, /* LATIN SMALL LETTER AE */ }, \
+	{ 0x00C7, /* LATIN CAPITAL LETTER C WITH CEDILLA */ \
+	  0x00E7, /* LATIN SMALL LETTER C WITH CEDILLA */ }, \
+	{ 0x00C9, /* LATIN CAPITAL LETTER E WITH ACUTE */ \
+	  0x00E9, /* LATIN SMALL LETTER E WITH ACUTE */ }, \
+	{ 0x00D1, /* LATIN CAPITAL LETTER N WITH TILDE */ \
+	  0x00F1, /* LATIN SMALL LETTER N WITH TILDE */ }, \
+	{ 0x00D6, /* LATIN CAPITAL LETTER O WITH DIAERESIS */ \
+	  0x00F6, /* LATIN SMALL LETTER O WITH DIAERESIS */ }, \
+	{ 0x00DC, /* LATIN CAPITAL LETTER U WITH DIAERESIS */ \
+	  0x00FC, /* LATIN SMALL LETTER U WITH DIAERESIS */ }, \
+	{ 0x03A3, /* GREEK CAPITAL LETTER SIGMA */ \
+	  0x03C3, /* GREEK SMALL LETTER SIGMA */ }, \
+	{ 0x03A6, /* GREEK CAPITAL LETTER PHI */ \
+	  0x03C6, /* GREEK SMALL LETTER PHI */ }, \
+	{ 0x0000, 0x0000, }, \
+}
+
+/*
+ * Correspondence table for small and capital letters of codepage 1250.
+ * Letters A-Z are handled in code.
+ */
+#define CP1250_CAPITALIZATION_TABLE { \
+	{ 0x00C1, /* LATIN CAPITAL LETTER A WITH ACUTE */ \
+	  0x00E1, /* LATIN SMALL LETTER A WITH ACUTE */ }, \
+	{ 0x00C2, /* LATIN CAPITAL LETTER A WITH CIRCUMFLEX */ \
+	  0x00E2, /* LATIN SMALL LETTER A WITH CIRCUMFLEX */ }, \
+	{ 0x00C4, /* LATIN CAPITAL LETTER A WITH DIAERESIS */ \
+	  0x00E4, /* LATIN SMALL LETTER A WITH DIAERESIS */ }, \
+	{ 0x00C7, /* LATIN CAPITAL LETTER C WITH CEDILLA */ \
+	  0x00E7, /* LATIN SMALL LETTER C WITH CEDILLA */ }, \
+	{ 0x00C9, /* LATIN CAPITAL LETTER E WITH ACUTE */ \
+	  0x00E9, /* LATIN SMALL LETTER E WITH ACUTE */ }, \
+	{ 0x00CB, /* LATIN CAPITAL LETTER E WITH DIAERESIS */ \
+	  0x00EB, /* LATIN SMALL LETTER E WITH DIAERESIS */ }, \
+	{ 0x00CD, /* LATIN CAPITAL LETTER I WITH ACUTE */ \
+	  0x00ED, /* LATIN SMALL LETTER I WITH ACUTE */ }, \
+	{ 0x00CE, /* LATIN CAPITAL LETTER I WITH CIRCUMFLEX */ \
+	  0x00EE, /* LATIN SMALL LETTER I WITH CIRCUMFLEX */ }, \
+	{ 0x00D3, /* LATIN CAPITAL LETTER O WITH ACUTE */ \
+	  0x00F3, /* LATIN SMALL LETTER O WITH ACUTE */ }, \
+	{ 0x00D4, /* LATIN CAPITAL LETTER O WITH CIRCUMFLEX */ \
+	  0x00F4, /* LATIN SMALL LETTER O WITH CIRCUMFLEX */ }, \
+	{ 0x00D6, /* LATIN CAPITAL LETTER O WITH DIAERESIS */ \
+	  0x00F6, /* LATIN SMALL LETTER O WITH DIAERESIS */ }, \
+	{ 0x00DA, /* LATIN CAPITAL LETTER U WITH ACUTE */ \
+	  0x00FA, /* LATIN SMALL LETTER U WITH ACUTE */ }, \
+	{ 0x00DC, /* LATIN CAPITAL LETTER U WITH DIAERESIS */ \
+	  0x00FC, /* LATIN SMALL LETTER U WITH DIAERESIS */ }, \
+	{ 0x00DD, /* LATIN CAPITAL LETTER Y WITH ACUTE */ \
+	  0x00FD, /* LATIN SMALL LETTER Y WITH ACUTE */ }, \
+	{ 0x0102, /* LATIN CAPITAL LETTER A WITH BREVE */ \
+	  0x0103, /* LATIN SMALL LETTER A WITH BREVE */ }, \
+	{ 0x0104, /* LATIN CAPITAL LETTER A WITH OGONEK */ \
+	  0x0105, /* LATIN SMALL LETTER A WITH OGONEK */ }, \
+	{ 0x0106, /* LATIN CAPITAL LETTER C WITH ACUTE */ \
+	  0x0107, /* LATIN SMALL LETTER C WITH ACUTE */ }, \
+	{ 0x010C, /* LATIN CAPITAL LETTER C WITH CARON */ \
+	  0x010D, /* LATIN SMALL LETTER C WITH CARON */ }, \
+	{ 0x010E, /* LATIN CAPITAL LETTER D WITH CARON */ \
+	  0x010F, /* LATIN SMALL LETTER D WITH CARON */ }, \
+	{ 0x0110, /* LATIN CAPITAL LETTER D WITH STROKE */ \
+	  0x0111, /* LATIN SMALL LETTER D WITH STROKE */ }, \
+	{ 0x0118, /* LATIN CAPITAL LETTER E WITH OGONEK */ \
+	  0x0119, /* LATIN SMALL LETTER E WITH OGONEK */ }, \
+	{ 0x011A, /* LATIN CAPITAL LETTER E WITH CARON */ \
+	  0x011B, /* LATIN SMALL LETTER E WITH CARON */ }, \
+	{ 0x0139, /* LATIN CAPITAL LETTER L WITH ACUTE */ \
+	  0x013A, /* LATIN SMALL LETTER L WITH ACUTE */ }, \
+	{ 0x013D, /* LATIN CAPITAL LETTER L WITH CARON */ \
+	  0x013E, /* LATIN SMALL LETTER L WITH CARON */ }, \
+	{ 0x0141, /* LATIN CAPITAL LETTER L WITH STROKE */ \
+	  0x0142, /* LATIN SMALL LETTER L WITH STROKE */ }, \
+	{ 0x0143, /* LATIN CAPITAL LETTER N WITH ACUTE */ \
+	  0x0144, /* LATIN SMALL LETTER N WITH ACUTE */ }, \
+	{ 0x0147, /* LATIN CAPITAL LETTER N WITH CARON */ \
+	  0x0148, /* LATIN SMALL LETTER N WITH CARON */ }, \
+	{ 0x0150, /* LATIN CAPITAL LETTER O WITH DOUBLE ACUTE */ \
+	  0x0151, /* LATIN SMALL LETTER O WITH DOUBLE ACUTE */ }, \
+	{ 0x0154, /* LATIN CAPITAL LETTER R WITH ACUTE */ \
+	  0x0155, /* LATIN SMALL LETTER R WITH ACUTE */ }, \
+	{ 0x0158, /* LATIN CAPITAL LETTER R WITH CARON */ \
+	  0x0159, /* LATIN SMALL LETTER R WITH CARON */ }, \
+	{ 0x015A, /* LATIN CAPITAL LETTER S WITH ACUTE */ \
+	  0x015B, /* LATIN SMALL LETTER S WITH ACUTE */ }, \
+	{ 0x015E, /* LATIN CAPITAL LETTER S WITH CEDILLA */ \
+	  0x015F, /* LATIN SMALL LETTER S WITH CEDILLA */ }, \
+	{ 0x0160, /* LATIN CAPITAL LETTER S WITH CARON */ \
+	  0x0161, /* LATIN SMALL LETTER S WITH CARON */ }, \
+	{ 0x0162, /* LATIN CAPITAL LETTER T WITH CEDILLA */ \
+	  0x0163, /* LATIN SMALL LETTER T WITH CEDILLA */ }, \
+	{ 0x0164, /* LATIN CAPITAL LETTER T WITH CARON */ \
+	  0x0165, /* LATIN SMALL LETTER T WITH CARON */ }, \
+	{ 0x016E, /* LATIN CAPITAL LETTER U WITH RING ABOVE */ \
+	  0x016F, /* LATIN SMALL LETTER U WITH RING ABOVE */ }, \
+	{ 0x0170, /* LATIN CAPITAL LETTER U WITH DOUBLE ACUTE */ \
+	  0x0171, /* LATIN SMALL LETTER U WITH DOUBLE ACUTE */ }, \
+	{ 0x0179, /* LATIN CAPITAL LETTER Z WITH ACUTE */ \
+	  0x017A, /* LATIN SMALL LETTER Z WITH ACUTE */ }, \
+	{ 0x017B, /* LATIN CAPITAL LETTER Z WITH DOT ABOVE */ \
+	  0x017C, /* LATIN SMALL LETTER Z WITH DOT ABOVE */ }, \
+	{ 0x017D, /* LATIN CAPITAL LETTER Z WITH CARON */ \
+	  0x017E, /* LATIN SMALL LETTER Z WITH CARON */ }, \
+	{ 0x0000, 0x0000, }, \
+}
diff --git a/include/cavium/atf.h b/include/cavium/atf.h
new file mode 100644
index 0000000..3cf05c4
--- /dev/null
+++ b/include/cavium/atf.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/**
+ * (C) Copyright 2014, Cavium Inc.
+**/
+#ifndef __ATF_H__
+#define __ATF_H__
+#include <cavium/atf_part.h>
+
+ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size);
+ssize_t atf_read_nor(uintptr_t offset, void *buffer, size_t size);
+ssize_t atf_get_pcount(void);
+ssize_t atf_get_part(struct storage_partition *part, unsigned int index);
+ssize_t atf_erase_nor(uintptr_t offset, size_t size);
+ssize_t atf_write_nor(uintptr_t offset, const void *buffer, size_t size);
+ssize_t atf_write_mmc(uintptr_t offset, const void *buffer, size_t size);
+ssize_t atf_dram_size(unsigned int node);
+ssize_t atf_node_count(void);
+ssize_t atf_env_count(void);
+ssize_t atf_env_string(size_t index, char *str);
+
+#endif
diff --git a/include/cavium/atf_part.h b/include/cavium/atf_part.h
new file mode 100644
index 0000000..6c00b01
--- /dev/null
+++ b/include/cavium/atf_part.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/**
+ * (C) Copyright 2014, Cavium Inc.
+**/
+
+#ifndef __ATF_PART_H__
+#define __ATF_PART_H__
+
+struct storage_partition {
+	unsigned int type;
+	unsigned int size;
+	unsigned long offset;
+};
+
+enum {
+	PARTITION_NBL1FW_REST = 0,
+	PARTITION_BL2_BL31 = 1,
+	PARTITION_UBOOT = 2,
+	PARTITION_UEFI = 2,
+	PARTITION_KERNEL = 3,
+	PARTITION_DEVICE_TREE = 4,
+	PARTITION_LAST,
+};
+
+#endif
diff --git a/include/cavium/thunderx_svc.h b/include/cavium/thunderx_svc.h
new file mode 100644
index 0000000..de36d66
--- /dev/null
+++ b/include/cavium/thunderx_svc.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/**
+ * (C) Copyright 2014, Cavium Inc.
+**/
+
+#ifndef __THUNDERX_SVC_H__
+#define __THUNDERX_SVC_H__
+
+/* SMC function IDs for general purpose queries */
+
+#define THUNDERX_SVC_CALL_COUNT		0x4300ff00
+#define THUNDERX_SVC_UID		0x4300ff01
+
+#define THUNDERX_SVC_VERSION		0x4300ff03
+
+#define ARM_STD_SVC_VERSION		0x8400ff03
+
+/* ThunderX Service Calls version numbers */
+#define THUNDERX_VERSION_MAJOR	0x0
+#define THUNDERX_VERSION_MINOR	0x1
+
+#define THUNDERX_MMC_READ		0x43000101
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_MMC_WRITE		0x43000102
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+
+#define THUNDERX_NOR_READ		0x43000111
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_NOR_WRITE		0x43000112
+/* x1 - block address
+ * x2 - size
+ * x3 - buffer address
+ */
+#define THUNDERX_NOR_ERASE		0x43000113
+/* x1 - block address
+ */
+
+#define THUNDERX_PART_COUNT		0x43000201
+#define THUNDERX_GET_PART		0x43000202
+/* x1 - pointer to the buffer
+ * x2 - index
+ */
+
+#define THUNDERX_DRAM_SIZE		0x43000301
+/* x1 - node number
+ */
+
+#define THUNDERX_GTI_SYNC		0x43000401
+
+#define THUNDERX_ENV_COUNT		0x43000501
+#define THUNDERX_ENV_STRING		0x43000502
+/* x1 - index
+ */
+
+#define THUNDERX_NODE_COUNT		0x43000601
+
+#endif /* __THUNDERX_SVC_H__ */
diff --git a/include/cbfs.h b/include/cbfs.h
new file mode 100644
index 0000000..6d4c4d4
--- /dev/null
+++ b/include/cbfs.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ */
+
+#ifndef __CBFS_H
+#define __CBFS_H
+
+#include <compiler.h>
+#include <linux/compiler.h>
+
+enum cbfs_result {
+	CBFS_SUCCESS = 0,
+	CBFS_NOT_INITIALIZED,
+	CBFS_BAD_HEADER,
+	CBFS_BAD_FILE,
+	CBFS_FILE_NOT_FOUND
+};
+
+enum cbfs_filetype {
+	CBFS_TYPE_BOOTBLOCK = 0x01,
+	CBFS_TYPE_CBFSHEADER = 0x02,
+	CBFS_TYPE_STAGE = 0x10,
+	CBFS_TYPE_PAYLOAD = 0x20,
+	CBFS_TYPE_FIT = 0x21,
+	CBFS_TYPE_OPTIONROM = 0x30,
+	CBFS_TYPE_BOOTSPLASH = 0x40,
+	CBFS_TYPE_RAW = 0x50,
+	CBFS_TYPE_VSA = 0x51,
+	CBFS_TYPE_MBI = 0x52,
+	CBFS_TYPE_MICROCODE = 0x53,
+	CBFS_TYPE_FSP = 0x60,
+	CBFS_TYPE_MRC = 0x61,
+	CBFS_TYPE_MMA = 0x62,
+	CBFS_TYPE_EFI = 0x63,
+	CBFS_TYPE_STRUCT = 0x70,
+	CBFS_TYPE_CMOS_DEFAULT = 0xaa,
+	CBFS_TYPE_SPD = 0xab,
+	CBFS_TYPE_MRC_CACHE = 0xac,
+	CBFS_TYPE_CMOS_LAYOUT = 0x01aa
+};
+
+enum {
+	CBFS_HEADER_MAGIC	= 0x4f524243,
+};
+
+/**
+ * struct cbfs_header - header at the start of a CBFS region
+ *
+ * All fields use big-endian format.
+ *
+ * @magic: Magic number (CBFS_HEADER_MAGIC)
+ */
+struct cbfs_header {
+	u32 magic;
+	u32 version;
+	u32 rom_size;
+	u32 boot_block_size;
+	u32 align;
+	u32 offset;
+	u32 pad[2];
+} __packed;
+
+struct cbfs_fileheader {
+	u8 magic[8];
+	u32 len;
+	u32 type;
+	/* offset to struct cbfs_file_attribute or 0 */
+	u32 attributes_offset;
+	u32 offset;
+} __packed;
+
+struct cbfs_cachenode {
+	struct cbfs_cachenode *next;
+	u32 type;
+	void *data;
+	u32 data_length;
+	char *name;
+	u32 name_length;
+	u32 attributes_offset;
+} __packed;
+
+extern enum cbfs_result file_cbfs_result;
+
+/**
+ * file_cbfs_error() - Return a string describing the most recent error
+ * condition.
+ *
+ * @return A pointer to the constant string.
+ */
+const char *file_cbfs_error(void);
+
+/**
+ * cbfs_get_result() - Get the result of the last CBFS operation
+ *
+ *@return last result
+ */
+enum cbfs_result cbfs_get_result(void);
+
+/**
+ * file_cbfs_init() - Initialize the CBFS driver and load metadata into RAM.
+ *
+ * @end_of_rom: Points to the end of the ROM the CBFS should be read
+ *                      from.
+ */
+void file_cbfs_init(uintptr_t end_of_rom);
+
+/**
+ * file_cbfs_get_header() - Get the header structure for the current CBFS.
+ *
+ * @return A pointer to the constant structure, or NULL if there is none.
+ */
+const struct cbfs_header *file_cbfs_get_header(void);
+
+/**
+ * file_cbfs_get_first() - Get a handle for the first file in CBFS.
+ *
+ * @return A handle for the first file in CBFS, NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_get_first(void);
+
+/**
+ * file_cbfs_get_next() - Get a handle to the file after this one in CBFS.
+ *
+ * @file:		A pointer to the handle to advance.
+ */
+void file_cbfs_get_next(const struct cbfs_cachenode **file);
+
+/**
+ * file_cbfs_find() - Find a file with a particular name in CBFS.
+ *
+ * @name:		The name to search for.
+ *
+ * @return A handle to the file, or NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_find(const char *name);
+
+struct cbfs_priv *priv;
+
+/**
+ * cbfs_find_file() - Find a file in a given CBFS
+ *
+ * @cbfs: CBFS to look in (use cbfs_init_mem() to set it up)
+ * @name: Filename to look for
+ * @return pointer to CBFS node if found, else NULL
+ */
+const struct cbfs_cachenode *cbfs_find_file(struct cbfs_priv *cbfs,
+					    const char *name);
+
+/**
+ * cbfs_init_mem() - Set up a new CBFS
+ *
+ * @base: Base address of CBFS
+ * @size: Size of CBFS in bytes
+ * @cbfsp: Returns a pointer to CBFS on success
+ * @return 0 if OK, -ve on error
+ */
+int cbfs_init_mem(ulong base, ulong size, struct cbfs_priv **privp);
+
+
+/***************************************************************************/
+/* All of the functions below can be used without first initializing CBFS. */
+/***************************************************************************/
+
+/**
+ * file_cbfs_find_uncached() - Find a file with a particular name in CBFS
+ * without using the heap.
+ *
+ * @end_of_rom:		Points to the end of the ROM the CBFS should be read
+ *                      from.
+ * @name:		The name to search for.
+ *
+ * @return A handle to the file, or NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom,
+						     const char *name);
+
+/**
+ * file_cbfs_name() - Get the name of a file in CBFS.
+ *
+ * @file:		The handle to the file.
+ *
+ * @return The name of the file, NULL on error.
+ */
+const char *file_cbfs_name(const struct cbfs_cachenode *file);
+
+/**
+ * file_cbfs_size() - Get the size of a file in CBFS.
+ *
+ * @file:		The handle to the file.
+ *
+ * @return The size of the file, zero on error.
+ */
+u32 file_cbfs_size(const struct cbfs_cachenode *file);
+
+/**
+ * file_cbfs_type() - Get the type of a file in CBFS.
+ *
+ * @file:		The handle to the file.
+ *
+ * @return The type of the file, zero on error.
+ */
+u32 file_cbfs_type(const struct cbfs_cachenode *file);
+
+/**
+ * file_cbfs_read() - Read a file from CBFS into RAM
+ *
+ * @file:		A handle to the file to read.
+ * @buffer:		Where to read it into memory.
+ * @maxsize:		Maximum number of bytes to read
+ *
+ * @return If positive or zero, the number of characters read. If negative, an
+ *	   error occurred.
+ */
+long file_cbfs_read(const struct cbfs_cachenode *file, void *buffer,
+		    unsigned long maxsize);
+
+#endif /* __CBFS_H */
diff --git a/include/charset.h b/include/charset.h
new file mode 100644
index 0000000..fde6bdd
--- /dev/null
+++ b/include/charset.h
@@ -0,0 +1,250 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  charset conversion utils
+ *
+ *  Copyright (c) 2017 Rob Clark
+ */
+
+#ifndef __CHARSET_H_
+#define __CHARSET_H_
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#define MAX_UTF8_PER_UTF16 3
+
+/**
+ * console_read_unicode() - read Unicode code point from console
+ *
+ * @code:	pointer to store Unicode code point
+ * Return:	0 = success
+ */
+int console_read_unicode(s32 *code);
+
+/**
+ * utf8_get() - get next UTF-8 code point from buffer
+ *
+ * @src:		pointer to current byte, updated to point to next byte
+ * Return:		code point, or 0 for end of string, or -1 if no legal
+ *			code point is found. In case of an error src points to
+ *			the incorrect byte.
+ */
+s32 utf8_get(const char **src);
+
+/**
+ * utf8_put() - write UTF-8 code point to buffer
+ *
+ * @code:		code point
+ * @dst:		pointer to destination buffer, updated to next position
+ * Return:		-1 if the input parameters are invalid
+ */
+int utf8_put(s32 code, char **dst);
+
+/**
+ * utf8_utf16_strnlen() - length of a truncated utf-8 string after conversion
+ *			  to utf-16
+ *
+ * @src:		utf-8 string
+ * @count:		maximum number of code points to convert
+ * Return:		length in u16 after conversion to utf-16 without the
+ *			trailing \0. If an invalid UTF-8 sequence is hit one
+ *			u16 will be reserved for a replacement character.
+ */
+size_t utf8_utf16_strnlen(const char *src, size_t count);
+
+/**
+ * utf8_utf16_strlen() - length of a utf-8 string after conversion to utf-16
+ *
+ * @src:		utf-8 string
+ * Return:		length in u16 after conversion to utf-16 without the
+ *			trailing \0. If an invalid UTF-8 sequence is hit one
+ *			u16 will be reserved for a replacement character.
+ */
+#define utf8_utf16_strlen(a) utf8_utf16_strnlen((a), SIZE_MAX)
+
+/**
+ * utf8_utf16_strncpy() - copy utf-8 string to utf-16 string
+ *
+ * @dst:		destination buffer
+ * @src:		source buffer
+ * @count:		maximum number of code points to copy
+ * Return:		-1 if the input parameters are invalid
+ */
+int utf8_utf16_strncpy(u16 **dst, const char *src, size_t count);
+
+/**
+ * utf8_utf16_strcpy() - copy utf-8 string to utf-16 string
+ *
+ * @dst:		destination buffer
+ * @src:		source buffer
+ * Return:		-1 if the input parameters are invalid
+ */
+#define utf8_utf16_strcpy(d, s) utf8_utf16_strncpy((d), (s), SIZE_MAX)
+
+/**
+ * utf16_get() - get next UTF-16 code point from buffer
+ *
+ * @src:		pointer to current word, updated to point to next word
+ * Return:		code point, or 0 for end of string, or -1 if no legal
+ *			code point is found. In case of an error src points to
+ *			the incorrect word.
+ */
+s32 utf16_get(const u16 **src);
+
+/**
+ * utf16_put() - write UTF-16 code point to buffer
+ *
+ * @code:		code point
+ * @dst:		pointer to destination buffer, updated to next position
+ * Return:		-1 if the input parameters are invalid
+ */
+int utf16_put(s32 code, u16 **dst);
+
+/**
+ * utf16_strnlen() - length of a truncated utf-16 string
+ *
+ * @src:		utf-16 string
+ * @count:		maximum number of code points to convert
+ * Return:		length in code points. If an invalid UTF-16 sequence is
+ *			hit one position will be reserved for a replacement
+ *			character.
+ */
+size_t utf16_strnlen(const u16 *src, size_t count);
+
+/**
+ * utf16_utf8_strnlen() - length of a truncated utf-16 string after conversion
+ *			  to utf-8
+ *
+ * @src:		utf-16 string
+ * @count:		maximum number of code points to convert
+ * Return:		length in bytes after conversion to utf-8 without the
+ *			trailing \0. If an invalid UTF-16 sequence is hit one
+ *			byte will be reserved for a replacement character.
+ */
+size_t utf16_utf8_strnlen(const u16 *src, size_t count);
+
+/**
+ * utf16_utf8_strlen() - length of a utf-16 string after conversion to utf-8
+ *
+ * @src:		utf-16 string
+ * Return:		length in bytes after conversion to utf-8 without the
+ *			trailing \0. If an invalid UTF-16 sequence is hit one
+ *			byte will be reserved for a replacement character.
+ */
+#define utf16_utf8_strlen(a) utf16_utf8_strnlen((a), SIZE_MAX)
+
+/**
+ * utf16_utf8_strncpy() - copy utf-16 string to utf-8 string
+ *
+ * @dst:		destination buffer
+ * @src:		source buffer
+ * @count:		maximum number of code points to copy
+ * Return:		-1 if the input parameters are invalid
+ */
+int utf16_utf8_strncpy(char **dst, const u16 *src, size_t count);
+
+/**
+ * utf16_utf8_strcpy() - copy utf-16 string to utf-8 string
+ *
+ * @dst:		destination buffer
+ * @src:		source buffer
+ * Return:		-1 if the input parameters are invalid
+ */
+#define utf16_utf8_strcpy(d, s) utf16_utf8_strncpy((d), (s), SIZE_MAX)
+
+/**
+ * utf_to_lower() - convert a Unicode letter to lower case
+ *
+ * @code:		letter to convert
+ * Return:		lower case letter or unchanged letter
+ */
+s32 utf_to_lower(const s32 code);
+
+/**
+ * utf_to_upper() - convert a Unicode letter to upper case
+ *
+ * @code:		letter to convert
+ * Return:		upper case letter or unchanged letter
+ */
+s32 utf_to_upper(const s32 code);
+
+/*
+ * u16_strncmp() - compare two u16 string
+ *
+ * @s1:		first string to compare
+ * @s2:		second string to compare
+ * @n:		maximum number of u16 to compare
+ * Return:	0  if the first n u16 are the same in s1 and s2
+ *		< 0 if the first different u16 in s1 is less than the
+ *		corresponding u16 in s2
+ *		> 0 if the first different u16 in s1 is greater than the
+ *		corresponding u16 in s2
+ */
+int u16_strncmp(const u16 *s1, const u16 *s2, size_t n);
+#define u16_strcmp(s1, s2)	u16_strncmp((s1), (s2), SIZE_MAX)
+
+/**
+ * u16_strlen - count non-zero words
+ *
+ * This function matches wsclen() if the -fshort-wchar compiler flag is set.
+ * In the EFI context we explicitly need a function handling u16 strings.
+ *
+ * @in:			null terminated u16 string
+ * ReturnValue:		number of non-zero words.
+ *			This is not the number of utf-16 letters!
+ */
+size_t u16_strlen(const void *in);
+
+/**
+ * u16_strlen - count non-zero words
+ *
+ * This function matches wscnlen_s() if the -fshort-wchar compiler flag is set.
+ * In the EFI context we explicitly need a function handling u16 strings.
+ *
+ * @in:			null terminated u16 string
+ * @count:		maximum number of words to count
+ * ReturnValue:		number of non-zero words.
+ *			This is not the number of utf-16 letters!
+ */
+size_t u16_strnlen(const u16 *in, size_t count);
+
+/**
+ * u16_strcpy() - copy u16 string
+ *
+ * Copy u16 string pointed to by src, including terminating null word, to
+ * the buffer pointed to by dest.
+ *
+ * @dest:		destination buffer
+ * @src:		source buffer (null terminated)
+ * Return:		'dest' address
+ */
+u16 *u16_strcpy(u16 *dest, const u16 *src);
+
+/**
+ * u16_strdup() - duplicate u16 string
+ *
+ * Copy u16 string pointed to by src, including terminating null word, to a
+ * newly allocated buffer.
+ *
+ * @src:		source buffer (null terminated)
+ * Return:		allocated new buffer on success, NULL on failure
+ */
+u16 *u16_strdup(const void *src);
+
+/**
+ * utf16_to_utf8() - Convert an utf16 string to utf8
+ *
+ * Converts 'size' characters of the utf16 string 'src' to utf8
+ * written to the 'dest' buffer.
+ *
+ * NOTE that a single utf16 character can generate up to 3 utf8
+ * characters.  See MAX_UTF8_PER_UTF16.
+ *
+ * @dest   the destination buffer to write the utf8 characters
+ * @src    the source utf16 string
+ * @size   the number of utf16 characters to convert
+ * @return the pointer to the first unwritten byte in 'dest'
+ */
+uint8_t *utf16_to_utf8(uint8_t *dest, const uint16_t *src, size_t size);
+
+#endif /* __CHARSET_H_ */
diff --git a/include/circbuf.h b/include/circbuf.h
new file mode 100644
index 0000000..e8ec127
--- /dev/null
+++ b/include/circbuf.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ */
+
+#ifndef __CIRCBUF_H__
+#define __CIRCBUF_H__
+
+typedef struct circbuf {
+	unsigned int size;	/* current number of bytes held */
+	unsigned int totalsize; /* number of bytes allocated */
+
+	char *top;		/* pointer to current buffer start */
+	char *tail;		/* pointer to space for next element */
+
+	char *data;		/* all data */
+	char *end;		/* end of data buffer */
+} circbuf_t;
+
+int buf_init (circbuf_t * buf, unsigned int size);
+int buf_free (circbuf_t * buf);
+int buf_pop (circbuf_t * buf, char *dest, unsigned int len);
+int buf_push (circbuf_t * buf, const char *src, unsigned int len);
+
+#endif
diff --git a/include/cli.h b/include/cli.h
new file mode 100644
index 0000000..39b9137
--- /dev/null
+++ b/include/cli.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 Google, Inc
+ * Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __CLI_H
+#define __CLI_H
+
+/**
+ * Go into the command loop
+ *
+ * This will return if we get a timeout waiting for a command. See
+ * CONFIG_BOOT_RETRY_TIME.
+ */
+void cli_simple_loop(void);
+
+/**
+ * cli_simple_run_command() - Execute a command with the simple CLI
+ *
+ * @cmd:	String containing the command to execute
+ * @flag	Flag value - see CMD_FLAG_...
+ * @return 1  - command executed, repeatable
+ *	0  - command executed but not repeatable, interrupted commands are
+ *	     always considered not repeatable
+ *	-1 - not executed (unrecognized, bootd recursion or too many args)
+ *           (If cmd is NULL or "" or longer than CONFIG_SYS_CBSIZE-1 it is
+ *           considered unrecognized)
+ */
+int cli_simple_run_command(const char *cmd, int flag);
+
+/**
+ * cli_simple_process_macros() - Expand $() and ${} format env. variables
+ *
+ * @param input		Input string possible containing $() / ${} vars
+ * @param output	Output string with $() / ${} vars expanded
+ */
+void cli_simple_process_macros(const char *input, char *output);
+
+/**
+ * cli_simple_run_command_list() - Execute a list of command
+ *
+ * The commands should be separated by ; or \n and will be executed
+ * by the built-in parser.
+ *
+ * This function cannot take a const char * for the command, since if it
+ * finds newlines in the string, it replaces them with \0.
+ *
+ * @param cmd	String containing list of commands
+ * @param flag	Execution flags (CMD_FLAG_...)
+ * @return 0 on success, or != 0 on error.
+ */
+int cli_simple_run_command_list(char *cmd, int flag);
+
+/**
+ * cli_readline() - read a line into the console_buffer
+ *
+ * This is a convenience function which calls cli_readline_into_buffer().
+ *
+ * @prompt: Prompt to display
+ * @return command line length excluding terminator, or -ve on error
+ */
+int cli_readline(const char *const prompt);
+
+/**
+ * readline_into_buffer() - read a line into a buffer
+ *
+ * Display the prompt, then read a command line into @buffer. The
+ * maximum line length is CONFIG_SYS_CBSIZE including a \0 terminator, which
+ * will always be added.
+ *
+ * The command is echoed as it is typed. Command editing is supported if
+ * CONFIG_CMDLINE_EDITING is defined. Tab auto-complete is supported if
+ * CONFIG_AUTO_COMPLETE is defined. If CONFIG_BOOT_RETRY_TIME is defined,
+ * then a timeout will be applied.
+ *
+ * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0,
+ * time out when time goes past endtime (timebase time in ticks).
+ *
+ * @prompt:	Prompt to display
+ * @buffer:	Place to put the line that is entered
+ * @timeout:	Timeout in milliseconds, 0 if none
+ * @return command line length excluding terminator, or -ve on error: of the
+ * timeout is exceeded (either CONFIG_BOOT_RETRY_TIME or the timeout
+ * parameter), then -2 is returned. If a break is detected (Ctrl-C) then
+ * -1 is returned.
+ */
+int cli_readline_into_buffer(const char *const prompt, char *buffer,
+				int timeout);
+
+/**
+ * parse_line() - split a command line down into separate arguments
+ *
+ * The argv[] array is filled with pointers into @line, and each argument
+ * is terminated by \0 (i.e. @line is changed in the process unless there
+ * is only one argument).
+ *
+ * #argv is terminated by a NULL after the last argument pointer.
+ *
+ * At most CONFIG_SYS_MAXARGS arguments are permited - if there are more
+ * than that then an error is printed, and this function returns
+ * CONFIG_SYS_MAXARGS, with argv[] set up to that point.
+ *
+ * @line:	Command line to parse
+ * @args:	Array to hold arguments
+ * @return number of arguments
+ */
+int cli_simple_parse_line(char *line, char *argv[]);
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+/**
+ * cli_process_fdt() - process the boot command from the FDT
+ *
+ * If bootcmmd is defined in the /config node of the FDT, we use that
+ * as the boot command. Further, if bootsecure is set to 1 (in the same
+ * node) then we return true, indicating that the command should be executed
+ * as securely as possible, avoiding the CLI parser.
+ *
+ * @cmdp:	On entry, the command that will be executed if the FDT does
+ *		not have a command. Returns the command to execute after
+ *		checking the FDT.
+ * @return true to execute securely, else false
+ */
+bool cli_process_fdt(const char **cmdp);
+
+/** cli_secure_boot_cmd() - execute a command as securely as possible
+ *
+ * This avoids using the parser, thus executing the command with the
+ * smallest amount of code. Parameters are not supported.
+ */
+void cli_secure_boot_cmd(const char *cmd);
+#else
+static inline bool cli_process_fdt(const char **cmdp)
+{
+	return false;
+}
+
+static inline void cli_secure_boot_cmd(const char *cmd)
+{
+}
+#endif /* CONFIG_OF_CONTROL */
+
+/**
+ * Go into the command loop
+ *
+ * This will return if we get a timeout waiting for a command, but only for
+ * the simple parser (not hush). See CONFIG_BOOT_RETRY_TIME.
+ */
+void cli_loop(void);
+
+/** Set up the command line interpreter ready for action */
+void cli_init(void);
+
+#define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk())
+
+#endif
diff --git a/include/cli_hush.h b/include/cli_hush.h
new file mode 100644
index 0000000..2bd3567
--- /dev/null
+++ b/include/cli_hush.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef _CLI_HUSH_H_
+#define _CLI_HUSH_H_
+
+#define FLAG_EXIT_FROM_LOOP 1
+#define FLAG_PARSE_SEMICOLON (1 << 1)	  /* symbol ';' is special for parser */
+#define FLAG_REPARSING       (1 << 2)	  /* >=2nd pass */
+#define FLAG_CONT_ON_NEWLINE (1 << 3)	  /* continue when we see \n */
+
+extern int u_boot_hush_start(void);
+extern int parse_string_outer(const char *, int);
+extern int parse_file_outer(void);
+
+int set_local_var(const char *s, int flg_export);
+void unset_local_var(const char *name);
+char *get_local_var(const char *s);
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+extern int hush_init_var (void);
+#endif
+#endif
diff --git a/include/clk-uclass.h b/include/clk-uclass.h
new file mode 100644
index 0000000..e76d98e
--- /dev/null
+++ b/include/clk-uclass.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _CLK_UCLASS_H
+#define _CLK_UCLASS_H
+
+/* See clk.h for background documentation. */
+
+#include <clk.h>
+
+struct ofnode_phandle_args;
+
+/**
+ * struct clk_ops - The functions that a clock driver must implement.
+ */
+struct clk_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) clock specifier.
+	 *
+	 * The clock core calls this function as the first step in implementing
+	 * a client's clk_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the clock core will use a
+	 * default implementation, which assumes #clock-cells = <1>, and that
+	 * the DT cell contains a simple integer clock ID.
+	 *
+	 * At present, the clock API solely supports device-tree. If this
+	 * changes, other xxx_xlate() functions may be added to support those
+	 * other mechanisms.
+	 *
+	 * @clock:	The clock struct to hold the translation result.
+	 * @args:	The clock specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct clk *clock,
+			struct ofnode_phandle_args *args);
+	/**
+	 * request - Request a translated clock.
+	 *
+	 * The clock core calls this function as the second step in
+	 * implementing a client's clk_get_by_*() call, following a successful
+	 * xxx_xlate() call, or as the only step in implementing a client's
+	 * clk_request() call.
+	 *
+	 * @clock:	The clock struct to request; this has been fille in by
+	 *		a previoux xxx_xlate() function call, or by the caller
+	 *		of clk_request().
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct clk *clock);
+	/**
+	 * free - Free a previously requested clock.
+	 *
+	 * This is the implementation of the client clk_free() API.
+	 *
+	 * @clock:	The clock to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct clk *clock);
+	/**
+	 * get_rate() - Get current clock rate.
+	 *
+	 * @clk:	The clock to query.
+	 * @return clock rate in Hz, or -ve error code
+	 */
+	ulong (*get_rate)(struct clk *clk);
+	/**
+	 * set_rate() - Set current clock rate.
+	 *
+	 * @clk:	The clock to manipulate.
+	 * @rate:	New clock rate in Hz.
+	 * @return new rate, or -ve error code.
+	 */
+	ulong (*set_rate)(struct clk *clk, ulong rate);
+	/**
+	 * set_parent() - Set current clock parent
+	 *
+	 * @clk:        The clock to manipulate.
+	 * @parent:     New clock parent.
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*set_parent)(struct clk *clk, struct clk *parent);
+	/**
+	 * enable() - Enable a clock.
+	 *
+	 * @clk:	The clock to manipulate.
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*enable)(struct clk *clk);
+	/**
+	 * disable() - Disable a clock.
+	 *
+	 * @clk:	The clock to manipulate.
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*disable)(struct clk *clk);
+};
+
+#endif
diff --git a/include/clk.h b/include/clk.h
new file mode 100644
index 0000000..18b2e3c
--- /dev/null
+++ b/include/clk.h
@@ -0,0 +1,381 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _CLK_H_
+#define _CLK_H_
+
+#include <dm/ofnode.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+
+/**
+ * A clock is a hardware signal that oscillates autonomously at a specific
+ * frequency and duty cycle. Most hardware modules require one or more clock
+ * signal to drive their operation. Clock signals are typically generated
+ * externally to the HW module consuming them, by an entity this API calls a
+ * clock provider. This API provides a standard means for drivers to enable and
+ * disable clocks, and to set the rate at which they oscillate.
+ *
+ * A driver that implements UCLASS_CLK is a clock provider. A provider will
+ * often implement multiple separate clocks, since the hardware it manages
+ * often has this capability. clk-uclass.h describes the interface which
+ * clock providers must implement.
+ *
+ * Clock consumers/clients are the HW modules driven by the clock signals. This
+ * header file describes the API used by drivers for those HW modules.
+ */
+
+struct udevice;
+
+/**
+ * struct clk - A handle to (allowing control of) a single clock.
+ *
+ * Clients provide storage for clock handles. The content of the structure is
+ * managed solely by the clock API and clock drivers. A clock struct is
+ * initialized by "get"ing the clock struct. The clock struct is passed to all
+ * other clock APIs to identify which clock signal to operate upon.
+ *
+ * @dev: The device which implements the clock signal.
+ * @rate: The clock rate (in HZ).
+ * @flags: Flags used across common clock structure (e.g. CLK_)
+ *         Clock IP blocks specific flags (i.e. mux, div, gate, etc) are defined
+ *         in struct's for those devices (e.g. struct clk_mux).
+ * @id: The clock signal ID within the provider.
+ * @data: An optional data field for scenarios where a single integer ID is not
+ *	  sufficient. If used, it can be populated through an .of_xlate op and
+ *	  processed during the various clock ops.
+ *
+ * Should additional information to identify and configure any clock signal
+ * for any provider be required in the future, the struct could be expanded to
+ * either (a) add more fields to allow clock providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct clk {
+	struct udevice *dev;
+	long long rate;	/* in HZ */
+	u32 flags;
+	int enable_count;
+	/*
+	 * Written by of_xlate. In the future, we might add more fields here.
+	 */
+	unsigned long id;
+	unsigned long data;
+};
+
+/**
+ * struct clk_bulk - A handle to (allowing control of) a bulk of clocks.
+ *
+ * Clients provide storage for the clock bulk. The content of the structure is
+ * managed solely by the clock API. A clock bulk struct is
+ * initialized by "get"ing the clock bulk struct.
+ * The clock bulk struct is passed to all other bulk clock APIs to apply
+ * the API to all the clock in the bulk struct.
+ *
+ * @clks: An array of clock handles.
+ * @count: The number of clock handles in the clks array.
+ */
+struct clk_bulk {
+	struct clk *clks;
+	unsigned int count;
+};
+
+#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
+struct phandle_1_arg;
+int clk_get_by_index_platdata(struct udevice *dev, int index,
+			      struct phandle_1_arg *cells, struct clk *clk);
+
+/**
+ * clock_get_by_index - Get/request a clock by integer index.
+ *
+ * This looks up and requests a clock. The index is relative to the client
+ * device; each device is assumed to have n clocks associated with it somehow,
+ * and this function finds and requests one of them. The mapping of client
+ * device clock indices to provider clocks may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the clock to request, within the client's list of
+ *		clocks.
+ * @clock	A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
+
+/**
+ * clock_get_by_index_nodev - Get/request a clock by integer index
+ * without a device.
+ *
+ * This is a version of clk_get_by_index() that does not use a device.
+ *
+ * @node:	The client ofnode.
+ * @index:	The index of the clock to request, within the client's list of
+ *		clocks.
+ * @clock	A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk);
+
+/**
+ * clock_get_bulk - Get/request all clocks of a device.
+ *
+ * This looks up and requests all clocks of the client device; each device is
+ * assumed to have n clocks associated with it somehow, and this function finds
+ * and requests all of them in a separate structure. The mapping of client
+ * device clock indices to provider clocks may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @bulk	A pointer to a clock bulk struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk);
+
+/**
+ * clock_get_by_name - Get/request a clock by name.
+ *
+ * This looks up and requests a clock. The name is relative to the client
+ * device; each device is assumed to have n clocks associated with it somehow,
+ * and this function finds and requests one of them. The mapping of client
+ * device clock names to provider clocks may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the clock to request, within the client's list of
+ *		clocks.
+ * @clock:	A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk);
+
+/**
+ * clk_release_all() - Disable (turn off)/Free an array of previously
+ * requested clocks.
+ *
+ * For each clock contained in the clock array, this function will check if
+ * clock has been previously requested and then will disable and free it.
+ *
+ * @clk:	A clock struct array that was previously successfully
+ *		requested by clk_request/get_by_*().
+ * @count	Number of clock contained in the array
+ * @return zero on success, or -ve error code.
+ */
+int clk_release_all(struct clk *clk, int count);
+
+#else
+static inline int clk_get_by_index(struct udevice *dev, int index,
+				   struct clk *clk)
+{
+	return -ENOSYS;
+}
+
+static inline int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
+{
+	return -ENOSYS;
+}
+
+static inline int clk_get_by_name(struct udevice *dev, const char *name,
+			   struct clk *clk)
+{
+	return -ENOSYS;
+}
+
+static inline int clk_release_all(struct clk *clk, int count)
+{
+	return -ENOSYS;
+}
+#endif
+
+#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
+	CONFIG_IS_ENABLED(CLK)
+/**
+ * clk_set_defaults - Process 'assigned-{clocks/clock-parents/clock-rates}'
+ *                    properties to configure clocks
+ *
+ * @dev:        A device to process (the ofnode associated with this device
+ *              will be processed).
+ */
+int clk_set_defaults(struct udevice *dev);
+#else
+static inline int clk_set_defaults(struct udevice *dev)
+{
+	return 0;
+}
+#endif
+
+/**
+ * clk_release_bulk() - Disable (turn off)/Free an array of previously
+ * requested clocks in a clock bulk struct.
+ *
+ * For each clock contained in the clock bulk struct, this function will check
+ * if clock has been previously requested and then will disable and free it.
+ *
+ * @clk:	A clock bulk struct that was previously successfully
+ *		requested by clk_get_bulk().
+ * @return zero on success, or -ve error code.
+ */
+static inline int clk_release_bulk(struct clk_bulk *bulk)
+{
+	return clk_release_all(bulk->clks, bulk->count);
+}
+
+/**
+ * clk_request - Request a clock by provider-specific ID.
+ *
+ * This requests a clock using a provider-specific ID. Generally, this function
+ * should not be used, since clk_get_by_index/name() provide an interface that
+ * better separates clients from intimate knowledge of clock providers.
+ * However, this function may be useful in core SoC-specific code.
+ *
+ * @dev:	The clock provider device.
+ * @clock:	A pointer to a clock struct to initialize. The caller must
+ *		have already initialized any field in this struct which the
+ *		clock provider uses to identify the clock.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_request(struct udevice *dev, struct clk *clk);
+
+/**
+ * clock_free - Free a previously requested clock.
+ *
+ * @clock:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_free(struct clk *clk);
+
+/**
+ * clk_get_rate() - Get current clock rate.
+ *
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return clock rate in Hz, or -ve error code.
+ */
+ulong clk_get_rate(struct clk *clk);
+
+/**
+ * clk_get_parent() - Get current clock's parent.
+ *
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return pointer to parent's struct clk, or error code passed as pointer
+ */
+struct clk *clk_get_parent(struct clk *clk);
+
+/**
+ * clk_get_parent_rate() - Get parent of current clock rate.
+ *
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return clock rate in Hz, or -ve error code.
+ */
+long long clk_get_parent_rate(struct clk *clk);
+
+/**
+ * clk_set_rate() - Set current clock rate.
+ *
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @rate:	New clock rate in Hz.
+ * @return new rate, or -ve error code.
+ */
+ulong clk_set_rate(struct clk *clk, ulong rate);
+
+/**
+ * clk_set_parent() - Set current clock parent.
+ *
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @parent:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return new rate, or -ve error code.
+ */
+int clk_set_parent(struct clk *clk, struct clk *parent);
+
+/**
+ * clk_enable() - Enable (turn on) a clock.
+ *
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return zero on success, or -ve error code.
+ */
+int clk_enable(struct clk *clk);
+
+/**
+ * clk_enable_bulk() - Enable (turn on) all clocks in a clock bulk struct.
+ *
+ * @bulk:	A clock bulk struct that was previously successfully requested
+ *		by clk_get_bulk().
+ * @return zero on success, or -ve error code.
+ */
+int clk_enable_bulk(struct clk_bulk *bulk);
+
+/**
+ * clk_disable() - Disable (turn off) a clock.
+ *
+ * @clk:	A clock struct that was previously successfully requested by
+ *		clk_request/get_by_*().
+ * @return zero on success, or -ve error code.
+ */
+int clk_disable(struct clk *clk);
+
+/**
+ * clk_disable_bulk() - Disable (turn off) all clocks in a clock bulk struct.
+ *
+ * @bulk:	A clock bulk struct that was previously successfully requested
+ *		by clk_get_bulk().
+ * @return zero on success, or -ve error code.
+ */
+int clk_disable_bulk(struct clk_bulk *bulk);
+
+/**
+ * clk_is_match - check if two clk's point to the same hardware clock
+ * @p: clk compared against q
+ * @q: clk compared against p
+ *
+ * Returns true if the two struct clk pointers both point to the same hardware
+ * clock node.
+ *
+ * Returns false otherwise. Note that two NULL clks are treated as matching.
+ */
+bool clk_is_match(const struct clk *p, const struct clk *q);
+
+int soc_clk_dump(void);
+
+/**
+ * clk_valid() - check if clk is valid
+ *
+ * @clk:	the clock to check
+ * @return true if valid, or false
+ */
+static inline bool clk_valid(struct clk *clk)
+{
+	return !!clk->dev;
+}
+
+/**
+ * clk_get_by_id() - Get the clock by its ID
+ *
+ * @id:	The clock ID to search for
+ *
+ * @clkp:	A pointer to clock struct that has been found among added clocks
+ *              to UCLASS_CLK
+ * @return zero on success, or -ENOENT on error
+ */
+int clk_get_by_id(ulong id, struct clk **clkp);
+
+/**
+ * clk_dev_binded() - Check whether the clk has a device binded
+ *
+ * @clk		A pointer to the clk
+ *
+ * @return true on binded, or false on no
+ */
+bool clk_dev_binded(struct clk *clk);
+#endif
diff --git a/include/cmd_spl.h b/include/cmd_spl.h
new file mode 100644
index 0000000..51ec12e
--- /dev/null
+++ b/include/cmd_spl.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ */
+#ifndef _NAND_SPL_H_
+#define	_NAND_SPL_H_
+
+#define SPL_EXPORT	(0x00000001)
+
+#define SPL_EXPORT_FDT		(0x00000001)
+#define SPL_EXPORT_ATAGS	(0x00000002)
+#define SPL_EXPORT_LAST		SPL_EXPORT_ATAGS
+
+#endif /* _NAND_SPL_H_ */
diff --git a/include/command.h b/include/command.h
new file mode 100644
index 0000000..f6170e7
--- /dev/null
+++ b/include/command.h
@@ -0,0 +1,362 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ *  Definitions for Command Processor
+ */
+#ifndef __COMMAND_H
+#define __COMMAND_H
+
+#include <env.h>
+#include <linker_lists.h>
+
+#ifndef NULL
+#define NULL	0
+#endif
+
+/* Default to a width of 8 characters for help message command width */
+#ifndef CONFIG_SYS_HELP_CMD_WIDTH
+#define CONFIG_SYS_HELP_CMD_WIDTH	10
+#endif
+
+#ifndef	__ASSEMBLY__
+/*
+ * Monitor Command Table
+ */
+
+struct cmd_tbl_s {
+	char		*name;		/* Command Name			*/
+	int		maxargs;	/* maximum number of arguments	*/
+					/*
+					 * Same as ->cmd() except the command
+					 * tells us if it can be repeated.
+					 * Replaces the old ->repeatable field
+					 * which was not able to make
+					 * repeatable property different for
+					 * the main command and sub-commands.
+					 */
+	int		(*cmd_rep)(struct cmd_tbl_s *cmd, int flags, int argc,
+				   char * const argv[], int *repeatable);
+					/* Implementation function	*/
+	int		(*cmd)(struct cmd_tbl_s *, int, int, char * const []);
+	char		*usage;		/* Usage message	(short)	*/
+#ifdef	CONFIG_SYS_LONGHELP
+	char		*help;		/* Help  message	(long)	*/
+#endif
+#ifdef CONFIG_AUTO_COMPLETE
+	/* do auto completion on the arguments */
+	int		(*complete)(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]);
+#endif
+};
+
+typedef struct cmd_tbl_s	cmd_tbl_t;
+
+
+#if defined(CONFIG_CMD_RUN)
+extern int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif
+
+/* common/command.c */
+int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
+	      flag, int argc, char * const argv[]);
+cmd_tbl_t *find_cmd(const char *cmd);
+cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len);
+int complete_subcmdv(cmd_tbl_t *cmdtp, int count, int argc,
+		     char * const argv[], char last_char, int maxv,
+		     char *cmdv[]);
+
+extern int cmd_usage(const cmd_tbl_t *cmdtp);
+
+/* Dummy ->cmd and ->cmd_rep wrappers. */
+int cmd_always_repeatable(cmd_tbl_t *cmdtp, int flag, int argc,
+			  char * const argv[], int *repeatable);
+int cmd_never_repeatable(cmd_tbl_t *cmdtp, int flag, int argc,
+			 char * const argv[], int *repeatable);
+int cmd_discard_repeatable(cmd_tbl_t *cmdtp, int flag, int argc,
+			   char * const argv[]);
+
+static inline bool cmd_is_repeatable(cmd_tbl_t *cmdtp)
+{
+	return cmdtp->cmd_rep == cmd_always_repeatable;
+}
+
+#ifdef CONFIG_AUTO_COMPLETE
+extern int var_complete(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]);
+extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp);
+#endif
+
+/**
+ * cmd_process_error() - report and process a possible error
+ *
+ * @cmdtp: Command which caused the error
+ * @err: Error code (0 if none, -ve for error, like -EIO)
+ * @return 0 (CMD_RET_SUCCESS) if there is not error,
+ *	   1 (CMD_RET_FAILURE) if an error is found
+ *	   -1 (CMD_RET_USAGE) if 'usage' error is found
+ */
+int cmd_process_error(cmd_tbl_t *cmdtp, int err);
+
+/*
+ * Monitor Command
+ *
+ * All commands use a common argument format:
+ *
+ * void function (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+ */
+
+#if defined(CONFIG_CMD_MEMORY) || \
+	defined(CONFIG_CMD_I2C) || \
+	defined(CONFIG_CMD_ITEST) || \
+	defined(CONFIG_CMD_PCI) || \
+	defined(CONFIG_CMD_SETEXPR)
+#define CMD_DATA_SIZE
+extern int cmd_get_data_size(char* arg, int default_size);
+#endif
+
+#ifdef CONFIG_CMD_BOOTD
+extern int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif
+#ifdef CONFIG_CMD_BOOTM
+extern int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd);
+#else
+static inline int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd)
+{
+	return 0;
+}
+#endif
+
+extern int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+extern int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+extern int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
+			   char *const argv[]);
+
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+extern unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
+				char * const argv[]);
+
+#if defined(CONFIG_CMD_NVEDIT_EFI)
+extern int do_env_print_efi(cmd_tbl_t *cmdtp, int flag, int argc,
+			    char * const argv[]);
+extern int do_env_set_efi(cmd_tbl_t *cmdtp, int flag, int argc,
+			  char * const argv[]);
+#endif
+
+/*
+ * Error codes that commands return to cmd_process(). We use the standard 0
+ * and 1 for success and failure, but add one more case - failure with a
+ * request to call cmd_usage(). But the cmd_process() function handles
+ * CMD_RET_USAGE itself and after calling cmd_usage() it will return 1.
+ * This is just a convenience for commands to avoid them having to call
+ * cmd_usage() all over the place.
+ */
+enum command_ret_t {
+	CMD_RET_SUCCESS,	/* 0 = Success */
+	CMD_RET_FAILURE,	/* 1 = Failure */
+	CMD_RET_USAGE = -1,	/* Failure, please report 'usage' error */
+};
+
+/**
+ * Process a command with arguments. We look up the command and execute it
+ * if valid. Otherwise we print a usage message.
+ *
+ * @param flag		Some flags normally 0 (see CMD_FLAG_.. above)
+ * @param argc		Number of arguments (arg 0 must be the command text)
+ * @param argv		Arguments
+ * @param repeatable	This function sets this to 0 if the command is not
+ *			repeatable. If the command is repeatable, the value
+ *			is left unchanged.
+ * @param ticks		If ticks is not null, this function set it to the
+ *			number of ticks the command took to complete.
+ * @return 0 if the command succeeded, 1 if it failed
+ */
+int cmd_process(int flag, int argc, char * const argv[],
+			       int *repeatable, unsigned long *ticks);
+
+void fixup_cmdtable(cmd_tbl_t *cmdtp, int size);
+
+/**
+ * board_run_command() - Fallback function to execute a command
+ *
+ * When no command line features are enabled in U-Boot, this function is
+ * called to execute a command. Typically the function can look at the
+ * command and perform a few very specific tasks, such as booting the
+ * system in a particular way.
+ *
+ * This function is only used when CONFIG_CMDLINE is not enabled.
+ *
+ * In normal situations this function should not return, since U-Boot will
+ * simply hang.
+ *
+ * @cmdline:	Command line string to execute
+ * @return 0 if OK, 1 for error
+ */
+int board_run_command(const char *cmdline);
+#endif	/* __ASSEMBLY__ */
+
+/*
+ * Command Flags:
+ */
+#define CMD_FLAG_REPEAT		0x0001	/* repeat last command		*/
+#define CMD_FLAG_BOOTD		0x0002	/* command is from bootd	*/
+#define CMD_FLAG_ENV		0x0004	/* command is from the environment */
+
+#ifdef CONFIG_AUTO_COMPLETE
+# define _CMD_COMPLETE(x) x,
+#else
+# define _CMD_COMPLETE(x)
+#endif
+#ifdef CONFIG_SYS_LONGHELP
+# define _CMD_HELP(x) x,
+#else
+# define _CMD_HELP(x)
+#endif
+
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+#define U_BOOT_SUBCMDS_RELOC(_cmdname)					\
+	static void _cmdname##_subcmds_reloc(void)			\
+	{								\
+		static int relocated;					\
+									\
+		if (relocated)						\
+			return;						\
+									\
+		fixup_cmdtable(_cmdname##_subcmds,			\
+			       ARRAY_SIZE(_cmdname##_subcmds));		\
+		relocated = 1;						\
+	}
+#else
+#define U_BOOT_SUBCMDS_RELOC(_cmdname)					\
+	static void _cmdname##_subcmds_reloc(void) { }
+#endif
+
+#define U_BOOT_SUBCMDS_DO_CMD(_cmdname)					\
+	static int do_##_cmdname(cmd_tbl_t *cmdtp, int flag, int argc,	\
+				 char * const argv[], int *repeatable)	\
+	{								\
+		cmd_tbl_t *subcmd;					\
+									\
+		_cmdname##_subcmds_reloc();				\
+									\
+		/* We need at least the cmd and subcmd names. */	\
+		if (argc < 2 || argc > CONFIG_SYS_MAXARGS)		\
+			return CMD_RET_USAGE;				\
+									\
+		subcmd = find_cmd_tbl(argv[1], _cmdname##_subcmds,	\
+				      ARRAY_SIZE(_cmdname##_subcmds));	\
+		if (!subcmd || argc - 1 > subcmd->maxargs)		\
+			return CMD_RET_USAGE;				\
+									\
+		if (flag == CMD_FLAG_REPEAT &&				\
+		    !cmd_is_repeatable(subcmd))				\
+			return CMD_RET_SUCCESS;				\
+									\
+		return subcmd->cmd_rep(subcmd, flag, argc - 1,		\
+				       argv + 1, repeatable);		\
+	}
+
+#ifdef CONFIG_AUTO_COMPLETE
+#define U_BOOT_SUBCMDS_COMPLETE(_cmdname)				\
+	static int complete_##_cmdname(int argc, char * const argv[],	\
+				       char last_char, int maxv,	\
+				       char *cmdv[])			\
+	{								\
+		return complete_subcmdv(_cmdname##_subcmds,		\
+					ARRAY_SIZE(_cmdname##_subcmds),	\
+					argc - 1, argv + 1, last_char,	\
+					maxv, cmdv);			\
+	}
+#else
+#define U_BOOT_SUBCMDS_COMPLETE(_cmdname)
+#endif
+
+#define U_BOOT_SUBCMDS(_cmdname, ...)					\
+	static cmd_tbl_t _cmdname##_subcmds[] = { __VA_ARGS__ };	\
+	U_BOOT_SUBCMDS_RELOC(_cmdname)					\
+	U_BOOT_SUBCMDS_DO_CMD(_cmdname)					\
+	U_BOOT_SUBCMDS_COMPLETE(_cmdname)
+
+#ifdef CONFIG_CMDLINE
+#define U_BOOT_CMDREP_MKENT_COMPLETE(_name, _maxargs, _cmd_rep,		\
+				     _usage, _help, _comp)		\
+		{ #_name, _maxargs, _cmd_rep, cmd_discard_repeatable,	\
+		  _usage, _CMD_HELP(_help) _CMD_COMPLETE(_comp) }
+
+#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd,		\
+				_usage, _help, _comp)			\
+		{ #_name, _maxargs,					\
+		 _rep ? cmd_always_repeatable : cmd_never_repeatable,	\
+		 _cmd, _usage, _CMD_HELP(_help) _CMD_COMPLETE(_comp) }
+
+#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \
+	ll_entry_declare(cmd_tbl_t, _name, cmd) =			\
+		U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd,	\
+						_usage, _help, _comp);
+
+#define U_BOOT_CMDREP_COMPLETE(_name, _maxargs, _cmd_rep, _usage,	\
+			       _help, _comp)				\
+	ll_entry_declare(cmd_tbl_t, _name, cmd) =			\
+		U_BOOT_CMDREP_MKENT_COMPLETE(_name, _maxargs, _cmd_rep,	\
+					     _usage, _help, _comp)
+
+#else
+#define U_BOOT_SUBCMD_START(name)	static cmd_tbl_t name[] = {};
+#define U_BOOT_SUBCMD_END
+
+#define _CMD_REMOVE(_name, _cmd)					\
+	int __remove_ ## _name(void)					\
+	{								\
+		if (0)							\
+			_cmd(NULL, 0, 0, NULL);				\
+		return 0;						\
+	}
+
+#define U_BOOT_CMDREP_MKENT_COMPLETE(_name, _maxargs, _cmd_rep,		\
+				     _usage, _help, _comp)		\
+		{ #_name, _maxargs, 0 ? _cmd_rep : NULL, NULL, _usage,	\
+			_CMD_HELP(_help) _CMD_COMPLETE(_comp) }
+
+#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, _usage,	\
+				  _help, _comp)				\
+		{ #_name, _maxargs, NULL, 0 ? _cmd : NULL, _usage,	\
+			_CMD_HELP(_help) _CMD_COMPLETE(_comp) }
+
+#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help,	\
+			    _comp)				\
+	_CMD_REMOVE(sub_ ## _name, _cmd)
+
+#define U_BOOT_CMDREP_COMPLETE(_name, _maxargs, _cmd_rep, _usage,	\
+			       _help, _comp)				\
+	_CMD_REMOVE(sub_ ## _name, _cmd_rep)
+
+#endif /* CONFIG_CMDLINE */
+
+#define U_BOOT_CMD(_name, _maxargs, _rep, _cmd, _usage, _help)		\
+	U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, NULL)
+
+#define U_BOOT_CMD_MKENT(_name, _maxargs, _rep, _cmd, _usage, _help)	\
+	U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd,		\
+					_usage, _help, NULL)
+
+#define U_BOOT_SUBCMD_MKENT_COMPLETE(_name, _maxargs, _rep, _do_cmd,	\
+				     _comp)				\
+	U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _do_cmd,	\
+				  "", "", _comp)
+
+#define U_BOOT_SUBCMD_MKENT(_name, _maxargs, _rep, _do_cmd)		\
+	U_BOOT_SUBCMD_MKENT_COMPLETE(_name, _maxargs, _rep, _do_cmd,	\
+				     NULL)
+
+#define U_BOOT_CMD_WITH_SUBCMDS(_name, _usage, _help, ...)		\
+	U_BOOT_SUBCMDS(_name, __VA_ARGS__)				\
+	U_BOOT_CMDREP_COMPLETE(_name, CONFIG_SYS_MAXARGS, do_##_name,	\
+			       _usage, _help, complete_##_name)
+
+#endif	/* __COMMAND_H */
diff --git a/include/common.h b/include/common.h
new file mode 100644
index 0000000..8b5cb2e
--- /dev/null
+++ b/include/common.h
@@ -0,0 +1,408 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common header file for U-Boot
+ *
+ * This file still includes quite a bit of stuff that should be in separate
+ * headers like command.h, cpu.h and timer.h. Please think before adding more
+ * things. Patches to remove things are welcome.
+ *
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __COMMON_H_
+#define __COMMON_H_	1
+
+#ifndef __ASSEMBLY__		/* put C only stuff in this section */
+
+typedef unsigned char		uchar;
+typedef volatile unsigned long	vu_long;
+typedef volatile unsigned short vu_short;
+typedef volatile unsigned char	vu_char;
+
+#include <config.h>
+#include <errno.h>
+#include <time.h>
+//#include <asm-offsets.h>
+#include <linux/bitops.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <linux/printk.h>
+#include <linux/string.h>
+#include <linux/stringify.h>
+#include <asm/ptrace.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include <linux/kernel.h>
+
+#include <part.h>
+#include <flash.h>
+#include <image.h>
+
+#ifdef __LP64__
+#define CONFIG_SYS_SUPPORT_64BIT_DATA
+#endif
+
+#include <log.h>
+
+typedef void (interrupt_handler_t)(void *);
+
+#include <asm/u-boot.h> /* boot information for Linux kernel */
+//#include <asm/global_data.h>	/* global data used for startup functions */
+
+/* startup functions, used in:
+ * common/board_f.c
+ * common/init/board_init.c
+ * common/board_r.c
+ * common/board_info.c
+ */
+//#include <init.h>
+
+/*
+ * Function Prototypes
+ */
+void	hang		(void) __attribute__ ((noreturn));
+
+int	cpu_init(void);
+
+#include <display_options.h>
+
+/* common/main.c */
+void	main_loop	(void);
+int run_command(const char *cmd, int flag);
+int run_command_repeatable(const char *cmd, int flag);
+
+/**
+ * Run a list of commands separated by ; or even \0
+ *
+ * Note that if 'len' is not -1, then the command does not need to be nul
+ * terminated, Memory will be allocated for the command in that case.
+ *
+ * @param cmd	List of commands to run, each separated bu semicolon
+ * @param len	Length of commands excluding terminator if known (-1 if not)
+ * @param flag	Execution flags (CMD_FLAG_...)
+ * @return 0 on success, or != 0 on error.
+ */
+int run_command_list(const char *cmd, int len, int flag);
+
+int checkflash(void);
+int checkdram(void);
+extern u8 __dtb_dt_begin[];	/* embedded device tree blob */
+extern u8 __dtb_dt_spl_begin[];	/* embedded device tree blob for SPL/TPL */
+int mdm_init(void);
+
+/**
+ * Show the DRAM size in a board-specific way
+ *
+ * This is used by boards to display DRAM information in their own way.
+ *
+ * @param size	Size of DRAM (which should be displayed along with other info)
+ */
+void board_show_dram(phys_size_t size);
+
+/**
+ * Get the uppermost pointer that is valid to access
+ *
+ * Some systems may not map all of their address space. This function allows
+ * boards to indicate what their highest support pointer value is for DRAM
+ * access.
+ *
+ * @param total_size	Size of U-Boot (unused?)
+ */
+ulong board_get_usable_ram_top(ulong total_size);
+
+/**
+ * arch_fixup_fdt() - Write arch-specific information to fdt
+ *
+ * Defined in arch/$(ARCH)/lib/bootm-fdt.c
+ *
+ * @blob:	FDT blob to write to
+ * @return 0 if ok, or -ve FDT_ERR_... on failure
+ */
+int arch_fixup_fdt(void *blob);
+
+/* common/flash.c */
+void flash_perror (int);
+
+/* common/cmd_source.c */
+int	source (ulong addr, const char *fit_uname);
+
+extern ulong load_addr;		/* Default Load Address */
+extern ulong save_addr;		/* Default Save Address */
+extern ulong save_size;		/* Default Save Size */
+
+/* common/cmd_net.c */
+int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+/* common/cmd_fat.c */
+int do_fat_fsload(cmd_tbl_t *, int, int, char * const []);
+
+/* common/cmd_ext2.c */
+int do_ext2load(cmd_tbl_t *, int, int, char * const []);
+
+void	pci_init_board(void);
+
+/* common/exports.c */
+void	jumptable_init(void);
+
+/* common/kallsysm.c */
+const char *symbol_lookup(unsigned long addr, unsigned long *caddr);
+
+/* common/memsize.c */
+long	get_ram_size  (long *, long);
+phys_size_t get_effective_memsize(void);
+
+/* $(BOARD)/$(BOARD).c */
+void	reset_phy     (void);
+void	fdc_hw_init   (void);
+
+/* $(BOARD)/eeprom.c */
+#ifdef CONFIG_CMD_EEPROM
+void eeprom_init  (int bus);
+int  eeprom_read  (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+int  eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+#else
+/*
+ * Some EEPROM code is depecated because it used the legacy I2C interface. Add
+ * some macros here so we don't have to touch every one of those uses
+ */
+#define eeprom_init(bus)
+#define eeprom_read(dev_addr, offset, buffer, cnt) ((void)-ENOSYS)
+#define eeprom_write(dev_addr, offset, buffer, cnt) ((void)-ENOSYS)
+#endif
+
+#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
+#endif
+
+/* $(BOARD)/$(BOARD).c */
+int board_early_init_f (void);
+int board_fix_fdt (void *rw_fdt_blob); /* manipulate the U-Boot fdt before its relocation */
+int board_late_init (void);
+int board_postclk_init (void); /* after clocks/timebase, before env/serial */
+int board_early_init_r (void);
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram(void);
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+#if 0
+/* $(CPU)/start.S */
+int	icache_status (void);
+void	icache_enable (void);
+void	icache_disable(void);
+int	dcache_status (void);
+void	dcache_enable (void);
+void	dcache_disable(void);
+void	mmu_disable(void);
+#if defined(CONFIG_ARM)
+void	relocate_code(ulong);
+#else
+void	relocate_code(ulong, gd_t *, ulong) __attribute__ ((noreturn));
+#endif
+ulong	get_endaddr   (void);
+void	trap_init     (ulong);
+#endif
+
+/* $(CPU)/cpu.c */
+static inline int cpumask_next(int cpu, unsigned int mask)
+{
+	for (cpu++; !((1 << cpu) & mask); cpu++)
+		;
+
+	return cpu;
+}
+
+#define for_each_cpu(iter, cpu, num_cpus, mask) \
+	for (iter = 0, cpu = cpumask_next(-1, mask); \
+		iter < num_cpus; \
+		iter++, cpu = cpumask_next(cpu, mask)) \
+
+int	cpu_numcores  (void);
+int	cpu_num_dspcores(void);
+u32	cpu_mask      (void);
+u32	cpu_dsp_mask(void);
+int	is_core_valid (unsigned int);
+
+void s_init(void);
+
+int	checkcpu      (void);
+int	checkicache   (void);
+int	checkdcache   (void);
+void	upmconfig     (unsigned int, unsigned int *, unsigned int);
+ulong	get_tbclk     (void);
+void	reset_misc    (void);
+void	reset_cpu     (ulong addr);
+void ft_cpu_setup(void *blob, bd_t *bd);
+void ft_pci_setup(void *blob, bd_t *bd);
+
+void smp_set_core_boot_addr(unsigned long addr, int corenr);
+void smp_kick_all_cpus(void);
+
+/* $(CPU)/serial.c */
+int	serial_init   (void);
+void	serial_setbrg (void);
+void	serial_putc   (const char);
+void	serial_putc_raw(const char);
+void	serial_puts   (const char *);
+int	serial_getc   (void);
+int	serial_tstc   (void);
+
+/* $(CPU)/speed.c */
+int	get_clocks (void);
+ulong	get_bus_freq  (ulong);
+int get_serial_clock(void);
+
+/* $(CPU)/interrupts.c */
+int	interrupt_init	   (void);
+void	timer_interrupt	   (struct pt_regs *);
+void	external_interrupt (struct pt_regs *);
+void	irq_install_handler(int, interrupt_handler_t *, void *);
+void	irq_free_handler   (int);
+void	reset_timer	   (void);
+
+/* Return value of monotonic microsecond timer */
+unsigned long timer_get_us(void);
+
+void	enable_interrupts  (void);
+int	disable_interrupts (void);
+
+/* $(CPU)/.../commproc.c */
+void	bootcount_store (ulong);
+ulong	bootcount_load (void);
+
+/* $(CPU)/.../<eth> */
+void mii_init (void);
+
+/* arch/$(ARCH)/lib/cache.c */
+void	enable_caches(void);
+void	flush_cache   (unsigned long, unsigned long);
+void	flush_dcache_all(void);
+void	flush_dcache_range(unsigned long start, unsigned long stop);
+void	invalidate_dcache_range(unsigned long start, unsigned long stop);
+void	invalidate_dcache_all(void);
+void	invalidate_icache_all(void);
+
+enum {
+	/* Disable caches (else flush caches but leave them active) */
+	CBL_DISABLE_CACHES		= 1 << 0,
+	CBL_SHOW_BOOTSTAGE_REPORT	= 1 << 1,
+
+	CBL_ALL				= 3,
+};
+
+/**
+ * Clean up ready for linux
+ *
+ * @param flags		Flags to control what is done
+ */
+int cleanup_before_linux_select(int flags);
+
+/* arch/$(ARCH)/lib/ticks.S */
+uint64_t get_ticks(void);
+void	wait_ticks    (unsigned long);
+
+/* arch/$(ARCH)/lib/time.c */
+ulong	usec2ticks    (unsigned long usec);
+ulong	ticks2usec    (unsigned long ticks);
+
+/* lib/lz4_wrapper.c */
+int ulz4fn(const void *src, size_t srcn, void *dst, size_t *dstn);
+
+/* lib/qsort.c */
+void qsort(void *base, size_t nmemb, size_t size,
+	   int(*compar)(const void *, const void *));
+int strcmp_compar(const void *, const void *);
+
+/* lib/uuid.c */
+#include <uuid.h>
+
+/* lib/vsprintf.c */
+#include <vsprintf.h>
+
+/* lib/strmhz.c */
+char *	strmhz(char *buf, unsigned long hz);
+
+/* lib/crc32.c */
+#include <u-boot/crc.h>
+
+/* lib/rand.c */
+#define RAND_MAX -1U
+void srand(unsigned int seed);
+unsigned int rand(void);
+unsigned int rand_r(unsigned int *seedp);
+
+#if 0
+/*
+ * STDIO based functions (can always be used)
+ */
+/* serial stuff */
+int	serial_printf (const char *fmt, ...)
+		__attribute__ ((format (__printf__, 1, 2)));
+
+/* lib/net_utils.c */
+#include <net.h>
+static inline struct in_addr env_get_ip(char *var)
+{
+	return string_to_ip(env_get(var));
+}
+
+#ifdef CONFIG_LED_STATUS
+# include <status_led.h>
+#endif
+
+#include <bootstage.h>
+
+#ifdef CONFIG_SHOW_ACTIVITY
+void show_activity(int arg);
+#endif
+#endif
+
+/* Multicore arch functions */
+#ifdef CONFIG_MP
+int cpu_status(u32 nr);
+int cpu_reset(u32 nr);
+int cpu_disable(u32 nr);
+int cpu_release(u32 nr, int argc, char * const argv[]);
+#endif
+
+#else	/* __ASSEMBLY__ */
+
+#endif	/* __ASSEMBLY__ */
+
+/* Put only stuff here that the assembler can digest */
+
+#ifdef CONFIG_POST
+#define CONFIG_HAS_POST
+#ifndef CONFIG_POST_ALT_LIST
+#define CONFIG_POST_STD_LIST
+#endif
+#endif
+
+#define ROUND(a,b)		(((a) + (b) - 1) & ~((b) - 1))
+
+/*
+ * check_member() - Check the offset of a structure member
+ *
+ * @structure:	Name of structure (e.g. global_data)
+ * @member:	Name of member (e.g. baudrate)
+ * @offset:	Expected offset in bytes
+ */
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset)
+
+/* Avoid using CONFIG_EFI_STUB directly as we may boot from other loaders */
+#ifdef CONFIG_EFI_STUB
+#define ll_boot_init()	false
+#else
+#define ll_boot_init()	true
+#endif
+
+/* Pull in stuff for the build system */
+#ifdef DO_DEPS_ONLY
+# include <env_internal.h>
+#endif
+
+#endif	/* __COMMON_H_ */
diff --git a/include/common_timing_params.h b/include/common_timing_params.h
new file mode 100644
index 0000000..96704cd
--- /dev/null
+++ b/include/common_timing_params.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef COMMON_TIMING_PARAMS_H
+#define COMMON_TIMING_PARAMS_H
+
+typedef struct {
+	/* parameters to constrict */
+
+	unsigned int tckmin_x_ps;
+	unsigned int tckmax_ps;
+	unsigned int trcd_ps;
+	unsigned int trp_ps;
+	unsigned int tras_ps;
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+	unsigned int taamin_ps;
+#endif
+
+#ifdef CONFIG_SYS_FSL_DDR4
+	unsigned int trfc1_ps;
+	unsigned int trfc2_ps;
+	unsigned int trfc4_ps;
+	unsigned int trrds_ps;
+	unsigned int trrdl_ps;
+	unsigned int tccdl_ps;
+	unsigned int trfc_slr_ps;
+#else
+	unsigned int twtr_ps;	/* maximum = 63750 ps */
+	unsigned int trfc_ps;	/* maximum = 255 ns + 256 ns + .75 ns
+					   = 511750 ps */
+
+	unsigned int trrd_ps;	/* maximum = 63750 ps */
+	unsigned int trtp_ps;	/* byte 38, spd->trtp */
+#endif
+	unsigned int twr_ps;	/* maximum = 63750 ps */
+	unsigned int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+
+	unsigned int refresh_rate_ps;
+	unsigned int extended_op_srt;
+
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
+	unsigned int tis_ps;	/* byte 32, spd->ca_setup */
+	unsigned int tih_ps;	/* byte 33, spd->ca_hold */
+	unsigned int tds_ps;	/* byte 34, spd->data_setup */
+	unsigned int tdh_ps;	/* byte 35, spd->data_hold */
+	unsigned int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
+	unsigned int tqhs_ps;	/* byte 45, spd->tqhs */
+#endif
+
+	unsigned int ndimms_present;
+	unsigned int lowest_common_spd_caslat;
+	unsigned int highest_common_derated_caslat;
+	unsigned int additive_latency;
+	unsigned int all_dimms_burst_lengths_bitmask;
+	unsigned int all_dimms_registered;
+	unsigned int all_dimms_unbuffered;
+	unsigned int all_dimms_ecc_capable;
+
+	unsigned long long total_mem;
+	unsigned long long base_address;
+
+	/* DDR3 RDIMM */
+	unsigned char rcw[16];	/* Register Control Word 0-15 */
+} common_timing_params_t;
+
+#endif
diff --git a/include/compiler.h b/include/compiler.h
new file mode 100644
index 0000000..29507f9
--- /dev/null
+++ b/include/compiler.h
@@ -0,0 +1,147 @@
+/*
+ * Keep all the ugly #ifdef for system stuff here
+ */
+
+#ifndef __COMPILER_H__
+#define __COMPILER_H__
+
+#include <stddef.h>
+
+#ifdef USE_HOSTCC
+
+#if defined(__BEOS__)	 || \
+    defined(__NetBSD__)  || \
+    defined(__FreeBSD__) || \
+    defined(__sun__)	 || \
+    defined(__APPLE__)
+# include <inttypes.h>
+#elif defined(__linux__) || defined(__WIN32__) || defined(__MINGW32__) || defined(__OpenBSD__)
+# include <stdint.h>
+#endif
+
+#include <errno.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#if !defined(__WIN32__) && !defined(__MINGW32__)
+# include <sys/mman.h>
+#endif
+
+/* Not all systems (like Windows) has this define, and yes
+ * we do replace/emulate mmap() on those systems ...
+ */
+#ifndef MAP_FAILED
+# define MAP_FAILED ((void *)-1)
+#endif
+
+#include <fcntl.h>
+#ifndef O_BINARY		/* should be define'd on __WIN32__ */
+#define O_BINARY	0
+#endif
+
+#ifdef __linux__
+# include <endian.h>
+# include <byteswap.h>
+#elif defined(__MACH__) || defined(__FreeBSD__)
+# include <machine/endian.h>
+typedef unsigned long ulong;
+#endif
+#ifdef __FreeBSD__
+# include <sys/endian.h> /* htole32 and friends */
+# define __BYTE_ORDER BYTE_ORDER
+# define __LITTLE_ENDIAN LITTLE_ENDIAN
+# define __BIG_ENDIAN BIG_ENDIAN
+#elif defined(__OpenBSD__)
+# include <endian.h>
+# define __BYTE_ORDER BYTE_ORDER
+# define __LITTLE_ENDIAN LITTLE_ENDIAN
+# define __BIG_ENDIAN BIG_ENDIAN
+#endif
+
+#include <time.h>
+
+typedef uint8_t __u8;
+typedef uint16_t __u16;
+typedef uint32_t __u32;
+typedef unsigned int uint;
+
+#define uswap_16(x) \
+	((((x) & 0xff00) >> 8) | \
+	 (((x) & 0x00ff) << 8))
+#define uswap_32(x) \
+	((((x) & 0xff000000) >> 24) | \
+	 (((x) & 0x00ff0000) >>  8) | \
+	 (((x) & 0x0000ff00) <<  8) | \
+	 (((x) & 0x000000ff) << 24))
+#define _uswap_64(x, sfx) \
+	((((x) & 0xff00000000000000##sfx) >> 56) | \
+	 (((x) & 0x00ff000000000000##sfx) >> 40) | \
+	 (((x) & 0x0000ff0000000000##sfx) >> 24) | \
+	 (((x) & 0x000000ff00000000##sfx) >>  8) | \
+	 (((x) & 0x00000000ff000000##sfx) <<  8) | \
+	 (((x) & 0x0000000000ff0000##sfx) << 24) | \
+	 (((x) & 0x000000000000ff00##sfx) << 40) | \
+	 (((x) & 0x00000000000000ff##sfx) << 56))
+#if defined(__GNUC__)
+# define uswap_64(x) _uswap_64(x, ull)
+#else
+# define uswap_64(x) _uswap_64(x, )
+#endif
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+# define cpu_to_le16(x)		(x)
+# define cpu_to_le32(x)		(x)
+# define cpu_to_le64(x)		(x)
+# define le16_to_cpu(x)		(x)
+# define le32_to_cpu(x)		(x)
+# define le64_to_cpu(x)		(x)
+# define cpu_to_be16(x)		uswap_16(x)
+# define cpu_to_be32(x)		uswap_32(x)
+# define cpu_to_be64(x)		uswap_64(x)
+# define be16_to_cpu(x)		uswap_16(x)
+# define be32_to_cpu(x)		uswap_32(x)
+# define be64_to_cpu(x)		uswap_64(x)
+#else
+# define cpu_to_le16(x)		uswap_16(x)
+# define cpu_to_le32(x)		uswap_32(x)
+# define cpu_to_le64(x)		uswap_64(x)
+# define le16_to_cpu(x)		uswap_16(x)
+# define le32_to_cpu(x)		uswap_32(x)
+# define le64_to_cpu(x)		uswap_64(x)
+# define cpu_to_be16(x)		(x)
+# define cpu_to_be32(x)		(x)
+# define cpu_to_be64(x)		(x)
+# define be16_to_cpu(x)		(x)
+# define be32_to_cpu(x)		(x)
+# define be64_to_cpu(x)		(x)
+#endif
+
+#else /* !USE_HOSTCC */
+
+/* Type for `void *' pointers. */
+typedef unsigned long int uintptr_t;
+
+#include <linux/string.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+#if __SIZEOF_LONG__ == 8
+# define __WORDSIZE	64
+#elif __SIZEOF_LONG__ == 4
+# define __WORDSIZE	32
+#else
+/*
+ * Assume 32-bit for now - only newer toolchains support this feature and
+ * this is only required for sandbox support at present.
+ */
+#define __WORDSIZE	32
+#endif
+
+#endif /* USE_HOSTCC */
+
+#define likely(x)	__builtin_expect(!!(x), 1)
+#define unlikely(x)	__builtin_expect(!!(x), 0)
+
+#endif
diff --git a/include/config_defaults.h b/include/config_defaults.h
new file mode 100644
index 0000000..d211a41
--- /dev/null
+++ b/include/config_defaults.h
@@ -0,0 +1,12 @@
+/*
+ * config_defaults.h - sane defaults for everyone
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _CONFIG_DEFAULTS_H_
+#define _CONFIG_DEFAULTS_H_
+
+#endif
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
new file mode 100644
index 0000000..3570a32
--- /dev/null
+++ b/include/config_distro_bootcmd.h
@@ -0,0 +1,491 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * Copyright 2014 Red Hat, Inc.
+ */
+
+#ifndef _CONFIG_CMD_DISTRO_BOOTCMD_H
+#define _CONFIG_CMD_DISTRO_BOOTCMD_H
+
+/*
+ * A note on error handling: It is possible for BOOT_TARGET_DEVICES to
+ * reference a device that is not enabled in the U-Boot configuration, e.g.
+ * it may include MMC in the list without CONFIG_CMD_MMC being enabled. Given
+ * that BOOT_TARGET_DEVICES is a macro that's expanded by the C pre-processor
+ * at compile time, it's not  possible to detect and report such problems via
+ * a simple #ifdef/#error combination. Still, the code needs to report errors.
+ * The best way I've found to do this is to make BOOT_TARGET_DEVICES expand to
+ * reference a non-existent symbol, and have the name of that symbol encode
+ * the error message. Consequently, this file contains references to e.g.
+ * BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC. Given the
+ * prevalence of capitals here, this looks like a pre-processor macro and
+ * hence seems like it should be all capitals, but it's really an error
+ * message that includes some other pre-processor symbols in the text.
+ */
+
+#define BOOTENV_SHARED_BLKDEV_BODY(devtypel) \
+		"if " #devtypel " dev ${devnum}; then " \
+			"devtype=" #devtypel "; " \
+			"run scan_dev_for_boot_part; " \
+		"fi\0"
+
+#define BOOTENV_SHARED_BLKDEV(devtypel) \
+	#devtypel "_boot=" \
+	BOOTENV_SHARED_BLKDEV_BODY(devtypel)
+
+#define BOOTENV_DEV_BLKDEV(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+		"devnum=" #instance "; " \
+		"run " #devtypel "_boot\0"
+
+#define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#ifdef CONFIG_SANDBOX
+#define BOOTENV_SHARED_HOST	BOOTENV_SHARED_BLKDEV(host)
+#define BOOTENV_DEV_HOST	BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_HOST	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_SHARED_HOST
+#define BOOTENV_DEV_HOST \
+	BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX
+#define BOOTENV_DEV_NAME_HOST \
+	BOOT_TARGET_DEVICES_references_HOST_without_CONFIG_SANDBOX
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOTENV_SHARED_MMC	BOOTENV_SHARED_BLKDEV(mmc)
+#define BOOTENV_DEV_MMC		BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_MMC	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_SHARED_MMC
+#define BOOTENV_DEV_MMC \
+	BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC
+#define BOOTENV_DEV_NAME_MMC \
+	BOOT_TARGET_DEVICES_references_MMC_without_CONFIG_CMD_MMC
+#endif
+
+#ifdef CONFIG_CMD_UBIFS
+#define BOOTENV_SHARED_UBIFS \
+	"ubifs_boot=" \
+		"env exists bootubipart || " \
+			"env set bootubipart UBI; " \
+		"env exists bootubivol || " \
+			"env set bootubivol boot; " \
+		"if ubi part ${bootubipart} && " \
+			"ubifsmount ubi${devnum}:${bootubivol}; " \
+		"then " \
+			"devtype=ubi; " \
+			"run scan_dev_for_boot; " \
+		"fi\0"
+#define BOOTENV_DEV_UBIFS	BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_UBIFS	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_SHARED_UBIFS
+#define BOOTENV_DEV_UBIFS \
+	BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS
+#define BOOTENV_DEV_NAME_UBIFS \
+	BOOT_TARGET_DEVICES_references_UBIFS_without_CONFIG_CMD_UBIFS
+#endif
+
+#ifdef CONFIG_EFI_LOADER
+#if defined(CONFIG_ARM64)
+#define BOOTEFI_NAME "bootaa64.efi"
+#elif defined(CONFIG_ARM)
+#define BOOTEFI_NAME "bootarm.efi"
+#elif defined(CONFIG_X86_RUN_32BIT)
+#define BOOTEFI_NAME "bootia32.efi"
+#elif defined(CONFIG_X86_RUN_64BIT)
+#define BOOTEFI_NAME "bootx64.efi"
+#elif defined(CONFIG_ARCH_RV32I)
+#define BOOTEFI_NAME "bootriscv32.efi"
+#elif defined(CONFIG_ARCH_RV64I)
+#define BOOTEFI_NAME "bootriscv64.efi"
+#endif
+#endif
+
+#ifdef BOOTEFI_NAME
+#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
+/*
+ * On 32bit ARM systems there is a reasonable number of systems that follow
+ * the $soc-$board$boardver.dtb name scheme for their device trees. Use that
+ * scheme if we don't have an explicit fdtfile variable.
+ */
+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK                                  \
+	"if test -z \"${fdtfile}\" -a -n \"${soc}\"; then "               \
+	  "setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; "           \
+	"fi; "
+#else
+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK
+#endif
+
+
+#define BOOTENV_SHARED_EFI                                                \
+	"boot_efi_binary="                                                \
+		"if fdt addr ${fdt_addr_r}; then "                        \
+			"bootefi bootmgr ${fdt_addr_r};"                  \
+		"else "                                                   \
+			"bootefi bootmgr ${fdtcontroladdr};"              \
+		"fi;"                                                     \
+		"load ${devtype} ${devnum}:${distro_bootpart} "           \
+			"${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; "      \
+		"if fdt addr ${fdt_addr_r}; then "                        \
+			"bootefi ${kernel_addr_r} ${fdt_addr_r};"         \
+		"else "                                                   \
+			"bootefi ${kernel_addr_r} ${fdtcontroladdr};"     \
+		"fi\0"                                                    \
+	\
+	"load_efi_dtb="                                                   \
+		"load ${devtype} ${devnum}:${distro_bootpart} "           \
+			"${fdt_addr_r} ${prefix}${efi_fdtfile}\0"         \
+	\
+	"efi_dtb_prefixes=/ /dtb/ /dtb/current/\0"                        \
+	"scan_dev_for_efi="                                               \
+		"setenv efi_fdtfile ${fdtfile}; "                         \
+		BOOTENV_EFI_SET_FDTFILE_FALLBACK                          \
+		"for prefix in ${efi_dtb_prefixes}; do "                  \
+			"if test -e ${devtype} "                          \
+					"${devnum}:${distro_bootpart} "   \
+					"${prefix}${efi_fdtfile}; then "  \
+				"run load_efi_dtb; "                      \
+			"fi;"                                             \
+		"done;"                                                   \
+		"if test -e ${devtype} ${devnum}:${distro_bootpart} "     \
+					"efi/boot/"BOOTEFI_NAME"; then "  \
+				"echo Found EFI removable media binary "  \
+					"efi/boot/"BOOTEFI_NAME"; "       \
+				"run boot_efi_binary; "                   \
+				"echo EFI LOAD FAILED: continuing...; "   \
+		"fi; "                                                    \
+		"setenv efi_fdtfile\0"
+#define SCAN_DEV_FOR_EFI "run scan_dev_for_efi;"
+#else
+#define BOOTENV_SHARED_EFI
+#define SCAN_DEV_FOR_EFI
+#endif
+
+#ifdef CONFIG_SATA
+#define BOOTENV_SHARED_SATA	BOOTENV_SHARED_BLKDEV(sata)
+#define BOOTENV_DEV_SATA	BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_SATA	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_SHARED_SATA
+#define BOOTENV_DEV_SATA \
+	BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_SATA
+#define BOOTENV_DEV_NAME_SATA \
+	BOOT_TARGET_DEVICES_references_SATA_without_CONFIG_SATA
+#endif
+
+#ifdef CONFIG_NVME
+#define BOOTENV_RUN_NVME_INIT "run nvme_init; "
+#define BOOTENV_SET_NVME_NEED_INIT "setenv nvme_need_init; "
+#define BOOTENV_SHARED_NVME \
+	"nvme_init=" \
+		"if ${nvme_need_init}; then " \
+			"setenv nvme_need_init false; " \
+			"nvme scan; " \
+		"fi\0" \
+	\
+	"nvme_boot=" \
+		BOOTENV_RUN_NVME_INIT \
+		BOOTENV_SHARED_BLKDEV_BODY(nvme)
+#define BOOTENV_DEV_NVME	BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_NVME	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_RUN_NVME_INIT
+#define BOOTENV_SET_NVME_NEED_INIT
+#define BOOTENV_SHARED_NVME
+#define BOOTENV_DEV_NVME \
+	BOOT_TARGET_DEVICES_references_NVME_without_CONFIG_NVME
+#define BOOTENV_DEV_NAME_NVME \
+	BOOT_TARGET_DEVICES_references_NVME_without_CONFIG_NVME
+#endif
+
+#ifdef CONFIG_SCSI
+#define BOOTENV_RUN_SCSI_INIT "run scsi_init; "
+#define BOOTENV_SET_SCSI_NEED_INIT "scsi_need_init=; "
+#define BOOTENV_SHARED_SCSI \
+	"scsi_init=" \
+		"if ${scsi_need_init}; then " \
+			"scsi_need_init=false; " \
+			"scsi scan; " \
+		"fi\0" \
+	\
+	"scsi_boot=" \
+		BOOTENV_RUN_SCSI_INIT \
+		BOOTENV_SHARED_BLKDEV_BODY(scsi)
+#define BOOTENV_DEV_SCSI	BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_SCSI	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_RUN_SCSI_INIT
+#define BOOTENV_SET_SCSI_NEED_INIT
+#define BOOTENV_SHARED_SCSI
+#define BOOTENV_DEV_SCSI \
+	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
+#define BOOTENV_DEV_NAME_SCSI \
+	BOOT_TARGET_DEVICES_references_SCSI_without_CONFIG_SCSI
+#endif
+
+#ifdef CONFIG_IDE
+#define BOOTENV_RUN_IDE_INIT "run ide_init; "
+#define BOOTENV_SET_IDE_NEED_INIT "setenv ide_need_init; "
+#define BOOTENV_SHARED_IDE \
+	"ide_init=" \
+		"if ${ide_need_init}; then " \
+			"setenv ide_need_init false; " \
+			"ide reset; " \
+		"fi\0" \
+	\
+	"ide_boot=" \
+		BOOTENV_RUN_IDE_INIT \
+		BOOTENV_SHARED_BLKDEV_BODY(ide)
+#define BOOTENV_DEV_IDE		BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_IDE	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_RUN_IDE_INIT
+#define BOOTENV_SET_IDE_NEED_INIT
+#define BOOTENV_SHARED_IDE
+#define BOOTENV_DEV_IDE \
+	BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE
+#define BOOTENV_DEV_NAME_IDE \
+	BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE
+#endif
+
+#if defined(CONFIG_DM_PCI)
+#define BOOTENV_RUN_PCI_ENUM "run boot_pci_enum; "
+#define BOOTENV_SHARED_PCI \
+	"boot_pci_enum=pci enum\0"
+#else
+#define BOOTENV_RUN_PCI_ENUM
+#define BOOTENV_SHARED_PCI
+#endif
+
+#ifdef CONFIG_CMD_USB
+#define BOOTENV_RUN_NET_USB_START "run boot_net_usb_start; "
+#define BOOTENV_SHARED_USB \
+	"boot_net_usb_start=usb start\0" \
+	"usb_boot=" \
+		"usb start; " \
+		BOOTENV_SHARED_BLKDEV_BODY(usb)
+#define BOOTENV_DEV_USB		BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_USB	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_RUN_NET_USB_START
+#define BOOTENV_SHARED_USB
+#define BOOTENV_DEV_USB \
+	BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
+#define BOOTENV_DEV_NAME_USB \
+	BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
+#endif
+
+#ifdef CONFIG_CMD_VIRTIO
+#define BOOTENV_RUN_VIRTIO_INIT "run virtio_init; "
+#define BOOTENV_SET_VIRTIO_NEED_INIT "virtio_need_init=; "
+#define BOOTENV_SHARED_VIRTIO \
+	"virtio_init=" \
+		"if ${virtio_need_init}; then " \
+			"virtio_need_init=false; " \
+			"virtio scan; " \
+		"fi\0" \
+	\
+	"virtio_boot=" \
+		BOOTENV_RUN_PCI_ENUM \
+		BOOTENV_RUN_VIRTIO_INIT \
+		BOOTENV_SHARED_BLKDEV_BODY(virtio)
+#define BOOTENV_DEV_VIRTIO	BOOTENV_DEV_BLKDEV
+#define BOOTENV_DEV_NAME_VIRTIO	BOOTENV_DEV_NAME_BLKDEV
+#else
+#define BOOTENV_RUN_VIRTIO_INIT
+#define BOOTENV_SET_VIRTIO_NEED_INIT
+#define BOOTENV_SHARED_VIRTIO
+#define BOOTENV_DEV_VIRTIO \
+	BOOT_TARGET_DEVICES_references_VIRTIO_without_CONFIG_CMD_VIRTIO
+#define BOOTENV_DEV_NAME_VIRTIO \
+	BOOT_TARGET_DEVICES_references_VIRTIO_without_CONFIG_CMD_VIRTIO
+#endif
+
+#if defined(CONFIG_CMD_DHCP)
+#if defined(CONFIG_EFI_LOADER)
+/* http://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml */
+#if defined(CONFIG_ARM64) || defined(__aarch64__)
+#define BOOTENV_EFI_PXE_ARCH "0xb"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000"
+#elif defined(CONFIG_ARM) || defined(__arm__)
+#define BOOTENV_EFI_PXE_ARCH "0xa"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00010:UNDI:003000"
+#elif defined(CONFIG_X86) || defined(__x86_64__)
+#define BOOTENV_EFI_PXE_ARCH "0x7"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000"
+#elif defined(__i386__)
+#define BOOTENV_EFI_PXE_ARCH "0x6"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00006:UNDI:003000"
+#elif defined(CONFIG_ARCH_RV32I) || ((defined(__riscv) && __riscv_xlen == 32))
+#define BOOTENV_EFI_PXE_ARCH "0x19"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00025:UNDI:003000"
+#elif defined(CONFIG_ARCH_RV64I) || ((defined(__riscv) && __riscv_xlen == 64))
+#define BOOTENV_EFI_PXE_ARCH "0x1b"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00027:UNDI:003000"
+#elif defined(CONFIG_SANDBOX)
+# error "sandbox EFI support is only supported on ARM and x86"
+#else
+#error Please specify an EFI client identifier
+#endif
+
+/*
+ * Ask the dhcp server for an EFI binary. If we get one, check for a
+ * device tree in the same folder. Then boot everything. If the file was
+ * not an EFI binary, we just return from the bootefi command and continue.
+ */
+#define BOOTENV_EFI_RUN_DHCP \
+	"setenv efi_fdtfile ${fdtfile}; "                                 \
+	BOOTENV_EFI_SET_FDTFILE_FALLBACK                                  \
+	"setenv efi_old_vci ${bootp_vci};"                                \
+	"setenv efi_old_arch ${bootp_arch};"                              \
+	"setenv bootp_vci " BOOTENV_EFI_PXE_VCI ";"                       \
+	"setenv bootp_arch " BOOTENV_EFI_PXE_ARCH ";"                     \
+	"if dhcp ${kernel_addr_r}; then "                                 \
+		"tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};"              \
+		"if fdt addr ${fdt_addr_r}; then "                        \
+			"bootefi ${kernel_addr_r} ${fdt_addr_r}; "        \
+		"else "                                                   \
+			"bootefi ${kernel_addr_r} ${fdtcontroladdr};"     \
+		"fi;"                                                     \
+	"fi;"                                                             \
+	"setenv bootp_vci ${efi_old_vci};"                                \
+	"setenv bootp_arch ${efi_old_arch};"                              \
+	"setenv efi_fdtfile;"                                             \
+	"setenv efi_old_arch;"                                            \
+	"setenv efi_old_vci;"
+#else
+#define BOOTENV_EFI_RUN_DHCP
+#endif
+#define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \
+	"bootcmd_dhcp=" \
+		BOOTENV_RUN_NET_USB_START \
+		BOOTENV_RUN_PCI_ENUM \
+		"if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \
+			"source ${scriptaddr}; " \
+		"fi;" \
+		BOOTENV_EFI_RUN_DHCP \
+		"\0"
+#define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \
+	"dhcp "
+#else
+#define BOOTENV_DEV_DHCP \
+	BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP
+#define BOOTENV_DEV_NAME_DHCP \
+	BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP
+#endif
+
+#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE)
+#define BOOTENV_DEV_PXE(devtypeu, devtypel, instance) \
+	"bootcmd_pxe=" \
+		BOOTENV_RUN_NET_USB_START \
+		BOOTENV_RUN_PCI_ENUM \
+		"dhcp; " \
+		"if pxe get; then " \
+			"pxe boot; " \
+		"fi\0"
+#define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \
+	"pxe "
+#else
+#define BOOTENV_DEV_PXE \
+	BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE
+#define BOOTENV_DEV_NAME_PXE \
+	BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE
+#endif
+
+#define BOOTENV_DEV_NAME(devtypeu, devtypel, instance) \
+	BOOTENV_DEV_NAME_##devtypeu(devtypeu, devtypel, instance)
+#define BOOTENV_BOOT_TARGETS \
+	"boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0"
+
+#define BOOTENV_DEV(devtypeu, devtypel, instance) \
+	BOOTENV_DEV_##devtypeu(devtypeu, devtypel, instance)
+#define BOOTENV \
+	BOOTENV_SHARED_HOST \
+	BOOTENV_SHARED_MMC \
+	BOOTENV_SHARED_PCI \
+	BOOTENV_SHARED_USB \
+	BOOTENV_SHARED_SATA \
+	BOOTENV_SHARED_SCSI \
+	BOOTENV_SHARED_NVME \
+	BOOTENV_SHARED_IDE \
+	BOOTENV_SHARED_UBIFS \
+	BOOTENV_SHARED_EFI \
+	BOOTENV_SHARED_VIRTIO \
+	"boot_prefixes=/ /boot/\0" \
+	"boot_scripts=boot.scr.uimg boot.scr\0" \
+	"boot_script_dhcp=boot.scr.uimg\0" \
+	BOOTENV_BOOT_TARGETS \
+	\
+	"boot_syslinux_conf=extlinux/extlinux.conf\0" \
+	"boot_extlinux="                                                  \
+		"sysboot ${devtype} ${devnum}:${distro_bootpart} any "    \
+			"${scriptaddr} ${prefix}${boot_syslinux_conf}\0"  \
+	\
+	"scan_dev_for_extlinux="                                          \
+		"if test -e ${devtype} "                                  \
+				"${devnum}:${distro_bootpart} "           \
+				"${prefix}${boot_syslinux_conf}; then "   \
+			"echo Found ${prefix}${boot_syslinux_conf}; "     \
+			"run boot_extlinux; "                             \
+			"echo SCRIPT FAILED: continuing...; "             \
+		"fi\0"                                                    \
+	\
+	"boot_a_script="                                                  \
+		"load ${devtype} ${devnum}:${distro_bootpart} "           \
+			"${scriptaddr} ${prefix}${script}; "              \
+		"source ${scriptaddr}\0"                                  \
+	\
+	"scan_dev_for_scripts="                                           \
+		"for script in ${boot_scripts}; do "                      \
+			"if test -e ${devtype} "                          \
+					"${devnum}:${distro_bootpart} "   \
+					"${prefix}${script}; then "       \
+				"echo Found U-Boot script "               \
+					"${prefix}${script}; "            \
+				"run boot_a_script; "                     \
+				"echo SCRIPT FAILED: continuing...; "     \
+			"fi; "                                            \
+		"done\0"                                                  \
+	\
+	"scan_dev_for_boot="                                              \
+		"echo Scanning ${devtype} "                               \
+				"${devnum}:${distro_bootpart}...; "       \
+		"for prefix in ${boot_prefixes}; do "                     \
+			"run scan_dev_for_extlinux; "                     \
+			"run scan_dev_for_scripts; "                      \
+		"done;"                                                   \
+		SCAN_DEV_FOR_EFI                                          \
+		"\0"                                                      \
+	\
+	"scan_dev_for_boot_part="                                         \
+		"part list ${devtype} ${devnum} -bootable devplist; "     \
+		"env exists devplist || setenv devplist 1; "              \
+		"for distro_bootpart in ${devplist}; do "                 \
+			"if fstype ${devtype} "                           \
+					"${devnum}:${distro_bootpart} "   \
+					"bootfstype; then "               \
+				"run scan_dev_for_boot; "                 \
+			"fi; "                                            \
+		"done; "                                                  \
+		"setenv devplist\0"					  \
+	\
+	BOOT_TARGET_DEVICES(BOOTENV_DEV)                                  \
+	\
+	"distro_bootcmd=" BOOTENV_SET_SCSI_NEED_INIT                      \
+		BOOTENV_SET_NVME_NEED_INIT                                \
+		BOOTENV_SET_IDE_NEED_INIT                                 \
+		BOOTENV_SET_VIRTIO_NEED_INIT                              \
+		"for target in ${boot_targets}; do "                      \
+			"run bootcmd_${target}; "                         \
+		"done\0"
+
+#ifndef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
+#endif
+
+#endif  /* _CONFIG_CMD_DISTRO_BOOTCMD_H */
diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h
new file mode 100644
index 0000000..c18f19a
--- /dev/null
+++ b/include/config_fallbacks.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2012 Texas Instruments
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License Version 2. This file is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __CONFIG_FALLBACKS_H
+#define __CONFIG_FALLBACKS_H
+
+#ifdef CONFIG_SPL
+#ifdef CONFIG_SPL_PAD_TO
+#ifdef CONFIG_SPL_MAX_SIZE
+#if CONFIG_SPL_PAD_TO && CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
+#error CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
+#endif
+#endif
+#else
+#ifdef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_PAD_TO	CONFIG_SPL_MAX_SIZE
+#else
+#define CONFIG_SPL_PAD_TO	0
+#endif
+#endif
+#endif
+
+#ifndef CONFIG_SYS_BAUDRATE_TABLE
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#endif
+
+/* Console I/O Buffer Size */
+#ifndef CONFIG_SYS_CBSIZE
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024
+#else
+#define CONFIG_SYS_CBSIZE	256
+#endif
+#endif
+
+#ifndef CONFIG_SYS_PBSIZE
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#endif
+
+#ifndef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS	16
+#endif
+
+#ifdef CONFIG_DM_I2C
+# ifdef CONFIG_SYS_I2C
+#  error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
+# endif
+#endif
+
+#endif	/* __CONFIG_FALLBACKS_H */
diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h
new file mode 100644
index 0000000..4f522db
--- /dev/null
+++ b/include/config_fsl_chain_trust.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CONFIG_FSL_CHAIN_TRUST_H
+#define __CONFIG_FSL_CHAIN_TRUST_H
+
+#ifdef CONFIG_CHAIN_OF_TRUST
+
+#ifndef CONFIG_EXTRA_ENV
+#define CONFIG_EXTRA_ENV	""
+#endif
+
+/*
+ * Control should not reach back to uboot after validation of images
+ * for secure boot flow and therefore bootscript should have
+ * the bootm command. If control reaches back to uboot anyhow
+ * after validating images, core should just spin.
+ */
+
+/*
+ * Define the key hash for boot script here if public/private key pair used to
+ * sign bootscript are different from the SRK hash put in the fuse
+ * Example of defining KEY_HASH is
+ * #define CONFIG_BOOTSCRIPT_KEY_HASH \
+ *	 "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
+ */
+
+#ifdef CONFIG_USE_BOOTARGS
+#define CONFIG_SET_BOOTARGS	"setenv bootargs \'" CONFIG_BOOTARGS" \';"
+#else
+#define CONFIG_SET_BOOTARGS	"setenv bootargs \'root=/dev/ram "	\
+				"rw console=ttyS0,115200 ramdisk_size=600000\';"
+#endif
+
+
+#ifdef CONFIG_BOOTSCRIPT_KEY_HASH
+#define CONFIG_SECBOOT \
+	"setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
+	CONFIG_SET_BOOTARGS	\
+	CONFIG_EXTRA_ENV	\
+	"esbc_validate $bs_hdraddr " \
+	  __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \
+	"source $img_addr;"	\
+	"esbc_halt\0"
+#else
+#define CONFIG_SECBOOT \
+	"setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \
+	CONFIG_SET_BOOTARGS	\
+	CONFIG_EXTRA_ENV	\
+	"esbc_validate $bs_hdraddr;" \
+	"source $img_addr;"	\
+	"esbc_halt\0"
+#endif
+
+#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
+#define CONFIG_BS_COPY_ENV \
+	"setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \
+	"setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \
+	"setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \
+	"setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \
+	"setenv bs_device " __stringify(CONFIG_BS_ADDR_DEVICE)";" \
+	"setenv bs_size " __stringify(CONFIG_BS_SIZE)";"
+
+/* For secure boot flow, default environment used will be used */
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_NAND_BOOT) || \
+	defined(CONFIG_SD_BOOT)
+#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_NAND_BOOT)
+#define CONFIG_BS_COPY_CMD \
+	"nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \
+	"nand read $bs_ram $bs_device $bs_size ;"
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_BS_COPY_CMD \
+	"mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \
+	"mmc read $bs_ram $bs_device $bs_size ;"
+#endif
+#else
+#define CONFIG_BS_COPY_CMD \
+	"cp.b $bs_hdr_device $bs_hdr_ram  $bs_hdr_size ;" \
+	"cp.b $bs_device $bs_ram  $bs_size ;"
+#endif
+#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */
+
+#ifndef CONFIG_BS_COPY_ENV
+#define CONFIG_BS_COPY_ENV
+#endif
+
+#ifndef CONFIG_BS_COPY_CMD
+#define CONFIG_BS_COPY_CMD
+#endif
+
+#define CONFIG_CHAIN_BOOT_CMD	CONFIG_BS_COPY_ENV \
+				CONFIG_BS_COPY_CMD \
+				CONFIG_SECBOOT
+
+#endif
+#endif
diff --git a/include/config_phylib_all_drivers.h b/include/config_phylib_all_drivers.h
new file mode 100644
index 0000000..36df725
--- /dev/null
+++ b/include/config_phylib_all_drivers.h
@@ -0,0 +1,32 @@
+/*
+ * Enable all PHYs
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * author Andy Fleming
+ *
+ */
+#ifndef _CONFIG_PHYLIB_ALL_H
+#define _CONFIG_PHYLIB_ALL_H
+
+#ifdef CONFIG_PHYLIB
+
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_BROADCOM
+#define CONFIG_PHY_DAVICOM
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_NATSEMI
+#define CONFIG_PHY_LXT
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_PHY_SMSC
+
+#ifdef CONFIG_PHYLIB_10G
+#define CONFIG_PHY_TERANETICS
+#endif /* CONFIG_PHYLIB_10G */
+
+#endif /* CONFIG_PHYLIB */
+
+#endif /*_CONFIG_PHYLIB_ALL_H */
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h
new file mode 100644
index 0000000..c2f9735
--- /dev/null
+++ b/include/config_uncmd_spl.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Ilya Yanok, ilya.yanok@gmail.com
+ */
+
+#ifndef __CONFIG_UNCMD_SPL_H__
+#define __CONFIG_UNCMD_SPL_H__
+
+#ifdef CONFIG_SPL_BUILD
+/* SPL needs only BOOTP + TFTP so undefine other stuff to save space */
+
+#ifndef CONFIG_SPL_DM
+#undef CONFIG_DM_SERIAL
+#undef CONFIG_DM_GPIO
+#undef CONFIG_DM_I2C
+#undef CONFIG_DM_SPI
+#endif
+
+#undef CONFIG_DM_WARN
+#undef CONFIG_DM_STDIO
+
+#endif /* CONFIG_SPL_BUILD */
+#endif /* __CONFIG_UNCMD_SPL_H__ */
diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h
new file mode 100644
index 0000000..4843a27
--- /dev/null
+++ b/include/configs/10m50_devboard.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+
+/*
+ * SERIAL
+ */
+#define CONFIG_SYS_NS16550_MEM32
+
+/*
+ * Flash
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+
+/*
+ * NET options
+ */
+#define CONFIG_SYS_RX_ETH_BUFFER	0
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * FDT options
+ */
+#define CONFIG_LMB
+
+/*
+ * MEMORY ORGANIZATION
+ * -Monitor at top of sdram.
+ * -The heap is placed below the monitor
+ * -The stack is placed below the heap (&grows down).
+ */
+#define CONFIG_SYS_SDRAM_BASE		0xc8000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_LEN		0x80000	/* Reserve 512k */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_MALLOC_LEN		0x20000
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+
+#define CONFIG_ENV_SIZE			0x10000	/* 64k, 1 sector */
+#define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+#define CONFIG_ENV_ADDR			(0xf4000000 + CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LOAD_ADDR		0xcc000000	/* Half of RAM */
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_ENV_SIZE - \
+					 CONFIG_SYS_MALLOC_LEN -	\
+					 0x10000)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h
new file mode 100644
index 0000000..f6ce430
--- /dev/null
+++ b/include/configs/3c120_devboard.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+
+/*
+ * SERIAL
+ */
+
+/*
+ * CFI Flash
+ */
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/*
+ * NET options
+ */
+#define CONFIG_SYS_RX_ETH_BUFFER	0
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * FDT options
+ */
+#define CONFIG_LMB
+
+/*
+ * MEMORY ORGANIZATION
+ * -Monitor at top of sdram.
+ * -The heap is placed below the monitor
+ * -The stack is placed below the heap (&grows down).
+ */
+#define CONFIG_SYS_SDRAM_BASE		0xD0000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_LEN		0x80000	/* Reserve 512k */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_MALLOC_LEN		0x20000
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+
+#define CONFIG_ENV_SIZE			0x20000	/* 128k, 1 sector */
+#define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+#define CONFIG_ENV_ADDR			(0xe2800000 + CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LOAD_ADDR		0xd4000000	/* Half of RAM */
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_ENV_SIZE - \
+					 CONFIG_SYS_MALLOC_LEN -	\
+					 0x10000)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
new file mode 100644
index 0000000..3ccd092
--- /dev/null
+++ b/include/configs/B4860QDS.h
@@ -0,0 +1,781 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * B4860 QDS board configuration file
+ */
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI	$(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW	$(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
+#ifndef CONFIG_NAND
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#else
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+#endif
+#endif
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#ifndef CONFIG_ARCH_B4420
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#endif
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR                0x77
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
+#define I2C_CH_DEFAULT                  0x8
+#define I2C_CH_VSC3316                  0xc
+#define I2C_CH_VSC3308                  0xd
+
+#define VSC3316_TX_ADDRESS              0x70
+#define VSC3316_RX_ADDRESS              0x71
+#define VSC3308_TX_ADDRESS              0x02
+#define VSC3308_RX_ADDRESS              0x03
+
+/* IDT clock synthesizers */
+#define CONFIG_IDT8T49N222A
+#define I2C_CH_IDT                     0x9
+
+#define IDT_SERDES1_ADDRESS            0x6E
+#define IDT_SERDES2_ADDRESS            0x6C
+
+/* Voltage monitor on channel 2*/
+#define I2C_MUX_CH_VOL_MONITOR		0xa
+#define I2C_VOL_MONITOR_ADDR		0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+
+#define CONFIG_ZM7300
+#define I2C_MUX_CH_DPM			0xa
+#define I2C_DPM_ADDR			0x28
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+#endif
+
+#if 0
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#endif
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		256 << 10
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_NAND
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x53
+
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128 * 1024 * 1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) | \
+				FTIM0_NOR_TEADC(0x04) | \
+				FTIM0_NOR_TEAHC(0x20))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x01) | \
+				FTIM2_NOR_TCH(0x0E) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define CONFIG_FSL_QIXIS_V2
+#define QIXIS_BASE		0xffdf0000
+#ifdef CONFIG_PHYS_64BIT
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+#else
+#define QIXIS_BASE_PHYS		QIXIS_BASE
+#endif
+#define QIXIS_LBMAP_SWITCH		0x01
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x02
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/*
+ * RapidIO
+ */
+#ifdef CONFIG_SYS_SRIO
+#ifdef CONFIG_SRIO1
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
+#endif
+
+#ifdef CONFIG_SRIO2
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
+#endif
+#endif
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * MAPLE
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
+#else
+#define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_BMAN_NUM_PORTALS	25
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE	0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE	0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE	CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE	(CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE	(CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE	(CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	25
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+
+#define CONFIG_SYS_DPAA_RMAN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_FMAN_FW_ADDR	(13 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x10
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x11
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
+#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
+
+/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7	 /*SLOT 1*/
+#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6	 /*SLOT 2*/
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
+
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define __USB_PHY_TYPE	ulpi
+
+#ifdef CONFIG_ARCH_B4860
+#define HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,"	\
+			"bank_intlv=cs0_cs1;"	\
+			"en_cpc:cpc2;"
+#else
+#define	HWCONFIG	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	HWCONFIG						\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"			\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=b4860qds/ramdisk.uboot\0"			\
+	"fdtaddr=1e00000\0"					\
+	"fdtfile=b4860qds/b4860qds.dtb\0"				\
+	"bdev=sda3\0"
+
+/* For emulation this causes u-boot to jump to the start of the proof point
+   app code automatically */
+#define CONFIG_PROOF_POINTS			\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "cpu 1 release 0x29000000 - - -;"		\
+ "cpu 2 release 0x29000000 - - -;"		\
+ "cpu 3 release 0x29000000 - - -;"		\
+ "cpu 4 release 0x29000000 - - -;"		\
+ "cpu 5 release 0x29000000 - - -;"		\
+ "cpu 6 release 0x29000000 - - -;"		\
+ "cpu 7 release 0x29000000 - - -;"		\
+ "go 0x29000000"
+
+#define CONFIG_HVBOOT	\
+ "setenv bootargs config-addr=0x60000000; "	\
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "cpu 1 release 0x01000000 - - -;"		\
+ "cpu 2 release 0x01000000 - - -;"		\
+ "cpu 3 release 0x01000000 - - -;"		\
+ "cpu 4 release 0x01000000 - - -;"		\
+ "cpu 5 release 0x01000000 - - -;"		\
+ "cpu 6 release 0x01000000 - - -;"		\
+ "cpu 7 release 0x01000000 - - -;"		\
+ "go 0x01000000"
+
+#define CONFIG_LINUX				\
+ "setenv bootargs root=/dev/ram rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "setenv ramdiskaddr 0x02000000;"		\
+ "setenv fdtaddr 0x01e00000;"			\
+ "setenv loadaddr 0x1000000;"			\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
new file mode 100644
index 0000000..b5d759c
--- /dev/null
+++ b/include/configs/BSC9131RDB.h
@@ -0,0 +1,348 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * BSC9131 RDB board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_NAND_FSL_IFC
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on 9131 RDB */
+#if defined(CONFIG_SYS_CLK_100)
+#define CONFIG_SYS_CLK_FREQ    100000000 /* SYSCLK for 9131 RDB */
+#else
+#define CONFIG_SYS_CLK_FREQ	66666666 /* SYSCLK for 9131 RDB */
+#endif
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* enable branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01ffffff
+
+/* DDR Setup */
+#undef CONFIG_SYS_DDR_RAW_TIMING
+#undef CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#define SPD_EEPROM_ADDRESS		0x52 /* I2C access */
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_sdram_size(void);
+#endif
+#define CONFIG_SYS_SDRAM_SIZE		get_sdram_size() /* DDR size */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
+#define CONFIG_SYS_DDR_TIMING_4		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5		0x02401400
+
+#define CONFIG_SYS_DDR_TIMING_3_800		0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_800		0x00110104
+#define CONFIG_SYS_DDR_TIMING_1_800		0x6f6b8644
+#define CONFIG_SYS_DDR_TIMING_2_800		0x0fa888cf
+#define CONFIG_SYS_DDR_CLK_CTRL_800		0x03000000
+#define CONFIG_SYS_DDR_MODE_1_800		0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL_800		0x0c300100
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8675f608
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR	CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
+
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses */
+							/* CONFIG_SYS_IMMR */
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x3FFF_FFFF	DDR			1G cacheable
+ * 0x8800_0000	0x8810_0000	IFC internal SRAM		1M
+ * 0xB000_0000	0xB0FF_FFFF	DSP core M2 memory	16M
+ * 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
+ * 0xC1F0_0000	0xC1F3_FFFF	PA L2 SRAM Region 0	256K
+ * 0xC1F8_0000	0xC1F9_FFFF	PA L2 SRAM Region 1	128K
+ * 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
+ * 0xFF60_0000	0xFF6F_FFFF	DSP CCSR		1M
+ * 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
+ * 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND flash buffer	8M
+ *
+ */
+
+/*
+ * IFC Definitions
+ */
+
+/* NAND Flash on IFC */
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	/* Port Size = 8 bit*/ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_2	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+/* NAND Flash Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03)  \
+					| FTIM0_NAND_TWP(0x05)   \
+					| FTIM0_NAND_TWCHT(0x02) \
+					| FTIM0_NAND_TWH(0x04))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1C) \
+					| FTIM1_NAND_TWBE(0x1E) \
+					| FTIM1_NAND_TRR(0x07)  \
+					| FTIM1_NAND_TRP(0x05))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08)  \
+					| FTIM2_NAND_TREH(0x04) \
+					| FTIM2_NAND_TWHRE(0x11))
+#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+/* Set up IFC registers for boot location NAND */
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
+
+/* Serial Port */
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* eSPI - Enhanced SPI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		3
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+
+#define TSEC2_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate change */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_HOSTNAME		"BSC9131rdb"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" CONFIG_UBOOTPATH "\0"				\
+	"loadaddr=1000000\0"			\
+	"bootfile=uImage\0"	\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=1e00000\0"				\
+	"fdtfile=bsc9131rdb.dtb\0"		\
+	"bdev=sda1\0"	\
+	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"	\
+	"bootm_size=0x37000000\0"	\
+	"othbootargs=ramdisk_size=600000 " \
+	"default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
+	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"usb start;"			\
+	"ext2load usb 0:4 $loadaddr $bootfile;"		\
+	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
+	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
+
+#define CONFIG_RAMBOOTCOMMAND		\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
new file mode 100644
index 0000000..1c615ac
--- /dev/null
+++ b/include/configs/BSC9132QDS.h
@@ -0,0 +1,565 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * BSC9132 QDS board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+#ifdef CONFIG_NAND_SECBOOT
+#define CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0x8ffffffc
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"PCIe Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xC0010000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xC0010000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SYS_CLK_100_DDR_100)
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	100000000
+#elif defined(CONFIG_SYS_CLK_100_DDR_133)
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133000000
+#endif
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* enable branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01ffffff
+
+/* DDR Setup */
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#define SPD_EEPROM_ADDRESS1		0x54 /* I2C access */
+#define SPD_EEPROM_ADDRESS2		0x56 /* I2C access */
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_SDRAM_SIZE		(1024)
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+/* DDR3 Controller Settings */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG_1333	0x80004302
+#define CONFIG_SYS_DDR_CS0_CONFIG_800	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CONFIG_SYS_DDR1_CS0_BNDS       0x0040007F
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL_800		0x470C0000
+#define CONFIG_SYS_DDR_CONTROL_2_800	0x04401050
+#define CONFIG_SYS_DDR_TIMING_4_800		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5_800		0x03402400
+
+#define CONFIG_SYS_DDR_CONTROL_1333		0x470C0008
+#define CONFIG_SYS_DDR_CONTROL_2_1333	0x24401010
+#define CONFIG_SYS_DDR_TIMING_4_1333		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5_1333		0x03401400
+
+#define CONFIG_SYS_DDR_TIMING_3_800		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800		0x00330004
+#define CONFIG_SYS_DDR_TIMING_1_800		0x6f6B4846
+#define CONFIG_SYS_DDR_TIMING_2_800		0x0FA8C8CF
+#define CONFIG_SYS_DDR_CLK_CTRL_800		0x03000000
+#define CONFIG_SYS_DDR_MODE_1_800		0x40461520
+#define CONFIG_SYS_DDR_MODE_2_800		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL_800		0x0C300000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8655A608
+
+#define CONFIG_SYS_DDR_TIMING_3_1333		0x01061000
+#define CONFIG_SYS_DDR_TIMING_0_1333		0x00440104
+#define CONFIG_SYS_DDR_TIMING_1_1333		0x98913A45
+#define CONFIG_SYS_DDR_TIMING_2_1333		0x0FB8B114
+#define CONFIG_SYS_DDR_CLK_CTRL_1333		0x02800000
+#define CONFIG_SYS_DDR_MODE_1_1333		0x00061A50
+#define CONFIG_SYS_DDR_MODE_2_1333		0x00100000
+#define CONFIG_SYS_DDR_INTERVAL_1333		0x144E0513
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333	0x8655F607
+
+/*FIXME: the following params are constant w.r.t diff freq
+combinations. this should be removed later
+*/
+#if CONFIG_DDR_CLK_FREQ == 100000000
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
+#define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_800
+#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
+#define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_800
+#define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_800
+#elif CONFIG_DDR_CLK_FREQ == 133000000
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
+#define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_1333
+#define CONFIG_SYS_DDR_CONTROL_2	CONFIG_SYS_DDR_CONTROL_2_1333
+#define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_1333
+#define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_1333
+#else
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
+#define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_800
+#define CONFIG_SYS_DDR_CONTROL_2	CONFIG_SYS_DDR_CONTROL_2_800
+#define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_800
+#define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_800
+#endif
+
+/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR	CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
+
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR
+
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+
+#define CONFIG_SYS_FLASH_BASE		0x88000000
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* Max number of sector: 32M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_NOR_CSPR	0x88000101
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(5)
+/* NOR Flash Timing Params */
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) \
+				| FTIM0_NOR_TEADC(0x03) \
+				| FTIM0_NOR_TAVDS(0x00) \
+				| FTIM0_NOR_TEAHC(0x0f))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1d) \
+				| FTIM1_NOR_TRAD_NOR(0x09) \
+				| FTIM1_NOR_TSEQRAD_NOR(0x09))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x1) \
+				| FTIM2_NOR_TCH(0x4) \
+				| FTIM2_NOR_TWPH(0x7) \
+				| FTIM2_NOR_TWP(0x1e))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+/* CFI for NOR Flash */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* NAND Flash on IFC */
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_2	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+/* NAND Flash Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03) \
+					| FTIM0_NAND_TWP(0x05) \
+					| FTIM0_NAND_TWCHT(0x02) \
+					| FTIM0_NAND_TWH(0x04))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1c) \
+					| FTIM1_NAND_TWBE(0x1e) \
+					| FTIM1_NAND_TRR(0x07) \
+					| FTIM1_NAND_TRP(0x05))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08) \
+					| FTIM2_NAND_TREH(0x04) \
+					| FTIM2_NAND_TWHRE(0x11))
+#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+/* NAND */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FSL_QIXIS
+#endif
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_SYS_FPGA_BASE	0xffb00000
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_BASE	CONFIG_SYS_FPGA_BASE
+#define QIXIS_LBMAP_SWITCH	9
+#define QIXIS_LBMAP_MASK	0x07
+#define QIXIS_LBMAP_SHIFT	0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x83
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+
+#define CONFIG_SYS_FPGA_BASE_PHYS	CONFIG_SYS_FPGA_BASE
+
+#define CONFIG_SYS_CSPR2		(CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
+					| CSPR_PORT_SIZE_8 \
+					| CSPR_MSEL_GPCM \
+					| CSPR_V)
+#define CONFIG_SYS_AMASK2		IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2		0x0
+/* CPLD Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+#endif
+
+/* Set up IFC registers for boot location NOR/NAND */
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
+
+/* Serial Port */
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR + 0x4700)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR + 0x4800)
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400800 /* I2C speed and slave address*/
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400800 /* I2C speed and slave address*/
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C EEPROM */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+
+/* enable read and write access to EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* I2C FPGA */
+#define CONFIG_I2C_FPGA
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+
+#define CONFIG_RTC_DS3231
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * SPI interface will not be available in case of NAND boot SPI CS0 will be
+ * used for SLIC
+ */
+/* eSPI - Enhanced SPI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+/* TBI PHY configuration for SGMII mode */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+		TBICR_PHY_RESET \
+		| TBICR_ANEG_ENABLE \
+		| TBICR_FULL_DUPLEX \
+		| TBICR_SPEED1_SET \
+		)
+
+#endif	/* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE			0x2000
+#else
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME		"BSC9132qds"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_DEF_HWCONFIG	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+#else
+#define CONFIG_DEF_HWCONFIG	"hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" CONFIG_UBOOTPATH "\0"				\
+	"loadaddr=1000000\0"			\
+	"bootfile=uImage\0"	\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=1e00000\0"				\
+	"fdtfile=bsc9132qds.dtb\0"		\
+	"bdev=sda1\0"	\
+	CONFIG_DEF_HWCONFIG\
+	"othbootargs=mem=880M ramdisk_size=600000 " \
+		"default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
+		"isolcpus=0\0" \
+	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
+		"console=$consoledev,$baudrate $othbootargs; "	\
+		"usb start;"			\
+		"ext2load usb 0:4 $loadaddr $bootfile;"		\
+		"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
+		"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
+	"debug_halt_off=mw ff7e0e30 0xf0000000;"
+
+#define CONFIG_NFSBOOTCOMMAND	\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "	\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;" \
+	"tftp $loadaddr $bootfile;"	\
+	"tftp $fdtaddr $fdtfile;"	\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT	\
+	"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
+	"console=$consoledev,$baudrate $othbootargs;" \
+	"usb start;"	\
+	"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
+	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
new file mode 100644
index 0000000..5a1a29b
--- /dev/null
+++ b/include/configs/C29XPCIE.h
@@ -0,0 +1,456 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * C29XPCIE board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifdef CONFIG_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_TPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_TPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_TPL_TEXT_BASE
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ	100000000
+#define CONFIG_SYS_CLK_FREQ	66666666
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/* DDR Setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#define SPD_EEPROM_ADDRESS		0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/* DDR ECC Setup*/
+#define CONFIG_DDR_ECC
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+
+#define CONFIG_SYS_SDRAM_SIZE		512
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* Platform SRAM setting  */
+#define CONFIG_SYS_PLATFORM_SRAM_BASE	0xffb00000
+#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
+			(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
+#define CONFIG_SYS_PLATFORM_SRAM_SIZE	(512 << 10)
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+#define CONFIG_SYS_FLASH_BASE		0xec000000
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* in ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* in ms */
+
+/* 16Bit NOR Flash - S29GL512S10TFI01 */
+#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(64*1024*1024)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+/* CFI for NOR Flash */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(1024 * 1024)
+
+/* 8Bit NAND Flash - K9F1G08U0B */
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_NAND \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_OOBSIZE	0x00000280	/* 640b */
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
+				| CSOR_NAND_PGS_8K	/* Page Size = 8K */ \
+				| CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
+				| CSOR_NAND_PB(128))	/*128 Pages Per Block*/
+#define CONFIG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x01) | \
+				FTIM0_NAND_TWP(0x0c)   | \
+				FTIM0_NAND_TWCHT(0x08) | \
+				FTIM0_NAND_TWH(0x06))
+#define CONFIG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x28) | \
+				FTIM1_NAND_TWBE(0x1d)  | \
+				FTIM1_NAND_TRR(0x08)   | \
+				FTIM1_NAND_TRP(0x0c))
+#define CONFIG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x0c) | \
+				FTIM2_NAND_TREH(0x0a) | \
+				FTIM2_NAND_TWHRE(0x18))
+#define CONFIG_SYS_NAND_FTIM3	(FTIM3_NAND_TWW(0x04))
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT		CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR1_EXT		CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+/* CPLD on IFC, selected by CS2 */
+#define CONFIG_SYS_CPLD_BASE		0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull \
+					| CONFIG_SYS_CPLD_BASE)
+
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2	0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
+				FTIM0_GPCM_TEADC(0x0e) | \
+				FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1	(FTIM1_GPCM_TACO(0x0e) | \
+				FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2	(FTIM2_GPCM_TCS(0x0e) | \
+				FTIM2_GPCM_TCH(0x8) | \
+				FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3	0x0
+
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C EEPROM */
+/* enable read and write access to EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* eSPI - Enhanced SPI */
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+/* Default mode is RGMII mode */
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		2
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE	CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET	CONFIG_SYS_NAND_BLOCK_SIZE
+#else
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_DEF_HWCONFIG	fsl_ddr:ecc=on
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"	\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"loadaddr=1000000\0"				\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"				\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=1e00000\0"				\
+	"fdtfile=name/of/device-tree.dtb\0"			\
+	"othbootargs=ramdisk_size=600000\0"		\
+
+#define CONFIG_RAMBOOTCOMMAND			\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
new file mode 100644
index 0000000..0a356f4
--- /dev/null
+++ b/include/configs/M5208EVBE.h
@@ -0,0 +1,181 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Freescale MCF5208EVBe.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+#ifndef _M5208EVBE_H
+#define _M5208EVBE_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT		5000
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#endif				/* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME		"M5208EVBe"
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off 0 3ffff;"		\
+	"era 0 3ffff;"				\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+
+#define CONFIG_SYS_LOAD_ADDR	0x40010000
+
+#define CONFIG_SYS_CLK		166666666	/* CPU Core Clock */
+#define CONFIG_SYS_PLL_ODR	0x36
+#define CONFIG_SYS_PLL_FDR	0x7D
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x43711630
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1002000
+#define CONFIG_SYS_SDRAM_EMOD		0x80010000
+#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/* FLASH organization */
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	254	/* max number of sectors on one chip */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+/*
+ * Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET		0x2000
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x2000
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text*);
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/* Chipselect bank definitions */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x007F0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+
+#endif				/* _M5208EVBE_H */
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
new file mode 100644
index 0000000..a9c260d
--- /dev/null
+++ b/include/configs/M52277EVB.h
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Freescale MCF52277 EVB board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M52277EVB_H
+#define _M52277EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#define CONFIG_HOSTNAME			"M52277EVB"
+#define CONFIG_SYS_UBOOT_END		0x3FFFF
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
+#ifdef CONFIG_SYS_STMICRO_BOOT
+/* ST Micro serial flash */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=loadb ${loadaddr} ${baudrate};"	\
+	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
+	"upd=run load; run prog\0"		\
+	"prog=sf probe 0:2 10000 1;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
+	"save\0"				\
+	""
+#endif
+#ifdef CONFIG_SYS_SPANSION_BOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=loadb ${loadaddr} ${baudrate}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
+	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
+	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
+	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" ${filesize}; save\0"			\
+	"updsbf=run loadsbf; run progsbf\0"	\
+	"loadsbf=loadb ${loadaddr} ${baudrate};"	\
+	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
+	"progsbf=sf probe 0:2 10000 1;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
+	""
+#endif
+
+/* LCD */
+#ifdef CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_LCD_LOGO
+#define CONFIG_SHARP_LQ035Q7DH06
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_SYS_USB_EHCI_REGS_BASE	0xFC0B0000
+#define CONFIG_SYS_USB_EHCI_CPU_INIT
+#endif
+
+/* Realtime clock */
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_DSPI
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_SYS_INPUT_CLKSRC	16000000
+
+#define CONFIG_PRAM		2048	/* 2048 KB */
+
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x43711630
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x81810000
+#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x00
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*
+ * Configuration for environment
+ * Environment is not embedded in u-boot. First time runing may have env
+ * crc error warning if there is no correct environment on the flash.
+ */
+#define CONFIG_ENV_OVERWRITE		1
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_STMICRO_BOOT
+#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_ENV_OFFSET	0x30000
+#	define CONFIG_ENV_SIZE		0x1000
+#	define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#ifdef CONFIG_SYS_SPANSION_BOOT
+#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#	define CONFIG_ENV_SIZE		0x1000
+#	define CONFIG_ENV_SECT_SIZE	0x8000
+#endif
+
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_SPANSION_S29WS_N	1
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
+#endif
+
+#define LDS_BOARD_TEXT \
+        arch/m68k/cpu/mcf5227x/built-in.o   (.text*) \
+	arch/m68k/lib/built-in.o            (.text*)
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#	define CONFIG_JFFS2_DEV		"nor0"
+#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x40000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x40000)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+#ifdef CONFIG_CF_SBF
+#define CONFIG_SYS_CS0_BASE		0x04000000
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#else
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#endif
+
+#endif				/* _M52277EVB_H */
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
new file mode 100644
index 0000000..a197c3a
--- /dev/null
+++ b/include/configs/M5235EVB.h
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5235EVB_H
+#define _M5235EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_i2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_I2C_PINMUX_REG	(gpio->par_qspi)
+#define CONFIG_SYS_I2C_PINMUX_CLR	~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
+#define CONFIG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#define CONFIG_BOOTFILE		"u-boot.bin"
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		"M5235EVB"
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b ${loadaddr} ffe00000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE+0x20000)
+
+#define CONFIG_SYS_CLK			75000000
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
+
+#define CONFIG_SYS_MBAR		0x40000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#ifdef NORFLASH_PS32BIT
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
+#else
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#endif
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text);
+
+#ifdef NORFLASH_PS32BIT
+#	define CONFIG_ENV_OFFSET		(0x8000)
+#	define CONFIG_ENV_SIZE		0x4000
+#	define CONFIG_ENV_SECT_SIZE	0x4000
+#else
+#	define CONFIG_ENV_OFFSET		(0x4000)
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x2000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ * CS6 - Available
+ * CS7 - Available
+ */
+#ifdef NORFLASH_PS32BIT
+#	define CONFIG_SYS_CS0_BASE	0xFFC00000
+#	define CONFIG_SYS_CS0_MASK	0x003f0001
+#	define CONFIG_SYS_CS0_CTRL	0x00001D00
+#else
+#	define CONFIG_SYS_CS0_BASE	0xFFE00000
+#	define CONFIG_SYS_CS0_MASK	0x001f0001
+#	define CONFIG_SYS_CS0_CTRL	0x00001D80
+#endif
+
+#endif				/* _M5329EVB_H */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
new file mode 100644
index 0000000..f214dc9
--- /dev/null
+++ b/include/configs/M5249EVB.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the esd TASREG board.
+ *
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5249EVB_H
+#define _M5249EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef  CONFIG_WATCHDOG
+
+#undef CONFIG_MONITOR_IS_IN_RAM		/* no pre-loader required!!! ;-) */
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
+
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+/*
+ * Clock configuration: enable only one of the following options
+ */
+
+#undef  CONFIG_SYS_PLL_BYPASS				/* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
+#define	CONFIG_SYS_CLK			132025600	/* MCF5249 can run at 140MHz   */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define	CONFIG_SYS_MBAR2		0x80000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text);
+
+#define CONFIG_ENV_OFFSET		0x4000	/* Address of Environment Sector*/
+#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	0x2000 /* see README - env sector total size	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+
+#if 0 /* test-only */
+#define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define	CONFIG_SYS_CS0_BASE		0xffe00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
+/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
+
+/* CS1 - FPGA, address 0xe0000000 */
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define	CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
+#define	CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
+#define	CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define	CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led                     */
+
+#endif	/* M5249 */
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
new file mode 100644
index 0000000..1199fa3
--- /dev/null
+++ b/include/configs/M5253DEMO.h
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ */
+
+#ifndef _M5253DEMO_H
+#define _M5253DEMO_H
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef CONFIG_WATCHDOG		/* disable watchdog */
+
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#	define CONFIG_ENV_OFFSET		0x4000
+#	define CONFIG_ENV_SECT_SIZE	0x1000
+#else
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
+#	define CONFIG_ENV_SECT_SIZE	0x1000
+#endif
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text*);
+
+/*
+ * Command line configuration.
+ */
+
+#ifdef CONFIG_IDE
+/* ATA */
+#	define CONFIG_IDE_RESET		1
+#	define CONFIG_IDE_PREINIT	1
+#	define CONFIG_ATAPI
+#	undef CONFIG_LBA48
+
+#	define CONFIG_SYS_IDE_MAXBUS		1
+#	define CONFIG_SYS_IDE_MAXDEVICE	2
+
+#	define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
+#	define CONFIG_SYS_ATA_IDE0_OFFSET	0
+
+#	define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
+#	define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#	define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
+#	define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
+#endif
+
+#define CONFIG_DRIVER_DM9000
+#ifdef CONFIG_DRIVER_DM9000
+#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
+#	define DM9000_IO		CONFIG_DM9000_BASE
+#	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
+#	undef CONFIG_DM9000_DEBUG
+#	define CONFIG_DM9000_BYTE_SWAPPED
+
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#	define CONFIG_EXTRA_ENV_SETTINGS		\
+		"netdev=eth0\0"				\
+		"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+		"loadaddr=10000\0"			\
+		"u-boot=u-boot.bin\0"			\
+		"load=tftp ${loadaddr) ${u-boot}\0"	\
+		"upd=run load; run prog\0"		\
+		"prog=prot off 0xff800000 0xff82ffff;"	\
+		"era 0xff800000 0xff82ffff;"		\
+		"cp.b ${loadaddr} 0xff800000 ${filesize};"	\
+		"save\0"				\
+		""
+#endif
+
+#define CONFIG_HOSTNAME		"M5253DEMO"
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000280
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_I2C_PINMUX_REG	(*(u32 *) (CONFIG_SYS_MBAR+0x19C))
+#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
+#define CONFIG_SYS_I2C_PINMUX_SET	(0)
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
+#	define CONFIG_SYS_PLLCR	0x1243E054
+#	define CONFIG_SYS_CLK		140000000
+#else
+#	define CONFIG_SYS_PLLCR	0x135a4140
+#	define CONFIG_SYS_CLK		70000000
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#	define CONFIG_SYS_MONITOR_BASE	0x20000
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		0x40000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+
+#define FLASH_SST6401B		0x200
+#define SST_ID_xF6401B		0x236D236D
+
+#ifdef CONFIG_SYS_FLASH_CFI
+/*
+ * Unable to use CFI driver, due to incompatible sector erase command by SST.
+ * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
+ * 0x30 is block erase in SST
+ */
+#	define CONFIG_SYS_FLASH_SIZE		0x800000
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_FLASH_CFI_LEGACY
+#else
+#	define CONFIG_SYS_SST_SECT		2048
+#	define CONFIG_SYS_SST_SECTSZ		0x1000
+#	define CONFIG_SYS_FLASH_WRITE_TOUT	500
+#endif
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(8) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
+/* Port configuration */
+#define CONFIG_SYS_FECI2C		0xF0
+
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		0x007F0021
+#define CONFIG_SYS_CS0_CTRL		0x00001D80
+
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		0x00000001
+#define CONFIG_SYS_CS1_CTRL		0x00003DD8
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
+#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
+#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
+#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */
+
+#endif				/* _M5253DEMO_H */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
new file mode 100644
index 0000000..9d3bf42
--- /dev/null
+++ b/include/configs/M5272C3.h
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Motorola MC5272C3 board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5272C3_H
+#define _M5272C3_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
+
+#undef CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#else
+#define CONFIG_ENV_ADDR		0xffe04000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#endif
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text);
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#endif				/* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME		"M5272C3"
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b ${loadaddr} ffe00000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_SYS_LOAD_ADDR		0x20000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+#define CONFIG_SYS_CLK			66000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define CONFIG_SYS_SCR			0x0003
+#define CONFIG_SYS_SPR			0xffff
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		4	/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		0xffe00000
+
+#ifdef	CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE	0x20000
+#else
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
+#define CONFIG_SYS_OR0_PRELIM		0xFFE00014
+#define CONFIG_SYS_BR1_PRELIM		0
+#define CONFIG_SYS_OR1_PRELIM		0
+#define CONFIG_SYS_BR2_PRELIM		0x30000001
+#define CONFIG_SYS_OR2_PRELIM		0xFFF80000
+#define CONFIG_SYS_BR3_PRELIM		0
+#define CONFIG_SYS_OR3_PRELIM		0
+#define CONFIG_SYS_BR4_PRELIM		0
+#define CONFIG_SYS_OR4_PRELIM		0
+#define CONFIG_SYS_BR5_PRELIM		0
+#define CONFIG_SYS_OR5_PRELIM		0
+#define CONFIG_SYS_BR6_PRELIM		0
+#define CONFIG_SYS_OR6_PRELIM		0
+#define CONFIG_SYS_BR7_PRELIM		0x00000701
+#define CONFIG_SYS_OR7_PRELIM		0xFFC0007C
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_PACNT		0x00000000
+#define CONFIG_SYS_PADDR		0x0000
+#define CONFIG_SYS_PADAT		0x0000
+#define CONFIG_SYS_PBCNT		0x55554155	/* Ethernet/UART configuration */
+#define CONFIG_SYS_PBDDR		0x0000
+#define CONFIG_SYS_PBDAT		0x0000
+#define CONFIG_SYS_PDCNT		0x00000000
+#endif				/* _M5272C3_H */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
new file mode 100644
index 0000000..682e2e3
--- /dev/null
+++ b/include/configs/M5275EVB.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Motorola MC5275EVB board.
+ *
+ * By Arthur Shipkowski <art@videon-central.com>
+ * Copyright (C) 2005 Videon Central, Inc.
+ *
+ * Based off of M5272C3 board code by Josef Baumgartner
+ * <josef.baumgartner@telex.de>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5275EVB_H
+#define _M5275EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#else
+#define CONFIG_ENV_ADDR		0xffe04000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#endif
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text);
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Available command configuration */
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#define CONFIG_MII_INIT		1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FEC0_PINMUX		0
+#define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#define CONFIG_SYS_FEC1_PINMUX		0
+#define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
+#define MCFFEC_TOUT_LOOP	50000
+#define CONFIG_HAS_ETH1
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#ifndef CONFIG_SYS_DISCOVER_PHY
+#define FECDUPLEX		FULL
+#define FECSPEED		_100BASET
+#else
+#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#endif
+#endif
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_I2C_PINMUX_REG	(gpio_reg->par_feci2c)
+#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFF0)
+#define CONFIG_SYS_I2C_PINMUX_SET	(0x000F)
+
+#define CONFIG_SYS_LOAD_ADDR		0x800000
+
+#define CONFIG_BOOTCOMMAND	"bootm ffe40000"
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_NET_RETRY_COUNT	5
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${uboot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b ${loadaddr} ffe00000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_SYS_CLK			150000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_MBAR		0x40000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE	0x20000
+#else
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+
+#define CONFIG_SYS_FLASH_SIZE		0x200000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+#define CONFIG_SYS_CS0_BASE		0xffe00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
+
+#define CONFIG_SYS_CS1_BASE		0x30000000
+#define CONFIG_SYS_CS1_CTRL		0x00001900
+#define CONFIG_SYS_CS1_MASK		0x00070001
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_FECI2C		0x0FA0
+
+#endif	/* _M5275EVB_H */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
new file mode 100644
index 0000000..a068726
--- /dev/null
+++ b/include/configs/M5282EVB.h
@@ -0,0 +1,204 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Motorola MC5282EVB board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _CONFIG_M5282EVB_H
+#define _CONFIG_M5282EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_ADDR		0xffe04000
+#define CONFIG_ENV_SIZE		0x2000
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text*);
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#endif				/* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME		"M5282EVB"
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b ${loadaddr} ffe00000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_SYS_LOAD_ADDR		0x20000
+
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+#define	CONFIG_SYS_CLK			64000000
+
+/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
+
+#define CONFIG_SYS_MFD			0x02	/* PLL Multiplication Factor Devider */
+#define CONFIG_SYS_RFD			0x00	/* PLL Reduce Frecuency Devider */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define	CONFIG_SYS_MBAR		0x40000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define	CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define	CONFIG_SYS_INT_FLASH_BASE	0xf0000000
+#define CONFIG_SYS_INT_FLASH_ENABLE	0x21
+
+/* If M5282 port is fully implemented the monitor base will be behind
+ * the vector table. */
+#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#else
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x418)	/* 24 Byte for CFM-Config */
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DBWE | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
+#define CONFIG_SYS_PADDR		0x0000000
+#define CONFIG_SYS_PADAT		0x0000000
+
+#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
+#define CONFIG_SYS_PBDDR		0x0000000
+#define CONFIG_SYS_PBDAT		0x0000000
+
+#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
+
+#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
+
+#define CONFIG_SYS_PEHLPAR		0xC0
+#define CONFIG_SYS_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
+#define CONFIG_SYS_DDRUA		0x05
+#define CONFIG_SYS_PJPAR		0xFF
+
+#endif				/* _CONFIG_M5282EVB_H */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
new file mode 100644
index 0000000..39e2748
--- /dev/null
+++ b/include/configs/M53017EVB.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Freescale MCF53017EVB.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M53017EVB_H
+#define _M53017EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT		5000
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_TX_ETH_BUFFER	8
+#	define CONFIG_SYS_FEC_BUF_USE_SRAM
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_PINMUX	0
+#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_CNT		(0x8000)
+#define CONFIG_SYS_RTC_SETUP		(RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		"M53017"
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off 0 3ffff;"		\
+	"era 0 3ffff;"				\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+
+#define CONFIG_SYS_LOAD_ADDR	0x40010000
+
+#define CONFIG_SYS_CLK		80000000
+#define CONFIG_SYS_CPU_CLK	CONFIG_SYS_CLK * 3
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x20000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x43711630
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x80010000
+#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_SPANSION_S29WS_N	1
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x8000
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text*)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Ext SRAM
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+
+#define CONFIG_SYS_CS1_BASE		0xC0000000
+#define CONFIG_SYS_CS1_MASK		0x00070001
+#define CONFIG_SYS_CS1_CTRL		0x00001FA0
+
+#endif				/* _M53017EVB_H */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
new file mode 100644
index 0000000..7a96dd1
--- /dev/null
+++ b/include/configs/M5329EVB.h
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5329EVB_H
+#define _M5329EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		"M5329EVB"
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"			\
+	"loadaddr=40010000\0"	\
+	"u-boot=u-boot.bin\0"	\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"	\
+	"prog=prot off 0 3ffff;"	\
+	"era 0 3ffff;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"	\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+
+#define CONFIG_SYS_LOAD_ADDR		0x40010000
+
+#define CONFIG_SYS_CLK			80000000
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x53722730
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#endif
+
+#ifdef CONFIG_NANDFLASH_SIZE
+#	define CONFIG_SYS_MAX_NAND_DEVICE	1
+#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
+#	define CONFIG_SYS_NAND_SIZE		1
+#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#	define NAND_ALLOW_ERASE_ALL	1
+#	define CONFIG_JFFS2_NAND	1
+#	define CONFIG_JFFS2_DEV		"nand0"
+#	define CONFIG_JFFS2_PART_SIZE	(CONFIG_SYS_CS2_MASK & ~1)
+#	define CONFIG_JFFS2_PART_OFFSET	0x00000000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text*);
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - NAND Flash 16, 32, or 64MB
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x007f0001
+#define CONFIG_SYS_CS0_CTRL		0x00001fa0
+
+#define CONFIG_SYS_CS1_BASE		0x10000000
+#define CONFIG_SYS_CS1_MASK		0x001f0001
+#define CONFIG_SYS_CS1_CTRL		0x002A3780
+
+#ifdef CONFIG_NANDFLASH_SIZE
+#define CONFIG_SYS_CS2_BASE		0x20000000
+#define CONFIG_SYS_CS2_MASK		((CONFIG_NANDFLASH_SIZE << 20) | 1)
+#define CONFIG_SYS_CS2_CTRL		0x00001f60
+#endif
+
+#endif				/* _M5329EVB_H */
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
new file mode 100644
index 0000000..f62fb5a
--- /dev/null
+++ b/include/configs/M5373EVB.h
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Freescale MCF5373 FireEngine board.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5373EVB_H
+#define _M5373EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	3360	/* timeout in ms, max is 3.36 sec */
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		"M5373EVB"
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"			\
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"	\
+	"u-boot=u-boot.bin\0"	\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"	\
+	"prog=prot off 0 3ffff;"	\
+	"era 0 3ffff;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"	\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+
+#define CONFIG_SYS_LOAD_ADDR		0x40010000
+
+#define CONFIG_SYS_CLK			80000000
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x53722730
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#endif
+
+#ifdef CONFIG_NANDFLASH_SIZE
+#	define CONFIG_SYS_MAX_NAND_DEVICE	1
+#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
+#	define CONFIG_SYS_NAND_SIZE		1
+#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#	define NAND_ALLOW_ERASE_ALL	1
+#	define CONFIG_JFFS2_NAND	1
+#	define CONFIG_JFFS2_DEV		"nand0"
+#	define CONFIG_JFFS2_PART_SIZE	(CONFIG_SYS_CS2_MASK & ~1)
+#	define CONFIG_JFFS2_PART_OFFSET	0x00000000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text*);
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - NAND Flash 16, 32, or 64MB
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x007f0001
+#define CONFIG_SYS_CS0_CTRL		0x00001fa0
+
+#define CONFIG_SYS_CS1_BASE		0x10000000
+#define CONFIG_SYS_CS1_MASK		0x001f0001
+#define CONFIG_SYS_CS1_CTRL		0x002A3780
+
+#ifdef CONFIG_NANDFLASH_SIZE
+#define CONFIG_SYS_CS2_BASE		0x20000000
+#define CONFIG_SYS_CS2_MASK		((CONFIG_NANDFLASH_SIZE << 20) | 1)
+#define CONFIG_SYS_CS2_CTRL		0x00001f60
+#endif
+
+#endif				/* _M5373EVB_H */
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
new file mode 100644
index 0000000..e07684d
--- /dev/null
+++ b/include/configs/M54418TWR.h
@@ -0,0 +1,309 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Freescale MCF54418 TWR board.
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M54418TWR_H
+#define _M54418TWR_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#define LDS_BOARD_TEXT			board/freescale/m54418twr/sbf_dram_init.o (.text*)
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * NAND FLASH
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_JFFS2_NAND
+#define CONFIG_NAND_FSL_NFC
+#define CONFIG_SYS_NAND_BASE		0xFC0FC000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE
+#endif
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#define CONFIG_MII_INIT		1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER	2
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_TX_ETH_BUFFER	2
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_SYS_FEC0_PINMUX		0
+#define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#define CONFIG_SYS_FEC1_PINMUX		0
+#define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_MIIBASE
+#define MCFFEC_TOUT_LOOP		50000
+#define CONFIG_SYS_FEC0_PHYADDR	0
+#define CONFIG_SYS_FEC1_PHYADDR	1
+
+#define CONFIG_ETHPRIME	"FEC0"
+#define CONFIG_IPADDR		192.168.1.2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP	192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+
+#define CONFIG_SYS_FEC_BUF_USE_SRAM
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#ifndef CONFIG_SYS_DISCOVER_PHY
+#define FECDUPLEX	FULL
+#define FECSPEED	_100BASET
+#define LINKSTATUS	1
+#else
+#define LINKSTATUS	0
+#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#endif
+#endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME		"M54418TWR"
+
+#if defined(CONFIG_CF_SBF)
+/* ST Micro serial flash */
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"sbfhdr=sbfhdr.bin\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${sbfhdr};"	\
+	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
+	"upd=run load; run prog\0"		\
+	"prog=sf probe 0:1 1000000 3;"		\
+	"sf erase 0 40000;"			\
+	"sf write ${loadaddr} 0 40000;"		\
+	"save\0"				\
+	""
+#elif defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${u-boot};\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=nand device 0;"			\
+	"nand erase 0 40000;"			\
+	"nb_update ${loadaddr} ${filesize};"	\
+	"save\0"				\
+	""
+#else
+#define CONFIG_SYS_UBOOT_END	0x3FFFF
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off mram" " ;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+#endif
+
+/* Realtime clock */
+#undef CONFIG_MCFRTC
+#define CONFIG_RTC_MCFRRTC
+#define CONFIG_SYS_MCFRRTC_BASE		0xFC0A8000
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#undef CONFIG_SYS_FSL_I2C
+#undef	CONFIG_SYS_I2C_SOFT	/* I2C bit-banged */
+/* I2C speed and slave address  */
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM			2048	/* 2048 KB */
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x400)
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_DRAM_TEST
+
+#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_SERIAL_BOOT
+#endif
+
+#if defined(CONFIG_SERIAL_BOOT)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
+#else
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
+/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
+				(CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#if !defined(CONFIG_SERIAL_BOOT)  /*MRAM boot*/
+#define CONFIG_ENV_ADDR		(0x40000 - 0x1000) /*MRAM size 40000*/
+#define CONFIG_ENV_SIZE		0x1000
+#endif
+
+#if defined(CONFIG_CF_SBF)
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#endif
+#if defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_ENV_OFFSET	0x80000
+#define CONFIG_ENV_SIZE	0x20000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+#undef CONFIG_ENV_OVERWRITE
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+#ifdef CONFIG_SYS_FLASH_CFI
+
+/* Max size that the board might have */
+#define CONFIG_SYS_FLASH_SIZE		0x1000000
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	270
+/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
+#else
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	270
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	0
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_OFFSET	(0x800000)
+
+#endif
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR + \
+			CONFIG_SYS_INIT_RAM_SIZE - 12)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 16MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+ /* Flash */
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x000F0101
+#define CONFIG_SYS_CS0_CTRL		0x00001D60
+
+#endif				/* _M54418TWR_H */
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
new file mode 100644
index 0000000..2bd0e62
--- /dev/null
+++ b/include/configs/M54451EVB.h
@@ -0,0 +1,260 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Freescale MCF54451 EVB board.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M54451EVB_H
+#define _M54451EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_M54451EVB	/* M54451EVB board */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#define LDS_BOARD_TEXT                  board/freescale/m54451evb/sbf_dram_init.o (.text*)
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP 50000
+
+#	define CONFIG_ETHPRIME		"FEC0"
+#	define CONFIG_IPADDR		192.162.1.2
+#	define CONFIG_NETMASK		255.255.255.0
+#	define CONFIG_SERVERIP		192.162.1.1
+#	define CONFIG_GATEWAYIP		192.162.1.1
+
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME		"M54451EVB"
+#ifdef CONFIG_SYS_STMICRO_BOOT
+/* ST Micro serial flash */
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"sbfhdr=sbfhdr.bin\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${sbfhdr};"	\
+	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
+	"upd=run load; run prog\0"		\
+	"prog=sf probe 0:1 1000000 3;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
+	"save\0"				\
+	""
+#else
+#define CONFIG_SYS_UBOOT_END	0x3FFFF
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END)	\
+	"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+#endif
+
+/* Realtime clock */
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM			2048	/* 2048 KB */
+
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_MBAR			0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x33633F30
+#define CONFIG_SYS_SDRAM_CFG2		0x57670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE20D2C00
+#define CONFIG_SYS_SDRAM_EMOD		0x80810000
+#define CONFIG_SYS_SDRAM_MODE		0x008D0000
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x44
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_SERIAL_BOOT
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is not embedded in u-boot. First time runing may have env
+ * crc error warning if there is no correct environment on the flash.
+ */
+#if defined(CONFIG_SYS_STMICRO_BOOT)
+#	define CONFIG_ENV_OFFSET		0x20000
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x10000
+#else
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+#undef CONFIG_ENV_OVERWRITE
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
+
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#	define CONFIG_JFFS2_DEV		"nor0"
+#	define CONFIG_JFFS2_PART_SIZE	0x01000000
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
+#endif
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE		16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 16MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+ /* Flash */
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00004D80
+
+#define CONFIG_SYS_SPANSION_BASE	CONFIG_SYS_CS0_BASE
+
+#endif				/* _M54451EVB_H */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
new file mode 100644
index 0000000..d73101f
--- /dev/null
+++ b/include/configs/M54455EVB.h
@@ -0,0 +1,376 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Freescale MCF54455 EVB board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M54455EVB_H
+#define _M54455EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_M54455EVB	/* M54455EVB board */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#define LDS_BOARD_TEXT                  board/freescale/m54455evb/sbf_dram_init.o (.text*)
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC1_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP 50000
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_ETHPRIME		"FEC0"
+#	define CONFIG_IPADDR		192.162.1.2
+#	define CONFIG_NETMASK		255.255.255.0
+#	define CONFIG_SERVERIP		192.162.1.1
+#	define CONFIG_GATEWAYIP		192.162.1.1
+
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME		"M54455EVB"
+#ifdef CONFIG_SYS_STMICRO_BOOT
+/* ST Micro serial flash */
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010013
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"sbfhdr=sbfhdr.bin\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${sbfhdr};"	\
+	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
+	"upd=run load; run prog\0"		\
+	"prog=sf probe 0:1 1000000 3;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 0x30000;"	\
+	"save\0"				\
+	""
+#else
+/* Atmel and Intel */
+#ifdef CONFIG_SYS_ATMEL_BOOT
+#	define CONFIG_SYS_UBOOT_END	0x0403FFFF
+#elif defined(CONFIG_SYS_INTEL_BOOT)
+#	define CONFIG_SYS_UBOOT_END	0x3FFFF
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${uboot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
+	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
+	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
+	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" ${filesize}; save\0"			\
+	""
+#endif
+
+/* ATA configuration */
+#define CONFIG_IDE_RESET	1
+#define CONFIG_IDE_PREINIT	1
+#define CONFIG_ATAPI
+#undef CONFIG_LBA48
+
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0x90000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O                            */
+#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers           */
+#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers                 */
+
+/* Realtime clock */
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_DSPI
+#define CONFIG_SYS_SBFHDR_SIZE		0x13
+
+/* PCI */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	4
+
+#define CONFIG_SYS_PCI_MEM_BUS		0xA0000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_SYS_PCI_IO_BUS		0xB1000000
+#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000
+
+#define CONFIG_SYS_PCI_CFG_BUS		0xB0000000
+#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
+#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
+#endif
+
+/* FPGA - Spartan 2 */
+/* experiment
+#define CONFIG_FPGA_COUNT	1
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
+*/
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM		2048	/* 2048 KB */
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_BASE1		0x48000000
+#define CONFIG_SYS_SDRAM_SIZE		256	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x65311610
+#define CONFIG_SYS_SDRAM_CFG2		0x59670000
+#define CONFIG_SYS_SDRAM_CTRL		0xEA0B2000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x00010033
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0xAA
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_SERIAL_BOOT
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*
+ * Configuration for environment
+ * Environment is not embedded in u-boot. First time runing may have env
+ * crc error warning if there is no correct environment on the flash.
+ */
+#undef CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_STMICRO_BOOT
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS1_BASE
+#	define CONFIG_ENV_OFFSET		0x30000
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#ifdef CONFIG_SYS_ATMEL_BOOT
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#ifdef CONFIG_SYS_INTEL_BOOT
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
+#	define CONFIG_FLASH_CFI_LEGACY
+
+#ifdef CONFIG_FLASH_CFI_LEGACY
+#	define CONFIG_SYS_ATMEL_REGION		4
+#	define CONFIG_SYS_ATMEL_TOTALSECT	11
+#	define CONFIG_SYS_ATMEL_SECT		{1, 2, 1, 7}
+#	define CONFIG_SYS_ATMEL_SECTSZ		{0x4000, 0x2000, 0x8000, 0x10000}
+#endif
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#ifdef CF_STMICRO_BOOT
+#	define CONFIG_JFFS2_DEV		"nor1"
+#	define CONFIG_JFFS2_PART_SIZE	0x01000000
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH2_BASE + 0x500000)
+#endif
+#ifdef CONFIG_SYS_ATMEL_BOOT
+#	define CONFIG_JFFS2_DEV		"nor1"
+#	define CONFIG_JFFS2_PART_SIZE	0x01000000
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH1_BASE + 0x500000)
+#endif
+#ifdef CONFIG_SYS_INTEL_BOOT
+#	define CONFIG_JFFS2_DEV		"nor0"
+#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x500000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
+#endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE		16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - CPLD
+ * CS3 - FPGA
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
+ /* Atmel Flash */
+#define CONFIG_SYS_CS0_BASE		0x04000000
+#define CONFIG_SYS_CS0_MASK		0x00070001
+#define CONFIG_SYS_CS0_CTRL		0x00001140
+/* Intel Flash */
+#define CONFIG_SYS_CS1_BASE		0x00000000
+#define CONFIG_SYS_CS1_MASK		0x01FF0001
+#define CONFIG_SYS_CS1_CTRL		0x00000D60
+
+#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS0_BASE
+#else
+/* Intel Flash */
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x01FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00000D60
+ /* Atmel Flash */
+#define CONFIG_SYS_CS1_BASE		0x04000000
+#define CONFIG_SYS_CS1_MASK		0x00070001
+#define CONFIG_SYS_CS1_CTRL		0x00001140
+
+#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS1_BASE
+#endif
+
+/* CPLD */
+#define CONFIG_SYS_CS2_BASE		0x08000000
+#define CONFIG_SYS_CS2_MASK		0x00070001
+#define CONFIG_SYS_CS2_CTRL		0x003f1140
+
+/* FPGA */
+#define CONFIG_SYS_CS3_BASE		0x09000000
+#define CONFIG_SYS_CS3_MASK		0x00070001
+#define CONFIG_SYS_CS3_CTRL		0x00000020
+
+#endif				/* _M54455EVB_H */
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
new file mode 100644
index 0000000..7cc09ab
--- /dev/null
+++ b/include/configs/M5475EVB.h
@@ -0,0 +1,256 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Freescale MCF5475 board.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5475EVB_H
+#define _M5475EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef CONFIG_HW_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+#define CONFIG_SLTTMR
+
+#define CONFIG_FSLDMAFEC
+#ifdef CONFIG_FSLDMAFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_SYS_DMA_USE_INTSRAM	1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	32
+#	define CONFIG_SYS_TX_ETH_BUFFER	48
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_PINMUX		0
+#	define CONFIG_SYS_FEC1_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+
+#endif
+
+#ifdef CONFIG_CMD_USB
+#	define CONFIG_USB_OHCI_NEW
+
+#	define CONFIG_PCI_OHCI
+
+#	undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#	undef CONFIG_SYS_USB_OHCI_CPU_INIT
+#	define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#	define CONFIG_SYS_USB_OHCI_SLOT_NAME		"isp1561"
+#	define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00008F00
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+/* PCI */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	8
+
+#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_SYS_PCI_IO_BUS		0x71000000
+#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000
+
+#define CONFIG_SYS_PCI_CFG_BUS		0x70000000
+#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
+#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
+#endif
+
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		"M547xEVB"
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off bank 1;"			\
+	"era ff800000 ff83ffff;"		\
+	"cp.b ${loadaddr} ff800000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+
+#define CONFIG_SYS_LOAD_ADDR		0x00010000
+
+#define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
+
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_INTSRAM		(CONFIG_SYS_MBAR + 0x10000)
+#define CONFIG_SYS_INTSRAMSZ		0x8000
+
+/*#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM1_CTRL	0x21
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_CFG1		0x73711630
+#define CONFIG_SYS_SDRAM_CFG2		0x46770000
+#define CONFIG_SYS_SDRAM_CTRL		0xE10B0000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+#define CONFIG_SYS_SDRAM_DRVSTRENGTH	0x000002AA
+#ifdef CONFIG_SYS_DRAMSZ1
+#	define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
+#else
+#	define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_DRAMSZ
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#ifdef CONFIG_SYS_NOR1SZ
+#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
+#else
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		(CONFIG_SYS_BOOTSZ << 20)
+#endif
+#endif
+
+/* Configuration for environment
+ * Environment is not embedded in u-boot but at offset 0x40000 on the flash.
+ * First time runing may have env crc error warning if there is
+ * no correct environment on the flash.
+ */
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
+					 CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
+					 CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - NOR Flash
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		(((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS0_CTRL		0x00101980
+
+#ifdef CONFIG_SYS_NOR1SZ
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		(((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS1_CTRL		0x00101D80
+#endif
+
+#endif				/* _M5475EVB_H */
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
new file mode 100644
index 0000000..3f5ced2
--- /dev/null
+++ b/include/configs/M5485EVB.h
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Freescale MCF5485 FireEngine board.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5485EVB_H
+#define _M5485EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef CONFIG_HW_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+#define CONFIG_SLTTMR
+
+#define CONFIG_FSLDMAFEC
+#ifdef CONFIG_FSLDMAFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_SYS_DMA_USE_INTSRAM	1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	32
+#	define CONFIG_SYS_TX_ETH_BUFFER	48
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_PINMUX		0
+#	define CONFIG_SYS_FEC1_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+
+#endif
+
+#ifdef CONFIG_CMD_USB
+#	define CONFIG_USB_OHCI_NEW
+/*#	define CONFIG_PCI_OHCI*/
+#	define CONFIG_SYS_USB_OHCI_REGS_BASE		0x80041000
+#	define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#	define CONFIG_SYS_USB_OHCI_SLOT_NAME		"isp1561"
+#	define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00008F00
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+/* PCI */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_SYS_PCI_IO_BUS		0x71000000
+#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000
+
+#define CONFIG_SYS_PCI_CFG_BUS		0x70000000
+#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
+#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
+#endif
+
+#define CONFIG_UDP_CHECKSUM
+
+#define CONFIG_HOSTNAME		"M548xEVB"
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off bank 1;"			\
+	"era ff800000 ff83ffff;"		\
+	"cp.b ${loadaddr} ff800000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+
+#define CONFIG_SYS_LOAD_ADDR		0x00010000
+
+#define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
+
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_INTSRAM		(CONFIG_SYS_MBAR + 0x10000)
+#define CONFIG_SYS_INTSRAMSZ		0x8000
+
+/*#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM1_CTRL	0x21
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_CFG1		0x73711630
+#define CONFIG_SYS_SDRAM_CFG2		0x46770000
+#define CONFIG_SYS_SDRAM_CTRL		0xE10B0000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+#define CONFIG_SYS_SDRAM_DRVSTRENGTH	0x000002AA
+#ifdef CONFIG_SYS_DRAMSZ1
+#	define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
+#else
+#	define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_DRAMSZ
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#ifdef CONFIG_SYS_NOR1SZ
+#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
+#else
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		(CONFIG_SYS_BOOTSZ << 20)
+#endif
+#endif
+
+/* Configuration for environment
+ * Environment is not embedded in u-boot. First time runing may have env
+ * crc error warning if there is no correct environment on the flash.
+ */
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
+					 CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
+					 CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - NOR Flash
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		(((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS0_CTRL		0x00101980
+
+#ifdef CONFIG_SYS_NOR1SZ
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		(((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS1_CTRL		0x00101D80
+#endif
+
+#endif				/* _M5485EVB_H */
diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h
new file mode 100644
index 0000000..3c46ae0
--- /dev/null
+++ b/include/configs/MCR3000.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"sdram_type=SDRAM\0"						\
+	"flash_type=AM29LV160DB\0"					\
+	"loadaddr=0x400000\0"						\
+	"filename=uImage.lzma\0"					\
+	"nfsroot=/opt/ofs\0"						\
+	"dhcp_ip=ip=:::::eth0:dhcp\0"					\
+	"console_args=console=ttyCPM0,115200N8\0"			\
+	"flashboot=setenv bootargs "					\
+		"${console_args} "					\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:"	\
+		"mcr3k:eth0:off;"					\
+		"${ofl_args}; "						\
+		"bootm 0x04060000 - 0x04050000\0"			\
+	"tftpboot=setenv bootargs "					\
+		"${console_args} "					\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:"	\
+		"mcr3k:eth0:off "					\
+		"${ofl_args}; "						\
+		"tftp ${loadaddr} ${filename};"				\
+		"tftp 0xf00000 mcr3000.dtb;"				\
+		"bootm ${loadaddr} - 0xf00000\0"			\
+	"netboot=dhcp ${loadaddr} ${filename};"				\
+		"tftp 0xf00000 mcr3000.dtb;"				\
+		"setenv bootargs "					\
+		"root=/dev/nfs rw "					\
+		"${console_args} "					\
+		"${dhcp_ip};"						\
+		"bootm ${loadaddr} - 0xf00000\0"			\
+	"nfsboot=setenv bootargs "					\
+		"root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} "	\
+		"${console_args} "					\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:"	\
+		"mcr3k:eth0:off;"					\
+		"bootm 0x04060000 - 0x04050000\0"			\
+	"dhcpboot=dhcp ${loadaddr} ${filename};"			\
+		"tftp 0xf00000 mcr3000.dtb;"				\
+		"setenv bootargs "					\
+		"${console_args} "					\
+		"${dhcp_ip} "						\
+		"${ofl_args}; "						\
+		"bootm ${loadaddr} - 0xf00000\0"
+
+#define CONFIG_IPADDR			192.168.0.3
+#define CONFIG_SERVERIP			192.168.0.1
+#define CONFIG_NETMASK			255.0.0.0
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START	0x00002000
+#define CONFIG_SYS_MEMTEST_END		0x00800000
+
+#define	CONFIG_SYS_LOAD_ADDR		0x200000
+
+#define	CONFIG_SYS_HZ			1000
+
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x2800)
+#define	CONFIG_SYS_INIT_RAM_SIZE	(0x2e00 - 0x2800)
+
+/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	35
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+#define	CONFIG_SYS_MONITOR_LEN		(320 << 10)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)
+
+/* Environment Configuration */
+
+/* environment is in FLASH */
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_OVERWRITE	1
+
+/* Ethernet configuration part */
+#define CONFIG_SYS_DISCOVER_PHY		1
+#define CONFIG_MII_INIT			1
+
+/* NAND configuration part */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_SYS_NAND_BASE		0x0C000000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
new file mode 100644
index 0000000..85d7ff6
--- /dev/null
+++ b/include/configs/MPC8308RDB.h
@@ -0,0 +1,341 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO
+#endif
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is SoC TSEC
+ * TSEC2 is VSC switch
+ */
+#define CONFIG_TSEC1
+#define CONFIG_VSC7385_ENET
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ONLY_CURRENT \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03600100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32)
+				/* 0x43080000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is 8M */
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+/* 127 64KB sectors and 8 8KB top sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CONFIG_SYS_NAND_BASE	0xE0600000		/* 0xE0600000 */
+#define CONFIG_SYS_NAND_WINDOW_SIZE	(32 * 1024)	/* 0x00008000 */
+				/* 0xFFFF8396 */
+
+#ifdef CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+					/* VSC7385 Base address on CS2 */
+#define CONFIG_SYS_VSC7385_BASE		0xF0000000
+#define CONFIG_SYS_VSC7385_SIZE		(128 * 1024) /* 0x00020000 */
+					/* 0xFFFE09FF */
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+#endif
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * SPI on header J8
+ *
+ * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
+ * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+#define CONFIG_USE_SPIFLASH
+#endif
+
+/*
+ * Board info - revision and where boot from
+ */
+#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+/* enable PCIE clock */
+#define CONFIG_SYS_SCCR_PCIEXP1CM	1
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${consoledev},${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"kernel_addr=FE080000\0"					\
+	"fdt_addr=FE280000\0"						\
+	"ramdisk_addr=FE290000\0"					\
+	"u-boot=mpc8308rdb/u-boot.bin\0"				\
+	"kernel_addr_r=1000000\0"					\
+	"fdt_addr_r=C00000\0"						\
+	"hostname=mpc8308rdb\0"						\
+	"bootfile=mpc8308rdb/uImage\0"					\
+	"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"				\
+	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"bootcmd=run flash_self\0"					\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+		" +${filesize};cp.b ${fileaddr} "			\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
+	"upd=run load update\0"						\
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
new file mode 100644
index 0000000..4153d60
--- /dev/null
+++ b/include/configs/MPC8313ERDB_NAND.h
@@ -0,0 +1,404 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1
+
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SPL_MAX_SIZE	(4 * 1024)
+#define CONFIG_SPL_PAD_TO	0x4000
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_ELBC 1
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is VSC switch
+ * TSEC2 is SoC TSEC
+ */
+#define CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00001000
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
+
+/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC1
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE	128		/* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ONLY_CURRENT \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (10 << TIMING_CFG1_REFREC_SHIFT) \
+				| (3 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x3835a322 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (5 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x129048c6 */ /* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_INTERVAL	((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x05100500 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32 \
+				| SDRAM_CFG_2T_EN)
+				/* 0x43088000 */
+#else
+#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32)
+				/* 0x43080000 */
+#endif
+#define CONFIG_SYS_SDRAM_CFG2		0x00401000
+/* set burst length to 8 for 32-bit data path */
+#define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0632 << SDRAM_MODE_SD_SHIFT))
+				/* 0x44480632 */
+#define CONFIG_SYS_DDR_MODE_2	0x8000C000
+
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/*0x02000000*/
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_NOMZ \
+				| DDRCDR_NZ_NOMZ \
+				| DDRCDR_M_ODR)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8	/* flash size in MB */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
+	!defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
+
+/* drivers/mtd/nand/raw/nand.c */
+#if defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE		0xE2800000
+#endif
+
+#define CONFIG_MTD_PARTITION
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
+
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
+
+/* local bus write LED / read status buffer (BCSR) mapping */
+#define CONFIG_SYS_BCSR_ADDR		0xFA000000
+#define CONFIG_SYS_BCSR_SIZE		(32 * 1024)	/* 0x00008000 */
+					/* map at 0xFA000000 on LCS3 */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+					/* VSC7385 Base address on LCS2 */
+#define CONFIG_SYS_VSC7385_BASE		0xF0000000
+#define CONFIG_SYS_VSC7385_SIZE		(128 * 1024)	/* 0x00020000 */
+
+
+#endif
+
+#define CONFIG_MPC83XX_GPIO 1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+
+/*
+ * TSEC
+ */
+
+#define CONFIG_GMII			/* MII PHY management */
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x1c
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC1_PHYIDX		0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define TSEC2_PHY_ADDR		4
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC2_PHYIDX		0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OFFSET		(512 * 1024)
+#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
+
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
+			/* Enable Internal USB Phy and GPIO on LCD Connector */
+#define CONFIG_SYS_SICRL	(SICRL_USBDR_10 | SICRL_LBC)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV		"eth1"
+
+#define CONFIG_HOSTNAME		"mpc8313erdb"
+#define CONFIG_ROOTPATH		"/nfs/root/path"
+#define CONFIG_BOOTFILE		"uImage"
+				/* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+#define CONFIG_FDTFILE		"mpc8313erdb.dtb"
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" CONFIG_NETDEV "\0"					\
+	"ethprime=TSEC1\0"						\
+	"uboot=" CONFIG_UBOOTPATH "\0"					\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"fdtaddr=780000\0"						\
+	"fdtfile=" CONFIG_FDTFILE "\0"					\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+							"$netdev:off " \
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"						\
+	"run setipargs;"						\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
new file mode 100644
index 0000000..ff8dedf
--- /dev/null
+++ b/include/configs/MPC8313ERDB_NOR.h
@@ -0,0 +1,377 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_ELBC 1
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is VSC switch
+ * TSEC2 is SoC TSEC
+ */
+#define CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+
+#define CONFIG_SYS_MEMTEST_START	0x00001000
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
+
+/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC1
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE	128		/* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ONLY_CURRENT \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (10 << TIMING_CFG1_REFREC_SHIFT) \
+				| (3 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x3835a322 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (5 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x129048c6 */ /* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_INTERVAL	((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x05100500 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32 \
+				| SDRAM_CFG_2T_EN)
+				/* 0x43088000 */
+#else
+#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32)
+				/* 0x43080000 */
+#endif
+#define CONFIG_SYS_SDRAM_CFG2		0x00401000
+/* set burst length to 8 for 32-bit data path */
+#define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0632 << SDRAM_MODE_SD_SHIFT))
+				/* 0x44480632 */
+#define CONFIG_SYS_DDR_MODE_2	0x8000C000
+
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/*0x02000000*/
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_NOMZ \
+				| DDRCDR_NZ_NOMZ \
+				| DDRCDR_M_ODR)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8	/* flash size in MB */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
+	!defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
+
+/* drivers/mtd/nand/nand.c */
+#define CONFIG_SYS_NAND_BASE		0xE2800000
+
+#define CONFIG_MTD_PARTITION
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
+
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+
+/* local bus write LED / read status buffer (BCSR) mapping */
+#define CONFIG_SYS_BCSR_ADDR		0xFA000000
+#define CONFIG_SYS_BCSR_SIZE		(32 * 1024)	/* 0x00008000 */
+					/* map at 0xFA000000 on LCS3 */
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+					/* VSC7385 Base address on LCS2 */
+#define CONFIG_SYS_VSC7385_BASE		0xF0000000
+#define CONFIG_SYS_VSC7385_SIZE		(128 * 1024)	/* 0x00020000 */
+
+
+#endif
+
+#define CONFIG_MPC83XX_GPIO 1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+
+/*
+ * TSEC
+ */
+
+#define CONFIG_GMII			/* MII PHY management */
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x1c
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC1_PHYIDX		0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define TSEC2_PHY_ADDR		4
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC2_PHYIDX		0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * Environment
+ */
+#if !defined(CONFIG_SYS_RAMBOOT)
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector */
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
+
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
+			/* Enable Internal USB Phy and GPIO on LCD Connector */
+#define CONFIG_SYS_SICRL	(SICRL_USBDR_10 | SICRL_LBC)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV		"eth1"
+
+#define CONFIG_HOSTNAME		"mpc8313erdb"
+#define CONFIG_ROOTPATH		"/nfs/root/path"
+#define CONFIG_BOOTFILE		"uImage"
+				/* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+#define CONFIG_FDTFILE		"mpc8313erdb.dtb"
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" CONFIG_NETDEV "\0"					\
+	"ethprime=TSEC1\0"						\
+	"uboot=" CONFIG_UBOOTPATH "\0"					\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"fdtaddr=780000\0"						\
+	"fdtfile=" CONFIG_FDTFILE "\0"					\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+							"$netdev:off " \
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"						\
+	"run setipargs;"						\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
new file mode 100644
index 0000000..521c5ca
--- /dev/null
+++ b/include/configs/MPC8315ERDB.h
@@ -0,0 +1,390 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH		0x00000000
+#define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */
+
+#define CONFIG_HWCONFIG
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ONLY_CURRENT \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03600100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32)
+				/* 0x43080000 */
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2	0x00000000
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00140000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_FSL_ELBC
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8	/* FLASH size is 8M */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+/* 127 64KB sectors and 8 8KB top sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE		0xE0600000
+#endif
+
+#define CONFIG_MTD_PARTITION
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_FSL_ELBC		1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+
+
+
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
+	!defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * Board info - revision and where boot from
+ */
+#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE
+
+#define CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_SCCR_USBDRCM		3
+
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_PHY_TYPE	"utmi"
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+/*
+ * TSEC
+ */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+/*
+ * SATA
+ */
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1_OFFSET	0x18000
+#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2_OFFSET	0x19000
+#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#endif
+
+/*
+ * Environment
+ */
+#if !defined(CONFIG_SYS_RAMBOOT)
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+/*
+ * MMU Setup
+ */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=ramfs.83xx\0"					\
+	"fdtaddr=780000\0"						\
+	"fdtfile=mpc8315erdb.dtb\0"					\
+	"usb_phy_type=utmi\0"						\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
new file mode 100644
index 0000000..94c2a61
--- /dev/null
+++ b/include/configs/MPC8323ERDB.h
@@ -0,0 +1,324 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 family */
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRL		0x00000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory */
+
+#undef CONFIG_SPD_EEPROM
+#if defined(CONFIG_SPD_EEPROM)
+/* Determine DDR configuration from I2C interface
+ */
+#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
+#else
+/* Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE	64	/* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_9)
+				/* 0x80010101 */
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (3 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x26253222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (31 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x1f9048c7 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/* 0x02000000 */
+#define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* 0x44480232 */
+#define CONFIG_SYS_DDR_MODE2	0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL	((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03200064 */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000003
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_32_BE)
+				/* 0x43080000 */
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00030000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x03f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size is 16M */
+
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * Config on-board EEPROM
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0xd0000000
+#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE		0x04000000	/* 64M */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_SKIP_HOST_BRIDGE
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"UEC0"
+
+#define CONFIG_UEC_ETH1		/* ETH3 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	4
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+#endif
+
+#define CONFIG_UEC_ETH2		/* ETH4 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK16
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK3
+#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	0
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x20000
+	#define CONFIG_ENV_SIZE		0x2000
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+					/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if (CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HAS_ETH0		/* add support for "ethaddr" */
+#define CONFIG_HAS_ETH1		/* add support for "eth1addr" */
+
+/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
+ * (see CONFIG_SYS_I2C_EEPROM) */
+					/* MAC address offset in I2C EEPROM */
+#define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00
+
+#define CONFIG_NETDEV		"eth1"
+
+#define CONFIG_HOSTNAME		"mpc8323erdb"
+#define CONFIG_ROOTPATH		"/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+				/* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+#define CONFIG_FDTFILE		"mpc832x_rdb.dtb"
+#define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" CONFIG_NETDEV "\0"					\
+	"uboot=" CONFIG_UBOOTPATH "\0"					\
+	"tftpflash=tftp $loadaddr $uboot;"				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"fdtaddr=780000\0"						\
+	"fdtfile=" CONFIG_FDTFILE "\0"					\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+								"$netdev:off "\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"						\
+	"run setipargs;"						\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
new file mode 100644
index 0000000..26a4407
--- /dev/null
+++ b/include/configs/MPC832XEMDS.h
@@ -0,0 +1,322 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 family */
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRL		0x00000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory */
+#define CONFIG_SYS_DDRCDR	0x73000002	/* DDR II voltage is 1.8V */
+
+#undef CONFIG_SPD_EEPROM
+#if defined(CONFIG_SPD_EEPROM)
+/* Determine DDR configuration from I2C interface
+ */
+#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
+#else
+/* Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE		128	/* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_AP \
+					| CSCONFIG_ODT_WR_CFG \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10)
+					/* 0x80840102 */
+#define CONFIG_SYS_DDR_TIMING_0		((0 << TIMING_CFG0_RWT_SHIFT) \
+					| (0 << TIMING_CFG0_WRT_SHIFT) \
+					| (0 << TIMING_CFG0_RRT_SHIFT) \
+					| (0 << TIMING_CFG0_WWT_SHIFT) \
+					| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+					| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+					| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+					| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+					/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1		((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+					| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+					| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+					| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+					| (13 << TIMING_CFG1_REFREC_SHIFT) \
+					| (3 << TIMING_CFG1_WRREC_SHIFT) \
+					| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+					| (2 << TIMING_CFG1_WRTORD_SHIFT))
+					/* 0x3935D322 */
+#define CONFIG_SYS_DDR_TIMING_2		((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (31 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x0F9048CA */
+#define CONFIG_SYS_DDR_TIMING_3		0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL		DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+					/* 0x02000000 */
+#define CONFIG_SYS_DDR_MODE		((0x4440 << SDRAM_MODE_ESD_SHIFT) \
+					| (0x0232 << SDRAM_MODE_SD_SHIFT))
+					/* 0x44400232 */
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL		((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
+					| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+					/* 0x03200064 */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x00000007
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+					| SDRAM_CFG_32_BE)
+					/* 0x43080000 */
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE	16	/* FLASH size is 16M */
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * BCSR on the Local Bus
+ */
+#define CONFIG_SYS_BCSR			0xF8000000
+					/* Access window base at BCSR base */
+
+
+/*
+ * Windows to access PIB via local bus
+ */
+					/* PIB window base 0xF8008000 */
+#define CONFIG_SYS_PIB_BASE		0xF8008000
+#define CONFIG_SYS_PIB_WINDOW_SIZE	(32 * 1024)
+
+/*
+ * CS2 on Local Bus, to PIB
+ */
+
+
+/*
+ * CS3 on Local Bus, to PIB
+ */
+
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x100000	/* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_83XX_PCI_STREAMING
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"UEC0"
+
+#define CONFIG_UEC_ETH1		/* ETH3 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	3
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+#endif
+
+#define CONFIG_UEC_ETH2		/* ETH4 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM	3	/* UCC4 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK7
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK8
+#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	4
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x20000
+	#define CONFIG_ENV_SIZE		0x2000
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+					/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */ #define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=ramfs.83xx\0"					\
+	"fdtaddr=780000\0"						\
+	"fdtfile=mpc832x_mds.dtb\0"					\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
new file mode 100644
index 0000000..7352e34
--- /dev/null
+++ b/include/configs/MPC8349EMDS.h
@@ -0,0 +1,394 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * mpc8349emds board configuration file
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC			/* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+
+/*
+ * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
+ * unselect it to use old spd_sdram.c
+ */
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x52
+#define SPD_EEPROM_ADDRESS2	0x51
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
+					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#undef  CONFIG_DDR_2T_TIMING
+
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CONFIG_SYS_DDRCDR_VALUE	0x80080001
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#else
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#if defined(CONFIG_DDR_II)
+#define CONFIG_SYS_DDRCDR		0x80080001
+#define CONFIG_SYS_DDR_CS2_BNDS		0x0000000f
+#define CONFIG_SYS_DDR_CS2_CONFIG	0x80330102
+#define CONFIG_SYS_DDR_TIMING_0		0x00220802
+#define CONFIG_SYS_DDR_TIMING_1		0x38357322
+#define CONFIG_SYS_DDR_TIMING_2		0x2f9048c8
+#define CONFIG_SYS_DDR_TIMING_3		0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL		0x02000000
+#define CONFIG_SYS_DDR_MODE		0x47d00432
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL		0x03cf0080
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#else
+#define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_TIMING_1	0x36332321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+				/* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE	0x00000023
+#else
+/* the default burst length is 4 - for 64-bit data path */
+				/* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE	0x00000022
+#endif
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		32	/* max flash size in MB */
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+/*
+ * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
+ */
+#define CONFIG_SYS_BCSR			0xE2400000
+					/* Access window base at BCSR base */
+
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* SPI */
+#undef CONFIG_SOFT_SPI			/* SPI bit-banged */
+
+/* GPIOs.  Used as SPI chip selects */
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR		0xC0000000  /* SPI CS on 0, LED on 1 */
+#define CONFIG_SYS_GPIO1_DAT		0xC0000000  /* Both are active LOW */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/* USB */
+#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_83XX_PCI_STREAMING
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_GMII		1	/* MII PHY management */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+/*
+ * System performance
+ */
+#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_HOSTNAME		"mpc8349emds"
+#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=mpc8349emds\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"		\
+	"update=protect off fe000000 fe03ffff; "			\
+		"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
+	"upd=run load update\0"						\
+	"fdtaddr=780000\0"						\
+	"fdtfile=mpc834x_mds.dtb\0"					\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
new file mode 100644
index 0000000..2ae1069
--- /dev/null
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -0,0 +1,451 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * mpc8349emds board configuration file
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC			/* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+
+/*
+ * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
+ * unselect it to use old spd_sdram.c
+ */
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x52
+#define SPD_EEPROM_ADDRESS2	0x51
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
+					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#undef  CONFIG_DDR_2T_TIMING
+
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CONFIG_SYS_DDRCDR_VALUE	0x80080001
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#else
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#if defined(CONFIG_DDR_II)
+#define CONFIG_SYS_DDRCDR		0x80080001
+#define CONFIG_SYS_DDR_CS2_BNDS		0x0000000f
+#define CONFIG_SYS_DDR_CS2_CONFIG	0x80330102
+#define CONFIG_SYS_DDR_TIMING_0		0x00220802
+#define CONFIG_SYS_DDR_TIMING_1		0x38357322
+#define CONFIG_SYS_DDR_TIMING_2		0x2f9048c8
+#define CONFIG_SYS_DDR_TIMING_3		0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL		0x02000000
+#define CONFIG_SYS_DDR_MODE		0x47d00432
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL		0x03cf0080
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#else
+#define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_TIMING_1	0x36332321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+				/* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE	0x00000023
+#else
+/* the default burst length is 4 - for 64-bit data path */
+				/* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE	0x00000022
+#endif
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		32	/* max flash size in MB */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+/*
+ * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
+ */
+#define CONFIG_SYS_BCSR			0xE2400000
+					/* Access window base at BCSR base */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
+
+/*
+ * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
+ */
+
+/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
+ */
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *                 XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
+ */
+
+
+				/* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT	0x32000000
+				/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN	\
+				| LSDMR_BSMA1516	\
+				| LSDMR_RFCR8		\
+				| LSDMR_PRETOACT6	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC3		\
+				| LSDMR_CL3)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* SPI */
+#undef CONFIG_SOFT_SPI			/* SPI bit-banged */
+
+/* GPIOs.  Used as SPI chip selects */
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR		0xC0000000  /* SPI CS on 0, LED on 1 */
+#define CONFIG_SYS_GPIO1_DAT		0xC0000000  /* Both are active LOW */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/* USB */
+#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_83XX_PCI_STREAMING
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_GMII		1	/* MII PHY management */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+/*
+ * System performance
+ */
+#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
+#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_HOSTNAME		"mpc8349emds"
+#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=mpc8349emds\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"		\
+	"update=protect off fe000000 fe03ffff; "			\
+		"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
+	"upd=run load update\0"						\
+	"fdtaddr=780000\0"						\
+	"fdtfile=mpc834x_mds.dtb\0"					\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
new file mode 100644
index 0000000..c395d62
--- /dev/null
+++ b/include/configs/MPC8349ITX.h
@@ -0,0 +1,454 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ */
+
+/*
+ MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
+
+ Memory map:
+
+ 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
+ 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
+ 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
+ 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
+ 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
+ 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
+ 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
+ 0xF001_0000-0xF001_FFFF Local bus expansion slot
+ 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
+ 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
+ 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
+
+ I2C address list:
+						Align.	Board
+ Bus	Addr	Part No.	Description	Length	Location
+ ----------------------------------------------------------------
+ I2C0	0x50	M24256-BWMN6P	Board EEPROM	2	U64
+
+ I2C1	0x20	PCF8574		I2C Expander	0	U8
+ I2C1	0x21	PCF8574		I2C Expander	0	U10
+ I2C1	0x38	PCF8574A	I2C Expander	0	U8
+ I2C1	0x39	PCF8574A	I2C Expander	0	U10
+ I2C1	0x51	(DDR)		DDR EEPROM	1	U1
+ I2C1	0x68	DS1339		RTC		1	U68
+
+ Note that a given board has *either* a pair of 8574s or a pair of 8574As.
+*/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MISC_INIT_F
+
+/*
+ * On-board devices
+ */
+
+#ifdef CONFIG_TARGET_MPC8349ITX
+/* The CF card interface on the back of the board */
+#define CONFIG_COMPACT_FLASH
+#define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
+#define CONFIG_SYS_USB_HOST	/* use the EHCI USB controller */
+#endif
+
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C
+
+/*
+ * Device configurations
+ */
+
+/* I2C */
+#ifdef CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+#define CONFIG_SYS_SPD_BUS_NUM		1	/* The I2C bus for SPD */
+#define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC */
+
+#define CONFIG_SYS_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
+#define CONFIG_SYS_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
+#define CONFIG_SYS_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
+#define CONFIG_SYS_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* I2C1, DS1339 RTC*/
+#define SPD_EEPROM_ADDRESS		0x51	/* I2C1, DDR */
+
+/* Don't probe these addresses: */
+#define CONFIG_SYS_I2C_NOPROBES	{ {1, CONFIG_SYS_I2C_8574_ADDR1}, \
+				 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
+				 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
+				 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
+/* Bit definitions for the 8574[A] I2C expander */
+				/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
+#define I2C_8574_REVISION	0x03
+#define I2C_8574_CF		0x08	/* 1=Compact flash absent, 0=present */
+#define I2C_8574_MPCICLKRN	0x10	/* MiniPCI Clk Run */
+#define I2C_8574_PCI66		0x20	/* 0=33MHz PCI, 1=66MHz PCI */
+#define I2C_8574_FLASHSIDE	0x40	/* 0=Reset vector from U4, 1=from U7*/
+
+#endif
+
+/* Compact Flash */
+#ifdef CONFIG_COMPACT_FLASH
+
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF_BASE
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
+#define CONFIG_SYS_ATA_STRIDE		2
+
+/* If a CF card is not inserted, time out quickly */
+#define ATA_RESET_TIME	1
+
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_SATA_SIL3114
+
+#define CONFIG_SYS_SATA_MAX_DEVICE      4
+#define CONFIG_LBA48
+
+#endif
+
+#ifdef CONFIG_SYS_USB_HOST
+/*
+ * Support USB
+ */
+#define CONFIG_USB_EHCI_FSL
+
+/* Current USB implementation supports the only USB controller,
+ * so we have to choose between the MPH or the DR ones */
+#if 1
+#define CONFIG_HAS_FSL_MPH_USB
+#else
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+#define CONFIG_SYS_MEMTEST_START	0x1000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x2000
+
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
+					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
+
+#ifdef CONFIG_SYS_I2C
+#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+#endif
+
+/* No SPD? Then manually set up DDR parameters */
+#ifndef CONFIG_SPD_EEPROM
+    #define CONFIG_SYS_DDR_SIZE		256	/* Mb */
+    #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10)
+
+    #define CONFIG_SYS_DDR_TIMING_1	0x26242321
+    #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
+#endif
+
+/*
+ *Flash on the Local Bus
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+/* 127 64KB sectors + 8 8KB sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+/* The ITX has two flash chips, but the ITX-GP has only one.  To support both
+boards, we say we have two, but don't display a message if we find only one. */
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	\
+		{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
+#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size in MB */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFEFFE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
+ * BRx, ORx, LBLAWBARx, and LBLAWARx
+ */
+
+
+/* Vitesse 7385 */
+
+#define CONFIG_SYS_VSC7385_BASE	0xF8000000
+
+#define CONFIG_SYS_LED_BASE	0xF9000000
+
+
+/* Compact Flash */
+
+#ifdef CONFIG_COMPACT_FLASH
+
+#define CONFIG_SYS_CF_BASE	0xF0000000
+
+
+#endif
+
+/*
+ * U-Boot memory configuration
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONSOLE			ttyS0
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/*
+ * PCI
+ */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_MPC83XX_PCI2
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	\
+			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x01000000	/* 16M */
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CONFIG_SYS_PCI2_MEM_BASE	\
+			(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	\
+			(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS		\
+			(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
+#define CONFIG_SYS_PCI2_IO_SIZE		0x01000000	/* 16M */
+#endif
+
+#ifndef CONFIG_PCI_PNP
+    #define PCI_ENET0_IOADDR	0x00000000
+    #define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI2_MEM_BASE
+    #define PCI_IDSEL_NUMBER	0x0f	/* IDSEL = AD15 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif
+
+/* TSEC */
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_TSEC1
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME  "TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
+#define TSEC1_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME  "TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+
+#define TSEC2_PHY_ADDR		4
+#define TSEC2_PHYIDX		0
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#endif
+
+#define CONFIG_ETHPRIME		"Freescale TSEC"
+
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef CONFIG_SYS_RAMBOOT
+  #define CONFIG_ENV_ADDR	\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+  #define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) for environment */
+  #define CONFIG_ENV_SIZE	0x2000
+#else
+  #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_SIZE	0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Watchdog */
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+/*
+ * System performance
+ */
+#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_USBMPHCM 3	/* USB MPH controller's clock */
+#define CONFIG_SYS_SCCR_USBDRCM	0	/* USB DR controller's clock */
+
+/*
+ * System IO Config
+ */
+/* Needed for gigabit to work on TSEC 1 */
+#define CONFIG_SYS_SICRH SICRH_TSOBI1
+				/* USB DR as device + USB MPH as host */
+#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1)
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV		"eth0"
+
+/* Default path and filenames */
+#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
+#define CONFIG_BOOTFILE		"uImage"
+				/* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+
+#ifdef CONFIG_TARGET_MPC8349ITX
+#define CONFIG_FDTFILE		"mpc8349emitx.dtb"
+#else
+#define CONFIG_FDTFILE		"mpc8349emitxgp.dtb"
+#endif
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=" __stringify(CONSOLE) "\0"			\
+	"netdev=" CONFIG_NETDEV "\0"					\
+	"uboot=" CONFIG_UBOOTPATH "\0"					\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"fdtaddr=780000\0"						\
+	"fdtfile=" CONFIG_FDTFILE "\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"	\
+	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
+	" console=$console,$baudrate $othbootargs; "			\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw"				\
+	" console=$console,$baudrate $othbootargs; "			\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
new file mode 100644
index 0000000..724f8af
--- /dev/null
+++ b/include/configs/MPC837XEMDS.h
@@ -0,0 +1,390 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+
+/*
+ * IP blocks clock configuration
+ */
+#define CONFIG_SYS_SCCR_TSEC1CM	1	/* CSB:eTSEC1 = 1:1 */
+#define CONFIG_SYS_SCCR_TSEC2CM	1	/* CSB:eTSEC2 = 1:1 */
+#define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* CSB:SATA[0:3] = 2:1 */
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH		0x00000000
+#define CONFIG_SYS_SICRL		0x00000000
+
+/*
+ * Output Buffer Impedance
+ */
+#define CONFIG_SYS_OBIR		0x31100000
+
+#define CONFIG_HWCONFIG
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+#define CONFIG_SYS_DDRCDR_VALUE		(DDRCDR_DHC_EN \
+					| DDRCDR_ODT \
+					| DDRCDR_Q_DRN)
+					/* 0x80080001 */ /* ODT 150ohm on SoC */
+
+#undef CONFIG_DDR_ECC		/* support DDR ECC function */
+#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+
+#define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
+#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
+
+#if defined(CONFIG_SPD_EEPROM)
+#define SPD_EEPROM_ADDRESS	0x51 /* I2C address of DDR SODIMM SPD */
+#else
+/*
+ * Manually set up DDR parameters
+ * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
+ * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
+ */
+#define CONFIG_SYS_DDR_SIZE		512 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+			| CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
+			| CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
+			| CSCONFIG_ROW_BIT_14 \
+			| CSCONFIG_COL_BIT_10)
+			/* 0x80010202 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00620802 */
+#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (13 << TIMING_CFG1_REFREC_SHIFT) \
+				| (3 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x3935d322 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (6 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x131088c8 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03E00100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE	((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x1432 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2	0x00000000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00140000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_FSL_ELBC		1
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE	0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE	32 /* max FLASH size is 32M */
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+/*
+ * BCSR on the Local Bus
+ */
+#define CONFIG_SYS_BCSR		0xF8000000
+					/* Access window base at BCSR base */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_FSL_ELBC	1
+
+#define CONFIG_SYS_NAND_BASE	0xE0600000
+
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#ifndef __ASSEMBLY__
+extern int board_pci_host_broken(void);
+#endif
+#define CONFIG_PCIE
+#define CONFIG_PQ_MDS_PIB	1 /* PQ MDS Platform IO Board */
+
+#define CONFIG_HAS_FSL_DR_USB	1 /* fixup device tree for the DR USB */
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#endif /* CONFIG_PCI */
+
+/*
+ * TSEC
+ */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		3
+#define TSEC1_PHY_ADDR_SGMII	8
+#define TSEC2_PHY_ADDR_SGMII	4
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+#define CONFIG_FSL_SERDES2	0xe3100
+
+/*
+ * SATA
+ */
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1_OFFSET	0x18000
+#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2_OFFSET	0x19000
+#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC_PIN_MUX
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=ramfs.83xx\0"					\
+	"fdtaddr=780000\0"						\
+	"fdtfile=mpc8379_mds.dtb\0"					\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
new file mode 100644
index 0000000..37f51ba
--- /dev/null
+++ b/include/configs/MPC837XERDB.h
@@ -0,0 +1,428 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Kevin Lam <kevin.lam@freescale.com>
+ * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+
+#define CONFIG_HWCONFIG
+
+/*
+ * On-board devices
+ */
+#define CONFIG_VSC7385_ENET
+
+/* System performance - define the value i.e. CONFIG_SYS_XXX
+*/
+
+/* System Clock Configuration Register */
+#define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH		0x08200000
+#define CONFIG_SYS_SICRL		0x00000000
+
+/*
+ * Output Buffer Impedance
+ */
+#define CONFIG_SYS_OBIR		0x30100000
+
+/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
+
+#undef CONFIG_DDR_ECC		/* support DDR ECC function */
+#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+
+#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU	/* Never assert ODT to internal IOs */
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_ODT_WR_ONLY_CURRENT \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00260802 */ /* DDR400 */
+#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (13 << TIMING_CFG1_REFREC_SHIFT) \
+				| (3 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x3937d322 */
+#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (5 << TIMING_CFG2_CPO_SHIFT) \
+				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x02984cc8 */
+
+#define CONFIG_SYS_DDR_INTERVAL	((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x06090100 */
+
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+					| SDRAM_CFG_32_BE \
+					| SDRAM_CFG_2T_EN)
+					/* 0x43088000 */
+#else
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+					| SDRAM_CFG_SDRAM_TYPE_DDR2)
+					/* 0x43000000 */
+#endif
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
+					| (0x0442 << SDRAM_MODE_SD_SHIFT))
+					/* 0x04400442 */ /* DDR400 */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x0ef70010
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_FSL_ELBC		1
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CONFIG_SYS_NAND_BASE	0xE0600000
+
+
+/* Vitesse 7385 */
+
+#define CONFIG_SYS_VSC7385_BASE	0xF0000000
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+#define CONFIG_FSL_SERDES2	0xe3100
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC
+ */
+#ifdef CONFIG_TSEC_ENET
+
+#define CONFIG_GMII			/* MII PHY management */
+
+#define CONFIG_TSEC1
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME		"TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET		0x24000
+#define TSEC1_PHY_ADDR			2
+#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHYIDX			0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET		0x25000
+#define TSEC2_PHY_ADDR			0x1c
+#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHYIDX			0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC0"
+
+#endif
+
+/*
+ * SATA
+ */
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1_OFFSET	0x18000
+#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2_OFFSET	0x19000
+#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K (one sector) for env */
+	#define CONFIG_ENV_SIZE		0x4000
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC_PIN_MUX
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_NETDEV		"eth1"
+
+#define CONFIG_HOSTNAME		"mpc837x_rdb"
+#define CONFIG_ROOTPATH		"/nfsroot"
+#define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"
+#define CONFIG_BOOTFILE		"uImage"
+				/* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+#define CONFIG_FDTFILE		"mpc8379_rdb.dtb"
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" CONFIG_NETDEV "\0"				\
+	"uboot=" CONFIG_UBOOTPATH "\0"					\
+	"tftpflash=tftp $loadaddr $uboot;"				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"fdtaddr=780000\0"						\
+	"fdtfile=" CONFIG_FDTFILE "\0"					\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"						\
+	"run setipargs;"						\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
new file mode 100644
index 0000000..7697e8d
--- /dev/null
+++ b/include/configs/MPC8536DS.h
@@ -0,0 +1,654 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * mpc8536ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/freescale/common/ics307_clk.h"
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD		1
+#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH		1
+#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
+#endif
+
+#ifndef	CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#define CONFIG_PCI1		1	/* Enable PCI controller 1 */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x00010000	/* skip exception vectors */
+#define CONFIG_SYS_MEMTEST_END   0x1f000000	/* skip u-boot at top of RAM */
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+#if defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+#define CONFIG_SYS_SPD_BUS_NUM		1
+
+/* These are used when DDR doesn't use SPD. */
+#define CONFIG_SYS_SDRAM_SIZE		256	/* DDR is 256MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102 /* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
+#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
+#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL	0x06180100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL	0xC3008000	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2	0x04400010
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00010000
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map -- xxx -this is wrong, needs updating
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	Promjet/free		128M non-cacheable
+ * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_FLASH_BR_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM	0xf8000ff7
+
+#define CONFIG_SYS_BR1_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+		 | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
+				      CONFIG_SYS_FLASH_BASE_PHYS }
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_HWCONFIG			/* enable hwconfig */
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS	0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS	PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_PWR		0x5	/* PIXIS Power status register */
+#define PIXIS_AUX		0x6	/* Auxiliary 1 register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VSTAT		0x11	/* VELA Status Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_LBMAP	0xe0	/* VBOOT - CFG_LBMAP */
+#define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
+#define PIXIS_VBOOT_LBMAP_NOR1	0x01	/* cfg_lbmap - boot from NOR 1 */
+#define PIXIS_VBOOT_LBMAP_NOR2	0x02	/* cfg_lbmap - boot from NOR 2 */
+#define PIXIS_VBOOT_LBMAP_NOR3	0x03	/* cfg_lbmap - boot from NOR 3 */
+#define PIXIS_VBOOT_LBMAP_PJET	0x04	/* cfg_lbmap - boot from projet */
+#define PIXIS_VBOOT_LBMAP_NAND	0x05	/* cfg_lbmap - boot from NAND */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
+#define PIXIS_VSYSCLK0		0x1A	/* VELA SYSCLK0 Register */
+#define PIXIS_VSYSCLK1		0x1B	/* VELA SYSCLK1 Register */
+#define PIXIS_VSYSCLK2		0x1C	/* VELA SYSCLK2 Register */
+#define PIXIS_VDDRCLK0		0x1D	/* VELA DDRCLK0 Register */
+#define PIXIS_VDDRCLK1		0x1E	/* VELA DDRCLK1 Register */
+#define PIXIS_VDDRCLK2		0x1F	/* VELA DDRCLK2 Register */
+#define PIXIS_VWATCH		0x24    /* Watchdog Register */
+#define PIXIS_LED		0x25    /* LED Register */
+
+#define PIXIS_SPD_SYSCLK	0x7	/* SYSCLK option */
+
+/* old pixis referenced names */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x4e
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+		(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
+
+#ifndef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#else
+#define CONFIG_SYS_NAND_BASE		0xfff00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#endif
+#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
+				CONFIG_SYS_NAND_BASE + 0x40000, \
+				CONFIG_SYS_NAND_BASE + 0x80000, \
+				CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE	4
+#define CONFIG_NAND_FSL_ELBC	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+		| BR_PS_8		/* Port Size = 8 bit */ \
+		| BR_MS_FCM		/* MSEL = FCM */ \
+		| BR_V)			/* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFC0000	/* length 256K */ \
+		| OR_FCM_PGS		/* Large Page*/ \
+		| OR_FCM_CSCT \
+		| OR_FCM_CST \
+		| OR_FCM_CHT \
+		| OR_FCM_SCY_1 \
+		| OR_FCM_TRLX \
+		| OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+#define CONFIG_SYS_BR4_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
+		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+		| BR_PS_8		/* Port Size = 8 bit */ \
+		| BR_MS_FCM		/* MSEL = FCM */ \
+		| BR_V)			/* valid */
+#define CONFIG_SYS_OR4_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
+		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+		| BR_PS_8		/* Port Size = 8 bit */ \
+		| BR_MS_FCM		/* MSEL = FCM */ \
+		| BR_V)			/* valid */
+#define CONFIG_SYS_OR5_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
+		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+		| BR_PS_8		/* Port Size = 8 bit */ \
+		| BR_MS_FCM		/* MSEL = FCM */ \
+		| BR_V)			/* valid */
+#define CONFIG_SYS_OR6_PRELIM	CONFIG_SYS_NAND_OR_PRELIM	/* NAND Options */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_BUS		0xf0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_VIRT		0xffc00000
+#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_IO_PHYS		0xfffc00000ull
+#else
+#define CONFIG_SYS_PCI1_IO_PHYS		0xffc00000
+#endif
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00010000	/* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xf8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc10000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x08000000	/* 128M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x98000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xf8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc18000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x98000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0x98000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x08000000	/* 128M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, direct to uli, tgtid 3, Base address 8000 */
+#define CONFIG_SYS_PCIE3_NAME		"Slot 3"
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc30000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc30000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc30000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE3_IO_VIRT
+
+/*PCI video card used*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
+
+/* video */
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
+#endif
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#ifndef CONFIG_PCI_PNP
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
+	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define CONFIG_FSL_SGMII_RISER	1
+#define SGMII_RISER_PHY_OFFSET	0x1c
+
+#define TSEC1_PHY_ADDR		1	/* TSEC1 -> PHY1 */
+#define TSEC3_PHY_ADDR		0	/* TSEC3 -> PHY0 */
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_SIZE		0x2000	/* 8KB */
+#define CONFIG_ENV_OFFSET	0xF0000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV  0
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+#else
+	#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+	#define CONFIG_ENV_SIZE		0x2000
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_MPH_USB
+#ifdef CONFIG_HAS_FSL_MPH_USB
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#define CONFIG_IPADDR		192.168.1.254
+
+#define CONFIG_HOSTNAME		"unknown"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+"netdev=eth0\0"						\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+"tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" +$filesize; "	\
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize; "	\
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize\0"	\
+"consoledev=ttyS0\0"				\
+"ramdiskaddr=2000000\0"			\
+"ramdiskfile=8536ds/ramdisk.uboot\0"		\
+"fdtaddr=1e00000\0"				\
+"fdtfile=8536ds/mpc8536ds.dtb\0"		\
+"bdev=sda3\0"					\
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+
+#define CONFIG_HDBOOT				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"			\
+ "tftp $fdtaddr $fdtfile;"			\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+ "setenv bootargs root=/dev/nfs rw "	\
+ "nfsroot=$serverip:$rootpath "		\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+ "setenv bootargs root=/dev/ram rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $ramdiskaddr $ramdiskfile;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
new file mode 100644
index 0000000..13ca2c3
--- /dev/null
+++ b/include/configs/MPC8540ADS.h
@@ -0,0 +1,375 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ */
+
+/*
+ * mpc8540ads board configuration file
+ *
+ * Please refer to doc/README.mpc85xx for more info.
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * default CCARBAR is at 0xff700000
+ * assume U-Boot is less than 0.5MB
+ */
+
+#ifndef CONFIG_HAS_FEC
+#define CONFIG_HAS_FEC		1	/* 8540 has FEC */
+#endif
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ *
+ * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
+ * 33MHz to accommodate, based on a PCI pin.
+ * Note that PCI-X won't work at 33MHz.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	33000000
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD. */
+#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
+#define CONFIG_SYS_DDR_TIMING_1	0x37344321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */
+
+#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CONFIG_SYS_BR2_PRELIM		0xf0001861
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
+				| LSDMR_RFCR5		\
+				| LSDMR_PRETOACT3	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC2		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
+
+/*
+ * 32KB, 8-bit wide for ADS config reg
+ */
+#define CONFIG_SYS_BR4_PRELIM          0xf8000801
+#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
+#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* RapidIO MMU */
+#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+#if CONFIG_HAS_FEC
+#define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME		"FEC"
+#define FEC_PHY_ADDR		3
+#define FEC_PHYIDX		0
+#define FEC_FLAGS		0
+#endif
+
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #define CONFIG_ENV_SIZE		0x2000
+#else
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME		"unknown"
+#define CONFIG_ROOTPATH		"/nfsroot"
+#define CONFIG_BOOTFILE		"your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS0\0"                                                 \
+   "ramdiskaddr=1000000\0"						\
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
new file mode 100644
index 0000000..e00a56e
--- /dev/null
+++ b/include/configs/MPC8541CDS.h
@@ -0,0 +1,397 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ */
+
+/*
+ * mpc8541cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_CPM2		1	/* has CPM2 */
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_FSL_VIA
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
+#define CONFIG_BTB			    /* toggle branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+
+#define CONFIG_SYS_BR0_PRELIM		0xff801001
+#define CONFIG_SYS_BR1_PRELIM		0xff001001
+
+#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR1_PRELIM		0xff806e65
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CONFIG_SYS_BR2_PRELIM          0xf0001861
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CONFIG_FSL_CADMUS
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#define CONFIG_SYS_BR3_PRELIM   0xf8000801
+#define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_CCID
+#define CONFIG_SYS_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_VIRT	0xe2100000
+#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xe2100000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x100000	/* 1M */
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_MPC85XX_PCI2
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  "unknown"
+#define CONFIG_ROOTPATH  "/nfsroot"
+#define CONFIG_BOOTFILE  "your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS1\0"                                                 \
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
new file mode 100644
index 0000000..2cbe855
--- /dev/null
+++ b/include/configs/MPC8544DS.h
@@ -0,0 +1,422 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * mpc8544ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PCI1		1	/* PCI controller 1 */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ *
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ *
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ *
+ * 0xe000_0000	0xe00f_ffff	CCSR			1M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus cacheable
+ *
+ * 0xf000_0000	0xf3ff_ffff	SDRAM			64M Cacheable
+ * 0xf401_0000	0xf401_3fff	L1 for stack		4K Cacheable TLB0
+ *
+ * Localbus non-cacheable
+ *
+ * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS (*)	1M non-cacheable
+ * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M non-cacheable
+ * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M non-cacheable
+ *
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* boot TLB */
+
+#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of FLASH 8M */
+
+#define CONFIG_SYS_BR0_PRELIM		0xff801001
+#define CONFIG_SYS_BR1_PRELIM		0xfe801001
+
+#define CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define CONFIG_SYS_OR1_PRELIM		0xff806e65
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_LBC_NONCACHE_BASE	0xf8000000
+
+#define CONFIG_SYS_BR2_PRELIM		0xf8201001	/* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
+
+#define CONFIG_SYS_BR3_PRELIM		0xf8100801	/* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
+
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch
+					 * register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
+#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define PIXIS_VSPEED2		0x1d	/* VELA VSpeed 2 */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
+#define PIXIS_VSPEED2_TSEC1SER	0x2
+#define PIXIS_VSPEED2_TSEC3SER	0x1
+#define PIXIS_VCFGEN1_TSEC1SER	0x20
+#define PIXIS_VCFGEN1_TSEC3SER	0x40
+#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
+#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
+
+#define CONFIG_SYS_INIT_RAM_LOCK      1
+#define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCIE_VIRT		0x80000000	/* 1G PCIE TLB */
+#define CONFIG_SYS_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
+#define CONFIG_SYS_PCI_VIRT		0xc0000000	/* 512M PCI TLB */
+#define CONFIG_SYS_PCI_PHYS		0xc0000000	/* 512M PCI TLB */
+
+#define CONFIG_SYS_PCI1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 1, tgtid 1, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xe1010000
+#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe1010000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 2,tgtid 2, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe1020000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe1020000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, direct to uli, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_NAME		"ULI"
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xb0100000	/* reuse mem LAW */
+#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCIE3_MEM_VIRT2	0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_BUS2	0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_PHYS2	0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_SIZE2	0x00200000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
+
+/*PCI video card used*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
+
+/* video */
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#ifndef CONFIG_PCI_PNP
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
+	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#endif /* CONFIG_SCSI_AHCI */
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define CONFIG_PIXIS_SGMII_CMD
+#define CONFIG_FSL_SGMII_RISER	1
+#define SGMII_RISER_PHY_OFFSET	0x1c
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC3_PHY_ADDR		1
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) */
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR		0xfff80000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * USB
+ */
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_PCI_EHCI_DEVICE			0
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_IPADDR	192.168.1.251
+
+#define CONFIG_HOSTNAME	"8544ds_unknown"
+#define CONFIG_ROOTPATH	"/nfs/mpc85xx"
+#define CONFIG_BOOTFILE	"8544ds/uImage.uboot"
+#define CONFIG_UBOOTPATH	8544ds/u-boot.bin	/* TFTP server */
+
+#define CONFIG_SERVERIP	192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK	255.255.0.0
+
+#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+"netdev=eth0\0"						\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+"tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" +$filesize; "	\
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize; "	\
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize\0"	\
+"consoledev=ttyS0\0"				\
+"ramdiskaddr=2000000\0"			\
+"ramdiskfile=8544ds/ramdisk.uboot\0"		\
+"fdtaddr=1e00000\0"				\
+"fdtfile=8544ds/mpc8544ds.dtb\0"		\
+"bdev=sda3\0"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+ "setenv bootargs root=/dev/nfs rw "	\
+ "nfsroot=$serverip:$rootpath "		\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+ "setenv bootargs root=/dev/ram rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $ramdiskaddr $ramdiskfile;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		\
+ "setenv bootargs root=/dev/$bdev rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
new file mode 100644
index 0000000..3a8c074
--- /dev/null
+++ b/include/configs/MPC8548CDS.h
@@ -0,0 +1,530 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
+ */
+
+/*
+ * mpc8548cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
+#define CONFIG_PCI1		/* PCI controller 1 */
+#define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
+#undef CONFIG_PCI2
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+#define CONFIG_FSL_VIA
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+/*
+ * Physical Address Map
+ *
+ * 32bit:
+ * 0x0000_0000	0x7fff_ffff	DDR			2G	cacheable
+ * 0x8000_0000	0x9fff_ffff	PCI1 MEM		512M	cacheable
+ * 0xa000_0000	0xbfff_ffff	PCIe MEM		512M	cacheable
+ * 0xc000_0000	0xdfff_ffff	RapidIO			512M	cacheable
+ * 0xe000_0000	0xe00f_ffff	CCSR			1M	non-cacheable
+ * 0xe200_0000	0xe20f_ffff	PCI1 IO			1M	non-cacheable
+ * 0xe300_0000	0xe30f_ffff	PCIe IO			1M	non-cacheable
+ * 0xf000_0000	0xf3ff_ffff	SDRAM			64M	cacheable
+ * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS		1M	non-cacheable
+ * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
+ * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M	non-cacheable
+ *
+ * 36bit:
+ * 0x00000_0000	0x07fff_ffff	DDR			2G	cacheable
+ * 0xc0000_0000	0xc1fff_ffff	PCI1 MEM		512M	cacheable
+ * 0xc2000_0000	0xc3fff_ffff	PCIe MEM		512M	cacheable
+ * 0xc4000_0000	0xc5fff_ffff	RapidIO			512M	cacheable
+ * 0xfe000_0000	0xfe00f_ffff	CCSR			1M	non-cacheable
+ * 0xfe200_0000	0xfe20f_ffff	PCI1 IO			1M	non-cacheable
+ * 0xfe300_0000	0xfe30f_ffff	PCIe IO			1M	non-cacheable
+ * 0xff000_0000	0xff3ff_ffff	SDRAM			64M	cacheable
+ * 0xff800_0000	0xff80f_ffff	NVRAM/CADMUS		1M	non-cacheable
+ * 0xfff00_0000	0xfff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
+ * 0xfff80_0000	0xfffff_ffff	FLASH (boot bank)	8M	non-cacheable
+ *
+ */
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001	 BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001	 BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65	 ORx
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfff000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_BR0_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR1_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+
+#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR1_PRELIM		0xff806e65
+
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+	{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_HWCONFIG			/* enable hwconfig */
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	0xff0000000ull
+#else
+#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	CONFIG_SYS_LBC_SDRAM_BASE
+#endif
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CONFIG_SYS_BR2_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
+	| BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows	OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *		    or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL	  = BR[24:26] = 000
+ *    Valid		  = BR[31]    = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,	  OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT		  OR[20]    = 1
+ *    ACS		  OR[21:22] = 11
+ *    XACS		  OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA		  OR[28]    = 0
+ *    TRLX		  OR[29]    = 1
+ *    EHTR		  OR[30]    = 1
+ *    EAD extra time	  OR[31]    = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CONFIG_FSL_CADMUS
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#ifdef CONFIG_PHYS_64BIT
+#define CADMUS_BASE_ADDR_PHYS	0xff8000000ull
+#else
+#define CADMUS_BASE_ADDR_PHYS	CADMUS_BASE_ADDR
+#endif
+#define CONFIG_SYS_BR3_PRELIM \
+	(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	 0xfff00ff7
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_CCID
+#define CONFIG_SYS_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_BUS		0xe0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
+#else
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#endif
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe3000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
+#endif
+#endif
+
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
+
+#if defined(CONFIG_PCI)
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT		1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	1
+#define CONFIG_SYS_PCIE1_NAME		"Slot"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC2"
+#define CONFIG_TSEC4
+#define CONFIG_TSEC4_NAME	"eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR	0xfff80000
+#else
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K for env */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#define CONFIG_IPADDR	 192.168.1.253
+
+#define CONFIG_HOSTNAME	 "unknown"
+#define CONFIG_ROOTPATH	 "/nfsroot"
+#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
+#define CONFIG_UBOOTPATH	8548cds/u-boot.bin	/* TFTP server */
+
+#define CONFIG_SERVERIP	 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK	 255.255.255.0
+
+#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:ecc=off\0"		\
+	"netdev=eth0\0"				\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot; "	\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"consoledev=ttyS1\0"			\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=ramdisk.uboot\0"		\
+	"fdtaddr=1e00000\0"			\
+	"fdtfile=mpc8548cds.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "					\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
new file mode 100644
index 0000000..5b39334
--- /dev/null
+++ b/include/configs/MPC8555CDS.h
@@ -0,0 +1,393 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ */
+
+/*
+ * mpc8555cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_CPM2		1	/* has CPM2 */
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_FSL_VIA
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
+#define CONFIG_BTB			    /* toggle branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+
+#define CONFIG_SYS_BR0_PRELIM		0xff801001
+#define CONFIG_SYS_BR1_PRELIM		0xff001001
+
+#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR1_PRELIM		0xff806e65
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CONFIG_SYS_BR2_PRELIM          0xf0001861
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CONFIG_FSL_CADMUS
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#define CONFIG_SYS_BR3_PRELIM   0xf8000801
+#define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_CCID
+#define CONFIG_SYS_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_VIRT	0xe2100000
+#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xe2100000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_MPC85XX_PCI2
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  "unknown"
+#define CONFIG_ROOTPATH  "/nfsroot"
+#define CONFIG_BOOTFILE  "your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS1\0"                                                 \
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
new file mode 100644
index 0000000..5ba2b6d
--- /dev/null
+++ b/include/configs/MPC8560ADS.h
@@ -0,0 +1,405 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ */
+
+/*
+ * mpc8560ads board configuration file
+ *
+ * Please refer to doc/README.mpc85xx for more info.
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_SERVERIP, etc. in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_CPM2		1	/* has CPM2 */
+
+/*
+ * default CCARBAR is at 0xff700000
+ * assume U-Boot is less than 0.5MB
+ */
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_RESET_PHY_R	1	/* Call reset_phy() */
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	33000000
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
+#define CONFIG_SYS_DDR_TIMING_1	0x37344321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */
+
+#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CONFIG_SYS_BR2_PRELIM		0xf0001861
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
+				| LSDMR_RFCR5		\
+				| LSDMR_PRETOACT3	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC2		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
+
+/*
+ * 32KB, 8-bit wide for ADS config reg
+ */
+#define CONFIG_SYS_BR4_PRELIM          0xf8000801
+#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
+#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_ON_SCC	/* define if console on SCC */
+#undef  CONFIG_CONS_NONE	/* define if console on something else */
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* RapidIO MMU */
+#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+#ifdef CONFIG_TSEC_ENET
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_ETHER_ON_FCC		/* CPM FCC Ethernet */
+
+#undef  CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX      2       /* which channel for ether */
+
+#if (CONFIG_ETHER_INDEX == 2)
+  /*
+   * - Rx-CLK is CLK13
+   * - Tx-CLK is CLK14
+   * - Select bus for bd/buffers
+   * - Full duplex
+   */
+  #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CONFIG_SYS_CPMFCR_RAMTYPE    0
+  #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
+  #define FETH2_RST		0x01
+#elif (CONFIG_ETHER_INDEX == 3)
+  /* need more definitions here for FE3 */
+  #define FETH3_RST		0x80
+#endif					/* CONFIG_ETHER_INDEX */
+
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT	2		/* Port C */
+#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
+				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE	MDIO_DECLARE
+
+#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY	udelay(1)
+
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #define CONFIG_ENV_SIZE		0x2000
+#else
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
+
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME		"unknown"
+#define CONFIG_ROOTPATH		"/nfsroot"
+#define CONFIG_BOOTFILE		"your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+	"netdev=eth0\0"							\
+	"consoledev=ttyCPM\0"						\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=400000\0"						\
+	"fdtfile=mpc8560ads.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
new file mode 100644
index 0000000..01ee69c
--- /dev/null
+++ b/include/configs/MPC8568MDS.h
@@ -0,0 +1,411 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
+ */
+
+/*
+ * mpc8568mds board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
+#define CONFIG_PCI1		1	/* PCI controller */
+#define CONFIG_PCIE1		1	/* PCIE controller */
+#define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif						  /*Replace a call to get_clock_freq (after it is implemented)*/
+#define CONFIG_SYS_CLK_FREQ	66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
+#define CONFIG_BTB				/* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+#define CONFIG_SYS_BCSR_BASE		0xf8000000
+
+#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
+
+/*Chip select 0 - Flash*/
+#define CONFIG_SYS_BR0_PRELIM		0xfe001001
+#define	CONFIG_SYS_OR0_PRELIM		0xfe006ff7
+
+/*Chip slelect 1 - BCSR*/
+#define CONFIG_SYS_BR1_PRELIM		0xf8000801
+#define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
+
+/*#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE} */
+#define CONFIG_SYS_MAX_FLASH_BANKS		1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT		512		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/*
+ * SDRAM on the LocalBus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */
+
+/*Chip select 2 - SDRAM*/
+#define CONFIG_SYS_BR2_PRELIM      0xf0001861
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * The bcsr registers are connected to CS3 on MDS.
+ * The new memory map places bcsr at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+#define CONFIG_SYS_BCSR (0xf8000000)
+
+/*Chip slelect 4 - PIB*/
+#define CONFIG_SYS_BR4_PRELIM   0xf8008801
+#define CONFIG_SYS_OR4_PRELIM   0xffffe9f7
+
+/*Chip select 5 - PIB*/
+#define CONFIG_SYS_BR5_PRELIM	 0xf8010801
+#define CONFIG_SYS_OR5_PRELIM	 0xffff69f7
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
+
+/*
+ * General PCI
+ * Memory Addresses are mapped 1-1. I/O is mapped from 0
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00800000	/* 8M */
+
+#define CONFIG_SYS_PCIE1_NAME		"Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
+
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#ifndef CONFIG_TSEC_ENET
+#define CONFIG_ETHPRIME         "UEC0"
+#endif
+#define CONFIG_PHY_MODE_NEED_CHANGE
+#define CONFIG_eTSEC_MDIO_BUS
+
+#ifdef CONFIG_eTSEC_MDIO_BUS
+#define CONFIG_MIIM_ADDRESS	0xE0024520
+#endif
+
+#define CONFIG_UEC_ETH1         /* GETH1 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
+#define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR       7
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
+#endif
+
+#define CONFIG_UEC_ETH2         /* GETH2 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
+#define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR       1
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
+#endif
+#endif /* CONFIG_QE */
+
+#if defined(CONFIG_PCI)
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		3
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  "unknown"
+#define CONFIG_ROOTPATH  "/nfsroot"
+#define CONFIG_BOOTFILE  "your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS0\0"                                                 \
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"						\
+   "nfsargs=setenv bootargs root=/dev/nfs rw "				\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs\0"			\
+   "ramargs=setenv bootargs root=/dev/ram rw "				\
+      "console=$consoledev,$baudrate $othbootargs\0"			\
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "run nfsargs;"							\
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "run ramargs;"							\
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
new file mode 100644
index 0000000..de187bf
--- /dev/null
+++ b/include/configs/MPC8569MDS.h
@@ -0,0 +1,503 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * mpc8569mds board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
+#define CONFIG_PCIE1		1	/* PCIE controller */
+#define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+/* Replace a call to get_clock_freq (after it is implemented)*/
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+
+#ifdef CONFIG_ATM
+#define CONFIG_PQ_MDS_PIB
+#define CONFIG_PQ_MDS_PIB_ATM
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
+#define CONFIG_BTB				/* toggle branch predition */
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+#if defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+					/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS    0x51    /* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE           1024		/* DDR is 1024MB */
+#define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
+#define CONFIG_SYS_DDR_TIMING_3         0x00020000
+#define CONFIG_SYS_DDR_TIMING_0         0x00330004
+#define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
+#define CONFIG_SYS_DDR_TIMING_2         0x002888D0
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000
+#define CONFIG_SYS_DDR_SDRAM_CFG_2	0x04401040
+#define CONFIG_SYS_DDR_SDRAM_MODE	0x40401521
+#define CONFIG_SYS_DDR_SDRAM_MODE_2	0x8000C000
+#define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x03E00000
+#define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x01000000
+#define CONFIG_SYS_DDR_TIMING_4         0x00220001
+#define CONFIG_SYS_DDR_TIMING_5         0x03402400
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x0655A604
+#define CONFIG_SYS_DDR_CDR_1		0x80040000
+#define CONFIG_SYS_DDR_CDR_2		0x00000000
+#define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
+#define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
+#define CONFIG_SYS_DDR_CONTROL2         0x24400000
+
+#define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS          0x00000000
+#define CONFIG_SYS_DDR_SBE              0x00010000
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_BCSR_BASE		0xf8000000
+#define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
+
+/*Chip select 0 - Flash*/
+#define CONFIG_FLASH_BR_PRELIM		0xfe000801
+#define	CONFIG_FLASH_OR_PRELIM		0xfe000ff7
+
+/*Chip select 1 - BCSR*/
+#define CONFIG_SYS_BR1_PRELIM		0xf8000801
+#define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
+
+/*Chip select 4 - PIB*/
+#define CONFIG_SYS_BR4_PRELIM		0xf8008801
+#define CONFIG_SYS_OR4_PRELIM		0xffffe9f7
+
+/*Chip select 5 - PIB*/
+#define CONFIG_SYS_BR5_PRELIM		0xf8010801
+#define CONFIG_SYS_OR5_PRELIM		0xffffe9f7
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#undef CONFIG_SYS_RAMBOOT
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Chip select 3 - NAND */
+#ifndef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xFC000000
+#else
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#endif
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_FSL_ELBC		1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
+				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+				| BR_PS_8	     /* Port Size = 8 bit */ \
+				| BR_MS_FCM	     /* MSEL = FCM */ \
+				| BR_V)		     /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFC0000	     /* length 256K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#define CONFIG_SYS_BR3_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+#define CONFIG_SYS_LBC_LCRR	0x00000004	/* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR	0x00040000	/* LB config reg */
+#define CONFIG_SYS_LBC_LSRT	0x20000000	/* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR	0x00000000	/* LB refresh timer prescal*/
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000  /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM       1
+
+#define PLPPAR1_I2C_BIT_MASK		0x0000000F
+#define PLPPAR1_I2C2_VAL		0x00000000
+#define PLPPAR1_ESDHC_VAL		0x0000000A
+#define PLPDIR1_I2C_BIT_MASK		0x0000000F
+#define PLPDIR1_I2C2_VAL		0x0000000F
+#define PLPDIR1_ESDHC_VAL		0x00000006
+#define PLPPAR1_UART0_BIT_MASK		0x00000fc0
+#define PLPPAR1_ESDHC_4BITS_VAL		0x00000a80
+#define PLPDIR1_UART0_BIT_MASK		0x00000fc0
+#define PLPDIR1_ESDHC_4BITS_VAL		0x00000a80
+
+/*
+ * General PCI
+ * Memory Addresses are mapped 1-1. I/O is mapped from 0
+ */
+#define CONFIG_SYS_PCIE1_NAME		"Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
+
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_SYS_UCC_RGMII_MODE	/* Set UCC work at RGMII by default */
+#undef CONFIG_SYS_UCC_RMII_MODE		/* Set UCC work at RMII mode */
+
+#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME         "UEC0"
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1         /* GETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
+#define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR       7
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16	/* CLK16 for RMII */
+#define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR       8	/* 0x8 for RMII */
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH1 */
+
+#define CONFIG_UEC_ETH2         /* GETH2 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
+#define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR       1
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16	/* CLK 16 for RMII */
+#define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR       0x9	/* 0x9 for RMII */
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH2 */
+
+#define CONFIG_UEC_ETH3         /* GETH3 */
+#define CONFIG_HAS_ETH2
+
+#ifdef CONFIG_UEC_ETH3
+#define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
+#define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+#define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
+#define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR       2
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC3_TX_CLK		QE_CLK16 /* CLK_16 for RMII */
+#define CONFIG_SYS_UEC3_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR	0xA     /* 0xA for RMII */
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH3 */
+
+#define CONFIG_UEC_ETH4         /* GETH4 */
+#define CONFIG_HAS_ETH3
+
+#ifdef CONFIG_UEC_ETH4
+#define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
+#define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+#define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
+#define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR       3
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC4_TX_CLK		QE_CLK16 /* CLK16 for RMII */
+#define CONFIG_SYS_UEC4_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR	0xB     /* 0xB for RMII */
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH4 */
+
+#undef CONFIG_UEC_ETH6         /* GETH6 */
+#define CONFIG_HAS_ETH5
+
+#ifdef CONFIG_UEC_ETH6
+#define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
+#define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC6_PHY_ADDR       4
+#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
+#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
+#endif /* CONFIG_UEC_ETH6 */
+
+#undef CONFIG_UEC_ETH8         /* GETH8 */
+#define CONFIG_HAS_ETH7
+
+#ifdef CONFIG_UEC_ETH8
+#define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
+#define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC8_PHY_ADDR       6
+#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
+#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
+#endif /* CONFIG_UEC_ETH8 */
+
+#endif /* CONFIG_QE */
+
+#if defined(CONFIG_PCI)
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FW_ADDR	0xfff00000
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC_PIN_MUX
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	2048		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME "mpc8569mds"
+#define CONFIG_ROOTPATH  "/nfsroot"
+#define CONFIG_BOOTFILE  "your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=600000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=400000\0"						\
+	"fdtfile=your.fdt.dtb\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw "			\
+	"console=$consoledev,$baudrate $othbootargs\0"			\
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"run nfsargs;"							\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"run ramargs;"							\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
new file mode 100644
index 0000000..e3952f4
--- /dev/null
+++ b/include/configs/MPC8572DS.h
@@ -0,0 +1,624 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * mpc8572ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/freescale/common/ics307_clk.h"
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk() /* ddrclk for MPC85xx */
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x7fffffff
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS		0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS		CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+#if defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define CONFIG_SYS_SPD_BUS_NUM		1	/* SPD EEPROMS locate on I2C bus 1 */
+#define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x626b2634
+#define CONFIG_SYS_DDR_TIMING_2		0x062874cf
+#define CONFIG_SYS_DDR_MODE_1		0x00440462
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL		0x0c300100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL		0x00800000
+#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xc3000008	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2		0x24400000
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00010000
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_FLASH_BR_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
+
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#undef CONFIG_SYS_RAMBOOT
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_HWCONFIG			/* enable hwconfig */
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS	0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS	PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_PWR		0x5	/* PIXIS Power status register */
+#define PIXIS_AUX		0x6	/* Auxiliary 1 register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VSTAT		0x11	/* VELA Status Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_LBMAP	0xc0	/* VBOOT - CFG_LBMAP */
+#define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
+#define PIXIS_VBOOT_LBMAP_PJET	0x01	/* cfg_lbmap - boot from projet */
+#define PIXIS_VBOOT_LBMAP_NAND	0x02	/* cfg_lbmap - boot from NAND */
+#define PIXIS_VBOOT_LBMAP_NOR1	0x03	/* cfg_lbmap - boot from NOR 1 */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
+#define PIXIS_VSYSCLK0		0x1C	/* VELA SYSCLK0 Register */
+#define PIXIS_VSYSCLK1		0x1D	/* VELA SYSCLK1 Register */
+#define PIXIS_VSYSCLK2		0x1E	/* VELA SYSCLK2 Register */
+#define PIXIS_VDDRCLK0		0x1F	/* VELA DDRCLK0 Register */
+#define PIXIS_VDDRCLK1		0x20	/* VELA DDRCLK1 Register */
+#define PIXIS_VDDRCLK2		0x21	/* VELA DDRCLK2 Register */
+#define PIXIS_VWATCH		0x24    /* Watchdog Register */
+#define PIXIS_LED		0x25    /* LED Register */
+
+#define PIXIS_SPD_SYSCLK_MASK		0x7		/* SYSCLK option */
+
+/* old pixis referenced names */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
+#define PIXIS_VSPEED2_TSEC1SER	0x8
+#define PIXIS_VSPEED2_TSEC2SER	0x4
+#define PIXIS_VSPEED2_TSEC3SER	0x2
+#define PIXIS_VSPEED2_TSEC4SER	0x1
+#define PIXIS_VCFGEN1_TSEC1SER	0x20
+#define PIXIS_VCFGEN1_TSEC2SER	0x20
+#define PIXIS_VCFGEN1_TSEC3SER	0x20
+#define PIXIS_VCFGEN1_TSEC4SER	0x20
+#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER \
+					| PIXIS_VSPEED2_TSEC2SER \
+					| PIXIS_VSPEED2_TSEC3SER \
+					| PIXIS_VSPEED2_TSEC4SER)
+#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER \
+					| PIXIS_VCFGEN1_TSEC2SER \
+					| PIXIS_VCFGEN1_TSEC3SER \
+					| PIXIS_VCFGEN1_TSEC4SER)
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+#ifndef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#else
+#define CONFIG_SYS_NAND_BASE		0xfff00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
+				CONFIG_SYS_NAND_BASE + 0x40000, \
+				CONFIG_SYS_NAND_BASE + 0x80000,\
+				CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE    4
+#define CONFIG_NAND_FSL_ELBC	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+#define CONFIG_SYS_NAND_MAX_OOBFREE	5
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
+			       | OR_FCM_PGS	       /* Large Page*/ \
+			       | OR_FCM_CSCT \
+			       | OR_FCM_CST \
+			       | OR_FCM_CHT \
+			       | OR_FCM_SCY_1 \
+			       | OR_FCM_TRLX \
+			       | OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_OR6_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 3, direct to uli, tgtid 3, Base address 8000 */
+#define CONFIG_SYS_PCIE3_NAME		"ULI"
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
+
+/* video */
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#ifndef CONFIG_PCI_PNP
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCIE3_IO_BUS
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCIE3_IO_BUS
+	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#endif /* SCSI */
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define CONFIG_TSEC4	1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
+
+#define CONFIG_PIXIS_SGMII_CMD
+#define CONFIG_FSL_SGMII_RISER	1
+#define SGMII_RISER_PHY_OFFSET	0x1c
+
+#ifdef CONFIG_FSL_SGMII_RISER
+#define CONFIG_SYS_TBIPA_VALUE		0x10 /* avoid conflict with eTSEC4 paddr */
+#endif
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+
+#if defined(CONFIG_SYS_RAMBOOT)
+
+#else
+	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+	#define CONFIG_ENV_ADDR	0xfff80000
+	#else
+	#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+	#endif
+	#define CONFIG_ENV_SIZE	0x2000
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * USB
+ */
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_PCI_EHCI_DEVICE			0
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#define CONFIG_IPADDR		192.168.1.254
+
+#define CONFIG_HOSTNAME		"unknown"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0"		\
+"netdev=eth0\0"						\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"				\
+"tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" +$filesize; "	\
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize; "	\
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize\0"	\
+"consoledev=ttyS0\0"				\
+"ramdiskaddr=2000000\0"			\
+"ramdiskfile=8572ds/ramdisk.uboot\0"		\
+"fdtaddr=1e00000\0"				\
+"fdtfile=8572ds/mpc8572ds.dtb\0"		\
+"bdev=sda3\0"
+
+#define CONFIG_HDBOOT				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"			\
+ "tftp $fdtaddr $fdtfile;"			\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+ "setenv bootargs root=/dev/nfs rw "	\
+ "nfsroot=$serverip:$rootpath "		\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+ "setenv bootargs root=/dev/ram rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $ramdiskaddr $ramdiskfile;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
new file mode 100644
index 0000000..04f55e3
--- /dev/null
+++ b/include/configs/MPC8610HPCD.h
@@ -0,0 +1,575 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * MPC8610HPCD board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
+
+/* video */
+#define CONFIG_FSL_DIU_FB
+
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x2c000)
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#ifdef RUN_DIAG
+#define CONFIG_SYS_DIAG_ADDR		0xff800000
+#endif
+
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xc0000000
+
+#define CONFIG_PCI1		1	/* PCI controller 1 */
+#define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
+#define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
+#define CONFIG_ALTIVEC		1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CONFIG_SYS_L2
+#define L2_INIT		0
+#define L2_ENABLE	(L2CR_L2E |0x00100000 )
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
+
+/* DDR Setup */
+#define CONFIG_SPD_EEPROM		/* Use SPD for DDR */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
+
+#if 0 /* TODO */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
+#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
+#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL	0x06180100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2	0x04400010
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x00000000
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x000f0000
+
+#endif
+
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+#define CONFIG_SYS_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE2		0xf8000000
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+
+#define CONFIG_SYS_BR0_PRELIM		0xf8001001 /* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM		0xf8006e65 /* 128MB NOR Flash*/
+
+#define CONFIG_SYS_BR1_PRELIM		0xf0001001 /* port size 16bit */
+#define CONFIG_SYS_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
+#if 0 /* TODO */
+#define CONFIG_SYS_BR2_PRELIM		0xf0000000
+#define CONFIG_SYS_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
+#endif
+#define CONFIG_SYS_BR3_PRELIM		0xe8000801 /* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
+
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE	0xe8000000	/* PIXIS registers */
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_BRDCFG0		0x8	/* PIXIS Board Configuration Register0*/
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xC0    /* Reset altbank mask */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#undef CONFIG_SPD_EEPROM
+#define CONFIG_SYS_SDRAM_SIZE	256
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#ifndef CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BUS	0x0000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+/* controller 1, Base address 0xa000 */
+#define CONFIG_SYS_PCIE1_NAME		"ULI"
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/* 1M */
+
+/* controller 2, Base Address 0x9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000	/* reuse mem LAW */
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#define CONFIG_ULI526X
+
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_PCI_OHCI		1
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
+
+#if !defined(CONFIG_PCI_PNP)
+#define PCI_ENET0_IOADDR	0xe0000000
+#define PCI_ENET0_MEMADDR	0xe0000000
+#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * BAT0		2G	Cacheable, non-guarded
+ * 0x0000_0000	2G	DDR
+ */
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW)
+
+/*
+ * BAT1		1G	Cache-inhibited, guarded
+ * 0x8000_0000	256M	PCI-1 Memory
+ * 0xa000_0000	256M	PCI-Express 1 Memory
+ * 0x9000_0000	256M	PCI-Express 2 Memory
+ */
+
+#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
+
+/*
+ * BAT2		16M	Cache-inhibited, guarded
+ * 0xe100_0000	1M	PCI-1 I/O
+ */
+
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+
+/*
+ * BAT3		4M	Cache-inhibited, guarded
+ * 0xe000_0000	4M	CCSR
+ */
+
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
+
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
+/*
+ * BAT4		32M	Cache-inhibited, guarded
+ * 0xe200_0000	1M	PCI-Express 2 I/O
+ * 0xe300_0000	1M	PCI-Express 1 I/O
+ */
+
+#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
+
+/*
+ * BAT5		128K	Cacheable, non-guarded
+ * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
+
+/*
+ * BAT6		256M	Cache-inhibited, guarded
+ * 0xf000_0000	256M	FLASH
+ */
+#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE	 | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE	 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
+/*
+ * BAT7		4M	Cache-inhibited, guarded
+ * 0xe800_0000	4M	PIXIS
+ */
+#define CONFIG_SYS_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 126k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_WATCHDOG			/* watchdog enabled */
+#define CONFIG_SYS_WATCHDOG_FREQ	5000	/* Feed interval, 5s */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(256 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_IPADDR		192.168.1.100
+
+#define CONFIG_HOSTNAME		"unknown"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	8610hpcd/u-boot.bin
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		0x10000000
+
+#if defined(CONFIG_PCI1)
+#define PCI_ENV \
+ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
+	"echo e;md ${a}e00 9\0" \
+ "pci1regs=setenv a e0008; run pcireg\0" \
+ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+	"pci d.w $b.0 56 1\0" \
+ "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
+	"pci w.w $b.0 56 ffff\0"	\
+ "pci1err=setenv a e0008; run pcierr\0"	\
+ "pci1errc=setenv a e0008; run pcierrc\0"
+#else
+#define	PCI_ENV ""
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
+#define PCIE_ENV \
+ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
+	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
+ "pcie1regs=setenv a e000a; run pciereg\0"	\
+ "pcie2regs=setenv a e0009; run pciereg\0"	\
+ "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
+	"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"	\
+	"pci d $b.0 130 1\0" \
+ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
+	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
+	"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"		\
+ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"	\
+ "pcie1err=setenv a e000a; run pcieerr\0"	\
+ "pcie2err=setenv a e0009; run pcieerr\0"	\
+ "pcie1errc=setenv a e000a; run pcieerrc\0"	\
+ "pcie2errc=setenv a e0009; run pcieerrc\0"
+#else
+#define	PCIE_ENV ""
+#endif
+
+#define DMA_ENV \
+ "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
+	"mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
+ "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
+	"mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
+ "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
+	"mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
+ "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
+	"mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
+
+#ifdef ENV_DEBUG
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+"netdev=eth0\0"							\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+"tftpflash=tftpboot $loadaddr $uboot; "				\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" +$filesize; "	\
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize; "	\
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize\0"	\
+"consoledev=ttyS0\0"						\
+"ramdiskaddr=0x18000000\0"					\
+"ramdiskfile=8610hpcd/ramdisk.uboot\0"				\
+"fdtaddr=0x17c00000\0"						\
+"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"				\
+"bdev=sda3\0"					\
+"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+"maxcpus=1"	\
+"eoi=mw e00400b0 0\0"						\
+"iack=md e00400a0 1\0"						\
+"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
+	"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
+	"md ${a}f00 5\0" \
+"ddr1regs=setenv a e0002; run ddrreg\0" \
+"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
+	"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
+	"md ${a}e60 1; md ${a}ef0 1d\0" \
+"guregs=setenv a e00e0; run gureg\0" \
+"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
+"mcmregs=setenv a e0001; run mcmreg\0" \
+"diuregs=md e002c000 1d\0" \
+"dium=mw e002c01c\0" \
+"diuerr=md e002c014 1\0" \
+"pmregs=md e00e1000 2b\0" \
+"lawregs=md e0000c08 4b\0" \
+"lbcregs=md e0005000 36\0" \
+"dma0regs=md e0021100 12\0" \
+"dma1regs=md e0021180 12\0" \
+"dma2regs=md e0021200 12\0" \
+"dma3regs=md e0021280 12\0" \
+ PCI_ENV \
+ PCIE_ENV \
+ DMA_ENV
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=0x18000000\0"				\
+	"ramdiskfile=8610hpcd/ramdisk.uboot\0"			\
+	"fdtaddr=0x17c00000\0"					\
+	"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"			\
+	"bdev=sda3\0"
+#endif
+
+#define CONFIG_NFSBOOTCOMMAND					\
+ "setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "				\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"		\
+ "tftp $loadaddr $bootfile;"					\
+ "tftp $fdtaddr $fdtfile;"					\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs;"		\
+ "tftp $ramdiskaddr $ramdiskfile;"				\
+ "tftp $loadaddr $bootfile;"					\
+ "tftp $fdtaddr $fdtfile;"					\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		\
+ "setenv bootargs root=/dev/$bdev rw "	\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
new file mode 100644
index 0000000..8c01891
--- /dev/null
+++ b/include/configs/MPC8641HPCN.h
@@ -0,0 +1,649 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2006, 2010-2011 Freescale Semiconductor.
+ *
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ */
+
+/*
+ * MPC8641HPCN board configuration file
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_SERVERIP, etc. in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
+#define CONFIG_ADDR_MAP		1	/* Use addr map */
+
+/*
+ * default CCSRBAR is at 0xff700000
+ * assume U-Boot is less than 0.5MB
+ */
+
+#ifdef RUN_DIAG
+#define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
+#endif
+
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xe0000000
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (ULI bridge) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
+#define CONFIG_SYS_NUM_ADDR_MAP 8	/* Number of addr map slots = 8 dbats */
+
+#define CONFIG_ALTIVEC		1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CONFIG_SYS_L2
+#define L2_INIT		0
+#define L2_ENABLE	(L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * With the exception of PCI Memory and Rapid IO, most devices will simply
+ * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
+ * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
+#else
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+
+/* Physical addresses */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	CONFIG_SYS_PHYS_ADDR_HIGH
+#define CONFIG_SYS_CCSRBAR_PHYS \
+	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
+			    CONFIG_SYS_CCSRBAR_PHYS_HIGH)
+
+#define CONFIG_HWCONFIG	/* use hwconfig to control memory interleaving */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/*
+ * I2C addresses of SPD EEPROMs
+ */
+#define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 0 DIMM 1 */
+#define SPD_EEPROM_ADDRESS3	0x53	/* CTLR 1 DIMM 0 */
+#define SPD_EEPROM_ADDRESS4	0x54	/* CTLR 1 DIMM 1 */
+
+/*
+ * These are used when DDR doesn't use SPD.
+ */
+#define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1	0x39357322
+#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
+#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL	0x06090100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2	0x04400000
+
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+#define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE_PHYS_LOW	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE_PHYS \
+	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
+			    CONFIG_SYS_PHYS_ADDR_HIGH)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				 | 0x00001001)	/* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
+
+#define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CF_BASE_PHYS)		\
+				 | 0x00001001)	/* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM	0xffffeff7	/* 32k Compact Flash */
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS)	\
+				 | 0x00000801) /* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32k PIXIS area*/
+
+/*
+ * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
+ * The PIXIS and CF by themselves aren't large enough to take up the 128k
+ * required for the smallest BAT mapping, so there's a 64k hole.
+ */
+#define CONFIG_SYS_LBC_BASE		0xffde0000
+#define CONFIG_SYS_LBC_BASE_PHYS_LOW	CONFIG_SYS_LBC_BASE
+
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
+#define PIXIS_BASE_PHYS_LOW	(CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
+#define PIXIS_BASE_PHYS		PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
+						    CONFIG_SYS_PHYS_ADDR_HIGH)
+#define PIXIS_SIZE		0x00008000	/* 32k */
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
+#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
+
+/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
+#define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
+#define CF_BASE_PHYS		(PIXIS_BASE_PHYS + PIXIS_SIZE)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#undef CONFIG_SPD_EEPROM
+#define CONFIG_SYS_SDRAM_SIZE	256
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#ifndef CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_SRIO1_MEM_BASE	0x80000000	/* base address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	0x00000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	CONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_PHYS \
+	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
+			    CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+
+#define CONFIG_SYS_PCIE1_NAME		"ULI"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	0x00000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x0000000c
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	CONFIG_SYS_PCIE1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	CONFIG_SYS_PCIE1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x00000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_PHYS \
+	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
+			    CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_PHYS_LOW	CONFIG_SYS_PCIE1_IO_VIRT
+#define CONFIG_SYS_PCIE1_IO_PHYS \
+	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
+			    CONFIG_SYS_PHYS_ADDR_HIGH)
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64K */
+
+#ifdef CONFIG_PHYS_64BIT
+/*
+ * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
+ * This will increase the amount of PCI address space available for
+ * for mapping RAM.
+ */
+#define CONFIG_SYS_PCIE2_MEM_BUS	CONFIG_SYS_PCIE1_MEM_BUS
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	(CONFIG_SYS_PCIE1_MEM_BUS \
+					 + CONFIG_SYS_PCIE1_MEM_SIZE)
+#endif
+#define CONFIG_SYS_PCIE2_MEM_VIRT 	(CONFIG_SYS_PCIE1_MEM_VIRT \
+					 + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW	(CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
+					 + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH	CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
+#define CONFIG_SYS_PCIE2_MEM_PHYS	(CONFIG_SYS_PCIE1_MEM_PHYS \
+					 + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_VIRT 	(CONFIG_SYS_PCIE1_IO_VIRT \
+					 + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_PHYS_LOW	(CONFIG_SYS_PCIE1_IO_PHYS_LOW \
+					 + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_PHYS	(CONFIG_SYS_PCIE1_IO_PHYS \
+					 + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_SIZE	CONFIG_SYS_PCIE1_IO_SIZE
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_PCI_OHCI			1
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
+
+/*PCI video card used*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCIE1_IO_VIRT*/
+
+/* video */
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3		1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define CONFIG_TSEC4		1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_PHYS_64BIT
+#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
+#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
+
+/* Put physical address into the BAT format */
+#define BAT_PHYS_ADDR(low, high) \
+	(low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
+/* Convert high/low pairs to actual 64-bit value */
+#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
+#else
+/* 32-bit systems just ignore the "high" bits */
+#define BAT_PHYS_ADDR(low, high)        (low)
+#define PAIRED_PHYS_TO_PHYS(low, high)  (low)
+#endif
+
+/*
+ * BAT0		DDR
+ */
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+
+/*
+ * BAT1		LBC (PIXIS/CF)
+ */
+#define CONFIG_SYS_DBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
+
+/* if CONFIG_PCI:
+ * BAT2		PCIE1 and PCIE1 MEM
+ * if CONFIG_RIO
+ * BAT2		Rapidio Memory
+ */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
+					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
+					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+#else /* CONFIG_RIO */
+#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
+					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
+					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+#endif
+
+/*
+ * BAT3		CCSR Space
+ */
+#define CONFIG_SYS_DBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
+					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
+				 | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
+					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
+
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
+/*
+ * BAT4		PCIE1_IO and PCIE2_IO
+ */
+#define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
+
+/*
+ * BAT5		Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
+
+/*
+ * BAT6		FLASH
+ */
+#define CONFIG_SYS_DBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
+				 | BATU_VP)
+#define CONFIG_SYS_IBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
+/*
+ * BAT7		FREE - used later for tmp mappings
+ */
+#define CONFIG_SYS_DBAT7L 0x00000000
+#define CONFIG_SYS_DBAT7U 0x00000000
+#define CONFIG_SYS_IBAT7L 0x00000000
+#define CONFIG_SYS_IBAT7U 0x00000000
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+    #define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+    #define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
+#else
+    #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#endif
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(256 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+    #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_HAS_ETH0		1
+#define CONFIG_HAS_ETH1		1
+#define CONFIG_HAS_ETH2		1
+#define CONFIG_HAS_ETH3		1
+
+#define CONFIG_IPADDR		192.168.1.100
+
+#define CONFIG_HOSTNAME		"unknown"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		0x10000000
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=0x18000000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=0x17c00000\0"						\
+	"fdtfile=mpc8641_hpcn.dtb\0"					\
+	"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"			\
+	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
+	"maxcpus=2"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	      "nfsroot=$serverip:$rootpath "				\
+	      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	      "console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	      "console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
new file mode 100644
index 0000000..64172f3
--- /dev/null
+++ b/include/configs/MigoR.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Renesas Solutions Migo-R board
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ */
+
+#ifndef __MIGO_R_H
+#define __MIGO_R_H
+
+#define CONFIG_CPU_SH7722	1
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* SMC9111 */
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE    (0xB0000000)
+
+/* MEMORY */
+#define MIGO_R_SDRAM_BASE	(0x8C000000)
+#define MIGO_R_FLASH_BASE_1	(0xA0000000)
+#define MIGO_R_FLASH_BANK_SIZE	(64 * 1024 * 1024)
+
+#define CONFIG_SYS_PBSIZE		256		/* Buffer size for Console output */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
+
+/* SCIF */
+#define CONFIG_CONS_SCIF0	1
+
+#define CONFIG_SYS_MEMTEST_START	(MIGO_R_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Enable alternate, more extensive, memory test */
+/* Scratch address used by the alternate memory test */
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE	(MIGO_R_SDRAM_BASE)
+/* maybe more, but if so u-boot doesn't know about it... */
+#define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)
+/* default load address for scripts ?!? */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CONFIG_SYS_MONITOR_BASE	(MIGO_R_FLASH_BASE_1)
+/* Monitor size */
+#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
+
+/* FLASH */
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+/* Physical start address of Flash memory */
+#define CONFIG_SYS_FLASH_BASE	(MIGO_R_FLASH_BASE_1)
+/* Max number of sectors on each Flash chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/* ENV setting */
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+
+#endif	/* __MIGO_R_H */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
new file mode 100644
index 0000000..1152bca
--- /dev/null
+++ b/include/configs/P1010RDB.h
@@ -0,0 +1,767 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * P010 RDB board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/config_mpc85xx.h>
+#define CONFIG_NAND_FSL_IFC
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_PAD_TO		0x18000
+#define CONFIG_SPL_MAX_SIZE		(96 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#else
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_PAD_TO			0x18000
+#define CONFIG_SPL_MAX_SIZE			(96 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+#endif
+
+#ifdef CONFIG_NAND
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#else
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_TPL_TEXT_BASE		0xD0001000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xD0000000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xD0000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO	0x20000
+#define CONFIG_TPL_PAD_TO	0x20000
+#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
+#endif
+#endif
+
+#ifdef CONFIG_NAND_SECBOOT	/* NAND Boot */
+#define CONFIG_RAMBOOT_NAND
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_TPL_TEXT_BASE
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2			/* PCIE controller 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"mini PCIe Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+#define CONFIG_SYS_PCIE2_NAME		"PCIe Slot"
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+#define CONFIG_SYS_PCIE2_NAME		"mini PCIe Slot"
+#endif
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on P1010 RDB */
+#define CONFIG_SYS_CLK_FREQ	66666666 /* SYSCLK for P1010 RDB */
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+
+/* DDR Setup */
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM		1
+#define SPD_EEPROM_ADDRESS		0x52
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_sdram_size(void);
+#endif
+#define CONFIG_SYS_SDRAM_SIZE		get_sdram_size() /* DDR size */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+/* DDR3 Controller Settings */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xc70c0008      /* Type = DDR3  */
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
+#define CONFIG_SYS_DDR_TIMING_4		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3_800	0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_800	0x00110104
+#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b8644
+#define CONFIG_SYS_DDR_TIMING_2_800	0x0FA888CF
+#define CONFIG_SYS_DDR_CLK_CTRL_800	0x03000000
+#define CONFIG_SYS_DDR_MODE_1_800	0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800	0x0C300100
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
+
+/* settings for DDR3 at 667MT/s */
+#define CONFIG_SYS_DDR_TIMING_3_667		0x00010000
+#define CONFIG_SYS_DDR_TIMING_0_667		0x00110004
+#define CONFIG_SYS_DDR_TIMING_1_667		0x5d59e544
+#define CONFIG_SYS_DDR_TIMING_2_667		0x0FA890CD
+#define CONFIG_SYS_DDR_CLK_CTRL_667		0x03000000
+#define CONFIG_SYS_DDR_MODE_1_667		0x00441210
+#define CONFIG_SYS_DDR_MODE_2_667		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_667		0x0a280000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_667	0x8675F608
+
+#define CONFIG_SYS_CCSRBAR			0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW		CONFIG_SYS_CCSRBAR
+
+/* Don't relocate CCSRBAR while in NAND_SPL */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x3fff_ffff	DDR			1G cacheable
+ * 0x8000_0000  0xbfff_ffff	PCI Express Mem		1.5G non-cacheable
+ * 0xffc0_0000  0xffc3_ffff	PCI IO range		256k non-cacheable
+ *
+ * Localbus non-cacheable
+ * 0xff80_0000	0xff8f_ffff	NAND Flash		1M non-cacheable
+ * 0xffb0_0000	0xffbf_ffff	Board CPLD		1M non-cacheable
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+
+#define CONFIG_SYS_FLASH_BASE		0xee000000
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(32*1024*1024)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(7)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_FTIM0	FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5)
+#define CONFIG_SYS_NOR_FTIM1	FTIM1_NOR_TACO(0x1e) | \
+				FTIM1_NOR_TRAD_NOR(0x0f)
+#define CONFIG_SYS_NOR_FTIM2	FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWP(0x1c)
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+/* CFI for NOR Flash */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* NAND Flash on IFC */
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_MTD_PARTITION
+
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	\
+				| CSPR_MSEL_NAND	\
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
+				| CSOR_NAND_RAL_2	/* RAL = 2 Bytes */ \
+				| CSOR_NAND_PGS_512	/* Page Size = 512b */ \
+				| CSOR_NAND_SPRZ_16	/* Spare size = 16 */ \
+				| CSOR_NAND_PB(32))	/* 32 Pages Per Block */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
+				| CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+/* NAND Flash Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		FTIM0_NAND_TCCST(0x01) | \
+					FTIM0_NAND_TWP(0x0C)   | \
+					FTIM0_NAND_TWCHT(0x04) | \
+					FTIM0_NAND_TWH(0x05)
+#define CONFIG_SYS_NAND_FTIM1		FTIM1_NAND_TADLE(0x1d) | \
+					FTIM1_NAND_TWBE(0x1d)  | \
+					FTIM1_NAND_TRR(0x07)   | \
+					FTIM1_NAND_TRP(0x0c)
+#define CONFIG_SYS_NAND_FTIM2		FTIM2_NAND_TRAD(0x0c) | \
+					FTIM2_NAND_TREH(0x05) | \
+					FTIM2_NAND_TWHRE(0x0f)
+#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
+
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a)  | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3	0x0
+#endif
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+/* Set up IFC registers for boot location NOR/NAND */
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE		0xffb00000
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CPLD_BASE_PHYS	0xfffb00000ull
+#else
+#define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
+#endif
+
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3		IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3		0x0
+/* CPLD Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
+	defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_A003399_NOR_WORKAROUND
+#endif
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xD0001000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(128 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xD0001000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
+/* Serial Port */
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define I2C_PCA9557_ADDR1		0x18
+#define I2C_PCA9557_ADDR2		0x19
+#define I2C_PCA9557_BUS_NUM		0
+
+/* I2C EEPROM */
+#if defined(CONFIG_TARGET_P1010RDB_PB)
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define MAX_NUM_PORTS			9 /* for 128Bytes EEPROM */
+#endif
+/* enable read and write access to EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* RTC */
+#define CONFIG_RTC_PT7C4338
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/*
+ * SPI interface will not be available in case of NAND boot SPI CS0 will be
+ * used for SLIC
+ */
+#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
+/* eSPI - Enhanced SPI */
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR		1
+#define TSEC2_PHY_ADDR		0
+#define TSEC3_PHY_ADDR		2
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+/* TBI PHY configuration for SGMII mode */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+		TBICR_PHY_RESET \
+		| TBICR_ANEG_ENABLE \
+		| TBICR_FULL_DUPLEX \
+		| TBICR_SPEED1_SET \
+		)
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#endif /* #ifdef CONFIG_FSL_SATA  */
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#endif
+#endif
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SDCARD)
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#elif defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_ENV_RANGE	(32 * CONFIG_ENV_SIZE) /* new block size 512K */
+#endif
+#endif
+#define CONFIG_ENV_OFFSET	(1024 * 1024)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE			0x2000
+#else
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
+		 || defined(CONFIG_FSL_SATA)
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"	\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"loadaddr=1000000\0"			\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=1e00000\0"				\
+	"fdtfile=p1010rdb.dtb\0"		\
+	"bdev=sda1\0"	\
+	"hwconfig=usb1:dr_mode=host,phy_type=utmi\0"	\
+	"othbootargs=ramdisk_size=600000\0" \
+	"usbfatboot=setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"usb start;"			\
+	"fatload usb 0:2 $loadaddr $bootfile;"		\
+	"fatload usb 0:2 $fdtaddr $fdtfile;"	\
+	"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"usb start;"			\
+	"ext2load usb 0:4 $loadaddr $bootfile;"		\
+	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
+	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
+	CONFIG_BOOTMODE
+
+#if defined(CONFIG_TARGET_P1010RDB_PA)
+#define CONFIG_BOOTMODE \
+	"boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
+	"boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
+	"boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
+
+#elif defined(CONFIG_TARGET_P1010RDB_PB)
+#define CONFIG_BOOTMODE \
+	"boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
+	"i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
+	"boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
+	"i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
+	"boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
+	"i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
+	"boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
+	"i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
+	"boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
+	"i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
+#endif
+
+#define CONFIG_RAMBOOTCOMMAND		\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
new file mode 100644
index 0000000..4b2eb65
--- /dev/null
+++ b/include/configs/P1022DS.h
@@ -0,0 +1,607 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/freescale/common/ics307_clk.h"
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+#define CONFIG_SYS_NAND_MAX_OOBFREE	5
+
+#ifdef CONFIG_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_TPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_MAX_SIZE		4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#endif
+
+/* High Level Configuration Options */
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2			/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3			/* PCIE controller 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x7fffffff
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
+       SPL code*/
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_VERY_BIG_RAM
+
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define CONFIG_SYS_SPD_BUS_NUM		1
+#define SPD_EEPROM_ADDRESS		0x51	/* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE		2048
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS1_BNDS		0x0040007F
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_TIMING_3		0x00010000
+#define CONFIG_SYS_DDR_TIMING_0		0x40110104
+#define CONFIG_SYS_DDR_TIMING_1		0x5c5bd746
+#define CONFIG_SYS_DDR_TIMING_2		0x0fa8d4ca
+#define CONFIG_SYS_DDR_MODE_1		0x00441221
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL		0x0a280100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL		0x02800000
+#define CONFIG_SYS_DDR_CONTROL		0xc7000008
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401041
+#define	CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define	CONFIG_SYS_DDR_TIMING_5		0x02401400
+#define	CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8675f608
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xdfff_ffff	PCI Express Mem		1.5G non-cacheable
+ * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xff80_0000	0xff80_7fff	NAND			32K non-cacheable
+ * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe8000000 /* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe8000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_FLASH_BR_PRELIM  \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM	(OR_AM_128MB | 0xff7)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#endif
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_TPL_TEXT_BASE
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+#endif
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Nand Flash */
+#if defined(CONFIG_NAND_FSL_ELBC)
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * 1024)
+#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB	       /* length 256K */ \
+			       | OR_FCM_PGS	       /* Large Page*/ \
+			       | OR_FCM_CSCT \
+			       | OR_FCM_CST \
+			       | OR_FCM_CHT \
+			       | OR_FCM_SCY_1 \
+			       | OR_FCM_TRLX \
+			       | OR_FCM_EHTR)
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#else
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+
+#endif /* CONFIG_NAND_FSL_ELBC */
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_FSL_NGPIXIS
+#define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS		0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS		PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_32KB | 0x6ff7)
+
+#define PIXIS_LBMAP_SWITCH	7
+#define PIXIS_LBMAP_MASK	0xF0
+#define PIXIS_LBMAP_ALTBANK	0x20
+#define PIXIS_SPD		0x07
+#define PIXIS_SPD_SYSCLK_MASK	0x07
+#define PIXIS_ELBC_SPI_MASK	0xc0
+#define PIXIS_SPI		0x80
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000 /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Video */
+
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
+#ifdef CONFIG_ATI
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
+#define CONFIG_BIOSEMU
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#ifdef CONFIG_TSEC_ENET
+
+#define CONFIG_TSECV2
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+#define TSEC1_PHY_ADDR		1
+#define TSEC2_PHY_ADDR		2
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_ENV_SIZE		0x2000	/* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define CONFIG_ENV_OFFSET	(1024 * 1024)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_HOSTNAME		"p1022ds"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+#define CONFIG_LOADADDR		1000000
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+		"protect off $ubootaddr +$filesize && "		\
+		"erase $ubootaddr +$filesize && "		\
+		"cp.b $loadaddr $ubootaddr $filesize && "	\
+		"protect on $ubootaddr +$filesize && "		\
+		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
+	"fdtaddr=1e00000\0"	  			      	\
+	"fdtfile=p1022ds.dtb\0"	  				\
+	"bdev=sda3\0"		  			      	\
+	"hwconfig=esdhc;audclk:12\0"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
+
+#endif
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
new file mode 100644
index 0000000..9535a7b
--- /dev/null
+++ b/include/configs/P1023RDB.h
@@ -0,0 +1,348 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors:  Roy Zang <tie-fei.zang@freescale.com>
+ *	     Chunhe Lan <Chunhe.Lan@freescale.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/* High Level Configuration Options */
+
+#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
+#define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3		/* PCIE controller 3 (slot 3) */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x02000000
+
+/* Implement conversion of addresses in the LBC */
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SDRAM_SIZE		512u	/* DDR is 512M */
+#define CONFIG_SYS_SPD_BUS_NUM          0
+#define SPD_EEPROM_ADDRESS              0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x1fff_ffff	DDR			512M cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ * 0xff00_0000	0xff3f_ffff	DPAA_QBMAN		4M cacheable
+ * 0xff60_0000	0xff7f_ffff	CCSR			2M non-cacheable
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K cacheable TLB0
+ *
+ * Localbus non-cacheable
+ *
+ * 0xec00_0000	0xefff_ffff	NOR flash		64M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xec000000 /* start of FLASH 64M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				| BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)	  /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(6 * 1024 * 1024) /* Reserved for malloc */
+
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB		/* length 256K */ \
+				| OR_FCM_PGS \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* Serial Port */
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_NAME		"Slot 3"
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)   /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)   /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	(u-boot.bin) /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+/* Qman/Bman */
+#define CONFIG_SYS_QMAN_MEM_BASE	0xff000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_BMAN_MEM_BASE	0xff200000
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+
+/* For FM */
+#define CONFIG_SYS_DPAA_FMAN
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_ATHEROS
+#endif
+
+/* Default address of microcode for the Linux Fman driver */
+/* QE microcode/firmware address */
+#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x2
+
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"loadaddr=1000000\0"					\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot; "			\
+		"protect off $ubootaddr +$filesize; "		\
+		"erase $ubootaddr +$filesize; "			\
+		"cp.b $loadaddr $ubootaddr $filesize; "		\
+		"protect on $ubootaddr +$filesize; "		\
+		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
+	"fdtaddr=1e00000\0"					\
+	"fdtfile=p1023rdb.dtb\0"				\
+	"othbootargs=ramdisk_size=600000\0"			\
+	"bdev=sda1\0"						\
+	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
new file mode 100644
index 0000000..f8cfef7
--- /dev/null
+++ b/include/configs/P2041RDB.h
@@ -0,0 +1,603 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * P2041 RDB board configuration file
+ * Also supports P2040 RDB
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
+#endif
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SPIFLASH)
+	#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+	#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+	#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+	#define CONFIG_FSL_FIXED_MMC_LOCATION
+	#define CONFIG_SYS_MMC_ENV_DEV          0
+	#define CONFIG_ENV_SIZE			0x2000
+	#define CONFIG_ENV_OFFSET		(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE \
+			- CONFIG_ENV_SECT_SIZE)
+	#define CONFIG_ENV_SIZE		0x2000
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
+		CONFIG_RAMBOOT_TEXT_BASE)
+#else
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
+#endif
+#define CONFIG_SYS_L3_SIZE		(1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x52
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of platform clock */
+#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
+
+/*
+ * This board doesn't have a promjet connector.
+ * However, it uses commone corenet board LAW and TLB.
+ * It is necessary to use the same start address with proper offset.
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_FLASH_BR_PRELIM \
+		(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
+		BR_PS_16 | BR_V)
+#define CONFIG_SYS_FLASH_OR_PRELIM \
+		((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+		 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
+
+#define CONFIG_FSL_CPLD
+#define CPLD_BASE		0xffdf0000	/* CPLD registers */
+#ifdef CONFIG_PHYS_64BIT
+#define CPLD_BASE_PHYS		0xfffdf0000ull
+#else
+#define CPLD_BASE_PHYS		CPLD_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_LBMAP_SWITCH	7
+#define PIXIS_LBMAP_MASK	0xf0
+#define PIXIS_LBMAP_SHIFT	4
+#define PIXIS_LBMAP_ALTBANK	0x40
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_NAND_FSL_ELBC
+/* Nand Flash */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
+			       | OR_FCM_PGS	       /* Large Page*/ \
+			       | OR_FCM_CSCT \
+			       | OR_FCM_CST \
+			       | OR_FCM_CHT \
+			       | OR_FCM_SCY_1 \
+			       | OR_FCM_TRLX \
+			       | OR_FCM_EHTR)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#endif /* CONFIG_NAND_FSL_ELBC */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
+
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+
+/* Qman/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#endif
+
+#ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x2
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x3
+#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR	0x4
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x1
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x0
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR	0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR	0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR	0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR	0x1f
+
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	0
+
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_HAS_FSL_MPH_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define __USB_PHY_TYPE	utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
+	"bank_intlv=cs0_cs1\0"					\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
+	"usb_dr_mode=host\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=p2041rdb/ramdisk.uboot\0"			\
+	"fdtaddr=1e00000\0"					\
+	"fdtfile=p2041rdb/p2041rdb.dtb\0"			\
+	"bdev=sda3\0"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
new file mode 100644
index 0000000..2f6cc5d
--- /dev/null
+++ b/include/configs/P3041DS.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * P3041 DS board configuration file
+ *
+ */
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE3
+#define CONFIG_PCIE4
+#define CONFIG_SYS_DPAA_RMAN
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
+
+#include "corenet_ds.h"
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
new file mode 100644
index 0000000..ed88b41
--- /dev/null
+++ b/include/configs/P4080DS.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * P4080 DS board configuration file
+ * Also supports P4040 DS
+ */
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_PCIE3
+
+#define CONFIG_SYS_SATA_MAX_DEVICE  2
+#define CONFIG_LBA48
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_ICS307_REFCLK_HZ		33333000  /* ICS307 ref clk freq */
+
+#include "corenet_ds.h"
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
new file mode 100644
index 0000000..873d39a
--- /dev/null
+++ b/include/configs/P5020DS.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * P5020 DS board configuration file
+ * Also supports P5010 DS
+ */
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE3
+#define CONFIG_PCIE4
+#define CONFIG_SYS_FSL_RAID_ENGINE
+#define CONFIG_SYS_DPAA_RMAN
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
+
+#include "corenet_ds.h"
diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h
new file mode 100644
index 0000000..12666d6
--- /dev/null
+++ b/include/configs/P5040DS.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * P5040 DS board configuration file
+ *
+ */
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_PCIE3
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_FSL_RAID_ENGINE
+
+#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
+
+#include "corenet_ds.h"
diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h
new file mode 100644
index 0000000..f24cd23
--- /dev/null
+++ b/include/configs/SBx81LIFKW.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Allied Telesis <www.alliedtelesis.co.nz>
+ */
+
+#ifndef _CONFIG_SBX81LIFKW_H
+#define _CONFIG_SBX81LIFKW_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+
+#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_PCIE_INIT	/* Enable PCIE Port0 */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_GPIO	1
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/*Console on UART0 */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
+
+#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
+#define MTDPARTS_MTDOOPS "errlog"
+#define CONFIG_DOS_PARTITION
+
+/*
+ *  Environment variables configurations
+ */
+#define CONFIG_ENV_SECT_SIZE		0x40000		/* 256K */
+#define CONFIG_ENV_SIZE			0x02000
+#define CONFIG_ENV_OFFSET		0xc0000		/* env starts here - 768K */
+
+/*
+ * U-Boot bootcode configuration
+ */
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for monitor */
+#define CONFIG_SYS_MALLOC_LEN		  (4 << 20)	/* Reserve 4.0 MB for malloc */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
+
+/* size in bytes reserved for initial data */
+
+#include <asm/arch/config.h>
+/* There is no PHY directly connected so don't ask it for link status */
+#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
+#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE	/* include NetConsole support */
+#define CONFIG_NET_MULTI	/* specify more that one ports available */
+#define CONFIG_MVGBE	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable a single port */
+#define CONFIG_PHY_BASE_ADR	0x01
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#endif /* CONFIG_CMD_NET */
+
+#define CONFIG_SYS_LOAD_ADDR  0x1000000      /* default location for tftp and bootm */
+
+#endif /* _CONFIG_SBX81LIFKW_H */
diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h
new file mode 100644
index 0000000..b602323
--- /dev/null
+++ b/include/configs/SBx81LIFXCAT.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Allied Telesis <www.alliedtelesis.co.nz>
+ */
+
+#ifndef _CONFIG_SBX81LIFXCAT_H
+#define _CONFIG_SBX81LIFXCAT_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+
+#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_PCIE_INIT	/* Enable PCIE Port0 */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_GPIO	1
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/*Console on UART0 */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
+
+#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
+#define MTDPARTS_MTDOOPS "errlog"
+#define CONFIG_DOS_PARTITION
+
+/*
+ *  Environment variables configurations
+ */
+#define CONFIG_ENV_SECT_SIZE		0x40000		/* 256K */
+#define CONFIG_ENV_SIZE			0x02000
+#define CONFIG_ENV_OFFSET		0xc0000		/* env starts here - 768K */
+
+/*
+ * U-Boot bootcode configuration
+ */
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for monitor */
+#define CONFIG_SYS_MALLOC_LEN		  (4 << 20)	/* Reserve 4.0 MB for malloc */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
+
+/* size in bytes reserved for initial data */
+
+#include <asm/arch/config.h>
+/* There is no PHY directly connected so don't ask it for link status */
+#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
+#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE	/* include NetConsole support */
+#define CONFIG_NET_MULTI	/* specify more that one ports available */
+#define CONFIG_MVGBE	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable a single port */
+#define CONFIG_PHY_BASE_ADR	0x01
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#endif /* CONFIG_CMD_NET */
+
+#define CONFIG_SYS_LOAD_ADDR  0x1000000      /* default location for tftp and bootm */
+
+#endif /* _CONFIG_SBX81LIFXCAT_H */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
new file mode 100644
index 0000000..fe9a909
--- /dev/null
+++ b/include/configs/T102xQDS.h
@@ -0,0 +1,772 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * T1024/T1023 QDS board configuration file
+ */
+
+#ifndef __T1024QDS_H
+#define __T1024QDS_H
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP		1
+#define CONFIG_SYS_NUM_ADDR_MAP	64	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DEEP_SLEEP
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/* PCIe Boot - Master */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#else
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
+#endif
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS	 0x3ffe00000ull
+#else
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
+#endif
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE     0x40000 /* 256K */
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/* PCIe Boot - Slave */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+/* Set 1M boot space for PCIe boot */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_SIZE			0x2000		/* 8KB */
+#define CONFIG_ENV_OFFSET		0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		(256 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x51
+
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE		0xffdf0000
+#ifdef CONFIG_PHYS_64BIT
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+#else
+#define QIXIS_BASE_PHYS		QIXIS_BASE
+#endif
+#define QIXIS_LBMAP_SWITCH		0x06
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define	QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Video */
+#ifdef CONFIG_ARCH_T1024		/* no DIU on T1023 */
+#define CONFIG_FSL_DIU_FB
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_FSL_DIU_CH7301
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	50000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	50000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+
+#define I2C_MUX_PCA_ADDR		0x77
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+#define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR		0x18
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+#define I2C_MUX_CH_DIU		0xC
+#define I2C_MUX_CH5		0xD
+#define I2C_MUX_CH7		0xF
+
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR	 0x38
+#define CONFIG_SYS_I2C_DVI_ADDR	 0x75
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231	1
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCIe
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0x90000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/*
+ *SATA
+ */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_LBA48
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+
+/* Default address of microcode for the Linux FMan driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#define CONFIG_SYS_QE_FW_ADDR	0x130000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
+#define CONFIG_SYS_QE_FW_ADDR		(512 * 0x920)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_FMAN_FW_ADDR		(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FW_ADDR		(12 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#define CONFIG_SYS_QE_FW_ADDR		0xEFE00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define RGMII_PHY1_ADDR		0x1
+#define RGMII_PHY2_ADDR		0x2
+#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
+#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
+#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_ETHPRIME		"FM1@DTSEC4"
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */
+#define CONFIG_LOADADDR		1000000 /* default location for tftp, bootm */
+#define __USB_PHY_TYPE		utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0"  \
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
+	"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
+	"ramdiskfile=t1024qds/ramdisk.uboot\0"			\
+	"fdtfile=t1024qds/t1024qds.dtb\0"			\
+	"netdev=eth0\0"						\
+	"video-mode=fslfb:1024x768-32@60,monitor=dvi\0"		\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"fdtaddr=d00000\0"					\
+	"bdev=sda3\0"
+
+#define CONFIG_LINUX					\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __T1024QDS_H */
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
new file mode 100644
index 0000000..8c1434f
--- /dev/null
+++ b/include/configs/T102xRDB.h
@@ -0,0 +1,744 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * T1024/T1023 RDB board configuration file
+ */
+
+#ifndef __T1024RDB_H
+#define __T1024RDB_H
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP		1
+#define CONFIG_SYS_NUM_ADDR_MAP	64	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+
+#define CONFIG_ENV_OVERWRITE
+
+/* support deep sleep */
+#ifdef CONFIG_ARCH_T1024
+#define CONFIG_DEEP_SLEEP
+#endif
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x30000000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x30000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
+#endif
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
+#endif
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RESET_VECTOR_ADDRESS	0x30000FFC
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x30000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x30000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
+#endif
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/* PCIe Boot - Master */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#else
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
+#endif
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS	 0x3ffe00000ull
+#else
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
+#endif
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE	0x40000 /* 256K */
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET	0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK	0x00000001 /* release core 0 */
+
+/* PCIe Boot - Slave */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+/* Set 1M boot space for PCIe boot */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS	\
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_SIZE			0x2000		/* 8KB */
+#define CONFIG_ENV_OFFSET		0x100000	/* 1MB */
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#endif
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_SIZE			0x2000
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_ENV_OFFSET		(2 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	100000000
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		(256 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x51
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_SDRAM_SIZE   2048
+#endif
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe8000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+/* NOR Flash Timing Params */
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
+				CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
+#endif
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+
+#ifdef CONFIG_TARGET_T1024RDB
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE		0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT		(0xf)
+#define CONFIG_SYS_CSPR2		(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+						| CSPR_PORT_SIZE_8 \
+						| CSPR_MSEL_GPCM \
+						| CSPR_V)
+#define CONFIG_SYS_AMASK2		IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2		0x0
+
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+						FTIM0_GPCM_TEADC(0x0e) | \
+						FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+						FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+						FTIM2_GPCM_TCH(0x8) | \
+						FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+#endif
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL 3Bytes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_128	/* Spare size = 128 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#endif
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe03c000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Video */
+#undef CONFIG_FSL_DIU_FB	/* RDB doesn't support DIU */
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	50000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	50000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+
+#define I2C_PCA6408_BUS_NUM		1
+#define I2C_PCA6408_ADDR		0x20
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT	0x8
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS1337	1
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCIe
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#endif
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+
+/* Default address of microcode for the Linux FMan driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#define CONFIG_SYS_QE_FW_ADDR	0x130000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
+#define CONFIG_SYS_QE_FW_ADDR		(512 * 0x920)
+#elif defined(CONFIG_NAND)
+#if defined(CONFIG_TARGET_T1024RDB)
+#define CONFIG_SYS_FMAN_FW_ADDR		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FW_ADDR		(4 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define CONFIG_SYS_FMAN_FW_ADDR		(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FW_ADDR		(12 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR		0xFFE00000
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#define CONFIG_SYS_QE_FW_ADDR		0xEFE00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_REALTEK
+#if defined(CONFIG_TARGET_T1024RDB)
+#define RGMII_PHY1_ADDR		0x2
+#define RGMII_PHY2_ADDR		0x6
+#define SGMII_AQR_PHY_ADDR	0x2
+#define FM1_10GEC1_PHY_ADDR	0x1
+#elif defined(CONFIG_TARGET_T1023RDB)
+#define RGMII_PHY1_ADDR		0x1
+#define SGMII_RTK_PHY_ADDR	0x3
+#define SGMII_AQR_PHY_ADDR	0x2
+#endif
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_ETHPRIME		"FM1@DTSEC4"
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
+#define CONFIG_LOADADDR		1000000 /* default location for tftp, bootm */
+#define __USB_PHY_TYPE		utmi
+
+#ifdef CONFIG_ARCH_T1024
+#define CONFIG_BOARDNAME t1024rdb
+#define BANK_INTLV cs0_cs1
+#else
+#define CONFIG_BOARDNAME t1023rdb
+#define BANK_INTLV  null
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
+	"bank_intlv=" __stringify(BANK_INTLV) "\0"		\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
+	"ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
+	"fdtfile=" __stringify(CONFIG_BOARDNAME) "/"		\
+	__stringify(CONFIG_BOARDNAME) ".dtb\0"			\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
+	"netdev=eth0\0"						\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"fdtaddr=1e00000\0"					\
+	"bdev=sda3\0"
+
+#define CONFIG_LINUX					\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __T1024RDB_H */
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
new file mode 100644
index 0000000..d8b65e6
--- /dev/null
+++ b/include/configs/T1040QDS.h
@@ -0,0 +1,681 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * T1040 QDS board configuration file
+ */
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
+#define CONFIG_PCIE4			/* PCIE controller 4 */
+
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_MTD_NOR_FLASH
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+#else /* CONFIG_MTD_NOR_FLASH */
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x51
+
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE	0xfe000000
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE		0xffdf0000
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+#define QIXIS_LBMAP_SWITCH		0x06
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define	QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Video */
+#define CONFIG_FSL_DIU_FB
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_FSL_DIU_CH7301
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	50000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SPEED	50000
+#define CONFIG_SYS_FSL_I2C3_SPEED	50000
+#define CONFIG_SYS_FSL_I2C4_SPEED	50000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET	0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET	0x119100
+
+#define I2C_MUX_PCA_ADDR		0x77
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+#define I2C_MUX_CH_DIU		0xC
+
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR         0x38
+#define CONFIG_SYS_I2C_DVI_ADDR         0x75
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 4, Base address 203000 */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#define CONFIG_SYS_QE_FW_ADDR		0xEFF10000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x10
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x11
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x01
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x02
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
+
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+/* Enable VSC9953 L2 Switch driver */
+#define CONFIG_VSC9953
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x14
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x18
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define __USB_PHY_TYPE	utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:bank_intlv=auto;"			\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"video-mode=fslfb:1024x768-32@60,monitor=dvi\0"		\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t1040qds/ramdisk.uboot\0"			\
+	"fdtaddr=1e00000\0"					\
+	"fdtfile=t1040qds/t1040qds.dtb\0"			\
+	"bdev=sda3\0"
+
+#define CONFIG_LINUX                       \
+	"setenv bootargs root=/dev/ram rw "            \
+	"console=$consoledev,$baudrate $othbootargs;"  \
+	"setenv ramdiskaddr 0x02000000;"               \
+	"setenv fdtaddr 0x00c00000;"		       \
+	"setenv loadaddr 0x1000000;"		       \
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
new file mode 100644
index 0000000..53ee148
--- /dev/null
+++ b/include/configs/T104xRDB.h
@@ -0,0 +1,824 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * T104x RDB board configuration file
+ */
+#include <asm/config_mpc85xx.h>
+
+#ifdef CONFIG_RAMBOOT_PBL
+
+#ifndef CONFIG_SECURE_BOOT
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_PBI \
+		$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
+#endif
+
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+
+#ifdef CONFIG_NAND
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image.
+ */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) + \
+					 CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#endif
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x30000000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x30000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#ifdef CONFIG_TARGET_T1040RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1040D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
+#endif
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define	CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x30000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x30000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#ifdef CONFIG_TARGET_T1040RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1040D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
+#endif
+#endif
+
+#ifdef CONFIG_SDCARD
+#define	CONFIG_RESET_VECTOR_ADDRESS		0x30000FFC
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x30000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x30000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#ifdef CONFIG_TARGET_T1040RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1040D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
+#endif
+#ifdef CONFIG_TARGET_T1042D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
+#endif
+#endif
+
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
+#define CONFIG_PCIE4			/* PCIE controller 4 */
+
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 0x800)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_RAMBOOT_NAND
+#define CONFIG_BOOTSCRIPT_COPY_RAM
+#endif
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+/*
+ * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
+ * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
+ * (CONFIG_SYS_INIT_L3_VADDR) will be different.
+ */
+#define CONFIG_SYS_INIT_L3_VADDR	0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		256 << 10
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x51
+
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE	0xfe000000
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* CPLD on IFC */
+#define CPLD_LBMAP_MASK			0x3F
+#define CPLD_BANK_SEL_MASK		0x07
+#define CPLD_BANK_OVERRIDE		0x40
+#define CPLD_LBMAP_ALTBANK		0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK		0x40 /* BANK OR | BANK0 */
+#define CPLD_LBMAP_RESET		0xFF
+#define CPLD_LBMAP_SHIFT		0x03
+
+#if defined(CONFIG_TARGET_T1042RDB_PI)
+#define CPLD_DIU_SEL_DFP		0x80
+#elif defined(CONFIG_TARGET_T1042D4RDB)
+#define CPLD_DIU_SEL_DFP		0xc0
+#endif
+
+#if defined(CONFIG_TARGET_T1040D4RDB)
+#define CPLD_INT_MASK_ALL		0xFF
+#define CPLD_INT_MASK_THERM		0x80
+#define CPLD_INT_MASK_DVI_DFP		0x40
+#define CPLD_INT_MASK_QSGMII1		0x20
+#define CPLD_INT_MASK_QSGMII2		0x10
+#define CPLD_INT_MASK_SGMI1		0x08
+#define CPLD_INT_MASK_SGMI2		0x04
+#define CPLD_INT_MASK_TDMR1		0x02
+#define CPLD_INT_MASK_TDMR2		0x01
+#endif
+
+#define CONFIG_SYS_CPLD_BASE	0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT	(0xf)
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2	0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008044
+#if defined(CONFIG_NAND)
+#define CONFIG_A008044_WORKAROUND
+#endif
+#endif
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
+/* Video */
+#define CONFIG_FSL_DIU_FB
+
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_FSL_DIU_CH7301
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C3_SPEED	400000
+#define CONFIG_SYS_FSL_I2C4_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET	0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET	0x119100
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR                0x70
+#define I2C_MUX_CH_DEFAULT      0x8
+
+#if defined(CONFIG_TARGET_T1042RDB_PI)	|| \
+	defined(CONFIG_TARGET_T1040D4RDB)	|| \
+	defined(CONFIG_TARGET_T1042D4RDB)
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR		0x38
+#define CONFIG_SYS_I2C_DVI_ADDR		0x75
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS1337               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/*DVI encoder*/
+#define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#endif
+
+/* controller 4, Base address 203000 */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#endif
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+#define CONFIG_U_QE
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_FMAN_FW_ADDR	(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_QE_FW_ADDR		0x130000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_QE_FW_ADDR		(512 * 0x920)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FW_ADDR		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FW_ADDR		0xEFF10000
+#endif
+
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
+#define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
+#elif defined(CONFIG_TARGET_T1040D4RDB)
+#define CONFIG_SYS_SGMII1_PHY_ADDR             0x01
+#elif defined(CONFIG_TARGET_T1042D4RDB)
+#define CONFIG_SYS_SGMII1_PHY_ADDR             0x02
+#define CONFIG_SYS_SGMII2_PHY_ADDR             0x03
+#define CONFIG_SYS_SGMII3_PHY_ADDR             0x01
+#endif
+
+#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
+#define CONFIG_SYS_RGMII1_PHY_ADDR             0x04
+#define CONFIG_SYS_RGMII2_PHY_ADDR             0x05
+#else
+#define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
+#define CONFIG_SYS_RGMII2_PHY_ADDR             0x02
+#endif
+
+/* Enable VSC9953 L2 Switch driver on T1040 SoC */
+#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
+#define CONFIG_VSC9953
+#ifdef CONFIG_TARGET_T1040RDB
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x04
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x08
+#else
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR	0x08
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR	0x0c
+#endif
+#endif
+
+#define CONFIG_ETHPRIME		"FM1@DTSEC4"
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define __USB_PHY_TYPE	utmi
+#define RAMDISKFILE	"t104xrdb/ramdisk.uboot"
+
+#ifdef CONFIG_TARGET_T1040RDB
+#define FDTFILE		"t1040rdb/t1040rdb.dtb"
+#elif defined(CONFIG_TARGET_T1042RDB_PI)
+#define FDTFILE		"t1042rdb_pi/t1042rdb_pi.dtb"
+#elif defined(CONFIG_TARGET_T1042RDB)
+#define FDTFILE		"t1042rdb/t1042rdb.dtb"
+#elif defined(CONFIG_TARGET_T1040D4RDB)
+#define FDTFILE		"t1042rdb/t1040d4rdb.dtb"
+#elif defined(CONFIG_TARGET_T1042D4RDB)
+#define FDTFILE		"t1042rdb/t1042d4rdb.dtb"
+#endif
+
+#ifdef CONFIG_FSL_DIU_FB
+#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
+#else
+#define DIU_ENVIRONMENT
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"			\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+	"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"video-mode=" __stringify(DIU_ENVIRONMENT) "\0"		\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=" __stringify(RAMDISKFILE) "\0"		\
+	"fdtaddr=1e00000\0"					\
+	"fdtfile=" __stringify(FDTFILE) "\0"			\
+	"bdev=sda3\0"
+
+#define CONFIG_LINUX                       \
+	"setenv bootargs root=/dev/ram rw "            \
+	"console=$consoledev,$baudrate $othbootargs;"  \
+	"setenv ramdiskaddr 0x02000000;"               \
+	"setenv fdtaddr 0x00c00000;"		       \
+	"setenv loadaddr 0x1000000;"		       \
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
new file mode 100644
index 0000000..54ec1ab
--- /dev/null
+++ b/include/configs/T208xQDS.h
@@ -0,0 +1,787 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * T2080/T2081 QDS board configuration file
+ */
+
+#ifndef __T208xQDS_H
+#define __T208xQDS_H
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
+#define CONFIG_SRIO1		/* SRIO port 1 */
+#define CONFIG_SRIO2		/* SRIO port 2 */
+#elif defined(CONFIG_ARCH_T2081)
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
+
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
+#elif defined(CONFIG_ARCH_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
+#endif
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
+#elif defined(CONFIG_ARCH_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
+#endif
+#endif
+
+#ifdef CONFIG_SDCARD
+#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
+#elif defined(CONFIG_ARCH_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
+#endif
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB		/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		(512 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+
+#define CONFIG_SYS_DCSRBAR	0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CTRL_INTLV_PREFERED	cacheline
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE			0xffdf0000
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_RCW_SRC_NAND		0x104
+#define QIXIS_RCW_SRC_SD		0x040
+#define QIXIS_RST_CTL_RESET		0x83
+#define QIXIS_RST_FORCE_MEM		0x1
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)    | \
+					FTIM0_NAND_TWCHT(0x07)  | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)   | \
+					FTIM1_NAND_TRR(0x0e)    | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+					FTIM2_NAND_TREH(0x0a)   | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+#define CONFIG_SYS_FSL_I2C_SPEED   100000
+#define CONFIG_SYS_FSL_I2C2_SPEED  100000
+#define CONFIG_SYS_FSL_I2C3_SPEED  100000
+#define CONFIG_SYS_FSL_I2C4_SPEED  100000
+#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
+#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
+#define I2C_MUX_CH_DEFAULT	0x8
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR           0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
+
+#define CONFIG_VID_FLS_ENV		"t208xqds_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_IR36021_READ
+/* The lowest and highest voltage allowed for T208xQDS */
+#define VDD_MV_MIN			819
+#define VDD_MV_MAX			1212
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+#define CONFIG_PCIE4		/* PCIE controller 4 */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+
+#ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_BMAN_NUM_PORTALS	18
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	18
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define RGMII_PHY1_ADDR	0x1
+#define RGMII_PHY2_ADDR	0x2
+#define FM1_10GEC1_PHY_ADDR	  0x3
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_ETHPRIME		"FM1@DTSEC3"
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_LBA48
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH	 "/opt/nfsroot"
+#define CONFIG_BOOTFILE	 "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+#define __USB_PHY_TYPE		utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
+	"fdtaddr=1e00000\0"					\
+	"fdtfile=t2080qds/t2080qds.dtb\0"			\
+	"bdev=sda3\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the
+ * proof point app code automatically
+ */
+#define CONFIG_PROOF_POINTS				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x29000000 - - -;"		\
+	"cpu 2 release 0x29000000 - - -;"		\
+	"cpu 3 release 0x29000000 - - -;"		\
+	"cpu 4 release 0x29000000 - - -;"		\
+	"cpu 5 release 0x29000000 - - -;"		\
+	"cpu 6 release 0x29000000 - - -;"		\
+	"cpu 7 release 0x29000000 - - -;"		\
+	"go 0x29000000"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x01000000 - - -;"		\
+	"cpu 2 release 0x01000000 - - -;"		\
+	"cpu 3 release 0x01000000 - - -;"		\
+	"cpu 4 release 0x01000000 - - -;"		\
+	"cpu 5 release 0x01000000 - - -;"		\
+	"cpu 6 release 0x01000000 - - -;"		\
+	"cpu 7 release 0x01000000 - - -;"		\
+	"go 0x01000000"
+
+#define CONFIG_LINUX				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __T208xQDS_H */
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
new file mode 100644
index 0000000..3d95c4a
--- /dev/null
+++ b/include/configs/T208xRDB.h
@@ -0,0 +1,736 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * T2080 RDB/PCIe board configuration file
+ */
+
+#ifndef __T2080RDB_H
+#define __T2080RDB_H
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
+#define CONFIG_FSL_SATA_V2
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
+
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
+#endif
+
+#ifdef CONFIG_SDCARD
+#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB		/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(2 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	66660000
+#define CONFIG_DDR_CLK_FREQ	133330000
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		(512 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+
+#define CONFIG_SYS_DCSRBAR	0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CTRL_INTLV_PREFERED	cacheline
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS }
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE	0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT	(0xf)
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2	0x0
+
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)    | \
+					FTIM0_NAND_TWCHT(0x07)  | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)   | \
+					FTIM1_NAND_TRR(0x0e)    | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+					FTIM2_NAND_TREH(0x0a)   | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+#define CONFIG_SYS_FSL_I2C_SPEED   100000
+#define CONFIG_SYS_FSL_I2C2_SPEED  100000
+#define CONFIG_SYS_FSL_I2C3_SPEED  100000
+#define CONFIG_SYS_FSL_I2C4_SPEED  100000
+#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
+#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
+#define I2C_MUX_CH_DEFAULT	0x8
+
+#define I2C_MUX_CH_VOL_MONITOR	0xa
+
+#define CONFIG_VID_FLS_ENV		"t208xrdb_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_IR36021_READ
+/* The lowest and highest voltage allowed for T208xRDB */
+#define VDD_MV_MIN			819
+#define VDD_MV_MAX			1212
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+#define CONFIG_PCIE4		/* PCIE controller 4 */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+
+#ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_BMAN_NUM_PORTALS	18
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	18
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR		0x110000
+#define CONFIG_CORTINA_FW_ADDR		0x120000
+
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
+ */
+#define CONFIG_SYS_CORTINA_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
+#define CONFIG_CORTINA_FW_ADDR		(512 * 0x8a0)
+
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_CORTINA_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_CORTINA_FW_ADDR		(4 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_CORTINA_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR		0xFFE00000
+#define CONFIG_CORTINA_FW_ADDR		0xFFE10000
+#else
+#define CONFIG_SYS_CORTINA_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#define CONFIG_CORTINA_FW_ADDR		0xEFE00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_CORTINA
+#define CONFIG_PHY_REALTEK
+#define CONFIG_CORTINA_FW_LENGTH	0x40000
+#define RGMII_PHY1_ADDR		0x01  /* RealTek RTL8211E */
+#define RGMII_PHY2_ADDR		0x02
+#define CORTINA_PHY_ADDR1	0x0c  /* Cortina CS4315 */
+#define CORTINA_PHY_ADDR2	0x0d
+#define FM1_10GEC3_PHY_ADDR	0x00  /* Aquantia AQ1202 10G Base-T */
+#define FM1_10GEC4_PHY_ADDR	0x01
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_ETHPRIME		"FM1@DTSEC3"
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_LBA48
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+
+/*
+ * Environment
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH	 "/opt/nfsroot"
+#define CONFIG_BOOTFILE	 "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+#define __USB_PHY_TYPE		utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t2080rdb/ramdisk.uboot\0"			\
+	"fdtaddr=1e00000\0"					\
+	"fdtfile=t2080rdb/t2080rdb.dtb\0"			\
+	"bdev=sda3\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the
+ * proof point app code automatically
+ */
+#define CONFIG_PROOF_POINTS				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x29000000 - - -;"		\
+	"cpu 2 release 0x29000000 - - -;"		\
+	"cpu 3 release 0x29000000 - - -;"		\
+	"cpu 4 release 0x29000000 - - -;"		\
+	"cpu 5 release 0x29000000 - - -;"		\
+	"cpu 6 release 0x29000000 - - -;"		\
+	"cpu 7 release 0x29000000 - - -;"		\
+	"go 0x29000000"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x01000000 - - -;"		\
+	"cpu 2 release 0x01000000 - - -;"		\
+	"cpu 3 release 0x01000000 - - -;"		\
+	"cpu 4 release 0x01000000 - - -;"		\
+	"cpu 5 release 0x01000000 - - -;"		\
+	"cpu 6 release 0x01000000 - - -;"		\
+	"cpu 7 release 0x01000000 - - -;"		\
+	"go 0x01000000"
+
+#define CONFIG_LINUX				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __T2080RDB_H */
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
new file mode 100644
index 0000000..f176253
--- /dev/null
+++ b/include/configs/T4240QDS.h
@@ -0,0 +1,560 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * T4240 QDS board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE4
+
+#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
+#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
+#define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
+#else
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+
+#ifdef	CONFIG_NAND
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
+#endif
+
+#ifdef	CONFIG_SDCARD
+#define	CONFIG_RESET_VECTOR_ADDRESS	0x200FFC
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_START	0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+#endif
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_DDR_ECC
+
+#include "t4qds.h"
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
+#define SPD_EEPROM_ADDRESS4	0x54
+#define SPD_EEPROM_ADDRESS5	0x55
+#define SPD_EEPROM_ADDRESS6	0x56
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE			0xffdf0000
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x83
+#define QIXIS_RST_FORCE_MEM		0x1
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_BRDCFG5			0x55
+#define QIXIS_MUX_SDHC			2
+#define QIXIS_MUX_SDHC_WIDTH8		1
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED	100000	/* I2C speed */
+#define CONFIG_SYS_FSL_I2C2_SPEED	100000	/* I2C2 speed */
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */
+
+#define I2C_MUX_CH_DEFAULT	0x8
+#define I2C_MUX_CH_VOL_MONITOR	0xa
+#define I2C_MUX_CH_VSC3316_FS	0xc
+#define I2C_MUX_CH_VSC3316_BS	0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR		0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
+#define VSC3316_FSM_TX_ADDR	0x70
+#define VSC3316_FSM_RX_ADDR	0x71
+
+/*
+ * RapidIO
+ */
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_BMAN_NUM_PORTALS	50
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	50
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#define FM1_10GEC1_PHY_ADDR	0x0
+#define FM1_10GEC2_PHY_ADDR	0x1
+#define FM2_10GEC1_PHY_ADDR	0x2
+#define FM2_10GEC2_PHY_ADDR	0x3
+#endif
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_ESDHC_DETECT_QUIRK \
+	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
+	IS_SVR_REV(get_svr(), 1, 0))
+#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
+	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
+#endif
+
+
+#define __USB_PHY_TYPE	utmi
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_ARCH_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t4240qds/ramdisk.uboot\0"			\
+	"fdtaddr=1e00000\0"					\
+	"fdtfile=t4240qds/t4240qds.dtb\0"				\
+	"bdev=sda3\0"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x01000000 - - -;"		\
+	"cpu 2 release 0x01000000 - - -;"		\
+	"cpu 3 release 0x01000000 - - -;"		\
+	"cpu 4 release 0x01000000 - - -;"		\
+	"cpu 5 release 0x01000000 - - -;"		\
+	"cpu 6 release 0x01000000 - - -;"		\
+	"cpu 7 release 0x01000000 - - -;"		\
+	"go 0x01000000"
+
+#define CONFIG_LINUX				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
new file mode 100644
index 0000000..57d8d17
--- /dev/null
+++ b/include/configs/T4240RDB.h
@@ -0,0 +1,696 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * T4240 RDB board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE4
+
+#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
+#ifndef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
+#else
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+
+#ifdef	CONFIG_SDCARD
+#define CONFIG_RESET_VECTOR_ADDRESS	0x200FFC
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_START	0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+#endif
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#define CONFIG_DDR_ECC
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB			/* toggle branch predition */
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		(512 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_DDR_SPD
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#endif
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+
+#ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_HVBOOT					\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_DDR_CLK_FREQ	133333333
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x52
+#define SPD_EEPROM_ADDRESS2	0x54
+#define SPD_EEPROM_ADDRESS3	0x56
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
+				| CSOR_NAND_PB(128))	/*Page Per Block = 128*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE	0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CSOR3	0x0
+
+/* CPLD Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED	100000	/* I2C speed */
+#define CONFIG_SYS_FSL_I2C2_SPEED	100000	/* I2C2 speed */
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */
+
+#define I2C_MUX_CH_DEFAULT	0x8
+#define I2C_MUX_CH_VOL_MONITOR	0xa
+#define I2C_MUX_CH_VSC3316_FS	0xc
+#define I2C_MUX_CH_VSC3316_BS	0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR		0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+
+#define CONFIG_VID_FLS_ENV		"t4240rdb_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_IR36021_READ
+/* The lowest and highest voltage allowed for T4240RDB */
+#define VDD_MV_MIN			819
+#define VDD_MV_MAX			1212
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_BMAN_NUM_PORTALS	50
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	50
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_CORTINA
+#define CONFIG_SYS_CORTINA_FW_IN_NOR
+#define CONFIG_CORTINA_FW_ADDR		0xefe00000
+#define CONFIG_CORTINA_FW_LENGTH	0x40000
+#define CONFIG_PHY_TERANETICS
+#define SGMII_PHY_ADDR1 0x0
+#define SGMII_PHY_ADDR2 0x1
+#define SGMII_PHY_ADDR3 0x2
+#define SGMII_PHY_ADDR4 0x3
+#define SGMII_PHY_ADDR5 0x4
+#define SGMII_PHY_ADDR6 0x5
+#define SGMII_PHY_ADDR7 0x6
+#define SGMII_PHY_ADDR8 0x7
+#define FM1_10GEC1_PHY_ADDR	0x10
+#define FM1_10GEC2_PHY_ADDR	0x11
+#define FM2_10GEC1_PHY_ADDR	0x12
+#define FM2_10GEC2_PHY_ADDR	0x13
+#define CORTINA_PHY_ADDR1	FM1_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR2	FM1_10GEC2_PHY_ADDR
+#define CORTINA_PHY_ADDR3	FM2_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR4	FM2_10GEC2_PHY_ADDR
+#endif
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+
+#define __USB_PHY_TYPE	utmi
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_ARCH_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t4240rdb/ramdisk.uboot\0"			\
+	"fdtaddr=1e00000\0"					\
+	"fdtfile=t4240rdb/t4240rdb.dtb\0"			\
+	"bdev=sda3\0"
+
+#define CONFIG_HVBOOT					\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_LINUX					\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
new file mode 100644
index 0000000..9bf5d9d
--- /dev/null
+++ b/include/configs/TQM834x.h
@@ -0,0 +1,288 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * TQM8349 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+
+/* board pre init: do not call, nothing to do */
+
+/* detect the number of flash banks */
+
+/*
+ * DDR Setup
+ */
+				/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define DDR_CASLAT_25		/* CASLAT set to 2.5 */
+#undef CONFIG_DDR_ECC		/* only for ECC DDR module */
+#undef CONFIG_SPD_EEPROM	/* do not use SPD EEPROM for DDR setup */
+
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * FLASH on the Local Bus
+ */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_BASE		0x80000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8		/* FLASH size in MB */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sectors */
+
+/*
+ * FLASH bank number detection
+ */
+
+/*
+ * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
+ * Flash banks has to be determined at runtime and stored in a gloabl variable
+ * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
+ * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
+ * flash_info, and should be made sufficiently large to accomodate the number
+ * of banks that might actually be detected.  Since most (all?) Flash related
+ * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
+ * the board, it is defined as tqm834x_num_flash_banks.
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	2
+
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */
+
+
+/* disable remaining mappings */
+#define CONFIG_SYS_BR1_PRELIM		0x00000000
+#define CONFIG_SYS_OR1_PRELIM		0x00000000
+
+#define CONFIG_SYS_BR2_PRELIM		0x00000000
+#define CONFIG_SYS_OR2_PRELIM		0x00000000
+
+#define CONFIG_SYS_BR3_PRELIM		0x00000000
+#define CONFIG_SYS_OR3_PRELIM		0x00000000
+
+/*
+ * Monitor config
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
+#else
+# undef  CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+				/* Reserve 384 kB = 3 sect. for Mon */
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)
+				/* Reserve 512 kB for malloc */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+
+/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16 bit */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes/write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20% */
+
+/* I2C RTC */
+#define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68 */
+
+/*
+ * TSEC
+ */
+
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+/* PCI1 host bridge */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	\
+			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE		0x1000000	/* 16M */
+
+#undef CONFIG_EEPRO100
+#define CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BASE
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_MEM_BASE
+	#define PCI_IDSEL_NUMBER	0x1c    /* slot0 (IDSEL) = 28 */
+#endif
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000	/*  32K max size */
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO		1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH	0
+#define CONFIG_SYS_SICRL	SICRL_LDP_A
+
+/* PCI */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		400000
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=tqm834x\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"flash_nfs_old=run nfsargs addip addcons;"			\
+		"bootm ${kernel_addr}\0"				\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self_old=run ramargs addip addcons;"			\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs_old=tftp 400000 ${bootfile};"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addcons; "				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=tqm834x/uImage\0"					\
+	"fdtfile=tqm834x/tqm834x.dtb\0"					\
+	"kernel_addr_r=400000\0"					\
+	"fdt_addr_r=600000\0"						\
+	"ramdisk_addr_r=800000\0"					\
+	"kernel_addr=800C0000\0"					\
+	"fdt_addr=800A0000\0"						\
+	"ramdisk_addr=80300000\0"					\
+	"u-boot=tqm834x/u-boot.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=protect off 80000000 +${filesize};"			\
+		"era 80000000 +${filesize};"				\
+		"cp.b 200000 80000000 ${filesize}\0"			\
+	"upd=run load update\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * JFFS2 partitions
+ */
+/* mtdparts command line support */
+
+/* default mtd partition table */
+#endif	/* __CONFIG_H */
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
new file mode 100644
index 0000000..6a01a90
--- /dev/null
+++ b/include/configs/UCP1020.h
@@ -0,0 +1,883 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2019 Arcturus Networks, Inc.
+ *           https://www.arcturusnetworks.com/products/ucp1020/
+ * based on include/configs/p1_p2_rdb_pc.h
+ * original copyright follows:
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * QorIQ uCP1020-xx boards configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*** Arcturus FirmWare Environment */
+
+#define MAX_SERIAL_SIZE 15
+#define MAX_HWADDR_SIZE 17
+
+#define MAX_FWENV_ADDR	4
+
+#define FWENV_MMC	1
+#define FWENV_SPI_FLASH	2
+#define FWENV_NOR_FLASH	3
+/*
+ #define FWENV_TYPE    FWENV_MMC
+ #define FWENV_TYPE    FWENV_SPI_FLASH
+*/
+#define FWENV_TYPE	FWENV_NOR_FLASH
+
+#if (FWENV_TYPE == FWENV_MMC)
+#ifndef CONFIG_SYS_MMC_ENV_DEV
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#endif
+#define FWENV_ADDR1 -1
+#define FWENV_ADDR2 -1
+#define FWENV_ADDR3 -1
+#define FWENV_ADDR4 -1
+#define EMPY_CHAR 0
+#endif
+
+#if (FWENV_TYPE == FWENV_SPI_FLASH)
+#ifndef CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_SF_DEFAULT_SPEED	1000000
+#endif
+#ifndef CONFIG_SF_DEFAULT_MODE
+#define CONFIG_SF_DEFAULT_MODE	SPI_MODE0
+#endif
+#ifndef CONFIG_SF_DEFAULT_CS
+#define CONFIG_SF_DEFAULT_CS	0
+#endif
+#ifndef CONFIG_SF_DEFAULT_BUS
+#define CONFIG_SF_DEFAULT_BUS	0
+#endif
+#define FWENV_ADDR1 (0x200 - sizeof(smac))
+#define FWENV_ADDR2 (0x400 - sizeof(smac))
+#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
+#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
+#define EMPY_CHAR 0xff
+#endif
+
+#if (FWENV_TYPE == FWENV_NOR_FLASH)
+#define FWENV_ADDR1 0xEC080000
+#define FWENV_ADDR2 -1
+#define FWENV_ADDR3 -1
+#define FWENV_ADDR4 -1
+#define EMPY_CHAR 0xff
+#endif
+/***********************************/
+
+#define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+
+#if defined(CONFIG_TARTGET_UCP1020T1)
+
+#define CONFIG_UCP1020_REV_1_3
+
+#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
+
+#define CONFIG_TSEC1
+#define CONFIG_TSEC3
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETHADDR		00:19:D3:FF:FF:FF
+#define CONFIG_ETH1ADDR		00:19:D3:FF:FF:FE
+#define CONFIG_ETH2ADDR		00:19:D3:FF:FF:FD
+#define CONFIG_IPADDR		10.80.41.229
+#define CONFIG_SERVERIP		10.80.41.227
+#define CONFIG_NETMASK		255.255.252.0
+#define CONFIG_ETHPRIME		"eTSEC3"
+
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+
+#endif
+
+#if defined(CONFIG_TARGET_UCP1020)
+
+#define CONFIG_UCP1020
+#define CONFIG_UCP1020_REV_1_3
+
+#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
+
+#define CONFIG_TSEC1
+#define CONFIG_TSEC3
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETHADDR		00:06:3B:FF:FF:FF
+#define CONFIG_ETH1ADDR		00:06:3B:FF:FF:FE
+#define CONFIG_ETH2ADDR		00:06:3B:FF:FF:FD
+#define CONFIG_IPADDR		192.168.1.81
+#define CONFIG_IPADDR1		192.168.1.82
+#define CONFIG_IPADDR2		192.168.1.83
+#define CONFIG_SERVERIP		192.168.1.80
+#define CONFIG_GATEWAYIP	102.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#undef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#endif
+
+#define CONFIG_SYS_TEXT_BASE_NOR	0xeff80000
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_LBA48
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_DDR_CLK_FREQ	66666666
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
+       SPL code*/
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_DDR_ECC_ENABLE
+#ifndef CONFIG_DDR_ECC_ENABLE
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_DDR_SPD
+#endif
+#define CONFIG_SYS_SPD_BUS_NUM 1
+
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_512M
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+/* Default settings for DDR3 */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655A608
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#ifdef CONFIG_DDR_ECC_ENABLE
+#define CONFIG_SYS_DDR_CONTROL		0xE70C0000	/* Type = DDR3 & ECC */
+#else
+#define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3 */
+#endif
+#define CONFIG_SYS_DDR_CONTROL_2	0x04401050
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00330004
+#define CONFIG_SYS_DDR_TIMING_1		0x6f6B4846
+#define CONFIG_SYS_DDR_TIMING_2		0x0FA8C8CF
+#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
+#define CONFIG_SYS_DDR_MODE_1		0x40461520
+#define CONFIG_SYS_DDR_MODE_2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL		0x0C300000
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x7fff_ffff	DDR		Up to 2GB cacheable
+ * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1G non-cacheable(PCIe * 2)
+ * 0xec00_0000 0xefff_ffff	NOR flash	Up to 64M non-cacheable	CS0/1
+ * 0xf8f8_0000 0xf8ff_ffff	L2 SRAM		Up to 256K cacheable
+ *   (early boot only)
+ * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
+ * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K cacheable
+ * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
+#define CONFIG_SYS_FLASH_BASE		0xec000000
+
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+	| BR_PS_16 | BR_V)
+
+#define CONFIG_FLASH_OR_PRELIM		0xfc000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
+/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+/* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
+
+#define CONFIG_SYS_PMC_BASE	0xff980000
+#define CONFIG_SYS_PMC_BASE_PHYS	CONFIG_SYS_PMC_BASE
+#define CONFIG_PMC_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
+					BR_PS_8 | BR_V)
+#define CONFIG_PMC_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
+				 OR_GPCM_EAD)
+
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+#define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
+
+#define CONFIG_RTC_DS1337
+#define CONFIG_RTC_DS1337_NOOSC
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
+#define CONFIG_SYS_I2C_NCT72_ADDR	0x4C
+#define CONFIG_SYS_I2C_IDT6V49205B	0x69
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT CON9"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"PCIe SLOT CON10"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#endif /* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_ENV_FIT_UCBOOT
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x20000)
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+
+#else
+
+
+#ifdef CONFIG_RAMBOOT_SPIFLASH
+
+#define CONFIG_ENV_SIZE		0x3000		/* 12KB */
+#define CONFIG_ENV_OFFSET	0x2000		/* 8KB */
+#define CONFIG_ENV_SECT_SIZE	0x1000
+
+#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#endif
+
+#elif defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+
+#else
+#define CONFIG_ENV_BASE		(CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR		(CONFIG_ENV_BASE + 0xC0000)
+#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+#endif
+
+#endif
+
+#endif	/* CONFIG_ENV_FIT_UCBOOT */
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#endif
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+/* Misc Extra Settings */
+#undef CONFIG_WATCHDOG	/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms tick */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
+#else
+#error "UCP1020 module revision is not defined !!!"
+#endif
+
+#define CONFIG_BOOTP_SERVERIP
+
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR	4
+#define TSEC2_PHY_ADDR	0
+#define TSEC2_PHY_ADDR_SGMII	0x00
+#define TSEC3_PHY_ADDR	6
+
+#define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX	0
+#define TSEC2_PHYIDX	0
+#define TSEC3_PHYIDX	0
+
+#endif
+
+#define CONFIG_HOSTNAME		"UCP1020"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#if defined(CONFIG_DONGLE)
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+"bootcmd=run prog_spi_mbrbootcramfs\0"					\
+"bootfile=uImage\0"							\
+"consoledev=ttyS0\0"							\
+"cramfsfile=image.cramfs\0"						\
+"dtbaddr=0x00c00000\0"							\
+"dtbfile=image.dtb\0"							\
+"ethaddr=" __stringify(CONFIG_ETHADDR) "\0"				\
+"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"				\
+"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"				\
+"fileaddr=0x01000000\0"							\
+"filesize=0x00080000\0"							\
+"flashmbr=sf probe 0; "							\
+	"tftp $loadaddr $mbr; "						\
+	"sf erase $mbr_offset +$filesize; "				\
+	"sf write $loadaddr $mbr_offset $filesize\0"			\
+"flashrecovery=tftp $recoveryaddr $cramfsfile; "			\
+	"protect off $nor_recoveryaddr +$filesize; "			\
+	"erase $nor_recoveryaddr +$filesize; "				\
+	"cp.b $recoveryaddr $nor_recoveryaddr $filesize; "		\
+	"protect on $nor_recoveryaddr +$filesize\0 "			\
+"flashuboot=tftp $ubootaddr $ubootfile; "				\
+	"protect off $nor_ubootaddr +$filesize; "			\
+	"erase $nor_ubootaddr +$filesize; "				\
+	"cp.b $ubootaddr $nor_ubootaddr $filesize; "			\
+	"protect on $nor_ubootaddr +$filesize\0 "			\
+"flashworking=tftp $workingaddr $cramfsfile; "				\
+	"protect off $nor_workingaddr +$filesize; "			\
+	"erase $nor_workingaddr +$filesize; "				\
+	"cp.b $workingaddr $nor_workingaddr $filesize; "		\
+	"protect on $nor_workingaddr +$filesize\0 "			\
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "				\
+"kerneladdr=0x01100000\0"						\
+"kernelfile=uImage\0"							\
+"loadaddr=0x01000000\0"							\
+"mbr=uCP1020d.mbr\0"							\
+"mbr_offset=0x00000000\0"						\
+"mmbr=uCP1020Quiet.mbr\0"						\
+"mmcpart=0:2\0"								\
+"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; "			\
+	"mmc erase 1 1; "						\
+	"mmc write $loadaddr 1 1\0"					\
+"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; "		\
+	"mmc erase 0x40 0x400; "					\
+	"mmc write $loadaddr 0x40 0x400\0"				\
+"netdev=eth0\0"								\
+"nor_recoveryaddr=0xEC0A0000\0"						\
+"nor_ubootaddr=0xEFF80000\0"						\
+"nor_workingaddr=0xECFA0000\0"						\
+"norbootrecovery=setenv bootargs $recoverybootargs"			\
+	" console=$consoledev,$baudrate $othbootargs; "			\
+	"run norloadrecovery; "						\
+	"bootm $kerneladdr - $dtbaddr\0"				\
+"norbootworking=setenv bootargs $workingbootargs"			\
+	" console=$consoledev,$baudrate $othbootargs; "			\
+	"run norloadworking; "						\
+	"bootm $kerneladdr - $dtbaddr\0"				\
+"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; "			\
+	"setenv cramfsaddr $nor_recoveryaddr; "				\
+	"cramfsload $dtbaddr $dtbfile; "				\
+	"cramfsload $kerneladdr $kernelfile\0"				\
+"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; "			\
+	"setenv cramfsaddr $nor_workingaddr; "				\
+	"cramfsload $dtbaddr $dtbfile; "				\
+	"cramfsload $kerneladdr $kernelfile\0"				\
+"prog_spi_mbr=run spi__mbr\0"						\
+"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0"	\
+"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; "	\
+	"run spi__cramfs\0"						\
+"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"	\
+	" console=$consoledev,$baudrate $othbootargs; "			\
+	"tftp $rootfsaddr $rootfsfile; "				\
+	"tftp $loadaddr $kernelfile; "					\
+	"tftp $dtbaddr $dtbfile; "					\
+	"bootm $loadaddr $rootfsaddr $dtbaddr\0"			\
+"ramdisk_size=120000\0"							\
+"ramdiskfile=rootfs.ext2.gz.uboot\0"					\
+"recoveryaddr=0x02F00000\0"						\
+"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0"		\
+"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "	\
+	"mw.l 0xffe0f008 0x00400000\0"					\
+"rootfsaddr=0x02F00000\0"						\
+"rootfsfile=rootfs.ext2.gz.uboot\0"					\
+"rootpath=/opt/nfsroot\0"						\
+"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; "		\
+	"protect off 0xeC000000 +$filesize; "				\
+	"erase 0xEC000000 +$filesize; "					\
+	"cp.b $loadaddr 0xEC000000 $filesize; "				\
+	"cmp.b $loadaddr 0xEC000000 $filesize; "			\
+	"protect on 0xeC000000 +$filesize\0"				\
+"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; "		\
+	"protect off 0xeFF80000 +$filesize; "				\
+	"erase 0xEFF80000 +$filesize; "					\
+	"cp.b $loadaddr 0xEFF80000 $filesize; "				\
+	"cmp.b $loadaddr 0xEFF80000 $filesize; "			\
+	"protect on 0xeFF80000 +$filesize\0"				\
+"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; "			\
+	"sf probe 0; sf erase 0x8000 +$filesize; "			\
+	"sf write $loadaddr 0x8000 $filesize\0"				\
+"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; "		\
+	"protect off 0xec0a0000 +$filesize; "				\
+	"erase 0xeC0A0000 +$filesize; "					\
+	"cp.b $loadaddr 0xeC0A0000 $filesize; "				\
+	"protect on 0xec0a0000 +$filesize\0"				\
+"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; "			\
+	"sf probe 1; sf erase 0 +$filesize; "				\
+	"sf write $loadaddr 0 $filesize\0"				\
+"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; "			\
+	"sf probe 0; sf erase 0 +$filesize; "				\
+	"sf write $loadaddr 0 $filesize\0"				\
+"tftpflash=tftpboot $loadaddr $uboot; "					\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
+"uboot= " __stringify(CONFIG_UBOOTPATH) "\0"				\
+"ubootaddr=0x01000000\0"						\
+"ubootfile=u-boot.bin\0"						\
+"ubootd=u-boot4dongle.bin\0"						\
+"upgrade=run flashworking\0"						\
+"usb_phy_type=ulpi\0 "							\
+"workingaddr=0x02F00000\0"						\
+"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
+
+#else
+
+#if defined(CONFIG_UCP1020T1)
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0"	\
+"bootfile=uImage\0"							\
+"consoledev=ttyS0\0"							\
+"cramfsfile=image.cramfs\0"						\
+"dtbaddr=0x00c00000\0"							\
+"dtbfile=image.dtb\0"							\
+"ethaddr=" __stringify(CONFIG_ETHADDR) "\0"				\
+"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"				\
+"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"				\
+"fileaddr=0x01000000\0"							\
+"filesize=0x00080000\0"							\
+"flashmbr=sf probe 0; "							\
+	"tftp $loadaddr $mbr; "						\
+	"sf erase $mbr_offset +$filesize; "				\
+	"sf write $loadaddr $mbr_offset $filesize\0"			\
+"flashrecovery=tftp $recoveryaddr $cramfsfile; "			\
+	"protect off $nor_recoveryaddr +$filesize; "			\
+	"erase $nor_recoveryaddr +$filesize; "				\
+	"cp.b $recoveryaddr $nor_recoveryaddr $filesize; "		\
+	"protect on $nor_recoveryaddr +$filesize\0 "			\
+"flashuboot=tftp $ubootaddr $ubootfile; "				\
+	"protect off $nor_ubootaddr +$filesize; "			\
+	"erase $nor_ubootaddr +$filesize; "				\
+	"cp.b $ubootaddr $nor_ubootaddr $filesize; "			\
+	"protect on $nor_ubootaddr +$filesize\0 "			\
+"flashworking=tftp $workingaddr $cramfsfile; "				\
+	"protect off $nor_workingaddr +$filesize; "			\
+	"erase $nor_workingaddr +$filesize; "				\
+	"cp.b $workingaddr $nor_workingaddr $filesize; "		\
+	"protect on $nor_workingaddr +$filesize\0 "			\
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "				\
+"kerneladdr=0x01100000\0"						\
+"kernelfile=uImage\0"							\
+"loadaddr=0x01000000\0"							\
+"mbr=uCP1020.mbr\0"							\
+"mbr_offset=0x00000000\0"						\
+"netdev=eth0\0"								\
+"nor_recoveryaddr=0xEC0A0000\0"						\
+"nor_ubootaddr=0xEFF80000\0"						\
+"nor_workingaddr=0xECFA0000\0"						\
+"norbootrecovery=setenv bootargs $recoverybootargs"			\
+	" console=$consoledev,$baudrate $othbootargs; "			\
+	"run norloadrecovery; "						\
+	"bootm $kerneladdr - $dtbaddr\0"				\
+"norbootworking=setenv bootargs $workingbootargs"			\
+	" console=$consoledev,$baudrate $othbootargs; "			\
+	"run norloadworking; "						\
+	"bootm $kerneladdr - $dtbaddr\0"				\
+"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; "			\
+	"setenv cramfsaddr $nor_recoveryaddr; "				\
+	"cramfsload $dtbaddr $dtbfile; "				\
+	"cramfsload $kerneladdr $kernelfile\0"				\
+"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; "			\
+	"setenv cramfsaddr $nor_workingaddr; "				\
+	"cramfsload $dtbaddr $dtbfile; "				\
+	"cramfsload $kerneladdr $kernelfile\0"				\
+"othbootargs=quiet\0"							\
+"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"	\
+	" console=$consoledev,$baudrate $othbootargs; "			\
+	"tftp $rootfsaddr $rootfsfile; "				\
+	"tftp $loadaddr $kernelfile; "					\
+	"tftp $dtbaddr $dtbfile; "					\
+	"bootm $loadaddr $rootfsaddr $dtbaddr\0"			\
+"ramdisk_size=120000\0"							\
+"ramdiskfile=rootfs.ext2.gz.uboot\0"					\
+"recoveryaddr=0x02F00000\0"						\
+"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0"		\
+"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "	\
+	"mw.l 0xffe0f008 0x00400000\0"					\
+"rootfsaddr=0x02F00000\0"						\
+"rootfsfile=rootfs.ext2.gz.uboot\0"					\
+"rootpath=/opt/nfsroot\0"						\
+"silent=1\0"								\
+"tftpflash=tftpboot $loadaddr $uboot; "					\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
+"uboot= " __stringify(CONFIG_UBOOTPATH) "\0"				\
+"ubootaddr=0x01000000\0"						\
+"ubootfile=u-boot.bin\0"						\
+"upgrade=run flashworking\0"						\
+"workingaddr=0x02F00000\0"						\
+"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
+
+#else /* For Arcturus Modules */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+"bootcmd=run norkernel\0"						\
+"bootfile=uImage\0"							\
+"consoledev=ttyS0\0"							\
+"dtbaddr=0x00c00000\0"							\
+"dtbfile=image.dtb\0"							\
+"ethaddr=" __stringify(CONFIG_ETHADDR) "\0"				\
+"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"				\
+"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"				\
+"fileaddr=0x01000000\0"							\
+"filesize=0x00080000\0"							\
+"flashmbr=sf probe 0; "							\
+	"tftp $loadaddr $mbr; "						\
+	"sf erase $mbr_offset +$filesize; "				\
+	"sf write $loadaddr $mbr_offset $filesize\0"			\
+"flashuboot=tftp $loadaddr $ubootfile; "				\
+	"protect off $nor_ubootaddr0 +$filesize; "			\
+	"erase $nor_ubootaddr0 +$filesize; "				\
+	"cp.b $loadaddr $nor_ubootaddr0 $filesize; "			\
+	"protect on $nor_ubootaddr0 +$filesize; "			\
+	"protect off $nor_ubootaddr1 +$filesize; "			\
+	"erase $nor_ubootaddr1 +$filesize; "				\
+	"cp.b $loadaddr $nor_ubootaddr1 $filesize; "			\
+	"protect on $nor_ubootaddr1 +$filesize\0 "			\
+"format0=protect off $part0base +$part0size; "				\
+	"erase $part0base +$part0size\0"				\
+"format1=protect off $part1base +$part1size; "				\
+	"erase $part1base +$part1size\0"				\
+"format2=protect off $part2base +$part2size; "				\
+	"erase $part2base +$part2size\0"				\
+"format3=protect off $part3base +$part3size; "				\
+	"erase $part3base +$part3size\0"				\
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 "				\
+"kerneladdr=0x01100000\0"						\
+"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"			\
+"kernelfile=uImage\0"							\
+"loadaddr=0x01000000\0"							\
+"mbr=uCP1020.mbr\0"							\
+"mbr_offset=0x00000000\0"						\
+"netdev=eth0\0"								\
+"nor_ubootaddr0=0xEC000000\0"						\
+"nor_ubootaddr1=0xEFF80000\0"						\
+"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; "	\
+	"run norkernelload; "						\
+	"bootm $kerneladdr - $dtbaddr\0"				\
+"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; "			\
+	"setenv cramfsaddr $part0base; "				\
+	"cramfsload $dtbaddr $dtbfile; "				\
+	"cramfsload $kerneladdr $kernelfile\0"				\
+"part0base=0xEC100000\0"						\
+"part0size=0x00700000\0"						\
+"part1base=0xEC800000\0"						\
+"part1size=0x02000000\0"						\
+"part2base=0xEE800000\0"						\
+"part2size=0x00800000\0"						\
+"part3base=0xEF000000\0"						\
+"part3size=0x00F80000\0"						\
+"partENVbase=0xEC080000\0"						\
+"partENVsize=0x00080000\0"						\
+"program0=tftp part0-000000.bin; "					\
+	"protect off $part0base +$filesize; "				\
+	"erase $part0base +$filesize; "					\
+	"cp.b $loadaddr $part0base $filesize; "				\
+	"echo Verifying...; "						\
+	"cmp.b $loadaddr $part0base $filesize\0"			\
+"program1=tftp part1-000000.bin; "					\
+	"protect off $part1base +$filesize; "				\
+	"erase $part1base +$filesize; "					\
+	"cp.b $loadaddr $part1base $filesize; "				\
+	"echo Verifying...; "						\
+	"cmp.b $loadaddr $part1base $filesize\0"			\
+"program2=tftp part2-000000.bin; "					\
+	"protect off $part2base +$filesize; "				\
+	"erase $part2base +$filesize; "					\
+	"cp.b $loadaddr $part2base $filesize; "				\
+	"echo Verifying...; "						\
+	"cmp.b $loadaddr $part2base $filesize\0"			\
+"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro"	\
+	"  console=$consoledev,$baudrate $othbootargs; "		\
+	"tftp $rootfsaddr $rootfsfile; "				\
+	"tftp $loadaddr $kernelfile; "					\
+	"tftp $dtbaddr $dtbfile; "					\
+	"bootm $loadaddr $rootfsaddr $dtbaddr\0"			\
+"ramdisk_size=120000\0"							\
+"ramdiskfile=rootfs.ext2.gz.uboot\0"					\
+"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; "	\
+	"mw.l 0xffe0f008 0x00400000\0"					\
+"rootfsaddr=0x02F00000\0"						\
+"rootfsfile=rootfs.ext2.gz.uboot\0"					\
+"rootpath=/opt/nfsroot\0"						\
+"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; "			\
+	"sf probe 0; sf erase 0 +$filesize; "				\
+	"sf write $loadaddr 0 $filesize\0"				\
+"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; "			\
+	"protect off 0xeC000000 +$filesize; "				\
+	"erase 0xEC000000 +$filesize; "					\
+	"cp.b $loadaddr 0xEC000000 $filesize; "				\
+	"cmp.b $loadaddr 0xEC000000 $filesize; "			\
+	"protect on 0xeC000000 +$filesize\0"				\
+"tftpflash=tftpboot $loadaddr $uboot; "					\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
+"uboot= " __stringify(CONFIG_UBOOTPATH) "\0"				\
+"ubootfile=u-boot.bin\0"						\
+"upgrade=run flashuboot\0"						\
+"usb_phy_type=ulpi\0 "							\
+"boot_nfs= "								\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr\0"					\
+"boot_hd = "								\
+	"setenv bootargs root=/dev/$bdev rw rootdelay=30 "		\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"usb start;"							\
+	"ext2load usb 0:1 $loadaddr /boot/$bootfile;"			\
+	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr\0"					\
+"boot_usb_fat = "							\
+	"setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs "			\
+	"ramdisk_size=$ramdisk_size;"					\
+	"usb start;"							\
+	"fatload usb 0:2 $loadaddr $bootfile;"				\
+	"fatload usb 0:2 $fdtaddr $fdtfile;"				\
+	"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0 "			\
+"boot_usb_ext2 = "							\
+	"setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs "			\
+	"ramdisk_size=$ramdisk_size;"					\
+	"usb start;"							\
+	"ext2load usb 0:4 $loadaddr $bootfile;"				\
+	"ext2load usb 0:4 $fdtaddr $fdtfile;"				\
+	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0 "			\
+"boot_nor = "								\
+	"setenv bootargs root=/dev/$jffs2nor rw "			\
+	"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
+	"bootm $norbootaddr - $norfdtaddr\0 "				\
+"boot_ram = "								\
+	"setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs "			\
+	"ramdisk_size=$ramdisk_size;"					\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"
+
+#endif
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h
new file mode 100644
index 0000000..1fe3391
--- /dev/null
+++ b/include/configs/adp-ae3xx.h
@@ -0,0 +1,223 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch-ae3xx/ae3xx.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SKIP_TRUNOFF_WATCHDOG
+
+#define CONFIG_ARCH_MAP_SYSMEM
+
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SERVERIP
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_OF_CONTROL
+#undef CONFIG_OF_SEPARATE
+#define CONFIG_OF_EMBED
+#endif
+#endif
+
+/*
+ * Timer
+ */
+#define CONFIG_SYS_CLK_FREQ	39062500
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(4*OSC_5MHZ)
+#define RTC_DIV_COUNT			(0.5)	/* Why?? */
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#endif
+#define CONFIG_SYS_NS16550_CLK		((18432000 * 20) / 25)	/* AG101P */
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_0	0x00000000  /* SDRAM Bank #1 */
+
+#define PHYS_SDRAM_1 \
+	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */
+
+#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * FLASH on ADP_AG101P is connected to BANK0
+ * Just disalbe the other BANK to avoid detection error.
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(0x00)
+#define FTSMC020_BANK1_TIMING	(0x00)
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
+
+/* support JEDEC */
+#ifdef CONFIG_CFI_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+#endif
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#define PHYS_FLASH_1			0x88000000	/* BANK 0 */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#endif
+#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* environments */
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x140000
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+
+/* SPI FLASH */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
+/* Increase max gunzip size */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
new file mode 100644
index 0000000..6cf494e
--- /dev/null
+++ b/include/configs/adp-ag101p.h
@@ -0,0 +1,338 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch-ag101/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_ARCH_MAP_SYSMEM
+
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SERVERIP
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_OF_CONTROL
+#undef CONFIG_OF_SEPARATE
+#define CONFIG_OF_EMBED
+#endif
+#endif
+
+/*
+ * Timer
+ */
+#define CONFIG_SYS_CLK_FREQ	39062500
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(4*OSC_5MHZ)
+#define RTC_DIV_COUNT			(0.5)	/* Why?? */
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#endif
+#define CONFIG_SYS_NS16550_CLK		((18432000 * 20) / 25)	/* AG101P */
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRAS(2)	|	\
+					 FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#define CONFIG_SYS_FTSDMC021_BANK1_BASE	\
+	(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
+#define CONFIG_SYS_FTSDMC021_BANK1_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK1_BASE)
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_SDRAM_0	0x00000000  /* SDRAM Bank #1 */
+#else
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_SDRAM_0	0x00000000	/* SDRAM Bank #1 */
+#else
+#define PHYS_SDRAM_0	0x80000000	/* SDRAM Bank #1 */
+#endif
+#endif
+
+#define PHYS_SDRAM_1 \
+	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
+#else
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
+#else
+#define PHYS_SDRAM_0_SIZE	0x08000000	/* 128 MB */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
+#endif
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * FLASH on ADP_AG101P is connected to BANK0
+ * Just disalbe the other BANK to avoid detection error.
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(0x00)
+#define FTSMC020_BANK1_TIMING	(0x00)
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif
+#endif	/* CONFIG_MEM_REMAP */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#endif
+#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* environments */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x140000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
+/* Increase max gunzip size */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h
new file mode 100644
index 0000000..1298859
--- /dev/null
+++ b/include/configs/advantech_dms-ba16.h
@@ -0,0 +1,242 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Timesys Corporation
+ * Copyright (C) 2016 Advantech Corporation
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __ADVANTECH_DMSBA16_CONFIG_H
+#define __ADVANTECH_DMSBA16_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/mach-imx/gpio.h>
+
+#define CONFIG_BOARD_NAME	"Advantech DMS-BA16"
+
+#define CONFIG_MXC_UART_BASE	UART4_BASE
+#define CONSOLE_DEV	"ttymxc3"
+#define CONFIG_EXTRA_BOOTARGS	"panic=10"
+
+#define CONFIG_BOOT_DIR	""
+#define CONFIG_LOADCMD "fatload"
+#define CONFIG_RFSPART "2"
+
+#include "mx6_common.h"
+#include <linux/sizes.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_MXC_UART
+
+/* SATA Configs */
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+/* USB Configs */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+#define CONFIG_USBD_HS
+
+/* Networking Configs */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME		"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		4
+#define CONFIG_PHY_ATHEROS
+
+/* Serial Flash */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_LOADADDR	0x12000000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=" CONFIG_BOOT_DIR "/uImage\0" \
+	"uboot=u-boot.imx\0" \
+	"fdt_file=" CONFIG_BOOT_DIR "/" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=yes\0" \
+	"ip_dyn=yes\0" \
+	"console=" CONSOLE_DEV "\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"initrd_high=0xffffffff\0" \
+	"sddev=0\0" \
+	"emmcdev=1\0" \
+	"partnum=1\0" \
+	"loadcmd=" CONFIG_LOADCMD "\0" \
+	"rfspart=" CONFIG_RFSPART "\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"update_sf_uboot=" \
+		"if tftp $loadaddr $uboot; then " \
+			"sf probe; " \
+			"sf erase 0 0xC0000; " \
+			"sf write $loadaddr 0x400 $filesize; " \
+			"echo 'U-Boot upgraded. Please reset'; " \
+		"fi\0" \
+	"setargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/${rootdev} rw rootwait " CONFIG_EXTRA_BOOTARGS "\0" \
+	"loadbootscript=" \
+		"${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
+		" source\0" \
+	"loadimage=" \
+		"${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
+	"loadfdt=${loadcmd} ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
+	"tryboot=" \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run doboot; " \
+			"fi; " \
+		"fi;\0" \
+	"doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \
+		"run setargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"usb start; " \
+	"setenv dev usb; " \
+	"setenv devnum 0; " \
+	"setenv rootdev sda${rfspart}; " \
+	"run tryboot; " \
+	\
+	"setenv dev mmc; " \
+	"setenv rootdev mmcblk0p${rfspart}; " \
+	\
+	"setenv devnum ${sddev}; " \
+	"if mmc dev ${devnum}; then " \
+		"run tryboot; " \
+	"fi; " \
+	\
+	"setenv devnum ${emmcdev}; " \
+	"setenv rootdev mmcblk${emmcdev}p${rfspart}; " \
+	"if mmc dev ${devnum}; then " \
+		"run tryboot; " \
+	"fi; " \
+	\
+	"bmode usb; " \
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+
+#define CONFIG_ENV_SIZE                 (8 * 1024)
+#define CONFIG_ENV_OFFSET               (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE            (64 * 1024)
+
+#define CONFIG_SYS_FSL_USDHC_NUM        3
+
+/* Framebuffer */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+#define CONFIG_IMX6_PWM_PER_CLK         66000000
+
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO      IMX_GPIO_NR(7, 12)
+#define CONFIG_PCIE_IMX_POWER_GPIO      IMX_GPIO_NR(1, 5)
+#endif
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED            100000
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_MXC_I2C2
+#define CONFIG_SYS_I2C_MXC_I2C3
+
+#endif	/* __ADVANTECH_DMSBA16_CONFIG_H */
diff --git a/include/configs/alt.h b/include/configs/alt.h
new file mode 100644
index 0000000..bb52675
--- /dev/null
+++ b/include/configs/alt.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/configs/alt.h
+ *     This file is alt board configuration.
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ */
+
+#ifndef __ALT_H
+#define __ALT_H
+
+#include "rcar-gen2-common.h"
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
+#define STACK_AREA_SIZE			0x00100000
+#define LOW_LEVEL_MERAM_STACK \
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE		0x40000000
+#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SPI_FLASH_QUAD
+
+/* SH Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK	20000000u
+#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootm_size=0x10000000\0"	\
+	"usb_pgood_delay=2000\0"
+
+/* SPL support */
+#define CONFIG_SPL_STACK		0xe6340000
+#define CONFIG_SPL_MAX_SIZE		0x4000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF2
+#define CONFIG_SH_SCIF_CLK_FREQ		65000000
+#endif
+
+#endif /* __ALT_H */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
new file mode 100644
index 0000000..be57106
--- /dev/null
+++ b/include/configs/am335x_evm.h
@@ -0,0 +1,332 @@
+/*
+ * am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_AM335X_EVM_H
+#define __CONFIG_AM335X_EVM_H
+
+#include <configs/ti_am335x_common.h>
+#include <linux/sizes.h>
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_16M
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_AM335XEVM
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
+		"nand read ${loadaddr} NAND.kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#else
+#define NANDARGS ""
+#endif
+
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"setenv mmcdev " #instance"; "\
+	"setenv bootpart " #instance":2 ; "\
+	"run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel "=" \
+	"run nandboot\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#if CONFIG_IS_ENABLED(CMD_PXE)
+# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_PXE(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_DHCP)
+# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DHCP(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(LEGACY_MMC, legacy_mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(LEGACY_MMC, legacy_mmc, 1) \
+	func(NAND, nand, 0) \
+	BOOT_TARGET_PXE(func) \
+	BOOT_TARGET_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
+#ifndef CONFIG_SPL_BUILD
+#include <environment/ti/dfu.h>
+#include <environment/ti/mmc.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	DEFAULT_MMC_TI_ARGS \
+	DEFAULT_FIT_TI_ARGS \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"fdtfile=undefined\0" \
+	"console=ttyO0,115200n8\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=bootloader,start=384K,size=1792K," \
+			"uuid=${uuid_gpt_bootloader};" \
+		"name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \
+	"optargs=\0" \
+	"ramroot=/dev/ram0 rw\0" \
+	"ramrootfstype=ext2\0" \
+	"spiroot=/dev/mtdblock4 rw\0" \
+	"spirootfstype=jffs2\0" \
+	"spisrcaddr=0xe0000\0" \
+	"spiimgsize=0x362000\0" \
+	"spibusno=0\0" \
+	"spiargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${spiroot} " \
+		"rootfstype=${spirootfstype}\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"spiboot=echo Booting from spi ...; " \
+		"run spiargs; " \
+		"sf probe ${spibusno}:0; " \
+		"sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
+		"bootz ${loadaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+	"findfdt="\
+		"if test $board_name = A335BONE; then " \
+			"setenv fdtfile am335x-bone.dtb; fi; " \
+		"if test $board_name = A335BNLT; then " \
+			"setenv fdtfile am335x-boneblack.dtb; fi; " \
+		"if test $board_name = A335PBGL; then " \
+			"setenv fdtfile am335x-pocketbeagle.dtb; fi; " \
+		"if test $board_name = BBBW; then " \
+			"setenv fdtfile am335x-boneblack-wireless.dtb; fi; " \
+		"if test $board_name = BBG1; then " \
+			"setenv fdtfile am335x-bonegreen.dtb; fi; " \
+		"if test $board_name = BBGW; then " \
+			"setenv fdtfile am335x-bonegreen-wireless.dtb; fi; " \
+		"if test $board_name = BBBL; then " \
+			"setenv fdtfile am335x-boneblue.dtb; fi; " \
+		"if test $board_name = BBEN; then " \
+			"setenv fdtfile am335x-sancloud-bbe.dtb; fi; " \
+		"if test $board_name = A33515BB; then " \
+			"setenv fdtfile am335x-evm.dtb; fi; " \
+		"if test $board_name = A335X_SK; then " \
+			"setenv fdtfile am335x-evmsk.dtb; fi; " \
+		"if test $board_name = A335_ICE; then " \
+			"setenv fdtfile am335x-icev2.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	"init_console=" \
+		"if test $board_name = A335_ICE; then "\
+			"setenv console ttyO3,115200n8;" \
+		"else " \
+			"setenv console ttyO0,115200n8;" \
+		"fi;\0" \
+	NANDARGS \
+	NETARGS \
+	DFUARGS \
+	BOOTENV
+#endif
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
+/* SPL */
+#ifndef CONFIG_NOR_BOOT
+/* Bootcount using the RTC block */
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* USB gadget RNDIS */
+#endif
+
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+/* NAND: driver related configs */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+#endif
+#endif /* !CONFIG_NAND */
+
+/*
+ * For NOR boot, we must set this to the start of where NOR is mapped
+ * in memory.
+ */
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)
+/* Remove other SPL modes. */
+/* disable host part of MUSB in SPL */
+/* disable EFI partitions and partition UUID support */
+#endif
+
+/* USB Device Firmware Update support */
+#ifndef CONFIG_SPL_BUILD
+#define DFUARGS \
+	DFU_ALT_INFO_EMMC \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_NAND
+#endif
+
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x020000 : SPL (128KiB)
+ * 0x020000 - 0x0A0000 : U-Boot (512KiB)
+ * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
+ * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
+ * 0x0E0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+/* SPL related */
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET		(768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND	(896 << 10) /* 896 KiB in */
+#elif defined(CONFIG_EMMC_BOOT)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		0
+#define CONFIG_ENV_OFFSET		0x260000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_SYS_MMC_MAX_DEVICE	2
+#elif defined(CONFIG_NOR_BOOT)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		(512 << 10)	/* 512 KiB */
+#define CONFIG_ENV_OFFSET_REDUND	(768 << 10)	/* 768 KiB */
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OFFSET		0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+
+/* SPI flash. */
+
+/* Network. */
+#define CONFIG_PHY_SMSC
+/* Enable Atheros phy driver */
+#define CONFIG_PHY_ATHEROS
+
+/*
+ * NOR Size = 16 MiB
+ * Number of Sectors/Blocks = 128
+ * Sector Size = 128 KiB
+ * Word length = 16 bits
+ * Default layout:
+ * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
+ * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
+ * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
+ * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
+ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
+ */
+#if defined(CONFIG_NOR)
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BASE		(0x08000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#endif  /* NOR support */
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+#define CONFIG_CLOCK_SYNTHESIZER
+#define CLK_SYNTHESIZER_I2C_ADDR 0x65
+#endif
+
+#endif	/* ! __CONFIG_AM335X_EVM_H */
diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h
new file mode 100644
index 0000000..b45b8d2
--- /dev/null
+++ b/include/configs/am335x_guardian.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * am335x_guardian_.h
+ *
+ * Copyright (C) 2018 Robert Bosch Power Tools GmbH
+ * Copyright (C) 2018 sjoerd Simons <sjoerd.simons@collabora.co.uk>
+ *
+ */
+
+#ifndef __CONFIG_AM335X_GUARDIAN_H
+#define __CONFIG_AM335X_GUARDIAN_H
+
+#include <configs/ti_am335x_common.h>
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_TIMESTAMP
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x80000000\0" \
+	"pxefile_addr_r=0x80100000\0" \
+	"kernel_addr_r=0x82000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"ramdisk_addr_r=0x88080000\0" \
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(UBIFS, ubifs, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#define AM335XX_BOARD_FDTFILE "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	AM335XX_BOARD_FDTFILE \
+	MEM_LAYOUT_ENV_SETTINGS \
+	BOOTENV \
+	"bootlimit=3\0" \
+	"bootubivol=rootfs\0" \
+	"altbootcmd=" \
+		"setenv boot_config \"extlinux-rollback.conf\"; " \
+		"run distro_bootcmd\0"
+
+#endif /* ! CONFIG_SPL_BUILD */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+
+/* Bootcount using the RTC block */
+#define CONFIG_SYS_BOOTCOUNT_LE
+
+#ifdef CONFIG_NAND
+
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
+					CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE       4096
+#define CONFIG_SYS_NAND_OOBSIZE         256
+#define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)
+
+#define CONFIG_SYS_NAND_ECCPOS  {   2,   3,   4,   5,   6,   7,   8,   9, \
+			 10,  11,  12,  13,  14,  15,  16,  17,  18,  19, \
+			 20,  21,  22,  23,  24,  25,  26,  27,  28,  29, \
+			 30,  31,  32,  33,  34,  35,  36,  37,  38,  39, \
+			 40,  41,  42,  43,  44,  45,  46,  47,  48,  49, \
+			 50,  51,  52,  53,  54,  55,  56,  57,  58,  59, \
+			 60,  61,  62,  63,  64,  65,  66,  67,  68,  69, \
+			 70,  71,  72,  73,  74,  75,  76,  77,  78,  79, \
+			 80,  81,  82,  83,  84,  85,  86,  87,  88,  89, \
+			 90,  91,  92,  93,  94,  95,  96,  97,  98,  99, \
+			100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+			110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
+			120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
+			130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
+			140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
+			150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
+			160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
+			170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
+			180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
+			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
+			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
+			}
+#define CONFIG_SYS_NAND_ECCSIZE         512
+#define CONFIG_SYS_NAND_ECCBYTES        26
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH16_CODE_HW
+#define MTDIDS_DEFAULT                  "nand0=nand.0"
+
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
+
+#endif /* CONFIG_NAND */
+
+#endif	/* ! __CONFIG_AM335X_GUARDIAN_H */
diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h
new file mode 100644
index 0000000..5b5e160
--- /dev/null
+++ b/include/configs/am335x_igep003x.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_IGEP003X_H
+#define __CONFIG_IGEP003X_H
+
+#include <configs/ti_am335x_common.h>
+
+/* Clock defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"console=ttyO0,115200n8\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+		"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
+		"load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run mmcload; then " \
+				"run mmcargs; " \
+				"bootz ${loadaddr} - ${fdtaddr};" \
+			"fi;" \
+		"fi;\0" \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=1\0" \
+	"nandrootfstype=ubifs rootwait\0" \
+	"nandload=ubi part UBI; " \
+		"ubi read ${loadaddr} kernel; " \
+		"ubi read ${fdtaddr} dtb \0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} \0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"run nandload; " \
+		"bootz ${loadaddr} - ${fdtaddr} \0" \
+	"netload=tftpboot ${loadaddr} ${bootfile}; " \
+		"tftpboot ${fdtaddr} ${fdtfile} \0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"ip=${ipaddr} nfsroot=${serverip}:${rootnfs},v3,tcp \0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"run netload; " \
+		"bootz ${loadaddr} - ${fdtaddr} \0" \
+	"findfdt="\
+		"if test ${board_name} = igep0033; then " \
+			"setenv fdtfile am335x-igep-base0033.dtb; fi; " \
+		"if test ${board_name} = igep0034; then " \
+			"setenv fdtfile am335x-igep-base0040.dtb; fi; " \
+		"if test ${board_name} = igep0034-lite; then " \
+			"setenv fdtfile am335x-igep-base0040-lite.dtb; fi; " \
+		"if test ${fdtfile} = ''; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt;" \
+	"run mmcboot;" \
+	"run nandboot;" \
+	"run netboot;"
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+
+/* Ethernet support */
+#define CONFIG_PHY_SMSC
+
+/* NAND support */
+#define CONFIG_SYS_NAND_ONFI_DETECTION	1
+
+/* NAND config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+
+#endif	/* ! __CONFIG_IGEP003X_H */
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
new file mode 100644
index 0000000..f4a000f
--- /dev/null
+++ b/include/configs/am335x_shc.h
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef __CONFIG_AM335X_SHC_H
+#define __CONFIG_AM335X_SHC_H
+
+#include <configs/ti_am335x_common.h>
+
+/* settings we don;t want on this board */
+#undef CONFIG_CMD_SPI
+
+#define CONFIG_CMD_CACHE
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+/*
+ * in case of SD Card or Network boot we want to have a possibility to
+ * debrick the shc, therefore do not read environment from eMMC
+ */
+#if defined(CONFIG_SHC_SDBOOT) || defined(CONFIG_SHC_NETBOOT)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#else
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#endif
+
+/*
+ * Info when using boot partitions: As environment resides within first
+ * 128 kB, MLO must start at 128 kB == 0x20000
+ * ENV at MMC Boot0 Partition - 0/Undefined=user, 1=boot0, 2=boot1,
+ * 4..7=general0..3
+ */
+#define CONFIG_ENV_SIZE				0x1000 /* 4 KB */
+#define CONFIG_ENV_OFFSET			0x7000 /* 28 kB */
+
+#define CONFIG_HSMMC2_8BIT
+
+#define CONFIG_ENV_OFFSET_REDUND    0x9000 /* 36 kB */
+#define CONFIG_ENV_SIZE_REDUND      CONFIG_ENV_SIZE
+
+#ifndef CONFIG_SHC_ICT
+/*
+ * In builds other than ICT, reset to retry after timeout
+ * Define a timeout after which a stopped bootloader continues autoboot
+ * (only works with CONFIG_RESET_TO_RETRY)
+ */
+# define CONFIG_BOOT_RETRY_TIME 30
+# define CONFIG_RESET_TO_RETRY
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"kloadaddr=0x84000000\0" \
+	"fdtaddr=0x85000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"rdaddr=0x81000000\0" \
+	"bootfile=uImage\0" \
+	"fdtfile=am335x-shc.dtb\0" \
+	"verify=no\0" \
+	"serverip=10.55.152.184\0" \
+	"rootpath=/srv/nfs/shc-rootfs\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=quiet\0" \
+	"mmcdev=1\0" \
+	"harakiri=0\0" \
+	"mmcpart=2\0" \
+	"active_root=root1\0" \
+	"inactive_root=root2\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"nfsopts=nolock\0" \
+	"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+		"::off\0" \
+	"ip_method=none\0" \
+	"bootargs_defaults=setenv bootargs " \
+		"console=${console} " \
+		"${optargs}\0" \
+	"mmcargs=run bootargs_defaults;" \
+		"setenv bootargs ${bootargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype} ip=${ip_method}\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=if fatload mmc ${mmcdev} ${loadaddr} ${bootenv}; then " \
+			"echo Loaded environment from ${bootenv}; " \
+			"run importbootenv; " \
+		"fi;\0" \
+	"importbootenv=echo Importing environment variables from uEnv.txt ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"loaduimagefat=fatload mmc ${mmcdev} ${kloadaddr} ${bootfile}\0" \
+	"loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${kloadaddr} /boot/${bootfile}\0" \
+	"loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdtaddr} /boot/${fdtfile}\0" \
+	"netloaduimage=tftp ${loadaddr} ${bootfile}\0" \
+	"netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \
+	"mmcboot=echo Booting Linux from ${mmcdevice} ...; " \
+		"run mmcargs; " \
+		"if run loadfdt; then " \
+			"echo device tree detected; " \
+			"bootm ${kloadaddr} - ${fdtaddr}; " \
+		"else " \
+			"bootm ${kloadaddr}; " \
+		"fi; \0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"run netloaduimage; " \
+		"run netargs; " \
+		"echo NFS path: ${serverip}:${rootpath};" \
+		"if run netloadfdt; then " \
+			"echo device tree detected; " \
+			"bootm ${loadaddr} - ${fdtaddr}; " \
+		"else " \
+			"bootm ${loadaddr}; " \
+		"fi; \0" \
+	"emmc_erase=if test ${harakiri} = 1 ; then echo erase emmc ...; setenv mmcdev 1; mmc erase 0 200; reset; fi; \0" \
+	"mmcpart_gp=mmcpart gp 1 40; \0" \
+	"mmcpart_enhance=mmcpart enhance 0 64; \0" \
+	"mmcpart_rel_write=mmcpart rel_write 1f; \0" \
+	"mmcpart_commit=mmcpart commit 1; \0" \
+	"mmc_hw_part=run mmcpart_gp; run mmcpart_enhance; run mmcpart_rel_write; run mmcpart_commit; \0" \
+	"led_success=gpio set 22; \0" \
+	"fusecmd=mmc dev 1; if mmcpart iscommitted; then echo HW Partitioning already committed; mmcpart list; else run mmc_hw_part; fi; run led_success; \0" \
+	"uenv_exec=if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...; " \
+			"run uenvcmd; " \
+		"fi;\0" \
+	"sd_setup=echo SD/MMC-Card detected on device 0; " \
+		"setenv mmcdevice SD; " \
+		"setenv mmcdev 0; " \
+		"setenv mmcpart 2; " \
+		"setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" \
+	"emmc_setup=echo eMMC detected on device 1; " \
+		"setenv mmcdevice eMMC; " \
+		"setenv mmcdev 1; " \
+		"run emmc_erase; " \
+		"if test ${active_root} = root2; then " \
+			"echo Active root is partition 6 (root2); " \
+			"setenv mmcpart 6; " \
+		"else " \
+			"echo Active root is partition 5 (root1); " \
+			"setenv mmcpart 5; " \
+		"fi; " \
+		"setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0"
+#endif /* #ifndef CONFIG_SPL_BUILD */
+
+#if defined CONFIG_SHC_NETBOOT
+/* Network Boot */
+# define CONFIG_BOOTCOMMAND \
+	"run fusecmd; " \
+	"if run netboot; then " \
+		"echo Booting from network; " \
+	"else " \
+		"echo ERROR: Cannot boot from network!; " \
+		"panic; " \
+	"fi; "
+
+#elif defined CONFIG_SHC_SDBOOT /* !defined CONFIG_SHC_NETBOOT */
+/* SD-Card Boot */
+# define CONFIG_BOOTCOMMAND \
+	"if mmc dev 0; mmc rescan; then " \
+		"run sd_setup; " \
+	"else " \
+		"echo ERROR: SD/MMC-Card not detected!; " \
+		"panic; " \
+	"fi; " \
+	"if run loaduimage; then " \
+		"echo Bootable SD/MMC-Card inserted, booting from it!; " \
+		"run mmcboot; " \
+	"else " \
+		"echo ERROR: Unable to load uImage from SD/MMC-Card!; " \
+		"panic; " \
+	"fi; "
+
+#elif defined CONFIG_SHC_ICT
+/* ICT adapter boots only u-boot and does HW partitioning */
+# define CONFIG_BOOTCOMMAND \
+	"if mmc dev 0; mmc rescan; then " \
+		"run sd_setup; " \
+	"else " \
+		"echo ERROR: SD/MMC-Card not detected!; " \
+		"panic; " \
+	"fi; " \
+	"run fusecmd; "
+
+#else /* !defined CONFIG_SHC_NETBOOT, !defined CONFIG_SHC_SDBOOT */
+/* Regular Boot from internal eMMC */
+# define CONFIG_BOOTCOMMAND \
+	"if mmc dev 1; mmc rescan; then " \
+		"run emmc_setup; " \
+	"else " \
+		"echo ERROR: eMMC device not detected!; " \
+		"panic; " \
+	"fi; " \
+	"if run loaduimage; then " \
+		"run mmcboot; " \
+	"else " \
+		"echo ERROR Unable to load uImage from eMMC!; " \
+		"echo Performing Rollback!; " \
+		"setenv _active_ ${active_root}; " \
+		"setenv _inactive_ ${inactive_root}; " \
+		"setenv active_root ${_inactive_}; " \
+		"setenv inactive_root ${_active_}; " \
+		"saveenv; " \
+		"reset; " \
+	"fi; "
+
+#endif /* Regular Boot */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+
+/* SPL */
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#endif
+
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_PHY_SMSC
+
+/* I2C configuration */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		1
+#endif	/* ! __CONFIG_AM335X_SHC_H */
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
new file mode 100644
index 0000000..a08e6bf
--- /dev/null
+++ b/include/configs/am335x_sl50.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * am335x_sl50.h
+ *
+ * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
+ */
+
+#ifndef __CONFIG_AM335X_EVM_H
+#define __CONFIG_AM335X_EVM_H
+
+#include <configs/ti_am335x_common.h>
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+/*#define CONFIG_MACH_TYPE		3589	 Until the next sync */
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#ifndef CONFIG_SPL_BUILD
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x80000000\0" \
+	"pxefile_addr_r=0x80100000\0" \
+	"kernel_addr_r=0x82000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"ramdisk_addr_r=0x88080000\0" \
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1)
+
+#define AM335XX_BOARD_FDTFILE \
+	"fdtfile=am335x-sl50.dtb\0" \
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	AM335XX_BOARD_FDTFILE \
+	MEM_LAYOUT_ENV_SETTINGS \
+	BOOTENV
+
+#endif
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
+/* SPL */
+
+/* Bootcount using the RTC block */
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)
+/* Remove other SPL modes. */
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* disable EFI partitions and partition UUID support */
+#endif
+
+#if defined(CONFIG_EMMC_BOOT)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x0
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* Network. */
+#define CONFIG_PHY_SMSC
+
+#endif	/* ! __CONFIG_AM335X_SL50_H */
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
new file mode 100644
index 0000000..5fa393d
--- /dev/null
+++ b/include/configs/am3517_crane.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * am3517_crane.h - Default configuration for AM3517 CraneBoard.
+ *
+ * Author: Srinath.R <srinath@mistralsolutions.com>
+ *
+ * Based on include/configs/am3517evm.h
+ *
+ * Copyright (C) 2011 Mistral Solutions pvt Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+						/* initial data */
+/*
+ * DDR related
+ */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+/*
+ * USB configuration
+ * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
+ */
+
+#ifdef CONFIG_USB_AM35X
+#ifdef CONFIG_USB_MUSB_UDC
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"AM3517CRANE"
+#endif /* CONFIG_USB_MUSB_UDC */
+
+#endif /* CONFIG_USB_AM35X */
+
+#define CONFIG_SYS_I2C
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"mmcdev=0\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		32	/* max number of command */
+						/* args */
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB sector */
+#define CONFIG_ENV_ADDR			0x260000
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
new file mode 100644
index 0000000..3e5f0b1
--- /dev/null
+++ b/include/configs/am3517_evm.h
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * am3517_evm.h - Default configuration for AM3517 EVM board.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on omap3_evm_config.h
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/ti_omap3_common.h>
+
+#define CONFIG_REVISION_TAG
+
+/* Hardware drivers */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * USB configuration
+ * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard
+ * Enable CONFIG_USB_MUSB_GADGET for Device functionalities.
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_USB_EHCI_OMAP
+#else
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	57
+#endif
+
+/* I2C */
+
+/* Ethernet */
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		10
+
+/* Board NAND Info. */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, 10, \
+					 11, 12, 13, 14, 16, 17, 18, 19, 20, \
+					 21, 22, 23, 24, 25, 26, 27, 28, 30, \
+					 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+					 40, 41, 42, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56 }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	13
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
+/* NAND block size is 128 KiB.  Synchronize these values with
+ * corresponding Device Tree entries in Linux:
+ *  MLO(SPL)             4 * NAND_BLOCK_SIZE = 512 KiB  @ 0x000000
+ *  U-Boot              15 * NAND_BLOCK_SIZE = 1920 KiB @ 0x080000
+ *  U-Boot environment   2 * NAND_BLOCK_SIZE = 256 KiB  @ 0x260000
+ *  Kernel              64 * NAND_BLOCK_SIZE = 8 MiB    @ 0x2A0000
+ *  DTB                  4 * NAND_BLOCK_SIZE = 512 KiB  @ 0xAA0000
+ *  RootFS              Remaining Flash Space           @ 0xB20000
+ */
+#endif /* CONFIG_NAND */
+
+/* Environment information */
+
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"fdtfile=am3517-evm.dtb\0" \
+	"fdtaddr=0x82C00000\0" \
+	"vram=16M\0" \
+	"bootenv=uEnv.txt\0" \
+	"cmdline=\0" \
+	"optargs=\0" \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait fixrtc\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype} " \
+		"${cmdline}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"${optargs} " \
+		"root=ubi0:rootfs rw ubi.mtd=rootfs " \
+		"rootfstype=ubifs rootwait " \
+		"${cmdline}\0" \
+	"loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootenv}\0"\
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootfile}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 2a0000 800000; " \
+		"nand read ${fdtaddr} aa0000 80000; " \
+		"bootm ${loadaddr} - ${fdtaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device $mmcdev; " \
+		"if run loadbootenv; then " \
+			"run importbootenv; " \
+		"fi; " \
+		"echo Checking if uenvcmd is set ...; " \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...; " \
+			"run uenvcmd; " \
+		"fi; " \
+		"echo Running default loadimage ...; " \
+		"setenv bootfile zImage; " \
+		"if run loadimage; then " \
+			"run loadfdt; " \
+			"run mmcboot; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+/* Miscellaneous configurable options */
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS		64
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+/* Physical Memory Map */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/* FLASH and environment organization */
+
+/* **** PISMO SUPPORT *** */
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_ADDR			0x260000
+
+/* Defines for SPL */
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
new file mode 100644
index 0000000..d355b80
--- /dev/null
+++ b/include/configs/am43xx_evm.h
@@ -0,0 +1,278 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * am43xx_evm.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef __CONFIG_AM43XX_EVM_H
+#define __CONFIG_AM43XX_EVM_H
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 21)	/* 2GB */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+
+#include <asm/arch/omap.h>
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_CLK		48000000
+#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_REG_SIZE    (-4)
+#define CONFIG_SYS_NS16550_SERIAL
+#endif
+
+/* I2C Configuration */
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/* Power */
+#ifndef CONFIG_DM_I2C
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#endif
+#define CONFIG_POWER_TPS65218
+#define CONFIG_POWER_TPS62362
+
+/* SPL defines. */
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (128 << 20))
+
+/* Enabling L2 Cache */
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	0x48242000
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * When building U-Boot such that there is no previous loader
+ * we need to call board_early_init_f.  This is taken care of in
+ * s_init when we have SPL used.
+ */
+
+/* Now bring in the rest of the common code. */
+#include <configs/ti_armv7_omap.h>
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+
+/* SPL USB Support */
+
+#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_USB_FAT_BOOT_PARTITION		1
+#define CONFIG_USB_XHCI_OMAP
+
+#define CONFIG_AM437X_USB2PHY2_HOST
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_ETHER)
+#undef CONFIG_USB_DWC3_PHY_OMAP
+#undef CONFIG_USB_DWC3_OMAP
+#undef CONFIG_USB_DWC3
+#undef CONFIG_USB_DWC3_GADGET
+
+#undef CONFIG_USB_GADGET_DOWNLOAD
+#undef CONFIG_USB_GADGET_VBUS_DRAW
+#undef CONFIG_USB_GADGET_MANUFACTURER
+#undef CONFIG_USB_GADGET_VENDOR_NUM
+#undef CONFIG_USB_GADGET_PRODUCT_NUM
+#undef CONFIG_USB_GADGET_DUALSPEED
+#endif
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_TIMER
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/* USB Device Firmware Update support */
+#define DFUARGS \
+	"dfu_bufsiz=0x10000\0" \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_EMMC \
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_QSPI_XIP
+#else
+#define DFUARGS
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND       0x120000
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#include <environment/ti/dfu.h>
+#include <environment/ti/mmc.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	DEFAULT_MMC_TI_ARGS \
+	DEFAULT_FIT_TI_ARGS \
+	"fdtfile=undefined\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"console=ttyO0,115200n8\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+	"optargs=\0" \
+	"usbroot=/dev/sda2 rw\0" \
+	"usbrootfstype=ext4 rootwait\0" \
+	"usbdev=0\0" \
+	"ramroot=/dev/ram0 rw\0" \
+	"ramrootfstype=ext2\0" \
+	"usbargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${usbroot} " \
+		"rootfstype=${usbrootfstype}\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \
+	"usbboot=" \
+		"setenv devnum ${usbdev}; " \
+		"setenv devtype usb; " \
+		"usb start ${usbdev}; " \
+		"if usb dev ${usbdev}; then " \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt; " \
+				"echo Booting from usb ${usbdev}...; " \
+				"run usbargs;" \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"fi;" \
+		"fi\0" \
+		"fi;" \
+		"usb stop ${usbdev};\0" \
+	"findfdt="\
+		"if test $board_name = AM43EPOS; then " \
+			"setenv fdtfile am43x-epos-evm.dtb; fi; " \
+		"if test $board_name = AM43__GP; then " \
+			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+		"if test $board_name = AM43XXHS; then " \
+			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+		"if test $board_name = AM43__SK; then " \
+			"setenv fdtfile am437x-sk-evm.dtb; fi; " \
+		"if test $board_name = AM43_IDK; then " \
+			"setenv fdtfile am437x-idk-evm.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree; fi; \0" \
+	NANDARGS \
+	NETARGS \
+	DFUARGS \
+
+#define CONFIG_BOOTCOMMAND \
+	"if test ${boot_fit} -eq 1; then "	\
+		"run update_to_fit;"	\
+	"fi;"	\
+	"run findfdt; " \
+	"run envboot;" \
+	"run mmcboot;" \
+	"run usbboot;" \
+	NANDBOOT \
+
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/* CPSW Ethernet */
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		10
+#endif
+
+#define PHY_ANEG_TIMEOUT	8000 /* PHY needs longer aneg time at 1G */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	64
+
+/* NAND support */
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_PAGE_SIZE	4096
+#define CONFIG_SYS_NAND_OOBSIZE		224
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH16_CODE_HW
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
+				10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+				20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
+				30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
+				50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+				60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
+				70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+				80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
+				90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
+			100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+			110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
+			120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
+			130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
+			140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
+			150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
+			160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
+			170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
+			180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
+			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
+			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
+			}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	26
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x00180000
+/* NAND: SPL related configs */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00300000 /* kernel offset */
+#endif
+#define NANDARGS \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
+		"nand read ${loadaddr} NAND.kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#define NANDBOOT			"run nandboot; "
+#else /* !CONFIG_NAND */
+#define NANDARGS
+#define NANDBOOT
+#endif /* CONFIG_NAND */
+
+#if defined(CONFIG_TI_SECURE_DEVICE)
+/* Avoid relocating onto firewalled area at end of DRAM */
+#define CONFIG_PRAM (64 * 1024)
+#endif /* CONFIG_TI_SECURE_DEVICE */
+
+#endif	/* __CONFIG_AM43XX_EVM_H */
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
new file mode 100644
index 0000000..531f79e
--- /dev/null
+++ b/include/configs/am57xx_evm.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated.
+ * Felipe Balbi <balbi@ti.com>
+ *
+ * Configuration settings for the TI Beagle x15 board.
+ * See ti_omap5_common.h for omap5 common settings.
+ */
+
+#ifndef __CONFIG_AM57XX_EVM_H
+#define __CONFIG_AM57XX_EVM_H
+
+#include <environment/ti/dfu.h>
+#include <linux/sizes.h>
+
+#define CONFIG_IODELAY_RECALIBRATION
+
+/* MMC ENV related defines */
+#define CONFIG_SYS_MMC_ENV_DEV		1		/* eMMC */
+#define CONFIG_SYS_MMC_ENV_PART		0
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+#define CONSOLEDEV			"ttyS2"
+#define CONFIG_SYS_NS16550_COM1		UART1_BASE	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		UART2_BASE	/* UART2 */
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE	/* UART3 */
+
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+#define CONFIG_SYS_OMAP_ABE_SYSCK
+
+#ifdef CONFIG_SPL_DFU
+#ifndef CONFIG_SPL_BUILD
+#define DFUARGS \
+	"dfu_bufsiz=0x10000\0" \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_EMMC \
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_QSPI
+#else
+#undef CONFIG_CMD_BOOTD
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
+#define DFUARGS \
+	"dfu_bufsiz=0x10000\0" \
+	DFU_ALT_INFO_RAM
+#endif
+#endif
+
+#include <configs/ti_omap5_common.h>
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_HSMMC2_8BIT
+
+/* CPSW Ethernet */
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		10
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs longer aneg time at 1G */
+
+/* USB xHCI HOST */
+#define CONFIG_USB_XHCI_OMAP
+
+#define CONFIG_OMAP_USB3PHY1_HOST
+
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
+ * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
+ * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
+ * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
+ * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
+ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
+ * 0x9E0000 - 0x2000000 : USERLAND
+ */
+#define CONFIG_SYS_SPI_KERNEL_OFFS      0x1E0000
+#define CONFIG_SYS_SPI_ARGS_OFFS        0x140000
+#define CONFIG_SYS_SPI_ARGS_SIZE        0x80000
+
+/* SPI SPL */
+
+#endif /* __CONFIG_AM57XX_EVM_H */
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
new file mode 100644
index 0000000..1149d55
--- /dev/null
+++ b/include/configs/am65x_evm.h
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for K3 AM654 EVM
+ *
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#ifndef __CONFIG_AM654_EVM_H
+#define __CONFIG_AM654_EVM_H
+
+#include <linux/sizes.h>
+#include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
+#include <environment/ti/k3_rproc.h>
+
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+/* DDR Configuration */
+#define CONFIG_SYS_SDRAM_BASE1		0x880000000
+
+/* SPL Loader Configuration */
+#ifdef CONFIG_TARGET_AM654_A53_EVM
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SPL_TEXT_BASE +	\
+					 CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
+#else
+/*
+ * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
+ * possible (to allow the build to go through), as this directly affects
+ * our memory footprint. The less we use for BSS the more we have available
+ * for everything else.
+ */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x5000
+/*
+ * Link BSS to be within SPL in a dedicated region located near the top of
+ * the MCU SRAM, this way making it available also before relocation. Note
+ * that we are not using the actual top of the MCU SRAM as there is a memory
+ * location filled in by the boot ROM that we want to read out without any
+ * interference from the C context.
+ */
+#define CONFIG_SPL_BSS_START_ADDR	(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
+					 CONFIG_SPL_BSS_MAX_SIZE)
+/* Set the stack right below the SPL BSS section */
+#define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_BSS_START_ADDR
+/* Configure R5 SPL post-relocation malloc pool in DDR */
+#define CONFIG_SYS_SPL_MALLOC_START	0x84000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_16M
+#endif
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"tispl.bin"
+#endif
+
+#ifndef CONFIG_CPU_V7R
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+#define PARTS_DEFAULT \
+	/* Linux partitions */ \
+	"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
+
+/* U-Boot general configuration */
+#define EXTRA_ENV_AM65X_BOARD_SETTINGS					\
+	"findfdt="							\
+		"setenv name_fdt k3-am654-base-board.dtb;"		\
+		"setenv fdtfile ${name_fdt}\0"				\
+	"loadaddr=0x80080000\0"						\
+	"fdtaddr=0x82000000\0"						\
+	"overlayaddr=0x83000000\0"					\
+	"name_kern=Image\0"						\
+	"console=ttyS2,115200n8\0"					\
+	"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \
+	"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"		\
+
+/* U-Boot MMC-specific configuration */
+#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC				\
+	"boot=mmc\0"							\
+	"mmcdev=1\0"							\
+	"bootpart=1:2\0"						\
+	"bootdir=/boot\0"						\
+	"rd_spec=-\0"							\
+	"init_mmc=run args_all args_mmc\0"				\
+	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
+	"get_overlay_mmc="						\
+		"fdt address ${fdtaddr};"				\
+		"fdt resize 0x100000;"					\
+		"for overlay in $name_overlays;"			\
+		"do;"							\
+		"load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay};"	\
+		"fdt apply ${overlayaddr};"				\
+		"done;\0"						\
+	"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "		\
+		"${bootdir}/${name_kern}\0"				\
+	"get_fit_mmc=load mmc ${bootpart} ${addr_fit} "			\
+		"${bootdir}/${name_fit}\0"				\
+	"partitions=" PARTS_DEFAULT
+
+#ifdef DEFAULT_RPROCS
+#undef DEFAULT_RPROCS
+#endif
+#define DEFAULT_RPROCS	""						\
+		"0 /lib/firmware/am65x-mcu-r5f0_0-fw "			\
+		"1 /lib/firmware/am65x-mcu-r5f0_1-fw "
+
+/* Incorporate settings into the U-Boot environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	DEFAULT_MMC_TI_ARGS						\
+	DEFAULT_FIT_TI_ARGS						\
+	EXTRA_ENV_AM65X_BOARD_SETTINGS					\
+	EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC				\
+	EXTRA_ENV_RPROC_SETTINGS
+
+/* MMC ENV related defines */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART	1
+#define CONFIG_ENV_SIZE		(128 << 10)
+#define CONFIG_ENV_OFFSET		0x680000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_AM654_EVM_H */
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
new file mode 100644
index 0000000..26d6fef
--- /dev/null
+++ b/include/configs/amcore.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sysam AMCORE board configuration
+ *
+ * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
+ */
+
+#ifndef __AMCORE_CONFIG_H
+#define __AMCORE_CONFIG_H
+
+#define CONFIG_HOSTNAME			"AMCORE"
+
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		0
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTCOMMAND		"bootm ffc20000"
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"upgrade_uboot=loady; "					\
+		"protect off 0xffc00000 0xffc1ffff; "		\
+		"erase 0xffc00000 0xffc1ffff; "			\
+		"cp.b 0x20000 0xffc00000 ${filesize}\0"		\
+	"upgrade_kernel=loady; "				\
+		"erase 0xffc20000 0xffefffff; "			\
+		"cp.b 0x20000 0xffc20000 ${filesize}\0"		\
+	"upgrade_jffs2=loady; "					\
+		"erase 0xfff00000 0xffffffff; "			\
+		"cp.b 0x20000 0xfff00000 ${filesize}\0"
+
+/* undef to save memory	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x20000	/* default load address */
+
+#define CONFIG_SYS_MEMTEST_START	0x0
+#define CONFIG_SYS_MEMTEST_END		0x1000000
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_SYS_CLK			45000000
+#define CONFIG_SYS_CPU_CLK		(CONFIG_SYS_CLK * 2)
+/* Register Base Addrs */
+#define CONFIG_SYS_MBAR			0x10000000
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+/* size of internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		0x1000000
+#define CONFIG_SYS_FLASH_BASE		0xffc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+
+/* amcore design has flash data bytes wired swapped */
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+/* reserve 128-4KB */
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN          ((128 - 4) * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
+
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x1000
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text*);
+
+/* memory map space for linux boot data */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * Cache Configuration
+ *
+ * Special 8K version 3 core cache.
+ * This is a single unified instruction/data cache.
+ * sdram - single region - no masks
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CF_ACR_CM_WT | CF_ACR_SM_ALL | \
+					 CF_ACR_EN)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_DCM_P | CF_CACR_ESB | \
+					 CF_CACR_EC)
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define	CONFIG_SYS_CS0_BASE		(CONFIG_SYS_FLASH_BASE>>16)
+/* 4MB, AA=0,V=1  C/I BIT for errata */
+#define	CONFIG_SYS_CS0_MASK		0x003f0001
+/* WS=10, AA=1, PS=16bit (10) */
+#define	CONFIG_SYS_CS0_CTRL		0x1980
+/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
+#define CONFIG_SYS_CS1_BASE		0x3000
+#define CONFIG_SYS_CS1_MASK		0x00070001
+#define CONFIG_SYS_CS1_CTRL		0x0100
+
+#endif  /* __AMCORE_CONFIG_H */
+
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
new file mode 100644
index 0000000..0e8c3f7
--- /dev/null
+++ b/include/configs/ap121.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_HZ                   1000
+#define CONFIG_SYS_MHZ                  200
+#define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN           0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN       0x20000
+
+#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CONFIG_SYS_LOAD_ADDR            0x81000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x8000
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTCOMMAND              "sf probe;" \
+					"mtdparts default;" \
+					"bootm 0x9f650000"
+
+#define CONFIG_ENV_OFFSET               0x40000
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#define CONFIG_ENV_SIZE                 0x10000
+
+/* Miscellaneous configurable options */
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START        0x80100000
+#define CONFIG_SYS_MEMTEST_END          0x83f00000
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
new file mode 100644
index 0000000..fa69210
--- /dev/null
+++ b/include/configs/ap143.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_HZ                   1000
+#define CONFIG_SYS_MHZ                  325
+#define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN           0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN       0x20000
+
+#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CONFIG_SYS_LOAD_ADDR            0x81000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x2000
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_CLK          25000000
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTCOMMAND              "sf probe;" \
+					"mtdparts default;" \
+					"bootm 0x9f680000"
+
+#define CONFIG_ENV_OFFSET               0x40000
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#define CONFIG_ENV_SIZE                 0x10000
+
+/* Miscellaneous configurable options */
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START        0x80100000
+#define CONFIG_SYS_MEMTEST_END          0x83f00000
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/ap152.h b/include/configs/ap152.h
new file mode 100644
index 0000000..c948a44
--- /dev/null
+++ b/include/configs/ap152.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Rosy Song <rosysong@rosinson.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_HZ                   1000
+#define CONFIG_SYS_MHZ                  375
+#define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN           0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN       0x20000
+
+#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CONFIG_SYS_LOAD_ADDR            0x81000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x2000
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_CLK          25000000
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTCOMMAND              "sf probe;" \
+					"mtdparts default;" \
+					"bootm 0x9f060000"
+
+#define CONFIG_ENV_SPI_MAX_HZ           25000000
+#define CONFIG_ENV_OFFSET               0x40000
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#define CONFIG_ENV_SIZE                 0x10000
+
+/* Miscellaneous configurable options */
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START        0x80100000
+#define CONFIG_SYS_MEMTEST_END          0x83f00000
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
new file mode 100644
index 0000000..3a8d2d4
--- /dev/null
+++ b/include/configs/apalis-imx8.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Toradex
+ */
+
+#ifndef __APALIS_IMX8_H
+#define __APALIS_IMX8_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define USDHC1_BASE_ADDR		0x5b010000
+#define USDHC2_BASE_ADDR		0x5b020000
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Networking */
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_TFTP_TSIZE
+
+#define CONFIG_IPADDR			192.168.10.2
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_SERVERIP			192.168.10.1
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"fdt_addr_r=0x84000000\0" \
+	"kernel_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x94400000\0" \
+	"scriptaddr=0x87000000\0"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
+	MEM_LAYOUT_ENV_SETTINGS \
+	"console=ttyLP1 earlycon\0" \
+	"fdt_addr=0x83000000\0"	\
+	"fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \
+	"fdtfile=fsl-imx8qm-apalis-eval.dtb\0" \
+	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+	"image=Image\0" \
+	"initrd_addr=0x83800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=PARTUUID=${uuid} rootwait " \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
+		"\0" \
+	"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
+		"apalis-imx8/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \
+	"panel=NULL\0" \
+	"script=boot.scr\0" \
+	"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
+		"if test \"$confirm\" = \"y\"; then " \
+		"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
+		"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
+		"${blkcnt}; fi\0"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
+
+#define CONFIG_SYS_MEMTEST_START	0x88000000
+#define CONFIG_SYS_MEMTEST_END		0x89000000
+
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
+					 CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* USDHC1 eMMC */
+#define CONFIG_SYS_MMC_ENV_PART		1
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M /* Increase max gunzip size */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		SZ_2G		/* 2 GB */
+#define PHYS_SDRAM_2_SIZE		SZ_2G		/* 2 GB */
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		SZ_2K
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+#endif /* __APALIS_IMX8_H */
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
new file mode 100644
index 0000000..fe45917
--- /dev/null
+++ b/include/configs/apalis-tk1.h
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex Apalis TK1 modules.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+#define CONFIG_ARCH_MISC_INIT
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define FDT_MODULE			"apalis-v1.2"
+#define FDT_MODULE_V1_0			"apalis"
+
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
+					 CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		1
+
+/* PCI host support */
+#undef CONFIG_PCI_SCAN_SHOW
+
+/* PCI networking support */
+#define CONFIG_E1000_NO_NVM
+
+/* General networking support */
+#define CONFIG_TFTP_TSIZE
+
+#undef CONFIG_IPADDR
+#define CONFIG_IPADDR		192.168.10.2
+#define CONFIG_NETMASK		255.255.255.0
+#undef CONFIG_SERVERIP
+#define CONFIG_SERVERIP		192.168.10.1
+
+#define DFU_ALT_EMMC_INFO	"apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \
+				"boot part 0 1 mmcpart 0; " \
+				"rootfs part 0 2 mmcpart 0; " \
+				"zImage fat 0 1 mmcpart 0; " \
+				"tegra124-apalis-eval.dtb fat 0 1 mmcpart 0"
+
+#define EMMC_BOOTCMD \
+	"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \
+		"ro rootfstype=ext4 rootwait\0" \
+	"emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
+		"setenv bootargs ${defargs} ${emmcargs} " \
+		"${setupargs} ${vidargs}; echo Booting from internal eMMC; " \
+		"run emmcdtbload; " \
+		"load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \
+		"${boot_file} && run fdt_fixup && " \
+		"bootz ${kernel_addr_r} - ${dtbparam}\0" \
+	"emmcbootpart=1\0" \
+	"emmcdev=0\0" \
+	"emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
+		"${fdt_addr_r} ${soc}-${fdt_module}-${fdt_board}.dtb && " \
+		"setenv dtbparam ${fdt_addr_r}\0" \
+	"emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \
+	"emmcrootpart=2\0"
+
+#define NFS_BOOTCMD \
+	"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
+	"nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \
+		"${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
+		"run nfsdtbload; dhcp ${kernel_addr_r} " \
+		"&& run fdt_fixup && bootz ${kernel_addr_r} - ${dtbparam}\0" \
+	"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \
+		"${soc}-${fdt_module}-${fdt_board}.dtb " \
+		"&& setenv dtbparam ${fdt_addr_r}\0"
+
+#define SD_BOOTCMD \
+	"set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} ro " \
+	"rootfstype=ext4 rootwait\0" \
+	"sdboot=run setup; run sdfinduuid; run set_sdargs; " \
+		"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
+		"${vidargs}; echo Booting from SD card in 8bit slot...; " \
+		"run sddtbload; load mmc ${sddev}:${sdbootpart} " \
+		"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
+		"bootz ${kernel_addr_r} - ${dtbparam}\0" \
+	"sdbootpart=1\0" \
+	"sddev=1\0" \
+	"sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
+		"${fdt_addr_r} ${soc}-${fdt_module}-${fdt_board}.dtb " \
+		"&& setenv dtbparam ${fdt_addr_r}\0" \
+	"sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
+	"sdrootpart=2\0"
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+	"boot_file=zImage\0" \
+	"console=ttyS0\0" \
+	"defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \
+		"usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \
+		"user_debug=30 pcie_aspm=off\0" \
+	"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
+	EMMC_BOOTCMD \
+	"fdt_board=eval\0" \
+	"fdt_fixup=;\0" \
+	"fdt_module=" FDT_MODULE "\0" \
+	NFS_BOOTCMD \
+	SD_BOOTCMD \
+	"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
+		"00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \
+		"flash_eth.img && source ${loadaddr}\0" \
+	"setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \
+		"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \
+		"|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1 " \
+		"${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	"setup=setenv setupargs igb_mac=${ethaddr} " \
+		"consoleblank=0 no_console_suspend=1 console=tty1 " \
+		"console=${console},${baudrate}n8 debug_uartport=lsport,0 " \
+		"${memargs}\0" \
+	"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
+	"setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
+		"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	"vidargs=fbcon=map:1\0"
+
+/* Increase console I/O buffer size */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Increase arguments buffer size */
+#undef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Increase maximum number of arguments */
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS		32
+
+#define CONFIG_CMD_TIME
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+/* Reserve top 1M for secure RAM */
+#define CONFIG_ARMV7_SECURE_BASE		0xfff00000
+#define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h
new file mode 100644
index 0000000..a5f9a96
--- /dev/null
+++ b/include/configs/apalis_imx6.h
@@ -0,0 +1,240 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2019 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex Apalis iMX6
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#undef CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE		4886
+
+#include <asm/arch/imx-regs.h>
+#include <asm/mach-imx/gpio.h>
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * 1024 * 1024)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_MXC_I2C3_SPEED	400000
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_LBA48
+#endif
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define PHY_ANEG_TIMEOUT		15000 /* PHY needs longer aneg time */
+#define CONFIG_FEC_MXC_PHYADDR		6
+#define CONFIG_TFTP_TSIZE
+
+/* USB Configs */
+/* Host */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+/* Client */
+#define CONFIG_USBD_HS
+
+/* Framebuffer and LCD */
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition */
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FLASH
+
+#undef CONFIG_IPADDR
+#define CONFIG_IPADDR			192.168.10.2
+#define CONFIG_NETMASK			255.255.255.0
+#undef CONFIG_SERVERIP
+#define CONFIG_SERVERIP			192.168.10.1
+
+#define CONFIG_LOADADDR			0x12000000
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
+#else /* CONFIG_SPL_BUILD */
+#define BOOTENV
+#endif /* CONFIG_SPL_BUILD */
+
+#define DFU_ALT_EMMC_INFO \
+	"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
+	"boot part 0 1;" \
+	"rootfs part 0 2;" \
+	"zImage fat 0 1;" \
+	"imx6q-apalis-eval.dtb fat 0 1;" \
+	"imx6q-apalis-cam-eval.dtb fat 0 1"
+
+#define EMMC_BOOTCMD \
+	"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \
+		"ro,noatime rootfstype=ext4 rootwait\0" \
+	"emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
+		"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
+		"${vidargs}; echo Booting from internal eMMC chip...; "	\
+		"run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \
+		"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
+	"emmcbootpart=1\0" \
+	"emmcdev=0\0" \
+	"emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
+		"${fdt_addr_r} ${fdt_file} && " \
+		"setenv dtbparam \" - ${fdt_addr_r}\" && true\0" \
+	"emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \
+	"emmcrootpart=2\0"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x20000000\0" \
+	"fdt_addr_r=0x12100000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_addr_r=0x11000000\0" \
+	"pxefile_addr_r=0x17100000\0" \
+	"ramdisk_addr_r=0x12200000\0" \
+	"scriptaddr=0x17000000\0"
+
+#define NFS_BOOTCMD \
+	"nfsargs=ip=:::::eth0:on root=/dev/nfs ro\0" \
+	"nfsboot=run setup; " \
+		"setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
+		"${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
+		"run nfsdtbload; dhcp ${kernel_addr_r} " \
+		"&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \
+	"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
+		"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#ifndef CONFIG_TDX_APALIS_IMX6_V1_0
+#define FDT_FILE "imx6q-apalis-eval.dtb"
+#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb"
+#else
+#define FDT_FILE "imx6q-apalis_v1_0-eval.dtb"
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
+	"bootcmd=setenv fdtfile ${fdt_file}; run distro_bootcmd ; " \
+		"usb start ; " \
+		"setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
+	"boot_file=zImage\0" \
+	"console=ttymxc0\0" \
+	"defargs=enable_wait_mode=off vmalloc=400M\0" \
+	"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
+	EMMC_BOOTCMD \
+	"fdt_file=" FDT_FILE "\0" \
+	"fdt_fixup=;\0" \
+	MEM_LAYOUT_ENV_SETTINGS \
+	NFS_BOOTCMD \
+	"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
+		"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
+		"flash_eth.img && source ${loadaddr}\0" \
+	"setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \
+		"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \
+		"|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1" \
+		" ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	"setup=setenv setupargs fec_mac=${ethaddr} " \
+		"consoleblank=0 no_console_suspend=1 console=tty1 " \
+		"console=${console},${baudrate}n8\0 " \
+	"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
+	"setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
+		"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	"splashpos=m,m\0" \
+	"splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+	"vidargs=mxc_hdmi.only_cea=1 " \
+		"video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24 " \
+		"video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \
+		"fbmem=32M\0 "
+
+/* Miscellaneous configurable options */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE		1024
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS		48
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
+					 CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		1
+#endif
+
+#define CONFIG_CMD_TIME
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
new file mode 100644
index 0000000..f6adfeb
--- /dev/null
+++ b/include/configs/apalis_t30.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014-2016 Marcel Ziswiler
+ *
+ * Configuration settings for the Toradex Apalis T30 modules.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra30-common.h"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_APALIS_T30
+
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
+					 CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		1
+
+/* PCI networking support */
+#define CONFIG_E1000_NO_NVM
+
+/* General networking support */
+#define CONFIG_TFTP_TSIZE
+
+/* Increase console I/O buffer size */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Increase arguments buffer size */
+#undef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Increase maximum number of arguments */
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS		32
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
new file mode 100644
index 0000000..044ce44
--- /dev/null
+++ b/include/configs/apf27.h
@@ -0,0 +1,274 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *
+ * Configuration settings for the Armadeus Project motherboard APF27
+ *
+ * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ENV_VERSION	10
+#define CONFIG_BOARD_NAME apf27
+
+/*
+ * SoC configurations
+ */
+#define CONFIG_MX27			/* This is a Freescale i.MX27 Chip */
+#define CONFIG_MACH_TYPE	1698	/* APF27 */
+
+/*
+ * Enable the call to miscellaneous platform dependent initialization.
+ */
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
+#define CONFIG_SPL_MAX_SIZE	2048
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x800
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	CONFIG_SYS_MONITOR_LEN - 0x800
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS2
+
+#define CONFIG_HOSTNAME	"apf27"
+#define CONFIG_ROOTPATH	"/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_POPULATED 1
+
+#define ACFG_SDRAM_MBYTE_SYZE 64
+
+#define PHYS_SDRAM_1			0xA0000000
+#define PHYS_SDRAM_2			0xB0000000
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (512<<10))
+#define CONFIG_SYS_MEMTEST_START	0xA0000000	/* memtest test area  */
+#define CONFIG_SYS_MEMTEST_END		0xA0300000	/* 3 MiB RAM test */
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
+		+ PHYS_SDRAM_1_SIZE - 0x0100000)
+
+/*
+ * FLASH organization
+ */
+#define	ACFG_MONITOR_OFFSET		0x00000000
+#define	CONFIG_SYS_MONITOR_LEN		0x00100000	/* 1MiB */
+#define	CONFIG_ENV_OVERWRITE
+#define	CONFIG_ENV_OFFSET		0x00100000	/* NAND offset */
+#define	CONFIG_ENV_SIZE			0x00020000	/* 128kB  */
+#define CONFIG_ENV_RANGE		0X00080000	/* 512kB */
+#define	CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)	/* +512kB */
+#define	CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE	/* 512kB */
+#define	CONFIG_FIRMWARE_OFFSET		0x00200000
+#define	CONFIG_FIRMWARE_SIZE		0x00080000	/* 512kB  */
+#define	CONFIG_KERNEL_OFFSET		0x00300000
+#define	CONFIG_ROOTFS_OFFSET		0x00800000
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_CBSIZE		2048		/* console I/O buffer */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG		/* send commandline to Kernel	*/
+#define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
+#define CONFIG_INITRD_TAG		/* send initrd params	*/
+
+#define	CONFIG_BOOTFILE		__stringify(CONFIG_BOARD_NAME) "-linux.bin"
+
+#define ACFG_CONSOLE_DEV	ttySMX0
+#define CONFIG_BOOTCOMMAND	"run ubifsboot"
+#define CONFIG_SYS_AUTOLOAD	"no"
+/*
+ * Default load address for user programs and kernel
+ */
+#define CONFIG_LOADADDR			0xA0000000
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"env_version="		__stringify(CONFIG_ENV_VERSION)		"\0" \
+	"consoledev="		__stringify(ACFG_CONSOLE_DEV)		"\0" \
+	"mtdparts="	 	CONFIG_MTDPARTS_DEFAULT	"\0" \
+	"partition=nand0,6\0"						\
+	"u-boot_addr="		__stringify(ACFG_MONITOR_OFFSET)	"\0" \
+	"env_addr="		__stringify(CONFIG_ENV_OFFSET)		"\0" \
+	"firmware_addr="	__stringify(CONFIG_FIRMWARE_OFFSET)	"\0" \
+	"firmware_size="	__stringify(CONFIG_FIRMWARE_SIZE)	"\0" \
+	"kernel_addr="		__stringify(CONFIG_KERNEL_OFFSET)	"\0" \
+	"rootfs_addr="		__stringify(CONFIG_ROOTFS_OFFSET)	"\0" \
+	"board_name="		__stringify(CONFIG_BOARD_NAME)		"\0" \
+	"kernel_addr_r=A0000000\0" \
+	"check_env=if test -n ${flash_env_version}; "			\
+		"then env default env_version; "			\
+		"else env set flash_env_version ${env_version}; env save; "\
+		"fi; "							\
+		"if itest ${flash_env_version} < ${env_version}; then " \
+			"echo \"*** Warning - Environment version"	\
+			" change suggests: run flash_reset_env; reset\"; "\
+			"env default flash_reset_env; "\
+		"fi; \0"						\
+	"check_flash=nand lock; nand unlock ${env_addr}; \0"	\
+	"flash_reset_env=env default -f -a; saveenv; run update_env;"	\
+		"echo Flash environment variables erased!\0"		\
+	"download_uboot=tftpboot ${loadaddr} ${board_name}"		\
+		"-u-boot-with-spl.bin\0"				\
+	"flash_uboot=nand unlock ${u-boot_addr} ;"			\
+		"nand erase.part u-boot;"		\
+		"if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
+			"then nand lock; nand unlock ${env_addr};"	\
+				"echo Flashing of uboot succeed;"	\
+			"else echo Flashing of uboot failed;"		\
+		"fi; \0"						\
+	"update_uboot=run download_uboot flash_uboot\0"			\
+	"download_env=tftpboot ${loadaddr} ${board_name}"		\
+		"-u-boot-env.txt\0"				\
+	"flash_env=env import -t ${loadaddr}; env save; \0"		\
+	"update_env=run download_env flash_env\0"			\
+	"update_all=run update_env update_uboot\0"			\
+	"unlock_regs=mw 10000008 0; mw 10020008 0\0"			\
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/*
+ * NOR
+ */
+
+/*
+ * NAND
+ */
+
+#define CONFIG_MXC_NAND_REGS_BASE	0xD8000000
+#define CONFIG_SYS_NAND_BASE		CONFIG_MXC_NAND_REGS_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	CONFIG_SYS_NAND_BLOCK_SIZE / \
+						CONFIG_SYS_NAND_PAGE_SIZE
+#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	11
+#define NAND_MAX_CHIPS			1
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_NAND_QUIET		1
+
+/*
+ * Partitions & Filsystems
+ */
+
+/*
+ * Ethernet (on SOC imx FEC)
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x1f
+
+/*
+ * FPGA
+ */
+#define CONFIG_FPGA_COUNT		1
+#define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
+#define CONFIG_SYS_FPGA_CHECK_ERROR
+
+/*
+ * Fuses - IIM
+ */
+#ifdef CONFIG_CMD_IMX_FUSE
+#define IIM_MAC_BANK		0
+#define IIM_MAC_ROW		5
+#define IIM0_SCC_KEY		11
+#define IIM1_SUID		1
+#endif
+
+/*
+ * I2C
+ */
+
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_MXC_I2C1_SPEED	100000	/* 100 kHz */
+#define CONFIG_SYS_MXC_I2C1_SLAVE	0x7F
+#define CONFIG_SYS_MXC_I2C2_SPEED	100000	/* 100 kHz */
+#define CONFIG_SYS_MXC_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES		{ }
+
+#ifdef CONFIG_CMD_EEPROM
+# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24LC02 */
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* msec */
+#endif /* CONFIG_CMD_EEPROM */
+#endif /* CONFIG_CMD_I2C */
+
+/*
+ * SD/MMC
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MXC_MCI_REGS_BASE	0x10014000
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1374
+#define CONFIG_SYS_RTC_BUS_NUM		0
+#endif /* CONFIG_CMD_DATE */
+
+/*
+ * PLL
+ *
+ *  31 | x  |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
+ *     |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
+ */
+#define CONFIG_MX27_CLK32		32768	/* 32768 or 32000 Hz crystal */
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
+/* micron 64MB */
+#define PHYS_SDRAM_1_SIZE			0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2_SIZE			0x04000000 /* 64 MB */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 128)
+/* micron 128MB */
+#define PHYS_SDRAM_1_SIZE			0x08000000 /* 128 MB */
+#define PHYS_SDRAM_2_SIZE			0x08000000 /* 128 MB */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 256)
+/* micron 256MB */
+#define PHYS_SDRAM_1_SIZE			0x10000000 /* 256 MB */
+#define PHYS_SDRAM_2_SIZE			0x10000000 /* 256 MB */
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h
new file mode 100644
index 0000000..09de1c0
--- /dev/null
+++ b/include/configs/apx4devkit.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Bluegiga Technologies Oy
+ *
+ * Authors:
+ * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
+ * Lauri Hintsala <lauri.hintsala@bluegiga.com>
+ *
+ * Based on m28evk.h:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+#ifndef __CONFIGS_APX4DEVKIT_H__
+#define __CONFIGS_APX4DEVKIT_H__
+
+/* System configurations */
+#define CONFIG_MACH_TYPE	MACH_TYPE_APX4DEVKIT
+
+/* Memory configuration */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x20000000	/* Max 512 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(256 * 1024)
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+/* Environment is in NAND */
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_SIZE			(128 * 1024)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_RANGE		(384 * 1024)
+#define CONFIG_ENV_OFFSET		0x120000
+#define CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#endif
+
+/* UBI and NAND partitioning */
+
+/* FEC Ethernet on SoC */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define IMX_FEC_BASE			MXS_ENET0_BASE
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#endif
+
+/* Boot Linux */
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_BOOTCOMMAND		"run bootcmd_nand"
+#define CONFIG_LOADADDR			0x41000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+
+/* Extra Environments */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"verify=no\0" \
+	"bootcmd=run bootcmd_nand\0" \
+	"kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \
+	"bootargs_nand=" \
+		"setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \
+		"root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \
+	"bootcmd_nand=" \
+		"run bootargs_nand && ubi part root 2048 && " \
+		"ubifsmount ubi:rootfs && ubifsload 41000000 boot/uImage && " \
+		"bootm 41000000\0" \
+	"bootargs_mmc=" \
+		"setenv bootargs ${kernelargs} " \
+		"root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \
+	"bootcmd_mmc=" \
+		"run bootargs_mmc && mmc rescan && " \
+		"ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \
+""
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_APX4DEVKIT_H__ */
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
new file mode 100644
index 0000000..e998d9b
--- /dev/null
+++ b/include/configs/aristainetos-common.h
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ */
+#ifndef __ARISTAINETOS_COMMON_CONFIG_H
+#define __ARISTAINETOS_COMMON_CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE	4501
+#define CONFIG_MMCROOT		"/dev/mmcblk0p1"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(64 * SZ_1M)
+
+#define CONFIG_MXC_UART
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0
+
+#define CONFIG_SPI_FLASH_MTD
+#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=u-boot.scr\0" \
+	"fit_file=/boot/system.itb\0" \
+	"loadaddr=0x12000000\0" \
+	"fit_addr_r=0x14000000\0" \
+	"uboot=/boot/u-boot.imx\0" \
+	"uboot_sz=d0000\0" \
+	"rescue_sys_addr=f0000\0" \
+	"rescue_sys_length=f10000\0" \
+	"panel=lb07wv8\0" \
+	"splashpos=m,m\0" \
+	"console=" CONSOLE_DEV "\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"initrd_high=0xffffffff\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \
+		"default ${board_type}\0" \
+	"get_env=mw ${loadaddr} 0 0x20000;" \
+		"mmc rescan;" \
+		"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \
+		"env import -t ${loadaddr}\0" \
+	"default_env=mw ${loadaddr} 0 0x20000;" \
+		"env export -t ${loadaddr} serial# ethaddr eth1addr " \
+		"board_type panel;" \
+		"env default -a;" \
+		"env import -t ${loadaddr}\0" \
+	"loadbootscript=" \
+		"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"mmcpart=1\0" \
+	"mmcdev=0\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs addmtd addmisc set_fit_default;" \
+		"bootm ${fit_addr_r}\0" \
+	"mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
+		"${fit_file}\0" \
+	"mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+		"${uboot}\0" \
+	"mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
+		"setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \
+		"setexpr uboot_maxsize ${uboot_sz} - 400;" \
+		"mw.b ${cmp_buf} 0x00 ${uboot_sz};" \
+		"run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
+		"sf write ${loadaddr} 400 ${filesize};" \
+		"sf read ${cmp_buf} 400 ${uboot_sz};" \
+		"cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \
+	"ubiboot=echo Booting from ubi ...; " \
+		"run ubiargs addmtd addmisc set_fit_default;" \
+		"bootm ${fit_addr_r}\0" \
+	"rescueargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/ram rw\0 " \
+	"rescueboot=echo Booting rescue system from NOR ...; " \
+		"run rescueargs addmtd addmisc set_fit_default;" \
+		"bootm ${fit_addr_r}\0" \
+	"rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \
+		"${rescue_sys_length}; imi ${fit_addr_r}\0" \
+	CONFIG_EXTRA_ENV_BOARD_SETTINGS
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev};" \
+	"if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run mmc_load_fit; then " \
+				"run mmcboot; " \
+			"else " \
+				"if run ubifs_load_fit; then " \
+					"run ubiboot; " \
+				"else " \
+					"if run rescue_load_fit; then " \
+						"run rescueboot; " \
+					"else " \
+						"echo RESCUE SYSTEM BOOT " \
+							"FAILURE;" \
+					"fi; " \
+				"fi; " \
+			"fi; " \
+		"fi; " \
+	"else " \
+		"if run ubifs_load_fit; then " \
+			"run ubiboot; " \
+		"else " \
+			"if run rescue_load_fit; then " \
+				"run rescueboot; " \
+			"else " \
+				"echo RESCUE SYSTEM BOOT FAILURE;" \
+			"fi; " \
+		"fi; " \
+	"fi"
+
+#define CONFIG_ARP_TIMEOUT		200UL
+
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			(12 * 1024)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SECT_SIZE		(0x010000)
+#define CONFIG_ENV_OFFSET		(0x0d0000)
+#define CONFIG_ENV_OFFSET_REDUND	(0x0e0000)
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0x7f
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x00} }
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+
+/* RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_RTC_BUS_NUM	2
+#define CONFIG_RTC_M41T11
+
+/* USB Configs */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+/* UBI support */
+
+/* Framebuffer */
+/* check this console not needed, after test remove it */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+
+#define CONFIG_IMX6_PWM_PER_CLK	66000000
+
+#endif /* __ARISTAINETOS_COMMON_CONFIG_H */
diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h
new file mode 100644
index 0000000..03e2a2b
--- /dev/null
+++ b/include/configs/aristainetos.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ */
+#ifndef __ARISTAINETOS_CONFIG_H
+#define __ARISTAINETOS_CONFIG_H
+
+#define CONFIG_SYS_BOARD_VERSION	1
+#define CONFIG_HOSTNAME		"aristainetos"
+#define CONFIG_BOARDNAME	"aristainetos"
+
+#define CONFIG_MXC_UART_BASE	UART5_BASE
+#define CONSOLE_DEV	"ttymxc4"
+
+#define CONFIG_FEC_XCV_TYPE		RMII
+
+#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
+	"board_type=aristainetos7@1\0" \
+	"mtdids=nand0=gpmi-nand,nor0=spi3.0\0" \
+	"mtdparts=mtdparts=spi3.0:832k(u-boot),64k(env),64k(env-red)," \
+		"-(rescue-system);gpmi-nand:-(ubi)\0" \
+	"addmisc=setenv bootargs ${bootargs} consoleblank=0\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"ubiargs=setenv bootargs console=${console},${baudrate} " \
+		"ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 " \
+	"ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \
+		"ubifsload ${fit_addr_r} /boot/system.itb; " \
+		"imi ${fit_addr_r}\0 "
+
+#define ARISTAINETOS_USB_OTG_PWR	IMX_GPIO_NR(4, 15)
+#define ARISTAINETOS_USB_H1_PWR		IMX_GPIO_NR(3, 31)
+#define CONFIG_GPIO_ENABLE_SPI_FLASH	IMX_GPIO_NR(2, 15)
+
+#include "aristainetos-common.h"
+
+#endif                         /* __ARISTAINETOS_CONFIG_H */
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
new file mode 100644
index 0000000..361e6ac
--- /dev/null
+++ b/include/configs/aristainetos2.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6DL aristainetos2 board.
+ */
+#ifndef __ARISTAINETOS2_CONFIG_H
+#define __ARISTAINETOS2_CONFIG_H
+
+#define CONFIG_SYS_BOARD_VERSION	2
+#define CONFIG_HOSTNAME		"aristainetos2"
+#define CONFIG_BOARDNAME	"aristainetos2"
+
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+#define CONSOLE_DEV	"ttymxc1"
+
+#define CONFIG_FEC_XCV_TYPE		RGMII
+
+#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
+	"board_type=aristainetos2_7@1\0" \
+	"nor_bootdelay=-2\0" \
+	"mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \
+	"mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \
+		"-(rescue-system);gpmi-nand:-(ubi)\0" \
+	"addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \
+	"ubiargs=setenv bootargs console=${console},${baudrate} " \
+		"ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \
+	"ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \
+		"ubifsload ${fit_addr_r} /boot/system.itb; " \
+		"imi ${fit_addr_r}\0 "
+
+#define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */
+
+#define ARISTAINETOS_USB_OTG_PWR	IMX_GPIO_NR(4, 15)
+#define ARISTAINETOS_USB_H1_PWR	IMX_GPIO_NR(1, 0)
+#define CONFIG_GPIO_ENABLE_SPI_FLASH	IMX_GPIO_NR(2, 15)
+
+/* Framebuffer */
+#define CONFIG_SYS_LDB_CLOCK 33246000
+#define CONFIG_LG4573
+#define CONFIG_LG4573_BUS 0
+#define CONFIG_LG4573_CS 0
+
+#include "aristainetos-common.h"
+
+#endif                         /* __ARISTAINETOS2_CONFIG_H */
diff --git a/include/configs/aristainetos2b.h b/include/configs/aristainetos2b.h
new file mode 100644
index 0000000..cdeb7a3
--- /dev/null
+++ b/include/configs/aristainetos2b.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6DL aristainetos2 board.
+ */
+#ifndef __ARISTAINETOS2B_CONFIG_H
+#define __ARISTAINETOS2B_CONFIG_H
+
+#define CONFIG_SYS_BOARD_VERSION	3
+#define CONFIG_HOSTNAME		"aristainetos2"
+#define CONFIG_BOARDNAME	"aristainetos2-revB"
+
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+#define CONSOLE_DEV	"ttymxc1"
+
+#define CONFIG_FEC_XCV_TYPE		RGMII
+
+#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
+	"board_type=aristainetos2_7@1\0" \
+	"nor_bootdelay=-2\0" \
+	"mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \
+	"mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \
+		"-(rescue-system);gpmi-nand:-(ubi)\0" \
+	"addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \
+	"ubiargs=setenv bootargs console=${console},${baudrate} " \
+		"ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \
+	"ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \
+		"ubifsload ${fit_addr_r} /boot/system.itb; " \
+		"imi ${fit_addr_r}\0 " \
+
+#define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */
+
+#define ARISTAINETOS_USB_OTG_PWR	IMX_GPIO_NR(4, 15)
+#define ARISTAINETOS_USB_H1_PWR	IMX_GPIO_NR(1, 0)
+#define CONFIG_GPIO_ENABLE_SPI_FLASH	IMX_GPIO_NR(2, 15)
+
+/* Framebuffer */
+#define CONFIG_SYS_LDB_CLOCK 33246000
+#define CONFIG_LG4573
+#define CONFIG_LG4573_BUS 0
+#define CONFIG_LG4573_CS 1
+
+#include "aristainetos-common.h"
+
+#endif                         /* __ARISTAINETOS2B_CONFIG_H */
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
new file mode 100644
index 0000000..c3cccee
--- /dev/null
+++ b/include/configs/armadillo-800eva.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the bonito board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ */
+
+#ifndef __ARMADILLO_800EVA_H
+#define __ARMADILLO_800EVA_H
+
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define BOARD_LATE_INIT
+
+#define CONFIG_TMU_TIMER
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE		(CONFIG_SYS_CLK_FREQ / 4)
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE8083000
+#define STACK_AREA_SIZE				0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define ARMADILLO_800EVA_SDRAM_BASE	0x40000000
+#define ARMADILLO_800EVA_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_CONS_SCIF1
+#define SCIF0_BASE		0xe6c40000
+#define SCIF1_BASE		0xe6c50000
+#define SCIF2_BASE		0xe6c60000
+#define SCIF4_BASE		0xe6c80000
+#define	CONFIG_SCIF_A
+
+#define CONFIG_SYS_MEMTEST_START	(ARMADILLO_800EVA_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(ARMADILLO_800EVA_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(ARMADILLO_800EVA_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 64 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+
+/* ENV setting */
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* SH Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x0
+#define CONFIG_SH_ETHER_BASE_ADDR	0xe9a00000
+#define CONFIG_SH_ETHER_SH7734_MII	(0x01)
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+#define CONFIG_PHY_SMSC
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	50000000
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+
+#endif	/* __ARMADILLO_800EVA_H */
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
new file mode 100644
index 0000000..8aa6e1d
--- /dev/null
+++ b/include/configs/arndale.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG Arndale board.
+ */
+
+#ifndef __CONFIG_ARNDALE_H
+#define __CONFIG_ARNDALE_H
+
+#define EXYNOS_FDTFILE_SETTING \
+	"fdtfile=exynos5250-arndale.dtb\0"
+
+#include "exynos5250-common.h"
+#include <configs/exynos5-common.h>
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* MMC SPL */
+#define CONFIG_EXYNOS_SPL
+
+/* Miscellaneous configurable options */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
+
+#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+#define CONFIG_IRAM_STACK	0x02050000
+
+#define CONFIG_SYS_INIT_SP_ADDR	CONFIG_IRAM_STACK
+
+#define CONFIG_S5P_PA_SYSRAM	0x02020000
+#define CONFIG_SMP_PEN_ADDR	CONFIG_S5P_PA_SYSRAM
+
+/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
+#define CONFIG_ARM_GIC_BASE_ADDRESS	0x10480000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
new file mode 100644
index 0000000..6815c5f
--- /dev/null
+++ b/include/configs/aspeed-common.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012-2020  ASPEED Technology Inc.
+ * Ryan Chen <ryan_chen@aspeedtech.com>
+ *
+ * Copyright 2016 IBM Corporation
+ * (C) Copyright 2016 Google, Inc
+ */
+
+#ifndef __AST_COMMON_CONFIG_H
+#define __AST_COMMON_CONFIG_H
+
+/* Misc CPU related */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+#ifdef CONFIG_PRE_CON_BUF_SZ
+#define CONFIG_SYS_INIT_RAM_ADDR	(0x1e720000 + CONFIG_PRE_CON_BUF_SZ)
+#define CONFIG_SYS_INIT_RAM_SIZE	(36*1024 - CONFIG_PRE_CON_BUF_SZ)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR	(0x1e720000)
+#define CONFIG_SYS_INIT_RAM_SIZE	(36*1024)
+#endif
+
+#define SYS_INIT_RAM_END		(CONFIG_SYS_INIT_RAM_ADDR \
+					 + CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(SYS_INIT_RAM_END \
+					 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
+
+/*
+ * NS16550 Configuration
+ */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_BOOTCOMMAND		"bootm 20080000 20300000"
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=yes\0"	\
+	"spi_dma=yes\0" \
+	""
+
+#endif	/* __AST_COMMON_CONFIG_H */
diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h
new file mode 100644
index 0000000..79bf8f2
--- /dev/null
+++ b/include/configs/aspenite.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#ifndef __CONFIG_ASPENITE_H
+#define __CONFIG_ASPENITE_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV331xV5	1	/* CPU Core subversion */
+#define CONFIG_ARMADA100		1	/* SOC Family Name */
+#define CONFIG_ARMADA168		1	/* SOC Used on this Board */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * There is no internal RAM in ARMADA100, using DRAM
+ * TBD: dcache to be used for this
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - 0x00200000)
+
+/*
+ * Commands configuration
+ */
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_SIZE	0x20000	/* 64k */
+
+#endif	/* __CONFIG_ASPENITE_H */
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
new file mode 100644
index 0000000..2e7fbfb
--- /dev/null
+++ b/include/configs/astro_mcf5373l.h
@@ -0,0 +1,297 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Sentec Cobra Board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ */
+
+/*
+ * configuration for ASTRO "Urmel" board.
+ * Originating from Cobra5272 configuration, messed up by
+ * Wolfgang Wegner <w.wegner@astro-kom.de>
+ * Please do not bother the original author with bug reports
+ * concerning this file.
+ */
+
+#ifndef _CONFIG_ASTRO_MCF5373L_H
+#define _CONFIG_ASTRO_MCF5373L_H
+
+#include <linux/stringify.h>
+
+/*
+ * set the card type to actually compile for; either of
+ * the possibilities listed below has to be used!
+ */
+#define CONFIG_ASTRO_V532	1
+
+#if CONFIG_ASTRO_V532
+#define ASTRO_ID	0xF8
+#elif CONFIG_ASTRO_V512
+#define ASTRO_ID	0xFA
+#elif CONFIG_ASTRO_TWIN7S2
+#define ASTRO_ID	0xF9
+#elif CONFIG_ASTRO_V912
+#define ASTRO_ID	0xFC
+#elif CONFIG_ASTRO_COFDMDUOS2
+#define ASTRO_ID	0xFB
+#else
+#error No card type defined!
+#endif
+
+/* Command line configuration */
+/*
+ * CONFIG_RAM defines if u-boot is loaded via BDM (or started from
+ * a different bootloader that has already performed RAM setup) or
+ * started directly from flash, which is the regular case for production
+ * boards.
+ */
+#ifdef CONFIG_RAM
+#define CONFIG_MONITOR_IS_IN_RAM
+#define ENABLE_JFFS	0
+#else
+#define ENABLE_JFFS	1
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+/*
+ * Defines processor clock - important for correct timings concerning serial
+ * interface etc.
+ */
+
+#define CONFIG_SYS_CLK			80000000
+#define CONFIG_SYS_CPU_CLK		(CONFIG_SYS_CLK * 3)
+#define CONFIG_SYS_SDRAM_SIZE		32		/* SDRAM size in MB */
+
+#define CONFIG_SYS_CORE_SRAM_SIZE	0x8000
+#define CONFIG_SYS_CORE_SRAM		0x80000000
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+/*
+ * Define baudrate for UART1 (console output, tftp, ...)
+ * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
+ * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
+ * in u-boot command interface
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(2)
+#define CONFIG_SYS_UART2_ALT3_GPIO
+
+/*
+ * Watchdog configuration; Watchdog is disabled for running from RAM
+ * and set to highest possible value else. Beware there is no check
+ * in the watchdog code to validate the timeout value set here!
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 3355	/* timeout in milliseconds */
+#endif
+
+/*
+ * Configuration for environment
+ * Environment is located in the last sector of the flash
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET		0x1FF8000
+#define CONFIG_ENV_SECT_SIZE		0x8000
+#else
+/*
+ * environment in RAM - This is used to use a single PC-based application
+ * to load an image, load U-Boot, load an environment and then start U-Boot
+ * to execute the commands from the environment. Feedback is done via setting
+ * and reading memory locations.
+ */
+#define CONFIG_ENV_ADDR		0x40060000
+#define CONFIG_ENV_SECT_SIZE	0x8000
+#endif
+
+/* here we put our FPGA configuration... */
+
+/* Define user parameters that have to be customized most likely */
+
+/* AUTOBOOT settings - booting images automatically by u-boot after power on */
+
+/*
+ * The following settings will be contained in the environment block ; if you
+ * want to use a neutral environment all those settings can be manually set in
+ * u-boot: 'set' command
+ */
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	"loaderversion=11\0"				\
+	"card_id="__stringify(ASTRO_ID)"\0"			\
+	"alterafile=0\0"				\
+	"xilinxfile=0\0"				\
+	"xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
+		"fpga load 0 0x41000000 $filesize\0" \
+	"alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\
+		"fpga load 1 0x41000000 $filesize\0" \
+	"env_default=1\0"				\
+	"env_check=if test $env_default -eq 1;"\
+		" then setenv env_default 0;saveenv;fi\0"
+
+/*
+ * "update" is a non-standard command that has to be supplied
+ * by external update.c; This is not included in mainline because
+ * it needs non-blocking CFI routines.
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_BOOTCOMMAND	""	/* no autoboot in this case */
+#else
+#if CONFIG_ASTRO_V532
+#define CONFIG_BOOTCOMMAND	"protect off 0x80000 0x1ffffff;run env_check;"\
+				"run xilinxload&&run alteraload&&bootm 0x80000;"\
+				"update;reset"
+#else
+#define CONFIG_BOOTCOMMAND	"protect off 0x80000 0x1ffffff;run env_check;"\
+				"run xilinxload&&bootm 0x80000;update;reset"
+#endif
+#endif
+
+/* default RAM address for user programs */
+#define CONFIG_SYS_LOAD_ADDR	0x20000
+
+#define CONFIG_FPGA_COUNT	1
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_WAIT		1000
+
+/* End of user parameters to be customized */
+
+/* Defines memory range for test */
+
+#define CONFIG_SYS_MEMTEST_START	0x40020000
+#define CONFIG_SYS_MEMTEST_END		0x41ffffff
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/* Base register address */
+
+#define CONFIG_SYS_MBAR		0xFC000000	/* Register Base Addrs */
+
+/* System Conf. Reg. & System Protection Reg. */
+
+#define CONFIG_SYS_SCR		0x0003;
+#define CONFIG_SYS_SPR		0xffff;
+
+/*
+ * Definitions for initial stack pointer and data area (in internal SRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x8000
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+/*
+ * Chipselect bank definitions
+ *
+ * CS0 - Flash 32MB (first 16MB)
+ * CS1 - Flash 32MB (second half)
+ * CS2 - FPGA
+ * CS3 - FPGA
+ * CS4 - unused
+ * CS5 - unused
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x00ff0001
+#define CONFIG_SYS_CS0_CTRL		0x00001fc0
+
+#define CONFIG_SYS_CS1_BASE		0x01000000
+#define CONFIG_SYS_CS1_MASK		0x00ff0001
+#define CONFIG_SYS_CS1_CTRL		0x00001fc0
+
+#define CONFIG_SYS_CS2_BASE		0x20000000
+#define CONFIG_SYS_CS2_MASK		0x00ff0001
+#define CONFIG_SYS_CS2_CTRL		0x0000fec0
+
+#define CONFIG_SYS_CS3_BASE		0x21000000
+#define CONFIG_SYS_CS3_MASK		0x00ff0001
+#define CONFIG_SYS_CS3_CTRL		0x0000fec0
+
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+
+#ifdef	CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#else
+/* This is mainly used during relocation in start.S */
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
+/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + \
+						(CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+
+#define CONFIG_SYS_FLASH_SIZE		0x2000000
+#define CONFIG_SYS_FLASH_CFI_NONBLOCK	1
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text*)
+
+#if ENABLE_JFFS
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0x40
+#endif
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
+#endif	/* _CONFIG_ASTRO_MCF5373L_H */
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
new file mode 100644
index 0000000..6131277
--- /dev/null
+++ b/include/configs/at91-sama5_common.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common part of configuration settings for the AT91 SAMA5 board.
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ *		      Josh Wu <josh.wu@atmel.com>
+ */
+
+#ifndef __AT91_SAMA5_COMMON_H
+#define __AT91_SAMA5_COMMON_H
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* general purpose I/O */
+#ifndef CONFIG_DM_GPIO
+#define CONFIG_AT91_GPIO
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#ifdef CONFIG_SD_BOOT
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+#define CONFIG_BOOTCOMMAND	"if test ! -n ${dtb_name}; then "	\
+				    "setenv dtb_name at91-${board_name}.dtb; " \
+				"fi; "					\
+				"fatload mmc 0:1 0x21000000 ${dtb_name}; " \
+				"fatload mmc 0:1 0x22000000 zImage; "	\
+				"bootz 0x22000000 - 0x21000000"
+
+#else
+
+#ifdef CONFIG_NAND_BOOT
+/* u-boot env in nand flash */
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_BOOTCOMMAND		"nand read 0x21000000 0x180000 0x80000;"	\
+					"nand read 0x22000000 0x200000 0x600000;"	\
+					"bootz 0x22000000 - 0x21000000"
+#elif CONFIG_SPI_BOOT
+/* u-boot env in serial flash, by default is bus 0 and cs 0 */
+#define CONFIG_BOOTCOMMAND		"sf probe 0; "				\
+					"sf read 0x21000000 0x60000 0xc000; "	\
+					"sf read 0x22000000 0x6c000 0x394000; "	\
+					"bootz 0x22000000 - 0x21000000"
+#elif CONFIG_QSPI_BOOT
+#define CONFIG_BOOTCOMMAND		"sf probe 0; "					\
+					"sf read 0x21000000 0x180000 0x80000; "		\
+					"sf read 0x22000000 0x200000 0x600000; "	\
+					"bootz 0x22000000 - 0x21000000"
+#endif
+
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#endif
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
new file mode 100644
index 0000000..8bfba35
--- /dev/null
+++ b/include/configs/at91rm9200ek.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
+ *
+ * based on previous work by
+ *
+ * Ulf Samuelsson <ulf@atmel.com>
+ * Rick Bronson <rick@efn.org>
+ *
+ * Configuration settings for the AT91RM9200EK board.
+ */
+
+#ifndef __AT91RM9200EK_CONFIG_H__
+#define __AT91RM9200EK_CONFIG_H__
+
+#include <linux/sizes.h>
+
+/*
+ * set some initial configurations depending on configure target
+ *
+ * at91rm9200ek_config     -> boot from 0x0 in NOR Flash at CS0
+ * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
+ *                            initialisation was done by some preloader
+ */
+#ifdef CONFIG_RAMBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
+ * AT91C_MAIN_CLOCK is the frequency of PLLA output
+ * AT91C_MASTER_CLOCK is the peripherial clock
+ * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
+ *  set in arch/arm/cpu/arm920t/at91/timer.c)
+ * CONFIG_SYS_HZ is the tick rate for timer tc0
+ */
+#define AT91C_XTAL_CLOCK		18432000
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define AT91C_MAIN_CLOCK		((AT91C_XTAL_CLOCK / 4) * 39)
+#define AT91C_MASTER_CLOCK		(AT91C_MAIN_CLOCK / 3 )
+#define CONFIG_SYS_HZ_CLOCK		(AT91C_MASTER_CLOCK / 2)
+
+/* CPU configuration */
+#define CONFIG_AT91RM9200
+#define CONFIG_AT91RM9200EK
+#define USE_920T_MMU
+
+#include <asm/hardware.h>	/* needed for port definitions */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Memory Configuration
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		SZ_32M
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		\
+		(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
+
+/*
+ * LowLevel Init
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR
+/* flash */
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_MCKR_VAL	0x00000202
+
+/* sdram */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM1	(CONFIG_SYS_SDRAM_BASE+0x80)
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * Hardware drivers
+ */
+/*
+ * Choose a USART for serial console
+ * CONFIG_DBGU is DBGU unit on J10
+ * CONFIG_USART1 is USART1 on J14
+ */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
+#define CONFIG_USART_ID		0/* ignored in arm */
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Network Driver Setting
+ */
+#define CONFIG_DRIVER_AT91EMAC
+#define CONFIG_SYS_RX_ETH_BUFFER	16
+#define CONFIG_RMII
+
+/*
+ * NOR Flash
+ */
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define PHYS_FLASH_1			CONFIG_SYS_FLASH_BASE
+#define PHYS_FLASH_SIZE			SZ_8M
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+/*
+ * USB Config
+ */
+#define CONFIG_USB_ATMEL			1
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW			1
+
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_USB_HOST_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+/*
+ * Environment Settings
+ */
+
+/*
+ * after u-boot.bin
+ */
+#define CONFIG_ENV_ADDR			\
+		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		SZ_256K
+
+/*
+ * Boot option
+ */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_16M
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Shell Settings
+ */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
+					     SZ_4K)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
+					- GENERATED_GBL_DATA_SIZE)
+
+#endif /* __AT91RM9200EK_CONFIG_H__ */
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
new file mode 100644
index 0000000..b283c9d
--- /dev/null
+++ b/include/configs/at91sam9260ek.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
+
+/* Define actual evaluation board type from used processor type */
+#ifdef CONFIG_AT91SAM9G20
+# define CONFIG_AT91SAM9G20EK	/* It's an Atmel AT91SAM9G20 EK */
+#else
+# define CONFIG_AT91SAM9260EK	/* It's an Atmel AT91SAM9260 EK */
+#endif
+
+/* Misc CPU related */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+#ifdef CONFIG_AT91SAM9XE
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#else
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+/*
+ * The (arm)linux board id set by generic code depending on configured board
+ * (see boards.cfg for different boards)
+ */
+#ifdef CONFIG_AT91SAM9G20
+	/* the sam9g20 variants have two different board ids */
+# ifdef CONFIG_AT91SAM9G20EK_2MMC
+	/* we may be setup for the 2MMC variant of at91sam9g20ek */
+#  define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK_2MMC
+# else
+	/* or the normal at91sam9g20ek */
+#  define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK
+# endif
+#else
+	/* otherwise default to good old at91sam9260ek */
+# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK
+#endif
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#endif
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_ENV_SECT_SIZE	0x210
+#define CONFIG_BOOTCOMMAND	"sf probe 0:0; " \
+				"sf read 0x22000000 0x84000 0x294000; " \
+				"bootm 0x22000000"
+
+#elif CONFIG_SYS_USE_DATAFLASH_CS1
+
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_ENV_SECT_SIZE	0x210
+#define CONFIG_BOOTCOMMAND	"sf probe 0:1; " \
+				"sf read 0x22000000 0x84000 0x294000; " \
+				"bootm 0x22000000"
+
+#elif defined(CONFIG_SYS_USE_NANDFLASH)
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET		0x140000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
+
+#else	/* CONFIG_SYS_USE_MMC */
+/* bootstrap + u-boot + env + linux in mmc */
+/* For FAT system, most cases it should be in the reserved sector */
+#define CONFIG_ENV_OFFSET		0x2000
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_BOOTCOMMAND						\
+	"fatload mmc 0:1 0x22000000 uImage; bootm"
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
new file mode 100644
index 0000000..599e262
--- /dev/null
+++ b/include/configs/at91sam9261ek.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9261EK board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432 MHz crystal */
+
+#ifdef CONFIG_AT91SAM9G10
+#define CONFIG_AT91SAM9G10EK		/* It's an Atmel AT91SAM9G10 EK*/
+#else
+#define CONFIG_AT91SAM9261EK		/* It's an Atmel AT91SAM9261 EK*/
+#endif
+
+#include <asm/hardware.h>
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_ATMEL_LEGACY
+
+/*
+ * Hardware drivers
+ */
+
+/* LCD */
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_ATMEL_LCD
+#ifdef CONFIG_AT91SAM9261EK
+#define CONFIG_ATMEL_LCD_BGR555
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD22 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
+/* our CLE is AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC15
+
+#endif
+
+/* Ethernet */
+#define CONFIG_DRIVER_DM9000
+#define CONFIG_DM9000_BASE		0x30000000
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT
+#define CONFIG_DM9000_NO_SROM
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9261_UHP_BASE */
+#ifdef CONFIG_AT91SAM9G10EK
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g10"
+#else
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
+#endif
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_ENV_SECT_SIZE	0x210
+#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
+				"sf read 0x22000000 0x84000 0x294000; " \
+				"bootm 0x22000000"
+
+#elif CONFIG_SYS_USE_DATAFLASH_CS3
+
+/* bootstrap + u-boot + env + linux in dataflash on CS3 */
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_ENV_SECT_SIZE	0x210
+#define CONFIG_BOOTCOMMAND	"sf probe 0:3; " \
+				"sf read 0x22000000 0x84000 0x294000; " \
+				"bootm 0x22000000"
+
+#else /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET		0x140000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
new file mode 100644
index 0000000..3e7adf6
--- /dev/null
+++ b/include/configs/at91sam9263ek.h
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9263EK board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#else
+#define CONFIG_SYS_USE_NORFLASH
+#endif
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_LEGACY
+
+/* LCD */
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_BGR555		1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NOR flash, if populated */
+#ifdef CONFIG_SYS_USE_NORFLASH
+#define PHYS_FLASH_1				0x10000000
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT		256
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+
+#define CONFIG_SYS_MONITOR_SEC	1:0-3
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x007E0000)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE		0x10000
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
+	"update=" \
+		"protect off ${monitor_base} +${filesize};" \
+		"erase ${monitor_base} +${filesize};" \
+		"cp.b ${fileaddr} ${monitor_base} ${filesize};" \
+		"protect on ${monitor_base} +${filesize}\0"
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define MASTER_PLL_MUL		171
+#define MASTER_PLL_DIV		14
+#define MASTER_PLL_OUT		3
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL						\
+		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
+#define CONFIG_SYS_PLLAR_VAL					\
+	(AT91_PMC_PLLAR_29 |					\
+	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
+	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
+	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | 		\
+	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL		\
+	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
+	 AT91_PMC_MCKR_MDIV_2)
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL		\
+	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | 	\
+	AT91_PMC_MCKR_MDIV_2)
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBICSA_VAL					\
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
+	 AT91_MATRIX_CSA_EBI_CS1A)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1		0
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL							\
+		(AT91_SDRAMC_NC_9 |						\
+		 AT91_SDRAMC_NR_13 |						\
+		 AT91_SDRAMC_NB_4 |						\
+		 AT91_SDRAMC_CAS_3 |						\
+		 AT91_SDRAMC_DBW_32 |						\
+		 (1 <<  8) |		/* Write Recovery Delay */		\
+		 (7 << 12) |		/* Row Cycle Delay */			\
+		 (2 << 16) |		/* Row Precharge Delay */		\
+		 (2 << 20) |		/* Row to Column Delay */		\
+		 (5 << 24) |		/* Active to Precharge Delay */		\
+		 (1 << 28))		/* Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL				\
+	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL				\
+	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
+	 AT91_SMC_MODE_DBW_16 |					\
+	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_MR_URSTEN |		\
+		AT91_RSTC_MR_ERSTL(15))
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xfff) |			\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xfff))
+
+#endif
+#endif
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8			1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
+#endif
+
+/* Ethernet */
+#define CONFIG_RESET_PHY_R		1
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_ENV_SECT_SIZE	0x210
+#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
+				"sf read 0x22000000 0x84000 0x294000; " \
+				"bootm 0x22000000"
+
+#elif CONFIG_SYS_USE_NANDFLASH
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET		0x140000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
new file mode 100644
index 0000000..044c428
--- /dev/null
+++ b/include/configs/at91sam9m10g45ek.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_AT91SAM9M10G45EK
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* LCD */
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_ATMEL_LCD
+#define CONFIG_ATMEL_LCD_RGB565
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE		0x73E00000
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE           0x70000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+
+#endif
+
+/* Ethernet */
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x23e00000
+
+#ifdef CONFIG_NAND_BOOT
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_OFFSET		0x140000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000
+
+#define CONFIG_BOOTCOMMAND						\
+	"nand read 0x70000000 0x200000 0x300000;"			\
+	"bootm 0x70000000"
+#elif CONFIG_SD_BOOT
+/* bootstrap + u-boot + env + linux in mmc */
+#define CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x71000000 dtb; " \
+				"fatload mmc 0:1 0x72000000 zImage; " \
+				"bootz 0x72000000 - 0x71000000"
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		0x010000
+#define CONFIG_SPL_STACK		0x310000
+
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+
+#ifdef CONFIG_SD_BOOT
+
+#define CONFIG_SPL_BSS_START_ADDR	0x70000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
+#define CONFIG_SYS_SPL_MALLOC_START	0x70080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+
+#elif CONFIG_NAND_BOOT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+#endif
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#endif
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
new file mode 100644
index 0000000..bc79e17
--- /dev/null
+++ b/include/configs/at91sam9n12ek.h
@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 Atmel Corporation.
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * Configuation settings for the AT91SAM9N12-EK boards.
+ */
+
+#ifndef __AT91SAM9N12_CONFIG_H_
+#define __AT91SAM9N12_CONFIG_H_
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16000000	/* main clock xtal */
+
+/* Misc CPU related */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* LCD */
+#define LCD_BPP				LCD_COLOR16
+#define LCD_OUTPUT_BPP			24
+#define CONFIG_LCD_LOGO
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_ATMEL_HLCD
+#define CONFIG_ATMEL_LCD_RGB565
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(4)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(5)
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS                                       \
+	"console=console=ttyS0,115200\0"                                \
+	"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"					\
+	"bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
+	"bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
+
+/* Ethernet */
+#define CONFIG_KS8851_MLL
+#define CONFIG_KS8851_MLL_BASEADDR	0x30000000 /* use NCS2 */
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x26e00000
+
+/* USB host */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9n12"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#endif
+
+#ifdef CONFIG_SPI_BOOT
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_OFFSET		0x5000
+#define CONFIG_ENV_SIZE			0x3000
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_BOOTCOMMAND						\
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_nand};"	\
+	"sf probe 0; sf read 0x22000000 0x100000 0x300000; "		\
+	"bootm 0x22000000"
+
+#elif defined(CONFIG_NAND_BOOT)
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET		0x140000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND						\
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_nand};"	\
+	"nand read 0x21000000 0x180000 0x080000;"			\
+	"nand read 0x22000000 0x200000 0x400000;"			\
+	"bootm 0x22000000 - 0x21000000"
+
+#else /* CONFIG_SD_BOOT */
+
+/* bootstrap + u-boot + env + linux in mmc */
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+/* Use raw reserved sectors to save environment */
+#define CONFIG_ENV_OFFSET		0x2000
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#else
+/* Use file in FAT file to save environment */
+#define CONFIG_ENV_SIZE			0x4000
+#endif
+
+#define CONFIG_BOOTCOMMAND						\
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};"	\
+	"fatload mmc 0:1 0x21000000 dtb;"				\
+	"fatload mmc 0:1 0x22000000 uImage;"				\
+	"bootm 0x22000000 - 0x21000000"
+
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(4 * 1024 * 1024)
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE		0x6000
+#define CONFIG_SPL_STACK		0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20953f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#elif CONFIG_NAND_BOOT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+
+#endif
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
new file mode 100644
index 0000000..1c67be5
--- /dev/null
+++ b/include/configs/at91sam9rlek.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9RLEK board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* main clock xtal */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_ATMEL_LEGACY
+
+/*
+ * Hardware drivers
+ */
+
+/* LCD */
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_RGB565		1
+/* Let board_init_f handle the framebuffer allocation */
+#undef CONFIG_FB_ADDR
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8			1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PB6
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PD17
+
+#endif
+
+/* Ethernet - not present */
+
+/* USB - not supported */
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_ENV_SECT_SIZE	0x210
+#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
+				"sf read 0x22000000 0x84000 0x294000; " \
+				"bootm 0x22000000"
+
+#elif CONFIG_SYS_USE_NANDFLASH
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET		0x140000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x600000; "	\
+				"nand read 0x21000000 0x180000 0x80000; "	\
+				"bootz 0x22000000 - 0x21000000"
+
+#else /* CONFIG_SYS_USE_MMC */
+
+/* bootstrap + u-boot + env + linux in mmc */
+#define CONFIG_ENV_SIZE		0x4000
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; " \
+				"fatload mmc 0:1 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
new file mode 100644
index 0000000..f9a100b
--- /dev/null
+++ b/include/configs/at91sam9x5ek.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * Configuation settings for the AT91SAM9X5EK board.
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
+ * NB: in this case, USB 1.1 devices won't be recognized.
+ */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 megs */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#ifndef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9x5"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
+#endif
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x26e00000
+
+#ifdef CONFIG_NAND_BOOT
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_BOOTCOMMAND	"nand read " \
+				"0x22000000 0x200000 0x600000; " \
+				"nand read 0x21000000 0x180000 0x20000; " \
+				"bootz 0x22000000 - 0x21000000"
+#elif defined(CONFIG_SPI_BOOT)
+/* bootstrap + u-boot + env + linux in spi flash */
+#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
+				"sf read 0x22000000 0x100000 0x300000; " \
+				"bootm 0x22000000"
+#elif defined(CONFIG_SYS_USE_DATAFLASH)
+/* bootstrap + u-boot + env + linux in data flash */
+#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
+				"sf read 0x22000000 0x84000 0x294000; " \
+				"bootm 0x22000000"
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024 + 0x1000)
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE		0x6000
+#define CONFIG_SPL_STACK		0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#elif CONFIG_NAND_BOOT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+
+#endif
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
new file mode 100644
index 0000000..a4037f3
--- /dev/null
+++ b/include/configs/ax25-ae350.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+
+/*
+ * Print Buffer Size
+ */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * max number of command args
+ */
+#define CONFIG_SYS_MAXARGS	16
+
+/*
+ * Boot Argument Buffer Size
+ */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Size of malloc() pool
+ * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
+ */
+#define CONFIG_SYS_MALLOC_LEN   (512 << 10)
+
+/* DT blob (fdt) address */
+#define CONFIG_SYS_FDT_BASE		0x800f0000
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_0	0x00000000		/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1	\
+	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */
+#define PHYS_SDRAM_0_SIZE	0x20000000	/* 512 MB */
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_0
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#endif
+#define CONFIG_SYS_NS16550_CLK		19660800
+
+/* Init Stack Pointer */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
+					GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Load address and memory test area should agree with
+ * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* SDRAM */
+
+/*
+ * memtest works on 512 MB in DRAM
+ */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
+
+/*
+ * FLASH and environment organization
+ */
+
+/* use CFI framework */
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
+
+/* support JEDEC */
+#ifdef CONFIG_CFI_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+#endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#define PHYS_FLASH_1			0x88000000	/* BANK 0 */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+*/
+#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#endif
+#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2)
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* environments */
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OVERWRITE
+
+/* SPI FLASH */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
+/* Increase max gunzip size */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)
+
+/* When we use RAM as ENV */
+#define CONFIG_ENV_SIZE 0x2000
+
+/* Enable distro boot */
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+				"kernel_addr_r=0x00080000\0" \
+				"pxefile_addr_r=0x01f00000\0" \
+				"scriptaddr=0x01f00000\0" \
+				"fdt_addr_r=0x02000000\0" \
+				"ramdisk_addr_r=0x02800000\0" \
+				BOOTENV
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h
new file mode 100644
index 0000000..0c5a3af
--- /dev/null
+++ b/include/configs/axs10x.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef _CONFIG_AXS10X_H_
+#define _CONFIG_AXS10X_H_
+
+#include <linux/sizes.h>
+/*
+ *  CPU configuration
+ */
+#define ARC_FPGA_PERIPHERAL_BASE	0xE0000000
+#define ARC_APB_PERIPHERAL_BASE		0xF0000000
+#define ARC_DWMMC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x15000)
+#define ARC_DWGMAC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x18000)
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		SZ_512M
+
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_2M
+#define CONFIG_SYS_BOOTM_LEN		SZ_128M
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+/*
+ * UART configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK		33333333
+#define CONFIG_SYS_NS16550_MEM32
+
+/*
+ * Ethernet PHY configuration
+ */
+
+/*
+ * USB 1.1 configuration
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"upgrade=if mmc rescan && " \
+		"fatload mmc 0:1 ${loadaddr} u-boot-update.img && " \
+		"iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
+		"\"Fail to upgrade.\n" \
+		"Do you have u-boot-update.img and u-boot.head on first (FAT) SD card partition?\"" \
+		"; fi\0"
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+
+#endif /* _CONFIG_AXS10X_H_ */
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
new file mode 100644
index 0000000..a9b14c5
--- /dev/null
+++ b/include/configs/baltos.h
@@ -0,0 +1,258 @@
+/*
+ * am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_BALTOS_H
+#define __CONFIG_BALTOS_H
+
+#include <linux/sizes.h>
+#include <configs/ti_am335x_common.h>
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_AM335XEVM
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+/* FIT support */
+#define CONFIG_SYS_BOOTM_LEN         SZ_64M
+
+#ifdef CONFIG_NAND
+
+#define NANDARGS \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"${mtdparts} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=5\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"setenv loadaddr 0x84000000; " \
+		"ubi part UBI; " \
+		"ubifsmount ubi0:kernel; " \
+		"ubifsload $loadaddr kernel-fit.itb;" \
+		"ubifsumount; " \
+		"bootm ${loadaddr}#conf${board_name}; " \
+		"if test $? -ne 0; then echo Using default FIT config; " \
+		"bootm ${loadaddr}; fi;\0"
+#else
+#define NANDARGS ""
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"boot_fdt=try\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"fdtfile=undefined\0" \
+	"console=ttyO0,115200n8\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 ro\0" \
+	"usbroot=/dev/sda2 ro\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"usbrootfstype=ext4 rootwait\0" \
+	"rootpath=/export/rootfs\0" \
+	"nfsopts=nolock\0" \
+	"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+		"::off\0" \
+	"ramroot=/dev/ram0 rw\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"${mtdparts} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"usbargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"${mtdparts} " \
+		"root=${usbroot} " \
+		"rootfstype=${usbrootfstype}\0" \
+	"spiroot=/dev/mtdblock4 rw\0" \
+	"spirootfstype=jffs2\0" \
+	"spisrcaddr=0xe0000\0" \
+	"spiimgsize=0x362000\0" \
+	"spibusno=0\0" \
+	"spiargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${spiroot} " \
+		"rootfstype=${spirootfstype}\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"usbloadbootenv=load usb 0:1 ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"usbimportbootenv=echo Importing environment from USB ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"usbloadimage=load usb 0:1 ${loadaddr} kernel-fit.itb\0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"usbloados=run usbargs; " \
+		"bootm ${loadaddr}#conf${board_name}; " \
+		"if test $? -ne 0; then " \
+			"echo Using default FIT configuration; " \
+			"bootm ${loadaddr}; " \
+		"fi;\0" \
+	"mmcloados=run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"usbboot=usb reset; " \
+		"if usb storage; then " \
+			"echo USB drive found;" \
+			"if run usbloadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run usbimportbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run usbloadimage; then " \
+				"run usbloados;" \
+			"fi;" \
+		"fi;\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run mmcloados;" \
+			"fi;" \
+		"fi;\0" \
+	"spiboot=echo Booting from spi ...; " \
+		"run spiargs; " \
+		"sf probe ${spibusno}:0; " \
+		"sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
+		"bootz ${loadaddr}\0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"tftp ${loadaddr} ${bootfile}; " \
+		"tftp ${fdtaddr} ${fdtfile}; " \
+		"run netargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+	"findfdt=setenv fdtfile am335x-baltos.dtb\0" \
+	NANDARGS
+	/*DFUARGS*/
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"run usbboot;" \
+	"run mmcboot;" \
+	"setenv mmcdev 1; " \
+	"setenv bootpart 1:2; " \
+	"run mmcboot;" \
+	"run nandboot;"
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65910
+
+/* SPL */
+#ifndef CONFIG_NOR_BOOT
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#endif
+#endif
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_HOST
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_OTG
+
+/* NAND support */
+#ifdef CONFIG_NAND
+#define GPMC_NAND_ECC_LP_x8_LAYOUT	1
+#endif
+
+#endif	/* ! __CONFIG_BALTOS_H */
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
new file mode 100644
index 0000000..db21a47
--- /dev/null
+++ b/include/configs/bav335x.h
@@ -0,0 +1,491 @@
+/*
+ * bav335x.h
+ *
+ * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_BAV335X_H
+#define __CONFIG_BAV335X_H
+
+#include <configs/ti_am335x_common.h>
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_AM335XEVM
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdtaddr} u-boot-spl-os; " \
+		"nand read ${loadaddr} kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#else
+#define NANDARGS ""
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+DEFAULT_LINUX_BOOT_ENV \
+"boot_fdt=try\0" \
+"bootpart=0:2\0" \
+"bootdir=\0" \
+"fdtdir=/dtbs\0" \
+"bootfile=zImage\0" \
+"fdtfile=undefined\0" \
+"console=ttyO0,115200n8\0" \
+"loadaddr=0x82000000\0" \
+"fdtaddr=0x88000000\0" \
+"rdaddr=0x88080000\0" \
+"initrd_high=0xffffffff\0" \
+"fdt_high=0xffffffff\0" \
+"partitions=" \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+"optargs=\0" \
+"cmdline=\0" \
+"mmcdev=0\0" \
+"mmcpart=1\0" \
+"mmcroot=/dev/mmcblk0p2 ro\0" \
+"mmcrootfstype=ext4 rootwait fixrtc\0" \
+"rootpath=/export/rootfs\0" \
+"nfsopts=nolock\0" \
+"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
+"ramroot=/dev/ram0 rw\0" \
+"ramrootfstype=ext2\0" \
+"mmcargs=setenv bootargs console=${console} ${optargs} " \
+	"root=${mmcroot} rootfstype=${mmcrootfstype} ${cmdline}\0" \
+"server_ip=192.168.1.100\0" \
+"gw_ip=192.168.1.1\0" \
+"netmask=255.255.255.0\0" \
+"hostname=\0" \
+"device=eth0\0" \
+"autoconf=off\0" \
+"root_dir=/home/userid/targetNFS\0" \
+"nfs_options=,vers=3\0" \
+"nfsrootfstype=ext4 rootwait fixrtc\0" \
+"nfsargs=setenv bootargs console=${console} ${optargs} " \
+	"root=/dev/nfs rw rootfstype=${nfsrootfstype} " \
+	"nfsroot=${nfsroot} ip=${ip} ${cmdline}\0" \
+"netargs=setenv bootargs console=${console} " \
+	"${optargs} root=/dev/nfs " \
+	"nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp\0" \
+"bootenv=uEnv.txt\0" \
+"script=boot.scr\0" \
+"scriptfile=${script}\0" \
+"loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \
+"bootscript=echo Running bootscript from mmc${bootpart} ...; " \
+	"source ${loadaddr}\0" \
+	"loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \
+"importbootenv=echo Importing environment from mmc ...; " \
+	"env import -t -r $loadaddr $filesize\0" \
+"ramargs=setenv bootargs console=${console} " \
+	"${optargs} root=${ramroot} rootfstype=${ramrootfstype}\0" \
+"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadrd=load mmc ${bootpart} ${rdaddr} " \
+	"${bootdir}/${rdfile}; setenv rdsize ${filesize}\0" \
+"loadfdt=echo loading ${fdtdir}/${fdtfile} ...; " \
+	"load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \
+"mmcboot=mmc dev ${mmcdev}; " \
+	"if mmc rescan; then " \
+		"gpio set 54;" \
+		"setenv bootpart ${mmcdev}:1; " \
+		"if test -e mmc ${bootpart} /etc/fstab; then " \
+			"setenv mmcpart 1;" \
+		"fi; " \
+		"echo Checking for: /uEnv.txt ...;" \
+		"if test -e mmc ${bootpart} /uEnv.txt; then " \
+			"if run loadbootenv; then " \
+				"gpio set 55;" \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"echo Checking if uenvcmd is set ...;" \
+			"if test -n ${uenvcmd}; then " \
+				"gpio set 56; " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"echo Checking if client_ip is set ...;" \
+			"if test -n ${client_ip}; then " \
+				"if test -n ${dtb}; then " \
+					"setenv fdtfile ${dtb};" \
+					"echo using ${fdtfile} ...;" \
+				"fi;" \
+				"gpio set 56; " \
+				"if test -n ${uname_r}; then " \
+					"echo Running nfsboot_uname_r ...;" \
+					"run nfsboot_uname_r;" \
+				"fi;" \
+				"echo Running nfsboot ...;" \
+				"run nfsboot;" \
+			"fi;" \
+		"fi; " \
+		"echo Checking for: /${script} ...;" \
+		"if test -e mmc ${bootpart} /${script}; then " \
+			"gpio set 55;" \
+			"setenv scriptfile ${script};" \
+			"run loadbootscript;" \
+			"echo Loaded script from ${scriptfile};" \
+			"gpio set 56; " \
+			"run bootscript;" \
+		"fi; " \
+		"echo Checking for: /boot/${script} ...;" \
+		"if test -e mmc ${bootpart} /boot/${script}; then " \
+			"gpio set 55;" \
+			"setenv scriptfile /boot/${script};" \
+			"run loadbootscript;" \
+			"echo Loaded script from ${scriptfile};" \
+			"gpio set 56; " \
+			"run bootscript;" \
+		"fi; " \
+		"echo Checking for: /boot/uEnv.txt ...;" \
+		"for i in 1 2 3 4 5 6 7 ; do " \
+			"setenv mmcpart ${i};" \
+			"setenv bootpart ${mmcdev}:${mmcpart};" \
+			"if test -e mmc ${bootpart} /boot/uEnv.txt; then " \
+				"gpio set 55;" \
+				"load mmc ${bootpart} ${loadaddr} " \
+						"/boot/uEnv.txt;" \
+				"env import -t ${loadaddr} ${filesize};" \
+				"echo Loaded environment from /boot/uEnv.txt;" \
+				"if test -n ${dtb}; then " \
+					"setenv fdtfile ${dtb};" \
+					"echo Using: dtb=${fdtfile} ...;" \
+				"fi;" \
+				"echo Checking if uname_r is set in " \
+						"/boot/uEnv.txt...;" \
+				"if test -n ${uname_r}; then " \
+					"gpio set 56; " \
+					"echo Running uname_boot ...;" \
+					"setenv mmcroot /dev/mmcblk${mmcdev}" \
+							"p${mmcpart} ro;" \
+					"run uname_boot;" \
+				"fi;" \
+			"fi;" \
+		"done;" \
+	"fi;\0" \
+"netboot=echo Booting from network ...; " \
+	"setenv autoload no; " \
+	"dhcp; " \
+	"tftp ${loadaddr} ${bootfile}; " \
+	"tftp ${fdtaddr} ${fdtfile}; " \
+	"run netargs; " \
+	"bootz ${loadaddr} - ${fdtaddr}\0" \
+"nfsboot=echo Booting from ${server_ip} ...; " \
+	"setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
+	"setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
+	":${device}:${autoconf}; " \
+	"setenv autoload no; " \
+	"setenv serverip ${server_ip}; " \
+	"setenv ipaddr ${client_ip}; " \
+	"tftp ${loadaddr} ${bootfile}; " \
+	"tftp ${fdtaddr} dtbs/${fdtfile}; " \
+	"run nfsargs; " \
+	"bootz ${loadaddr} - ${fdtaddr}\0" \
+"nfsboot_uname_r=echo Booting from ${server_ip} ...; " \
+	"setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
+	"setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
+			":${device}:${autoconf}; " \
+	"setenv autoload no; " \
+	"setenv serverip ${server_ip}; " \
+	"setenv ipaddr ${client_ip}; " \
+	"tftp ${loadaddr} vmlinuz-${uname_r}; " \
+	"tftp ${fdtaddr} dtbs/${uname_r}/${fdtfile}; " \
+	"run nfsargs; " \
+	"bootz ${loadaddr} - ${fdtaddr}\0" \
+"ramboot=echo Booting from ramdisk ...; " \
+	"run ramargs; " \
+	"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+"findfdt="\
+	"if test $board_rev = B; then " \
+		"setenv fdtfile birdland_bav335b.dtb; " \
+		"setenv fdtbase am335x-boneblack; fi; " \
+	"if test $board_rev = A; then " \
+		"setenv fdtfile birdland_bav335a.dtb; " \
+		"setenv fdtbase am335x-boneblack; fi; " \
+	"if test $fdtfile = undefined; then " \
+		"echo WARNING: Could not determine device tree to use; fi; \0" \
+"uname_boot="\
+	"setenv bootdir /boot; " \
+	"setenv bootfile vmlinuz-${uname_r}; " \
+	"if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
+		"echo loading ${bootdir}/${bootfile} ...; "\
+		"run loadimage;" \
+		"setenv fdtdir /boot/dtbs/${uname_r}; " \
+		"if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
+			"run loadfdt;" \
+		"else " \
+			"setenv fdtdir /lib/firmware/${uname_r}/device-tree; " \
+			"if test -e mmc ${bootpart} ${fdtdir}/" \
+					"${fdtfile}; then " \
+				"run loadfdt;" \
+			"else " \
+				"setenv fdtdir /boot/dtb-${uname_r}; " \
+				"if test -e mmc ${bootpart} ${fdtdir}" \
+						"/${fdtfile}; then " \
+					"run loadfdt;" \
+				"else " \
+					"setenv fdtdir /boot/dtbs; " \
+					"if test -e mmc ${bootpart} ${fdtdir}" \
+							"/${fdtfile}; then " \
+						"run loadfdt;" \
+					"else " \
+						"echo; echo unable to find " \
+							"[${fdtfile}] " \
+						"did you name it correctly?" \
+						"echo booting fallback " \
+							"[/boot/dtbs/" \
+							"${uname_r}" \
+							"/${fdtbase}.dtb]...;" \
+						"setenv fdtdir /boot/dtbs/" \
+							"${uname_r}; " \
+						"setenv fdtfile " \
+							"${fdtbase}.dtb; " \
+						"run loadfdt;" \
+					"fi;" \
+				"fi;" \
+			"fi;" \
+		"fi;" \
+	"fi; " \
+	"setenv rdfile initrd.img-${uname_r}; " \
+	"if test -e mmc ${bootpart} ${bootdir}/${rdfile}; then " \
+		"echo loading ${bootdir}/${rdfile} ...; "\
+		"run loadrd;" \
+		"if test -n ${uuid}; then " \
+			"setenv mmcroot UUID=${uuid} ro;" \
+		"fi;" \
+		"run mmcargs;" \
+		"echo debug: [${bootargs}] ... ;" \
+		"echo debug: [bootz ${loadaddr} ${rdaddr}:${rdsize} " \
+					"${fdtaddr}] ... ;" \
+		"bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}; " \
+	"else " \
+		"run mmcargs;" \
+		"echo debug: [${bootargs}] ... ;" \
+		"echo debug: [bootz ${loadaddr} - ${fdtaddr}] ... ;" \
+		"bootz ${loadaddr} - ${fdtaddr}; " \
+	"fi;" \
+"fi;\0" \
+	NANDARGS \
+	DFUARGS
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+	"gpio set 53; " \
+	"i2c mw 0x24 1 0x3e; " \
+	"run findfdt; " \
+	"setenv mmcdev 0; " \
+	"setenv bootpart 0:1; " \
+	"run mmcboot;" \
+	"gpio clear 56; " \
+	"gpio clear 55; " \
+	"gpio clear 54; " \
+	"setenv mmcdev 1; " \
+	"setenv bootpart 1:1; " \
+	"run mmcboot;"
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
+/* SPL */
+#ifndef CONFIG_NOR_BOOT
+/* Bootcount using the RTC block */
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* USB gadget RNDIS */
+#endif
+
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+/* NAND: driver related configs */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS	{ \
+	2, 3, 4, 5, 6, 7, 8, 9, \
+	10, 11, 12, 13, 14, 15, 16, 17, \
+	18, 19, 20, 21, 22, 23, 24, 25, \
+	26, 27, 28, 29, 30, 31, 32, 33, \
+	34, 35, 36, 37, 38, 39, 40, 41, \
+	42, 43, 44, 45, 46, 47, 48, 49, \
+	50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
+#define CONFIG_ENV_OFFSET		0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+#endif
+#endif /* !CONFIG_NAND */
+
+/*
+ * For NOR boot, we must set this to the start of where NOR is mapped
+ * in memory.
+ */
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)
+/* disable host part of MUSB in SPL */
+/* disable EFI partitions and partition UUID support */
+#endif
+
+/* USB Device Firmware Update support */
+#ifndef CONFIG_SPL_BUILD
+#define DFU_ALT_INFO_MMC \
+	"dfu_alt_info_mmc=" \
+	"boot part 0 1;" \
+	"rootfs part 0 2;" \
+	"MLO fat 0 1;" \
+	"MLO.raw raw 0x100 0x100;" \
+	"u-boot.img.raw raw 0x300 0x400;" \
+	"spl-os-args.raw raw 0x80 0x80;" \
+	"spl-os-image.raw raw 0x900 0x2000;" \
+	"spl-os-args fat 0 1;" \
+	"spl-os-image fat 0 1;" \
+	"u-boot.img fat 0 1;" \
+	"uEnv.txt fat 0 1\0"
+#ifdef CONFIG_NAND
+#define DFU_ALT_INFO_NAND \
+	"dfu_alt_info_nand=" \
+	"SPL part 0 1;" \
+	"SPL.backup1 part 0 2;" \
+	"SPL.backup2 part 0 3;" \
+	"SPL.backup3 part 0 4;" \
+	"u-boot part 0 5;" \
+	"u-boot-spl-os part 0 6;" \
+	"kernel part 0 8;" \
+	"rootfs part 0 9\0"
+#else
+#define DFU_ALT_INFO_NAND ""
+#endif
+#define DFU_ALT_INFO_RAM \
+	"dfu_alt_info_ram=" \
+	"kernel ram 0x80200000 0xD80000;" \
+	"fdt ram 0x80F80000 0x80000;" \
+	"ramdisk ram 0x81000000 0x4000000\0"
+#define DFUARGS \
+	"dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_NAND
+#endif
+
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x020000 : SPL (128KiB)
+ * 0x020000 - 0x0A0000 : U-Boot (512KiB)
+ * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
+ * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
+ * 0x0E0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+/* SPL related */
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET		(768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND	(896 << 10) /* 896 KiB in */
+#elif defined(CONFIG_EMMC_BOOT)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x0
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* SPI flash. */
+
+/* Network. */
+#define CONFIG_PHY_SMSC
+
+/*
+ * NOR Size = 16 MiB
+ * Number of Sectors/Blocks = 128
+ * Sector Size = 128 KiB
+ * Word length = 16 bits
+ * Default layout:
+ * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
+ * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
+ * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
+ * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
+ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
+ */
+#if defined(CONFIG_NOR)
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BASE		(0x08000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		(512 << 10)	/* 512 KiB */
+#define CONFIG_ENV_OFFSET_REDUND	(768 << 10)	/* 768 KiB */
+#endif
+#endif  /* NOR support */
+
+#endif	/* ! __CONFIG_AM335X_EVM_H */
diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h
new file mode 100644
index 0000000..288bb8e
--- /dev/null
+++ b/include/configs/bayleybay.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,usbkbd\0" \
+					"stdout=serial,vidconsole\0" \
+					"stderr=serial,vidconsole\0"
+
+/* Environment configuration */
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x006ff000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h
new file mode 100644
index 0000000..f59cd75
--- /dev/null
+++ b/include/configs/bcm23550_w1d.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#ifndef __BCM23550_W1D_H
+#define __BCM23550_W1D_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap.h>
+
+/* CPU, chip, mach, etc */
+#define CONFIG_KONA
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_KONA_RESET_S
+
+/*
+ * Memory configuration
+ */
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M	/* see armv7/start.S. */
+
+/* GPIO Driver */
+#define CONFIG_KONA_GPIO
+
+/* MMC/SD Driver */
+#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR
+#define CONFIG_SYS_SDIO0_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO1_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO2_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO3_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO0 "sdio1"
+#define CONFIG_SYS_SDIO1 "sdio2"
+#define CONFIG_SYS_SDIO2 "sdio3"
+#define CONFIG_SYS_SDIO3 "sdio4"
+
+/* I2C Driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_KONA
+#define CONFIG_SYS_SPD_BUS_NUM	3	/* Start with PMU bus */
+#define CONFIG_SYS_MAX_I2C_BUS	4
+#define CONFIG_SYS_I2C_BASE0	BSC1_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE1	BSC2_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE2	BSC3_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE3	PMU_BSC_BASE_ADDR
+
+/* Timer Driver */
+#define CONFIG_SYS_TIMER_RATE		32000
+#define CONFIG_SYS_TIMER_COUNTER	(TIMER_BASE_ADDR + 4) /* STCLO offset */
+
+/* Init functions */
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+/* No mtest functions as recommended */
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Serial Info */
+#define CONFIG_SYS_NS16550_SERIAL
+/* Post pad 3 bytes after each reg addr */
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		13000000
+#define CONFIG_SYS_NS16550_COM1		0x3e000000
+
+/* must fit into GPT:u-boot-env partition */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		(0x00011a00 * 512)
+#define CONFIG_ENV_SIZE			(8 * 512)
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE		1024	/* Console buffer size */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * One partition type must be defined for part.c
+ * This is necessary for the fatls command to work on an SD card
+ * for example.
+ */
+
+/* version string, parser, etc */
+
+/* Initial upstream - boot to cmd prompt only */
+#define CONFIG_BOOTCOMMAND		""
+
+#define CONFIG_USBID_ADDR		0x34052c46
+
+#define CONFIG_SYS_L2CACHE_OFF
+
+#endif /* __BCM23550_W1D_H */
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
new file mode 100644
index 0000000..111858f
--- /dev/null
+++ b/include/configs/bcm28155_ap.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Broadcom Corporation.
+ */
+
+#ifndef __BCM28155_AP_H
+#define __BCM28155_AP_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap.h>
+
+/* CPU, chip, mach, etc */
+#define CONFIG_KONA
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Memory configuration
+ */
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_SIZE		0x80000000
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M	/* see armv7/start.S. */
+
+/* GPIO Driver */
+#define CONFIG_KONA_GPIO
+
+/* MMC/SD Driver */
+#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR
+#define CONFIG_SYS_SDIO0_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO1_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO2_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO3_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO0 "sdio1"
+#define CONFIG_SYS_SDIO1 "sdio2"
+#define CONFIG_SYS_SDIO2 "sdio3"
+#define CONFIG_SYS_SDIO3 "sdio4"
+
+/* I2C Driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_KONA
+#define CONFIG_SYS_SPD_BUS_NUM	3	/* Start with PMU bus */
+#define CONFIG_SYS_MAX_I2C_BUS	4
+#define CONFIG_SYS_I2C_BASE0	BSC1_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE1	BSC2_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE2	BSC3_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE3	PMU_BSC_BASE_ADDR
+
+/* Timer Driver */
+#define CONFIG_SYS_TIMER_RATE		32000
+#define CONFIG_SYS_TIMER_COUNTER	(TIMER_BASE_ADDR + 4) /* STCLO offset */
+
+/* Init functions */
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+/* No mtest functions as recommended */
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Serial Info */
+#define CONFIG_SYS_NS16550_SERIAL
+/* Post pad 3 bytes after each reg addr */
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		13000000
+#define CONFIG_SYS_NS16550_COM1		0x3e000000
+
+/* must fit into GPT:u-boot-env partition */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		(0x00011a00 * 512)
+#define CONFIG_ENV_SIZE			(8 * 512)
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE		1024	/* Console buffer size */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * One partition type must be defined for part.c
+ * This is necessary for the fatls command to work on an SD card
+ * for example.
+ */
+
+/* version string, parser, etc */
+
+/* Initial upstream - boot to cmd prompt only */
+#define CONFIG_BOOTCOMMAND		""
+
+#define CONFIG_USBID_ADDR		0x34052c46
+
+#endif /* __BCM28155_AP_H */
diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h
new file mode 100644
index 0000000..967bde5
--- /dev/null
+++ b/include/configs/bcm7260.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018  Cisco Systems, Inc.
+ *
+ * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
+ *
+ * Configuration settings for the Broadcom BCM7260 SoC family.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NS16550_COM1	0xf040c000
+
+#define CONFIG_SYS_TEXT_BASE		0x10100000
+#define CONFIG_SYS_INIT_RAM_ADDR	0x10200000
+
+#define CONFIG_SYS_MALLOC_LEN		((40 * 1024) << 10) /* 40 MiB */
+
+#include "bcmstb.h"
+
+#define BCMSTB_TIMER_LOW	0xf0412008
+#define BCMSTB_TIMER_HIGH	0xf041200c
+#define BCMSTB_TIMER_FREQUENCY	0xf0412020
+#define BCMSTB_HIF_MSPI_BASE	0xf0203c00
+#define BCMSTB_BSPI_BASE	0xf0203a00
+#define BCMSTB_HIF_SPI_INTR2	0xf0201a00
+#define BCMSTB_CS_REG		0xf0200920
+
+/*
+ * Environment configuration for eMMC.
+ */
+#define CONFIG_ENV_OFFSET	(0x000040a4 * 512)
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_SYS_MMC_ENV_PART	0
+
+#define CONFIG_CMD_GPT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h
new file mode 100644
index 0000000..3ff4677
--- /dev/null
+++ b/include/configs/bcm7445.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018  Cisco Systems, Inc.
+ *
+ * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
+ *
+ * Configuration settings for the Broadcom BCM7445 SoC family.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NS16550_COM1	0xf040ab00
+
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80200000
+
+#define CONFIG_SYS_MALLOC_LEN		((10 * 1024) << 10) /* 10 MiB */
+
+#include "bcmstb.h"
+
+#define BCMSTB_TIMER_LOW	0xf0412008
+#define BCMSTB_TIMER_HIGH	0xf041200c
+#define BCMSTB_TIMER_FREQUENCY	0xf0412020
+#define BCMSTB_HIF_MSPI_BASE	0xf03e3400
+#define BCMSTB_BSPI_BASE	0xf03e3200
+#define BCMSTB_HIF_SPI_INTR2	0xf03e1a00
+#define BCMSTB_CS_REG		0xf03e0920
+
+/*
+ * Environment configuration for SPI flash.
+ */
+#define CONFIG_ENV_OFFSET	0x1e0000
+#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h
new file mode 100644
index 0000000..b67100a
--- /dev/null
+++ b/include/configs/bcm_ep_board.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#ifndef __BCM_EP_BOARD_H
+#define __BCM_EP_BOARD_H
+
+#include <asm/arch/configs.h>
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Memory configuration
+ * (these must be defined elsewhere)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#error	CONFIG_SYS_TEXT_BASE must be defined!
+#endif
+#ifndef CONFIG_SYS_SDRAM_BASE
+#error	CONFIG_SYS_SDRAM_BASE must be defined!
+#endif
+#ifndef CONFIG_SYS_SDRAM_SIZE
+#error	CONFIG_SYS_SDRAM_SIZE must be defined!
+#endif
+
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Serial Info */
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_ENV_SIZE			0x2000
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE		1024	/* Console buffer size */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* version string, parser, etc */
+
+/* Enable Time Command */
+
+#endif /* __BCM_EP_BOARD_H */
diff --git a/include/configs/bcm_northstar2.h b/include/configs/bcm_northstar2.h
new file mode 100644
index 0000000..754bf2e
--- /dev/null
+++ b/include/configs/bcm_northstar2.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Broadcom NS2.
+ */
+
+#ifndef __BCM_NORTHSTAR2_H
+#define __BCM_NORTHSTAR2_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_HOSTNAME				"northstar2"
+
+/* Physical Memory Map */
+#define V2M_BASE				0x80000000
+#define PHYS_SDRAM_1				V2M_BASE
+
+#define PHYS_SDRAM_1_SIZE			(4UL * SZ_1G)
+#define PHYS_SDRAM_2_SIZE			(4UL * SZ_1G)
+#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
+
+/* define text_base for U-boot image */
+#define CONFIG_SYS_INIT_SP_ADDR			(PHYS_SDRAM_1 + 0x7ff00)
+#define CONFIG_SYS_LOAD_ADDR			0x90000000
+#define CONFIG_SYS_MALLOC_LEN			SZ_16M
+
+/* Serial Configuration */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE		(-4)
+#define CONFIG_SYS_NS16550_CLK			25000000
+#define CONFIG_SYS_NS16550_COM1			0x66100000
+#define CONFIG_SYS_NS16550_COM2			0x66110000
+#define CONFIG_SYS_NS16550_COM3			0x66120000
+#define CONFIG_SYS_NS16550_COM4			0x66130000
+#define CONFIG_BAUDRATE				115200
+
+#define CONFIG_ENV_SIZE				SZ_8K
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE			SZ_1K
+#define CONFIG_SYS_MAXARGS			64
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
+
+/* version string, parser, etc */
+
+#endif /* __BCM_NORTHSTAR2_H */
diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h
new file mode 100644
index 0000000..b843705
--- /dev/null
+++ b/include/configs/bcmstb.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018  Cisco Systems, Inc.
+ *
+ * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
+ *
+ * Configuration settings for the Broadcom BCMSTB SoC family.
+ */
+
+#ifndef __BCMSTB_H
+#define __BCMSTB_H
+
+#include "version.h"
+#include <linux/sizes.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+struct bcmstb_boot_parameters {
+	u32 r0;
+	u32 r1;
+	u32 r2;
+	u32 r3;
+	u32 sp;
+	u32 lr;
+};
+
+extern struct bcmstb_boot_parameters bcmstb_boot_parameters;
+
+extern phys_addr_t prior_stage_fdt_address;
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * CPU configuration.
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Memory configuration.
+ *
+ * The prior stage BOLT bootloader sets up memory for us.
+ *
+ * An example boot memory layout after loading everything is:
+ *
+ *	 0x0000 8000	vmlinux.bin.gz
+ *	       :	[~31 MiB uncompressed max]
+ *	 0x01ef f000	FIT containing signed public key
+ *	       :	[~2 KiB in size]
+ *	 0x01f0 0000	DTB copied from prior-stage-provided region
+ *	       :	[~1 MiB max]
+ *	 0x0200 0000	FIT containing ramdisk and device tree
+ *             :	  initramfs.cpio.gz
+ *	       :	  [~208 MiB uncompressed max, to CMA/bmem low address]
+ *	       :	  [~80 MiB compressed max, to PSB low address]
+ *             :	  device tree binary
+ *             :	  [~60 KiB]
+ *	 0x0700 0000	Prior stage bootloader (PSB)
+ *	       :
+ *	 0x0761 7000	Prior-stage-provided device tree binary (DTB)
+ *	       :	[~40 KiB in size]
+ *	 0x0f00 0000	Contiguous memory allocator (CMA/bmem) low address
+ *	       :
+ *	 0x8010 0000	U-Boot code at ELF load address
+ *	       :	[~500 KiB in size, stripped]
+ *	 0xc000 0000	Top of RAM
+ *
+ * Setting gd->relocaddr to CONFIG_SYS_TEXT_BASE in dram_init_banksize
+ * prevents U-Boot from relocating itself when it is run as an ELF
+ * program by the prior stage bootloader.
+ *
+ * We want to keep the ramdisk and FDT in the FIT image in-place, to
+ * accommodate stblinux's bmem and CMA regions.  To accomplish this,
+ * we set initrd_high and fdt_high to 0xffffffff, and the load and
+ * entry addresses of the FIT ramdisk entry to 0x0.
+ *
+ * Overwriting the prior stage bootloader causes memory instability,
+ * so the compressed initramfs needs to fit between the load address
+ * and the PSB low address.  In BOLT's default configuration this
+ * limits the compressed size of the initramfs to approximately 80
+ * MiB.  However, BOLT can be configured to allow loading larger
+ * initramfs images, in which case this limitation is eliminated.
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x100000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
+					 CONFIG_SYS_INIT_RAM_SIZE -	\
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		0x2000000
+
+/*
+ * CONFIG_SYS_LOAD_ADDR - 1 MiB.
+ */
+#define CONFIG_SYS_FDT_SAVE_ADDRESS	0x1f00000
+#define CONFIG_SYS_CBSIZE		512
+#define CONFIG_SYS_MAXARGS		32
+
+/*
+ * Large kernel image bootm configuration.
+ */
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+/*
+ * NS16550 configuration.
+ */
+#define V_NS16550_CLK			81000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * Serial console configuration.
+ */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+					 115200}
+
+/*
+ * Informational display configuration.
+ */
+#define CONFIG_REVISION_TAG
+
+/*
+ * Command configuration.
+ */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_MMC
+
+/*
+ * Flash configuration.
+ */
+#define CONFIG_ST_SMI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_MACRONIX
+
+/*
+ * Filesystem configuration.
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT4
+#define CONFIG_FS_EXT4
+#define CONFIG_CMD_FS_GENERIC
+
+/*
+ * Environment configuration.
+ */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64 KiB */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Save the prior stage provided DTB.
+ */
+/*
+ * Enable in-place RFS with this initrd_high setting.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"fdtsaveaddr=" __stringify(CONFIG_SYS_FDT_SAVE_ADDRESS) "\0"	\
+	"initrd_high=0xffffffff\0"					\
+	"fdt_high=0xffffffff\0"
+
+/*
+ * Set fdtaddr to prior stage-provided DTB in board_late_init, when
+ * writeable environment is available.
+ */
+#define CONFIG_BOARD_LATE_INIT
+
+#endif /* __BCMSTB_H */
diff --git a/include/configs/beaver.h b/include/configs/beaver.h
new file mode 100644
index 0000000..4c5826c
--- /dev/null
+++ b/include/configs/beaver.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra30-common.h"
+
+/* VDD core PMIC */
+#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Beaver"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_BEAVER
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* SPI */
+#define CONFIG_TEGRA_SLINK_CTRLS       6
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h
new file mode 100644
index 0000000..c05b06a
--- /dev/null
+++ b/include/configs/bg0900.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIGS_BG0900_H__
+#define __CONFIGS_BG0900_H__
+
+/* Memory configuration */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x10000000	/* Max 256 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_ENV_OVERWRITE
+
+/* FEC Ethernet on SoC */
+#ifdef	CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#endif
+
+/* Boot Linux */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTCOMMAND	"bootm"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"update_spi_firmware_filename=u-boot.sb\0"			\
+	"update_spi_firmware_maxsz=0x80000\0"				\
+	"update_spi_firmware="	/* Update the SPI flash firmware */	\
+		"if sf probe 2:0 ; then "				\
+		"if tftp ${update_spi_firmware_filename} ; then "	\
+		"sf erase 0x0 +${filesize} ; "				\
+		"sf write ${loadaddr} 0x0 ${filesize} ; "		\
+		"fi ; "							\
+		"fi\0"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_BG0900_H__ */
diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h
new file mode 100644
index 0000000..a9f45f1
--- /dev/null
+++ b/include/configs/bitmain_antminer_s9.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2018 Michal Simek <monstr@monstr.eu>
+ */
+
+#ifndef __CONFIG_BITMAIN_ANTMINER_S9_H
+#define __CONFIG_BITMAIN_ANTMINER_S9_H
+
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_SIZE	0x40000000
+
+#define CONFIG_BOOTP_SERVERIP
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"autoload=no\0" \
+	"pxefile_addr_r=0x2000000\0" \
+	"scriptaddr=0x3000000\0" \
+	"kernel_addr_r=0x2000000\0" \
+	"fdt_high=0xefff000\0" \
+	"initrd_high=0xefff000\0" \
+	"devnum=0\0" \
+	"wdstop=mw f8005000 ABC000\0" \
+	BOOTENV
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_BITMAIN_ANTMINER_S9_H */
diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h
new file mode 100644
index 0000000..285e28b
--- /dev/null
+++ b/include/configs/bk4r1.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright 2016 3ADEV <http://3adev.com>
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Configuration settings for BK4R1.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Define the BK4r1-specific env commands */
+#define BK4_EXTRA_ENV_SETTINGS \
+	"bootlimit=3\0" \
+	"eraseuserdata=false\0" \
+	"altbootcmd=led 5 on; " \
+		"boot\0" \
+	"set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \
+	"set_gpio102=mw 0x400ff0c4 0x40; mw 0x40048198 0x000011bf\0" \
+	"set_gpio96=mw 0x40048180 0x282; mw 0x400ff0c4 0x1\0"\
+	"set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"\
+	"set_gpio6=mw 0x40048018 0x282; mw 0x400ff008 0x40\0"\
+	"manage_userdata=" MANAGE_USERDATA "\0"\
+	"ncenable=true\0"\
+	"ncserverip=192.168.0.77\0"\
+	"if_netconsole=ping $ncserverip\0"\
+	"start_netconsole=setenv ncip $serverip; setenv bootdelay 10;" \
+	     "setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \
+	"preboot=" BK4_NET_INIT \
+		"if ${ncenable}; then run if_netconsole start_netconsole; fi\0"
+
+/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/
+#define BK4_BOOTCOMMAND "run set_gpio122; run set_gpio96; sf probe; " \
+			"run manage_userdata; "
+
+/* Enable PREBOOT variable */
+
+/* Set ARP_TIMEOUT to 500ms */
+#define CONFIG_ARP_TIMEOUT 500UL
+
+/* Set ARP_TIMEOUT_COUNT to 3 repetitions */
+#define CONFIG_NET_RETRY_COUNT	5
+
+/* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */
+#define BK4_NET_INIT "run set_gpio122;"
+
+/* Check if userdata volume shall be erased */
+#define MANAGE_USERDATA "if ${eraseuserdata}; " \
+						"then ubi part system; " \
+						"ubi remove userdata; " \
+						"ubi create userdata; " \
+						"ubi detach; " \
+						"setenv eraseuserdata false; " \
+						"saveenv; " \
+						"fi; "
+
+/* Autoboot options */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Enter passphrase to stop autoboot, booting in %d seconds\n"
+#define CONFIG_AUTOBOOT_STOP_STR "123"
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 4 * SZ_1M)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* NAND support */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define IMX_FEC1_BASE			ENET1_BASE_ADDR
+
+/* QSPI Configs*/
+#ifdef CONFIG_FSL_QSPI
+#define FSL_QSPI_FLASH_SIZE		(SZ_16M)
+#define FSL_QSPI_FLASH_NUM		2
+#define CONFIG_SYS_FSL_QSPI_LE
+#endif
+
+#define CONFIG_LOADADDR	0x82000000
+
+/* We boot from the gfxRAM area of the OCRAM. */
+#define CONFIG_BOARD_SIZE_LIMIT		520192
+
+/* boot command, including the target-defined one if any */
+#define CONFIG_BOOTCOMMAND	BK4_BOOTCOMMAND "run bootcmd_nand"
+
+/* Extra env settings (including the target-defined ones if any) */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	BK4_EXTRA_ENV_SETTINGS \
+	"autoload=no\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"blimg_file=u-boot.vyb\0" \
+	"blimg_addr=0x81000000\0" \
+	"dtbkernel_file=fitImage\0" \
+	"dtbkernel_addr=0x82000000\0" \
+	"ram_file=uRamdisk\0" \
+	"ram_addr=0x83000000\0" \
+	"filesys=rootfs.ubifs\0" \
+	"sys_addr=0x81000000\0" \
+	"nfs_root=/path/to/nfs/root\0" \
+	"tftptimeout=1000\0" \
+	"tftptimeoutcountmax=1000000\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"ipaddr=192.168.0.60\0" \
+	"serverip=192.168.0.1\0" \
+	"bootargs_base=setenv bootargs rw " \
+	"console=ttyLP1,115200n8\0" \
+	"bootargs_sd=setenv bootargs ${bootargs} " \
+		"root=/dev/mmcblk0p2 rootwait\0" \
+	"bootargs_nand=setenv bootargs ${bootargs} " \
+		"ubi.mtd=5 rootfstype=" \
+				"ubifs root=ubi0:rootfs${active_workset}\0" \
+	"bootargs_ram=setenv bootargs ${bootargs} " \
+		"root=/dev/ram rw initrd=${ram_addr}\0" \
+	"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
+		"fatload mmc 0:2 ${dtbkernel_addr} ${dtbkernel_file}; " \
+		"bootm ${dtbkernel_addr}\0" \
+	"bootcmd_nand=sf probe;run bootargs_base bootargs_nand bootargs_mtd; " \
+		"ubi part dtbkernel; " \
+		"ubi readvol ${dtbkernel_addr} dtbkernel${active_workset}; " \
+		"led 0 on; " \
+		"bootm ${dtbkernel_addr}\0" \
+	"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
+		"nand read ${fdt_addr} dtb; " \
+		"nand read ${kernel_addr} kernel; " \
+		"nand read ${ram_addr} root; " \
+		"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
+	"update_bootloader_from_sd=if fatload mmc 0:2 ${blimg_addr} " \
+		"${blimg_file}; " \
+		"then sf probe; " \
+		"mtdparts default; " \
+		"nand erase.part bootloader; " \
+		"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
+	"update_bootloader_from_tftp=if tftp ${blimg_addr} "\
+		"${tftpdir}${blimg_file}; "\
+		"then sf probe; " \
+		"mtdparts default; " \
+		"nand erase.part bootloader; " \
+		"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
+	"update_dtbkernel_from_sd=if fatload mmc 0:2 ${dtbkernel_addr} " \
+		"${dtbkernel_file}; " \
+		"then sf probe; " \
+		"ubi part dtbkernel; " \
+		"ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \
+		"${filesize}; " \
+		"ubi detach; fi\0" \
+	"update_dtbkernel_from_tftp=if tftp ${dtbkernel_addr} " \
+		"${tftpdir}${dtbkernel_file}; " \
+		"then sf probe; " \
+		"ubi part dtbkernel; " \
+		"ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \
+		"${filesize}; " \
+		"ubi detach; fi\0" \
+	"update_ramdisk_from_sd=if fatload mmc 0:2 ${ram_addr} " \
+		"${ram_file}; " \
+		"then sf probe; " \
+		"mtdparts default; " \
+		"nand erase.part initrd; " \
+		"nand write ${ram_addr} initrd ${filesize}; fi\0" \
+	"update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
+		"then sf probe; " \
+		"nand erase.part initrd; " \
+		"nand write ${ram_addr} initrd ${filesize}; fi\0" \
+	"update_rootfs_from_sd=if fatload mmc 0:2 ${sys_addr} " \
+		"${filesys}; " \
+		"then sf probe; " \
+		"ubi part system; " \
+		"ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \
+		"ubi detach; fi\0" \
+	"update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
+		"then sf probe; " \
+		"ubi part system; " \
+		"ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \
+		"ubi detach; fi\0" \
+	"setup_dtbkernel=nand erase.part dtbkernel; " \
+		"ubi part dtbkernel; " \
+		"ubi create dtbkernel1 972000 s; " \
+		"ubi create dtbkernel2 972000 s; " \
+		"ubi detach\0" \
+	"setup_system=nand erase.part system; " \
+		"ubi part system; " \
+		"ubi create rootfs1 15E15000 d; " \
+		"ubi create rootfs2 15E15000 d; " \
+		"ubi create userdata; " \
+		"ubi detach\0" \
+	"setup_nor1=" BK4_NET_INIT \
+		"if tftp ${sys_addr} ${tftpdir}ubinor1.img; " \
+		"then sf probe 0:0; " \
+		"sf erase 0 01000000; " \
+		"mtdparts default; " \
+		"ubi part nor; " \
+		"ubi create nor1fs; " \
+		"ubi write ${sys_addr} nor1fs ${filesize}; " \
+		"ubi detach; fi\0" \
+	"setup_nor2=" BK4_NET_INIT \
+		"if tftp ${sys_addr} ${tftpdir}ubinor2.img; " \
+		"then sf probe 0:1; " \
+		"sf erase 0 01000000; " \
+		"mtdparts default; " \
+		"ubi part nor; " \
+		"ubi create nor2fs; " \
+		"ubi write ${sys_addr} nor2fs ${filesize}; " \
+		"ubi detach; fi\0" \
+	"prepare_install_bk4r1_envs=" \
+		"echo 'Preparing envs for SD card recovery!';" \
+		"setenv ipaddr 192.168.0.99;" \
+		"setenv serverip 192.168.0.50;" \
+		"\0" \
+	"install_bk4r1rs="\
+		"led 0 on; " \
+		"nand erase.chip; mtdparts default; "\
+		"led 1 on; "\
+		"run setup_dtbkernel; " \
+		"run setup_system; " \
+		"led 2 on;" \
+		"run update_bootloader_from_sd; "\
+		"run update_dtbkernel_from_sd; "\
+		"run update_rootfs_from_sd; "\
+		"setenv bootcmd 'run bootcmd_nand'; "\
+		"saveenv; " \
+		"led 3 on; " \
+		"echo Finished - Please Power off, REMOVE SDCARD and set boot" \
+			"source to NAND\0" \
+	"active_workset=1\0"
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START	0x80010000
+#define CONFIG_SYS_MEMTEST_END		0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical memory map */
+#define PHYS_SDRAM			(0x80000000)
+#define PHYS_SDRAM_SIZE		(SZ_512M)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE	(SZ_128K)
+#define CONFIG_ENV_SIZE		(SZ_8K)
+#define CONFIG_ENV_OFFSET	0x200000
+#define CONFIG_ENV_SIZE_REDUND	(SZ_8K)
+#define CONFIG_ENV_OFFSET_REDUND	0x220000
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/blanche.h b/include/configs/blanche.h
new file mode 100644
index 0000000..8774bde
--- /dev/null
+++ b/include/configs/blanche.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/configs/blanche.h
+ *     This file is blanche board configuration.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ */
+
+#ifndef __BLANCHE_H
+#define __BLANCHE_H
+
+#include "rcar-gen2-common.h"
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
+#define STACK_AREA_SIZE			0x00100000
+#define LOW_LEVEL_MERAM_STACK \
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE		0x40000000
+#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* FLASH */
+#if !defined(CONFIG_MTD_NOR_FLASH)
+#define CONFIG_SH_QSPI_BASE	0xE6B10000
+#else
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+#undef  CONFIG_CMD_SF
+#undef  CONFIG_CMD_SPI
+#endif
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK	20000000u
+#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+
+/* ENV setting */
+#if !defined(CONFIG_MTD_NOR_FLASH)
+#else
+#undef  CONFIG_ENV_ADDR
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+#endif
+
+#endif	/* __BLANCHE_H */
diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h
new file mode 100644
index 0000000..573ff3e
--- /dev/null
+++ b/include/configs/bmips_bcm3380.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM3380_H
+#define __CONFIG_BMIPS_BCM3380_H
+
+#include <linux/sizes.h>
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	166500000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM3380_H */
diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h
new file mode 100644
index 0000000..c7e7119
--- /dev/null
+++ b/include/configs/bmips_bcm6318.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6318_H
+#define __CONFIG_BMIPS_BCM6318_H
+
+#include <linux/sizes.h>
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	166500000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6318_H */
diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h
new file mode 100644
index 0000000..45f26bb
--- /dev/null
+++ b/include/configs/bmips_bcm63268.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM63268_H
+#define __CONFIG_BMIPS_BCM63268_H
+
+#include <linux/sizes.h>
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	200000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM63268_H */
diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
new file mode 100644
index 0000000..8d59438
--- /dev/null
+++ b/include/configs/bmips_bcm6328.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6328_H
+#define __CONFIG_BMIPS_BCM6328_H
+
+#include <linux/sizes.h>
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	160000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6328_H */
diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h
new file mode 100644
index 0000000..38dd9e3
--- /dev/null
+++ b/include/configs/bmips_bcm6338.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6338_H
+#define __CONFIG_BMIPS_BCM6338_H
+
+#include <linux/sizes.h>
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	120000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xbfc00000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6338_H */
diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
new file mode 100644
index 0000000..061d6b2
--- /dev/null
+++ b/include/configs/bmips_bcm6348.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6348_H
+#define __CONFIG_BMIPS_BCM6348_H
+
+#include <linux/sizes.h>
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	128000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* USB */
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xbfc00000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6348_H */
diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h
new file mode 100644
index 0000000..583217d
--- /dev/null
+++ b/include/configs/bmips_bcm6358.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6358_H
+#define __CONFIG_BMIPS_BCM6358_H
+
+#include <linux/sizes.h>
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	150000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xbe000000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6358_H */
diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h
new file mode 100644
index 0000000..570bc3b
--- /dev/null
+++ b/include/configs/bmips_bcm6362.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6362_H
+#define __CONFIG_BMIPS_BCM6362_H
+
+#include <linux/sizes.h>
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	200000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6362_H */
diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h
new file mode 100644
index 0000000..ab5bdac
--- /dev/null
+++ b/include/configs/bmips_bcm6368.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6368_H
+#define __CONFIG_BMIPS_BCM6368_H
+
+#include <linux/sizes.h>
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	200000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xb8000000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6368_H */
diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h
new file mode 100644
index 0000000..f1ff054
--- /dev/null
+++ b/include/configs/bmips_bcm6838.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6838_H
+#define __CONFIG_BMIPS_BCM6838_H
+
+#include <linux/sizes.h>
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	160000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_1M
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	SZ_8K
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM6838_H */
diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h
new file mode 100644
index 0000000..3cb2d40
--- /dev/null
+++ b/include/configs/bmips_common.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __CONFIG_BMIPS_COMMON_H
+#define __CONFIG_BMIPS_COMMON_H
+
+#include <linux/sizes.h>
+
+/* ETH */
+#define CONFIG_PHY_RESET_DELAY		20
+#define CONFIG_SYS_RX_ETH_BUFFER	6
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		SZ_2M
+#define CONFIG_SYS_BOOTPARAMS_LEN	SZ_128K
+#define CONFIG_SYS_CBSIZE		SZ_512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#endif /* __CONFIG_BMIPS_COMMON_H */
diff --git a/include/configs/boston.h b/include/configs/boston.h
new file mode 100644
index 0000000..61aaa26
--- /dev/null
+++ b/include/configs/boston.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ */
+
+#ifndef __CONFIGS_BOSTON_H__
+#define __CONFIGS_BOSTON_H__
+
+/*
+ * General board configuration
+ */
+#define CONFIG_SYS_BOOTM_LEN		(64 * 1024 * 1024)
+
+/*
+ * CPU
+ */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	30000000
+
+/*
+ * PCI
+ */
+
+/*
+ * Memory map
+ */
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
+#else
+# define CONFIG_SYS_SDRAM_BASE		0x80000000
+#endif
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x08000000)
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+
+/*
+ * Console
+ */
+
+/*
+ * Flash
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+#define CONFIG_SYS_MAX_FLASH_SECT		1024
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#ifdef CONFIG_64BIT
+# define CONFIG_ENV_ADDR \
+	(0xffffffffb8000000 + (128 << 20) - CONFIG_ENV_SIZE)
+#else
+# define CONFIG_ENV_ADDR \
+	(0xb8000000 + (128 << 20) - CONFIG_ENV_SIZE)
+#endif
+
+#endif /* __CONFIGS_BOSTON_H__ */
diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h
new file mode 100644
index 0000000..a0f7ead
--- /dev/null
+++ b/include/configs/broadcom_bcm963158.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN		(16 * 1024 * 1024)
+
+/*
+ * 63158
+ */
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/* U-Boot */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif /* CONFIG_NAND */
+
+/*
+ * bcm963158
+ */
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
diff --git a/include/configs/broadcom_bcm968380gerg.h b/include/configs/broadcom_bcm968380gerg.h
new file mode 100644
index 0000000..b0e9337
--- /dev/null
+++ b/include/configs/broadcom_bcm968380gerg.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6838.h>
+
+#define CONFIG_ENV_SIZE	SZ_8K
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif /* CONFIG_NAND */
diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h
new file mode 100644
index 0000000..fdb6203
--- /dev/null
+++ b/include/configs/broadcom_bcm968580xref.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ */
+
+#include <linux/sizes.h>
+
+/*
+ * common
+ */
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 500000, 1500000 }
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+/*
+ * 6858
+ */
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/* U-Boot */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_16M)
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif /* CONFIG_NAND */
+
+/*
+ * 968580xref
+ */
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h
new file mode 100644
index 0000000..bc0dabb
--- /dev/null
+++ b/include/configs/brppt1.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * brtpp1.h
+ *
+ * specific parts for B&R T-Series Motherboard
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ */
+
+#ifndef __CONFIG_BRPPT1_H__
+#define __CONFIG_BRPPT1_H__
+
+#include <configs/bur_cfg_common.h>
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+/* memory */
+#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN		SZ_32M
+
+/* Clock Defines */
+#define V_OSCK				26000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_POWER_TPS65217
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+/*#define CONFIG_MACH_TYPE		3589*/
+#define CONFIG_MACH_TYPE		0xFFFFFFFF /* TODO: check with kernel*/
+
+/*
+ * When we have NAND flash we expect to be making use of mtdparts,
+ * both for ease of use in U-Boot and for passing information on to
+ * the Linux kernel.
+ */
+
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_SPL_ARGS_ADDR		0x80F80000
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
+
+/* NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0x140000
+#endif /* CONFIG_NAND */
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_NAND
+#define NANDTGTS \
+"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+"cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \
+" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
+"nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \
+	"root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \
+"b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \
+	"run nandargs; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
+"b_tgts_std=usb0 nand net\0" \
+"b_tgts_rcy=net usb0 nand\0" \
+"b_tgts_pme=usb0 nand net\0"
+#else
+#define NANDTGTS ""
+#endif /* CONFIG_NAND */
+
+#define MMCSPI_TGTS \
+"t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
+	"b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \
+"b_t30lgcy#0=" \
+	"load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \
+	"load ${loaddev}:2 ${loadaddr} /boot/zImage && " \
+	"load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb || " \
+	"load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\
+	"run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \
+"t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \
+	"b_mode=${b_mode}\0" \
+"b_t30lgcy#1=" \
+	"load ${loaddev}:1 ${loadaddr} zImage && " \
+	"load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \
+	"load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \
+	"run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \
+"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \
+"b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \
+"b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \
+"b_tgts_rcy=t30lgcy#1 usb0 net\0" \
+"b_tgts_pme=net usb0 mmc0 mmc1\0" \
+"loaddev=mmc 1\0"
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define MMCTGTS \
+MMCSPI_TGTS \
+"cfgscr=mw ${dtbaddr} 0;" \
+" mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \
+" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
+#else
+#define MMCTGTS ""
+#endif /* CONFIG_MMC */
+
+#ifdef CONFIG_SPI
+#define SPITGTS \
+MMCSPI_TGTS \
+"cfgscr=mw ${dtbaddr} 0;" \
+" sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \
+" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0"
+#else
+#define SPITGTS ""
+#endif /* CONFIG_SPI */
+
+#define LOAD_OFFSET(x)			0x8##x
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+BUR_COMMON_ENV \
+"verify=no\0" \
+"autoload=0\0" \
+"scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \
+"cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \
+"dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \
+"loadaddr=" __stringify(LOAD_OFFSET(0100000)) "\0" \
+"ramaddr=" __stringify(LOAD_OFFSET(2000000)) "\0" \
+"console=ttyO0,115200n8\0" \
+"optargs=consoleblank=0 quiet panic=2\0" \
+"b_break=0\0" \
+"b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \
+"b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \
+MMCTGTS \
+SPITGTS \
+NANDTGTS \
+"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
+" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
+" else setenv b_tgts ${b_tgts_std}; fi\0" \
+"b_default=run b_deftgts; for target in ${b_tgts};"\
+" do echo \"### booting ${target} ###\"; run b_${target};" \
+" if test ${b_break} = 1; then; exit; fi; done\0"
+#endif /* !CONFIG_SPL_BUILD*/
+
+#ifdef CONFIG_NAND
+/*
+ * GPMC  block.  We support 1 device and the physical address to
+ * access CS0 at is 0x8000000.
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x8000000
+/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, \
+					10, 11, 12, 13, 14, 15, 16, 17, \
+					18, 19, 20, 21, 22, 23, 24, 25, \
+					26, 27, 28, 29, 30, 31, 32, 33, \
+					34, 35, 36, 37, 38, 39, 40, 41, \
+					42, 43, 44, 45, 46, 47, 48, 49, \
+					50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_NAND_OMAP_GPMC_WSCFG	1
+#endif /* CONFIG_NAND */
+
+#if defined(CONFIG_SPI)
+/* SPI Flash */
+/* Environment */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND		(CONFIG_ENV_OFFSET + \
+						 CONFIG_ENV_SECT_SIZE)
+#elif defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x40000	/* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+/* No NAND env support in SPL */
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#else
+#error "no storage for Environment defined!"
+#endif
+
+#endif	/* ! __CONFIG_BRPPT1_H__ */
diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h
new file mode 100644
index 0000000..19e796e
--- /dev/null
+++ b/include/configs/brsmarc1.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * brsmarc1.h
+ *
+ * specific parts for B&R BRSMARC1 Motherboard
+ *
+ * Copyright (C) 2017 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * B&R Industrial Automation GmbH - http://www.br-automation.com
+ *
+ */
+
+#ifndef __CONFIG_BRSMARC1_H__
+#define __CONFIG_BRSMARC1_H__
+
+#include <configs/bur_cfg_common.h>
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+#define CONFIG_BOARD_TYPES
+
+/* memory */
+#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+/* Clock Defines */
+#define V_OSCK				26000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_MACH_TYPE		3589
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+BUR_COMMON_ENV \
+"autoload=0\0" \
+"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+"cfgscr=mw ${dtbaddr} 0;" \
+" sf probe && sf read ${scradr} 0xC0000 0x10000 && source ${scradr};" \
+" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \
+"dtbaddr=0x84000000\0" \
+"loadaddr=0x82000000\0" \
+"b_break=0\0" \
+"b_tgts_std=mmc0 mmc1 def net usb0\0" \
+"b_tgts_rcy=def net usb0\0" \
+"b_tgts_pme=net usb0 mmc0 mmc1\0" \
+"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
+" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
+" else setenv b_tgts ${b_tgts_std}; fi\0" \
+"b_mmc0=load mmc 1 ${scradr} bootscr.img && source ${scradr}\0" \
+"b_mmc1=load mmc 1 ${loadaddr} arimg.ugz && run startsys\0" \
+"b_def=sf read ${loadaddr} 100000 700000; run startsys\0" \
+"b_net=tftp ${scradr} netscript.img && source ${scradr}\0" \
+"b_usb0=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}\0" \
+"b_default=run b_deftgts; for target in ${b_tgts};"\
+" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" \
+"vxargs=setenv bootargs cpsw(0,0)host:vxWorks h=${serverip}" \
+" e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks\0" \
+"vxfdt=fdt addr ${dtbaddr}; fdt resize 0x8000;" \
+" fdt boardsetup\0" \
+"startsys=run vxargs && mw 0x80001100 0 && run vxfdt &&" \
+" bootm ${loadaddr} - ${dtbaddr}\0"
+#endif /* !CONFIG_SPL_BUILD*/
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* SPI Flash */
+
+/* Environment */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND		(CONFIG_ENV_OFFSET + \
+						 CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_CONS_INDEX			1
+#endif	/* __CONFIG_BRSMARC1_H__ */
diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h
new file mode 100644
index 0000000..c6e308b
--- /dev/null
+++ b/include/configs/brxre1.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * brxre1.h
+ *
+ * specific parts for B&R KWB Motherboard
+ *
+ * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ */
+
+#ifndef __CONFIG_BRXRE1_H__
+#define __CONFIG_BRXRE1_H__
+
+#include <configs/bur_cfg_common.h>
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+#define CONFIG_AM335X_LCD
+#define LCD_BPP				LCD_COLOR32
+
+/* memory */
+#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
+
+/* Clock Defines */
+#define V_OSCK				26000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_MACH_TYPE		3589
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+BUR_COMMON_ENV \
+"autoload=0\0" \
+"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+"bootaddr=0x80001100\0" \
+"bootdev=cpsw(0,0)\0" \
+"vx_romfsbase=0x800E0000\0" \
+"vx_romfssize=0x20000\0" \
+"vx_memtop=0x8FBEF000\0" \
+"loadromfs=mmc read ${vx_romfsbase} 700 100\0" \
+"loadaddr=0x80100000\0" \
+"startvx=run loadromfs; bootvx ${loadaddr}\0" \
+"b_break=0\0" \
+"b_tgts_std=mmc def net usb0\0" \
+"b_tgts_rcy=def net usb0\0" \
+"b_tgts_pme=net usb0 mmc\0" \
+"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \
+" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \
+" else setenv b_tgts ${b_tgts_std}; fi\0" \
+"b_mmc=load mmc 1 ${loadaddr} arimg && run startvx\0" \
+"b_def=mmc read ${loadaddr} 800 8000; run startvx\0" \
+"b_net=tftp ${scradr} netscript.img && source ${scradr}\0" \
+"b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}\0" \
+"b_default=run b_deftgts; for target in ${b_tgts};"\
+" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0"
+#endif /* !CONFIG_SPL_BUILD*/
+
+#define CONFIG_BOOTCOMMAND		"mmc dev 1; run b_default"
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* Environment */
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_OFFSET		0x40000	/* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#endif	/* __CONFIG_BRXRE1_H__ */
diff --git a/include/configs/bubblegum_96.h b/include/configs/bubblegum_96.h
new file mode 100644
index 0000000..e1dc37b
--- /dev/null
+++ b/include/configs/bubblegum_96.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board configuration file for Bubblegum-96
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _BUBBLEGUM_96_H_
+#define _BUGGLEGUM_96_H_
+
+/* SDRAM Definitions */
+#define CONFIG_SYS_SDRAM_BASE		0x0
+#define CONFIG_SYS_SDRAM_SIZE		0x80000000
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		(24000000)	/* 24MHz */
+
+#define CONFIG_SYS_MALLOC_LEN		(32 * 1024 * 1024)
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7ffc0)
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x7ff00)
+
+/* UART Definitions */
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_ENV_SIZE			0x2000
+
+/* Console configuration */
+#define CONFIG_SYS_CBSIZE		1024	/* Console buffer size */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#endif
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
new file mode 100644
index 0000000..42e3e56
--- /dev/null
+++ b/include/configs/bur_am335x_common.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * bur_am335x_common.h
+ *
+ * common parts used by B&R AM335x based boards
+ *
+ * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ */
+
+#ifndef __BUR_AM335X_COMMON_H__
+#define __BUR_AM335X_COMMON_H__
+/* ------------------------------------------------------------------------- */
+
+/* legacy #defines for non DM bur-board */
+#ifndef CONFIG_DM
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(48000000)
+#define CONFIG_SYS_NS16550_COM1		0x44e09000
+
+#define CONFIG_I2C
+#define CONFIG_SYS_I2C
+
+#endif /* CONFIG_DM */
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+
+/* Timer information */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_POWER_TPS65217
+
+#include <asm/arch/omap.h>
+
+/*
+ * SPL related defines.  The Public RAM memory map the ROM defines the
+ * area between 0x402F0400 and 0x4030B800 as a download area and
+ * 0x4030B800 to 0x4030CE00 as a public stack area.  The ROM also
+ * supports X-MODEM loading via UART, and we leverage this and then use
+ * Y-MODEM to load u-boot.img, when booted over UART.  We must also include
+ * the scratch space that U-Boot uses in SRAM.
+ */
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif /* !CONFIG_SPL_BUILD, ... */
+/*
+ * Our DDR memory always starts at 0x80000000 and U-Boot shall have
+ * relocated itself to higher in memory by the time this value is used.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x80000000
+/*
+ * ----------------------------------------------------------------------------
+ * DDR information.  We say (for simplicity) that we have 1 bank,
+ * always, even when we have more.  We always start at 0x80000000,
+ * and we place the initial stack pointer in our SRAM.
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
+					GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Our platforms make use of SPL to initalize the hardware (primarily
+ * memory) enough for full U-Boot to be loaded.  We also support Falcon
+ * Mode so that the Linux kernel can be booted directly from SPL
+ * instead, if desired.  We make use of the general SPL framework found
+ * under common/spl/.  Given our generally common memory map, we set a
+ * number of related defaults and sizes here.
+ */
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack.  We load U-Boot itself into memory at
+ * 0x80800000 for legacy reasons (to not conflict with older SPLs).  We
+ * have our BSS be placed 1MiB after this, to allow for the default
+ * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
+ * We have the SPL malloc pool at the end of the BSS area.
+ *
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SPL_BSS_START_ADDR	0x80A00000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
+
+/* General parts of the framework, required. */
+
+#endif	/* ! __BUR_AM335X_COMMON_H__ */
diff --git a/include/configs/bur_cfg_common.h b/include/configs/bur_cfg_common.h
new file mode 100644
index 0000000..dff4123
--- /dev/null
+++ b/include/configs/bur_cfg_common.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * bur_cfg_common.h
+ *
+ * common parts used over all B&R boards
+ *
+ * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ */
+
+#ifndef __BUR_CFG_COMMON_H__
+#define __BUR_CFG_COMMON_H__
+/* ------------------------------------------------------------------------- */
+#define BUR_COMMON_ENV \
+"usbscript=usb start && fatload usb 0 ${scradr} usbscript.img &&" \
+" source ${scradr}\0" \
+"brdefaultip=if test -r ${ipaddr}; then; else" \
+" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \
+" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \
+"netconsole=echo switching to network console ...; " \
+"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \
+"setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \
+"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \
+"setenv stdout nc;setenv stdin nc;setenv stderr nc\0"
+
+/* Network defines */
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		10
+
+/* Network console */
+#define CONFIG_NETCONSOLE		1
+#define CONFIG_BOOTP_MAY_FAIL		/* if we don't have DHCP environment */
+
+#define CONFIG_ENV_OVERWRITE		/* Overwrite ethaddr / serial# */
+
+/* As stated above, the following choices are optional. */
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS		64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+
+#endif	/* __BUR_CFG_COMMON_H__ */
diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
new file mode 100644
index 0000000..89deeac
--- /dev/null
+++ b/include/configs/caddy2.h
@@ -0,0 +1,333 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * esd vme8349 U-Boot configuration file
+ * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
+ *
+ * (C) Copyright 2006-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * reinhard.arlt@esd-electronics.de
+ * Based on the MPC8349EMDS config.
+ */
+
+/*
+ * vme8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+
+/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
+
+#undef CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM
+#define SPD_EEPROM_ADDRESS		0x54
+#define CONFIG_SYS_READ_SPD		vme8349_read_spd
+#define CONFIG_SYS_83XX_DDR_USES_CS0	/* esd; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* DDR is sys memory*/
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
+					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+#define CONFIG_SYS_DDRCDR		(DDRCDR_DHC_EN \
+					| DDRCDR_ODT \
+					| DDRCDR_Q_DRN)
+					/* 0x80080001 */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE		0xffc00000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		4		/* flash size in MB */
+
+
+#define CONFIG_SYS_WINDOW1_BASE		0xf0000000
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device*/
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase TO (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write TO (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xF7000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000		/* size */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Malloc size */
+
+#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR + 0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
+
+#define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0xFIXME
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_GMII			/* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define CONFIG_PHY_M88E1111
+#define TSEC1_PHY_ADDR		0x08
+#define TSEC2_PHY_ADDR		0x10
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0xc0000)
+	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_RTC_BUS_NUM  0x01
+#define CONFIG_SYS_I2C_RTC_ADDR	0x32
+
+/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x000043f0
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Init Memory map for Linux*/
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR	0x00100000
+#define CONFIG_SYS_GPIO1_DAT	0x00100000
+
+#define CONFIG_SYS_GPIO2_PRELIM
+#define CONFIG_SYS_GPIO2_DIR	0x78900000
+#define CONFIG_SYS_GPIO2_DAT	0x70100000
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME		"VME8349"
+#define CONFIG_ROOTPATH		"/tftpboot/rootfs"
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_LOADADDR		800000	/* def location for tftp and bootm */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=vme8349\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"		\
+	"update=protect off fff00000 fff3ffff; "			\
+		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+	"upd=run load update\0"						\
+	"fdtaddr=780000\0"						\
+	"fdtfile=vme8349.dtb\0"						\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#ifndef __ASSEMBLY__
+int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
+		     unsigned char *buffer, int len);
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
new file mode 100644
index 0000000..8d541a1
--- /dev/null
+++ b/include/configs/cardhu.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra30-common.h"
+
+/* VDD core PMIC */
+#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Cardhu"
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+	"board_name=cardhu-a04\0" \
+	"fdtfile=tegra30-cardhu-a04.dtb\0"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_CARDHU
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* SPI */
+#define CONFIG_TEGRA_SLINK_CTRLS       6
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h
new file mode 100644
index 0000000..e6abfe2
--- /dev/null
+++ b/include/configs/cei-tk1-som.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (c) Copyright 2016, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ *
+ * Based on jetson-tk1.h which is:
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"CEI tk1-som"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* SPI */
+#define CONFIG_SPI_FLASH_SIZE		(4 << 20)
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#define CONFIG_ARMV7_PSCI			1
+#define CONFIG_ARMV7_PSCI_NR_CPUS		4
+/* Reserve top 1M for secure RAM */
+#define CONFIG_ARMV7_SECURE_BASE		0xfff00000
+#define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
new file mode 100644
index 0000000..f109b22
--- /dev/null
+++ b/include/configs/cgtqmx6eval.h
@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *
+ * Congatec Conga-QEVAl board configuration file.
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Based on Freescale i.MX6Q Sabre Lite board configuration file.
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Leo Sartre, <lsartre@adeneo-embedded.com>
+ */
+
+#ifndef __CONFIG_CGTQMX6EVAL_H
+#define __CONFIG_CGTQMX6EVAL_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE	4122
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+/* SPI NOR */
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+
+/* Thermal support */
+#define CONFIG_IMX_THERMAL
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
+
+#define CONFIG_USBD_HS
+
+/* Framebuffer */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_HDMI
+
+/* SATA */
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		6
+#define CONFIG_PHY_ATHEROS
+
+/* Command definition */
+
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+#define CONSOLE_DEV	"ttymxc1"
+#define CONFIG_MMCROOT		"/dev/mmcblk0p2"
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"fdtfile=undefined\0" \
+	"fdt_addr_r=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"console=" CONSOLE_DEV "\0" \
+	"dfuspi=dfu 0 sf 0:0:10000000:0\0" \
+	"dfu_alt_info_spl=spl raw 0x400\0" \
+	"dfu_alt_info_img=u-boot raw 0x10000\0" \
+	"dfu_alt_info=spl raw 0x400\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"findfdt="\
+		"if test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-qmx6.dtb; fi; " \
+		"if test $board_rev = MX6DL ; then " \
+			"setenv fdtfile imx6dl-qmx6.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine dtb to use; fi; \0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+				"bootz ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\
+
+#define CONFIG_BOOTCOMMAND \
+	"run spilock;"	    \
+	"run findfdt; "	\
+	"mmc dev ${mmcdev};" \
+	"if mmc rescan; then " \
+		"if run loadbootscript; then " \
+		"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END	       0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#if defined (CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#endif
+
+#endif			       /* __CONFIG_CGTQMX6EVAL_H */
diff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h
new file mode 100644
index 0000000..77ace93
--- /dev/null
+++ b/include/configs/cherryhill.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(2 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=usbkbd,serial\0" \
+					"stdout=vidconsole,serial\0" \
+					"stderr=vidconsole,serial\0"
+
+/* Environment configuration */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_ENV_OFFSET		0x005f0000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
new file mode 100644
index 0000000..13c15bd
--- /dev/null
+++ b/include/configs/chiliboard.h
@@ -0,0 +1,175 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Grinn - http://grinn-global.com/
+ */
+
+#ifndef __CONFIG_CHILIBOARD_H
+#define __CONFIG_CHILIBOARD_H
+
+#include <configs/ti_am335x_common.h>
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+#endif
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define NANDARGS \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} ${optargs} " \
+		"${mtdparts} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdt_addr} NAND.u-boot-spl-os; " \
+		"nand read ${loadaddr} NAND.kernel; " \
+		"bootz ${loadaddr} - ${fdt_addr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run mmcboot; " \
+	"run nandboot; " \
+	"run netboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"fdt_addr=0x87800000\0" \
+	"boot_fdt=try\0" \
+	"console=ttyO0,115200n8\0" \
+	"image=zImage\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"ip_dyn=yes\0" \
+	"optargs=\0" \
+	"loadbootscript=" \
+		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+		"${boot_dir}/${image}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
+		"${boot_dir}/${fdt_file}\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} ${optargs} " \
+		"${mtdparts} " \
+		"root=${mmcroot}\0" \
+	"mmcloados=run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadimage; then " \
+				"run mmcloados;" \
+			"fi;" \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} ${optargs} " \
+		"${mtdparts} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	NANDARGS
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+
+/* SPL */
+/* Bootcount using the RTC block */
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+/* NAND: driver related configs */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
+/* NAND: SPL related configs */
+
+/* USB configuration */
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#else
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* Network. */
+#define CONFIG_PHY_SMSC
+
+#endif	/* ! __CONFIG_CHILIBOARD_H */
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
new file mode 100644
index 0000000..f26e463
--- /dev/null
+++ b/include/configs/chromebook_link.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+#include <configs/x86-chromebook.h>
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x003f8000
+
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h
new file mode 100644
index 0000000..2f7dd69
--- /dev/null
+++ b/include/configs/chromebook_samus.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+#include <configs/x86-chromebook.h>
+
+#undef CONFIG_STD_DEVICES_SETTINGS
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,i8042-kbd,serial\0" \
+					"stdout=vidconsole,serial\0" \
+					"stderr=vidconsole,serial\0"
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x003f8000
+
+#define CONFIG_TPL_TEXT_BASE		0xfffd8000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h
new file mode 100644
index 0000000..a7c2606
--- /dev/null
+++ b/include/configs/chromebox_panther.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+#include <configs/x86-chromebook.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ci20.h b/include/configs/ci20.h
new file mode 100644
index 0000000..21a8632
--- /dev/null
+++ b/include/configs/ci20.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * CI20 configuration
+ *
+ * Copyright (c) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ */
+
+#ifndef __CONFIG_CI20_H__
+#define __CONFIG_CI20_H__
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Ingenic JZ4780 clock configuration. */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_MHZ			1200
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+/* Memory configuration */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000 /* cached (KSEG0) address */
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+#define CONFIG_SYS_LOAD_ADDR		0x81000000
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x88000000
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+/* NS16550-ish UARTs */
+#define CONFIG_SYS_NS16550_CLK		48000000
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* Ethernet: davicom DM9000 */
+#define CONFIG_DRIVER_DM9000		1
+#define CONFIG_DM9000_BASE		0xb6000000
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 2)
+
+/* Environment */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			(32 << 10)
+#define CONFIG_ENV_OFFSET		((14 + 512) << 10)
+#define CONFIG_ENV_OVERWRITE
+
+/* Command line configuration. */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+
+/* Miscellaneous configuration options */
+#define CONFIG_SYS_BOOTM_LEN		(64 << 20)
+
+/* SPL */
+#define CONFIG_SPL_STACK		0xf4008000 /* only max. 2KB spare! */
+
+#define CONFIG_SPL_MAX_SIZE		((14 * 1024) - 0xa00)
+
+#define CONFIG_SPL_BSS_START_ADDR	0xf4004000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00002000 /* 512KB, arbitrary */
+
+#define CONFIG_SPL_START_S_PATH		"arch/mips/mach-jz47xx"
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x1c	/* 14 KiB offset */
+
+#endif /* __CONFIG_CI20_H__ */
diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h
new file mode 100644
index 0000000..d0a60c2
--- /dev/null
+++ b/include/configs/cl-som-imx7.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 CompuLab, Ltd.
+ *
+ * Configuration settings for the CompuLab CL-SOM-iMX7 System-on-Module.
+ */
+
+#ifndef __CL_SOM_IMX7_CONFIG_H
+#define __CL_SOM_IMX7_CONFIG_H
+
+#include "mx7_common.h"
+
+#define CONFIG_MXC_UART_BASE            UART1_IPS_BASE_ADDR
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+/* ENET1 */
+#define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE3000
+#define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
+
+/* I2C configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C2		/* Enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define SYS_I2C_BUS_SOM			0
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	SYS_I2C_BUS_SOM
+
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x20
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x20, 16} }
+
+#undef CONFIG_SYS_AUTOLOAD
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_SYS_AUTOLOAD		"no"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"autoload=off\0" \
+	"script=boot.scr\0" \
+	"loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \
+	"loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \
+	"loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${fdtfile};\0" \
+	"bootscript=echo Running bootscript from ${storagetype} ...; source ${loadaddr};\0" \
+	"storagebootcmd=echo Booting from ${storagetype} ...; run ${storagetype}args; run doboot;\0" \
+	"kernel=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdtfile=imx7d-sbc-imx7.dtb\0" \
+	"fdtaddr=0x83000000\0" \
+	"mmcdev_def="__stringify(CONFIG_SYS_MMC_DEV)"\0" \
+	"usbdev_def="__stringify(CONFIG_SYS_USB_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"usbpart=" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) "\0" \
+	"doboot=bootz ${loadaddr} - ${fdtaddr}\0" \
+	"mmc_config=mmc dev ${mmcdev}; mmc rescan\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/mmcblk${mmcblk}p2 rootwait rw\0" \
+	"mmcbootscript=" \
+		"if run mmc_config; then " \
+			"setenv storagetype mmc;" \
+			"setenv storagedev ${mmcdev}:${mmcpart};" \
+			"if run loadscript; then " \
+				"run bootscript; " \
+			"fi; " \
+		"fi;\0" \
+	"mmcboot=" \
+		"if run mmc_config; then " \
+			"setenv storagetype mmc;" \
+			"setenv storagedev ${mmcdev}:${mmcpart};" \
+			"if run loadkernel; then " \
+				"if run loadfdt; then " \
+					"run storagebootcmd;" \
+				"fi; " \
+			"fi; " \
+		"fi;\0" \
+	"sdbootscript=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; " \
+		"run mmcbootscript\0" \
+	"usbbootscript=setenv usbdev ${usbdev_def}; " \
+		"setenv storagetype usb;" \
+		"setenv storagedev ${usbdev}:${usbpart};" \
+		"if run loadscript; then " \
+			"run bootscript; " \
+		"fi; " \
+	"sdboot=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; run mmcboot\0" \
+	"emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\0" \
+	"emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"echo SD boot attempt ...; run sdbootscript; run sdboot; " \
+	"echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \
+	"echo USB boot attempt ...; run usbbootscript; "
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* SPI Flash support */
+
+/* FLASH and environment organization */
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+
+/* MMC Config*/
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC1_BASE_ADDR
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2" /* USDHC1 */
+#endif
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* Uncomment to enable iMX thermal driver support */
+/*#define CONFIG_IMX_THERMAL*/
+
+/* SPL */
+#include "imx7_spl.h"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h
new file mode 100644
index 0000000..9d20a5e
--- /dev/null
+++ b/include/configs/clearfog.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_CLEARFOG_H
+#define _CONFIG_CLEARFOG_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * SDIO/MMC Card Configuration
+ */
+#define CONFIG_SYS_MMC_BASE		MVEBU_SDIO_BASE
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+#define CONFIG_ENV_MIN_ENTRIES		128
+
+/* Environment in MMC */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SECT_SIZE		0x200
+#define CONFIG_ENV_SIZE			0x10000
+/*
+ * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC
+ * boot image starts @ LBA-0.
+ * As result in MMC/eMMC case it will be a 1 sector gap between u-boot
+ * image and environment
+ */
+#define CONFIG_ENV_OFFSET		0xf0000
+#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* SATA support */
+#ifdef CONFIG_SCSI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define RELOCATION_LIMITS_ENV_SETTINGS	\
+	"fdt_high=0x10000000\0"		\
+	"initrd_high=0x10000000\0"
+
+/* SPL */
+
+/* Defines for SPL */
+#define CONFIG_SPL_SIZE			(140 << 10)
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI)
+/* SPL related SPI defines */
+#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA)
+/* SPL related MMC defines */
+#define CONFIG_SYS_MMC_U_BOOT_OFFS		(160 << 10)
+#define CONFIG_SYS_U_BOOT_OFFS			CONFIG_SYS_MMC_U_BOOT_OFFS
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER	0x00180000	/* in SDRAM */
+#endif
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Include the common distro boot environment */
+#ifndef CONFIG_SPL_BUILD
+
+#ifdef CONFIG_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_USB(func) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#define KERNEL_ADDR_R	__stringify(0x800000)
+#define FDT_ADDR_R	__stringify(0x100000)
+#define RAMDISK_ADDR_R	__stringify(0x1800000)
+#define SCRIPT_ADDR_R	__stringify(0x200000)
+#define PXEFILE_ADDR_R	__stringify(0x300000)
+
+#define LOAD_ADDRESS_ENV_SETTINGS \
+	"kernel_addr_r=" KERNEL_ADDR_R "\0" \
+	"fdt_addr_r=" FDT_ADDR_R "\0" \
+	"ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
+	"scriptaddr=" SCRIPT_ADDR_R "\0" \
+	"pxefile_addr_r=" PXEFILE_ADDR_R "\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	RELOCATION_LIMITS_ENV_SETTINGS \
+	LOAD_ADDRESS_ENV_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+	"console=ttyS0,115200\0" \
+	BOOTENV
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* _CONFIG_CLEARFOG_H */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
new file mode 100644
index 0000000..b957e9c
--- /dev/null
+++ b/include/configs/cm_fx6.h
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Config file for Compulab CM-FX6 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Nikita Kiryanov <nikita@compulab.co.il>
+ */
+
+#ifndef __CONFIG_CM_FX6_H
+#define __CONFIG_CM_FX6_H
+
+#include "mx6_common.h"
+
+/* Machine config */
+#define CONFIG_SYS_LITTLE_ENDIAN
+#define CONFIG_MACH_TYPE		4273
+
+/* MMC */
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* RAM */
+#define PHYS_SDRAM_1			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_2			MMDC1_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Serial console */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART4_BASE
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/* SPI flash */
+
+/* MTD support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SPI_FLASH_MTD
+#endif
+
+/* Environment */
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_addr_r=0x18000000\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdtfile=undefined\0" \
+	"stdin=serial,usbkbd\0" \
+	"stdout=serial,vga\0" \
+	"stderr=serial,vga\0" \
+	"panel=HDMI\0" \
+	"autoload=no\0" \
+	"uImage=uImage-cm-fx6\0" \
+	"zImage=zImage-cm-fx6\0" \
+	"kernel=uImage-cm-fx6\0" \
+	"dtb=cm-fx6.dtb\0" \
+	"console=ttymxc3,115200\0" \
+	"ethprime=FEC0\0" \
+	"video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \
+	"video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \
+	"doboot=bootm ${kernel_addr_r}\0" \
+	"doloadfdt=false\0" \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"setboottypez=setenv kernel ${zImage};" \
+		"setenv doboot bootz ${kernel_addr_r} - ${fdt_addr_r};" \
+		"setenv doloadfdt true;\0" \
+	"setboottypem=setenv kernel ${uImage};" \
+		"setenv doboot bootm ${kernel_addr_r};" \
+		"setenv doloadfdt false;\0"\
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"sataroot=/dev/sda2 rw rootwait\0" \
+	"nandroot=/dev/mtdblock4 rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"mmcargs=setenv bootargs console=${console} root=${mmcroot} " \
+		"${video} ${extrabootargs}\0" \
+	"sataargs=setenv bootargs console=${console} root=${sataroot} " \
+		"${video} ${extrabootargs}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} " \
+		"${video} ${extrabootargs}\0" \
+	"nandboot=if run nandloadkernel; then " \
+			"run nandloadfdt;" \
+			"run setboottypem;" \
+			"run storagebootcmd;" \
+			"run setboottypez;" \
+			"run storagebootcmd;" \
+		"fi;\0" \
+	"run_eboot=echo Starting EBOOT ...; "\
+		"mmc dev 2 && " \
+		"mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \
+	"loadkernel=load ${storagetype} ${storagedev} ${kernel_addr_r} ${kernel};\0"\
+	"loadfdt=load ${storagetype} ${storagedev} ${fdt_addr_r} ${dtb};\0" \
+	"nandloadkernel=nand read ${kernel_addr_r} 0 780000;\0" \
+	"nandloadfdt=nand read ${fdt_addr_r} 780000 80000;\0" \
+	"setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \
+	"setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \
+	"setupnandboot=setenv storagetype nand;\0" \
+	"storagebootcmd=echo Booting from ${storagetype} ...;" \
+			"run ${storagetype}args; run doboot;\0" \
+	"trybootk=if run loadkernel; then " \
+		"if ${doloadfdt}; then " \
+			"run loadfdt;" \
+		"fi;" \
+		"run storagebootcmd;" \
+		"fi;\0" \
+	"trybootsmz=" \
+		"run setboottypem;" \
+		"run trybootk;" \
+		"run setboottypez;" \
+		"run trybootk;\0" \
+	"legacy_bootcmd=" \
+		"run setupmmcboot;" \
+		"mmc dev ${storagedev};" \
+		"if mmc rescan; then " \
+			"run trybootsmz;" \
+		"fi;" \
+		"run setupsataboot;" \
+		"if sata init; then " \
+			"run trybootsmz;" \
+		"fi;" \
+		"run setupnandboot;" \
+		"run nandboot;\0" \
+	"findfdt="\
+		"if test $board_name = Utilite && test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-utilite-pro.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine dtb to use; fi; \0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(MMC, mmc, 2) \
+	func(SATA, sata, 0)
+
+#include <config_distro_bootcmd.h>
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS
+#endif
+
+/* NAND */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* APBH DMA is required for NAND support */
+#endif
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_ETHPRIME			"FEC0"
+#define CONFIG_ARP_TIMEOUT		200UL
+#define CONFIG_NET_RETRY_COUNT		5
+
+/* USB */
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_MXC_I2C3_SPEED	400000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	2
+
+/* SATA */
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_LBA48
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+
+/* Boot */
+#define CONFIG_SYS_BOOTMAPSZ	        (8 << 20)
+#define CONFIG_SERIAL_TAG
+
+/* misc */
+#define CONFIG_SYS_MALLOC_LEN			(10 * 1024 * 1024)
+
+/* SPL */
+#include "imx6_spl.h"
+
+/* Display */
+#define CONFIG_IMX_HDMI
+
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SOURCE
+#define CONFIG_VIDEO_BMP_RLE8
+
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+
+/* EEPROM */
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#endif	/* __CONFIG_CM_FX6_H */
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
new file mode 100644
index 0000000..54f2cea
--- /dev/null
+++ b/include/configs/cm_t335.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Config file for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ */
+
+#ifndef __CONFIG_CM_T335_H
+#define __CONFIG_CM_T335_H
+
+#define CONFIG_CM_T335
+
+#include <configs/ti_am335x_common.h>
+
+#undef CONFIG_MAX_RAM_BANK_SIZE
+#define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)	/* 512MB */
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_CM_T335
+
+/* Clock Defines */
+#define V_OSCK				25000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#ifndef CONFIG_SPL_BUILD
+#define MMCARGS \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"mmcrootfstype=ext4\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0"
+
+#define NANDARGS \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandroot=ubi0:rootfs rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} " \
+		"ubi.mtd=${rootfs_name}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nboot ${loadaddr} nand0 900000; " \
+		"bootm ${loadaddr}\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=82000000\0" \
+	"console=ttyO0,115200n8\0" \
+	"rootfs_name=rootfs\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	MMCARGS \
+	NANDARGS
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD		"no"
+
+/* Serial console configuration */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
+
+/* SPL */
+
+/* Network. */
+#define CONFIG_PHY_ATHEROS
+
+/* NAND support */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#undef CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000
+
+#define CONFIG_ENV_OFFSET		0x300000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x500000
+#endif
+
+/* GPIO pin + bank to pin ID mapping */
+#define GPIO_PIN(_bank, _pin)		((_bank << 5) + _pin)
+
+/* Status LED */
+/* Status LED polarity is inversed, so init it in the "off" state */
+
+/* EEPROM */
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Enable PCA9555 at I2C0-0x26.
+ * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
+ */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x26
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x26, 16} }
+#endif /* CONFIG_SPL_BUILD */
+
+#endif	/* __CONFIG_CM_T335_H */
+
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
new file mode 100644
index 0000000..f9a6444
--- /dev/null
+++ b/include/configs/cm_t35.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 CompuLab, Ltd.
+ * Mike Rapoport <mike@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * Based on omap3_beagle.h
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_CM_T3X	/* working with CM-T35 and CM-T3730 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/*
+ * Size of malloc() pool
+ */
+					/* Sector */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+
+/* commands to include */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * TWL4030
+ */
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+
+/* Environment information */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"usbtty=cdc_acm\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=500\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"nandroot=/dev/mtdblock4 rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 2a0000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD		"no"
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
+								/* works on */
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_ENV_ADDR			0x260000
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
+					 CONFIG_SYS_INIT_RAM_SIZE -	\
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Status LED */
+#define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */
+
+#define CONFIG_SPLASHIMAGE_GUARD
+
+/* Display Configuration */
+#define LCD_BPP		LCD_COLOR16
+
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SOURCE
+#define CONFIG_BMP_16BPP
+#define CONFIG_SCF0403_LCD
+
+/* Defines for SPL */
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+/*
+ * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
+ * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
+ */
+#define CONFIG_SYS_NAND_ECCPOS		{ 1, 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12 }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+
+/*
+ * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
+ * older x-loader implementations. And move the BSS area so that it
+ * doesn't overlap with TEXT_BASE.
+ */
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/* EEPROM */
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
new file mode 100644
index 0000000..1314cf9
--- /dev/null
+++ b/include/configs/cm_t43.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * cm_t43.h
+ *
+ * Copyright (C) 2015 Compulab, Ltd.
+ */
+
+#ifndef __CONFIG_CM_T43_H
+#define __CONFIG_CM_T43_H
+
+#define CONFIG_CM_T43
+#define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2GB */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+
+#include <asm/arch/omap.h>
+
+/* Serial support */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK		48000000
+#define CONFIG_SYS_NS16550_COM1		0x44e09000
+#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#endif
+
+/* NAND support */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+/* CPSW Ethernet support */
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_SYS_RX_ETH_BUFFER	64
+
+/* USB support */
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_AM437X_USB2PHY2_HOST
+
+/* Power */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_TPS65218
+
+/* Enabling L2 Cache */
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE		0x48242000
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_HSMMC2_8BIT
+
+#include <configs/ti_armv7_omap.h>
+#undef CONFIG_SYS_MONITOR_LEN
+
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"fdtaddr=0x81200000\0" \
+	"bootm_size=0x8000000\0" \
+	"autoload=no\0" \
+	"console=ttyO0,115200n8\0" \
+	"fdtfile=am437x-sb-som-t43.dtb\0" \
+	"kernel=zImage-cm-t43\0" \
+	"bootscr=bootscr.img\0" \
+	"emmcroot=/dev/mmcblk0p2 rw\0" \
+	"emmcrootfstype=ext4 rootwait\0" \
+	"emmcargs=setenv bootargs console=${console} " \
+		"root=${emmcroot} " \
+		"rootfstype=${emmcrootfstype}\0" \
+	"loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"emmcboot=echo Booting from emmc ... && " \
+		"run emmcargs && " \
+		"load mmc 1 ${loadaddr} ${kernel} && " \
+		"load mmc 1 ${fdtaddr} ${fdtfile} && " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev 0; " \
+	"if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"fi; " \
+	"fi; " \
+	"mmc dev 1; " \
+	"if mmc rescan; then " \
+		"run emmcboot; " \
+	"fi;"
+
+/* SPL defines. */
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + (128 << 20))
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+/* EEPROM */
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+#endif	/* __CONFIG_CM_T43_H */
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
new file mode 100644
index 0000000..2387f86
--- /dev/null
+++ b/include/configs/cm_t54.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Config file for Compulab CM-T54 board
+ *
+ * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
+ */
+
+#ifndef __CONFIG_CM_T54_H
+#define __CONFIG_CM_T54_H
+
+#define CONFIG_CM_T54
+#define CONFIG_DRAM_2G
+
+#define PARTS_DEFAULT
+
+#include <configs/ti_omap5_common.h>
+
+/* EEPROM related defines */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_BUS	0
+
+/* Enable SD/MMC CD and WP GPIOs */
+#define OMAP_HSMMC_USE_GPIO
+
+/* UART setup */
+#define CONFIG_SYS_NS16550_COM4		UART4_BASE
+
+/* MMC ENV related defines */
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_SIZE
+
+#define CONFIG_SYS_MMC_ENV_DEV		1		/* SLOT2: eMMC(1) */
+#define CONFIG_SYS_MMC_ENV_PART		0
+#define CONFIG_ENV_OFFSET		0xc0000		/* (in bytes) 768 KB */
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_HSMMC2_8BIT
+
+/* SATA Boot related defines */
+#define CONFIG_SPL_SATA_BOOT_DEVICE		0
+#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION	1
+
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+/* USB UHH support options */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO	76 /* HSIC2 HUB #RESET */
+#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO	83 /* HSIC3 ETH #RESET */
+
+/* Enabled commands */
+
+/* EEPROM */
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_EEPROM_SIZE			256
+
+/* USB Networking options */
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CONFIG_SYS_AUTOLOAD
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_SYS_AUTOLOAD		"no"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"baudrate=115200\0" \
+	"bootdelay=3\0" \
+	"autoload=no\0" \
+	"bootscr=bootscr.img\0" \
+	"fdtfile=omap5-sbc-t54.dtb\0" \
+	"kernel=zImage-cm-t54\0" \
+	"ramdisk=ramdisk-cm-t54.img\0" \
+	"console=ttyO3\0" \
+	"ramdisksize=16384\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk1p2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} rw rootwait\0" \
+	"ramroot=/dev/ram0\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"root=${ramroot} ramdisk_size=${ramdisksize} rw\0" \
+	"mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
+	"mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
+	"mmcloadramdisk=load mmc ${mmcdev} ${rdaddr} ${ramdisk}\0" \
+	"mmcloadbootscript=load mmc ${mmcdev} ${loadaddr} ${bootsrc}\0" \
+	"mmcbootscript=echo Running bootscript from mmc${mmcdev}...; " \
+			"source ${loadaddr}\0" \
+	"mmcbootlinux=echo Booting from mmc${mmcdev} ...; " \
+			"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+	"mmcboot=if mmc dev ${mmcdev} && mmc rescan; then " \
+			"if run mmcloadbootscript; " \
+				"then run mmcbootscript; " \
+			"fi; " \
+			"if run mmcloadkernel; then " \
+				"if run mmcloadfdt; then " \
+					"if run mmcloadramdisk; then " \
+						"run ramargs; " \
+						"run mmcbootlinux; " \
+					"fi; " \
+					"run mmcargs; " \
+					"setenv rdaddr - ; " \
+					"run mmcbootlinux; " \
+				"fi; " \
+			"fi; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"bootcmd=run mmcboot || setenv mmcdev 1; setenv mmcroot /dev/mmcblk0p2; run mmcboot;"
+
+#endif /* __CONFIG_CM_T54_H */
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
new file mode 100644
index 0000000..337c875
--- /dev/null
+++ b/include/configs/cobra5272.h
@@ -0,0 +1,336 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Sentec Cobra Board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ */
+
+/* ---
+ * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
+ * Date: 2004-03-29
+ * Author: Florian Schlote
+ *
+ * For a description of configuration options please refer also to the
+ * general u-boot-1.x.x/README file
+ * ---
+ */
+
+/* ---
+ * board/config.h - configuration options, board specific
+ * ---
+ */
+
+#ifndef _CONFIG_COBRA5272_H
+#define _CONFIG_COBRA5272_H
+
+/* ---
+ * Defines processor clock - important for correct timings concerning serial
+ * interface etc.
+ * ---
+ */
+
+#define CONFIG_SYS_CLK			66000000
+#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+
+/* ---
+ * Enable use of Ethernet
+ * ---
+ */
+#define CONFIG_MCFFEC
+
+/* Enable Dma Timer */
+#define CONFIG_MCFTMR
+
+/* ---
+ * Define baudrate for UART1 (console output, tftp, ...)
+ * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
+ * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
+ * interface
+ * ---
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+/* ---
+ * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
+ * timeout acc. to your needs
+ * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
+ * for 10 sec
+ * ---
+ */
+
+#if 0
+#define CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
+#endif
+
+/* ---
+ * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
+ * bootloader residing in flash ('chainloading'); if you want to use
+ * chainloading or want to compile a u-boot binary that can be loaded into
+ * RAM via BDM set
+ *	"#if 0" to "#if 1"
+ * You will need a first stage bootloader then, e. g. colilo or a working BDM
+ * cable (Background Debug Mode)
+ *
+ * Setting #if 0: u-boot will start from flash and relocate itself to RAM
+ *
+ * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
+ * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
+ *
+ * ---
+ */
+
+#if 0
+#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
+#endif
+
+/* ---
+ * Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ * ---
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#else
+#define CONFIG_ENV_ADDR		0xffe04000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#endif
+
+#define LDS_BOARD_TEXT \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	env/embedded.o(.text);
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+/*
+ *-----------------------------------------------------------------------------
+ * Define user parameters that have to be customized most likely
+ *-----------------------------------------------------------------------------
+ */
+
+/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
+
+/* The following settings will be contained in the environment block ; if you
+want to use a neutral environment all those settings can be manually set in
+u-boot: 'set' command */
+
+#if 0
+
+#define CONFIG_BOOTCOMMAND	"bootm 0xffe80000"	/*Autoboto command, please
+enter a valid image address in flash */
+
+/* User network settings */
+
+#define CONFIG_IPADDR 192.168.100.2		/* default board IP address */
+#define CONFIG_SERVERIP 192.168.100.1	/* default tftp server IP address */
+
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x20000		/*Defines default RAM address
+from which user programs will be started */
+
+/*---*/
+
+/*
+ *-----------------------------------------------------------------------------
+ * End of user parameters to be customized
+ *-----------------------------------------------------------------------------
+ */
+
+/* ---
+ * Defines memory range for test
+ * ---
+ */
+
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+/* ---
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * ---
+ */
+
+/* ---
+ * Base register address
+ * ---
+ */
+
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+
+/* ---
+ * System Conf. Reg. & System Protection Reg.
+ * ---
+ */
+
+#define CONFIG_SYS_SCR			0x0003
+#define CONFIG_SYS_SPR			0xffff
+
+/* ---
+ * Ethernet settings
+ * ---
+ */
+
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_ENET_BD_BASE	0x780000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in internal SRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/*
+ *-------------------------------------------------------------------------
+ * RAM SIZE (is defined above)
+ *-----------------------------------------------------------------------
+ */
+
+/* #define CONFIG_SYS_SDRAM_SIZE		16 */
+
+/*
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xffe00000
+
+#ifdef	CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE	0x20000
+#else
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000	/* flash timeout */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ *
+ * Please refer also to Motorola Coldfire user manual - Chapter XXX
+ * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
+ */
+#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
+#define CONFIG_SYS_OR0_PRELIM		0xFFE00014
+
+#define CONFIG_SYS_BR1_PRELIM		0
+#define CONFIG_SYS_OR1_PRELIM		0
+
+#define CONFIG_SYS_BR2_PRELIM		0
+#define CONFIG_SYS_OR2_PRELIM		0
+
+#define CONFIG_SYS_BR3_PRELIM		0
+#define CONFIG_SYS_OR3_PRELIM		0
+
+#define CONFIG_SYS_BR4_PRELIM		0
+#define CONFIG_SYS_OR4_PRELIM		0
+
+#define CONFIG_SYS_BR5_PRELIM		0
+#define CONFIG_SYS_OR5_PRELIM		0
+
+#define CONFIG_SYS_BR6_PRELIM		0
+#define CONFIG_SYS_OR6_PRELIM		0
+
+#define CONFIG_SYS_BR7_PRELIM		0x00000701
+#define CONFIG_SYS_OR7_PRELIM		0xFF00007C
+
+/*-----------------------------------------------------------------------
+ * LED config
+ */
+#define	LED_STAT_0	0xffff /*all LEDs off*/
+#define	LED_STAT_1	0xfffe
+#define	LED_STAT_2	0xfffd
+#define	LED_STAT_3	0xfffb
+#define	LED_STAT_4	0xfff7
+#define	LED_STAT_5	0xffef
+#define	LED_STAT_6	0xffdf
+#define	LED_STAT_7	0xff00 /*all LEDs on*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration (GPIO)
+ */
+#define CONFIG_SYS_PACNT		0x00000000		/* PortA control reg.: All pins are external
+GPIO*/
+#define CONFIG_SYS_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
+(1^=output, 0^=input) */
+#define CONFIG_SYS_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
+#define CONFIG_SYS_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
+configuration */
+#define CONFIG_SYS_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
+#define CONFIG_SYS_PBDAT		0x0000			/* PortB value reg. */
+#define CONFIG_SYS_PDCNT		0x00000000		/* PortD control reg. */
+
+#endif	/* _CONFIG_COBRA5272_H */
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
new file mode 100644
index 0000000..de94eb9
--- /dev/null
+++ b/include/configs/colibri-imx6ull.h
@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 Toradex AG
+ *
+ * Configuration settings for the Colibri iMX6ULL module.
+ *
+ * based on colibri_imx7.h
+ */
+
+#ifndef __COLIBRI_IMX6ULL_CONFIG_H
+#define __COLIBRI_IMX6ULL_CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_IOMUX_LPSR
+
+#define PHYS_SDRAM_SIZE			SZ_512M
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
+/* Network */
+#define CONFIG_TFTP_TSIZE
+
+/* ENET1 */
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+
+/* MMC Config */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+/* I2C configs */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_IPADDR			192.168.10.2
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_SERVERIP			192.168.10.1
+
+#define FDT_FILE "imx6ull-colibri${variant}-${fdt_board}.dtb"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"fdt_addr_r=0x82100000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"pxefile_addr_r=0x87100000\0" \
+	"ramdisk_addr_r=0x82200000\0" \
+	"scriptaddr=0x87000000\0"
+
+#define NFS_BOOTCMD \
+	"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
+	"nfsboot=run setup; " \
+		"setenv bootargs ${defargs} ${nfsargs} " \
+		"${setupargs} ${vidargs}; echo Booting from NFS...;" \
+		"dhcp ${kernel_addr_r} && " \
+		"tftp ${fdt_addr_r} " FDT_FILE " && " \
+		"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define UBI_BOOTCMD \
+	"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \
+		"ubi.fm_autoconvert=1\0" \
+	"ubiboot=run setup; " \
+		"setenv bootargs ${defargs} ${ubiargs} " \
+		"${setupargs} ${vidargs}; echo Booting from NAND...; " \
+		"ubi part ubi &&" \
+		"ubi read ${kernel_addr_r} kernel && " \
+		"ubi read ${fdt_addr_r} dtb && " \
+		"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define CONFIG_BOOTCOMMAND "run ubiboot; " \
+	"setenv fdtfile " FDT_FILE " && run distro_bootcmd;"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
+	MEM_LAYOUT_ENV_SETTINGS \
+	NFS_BOOTCMD \
+	UBI_BOOTCMD \
+	"console=ttymxc0\0" \
+	"defargs=user_debug=30\0" \
+	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
+	"fdt_board=eval-v3\0" \
+	"fdt_fixup=;\0" \
+	"ip_dyn=yes\0" \
+	"kernel_file=zImage\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
+		"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
+		"${board}/flash_eth.img && source ${loadaddr}\0" \
+	"setsdupdate=mmc rescan && setenv interface mmc && " \
+		"fatload ${interface} 0:1 ${loadaddr} " \
+		"${board}/flash_blk.img && source ${loadaddr}\0" \
+	"setup=setenv setupargs " \
+		"console=tty1 console=${console}" \
+		",${baudrate}n8 ${memargs} consoleblank=0\0" \
+	"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
+	"setusbupdate=usb start && setenv interface usb && " \
+		"fatload ${interface} 0:1 ${loadaddr} " \
+		"${board}/flash_blk.img && source ${loadaddr}\0" \
+	"splashpos=m,m\0" \
+	"videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \
+	"vidargs=video=mxsfb:640x480M-16@60"
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x08000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#if defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_OFFSET		(28 * CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#endif
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */
+#define CONFIG_SYS_NAND_BASE		-1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_USBD_HS
+
+/* USB Device Firmware Update support */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_16M
+#define DFU_DEFAULT_POLL_TIMEOUT	300
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
+#define CONFIG_VIDEO_MXS
+#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#endif /* __COLIBRI_IMX6ULL_CONFIG_H */
diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h
new file mode 100644
index 0000000..ab98da6
--- /dev/null
+++ b/include/configs/colibri-imx8x.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 Toradex
+ */
+
+#ifndef __COLIBRI_IMX8X_H
+#define __COLIBRI_IMX8X_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define USDHC1_BASE_ADDR		0x5b010000
+#define USDHC2_BASE_ADDR		0x5b020000
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Networking */
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_TFTP_TSIZE
+
+#define CONFIG_IPADDR			192.168.10.2
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_SERVERIP			192.168.10.1
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"fdt_addr_r=0x83000000\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"ramdisk_addr_r=0x83800000\0" \
+	"scriptaddr=0x80800000\0"
+
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
+/* Boot M4 */
+#define M4_BOOT_ENV \
+	"m4_0_image=m4_0.bin\0" \
+	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+		"${m4_0_image}\0" \
+	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+
+#define MFG_NAND_PARTITION ""
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc g_mass_storage.stall=0 " \
+		"g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \
+		"g_mass_storage.idProduct=0x37FF " \
+		"g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \
+		"${vidargs} clk_ignore_unused\0" \
+	"initrd_addr=0x83800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \
+		"${fdt_addr};\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	AHAB_ENV \
+	BOOTENV \
+	CONFIG_MFG_ENV_SETTINGS \
+	M4_BOOT_ENV \
+	MEM_LAYOUT_ENV_SETTINGS \
+	"boot_file=Image\0" \
+	"console=ttyLP3 earlycon\0" \
+	"fdt_addr=0x83000000\0"	\
+	"fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \
+	"fdtfile=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \
+	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+	"image=Image\0" \
+	"initrd_addr=0x83800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=PARTUUID=${uuid} rootwait " \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
+		"${vidargs}\0" \
+	"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
+		"colibri-imx8x/${fdt_file}; booti ${loadaddr} - " \
+		"${fdt_addr}\0" \
+	"panel=NULL\0" \
+	"script=boot.scr\0" \
+	"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
+		"if test \"$confirm\" = \"y\"; then " \
+		"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
+		"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
+		"${blkcnt}; fi\0" \
+	"vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
+
+#define CONFIG_SYS_MEMTEST_START	0x88000000
+#define CONFIG_SYS_MEMTEST_END		0x89000000
+
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
+					 CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* USDHC1 eMMC */
+#define CONFIG_SYS_MMC_ENV_PART		1
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M /* Increase max gunzip size */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		SZ_2G		/* 2 GB */
+#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 GB */
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		SZ_2K
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
+#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
+
+#endif /* __COLIBRI_IMX8X_H */
diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h
new file mode 100644
index 0000000..1f2b89e
--- /dev/null
+++ b/include/configs/colibri_imx6.h
@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2019 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex Colibri iMX6
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#undef CONFIG_DISPLAY_BOARDINFO
+
+#include <asm/arch/imx-regs.h>
+#include <asm/mach-imx/gpio.h>
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * 1024 * 1024)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_MXC_I2C3_SPEED	400000
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		1
+#define CONFIG_TFTP_TSIZE
+
+/* USB Configs */
+/* Host */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+/* Client */
+#define CONFIG_USBD_HS
+
+/* Framebuffer and LCD */
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition */
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FLASH
+
+#undef CONFIG_IPADDR
+#define CONFIG_IPADDR			192.168.10.2
+#define CONFIG_NETMASK			255.255.255.0
+#undef CONFIG_SERVERIP
+#define CONFIG_SERVERIP			192.168.10.1
+
+#define CONFIG_LOADADDR			0x12000000
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
+#else /* CONFIG_SPL_BUILD */
+#define BOOTENV
+#endif /* CONFIG_SPL_BUILD */
+
+#define DFU_ALT_EMMC_INFO \
+	"u-boot.imx raw 0x2 0x3ff mmcpart 0;" \
+	"boot part 0 1;" \
+	"rootfs part 0 2;" \
+	"zImage fat 0 1;" \
+	"imx6dl-colibri-eval-v3.dtb fat 0 1;" \
+	"imx6dl-colibri-cam-eval-v3.dtb fat 0 1"
+
+#define EMMC_BOOTCMD \
+	"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} "\
+		"rw,noatime rootfstype=ext4 " \
+		"rootwait\0" \
+	"emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
+		"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
+		"${vidargs}; echo Booting from internal eMMC chip...; "	\
+		"run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \
+		"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
+		"bootz ${kernel_addr_r} ${dtbparam}\0" \
+	"emmcbootpart=1\0" \
+	"emmcdev=0\0" \
+	"emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
+		"${fdt_addr_r} ${fdt_file} && " \
+		"setenv dtbparam \" - ${fdt_addr_r}\" && true\0" \
+	"emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \
+	"emmcrootpart=2\0"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"fdt_addr_r=0x12100000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_addr_r=0x11000000\0" \
+	"pxefile_addr_r=0x17100000\0" \
+	"ramdisk_addr_r=0x12200000\0" \
+	"scriptaddr=0x17000000\0"
+
+#define NFS_BOOTCMD \
+	"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
+	"nfsboot=run setup; " \
+		"setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \
+		"${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
+		"run nfsdtbload; dhcp ${kernel_addr_r} " \
+		"&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \
+	"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \
+		"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
+
+#define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
+	"bootcmd=setenv fdtfile ${fdt_file}; run distro_bootcmd; " \
+		"usb start ; " \
+		"setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \
+	"boot_file=zImage\0" \
+	"console=ttymxc0\0" \
+	"defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \
+	"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
+	EMMC_BOOTCMD \
+	"fdt_file=" FDT_FILE "\0" \
+	"fdt_fixup=;\0" \
+	MEM_LAYOUT_ENV_SETTINGS \
+	NFS_BOOTCMD \
+	"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
+		"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
+		"flash_eth.img && source ${loadaddr}\0" \
+	"setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \
+		"${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	"setup=setenv setupargs fec_mac=${ethaddr} " \
+		"consoleblank=0 no_console_suspend=1 console=tty1 " \
+		"console=${console},${baudrate}n8\0 " \
+	"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
+	"setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
+		"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	"splashpos=m,m\0" \
+	"splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+	"vidargs=video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 " \
+		"video=mxcfb1:off fbmem=8M\0 "
+
+/* Miscellaneous configurable options */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE		1024
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS		48
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
+					 CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		1
+#endif
+
+#define CONFIG_CMD_TIME
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
new file mode 100644
index 0000000..c2d9829
--- /dev/null
+++ b/include/configs/colibri_imx7.h
@@ -0,0 +1,260 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016-2018 Toradex AG
+ *
+ * Configuration settings for the Colibri iMX7 module.
+ *
+ * based on mx7dsabresd.h:
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __COLIBRI_IMX7_CONFIG_H
+#define __COLIBRI_IMX7_CONFIG_H
+
+#include "mx7_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define CONFIG_TFTP_TSIZE
+
+/* ENET1 */
+#define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
+
+/* MMC Config*/
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#elif CONFIG_TARGET_COLIBRI_IMX7_EMMC
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
+
+/* I2C configs */
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_IPADDR			192.168.10.2
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_SERVERIP			192.168.10.1
+
+#ifndef PARTS_DEFAULT
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+	/* Android partitions */ \
+	"partitions_android=" \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=boot,start=1M,size=32M,uuid=${uuid_gpt_boot};" \
+	"name=environment,size=4M,uuid=${uuid_gpt_environment};" \
+	"name=recovery,size=16M,uuid=${uuid_gpt_recovery};" \
+	"name=system,size=1536M,uuid=${uuid_gpt_system};" \
+	"name=cache,size=512M,uuid=${uuid_gpt_cache};" \
+	"name=device,size=8M,uuid=${uuid_gpt_device};" \
+	"name=misc,size=4M,uuid=${uuid_gpt_misc};" \
+	"name=datafooter,size=2M,uuid=${uuid_gpt_datafooter};" \
+	"name=metadata,size=2M,uuid=${uuid_gpt_metadata};" \
+	"name=persistdata,size=2M,uuid=${uuid_gpt_persistdata};" \
+	"name=userdata,size=128M,uuid=${uuid_gpt_userdata};" \
+	"name=fbmisc,size=-,uuid=${uuid_gpt_fbmisc}\0"
+#endif /* PARTS_DEFAULT */
+
+#define EMMC_ANDROID_BOOTCMD \
+	"android_args=androidboot.storage_type=emmc\0" \
+	PARTS_DEFAULT \
+	"android_fdt_addr=0x83700000\0" \
+	"android_mmc_dev=0\0" \
+	"m4binary=rpmsg_imu_freertos.elf\0" \
+	"androidboot=ext4load mmc 0:a ${loadaddr} media/0/${m4binary}; "\
+		"bootaux ${loadaddr}; " \
+		"setenv loadaddr 0x88000000; " \
+		"setenv bootm_boot_mode sec;" \
+		"setenv bootargs androidboot.serialno=${serial#} " \
+			"$android_args; " \
+		"part start mmc ${android_mmc_dev} boot boot_start; " \
+		"part size mmc ${android_mmc_dev} boot boot_size; " \
+		"mmc read ${loadaddr} ${boot_start} ${boot_size}; " \
+		"part start mmc ${android_mmc_dev} environment env_start; " \
+		"part size mmc ${android_mmc_dev} environment env_size; " \
+		"mmc read ${android_fdt_addr} ${env_start} ${env_size}; " \
+		"bootm ${loadaddr} ${loadaddr} ${android_fdt_addr}\0 "
+
+#define EMMC_BOOTCMD \
+	"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} ro " \
+		"rootfstype=ext4 rootwait\0" \
+	"emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
+		"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
+		"${vidargs}; echo Booting from internal eMMC chip...; " \
+		"run m4boot && " \
+		"load mmc ${emmcdev}:${emmcbootpart} ${fdt_addr_r} " \
+		"${soc}-colibri-emmc-${fdt_board}.dtb && " \
+		"load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \
+		"${boot_file} && run fdt_fixup && " \
+		"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+	"emmcbootpart=1\0" \
+	"emmcdev=0\0" \
+	"emmcfinduuid=part uuid mmc ${emmcdev}:${emmcrootpart} uuid\0" \
+	"emmcrootpart=2\0"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"ramdisk_addr_r=0x82100000\0" \
+	"scriptaddr=0x82500000\0"
+
+#define NFS_BOOTCMD \
+	"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
+	"nfsboot=run setup; " \
+		"setenv bootargs ${defargs} ${nfsargs} " \
+		"${setupargs} ${vidargs}; echo Booting from NFS...;" \
+		"dhcp ${kernel_addr_r} && " \
+		"tftp ${fdt_addr_r} ${soc}-colibri${variant}-${fdt_board}.dtb && " \
+		"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define UBI_BOOTCMD	\
+	"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
+		"ubi.fm_autoconvert=1\0" \
+	"ubiboot=run setup; " \
+		"setenv bootargs ${defargs} ${ubiargs} " \
+		"${setupargs} ${vidargs}; echo Booting from NAND...; " \
+		"ubi part ubi && run m4boot && " \
+		"ubi read ${kernel_addr_r} kernel && " \
+		"ubi read ${fdt_addr_r} dtb && " \
+		"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND)
+#define CONFIG_BOOTCOMMAND "run ubiboot ; echo ; echo ubiboot failed ; " \
+	"setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;"
+#define MODULE_EXTRA_ENV_SETTINGS \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	UBI_BOOTCMD
+#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC)
+#define CONFIG_BOOTCOMMAND \
+	"setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb && run distro_bootcmd;"
+#define MODULE_EXTRA_ENV_SETTINGS \
+	"variant=-emmc\0" \
+	EMMC_BOOTCMD \
+	EMMC_ANDROID_BOOTCMD
+#endif
+
+#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND)
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC)
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#endif
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
+	MEM_LAYOUT_ENV_SETTINGS \
+	NFS_BOOTCMD \
+	MODULE_EXTRA_ENV_SETTINGS \
+	"boot_file=zImage\0" \
+	"console=ttymxc0\0" \
+	"defargs=\0" \
+	"fdt_board=eval-v3\0" \
+	"fdt_fixup=;\0" \
+	"m4boot=;\0" \
+	"ip_dyn=yes\0" \
+	"kernel_file=zImage\0" \
+	"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
+		"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
+		"${board}/flash_eth.img && source ${loadaddr}\0" \
+	"setsdupdate=mmc rescan && setenv interface mmc && " \
+		"fatload ${interface} 0:1 ${loadaddr} " \
+		"${board}/flash_blk.img && source ${loadaddr}\0" \
+	"setup=setenv setupargs " \
+		"console=tty1 console=${console}" \
+		",${baudrate}n8 ${memargs} consoleblank=0\0" \
+	"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
+	"setusbupdate=usb start && setenv interface usb && " \
+		"fatload ${interface} 0:1 ${loadaddr} " \
+		"${board}/flash_blk.img && source ${loadaddr}\0" \
+	"splashpos=m,m\0" \
+	"videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \
+	"updlevel=2\0"
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x0c000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
+					 CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		1
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_OFFSET		(28 * CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#endif
+
+#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES
+#endif
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_USBD_HS
+
+/* USB Device Firmware Update support */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_16M
+#define DFU_DEFAULT_POLL_TIMEOUT	300
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#endif
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
new file mode 100644
index 0000000..bc3d40e
--- /dev/null
+++ b/include/configs/colibri_pxa270.h
@@ -0,0 +1,184 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Toradex Colibri PXA270 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
+ */
+
+#ifndef	__CONFIG_H
+#define	__CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
+/* Avoid overwriting factory configuration block */
+#define CONFIG_BOARD_SIZE_LIMIT		0x40000
+
+/*
+ * Environment settings
+ */
+#define	CONFIG_ENV_OVERWRITE
+#define	CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+#define	CONFIG_BOOTCOMMAND						\
+	"if fatload mmc 0 0xa0000000 uImage; then "			\
+		"bootm 0xa0000000; "					\
+	"fi; "								\
+	"if usb reset && fatload usb 0 0xa0000000 uImage; then "	\
+		"bootm 0xa0000000; "					\
+	"fi; "								\
+	"bootm 0xc0000;"
+#define	CONFIG_TIMESTAMP
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+
+/*
+ * Serial Console Configuration
+ */
+
+/*
+ * Bootloader Components Configuration
+ */
+
+/* I2C support */
+#ifdef CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PXA
+#define CONFIG_PXA_STD_I2C
+#define CONFIG_PXA_PWR_I2C
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+/* LCD support */
+#ifdef CONFIG_LCD
+#define CONFIG_PXA_LCD
+#define CONFIG_PXA_VGA
+#define CONFIG_LCD_LOGO
+#endif
+
+/*
+ * Networking Configuration
+ */
+#ifdef	CONFIG_CMD_NET
+
+#define	CONFIG_DRIVER_DM9000		1
+#define CONFIG_DM9000_BASE		0x08000000
+#define DM9000_IO			(CONFIG_DM9000_BASE)
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define	CONFIG_NET_RETRY_COUNT		10
+
+#define	CONFIG_BOOTP_BOOTFILESIZE
+#endif
+
+#define	CONFIG_SYS_DEVICE_NULLDEV	1
+
+/*
+ * Clock Configuration
+ */
+#define	CONFIG_SYS_CPUSPEED		0x290		/* 520MHz */
+
+/*
+ * DRAM Map
+ */
+#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define	PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
+
+#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
+#define	CONFIG_SYS_DRAM_SIZE		0x04000000	/* 64 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
+
+#define	CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000
+
+/*
+ * NOR FLASH
+ */
+#ifdef	CONFIG_CMD_FLASH
+#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define	PHYS_FLASH_SIZE			0x02000000	/* 32 MB */
+#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+#define	CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
+
+#define	CONFIG_SYS_MAX_FLASH_SECT	(4 + 255)
+#define	CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25 * CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25 * CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_LOCK_TOUT	(25 * CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	(25 * CONFIG_SYS_HZ)
+#endif
+
+#define	CONFIG_SYS_MONITOR_BASE		0x0
+#define	CONFIG_SYS_MONITOR_LEN		0x40000
+
+/* Skip factory configuration block */
+#define	CONFIG_ENV_ADDR			\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
+#define	CONFIG_ENV_SIZE			0x40000
+#define	CONFIG_ENV_SECT_SIZE		0x40000
+
+/*
+ * GPIO settings
+ */
+#define	CONFIG_SYS_GPSR0_VAL	0x00000000
+#define	CONFIG_SYS_GPSR1_VAL	0x00020000
+#define	CONFIG_SYS_GPSR2_VAL	0x0002c000
+#define	CONFIG_SYS_GPSR3_VAL	0x00000000
+
+#define	CONFIG_SYS_GPCR0_VAL	0x00000000
+#define	CONFIG_SYS_GPCR1_VAL	0x00000000
+#define	CONFIG_SYS_GPCR2_VAL	0x00000000
+#define	CONFIG_SYS_GPCR3_VAL	0x00000000
+
+#define	CONFIG_SYS_GPDR0_VAL	0xc8008000
+#define	CONFIG_SYS_GPDR1_VAL	0xfc02a981
+#define	CONFIG_SYS_GPDR2_VAL	0x92c3ffff
+#define	CONFIG_SYS_GPDR3_VAL	0x0061e804
+
+#define	CONFIG_SYS_GAFR0_L_VAL	0x80100000
+#define	CONFIG_SYS_GAFR0_U_VAL	0xa5c00010
+#define	CONFIG_SYS_GAFR1_L_VAL	0x6992901a
+#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa50008
+#define	CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
+#define	CONFIG_SYS_GAFR2_U_VAL	0x4109a002
+#define	CONFIG_SYS_GAFR3_L_VAL	0x54000310
+#define	CONFIG_SYS_GAFR3_U_VAL	0x00005401
+
+#define	CONFIG_SYS_PSSR_VAL	0x30
+
+/*
+ * Clock settings
+ */
+#define	CONFIG_SYS_CKEN		0x00500240
+#define	CONFIG_SYS_CCCR		0x02000290
+
+/*
+ * Memory settings
+ */
+#define	CONFIG_SYS_MSC0_VAL	0x9ee1c5f2
+#define	CONFIG_SYS_MSC1_VAL	0x9ee1f994
+#define	CONFIG_SYS_MSC2_VAL	0x9ee19ee1
+#define	CONFIG_SYS_MDCNFG_VAL	0x090009c9
+#define	CONFIG_SYS_MDREFR_VAL	0x2003a031
+#define	CONFIG_SYS_MDMRS_VAL	0x00220022
+#define	CONFIG_SYS_FLYCNFG_VAL	0x00010001
+#define	CONFIG_SYS_SXCNFG_VAL	0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define	CONFIG_SYS_MECR_VAL	0x00000000
+#define	CONFIG_SYS_MCMEM0_VAL	0x00028307
+#define	CONFIG_SYS_MCMEM1_VAL	0x00014307
+#define	CONFIG_SYS_MCATT0_VAL	0x00038787
+#define	CONFIG_SYS_MCATT1_VAL	0x0001c787
+#define	CONFIG_SYS_MCIO0_VAL	0x0002830f
+#define	CONFIG_SYS_MCIO1_VAL	0x0001430f
+
+#include "pxa-common.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
new file mode 100644
index 0000000..cd7e168
--- /dev/null
+++ b/include/configs/colibri_t20.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Lucas Stach
+ *
+ * Configuration settings for the Toradex Colibri T20 modules.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra20-common.h"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_SDIO1
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_COLIBRI_TEGRA2
+
+/* General networking support */
+#define CONFIG_TFTP_TSIZE
+
+/* LCD support */
+#define CONFIG_LCD_LOGO
+
+/* NAND support */
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
+#define CONFIG_ENV_OFFSET		(SZ_2M)
+#undef CONFIG_ENV_SIZE		/* undef size from tegra20-common.h */
+#define CONFIG_ENV_SIZE			(SZ_64K)
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+
+/* Increase console I/O buffer size */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Increase arguments buffer size */
+#undef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Increase maximum number of arguments */
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS		32
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
new file mode 100644
index 0000000..8ff6433
--- /dev/null
+++ b/include/configs/colibri_t30.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013-2016 Stefan Agner
+ *
+ * Configuration settings for the Toradex Colibri T30 modules.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra30-common.h"
+
+/* High-level configuration options */
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_COLIBRI_T30
+
+/* Environment in eMMC, before config block at the end of 1st "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE + \
+					 CONFIG_TDX_CFG_BLOCK_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		1
+
+/* General networking support */
+#define CONFIG_TFTP_TSIZE
+
+/* Increase console I/O buffer size */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Increase arguments buffer size */
+#undef CONFIG_SYS_BARGSIZE
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Increase maximum number of arguments */
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS		32
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
new file mode 100644
index 0000000..da9a842
--- /dev/null
+++ b/include/configs/colibri_vf.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2019 Toradex, Inc.
+ *
+ * Configuration settings for the Toradex VF50/VF61 modules.
+ *
+ * Based on vf610twr.h:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_SYS_FSL_DCU_LE
+
+#define CONFIG_SYS_DCU_ADDR		DCU0_BASE_ADDR
+#define DCU_LAYER_MAX_NUM		64
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * SZ_1M)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* NAND support */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_IPADDR		192.168.10.2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.168.10.1
+
+#define CONFIG_LOADADDR			0x80008000
+#define CONFIG_FDTADDR			0x84000000
+
+/* We boot from the gfxRAM area of the OCRAM. */
+#define CONFIG_BOARD_SIZE_LIMIT		520192
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"pxefile_addr_r=0x87100000\0" \
+	"ramdisk_addr_r=0x82100000\0" \
+	"scriptaddr=0x87000000\0"
+
+#define NFS_BOOTCMD \
+	"nfsargs=ip=:::::eth0: root=/dev/nfs\0"	\
+	"nfsboot=run setup; " \
+	"setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \
+	"${setupargs} ${vidargs}; echo Booting from NFS...;" \
+	"dhcp ${kernel_addr_r} && "	\
+	"tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \
+	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define SD_BOOTCMD \
+	"set_sdargs=setenv sdargs root=PARTUUID=${uuid} ro rootwait\0"	\
+	"sdboot=run setup; run sdfinduuid; run set_sdargs; " \
+	"setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \
+	"${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \
+	"load mmc ${sddev}:${sdbootpart} ${kernel_addr_r} ${kernel_file} && " \
+	"load mmc ${sddev}:${sdbootpart} ${fdt_addr_r} " \
+		"${soc}-colibri-${fdt_board}.dtb && " \
+	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+	"sdbootpart=1\0" \
+	"sddev=0\0" \
+	"sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
+	"sdrootpart=2\0"
+
+
+#define UBI_BOOTCMD \
+	"ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \
+	"ubi.fm_autoconvert=1\0" \
+	"ubiboot=run setup; " \
+	"setenv bootargs ${defargs} ${ubiargs} ${mtdparts} "   \
+	"${setupargs} ${vidargs}; echo Booting from NAND...; " \
+	"ubi part ubi && " \
+	"ubi read ${kernel_addr_r} kernel && " \
+	"ubi read ${fdt_addr_r} dtb && " \
+	"run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
+
+#define CONFIG_BOOTCOMMAND "run ubiboot; " \
+	"setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#undef BOOTENV_RUN_NET_USB_START
+#define BOOTENV_RUN_NET_USB_START ""
+
+#define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	BOOTENV \
+	MEM_LAYOUT_ENV_SETTINGS \
+	NFS_BOOTCMD \
+	SD_BOOTCMD \
+	UBI_BOOTCMD \
+	"console=ttyLP0\0" \
+	"defargs=user_debug=30\0" \
+	"dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \
+	"fdt_board=eval-v3\0" \
+	"fdt_fixup=;\0" \
+	"kernel_file=zImage\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"setsdupdate=mmc rescan && set interface mmc && " \
+		"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	"setup=setenv setupargs console=tty1 console=${console}" \
+		",${baudrate}n8 ${memargs}\0" \
+	"setupdate=run setsdupdate || run setusbupdate\0" \
+	"setusbupdate=usb start && set interface usb && " \
+		"fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \
+		"source ${loadaddr}\0" \
+	"splashpos=m,m\0" \
+	"video-mode=dcufb:640x480-16@60,monitor=lcd\0"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x80010000
+#define CONFIG_SYS_MEMTEST_END		0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical memory map */
+#define PHYS_SDRAM			(0x80000000)
+#define PHYS_SDRAM_SIZE			(256 * SZ_1M)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			(64 * 2048)
+#define CONFIG_ENV_RANGE		(4 * 64 * 2048)
+#define CONFIG_ENV_OFFSET		(12 * 64 * 2048)
+#endif
+
+/* USB Host Support */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+/* USB DFU */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/comtrend_ar5315u.h b/include/configs/comtrend_ar5315u.h
new file mode 100644
index 0000000..1da96c1
--- /dev/null
+++ b/include/configs/comtrend_ar5315u.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6318.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE	SZ_8K
diff --git a/include/configs/comtrend_ar5387un.h b/include/configs/comtrend_ar5387un.h
new file mode 100644
index 0000000..73e6a5d
--- /dev/null
+++ b/include/configs/comtrend_ar5387un.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6328.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE	SZ_8K
diff --git a/include/configs/comtrend_ct5361.h b/include/configs/comtrend_ct5361.h
new file mode 100644
index 0000000..72f9ecb
--- /dev/null
+++ b/include/configs/comtrend_ct5361.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6348.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE	SZ_8K
diff --git a/include/configs/comtrend_vr3032u.h b/include/configs/comtrend_vr3032u.h
new file mode 100644
index 0000000..cb88805
--- /dev/null
+++ b/include/configs/comtrend_vr3032u.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm63268.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE	SZ_8K
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif /* CONFIG_NAND */
diff --git a/include/configs/comtrend_wap5813n.h b/include/configs/comtrend_wap5813n.h
new file mode 100644
index 0000000..b67f654
--- /dev/null
+++ b/include/configs/comtrend_wap5813n.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6368.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE	SZ_8K
diff --git a/include/configs/condor.h b/include/configs/condor.h
new file mode 100644
index 0000000..e3c146e
--- /dev/null
+++ b/include/configs/condor.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/condor.h
+ *     This file is Condor board configuration.
+ *
+ * Copyright (C) 2019 Renesas Electronics Corporation
+ */
+
+#ifndef __CONDOR_H
+#define __CONDOR_H
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Environment compatibility */
+#undef CONFIG_ENV_SIZE_REDUND
+#undef CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_OFFSET	0x700000
+
+/* SH Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define CONFIG_SYS_CLK_FREQ	33333333u
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
+
+#endif /* __CONDOR_H */
diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h
new file mode 100644
index 0000000..93dcad4
--- /dev/null
+++ b/include/configs/conga-qeval20-qa3-e3845.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \
+					"stdout=serial\0" \
+					"stderr=serial\0"
+
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x006ef000
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND	\
+	"load scsi 0:2 03000000 /boot/vmlinuz-${kernel-ver}-generic;"	\
+	"load scsi 0:2 04000000 /boot/initrd.img-${kernel-ver}-generic;" \
+	"run boot"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"kernel-ver=4.4.0-22\0"					\
+	"boot=zboot 03000000 0 04000000 ${filesize}\0"		\
+	"upd_uboot=tftp 100000 conga/u-boot.rom;"		\
+		"sf probe;sf update 100000 0 800000;saveenv\0"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
new file mode 100644
index 0000000..19223e2
--- /dev/null
+++ b/include/configs/controlcenterd.h
@@ -0,0 +1,369 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * based on P1022DS.h
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_CONTROLCENTERD
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_SYS_CLK_FREQ	66666600
+#define CONFIG_DDR_CLK_FREQ	66666600
+
+#define CONFIG_SYS_RAMBOOT
+
+#ifdef CONFIG_TRAILBLAZER
+
+#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+
+/*
+ * Config the L2 Cache
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8fc0000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8fc0000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+#else /* CONFIG_TRAILBLAZER */
+
+#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#endif /* CONFIG_TRAILBLAZER */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x3fff_ffff	DDR			1G Cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI Express Mem		512M non-cacheable
+ * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe00f_ffff	eLBC			1M non-cacheable
+ * 0xf8fc0000	0xf8ff_ffff	L2 SRAM			256k Cacheable
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#ifdef CONFIG_TRAILBLAZER
+/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
+#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
+#else
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#endif
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_MPC85xx_GPIO3_ADDR	(CONFIG_SYS_CCSRBAR+0xf200)
+
+/*
+ * DDR Setup
+ */
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE 1024
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x3fffffff
+
+#ifdef CONFIG_TRAILBLAZER
+#define CONFIG_SPD_EEPROM
+#define SPD_EEPROM_ADDRESS 0x52
+/*#define CONFIG_FSL_DDR_INTERACTIVE*/
+#endif
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CONFIG_SYS_ELBC_BASE		0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_ELBC_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_ELBC_BASE_PHYS	CONFIG_SYS_ELBC_BASE
+#endif
+
+#define CONFIG_UART_BR_PRELIM  \
+	(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
+#define CONFIG_UART_OR_PRELIM	(OR_AM_32KB | 0xff7)
+
+#define CONFIG_SYS_BR0_PRELIM	0 /* CS0 was originally intended for FPGA */
+#define CONFIG_SYS_OR0_PRELIM	0 /* debugging, was never used */
+
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_UART_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_UART_OR_PRELIM
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+#define CONFIG_PCA9698			/* NXP PCA9698 */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/*
+ * MMC
+ */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+
+#ifndef CONFIG_TRAILBLAZER
+
+/*
+ * Video
+ */
+#define CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/*
+ * SATA
+ */
+#define CONFIG_LBA48
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+/*
+ * Ethernet
+ */
+
+#define CONFIG_TSECV2
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+/*
+ * USB
+ */
+
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#endif /* CONFIG_TRAILBLAZER */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_TRAILBLAZER)
+#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#endif
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#ifndef CONFIG_TRAILBLAZER
+/*
+ * Board initialisation callbacks
+ */
+#endif /* CONFIG_TRAILBLAZER */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Linux Memory map */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+
+#ifdef CONFIG_TRAILBLAZER
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"mp_holdoff=1\0"
+
+#else
+
+#define CONFIG_HOSTNAME		"controlcenterd"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP */
+
+#define CONFIG_LOADADDR		1000000
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+		"protect off $ubootaddr +$filesize && "		\
+		"erase $ubootaddr +$filesize && "		\
+		"cp.b $loadaddr $ubootaddr $filesize && "	\
+		"protect on $ubootaddr +$filesize && "		\
+		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
+	"consoledev=ttyS1\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
+	"fdtaddr=1e00000\0"					\
+	"fdtfile=controlcenterd.dtb\0"				\
+	"bdev=sda3\0"
+
+/* these are used and NUL-terminated in env_default.h */
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
+
+#endif /* CONFIG_TRAILBLAZER */
+
+#endif
diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h
new file mode 100644
index 0000000..f6d5328
--- /dev/null
+++ b/include/configs/controlcenterdc.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
+ */
+
+#ifndef _CONFIG_CONTROLCENTERDC_H
+#define _CONFIG_CONTROLCENTERDC_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_CUSTOMER_BOARD_SUPPORT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+#define CONFIG_LOADADDR 		1000000
+
+/*
+ * SDIO/MMC Card Configuration
+ */
+#define CONFIG_SYS_MMC_BASE		MVEBU_SDIO_BASE
+
+/*
+ * SATA/SCSI/AHCI configuration
+ */
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					 CONFIG_SYS_SCSI_MAX_LUN)
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/*
+ * Software (bit-bang) MII driver configuration
+ */
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+/* SPL */
+/*
+ * Select the boot device here
+ *
+ * Currently supported are:
+ * SPL_BOOT_SPI_NOR_FLASH	- Booting via SPI NOR flash
+ * SPL_BOOT_SDIO_MMC_CARD	- Booting via SDIO/MMC card (partition 1)
+ */
+#define SPL_BOOT_SPI_NOR_FLASH		1
+#define SPL_BOOT_SDIO_MMC_CARD		2
+#define CONFIG_SPL_BOOT_DEVICE		SPL_BOOT_SPI_NOR_FLASH
+
+/* Defines for SPL */
+#define CONFIG_SPL_SIZE			(160 << 10)
+
+#if defined(CONFIG_SECURED_MODE_IMAGE)
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x2614)
+#else
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x30)
+#endif
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((212 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+/* SPL related SPI defines */
+#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
+/* SPL related MMC defines */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
+#define CONFIG_SYS_MMC_U_BOOT_OFFS		(168 << 10)
+#define CONFIG_SYS_U_BOOT_OFFS			CONFIG_SYS_MMC_U_BOOT_OFFS
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	(CONFIG_SYS_U_BOOT_OFFS / 512)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER	0x00180000	/* in SDRAM */
+#endif
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_HOSTNAME		"ccdc"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"ccdc.img"
+
+#define CONFIG_EXTRA_ENV_SETTINGS						\
+	"netdev=eth1\0"						\
+	"consoledev=ttyS1\0"							\
+	"u-boot=u-boot.bin\0"							\
+	"bootfile_addr=1000000\0"						\
+	"keyprogram_addr=3000000\0"						\
+	"keyprogram_file=keyprogram.img\0"						\
+	"fdtfile=controlcenterdc.dtb\0"						\
+	"load=tftpboot ${loadaddr} ${u-boot}\0"					\
+	"mmcdev=0:2\0"								\
+	"update=sf probe 1:0;"							\
+		" sf erase 0 +${filesize};"					\
+		" sf write ${fileaddr} 0 ${filesize}\0"				\
+	"upd=run load update\0"							\
+	"fdt_high=0x10000000\0"							\
+	"initrd_high=0x10000000\0"						\
+	"loadkeyprogram=tpm flush_keys;"					\
+		" mmc rescan;"							\
+		" ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\
+		" source ${keyprogram_addr}:script@1\0"				\
+	"gpio1=gpio@22_25\0"							\
+	"gpio2=A29\0"								\
+	"blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 "	\
+		  "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0"	\
+	"bootfail=for i in ${blinkseq}; do"					\
+		" if test $i -eq 0; then"					\
+		" gpio clear ${gpio1}; gpio set ${gpio2};"			\
+		" elif test $i -eq 1; then"					\
+		" gpio clear ${gpio1}; gpio clear ${gpio2};"			\
+		" elif test $i -eq 2; then"					\
+		" gpio set ${gpio1}; gpio set ${gpio2};"			\
+		" else;"							\
+		" gpio clear ${gpio1}; gpio set ${gpio2};"			\
+		" fi; sleep 0.12; done\0"
+
+#define CONFIG_NFSBOOTCOMMAND								\
+	"setenv bootargs root=/dev/nfs rw "						\
+	"nfsroot=${serverip}:${rootpath} "						\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off "	\
+	"console=${consoledev},${baudrate} ${othbootargs}; "				\
+	"tftpboot ${bootfile_addr} ${bootfile}; "						\
+	"bootm ${bootfile_addr}"
+
+#define CONFIG_MMCBOOTCOMMAND					\
+	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait "	\
+	"console=${consoledev},${baudrate} ${othbootargs}; "	\
+	"ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; "	\
+	"bootm ${bootfile_addr}"
+
+#define CONFIG_BOOTCOMMAND			\
+	"if env exists keyprogram; then;"	\
+	" setenv keyprogram; run nfsboot;"	\
+        " fi;"					\
+        " run dobootfail"
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_CONTROLCENTERDC_H */
diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
new file mode 100644
index 0000000..1cf5c03
--- /dev/null
+++ b/include/configs/coreboot.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd,usbkbd\0" \
+					"stdout=serial,vidconsole\0" \
+					"stderr=serial,vidconsole\0"
+
+/* ATA/IDE support */
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	4
+#define CONFIG_SYS_ATA_BASE_ADDR	0
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_ALT_OFFSET	0
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
+#define CONFIG_ATAPI
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
new file mode 100644
index 0000000..60e09c1
--- /dev/null
+++ b/include/configs/corenet_ds.h
@@ -0,0 +1,616 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/freescale/common/ics307_clk.h"
+
+#ifdef CONFIG_RAMBOOT_PBL
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#ifdef CONFIG_NAND
+#define CONFIG_RAMBOOT_NAND
+#endif
+#define CONFIG_BOOTSCRIPT_COPY_RAM
+#else
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
+#if defined(CONFIG_TARGET_P3041DS)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
+#elif defined(CONFIG_TARGET_P4080DS)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
+#elif defined(CONFIG_TARGET_P5020DS)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
+#elif defined(CONFIG_TARGET_P5040DS)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
+#endif
+#endif
+#endif
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define	CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
+#else
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
+#endif
+#define CONFIG_SYS_L3_SIZE		(1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM	1
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of platform clock */
+#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
+
+#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* Start of PromJet */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_FLASH_BR_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
+		 | BR_PS_16 | BR_V)
+#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+					| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
+
+#define CONFIG_SYS_BR1_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
+
+#define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS		0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS		PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_LBMAP_SWITCH	7
+#define PIXIS_LBMAP_MASK	0xf0
+#define PIXIS_LBMAP_SHIFT	4
+#define PIXIS_LBMAP_ALTBANK	0x40
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/* Nand Flash */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
+			       | OR_FCM_PGS	       /* Large Page*/ \
+			       | OR_FCM_CSCT \
+			       | OR_FCM_CST \
+			       | OR_FCM_CHT \
+			       | OR_FCM_SCY_1 \
+			       | OR_FCM_TRLX \
+			       | OR_FCM_EHTR)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#endif /* CONFIG_NAND_FSL_ELBC */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000	/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
+
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+
+/* Qman/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#endif
+
+#ifdef CONFIG_PCI
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1c
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x1d
+#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR	0x1e
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x1f
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	4
+
+#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR	0x1c
+#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR	0x1d
+#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR	0x1e
+#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR	0x1f
+#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR	0
+
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_HAS_FSL_MPH_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#ifdef CONFIG_TARGET_P4080DS
+#define __USB_PHY_TYPE	ulpi
+#else
+#define __USB_PHY_TYPE	utmi
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
+	"bank_intlv=cs0_cs1;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+	"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=p4080ds/ramdisk.uboot\0"			\
+	"fdtaddr=1e00000\0"					\
+	"fdtfile=p4080ds/p4080ds.dtb\0"				\
+	"bdev=sda3\0"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
new file mode 100644
index 0000000..f2df66e
--- /dev/null
+++ b/include/configs/corvus.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common board functions for siemens AT91SAM9G45 based boards
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9m10g45ek.h
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+#include <linux/sizes.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
+#define CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* DFU class support */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
+#define DFU_MANIFEST_POLL_TIMEOUT	25000
+
+#define CONFIG_SYS_LOAD_ADDR	ATMEL_BASE_CS6
+
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_OFFSET_REDUND	0x180000
+
+#define CONFIG_BOOTCOMMAND						\
+	"nand read 0x70000000 0x200000 0x300000;"			\
+	"bootm 0x70000000"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + \
+				SZ_4M, 0x1000)
+
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		(12 * SZ_1K)
+#define CONFIG_SPL_STACK		(SZ_16K)
+
+#define CONFIG_SPL_BSS_START_ADDR	CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_BSS_MAX_SIZE		(SZ_2K)
+
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	SZ_2K
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(SZ_128K)
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define AT91_PLL_LOCK_TIMEOUT		1000000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#define CONFIG_SPL_PAD_TO		CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_SPL_LEN		CONFIG_SPL_PAD_TO
+
+#endif
diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h
new file mode 100644
index 0000000..8070af7
--- /dev/null
+++ b/include/configs/cougarcanyon2.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(2 << 20)
+
+#define CONFIG_SMSC_SIO1007
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd,usbkbd\0" \
+					"stdout=serial,vga\0" \
+					"stderr=serial,vga\0"
+
+/* Environment configuration */
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x5ff000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
new file mode 100644
index 0000000..75f677f
--- /dev/null
+++ b/include/configs/crownbay.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+
+#define CONFIG_SMSC_LPC47M
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd,usbkbd\0" \
+					"stdout=serial,vidconsole\0" \
+					"stderr=serial,vidconsole\0"
+
+/* Environment configuration */
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/crs305-1g-4s.h b/include/configs/crs305-1g-4s.h
new file mode 100644
index 0000000..a2df69a
--- /dev/null
+++ b/include/configs/crs305-1g-4s.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_CRS305_1G_4S_H
+#define _CONFIG_CRS305_1G_4S_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_SYS_BOOTM_LEN	(64 * 1024 * 1024) /* 64 MB */
+#define CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_SYS_TCLK		200000000	/* 200MHz */
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0x10000000\0"		\
+	"initrd_high=0x10000000\0"
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 96
+
+#endif /* _CONFIG_CRS305_1G_4S_H */
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
new file mode 100644
index 0000000..d152f23
--- /dev/null
+++ b/include/configs/cyrus.h
@@ -0,0 +1,468 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Based on corenet_ds.h
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
+#error Must call Cyrus CONFIG with a specific CPU enabled.
+#endif
+
+#define CONFIG_SDCARD
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE3
+#define CONFIG_PCIE4
+#ifdef CONFIG_ARCH_P5020
+#define CONFIG_SYS_FSL_RAID_ENGINE
+#define CONFIG_SYS_DPAA_RMAN
+#endif
+#define CONFIG_SYS_DPAA_PME
+
+/*
+ * Corenet DS style board configuration file
+ */
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
+#if defined(CONFIG_ARCH_P5020)
+#define CONFIG_SYS_CLK_FREQ 133000000
+#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
+#elif defined(CONFIG_ARCH_P5040)
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+
+#define CONFIG_SYS_MMC_MAX_DEVICE     1
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SDCARD)
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1658)
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define	CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+#endif
+
+/* test POST memory test */
+#undef CONFIG_POST
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
+#else
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
+#endif
+#define CONFIG_SYS_L3_SIZE		(1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM	1
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CONFIG_SYS_LBC0_BASE		0xe0000000 /* Start of LBC Registers */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_LBC0_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_LBC0_BASE_PHYS	CONFIG_SYS_LBC0_BASE
+#endif
+
+#define CONFIG_SYS_LBC1_BASE		0xe1000000 /* Start of LBC Registers */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_LBC1_BASE_PHYS	0xfe1000000ull
+#else
+#define CONFIG_SYS_LBC1_BASE_PHYS	CONFIG_SYS_LBC1_BASE
+#endif
+
+/* Set the local bus clock 1/16 of platform clock */
+#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_16 | LCRR_EADC_1)
+
+#define CONFIG_SYS_BR0_PRELIM \
+(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR1_PRELIM \
+(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
+
+#define CONFIG_SYS_OR0_PRELIM	0xfff00010
+#define CONFIG_SYS_OR1_PRELIM	0xfff00010
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000	/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_FSL_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_FSL_I2C_SLAVE		0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET		0x118000
+#define CONFIG_SYS_FSL_I2C2_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_FSL_I2C2_SLAVE		0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET		0x118100
+#define CONFIG_SYS_FSL_I2C3_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_FSL_I2C3_SLAVE		0x7F
+#define CONFIG_SYS_FSL_I2C3_OFFSET		0x119000
+#define CONFIG_SYS_FSL_I2C4_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_FSL_I2C4_SLAVE		0x7F
+#define CONFIG_SYS_FSL_I2C4_OFFSET		0x119100
+
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+
+#define CONFIG_SYS_I2C_GENERIC_MAC
+#define CONFIG_SYS_I2C_MAC1_BUS 3
+#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
+#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
+#define CONFIG_SYS_I2C_MAC2_BUS 0
+#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
+#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
+
+#define CONFIG_RTC_MCP79411		1
+#define CONFIG_SYS_RTC_BUS_NUM		3
+#define CONFIG_SYS_I2C_RTC_ADDR		0x6f
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					 CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					  CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+/* Default address of microcode for the Linux Fman driver */
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
+
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_ETHPRIME		"FM1@DTSEC4"
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_HAS_FSL_MPH_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_EHCI_IS_TDI
+ /* _VIA_CONTROL_EP  */
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define __USB_PHY_TYPE	utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
+"bank_intlv=cs0_cs1;"					\
+"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+"netdev=eth0\0"						\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"			\
+"consoledev=ttyS0\0"					\
+"ramdiskaddr=2000000\0"					\
+"fdtaddr=1e00000\0"					\
+"bdev=sda3\0"
+
+#define CONFIG_HDBOOT					\
+"setenv bootargs root=/dev/$bdev rw "		\
+"console=$consoledev,$baudrate $othbootargs;"	\
+"tftp $loadaddr $bootfile;"			\
+"tftp $fdtaddr $fdtfile;"			\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+"setenv bootargs root=/dev/nfs rw "	\
+"nfsroot=$serverip:$rootpath "		\
+"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+"console=$consoledev,$baudrate $othbootargs;"	\
+"tftp $loadaddr $bootfile;"		\
+"tftp $fdtaddr $fdtfile;"		\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+"setenv bootargs root=/dev/ram rw "		\
+"console=$consoledev,$baudrate $othbootargs;"	\
+"tftp $ramdiskaddr $ramdiskfile;"		\
+"tftp $loadaddr $bootfile;"			\
+"tftp $fdtaddr $fdtfile;"			\
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
new file mode 100644
index 0000000..41f0813
--- /dev/null
+++ b/include/configs/da850evm.h
@@ -0,0 +1,282 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+/* check if direct NOR boot config is used */
+#ifndef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_USE_SPIFLASH
+#endif
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+
+#ifdef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)
+#endif
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
+#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
+	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
+	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
+	DAVINCI_SYSCFG_SUSPSRC_I2C)
+
+/*
+ * PLL configuration
+ */
+
+#define CONFIG_SYS_DA850_PLL0_PLLM     24
+#define CONFIG_SYS_DA850_PLL1_PLLM     21
+
+/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+					DV_DDR_PHY_EXT_STRBEN | \
+					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
+	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
+	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
+	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) |	\
+	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
+	(14 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
+	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
+	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
+	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
+	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
+	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
+	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
+	(0 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
+	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_XP_SHIFT) |		\
+	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
+	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
+	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
+#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+
+#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
+
+#ifdef CONFIG_USE_SPIFLASH
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
+#endif
+
+/*
+ * I2C Configuration
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
+#endif
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_NAND
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_ENV_SECT_SIZE	(128 << 10)
+#endif
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define	CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS		3
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_NAND_MASK_CLE		0x10
+#define CONFIG_SYS_NAND_MASK_ALE		0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x40000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
+					CONFIG_SYS_NAND_U_BOOT_SIZE - \
+					CONFIG_SYS_MALLOC_LEN -       \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS		{				\
+				24, 25, 26, 27, 28, \
+				29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
+				39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
+				59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_LOAD
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NAND_SELF_INIT
+#endif
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#endif
+
+#ifdef CONFIG_USE_NOR
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
+#define CONFIG_ENV_OFFSET		(SZ_1M)
+#define CONFIG_ENV_SIZE			(10 << 10) /* 10KB */
+#define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
+#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
+	       + 3)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			(64 << 10)
+#define CONFIG_ENV_OFFSET		(512 << 10)
+#define CONFIG_ENV_SECT_SIZE	(64 << 10)
+#endif
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SPI_FLASH_MTD
+#endif
+#endif
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_HWCONFIG		/* enable hwconfig */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_BOOTCOMMAND \
+		"run envboot; " \
+		"run mmcboot; "
+
+#define DEFAULT_LINUX_BOOT_ENV \
+	"loadaddr=0xc0700000\0" \
+	"fdtaddr=0xc0600000\0" \
+	"scriptaddr=0xc0600000\0"
+
+#include <environment/ti/mmc.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	DEFAULT_MMC_TI_ARGS \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"fdtfile=da850-evm.dtb\0" \
+	"boot_fdt=yes\0" \
+	"boot_fit=0\0" \
+	"console=ttyS2,115200n8\0" \
+	"hwconfig=dsp:wake=yes"
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#if !defined(CONFIG_NAND) && \
+	!defined(CONFIG_USE_NOR) && \
+	!defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_SIZE		(16 << 10)
+#endif
+
+/* USB Configs */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+#ifndef CONFIG_DIRECT_NOR_BOOT
+/* defines for SPL */
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
+						CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SPL_STACK	0x8001ff00
+#define CONFIG_SPL_MAX_FOOTPRINT	32768
+#define CONFIG_SPL_PAD_TO	32768
+#endif
+
+/* Load U-Boot Image From MMC */
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+
+#ifdef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_SYS_INIT_SP_ADDR		0x8001ff00
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_DIRECT_NOR_BOOT */
+
+#include <asm/arch/hardware.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
new file mode 100644
index 0000000..e8a4e3c
--- /dev/null
+++ b/include/configs/dalmore.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra114-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Dalmore"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_DALMORE
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h
new file mode 100644
index 0000000..4f99805
--- /dev/null
+++ b/include/configs/dart_6ul.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board configuration file for Variscite DART-6UL Evaluation Kit
+ * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ */
+#ifndef __DART_6UL_H
+#define __DART_6UL_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/* NAND pin conflicts with usdhc2 */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_FSL_USDHC_NUM        1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM        2
+#endif
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_ENET_DEV		0
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x1
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"eth0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x3
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"eth1"
+#endif
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+/* Environment settings */
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET		(14 * SZ_64K)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND	\
+	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+
+/* Environment in SD */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		0
+#define MMC_ROOTFS_DEV			0
+#define MMC_ROOTFS_PART			2
+
+/* Console configs */
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* I2C configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			SZ_512M
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+
+#define CONFIG_IMX_THERMAL
+
+#define ENV_MMC \
+	"mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
+	"mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
+	"fitpart=1\0" \
+	"bootdelay=3\0" \
+	"silent=1\0" \
+	"optargs=rw rootwait\0" \
+	"mmcautodetect=yes\0" \
+	"mmcrootfstype=ext4\0" \
+	"mmcfit_name=fitImage\0" \
+	"mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
+		    "${mmcfit_name}\0" \
+	"mmcargs=setenv bootargs " \
+		"root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \
+		"console=${console} rootfstype=${mmcrootfstype}\0" \
+	"mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0xffffffff\0" \
+	"console=ttymxc0,115200n8\0" \
+	"addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
+	"fit_addr=0x82000000\0" \
+	ENV_MMC
+
+#define CONFIG_BOOTCOMMAND		"run mmc_mmc_fit"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+#endif /* __DART_6UL_H */
diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h
new file mode 100644
index 0000000..1b5541e
--- /dev/null
+++ b/include/configs/db-88f6281-bp.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _CONFIG_DB_88F6281_BP_H
+#define _CONFIG_DB_88F6281_BP_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_SYS_TCLK		166666667
+#define CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_BUILD_TARGET	"u-boot.kwb"
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+
+#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_PCIE_INIT	/* Enable PCIE Port0 */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_GPIO	1
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
+
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/* Console on UART0 */
+
+/*
+ *  Environment variables configurations
+ */
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		20000000	/* 20Mhz */
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SECT_SIZE		0x40000		/* 256K */
+#define CONFIG_ENV_SIZE			0x01000
+#define CONFIG_ENV_OFFSET		0xC0000
+
+/*
+ * U-Boot bootcode configuration
+ */
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for monitor */
+#define CONFIG_SYS_MALLOC_LEN		  (4 << 20)	/* Reserve 4.0 MB for malloc */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
+
+/* size in bytes reserved for initial data */
+
+#include <asm/arch/config.h>
+/* There is no PHY directly connected so don't ask it for link status */
+#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
+#define CONFIG_SYS_MEMTEST_END	0x007fffff	/* (_8M - 1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+
+/*
+ * SDIO/MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MVEBU_MMC
+#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
+#endif /* CONFIG_CMD_MMC */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#define CONFIG_SYS_LOAD_ADDR  0x1000000      /* default location for tftp and bootm */
+
+#endif /* _CONFIG_DB_88F6281_BP_H */
diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h
new file mode 100644
index 0000000..79b9ccf
--- /dev/null
+++ b/include/configs/db-88f6720.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_DB_88F6720_H
+#define _CONFIG_DB_88F6720_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TCLK		200000000	/* 200MHz */
+
+/*
+ * Commands configuration
+ */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
+
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
+ * 0x4000.4030			bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
+ * 0x4007.fffc			BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+/* SPL related SPI defines */
+#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+
+#endif /* _CONFIG_DB_88F6720_H */
diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h
new file mode 100644
index 0000000..61b91dd
--- /dev/null
+++ b/include/configs/db-88f6820-amc.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_DB_88F6820_AMC_H
+#define _CONFIG_DB_88F6820_AMC_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_SYS_TCLK		200000000	/* 200MHz */
+
+/*
+ * Commands configuration
+ */
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* NAND */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0x10000000\0"		\
+	"initrd_high=0x10000000\0"
+
+/* SPL */
+/*
+ * Select the boot device here
+ *
+ * Currently supported are:
+ * SPL_BOOT_SPI_NOR_FLASH	- Booting via SPI NOR flash
+ *
+ * MMC is not populated on this board.
+ * NAND support may be added in the future.
+ */
+#define SPL_BOOT_SPI_NOR_FLASH		1
+#define CONFIG_SPL_BOOT_DEVICE		SPL_BOOT_SPI_NOR_FLASH
+
+/* Defines for SPL */
+#define CONFIG_SPL_SIZE			(140 << 10)
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+/* SPL related SPI defines */
+#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 96
+
+#endif /* _CONFIG_DB_88F6820_AMC_H */
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
new file mode 100644
index 0000000..900c962
--- /dev/null
+++ b/include/configs/db-88f6820-gp.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_DB_88F6820_GP_H
+#define _CONFIG_DB_88F6820_GP_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/*
+ * SDIO/MMC Card Configuration
+ */
+#define CONFIG_SYS_MMC_BASE		MVEBU_SDIO_BASE
+
+/*
+ * SATA/SCSI/AHCI configuration
+ */
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					 CONFIG_SYS_SCSI_MAX_LUN)
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0x10000000\0"		\
+	"initrd_high=0x10000000\0"
+
+/* SPL */
+/*
+ * Select the boot device here
+ *
+ * Currently supported are:
+ * SPL_BOOT_SPI_NOR_FLASH	- Booting via SPI NOR flash
+ * SPL_BOOT_SDIO_MMC_CARD	- Booting via SDIO/MMC card (partition 1)
+ */
+#define SPL_BOOT_SPI_NOR_FLASH		1
+#define SPL_BOOT_SDIO_MMC_CARD		2
+#define CONFIG_SPL_BOOT_DEVICE		SPL_BOOT_SPI_NOR_FLASH
+
+/* Defines for SPL */
+#define CONFIG_SPL_SIZE			(140 << 10)
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+/* SPL related SPI defines */
+#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
+/* SPL related MMC defines */
+#define CONFIG_SYS_MMC_U_BOOT_OFFS		(160 << 10)
+#define CONFIG_SYS_U_BOOT_OFFS			CONFIG_SYS_MMC_U_BOOT_OFFS
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER	0x00180000	/* in SDRAM */
+#endif
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_DB_88F6820_GP_H */
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
new file mode 100644
index 0000000..907bd0d
--- /dev/null
+++ b/include/configs/db-mv784mp-gp.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_DB_MV7846MP_GP_H
+#define _CONFIG_DB_MV7846MP_GP_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_DB_784MP_GP		/* Board target name for DDR training */
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
+
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/* SATA support */
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_LBA48
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* NAND */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
+ * 0x4000.4030			bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
+ * 0x4007.fffc			BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+/* SPL related SPI defines */
+#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CONFIG_SPD_EEPROM		0x4e
+#define CONFIG_BOARD_ECC_SUPPORT	/* this board supports ECC */
+
+#endif /* _CONFIG_DB_MV7846MP_GP_H */
diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h
new file mode 100644
index 0000000..86d11e4
--- /dev/null
+++ b/include/configs/db-xc3-24g4xg.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_DB_XC3_24G4G_H
+#define _CONFIG_DB_XC3_24G4G_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_SYS_KWD_CONFIG	$(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_SYS_TCLK		200000000	/* 200MHz */
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+
+/* NAND */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0x10000000\0"		\
+	"initrd_high=0x10000000\0"
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_SYS_MAXARGS
+#define CONFIG_SYS_MAXARGS 96
+
+#endif /* _CONFIG_DB_XC3_24G4G_H */
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
new file mode 100644
index 0000000..16031c1
--- /dev/null
+++ b/include/configs/devkit3250.h
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Embest/Timll DevKit3250 board configuration file
+ *
+ * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#ifndef __CONFIG_DEVKIT3250_H__
+#define __CONFIG_DEVKIT3250_H__
+
+/* SoC and board defines */
+#include <linux/sizes.h>
+#include <asm/arch/cpu.h>
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_DEVKIT3250
+
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_SYS_MALLOC_LEN		SZ_1M
+#define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
+#define CONFIG_SYS_SDRAM_SIZE		SZ_64M
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + SZ_32K)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - SZ_1M)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_32K)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
+					 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_SYS_LPC32XX_UART		5   /* UART5 */
+
+/*
+ * DMA
+ */
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_DMA_LPC32XX
+#endif
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_LPC32XX
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/*
+ * GPIO
+ */
+#define CONFIG_LPC32XX_GPIO
+
+/*
+ * SSP/SPI
+ */
+#define CONFIG_LPC32XX_SSP_TIMEOUT	100000
+
+/*
+ * Ethernet
+ */
+#define CONFIG_RMII
+#define CONFIG_PHY_SMSC
+#define CONFIG_LPC32XX_ETH
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+/*
+ * NOR Flash
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+#define CONFIG_SYS_FLASH_BASE		EMC_CS0_BASE
+#define CONFIG_SYS_FLASH_SIZE		SZ_4M
+
+/*
+ * NAND controller
+ */
+#define CONFIG_SYS_NAND_BASE		SLC_NAND_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+
+/*
+ * NAND chip timings
+ */
+#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS	14
+#define CONFIG_LPC32XX_NAND_SLC_WWIDTH		66666666
+#define CONFIG_LPC32XX_NAND_SLC_WHOLD		200000000
+#define CONFIG_LPC32XX_NAND_SLC_WSETUP		50000000
+#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS	14
+#define CONFIG_LPC32XX_NAND_SLC_RWIDTH		66666666
+#define CONFIG_LPC32XX_NAND_SLC_RHOLD		200000000
+#define CONFIG_LPC32XX_NAND_SLC_RSETUP		50000000
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE		0x20000
+#define CONFIG_SYS_NAND_PAGE_SIZE		NAND_LARGE_BLOCK_PAGE_SIZE
+
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI_LPC32XX
+#define CONFIG_USB_ISP1301_I2C_ADDR		0x2d
+
+/*
+ * U-Boot General Configurations
+ */
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * Pass open firmware flat tree
+ */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SIZE			SZ_128K
+#define CONFIG_ENV_OFFSET		0x000A0000
+
+#define CONFIG_BOOTCOMMAND			\
+	"dhcp; "				\
+	"tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; "		\
+	"tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; "	\
+	"setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; "	\
+	"setenv bootargs ${bootargs} ${nfsargs} ${userargs}; "			\
+	"bootm ${loadaddr} - ${dtbaddr}"
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"autoload=no\0"				\
+	"ethaddr=00:01:90:00:C0:81\0"		\
+	"dtbaddr=0x81000000\0"			\
+	"nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0"	\
+	"tftpdir=vladimir/oe/devkit3250\0"	\
+	"userargs=oops=panic\0"
+
+/*
+ * U-Boot Commands
+ */
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_LOADADDR			0x80008000
+
+/*
+ * SPL specific defines
+ */
+/* SPL will be executed at offset 0 */
+
+/* SPL will use SRAM as stack */
+#define CONFIG_SPL_STACK		0x0000FFF8
+
+/* Use the framework and generic lib */
+
+/* SPL will use serial */
+
+/* SPL loads an image from NAND */
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_DRIVERS
+
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SOFTECC
+
+#define CONFIG_SPL_MAX_SIZE		0x20000
+#define CONFIG_SPL_PAD_TO		CONFIG_SPL_MAX_SIZE
+
+/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+
+/* See common/spl/spl.c  spl_set_header_raw_uboot() */
+#define CONFIG_SYS_MONITOR_LEN		CONFIG_SYS_NAND_U_BOOT_SIZE
+
+/*
+ * Include SoC specific configuration
+ */
+#include <asm/arch/config.h>
+
+#endif  /* __CONFIG_DEVKIT3250_H__*/
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
new file mode 100644
index 0000000..baf1a73
--- /dev/null
+++ b/include/configs/devkit8000.h
@@ -0,0 +1,181 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * Configuration settings for the DevKit8000 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MACH_TYPE	MACH_TYPE_DEVKIT8000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+
+#define CONFIG_SPL_BSS_START_ADDR       0x80000500 /* leave space for bootargs*/
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
+
+/*  Physical Memory Map  */
+
+#include <configs/ti_omap3_common.h>
+
+#define CONFIG_REVISION_TAG		1
+
+/* Size of malloc() pool */
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+
+/* Hardware drivers */
+/* DM9000 */
+#define CONFIG_NET_RETRY_COUNT		20
+#define	CONFIG_DRIVER_DM9000		1
+#define	CONFIG_DM9000_BASE		0x2c000000
+#define	DM9000_IO			CONFIG_DM9000_BASE
+#define	DM9000_DATA			(CONFIG_DM9000_BASE + 0x400)
+#define	CONFIG_DM9000_USE_16BIT		1
+#define CONFIG_DM9000_NO_SROM		1
+#undef	CONFIG_DM9000_DEBUG
+
+/* TWL4030 */
+
+/* Board NAND Info */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
+							/* partition */
+
+/* BOOTP/DHCP options */
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_TIMEOFFSET
+#undef CONFIG_BOOTP_VENDOREX
+
+/* Environment information */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"mmcdev=0\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
+	"kernelopts=rw\0" \
+	"commonargs=" \
+		"setenv bootargs console=${console} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay}\0" \
+	"mmcargs=" \
+		"run commonargs; " \
+		"setenv bootargs ${bootargs} " \
+		"root=/dev/mmcblk0p2 " \
+		"rootwait " \
+		"${kernelopts}\0" \
+	"nandargs=" \
+		"run commonargs; " \
+		"setenv bootargs ${bootargs} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=/dev/mtdblock4 " \
+		"rootfstype=jffs2 " \
+		"${kernelopts}\0" \
+	"netargs=" \
+		"run commonargs; " \
+		"setenv bootargs ${bootargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
+		"${kernelopts} " \
+		"dnsip1=${dnsip} " \
+		"dnsip2=${dnsip2}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+	"netboot=echo Booting from network ...; " \
+		"dhcp ${loadaddr}; " \
+		"run netargs; " \
+		"bootm ${loadaddr}\0" \
+	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
+			"if run loadbootscript; then " \
+				"run bootscript; " \
+			"else " \
+				"if run loaduimage; then " \
+					"run mmcboot; " \
+				"else run nandboot; " \
+				"fi; " \
+			"fi; " \
+		"else run nandboot; fi\0"
+
+#define CONFIG_BOOTCOMMAND "run autoboot"
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x07000000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					0x01000000) /* 16MB */
+
+/* SRAM config */
+#define CONFIG_SYS_SRAM_START              0x40200000
+#define CONFIG_SYS_SRAM_SIZE               0x10000
+
+/* Defines for SPL */
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x200000
+
+/* SPL OS boot options */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+
+#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
+#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
+#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x500 /* address 0xa0000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x8   /* address 0x1000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	8     /* 4KB */
+
+#undef CONFIG_SYS_SPL_ARGS_ADDR
+#define CONFIG_SYS_SPL_ARGS_ADDR        (PHYS_SDRAM_1 + 0x100)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h
new file mode 100644
index 0000000..a8e1850
--- /dev/null
+++ b/include/configs/dfi-bt700.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+
+#ifndef CONFIG_INTERNAL_UART
+/* Use BayTrail internal HS UART which is memory-mapped */
+#undef  CONFIG_SYS_NS16550_PORT_MAPPED
+#endif
+
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \
+					"stdout=serial\0" \
+					"stderr=serial\0"
+
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x006ef000
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND	\
+	"load scsi 0:1 03000000 /boot/vmlinuz-${kernel-ver}-generic;"	\
+	"load scsi 0:1 04000000 /boot/initrd.img-${kernel-ver}-generic;" \
+	"run boot"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"kernel-ver=4.4.0-24\0"					\
+	"boot=zboot 03000000 0 04000000 ${filesize}\0"		\
+	"upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;"	\
+		"sf probe;sf update 100000 0 800000;saveenv\0"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
new file mode 100644
index 0000000..a854d0b
--- /dev/null
+++ b/include/configs/dh_imx6.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * DHCOM DH-iMX6 PDK board configuration
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __DH_IMX6_CONFIG_H
+#define __DH_IMX6_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#include "mx6_common.h"
+
+/*
+ * SPI NOR layout:
+ * 0x00_0000-0x00_ffff ... U-Boot SPL
+ * 0x01_0000-0x0f_ffff ... U-Boot
+ * 0x10_0000-0x10_ffff ... U-Boot env #1
+ * 0x11_0000-0x11_ffff ... U-Boot env #2
+ * 0x12_0000-0x1f_ffff ... UNUSED
+ */
+
+/* SPL */
+#include "imx6_spl.h"			/* common IMX6 SPL configuration */
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.imx"
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_BZIP2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(4 * SZ_1M)
+
+/* Bootcounter */
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* FEC ethernet */
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_ARP_TIMEOUT		200UL
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_MMC_ENV_DEV		2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */
+
+/* SATA Configs */
+#define CONFIG_LBA48
+
+/* SPI Flash Configs */
+#if defined(CONFIG_SPL_BUILD)
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#undef CONFIG_SPI_FLASH_MTD
+#endif
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+#define CONFIG_BAUDRATE			115200
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2 /* Enabled USB controller number */
+
+/* USB Gadget (DFU, UMS) */
+#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(16 * 1024 * 1024)
+#define DFU_DEFAULT_POLL_TIMEOUT	300
+
+/* USB IDs */
+#define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
+#define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
+#endif
+#endif
+
+/* Watchdog */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"console=ttymxc0,115200\0"	\
+	"fdt_addr=0x18000000\0"		\
+	"fdt_high=0xffffffff\0"		\
+	"initrd_high=0xffffffff\0"	\
+	"kernel_addr_r=0x10008000\0"	\
+	"fdt_addr_r=0x13000000\0"	\
+	"ramdisk_addr_r=0x18000000\0"	\
+	"scriptaddr=0x14000000\0"	\
+	"fdtfile=imx6q-dhcom-pdk2.dtb\0"\
+	BOOTENV
+
+#define CONFIG_BOOTCOMMAND		"run distro_bootcmd"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 2) \
+	func(USB, usb, 1) \
+	func(SATA, sata, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+#endif
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET		(1024 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_OFFSET_REDUND	\
+	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#endif
+
+#endif	/* __DH_IMX6_CONFIG_H */
diff --git a/include/configs/display5.h b/include/configs/display5.h
new file mode 100644
index 0000000..d806415
--- /dev/null
+++ b/include/configs/display5.h
@@ -0,0 +1,363 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+/* Falcon Mode */
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x18000000
+#define CONFIG_CMD_SPL_WRITE_SIZE	(44 * SZ_1K)
+
+/* Falcon Mode - MMC support */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x3F00
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	\
+	(CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x100	/* 128KiB */
+
+/*
+ * display5 SPI-NOR memory layout
+ *
+ * The definition can be found in Kconfig's
+ * CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT
+ *
+ * 0x000000 - 0x020000 : SPI.SPL (128KiB)
+ * 0x020000 - 0x120000 : SPI.u-boot (1MiB)
+ * 0x120000 - 0x130000 : SPI.u-boot-env1 (64KiB)
+ * 0x130000 - 0x140000 : SPI.u-boot-env2 (64KiB)
+ * 0x140000 - 0x540000 : SPI.swupdate-kernel-FIT (4MiB)
+ * 0x540000 - 0x1540000 : SPI.swupdate-initramfs  (16MiB)
+ * 0x1540000 - 0x1640000 : SPI.factory  (1MiB)
+ */
+
+/* SPI Flash Configs */
+#if defined(CONFIG_SPL_BUILD)
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#undef CONFIG_SPI_FLASH_MTD
+#endif
+
+/* Below values are "dummy" - only to avoid build break */
+#define CONFIG_SYS_SPI_KERNEL_OFFS      0x150000
+#define CONFIG_SYS_SPI_ARGS_OFFS        0x140000
+#define CONFIG_SYS_SPI_ARGS_SIZE        0x10000
+
+#include "imx6_spl.h"
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * 1024 * 1024)
+
+#define CONFIG_MXC_UART_BASE		UART5_BASE
+
+/* I2C Configs */
+#define CONFIG_I2C_MULTI_BUS
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+
+#ifndef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND "if run check_em_pad; then " \
+	     "run recovery;" \
+	"else if test ${BOOT_FROM} = FACTORY; then " \
+	     "run factory_nfs;" \
+	"else " \
+	     "run boot_mmc;" \
+	"fi;fi"
+#endif
+
+#define PARTS_DEFAULT \
+	/* Linux partitions */ \
+	"partitions=" \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=kernel_raw1,start=128K,size=8M,uuid=${uuid_gpt_kernel_raw1};" \
+	"name=rootfs1,size=1528M,uuid=${uuid_gpt_rootfs1};" \
+	"name=kernel_raw2,size=8M,uuid=${uuid_gpt_kernel_raw2};" \
+	"name=rootfs2,size=512M,uuid=${uuid_gpt_rootfs2};" \
+	"name=data,size=-,uuid=${uuid_gpt_data}\0"
+
+#define SWUPDATE_RECOVERY_PROCEDURE \
+	"echo '#######################';" \
+	"echo '# RECOVERY SWUupdate  #';" \
+	"echo '#######################';" \
+	"echo '#######################';" \
+	"echo '# GPT verify          #';" \
+	"if gpt verify mmc ${mmcdev} ${partitions}; then " \
+		"echo '# OK !                #';" \
+	"else " \
+		"echo '# FAILED !            #';" \
+		"echo '# GPT RESTORATION     #';" \
+		"gpt write mmc ${mmcdev} ${partitions};" \
+	"fi;" \
+	"echo '#######################';" \
+	"setenv loadaddr_swu_initramfs 0x14000000;" \
+	"setenv bootargs console=${console} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+		":${hostname}::off root=/dev/ram rw;" \
+	"sf probe;" \
+	"sf read ${loadaddr} swu-kernel;" \
+	"sf read ${loadaddr_swu_initramfs} swu-initramfs;" \
+	"bootm ${loadaddr} ${loadaddr_swu_initramfs};reset;"
+
+#define SETUP_BOOTARGS \
+	"run set_rootfs_part;" \
+	"setenv bootargs ${bootargs} console=${console} "	  \
+		      "root=/dev/mmcblk${mmcdev}p${rootfs_part} " \
+		      "rootwait rootfstype=ext4 rw; " \
+	"run set_kernel_part;" \
+	"part start mmc ${mmcdev} ${kernel_part} lba_start; " \
+	"mmc read ${loadaddr} ${lba_start} ${fitImg_fw_sz}; " \
+	"setenv fdt_conf imx6q-${board}-${display}.dtb; "
+
+/* All the numbers are in LBAs */
+#define __TFTP_UPDATE_KERNEL \
+	"tftp_mmc_fitImg=" \
+	   "if test ! -n ${kernel_part}; then " \
+	       "setenv kernel_part ${kernel_part_active};" \
+	   "fi;" \
+	   "if tftp ${loadaddr} ${kernel_file}; then " \
+	       "setexpr fw_sz ${filesize} / 0x200; " \
+	       "setexpr fw_sz ${fw_sz} + 1; "  \
+	       "part start mmc ${mmcdev} ${kernel_part} lba_start; " \
+	       "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \
+	   "; fi\0" \
+
+#define TFTP_UPDATE_KERNEL \
+	"setenv kernel_part ${kernel_part_active};" \
+	"run tftp_mmc_fitImg;" \
+	"setenv kernel_part ${kernel_part_backup};" \
+	"run tftp_mmc_fitImg;" \
+
+#define __TFTP_UPDATE_ROOTFS \
+	"tftp_mmc_rootfs=" \
+	   "if test ! -n ${rootfs_part}; then " \
+	       "setenv rootfs_part ${rootfs_part_active};" \
+	   "fi;" \
+	   "if tftp ${loadaddr} ${rootfs_file}; then " \
+	       "setexpr fw_sz ${filesize} / 0x200; " \
+	       "setexpr fw_sz ${fw_sz} + 1; "  \
+	       "part start mmc ${mmcdev} ${rootfs_part} lba_start; " \
+	       "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \
+	   "; fi\0" \
+
+#define TFTP_UPDATE_ROOTFS \
+	"setenv rootfs_part ${rootfs_part_active};" \
+	"run tftp_mmc_rootfs;" \
+	"run tftp_mmc_rootfs_bkp;" \
+
+
+#define TFTP_UPDATE_RECOVERY_SWU_KERNEL \
+	"tftp_sf_fitImg_SWU=" \
+	    "if tftp ${loadaddr} ${kernel_file}; then " \
+		"sf probe;" \
+		"sf erase swu-kernel +${filesize};" \
+		"sf write ${loadaddr} swu-kernel ${filesize};" \
+	"; fi\0"	  \
+
+#define TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \
+	"swu_initramfs_file=swupdate-image-display5.ext4.gz.u-boot\0" \
+	"tftp_sf_initramfs_SWU=" \
+	    "if tftp ${loadaddr} ${swu_initramfs_file}; then " \
+		"sf probe;" \
+		"sf erase swu-initramfs +${filesize};" \
+		"sf write ${loadaddr} swu-initramfs ${filesize};" \
+	"; fi\0"	  \
+
+#define TFTP_UPDATE_BOOTLOADER \
+	"ubootfile=u-boot.img\0" \
+	"ubootfileSPL=SPL\0" \
+	"tftp_sf_uboot=" \
+	    "if tftp ${loadaddr} ${ubootfile}; then " \
+		"sf probe;" \
+		"sf erase u-boot +${filesize};" \
+		"sf write ${loadaddr} u-boot ${filesize}" \
+	"; fi\0"	  \
+	"tftp_sf_SPL="	  \
+	    "if tftp ${loadaddr} ${ubootfileSPL}; then " \
+		"sf probe;" \
+		"setexpr uboot_SPL_size ${filesize} + 0x400;" \
+		"sf erase 0x0 +${uboot_SPL_size};" \
+		"sf write ${loadaddr} 0x400 ${filesize};" \
+	"fi\0" \
+
+#define TFTP_UPDATE_SPINOR \
+	"spinorfile=core-image-lwn-display5.spinor\0" \
+	"spinorsize=0x2000000\0" \
+	"tftp_sf_img=" \
+	    "if tftp ${loadaddr} ${spinorfile}; then " \
+		"sf probe;" \
+		"sf erase 0x0 ${spinorsize};" \
+		"sf write ${loadaddr} 0x0 ${filesize};" \
+	"fi\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS	  \
+	PARTS_DEFAULT \
+	"gpio_recovery=93\0" \
+	"check_em_pad=gpio input ${gpio_recovery};test $? -eq 0;\0" \
+	"display=tianma-tm070-800x480\0" \
+	"board=display5\0" \
+	"mmcdev=0\0" \
+	"altbootcmd=run recovery\0" \
+	"bootdelay=1\0" \
+	"baudrate=115200\0" \
+	"bootcmd=" CONFIG_BOOTCOMMAND "\0" \
+	"ethact=FEC\0" \
+	"netdev=eth0\0" \
+	"boot_os=y\0" \
+	"hostname=display5\0" \
+	"loadaddr=0x12000000\0" \
+	"fdtaddr=0x12800000\0" \
+	"console=ttymxc4,115200 quiet cma=256M\0" \
+	"fdtfile=imx6q-display5.dtb\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_file=fitImage\0" \
+	"fitImg_fw_sz=0x2200\0" \
+	"up=run tftp_sf_SPL; run tftp_sf_uboot\0" \
+	"download_kernel=" \
+		"tftpboot ${loadaddr} ${kernel_file};\0" \
+	"factory_nfs=" \
+	     "setenv ipaddr 192.168.1.102;" \
+	     "setenv gatewayip 192.168.1.1;" \
+	     "setenv netmask 255.255.255.0;" \
+	     "setenv serverip 192.168.1.2;" \
+	     "echo BOOT: FACTORY (LEG);" \
+	     "run boot_nfs\0" \
+	"boot_swu_recovery=" SWUPDATE_RECOVERY_PROCEDURE "\0" \
+	"recovery=" \
+	     "echo BOOT: RECOVERY: SWU;" \
+	     "run boot_swu_recovery\0" \
+	"boot_tftp=" \
+	"if run download_kernel; then "	  \
+	     "setenv bootargs console=${console} " \
+	     "root=/dev/mmcblk0p2 rootwait;" \
+	     "bootm ${loadaddr} - ${fdtaddr};reset;" \
+	"fi\0" \
+	"addip=setenv bootargs ${bootargs} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
+	    "${hostname}:eth0:on"	  \
+	"\0"	  \
+	"nfsargs=setenv bootargs " \
+	"root=/dev/nfs rw "	  \
+	"nfsroot=${serverip}:${rootpath},nolock,nfsvers=3" \
+	"\0" \
+	"rootpath=/srv/tftp/DISP5/rootfs\0" \
+	"boot_nfs=" \
+	"if run download_kernel; then "	  \
+	     "run nfsargs;"	  \
+	     "run addip;"	  \
+	     "setenv bootargs ${bootargs} console=${console};"	  \
+	     "setenv fdt_conf imx6q-${board}-${display}.dtb; " \
+	     "bootm ${loadaddr}#conf@${fdt_conf};reset;" \
+	"fi\0" \
+	"falcon_setup=" \
+	"if mmc dev ${mmcdev}; then "	  \
+	     SETUP_BOOTARGS \
+	     "spl export fdt ${loadaddr}#conf@${fdt_conf};" \
+	     "setexpr fw_sz ${fdtargslen} / 0x200; " \
+	     "setexpr fw_sz ${fw_sz} + 1; "  \
+	     "mmc write ${fdtargsaddr} " \
+	     __stringify(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR)" ${fw_sz}; " \
+	"fi\0" \
+	"boot_mmc=" \
+	"if mmc dev ${mmcdev}; then "	  \
+	     SETUP_BOOTARGS \
+	     "bootm ${loadaddr}#conf@${fdt_conf};reset;" \
+	"fi\0" \
+	"set_kernel_part=" \
+	"if test ${BOOT_FROM} = ACTIVE; then " \
+	     "setenv kernel_part ${kernel_part_active};" \
+	     "echo BOOT: ACTIVE;" \
+	"else if test ${BOOT_FROM} = BACKUP; then " \
+	     "setenv kernel_part ${kernel_part_backup};" \
+	     "echo BOOT: BACKUP;" \
+	"else " \
+	     "run recovery;" \
+	"fi;fi\0" \
+	"set_rootfs_part=" \
+	"if test ${BOOT_FROM} = ACTIVE; then " \
+	     "setenv rootfs_part ${rootfs_part_active};" \
+	"else if test ${BOOT_FROM} = BACKUP; then " \
+	     "setenv rootfs_part ${rootfs_part_backup};" \
+	"else " \
+	     "run recovery;" \
+	"fi;fi\0" \
+	"BOOT_FROM=ACTIVE\0" \
+	TFTP_UPDATE_BOOTLOADER \
+	TFTP_UPDATE_SPINOR \
+	"kernel_part_active=1\0" \
+	"kernel_part_backup=3\0" \
+	__TFTP_UPDATE_KERNEL \
+	"rootfs_part_active=2\0" \
+	"rootfs_part_backup=4\0" \
+	"rootfs_file=core-image-lwn-display5.ext4\0" \
+	"rootfs_file_backup=core-image-lwn-backup-display5.ext4\0" \
+	__TFTP_UPDATE_ROOTFS \
+	"tftp_mmc_rootfs_bkp=" \
+	   "setenv rootfs_part ${rootfs_part_backup};" \
+	   "setenv rootfs_file ${rootfs_file_backup};" \
+	   "run tftp_mmc_rootfs\0" \
+	TFTP_UPDATE_RECOVERY_SWU_KERNEL \
+	TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \
+	"\0" \
+
+/* Miscellaneous configurable options */
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE		2048
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_STANDALONE_LOAD_ADDR	0x10001000
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Watchdog */
+#if defined(CONFIG_SPL_BUILD)
+#undef CONFIG_WDT
+#undef CONFIG_WATCHDOG
+#define CONFIG_HW_WATCHDOG
+#endif
+
+/* ENV config */
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE		(SZ_64K)
+/* The 0x120000 value corresponds to above SPI-NOR memory MAP */
+#define CONFIG_ENV_OFFSET		(0x120000)
+#define CONFIG_ENV_SECT_SIZE		(SZ_64K)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#endif
+
+#define CONFIG_MXC_USB_PORTSC           (PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif /* __CONFIG_H */
diff --git a/include/configs/dns325.h b/include/configs/dns325.h
new file mode 100644
index 0000000..f72ee90
--- /dev/null
+++ b/include/configs/dns325.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011
+ * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef _CONFIG_DNS325_H
+#define _CONFIG_DNS325_H
+
+/*
+ * Machine number definition
+ */
+#define CONFIG_MACH_TYPE		MACH_TYPE_DNS325
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS		{1, 0} /* enable port 0 only */
+#define CONFIG_NETCONSOLE
+#endif
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
+#endif
+
+/*
+ * Enable GPI0 support
+ */
+#define CONFIG_KIRKWOOD_GPIO
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128KB */
+#endif
+
+#define CONFIG_ENV_SIZE			0x20000	/* 128KB */
+#define CONFIG_ENV_ADDR			0xe0000
+#define CONFIG_ENV_OFFSET		0xe0000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0" \
+	"loadaddr=0x800000\0" \
+	"autoload=no\0" \
+	"console=ttyS0,115200\0" \
+	"mtdparts="CONFIG_MTDPARTS_DEFAULT \
+	"optargs=\0" \
+	"bootenv=uEnv.txt\0" \
+	"importbootenv=echo Importing environment ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadbootenv=fatload usb 0 ${loadaddr} ${bootenv}\0" \
+	"setbootargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"${mtdparts} " \
+		"root=${bootenvroot} " \
+		"rootfstype=${bootenvrootfstype}\0" \
+	"subbootcmd=run setbootargs; " \
+		"if run bootenvloadimage; then " \
+			"bootm ${loadaddr};" \
+		"fi;\0" \
+	"nandroot=ubi0:rootfs ubi.mtd=rootfs\0" \
+	"nandrootfstype=ubifs\0" \
+	"nandloadimage=nand read ${loadaddr} kernel\0" \
+	"setnandbootenv=echo Booting from nand ...; " \
+		"setenv bootenvroot ${nandroot}; " \
+		"setenv bootenvrootfstype ${nandrootfstype}; " \
+		"setenv bootenvloadimage ${nandloadimage}\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"if test -n ${bootenv} && usb start; then " \
+		"if run loadbootenv; then " \
+			"echo Loaded environment ${bootenv} from usb;" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n ${bootenvcmd}; then " \
+			"echo Running bootenvcmd ...;" \
+			"run bootenvcmd;" \
+		"fi;" \
+	"fi;" \
+	"run setnandbootenv subbootcmd;"
+
+#endif /* _CONFIG_DNS325_H */
diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h
new file mode 100644
index 0000000..f339788
--- /dev/null
+++ b/include/configs/dockstar.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.h originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#ifndef _CONFIG_DOCKSTAR_H
+#define _CONFIG_DOCKSTAR_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0x80000
+#define CONFIG_ENV_OFFSET		0x80000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; "	\
+	"ubi part root; " \
+	"ubifsmount ubi:root; " \
+	"ubifsload 0x800000 ${kernel}; " \
+	"ubifsload 0x1100000 ${initrd}; " \
+	"bootm 0x800000 0x1100000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=console=ttyS0,115200\0" \
+	"mtdids=nand0=orion_nand\0" \
+	"mtdparts="CONFIG_MTDPARTS_DEFAULT \
+	"kernel=/boot/uImage\0" \
+	"initrd=/boot/uInitrd\0" \
+	"bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * File system
+ */
+
+#endif /* _CONFIG_DOCKSTAR_H */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
new file mode 100644
index 0000000..3487b8a
--- /dev/null
+++ b/include/configs/dra7xx_evm.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Lokesh Vutla	  <lokeshvutla@ti.com>
+ *
+ * Configuration settings for the TI DRA7XX board.
+ * See ti_omap5_common.h for omap5 common settings.
+ */
+
+#ifndef __CONFIG_DRA7XX_EVM_H
+#define __CONFIG_DRA7XX_EVM_H
+
+#include <environment/ti/dfu.h>
+
+#define CONFIG_IODELAY_RECALIBRATION
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED		0x80000000
+
+#ifndef CONFIG_QSPI_BOOT
+/* MMC ENV related defines */
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+#if (CONFIG_CONS_INDEX == 1)
+#define CONSOLEDEV			"ttyS0"
+#elif (CONFIG_CONS_INDEX == 3)
+#define CONSOLEDEV			"ttyS2"
+#endif
+#define CONFIG_SYS_NS16550_COM1		UART1_BASE	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		UART2_BASE	/* UART2 */
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE	/* UART3 */
+
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+#define CONFIG_SYS_OMAP_ABE_SYSCK
+
+#ifndef CONFIG_SPL_BUILD
+#define DFUARGS \
+	"dfu_bufsiz=0x10000\0" \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_EMMC \
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_QSPI
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_CMD_BOOTD
+#ifdef CONFIG_SPL_DFU
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
+#define DFUARGS \
+	"dfu_bufsiz=0x10000\0" \
+	DFU_ALT_INFO_RAM
+#endif
+#endif
+
+#include <configs/ti_omap5_common.h>
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_HSMMC2_8BIT
+
+/* CPSW Ethernet */
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		10
+#define CONFIG_PHY_TI
+
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
+ * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
+ * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
+ * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
+ * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
+ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
+ * 0x9E0000 - 0x2000000 : USERLAND
+ */
+#define CONFIG_SYS_SPI_KERNEL_OFFS	0x1E0000
+#define CONFIG_SYS_SPI_ARGS_OFFS	0x140000
+#define CONFIG_SYS_SPI_ARGS_SIZE	0x80000
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE			(64 << 10)
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64 KB sectors */
+#define CONFIG_ENV_OFFSET		0x1C0000
+#define CONFIG_ENV_OFFSET_REDUND	0x1D0000
+#endif
+
+/* SPI SPL */
+
+/* USB xHCI HOST */
+#define CONFIG_USB_XHCI_OMAP
+
+#define CONFIG_OMAP_USB2PHY2_HOST
+
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+/* NAND support */
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x00140000
+/* NAND: SPL related configs */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+#endif
+#endif /* !CONFIG_NAND */
+
+/* Parallel NOR Support */
+#if defined(CONFIG_NOR)
+/* NOR: device related configs */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE		(64 * 1024 * 1024) /* 64 MB */
+/* #define CONFIG_INIT_IGNORE_ERROR */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BASE		(0x08000000)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
+#endif
+#endif  /* NOR support */
+
+#endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/draak.h b/include/configs/draak.h
new file mode 100644
index 0000000..9a8d6a4
--- /dev/null
+++ b/include/configs/draak.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/draak.h
+ *     This file is Draak board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ */
+
+#ifndef __DRAAK_H
+#define __DRAAK_H
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0x08000000 }
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+#endif /* __DRAAK_H */
diff --git a/include/configs/draco.h b/include/configs/draco.h
new file mode 100644
index 0000000..ffeb398
--- /dev/null
+++ b/include/configs/draco.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef __CONFIG_DRACO_H
+#define __CONFIG_DRACO_H
+
+#define CONFIG_SIEMENS_MACH_TYPE	MACH_TYPE_DRACO
+
+#include "siemens-am33x-common.h"
+
+#define DDR_PLL_FREQ	303
+
+#define BOARD_DFU_BUTTON_GPIO	27	/* Use as default */
+#define GPIO_LAN9303_NRST	88	/* GPIO2_24 = gpio88 */
+
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	"button_dfu0=27\0" \
+	"led0=103,1,0\0" \
+	"led1=64,0,1\0"
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* Define own nand partitions */
+#define CONFIG_ENV_OFFSET_REDUND    0x2E0000
+#define CONFIG_ENV_SIZE_REDUND      0x2000
+#define CONFIG_ENV_RANGE        (4 * CONFIG_SYS_ENV_SECT_SIZE)
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=draco\0" \
+	"ubi_off=2048\0"\
+	"nand_img_size=0x400000\0" \
+	"optargs=\0" \
+	"preboot=draco_led 0\0" \
+	CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	CONFIG_ENV_SETTINGS_V2 \
+	CONFIG_ENV_SETTINGS_NAND_V2
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+	"run dfu_start; " \
+	"reset; " \
+"fi;" \
+"run nand_boot;" \
+"run nand_boot_backup;" \
+"reset;"
+
+#else
+
+#define CONFIG_BOOTCOMMAND			\
+	"setenv autoload no; "			\
+	"dhcp; "				\
+	"if tftp 80000000 debrick.scr; then "	\
+		"source 80000000; "		\
+	"fi"
+#endif
+#endif	/* CONFIG_SPL_BUILD */
+#endif	/* ! __CONFIG_DRACO_H */
diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h
new file mode 100644
index 0000000..bf0e031
--- /dev/null
+++ b/include/configs/dragonboard410c.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board configuration file for Dragonboard 410C
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ */
+
+#ifndef __CONFIGS_DRAGONBOARD410C_H
+#define __CONFIGS_DRAGONBOARD410C_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap-apq8016.h>
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1			0x80000000
+/* 1008 MB (the last ~30Mb are secured for TrustZone by ATF*/
+#define PHYS_SDRAM_1_SIZE		0x3da00000
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x80000)
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+/* UART */
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		19000000
+
+/* Fixup - in init code we switch from device to host mode,
+ * it has to be done after each HCD reset */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Does what recovery does */
+#define REFLASH(file, part) \
+"part start mmc 0 "#part" start && "\
+"part size mmc 0 "#part" size && "\
+"tftp $loadaddr "#file" && " \
+"mmc write $loadaddr $start $size && "
+
+#define CONFIG_ENV_REFLASH \
+"mmc dev 0 && "\
+"usb start && "\
+"dhcp && "\
+"tftp $loadaddr dragonboard/rescue/gpt_both0.bin && "\
+"mmc write $loadaddr 0 43 && " \
+"mmc rescan && "\
+REFLASH(dragonboard/rescue/NON-HLOS.bin, 1)\
+REFLASH(dragonboard/rescue/sbl1.mbn, 2)\
+REFLASH(dragonboard/rescue/rpm.mbn, 3)\
+REFLASH(dragonboard/rescue/tz.mbn, 4)\
+REFLASH(dragonboard/rescue/hyp.mbn, 5)\
+REFLASH(dragonboard/rescue/sec.dat, 6)\
+REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7)\
+REFLASH(dragonboard/u-boot.img, 8)\
+"usb stop &&"\
+"echo Reflash completed"
+
+/* Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"reflash="CONFIG_ENV_REFLASH"\0"\
+	"loadaddr=0x81000000\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"linux_image=Image\0" \
+	"kernel_addr_r=0x81000000\0"\
+	"fdtfile=qcom/apq8016-sbc.dtb\0" \
+	"fdt_addr_r=0x83000000\0"\
+	"ramdisk_addr_r=0x84000000\0"\
+	"scriptaddr=0x90000000\0"\
+	"pxefile_addr_r=0x90100000\0"\
+	BOOTENV
+
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* mmc0 = emmc, mmc1 = sd */
+#define CONFIG_SYS_MMC_ENV_PART 2 /* Set env partition to BOOT2 partition */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_8M)
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#endif
diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h
new file mode 100644
index 0000000..a41df22
--- /dev/null
+++ b/include/configs/dragonboard820c.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board configuration file for Dragonboard 410C
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ */
+
+#ifndef __CONFIGS_DRAGONBOARD820C_H
+#define __CONFIGS_DRAGONBOARD820C_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap-apq8096.h>
+
+/* Physical Memory Map */
+
+#define PHYS_SDRAM_SIZE			0xC0000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_1_SIZE		0x60000000
+#define PHYS_SDRAM_2			0x100000000
+#define PHYS_SDRAM_2_SIZE		0x5ea4ffff
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x80000)
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		19000000
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_bootcmd.h>
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x95000000\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"linux_image=uImage\0" \
+	"kernel_addr_r=0x95000000\0"\
+	"fdtfile=qcom/apq8096-db820c.dtb\0" \
+	"fdt_addr_r=0x93000000\0"\
+	"ramdisk_addr_r=0x91000000\0"\
+	"scriptaddr=0x90000000\0"\
+	"pxefile_addr_r=0x90100000\0"\
+	BOOTENV
+
+#define CONFIG_ENV_SIZE			0x4000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_8M)
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512
+#define CONFIG_SYS_MAXARGS		64
+
+#endif
diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h
new file mode 100644
index 0000000..f7f9141
--- /dev/null
+++ b/include/configs/dreamplug.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ */
+
+#ifndef _CONFIG_DREAMPLUG_H
+#define _CONFIG_DREAMPLUG_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SHEEVA_88SV131	1	/* CPU Core subversion */
+#define CONFIG_MACH_TYPE	MACH_TYPE_DREAMPLUG
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * mv-plug-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-plug-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE		0x10000	/* 64k */
+#endif
+
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x1000  /* 4k */
+#define CONFIG_ENV_ADDR			0x100000
+#define CONFIG_ENV_OFFSET		0x100000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"setenv ethact egiga0; " \
+	"${x_bootcmd_ethernet}; setenv ethact egiga1; " \
+	"${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"bootm 0x6400000;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"x_bootcmd_ethernet=ping 192.168.2.1\0"	\
+	"x_bootcmd_usb=usb start\0"	\
+	"x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \
+	"x_bootargs=console=ttyS0,115200\0"	\
+	"x_bootargs_root=root=/dev/sda2 rootdelay=10\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 1}	/* enable both ports */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#endif /* _CONFIG_DREAMPLUG_H */
diff --git a/include/configs/ds109.h b/include/configs/ds109.h
new file mode 100644
index 0000000..31abb4b
--- /dev/null
+++ b/include/configs/ds109.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ */
+
+#ifndef _CONFIG_DS109_H
+#define _CONFIG_DS109_H
+
+/* Provide the MACH_TYPE value that the vendor kernel requires. */
+#define CONFIG_MACH_TYPE		527
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SHEEVA_88SV131	1	/* CPU Core subversion */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_EXT2
+
+/*
+ * mv-plug-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-plug-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE		0x10000	/* 64k */
+#endif
+
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_ADDR			0x3d0000
+#define CONFIG_ENV_OFFSET		0x3d0000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"setenv ethact egiga0; " \
+	"${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"bootm 0x6400000;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"x_bootcmd_ethernet=ping 192.168.1.2\0"	\
+	"x_bootcmd_usb=usb start\0"	\
+	"x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \
+	"x_bootargs=console=ttyS0,115200\0"	\
+	"x_bootargs_root=root=/dev/sda2 rootdelay=10\0" \
+	"ipaddr=192.168.1.5\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable one port */
+#define CONFIG_PHY_BASE_ADR	8
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#endif /* _CONFIG_DS109_H */
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
new file mode 100644
index 0000000..552c744
--- /dev/null
+++ b/include/configs/ds414.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_SYNOLOGY_DS414_H
+#define _CONFIG_SYNOLOGY_DS414_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		0x7E0000   /* RedBoot config partition in DTS */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
+
+#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_RGMII
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* USB/EHCI/XHCI configuration */
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* FIXME: broken XHCI support
+ * Below defines should enable support for the two rear USB3 ports. Sadly, this
+ * does not work because:
+ * - xhci-pci seems to not support DM_USB, so with that enabled it is not
+ *   found.
+ * - USB init fails, controller does not respond in time */
+
+#if !defined(CONFIG_USB_XHCI_HCD)
+#define CONFIG_EHCI_IS_TDI
+#endif
+
+/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
+ * 0x4000.4030			bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
+ * 0x4007.fffc			BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+/* SPL related SPI defines */
+
+/* DS414 bus width is 32bits */
+#define CONFIG_DDR_32BIT
+
+/* Default Environment */
+#define CONFIG_BOOTCOMMAND	"sf read ${loadaddr} 0xd0000 0x700000; bootm"
+#define CONFIG_LOADADDR		0x80000
+
+#endif /* _CONFIG_SYNOLOGY_DS414_H */
diff --git a/include/configs/duovero.h b/include/configs/duovero.h
new file mode 100644
index 0000000..dccb369
--- /dev/null
+++ b/include/configs/duovero.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright: 2013
+ * Gumstix, Inc - http://www.gumstix.com
+ * Maintainer: Ash Charles  <ash@gumstix.com>
+ *
+ * Configuration settings for the Gumstix DuoVero board.
+ * See omap4_common.h for OMAP4 common part
+ */
+
+#ifndef __CONFIG_DUOVERO_H
+#define __CONFIG_DUOVERO_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_DUOVERO
+#define CONFIG_MACH_TYPE                MACH_TYPE_DUOVERO
+
+#include <configs/ti_omap4_common.h>
+
+#undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+
+/* USB UHH support options */
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
+
+#define CONFIG_SYS_ENABLE_PADS_ALL
+
+/* GPIO */
+
+/* ENV related config options */
+
+#endif /* __CONFIG_DUOVERO_H */
diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h
new file mode 100644
index 0000000..c636bf9
--- /dev/null
+++ b/include/configs/e2220-1170.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _E2220_1170_H
+#define _E2220_1170_H
+
+#include <linux/sizes.h>
+
+#include "tegra210-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA E2220-1170"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_SPI_FLASH_SIZE		(4 << 20)
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* _E2220_1170_H */
diff --git a/include/configs/eagle.h b/include/configs/eagle.h
new file mode 100644
index 0000000..f0e4bca
--- /dev/null
+++ b/include/configs/eagle.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/eagle.h
+ *     This file is Eagle board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ */
+
+#ifndef __EAGLE_H
+#define __EAGLE_H
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Environment compatibility */
+#undef CONFIG_ENV_SIZE_REDUND
+#undef CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_OFFSET	0x700000
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define CONFIG_SYS_CLK_FREQ	33333333u
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
+
+#endif /* __EAGLE_H */
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
new file mode 100644
index 0000000..e266e1f
--- /dev/null
+++ b/include/configs/eb_cpu5282.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
+ *
+ * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ */
+
+#ifndef _CONFIG_EB_CPU5282_H_
+#define _CONFIG_EB_CPU5282_H_
+
+#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
+
+/*----------------------------------------------------------------------*
+ * High Level Configuration Options (easy to change)                    *
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+
+#undef	CONFIG_MONITOR_IS_IN_RAM		/* starts uboot direct */
+
+#define CONFIG_BOOTCOMMAND "printenv"
+
+/*----------------------------------------------------------------------*
+ * Options								*
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_BOOT_RETRY_TIME	-1
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_SPLASH_SCREEN
+
+#define CONFIG_HW_WATCHDOG
+
+#define STATUS_LED_ACTIVE		0
+
+/*----------------------------------------------------------------------*
+ * Configuration for environment					*
+ * Environment is in the second sector of the first 256k of flash	*
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_ENV_ADDR		0xFF040000
+#define CONFIG_ENV_SECT_SIZE	0x00020000
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_MCFTMR
+
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		0x20000
+
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		0x400000
+/*#define CONFIG_SYS_DRAM_TEST		1 */
+#undef CONFIG_SYS_DRAM_TEST
+
+/*----------------------------------------------------------------------*
+ * Clock and PLL Configuration						*
+ *----------------------------------------------------------------------*/
+#define	CONFIG_SYS_CLK			80000000      /* 8MHz * 8 */
+
+/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
+
+#define CONFIG_SYS_MFD		0x02	/* PLL Multiplication Factor Devider */
+#define CONFIG_SYS_RFD		0x00	/* PLL Reduce Frecuency Devider */
+
+/*----------------------------------------------------------------------*
+ * Network								*
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_MCFFEC
+#define CONFIG_MII_INIT			1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#define CONFIG_SYS_FEC0_PINMUX		0
+#define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#define MCFFEC_TOUT_LOOP		50000
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*-------------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ *-----------------------------------------------------------------------*/
+
+#define	CONFIG_SYS_MBAR			0x40000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE0		0x00000000
+#define	CONFIG_SYS_SDRAM_SIZE0		16	/* SDRAM size in MB */
+
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_SDRAM_BASE0
+#define	CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_SDRAM_SIZE0
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define	CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define	CONFIG_SYS_INT_FLASH_BASE	0xF0000000
+#define CONFIG_SYS_INT_FLASH_ENABLE	0x21
+
+#define	CONFIG_SYS_MAX_FLASH_SECT	128
+#define	CONFIG_SYS_MAX_FLASH_BANKS	1
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	10000000
+
+#define CONFIG_SYS_FLASH_SIZE		16*1024*1024
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DBWE | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+#define CONFIG_SYS_CS0_BASE		0xFF000000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+
+#define CONFIG_SYS_CS2_BASE		0xE0000000
+#define CONFIG_SYS_CS2_CTRL		0x00001980
+#define CONFIG_SYS_CS2_MASK		0x000F0001
+
+#define CONFIG_SYS_CS3_BASE		0xE0100000
+#define CONFIG_SYS_CS3_CTRL		0x00001980
+#define CONFIG_SYS_CS3_MASK		0x000F0001
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
+#define CONFIG_SYS_PADDR		0x0000000
+#define CONFIG_SYS_PADAT		0x0000000
+
+#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
+#define CONFIG_SYS_PBDDR		0x0000000
+#define CONFIG_SYS_PBDAT		0x0000000
+
+#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
+
+#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
+
+#define CONFIG_SYS_PASPAR		0x0F0F
+#define CONFIG_SYS_PEHLPAR		0xC0
+#define CONFIG_SYS_PUAPAR		0x0F
+#define CONFIG_SYS_DDRUA		0x05
+#define CONFIG_SYS_PJPAR		0xFF
+
+/*-----------------------------------------------------------------------
+ * I2C
+ */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+#define CONFIG_SYS_FSL_I2C_SPEED	100000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0
+
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1338
+#define CONFIG_I2C_RTC_ADDR		0x68
+#endif
+
+/*-----------------------------------------------------------------------
+ * VIDEO configuration
+ */
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_VCXK			1
+
+#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN	2
+#define	CONFIG_SYS_VCXK_DOUBLEBUFFERED		1
+#define CONFIG_SYS_VCXK_BASE			CONFIG_SYS_CS2_BASE
+
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT	MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR		MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN		0x0001
+
+#define CONFIG_SYS_VCXK_ENABLE_PORT		MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_ENABLE_DDR		MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_ENABLE_PIN		0x0002
+
+#define CONFIG_SYS_VCXK_REQUEST_PORT		MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_REQUEST_DDR		MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_REQUEST_PIN		0x0004
+
+#define CONFIG_SYS_VCXK_INVERT_PORT		MCFGPIO_PORTE
+#define CONFIG_SYS_VCXK_INVERT_DDR		MCFGPIO_DDRE
+#define CONFIG_SYS_VCXK_INVERT_PIN		MCFGPIO_PORT2
+
+#endif /* CONFIG_VIDEO */
+#endif	/* _CONFIG_M5282EVB_H */
+/*---------------------------------------------------------------------*/
diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h
new file mode 100644
index 0000000..2e4974a
--- /dev/null
+++ b/include/configs/ebisu.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/ebisu.h
+ *     This file is Ebisu board configuration.
+ *
+ * Copyright (C) 2018 Renesas Electronics Corporation
+ */
+
+#ifndef __EBISU_H
+#define __EBISU_H
+
+#undef DEBUG
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_NET_MULTI
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		2
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+#endif /* __EBISU_H */
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
new file mode 100644
index 0000000..84cbcdd
--- /dev/null
+++ b/include/configs/edb93xx.h
@@ -0,0 +1,201 @@
+/*
+ * U-Boot - Configuration file for Cirrus Logic EDB93xx boards
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_MK_edb9301
+#define CONFIG_EDB9301
+#elif defined(CONFIG_MK_edb9302)
+#define CONFIG_EDB9302
+#elif defined(CONFIG_MK_edb9302a)
+#define CONFIG_EDB9302A
+#elif defined(CONFIG_MK_edb9307)
+#define CONFIG_EDB9307
+#elif defined(CONFIG_MK_edb9307a)
+#define CONFIG_EDB9307A
+#elif defined(CONFIG_MK_edb9312)
+#define CONFIG_EDB9312
+#elif defined(CONFIG_MK_edb9315)
+#define CONFIG_EDB9315
+#elif defined(CONFIG_MK_edb9315a)
+#define CONFIG_EDB9315A
+#else
+#error "no board defined"
+#endif
+
+/* Initial environment and monitor configuration options. */
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_BOOTFILE		"edb93xx.img"
+
+#ifdef CONFIG_EDB9301
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9301
+#define CONFIG_ENV_SECT_SIZE		0x00020000
+#elif defined(CONFIG_EDB9302)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9302
+#define CONFIG_ENV_SECT_SIZE		0x00020000
+#elif defined(CONFIG_EDB9302A)
+#define CONFIG_EP9302
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9302A
+#define CONFIG_ENV_SECT_SIZE		0x00020000
+#elif defined(CONFIG_EDB9307)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9307
+#define CONFIG_ENV_SECT_SIZE		0x00040000
+#elif defined(CONFIG_EDB9307A)
+#define CONFIG_EP9307
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9307A
+#define CONFIG_ENV_SECT_SIZE		0x00020000
+#elif defined(CONFIG_EDB9312)
+#define CONFIG_EP9312
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9312
+#define CONFIG_ENV_SECT_SIZE		0x00040000
+#elif defined(CONFIG_EDB9315)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9315
+#define CONFIG_ENV_SECT_SIZE		0x00040000
+#elif defined(CONFIG_EDB9315A)
+#define CONFIG_EP9315
+#define CONFIG_MACH_TYPE		MACH_TYPE_EDB9315A
+#define CONFIG_ENV_SECT_SIZE		0x00020000
+#else
+#error "no board defined"
+#endif
+
+/* High-level configuration options */
+#define CONFIG_EP93XX		1		/* This is a Cirrus Logic 93xx SoC */
+
+#define CONFIG_SYS_CLK_FREQ	14745600	/* EP93xx has a 14.7456 clock */
+
+/* Monitor configuration */
+
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O buffer size */
+
+/* Serial port hardware configuration */
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, \
+                        115200, 230400}
+#define CONFIG_SYS_SERIAL0		0x808C0000
+#define CONFIG_SYS_SERIAL1		0x808D0000
+/*#define CONFIG_PL01x_PORTS	{(void *)CONFIG_SYS_SERIAL0, \
+            (void *)CONFIG_SYS_SERIAL1} */
+
+#define CONFIG_PL01x_PORTS	{(void *)CONFIG_SYS_SERIAL0}
+
+/* Status LED */
+/* Optional value */
+
+/* Network hardware configuration */
+#define CONFIG_DRIVER_EP93XX_MAC
+#define CONFIG_MII_SUPPRESS_PREAMBLE
+#undef CONFIG_NETCONSOLE
+
+/* SDRAM configuration */
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
+    defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \
+    defined(CONFIG_EDB9315)
+/*
+ * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ *
+ * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of
+ * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of
+ * 64 MB of SDRAM.
+ */
+
+#define CONFIG_EDB93XX_SDCS3
+
+#elif defined(CONFIG_EDB9302A) || \
+    defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
+/*
+ * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75
+ * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set
+ * the SROMLL bit on the processor, resulting in this non-contiguous memory map.
+ *
+ * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung
+ * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM.
+ */
+#define CONFIG_EDB93XX_SDCS0
+
+#else
+#error "no SDCS configuration for this board"
+#endif
+
+#if defined(CONFIG_EDB93XX_SDCS3)
+#define CONFIG_SYS_LOAD_ADDR	0x01000000	/* Default load address	*/
+#define PHYS_SDRAM_1		0x00000000
+#elif defined(CONFIG_EDB93XX_SDCS0)
+#define CONFIG_SYS_LOAD_ADDR	0xc1000000	/* Default load address	*/
+#define PHYS_SDRAM_1		0xc0000000
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+    (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE)
+
+/* Must match kernel config */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+
+/* Run-time memory allocatons */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+
+/* -----------------------------------------------------------------------------
+ * FLASH and environment organization
+ *
+ * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at
+ * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit
+ * data bus, for a total of 16 MB of CFI-compatible flash.
+ *
+ * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at
+ * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
+ * data bus, for a total of 32 MB of CFI-compatible flash.
+ *
+ *
+ *                            EDB9301/02(a)7a/15a    EDB9307/12/15
+ * 0x60000000 - 0x0003FFFF    u-boot                 u-boot
+ * 0x60040000 - 0x0005FFFF    environment #1         environment #1
+ * 0x60060000 - 0x0007FFFF    environment #2         environment #1 (continued)
+ * 0x60080000 - 0x0009FFFF    unused                 environment #2
+ * 0x600A0000 - 0x000BFFFF    unused                 environment #2 (continued)
+ * 0x600C0000 - 0x00FFFFFF    unused                 unused
+ * 0x61000000 - 0x01FFFFFF    not present            unused
+ */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	(256+8)
+
+#define PHYS_FLASH_1			CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+
+#define CONFIG_ENV_OVERWRITE		/* Vendor params unprotected */
+
+#define CONFIG_ENV_ADDR			0x60040000
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_OHCI_EP93XX
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ep93xx-ohci"
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x80020000
+
+/* Define to disable flash configuration*/
+/* #define CONFIG_EP93XX_NO_FLASH_CFG */
+
+/* Define this for indusrial rated chips */
+/* #define CONFIG_EDB93XX_INDUSTRIAL */
+
+#endif /* !defined (__CONFIG_H) */
diff --git a/include/configs/edison.h b/include/configs/edison.h
new file mode 100644
index 0000000..218b50a
--- /dev/null
+++ b/include/configs/edison.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Intel Corp.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/ibmpc.h>
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_CBSIZE	2048
+#define CONFIG_SYS_MAXARGS	128
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/* Memory */
+#define CONFIG_SYS_LOAD_ADDR			0x100000
+#define CONFIG_PHYSMEM
+
+#define CONFIG_SYS_STACK_SIZE			(32 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN			(256 * 1024)
+
+#define CONFIG_SYS_MALLOC_LEN			(128 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START		0x00100000
+#define CONFIG_SYS_MEMTEST_END			0x01000000
+
+/* Environment */
+#define CONFIG_SYS_MMC_ENV_DEV			0
+#define CONFIG_SYS_MMC_ENV_PART			0
+#define CONFIG_ENV_SIZE				(64 * 1024)
+#define CONFIG_ENV_OFFSET			(3 * 1024 * 1024)
+#define CONFIG_ENV_OFFSET_REDUND		(6 * 1024 * 1024)
+
+/* RTC */
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
+
+#endif
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
new file mode 100644
index 0000000..f071718
--- /dev/null
+++ b/include/configs/edminiv2.h
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef _CONFIG_EDMINIV2_H
+#define _CONFIG_EDMINIV2_H
+
+/*
+ * SPL
+ */
+
+#define CONFIG_SPL_MAX_SIZE		0x0000fff0
+#define CONFIG_SPL_STACK		0x00020000
+#define CONFIG_SPL_BSS_START_ADDR	0x00020000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x0001ffff
+#define CONFIG_SYS_SPL_MALLOC_START	0x00040000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x0001ffff
+#define CONFIG_SYS_UBOOT_BASE		0xfff90000
+#define CONFIG_SYS_UBOOT_START		0x00800000
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_FEROCEON		1	/* CPU Core subversion */
+#define CONFIG_88F5182		1	/* SOC Name */
+
+#include <asm/arch/orion5x.h>
+/*
+ * CLKs configurations
+ */
+
+/*
+ * Board-specific values for Orion5x MPP low level init:
+ * - MPPs 12 to 15 are SATA LEDs (mode 5)
+ * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
+ *   MPP16 to MPP19, mode 0 for others
+ */
+
+#define ORION5X_MPP0_7		0x00000003
+#define ORION5X_MPP8_15		0x55550000
+#define ORION5X_MPP16_23	0x00005555
+
+/*
+ * Board-specific values for Orion5x GPIO low level init:
+ * - GPIO3 is input (RTC interrupt)
+ * - GPIO16 is Power LED control (0 = on, 1 = off)
+ * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
+ * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
+ * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
+ * - GPIO22 is SATA disk power status ()
+ * - GPIO23 is supply status for SATA disk ()
+ * - GPIO24 is supply control for board (write 1 to power off)
+ * Last GPIO is 25, further bits are supposed to be 0.
+ * Enable mask has ones for INPUT, 0 for OUTPUT.
+ * Default is LED ON, board ON :)
+ */
+
+#define ORION5X_GPIO_OUT_ENABLE		0xfef4f0ca
+#define ORION5X_GPIO_OUT_VALUE		0x00000000
+#define ORION5X_GPIO_IN_POLARITY	0x000000d0
+
+/*
+ * NS16550 Configuration
+ */
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		ORION5X_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
+
+/*
+ * FLASH configuration
+ */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1  /* max num of flash banks       */
+#define CONFIG_SYS_MAX_FLASH_SECT	11 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BASE		0xfff80000
+
+/* auto boot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
+
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+/*
+ * Commands configuration
+ */
+
+/*
+ * Network
+ */
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1}		/* enable port 0 only */
+#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION	/* don't randomize MAC */
+#define CONFIG_PHY_BASE_ADR	0x8
+#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#endif
+
+/*
+ * IDE
+ */
+#ifdef CONFIG_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+/* ED Mini V has an IDE-compatible SATA connector for port 1 */
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE		4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* A single bus, a single device */
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR	ORION5X_SATA_BASE
+/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	ORION5X_SATA_PORT1_OFFSET
+/* end of IDE defines */
+#endif /* CMD_IDE */
+
+/*
+ * Common USB/EHCI configuration
+ */
+#ifdef CONFIG_CMD_USB
+#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0		ORION5X_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+/*
+ *  Environment variables configurations
+ */
+#define CONFIG_ENV_SECT_SIZE		0x2000	/* 16K */
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x4000	/* env starts here */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 256) /* 256kB for malloc() */
+
+/*
+ * Other required minimal configurations
+ */
+
+#define CONFIG_SYS_LOAD_ADDR		0x00800000
+#define CONFIG_SYS_MEMTEST_START	0x00400000
+#define CONFIG_SYS_MEMTEST_END		0x007fffff
+#define CONFIG_SYS_RESET_ADDRESS	0xffff0000
+
+/* Enable command line editing */
+
+/* provide extensive help */
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_INIT_SP_ADDR	\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#endif /* _CONFIG_EDMINIV2_H */
diff --git a/include/configs/efi-x86_app.h b/include/configs/efi-x86_app.h
new file mode 100644
index 0000000..33418cf
--- /dev/null
+++ b/include/configs/efi-x86_app.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#undef CONFIG_TPM_TIS_BASE_ADDRESS
+
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
+					"stdout=vga,serial\0" \
+					"stderr=vga,serial\0"
+
+#endif
diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h
new file mode 100644
index 0000000..1cf5c03
--- /dev/null
+++ b/include/configs/efi-x86_payload.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd,usbkbd\0" \
+					"stdout=serial,vidconsole\0" \
+					"stderr=serial,vidconsole\0"
+
+/* ATA/IDE support */
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	4
+#define CONFIG_SYS_ATA_BASE_ADDR	0
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_ALT_OFFSET	0
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
+#define CONFIG_ATAPI
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h
new file mode 100644
index 0000000..fe28154
--- /dev/null
+++ b/include/configs/el6x_common.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * Configuration settings for the E+L i.MX6Q DO82 board.
+ */
+
+#ifndef __EL6Q_COMMON_CONFIG_H
+#define __EL6Q_COMMON_CONFIG_H
+
+#define CONFIG_BOARD_NAME		EL6Q
+
+#include "mx6_common.h"
+
+#define CONFIG_IMX_THERMAL
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_MXC_UART
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* I2C config */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED			100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+/* Commands */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+
+#define CONFIG_BOARD_NAME	EL6Q
+
+#define CONFIG_EXTRA_ENV_SETTINGS                                               \
+	"board="__stringify(CONFIG_BOARD_NAME)"\0"                              \
+	"cma_size="__stringify(EL6Q_CMA_SIZE)"\0"                               \
+	"chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0"                     \
+	"console=" CONSOLE_DEV "\0"					\
+	"fdtfile=undefined\0" \
+	"fdt_high=0xffffffff\0" \
+	"fdt_addr_r=0x18000000\0" \
+	"fdt_addr=0x18000000\0" \
+	"findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0"                  \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(PXE, PXE, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10800000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x0
+#endif
+
+#endif                         /* __EL6Q_COMMON_CONFIG_H */
diff --git a/include/configs/elgin_rv1108.h b/include/configs/elgin_rv1108.h
new file mode 100644
index 0000000..aa6c4b0
--- /dev/null
+++ b/include/configs/elgin_rv1108.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rv1108_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV	0
+
+#endif
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
new file mode 100644
index 0000000..8bc7a3a
--- /dev/null
+++ b/include/configs/embestmx6boards.h
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Eukréa Electromatique
+ * Author: Eric Bénard <eric@eukrea.com>
+ *
+ * Configuration settings for the Embest RIoTboard
+ *
+ * based on mx6*sabre*.h which are :
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __RIOTBOARD_CONFIG_H
+#define __RIOTBOARD_CONFIG_H
+
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+#define CONSOLE_DEV		"ttymxc1"
+
+#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
+
+#define CONFIG_IMX_THERMAL
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_MXC_UART
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* USB Configs */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		4
+
+#define CONFIG_PHY_ATHEROS
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+/* RiOTboard */
+#define CONFIG_FDTFILE	"imx6dl-riotboard.dtb"
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_MMC_ENV_DEV		2	/* SDHC4 */
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+/* MarSBoard */
+#define CONFIG_FDTFILE	"imx6q-marsboard.dtb"
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(8 * 1024)
+#endif
+
+/* Framebuffer */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+#include "mx6_common.h"
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+/* RiOTboard */
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6dl-riotboard.dtb"
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0 /* offset 69KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0 /* offset 69KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* offset 69KB */
+
+#endif
+
+/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe and the ramdisk at the end */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x12000000\0" \
+	"fdt_addr_r=0x13000000\0" \
+	"scriptaddr=0x13100000\0" \
+	"pxefile_addr_r=0x13200000\0" \
+	"ramdisk_addr_r=0x13300000\0"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONSOLE_STDIN_SETTINGS \
+	"stdin=serial\0"
+
+#define CONSOLE_STDOUT_SETTINGS \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+
+#define CONSOLE_ENV_SETTINGS \
+	CONSOLE_STDIN_SETTINGS \
+	CONSOLE_STDOUT_SETTINGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONSOLE_ENV_SETTINGS \
+	MEM_LAYOUT_ENV_SETTINGS \
+	"fdtfile=" CONFIG_FDTFILE "\0" \
+	"finduuid=part uuid mmc 0:1 uuid\0" \
+	BOOTENV
+
+#endif                         /* __RIOTBOARD_CONFIG_H */
diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h
new file mode 100644
index 0000000..a872d48
--- /dev/null
+++ b/include/configs/emsdp.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef _CONFIG_EMSDP_H_
+#define _CONFIG_EMSDP_H_
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_SDRAM_BASE		0x10000000
+#define CONFIG_SYS_SDRAM_SIZE		SZ_16M
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_1M)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_64K
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+/*
+ * Environment
+ */
+#define CONFIG_BOOTFILE			"app.bin"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"upgrade_image=u-boot.bin\0" \
+	"upgrade=emsdp rom unlock && " \
+		"fatload mmc 0 ${loadaddr} ${upgrade_image} && " \
+		"cp.b ${loadaddr} 0 ${filesize} && " \
+		"dcache flush && " \
+		"emsdp rom lock\0"
+
+#endif /* _CONFIG_EMSDP_H_ */
+
diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h
new file mode 100644
index 0000000..5aeb009
--- /dev/null
+++ b/include/configs/espresso7420.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the SAMSUNG ESPRESSO7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ */
+
+#ifndef __CONFIG_ESPRESSO7420_H
+#define __CONFIG_ESPRESSO7420_H
+
+#include <configs/exynos7420-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_ESPRESSO7420
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SPL_STACK		CONFIG_IRAM_END
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_IRAM_END
+
+/* select serial console configuration */
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+/* DRAM Memory Banks */
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+
+#endif	/* __CONFIG_ESPRESSO7420_H */
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
new file mode 100644
index 0000000..726f8a5
--- /dev/null
+++ b/include/configs/etamin.h
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef __CONFIG_ETAMIN_H
+#define __CONFIG_ETAMIN_H
+
+#include "siemens-am33x-common.h"
+/* NAND specific changes for etamin due to different page size */
+#undef CONFIG_SYS_NAND_PAGE_SIZE
+#undef CONFIG_SYS_NAND_OOBSIZE
+#undef CONFIG_SYS_NAND_BLOCK_SIZE
+#undef CONFIG_SYS_NAND_ECCPOS
+#undef CONFIG_SYS_NAND_U_BOOT_OFFS
+#undef CONFIG_SYS_ENV_SECT_SIZE
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_NAND_OMAP_ECCSCHEME
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH16_CODE_HW
+
+#define CONFIG_ENV_OFFSET       0x980000
+#define CONFIG_SYS_ENV_SECT_SIZE       (512 << 10)     /* 512 KiB */
+#define CONFIG_SYS_NAND_PAGE_SIZE       4096
+#define CONFIG_SYS_NAND_OOBSIZE         224
+#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
+				10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+				20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
+				30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
+				50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+				60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
+				70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+				80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
+				90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
+			100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+			110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
+			120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
+			130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
+			140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
+			150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
+			160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
+			170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
+			180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
+			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
+			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
+			}
+
+#undef CONFIG_SYS_NAND_ECCSIZE
+#undef CONFIG_SYS_NAND_ECCBYTES
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 26
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x200000
+
+#define CONFIG_SYS_NAND_MAX_CHIPS       1
+
+#undef CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_MAX_NAND_DEVICE      3
+#define CONFIG_SYS_NAND_BASE2           (0x18000000)    /* physical address */
+#define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
+					CONFIG_SYS_NAND_BASE2}
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define DDR_PLL_FREQ	303
+
+/* FWD Button = 27
+ * SRV Button = 87 */
+#define BOARD_DFU_BUTTON_GPIO	27
+#define GPIO_LAN9303_NRST	88	/* GPIO2_24 = gpio88 */
+/* In dfu mode keep led1 on */
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	"button_dfu0=27\0" \
+	"button_dfu1=87\0" \
+	"led0=3,0,1\0" \
+	"led1=4,0,0\0" \
+	"led2=5,0,1\0" \
+	"led3=87,0,1\0" \
+	"led4=60,0,1\0" \
+	"led5=63,0,1\0"
+
+/* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE       (1024 << 20)    /* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* use both define to compile a SPL compliance test  */
+/*
+#define CONFIG_SPL_CMT
+#define CONFIG_SPL_CMT_DEBUG
+*/
+
+/* nedded by compliance test in read mode */
+#if defined(CONFIG_SPL_CMT)
+#define CONFIG_SYS_DCACHE_OFF
+#endif
+
+/* Define own nand partitions */
+#define CONFIG_ENV_OFFSET_REDUND	0xB80000
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_RANGE		(4 * CONFIG_SYS_ENV_SECT_SIZE)
+
+
+
+#undef COMMON_ENV_DFU_ARGS
+#define COMMON_ENV_DFU_ARGS	"dfu_args=run bootargs_defaults;" \
+				"setenv bootargs ${bootargs};" \
+				"mtdparts default;" \
+				"draco_led 1;" \
+				"dfu 0 mtd 0;" \
+				"draco_led 0;\0" \
+
+#undef DFU_ALT_INFO_NAND_V2
+#define DFU_ALT_INFO_NAND_V2 \
+	"spl mtddev;" \
+	"spl.backup1 mtddev;" \
+	"spl.backup2 mtddev;" \
+	"spl.backup3 mtddev;" \
+	"u-boot mtddev;" \
+	"u-boot.env0 mtddev;" \
+	"u-boot.env1 mtddev;" \
+	"rootfs mtddevubi" \
+
+#undef CONFIG_ENV_SETTINGS_NAND_V2
+#define CONFIG_ENV_SETTINGS_NAND_V2 \
+	"nand_active_ubi_vol=rootfs_a\0" \
+	"rootfs_name=rootfs\0" \
+	"kernel_name=uImage\0"\
+	"nand_root_fs_type=ubifs rootwait=1\0" \
+	"nand_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv ${partitionset_active} true;" \
+		"if test -n ${A}; then " \
+			"setenv nand_active_ubi_vol ${rootfs_name}_a;" \
+		"fi;" \
+		"if test -n ${B}; then " \
+			"setenv nand_active_ubi_vol ${rootfs_name}_b;" \
+		"fi;" \
+		"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
+		"ubi.mtd=rootfs,${ubi_off};" \
+		"setenv bootargs ${bootargs} " \
+		"root=${nand_root} noinitrd ${mtdparts} " \
+		"rootfstype=${nand_root_fs_type} ip=${ip_method} " \
+		"console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
+		"=mtdoops\0" \
+	COMMON_ENV_DFU_ARGS \
+		"dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \
+	COMMON_ENV_NAND_BOOT \
+		"ubi part rootfs ${ubi_off};" \
+		"ubifsmount ubi0:${nand_active_ubi_vol};" \
+		"ubifsload ${kloadaddr} boot/${kernel_name};" \
+		"ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \
+		"bootm ${kloadaddr} - ${loadaddr}\0" \
+	"nand_boot_backup=ubifsload ${loadaddr} boot/am335x-draco.dtb;" \
+		"bootm ${kloadaddr} - ${loadaddr}\0" \
+	COMMON_ENV_NAND_CMDS
+
+#ifndef CONFIG_SPL_BUILD
+
+#define CONFIG_NAND_CS_INIT
+#define ETAMIN_NAND_GPMC_CONFIG1	0x00000800
+#define ETAMIN_NAND_GPMC_CONFIG2	0x001e1e00
+#define ETAMIN_NAND_GPMC_CONFIG3	0x001e1e00
+#define ETAMIN_NAND_GPMC_CONFIG4	0x16051807
+#define ETAMIN_NAND_GPMC_CONFIG5	0x00151e1e
+#define ETAMIN_NAND_GPMC_CONFIG6	0x16000f80
+#define CONFIG_MTD_CONCAT
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=etamin\0" \
+	"ubi_off=4096\0"\
+	"nand_img_size=0x400000\0" \
+	"optargs=\0" \
+	"preboot=draco_led 0\0" \
+	CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	CONFIG_ENV_SETTINGS_V2 \
+	CONFIG_ENV_SETTINGS_NAND_V2
+
+#ifndef CONFIG_RESTORE_FLASH
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+	"run dfu_start; " \
+	"reset; " \
+"fi;" \
+"run nand_boot;" \
+"run nand_boot_backup;" \
+"reset;"
+
+
+#else
+#define CONFIG_BOOTCOMMAND			\
+	"setenv autoload no; "			\
+	"dhcp; "				\
+	"if tftp 80000000 debrick.scr; then "	\
+		"source 80000000; "		\
+	"fi"
+#endif
+#endif	/* CONFIG_SPL_BUILD */
+#endif	/* ! __CONFIG_ETAMIN_H */
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
new file mode 100644
index 0000000..c9e7c8c
--- /dev/null
+++ b/include/configs/ethernut5.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * egnite GmbH <info@egnite.de>
+ *
+ * Configuation settings for Ethernut 5 with AT91SAM9XE.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+/* The first stage boot loader expects u-boot running at this address. */
+
+/* The first stage boot loader takes care of low level initialization. */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Set our official architecture number. */
+#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
+
+/* CPU information */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* 18.432 MHz crystal */
+
+/* 32kB internal SRAM */
+#define CONFIG_SRAM_BASE	0x00300000 /*AT91SAM9XE_SRAM_BASE */
+#define CONFIG_SRAM_SIZE	(32 << 10)
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
+				GENERATED_GBL_DATA_SIZE)
+
+/* 128MB SDRAM in 1 bank */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		(128 << 20)
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE \
+					- CONFIG_SYS_MALLOC_LEN)
+
+/* 512kB on-chip NOR flash */
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_FLASH_BASE		0x00200000 /* AT91SAM9XE_FLASH_BASE */
+# define CONFIG_AT91_EFLASH
+# define CONFIG_SYS_MAX_FLASH_SECT	32
+# define CONFIG_EFLASH_PROTSECTORS	1
+
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_OFFSET	0x3DE000
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
+#endif
+
+/* JFFS2 */
+#ifdef CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_NAND
+#endif
+
+/* Ethernet */
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_PHY_ID			0
+#define CONFIG_MACB_SEARCH_PHY
+
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_SYS_MMC_CD_PIN		AT91_PIO_PORTC, 8
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"host"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#endif
+
+/* RTC */
+#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+#endif
+
+/* I2C */
+#define CONFIG_SYS_MAX_I2C_BUS	1
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0
+
+#define I2C_SOFT_DECLARATIONS
+
+#define GPIO_I2C_SCL		AT91_PIO_PORTA, 24
+#define GPIO_I2C_SDA		AT91_PIO_PORTA, 23
+
+#define I2C_INIT { \
+	at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
+	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
+	at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
+	at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
+	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
+}
+
+#define I2C_ACTIVE	at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
+#define I2C_TRISTATE	at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
+#define I2C_SCL(bit)	at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
+#define I2C_SDA(bit)	at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
+#define I2C_DELAY	udelay(100)
+#define I2C_READ	at91_get_pio_value(AT91_PIO_PORTA, 23)
+
+/* DHCP/BOOTP options */
+#ifdef CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_SYS_AUTOLOAD	"n"
+#endif
+
+/* File systems */
+
+/* Boot command */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_BOOTCOMMAND	"sf probe 0:0; " \
+				"sf read 0x22000000 0xc6000 0x294000; " \
+				"bootm 0x22000000"
+
+/* Misc. u-boot settings */
+
+#endif
diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h
new file mode 100644
index 0000000..e4b07e3
--- /dev/null
+++ b/include/configs/evb_ast2500.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012-2020  ASPEED Technology Inc.
+ * Ryan Chen <ryan_chen@aspeedtech.com>
+ *
+ * Copyright 2016 Google Inc
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/aspeed-common.h>
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x300000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x5000000)
+
+#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
+
+/* Memory Info */
+#define CONFIG_SYS_LOAD_ADDR		0x83000000
+
+#define CONFIG_ENV_SIZE			0x20000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/evb_px5.h b/include/configs/evb_px5.h
new file mode 100644
index 0000000..e930420
--- /dev/null
+++ b/include/configs/evb_px5.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIGS_PX5_EVB_H
+#define __CONFIGS_PX5_EVB_H
+
+#include <configs/rk3368_common.h>
+
+#define CONFIG_CONSOLE_SCROLL_LINES	10
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/evb_rk3036.h b/include/configs/evb_rk3036.h
new file mode 100644
index 0000000..b03612c
--- /dev/null
+++ b/include/configs/evb_rk3036.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rk3036_common.h>
+
+#endif
diff --git a/include/configs/evb_rk3128.h b/include/configs/evb_rk3128.h
new file mode 100644
index 0000000..73ceab0
--- /dev/null
+++ b/include/configs/evb_rk3128.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __EVB_RK3128_H
+#define __EVB_RK3128_H
+
+#include <configs/rk3128_common.h>
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/evb_rk3229.h b/include/configs/evb_rk3229.h
new file mode 100644
index 0000000..6a91a82
--- /dev/null
+++ b/include/configs/evb_rk3229.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rk322x_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/evb_rk3288.h b/include/configs/evb_rk3288.h
new file mode 100644
index 0000000..ddd7012
--- /dev/null
+++ b/include/configs/evb_rk3288.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3288_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h
new file mode 100644
index 0000000..ed5888b
--- /dev/null
+++ b/include/configs/evb_rk3328.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __EVB_RK3328_H
+#define __EVB_RK3328_H
+
+#include <configs/rk3328_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 1
+
+#define SDRAM_BANK_SIZE			(2UL << 30)
+
+#define CONFIG_CONSOLE_SCROLL_LINES		10
+
+#endif
diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
new file mode 100644
index 0000000..b9c4d68
--- /dev/null
+++ b/include/configs/evb_rk3399.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __EVB_RK3399_H
+#define __EVB_RK3399_H
+
+#include <configs/rk3399_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define SDRAM_BANK_SIZE			(2UL << 30)
+
+#endif
diff --git a/include/configs/evb_rv1108.h b/include/configs/evb_rv1108.h
new file mode 100644
index 0000000..b742d98
--- /dev/null
+++ b/include/configs/evb_rv1108.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rv1108_common.h>
+
+/*
+ * Default environment settings
+ */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS                                       \
+	"netdev=eth0\0"                                                 \
+	"ipaddr=172.16.12.50\0"                                         \
+	"serverip=172.16.12.69\0"					\
+	""
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND						\
+	"sf probe;"							\
+	"sf read 0x62000000 0x140800 0x500000;"				\
+	"dcache off;"							\
+	"go 0x62000000"
+
+#endif
diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
new file mode 100644
index 0000000..5ae2b42
--- /dev/null
+++ b/include/configs/exynos-common.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Common configuration settings for the SAMSUNG EXYNOS boards.
+ */
+
+#ifndef __EXYNOS_COMMON_H
+#define __EXYNOS_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_S5P			/* S5P Family */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <linux/sizes.h>
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Keep L2 Cache Disabled */
+
+/* input clock of PLL: 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+#define COUNTER_FREQUENCY		CONFIG_SYS_CLK_FREQ
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_ENV_OVERWRITE
+
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
+
+/* select serial console configuration */
+
+/* PWM */
+#define CONFIG_PWM
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		1024	/* Print Buffer Size */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
new file mode 100644
index 0000000..005f65d
--- /dev/null
+++ b/include/configs/exynos4-common.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ */
+
+#ifndef __CONFIG_EXYNOS4_COMMON_H
+#define __CONFIG_EXYNOS4_COMMON_H
+
+#define CONFIG_EXYNOS4			/* Exynos4 Family */
+
+#include "exynos-common.h"
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_REVISION_TAG
+
+/* SD/MMC configuration */
+#define CONFIG_MMC_DEFAULT_DEV	0
+
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
+#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_USB_GADGET_DWC2_OTG_PHY
+
+/* Common environment variables */
+#define CONFIG_EXTRA_ENV_ITB \
+	"loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \
+		"${kernelname}\0" \
+	"loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \
+		"${initrdname}\0" \
+	"loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \
+		"${fdtfile}\0" \
+	"check_ramdisk=" \
+		"if run loadinitrd; then " \
+			"setenv initrd_addr ${initrdaddr};" \
+		"else " \
+			"setenv initrd_addr -;" \
+		"fi;\0" \
+	"check_dtb=" \
+		"if run loaddtb; then " \
+			"setenv fdt_addr ${fdtaddr};" \
+		"else " \
+			"setenv fdt_addr;" \
+		"fi;\0" \
+	"kernel_args=" \
+		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart}" \
+		" ${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};\0" \
+	"boot_fit=" \
+		"setenv kerneladdr 0x42000000;" \
+		"setenv kernelname Image.itb;" \
+		"run loadkernel;" \
+		"run kernel_args;" \
+		"bootm ${kerneladdr}#${board_name}\0" \
+	"boot_uimg=" \
+		"setenv kerneladdr 0x40007FC0;" \
+		"setenv kernelname uImage;" \
+		"run check_dtb;" \
+		"run check_ramdisk;" \
+		"run loadkernel;" \
+		"run kernel_args;" \
+		"bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
+	"boot_zimg=" \
+		"setenv kerneladdr 0x40007FC0;" \
+		"setenv kernelname zImage;" \
+		"run check_dtb;" \
+		"run check_ramdisk;" \
+		"run loadkernel;" \
+		"run kernel_args;" \
+		"bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
+	"autoboot=" \
+		"if test -e mmc ${mmcdev}:${mmcbootpart} Image.itb; then; " \
+			"run boot_fit;" \
+		"elif test -e mmc ${mmcdev}:${mmcbootpart} zImage; then; " \
+			"run boot_zimg;" \
+		"elif test -e mmc ${mmcdev}:${mmcbootpart} uImage; then; " \
+			"run boot_uimg;" \
+		"fi;\0"
+
+#endif	/* __CONFIG_EXYNOS4_COMMON_H */
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
new file mode 100644
index 0000000..e0a4d76
--- /dev/null
+++ b/include/configs/exynos5-common.h
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ */
+
+#ifndef __CONFIG_EXYNOS5_COMMON_H
+#define __CONFIG_EXYNOS5_COMMON_H
+
+#define CONFIG_EXYNOS5			/* Exynos5 Family */
+
+#include "exynos-common.h"
+
+#define CONFIG_EXYNOS_SPL
+
+#ifdef FTRACE
+#define CONFIG_TRACE
+#define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
+#define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR		0x50000000
+#endif
+
+/* Enable ACE acceleration for SHA1 and SHA256 */
+#define CONFIG_EXYNOS_ACE_SHA
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET			0x800
+#define INFORM1_OFFSET			0x804
+#define INFORM2_OFFSET			0x808
+#define INFORM3_OFFSET			0x80c
+
+/* select serial console configuration */
+#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
+
+/* Thermal Management Unit */
+#define CONFIG_EXYNOS_TMU
+
+/* MMC SPL */
+#define COPY_BL2_FNPTR_ADDR	0x02020030
+
+/* specific .lds file */
+
+/* Boot Argument Buffer Size */
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_RD_LVL
+
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
+#else
+#define CONFIG_SEC_FW_SIZE 0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE	(512)
+#define CONFIG_BL1_SIZE	(16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_BL2_SIZE	(512UL << 10UL) /* 512 KB */
+#define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
+
+#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+
+/* U-Boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
+
+#define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
+#define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
+
+/* I2C */
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
+
+/* SPI */
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#endif
+
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_ENV_SROM_BANK		1
+#endif /*CONFIG_CMD_NET*/
+
+/* Enable Time Command */
+
+/* USB */
+
+/* USB boot mode */
+#define CONFIG_USB_BOOTING
+#define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
+#define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
+#define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 2) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+/* 2GB RAM, bootm size of 256M, load scripts after that */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x42000000\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"ramdisk_addr_r=0x43300000\0" \
+	"scriptaddr=0x50000000\0" \
+	"pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS \
+	EXYNOS_FDTFILE_SETTING \
+	MEM_LAYOUT_ENV_SETTINGS \
+	BOOTENV
+
+#endif	/* __CONFIG_EXYNOS5_COMMON_H */
diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h
new file mode 100644
index 0000000..a87182a
--- /dev/null
+++ b/include/configs/exynos5-dt-common.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * Configuration settings for generic Exynos 5 board
+ */
+
+#ifndef __CONFIG_EXYNOS5_DT_COMMON_H
+#define __CONFIG_EXYNOS5_DT_COMMON_H
+
+/* Console configuration */
+#undef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+		"stdin=serial,cros-ec-keyb\0" \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#define CONFIG_EXYNOS5_DT
+
+#define CONFIG_SYS_SPI_BASE	0x12D30000
+#define FLASH_SIZE		(4 << 20)
+#define CONFIG_ENV_OFFSET	(FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_SPI_BOOTING
+
+#define CONFIG_BOARD_COMMON
+
+/* Display */
+#ifdef CONFIG_LCD
+#define CONFIG_EXYNOS_FB
+#define CONFIG_EXYNOS_DP
+#define LCD_BPP			LCD_COLOR16
+#endif
+
+/* Enable keyboard */
+#define CONFIG_KEYBOARD
+
+#endif
diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h
new file mode 100644
index 0000000..65da381
--- /dev/null
+++ b/include/configs/exynos5250-common.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5250 board.
+ */
+
+#ifndef __CONFIG_5250_H
+#define __CONFIG_5250_H
+
+#define CONFIG_EXYNOS5250
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5250
+
+#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
+
+#define CONFIG_IRAM_STACK	0x02050000
+
+#define CONFIG_SYS_INIT_SP_ADDR	CONFIG_IRAM_STACK
+
+/* USB */
+#define CONFIG_USB_EHCI_EXYNOS
+
+#define CONFIG_USB_XHCI_EXYNOS
+
+/* DRAM Memory Banks */
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+
+#endif  /* __CONFIG_5250_H */
diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h
new file mode 100644
index 0000000..2d362f3
--- /dev/null
+++ b/include/configs/exynos5420-common.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5420 SoC
+ */
+
+#ifndef __CONFIG_EXYNOS5420_H
+#define __CONFIG_EXYNOS5420_H
+
+#define CONFIG_EXYNOS5420
+
+#define CONFIG_EXYNOS5_DT
+
+/* Provide the MACH_TYPE value that the vendor kernel requires. */
+#define CONFIG_MACH_TYPE		8002
+
+#define CONFIG_VAR_SIZE_SPL
+
+#define CONFIG_IRAM_TOP			0x02074000
+
+#define CONFIG_SPL_MAX_FOOTPRINT	(30 * 1024)
+
+#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi"	\
+				"exynos5420-peach-pit exynos5420-smdk5420"
+
+#define CONFIG_PHY_IRAM_BASE		0x02020000
+
+/* Address for relocating helper code (Last 4 KB of IRAM) */
+#define CONFIG_EXYNOS_RELOCATE_CODE_BASE	(CONFIG_IRAM_TOP - 0x1000)
+
+/*
+ * Low Power settings
+ */
+#define CONFIG_LOWPOWER_FLAG		0x02020028
+#define CONFIG_LOWPOWER_ADDR		0x0202002C
+
+#define CONFIG_USB_XHCI_EXYNOS
+
+#endif	/* __CONFIG_EXYNOS5420_H */
diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
new file mode 100644
index 0000000..157260c
--- /dev/null
+++ b/include/configs/exynos7420-common.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Espresso7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ */
+
+#ifndef __CONFIG_EXYNOS7420_COMMON_H
+#define __CONFIG_EXYNOS7420_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_EXYNOS7420		/* Exynos7 Family */
+#define CONFIG_S5P
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <linux/sizes.h>
+
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		1024	/* Print Buffer Size */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* select serial console configuration */
+
+/* Timer input clock frequency */
+#define COUNTER_FREQUENCY		24000000
+
+/* Device Tree */
+#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
+
+/* IRAM Layout */
+#define CONFIG_IRAM_BASE		0x02100000
+#define CONFIG_IRAM_SIZE		0x58000
+#define CONFIG_IRAM_END			(CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
+#define CPU_RELEASE_ADDR		secondary_boot_addr
+
+/* select serial console configuration */
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
+
+/* Configuration of ENV Blocks */
+#define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x42000000\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"ramdisk_addr_r=0x43300000\0" \
+	"scriptaddr=0x50000000\0" \
+	"pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS \
+	EXYNOS_FDTFILE_SETTING \
+	MEM_LAYOUT_ENV_SETTINGS
+
+#endif	/* __CONFIG_EXYNOS7420_COMMON_H */
diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h
new file mode 100644
index 0000000..9e4a669
--- /dev/null
+++ b/include/configs/firefly-rk3288.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdin=serial,usbkbd\0" \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3288_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
new file mode 100644
index 0000000..4cd823f
--- /dev/null
+++ b/include/configs/flea3.h
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the flea3 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_MX35
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_FLEA3
+
+/* Set TEXT at the beginning of the NOR flash */
+
+/* This is required to setup the ESDC controller */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_SPD_BUS_NUM		2 /* I2C3 */
+#define CONFIG_SYS_MXC_I2C3_SLAVE	0xfe
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART3_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command definition
+ */
+
+#define CONFIG_NET_RETRY_COUNT	100
+
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_CBSIZE	512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
+
+#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE		(IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * CFI FLASH driver setup
+ */
+
+/* A non-standard buffered write algorithm */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+
+#define CONFIG_HOSTNAME "flea3"
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"				\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc2,${baudrate}\0"			\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"loadaddr=80800000\0"						\
+	"kernel_addr_r=80800000\0"					\
+	"hostname=" CONFIG_HOSTNAME "\0"			\
+	"bootfile=" CONFIG_HOSTNAME "/uImage\0"		\
+	"ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0"	\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
+	"net_self=if run net_self_load;then "				\
+		"run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
+		"else echo Images not loades;fi\0"			\
+	"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"		\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
+	"update=protect off ${uboot_addr} +80000;"			\
+		"erase ${uboot_addr} +80000;"				\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+	"bootcmd=run net_nfs\0"
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/galileo.h b/include/configs/galileo.h
new file mode 100644
index 0000000..507d08c
--- /dev/null
+++ b/include/configs/galileo.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+
+/* ns16550 UART is memory-mapped in Quark SoC */
+#undef  CONFIG_SYS_NS16550_PORT_MAPPED
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial\0" \
+					"stdout=serial\0" \
+					"stderr=serial\0"
+
+/* 10/100M Ethernet support */
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_ALTDESCRIPTOR
+
+/* Environment configuration */
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h
new file mode 100644
index 0000000..482e471
--- /dev/null
+++ b/include/configs/gardena-smart-gateway-at91sam.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ * Copyright (C) 2019 Stefan Roese <sr@denx.de>
+ *
+ * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25)
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 megs */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		(16 * 1024 * 1024)
+
+/* NAND flash */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE		0x7000
+#define CONFIG_SPL_STACK		0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0xa0000
+#define	CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+
+#define CONFIG_SPL_PAD_TO		CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_SPL_LEN		CONFIG_SPL_PAD_TO
+
+#endif
diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h
new file mode 100644
index 0000000..e83a96a
--- /dev/null
+++ b/include/configs/gardena-smart-gateway-mt7688.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H
+#define __CONFIG_GARDENA_SMART_GATEWAY_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	290000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+#ifdef CONFIG_BOOT_RAM
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 460800, 921600 }
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80400000
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_MALLOC_LEN		(16 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+#define CONFIG_SYS_CBSIZE		512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+/* Environment settings */
+#define CONFIG_ENV_OFFSET		0xa0000
+#define CONFIG_ENV_SIZE			(64 << 10)
+#define CONFIG_ENV_SECT_SIZE		(64 << 10)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+/*
+ * Environment is right behind U-Boot in flash. Make sure U-Boot
+ * doesn't grow into the environment area.
+ */
+#define CONFIG_BOARD_SIZE_LIMIT		CONFIG_ENV_OFFSET
+
+#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */
diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h
new file mode 100644
index 0000000..0ff4828
--- /dev/null
+++ b/include/configs/gazerbeam.h
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_SDRAM_BASE
+
+/*
+ * Memory test
+ * TODO: Migrate!
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x07e00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
+
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+/* TODO: Turn into string option and migrate to Kconfig */
+#define CONFIG_HOSTNAME		"gazerbeam"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS1\0"						\
+	"u-boot=u-boot.bin\0"						\
+	"kernel_addr=1000000\0"					\
+	"fdt_addr=C00000\0"						\
+	"fdtfile=hrcon.dtb\0"				\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+		" +${filesize};cp.b ${fileaddr} "			\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
+	"upd=run load update\0"						\
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp ${kernel_addr} $bootfile;"				\
+	"tftp ${fdt_addr} $fdtfile;"					\
+	"bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_MMCBOOTCOMMAND						\
+	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait "		\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"ext2load mmc 0:2 ${kernel_addr} $bootfile;"			\
+	"ext2load mmc 0:2 ${fdt_addr} $fdtfile;"			\
+	"bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_MMCBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
new file mode 100644
index 0000000..6de5119
--- /dev/null
+++ b/include/configs/ge_bx50v3.h
@@ -0,0 +1,237 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Timesys Corporation
+ * Copyright (C) 2015 General Electric Company
+ * Copyright (C) 2014 Advantech
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the GE MX6Q Bx50v3 boards.
+ */
+
+#ifndef __GE_BX50V3_CONFIG_H
+#define __GE_BX50V3_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/mach-imx/gpio.h>
+
+#define CONFIG_BOARD_NAME	"General Electric Bx50v3"
+
+#define CONFIG_MXC_UART_BASE	UART3_BASE
+#define CONSOLE_DEV	"ttymxc2"
+
+#include "mx6_common.h"
+#include <linux/sizes.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_MXC_UART
+
+/* SATA Configs */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#endif
+
+/* USB Configs */
+#ifdef CONFIG_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#endif
+
+/* Networking Configs */
+#ifdef CONFIG_NET
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME		"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		4
+#define CONFIG_PHY_ATHEROS
+#endif
+
+/* Serial Flash */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_LOADADDR	0x12000000
+
+#ifdef CONFIG_NFS_CMD
+#define NETWORKBOOT \
+        "setnetworkboot=" \
+                "setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \
+                "setenv gatewayip 172.16.2.20; setenv nfsserver 172.16.2.20; " \
+                "setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \
+                "setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \
+                "setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \
+                "setenv bootargs $bootargs cma=128M bootcause=POR console=${console} ${videoargs} " \
+                "setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \
+                "setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \
+        "networkboot=" \
+                "run setnetworkboot; " \
+                "nfs ${loadaddr} /srv/nfs/fitImage; " \
+                "bootm ${loadaddr}#conf@${confidx}\0" \
+
+#define CONFIG_NETWORKBOOTCOMMAND \
+	"run networkboot; " \
+
+#else
+#define NETWORKBOOT \
+
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	NETWORKBOOT \
+	"bootcause=POR\0" \
+	"image=/boot/fitImage\0" \
+	"fdt_high=0xffffffff\0" \
+	"dev=mmc\0" \
+	"devnum=2\0" \
+	"rootdev=mmcblk0p\0" \
+	"quiet=quiet loglevel=0\0" \
+	"console=" CONSOLE_DEV "\0" \
+	"setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \
+		"ro rootwait cma=128M " \
+		"bootcause=${bootcause} " \
+		"${quiet} console=${console} ${rtc_status} " \
+		"${videoargs}" "\0" \
+	"doquiet=" \
+		"if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
+			"then setenv quiet; fi\0" \
+	"hasfirstboot=" \
+		"ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
+		"/boot/bootcause/firstboot\0" \
+	"swappartitions=" \
+		"setexpr partnum 3 - ${partnum}\0" \
+	"failbootcmd=" \
+		"bx50_backlight_enable; " \
+		"msg=\"Monitor failed to start.  Try again, or contact GE Service for support.\"; " \
+		"echo $msg; " \
+		"setenv stdout vga; " \
+		"echo \"\n\n\n\n    \" $msg; " \
+		"setenv stdout serial; " \
+		"mw.b 0x7000A000 0xbc; " \
+		"mw.b 0x7000A001 0x00; " \
+		"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
+	"altbootcmd=" \
+		"run doquiet; " \
+		"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
+		"run hasfirstboot || setenv partnum 0; " \
+		"if test ${partnum} != 0; then " \
+			"setenv bootcause REVERT; " \
+			"run swappartitions loadimage doboot; " \
+		"fi; " \
+		"run failbootcmd\0" \
+	"loadimage=" \
+		"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
+	"doboot=" \
+		"echo Booting from ${dev}:${devnum}:${partnum} ...; " \
+		"run setargs; " \
+		"bootm ${loadaddr}#conf@${confidx}\0" \
+	"tryboot=" \
+		"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
+		"run loadimage || run swappartitions && run loadimage || " \
+		"setenv partnum 0 && echo MISSING IMAGE;" \
+		"run doboot; " \
+		"run failbootcmd\0" \
+
+#define CONFIG_MMCBOOTCOMMAND \
+	"if mmc dev ${devnum}; then " \
+		"run doquiet; " \
+		"run tryboot; " \
+	"fi; " \
+
+#define CONFIG_USBBOOTCOMMAND \
+	"echo Unsupported; " \
+
+#ifdef CONFIG_NFS_CMD
+#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND
+#elif CONFIG_CMD_USB
+#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
+#else
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+#endif
+
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_SIZE		(8 * 1024)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+
+/* Framebuffer */
+#define CONFIG_HIDE_LOGO_VERSION
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_CMD_BMP
+
+#define CONFIG_IMX6_PWM_PER_CLK	66000000
+
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(1, 5)
+
+#define CONFIG_RTC_RX8010SJ
+#define CONFIG_SYS_RTC_BUS_NUM 2
+#define CONFIG_SYS_I2C_RTC_ADDR	0x32
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		  100000
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_MXC_I2C2
+#define CONFIG_SYS_I2C_MXC_I2C3
+
+#define CONFIG_SYS_NUM_I2C_BUSES        11
+#define CONFIG_SYS_I2C_MAX_HOPS         1
+#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+					{1, {I2C_NULL_HOP} }, \
+					{2, {I2C_NULL_HOP} }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
+				}
+
+#define CONFIG_BCH
+
+#endif	/* __GE_BX50V3_CONFIG_H */
diff --git a/include/configs/geekbox.h b/include/configs/geekbox.h
new file mode 100644
index 0000000..91f4feb
--- /dev/null
+++ b/include/configs/geekbox.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Andreas Färber
+ */
+
+#ifndef __CONFIGS_GEEKBOX_H
+#define __CONFIGS_GEEKBOX_H
+
+#include <configs/rk3368_common.h>
+
+#define CONFIG_CONSOLE_SCROLL_LINES		10
+
+#endif
diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h
new file mode 100644
index 0000000..1d69a4e
--- /dev/null
+++ b/include/configs/goflexhome.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+ *
+ * Based on dockstar.h originally written by
+ * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.h originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#ifndef _CONFIG_GOFLEXHOME_H
+#define _CONFIG_GOFLEXHOME_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Default GPIO configuration and LED status
+ */
+#define GOFLEXHOME_OE_LOW               (~(0))
+#define GOFLEXHOME_OE_HIGH              (~(0))
+#define GOFLEXHOME_OE_VAL_LOW           (1 << 29)       /* USB_PWEN low */
+#define GOFLEXHOME_OE_VAL_HIGH          (1 << 17)       /* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG         10
+#define MV88E1116_CPRSP_CR3_REG         21
+#define MV88E1116_MAC_CTRL_REG          21
+#define MV88E1116_PGADR_REG             22
+#define MV88E1116_RGMII_TXTM_CTRL       (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL       (1 << 5)
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0xC0000
+#define CONFIG_ENV_OFFSET		0xC0000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+	"ubi part root; " \
+	"ubifsmount ubi:root; " \
+	"ubifsload 0x800000 ${kernel}; " \
+	"bootm 0x800000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=console=ttyS0,115200\0" \
+	"mtdids=nand0=orion_nand\0" \
+	"mtdparts="CONFIG_MTDPARTS_DEFAULT \
+	"kernel=/boot/uImage\0" \
+	"bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ *  * SATA Driver configuration
+ *   */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#endif /* _CONFIG_GOFLEXHOME_H */
diff --git a/include/configs/gose.h b/include/configs/gose.h
new file mode 100644
index 0000000..fcb9f17
--- /dev/null
+++ b/include/configs/gose.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/configs/gose.h
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ */
+
+#ifndef __GOSE_H
+#define __GOSE_H
+
+#include "rcar-gen2-common.h"
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
+#define STACK_AREA_SIZE			0x00100000
+#define LOW_LEVEL_MERAM_STACK \
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE		0x40000000
+#define RCAR_GEN2_SDRAM_SIZE		(1048u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512u * 1024 * 1024)
+
+/* SH Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK	20000000u
+#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootm_size=0x10000000\0"
+
+/* SPL support */
+#define CONFIG_SPL_STACK		0xe6340000
+#define CONFIG_SPL_MAX_SIZE		0x4000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ		65000000
+#endif
+
+#endif	/* __GOSE_H */
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
new file mode 100644
index 0000000..7da8739
--- /dev/null
+++ b/include/configs/gplugd.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <contact@8051projects.net>
+ *
+ * Based on Aspenite:
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ */
+
+#ifndef __CONFIG_GPLUGD_H
+#define __CONFIG_GPLUGD_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV331xV5	1	/* CPU Core subversion */
+#define CONFIG_ARMADA100		1	/* SOC Family Name */
+#define CONFIG_ARMADA168		1	/* SOC Used on this Board */
+#define CONFIG_MACH_TYPE		MACH_TYPE_GPLUGD /* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * There is no internal RAM in ARMADA100, using DRAM
+ * TBD: dcache to be used for this
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - 0x00200000)
+
+/*
+ * Commands configuration
+ */
+
+/* Network configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_ARMADA100_FEC
+
+/* DHCP Support */
+#define CONFIG_BOOTP_DHCP_REQUEST_DELAY		50000
+#endif /* CONFIG_CMD_NET */
+
+/* GPIO Support */
+#define CONFIG_MARVELL_GPIO
+
+/* PHY configuration */
+#define CONFIG_RESET_PHY_R
+/* 88E3015 register definition */
+#define PHY_LED_PAR_SEL_REG		22
+#define PHY_LED_MAN_REG			25
+#define PHY_LED_VAL			0x5b	/* LINK LED1, ACT LED2 */
+/* GPIO Configuration for PHY */
+#define CONFIG_SYS_GPIO_PHY_RST		104	/* GPIO104 */
+
+/* Flash Support */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#ifdef CONFIG_SYS_NS16550_COM1
+#undef CONFIG_SYS_NS16550_COM1
+#endif /* CONFIG_SYS_NS16550_COM1 */
+
+#define CONFIG_SYS_NS16550_COM1 ARMD1_UART3_BASE
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_SIZE			0x4000
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_ARMADA100
+#define CONFIG_EHCI_IS_TDI
+#endif /* CONFIG_CMD_USB */
+
+#endif	/* __CONFIG_GPLUGD_H */
diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
new file mode 100644
index 0000000..26ca694
--- /dev/null
+++ b/include/configs/grpeach.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Renesas GRPEACH board
+ *
+ * Copyright (C) 2017-2019 Renesas Electronics
+ */
+
+#ifndef __GRPEACH_H
+#define __GRPEACH_H
+
+/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
+#define CONFIG_SYS_CLK_FREQ	66666666
+
+/* Serial Console */
+#define CONFIG_BAUDRATE		115200
+
+/* Miscellaneous */
+#define CONFIG_SYS_PBSIZE	256
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+#define CONFIG_CMDLINE_TAG
+
+/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		(10 * 1024 * 1024)
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+
+#define CONFIG_ENV_OVERWRITE		1
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_SIZE			(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET		0x80000
+
+/* Malloc */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+/* Kernel Boot */
+#define CONFIG_BOOTARGS			"ignore_loglevel"
+
+/* Network interface */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+#endif	/* __GRPEACH_H */
diff --git a/include/configs/gru.h b/include/configs/gru.h
new file mode 100644
index 0000000..a0d27b6
--- /dev/null
+++ b/include/configs/gru.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdin=serial,cros-ec-keyb\0" \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3399_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
new file mode 100644
index 0000000..739ab32
--- /dev/null
+++ b/include/configs/guruplug.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009-2014
+ * Gerald Kerma <dreagle@doukki.net>
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ */
+
+#ifndef _CONFIG_GURUPLUG_H
+#define _CONFIG_GURUPLUG_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SHEEVA_88SV131	1	/* CPU Core subversion */
+
+/*
+ * Standard filesystems
+ */
+#define CONFIG_BZIP2
+
+/*
+ * mv-plug-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-plug-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_OFFSET		0xE0000	/* env starts here */
+/*
+ * Environment is right behind U-Boot in flash. Make sure U-Boot
+ * doesn't grow into the environment area.
+ */
+#define CONFIG_BOARD_SIZE_LIMIT		CONFIG_ENV_OFFSET
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; "	\
+	"ubi part root; "						\
+	"ubifsmount ubi:rootfs; "					\
+	"ubifsload 0x800000 ${kernel}; "				\
+	"ubifsload 0x700000 ${fdt}; "					\
+	"ubifsumount; "							\
+	"fdt addr 0x700000; fdt resize; fdt chosen; "			\
+	"bootz 0x800000 - 0x700000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=console=ttyS0,115200\0"				\
+	"mtdids=nand0=orion_nand\0"					\
+	"mtdparts="CONFIG_MTDPARTS_DEFAULT			\
+	"kernel=/boot/zImage\0"						\
+	"fdt=/boot/guruplug-server-plus.dtb\0"				\
+	"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 1}	/* enable both ports */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#endif /* _CONFIG_GURUPLUG_H */
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
new file mode 100644
index 0000000..a27627e
--- /dev/null
+++ b/include/configs/gw_ventana.h
@@ -0,0 +1,341 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SPL */
+/* Location in NAND to read U-Boot from */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     (14 * SZ_1M)
+
+/* Falcon Mode */
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x18000000
+
+/* Falcon Mode - NAND support: args@17MB kernel@18MB */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	(18 * SZ_1M)
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x800	/* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	(CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x1000	/* 2MB */
+
+#include "imx6_spl.h"                  /* common IMX6 SPL configuration */
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE	4520   /* Gateworks Ventana Platform */
+
+/* Serial ATAG */
+#define CONFIG_SERIAL_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+/* Init Functions */
+
+/* Driver Model */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_THERMAL
+#endif
+
+/* Thermal */
+#define CONFIG_IMX_THERMAL
+
+/* Serial */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
+
+#ifdef CONFIG_SPI_FLASH
+
+/* SPI */
+#ifdef CONFIG_CMD_SF
+  #define CONFIG_SPI_FLASH_MTD
+					     /* GPIO 3-19 (21248) */
+#endif
+
+#elif defined(CONFIG_SPL_NAND_SUPPORT)
+/* Enable NAND support */
+#ifdef CONFIG_CMD_NAND
+  #define CONFIG_SYS_MAX_NAND_DEVICE	1
+  #define CONFIG_SYS_NAND_BASE		0x40000000
+  #define CONFIG_SYS_NAND_5_ADDR_CYCLE
+  #define CONFIG_SYS_NAND_ONFI_DETECTION
+
+  /* DMA stuff, needed for GPMI/MXS NAND support */
+#endif
+
+#endif /* CONFIG_SPI_FLASH */
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_I2C_GSC			0
+#define CONFIG_I2C_EDID
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+  #define CONFIG_SYS_SATA_MAX_DEVICE	1
+  #define CONFIG_DWC_AHSATA_PORT_ID	0
+  #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+  #define CONFIG_LBA48
+#endif
+
+/*
+ * PCI express
+ */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCI_FIXUP_DEV
+#define CONFIG_PCIE_IMX
+#endif
+
+/*
+ * PMIC
+ */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+#define CONFIG_POWER_LTC3676
+#define CONFIG_POWER_LTC3676_I2C_ADDR  0x3c
+
+/* Various command support */
+#define CONFIG_CMD_UNZIP         /* gzwrite */
+
+/* Ethernet support */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE             ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE      RGMII
+#define CONFIG_FEC_MXC_PHYADDR   0
+#define CONFIG_ARP_TIMEOUT       200UL
+
+/* USB Configs */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET  /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC     (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS      0
+#define CONFIG_USBD_HS
+#define CONFIG_NETCONSOLE
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_HIDE_LOGO_VERSION  /* Custom config to hide U-boot version */
+
+/* Miscellaneous configurable options */
+#define CONFIG_HWCONFIG
+
+/* Memory configuration */
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END	       0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+
+/* Persistent Environment Config */
+#if defined(CONFIG_ENV_IS_IN_MMC)
+  #define CONFIG_SYS_MMC_ENV_DEV         0
+  #define CONFIG_SYS_MMC_ENV_PART        1
+  #define CONFIG_ENV_OFFSET              (709 * SZ_1K)
+  #define CONFIG_ENV_SIZE                (128 * SZ_1K)
+  #define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + (128 * SZ_1K))
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+  #define CONFIG_ENV_OFFSET              (16 * SZ_1M)
+  #define CONFIG_ENV_SECT_SIZE           (128 * SZ_1K)
+  #define CONFIG_ENV_SIZE                CONFIG_ENV_SECT_SIZE
+  #define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + (512 * SZ_1K))
+  #define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+  #define CONFIG_ENV_OFFSET		(512 * SZ_1K)
+  #define CONFIG_ENV_SECT_SIZE		(64 * SZ_1K)
+  #define CONFIG_ENV_SIZE		(8 * SZ_1K)
+#endif
+
+/* Environment */
+#define CONFIG_IPADDR             192.168.1.1
+#define CONFIG_SERVERIP           192.168.1.146
+
+#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+	"pcidisable=1\0" \
+	"splashpos=m,m\0" \
+	"usb_pgood_delay=2000\0" \
+	"console=ttymxc1\0" \
+	"bootdevs=usb mmc sata flash\0" \
+	"hwconfig=_UNKNOWN_\0" \
+	"video=\0" \
+	\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"disk=0\0" \
+	"part=1\0" \
+	\
+	"fdt_high=0xffffffff\0" \
+	"fdt_addr=0x18000000\0" \
+	"initrd_high=0xffffffff\0" \
+	"fixfdt=" \
+		"fdt addr ${fdt_addr}\0" \
+	"bootdir=boot\0" \
+	"loadfdt=" \
+		"if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \
+			"echo Loaded DTB from ${bootdir}/${fdt_file}; " \
+			"run fixfdt; " \
+		"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \
+			"echo Loaded DTB from ${bootdir}/${fdt_file1}; " \
+			"run fixfdt; " \
+		"elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \
+			"echo Loaded DTB from ${bootdir}/${fdt_file2}; " \
+			"run fixfdt; " \
+		"fi\0" \
+	\
+	"fs=ext4\0" \
+	"script=6x_bootscript-ventana\0" \
+	"loadscript=" \
+		"if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \
+			"source ${loadaddr}; " \
+		"fi\0" \
+	\
+	"uimage=uImage\0" \
+	"mmc_root=mmcblk0p1\0" \
+	"mmc_boot=" \
+		"setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \
+		"mmc dev ${disk} && mmc rescan && " \
+		"setenv dtype mmc; run loadscript; " \
+		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/${mmc_root} rootfstype=${fs} " \
+				"rootwait rw ${video} ${extra}; " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"bootm; " \
+			"fi; " \
+		"fi\0" \
+	\
+	"sata_boot=" \
+		"setenv fsload \"${fs}load sata ${disk}:${part}\"; " \
+		"sata init && " \
+		"setenv dtype sata; run loadscript; " \
+		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/sda1 rootfstype=${fs} " \
+				"rootwait rw ${video} ${extra}; " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"bootm; " \
+			"fi; " \
+		"fi\0" \
+	"usb_boot=" \
+		"setenv fsload \"${fs}load usb ${disk}:${part}\"; " \
+		"usb start && usb dev ${disk} && " \
+		"setenv dtype usb; run loadscript; " \
+		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/sda1 rootfstype=${fs} " \
+				"rootwait rw ${video} ${extra}; " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"bootm; " \
+			"fi; " \
+		"fi\0"
+
+#ifdef CONFIG_SPI_FLASH
+	#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+	"image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \
+	"image_uboot=ventana/u-boot_spi.imx\0" \
+	\
+	"spi_koffset=0x90000\0" \
+	"spi_klen=0x200000\0" \
+	\
+	"spi_updateuboot=echo Updating uboot from " \
+		"${serverip}:${image_uboot}...; " \
+		"tftpboot ${loadaddr} ${image_uboot} && " \
+		"sf probe && sf erase 0 80000 && " \
+			"sf write ${loadaddr} 400 ${filesize}\0" \
+	"spi_update=echo Updating OS from ${serverip}:${image_os} " \
+		"to ${spi_koffset} ...; " \
+		"tftp ${loadaddr} ${image_os} && " \
+		"sf probe && " \
+		"sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \
+	\
+	"flash_boot=" \
+		"if sf probe && " \
+		"sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/mtdblock3 " \
+				"rootfstype=squashfs,jffs2 " \
+				"${video} ${extra}; " \
+			"bootm; " \
+		"fi\0"
+#else
+	#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+	\
+	"image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \
+	"nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \
+		"tftp ${loadaddr} ${image_rootfs} && " \
+		"nand erase.part rootfs && " \
+		"nand write ${loadaddr} rootfs ${filesize}\0" \
+	\
+	"flash_boot=" \
+		"setenv fsload 'ubifsload'; " \
+		"ubi part rootfs; " \
+		"if ubi check boot; then " \
+			"ubifsmount ubi0:boot; " \
+			"setenv root ubi0:rootfs ubi.mtd=2 " \
+				"rootfstype=squashfs,ubifs; " \
+			"setenv bootdir; " \
+		"elif ubi check rootfs; then " \
+			"ubifsmount ubi0:rootfs; " \
+			"setenv root ubi0:rootfs ubi.mtd=2 " \
+				"rootfstype=ubifs; " \
+		"fi; " \
+		"setenv dtype nand; run loadscript; " \
+		"if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=${root} ${video} ${extra}; " \
+			"if run loadfdt; then " \
+				"ubifsumount; " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"ubifsumount; bootm; " \
+			"fi; " \
+		"fi\0"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+	"for btype in ${bootdevs}; do " \
+		"echo; echo Attempting ${btype} boot...; " \
+		"if run ${btype}_boot; then; fi; " \
+	"done"
+
+#endif			       /* __CONFIG_H */
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
new file mode 100644
index 0000000..f873cea
--- /dev/null
+++ b/include/configs/harmony.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include "tegra20-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Harmony"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD
+
+/* UARTD: keyboard satellite board UART, default */
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
+/* UARTA: debug board UART */
+#define CONFIG_SYS_NS16550_COM2		NV_PA_APB_UARTA_BASE
+#endif
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_HARMONY
+
+/* NAND support */
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Environment in NAND (which is 512M), aligned to start of last sector */
+#define CONFIG_ENV_OFFSET	(SZ_512M - SZ_128K) /* 128K sector size */
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/helios4.h b/include/configs/helios4.h
new file mode 100644
index 0000000..4df3200
--- /dev/null
+++ b/include/configs/helios4.h
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Dennis Gilmore <dgilmore@redhat.com>
+ */
+
+#ifndef _CONFIG_HELIOS4_H
+#define _CONFIG_HELIOS4_H
+
+#include <linux/sizes.h>
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * SDIO/MMC Card Configuration
+ */
+#define CONFIG_SYS_MMC_BASE		MVEBU_SDIO_BASE
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+#define CONFIG_ENV_MIN_ENTRIES		128
+
+/*
+ * SATA/SCSI/AHCI configuration
+ */
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID     2
+#define CONFIG_SYS_SCSI_MAX_LUN         2
+#define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					CONFIG_SYS_SCSI_MAX_LUN)
+
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_SECT_SIZE		SZ_64K
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_OFFSET		SZ_1M
+#endif
+
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
+/* Environment in MMC */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SECT_SIZE		0x200
+#define CONFIG_ENV_SIZE			0x2000
+/* stay within first 1M */
+#define CONFIG_ENV_OFFSET		(SZ_1M - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+#endif
+
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define RELOCATION_LIMITS_ENV_SETTINGS	\
+	"fdt_high=0x10000000\0"		\
+	"initrd_high=0x10000000\0"
+
+/* SPL */
+/*
+ * Select the boot device here
+ *
+ * Currently supported are:
+ * SPL_BOOT_SPI_NOR_FLASH	- Booting via SPI NOR flash
+ * SPL_BOOT_SDIO_MMC_CARD	- Booting via SDIO/MMC card (partition 1)
+ */
+#define SPL_BOOT_SPI_NOR_FLASH		1
+#define SPL_BOOT_SDIO_MMC_CARD		2
+
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
+#define CONFIG_SPL_BOOT_DEVICE		SPL_BOOT_SPI_NOR_FLASH
+#endif
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
+#define CONFIG_SPL_BOOT_DEVICE		SPL_BOOT_SDIO_MMC_CARD
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL_SIZE			(140 << 10)
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
+/* SPL related MMC defines */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMC_U_BOOT_OFFS		(160 << 10)
+#define CONFIG_SYS_U_BOOT_OFFS			CONFIG_SYS_MMC_U_BOOT_OFFS
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER	0x00180000	/* in SDRAM */
+#endif
+#endif
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Include the common distro boot environment */
+#ifndef CONFIG_SPL_BUILD
+
+#ifdef CONFIG_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#ifdef CONFIG_SATA
+#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0)
+#else
+#define BOOT_TARGET_DEVICES_SATA(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_USB(func) \
+	BOOT_TARGET_DEVICES_SATA(func) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#define KERNEL_ADDR_R	__stringify(0x800000)
+#define FDT_ADDR_R	__stringify(0x100000)
+#define RAMDISK_ADDR_R	__stringify(0x1800000)
+#define SCRIPT_ADDR_R	__stringify(0x200000)
+#define PXEFILE_ADDR_R	__stringify(0x300000)
+
+#define LOAD_ADDRESS_ENV_SETTINGS \
+	"kernel_addr_r=" KERNEL_ADDR_R "\0" \
+	"fdt_addr_r=" FDT_ADDR_R "\0" \
+	"ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
+	"scriptaddr=" SCRIPT_ADDR_R "\0" \
+	"pxefile_addr_r=" PXEFILE_ADDR_R "\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	RELOCATION_LIMITS_ENV_SETTINGS \
+	LOAD_ADDRESS_ENV_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+	"console=ttyS0,115200\0" \
+	BOOTENV
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* _CONFIG_HELIOS4_H */
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
new file mode 100644
index 0000000..c0e295b
--- /dev/null
+++ b/include/configs/highbank.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
+
+#define CONFIG_SYS_TIMER_RATE		(150000000/256)
+#define CONFIG_SYS_TIMER_COUNTER	(0xFFF34000 + 0x4)
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+
+#define CONFIG_PL011_CLOCK		150000000
+#define CONFIG_PL01x_PORTS		{ (void *)(0xFFF36000) }
+
+#define CONFIG_SYS_BOOTCOUNT_LE		/* Use little-endian accessors */
+
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	5
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					CONFIG_SYS_SCSI_MAX_LUN)
+
+#define CONFIG_CALXEDA_XGMAC
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_BOOT_RETRY_TIME		-1
+#define CONFIG_RESET_TO_RETRY
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		0x800000
+#define CONFIG_SYS_64BIT_LBA
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ * The DRAM is already setup, so do not touch the DT node later.
+ */
+#define PHYS_SDRAM_1_SIZE		(4089 << 20)
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1_SIZE - 0x100000)
+
+/* Environment data setup
+*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfff88000	/* NVRAM base address */
+#define CONFIG_SYS_NVRAM_SIZE		0x8000		/* NVRAM size */
+#define CONFIG_ENV_SIZE			0x2000		/* Size of Environ */
+#define CONFIG_ENV_ADDR			CONFIG_SYS_NVRAM_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR		0x01000000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#endif
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
new file mode 100644
index 0000000..60c6bde
--- /dev/null
+++ b/include/configs/hikey.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Linaro
+ *
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * Configuration for HiKey 96boards CE. Parts were derived from other ARM
+ * configurations.
+ */
+
+#ifndef __HIKEY_H
+#define __HIKEY_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_POWER
+#define CONFIG_POWER_HI6553
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+/* Physical Memory Map */
+
+/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
+
+#define PHYS_SDRAM_1			0x00000000
+
+/* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/
+#define PHYS_SDRAM_1_SIZE		0x3EFFFFFF
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x80000)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		19000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0xf6801000
+#define GICC_BASE			0xf6802000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_8M)
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000
+/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/
+#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
+#endif
+
+#define CONFIG_HIKEY_GPIO
+
+/* Command line configuration */
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Initial environment variables */
+
+/*
+ * Defines where the kernel and FDT will be put in RAM
+ */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(MMC, mmc, 1) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+				"kernel_name=Image\0"	\
+				"kernel_addr_r=0x00080000\0" \
+				"fdtfile=hi6220-hikey.dtb\0" \
+				"fdt_addr_r=0x02000000\0" \
+				"fdt_high=0xffffffffffffffff\0" \
+				"initrd_high=0xffffffffffffffff\0" \
+				BOOTENV
+
+/* Preserve environment on eMMC */
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* Use eMMC */
+#define CONFIG_SYS_MMC_ENV_PART		2	/* Use Boot1 partition */
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#endif /* __HIKEY_H */
diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h
new file mode 100644
index 0000000..f6f9c8d
--- /dev/null
+++ b/include/configs/hikey960.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Linaro
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#ifndef __HIKEY_H
+#define __HIKEY_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+/* Physical Memory Map */
+
+/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
+
+#define PHYS_SDRAM_1			0x00000000
+#define PHYS_SDRAM_1_SIZE		0xC0000000
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x80000)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		19000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0xe82b1000
+#define GICC_BASE			0xe82b2000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_8M)
+
+#define CONFIG_ENV_SIZE			0x1000
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+				"image=Image\0"	\
+				"fdtfile=hi3660-hikey960.dtb\0" \
+				"fdt_addr_r=0x10000000\0" \
+				"kernel_addr_r=0x11000000\0" \
+				"scriptaddr=0x00020000\0" \
+				"fdt_high=0xffffffffffffffff\0" \
+				"initrd_high=0xffffffffffffffff\0" \
+				BOOTENV
+
+#define CONFIG_ENV_SIZE			0x1000
+
+/* TODO: Remove this once the SD clock is fixed */
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	1024
+
+#endif /* __HIKEY_H */
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
new file mode 100644
index 0000000..8fb3211
--- /dev/null
+++ b/include/configs/hrcon.h
@@ -0,0 +1,438 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of one chip NT5TU64M16HG from NANYA
+ */
+
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ONLY_CURRENT \
+				| CSCONFIG_BANK_BIT_3 \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00260802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (9 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x26279222 */
+#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x021848c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x08240100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_16)
+				/* 0x43100000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0440 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0242 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=4, AL=0 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * FLASH on the Local Bus
+ */
+#if 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx16
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
+
+#define CONFIG_SYS_FPGA_COUNT		1
+
+#define CONFIG_SYS_MCLINK_MAX		3
+
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* Pass open firmware flat tree */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+
+#define CONFIG_PCA953X			/* NXP PCA9554 */
+#define CONFIG_PCA9698			/* NXP PCA9698 */
+
+#define CONFIG_SYS_I2C_IHS
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH2
+#define CONFIG_SYS_I2C_IHS_SPEED_2		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2		0x7F
+#define CONFIG_SYS_I2C_IHS_CH3
+#define CONFIG_SYS_I2C_IHS_SPEED_3		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F
+
+#ifdef CONFIG_HRCON_DH
+#define CONFIG_SYS_I2C_IHS_DUAL
+#define CONFIG_SYS_I2C_IHS_CH0_1
+#define CONFIG_SYS_I2C_IHS_SPEED_0_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH1_1
+#define CONFIG_SYS_I2C_IHS_SPEED_1_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH2_1
+#define CONFIG_SYS_I2C_IHS_SPEED_2_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH3_1
+#define CONFIG_SYS_I2C_IHS_SPEED_3_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3_1		0x7F
+#endif
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE		0x7F
+#define I2C_SOFT_DECLARATIONS2
+#define CONFIG_SYS_I2C_SOFT_SPEED_2		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_2		0x7F
+#define I2C_SOFT_DECLARATIONS3
+#define CONFIG_SYS_I2C_SOFT_SPEED_3		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_3		0x7F
+#define I2C_SOFT_DECLARATIONS4
+#define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
+#define I2C_SOFT_DECLARATIONS5
+#define CONFIG_SYS_I2C_SOFT_SPEED_5		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_5		0x7F
+#define I2C_SOFT_DECLARATIONS6
+#define CONFIG_SYS_I2C_SOFT_SPEED_6		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_6		0x7F
+#define I2C_SOFT_DECLARATIONS7
+#define CONFIG_SYS_I2C_SOFT_SPEED_7		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_7		0x7F
+#define I2C_SOFT_DECLARATIONS8
+#define CONFIG_SYS_I2C_SOFT_SPEED_8		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_8		0x7F
+
+#ifdef CONFIG_HRCON_DH
+#define I2C_SOFT_DECLARATIONS9
+#define CONFIG_SYS_I2C_SOFT_SPEED_9		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_9		0x7F
+#define I2C_SOFT_DECLARATIONS10
+#define CONFIG_SYS_I2C_SOFT_SPEED_10		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_10		0x7F
+#define I2C_SOFT_DECLARATIONS11
+#define CONFIG_SYS_I2C_SOFT_SPEED_11		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_11		0x7F
+#define I2C_SOFT_DECLARATIONS12
+#define CONFIG_SYS_I2C_SOFT_SPEED_12		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_12		0x7F
+#endif
+
+#ifdef CONFIG_HRCON_DH
+#define CONFIG_SYS_ICS8N3QV01_I2C		{13, 14, 15, 16, 17, 18, 19, 20}
+#define CONFIG_SYS_DP501_I2C			{1, 3, 5, 7, 2, 4, 6, 8}
+#define CONFIG_HRCON_FANS			{ {10, 0x4c}, {11, 0x4c}, \
+						  {12, 0x4c} }
+#else
+#define CONFIG_SYS_ICS8N3QV01_I2C		{9, 10, 11, 12}
+#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
+#define CONFIG_HRCON_FANS			{ {6, 0x4c}, {7, 0x4c}, \
+						  {8, 0x4c} }
+#endif
+
+#ifndef __ASSEMBLY__
+void fpga_gpio_set(unsigned int bus, int pin);
+void fpga_gpio_clear(unsigned int bus, int pin);
+int fpga_gpio_get(unsigned int bus, int pin);
+void fpga_control_set(unsigned int bus, int pin);
+void fpga_control_clear(unsigned int bus, int pin);
+#endif
+
+#define I2C_SDA_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
+#define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
+#define I2C_FPGA_IDX	(I2C_ADAP_HWNR % 4)
+
+#ifdef CONFIG_HRCON_DH
+#define I2C_ACTIVE \
+	do { \
+		if (I2C_ADAP_HWNR > 7) \
+			fpga_control_set(I2C_FPGA_IDX, 0x0004); \
+		else \
+			fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
+	} while (0)
+#else
+#define I2C_ACTIVE	{ }
+#endif
+#define I2C_TRISTATE	{ }
+#define I2C_READ \
+	(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
+#define I2C_SDA(bit) \
+	do { \
+		if (bit) \
+			fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
+		else \
+			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
+	} while (0)
+#define I2C_SCL(bit) \
+	do { \
+		if (bit) \
+			fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
+		else \
+			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
+	} while (0)
+#define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
+
+/*
+ * Software (bit-bang) MII driver configuration
+ */
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_OSD_SCREENS		1
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
+
+#ifdef CONFIG_HRCON_DH
+#define CONFIG_SYS_OSD_DH
+#endif
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+/* enable PCIE clock */
+#define CONFIG_SYS_SCCR_PCIEXP1CM	1
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+/*
+ * Environment
+ */
+#if 1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+#else
+#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
+
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+
+#define CONFIG_HOSTNAME		"hrcon"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS1\0"						\
+	"u-boot=u-boot.bin\0"						\
+	"kernel_addr=1000000\0"					\
+	"fdt_addr=C00000\0"						\
+	"fdtfile=hrcon.dtb\0"				\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+		" +${filesize};cp.b ${fileaddr} "			\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
+	"upd=run load update\0"						\
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp ${kernel_addr} $bootfile;"				\
+	"tftp ${fdt_addr} $fdtfile;"					\
+	"bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_MMCBOOTCOMMAND						\
+	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait "		\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"ext2load mmc 0:2 ${kernel_addr} $bootfile;"			\
+	"ext2load mmc 0:2 ${fdt_addr} $fdtfile;"			\
+	"bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_MMCBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h
new file mode 100644
index 0000000..7735cc1
--- /dev/null
+++ b/include/configs/hsdk.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef _CONFIG_HSDK_H_
+#define _CONFIG_HSDK_H_
+
+#include <linux/sizes.h>
+
+/*
+ *  CPU configuration
+ */
+#define NR_CPUS				4
+#define ARC_PERIPHERAL_BASE		0xF0000000
+#define ARC_DWMMC_BASE			(ARC_PERIPHERAL_BASE + 0xA000)
+#define ARC_DWGMAC_BASE			(ARC_PERIPHERAL_BASE + 0x18000)
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		SZ_1G
+
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_2M
+#define CONFIG_SYS_BOOTM_LEN		SZ_128M
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+/*
+ * UART configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK		33330000
+#define CONFIG_SYS_NS16550_MEM32
+
+/*
+ * Ethernet PHY configuration
+ */
+
+/*
+ * USB 1.1 configuration
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"upgrade=if mmc rescan && " \
+		"fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
+		"iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
+		"\"Fail to upgrade.\n" \
+		"Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \
+		"; fi\0" \
+	"core_dccm_0=0x10\0" \
+	"core_dccm_1=0x6\0" \
+	"core_dccm_2=0x10\0" \
+	"core_dccm_3=0x6\0" \
+	"core_iccm_0=0x10\0" \
+	"core_iccm_1=0x6\0" \
+	"core_iccm_2=0x10\0" \
+	"core_iccm_3=0x6\0" \
+	"core_mask=0xF\0" \
+	"dcache_ena=0x1\0" \
+	"icache_ena=0x1\0" \
+	"non_volatile_limit=0xE\0" \
+	"hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \
+setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \
+	"hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
+	"hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
+	"hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
+	"hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
+	"hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
+	"hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
+	"hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
+setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
+setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
+setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+/* Cli configuration */
+#define CONFIG_SYS_CBSIZE		SZ_2K
+
+/*
+ * Callback configuration
+ */
+#define CONFIG_BOARD_LATE_INIT
+
+#endif /* _CONFIG_HSDK_H_ */
diff --git a/include/configs/huawei_hg556a.h b/include/configs/huawei_hg556a.h
new file mode 100644
index 0000000..2aa5c66
--- /dev/null
+++ b/include/configs/huawei_hg556a.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6358.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE	SZ_8K
diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h
new file mode 100644
index 0000000..5e54441
--- /dev/null
+++ b/include/configs/ib62x0.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011-2012
+ * Gerald Kerma <dreagle@doukki.net>
+ * Luka Perkov <luka@openwrt.org>
+ */
+
+#ifndef _CONFIG_IB62x0_H
+#define _CONFIG_IB62x0_H
+
+/*
+ * High level configuration options
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Compression configuration
+ */
+#define CONFIG_BZIP2
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Environment variables configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_OFFSET	0xe0000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; "	\
+	"ubi part root; "						\
+	"ubifsmount ubi:rootfs; "					\
+	"ubifsload 0x800000 ${kernel}; "				\
+	"ubifsload 0x700000 ${fdt}; "					\
+	"ubifsumount; "							\
+	"fdt addr 0x700000; fdt resize; fdt chosen; "			\
+	"bootz 0x800000 - 0x700000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=console=ttyS0,115200\0"				\
+	"mtdids=nand0=orion_nand\0"					\
+	"mtdparts="CONFIG_MTDPARTS_DEFAULT			\
+	"kernel=/boot/zImage\0"						\
+	"fdt=/boot/ib62x0.dtb\0"					\
+	"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
+
+/*
+ * Ethernet driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#undef CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA driver configuration
+ */
+#ifdef CONFIG_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_MVSATA_IDE_USE_PORT1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
+#endif /* CONFIG_IDE */
+
+/*
+ * RTC driver configuration
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_IB62x0_H */
diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h
new file mode 100644
index 0000000..87113d7
--- /dev/null
+++ b/include/configs/iconnect.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ */
+
+#ifndef _CONFIG_ICONNECT_H
+#define _CONFIG_ICONNECT_H
+
+/*
+ * High level configuration options
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Machine type
+ */
+#define CONFIG_MACH_TYPE	MACH_TYPE_ICONNECT
+
+/*
+ * Compression configuration
+ */
+#define CONFIG_BZIP2
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Environment variables configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_OFFSET	0x80000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; "	\
+	"ubi part rootfs; "						\
+	"ubifsmount ubi:rootfs; "					\
+	"ubifsload 0x800000 ${kernel}; "				\
+	"bootm 0x800000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=console=ttyS0,115200\0"	\
+	"mtdids=nand0=orion_nand\0"		\
+	"mtdparts="CONFIG_MTDPARTS_DEFAULT	\
+	"kernel=/boot/uImage\0"			\
+	"bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+
+/*
+ * Ethernet driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	11
+#undef CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * File system
+ */
+
+#endif /* _CONFIG_ICONNECT_H */
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
new file mode 100644
index 0000000..43cb14c
--- /dev/null
+++ b/include/configs/ids8313.h
@@ -0,0 +1,306 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (c) 2011 IDS GmbH, Germany
+ * Sergej Stepanov <ste@ids.de>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_FSL_ELBC
+
+#define CONFIG_BOOT_RETRY_TIME		900
+#define CONFIG_BOOT_RETRY_MIN		30
+#define CONFIG_RESET_TO_RETRY
+
+#define CONFIG_SYS_SICRH	0x00000000
+#define CONFIG_SYS_SICRL	(SICRL_LBC | SICRL_SPI_D)
+
+#define CONFIG_HWCONFIG
+
+/*
+ * Definitions for initial stack pointer and data area (in DCACHE )
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000  /* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+					 - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Internal Definitions
+ */
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/*
+ * Manually set up DDR parameters,
+ * as this board has not the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN |\
+					 0x00010000 |\
+					 CSCONFIG_ROW_BIT_13 |\
+					 CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_CONFIG_256	(CONFIG_SYS_DDR_CONFIG | \
+					 CSCONFIG_BANK_BIT_3)
+
+#define CONFIG_SYS_DDR_TIMING_3	(1 << 16)	/* ext refrec */
+#define CONFIG_SYS_DDR_TIMING_0	((3 << TIMING_CFG0_RWT_SHIFT) |\
+				(3 << TIMING_CFG0_WRT_SHIFT) |\
+				(3 << TIMING_CFG0_RRT_SHIFT) |\
+				(3 << TIMING_CFG0_WWT_SHIFT) |\
+				(6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
+				(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
+				(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				(2 << TIMING_CFG0_MRS_CYC_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_1	((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
+				(12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
+				(4 << TIMING_CFG1_ACTTORW_SHIFT) |\
+				(7 << TIMING_CFG1_CASLAT_SHIFT) |\
+				(4 << TIMING_CFG1_REFREC_SHIFT) |\
+				(4 << TIMING_CFG1_WRREC_SHIFT) |\
+				(2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
+				(2 << TIMING_CFG1_WRTORD_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
+				(5 << TIMING_CFG2_CPO_SHIFT) |\
+				(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
+				(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
+				(0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
+				(1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
+				(6 << TIMING_CFG2_FOUR_ACT_SHIFT))
+
+#define CONFIG_SYS_DDR_INTERVAL	((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
+				(0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+
+#define CONFIG_SYS_SDRAM_CFG		(SDRAM_CFG_SREN |\
+					 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
+					 SDRAM_CFG_DBW_32 |\
+					 SDRAM_CFG_SDRAM_TYPE_DDR2)
+
+#define CONFIG_SYS_SDRAM_CFG2		0x00401000
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
+					 (0x0242 << SDRAM_MODE_SD_SHIFT))
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN |\
+					 DDRCDR_PZ_NOMZ |\
+					 DDRCDR_NZ_NOMZ |\
+					 DDRCDR_ODT |\
+					 DDRCDR_M_ODR |\
+					 DDRCDR_Q_DRN)
+
+/*
+ * on-board devices
+ */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+
+/*
+ * NOR FLASH setup
+ */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_FLASH_SHOW_PROGRESS	50
+
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_FLASH_SIZE		8
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+/*
+ * NAND FLASH setup
+ */
+#define CONFIG_SYS_NAND_BASE		0xE1000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2048)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
+#define NAND_CACHE_PAGES		64
+
+
+/*
+ * MRAM setup
+ */
+#define CONFIG_SYS_MRAM_BASE		0xE2000000
+#define CONFIG_SYS_MRAM_SIZE		0x20000	/* 128 Kb */
+
+#define CONFIG_SYS_OR_TIMING_MRAM
+
+
+/*
+ * CPLD setup
+ */
+#define CONFIG_SYS_CPLD_BASE		0xE3000000
+#define CONFIG_SYS_CPLD_SIZE		0x8000
+
+#define CONFIG_SYS_OR_TIMING_MRAM
+
+
+/*
+ * HW-Watchdog
+ */
+#define CONFIG_WATCHDOG		1
+#define CONFIG_SYS_WATCHDOG_VALUE	0xFFFF
+
+/*
+ * I2C setup
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
+
+/*
+ * Ethernet setup
+ */
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME		"TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR			0x1
+#define TSEC1_FLAGS			TSEC_GIGABIT
+#define TSEC1_PHYIDX			0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define TSEC2_PHY_ADDR			0x3
+#define TSEC2_FLAGS			TSEC_GIGABIT
+#define TSEC2_PHYIDX			0
+#endif
+#define CONFIG_ETHPRIME		"TSEC1"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
+
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_SCCR_USBDRCM	3
+
+/*
+ * U-Boot environment setup
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(8 * 1024 * 1024)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE \
+				+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_NETDEV			eth1
+#define CONFIG_HOSTNAME		"ids8313"
+#define CONFIG_ROOTPATH		"/opt/eldk-4.2/ppc_6xx"
+#define CONFIG_BOOTFILE		"ids8313/uImage"
+#define CONFIG_UBOOTPATH		"ids8313/u-boot.bin"
+#define CONFIG_FDTFILE			"ids8313/ids8313.dtb"
+#define CONFIG_LOADADDR		0x400000
+#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x00001000
+#define CONFIG_SYS_MEMTEST_END		0x00C00000
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000
+#define CONFIG_LOADS_ECHO
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTCOMMAND		"run boot_cramfs"
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV		"0"
+
+/* mtdparts command line support */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" __stringify(CONFIG_NETDEV) "\0"			\
+	"ethprime=TSEC1\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"tftpflash=tftpboot ${loadaddr} ${uboot}; "			\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" +${filesize}; "					\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +${filesize}; "					\
+		"cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" ${filesize}; "					\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +${filesize}; "					\
+		"cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" ${filesize}\0"					\
+	"console=ttyS0\0"						\
+	"fdtaddr=0x780000\0"						\
+	"kernel_addr=ff800000\0"					\
+	"fdtfile=" __stringify(CONFIG_FDTFILE) "\0"			\
+	"setbootargs=setenv bootargs "					\
+		"root=${rootdev} rw console=${console},"		\
+			"${baudrate} ${othbootargs}\0"			\
+	"setipargs=setenv bootargs root=${rootdev} rw "			\
+			"nfsroot=${serverip}:${rootpath} "		\
+			"ip=${ipaddr}:${serverip}:${gatewayip}:"	\
+			"${netmask}:${hostname}:${netdev}:off "		\
+			"console=${console},${baudrate} ${othbootargs}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
+	"\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setipargs;run addmtd;"					\
+	"tftp ${loadaddr} ${bootfile};"				\
+	"tftp ${fdtaddr} ${fdtfile};"					\
+	"fdt addr ${fdtaddr};"						\
+	"bootm ${loadaddr} - ${fdtaddr}"
+
+/* UBI Support */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h
new file mode 100644
index 0000000..8e2d723
--- /dev/null
+++ b/include/configs/imgtec_xilfpga.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Imagination Technologies Ltd.
+ *
+ * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+ *
+ * Imagination Technologies Ltd. MIPSfpga
+ */
+
+#ifndef __XILFPGA_CONFIG_H
+#define __XILFPGA_CONFIG_H
+
+/* BootROM + MIG is pretty smart. DDR and Cache initialized */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*--------------------------------------------
+ * CPU configuration
+ */
+/* CPU Timer rate */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	50000000
+
+/*----------------------------------------------------------------------
+ * Memory Layout
+ */
+
+/* SDRAM Configuration (for final code, data, stack, heap) */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 Mbytes */
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000)
+
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_LOAD_ADDR		0x80500000 /* default load address */
+
+/*----------------------------------------------------------------------
+ * Commands
+ */
+
+/*------------------------------------------------------------
+ * Console Configuration
+ */
+#define CONFIG_SYS_CBSIZE		1024 /* Console I/O Buffer Size   */
+
+/* -------------------------------------------------
+ * Environment
+ */
+#define CONFIG_ENV_SIZE		0x4000
+
+/* ---------------------------------------------------------------------
+ * Board boot configuration
+ */
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+#endif	/* __XILFPGA_CONFIG_H */
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
new file mode 100644
index 0000000..730e874
--- /dev/null
+++ b/include/configs/imx27lite-common.h
@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
+ *
+ * based on:
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ */
+
+#ifndef __IMX27LITE_COMMON_CONFIG_H
+#define __IMX27LITE_COMMON_CONFIG_H
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MX27
+#define CONFIG_MX27_CLK32	32768		/* OSC32K frequency */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Lowlevel configuration
+ */
+#define SDRAM_ESDCFG_REGISTER_VAL(cas)	\
+		(ESDCFG_TRC(10) |	\
+		ESDCFG_TRCD(3) |	\
+		ESDCFG_TCAS(cas) |	\
+		ESDCFG_TRRD(1) |	\
+		ESDCFG_TRAS(5) |	\
+		ESDCFG_TWR |		\
+		ESDCFG_TMRD(2) |	\
+		ESDCFG_TRP(2) |		\
+		ESDCFG_TXP(3))
+
+#define SDRAM_ESDCTL_REGISTER_VAL	\
+		(ESDCTL_PRCT(0) |	\
+		 ESDCTL_BL |		\
+		 ESDCTL_PWDT(0) |	\
+		 ESDCTL_SREFR(3) |	\
+		 ESDCTL_DSIZ_32 |	\
+		 ESDCTL_COL10 |		\
+		 ESDCTL_ROW13 |		\
+		 ESDCTL_SDE)
+
+#define SDRAM_ALL_VAL		0xf00
+
+#define SDRAM_MODE_REGISTER_VAL	0x33	/* BL: 8, CAS: 3 */
+#define SDRAM_EXT_MODE_REGISTER_VAL	0x1000000
+
+#define MPCTL0_VAL	0x1ef15d5
+
+#define SPCTL0_VAL	0x043a1c09
+
+#define CSCR_VAL	0x33f08107
+
+#define PCDR0_VAL	0x120470c3
+#define PCDR1_VAL	0x03030303
+#define PCCR0_VAL	0xffffffff
+#define PCCR1_VAL	0xfffffffc
+
+#define AIPI1_PSR0_VAL	0x20040304
+#define AIPI1_PSR1_VAL	0xdffbfcfb
+#define AIPI2_PSR0_VAL	0x07ffc200
+#define AIPI2_PSR1_VAL	0xffffffff
+
+/*
+ * Memory Info
+ */
+/* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 512 * 1024)
+/* memtest start address */
+#define CONFIG_SYS_MEMTEST_START	0xA0000000
+#define CONFIG_SYS_MEMTEST_END		0xA1000000	/* 16MB RAM test */
+#define PHYS_SDRAM_1		0xA0000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/*
+ * Flash & Environment
+ */
+/* Use buffered writes (~10x faster) */
+/* Use hardware sector protection */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of flash banks */
+/* CS2 Base address */
+#define PHYS_FLASH_1			0xc0000000
+/* Flash Base for U-Boot */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE / \
+		CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x1f
+
+/*
+ * MTD
+ */
+
+/*
+ * NAND
+ */
+#define CONFIG_MXC_NAND_REGS_BASE	0xd8000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0xd8000000
+#define CONFIG_JFFS2_NAND
+#define CONFIG_MXC_NAND_HWECC
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+#define CONFIG_LOADADDR		0xa0800000	/* loadaddr env var */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"		\
+	"kernel_addr_r=a0800000\0"					\
+	"bootfile=" CONFIG_HOSTNAME "/uImage\0"		\
+	"rootpath=/opt/eldk-4.2-arm/arm\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm\0"						\
+	"bootcmd=run net_nfs\0"						\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+		" +${filesize};cp.b ${fileaddr} "			\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
+	"upd=run load update\0"						\
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* __IMX27LITE_COMMON_CONFIG_H */
diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h
new file mode 100644
index 0000000..0826195
--- /dev/null
+++ b/include/configs/imx6-engicam.h
@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * Configuration settings for the Engicam i.MX6 SOM Starter Kits.
+ */
+
+#ifndef __IMX6_ENGICAM_CONFIG_H
+#define __IMX6_ENGICAM_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE			SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+#  define CONFIG_ENV_OFFSET		0x100000
+/* Environment in NAND */
+# elif defined(CONFIG_ENV_IS_IN_NAND)
+#  define CONFIG_ENV_OFFSET		0x400000
+#  define CONFIG_ENV_SECT_SIZE		CONFIG_ENV_SIZE
+# endif
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"splashpos=m,m\0" \
+	"splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+	"image=uImage\0" \
+	"fit_image=fit.itb\0" \
+	"fdt_high=0xffffffff\0" \
+	"fdt_addr=" FDT_ADDR "\0" \
+	"boot_fdt=try\0" \
+	"mmcpart=1\0" \
+	"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"ubiargs=setenv bootargs console=${console},${baudrate} " \
+		"ubi.mtd=5 root=${nandroot} ${mtdparts}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \
+	"altbootcmd=run recoveryboot\0"\
+	"fitboot=echo Booting FIT image from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"_mmcboot=run mmcargs; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"if mmc rescan; then " \
+			"if run loadbootscript; then " \
+				"run bootscript; " \
+			"else " \
+				"if run loadfit; then " \
+					"run fitboot; " \
+				"else " \
+					"if run loadimage; then " \
+						"run _mmcboot; " \
+					"fi; " \
+				"fi; " \
+			"fi; " \
+		"fi\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"if mtdparts; then " \
+			"echo Starting nand boot ...; " \
+		"else " \
+			"mtdparts default; " \
+		"fi; " \
+		"run ubiargs; " \
+		"nand read ${loadaddr} kernel 0x800000; " \
+		"nand read ${fdt_addr} dtb 0x100000; " \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"recoveryboot=if test ${modeboot} = mmcboot; then " \
+			"run mmcboot; " \
+		"else " \
+			"run nandboot; " \
+		"fi\0"
+
+#define CONFIG_BOOTCOMMAND		"run $modeboot"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+#ifdef CONFIG_MX6UL
+# define DRAM_OFFSET(x)			0x87##x
+# define FDT_ADDR			__stringify(DRAM_OFFSET(800000))
+#else 
+# define DRAM_OFFSET(x)			0x1##x
+# define FDT_ADDR			__stringify(DRAM_OFFSET(8000000))
+#endif
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_SP_OFFSET)
+
+/* UART */
+#ifdef CONFIG_MXC_UART
+# ifdef CONFIG_MX6UL
+#  define CONFIG_MXC_UART_BASE		UART1_BASE
+# else
+#  define CONFIG_MXC_UART_BASE		UART4_BASE
+# endif
+#endif
+
+/* MMC */
+#ifdef CONFIG_FSL_USDHC
+# define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+/* NAND */
+#ifdef CONFIG_NAND_MXS
+# define CONFIG_SYS_MAX_NAND_DEVICE	1
+# define CONFIG_SYS_NAND_BASE		0x40000000
+# define CONFIG_SYS_NAND_5_ADDR_CYCLE
+# define CONFIG_SYS_NAND_ONFI_DETECTION
+# define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+# define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000
+
+/* MTD device */
+#endif
+
+/* Ethernet */
+#ifdef CONFIG_FEC_MXC
+# ifdef CONFIG_TARGET_MX6Q_ICORE_RQS
+#  define CONFIG_FEC_MXC_PHYADDR	3
+#  define CONFIG_FEC_XCV_TYPE		RGMII
+# else
+#  define CONFIG_FEC_MXC_PHYADDR	0
+#  define CONFIG_FEC_XCV_TYPE		RMII
+# endif
+#endif
+
+/* Falcon Mode */
+#ifdef CONFIG_SPL_OS_BOOT
+# define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
+# define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
+# define CONFIG_CMD_SPL
+# define CONFIG_SYS_SPL_ARGS_ADDR	0x18000000
+# define CONFIG_CMD_SPL_WRITE_SIZE	(128 * SZ_1K)
+
+/* MMC support: args@1MB kernel@2MB */
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR		0x800   /* 1MB */
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS		(CONFIG_CMD_SPL_WRITE_SIZE / 512)
+# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x1000  /* 2MB */
+#endif
+
+/* Framebuffer */
+#ifdef CONFIG_VIDEO_IPUV3
+# define CONFIG_IMX_VIDEO_SKIP
+
+# define CONFIG_SPLASH_SCREEN
+# define CONFIG_SPLASH_SCREEN_ALIGN
+# define CONFIG_BMP_16BPP
+# define CONFIG_VIDEO_BMP_RLE8
+# define CONFIG_VIDEO_LOGO
+# define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL
+# ifdef CONFIG_ENV_IS_IN_NAND
+#  define CONFIG_SPL_NAND_SUPPORT
+# else
+#  define CONFIG_SPL_MMC_SUPPORT
+# endif
+
+# include "imx6_spl.h"
+#endif
+
+#endif /* __IMX6_ENGICAM_CONFIG_H */
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h
new file mode 100644
index 0000000..d6b7477
--- /dev/null
+++ b/include/configs/imx6_logic.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Logic PD, Inc.
+ *
+ * Configuration settings for the LogicPD i.MX6 SOM.
+ */
+
+#ifndef __IMX6LOGIC_CONFIG_H
+#define __IMX6LOGIC_CONFIG_H
+
+#define CONFIG_MXC_UART_BASE   UART1_BASE
+#define CONSOLE_DEV            "ttymxc0"
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN          (10 * SZ_1M)
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+
+
+/* Ethernet Configs */
+#define CONFIG_FEC_XCV_TYPE            RMII
+#define CONFIG_ETHPRIME                "FEC"
+#define CONFIG_FEC_MXC_PHYADDR         0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"bootm_size=0x10000000\0" \
+	"fdt_addr_r=0x13000000\0" \
+	"ramdisk_addr_r=0x14000000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_file=rootfs.cpio.uboot\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"console=" CONSOLE_DEV "\0" \
+	"mmcdev=1\0" \
+	"mmcpart=1\0" \
+	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+	"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate}" \
+	" root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \
+	"nandargs=setenv bootargs console=${console},${baudrate}" \
+	" ubi.mtd=fs root=${nandroot} ${mtdparts} ${optargs}\0" \
+	"ramargs=setenv bootargs console=${console},${baudrate}" \
+	" root=/dev/ram rw ${mtdparts} ${optargs}\0"                    \
+	"loadbootscript=" \
+	"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...;" \
+	" source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};" \
+	" setenv kernelsize ${filesize}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdt_file}\0" \
+	"loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr_r}" \
+	" ${ramdisk_file}; setenv ramdisksize ${filesize}\0" \
+	"mmcboot=echo Booting from mmc...; run finduuid; run mmcargs;" \
+	"run loadimage; run loadfdt; bootz ${loadaddr} - ${fdt_addr_r}\0" \
+	"mmcramboot=run ramargs; run loadimage;" \
+	" run loadfdt; run loadramdisk;" \
+	" bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
+	"nandboot=echo Booting from nand ...; " \
+	" run nandargs;" \
+	" nand read ${loadaddr} kernel ${kernelsize};" \
+	" nand read ${fdt_addr_r} dtb;" \
+	" bootz ${loadaddr} - ${fdt_addr_r}\0" \
+	"nandramboot=echo Booting RAMdisk from nand ...; " \
+	" nand read ${ramdisk_addr_r} fs ${ramdisksize};" \
+	" nand read ${loadaddr} kernel ${kernelsize};" \
+	" nand read ${fdt_addr_r} dtb;" \
+	" run ramargs;" \
+	" bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+	"root=/dev/nfs" \
+	" ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+	"run netargs; " \
+	"if test ${ip_dyn} = yes; then " \
+		"setenv get_cmd dhcp; " \
+	"else " \
+		"setenv get_cmd tftp; " \
+	"fi; " \
+	"${get_cmd} ${image}; " \
+	"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+		"if ${get_cmd} ${fdt_addr_r} ${fdt_file}; then " \
+			"bootz ${loadaddr} - ${fdt_addr_r}; " \
+		"else " \
+			"if test ${boot_fdt} = try; then " \
+				"bootz; " \
+				"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi; " \
+	"else " \
+	       "bootz; " \
+	"fi;\0" \
+	"autoboot=mmc dev ${mmcdev};" \
+	"if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+		"if run loadimage; then " \
+			"run mmcboot; " \
+		"else run netboot; " \
+		"fi; " \
+	"fi; " \
+	"else run netboot; fi"
+#define CONFIG_BOOTCOMMAND \
+	"run autoboot"
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE               (1024 * 1024)
+#define CONFIG_ENV_OFFSET             0x400000
+#define CONFIG_ENV_SECT_SIZE          CONFIG_ENV_SIZE
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000
+
+/* MTD device */
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+
+/* EEPROM  contains serial no, MAC addr and other Logic PD info */
+#define CONFIG_I2C_EEPROM
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1 /* Enabled USB controller number */
+#endif
+
+/* Falcon Mode */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
+#define CONFIG_SYS_SPL_ARGS_ADDR       0x18000000
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
+
+#endif                         /* __IMX6LOGIC_CONFIG_H */
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
new file mode 100644
index 0000000..a223930
--- /dev/null
+++ b/include/configs/imx6_spl.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ */
+#ifndef __IMX6_SPL_CONFIG_H
+#define __IMX6_SPL_CONFIG_H
+
+#ifdef CONFIG_SPL
+
+#ifdef CONFIG_MX6_OCRAM_256KB
+/*
+ * see Figure 8.4.1 in IMX6DQ Reference manuals:
+ *  - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF
+ *  - BOOT ROM stack is at 0x0093FFB8
+ *  - if icache/dcache is enabled (eFuse/strapping controlled) then the
+ *    IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to
+ *    fit between 0x00907000 and 0x00938000.
+ *  - Additionally the BOOT ROM loads what they consider the firmware image
+ *    which consists of a 4K header in front of us that contains the IVT, DCD
+ *    and some padding thus 'our' max size is really 0x00908000 - 0x00938000
+ *    or 192KB
+ */
+#define CONFIG_SPL_MAX_SIZE		0x30000
+#define CONFIG_SPL_STACK		0x0093FFB8
+/*
+ * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the
+ * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+ * boot media (given that boot media specific offset is configured properly).
+ */
+#define CONFIG_SPL_PAD_TO		0x31000
+#else
+/*
+ * see Figure 8-3 in IMX6SDL Reference manuals:
+ *  - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF
+ *  - BOOT ROM stack is at 0x0091FFB8
+ *  - if icache/dcache is enabled (eFuse/strapping controlled) then the
+ *    IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to
+ *    fit between 0x00907000 and 0x00918000.
+ *  - Additionally the BOOT ROM loads what they consider the firmware image
+ *    which consists of a 4K header in front of us that contains the IVT, DCD
+ *    and some padding thus 'our' max size is really 0x00908000 - 0x00918000
+ *    or 64KB
+ */
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_STACK		0x0091FFB8
+/*
+ * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
+ * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+ * boot media (given that boot media specific offset is configured properly).
+ */
+#define CONFIG_SPL_PAD_TO		0x11000
+
+#endif
+
+/* MMC support */
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SYS_MONITOR_LEN			409600	/* 400 KB */
+#endif
+
+/* SATA support */
+#if defined(CONFIG_SPL_SATA_SUPPORT)
+#define CONFIG_SPL_SATA_BOOT_DEVICE		0
+#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION	1
+#endif
+
+/* Define the payload for FAT/EXT support */
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
+# ifdef CONFIG_OF_CONTROL
+#  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot-dtb.img"
+# else
+#  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+# endif
+#endif
+
+#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#define CONFIG_SPL_BSS_START_ADDR      0x88200000
+#define CONFIG_SPL_BSS_MAX_SIZE        0x100000		/* 1 MB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x88300000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000		/* 1 MB */
+#else
+#define CONFIG_SPL_BSS_START_ADDR	0x18200000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x18300000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
+#endif
+#endif
+
+#endif
diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h
new file mode 100644
index 0000000..7605e14
--- /dev/null
+++ b/include/configs/imx6dl-mamoj.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
+ * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * Configuration settings for the BTicion i.MX6DL Mamoj board.
+ */
+
+#ifndef __IMX6DL_MAMOJ_CONFIG_H
+#define __IMX6DL_MAMOJ_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(35 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE			SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+#  define CONFIG_ENV_OFFSET		0x100000
+# endif
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"scriptaddr=0x14000000\0"	\
+	"fdt_addr_r=0x13000000\0"	\
+	"kernel_addr_r=0x10008000\0"	\
+	"fdt_high=0xffffffff\0"		\
+	"dfu_alt_info_spl=spl raw 0x2 0x400\0" \
+	"dfu_alt_info_uboot=u-boot raw 0x8a 0x11400\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+#endif
+
+/* UART */
+#define CONFIG_MXC_UART_BASE		UART3_BASE
+
+/* MMC */
+#define CONFIG_SYS_MMC_ENV_DEV		2
+
+/* Ethernet */
+#define CONFIG_FEC_MXC_PHYADDR		1
+
+/* USB */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC			(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS			0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
+
+/* Falcon */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x13000000
+#define CONFIG_CMD_SPL_WRITE_SIZE	(128 * SZ_1K)
+
+/* MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR		0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS		(CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR		0x1000  /* 2MB */
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_SP_OFFSET)
+
+/* SPL */
+#include "imx6_spl.h"
+
+#endif /* __IMX6DL_MAMOJ_CONFIG_H */
diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h
new file mode 100644
index 0000000..7ef7017
--- /dev/null
+++ b/include/configs/imx7_spl.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * SPL definitions for the i.MX7 SPL
+ *
+ * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
+ *
+ * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
+ */
+
+#ifndef __IMX7_SPL_CONFIG_H
+#define __IMX7_SPL_CONFIG_H
+
+#ifdef CONFIG_SPL
+/*
+ * see figure 6-22 in i.MX 7Dual/Solo Reference manuals:
+ *  - IMX7D/S OCRAM free area RAM (OCRAM) is from 0x00910000 to
+ *    0x00946C00.
+ *  - Set the stack at the end of the free area section, at 0x00946BB8.
+ *  - The BOOT ROM loads what they consider the firmware image
+ *    which consists of a 4K header in front of us that contains the IVT, DCD
+ *    and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000.
+ *    64KB is more then enough for the SPL.
+ */
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_STACK		0x00946BB8
+/*
+ * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
+ * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+ * boot media (given that boot media specific offset is configured properly).
+ */
+#define CONFIG_SPL_PAD_TO		0x11000
+
+/* MMC support */
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SYS_MONITOR_LEN			409600	/* 400 KB */
+#endif
+
+/* Define the payload for FAT/EXT support */
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
+# ifdef CONFIG_OF_CONTROL
+#  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot-dtb.img"
+# else
+#  define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+# endif
+#endif
+
+#define CONFIG_SPL_BSS_START_ADDR      0x88200000
+#define CONFIG_SPL_BSS_MAX_SIZE        0x100000		/* 1 MB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x88300000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000		/* 1 MB */
+
+#endif /* CONFIG_SPL */
+
+#endif /* __IMX7_SPL_CONFIG_H */
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
new file mode 100644
index 0000000..a9d99ec
--- /dev/null
+++ b/include/configs/imx8mm_evk.h
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __IMX8MM_EVK_H
+#define __IMX8MM_EVK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE			SZ_8K
+#endif
+
+#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SYS_UBOOT_BASE	\
+	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK		0x920000
+#define CONFIG_SPL_BSS_START_ADDR	0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE		SZ_8K	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR		0x930000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"script=boot.scr\0" \
+	"image=Image.itb\0" \
+	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fit=try\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"initrd_addr=0x43800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "fi;"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET               (64 * SZ_64K)
+#endif
+#define CONFIG_ENV_SIZE			SZ_4K
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		SZ_32M
+
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
+
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* USDHC */
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#endif
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
new file mode 100644
index 0000000..d4d8d20
--- /dev/null
+++ b/include/configs/imx8mq_evk.h
@@ -0,0 +1,233 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8M_EVK_H
+#define __IMX8M_EVK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SPL_MAX_SIZE		(124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x187FF0
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BSS_START_ADDR      0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE        0x2000	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE    0x80000	/* 512 KB */
+#define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR		0x182000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+#define CONFIG_ETHPRIME                 "FEC"
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_PHY_GIGE
+#define IMX_FEC_BASE			0x30BE0000
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		"clk_ignore_unused "\
+		"\0" \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+	"fdt_file=fsl-imx8mq-evk.dtb\0" \
+	"initrd_addr=0x43800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET               (64 * SZ_64K)
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+#define PHYS_SDRAM_SIZE			0xC0000000 /* 3GB DDR */
+
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					(PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
+
+/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"u-boot=> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+#define CONFIG_CMD_MMC
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_CMD_FUSE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DM_PMIC
+#endif
+
+#endif
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
new file mode 100644
index 0000000..2b8f85d
--- /dev/null
+++ b/include/configs/imx8qm_mek.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8QM_MEK_H
+#define __IMX8QM_MEK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_MAX_SIZE				(124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0x800
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION		0
+
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x013E000
+#define CONFIG_SPL_BSS_START_ADDR	0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x00120000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x3000	/* 12 KB */
+#define CONFIG_SERIAL_LPUART_BASE	0x5a060000
+#define CONFIG_MALLOC_F_ADDR		0x00120000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_OF_EMBED
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define USDHC1_BASE_ADDR                0x5B010000
+#define USDHC2_BASE_ADDR                0x5B020000
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"panel=NULL\0" \
+	"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
+	"fdt_addr=0x83000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+	"fdt_file=imx8qm-mek.dtb\0" \
+	"initrd_addr=0x83800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR         0x80200000
+
+/* Default environment is in SD */
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_OFFSET		(64 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
+#define PHYS_SDRAM_2_SIZE		0x100000000	/* 4 GB */
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+/* Networking */
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define FEC_QUIRK_ENET_MAC
+
+#endif /* __IMX8QM_MEK_H */
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
new file mode 100644
index 0000000..872805c
--- /dev/null
+++ b/include/configs/imx8qxp_mek.h
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8QXP_MEK_H
+#define __IMX8QXP_MEK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_MAX_SIZE				(124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0x800
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION		0
+
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x013E000
+#define CONFIG_SPL_BSS_START_ADDR	0x00128000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x00120000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x3000	/* 12 KB */
+#define CONFIG_SERIAL_LPUART_BASE	0x5a060000
+#define CONFIG_MALLOC_F_ADDR		0x00120000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_OF_EMBED
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define USDHC1_BASE_ADDR                0x5B010000
+#define USDHC2_BASE_ADDR                0x5B020000
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"panel=NULL\0" \
+	"console=ttyLP0,${baudrate} earlycon\0" \
+	"fdt_addr=0x83000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+	"fdt_file=imx8qxp-mek.dtb\0" \
+	"initrd_addr=0x83800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR         0x80200000
+
+/* Default environment is in SD */
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_OFFSET		(64 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
+/* LPDDR4 board total DDR is 3GB */
+#define PHYS_SDRAM_2_SIZE		0x40000000	/* 1 GB */
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+#ifndef CONFIG_DM_PCA953X
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#endif
+
+/* Networking */
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define FEC_QUIRK_ENET_MAC
+
+#endif /* __IMX8QXP_MEK_H */
diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h
new file mode 100644
index 0000000..9223fc2
--- /dev/null
+++ b/include/configs/integrator-common.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Common ARM Integrator configuration settings
+ */
+
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		0x10000000
+#define CONFIG_SYS_TIMERBASE		0x13000100	/* Timer1 */
+#define CONFIG_SYS_LOAD_ADDR		0x7fc0	/* default load address */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/*
+ * There are various dependencies on the core module (CM) fitted
+ * Users should refer to their CM user guide
+ */
+#include "armcoremodule.h"
+
+/*
+ * Initialize and remap the core module, use SPD to detect memory size
+ * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
+ * the core module has a CM_INIT register
+ * then the U-Boot initialisation code will
+ * e.g. ARM Boot Monitor or pre-loader is repeated once
+ * (to re-initialise any existing CM_INIT settings to safe values).
+ *
+ * This is usually not the desired behaviour since the platform
+ * will either reboot into the ARM monitor (or pre-loader)
+ * or continuously cycle thru it without U-Boot running,
+ * depending upon the setting of Integrator/CP switch S2-4.
+ *
+ * However it may be needed if Integrator/CP switch S2-1
+ * is set OFF to boot direct into U-Boot.
+ * In that case comment out the line below.
+ */
+#define CONFIG_CM_INIT
+#define CONFIG_CM_REMAP
+#define CONFIG_CM_SPD_DETECT
+
+/*
+ * The ARM boot monitor initializes the board.
+ * However, the default U-Boot code also performs the initialization.
+ * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
+ * - see documentation supplied with board for details of how to choose the
+ * image to run at reset/power up
+ * e.g. whether the ARM Boot Monitor runs before U-Boot
+ */
+/* #define CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * The ARM boot monitor does not relocate U-Boot.
+ * However, the default U-Boot code performs the relocation check,
+ * and may relocate the code if the memory map is changed.
+ * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
+ */
+/* #define SKIP_CONFIG_RELOCATE_UBOOT */
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
+				    CONFIG_SYS_INIT_RAM_SIZE - \
+				    GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * FLASH and environment organization
+ * Top varies according to amount fitted
+ * Reserve top 4 blocks of flash
+ * - ARM Boot Monitor
+ * - Unused
+ * - SIB block
+ * - U-Boot environment
+ */
+#define CONFIG_SYS_FLASH_BASE		0x24000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* Timeout values in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
new file mode 100644
index 0000000..4a9c60d
--- /dev/null
+++ b/include/configs/integratorap.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ * Configuration for Integrator AP board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "integrator-common.h"
+
+/* Integrator/AP-specific configuration */
+#define CONFIG_SYS_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_BOOTCOMMAND	""
+
+/* Flash settings */
+#define CONFIG_SYS_FLASH_SIZE		0x02000000 /* 32 MiB */
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_ENV_SIZE			32768
+
+/*-----------------------------------------------------------------------
+ * PCI definitions
+ */
+
+#define CONFIG_TULIP
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+
+/*-----------------------------------------------------------------------
+ * There are various dependencies on the core module (CM) fitted
+ * Users should refer to their CM user guide
+ * - when porting adjust u-boot/Makefile accordingly
+ *   to define the necessary CONFIG_ s for the CM involved
+ * see e.g. integratorcp_CM926EJ-S_config
+ */
+#include "armcoremodule.h"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
new file mode 100644
index 0000000..56931b7
--- /dev/null
+++ b/include/configs/integratorcp.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ * Configuration for Compact Integrator board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "integrator-common.h"
+
+/* Integrator CP-specific configuration */
+#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer 1 is clocked at 1Mhz */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+#define CONFIG_SMC91111_BASE    0xC8000000
+#undef CONFIG_SMC91111_EXT_PHY
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_BOOTCOMMAND "tftpboot ; bootm"
+#define CONFIG_SERVERIP 192.168.1.100
+#define CONFIG_IPADDR 192.168.1.104
+#define CONFIG_BOOTFILE "uImage"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define PHYS_FLASH_SIZE			0x01000000	/* 16MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	64
+#define CONFIG_SYS_MONITOR_LEN		0x00100000
+
+/*
+ * Move up the U-Boot & monitor area if more flash is fitted.
+ * If this U-Boot is to be run on Integrators with varying flash sizes,
+ * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
+ * register and dynamically assign CONFIG_ENV_ADDR & CONFIG_SYS_MONITOR_BASE
+ * - CONFIG_SYS_MONITOR_BASE is set to indicate that the environment is not
+ * embedded in the boot monitor(s) area
+ */
+#if ( PHYS_FLASH_SIZE == 0x04000000 )
+
+#define CONFIG_ENV_ADDR		0x27F00000
+#define CONFIG_SYS_MONITOR_BASE	0x27F40000
+
+#elif (PHYS_FLASH_SIZE == 0x02000000 )
+
+#define CONFIG_ENV_ADDR		0x25F00000
+#define CONFIG_SYS_MONITOR_BASE	0x25F40000
+
+#else
+
+#define CONFIG_ENV_ADDR		0x24F00000
+#define CONFIG_SYS_MONITOR_BASE	0x27F40000
+
+#endif
+
+#define CONFIG_ENV_SECT_SIZE	0x40000		/* 256KB */
+#define CONFIG_ENV_SIZE		8192		/* 8KB */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h
new file mode 100644
index 0000000..1ba69d9
--- /dev/null
+++ b/include/configs/iot_devkit.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef _CONFIG_IOT_DEVKIT_H_
+#define _CONFIG_IOT_DEVKIT_H_
+
+#include <linux/sizes.h>
+
+/*
+ *                         MEMORY MAP
+ *
+ * eFlash: 0x0000_0000 - 0x0008_0000 (512K)
+ *   ICCM: 0x2000_0000 - 0x2004_0000 (256K)
+ *   SRAM: 0x3000_0000 - 0x3002_0000 (128K)
+ *   DCCM: 0x8000_0000 - 0x8002_0000 (128K)
+ *     Note: only data goes here, as IFQ cannot fetch instructions from DCCM
+ *
+ *
+ *                         RAM PARTITIONING
+ *
+ *   +-----------+----------+---------------------+-------------+
+ *   | <-- Stack |  .data   | Malloc              | Environment |
+ *   +-----------+----------+---------------------+-------------+
+ *   :           :          :                     :\___________/
+ *   :           :          :                     :      |
+ *   :           :          :                     :     CONFIG_ENV_SIZE
+ *   :           :           \____________________/
+ *   :           :                     |
+ *   :           :                    CONFIG_SYS_MALLOC_LEN
+ *   :           :
+ *   :          Specified explicitly by CONFIG_SYS_INIT_SP_ADDR
+ *   :
+ *  Specified explicitly by CONFIG_SYS_SDRAM_BASE
+ *
+ *  NOTES:
+ *    - Stack starts from CONFIG_SYS_INIT_SP_ADDR and grows down,
+ *      i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing
+ *      that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on
+ *      stack any longer and values popped from stack will contain garbage
+ *      leading to unexpected behavior, typically but not limited to:
+ *        - "Returning" back to bogus caller function
+ *        - Reading data from weird addresses
+ */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define SRAM_BASE			0x30000000
+#define SRAM_SIZE			SZ_128K
+
+#define DCCM_BASE			0x80000000
+#define DCCM_SIZE			SZ_128K
+
+#define CONFIG_SYS_SDRAM_BASE		DCCM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		DCCM_SIZE
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_32K)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_64K
+#define CONFIG_SYS_BOOTM_LEN		SZ_128K
+#define CONFIG_SYS_LOAD_ADDR		SRAM_BASE
+
+#define ROM_BASE			CONFIG_SYS_MONITOR_BASE
+#define ROM_SIZE			SZ_256K
+
+#define RAM_DATA_BASE			CONFIG_SYS_INIT_SP_ADDR
+#define RAM_DATA_SIZE			CONFIG_SYS_SDRAM_SIZE - \
+					(CONFIG_SYS_INIT_SP_ADDR - \
+					CONFIG_SYS_SDRAM_BASE) - \
+					CONFIG_SYS_MALLOC_LEN - \
+					CONFIG_ENV_SIZE
+
+/*
+ * Environment
+ */
+#define CONFIG_BOOTFILE			"app.bin"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+#endif /* _CONFIG_IOT_DEVKIT_H_ */
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
new file mode 100644
index 0000000..639d87a
--- /dev/null
+++ b/include/configs/j721e_evm.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for K3 J721E EVM
+ *
+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#ifndef __CONFIG_J721E_EVM_H
+#define __CONFIG_J721E_EVM_H
+
+#include <linux/sizes.h>
+#include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
+#include <environment/ti/k3_rproc.h>
+#include <environment/ti/ufs.h>
+
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+/* DDR Configuration */
+#define CONFIG_SYS_SDRAM_BASE1		0x880000000
+
+/* SPL Loader Configuration */
+#ifdef CONFIG_TARGET_J721E_A72_EVM
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SPL_TEXT_BASE +	\
+					 CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
+#else
+/*
+ * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
+ * possible (to allow the build to go through), as this directly affects
+ * our memory footprint. The less we use for BSS the more we have available
+ * for everything else.
+ */
+#define CONFIG_SPL_BSS_MAX_SIZE		0xA000
+/*
+ * Link BSS to be within SPL in a dedicated region located near the top of
+ * the MCU SRAM, this way making it available also before relocation. Note
+ * that we are not using the actual top of the MCU SRAM as there is a memory
+ * location filled in by the boot ROM that we want to read out without any
+ * interference from the C context.
+ */
+#define CONFIG_SPL_BSS_START_ADDR	(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
+					 CONFIG_SPL_BSS_MAX_SIZE)
+/* Set the stack right below the SPL BSS section */
+#define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_BSS_START_ADDR
+/* Configure R5 SPL post-relocation malloc pool in DDR */
+#define CONFIG_SYS_SPL_MALLOC_START	0x84000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_16M
+#endif
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"tispl.bin"
+#endif
+
+#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+#define CONFIG_CQSPI_REF_CLK		133333333
+
+/* HyperFlash related configuration */
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+
+/* U-Boot general configuration */
+#define EXTRA_ENV_J721E_BOARD_SETTINGS					\
+	"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"	\
+	"findfdt=setenv fdtfile ${default_device_tree}\0"		\
+	"loadaddr=0x80080000\0"						\
+	"fdtaddr=0x82000000\0"						\
+	"overlayaddr=0x83000000\0"					\
+	"name_kern=Image\0"						\
+	"console=ttyS2,115200n8\0"					\
+	"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \
+	"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
+
+/* U-Boot MMC-specific configuration */
+#define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC				\
+	"boot=mmc\0"							\
+	"mmcdev=1\0"							\
+	"bootpart=1:2\0"						\
+	"bootdir=/boot\0"						\
+	"rd_spec=-\0"							\
+	"init_mmc=run args_all args_mmc\0"				\
+	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"get_overlay_mmc="						\
+		"fdt address ${fdtaddr};"				\
+		"fdt resize 0x100000;"					\
+		"for overlay in $name_overlays;"			\
+		"do;"							\
+		"load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && "	\
+		"fdt apply ${overlayaddr};"				\
+		"done;\0"						\
+	"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "		\
+		"${bootdir}/${name_kern}\0"
+
+#ifdef DEFAULT_RPROCS
+#undef DEFAULT_RPROCS
+#endif
+#define DEFAULT_RPROCS	""						\
+		"3 /lib/firmware/j7-main-r5f0_1-fw "			\
+		"4 /lib/firmware/j7-main-r5f1_0-fw "			\
+		"6 /lib/firmware/j7-c66_0-fw "				\
+		"7 /lib/firmware/j7-c66_1-fw "				\
+		"8 /lib/firmware/j7-c71_0-fw "
+
+/* Incorporate settings into the U-Boot environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	DEFAULT_MMC_TI_ARGS						\
+	EXTRA_ENV_J721E_BOARD_SETTINGS					\
+	EXTRA_ENV_J721E_BOARD_SETTINGS_MMC				\
+	EXTRA_ENV_RPROC_SETTINGS					\
+	DEFAULT_UFS_TI_ARGS
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_J721E_EVM_H */
diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
new file mode 100644
index 0000000..6504469
--- /dev/null
+++ b/include/configs/jetson-tk1.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Jetson TK1"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* SPI */
+#define CONFIG_SPI_FLASH_SIZE		(4 << 20)
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+/* Reserve top 1M for secure RAM */
+#define CONFIG_ARMV7_SECURE_BASE		0xfff00000
+#define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
new file mode 100644
index 0000000..5471274
--- /dev/null
+++ b/include/configs/k2e_evm.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for TI's k2e-evm
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef __CONFIG_K2E_EVM_H
+#define __CONFIG_K2E_EVM_H
+
+#include <environment/ti/spi.h>
+
+/* Platform type */
+#define CONFIG_SOC_K2E
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+#define DEFAULT_SEC_BOOT_ENV						\
+	DEFAULT_FIT_TI_ARGS						\
+	"findfdt=setenv fdtfile ${name_fdt}\0"
+#else
+#define DEFAULT_SEC_BOOT_ENV
+#endif
+
+/* U-Boot general configuration */
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
+	DEFAULT_FW_INITRAMFS_BOOT_ENV					\
+	DEFAULT_SEC_BOOT_ENV						\
+	"boot=ubi\0"							\
+	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
+	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
+	"name_fdt=keystone-k2e-evm.dtb\0"				\
+	"name_mon=skern-k2e.bin\0"					\
+	"name_ubi=k2e-evm-ubifs.ubi\0"					\
+	"name_uboot=u-boot-spi-k2e-evm.gph\0"				\
+	"name_fs=arago-console-image-k2e-evm.cpio.gz\0"
+
+#define CONFIG_ENV_SIZE				(256 << 10)  /* 256 KiB */
+#define CONFIG_ENV_OFFSET			0x100000
+
+#include <configs/ti_armv7_keystone2.h>
+
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
+/* NAND Configuration */
+#define CONFIG_SYS_NAND_PAGE_2K
+
+/* Network */
+#define CONFIG_KSNET_NETCP_V1_5
+#define CONFIG_KSNET_CPSW_NUM_PORTS	9
+#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+
+#define CONFIG_DDR_SPD
+
+#endif /* __CONFIG_K2E_EVM_H */
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
new file mode 100644
index 0000000..b39e956
--- /dev/null
+++ b/include/configs/k2g_evm.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for TI's k2g-evm
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef __CONFIG_K2G_EVM_H
+#define __CONFIG_K2G_EVM_H
+
+#include <environment/ti/mmc.h>
+#include <environment/ti/spi.h>
+
+/* Platform type */
+#define CONFIG_SOC_K2G
+
+/* U-Boot general configuration */
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
+	DEFAULT_MMC_TI_ARGS						\
+	DEFAULT_PMMC_BOOT_ENV						\
+	DEFAULT_FW_INITRAMFS_BOOT_ENV					\
+	DEFAULT_FIT_TI_ARGS						\
+	"boot=mmc\0"							\
+	"console=ttyS0,115200n8\0"					\
+	"bootpart=0:2\0"						\
+	"bootdir=/boot\0"						\
+	"rd_spec=-\0"							\
+	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
+	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
+	"findfdt="\
+		"if test $board_name = 66AK2GGP; then " \
+			 "setenv name_fdt keystone-k2g-evm.dtb; " \
+		"else if test $board_name = 66AK2GG1; then " \
+			"setenv name_fdt keystone-k2g-evm.dtb; " \
+		"else if test $board_name = 66AK2GIC; then " \
+			 "setenv name_fdt keystone-k2g-ice.dtb; " \
+		"else if test $name_fdt = undefined; then " \
+			"echo WARNING: Could not determine device tree to use;"\
+		"fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \
+	"name_mon=skern-k2g.bin\0"					\
+	"name_ubi=k2g-evm-ubifs.ubi\0"					\
+	"name_uboot=u-boot-spi-k2g-evm.gph\0"				\
+	"init_mmc=run args_all args_mmc\0"				\
+	"init_fw_rd_mmc=load mmc ${bootpart} ${rdaddr} "		\
+		"${bootdir}/${name_fw_rd}; run set_rd_spec\0"		\
+	"soc_variant=k2g\0"						\
+	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0"\
+	"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "		\
+		"${bootdir}/${name_kern}\0"				\
+	"get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\
+	"name_fs=arago-base-tisdk-image-k2g-evm.cpio\0"
+
+#ifndef CONFIG_TI_SECURE_DEVICE
+#define CONFIG_BOOTCOMMAND						\
+	"run findfdt; "							\
+	"run envboot; "							\
+	"run init_${boot}; "						\
+	"run get_mon_${boot} run_mon; "					\
+	"run set_name_pmmc get_pmmc_${boot} run_pmmc; "			\
+	"run get_kern_${boot}; "					\
+	"run init_fw_rd_${boot}; "					\
+	"run get_fdt_${boot}; "						\
+	"run run_kern"
+#else
+#define CONFIG_BOOTCOMMAND						\
+	"run findfdt; "							\
+	"run envboot; "							\
+	"run run_mon_hs; "						\
+	"run init_${boot}; "						\
+	"run get_fit_${boot}; "						\
+	"bootm ${addr_fit}#${name_fdt}"
+#endif
+
+/* NAND Configuration */
+#define CONFIG_SYS_NAND_PAGE_2K
+
+/* Network */
+#define CONFIG_KSNET_NETCP_V1_5
+#define CONFIG_KSNET_CPSW_NUM_PORTS	2
+#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+#define PHY_ANEG_TIMEOUT	10000 /* PHY needs longer aneg time */
+
+#define CONFIG_ENV_SIZE			(256 << 10)  /* 256 KiB */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CADENCE_QSPI
+#define CONFIG_CQSPI_REF_CLK 384000000
+#endif
+
+#define SPI_MTD_PARTS	KEYSTONE_SPI1_MTD_PARTS
+
+#include <configs/ti_armv7_keystone2.h>
+
+#endif /* __CONFIG_K2G_EVM_H */
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
new file mode 100644
index 0000000..d4f2e96
--- /dev/null
+++ b/include/configs/k2hk_evm.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for TI's k2hk-evm
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef __CONFIG_K2HK_EVM_H
+#define __CONFIG_K2HK_EVM_H
+
+#include <environment/ti/spi.h>
+
+/* Platform type */
+#define CONFIG_SOC_K2HK
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+#define DEFAULT_SEC_BOOT_ENV						\
+	DEFAULT_FIT_TI_ARGS						\
+	"findfdt=setenv fdtfile ${name_fdt}\0"
+#else
+#define DEFAULT_SEC_BOOT_ENV
+#endif
+
+/* U-Boot general configuration */
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
+	DEFAULT_FW_INITRAMFS_BOOT_ENV					\
+	DEFAULT_SEC_BOOT_ENV						\
+	"boot=ubi\0"							\
+	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
+	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
+	"name_fdt=keystone-k2hk-evm.dtb\0"				\
+	"name_mon=skern-k2hk.bin\0"					\
+	"name_ubi=k2hk-evm-ubifs.ubi\0"					\
+	"name_uboot=u-boot-spi-k2hk-evm.gph\0"				\
+	"name_fs=arago-console-image-k2hk-evm.cpio.gz\0"
+
+#define CONFIG_ENV_SIZE				(256 << 10)  /* 256 KiB */
+#define CONFIG_ENV_OFFSET			0x100000
+
+#include <configs/ti_armv7_keystone2.h>
+
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
+/* NAND Configuration */
+#define CONFIG_SYS_NAND_PAGE_2K
+
+/* Network */
+#define CONFIG_KSNET_NETCP_V1_0
+#define CONFIG_KSNET_CPSW_NUM_PORTS	5
+
+#define CONFIG_DDR_SPD
+
+#endif /* __CONFIG_K2HK_EVM_H */
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
new file mode 100644
index 0000000..cfdb36e
--- /dev/null
+++ b/include/configs/k2l_evm.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for TI's k2l-evm
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef __CONFIG_K2L_EVM_H
+#define __CONFIG_K2L_EVM_H
+
+#include <environment/ti/spi.h>
+
+/* Platform type */
+#define CONFIG_SOC_K2L
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+#define DEFAULT_SEC_BOOT_ENV						\
+	DEFAULT_FIT_TI_ARGS						\
+	"findfdt=setenv fdtfile ${name_fdt}\0"
+#else
+#define DEFAULT_SEC_BOOT_ENV
+#endif
+
+/* U-Boot general configuration */
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
+	DEFAULT_FW_INITRAMFS_BOOT_ENV					\
+	DEFAULT_SEC_BOOT_ENV						\
+	"boot=ubi\0"							\
+	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
+	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0"	\
+	"name_fdt=keystone-k2l-evm.dtb\0"				\
+	"name_mon=skern-k2l.bin\0"					\
+	"name_ubi=k2l-evm-ubifs.ubi\0"					\
+	"name_uboot=u-boot-spi-k2l-evm.gph\0"				\
+	"name_fs=arago-console-image-k2l-evm.cpio.gz\0"
+
+#define CONFIG_ENV_SIZE				(256 << 10)  /* 256 KiB */
+#define CONFIG_ENV_OFFSET			0x100000
+
+#include <configs/ti_armv7_keystone2.h>
+
+#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS
+
+/* NAND Configuration */
+#define CONFIG_SYS_NAND_PAGE_4K
+
+/* Network */
+#define CONFIG_KSNET_NETCP_V1_5
+#define CONFIG_KSNET_CPSW_NUM_PORTS	5
+#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+
+#endif /* __CONFIG_K2L_EVM_H */
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
new file mode 100644
index 0000000..e3a219c
--- /dev/null
+++ b/include/configs/kc1.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Amazon Kindle Fire (first generation) codename kc1 config
+ *
+ * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+/*
+ * Build
+ */
+
+/*
+ * CPU
+ */
+
+#define CONFIG_SYS_L2_PL310		1
+#define CONFIG_SYS_PL310_BASE		0x48242000
+
+/*
+ * Board
+ */
+
+/*
+ * Clocks
+ */
+
+#define CONFIG_SYS_TIMERBASE	GPT2_BASE
+#define CONFIG_SYS_PTV		2
+
+/*
+ * DRAM
+ */
+
+/*
+ * Memory
+ */
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 + CONFIG_ENV_SIZE)
+
+/*
+ * I2C
+ */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * Power
+ */
+
+#define CONFIG_TWL6030_POWER
+
+/*
+ * Input
+ */
+
+#define CONFIG_TWL6030_INPUT
+
+/*
+ * SPL
+ */
+
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		(512 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(1024 * 1024)
+
+/*
+ * Console
+ */
+
+#define CONFIG_SYS_CBSIZE	512
+
+/*
+ * Serial
+ */
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 4800, 9600, 19200, 38400, 57600, \
+					  115200 }
+
+/*
+ * USB gadget
+ */
+
+/*
+ * Environment
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_addr_r=0x82000000\0" \
+	"loadaddr=0x82000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"fdtaddr=0x88000000\0" \
+	"ramdisk_addr_r=0x88080000\0" \
+	"pxefile_addr_r=0x80100000\0" \
+	"scriptaddr=0x80000000\0" \
+	"bootm_size=0x10000000\0" \
+	"boot_mmc_dev=0\0" \
+	"kernel_mmc_part=7\0" \
+	"recovery_mmc_part=5\0" \
+	"fdtfile=omap4-kc1.dtb\0" \
+	"bootfile=/boot/extlinux/extlinux.conf\0" \
+	"bootargs=console=ttyO2,115200 mem=512M\0"
+
+/*
+ * ATAGs
+ */
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/*
+ * Boot
+ */
+
+#define CONFIG_SYS_LOAD_ADDR	0x82000000
+
+#define CONFIG_BOOTCOMMAND \
+	"setenv boot_mmc_part ${kernel_mmc_part}; " \
+	"if test reboot-${reboot-mode} = reboot-r; then " \
+	"echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; " \
+	"if test reboot-${reboot-mode} = reboot-b; then " \
+	"echo fastboot; fastboot 0; fi; " \
+	"part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \
+	"part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \
+	"mmc dev ${boot_mmc_dev}; " \
+	"mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \
+	"bootm ${kernel_addr_r};"
+
+/*
+ * Defaults
+ */
+
+#include <config_defaults.h>
+
+#endif
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
new file mode 100644
index 0000000..8433d8e
--- /dev/null
+++ b/include/configs/km/keymile-common.h
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008-2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#ifndef __CONFIG_KEYMILE_H
+#define __CONFIG_KEYMILE_H
+
+/*
+ * Miscellaneous configurable options
+ */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_MAXARGS		32 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_HUSH_INIT_VAR
+
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* UBI Support for all Keymile boards */
+#define CONFIG_MTD_CONCAT
+
+#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
+#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
+	"actual_bank=0\0"
+#endif
+
+#ifndef CONFIG_KM_DEF_NETDEV
+#define CONFIG_KM_DEF_NETDEV	\
+	"netdev=eth0\0"
+#endif
+
+#ifndef CONFIG_KM_UBI_PARTITION_NAME_BOOT
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
+#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+
+#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS
+#define CONFIG_KM_UBI_PART_BOOT_OPTS		""
+#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */
+
+#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP
+/* one flash chip only called boot */
+/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+# define CONFIG_KM_UBI_LINUX_MTD					\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT			\
+	CONFIG_KM_UBI_PART_BOOT_OPTS
+# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
+	"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0"
+#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */
+/* two flash chips called boot and app */
+/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+/* app:  CONFIG_KM_UBI_PARTITION_NAME_APP */
+# define CONFIG_KM_UBI_LINUX_MTD					\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT			\
+	CONFIG_KM_UBI_PART_BOOT_OPTS " "				\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP
+# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
+	"ubiattach=if test ${boot_bank} -eq 0; then; "			\
+	"ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "; else; "	\
+	"ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0"
+#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */
+
+#ifdef CONFIG_NAND_ECC_BCH
+#define CONFIG_KM_UIMAGE_NAME "ecc_bch_uImage\0"
+#define CONFIG_KM_ECC_MODE    " eccmode=bch"
+#else
+#define CONFIG_KM_UIMAGE_NAME "uImage\0"
+#define CONFIG_KM_ECC_MODE
+#endif
+
+/*
+ * boottargets
+ * - set 'subbootcmds'
+ * - set 'bootcmd' and 'altbootcmd'
+ * available targets:
+ * - 'release': for a standalone system		kernel/rootfs from flash
+ */
+#define CONFIG_KM_DEF_ENV_BOOTTARGETS					\
+	"subbootcmds=ubiattach ubicopy checkfdt cramfsloadfdt "		\
+		"set_fdthigh cramfsloadkernel flashargs add_default "	\
+		"addpanic boot\0"					\
+	"develop="							\
+		"tftp 200000 scripts/develop-${arch}.txt && "		\
+		"env import -t 200000 ${filesize} && "			\
+		"run setup_debug_env\0"					\
+	"ramfs="							\
+		"tftp 200000 scripts/ramfs-${arch}.txt && "		\
+		"env import -t 200000 ${filesize} && "			\
+		"run setup_debug_env\0"					\
+	""
+
+/*
+ * bootargs
+ * - modify 'bootargs'
+ *
+ * - 'add_default': default bootargs common for all arm/ppc boards
+ * - 'addpanic': add kernel panic options
+ * - 'flashargs': defaults arguments for flash base boot
+ *
+ */
+#define CONFIG_KM_DEF_ENV_BOOTARGS					\
+	"add_default="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off:"				\
+		" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}"	\
+		" mem=${kernelmem} init=${init}"			\
+		CONFIG_KM_ECC_MODE					\
+		" phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\
+		" " CONFIG_KM_UBI_LINUX_MTD " "				\
+		CONFIG_KM_DEF_BOOT_ARGS_CPU				\
+		"\0"							\
+	"addpanic="							\
+		"setenv bootargs ${bootargs} panic=1 panic_on_oops=1\0"	\
+	"flashargs="							\
+		"setenv bootargs "					\
+		"root=mtdblock:rootfs${boot_bank} "			\
+		"rootfstype=squashfs ro\0"				\
+	""
+
+/*
+ * flash_boot
+ * - commands for booting from flash
+ *
+ * - 'cramfsloadkernel': copy kernel from a cramfs to ram
+ * - 'ubiattach': attach ubi partition
+ * - 'ubicopy': copy ubi volume to ram
+ *              - volume names: bootfs0, bootfs1, bootfs2, ...
+ *
+ * processor specific settings
+ * - 'cramfsloadfdt': copy fdt from a cramfs to ram
+ */
+#define CONFIG_KM_DEF_ENV_FLASH_BOOT					\
+	"cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0"		\
+	"cramfsloadkernel=cramfsload ${load_addr_r} ${uimage}\0"	\
+	"ubicopy=ubi read "__stringify(CONFIG_KM_CRAMFS_ADDR)		\
+			" bootfs${boot_bank}\0"				\
+	"uimage=" CONFIG_KM_UIMAGE_NAME					\
+	CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
+
+/*
+ * constants
+ * - KM specific constants and commands
+ *
+ * - 'default': setup default environment
+ */
+#define CONFIG_KM_DEF_ENV_CONSTANTS					\
+	"backup_bank=0\0"						\
+	"release=run newenv; reset\0"					\
+	"pnvramsize=" __stringify(CONFIG_KM_PNVRAM) "\0"		\
+	"testbootcmd=setenv boot_bank ${test_bank}; "			\
+		"run ${subbootcmds}; reset\0"				\
+	""
+
+#ifndef CONFIG_KM_DEF_ENV
+#define CONFIG_KM_DEF_ENV	\
+	CONFIG_KM_DEF_ENV_BOOTPARAMS					\
+	CONFIG_KM_DEF_NETDEV						\
+	CONFIG_KM_DEF_ENV_CPU						\
+	CONFIG_KM_DEF_ENV_BOOTTARGETS					\
+	CONFIG_KM_DEF_ENV_BOOTARGS					\
+	CONFIG_KM_DEF_ENV_FLASH_BOOT					\
+	CONFIG_KM_DEF_ENV_CONSTANTS					\
+	"altbootcmd=run bootcmd\0"					\
+	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
+	"bootcmd=km_checkbidhwk &&  "					\
+		"setenv bootcmd \'if km_checktestboot; then; "          \
+				"setenv boot_bank ${test_bank}; else; " \
+				"setenv boot_bank ${actual_bank}; fi;"  \
+			"run ${subbootcmds}; reset\' && "		\
+		"setenv altbootcmd \'setenv boot_bank ${backup_bank}; "	\
+			"run ${subbootcmds}; reset\' && "		\
+		"saveenv && saveenv && boot\0"				\
+	"cramfsloadfdt="						\
+		"cramfsload ${fdt_addr_r} "				\
+		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
+	"fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0"		\
+	"init=/sbin/init-overlay.sh\0"					\
+	"load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0"		\
+	"load=tftpboot ${load_addr_r} ${u-boot}\0"			\
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
+	""
+#endif /* CONFIG_KM_DEF_ENV */
+
+#endif /* __CONFIG_KEYMILE_H */
diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h
new file mode 100644
index 0000000..9aaea27
--- /dev/null
+++ b/include/configs/km/km-mpc8309.h
@@ -0,0 +1,135 @@
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 family */
+
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN		66000000
+#define CONFIG_SYS_CLK_FREQ		66000000
+#define CONFIG_83XX_PCICLK		66000000
+
+/* QE microcode/firmware address */
+/* between the u-boot partition and env */
+#ifndef CONFIG_SYS_QE_FW_ADDR
+#define CONFIG_SYS_QE_FW_ADDR   0xF00C0000
+#endif
+
+/*
+ * System IO Config
+ */
+/* 0x14000180 SICR_1 */
+#define CONFIG_SYS_SICRL (0			\
+		| SICR_1_UART1_UART1RTS		\
+		| SICR_1_I2C_CKSTOP		\
+		| SICR_1_IRQ_A_IRQ		\
+		| SICR_1_IRQ_B_IRQ		\
+		| SICR_1_GPIO_A_GPIO		\
+		| SICR_1_GPIO_B_GPIO		\
+		| SICR_1_GPIO_C_GPIO		\
+		| SICR_1_GPIO_D_GPIO		\
+		| SICR_1_GPIO_E_GPIO		\
+		| SICR_1_GPIO_F_GPIO		\
+		| SICR_1_USB_A_UART2S		\
+		| SICR_1_USB_B_UART2RTS		\
+		| SICR_1_FEC1_FEC1		\
+		| SICR_1_FEC2_FEC2		\
+		)
+
+/* 0x00080400 SICR_2 */
+#define CONFIG_SYS_SICRH (0			\
+		| SICR_2_FEC3_FEC3		\
+		| SICR_2_HDLC1_A_HDLC1		\
+		| SICR_2_ELBC_A_LA		\
+		| SICR_2_ELBC_B_LCLK		\
+		| SICR_2_HDLC2_A_HDLC2		\
+		| SICR_2_USB_D_GPIO		\
+		| SICR_2_PCI_PCI		\
+		| SICR_2_HDLC1_B_HDLC1		\
+		| SICR_2_HDLC1_C_HDLC1		\
+		| SICR_2_HDLC2_B_GPIO		\
+		| SICR_2_HDLC2_C_HDLC2		\
+		| SICR_2_QUIESCE_B		\
+		)
+
+/* GPR_1 */
+#define CONFIG_SYS_GPR1  0x50008060
+
+#define CONFIG_SYS_GP1DIR 0x00000000
+#define CONFIG_SYS_GP1ODR 0x00000000
+#define CONFIG_SYS_GP2DIR 0xFF000000
+#define CONFIG_SYS_GP2ODR 0x00000000
+
+#define CONFIG_SYS_DDRCDR (\
+	DDRCDR_EN | \
+	DDRCDR_PZ_MAXZ | \
+	DDRCDR_NZ_MAXZ | \
+	DDRCDR_M_ODR)
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+					 SDRAM_CFG_32_BE | \
+					 SDRAM_CFG_SREN | \
+					 SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ODT_RD_NEVER | \
+					 CSCONFIG_ODT_WR_ONLY_CURRENT | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE	0x47860242
+#define CONFIG_SYS_DDR_MODE2	0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/* ethernet port connected to piggy (UEC2) */
+#define CONFIG_HAS_ETH1
+#define CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM		2       /* UCC3 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK12
+#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	0
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h
new file mode 100644
index 0000000..d7186ab
--- /dev/null
+++ b/include/configs/km/km-mpc832x.h
@@ -0,0 +1,90 @@
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM8321	/* Keymile PBEC8321 board specific */
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN		66000000
+#define CONFIG_SYS_CLK_FREQ		66000000
+#define CONFIG_83XX_PCICLK		66000000
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH1		/* GETH1 */
+#define UEC_VERBOSE_DEBUG	1
+
+#define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	0
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
+
+#define CONFIG_SYS_DDRCDR (\
+	DDRCDR_EN | \
+	DDRCDR_PZ_MAXZ | \
+	DDRCDR_NZ_MAXZ | \
+	DDRCDR_M_ODR)
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+					 SDRAM_CFG_32_BE | \
+					 SDRAM_CFG_SREN | \
+					 SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ODT_WR_CFG | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE	0x47860242
+#define CONFIG_SYS_DDR_MODE2	0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h
new file mode 100644
index 0000000..bdbb8bf
--- /dev/null
+++ b/include/configs/km/km-mpc8360.h
@@ -0,0 +1,90 @@
+/* KMBEC FPGA (PRIO) */
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	64
+
+/*
+ * High Level Configuration Options
+ */
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH1		/* GETH1 */
+#define UEC_VERBOSE_DEBUG	1
+
+#define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	0
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+
+/*
+ * System IO Setup
+ */
+#define CONFIG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)
+
+/**
+ * DDR RAM settings
+ */
+#define CONFIG_SYS_DDR_SDRAM_CFG (\
+	SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+	SDRAM_CFG_SREN | \
+	SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+
+#define CONFIG_SYS_DDR_CLK_CNTL (\
+	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CONFIG_SYS_DDR_INTERVAL (\
+	(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+	(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_BNDS			0x0000007f
+
+#define CONFIG_SYS_DDRCDR (\
+	DDRCDR_EN | \
+	DDRCDR_Q_DRN)
+#define CONFIG_SYS_DDR_MODE		0x47860452
+#define CONFIG_SYS_DDR_MODE2		0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 (\
+	(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+	(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+	(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+	(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+	(0 << TIMING_CFG0_WWT_SHIFT) | \
+	(0 << TIMING_CFG0_RRT_SHIFT) | \
+	(0 << TIMING_CFG0_WRT_SHIFT) | \
+	(0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 (\
+	(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+	(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+	(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+	(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+	(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+	(5 << TIMING_CFG2_CPO_SHIFT) | \
+	(0 << TIMING_CFG2_ADD_LAT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3			0x00000000
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+
+/*
+ * PAXE on the local bus CS3
+ */
+#define CONFIG_SYS_PAXE_BASE		0xA0000000
+#define CONFIG_SYS_PAXE_SIZE		256
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
new file mode 100644
index 0000000..c06143c
--- /dev/null
+++ b/include/configs/km/km-mpc83xx.h
@@ -0,0 +1,156 @@
+/*
+ * Internal Definitions
+ */
+#define BOOTFLASH_START	0xF0000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
+
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CFG_83XX_DDR_USES_CS0
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_DDR_II
+#define CONFIG_SYS_DDR_SIZE		2048 /* MB */
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_FLASH_BASE		0xF0000000
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/* Reserve 768 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Size  Device
+ * ---- ---     ------- ------  -----  ------
+ *  0   Local   GPCM    16 bit  256MB FLASH
+ *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
+ *
+ */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1   /* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_NUM_I2C_BUSES	4
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	200000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	200000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
+		{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+		{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+		{1, {I2C_NULL_HOP} } }
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * Environment
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#ifndef CONFIG_ENV_ADDR
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+					CONFIG_SYS_MONITOR_LEN)
+#endif
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+#ifndef CONFIG_ENV_OFFSET
+#define CONFIG_ENV_OFFSET	(CONFIG_SYS_MONITOR_LEN)
+#endif
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else /* CFG_SYS_RAMBOOT */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif /* CFG_SYS_RAMBOOT */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_KM_DEF_ENV						 \
+	CONFIG_KM_DEF_ARCH						 \
+	"newenv="							 \
+		"prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \
+		"era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0"	 \
+	"unlock=yes\0"							 \
+	""
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#endif
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"UEC0"
diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h
new file mode 100644
index 0000000..20b596f
--- /dev/null
+++ b/include/configs/km/km-powerpc.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#ifndef __CONFIG_KEYMILE_POWERPC_H
+#define __CONFIG_KEYMILE_POWERPC_H
+
+/* Do boardspecific init for all boards */
+
+#define CONFIG_JFFS2_CMDLINE
+
+/* EEprom support 24C08, 24C16, 24C64 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3  /* 8 Byte write page */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define CONFIG_ENV_SIZE		0x04000		/* Size of Environment */
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000	/* memtest works on */
+
+#define CONFIG_SYS_MEMTEST_END	0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+
+/* Reserve 4 MB for malloc */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE	0x0
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM */
+#define CONFIG_PRAM		((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
+
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"u-boot="CONFIG_HOSTNAME "/u-boot.bin\0"		\
+	"update="							\
+		"protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\
+		"erase " __stringify(BOOTFLASH_START) "  +${filesize} && "\
+		"cp.b ${load_addr_r} " __stringify(BOOTFLASH_START)	\
+		"  ${filesize} && "					\
+		"protect on " __stringify(BOOTFLASH_START) "  +${filesize}\0"\
+	"set_fdthigh=true\0"						\
+	"checkfdt=true\0"						\
+	""
+
+#endif /* __CONFIG_KEYMILE_POWERPC_H */
diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h
new file mode 100644
index 0000000..829a5c7
--- /dev/null
+++ b/include/configs/km/km_arm.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2010-2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+/*
+ * for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
+ */
+
+#ifndef _CONFIG_KM_ARM_H
+#define _CONFIG_KM_ARM_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KW88F6281		/* SOC Name */
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_KM_KIRKWOOD
+
+#define CONFIG_NAND_ECC_BCH
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+
+/* Reserve 4 MB for malloc */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#include "asm/arch/config.h"
+
+#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
+#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU					\
+		"bootcountaddr=${bootcountaddr} ${mtdparts}"		\
+		" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
+
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"u-boot="CONFIG_HOSTNAME "/u-boot.kwb\0"		\
+	CONFIG_KM_UPDATE_UBOOT						\
+	"set_fdthigh=setenv fdt_high ${kernelmem}\0"			\
+	"checkfdt="							\
+		"if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; "	\
+		"then true; else setenv cramfsloadfdt true; "		\
+		"setenv boot bootm ${load_addr_r}; "			\
+		"echo No FDT found, booting with the kernel "		\
+		"appended one; fi\0"					\
+	""
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG		/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */
+
+/*
+ * NAND Flash configuration
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/*
+ * Other required minimal configurations
+ */
+
+/*
+ * Ethernet Driver configuration
+ */
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer autoneg timeout */
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+
+/*
+ * I2C related stuff
+ */
+#undef CONFIG_I2C_MVTWSI
+#define CONFIG_SYS_I2C
+#define	CONFIG_SYS_I2C_SOFT	/* I2C bit-banged	*/
+#define CONFIG_SYS_I2C_INIT_BOARD
+
+#define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
+#define CONFIG_SYS_NUM_I2C_BUSES	6
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
+				}
+
+#ifndef __ASSEMBLY__
+#include <asm/arch/gpio.h>
+extern void __set_direction(unsigned pin, int high);
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#define KM_KIRKWOOD_SDA_PIN	8
+#define KM_KIRKWOOD_SCL_PIN	9
+#define KM_KIRKWOOD_SOFT_I2C_GPIOS	0x0300
+#define KM_KIRKWOOD_ENV_WP	38
+
+#define I2C_ACTIVE	__set_direction(KM_KIRKWOOD_SDA_PIN, 0)
+#define I2C_TRISTATE	__set_direction(KM_KIRKWOOD_SDA_PIN, 1)
+#define I2C_READ	(kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
+#define I2C_SDA(bit)	kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
+#define I2C_SCL(bit)	kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
+#endif
+
+#define I2C_DELAY	udelay(1)
+#define I2C_SOFT_DECLARATIONS
+
+#define	CONFIG_SYS_I2C_SOFT_SLAVE	0x0
+#define	CONFIG_SYS_I2C_SOFT_SPEED	100000
+
+/* EEprom support 24C128, 24C256 valid for environment eeprom */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6 /* 64 Byte write page */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/*
+ *  Environment variables configurations
+ */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_OFFSET		0xc0000     /* no bracets! */
+#define CONFIG_ENV_SIZE			0x02000     /* Size of Environment */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_TOTAL_SIZE		0x20000     /* no bracets! */
+#else
+#define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_EEPROM_WREN
+#define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
+#define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
+#define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */
+#define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#endif
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#define KM_FLASH_GPIO_PIN	16
+
+#define	CONFIG_KM_UPDATE_UBOOT						\
+	"update="							\
+		"sf probe 0;sf erase 0 +${filesize};"			\
+		"sf write ${load_addr_r} 0 ${filesize};\0"
+
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=sf probe 0;"						\
+		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
+		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
+#else
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=setenv addr 0x100000 && "				\
+		"i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; "  \
+		"mw.b ${addr} 0 4 && "					\
+		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
+		" ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && "	\
+		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
+		" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
+#endif
+
+#ifndef CONFIG_KM_BOARD_EXTRA_ENV
+#define CONFIG_KM_BOARD_EXTRA_ENV       ""
+#endif
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_BOARD_EXTRA_ENV					\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_NEW_ENV						\
+	"arch=arm\0"							\
+	""
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/* address for the bootcount (taken from end of RAM) */
+#define BOOTCOUNT_ADDR          (CONFIG_KM_RESERVED_PRAM)
+
+/* enable POST tests */
+#define CONFIG_POST	(CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST_SKIP_ENV_FLAGS
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS
+
+#endif /* _CONFIG_KM_ARM_H */
diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h
new file mode 100644
index 0000000..6fce83c
--- /dev/null
+++ b/include/configs/km_kirkwood.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2011-2012
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+ */
+
+/*
+ * for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
+ */
+
+#ifndef _CONFIG_KM_KIRKWOOD_H
+#define _CONFIG_KM_KIRKWOOD_H
+
+/* KM_KIRKWOOD */
+#if defined(CONFIG_KM_KIRKWOOD)
+#define CONFIG_HOSTNAME			"km_kirkwood"
+#define CONFIG_KM_DISABLE_PCIE
+
+/* KM_KIRKWOOD_PCI */
+#elif defined(CONFIG_KM_KIRKWOOD_PCI)
+#define CONFIG_HOSTNAME			"km_kirkwood_pci"
+#define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
+#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+
+/* KM_KIRKWOOD_128M16 */
+#elif defined(CONFIG_KM_KIRKWOOD_128M16)
+#define CONFIG_HOSTNAME			"km_kirkwood_128m16"
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_KM_DISABLE_PCIE
+
+/* KM_NUSA / KM_SUGP1 */
+#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
+
+# if defined(CONFIG_KM_NUSA)
+#define CONFIG_HOSTNAME			"kmnusa"
+# elif defined(CONFIG_KM_SUGP1)
+#define CONFIG_HOSTNAME			"kmsugp1"
+#define KM_PCIE_RESET_MPP7
+#endif
+
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+
+/* KM_MGCOGE3UN */
+#elif defined(CONFIG_KM_MGCOGE3UN)
+#define CONFIG_HOSTNAME			"mgcoge3un"
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
+#define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
+#define CONFIG_KM_DISABLE_PCIE
+
+/* KMCOGE5UN */
+#elif defined(CONFIG_KM_COGE5UN)
+#undef	CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
+#define CONFIG_HOSTNAME			"kmcoge5un"
+#define CONFIG_KM_DISABLE_PCIE
+
+/* KM_SUV31 */
+#elif defined(CONFIG_KM_SUV31)
+#define CONFIG_HOSTNAME			"kmsuv31"
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
+#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+#else
+#error ("Board unsupported")
+#endif
+
+/* include common defines/options for all arm based Keymile boards */
+#include "km/km_arm.h"
+
+#if defined(CONFIG_KM_PIGGY4_88E6352)
+/*
+ * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
+ * an Marvell 88E6352 simple switch.
+ * In this case we have to change the default settings for the etherent mac.
+ * There is NO ethernet phy. The ARM and Switch are conencted directly over
+ * RGMII in MAC-MAC mode
+ * In this case 1GBit full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE		( \
+	MVGBE_FORCE_LINK_PASS			    | \
+	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
+	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
+	MVGBE_ADV_NO_FLOW_CTRL			    | \
+	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
+	MVGBE_FORCE_BP_MODE_NO_JAM		    | \
+	(1 << 9) /* Reserved bit has to be 1 */	| \
+	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
+	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
+	MVGBE_DTE_ADV_0				        | \
+	MVGBE_MIIPHY_MAC_MODE			    | \
+	MVGBE_AUTO_NEG_NO_CHANGE		    | \
+	MVGBE_MAX_RX_PACKET_1552BYTE		| \
+	MVGBE_CLR_EXT_LOOPBACK			    | \
+	MVGBE_SET_FULL_DUPLEX_MODE		    | \
+	MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
+	MVGBE_SET_GMII_SPEED_TO_1000	    |\
+	MVGBE_SET_MII_SPEED_TO_100)
+
+#endif
+
+#ifdef CONFIG_KM_PIGGY4_88E6061
+/*
+ * Some keymile boards like mgcoge3un have their PIGGY4 connected via
+ * an Marvell 88E6061 simple switch.
+ * In this case we have to change the default settings for the
+ * ethernet phy connected to the kirkwood.
+ * In this case 100MB full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE		( \
+	MVGBE_FORCE_LINK_PASS			| \
+	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
+	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
+	MVGBE_ADV_NO_FLOW_CTRL			| \
+	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
+	MVGBE_FORCE_BP_MODE_NO_JAM		| \
+	(1 << 9) /* Reserved bit has to be 1 */	| \
+	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
+	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
+	MVGBE_DTE_ADV_0				| \
+	MVGBE_MIIPHY_MAC_MODE			| \
+	MVGBE_AUTO_NEG_NO_CHANGE		| \
+	MVGBE_MAX_RX_PACKET_1552BYTE		| \
+	MVGBE_CLR_EXT_LOOPBACK			| \
+	MVGBE_SET_FULL_DUPLEX_MODE		| \
+	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
+	MVGBE_SET_GMII_SPEED_TO_10_100	|\
+	MVGBE_SET_MII_SPEED_TO_100)
+#endif
+
+#ifdef CONFIG_KM_DISABLE_PCIE
+#undef  CONFIG_KIRKWOOD_PCIE_INIT
+#endif
+
+#endif /* _CONFIG_KM_KIRKWOOD */
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h
new file mode 100644
index 0000000..fc78b27
--- /dev/null
+++ b/include/configs/kmcoge5ne.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
+ * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_HOSTNAME		"kmcoge5ne"
+#define CONFIG_KM_BOARD_NAME	"kmcoge5ne"
+#define CONFIG_KM_DEF_NETDEV	"netdev=eth1\0"
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS				1
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
+#define CONFIG_KM_UBI_PARTITION_NAME_APP	"ubi1"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8360.h"
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN		66000000
+#define CONFIG_SYS_CLK_FREQ		66000000
+#define CONFIG_83XX_PCICLK		66000000
+
+/**
+ * KMCOGE5NE has 512 MB RAM
+ */
+#define CONFIG_SYS_DDR_CS0_CONFIG (\
+	CSCONFIG_EN | \
+	CSCONFIG_AP | \
+	CSCONFIG_ODT_WR_ONLY_CURRENT | \
+	CSCONFIG_BANK_BIT_3 | \
+	CSCONFIG_ROW_BIT_13 | \
+	CSCONFIG_COL_BIT_10)
+
+/*
+ * BFTIC3 on the local bus CS4
+ */
+#define CONFIG_SYS_BFTIC3_BASE			0xB0000000
+#define CONFIG_SYS_BFTIC3_SIZE			256
+
+/* enable POST tests */
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
+#define CPM_POST_WORD_ADDR  CONFIG_SYS_MEMTEST_END
+#define CONFIG_TESTPIN_REG  gprt3	/* for kmcoge5ne */
+#define CONFIG_TESTPIN_MASK 0x20	/* for kmcoge5ne */
+
+#endif /* CONFIG */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
new file mode 100644
index 0000000..bfa7ca2
--- /dev/null
+++ b/include/configs/kmeter1.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
+ * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_HOSTNAME		"kmeter1"
+#define CONFIG_KM_BOARD_NAME   "kmeter1"
+#define CONFIG_KM_DEF_NETDEV	"netdev=eth2\0"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8360.h"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10 | \
+					 CSCONFIG_ODT_WR_ONLY_CURRENT)
+#endif /* CONFIG */
diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h
new file mode 100644
index 0000000..67e864f
--- /dev/null
+++ b/include/configs/kmopti2.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME	"kmopti2"
+#define CONFIG_HOSTNAME		"kmopti2"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h
new file mode 100644
index 0000000..75480a8
--- /dev/null
+++ b/include/configs/kmp204x.h
@@ -0,0 +1,442 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_KMCOGE4)
+#define CONFIG_HOSTNAME		"kmcoge4"
+#define CONFIG_KM_BOARD_NAME	"kmcoge4"
+
+#else
+#error ("Board not supported")
+#endif
+
+#define CONFIG_KMP204X
+
+#define CONFIG_KM_DEF_NETDEV	"netdev=eth0\0"
+
+/* an additionnal option is required for UBI as subpage access is
+ * supported in u-boot
+ */
+#define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
+
+#define CONFIG_NAND_ECC_BCH
+
+/* common KM defines */
+#include "km/keymile-common.h"
+
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+
+/* Environment in SPI Flash */
+#define CONFIG_ENV_OFFSET               0x100000	/* 1MB for u-boot */
+#define CONFIG_ENV_SIZE			0x004000	/* 16K env */
+#define CONFIG_ENV_SECT_SIZE            0x010000
+#define CONFIG_ENV_OFFSET_REDUND	0x110000
+#define CONFIG_ENV_TOTAL_SIZE		0x020000
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS	/* POST memory regions test */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
+		CONFIG_RAMBOOT_TEXT_BASE)
+#define CONFIG_SYS_L3_SIZE		(1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x54
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE	0x0
+/* pseudo-non volatile RAM [hex] */
+#define CONFIG_KM_PNVRAM	0x80000
+/* physical RAM MTD size [hex] */
+#define CONFIG_KM_PHRAM		0x100000
+/* reserved pram area at the end of memory [hex]
+ * u-boot reserves some memory for the MP boot page
+ */
+#define CONFIG_KM_RESERVED_PRAM	0x1000
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM
+ */
+#define CONFIG_PRAM		((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
+
+#define CONFIG_KM_CRAMFS_ADDR	0x2000000
+#define CONFIG_KM_KERNEL_ADDR	0x1000000	/* max kernel size 15.5Mbytes */
+#define CONFIG_KM_FDT_ADDR	0x1F80000	/* max dtb    size  0.5Mbytes */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
+#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_8 | LCRR_EADC_2)
+
+/* Nand Flash */
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+
+#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB	      /* length 256K */ \
+			       | OR_FCM_BCTLD	/* LBCTL not ass */	\
+			       | OR_FCM_SCY_1	/* 1 clk wait cycle */	\
+			       | OR_FCM_RST	/* 1 clk read setup */	\
+			       | OR_FCM_PGS	/* Large page size */	\
+			       | OR_FCM_CST)	/* 0.25 command setup */
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* QRIO FPGA */
+#define CONFIG_SYS_QRIO_BASE		0xfb000000
+#define CONFIG_SYS_QRIO_BASE_PHYS	0xffb000000ull
+
+#define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
+				| BR_PS_8	/* Port Size 8 bits */ \
+				| BR_DECC_OFF	/* no error corr */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+
+#define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB	/* length 64K */ \
+				| OR_GPCM_BCTLD /* no LCTL assert */ \
+				| OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
+				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
+				| OR_GPCM_TRLX /* relaxed tmgs */ \
+				| OR_GPCM_EAD) /* extra bus clk cycles */
+
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
+
+#define CONFIG_MISC_INIT_F
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0) / 2)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR + 0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR + 0x11D600)
+
+#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
+
+/* I2C */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED		100000 /* deblocking */
+#define CONFIG_SYS_NUM_I2C_BUSES	3
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_FSL		/* Use FSL I2C driver */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
+				}
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#endif
+
+#define CONFIG_KM_IVM_BUS		1	/* I2C1 (Mux-Port 1)*/
+
+/*
+ * eSPI - Enhanced SPI
+ */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver
+ * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
+ * ucode is stored after env, so we got 0x120000.
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR	0x120000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#define CONFIG_PHYLIB_10G
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x11
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_ETHPRIME		"FM1@DTSEC5"
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Hardware Watchdog
+ */
+#define CONFIG_WATCHDOG			/* enable CPU watchdog */
+#define CONFIG_WATCHDOG_PRESC 34	/* wdog prescaler 2^(64-34) (~10min) */
+#define CONFIG_WATCHDOG_RC WRC_CHIP	/* reset chip on watchdog event */
+
+/*
+ * additionnal command line configuration.
+ */
+
+/* we don't need flash support */
+#undef CONFIG_JFFS2_CMDLINE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+#define __USB_PHY_TYPE	utmi
+#define CONFIG_USB_EHCI_FSL
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
+
+/* FIXME: FDT_ADDR is unspecified */
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
+	"cramfsloadfdt="						\
+		"cramfsload ${fdt_addr_r} "				\
+		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
+	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
+	"u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0"		\
+	"update="							\
+		"sf probe 0;sf erase 0 +${filesize};"			\
+		"sf write ${load_addr_r} 0 ${filesize};\0"		\
+	"set_fdthigh=true\0"						\
+	"checkfdt=true\0"						\
+	""
+
+#define CONFIG_HW_ENV_SETTINGS						\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"			\
+	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
+	"usb_dr_mode=host\0"
+
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=sf probe 0;"						\
+		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
+		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
+
+/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_DEF_ARCH						\
+	CONFIG_KM_NEW_ENV						\
+	CONFIG_HW_ENV_SETTINGS						\
+	"EEprom_ivm=pca9547:70:9\0"					\
+	""
+
+/* App2 Local bus */
+#define CONFIG_SYS_LBAPP2_BASE		0xE0000000
+#define CONFIG_SYS_LBAPP2_BASE_PHYS	0xFE0000000ull
+
+#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
+				| BR_PS_8	/* Port Size 8 bits */ \
+				| BR_DECC_OFF	/* no error corr */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+
+#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB	/* length 256MB */ \
+				| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
+				| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
+				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
+				| OR_GPCM_TRLX /* relaxed tmgs */ \
+				| OR_GPCM_EAD) /* extra bus clk cycles */
+/* Local bus app2 Base Address */
+#define CONFIG_SYS_BR3_PRELIM  CONFIG_SYS_LBAPP2_BR_PRELIM
+/* Local bus app2 Options */
+#define CONFIG_SYS_OR3_PRELIM  CONFIG_SYS_LBAPP2_OR_PRELIM
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
new file mode 100644
index 0000000..ba33e60
--- /dev/null
+++ b/include/configs/kmsupx5.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME	"kmsupx5"
+#define CONFIG_HOSTNAME		"kmsupx5"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
new file mode 100644
index 0000000..701eb53
--- /dev/null
+++ b/include/configs/kmtegr1.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_HOSTNAME   "kmtegr1"
+#define CONFIG_KM_BOARD_NAME   "kmtegr1"
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
+#define CONFIG_KM_UBI_PARTITION_NAME_APP	"ubi1"
+
+#define CONFIG_ENV_ADDR		0xF0100000
+#define CONFIG_ENV_OFFSET	0x100000
+
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS				1
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc8309.h"
+
+/* must be after the include because KMBEC_FPGA is otherwise undefined */
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h
new file mode 100644
index 0000000..e0c907d
--- /dev/null
+++ b/include/configs/kmtepr2.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME    "kmtepr2"
+#define CONFIG_HOSTNAME         "kmtepr2"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
new file mode 100644
index 0000000..140076a
--- /dev/null
+++ b/include/configs/koelsch.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/configs/koelsch.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ */
+
+#ifndef __KOELSCH_H
+#define __KOELSCH_H
+
+#include "rcar-gen2-common.h"
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
+#define STACK_AREA_SIZE			0x00100000
+#define LOW_LEVEL_MERAM_STACK \
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE		0x40000000
+#define RCAR_GEN2_SDRAM_SIZE		(2048u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+/* SH Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK	20000000u
+#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootm_size=0x10000000\0"
+
+/* SPL support */
+#define CONFIG_SPL_STACK		0xe6340000
+#define CONFIG_SPL_MAX_SIZE		0x4000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ		65000000
+#endif
+
+#endif	/* __KOELSCH_H */
diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h
new file mode 100644
index 0000000..55bfa0f
--- /dev/null
+++ b/include/configs/kp_imx53.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#ifndef __CONFIG_H_
+#define __CONFIG_H_
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_EEPROM_BUS_NUM 1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition */
+#define CONFIG_LOADADDR		0x72000000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc1,115200\0"	\
+	"fdt_addr=0x75000000\0"		\
+	"fdt_high=0xffffffff\0"		\
+	"scriptaddr=0x74000000\0"	\
+	"kernel_file=fitImage\0"\
+	"silent=1\0"\
+	"rdinit=/sbin/init\0" \
+	"addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \
+	"upd_image=st.4k\0" \
+	"uboot_file=u-boot.imx\0" \
+	"updargs=setenv bootargs console=${console} ${smp} ${displayargs}\0" \
+	"initrd_ram_dev=/dev/ram\0" \
+	"addswupdate=setenv bootargs ${bootargs} root=${initrd_ram_dev} rw\0" \
+	"addkeys=setenv bootargs ${bootargs} di=${dig_in} key1=${key1}\0" \
+	"loadusb=usb start; " \
+	       "fatload usb 0 ${loadaddr} ${upd_image}\0" \
+	"up=if tftp ${loadaddr} ${uboot_file}; then " \
+	       "setexpr blkc ${filesize} / 0x200; " \
+	       "setexpr blkc ${blkc} + 1; " \
+	       "mmc write ${loadaddr} 0x2 ${blkc}" \
+	"; fi\0"	  \
+	"upwic=setenv wic_file kp-image-kp${boardsoc}.wic; "\
+	       "if tftp ${loadaddr} ${wic_file}; then " \
+	       "setexpr blkc ${filesize} / 0x200; " \
+	       "setexpr blkc ${blkc} + 1; " \
+	       "mmc write ${loadaddr} 0x0 ${blkc}" \
+	"; fi\0"	  \
+	"usbupd=echo Booting update from usb ...; " \
+	       "setenv bootargs; " \
+	       "run updargs; " \
+	       "run addinitrd; " \
+	       "run addswupdate; " \
+	       "run addkeys; " \
+	       "run loadusb; " \
+	       "bootm ${loadaddr}#${fit_config}\0" \
+	BOOTENV
+
+#define CONFIG_BOOTCOMMAND		"run usbupd; run distro_bootcmd"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(512 * SZ_1M)
+#define PHYS_SDRAM_SIZE		(PHYS_SDRAM_1_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_OFFSET      (SZ_1M)
+#define CONFIG_ENV_SIZE        (SZ_8K)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif				/* __CONFIG_H_ */
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
new file mode 100644
index 0000000..f6746a9
--- /dev/null
+++ b/include/configs/kp_imx6q_tpc.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K+P iMX6Q KP_IMX6Q_TPC board configuration
+ *
+ * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
+ */
+
+#ifndef __KP_IMX6Q_TPC_IMX6_CONFIG_H_
+#define __KP_IMX6Q_TPC_IMX6_CONFIG_H_
+
+#include <asm/arch/imx-regs.h>
+
+#include "mx6_common.h"
+
+/* SPL */
+#include "imx6_spl.h"			/* common IMX6 SPL configuration */
+
+/* Miscellaneous configurable options */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(4 * SZ_1M)
+
+/* FEC ethernet */
+#define CONFIG_ARP_TIMEOUT		200UL
+
+#define CONFIG_SYS_MMC_ENV_DEV		1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2 /* Enabled USB controller number */
+#endif
+
+/* Watchdog */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"console=ttymxc0,115200\0"	\
+	"fdt_addr=0x18000000\0"		\
+	"fdt_high=0xffffffff\0"		\
+	"initrd_high=0xffffffff\0"	\
+	"kernel_addr_r=0x10008000\0"	\
+	"fdt_addr_r=0x13000000\0"	\
+	"ramdisk_addr_r=0x18000000\0"	\
+	"scriptaddr=0x14000000\0"	\
+	"kernel_file=fitImage\0"\
+	"rdinit=/sbin/init\0" \
+	"addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \
+	"fit_config=mx6q_tpc70_conf\0" \
+	"uboot_file=u-boot.img\0" \
+	"SPL_file=SPL\0" \
+	"wic_file=kp-image-kpimx6qtpc.wic\0" \
+	"upd_image=st.4k\0" \
+	"updargs=setenv bootargs console=${console} ${smp} ${displayargs}\0" \
+	"initrd_ram_dev=/dev/ram\0" \
+	"addswupdate=setenv bootargs ${bootargs} root=${initrd_ram_dev} rw\0" \
+	"loadusb=usb start; " \
+	       "fatload usb 0 ${loadaddr} ${upd_image}\0" \
+	"upd_uboot_sd=" \
+	    "if tftp ${loadaddr} ${uboot_file}; then " \
+	       "setexpr blkc ${filesize} / 0x200;" \
+	       "setexpr blkc ${blkc} + 1;" \
+	       "mmc write ${loadaddr} 0x8A ${blkc};" \
+	    "fi;\0" \
+	"upd_SPL_sd=" \
+	    "if tftp ${loadaddr} ${SPL_file}; then " \
+	       "setexpr blkc ${filesize} / 0x200;" \
+	       "setexpr blkc ${blkc} + 1;" \
+	       "mmc write ${loadaddr} 0x2 ${blkc};" \
+	    "fi;\0" \
+	"upd_SPL_mmc=mmc dev 1; mmc partconf 1 0 1 1; run upd_SPL_sd\0" \
+	"upd_uboot_mmc=mmc dev 1; mmc partconf 1 0 1 1; run upd_uboot_sd\0" \
+	"up_mmc=run upd_SPL_mmc; run upd_uboot_mmc\0" \
+	"up_sd=run upd_SPL_sd; run upd_uboot_sd\0" \
+	"upd_wic=" \
+	    "if tftp ${loadaddr} ${wic_file}; then " \
+	       "setexpr blkc ${filesize} / 0x200;" \
+	       "setexpr blkc ${blkc} + 1;" \
+	       "mmc write ${loadaddr} 0x0 ${blkc};" \
+	    "fi;\0" \
+	"usbupd=echo Booting update from usb ...; " \
+	       "setenv bootargs; " \
+	       "run updargs; " \
+	       "run addinitrd; " \
+	       "run addswupdate; " \
+	       "run loadusb; " \
+	       "bootm ${loadaddr}#${fit_config}\0" \
+	BOOTENV
+
+#define CONFIG_BOOTCOMMAND		"run usbupd; run distro_bootcmd"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+#endif
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment */
+#define CONFIG_ENV_SIZE	(SZ_8K)
+#define CONFIG_ENV_OFFSET       0x100000
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#endif	/* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */
diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h
new file mode 100644
index 0000000..1ef7633
--- /dev/null
+++ b/include/configs/kylin_rk3036.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include <configs/rk3036_common.h>
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Store env in emmc */
+#define CONFIG_SYS_MMC_ENV_DEV		0 /* emmc */
+#define CONFIG_SYS_MMC_ENV_PART		0 /* user area */
+
+#endif
+
+#endif
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
new file mode 100644
index 0000000..5a2b040
--- /dev/null
+++ b/include/configs/kzm9g.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ */
+
+#ifndef __KZM9G_H
+#define __KZM9G_H
+
+#define CONFIG_SH73A0
+#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* MEMORY */
+#define KZM_SDRAM_BASE	(0x40000000)
+#define PHYS_SDRAM		KZM_SDRAM_BASE
+#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
+
+/* NOR Flash */
+#define KZM_FLASH_BASE	(0x00000000)
+#define CONFIG_SYS_FLASH_BASE		(KZM_FLASH_BASE)
+#define CONFIG_SYS_FLASH_CFI_WIDTH	(FLASH_CFI_16BIT)
+#define CONFIG_SYS_MAX_FLASH_BANKS	(1)
+#define CONFIG_SYS_MAX_FLASH_SECT	(512)
+
+/* prompt */
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_CONS_SCIF4
+
+#define CONFIG_SYS_MEMTEST_START	(KZM_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END \
+	(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_INIT_RAM_ADDR	(0xE5600000) /* on MERAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000)
+#define LOW_LEVEL_MERAM_STACK		(CONFIG_SYS_INIT_RAM_ADDR - 4)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SDRAM_OFFSET_FOR_RT	(16 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE	(KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
+#define CONFIG_SYS_SDRAM_SIZE	(PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE	(KZM_FLASH_BASE)
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
+
+#define CONFIG_STANDALONE_LOAD_ADDR	0x41000000
+
+/* FLASH */
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define FLASH_SECTOR_SIZE	(256 * 1024)	/* 256 KB sectors */
+#define CONFIG_ENV_SIZE		FLASH_SECTOR_SIZE
+#define CONFIG_ENV_OFFSET	FLASH_SECTOR_SIZE
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/* GPIO / PFC */
+#define CONFIG_SH_GPIO_PFC
+
+/* Clock */
+#define CONFIG_GLOBAL_TIMER
+#define CONFIG_SYS_CLK_FREQ	(48000000)
+#define CONFIG_SYS_CPU_CLK	(1196000000)
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
+
+#define CONFIG_NFS_TIMEOUT 10000UL
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
+#define CONFIG_SYS_I2C_SH_BASE0	0xE6820000
+#define CONFIG_SYS_I2C_SH_SPEED0	100000
+#define CONFIG_SYS_I2C_SH_BASE1	0xE6822000
+#define CONFIG_SYS_I2C_SH_SPEED1	100000
+#define CONFIG_SYS_I2C_SH_BASE2	0xE6824000
+#define CONFIG_SYS_I2C_SH_SPEED2	100000
+#define CONFIG_SYS_I2C_SH_BASE3	0xE6826000
+#define CONFIG_SYS_I2C_SH_SPEED3	100000
+#define CONFIG_SYS_I2C_SH_BASE4	0xE6828000
+#define CONFIG_SYS_I2C_SH_SPEED4	100000
+#define CONFIG_SH_I2C_8BIT
+#define CONFIG_SH_I2C_DATA_HIGH 4
+#define CONFIG_SH_I2C_DATA_LOW  5
+#define CONFIG_SH_I2C_CLOCK     104000000 /* 104 MHz */
+
+#endif /* __KZM9G_H */
diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h
new file mode 100644
index 0000000..1ba28b5
--- /dev/null
+++ b/include/configs/lacie_kw.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ */
+
+#ifndef _CONFIG_LACIE_KW_H
+#define _CONFIG_LACIE_KW_H
+
+/*
+ * Machine number definition
+ */
+#if defined(CONFIG_INETSPACE_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_INETSPACE_V2
+#elif defined(CONFIG_NETSPACE_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_NETSPACE_V2
+#elif defined(CONFIG_NETSPACE_LITE_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_NETSPACE_LITE_V2
+#elif defined(CONFIG_NETSPACE_MINI_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_NETSPACE_MINI_V2
+#elif defined(CONFIG_NETSPACE_MAX_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_NETSPACE_MAX_V2
+#elif defined(CONFIG_D2NET_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_D2NET_V2
+#elif defined(CONFIG_NET2BIG_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_NET2BIG_V2
+#else
+#error "Unknown board"
+#endif
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+/* SoC name */
+#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+#define CONFIG_KW88F6192
+#else
+#define CONFIG_KW88F6281
+#endif
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Core clock definition
+ */
+#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
+
+/*
+ * SDRAM configuration
+ */
+
+/*
+ * Different SDRAM configuration and size for some of the boards derived
+ * from the Network Space v2
+ */
+#if defined(CONFIG_INETSPACE_V2)
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg
+#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+#undef CONFIG_SYS_IDE_MAXBUS
+#undef CONFIG_SYS_IDE_MAXDEVICE
+
+/*
+ * Enable platform initialisation via misc_init_r() function
+ */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS		{1, 0} /* enable port 0 only */
+#define CONFIG_NETCONSOLE
+#endif
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
+#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
+	defined(CONFIG_NET2BIG_V2)
+#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
+#define CONFIG_SYS_IDE_MAXBUS           2
+#define CONFIG_SYS_IDE_MAXDEVICE        2
+#else
+#define CONFIG_SYS_IDE_MAXBUS           1
+#define CONFIG_SYS_IDE_MAXDEVICE        1
+#endif
+#endif /* CONFIG_MVSATA_IDE */
+
+/*
+ * Enable GPI0 support
+ */
+#define CONFIG_KIRKWOOD_GPIO
+
+/*
+ * Enable I2C support
+ */
+#ifdef CONFIG_CMD_I2C
+/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4 /* 16-byte page size */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1 /* 8-bit device address */
+#if defined(CONFIG_NET2BIG_V2)
+#define CONFIG_SYS_I2C_G762_ADDR		0x3e
+#endif
+#endif /* CONFIG_CMD_I2C */
+
+/*
+ * Partition support
+ */
+
+/*
+ * File systems support
+ */
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_SECT_SIZE		0x10000	/* 64KB */
+#define CONFIG_ENV_SIZE			0x1000	/* 4KB */
+#define CONFIG_ENV_ADDR			0x70000
+#define CONFIG_ENV_OFFSET		0x70000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND					\
+	"dhcp && run netconsole; "				\
+	"if run usbload || run diskload; then bootm; fi"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"stdin=serial\0"					\
+	"stdout=serial\0"					\
+	"stderr=serial\0"					\
+	"bootfile=uImage\0"					\
+	"loadaddr=0x800000\0"					\
+	"autoload=no\0"						\
+	"netconsole="						\
+		"set stdin $stdin,nc; "				\
+		"set stdout $stdout,nc; "			\
+		"set stderr $stderr,nc;\0"			\
+	"diskload=ide reset && "				\
+		"ext2load ide 0:1 $loadaddr /boot/$bootfile\0"	\
+	"usbload=usb start && "					\
+		"fatload usb 0:1 $loadaddr /boot/$bootfile\0"
+
+#endif /* _CONFIG_LACIE_KW_H */
diff --git a/include/configs/lager.h b/include/configs/lager.h
new file mode 100644
index 0000000..db1dbc0
--- /dev/null
+++ b/include/configs/lager.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/configs/lager.h
+ *     This file is lager board configuration.
+ *
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
+ */
+
+#ifndef __LAGER_H
+#define __LAGER_H
+
+#include "rcar-gen2-common.h"
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
+#define STACK_AREA_SIZE			0x00100000
+#define LOW_LEVEL_MERAM_STACK \
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE		0x40000000
+#define RCAR_GEN2_SDRAM_SIZE		(2048u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+/* SH Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK	20000000u
+#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootm_size=0x10000000\0"
+
+/* SPL support */
+#define CONFIG_SPL_STACK		0xe6340000
+#define CONFIG_SPL_MAX_SIZE		0x4000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ		65000000
+#endif
+
+#endif	/* __LAGER_H */
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
new file mode 100644
index 0000000..c1eeca0
--- /dev/null
+++ b/include/configs/legoev3.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 David Lechner <david@lechnology.com>
+ *
+ * Based on da850evm.h
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+
+#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI0_CLKID)
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_DAVINCI_I2C_SPEED		400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_HWCONFIG		/* enable hwconfig */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SETUP_INITRD_TAG
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan; then " \
+		"if run loadbootscr; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadbootenv; then " \
+				"echo Loaded env from ${bootenvfile};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run mmcargs; " \
+				"if run loadfdt; then " \
+					"echo Using ${fdtfile}...;" \
+					"run fdtfixup; " \
+					"run fdtboot; "\
+				"fi; " \
+				"run mmcboot; " \
+			"fi; " \
+		"fi; " \
+	"fi; "\
+	"run flashargs; " \
+	"run flashboot"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootenvfile=uEnv.txt\0" \
+	"fdtfile=da850-lego-ev3.dtb\0" \
+	"memsize=64M\0" \
+	"filesyssize=10M\0" \
+	"verify=n\0" \
+	"console=ttyS1,115200n8\0" \
+	"bootscraddr=0xC0600000\0" \
+	"fdtaddr=0xC0600000\0" \
+	"loadaddr=0xC0007FC0\0" \
+	"filesysaddr=0xC1180000\0" \
+	"fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \
+	"importbootenv=echo Importing environment...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadbootenv=fatload mmc 0 ${loadaddr} ${bootenvfile}\0" \
+	"mmcargs=setenv bootargs console=${console} root=/dev/mmcblk0p2 rw " \
+		"rootwait ${optargs}\0" \
+	"mmcboot=bootm ${loadaddr}\0" \
+	"flashargs=setenv bootargs initrd=${filesysaddr},${filesyssize} " \
+		"root=/dev/ram0 rw rootfstype=squashfs console=${console} " \
+		"${optargs}\0" \
+	"flashboot=sf probe 0; " \
+		"sf read ${fdtaddr} 0x40000 0x10000; " \
+		"sf read ${loadaddr} 0x50000 0x400000; " \
+		"sf read ${filesysaddr} 0x450000 0xA00000; " \
+		"run fdtfixup; " \
+		"run fdtboot\0" \
+	"loadimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"loadfdt=fatload mmc 0 ${fdtaddr} ${fdtfile}\0" \
+	"fdtfixup=fdt addr ${fdtaddr}; fdt resize; fdt chosen\0" \
+	"fdtboot=bootm ${loadaddr} - ${fdtaddr}\0" \
+	"loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \
+	"bootscript=source ${bootscraddr}\0"
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#define CONFIG_ENV_SIZE		(16 << 10)
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x80010000
+
+#include <asm/arch/hardware.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/libretech-ac.h b/include/configs/libretech-ac.h
new file mode 100644
index 0000000..419dc61
--- /dev/null
+++ b/include/configs/libretech-ac.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for LibreTech AC
+ *
+ * Copyright (C) 2017 Baylibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OFFSET	(-0x10000)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(ROMUSB, romusb, na)  \
+	func(MMC, mmc, 0) \
+	BOOT_TARGET_DEVICES_USB(func) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <configs/meson64.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h
new file mode 100644
index 0000000..4d30d98
--- /dev/null
+++ b/include/configs/linkit-smart-7688.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef __CONFIG_LINKIT_SMART_7688_H
+#define __CONFIG_LINKIT_SMART_7688_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	290000000
+
+/* RAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+#ifdef CONFIG_BOOT_RAM
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* UART */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, \
+					  230400, 460800, 921600 }
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80400000
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+#define CONFIG_SYS_CBSIZE		512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+/* Environment settings */
+#define CONFIG_ENV_OFFSET		0x80000
+#define CONFIG_ENV_SIZE			(16 << 10)
+#define CONFIG_ENV_SECT_SIZE		(64 << 10)
+
+/*
+ * Environment is right behind U-Boot in flash. Make sure U-Boot
+ * doesn't grow into the environment area.
+ */
+#define CONFIG_BOARD_SIZE_LIMIT		CONFIG_ENV_OFFSET
+
+#endif /* __CONFIG_LINKIT_SMART_7688_H */
diff --git a/include/configs/lion_rk3368.h b/include/configs/lion_rk3368.h
new file mode 100644
index 0000000..cae0f1e
--- /dev/null
+++ b/include/configs/lion_rk3368.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#ifndef __CONFIGS_LION_RK3368_H
+#define __CONFIGS_LION_RK3368_H
+
+#include <configs/rk3368_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define KERNEL_LOAD_ADDR		0x280000
+#define DTB_LOAD_ADDR			0x5600000
+#define INITRD_LOAD_ADDR		0x5bf0000
+/* PHY needs longer aneg time at 1G */
+#define PHY_ANEG_TIMEOUT		8000
+
+#endif
diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h
new file mode 100644
index 0000000..975f324
--- /dev/null
+++ b/include/configs/liteboard.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2016 Grinn
+ *
+ * Configuration settings for the Grinn liteBoard (i.MX6UL).
+ */
+#ifndef __LITEBOARD_CONFIG_H
+#define __LITEBOARD_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
+#endif
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_128M)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		0
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_ENET_DEV		0
+
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x0
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC"
+
+#define CONFIG_PHY_SMSC
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#endif
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
new file mode 100644
index 0000000..cb32938
--- /dev/null
+++ b/include/configs/ls1012a2g5rdb.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef __LS1012A2G5RDB_H__
+#define __LS1012A2G5RDB_H__
+
+#include "ls1012a_common.h"
+
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"verify=no\0"				\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x00f00000\0"			\
+	"kernel_addr=0x01000000\0"		\
+	"kernelheader_addr=0x800000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"console=ttyS0,115200\0"		\
+	BOOTENV					\
+	"boot_scripts=ls1012ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1012ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+	     "part list ${devtype} ${devnum} devplist; "	\
+	     "env exists devplist || setenv devplist 1; "	\
+	     "for distro_bootpart in ${devplist}; do "		\
+		  "if fstype ${devtype} "			\
+		      "${devnum}:${distro_bootpart} "		\
+		      "bootfstype; then "			\
+		      "run scan_dev_for_boot; "	\
+		  "fi; "			\
+	      "done\0"				\
+	"scan_dev_for_boot="				  \
+		"echo Scanning ${devtype} "		  \
+				"${devnum}:${distro_bootpart}...; "  \
+		"for prefix in ${boot_prefixes}; do "	  \
+			"run scan_dev_for_scripts; "	  \
+		"done;"					  \
+		"\0"					  \
+	"boot_a_script="				  \
+		"load ${devtype} ${devnum}:${distro_bootpart} "  \
+			"${scriptaddr} ${prefix}${script}; "    \
+		"env exists secureboot && load ${devtype} "     \
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+			"&& esbc_validate ${scripthdraddr};"    \
+		"source ${scriptaddr}\0"	  \
+	"installer=load mmc 0:2 $load_addr "	\
+		   "/flex_installer_arm64.itb; "	\
+		   "bootm $load_addr#$board\0"	\
+	"qspi_bootcmd=echo Trying load from qspi..;"	\
+		"sf probe && sf read $load_addr "	\
+		"$kernel_addr $kernel_size; env exists secureboot "	\
+		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#undef QSPI_NOR_BOOTCOMMAND
+#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \
+			     "env exists secureboot && esbc_halt;"
+#else
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \
+			   "env exists secureboot && esbc_halt;"
+#endif
+#endif
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A2G5RDB_H__ */
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
new file mode 100644
index 0000000..dd2a679
--- /dev/null
+++ b/include/configs/ls1012a_common.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor
+ */
+
+#ifndef __LS1012A_COMMON_H
+#define __LS1012A_COMMON_H
+
+#define CONFIG_GICV2
+
+#include <asm/arch/config.h>
+#include <asm/arch/stream_id_lsch2.h>
+
+#define CONFIG_SYS_CLK_FREQ		125000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR                CONFIG_SYS_TEXT_BASE
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE     0x880000000ULL
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*SPI device */
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT)
+#define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+
+#define QSPI0_AMBA_BASE		0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+
+#define FSL_QSPI_FLASH_SIZE		SZ_64M
+#define FSL_QSPI_FLASH_NUM		2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_SIZE			0x40000          /* 256KB */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_ENV_OFFSET		0x500000        /* 5MB */
+#else
+#define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
+#endif
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#endif
+
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(SCSI, scsi, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"verify=no\0"				\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x1000000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND	"pfe stop; sf probe 0:0; sf read $kernel_load "\
+				"$kernel_start $kernel_size && "\
+				"bootm $kernel_load"
+#else
+#define CONFIG_BOOTCOMMAND	"pfe stop; sf probe 0:0; sf read $kernel_load "\
+				"$kernel_start $kernel_size && "\
+				"bootm $kernel_load"
+#endif
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#include <asm/arch/soc.h>
+
+#endif /* __LS1012A_COMMON_H */
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
new file mode 100644
index 0000000..8c7d4e5
--- /dev/null
+++ b/include/configs/ls1012afrdm.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#ifndef CONFIG_SPL_BUILD
+#undef BOOT_TARGET_DEVICES
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0)
+#endif
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"verify=no\0"				\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x00f00000\0"			\
+	"kernel_addr=0x01000000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x96000000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0x96000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"console=ttyS0,115200\0"		\
+	BOOTENV					\
+	"boot_scripts=ls1012afrdm_boot.scr\0"	\
+	"scan_dev_for_boot_part="		\
+	     "part list ${devtype} ${devnum} devplist; "	\
+	     "env exists devplist || setenv devplist 1; "	\
+	     "for distro_bootpart in ${devplist}; do "		\
+		  "if fstype ${devtype} "			\
+		      "${devnum}:${distro_bootpart} "		\
+		      "bootfstype; then "			\
+		      "run scan_dev_for_boot; "	\
+		  "fi; "			\
+	      "done\0"				\
+	"scan_dev_for_boot="				  \
+		"echo Scanning ${devtype} "		  \
+				"${devnum}:${distro_bootpart}...; "  \
+		"for prefix in ${boot_prefixes}; do "	  \
+			"run scan_dev_for_scripts; "	  \
+		"done;"					  \
+		"\0"					  \
+	"installer=load usb 0:2 $load_addr "	\
+		   "/flex_installer_arm64.itb; "	\
+		   "bootm $load_addr#$board\0"	\
+	"qspi_bootcmd=echo Trying load from qspi..;"	\
+		"sf probe && sf read $load_addr "	\
+		"$kernel_addr $kernel_size && bootm $load_addr#$board\0"
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#undef QSPI_NOR_BOOTCOMMAND
+#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd"
+#else
+#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd"
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
new file mode 100644
index 0000000..1b0f156
--- /dev/null
+++ b/include/configs/ls1012afrwy.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __LS1012AFRWY_H__
+#define __LS1012AFRWY_H__
+
+#include "ls1012a_common.h"
+
+/* Board Rev*/
+#define BOARD_REV_A_B			0x0
+#define BOARD_REV_C			0x00080000
+#define BOARD_REV_MASK			0x001A0000
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define SYS_SDRAM_SIZE_512		0x20000000
+#define SYS_SDRAM_SIZE_1024		0x40000000
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/* ENV */
+#define CONFIG_SYS_FSL_QSPI_BASE	0x40000000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FSL_QSPI_BASE + \
+				CONFIG_ENV_OFFSET)
+
+#ifndef CONFIG_SPL_BUILD
+#undef BOOT_TARGET_DEVICES
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0)
+#endif
+
+#undef CONFIG_ENV_OFFSET
+#define CONFIG_ENV_OFFSET              0x1D0000
+#undef FSL_QSPI_FLASH_SIZE
+#define FSL_QSPI_FLASH_SIZE            SZ_16M
+#undef CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE		0x10000 /*64 KB*/
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE			0x10000 /*64 KB*/
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+
+#define CONFIG_PCI_SCAN_SHOW
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"verify=no\0"				\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x00f00000\0"			\
+	"kernel_addr=0x01000000\0"		\
+	"kernel_size_sd=0x16000\0"		\
+	"kernelhdr_size_sd=0x10\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernelhdr_addr_sd=0x4000\0"		\
+	"kernelheader_addr=0x1fc000\0"		\
+	"kernelheader_addr=0x1fc000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernelheader_size=0x40000\0"		\
+	"kernel_addr_r=0x81000000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0x96000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"console=ttyS0,115200\0"		\
+	BOOTENV					\
+	"boot_scripts=ls1012afrwy_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1012afrwy_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+	     "part list ${devtype} ${devnum} devplist; "	\
+	     "env exists devplist || setenv devplist 1; "	\
+	     "for distro_bootpart in ${devplist}; do "		\
+		  "if fstype ${devtype} "			\
+		      "${devnum}:${distro_bootpart} "		\
+		      "bootfstype; then "			\
+		      "run scan_dev_for_boot; "	\
+		  "fi; "			\
+	      "done\0"				\
+	"scan_dev_for_boot="				  \
+		"echo Scanning ${devtype} "		  \
+				"${devnum}:${distro_bootpart}...; "  \
+		"for prefix in ${boot_prefixes}; do "	  \
+			"run scan_dev_for_scripts; "	  \
+		"done;"					  \
+		"\0"					  \
+	"boot_a_script="				  \
+		"load ${devtype} ${devnum}:${distro_bootpart} "  \
+			"${scriptaddr} ${prefix}${script}; "    \
+		"env exists secureboot && load ${devtype} "     \
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
+			"&& esbc_validate ${scripthdraddr};"    \
+		"source ${scriptaddr}\0"	  \
+	"installer=load mmc 0:2 $load_addr "	\
+		   "/flex_installer_arm64.itb; "	\
+		   "bootm $load_addr#$board\0"	\
+	"qspi_bootcmd=echo Trying load from qspi..;"	\
+		"sf probe && sf read $load_addr "	\
+		"$kernel_addr $kernel_size; env exists secureboot "	\
+		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"	\
+	"sd_bootcmd=echo Trying load from sd card..;"		\
+		"mmcinfo; mmc read $load_addr "			\
+		"$kernel_addr_sd $kernel_size_sd ;"		\
+		"env exists secureboot && mmc read $kernelheader_addr_r "\
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#undef QSPI_NOR_BOOTCOMMAND
+#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\
+			     "env exists secureboot && esbc_halt;"
+#else
+#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\
+			   "env exists secureboot && esbc_halt;"
+#endif
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#include <asm/fsl_secure_boot.h>
+
+#include <asm/fsl_secure_boot.h>
+#endif /* __LS1012AFRWY_H__ */
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
new file mode 100644
index 0000000..fb0d1ba
--- /dev/null
+++ b/include/configs/ls1012aqds.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __LS1012AQDS_H__
+#define __LS1012AQDS_H__
+
+#include "ls1012a_common.h"
+
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_BRDCFG_REG		0x04
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0x08
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x08
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI		0x77
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR		0x18
+#define I2C_MUX_CH_DEFAULT		0x8
+#define I2C_MUX_CH_CH7301		0xC
+#define I2C_MUX_CH5			0xD
+#define I2C_MUX_CH7			0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_RTC_PCF8563 1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM    0
+#define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN     1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR           0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
+
+/* DSPI */
+#define CONFIG_FSL_DSPI1
+
+#define MMAP_DSPI          DSPI1_BASE_ADDR
+
+#define CONFIG_SYS_DSPI_CTAR0   1
+
+#define CONFIG_SYS_DSPI_CTAR1	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_SST /* cs1 */
+
+#define CONFIG_SYS_DSPI_CTAR2	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
+
+#define CONFIG_SYS_DSPI_CTAR3	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_EON /* cs3 */
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+
+#define CONFIG_PCI_SCAN_SHOW
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#include <asm/fsl_secure_boot.h>
+#endif /* __LS1012AQDS_H__ */
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
new file mode 100644
index 0000000..a5e2740
--- /dev/null
+++ b/include/configs/ls1012ardb.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+
+/* ENV */
+#define CONFIG_SYS_FSL_QSPI_BASE	0x40000000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FSL_QSPI_BASE + \
+					 CONFIG_ENV_OFFSET)
+/*
+ * I2C IO expander
+ */
+
+#define I2C_MUX_IO_ADDR		0x24
+#define I2C_MUX_IO2_ADDR	0x25
+#define I2C_MUX_IO_0		0
+#define I2C_MUX_IO_1		1
+#define SW_BOOT_MASK		0x03
+#define SW_BOOT_EMU		0x02
+#define SW_BOOT_BANK1		0x00
+#define SW_BOOT_BANK2		0x01
+#define SW_REV_MASK		0xF8
+#define SW_REV_A		0xF8
+#define SW_REV_B		0xF0
+#define SW_REV_C		0xE8
+#define SW_REV_C1		0xE0
+#define SW_REV_C2		0xD8
+#define SW_REV_D		0xD0
+#define SW_REV_E		0xC8
+#define __PHY_MASK		0xF9
+#define __PHY_ETH2_MASK		0xFB
+#define __PHY_ETH1_MASK		0xFD
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+
+#define CONFIG_PCI_SCAN_SHOW
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"verify=no\0"				\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x00f00000\0"			\
+	"kernel_addr=0x01000000\0"		\
+	"kernelheader_addr=0x800000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"console=ttyS0,115200\0"		\
+	BOOTENV					\
+	"boot_scripts=ls1012ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1012ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+	     "part list ${devtype} ${devnum} devplist; "	\
+	     "env exists devplist || setenv devplist 1; "	\
+	     "for distro_bootpart in ${devplist}; do "		\
+		  "if fstype ${devtype} "			\
+		      "${devnum}:${distro_bootpart} "		\
+		      "bootfstype; then "			\
+		      "run scan_dev_for_boot; "	\
+		  "fi; "			\
+	      "done\0"				\
+	"scan_dev_for_boot="				  \
+		"echo Scanning ${devtype} "		  \
+				"${devnum}:${distro_bootpart}...; "  \
+		"for prefix in ${boot_prefixes}; do "	  \
+			"run scan_dev_for_scripts; "	  \
+		"done;"					  \
+		"\0"					  \
+	"boot_a_script="				  \
+		"load ${devtype} ${devnum}:${distro_bootpart} "  \
+			"${scriptaddr} ${prefix}${script}; "    \
+		"env exists secureboot && load ${devtype} "     \
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
+			"&& esbc_validate ${scripthdraddr};"    \
+		"source ${scriptaddr}\0"	  \
+	"installer=load mmc 0:2 $load_addr "	\
+		   "/flex_installer_arm64.itb; "	\
+		   "bootm $load_addr#$board\0"	\
+	"qspi_bootcmd=echo Trying load from qspi..;"	\
+		"sf probe && sf read $load_addr "	\
+		"$kernel_addr $kernel_size; env exists secureboot "	\
+		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#undef QSPI_NOR_BOOTCOMMAND
+#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
+			     "env exists secureboot && esbc_halt;"
+#else
+#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
+			   "env exists secureboot && esbc_halt;"
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012ARDB_H__ */
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
new file mode 100644
index 0000000..ee570bc
--- /dev/null
+++ b/include/configs/ls1021aiot.h
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
+
+#define CONFIG_SYS_FSL_CLK
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+
+/*
+ * DDR: 800 MHz ( 1600 MT/s data rate )
+ */
+
+#define DDR_SDRAM_CFG			0x470c0008
+#define DDR_CS0_BNDS			0x008000bf
+#define DDR_CS0_CONFIG			0x80014302
+#define DDR_TIMING_CFG_0		0x50550004
+#define DDR_TIMING_CFG_1		0xbcb38c56
+#define DDR_TIMING_CFG_2		0x0040d120
+#define DDR_TIMING_CFG_3		0x010e1000
+#define DDR_TIMING_CFG_4		0x00000001
+#define DDR_TIMING_CFG_5		0x03401400
+#define DDR_SDRAM_CFG_2			0x00401010
+#define DDR_SDRAM_MODE			0x00061c60
+#define DDR_SDRAM_MODE_2		0x00180000
+#define DDR_SDRAM_INTERVAL		0x18600618
+#define DDR_DDR_WRLVL_CNTL		0x8655f605
+#define DDR_DDR_WRLVL_CNTL_2	0x05060607
+#define DDR_DDR_WRLVL_CNTL_3	0x05050505
+#define DDR_DDR_CDR1			0x80040000
+#define DDR_DDR_CDR2			0x00000001
+#define DDR_SDRAM_CLK_CNTL		0x02000000
+#define DDR_DDR_ZQ_CNTL			0x89080600
+#define DDR_CS0_CONFIG_2		0
+#define DDR_SDRAM_CFG_MEM_EN	0x80000000
+#define SDRAM_CFG2_D_INIT		0x00000010
+#define DDR_CDR2_VREF_TRAIN_EN	0x00000080
+#define SDRAM_CFG2_FRC_SR		0x80000000
+#define SDRAM_CFG_BI			0x00000001
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI	\
+	board/freescale/ls1021aiot/ls102xa_pbi.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW	\
+	board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0xe8
+
+#define CONFIG_SPL_MAX_SIZE		0x1a000
+#define CONFIG_SPL_STACK		0x1001d000
+#define CONFIG_SPL_PAD_TO		0x1c000
+
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
+		CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+#endif
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+/*
+ * I2C
+ */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x51
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/*
+ * MMC
+ */
+#define CONFIG_CMD_MMC
+
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+#ifndef PCI_DEVICE_ID_FREESCALE_AHCI
+#define PCI_DEVICE_ID_FREESCALE_AHCI	0x0440
+#endif
+#define CONFIG_SCSI_DEV_LIST		{PCI_VENDOR_ID_FREESCALE, \
+	PCI_DEVICE_ID_FREESCALE_AHCI}
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+		CONFIG_SYS_SCSI_MAX_LUN)
+
+/* SPI */
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SPI_FLASH_SPANSION
+
+/* QSPI */
+#define QSPI0_AMBA_BASE			0x40000000
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+#define CONFIG_SPI_FLASH_SPANSION
+#endif
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
+#define CONFIG_CMD_SF
+#define CONFIG_DM_SPI_FLASH
+#endif
+
+/*
+ * eTSEC
+ */
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_MII_DEFAULT_TSEC		1
+#define CONFIG_TSEC1			1
+#define CONFIG_TSEC1_NAME		"eTSEC1"
+#define CONFIG_TSEC2			1
+#define CONFIG_TSEC2_NAME		"eTSEC2"
+
+#define TSEC1_PHY_ADDR			1
+#define TSEC2_PHY_ADDR			3
+
+#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX			0
+#define TSEC2_PHYIDX			0
+
+#define CONFIG_ETHPRIME			"eTSEC2"
+
+#define CONFIG_PHY_ATHEROS
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+/* PCIe */
+#define CONFIG_PCIE1		/* PCIE controler 1 */
+#define CONFIG_PCIE2		/* PCIE controler 2 */
+
+#define FSL_PCIE_COMPAT		"fsl,ls1021a-pcie"
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_CMD_MII
+
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR		0x01ee0200
+#define COUNTER_FREQUENCY		12500000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		256
+
+#define CONFIG_FSL_DEVICE_DISABLE
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
+"initrd_high=0xffffffff\0"	\
+"fdt_high=0xffffffff\0"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MEMINFO
+
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+#define CONFIG_LS102XA_STREAM_ID
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+#define CONFIG_SYS_QE_FW_ADDR	0x67f40000
+
+/*
+ * Environment
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_ENV_SIZE			0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#include <asm/fsl_secure_boot.h>
+
+#endif
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
new file mode 100644
index 0000000..66771e2
--- /dev/null
+++ b/include/configs/ls1021aqds.h
@@ -0,0 +1,515 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARMV7_PSCI_1_0
+
+#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR
+
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_DEEP_SLEEP
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+#define CONFIG_QIXIS_I2C_ACCESS
+#else
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
+#endif
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021aqds/ls102xa_pbi.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW	\
+	board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_RCW	\
+	board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
+#endif
+
+#define CONFIG_SPL_MAX_SIZE		0x1a000
+#define CONFIG_SPL_STACK		0x1001d000
+#define CONFIG_SPL_PAD_TO		0x1c000
+
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
+		CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_MONITOR_LEN		0xc0000
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW	board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
+
+#define CONFIG_SPL_MAX_SIZE		0x1a000
+#define CONFIG_SPL_STACK		0x1001d000
+#define CONFIG_SPL_PAD_TO		0x1c000
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(400 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+#endif
+
+#define CONFIG_DDR_SPD
+#define SPD_EEPROM_ADDRESS		0x51
+#define CONFIG_SYS_SPD_BUS_NUM		0
+
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_DDR_RAW_TIMING
+#endif
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
+#endif
+
+/*
+ * IFC Definitions
+ */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_FSL_IFC
+#define CONFIG_SYS_FLASH_BASE		0x60000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
+
+#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_TRHZ_80)
+#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
+					FTIM0_NOR_TEADC(0x5) | \
+					FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
+					FTIM1_NOR_TRAD_NOR(0x1a) | \
+					FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
+					FTIM2_NOR_TCH(0x4) | \
+					FTIM2_NOR_TWPH(0xe) | \
+					FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3		0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
+					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+
+#define CONFIG_SYS_NAND_BASE		0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	\
+				| CSPR_MSEL_NAND	\
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x7) | \
+					FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0xe)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+					FTIM2_NAND_TREH(0xa) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3           0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#endif
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE			0x7fb00000
+#define QIXIS_BASE_PHYS			QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_PWR_CTL			0x21
+#define QIXIS_PWR_CTL_POWEROFF		0x80
+#define QIXIS_RST_CTL_RESET		0x44
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_CTL_SYS			0x5
+#define QIXIS_CTL_SYS_EVTSW_MASK	0x0c
+#define QIXIS_CTL_SYS_EVTSW_IRQ		0x04
+#define QIXIS_RST_FORCE_3		0x45
+#define QIXIS_RST_FORCE_3_PCIESLOT1	0x80
+#define QIXIS_PWR_CTL2			0x21
+#define QIXIS_PWR_CTL2_PCTL		0x2
+
+#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_NOR_MODE_AVD_NOR | \
+					CSOR_NOR_TRHZ_80)
+
+/*
+ * QIXIS Timing parameters for IFC GPCM
+ */
+#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xe) | \
+					FTIM0_GPCM_TEADC(0xe) | \
+					FTIM0_GPCM_TEAHC(0xe))
+#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xe) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xe) | \
+					FTIM2_GPCM_TCH(0xe) | \
+					FTIM2_GPCM_TWP(0xf0))
+#define CONFIG_SYS_FPGA_FTIM3		0x0
+#endif
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#endif
+
+/*
+ * Serial Port
+ */
+#ifdef CONFIG_LPUART
+#define CONFIG_LPUART_32B_REG
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#endif
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#endif
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI		0x77
+#define I2C_MUX_CH_DEFAULT		0x8
+#define I2C_MUX_CH_CH7301		0xC
+
+/*
+ * MMC
+ */
+
+/* SPI */
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+/* QSPI */
+#define QSPI0_AMBA_BASE			0x40000000
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+
+/* DSPI */
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_SPI_FLASH_DATAFLASH
+#endif
+#endif
+
+/*
+ * Video
+ */
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+
+#define CONFIG_FSL_DIU_CH7301
+#define CONFIG_SYS_I2C_DVI_BUS_NUM	0
+#define CONFIG_SYS_I2C_QIXIS_ADDR	0x66
+#define CONFIG_SYS_I2C_DVI_ADDR		0x75
+#endif
+
+/*
+ * eTSEC
+ */
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_MII_DEFAULT_TSEC		3
+#define CONFIG_TSEC1			1
+#define CONFIG_TSEC1_NAME		"eTSEC1"
+#define CONFIG_TSEC2			1
+#define CONFIG_TSEC2_NAME		"eTSEC2"
+#define CONFIG_TSEC3			1
+#define CONFIG_TSEC3_NAME		"eTSEC3"
+
+#define TSEC1_PHY_ADDR			1
+#define TSEC2_PHY_ADDR			2
+#define TSEC3_PHY_ADDR			3
+
+#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX			0
+#define TSEC2_PHYIDX			0
+#define TSEC3_PHYIDX			0
+
+#define CONFIG_ETHPRIME			"eTSEC1"
+
+#define CONFIG_PHY_REALTEK
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_FSL_SGMII_RISER		1
+#define SGMII_RISER_PHY_OFFSET		0x1b
+
+#ifdef CONFIG_FSL_SGMII_RISER
+#define CONFIG_SYS_TBIPA_VALUE		8
+#endif
+
+#endif
+
+/* PCIe */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR		0x01ee0200
+#define COUNTER_FREQUENCY		12500000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		256
+
+#define CONFIG_FSL_DEVICE_DISABLE
+
+
+#define CONFIG_SYS_QE_FW_ADDR     0x60940000
+
+#ifdef CONFIG_LPUART
+#define CONFIG_EXTRA_ENV_SETTINGS       \
+	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
+	"fdt_high=0xffffffff\0"         \
+	"initrd_high=0xffffffff\0"      \
+	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
+	"fdt_high=0xffffffff\0"		\
+	"initrd_high=0xffffffff\0"      \
+	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+#define CONFIG_LS102XA_STREAM_ID
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET		0x300000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#elif defined(CONFIG_NAND_BOOT)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
+#endif
+
+#include <asm/fsl_secure_boot.h>
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+#endif
diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h
new file mode 100644
index 0000000..b011cb2
--- /dev/null
+++ b/include/configs/ls1021atsn.h
@@ -0,0 +1,250 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * Copyright 2016-2018 NXP Semiconductors
+ * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR
+
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_DEEP_SLEEP
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
+
+/* XHCI Support - enabled by default */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+
+#define DDR_SDRAM_CFG			0x470c0008
+#define DDR_CS0_BNDS			0x008000bf
+#define DDR_CS0_CONFIG			0x80014302
+#define DDR_TIMING_CFG_0		0x50550004
+#define DDR_TIMING_CFG_1		0xbcb38c56
+#define DDR_TIMING_CFG_2		0x0040d120
+#define DDR_TIMING_CFG_3		0x010e1000
+#define DDR_TIMING_CFG_4		0x00000001
+#define DDR_TIMING_CFG_5		0x03401400
+#define DDR_SDRAM_CFG_2			0x00401010
+#define DDR_SDRAM_MODE			0x00061c60
+#define DDR_SDRAM_MODE_2		0x00180000
+#define DDR_SDRAM_INTERVAL		0x18600618
+#define DDR_DDR_WRLVL_CNTL		0x8655f605
+#define DDR_DDR_WRLVL_CNTL_2		0x05060607
+#define DDR_DDR_WRLVL_CNTL_3		0x05050505
+#define DDR_DDR_CDR1			0x80040000
+#define DDR_DDR_CDR2			0x00000001
+#define DDR_SDRAM_CLK_CNTL		0x02000000
+#define DDR_DDR_ZQ_CNTL			0x89080600
+#define DDR_CS0_CONFIG_2		0
+#define DDR_SDRAM_CFG_MEM_EN		0x80000000
+#define SDRAM_CFG2_D_INIT		0x00000010
+#define DDR_CDR2_VREF_TRAIN_EN		0x00000080
+#define SDRAM_CFG2_FRC_SR		0x80000000
+#define SDRAM_CFG_BI			0x00000001
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI	\
+		"board/freescale/ls1021atsn/ls102xa_pbi.cfg"
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW	\
+		"board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
+#endif /* ifdef CONFIG_SECURE_BOOT */
+
+#define CONFIG_SPL_MAX_SIZE		0x1a000
+#define CONFIG_SPL_STACK		0x1001d000
+#define CONFIG_SPL_PAD_TO		0x1c000
+
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
+		CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#ifdef CONFIG_U_BOOT_HDR_SIZE
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw U-Boot image instead of FIT image.
+ */
+#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN		0x100000
+#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x80000000
+#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#endif
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#define CONFIG_BAUDRATE			115200
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x51
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/* QSPI */
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+
+/* PCIe */
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define FSL_PCIE_COMPAT			"fsl,ls1021a-pcie"
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+#define COUNTER_FREQUENCY		12500000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		256
+
+#define CONFIG_FSL_DEVICE_DISABLE
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0"		\
+	"initrd_high=0xffffffff\0"					\
+	"fdt_high=0xffffffff\0"						\
+	"fdt_addr=0x64f00000\0"						\
+	"kernel_addr=0x61000000\0"					\
+	"kernelheader_addr=0x60800000\0"				\
+	"scriptaddr=0x80000000\0"					\
+	"scripthdraddr=0x80080000\0"					\
+	"fdtheader_addr_r=0x80100000\0"					\
+	"kernelheader_addr_r=0x80200000\0"				\
+	"kernel_addr_r=0x80008000\0"					\
+	"kernelheader_size=0x40000\0"					\
+	"fdt_addr_r=0x8f000000\0"					\
+	"ramdisk_addr_r=0xa0000000\0"					\
+	"load_addr=0x80008000\0"					\
+	"kernel_size=0x2800000\0"					\
+	"kernel_addr_sd=0x8000\0"					\
+	"kernel_size_sd=0x14000\0"					\
+	"kernelhdr_addr_sd=0x4000\0"					\
+	"kernelhdr_size_sd=0x10\0"					\
+	BOOTENV								\
+	"boot_scripts=ls1021atsn_boot.scr\0"				\
+	"boot_script_hdr=hdr_ls1021atsn_bs.out\0"			\
+		"scan_dev_for_boot_part="				\
+			"part list ${devtype} ${devnum} devplist; "	\
+			"env exists devplist || setenv devplist 1; "	\
+			"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "				\
+				"${devnum}:${distro_bootpart} "		\
+				"bootfstype; then "			\
+				"run scan_dev_for_boot; "		\
+			"fi; "						\
+		"done\0"						\
+	"scan_dev_for_boot="						\
+		"echo Scanning ${devtype} "				\
+				"${devnum}:${distro_bootpart}...; "	\
+		"for prefix in ${boot_prefixes}; do "			\
+			"run scan_dev_for_scripts; "			\
+			"run scan_dev_for_extlinux; "			\
+		"done;"							\
+		"\0"							\
+	"boot_a_script="						\
+		"load ${devtype} ${devnum}:${distro_bootpart} "		\
+			"${scriptaddr} ${prefix}${script}; "		\
+		"env exists secureboot && load ${devtype} "		\
+			"${devnum}:${distro_bootpart} "			\
+			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
+			"&& esbc_validate ${scripthdraddr};"		\
+		"source ${scriptaddr}\0"				\
+	"qspi_bootcmd=echo Trying load from qspi..;"			\
+		"sf probe && sf read $load_addr "			\
+		"$kernel_addr $kernel_size; env exists secureboot "	\
+		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"				\
+	"sd_bootcmd=echo Trying load from SD ..;"			\
+		"mmcinfo && mmc read $load_addr "			\
+		"$kernel_addr_sd $kernel_size_sd && "			\
+		"env exists secureboot && mmc read $kernelheader_addr_r " \
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
+		" && esbc_validate ${kernelheader_addr_r};"		\
+		"bootm $load_addr#$board\0"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		\
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+#define CONFIG_LS102XA_STREAM_ID
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET		0x300000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x20000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x300000
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN		0x8000000 /* 128 MB */
+
+#endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
new file mode 100644
index 0000000..31abee8
--- /dev/null
+++ b/include/configs/ls1021atwr.h
@@ -0,0 +1,477 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARMV7_PSCI_1_0
+
+#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR
+
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_DEEP_SLEEP
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+
+#define DDR_SDRAM_CFG			0x470c0008
+#define DDR_CS0_BNDS			0x008000bf
+#define DDR_CS0_CONFIG			0x80014302
+#define DDR_TIMING_CFG_0		0x50550004
+#define DDR_TIMING_CFG_1		0xbcb38c56
+#define DDR_TIMING_CFG_2		0x0040d120
+#define DDR_TIMING_CFG_3		0x010e1000
+#define DDR_TIMING_CFG_4		0x00000001
+#define DDR_TIMING_CFG_5		0x03401400
+#define DDR_SDRAM_CFG_2			0x00401010
+#define DDR_SDRAM_MODE			0x00061c60
+#define DDR_SDRAM_MODE_2		0x00180000
+#define DDR_SDRAM_INTERVAL		0x18600618
+#define DDR_DDR_WRLVL_CNTL		0x8655f605
+#define DDR_DDR_WRLVL_CNTL_2		0x05060607
+#define DDR_DDR_WRLVL_CNTL_3		0x05050505
+#define DDR_DDR_CDR1			0x80040000
+#define DDR_DDR_CDR2			0x00000001
+#define DDR_SDRAM_CLK_CNTL		0x02000000
+#define DDR_DDR_ZQ_CNTL			0x89080600
+#define DDR_CS0_CONFIG_2		0
+#define DDR_SDRAM_CFG_MEM_EN		0x80000000
+#define SDRAM_CFG2_D_INIT		0x00000010
+#define DDR_CDR2_VREF_TRAIN_EN		0x00000080
+#define SDRAM_CFG2_FRC_SR		0x80000000
+#define SDRAM_CFG_BI			0x00000001
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021atwr/ls102xa_pbi.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW	\
+	board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_RCW	\
+	board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
+#endif
+
+#ifdef CONFIG_SECURE_BOOT
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image.
+ */
+#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
+#endif /* ifdef CONFIG_SECURE_BOOT */
+
+#define CONFIG_SPL_MAX_SIZE		0x1a000
+#define CONFIG_SPL_STACK		0x1001d000
+#define CONFIG_SPL_PAD_TO		0x1c000
+
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
+		CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#ifdef CONFIG_U_BOOT_HDR_SIZE
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw u-boot image instead of fit image.
+ */
+#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN		0x100000
+#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
+#endif
+
+#define PHYS_SDRAM			0x80000000
+#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+/*
+ * IFC Definitions
+ */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_FSL_IFC
+#define CONFIG_SYS_FLASH_BASE		0x60000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_TRHZ_80)
+#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
+					FTIM0_NOR_TEADC(0x5) | \
+					FTIM0_NOR_TAVDS(0x0) | \
+					FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
+					FTIM1_NOR_TRAD_NOR(0x1A) | \
+					FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
+					FTIM2_NOR_TCH(0x4) | \
+					FTIM2_NOR_TWP(0x1c) | \
+					FTIM2_NOR_TWPH(0x0e))
+#define CONFIG_SYS_NOR_FTIM3		0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#endif
+
+/* CPLD */
+
+#define CONFIG_SYS_CPLD_BASE	0x7fb00000
+#define CPLD_BASE_PHYS		CONFIG_SYS_CPLD_BASE
+
+#define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
+#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_NOR_MODE_AVD_NOR | \
+					CSOR_NOR_TRHZ_80)
+
+/* CPLD Timing parameters for IFC GPCM */
+#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
+					FTIM0_GPCM_TEADC(0xf) | \
+					FTIM0_GPCM_TEAHC(0xf))
+#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0xff))
+#define CONFIG_SYS_FPGA_FTIM3           0x0
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_FPGA_FTIM3
+
+/*
+ * Serial Port
+ */
+#ifdef CONFIG_LPUART
+#define CONFIG_LPUART_32B_REG
+#else
+#define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#endif
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#endif
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+/*
+ * MMC
+ */
+
+/* SPI */
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+/* QSPI */
+#define QSPI0_AMBA_BASE			0x40000000
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+
+/* DSPI */
+#endif
+
+/* DM SPI */
+#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
+#define CONFIG_DM_SPI_FLASH
+#endif
+
+/*
+ * Video
+ */
+#ifdef CONFIG_VIDEO_FSL_DCU_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+
+#define CONFIG_FSL_DCU_SII9022A
+#define CONFIG_SYS_I2C_DVI_BUS_NUM	1
+#define CONFIG_SYS_I2C_DVI_ADDR		0x39
+#endif
+
+/*
+ * eTSEC
+ */
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_ETHPRIME			"ethernet@2d10000"
+#endif
+
+/* PCIe */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+#define CONFIG_SMP_PEN_ADDR		0x01ee0200
+#define COUNTER_FREQUENCY		12500000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		256
+
+#define CONFIG_FSL_DEVICE_DISABLE
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#ifdef CONFIG_LPUART
+#define CONFIG_EXTRA_ENV_SETTINGS       \
+	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
+	"initrd_high=0xffffffff\0"      \
+	"fdt_high=0xffffffff\0"		\
+	"fdt_addr=0x64f00000\0"		\
+	"kernel_addr=0x65000000\0"	\
+	"scriptaddr=0x80000000\0"	\
+	"scripthdraddr=0x80080000\0"	\
+	"fdtheader_addr_r=0x80100000\0"	\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"	\
+	"fdt_addr_r=0x90000000\0"	\
+	"ramdisk_addr_r=0xa0000000\0"	\
+	"load_addr=0xa0000000\0"	\
+	"kernel_size=0x2800000\0"	\
+	"kernel_addr_sd=0x8000\0"	\
+	"kernel_size_sd=0x14000\0"	\
+	BOOTENV				\
+	"boot_scripts=ls1021atwr_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
+		"scan_dev_for_boot_part="	\
+			"part list ${devtype} ${devnum} devplist; "	\
+			"env exists devplist || setenv devplist 1; "	\
+			"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "				\
+				"${devnum}:${distro_bootpart} "		\
+				"bootfstype; then "			\
+				"run scan_dev_for_boot; "		\
+			"fi; "			\
+		"done\0"			\
+	"scan_dev_for_boot="				  \
+		"echo Scanning ${devtype} "		  \
+				"${devnum}:${distro_bootpart}...; "  \
+		"for prefix in ${boot_prefixes}; do "	  \
+			"run scan_dev_for_scripts; "	  \
+		"done;"					  \
+		"\0"					  \
+	"boot_a_script="				  \
+		"load ${devtype} ${devnum}:${distro_bootpart} "  \
+			"${scriptaddr} ${prefix}${script}; "    \
+		"env exists secureboot && load ${devtype} "     \
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
+			"&& esbc_validate ${scripthdraddr};"    \
+		"source ${scriptaddr}\0"	  \
+	"installer=load mmc 0:2 $load_addr "	\
+		"/flex_installer_arm32.itb; "		\
+		"bootm $load_addr#ls1021atwr\0"	\
+	"qspi_bootcmd=echo Trying load from qspi..;"	\
+		"sf probe && sf read $load_addr "	\
+		"$kernel_addr $kernel_size && bootm $load_addr#$board\0"	\
+	"nor_bootcmd=echo Trying load from nor..;"	\
+		"cp.b $kernel_addr $load_addr "		\
+		"$kernel_size && bootm $load_addr#$board\0"
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
+	"initrd_high=0xffffffff\0"      \
+	"fdt_high=0xffffffff\0"		\
+	"fdt_addr=0x64f00000\0"		\
+	"kernel_addr=0x61000000\0"	\
+	"kernelheader_addr=0x60800000\0"	\
+	"scriptaddr=0x80000000\0"	\
+	"scripthdraddr=0x80080000\0"	\
+	"fdtheader_addr_r=0x80100000\0"	\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"	\
+	"kernelheader_size=0x40000\0"	\
+	"fdt_addr_r=0x90000000\0"	\
+	"ramdisk_addr_r=0xa0000000\0"	\
+	"load_addr=0xa0000000\0"	\
+	"kernel_size=0x2800000\0"	\
+	"kernel_addr_sd=0x8000\0"	\
+	"kernel_size_sd=0x14000\0"	\
+	"kernelhdr_addr_sd=0x4000\0"		\
+	"kernelhdr_size_sd=0x10\0"		\
+	BOOTENV				\
+	"boot_scripts=ls1021atwr_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1021atwr_bs.out\0"	\
+		"scan_dev_for_boot_part="	\
+			"part list ${devtype} ${devnum} devplist; "	\
+			"env exists devplist || setenv devplist 1; "	\
+			"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "				\
+				"${devnum}:${distro_bootpart} "		\
+				"bootfstype; then "			\
+				"run scan_dev_for_boot; "		\
+			"fi; "			\
+		"done\0"			\
+	"scan_dev_for_boot="				  \
+		"echo Scanning ${devtype} "		  \
+				"${devnum}:${distro_bootpart}...; "  \
+		"for prefix in ${boot_prefixes}; do "	  \
+			"run scan_dev_for_scripts; "	  \
+		"done;"					  \
+		"\0"					  \
+	"boot_a_script="				  \
+		"load ${devtype} ${devnum}:${distro_bootpart} "  \
+			"${scriptaddr} ${prefix}${script}; "    \
+		"env exists secureboot && load ${devtype} "     \
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+			"&& esbc_validate ${scripthdraddr};"    \
+		"source ${scriptaddr}\0"	  \
+	"qspi_bootcmd=echo Trying load from qspi..;"	\
+		"sf probe && sf read $load_addr "	\
+		"$kernel_addr $kernel_size; env exists secureboot "	\
+		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0" \
+	"nor_bootcmd=echo Trying load from nor..;"	\
+		"cp.b $kernel_addr $load_addr "		\
+		"$kernel_size; env exists secureboot "	\
+		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"	\
+	"sd_bootcmd=echo Trying load from SD ..;"       \
+		"mmcinfo && mmc read $load_addr "	\
+		"$kernel_addr_sd $kernel_size_sd && "	\
+		"env exists secureboot && mmc read $kernelheader_addr_r "		\
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"
+#endif
+
+#undef CONFIG_BOOTCOMMAND
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
+			   "env exists secureboot && esbc_halt"
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;"
+#else
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;"	\
+			   "env exists secureboot && esbc_halt;"
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+#define CONFIG_LS102XA_STREAM_ID
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
+
+#define CONFIG_SYS_QE_FW_ADDR     0x60940000
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET		0x300000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x20000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x300000
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#else
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
+#endif
+
+#include <asm/fsl_secure_boot.h>
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+#endif
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
new file mode 100644
index 0000000..40fcd22
--- /dev/null
+++ b/include/configs/ls1028a_common.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __L1028A_COMMON_H
+#define __L1028A_COMMON_H
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_MP
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+#include <asm/arch/soc.h>
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE	0x2080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	1
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START        0x80000000
+#define CONFIG_SYS_MEMTEST_END          0x9fffffff
+
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR		secondary_boot_func
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* I2C */
+#ifndef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C
+#endif
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX       1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0)
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"board=ls1028ardb\0"			\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x00f00000\0"                 \
+	"kernel_addr=0x01000000\0"              \
+	"scriptaddr=0x80000000\0"               \
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"         \
+	"kernelheader_addr_r=0x80200000\0"      \
+	"load_addr=0xa0000000\0"            \
+	"kernel_addr_r=0x81000000\0"            \
+	"fdt_addr_r=0x90000000\0"               \
+	"ramdisk_addr_r=0xa0000000\0"           \
+	"kernel_start=0x1000000\0"		\
+	"kernelheader_start=0x800000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernel_size_sd=0x14000\0"		\
+	"kernelhdr_addr_sd=0x4000\0"		\
+	"kernelhdr_size_sd=0x10\0"		\
+	"console=ttyS0,115200\0"                \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"	\
+	BOOTENV					\
+	"boot_scripts=ls1028ardb_boot.scr\0"    \
+	"boot_script_hdr=hdr_ls1028ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="               \
+		"part list ${devtype} ${devnum} devplist; "   \
+		"env exists devplist || setenv devplist 1; "  \
+		"for distro_bootpart in ${devplist}; do "     \
+		  "if fstype ${devtype} "                  \
+			"${devnum}:${distro_bootpart} "      \
+			"bootfstype; then "                  \
+			"run scan_dev_for_boot; "            \
+		  "fi; "                                   \
+		"done\0"                                   \
+	"scan_dev_for_boot="				  \
+		"echo Scanning ${devtype} "		  \
+				"${devnum}:${distro_bootpart}...; "  \
+		"for prefix in ${boot_prefixes}; do "	  \
+			"run scan_dev_for_scripts; "	  \
+		"done;"					  \
+		"\0"					  \
+	"boot_a_script="				  \
+		"load ${devtype} ${devnum}:${distro_bootpart} "  \
+			"${scriptaddr} ${prefix}${script}; "    \
+		"env exists secureboot && load ${devtype} "     \
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+			"&& esbc_validate ${scripthdraddr};"    \
+		"source ${scriptaddr}\0"	  \
+	"sd_bootcmd=echo Trying load from SD ..;"	\
+		"mmcinfo; mmc read $load_addr "		\
+		"$kernel_addr_sd $kernel_size_sd && "	\
+		"env exists secureboot && mmc read $kernelheader_addr_r " \
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"		\
+	"emmc_bootcmd=echo Trying load from EMMC ..;"	\
+		"mmcinfo; mmc dev 1; mmc read $load_addr "		\
+		"$kernel_addr_sd $kernel_size_sd && "	\
+		"env exists secureboot && mmc read $kernelheader_addr_r " \
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"
+
+#undef CONFIG_BOOTCOMMAND
+
+#define SD_BOOTCOMMAND	\
+	"run distro_bootcmd;run sd_bootcmd; " \
+	"env exists secureboot && esbc_halt;"
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+
+#ifndef CONFIG_CMDLINE_EDITING
+#define CONFIG_CMDLINE_EDITING		1
+#endif
+
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define OCRAM_NONSECURE_SIZE		0x00010000
+#define CONFIG_ENV_OFFSET              0x500000        /* 5MB */
+#define CONFIG_SYS_FSL_QSPI_BASE	0x20000000
+#define CONFIG_ENV_ADDR	CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_SECT_SIZE           0x40000
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
+#define I2C_MUX_CH_DEFAULT              0x8
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+/* Ethernet */
+/* smallest ENETC BD ring has 8 entries */
+#define CONFIG_SYS_RX_ETH_BUFFER		8
+
+#endif /* __L1028A_COMMON_H */
diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
new file mode 100644
index 0000000..b0e9441
--- /dev/null
+++ b/include/configs/ls1028aqds.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1028A_QDS_H
+#define __LS1028A_QDS_H
+
+#include "ls1028a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ / 4)
+
+/* DDR */
+#define CONFIG_DIMM_SLOTS_PER_CTLR		2
+
+#define CONFIG_QIXIS_I2C_ACCESS
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE			0x7fb00000
+#define QIXIS_BASE_PHYS			QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_SWITCH		1
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		5
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x00
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_LBMAP_EMMC		0x00
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_SD		0x8
+#define QIXIS_RCW_SRC_EMMC		0x9
+#define QIXIS_RCW_SRC_QSPI		0xf
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_NOR_MODE_AVD_NOR | \
+					CSOR_NOR_TRHZ_80)
+#endif
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM         1
+#define I2C_MUX_CH_RTC                 0xB
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_SIZE			0x2000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+/* DSPI */
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifndef SPL_NO_ENV
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"board=ls1028aqds\0" \
+	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
+	"ramdisk_addr=0x800000\0" \
+	"ramdisk_size=0x2000000\0" \
+	"fdt_high=0xffffffffffffffff\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"fdt_addr=0x00f00000\0" \
+	"kernel_addr=0x01000000\0" \
+	"scriptaddr=0x80000000\0" \
+	"scripthdraddr=0x80080000\0" \
+	"fdtheader_addr_r=0x80100000\0" \
+	"kernelheader_addr_r=0x80200000\0" \
+	"load_addr=0xa0000000\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"fdt_addr_r=0x90000000\0" \
+	"ramdisk_addr_r=0xa0000000\0" \
+	"kernel_start=0x1000000\0" \
+	"kernelheader_start=0x800000\0" \
+	"kernel_load=0xa0000000\0" \
+	"kernel_size=0x2800000\0" \
+	"kernelheader_size=0x40000\0" \
+	"kernel_addr_sd=0x8000\0" \
+	"kernel_size_sd=0x14000\0" \
+	"kernelhdr_addr_sd=0x4000\0" \
+	"kernelhdr_size_sd=0x10\0" \
+	"console=ttyS0,115200\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	BOOTENV \
+	"boot_scripts=ls1028aqds_boot.scr\0" \
+	"boot_script_hdr=hdr_ls1028aqds_bs.out\0" \
+	"scan_dev_for_boot_part=" \
+		"part list ${devtype} ${devnum} devplist; " \
+		"env exists devplist || setenv devplist 1; " \
+		"for distro_bootpart in ${devplist}; do " \
+		  "if fstype ${devtype} " \
+			"${devnum}:${distro_bootpart} " \
+			"bootfstype; then " \
+			"run scan_dev_for_boot; " \
+		  "fi; " \
+		"done\0" \
+	"scan_dev_for_boot=" \
+		"echo Scanning ${devtype} " \
+				"${devnum}:${distro_bootpart}...; " \
+		"for prefix in ${boot_prefixes}; do " \
+			"run scan_dev_for_scripts; " \
+		"done;" \
+		"\0" \
+	"boot_a_script=" \
+		"load ${devtype} ${devnum}:${distro_bootpart} " \
+			"${scriptaddr} ${prefix}${script}; " \
+		"env exists secureboot && load ${devtype} " \
+			"${devnum}:${distro_bootpart} " \
+			"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+			"&& esbc_validate ${scripthdraddr};" \
+		"source ${scriptaddr}\0" \
+	"sd_bootcmd=echo Trying load from SD ..;" \
+		"mmcinfo; mmc read $load_addr " \
+		"$kernel_addr_sd $kernel_size_sd && " \
+		"env exists secureboot && mmc read $kernelheader_addr_r " \
+		"$kernelhdr_addr_sd $kernelhdr_size_sd " \
+		" && esbc_validate ${kernelheader_addr_r};" \
+		"bootm $load_addr#$board\0" \
+	"emmc_bootcmd=echo Trying load from EMMC ..;" \
+		"mmcinfo; mmc dev 1; mmc read $load_addr " \
+		"$kernel_addr_sd $kernel_size_sd && " \
+		"env exists secureboot && mmc read $kernelheader_addr_r " \
+		"$kernelhdr_addr_sd $kernelhdr_size_sd " \
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"
+#endif
+#endif /* __LS1028A_QDS_H */
diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h
new file mode 100644
index 0000000..b77c36d
--- /dev/null
+++ b/include/configs/ls1028ardb.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1028A_RDB_H
+#define __LS1028A_RDB_H
+
+#include "ls1028a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ / 4)
+
+#define CONFIG_SYS_RTC_BUS_NUM         0
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_SIZE			0x2000
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR          1
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_QIXIS_I2C_ACCESS
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE			0x7fb00000
+#define QIXIS_BASE_PHYS			QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_SWITCH		2
+#define QIXIS_LBMAP_MASK		0xe0
+#define QIXIS_LBMAP_SHIFT		0x5
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x00
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_LBMAP_EMMC		0x00
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_SD		0xf8
+#define QIXIS_RCW_SRC_EMMC		0xf9
+#define QIXIS_RCW_SRC_QSPI		0xff
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x10
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x11
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_NOR_MODE_AVD_NOR | \
+					CSOR_NOR_TRHZ_80)
+#endif
+
+/* SATA */
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define SCSI_VEND_ID 0x1b4b
+#define SCSI_DEV_ID  0x9170
+#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
+
+#endif /* __LS1028A_RDB_H */
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
new file mode 100644
index 0000000..70447a2
--- /dev/null
+++ b/include/configs/ls1043a_common.h
@@ -0,0 +1,336 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor
+ */
+
+#ifndef __LS1043A_COMMON_H
+#define __LS1043A_COMMON_H
+
+/* SPL build */
+#ifdef CONFIG_SPL_BUILD
+#define SPL_NO_FMAN
+#define SPL_NO_DSPI
+#define SPL_NO_PCIE
+#define SPL_NO_ENV
+#define SPL_NO_MISC
+#define SPL_NO_USB
+#define SPL_NO_SATA
+#define SPL_NO_QE
+#define SPL_NO_EEPROM
+#endif
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
+#define SPL_NO_MMC
+#endif
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
+#define SPL_NO_IFC
+#endif
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_GICV2
+
+#include <asm/arch/stream_id_lsch2.h>
+#include <asm/arch/config.h>
+
+/* Link Definitions */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
+
+#define CPU_RELEASE_ADDR               secondary_boot_func
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* SD boot SPL */
+#ifdef CONFIG_SD_BOOT
+
+#define CONFIG_SPL_MAX_SIZE		0x17000
+#define CONFIG_SPL_STACK		0x1001e000
+#define CONFIG_SPL_PAD_TO		0x1d000
+
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw u-boot image instead of fit image.
+ */
+#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN		0x100000
+#endif /* ifdef CONFIG_SECURE_BOOT */
+#endif
+
+/* NAND SPL */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PBL_PAD
+#define CONFIG_SPL_MAX_SIZE		0x1a000
+#define CONFIG_SPL_STACK		0x1001d000
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
+#endif /* ifdef CONFIG_SECURE_BOOT */
+
+#ifdef CONFIG_U_BOOT_HDR_SIZE
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw u-boot image instead of fit image.
+ */
+#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN		0x100000
+#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
+
+#endif
+
+/* IFC */
+#ifndef SPL_NO_IFC
+#if defined(CONFIG_TFABOOT) || \
+	(!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI))
+#define CONFIG_FSL_IFC
+/*
+ * CONFIG_SYS_FLASH_BASE has the final address (core view)
+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
+ */
+#define CONFIG_SYS_FLASH_BASE			0x60000000
+#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
+
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+#endif
+#endif
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+
+/* PCIe */
+#ifndef SPL_NO_PCIE
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+#endif
+
+/* Command line configuration */
+
+/*  MMC  */
+#ifndef SPL_NO_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+#endif
+
+/*  DSPI  */
+#ifndef SPL_NO_DSPI
+#define CONFIG_FSL_DSPI
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_DM_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
+#define CONFIG_SPI_FLASH_SST		/* cs1 */
+#define CONFIG_SPI_FLASH_EON		/* cs2 */
+#endif
+#endif
+
+/* FMan ucode */
+#ifndef SPL_NO_FMAN
+#define CONFIG_SYS_DPAA_FMAN
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_FMAN_FW_ADDR		0x900000
+#define CONFIG_SYS_QE_FW_ADDR		0x940000
+
+
+#else
+#ifdef CONFIG_NAND_BOOT
+/* Store Fman ucode at offeset 0x900000(72 blocks). */
+#define CONFIG_SYS_FMAN_FW_ADDR		(72 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SD_BOOT)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2040 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
+#define CONFIG_SYS_QE_FW_ADDR		(512 * 0x4A00)
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
+#else
+/* FMan fireware Pre-load address */
+#define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
+#define CONFIG_SYS_QE_FW_ADDR		0x60940000
+#endif
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+#ifndef SPL_NO_MISC
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x64f00000\0"		 	\
+	"kernel_addr=0x61000000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"kernel_start=0x1000000\0"		\
+	"kernelheader_start=0x800000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernelheader_addr=0x60800000\0"	\
+	"kernel_size=0x2800000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernel_size_sd=0x14000\0"		\
+	"kernelhdr_addr_sd=0x4000\0"		\
+	"kernelhdr_size_sd=0x10\0"		\
+	"console=ttyS0,115200\0"		\
+	"boot_os=y\0"				\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"	\
+	BOOTENV					\
+	"boot_scripts=ls1043ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1043ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+		"part list ${devtype} ${devnum} devplist; "	\
+		"env exists devplist || setenv devplist 1; "	\
+		"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "			\
+				"${devnum}:${distro_bootpart} "	\
+				"bootfstype; then "		\
+				"run scan_dev_for_boot; "	\
+			"fi; "					\
+		"done\0"			\
+	"boot_a_script="					\
+		"load ${devtype} ${devnum}:${distro_bootpart} "	\
+			"${scriptaddr} ${prefix}${script}; "	\
+		"env exists secureboot && load ${devtype} "	\
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
+			"&& esbc_validate ${scripthdraddr};"	\
+		"source ${scriptaddr}\0"			\
+	"qspi_bootcmd=echo Trying load from qspi..;"	\
+		"sf probe && sf read $load_addr "	\
+		"$kernel_addr $kernel_size; env exists secureboot "	\
+		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"	\
+	"nor_bootcmd=echo Trying load from nor..;"	\
+		"cp.b $kernel_addr $load_addr "	\
+		"$kernel_size; env exists secureboot "	\
+		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"	    \
+	"nand_bootcmd=echo Trying load from NAND..;"	\
+		"nand info; nand read $load_addr "	\
+		"$kernel_start $kernel_size; env exists secureboot "	\
+		"&& nand read $kernelheader_addr_r $kernelheader_start "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"	\
+	"sd_bootcmd=echo Trying load from SD ..;"       \
+		"mmcinfo; mmc read $load_addr "         \
+		"$kernel_addr_sd $kernel_size_sd && "     \
+		"env exists secureboot && mmc read $kernelheader_addr_r "		\
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"
+
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;"
+#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "  \
+			   "env exists secureboot && esbc_halt;"
+#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;"
+#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;"
+#else
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;"
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "  \
+			   "env exists secureboot && esbc_halt;"
+#else
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;"
+#endif
+#endif
+#endif
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#include <asm/arch/soc.h>
+
+#endif /* __LS1043A_COMMON_H */
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
new file mode 100644
index 0000000..0ea3ca0
--- /dev/null
+++ b/include/configs/ls1043aqds.h
@@ -0,0 +1,445 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __LS1043AQDS_H__
+#define __LS1043AQDS_H__
+
+#include "ls1043a_common.h"
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_DDR_SPD
+#define SPD_EEPROM_ADDRESS		0x51
+#define CONFIG_SYS_SPD_BUS_NUM		0
+
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHYLIB_10G
+#define RGMII_PHY1_ADDR		0x1
+#define RGMII_PHY2_ADDR		0x2
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+/* PHY address on QSGMII riser card on slot 1 */
+#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
+#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
+#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
+#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
+/* PHY address on QSGMII riser card on slot 2 */
+#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
+#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
+#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
+#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
+#endif
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW \
+	board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
+#endif
+#endif
+
+/* LPUART */
+#ifdef CONFIG_LPUART
+#define CONFIG_LPUART_32B_REG
+#endif
+
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
+/*
+ * IFC Definitions
+ */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
+
+#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_TRHZ_80)
+#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
+					FTIM0_NOR_TEADC(0x5) | \
+					FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
+					FTIM1_NOR_TRAD_NOR(0x1a) | \
+					FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
+					FTIM2_NOR_TCH(0x4) | \
+					FTIM2_NOR_TWPH(0xe) | \
+					FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3		0
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
+					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+
+#define CONFIG_SYS_NAND_BASE		0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	\
+				| CSPR_MSEL_NAND	\
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x7) | \
+					FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0xe)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+					FTIM2_NAND_TREH(0xa) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3           0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PAD_TO		0x20000		/* block aligned */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
+#endif
+
+#if defined(CONFIG_TFABOOT) || \
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+#endif
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE			0x7fb00000
+#define QIXIS_BASE_PHYS			QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_LBMAP_SD_QSPI		0xff
+#define QIXIS_LBMAP_QSPI		0xff
+#define QIXIS_RCW_SRC_NAND		0x106
+#define QIXIS_RCW_SRC_SD		0x040
+#define QIXIS_RCW_SRC_QSPI		0x045
+#define QIXIS_RST_CTL_RESET		0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+
+#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_NOR_MODE_AVD_NOR | \
+					CSOR_NOR_TRHZ_80)
+
+/*
+ * QIXIS Timing parameters for IFC GPCM
+ */
+#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xc) | \
+					FTIM0_GPCM_TEADC(0x20) | \
+					FTIM0_GPCM_TEAHC(0x10))
+#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0x50) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0x8) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0xf0))
+#define CONFIG_SYS_FPGA_FTIM3		0x0
+#endif
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#else
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#endif
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI		0x77
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR		0x18
+#define I2C_MUX_CH_DEFAULT		0x8
+#define I2C_MUX_CH_CH7301		0xC
+#define I2C_MUX_CH5			0xD
+#define I2C_MUX_CH7			0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR           0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
+
+#define CONFIG_VID_FLS_ENV		"ls1043aqds_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_INA220
+/* The lowest and highest voltage allowed for LS1043AQDS */
+#define VDD_MV_MIN			819
+#define VDD_MV_MAX			1212
+
+/* QSPI device */
+#if defined(CONFIG_TFABOOT) || \
+	(defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI))
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x500000        /* 5MB */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x500000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#else
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(24 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#else
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x20000
+#endif
+#endif
+
+#define CONFIG_CMDLINE_TAG
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1043AQDS_H__ */
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
new file mode 100644
index 0000000..d2979ef
--- /dev/null
+++ b/include/configs/ls1043ardb.h
@@ -0,0 +1,310 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor
+ */
+
+#ifndef __LS1043ARDB_H__
+#define __LS1043ARDB_H__
+
+#include "ls1043a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_SYS_SPD_BUS_NUM		0
+
+#ifndef CONFIG_SPL
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
+#endif
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x90000000
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x10000
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x500
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	30
+#endif
+
+/*
+ * NOR Flash Definitions
+ */
+#define CONFIG_SYS_NOR_CSPR_EXT		(0x0)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_TRHZ_80)
+#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x1) | \
+					FTIM0_NOR_TEADC(0x1) | \
+					FTIM0_NOR_TAVDS(0x0) | \
+					FTIM0_NOR_TEAHC(0xc))
+#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x1c) | \
+					FTIM1_NOR_TRAD_NOR(0xb) | \
+					FTIM1_NOR_TSEQRAD_NOR(0x9))
+#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x1) | \
+					FTIM2_NOR_TCH(0x4) | \
+					FTIM2_NOR_TWPH(0x8) | \
+					FTIM2_NOR_TWP(0x10))
+#define CONFIG_SYS_NOR_FTIM3		0
+#define CONFIG_SYS_IFC_CCR		0x01000000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+/*
+ * NAND Flash Definitions
+ */
+#ifndef SPL_NO_IFC
+#define CONFIG_NAND_FSL_IFC
+#endif
+
+#define CONFIG_SYS_NAND_BASE		0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	\
+				| CSPR_MSEL_NAND	\
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x7) | \
+					FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0xe)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+					FTIM2_NAND_TREH(0xa) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PAD_TO		0x20000		/* block aligned */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(1024 << 10)
+#endif
+
+/*
+ * CPLD
+ */
+#define CONFIG_SYS_CPLD_BASE		0x7fb00000
+#define CPLD_BASE_PHYS			CONFIG_SYS_CPLD_BASE
+
+#define CONFIG_SYS_CPLD_CSPR_EXT	(0x0)
+#define CONFIG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CPLD_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_NOR_MODE_AVD_NOR | \
+					CSOR_NOR_TRHZ_80)
+
+/* CPLD Timing parameters for IFC GPCM */
+#define CONFIG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
+					FTIM0_GPCM_TEADC(0xf) | \
+					FTIM0_GPCM_TEAHC(0xf))
+#define CONFIG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0xff))
+#define CONFIG_SYS_CPLD_FTIM3		0x0
+
+/* IFC Timing Params */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#else
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+#endif
+
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_CPLD_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_CPLD_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_CPLD_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_CPLD_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_CPLD_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3
+
+/* EEPROM */
+#ifndef SPL_NO_EEPROM
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#endif
+
+/*
+ * Environment
+ */
+#ifndef SPL_NO_ENV
+#define CONFIG_ENV_OVERWRITE
+#endif
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x500000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x500000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#else
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(24 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#else
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x20000
+#endif
+#endif
+
+/* FMan */
+#ifndef SPL_NO_FMAN
+#define AQR105_IRQ_MASK			0x40000000
+
+#ifdef CONFIG_NET
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define RGMII_PHY1_ADDR			0x1
+#define RGMII_PHY2_ADDR			0x2
+
+#define QSGMII_PORT1_PHY_ADDR		0x4
+#define QSGMII_PORT2_PHY_ADDR		0x5
+#define QSGMII_PORT3_PHY_ADDR		0x6
+#define QSGMII_PORT4_PHY_ADDR		0x7
+
+#define FM1_10GEC1_PHY_ADDR		0x1
+
+#define CONFIG_ETHPRIME			"FM1@DTSEC3"
+#endif
+#endif
+
+/* SATA */
+#ifndef SPL_NO_SATA
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		2
+#define CONFIG_SYS_SCSI_MAX_LUN			2
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define SCSI_VEND_ID 0x1b4b
+#define SCSI_DEV_ID  0x9170
+#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1043ARDB_H__ */
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h
new file mode 100644
index 0000000..59c43f1
--- /dev/null
+++ b/include/configs/ls1046a_common.h
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1046A_COMMON_H
+#define __LS1046A_COMMON_H
+
+/* SPL build */
+#ifdef CONFIG_SPL_BUILD
+#define SPL_NO_QBMAN
+#define SPL_NO_FMAN
+#define SPL_NO_ENV
+#define SPL_NO_MISC
+#define SPL_NO_QSPI
+#define SPL_NO_USB
+#define SPL_NO_SATA
+#endif
+#if defined(CONFIG_SPL_BUILD) && \
+	(defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT))
+#define SPL_NO_MMC
+#endif
+#if defined(CONFIG_SPL_BUILD)		&& \
+	!defined(CONFIG_SPL_FSL_LS_PPA)
+#define SPL_NO_IFC
+#endif
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_GICV2
+
+#include <asm/arch/config.h>
+#include <asm/arch/stream_id_lsch2.h>
+
+/* Link Definitions */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
+
+#define CPU_RELEASE_ADDR               secondary_boot_func
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* SD boot SPL */
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SPL_MAX_SIZE		0x1f000		/* 124 KiB */
+#define CONFIG_SPL_STACK		0x10020000
+#define CONFIG_SPL_PAD_TO		0x21000		/* 132 KiB */
+#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw u-boot image instead of fit image.
+ */
+#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN		0x100000
+#endif /* ifdef CONFIG_SECURE_BOOT */
+#endif
+
+#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL)
+#define CONFIG_SPL_TARGET		"spl/u-boot-spl.pbl"
+#define CONFIG_SPL_MAX_SIZE		0x1f000
+#define CONFIG_SPL_STACK		0x10020000
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SYS_MONITOR_LEN		0x100000
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#endif
+
+/* NAND SPL */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PBL_PAD
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_MAX_SIZE		0x17000		/* 90 KiB */
+#define CONFIG_SPL_STACK		0x1001f000
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SYS_MONITOR_LEN		0xa0000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+
+/* PCIe */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* SATA */
+#ifndef SPL_NO_SATA
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+/* Command line configuration */
+
+/* MMC */
+#ifndef SPL_NO_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+#endif
+
+/* FMan ucode */
+#ifndef SPL_NO_FMAN
+#define CONFIG_SYS_DPAA_FMAN
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#endif
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_FMAN_FW_ADDR		0x900000
+#else
+#ifdef CONFIG_SD_BOOT
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800).
+ */
+#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
+#elif defined(CONFIG_NAND_BOOT)
+#define CONFIG_SYS_FMAN_FW_ADDR		(36 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
+#endif
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(SCSI, scsi, 0) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#endif
+
+#if defined(CONFIG_TARGET_LS1046AFRWY)
+#define LS1046A_BOOT_SRC_AND_HDR\
+	"boot_scripts=ls1046afrwy_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
+#else
+#define LS1046A_BOOT_SRC_AND_HDR\
+	"boot_scripts=ls1046ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1046ardb_bs.out\0"
+#endif
+#ifndef SPL_NO_MISC
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x64f00000\0"                 \
+	"kernel_addr=0x65000000\0"              \
+	"scriptaddr=0x80000000\0"               \
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"         \
+	"kernelheader_addr_r=0x80200000\0"      \
+	"load_addr=0xa0000000\0"            \
+	"kernel_addr_r=0x81000000\0"            \
+	"fdt_addr_r=0x90000000\0"               \
+	"ramdisk_addr_r=0xa0000000\0"           \
+	"kernel_start=0x1000000\0"		\
+	"kernelheader_start=0x800000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernel_size_sd=0x14000\0"		\
+	"kernelhdr_addr_sd=0x4000\0"		\
+	"kernelhdr_size_sd=0x10\0"		\
+	"console=ttyS0,115200\0"                \
+	 CONFIG_MTDPARTS_DEFAULT "\0"		\
+	BOOTENV					\
+	LS1046A_BOOT_SRC_AND_HDR		\
+	"scan_dev_for_boot_part="               \
+		"part list ${devtype} ${devnum} devplist; "   \
+		"env exists devplist || setenv devplist 1; "  \
+		"for distro_bootpart in ${devplist}; do "     \
+		  "if fstype ${devtype} "                  \
+			"${devnum}:${distro_bootpart} "      \
+			"bootfstype; then "                  \
+			"run scan_dev_for_boot; "            \
+		  "fi; "                                   \
+		"done\0"                                   \
+	"boot_a_script="				  \
+		"load ${devtype} ${devnum}:${distro_bootpart} "  \
+			"${scriptaddr} ${prefix}${script}; "    \
+		"env exists secureboot && load ${devtype} "     \
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
+			"&& esbc_validate ${scripthdraddr};"	\
+		"source ${scriptaddr}\0"	  \
+	"qspi_bootcmd=echo Trying load from qspi..;"      \
+		"sf probe && sf read $load_addr "         \
+		"$kernel_start $kernel_size; env exists secureboot "	\
+		"&& sf read $kernelheader_addr_r $kernelheader_start "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+		"bootm $load_addr#$board\0"		\
+	"sd_bootcmd=echo Trying load from SD ..;"	\
+		"mmcinfo; mmc read $load_addr "		\
+		"$kernel_addr_sd $kernel_size_sd && "	\
+		"env exists secureboot && mmc read $kernelheader_addr_r "		\
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$board\0"
+
+#endif
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#include <asm/arch/soc.h>
+
+#endif /* __LS1046A_COMMON_H */
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h
new file mode 100644
index 0000000..8609ebf
--- /dev/null
+++ b/include/configs/ls1046afrwy.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1046AFRWY_H__
+#define __LS1046AFRWY_H__
+
+#include "ls1046a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   4
+
+#define CONFIG_SYS_UBOOT_BASE		0x40100000
+
+/* IFC */
+#define CONFIG_FSL_IFC
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+
+#define CONFIG_SYS_NAND_BASE		0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	\
+				| CSPR_MSEL_NAND	\
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_128	/* Spare size = 128 */ \
+				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x7) | \
+					FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0xe)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+					FTIM2_NAND_TREH(0xa) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* IFC Timing Params */
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define I2C_RETIMER_ADDR			0x18
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR_PRI			0x77 /* Primary Mux*/
+#define I2C_MUX_CH_DEFAULT			0x1 /* Channel 0*/
+#define I2C_MUX_CH_RTC				0x1 /* Channel 0*/
+
+/* RTC */
+#define RTC
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51  /* Channel 0 I2C bus 0*/
+#define CONFIG_SYS_RTC_BUS_NUM			0
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_ENV_SIZE			0x2000		/* 8KB */
+#define CONFIG_ENV_OFFSET		0x500000	/* 5MB */
+#define CONFIG_ENV_SECT_SIZE		0x40000		/* 256KB */
+#define CONFIG_SYS_FSL_QSPI_BASE	0x40000000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FSL_QSPI_BASE + \
+					 CONFIG_ENV_OFFSET)
+
+/* FMan */
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+
+#define QSGMII_PORT1_PHY_ADDR		0x1c
+#define QSGMII_PORT2_PHY_ADDR		0x1d
+#define QSGMII_PORT3_PHY_ADDR		0x1e
+#define QSGMII_PORT4_PHY_ADDR		0x1f
+
+#define FDT_SEQ_MACADDR_FROM_ENV
+
+#define CONFIG_ETHPRIME			"FM1@DTSEC3"
+
+#endif
+
+/* QSPI device */
+#ifdef CONFIG_FSL_QSPI
+#define FSL_QSPI_FLASH_SIZE		SZ_64M
+#define FSL_QSPI_FLASH_NUM		1
+#endif
+
+#undef CONFIG_BOOTCOMMAND
+#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;;"
+#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1046AFRWY_H__ */
diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h
new file mode 100644
index 0000000..eea738e
--- /dev/null
+++ b/include/configs/ls1046aqds.h
@@ -0,0 +1,478 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __LS1046AQDS_H__
+#define __LS1046AQDS_H__
+
+#include "ls1046a_common.h"
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_DDR_SPD
+#define SPD_EEPROM_ADDRESS		0x51
+#define CONFIG_SYS_SPD_BUS_NUM		0
+
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
+#endif
+
+/* DSPI */
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
+#define CONFIG_SPI_FLASH_SST		/* cs1 */
+#define CONFIG_SPI_FLASH_EON		/* cs2 */
+#endif
+
+/* QSPI */
+#if defined(CONFIG_TFABOOT) ||	\
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+#endif
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHYLIB_10G
+#define RGMII_PHY1_ADDR		0x1
+#define RGMII_PHY2_ADDR		0x2
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+/* PHY address on QSGMII riser card on slot 2 */
+#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
+#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
+#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
+#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
+#endif
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI \
+	board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW \
+	board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#ifdef CONFIG_SD_BOOT_QSPI
+#define CONFIG_SYS_FSL_PBL_RCW \
+	board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_RCW \
+	board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
+#endif
+#endif
+
+/* IFC */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define	CONFIG_FSL_IFC
+/*
+ * CONFIG_SYS_FLASH_BASE has the final address (core view)
+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
+ */
+#define CONFIG_SYS_FLASH_BASE			0x60000000
+#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
+
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+#endif
+#endif
+
+/* LPUART */
+#ifdef CONFIG_LPUART
+#define CONFIG_LPUART_32B_REG
+#define CFG_UART_MUX_MASK	0x6
+#define CFG_UART_MUX_SHIFT	1
+#define CFG_LPUART_EN		0x2
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+/*
+ * IFC Definitions
+ */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
+
+#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_TRHZ_80)
+#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
+					FTIM0_NOR_TEADC(0x5) | \
+					FTIM0_NOR_TAVDS(0x6) | \
+					FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
+					FTIM1_NOR_TRAD_NOR(0x1a) | \
+					FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x8) | \
+					FTIM2_NOR_TCH(0x8) | \
+					FTIM2_NOR_TWPH(0xe) | \
+					FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3		0
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
+					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+
+#define CONFIG_SYS_NAND_BASE		0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	\
+				| CSPR_MSEL_NAND	\
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
+				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x7) | \
+					FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0xe)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+					FTIM2_NAND_TREH(0xa) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3           0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * 1024)
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PAD_TO		0x40000		/* block aligned */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#endif
+
+#if defined(CONFIG_TFABOOT) || \
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_EARLY_INIT
+#endif
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define QIXIS_BASE			0x7fb00000
+#define QIXIS_BASE_PHYS			QIXIS_BASE
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_LBMAP_SD_QSPI		0xff
+#define QIXIS_LBMAP_QSPI		0xff
+#define QIXIS_RCW_SRC_NAND		0x110
+#define QIXIS_RCW_SRC_SD		0x040
+#define QIXIS_RCW_SRC_QSPI		0x045
+#define QIXIS_RST_CTL_RESET		0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+
+#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+					CSOR_NOR_NOR_MODE_AVD_NOR | \
+					CSOR_NOR_TRHZ_80)
+
+/*
+ * QIXIS Timing parameters for IFC GPCM
+ */
+#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xc) | \
+					FTIM0_GPCM_TEADC(0x20) | \
+					FTIM0_GPCM_TEAHC(0x10))
+#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0x50) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0x8) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0xf0))
+#define CONFIG_SYS_FPGA_FTIM3		0x0
+#endif
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#else
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
+#endif
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI		0x77
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR		0x18
+#define I2C_MUX_CH_DEFAULT		0x8
+#define I2C_MUX_CH_CH7301		0xC
+#define I2C_MUX_CH5			0xD
+#define I2C_MUX_CH6			0xE
+#define I2C_MUX_CH7			0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR           0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
+
+#define CONFIG_VID_FLS_ENV		"ls1046aqds_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_INA220
+/* The lowest and highest voltage allowed for LS1046AQDS */
+#define VDD_MV_MIN			819
+#define VDD_MV_MAX			1212
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x500000        /* 5MB */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x500000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#else
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(12 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#else
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x20000
+#endif
+#endif
+
+#define CONFIG_CMDLINE_TAG
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
+					"e0000 f00000 && bootm $kernel_load"
+#define IFC_NOR_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
+					"$kernel_size && bootm $kernel_load"
+#define SD_BOOTCOMMAND		"mmc info; mmc read $kernel_load"     \
+					"$kernel_addr_sd $kernel_size_sd && bootm $kernel_load"
+#else
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
+					"e0000 f00000 && bootm $kernel_load"
+#else
+#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
+					"$kernel_size && bootm $kernel_load"
+#endif
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1046AQDS_H__ */
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h
new file mode 100644
index 0000000..2d20f15
--- /dev/null
+++ b/include/configs/ls1046ardb.h
@@ -0,0 +1,233 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LS1046ARDB_H__
+#define __LS1046ARDB_H__
+
+#include "ls1046a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_DDR_SPD
+#define SPD_EEPROM_ADDRESS		0x51
+#define CONFIG_SYS_SPD_BUS_NUM		0
+
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg
+#ifdef CONFIG_EMMC_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW \
+	board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg
+#else
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg
+#endif
+#elif defined(CONFIG_QSPI_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW \
+	board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
+#define CONFIG_SYS_FSL_PBL_PBI \
+	board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
+#define CONFIG_SYS_UBOOT_BASE		0x40100000
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x90000000
+#endif
+
+#ifndef SPL_NO_IFC
+/* IFC */
+#define CONFIG_FSL_IFC
+/*
+ * NAND Flash Definitions
+ */
+#define CONFIG_NAND_FSL_IFC
+#endif
+
+#define CONFIG_SYS_NAND_BASE		0x7e800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	\
+				| CSPR_MSEL_NAND	\
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_8	/* 8-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
+				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x7) | \
+					FTIM0_NAND_TWH(0xa))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0xe)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
+					FTIM2_NAND_TREH(0xa) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/*
+ * CPLD
+ */
+#define CONFIG_SYS_CPLD_BASE		0x7fb00000
+#define CPLD_BASE_PHYS			CONFIG_SYS_CPLD_BASE
+
+#define CONFIG_SYS_CPLD_CSPR_EXT	(0x0)
+#define CONFIG_SYS_CPLD_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+					CSPR_PORT_SIZE_8 | \
+					CSPR_MSEL_GPCM | \
+					CSPR_V)
+#define CONFIG_SYS_CPLD_AMASK		IFC_AMASK(64 * 1024)
+#define CONFIG_SYS_CPLD_CSOR		CSOR_NOR_ADM_SHIFT(16)
+
+/* CPLD Timing parameters for IFC GPCM */
+#define CONFIG_SYS_CPLD_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CPLD_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CPLD_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0x3E))
+#define CONFIG_SYS_CPLD_FTIM3		0x0
+
+/* IFC Timing Params */
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_CPLD_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_CPLD_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_CPLD_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_CPLD_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_CPLD_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define I2C_RETIMER_ADDR			0x18
+
+/* PMIC */
+#define CONFIG_POWER
+#ifdef CONFIG_POWER
+#define CONFIG_POWER_I2C
+#endif
+
+/*
+ * Environment
+ */
+#ifndef SPL_NO_ENV
+#define CONFIG_ENV_OVERWRITE
+#endif
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_ENV_SIZE			0x2000		/* 8KB */
+#define CONFIG_ENV_OFFSET		0x500000	/* 5MB */
+#define CONFIG_ENV_SECT_SIZE		0x40000		/* 256KB */
+#define CONFIG_SYS_FSL_QSPI_BASE        0x40000000
+#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET
+#else
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
+#define CONFIG_ENV_SIZE			0x2000
+#else
+#define CONFIG_ENV_SIZE			0x2000		/* 8KB */
+#define CONFIG_ENV_OFFSET		0x300000	/* 3MB */
+#define CONFIG_ENV_SECT_SIZE		0x40000		/* 256KB */
+#endif
+#endif
+
+#define AQR105_IRQ_MASK			0x80000000
+/* FMan */
+#ifndef SPL_NO_FMAN
+
+#ifdef CONFIG_NET
+#define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define RGMII_PHY1_ADDR			0x1
+#define RGMII_PHY2_ADDR			0x2
+
+#define SGMII_PHY1_ADDR			0x3
+#define SGMII_PHY2_ADDR			0x4
+
+#define FM1_10GEC1_PHY_ADDR		0x0
+
+#define FDT_SEQ_MACADDR_FROM_ENV
+
+#define CONFIG_ETHPRIME			"FM1@DTSEC3"
+#endif
+
+#endif
+
+/* QSPI device */
+#ifndef SPL_NO_QSPI
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE		(1 << 26)
+#define FSL_QSPI_FLASH_NUM		2
+#endif
+#endif
+
+#ifndef SPL_NO_MISC
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;;"
+#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;"
+#else
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;;"
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; "	\
+			   "env exists secureboot && esbc_halt;"
+#endif
+#endif
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1046ARDB_H__ */
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
new file mode 100644
index 0000000..6f04dba
--- /dev/null
+++ b/include/configs/ls1088a_common.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef __LS1088_COMMON_H
+#define __LS1088_COMMON_H
+
+/* SPL build */
+#ifdef CONFIG_SPL_BUILD
+#define SPL_NO_BOARDINFO
+#define SPL_NO_QIXIS
+#define SPL_NO_PCI
+#define SPL_NO_ENV
+#define SPL_NO_RTC
+#define SPL_NO_USB
+#define SPL_NO_SATA
+#define SPL_NO_QSPI
+#define SPL_NO_IFC
+#undef CONFIG_DISPLAY_CPUINFO
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+#include <asm/arch/soc.h>
+
+#define LS1088ARDB_PB_BOARD            0x4A
+/* Link Definitions */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
+
+/* Link Definitions */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_FSL_QSPI_BASE	0x20000000
+#else
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_FSL_QSPI_BASE	0x20000000
+#define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FSL_QSPI_BASE + \
+						CONFIG_ENV_OFFSET)
+#endif
+#endif
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	1
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR		secondary_boot_func
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* I2C */
+#ifndef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C
+#endif
+
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS)
+/* IFC */
+#define CONFIG_FSL_IFC
+#endif
+
+/*
+ * During booting, IFC is mapped at the region of 0x30000000.
+ * But this region is limited to 256MB. To accommodate NOR, promjet
+ * and FPGA. This region is divided as below:
+ * 0x30000000 - 0x37ffffff : 128MB : NOR flash
+ * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
+ * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
+ *
+ * To accommodate bigger NOR flash and other devices, we will map IFC
+ * chip selects to as below:
+ * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
+ * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
+ * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
+ * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
+ * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
+ *
+ * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
+ * CONFIG_SYS_FLASH_BASE has the final address (core view)
+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
+ */
+
+#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
+#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
+
+#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
+#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
+
+#ifndef __ASSEMBLY__
+unsigned long long get_qixis_addr(void);
+#endif
+
+#define QIXIS_BASE				get_qixis_addr()
+#define QIXIS_BASE_PHYS				0x20000000
+#define QIXIS_BASE_PHYS_EARLY			0xC000000
+
+
+#define CONFIG_SYS_NAND_BASE			0x530000000ULL
+#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
+
+
+/* MC firmware */
+/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
+#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
+#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
+
+/* Define phy_reset function to boot the MC based on mcinitcmd.
+ * This happens late enough to properly fixup u-boot env MAC addresses.
+ */
+#define CONFIG_RESET_PHY_R
+
+/*
+ * Carve out a DDR region which will not be used by u-boot/Linux
+ *
+ * It will be used by MC and Debug Server. The MC region must be
+ * 512MB aligned, so the min size to hide is 512MB.
+ */
+
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(128UL * 1024 * 1024)
+#endif
+/* Command line configuration */
+#define CONFIG_CMD_CACHE
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* SATA */
+#ifdef CONFIG_SCSI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SATA1		AHCI_BASE_ADDR1
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+/* Physical Memory Map */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+/* #define CONFIG_DISPLAY_CPUINFO */
+
+#ifndef SPL_NO_ENV
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x581000000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"console=ttyAMA0,38400n8\0"		\
+	"mcinitcmd=fsl_mc start mc 0x580a00000"	\
+	" 0x580e00000 \0"
+
+#ifndef CONFIG_TFABOOT
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_BOOTCOMMAND	"sf probe 0:0;" \
+				"sf read 0x80001000 0xd00000 0x100000;"\
+				" fsl_mc lazyapply dpl 0x80001000 &&" \
+				" sf read $kernel_load $kernel_start" \
+				" $kernel_size && bootm $kernel_load"
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_BOOTCOMMAND	"mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
+				" fsl_mc lazyapply dpl 0x80001000 &&" \
+				" mmc read $kernel_load $kernel_start" \
+				" $kernel_size && bootm $kernel_load"
+#else /* NOR BOOT*/
+#define CONFIG_BOOTCOMMAND	"fsl_mc lazyapply dpl 0x580d00000 &&" \
+				" cp.b $kernel_start $kernel_load" \
+				" $kernel_size && bootm $kernel_load"
+#endif
+#endif /* CONFIG_TFABOOT  */
+#endif
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_BSS_START_ADDR      0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x00100000
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE            0x16000
+#define CONFIG_SPL_STACK               (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
+#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
+
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START    0x80200000
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
+/*
+ * HDR would be appended at end of image and copied to DDR along
+ * with U-Boot image. Here u-boot max. size is 512K. So if binary
+ * size increases then increase this size in case of secure boot as
+ * it uses raw u-boot image instead of fit image.
+ */
+#define CONFIG_SYS_MONITOR_LEN         (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
+#else
+#define CONFIG_SYS_MONITOR_LEN         0x100000
+#endif /* ifdef CONFIG_SECURE_BOOT */
+
+#endif
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#endif /* __LS1088_COMMON_H */
diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
new file mode 100644
index 0000000..85e2061
--- /dev/null
+++ b/include/configs/ls1088aqds.h
@@ -0,0 +1,572 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef __LS1088A_QDS_H
+#define __LS1088A_QDS_H
+
+#include "ls1088a_common.h"
+
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_ENV_OFFSET		0x500000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#else
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#else
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x20000
+#endif
+#endif
+
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_QIXIS_I2C_ACCESS
+#define SYS_NO_FLASH
+
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+#else
+#define CONFIG_QIXIS_I2C_ACCESS
+#ifndef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C_EARLY_INIT
+#endif
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
+#endif
+
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
+#define SPD_EEPROM_ADDRESS		0x51
+#define CONFIG_SYS_SPD_BUS_NUM		0
+
+
+/*
+ * IFC Definitions
+ */
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
+
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TAVDS(0x6) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1a) | \
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x8) | \
+				FTIM2_NOR_TCH(0x8) | \
+				FTIM2_NOR_TWPH(0xe) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#ifndef SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
+					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#endif
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#define CONFIG_FSL_QIXIS
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_QMAP_MASK			0xe0
+#define QIXIS_QMAP_SHIFT		5
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x0e
+#define QIXIS_LBMAP_ALTBANK		0x2e
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_LBMAP_EMMC		0x00
+#define QIXIS_LBMAP_IFC			0x00
+#define QIXIS_LBMAP_SD_QSPI		0x0e
+#define QIXIS_LBMAP_QSPI		0x0e
+#define QIXIS_RCW_SRC_IFC		0x25
+#define QIXIS_RCW_SRC_SD		0x40
+#define QIXIS_RCW_SRC_EMMC		0x41
+#define QIXIS_RCW_SRC_QSPI		0x62
+#define QIXIS_RST_CTL_RESET		0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define	QIXIS_RST_FORCE_MEM		0x01
+#define QIXIS_STAT_PRES1		0xb
+#define QIXIS_SDID_MASK			0x07
+#define QIXIS_ESDHC_NO_ADAPTER		0x7
+
+#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+					| CSPR_PORT_SIZE_8 \
+					| CSPR_MSEL_GPCM \
+					| CSPR_V)
+#define SYS_FPGA_CSPR_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+					| CSPR_PORT_SIZE_8 \
+					| CSPR_MSEL_GPCM \
+					| CSPR_V)
+
+#define SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(0)
+#else
+#define CONFIG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(12)
+#endif
+/* QIXIS Timing parameters*/
+#define SYS_FPGA_CS_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define SYS_FPGA_CS_FTIM1	(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define SYS_FPGA_CS_FTIM2	(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0x3E))
+#define SYS_FPGA_CS_FTIM3	0x0
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK3		SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
+#else
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK2		SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS2_FTIM0		SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		SYS_FPGA_CS_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_CSPR3_FINAL		SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK3		SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS3_FTIM0		SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS3_FTIM1		SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS3_FTIM2		SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS3_FTIM3		SYS_FPGA_CS_FTIM3
+#endif
+#endif
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI		0x77
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR		0x18
+#define I2C_RETIMER_ADDR2		0x19
+#define I2C_MUX_CH_DEFAULT		0x8
+#define I2C_MUX_CH5			0xD
+
+#define I2C_MUX_CH_VOL_MONITOR          0xA
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR           0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
+#define I2C_SVDD_MONITOR_ADDR           0x4F
+
+#define CONFIG_VID_FLS_ENV              "ls1088aqds_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed for LS1088AQDS */
+#define VDD_MV_MIN			819
+#define VDD_MV_MAX			1212
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE                  0x0
+#define PMBUS_CMD_READ_VOUT             0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
+#define PMBUS_CMD_VOUT_COMMAND          0x21
+
+#define PWM_CHANNEL0                    0x0
+
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+/* QSPI device */
+#if defined(CONFIG_TFABOOT) || \
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define FSL_QSPI_FLASH_SIZE		(1 << 26)
+#define FSL_QSPI_FLASH_NUM		2
+
+#endif
+
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#if !defined(CONFIG_TFABOOT) && \
+	!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#endif
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+#define CONFIG_FSL_MEMAC
+
+/*  MMC  */
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
+	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
+
+/* Initial environment variables */
+#ifdef CONFIG_SECURE_BOOT
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x90100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x1000000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;"	\
+	"sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;"	\
+	"sf read 0xa0e00000 0xe00000 0x100000;"	\
+	"sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;"	\
+	"fsl_mc start mc 0xa0a00000 0xa0e00000\0"			\
+	"mcmemsize=0x70000000 \0"
+#else /* if !(CONFIG_SECURE_BOOT) */
+#ifdef CONFIG_TFABOOT
+#define QSPI_MC_INIT_CMD				\
+	"sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"	\
+	"sf read 0x80100000 0xE00000 0x100000;" \
+	"fsl_mc start mc 0x80000000 0x80100000\0"
+#define SD_MC_INIT_CMD				\
+	"mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
+	"mmc read 0x80100000 0x7000 0x800;" \
+	"fsl_mc start mc 0x80000000 0x80100000\0"
+#define IFC_MC_INIT_CMD				\
+	"fsl_mc start mc 0x580A00000 0x580E00000\0"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x90100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"kernel_addr_sd=0x800\0"                \
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x1000000\0"		\
+	"kernel_start_sd=0x8000\0"              \
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernel_size_sd=0x14000\0"               \
+	"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"	\
+	"sf read 0x80100000 0xE00000 0x100000;" \
+	"fsl_mc start mc 0x80000000 0x80100000\0"	\
+	"mcmemsize=0x70000000 \0"
+#define QSPI_NOR_BOOTCOMMAND	"sf probe 0:0;" \
+				"sf read 0x80001000 0xd00000 0x100000;"\
+				" fsl_mc lazyapply dpl 0x80001000 &&" \
+				" sf read $kernel_load $kernel_start" \
+				" $kernel_size && bootm $kernel_load"
+#define SD_BOOTCOMMAND		"mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
+				" fsl_mc lazyapply dpl 0x80001000 &&" \
+				" mmc read $kernel_load $kernel_start_sd" \
+				" $kernel_size_sd && bootm $kernel_load"
+#define IFC_NOR_BOOTCOMMAND	"fsl_mc lazyapply dpl 0x580d00000 &&" \
+				" cp.b $kernel_start $kernel_load" \
+				" $kernel_size && bootm $kernel_load"
+#else
+#if defined(CONFIG_QSPI_BOOT)
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x90100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x1000000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"	\
+	"sf read 0x80100000 0xE00000 0x100000;" \
+	"fsl_mc start mc 0x80000000 0x80100000\0"	\
+	"mcmemsize=0x70000000 \0"
+#elif defined(CONFIG_SD_BOOT)
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS               \
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
+	"loadaddr=0x90100000\0"                 \
+	"kernel_addr=0x800\0"                \
+	"ramdisk_addr=0x800000\0"               \
+	"ramdisk_size=0x2000000\0"              \
+	"fdt_high=0xa0000000\0"                 \
+	"initrd_high=0xffffffffffffffff\0"      \
+	"kernel_start=0x8000\0"              \
+	"kernel_load=0xa0000000\0"              \
+	"kernel_size=0x14000\0"               \
+	"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
+	"mmc read 0x80100000 0x7000 0x800;" \
+	"fsl_mc start mc 0x80000000 0x80100000\0"       \
+	"mcmemsize=0x70000000 \0"
+#else	/* NOR BOOT */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x90100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x1000000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"	\
+	"mcmemsize=0x70000000 \0"
+#endif
+#endif /* CONFIG_TFABOOT */
+#endif /* CONFIG_SECURE_BOOT */
+
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_FSL_MEMAC
+#define	CONFIG_PHYLIB
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define RGMII_PHY1_ADDR		0x1
+#define RGMII_PHY2_ADDR		0x2
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
+
+#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(MMC, mmc, 0) \
+	func(SCSI, scsi, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1088A_QDS_H */
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h
new file mode 100644
index 0000000..b71f704
--- /dev/null
+++ b/include/configs/ls1088ardb.h
@@ -0,0 +1,574 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef __LS1088A_RDB_H
+#define __LS1088A_RDB_H
+
+#include "ls1088a_common.h"
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET		0x500000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#else
+#if defined(CONFIG_QSPI_BOOT)
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x20000
+#endif
+#endif /* CONFIG_TFABOOT */
+
+#if defined(CONFIG_TFABOOT) || \
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_QIXIS_I2C_ACCESS
+#endif
+#define SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		100000000
+#define COUNTER_FREQUENCY_REAL		25000000	/* 25MHz */
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
+
+#define CONFIG_DDR_SPD
+#ifdef CONFIG_EMU
+#define CONFIG_SYS_FSL_DDR_EMU
+#define CONFIG_SYS_MXC_I2C1_SPEED	40000000
+#define CONFIG_SYS_MXC_I2C2_SPEED	40000000
+#else
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+#define SPD_EEPROM_ADDRESS	0x51
+#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64 * 1024 * 1024)
+
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(6)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+				FTIM0_NOR_TEADC(0x1) | \
+				FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+				FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
+				FTIM2_NOR_TCH(0x0) | \
+				FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#ifndef SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+#endif
+
+#ifndef SPL_NO_IFC
+#define CONFIG_NAND_FSL_IFC
+#endif
+
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#ifndef SPL_NO_QIXIS
+#define CONFIG_FSL_QIXIS
+#endif
+
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_BRDCFG4_OFFSET            0x54
+#define QIXIS_LBMAP_SWITCH		2
+#define QIXIS_QMAP_MASK			0xe0
+#define QIXIS_QMAP_SHIFT		5
+#define QIXIS_LBMAP_MASK		0x1f
+#define QIXIS_LBMAP_SHIFT		5
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x20
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_LBMAP_EMMC		0x00
+#define QIXIS_LBMAP_SD_QSPI		0x00
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_SD		0x40
+#define QIXIS_RCW_SRC_EMMC		0x41
+#define QIXIS_RCW_SRC_QSPI		0x62
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define	QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+					| CSPR_PORT_SIZE_8 \
+					| CSPR_MSEL_GPCM \
+					| CSPR_V)
+#define SYS_FPGA_CSPR_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+					| CSPR_PORT_SIZE_8 \
+					| CSPR_MSEL_GPCM \
+					| CSPR_V)
+
+#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64*1024)
+#define CONFIG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(0)
+/* QIXIS Timing parameters*/
+#define SYS_FPGA_CS_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define SYS_FPGA_CS_FTIM1	(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define SYS_FPGA_CS_FTIM2	(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0x3E))
+#define SYS_FPGA_CS_FTIM3	0x0
+
+#if defined(CONFIG_TFABOOT) || \
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_FPGA_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_FPGA_CSPR
+#define CONFIG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_FPGA_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_FPGA_CSOR
+#define CONFIG_SYS_CS2_FTIM0		SYS_FPGA_CS_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		SYS_FPGA_CS_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		SYS_FPGA_CS_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		SYS_FPGA_CS_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#endif
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+#define I2C_MUX_CH_VOL_MONITOR          0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR           0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
+#define I2C_SVDD_MONITOR_ADDR		0x4F
+
+#define CONFIG_VID_FLS_ENV              "ls1088ardb_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed for LS1088ARDB */
+#define VDD_MV_MIN			819
+#define VDD_MV_MAX			1212
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE                  0x0
+#define PMBUS_CMD_READ_VOUT             0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
+#define PMBUS_CMD_VOUT_COMMAND          0x21
+
+#define PWM_CHANNEL0                    0x0
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI		0x77
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR		0x18
+#define I2C_MUX_CH_DEFAULT		0x8
+#define I2C_MUX_CH5			0xD
+
+#ifndef SPL_NO_RTC
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+#ifndef SPL_NO_QSPI
+/* QSPI device */
+#if defined(CONFIG_TFABOOT) || \
+	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define FSL_QSPI_FLASH_SIZE		(1 << 26)
+#define FSL_QSPI_FLASH_NUM		2
+#endif
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#endif
+
+#define CONFIG_FSL_MEMAC
+
+#ifndef SPL_NO_ENV
+/* Initial environment variables */
+#ifdef CONFIG_TFABOOT
+#define QSPI_MC_INIT_CMD				\
+	"sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"	\
+	"sf read 0x80100000 0xE00000 0x100000;"				\
+	"env exists secureboot && "			\
+	"sf read 0x80700000 0x700000 0x40000 && "	\
+	"sf read 0x80740000 0x740000 0x40000 && "	\
+	"esbc_validate 0x80700000 && "			\
+	"esbc_validate 0x80740000 ;"			\
+	"fsl_mc start mc 0x80000000 0x80100000\0"
+#define SD_MC_INIT_CMD				\
+	"mmcinfo;mmc read 0x80000000 0x5000 0x800;"		\
+	"mmc read 0x80100000 0x7000 0x800;"				\
+	"env exists secureboot && "			\
+	"mmc read 0x80700000 0x3800 0x10 && "		\
+	"mmc read 0x80740000 0x3A00 0x10 && "		\
+	"esbc_validate 0x80700000 && "			\
+	"esbc_validate 0x80740000 ;"			\
+	"fsl_mc start mc 0x80000000 0x80100000\0"
+#else
+#if defined(CONFIG_QSPI_BOOT)
+#define MC_INIT_CMD				\
+	"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"	\
+	"sf read 0x80100000 0xE00000 0x100000;"				\
+	"env exists secureboot && "			\
+	"sf read 0x80700000 0x700000 0x40000 && "	\
+	"sf read 0x80740000 0x740000 0x40000 && "	\
+	"esbc_validate 0x80700000 && "			\
+	"esbc_validate 0x80740000 ;"			\
+	"fsl_mc start mc 0x80000000 0x80100000\0"	\
+	"mcmemsize=0x70000000\0"
+#elif defined(CONFIG_SD_BOOT)
+#define MC_INIT_CMD				\
+	"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"		\
+	"mmc read 0x80100000 0x7000 0x800;"				\
+	"env exists secureboot && "			\
+	"mmc read 0x80700000 0x3800 0x10 && "		\
+	"mmc read 0x80740000 0x3A00 0x10 && "		\
+	"esbc_validate 0x80700000 && "			\
+	"esbc_validate 0x80740000 ;"			\
+	"fsl_mc start mc 0x80000000 0x80100000\0"	\
+	"mcmemsize=0x70000000\0"
+#endif
+#endif /* CONFIG_TFABOOT */
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#ifdef CONFIG_TFABOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"BOARD=ls1088ardb\0"			\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x64f00000\0"			\
+	"kernel_addr=0x1000000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernelhdr_addr_sd=0x4000\0"		\
+	"kernel_start=0x580100000\0"		\
+	"kernelheader_start=0x580800000\0"	\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr=0x800000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernel_size_sd=0x14000\0"		\
+	"kernelhdr_size_sd=0x10\0"		\
+	QSPI_MC_INIT_CMD			\
+	"mcmemsize=0x70000000\0"		\
+	BOOTENV					\
+	"boot_scripts=ls1088ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1088ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+		"part list ${devtype} ${devnum} devplist; "	\
+		"env exists devplist || setenv devplist 1; "	\
+		"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "			\
+				"${devnum}:${distro_bootpart} "	\
+				"bootfstype; then "		\
+				"run scan_dev_for_boot; "	\
+			"fi; "					\
+		"done\0"					\
+	"boot_a_script="					\
+		"load ${devtype} ${devnum}:${distro_bootpart} " \
+		"${scriptaddr} ${prefix}${script}; "		\
+	"env exists secureboot && load ${devtype} "		\
+		"${devnum}:${distro_bootpart} "			\
+		"${scripthdraddr} ${prefix}${boot_script_hdr}; "\
+		"env exists secureboot "			\
+		"&& esbc_validate ${scripthdraddr};"		\
+		"source ${scriptaddr}\0"			\
+	"installer=load mmc 0:2 $load_addr "			\
+		"/flex_installer_arm64.itb; "			\
+		"env exists mcinitcmd && run mcinitcmd && "	\
+		"mmc read 0x80001000 0x6800 0x800;"		\
+		"fsl_mc lazyapply dpl 0x80001000;"			\
+		"bootm $load_addr#ls1088ardb\0"			\
+	"qspi_bootcmd=echo Trying load from qspi..;"		\
+		"sf probe && sf read $load_addr "		\
+		"$kernel_addr $kernel_size ; env exists secureboot "	\
+		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		"bootm $load_addr#$BOARD\0"			\
+		"sd_bootcmd=echo Trying load from sd card..;"		\
+		"mmcinfo; mmc read $load_addr "			\
+		"$kernel_addr_sd $kernel_size_sd ;"		\
+		"env exists secureboot && mmc read $kernelheader_addr_r "\
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$BOARD\0"
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"BOARD=ls1088ardb\0"			\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x64f00000\0"			\
+	"kernel_addr=0x1000000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernelhdr_addr_sd=0x4000\0"		\
+	"kernel_start=0x580100000\0"		\
+	"kernelheader_start=0x580800000\0"	\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr=0x800000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernel_size_sd=0x14000\0"		\
+	"kernelhdr_size_sd=0x10\0"		\
+	MC_INIT_CMD				\
+	BOOTENV					\
+	"boot_scripts=ls1088ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls1088ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+		"part list ${devtype} ${devnum} devplist; "	\
+		"env exists devplist || setenv devplist 1; "	\
+		"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "			\
+				"${devnum}:${distro_bootpart} "	\
+				"bootfstype; then "		\
+				"run scan_dev_for_boot; "	\
+			"fi; "					\
+		"done\0"					\
+	"boot_a_script="					\
+		"load ${devtype} ${devnum}:${distro_bootpart} " \
+		"${scriptaddr} ${prefix}${script}; "		\
+	"env exists secureboot && load ${devtype} "		\
+		"${devnum}:${distro_bootpart} "			\
+		"${scripthdraddr} ${prefix}${boot_script_hdr} " \
+		"&& esbc_validate ${scripthdraddr};"		\
+		"source ${scriptaddr}\0"			\
+	"installer=load mmc 0:2 $load_addr "			\
+		"/flex_installer_arm64.itb; "			\
+		"env exists mcinitcmd && run mcinitcmd && "	\
+		"mmc read 0x80001000 0x6800 0x800;"		\
+		"fsl_mc lazyapply dpl 0x80001000;"			\
+		"bootm $load_addr#ls1088ardb\0"			\
+	"qspi_bootcmd=echo Trying load from qspi..;"		\
+		"sf probe && sf read $load_addr "		\
+		"$kernel_addr $kernel_size ; env exists secureboot "	\
+		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		"bootm $load_addr#$BOARD\0"			\
+		"sd_bootcmd=echo Trying load from sd card..;"		\
+		"mmcinfo; mmc read $load_addr "			\
+		"$kernel_addr_sd $kernel_size_sd ;"		\
+		"env exists secureboot && mmc read $kernelheader_addr_r "\
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$BOARD\0"
+#endif /* CONFIG_TFABOOT */
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND					\
+		"sf read 0x80001000 0xd00000 0x100000;"		\
+		"env exists mcinitcmd && env exists secureboot "	\
+		" && sf read 0x80780000 0x780000 0x100000 "	\
+		"&& esbc_validate 0x80780000;env exists mcinitcmd "	\
+		"&& fsl_mc lazyapply dpl 0x80001000;"		\
+		"run distro_bootcmd;run qspi_bootcmd;"		\
+		"env exists secureboot && esbc_halt;"
+#define SD_BOOTCOMMAND						\
+		"env exists mcinitcmd && mmcinfo; "		\
+		"mmc read 0x80001000 0x6800 0x800; "		\
+		"env exists mcinitcmd && env exists secureboot "	\
+		" && mmc read 0x80780000 0x3C00 0x10 "		\
+		"&& esbc_validate 0x80780000;env exists mcinitcmd "	\
+		"&& fsl_mc lazyapply dpl 0x80001000;"		\
+		"run distro_bootcmd;run sd_bootcmd;"		\
+		"env exists secureboot && esbc_halt;"
+#else
+#if defined(CONFIG_QSPI_BOOT)
+/* Try to boot an on-QSPI kernel first, then do normal distro boot */
+#define CONFIG_BOOTCOMMAND                                      \
+		"sf read 0x80001000 0xd00000 0x100000;"		\
+		"env exists mcinitcmd && env exists secureboot "	\
+		" && sf read 0x80780000 0x780000 0x100000 "	\
+		"&& esbc_validate 0x80780000;env exists mcinitcmd "	\
+		"&& fsl_mc lazyapply dpl 0x80001000;"		\
+		"run distro_bootcmd;run qspi_bootcmd;"		\
+		"env exists secureboot && esbc_halt;"
+
+/* Try to boot an on-SD kernel first, then do normal distro boot */
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_BOOTCOMMAND                                      \
+		"env exists mcinitcmd && mmcinfo; "		\
+		"mmc read 0x80001000 0x6800 0x800; "		\
+		"env exists mcinitcmd && env exists secureboot "	\
+		" && mmc read 0x80780000 0x3C00 0x10 "		\
+		"&& esbc_validate 0x80780000;env exists mcinitcmd "	\
+		"&& fsl_mc lazyapply dpl 0x80001000;"		\
+		"run distro_bootcmd;run sd_bootcmd;"		\
+		"env exists secureboot && esbc_halt;"
+#endif
+#endif /* CONFIG_TFABOOT */
+
+/* MAC/PHY configuration */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_PHYLIB
+
+#define CONFIG_PHY_VITESSE
+#define AQ_PHY_ADDR1			0x00
+#define AQR105_IRQ_MASK			0x00000004
+
+#define QSGMII1_PORT1_PHY_ADDR		0x0c
+#define QSGMII1_PORT2_PHY_ADDR		0x0d
+#define QSGMII1_PORT3_PHY_ADDR		0x0e
+#define QSGMII1_PORT4_PHY_ADDR		0x0f
+#define QSGMII2_PORT1_PHY_ADDR		0x1c
+#define QSGMII2_PORT2_PHY_ADDR		0x1d
+#define QSGMII2_PORT3_PHY_ADDR		0x1e
+#define QSGMII2_PORT4_PHY_ADDR		0x1f
+
+#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
+#define CONFIG_PHY_GIGE
+#endif
+#endif
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+#ifndef SPL_NO_ENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(SCSI, scsi, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1088A_RDB_H */
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
new file mode 100644
index 0000000..6be581a
--- /dev/null
+++ b/include/configs/ls2080a_common.h
@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2014 Freescale Semiconductor
+ */
+
+#ifndef __LS2_COMMON_H
+#define __LS2_COMMON_H
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_GICV3
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+
+/* Link Definitions */
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#endif
+
+/* We need architecture specific misc initializations */
+
+/* Link Definitions */
+#ifndef CONFIG_TFABOOT
+#ifndef CONFIG_QSPI_BOOT
+#else
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#endif
+#endif
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_DDR_RAW_TIMING
+#endif
+
+#define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
+
+/*
+ * SMP Definitinos
+ */
+#define CPU_RELEASE_ADDR		secondary_boot_func
+
+#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+#define CONFIG_SYS_DP_DDR_BASE		0x6000000000ULL
+/*
+ * DDR controller use 0 as the base address for binding.
+ * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+ */
+#define CONFIG_SYS_DP_DDR_BASE_PHY	0
+#define CONFIG_DP_DDR_CTRL		2
+#define CONFIG_DP_DDR_NUM_CTRLS		1
+#endif
+
+/* Generic Timer Definitions */
+/*
+ * This is not an accurate number. It is used in start.S. The frequency
+ * will be udpated later when get_bus_freq(0) is available.
+ */
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* I2C */
+#ifndef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C
+#endif
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* IFC */
+#define CONFIG_FSL_IFC
+
+/*
+ * During booting, IFC is mapped at the region of 0x30000000.
+ * But this region is limited to 256MB. To accommodate NOR, promjet
+ * and FPGA. This region is divided as below:
+ * 0x30000000 - 0x37ffffff : 128MB : NOR flash
+ * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
+ * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
+ *
+ * To accommodate bigger NOR flash and other devices, we will map IFC
+ * chip selects to as below:
+ * 0x5_1000_0000..0x5_1fff_ffff	Memory Hole
+ * 0x5_2000_0000..0x5_3fff_ffff	IFC CSx (FPGA, NAND and others 512MB)
+ * 0x5_4000_0000..0x5_7fff_ffff	ASIC or others 1GB
+ * 0x5_8000_0000..0x5_bfff_ffff	IFC CS0 1GB (NOR/Promjet)
+ * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
+ *
+ * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
+ * CONFIG_SYS_FLASH_BASE has the final address (core view)
+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
+ */
+
+#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
+#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
+
+#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
+#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
+
+#ifndef __ASSEMBLY__
+unsigned long long get_qixis_addr(void);
+#endif
+#define QIXIS_BASE				get_qixis_addr()
+#define QIXIS_BASE_PHYS				0x20000000
+#define QIXIS_BASE_PHYS_EARLY			0xC000000
+#define QIXIS_STAT_PRES1			0xb
+#define QIXIS_SDID_MASK				0x07
+#define QIXIS_ESDHC_NO_ADAPTER			0x7
+
+#define CONFIG_SYS_NAND_BASE			0x530000000ULL
+#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
+
+/* MC firmware */
+/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
+/* For LS2085A */
+#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
+#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
+
+/* Define phy_reset function to boot the MC based on mcinitcmd.
+ * This happens late enough to properly fixup u-boot env MAC addresses.
+ */
+#define CONFIG_RESET_PHY_R
+
+/*
+ * Carve out a DDR region which will not be used by u-boot/Linux
+ *
+ * It will be used by MC and Debug Server. The MC region must be
+ * 512MB aligned, so the min size to hide is 512MB.
+ */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(128UL * 1024 * 1024)
+#endif
+
+/* Command line configuration */
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* Physical Memory Map */
+/* fixme: these need to be checked against the board */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x581000000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"console=ttyAMA0,38400n8\0"		\
+	"mcinitcmd=fsl_mc start mc 0x580a00000"	\
+	" 0x580e00000 \0"
+
+#ifndef CONFIG_TFABOOT
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_BOOTCOMMAND	"mmc read 0x80200000 0x6800 0x800;"\
+				" fsl_mc apply dpl 0x80200000 &&" \
+				" mmc read $kernel_load $kernel_start" \
+				" $kernel_size && bootm $kernel_load"
+#else
+#define CONFIG_BOOTCOMMAND	"fsl_mc apply dpl 0x580d00000 &&" \
+				" cp.b $kernel_start $kernel_load" \
+				" $kernel_size && bootm $kernel_load"
+#endif
+#endif
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
+#define CONFIG_SPL_MAX_SIZE		0x16000
+#define CONFIG_SPL_STACK		(CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x80400000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#endif
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SYS_MONITOR_LEN		(1024 * 1024)
+
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#include <asm/arch/soc.h>
+
+#endif /* __LS2_COMMON_H */
diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h
new file mode 100644
index 0000000..d5cb3e4
--- /dev/null
+++ b/include/configs/ls2080a_emu.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor
+ */
+
+#ifndef __LS2_EMU_H
+#define __LS2_EMU_H
+
+#include "ls2080a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133333333
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR_EMU		/* Support emulator */
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM	1	/* SPD on I2C bus 1 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR		1
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/*
+ * NOR Flash Timing Params
+ */
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+				FTIM0_NOR_TEADC(0x1) | \
+				FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+				FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
+				FTIM2_NOR_TCH(0x0) | \
+				FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580C00000ULL
+
+/*
+ * This trick allows users to load MC images into DDR directly without
+ * copying from NOR flash. It dramatically improves speed.
+ */
+#define CONFIG_SYS_LS_MC_FW_IN_DDR
+#define CONFIG_SYS_LS_MC_DPL_IN_DDR
+#define CONFIG_SYS_LS_MC_DPC_IN_DDR
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_SIZE			0x1000
+
+#endif /* __LS2_EMU_H */
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
new file mode 100644
index 0000000..a526658
--- /dev/null
+++ b/include/configs/ls2080a_simu.h
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ */
+
+#ifndef __LS2_SIMU_H
+#define __LS2_SIMU_H
+
+#include "ls2080a_common.h"
+
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133333333
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR		1
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif
+
+/* SMSC 91C111 ethernet configuration */
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE	(0x2210000)
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
+/*
+ * NOR Flash Timing Params
+ */
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+				FTIM0_NOR_TEADC(0x1) | \
+				FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+				FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
+				FTIM2_NOR_TCH(0x0) | \
+				FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580C00000ULL
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
+
+#define CONFIG_SYS_LS_MC_DPC_IN_NOR
+#define CONFIG_SYS_LS_MC_DPC_ADDR	0x5806F8000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_SIZE			0x1000
+
+#endif /* __LS2_SIMU_H */
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
new file mode 100644
index 0000000..e2a8975
--- /dev/null
+++ b/include/configs/ls2080aqds.h
@@ -0,0 +1,500 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017, 2019 NXP
+ * Copyright 2015 Freescale Semiconductor
+ */
+
+#ifndef __LS2_QDS_H
+#define __LS2_QDS_H
+
+#include "ls2080a_common.h"
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_QIXIS_I2C_ACCESS
+#ifndef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C_EARLY_INIT
+#endif
+#define CONFIG_SYS_I2C_IFDR_DIV		0x7e
+#endif
+
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
+#define SPD_EEPROM_ADDRESS4	0x54
+#define SPD_EEPROM_ADDRESS5	0x55
+#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR		2
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif
+
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
+#define CONFIG_SYS_SATA2			AHCI_BASE_ADDR2
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_ENV_OFFSET		0x500000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
+
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1a) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
+					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_LBMAP_SWITCH		0x06
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_LBMAP_QSPI		0x0f
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RCW_SRC_NAND		0x107
+#define QIXIS_RCW_SRC_SD		0x40
+#define QIXIS_RCW_SRC_QSPI		0x62
+#define	QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_CSPR3_EXT	(0x0)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0x3E))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#if defined(CONFIG_SPL)
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK2_FINAL		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_ENV_OFFSET		(896 * 1024)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 * 1024)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET		0x300000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x20000
+#endif
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_TFABOOT)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#endif
+#endif
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/*
+ * I2C
+ */
+#define I2C_MUX_PCA_ADDR		0x77
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+
+/* SPI */
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SPI_FLASH_SPANSION
+#define FSL_QSPI_FLASH_SIZE		(1 << 26) /* 64MB */
+#define FSL_QSPI_FLASH_NUM		4
+#endif
+/*
+ * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
+ * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
+ * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
+ */
+#define FSL_QIXIS_BRDCFG9_QSPI		0x1
+
+#endif
+
+/*
+ * MMC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
+	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
+#endif
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_FSL_MEMAC
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* Initial environment variables */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x581000000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"mcmemsize=0x40000000\0"		\
+	"mcinitcmd=esbc_validate 0x580700000;"  \
+	"esbc_validate 0x580740000;"            \
+	"fsl_mc start mc 0x580a00000"           \
+	" 0x580e00000 \0"
+#else
+#ifdef CONFIG_TFABOOT
+#define SD_MC_INIT_CMD				\
+	"mmcinfo;mmc read 0x80a00000 0x5000 0x1200;"  \
+	"mmc read 0x80e00000 0x7000 0x800;" \
+	"fsl_mc start mc 0x80a00000 0x80e00000\0"
+#define IFC_MC_INIT_CMD				\
+	"fsl_mc start mc 0x580a00000" \
+	" 0x580e00000 \0"
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
+	"loadaddr=0x80100000\0"                 \
+	"loadaddr_sd=0x90100000\0"                 \
+	"kernel_addr=0x581000000\0"		          \
+	"kernel_addr_sd=0x8000\0"                \
+	"ramdisk_addr=0x800000\0"               \
+	"ramdisk_size=0x2000000\0"              \
+	"fdt_high=0xa0000000\0"                 \
+	"initrd_high=0xffffffffffffffff\0"      \
+	"kernel_start=0x581000000\0"            \
+	"kernel_start_sd=0x8000\0"              \
+	"kernel_load=0xa0000000\0"              \
+	"kernel_size=0x2800000\0"               \
+	"kernel_size_sd=0x14000\0"               \
+	"load_addr=0xa0000000\0"		            \
+	"kernelheader_addr=0x580800000\0"	\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernelheader_size=0x40000\0"		\
+	"BOARD=ls2088aqds\0" \
+	"mcmemsize=0x70000000 \0" \
+	IFC_MC_INIT_CMD				\
+	"nor_bootcmd=echo Trying load from nor..;"		\
+		"cp.b $kernel_addr $load_addr "			\
+		"$kernel_size ; env exists secureboot && "	\
+		"cp.b $kernelheader_addr $kernelheader_addr_r "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		"bootm $load_addr#$BOARD\0"	\
+	"sd_bootcmd=echo Trying load from SD ..;" \
+	"mmcinfo; mmc read $load_addr "		\
+	"$kernel_addr_sd $kernel_size_sd && "	\
+	"bootm $load_addr#$BOARD\0"
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
+	"loadaddr=0x90100000\0"                 \
+	"kernel_addr=0x800\0"                \
+	"ramdisk_addr=0x800000\0"               \
+	"ramdisk_size=0x2000000\0"              \
+	"fdt_high=0xa0000000\0"                 \
+	"initrd_high=0xffffffffffffffff\0"      \
+	"kernel_start=0x8000\0"              \
+	"kernel_load=0xa0000000\0"              \
+	"kernel_size=0x14000\0"               \
+	"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
+	"mmc read 0x80100000 0x7000 0x800;" \
+	"fsl_mc start mc 0x80000000 0x80100000\0"       \
+	"mcmemsize=0x70000000 \0"
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0x581000000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"mcmemsize=0x40000000\0"		\
+	"mcinitcmd=fsl_mc start mc 0x580a00000" \
+	" 0x580e00000 \0"
+#endif /* CONFIG_TFABOOT */
+#endif /* CONFIG_SECURE_BOOT */
+
+#ifdef CONFIG_TFABOOT
+#define SD_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
+			"&& esbc_validate $load_addr; "			\
+			"env exists mcinitcmd && run mcinitcmd "	\
+			"&& mmc read 0x80d00000 0x6800 0x800 "		\
+			"&& fsl_mc lazyapply dpl 0x80d00000; "		\
+			"run sd_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+
+#define IFC_NOR_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& esbc_validate 0x580780000; env exists mcinitcmd "\
+			"&& fsl_mc lazyapply dpl 0x580d00000;"		\
+			"run nor_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+#endif
+
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#define CONFIG_FSL_MEMAC
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
+#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
+#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
+#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
+#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
+#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
+#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
+#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
+#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
+#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
+#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
+#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
+#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
+#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
+#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
+#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
+
+#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
+
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS2_QDS_H */
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
new file mode 100644
index 0000000..2bf8217
--- /dev/null
+++ b/include/configs/ls2080ardb.h
@@ -0,0 +1,604 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017, 2019 NXP
+ * Copyright 2015 Freescale Semiconductor
+ */
+
+#ifndef __LS2_RDB_H
+#define __LS2_RDB_H
+
+#include "ls2080a_common.h"
+
+#ifdef CONFIG_FSL_QSPI
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_QIXIS_I2C_ACCESS
+#endif
+#ifndef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C_EARLY_INIT
+#endif
+#endif
+
+#define I2C_MUX_CH_VOL_MONITOR		0xa
+#define I2C_VOL_MONITOR_ADDR		0x38
+#define CONFIG_VOL_MONITOR_IR36021_READ
+#define CONFIG_VOL_MONITOR_IR36021_SET
+
+#define CONFIG_VID_FLS_ENV		"ls2080ardb_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+/* step the IR regulator in 5mV increments */
+#define IR_VDD_STEP_DOWN		5
+#define IR_VDD_STEP_UP			5
+/* The lowest and highest voltage allowed for LS2080ARDB */
+#define VDD_MV_MIN			819
+#define VDD_MV_MAX			1212
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		133333333
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ/4)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
+#define SPD_EEPROM_ADDRESS4	0x54
+#define SPD_EEPROM_ADDRESS5	0x55
+#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR		2
+#define CONFIG_CHIP_SELECTS_PER_CTRL		4
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
+#endif
+
+/* SATA */
+#define CONFIG_SCSI_AHCI_PLAT
+
+#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
+#define CONFIG_SYS_SATA2			AHCI_BASE_ADDR2
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_MMC_ENV_DEV         0
+
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x500000	/* 5MB */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#endif
+
+#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)
+
+#define CONFIG_SYS_NOR0_CSPR					\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY				\
+	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
+	CSPR_PORT_SIZE_16					| \
+	CSPR_MSEL_NOR						| \
+	CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1a) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
+					 CONFIG_SYS_FLASH_BASE + 0x40000000}
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
+				| CSOR_NAND_PB(128))	/* Pages Per Block 128*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
+					FTIM0_NAND_TWP(0x30)   | \
+					FTIM0_NAND_TWCHT(0x0e) | \
+					FTIM0_NAND_TWH(0x14))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
+					FTIM1_NAND_TWBE(0xab)  | \
+					FTIM1_NAND_TRR(0x1c)   | \
+					FTIM1_NAND_TRP(0x30))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
+					FTIM2_NAND_TREH(0x14) | \
+					FTIM2_NAND_TWHRE(0x3c))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_LBMAP_SWITCH		0x06
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_RCW_SRC_NAND		0x119
+#define	QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_CSPR3_EXT	(0x0)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
+					FTIM2_GPCM_TCH(0xf) | \
+					FTIM2_GPCM_TWP(0x3E))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#ifndef CONFIG_TFABOOT
+#define CONFIG_ENV_OFFSET		(2048 * 1024)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#endif
+#define CONFIG_SPL_PAD_TO		0x80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(1024 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#ifndef CONFIG_TFABOOT
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			0x2000
+#endif
+#endif
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL
+#endif
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_QMAP_MASK			0x07
+#define QIXIS_QMAP_SHIFT		5
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_QSPI		0x62
+#define QIXIS_LBMAP_ALTBANK		0x20
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#endif
+
+/*
+ * I2C
+ */
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#endif
+#define I2C_MUX_PCA_ADDR		0x75
+#define I2C_MUX_PCA_ADDR_PRI		0x75 /* Primary Mux*/
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+
+/* SPI */
+#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
+#ifdef CONFIG_FSL_DSPI
+#define CONFIG_SPI_FLASH_STMICRO
+#endif
+#define FSL_QSPI_FLASH_SIZE		SZ_64M	/* 64MB */
+#define FSL_QSPI_FLASH_NUM		2
+#endif
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#ifdef CONFIG_TARGET_LS2081ARDB
+#define CONFIG_RTC_PCF8563		1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x51
+#else
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_FSL_MEMAC
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/*  MMC  */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(MMC, mmc, 0) \
+	func(SCSI, scsi, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#ifdef CONFIG_TFABOOT
+#define QSPI_MC_INIT_CMD			\
+	"env exists secureboot && "		\
+	"esbc_validate 0x20700000 && "		\
+	"esbc_validate 0x20740000;"		\
+	"fsl_mc start mc 0x20a00000 0x20e00000 \0"
+#define SD_MC_INIT_CMD				\
+	"mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
+	"mmc read 0x80e00000 0x7000 0x800;"	\
+	"env exists secureboot && "		\
+	"mmc read 0x80700000 0x3800 0x10 && "	\
+	"mmc read 0x80740000 0x3A00 0x10 && "	\
+	"esbc_validate 0x80700000 && "		\
+	"esbc_validate 0x80740000 ;"		\
+	"fsl_mc start mc 0x80a00000 0x80e00000\0"
+#define IFC_MC_INIT_CMD				\
+	"env exists secureboot && "	\
+	"esbc_validate 0x580700000 && "		\
+	"esbc_validate 0x580740000; "		\
+	"fsl_mc start mc 0x580a00000 0x580e00000 \0"
+#else
+#ifdef CONFIG_QSPI_BOOT
+#define MC_INIT_CMD				\
+	"mcinitcmd=env exists secureboot && "	\
+	"esbc_validate 0x20700000 && "		\
+	"esbc_validate 0x20740000;"		\
+	"fsl_mc start mc 0x20a00000 0x20e00000 \0"
+#elif defined(CONFIG_SD_BOOT)
+#define MC_INIT_CMD                             \
+	"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
+	"mmc read 0x80100000 0x7000 0x800;"	\
+	"env exists secureboot && "		\
+	"mmc read 0x80700000 0x3800 0x10 && "	\
+	"mmc read 0x80740000 0x3A00 0x10 && "	\
+	"esbc_validate 0x80700000 && "		\
+	"esbc_validate 0x80740000 ;"		\
+	"fsl_mc start mc 0x80000000 0x80100000\0" \
+	"mcmemsize=0x70000000\0"
+#else
+#define MC_INIT_CMD				\
+	"mcinitcmd=env exists secureboot && "	\
+	"esbc_validate 0x580700000 && "		\
+	"esbc_validate 0x580740000; "		\
+	"fsl_mc start mc 0x580a00000 0x580e00000 \0"
+#endif
+#endif
+
+/* Initial environment variables */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#ifdef CONFIG_TFABOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x64f00000\0"			\
+	"kernel_addr=0x581000000\0"		\
+	"kernel_start=0x1000000\0"		\
+	"kernelheader_start=0x800000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernelheader_addr=0x580800000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernel_size_sd=0x14000\0"              \
+	"console=ttyAMA0,38400n8\0"		\
+	"mcmemsize=0x70000000\0"		\
+	"sd_bootcmd=echo Trying load from SD ..;" \
+	"mmcinfo; mmc read $load_addr "		\
+	"$kernel_addr_sd $kernel_size_sd && "	\
+	"bootm $load_addr#$board\0"             \
+	QSPI_MC_INIT_CMD				\
+	BOOTENV					\
+	"boot_scripts=ls2088ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls2088ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+		"part list ${devtype} ${devnum} devplist; "	\
+		"env exists devplist || setenv devplist 1; "	\
+		"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "			\
+				"${devnum}:${distro_bootpart} "	\
+				"bootfstype; then "		\
+				"run scan_dev_for_boot; "	\
+			"fi; "					\
+		"done\0"					\
+	"boot_a_script="					\
+		"load ${devtype} ${devnum}:${distro_bootpart} "	\
+			"${scriptaddr} ${prefix}${script}; "	\
+		"env exists secureboot && load ${devtype} "	\
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
+			"&& esbc_validate ${scripthdraddr};"	\
+		"source ${scriptaddr}\0"			\
+	"qspi_bootcmd=echo Trying load from qspi..;"		\
+		"sf probe && sf read $load_addr "		\
+		"$kernel_start $kernel_size ; env exists secureboot &&"	\
+		"sf read $kernelheader_addr_r $kernelheader_start "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		" bootm $load_addr#$board\0"			\
+	"nor_bootcmd=echo Trying load from nor..;"		\
+		"cp.b $kernel_addr $load_addr "			\
+		"$kernel_size ; env exists secureboot && "	\
+		"cp.b $kernelheader_addr $kernelheader_addr_r "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		"bootm $load_addr#$board\0"
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x64f00000\0"			\
+	"kernel_addr=0x581000000\0"		\
+	"kernel_start=0x1000000\0"		\
+	"kernelheader_start=0x800000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernelheader_addr=0x580800000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernel_size_sd=0x14000\0"              \
+	"console=ttyAMA0,38400n8\0"		\
+	"mcmemsize=0x70000000\0"		\
+	"sd_bootcmd=echo Trying load from SD ..;" \
+	"mmcinfo; mmc read $load_addr "		\
+	"$kernel_addr_sd $kernel_size_sd && "	\
+	"bootm $load_addr#$board\0"             \
+	MC_INIT_CMD				\
+	BOOTENV					\
+	"boot_scripts=ls2088ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_ls2088ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+		"part list ${devtype} ${devnum} devplist; "	\
+		"env exists devplist || setenv devplist 1; "	\
+		"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "			\
+				"${devnum}:${distro_bootpart} "	\
+				"bootfstype; then "		\
+				"run scan_dev_for_boot; "	\
+			"fi; "					\
+		"done\0"					\
+	"boot_a_script="					\
+		"load ${devtype} ${devnum}:${distro_bootpart} "	\
+			"${scriptaddr} ${prefix}${script}; "	\
+		"env exists secureboot && load ${devtype} "	\
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
+			"env exists secureboot "	\
+			"&& esbc_validate ${scripthdraddr};"	\
+		"source ${scriptaddr}\0"			\
+	"qspi_bootcmd=echo Trying load from qspi..;"		\
+		"sf probe && sf read $load_addr "		\
+		"$kernel_start $kernel_size ; env exists secureboot &&"	\
+		"sf read $kernelheader_addr_r $kernelheader_start "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		" bootm $load_addr#$board\0"			\
+	"nor_bootcmd=echo Trying load from nor..;"		\
+		"cp.b $kernel_addr $load_addr "			\
+		"$kernel_size ; env exists secureboot && "	\
+		"cp.b $kernelheader_addr $kernelheader_addr_r "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		"bootm $load_addr#$board\0"
+#endif
+
+#ifdef CONFIG_TFABOOT
+#define QSPI_NOR_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& esbc_validate 0x20780000; "			\
+			"env exists mcinitcmd && "			\
+			"fsl_mc lazyapply dpl 0x20d00000; "		\
+			"run distro_bootcmd;run qspi_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+
+/* Try to boot an on-SD kernel first, then do normal distro boot */
+#define SD_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
+			"&& esbc_validate $load_addr; "			\
+			"env exists mcinitcmd && run mcinitcmd "	\
+			"&& mmc read 0x80d00000 0x6800 0x800 "		\
+			"&& fsl_mc lazyapply dpl 0x80d00000; "		\
+			"run distro_bootcmd;run sd_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+
+/* Try to boot an on-NOR kernel first, then do normal distro boot */
+#define IFC_NOR_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& esbc_validate 0x580780000; env exists mcinitcmd "\
+			"&& fsl_mc lazyapply dpl 0x580d00000;"		\
+			"run distro_bootcmd;run nor_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+#else
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_QSPI_BOOT
+/* Try to boot an on-QSPI kernel first, then do normal distro boot */
+#define CONFIG_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& esbc_validate 0x20780000; "			\
+			"env exists mcinitcmd && "			\
+			"fsl_mc lazyapply dpl 0x20d00000; "		\
+			"run distro_bootcmd;run qspi_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+#elif defined(CONFIG_SD_BOOT)
+/* Try to boot an on-SD kernel first, then do normal distro boot */
+#define CONFIG_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
+			"&& esbc_validate $load_addr; "			\
+			"env exists mcinitcmd && run mcinitcmd "	\
+			"&& mmc read 0x88000000 0x6800 0x800 "		\
+			"&& fsl_mc lazyapply dpl 0x88000000; "		\
+			"run distro_bootcmd;run sd_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+#else
+/* Try to boot an on-NOR kernel first, then do normal distro boot */
+#define CONFIG_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& esbc_validate 0x580780000; env exists mcinitcmd "\
+			"&& fsl_mc lazyapply dpl 0x580d00000;"		\
+			"run distro_bootcmd;run nor_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+#endif
+#endif
+
+/* MAC/PHY configuration */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_PHY_CORTINA
+#define	CONFIG_SYS_CORTINA_FW_IN_NOR
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_CORTINA_FW_ADDR		0x20980000
+#else
+#define CONFIG_CORTINA_FW_ADDR		0x580980000
+#endif
+#define CONFIG_CORTINA_FW_LENGTH	0x40000
+
+#define CORTINA_PHY_ADDR1	0x10
+#define CORTINA_PHY_ADDR2	0x11
+#define CORTINA_PHY_ADDR3	0x12
+#define CORTINA_PHY_ADDR4	0x13
+#define AQ_PHY_ADDR1		0x00
+#define AQ_PHY_ADDR2		0x01
+#define AQ_PHY_ADDR3		0x02
+#define AQ_PHY_ADDR4		0x03
+#define AQR405_IRQ_MASK		0x36
+
+#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
+#endif
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS2_RDB_H */
diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h
new file mode 100644
index 0000000..3ba5548
--- /dev/null
+++ b/include/configs/lsxl.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ */
+
+#ifndef _CONFIG_LSXL_H
+#define _CONFIG_LSXL_H
+
+/*
+ * Version number information
+ */
+#if defined(CONFIG_LSCHLV2)
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
+#define CONFIG_MACH_TYPE 3006
+#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
+#elif defined(CONFIG_LSXHL)
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
+#define CONFIG_MACH_TYPE 2663
+/* CONFIG_SYS_TCLK is 200000000 by default */
+#else
+#error "unknown board"
+#endif
+
+/*
+ * General configuration options
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KW88F6281		/* SOC Name */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+#define CONFIG_KIRKWOOD_GPIO
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* loading initramfs images without uimage header */
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	8
+#define CONFIG_ENV_SECT_SIZE		0x10000 /* 64K */
+#endif
+
+#define CONFIG_ENV_SIZE			0x10000 /* 64k */
+#define CONFIG_ENV_OFFSET		0x70000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_LOADADDR		0x00800000
+
+#if defined(CONFIG_LSXHL)
+#define CONFIG_FDTFILE "kirkwood-lsxhl.dtb"
+#elif defined(CONFIG_LSCHLV2)
+#define CONFIG_FDTFILE "kirkwood-lschlv2.dtb"
+#else
+#error "Unsupported board"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootsource=legacy\0"						\
+	"hdpart=0:1\0"							\
+	"kernel_addr=0x00800000\0"					\
+	"ramdisk_addr=0x01000000\0"					\
+	"fdt_addr=0x00ff0000\0"						\
+	"bootcmd_legacy=sata init "					\
+		"&& load sata ${hdpart} ${kernel_addr} /uImage.buffalo "\
+		"&& load sata ${hdpart} ${ramdisk_addr} /initrd.buffalo "\
+		"&& bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"bootcmd_net=bootp ${kernel_addr} vmlinuz "			\
+		"&& tftpboot ${ramdisk_addr} initrd.img "		\
+		"&& setenv ramdisk_len ${filesize} "			\
+		"&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " "		\
+		"&& bootz ${kernel_addr} "				\
+			"${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0"	\
+	"bootcmd_hdd=sata init "					\
+		"&& load sata ${hdpart} ${kernel_addr} /vmlinuz "	\
+		"&& load sata ${hdpart} ${ramdisk_addr} /initrd.img "	\
+		"&& setenv ramdisk_len ${filesize} "			\
+		"&& load sata ${hdpart} ${fdt_addr} /dtb "		\
+		"&& bootz ${kernel_addr} "				\
+			"${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0"	\
+	"bootcmd_usb=usb start "					\
+		"&& load usb 0:1 ${kernel_addr} /vmlinuz "		\
+		"&& load usb 0:1 ${ramdisk_addr} /initrd.img "		\
+		"&& setenv ramdisk_len ${filesize} "			\
+		"&& load usb 0:1 ${fdt_addr} " CONFIG_FDTFILE " "	\
+		"&& bootz ${kernel_addr} "				\
+			"${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0"	\
+	"bootcmd_rescue=run config_nc_dhcp; run nc\0"			\
+	"eraseenv=sf probe 0 "						\
+		"&& sf erase " __stringify(CONFIG_ENV_OFFSET)		\
+			" +" __stringify(CONFIG_ENV_SIZE) "\0"		\
+	"config_nc_dhcp=setenv autoload_old ${autoload}; "		\
+		"setenv autoload no "					\
+		"&& bootp "						\
+		"&& setenv ncip "					\
+		"&& setenv autoload ${autoload_old}; "			\
+		"setenv autoload_old\0"					\
+	"standard_env=setenv ipaddr; setenv netmask; setenv serverip; "	\
+		"setenv ncip; setenv gatewayip; setenv ethact; "	\
+		"setenv bootfile; setenv dnsip; "			\
+		"setenv bootsource legacy; run ser\0"			\
+	"restore_env=run standard_env; saveenv; reset\0"		\
+	"ser=setenv stdin serial; setenv stdout serial; "		\
+		"setenv stderr serial\0"				\
+	"nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0"	\
+	"stdin=serial\0"						\
+	"stdout=serial\0"						\
+	"stderr=serial\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS		{0, 1} /* enable port 1 only */
+#define CONFIG_PHY_BASE_ADR		7
+#undef CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+#ifdef CONFIG_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_SYS_64BIT_LBA
+#define CONFIG_LBA48
+#endif
+
+#endif /* _CONFIG_LSXL_H */
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
new file mode 100644
index 0000000..110d497
--- /dev/null
+++ b/include/configs/lx2160a_common.h
@@ -0,0 +1,282 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __LX2_COMMON_H
+#define __LX2_COMMON_H
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+#include <asm/arch/soc.h>
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_MEMAC
+
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+/* DDR */
+#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE		0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_DDR_BLOCK2_BASE		0x2080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
+#define CONFIG_SYS_SDRAM_SIZE			0x200000000UL
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1		0x51
+#define SPD_EEPROM_ADDRESS2		0x52
+#define SPD_EEPROM_ADDRESS3		0x53
+#define SPD_EEPROM_ADDRESS4		0x54
+#define SPD_EEPROM_ADDRESS5		0x55
+#define SPD_EEPROM_ADDRESS6		0x56
+#define SPD_EEPROM_ADDRESS		SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM		0	/* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+#define CONFIG_FSL_DDR_BIST	/* enable built-in memory test */
+#define CONFIG_SYS_MONITOR_LEN		(936 * 1024)
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* SMP Definitinos  */
+#define CPU_RELEASE_ADDR		secondary_boot_func
+
+/* Generic Timer Definitions */
+/*
+ * This is not an accurate number. It is used in start.S. The frequency
+ * will be udpated later when get_bus_freq(0) is available.
+ */
+
+#define COUNTER_FREQUENCY		25000000	/* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* Serial Port */
+#define CONFIG_PL01X_SERIAL
+#define CONFIG_PL011_CLOCK		(get_bus_freq(0) / 4)
+#define CONFIG_SYS_SERIAL0		0x21c0000
+#define CONFIG_SYS_SERIAL1		0x21d0000
+#define CONFIG_SYS_SERIAL2		0x21e0000
+#define CONFIG_SYS_SERIAL3		0x21f0000
+/*below might needs to be removed*/
+#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
+					(void *)CONFIG_SYS_SERIAL1, \
+					(void *)CONFIG_SYS_SERIAL2, \
+					(void *)CONFIG_SYS_SERIAL3 }
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH		0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET	0x00F00000
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH		0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET	0x00F20000
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS	5000
+
+/* Define phy_reset function to boot the MC based on mcinitcmd.
+ * This happens late enough to properly fixup u-boot env MAC addresses.
+ */
+#define CONFIG_RESET_PHY_R
+
+/*
+ * Carve out a DDR region which will not be used by u-boot/Linux
+ *
+ * It will be used by MC and Debug Server. The MC region must be
+ * 512MB aligned, so the min size to hide is 512MB.
+ */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(256UL * 1024 * 1024)
+#endif
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+#define I2C_MUX_CH_DEFAULT		0x8
+
+/* RTC */
+#define RTC
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51  /* Channel 3*/
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+/* Qixis */
+#define CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR		0x66
+
+/* PCI */
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* SATA */
+
+#ifdef CONFIG_SCSI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SATA1		AHCI_BASE_ADDR1
+#define CONFIG_SYS_SATA2		AHCI_BASE_ADDR2
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+/* USB */
+#ifdef CONFIG_USB
+#define CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#endif
+
+/* FlexSPI */
+#ifdef CONFIG_NXP_FSPI
+#define NXP_FSPI_FLASH_SIZE		SZ_64M
+#define NXP_FSPI_FLASH_NUM		1
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
+#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ / 4)
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_OFFSET		0x500000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_ENV_OFFSET)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+/* Initial environment variables */
+#define XSPI_MC_INIT_CMD			\
+	"env exists secureboot && "		\
+	"esbc_validate 0x20700000 && "		\
+	"esbc_validate 0x20740000 ;"		\
+	"fsl_mc start mc 0x20a00000 0x20e00000\0"
+
+#define SD_MC_INIT_CMD				\
+	"mmc read 0x80a00000 0x5000 0x1200;"	\
+	"mmc read 0x80e00000 0x7000 0x800;"	\
+	"env exists secureboot && "		\
+	"mmc read 0x80700000 0x3800 0x10 && "	\
+	"mmc read 0x80740000 0x3A00 0x10 && "	\
+	"esbc_validate 0x80700000 && "		\
+	"esbc_validate 0x80740000 ;"		\
+	"fsl_mc start mc 0x80a00000 0x80e00000\0"
+
+#define EXTRA_ENV_SETTINGS			\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xa0000000\0"			\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"fdt_addr=0x64f00000\0"			\
+	"kernel_start=0x1000000\0"		\
+	"kernelheader_start=0x7C0000\0"		\
+	"scriptaddr=0x80000000\0"		\
+	"scripthdraddr=0x80080000\0"		\
+	"fdtheader_addr_r=0x80100000\0"		\
+	"kernelheader_addr_r=0x80200000\0"	\
+	"kernel_addr_r=0x81000000\0"		\
+	"kernelheader_size=0x40000\0"		\
+	"fdt_addr_r=0x90000000\0"		\
+	"load_addr=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"kernel_addr_sd=0x8000\0"		\
+	"kernelhdr_addr_sd=0x3E00\0"            \
+	"kernel_size_sd=0x1d000\0"              \
+	"kernelhdr_size_sd=0x10\0"              \
+	"console=ttyAMA0,38400n8\0"		\
+	BOOTENV					\
+	"mcmemsize=0x70000000\0"		\
+	XSPI_MC_INIT_CMD				\
+	"boot_scripts=lx2160ardb_boot.scr\0"	\
+	"boot_script_hdr=hdr_lx2160ardb_bs.out\0"	\
+	"scan_dev_for_boot_part="		\
+		"part list ${devtype} ${devnum} devplist; "	\
+		"env exists devplist || setenv devplist 1; "	\
+		"for distro_bootpart in ${devplist}; do "	\
+			"if fstype ${devtype} "			\
+				"${devnum}:${distro_bootpart} "	\
+				"bootfstype; then "		\
+				"run scan_dev_for_boot; "	\
+			"fi; "					\
+		"done\0"					\
+	"boot_a_script="					\
+		"load ${devtype} ${devnum}:${distro_bootpart} "	\
+			"${scriptaddr} ${prefix}${script}; "	\
+		"env exists secureboot && load ${devtype} "	\
+			"${devnum}:${distro_bootpart} "		\
+			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
+			"&& esbc_validate ${scripthdraddr};"	\
+		"source ${scriptaddr}\0"
+
+#define XSPI_NOR_BOOTCOMMAND						\
+			"env exists mcinitcmd && env exists secureboot "\
+			"&& esbc_validate 0x20780000; "			\
+			"env exists mcinitcmd && "			\
+			"fsl_mc lazyapply dpl 0x20d00000; "		\
+			"run distro_bootcmd;run xspi_bootcmd; "		\
+			"env exists secureboot && esbc_halt;"
+
+#define SD_BOOTCOMMAND						\
+		"env exists mcinitcmd && mmcinfo; "		\
+		"mmc read 0x80d00000 0x6800 0x800; "		\
+		"env exists mcinitcmd && env exists secureboot "	\
+		" && mmc read 0x80780000 0x3C00 0x10 "		\
+		"&& esbc_validate 0x80780000;env exists mcinitcmd "	\
+		"&& fsl_mc lazyapply dpl 0x80d00000;"		\
+		"run distro_bootcmd;run sd_bootcmd;"		\
+		"env exists secureboot && esbc_halt;"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(MMC, mmc, 0) \
+	func(SCSI, scsi, 0)
+#include <config_distro_bootcmd.h>
+
+#endif /* __LX2_COMMON_H */
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
new file mode 100644
index 0000000..662e601
--- /dev/null
+++ b/include/configs/lx2160aqds.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __LX2_QDS_H
+#define __LX2_QDS_H
+
+#include "lx2160a_common.h"
+
+/* Qixis */
+#define QIXIS_XMAP_MASK			0x07
+#define QIXIS_XMAP_SHIFT		5
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x20
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_QSPI		0xff
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SD
+#define QIXIS_RCW_SRC_SD		0x08
+#define NON_EXTENDED_DUTCFG
+#define QIXIS_SDID_MASK			0x07
+#define QIXIS_ESDHC_NO_ADAPTER		0x7
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_100		0x0
+#define QIXIS_SYSCLK_125		0x1
+#define QIXIS_SYSCLK_133		0x2
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_100		0x0
+#define QIXIS_DDRCLK_125		0x1
+#define QIXIS_DDRCLK_133		0x2
+
+#define BRDCFG4_EMI1SEL_MASK		0xF8
+#define BRDCFG4_EMI1SEL_SHIFT		3
+#define BRDCFG4_EMI2SEL_MASK		0x07
+#define BRDCFG4_EMI2SEL_SHIFT		0
+
+/* VID */
+
+#define I2C_MUX_CH_VOL_MONITOR		0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR		0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+#define CONFIG_VID_FLS_ENV		"lx2160aqds_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN			775
+#define VDD_MV_MAX			925
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE                  0x0
+#define PMBUS_CMD_READ_VOUT             0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
+#define PMBUS_CMD_VOUT_COMMAND          0x21
+#define PWM_CHANNEL0                    0x0
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM		0
+#define I2C_MUX_CH_RTC			0xB
+
+/*
+ * MMC
+ */
+#ifdef CONFIG_MMC
+#ifndef __ASSEMBLY__
+u8 qixis_esdhc_detect_quirk(void);
+#endif
+#define CONFIG_ESDHC_DETECT_QUIRK  qixis_esdhc_detect_quirk()
+#endif
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME		"DPMAC17@rgmii-id"
+
+#define AQ_PHY_ADDR1		0x00
+#define AQ_PHY_ADDR2		0x01
+#define AQ_PHY_ADDR3		0x02
+#define AQ_PHY_ADDR4		0x03
+
+#define CORTINA_NO_FW_UPLOAD
+#define CORTINA_PHY_ADDR1	0x0
+
+#define INPHI_PHY_ADDR1		0x0
+#define INPHI_PHY_ADDR2		0x1
+
+#define RGMII_PHY_ADDR1		0x01
+#define RGMII_PHY_ADDR2		0x02
+
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	EXTRA_ENV_SETTINGS			\
+	"lx2160aqds_vdd_mv=800\0"		\
+	"BOARD=lx2160aqds\0"			\
+	"xspi_bootcmd=echo Trying load from flexspi..;"		\
+		"sf probe 0:0 && sf read $load_addr "		\
+		"$kernel_start $kernel_size ; env exists secureboot &&"	\
+		"sf read $kernelheader_addr_r $kernelheader_start "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		" bootm $load_addr#$BOARD\0"			\
+	"sd_bootcmd=echo Trying load from sd card..;"		\
+		"mmcinfo; mmc read $load_addr "			\
+		"$kernel_addr_sd $kernel_size_sd ;"		\
+		"env exists secureboot && mmc read $kernelheader_addr_r "\
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$BOARD\0"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2_QDS_H */
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
new file mode 100644
index 0000000..c6bacb6
--- /dev/null
+++ b/include/configs/lx2160ardb.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __LX2_RDB_H
+#define __LX2_RDB_H
+
+#include "lx2160a_common.h"
+
+/* Qixis */
+#define QIXIS_XMAP_MASK			0x07
+#define QIXIS_XMAP_SHIFT		5
+#define QIXIS_RST_CTL_RESET_EN		0x30
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x20
+#define QIXIS_LBMAP_QSPI		0x00
+#define QIXIS_RCW_SRC_QSPI		0xff
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SD
+#define QIXIS_RCW_SRC_SD           0x08
+#define NON_EXTENDED_DUTCFG
+
+/* VID */
+
+#define I2C_MUX_CH_VOL_MONITOR		0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR		0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+#define CONFIG_VID_FLS_ENV		"lx2160ardb_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN			775
+#define VDD_MV_MAX			855
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE                  0x0
+#define PMBUS_CMD_READ_VOUT             0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
+#define PMBUS_CMD_VOUT_COMMAND          0x21
+#define PWM_CHANNEL0                    0x0
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM		4
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
+
+#define AQR107_PHY_ADDR1	0x04
+#define AQR107_PHY_ADDR2	0x05
+#define AQR107_IRQ_MASK		0x0C
+
+#define CORTINA_NO_FW_UPLOAD
+#define CORTINA_PHY_ADDR1	0x0
+#define INPHI_PHY_ADDR1		0x0
+
+#define RGMII_PHY_ADDR1		0x01
+#define RGMII_PHY_ADDR2		0x02
+
+#endif
+
+/* EMC2305 */
+#define I2C_MUX_CH_EMC2305		0x09
+#define I2C_EMC2305_ADDR		0x4D
+#define I2C_EMC2305_CMD		0x40
+#define I2C_EMC2305_PWM		0x80
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	           0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	           0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	    1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	EXTRA_ENV_SETTINGS			\
+	"lx2160ardb_vdd_mv=800\0"		\
+	"BOARD=lx2160ardb\0"			\
+	"xspi_bootcmd=echo Trying load from flexspi..;"		\
+		"sf probe 0:0 && sf read $load_addr "		\
+		"$kernel_start $kernel_size ; env exists secureboot &&"	\
+		"sf read $kernelheader_addr_r $kernelheader_start "	\
+		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+		" bootm $load_addr#$BOARD\0"			\
+	"sd_bootcmd=echo Trying load from sd card..;"		\
+		"mmcinfo; mmc read $load_addr "			\
+		"$kernel_addr_sd $kernel_size_sd ;"		\
+		"env exists secureboot && mmc read $kernelheader_addr_r "\
+		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
+		" && esbc_validate ${kernelheader_addr_r};"	\
+		"bootm $load_addr#$BOARD\0"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2_RDB_H */
diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
new file mode 100644
index 0000000..113e844
--- /dev/null
+++ b/include/configs/m53menlo.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Menlosystems M53Menlo configuration
+ * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
+ */
+
+#ifndef __M53MENLO_CONFIG_H__
+#define __M53MENLO_CONFIG_H__
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2			CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE			(gd->ram_size)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	0x70000000
+#define CONFIG_SYS_MEMTEST_END		0x8ff00000
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+#endif
+
+/*
+ * NAND
+ */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_IP_REGS_BASE	NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_MXC_NAND_HWECC
+
+/* Environment is in NAND */
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_RANGE		(4 * CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET		(8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
+#define CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#endif
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x0
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC0"
+#endif
+
+/*
+ * I2C
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_RTC_BUS_NUM		1 /* I2C2 */
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_MXC_USB_PORT		1
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_BASE_ADDR
+#define CONFIG_LBA48
+#endif
+
+/*
+ * LCD
+ */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASHIMAGE_GUARD
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
+
+/* LVDS display */
+#define CONFIG_SYS_LDB_CLOCK			33260000
+#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_SPLASH_SOURCE
+
+/* IIM Fuses */
+#define CONFIG_FSL_IIM
+
+/* Watchdog */
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTFILE		"boot/fitImage"
+#define CONFIG_LOADADDR		0x70800000
+#define CONFIG_BOOTCOMMAND	"run mmc_mmc"
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/*
+ * NAND SPL
+ */
+#define CONFIG_SPL_TARGET		"u-boot-with-nand-spl.imx"
+#define CONFIG_SPL_PAD_TO		0x8000
+#define CONFIG_SPL_STACK		0x70004000
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_HOSTNAME		"m53menlo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"consdev=ttymxc0\0"						\
+	"baudrate=115200\0"						\
+	"bootscript=boot.scr\0"						\
+	"mmcdev=0\0"							\
+	"mmcpart=1\0"							\
+	"rootpath=/srv/\0"						\
+	"kernel_addr_r=0x72000000\0"					\
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"				\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"			\
+	"netdev=eth0\0"							\
+	"splashsource=mmc_fs\0"						\
+	"splashfile=boot/usplash.bmp.gz\0"				\
+	"splashimage=0x88000000\0"					\
+	"splashpos=m,m\0"						\
+	"stdout=serial,vidconsole\0"					\
+	"stderr=serial,vidconsole\0"					\
+	"addcons="							\
+		"setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"addip="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0"				\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc="							\
+		"setenv bootargs ${bootargs} ${miscargs}\0"		\
+	"addargs=run addcons addmisc addmtd\0"				\
+	"mmcload="							\
+		"mmc rescan ; load mmc ${mmcdev}:${mmcpart} "		\
+		"${kernel_addr_r} ${bootfile}\0"			\
+	"miscargs=nohlt panic=1\0"					\
+	"mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw "	\
+		"rootwait\0"						\
+	"mmc_mmc="							\
+		"run mmcload mmcargs addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0"	\
+	"net_nfs="							\
+		"run netload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"nfsargs="							\
+		"setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0"	\
+	"try_bootscript="						\
+		"mmc rescan;"						\
+		"if test -e mmc 0:1 ${bootscript} ; then "		\
+		"if load mmc 0:1 ${kernel_addr_r} ${bootscript};"	\
+		"then ; "						\
+			"echo Running bootscript... ; "			\
+			"source ${kernel_addr_r} ; "			\
+		"fi ; "							\
+		"fi\0"
+
+#if defined(CONFIG_SPL_BUILD)
+#undef CONFIG_WATCHDOG
+#define CONFIG_HW_WATCHDOG
+#endif
+
+#endif	/* __M53MENLO_CONFIG_H__ */
diff --git a/include/configs/malta.h b/include/configs/malta.h
new file mode 100644
index 0000000..f536234
--- /dev/null
+++ b/include/configs/malta.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+#ifndef _MALTA_CONFIG_H
+#define _MALTA_CONFIG_H
+
+/*
+ * System configuration
+ */
+#define CONFIG_MALTA
+
+#define CONFIG_MEMSIZE_IN_BYTES
+
+#define CONFIG_PCI_GT64120
+#define CONFIG_PCI_MSC01
+#define CONFIG_PCNET
+#define CONFIG_PCNET_79C973
+#define PCNET_HAS_PROM
+
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
+
+/*
+ * CPU Configuration
+ */
+#define CONFIG_SYS_MHZ			250	/* arbitrary value */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
+#else
+# define CONFIG_SYS_SDRAM_BASE		0x80000000
+#endif
+#define CONFIG_SYS_MEM_SIZE		(256 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x01000000)
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x00100000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x00800000)
+
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+#define CONFIG_SYS_BOOTM_LEN		(64 * 1024 * 1024)
+
+/*
+ * Serial driver
+ */
+#define CONFIG_SYS_NS16550_PORT_MAPPED
+
+/*
+ * Flash configuration
+ */
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_FLASH_BASE		0xffffffffbe000000
+#else
+# define CONFIG_SYS_FLASH_BASE		0xbe000000
+#endif
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR \
+	(CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
+
+/*
+ * IDE/ATA
+ */
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_ISA_IO_BASE_ADDRESS
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01f0
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+
+/*
+ * Commands
+ */
+
+#endif /* _MALTA_CONFIG_H */
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
new file mode 100644
index 0000000..9d5fbcd
--- /dev/null
+++ b/include/configs/maxbcm.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_DB_MV7846MP_GP_H
+#define _CONFIG_DB_MV7846MP_GP_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* SPI NOR flash default params, used by sf commands */
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
+
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
+ * 0x4000.4030			bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
+ * 0x4007.fffc			BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+/* SPL related SPI defines */
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CONFIG_DDR_FIXED_SIZE		(1 << 20)	/* 1GiB */
+#define CONFIG_BOARD_ECC_SUPPORT	/* this board supports ECC */
+
+#endif /* _CONFIG_DB_MV7846MP_GP_H */
diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h
new file mode 100644
index 0000000..667dac7
--- /dev/null
+++ b/include/configs/mccmon6.h
@@ -0,0 +1,282 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016-2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#include "imx6_spl.h"
+
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000)
+#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000)
+#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000)
+#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K)
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x18000000
+
+/*
+ * Below defines are set but NOT really used since we by
+ * design force U-Boot run when we boot in development
+ * mode from SD card (SD2)
+ */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800)
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000)
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+/* NOR 16-bit mode */
+#define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_FLASH_VERIFY
+
+/* NOR Flash MTD */
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define CONFIG_SYS_FLASH_BANKS_SIZES	{ (32 * SZ_1M) }
+
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc0,115200 quiet\0" \
+	"fdtfile=imx6q-mccmon6.dtb\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"boot_os=yes\0" \
+	"disable_giga=yes\0" \
+	"download_kernel=" \
+		"tftpboot ${kernel_addr} ${kernel_file};" \
+		"tftpboot ${fdt_addr} ${fdtfile};\0" \
+	"get_boot_medium=" \
+		"setenv boot_medium nor;" \
+		"setexpr.l _src_sbmr1 *0x020d8004;" \
+		"setexpr _b_medium ${_src_sbmr1} '&' 0x00000040;" \
+		"if test ${_b_medium} = 40; then " \
+			"setenv boot_medium sdcard;" \
+		"fi\0" \
+	"kernel_file=uImage\0" \
+	"load_kernel=" \
+		"load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \
+		"load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \
+	"boot_sd=" \
+		"echo '#######################';" \
+		"echo '# Factory SDcard Boot #';" \
+		"echo '#######################';" \
+		"setenv mmcdev 1;" \
+		"setenv mmcfactorydev 0;" \
+		"setenv mmcfactorypart 1;" \
+		"run factory_flash_img;\0" \
+	"boot_nor=" \
+		"setenv kernelnor 0x08180000;" \
+		"setenv dtbnor 0x09980000;" \
+		"setenv bootargs console=${console} " \
+		CONFIG_MTDPARTS_DEFAULT " " \
+		"root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \
+		"cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \
+		"bootm ${kernelnor} - ${dtbloadaddr};\0" \
+	"boot_recovery=" \
+		"echo '#######################';" \
+		"echo '# RECOVERY SWU Boot   #';" \
+		"echo '#######################';" \
+		"setenv rootfsloadaddr 0x13000000;" \
+		"setenv swukernelnor 0x08980000;" \
+		"setenv swurootfsnor 0x09180000;" \
+		"setenv swudtbnor 0x099A0000;" \
+		"setenv bootargs console=${console} " \
+		CONFIG_MTDPARTS_DEFAULT " " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+		    ":${hostname}::off root=/dev/ram rw;" \
+		"cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \
+		"cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \
+		"bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \
+	"boot_tftp=" \
+		"echo '#######################';" \
+		"echo '# TFTP Boot           #';" \
+		"echo '#######################';" \
+		"if run download_kernel; then " \
+		     "setenv bootargs console=${console} " \
+		     "root=/dev/mmcblk0p2 rootwait;" \
+		     "bootm ${kernel_addr} - ${fdt_addr};" \
+		"fi\0" \
+	"bootcmd=" \
+		"if test -n ${recovery_status}; then " \
+		     "run boot_recovery;" \
+		"else " \
+		     "if test ! -n ${boot_medium}; then " \
+			  "run get_boot_medium;" \
+			  "if test ${boot_medium} = sdcard; then " \
+			      "run boot_sd;" \
+			  "else " \
+			      "run boot_nor;" \
+			  "fi;" \
+		     "else " \
+			  "if test ${boot_medium} = tftp; then " \
+			      "run boot_tftp;" \
+			  "fi;" \
+		     "fi;" \
+		"fi\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"fdt_addr=0x18000000\0" \
+	"bootdev=1\0" \
+	"bootpart=1\0" \
+	"kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \
+	"netdev=eth0\0" \
+	"load_addr=0x11000000\0" \
+	"dtbloadaddr=0x12000000\0" \
+	"uboot_file=u-boot.img\0" \
+	"SPL_file=SPL\0" \
+	"load_uboot=tftp ${load_addr} ${uboot_file}\0" \
+	"nor_img_addr=0x11000000\0" \
+	"nor_img_file=core-image-lwn-mccmon6.nor\0" \
+	"emmc_img_file=core-image-lwn-mccmon6.ext4\0" \
+	"nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \
+	"nor_img_size=0x02000000\0" \
+	"factory_script_file=factory.scr\0" \
+	"factory_load_script=" \
+		"if test -e mmc ${mmcdev}:${mmcfactorypart} " \
+		    "${factory_script_file}; then " \
+		    "load mmc ${mmcdev}:${mmcfactorypart} " \
+		     "${loadaddr} ${factory_script_file};" \
+		"fi\0" \
+	"factory_script=echo Running factory script from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"factory_flash_img="\
+		"echo 'Flash mccmon6 with factory images'; " \
+		"if run factory_load_script; then " \
+			"run factory_script;" \
+		"else " \
+		    "echo No factory script: ${factory_script_file} found on " \
+		    "device ${mmcdev};" \
+		    "run factory_nor_img;" \
+		    "run factory_eMMC_img;" \
+		"fi\0" \
+	"factory_eMMC_img="\
+		"echo 'Update mccmon6 eMMC image'; " \
+		"if load mmc ${mmcdev}:${mmcfactorypart} " \
+		    "${loadaddr} ${emmc_img_file}; then " \
+		    "setexpr fw_sz ${filesize} / 0x200;" \
+		    "setexpr fw_sz ${fw_sz} + 1;" \
+		    "mmc dev ${mmcfactorydev};" \
+		    "mmc write ${loadaddr} 0x0 ${fw_sz};" \
+		"fi\0" \
+	"factory_nor_img="\
+		"echo 'Update mccmon6 NOR image'; " \
+		"if load mmc ${mmcdev}:${mmcfactorypart} " \
+		    "${nor_img_addr} ${nor_img_file}; then " \
+			"run nor_update;" \
+		"fi\0" \
+	"nor_update=" \
+		    "protect off ${nor_bank_start} +${nor_img_size};" \
+		    "erase ${nor_bank_start} +${nor_img_size};" \
+		    "setexpr nor_img_size ${nor_img_size} / 4; " \
+		    "cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \
+	"tftp_nor_uboot="\
+		"echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \
+		"setenv nor_img_file u-boot.img; " \
+		"setenv nor_img_size 0x80000; " \
+		"setenv nor_bank_start 0x08080000; " \
+		"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+		    "run nor_update;" \
+		"fi\0" \
+	"tftp_nor_uImg="\
+		"echo 'Update mccmon6 NOR uImage via TFTP'; " \
+		"setenv nor_img_file uImage; " \
+		"setenv nor_img_size 0x500000; " \
+		"setenv nor_bank_start 0x08180000; " \
+		"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+		    "run nor_update;" \
+		"fi\0" \
+	"tftp_nor_dtb="\
+		"echo 'Update mccmon6 NOR DTB via TFTP'; " \
+		"setenv nor_img_file imx6q-mccmon6.dtb; " \
+		"setenv nor_img_size 0x20000; " \
+		"setenv nor_bank_start 0x09980000; " \
+		"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+		    "run nor_update;" \
+		"fi\0" \
+	"tftp_nor_img="\
+		"echo 'Update mccmon6 NOR image via TFTP'; " \
+		"if tftpboot ${nor_img_addr} ${nor_img_file}; then " \
+		    "run nor_update;" \
+		"fi\0" \
+	"tftp_nor_SPL="\
+		"if tftp ${load_addr} SPL_padded; then " \
+		    "erase 0x08000000 +0x20000;" \
+		    "cp.b ${load_addr} 0x08000000 0x20000;" \
+		"fi;\0" \
+	"tftp_sd_SPL="\
+	    "if mmc dev 1; then "      \
+		"if tftp ${load_addr} ${SPL_file}; then " \
+		    "setexpr fw_sz ${filesize} / 0x200; " \
+		    "setexpr fw_sz ${fw_sz} + 1; " \
+		    "mmc write ${load_addr} 0x2 ${fw_sz};" \
+		"fi;" \
+	    "fi;\0" \
+	"tftp_sd_uboot="\
+	    "if mmc dev 1; then "      \
+		"if run load_uboot; then " \
+		    "setexpr fw_sz ${filesize} / 0x200; " \
+		    "setexpr fw_sz ${fw_sz} + 1; " \
+		    "mmc write ${load_addr} 0x8A ${fw_sz};" \
+		"fi;" \
+	    "fi;\0"
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			(SZ_128K)
+
+/* Envs are stored in NOR flash */
+#define CONFIG_ENV_SECT_SIZE    (SZ_128K)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + 0x40000)
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x60000)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#endif			       /* __CONFIG_H * */
diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h
new file mode 100644
index 0000000..d212a7f
--- /dev/null
+++ b/include/configs/medcom-wide.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011-2012
+ *  Avionic Design GmbH <www.avionic-design.de>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra20-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Medcom-Wide"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+/* NAND support */
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Environment in NAND, aligned to start of last sector */
+#define CONFIG_ENV_OFFSET		(SZ_512M - SZ_128K) /* 128K sectors */
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h
new file mode 100644
index 0000000..d0450af
--- /dev/null
+++ b/include/configs/meerkat96.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Linaro Ltd.
+ * Copyright (C) 2016 NXP Semiconductors
+ *
+ * Configuration settings for Meerkat96 board.
+ */
+
+#ifndef __MEERKAT96_CONFIG_H
+#define __MEERKAT96_CONFIG_H
+
+#include "mx7_common.h"
+#include <imximage.h>
+
+#define PHYS_SDRAM_SIZE			SZ_512M
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment configs */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		0
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+
+/* USB configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+
+#endif
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
new file mode 100644
index 0000000..3a173a2
--- /dev/null
+++ b/include/configs/meesc.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009-2015
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * Configuation settings for the esd MEESC board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* 32.768 kHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16000000/* 16.0 MHz crystal */
+
+/* Misc CPU related */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define PHYS_SDRAM					ATMEL_BASE_CS1 /* 0x20000000 */
+#define PHYS_SDRAM_SIZE				0x02000000     /* 32 MByte */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_SIZE
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x00100000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x00100000)
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+# define CONFIG_SYS_MAX_NAND_DEVICE		1
+# define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3 /* 0x40000000 */
+# define CONFIG_SYS_NAND_DBW_8
+# define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+# define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT			20
+#undef CONFIG_RESET_PHY_R
+
+/* hw-controller addresses */
+#define CONFIG_ET1100_BASE		0x70000000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env in dataflash on CS0 */
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_ENV_SECT_SIZE	0x210
+
+#elif CONFIG_SYS_USE_NANDFLASH
+
+/* bootstrap + u-boot + env + linux in nandflash */
+# define CONFIG_ENV_OFFSET		0xC0000
+# define CONFIG_ENV_SIZE		0x20000
+
+#endif
+
+#define CONFIG_SYS_CBSIZE		512
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + \
+					128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/meson64.h b/include/configs/meson64.h
new file mode 100644
index 0000000..f8d3eee
--- /dev/null
+++ b/include/configs/meson64.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Amlogic Meson 64bits SoCs
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ */
+
+#ifndef __MESON64_CONFIG_H
+#define __MESON64_CONFIG_H
+
+/* Generic Interrupt Controller Definitions */
+#if defined(CONFIG_MESON_AXG)
+#define GICD_BASE			0xffc01000
+#define GICC_BASE			0xffc02000
+#else /* MESON GXL and GXBB */
+#define GICD_BASE			0xc4301000
+#define GICC_BASE			0xc4302000
+#endif
+
+/* For splashscreen */
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define STDOUT_CFG "vidconsole,serial"
+#else
+#define STDOUT_CFG "serial"
+#endif
+
+#ifdef CONFIG_USB_KEYBOARD
+#define STDIN_CFG "usbkbd,serial"
+#else
+#define STDIN_CFG "serial"
+#endif
+
+#define CONFIG_CPU_ARMV8
+#define CONFIG_REMAKE_ELF
+#ifndef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE			0x2000
+#endif
+#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
+#define CONFIG_SYS_CBSIZE		1024
+
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_INIT_SP_ADDR		0x20000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_BOOTM_LEN		(64 << 20) /* 64 MiB */
+
+/* ROM USB boot support, auto-execute boot.scr at scriptaddr */
+#define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \
+	"bootcmd_romusb=" \
+		"if test \"${boot_source}\" = \"usb\" && " \
+				"test -n \"${scriptaddr}\"; then " \
+			"echo '(ROM USB boot)'; " \
+			"source ${scriptaddr}; " \
+		"fi\0"
+
+#define BOOTENV_DEV_NAME_ROMUSB(devtypeu, devtypel, instance)	\
+		"romusb "
+
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#ifndef BOOT_TARGET_DEVICES
+#define BOOT_TARGET_DEVICES(func) \
+	func(ROMUSB, romusb, na)  \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2) \
+	BOOT_TARGET_DEVICES_USB(func) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+#endif
+
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"stdin=" STDIN_CFG "\0" \
+	"stdout=" STDOUT_CFG "\0" \
+	"stderr=" STDOUT_CFG "\0" \
+	"fdt_addr_r=0x08008000\0" \
+	"scriptaddr=0x08000000\0" \
+	"kernel_addr_r=0x08080000\0" \
+	"pxefile_addr_r=0x01080000\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	"fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+	BOOTENV
+#endif
+
+#include <config_distro_bootcmd.h>
+
+#endif /* __MESON64_CONFIG_H */
diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h
new file mode 100644
index 0000000..055fb44
--- /dev/null
+++ b/include/configs/meson64_android.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Android Amlogic Meson 64bits SoCs
+ *
+ * Copyright (C) 2019 Baylibre, SAS
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef __MESON64_ANDROID_CONFIG_H
+#define __MESON64_ANDROID_CONFIG_H
+
+#define CONFIG_SYS_MMC_ENV_DEV	2
+#define CONFIG_SYS_MMC_ENV_PART	1
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_OFFSET	(-0x10000)
+
+
+#define BOOTENV_DEV_FASTBOOT(devtypeu, devtypel, instance) \
+	"bootcmd_fastboot=" \
+		"sm reboot_reason reason;" \
+		"setenv run_fastboot 0;" \
+		"if test \"${boot_source}\" = \"usb\"; then " \
+			"echo Fastboot forced by usb rom boot;" \
+			"setenv run_fastboot 1;" \
+		"fi;" \
+		"if gpt verify mmc ${mmcdev} ${partitions}; then; " \
+		"else " \
+			"echo Broken MMC partition scheme;" \
+			"setenv run_fastboot 1;" \
+		"fi;" \
+		"if test \"${reason}\" = \"bootloader\" -o " \
+			"\"${reason}\" = \"fastboot\"; then " \
+			"echo Fastboot asked by reboot reason;" \
+			"setenv run_fastboot 1;" \
+		"fi;" \
+		"if test \"${skip_fastboot}\" -eq 1; then " \
+			"echo Fastboot skipped by environment;" \
+			"setenv run_fastboot 0;" \
+		"fi;" \
+		"if test \"${force_fastboot}\" -eq 1; then " \
+			"echo Fastboot forced by environment;" \
+			"setenv run_fastboot 1;" \
+		"fi;" \
+		"if test \"${run_fastboot}\" -eq 1; then " \
+			"echo Running Fastboot...;" \
+			"fastboot 0;" \
+		"fi\0"
+
+#define BOOTENV_DEV_NAME_FASTBOOT(devtypeu, devtypel, instance)	\
+		"fastboot "
+
+/* TOFIX: Run actual recovery instead of fastboot */
+#define BOOTENV_DEV_RECOVERY(devtypeu, devtypel, instance) \
+	"bootcmd_recovery=" \
+		"pinmux dev pinctrl@14;" \
+		"pinmux dev pinctrl@40;" \
+		"sm reboot_reason reason;" \
+		"setenv run_recovery 0;" \
+		"if run check_button; then " \
+			"echo Recovery button is pressed;" \
+			"setenv run_recovery 1;" \
+		"elif test \"${reason}\" = \"recovery\" -o " \
+			  "\"${reason}\" = \"update\"; then " \
+			"echo Recovery asked by reboot reason;" \
+			"setenv run_recovery 1;" \
+		"fi;" \
+		"if test \"${skip_recovery}\" -eq 1; then " \
+			"echo Recovery skipped by environment;" \
+			"setenv run_recovery 0;" \
+		"fi;" \
+		"if test \"${force_recovery}\" -eq 1; then " \
+			"echo Recovery forced by environment;" \
+			"setenv run_recovery 1;" \
+		"fi;" \
+		"if test \"${run_recovery}\" -eq 1; then " \
+			"echo Running Recovery...;" \
+			"fastboot 0;" \
+		"fi\0"
+
+#define BOOTENV_DEV_NAME_RECOVERY(devtypeu, devtypel, instance)	\
+		"recovery "
+
+#define BOOTENV_DEV_SYSTEM(devtypeu, devtypel, instance) \
+	"bootcmd_system=" \
+		"echo Loading Android boot partition...;" \
+		"mmc dev ${mmcdev};" \
+		"setenv bootargs ${bootargs} console=${console} androidboot.serialno=${serial#};" \
+		"part start mmc ${mmcdev} ${bootpart} boot_start;" \
+		"part size mmc ${mmcdev} ${bootpart} boot_size;" \
+		"if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \
+			"echo Running Android...;" \
+			"bootm ${loadaddr};" \
+		"fi;" \
+		"echo Failed to boot Android...;" \
+		"reset\0"
+
+#define BOOTENV_DEV_NAME_SYSTEM(devtypeu, devtypel, instance)	\
+		"system "
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(FASTBOOT, fastboot, na) \
+	func(RECOVERY, recovery, na) \
+	func(SYSTEM, system, na) \
+
+#define PREBOOT_LOAD_LOGO \
+	"mmc dev ${mmcdev};" \
+	"part start mmc ${mmcdev} ${logopart} boot_start;" \
+	"part size mmc ${mmcdev} ${logopart} boot_size;" \
+	"if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \
+			"bmp display ${loadaddr} m m;" \
+	"fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS                                     \
+	"partitions=" PARTS_DEFAULT "\0"                              \
+	"mmcdev=2\0"                                                  \
+	"bootpart=1\0"                                                \
+	"logopart=2\0"                                                \
+	"gpio_recovery=88\0"                                          \
+	"check_button=gpio input ${gpio_recovery};test $? -eq 0;\0"   \
+	"load_logo=" PREBOOT_LOAD_LOGO "\0"			      \
+	"console=/dev/ttyAML0\0"                                      \
+	"bootargs=no_console_suspend\0"                               \
+	"stdin=" STDIN_CFG "\0"                                       \
+	"stdout=" STDOUT_CFG "\0"                                     \
+	"stderr=" STDOUT_CFG "\0"                                     \
+	"loadaddr=0x01000000\0"                                       \
+	"fdt_addr_r=0x01000000\0"                                     \
+	"scriptaddr=0x08000000\0"                                     \
+	"kernel_addr_r=0x01080000\0"                                  \
+	"pxefile_addr_r=0x01080000\0"                                 \
+	"ramdisk_addr_r=0x13000000\0"                                 \
+	"fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" BOOTENV
+
+#include <configs/meson64.h>
+
+#endif /* __MESON64_ANDROID_CONFIG_H */
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
new file mode 100644
index 0000000..f1d0def
--- /dev/null
+++ b/include/configs/microblaze-generic.h
@@ -0,0 +1,198 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2010 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/xilinx/microblaze-generic/xparameters.h"
+
+/* MicroBlaze CPU */
+#define	MICROBLAZE_V5		1
+
+#define CONFIG_SYS_BOOTM_LEN	(64 * 1024 * 1024)
+
+/* linear and spi flash memory */
+#ifdef XILINX_FLASH_START
+#define	FLASH
+#undef	SPIFLASH
+#undef	RAMENV	/* hold environment in flash */
+#else
+#undef	FLASH
+#undef	SPIFLASH
+#define	RAMENV	/* hold environment in RAM */
+#endif
+
+/* uart */
+/* The following table includes the supported baudrates */
+# define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/* setting reset address */
+/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/
+
+#define CONFIG_SYS_MALLOC_LEN	0xC0000
+
+/* Stack location before relocation */
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_TEXT_BASE - \
+					 CONFIG_SYS_MALLOC_F_LEN)
+
+/*
+ * CFI flash memory layout - Example
+ * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
+ * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
+ *
+ * SECT_SIZE = 0x20000;			128kB is one sector
+ * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
+ *
+ * 0x2200_0000	CONFIG_SYS_FLASH_BASE
+ *					FREE		256kB
+ * 0x2204_0000	CONFIG_ENV_ADDR
+ *					ENV_AREA	128kB
+ * 0x2206_0000
+ *					FREE
+ * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
+ *
+ */
+
+#ifdef FLASH
+# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
+# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
+/* ?empty sector */
+# define CONFIG_SYS_FLASH_EMPTY_INFO	1
+/* max number of memory banks */
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+/* max number of sectors on one chip */
+# define CONFIG_SYS_MAX_FLASH_SECT	512
+/* hardware flash protection */
+/* use buffered writes (20x faster) */
+# ifdef	RAMENV
+#  define CONFIG_ENV_SIZE	0x1000
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+
+# else	/* FLASH && !RAMENV */
+/* 128K(one sector) for env */
+#  define CONFIG_ENV_SECT_SIZE	0x20000
+#  define CONFIG_ENV_ADDR \
+			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+#  define CONFIG_ENV_SIZE	0x20000
+# endif /* FLASH && !RAMBOOT */
+#else /* !FLASH */
+
+#ifdef SPIFLASH
+# ifdef	RAMENV
+#  define CONFIG_ENV_SIZE	0x1000
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+
+# else	/* SPIFLASH && !RAMENV */
+/* 128K(two sectors) for env */
+#  define CONFIG_ENV_SECT_SIZE	0x10000
+#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
+/* Warning: adjust the offset in respect of other flash content and size */
+#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
+# endif /* SPIFLASH && !RAMBOOT */
+#else /* !SPIFLASH */
+
+/* ENV in RAM */
+# define CONFIG_ENV_SIZE	0x1000
+# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+#endif /* !SPIFLASH */
+#endif /* !FLASH */
+
+#define XILINX_USE_ICACHE 1
+#define XILINX_USE_DCACHE 1
+
+#if defined(XILINX_USE_ICACHE)
+# define CONFIG_ICACHE
+#else
+# undef CONFIG_ICACHE
+#endif
+
+#if defined(XILINX_USE_DCACHE)
+# define CONFIG_DCACHE
+#else
+# undef CONFIG_DCACHE
+#endif
+
+#ifndef XILINX_DCACHE_BYTE_SIZE
+#define XILINX_DCACHE_BYTE_SIZE	32768
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#if defined(CONFIG_MTD_PARTITIONS)
+/* MTD partitions */
+
+/* default mtd partition table */
+#endif
+
+/* size of console buffer */
+#define	CONFIG_SYS_CBSIZE	512
+/* max number of command args */
+#define	CONFIG_SYS_MAXARGS	15
+/* default load address */
+#define	CONFIG_SYS_LOAD_ADDR	0
+
+#define	CONFIG_HOSTNAME		"microblaze-generic"
+#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
+
+/* architecture dependent code */
+#define	CONFIG_SYS_USR_EXCEP	/* user exception */
+
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
+					"nor0=flash-0\0"\
+					"mtdparts=mtdparts=flash-0:"\
+					"256k(u-boot),256k(env),3m(kernel),"\
+					"1m(romfs),1m(cramfs),-(jffs2)\0"\
+					"nc=setenv stdout nc;"\
+					"setenv stdin nc\0" \
+					"serial=setenv stdout serial;"\
+					"setenv stdin serial\0"
+#endif
+
+#if defined(CONFIG_XILINX_AXIEMAC)
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
+#endif
+
+/* SPL part */
+
+#ifdef CONFIG_SYS_FLASH_BASE
+# define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
+#endif
+
+/* for booting directly linux */
+
+#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
+					 0x40000)
+#define CONFIG_SYS_FDT_SIZE		(16 << 10)
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
+					 0x1000000)
+
+/* SP location before relocation, must use scratch RAM */
+/* BRAM start */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x0
+/* BRAM size - will be generated */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x100000
+
+# define CONFIG_SPL_STACK_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 CONFIG_SYS_MALLOC_F_LEN)
+
+/* Just for sure that there is a space for stack */
+#define CONFIG_SPL_STACK_SIZE		0x100
+
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 CONFIG_SYS_INIT_RAM_ADDR - \
+					 CONFIG_SYS_MALLOC_F_LEN - \
+					 CONFIG_SPL_STACK_SIZE)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h
new file mode 100644
index 0000000..82c7fbb
--- /dev/null
+++ b/include/configs/microchip_mpfs_icicle.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+/*
+ * Print Buffer Size
+ */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * max number of command args
+ */
+#define CONFIG_SYS_MAXARGS	16
+
+/*
+ * Boot Argument Buffer Size
+ */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Size of malloc() pool
+ * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
+ */
+#define CONFIG_SYS_MALLOC_LEN	(512 << 10)
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_0		0x80000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_0_SIZE	0x40000000 /* 1 GB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_0
+
+/* Init Stack Pointer */
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x200000)
+
+#define CONFIG_SYS_LOAD_ADDR	0x80000000 /* SDRAM */
+
+/*
+ * memtest works on DRAM
+ */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
+
+/* When we use RAM as ENV */
+#define CONFIG_ENV_SIZE	0x2000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
new file mode 100644
index 0000000..d0fe582
--- /dev/null
+++ b/include/configs/minnowmax.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Google, Inc
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=usbkbd,serial\0" \
+					"stdout=vidconsole,serial\0" \
+					"stderr=vidconsole,serial\0" \
+					"usb_pgood_delay=40\0"
+
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x006ef000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/miqi_rk3288.h b/include/configs/miqi_rk3288.h
new file mode 100644
index 0000000..c9691a0
--- /dev/null
+++ b/include/configs/miqi_rk3288.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdin=serial,cros-ec-keyb\0" \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3288_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
new file mode 100644
index 0000000..3ce4b70
--- /dev/null
+++ b/include/configs/mpc8308_p1m.h
@@ -0,0 +1,319 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+
+/*
+ * On-board devices
+ *
+ * TSECs
+ */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+
+#define CONFIG_SYS_GPIO1_PRELIM
+/* GPIO Default input/output settings */
+#define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
+/*
+ * Default GPIO values:
+ * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
+ */
+#define CONFIG_SYS_GPIO1_DAT        0x08008C00
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_ODT_RD_NEVER \
+					| CSCONFIG_ODT_WR_ONLY_CURRENT \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10)
+					/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03600100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32)
+				/* 0x43080000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		64 /* FLASH size is 64M */
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(1000 * 1024)
+/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(500 * 1024)
+
+/*
+ * SJA1000 CAN controller on Local Bus
+ */
+#define CONFIG_SYS_SJA1000_BASE	0xFBFF0000
+
+
+/*
+ * CPLD on Local Bus
+ */
+#define CONFIG_SYS_CPLD_BASE	0xFBFF8000
+
+
+/*
+ * Serial Port
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+/* enable PCIE clock */
+#define CONFIG_SYS_SCCR_PCIEXP1CM	1
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		1
+#define TSEC2_PHY_ADDR		2
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		0
+#define TSEC2_FLAGS		0
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${consoledev},${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"kernel_addr=FC0A0000\0"					\
+	"fdt_addr=FC2A0000\0"						\
+	"ramdisk_addr=FC2C0000\0"					\
+	"u-boot=mpc8308_p1m/u-boot.bin\0"				\
+	"kernel_addr_r=1000000\0"					\
+	"fdt_addr_r=C00000\0"						\
+	"hostname=mpc8308_p1m\0"					\
+	"bootfile=mpc8308_p1m/uImage\0"					\
+	"fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"				\
+	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"bootcmd=run flash_self\0"					\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+		" +${filesize};cp.b ${fileaddr} "			\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
+	"upd=run load update\0"						\
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h
new file mode 100644
index 0000000..5f67893
--- /dev/null
+++ b/include/configs/mt7623.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT7623 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef __MT7623_H
+#define __MT7623_H
+
+#include <linux/sizes.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_SYS_MAXARGS		8
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+#define CONFIG_SYS_CBSIZE		SZ_1K
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +	\
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M
+#define CONFIG_SYS_NONCACHED_MEMORY	SZ_1M
+
+/* Environment */
+#define CONFIG_ENV_SIZE			SZ_4K
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Preloader -> Uboot */
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_2M - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* UBoot -> Kernel */
+#define CONFIG_LOADADDR			0x84000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* MMC */
+#define MMC_SUPPORTS_TUNING
+
+/* DRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* This is needed for kernel booting */
+#define FDT_HIGH			"fdt_high=0xac000000\0"
+
+/* Extra environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	FDT_HIGH
+
+/* Ethernet */
+#define CONFIG_IPADDR			192.168.1.1
+#define CONFIG_SERVERIP			192.168.1.2
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		0x100000
+
+#endif
diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h
new file mode 100644
index 0000000..741b6fb
--- /dev/null
+++ b/include/configs/mt7629.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT7629 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#ifndef __MT7629_H
+#define __MT7629_H
+
+#include <linux/sizes.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_SYS_MAXARGS		8
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+#define CONFIG_SYS_CBSIZE		SZ_1K
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +	\
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M
+#define CONFIG_SYS_NONCACHED_MEMORY	SZ_1M
+
+/* Environment */
+#define CONFIG_ENV_SIZE			SZ_4K
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Defines for SPL */
+#define CONFIG_SPL_STACK		0x106000
+#define CONFIG_SPL_MAX_SIZE		SZ_64K
+#define CONFIG_SPL_MAX_FOOTPRINT	SZ_64K
+#define CONFIG_SPL_PAD_TO		0x10000
+
+#define CONFIG_SPI_ADDR			0x30000000
+#define CONFIG_SYS_UBOOT_BASE		(CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)
+
+/* SPL -> Uboot */
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_2M - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* UBoot -> Kernel */
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x40000000
+#define CONFIG_LOADADDR			0x42007f1c
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* DRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+/* Ethernet */
+#define CONFIG_IPADDR			192.168.1.1
+#define CONFIG_SERVERIP			192.168.1.2
+
+#endif
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
new file mode 100644
index 0000000..a041ddb
--- /dev/null
+++ b/include/configs/mv-common.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+/*
+ * This file contains Marvell Board Specific common defincations.
+ * This file should be included in board config header file.
+ *
+ * It supports common definations for Kirkwood platform
+ * TBD: support for Orion5X platforms
+ */
+
+#ifndef _MV_COMMON_H
+#define _MV_COMMON_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+/*
+ * Custom CONFIG_SYS_TEXT_BASE can be done in <board>.h
+ */
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#if !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_COM1		MV_UART_CONSOLE_BASE
+#endif
+
+/* auto boot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
+
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024 * 4) /* 4MiB for malloc() */
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00800000	/* 8M */
+#define CONFIG_SYS_MEMTEST_END	0x00ffffff	/*(_16M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
+
+/* ====> Include platform Common Definitions */
+#include <asm/arch/config.h>
+
+/* ====> Include driver Common Definitions */
+/*
+ * Common NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#endif
+
+#endif /* _MV_COMMON_H */
diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h
new file mode 100644
index 0000000..486650f
--- /dev/null
+++ b/include/configs/mv-plug-common.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009-2015
+ * Marvell Semiconductor <www.marvell.com>
+ */
+
+#ifndef _CONFIG_MARVELL_PLUG_H
+#define _CONFIG_MARVELL_PLUG_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_MARVELL_PLUG_H */
diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h
new file mode 100644
index 0000000..bc24903
--- /dev/null
+++ b/include/configs/mvebu_armada-37xx.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_MVEBU_ARMADA_37XX_H
+#define _CONFIG_MVEBU_ARMADA_37XX_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+
+/* auto boot */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
+					  115200, 230400, 460800, 921600 }
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG		/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */
+
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(4 << 20) /* 4MiB for malloc() */
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00800000	/* 8M */
+#define CONFIG_SYS_MEMTEST_END	0x00ffffff	/*(_16M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
+
+/* End of 16M scrubbed by training in bootrom */
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE + 0xFF0000)
+
+/*
+ * I2C
+ */
+#define CONFIG_I2C_MV
+#define CONFIG_SYS_I2C_SLAVE		0x0
+
+/*
+ * SPI Flash configuration
+ */
+
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS		/* required for UBI partition support */
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		0x180000 /* as Marvell U-Boot version */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
+
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_ARP_TIMEOUT	200
+#define CONFIG_NET_RETRY_COUNT	50
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
+
+/* USB ethernet */
+
+/*
+ * SATA/SCSI/AHCI configuration
+ */
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_LBA48
+#define CONFIG_SYS_64BIT_LBA
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					 CONFIG_SYS_SCSI_MAX_LUN)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(SCSI, scsi, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"scriptaddr=0x4d00000\0"	\
+	"pxefile_addr_r=0x4e00000\0"	\
+	"fdt_addr_r=0x4f00000\0"	\
+	"kernel_addr_r=0x5000000\0"	\
+	"ramdisk_addr_r=0x8000000\0"	\
+	BOOTENV
+
+#endif /* _CONFIG_MVEBU_ARMADA_37XX_H */
diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h
new file mode 100644
index 0000000..3be3683
--- /dev/null
+++ b/include/configs/mvebu_armada-8k.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_MVEBU_ARMADA_8K_H
+#define _CONFIG_MVEBU_ARMADA_8K_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+
+/* auto boot */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
+					  115200, 230400, 460800, 921600 }
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG		/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */
+
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(4 << 20) /* 4MiB for malloc() */
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00800000	/* 8M */
+#define CONFIG_SYS_MEMTEST_END	0x00ffffff	/*(_16M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
+
+/* End of 16M scrubbed by training in bootrom */
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE + 0xFF0000)
+
+#define CONFIG_ENV_OFFSET		0x180000 /* as Marvell U-Boot version */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
+
+/* When runtime detection fails this is the default */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_ARP_TIMEOUT	200
+#define CONFIG_NET_RETRY_COUNT	50
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
+
+/* USB ethernet */
+
+/*
+ * SATA/SCSI/AHCI configuration
+ */
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_LBA48
+#define CONFIG_SYS_64BIT_LBA
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					 CONFIG_SYS_SCSI_MAX_LUN)
+
+/*
+ * PCI configuration
+ */
+#ifdef CONFIG_PCIE_DW_MVEBU
+#define CONFIG_E1000
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(SCSI, scsi, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"scriptaddr=0x4d00000\0"	\
+	"pxefile_addr_r=0x4e00000\0"	\
+	"fdt_addr_r=0x4f00000\0"	\
+	"kernel_addr_r=0x5000000\0"	\
+	"ramdisk_addr_r=0x8000000\0"	\
+	"fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+	BOOTENV
+
+#endif /* _CONFIG_MVEBU_ARMADA_8K_H */
diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
new file mode 100644
index 0000000..330f020
--- /dev/null
+++ b/include/configs/mx23_olinuxino.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIGS_MX23_OLINUXINO_H__
+#define __CONFIGS_MX23_OLINUXINO_H__
+
+/* System configurations */
+#define CONFIG_MACH_TYPE	4105
+
+/* U-Boot Commands */
+
+/* Memory configuration */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET	(256 * 1024)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#endif
+
+/* Status LED */
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
+/* Ethernet */
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"update_sd_firmware_filename=u-boot.sd\0" \
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "	\
+		"if tftp ${update_sd_firmware_filename} ; then " \
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "	\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+		"fi ; "	\
+		"fi\0" \
+	"script=boot.scr\0"	\
+	"uimage=uImage\0" \
+	"console=ttyAMA0\0" \
+	"fdt_file=imx23-olinuxino.dtb\0" \
+	"fdt_addr=0x41000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript="  \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; "	\
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"usb start; " \
+		"run netargs; "	\
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${uimage}; " \
+		"if test ${boot_fdt} = yes; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi;" \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_MX23_OLINUXINO_H__ */
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
new file mode 100644
index 0000000..da1d53c
--- /dev/null
+++ b/include/configs/mx23evk.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale i.MX23 EVK board config
+ *
+ * Copyright (C) 2013 Otavio Salvador <otavio@ossystems.com.br>
+ * on behalf of O.S. Systems Software LTDA.
+ */
+#ifndef __CONFIGS_MX23EVK_H__
+#define __CONFIGS_MX23EVK_H__
+
+/* System configurations */
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX23EVK
+
+/* U-Boot Commands */
+
+/* Memory configuration */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET	(256 * 1024)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#endif
+
+/* USB */
+#ifdef	CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+
+/* Framebuffer support */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(512 << 10)
+#endif
+
+/* Boot Linux */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environments */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"update_sd_firmware_filename=u-boot.sd\0" \
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "	\
+		"if tftp ${update_sd_firmware_filename} ; then " \
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "	\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+		"fi ; "	\
+		"fi\0" \
+	"script=boot.scr\0"	\
+	"image=zImage\0" \
+	"console=ttyAMA0\0" \
+	"fdt_file=imx23-evk.dtb\0" \
+	"fdt_addr=0x41000000\0" \
+	"boot_fdt=try\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript="  \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; "	\
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else " \
+				"echo ERR: Fail to boot from MMC; " \
+			"fi; " \
+		"fi; " \
+	"else exit; fi"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_MX23EVK_H__ */
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
new file mode 100644
index 0000000..6537e3a
--- /dev/null
+++ b/include/configs/mx25pdk.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/* High Level Configuration Options */
+
+#define CONFIG_SYS_TEXT_BASE		0x81200000
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_SYS_TIMER_RATE		32768
+#define CONFIG_SYS_TIMER_COUNTER	\
+	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX25_3DS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+/* Physical Memory Map */
+
+#define PHYS_SDRAM_1		0x80000000
+#define PHYS_SDRAM_1_SIZE	(64 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IMX_RAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE	IMX_RAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Memory Test */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2)
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+
+/* Serial Info */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* No NOR flash present */
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x1f
+#define CONFIG_ENV_OVERWRITE
+
+/* ESDHC driver */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	IMX_MMC_SDHC1_BASE
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+/* PMIC Configs */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
+#define CONFIG_POWER_FSL_MC34704
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x54
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+
+/* RTC */
+#define CONFIG_RTC_IMXDI
+
+/* Fuse API support */
+#define CONFIG_FSL_IIM
+#define CONFIG_CMD_FUSE
+
+/* Ethernet Configs */
+
+
+#define CONFIG_LOADADDR		0x81000000	/* loadaddr env var */
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x82000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
new file mode 100644
index 0000000..dd04580
--- /dev/null
+++ b/include/configs/mx28evk.h
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Based on m28evk.h:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ */
+#ifndef __CONFIGS_MX28EVK_H__
+#define __CONFIGS_MX28EVK_H__
+
+/* System configurations */
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX28EVK
+
+/* Memory configuration */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* Max 1 GB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#else
+#define CONFIG_ENV_SIZE			(4 * 1024)
+#endif
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(256 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+/* Environment is in NAND */
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_RANGE		(512 * 1024)
+#define CONFIG_ENV_OFFSET		0x300000
+#define CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#endif
+
+/* Environment is in SPI flash */
+#if defined(CONFIG_CMD_SF) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET		0x40000		/* 256K */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#endif
+
+/* UBI and NAND partitioning */
+
+/* FEC Ethernet on SoC */
+#ifdef	CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE
+#define CONFIG_MX28_FEC_MAC_IN_OCOTP
+#endif
+
+/* RTC */
+#ifdef	CONFIG_CMD_DATE
+#define	CONFIG_RTC_MXS
+#endif
+
+/* USB */
+#ifdef	CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#endif
+
+/* Framebuffer support */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(512 << 10)
+#endif
+
+/* Boot Linux */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"ubifs_file=filesystem.ubifs\0" \
+	"update_nand_full_filename=u-boot.nand\0" \
+	"update_nand_firmware_filename=u-boot.sb\0"	\
+	"update_nand_firmware_maxsz=0x100000\0"	\
+	"update_nand_stride=0x40\0"	/* MX28 datasheet ch. 12.12 */ \
+	"update_nand_count=0x4\0"	/* MX28 datasheet ch. 12.12 */ \
+	"update_nand_get_fcb_size="	/* Get size of FCB blocks */ \
+		"nand device 0 ; " \
+		"nand info ; " \
+		"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
+		"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
+	"update_nand_firmware_full=" /* Update FCB, DBBT and FW */ \
+		"if tftp ${update_nand_full_filename} ; then " \
+		"run update_nand_get_fcb_size ; " \
+		"nand scrub -y 0x0 ${filesize} ; " \
+		"nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \
+		"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
+		"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
+		"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
+		"fi\0" \
+	"update_nand_firmware="		/* Update only firmware */ \
+		"if tftp ${update_nand_firmware_filename} ; then " \
+		"run update_nand_get_fcb_size ; " \
+		"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
+		"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \
+		"setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
+		"nand erase ${fcb_sz} ${fw_sz} ; " \
+		"nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
+		"nand write ${loadaddr} ${fw_off} ${filesize} ; " \
+		"fi\0" \
+	"update_nand_kernel="		/* Update kernel */ \
+		"mtdparts default; " \
+		"nand erase.part kernel; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"nand write ${loadaddr} kernel ${filesize}\0" \
+	"update_nand_fdt="		/* Update fdt */ \
+		"mtdparts default; " \
+		"nand erase.part fdt; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${fdt_file}; " \
+		"nand write ${loadaddr} fdt ${filesize}\0" \
+	"update_nand_filesystem="		/* Update filesystem */ \
+		"mtdparts default; " \
+		"nand erase.part filesystem; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${ubifs_file}; " \
+		"ubi part filesystem; " \
+		"ubi create filesystem; " \
+		"ubi write ${loadaddr} filesystem ${filesize}\0" \
+	"nandargs=setenv bootargs console=${console_mainline},${baudrate} " \
+		"rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \
+	"nandboot="		/* Boot from NAND */ \
+		"mtdparts default; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} kernel 0x00400000; " \
+		"if test ${boot_fdt} = yes; then " \
+			"nand read ${fdt_addr} fdt 0x00080000; " \
+			"bootz ${loadaddr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = no; then " \
+				"bootz; " \
+			"else " \
+				"echo \"ERROR: Set boot_fdt to yes or no.\"; " \
+			"fi; " \
+		"fi\0" \
+	"update_sd_firmware_filename=u-boot.sd\0" \
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "	\
+		"if tftp ${update_sd_firmware_filename} ; then " \
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "	\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+		"fi ; "	\
+		"fi\0" \
+	"script=boot.scr\0"	\
+	"image=zImage\0" \
+	"console_fsl=ttyAM0\0" \
+	"console_mainline=ttyAMA0\0" \
+	"fdt_file=imx28-evk.dtb\0" \
+	"fdt_addr=0x41000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
+	"mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript="  \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; "	\
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console_mainline},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; "	\
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi;" \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_MX28EVK_H__ */
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
new file mode 100644
index 0000000..04e3b8f
--- /dev/null
+++ b/include/configs/mx31pdk.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the Freescale i.MX31 PDK board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX31_3DS
+
+#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
+#define CONFIG_SPL_MAX_SIZE	2048
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
+#define CONFIG_FSL_PMIC_BUS	1
+#define CONFIG_FSL_PMIC_CS	2
+#define CONFIG_FSL_PMIC_CLK	1000000
+#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN	32
+#define CONFIG_RTC_MC13XXX
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
+	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
+		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
+	"bootcmd=run bootcmd_net\0"					\
+	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "	\
+		"tftpboot 0x81000000 uImage-mx31; bootm\0"		\
+	"prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; "		\
+		"nand erase 0x0 0x40000; "				\
+		"nand write 0x81000000 0x0 0x40000\0"
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x80010000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x81000000
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		CSD0_BASE
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_INIT_RAM_SIZE)
+
+/*
+ * environment organization
+ */
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_OFFSET_REDUND	0x60000
+#define CONFIG_ENV_SIZE			(128 * 1024)
+
+/*
+ * NAND driver
+ */
+#define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/* NAND configuration for the NAND_SPL */
+
+/* Start copying real U-Boot from the second page */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x3f800
+/* Load U-Boot to this address */
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+
+/* Configuration of lowlevel_init.S (clocks and SDRAM) */
+#define CCM_CCMR_SETUP		0x074B0BF5
+#define CCM_PDR0_SETUP_532MHZ	(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
+				 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
+				 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
+				 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ	(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
+				 PLL_MFN(12))
+
+#define ESDMISC_MDDR_SETUP	0x00000004
+#define ESDMISC_MDDR_RESET_DL	0x0000000c
+#define ESDCFG0_MDDR_SETUP	0x006ac73a
+
+#define ESDCTL_ROW_COL		(ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
+#define ESDCTL_SETTINGS		(ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
+				 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
+#define ESDCTL_PRECHARGE	(ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
+#define ESDCTL_AUTOREFRESH	(ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
+#define ESDCTL_LOADMODEREG	(ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
+#define ESDCTL_RW		ESDCTL_SETTINGS
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
new file mode 100644
index 0000000..e153dfb
--- /dev/null
+++ b/include/configs/mx35pdk.h
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the MX35pdk Freescale board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_MX35
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Set TEXT at the beginning of the NOR flash */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+/*
+ * PMIC Configs
+ */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
+#define CONFIG_POWER_FSL_MC13892
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x08
+#define CONFIG_RTC_MC13XXX
+
+/*
+ * MFD MC9SDZ60
+ */
+#define CONFIG_FSL_MC9SDZ60
+#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR	0x69
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command definition
+ */
+
+#define CONFIG_NET_RETRY_COUNT	100
+
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+/*
+ * Ethernet on the debug board (SMC911)
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETHPRIME
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+#define PHYS_SDRAM_2		CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE	(128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE		(IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+	#define CONFIG_ENV_OFFSET       (1024 * 1024)
+#endif
+
+/*
+ * CFI FLASH driver setup
+ */
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_FLASH_SPANSION_S29WS_N
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/* EHCI driver */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_MXC_USB_PORT	0
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERFACE_DIFF_UNI | \
+				 MXC_EHCI_POWER_PINS_ENABLED | \
+				 MXC_EHCI_OC_PIN_ACTIVE_LOW)
+#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
+
+/* mmc driver */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+
+#define CONFIG_HOSTNAME "mx35pdk"
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth1\0"							\
+	"ethprime=smc911x\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"				\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"loadaddr=80800000\0"						\
+	"kernel_addr_r=80800000\0"					\
+	"hostname=" CONFIG_HOSTNAME "\0"			\
+	"bootfile=" CONFIG_HOSTNAME "/uImage\0"		\
+	"ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0"	\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
+	"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"		\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
+	"update=protect off ${uboot_addr} +80000;"			\
+		"erase ${uboot_addr} +80000;"				\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+	"bootcmd=run net_nfs\0"
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
new file mode 100644
index 0000000..fc498b2
--- /dev/null
+++ b/include/configs/mx51evk.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51EVK Board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+
+#define CONFIG_SYS_FSL_CLK
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX51_BABBAGE
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_FSL_IIM
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
+#define CONFIG_FSL_PMIC_BUS	0
+#define CONFIG_FSL_PMIC_CS	0
+#define CONFIG_FSL_PMIC_CLK	2500000
+#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN	32
+#define CONFIG_RTC_MC13XXX
+
+/*
+ * MMC Configs
+ * */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	MMC_SDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+/*
+ * Eth Configs
+ */
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	PORT_PTS_ULPI
+#define CONFIG_MXC_USB_FLAGS	MXC_EHCI_POWER_PINS_ENABLED
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ETHPRIME		"FEC0"
+
+#define CONFIG_LOADADDR		0x92000000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"fdt_file=imx51-babbage.dtb\0" \
+	"fdt_addr=0x91000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes ||  test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo ERROR: Cannot load the DT; " \
+					"exit; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_MEMTEST_START       0x90000000
+#define CONFIG_SYS_MEMTEST_END         0x90010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_DDR_CLKSEL	0
+#define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
+
+/*-----------------------------------------------------------------------
+ * environment organization
+ */
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
new file mode 100644
index 0000000..d25629f
--- /dev/null
+++ b/include/configs/mx53ard.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53ARD Freescale board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_ARD
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_IP_REGS_BASE	NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_MXC_NAND_HWECC
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+/* Eth Configs */
+#define CONFIG_HAS_ETH1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition */
+
+#define CONFIG_ETHPRIME		"smc911x"
+
+#define CONFIG_LOADADDR		0x72000000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x78000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${uimage}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loaduimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+#define PHYS_SDRAM_2		CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE	(512 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE         (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV	0
+
+#define MX53ARD_CS1GCR1		(CSEN | DSZ(2))
+#define MX53ARD_CS1RCR1		(RCSN(2) | OEN (1) | RWSC(22))
+#define MX53ARD_CS1RCR2		RBEN(2)
+#define MX53ARD_CS1WCR1		(WCSN(2) | WEN(2) | WBEN(2) | WWSC(22))
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h
new file mode 100644
index 0000000..bbe0574
--- /dev/null
+++ b/include/configs/mx53cx9020.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015  Beckhoff Automation GmbH & Co. KG
+ * Patrick Bruenn <p.bruenn@beckhoff.com>
+ *
+ * Configuration settings for Beckhoff CX9020.
+ *
+ * Based on Freescale's Linux i.MX mx53loco.h file:
+ * Copyright (C) 2010-2011 Freescale Semiconductor.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_MXC_UART_BASE UART2_BASE
+
+#define CONFIG_FPGA_COUNT 1
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+/* bootz: zImage/initrd.img support */
+
+/* Eth Configs */
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_ETHPRIME		"FEC0"
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition */
+
+#define CONFIG_LOADADDR		0x70010000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_addr_r=0x71ff0000\0" \
+	"pxefile_addr_r=0x73000000\0" \
+	"ramdisk_addr_r=0x72000000\0" \
+	"console=ttymxc1,115200\0" \
+	"uenv=/boot/uEnv.txt\0" \
+	"optargs=\0" \
+	"cmdline=\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcrootfstype=ext4 rootwait fixrtc\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/mmcblk${mmcdev}p${mmcpart} ro " \
+		"rootfstype=${mmcrootfstype} " \
+		"${cmdline}\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadpxe=dhcp;setenv kernel_addr_r ${loadaddr};pxe get;pxe boot;\0" \
+	"loadrd=load mmc ${bootpart} ${ramdisk_addr_r} ${bootdir}/${rdfile};" \
+		"setenv rdsize ${filesize}\0" \
+	"loadfdt=echo loading ${fdt_path} ...;" \
+		"load mmc ${bootpart} ${fdt_addr_r} ${fdt_path}\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"echo Checking for: ${uenv} ...;" \
+			"setenv bootpart ${mmcdev}:${mmcpart};" \
+			"if test -e mmc ${bootpart} ${uenv}; then " \
+				"load mmc ${bootpart} ${loadaddr} ${uenv};" \
+				"env import -t ${loadaddr} ${filesize};" \
+				"echo Loaded environment from ${uenv};" \
+				"if test -n ${dtb}; then " \
+					"setenv fdt_file ${dtb};" \
+					"echo Using: dtb=${fdt_file} ...;" \
+				"fi;" \
+				"echo Checking for uname_r in ${uenv}...;" \
+				"if test -n ${uname_r}; then " \
+					"echo Running uname_boot ...;" \
+					"run uname_boot;" \
+				"fi;" \
+			"fi;" \
+		"fi;\0" \
+	"uname_boot="\
+		"setenv bootdir /boot; " \
+		"setenv bootfile vmlinuz-${uname_r}; " \
+		"setenv ccatfile /boot/ccat.rbf; " \
+		"echo loading CCAT firmware from ${ccatfile}; " \
+		"load mmc ${bootpart} ${loadaddr} ${ccatfile}; " \
+		"fpga load 0 ${loadaddr} ${filesize}; " \
+		"if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
+			"echo loading ${bootdir}/${bootfile} ...; " \
+			"run loadimage;" \
+			"setenv fdt_path /boot/dtbs/${uname_r}/${fdt_file}; " \
+			"if test -e mmc ${bootpart} ${fdt_path}; then " \
+				"run loadfdt;" \
+			"else " \
+				"echo; echo unable to find ${fdt_file} ...;" \
+				"echo booting legacy ...;"\
+				"run mmcargs;" \
+				"echo debug: [${bootargs}] ... ;" \
+				"echo debug: [bootz ${loadaddr}] ... ;" \
+				"bootz ${loadaddr}; " \
+			"fi;" \
+			"run mmcargs;" \
+			"echo debug: [${bootargs}] ... ;" \
+			"echo debug: [bootz ${loadaddr} - ${fdt_addr_r}];" \
+			"bootz ${loadaddr} - ${fdt_addr_r}; " \
+		"else " \
+			"echo loading from dhcp ...; " \
+			"run loadpxe; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run mmcboot;"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2			CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE			(gd->ram_size)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* Framebuffer and LCD */
+#define CONFIG_IMX_VIDEO_SKIP
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
new file mode 100644
index 0000000..17ff13d
--- /dev/null
+++ b/include/configs/mx53evk.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_EVK
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+/* PMIC Configs */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR    8
+#define CONFIG_POWER_FSL_MC13892
+#define CONFIG_RTC_MC13XXX
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+/* Eth Configs */
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition */
+
+#define CONFIG_ETHPRIME		"FEC0"
+
+#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
new file mode 100644
index 0000000..65a5993
--- /dev/null
+++ b/include/configs/mx53loco.h
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * Configuration settings for Freescale MX53 low cost board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_LOCO
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+/* Eth Configs */
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_DIALOG_POWER
+#define CONFIG_POWER_FSL
+#define CONFIG_POWER_FSL_MC13892
+#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR	0x48
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition */
+
+
+#define CONFIG_ETHPRIME		"FEC0"
+
+#define CONFIG_LOADADDR		0x72000000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"fdt_addr=0x71000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes ||  test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo ERROR: Cannot load the DT; " \
+					"exit; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2			CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE			(gd->ram_size)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment starts at 768k = 768 * 1024 = 786432 */
+#define CONFIG_ENV_OFFSET		786432
+/*
+ * Detect overlap between U-Boot image and environment area in build-time
+ *
+ * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset
+ * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
+ *
+ * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
+ * write the direct value here
+ */
+#define CONFIG_BOARD_SIZE_LIMIT		785408
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#ifdef CONFIG_CMD_SATA
+	#define CONFIG_SYS_SATA_MAX_DEVICE      1
+	#define CONFIG_DWC_AHSATA_PORT_ID       0
+	#define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
+	#define CONFIG_LBA48
+#endif
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
new file mode 100644
index 0000000..59988ef
--- /dev/null
+++ b/include/configs/mx53ppd.h
@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * Configuration settings for Freescale MX53 low cost board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONSOLE_DEV	"ttymxc0"
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* Eth Configs */
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+/* USB Configs */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+#define CONFIG_SYS_RTC_BUS_NUM		2
+#define CONFIG_SYS_I2C_RTC_ADDR	0x30
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_DIALOG_POWER
+#define CONFIG_POWER_FSL
+#define CONFIG_POWER_FSL_MC13892
+#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR	0x48
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+
+#define CONFIG_ETHPRIME		"FEC0"
+
+#define CONFIG_LOADADDR		0x72000000	/* loadaddr env var */
+
+#define PPD_CONFIG_NFS \
+	"nfsserver=192.168.252.95\0" \
+	"gatewayip=192.168.252.95\0" \
+	"netmask=255.255.255.0\0" \
+	"ipaddr=192.168.252.99\0" \
+	"kernsize=0x2000\0" \
+	"use_dhcp=0\0" \
+	"nfsroot=/opt/springdale/rd\0" \
+	"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
+		"${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \
+	"choose_ip=if test $use_dhcp = 1; then setenv kern_ipconf ip=dhcp; " \
+		"setenv getcmd dhcp; else setenv kern_ipconf " \
+		"ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \
+		"setenv getcmd tftp; fi\0" \
+	"nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \
+		"${nfsserver}:${image}; bootm ${loadaddr}\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	PPD_CONFIG_NFS \
+	"image=/boot/fitImage\0" \
+	"fdt_high=0xffffffff\0" \
+	"dev=mmc\0" \
+	"devnum=2\0" \
+	"rootdev=mmcblk0p\0" \
+	"quiet=quiet loglevel=0\0" \
+	"console=" CONSOLE_DEV "\0" \
+	"lvds=ldb\0" \
+	"setargs=setenv bootargs ${lvds} jtag=on mem=2G " \
+		"vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \
+		"console=${console} ${rtc_status}\0" \
+	"bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \
+		"rootwait ${bootargs}\0" \
+	"doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
+		"then setenv quiet; fi\0" \
+	"hasfirstboot=ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \
+		"/boot/bootcause/firstboot\0" \
+	"swappartitions=setexpr partnum 3 - ${partnum}\0" \
+	"failbootcmd=" \
+		"ppd_lcd_enable; " \
+		"msg=\"Monitor failed to start.  " \
+			"Try again, or contact GE Service for support.\"; " \
+		"echo $msg; " \
+		"setenv stdout vga; " \
+		"echo \"\n\n\n\n    \" $msg; " \
+		"setenv stdout serial; " \
+		"mw.b 0x7000A000 0xbc; " \
+		"mw.b 0x7000A001 0x00; " \
+		"ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \
+	"altbootcmd=" \
+		"run doquiet; " \
+		"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
+		"run hasfirstboot || setenv partnum 0; " \
+		"if test ${partnum} != 0; then " \
+			"setenv bootcause REVERT; " \
+			"run swappartitions loadimage doboot; " \
+		"fi; " \
+		"run failbootcmd\0" \
+	"loadimage=" \
+		"ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
+	"doboot=" \
+		"echo Booting from ${dev}:${devnum}:${partnum} ...; " \
+		"run setargs; " \
+		"run bootargs_emmc; " \
+		"bootm ${loadaddr}\0" \
+	"tryboot=" \
+		"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
+		"run loadimage || run swappartitions && run loadimage || " \
+			"setenv partnum 0 && echo MISSING IMAGE;" \
+		"run doboot; " \
+		"run failbootcmd\0" \
+	"video-mode=" \
+		"lcd:800x480-24@60,monitor=lcd\0" \
+
+#define CONFIG_MMCBOOTCOMMAND \
+	"if mmc dev ${devnum}; then " \
+		"run doquiet; " \
+		"run tryboot; " \
+	"fi; " \
+
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MAXARGS	48	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2			CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE			(gd->ram_size)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_ENV_OFFSET      (12 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (10 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_CMD_FUSE
+#define CONFIG_FSL_IIM
+
+#define CONFIG_SYS_I2C_SPEED	100000
+
+/* I2C1 */
+#define CONFIG_SYS_NUM_I2C_BUSES	9
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \
+				}
+
+#define CONFIG_BCH
+
+/* Backlight Control */
+#define CONFIG_IMX6_PWM_PER_CLK 66666000
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
new file mode 100644
index 0000000..e606ee8
--- /dev/null
+++ b/include/configs/mx53smd.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53SMD Freescale board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_SMD
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_FSL_CLK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+/* Eth Configs */
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition */
+
+#define CONFIG_ETHPRIME		"FEC0"
+
+#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+#define PHYS_SDRAM_2		CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE	(512 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE         (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
new file mode 100644
index 0000000..07b1e06
--- /dev/null
+++ b/include/configs/mx6_common.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef __MX6_COMMON_H
+#define __MX6_COMMON_H
+
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
+#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
+#else
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	L2_PL310_BASE
+#endif
+
+#endif
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_MXC_GPT_HCLK
+
+#define CONFIG_SYS_BOOTM_LEN	0x1000000
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/mach-imx/gpio.h>
+
+#ifndef CONFIG_MX6
+#define CONFIG_MX6
+#endif
+
+#define CONFIG_SYS_FSL_CLK
+
+/* ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Boot options */
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
+	defined(CONFIG_MX6SX) || \
+	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#define CONFIG_LOADADDR		0x82000000
+#else
+#define CONFIG_LOADADDR		0x12000000
+#endif
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE	512
+#define CONFIG_SYS_MAXARGS	32
+
+/* MMC */
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#endif
+
+#endif
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
new file mode 100644
index 0000000..3cf2f1c
--- /dev/null
+++ b/include/configs/mx6cuboxi.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the SolidRun mx6 based boards
+ */
+#ifndef __MX6CUBOXI_CONFIG_H
+#define __MX6CUBOXI_CONFIG_H
+
+#include "mx6_common.h"
+
+#include "imx6_spl.h"
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+#define CONFIG_MXC_UART
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* SATA Configuration */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE      1
+#define CONFIG_DWC_AHSATA_PORT_ID       0
+#define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#endif
+
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_PHY_ATHEROS
+
+/* Framebuffer */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+/* USB */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+
+/* Command definition */
+
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONSOLE_DEV	"ttymxc0"
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* SDHC2 */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"som_rev=undefined\0" \
+	"has_emmc=undefined\0" \
+	"fdtfile=undefined\0" \
+	"fdt_addr_r=0x18000000\0" \
+	"fdt_addr=0x18000000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0"  \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	"ramdiskaddr=0x13000000\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_high=0xffffffff\0" \
+	"ip_dyn=yes\0" \
+	"console=" CONSOLE_DEV ",115200\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"finduuid=part uuid mmc 0:1 uuid\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"findfdt="\
+		"if test ${board_rev} = MX6Q; then " \
+			"setenv fdtprefix imx6q; fi; " \
+		"if test ${board_rev} = MX6DL; then " \
+			"setenv fdtprefix imx6dl; fi; " \
+		"if test ${som_rev} = V15; then " \
+			"setenv fdtsuffix -som-v15; fi; " \
+		"if test ${has_emmc} = yes; then " \
+			"setenv emmcsuffix -emmc; fi; " \
+		"if test ${board_name} = HUMMINGBOARD2 ; then " \
+			"setenv fdtfile ${fdtprefix}-hummingboard2${emmcsuffix}${fdtsuffix}.dtb; fi; " \
+		"if test ${board_name} = HUMMINGBOARD ; then " \
+			"setenv fdtfile ${fdtprefix}-hummingboard${emmcsuffix}${fdtsuffix}.dtb; fi; " \
+		"if test ${board_name} = CUBOXI ; then " \
+			"setenv fdtfile ${fdtprefix}-cubox-i${emmcsuffix}${fdtsuffix}.dtb; fi; " \
+		"if test ${fdtfile} = undefined; then " \
+			"echo WARNING: Could not determine dtb to use; fi; \0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(SATA, sata, 0) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS
+#endif /* CONFIG_SPL_BUILD */
+
+/* Physical Memory Map */
+#define CONFIG_SYS_SDRAM_BASE          MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_OFFSET		(SZ_1M - CONFIG_ENV_SIZE)
+
+#endif                         /* __MX6CUBOXI_CONFIG_H */
diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h
new file mode 100644
index 0000000..58d5ebf
--- /dev/null
+++ b/include/configs/mx6memcal.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010-2018 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the virtual mx6memcal board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SPL */
+
+#include "mx6_common.h"
+#include "imx6_spl.h"
+
+#undef CONFIG_MMC
+#undef CONFIG_SPL_MMC_SUPPORT
+#undef CONFIG_GENERIC_MMC
+#undef CONFIG_CMD_FUSE
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
+
+#define CONFIG_MXC_UART
+#ifdef CONFIG_SERIAL_CONSOLE_UART1
+#if defined(CONFIG_MX6SL)
+#define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
+#else
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+#endif
+#elif defined(CONFIG_SERIAL_CONSOLE_UART2)
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+#else
+#error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx)
+#endif
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16)
+
+/* Physical Memory Map */
+#define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_MXC_USB_PORTSC	PORT_PTS_UTMI
+
+#endif	       /* __CONFIG_H */
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
new file mode 100644
index 0000000..6e4e751
--- /dev/null
+++ b/include/configs/mx6qarm2.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q Armadillo2 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART4_BASE
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+#define	CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define	CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc3\0" \
+	"fdt_file=imx6q-arm2.dtb\0" \
+	"fdt_addr=0x18000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=1\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev};" \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
new file mode 100644
index 0000000..56b10d8
--- /dev/null
+++ b/include/configs/mx6sabre_common.h
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ */
+
+#ifndef __MX6QSABRE_COMMON_CONFIG_H
+#define __MX6QSABRE_COMMON_CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_IMX_THERMAL
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_MXC_UART
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		1
+
+#define CONFIG_PHY_ATHEROS
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+#define EMMC_ENV \
+	"emmcdev=2\0" \
+	"update_emmc_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+			"if mmc dev ${emmcdev} 1; then "	\
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0"
+#else
+#define EMMC_ENV ""
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"fdtfile=undefined\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"console=" CONSOLE_DEV "\0" \
+	"dfuspi=dfu 0 sf 0:0:10000000:0\0" \
+	"dfu_alt_info_spl=spl raw 0x400\0" \
+	"dfu_alt_info_img=u-boot raw 0x10000\0" \
+	"dfu_alt_info=spl raw 0x400\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"initrd_high=0xffffffff\0" \
+	"splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	EMMC_ENV	  \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=PARTUUID=${uuid} rootwait rw\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run finduuid; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+		"findfdt="\
+			"if test $fdtfile = undefined; then " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
+					"setenv fdtfile imx6qp-sabreauto.dtb; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
+					"setenv fdtfile imx6q-sabreauto.dtb; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
+					"setenv fdtfile imx6dl-sabreauto.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
+					"setenv fdtfile imx6qp-sabresd.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
+					"setenv fdtfile imx6q-sabresd.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
+					"setenv fdtfile imx6dl-sabresd.dtb; fi; " \
+				"if test $fdtfile = undefined; then " \
+					"echo WARNING: Could not determine dtb to use; fi; " \
+			"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt;" \
+	"mmc dev ${mmcdev};" \
+	"if mmc rescan; then " \
+		"if run loadbootscript; then " \
+		"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#endif
+
+/* Framebuffer */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+#define CONFIG_USBD_HS
+
+#endif                         /* __MX6QSABRE_COMMON_CONFIG_H */
diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h
new file mode 100644
index 0000000..e444930
--- /dev/null
+++ b/include/configs/mx6sabreauto.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreAuto board.
+ */
+
+#ifndef __MX6SABREAUTO_CONFIG_H
+#define __MX6SABREAUTO_CONFIG_H
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+#define CONFIG_MACH_TYPE	3529
+#define CONFIG_MXC_UART_BASE	UART4_BASE
+#define CONSOLE_DEV		"ttymxc3"
+
+/* USB Configs */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x30, 8}, {0x32, 8}, {0x34, 8} }
+
+#include "mx6sabre_common.h"
+
+/* Falcon Mode */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
+#define CONFIG_SYS_SPL_ARGS_ADDR       0x18000000
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_SECT_SIZE      (128 * 1024)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1    /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256   /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#endif
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+#endif                         /* __MX6SABREAUTO_CONFIG_H */
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
new file mode 100644
index 0000000..ec15375
--- /dev/null
+++ b/include/configs/mx6sabresd.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ */
+
+#ifndef __MX6SABRESD_CONFIG_H
+#define __MX6SABRESD_CONFIG_H
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+#define CONFIG_MACH_TYPE	3980
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONSOLE_DEV		"ttymxc0"
+
+#include "mx6sabre_common.h"
+
+/* Falcon Mode */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
+#define CONFIG_SYS_SPL_ARGS_ADDR       0x18000000
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
+
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SDHC3 */
+#endif
+
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(3, 19)
+#endif
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1 /* Enabled USB controller number */
+#endif
+
+#endif                         /* __MX6SABRESD_CONFIG_H */
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
new file mode 100644
index 0000000..5d649f6
--- /dev/null
+++ b/include/configs/mx6slevk.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SL EVK board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_MX6SL_EVK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_FEC_MXC_PHYADDR		0
+
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx6sl-evk.dtb\0" \
+	"fdt_addr=0x88000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=1\0" \
+	"mmcpart=1\0" \
+	"finduuid=part uuid mmc 1:2 uuid\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=PARTUUID=${uuid} rootwait rw\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run finduuid; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_512M)
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			SZ_8K
+
+#if defined CONFIG_SPI_BOOT
+#define CONFIG_ENV_OFFSET               (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE            (64 * 1024)
+#else
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#endif
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#endif
+
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SDHC2*/
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
new file mode 100644
index 0000000..b96e631
--- /dev/null
+++ b/include/configs/mx6sllevk.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SL EVK board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* I2C Configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"epdc_waveform=epdc_splash.bin\0" \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx6sll-evk.dtb\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"usb start; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_128M)
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			SZ_2G
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_SYS_MMC_ENV_PART		0   /* user partition */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+
+#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC1 */
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_IOMUX_LPSR
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
new file mode 100644
index 0000000..c4d8a89
--- /dev/null
+++ b/include/configs/mx6sxsabreauto.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SX Sabreauto board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx6sx-sabreauto.dtb\0" \
+	"fdt_addr=0x88000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000)
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC3_BASE_ADDR
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+
+/* Network */
+
+#define CONFIG_FEC_MXC
+
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x0
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_ETHPRIME                 "FEC"
+
+#define CONFIG_PHY_ATHEROS
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define FSL_QSPI_FLASH_SIZE		SZ_32M
+#define FSL_QSPI_FLASH_NUM		2
+#endif
+
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#define CONFIG_ENV_SIZE			SZ_8K
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV		0  /*USDHC3*/
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
new file mode 100644
index 0000000..dc4181d
--- /dev/null
+++ b/include/configs/mx6sxsabresd.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SX Sabresd board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+#ifdef CONFIG_IMX_BOOTAUX
+/* Set to QSPI2 B flash at default */
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000
+
+#define UPDATE_M4_ENV \
+	"m4image=m4_qspi.bin\0" \
+	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
+	"update_m4_from_sd=" \
+		"if sf probe 1:0; then " \
+			"if run loadm4image; then " \
+				"setexpr fw_sz ${filesize} + 0xffff; " \
+				"setexpr fw_sz ${fw_sz} / 0x10000; "	\
+				"setexpr fw_sz ${fw_sz} * 0x10000; "	\
+				"sf erase 0x0 ${fw_sz}; " \
+				"sf write ${loadaddr} 0x0 ${filesize}; " \
+			"fi; " \
+		"fi\0" \
+	"m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+#else
+#define UPDATE_M4_ENV ""
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	UPDATE_M4_ENV \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx6sx-sdb.dtb\0" \
+	"fdt_addr=0x88000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \
+	"mmcdev=2\0" \
+	"mmcpart=1\0" \
+	"finduuid=part uuid mmc 2:2 uuid\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=PARTUUID=${uuid} rootwait rw\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run finduuid; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"findfdt="\
+		"if test test $board_rev = REVA ; then " \
+			"setenv fdt_file imx6sx-sdb-reva.dtb; fi; " \
+
+#define CONFIG_BOOTCOMMAND \
+	   "run findfdt; " \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000)
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* Network */
+#define CONFIG_FEC_MXC
+
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x1
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_ETHPRIME                 "FEC"
+
+#define CONFIG_PHY_ATHEROS
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(2, 0)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(2, 1)
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_FSL_QSPI_LE
+#define CONFIG_SYS_FSL_QSPI_AHB
+#ifdef CONFIG_MX6SX_SABRESD_REVA
+#define FSL_QSPI_FLASH_SIZE		SZ_16M
+#else
+#define FSL_QSPI_FLASH_SIZE		SZ_32M
+#endif
+#define FSL_QSPI_FLASH_NUM		2
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR
+#endif
+#endif
+
+#define CONFIG_ENV_OFFSET		(14 * SZ_64K)
+#define CONFIG_ENV_SIZE			SZ_8K
+
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV		2  /*USDHC4*/
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
new file mode 100644
index 0000000..87f8869
--- /dev/null
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
+ */
+#ifndef __MX6UL_14X14_EVK_CONFIG_H
+#define __MX6UL_14X14_EVK_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+#include <asm/mach-imx/gpio.h>
+
+#define is_mx6ul_9x9_evk()	CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK)
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* NAND pin conflicts with usdhc2 */
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
+
+#endif
+
+/* I2C configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#ifdef CONFIG_DM_GPIO
+#define CONFIG_DM_74X164
+#endif
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=undefined\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+		"findfdt="\
+			"if test $fdt_file = undefined; then " \
+				"if test $board_name = EVK && test $board_rev = 9X9; then " \
+					"setenv fdt_file imx6ul-9x9-evk.dtb; fi; " \
+				"if test $board_name = EVK && test $board_rev = 14X14; then " \
+					"setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \
+				"if test $fdt_file = undefined; then " \
+					"echo WARNING: Could not determine dtb to use; fi; " \
+			"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	   "run findfdt;" \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define FSL_QSPI_FLASH_NUM		1
+#define FSL_QSPI_FLASH_SIZE		SZ_32M
+#endif
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_ENET_DEV		1
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x2
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME			"eth0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x1
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"eth1"
+#endif
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#ifndef CONFIG_SPL_BUILD
+#if defined(CONFIG_DM_VIDEO)
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
+#endif
+#endif
+
+#endif
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
new file mode 100644
index 0000000..3bcd0d3
--- /dev/null
+++ b/include/configs/mx6ullevk.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
+ */
+#ifndef __MX6ULLEVK_CONFIG_H
+#define __MX6ULLEVK_CONFIG_H
+
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+#include <asm/mach-imx/gpio.h>
+
+#define PHYS_SDRAM_SIZE	SZ_512M
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+#ifdef CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* NAND pin conflicts with usdhc2 */
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
+#endif
+
+/* I2C configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=undefined\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+		"findfdt="\
+			"if test $fdt_file = undefined; then " \
+				"if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \
+					"setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \
+				"if test $board_name = EVK && test $board_rev = 14X14; then " \
+					"setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \
+				"if test $fdt_file = undefined; then " \
+					"echo WARNING: Could not determine dtb to use; " \
+				"fi; " \
+			"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	   "run findfdt;" \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_IOMUX_LPSR
+
+#define CONFIG_SOFT_SPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define FSL_QSPI_FLASH_NUM		1
+#define FSL_QSPI_FLASH_SIZE		SZ_32M
+#endif
+
+#endif
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
new file mode 100644
index 0000000..b6ded77
--- /dev/null
+++ b/include/configs/mx7_common.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7.
+ */
+
+#ifndef __MX7_COMMON_H
+#define __MX7_COMMON_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/mach-imx/gpio.h>
+
+#ifndef CONFIG_MX7
+#define CONFIG_MX7
+#endif
+
+/* Timer settings */
+#define CONFIG_MXC_GPT_HCLK
+#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
+#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_SYS_BOOTM_LEN	0x1000000
+
+/* Enable iomux-lpsr support */
+#define CONFIG_IOMUX_LPSR
+
+#define CONFIG_LOADADDR                 0x80800000
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		512
+#define CONFIG_SYS_MAXARGS		32
+
+/* UART */
+#define CONFIG_MXC_UART
+
+/* MMC */
+
+#define CONFIG_ARMV7_SECURE_BASE	0x00900000
+
+#define CONFIG_ARMV7_PSCI_1_0
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#endif
+
+/*
+ * If we have defined the OPTEE ram size and not OPTEE it means that we were
+ * launched by OPTEE, because of that we shall skip all the low level
+ * initialization since it was already done by ATF or OPTEE
+ */
+#if (CONFIG_OPTEE_TZDRAM_SIZE != 0)
+#ifndef CONFIG_OPTEE
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+#endif
+
+#endif
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
new file mode 100644
index 0000000..e1f92da
--- /dev/null
+++ b/include/configs/mx7dsabresd.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7D SABRESD board.
+ */
+
+#ifndef __MX7D_SABRESD_CONFIG_H
+#define __MX7D_SABRESD_CONFIG_H
+
+#include "mx7_common.h"
+
+#define PHYS_SDRAM_SIZE			SZ_1G
+
+#define CONFIG_MXC_UART_BASE            UART1_IPS_BASE_ADDR
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define CONFIG_PHY_BROADCOM
+/* ENET1 */
+#define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
+
+/* MMC Config*/
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+
+/* I2C configs */
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#ifdef CONFIG_IMX_BOOTAUX
+/* Set to QSPI1 A flash at default */
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
+
+#define UPDATE_M4_ENV \
+	"m4image=m4_qspi.bin\0" \
+	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
+	"update_m4_from_sd=" \
+		"if sf probe 0:0; then " \
+			"if run loadm4image; then " \
+				"setexpr fw_sz ${filesize} + 0xffff; " \
+				"setexpr fw_sz ${fw_sz} / 0x10000; "	\
+				"setexpr fw_sz ${fw_sz} * 0x10000; "	\
+				"sf erase 0x0 ${fw_sz}; " \
+				"sf write ${loadaddr} 0x0 ${filesize}; " \
+			"fi; " \
+		"fi\0" \
+	"m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+#else
+#define UPDATE_M4_ENV ""
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		"clk_ignore_unused "\
+		"\0" \
+	"initrd_addr=0x83800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+#define CONFIG_DFU_ENV_SETTINGS \
+	"dfu_alt_info=image raw 0 0x800000;"\
+		"u-boot raw 0 0x4000;"\
+		"bootimg part 0 1;"\
+		"rootfs part 0 2\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	UPDATE_M4_ENV \
+	CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_DFU_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx7d-sdb.dtb\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_SIZE			SZ_8K
+
+/*
+ * If want to use nand, define CONFIG_NAND_MXS and rework board
+ * to support nand, since emmc has pin conflicts with nand
+ */
+#ifdef CONFIG_NAND_MXS
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#endif
+
+#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
+
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_USBD_HS
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define FSL_QSPI_FLASH_NUM		1
+#define FSL_QSPI_FLASH_SIZE		SZ_64M
+#define QSPI0_BASE_ADDR			QSPI1_IPS_BASE_ADDR
+#define QSPI0_AMBA_BASE			QSPI0_ARB_BASE_ADDR
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
new file mode 100644
index 0000000..3b02362
--- /dev/null
+++ b/include/configs/mx7ulp_evk.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7ULP EVK board.
+ */
+
+#ifndef __MX7ULP_EVK_CONFIG_H
+#define __MX7ULP_EVK_CONFIG_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_SYS_BOOTM_LEN		0x1000000
+
+#define SRC_BASE_ADDR			CMC1_RBASE
+#define IRAM_BASE_ADDR			OCRAM_0_BASE
+#define IOMUXC_BASE_ADDR		IOMUXC1_RBASE
+
+#define CONFIG_SYS_FSL_USDHC_NUM        1
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define CONFIG_SYS_MMC_ENV_DEV          0	/* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART         0	/* user area */
+#define CONFIG_MMCROOT                  "/dev/mmcblk0p2"  /* USDHC1 */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART    1
+
+#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
+#define CONFIG_ENV_SIZE			SZ_8K
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR			WDG1_RBASE
+
+#define CONFIG_SYS_HZ_CLOCK		1000000 /* Fixed at 1Mhz from TSTMR */
+
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+/*#define CONFIG_REVISION_TAG*/
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(8 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* UART */
+#define LPUART_BASE			LPUART4_RBASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_CACHELINE_SIZE      64
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		512
+
+#define CONFIG_SYS_MAXARGS		256
+
+/* Physical Memory Map */
+
+#define PHYS_SDRAM			0x60000000
+#define PHYS_SDRAM_SIZE			SZ_1G
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+
+#define CONFIG_LOADADDR             0x60800000
+
+#define CONFIG_SYS_MEMTEST_END      0x9E000000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttyLP0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx7ulp-evk.dtb\0" \
+	"fdt_addr=0x63000000\0" \
+	"boot_fdt=try\0" \
+	"earlycon=lpuart32,0x402D0010\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"usb start; "\
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "fi"
+
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	SZ_256K
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
new file mode 100644
index 0000000..e079f80
--- /dev/null
+++ b/include/configs/mxs.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIGS_MXS_H__
+#define __CONFIGS_MXS_H__
+
+/*
+ * Includes
+ */
+
+#if defined(CONFIG_MX23) && defined(CONFIG_MX28)
+#error Select either CONFIG_MX23 or CONFIG_MX28 , never both!
+#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28)
+#error Select one of CONFIG_MX23 or CONFIG_MX28 !
+#endif
+
+#include <asm/arch/regs-base.h>
+
+#if defined(CONFIG_MX23)
+#include <asm/arch/iomux-mx23.h>
+#elif defined(CONFIG_MX28)
+#include <asm/arch/iomux-mx28.h>
+#endif
+
+/*
+ * CPU specifics
+ */
+
+/* Startup hooks */
+
+/* SPL */
+#ifndef CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NO_CPU_SUPPORT
+#define CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/mxs"
+#endif
+
+/* Memory sizes */
+#define CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
+#define CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
+#define CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */
+
+/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00000000
+#if defined(CONFIG_MX23)
+#define CONFIG_SYS_INIT_RAM_SIZE	(32 * 1024)
+#elif defined(CONFIG_MX28)
+#define CONFIG_SYS_INIT_RAM_SIZE	(128 * 1024)
+#endif
+
+/* Point initial SP in SRAM so SPL can use it too. */
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ *
+ * In case of a HAB boot, we cannot for some weird reason use the first 4KiB
+ * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST
+ * blocks, thus U-Boot starts at offset +8 KiB of DRAM start.
+ *
+ * As for the SPL, we must avoid the first 4 KiB as well, but we load the
+ * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
+ */
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+
+/* Booting Linux */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/*
+ * Drivers
+ */
+/*
+ * DUART Serial Driver.
+ * Conflicts with AUART driver which can be set by board.
+ */
+#define CONFIG_PL011_CLOCK		24000000
+#define CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
+/* Default baudrate can be overridden by board! */
+
+/* FEC Ethernet on SoC */
+#ifdef CONFIG_FEC_MXC
+#ifndef CONFIG_ETHPRIME
+#define CONFIG_ETHPRIME			"FEC0"
+#endif
+#ifndef CONFIG_FEC_XCV_TYPE
+#define CONFIG_FEC_XCV_TYPE		RMII
+#endif
+#endif
+
+/* LCD */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#endif
+
+/* NAND */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x60000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#endif
+
+/* OCOTP */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXS_OCOTP
+#endif
+
+/* SPI */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_SPI_HALF_DUPLEX
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_MXS
+#define CONFIG_EHCI_IS_TDI
+#endif
+
+#endif	/* __CONFIGS_MXS_H__ */
diff --git a/include/configs/nas220.h b/include/configs/nas220.h
new file mode 100644
index 0000000..bdfa42f
--- /dev/null
+++ b/include/configs/nas220.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
+ *
+ * based on work from:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef _CONFIG_NAS220_H
+#define _CONFIG_NAS220_H
+
+/*
+ * Machine type ID
+ */
+#define CONFIG_MACH_TYPE		MACH_TYPE_RD88F6192_NAS
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* #define CPU Core subversion */
+#define CONFIG_KW88F6192		/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/* power-on led, regulator, sata0, sata1 */
+#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))
+#define NAS220_GE_OE_VAL_HIGH (0)
+#define NAS220_GE_OE_LOW (~((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)))
+#define NAS220_GE_OE_HIGH (~(0))
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#endif
+
+#define CONFIG_ENV_SIZE	0x10000
+#define CONFIG_ENV_OFFSET 0xa0000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND ""
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootargs=console=ttyS0,115200\0" \
+	"mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\
+	"0x010000@0xa0000(env),"\
+	"0x500000@0xc0000(uimage),"\
+	"0x1a40000@0x5c0000(rootfs)\0" \
+	"mtdids=nand0=orion_nand\0"\
+	"autostart=no\0"\
+	"autoload=no\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS {1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 8
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_KIRKWOOD	/* on Kirkwood platform	*/
+#define CONFIG_EHCI_IS_TDI
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * File system
+ */
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_LZO
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
+#endif
+
+/*
+ * EFI partition
+ */
+
+#define CONFIG_KIRKWOOD_GPIO
+
+#endif /* _CONFIG_NAS220_H */
+
diff --git a/include/configs/netgear_cg3100d.h b/include/configs/netgear_cg3100d.h
new file mode 100644
index 0000000..e5a9601
--- /dev/null
+++ b/include/configs/netgear_cg3100d.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm3380.h>
+
+#define CONFIG_ENV_SIZE	SZ_8K
diff --git a/include/configs/netgear_dgnd3700v2.h b/include/configs/netgear_dgnd3700v2.h
new file mode 100644
index 0000000..3baa17a
--- /dev/null
+++ b/include/configs/netgear_dgnd3700v2.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6362.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE	SZ_8K
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
new file mode 100644
index 0000000..23c370b
--- /dev/null
+++ b/include/configs/nitrogen6x.h
@@ -0,0 +1,168 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Boundary Devices Nitrogen6X
+ * and Freescale i.MX6Q Sabre Lite boards.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE	3769
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_USBD_HS
+#define CONFIG_NETCONSOLE
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_I2C_EDID
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#endif
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		6
+
+/* USB Configs */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024)
+#define CONFIG_BMP_16BPP
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+#ifdef CONFIG_CMD_MMC
+#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+#define DISTRO_BOOT_DEV_MMC(func)
+#endif
+
+#ifdef CONFIG_CMD_SATA
+#define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0)
+#else
+#define DISTRO_BOOT_DEV_SATA(func)
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+#define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0)
+#else
+#define DISTRO_BOOT_DEV_USB(func)
+#endif
+
+#ifdef CONFIG_CMD_PXE
+#define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na)
+#else
+#define DISTRO_BOOT_DEV_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define DISTRO_BOOT_DEV_DHCP(func)
+#endif
+
+
+#if defined(CONFIG_SABRELITE)
+#define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0"
+#else
+/* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */
+#define FDTFILE
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	DISTRO_BOOT_DEV_MMC(func) \
+	DISTRO_BOOT_DEV_SATA(func) \
+	DISTRO_BOOT_DEV_USB(func) \
+	DISTRO_BOOT_DEV_PXE(func) \
+	DISTRO_BOOT_DEV_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc1\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_addr_r=0x18000000\0" \
+	FDTFILE \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0"  \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	"ramdiskaddr=0x13000000\0" \
+	"ip_dyn=yes\0" \
+	"usb_pgood_delay=2000\0" \
+	BOOTENV
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END	       0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(8 * 1024)
+#endif
+
+/*
+ * PCI express
+ */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#endif
+
+#endif	       /* __CONFIG_H */
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
new file mode 100644
index 0000000..fd755bb
--- /dev/null
+++ b/include/configs/nokia_rx51.h
@@ -0,0 +1,321 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2010
+ * Alistair Buxton <a.j.buxton@gmail.com>
+ *
+ * Derived from Beagle Board code:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the Nokia RX-51 aka N900.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SYS_L2CACHE_OFF		/* pretend there is no L2 CACHE */
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_NOKIA_RX51
+
+/*
+ * Nokia X-Loader loading secondary image to address 0x80400000
+ * NOLO loading boot image to random place, so it doesn't really
+ * matter what we set this to. We have to copy u-boot to this address
+ */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap.h>
+#include <asm/arch/mem.h>
+#include <linux/stringify.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_SKIP_LOWLEVEL_INIT		/* X-Loader set everything up */
+
+#define CONFIG_CMDLINE_TAG	/* enable passing kernel command line string */
+#define CONFIG_INITRD_TAG			/* enable passing initrd */
+#define CONFIG_REVISION_TAG			/* enable passing revision tag*/
+#define CONFIG_SETUP_MEMORY_TAGS		/* enable memory tag */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_UBI_SIZE			(512 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \
+					(128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		48000000		/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USBD_VENDORID		0x0421
+#define CONFIG_USBD_PRODUCTID		0x01c8
+#define CONFIG_USBD_MANUFACTURER	"Nokia"
+#define CONFIG_USBD_PRODUCT_NAME	"N900"
+
+/* commands to include */
+
+#define CONFIG_SYS_I2C
+
+/*
+ * TWL4030
+ */
+
+#define GPIO_SLIDE			71
+
+/*
+ * Board ONENAND Info.
+ */
+
+#define PART1_NAME			"bootloader"
+#define PART1_SIZE			128
+#define PART1_MULL			1024
+#define PART1_SUFF			"k"
+#define PART1_OFFS			0x00000000
+#define PART1_MASK			0x00000003
+
+#define PART2_NAME			"config"
+#define PART2_SIZE			384
+#define PART2_MULL			1024
+#define PART2_SUFF			"k"
+#define PART2_OFFS			0x00020000
+#define PART2_MASK			0x00000000
+
+#define PART3_NAME			"log"
+#define PART3_SIZE			256
+#define PART3_MULL			1024
+#define PART3_SUFF			"k"
+#define PART3_OFFS			0x00080000
+#define PART3_MASK			0x00000000
+
+#define PART4_NAME			"kernel"
+#define PART4_SIZE			2
+#define PART4_MULL			1024*1024
+#define PART4_SUFF			"m"
+#define PART4_OFFS			0x000c0000
+#define PART4_MASK			0x00000000
+
+#define PART5_NAME			"initfs"
+#define PART5_SIZE			2
+#define PART5_MULL			1024*1024
+#define PART5_SUFF			"m"
+#define PART5_OFFS			0x002c0000
+#define PART5_MASK			0x00000000
+
+#define PART6_NAME			"rootfs"
+#define PART6_SIZE			257280
+#define PART6_MULL			1024
+#define PART6_SUFF			"k"
+#define PART6_OFFS			0x004c0000
+#define PART6_MASK			0x00000000
+
+#ifdef ONENAND_SUPPORT
+
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#endif
+
+/* Watchdog support */
+#define CONFIG_HW_WATCHDOG
+
+/*
+ * Framebuffer
+ */
+/* Video console */
+#define CONFIG_VIDEO_LOGO
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_SPLASH_SCREEN
+
+/* functions for cfb_console */
+#define VIDEO_KBD_INIT_FCT		rx51_kp_init()
+#define VIDEO_TSTC_FCT			rx51_kp_tstc
+#define VIDEO_GETC_FCT			rx51_kp_getc
+#ifndef __ASSEMBLY__
+struct stdio_dev;
+int rx51_kp_init(void);
+int rx51_kp_tstc(struct stdio_dev *sdev);
+int rx51_kp_getc(struct stdio_dev *sdev);
+#endif
+
+/* Environment information */
+#ifdef CONFIG_MTDPARTS_DEFAULT
+#define MTDPARTS "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+#else
+#define MTDPARTS
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MTDPARTS \
+	"usbtty=cdc_acm\0" \
+	"stdin=vga\0" \
+	"stdout=vga\0" \
+	"stderr=vga\0" \
+	"setcon=setenv stdin ${con};" \
+		"setenv stdout ${con};" \
+		"setenv stderr ${con}\0" \
+	"sercon=setenv con serial; run setcon\0" \
+	"usbcon=setenv con usbtty; run setcon\0" \
+	"vgacon=setenv con vga; run setcon\0" \
+	"slide=gpio input " __stringify(GPIO_SLIDE) "\0" \
+	"switchmmc=mmc dev ${mmcnum}\0" \
+	"kernaddr=0x82008000\0" \
+	"initrdaddr=0x84008000\0" \
+	"scriptaddr=0x86008000\0" \
+	"fileload=${mmctype}load mmc ${mmcnum}:${mmcpart} " \
+		"${loadaddr} ${mmcfile}\0" \
+	"kernload=setenv loadaddr ${kernaddr};" \
+		"setenv mmcfile ${mmckernfile};" \
+		"run fileload\0" \
+	"initrdload=setenv loadaddr ${initrdaddr};" \
+		"setenv mmcfile ${mmcinitrdfile};" \
+		"run fileload\0" \
+	"scriptload=setenv loadaddr ${scriptaddr};" \
+		"setenv mmcfile ${mmcscriptfile};" \
+		"run fileload\0" \
+	"scriptboot=echo Running ${mmcscriptfile} from mmc " \
+		"${mmcnum}:${mmcpart} ...; source ${scriptaddr}\0" \
+	"kernboot=echo Booting ${mmckernfile} from mmc " \
+		"${mmcnum}:${mmcpart} ...; bootm ${kernaddr}\0" \
+	"kerninitrdboot=echo Booting ${mmckernfile} ${mmcinitrdfile} from mmc "\
+		"${mmcnum}:${mmcpart} ...; bootm ${kernaddr} ${initrdaddr}\0" \
+	"attachboot=echo Booting attached kernel image ...;" \
+		"setenv setup_omap_atag 1;" \
+		"bootm ${attkernaddr};" \
+		"setenv setup_omap_atag\0" \
+	"trymmcscriptboot=if run switchmmc; then " \
+			"if run scriptload; then " \
+				"run scriptboot;" \
+			"fi;" \
+		"fi\0" \
+	"trymmckernboot=if run switchmmc; then " \
+			"if run kernload; then " \
+				"run kernboot;" \
+			"fi;" \
+		"fi\0" \
+	"trymmckerninitrdboot=if run switchmmc; then " \
+			"if run initrdload; then " \
+				"if run kernload; then " \
+					"run kerninitrdboot;" \
+				"fi;" \
+			"fi; " \
+		"fi\0" \
+	"trymmcpartboot=setenv mmcscriptfile boot.scr; run trymmcscriptboot;" \
+		"setenv mmckernfile uImage; run trymmckernboot\0" \
+	"trymmcallpartboot=setenv mmcpart 1; run trymmcpartboot;" \
+		"setenv mmcpart 2; run trymmcpartboot;" \
+		"setenv mmcpart 3; run trymmcpartboot;" \
+		"setenv mmcpart 4; run trymmcpartboot\0" \
+	"trymmcboot=if run switchmmc; then " \
+			"setenv mmctype fat;" \
+			"run trymmcallpartboot;" \
+			"setenv mmctype ext2;" \
+			"run trymmcallpartboot;" \
+			"setenv mmctype ext4;" \
+			"run trymmcallpartboot;" \
+		"fi\0" \
+	"emmcboot=setenv mmcnum 1; run trymmcboot\0" \
+	"sdboot=setenv mmcnum 0; run trymmcboot\0" \
+	"menucmd=bootmenu\0" \
+	"bootmenu_0=Attached kernel=run attachboot\0" \
+	"bootmenu_1=Internal eMMC=run emmcboot\0" \
+	"bootmenu_2=External SD card=run sdboot\0" \
+	"bootmenu_3=U-Boot boot order=boot\0" \
+	"bootmenu_delay=30\0" \
+	""
+
+#define CONFIG_POSTBOOTMENU \
+	"echo;" \
+	"echo Extra commands:;" \
+	"echo run sercon - Use serial port for control.;" \
+	"echo run usbcon - Use usbtty for control.;" \
+	"echo run vgacon - Use framebuffer/keyboard.;" \
+	"echo run sdboot - Boot from SD card slot.;" \
+	"echo run emmcboot - Boot internal eMMC memory.;" \
+	"echo run attachboot - Boot attached kernel image.;" \
+	"echo"
+
+#define CONFIG_BOOTCOMMAND \
+	"run sdboot;" \
+	"run emmcboot;" \
+	"run attachboot;" \
+	"echo"
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + 0x01F00000)/*31MB*/
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+			CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Attached kernel image
+ */
+
+#define SDRAM_SIZE			0x10000000	/* 256 MB */
+#define SDRAM_END			(CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE)
+
+#define IMAGE_MAXSIZE			0x1FF800	/* 2 MB - 2 kB */
+#define KERNEL_OFFSET			0x40000		/* 256 kB */
+#define KERNEL_MAXSIZE			(IMAGE_MAXSIZE-KERNEL_OFFSET)
+#define KERNEL_ADDRESS			(SDRAM_END-KERNEL_MAXSIZE)
+
+/* Reserve protected RAM for attached kernel */
+#define CONFIG_PRAM			((KERNEL_MAXSIZE >> 10)+1)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/novena.h b/include/configs/novena.h
new file mode 100644
index 0000000..cdc437c
--- /dev/null
+++ b/include/configs/novena.h
@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Novena U-Boot.
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* System configurations */
+#define CONFIG_KEYBOARD
+
+#include "mx6_common.h"
+
+/* U-Boot Commands */
+
+/* U-Boot general configurations */
+
+/* U-Boot environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+/*
+ * Environment is on MMC, starting at offset 512KiB from start of the card.
+ * Please place first partition at offset 1MiB from the start of the card
+ * as recommended by GNU/fdisk. See below for details:
+ * http://homepage.ntlworld.com./jonathan.deboynepollard/FGA/disc-partition-alignment.html
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		(512 * 1024)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#endif
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE			"fitImage"
+#define CONFIG_HOSTNAME			"novena"
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+
+#define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
+
+/* SPL */
+#include "imx6_spl.h"			/* common IMX6 SPL configuration */
+
+/* Ethernet Configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0x7
+#define CONFIG_ARP_TIMEOUT		200UL
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_SPD_BUS_NUM		0
+
+/* I2C EEPROM */
+#ifdef CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_EEPROM_BUS	2
+#endif
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* PCI express */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(3, 29)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(7, 12)
+#endif
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+/* SATA Configs */
+#define CONFIG_LBA48
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+/* Gadget part */
+#define CONFIG_USBD_HS
+#define CONFIG_NETCONSOLE
+#endif
+
+/* Video output */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+/* Extra U-Boot environment. */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"fdt_high=0xffffffff\0"						\
+	"initrd_high=0xffffffff\0"					\
+	"consdev=ttymxc1\0"						\
+	"baudrate=115200\0"						\
+	"bootdev=/dev/mmcblk0p1\0"					\
+	"rootdev=/dev/mmcblk0p2\0"					\
+	"netdev=eth0\0"							\
+	"kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0"		\
+	"pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0"		\
+	"scriptaddr="__stringify(CONFIG_LOADADDR)"\0"			\
+	"ramdisk_addr_r=0x28000000\0"		   			\
+	"fdt_addr_r=0x18000000\0"					\
+	"fdtfile=imx6q-novena.dtb\0"					\
+	"stdout=serial,vidconsole\0"					\
+	"stderr=serial,vidconsole\0"					\
+	"addcons="							\
+		"setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"addip="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+			"${netmask}:${hostname}:${netdev}:off\0"	\
+	"addmisc="							\
+		"setenv bootargs ${bootargs} ${miscargs}\0"		\
+	"addargs=run addcons addmisc\0"					\
+	"mmcload="							\
+		"mmc rescan ; "						\
+		"ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0"	\
+	"netload="							\
+		"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0"	\
+	"miscargs=nohlt panic=1\0"					\
+	"mmcargs=setenv bootargs root=${rootdev} rw rootwait\0"		\
+	"nfsargs="							\
+		"setenv bootargs root=/dev/nfs rw "			\
+			"nfsroot=${serverip}:${rootpath},v3,tcp\0"	\
+	"mmc_mmc="							\
+		"run mmcload mmcargs addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"mmc_nfs="							\
+		"run mmcload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_mmc="							\
+		"run netload mmcargs addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_nfs="							\
+		"run netload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"update_sd_spl_filename=SPL\0"					\
+	"update_sd_uboot_filename=u-boot.img\0"				\
+	"update_sd_firmware="	/* Update the SD firmware partition */	\
+		"if mmc rescan ; then "					\
+		"if dhcp ${update_sd_spl_filename} ; then "		\
+		"mmc write ${loadaddr} 2 0x200 ; "			\
+		"fi ; "							\
+		"if dhcp ${update_sd_uboot_filename} ; then "		\
+		"fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\
+		"fi ; "							\
+		"fi\0"							\
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(SATA, sata, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS
+#endif /* CONFIG_SPL_BUILD */
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h
new file mode 100644
index 0000000..eb465e0
--- /dev/null
+++ b/include/configs/nsa310s.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015
+ * Gerald Kerma <dreagle@doukki.net>
+ * Tony Dinh <mibodhi@gmail.com>
+ * Luka Perkov <luka.perkov@sartura.hr>
+ */
+
+#ifndef _CONFIG_NSA310S_H
+#define _CONFIG_NSA310S_H
+
+/* high level configuration options */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KW88F6192		1	/* SOC Name */
+#define CONFIG_KW88F6702		1	/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/* compression configuration */
+#define CONFIG_BZIP2
+
+/* commands configuration */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* environment variables configuration */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_OFFSET	0xe0000
+
+/* default environment variables */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+	"ubi part root; " \
+	"ubifsmount ubi:rootfs; " \
+	"ubifsload 0x800000 ${kernel}; " \
+	"ubifsload 0x700000 ${fdt}; " \
+	"ubifsumount; " \
+	"fdt addr 0x700000; fdt resize; fdt chosen; " \
+	"bootz 0x800000 - 0x700000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=console=ttyS0,115200\0" \
+	"mtdids=nand0=orion_nand\0" \
+	"mtdparts="CONFIG_MTDPARTS_DEFAULT \
+	"kernel=/boot/zImage\0" \
+	"fdt=/boot/nsa310s.dtb\0" \
+	"bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0"
+
+/* Ethernet driver configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	1
+#define CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/* SATA driver configuration */
+#ifdef CONFIG_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif /* CONFIG_IDE */
+
+/* RTC driver configuration */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_NSA310S_H */
diff --git a/include/configs/nsim.h b/include/configs/nsim.h
new file mode 100644
index 0000000..61217bb
--- /dev/null
+++ b/include/configs/nsim.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved.
+ */
+
+#ifndef _CONFIG_NSIM_H_
+#define _CONFIG_NSIM_H_
+
+#include <linux/sizes.h>
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		SZ_256M
+
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_2M
+#define CONFIG_SYS_BOOTM_LEN		SZ_32M
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+
+#endif /* _CONFIG_NSIM_H_ */
diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h
new file mode 100644
index 0000000..fca4eb5
--- /dev/null
+++ b/include/configs/nyan-big.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"Google/NVIDIA Nyan-big"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
+
+/* SPI */
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+#undef CONFIG_LOADADDR
+#define CONFIG_LOADADDR		0x82408000
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
new file mode 100644
index 0000000..9f2d43e
--- /dev/null
+++ b/include/configs/odroid.h
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Sanghee Kim <sh0130.kim@samsung.com>
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * Configuation settings for the Odroid-U3 (EXYNOS4412) board.
+ */
+
+#ifndef __CONFIG_ODROID_U3_H
+#define __CONFIG_ODROID_U3_H
+
+#include <configs/exynos4-common.h>
+
+#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	0x10502000
+#endif
+
+#define CONFIG_MACH_TYPE	4289
+
+#define CONFIG_SYS_SDRAM_BASE	0x40000000
+#define SDRAM_BANK_SIZE		(256 << 20)	/* 256 MB */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+/* Reserve the last 1 MiB for the secure firmware */
+#define CONFIG_SYS_MEM_TOP_HIDE		(1UL << 20UL)
+#define CONFIG_TZSW_RESERVED_DRAM_SIZE	CONFIG_SYS_MEM_TOP_HIDE
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#include <linux/sizes.h>
+
+/* select serial console configuration */
+
+/* Console configuration */
+
+#define CONFIG_BOOTCOMMAND		"run distro_bootcmd ; run autoboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			SZ_16K
+#define CONFIG_ENV_OFFSET		(SZ_1K * 1280) /* 1.25 MiB offset */
+#define CONFIG_ENV_OVERWRITE
+
+/* Partitions name */
+#define PARTS_BOOT		"boot"
+#define PARTS_ROOT		"platform"
+
+#define CONFIG_DFU_ALT \
+	"uImage fat 0 1;" \
+	"zImage fat 0 1;" \
+	"Image.itb fat 0 1;" \
+	"uInitrd fat 0 1;" \
+	"exynos4412-odroidu3.dtb fat 0 1;" \
+	"exynos4412-odroidx2.dtb fat 0 1;" \
+	""PARTS_BOOT" part 0 1;" \
+	""PARTS_ROOT" part 0 2\0" \
+
+#define CONFIG_SET_DFU_ALT_INFO
+#define CONFIG_SET_DFU_ALT_BUF_LEN	(SZ_1K)
+
+#define CONFIG_DFU_ALT_BOOT_EMMC \
+	"u-boot raw 0x3e 0x800 mmcpart 1;" \
+	"bl1 raw 0x0 0x1e mmcpart 1;" \
+	"bl2 raw 0x1e 0x1d mmcpart 1;" \
+	"tzsw raw 0x83e 0x138 mmcpart 1\0"
+
+#define CONFIG_DFU_ALT_BOOT_SD \
+	"u-boot raw 0x3f 0x800;" \
+	"bl1 raw 0x1 0x1e;" \
+	"bl2 raw 0x1f 0x1d;" \
+	"tzsw raw 0x83f 0x138\0"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+
+/*
+ * Bootable media layout:
+ * dev:    SD   eMMC(part boot)
+ * BL1      1    0
+ * BL2     31   30
+ * UBOOT   63   62
+ * TZSW  2111 2110
+ * ENV   2560 2560(part user)
+ *
+ * MBR Primary partiions:
+ * Num Name   Size  Offset
+ * 1.  BOOT:  100MiB 2MiB
+ * 2.  ROOT:  -
+*/
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadbootscript=load mmc ${mmcbootdev}:${mmcbootpart} ${scriptaddr} " \
+		"boot.scr\0" \
+	"loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kernel_addr_r} " \
+		"${kernelname}\0" \
+	"loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${ramdisk_addr_r} " \
+		"${initrdname}\0" \
+	"loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdt_addr_r} " \
+		"${fdtfile}\0" \
+	"check_ramdisk=" \
+		"if run loadinitrd; then " \
+			"setenv initrd_addr ${ramdisk_addr_r};" \
+		"else " \
+			"setenv initrd_addr -;" \
+		"fi;\0" \
+	"check_dtb=" \
+		"if run loaddtb; then " \
+			"setenv fdt_addr ${fdt_addr_r};" \
+		"else " \
+			"setenv fdt_addr;" \
+		"fi;\0" \
+	"kernel_args=" \
+		"setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \
+		" rootwait ${console} ${opts}\0" \
+	"boot_script=" \
+		"run loadbootscript;" \
+		"source ${scriptaddr}\0" \
+	"boot_fit=" \
+		"setenv kernelname Image.itb;" \
+		"run loadkernel;" \
+		"run kernel_args;" \
+		"bootm ${kernel_addr_r}#${board_name}\0" \
+	"boot_uimg=" \
+		"setenv kernelname uImage;" \
+		"run check_dtb;" \
+		"run check_ramdisk;" \
+		"run loadkernel;" \
+		"run kernel_args;" \
+		"bootm ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \
+	"boot_zimg=" \
+		"setenv kernelname zImage;" \
+		"run check_dtb;" \
+		"run check_ramdisk;" \
+		"run loadkernel;" \
+		"run kernel_args;" \
+		"bootz ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \
+	"autoboot=" \
+		"if test -e mmc 0 boot.scr; then; " \
+			"run boot_script; " \
+		"elif test -e mmc 0 Image.itb; then; " \
+			"run boot_fit;" \
+		"elif test -e mmc 0 zImage; then; " \
+			"run boot_zimg;" \
+		"elif test -e mmc 0 uImage; then; " \
+			"run boot_uimg;" \
+		"fi;\0" \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+	"mmcbootdev=0\0" \
+	"mmcbootpart=1\0" \
+	"mmcrootdev=0\0" \
+	"mmcrootpart=2\0" \
+	"dfu_alt_system="CONFIG_DFU_ALT \
+	"dfu_alt_info=Please reset the board\0" \
+	"consoleon=set console console=ttySAC1,115200n8; save; reset\0" \
+	"consoleoff=set console console=ram; save; reset\0" \
+	"initrdname=uInitrd\0" \
+	"ramdisk_addr_r=0x42000000\0" \
+	"scriptaddr=0x42000000\0" \
+	"fdt_addr_r=0x40800000\0" \
+	"kernel_addr_r=0x41000000\0" \
+	BOOTENV
+
+/* GPT */
+
+/* Security subsystem - enable hw_rand() */
+#define CONFIG_EXYNOS_ACE_SHA
+
+/* USB */
+#define CONFIG_USB_EHCI_EXYNOS
+
+/*
+ * Supported Odroid boards: X3, U3
+ * TODO: Add Odroid X support
+ */
+#define CONFIG_MISC_COMMON
+
+#undef CONFIG_REVISION_TAG
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
new file mode 100644
index 0000000..af6004e
--- /dev/null
+++ b/include/configs/odroid_xu3.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Hyungwon Hwang <human.hwang@samsung.com>
+ */
+
+#ifndef __CONFIG_ODROID_XU3_H
+#define __CONFIG_ODROID_XU3_H
+
+#include <configs/exynos5420-common.h>
+#include <configs/exynos5-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+/* select serial console configuration */
+
+#define TZPC_BASE_OFFSET		0x10000
+
+#define SDRAM_BANK_SIZE			(256UL << 20UL)	/* 256 MB */
+/* Reserve the last 22 MiB for the secure firmware */
+#define CONFIG_SYS_MEM_TOP_HIDE		(22UL << 20UL)
+#define CONFIG_TZSW_RESERVED_DRAM_SIZE	CONFIG_SYS_MEM_TOP_HIDE
+
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_ENV_OFFSET
+#define CONFIG_ENV_SIZE			(SZ_1K * 16)
+#define CONFIG_ENV_OFFSET		(SZ_1K * 3136) /* ~3 MiB offset */
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
+
+/* USB */
+#define CONFIG_USB_EHCI_EXYNOS
+
+/* DFU */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_32M
+#define DFU_DEFAULT_POLL_TIMEOUT	300
+#define DFU_MANIFEST_POLL_TIMEOUT	25000
+
+/* THOR */
+#define CONFIG_G_DNL_THOR_VENDOR_NUM	CONFIG_USB_GADGET_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM	0x685D
+
+/* UMS */
+#define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
+#define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
+
+/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */
+#undef CONFIG_EXYNOS_TMU
+
+#define CONFIG_DFU_ALT_SYSTEM               \
+	"uImage fat 0 1;"                   \
+	"zImage fat 0 1;"                   \
+	"Image.itb fat 0 1;"                \
+	"uInitrd fat 0 1;"                  \
+	"boot.scr fat 0 1;"                 \
+	"boot.cmd fat 0 1;"                 \
+	"exynos5422-odroidxu3.dtb fat 0 1;" \
+	"exynos5422-odroidxu3-lite.dtb fat 0 1;" \
+	"exynos5422-odroidxu4.dtb fat 0 1;" \
+	"exynos5422-odroidhc1.dtb fat 0 1;" \
+	"boot part 0 1;"                    \
+	"root part 0 2\0"
+
+#define CONFIG_DFU_ALT_BOOT_EMMC           \
+	"u-boot raw 0x3e 0x800 mmcpart 1;" \
+	"bl1 raw 0x0 0x1e mmcpart 1;"      \
+	"bl2 raw 0x1e 0x1d mmcpart 1;"     \
+	"tzsw raw 0x83e 0x200 mmcpart 1;"  \
+	"params.bin raw 0x1880 0x20\0"
+
+#define CONFIG_DFU_ALT_BOOT_SD   \
+	"u-boot raw 0x3f 0x800;" \
+	"bl1 raw 0x1 0x1e;"      \
+	"bl2 raw 0x1f 0x1d;"     \
+	"tzsw raw 0x83f 0x200;"  \
+	"params.bin raw 0x1880 0x20\0"
+
+/* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */
+#define CONFIG_MISC_COMMON
+#define CONFIG_SET_DFU_ALT_INFO
+#define CONFIG_SET_DFU_ALT_BUF_LEN	(SZ_1K)
+
+/* Set soc_rev, soc_id, board_rev, board_name, fdtfile */
+#define CONFIG_ODROID_REV_AIN		9
+#define CONFIG_REVISION_TAG
+
+/*
+ * Need to override existing one (smdk5420) with odroid so set_board_info will
+ * use proper prefix when creating full board_name (SYS_BOARD + type)
+ */
+#undef CONFIG_SYS_BOARD
+#define CONFIG_SYS_BOARD		"odroid"
+
+/* Define new extra env settings, including DFU settings */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS \
+	EXYNOS_FDTFILE_SETTING \
+	MEM_LAYOUT_ENV_SETTINGS \
+	BOOTENV \
+	"rootfstype=ext4\0" \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+	"fdtfile=exynos5422-odroidxu3.dtb\0" \
+	"board_name=odroidxu3\0" \
+	"mmcbootdev=0\0" \
+	"mmcrootdev=0\0" \
+	"mmcbootpart=1\0" \
+	"mmcrootpart=2\0" \
+	"dfu_alt_system="CONFIG_DFU_ALT_SYSTEM \
+	"dfu_alt_info=Autoset by THOR/DFU command run.\0"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
new file mode 100644
index 0000000..e8c6083
--- /dev/null
+++ b/include/configs/omap3_beagle.h
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/ti_omap3_common.h>
+
+/*
+ * We are only ever GP parts and will utilize all of the "downloaded image"
+ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
+ */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* NAND */
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE      1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT      64
+#define CONFIG_SYS_NAND_PAGE_SIZE       2048
+#define CONFIG_SYS_NAND_OOBSIZE         64
+#define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
+                                         10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE         512
+#define CONFIG_SYS_NAND_ECCBYTES        3
+#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
+#define CONFIG_SYS_ENV_SECT_SIZE        SZ_128K
+#define CONFIG_ENV_ADDR                 0x260000
+#define CONFIG_ENV_OVERWRITE
+/* NAND: SPL falcon mode configs */
+#if defined(CONFIG_SPL_OS_BOOT)
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
+#endif /* CONFIG_SPL_OS_BOOT */
+#endif /* CONFIG_NAND */
+
+/* USB EHCI */
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	147
+
+/* Enable Multi Bus support for I2C */
+#define CONFIG_I2C_MULTI_BUS
+
+/* DSS Support */
+
+/* TWL4030 LED Support */
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV
+
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"setenv mmcdev " #instance "; " \
+	"run mmcboot\0"
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#if defined(CONFIG_NAND)
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \
+		"echo NAND boot disabled: No mtdids and/or mtdparts; " \
+	"else " \
+		"run nandboot; " \
+	"fi\0"
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(LEGACY_MMC, legacy_mmc, 0) \
+	func(UBIFS, ubifs, 0) \
+	func(NAND, nand, 0)
+
+#else /* !CONFIG_NAND */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(LEGACY_MMC, legacy_mmc, 0)
+
+#endif /* CONFIG_NAND */
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MEM_LAYOUT_ENV_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_high=0xffffffff\0" \
+	"console=ttyO2,115200n8\0" \
+	"bootdir=/boot\0" \
+	"bootenv=uEnv.txt\0" \
+	"bootfile=zImage\0" \
+	"bootpart=0:2\0" \
+	"bootubivol=rootfs\0" \
+	"bootubipart=rootfs\0" \
+	"usbtty=cdc_acm\0" \
+	"mpurate=auto\0" \
+	"buddy=none\0" \
+	"camera=none\0" \
+	"vram=12M\0" \
+	"dvimode=640x480MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"defaultargs=setenv defargs " \
+		"mpurate=${mpurate} " \
+		"buddy=${buddy} "\
+		"camera=${camera} "\
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay}\0" \
+	"optargs=\0" \
+	"findfdt=" \
+		"if test $beaglerev = AxBx; then " \
+			"setenv fdtfile omap3-beagle.dtb; fi; " \
+		"if test $beaglerev = Cx; then " \
+			"setenv fdtfile omap3-beagle.dtb; fi; " \
+		"if test $beaglerev = C4; then " \
+			"setenv fdtfile omap3-beagle.dtb; fi; " \
+		"if test $beaglerev = xMAB; then " \
+			"setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \
+		"if test $beaglerev = xMC; then " \
+			"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"mmcargs=run defaultargs; setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"${defargs} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"userbutton_xm=gpio input 4;\0" \
+	"userbutton_nonxm=gpio input 7;\0" \
+	"userbutton=if gpio input 173; then " \
+			"run userbutton_xm; " \
+		"else " \
+			"run userbutton_nonxm; " \
+		"fi;\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \
+		"mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"if run userbutton; then " \
+				"setenv bootenv uEnv.txt;" \
+			"else " \
+				"setenv bootenv user.txt;" \
+			"fi;" \
+			"run loadbootenv && run importbootenv; " \
+			"run ext4bootenv && run importbootenv; " \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...; " \
+				"run uenvcmd; " \
+			"fi; " \
+		"fi\0" \
+	"validatefdt=" \
+		"if test $beaglerev = xMAB; then " \
+			"if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \
+				"setenv fdtfile omap3-beagle-xm.dtb; " \
+			"fi; " \
+		"fi; \0" \
+	"loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loaddtb=run validatefdt; ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcboot=run mmcbootenv; " \
+		"if run loadimage && run loaddtb; then " \
+			"echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \
+			"run mmcargs; " \
+			"if test ${bootfile} = uImage; then " \
+				"bootm ${loadaddr} - ${fdtaddr}; " \
+			"fi; " \
+			"if test ${bootfile} = zImage; then " \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"fi; " \
+		"fi\0" \
+	"nandroot=ubi0:rootfs ubi.mtd=rootfs rw\0" \
+	"nandrootfstype=ubifs rootwait\0" \
+	"nandargs=run defaultargs; setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"${defargs} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandboot=if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \
+			"echo Booting uImage from NAND MTD 'kernel' partition ...; " \
+			"run nandargs; " \
+			"bootm ${loadaddr} - ${fdtaddr}; " \
+		"fi\0" \
+	"loadramdisk=ext4load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
+	"ramdisk=rootfs.ext2.gz.uboot\0" \
+	"ramdisk_size=16384\0" \
+	"ramroot=/dev/ram rw\0" \
+	"ramrootfstype=ext2\0" \
+	"ramargs=run defaultargs; setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"${defargs} " \
+		"${optargs} " \
+		"root=${ramroot} ramdisk_size=${ramdisk_size} " \
+	 	"rootfstype=${ramrootfstype}\0" \
+	"ramboot=run mmcbootenv; " \
+		"if run loadimage && run loaddtb && run loadramdisk; then " \
+			"echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} w/ramdisk ...; " \
+			"run ramargs; " \
+			"bootz ${loadaddr} ${rdaddr} ${fdtaddr}; " \
+		"fi\0" \
+	BOOTENV
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
new file mode 100644
index 0000000..9e2b752
--- /dev/null
+++ b/include/configs/omap3_cairo.h
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the QUIPOS Cairo board.
+ *
+ * Copyright (C) DENX GmbH
+ *
+ * Author :
+ *	Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Derived from EVM  code by
+ *	Manikandan Pillai <mani.pillai@ti.com>
+ * Itself derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Also derived from include/configs/omap3_beagle.h
+ */
+
+#ifndef __OMAP3_CAIRO_CONFIG_H
+#define __OMAP3_CAIRO_CONFIG_H
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.  We use this rather than the inherited defines from
+ * ti_armv7_common.h for backwards compatibility.
+ */
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		(512 << 10)	/* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#include <configs/ti_omap3_common.h>
+
+#define CONFIG_REVISION_TAG		1
+#define CONFIG_ENV_OVERWRITE
+
+/* Enable Multi Bus support for I2C */
+#define CONFIG_I2C_MULTI_BUS		1
+
+/* Probe all devices */
+#define CONFIG_SYS_I2C_NOPROBES		{ {0x0, 0x0} }
+
+/*
+ * TWL4030
+ */
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"machid=ffffffff\0" \
+	"fdt_high=0x87000000\0" \
+	"baudrate=115200\0" \
+	"fec_addr=00:50:C2:7E:90:F0\0" \
+	"netmask=255.255.255.0\0" \
+	"ipaddr=192.168.2.9\0" \
+	"gateway=192.168.2.1\0" \
+	"serverip=192.168.2.10\0" \
+	"nfshost=192.168.2.10\0" \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0" \
+	"bootargs_mmc_ramdisk=mem=128M " \
+		"console=ttyO1,115200n8 " \
+		"root=/dev/ram0 rw " \
+		"initrd=0x81600000,16M " \
+		"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
+		"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
+	"mmcboot=mmc init; " \
+		"fatload mmc 0 0x80000000 uImage; " \
+		"fatload mmc 0 0x81600000 ramdisk.gz; " \
+		"setenv bootargs ${bootargs_mmc_ramdisk}; " \
+		"bootm 0x80000000\0" \
+	"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
+	"root=/dev/nfs " \
+	"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
+	"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
+	"omap_vout.vid1_static_vrfb_alloc=y\0" \
+	"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
+	"bootm 0x80000000\0" \
+	"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
+	"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
+	"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
+	"omapfb.rotate_type=1\0" \
+	"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
+	"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
+	"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+	"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
+	"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
+	"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
+	"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+	"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
+	"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
+	"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
+	"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
+	"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
+		"nand erase 0 20000; " \
+		"fatload mmc 0 0x81600000 MLO; " \
+		"nandecc hw; " \
+		"nand write.i 0x81600000 0 20000;\0" \
+	"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
+		"nand erase 80000 40000; " \
+		"fatload mmc 0 0x81600000 u-boot.bin; " \
+		"nandecc sw; " \
+		"nand write.i 0x81600000 80000 40000;\0" \
+	"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
+		"nand erase 280000 300000; " \
+		"fatload mmc 0 0x81600000 uImage; " \
+		"nandecc sw; " \
+		"nand write.i 0x81600000 280000 300000;\0" \
+	"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
+		"nandecc sw; " \
+		"nand write.jffs2 0x680000 0xFF ${filesize}; " \
+		"nand erase 680000 ${filesize}; " \
+		"nand write.jffs2 81600000 680000 ${filesize};\0" \
+	"flash_scrub=nand scrub; " \
+		"run flash_xloader; " \
+		"run flash_uboot; " \
+		"run flash_kernel; " \
+		"run flash_rootfs;\0" \
+	"flash_all=run ledred; " \
+		"nand erase.chip; " \
+		"run ledorange; " \
+		"run flash_xloader; " \
+		"run flash_uboot; " \
+		"run flash_kernel; " \
+		"run flash_rootfs; " \
+		"run ledgreen; " \
+		"run boot_nand; \0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
+	"else run boot_nand; fi"
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_ADDR			0x260000
+
+/* Defines for SPL */
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#endif
+
+/* env defaults */
+#define CONFIG_BOOTFILE			"uImage"
+
+/* Provide the MACH_TYPE value the vendor kernel requires */
+#define CONFIG_MACH_TYPE	3063
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#endif /* __OMAP3_CAIRO_CONFIG_H */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
new file mode 100644
index 0000000..8e98977
--- /dev/null
+++ b/include/configs/omap3_evm.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the TI OMAP3 EVM board.
+ *
+ * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ *	Manikandan Pillai <mani.pillai@ti.com>
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Manikandan Pillai <mani.pillai@ti.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/ti_omap3_common.h>
+
+/*
+ * We are only ever GP parts and will utilize all of the "downloaded image"
+ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
+ */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* NAND */
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE      1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT      64
+#define CONFIG_SYS_NAND_PAGE_SIZE       2048
+#define CONFIG_SYS_NAND_OOBSIZE         64
+#define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
+                                         10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE         512
+#define CONFIG_SYS_NAND_ECCBYTES        3
+#define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_SYS_ENV_SECT_SIZE        SZ_128K
+#define CONFIG_ENV_ADDR                 0x260000
+#define CONFIG_ENV_OVERWRITE
+/* NAND: SPL falcon mode configs */
+#if defined(CONFIG_SPL_OS_BOOT)
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
+#endif /* CONFIG_SPL_OS_BOOT */
+#endif /* CONFIG_NAND */
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV
+
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"setenv mmcdev " #instance "; " \
+	"run mmcboot\0"
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#if defined(CONFIG_NAND)
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \
+		"echo NAND boot disabled: No mtdids and/or mtdparts; " \
+	"else " \
+		"run nandboot; " \
+	"fi\0"
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(LEGACY_MMC, legacy_mmc, 0) \
+	func(UBIFS, ubifs, 0) \
+	func(NAND, nand, 0)
+
+#else /* !CONFIG_NAND */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(LEGACY_MMC, legacy_mmc, 0)
+
+#endif /* CONFIG_NAND */
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MEM_LAYOUT_ENV_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"fdt_high=0xffffffff\0" \
+	"console=ttyO0,115200n8\0" \
+	"bootdir=/boot\0" \
+	"bootenv=uEnv.txt\0" \
+	"bootfile=zImage\0" \
+	"bootpart=0:2\0" \
+	"bootubivol=rootfs\0" \
+	"bootubipart=rootfs\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \
+		"mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"run loadbootenv && run importbootenv; " \
+			"run ext4bootenv && run importbootenv; " \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...; " \
+				"run uenvcmd; " \
+			"fi; " \
+		"fi\0" \
+	"loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loaddtb=ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcboot=run mmcbootenv; " \
+		"if run loadimage && run loaddtb; then " \
+			"echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \
+			"run mmcargs; " \
+			"if test ${bootfile} = uImage; then " \
+				"bootm ${loadaddr} - ${fdtaddr}; " \
+			"fi; " \
+			"if test ${bootfile} = zImage; then " \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"fi; " \
+		"fi\0" \
+	"nandroot=ubi0:rootfs ubi.mtd=rootfs rw noinitrd\0" \
+	"nandrootfstype=ubifs rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandboot=if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \
+			"echo Booting uImage from NAND MTD 'kernel' partition ...; " \
+			"run nandargs; " \
+			"bootm ${loadaddr} - ${fdtaddr}; " \
+		"fi\0" \
+	BOOTENV
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
new file mode 100644
index 0000000..4ad7dc1
--- /dev/null
+++ b/include/configs/omap3_igep00x0.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common configuration settings for IGEP technology based boards
+ *
+ * (C) Copyright 2012
+ * ISEE 2007 SL, <www.iseebcn.com>
+ */
+
+#ifndef __IGEP00X0_H
+#define __IGEP00X0_H
+
+#include <configs/ti_omap3_common.h>
+
+/*
+ * We are only ever GP parts and will utilize all of the "downloaded image"
+ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
+ */
+
+#define CONFIG_REVISION_TAG		1
+
+/* TPS65950 */
+#define PBIASLITEVMODE1			(1 << 8)
+
+/* LED */
+#define IGEP0020_GPIO_LED		27
+#define IGEP0030_GPIO_LED		16
+
+/* Board and revision detection GPIOs */
+#define IGEP0030_USB_TRANSCEIVER_RESET		54
+#define GPIO_IGEP00X0_BOARD_DETECTION		28
+#define GPIO_IGEP00X0_REVISION_DETECTION	129
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Environment */
+#define ENV_DEVICE_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+
+#define MEM_LAYOUT_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"scriptaddr=0x87E00000\0" \
+	"pxefile_addr_r=0x87F00000\0"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+
+#define ENV_FINDFDT \
+	"findfdt="\
+		"if test ${board_name} = igep0020; then " \
+			"if test ${board_rev} = F; then " \
+				"setenv fdtfile omap3-igep0020-rev-f.dtb; " \
+			"else " \
+				"setenv fdtfile omap3-igep0020.dtb; fi; fi; " \
+		"if test ${board_name} = igep0030; then " \
+			"if test ${board_rev} = G; then " \
+				"setenv fdtfile omap3-igep0030-rev-g.dtb; " \
+			"else " \
+				"setenv fdtfile omap3-igep0030.dtb; fi; fi; " \
+		"if test ${fdtfile} = ''; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_FINDFDT \
+	ENV_DEVICE_SETTINGS \
+	MEM_LAYOUT_SETTINGS \
+	BOOTENV
+
+#endif
+
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+
+/* OneNAND config */
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+#define CONFIG_SYS_ONENAND_BLOCK_SIZE	(128*1024)
+
+/* NAND config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2,  3,  4,  5,  6,  7,  8,  9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+
+#endif /* __IGEP00X0_H */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
new file mode 100644
index 0000000..90292ae
--- /dev/null
+++ b/include/configs/omap3_logic.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
+ *	Peter Barada <peter.barada@logicpd.com>
+ *
+ * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
+ * reference boards.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+
+#include <configs/ti_omap3_common.h>
+
+/*
+ * We are only ever GP parts and will utilize all of the "downloaded image"
+ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in
+ * order to allow for BCH8 to fit in.
+ */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Hardware drivers */
+
+/* I2C */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM AT24C64      */
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_USB_EHCI_OMAP
+#endif
+#ifdef CONFIG_USB_EHCI_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	4
+#endif
+
+/* Board NAND Info. */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	  /* Max number of */
+						  /* NAND devices */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
+					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
+					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
+					 52, 53, 54, 55, 56}
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	13
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+#endif
+
+/* Environment information */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"	\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"mmcdev=0\0" \
+	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \
+	"nandrootfstype=ubifs rootwait\0" \
+	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
+			"if run loadbootscript; then " \
+				"run bootscript; " \
+			"else " \
+				"run defaultboot;" \
+			"fi; " \
+		"else run defaultboot; fi\0" \
+	"defaultboot=run mmcramboot\0" \
+	"consoledevice=ttyS0\0" \
+	"setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
+	"dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
+	"rotation=0\0" \
+	"vrfb_arg=if itest ${rotation} -ne 0; then " \
+		"setenv bootargs ${bootargs} omapfb.vrfb=y " \
+		"omapfb.rotate=${rotation}; " \
+		"fi\0" \
+	"optargs=ignore_loglevel early_printk no_console_suspend\0" \
+	"common_bootargs=run setconsole; setenv bootargs " \
+		"${bootargs} "\
+		"console=${console} " \
+		"${mtdparts} "\
+		"${optargs}; " \
+		"run vrfb_arg\0" \
+	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo 'Running bootscript from mmc ...'; " \
+		"source ${loadaddr}\0" \
+	"loadimage=mmc rescan; " \
+		"load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"ramdisksize=64000\0" \
+	"ramdiskimage=rootfs.ext2.gz.uboot\0" \
+	"loadramdisk=mmc rescan; " \
+		"load mmc ${mmcdev} ${rdaddr} ${ramdiskimage}\0" \
+	"ramargs=setenv bootargs "\
+		"root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
+	"mmcargs=setenv bootargs "\
+		"root=PARTUUID=${uuid} " \
+		"rootfstype=${mmcrootfstype} rw\0" \
+	"nandargs=setenv bootargs "\
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nfsargs=setenv serverip ${tftpserver}; " \
+		"setenv bootargs root=/dev/nfs " \
+		"nfsroot=${nfsrootpath} " \
+		"ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \
+	"nfsrootpath=/opt/nfs-exports/omap\0" \
+	"autoload=no\0" \
+	"fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+	"loadfdt=mmc rescan; " \
+		"load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
+	"mmcbootcommon=echo Booting with DT from mmc${mmcdev} ...; " \
+		"run finduuid; "\
+		"run mmcargs; " \
+		"run common_bootargs; " \
+		"run dump_bootargs; " \
+		"run loadimage; " \
+		"run loadfdt;\0 " \
+	"mmcbootz=setenv bootfile zImage; " \
+		"run mmcbootcommon; "\
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"mmcboot=setenv bootfile uImage; "\
+		"run mmcbootcommon; "\
+		"bootm ${loadaddr} - ${fdtaddr}\0" \
+	"mmcrambootcommon=echo 'Booting kernel from MMC w/ramdisk...'; " \
+		"run ramargs; " \
+		"run common_bootargs; " \
+		"run dump_bootargs; " \
+		"run loadimage; " \
+		"run loadfdt; " \
+		"run loadramdisk\0" \
+	"mmcramboot=setenv bootfile uImage; " \
+		"run mmcrambootcommon; " \
+		"bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+	"mmcrambootz=setenv bootfile zImage; " \
+		"run mmcrambootcommon; " \
+		"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+	"tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
+		"run ramargs; " \
+		"run common_bootargs; " \
+		"run dump_bootargs; " \
+		"tftpboot ${loadaddr} ${zimage}; " \
+		"tftpboot ${rdaddr} ${ramdiskimage}; " \
+		"bootm ${loadaddr} ${rdaddr}\0" \
+	"tftpbootz=echo 'Booting kernel NFS rootfs...'; " \
+		"dhcp;" \
+		"run nfsargs;" \
+		"run common_bootargs;" \
+		"run dump_bootargs;" \
+		"tftpboot $loadaddr zImage;" \
+		"bootz $loadaddr\0" \
+	"nandbootcommon=echo 'Booting kernel from NAND...';" \
+		"run nandargs;" \
+		"run common_bootargs;" \
+		"run dump_bootargs;" \
+		"nand read ${loadaddr} kernel;" \
+		"nand read ${fdtaddr} spl-os;\0" \
+	"nandbootz=run nandbootcommon; "\
+		"bootz ${loadaddr} - ${fdtaddr}\0"\
+	"nandboot=run nandbootcommon; "\
+		"bootm ${loadaddr} - ${fdtaddr}\0"\
+
+#define CONFIG_BOOTCOMMAND \
+	"run autoboot"
+
+/* Miscellaneous configurable options */
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+/* FLASH and environment organization */
+
+/* **** PISMO SUPPORT *** */
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#endif
+
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE		0x4000000
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_ADDR			0x260000
+
+/* Defines for SPL */
+
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
new file mode 100644
index 0000000..38a10e2
--- /dev/null
+++ b/include/configs/omap3_overo.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Gumstix Overo board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/ti_omap3_common.h>
+/*
+ * We are only ever GP parts and will utilize all of the "downloaded image"
+ * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
+ */
+
+/* call misc_init_r */
+
+/* pass the revision tag */
+#define CONFIG_REVISION_TAG
+
+/* override size of malloc() pool */
+#undef CONFIG_SYS_MALLOC_LEN
+/* Shift 128 << 15 provides 4 MiB heap to support UBI commands.
+ * Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 15))
+
+/* I2C Support */
+
+/* TWL4030 LED */
+
+/* USB EHCI */
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	183
+
+/* commands to include */
+
+#ifdef CONFIG_NAND
+/* NAND block size is 128 KiB.  Synchronize these values with
+ * overo_nand_partitions in mach-omap2/board-overo.c in Linux:
+ *  xloader              4 * NAND_BLOCK_SIZE = 512 KiB
+ *  uboot               14 * NAND_BLOCK_SIZE = 1792 KiB
+ *  uboot environtment   2 * NAND_BLOCK_SIZE = 256 KiB
+ *  linux               64 * NAND_BLOCK_SIZE = 8 MiB
+ *  rootfs              remainder
+ */
+#endif /* CONFIG_NAND */
+
+/* Board NAND Info. */
+/* Environment information */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"usbtty=cdc_acm\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=auto\0" \
+	"optargs=\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
+	"nandrootfstype=ubifs\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running boot script from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"loadubizimage=ubifsload ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadubifdt=ubifsload ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcbootfdt=echo Booting with DT from mmc ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"if nand read ${loadaddr} linux; then " \
+			"bootm ${loadaddr};" \
+		"fi;\0" \
+	"nanddtsboot=echo Booting from nand with DTS...; " \
+		"run nandargs; " \
+		"ubi part rootfs; "\
+		"ubifsmount ubi0:rootfs; "\
+		"run loadubifdt; "\
+		"run loadubizimage; "\
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"fi;" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loaduimage; then " \
+			"run mmcboot;" \
+		"fi;" \
+		"if run loadzimage; then " \
+			"if test -z \"${fdtfile}\"; then " \
+				"setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \
+			"fi;" \
+			"if run loadfdt; then " \
+				"run mmcbootfdt;" \
+			"fi;" \
+		"fi;" \
+	"fi;" \
+	"run nandboot; " \
+	"if test -z \"${fdtfile}\"; then "\
+		"setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \
+	"fi;" \
+	"run nanddtsboot; " \
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+/* FLASH and environment organization */
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define ONENAND_ENV_OFFSET		0x240000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		0x240000
+#define CONFIG_ENV_ADDR			0x240000
+
+/* Initial RAM setup */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_MAX_ECCPOS  56
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS      {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+					13, 14, 16, 17, 18, 19, 20, 21, 22, \
+					23, 24, 25, 26, 27, 28, 30, 31, 32, \
+					33, 34, 35, 36, 37, 38, 39, 40, 41, \
+					42, 44, 45, 46, 47, 48, 49, 50, 51, \
+					52, 53, 54, 55, 56}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	13
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
new file mode 100644
index 0000000..98f243f
--- /dev/null
+++ b/include/configs/omap3_pandora.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008-2010
+ * Gražvydas Ignotas <notasas@gmail.com>
+ *
+ * Configuration settings for the OMAP3 Pandora.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* override base for compatibility with MLO the device ships with */
+
+#include <configs/ti_omap3_common.h>
+
+#define CONFIG_REVISION_TAG		1
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+
+
+#define CONFIG_BOOTCOMMAND \
+	"run distro_bootcmd; " \
+	"setenv bootargs ${bootargs_ubi}; " \
+	"if mmc rescan && load mmc 0:1 ${loadaddr} autoboot.scr; then " \
+		"source ${loadaddr}; " \
+	"fi; " \
+	"ubi part boot && ubifsmount ubi:boot && " \
+		"ubifsload ${loadaddr} uImage && bootm ${loadaddr}"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"usbtty=cdc_acm\0" \
+	"bootargs_ubi=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \
+		"rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	BOOTENV \
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_ADDR			0x260000
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
new file mode 100644
index 0000000..4dc22a7
--- /dev/null
+++ b/include/configs/omap3_zoom1.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ * Nishanth Menon <nm@ti.com>
+ *
+ * Configuration settings for the TI OMAP3430 Zoom MDK board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap.h>
+#include <configs/ti_omap3_common.h>
+
+/* Remove SPL boot option - we do not support that on LDP yet */
+
+/* Generic NAND definition conflicts with debug_base */
+#undef CONFIG_SYS_NAND_BASE
+
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Hardware drivers
+ */
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"Zoom1"
+
+#if defined(CONFIG_CMD_NAND)
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#endif
+#endif
+
+/*
+ * TWL4030
+ */
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+
+/* Environment information */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"fdtaddr=0x80f80000\0" \
+	"bootfile=uImage\0" \
+	"fdtfile=omap3-ldp.dtb\0" \
+	"bootdir=/\0" \
+	"bootpart=0:1\0" \
+	"usbtty=cdc_acm\0" \
+	"console=ttyO2,115200n8\0" \
+	"mmcdev=0\0" \
+	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
+	"videospec=omapfb:vram:2M,vram:4M\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"video=${videospec},mode:${videomode} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"video=${videospec},mode:${videomode} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"loadzimage=setenv bootfile zImage; if run loadimage; then run loadfdt;fi\0"\
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"mmczboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else if run loadzimage; then " \
+				"run mmczboot; " \
+			"else run nandboot; " \
+			"fi; fi;" \
+		"fi; " \
+	"else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1)	/* memtest */
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_2 + \
+					0x01F00000) /* 31MB */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_ADDR			0x260000
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
new file mode 100644
index 0000000..835b7c2
--- /dev/null
+++ b/include/configs/omap4_panda.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * Configuration settings for the TI OMAP4 Panda board.
+ * See ti_omap4_common.h for OMAP4 common part
+ */
+
+#ifndef __CONFIG_PANDA_H
+#define __CONFIG_PANDA_H
+
+/*
+ * High Level Configuration Options
+ */
+
+/* USB UHH support options */
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
+
+/* USB Networking options */
+
+#define CONFIG_UBOOT_ENABLE_PADS_ALL
+
+#include <configs/ti_omap4_common.h>
+
+/* GPIO */
+
+/* ENV related config options */
+
+#define CONFIG_ENV_OVERWRITE
+
+#endif /* __CONFIG_PANDA_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
new file mode 100644
index 0000000..1a0f9ca
--- /dev/null
+++ b/include/configs/omap4_sdp4430.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * Configuration settings for the TI SDP4430 board.
+ * See ti_omap4_common.h for OMAP4 common part
+ */
+
+#ifndef __CONFIG_SDP4430_H
+#define __CONFIG_SDP4430_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MACH_TYPE	MACH_TYPE_OMAP_4430SDP
+
+#include <configs/ti_omap4_common.h>
+
+/* ENV related config options */
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET		0xE0000
+
+#endif /* __CONFIG_SDP4430_H */
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
new file mode 100644
index 0000000..3710a71
--- /dev/null
+++ b/include/configs/omap5_uevm.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Sricharan R	  <r.sricharan@ti.com>
+ *
+ * Configuration settings for the TI EVM5430 board.
+ * See ti_omap5_common.h for omap5 common settings.
+ */
+
+#ifndef __CONFIG_OMAP5_EVM_H
+#define __CONFIG_OMAP5_EVM_H
+
+#include <environment/ti/dfu.h>
+
+#ifndef CONFIG_SPL_BUILD
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+#endif
+
+#define DFUARGS \
+	"dfu_bufsiz=0x10000\0" \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_EMMC \
+	DFU_ALT_INFO_RAM
+
+#include <configs/ti_omap5_common.h>
+
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+
+/* MMC ENV related defines */
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_HSMMC2_8BIT
+
+/* Required support for the TCA642X GPIO we have on the uEVM */
+#define CONFIG_TCA642X
+#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
+#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
+
+/* USB UHH support options */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
+#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
+
+/* Enabled commands */
+
+/* USB Networking options */
+
+#define CONSOLEDEV		"ttyS2"
+
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
+#endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
new file mode 100644
index 0000000..1c41e7e
--- /dev/null
+++ b/include/configs/omapl138_lcdk.h
@@ -0,0 +1,240 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_OMAPL138_LCDK
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
+#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
+	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
+	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
+	DAVINCI_SYSCFG_SUSPSRC_I2C)
+
+/*
+ * PLL configuration
+ */
+
+/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
+#define CONFIG_SYS_DA850_PLL0_PLLM     18
+#define CONFIG_SYS_DA850_PLL1_PLLM     21
+
+/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+					DV_DDR_PHY_EXT_STRBEN | \
+					(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (		  \
+	(1 << DV_DDR_SDCR_DDR2EN_SHIFT)		| \
+	(1 << DV_DDR_SDCR_DDREN_SHIFT)		| \
+	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT)	| \
+	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	| \
+	(4 << DV_DDR_SDCR_CL_SHIFT)		| \
+	(3 << DV_DDR_SDCR_IBANK_SHIFT)		| \
+	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (		  \
+	(19 << DV_DDR_SDTMR1_RFC_SHIFT)		| \
+	(1 << DV_DDR_SDTMR1_RP_SHIFT)		| \
+	(1 << DV_DDR_SDTMR1_RCD_SHIFT)		| \
+	(2 << DV_DDR_SDTMR1_WR_SHIFT)		| \
+	(6 << DV_DDR_SDTMR1_RAS_SHIFT)		| \
+	(8 << DV_DDR_SDTMR1_RC_SHIFT)		| \
+	(1 << DV_DDR_SDTMR1_RRD_SHIFT)		| \
+	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		  \
+	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT)	| \
+	(2 << DV_DDR_SDTMR2_XP_SHIFT)		| \
+	(0 << DV_DDR_SDTMR2_ODT_SHIFT)		| \
+	(20 << DV_DDR_SDTMR2_XSNR_SHIFT)	| \
+	(199 << DV_DDR_SDTMR2_XSRD_SHIFT)	| \
+	(1 << DV_DDR_SDTMR2_RTP_SHIFT)		| \
+	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
+#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED	25000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE	10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR	0x20
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_NAND
+#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE			(128 << 9)
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define	CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS		3
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_NAND_MASK_CLE	0x10
+#define CONFIG_SYS_NAND_MASK_ALE	0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
+					CONFIG_SYS_NAND_U_BOOT_SIZE - \
+					CONFIG_SYS_MALLOC_LEN -       \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS		{				\
+				6, 7, 8, 9, 10, 11, 12, 13, 14, 15,	\
+				22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
+				38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
+				54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_LOAD
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#undef	CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#endif
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE		"zImage" /* Boot file name */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+
+/*
+ * USB Configs
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTCOMMAND \
+		"run envboot; " \
+		"run mmcboot; "
+
+#define DEFAULT_LINUX_BOOT_ENV \
+	"loadaddr=0xc0700000\0" \
+	"fdtaddr=0xc0600000\0" \
+	"scriptaddr=0xc0600000\0"
+
+#include <environment/ti/mmc.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	DEFAULT_MMC_TI_ARGS \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"fdtfile=da850-lcdk.dtb\0" \
+	"boot_fdt=yes\0" \
+	"boot_fit=0\0" \
+	"console=ttyS2,115200n8\0"
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+/* SD/MMC */
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_ENV_OFFSET
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
+#endif
+
+/* defines for SPL */
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
+						CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SPL_STACK	0x8001ff00
+#define CONFIG_SPL_MAX_FOOTPRINT	32768
+#define CONFIG_SPL_PAD_TO	32768
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+					GENERATED_GBL_DATA_SIZE)
+
+#include <asm/arch/hardware.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/openrd.h b/include/configs/openrd.h
new file mode 100644
index 0000000..62d8862
--- /dev/null
+++ b/include/configs/openrd.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef _CONFIG_OPENRD_H
+#define _CONFIG_OPENRD_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SHEEVA_88SV131	1	/* CPU Core subversion */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_OFFSET		0x80000	/* env starts here */
+/*
+ * Environment is right behind U-Boot in flash. Make sure U-Boot
+ * doesn't grow into the environment area.
+ */
+#define CONFIG_BOARD_SIZE_LIMIT		CONFIG_ENV_OFFSET
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"${x_bootcmd_kernel}; "	\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console=ttyS0,115200 " \
+	CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
+	"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0"	\
+	"x_bootcmd_usb=usb start\0"					\
+	"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+# ifdef CONFIG_BOARD_IS_OPENRD_BASE
+#  define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+# else
+#  define CONFIG_MVGBE_PORTS	{1, 1}	/* enable both ports */
+# endif
+# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
+#  define CONFIG_PHY_BASE_ADR	0x0
+#  define PHY_NO		"88E1121"
+# else
+#  define CONFIG_PHY_BASE_ADR	0x8
+#  define PHY_NO		"88E1116"
+# endif
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MVEBU_MMC
+#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
+#endif /* CONFIG_CMD_MMC */
+
+#endif /* _CONFIG_OPENRD_BASE_H */
diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h
new file mode 100644
index 0000000..309b471
--- /dev/null
+++ b/include/configs/opos6uldev.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Armadeus Systems
+ *
+ * Configuration settings for the OPOS6ULDev board
+ */
+
+#ifndef __OPOS6ULDEV_CONFIG_H
+#define __OPOS6ULDEV_CONFIG_H
+
+#include "mx6_common.h"
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_REGULATOR
+#endif
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 << 20)
+
+/* Miscellaneous configurable options */
+#define CONFIG_STANDALONE_LOAD_ADDR	CONFIG_SYS_LOAD_ADDR
+
+/* Physical Memory Map */
+#define CONFIG_SYS_SDRAM_BASE		MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* USB */
+#ifdef CONFIG_USB_EHCI_MX6
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#endif
+
+/* Ethernet */
+#ifdef CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x1
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME			"FEC"
+#endif
+
+/* LCD */
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_SPLASH_SOURCE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_MXS
+#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
+#endif
+#endif
+
+/* Environment is stored in the eMMC boot partition */
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_SYS_MMC_ENV_PART         1
+#define CONFIG_ENV_SIZE                 (10 * 1024)
+#define CONFIG_ENV_OFFSET               (1024 * 1024) /* 1 MB */
+#define CONFIG_ENV_OFFSET_REDUND        (1536 * 1024) /* 512KB from CONFIG_ENV_OFFSET */
+
+#define CONFIG_ENV_VERSION	100
+#define CONFIG_BOARD_NAME	opos6ul
+#define ACFG_CONSOLE_DEV        ttymxc0
+#define CONFIG_SYS_AUTOLOAD     "no"
+#define CONFIG_ROOTPATH         "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
+#define CONFIG_BOOTCOMMAND	"run emmcboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"env_version="          __stringify(CONFIG_ENV_VERSION)         "\0"                    \
+	"consoledev="           __stringify(ACFG_CONSOLE_DEV)           "\0"                    \
+	"board_name="           __stringify(CONFIG_BOARD_NAME)          "\0"                    \
+	"fdt_addr=0x88000000\0"                                                                 \
+	"fdt_high=0xffffffff\0"                                                                 \
+	"fdt_name="           __stringify(CONFIG_BOARD_NAME)          "dev\0"                   \
+	"initrd_high=0xffffffff\0"                                                              \
+	"ip_dyn=yes\0"                                                                          \
+	"stdin=serial\0"                                                                        \
+	"stdout=serial\0"                                                                       \
+	"stderr=serial\0"                                                                       \
+	"mmcdev=0\0"                                                                            \
+	"mmcpart=2\0"                                                                           \
+	"mmcroot=/dev/mmcblk0p2 ro\0"                                                           \
+	"mmcrootfstype=ext4 rootwait\0"                                                         \
+	"kernelimg="           __stringify(CONFIG_BOARD_NAME)          "-linux.bin\0"           \
+	"videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \
+	"check_env=if test -n ${flash_env_version}; "                                           \
+		"then env default env_version; "                                                \
+		"else env set flash_env_version ${env_version}; env save; "                     \
+		"fi; "                                                                          \
+		"if itest ${flash_env_version} != ${env_version}; then "                        \
+			"echo \"*** Warning - Environment version"                              \
+			" change suggests: run flash_reset_env; reset\"; "                      \
+			"env default flash_reset_env; "                                         \
+		"else exit; fi; \0"                                                             \
+	"flash_reset_env=env default -f -a && saveenv && "                                      \
+		"echo Environment variables erased!\0"                                          \
+	"download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl\0"                    \
+	"flash_uboot_spl="                                                                      \
+		"if mmc dev 0 1; then "                                                         \
+			"setexpr sz ${filesize} / 0x200; "                                      \
+			"setexpr sz ${sz} + 1; "                                                \
+			"if mmc write ${loadaddr} 0x2 ${sz}; then "                             \
+				"echo Flashing of U-boot SPL succeed; "                         \
+			"else echo Flashing of U-boot SPL failed; "                             \
+			"fi; "                                                                  \
+		"fi;\0"                                                                         \
+	"download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img\0"                    \
+	"flash_uboot_img="                                                                      \
+		"if mmc dev 0 1; then "                                                         \
+			"setexpr sz ${filesize} / 0x200; "                                      \
+			"setexpr sz ${sz} + 1; "                                                \
+			"if mmc write ${loadaddr} 0x8a ${sz}; then "                            \
+				"echo Flashing of U-boot image succeed; "                       \
+			"else echo Flashing of U-boot image failed; "                           \
+			"fi; "                                                                  \
+		"fi;\0"                                                                         \
+	"update_uboot=run download_uboot_spl flash_uboot_spl "                                  \
+		"download_uboot_img flash_uboot_img\0"                                          \
+	"download_kernel=tftpboot ${loadaddr} ${kernelimg}\0"                                   \
+	"flash_kernel="                                                                         \
+		"if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then "    \
+			"echo kernel update succeed; "                                          \
+			"else echo kernel update failed; "                                      \
+		"fi;\0"                                                                         \
+	"update_kernel=run download_kernel flash_kernel\0"                                      \
+	"download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb\0"                            \
+	"flash_dtb="                                                                            \
+		"if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then " \
+			"echo dtb update succeed; "                                             \
+			"else echo dtb update in failed; "                                      \
+		"fi;\0"                                                                         \
+	"update_dtb=run download_dtb flash_dtb\0"                                               \
+	"download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4\0"                      \
+	"flash_rootfs="                                                                         \
+		"if mmc dev 0 0; then "                                                         \
+			"setexpr nbblocks ${filesize} / 0x200; "                                \
+			"setexpr nbblocks ${nbblocks} + 1; "                                    \
+			"if mmc write ${loadaddr} 0x40800 ${nbblocks}; then "                   \
+				"echo Flashing of rootfs image succeed; "                       \
+			"else echo Flashing of rootfs image failed; "                           \
+			"fi; "                                                                  \
+		"fi;\0"                                                                         \
+	"update_rootfs=run download_rootfs flash_rootfs\0"                                      \
+	"flash_failsafe="                                                                       \
+		"if mmc dev 0 0; then "                                                         \
+			"setexpr nbblocks ${filesize} / 0x200; "                                \
+			"setexpr nbblocks ${nbblocks} + 1; "                                    \
+			"if mmc write ${loadaddr} 0x800 ${nbblocks}; then "                     \
+				"echo Flashing of rootfs image in failsafe partition succeed; " \
+			"else echo Flashing of rootfs image in failsafe partition failed; "     \
+			"fi; "                                                                  \
+		"fi;\0"                                                                         \
+	"update_failsafe=run download_rootfs flash_failsafe\0"                                  \
+	"download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4\0"                 \
+	"flash_userdata="                                                                       \
+		"if mmc dev 0 0; then "                                                         \
+			"setexpr nbblocks ${filesize} / 0x200; "                                \
+			"setexpr nbblocks ${nbblocks} + 1; "                                    \
+			"if mmc write ${loadaddr} 0 ${nbblocks}; then "                         \
+				"echo Flashing of user_data image succeed; "                    \
+			"else echo Flashing of user_data image failed; "                        \
+			"fi; "                                                                  \
+		"fi;\0"                                                                         \
+	"update_userdata=run download_userdata flash_userdata; mmc rescan\0"                    \
+	"erase_userdata="                                                                       \
+		"if mmc dev 0 0; then "                                                         \
+			"echo Erasing eMMC User Data partition, no way out...; "                \
+			"mw ${loadaddr} 0 0x200000; "                                           \
+			"mmc write ${loadaddr} 0 0x1000; "                                      \
+			"mmc write ${loadaddr} 0x800 0x1000; "                                  \
+			"mmc write ${loadaddr} 0x40800 0x1000; "                                \
+			"mmc write ${loadaddr} 0x440800 0x1000; "                               \
+		"fi;"                                                                           \
+		"mmc rescan\0"                                                                  \
+	"update_all=run update_rootfs update_uboot\0"						\
+	"initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs}\0"         \
+	"addipargs=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:"                       \
+		"${gatewayip}:${netmask}:${hostname}:eth0:off\0"                                \
+	"addmmcargs=setenv bootargs ${bootargs} root=${mmcroot} "                               \
+		"rootfstype=${mmcrootfstype}\0"                                                 \
+	"emmcboot=run initargs; run addmmcargs; "                                               \
+		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} && "              \
+		"load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb && "    \
+		"bootz ${loadaddr} - ${fdt_addr};\0"                                            \
+	"emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot;\0"      \
+	"addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw "                              \
+		"nfsroot=${serverip}:${rootpath}\0"                                             \
+	"nfsboot=run initargs; run addnfsargs addipargs; "                                      \
+		"nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} && "                 \
+		"nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb && "       \
+		"bootz ${loadaddr} - ${fdt_addr};\0"
+
+#endif /* __OPOS6ULDEV_CONFIG_H */
diff --git a/include/configs/origen.h b/include/configs/origen.h
new file mode 100644
index 0000000..44561ac
--- /dev/null
+++ b/include/configs/origen.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board.
+ */
+
+#ifndef __CONFIG_ORIGEN_H
+#define __CONFIG_ORIGEN_H
+
+#include <configs/exynos4-common.h>
+
+/* High Level Configuration Options */
+#define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
+#define CONFIG_ORIGEN			1	/* working with ORIGEN*/
+
+/* ORIGEN has 4 bank of DRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_ORIGEN
+
+/* select serial console configuration */
+
+/* Console configuration */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+/* MMC SPL */
+#define COPY_BL2_FNPTR_ADDR	0x02020030
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x40007000\0" \
+	"rdaddr=0x48000000\0" \
+	"kerneladdr=0x40007000\0" \
+	"ramdiskaddr=0x48000000\0" \
+	"console=ttySAC2,115200n8\0" \
+	"mmcdev=0\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+        "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+        "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+                "source ${loadaddr}\0"
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"fi; " \
+	"fi;" \
+	"load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} "
+
+#define CONFIG_CLK_1000_400_200
+
+/* MIU (Memory Interleaving Unit) */
+#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
+#define RESERVE_BLOCK_SIZE		(512)
+#define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
+
+#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x02040000
+
+/* U-Boot copy size from boot Media to DRAM.*/
+#define COPY_BL2_SIZE		0x80000
+#define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
+#define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
new file mode 100644
index 0000000..4efef89
--- /dev/null
+++ b/include/configs/ot1200.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014 Bachmann electronic GmbH
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
+
+/* UART Configs */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE           UART1_BASE
+
+/* SF Configs */
+
+/* IO expander */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x20
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x20, 16} }
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED            100000
+
+/* OCOTP Configs */
+#define CONFIG_IMX_OTP
+#define IMX_OTP_BASE                    OCOTP_BASE_ADDR
+#define IMX_OTP_ADDR_MAX                0x7F
+#define IMX_OTP_DATA_ERROR_VAL          0xBADABADA
+#define IMX_OTPWRITE_ENABLED
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE                    ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE             MII100
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          0x5
+#define CONFIG_PHY_SMSC
+
+#ifndef CONFIG_SPL
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_BUS             1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#endif
+
+/* Thermal support */
+#define CONFIG_IMX_THERMAL
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE                 (64 * 1024)	/* 64 kb */
+#define CONFIG_ENV_OFFSET               (1024 * 1024)
+/* M25P16 has an erase size of 64 KiB */
+#define CONFIG_ENV_SECT_SIZE            (64 * 1024)
+
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_BOOTFILE
+
+#endif         /* __CONFIG_H */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
new file mode 100644
index 0000000..1481d68
--- /dev/null
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -0,0 +1,889 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * QorIQ RDB boards configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_TARGET_P1020MBG)
+#define CONFIG_BOARDNAME "P1020MBG-PC"
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0xe4
+#define __SW_BOOT_SD		0x54
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+#if defined(CONFIG_TARGET_P1020UTM)
+#define CONFIG_BOARDNAME "P1020UTM-PC"
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0xe0
+#define __SW_BOOT_SD		0x50
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+#if defined(CONFIG_TARGET_P1020RDB_PC)
+#define CONFIG_BOARDNAME "P1020RDB-PC"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0x5c
+#define __SW_BOOT_SPI		0x1c
+#define __SW_BOOT_SD		0x9c
+#define __SW_BOOT_NAND		0xec
+#define __SW_BOOT_PCIE		0x6c
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+/*
+ * P1020RDB-PD board has user selectable switches for evaluating different
+ * frequency and boot options for the P1020 device. The table that
+ * follow describe the available options. The front six binary number was in
+ * accordance with SW3[1:6].
+ * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
+ * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
+ * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
+ * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
+ * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
+ * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
+ * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
+ */
+#if defined(CONFIG_TARGET_P1020RDB_PD)
+#define CONFIG_BOARDNAME "P1020RDB-PD"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0x64
+#define __SW_BOOT_SPI		0x34
+#define __SW_BOOT_SD		0x24
+#define __SW_BOOT_NAND		0x44
+#define __SW_BOOT_PCIE		0x74
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#endif
+
+#if defined(CONFIG_TARGET_P1021RDB)
+#define CONFIG_BOARDNAME "P1021RDB-PC"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
+						addresses in the LBC */
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0x5c
+#define __SW_BOOT_SPI		0x1c
+#define __SW_BOOT_SD		0x9c
+#define __SW_BOOT_NAND		0xec
+#define __SW_BOOT_PCIE		0x6c
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#endif
+
+#if defined(CONFIG_TARGET_P1024RDB)
+#define CONFIG_BOARDNAME "P1024RDB"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK		0xf3
+#define __SW_BOOT_NOR		0x00
+#define __SW_BOOT_SPI		0x08
+#define __SW_BOOT_SD		0x04
+#define __SW_BOOT_NAND		0x0c
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+#if defined(CONFIG_TARGET_P1025RDB)
+#define CONFIG_BOARDNAME "P1025RDB"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SLIC
+
+#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
+						addresses in the LBC */
+#define __SW_BOOT_MASK		0xf3
+#define __SW_BOOT_NOR		0x00
+#define __SW_BOOT_SPI		0x08
+#define __SW_BOOT_SD		0x04
+#define __SW_BOOT_NAND		0x0c
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+#if defined(CONFIG_TARGET_P2020RDB)
+#define CONFIG_BOARDNAME "P2020RDB-PC"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_VSC7385_ENET
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0xc8
+#define __SW_BOOT_SPI		0x28
+#define __SW_BOOT_SD		0x68 /* or 0x18 */
+#define __SW_BOOT_NAND		0xe8
+#define __SW_BOOT_PCIE		0xa8
+#define CONFIG_SYS_L2_SIZE	(512 << 10)
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_TPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_MAX_SIZE		4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif /* not CONFIG_TPL_BUILD */
+
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_TPL_TEXT_BASE
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+#endif
+
+#define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_LBA48
+
+#if defined(CONFIG_TARGET_P2020RDB)
+#define CONFIG_SYS_CLK_FREQ	100000000
+#else
+#define CONFIG_SYS_CLK_FREQ	66666666
+#endif
+#define CONFIG_DDR_CLK_FREQ	66666666
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
+       SPL code*/
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM 1
+#define SPD_EEPROM_ADDRESS 0x52
+
+#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+#else
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_1G
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#endif
+#define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+/* Default settings for DDR3 */
+#ifndef CONFIG_TARGET_P2020RDB
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655A608
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x04401050
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00330004
+#define CONFIG_SYS_DDR_TIMING_1		0x6f6B4846
+#define CONFIG_SYS_DDR_TIMING_2		0x0FA8C8CF
+#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
+#define CONFIG_SYS_DDR_MODE_1		0x40461520
+#define CONFIG_SYS_DDR_MODE_2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL		0x0C300000
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x7fff_ffff	DDR		Up to 2GB cacheable
+ * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
+ * 0xec00_0000 0xefff_ffff	NOR flash	Up to 64M non-cacheable	CS0/1
+ * 0xf8f8_0000 0xf8ff_ffff	L2 SRAM		Up to 512K cacheable
+ *   (early boot only)
+ * 0xff80_0000 0xff80_7fff	NAND flash	32K non-cacheable	CS1/0
+ * 0xff98_0000 0xff98_ffff	PMC		64K non-cacheable	CS2
+ * 0xffa0_0000 0xffaf_ffff	CPLD		1M non-cacheable	CS3
+ * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable	CS2
+ * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
+ * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K cacheable
+ * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
+#define CONFIG_SYS_FLASH_BASE		0xec000000
+#elif defined(CONFIG_TARGET_P1020UTM)
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
+#define CONFIG_SYS_FLASH_BASE		0xee000000
+#else
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* 16M */
+#define CONFIG_SYS_FLASH_BASE		0xef000000
+#endif
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+	| BR_PS_16 | BR_V)
+
+#define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Nand Flash */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#if defined(CONFIG_TARGET_P1020RDB_PD)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#else
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+#endif
+
+#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+	| BR_PS_8	/* Port Size = 8 bit */ \
+	| BR_MS_FCM	/* MSEL = FCM */ \
+	| BR_V)	/* valid */
+#if defined(CONFIG_TARGET_P1020RDB_PD)
+#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
+	| OR_FCM_PGS	/* Large Page*/ \
+	| OR_FCM_CSCT \
+	| OR_FCM_CST \
+	| OR_FCM_CHT \
+	| OR_FCM_SCY_1 \
+	| OR_FCM_TRLX \
+	| OR_FCM_EHTR)
+#else
+#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
+	| OR_FCM_CSCT \
+	| OR_FCM_CST \
+	| OR_FCM_CHT \
+	| OR_FCM_SCY_1 \
+	| OR_FCM_TRLX \
+	| OR_FCM_EHTR)
+#endif
+#endif /* CONFIG_NAND_FSL_ELBC */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+/* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
+
+#define CONFIG_SYS_CPLD_BASE	0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CPLD_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
+#endif
+/* CPLD config size: 1Mb */
+#define CONFIG_CPLD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
+					BR_PS_8 | BR_V)
+#define CONFIG_CPLD_OR_PRELIM	(0xfff009f7)
+
+#define CONFIG_SYS_PMC_BASE	0xff980000
+#define CONFIG_SYS_PMC_BASE_PHYS	CONFIG_SYS_PMC_BASE
+#define CONFIG_PMC_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
+					BR_PS_8 | BR_V)
+#define CONFIG_PMC_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
+				 OR_GPCM_EAD)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#endif
+#define CONFIG_SYS_BR3_PRELIM	CONFIG_CPLD_BR_PRELIM	/* CPLD Base Address */
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_CPLD_OR_PRELIM	/* CPLD Options */
+
+/* Vsc7385 switch */
+#ifdef CONFIG_VSC7385_ENET
+#define CONFIG_SYS_VSC7385_BASE		0xffb00000
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
+#else
+#define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
+#endif
+
+#define CONFIG_SYS_VSC7385_BR_PRELIM	\
+	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_VSC7385_OR_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | \
+			OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
+			OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_BR2_PRELIM	CONFIG_SYS_VSC7385_BR_PRELIM
+#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_VSC7385_OR_PRELIM
+
+/* The size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+#endif
+
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#if defined(CONFIG_TARGET_P2020RDB)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(364 << 10)
+#else
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
+#endif
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif /* CONFIG_TPL_BUILD */
+#endif
+#endif
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
+#define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
+
+/*
+ * I2C2 EEPROM
+ */
+#undef CONFIG_ID_EEPROM
+
+#define CONFIG_RTC_PT7C4338
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
+
+/* enable read and write access to EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
+#endif
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR	2
+#define TSEC2_PHY_ADDR	0
+#define TSEC3_PHY_ADDR	1
+
+#define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX	0
+#define TSEC2_PHYIDX	0
+#define TSEC3_PHYIDX	0
+
+#define CONFIG_ETHPRIME	"eTSEC1"
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif /* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_QE
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FW_ADDR	0xefec0000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#endif /* CONFIG_QE */
+
+#ifdef CONFIG_TARGET_P1025RDB
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
+
+#undef CONFIG_UEC_ETH
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1	/* ETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
+#define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	0x0	/* 0x0 for MII */
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+#endif /* CONFIG_UEC_ETH1 */
+
+#define CONFIG_UEC_ETH5	/* ETH5 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH5
+#define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
+#define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
+#define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
+#define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC5_PHY_ADDR	0x3	/* 0x3 for RMII */
+#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
+#endif /* CONFIG_UEC_ETH5 */
+#endif /* CONFIG_TARGET_P1025RDB */
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_ENV_SIZE		0x2000	/* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define CONFIG_ENV_OFFSET	(1024 * 1024)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#endif
+#endif
+
+#if defined(CONFIG_TARGET_P1020RDB_PD)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#undef CONFIG_WATCHDOG	/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME		"unknown"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR	1000000
+
+#ifdef __SW_BOOT_NOR
+#define __NOR_RST_CMD	\
+norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_SPI
+#define __SPI_RST_CMD	\
+spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_SD
+#define __SD_RST_CMD	\
+sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_NAND
+#define __NAND_RST_CMD	\
+nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_PCIE
+#define __PCIE_RST_CMD	\
+pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+"netdev=eth0\0"	\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
+"loadaddr=1000000\0"	\
+"bootfile=uImage\0"	\
+"tftpflash=tftpboot $loadaddr $uboot; "	\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
+"consoledev=ttyS0\0"	\
+"ramdiskaddr=2000000\0"	\
+"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
+"fdtaddr=1e00000\0"	\
+"bdev=sda1\0" \
+"jffs2nor=mtdblock3\0"	\
+"norbootaddr=ef080000\0"	\
+"norfdtaddr=ef040000\0"	\
+"jffs2nand=mtdblock9\0"	\
+"nandbootaddr=100000\0"	\
+"nandfdtaddr=80000\0"		\
+"ramdisk_size=120000\0"	\
+"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
+"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
+__stringify(__NOR_RST_CMD)"\0" \
+__stringify(__SPI_RST_CMD)"\0" \
+__stringify(__SD_RST_CMD)"\0" \
+__stringify(__NAND_RST_CMD)"\0" \
+__stringify(__PCIE_RST_CMD)"\0"
+
+#define CONFIG_NFSBOOTCOMMAND	\
+"setenv bootargs root=/dev/nfs rw "	\
+"nfsroot=$serverip:$rootpath "	\
+"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"tftp $loadaddr $bootfile;"	\
+"tftp $fdtaddr $fdtfile;"	\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT	\
+"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
+"console=$consoledev,$baudrate $othbootargs;" \
+"usb start;"	\
+"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
+"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_USB_FAT_BOOT	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"usb start;"	\
+"fatload usb 0:2 $loadaddr $bootfile;"	\
+"fatload usb 0:2 $fdtaddr $fdtfile;"	\
+"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_USB_EXT2_BOOT	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"usb start;"	\
+"ext2load usb 0:4 $loadaddr $bootfile;"	\
+"ext2load usb 0:4 $fdtaddr $fdtfile;" \
+"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_NORBOOT	\
+"setenv bootargs root=/dev/$jffs2nor rw "	\
+"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
+"bootm $norbootaddr - $norfdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"tftp $ramdiskaddr $ramdiskfile;"	\
+"tftp $loadaddr $bootfile;"	\
+"tftp $fdtaddr $fdtfile;"	\
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_HDBOOT
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
new file mode 100644
index 0000000..1e0708a
--- /dev/null
+++ b/include/configs/p1_twr.h
@@ -0,0 +1,490 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * QorIQ P1 Tower boards configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_TWR_P1025)
+#define CONFIG_BOARDNAME "TWR-P1025"
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Conversion of LBC addr */
+#define CONFIG_SYS_LBC_LCRR	0x80000002	/* LB clock ratio reg */
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_LBA48
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /*sysclk for TWR-P1025 */
+
+#define CONFIG_DDR_CLK_FREQ	66666666
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_512M
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+/* Default settings for DDR3 */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655a608
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xc70c0000	/* Type = DDR3	*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x04401050
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00220004
+#define CONFIG_SYS_DDR_TIMING_1		0x5c5b6544
+#define CONFIG_SYS_DDR_TIMING_2		0x0fa880de
+#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
+#define CONFIG_SYS_DDR_MODE_1		0x80461320
+#define CONFIG_SYS_DDR_MODE_2		0x00008000
+#define CONFIG_SYS_DDR_INTERVAL		0x09480000
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x1fff_ffff	DDR		Up to 512MB cacheable
+ * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
+ * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
+ *
+ * Localbus
+ * 0xe000_0000 0xe002_0000	SSD1289		128K non-cacheable
+ * 0xec00_0000 0xefff_ffff	FLASH		Up to 64M non-cacheable
+ *
+ * 0xff90_0000 0xff97_ffff	L2 SRAM		Up to 512K cacheable
+ * 0xffd0_0000 0xffd0_3fff	init ram	16K Cacheable
+ * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
+#define CONFIG_SYS_FLASH_BASE		0xec000000
+
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
+	| BR_PS_16 | BR_V)
+
+#define CONFIG_FLASH_OR_PRELIM	0xfc0000b1
+
+#define CONFIG_SYS_SSD_BASE	0xe0000000
+#define CONFIG_SYS_SSD_BASE_PHYS	CONFIG_SYS_SSD_BASE
+#define CONFIG_SSD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
+					BR_PS_16 | BR_V)
+#define CONFIG_SSD_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+				 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
+				 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
+#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
+/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+/* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
+
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+
+/* Serial Port
+ * open - index 2
+ * shorted - index 1
+ */
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL			/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C spd and slave address */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C spd and slave address */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+#define CONFIG_SYS_I2C_PCA9555_ADDR	0x23
+
+/* enable read and write access to EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"TWR-ELEV PCIe SLOT"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#undef CONFIG_TSEC2
+#undef CONFIG_TSEC2_NAME
+#define CONFIG_TSEC3
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR	2
+#define TSEC2_PHY_ADDR	0
+#define TSEC3_PHY_ADDR	1
+
+#define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX	0
+#define TSEC2_PHYIDX	0
+#define TSEC3_PHYIDX	0
+
+#define CONFIG_ETHPRIME	"eTSEC1"
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#undef CONFIG_HAS_ETH2
+#endif /* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_QE
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FW_ADDR	0xefec0000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#endif /* CONFIG_QE */
+
+#ifdef CONFIG_TWR_P1025
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
+
+#undef CONFIG_UEC_ETH
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1	/* ETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
+#define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	0x18	/* 0x18 for MII */
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+#endif /* CONFIG_UEC_ETH1 */
+
+#define CONFIG_UEC_ETH5	/* ETH5 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH5
+#define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
+#define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
+#define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
+#define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC5_PHY_ADDR	0x19	/* 0x19 for RMII */
+#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
+#endif /* CONFIG_UEC_ETH5 */
+#endif /* CONFIG_TWR-P1025 */
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_SYS_RAMBOOT
+#ifdef CONFIG_RAMBOOT_SDCARD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+#else
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#endif
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#undef CONFIG_WATCHDOG	/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME		"unknown"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR	1000000
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+"netdev=eth0\0"	\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
+"loadaddr=1000000\0"	\
+"bootfile=uImage\0"	\
+"dtbfile=twr-p1025twr.dtb\0"	\
+"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
+"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0"	\
+"tftpflash=tftpboot $loadaddr $uboot; "	\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"kernelflash=tftpboot $loadaddr $bootfile; "	\
+	"protect off 0xefa80000 +$filesize; "	\
+	"erase 0xefa80000 +$filesize; "	\
+	"cp.b $loadaddr 0xefa80000 $filesize; "	\
+	"protect on 0xefa80000 +$filesize; "	\
+	"cmp.b $loadaddr 0xefa80000 $filesize\0"	\
+"dtbflash=tftpboot $loadaddr $dtbfile; "	\
+	"protect off 0xefe80000 +$filesize; "	\
+	"erase 0xefe80000 +$filesize; "	\
+	"cp.b $loadaddr 0xefe80000 $filesize; "	\
+	"protect on 0xefe80000 +$filesize; "	\
+	"cmp.b $loadaddr 0xefe80000 $filesize\0"	\
+"ramdiskflash=tftpboot $loadaddr $ramdiskfile; "	\
+	"protect off 0xeeb80000 +$filesize; "	\
+	"erase 0xeeb80000 +$filesize; "	\
+	"cp.b $loadaddr 0xeeb80000 $filesize; "	\
+	"protect on 0xeeb80000 +$filesize; "	\
+	"cmp.b $loadaddr 0xeeb80000 $filesize\0"	\
+"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; "	\
+	"protect off 0xefec0000 +$filesize; "	\
+	"erase 0xefec0000 +$filesize; "	\
+	"cp.b $loadaddr 0xefec0000 $filesize; "	\
+	"protect on 0xefec0000 +$filesize; "	\
+	"cmp.b $loadaddr 0xefec0000 $filesize\0"	\
+"consoledev=ttyS0\0"	\
+"ramdiskaddr=2000000\0"	\
+"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
+"fdtaddr=1e00000\0"	\
+"bdev=sda1\0"	\
+"norbootaddr=ef080000\0"	\
+"norfdtaddr=ef040000\0"	\
+"ramdisk_size=120000\0" \
+"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
+"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
+
+#define CONFIG_NFSBOOTCOMMAND	\
+"setenv bootargs root=/dev/nfs rw "	\
+"nfsroot=$serverip:$rootpath "	\
+"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"tftp $loadaddr $bootfile&&"	\
+"tftp $fdtaddr $fdtfile&&"	\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT	\
+"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
+"console=$consoledev,$baudrate $othbootargs;" \
+"usb start;"	\
+"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
+"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_USB_FAT_BOOT	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"usb start;"	\
+"fatload usb 0:2 $loadaddr $bootfile;"	\
+"fatload usb 0:2 $fdtaddr $fdtfile;"	\
+"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_USB_EXT2_BOOT	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"usb start;"	\
+"ext2load usb 0:4 $loadaddr $bootfile;"	\
+"ext2load usb 0:4 $fdtaddr $fdtfile;" \
+"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_NORBOOT	\
+"setenv bootargs root=/dev/mtdblock3 rw "	\
+"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
+"bootm $norbootaddr - $norfdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND_TFTP	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"tftp $ramdiskaddr $ramdiskfile;"	\
+"tftp $loadaddr $bootfile;"	\
+"tftp $fdtaddr $fdtfile;"	\
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"bootm 0xefa80000 0xeeb80000 0xefe80000"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_RAMBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h
new file mode 100644
index 0000000..177e8d8
--- /dev/null
+++ b/include/configs/p2371-0000.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _P2371_0000_H
+#define _P2371_0000_H
+
+#include <linux/sizes.h>
+
+#include "tegra210-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA P2371-0000"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_SPI_FLASH_SIZE		(4 << 20)
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* _P2371_0000_H */
diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h
new file mode 100644
index 0000000..7205a17
--- /dev/null
+++ b/include/configs/p2371-2180.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _P2371_2180_H
+#define _P2371_2180_H
+
+#include <linux/sizes.h>
+
+#include "tegra210-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA P2371-2180"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_SPI_FLASH_SIZE		(4 << 20)
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
+#define COUNTER_FREQUENCY	19200000
+
+#endif /* _P2371_2180_H */
diff --git a/include/configs/p2571.h b/include/configs/p2571.h
new file mode 100644
index 0000000..02db6bb
--- /dev/null
+++ b/include/configs/p2571.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _P2571_H
+#define _P2571_H
+
+#include <linux/sizes.h>
+
+#include "tegra210-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA P2571"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_SPI_FLASH_SIZE		(4 << 20)
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* _P2571_H */
diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h
new file mode 100644
index 0000000..e546c1d
--- /dev/null
+++ b/include/configs/p2771-0000.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2013-2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _P2771_0000_H
+#define _P2771_0000_H
+
+#include <linux/sizes.h>
+
+#include "tegra186-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA P2771-0000"
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+	"calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \
+		"ramdisk_addr_r\0" \
+	"kernel_addr_r_align=00200000\0" \
+	"kernel_addr_r_offset=00080000\0" \
+	"kernel_addr_r_size=02000000\0" \
+	"kernel_addr_r_aliases=loadaddr\0" \
+	"fdt_addr_r_align=00200000\0" \
+	"fdt_addr_r_offset=00000000\0" \
+	"fdt_addr_r_size=00200000\0" \
+	"scriptaddr_align=00200000\0" \
+	"scriptaddr_offset=00000000\0" \
+	"scriptaddr_size=00200000\0" \
+	"pxefile_addr_r_align=00200000\0" \
+	"pxefile_addr_r_offset=00000000\0" \
+	"pxefile_addr_r_size=00200000\0" \
+	"ramdisk_addr_r_align=00200000\0" \
+	"ramdisk_addr_r_offset=00000000\0" \
+	"ramdisk_addr_r_size=02000000\0"
+
+#include "tegra-common-post.h"
+
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
+#define COUNTER_FREQUENCY	19200000
+
+#endif
diff --git a/include/configs/paz00.h b/include/configs/paz00.h
new file mode 100644
index 0000000..b76958c
--- /dev/null
+++ b/include/configs/paz00.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include "tegra20-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"Compal Paz00"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_PAZ00
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h
new file mode 100644
index 0000000..943fca9
--- /dev/null
+++ b/include/configs/pcl063.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Collabora Ltd.
+ *
+ * Based on include/configs/xpress.h:
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ */
+#ifndef __PCL063_H
+#define __PCL063_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/*
+ * There is a bug in some i.MX6UL processors that results in the initial
+ * portion of OCRAM being unavailable when booting from (at least) an SD
+ * card.
+ *
+ * Tweak the SPL text base address to avoid this.
+ */
+
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+/* Console configs */
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			SZ_256M
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_SIZE			(16 << 10)
+#define CONFIG_ENV_OFFSET		(512 << 10)
+
+/* NAND */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc0,115200n8\0" \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"pxefile_addr_r=0x87100000\0" \
+	"ramdisk_addr_r=0x82100000\0" \
+	"scriptaddr=0x87000000\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(UBIFS, ubifs, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#endif /* __PCL063_H */
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h
new file mode 100644
index 0000000..650caaa
--- /dev/null
+++ b/include/configs/pcl063_ull.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board configuration file for Phytec phyBOARD-i.MX6ULL-Segin SBC
+ * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
+ *
+ * Based on include/configs/xpress.h:
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ */
+#ifndef __PCL063_ULL_H
+#define __PCL063_ULL_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* SPL options */
+#include "imx6_spl.h"
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+/* Environment settings */
+#define CONFIG_ENV_SIZE			(0x4000)
+#define CONFIG_ENV_OFFSET		(0x80000)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND	\
+	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+
+/* Environment in SD */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		0
+#define MMC_ROOTFS_DEV		0
+#define MMC_ROOTFS_PART		2
+
+/* Console configs */
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* I2C configs */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			SZ_256M
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* NAND */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+
+#define CONFIG_IMX_THERMAL
+
+#define ENV_MMC \
+	"mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
+	"mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
+	"fitpart=1\0" \
+	"bootdelay=3\0" \
+	"silent=1\0" \
+	"optargs=rw rootwait\0" \
+	"mmcautodetect=yes\0" \
+	"mmcrootfstype=ext4\0" \
+	"mmcfit_name=fitImage\0" \
+	"mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
+		    "${mmcfit_name}\0" \
+	"mmcargs=setenv bootargs " \
+		"root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \
+		"console=${console} rootfstype=${mmcrootfstype}\0" \
+	"mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0xffffffff\0" \
+	"console=ttymxc0,115200n8\0" \
+	"addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
+	"fit_addr=0x82000000\0" \
+	ENV_MMC
+
+#define CONFIG_BOOTCOMMAND		"run mmc_mmc_fit"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#endif /* __PCL063_ULL_H */
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
new file mode 100644
index 0000000..fdbc075
--- /dev/null
+++ b/include/configs/pcm051.h
@@ -0,0 +1,133 @@
+/*
+ * pcm051.h
+ *
+ * Phytec phyCORE-AM335x (pcm051) boards information header
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_PCM051_H
+#define __CONFIG_PCM051_H
+
+#include <configs/ti_am335x_common.h>
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_PCM051
+
+/* set to negative value for no autoboot */
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"setenv mmcdev " #instance"; "\
+	"setenv bootpart " #instance":2 ; "\
+	"run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel "=" \
+	"run nandboot\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(LEGACY_MMC, legacy_mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(LEGACY_MMC, legacy_mmc, 1) \
+	func(NAND, nand, 0)
+
+#define CONFIG_BOOTCOMMAND \
+	"run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
+#include <environment/ti/dfu.h>
+#include <environment/ti/mmc.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	DEFAULT_MMC_TI_ARGS \
+	"bootfile=uImage\0" \
+	"fdtfile=am335x-wega-rdk.dtb\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+	"ramrootfstype=ext2\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run args_mmc; " \
+		"bootm ${loadaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootm ${loadaddr}\0" \
+	BOOTENV
+
+/* Clock Defines */
+#define V_OSCK				25000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+/*
+ * memtest works on 8 MB in DRAM after skipping 32MB from
+ * start addr of ram disk
+ */
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + (64 << 20))
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
+					+ (8 * 1024 * 1024))
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+
+/* I2C Configuration */
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
+4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
+
+/* CPU */
+
+#ifdef CONFIG_SPI_BOOT
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
+#endif
+
+/*
+ * USB configuration
+ */
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#define CONFIG_PHY_SMSC
+
+#endif	/* ! __CONFIG_PCM051_H */
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
new file mode 100644
index 0000000..fb8f3c8
--- /dev/null
+++ b/include/configs/pcm052.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the phytec PCM-052 SoM.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * SZ_1M)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* NAND support */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+/* QSPI Configs*/
+#ifdef CONFIG_FSL_QSPI
+#define FSL_QSPI_FLASH_SIZE		(SZ_16M)
+#define FSL_QSPI_FLASH_NUM		2
+#define CONFIG_SYS_FSL_QSPI_LE
+#endif
+
+
+#define CONFIG_LOADADDR			0x82000000
+
+/* We boot from the gfxRAM area of the OCRAM. */
+#define CONFIG_BOARD_SIZE_LIMIT		520192
+
+/* if no target-specific extra environment settings were defined by the
+   target, define an empty one */
+#ifndef PCM052_EXTRA_ENV_SETTINGS
+#define PCM052_EXTRA_ENV_SETTINGS
+#endif
+
+/* if no target-specific boot command was defined by the target,
+   define an empty one */
+#ifndef PCM052_BOOTCOMMAND
+#define PCM052_BOOTCOMMAND
+#endif
+
+/* if no target-specific extra environment settings were defined by the
+   target, define an empty one */
+#ifndef PCM052_NET_INIT
+#define PCM052_NET_INIT
+#endif
+
+/* boot command, including the target-defined one if any */
+#define CONFIG_BOOTCOMMAND	PCM052_BOOTCOMMAND "run bootcmd_nand"
+
+/* Extra env settings (including the target-defined ones if any) */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	PCM052_EXTRA_ENV_SETTINGS \
+	"autoload=no\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"blimg_file=u-boot.vyb\0" \
+	"blimg_addr=0x81000000\0" \
+	"kernel_file=zImage\0" \
+	"kernel_addr=0x82000000\0" \
+	"fdt_file=zImage.dtb\0" \
+	"fdt_addr=0x81000000\0" \
+	"ram_file=uRamdisk\0" \
+	"ram_addr=0x83000000\0" \
+	"filesys=rootfs.ubifs\0" \
+	"sys_addr=0x81000000\0" \
+	"tftploc=/path/to/tftp/directory/\0" \
+	"nfs_root=/path/to/nfs/root\0" \
+	"tftptimeout=1000\0" \
+	"tftptimeoutcountmax=1000000\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"bootargs_base=setenv bootargs rw " \
+		" mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \
+		"console=ttyLP1,115200n8\0" \
+	"bootargs_sd=setenv bootargs ${bootargs} " \
+		"root=/dev/mmcblk0p2 rootwait\0" \
+	"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
+		"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
+	"bootargs_nand=setenv bootargs ${bootargs} " \
+		"ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \
+	"bootargs_ram=setenv bootargs ${bootargs} " \
+		"root=/dev/ram rw initrd=${ram_addr}\0" \
+	"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
+		"fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
+		"fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
+		"bootz ${kernel_addr} - ${fdt_addr}\0" \
+	"bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
+		"tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
+		"tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
+		"bootz ${kernel_addr} - ${fdt_addr}\0" \
+	"bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
+		"nand read ${fdt_addr} dtb; " \
+		"nand read ${kernel_addr} kernel; " \
+		"bootz ${kernel_addr} - ${fdt_addr}\0" \
+	"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
+		"nand read ${fdt_addr} dtb; " \
+		"nand read ${kernel_addr} kernel; " \
+		"nand read ${ram_addr} root; " \
+		"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
+	"update_bootloader_from_tftp=" PCM052_NET_INIT \
+		"if tftp ${blimg_addr} "\
+		"${tftpdir}${blimg_file}; then " \
+		"mtdparts default; " \
+		"nand erase.part bootloader; " \
+		"nand write ${blimg_addr} bootloader ${filesize}; fi\0" \
+	"update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
+		"${kernel_file}; " \
+		"then mtdparts default; " \
+		"nand erase.part kernel; " \
+		"nand write ${kernel_addr} kernel ${filesize}; " \
+		"if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
+		"nand erase.part dtb; " \
+		"nand write ${fdt_addr} dtb ${filesize}; fi\0" \
+	"update_kernel_from_tftp=" PCM052_NET_INIT \
+		"if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
+		"then setenv fdtsize ${filesize}; " \
+		"if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
+		"mtdparts default; " \
+		"nand erase.part dtb; " \
+		"nand write ${fdt_addr} dtb ${fdtsize}; " \
+		"nand erase.part kernel; " \
+		"nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
+	"update_rootfs_from_tftp=" PCM052_NET_INIT \
+		"if tftp ${sys_addr} ${tftpdir}${filesys}; " \
+		"then mtdparts default; " \
+		"nand erase.part root; " \
+		"ubi part root; " \
+		"ubi create rootfs; " \
+		"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
+	"update_ramdisk_from_tftp=" PCM052_NET_INIT \
+		"if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
+		"then mtdparts default; " \
+		"nand erase.part root; " \
+		"nand write ${ram_addr} root ${filesize}; fi\0"
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START	0x80010000
+#define CONFIG_SYS_MEMTEST_END		0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical memory map */
+#define PHYS_SDRAM			(0x80000000)
+#define PHYS_SDRAM_SIZE			(CONFIG_PCM052_DDR_SIZE * SZ_1M)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_SIZE			(SZ_8K)
+
+#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE		(SZ_128K)
+#define CONFIG_ENV_SIZE			(SZ_8K)
+#define CONFIG_ENV_OFFSET		0xA0000
+#define CONFIG_ENV_SIZE_REDUND		(SZ_8K)
+#define CONFIG_ENV_OFFSET_REDUND	0xC0000
+#endif
+
+#endif
diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h
new file mode 100644
index 0000000..855bc44
--- /dev/null
+++ b/include/configs/pcm058.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ */
+
+
+#ifndef __PCM058_CONFIG_H
+#define __PCM058_CONFIG_H
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+#include "mx6_common.h"
+
+/* Thermal */
+#define CONFIG_IMX_THERMAL
+
+/* Serial */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
+#define CONSOLE_DEV		"ttymxc1"
+
+#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
+
+/* Early setup */
+
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(8 * SZ_1M)
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		3
+
+/* SPI Flash */
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+#ifndef CONFIG_SPL_BUILD
+/* Enable NAND support */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+
+/* Filesystem support */
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE                (16 * 1024)
+#define CONFIG_ENV_OFFSET		(1024 * SZ_1K)
+#define CONFIG_ENV_SECT_SIZE		(64 * SZ_1K)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + \
+						CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET              (0x1E0000)
+#define CONFIG_ENV_SECT_SIZE           (128 * SZ_1K)
+#endif
+
+#endif
diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h
new file mode 100644
index 0000000..e4c2872
--- /dev/null
+++ b/include/configs/pdu001.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * pdu001.h
+ *
+ * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef __CONFIG_PDU001_H
+#define __CONFIG_PDU001_H
+
+#include <configs/ti_am335x_common.h>
+
+/* Using 32K of volatile storage for environment */
+#define CONFIG_ENV_SIZE		0x4000
+
+#define MACH_TYPE_PDU001	5075
+#define CONFIG_MACH_TYPE	MACH_TYPE_PDU001
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK			24000000  /* Clock output from T2 */
+#define V_SCLK			(V_OSCK)
+
+#if CONFIG_CONS_INDEX == 1
+	#define CONSOLE_DEV "ttyO0"
+#elif CONFIG_CONS_INDEX == 2
+	#define CONSOLE_DEV "ttyO1"
+#elif CONFIG_CONS_INDEX == 3
+	#define CONSOLE_DEV "ttyO2"
+#elif CONFIG_CONS_INDEX == 4
+	#define CONSOLE_DEV "ttyO3"
+#elif CONFIG_CONS_INDEX == 5
+	#define CONSOLE_DEV "ttyO4"
+#elif CONFIG_CONS_INDEX == 6
+	#define CONSOLE_DEV "ttyO5"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+	"run eval_boot_device;" \
+	"setenv bootargs console=${console} " \
+	"vt.global_cursor_default=0 " \
+	"root=/dev/mmcblk${mmc_boot}p${root_fs_partition} " \
+	"rootfstype=ext4 " \
+	"rootwait " \
+	"rootdelay=1;" \
+	"fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};" \
+	"fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};" \
+	"bootz ${loadaddr} - ${fdtaddr}"
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"fdtfile=am335x-pdu001.dtb\0" \
+	"bootfile=zImage\0" \
+	"console=" CONSOLE_DEV ",115200n8\0" \
+	"root_fs_partition=2\0" \
+	"eval_boot_device=" \
+		"if test $boot_device = emmc; then " \
+			"setenv mmc_boot 0;" \
+		"elif test $boot_device = sdcard; then " \
+			"setenv mmc_boot 1;" \
+		"else " \
+			"echo Bootdevice is neither MMC0 nor MMC1;" \
+			"reset;" \
+		"fi;" \
+	"\0"
+#endif
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1	UART0_BASE
+#define CONFIG_SYS_NS16550_COM2	UART1_BASE
+#define CONFIG_SYS_NS16550_COM3	UART2_BASE
+#define CONFIG_SYS_NS16550_COM4	UART3_BASE
+#define CONFIG_SYS_NS16550_COM5	UART4_BASE
+#define CONFIG_SYS_NS16550_COM6	UART5_BASE
+#define CONFIG_BAUDRATE		115200
+
+#endif	/* ! __CONFIG_PDU001_H */
diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h
new file mode 100644
index 0000000..a732e06
--- /dev/null
+++ b/include/configs/peach-pi.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board.
+ */
+
+#ifndef __CONFIG_PEACH_PI_H
+#define __CONFIG_PEACH_PI_H
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x22000000\0" \
+	"fdt_addr_r=0x23000000\0" \
+	"ramdisk_addr_r=0x23300000\0" \
+	"scriptaddr=0x30000000\0" \
+	"pxefile_addr_r=0x31000000\0"
+
+#include <configs/exynos5420-common.h>
+#include <configs/exynos5-dt-common.h>
+#include <configs/exynos5-common.h>
+
+#define CONFIG_SYS_SDRAM_BASE	0x20000000
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
+
+/* select serial console configuration */
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+/* Display */
+#ifdef CONFIG_LCD
+#define CONFIG_EXYNOS_FB
+#define CONFIG_EXYNOS_DP
+#define LCD_BPP			LCD_COLOR16
+#endif
+
+#define CONFIG_POWER_TPS65090_EC
+
+/* DRAM Memory Banks */
+#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
+
+#endif	/* __CONFIG_PEACH_PI_H */
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
new file mode 100644
index 0000000..6c5960c
--- /dev/null
+++ b/include/configs/peach-pit.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG/GOOGLE PEACH-PIT board.
+ */
+
+#ifndef __CONFIG_PEACH_PIT_H
+#define __CONFIG_PEACH_PIT_H
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x22000000\0" \
+	"fdt_addr_r=0x23000000\0" \
+	"ramdisk_addr_r=0x23300000\0" \
+	"scriptaddr=0x30000000\0" \
+	"pxefile_addr_r=0x31000000\0"
+
+#include <configs/exynos5420-common.h>
+#include <configs/exynos5-dt-common.h>
+#include <configs/exynos5-common.h>
+
+#define CONFIG_SYS_SDRAM_BASE	0x20000000
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
+
+/* select serial console configuration */
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+/* DRAM Memory Banks */
+#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
+
+#endif	/* __CONFIG_PEACH_PIT_H */
diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h
new file mode 100644
index 0000000..a535d0c
--- /dev/null
+++ b/include/configs/pengwyn.h
@@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * pengwyn.h
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
+ */
+
+#ifndef __CONFIG_PENGWYN_H
+#define __CONFIG_PENGWYN_H
+
+
+#include <configs/ti_am335x_common.h>
+
+/* Clock Defines */
+#define V_OSCK				24000000
+#define V_SCLK				V_OSCK
+
+/* set env size */
+#define CONFIG_ENV_SIZE			0x4000
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"fdtaddr=0x80F80000\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"fdtfile=am335x-pengwyn.dtb\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 ro\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"rootpath=/export/rootfs\0" \
+	"nfsopts=nolock\0" \
+	"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+		"::off\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcloados=run mmcargs; " \
+		"bootz ${loadaddr} - ${fdtaddr};\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt;" \
+				"run mmcloados;" \
+			"fi;" \
+		"fi;\0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"tftp ${loadaddr} ${bootfile}; " \
+		"tftp ${fdtaddr} ${fdtfile}; " \
+		"run netargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdtaddr} u-boot-spl-os; " \
+		"nand read ${loadaddr} kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+	"run mmcboot;" \
+	"run nandboot;"
+
+/* NS16550 Configuration: primary UART via FTDI */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000
+
+/* I2C Configuration */
+#define	CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/* SPL */
+
+/* NAND support */
+
+/* NAND Configuration. */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	4096
+#define CONFIG_SYS_NAND_OOBSIZE		224
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*4096)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{   2,   3,   4,   5,   6,   7,   8,   9,  10,  11,  12,  13,  14,  15,  16,  17,\
+					   18,  19,  20,  21,  22,  23,  24,  25,  26,  27,  28,  29,  30,  31,  32,  33,\
+					   34,  35,  36,  37,  38,  39,  40,  41,  42,  43,  44,  45,  46,  47,  48,  49,\
+					   50,  51,  52,  53,  54,  55,  56,  57,  58,  59,  60,  61,  62,  63,  64,  65,\
+					   66,  67,  68,  69,  70,  71,  72,  73,  74,  75,  76,  77,  78,  79,  80,  81,\
+					   82,  83,  84,  85,  86,  87,  88,  89,  90,  91,  92,  93,  94,  95,  96,  97,\
+					   98,  99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,\
+					  114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\
+					  134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153,\
+					  154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,\
+					  174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\
+					  194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209}
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	26
+#define CONFIG_SYS_NAND_ECCSTEPS	8
+#define	CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH16_CODE_HW
+/* END NAND Configuration. */
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+/* #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000 */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000
+
+/* Size must be a multiple of Nand erase size (524288 b) */
+#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x280000
+#endif
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support.
+ */
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+/* Network */
+#define CONFIG_PHY_RESET	1
+#define CONFIG_PHY_NATSEMI
+#define CONFIG_PHY_REALTEK
+
+#endif	/* ! __CONFIG_PENGWYN_H */
diff --git a/include/configs/pepper.h b/include/configs/pepper.h
new file mode 100644
index 0000000..662fce3
--- /dev/null
+++ b/include/configs/pepper.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Gumstix, Inc. - http://www.gumstix.com/
+ */
+
+#ifndef __CONFIG_PEPPER_H
+#define __CONFIG_PEPPER_H
+
+#include <configs/ti_am335x_common.h>
+
+/* Clock defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+
+/* Mach type */
+#define CONFIG_MACH_TYPE		MACH_TYPE_PEPPER
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"fdtfile=am335x-pepper.dtb\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
+		"load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"loaduimage=fatload mmc ${mmcdev}:1 ${loadaddr} uImage\0" \
+	"uimageboot=echo Booting from mmc${mmcdev} ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"ubiboot=echo Booting from nand (ubifs) ...; " \
+		"run ubiargs; run ubiload; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run mmcload; then " \
+			"run mmcboot;" \
+		"fi;" \
+		"if run loaduimage; then " \
+			"run uimageboot;" \
+		"fi;" \
+	"fi;" \
+
+/* Serial console configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000
+
+/* Ethernet support */
+#define CONFIG_PHY_RESET_DELAY 1000
+
+/* SPL */
+
+#endif /* __CONFIG_PEPPER_H */
diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h
new file mode 100644
index 0000000..8731d89
--- /dev/null
+++ b/include/configs/pfla02.h
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ */
+
+
+#ifndef __PCM058_CONFIG_H
+#define __PCM058_CONFIG_H
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+#include "mx6_common.h"
+
+/* Thermal */
+#define CONFIG_IMX_THERMAL
+
+/* Serial */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART4_BASE
+#define CONSOLE_DEV		"ttymxc3"
+
+/* Early setup */
+
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(8 * SZ_1M)
+
+/* Ethernet */
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		3
+
+/* SPI Flash */
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 0 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_NAND
+/* Enable NAND support */
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+
+/* Filesystem support */
+
+/* Various command support */
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* Environment organization */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                (16 * 1024)
+#define CONFIG_ENV_OFFSET		(1024 * SZ_1K)
+#define CONFIG_ENV_SECT_SIZE		(64 * SZ_1K)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + \
+						CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET              (0x1E0000)
+#define CONFIG_ENV_SECT_SIZE           (128 * SZ_1K)
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=${console},${baudrate}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+		"${netmask}:${hostname}:${netdev}:off\0"		\
+	"addmisc=setenv bootargs ${bootargs} ${miscargs}\0"		\
+	"addmtd=run mtdnand;run mtdspi;"				\
+		"setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"mtdnand=setenv mtdparts mtdparts=gpmi-nand:"			\
+		"40m(Kernels),400m(root),-(nand)\0"			\
+	"mtdspi=setenv mtdparts ${mtdparts}"				\
+		"';spi2.0:1024k(bootloader),"				\
+			"64k(env1),64k(env2),-(rescue)'\0"		\
+	"bootcmd=if test -n ${rescue};"					\
+		"then run swupdate;fi;run nandboot;run swupdate\0"	\
+	"bootfile=uImage\0"						\
+	"bootimage=uImage\0"						\
+	"console=ttymxc3\0"						\
+	"fdt_addr_r=0x18000000\0"					\
+	"fdt_file=pfla02.dtb\0"						\
+	"fdt_high=0xffffffff\0"						\
+	"initrd_high=0xffffffff\0"					\
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0"		\
+	"miscargs=panic=1 quiet\0"					\
+	"mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0"		\
+	"mmcboot=if run mmcload;then "					\
+		"run mmcargs addcons addmisc;"				\
+			"bootm;fi\0"					\
+	"mmcload=mmc rescan;"						\
+		"load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\
+	"mmcpart=1\0"							\
+	"mmcroot=/dev/mmcblk0p1\0"					\
+	"ubiroot=1\0"							\
+	"nandargs=setenv bootargs ubi.mtd=1 "				\
+		"root=ubi0:rootfs${ubiroot} rootfstype=ubifs\0"		\
+	"nandboot=run mtdnand;ubi part nand0,0;"			\
+		"ubi readvol ${kernel_addr_r} kernel${ubiroot};"	\
+		"run nandargs addip addcons addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};"	\
+		"tftp ${fdt_addr_r} ${board_name}/${fdt_file};"		\
+		"run nfsargs addip addcons addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_nfs_fit=tftp ${kernel_addr_r} ${board_name}/${fitfile};"	\
+		"run nfsargs addip addcons addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"nfsargs=setenv bootargs root=/dev/nfs"				\
+		" nfsroot=${serverip}:${nfsroot},v3 panic=1\0"		\
+	"swupdate=setenv bootargs root=/dev/ram;"			\
+		"run addip addcons addmtd addmisc;"			\
+		"sf probe;"						\
+		"sf read ${kernel_addr_r} 120000 600000;"		\
+		"sf read 14000000 730000 800000;"			\
+		"bootm ${kernel_addr_r} 14000000\0"
+
+#endif
diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h
new file mode 100644
index 0000000..ca28b6f
--- /dev/null
+++ b/include/configs/phycore_am335x_r2.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * phycore_am335x_r2.h
+ *
+ * Phytec phyCORE-AM335x R2 (PCL060 / PCM060) boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#ifndef __CONFIG_PHYCORE_AM335x_R2_H
+#define __CONFIG_PHYCORE_AM335x_R2_H
+
+#include <configs/ti_am335x_common.h>
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_SBC_PHYCORE_AM335X
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:root ubi.mtd=NAND.UBI\0" \
+	"nandrootfstype=ubifs rootwait rw fsck.repair=yes\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"ubi part NAND.UBI; " \
+		"ubi readvol ${fdtaddr} oftree; " \
+		"ubi readvol ${loadaddr} kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+
+#else
+#define NANDARGS ""
+#endif
+
+/* set to negative value for no autoboot */
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"setenv mmcdev " #instance "; "\
+	"setenv bootpart " #instance ":1 ; "\
+	"setenv rootpart " #instance ":2 ; "\
+	"run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"run nandboot\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(LEGACY_MMC, legacy_mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(LEGACY_MMC, legacy_mmc, 1) \
+	func(NAND, nand, 0)
+
+#include <config_distro_bootcmd.h>
+#include <environment/ti/dfu.h>
+#include <environment/ti/mmc.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_MMC_TI_ARGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"bootfile=zImage\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"console=ttyS0,115200\0" \
+	"optargs=\0" \
+	"mmcrootfstype=ext2 rootwait\0" \
+	"finduuid=part uuid mmc ${rootpart} uuid\0" \
+	"boot_fit=0\0" \
+	NANDARGS \
+	BOOTENV
+
+/* Clock Macros */
+#define V_OSCK				25000000  /* Clock output from T2 */
+#define V_SCLK				V_OSCK
+
+#define CONFIG_POWER_TPS65910
+
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+/* NAND: driver related configs */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+#endif
+#endif /* !CONFIG_NAND */
+
+/* CPU */
+
+#ifdef CONFIG_SPI_BOOT
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+
+#endif	/* ! __CONFIG_PHYCORE_AM335x_R2_H */
diff --git a/include/configs/phycore_rk3288.h b/include/configs/phycore_rk3288.h
new file mode 100644
index 0000000..9135aa6
--- /dev/null
+++ b/include/configs/phycore_rk3288.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3288_common.h>
+
+#undef BOOT_TARGET_DEVICES
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1)
+
+#define CONFIG_SYS_MMC_ENV_DEV 1
+
+#endif
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
new file mode 100644
index 0000000..d3ab557
--- /dev/null
+++ b/include/configs/pic32mzdask.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ * Microchip PIC32MZ[DA] Starter Kit.
+ */
+
+#ifndef __PIC32MZDASK_CONFIG_H
+#define __PIC32MZDASK_CONFIG_H
+
+/* System Configuration */
+
+/*--------------------------------------------
+ * CPU configuration
+ */
+/* CPU Timer rate */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	100000000
+
+/*----------------------------------------------------------------------
+ * Memory Layout
+ */
+#define CONFIG_SYS_SRAM_BASE		0x80000000
+#define CONFIG_SYS_SRAM_SIZE		0x00080000 /* 512K */
+
+/* Initial RAM for temporary stack, global data */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_INIT_RAM_ADDR	\
+	(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1)
+
+/* SDRAM Configuration (for final code, data, stack, heap) */
+#define CONFIG_SYS_SDRAM_BASE		0x88000000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(4 << 10)
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
+
+#define CONFIG_SYS_LOAD_ADDR		0x88500000 /* default load address */
+#define CONFIG_SYS_ENV_ADDR		0x88300000
+#define CONFIG_SYS_FDT_ADDR		0x89d00000
+
+/* Memory Test */
+#define CONFIG_SYS_MEMTEST_START	0x88000000
+#define CONFIG_SYS_MEMTEST_END		0x88080000
+
+/*----------------------------------------------------------------------
+ * Commands
+ */
+
+/*------------------------------------------------------------
+ * Console Configuration
+ */
+#define CONFIG_SYS_CBSIZE		1024 /* Console I/O Buffer Size   */
+
+/*-----------------------------------------------------------------------
+ * Networking Configuration
+ */
+#define CONFIG_PHY_SMSC
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_ARP_TIMEOUT		500 /* millisec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*--------------------------------------------------
+ * USB Configuration
+ */
+
+/* -------------------------------------------------
+ * Environment
+ */
+#define CONFIG_ENV_SIZE		0x4000
+
+/* ---------------------------------------------------------------------
+ * Board boot configuration
+ */
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+#define MEM_LAYOUT_ENV_SETTINGS					\
+	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0"	\
+	"fdt_addr_r="__stringify(CONFIG_SYS_FDT_ADDR)"\0"	\
+	"scriptaddr="__stringify(CONFIG_SYS_ENV_ADDR)"\0"
+
+#define CONFIG_LEGACY_BOOTCMD_ENV					\
+	"legacy_bootcmd= "						\
+		"if load mmc 0 ${scriptaddr} uEnv.txt; then "		\
+			"env import -tr ${scriptaddr} ${filesize}; "	\
+			"if test -n \"${bootcmd_uenv}\" ; then "	\
+				"echo Running bootcmd_uenv ...; "	\
+				"run bootcmd_uenv; "			\
+			"fi; "						\
+		"fi; \0"
+
+#define BOOT_TARGET_DEVICES(func)	\
+	func(MMC, mmc, 0)		\
+	func(USB, usb, 0)		\
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	MEM_LAYOUT_ENV_SETTINGS		\
+	CONFIG_LEGACY_BOOTCMD_ENV	\
+	BOOTENV
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND	"run distro_bootcmd || run legacy_bootcmd"
+
+#endif	/* __PIC32MZDASK_CONFIG_H */
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
new file mode 100644
index 0000000..5bbb9ea
--- /dev/null
+++ b/include/configs/pico-imx6.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the pico-imx6 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#include "imx6_spl.h"
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* Falcon Mode */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME   "args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SYS_SPL_ARGS_ADDR   0x18000000
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(35 * SZ_1M) /* Increase due to DFU */
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC3_BASE_ADDR
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+#define CONFIG_DFU_ENV_SETTINGS \
+	"dfu_alt_info=" \
+		"spl raw 0x2 0x400;" \
+		"u-boot raw 0x8a 0x1000;" \
+		"/boot/zImage ext4 0 1;" \
+		"rootfs part 0 1\0" \
+
+#define BOOTMENU_ENV \
+	"bootmenu_0=Boot using PICO-Hobbit baseboard=" \
+		"setenv baseboard hobbit; saveenv; run base_boot\0" \
+	"bootmenu_1=Boot using PICO-Pi baseboard=" \
+		"setenv baseboard pi; saveenv; run base_boot\0" \
+	"bootmenu_2=Boot using PICO-Dwarf baseboard=" \
+		"setenv baseboard dwarf; saveenv; run base_boot\0" \
+	"bootmenu_3=Boot using PICO-Nymph baseboard=" \
+		"setenv baseboard nymph; saveenv; run base_boot\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc0\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	BOOTMENU_ENV \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_addr_r=0x18000000\0" \
+	"fdt_addr=0x18000000\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	CONFIG_DFU_ENV_SETTINGS \
+	"finduuid=part uuid mmc 0:1 uuid\0" \
+	"findfdt="\
+		"if test $baseboard = hobbit && test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-pico-hobbit.dtb; fi; " \
+		"if test $baseboard = pi && test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-pico-pi.dtb; fi; " \
+		"if test $baseboard = dwarf && test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-pico-dwarf.dtb; fi; " \
+		"if test $baseboard = nymph && test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-pico-nymph.dtb; fi; " \
+		"if test $baseboard = hobbit && test $board_rev = MX6DL ; then " \
+			"setenv fdtfile imx6dl-pico-hobbit.dtb; fi; " \
+		"if test $baseboard = pi && test $board_rev = MX6DL ; then " \
+			"setenv fdtfile imx6dl-pico-pi.dtb; fi; " \
+		"if test $baseboard = dwarf && test $board_rev = MX6DL ; then " \
+			"setenv fdtfile imx6dl-pico-dwarf.dtb; fi; " \
+		"if test $baseboard = nymph && test $board_rev = MX6DL ; then " \
+			"setenv fdtfile imx6dl-pico-nymph.dtb; fi; " \
+		"if test $fdtfile = ask; then " \
+			"echo WARNING: Could not determine dtb to use; fi; \0" \
+	"default_boot=" \
+		"if test $baseboard = ask ; then " \
+			"bootmenu -1; " \
+		"else " \
+			"run base_boot;" \
+		"fi; \0" \
+	"base_boot=run findfdt; run finduuid; run distro_bootcmd\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	"ramdiskaddr=0x13000000\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0)
+
+#include <config_distro_bootcmd.h>
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+/* Environment starts at 768k = 768 * 1024 = 786432 */
+#define CONFIG_ENV_OFFSET		786432
+/*
+ * Detect overlap between U-Boot image and environment area in build-time
+ *
+ * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset
+ * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776
+ *
+ * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
+ * write the direct value here
+ */
+#define CONFIG_BOARD_SIZE_LIMIT		715776
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* Framebuffer */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+#endif			       /* __CONFIG_H * */
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
new file mode 100644
index 0000000..22dfac7
--- /dev/null
+++ b/include/configs/pico-imx6ul.h
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Technexion Ltd.
+ *
+ * Configuration settings for the Technexion PICO-IMX6UL-EMMC board.
+ */
+#ifndef __PICO_IMX6UL_CONFIG_H
+#define __PICO_IMX6UL_CONFIG_H
+
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+#include <asm/mach-imx/gpio.h>
+#include "imx6_spl.h"
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* Falcon Mode */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME   "args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
+#define CONFIG_SYS_SPL_ARGS_ADDR   0x88000000
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
+#endif
+
+/* Network support */
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x1
+#define CONFIG_FEC_XCV_TYPE		RMII
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(35 * SZ_1M) /* Increase due to DFU */
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART6_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+
+#define CONFIG_USBD_HS
+
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+#define CONFIG_DFU_ENV_SETTINGS \
+	"dfu_alt_info=" \
+		"spl raw 0x2 0x400;" \
+		"u-boot raw 0x8a 0x400;" \
+		"/boot/zImage ext4 0 1;" \
+		"/boot/imx6ul-pico-hobbit.dtb ext4 0 1;" \
+		"/boot/imx6ul-pico-pi.dtb ext4 0 1;" \
+		"rootfs part 0 1\0" \
+
+#define BOOTMENU_ENV \
+	"bootmenu_0=Boot using PICO-Dwarf baseboard=" \
+		"setenv fdtfile imx6ul-pico-dwarf.dtb\0" \
+	"bootmenu_1=Boot using PICO-Hobbit baseboard=" \
+		"setenv fdtfile imx6ul-pico-hobbit.dtb\0" \
+	"bootmenu_2=Boot using PICO-Pi baseboard=" \
+		"setenv fdtfile imx6ul-pico-pi.dtb\0" \
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"splashpos=m,m\0" \
+	"console=ttymxc5\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \
+	BOOTMENU_ENV \
+	"fdt_addr=0x83000000\0" \
+	"fdt_addr_r=0x83000000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x83000000\0" \
+	"ramdiskaddr=0x83000000\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	"mmcautodetect=yes\0" \
+	CONFIG_DFU_ENV_SETTINGS \
+	"findfdt=" \
+		"if test $fdtfile = ask ; then " \
+			"bootmenu -1; fi;" \
+		"if test $fdtfile != ask ; then " \
+			"saveenv; fi;\0" \
+	"finduuid=part uuid mmc 0:1 uuid\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
+	"fastboot_partition_alias_system=rootfs\0" \
+	"setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_MEMTEST_START + SZ_128M
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* I2C configs */
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* environment organization */
+#define CONFIG_ENV_SIZE			SZ_8K
+/* Environment starts at 768k = 768 * 1024 = 786432 */
+#define CONFIG_ENV_OFFSET		786432
+/*
+ * Detect overlap between U-Boot image and environment area in build-time
+ *
+ * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset
+ * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776
+ *
+ * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
+ * write the direct value here
+ */
+#define CONFIG_BOARD_SIZE_LIMIT		715776
+
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		0
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
+#endif
+
+#endif /* __PICO_IMX6UL_CONFIG_H */
diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h
new file mode 100644
index 0000000..607784e
--- /dev/null
+++ b/include/configs/pico-imx7d.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 NXP Semiconductors
+ *
+ * Configuration settings for the i.MX7D Pico board.
+ */
+
+#ifndef __PICO_IMX7D_CONFIG_H
+#define __PICO_IMX7D_CONFIG_H
+
+#include "mx7_common.h"
+
+#include "imx7_spl.h"
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* Falcon Mode */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x88000000
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+
+#define CONFIG_MXC_UART_BASE		UART5_IPS_BASE_ADDR
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		1
+
+#define CONFIG_PHY_ATHEROS
+
+/* ENET1 */
+#define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
+
+/* MMC Config */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_DFU_ENV_SETTINGS \
+	"dfu_alt_info=" \
+		"spl raw 0x2 0x400;" \
+		"u-boot raw 0x8a 0x1000;" \
+		"/boot/zImage ext4 0 1;" \
+		"/boot/imx7d-pico-hobbit.dtb ext4 0 1;" \
+		"/boot/imx7d-pico-pi.dtb ext4 0 1;" \
+		"rootfs part 0 1\0" \
+
+/* When booting with FIT specify the node entry containing boot.scr */
+#if defined(CONFIG_FIT)
+#define PICO_BOOT_ENV \
+	BOOTENV								\
+	"fdtovaddr=0x83100000\0"					\
+	"scriptaddr=0x83200000\0"					\
+	"mmcargs=setenv bootargs console=${console},${baudrate} "	\
+		"rootwait rw\0"						\
+	"boot_a_script="						\
+		"load ${devtype} ${devnum}:${distro_bootpart} "		\
+			"${scriptaddr} ${prefix}${script}; "		\
+		"iminfo ${scriptaddr};"					\
+		"if test $? -eq 1; then hab_failsafe; fi;"		\
+		"source ${scriptaddr}:bootscr\0"
+#else
+#define PICO_BOOT_ENV \
+	"bootmenu_0=Boot using PICO-Hobbit baseboard=" \
+		"setenv fdtfile imx7d-pico-hobbit.dtb\0" \
+	"bootmenu_1=Boot using PICO-Dwarf baseboard=" \
+		"setenv fdtfile imx7d-pico-dwarf.dtb\0" \
+	"bootmenu_2=Boot using PICO-Nymph baseboard=" \
+		"setenv fdtfile imx7d-pico-nymph.dtb\0" \
+	"bootmenu_3=Boot using PICO-Pi baseboard=" \
+		"setenv fdtfile imx7d-pico-pi.dtb\0" \
+	BOOTENV
+#endif
+
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"image=zImage\0" \
+	"splashpos=m,m\0" \
+	"splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+	"console=ttymxc4\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \
+	"fdt_addr=0x83000000\0" \
+	"fdt_addr_r=0x83000000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x83000000\0" \
+	"ramdiskaddr=0x83000000\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	CONFIG_DFU_ENV_SETTINGS \
+	"findfdt=" \
+		"if test $fdtfile = ask ; then " \
+			"bootmenu -1; fi;" \
+		"if test $fdtfile != ask ; then " \
+			"saveenv; fi;\0" \
+	"finduuid=part uuid mmc 0:1 uuid\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \
+	"fastboot_partition_alias_system=rootfs\0" \
+	"setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \
+	PICO_BOOT_ENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* I2C configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_MXC_I2C2
+#define CONFIG_SYS_I2C_MXC_I2C3
+#define CONFIG_SYS_I2C_MXC_I2C4
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE3000
+#define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
+
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+/* FLASH and environment organization */
+#define CONFIG_ENV_SIZE			SZ_8K
+
+/* Environment starts at 768k = 768 * 1024 = 786432 */
+#define CONFIG_ENV_OFFSET		786432
+/*
+ * Detect overlap between U-Boot image and environment area in build-time
+ *
+ * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset
+ * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776
+ *
+ * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
+ * write the direct value here
+ */
+#define CONFIG_BOARD_SIZE_LIMIT		715776
+
+#define CONFIG_SYS_FSL_USDHC_NUM		2
+
+#define CONFIG_SYS_MMC_ENV_DEV			0
+#define CONFIG_SYS_MMC_ENV_PART		0
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC			(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS			0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+
+#define CONFIG_IMX_THERMAL
+
+#endif
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
new file mode 100644
index 0000000..ad41d16
--- /dev/null
+++ b/include/configs/picosam9g45.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the mini-box PICOSAM9G45 board.
+ * (C) Copyright 2015 Inter Act B.V.
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9m10g45ek.h
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LCD */
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_ATMEL_LCD
+#define CONFIG_ATMEL_LCD_RGB565
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE		0x23E00000
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_GREEN_LED	AT91_PIN_PD31	/* this is the user1 led */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+/* SDRAM */
+#define PHYS_SDRAM_1		ATMEL_BASE_CS1	/* on DDRSDRC1 */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
+#define PHYS_SDRAM_2		ATMEL_BASE_CS6	/* on DDRSDRC0 */
+#define PHYS_SDRAM_2_SIZE       0x08000000	/* 128 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* MMC */
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x23e00000
+
+#ifdef CONFIG_SYS_USE_MMC
+/* bootstrap + u-boot + env + linux in mmc */
+#define CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 dtb; " \
+				"fatload mmc 0:1 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		0x010000
+#define CONFIG_SPL_STACK		0x310000
+
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+
+#ifdef CONFIG_SYS_USE_MMC
+
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#endif
+#endif
diff --git a/include/configs/platinum.h b/include/configs/platinum.h
new file mode 100644
index 0000000..1b57e99
--- /dev/null
+++ b/include/configs/platinum.h
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Barco (www.barco.com)
+ */
+
+#ifndef __PLATINUM_CONFIG_H__
+#define __PLATINUM_CONFIG_H__
+
+/* SPL */
+
+/* Location in NAND to read U-Boot from */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     (14 * 1024 * 1024)
+
+#include "imx6_spl.h"                  /* common IMX6 SPL configuration */
+#include "mx6_common.h"
+
+/*
+ * Hardware configuration
+ */
+
+/* UART config */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE			UART1_BASE
+
+/* I2C config */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED			100000
+
+/* MMC config */
+#define CONFIG_SYS_FSL_ESDHC_ADDR		0
+#define CONFIG_SYS_FSL_USDHC_NUM		1
+
+/* Ethernet config */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE				ENET_BASE_ADDR
+
+/* USB config */
+#define CONFIG_MXC_USB_PORT			1
+#define CONFIG_MXC_USB_PORTSC			(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS			0
+
+/* Memory config */
+#define PHYS_SDRAM				MMDC0_ARB_BASE_ADDR
+#ifndef PHYS_SDRAM_SIZE
+#define PHYS_SDRAM_SIZE				(1024 << 20)
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR		IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE		IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET		(CONFIG_SYS_INIT_RAM_SIZE - \
+						 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR			(CONFIG_SYS_INIT_RAM_ADDR + \
+						 CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MALLOC_LEN			(16 * 1024 * 1024)
+
+#ifdef CONFIG_CMD_NAND
+
+/* NAND config */
+#ifndef CONFIG_SYS_NAND_MAX_CHIPS
+#define CONFIG_SYS_NAND_MAX_CHIPS		2
+#endif
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA config, needed for GPMI/MXS NAND support */
+
+/* Environment in NAND */
+#define CONFIG_ENV_OFFSET		(16 << 20)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + (512 << 10))
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#else /* CONFIG_CMD_NAND */
+
+/* Environment in MMC */
+#define CONFIG_ENV_SIZE			(8 << 10)
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#endif /* CONFIG_CMD_NAND */
+
+/*
+ * U-Boot configuration
+ */
+
+/* Board startup config */
+
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + \
+						 PHYS_SDRAM_SIZE - (12 << 20))
+
+#define CONFIG_BOOTCOMMAND			"run bootubi_scr"
+
+/* Miscellaneous configurable options */
+
+/* MTD/UBI/UBIFS config */
+
+/*
+ * Environment configuration
+ */
+
+#if (CONFIG_SYS_NAND_MAX_CHIPS == 1)
+#define CONFIG_COMMON_ENV_UBI						\
+	"setubipartition=env set ubipartition ubi\0"			\
+	"setubirfs=env set ubirfs $ubipartition:rootfs$boot_vol\0"
+#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2)
+#define CONFIG_COMMON_ENV_UBI						\
+	"setubipartition=env set ubipartition ubi$boot_vol\0"		\
+	"setubirfs=env set ubirfs ubi0:rootfs\0"
+#endif
+
+#define CONFIG_COMMON_ENV_MISC						\
+	"user=user\0"							\
+	"project="CONFIG_PLATINUM_PROJECT"\0"				\
+	"uimage=uImage\0"						\
+	"dtb="CONFIG_PLATINUM_CPU"-platinum-"CONFIG_PLATINUM_PROJECT".dtb\0" \
+	"serverip=serverip\0"						\
+	"memaddrlinux=0x10800000\0"					\
+	"memaddrsrc=0x11000000\0"					\
+	"memaddrdtb=0x12000000\0"					\
+	"console=ttymxc0\0"						\
+	"baudrate=115200\0"						\
+	"boot_scr=boot.uboot\0"						\
+	"boot_vol=0\0"							\
+	"mtdids="CONFIG_MTDIDS_DEFAULT"\0"					\
+	"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"					\
+	"mmcfs=ext2\0"							\
+	"mmcrootpart=1\0"						\
+	\
+	"setnfspath=env set nfspath /home/nfs/$user/$project/root\0"	\
+	"settftpfilelinux=env set tftpfilelinux $user/$project/$uimage\0" \
+	"settftpfiledtb=env set tftpfiledtb $user/$project/$dtb\0"	\
+	"setubifilelinux=env set ubifilelinux boot/$uimage\0"		\
+	"setubipfiledtb=env set ubifiledtb boot/$dtb\0"			\
+	"setmmcrootdev=env set mmcrootdev /dev/mmcblk0p$mmcrootpart\0"	\
+	"setmmcfilelinux=env set mmcfilelinux /boot/$uimage\0"		\
+	"setmmcfiledtb=env set mmcfiledtb /boot/$dtb\0"			\
+	\
+	"loadtftpkernel=dhcp $memaddrlinux $tftpfilelinux\0"		\
+	"loadtftpdtb=dhcp $memaddrdtb $tftpfiledtb\0"			\
+	"loadubikernel=ubifsload $memaddrlinux $ubifilelinux\0"		\
+	"loadubidtb=ubifsload $memaddrdtb $ubifiledtb\0"		\
+	"loadmmckernel=${mmcfs}load mmc 0:$mmcrootpart $memaddrlinux "	\
+		"$mmcfilelinux\0"					\
+	"loadmmcdtb=${mmcfs}load mmc 0:$mmcrootpart $memaddrdtb "	\
+		"$mmcfiledtb\0"						\
+	\
+	"ubipart=ubi part $ubipartition\0"				\
+	"ubimount=ubifsmount $ubirfs\0"					\
+	\
+	"setbootargscommon=env set bootargs $bootargs "			\
+		"console=$console,$baudrate enable_wait_mode=off\0"	\
+	"setbootargsmtd=env set bootargs $bootargs $mtdparts\0"		\
+	"setbootargsdhcp=env set bootargs $bootargs ip=dhcp\0"		\
+	"setbootargsubirfs=env set bootargs $bootargs "			\
+		"ubi.mtd=$ubipartition root=$ubirfs rootfstype=ubifs\0" \
+	"setbootargsnfsrfs=env set bootargs $bootargs root=/dev/nfs "	\
+		"nfsroot=$serverip:$nfspath,v3,tcp\0"			\
+	"setbootargsmmcrfs=env set bootargs $bootargs "			\
+		"root=$mmcrootdev rootwait rw\0"			\
+	\
+	"bootnet=run settftpfilelinux settftpfiledtb setnfspath "	\
+		"setbootargscommon setbootargsmtd setbootargsdhcp "	\
+			"setbootargsnfsrfs;"				\
+			"run loadtftpkernel loadtftpdtb;"		\
+			"bootm $memaddrlinux - $memaddrdtb\0"		\
+	"bootnet_ubirfs=run settftpfilelinux settftpfiledtb;"		\
+			"run setubipartition setubirfs;"		\
+			"run setbootargscommon setbootargsmtd "		\
+				"setbootargsubirfs;"			\
+			"run loadtftpkernel loadtftpdtb;"		\
+			"bootm $memaddrlinux - $memaddrdtb\0"		\
+	"bootubi=run setubipartition setubirfs setubifilelinux "	\
+				"setubipfiledtb;"			\
+			"run setbootargscommon setbootargsmtd "		\
+				"setbootargsubirfs;"			\
+			"run ubipart ubimount loadubikernel loadubidtb;" \
+			"bootm $memaddrlinux - $memaddrdtb\0"		\
+	"bootubi_scr=run setubipartition setubirfs;"			\
+			"run ubipart ubimount;"				\
+			"if ubifsload ${memaddrsrc} boot/${boot_scr}; "	\
+			"then source ${memaddrsrc}; else run bootubi; fi\0" \
+	"bootmmc=run setmmcrootdev setmmcfilelinux setmmcfiledtb "	\
+			"setbootargscommon setbootargsmmcrfs;"		\
+			"run loadmmckernel loadmmcdtb;"			\
+			"bootm $memaddrlinux - $memaddrdtb\0"		\
+	\
+	"bootcmd="CONFIG_BOOTCOMMAND"\0"
+
+#define CONFIG_COMMON_ENV_SETTINGS			CONFIG_COMMON_ENV_MISC \
+							CONFIG_COMMON_ENV_UBI
+#endif /* __PLATINUM_CONFIG_H__ */
diff --git a/include/configs/platinum_picon.h b/include/configs/platinum_picon.h
new file mode 100644
index 0000000..1b55e73
--- /dev/null
+++ b/include/configs/platinum_picon.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Barco (www.barco.com)
+ */
+
+#ifndef __PLATINUM_PICON_CONFIG_H__
+#define __PLATINUM_PICON_CONFIG_H__
+
+#define CONFIG_PLATINUM_BOARD			"Barco Picon"
+#define CONFIG_PLATINUM_PROJECT			"picon"
+#define CONFIG_PLATINUM_CPU			"imx6dl"
+
+#include <configs/platinum.h>
+
+#define CONFIG_FEC_XCV_TYPE			RMII
+#define CONFIG_FEC_MXC_PHYADDR			0
+
+#define CONFIG_HOSTNAME				"picon"
+
+#define CONFIG_PLATFORM_ENV_SETTINGS		"\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS		CONFIG_COMMON_ENV_SETTINGS \
+						CONFIG_PLATFORM_ENV_SETTINGS
+
+#endif /* __PLATINUM_PICON_CONFIG_H__ */
diff --git a/include/configs/platinum_titanium.h b/include/configs/platinum_titanium.h
new file mode 100644
index 0000000..b402883
--- /dev/null
+++ b/include/configs/platinum_titanium.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Barco (www.barco.com)
+ */
+
+#ifndef __PLATINUM_TITANIUM_CONFIG_H__
+#define __PLATINUM_TITANIUM_CONFIG_H__
+
+#define CONFIG_PLATINUM_BOARD			"Barco Titanium"
+#define CONFIG_PLATINUM_PROJECT			"titanium"
+#define CONFIG_PLATINUM_CPU			"imx6q"
+
+#define PHYS_SDRAM_SIZE				(512 << 20)
+#define CONFIG_SYS_NAND_MAX_CHIPS		1
+
+#include <configs/platinum.h>
+
+#define CONFIG_FEC_XCV_TYPE			RGMII
+#define CONFIG_FEC_MXC_PHYADDR			4
+
+#define CONFIG_PHY_RESET_DELAY			1000
+
+#define CONFIG_HOSTNAME				"titanium"
+
+#define CONFIG_PLATFORM_ENV_SETTINGS		"\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS		CONFIG_COMMON_ENV_SETTINGS \
+						CONFIG_PLATFORM_ENV_SETTINGS
+
+#endif /* __PLATINUM_TITANIUM_CONFIG_H__ */
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
new file mode 100644
index 0000000..43856ba
--- /dev/null
+++ b/include/configs/plutux.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011-2012
+ *  Avionic Design GmbH <www.avionic-design.de>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra20-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Plutux"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+/* NAND support */
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Environment in NAND, aligned to start of last sector */
+#define CONFIG_ENV_OFFSET		(SZ_512M - SZ_128K) /* 128K sectors */
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
new file mode 100644
index 0000000..99ca1f7
--- /dev/null
+++ b/include/configs/pm9261.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * Configuation settings for the RONETIX PM9261 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+
+#include <asm/hardware.h>
+/* ARM asynchronous clock */
+
+#define MASTER_PLL_DIV		15
+#define MASTER_PLL_MUL		162
+#define MAIN_PLL_DIV		2
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
+
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9261"
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_PM9261
+
+/* clocks */
+/* CKGR_MOR - enable main osc. */
+#define CONFIG_SYS_MOR_VAL						\
+		(AT91_PMC_MOR_MOSCEN |					\
+		 (255 << 8))		/* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL						\
+		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
+		 AT91_PMC_PLLXR_OUT(3) |						\
+		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL		\
+		(AT91_PMC_MCKR_CSS_SLOW |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2)
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL		\
+		(AT91_PMC_MCKR_CSS_PLLA |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2)
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOC_PPUDR_VAL	0xFFFF0000
+
+/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
+#define CONFIG_SYS_MATRIX_EBICSA_VAL		\
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1		AT91_SDRAMC_MODE_NORMAL
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL							\
+		(AT91_SDRAMC_NC_9 |						\
+		 AT91_SDRAMC_NR_13 |						\
+		 AT91_SDRAMC_NB_4 |						\
+		 AT91_SDRAMC_CAS_3 |						\
+		 AT91_SDRAMC_DBW_32 |						\
+		 (1 <<  8) |		/* Write Recovery Delay */		\
+		 (7 << 12) |		/* Row Cycle Delay */			\
+		 (3 << 16) |		/* Row Precharge Delay */		\
+		 (2 << 20) |		/* Row to Column Delay */		\
+		 (5 << 24) |		/* Active to Precharge Delay */		\
+		 (1 << 28))		/* Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
+		 AT91_SMC_MODE_DBW_16 |				\
+		 AT91_SMC_MODE_TDF |				\
+		 AT91_SMC_MODE_TDF_CYCLE(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_CR_PROCRST |		\
+		AT91_RSTC_MR_ERSTL(1) |	\
+		AT91_RSTC_MR_ERSTL(2))
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xfff) |					\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xfff))
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Hardware drivers
+ */
+
+/* LCD */
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_BGR555		1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+
+/* SDRAM */
+#define PHYS_SDRAM				0x20000000
+#define PHYS_SDRAM_SIZE				0x04000000	/* 64 megs */
+
+/* NAND flash */
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8			1
+/* our ALE is AD22 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
+/* our CLE is AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)
+
+/* NOR flash */
+#define PHYS_FLASH_1				0x10000000
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT		256
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+
+/* Ethernet */
+#define CONFIG_DRIVER_DM9000			1
+#define CONFIG_DM9000_BASE			0x30000000
+#define DM9000_IO				CONFIG_DM9000_BASE
+#define DM9000_DATA				(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT			1
+#define CONFIG_NET_RETRY_COUNT			20
+#define CONFIG_RESET_PHY_R			1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW			1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#undef CONFIG_SYS_USE_DATAFLASH_CS0
+#undef CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SYS_USE_FLASH	1
+
+#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_ENV_SECT_SIZE	0x210
+#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
+				"sf read 0x22000000 0x84000 0x210000; " \
+				"bootm 0x22000000"
+
+#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_ENV_OFFSET_REDUND	0x80000
+#define CONFIG_ENV_SIZE			0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
+
+#elif defined (CONFIG_SYS_USE_FLASH)
+
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define	CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_OVERWRITE	1
+
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11
+
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+
+#define CONFIG_CON_ROT "fbcon=rotate:3 "
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"				\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"			\
+	"partition=nand0,0\0"					\
+	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
+		CONFIG_CON_ROT					\
+		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
+	"addip=setenv bootargs $(bootargs) "			\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
+		":$(hostname):eth0:off\0"			\
+	"ramboot=tftpboot 0x22000000 vmImage;"			\
+		"run ramargs;run addip;bootm 22000000\0"	\
+	"nfsboot=tftpboot 0x22000000 vmImage;"			\
+		"run nfsargs;run addip;bootm 22000000\0"	\
+	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
+	""
+#else
+#error "Undefined memory device"
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		\
+		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
+				GENERATED_GBL_DATA_SIZE)
+
+#endif
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
new file mode 100644
index 0000000..595acf1
--- /dev/null
+++ b/include/configs/pm9263.h
@@ -0,0 +1,300 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * Configuation settings for the RONETIX PM9263 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+
+#define MASTER_PLL_DIV		6
+#define MASTER_PLL_MUL		65
+#define MAIN_PLL_DIV		2	/* 2 or 4 */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9263"
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_PM9263
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL						\
+		(AT91_PMC_MOR_MOSCEN |					\
+		 (255 << 8))		/* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL						\
+		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
+		 AT91_PMC_PLLXR_OUT(3) |				\
+		 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |	/* PLL Counter */\
+		 (2 << 28) |		/* PLL Clock Frequency Range */	\
+		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+#if (MAIN_PLL_DIV == 2)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL		\
+		(AT91_PMC_MCKR_CSS_SLOW |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL		\
+		(AT91_PMC_MCKR_CSS_PLLA |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2)
+#else
+/* PCK/4 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL			\
+		(AT91_PMC_MCKR_CSS_SLOW |		\
+		 AT91_PMC_MCKR_PRES_1 |		\
+		 AT91_PMC_MCKR_MDIV_4)
+/* PCK/4 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL			\
+		(AT91_PMC_MCKR_CSS_PLLA |		\
+		 AT91_PMC_MCKR_PRES_1 |		\
+		 AT91_PMC_MCKR_MDIV_4)
+#endif
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
+	 AT91_MATRIX_CSA_EBI_CS1A)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1		0
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1		0x3AA
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL							\
+		(AT91_SDRAMC_NC_9 |						\
+		 AT91_SDRAMC_NR_13 |						\
+		 AT91_SDRAMC_NB_4 |						\
+		 AT91_SDRAMC_CAS_2 |						\
+		 AT91_SDRAMC_DBW_32 |						\
+		 (2 <<  8) |	/* tWR -  Write Recovery Delay */		\
+		 (7 << 12) |	/* tRC -  Row Cycle Delay */			\
+		 (2 << 16) |	/* tRP -  Row Precharge Delay */		\
+		 (2 << 20) |	/* tRCD - Row to Column Delay */		\
+		 (5 << 24) |	/* tRAS - Active to Precharge Delay */		\
+		 (8 << 28))	/* tXSR - Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
+		 AT91_SMC_MODE_DBW_16 |				\
+		 AT91_SMC_MODE_TDF |				\
+		 AT91_SMC_MODE_TDF_CYCLE(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_CR_PROCRST |		\
+		AT91_RSTC_MR_ERSTL(1) |	\
+		AT91_RSTC_MR_ERSTL(2))
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xfff) |					\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xfff))
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_USER_LOWLEVEL_INIT	1
+
+/*
+ * Hardware drivers
+ */
+/* LCD */
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_BGR555		1
+
+#define CONFIG_LCD_IN_PSRAM		1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+
+/* SDRAM */
+#define PHYS_SDRAM		0x20000000
+#define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */
+
+/* NOR flash, if populated */
+#define PHYS_FLASH_1			0x10000000
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)
+
+#endif
+
+#define CONFIG_JFFS2_CMDLINE		1
+#define CONFIG_JFFS2_NAND		1
+#define CONFIG_JFFS2_DEV		"nand0" /* NAND device jffs2 lives on */
+#define CONFIG_JFFS2_PART_OFFSET	0	/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE		(256 * 1024 * 1024) /* partition size*/
+
+/* PSRAM */
+#define	PHYS_PSRAM			0x70000000
+#define	PHYS_PSRAM_SIZE			0x00400000	/* 4MB */
+/* Slave EBI1, PSRAM connected */
+#define CONFIG_PSRAM_SCFG		(AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	| \
+					 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5)	| \
+					 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	| \
+					 AT91_MATRIX_SCFG_SLOT_CYCLE(255))
+
+/* Ethernet */
+#define CONFIG_MACB			1
+#define CONFIG_RMII			1
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R		1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW			1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#define CONFIG_SYS_USE_FLASH	1
+#undef CONFIG_SYS_USE_DATAFLASH
+#undef CONFIG_SYS_USE_NANDFLASH
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_ENV_SECT_SIZE	0x210
+#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
+				"sf read 0x22000000 0x84000 0x294000; " \
+				"bootm 0x22000000"
+
+#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_ENV_OFFSET_REDUND	0x80000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
+
+#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
+
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define	CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_OVERWRITE	1
+
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11
+
+#define CONFIG_BOOTCOMMAND		"run flashboot"
+#define CONFIG_ROOTPATH			"/ronetix/rootfs"
+
+#define CONFIG_CON_ROT			"fbcon=rotate:3 "
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"				\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"			\
+	"partition=nand0,0\0"					\
+	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
+		CONFIG_CON_ROT					\
+		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
+	"addip=setenv bootargs $(bootargs) "			\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
+		":$(hostname):eth0:off\0"			\
+	"ramboot=tftpboot 0x22000000 vmImage;"			\
+		"run ramargs;run addip;bootm 22000000\0"	\
+	"nfsboot=tftpboot 0x22000000 vmImage;"			\
+		"run nfsargs;run addip;bootm 22000000\0"	\
+	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
+	""
+
+#else
+#error "Undefined memory device"
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
+				GENERATED_GBL_DATA_SIZE)
+
+#endif
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
new file mode 100644
index 0000000..ae87f9b
--- /dev/null
+++ b/include/configs/pm9g45.h
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Ilko Iliev <iliev@ronetix.at>
+ * Asen Dimov <dimov@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the PM9G45 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE           0x70000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		BIT(21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		BIT(22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PD3
+#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
+#endif
+
+/* Ethernet */
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x23e00000
+
+#ifdef CONFIG_NAND_BOOT
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_OFFSET		0x140000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000
+
+#define CONFIG_BOOTCOMMAND						\
+	"nand read 0x70000000 0x200000 0x300000;"			\
+	"bootm 0x70000000"
+#elif CONFIG_SD_BOOT
+/* bootstrap + u-boot + env + linux in mmc */
+#define CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x71000000 dtb; " \
+				"fatload mmc 0:1 0x72000000 zImage; " \
+				"bootz 0x72000000 - 0x71000000"
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + \
+					      128 * 1024, 0x1000)
+
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		0x010000
+#define CONFIG_SPL_STACK		0x310000
+
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+
+#ifdef CONFIG_SD_BOOT
+
+#define CONFIG_SPL_BSS_START_ADDR	0x70000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
+#define CONFIG_SYS_SPL_MALLOC_START	0x70080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+
+#elif CONFIG_NAND_BOOT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+#endif
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#endif
diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h
new file mode 100644
index 0000000..68d7268
--- /dev/null
+++ b/include/configs/pogo_e02.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012
+ * David Purdy <david.c.purdy@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef _CONFIG_POGO_E02_H
+#define _CONFIG_POGO_E02_H
+
+/*
+ * Machine type definition and ID
+ */
+#define CONFIG_MACH_TYPE		MACH_TYPE_POGO_E02
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#endif
+
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_OFFSET		0x60000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs $(bootargs_console); " \
+	"run bootcmd_usb; " \
+	"bootm 0x00800000 0x01100000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \
+	"32M(rootfs),-(data)\0"\
+	"mtdids=nand0=orion_nand\0"\
+	"bootargs_console=console=ttyS0,115200\0" \
+	"bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \
+	"ext2load usb 0:1 0x01100000 /uInitrd\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * File system
+ */
+
+#endif /* _CONFIG_POGO_E02_H */
diff --git a/include/configs/poplar.h b/include/configs/poplar.h
new file mode 100644
index 0000000..be9a0b5
--- /dev/null
+++ b/include/configs/poplar.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Linaro
+ *
+ * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * Configuration for Poplar 96boards CE. Parts were derived from other ARM
+ * configurations.
+ */
+
+#ifndef _POPLAR_H_
+#define _POPLAR_H_
+
+#include <linux/sizes.h>
+
+/* DRAM banks */
+
+/* SYS */
+#define CONFIG_SYS_BOOTM_LEN			SZ_64M
+#define CONFIG_SYS_INIT_SP_ADDR			0x200000
+#define CONFIG_SYS_LOAD_ADDR			0x800000
+#define CONFIG_SYS_MALLOC_LEN			SZ_32M
+
+/* ATF bl33.bin load address (must match) */
+
+/* USB configuration */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		2
+
+/*****************************************************************************
+ *  Initial environment variables
+ *****************************************************************************/
+
+#define BOOT_TARGET_DEVICES(func)					\
+					func(USB, usb, 0)		\
+					func(MMC, mmc, 0)		\
+					func(DHCP, dhcp, na)
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_bootcmd.h>
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+			"loader_mmc_blknum=0x0\0"			\
+			"loader_mmc_nblks=0x780\0"			\
+			"env_mmc_blknum=0xf80\0"			\
+			"env_mmc_nblks=0x80\0"				\
+			"kernel_addr_r=0x30000000\0"			\
+			"pxefile_addr_r=0x32000000\0"			\
+			"scriptaddr=0x32000000\0"			\
+			"fdt_addr_r=0x32200000\0"			\
+			"fdtfile=hisilicon/hi3798cv200-poplar.dtb\0"	\
+			"ramdisk_addr_r=0x32400000\0"			\
+			BOOTENV
+
+
+/* Command line configuration */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		(0xf80 * 512) /* env_mmc_blknum bytes */
+#define CONFIG_ENV_SIZE			(0x80 * 512)  /* env_mmc_nblks bytes */
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512
+#define CONFIG_SYS_MAXARGS		64
+
+#endif /* _POPLAR_H_ */
diff --git a/include/configs/popmetal_rk3288.h b/include/configs/popmetal_rk3288.h
new file mode 100644
index 0000000..ddd7012
--- /dev/null
+++ b/include/configs/popmetal_rk3288.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3288_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/porter.h b/include/configs/porter.h
new file mode 100644
index 0000000..db42176
--- /dev/null
+++ b/include/configs/porter.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/configs/porter.h
+ *     This file is Porter board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#ifndef __PORTER_H
+#define __PORTER_H
+
+#include "rcar-gen2-common.h"
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
+#define STACK_AREA_SIZE			0x00100000
+#define LOW_LEVEL_MERAM_STACK \
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE		0x40000000
+#define RCAR_GEN2_SDRAM_SIZE		(2048u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(1024u * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SPI_FLASH_QUAD
+
+/* SH Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK	20000000u
+#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootm_size=0x10000000\0"
+
+/* SPL support */
+#define CONFIG_SPL_STACK		0xe6340000
+#define CONFIG_SPL_MAX_SIZE		0x4000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF0
+#define CONFIG_SH_SCIF_CLK_FREQ		65000000
+#endif
+
+#endif /* __PORTER_H */
diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h
new file mode 100644
index 0000000..4d6085d
--- /dev/null
+++ b/include/configs/puma_rk3399.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#ifndef __PUMA_RK3399_H
+#define __PUMA_RK3399_H
+
+#include <configs/rk3399_common.h>
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 1
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_SECT_SIZE		(8 * 1024)
+#endif
+
+#define SDRAM_BANK_SIZE			(2UL << 30)
+
+#define CONFIG_SERIAL_TAG
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+
+#endif
diff --git a/include/configs/pumpkin.h b/include/configs/pumpkin.h
new file mode 100644
index 0000000..b2dda64
--- /dev/null
+++ b/include/configs/pumpkin.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Pumpkin board
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com
+ */
+
+#ifndef __PUMPKIN_H
+#define __PUMPKIN_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_ENV_SIZE			SZ_4K
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M
+
+#define CONFIG_CPU_ARMV8
+#define COUNTER_FREQUENCY		13000000
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_COM1		0x11005000
+#define CONFIG_SYS_NS16550_CLK		26000000
+
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + SZ_2M - \
+						 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+/* Environment settings */
+#include <config_distro_bootcmd.h>
+
+#define MMCBOOT \
+	"mmcdev=0\0" \
+	"kernel_partition=2\0" \
+	"rootfs_partition=3\0" \
+	"mmc_discover_partition=" \
+		"part start mmc ${mmcdev} ${kernel_partition} kernel_part_addr;" \
+		"part size mmc ${mmcdev} ${kernel_partition} kernel_part_size;\0" \
+	"mmcboot=" \
+		"mmc dev ${mmcdev};" \
+		"run mmc_discover_partition;" \
+		"mmc read ${kerneladdr} ${kernel_part_addr} ${kernel_part_size};" \
+		"setenv bootargs ${bootargs} root=/dev/mmcblk${mmcdev}p${rootfs_partition} rootwait; " \
+		"bootm ${kerneladdr}; \0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kerneladdr=0x4A000000\0" \
+	MMCBOOT \
+	"bootcmd=run mmcboot;\0"
+
+#endif
diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h
new file mode 100644
index 0000000..e25800a
--- /dev/null
+++ b/include/configs/pxa-common.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Toradex Colibri PXA270 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#ifndef	__CONFIG_PXA_COMMON_H__
+#define	__CONFIG_PXA_COMMON_H__
+
+#define	CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+
+/*
+ * KGDB
+ */
+#ifdef	CONFIG_CMD_KGDB
+#define	CONFIG_KGDB_BAUDRATE		230400
+#endif
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef	CONFIG_CMD_MMC
+#define	CONFIG_PXA_MMC_GENERIC
+#endif
+
+/*
+ * OHCI USB
+ */
+#ifdef	CONFIG_CMD_USB
+#define	CONFIG_USB_OHCI_NEW
+#define	CONFIG_SYS_USB_OHCI_CPU_INIT
+#define	CONFIG_SYS_USB_OHCI_BOARD_INIT
+#ifdef CONFIG_CPU_PXA27X
+#define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
+#else
+#define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#endif
+#define	CONFIG_SYS_USB_OHCI_REGS_BASE		0x4c000000
+#define	CONFIG_SYS_USB_OHCI_SLOT_NAME		"pxa-ohci"
+#endif
+
+#endif	/* __CONFIG_PXA_COMMON_H__ */
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
new file mode 100644
index 0000000..543eb2d
--- /dev/null
+++ b/include/configs/pxm2.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * siemens pxm2
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef __CONFIG_PXM2_H
+#define __CONFIG_PXM2_H
+
+#define CONFIG_SIEMENS_MACH_TYPE	MACH_TYPE_PXM2
+
+#include "siemens-am33x-common.h"
+
+#define DDR_IOCTRL_VAL		0x18b
+#define DDR_PLL_FREQ		266
+
+#define BOARD_DFU_BUTTON_GPIO	59
+#define BOARD_LCD_POWER		111
+#define BOARD_BACK_LIGHT	112
+#define BOARD_TOUCH_POWER	57
+
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	"button_dfu0=59\0" \
+	"led0=117,0,1\0" \
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)	/* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+
+#define CONFIG_PHY_ATHEROS
+
+#define CONFIG_FACTORYSET
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Use common default */
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=pxm2\0" \
+	"ubi_off=2048\0"\
+	"nand_img_size=0x500000\0" \
+	"optargs=\0" \
+	"preboot=draco_led 0\0" \
+	CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	"splashpos=m,m\0"	\
+	CONFIG_ENV_SETTINGS_V1 \
+	CONFIG_ENV_SETTINGS_NAND_V1 \
+	"mmc_dev=0\0" \
+	"mmc_root=/dev/mmcblk0p2 rw\0" \
+	"mmc_root_fs_type=ext4 rootwait\0" \
+	"mmc_load_uimage=" \
+		"mmc rescan; " \
+		"setenv bootfile uImage;" \
+		"fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \
+	"loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"mmc_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv bootargs ${bootargs} " \
+		"root=${mmc_root} ${mtdparts}" \
+		"rootfstype=${mmc_root_fs_type} ip=${ip_method} " \
+		"eth=${ethaddr} " \
+		"\0" \
+	"mmc_boot=run mmc_args; " \
+		"run mmc_load_uimage; " \
+		"bootm ${kloadaddr}\0" \
+	""
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+
+#define CONFIG_BOOTCOMMAND \
+	"if dfubutton; then " \
+		"run dfu_start; " \
+		"reset; " \
+	"fi; " \
+	"if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmc_dev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run mmc_load_uimage; then " \
+			"run mmc_args;" \
+			"bootm ${kloadaddr};" \
+		"fi;" \
+	"fi;" \
+	"run nand_boot;" \
+	"reset;"
+
+#else
+
+#define CONFIG_BOOTCOMMAND			\
+	"setenv autoload no; "			\
+	"dhcp; "				\
+	"if tftp 80000000 debrick.scr; then "	\
+		"source 80000000; "		\
+	"fi"
+#endif
+#endif	/* CONFIG_SPL_BUILD */
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_VIDEO_DA8XX
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define DA8XX_LCD_CNTL_BASE	LCD_CNTL_BASE
+#define PWM_TICKS	0x1388
+#define PWM_DUTY	0x200
+#endif
+
+#endif	/* ! __CONFIG_PXM2_H */
diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h
new file mode 100644
index 0000000..c7aaafa
--- /dev/null
+++ b/include/configs/qemu-arm.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Tuomas Tynkkynen
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+/* Physical memory map */
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+/* The DTB generated by QEMU is placed at start of RAM, stay away from there */
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + SZ_2M)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+#define CONFIG_SYS_MALLOC_LEN		SZ_16M
+
+/* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */
+#define CONFIG_SYS_HZ                       1000
+
+/* Environment options */
+#define CONFIG_ENV_ADDR			0x4000000
+#define CONFIG_ENV_SIZE			SZ_256K
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(SCSI, scsi, 0) \
+	func(VIRTIO, virtio, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_addr=0x40000000\0" \
+	"scriptaddr=0x40200000\0" \
+	"pxefile_addr_r=0x40300000\0" \
+	"kernel_addr_r=0x40400000\0" \
+	"ramdisk_addr_r=0x44000000\0" \
+	BOOTENV
+
+#define CONFIG_SYS_CBSIZE 512
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_TFABOOT
+#define CONFIG_SYS_FLASH_BASE		0x4000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#else
+#define CONFIG_SYS_FLASH_BASE		0x0
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+#endif
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* Sector: 256K, Bank: 64M */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
new file mode 100644
index 0000000..1937829
--- /dev/null
+++ b/include/configs/qemu-mips.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_QEMU_MIPS
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"panic=1\0"						\
+	"bootfile=/tftpboot/vmlinux\0"				\
+	"load=tftp 80500000 ${u-boot}\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"bootp;bootelf"
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE	0xb4000300
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		115200
+#define CONFIG_SYS_NS16550_COM1		0xb40003f8
+
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_IDE_SWAP_IO
+#endif
+
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_BASE_ADDR	0xb4000000
+
+#define CONFIG_SYS_IDE_MAXDEVICE	4
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
+
+#define CONFIG_SYS_MHZ			132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+/* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x81000000
+
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+/* We boot from this flash, selected with dip switch */
+#define CONFIG_SYS_FLASH_BASE		0xbfc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
+
+#define CONFIG_ENV_OVERWRITE	1
+
+#define MEM_SIZE		128
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
new file mode 100644
index 0000000..fe384ec
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_QEMU_MIPS
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"panic=1\0"						\
+	"bootfile=/tftpboot/vmlinux\0"					\
+	"load=tftp ffffffff80500000 ${u-boot}\0"			\
+	""
+
+#define CONFIG_BOOTCOMMAND	"bootp;bootelf"
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE	0xffffffffb4000300
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		115200
+#define CONFIG_SYS_NS16550_COM1		0xffffffffb40003f8
+
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_IDE_SWAP_IO
+#endif
+
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_BASE_ADDR	0xffffffffb4000000
+
+#define CONFIG_SYS_IDE_MAXDEVICE	4
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
+
+#define CONFIG_SYS_MHZ			132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+/* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0xffffffff81000000
+
+#define CONFIG_SYS_MEMTEST_START	0xffffffff80100000
+#define CONFIG_SYS_MEMTEST_END		0xffffffff80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+/* We boot from this flash, selected with dip switch */
+#define CONFIG_SYS_FLASH_BASE		0xffffffffbfc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
+
+#define CONFIG_ENV_OVERWRITE	1
+
+#define MEM_SIZE		128
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
new file mode 100644
index 0000000..424235e
--- /dev/null
+++ b/include/configs/qemu-ppce500.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __QEMU_PPCE500_H
+#define __QEMU_PPCE500_H
+
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+
+#define CONFIG_SYS_RAMBOOT
+
+#define CONFIG_PCI1		1	/* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/* Needed to fill the ccsrbar pointer */
+
+/* Virtual address to CCSRBAR */
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+/* Physical address should be a function call */
+#ifndef __ASSEMBLY__
+extern unsigned long long get_phys_ccsrbar_addr_early(void);
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
+#endif
+
+/* Virtual address range for PCI region maps */
+#define CONFIG_SYS_PCI_MAP_START	0x80000000
+#define CONFIG_SYS_PCI_MAP_END		0xe8000000
+
+/* Virtual address to a temporary map if we need it (max 128MB) */
+#define CONFIG_SYS_TMPVIRT		0xe8000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_CHIP_SELECTS_PER_CTRL	0
+
+#define CONFIG_SYS_CLK_FREQ        33000000
+
+#define CONFIG_SYS_BOOT_BLOCK		0x00000000	/* boot TLB */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_INIT_RAM_ADDR		0x00100000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0x0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0x00100000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+#define CONFIG_LBA48
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTCOMMAND		\
+	"test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
+
+#endif	/* __QEMU_PPCE500_H */
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
new file mode 100644
index 0000000..fa9b9af
--- /dev/null
+++ b/include/configs/qemu-riscv.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE		0x00100000
+#define CONFIG_SPL_BSS_START_ADDR	0x84000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x84100000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	0x80200000
+
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_8M
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+#define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
+
+/* Environment options */
+#define CONFIG_ENV_SIZE			SZ_128K
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(QEMU, qemu, na) \
+	func(VIRTIO, virtio, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define BOOTENV_DEV_QEMU(devtypeu, devtypel, instance) \
+	"bootcmd_qemu=" \
+		"if env exists kernel_start; then " \
+			"bootm ${kernel_start} - ${fdtcontroladdr};" \
+		"fi;\0"
+
+#define BOOTENV_DEV_NAME_QEMU(devtypeu, devtypel, instance) \
+	"qemu "
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0xffffffffffffffff\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"kernel_addr_r=0x84000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"scriptaddr=0x88100000\0" \
+	"pxefile_addr_r=0x88200000\0" \
+	"ramdisk_addr_r=0x88300000\0" \
+	BOOTENV
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
new file mode 100644
index 0000000..c557420
--- /dev/null
+++ b/include/configs/qemu-x86.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(SCSI, scsi, 0) \
+	func(VIRTIO, virtio, 0) \
+	func(IDE, ide, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+#include <configs/x86-common.h>
+
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE			SZ_256K
+
+#define CONFIG_PREBOOT "pci enum"
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,i8042-kbd\0" \
+					"stdout=serial,vidconsole\0" \
+					"stderr=serial,vidconsole\0"
+
+/*
+ * ATA/SATA support for QEMU x86 targets
+ *   - Only legacy IDE controller is supported for QEMU '-M pc' target
+ *   - AHCI controller is supported for QEMU '-M q35' target
+ */
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	4
+#define CONFIG_SYS_ATA_BASE_ADDR	0
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_ALT_OFFSET	0
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
+#define CONFIG_ATAPI
+
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
new file mode 100644
index 0000000..0b16fb0
--- /dev/null
+++ b/include/configs/r2dplus.h
@@ -0,0 +1,69 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_CPU_SH7751	1
+#define __LITTLE_ENDIAN__	1
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* SCIF */
+#define CONFIG_CONS_SCIF1	1
+
+#define CONFIG_ENV_OVERWRITE	1
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x8C000000
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_PBSIZE		256
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/*
+ * NOR Flash ( Spantion S29GL256P )
+ */
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+#define CONFIG_SYS_MAX_FLASH_SECT  256
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_ENV_SECT_SIZE	0x40000
+#define CONFIG_ENV_SIZE        (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * SuperH Clock setting
+ */
+#define CONFIG_SYS_CLK_FREQ	60000000
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define	CONFIG_SYS_PLL_SETTLING_TIME	100/* in us */
+
+/*
+ * IDE support
+ */
+#define CONFIG_IDE_RESET	1
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1 /* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	0xb4000000
+#define CONFIG_SYS_ATA_STRIDE		2 /* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x1000	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x1000	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x800	/* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
+
+/*
+ * SuperH PCI Bridge Configration
+ */
+#define CONFIG_SH7751_PCI
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
new file mode 100644
index 0000000..6ea7f38
--- /dev/null
+++ b/include/configs/r7780mp.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Renesas R7780MP board
+ *
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ */
+
+#ifndef __R7780RP_H
+#define __R7780RP_H
+
+#define CONFIG_CPU_SH7780	1
+#define CONFIG_R7780MP		1
+#define CONFIG_SYS_R7780MP_OLD_FLASH	1
+#define __LITTLE_ENDIAN__ 1
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CONS_SCIF0	1
+
+#define CONFIG_ENV_OVERWRITE	1
+
+#define CONFIG_SYS_SDRAM_BASE		(0x08000000)
+#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
+
+#define CONFIG_SYS_PBSIZE		256
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
+
+/* Flash board support */
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
+/* NOR Flash (S29PL127J60TFI130) */
+# define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
+# define CONFIG_SYS_MAX_FLASH_BANKS	(2)
+# define CONFIG_SYS_MAX_FLASH_SECT	270
+# define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
+				CONFIG_SYS_FLASH_BASE + 0x100000,\
+				CONFIG_SYS_FLASH_BASE + 0x400000,\
+				CONFIG_SYS_FLASH_BASE + 0x700000, }
+#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
+/* NOR Flash (Spantion S29GL256P) */
+# define CONFIG_SYS_MAX_FLASH_BANKS	(1)
+# define CONFIG_SYS_MAX_FLASH_SECT		256
+# define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(1204 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_RX_ETH_BUFFER	(8)
+
+#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+
+/* PCI Controller */
+#if defined(CONFIG_CMD_PCI)
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7780_PCI
+#define CONFIG_SH7780_PCI_LSR	0x07f00001
+#define CONFIG_SH7780_PCI_LAR	CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SH7780_PCI_BAR	CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_PCI_SCAN_SHOW	1
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
+
+#define CONFIG_PCI_IO_BUS	0xFE200000	/* IO space base address */
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x00200000	/* Size of IO window */
+#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_BUS  CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
+#endif /* CONFIG_CMD_PCI */
+
+#if defined(CONFIG_CMD_NET)
+/* AX88796L Support(NE2000 base chip) */
+#define CONFIG_DRIVER_AX88796L
+#define CONFIG_DRIVER_NE2000_BASE	0xA4100000
+#endif
+
+/* Compact flash Support */
+#if defined(CONFIG_IDE)
+#define CONFIG_IDE_RESET        1
+#define CONFIG_SYS_PIO_MODE            1
+#define CONFIG_SYS_IDE_MAXBUS          1   /* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE       1
+#define CONFIG_SYS_ATA_BASE_ADDR       0xb4000000
+#define CONFIG_SYS_ATA_STRIDE          2               /* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET     0x1000          /* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET      0x1000          /* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET      0x800           /* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
+#endif /* CONFIG_IDE */
+
+#endif /* __R7780RP_H */
diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h
new file mode 100644
index 0000000..c69535a
--- /dev/null
+++ b/include/configs/rastaban.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef __CONFIG_RASTABAN_H
+#define __CONFIG_RASTABAN_H
+
+#include "siemens-am33x-common.h"
+
+#define DDR_PLL_FREQ	303
+
+/* FWD Button = 27
+ * SRV Button = 87 */
+#define BOARD_DFU_BUTTON_GPIO	27
+#define GPIO_LAN9303_NRST	88	/* GPIO2_24 = gpio88 */
+/* In dfu mode keep led1 on */
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	"button_dfu0=27\0" \
+	"button_dfu1=87\0" \
+	"led0=3,0,1\0" \
+	"led1=4,0,0\0" \
+	"led2=5,0,1\0" \
+	"led3=62,0,1\0" \
+	"led4=60,0,1\0" \
+	"led5=63,0,1\0"
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* Define own nand partitions */
+#define CONFIG_ENV_OFFSET_REDUND	0x2E0000
+#define CONFIG_ENV_SIZE_REDUND		0x2000
+#define CONFIG_ENV_RANGE		(4 * CONFIG_SYS_ENV_SECT_SIZE)
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=rastaban\0" \
+	"ubi_off=2048\0"\
+	"nand_img_size=0x400000\0" \
+	"optargs=\0" \
+	"preboot=draco_led 0\0" \
+	CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	CONFIG_ENV_SETTINGS_V2 \
+	CONFIG_ENV_SETTINGS_NAND_V2
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+	"run dfu_start; " \
+	"reset; " \
+"fi;" \
+"run nand_boot;" \
+"run nand_boot_backup;" \
+"reset;"
+
+#else
+
+#define CONFIG_BOOTCOMMAND			\
+	"setenv autoload no; "			\
+	"dhcp; "				\
+	"if tftp 80000000 debrick.scr; then "	\
+		"source 80000000; "		\
+	"fi"
+#endif
+#endif	/* CONFIG_SPL_BUILD */
+#endif	/* ! __CONFIG_RASTABAN_H */
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
new file mode 100644
index 0000000..71a5909
--- /dev/null
+++ b/include/configs/rcar-gen2-common.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/configs/rcar-gen2-common.h
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ */
+
+#ifndef __RCAR_GEN2_COMMON_H
+#define __RCAR_GEN2_COMMON_H
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_TARGET	"spl/u-boot-spl.srec"
+#endif
+
+#ifndef CONFIG_PINCTRL_PFC
+#define CONFIG_SH_GPIO_PFC
+#endif
+
+/* console */
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
+
+#define CONFIG_SYS_SDRAM_BASE		(RCAR_GEN2_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(RCAR_GEN2_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		0x50000000
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_ADDR	0xC0000
+
+/* Common ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+
+/* SF MTD */
+#if defined(CONFIG_SPI_FLASH_MTD) && !defined(CONFIG_SPL_BUILD)
+#else
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#undef CONFIG_SPI_FLASH_MTD
+#endif
+
+/* Timer */
+#define CONFIG_TMU_TIMER
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
+#define CONFIG_SYS_TIMER_RATE		(CONFIG_SYS_CLK_FREQ / 8)
+
+#endif	/* __RCAR_GEN2_COMMON_H */
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
new file mode 100644
index 0000000..95bd97c
--- /dev/null
+++ b/include/configs/rcar-gen3-common.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/rcar-gen3-common.h
+ *	This file is R-Car Gen3 common configuration file.
+ *
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
+ */
+
+#ifndef __RCAR_GEN3_COMMON_H
+#define __RCAR_GEN3_COMMON_H
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_REMAKE_ELF
+
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_TARGET	"spl/u-boot-spl.scif"
+#endif
+
+/* boot option */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* Generic Interrupt Controller Definitions */
+#define CONFIG_GICV2
+#define GICD_BASE	0xF1010000
+#define GICC_BASE	0xF1020000
+
+/* console */
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 38400 }
+
+/* MEMORY */
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+#define DRAM_RSV_SIZE			0x08000000
+#define CONFIG_SYS_SDRAM_BASE		(0x40000000 + DRAM_RSV_SIZE)
+#define CONFIG_SYS_SDRAM_SIZE		(0x80000000u - DRAM_RSV_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		0x58000000
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED		(0x80000000u - DRAM_RSV_SIZE)
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN		(64 << 20)
+
+/* ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootm_size=0x10000000\0"
+
+#define CONFIG_BOOTCOMMAND	\
+	"tftp 0x48080000 Image; " \
+	"tftp 0x48000000 Image-"CONFIG_DEFAULT_FDT_FILE"; " \
+	"booti 0x48080000 - 0x48000000"
+
+/* SPL support */
+#if defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796) || defined(CONFIG_R8A77965)
+#define CONFIG_SPL_BSS_START_ADDR	0xe633f000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000
+#else
+#define CONFIG_SPL_BSS_START_ADDR	0xe631f000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000
+#endif
+#define CONFIG_SPL_STACK		0xe6304000
+#define CONFIG_SPL_MAX_SIZE		0x7000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF2
+#define CONFIG_SH_SCIF_CLK_FREQ		65000000
+#endif
+
+#endif	/* __RCAR_GEN3_COMMON_H */
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
new file mode 100644
index 0000000..7f148ef
--- /dev/null
+++ b/include/configs/rk3036_common.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ */
+#ifndef __CONFIG_RK3036_COMMON_H
+#define __CONFIG_RK3036_COMMON_H
+
+#include <asm/arch-rockchip/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_ROCKCHIP_STIMER_BASE	0x200440a0
+#define COUNTER_FREQUENCY		24000000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK		24000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x60100000
+#define CONFIG_SYS_LOAD_ADDR		0x60800800
+#define CONFIG_SPL_STACK		0x10081fff
+
+#define CONFIG_ROCKCHIP_MAX_INIT_SIZE	(4 << 10)
+#define CONFIG_ROCKCHIP_CHIP_TAG	"RK30"
+
+#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define SDRAM_BANK_SIZE			(512UL << 20UL)
+#define SDRAM_MAX_SIZE                  (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
+
+#ifndef CONFIG_SPL_BUILD
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x60000000\0" \
+	"pxefile_addr_r=0x60100000\0" \
+	"fdt_addr_r=0x61f00000\0" \
+	"kernel_addr_r=0x62000000\0" \
+	"ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+
+/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
+ * so limit the fdt reallocation to that */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_high=0x7fffffff\0" \
+	"partitions=" PARTS_DEFAULT \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTENV
+#endif
+
+#endif
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
new file mode 100644
index 0000000..d0c9e5c
--- /dev/null
+++ b/include/configs/rk3128_common.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_RK3128_COMMON_H
+#define __CONFIG_RK3128_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_ROCKCHIP_STIMER_BASE	0x200440a0
+#define COUNTER_FREQUENCY		24000000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK		24000000
+
+#define CONFIG_IRAM_BASE		0x10080000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x60100000
+#define CONFIG_SYS_LOAD_ADDR		0x60800800
+
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* 64M */
+
+/* RAW SD card / eMMC locations. */
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define SDRAM_MAX_SIZE			0x80000000
+
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     1
+
+#ifndef CONFIG_SPL_BUILD
+
+/* usb mass storage */
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x60500000\0" \
+	"pxefile_addr_r=0x60600000\0" \
+	"fdt_addr_r=0x61f00000\0" \
+	"kernel_addr_r=0x62000000\0" \
+	"ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"partitions=" PARTS_DEFAULT \
+	BOOTENV
+
+#endif
+
+#endif
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
new file mode 100644
index 0000000..3bcc048
--- /dev/null
+++ b/include/configs/rk3188_common.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_RK3188_COMMON_H
+#define __CONFIG_RK3188_COMMON_H
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#include <asm/arch-rockchip/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#define CONFIG_SYS_CBSIZE		1024
+
+#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
+/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
+#endif
+#define CONFIG_SYS_INIT_SP_ADDR		0x60100000
+#define CONFIG_SYS_LOAD_ADDR		0x60800800
+
+#define CONFIG_ROCKCHIP_MAX_INIT_SIZE	(0x8000 - 0x800)
+#define CONFIG_ROCKCHIP_CHIP_TAG	"RK31"
+#define CONFIG_IRAM_BASE	0x10080000
+
+/* spl size 32kb sram - 2kb bootrom */
+#define CONFIG_SPL_MAX_SIZE		(0x8000 - 0x800)
+#define CONFIG_ROCKCHIP_SERIAL		1
+
+#define CONFIG_SPL_STACK		0x10087fff
+
+#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define SDRAM_BANK_SIZE			(2UL << 30)
+#define SDRAM_MAX_SIZE			0x80000000
+
+#ifndef CONFIG_SPL_BUILD
+/* usb otg */
+
+/* usb host support */
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x60000000\0" \
+	"pxefile_addr_r=0x60100000\0" \
+	"fdt_addr_r=0x61f00000\0" \
+	"kernel_addr_r=0x62000000\0" \
+	"ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+
+/* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
+ * so limit the fdt reallocation to that */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_high=0x6fffffff\0" \
+	"initrd_high=0x6fffffff\0" \
+	"partitions=" PARTS_DEFAULT \
+	ENV_MEM_LAYOUT_SETTINGS \
+	ROCKCHIP_DEVICE_SETTINGS \
+	BOOTENV
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
new file mode 100644
index 0000000..7e0c831
--- /dev/null
+++ b/include/configs/rk322x_common.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+#ifndef __CONFIG_RK322X_COMMON_H
+#define __CONFIG_RK322X_COMMON_H
+
+#include <asm/arch-rockchip/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/*  64M */
+
+#define CONFIG_ROCKCHIP_STIMER_BASE	0x110d0020
+#define COUNTER_FREQUENCY		24000000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK		24000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x61100000
+#define CONFIG_SYS_LOAD_ADDR		0x61800800
+#define CONFIG_SPL_MAX_SIZE		0x100000
+
+#define CONFIG_ROCKCHIP_MAX_INIT_SIZE	(28 << 10)
+#define CONFIG_ROCKCHIP_CHIP_TAG	"RK32"
+#define CONFIG_IRAM_BASE		0x10080000
+
+#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define SDRAM_BANK_SIZE			(512UL << 20UL)
+#define SDRAM_MAX_SIZE			0x80000000
+
+#ifndef CONFIG_SPL_BUILD
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x60000000\0" \
+	"pxefile_addr_r=0x60100000\0" \
+	"fdt_addr_r=0x61f00000\0" \
+	"kernel_addr_r=0x62000000\0" \
+	"ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+
+/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
+ * so limit the fdt reallocation to that */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_high=0x7fffffff\0" \
+	"partitions=" PARTS_DEFAULT \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTENV
+#endif
+
+#endif
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
new file mode 100644
index 0000000..910fe58
--- /dev/null
+++ b/include/configs/rk3288_common.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_RK3288_COMMON_H
+#define __CONFIG_RK3288_COMMON_H
+
+#include <asm/arch-rockchip/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_BOOTM_LEN		(64 << 20) /* 64MB */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#define CONFIG_SYS_CBSIZE		1024
+
+#define CONFIG_ROCKCHIP_STIMER_BASE	0xff810020
+#define COUNTER_FREQUENCY		24000000
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK		24000000
+
+#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
+/* Bootrom will load u-boot binary to 0x0 once return from SPL */
+#endif
+#define CONFIG_SYS_INIT_SP_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00800800
+#define CONFIG_SPL_STACK		0xff718000
+
+#define CONFIG_IRAM_BASE		0xff700000
+
+/* RAW SD card / eMMC locations. */
+
+/* FAT sd card locations. */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+
+#define CONFIG_SYS_SDRAM_BASE		0
+#define SDRAM_BANK_SIZE			(2UL << 30)
+#define SDRAM_MAX_SIZE			0xfe000000
+
+#define CONFIG_SYS_MONITOR_LEN (600 * 1024)
+
+#ifndef CONFIG_SPL_BUILD
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x00000000\0" \
+	"pxefile_addr_r=0x00100000\0" \
+	"fdt_addr_r=0x01f00000\0" \
+	"kernel_addr_r=0x02000000\0" \
+	"ramdisk_addr_r=0x04000000\0"
+
+#include <config_distro_bootcmd.h>
+
+/* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so
+ * limit the fdt reallocation to that */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0x0fffffff\0" \
+	"initrd_high=0x0fffffff\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"partitions=" PARTS_DEFAULT \
+	ENV_MEM_LAYOUT_SETTINGS \
+	ROCKCHIP_DEVICE_SETTINGS \
+	BOOTENV
+#endif
+
+#endif
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
new file mode 100644
index 0000000..3ff3331
--- /dev/null
+++ b/include/configs/rk3328_common.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_RK3328_COMMON_H
+#define __CONFIG_RK3328_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_IRAM_BASE		0xff090000
+
+#define CONFIG_ROCKCHIP_STIMER_BASE    0xff1d0020
+
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x00300000
+#define CONFIG_SYS_LOAD_ADDR		0x00800800
+#define CONFIG_SPL_STACK		0x00400000
+#define CONFIG_SPL_MAX_SIZE		0x100000
+#define CONFIG_SPL_BSS_START_ADDR	0x2000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x2000
+
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* 64M */
+
+/* FAT sd card locations. */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SYS_SDRAM_BASE		0
+#define SDRAM_MAX_SIZE			0xff000000
+
+#ifndef CONFIG_SPL_BUILD
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x00500000\0" \
+	"pxefile_addr_r=0x00600000\0" \
+	"fdt_addr_r=0x01f00000\0" \
+	"kernel_addr_r=0x02080000\0" \
+	"ramdisk_addr_r=0x04000000\0"
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"partitions=" PARTS_DEFAULT \
+	BOOTENV
+
+#endif
+
+/* rockchip ohci host driver */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+
+#endif
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
new file mode 100644
index 0000000..e4b2114
--- /dev/null
+++ b/include/configs/rk3368_common.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Andreas Färber
+ */
+
+#ifndef __CONFIG_RK3368_COMMON_H
+#define __CONFIG_RK3368_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#include <asm/arch-rockchip/hardware.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_SDRAM_BASE		0
+#define SDRAM_MAX_SIZE			0xff000000
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_ROCKCHIP_STIMER_BASE	0xff830020
+#define COUNTER_FREQUENCY		24000000
+
+#define CONFIG_IRAM_BASE		0xff8c0000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x00300000
+#define CONFIG_SYS_LOAD_ADDR		0x00280000
+
+#define CONFIG_SPL_MAX_SIZE             0x60000
+#define CONFIG_SPL_BSS_START_ADDR       0x400000
+#define CONFIG_SPL_BSS_MAX_SIZE         0x20000
+#define CONFIG_SPL_STACK                0x00188000
+
+#ifndef CONFIG_SPL_BUILD
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x00500000\0" \
+	"pxefile_addr_r=0x00600000\0" \
+	"fdt_addr_r=0x5600000\0" \
+	"kernel_addr_r=0x280000\0" \
+	"ramdisk_addr_r=0x5bf0000\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+	ENV_MEM_LAYOUT_SETTINGS	\
+	BOOTENV
+
+#endif
+
+#endif
diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
new file mode 100644
index 0000000..126c347
--- /dev/null
+++ b/include/configs/rk3399_common.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_RK3399_COMMON_H
+#define __CONFIG_RK3399_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define COUNTER_FREQUENCY               24000000
+#define CONFIG_ROCKCHIP_STIMER_BASE	0xff8680a0
+
+#define CONFIG_IRAM_BASE		0xff8c0000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x00300000
+#define CONFIG_SYS_LOAD_ADDR		0x00800800
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT)
+#define CONFIG_SPL_STACK		0x00400000
+#define CONFIG_SPL_MAX_SIZE             0x100000
+#define CONFIG_SPL_BSS_START_ADDR	0x00400000
+#define CONFIG_SPL_BSS_MAX_SIZE         0x2000
+#else
+#define CONFIG_SPL_STACK		0xff8effff
+#define CONFIG_SPL_MAX_SIZE		0x30000 - 0x2000
+/*  BSS setup */
+#define CONFIG_SPL_BSS_START_ADDR       0xff8e0000
+#define CONFIG_SPL_BSS_MAX_SIZE         0x10000
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* 64M */
+
+/* MMC/SD IP block */
+#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ	200000000
+
+/* RAW SD card / eMMC locations. */
+
+/* FAT sd card locations. */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SYS_SDRAM_BASE		0
+#define SDRAM_MAX_SIZE			0xf8000000
+
+#ifndef CONFIG_SPL_BUILD
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x00500000\0" \
+	"pxefile_addr_r=0x00600000\0" \
+	"fdt_addr_r=0x01f00000\0" \
+	"kernel_addr_r=0x02080000\0" \
+	"ramdisk_addr_r=0x04000000\0"
+
+#ifndef ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS
+#endif
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"partitions=" PARTS_DEFAULT \
+	ROCKCHIP_DEVICE_SETTINGS \
+	BOOTENV
+
+#endif
+
+/* enable usb config for usb ether */
+
+#endif
diff --git a/include/configs/rock.h b/include/configs/rock.h
new file mode 100644
index 0000000..d917757
--- /dev/null
+++ b/include/configs/rock.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3188_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/rock2.h b/include/configs/rock2.h
new file mode 100644
index 0000000..917caf4
--- /dev/null
+++ b/include/configs/rock2.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdin=serial,cros-ec-keyb\0" \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3288_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h
new file mode 100644
index 0000000..746d24c
--- /dev/null
+++ b/include/configs/rock960_rk3399.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#ifndef __ROCK960_RK3399_H
+#define __ROCK960_RK3399_H
+
+#include <configs/rk3399_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV		1
+
+#define SDRAM_BANK_SIZE			(2UL << 30)
+
+#endif
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
new file mode 100644
index 0000000..68e1105
--- /dev/null
+++ b/include/configs/rockchip-common.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _ROCKCHIP_COMMON_H_
+#define _ROCKCHIP_COMMON_H_
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_NS16550_MEM32
+
+#ifndef CONFIG_SPL_BUILD
+
+/* First try to boot from SD (index 0), then eMMC (index 1) */
+#if CONFIG_IS_ENABLED(CMD_MMC)
+	#define BOOT_TARGET_MMC(func) \
+		func(MMC, mmc, 0) \
+		func(MMC, mmc, 1)
+#else
+	#define BOOT_TARGET_MMC(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_USB)
+	#define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+	#define BOOT_TARGET_USB(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_PXE)
+	#define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+	#define BOOT_TARGET_PXE(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_DHCP)
+	#define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
+#else
+	#define BOOT_TARGET_DHCP(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_MMC(func) \
+	BOOT_TARGET_USB(func) \
+	BOOT_TARGET_PXE(func) \
+	BOOT_TARGET_DHCP(func)
+
+#ifdef CONFIG_ARM64
+#define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0"
+#else
+#define ROOT_UUID "69DAD710-2CE4-4E3C-B16C-21A1D49ABED3;\0"
+#endif
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \
+	"name=loader2,start=8MB,size=4MB,uuid=${uuid_gpt_loader2};" \
+	"name=trust,size=4M,uuid=${uuid_gpt_atf};" \
+	"name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \
+	"name=rootfs,size=-,uuid="ROOT_UUID
+
+#endif
+
+#endif /* _ROCKCHIP_COMMON_H_ */
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
new file mode 100644
index 0000000..77d2d54
--- /dev/null
+++ b/include/configs/rpi.h
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2012-2016 Stephen Warren
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include <asm/arch/timer.h>
+
+#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* Architecture, CPU, etc.*/
+
+/* Use SoC timer for AArch32, but architected timer for AArch64 */
+#ifndef CONFIG_ARM64
+#define CONFIG_SYS_TIMER_RATE		1000000
+#define CONFIG_SYS_TIMER_COUNTER	\
+	(&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
+#endif
+
+/*
+ * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
+ * so 2708 has historically been used rather than a dedicated 2835 ID.
+ *
+ * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
+ * chose to use someone else's previously registered machine ID (3139, MX51_GGC)
+ * rather than obtaining a valid ID:-/
+ *
+ * For the bcm2837, hopefully a machine type is not needed, since everything
+ * is DT.
+ */
+#ifdef CONFIG_BCM2835
+#define CONFIG_MACH_TYPE		MACH_TYPE_BCM2708
+#endif
+
+/* Memory layout */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
+/*
+ * The board really has 256M. However, the VC (VideoCore co-processor) shares
+ * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
+ * smaller amount of RAM is present in order to avoid stomping on the area
+ * the VC uses.
+ */
+#define CONFIG_SYS_SDRAM_SIZE		SZ_128M
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M
+#define CONFIG_SYS_MEMTEST_START	0x00100000
+#define CONFIG_SYS_MEMTEST_END		0x00200000
+#define CONFIG_LOADADDR			0x00200000
+
+#ifdef CONFIG_ARM64
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+#endif
+
+/* Devices */
+/* GPIO */
+#define CONFIG_BCM2835_GPIO
+/* LCD */
+#define CONFIG_LCD_DT_SIMPLEFB
+#define CONFIG_VIDEO_BCM2835
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_TFTP_TSIZE
+#endif
+
+/* Console configuration */
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Environment */
+#define CONFIG_ENV_SIZE			SZ_16K
+#define CONFIG_SYS_LOAD_ADDR		0x1000000
+
+/* Shell */
+
+/* ATAGs support for bootm/bootz */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+/* Environment */
+#define ENV_DEVICE_SETTINGS \
+	"stdin=serial,usbkbd\0" \
+	"stdout=serial,vidconsole\0" \
+	"stderr=serial,vidconsole\0"
+
+#ifdef CONFIG_ARM64
+#define FDT_HIGH "ffffffffffffffff"
+#define INITRD_HIGH "ffffffffffffffff"
+#else
+#define FDT_HIGH "ffffffff"
+#define INITRD_HIGH "ffffffff"
+#endif
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this.
+ *
+ * Older versions of the boot firmware place the firmware-loaded DTB at 0x100,
+ * newer versions place it in high memory. So prevent U-Boot from doing its own
+ * DTB + initrd relocation so that we won't accidentally relocate the initrd
+ * over the firmware-loaded DTB and generally try to lay out things starting
+ * from the bottom of RAM.
+ *
+ * kernel_addr_r has different constraints on ARM and Aarch64.  For 32-bit ARM,
+ * it must be within the first 128M of RAM in order for the kernel's
+ * CONFIG_AUTO_ZRELADDR option to work. The kernel itself will be decompressed
+ * to 0x8000 but the decompressor clobbers 0x4000-0x8000 as well. The
+ * decompressor also likes to relocate itself to right past the end of the
+ * decompressed kernel, so in total the sum of the compressed and and
+ * decompressed kernel needs to be reserved.
+ *
+ *   For Aarch64, the kernel image is uncompressed and must be loaded at
+ *   text_offset bytes (specified in the header of the Image) into a 2MB
+ *   boundary. The 'booti' command relocates the image if necessary. Linux uses
+ *   a default text_offset of 0x80000.  In summary, loading at 0x80000
+ *   satisfies all these constraints and reserving memory up to 0x02400000
+ *   permits fairly large (roughly 36M) kernels.
+ *
+ * scriptaddr and pxefile_addr_r can be pretty much anywhere that doesn't
+ * conflict with something else. Reserving 1M for each of them at
+ * 0x02400000-0x02500000 and 0x02500000-0x02600000 should be plenty.
+ *
+ * On ARM, both the DTB and any possible initrd must be loaded such that they
+ * fit inside the lowmem mapping in Linux. In practice, this usually means not
+ * more than ~700M away from the start of the kernel image but this number can
+ * be larger OR smaller depending on e.g. the 'vmalloc=xxxM' command line
+ * parameter given to the kernel. So reserving memory from low to high
+ * satisfies this constraint again. Reserving 1M at 0x02600000-0x02700000 for
+ * the DTB leaves rest of the free RAM to the initrd starting at 0x02700000.
+ * Even with the smallest possible CPU-GPU memory split of the CPU getting
+ * only 64M, the remaining 25M starting at 0x02700000 should allow quite
+ * large initrds before they start colliding with U-Boot.
+ */
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"fdt_high=" FDT_HIGH "\0" \
+	"initrd_high=" INITRD_HIGH "\0" \
+	"kernel_addr_r=0x00080000\0" \
+	"scriptaddr=0x02400000\0" \
+	"pxefile_addr_r=0x02500000\0" \
+	"fdt_addr_r=0x02600000\0" \
+	"ramdisk_addr_r=0x02700000\0"
+
+#if CONFIG_IS_ENABLED(CMD_MMC)
+	#define BOOT_TARGET_MMC(func) \
+		func(MMC, mmc, 0) \
+		func(MMC, mmc, 1)
+#else
+	#define BOOT_TARGET_MMC(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_USB)
+	#define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+	#define BOOT_TARGET_USB(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_PXE)
+	#define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+	#define BOOT_TARGET_PXE(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_DHCP)
+	#define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
+#else
+	#define BOOT_TARGET_DHCP(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_MMC(func) \
+	BOOT_TARGET_USB(func) \
+	BOOT_TARGET_PXE(func) \
+	BOOT_TARGET_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \
+	ENV_DEVICE_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTENV
+
+
+#endif
diff --git a/include/configs/rut.h b/include/configs/rut.h
new file mode 100644
index 0000000..296bdc2
--- /dev/null
+++ b/include/configs/rut.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * siemens rut
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef __CONFIG_RUT_H
+#define __CONFIG_RUT_H
+
+#define CONFIG_SIEMENS_MACH_TYPE	MACH_TYPE_RUT
+
+#include "siemens-am33x-common.h"
+
+#define RUT_IOCTRL_VAL	0x18b
+#define DDR_PLL_FREQ	303
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20) /* 256 MiB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
+
+#define CONFIG_PHY_NATSEMI
+
+#define CONFIG_FACTORYSET
+
+/* Watchdog */
+#define WATCHDOG_TRIGGER_GPIO	14
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Use common default */
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=rut\0" \
+	"ubi_off=2048\0"\
+	"nand_img_size=0x500000\0" \
+	"splashpos=m,m\0" \
+	"optargs=fixrtc --no-log consoleblank=0 \0" \
+	CONFIG_ENV_SETTINGS_V1 \
+	CONFIG_ENV_SETTINGS_NAND_V1 \
+	"mmc_dev=0\0" \
+	"mmc_root=/dev/mmcblk0p2 rw\0" \
+	"mmc_root_fs_type=ext4 rootwait\0" \
+	"mmc_load_uimage=" \
+		"mmc rescan; " \
+		"setenv bootfile uImage;" \
+		"fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \
+	"loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"mmc_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv bootargs ${bootargs} " \
+		"root=${mmc_root} ${mtdparts}" \
+		"rootfstype=${mmc_root_fs_type} ip=${ip_method} " \
+		"eth=${ethaddr} " \
+		"\0" \
+	"mmc_boot=run mmc_args; " \
+		"run mmc_load_uimage; " \
+		"bootm ${kloadaddr}\0" \
+	""
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmc_dev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run mmc_load_uimage; then " \
+			"run mmc_args;" \
+			"bootm ${kloadaddr};" \
+		"fi;" \
+	"fi;" \
+	"run nand_boot;" \
+	"reset;"
+
+#else
+
+#define CONFIG_BOOTCOMMAND			\
+	"setenv autoload no; "			\
+	"dhcp; "				\
+	"if tftp 80000000 debrick.scr; then "	\
+		"source 80000000; "		\
+	"fi"
+#endif
+
+#endif /* CONFIG_SPL_BUILD */
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_VIDEO_DA8XX
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define DA8XX_LCD_CNTL_BASE	LCD_CNTL_BASE
+
+#define BOARD_LCD_RESET		115	/* Bank 3 pin 19 */
+#define CONFIG_FORMIKE
+#define DISPL_PLL_SPREAD_SPECTRUM
+#endif
+
+#endif	/* ! __CONFIG_RUT_H */
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
new file mode 100644
index 0000000..758e85e
--- /dev/null
+++ b/include/configs/rv1108_common.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+#ifndef __CONFIG_RV1108_COMMON_H
+#define __CONFIG_RV1108_COMMON_H
+
+#include <asm/arch-rockchip/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_IRAM_BASE		0x10080000
+
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
+/* TIMER1,initialized by ddr initialize code */
+#define CONFIG_SYS_TIMER_BASE		0x10350020
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
+
+#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x100000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x2000000)
+
+/* rockchip ohci host driver */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x60000000\0" \
+	"fdt_addr_r=0x61f00000\0" \
+	"kernel_addr_r=0x62000000\0" \
+	"ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"partitions=" PARTS_DEFAULT \
+	BOOTENV
+#endif
diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h
new file mode 100644
index 0000000..cc6d920
--- /dev/null
+++ b/include/configs/s32v234evb.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale S32V234 EVB board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_S32V234
+
+/* Config GIC */
+#define CONFIG_GICV2
+#define GICD_BASE 0x7D001000
+#define GICC_BASE 0x7D002000
+
+#define CONFIG_REMAKE_ELF
+#undef CONFIG_RUN_FROM_IRAM_ONLY
+
+#define CONFIG_RUN_FROM_DDR1
+#undef CONFIG_RUN_FROM_DDR0
+
+/* Run by default from DDR1  */
+#ifdef CONFIG_RUN_FROM_DDR0
+#define DDR_BASE_ADDR		0x80000000
+#else
+#define DDR_BASE_ADDR		0xC0000000
+#endif
+
+#define CONFIG_MACH_TYPE		4146
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Config CACHE */
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_SYS_FULL_VA
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+/* SMP Spin Table Definitions */
+#define CPU_RELEASE_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY               (1000000000)	/* 1000MHz */
+#define CONFIG_SYS_FSL_ERRATUM_A008585
+
+/* Size of malloc() pool */
+#ifdef CONFIG_RUN_FROM_IRAM_ONLY
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1 * 1024 * 1024)
+#else
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#endif
+
+#define LINFLEXUART_BASE		LINFLEXD0_BASE_ADDR
+
+#define CONFIG_DEBUG_UART_LINFLEXUART
+#define CONFIG_DEBUG_UART_BASE		LINFLEXUART_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_UART_PORT		(1)
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC_BASE_ADDR
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_CMD_MMC
+/* #define CONFIG_CMD_EXT2 EXT2 Support */
+
+#if 0
+
+/* Ethernet config */
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE            ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE     RMII
+#define CONFIG_FEC_MXC_PHYADDR  0
+#endif
+
+#if 0				/* Disable until the FLASH will be implemented */
+#define CONFIG_SYS_USE_NAND
+#endif
+
+#ifdef CONFIG_SYS_USE_NAND
+/* Nand Flash Configs */
+#define CONFIG_JFFS2_NAND
+#define MTD_NAND_FSL_NFC_SWECC 1
+#define CONFIG_NAND_FSL_NFC
+#define CONFIG_SYS_NAND_BASE		0x400E0000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE
+#define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
+#endif
+
+#define CONFIG_LOADADDR			0xC307FFC0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"boot_scripts=boot.scr.uimg boot.scr\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	"console=ttyLF0,115200\0" \
+	"fdt_file=s32v234-evb.dtb\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_addr_r=0xC2000000\0" \
+	"kernel_addr_r=0xC307FFC0\0" \
+	"ramdisk_addr_r=0xC4000000\0" \
+	"ramdisk=rootfs.uimg\0"\
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \
+	"jtagboot=echo Booting using jtag...; " \
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+	"jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \
+		"run loaduimage; run loadramdisk; run loadfdt;"\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+	"boot_net_usb_start=true\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
+
+#define CONFIG_BOOTCOMMAND \
+	"run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_PROMPT		"=> "
+
+#define CONFIG_SYS_MEMTEST_START	(DDR_BASE_ADDR)
+#define CONFIG_SYS_MEMTEST_END		(DDR_BASE_ADDR + 0x7C00000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ				1000
+
+#ifdef CONFIG_RUN_FROM_IRAM_ONLY
+#define CONFIG_SYS_MALLOC_BASE		(DDR_BASE_ADDR)
+#endif
+
+#if 0
+/* Configure PXE */
+#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
+#endif
+
+/* Physical memory map */
+/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */
+#define PHYS_SDRAM			(DDR_BASE_ADDR)
+#define PHYS_SDRAM_SIZE			(256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#endif
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
new file mode 100644
index 0000000..be6f011
--- /dev/null
+++ b/include/configs/s5p_goni.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG Universal (s5pc100) board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
+#define CONFIG_S5P		1	/* which is in a S5P Family */
+#define CONFIG_S5PC110		1	/* which is in a S5PC110 */
+
+#include <linux/sizes.h>
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+/* input clock of PLL: has 24MHz input clock at S5PC110 */
+#define CONFIG_SYS_CLK_FREQ_C110	24000000
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE		0x30000000
+
+/* Text Base */
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_INITRD_TAG
+
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
+
+/*
+ * select serial console configuration
+ */
+
+/* MMC */
+#define SDHCI_MAX_HOSTS		4
+
+/* PWM */
+#define CONFIG_PWM			1
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+/* USB Samsung's IDs */
+
+#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
+#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
+
+/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
+
+/* partitions definitions */
+#define PARTS_CSA			"csa-mmc"
+#define PARTS_BOOTLOADER	"u-boot"
+#define PARTS_BOOT			"boot"
+#define PARTS_ROOT			"platform"
+#define PARTS_DATA			"data"
+#define PARTS_CSC			"csc"
+#define PARTS_UMS			"ums"
+
+#define CONFIG_DFU_ALT \
+	"u-boot raw 0x80 0x400;" \
+	"uImage ext4 0 2;" \
+	"exynos3-goni.dtb ext4 0 2;" \
+	""PARTS_ROOT" part 0 5\0"
+
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+	"name="PARTS_BOOTLOADER",size=60MiB," \
+	"uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
+	"name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+	"name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+	"name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
+
+#define CONFIG_BOOTCOMMAND	"run mmcboot"
+
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC2,115200n8\0"
+
+#define CONFIG_RAMDISK_BOOT	"root=/dev/ram0 rw rootfstype=ext4" \
+		" ${console} ${meminfo}"
+
+#define CONFIG_COMMON_BOOT	"${console} ${meminfo} ${mtdparts}"
+
+#define CONFIG_UPDATEB	"updateb=onenand erase 0x0 0x100000;" \
+			" onenand write 0x32008000 0x0 0x100000\0"
+
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_UPDATEB \
+	"updatek=" \
+		"onenand erase 0xc00000 0x600000;" \
+		"onenand write 0x31008000 0xc00000 0x600000\0" \
+	"updateu=" \
+		"onenand erase 0x01560000 0x1eaa0000;" \
+		"onenand write 0x32000000 0x1260000 0x8C0000\0" \
+	"bootk=" \
+		"run loaduimage;" \
+		"bootm 0x30007FC0\0" \
+	"flashboot=" \
+		"set bootargs root=/dev/mtdblock${bootblock} " \
+		"rootfstype=${rootfstype} ${opts} " \
+		"${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \
+	"ubifsboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		"${opts} ${lcdinfo} " \
+		CONFIG_COMMON_BOOT "; run bootk\0" \
+	"tftpboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		"${opts} ${lcdinfo} " CONFIG_COMMON_BOOT \
+		"; tftp 0x30007FC0 uImage; bootm 0x30007FC0\0" \
+	"ramboot=" \
+		"set bootargs " CONFIG_RAMDISK_BOOT \
+		"initrd=0x33000000,8M ramdisk=8192\0" \
+	"mmcboot=" \
+		"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+		"rootfstype=${rootfstype} ${opts} ${lcdinfo} " \
+		CONFIG_COMMON_BOOT "; run bootk\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
+	"verify=n\0" \
+	"rootfstype=ext4\0" \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+	"meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \
+	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \
+	"mmcdev=0\0" \
+	"mmcbootpart=2\0" \
+	"mmcrootpart=5\0" \
+	"partitions=" PARTS_DEFAULT \
+	"bootblock=9\0" \
+	"ubiblock=8\0" \
+	"ubi=enabled\0" \
+	"opts=always_resume=1\0" \
+	"dfu_alt_info=" CONFIG_DFU_ALT "\0"
+
+#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4000000)
+
+/* Goni has 3 banks of DRAM, but swap the bank */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* OneDRAM Bank #0 */
+#define PHYS_SDRAM_1_SIZE	(80 << 20)		/* 80 MB in Bank #0 */
+#define PHYS_SDRAM_2		0x40000000		/* mDDR DMC1 Bank #1 */
+#define PHYS_SDRAM_2_SIZE	(256 << 20)		/* 256 MB in Bank #1 */
+#define PHYS_SDRAM_3		0x50000000		/* mDDR DMC2 Bank #2 */
+#define PHYS_SDRAM_3_SIZE	(128 << 20)		/* 128 MB in Bank #2 */
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 KiB */
+
+/* FLASH and environment organization */
+#define CONFIG_MMC_DEFAULT_DEV	0
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND		1
+#define CONFIG_SYS_ONENAND_BASE		0xB0000000
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
+#define CONFIG_USB_GADGET_DWC2_OTG_PHY
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
new file mode 100644
index 0000000..832032d
--- /dev/null
+++ b/include/configs/s5pc210_universal.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG Universal (EXYNOS4210) board.
+ */
+
+#ifndef __CONFIG_UNIVERSAL_H
+#define __CONFIG_UNIVERSAL_H
+
+#include <configs/exynos4-common.h>
+
+#define CONFIG_TIZEN			/* TIZEN lib */
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_L2CACHE_OFF		1
+
+/* Universal has 2 banks of DRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
+
+/* select serial console configuration */
+
+/* Console configuration */
+
+#define CONFIG_BOOTCOMMAND		"run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
+
+#define NORMAL_MTDPARTS_DEFAULT CONFIG_MTDPARTS_DEFAULT
+
+#define MBRPARTS_DEFAULT	"20M(permanent)"\
+				",20M(boot)"\
+				",1G(system)"\
+				",100M(swap)"\
+				",-(UMS)\0"
+
+#define CONFIG_ENV_UBI_MTD	" ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7"
+#define CONFIG_BOOTBLOCK	"10"
+#define CONFIG_UBIBLOCK		"9"
+
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
+
+#define CONFIG_ENV_UBIFS_OPTION	" rootflags=bulk_read,no_chk_data_crc "
+#define CONFIG_ENV_FLASHBOOT	CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \
+				"${mtdparts}"
+
+#define CONFIG_ENV_COMMON_BOOT	"${console} ${meminfo}"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"updateb=" \
+		"onenand erase 0x0 0x100000;" \
+		"onenand write 0x42008000 0x0 0x100000\0" \
+	"updatek=" \
+		"onenand erase 0xc00000 0x500000;" \
+		"onenand write 0x41008000 0xc00000 0x500000\0" \
+	"bootk=" \
+		"run loaduimage; bootm 0x40007FC0\0" \
+	"updatebackup=" \
+		"mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
+		"mmc dev 0 0\0" \
+	"updatebootb=" \
+		"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
+	"lpj=lpj=3981312\0" \
+	"ubifsboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs ${lpj} " \
+		CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \
+		CONFIG_ENV_COMMON_BOOT "; run bootk\0" \
+	"tftpboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \
+		CONFIG_ENV_COMMON_BOOT \
+		"; tftp 0x40007FC0 uImage; bootm 0x40007FC0\0" \
+	"nfsboot=" \
+		"set bootargs root=/dev/nfs rw " \
+		"nfsroot=${nfsroot},nolock,tcp " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+		"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
+		"; run bootk\0" \
+	"ramfsboot=" \
+		"set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
+		"${console} ${meminfo} " \
+		"initrd=0x43000000,8M ramdisk=8192\0" \
+	"mmcboot=" \
+		"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
+		"run loaduimage; bootm 0x40007FC0\0" \
+	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
+	"verify=n\0" \
+	"rootfstype=ext4\0" \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT \
+	"mbrparts=" MBRPARTS_DEFAULT \
+	"meminfo=crashkernel=32M@0x50000000\0" \
+	"nfsroot=/nfsroot/arm\0" \
+	"bootblock=" CONFIG_BOOTBLOCK "\0" \
+	"ubiblock=" CONFIG_UBIBLOCK" \0" \
+	"ubi=enabled\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
+	"mmcdev=0\0" \
+	"mmcbootpart=2\0" \
+	"mmcrootpart=3\0" \
+	"opts=always_resume=1"
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND
+#define CONFIG_SYS_ONENAND_BASE		0x0C000000
+
+#define CONFIG_USB_GADGET_DWC2_OTG_PHY
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_SOFT_SPI
+
+#ifndef	__ASSEMBLY__
+void universal_spi_scl(int bit);
+void universal_spi_sda(int bit);
+int universal_spi_read(void);
+#endif
+
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+
+#define KEY_PWR_PMIC_NAME		"MAX8998_PMIC"
+#define KEY_PWR_STATUS_REG		MAX8998_REG_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 7)
+#define KEY_PWR_INTERRUPT_REG		MAX8998_REG_IRQ1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 7)
+
+#define KEY_VOL_UP_GPIO			EXYNOS4_GPIO_X20
+#define KEY_VOL_DOWN_GPIO		EXYNOS4_GPIO_X21
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP			LCD_COLOR16
+
+/*
+ * LCD Settings
+ */
+#define CONFIG_BMP_16BPP
+#define CONFIG_LD9040
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sagem_f@st1704.h b/include/configs/sagem_f@st1704.h
new file mode 100644
index 0000000..5a526d9
--- /dev/null
+++ b/include/configs/sagem_f@st1704.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6338.h>
+
+#define CONFIG_ENV_SIZE	SZ_8K
diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h
new file mode 100644
index 0000000..1bf2234
--- /dev/null
+++ b/include/configs/salvator-x.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/salvator-x.h
+ *     This file is Salvator-X board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ */
+
+#ifndef __SALVATOR_X_H
+#define __SALVATOR_X_H
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+#endif /* __SALVATOR_X_H */
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
new file mode 100644
index 0000000..5f89ae4
--- /dev/null
+++ b/include/configs/sam9x60ek.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the SAM9X60EK board.
+ *
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK	24000000	/* 24 MHz crystal */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_USART_BASE   ATMEL_BASE_DBGU
+#define CONFIG_USART_ID     0 /* ignored in arm */
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY            /* required until (g)pio is fixed */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
+ * NB: in this case, USB 1.1 devices won't be recognized.
+ */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000	/* 256 megs */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
+#define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_MTD_DEVICE
+#endif
+
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP		8
+#define CONFIG_PMECC_SECTOR_SIZE	512
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#ifdef CONFIG_SD_BOOT
+/* bootstrap + u-boot + env + linux in sd card */
+#define CONFIG_BOOTCOMMAND  \
+			"fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;" \
+			"fatload mmc 0:1 0x22000000 zImage;" \
+			"bootz 0x22000000 - 0x21000000"
+
+#elif defined(CONFIG_NAND_BOOT)
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_BOOTCOMMAND	"nand read " \
+				"0x22000000 0x200000 0x600000; " \
+				"nand read 0x21000000 0x180000 0x20000; " \
+				"bootz 0x22000000 - 0x21000000"
+
+#elif defined(CONFIG_QSPI_BOOT)
+/* bootstrap + u-boot + env + linux in SPI NOR flash */
+#define CONFIG_BOOTCOMMAND	"sf probe 0; "					\
+				"sf read 0x21000000 0x180000 0x80000; "		\
+				"sf read 0x22000000 0x200000 0x600000; "	\
+				"bootz 0x22000000 - 0x21000000"
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024 + 0x1000)
+
+#endif
diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h
new file mode 100644
index 0000000..7343201
--- /dev/null
+++ b/include/configs/sama5d27_som1_ek.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for the SAMA5D27 SOM1 EK Board.
+ *
+ * Copyright (C) 2017 Microchip Corporation
+ *		      Wenyou Yang <wenyou.yang@microchip.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+#undef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x8000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x218000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+/* NAND flash */
+#undef CONFIG_CMD_NAND
+
+/* SPI flash */
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_SD_BOOT
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_BOOTCOMMAND	"fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d27_som1_ek.dtb; " \
+				"fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS \
+	"console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+#endif
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#endif
+
+#endif
diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h
new file mode 100644
index 0000000..6bcbc06
--- /dev/null
+++ b/include/configs/sama5d27_wlsom1_ek.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for the SAMA5D27 WLSOM1 EK Board.
+ *
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+#undef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x218000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+/* SPL */
+#define CONFIG_SPL_TEXT_BASE		0x200000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#endif
+
+#endif
diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h
new file mode 100644
index 0000000..17028ca
--- /dev/null
+++ b/include/configs/sama5d2_icp.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for the SAMA5D2 ICP Board.
+ *
+ * Copyright (C) 2018 Microchip Corporation
+ *		      Eugen Hristev <eugen.hristev@microchip.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+#undef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_MISC_INIT_R
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x218000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+/* NAND flash */
+#undef CONFIG_CMD_NAND
+
+/* SPI flash */
+#define CONFIG_SF_DEFAULT_SPEED		66000000
+
+#undef CONFIG_BOOTCOMMAND
+#ifdef CONFIG_SD_BOOT
+/* u-boot env in sd/mmc card */
+#define FAT_ENV_INTERFACE	"mmc"
+#define FAT_ENV_DEVICE_AND_PART	"0"
+#define FAT_ENV_FILE		"uboot.env"
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; " \
+				"fatload mmc 0:1 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS \
+	"console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+#endif
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#endif
+
+#endif
diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h
new file mode 100644
index 0000000..f42e26a
--- /dev/null
+++ b/include/configs/sama5d2_ptc_ek.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for the SAMA5D2 PTC EK Board.
+ *
+ * Copyright (C) 2017 Microchip Technology Inc.
+ *		      Wenyou Yang <wenyou.yang@microchip.com>
+ *		      Ludovic Desroches <ludovic.desroches@microchip.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+#undef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK      24000000 /* from 24 MHz crystal */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+/* NAND Flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
new file mode 100644
index 0000000..4873395
--- /dev/null
+++ b/include/configs/sama5d2_xplained.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for the SAMA5D2 Xplained Board.
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ *		      Wenyou Yang <wenyou.yang@atmel.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE           0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x218000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+/* SerialFlash */
+
+#ifdef CONFIG_SD_BOOT
+
+/* bootstrap + u-boot + env in sd card */
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_BOOTCOMMAND	"fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d2_xplained.dtb; " \
+				"fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+
+#elif CONFIG_SPI_BOOT
+
+/* bootstrap + u-boot + env in sd card, but kernel + dtb in eMMC */
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_BOOTCOMMAND	"ext4load mmc 0:1 0x21000000 /boot/at91-sama5d2_xplained.dtb; " \
+				"ext4load mmc 0:1 0x22000000 /boot/zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+
+#endif
+
+#ifdef CONFIG_QSPI_BOOT
+#undef CONFIG_ENV_SPI_BUS
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_ENV_SPI_BUS	1
+#define CONFIG_BOOTCOMMAND	"sf probe 1:0; "			\
+				"sf read 0x21000000 0x180000 0x80000; "	\
+				"sf read 0x22000000 0x200000 0x600000; "\
+				"bootz 0x22000000 - 0x21000000"
+
+#endif
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#endif
+
+#endif
diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h
new file mode 100644
index 0000000..696933d
--- /dev/null
+++ b/include/configs/sama5d3_xplained.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the SAMA5D3 Xplained board.
+ *
+ * Copyright (C) 2014 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP			32
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP			(1 <<  6)
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE           0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x318000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x60000000
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00600000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"SAMA5D3 Xplained"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE		0x18000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#elif CONFIG_NAND_BOOT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+
+#endif
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
new file mode 100644
index 0000000..3a712b5
--- /dev/null
+++ b/include/configs/sama5d3xek.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the SAMA5D3xEK board.
+ *
+ * Copyright (C) 2012 - 2013 Atmel
+ *
+ * based on at91sam9m10g45ek.h by:
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP			32
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP			(1 <<  6)
+
+/* board specific (not enough SRAM) */
+#define CONFIG_SAMA5D3_LCD_BASE		0x23E00000
+
+/* NOR flash */
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define CONFIG_SYS_MAX_FLASH_SECT	131
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#endif
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE           0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x318000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+/* SerialFlash */
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x60000000
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"sama5d3"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE		0x18000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+#elif CONFIG_NAND_BOOT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+
+#endif
diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h
new file mode 100644
index 0000000..1773412
--- /dev/null
+++ b/include/configs/sama5d4_xplained.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the SAMA5D4 Xplained ultra board.
+ *
+ * Copyright (C) 2014 Atmel
+ *		      Bo Shen <voice.shen@atmel.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE           0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x218000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x80000000
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE		0x18000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#elif CONFIG_NAND_BOOT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x1000
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		224
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x40000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+
+#endif
diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h
new file mode 100644
index 0000000..6cf07a1
--- /dev/null
+++ b/include/configs/sama5d4ek.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the SAMA5D4EK board.
+ *
+ * Copyright (C) 2014 Atmel
+ *		      Bo Shen <voice.shen@atmel.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE           0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x218000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x80000000
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE		0x18000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#elif CONFIG_NAND_BOOT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x1000
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		224
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x40000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+
+#endif
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
new file mode 100644
index 0000000..5d75021
--- /dev/null
+++ b/include/configs/sandbox.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef FTRACE
+#define CONFIG_TRACE
+#define CONFIG_CMD_TRACE
+#define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
+#define CONFIG_TRACE_EARLY_SIZE		(16 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR		0x00100000
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_IO_TRACE
+#endif
+
+#ifndef CONFIG_TIMER
+#define CONFIG_SYS_TIMER_RATE		1000000
+#endif
+
+#define CONFIG_LMB
+
+#define CONFIG_HOST_MAX_DEVICES 4
+
+/*
+ * Size of malloc() pool, before and after relocation
+ */
+#define CONFIG_MALLOC_F_ADDR		0x0010000
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)	/* 32MB  */
+
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+
+/* turn on command-line edit/c/auto */
+
+#define CONFIG_ENV_SIZE		8192
+
+/* SPI - enable all SPI flash types for testing purposes */
+
+#define CONFIG_I2C_EDID
+
+/* Memory things - we don't really want a memory test */
+#define CONFIG_SYS_LOAD_ADDR		0x00000000
+#define CONFIG_SYS_MEMTEST_START	0x00100000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x1000)
+#define CONFIG_SYS_FDT_LOAD_ADDR	        0x100
+
+#define CONFIG_PHYSMEM
+
+/* Size of our emulated memory */
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_SDRAM_SIZE		(128 << 20)
+#define CONFIG_SYS_MONITOR_BASE	0
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(HOST, host, 1) \
+	func(HOST, host, 0)
+
+#ifdef __ASSEMBLY__
+#define BOOTENV
+#else
+#include <config_distro_bootcmd.h>
+#endif
+
+#define CONFIG_KEEP_SERVERADDR
+#define CONFIG_UDP_CHECKSUM
+#define CONFIG_TIMESTAMP
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SERVERIP
+
+#ifndef SANDBOX_NO_SDL
+#define CONFIG_SANDBOX_SDL
+#endif
+
+/* LCD and keyboard require SDL support */
+#ifdef CONFIG_SANDBOX_SDL
+#define LCD_BPP			LCD_COLOR16
+#define CONFIG_LCD_BMP_RLE8
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN_ALIGN
+
+#define CONFIG_KEYBOARD
+
+#define SANDBOX_SERIAL_SETTINGS		"stdin=serial,cros-ec-keyb,usbkbd\0" \
+					"stdout=serial,vidconsole\0" \
+					"stderr=serial,vidconsole\0"
+#else
+#define SANDBOX_SERIAL_SETTINGS		"stdin=serial\0" \
+					"stdout=serial,vidconsole\0" \
+					"stderr=serial,vidconsole\0"
+#endif
+
+#define SANDBOX_ETH_SETTINGS		"ethaddr=00:00:11:22:33:44\0" \
+					"eth1addr=00:00:11:22:33:45\0" \
+					"eth3addr=00:00:11:22:33:46\0" \
+					"eth5addr=00:00:11:22:33:47\0" \
+					"ipaddr=1.2.3.4\0"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x1000000\0" \
+	"fdt_addr_r=0xc00000\0" \
+	"ramdisk_addr_r=0x2000000\0" \
+	"scriptaddr=0x1000\0" \
+	"pxefile_addr_r=0x2000\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	SANDBOX_SERIAL_SETTINGS \
+	SANDBOX_ETH_SETTINGS \
+	BOOTENV \
+	MEM_LAYOUT_ENV_SETTINGS
+
+#define CONFIG_GZIP_COMPRESSED
+#define CONFIG_BZIP2
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+#define CONFIG_SYS_ATA_BASE_ADDR	0x100
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	1
+#define CONFIG_SYS_ATA_ALT_OFFSET	2
+#define CONFIG_SYS_ATA_STRIDE		4
+#endif
+
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_DEVICE	2
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	8
+#define CONFIG_SYS_SCSI_MAX_LUN		4
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+
+#define CONFIG_MISC_INIT_F
+
+#endif
diff --git a/include/configs/sandbox_spl.h b/include/configs/sandbox_spl.h
new file mode 100644
index 0000000..f536882
--- /dev/null
+++ b/include/configs/sandbox_spl.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __SANDBOX_SPL_CONFIG_H
+#define __SANDBOX_SPL_CONFIG_H
+
+#include <configs/sandbox.h>
+
+#endif
diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h
new file mode 100644
index 0000000..1beff23
--- /dev/null
+++ b/include/configs/sansa_fuze_plus.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIGS_SANSA_FUZE_PLUS_H__
+#define __CONFIGS_SANSA_FUZE_PLUS_H__
+
+/* U-Boot Commands */
+
+/* Memory configuration */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_ENV_OVERWRITE
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* LCD */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_FONT_4X6
+#define CONFIG_VIDEO_MXS_MODE_SYSTEM
+#define CONFIG_SYS_BLACK_IN_WRITE
+#define LCD_BPP	LCD_COLOR16
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_NETCONSOLE
+#endif
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif	/* __CONFIGS_SANSA_FUZE_PLUS_H__ */
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
new file mode 100644
index 0000000..d2053cc
--- /dev/null
+++ b/include/configs/sbc8349.h
@@ -0,0 +1,341 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * WindRiver SBC8349 U-Boot configuration file.
+ * Copyright (c) 2006, 2007 Wind River Systems, Inc.
+ *
+ * Paul Gortmaker <paul.gortmaker@windriver.com>
+ * Based on the MPC8349EMDS config.
+ */
+
+/*
+ * sbc8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+
+/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
+
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * DDR Setup
+ */
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+#undef CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+#define CONFIG_SYS_83XX_DDR_USES_CS0	/* WRS; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS	0x52		/* DDR DIMM */
+
+#else
+/*
+ * Manually set up DDR parameters
+ * NB: manual DDR setup untested on sbc834x
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_TIMING_1	0x36332321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+				/* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE	0x00000023
+#else
+/* the default burst length is 4 - for 64-bit data path */
+				/* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE	0x00000022
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8		/* flash size in MB */
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+					/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000
+					/* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
+
+#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69}, {1, 0x69} }
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0xFIXME
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define CONFIG_PHY_BCM5421S	1
+#define TSEC1_PHY_ADDR		0x19
+#define TSEC2_PHY_ADDR		0x1a
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME		"SBC8349"
+#define CONFIG_ROOTPATH		"/tftpboot/rootfs"
+#define CONFIG_BOOTFILE		"uImage"
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=sbc8349\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"		\
+	"update=protect off ff800000 ff83ffff; "			\
+		"era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
+	"upd=run load update\0"						\
+	"fdtaddr=780000\0"						\
+	"fdtfile=sbc8349.dtb\0"						\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
new file mode 100644
index 0000000..6aa40ca
--- /dev/null
+++ b/include/configs/sbc8548.h
@@ -0,0 +1,560 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2007,2009 Wind River Systems <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ */
+
+/*
+ * sbc8548 board configuration file
+ * Please refer to doc/README.sbc8548 for more info.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI1
+#endif
+
+#ifdef CONFIG_66
+#define CONFIG_SYS_CLK_DIV 1
+#endif
+
+#ifdef CONFIG_33
+#define CONFIG_SYS_CLK_DIV 2
+#endif
+
+#ifdef CONFIG_PCIE
+#define CONFIG_PCIE1
+#endif
+
+/*
+ * High Level Configuration Options
+ */
+
+/*
+ * If you want to boot from the SODIMM flash, instead of the soldered
+ * on flash, set this, and change JP12, SW2:8 accordingly.
+ */
+#undef CONFIG_SYS_ALT_BOOT
+
+#undef CONFIG_RIO
+
+#ifdef CONFIG_PCI
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT    1	/* enable 64-bit PCI resources */
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+/*
+ * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
+ */
+#ifndef CONFIG_SYS_CLK_DIV
+#define CONFIG_SYS_CLK_DIV	1	/* 2, if 33MHz PCI card installed */
+#endif
+#define CONFIG_SYS_CLK_FREQ	(66000000 / CONFIG_SYS_CLK_DIV)
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+/*
+ * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
+ * to collide, meaning you couldn't reliably read either. So
+ * physically remove the LBC PC100 SDRAM module from the board
+ * before enabling the two SPD options below, or check that you
+ * have the hardware fix on your board via "i2c probe" and looking
+ * for a device at 0x53.
+ */
+#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/*
+ * The hardware fix for the I2C address collision puts the DDR
+ * SPD at 0x53, but if we are running on an older board w/o the
+ * fix, it will still be at 0x51.  We check 0x53 1st.
+ */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+#define ALT_SPD_EEPROM_ADDRESS	0x53	/* CTLR 0 DIMM 0 */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+	#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
+	#define CONFIG_SYS_DDR_CONTROL	0xc300c000
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, one 8MB the other 64MB, using the CFI driver.
+ * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
+ * CS0 the 8MB boot flash, and CS6 the 64MB flash.
+ *
+ *	Default:
+ *	ec00_0000	efff_ffff	64MB SODIMM
+ *	ff80_0000	ffff_ffff	8MB soldered flash
+ *
+ *	Alternate:
+ *	ef80_0000	efff_ffff	8MB soldered flash
+ *	fc00_0000	ffff_ffff	64MB SODIMM
+ *
+ * BR0_8M:
+ *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 8 bits = BRx[19:20] = 01
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * BR0_64M:
+ *    Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
+ *    Port Size = 32 bits = BRx[19:20] = 11
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0_8M
+ * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801    BR0_64M
+ */
+#define CONFIG_SYS_BR0_8M	0xff800801
+#define CONFIG_SYS_BR0_64M	0xfc001801
+
+/*
+ * BR6_8M:
+ *    Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
+ *    Port Size = 8 bits = BRx[19:20] = 01
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+
+ * BR6_64M:
+ *    Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
+ *    Port Size = 32 bits = BRx[19:20] = 11
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801    BR6_8M
+ * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801    BR6_64M
+ */
+#define CONFIG_SYS_BR6_8M	0xef800801
+#define CONFIG_SYS_BR6_64M	0xec001801
+
+/*
+ * OR0_8M:
+ *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
+ *    XAM = OR0[17:18] = 11
+ *    CSNT = OR0[20] = 1
+ *    ACS = half cycle delay = OR0[21:22] = 11
+ *    SCY = 6 = OR0[24:27] = 0110
+ *    TRLX = use relaxed timing = OR0[29] = 1
+ *    EAD = use external address latch delay = OR0[31] = 1
+ *
+ * OR0_64M:
+ *    Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
+ *
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0_8M
+ * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR0_64M
+ */
+#define CONFIG_SYS_OR0_8M	0xff806e65
+#define CONFIG_SYS_OR0_64M	0xfc006e65
+
+/*
+ * OR6_8M:
+ *    Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
+ *    XAM = OR6[17:18] = 11
+ *    CSNT = OR6[20] = 1
+ *    ACS = half cycle delay = OR6[21:22] = 11
+ *    SCY = 6 = OR6[24:27] = 0110
+ *    TRLX = use relaxed timing = OR6[29] = 1
+ *    EAD = use external address latch delay = OR6[31] = 1
+ *
+ * OR6_64M:
+ *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR6_8M
+ * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6_64M
+ */
+#define CONFIG_SYS_OR6_8M	0xff806e65
+#define CONFIG_SYS_OR6_64M	0xfc006e65
+
+#ifndef CONFIG_SYS_ALT_BOOT		/* JP12 in default position */
+#define CONFIG_SYS_BOOT_BLOCK		0xff800000	/* start of 8MB Flash */
+#define CONFIG_SYS_ALT_FLASH		0xec000000	/* 64MB "user" flash */
+
+#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_BR0_8M
+#define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_OR0_8M
+
+#define CONFIG_SYS_BR6_PRELIM		CONFIG_SYS_BR6_64M
+#define CONFIG_SYS_OR6_PRELIM		CONFIG_SYS_OR6_64M
+#else					/* JP12 in alternate position */
+#define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* start 64MB Flash */
+#define CONFIG_SYS_ALT_FLASH		0xef800000	/* 8MB soldered flash */
+
+#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_BR0_64M
+#define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_OR0_64M
+
+#define CONFIG_SYS_BR6_PRELIM		CONFIG_SYS_BR6_8M
+#define CONFIG_SYS_OR6_PRELIM		CONFIG_SYS_OR6_8M
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_BOOT_BLOCK
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, \
+					 CONFIG_SYS_ALT_FLASH}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* CS5 = Local bus peripherals controlled by the EPLD */
+
+#define CONFIG_SYS_BR5_PRELIM		0xf8000801
+#define CONFIG_SYS_OR5_PRELIM		0xff006e65
+#define CONFIG_SYS_EPLD_BASE		0xf8000000
+#define CONFIG_SYS_LED_DISP_BASE	0xf8000000
+#define CONFIG_SYS_USER_SWITCHES_BASE	0xf8100000
+#define CONFIG_SYS_BD_REV		0xf8300000
+#define CONFIG_SYS_EEPROM_BASE		0xf8b00000
+
+/*
+ * SDRAM on the Local Bus (CS3 and CS4)
+ * Note that most boards have a hardware errata where both the
+ * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
+ * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
+ * A hardware workaround is also available, see README.sbc8548 file.
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */
+
+/*
+ * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ */
+
+#define CONFIG_SYS_BR3_PRELIM		0xf0001861
+
+/*
+ * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR3, need:
+ *    64MB mask for AM, OR3[0:7] = 1111 1100
+ *		   XAM, OR3[17:18] = 11
+ *    10 columns OR3[19-21] = 011
+ *    12 rows   OR3[23-25] = 011
+ *    EAD set for extra time OR[31] = 0
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
+ */
+
+#define CONFIG_SYS_OR3_PRELIM		0xfc006cc0
+
+/*
+ * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
+ * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
+ *
+ * For BR4, need:
+ *    Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
+ *
+ */
+
+#define CONFIG_SYS_BR4_PRELIM		0xf4001861
+
+/*
+ * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR4, need:
+ *    64MB mask for AM, OR3[0:7] = 1111 1100
+ *		   XAM, OR3[17:18] = 11
+ *    10 columns OR3[19-21] = 011
+ *    12 rows   OR3[23-25] = 011
+ *    EAD set for extra time OR[31] = 0
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
+ */
+
+#define CONFIG_SYS_OR4_PRELIM		0xfc006cc0
+
+#define CONFIG_SYS_LBC_LCRR		0x00000002    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ */
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_BSMA1516	\
+				| LSDMR_PRETOACT3	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BUFCMD		\
+				| LSDMR_BL8		\
+				| LSDMR_WRC2		\
+				| LSDMR_CL3		\
+				)
+
+#define CONFIG_SYS_LBC_LSDMR_PCHALL	\
+	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_ARFRSH	\
+	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_MRW	\
+	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_RFEN	\
+	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
+ * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total).  For SODIMM
+ * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
+ * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total).  This dynamically sets the right
+ * thing for MONITOR_LEN in both cases.
+ */
+#define CONFIG_SYS_MONITOR_LEN		(~CONFIG_SYS_TEXT_BASE + 1)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(400000000 / CONFIG_SYS_CLK_DIV)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI_VIRT		0x80000000	/* 1G PCI TLB */
+#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
+
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT		0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 8M */
+
+#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+#endif
+
+#ifdef CONFIG_RIO
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_RIO_MEM_BASE	0xC0000000
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M */
+#endif
+
+#if defined(CONFIG_PCI)
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR		0x19
+#define TSEC2_PHY_ADDR		0x1a
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SIZE		0x2000
+#if CONFIG_SYS_TEXT_BASE == 0xfff00000	/* Boot from 64MB SODIMM */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x80000)
+#define CONFIG_ENV_SECT_SIZE	0x80000	/* 512K(one sector) for env */
+#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000	/* Boot from 8MB soldered flash */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+#else
+#warning undefined environment size/location.
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_IPADDR	 192.168.0.55
+
+#define CONFIG_HOSTNAME	 "sbc8548"
+#define CONFIG_ROOTPATH	 "/opt/eldk/ppc_85xx"
+#define CONFIG_BOOTFILE	 "/uImage"
+#define CONFIG_UBOOTPATH /u-boot.bin	/* TFTP server */
+
+#define CONFIG_SERVERIP	 192.168.0.2
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_NETMASK	 255.255.255.0
+
+#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+"netdev=eth0\0"						\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"				\
+"tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"consoledev=ttyS0\0"				\
+"ramdiskaddr=2000000\0"			\
+"ramdiskfile=uRamdisk\0"			\
+"fdtaddr=1e00000\0"				\
+"fdtfile=sbc8548.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "					\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_RAMBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
new file mode 100644
index 0000000..d1535b6
--- /dev/null
+++ b/include/configs/sbc8641d.h
@@ -0,0 +1,520 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2007 Wind River Systems <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman <joe.hamman@embeddedspecialties.com>
+ *
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ */
+
+/*
+ * SBC8641D board configuration file
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
+
+#ifdef RUN_DIAG
+#define CONFIG_SYS_DIAG_ADDR        0xff800000
+#endif
+
+#define CONFIG_SYS_RESET_ADDRESS    0xfff00100
+
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xe8000000
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
+
+#undef CONFIG_SPD_EEPROM		/* Do not use SPD EEPROM for DDR setup*/
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+#define CACHE_LINE_INTERLEAVING		0x20000000
+#define PAGE_INTERLEAVING		0x21000000
+#define BANK_INTERLEAVING		0x22000000
+#define SUPER_BANK_INTERLEAVING		0x23000000
+
+#define CONFIG_ALTIVEC          1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CONFIG_SYS_L2
+#define L2_INIT		0
+#define L2_ENABLE	(L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
+#endif
+
+#undef	CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE2	0x10000000	/* DDR bank 2 */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE2		CONFIG_SYS_DDR_SDRAM_BASE2
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#if defined(CONFIG_SPD_EEPROM)
+    /*
+     * Determine DDR configuration from I2C interface.
+     */
+    #define SPD_EEPROM_ADDRESS1		0x51		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS2		0x52		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS3		0x53		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS4		0x54		/* DDR DIMM */
+
+#else
+    /*
+     * Manually set up DDR1 & DDR2 parameters
+     */
+
+    #define CONFIG_SYS_SDRAM_SIZE	512		/* DDR is 512MB */
+
+    #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
+    #define CONFIG_SYS_DDR_CS1_BNDS	0x00000000
+    #define CONFIG_SYS_DDR_CS2_BNDS	0x00000000
+    #define CONFIG_SYS_DDR_CS3_BNDS	0x00000000
+    #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102
+    #define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR_CS2_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR_CS3_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR_TIMING_3 0x00000000
+    #define CONFIG_SYS_DDR_TIMING_0	0x00220802
+    #define CONFIG_SYS_DDR_TIMING_1	0x38377322
+    #define CONFIG_SYS_DDR_TIMING_2	0x002040c7
+    #define CONFIG_SYS_DDR_CFG_1A	0x43008008
+    #define CONFIG_SYS_DDR_CFG_2	0x24401000
+    #define CONFIG_SYS_DDR_MODE_1	0x23c00542
+    #define CONFIG_SYS_DDR_MODE_2	0x00000000
+    #define CONFIG_SYS_DDR_MODE_CTL	0x00000000
+    #define CONFIG_SYS_DDR_INTERVAL	0x05080100
+    #define CONFIG_SYS_DDR_DATA_INIT	0x00000000
+    #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+    #define CONFIG_SYS_DDR_CFG_1B	0xC3008008
+
+    #define CONFIG_SYS_DDR2_CS0_BNDS	0x0010001F
+    #define CONFIG_SYS_DDR2_CS1_BNDS	0x00000000
+    #define CONFIG_SYS_DDR2_CS2_BNDS	0x00000000
+    #define CONFIG_SYS_DDR2_CS3_BNDS	0x00000000
+    #define CONFIG_SYS_DDR2_CS0_CONFIG	0x80010102
+    #define CONFIG_SYS_DDR2_CS1_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR2_CS2_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR2_CS3_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
+    #define CONFIG_SYS_DDR2_TIMING_0	0x00220802
+    #define CONFIG_SYS_DDR2_TIMING_1	0x38377322
+    #define CONFIG_SYS_DDR2_TIMING_2	0x002040c7
+    #define CONFIG_SYS_DDR2_CFG_1A	0x43008008
+    #define CONFIG_SYS_DDR2_CFG_2	0x24401000
+    #define CONFIG_SYS_DDR2_MODE_1	0x23c00542
+    #define CONFIG_SYS_DDR2_MODE_2	0x00000000
+    #define CONFIG_SYS_DDR2_MODE_CTL	0x00000000
+    #define CONFIG_SYS_DDR2_INTERVAL	0x05080100
+    #define CONFIG_SYS_DDR2_DATA_INIT	0x00000000
+    #define CONFIG_SYS_DDR2_CLK_CTRL	0x03800000
+    #define CONFIG_SYS_DDR2_CFG_1B	0xC3008008
+
+#endif
+
+/* #define CONFIG_ID_EEPROM	1
+#define ID_EEPROM_ADDR 0x57 */
+
+/*
+ * The SBC8641D contains 16MB flash space at ff000000.
+ */
+#define CONFIG_SYS_FLASH_BASE      0xff000000  /* start of FLASH 16M */
+
+/* Flash */
+#define CONFIG_SYS_BR0_PRELIM		0xff001001	/* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM		0xff006e65	/* 16MB Boot Flash area */
+
+/* 64KB EEPROM */
+#define CONFIG_SYS_BR1_PRELIM		0xf0000801	/* port size 16bit */
+#define CONFIG_SYS_OR1_PRELIM		0xffff6e65	/* 64K EEPROM area */
+
+/* EPLD - User switches, board id, LEDs */
+#define CONFIG_SYS_BR2_PRELIM		0xf1000801	/* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM		0xfff06e65	/* EPLD (switches, board ID, LEDs) area */
+
+/* Local bus SDRAM 128MB */
+#define CONFIG_SYS_BR3_PRELIM		0xe0001861	/* port size ?bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfc006cc0	/* 128MB local bus SDRAM area (1st half) */
+#define CONFIG_SYS_BR4_PRELIM		0xe4001861	/* port size ?bit */
+#define CONFIG_SYS_OR4_PRELIM		0xfc006cc0	/* 128MB local bus SDRAM area (2nd half) */
+
+/* Disk on Chip (DOC) 128MB */
+#define CONFIG_SYS_BR5_PRELIM		0xe8001001	/* port size ?bit */
+#define CONFIG_SYS_OR5_PRELIM		0xf8006e65	/* 128MB local bus SDRAM area (2nd half) */
+
+/* LCD */
+#define CONFIG_SYS_BR6_PRELIM		0xf4000801	/* port size ?bit */
+#define CONFIG_SYS_OR6_PRELIM		0xfff06e65	/* 128MB local bus SDRAM area (2nd half) */
+
+/* Control logic & misc peripherals */
+#define CONFIG_SYS_BR7_PRELIM		0xf2000801	/* port size ?bit */
+#define CONFIG_SYS_OR7_PRELIM		0xfff06e65	/* 128MB local bus SDRAM area (2nd half) */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	131		/* sectors per device */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
+
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#ifndef CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)    /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)   /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_SRIO1_MEM_BASE	0xc0000000	/* base address */
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_VIRT	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0xe2000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	CONFIG_SYS_PCIE1_IO_BUS
+#define CONFIG_SYS_PCIE1_IO_VIRT	CONFIG_SYS_PCIE1_IO_BUS
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x1000000	/* 16M */
+
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_VIRT	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0xe3000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	CONFIG_SYS_PCIE2_IO_BUS
+#define CONFIG_SYS_PCIE2_IO_VIRT	CONFIG_SYS_PCIE2_IO_BUS
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x1000000	/* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_TSEC1    1
+#define CONFIG_TSEC1_NAME       "eTSEC1"
+#define CONFIG_TSEC2    1
+#define CONFIG_TSEC2_NAME       "eTSEC2"
+#define CONFIG_TSEC3    1
+#define CONFIG_TSEC3_NAME       "eTSEC3"
+#define CONFIG_TSEC4    1
+#define CONFIG_TSEC4_NAME       "eTSEC4"
+
+#define TSEC1_PHY_ADDR		0x1F
+#define TSEC2_PHY_ADDR		0x00
+#define TSEC3_PHY_ADDR		0x01
+#define TSEC4_PHY_ADDR		0x02
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC3_FLAGS		TSEC_GIGABIT
+#define TSEC4_FLAGS		TSEC_GIGABIT
+
+#define CONFIG_SYS_TBIPA_VALUE	0x1e	/* Set TBI address not to conflict with TSEC1_PHY_ADDR */
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * BAT0         2G     Cacheable, non-guarded
+ * 0x0000_0000  2G     DDR
+ */
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
+
+/*
+ * BAT1         1G     Cache-inhibited, guarded
+ * 0x8000_0000  512M   PCI-Express 1 Memory
+ * 0xa000_0000  512M   PCI-Express 2 Memory
+ *	Changed it for operating from 0xd0000000
+ */
+#define CONFIG_SYS_DBAT1L	( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
+
+/*
+ * BAT2         512M   Cache-inhibited, guarded
+ * 0xc000_0000  512M   RapidIO Memory
+ */
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+
+/*
+ * BAT3         4M     Cache-inhibited, guarded
+ * 0xf800_0000  4M     CCSR
+ */
+#define CONFIG_SYS_DBAT3L	( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
+
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
+/*
+ * BAT4         32M    Cache-inhibited, guarded
+ * 0xe200_0000  16M    PCI-Express 1 I/O
+ * 0xe300_0000  16M    PCI-Express 2 I/0
+ *    Note that this is at 0xe0000000
+ */
+#define CONFIG_SYS_DBAT4L	( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
+
+/*
+ * BAT5         128K   Cacheable, non-guarded
+ * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
+
+/*
+ * BAT6         32M    Cache-inhibited, guarded
+ * 0xfe00_0000  32M    FLASH
+ */
+#define CONFIG_SYS_DBAT6L	((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U	((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L	((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
+#define CONFIG_SYS_DBAT7L	0x00000000
+#define CONFIG_SYS_DBAT7U	0x00000000
+#define CONFIG_SYS_IBAT7L	0x00000000
+#define CONFIG_SYS_IBAT7U	0x00000000
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128k(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_HAS_ETH0		1
+#define CONFIG_HAS_ETH1		1
+#define CONFIG_HAS_ETH2		1
+#define CONFIG_HAS_ETH3		1
+
+#define CONFIG_IPADDR		192.168.0.50
+
+#define CONFIG_HOSTNAME		"sbc8641d"
+#define CONFIG_ROOTPATH		"/opt/eldk/ppc_74xx"
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_SERVERIP		192.168.0.2
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+   "netdev=eth0\0"							\
+   "consoledev=ttyS0\0"							\
+   "ramdiskaddr=2000000\0"						\
+   "ramdiskfile=uRamdisk\0"						\
+   "dtbaddr=400000\0"							\
+   "dtbfile=sbc8641d.dtb\0"						\
+   "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0"	\
+   "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0"	\
+   "maxcpus=1"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "	\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $dtbaddr $dtbfile;"						\
+   "bootm $loadaddr - $dtbaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "	\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $dtbaddr $dtbfile;"						\
+   "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_FLASHBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "	\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "bootm ffd00000 ffb00000 ffa00000"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_FLASHBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h
new file mode 100644
index 0000000..cc10892
--- /dev/null
+++ b/include/configs/sc_sps_1.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * SchulerControl GmbH, SC_SPS_1 module config
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ */
+#ifndef __CONFIGS_SC_SPS_1_H__
+#define __CONFIGS_SC_SPS_1_H__
+
+/* System configuration */
+#define CONFIG_MACH_TYPE	MACH_TYPE_SC_SPS_1
+
+/* U-Boot Commands */
+
+/* Memory configuration */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* Max 1 GB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(256 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+/* FEC Ethernet on SoC */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_PHY_SMSC
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#endif
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTCOMMAND	"bootm"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"update_sd_firmware_filename=u-boot.sd\0"			\
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "					\
+		"if tftp ${update_sd_firmware_filename} ; then "	\
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "				\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; "		\
+		"fi ; "							\
+		"fi\0"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_SC_SPS_1_H__ */
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
new file mode 100644
index 0000000..5df013b
--- /dev/null
+++ b/include/configs/seaboard.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+/* LP0 suspend / resume */
+#define CONFIG_TEGRA_LP0
+#define CONFIG_TEGRA_PMU
+#define CONFIG_TPS6586X_POWER
+#define CONFIG_TEGRA_CLOCK_SCALING
+
+#include "tegra20-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Seaboard"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_SEABOARD
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+
+/* NAND support */
+#define CONFIG_TEGRA_NAND
+
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h
new file mode 100644
index 0000000..2d219b2
--- /dev/null
+++ b/include/configs/secomx6quq7.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Seco S.r.l
+ *
+ * Configuration settings for the Seco Boards.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_BOARD_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_USDHC_NUM        2
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		6
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"ethprime=FEC0\0"						\
+	"netdev=eth0\0"							\
+	"ethprime=FEC0\0"						\
+	"uboot=u-boot.bin\0"						\
+	"kernel=uImage\0"						\
+	"nfsroot=/opt/eldk/arm\0"					\
+	"ip_local=10.0.0.5::10.0.0.1:255.255.255.0::eth0:off\0"		\
+	"ip_server=10.0.0.1\0"						\
+	"nfs_path=/targetfs \0"						\
+	"memory=mem=1024M\0"						\
+	"bootdev=mmc dev 0; ext2load mmc 0:1\0"				\
+	"root=root=/dev/mmcblk0p1\0"					\
+	"option=rootwait rw fixrtc rootflags=barrier=1\0"		\
+	"cpu_freq=arm_freq=996\0"					\
+	"setbootargs=setenv bootargs console=ttymxc1,115200 ${root}"	\
+		" ${option} ${memory} ${cpu_freq}\0"			\
+	"setbootargs_nfs=setenv bootargs console=ttymxc1,115200"	\
+		" root=/dev/nfs  nfsroot=${ip_server}:${nfs_path}"	\
+		" nolock,wsize=4096,rsize=4096  ip=:::::eth0:dhcp"	\
+		" ${memory} ${cpu_freq}\0"				\
+	"setbootdev=setenv boot_dev ${bootdev} 10800000 /boot/uImage\0"	\
+	"bootcmd=run setbootargs; run setbootdev; run boot_dev;"	\
+		" bootm 0x10800000\0"					\
+	"stdin=serial\0"						\
+	"stdout=serial\0"						\
+	"stderr=serial\0"
+
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			(2u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+	#define CONFIG_ENV_OFFSET		(6 * 128 * 1024)
+	#define CONFIG_SYS_MMC_ENV_DEV		0
+	#define CONFIG_DYNAMIC_MMC_DEVNO
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sei510.h b/include/configs/sei510.h
new file mode 100644
index 0000000..d37b4c6
--- /dev/null
+++ b/include/configs/sei510.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for the SEI510
+ *
+ * Copyright (C) 2019 Baylibre, SAS
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define LOGO_UUID "43a3305d-150f-4cc9-bd3b-38fca8693846;"
+#define CACHE_UUID "99207ae6-5207-11e9-999e-6f77a3612069;"
+#define SYSTEM_UUID "99f9b7ac-5207-11e9-8507-c3c037e393f3;"
+#define VENDOR_UUID "9d082802-5207-11e9-954c-cbbce08ba108;"
+#define USERDATA_UUID "9b976e42-5207-11e9-8f16-ff47ac594b22;"
+#define ROOT_UUID "ddb8c3f6-d94d-4394-b633-3134139cc2e0;"
+
+#define PARTS_DEFAULT                                        \
+	"uuid_disk=${uuid_gpt_disk};"  			\
+	"name=boot,size=64M,bootable,uuid=${uuid_gpt_boot};" \
+	"name=logo,size=2M,uuid=" LOGO_UUID             \
+	"name=cache,size=256M,uuid=" CACHE_UUID             \
+	"name=system,size=1536M,uuid=" SYSTEM_UUID           \
+	"name=vendor,size=256M,uuid=" VENDOR_UUID            \
+	"name=userdata,size=5341M,uuid=" USERDATA_UUID	\
+	"name=rootfs,size=-,uuid=" ROOT_UUID
+
+
+#include <configs/meson64_android.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sei610.h b/include/configs/sei610.h
new file mode 100644
index 0000000..6d09316
--- /dev/null
+++ b/include/configs/sei610.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for the SEI510
+ *
+ * Copyright (C) 2019 Baylibre, SAS
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define LOGO_UUID "43a3305d-150f-4cc9-bd3b-38fca8693846;"
+#define CACHE_UUID "99207ae6-5207-11e9-999e-6f77a3612069;"
+#define SYSTEM_UUID "99f9b7ac-5207-11e9-8507-c3c037e393f3;"
+#define VENDOR_UUID "9d082802-5207-11e9-954c-cbbce08ba108;"
+#define USERDATA_UUID "9b976e42-5207-11e9-8f16-ff47ac594b22;"
+#define ROOT_UUID "ddb8c3f6-d94d-4394-b633-3134139cc2e0;"
+
+#define PARTS_DEFAULT                                        \
+	"uuid_disk=${uuid_gpt_disk};"  			\
+	"name=boot,size=64M,bootable,uuid=${uuid_gpt_boot};" \
+	"name=logo,size=2M,uuid=" LOGO_UUID             \
+	"name=cache,size=256M,uuid=" CACHE_UUID             \
+	"name=system,size=1536M,uuid=" SYSTEM_UUID           \
+	"name=vendor,size=256M,uuid=" VENDOR_UUID            \
+	"name=userdata,size=12795M,uuid=" USERDATA_UUID	\
+	"name=rootfs,size=-,uuid=" ROOT_UUID
+
+#include <configs/meson64_android.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sfr_nb4_ser.h b/include/configs/sfr_nb4_ser.h
new file mode 100644
index 0000000..2aa5c66
--- /dev/null
+++ b/include/configs/sfr_nb4_ser.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm6358.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_ENV_SIZE	SZ_8K
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
new file mode 100644
index 0000000..cd7f51c
--- /dev/null
+++ b/include/configs/sh7752evb.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the sh7752evb board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ */
+
+#ifndef __SH7752EVB_H
+#define __SH7752EVB_H
+
+#define CONFIG_CPU_SH7752	1
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* MEMORY */
+#define SH7752EVB_SDRAM_BASE		(0x40000000)
+#define SH7752EVB_SDRAM_SIZE		(512 * 1024 * 1024)
+
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_CONS_SCIF2	1
+
+#define CONFIG_SYS_MEMTEST_START	(SH7752EVB_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 480 * 1024 * 1024)
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(SH7752EVB_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(SH7752EVB_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 128 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	18
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
+#define CONFIG_SH_ETHER_USE_GETHER	1
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
+#define CONFIG_PHY_VITESSE
+
+#define SH7752EVB_ETHERNET_MAC_BASE_SPI	0x00090000
+#define SH7752EVB_SPI_SECTOR_SIZE	(64 * 1024)
+#define SH7752EVB_ETHERNET_MAC_BASE	SH7752EVB_ETHERNET_MAC_BASE_SPI
+#define SH7752EVB_ETHERNET_MAC_SIZE	17
+#define SH7752EVB_ETHERNET_NUM_CH	2
+
+/* SPI */
+#define CONFIG_SH_SPI_BASE		0xfe002000
+
+/* MMCIF */
+#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
+#define CONFIG_SH_MMCIF_CLK		48000000
+
+/* ENV setting */
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_ADDR		(0x00080000)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+		"netboot=bootp; bootm\0"
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#endif	/* __SH7752EVB_H */
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
new file mode 100644
index 0000000..6b00bd7
--- /dev/null
+++ b/include/configs/sh7753evb.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the sh7753evb board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ */
+
+#ifndef __SH7753EVB_H
+#define __SH7753EVB_H
+
+#define CONFIG_CPU_SH7753	1
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* MEMORY */
+#define SH7753EVB_SDRAM_BASE		(0x40000000)
+#define SH7753EVB_SDRAM_SIZE		(512 * 1024 * 1024)
+
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_CONS_SCIF2	1
+
+#define CONFIG_SYS_MEMTEST_START	(SH7753EVB_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 480 * 1024 * 1024)
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(SH7753EVB_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(SH7753EVB_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 128 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	18
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
+#define CONFIG_SH_ETHER_USE_GETHER	1
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
+#define CONFIG_PHY_VITESSE
+
+#define SH7753EVB_ETHERNET_MAC_BASE_SPI	0x00090000
+#define SH7753EVB_SPI_SECTOR_SIZE	(64 * 1024)
+#define SH7753EVB_ETHERNET_MAC_BASE	SH7753EVB_ETHERNET_MAC_BASE_SPI
+#define SH7753EVB_ETHERNET_MAC_SIZE	17
+#define SH7753EVB_ETHERNET_NUM_CH	2
+
+/* SPI */
+#define CONFIG_SH_SPI_BASE		0xfe002000
+
+/* MMCIF */
+#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
+#define CONFIG_SH_MMCIF_CLK		48000000
+
+/* ENV setting */
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_ADDR		(0x00080000)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+		"netboot=bootp; bootm\0"
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#endif	/* __SH7753EVB_H */
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
new file mode 100644
index 0000000..f1955a1
--- /dev/null
+++ b/include/configs/sh7757lcr.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the sh7757lcr board
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ */
+
+#ifndef __SH7757LCR_H
+#define __SH7757LCR_H
+
+#define CONFIG_CPU_SH7757	1
+#define CONFIG_SH7757LCR_DDR_ECC	1
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* MEMORY */
+#define SH7757LCR_SDRAM_BASE		(0x80000000)
+#define SH7757LCR_SDRAM_SIZE		(240 * 1024 * 1024)
+#define SH7757LCR_SDRAM_ECC_SETTING	0x0f000000	/* 240MByte */
+#define SH7757LCR_SDRAM_DVC_SIZE	(16 * 1024 * 1024)
+
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_CONS_SCIF2	1
+
+#define CONFIG_SYS_MEMTEST_START	(SH7757LCR_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 224 * 1024 * 1024)
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(SH7757LCR_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(SH7757LCR_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 (128 + 16) * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	1
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+
+#define SH7757LCR_ETHERNET_MAC_BASE_SPI	0x000b0000
+#define SH7757LCR_SPI_SECTOR_SIZE	(64 * 1024)
+#define SH7757LCR_ETHERNET_MAC_BASE	SH7757LCR_ETHERNET_MAC_BASE_SPI
+#define SH7757LCR_ETHERNET_MAC_SIZE	17
+#define SH7757LCR_ETHERNET_NUM_CH	2
+
+/* Gigabit Ether */
+#define SH7757LCR_GIGA_ETHERNET_NUM_CH	2
+
+/* SPI */
+#define CONFIG_SH_SPI_BASE		0xfe002000
+
+/* MMCIF */
+#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
+#define CONFIG_SH_MMCIF_CLK		48000000
+
+/* SH7757 board */
+#define SH7757LCR_SDRAM_PHYS_TOP	0x40000000
+#define SH7757LCR_GRA_OFFSET		0x1f000000
+#define SH7757LCR_PCIEBRG_ADDR_B0	0x000a0000
+#define SH7757LCR_PCIEBRG_SIZE_B0	(64 * 1024)
+#define SH7757LCR_PCIEBRG_ADDR		0x00090000
+#define SH7757LCR_PCIEBRG_SIZE		(96 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_ADDR		(0x00080000)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+		"netboot=bootp; bootm\0"
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#endif	/* __SH7757LCR_H */
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
new file mode 100644
index 0000000..10961b1
--- /dev/null
+++ b/include/configs/sh7763rdp.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the Renesas SH7763RDP board
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ */
+
+#ifndef __SH7763RDP_H
+#define __SH7763RDP_H
+
+#define CONFIG_CPU_SH7763	1
+#define __LITTLE_ENDIAN		1
+
+#define CONFIG_ENV_OVERWRITE    1
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* SCIF */
+#define CONFIG_CONS_SCIF2		1
+
+#define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
+												settings for this board */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Flash(NOR) */
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
+#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+#define CONFIG_SYS_MAX_FLASH_SECT  (520)
+
+/* U-Boot setting */
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+
+/* Clock */
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+
+/* Ether */
+#define CONFIG_SH_ETHER_USE_PORT (1)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+
+#endif /* __SH7763RDP_H */
diff --git a/include/configs/sheep_rk3368.h b/include/configs/sheep_rk3368.h
new file mode 100644
index 0000000..238838f
--- /dev/null
+++ b/include/configs/sheep_rk3368.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIGS_PX5_EVB_H
+#define __CONFIGS_PX5_EVB_H
+
+#include <configs/rk3368_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define KERNEL_LOAD_ADDR		0x280000
+#define DTB_LOAD_ADDR			0x5600000
+#define INITRD_LOAD_ADDR		0x5bf0000
+
+#define CONFIG_CONSOLE_SCROLL_LINES	10
+
+#endif
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
new file mode 100644
index 0000000..deec717
--- /dev/null
+++ b/include/configs/sheevaplug.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009-2014
+ * Gerald Kerma <dreagle@doukki.net>
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef _CONFIG_SHEEVAPLUG_H
+#define _CONFIG_SHEEVAPLUG_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * Standard filesystems
+ */
+#define CONFIG_BZIP2
+
+/*
+ * mv-plug-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-plug-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0x80000
+#define CONFIG_ENV_OFFSET		0x80000	/* env starts here */
+/*
+ * Environment is right behind U-Boot in flash. Make sure U-Boot
+ * doesn't grow into the environment area.
+ */
+#define CONFIG_BOARD_SIZE_LIMIT		CONFIG_ENV_OFFSET
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"${x_bootcmd_kernel}; "	\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"bootm 0x6400000;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console"	\
+	"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT	\
+	"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \
+	"x_bootcmd_usb=usb start\0" \
+	"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SDIO/MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MVEBU_MMC
+#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
+#endif /* CONFIG_CMD_MMC */
+
+/*
+ * SATA driver configuration
+ */
+#ifdef CONFIG_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_MVSATA_IDE_USE_PORT1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
+#endif /* CONFIG_IDE */
+
+#endif /* _CONFIG_SHEEVAPLUG_H */
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
new file mode 100644
index 0000000..ea6cc38
--- /dev/null
+++ b/include/configs/siemens-am33x-common.h
@@ -0,0 +1,468 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * siemens am33x common board options
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H
+#define __CONFIG_SIEMENS_AM33X_COMMON_H
+
+#include <asm/arch/omap.h>
+
+#define CONFIG_DMA_COHERENT
+#define CONFIG_DMA_COHERENT_SIZE	(1 << 20)
+
+#define CONFIG_SYS_MALLOC_LEN		(16 * 1024 * 1024)
+#ifdef CONFIG_SIEMENS_MACH_TYPE
+#define CONFIG_MACH_TYPE		CONFIG_SIEMENS_MACH_TYPE
+#endif
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* commands to include */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_ROOTPATH		"/opt/eldk"
+#endif
+
+#define CONFIG_ENV_OVERWRITE		1
+
+#define CONFIG_SYS_AUTOLOAD	"yes"
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS		32
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * memtest works on 8 MB in DRAM after skipping 32MB from
+ * start addr of ram disk
+ */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_DRAM_1 + (64 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
+					+ (8 * 1024 * 1024))
+
+#define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
+
+ /* Physical Memory Map */
+#define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
+						GENERATED_GBL_DATA_SIZE)
+ /* Platform/Board specific defs */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/* NS16550 Configuration */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#endif
+#define CONFIG_SYS_NS16550_CLK		(48000000)
+#define CONFIG_SYS_NS16550_COM1		0x44e09000
+#define CONFIG_SYS_NS16550_COM4		0x481a6000
+
+
+/* I2C Configuration */
+#define CONFIG_I2C
+#define CONFIG_SYS_I2C
+
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+
+#define CONFIG_SYS_NAND_ECCSTEPS	4
+#define	CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * USB configuration
+ */
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+/* USB DRACO ID as default */
+#define CONFIG_USBD_HS
+
+/* USB Device Firmware Update support */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(1 << 20)
+#define DFU_MANIFEST_POLL_TIMEOUT	25000
+
+#endif /* CONFIG_SPL_BUILD */
+
+/*
+ * Default to using SPI for environment, etc.  We have multiple copies
+ * of SPL as the ROM will check these locations.
+ * 0x0 - 0x20000 : First copy of SPL
+ * 0x20000 - 0x40000 : Second copy of SPL
+ * 0x40000 - 0x60000 : Third copy of SPL
+ * 0x60000 - 0x80000 : Fourth copy of SPL
+ * 0x80000 - 0xDF000 : U-Boot
+ * 0xDF000 - 0xE0000 : U-Boot Environment
+ * 0xE0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+# define CONFIG_ENV_OFFSET		(892 << 10) /* 892 KiB in */
+# define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
+#endif /* SPI support */
+
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT         10
+
+/* NAND support */
+#ifdef CONFIG_NAND
+/* UBI Support */
+
+/* Commen environment */
+#define COMMON_ENV_DFU_ARGS	"dfu_args=run bootargs_defaults;" \
+				"setenv bootargs ${bootargs};" \
+				"mtdparts default;" \
+				"draco_led 1;" \
+				"dfu 0 nand 0;" \
+				"draco_led 0;\0" \
+
+#define COMMON_ENV_NAND_BOOT \
+		"nand_boot=echo Booting from nand; " \
+		"if test ${upgrade_available} -eq 1; then " \
+			"if test ${bootcount} -gt ${bootlimit}; " \
+				"then " \
+				"setenv upgrade_available 0;" \
+				"setenv ${partitionset_active} true;" \
+				"if test -n ${A}; then " \
+					"setenv partitionset_active B; " \
+					"env delete A; " \
+				"fi;" \
+				"if test -n ${B}; then " \
+					"setenv partitionset_active A; " \
+					"env delete B; " \
+				"fi;" \
+				"saveenv; " \
+			"fi;" \
+		"fi;" \
+		"echo set ${partitionset_active}...;" \
+		"run nand_args; "
+
+#define COMMON_ENV_NAND_CMDS	"flash_self=run nand_boot\0" \
+				"flash_self_test=setenv testargs test; " \
+					"run nand_boot\0" \
+				"dfu_start=echo Preparing for dfu mode ...; " \
+				"run dfu_args; \0"
+
+#define COMMON_ENV_SETTINGS \
+	"verify=no \0" \
+	"project_dir=targetdir\0" \
+	"upgrade_available=0\0" \
+	"altbootcmd=run bootcmd\0" \
+	"partitionset_active=A\0" \
+	"loadaddr=0x82000000\0" \
+	"kloadaddr=0x81000000\0" \
+	"script_addr=0x81900000\0" \
+	"console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \
+	"nfsopts=nolock rw\0" \
+	"ip_method=none\0" \
+	"bootenv=uEnv.txt\0" \
+	"bootargs_defaults=setenv bootargs " \
+		"console=${console} " \
+		"${testargs} " \
+		"${optargs}\0" \
+	"siemens_help=echo; "\
+		"echo Type 'run flash_self' to use kernel and root " \
+		"filesystem on memory; echo Type 'run flash_self_test' to " \
+		"use kernel and root filesystem on memory, boot in test " \
+		"mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
+		"from memory and root filesystem over NFS; echo Type " \
+		"'run net_nfs' to get Kernel over TFTP and mount root " \
+		"filesystem over NFS; " \
+		"echo Set partitionset_active variable to 'A' " \
+		"or 'B' to select kernel and rootfs partition; " \
+		"echo" \
+		"\0"
+
+/*
+ * Variant 1 partition layout
+ * chip-size = 256MiB
+ *|         name |        size |           address area |
+ *-------------------------------------------------------
+ *|          spl | 128.000 KiB | 0x       0..0x   1ffff |
+ *|  spl.backup1 | 128.000 KiB | 0x   20000..0x   3ffff |
+ *|  spl.backup2 | 128.000 KiB | 0x   40000..0x   5ffff |
+ *|  spl.backup3 | 128.000 KiB | 0x   60000..0x   7ffff |
+ *|       u-boot |   1.875 MiB | 0x   80000..0x  25ffff |
+ *|    uboot.env | 128.000 KiB | 0x  260000..0x  27ffff |
+ *|     kernel_a |   5.000 MiB | 0x  280000..0x  77ffff |
+ *|     kernel_b |   5.000 MiB | 0x  780000..0x  c7ffff |
+ *|      mtdoops |   8.000 MiB | 0x  c80000..0x 147ffff |
+ *|       rootfs | 235.500 MiB | 0x 1480000..0x fffffff |
+ *-------------------------------------------------------
+
+					"mtdparts=omap2-nand.0:" \
+					"128k(spl),"		\
+					"128k(spl.backup1),"	\
+					"128k(spl.backup2),"	\
+					"128k(spl.backup3),"	\
+					"1920k(u-boot),"	\
+					"128k(uboot.env),"	\
+					"5120k(kernel_a),"	\
+					"5120k(kernel_b),"	\
+					"8192k(mtdoops),"	\
+					"-(rootfs)"
+ */
+
+#define DFU_ALT_INFO_NAND_V1 \
+	"spl part 0 1;" \
+	"spl.backup1 part 0 2;" \
+	"spl.backup2 part 0 3;" \
+	"spl.backup3 part 0 4;" \
+	"u-boot part 0 5;" \
+	"u-boot.env part 0 6;" \
+	"kernel_a part 0 7;" \
+	"kernel_b part 0 8;" \
+	"rootfs partubi 0 10"
+
+#define CONFIG_ENV_SETTINGS_NAND_V1 \
+	"nand_active_ubi_vol=rootfs_a\0" \
+	"nand_active_ubi_vol_A=rootfs_a\0" \
+	"nand_active_ubi_vol_B=rootfs_b\0" \
+	"nand_root_fs_type=ubifs rootwait=1\0" \
+	"nand_src_addr=0x280000\0" \
+	"nand_src_addr_A=0x280000\0" \
+	"nand_src_addr_B=0x780000\0" \
+	"nand_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv ${partitionset_active} true;" \
+		"if test -n ${A}; then " \
+			"setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \
+			"setenv nand_src_addr ${nand_src_addr_A};" \
+		"fi;" \
+		"if test -n ${B}; then " \
+			"setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \
+			"setenv nand_src_addr ${nand_src_addr_B};" \
+		"fi;" \
+		"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
+		"ubi.mtd=9,${ubi_off};" \
+		"setenv bootargs ${bootargs} " \
+		"root=${nand_root} noinitrd ${mtdparts} " \
+		"rootfstype=${nand_root_fs_type} ip=${ip_method} " \
+		"console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
+		"=mtdoops\0" \
+	COMMON_ENV_DFU_ARGS \
+		"dfu_alt_info=" DFU_ALT_INFO_NAND_V1 "\0" \
+	COMMON_ENV_NAND_BOOT \
+		"nand read.i ${kloadaddr} ${nand_src_addr} " \
+		"${nand_img_size}; bootm ${kloadaddr}\0" \
+	COMMON_ENV_NAND_CMDS
+
+#define CONFIG_ENV_SETTINGS_V1 \
+		COMMON_ENV_SETTINGS \
+	"net_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv bootfile ${project_dir}/kernel/uImage;" \
+		"setenv rootpath /home/projects/${project_dir}/rootfs;" \
+		"setenv bootargs ${bootargs} " \
+		"root=/dev/nfs ${mtdparts} " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
+		"ip=${ipaddr}:${serverip}:" \
+		"${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
+	"net_nfs=echo Booting from network ...; " \
+		"run net_args; " \
+		"tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
+		"bootm ${kloadaddr}\0"
+
+/*
+ * Variant 2 partition layout (default)
+ * chip-size = 256MiB or 512 MiB
+ *|         name |        size |           address area |
+ *-------------------------------------------------------
+ *|          spl | 128.000 KiB | 0x       0..0x   1ffff |
+ *|  spl.backup1 | 128.000 KiB | 0x   20000..0x   3ffff |
+ *|  spl.backup2 | 128.000 KiB | 0x   40000..0x   5ffff |
+ *|  spl.backup3 | 128.000 KiB | 0x   60000..0x   7ffff |
+ *|       u-boot |   1.875 MiB | 0x   80000..0x  25ffff |
+ *|   uboot.env0 | 512.000 KiB | 0x  260000..0x  2Dffff |
+ *|   uboot.env1 | 512.000 KiB | 0x  2E0000..0x  35ffff |
+ *|      mtdoops | 512.000 KiB | 0x  360000..0x  3dffff |
+ *| (256) rootfs | 252.125 MiB | 0x  3E0000..0x fffffff |
+ *| (512) rootfs | 508.125 MiB | 0x  3E0000..0x1fffffff |
+ *-------------------------------------------------------
+ */
+
+#define DFU_ALT_INFO_NAND_V2 \
+	"spl part 0 1;" \
+	"spl.backup1 part 0 2;" \
+	"spl.backup2 part 0 3;" \
+	"spl.backup3 part 0 4;" \
+	"u-boot part 0 5;" \
+	"u-boot.env0 part 0 6;" \
+	"u-boot.env1 part 0 7;" \
+	"rootfs partubi 0 9" \
+
+#define CONFIG_ENV_SETTINGS_NAND_V2 \
+	"nand_active_ubi_vol=rootfs_a\0" \
+	"rootfs_name=rootfs\0" \
+	"kernel_name=uImage\0"\
+	"nand_root_fs_type=ubifs rootwait=1\0" \
+	"nand_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv ${partitionset_active} true;" \
+		"if test -n ${A}; then " \
+			"setenv nand_active_ubi_vol ${rootfs_name}_a;" \
+		"fi;" \
+		"if test -n ${B}; then " \
+			"setenv nand_active_ubi_vol ${rootfs_name}_b;" \
+		"fi;" \
+		"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
+		"ubi.mtd=rootfs,2048;" \
+		"setenv bootargs ${bootargs} " \
+		"root=${nand_root} noinitrd ${mtdparts} " \
+		"rootfstype=${nand_root_fs_type} ip=${ip_method} " \
+		"console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
+		"=mtdoops\0" \
+	COMMON_ENV_DFU_ARGS \
+		"dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \
+	COMMON_ENV_NAND_BOOT \
+		"ubi part rootfs ${ubi_off};" \
+		"ubifsmount ubi0:${nand_active_ubi_vol};" \
+		"ubifsload ${kloadaddr} boot/${kernel_name};" \
+		"ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \
+		"bootm ${kloadaddr} - ${loadaddr}\0" \
+	"nand_boot_backup=ubifsload ${loadaddr} boot/am335x-draco.dtb;" \
+		"bootm ${kloadaddr} - ${loadaddr}\0" \
+	COMMON_ENV_NAND_CMDS
+
+#define CONFIG_ENV_SETTINGS_V2 \
+		COMMON_ENV_SETTINGS \
+	"net_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv bootfile ${project_dir}/kernel/uImage;" \
+		"setenv bootdtb ${project_dir}/kernel/dtb;" \
+		"setenv rootpath /home/projects/${project_dir}/rootfs;" \
+		"setenv bootargs ${bootargs} " \
+		"root=/dev/nfs ${mtdparts} " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
+		"ip=${ipaddr}:${serverip}:" \
+		"${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
+	"net_nfs=echo Booting from network ...; " \
+		"run net_args; " \
+		"tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
+		"tftpboot ${loadaddr} ${serverip}:${bootdtb}; " \
+		"bootm ${kloadaddr} - ${loadaddr}\0"
+
+/*
+ * Variant 3 partition layout
+ * chip-size = 512MiB
+ *|         name |        size |           address area |
+ *-------------------------------------------------------
+ *|          spl | 128.000 KiB | 0x       0..0x   1ffff |
+ *|  spl.backup1 | 128.000 KiB | 0x   20000..0x   3ffff |
+ *|  spl.backup2 | 128.000 KiB | 0x   40000..0x   5ffff |
+ *|  spl.backup3 | 128.000 KiB | 0x   60000..0x   7ffff |
+ *|       u-boot |   1.875 MiB | 0x   80000..0x  25ffff |
+ *|   uboot.env0 | 512.000 KiB | 0x  260000..0x  2Dffff |
+ *|   uboot.env1 | 512.000 KiB | 0x  2E0000..0x  35ffff |
+ *|       rootfs | 300.000 MiB | 0x  360000..0x12f5ffff |
+ *|      mtdoops | 512.000 KiB | 0x12f60000..0x12fdffff |
+ *|configuration | 104.125 MiB | 0x12fe0000..0x1fffffff |
+ *-------------------------------------------------------
+
+					"mtdparts=omap2-nand.0:" \
+					"128k(spl),"		\
+					"128k(spl.backup1),"	\
+					"128k(spl.backup2),"	\
+					"128k(spl.backup3),"	\
+					"1920k(u-boot),"	\
+					"512k(u-boot.env0),"	\
+					"512k(u-boot.env1),"	\
+					"300m(rootfs),"		\
+					"512k(mtdoops),"	\
+					"-(configuration)"
+
+ */
+
+#define CONFIG_SYS_NAND_BASE		(0x08000000)	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND
+							   devices */
+#if !defined(CONFIG_SPI_BOOT)
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#endif
+#endif
+
+/* Reboot after 60 sec if bootcmd fails */
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_BOOT_RETRY_TIME 60
+
+#endif	/* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
new file mode 100644
index 0000000..736ceb1
--- /dev/null
+++ b/include/configs/sifive-fu540.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_8M
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+#define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
+
+/* Environment options */
+#define CONFIG_ENV_SIZE			SZ_128K
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0xffffffffffffffff\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"kernel_addr_r=0x84000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"scriptaddr=0x88100000\0" \
+	"pxefile_addr_r=0x88200000\0" \
+	"ramdisk_addr_r=0x88300000\0" \
+	BOOTENV
+
+#define CONFIG_PREBOOT \
+	"setenv fdt_addr ${fdtcontroladdr};" \
+	"fdt addr ${fdtcontroladdr};"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/silk.h b/include/configs/silk.h
new file mode 100644
index 0000000..a78da46
--- /dev/null
+++ b/include/configs/silk.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/configs/silk.h
+ *     This file is silk board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#ifndef __SILK_H
+#define __SILK_H
+
+#include "rcar-gen2-common.h"
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
+#define STACK_AREA_SIZE			0x00100000
+#define LOW_LEVEL_MERAM_STACK \
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE		0x40000000
+#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SPI_FLASH_QUAD
+
+/* SH Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK	20000000u
+#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootm_size=0x10000000\0"
+
+/* SPL support */
+#define CONFIG_SPL_STACK		0xe6340000
+#define CONFIG_SPL_MAX_SIZE		0x4000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIF2
+#define CONFIG_SH_SCIF_CLK_FREQ		65000000
+#endif
+
+#endif /* __SILK_H */
diff --git a/include/configs/sksimx6.h b/include/configs/sksimx6.h
new file mode 100644
index 0000000..4f7ec2d
--- /dev/null
+++ b/include/configs/sksimx6.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ */
+
+
+#ifndef __SKSIMX6_CONFIG_H
+#define __SKSIMX6_CONFIG_H
+
+#include "mx6_common.h"
+#include "imx6_spl.h"
+
+/* Thermal */
+#define CONFIG_IMX_THERMAL
+
+/* Serial */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART1_BASE
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(8 * SZ_1M)
+
+/* Ethernet */
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0x01
+
+#define CONFIG_PHY_MICREL_KSZ9021
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C2
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* Filesystem support */
+
+/* Physical Memory Map */
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE                (16 * 1024)
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + \
+						CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=${console},${baudrate}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+		"${netmask}:${hostname}:${netdev}:off\0"		\
+	"addmisc=setenv bootargs ${bootargs} ${miscargs}\0" 		\
+	"bootcmd=run mmcboot\0"						\
+	"bootfile=uImage\0"						\
+	"bootimage=uImage\0"						\
+	"console=ttymxc0\0"						\
+	"fdt_addr_r=0x18000000\0" 					\
+	"fdt_file=imx6dl-sks-cts.dtb\0"					\
+	"fdt_high=0xffffffff\0" 					\
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" 		\
+	"miscargs=quiet\0"						\
+	"mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0"		\
+	"mmcboot=if run mmcload;then " 					\
+		"run mmcargs addcons addmisc;"				\
+			"bootm;fi\0" 					\
+	"mmcload=mmc rescan;"						\
+		"load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\
+	"mmcpart=1\0"							\
+	"mmcroot=/dev/mmcblk0p1\0"					\
+	"net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};"	\
+		"tftp ${fdt_addr_r} ${board_name}/${fdt_file};"		\
+		"run nfsargs addip addcons addmisc;"			\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"nfsargs=setenv bootargs root=/dev/nfs "			\
+		"nfsroot=${serverip}:${nfsroot},v3 panic=1\0"
+
+#endif
diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h
new file mode 100644
index 0000000..e0011ed
--- /dev/null
+++ b/include/configs/slimbootloader.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef __SLIMBOOTLOADER_CONFIG_H__
+#define __SLIMBOOTLOADER_CONFIG_H__
+
+#include <configs/x86-common.h>
+
+/*
+ * By default, CONFIG_SYS_NS16550_PORT_MAPPED is enabled for port io serial.
+ * To use mmio base serial, enable CONFIG_SYS_NS16550_MEM32 and disable
+ * CONFIG_SYS_NS16550_PORT_MAPPED until ns16550 driver supports serial port
+ * configuration in run-time.
+ *
+ * #define CONFIG_SYS_NS16550_MEM32
+ * #undef CONFIG_SYS_NS16550_PORT_MAPPED
+ */
+#ifdef CONFIG_SYS_NS16550_MEM32
+#undef CONFIG_SYS_NS16550_PORT_MAPPED
+#endif
+
+#define CONFIG_STD_DEVICES_SETTINGS		\
+	"stdin=serial,i8042-kbd,usbkbd\0"	\
+	"stdout=serial\0"			\
+	"stderr=serial\0"
+
+/*
+ * Override CONFIG_EXTRA_ENV_SETTINGS in x86-common.h
+ */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_STD_DEVICES_SETTINGS		\
+	"netdev=eth0\0"				\
+	"consoledev=ttyS0\0"			\
+	"ramdiskaddr=0x4000000\0"		\
+	"ramdiskfile=initrd\0"			\
+	"bootdev=usb\0"				\
+	"bootdevnum=0\0"			\
+	"bootdevpart=0\0"			\
+	"bootfsload=fatload\0"			\
+	"bootusb=setenv bootdev usb; boot\0"	\
+	"bootscsi=setenv bootdev scsi; boot\0"	\
+	"bootmmc=setenv bootdev mmc; boot\0"	\
+	"bootargs=console=ttyS0,115200 console=tty0\0"
+
+/*
+ * Override CONFIG_BOOTCOMMAND in x86-common.h
+ */
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND						\
+	"if test ${bootdev} = \"usb\"; then ${bootdev} start; fi; "	\
+	"if test ${bootdev} = \"scsi\"; then ${bootdev} scan; fi; "	\
+	"${bootdev} info; "						\
+	"${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} "	\
+	"${loadaddr} ${bootfile}; "					\
+	"${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} "	\
+	"${ramdiskaddr} ${ramdiskfile}; "				\
+	"zboot ${loadaddr} 0 ${ramdiskaddr} ${filesize}"
+
+#endif /* __SLIMBOOTLOADER_CONFIG_H__ */
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
new file mode 100644
index 0000000..c1a43a5
--- /dev/null
+++ b/include/configs/smartweb.h
@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2010
+ * Achim Ehrlich <aehrlich@taskit.de>
+ * taskit GmbH <www.taskit.de>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * (C) Copyright 2014
+ * Heiko Schocher <hs@denx.de>
+ * DENX Software Engineering GmbH
+ *
+ * Configuation settings for the smartweb.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+#include <linux/sizes.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
+ * program. Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432MHz crystal */
+
+/* misc settings */
+#define CONFIG_CMDLINE_TAG		/* pass commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS	/* pass memory defs to kernel */
+#define CONFIG_INITRD_TAG		/* pass initrd param to kernel */
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY	/* U-Boot is loaded by a bootloader */
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS    32
+
+/* setting board specific options */
+#define CONFIG_MACH_TYPE		MACH_TYPE_SMARTWEB
+#define CONFIG_ENV_OVERWRITE    1 /* Overwrite ethaddr / serial# */
+#define CONFIG_SYS_AUTOLOAD "yes"
+#define CONFIG_RESET_TO_RETRY
+
+/* The LED PINs */
+#define CONFIG_RED_LED			AT91_PIN_PA9
+#define CONFIG_GREEN_LED		AT91_PIN_PA6
+
+/*
+ * SDRAM: 1 bank, 64 MB, base address 0x20000000
+ * Already initialized before u-boot gets started.
+ */
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		(64 * SZ_1M)
+
+/*
+ * Perform a SDRAM Memtest from the start of SDRAM
+ * till the beginning of the U-Boot position in RAM.
+ */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN \
+	ROUND(3 * CONFIG_ENV_SIZE + (4 * SZ_1M), 0x1000)
+
+/* NAND flash settings */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO		/* enable the GPIO features */
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+
+/*
+ * Ethernet configuration
+ *
+ */
+#define CONFIG_MACB
+#define CONFIG_RMII			/* use reduced MII inteface */
+#define CONFIG_NET_RETRY_COUNT	20      /* # of DHCP/BOOTP retries */
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* BOOTP and DHCP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv autoload yes; setenv autoboot yes; "			\
+	"setenv bootargs ${basicargs} ${mtdparts} "			\
+	"root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; "	\
+	"dhcp"
+
+#if !defined(CONFIG_SPL_BUILD)
+/* USB configuration */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
+/* USB DFU support */
+
+#define CONFIG_USB_GADGET_AT91
+
+/* DFU class support */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_1M
+#define DFU_MANIFEST_POLL_TIMEOUT	25000
+#endif
+
+/* General Boot Parameter */
+#define CONFIG_BOOTCOMMAND		"run flashboot"
+#define CONFIG_SYS_CBSIZE		512
+
+/*
+ * RAM Memory address where to put the
+ * Linux Kernel befor starting.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x22000000
+
+/*
+ * The NAND Flash partitions:
+ */
+#define CONFIG_ENV_OFFSET_REDUND	(0x180000)
+#define CONFIG_ENV_RANGE		(SZ_512K)
+
+/*
+ * Predefined environment variables.
+ * Usefull to define some easy to use boot commands.
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+									\
+	"basicargs=console=ttyS0,115200\0"				\
+									\
+	"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x301000
+#define CONFIG_SPL_STACK_R
+#define CONFIG_SPL_STACK_R_ADDR		CONFIG_SYS_TEXT_BASE
+#else
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above that
+ * address while providing maximum stack area below.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		(SZ_4K)
+
+#define CONFIG_SPL_BSS_START_ADDR	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SPL_BSS_MAX_SIZE		(SZ_16K)
+#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
+					CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
+
+#define CONFIG_SYS_NAND_ENABLE_PIN_SPL	(2*32 + 14)
+#define CONFIG_SYS_USE_NANDFLASH	1
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_SIZE		(SZ_256M)
+#define CONFIG_SYS_NAND_PAGE_SIZE	SZ_2K
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(SZ_128K)
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		(198656000/2)
+#define AT91_PLL_LOCK_TIMEOUT		1000000
+#define CONFIG_SYS_AT91_PLLA		0x2060bf09
+#define CONFIG_SYS_MCKR			0x100
+#define CONFIG_SYS_MCKR_CSS		(0x02 | CONFIG_SYS_MCKR)
+#define CONFIG_SYS_AT91_PLLB		0x10483f0e
+
+#define CONFIG_SPL_PAD_TO		CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_SPL_LEN		CONFIG_SPL_PAD_TO
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
new file mode 100644
index 0000000..82251b3
--- /dev/null
+++ b/include/configs/smdk5250.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG SMDK5250 board.
+ */
+
+#ifndef __CONFIG_SMDK_H
+#define __CONFIG_SMDK_H
+
+#include <configs/exynos5250-common.h>
+#include <configs/exynos5-dt-common.h>
+#include <configs/exynos5-common.h>
+
+#undef CONFIG_EXYNOS_FB
+#undef CONFIG_EXYNOS_DP
+#undef CONFIG_KEYBOARD
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#endif	/* __CONFIG_SMDK_H */
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
new file mode 100644
index 0000000..14ec099
--- /dev/null
+++ b/include/configs/smdk5420.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG SMDK5420 board.
+ */
+
+#ifndef __CONFIG_SMDK5420_H
+#define __CONFIG_SMDK5420_H
+
+#include <configs/exynos5420-common.h>
+#include <configs/exynos5-dt-common.h>
+#include <configs/exynos5-common.h>
+
+#undef CONFIG_EXYNOS_FB
+#undef CONFIG_EXYNOS_DP
+
+#undef CONFIG_KEYBOARD
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_SMDK5420			/* which is in a SMDK5420 */
+
+#define CONFIG_SYS_SDRAM_BASE	0x20000000
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
+
+/* select serial console configuration */
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+/* USB */
+#define CONFIG_USB_XHCI_EXYNOS
+
+/* DRAM Memory Banks */
+#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
+
+#endif	/* __CONFIG_SMDK5420_H */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
new file mode 100644
index 0000000..1d09792
--- /dev/null
+++ b/include/configs/smdkc100.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * HeungJun Kim <riverful.kim@samsung.com>
+ * Inki Dae <inki.dae@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG SMDKC100 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
+#define CONFIG_S5P		1	/* which is in a S5P Family */
+#define CONFIG_S5PC100		1	/* which is in a S5PC100 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+/* input clock of PLL: SMDKC100 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		12000000
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE		0x30000000
+
+/* Text Base */
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+
+/*
+ * select serial console configuration
+ */
+
+/* PWM */
+#define CONFIG_PWM			1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOOTCOMMAND	"run ubifsboot"
+
+#define CONFIG_RAMDISK_BOOT	"root=/dev/ram0 rw rootfstype=ext2" \
+				" console=ttySAC0,115200n8" \
+				" mem=128M"
+
+#define CONFIG_COMMON_BOOT	"console=ttySAC0,115200n8" \
+				" mem=128M " \
+				" " CONFIG_MTDPARTS_DEFAULT
+
+#define CONFIG_UPDATEB	"updateb=onenand erase 0x0 0x40000;" \
+			" onenand write 0x32008000 0x0 0x40000\0"
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_UPDATEB \
+	"updatek=" \
+		"onenand erase 0x60000 0x300000;" \
+		"onenand write 0x31008000 0x60000 0x300000\0" \
+	"updateu=" \
+		"onenand erase block 147-4095;" \
+		"onenand write 0x32000000 0x1260000 0x8C0000\0" \
+	"bootk=" \
+		"onenand read 0x30007FC0 0x60000 0x300000;" \
+		"bootm 0x30007FC0\0" \
+	"flashboot=" \
+		"set bootargs root=/dev/mtdblock${bootblock} " \
+		"rootfstype=${rootfstype} " \
+		"ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \
+		"run bootk\0" \
+	"ubifsboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		" ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"android=" \
+		"set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \
+		"rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"nfsboot=" \
+		"set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \
+		"nfsroot=${nfsroot},nolock " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+		"${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"ramboot=" \
+		"set bootargs " CONFIG_RAMDISK_BOOT \
+		" initrd=0x33000000,8M ramdisk=8192\0" \
+	"rootfstype=cramfs\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"meminfo=mem=128M\0" \
+	"nfsroot=/nfsroot/arm\0" \
+	"bootblock=5\0" \
+	"ubiblock=4\0" \
+	"ubi=enabled"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5e00000)
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	(128 << 20)	/* 0x8000000, 128 MB Bank #1 */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 KiB */
+
+#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
+#define CONFIG_ENABLE_MMU
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+#define CONFIG_SYS_MAPPED_RAM_BASE	0xc0000000
+#else
+#define CONFIG_SYS_MAPPED_RAM_BASE	CONFIG_SYS_SDRAM_BASE
+#endif
+
+/*-----------------------------------------------------------------------
+ * Boot configuration
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128KiB, 0x20000 */
+#define CONFIG_ENV_ADDR			(256 << 10)	/* 256KiB, 0x40000 */
+#define CONFIG_ENV_OFFSET		(256 << 10)	/* 256KiB, 0x40000 */
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND		1
+#define CONFIG_SYS_ONENAND_BASE		0xE7100000
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
+/*
+ * Ethernet Contoller driver
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_ENV_SROM_BANK   3       /* Select SROM Bank-3 for Ethernet*/
+#endif /* CONFIG_CMD_NET */
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h
new file mode 100644
index 0000000..68af0ef
--- /dev/null
+++ b/include/configs/smdkv310.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "exynos4-common.h"
+
+#undef CONFIG_BOARD_COMMON
+#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
+#undef CONFIG_REVISION_TAG
+
+/* High Level Configuration Options */
+#define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
+
+/* Mach Type */
+#define CONFIG_MACH_TYPE		MACH_TYPE_SMDKV310
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+/* Handling Sleep Mode*/
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+/* select serial console configuration */
+#define EXYNOS4_DEFAULT_UART_OFFSET	0x010000
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* MMC SPL */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define COPY_BL2_FNPTR_ADDR	0x00002488
+
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+/* SMDKV310 has 4 bank of DRAM */
+#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+
+/* FLASH and environment organization */
+
+#define CONFIG_CLK_1000_400_200
+
+/* MIU (Memory Interleaving Unit) */
+#define CONFIG_MIU_2BIT_INTERLEAVED
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
+#define RESERVE_BLOCK_SIZE		(512)
+#define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
+
+#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x02040000
+
+/* U-Boot copy size from boot Media to DRAM.*/
+#define	COPY_BL2_SIZE		0x80000
+#define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
+#define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)
+
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_ENV_SROM_BANK		1
+#endif /*CONFIG_CMD_NET*/
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
new file mode 100644
index 0000000..b0408a5
--- /dev/null
+++ b/include/configs/snapper9260.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Bluewater Systems Snapper 9260 and 9G20 modules
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SoC type is defined in boards.cfg */
+#include <asm/hardware.h>
+#include <linux/sizes.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* External Crystal, in Hz */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+
+/* CPU */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024) /* 64MB */
+#define CONFIG_SYS_INIT_SP_ADDR		(ATMEL_BASE_SRAM1 + 0x1000 - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Mem test settings */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
+
+/* NAND Flash */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+#define CONFIG_TFTP_PORT
+#define CONFIG_TFTP_TSIZE
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
+/* GPIOs and IO expander */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP		1
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x28
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x28, 16} }
+
+/* UARTs/Serial console */
+#define CONFIG_ATMEL_USART
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#endif
+
+/* I2C - Bit-bashed */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define I2C_INIT do {							\
+		at91_set_gpio_output(AT91_PIN_PA23, 1);			\
+		at91_set_gpio_output(AT91_PIN_PA24, 1);			\
+		at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1);	\
+		at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1);	\
+	} while (0)
+#define I2C_SOFT_DECLARATIONS
+#define I2C_ACTIVE
+#define I2C_TRISTATE	at91_set_gpio_input(AT91_PIN_PA23, 1);
+#define I2C_READ	at91_get_gpio_value(AT91_PIN_PA23);
+#define I2C_SDA(bit) do {						\
+		if (bit) {						\
+			at91_set_gpio_input(AT91_PIN_PA23, 1);		\
+		} else {						\
+			at91_set_gpio_output(AT91_PIN_PA23, 1);		\
+			at91_set_gpio_value(AT91_PIN_PA23, bit);	\
+		}							\
+	} while (0)
+#define I2C_SCL(bit)	at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
+#define I2C_DELAY	udelay(2)
+
+/* Boot options */
+#define CONFIG_SYS_LOAD_ADDR		0x23000000
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Environment settings */
+#define CONFIG_ENV_OVERWRITE
+
+/* Console settings */
+
+/* U-Boot memory settings */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
new file mode 100644
index 0000000..ffcfdca
--- /dev/null
+++ b/include/configs/snapper9g45.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Bluewater Systems Snapper 9G45 module
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SoC type is defined in boards.cfg */
+#include <asm/hardware.h>
+#include <linux/sizes.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+
+/* CPU */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS6
+#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024) /* 64MB */
+#define CONFIG_SYS_INIT_SP_ADDR		(ATMEL_BASE_SRAM + 0x1000 - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Mem test settings */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
+
+/* NAND Flash */
+#define CONFIG_SYS_NAND_ECC_BASE	ATMEL_BASE_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC8
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+#define CONFIG_TFTP_PORT
+#define CONFIG_TFTP_TSIZE
+
+/* MMC */
+#define CONFIG_GENERIC_ATMEL_MCI
+
+/* LCD */
+#define CONFIG_ATMEL_LCD
+#define CONFIG_GURNARD_SPLASH
+
+/* GPIOs and IO expander */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP		1
+
+/* UARTs/Serial console */
+#define CONFIG_ATMEL_USART
+
+/* Boot options */
+#define CONFIG_SYS_LOAD_ADDR		0x23000000
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Environment settings */
+#define CONFIG_ENV_OVERWRITE
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+	"ethaddr=00:00:00:00:00:00\0" \
+	"serial=0\0" \
+	"stdout=serial_atmel\0" \
+	"stderr=serial_atmel\0" \
+	"stdin=serial_atmel\0" \
+	"bootlimit=3\0" \
+	"loadaddr=0x71000000\0" \
+	"board_rev=2\0" \
+	"bootfile=/tftpboot/uImage\0" \
+	"bootargs_def=console=ttyS0,115200 panic=5 quiet lpj=997376\0" \
+	"nfsroot=/export/root\0" \
+	"boot_working=setenv bootargs $bootargs_def; nboot $loadaddr 0 0x20c0000 && bootm\0" \
+	"boot_safe=setenv bootargs $bootargs_def; nboot $loadaddr 0 0xc0000 && bootm\0" \
+	"boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \
+	"boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \
+	"boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \
+	"bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \
+	"altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0"
+
+/* Console settings */
+
+/* U-Boot memory settings */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
+
+/* Command line configuration */
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_CACHE
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
new file mode 100644
index 0000000..0e2fcc3
--- /dev/null
+++ b/include/configs/sniper.h
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * LG Optimus Black codename sniper config
+ *
+ * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+/*
+ * CPU
+ */
+
+#define CONFIG_ARM_ARCH_CP15_ERRATA
+
+/*
+ * Board
+ */
+
+/*
+ * Clocks
+ */
+
+#define CONFIG_SYS_TIMERBASE	OMAP34XX_GPT2
+#define CONFIG_SYS_PTV		2
+
+#define V_NS16550_CLK		48000000
+#define V_OSCK			26000000
+#define V_SCLK			(V_OSCK >> 1)
+
+/*
+ * DRAM
+ */
+
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * Memory
+ */
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 + CONFIG_ENV_SIZE)
+
+/*
+ * I2C
+ */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * Input
+ */
+
+/*
+ * SPL
+ */
+
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		(512 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(1024 * 1024)
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION		1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME			"u-boot.img"
+
+#define CONFIG_SYS_CBSIZE	512
+
+/*
+ * Serial
+ */
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#endif
+
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 4800, 9600, 19200, 38400, 57600, \
+					  115200 }
+
+/*
+ * Environment
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_addr_r=0x82000000\0" \
+	"loadaddr=0x82000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"fdtaddr=0x88000000\0" \
+	"ramdisk_addr_r=0x88080000\0" \
+	"pxefile_addr_r=0x80100000\0" \
+	"scriptaddr=0x80000000\0" \
+	"bootm_size=0x10000000\0" \
+	"boot_mmc_dev=0\0" \
+	"kernel_mmc_part=3\0" \
+	"recovery_mmc_part=4\0" \
+	"fdtfile=omap3-sniper.dtb\0" \
+	"bootfile=/boot/extlinux/extlinux.conf\0" \
+	"bootargs=console=ttyO2,115200 vram=5M,0x9FA00000 omapfb.vram=0:5M\0"
+
+/*
+ * ATAGs
+ */
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/*
+ * Boot
+ */
+
+#define CONFIG_SYS_LOAD_ADDR	0x82000000
+
+#define CONFIG_BOOTCOMMAND \
+	"setenv boot_mmc_part ${kernel_mmc_part}; " \
+	"if test reboot-${reboot-mode} = reboot-r; then " \
+	"echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; " \
+	"if test reboot-${reboot-mode} = reboot-b; then " \
+	"echo fastboot; fastboot 0; fi; " \
+	"part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \
+	"part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \
+	"mmc dev ${boot_mmc_dev}; " \
+	"mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \
+	"bootm ${kernel_addr_r};"
+
+/*
+ * Defaults
+ */
+
+#include <config_defaults.h>
+
+#endif
diff --git a/include/configs/snow.h b/include/configs/snow.h
new file mode 100644
index 0000000..c546a5a
--- /dev/null
+++ b/include/configs/snow.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 Snow board.
+ */
+
+#ifndef __CONFIG_SNOW_H
+#define __CONFIG_SNOW_H
+
+#define EXYNOS_FDTFILE_SETTING \
+	"fdtfile=exynos5250-snow.dtb\0"
+
+#include <configs/exynos5250-common.h>
+#include <configs/exynos5-dt-common.h>
+#include <configs/exynos5-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#endif	/* __CONFIG_SNOW_H */
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 0000000..645e66e
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2015-2019 Altera Corporation <www.altera.com>
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include <asm/arch/base_addr_a10.h>
+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/*
+ * U-Boot general configurations
+ */
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE		0x40000000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+
+/* SPL memory allocation configuration, this is for FAT implementation */
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00015000
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFGPA_ARRIA10_H__ */
diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
new file mode 100644
index 0000000..af6137a
--- /dev/null
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
+#define __CONFIG_SOCFPGA_ARRIA5_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFPGA_ARRIA5_H__ */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
new file mode 100644
index 0000000..94268ed
--- /dev/null
+++ b/include/configs/socfpga_common.h
@@ -0,0 +1,268 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+#ifndef __CONFIG_SOCFPGA_COMMON_H__
+#define __CONFIG_SOCFPGA_COMMON_H__
+
+/*
+ * High level configuration
+ */
+#define CONFIG_CLOCKS
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1			0x0
+#define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
+/* SPL memory allocation configuration, this is for FAT implementation */
+#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x10000
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE)
+#endif
+
+/*
+ * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
+ * SRAM as bootcounter storage. Make sure to not put the stack directly
+ * at this address to not overwrite the bootcounter by checking, if the
+ * bootcounter address is located in the internal SRAM.
+ */
+#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) &&	\
+     (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR +	\
+				   CONFIG_SYS_INIT_RAM_SIZE)))
+#define CONFIG_SPL_STACK		CONFIG_SYS_BOOTCOUNT_ADDR
+#else
+#define CONFIG_SPL_STACK			\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+#endif
+
+/*
+ * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
+ * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
+ * in U-Boot pre-reloc is higher than in SPL.
+ */
+#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SPL_STACK_R_ADDR
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SPL_STACK
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+						/* Print buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+
+/*
+ * Cache
+ */
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
+
+/*
+ * Ethernet on SoC (EMAC)
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_DW_ALTDESCRIPTOR
+#endif
+
+/*
+ * FPGA Driver
+ */
+#ifdef CONFIG_CMD_FPGA
+#define CONFIG_FPGA_COUNT		1
+#endif
+
+/*
+ * L4 OSC1 Timer 0
+ */
+#ifndef CONFIG_TIMER
+/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+#define CONFIG_SYS_TIMER_RATE		25000000
+#endif
+
+/*
+ * L4 Watchdog
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#define CONFIG_DW_WDT_CLOCK_KHZ		25000
+#endif
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+/* FIXME */
+/* using smaller max blk cnt to avoid flooding the limited stack we have */
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
+#endif
+
+/*
+ * NAND Support
+ */
+#ifdef CONFIG_NAND_DENALI
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
+#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
+#endif
+
+/*
+ * QSPI support
+ */
+/* Enable multiple SPI NOR flash manufacturers */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SPI_FLASH_MTD
+#endif
+/* QSPI reference clock */
+#ifndef __ASSEMBLY__
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
+#endif
+
+/*
+ * USB
+ */
+
+/*
+ * USB Gadget (DFU, UMS)
+ */
+#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(16 * 1024 * 1024)
+#define DFU_DEFAULT_POLL_TIMEOUT	300
+
+/* USB IDs */
+#define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
+#define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
+#endif
+
+/*
+ * U-Boot environment
+ */
+#if !defined(CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#endif
+
+/* Environment for SDMMC boot */
+#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_MMC_ENV_DEV		0 /* device 0 */
+#define CONFIG_ENV_OFFSET		(34 * 512) /* just after the GPT */
+#endif
+
+/* Environment for QSPI boot */
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_OFFSET		0x00100000
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#endif
+
+/*
+ * SPL
+ *
+ * SRAM Memory layout for gen 5:
+ *
+ * 0xFFFF_0000 ...... Start of SRAM
+ * 0xFFFF_xxxx ...... Top of stack (grows down)
+ * 0xFFFF_yyyy ...... Global Data
+ * 0xFFFF_zzzz ...... Malloc area
+ * 0xFFFF_FFFF ...... End of SRAM
+ *
+ * SRAM Memory layout for Arria 10:
+ * 0xFFE0_0000 ...... Start of SRAM (bottom)
+ * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
+ * 0xFFEy_yyyy ...... Global Data
+ * 0xFFEz_zzzz ...... Malloc area (grows up to top)
+ * 0xFFE3_FFFF ...... End of SRAM (top)
+ */
+#ifndef CONFIG_SPL_TEXT_BASE
+#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
+#endif
+
+/* SPL SDMMC boot support */
+#ifdef CONFIG_SPL_MMC_SUPPORT
+#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#endif
+#else
+#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	1
+#endif
+#endif
+
+/* SPL QSPI boot support */
+
+/* SPL NAND boot support */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x100000
+#endif
+#endif
+
+/* Extra Environment */
+#ifndef CONFIG_SPL_BUILD
+
+#ifdef CONFIG_CMD_DHCP
+#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
+#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
+#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
+#else
+#define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_PXE(func) \
+	BOOT_TARGET_DEVICES_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"bootm_size=0xa000000\0" \
+	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
+	"fdt_addr_r=0x02000000\0" \
+	"scriptaddr=0x02100000\0" \
+	"pxefile_addr_r=0x02200000\0" \
+	"ramdisk_addr_r=0x02300000\0" \
+	"socfpga_legacy_reset_compat=1\0" \
+	BOOTENV
+
+#endif
+#endif
+
+#endif	/* __CONFIG_SOCFPGA_COMMON_H__ */
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
new file mode 100644
index 0000000..028db2a
--- /dev/null
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
+#define __CONFIG_SOCFPGA_CYCLONE5_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFPGA_CYCLONE5_H__ */
diff --git a/include/configs/socfpga_dbm_soc1.h b/include/configs/socfpga_dbm_soc1.h
new file mode 100644
index 0000000..befaeaa
--- /dev/null
+++ b/include/configs/socfpga_dbm_soc1.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIG_DEVBOARDS_DBM_SOC1_H__
+#define __CONFIG_DEVBOARDS_DBM_SOC1_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB */
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE		"fitImage"
+#define CONFIG_BOOTCOMMAND	"run mmc_mmc"
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Environment is in MMC */
+#define CONFIG_ENV_OVERWRITE
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"consdev=ttyS0\0"						\
+	"baudrate=115200\0"						\
+	"bootscript=boot.scr\0"						\
+	"bootdev=/dev/mmcblk0p2\0"					\
+	"rootdev=/dev/mmcblk0p3\0"					\
+	"netdev=eth0\0"							\
+	"hostname=dbm_soc1\0"						\
+	"kernel_addr_r=0x10000000\0"					\
+	"dfu_alt_info=mmc raw 0 3867148288\0"				\
+	"update_filename=u-boot-with-spl.sfp\0"				\
+	"update_sd_offset=0x800\0"					\
+	"update_sd="		/* Update the SD firmware partition */	\
+		"if mmc rescan ; then "					\
+		"if tftp ${update_filename} ; then "			\
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "				\
+		"mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; "	\
+		"fi ; "							\
+		"fi\0"							\
+	"fpga_filename=output_file.rbf\0"				\
+	"load_fpga="		/* Load FPGA bitstream */		\
+		"if tftp ${fpga_filename} ; then "			\
+		"fpga load 0 $loadaddr $filesize ; "			\
+		"bridge enable ; "					\
+		"fi\0"							\
+	"addcons="							\
+		"setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"addip="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+			"${netmask}:${hostname}:${netdev}:off\0"	\
+	"addmisc="							\
+		"setenv bootargs ${bootargs} ${miscargs}\0"		\
+	"addargs=run addcons addmisc\0"					\
+	"mmcload="							\
+		"mmc rescan ; "						\
+		"load mmc 0:2 ${kernel_addr_r} ${bootfile}\0"		\
+	"netload="							\
+		"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0"	\
+	"miscargs=nohlt panic=1\0"					\
+	"mmcargs=setenv bootargs root=${rootdev} rw rootwait\0"		\
+	"nfsargs="							\
+		"setenv bootargs root=/dev/nfs rw "			\
+			"nfsroot=${serverip}:${rootpath},v3,tcp\0"	\
+	"mmc_mmc="							\
+		"run mmcload mmcargs addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"mmc_nfs="							\
+		"run mmcload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_mmc="							\
+		"run netload mmcargs addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_nfs="							\
+		"run netload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"try_bootscript="						\
+		"mmc rescan;"						\
+		"if test -e mmc 0:2 ${bootscript} ; then "		\
+		"if load mmc 0:2 ${kernel_addr_r} ${bootscript};"	\
+		"then ; "						\
+			"echo Running bootscript... ; "			\
+			"source ${kernel_addr_r} ; "			\
+		"fi ; "							\
+		"fi\0"							\
+	"socfpga_legacy_reset_compat=1\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_DEVBOARDS_DBM_SOC1_H__ */
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
new file mode 100644
index 0000000..21108e3
--- /dev/null
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIG_TERASIC_DE0_H__
+#define __CONFIG_TERASIC_DE0_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB */
+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_TERASIC_DE0_H__ */
diff --git a/include/configs/socfpga_de10_nano.h b/include/configs/socfpga_de10_nano.h
new file mode 100644
index 0000000..d85f98f
--- /dev/null
+++ b/include/configs/socfpga_de10_nano.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, Intel Corporation
+ */
+#ifndef __CONFIG_TERASIC_DE10_H__
+#define __CONFIG_TERASIC_DE10_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB */
+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_TERASIC_DE10_H__ */
diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h
new file mode 100644
index 0000000..9919d29
--- /dev/null
+++ b/include/configs/socfpga_de1_soc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIG_TERASIC_DE1_SOC_H__
+#define __CONFIG_TERASIC_DE1_SOC_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB */
+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_TERASIC_DE1_SOC_H__ */
diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h
new file mode 100644
index 0000000..c4da594
--- /dev/null
+++ b/include/configs/socfpga_is1.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2016 Pavel Machek <pavel@denx.de>
+ */
+#ifndef __CONFIG_SOCFPGA_IS1_H__
+#define __CONFIG_SOCFPGA_IS1_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x10000000
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE		"zImage"
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_ARP_TIMEOUT		500UL
+#endif
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+/*
+ * Bootcounter
+ */
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+#endif	/* __CONFIG_SOCFPGA_IS1_H__ */
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
new file mode 100644
index 0000000..590a9af
--- /dev/null
+++ b/include/configs/socfpga_mcvevk.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIG_ARIES_MCVEVK_H__
+#define __CONFIG_ARIES_MCVEVK_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on MCV */
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE		"fitImage"
+#define CONFIG_BOOTCOMMAND	"run mmc_mmc"
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Environment is in MMC */
+#define CONFIG_ENV_OVERWRITE
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"consdev=ttyS0\0"						\
+	"baudrate=115200\0"						\
+	"bootscript=boot.scr\0"						\
+	"setuuid=part uuid mmc 0:3 uuid\0"				\
+	"netdev=eth0\0"							\
+	"hostname=mcvevk\0"						\
+	"kernel_addr_r=0x10000000\0"					\
+	"socfpga_legacy_reset_compat=1\0"				\
+	"bootm_size=0xa000000\0"					\
+	"dfu_alt_info=mmc raw 0 3867148288\0"				\
+	"update_filename=u-boot-with-spl.sfp\0"				\
+	"update_sd_offset=0x800\0"					\
+	"update_sd="		/* Update the SD firmware partition */	\
+		"if mmc rescan ; then "					\
+		"if tftp ${update_filename} ; then "			\
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "				\
+		"mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; "	\
+		"fi ; "							\
+		"fi\0"							\
+	"update_qspi_offset=0x0\0"					\
+	"update_qspi="		/* Update the QSPI firmware */		\
+		"if sf probe ; then "					\
+		"if tftp ${update_filename} ; then "			\
+		"sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
+		"fi ; "							\
+		"fi\0"							\
+	"fpga_filename=output_file.rbf\0"				\
+	"load_fpga="		/* Load FPGA bitstream */		\
+		"if tftp ${fpga_filename} ; then "			\
+		"fpga load 0 $loadaddr $filesize ; "			\
+		"bridge enable ; "					\
+		"fi\0"							\
+	"addcons="							\
+		"setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"addip="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+			"${netmask}:${hostname}:${netdev}:off\0"	\
+	"addmisc="							\
+		"setenv bootargs ${bootargs} ${miscargs}\0"		\
+	"addargs=run addcons addmisc\0"					\
+	"mmcload="							\
+		"mmc rescan ; "						\
+		"load mmc 0:2 ${kernel_addr_r} ${bootfile}\0"		\
+	"netload="							\
+		"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0"	\
+	"miscargs=nohlt panic=1\0"					\
+	"mmcargs=setenv bootargs root=PARTUUID=${uuid} rw rootwait\0"	\
+	"nfsargs="							\
+		"setenv bootargs root=/dev/nfs rw "			\
+			"nfsroot=${serverip}:${rootpath},v3,tcp\0"	\
+	"mmc_mmc="							\
+	"run mmcload setuuid mmcargs addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"mmc_nfs="							\
+		"run mmcload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_mmc="							\
+	"run netload setuuid mmcargs addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_nfs="							\
+		"run netload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"try_bootscript="						\
+		"mmc rescan;"						\
+		"if test -e mmc 0:2 ${bootscript} ; then "		\
+		"if load mmc 0:2 ${kernel_addr_r} ${bootscript};"	\
+		"then ; "						\
+			"echo Running bootscript... ; "			\
+			"source ${kernel_addr_r} ; "			\
+		"fi ; "							\
+		"fi\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_ARIES_MCVEVK_H__ */
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
new file mode 100644
index 0000000..9729999
--- /dev/null
+++ b/include/configs/socfpga_sockit.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIG_TERASIC_SOCKIT_H__
+#define __CONFIG_TERASIC_SOCKIT_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_TERASIC_SOCKIT_H__ */
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
new file mode 100644
index 0000000..7faea15
--- /dev/null
+++ b/include/configs/socfpga_socrates.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIG_SOCFPGA_SOCRATES_H__
+#define __CONFIG_SOCFPGA_SOCRATES_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCrates */
+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFPGA_SOCRATES_H__ */
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
new file mode 100644
index 0000000..3a8ccc3
--- /dev/null
+++ b/include/configs/socfpga_sr1500.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+#ifndef __CONFIG_SOCFPGA_SR1500_H__
+#define __CONFIG_SOCFPGA_SR1500_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */
+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
+/* The PHY is autodetected, so no MII PHY address is needed here */
+#define PHY_ANEG_TIMEOUT	8000
+
+/* Enable SPI NOR flash reset, needed for SPI booting */
+#define CONFIG_SPI_N25Q256A_RESET
+
+/*
+ * Bootcounter
+ */
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* Environment setting for SPI flash */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_ENV_OFFSET	0x000e0000
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFPGA_SR1500_H__ */
diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h
new file mode 100644
index 0000000..8e6ecf4
--- /dev/null
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -0,0 +1,208 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_STRATIX10_H__
+#define __CONFIG_SOCFGPA_STRATIX10_H__
+
+#include <asm/arch/base_addr_s10.h>
+#include <asm/arch/handoff_s10.h>
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_LOADADDR			0x2000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_REMAKE_ELF
+/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */
+#define CPU_RELEASE_ADDR		0xFFD12210
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_MEM_RESERVE_SECURE	0	/* using OCRAM, not DDR */
+
+/*
+ * U-Boot console configurations
+ */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN		(32 * 1024 * 1024)
+
+/*
+ * U-Boot run time memory configurations
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x40000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR  \
+					+ CONFIG_SYS_INIT_RAM_SIZE \
+					- S10_HANDOFF_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_SP_ADDR)
+#define CONFIG_SYS_MALLOC_LEN		(5 * 1024 * 1024)
+
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* device 0 */
+#define CONFIG_ENV_OFFSET		512	/* just after the MBR */
+
+/*
+ * QSPI support
+ */
+ #ifdef CONFIG_CADENCE_QSPI
+/* Enable it if you want to use dual-stacked mode */
+/*#define CONFIG_QSPI_RBF_ADDR		0x720000*/
+
+/* Flash device info */
+
+/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET		0x710000
+#define CONFIG_ENV_SIZE			(4 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(4 * 1024)
+#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT			"nor0=ff705000.spi.0"
+#endif /* CONFIG_SPL_BUILD */
+
+#ifndef __ASSEMBLY__
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
+#endif
+
+#endif /* CONFIG_CADENCE_QSPI */
+
+/*
+ * Boot arguments passed to the boot command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will override also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "earlycon"
+#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \
+			   "run mmcboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"bootfile=Image\0" \
+	"fdt_addr=8000000\0" \
+	"fdtimage=socfpga_stratix10_socdk.dtb\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"booti ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootfile};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"linux_qspi_enable=if sf probe; then " \
+		"echo Enabling QSPI at Linux DTB...;" \
+		"fdt addr ${fdt_addr}; fdt resize;" \
+		"fdt set /soc/spi@ff8d2000 status okay;" \
+		"fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \
+		" ${qspi_clock}; fi; \0" \
+	"scriptaddr=0x02100000\0" \
+	"scriptfile=u-boot.scr\0" \
+	"fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+		   "then source ${scriptaddr}; fi\0" \
+	"socfpga_legacy_reset_compat=1\0"
+
+/*
+ * Generic Interrupt Controller Definitions
+ */
+#define CONFIG_GICV2
+
+/*
+ * External memory configurations
+ */
+#define PHYS_SDRAM_1			0x0
+#define PHYS_SDRAM_1_SIZE		(1 * 1024 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_MEMTEST_START	0
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE - 0x200000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_CLK		100000000
+#define CONFIG_SYS_NS16550_MEM32
+
+/*
+ * Timer & watchdog configurations
+ */
+#define COUNTER_FREQUENCY		400000000
+
+/*
+ * SDMMC configurations
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256
+#endif
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_DW_ALTDESCRIPTOR
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * L4 Watchdog
+ */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#ifndef __ASSEMBLY__
+unsigned int cm_get_l4_sys_free_clk_hz(void);
+#define CONFIG_DW_WDT_CLOCK_KHZ		(cm_get_l4_sys_free_clk_hz() / 1000)
+#endif
+#endif
+
+/*
+ * SPL memory layout
+ *
+ * On chip RAM
+ * 0xFFE0_0000 ...... Start of OCRAM
+ * SPL code, rwdata
+ * empty space
+ * 0xFFEx_xxxx ...... Top of stack (grows down)
+ * 0xFFEy_yyyy ...... Global Data
+ * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
+ * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB)
+ * 0xFFE3_FFFF ...... End of OCRAM
+ *
+ * SDRAM
+ * 0x0000_0000 ...... Start of SDRAM_1
+ * unused / empty space for image loading
+ * Size 64MB   ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
+ * Size 1MB    ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
+ * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
+ *
+ */
+#define CONFIG_SPL_TARGET		"spl/u-boot-spl.hex"
+#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000	/* 1 MB */
+#define CONFIG_SPL_BSS_START_ADDR	(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
+					- CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR \
+					- CONFIG_SYS_SPL_MALLOC_SIZE)
+
+/* SPL SDMMC boot support */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h
new file mode 100644
index 0000000..debf3ea
--- /dev/null
+++ b/include/configs/socfpga_vining_fpga.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2019 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIG_SOFTING_VINING_FPGA_H__
+#define __CONFIG_SOFTING_VINING_FPGA_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on VINING_FPGA */
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE		"fitImage"
+#define CONFIG_BOOTCOMMAND	"run selboot"
+#define CONFIG_SYS_BOOTM_LEN	0x2000000	/* 32 MiB */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#endif
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME			"socfpga_vining_fpga"
+
+/*
+ * Active LOW GPIO buttons:
+ * A: GPIO 77 ... the button between USB B and ethernet
+ * B: GPIO 78 ... the button between USB A ports
+ *
+ * The logic:
+ *  if button B is pressed, boot recovery system after 10 seconds
+ *  if force_boottype is set, boot system depending on the value in the
+ *                            $force_boottype variable after 1 second
+ *  if button B is not pressed and force_boottype is not set, boot normal
+ *                            Linux system after 5 seconds
+ */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"consdev=ttyS0\0"						\
+	"baudrate=115200\0"						\
+	"bootscript=boot.scr\0"						\
+	"ubimtdnr=5\0"							\
+	"ubimtd=rootfs\0"						\
+	"ubipart=ubi0:vining-fpga-rootfs\0"						\
+	"ubisfcs=1\0"		/* Default is flash at CS#1 */		\
+	"netdev=eth0\0"							\
+	"hostname=vining_fpga\0"					\
+	"kernel_addr_r=0x10000000\0"					\
+	"fdt_addr_r=0x20000000\0"					\
+	"fdt_high=0xffffffff\0"						\
+	"initrd_high=0xffffffff\0"					\
+	"dfu_alt_info=qspi0 sf 0:0;qspi1 sf 0:1\0"			\
+	"mtdparts_0_16m=ff705000.spi.0:" /* 16MiB+128MiB SF config */	\
+		"1m(u-boot),"						\
+		"64k(env1),"						\
+		"64k(env2),"						\
+		"256k(softing1),"					\
+		"256k(softing2),"					\
+		"-(rcvrfs)\0"	/* Recovery */				\
+	"mtdparts_0_256m=ff705000.spi.0:" /* 256MiB(+256MiB) config */	\
+		"1m(u-boot),"						\
+		"64k(env1),"						\
+		"64k(env2),"						\
+		"256k(softing1),"					\
+		"256k(softing2),"					\
+		"14720k(rcvrfs),"	/* Recovery */			\
+		"64m(rootfs),"		/* Root */			\
+		"-(userfs)\0"		/* User */			\
+	"mtdparts_1_128m=ff705000.spi.1:" /* 16MiB+128MiB SF config */	\
+		"64m(rootfs),"						\
+		"-(userfs)\0"						\
+	"mtdparts_1_256m=ff705000.spi.1:" /* 256MiB+256MiB SF config */	\
+		"-(userfs2)\0"						\
+	"update_filename=u-boot-with-spl-dtb.sfp\0"			\
+	"update_qspi_offset=0x0\0"					\
+	"update_qspi="		/* Update the QSPI firmware */		\
+		"if sf probe ; then "					\
+		"if tftp ${update_filename} ; then "			\
+		"sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
+		"fi ; "							\
+		"fi\0"							\
+	"sf_identify="							\
+		"setenv sf_size_0 ; setenv sf_size_1 ; "		\
+		"sf probe 0:0 && setenv sf_size_0 ${sf_size} ; "	\
+		"sf probe 0:1 && setenv sf_size_1 ${sf_size} ; "	\
+		"if test -z \"${sf_size_1}\" ; then "			\
+			/* 1x256MiB SF */				\
+			"setenv mtdparts_0 ${mtdparts_0_256m} ; "	\
+			"setenv mtdparts_1 ; "				\
+		"elif test \"${sf_size_0}\" = \"1000000\" ; then "	\
+			/* 16MiB+128MiB SF */				\
+			"setenv mtdparts_0 ${mtdparts_0_16m} ; "	\
+			"setenv mtdparts_1 ${mtdparts_1_128m} ; "	\
+		"else "							\
+			/* 256MiB+256MiB SF */				\
+			"setenv mtdparts_0 ${mtdparts_0_256m} ; "	\
+			"setenv mtdparts_1 ${mtdparts_1_256m} ; "	\
+		"fi\0"							\
+	"fpga_filename=output_file.rbf\0"				\
+	"load_fpga="		/* Load FPGA bitstream */		\
+		"if tftp ${fpga_filename} ; then "			\
+		"fpga load 0 $loadaddr $filesize ; "			\
+		"bridge enable ; "					\
+		"fi\0"							\
+	"addcons="							\
+		"setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"addip="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+			"${netmask}:${hostname}:${netdev}:off\0"	\
+	"addmisc="							\
+		"setenv bootargs ${bootargs} ${miscargs}\0"		\
+	"addmtd="							\
+		"if test -z \"${sf_size_1}\" ; then "			\
+			"setenv mtdparts \"${mtdparts_0}\" ; "		\
+		"else "							\
+			"setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; "	\
+		"fi ; "							\
+		"setenv bootargs ${bootargs} mtdparts=${mtdparts}\0"	\
+	"addargs=run addcons addmtd addmisc\0"				\
+	"ubiload="							\
+		"ubi part ${ubimtd} ; ubifsmount ${ubipart} ; "		\
+		"ubifsload ${kernel_addr_r} /boot/${bootfile}\0"	\
+	"netload="							\
+		"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0"	\
+	"miscargs=nohlt panic=1\0"					\
+	"ubiargs="							\
+		"setenv bootargs ubi.mtd=${ubimtdnr} "			\
+		"root=${ubipart} rootfstype=ubifs\0"			\
+	"nfsargs="							\
+		"setenv bootargs root=/dev/nfs rw "			\
+			"nfsroot=${serverip}:${rootpath},v3,tcp\0"	\
+	"ubi_sfsel="							\
+		"if test \"${boottype}\" = \"rcvr\" ; then "		\
+			"setenv ubisfcs 0 ; "				\
+			"setenv ubimtd rcvrfs ; "			\
+			"setenv ubimtdnr 5 ; "				\
+			"setenv mtdparts mtdparts=${mtdparts_0} ; "	\
+			"setenv mtdids nor0=ff705000.spi.0 ; "		\
+			"setenv ubipart ubi0:vining-fpga-rootfs ; "	\
+		"else "							\
+			"if test \"${sf_size_0}\" = \"1000000\" ; then "\
+				/* 16MiB+128MiB SF */			\
+				"setenv ubisfcs 1 ; "			\
+				"setenv ubimtd rootfs ; "		\
+				"setenv ubimtdnr 6 ; "			\
+				"setenv mtdparts mtdparts=${mtdparts_1} ; "	\
+				"setenv mtdids nor0=ff705000.spi.1 ; "	\
+				"setenv ubipart ubi0:vining-fpga-rootfs ; "	\
+			"else "						\
+				/* 256MiB(+256MiB) SF */		\
+				"setenv ubisfcs 0 ; "			\
+				"setenv ubimtd rootfs ; "		\
+				"setenv ubimtdnr 6 ; "			\
+				"setenv mtdparts mtdparts=${mtdparts_0} ; "	\
+				"setenv mtdids nor0=ff705000.spi.0 ; "	\
+				"setenv ubipart ubi0:vining-fpga-rootfs ; "	\
+			"fi ; "						\
+		"fi ; "							\
+		"sf probe 0:${ubisfcs}\0"				\
+	"boot_kernel="							\
+		"if test -z \"${sf_size_1}\" ; then " /* 1x256MiB SF */	\
+			"imxtract ${kernel_addr_r} fdt@1 ${fdt_addr_r} && " \
+			"fdt addr ${fdt_addr_r} && "			\
+			"fdt resize && "				\
+			"fdt set /soc/spi@ff705000/n25q00@1 status disabled && " \
+			"bootm ${kernel_addr_r}:kernel@1 - ${fdt_addr_r} ; "	\
+		"else "							\
+			"bootm ${kernel_addr_r} ; "			\
+		"fi\0"							\
+	"ubi_ubi="							\
+		"run ubi_sfsel ubiload ubiargs addargs boot_kernel\0"	\
+	"ubi_nfs="							\
+		"run ubiload nfsargs addip addargs boot_kernel\0"	\
+	"net_ubi="							\
+		"run netload ubiargs addargs boot_kernel\0"		\
+	"net_nfs="							\
+		"run netload nfsargs addip addargs boot_kernel\0"	\
+	"selboot="	/* Select from where to boot. */		\
+		"run sf_identify ; "					\
+		"if test \"${bootmode}\" = \"qspi\" ; then "		\
+			"led all off ; "				\
+			"if test \"${boottype}\" = \"rcvr\" ; then "	\
+				"echo \"Booting recovery system\" ; "	\
+				"led 3 on ; "	/* Bottom RED */	\
+			"fi ; "						\
+			"led 1 on ; "		/* Top RED */		\
+			"run ubi_ubi ; "				\
+		"else echo \"Unsupported boot mode: \"${bootmode} ; "	\
+		"fi\0"							\
+		"socfpga_legacy_reset_compat=1\0"
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	\
+	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+
+/* Support changing the prompt string */
+#define CONFIG_CMDLINE_PS_SUPPORT
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOFTING_VINING_FPGA_H__ */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
new file mode 100644
index 0000000..c7c30d3
--- /dev/null
+++ b/include/configs/socrates.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Wolfgang Denk <wd@denx.de>
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ */
+
+/*
+ * Socrates
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SOCRATES		1
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66666666
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache		*/
+#define CONFIG_BTB			/* toggle branch predition	*/
+
+#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
+
+#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000
+#define CONFIG_SYS_MEMTEST_END		0x00C00000
+
+#define CONFIG_SYS_CCSRBAR		0xE0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x50	/* CTLR 0 DIMM 0 */
+
+#define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
+
+/* Hardcoded values, to use instead of SPD */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG		0x80010102
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x3935D322
+#define CONFIG_SYS_DDR_TIMING_2		0x14904CC8
+#define CONFIG_SYS_DDR_MODE			0x00480432
+#define CONFIG_SYS_DDR_INTERVAL		0x030C0100
+#define CONFIG_SYS_DDR_CONFIG_2		0x04400000
+#define CONFIG_SYS_DDR_CONFIG			0xC3008000
+#define CONFIG_SYS_DDR_CLK_CONTROL		0x03800000
+#define CONFIG_SYS_SDRAM_SIZE			256 /* in Megs */
+
+/*
+ * Flash on the LocalBus
+ */
+#define CONFIG_SYS_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */
+
+#define CONFIG_SYS_FLASH0		0xFE000000
+#define CONFIG_SYS_FLASH1		0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
+
+#define CONFIG_SYS_LBC_FLASH_BASE	CONFIG_SYS_FLASH1	/* Localbus flash start	*/
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH	*/
+
+#define CONFIG_SYS_BR0_PRELIM		0xfe001001	/* port size 16bit	*/
+#define CONFIG_SYS_OR0_PRELIM		0xfe000030	/* 32MB Flash		*/
+#define CONFIG_SYS_BR1_PRELIM		0xfc001001	/* port size 16bit	*/
+#define CONFIG_SYS_OR1_PRELIM		0xfe000030	/* 32MB Flash		*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per device	*/
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor	*/
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg	*/
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg		*/
+#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
+#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384KiB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc */
+
+/* FPGA and NAND */
+#define CONFIG_SYS_FPGA_BASE		0xc0000000
+#define CONFIG_SYS_FPGA_SIZE		0x00100000	/* 1 MB		*/
+#define CONFIG_SYS_HMI_BASE		0xc0010000
+#define CONFIG_SYS_BR3_PRELIM		0xc0001881	/* UPMA, 32-bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfff00000	/* 1 MB 	*/
+
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_FPGA_BASE + 0x70)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* LIME GDC */
+#define CONFIG_SYS_LIME_BASE		0xc8000000
+#define CONFIG_SYS_LIME_SIZE		0x04000000	/* 64 MB	*/
+#define CONFIG_SYS_BR2_PRELIM		0xc80018a1	/* UPMB, 32-bit	*/
+#define CONFIG_SYS_OR2_PRELIM		0xfc000000	/* 64 MB	*/
+
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
+
+/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
+#define CONFIG_SYS_MB862xx_CCF		0x10000
+/* SDRAM parameter */
+#define CONFIG_SYS_MB862xx_MMR		0x4157BA63
+
+/* Serial Port */
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	102124
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	102124
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x32	/* at address 0x32		*/
+
+/* I2C W83782G HW-Monitoring IC */
+#define CONFIG_SYS_I2C_W83782G_ADDR	0x28	/* W83782G address 		*/
+
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1.
+ */
+#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
+
+/* PCI is clocked by the external source at 33 MHz */
+#define CONFIG_PCI_CLK_FREQ	33000000
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
+#define CONFIG_SYS_PCI1_IO_BASE	0xE2000000
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M			*/
+
+#if defined(CONFIG_PCI)
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#endif	/* CONFIG_PCI */
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"TSEC1"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC3_PHY_ADDR		1
+
+#define TSEC1_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC3_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0,1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x4000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with ts	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
+#endif
+
+#define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consdev=ttyS0\0"						\
+	"uboot_file=/home/tftp/syscon3/u-boot.bin\0"			\
+	"bootfile=/home/tftp/syscon3/uImage\0"				\
+	"fdt_file=/home/tftp/syscon3/socrates.dtb\0"			\
+	"initrd_file=/home/tftp/syscon3/uinitrd.gz\0"			\
+	"uboot_addr=FFFA0000\0"						\
+	"kernel_addr=FE000000\0"					\
+	"fdt_addr=FE1E0000\0"						\
+	"ramdisk_addr=FE200000\0"					\
+	"fdt_addr_r=B00000\0"						\
+	"kernel_addr_r=200000\0"					\
+	"ramdisk_addr_r=400000\0"					\
+	"rootpath=/opt/eldk/ppc_85xxDP\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$serverip:$rootpath\0"				\
+	"addcons=setenv bootargs $bootargs "				\
+		"console=$consdev,$baudrate\0"				\
+	"addip=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
+		":$hostname:$netdev:off panic=1\0"			\
+	"boot_nor=run ramargs addcons;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"update_uboot=tftp 100000 ${uboot_file};"			\
+		"protect off fffa0000 ffffffff;"			\
+		"era fffa0000 ffffffff;"				\
+		"cp.b 100000 fffa0000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"update_kernel=tftp 100000 ${bootfile};"			\
+		"era fe000000 fe1dffff;"				\
+		"cp.b 100000 fe000000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"update_fdt=tftp 100000 ${fdt_file};" 				\
+		"era fe1e0000 fe1fffff;"				\
+		"cp.b 100000 fe1e0000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"update_initrd=tftp 100000 ${initrd_file};" 			\
+		"era fe200000 fe9fffff;"				\
+		"cp.b 100000 fe200000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"clean_data=era fea00000 fff5ffff\0"				\
+	"usbargs=setenv bootargs root=/dev/sda1 rw\0" 			\
+	"load_usb=usb start;" 						\
+		"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"	\
+	"boot_usb=run load_usb usbargs addcons;"			\
+		"bootm ${kernel_addr_r} - ${fdt_addr};"			\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	""
+#define CONFIG_BOOTCOMMAND	"run boot_nor"
+
+/* pass open firmware flat tree */
+
+/* USB support */
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_PCI_OHCI			1
+#define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
+#define CONFIG_PCI_EHCI_DEVNO		(CONFIG_PCI_OHCI_DEVNO / 2)
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h
new file mode 100644
index 0000000..cfcc9c8
--- /dev/null
+++ b/include/configs/som-db5800-som-6867.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Google, Inc
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=serial,usbkbd\0" \
+					"stdout=serial,vidconsole\0" \
+					"stderr=serial,vidconsole\0"
+
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x006ef000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
new file mode 100644
index 0000000..d21ff97
--- /dev/null
+++ b/include/configs/spear-common.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ */
+
+#ifndef _SPEAR_COMMON_H
+#define _SPEAR_COMMON_H
+/*
+ * Common configurations used for both spear3xx as well as spear6xx
+ */
+
+/* U-Boot Load Address */
+
+/* Ethernet driver configuration */
+#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
+
+/* USBD driver configuration */
+#if defined(CONFIG_SPEAR_USBTTY)
+#define CONFIG_DW_UDC
+#define CONFIG_USB_DEVICE
+#define CONFIG_USBD_HS
+#define CONFIG_USB_TTY
+
+#define CONFIG_USBD_PRODUCT_NAME		"SPEAr SoC"
+#define CONFIG_USBD_MANUFACTURER		"ST Microelectronics"
+
+#endif
+
+#define CONFIG_EXTRA_ENV_USBTTY			"usbtty=cdc_acm\0"
+
+/* I2C driver configuration */
+#define CONFIG_SYS_I2C
+#if defined(CONFIG_SPEAR600)
+#define CONFIG_SYS_I2C_BASE			0xD0200000
+#elif defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#endif
+#define CONFIG_SYS_I2C_SPEED			400000
+#define CONFIG_SYS_I2C_SLAVE			0x02
+
+#define CONFIG_I2C_CHIPADDRESS			0x50
+
+/* Timer, HZ specific defines */
+
+/* Flash configuration */
+#if defined(CONFIG_FLASH_PNOR)
+#define CONFIG_SPEAR_EMI
+#else
+#define CONFIG_ST_SMI
+#endif
+
+#if defined(CONFIG_ST_SMI)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS		2
+#define CONFIG_SYS_FLASH_BASE			0xF8000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0xF9000000
+#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
+#define CONFIG_SYS_FLASH_ADDR_BASE		{CONFIG_SYS_FLASH_BASE, \
+						CONFIG_SYS_CS1_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT		128
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
+
+#endif
+
+/*
+ * Serial Configuration (PL011)
+ * CONFIG_PL01x_PORTS is defined in specific files
+ */
+#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
+						57600, 115200 }
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* NAND FLASH Configuration */
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/*
+ * Default Environment Varible definitions
+ */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * U-Boot Environment placing definitions.
+ */
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+#ifdef CONFIG_ST_SMI
+/*
+ * Environment is in serial NOR flash
+ */
+#define CONFIG_SYS_MONITOR_LEN			0x00040000
+#define CONFIG_ENV_SECT_SIZE			0x00010000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "
+
+#define CONFIG_BOOTCOMMAND			"bootm 0xf8050000"
+
+#elif defined(CONFIG_SPEAR_EMI)
+/*
+ * Environment is in parallel NOR flash
+ */
+#define CONFIG_SYS_MONITOR_LEN			0x00060000
+#define CONFIG_ENV_SECT_SIZE			0x00020000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "
+
+#define CONFIG_BOOTCOMMAND			"cp.b 0x50080000 0x1600000 " \
+						"0x4C0000; bootm 0x1600000"
+#endif
+
+#define CONFIG_ENV_ADDR				(CONFIG_SYS_FLASH_BASE + \
+						CONFIG_SYS_MONITOR_LEN)
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+/*
+ * Environment is in NAND
+ */
+
+#define CONFIG_ENV_OFFSET			0x60000
+#define CONFIG_ENV_RANGE			0x10000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock7 "
+
+#define CONFIG_BOOTCOMMAND			"nand read.jffs2 0x1600000 " \
+						"0x80000 0x4C0000; " \
+						"bootm 0x1600000"
+#endif
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"bootp; "							\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$(serverip):$(rootpath) "				\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):"			\
+			"$(netmask):$(hostname):$(netdev):off "		\
+			"console=ttyAMA0,115200 $(othbootargs);"	\
+	"bootm; "
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=ttyAMA0,115200 $(othbootargs);"		\
+	CONFIG_BOOTCOMMAND
+
+#define CONFIG_ENV_SIZE				0x02000
+#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE
+
+/* Miscellaneous configurable options */
+#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_SYS_MEMTEST_START		0x00800000
+#define CONFIG_SYS_MEMTEST_END			0x04000000
+#define CONFIG_SYS_MALLOC_LEN			(1024*1024)
+#define CONFIG_SYS_LOAD_ADDR			0x00800000
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1				0x00000000
+#define PHYS_SDRAM_1_MAXSIZE			0x40000000
+
+#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR		0xD2800000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x2000
+
+#define CONFIG_SYS_INIT_SP_OFFSET		\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR			\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#endif
diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h
new file mode 100644
index 0000000..2f642b1
--- /dev/null
+++ b/include/configs/spear3xx_evb.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_SPEAR3XX
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SPEAR3XX
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SPEAR3XX
+#endif
+
+#if defined(CONFIG_USBTTY)
+#define CONFIG_SPEAR_USBTTY
+#endif
+
+#include <configs/spear-common.h>
+
+/* Ethernet driver configuration */
+#define CONFIG_DW_ALTDESCRIPTOR
+
+#if defined(CONFIG_SPEAR310)
+#define CONFIG_MACB
+#define CONFIG_MACB0_PHY			0x01
+#define CONFIG_MACB1_PHY			0x03
+#define CONFIG_MACB2_PHY			0x05
+#define CONFIG_MACB3_PHY			0x07
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_MACB
+#define CONFIG_MACB0_PHY			0x01
+
+#endif
+
+/* Serial Configuration (PL011) */
+#define CONFIG_SYS_SERIAL0			0xD0000000
+
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0}
+
+#elif defined(CONFIG_SPEAR310)
+
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xB2000000
+#define CONFIG_SYS_SERIAL2			0xB2080000
+#define CONFIG_SYS_SERIAL3			0xB2100000
+#define CONFIG_SYS_SERIAL4			0xB2180000
+#define CONFIG_SYS_SERIAL5			0xB2200000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2, \
+						(void *)CONFIG_SYS_SERIAL3, \
+						(void *)CONFIG_SYS_SERIAL4, \
+						(void *)CONFIG_SYS_SERIAL5 }
+#elif defined(CONFIG_SPEAR320)
+
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xA3000000
+#define CONFIG_SYS_SERIAL2			0xA4000000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2 }
+#endif
+
+#if defined(CONFIG_SPEAR_EMI)
+#if defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_FLASH_BASE			0x50000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x60000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x70000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x80000000
+#define CONFIG_SYS_CS4_FLASH_BASE		0x90000000
+#define CONFIG_SYS_CS5_FLASH_BASE		0xA0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE, \
+						CONFIG_SYS_CS4_FLASH_BASE, \
+						CONFIG_SYS_CS5_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		6
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_FLASH_BASE			0x44000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x45000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x46000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x47000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		4
+
+#endif
+
+#define CONFIG_SYS_MAX_FLASH_SECT		(127 + 8)
+#define CONFIG_SYS_FLASH_QUIET_TEST
+
+#endif
+
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_NAND_BASE			0x80000000
+
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_NAND_BASE			0x40000000
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_NAND_BASE			0x50000000
+
+#endif
+
+/* Environment Settings */
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY
+
+#elif defined(CONFIG_SPEAR310) || defined(CONFIG_SPEAR320)
+#define CONFIG_EXTRA_ENV_UNLOCK                        "unlock=yes\0"
+#define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY \
+						CONFIG_EXTRA_ENV_UNLOCK
+#endif
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h
new file mode 100644
index 0000000..cfadfc8
--- /dev/null
+++ b/include/configs/spear6xx_evb.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#if defined(CONFIG_USBTTY)
+#define CONFIG_SPEAR_USBTTY
+#endif
+
+#include <configs/spear-common.h>
+
+/* Serial Configuration (PL011) */
+#define CONFIG_SYS_SERIAL0			0xD0000000
+#define CONFIG_SYS_SERIAL1			0xD0080000
+#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1 }
+
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
+#define CONFIG_SYS_NAND_BASE			0xD2000000
+
+/* Ethernet PHY configuration */
+#define CONFIG_PHY_NATSEMI
+
+/* Environment Settings */
+#define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/spring.h b/include/configs/spring.h
new file mode 100644
index 0000000..272622a
--- /dev/null
+++ b/include/configs/spring.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_SPRING_H
+#define __CONFIG_SPRING_H
+
+#include <configs/exynos5250-common.h>
+#include <configs/exynos5-dt-common.h>
+#include <configs/exynos5-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#endif	/* __CONFIG_SPRING_H */
diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h
new file mode 100644
index 0000000..b67efbb
--- /dev/null
+++ b/include/configs/stih410-b2260.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+/* ram memory-related information */
+#define PHYS_SDRAM_1			0x40000000
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define PHYS_SDRAM_1_SIZE		0x3E000000
+#define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1	/* default load addr */
+
+#define CONFIG_SYS_HZ_CLOCK		1000000000	/* 1 GHz */
+
+/* Environment */
+
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_BOOTM_LEN		SZ_16M
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+			"kernel_addr_r=0x40000000\0"		\
+			"fdtfile=stih410-b2260.dtb\0"		\
+			"fdt_addr_r=0x47000000\0"		\
+			"scriptaddr=0x50000000\0"		\
+			"pxefile_addr_r=0x50100000\0"		\
+			"fdt_high=0xffffffffffffffff\0"		\
+			"initrd_high=0xffffffffffffffff\0"	\
+			"ramdisk_addr_r=0x48000000\0"		\
+			BOOTENV
+
+
+#define CONFIG_ENV_SIZE 0x4000
+
+/* Extra Commands */
+#define CONFIG_CMD_ASKENV
+
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		0x1800000
+#define CONFIG_SYS_GBL_DATA_SIZE	1024	/* Global data structures */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - \
+					 CONFIG_SYS_MALLOC_LEN - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* USB Configs */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/* NET Configs */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
new file mode 100644
index 0000000..31c17d0
--- /dev/null
+++ b/include/configs/stm32f429-discovery.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <kamil.lulko@gmail.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x10010000
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x90400000
+#define CONFIG_LOADADDR			0x90400000
+
+#define CONFIG_SYS_MAX_FLASH_SECT	12
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+
+#define CONFIG_ENV_OFFSET		(256 << 10)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			(8 << 10)
+
+#define CONFIG_RED_LED			110
+#define CONFIG_GREEN_LED		109
+
+#define CONFIG_STM32_FLASH
+
+#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE		1024
+
+#define CONFIG_SYS_MALLOC_LEN		(2 << 20)
+
+#define CONFIG_BOOTCOMMAND						\
+	"run bootcmd_romfs"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
+	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
+	"bootm 0x08044000 - 0x08042000\0"
+
+/*
+ * Command line configuration.
+ */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h
new file mode 100644
index 0000000..a5390f8
--- /dev/null
+++ b/include/configs/stm32f429-evaluation.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x10010000
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x00400000
+#define CONFIG_LOADADDR			0x00400000
+
+#define CONFIG_SYS_MAX_FLASH_SECT	12
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+
+#define CONFIG_ENV_OFFSET		(256 << 10)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			(8 << 10)
+
+#define CONFIG_STM32_FLASH
+
+#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE		1024
+
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+			"kernel_addr_r=0x00008000\0"		\
+			"fdtfile=stm32429i-eval.dtb\0"	\
+			"fdt_addr_r=0x00700000\0"		\
+			"scriptaddr=0x00800000\0"		\
+			"pxefile_addr_r=0x00800000\0" \
+			"fdt_high=0xffffffffffffffff\0"		\
+			"initrd_high=0xffffffffffffffff\0"	\
+			"ramdisk_addr_r=0x00900000\0"		\
+			BOOTENV
+
+/*
+ * Command line configuration.
+ */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h
new file mode 100644
index 0000000..1c7efd1
--- /dev/null
+++ b/include/configs/stm32f469-discovery.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x10010000
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x00400000
+#define CONFIG_LOADADDR			0x00400000
+
+#define CONFIG_SYS_MAX_FLASH_SECT	12
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+
+#define CONFIG_ENV_OFFSET		(256 << 10)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			(8 << 10)
+
+#define CONFIG_STM32_FLASH
+
+#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE		1024
+
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+			"kernel_addr_r=0x00008000\0"		\
+			"fdtfile=stm32f469-disco.dtb\0"	\
+			"fdt_addr_r=0x00700000\0"		\
+			"scriptaddr=0x00800000\0"		\
+			"pxefile_addr_r=0x00800000\0" \
+			"fdt_high=0xffffffffffffffff\0"		\
+			"initrd_high=0xffffffffffffffff\0"	\
+			"ramdisk_addr_r=0x00900000\0"		\
+			BOOTENV
+
+/*
+ * Command line configuration.
+ */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
new file mode 100644
index 0000000..cc26f83
--- /dev/null
+++ b/include/configs/stm32f746-disco.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CONFIG_SYS_INIT_SP_ADDR		0x20050000
+
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SYS_LOAD_ADDR		0x08008000
+#else
+#define CONFIG_SYS_LOAD_ADDR		0xC0400000
+#define CONFIG_LOADADDR			0xC0400000
+#endif
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+
+#define CONFIG_SYS_MAX_FLASH_SECT	8
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_ENV_SIZE			(8 << 10)
+
+#define CONFIG_STM32_FLASH
+
+#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL	(8)
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE		1024
+
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+			"kernel_addr_r=0xC0008000\0"		\
+			"fdtfile=stm32f746-disco.dtb\0"	\
+			"fdt_addr_r=0xC0500000\0"		\
+			"scriptaddr=0xC0008000\0"		\
+			"pxefile_addr_r=0xC0008000\0" \
+			"fdt_high=0xffffffffffffffff\0"		\
+			"initrd_high=0xffffffffffffffff\0"	\
+			"ramdisk_addr_r=0xC0600000\0"		\
+			BOOTENV
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* For SPL */
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_SPL_LEN		0x00008000
+#define CONFIG_SYS_UBOOT_START		0x080083FD
+#define CONFIG_SYS_UBOOT_BASE		(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_SYS_SPL_LEN)
+
+/* DT blob (fdt) address */
+#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
+					0x1C0000)
+#endif
+/* For SPL ends */
+
+/* For splashcreen */
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h
new file mode 100644
index 0000000..f110e29
--- /dev/null
+++ b/include/configs/stm32h743-disco.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config.h>
+
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CONFIG_SYS_INIT_SP_ADDR		0x24040000
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_SYS_LOAD_ADDR		0xD0400000
+#define CONFIG_LOADADDR			0xD0400000
+
+#define CONFIG_ENV_SIZE			(8 << 10)
+
+#define CONFIG_SYS_HZ_CLOCK		1000000
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+			"kernel_addr_r=0xD0008000\0"		\
+			"fdtfile=stm32h743i-disco.dtb\0"	\
+			"fdt_addr_r=0xD0700000\0"		\
+			"scriptaddr=0xD0800000\0"		\
+			"pxefile_addr_r=0xD0800000\0" \
+			"fdt_high=0xffffffffffffffff\0"		\
+			"initrd_high=0xffffffffffffffff\0"	\
+			"ramdisk_addr_r=0xD0900000\0"		\
+			BOOTENV
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_BOARD_LATE_INIT
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h
new file mode 100644
index 0000000..e3bf5b2
--- /dev/null
+++ b/include/configs/stm32h743-eval.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config.h>
+
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+#define CONFIG_SYS_INIT_SP_ADDR		0x24040000
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_SYS_LOAD_ADDR		0xD0400000
+#define CONFIG_LOADADDR			0xD0400000
+
+#define CONFIG_ENV_SIZE			(8 << 10)
+
+#define CONFIG_SYS_HZ_CLOCK		1000000
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+			"kernel_addr_r=0xD0008000\0"		\
+			"fdtfile=stm32h743i-eval.dtb\0"	\
+			"fdt_addr_r=0xD0700000\0"		\
+			"scriptaddr=0xD0800000\0"		\
+			"pxefile_addr_r=0xD0800000\0" \
+			"fdt_high=0xffffffffffffffff\0"		\
+			"initrd_high=0xffffffffffffffff\0"	\
+			"ramdisk_addr_r=0xD0900000\0"		\
+			BOOTENV
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_BOARD_LATE_INIT
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
new file mode 100644
index 0000000..988992b
--- /dev/null
+++ b/include/configs/stm32mp1.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * Configuration settings for the STM32MP15x CPU
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <linux/sizes.h>
+#include <asm/arch/stm32.h>
+
+#ifndef CONFIG_STM32MP1_TRUSTED
+/* PSCI support */
+#define CONFIG_ARMV7_PSCI_1_0
+#define CONFIG_ARMV7_SECURE_BASE		STM32_SYSRAM_BASE
+#define CONFIG_ARMV7_SECURE_MAX_SIZE		STM32_SYSRAM_SIZE
+#endif
+
+/*
+ * Configuration of the external SRAM memory used by U-Boot
+ */
+#define CONFIG_SYS_SDRAM_BASE			STM32_DDR_BASE
+#define CONFIG_SYS_INIT_SP_ADDR			CONFIG_SYS_TEXT_BASE
+
+#ifdef CONFIG_STM32MP1_OPTEE
+#define CONFIG_SYS_MEM_TOP_HIDE			SZ_32M
+#endif /* CONFIG_STM32MP1_OPTEE */
+
+/*
+ * Console I/O buffer size
+ */
+#define CONFIG_SYS_CBSIZE			SZ_1K
+
+/*
+ * Needed by "loadb"
+ */
+#define CONFIG_SYS_LOAD_ADDR			STM32_DDR_BASE
+
+/* ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN			SZ_32M
+
+/* SPL support */
+#ifdef CONFIG_SPL
+/* SPL use DDR */
+#define CONFIG_SPL_BSS_START_ADDR	0xC0200000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START	0xC0300000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
+
+/* limit SYSRAM usage to first 128 KB */
+#define CONFIG_SPL_MAX_SIZE		0x00020000
+#define CONFIG_SPL_STACK		(STM32_SYSRAM_BASE + \
+					 STM32_SYSRAM_SIZE)
+#endif /* #ifdef CONFIG_SPL */
+
+#define CONFIG_SYS_MEMTEST_START	STM32_DDR_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_64M)
+#define CONFIG_SYS_MEMTEST_SCRATCH	(CONFIG_SYS_MEMTEST_END + 4)
+
+/*MMC SD*/
+#define CONFIG_SYS_MMC_MAX_DEVICE	3
+
+/* NAND support */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Ethernet need */
+#ifdef CONFIG_DWC_ETH_QOS
+#define CONFIG_SYS_NONCACHED_MEMORY	(1 * SZ_1M)	/* 1M */
+#define CONFIG_SERVERIP                 192.168.1.1
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_SYS_AUTOLOAD		"no"
+#endif
+
+/* Dynamic MTD partition support */
+#if defined(CONFIG_STM32_QSPI) || defined(CONFIG_NAND_STM32_FMC2)
+#define CONFIG_SYS_MTDPARTS_RUNTIME
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#endif
+
+/*****************************************************************************/
+#ifdef CONFIG_DISTRO_DEFAULTS
+/*****************************************************************************/
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(UBIFS, ubifs, 0) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 2) \
+	func(PXE, pxe, na)
+
+/*
+ * bootcmd for stm32mp1:
+ * for serial/usb: execute the stm32prog command
+ * for mmc boot (eMMC, SD card), boot only on the same device
+ * for nand boot, boot with on ubifs partition on nand
+ * for nor boot, use the default order
+ */
+#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \
+	"echo \"Boot over ${boot_device}${boot_instance}!\";" \
+	"if test ${boot_device} = serial || test ${boot_device} = usb;" \
+	"then stm32prog ${boot_device} ${boot_instance}; " \
+	"else " \
+		"run env_check;" \
+		"if test ${boot_device} = mmc;" \
+		"then env set boot_targets \"mmc${boot_instance}\"; fi;" \
+		"if test ${boot_device} = nand;" \
+		"then env set boot_targets ubifs0; fi;" \
+		"run distro_bootcmd;" \
+	"fi;\0"
+
+#include <config_distro_bootcmd.h>
+
+#ifdef CONFIG_STM32MP1_OPTEE
+/* with OPTEE: define specific MTD partitions = teeh, teed, teex */
+#define STM32MP_MTDPARTS \
+	"mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),256k(teeh),256k(teed),256k(teex),-(nor_user)\0" \
+	"mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),512k(teeh),512k(teed),512k(teex),-(UBI)\0"
+
+#else /* CONFIG_STM32MP1_OPTEE */
+#define STM32MP_MTDPARTS \
+	"mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),-(nor_user)\0" \
+	"mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),-(UBI)\0"
+
+#endif /* CONFIG_STM32MP1_OPTEE */
+
+#ifndef CONFIG_SYS_MTDPARTS_RUNTIME
+#undef STM32MP_MTDPARTS
+#define STM32MP_MTDPARTS
+#endif
+
+/*
+ * memory layout for 32M uncompressed/compressed kernel,
+ * 1M fdt, 1M script, 1M pxe and 1M for splashimage
+ * and the ramdisk at the end.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootdelay=1\0" \
+	"kernel_addr_r=0xc2000000\0" \
+	"fdt_addr_r=0xc4000000\0" \
+	"scriptaddr=0xc4100000\0" \
+	"pxefile_addr_r=0xc4200000\0" \
+	"splashimage=0xc4300000\0"  \
+	"ramdisk_addr_r=0xc4400000\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"altbootcmd=run bootcmd\0" \
+	"env_default=1\0" \
+	"env_check=if test $env_default -eq 1;"\
+		" then env set env_default 0;env save;fi\0" \
+	STM32MP_BOOTCMD \
+	STM32MP_MTDPARTS \
+	BOOTENV \
+	"boot_net_usb_start=true\0"
+
+#endif /* ifndef CONFIG_SPL_BUILD */
+#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
new file mode 100644
index 0000000..3596658
--- /dev/null
+++ b/include/configs/stmark2.h
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Sysam stmark2 board configuration
+ *
+ * (C) Copyright 2017  Angelo Dureghello <angelo@sysam.it>
+ */
+
+#ifndef __STMARK2_CONFIG_H
+#define __STMARK2_CONFIG_H
+
+#define CONFIG_HOSTNAME			"stmark2"
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		0
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#define LDS_BOARD_TEXT						\
+	board/sysam/stmark2/sbf_dram_init.o (.text*)
+
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_BOOTARGS						\
+	"console=ttyS0,115200 root=/dev/ram0 rw "		\
+		"rootfstype=ramfs "				\
+		"rdinit=/bin/init "				\
+		"devtmpfs.mount=1"
+
+#define CONFIG_BOOTCOMMAND					\
+	"sf probe 0:1 50000000; "				\
+	"sf read ${loadaddr} 0x100000 ${kern_size}; "		\
+	"bootm ${loadaddr}"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"kern_size=0x700000\0"					\
+	"loadaddr=0x40001000\0"					\
+		"-(rootfs)\0"					\
+	"update_uboot=loady ${loadaddr}; "			\
+		"sf probe 0:1 50000000; "			\
+		"sf erase 0 0x80000; "				\
+		"sf write ${loadaddr} 0 ${filesize}\0"		\
+	"update_kernel=loady ${loadaddr}; "			\
+		"setenv kern_size ${filesize}; saveenv; "	\
+		"sf probe 0:1 50000000; "			\
+		"sf erase 0x100000 0x700000; "			\
+		"sf write ${loadaddr} 0x100000 ${filesize}\0"	\
+	"update_rootfs=loady ${loadaddr}; "			\
+		"sf probe 0:1 50000000; "			\
+		"sf erase 0x00800000 0x100000; "		\
+		"sf write ${loadaddr} 0x00800000 ${filesize}\0"	\
+	""
+
+/* Realtime clock */
+#undef CONFIG_MCFRTC
+#define CONFIG_RTC_MCFRRTC
+#define CONFIG_SYS_MCFRRTC_BASE		0xFC0A8000
+
+/* spi not partitions */
+#define CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM			2048	/* 2048 KB */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
+#define CONFIG_SYS_MBAR			0xFC000000
+
+/*
+ * Definitions for initial stack pointer and data area (in internal SRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x400)
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_DRAM_TEST
+
+#if defined(CONFIG_CF_SBF)
+#define CONFIG_SERIAL_BOOT
+#endif
+
+#if defined(CONFIG_SERIAL_BOOT)
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_TEXT_BASE + 0x400)
+#else
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
+/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + \
+					(CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+
+#if defined(CONFIG_CF_SBF)
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#endif
+
+#undef CONFIG_ENV_OVERWRITE
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+#define CACR_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_RAM_SIZE - 12)
+
+#endif /* __STMARK2_CONFIG_H */
diff --git a/include/configs/stout.h b/include/configs/stout.h
new file mode 100644
index 0000000..6734595
--- /dev/null
+++ b/include/configs/stout.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * include/configs/stout.h
+ *     This file is Stout board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Europe GmbH
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Cogent Embedded, Inc.
+ */
+
+#ifndef __STOUT_H
+#define __STOUT_H
+
+#include "rcar-gen2-common.h"
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
+#define STACK_AREA_SIZE			0x00100000
+#define LOW_LEVEL_MERAM_STACK \
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE		0x40000000
+#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+/* SCIF */
+#define CONFIG_SCIF_A
+
+/* SPI */
+#define CONFIG_SPI_FLASH_QUAD
+
+/* SH Ether */
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK	20000000u
+#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"bootm_size=0x10000000\0"
+
+/* SPL support */
+#define CONFIG_SPL_STACK		0xe6340000
+#define CONFIG_SPL_MAX_SIZE		0x4000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_CONS_SCIFA0
+#define CONFIG_SH_SCIF_CLK_FREQ		52000000
+#endif
+
+#endif	/* __STOUT_H */
diff --git a/include/configs/strider.h b/include/configs/strider.h
new file mode 100644
index 0000000..e3d64e5
--- /dev/null
+++ b/include/configs/strider.h
@@ -0,0 +1,471 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of one chip NT5TU64M16HG from NANYA
+ */
+
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ONLY_CURRENT \
+				| CSCONFIG_BANK_BIT_3 \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00260802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (9 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x26279222 */
+#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x021848c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x08240100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_16)
+				/* 0x43100000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0440 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0242 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=4, AL=0 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx16
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
+
+#define CONFIG_SYS_FPGA_COUNT		1
+
+#define CONFIG_SYS_MCLINK_MAX		3
+
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
+
+#define CONFIG_SYS_FPGA_NO_RFL_HI
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* Pass open firmware flat tree */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+
+#define CONFIG_PCA953X			/* NXP PCA9554 */
+#define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
+					  {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
+
+#define CONFIG_PCA9698			/* NXP PCA9698 */
+
+#define CONFIG_SYS_I2C_IHS
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH2
+#define CONFIG_SYS_I2C_IHS_SPEED_2		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2		0x7F
+#define CONFIG_SYS_I2C_IHS_CH3
+#define CONFIG_SYS_I2C_IHS_SPEED_3		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F
+
+#ifdef CONFIG_STRIDER_CON_DP
+#define CONFIG_SYS_I2C_IHS_DUAL
+#define CONFIG_SYS_I2C_IHS_CH0_1
+#define CONFIG_SYS_I2C_IHS_SPEED_0_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH1_1
+#define CONFIG_SYS_I2C_IHS_SPEED_1_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH2_1
+#define CONFIG_SYS_I2C_IHS_SPEED_2_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH3_1
+#define CONFIG_SYS_I2C_IHS_SPEED_3_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3_1		0x7F
+#endif
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define CONFIG_SYS_I2C_SOFT
+#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define CONFIG_SYS_I2C_SOFT_SPEED		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE		0x7F
+#define I2C_SOFT_DECLARATIONS2
+#define CONFIG_SYS_I2C_SOFT_SPEED_2		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_2		0x7F
+#define I2C_SOFT_DECLARATIONS3
+#define CONFIG_SYS_I2C_SOFT_SPEED_3		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_3		0x7F
+#define I2C_SOFT_DECLARATIONS4
+#define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
+#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
+#define I2C_SOFT_DECLARATIONS5
+#define CONFIG_SYS_I2C_SOFT_SPEED_5		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_5		0x7F
+#define I2C_SOFT_DECLARATIONS6
+#define CONFIG_SYS_I2C_SOFT_SPEED_6		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_6		0x7F
+#define I2C_SOFT_DECLARATIONS7
+#define CONFIG_SYS_I2C_SOFT_SPEED_7		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_7		0x7F
+#define I2C_SOFT_DECLARATIONS8
+#define CONFIG_SYS_I2C_SOFT_SPEED_8		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_8		0x7F
+#endif
+#ifdef CONFIG_STRIDER_CON_DP
+#define I2C_SOFT_DECLARATIONS9
+#define CONFIG_SYS_I2C_SOFT_SPEED_9		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_9		0x7F
+#define I2C_SOFT_DECLARATIONS10
+#define CONFIG_SYS_I2C_SOFT_SPEED_10		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_10		0x7F
+#define I2C_SOFT_DECLARATIONS11
+#define CONFIG_SYS_I2C_SOFT_SPEED_11		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_11		0x7F
+#define I2C_SOFT_DECLARATIONS12
+#define CONFIG_SYS_I2C_SOFT_SPEED_12		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_12		0x7F
+#endif
+
+#ifdef CONFIG_STRIDER_CON
+#define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
+#define CONFIG_SYS_CH7301_I2C			{5, 6, 7, 8}
+#define CONFIG_SYS_ADV7611_I2C			{5, 6, 7, 8}
+#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
+#define CONFIG_STRIDER_FANS			{ {10, 0x4c}, {11, 0x4c}, \
+						  {12, 0x4c} }
+#elif defined(CONFIG_STRIDER_CON_DP)
+#define CONFIG_SYS_ICS8N3QV01_I2C		{13, 14, 15, 16, 17, 18, 19, 20}
+#define CONFIG_SYS_CH7301_I2C			{1, 3, 5, 7}
+#define CONFIG_SYS_ADV7611_I2C			{1, 3, 5, 7}
+#define CONFIG_SYS_DP501_I2C			{1, 3, 5, 7, 2, 4, 6, 8}
+#define CONFIG_STRIDER_FANS			{ {10, 0x4c}, {11, 0x4c}, \
+						  {12, 0x4c} }
+#elif defined(CONFIG_STRIDER_CPU_DP)
+#define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
+#define CONFIG_SYS_ADV7611_I2C			{1, 2, 3, 4}
+#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
+#define CONFIG_STRIDER_FANS			{ {6, 0x4c}, {7, 0x4c}, \
+						  {8, 0x4c} }
+#else
+#define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
+#define CONFIG_SYS_ADV7611_I2C			{1, 2, 3, 4}
+#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
+#define CONFIG_STRIDER_FANS			{ {2, 0x18}, {3, 0x18}, \
+						  {4, 0x18} }
+#endif
+
+#ifndef __ASSEMBLY__
+void fpga_gpio_set(unsigned int bus, int pin);
+void fpga_gpio_clear(unsigned int bus, int pin);
+int fpga_gpio_get(unsigned int bus, int pin);
+void fpga_control_set(unsigned int bus, int pin);
+void fpga_control_clear(unsigned int bus, int pin);
+#endif
+
+#ifdef CONFIG_STRIDER_CON
+#define I2C_SDA_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
+#define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
+#define I2C_FPGA_IDX	((I2C_ADAP_HWNR > 3) ? \
+			 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
+#elif defined(CONFIG_STRIDER_CON_DP)
+#define I2C_SDA_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
+#define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
+#define I2C_FPGA_IDX	(I2C_ADAP_HWNR % 4)
+#else
+#define I2C_SDA_GPIO	0x0040
+#define I2C_SCL_GPIO	0x0020
+#define I2C_FPGA_IDX	I2C_ADAP_HWNR
+#endif
+
+#ifdef CONFIG_STRIDER_CON_DP
+#define I2C_ACTIVE \
+	do { \
+		if (I2C_ADAP_HWNR > 7) \
+			fpga_control_set(I2C_FPGA_IDX, 0x0004); \
+		else \
+			fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
+	} while (0)
+#else
+#define I2C_ACTIVE	{ }
+#endif
+
+#define I2C_TRISTATE	{ }
+#define I2C_READ \
+	(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
+#define I2C_SDA(bit) \
+	do { \
+		if (bit) \
+			fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
+		else \
+			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
+	} while (0)
+#define I2C_SCL(bit) \
+	do { \
+		if (bit) \
+			fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
+		else \
+			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
+	} while (0)
+#define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
+
+/*
+ * Software (bit-bang) MII driver configuration
+ */
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_OSD_SCREENS		1
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
+
+#ifdef CONFIG_STRIDER_CON_DP
+#define CONFIG_SYS_OSD_DH
+#endif
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+/* enable PCIE clock */
+#define CONFIG_SYS_SCCR_PCIEXP1CM	1
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC1_FLAGS		0
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+/*
+ * Environment
+ */
+#if 1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+#else
+#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
+
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+
+#define CONFIG_HOSTNAME		"hrcon"
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS1\0"						\
+	"u-boot=u-boot.bin\0"						\
+	"kernel_addr=1000000\0"					\
+	"fdt_addr=C00000\0"						\
+	"fdtfile=hrcon.dtb\0"				\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+		" +${filesize};cp.b ${fileaddr} "			\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
+	"upd=run load update\0"						\
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp ${kernel_addr} $bootfile;"				\
+	"tftp ${fdt_addr} $fdtfile;"					\
+	"bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_MMCBOOTCOMMAND						\
+	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait "		\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"ext2load mmc 0:2 ${kernel_addr} $bootfile;"			\
+	"ext2load mmc 0:2 ${fdt_addr} $fdtfile;"			\
+	"bootm ${kernel_addr} - ${fdt_addr}"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_MMCBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
new file mode 100644
index 0000000..e526208
--- /dev/null
+++ b/include/configs/stv0991.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ */
+
+#ifndef __CONFIG_STV0991_H
+#define __CONFIG_STV0991_H
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+
+/* ram memory-related information */
+#define PHYS_SDRAM_1				0x00000000
+#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
+#define PHYS_SDRAM_1_SIZE			0x00198000
+
+#define CONFIG_ENV_SIZE				0x10000
+#define CONFIG_ENV_SECT_SIZE			CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET			0x30000
+#define CONFIG_ENV_ADDR				\
+	(PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 16 * 1024)
+
+/* user interface */
+#define CONFIG_SYS_CBSIZE			1024
+
+/* MISC */
+#define CONFIG_SYS_LOAD_ADDR			0x00000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x8000
+#define CONFIG_SYS_INIT_RAM_ADDR		0x00190000
+#define CONFIG_SYS_INIT_SP_OFFSET		\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+/* U-Boot Load Address */
+#define CONFIG_SYS_INIT_SP_ADDR			\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* GMAC related configs */
+
+#define CONFIG_DW_ALTDESCRIPTOR
+
+/* Command support defines */
+#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
+
+#define CONFIG_SYS_MEMTEST_START               0x0000
+#define CONFIG_SYS_MEMTEST_END                 1024*1024
+
+/* Misc configuration */
+
+#define CONFIG_BOOTCOMMAND                     "go 0x40040000"
+
+/*
++ * QSPI support
++ */
+#ifdef CONFIG_OF_CONTROL		/* QSPI is controlled via DT */
+#define CONFIG_CQSPI_REF_CLK		((30/4)/2)*1000*1000
+
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h
new file mode 100644
index 0000000..6033760
--- /dev/null
+++ b/include/configs/sun4i.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * Configuration settings for the Allwinner A10 (sun4i) CPU
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A10 specific configuration
+ */
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#define CONFIG_MACH_TYPE	(4104 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28))
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h
new file mode 100644
index 0000000..e050a52
--- /dev/null
+++ b/include/configs/sun50i.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the Allwinner A64 (sun50i) CPU
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A64 specific configuration
+ */
+
+#ifndef CONFIG_MACH_SUN50I_H6
+#define GICD_BASE		0x1c81000
+#define GICC_BASE		0x1c82000
+#else
+#define GICD_BASE		0x3021000
+#define GICC_BASE		0x3022000
+#endif
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
new file mode 100644
index 0000000..ee42af8
--- /dev/null
+++ b/include/configs/sun5i.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * Configuration settings for the Allwinner A13 (sun5i) CPU
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#define CONFIG_MACH_TYPE	(4138 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28))
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h
new file mode 100644
index 0000000..1e490da
--- /dev/null
+++ b/include/configs/sun6i.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ * (C) Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Configuration settings for the Allwinner A31 (sun6i) CPU
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A31 specific configuration
+ */
+
+#define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
+#define CONFIG_ARMV7_SECURE_MAX_SIZE    (64 * 1024) /* 64 KB */
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h
new file mode 100644
index 0000000..d2fd586
--- /dev/null
+++ b/include/configs/sun7i.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * Configuration settings for the Allwinner A20 (sun7i) CPU
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A20 specific configuration
+ */
+
+#define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
+#define CONFIG_ARMV7_SECURE_MAX_SIZE	(64 * 1024) /* 64 KB */
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#define CONFIG_MACH_TYPE	(4283 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28))
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
new file mode 100644
index 0000000..9b4675e
--- /dev/null
+++ b/include/configs/sun8i.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 Chen-Yu Tsai <wens@csie.org>
+ *
+ * Configuration settings for the Allwinner A23 (sun8i) CPU
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A23 specific configuration
+ */
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sun9i.h b/include/configs/sun9i.h
new file mode 100644
index 0000000..6ee08cf
--- /dev/null
+++ b/include/configs/sun9i.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Configuration settings for the Allwinner A80 (sun9i) CPU
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A80 specific configuration
+ */
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
new file mode 100644
index 0000000..0ef289f
--- /dev/null
+++ b/include/configs/sunxi-common.h
@@ -0,0 +1,509 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Configuration settings for the Allwinner sunxi series of boards.
+ */
+
+#ifndef _SUNXI_COMMON_CONFIG_H
+#define _SUNXI_COMMON_CONFIG_H
+
+#include <asm/arch/cpu.h>
+#include <linux/stringify.h>
+
+#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
+/*
+ * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the
+ * expense of restricting some features, so the regular machine id values can
+ * be used.
+ */
+# define CONFIG_MACH_TYPE_COMPAT_REV	0
+#else
+/*
+ * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels.
+ * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass
+ * beyond the machine id check.
+ */
+# define CONFIG_MACH_TYPE_COMPAT_REV	1
+#endif
+
+#ifdef CONFIG_ARM64
+#define CONFIG_SYS_BOOTM_LEN		(32 << 20)
+#endif
+
+/* Serial & console */
+#define CONFIG_SYS_NS16550_SERIAL
+/* ns16550 reg in the low bits of cpu reg */
+#define CONFIG_SYS_NS16550_CLK		24000000
+#ifndef CONFIG_DM_SERIAL
+# define CONFIG_SYS_NS16550_REG_SIZE	-4
+# define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
+# define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
+# define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
+# define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
+# define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
+#endif
+
+/* CPU */
+#define COUNTER_FREQUENCY		24000000
+
+/*
+ * The DRAM Base differs between some models. We cannot use macros for the
+ * CONFIG_FOO defines which contain the DRAM base address since they end
+ * up unexpanded in include/autoconf.mk .
+ *
+ * So we have to have this #ifdef #else #endif block for these.
+ */
+#ifdef CONFIG_MACH_SUN9I
+#define SDRAM_OFFSET(x) 0x2##x
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* default load address */
+/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here 
+ * since it needs to fit in with the other values. By also #defining it
+ * we get warnings if the Kconfig value mismatches. */
+#define CONFIG_SPL_STACK_R_ADDR		0x2fe00000
+#define CONFIG_SPL_BSS_START_ADDR	0x2ff80000
+#else
+#define SDRAM_OFFSET(x) 0x4##x
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_LOAD_ADDR		0x42000000 /* default load address */
+/* V3s do not have enough memory to place code at 0x4a000000 */
+/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here 
+ * since it needs to fit in with the other values. By also #defining it
+ * we get warnings if the Kconfig value mismatches. */
+#define CONFIG_SPL_STACK_R_ADDR		0x4fe00000
+#define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
+#endif
+
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000 /* 512 KiB */
+
+/*
+ * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
+ * slightly bigger. Note that it is possible to map the first 32 KiB of the
+ * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
+ * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
+ * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
+ * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register
+ * is known yet.
+ * H6 has SRAM A1 at 0x00020000.
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SUNXI_SRAM_ADDRESS
+/* FIXME: this may be larger on some SoCs */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000 /* 32 KiB */
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define PHYS_SDRAM_0			CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */
+
+#ifdef CONFIG_AHCI
+#define CONFIG_SYS_64BIT_LBA
+#endif
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_SERIAL_TAG
+
+#ifdef CONFIG_NAND_SUNXI
+#define CONFIG_SYS_NAND_MAX_ECCPOS 1664
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_MAX_NAND_DEVICE 8
+#endif
+
+/* mmc config */
+#ifdef CONFIG_MMC
+#define CONFIG_MMC_SUNXI_SLOT		0
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+
+#ifdef CONFIG_ARM64
+/*
+ * This is actually (CONFIG_ENV_OFFSET -
+ * (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)), but the value will be used
+ * directly in a makefile, without the preprocessor expansion.
+ */
+#define CONFIG_BOARD_SIZE_LIMIT		0x7e000
+#endif
+
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
+/* If we have two devices (most likely eMMC + MMC), favour the eMMC */
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#else
+/* Otherwise, use the only device we have */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+#define CONFIG_SYS_MMC_MAX_DEVICE	4
+#endif
+
+#ifndef CONFIG_MACH_SUN8I_V3S
+/* 64MB of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (64 << 20))
+#else
+/* 2MB of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (2 << 20))
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	1024	/* Print Buffer Size */
+
+/* standalone support */
+#define CONFIG_STANDALONE_LOAD_ADDR	CONFIG_SYS_LOAD_ADDR
+
+/* FLASH and environment organization */
+
+#define CONFIG_SYS_MONITOR_LEN		(768 << 10)	/* 768 KiB */
+
+#ifndef CONFIG_ARM64		/* AArch64 FEL support is not ready yet */
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+#endif
+
+/*
+ * We cannot use expressions here, because expressions won't be evaluated in
+ * autoconf.mk.
+ */
+#if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000
+#define CONFIG_SPL_MAX_SIZE		0x7fa0		/* 32 KiB */
+#ifdef CONFIG_ARM64
+/* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */
+#define LOW_LEVEL_SRAM_STACK		0x00054000
+#else
+#define LOW_LEVEL_SRAM_STACK		0x00018000
+#endif /* !CONFIG_ARM64 */
+#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000
+#define CONFIG_SPL_MAX_SIZE		0x7fa0		/* 32 KiB */
+/* end of SRAM A2 on H6 for now */
+#define LOW_LEVEL_SRAM_STACK		0x00118000
+#else
+#define CONFIG_SPL_MAX_SIZE		0x5fa0		/* 24KB on sun4i/sun7i */
+#define LOW_LEVEL_SRAM_STACK		0x00008000	/* End of sram */
+#endif
+
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_PAD_TO		32768		/* decimal for 'dd' */
+
+
+/* I2C */
+#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
+    defined CONFIG_SY8106A_POWER
+#endif
+
+#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
+    defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
+    defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE
+#define CONFIG_SYS_I2C_MVTWSI
+#ifndef CONFIG_DM_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		0x7f
+#endif
+#endif
+
+#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
+#define CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x00
+/* We use pin names in Kconfig and sunxi_name_to_gpio() */
+#define CONFIG_SOFT_I2C_GPIO_SDA	soft_i2c_gpio_sda
+#define CONFIG_SOFT_I2C_GPIO_SCL	soft_i2c_gpio_scl
+#ifndef __ASSEMBLY__
+extern int soft_i2c_gpio_sda;
+extern int soft_i2c_gpio_scl;
+#endif
+#define CONFIG_VIDEO_LCD_I2C_BUS	0 /* The lcd panel soft i2c is bus 0 */
+#define CONFIG_SYS_SPD_BUS_NUM		1 /* And the axp209 i2c bus is bus 1 */
+#else
+#define CONFIG_SYS_SPD_BUS_NUM		0 /* The axp209 i2c bus is bus 0 */
+#define CONFIG_VIDEO_LCD_I2C_BUS	-1 /* NA, but necessary to compile */
+#endif
+
+/* PMU */
+#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
+    defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \
+    defined CONFIG_SY8106A_POWER
+#endif
+
+#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE
+#if CONFIG_CONS_INDEX == 1
+#ifdef CONFIG_MACH_SUN9I
+#define OF_STDOUT_PATH		"/soc/serial@07000000:115200"
+#else
+#define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28000:115200"
+#endif
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
+#define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28400:115200"
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
+#define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28800:115200"
+#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
+#define OF_STDOUT_PATH		"/soc@01c00000/serial@01f02800:115200"
+#else
+#error Unsupported console port nr. Please fix stdout-path in sunxi-common.h.
+#endif
+#endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */
+
+#ifdef CONFIG_VIDEO_SUNXI
+/*
+ * The amount of RAM to keep free at the top of RAM when relocating u-boot,
+ * to use as framebuffer. This must be a multiple of 4096.
+ */
+#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20)
+
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_STD_TIMINGS
+#define CONFIG_I2C_EDID
+#define VIDEO_LINE_LEN (pGD->plnSizeX)
+
+/* allow both serial and cfb console. */
+/* stop x86 thinking in cfbconsole from trying to init a pc keyboard */
+
+#endif /* CONFIG_VIDEO_SUNXI */
+
+/* Ethernet support */
+
+#ifdef CONFIG_SUN7I_GMAC
+#define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+
+#ifdef CONFIG_ARM64
+/*
+ * Boards seem to come with at least 512MB of DRAM.
+ * The kernel should go at 512K, which is the default text offset (that will
+ * be adjusted at runtime if needed).
+ * There is no compression for arm64 kernels (yet), so leave some space
+ * for really big kernels, say 256MB for now.
+ * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd.
+ * Align the initrd to a 2MB page.
+ */
+#define BOOTM_SIZE	__stringify(0xa000000)
+#define KERNEL_ADDR_R	__stringify(SDRAM_OFFSET(0080000))
+#define FDT_ADDR_R	__stringify(SDRAM_OFFSET(FA00000))
+#define SCRIPT_ADDR_R	__stringify(SDRAM_OFFSET(FC00000))
+#define PXEFILE_ADDR_R	__stringify(SDRAM_OFFSET(FD00000))
+#define RAMDISK_ADDR_R	__stringify(SDRAM_OFFSET(FE00000))
+
+#else
+/*
+ * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
+ * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe and the ramdisk at the end.
+ */
+#ifndef CONFIG_MACH_SUN8I_V3S
+#define BOOTM_SIZE     __stringify(0xa000000)
+#define KERNEL_ADDR_R  __stringify(SDRAM_OFFSET(2000000))
+#define FDT_ADDR_R     __stringify(SDRAM_OFFSET(3000000))
+#define SCRIPT_ADDR_R  __stringify(SDRAM_OFFSET(3100000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
+#else
+/*
+ * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc.
+ * 16M uncompressed kernel, 8M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe and the ramdisk at the end.
+ */
+#define BOOTM_SIZE     __stringify(0x2e00000)
+#define KERNEL_ADDR_R  __stringify(SDRAM_OFFSET(1000000))
+#define FDT_ADDR_R     __stringify(SDRAM_OFFSET(1800000))
+#define SCRIPT_ADDR_R  __stringify(SDRAM_OFFSET(1900000))
+#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000))
+#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1B00000))
+#endif
+#endif
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=" BOOTM_SIZE "\0" \
+	"kernel_addr_r=" KERNEL_ADDR_R "\0" \
+	"fdt_addr_r=" FDT_ADDR_R "\0" \
+	"scriptaddr=" SCRIPT_ADDR_R "\0" \
+	"pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
+	"ramdisk_addr_r=" RAMDISK_ADDR_R "\0"
+
+#define DFU_ALT_INFO_RAM \
+	"dfu_alt_info_ram=" \
+	"kernel ram " KERNEL_ADDR_R " 0x1000000;" \
+	"fdt ram " FDT_ADDR_R " 0x100000;" \
+	"ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0"
+
+#ifdef CONFIG_MMC
+#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
+#define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance)		\
+	BOOTENV_DEV_MMC(MMC, mmc, 0)					\
+	BOOTENV_DEV_MMC(MMC, mmc, 1)					\
+	"bootcmd_mmc_auto="						\
+		"if test ${mmc_bootdev} -eq 1; then "			\
+			"run bootcmd_mmc1; "				\
+			"run bootcmd_mmc0; "				\
+		"elif test ${mmc_bootdev} -eq 0; then "			\
+			"run bootcmd_mmc0; "				\
+			"run bootcmd_mmc1; "				\
+		"fi\0"
+
+#define BOOTENV_DEV_NAME_MMC_AUTO(devtypeu, devtypel, instance) \
+	"mmc_auto "
+
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC_AUTO, mmc_auto, na)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#endif
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#ifdef CONFIG_AHCI
+#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
+#else
+#define BOOT_TARGET_DEVICES_SCSI(func)
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#ifdef CONFIG_CMD_PXE
+#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
+#else
+#define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
+/* FEL boot support, auto-execute boot.scr if a script address was provided */
+#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \
+	"bootcmd_fel=" \
+		"if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \
+			"echo '(FEL boot)'; " \
+			"source ${fel_scriptaddr}; " \
+		"fi\0"
+#define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \
+	"fel "
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(FEL, fel, na) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_SCSI(func) \
+	BOOT_TARGET_DEVICES_USB(func) \
+	BOOT_TARGET_DEVICES_PXE(func) \
+	BOOT_TARGET_DEVICES_DHCP(func)
+
+#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
+#define BOOTCMD_SUNXI_COMPAT \
+	"bootcmd_sunxi_compat=" \
+		"setenv root /dev/mmcblk0p3 rootwait; " \
+		"if ext2load mmc 0 0x44000000 uEnv.txt; then " \
+			"echo Loaded environment from uEnv.txt; " \
+			"env import -t 0x44000000 ${filesize}; " \
+		"fi; " \
+		"setenv bootargs console=${console} root=${root} ${extraargs}; " \
+		"ext2load mmc 0 0x43000000 script.bin && " \
+		"ext2load mmc 0 0x48000000 uImage && " \
+		"bootm 0x48000000\0"
+#else
+#define BOOTCMD_SUNXI_COMPAT
+#endif
+
+#include <config_distro_bootcmd.h>
+
+#ifdef CONFIG_USB_KEYBOARD
+#define CONSOLE_STDIN_SETTINGS \
+	"preboot=usb start\0" \
+	"stdin=serial,usbkbd\0"
+#else
+#define CONSOLE_STDIN_SETTINGS \
+	"stdin=serial\0"
+#endif
+
+#ifdef CONFIG_VIDEO
+#define CONSOLE_STDOUT_SETTINGS \
+	"stdout=serial,vga\0" \
+	"stderr=serial,vga\0"
+#elif CONFIG_DM_VIDEO
+#define CONSOLE_STDOUT_SETTINGS \
+	"stdout=serial,vidconsole\0" \
+	"stderr=serial,vidconsole\0"
+#else
+#define CONSOLE_STDOUT_SETTINGS \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+#endif
+
+#ifdef CONFIG_MTDIDS_DEFAULT
+#define SUNXI_MTDIDS_DEFAULT \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"
+#else
+#define SUNXI_MTDIDS_DEFAULT
+#endif
+
+#ifdef CONFIG_MTDPARTS_DEFAULT
+#define SUNXI_MTDPARTS_DEFAULT \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
+#else
+#define SUNXI_MTDPARTS_DEFAULT
+#endif
+
+#define PARTS_DEFAULT \
+	"name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \
+	"name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \
+	"name=esp,size=128M,bootable,uuid=${uuid_gpt_esp};" \
+	"name=system,size=-,uuid=${uuid_gpt_system};"
+
+#define UUID_GPT_ESP "c12a7328-f81f-11d2-ba4b-00a0c93ec93b"
+
+#ifdef CONFIG_ARM64
+#define UUID_GPT_SYSTEM "b921b045-1df0-41c3-af44-4c6f280d3fae"
+#else
+#define UUID_GPT_SYSTEM "69dad710-2ce4-4e3c-b16c-21a1d49abed3"
+#endif
+
+#define CONSOLE_ENV_SETTINGS \
+	CONSOLE_STDIN_SETTINGS \
+	CONSOLE_STDOUT_SETTINGS
+
+#ifdef CONFIG_ARM64
+#define FDTFILE "allwinner/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
+#else
+#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONSOLE_ENV_SETTINGS \
+	MEM_LAYOUT_ENV_SETTINGS \
+	DFU_ALT_INFO_RAM \
+	"fdtfile=" FDTFILE "\0" \
+	"console=ttyS0,115200\0" \
+	SUNXI_MTDIDS_DEFAULT \
+	SUNXI_MTDPARTS_DEFAULT \
+	"uuid_gpt_esp=" UUID_GPT_ESP "\0" \
+	"uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \
+	"partitions=" PARTS_DEFAULT "\0" \
+	BOOTCMD_SUNXI_COMPAT \
+	BOOTENV
+
+#else /* ifndef CONFIG_SPL_BUILD */
+#define CONFIG_EXTRA_ENV_SETTINGS
+#endif
+
+#endif /* _SUNXI_COMMON_CONFIG_H */
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
new file mode 100644
index 0000000..1705f9c
--- /dev/null
+++ b/include/configs/suvd3.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_HOSTNAME		"suvd3"
+#define CONFIG_KM_BOARD_NAME	"suvd3"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#define CONFIG_SYS_MAMR	(MxMR_GPL_x4DIS | \
+			 0x0000c000 | \
+			 MxMR_WLFx_2X)
+#endif /* __CONFIG_H */
diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h
new file mode 100644
index 0000000..e31b77c
--- /dev/null
+++ b/include/configs/syzygy_hub.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012 Xilinx
+ * (C) Copyright 2017 Opal Kelly Inc.
+ *
+ * Configuration settings for the SYZYGY Hub development board
+ * See zynq-common.h for Zynq common configs
+ */
+
+#ifndef __CONFIG_SYZYGY_HUB_H
+#define __CONFIG_SYZYGY_HUB_H
+
+#define CONFIG_EXTRA_ENV_SETTINGS       \
+	"fit_image=fit.itb\0"		\
+	"bitstream_image=download.bit\0"    \
+	"loadbit_addr=0x1000000\0"      \
+	"load_addr=0x2000000\0"		\
+	"fit_size=0x800000\0"		\
+	"flash_off=0x100000\0"		\
+	"nor_flash_off=0xE2100000\0"	\
+	"fdt_high=0x20000000\0"		\
+	"initrd_high=0x20000000\0"	\
+	"loadbootenv_addr=0x2000000\0"  \
+	"fdt_addr_r=0x1f00000\0"        \
+	"pxefile_addr_r=0x2000000\0"    \
+	"kernel_addr_r=0x2000000\0"     \
+	"scriptaddr=0x3000000\0"        \
+	"ramdisk_addr_r=0x3100000\0"    \
+	"bootenv=uEnv.txt\0" \
+	"bootenv_dev=mmc\0" \
+	"loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from ${bootenv_dev} ...; " \
+		"env import -t ${loadbootenv_addr} $filesize\0" \
+	"bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
+	"setbootenv=if env run bootenv_existence_test; then " \
+			"if env run loadbootenv; then " \
+				"env run importbootenv; " \
+			"fi; " \
+		"fi; \0" \
+	"sd_loadbootenv=set bootenv_dev mmc && " \
+			"run setbootenv \0" \
+	"usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv\0" \
+	"preboot=if test $modeboot = sdboot; then " \
+			"run sd_loadbootenv; " \
+			"echo Checking if uenvcmd is set ...; " \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...; " \
+				"run uenvcmd; " \
+			"fi; " \
+		"fi; \0" \
+	"sdboot=echo Copying FPGA Bitstream from SD to RAM... && " \
+		"load mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+		"echo Programming FPGA... && " \
+		"fpga loadb 0 ${loadbit_addr} ${filesize} && " \
+		"echo Copying FIT from SD to RAM... && " \
+		"load mmc 0 ${load_addr} ${fit_image} && " \
+		"bootm ${load_addr}\0" \
+	"jtagboot=echo TFTPing FIT to RAM... && " \
+		"tftpboot ${load_addr} ${fit_image} && " \
+		"bootm ${load_addr}\0" \
+		DFU_ALT_INFO \
+		BOOTENV
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_SYZYGY_HUB_H */
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
new file mode 100644
index 0000000..bf37501
--- /dev/null
+++ b/include/configs/t4qds.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __T4QDS_H
+#define __T4QDS_H
+
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_PCIE1			/* PCIE controller 1 */
+#define CONFIG_PCIE2			/* PCIE controller 2 */
+#define CONFIG_PCIE3			/* PCIE controller 3 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB			/* toggle branch predition */
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		(512 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+
+#define CONFIG_DDR_SPD
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
+
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_HVBOOT				\
+ "setenv bootargs config-addr=0x60000000; "	\
+ "bootm 0x01000000 - 0x00f00000"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
new file mode 100644
index 0000000..121de2b
--- /dev/null
+++ b/include/configs/tam3517-common.h
@@ -0,0 +1,326 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2009 TechNexion Ltd.
+ */
+
+#ifndef __TAM3517_H
+#define __TAM3517_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
+					2 * 1024 * 1024)
+/*
+ * DDR related
+ */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+/* EHCI */
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MAXARGS		32	/* max number of command */
+						/* args */
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Redundant Environment */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		0x180000
+#define CONFIG_ENV_ADDR			0x180000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						2 * CONFIG_SYS_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/*
+ * ethernet support, EMAC
+ *
+ */
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+
+/* Defines for SPL */
+#define CONFIG_SPL_CONSOLE
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */
+
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+
+/* FAT */
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
+					 48, 49, 50, 51, 52, 53, 54, 55,\
+					 56, 57, 58, 59, 60, 61, 62, 63}
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+
+/* Setup MTD for NAND on the SOM */
+
+#define	CONFIG_TAM3517_SETTINGS						\
+	"netdev=eth0\0"							\
+	"nandargs=setenv bootargs root=${nandroot} "			\
+		"rootfstype=${nandrootfstype}\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"				\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttyO0,${baudrate}\0"				\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"loadaddr=82000000\0"						\
+	"kernel_addr_r=82000000\0"					\
+	"hostname=" CONFIG_HOSTNAME "\0"			\
+	"bootfile=" CONFIG_HOSTNAME "/uImage\0"		\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
+		"nand read ${kernel_addr_r} kernel\0"			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self=if run net_self_load;then "				\
+		"run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
+		"else echo Images not loades;fi\0"			\
+	"u-boot=" CONFIG_HOSTNAME "/u-boot.img\0"		\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
+	"mlo=" CONFIG_HOSTNAME "/MLO\0"			\
+	"uboot_addr=0x80000\0"						\
+	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
+		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
+	"updatemlo=nandecc hw;nand erase 0 20000;"			\
+		"nand write ${loadaddr} 0 20000\0"			\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+
+/*
+ * this is common code for all TAM3517 boards.
+ * MAC address is stored from manufacturer in
+ * I2C EEPROM
+ */
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/*
+ * The I2C EEPROM on the TAM3517 contains
+ * mac address and production data
+ */
+struct tam3517_module_info {
+	char customer[48];
+	char product[48];
+
+	/*
+	 * bit 0~47  : sequence number
+	 * bit 48~55 : week of year, from 0.
+	 * bit 56~63 : year
+	 */
+	unsigned long long sequence_number;
+
+	/*
+	 * bit 0~7   : revision fixed
+	 * bit 8~15  : revision major
+	 * bit 16~31 : TNxxx
+	 */
+	unsigned int revision;
+	unsigned char eth_addr[4][8];
+	unsigned char _rev[100];
+};
+
+#define TAM3517_READ_EEPROM(info, ret) \
+do {								\
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
+		(void *)info, sizeof(*info)))			\
+		ret = 1;					\
+	else							\
+		ret = 0;					\
+} while (0)
+
+#define TAM3517_READ_MAC_FROM_EEPROM(info)			\
+do {								\
+	char buf[80], ethname[20];				\
+	int i;							\
+	memset(buf, 0, sizeof(buf));				\
+	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
+		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
+			(info)->eth_addr[i][5],			\
+			(info)->eth_addr[i][4],			\
+			(info)->eth_addr[i][3],			\
+			(info)->eth_addr[i][2],			\
+			(info)->eth_addr[i][1],			\
+			(info)->eth_addr[i][0]);			\
+								\
+		if (i)						\
+			sprintf(ethname, "eth%daddr", i);	\
+		else						\
+			strcpy(ethname, "ethaddr");		\
+		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
+		env_set(ethname, buf);				\
+	}							\
+} while (0)
+
+/* The following macros are taken from Technexion's documentation */
+#define TAM3517_sequence_number(info) \
+	((info)->sequence_number % 0x1000000000000LL)
+#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
+#define TAM3517_year(info) ((info)->sequence_number >> 56)
+#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
+#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
+#define TAM3517_revision_tn(info) ((info)->revision >> 16)
+
+#define TAM3517_PRINT_SOM_INFO(info)				\
+do {								\
+	printf("Vendor:%s\n", (info)->customer);		\
+	printf("SOM:   %s\n", (info)->product);			\
+	printf("SeqNr: %02llu%02llu%012llu\n",			\
+		TAM3517_year(info),				\
+		TAM3517_week_of_year(info),			\
+		TAM3517_sequence_number(info));			\
+	printf("Rev:   TN%u %u.%u\n",				\
+		TAM3517_revision_tn(info),			\
+		TAM3517_revision_major(info),			\
+		TAM3517_revision_fixed(info));			\
+} while (0)
+
+#endif
+
+#endif /* __TAM3517_H */
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
new file mode 100644
index 0000000..7a54fe3
--- /dev/null
+++ b/include/configs/tao3530.h
@@ -0,0 +1,234 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the TechNexion TAO-3530 SOM
+ * equipped on Thunder baseboard.
+ *
+ * Edward Lin <linuxfae@technexion.com>
+ * Tapani Utriainen <linuxfae@technexion.com>
+ *
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* commands to include */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * TWL4030
+ */
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+/* Environment information */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=600\0" \
+	"dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
+	"tv_mode=omapfb.mode=tv:ntsc\0" \
+	"video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
+	"lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
+	"extra_options= \0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
+	"nandrootfstype=ubifs\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"${video_mode} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype} " \
+		"${extra_options}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"${video_mode} " \
+		"${network_setting} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} "\
+		"${extra_options}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+
+/* turn on command-line edit/hist/auto */
+
+#define CONFIG_SYS_MEMTEST_START	(0x82000000)		/* memtest */
+								/* defaults */
+#define CONFIG_SYS_MEMTEST_END		(0x83FFFFFF)		/* 64MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH	(0x81000000)	/* dummy address */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+#define CONFIG_SYS_FLASH_BASE		NAND_BASE
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)
+#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/*
+ * USB
+ *
+ * Currently only EHCI is enabled, the MUSB OTG controller
+ * is not enabled.
+ */
+
+/* USB EHCI */
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	162
+
+/* Defines for SPL */
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+/*
+ * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
+ * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
+ */
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13 }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+
+/*
+ * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
+ * older x-loader implementations. And move the BSS area so that it
+ * doesn't overlap with TEXT_BASE.
+ */
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
new file mode 100644
index 0000000..fdd1c52
--- /dev/null
+++ b/include/configs/taurus.h
@@ -0,0 +1,216 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9260ek.h
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+#include <linux/sizes.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
+
+/* Misc CPU related */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		(128 * SZ_1M)
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#if defined(CONFIG_BOARD_TAURUS)
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
+/* USB DFU support */
+
+#define CONFIG_USB_GADGET_AT91
+
+/* DFU class support */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
+#define DFU_MANIFEST_POLL_TIMEOUT	25000
+#endif
+
+/* SPI EEPROM */
+#define TAURUS_SPI_MASK (1 << 4)
+
+#if defined(CONFIG_SPL_BUILD)
+/* SPL related */
+#endif
+
+/* load address */
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+/* bootstrap in spi flash , u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET_REDUND	0x180000
+
+#ifndef CONFIG_SPL_BUILD
+#if defined(CONFIG_BOARD_AXM)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
+		"${gatewayip}:${netmask}:${hostname}:${netdev}::off\0" \
+	"addtest=setenv bootargs ${bootargs} loglevel=4 test\0" \
+	"boot_file=setenv bootfile /${project_dir}/kernel/uImage\0" \
+	"boot_retries=0\0" \
+	"ethact=macb0\0" \
+	"flash_nfs=run nand_kernel;run nfsargs;run addip;" \
+		"upgrade_available;bootm ${kernel_ram};reset\0" \
+	"flash_self=run nand_kernel;run setbootargs;upgrade_available;" \
+		"bootm ${kernel_ram};reset\0" \
+	"flash_self_test=run nand_kernel;run setbootargs addtest;" \
+		"upgrade_available;bootm ${kernel_ram};reset\0" \
+	"hostname=systemone\0" \
+	"kernel_Off=0x00200000\0" \
+	"kernel_Off_fallback=0x03800000\0" \
+	"kernel_ram=0x21500000\0" \
+	"kernel_size=0x00400000\0" \
+	"kernel_size_fallback=0x00400000\0" \
+	"loads_echo=1\0" \
+	"nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} " \
+		"${kernel_size}\0" \
+	"net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};" \
+		"run nfsargs;run addip;upgrade_available;" \
+		"bootm ${kernel_ram};reset\0" \
+	"netdev=eth0\0" \
+	"nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs " \
+		"rw nfsroot=${serverip}:${rootpath} " \
+		"at91sam9_wdt.wdt_timeout=16\0" \
+	"partitionset_active=A\0" \
+	"preboot=echo;echo Type 'run flash_self' to use kernel and root " \
+		"filesystem on memory;echo Type 'run flash_nfs' to use " \
+		"kernel from memory and root filesystem over NFS;echo Type " \
+		"'run net_nfs' to get Kernel over TFTP and mount root " \
+		"filesystem over NFS;echo\0" \
+	"project_dir=systemone\0" \
+	"root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0" \
+	"rootfs=/dev/mtdblock5\0" \
+	"rootfs_fallback=/dev/mtdblock7\0" \
+	"setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops " \
+		"root=${rootfs} rootfstype=jffs2 panic=7 " \
+		"at91sam9_wdt.wdt_timeout=16\0" \
+	"stderr=serial\0" \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"upgrade_available=0\0"
+#endif
+#endif /* #ifndef CONFIG_SPL_BUILD */
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN \
+	ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000)
+
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		(31 * SZ_512)
+#define	CONFIG_SPL_STACK		(ATMEL_BASE_SRAM1 + SZ_16K)
+#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
+					CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
+
+#define CONFIG_SPL_BSS_START_ADDR	CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_BSS_MAX_SIZE		(3 * SZ_512)
+
+#define CONFIG_SYS_NAND_ENABLE_PIN_SPL	(2*32 + 14)
+#define CONFIG_SYS_USE_NANDFLASH	1
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_SIZE		(256 * SZ_1M)
+#define CONFIG_SYS_NAND_PAGE_SIZE	SZ_2K
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(SZ_128K)
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define AT91_PLL_LOCK_TIMEOUT		1000000
+#define CONFIG_SYS_AT91_PLLA		0x202A3F01
+#define CONFIG_SYS_MCKR			0x1300
+#define CONFIG_SYS_MCKR_CSS		(0x02 | CONFIG_SYS_MCKR)
+#define CONFIG_SYS_AT91_PLLB		0x10193F05
+
+#define CONFIG_SPL_PAD_TO		CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_SPL_LEN		CONFIG_SPL_PAD_TO
+
+#endif
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
new file mode 100644
index 0000000..a761c37
--- /dev/null
+++ b/include/configs/tb100.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011-2014 Pierrick Hascoet, Abilis Systems
+ */
+
+#ifndef _CONFIG_TB100_H_
+#define _CONFIG_TB100_H_
+
+#include <linux/sizes.h>
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		SZ_128M
+
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_128K
+#define CONFIG_SYS_BOOTM_LEN		SZ_32M
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+/*
+ * UART configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK		166666666
+
+/*
+ * Even though the board houses Realtek RTL8211E PHY
+ * corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly.
+ * In particular "parse_status" reports link is down.
+ *
+ * Until Realtek PHY driver is fixed fall back to generic PHY driver
+ * which implements all required functionality and behaves much more stable.
+ *
+ * #define CONFIG_PHY_REALTEK
+ *
+ */
+
+/*
+ * Ethernet configuration
+ */
+#define ETH0_BASE_ADDRESS		0xFE100000
+#define ETH1_BASE_ADDRESS		0xFE110000
+
+/*
+ * Command line configuration
+ */
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+
+#endif /* _CONFIG_TB100_H_ */
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
new file mode 100644
index 0000000..46d67a7
--- /dev/null
+++ b/include/configs/tbs2910.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Soeren Moch <smoch@web.de>
+ *
+ * Configuration settings for the TBS2910 MatrixARM board.
+ */
+
+#ifndef __TBS2910_CONFIG_H
+#define __TBS2910_CONFIG_H
+
+#include "mx6_common.h"
+
+/* General configuration */
+
+#define CONFIG_MACH_TYPE		3980
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_IMX_THERMAL
+
+/* Physical Memory Map */
+#define CONFIG_SYS_SDRAM_BASE		MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END \
+	(CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ		0x10000000
+
+/* Serial console */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE /* select UART1/UART2 */
+
+/* Framebuffer */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+/* PCI */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
+#endif
+
+/* SATA */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_SYS_64BIT_LBA
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#ifdef CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USBD_HS
+#endif /* CONFIG_CMD_USB_MASS_STORAGE */
+#endif /* CONFIG_CMD_USB      */
+
+/* Environment organization */
+#define CONFIG_SYS_MMC_ENV_DEV		2 /* overwritten on SD boot */
+#define CONFIG_SYS_MMC_ENV_PART		1 /* overwritten on SD boot */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_OFFSET		(384 * 1024)
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOARD_SIZE_LIMIT		392192 /* (CONFIG_ENV_OFFSET - 1024) */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
+	"bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
+			"video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
+	"bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
+	"bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
+			"${bootargs_mmc3}\0" \
+	"bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
+			"rdinit=/sbin/init enable_wait_mode=off\0" \
+	"bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
+			"mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
+	"bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
+	"bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
+			"run bootargs_upd; " \
+			"bootm 0x10800000 0x10d00000\0" \
+	"console=ttymxc0\0" \
+	"fan=gpio set 92\0" \
+	"set_con_serial=setenv stdout serial; " \
+			"setenv stderr serial\0" \
+	"set_con_hdmi=setenv stdout serial,vga; " \
+			"setenv stderr serial,vga\0" \
+	"stderr=serial,vga\0" \
+	"stdin=serial,usbkbd\0" \
+	"stdout=serial,vga\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc rescan; " \
+	"if run bootcmd_up1; then " \
+		"run bootcmd_up2; " \
+	"else " \
+		"run bootcmd_mmc; " \
+	"fi"
+
+#endif			       /* __TBS2910_CONFIG_H * */
diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
new file mode 100644
index 0000000..b637832
--- /dev/null
+++ b/include/configs/tec-ng.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra30-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamontenâ„¢ NG Evaluation Carrier"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* SPI */
+#define CONFIG_TEGRA_SLINK_CTRLS       6
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* Tag support */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tec.h b/include/configs/tec.h
new file mode 100644
index 0000000..907c8d5
--- /dev/null
+++ b/include/configs/tec.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011-2012
+ *  Avionic Design GmbH <www.avionic-design.de>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra20-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamonten Evaluation Carrier"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+/* NAND support */
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Environment in NAND, aligned to start of last sector */
+#define CONFIG_ENV_OFFSET		(SZ_512M - SZ_128K) /* 128K sectors */
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
new file mode 100644
index 0000000..fae0e76
--- /dev/null
+++ b/include/configs/tegra-common-post.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __TEGRA_COMMON_POST_H
+#define __TEGRA_COMMON_POST_H
+
+/*
+ * Size of malloc() pool
+ */
+#ifdef CONFIG_DFU_OVER_USB
+#define CONFIG_SYS_MALLOC_LEN	(SZ_4M + \
+					CONFIG_SYS_DFU_DATA_BUF_SIZE + \
+					CONFIG_SYS_DFU_MAX_FILE_SIZE)
+#else
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */
+#endif
+
+#define CONFIG_SYS_NONCACHED_MEMORY	(1 << 20)	/* 1 MiB */
+
+#ifndef CONFIG_SPL_BUILD
+#ifndef BOOT_TARGET_DEVICES
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+#endif
+#include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
+
+#ifdef CONFIG_TEGRA_KEYBOARD
+#define STDIN_KBD_KBC ",tegra-kbc"
+#else
+#define STDIN_KBD_KBC ""
+#endif
+
+#ifdef CONFIG_USB_KEYBOARD
+#define STDIN_KBD_USB ",usbkbd"
+#else
+#define STDIN_KBD_USB ""
+#endif
+
+#ifdef CONFIG_LCD
+#define STDOUT_LCD ",lcd"
+#else
+#define STDOUT_LCD ""
+#endif
+
+#ifdef CONFIG_DM_VIDEO
+#define STDOUT_VIDEO ",vidconsole"
+#else
+#define STDOUT_VIDEO ""
+#endif
+
+#ifdef CONFIG_CROS_EC_KEYB
+#define STDOUT_CROS_EC	",cros-ec-keyb"
+#else
+#define STDOUT_CROS_EC	""
+#endif
+
+#define TEGRA_DEVICE_SETTINGS \
+	"stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC "\0" \
+	"stdout=serial" STDOUT_LCD STDOUT_VIDEO "\0" \
+	"stderr=serial" STDOUT_LCD STDOUT_VIDEO "\0" \
+	""
+
+#ifndef BOARD_EXTRA_ENV_SETTINGS
+#define BOARD_EXTRA_ENV_SETTINGS
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
+#define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
+#endif
+
+#ifdef CONFIG_ARM64
+#define FDT_HIGH "ffffffffffffffff"
+#define INITRD_HIGH "ffffffffffffffff"
+#else
+#define FDT_HIGH "ffffffff"
+#define INITRD_HIGH "ffffffff"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	TEGRA_DEVICE_SETTINGS \
+	MEM_LAYOUT_ENV_SETTINGS \
+	"fdt_high=" FDT_HIGH "\0" \
+	"initrd_high=" INITRD_HIGH "\0" \
+	BOOTENV \
+	BOARD_EXTRA_ENV_SETTINGS \
+	CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
+
+#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
+#define CONFIG_TEGRA_SPI
+#endif
+
+/* overrides for SPL build here */
+#ifdef CONFIG_SPL_BUILD
+
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+
+/* remove I2C support */
+#ifdef CONFIG_SYS_I2C_TEGRA
+#undef CONFIG_SYS_I2C_TEGRA
+#endif
+
+/* remove USB */
+#ifdef CONFIG_USB_EHCI_TEGRA
+#undef CONFIG_USB_EHCI_TEGRA
+#endif
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* __TEGRA_COMMON_POST_H */
diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h
new file mode 100644
index 0000000..e6b61c4
--- /dev/null
+++ b/include/configs/tegra-common-usb-gadget.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_COMMON_USB_GADGET_H_
+#define _TEGRA_COMMON_USB_GADGET_H_
+
+#ifndef CONFIG_SPL_BUILD
+/* USB gadget mode support*/
+#ifndef CONFIG_TEGRA20
+#define CONFIG_CI_UDC_HAS_HOSTPC
+#endif
+/* DFU protocol */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
+#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_32M
+#endif
+
+#endif /* _TEGRA_COMMON_USB_GADGET_H_ */
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
new file mode 100644
index 0000000..84f671d
--- /dev/null
+++ b/include/configs/tegra-common.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA_COMMON_H_
+#define _TEGRA_COMMON_H_
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
+
+#include <asm/arch/tegra.h>		/* get chip and board defs */
+
+/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
+#ifndef CONFIG_ARM64
+#define CONFIG_SYS_TIMER_RATE		1000000
+#define CONFIG_SYS_TIMER_COUNTER	NV_PA_TMRUS_BASE
+#endif
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+
+/* Environment */
+#define CONFIG_ENV_SIZE			0x2000	/* Total Size Environment */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * Common HW configuration.
+ * If this varies between SoCs later, move to tegraNN-common.h
+ * Note: This is number of devices, not max device ID.
+ */
+#define CONFIG_SYS_MMC_MAX_DEVICE 4
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Increasing the size of the IO buffer as default nfsargs size is more
+ *  than 256 and so it is not possible to edit it
+ */
+#define CONFIG_SYS_CBSIZE		(1024 * 2) /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		64	/* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		NV_PA_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
+
+#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* 256M */
+
+#ifndef CONFIG_ARM64
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#endif
+
+#ifndef CONFIG_ARM64
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_TEXT_BASE - \
+						CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
+#endif
+
+#endif /* _TEGRA_COMMON_H_ */
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
new file mode 100644
index 0000000..d3a7045
--- /dev/null
+++ b/include/configs/tegra114-common.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#ifndef _TEGRA114_COMMON_H_
+#define _TEGRA114_COMMON_H_
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_STACKBASE	0x83800000	/* 56MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 32M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
+ *   the compressed kernel to be up to 32M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x81000000
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdt_addr_r=0x83000000\0" \
+	"ramdisk_addr_r=0x83100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+
+#endif /* _TEGRA114_COMMON_H_ */
diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h
new file mode 100644
index 0000000..522993b
--- /dev/null
+++ b/include/configs/tegra124-common.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA124_COMMON_H_
+#define _TEGRA124_COMMON_H_
+
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_STACKBASE	0x83800000	/* 56MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 32M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
+ *   the compressed kernel to be up to 32M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x81000000
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdt_addr_r=0x83000000\0" \
+	"ramdisk_addr_r=0x83100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+
+/* GPU needs setup */
+#define CONFIG_TEGRA_GPU
+
+#endif /* _TEGRA124_COMMON_H_ */
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
new file mode 100644
index 0000000..b4936cc
--- /dev/null
+++ b/include/configs/tegra186-common.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2013-2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _TEGRA186_COMMON_H_
+#define _TEGRA186_COMMON_H_
+
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+/* Generic Interrupt Controller */
+#define CONFIG_GICV2
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x80080000
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+#endif
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
new file mode 100644
index 0000000..1e31d82
--- /dev/null
+++ b/include/configs/tegra20-common.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA20_COMMON_H_
+#define _TEGRA20_COMMON_H_
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_STACKBASE	0x03800000	/* 56MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 32M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
+ *   the compressed kernel to be up to 32M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x01000000
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x10000000\0" \
+	"pxefile_addr_r=0x10100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdt_addr_r=0x03000000\0" \
+	"ramdisk_addr_r=0x03100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SYS_SPL_MALLOC_START	0x00090000
+#define CONFIG_SPL_STACK		0x000ffffc
+
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
+
+#ifdef CONFIG_TEGRA_LP0
+#define TEGRA_LP0_ADDR			0x1C406000
+#define TEGRA_LP0_SIZE			0x2000
+#define TEGRA_LP0_VEC \
+	"lp0_vec=" __stringify(TEGRA_LP0_SIZE)  \
+	"@" __stringify(TEGRA_LP0_ADDR) " "
+#else
+#define TEGRA_LP0_VEC
+#endif
+
+/*
+ * This parameter affects a TXFILLTUNING field that controls how much data is
+ * sent to the latency fifo before it is sent to the wire. Without this
+ * parameter, the default (2) causes occasional Data Buffer Errors in OUT
+ * packets depending on the buffer address and size.
+ */
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_EHCI_IS_TDI
+
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#endif /* _TEGRA20_COMMON_H_ */
diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h
new file mode 100644
index 0000000..1c53311
--- /dev/null
+++ b/include/configs/tegra210-common.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2015
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA210_COMMON_H_
+#define _TEGRA210_COMMON_H_
+
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/* Generic Interrupt Controller */
+#define CONFIG_GICV2
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x80080000
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+
+/* GPU needs setup */
+#define CONFIG_TEGRA_GPU
+
+#endif /* _TEGRA210_COMMON_H_ */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
new file mode 100644
index 0000000..54bc675
--- /dev/null
+++ b/include/configs/tegra30-common.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TEGRA30_COMMON_H_
+#define _TEGRA30_COMMON_H_
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_STACKBASE	0x83800000	/* 56MB */
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 32M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
+ *   the compressed kernel to be up to 32M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x81000000
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdt_addr_r=0x83000000\0" \
+	"ramdisk_addr_r=0x83100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+
+#endif /* _TEGRA30_COMMON_H_ */
diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h
new file mode 100644
index 0000000..0c563e7
--- /dev/null
+++ b/include/configs/theadorable-x86-common.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+/*
+ * Common options, macros and default environment for all
+ * theadorable x86 based boards
+ */
+
+#ifndef __THEADORABLE_X86_COMMON_H
+#define __THEADORABLE_X86_COMMON_H
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \
+					"stdout=serial\0" \
+					"stderr=serial\0"
+
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+
+/* Environment settings */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x006ec000
+#define CONFIG_ENV_OFFSET_REDUND	\
+	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+
+#undef CONFIG_BOOTCOMMAND
+#undef CONFIG_EXTRA_ENV_SETTINGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"tftpdir=" DEF_ENV_TFTPDIR "\0"				\
+	"eth_init=" DEF_ENV_ETH_INIT "\0"			\
+	"ubuntu_part=" __stringify(DEF_ENV_UBUNTU_PART) "\0"	\
+	"yocto_part=" __stringify(DEF_ENV_YOCTO_PART) "\0"	\
+	"ubuntu_tty=" __stringify(DEF_ENV_UBUNTU_TTY) "\0"	\
+	"yocto_tty=" __stringify(DEF_ENV_YOCTO_TTY) "\0"	\
+	"start_eth=if test -n \"${eth_init}\";"			\
+		"then run eth_init;else sleep 0;fi\0"		\
+	"kernel-ver=4.8.0-54-generic\0"				\
+	"boot=zboot 03000000 0 04000000 ${filesize}\0"		\
+	"mtdparts=mtdparts=intel-spi:4k(descriptor),7084k(me)," \
+		"8k(env1),8k(env2),64k(mrc),640k(u-boot),"	\
+		"64k(vga),-(fsp)\0"				\
+	"addtty_ubuntu=setenv bootargs ${bootargs} "		\
+		"console=ttyS${ubuntu_tty},${baudrate}\0"	\
+	"addtty_yocto=setenv bootargs ${bootargs} "		\
+		"console=ttyS${yocto_tty},${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"addmisc=setenv bootargs ${bootargs} "			\
+		"intel-spi.writeable=1 vmalloc=300M "		\
+		"pci=realloc=on,hpmemsize=0,hpiosize=0\0"	\
+	"bootcmd=if env exists recovery_status;"		\
+		"then run swupdate;"				\
+		"else run yocto_boot;run swupdate;"		\
+		"fi\0"						\
+	"setroot=part uuid scsi 0:${partnr} uuid;"		\
+		"setenv root PARTUUID=${uuid}\0"		\
+	"setroot_ubuntu=setenv partnr ${ubuntu_part};run setroot\0" \
+	"setroot_yocto=setenv partnr ${yocto_part};run setroot\0" \
+	"ubuntu_args=setenv bootargs "				\
+		"root=${root} ro\0"				\
+	"ubuntu_args_quiet=setenv bootargs "			\
+		"root=${root} ro quiet\0"			\
+	"ubuntu_load=load scsi 0:${ubuntu_part} 03000000 "	\
+		"/boot/vmlinuz-${kernel-ver};"			\
+		"load scsi 0:${ubuntu_part} 04000000 "		\
+		"/boot/initrd.img-${kernel-ver}\0"		\
+	"ubuntu_boot=run setroot_ubuntu ubuntu_args_quiet "	\
+		"addmtd addmisc ubuntu_load boot\0"		\
+	"ubuntu_boot_console=run setroot_ubuntu ubuntu_args "	\
+		"addtty_ubuntu addmtd addmisc ubuntu_load boot\0" \
+	"net_args=setenv bootargs root=${root} ro\0"		\
+	"net_boot=run start_eth setroot_ubuntu net_args "	\
+		"addtty_ubuntu addmtd addmisc;"			\
+		"tftp 03000000 ${tftpdir}/bzImage;"		\
+		"load scsi 0:${ubuntu_part} 04000000 "		\
+		"/boot/initrd.img-${kernel-ver};"		\
+		"run boot\0"					\
+	"yocto_args=setenv bootargs root=${root} "		\
+		"panic=1\0"					\
+	"yocto_args_fast=setenv bootargs root=${root} "		\
+		"quiet panic=1\0"				\
+	"yocto_boot=run setroot_yocto yocto_args addmtd addmisc " \
+		"addtty_yocto;"	\
+		"if run yocto_load;then zboot 03000000;fi\0"	\
+	"yocto_boot_fast=run setroot_yocto yocto_args_fast addmtd " \
+		"addmisc addtty_yocto yocto_load;zboot 03000000\0" \
+	"yocto_boot_tftp=run setroot_yocto yocto_args addmtd "	\
+		"addmisc addtty_yocto "				\
+		"start_eth yocto_load_tftp;zboot 03000000\0"	\
+	"yocto_kernel=bzImage\0"				\
+	"yocto_load=load scsi 0:${yocto_part} 03000000 "	\
+		"/boot/${yocto_kernel}\0"			\
+	"yocto_load_tftp=tftp 03000000 dfi/bzImage\0"		\
+	"swupdate=if env exists swupdate_factory;"		\
+		"then run swupdate_usb;run swupdate_run;"	\
+		"else setenv swupdate_part 2;run swupdate_mmc;" \
+			"run swupdate_run;setenv swupdate_part 1;" \
+			"run swupdate_mmc;run swupdate_usb;"	\
+			"run swupdate_run;"			\
+		"fi\0"						\
+	"swupdate-initrd=/boot/swupdate-image-theadorable.ext4.gz\0" \
+	"swupdate-kernel=/boot/bzImage\0"			\
+	"swupdate_args=setenv bootargs root=/dev/ram rw panic=1\0" \
+	"swupdate_dev=0\0"					\
+	"swupdate_factory=0\0"					\
+	"swupdate_interface=usb\0"				\
+	"swupdate_kernel=vmlinuz-4.4.0-28-generic\0"		\
+	"swupdate_load=load ${swupdate_interface} ${swupdate_dev}:" \
+		"${swupdate_part} 03000000 ${swupdate-kernel}"	\
+		" && load ${swupdate_interface} ${swupdate_dev}:" \
+		"${swupdate_part} 04000000 ${swupdate-initrd}\0" \
+	"swupdate_mmc=setenv swupdate_interface mmc;"		\
+		"setenv swupdate_dev ${swupdate_mmcdev};"	\
+		"setenv swupdate_part 1;"			\
+		"mmc dev ${swupdate_dev};mmc rescan\0"		\
+	"swupdate_mmcdev=0\0"					\
+	"swupdate_part=1\0"					\
+	"swupdate_run=run swupdate_args addtty_yocto addmtd addmisc;" \
+		"if run swupdate_load;then run boot;"		\
+		"else echo SWUpdate cannot be started from "	\
+		"${swupdate_interface};"			\
+		"fi\0"						\
+	"swupdate_usb=setenv swupdate_interface usb;"		\
+		"setenv swupdate_dev 0;setenv swupdate_part 1;"	\
+		"usb start\0"					\
+	"logo_tftp=tftp ${loadaddr} ${tftpdir}/logo.bmp;"	\
+		"bmp display ${loadaddr}\0"			\
+	"preboot=scsi scan;load scsi 0:${ubuntu_part} ${loadaddr} " \
+		"/boot/logo/logo.bmp;bmp display ${loadaddr}\0" \
+	"rootpath=/tftpboot/theadorable-x86-conga/work/"	\
+		"rootfs-yocto-swupdate-2017-03-29\0"		\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
+		"${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
+	"set_bootargs_nfs=setenv bootargs root=/dev/nfs rw "	\
+		"nfsroot=${serverip}:${rootpath},tcp,nfsvers=3\0" \
+	"net_nfs=run start_eth set_bootargs_nfs addtty_yocto addip " \
+		"addmtd addmisc;tftp 03000000 ${tftpdir}/bzImage;" \
+		"zboot 03000000\0"				\
+	"load_uboot=tftp ${loadaddr} ${tftpdir}/u-boot.rom\0"	\
+	"update_uboot=sf probe;"				\
+		"sf update ${loadaddr} 0 800000;saveenv\0"	\
+	"upd_uboot=run start_eth load_uboot update_uboot\0"
+
+#endif /* __THEADORABLE_X86_COMMON_H */
diff --git a/include/configs/theadorable-x86-conga-qa3-e3845.h b/include/configs/theadorable-x86-conga-qa3-e3845.h
new file mode 100644
index 0000000..1c4362d
--- /dev/null
+++ b/include/configs/theadorable-x86-conga-qa3-e3845.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+/* Set the board specific parameters */
+#define DEF_ENV_TFTPDIR		"theadorable-x86-conga"
+#define DEF_ENV_ETH_INIT	""
+#define DEF_ENV_UBUNTU_PART	2
+#define DEF_ENV_UBUNTU_TTY	0	/* Use ttyS0 */
+#define DEF_ENV_YOCTO_PART	3
+#define DEF_ENV_YOCTO_TTY	0	/* Use ttyS0 */
+
+/*
+ * Include the theadorable-x86 common options, macros and default
+ * environment
+ */
+#include <configs/theadorable-x86-common.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/theadorable-x86-dfi-bt700.h b/include/configs/theadorable-x86-dfi-bt700.h
new file mode 100644
index 0000000..bb3186e
--- /dev/null
+++ b/include/configs/theadorable-x86-dfi-bt700.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+/* Use BayTrail internal HS UART which is memory-mapped */
+#undef  CONFIG_SYS_NS16550_PORT_MAPPED
+
+/* Set the board specific parameters */
+#define DEF_ENV_TFTPDIR		"theadorable-x86-dfi"
+#define DEF_ENV_ETH_INIT	"usb reset"
+#define DEF_ENV_UBUNTU_PART	1
+#define DEF_ENV_UBUNTU_TTY	4	/* Use ttyS4 */
+#define DEF_ENV_YOCTO_PART	2
+#define DEF_ENV_YOCTO_TTY	1	/* Use ttyS1 */
+
+/*
+ * Include the theadorable-x86 common options, macros and default
+ * environment
+ */
+#include <configs/theadorable-x86-common.h>
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
new file mode 100644
index 0000000..45cd7e2
--- /dev/null
+++ b/include/configs/theadorable.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_THEADORABLE_H
+#define _CONFIG_THEADORABLE_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+
+/*
+ * The debugging version enables USB support via defconfig.
+ * This version should also enable all other non-production
+ * interfaces / features.
+ */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE1		MVEBU_TWSI1_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+#define CONFIG_ENV_OVERWRITE
+
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0x10000000\0"		\
+	"initrd_high=0x10000000\0"
+
+/* SATA support */
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_LBA48
+
+/* Enable LCD and reserve 512KB from top of memory*/
+#define CONFIG_SYS_MEM_TOP_HIDE		0x80000
+
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+
+/* FPGA programming support */
+#define CONFIG_FPGA_STRATIX_V
+
+/*
+ * Bootcounter
+ */
+/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
+#define BOOTCOUNT_ADDR			0x1000
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
+ * 0x4000.4030			bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
+ * 0x4007.fffc			BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+/* SPL related SPI defines */
+#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CONFIG_DDR_FIXED_SIZE		(2 << 20)	/* 2GiB */
+
+#endif /* _CONFIG_THEADORABLE_H */
diff --git a/include/configs/thuban.h b/include/configs/thuban.h
new file mode 100644
index 0000000..569df9e
--- /dev/null
+++ b/include/configs/thuban.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef __CONFIG_THUBAN_H
+#define __CONFIG_THUBAN_H
+
+#include "siemens-am33x-common.h"
+
+#define DDR_PLL_FREQ	303
+
+#define BOARD_DFU_BUTTON_GPIO	27	/* Use as default */
+#define GPIO_LAN9303_NRST	88	/* GPIO2_24 = gpio88 */
+
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	"button_dfu0=27\0" \
+	"led0=103,1,0\0" \
+	"led1=64,0,1\0"
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* Define own nand partitions */
+#define CONFIG_ENV_OFFSET_REDUND    0x2E0000
+#define CONFIG_ENV_SIZE_REDUND      0x2000
+#define CONFIG_ENV_RANGE        (4 * CONFIG_SYS_ENV_SECT_SIZE)
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=thuban\0" \
+	"ubi_off=2048\0"\
+	"nand_img_size=0x400000\0" \
+	"optargs=\0" \
+	"preboot=draco_led 0\0" \
+	CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	CONFIG_ENV_SETTINGS_V2 \
+	CONFIG_ENV_SETTINGS_NAND_V2
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+	"run dfu_start; " \
+	"reset; " \
+"fi;" \
+"run nand_boot;" \
+"run nand_boot_backup;" \
+"reset;"
+
+#else
+
+#define CONFIG_BOOTCOMMAND			\
+	"setenv autoload no; "			\
+	"dhcp; "				\
+	"if tftp 80000000 debrick.scr; then "	\
+		"source 80000000; "		\
+	"fi"
+#endif
+#endif	/* CONFIG_SPL_BUILD */
+#endif	/* ! __CONFIG_THUBAN_H */
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
new file mode 100644
index 0000000..619571d
--- /dev/null
+++ b/include/configs/thunderx_88xx.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/**
+ * (C) Copyright 2014, Cavium Inc.
+**/
+
+#ifndef __THUNDERX_88XX_H__
+#define __THUNDERX_88XX_H__
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_THUNDERX
+
+#define CONFIG_SYS_64BIT
+
+#define MEM_BASE			0x00500000
+
+#define CONFIG_SYS_LOWMEM_BASE		MEM_BASE
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* SMP Spin Table Definitions */
+#define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */
+
+#define CONFIG_SYS_MEMTEST_START	MEM_BASE
+#define CONFIG_SYS_MEMTEST_END		(MEM_BASE + PHYS_SDRAM_1_SIZE)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/* PL011 Serial Configuration */
+
+#define CONFIG_PL011_CLOCK		24000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			(0x801000000000)
+#define GICR_BASE			(0x801000002000)
+#define CONFIG_SYS_SERIAL0		0x87e024000000
+#define CONFIG_SYS_SERIAL1		0x87e025000000
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR		(MEM_BASE)
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1			(MEM_BASE)	  /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE		(0x80000000-MEM_BASE)	/* 2048 MB */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Initial environment variables */
+#define UBOOT_IMG_HEAD_SIZE		0x40
+/* C80000 - 0x40 */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+					"kernel_addr=08007ffc0\0"	\
+					"fdt_addr=0x94C00000\0"		\
+					"fdt_high=0x9fffffff\0"
+
+/* Do not preserve environment */
+#define CONFIG_ENV_SIZE			0x1000
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		64		/* max command args */
+#define CONFIG_NO_RELOCATION		1
+#define PLL_REF_CLK			50000000	/* 50 MHz */
+#define NS_PER_REF_CLK_TICK		(1000000000/PLL_REF_CLK)
+
+#endif /* __THUNDERX_88XX_H__ */
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
new file mode 100644
index 0000000..46b1b41
--- /dev/null
+++ b/include/configs/ti814x_evm.h
@@ -0,0 +1,158 @@
+/*
+ * ti814x_evm.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_TI814X_EVM_H
+#define __CONFIG_TI814X_EVM_H
+
+#include <asm/arch/omap.h>
+
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_MACH_TYPE		MACH_TYPE_TI8148EVM
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG		/* for ramdisk support */
+
+/* commands to include */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"fdtaddr=0x80F80000\0" \
+	"rdaddr=0x81000000\0" \
+	"bootfile=/boot/uImage\0" \
+	"fdtfile=\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 ro\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootm ${loadaddr}\0" \
+	"fdtfile=ti814x-evm.dtb\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loaduimage; then " \
+			"run mmcboot;" \
+		"fi;" \
+	"fi;" \
+
+/* Clock Defines */
+#define V_OSCK			24000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
+					+ PHYS_DRAM_1_SIZE - (8 << 12))
+
+#define CONFIG_SYS_LOAD_ADDR		0x81000000	/* Default */
+
+/**
+ * Physical Memory Map
+ */
+#define PHYS_DRAM_1_SIZE		0x20000000	/* 512MB */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1024MB */
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/**
+ * Platform/Board specific defs
+ */
+#define CONFIG_SYS_TIMERBASE		0x4802E000
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(48000000)
+#define CONFIG_SYS_NS16550_COM1		0x48020000	/* Base EVM has UART0 */
+
+/* CPU */
+
+#define CONFIG_ENV_OVERWRITE
+
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
+
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80800000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* Ethernet */
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_PHY_ET1011C
+#define CONFIG_PHY_ET1011C_TX_CLK_FIX
+
+#endif	/* ! __CONFIG_TI814X_EVM_H */
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
new file mode 100644
index 0000000..fc5608b
--- /dev/null
+++ b/include/configs/ti816x_evm.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ti816x_evm.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ */
+
+#ifndef __CONFIG_TI816X_EVM_H
+#define __CONFIG_TI816X_EVM_H
+
+#include <configs/ti_armv7_omap.h>
+#include <asm/arch/omap.h>
+
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_MACH_TYPE		MACH_TYPE_TI8168EVM
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	DEFAULT_LINUX_BOOT_ENV \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+
+#define CONFIG_BOOTCOMMAND			\
+	"mmc rescan;"				\
+	"fatload mmc 0 ${loadaddr} uImage;"	\
+	"bootm ${loadaddr}"			\
+
+/* Clock Defines */
+#define V_OSCK          24000000    /* Clock output from T2 */
+#define V_SCLK          (V_OSCK >> 1)
+
+#define CONFIG_CMD_ASKENV
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2048MB */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/**
+ * Platform/Board specific defs
+ */
+#define CONFIG_SYS_CLK_FREQ     27000000
+#define CONFIG_SYS_TIMERBASE    0x4802E000
+#define CONFIG_SYS_PTV          2   /* Divisor: 2^(PTV+1) => 8 */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK      (48000000)
+#define CONFIG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+
+/*
+ * GPMC NAND block.  We support 1 device and the physical address to
+ * access CS0 at is 0x8000000.
+ */
+#define CONFIG_SYS_NAND_BASE		0x8000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* NAND: SPL related configs */
+
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+/* NAND: driver related configs */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
+#define CONFIG_ENV_OFFSET		0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+
+/* Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#endif
+#endif
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
new file mode 100644
index 0000000..19e1e22
--- /dev/null
+++ b/include/configs/ti_am335x_common.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ti_am335x_common.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * For more details, please see the technical documents listed at
+ * http://www.ti.com/product/am3359#technicaldocuments
+ */
+
+#ifndef __CONFIG_TI_AM335X_COMMON_H__
+#define __CONFIG_TI_AM335X_COMMON_H__
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+
+#include <asm/arch/omap.h>
+
+/* NS16550 Configuration */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NS16550_SERIAL
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#endif
+#endif
+#define CONFIG_SYS_NS16550_CLK		48000000
+
+#ifndef CONFIG_SPL_BUILD
+/* Network defines. */
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT         10
+#endif
+
+/*
+ * SPL related defines.  The Public RAM memory map the ROM defines the
+ * area between 0x402F0400 and 0x4030B800 as a download area and
+ * 0x4030B800 to 0x4030CE00 as a public stack area.  The ROM also
+ * supports X-MODEM loading via UART, and we leverage this and then use
+ * Y-MODEM to load u-boot.img, when booted over UART.
+ */
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (128 << 20))
+
+/* Enable the watchdog inside of SPL */
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * When building U-Boot such that there is no previous loader
+ * we need to call board_early_init_f.  This is taken care of in
+ * s_init when we have SPL used.
+ */
+
+/* Now bring in the rest of the common code. */
+#include <configs/ti_armv7_omap.h>
+
+#endif	/* __CONFIG_TI_AM335X_COMMON_H__ */
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
new file mode 100644
index 0000000..6d15304
--- /dev/null
+++ b/include/configs/ti_armv7_common.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ti_armv7_common.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * The various ARMv7 SoCs from TI all share a number of IP blocks when
+ * implementing a given feature.  Rather than define these in every
+ * board or even SoC common file, we define a common file to be re-used
+ * in all cases.  While technically true that some of these details are
+ * configurable at the board design, they are common throughout SoC
+ * reference platforms as well as custom designs and become de facto
+ * standards.
+ */
+
+#ifndef __CONFIG_TI_ARMV7_COMMON_H__
+#define __CONFIG_TI_ARMV7_COMMON_H__
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Our DDR memory always starts at 0x80000000 and U-Boot shall have
+ * relocated itself to higher in memory by the time this value is used.
+ * However, set this to a 32MB offset to allow for easier Linux kernel
+ * booting as the default is often used as the kernel load address.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+/*
+ * We setup defaults based on constraints from the Linux kernel, which should
+ * also be safe elsewhere.  We have the default load at 32MB into DDR (for
+ * the kernel), FDT above 128MB (the maximum location for the end of the
+ * kernel), and the ramdisk 512KB above that (allowing for hopefully never
+ * seen large trees).  We say all of this must be within the first 256MB
+ * as that will normally be within the kernel lowmem and thus visible via
+ * bootm_size and we only run on platforms with 256MB or more of memory.
+ */
+#define DEFAULT_LINUX_BOOT_ENV \
+	"loadaddr=0x82000000\0" \
+	"kernel_addr_r=0x82000000\0" \
+	"fdtaddr=0x88000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"rdaddr=0x88080000\0" \
+	"ramdisk_addr_r=0x88080000\0" \
+	"scriptaddr=0x80000000\0" \
+	"pxefile_addr_r=0x80100000\0" \
+	"bootm_size=0x10000000\0" \
+	"boot_fdt=try\0"
+
+#define DEFAULT_FIT_TI_ARGS \
+	"boot_fit=0\0" \
+	"addr_fit=0x90000000\0" \
+	"name_fit=fitImage\0" \
+	"update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile ${name_fit}\0" \
+	"get_overlaystring=" \
+		"for overlay in $overlay_files;" \
+		"do;" \
+		"setenv overlaystring ${overlaystring}'#'${overlay};" \
+		"done;\0" \
+	"run_fit=bootm ${addr_fit}#${fdtfile}${overlaystring}\0" \
+	"loadfit=run args_mmc; run run_fit;\0" \
+
+/*
+ * DDR information.  If the CONFIG_NR_DRAM_BANKS is not defined,
+ * we say (for simplicity) that we have 1 bank, always, even when
+ * we have more.  We always start at 0x80000000, and we place the
+ * initial stack pointer in our SRAM. Otherwise, we can define
+ * CONFIG_NR_DRAM_BANKS before including this file.
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+#ifndef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
+						GENERATED_GBL_DATA_SIZE)
+#endif
+
+/* Timer information. */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/* If DM_I2C, enable non-DM I2C support */
+#if !defined(CONFIG_DM_I2C)
+#define CONFIG_I2C
+#define CONFIG_SYS_I2C
+#endif
+
+/*
+ * The following are general good-enough settings for U-Boot.  We set a
+ * large malloc pool as we generally have a lot of DDR, and we opt for
+ * function over binary size in the main portion of U-Boot as this is
+ * generally easily constrained later if needed.  We enable the config
+ * options that give us information in the environment about what board
+ * we are on so we do not need to rely on the command prompt.  We set a
+ * console baudrate of 115200 and use the default baud rate table.
+ */
+#define CONFIG_SYS_MALLOC_LEN		SZ_32M
+#define CONFIG_ENV_OVERWRITE		/* Overwrite ethaddr / serial# */
+
+/* As stated above, the following choices are optional. */
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS		64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		1024
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * When we have SPI, NOR or NAND flash we expect to be making use of
+ * mtdparts, both for ease of use in U-Boot and for passing information
+ * on to the Linux kernel.
+ */
+
+/*
+ * Our platforms make use of SPL to initalize the hardware (primarily
+ * memory) enough for full U-Boot to be loaded. We make use of the general
+ * SPL framework found under common/spl/.  Given our generally common memory
+ * map, we set a number of related defaults and sizes here.
+ */
+#if !defined(CONFIG_NOR_BOOT) && \
+	!(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX))
+
+/*
+ * We also support Falcon Mode so that the Linux kernel can be booted
+ * directly from SPL. This is not currently available on HS devices.
+ */
+
+/*
+ * Place the image at the start of the ROM defined image space (per
+ * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined
+ * downloaded image area minus 1KiB for scratch space.  We initalize DRAM as
+ * soon as we can so that we can place stack, malloc and BSS there.  We load
+ * U-Boot itself into memory at 0x80800000 for legacy reasons (to not conflict
+ * with older SPLs).  We have our BSS be placed 2MiB after this, to allow for
+ * the default Linux kernel address of 0x80008000 to work with most sized
+ * kernels, in the Falcon Mode case.  We have the SPL malloc pool at the end
+ * of the BSS area.  We suggest that the stack be placed at 32MiB after the
+ * start of DRAM to allow room for all of the above (handled in Kconfig).
+ */
+#ifndef CONFIG_SPL_BSS_START_ADDR
+#define CONFIG_SPL_BSS_START_ADDR	0x80a00000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+#endif
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					 CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_8M
+#endif
+#ifndef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+#endif
+
+
+/* FAT sd card locations. */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#ifndef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* FAT */
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"args"
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x1700  /* address 0x2E0000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x1500  /* address 0x2A0000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x200   /* 256KiB */
+#endif
+
+/* General parts of the framework, required. */
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#endif
+#endif /* !CONFIG_NOR_BOOT */
+
+/* Generic Environment Variables */
+
+#ifdef CONFIG_CMD_NET
+#define NETARGS \
+	"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+		"::off\0" \
+	"nfsopts=nolock\0" \
+	"rootpath=/export/rootfs\0" \
+	"netloadimage=tftp ${loadaddr} ${bootfile}\0" \
+	"netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"run netloadimage; " \
+		"run netloadfdt; " \
+		"run netargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#else
+#define NETARGS ""
+#endif
+
+#endif	/* __CONFIG_TI_ARMV7_COMMON_H__ */
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
new file mode 100644
index 0000000..ba12428
--- /dev/null
+++ b/include/configs/ti_armv7_keystone2.h
@@ -0,0 +1,302 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common configuration header file for all Keystone II EVM platforms
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#ifndef __CONFIG_KS2_EVM_H
+#define __CONFIG_KS2_EVM_H
+
+#define CONFIG_SOC_KEYSTONE
+
+/* U-Boot Build Configuration */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 2nd stage loader */
+
+/* SoC Configuration */
+#define CONFIG_SPL_TARGET		"u-boot-spi.gph"
+
+/* Memory Configuration */
+#define CONFIG_SYS_LPAE_SDRAM_BASE	0x800000000
+#define CONFIG_MAX_RAM_BANK_SIZE	(2 << 30)       /* 2GB */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_ISW_ENTRY_ADDR - \
+					GENERATED_GBL_DATA_SIZE)
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+#define SPL_MALLOC_F_SIZE	CONFIG_SYS_MALLOC_F_LEN
+#else
+#define SPL_MALLOC_F_SIZE	0
+#endif
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_PAD_TO		65536
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_PAD_TO - 8)
+#define CONFIG_SPL_BSS_START_ADDR	(CONFIG_ISW_ENTRY_ADDR + \
+					CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE		(32 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	(32 * 1024)
+#define KEYSTONE_SPL_STACK_SIZE		(8 * 1024)
+#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC_START + \
+					CONFIG_SYS_SPL_MALLOC_SIZE + \
+					SPL_MALLOC_F_SIZE + \
+					KEYSTONE_SPL_STACK_SIZE - 4)
+
+/* SRAM scratch space entries  */
+#define SRAM_SCRATCH_SPACE_ADDR	CONFIG_SPL_STACK + 0x8
+
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START	(SRAM_SCRATCH_SPACE_ADDR)
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_END	(SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#define KEYSTONE_SRAM_SCRATCH_SPACE_END		(TI_SRAM_SCRATCH_BOARD_EEPROM_END)
+
+/* UART Configuration */
+#define CONFIG_SYS_NS16550_MEM32
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#endif
+#define CONFIG_SYS_NS16550_COM1		KS2_UART0_BASE
+#define CONFIG_SYS_NS16550_COM2		KS2_UART1_BASE
+
+#ifndef CONFIG_SOC_K2G
+#define CONFIG_SYS_NS16550_CLK		ks_clk_get_rate(KS2_CLK1_6)
+#else
+#define CONFIG_SYS_NS16550_CLK		ks_clk_get_rate(uart_pll_clk) / 2
+#endif
+
+/* SPI Configuration */
+#define CONFIG_SYS_SPI_CLK		ks_clk_get_rate(KS2_CLK1_6)
+#define CONFIG_SYS_SPI0
+#define CONFIG_SYS_SPI_BASE		KS2_SPI0_BASE
+#define CONFIG_SYS_SPI0_NUM_CS		4
+#define CONFIG_SYS_SPI1
+#define CONFIG_SYS_SPI1_BASE		KS2_SPI1_BASE
+#define CONFIG_SYS_SPI1_NUM_CS		4
+#define CONFIG_SYS_SPI2
+#define CONFIG_SYS_SPI2_BASE		KS2_SPI2_BASE
+#define CONFIG_SYS_SPI2_NUM_CS		4
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#endif
+
+/* Network Configuration */
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		32
+#define CONFIG_SYS_SGMII_REFCLK_MHZ	312
+#define CONFIG_SYS_SGMII_LINERATE_MHZ	1250
+#define CONFIG_SYS_SGMII_RATESCALE	2
+
+/* Keyston Navigator Configuration */
+#define CONFIG_TI_KSNAV
+#define CONFIG_KSNAV_QM_BASE_ADDRESS		KS2_QM_BASE_ADDRESS
+#define CONFIG_KSNAV_QM_CONF_BASE		KS2_QM_CONF_BASE
+#define CONFIG_KSNAV_QM_DESC_SETUP_BASE		KS2_QM_DESC_SETUP_BASE
+#define CONFIG_KSNAV_QM_STATUS_RAM_BASE		KS2_QM_STATUS_RAM_BASE
+#define CONFIG_KSNAV_QM_INTD_CONF_BASE		KS2_QM_INTD_CONF_BASE
+#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE		KS2_QM_PDSP1_CMD_BASE
+#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE		KS2_QM_PDSP1_CTRL_BASE
+#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE		KS2_QM_PDSP1_IRAM_BASE
+#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE	KS2_QM_MANAGER_QUEUES_BASE
+#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE	KS2_QM_MANAGER_Q_PROXY_BASE
+#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE	KS2_QM_QUEUE_STATUS_BASE
+#define CONFIG_KSNAV_QM_LINK_RAM_BASE		KS2_QM_LINK_RAM_BASE
+#define CONFIG_KSNAV_QM_REGION_NUM		KS2_QM_REGION_NUM
+#define CONFIG_KSNAV_QM_QPOOL_NUM		KS2_QM_QPOOL_NUM
+
+/* NETCP pktdma */
+#define CONFIG_KSNAV_PKTDMA_NETCP
+#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE	KS2_NETCP_PDMA_CTRL_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE		KS2_NETCP_PDMA_TX_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM	KS2_NETCP_PDMA_TX_CH_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE		KS2_NETCP_PDMA_RX_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM	KS2_NETCP_PDMA_RX_CH_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE	KS2_NETCP_PDMA_SCHED_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE	KS2_NETCP_PDMA_RX_FLOW_BASE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM	KS2_NETCP_PDMA_RX_FLOW_NUM
+#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE	KS2_NETCP_PDMA_RX_FREE_QUEUE
+#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE	KS2_NETCP_PDMA_RX_RCV_QUEUE
+#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE	KS2_NETCP_PDMA_TX_SND_QUEUE
+
+/* Keystone net */
+#define CONFIG_KSNET_MAC_ID_BASE		KS2_MAC_ID_BASE_ADDR
+#define CONFIG_KSNET_NETCP_BASE			KS2_NETCP_BASE
+#define CONFIG_KSNET_SERDES_SGMII_BASE		KS2_SGMII_SERDES_BASE
+#define CONFIG_KSNET_SERDES_SGMII2_BASE		KS2_SGMII_SERDES2_BASE
+#define CONFIG_KSNET_SERDES_LANES_PER_SGMII	KS2_LANES_PER_SGMII_SERDES
+
+#define CONFIG_AEMIF_CNTRL_BASE		KS2_AEMIF_CNTRL_BASE
+
+/* I2C Configuration */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED	100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE	0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED1	100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE1	0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED2	100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE2	0x10 /* SMBus host address */
+
+/* EEPROM definitions */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+
+/* NAND Configuration */
+#define CONFIG_KEYSTONE_RBL_NAND
+#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE	CONFIG_ENV_OFFSET
+#define CONFIG_SYS_NAND_MASK_CLE		0x4000
+#define CONFIG_SYS_NAND_MASK_ALE		0x2000
+#define CONFIG_SYS_NAND_CS			2
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST		{ 0x30000000, }
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_MAX_CHIPS		1
+#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+
+#define DFU_ALT_INFO_MMC \
+	"dfu_alt_info_mmc=" \
+	"MLO fat 0 1;" \
+	"u-boot.img fat 0 1;" \
+	"uEnv.txt fat 0 1\0"
+
+/* DFU settings */
+#define DFUARGS \
+	"dfu_bufsiz=0x10000\0" \
+	DFU_ALT_INFO_MMC \
+
+/* U-Boot general configuration */
+#define CONFIG_TIMESTAMP
+
+/* EDMA3 */
+#define CONFIG_TI_EDMA3
+
+#define KERNEL_MTD_PARTS						\
+	"mtdparts="							\
+	SPI_MTD_PARTS
+
+#define DEFAULT_FW_INITRAMFS_BOOT_ENV					\
+	"name_fw_rd=k2-fw-initrd.cpio.gz\0"				\
+	"set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0"		\
+	"init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; "	\
+		"run set_rd_spec\0"					\
+	"init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; "	\
+		"run set_rd_spec\0"					\
+	"init_fw_rd_ramfs=setenv rd_spec -\0"				\
+	"init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; "	\
+		"run set_rd_spec\0"					\
+
+#define DEFAULT_PMMC_BOOT_ENV						\
+	"set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \
+	"dev_pmmc=0\0"							\
+	"get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0"	\
+	"get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc}\0"	\
+	"get_pmmc_ramfs=run get_pmmc_net\0"				\
+	"get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} "		\
+			"${bootdir}/${name_pmmc}\0"			\
+	"get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0"	\
+	"run_pmmc=rproc init; rproc list; "				\
+		"rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; "	\
+		"rproc start ${dev_pmmc}\0"				\
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	DEFAULT_LINUX_BOOT_ENV						\
+	CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
+	DFUARGS								\
+	"bootdir=/boot\0" \
+	"tftp_root=/\0"							\
+	"nfs_root=/export\0"						\
+	"mem_lpae=1\0"							\
+	"addr_ubi=0x82000000\0"						\
+	"addr_secdb_key=0xc000000\0"					\
+	"name_kern=zImage\0"						\
+	"addr_mon=0x87000000\0"						\
+	"addr_non_sec_mon=0x0c097fc0\0"					\
+	"addr_load_sec_bm=0x0c09c000\0"					\
+	"run_mon=mon_install ${addr_mon}\0"				\
+	"run_mon_hs=mon_install ${addr_non_sec_mon} "			\
+			"${addr_load_sec_bm}\0"				\
+	"run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0"		\
+	"init_net=run args_all args_net\0"				\
+	"init_nfs=setenv autoload no; dhcp; run args_all args_net\0"	\
+	"init_ubi=run args_all args_ubi; "				\
+		"ubi part ubifs; ubifsmount ubi:rootfs;\0"			\
+	"get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0"	\
+	"get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}\0"	\
+	"get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0"		\
+	"get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0"	\
+	"get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}\0"	\
+	"get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0"		\
+	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
+	"get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0"	\
+	"get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0"	\
+	"get_fit_net=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0"	\
+	"get_fit_nfs=nfs ${addr_fit} ${nfs_root}/boot/${name_fit}\0"	\
+	"get_fit_ubi=ubifsload ${addr_fit} ${bootdir}/${name_fit}\0"	\
+	"get_fit_mmc=load mmc ${bootpart} ${addr_fit} ${bootdir}/${name_fit}\0" \
+	"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0"	\
+	"get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \
+	"burn_uboot_spi=sf probe; sf erase 0 0x100000; "		\
+		"sf write ${loadaddr} 0 ${filesize}\0"		\
+	"burn_uboot_nand=nand erase 0 0x100000; "			\
+		"nand write ${loadaddr} 0 ${filesize}\0"		\
+	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 "	\
+		KERNEL_MTD_PARTS					\
+	"args_net=setenv bootargs ${bootargs} rootfstype=nfs "		\
+		"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},"	\
+		"${nfs_options} ip=dhcp\0"				\
+	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0"			\
+	"get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0"	\
+	"get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0"	\
+	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
+	"get_fit_ramfs=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0"	\
+	"get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0"	\
+	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0"	\
+	"get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0"	\
+	"burn_ubi=nand erase.part ubifs; "				\
+		"nand write ${addr_ubi} ubifs ${filesize}\0"		\
+	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0"		\
+	"args_ramfs=setenv bootargs ${bootargs} "			\
+		"rdinit=/sbin/init rw root=/dev/ram0 "			\
+		"initrd=0x808080000,80M\0"				\
+	"no_post=1\0"							\
+	"mtdparts=mtdparts=davinci_nand.0:"				\
+		"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
+
+#ifndef CONFIG_BOOTCOMMAND
+#ifndef CONFIG_TI_SECURE_DEVICE
+#define CONFIG_BOOTCOMMAND						\
+	"run init_${boot}; "						\
+	"run get_mon_${boot} run_mon; "					\
+	"run get_kern_${boot}; "					\
+	"run init_fw_rd_${boot}; "					\
+	"run get_fdt_${boot}; "						\
+	"run run_kern"
+#else
+#define CONFIG_BOOTCOMMAND						\
+	"run run_mon_hs; "						\
+	"run init_${boot}; "						\
+	"run get_fit_${boot}; "						\
+	"bootm ${addr_fit}#${name_fdt}"
+#endif
+#endif
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+/* we may include files below only after all above definitions */
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#ifndef CONFIG_SOC_K2G
+#define CONFIG_SYS_HZ_CLOCK		ks_clk_get_rate(KS2_CLK1_6)
+#else
+#define CONFIG_SYS_HZ_CLOCK		get_external_clk(sys_clk)
+#endif
+
+#endif /* __CONFIG_KS2_EVM_H */
diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h
new file mode 100644
index 0000000..98b5839
--- /dev/null
+++ b/include/configs/ti_armv7_omap.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ti_armv7_omap.h
+ *
+ * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * The various ARMv7 SoCs from TI all share a number of IP blocks when
+ * implementing a given feature. This is meant to isolate the features
+ * that are based on OMAP architecture.
+ */
+#ifndef __CONFIG_TI_ARMV7_OMAP_H__
+#define __CONFIG_TI_ARMV7_OMAP_H__
+
+/*
+ * GPMC NAND block.  We support 1 device and the physical address to
+ * access CS0 at is 0x8000000.
+ */
+#ifdef CONFIG_NAND
+#ifndef CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE		0x8000000
+#endif
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#endif
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_TI_ARMV7_OMAP_H__ */
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
new file mode 100644
index 0000000..5d9c8ef
--- /dev/null
+++ b/include/configs/ti_omap3_common.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ti_omap3_common.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * For more details, please see the technical documents listed at
+ *   http://www.ti.com/product/omap3530
+ *   http://www.ti.com/product/omap3630
+ *   http://www.ti.com/product/dm3730
+ */
+
+#ifndef __CONFIG_TI_OMAP3_COMMON_H__
+#define __CONFIG_TI_OMAP3_COMMON_H__
+
+/*
+ * High Level Configuration Options
+ */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+/* NS16550 Configuration */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#if !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#endif /* !CONFIG_DM_SERIAL */
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+					115200}
+
+/* Select serial console configuration */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
+#define CONFIG_SYS_NS16550_COM2		OMAP34XX_UART2
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#endif
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+/* SPL */
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (64 << 20))
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE		0x30000000
+#endif
+
+/* Now bring in the rest of the common code. */
+#include <configs/ti_armv7_omap.h>
+
+#endif	/* __CONFIG_TI_OMAP3_COMMON_H__ */
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
new file mode 100644
index 0000000..1e31622
--- /dev/null
+++ b/include/configs/ti_omap4_common.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * TI OMAP4 common configuration settings
+ */
+
+#ifndef __CONFIG_TI_OMAP4_COMMON_H
+#define __CONFIG_TI_OMAP4_COMMON_H
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310		1
+#define CONFIG_SYS_PL310_BASE	0x48242000
+#endif
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
+
+/*
+ * For the DDR timing information we can either dynamically determine
+ * the timings to use or use pre-determined timings (based on using the
+ * dynamic method.  Default to the static timing infomation.
+ */
+#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+#include <configs/ti_armv7_omap.h>
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_NS16550_CLK		48000000
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+#endif
+
+/* TWL6030 */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_TWL6030_POWER		1
+#endif
+
+/* USB */
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+
+/*
+ * Environment setup
+ */
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"setenv mmcdev " #instance"; "\
+	"setenv bootpart " #instance":2 ; "\
+	"run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(LEGACY_MMC, legacy_mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(LEGACY_MMC, legacy_mmc, 1) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	DEFAULT_MMC_TI_ARGS \
+	DEFAULT_FIT_TI_ARGS \
+	"console=ttyO2,115200n8\0" \
+	"fdtfile=undefined\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
+	"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"uimageboot=echo Booting from mmc${mmcdev} ...; " \
+		"run args_mmc; " \
+		"bootm ${loadaddr}\0" \
+	"findfdt="\
+		"if test $board_name = sdp4430; then " \
+			"setenv fdtfile omap4-sdp.dtb; fi; " \
+		"if test $board_name = panda; then " \
+			"setenv fdtfile omap4-panda.dtb; fi;" \
+		"if test $board_name = panda-a4; then " \
+			"setenv fdtfile omap4-panda-a4.dtb; fi;" \
+		"if test $board_name = panda-es; then " \
+			"setenv fdtfile omap4-panda-es.dtb; fi;" \
+		"if test $board_name = duovero; then " \
+			"setenv fdtfile omap4-duovero-parlor.dtb; fi;" \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	BOOTENV
+
+/*
+ * Defines for SPL
+ * It is known that this will break HS devices. Since the current size of
+ * SPL is overlapped with public stack and breaking non HS devices to boot.
+ * So moving TEXT_BASE down to non-HS limit.
+ */
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (128 << 20))
+
+#ifdef CONFIG_SPL_BUILD
+/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */
+#undef CONFIG_SYS_I2C
+#endif
+
+#endif /* __CONFIG_TI_OMAP4_COMMON_H */
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
new file mode 100644
index 0000000..de0a6af
--- /dev/null
+++ b/include/configs/ti_omap5_common.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Sricharan R	  <r.sricharan@ti.com>
+ *
+ * Derived from OMAP4 done by:
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * TI OMAP5 AND DRA7XX common configuration settings
+ *
+ * For more details, please see the technical documents listed at
+ * http://www.ti.com/product/omap5432
+ */
+
+#ifndef __CONFIG_TI_OMAP5_COMMON_H
+#define __CONFIG_TI_OMAP5_COMMON_H
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
+
+/*
+ * For the DDR timing information we can either dynamically determine
+ * the timings to use or use pre-determined timings (based on using the
+ * dynamic method.  Default to the static timing infomation.
+ */
+#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+#define CONFIG_PALMAS_POWER
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+#include <configs/ti_armv7_omap.h>
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_NS16550_CLK		48000000
+#if !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#endif
+
+/*
+ * Environment setup
+ */
+
+#ifndef DFUARGS
+#define DFUARGS
+#endif
+
+#include <environment/ti/boot.h>
+#include <environment/ti/mmc.h>
+#include <environment/ti/nand.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	DEFAULT_MMC_TI_ARGS \
+	DEFAULT_FIT_TI_ARGS \
+	DEFAULT_COMMON_BOOT_TI_ARGS \
+	DEFAULT_FDT_TI_ARGS \
+	DFUARGS \
+	NETARGS \
+	NANDARGS \
+
+/*
+ * SPL related defines.  The Public RAM memory map the ROM defines the
+ * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
+ * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
+ * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
+ * print some information.
+ */
+#ifdef CONFIG_TI_SECURE_DEVICE
+/*
+ * For memory booting on HS parts, the first 4KB of the internal RAM is
+ * reserved for secure world use and the flash loader image is
+ * preceded by a secure certificate. The SPL will therefore run in internal
+ * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
+ */
+#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ	0x1000
+/* If no specific start address is specified then the secure EMIF
+ * region will be placed at the end of the DDR space. In order to prevent
+ * the main u-boot relocation from clobbering that memory and causing a
+ * firewall violation, we tell u-boot that memory is protected RAM (PRAM)
+ */
+#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0)
+#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10
+#endif
+#else
+/*
+ * For all booting on GP parts, the flash loader image is
+ * downloaded into internal RAM at address 0x40300000.
+ */
+#endif
+
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (128 << 20))
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_TIMER
+#endif
+
+#endif /* __CONFIG_TI_OMAP5_COMMON_H */
diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h
new file mode 100644
index 0000000..5adae68
--- /dev/null
+++ b/include/configs/tinker_rk3288.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3288_common.h>
+
+#undef BOOT_TARGET_DEVICES
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dchp, na)
+
+#define CONFIG_SYS_MMC_ENV_DEV 1
+
+#endif
diff --git a/include/configs/titanium.h b/include/configs/titanium.h
new file mode 100644
index 0000000..c24d657
--- /dev/null
+++ b/include/configs/titanium.h
@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * Configuration settings for the ProjectionDesign / Barco
+ * Titanium board.
+ *
+ * Based on mx6qsabrelite.h which is:
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MX6Q
+
+/* Provide the MACH_TYPE value that the vendor kernel requires. */
+#define CONFIG_MACH_TYPE		3769
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		4
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (500 << 20))
+
+#define CONFIG_HOSTNAME			"titanium"
+#define CONFIG_UBI_PART			ubi
+#define CONFIG_UBIFS_VOLUME		rootfs0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel=" CONFIG_HOSTNAME "/uImage\0"		\
+	"kernel_fs=/boot/uImage\0"					\
+	"kernel_addr=11000000\0"					\
+	"dtb=" CONFIG_HOSTNAME "/"				\
+		CONFIG_HOSTNAME ".dtb\0"			\
+	"dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0"		\
+	"dtb_addr=12800000\0"						\
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"console=ttymxc0\0" \
+	"baudrate=115200\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"initrd_high=0xffffffff\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"uimage=uImage\0" \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
+		" ${script}\0" \
+	"bootscript=echo Running bootscript from mmc ...; source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot} rootwait rw\0" \
+	"bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
+		" ${uimage}; bootm\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcon=setenv bootargs ${bootargs} console=ttymxc0,"		\
+		"${baudrate}\0"						\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ubifs=" CONFIG_HOSTNAME "/ubifs.img\0"		\
+	"part=" __stringify(CONFIG_UBI_PART) "\0"			\
+	"boot_vol=0\0"							\
+	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"			\
+	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
+	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
+		" ${filesize}\0"					\
+	"upd_ubifs=run load_ubifs update_ubifs\0"			\
+	"init_ubi=nand erase.part ubi;ubi part ${part};"		\
+		"ubi create ${vol} c800000\0"				\
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
+	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"		\
+		" addcon addmtd;"					\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"ubifsargs=set bootargs ubi.mtd=ubi "				\
+		"root=ubi:rootfs${boot_vol} rootfstype=ubifs\0"		\
+	"ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0"	\
+	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"		\
+		"ubifsload ${dtb_addr} ${dtb_fs};\0"			\
+	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon "	\
+		"addmtd;bootm ${kernel_addr} - ${dtb_addr}\0"		\
+	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
+	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
+	"net_nfs=run load_dtb load_kernel; "				\
+		"run nfsargs addip addcon addmtd;"			\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"delenv=env default -a -f; saveenv; reset\0"
+
+#define CONFIG_BOOTCOMMAND		"run nand_ubifs"
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			(512 << 20)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Enable NAND support */
+#ifdef CONFIG_CMD_NAND
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+
+/* Environment in NAND */
+#define CONFIG_ENV_OFFSET		(16 << 20)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + (512 << 10))
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#else /* CONFIG_CMD_NAND */
+
+/* Environment in MMC */
+#define CONFIG_ENV_SIZE			(8 << 10)
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#endif /* CONFIG_CMD_NAND */
+
+/* UBI/UBIFS config options */
+
+#endif			       /* __CONFIG_H */
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
new file mode 100644
index 0000000..b98656d
--- /dev/null
+++ b/include/configs/topic_miami.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 Topic Embedded Products
+ *
+ * Configuration for Zynq Evaluation and Development Board - Miami
+ * See zynq-common.h for Zynq common configs
+ */
+
+#ifndef __CONFIG_TOPIC_MIAMI_H
+#define __CONFIG_TOPIC_MIAMI_H
+
+
+/* Speed up boot time by ignoring the environment which we never used */
+
+#include "zynq-common.h"
+
+/* Fixup settings */
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE			0x8000
+#undef CONFIG_ENV_OFFSET
+#define CONFIG_ENV_OFFSET		0x80000
+
+/* SPL settings */
+#undef CONFIG_SPL_ETH_SUPPORT
+#undef CONFIG_SPL_MAX_FOOTPRINT
+#define CONFIG_SPL_MAX_FOOTPRINT	CONFIG_SYS_SPI_U_BOOT_OFFS
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot.img"
+
+/* sspi command isn't useful */
+#undef CONFIG_CMD_SPI
+
+/* No useful gpio */
+#undef CONFIG_ZYNQ_GPIO
+#undef CONFIG_CMD_GPIO
+
+/* No falcon support */
+#undef CONFIG_SPL_OS_BOOT
+#undef CONFIG_SPL_FPGA_SUPPORT
+
+/* FPGA commands that we don't use */
+
+/* Extras */
+#undef CONFIG_SYS_MEMTEST_START
+#define CONFIG_SYS_MEMTEST_START	0
+#undef CONFIG_SYS_MEMTEST_END
+#define CONFIG_SYS_MEMTEST_END	0x18000000
+
+/* Faster flash, ours may run at 108 MHz */
+#undef CONFIG_SPI_FLASH_WINBOND
+
+/* Setup proper boot sequences for Miami boards */
+
+#if defined(CONFIG_USB)
+# define EXTRA_ENV_USB \
+	"usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\
+		"i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
+	"usbboot=run usbreset && if usb start; then " \
+		"echo Booting from USB... && " \
+		"if load usb 0 0x1900000 ${bootscript}; then "\
+		"source 0x1900000; fi; " \
+		"load usb 0 ${kernel_addr} ${kernel_image} && " \
+		"load usb 0 ${devicetree_addr} ${devicetree_image} && " \
+		"load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \
+		"bootm ${kernel_addr} ${ramdisk_load_address} "\
+			"${devicetree_addr}; " \
+	"fi\0"
+  /* Note that addresses here should match the addresses in the env */
+# undef DFU_ALT_INFO
+# define DFU_ALT_INFO \
+	"dfu_alt_info=" \
+	"uImage ram 0x2080000 0x500000;" \
+	"devicetree.dtb ram 0x2000000 0x20000;" \
+	"uramdisk.image.gz ram 0x4000000 0x10000000\0" \
+	"dfu_ram=run usbreset && dfu 0 ram 0\0" \
+	"thor_ram=run usbreset && thordown 0 ram 0\0"
+#else
+# define EXTRA_ENV_USB
+#endif
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"kernel_image=uImage\0"	\
+	"kernel_addr=0x2080000\0" \
+	"ramdisk_image=uramdisk.image.gz\0"	\
+	"ramdisk_load_address=0x4000000\0"	\
+	"devicetree_image=devicetree.dtb\0"	\
+	"devicetree_addr=0x2000000\0"	\
+	"bitstream_image=fpga.bin\0"	\
+	"bootscript=autorun.scr\0" \
+	"loadbit_addr=0x100000\0"	\
+	"loadbootenv_addr=0x2000000\0" \
+	"kernel_size=0x440000\0"	\
+	"devicetree_size=0x10000\0"	\
+	"boot_size=0xF00000\0"	\
+	"fdt_high=0x20000000\0"	\
+	"initrd_high=0x20000000\0"	\
+	"mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \
+		"mmcinfo && " \
+		"load mmc 0 ${loadbit_addr} ${bitstream_image} && " \
+		"fpga load 0 ${loadbit_addr} ${filesize}\0" \
+	"qspiboot=echo Booting from QSPI flash... && " \
+		"sf probe && " \
+		"sf read ${devicetree_addr} 0xA0000 ${devicetree_size} && " \
+		"sf read ${kernel_addr} 0xC0000 ${kernel_size} && " \
+		"bootm ${kernel_addr} - ${devicetree_addr}\0" \
+	"sdboot=if mmcinfo; then " \
+			"setenv bootargs console=ttyPS0,115200 " \
+				"root=/dev/mmcblk0p2 rw rootfstype=ext4 " \
+				"rootwait quiet ; " \
+			"load mmc 0 ${kernel_addr} ${kernel_image}&& " \
+			"load mmc 0 ${devicetree_addr} ${devicetree_image}&& " \
+			"bootm ${kernel_addr} - ${devicetree_addr}; " \
+		"fi\0" \
+	EXTRA_ENV_USB \
+	DFU_ALT_INFO
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND	"if mmcinfo; then " \
+	"if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; " \
+	"fi; fi; run $modeboot"
+#undef CONFIG_DISPLAY_BOARDINFO
+
+#endif /* __CONFIG_TOPIC_MIAMI_H */
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
new file mode 100644
index 0000000..4367158
--- /dev/null
+++ b/include/configs/tplink_wdr4300.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_MHZ			280
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN		0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN	0x20000
+
+#define CONFIG_SYS_SDRAM_BASE		0xa0000000
+#define CONFIG_SYS_LOAD_ADDR		0xa1000000
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_CLK		40000000
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTCOMMAND		\
+	"dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr"
+
+#define CONFIG_ENV_SIZE			0x10000
+
+/*
+ * Command
+ */
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+
+/* USB, USB storage, USB ethernet */
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_IS_TDI
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x83f00000
+
+#define CONFIG_CMD_MII
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
new file mode 100644
index 0000000..13e3d60
--- /dev/null
+++ b/include/configs/tqma6.h
@@ -0,0 +1,341 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013, 2014, 2017 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * Configuration settings for the TQ Systems TQMa6<Q,D,DL,S> module.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/kconfig.h>
+/* SPL */
+/* #if defined(CONFIG_SPL_BUILD) */
+/* common IMX6 SPL configuration */
+#include "imx6_spl.h"
+
+/* #endif */
+
+/* place code in last 4 MiB of RAM */
+
+#include "mx6_common.h"
+
+#if defined(CONFIG_TQMA6S)
+#define PHYS_SDRAM_SIZE			(512u * SZ_1M)
+#elif defined(CONFIG_TQMA6DL)
+#define PHYS_SDRAM_SIZE			(SZ_1G)
+#elif defined(CONFIG_TQMA6Q)
+#define PHYS_SDRAM_SIZE			(SZ_1G)
+#endif
+
+#define CONFIG_MXC_UART
+
+/* SPI Flash */
+
+#define TQMA6_SPI_FLASH_SECTOR_SIZE	SZ_64K
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* I2C EEPROM (M24C64) */
+#define CONFIG_SYS_I2C_EEPROM_ADDR			0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN			2
+#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS		5 /* 32 Bytes */
+#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+#define TQMA6_PFUZE100_I2C_BUS		2
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+
+#define CONFIG_ARP_TIMEOUT		200UL
+
+#define CONFIG_ENV_SIZE			(SZ_8K)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * SZ_1M)
+
+#if defined(CONFIG_TQMA6X_MMC_BOOT)
+
+#define TQMA6_UBOOT_OFFSET		SZ_1K
+#define TQMA6_UBOOT_SECTOR_START	0x2
+#define TQMA6_UBOOT_SECTOR_COUNT	0x7fe
+
+#define CONFIG_ENV_OFFSET		SZ_1M
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define TQMA6_FDT_OFFSET		(2 * SZ_1M)
+#define TQMA6_FDT_SECTOR_START		0x1000
+#define TQMA6_FDT_SECTOR_COUNT		0x800
+
+#define TQMA6_KERNEL_SECTOR_START	0x2000
+#define TQMA6_KERNEL_SECTOR_COUNT	0x2000
+
+#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS                                       \
+	"uboot_start="__stringify(TQMA6_UBOOT_SECTOR_START)"\0"                \
+	"uboot_size="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0"                 \
+	"fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0"                    \
+	"fdt_size="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0"                     \
+	"kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0"              \
+	"kernel_size="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0"               \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0"                       \
+	"loadimage=mmc dev ${mmcdev}; "                                        \
+		"mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0"       \
+	"loadfdt=mmc dev ${mmcdev}; "                                          \
+		"mmc read ${fdt_addr} ${fdt_start} ${fdt_size};\0"             \
+	"update_uboot=if tftp ${uboot}; then "                                 \
+		"if itest ${filesize} > 0; then "                              \
+			"mmc dev ${mmcdev}; mmc rescan; "                      \
+			"setexpr blkc ${filesize} + 0x1ff; "                   \
+			"setexpr blkc ${blkc} / 0x200; "                       \
+			"if itest ${blkc} <= ${uboot_size}; then "             \
+				"mmc write ${loadaddr} ${uboot_start} "        \
+					"${blkc}; "                            \
+			"fi; "                                                 \
+		"fi; fi; "                                                     \
+		"setenv filesize; setenv blkc \0"                              \
+	"update_kernel=run kernel_name; "                                      \
+		"if tftp ${kernel}; then "                                     \
+			"if itest ${filesize} > 0; then "                      \
+				"mmc dev ${mmcdev}; mmc rescan; "              \
+				"setexpr blkc ${filesize} + 0x1ff; "           \
+				"setexpr blkc ${blkc} / 0x200; "               \
+				"if itest ${blkc} <= ${kernel_size}; then "    \
+					"mmc write ${loadaddr} "               \
+						"${kernel_start} ${blkc}; "    \
+				"fi; "                                         \
+			"fi; "                                                 \
+		"fi; "                                                         \
+		"setenv filesize; setenv blkc \0"                              \
+	"update_fdt=if tftp ${fdt_file}; then "                                \
+		"if itest ${filesize} > 0; then "                              \
+			"mmc dev ${mmcdev}; mmc rescan; "                      \
+			"setexpr blkc ${filesize} + 0x1ff; "                   \
+			"setexpr blkc ${blkc} / 0x200; "                       \
+			"if itest ${blkc} <= ${fdt_size}; then "               \
+				"mmc write ${loadaddr} ${fdt_start} ${blkc}; " \
+			"fi; "                                                 \
+		"fi; fi; "                                                     \
+		"setenv filesize; setenv blkc \0"                              \
+
+#define CONFIG_BOOTCOMMAND \
+	"run mmcboot; run netboot; run panicboot"
+
+#elif defined(CONFIG_TQMA6X_SPI_BOOT)
+
+#define TQMA6_UBOOT_OFFSET		0x400
+#define TQMA6_UBOOT_SECTOR_START	0x0
+/* max u-boot size: 512k */
+#define TQMA6_UBOOT_SECTOR_SIZE		TQMA6_SPI_FLASH_SECTOR_SIZE
+#define TQMA6_UBOOT_SECTOR_COUNT	0x8
+#define TQMA6_UBOOT_SIZE		(TQMA6_UBOOT_SECTOR_SIZE * \
+					 TQMA6_UBOOT_SECTOR_COUNT)
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_OFFSET		(TQMA6_UBOOT_SIZE)
+#define CONFIG_ENV_SECT_SIZE		TQMA6_SPI_FLASH_SECTOR_SIZE
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					 CONFIG_ENV_SECT_SIZE)
+
+#define TQMA6_FDT_OFFSET		(CONFIG_ENV_OFFSET_REDUND + \
+					 CONFIG_ENV_SECT_SIZE)
+#define TQMA6_FDT_SECT_SIZE		(TQMA6_SPI_FLASH_SECTOR_SIZE)
+
+#define TQMA6_FDT_SECTOR_START		0x0a /* 8 Sector u-boot, 2 Sector env */
+#define TQMA6_FDT_SECTOR_COUNT		0x01
+
+#define TQMA6_KERNEL_SECTOR_START	0x10
+#define TQMA6_KERNEL_SECTOR_COUNT	0x60
+
+#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS                                       \
+	"mmcblkdev=0\0"                                                        \
+	"uboot_offset="__stringify(TQMA6_UBOOT_OFFSET)"\0"                     \
+	"uboot_sectors="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0"              \
+	"fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0"                    \
+	"fdt_sectors="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0"                  \
+	"kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0"              \
+	"kernel_sectors="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0"            \
+	"update_uboot=if tftp ${uboot}; then "                                 \
+		"if itest ${filesize} > 0; then "                              \
+			"setexpr blkc ${filesize} + "                          \
+				__stringify(TQMA6_UBOOT_OFFSET) "; "           \
+			"setexpr size ${uboot_sectors} * "                     \
+				__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "   \
+			"if itest ${blkc} <= ${size}; then "                   \
+				"sf probe; "                                   \
+				"sf erase 0 ${size}; "                         \
+				"sf write ${loadaddr} ${uboot_offset} "        \
+					"${filesize}; "                        \
+			"fi; "                                                 \
+		"fi; fi; "                                                     \
+		"setenv filesize 0; setenv blkc; setenv size \0"               \
+	"update_kernel=run kernel_name; if tftp ${kernel}; then "              \
+		"if itest ${filesize} > 0; then "                              \
+			"setexpr size ${kernel_sectors} * "                    \
+				__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "   \
+			"setexpr offset ${kernel_start} * "                    \
+				__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "   \
+			"if itest ${filesize} <= ${size}; then "               \
+				"sf probe; "                                   \
+				"sf erase ${offset} ${size}; "                 \
+				"sf write ${loadaddr} ${offset} "              \
+					"${filesize}; "                        \
+			"fi; "                                                 \
+		"fi; fi; "                                                     \
+		"setenv filesize 0; setenv size ; setenv offset\0"             \
+	"update_fdt=if tftp ${fdt_file}; then "                                \
+		"if itest ${filesize} > 0; then "                              \
+			"setexpr size ${fdt_sectors} * "                       \
+				__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "   \
+			"setexpr offset ${fdt_start} * "                       \
+				__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "   \
+			"if itest ${filesize} <= ${size}; then "               \
+				"sf probe; "                                   \
+				"sf erase ${offset} ${size}; "                 \
+				"sf write ${loadaddr} ${offset} "              \
+					"${filesize}; "                        \
+			"fi; "                                                 \
+		"fi; fi; "                                                     \
+		"setenv filesize 0; setenv size ; setenv offset\0"             \
+	"loadimage=sf probe; "                                                 \
+		"setexpr size ${kernel_sectors} * "                            \
+			__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "           \
+		"setexpr offset ${kernel_start} * "                            \
+			__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "           \
+		"sf read ${loadaddr} ${offset} ${size}; "                      \
+		"setenv size ; setenv offset\0"                                \
+	"loadfdt=sf probe; "                                                   \
+		"setexpr size ${fdt_sectors} * "                               \
+			__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "           \
+		"setexpr offset ${fdt_start} * "                               \
+			__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; "           \
+		"sf read ${fdt_addr} ${offset} ${size}; "                      \
+		"setenv size ; setenv offset\0"                                \
+
+#define CONFIG_BOOTCOMMAND                                                     \
+	"sf probe; run mmcboot; run netboot; run panicboot"                    \
+
+#else
+
+#error "need to define boot source"
+
+#endif
+
+/* 128 MiB offset as in ARM related docu for linux suggested */
+#define TQMA6_FDT_ADDRESS		0x18000000
+
+/* set to a resonable value, changeable by user */
+#define TQMA6_CMA_SIZE                 160M
+
+#define CONFIG_EXTRA_ENV_SETTINGS                                              \
+	"board=tqma6\0"                                                        \
+	"uimage=uImage\0"                                                      \
+	"zimage=zImage\0"                                                      \
+	"boot_type=bootz\0"                                                    \
+	"kernel_name=if test \"${boot_type}\" != bootz; then "                 \
+		"setenv kernel ${uimage}; "                                    \
+		"else setenv kernel ${zimage}; fi\0"                           \
+	"uboot=u-boot.imx\0"                                                   \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0"                               \
+	"fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0"                          \
+	"console=" CONSOLE_DEV "\0"                                            \
+	"cma_size="__stringify(TQMA6_CMA_SIZE)"\0"                             \
+	"fdt_high=0xffffffff\0"                                                \
+	"initrd_high=0xffffffff\0"                                             \
+	"rootfsmode=ro\0"                                                      \
+	"addcma=setenv bootargs ${bootargs} cma=${cma_size}\0"                 \
+	"addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0"  \
+	"addfb=setenv bootargs ${bootargs} "                                   \
+		"imx-fbdev.legacyfb_depth=32 consoleblank=0\0"                 \
+	"mmcpart=2\0"                                                          \
+	"mmcblkdev=0\0"                                                        \
+	"mmcargs=run addmmc addtty addfb addcma\0"                             \
+	"addmmc=setenv bootargs ${bootargs} "                                  \
+		"root=/dev/mmcblk${mmcblkdev}p${mmcpart} ${rootfsmode} "       \
+		"rootwait\0"                                                   \
+	"mmcboot=echo Booting from mmc ...; "                                  \
+		"setenv bootargs; "                                            \
+		"run mmcargs; "                                                \
+		"run loadimage; "                                              \
+		"if run loadfdt; then "                                        \
+			"echo boot device tree kernel ...; "                   \
+			"${boot_type} ${loadaddr} - ${fdt_addr}; "             \
+		"else "                                                        \
+			"${boot_type}; "                                       \
+		"fi;\0"                                                        \
+		"setenv bootargs \0"                                           \
+	"netdev=eth0\0"                                                        \
+	"rootpath=/srv/nfs/tqma6\0"                                            \
+	"ipmode=static\0"                                                      \
+	"netargs=run addnfs addip addtty addfb addcma\0"                       \
+	"addnfs=setenv bootargs ${bootargs} "                                  \
+		"root=/dev/nfs rw "                                            \
+		"nfsroot=${serverip}:${rootpath},v3,tcp;\0"                    \
+	"addip_static=setenv bootargs ${bootargs} "                            \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:"            \
+		"${hostname}:${netdev}:off\0"                                  \
+	"addip_dynamic=setenv bootargs ${bootargs} ip=dhcp\0"                  \
+	"addip=if test \"${ipmode}\" != static; then "                         \
+		"run addip_dynamic; else run addip_static; fi\0"               \
+	"set_getcmd=if test \"${ipmode}\" != static; then "                    \
+		"setenv getcmd dhcp; setenv autoload yes; "                    \
+		"else setenv getcmd tftp; setenv autoload no; fi\0"            \
+	"netboot=echo Booting from net ...; "                                  \
+		"run kernel_name; "                                            \
+		"run set_getcmd; "                                             \
+		"setenv bootargs; "                                            \
+		"run netargs; "                                                \
+		"if ${getcmd} ${kernel}; then "                                \
+			"if ${getcmd} ${fdt_addr} ${fdt_file}; then "          \
+				"${boot_type} ${loadaddr} - ${fdt_addr}; "     \
+			"fi; "                                                 \
+		"fi; "                                                         \
+		"echo ... failed\0"                                            \
+	"panicboot=echo No boot device !!! reset\0"                            \
+	TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS                                      \
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * All the defines above are for the TQMa6 SoM
+ *
+ * Now include the baseboard specific configuration
+ */
+#ifdef CONFIG_MBA6
+#include "tqma6_mba6.h"
+#elif CONFIG_WRU4
+#include "tqma6_wru4.h"
+#else
+#error "No baseboard for the TQMa6 defined!"
+#endif
+
+/* Support at least the sensor on TQMa6 SOM */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h
new file mode 100644
index 0000000..bee6d2f
--- /dev/null
+++ b/include/configs/tqma6_mba6.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 - 2017 Markus Niebel <Markus.Niebel@tq-group.com>
+ *
+ * Configuration settings for the TQ Systems TQMa6<Q,D,DL,S> module on
+ * MBa6 starter kit
+ */
+
+#ifndef __CONFIG_TQMA6_MBA6_H
+#define __CONFIG_TQMA6_MBA6_H
+
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+
+#define CONFIG_FEC_MXC_PHYADDR		0x03
+
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+#define CONSOLE_DEV		"ttymxc1"
+
+#endif /* __CONFIG_TQMA6_MBA6_H */
diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h
new file mode 100644
index 0000000..0af52e5
--- /dev/null
+++ b/include/configs/tqma6_wru4.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef __CONFIG_TQMA6_WRU4_H
+#define __CONFIG_TQMA6_WRU4_H
+
+/* Ethernet */
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0x01
+#define CONFIG_PHY_SMSC
+
+/* UART */
+#define CONFIG_MXC_UART_BASE		UART4_BASE
+#define CONSOLE_DEV		"ttymxc3"
+
+/* Watchdog */
+
+/* Config on-board RTC */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_RTC_BUS_NUM		2
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+/* Turn off RTC square-wave output to save battery */
+#define CONFIG_RTC_DS1337_NOOSC
+
+/* LED */
+
+/* Bootcounter */
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+#endif /* __CONFIG_TQMA6_WRU4_H */
diff --git a/include/configs/trats.h b/include/configs/trats.h
new file mode 100644
index 0000000..af8e8ce
--- /dev/null
+++ b/include/configs/trats.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
+ */
+
+#ifndef __CONFIG_TRATS_H
+#define __CONFIG_TRATS_H
+
+#include <configs/exynos4-common.h>
+
+#define CONFIG_TRATS
+
+#define CONFIG_TIZEN			/* TIZEN lib */
+
+#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	0x10502000
+#endif
+
+/* TRATS has 4 banks of DRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+/* select serial console configuration */
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS
+
+#define CONFIG_BOOTCOMMAND		"run autoboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+#define CONFIG_BOOTBLOCK		"10"
+#define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"
+
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/* Tizen - partitions definitions */
+#define PARTS_CSA		"csa-mmc"
+#define PARTS_BOOT		"boot"
+#define PARTS_QBOOT		"qboot"
+#define PARTS_CSC		"csc"
+#define PARTS_ROOT		"platform"
+#define PARTS_DATA		"data"
+#define PARTS_UMS		"ums"
+
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
+	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
+
+#define CONFIG_DFU_ALT \
+	"u-boot raw 0x80 0x400;" \
+	"/uImage ext4 0 2;" \
+	"/modem.bin ext4 0 2;" \
+	"/exynos4210-trats.dtb ext4 0 2;" \
+	""PARTS_CSA" part 0 1;" \
+	""PARTS_BOOT" part 0 2;" \
+	""PARTS_QBOOT" part 0 3;" \
+	""PARTS_CSC" part 0 4;" \
+	""PARTS_ROOT" part 0 5;" \
+	""PARTS_DATA" part 0 6;" \
+	""PARTS_UMS" part 0 7;" \
+	"params.bin raw 0x38 0x8;" \
+	"/Image.itb ext4 0 2\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootk=" \
+		"run loaduimage;" \
+		"if run loaddtb; then " \
+			"bootm 0x40007FC0 - ${fdtaddr};" \
+		"fi;" \
+		"bootm 0x40007FC0;\0" \
+	"updatebackup=" \
+		"mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
+		"mmc dev 0 0\0" \
+	"updatebootb=" \
+		"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
+	"lpj=lpj=3981312\0" \
+	"nfsboot=" \
+		"setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=${nfsroot},nolock,tcp " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+		"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
+		"; run bootk\0" \
+	"ramfsboot=" \
+		"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
+		"${console} ${meminfo} " \
+		"initrd=0x43000000,8M ramdisk=8192\0" \
+	"mmcboot=" \
+		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
+		"run bootk\0" \
+	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
+	"verify=n\0" \
+	"rootfstype=ext4\0" \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+	"meminfo=crashkernel=32M@0x50000000\0" \
+	"nfsroot=/nfsroot/arm\0" \
+	"bootblock=" CONFIG_BOOTBLOCK "\0" \
+	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
+	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
+		"${fdtfile}\0" \
+	"mmcdev=0\0" \
+	"mmcbootpart=2\0" \
+	"mmcrootpart=5\0" \
+	"opts=always_resume=1\0" \
+	"partitions=" PARTS_DEFAULT \
+	"dfu_alt_info=" CONFIG_DFU_ALT \
+	"spladdr=0x40000100\0" \
+	"splsize=0x200\0" \
+	"splfile=falcon.bin\0" \
+	"spl_export=" \
+		   "setexpr spl_imgsize ${splsize} + 8 ;" \
+		   "setenv spl_imgsize 0x${spl_imgsize};" \
+		   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
+		   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
+		   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
+		   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+		   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
+		   "spl export atags 0x40007FC0;" \
+		   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
+		   "mw.l ${spl_addr_tmp} ${splsize};" \
+		   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
+		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
+		   "setenv spl_imgsize;" \
+		   "setenv spl_imgaddr;" \
+		   "setenv spl_addr_tmp;\0" \
+	CONFIG_EXTRA_ENV_ITB \
+	"fdtaddr=40800000\0" \
+
+/* Falcon mode definitions */
+#define CONFIG_SYS_SPL_ARGS_ADDR        CONFIG_SYS_SDRAM_BASE + 0x100
+
+/* GPT */
+
+/* Security subsystem - enable hw_rand() */
+#define CONFIG_EXYNOS_ACE_SHA
+
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+
+#define KEY_PWR_PMIC_NAME		"MAX8997_PMIC"
+#define KEY_PWR_STATUS_REG		MAX8997_REG_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 0)
+#define KEY_PWR_INTERRUPT_REG		MAX8997_REG_INT1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 0)
+
+#define KEY_VOL_UP_GPIO			EXYNOS4_GPIO_X20
+#define KEY_VOL_DOWN_GPIO		EXYNOS4_GPIO_X21
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP			LCD_COLOR16
+
+/* LCD */
+#define CONFIG_BMP_16BPP
+#define CONFIG_FB_ADDR		0x52504000
+#define CONFIG_EXYNOS_MIPI_DSIM
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
new file mode 100644
index 0000000..9c6b2bb
--- /dev/null
+++ b/include/configs/trats2.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Sanghee Kim <sh0130.kim@samsung.com>
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board.
+ */
+
+#ifndef __CONFIG_TRATS2_H
+#define __CONFIG_TRATS2_H
+
+#include <configs/exynos4-common.h>
+
+#define CONFIG_TIZEN			/* TIZEN lib */
+
+#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	0x10502000
+#endif
+
+/* TRATS2 has 4 banks of DRAM */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+/* select serial console configuration */
+
+/* Console configuration */
+
+#define CONFIG_BOOTCOMMAND		"run autoboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+/* Tizen - partitions definitions */
+#define PARTS_CSA		"csa-mmc"
+#define PARTS_BOOT		"boot"
+#define PARTS_QBOOT		"qboot"
+#define PARTS_CSC		"csc"
+#define PARTS_ROOT		"platform"
+#define PARTS_DATA		"data"
+#define PARTS_UMS		"ums"
+
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
+	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
+
+#define CONFIG_DFU_ALT \
+	"u-boot raw 0x80 0x800;" \
+	"/uImage ext4 0 2;" \
+	"/modem.bin ext4 0 2;" \
+	"/exynos4412-trats2.dtb ext4 0 2;" \
+	""PARTS_CSA" part 0 1;" \
+	""PARTS_BOOT" part 0 2;" \
+	""PARTS_QBOOT" part 0 3;" \
+	""PARTS_CSC" part 0 4;" \
+	""PARTS_ROOT" part 0 5;" \
+	""PARTS_DATA" part 0 6;" \
+	""PARTS_UMS" part 0 7;" \
+	"params.bin raw 0x38 0x8;" \
+	"/Image.itb ext4 0 2\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootk=" \
+		"run loaduimage;" \
+		"if run loaddtb; then " \
+			"bootm 0x40007FC0 - ${fdtaddr};" \
+		"fi;" \
+		"bootm 0x40007FC0;\0" \
+	"updatebackup=" \
+		"mmc dev 0 2; mmc write 0x51000000 0 0x800;" \
+		" mmc dev 0 0\0" \
+	"updatebootb=" \
+		"mmc read 0x51000000 0x80 0x800; run updatebackup\0" \
+	"mmcboot=" \
+		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
+		"run bootk\0" \
+	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"verify=n\0" \
+	"rootfstype=ext4\0" \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+	"kernelname=uImage\0" \
+	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
+		"${kernelname}\0" \
+	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
+		"${fdtfile}\0" \
+	"mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \
+	"mmcbootpart=2\0" \
+	"mmcrootpart=5\0" \
+	"opts=always_resume=1\0" \
+	"partitions=" PARTS_DEFAULT \
+	"dfu_alt_info=" CONFIG_DFU_ALT \
+	"uartpath=ap\0" \
+	"usbpath=ap\0" \
+	"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
+	"consoleoff=set console console=ram; save; reset\0" \
+	"spladdr=0x40000100\0" \
+	"splsize=0x200\0" \
+	"splfile=falcon.bin\0" \
+	"spl_export=" \
+		   "setexpr spl_imgsize ${splsize} + 8 ;" \
+		   "setenv spl_imgsize 0x${spl_imgsize};" \
+		   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
+		   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
+		   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
+		   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+		   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
+		   "spl export atags 0x40007FC0;" \
+		   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
+		   "mw.l ${spl_addr_tmp} ${splsize};" \
+		   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
+		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
+		   "setenv spl_imgsize;" \
+		   "setenv spl_imgaddr;" \
+		   "setenv spl_addr_tmp;\0" \
+	CONFIG_EXTRA_ENV_ITB \
+	"fdtaddr=40800000\0" \
+
+/* GPT */
+
+/* Security subsystem - enable hw_rand() */
+#define CONFIG_EXYNOS_ACE_SHA
+
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+
+#define KEY_PWR_PMIC_NAME		"MAX77686_PMIC"
+#define KEY_PWR_STATUS_REG		MAX77686_REG_PMIC_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 0)
+#define KEY_PWR_INTERRUPT_REG		MAX77686_REG_PMIC_INT1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 1)
+
+#define KEY_VOL_UP_GPIO			EXYNOS4X12_GPIO_X22
+#define KEY_VOL_DOWN_GPIO		EXYNOS4X12_GPIO_X33
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP                 LCD_COLOR16
+
+/* LCD */
+#define CONFIG_BMP_16BPP
+#define CONFIG_FB_ADDR		0x52504000
+#define CONFIG_EXYNOS_MIPI_DSIM
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
new file mode 100644
index 0000000..2106f4e
--- /dev/null
+++ b/include/configs/tricorder.h
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * (C) Copyright 2012
+ * Corscience GmbH & Co. KG
+ * Thomas Weber <weber@corscience.de>
+ *
+ * Configuration settings for the Tricorder board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_TRICORDER
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap.h>
+
+/* Clock Defines */
+#define V_OSCK				26000000 /* Clock output from T2 */
+#define V_SCLK				(V_OSCK >> 1)
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(1024*1024)
+
+/* Hardware drivers */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000 /* 48MHz (APLL96/2) */
+
+/* select serial console configuration */
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+/* I2C */
+#define CONFIG_SYS_I2C
+ 
+
+/* EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
+
+/* TWL4030 */
+
+/* Board NAND Info */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+
+/* needed for ubi */
+
+/* Environment information (this is the common part) */
+
+
+/* hang() the board on panic() */
+
+/* environment placement (for NAND), is different for FLASHCARD but does not
+ * harm there */
+#define CONFIG_ENV_OFFSET_REDUND	0x2A0000    /* redundant env start */
+#define CONFIG_ENV_RANGE		(384 << 10) /* allow badblocks in env */
+
+/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
+ * value can not be used here! */
+#define CONFIG_LOADADDR		0x82000000
+
+#define CONFIG_COMMON_ENV_SETTINGS \
+	"console=ttyO2,115200n8\0" \
+	"mmcdev=0\0" \
+	"vram=3M\0" \
+	"defaultdisplay=lcd\0" \
+	"kernelopts=mtdoops.mtddev=3\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"commonargs=" \
+		"setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"${kernelopts} " \
+		"vt.global_cursor_default=0 " \
+		"vram=${vram} " \
+		"omapdss.def_disp=${defaultdisplay}\0"
+
+#define CONFIG_BOOTCOMMAND "run autoboot"
+
+/* specific environment settings for different use cases
+ * FLASHCARD: used to run a rdimage from sdcard to program the device
+ * 'NORMAL': used to boot kernel from sdcard, nand, ...
+ *
+ * The main aim for the FLASHCARD skin is to have an embedded environment
+ * which will not be influenced by any data already on the device.
+ */
+#ifdef CONFIG_FLASHCARD
+/* the rdaddr is 16 MiB before the loadaddr */
+#define CONFIG_ENV_RDADDR	"rdaddr=0x81000000\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_COMMON_ENV_SETTINGS \
+	CONFIG_ENV_RDADDR \
+	"autoboot=" \
+	"run commonargs; " \
+	"setenv bootargs ${bootargs} " \
+		"flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
+		"rdinit=/sbin/init; " \
+	"mmc dev ${mmcdev}; mmc rescan; " \
+	"fatload mmc ${mmcdev} ${loadaddr} uImage; " \
+	"fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
+	"bootm ${loadaddr} ${rdaddr}\0"
+
+#else /* CONFIG_FLASHCARD */
+
+#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_COMMON_ENV_SETTINGS \
+	"mmcargs=" \
+		"run commonargs; " \
+		"setenv bootargs ${bootargs} " \
+		"root=/dev/mmcblk0p2 " \
+		"rootwait " \
+		"rw\0" \
+	"nandargs=" \
+		"run commonargs; " \
+		"setenv bootargs ${bootargs} " \
+		"root=ubi0:root " \
+		"ubi.mtd=7 " \
+		"rootfstype=ubifs " \
+		"ro\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"loaduimage_ubi=ubi part ubi; " \
+		"ubifsmount ubi:root; " \
+		"ubifsload ${loadaddr} /boot/uImage\0" \
+	"loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"run loaduimage_nand; " \
+		"bootm ${loadaddr}\0" \
+	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
+			"if run loadbootscript; then " \
+				"run bootscript; " \
+			"else " \
+				"if run loaduimage; then " \
+					"run mmcboot; " \
+				"else run nandboot; " \
+				"fi; " \
+			"fi; " \
+		"else run nandboot; fi\0"
+
+#endif /* CONFIG_FLASHCARD */
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x00000000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					0x07000000) /* 112 MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2 /* Divisor: 2^(PTV+1) => 8 */
+
+/*  Physical Memory Map  */
+#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
+
+/* NAND and environment organization  */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+
+/* SRAM config */
+#define CONFIG_SYS_SRAM_START		0x40200000
+#define CONFIG_SYS_SRAM_SIZE		0x10000
+
+/* Defines for SPL */
+
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
+
+#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
+					 CONFIG_SPL_TEXT_BASE)
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
+					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
+					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
+					 52, 53, 54, 55, 56}
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	13
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
+
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x81000000
+#endif /* __CONFIG_H */
diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h
new file mode 100644
index 0000000..93db175
--- /dev/null
+++ b/include/configs/trimslice.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include "tegra20-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"Compulab Trimslice"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_GPU
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_TRIMSLICE
+
+/* SPI */
+
+/* Environment in SPI */
+#define CONFIG_ENV_SECT_SIZE		CONFIG_ENV_SIZE
+/* 1MiB flash, environment located as high as possible */
+#define CONFIG_ENV_OFFSET		(SZ_1M - CONFIG_ENV_SIZE)
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ts4600.h b/include/configs/ts4600.h
new file mode 100644
index 0000000..a107e96
--- /dev/null
+++ b/include/configs/ts4600.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Derived from MX28EVK code by
+ *   Fabio Estevam <fabio.estevam@freescale.com>
+ *   Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the TS4600 Board
+ */
+#ifndef __CONFIGS_TS4600_H__
+#define __CONFIGS_TS4600_H__
+
+/* U-Boot Commands */
+
+/* Memory configuration */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* Max 1 GB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(256 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+/* Boot Linux */
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_addr=0x41000000\0" \
+	"loadkernel=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} imx28-ts4600.dtb\0" \
+	"loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot.ub\0" \
+	"bootscript=echo Running bootscript from mmc...; " \
+		"setenv mmcdev 0; " \
+		"setenv mmcpart 2; " \
+		"run loadbootscript && source ${loadaddr}; \0" \
+	"sdboot=echo Booting from SD card ...; " \
+		"setenv mmcdev 0; " \
+		"setenv mmcpart 2; " \
+		"setenv root /dev/mmcblk0p3; " \
+		"run loadkernel && run loadfdt; \0" \
+	"startbootsequence=run bootscript || run sdboot \0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc rescan; " \
+	"run startbootsequence; " \
+	"setenv cmdline_append console=ttyAMA0,115200; " \
+	"setenv bootargs root=${root} rootwait rw ${cmdline_append}; " \
+	"bootz ${loadaddr} - ${fdt_addr}; "
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_TS4600_H__ */
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
new file mode 100644
index 0000000..4e274bd
--- /dev/null
+++ b/include/configs/ts4800.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Savoir-faire Linux Inc.
+ *
+ * Derived from MX51EVK code by
+ *   Guennadi Liakhovetski <lg@denx.de>
+ *   Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the TS4800 Board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 2nd stage bootloader */
+
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_TS48XX
+
+/* text base address used when linking */
+
+#include <asm/arch/imx-regs.h>
+
+/* enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/*
+ * MMC Configs
+ * */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	MMC_SDHC1_BASE_ADDR
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	        FEC_BASE_ADDR
+#define CONFIG_ETHPRIME		"FEC"
+#define CONFIG_FEC_MXC_PHYADDR	0
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE		/* disable vendor parameters protection (serial#, ethaddr) */
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+/* Environment variables */
+
+
+#define CONFIG_LOADADDR		0x91000000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"fdt_file=imx51-ts4800.dtb\0" \
+	"fdt_addr=0x90fe0000\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"mmcargs=setenv bootargs root=${mmcroot}\0" \
+	"addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs addtty; " \
+		"if run loadfdt; then " \
+			"bootz ${loadaddr} - ${fdt_addr}; " \
+		"else " \
+			"echo ERR: cannot load FDT; " \
+		"fi; "
+
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"fi; " \
+		"fi; " \
+	"fi; "
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Low level init */
+#define CONFIG_SYS_DDR_CLKSEL	0
+#define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
+
+/*-----------------------------------------------------------------------
+ * Environment organization
+ */
+
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h
new file mode 100644
index 0000000..808538e
--- /dev/null
+++ b/include/configs/tuge1.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME	"tuge1"
+#define CONFIG_HOSTNAME		"tuge1"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h
new file mode 100644
index 0000000..16a49c7
--- /dev/null
+++ b/include/configs/turris_mox.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Marek Behun <marek.behun@nic.cz>
+ *
+ * Based on mvebu_armada-37xx.h by Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _CONFIG_TURRIS_MOX_H
+#define _CONFIG_TURRIS_MOX_H
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+
+/* auto boot */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
+					  115200, 230400, 460800, 921600 }
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG		/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */
+
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(4 << 20) /* 4MiB for malloc() */
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00800000	/* 8M */
+#define CONFIG_SYS_MEMTEST_END	0x00ffffff	/*(_16M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* End of 16M scrubbed by training in bootrom */
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE + 0xFF0000)
+
+/*
+ * I2C
+ */
+#define CONFIG_I2C_MV
+#define CONFIG_SYS_I2C_SLAVE		0x0
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		0x180000 /* as Marvell U-Boot version */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
+
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_ARP_TIMEOUT	200
+#define CONFIG_NET_RETRY_COUNT	50
+#define CONFIG_PHY_MARVELL
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"scriptaddr=0x4d00000\0"	\
+	"pxefile_addr_r=0x4e00000\0"	\
+	"fdt_addr_r=0x4f00000\0"	\
+	"kernel_addr_r=0x5000000\0"	\
+	"ramdisk_addr_r=0x8000000\0"	\
+	BOOTENV
+
+#endif /* _CONFIG_TURRIS_MOX_H */
diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h
new file mode 100644
index 0000000..abe1e99
--- /dev/null
+++ b/include/configs/turris_omnia.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
+ * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
+ */
+
+#ifndef _CONFIG_TURRIS_OMNIA_H
+#define _CONFIG_TURRIS_OMNIA_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_OFFSET		((1 << 20) - CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB */
+
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define RELOCATION_LIMITS_ENV_SETTINGS	\
+	"fdt_high=0x10000000\0"		\
+	"initrd_high=0x10000000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_SIZE			(140 << 10)
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI
+/* SPL related SPI defines */
+# define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+#endif
+
+#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC
+/* SPL related MMC defines */
+# define CONFIG_SYS_MMC_U_BOOT_OFFS		(160 << 10)
+# define CONFIG_SYS_U_BOOT_OFFS			CONFIG_SYS_MMC_U_BOOT_OFFS
+# ifdef CONFIG_SPL_BUILD
+#  define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER	0x00180000	/* in SDRAM */
+# endif
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Include the common distro boot environment */
+#ifndef CONFIG_SPL_BUILD
+
+#ifdef CONFIG_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#ifdef CONFIG_SCSI
+#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
+#else
+#define BOOT_TARGET_DEVICES_SCSI(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_SCSI(func) \
+	BOOT_TARGET_DEVICES_USB(func) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#define KERNEL_ADDR_R	__stringify(0x1000000)
+#define FDT_ADDR_R	__stringify(0x2000000)
+#define RAMDISK_ADDR_R	__stringify(0x2200000)
+#define SCRIPT_ADDR_R	__stringify(0x1800000)
+#define PXEFILE_ADDR_R	__stringify(0x1900000)
+
+#define LOAD_ADDRESS_ENV_SETTINGS \
+	"kernel_addr_r=" KERNEL_ADDR_R "\0" \
+	"fdt_addr_r=" FDT_ADDR_R "\0" \
+	"ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
+	"scriptaddr=" SCRIPT_ADDR_R "\0" \
+	"pxefile_addr_r=" PXEFILE_ADDR_R "\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	RELOCATION_LIMITS_ENV_SETTINGS \
+	LOAD_ADDRESS_ENV_SETTINGS \
+	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+	"console=ttyS0,115200\0" \
+	"ethact=ethernet@34000\0" \
+	BOOTENV
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* _CONFIG_TURRIS_OMNIA_H */
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h
new file mode 100644
index 0000000..0eb673a
--- /dev/null
+++ b/include/configs/tuxx1.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_KM_BOARD_NAME	"tuxx1"
+#define CONFIG_HOSTNAME		"tuxx1"
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+#include "km/km-mpc83xx.h"
+#include "km/km-mpc832x.h"
+
+#define CONFIG_SYS_MAMR		(MxMR_GPL_x4DIS | \
+				 0x0000c000 | \
+				 MxMR_WLFx_2X)
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
new file mode 100644
index 0000000..3378b4a
--- /dev/null
+++ b/include/configs/udoo.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for Udoo board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#include "imx6_spl.h"
+
+/* Provide the MACH_TYPE value that the vendor kernel requires. */
+#define CONFIG_MACH_TYPE		4800
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(2 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+
+/* SATA Configs */
+
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#endif
+
+/* Network support */
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE                    ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          6
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc1,115200\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdtfile=undefined\0" \
+	"fdt_addr=0x18000000\0" \
+	"fdt_addr_r=0x18000000\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcrootfstype=ext4\0" \
+	"findfdt="\
+		"if test ${board_rev} = MX6Q; then " \
+			"setenv fdtfile imx6q-udoo.dtb; fi; " \
+		"if test ${board_rev} = MX6DL; then " \
+			"setenv fdtfile imx6dl-udoo.dtb; fi; " \
+		"if test ${fdtfile} = undefined; then " \
+			"echo WARNING: Could not determine dtb to use; fi\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(SATA, sata, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#endif			       /* __CONFIG_H * */
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
new file mode 100644
index 0000000..6ba4270
--- /dev/null
+++ b/include/configs/udoo_neo.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright Jasbir Matharu
+ * Copyright 2015 UDOO Team
+ *
+ * Configuration settings for the UDOO NEO board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
+#define CONFIG_MXC_UART
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* Command definition */
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+#define CONFIG_SYS_MMC_ENV_DEV		0  /*USDHC2*/
+
+/* Linux only */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc0,115200\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdtfile=undefined\0" \
+	"fdt_addr=0x83000000\0" \
+	"fdt_addr_r=0x83000000\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcrootfstype=ext4\0" \
+	"findfdt="\
+		"if test $board_name = BASIC; then " \
+			"setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \
+		"if test $board_name = BASICKS; then " \
+			"setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \
+		"if test $board_name = FULL; then " \
+			"setenv fdtfile imx6sx-udoo-neo-full.dtb; fi; " \
+		"if test $board_name = EXTENDED; then " \
+			"setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \
+		"if test $fdtfile = UNDEFINED; then " \
+			"echo WARNING: Could not determine dtb to use; fi\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x84000000\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000)
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#define CONFIG_ENV_SIZE			SZ_8K
+
+#define CONFIG_IMX_THERMAL
+
+/* I2C configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE3000
+#define CONFIG_POWER_PFUZE3000_I2C_ADDR	0x08
+#define PFUZE3000_I2C_BUS	0
+
+/* Network */
+#define CONFIG_FEC_MXC
+
+#define CONFIG_FEC_ENET_DEV 0
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x0
+
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME                 "FEC0"
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h
new file mode 100644
index 0000000..6f2a0cc
--- /dev/null
+++ b/include/configs/ulcb.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/ulcb.h
+ *     This file is ULCB board configuration.
+ *
+ * Copyright (C) 2017 Renesas Electronics Corporation
+ */
+
+#ifndef __ULCB_H
+#define __ULCB_H
+
+#include "rcar-gen3-common.h"
+
+/* Ethernet RAVB */
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+#endif /* __ULCB_H */
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
new file mode 100644
index 0000000..68568f4
--- /dev/null
+++ b/include/configs/uniphier.h
@@ -0,0 +1,231 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+/* U-Boot - Common settings for UniPhier Family */
+
+#ifndef __CONFIG_UNIPHIER_COMMON_H__
+#define __CONFIG_UNIPHIER_COMMON_H__
+
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_bootcmd.h>
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICE_MMC(func)	func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+#define BOOT_TARGET_DEVICE_MMC(func)
+#endif
+
+#ifdef CONFIG_CMD_UBIFS
+#define BOOT_TARGET_DEVICE_UBIFS(func)	func(UBIFS, ubifs, 0)
+#else
+#define BOOT_TARGET_DEVICE_UBIFS(func)
+#endif
+
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_DEVICE_USB(func)	func(USB, usb, 0)
+#else
+#define BOOT_TARGET_DEVICE_USB(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func)	\
+	BOOT_TARGET_DEVICE_MMC(func)	\
+	BOOT_TARGET_DEVICE_UBIFS(func)	\
+	BOOT_TARGET_DEVICE_USB(func)
+#else
+#define BOOTENV
+#endif
+
+#define CONFIG_ARMV7_PSCI_1_0
+
+/*-----------------------------------------------------------------------
+ * MMU and Cache Setting
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#define CONFIG_TIMESTAMP
+
+/* FLASH related */
+
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MONITOR_BASE		0
+#define CONFIG_SYS_MONITOR_LEN		0x000d0000	/* 832KB */
+#define CONFIG_SYS_FLASH_BASE		0
+
+/*
+ * flash_toggle does not work for our support card.
+ * We need to use flash_status_poll.
+ */
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+
+/* serial console configuration */
+
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_ENV_OFFSET			0x100000
+#define CONFIG_ENV_SIZE				0x2000
+/* #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		1
+
+#if !defined(CONFIG_ARM64)
+/* Time clock 1MHz */
+#define CONFIG_SYS_TIMER_RATE			1000000
+#endif
+
+#define CONFIG_SYS_MAX_NAND_DEVICE			1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_REGS_BASE			0x68100000
+#define CONFIG_SYS_NAND_DATA_BASE			0x68000000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS			0
+
+/*
+ * Network Configuration
+ */
+#define CONFIG_SERVERIP			192.168.11.1
+#define CONFIG_IPADDR			192.168.11.10
+#define CONFIG_GATEWAYIP		192.168.11.1
+#define CONFIG_NETMASK			255.255.255.0
+
+#define CONFIG_SYS_LOAD_ADDR		0x85000000
+#define CONFIG_SYS_BOOTM_LEN		(32 << 20)
+
+#if defined(CONFIG_ARM64)
+/* ARM Trusted Firmware */
+#define BOOT_IMAGES \
+	"second_image=unph_bl.bin\0" \
+	"third_image=fip.bin\0"
+#else
+#define BOOT_IMAGES \
+	"second_image=u-boot-spl.bin\0" \
+	"third_image=u-boot.bin\0"
+#endif
+
+#define CONFIG_ROOTPATH			"/nfs/root/path"
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs $bootargs root=/dev/nfs rw "			\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
+		"run __nfsboot"
+
+#ifdef CONFIG_FIT
+#define CONFIG_BOOTFILE			"fitImage"
+#define KERNEL_ADDR_R_OFFSET		"0x05100000"
+#define LINUXBOOT_ENV_SETTINGS \
+	"tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
+		"bootm $kernel_addr_r\0" \
+	"__nfsboot=run tftpboot\0"
+#else
+#ifdef CONFIG_ARM64
+#define CONFIG_BOOTFILE			"Image"
+#define LINUXBOOT_CMD			"booti"
+#define KERNEL_ADDR_R_OFFSET		"0x02080000"
+#else
+#define CONFIG_BOOTFILE			"zImage"
+#define LINUXBOOT_CMD			"bootz"
+#define KERNEL_ADDR_R_OFFSET		"0x00208000"
+#endif
+#define LINUXBOOT_ENV_SETTINGS \
+	"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \
+		LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
+	"tftpboot=tftpboot $kernel_addr_r $bootfile && " \
+		"tftpboot $fdt_addr_r $fdtfile &&" \
+		"tftpboot $ramdisk_addr_r $ramdisk_file &&" \
+		"setenv ramdisk_addr_r $ramdisk_addr_r:$filesize &&" \
+		"run boot_common\0" \
+	"__nfsboot=tftpboot $kernel_addr_load $bootfile && " \
+		"tftpboot $fdt_addr_r $fdtfile &&" \
+		"setenv ramdisk_addr_r - &&" \
+		"run boot_common\0"
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"fdt_addr_r_offset=0x05100000\0" \
+	"kernel_addr_r_offset=" KERNEL_ADDR_R_OFFSET "\0" \
+	"ramdisk_addr_r_offset=0x06000000\0" \
+	"ramdisk_file=rootfs.cpio.gz\0" \
+	"netdev=eth0\0"						\
+	"initrd_high=0xffffffffffffffff\0"			\
+	"loadaddr_offset=0x05000000\0" \
+	"script=boot.scr\0" \
+	"scriptaddr=0x85000000\0"				\
+	"nor_base=0x42000000\0"					\
+	"emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \
+	"nandboot=run bootcmd_ubifs0\0" \
+	"norboot=run tftpboot\0" \
+	"usbboot=run bootcmd_usb0\0" \
+	"emmcscript=setenv devtype mmc && " \
+		"mmcsetn && " \
+		"setenv devnum ${mmc_first_dev} && " \
+		"run loadscript_fat\0" \
+	"nandscript=echo Running ${script} from ubi ... && " \
+		"ubi part UBI && " \
+		"ubifsmount ubi0:boot && " \
+		"ubifsload ${loadaddr} ${script} && " \
+		"source\0" \
+	"norscript=echo Running ${script} from tftp ... && " \
+		"tftpboot ${script} &&" \
+		"source\0" \
+	"usbscript=usb start && " \
+		"setenv devtype usb && " \
+		"setenv devnum 0 && " \
+		"run loadscript_fat\0" \
+	"loadscript_fat=echo Running ${script} from ${devtype}${devnum} ... && " \
+		"load ${devtype} ${devnum}:1 ${loadaddr} ${script} && " \
+		"source\0" \
+	"sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&"	\
+		"tftpboot $tmp_addr $second_image && " \
+		"setexpr tmp_addr $nor_base + 0x70000 && " \
+		"tftpboot $tmp_addr $third_image\0" \
+	"emmcupdate=mmcsetn &&"					\
+		"mmc dev $mmc_first_dev &&"			\
+		"mmc partconf $mmc_first_dev 0 1 1 &&"		\
+		"tftpboot $second_image && " \
+		"mmc write $loadaddr 0 100 && " \
+		"tftpboot $third_image && " \
+		"mmc write $loadaddr 100 f00\0" \
+	"nandupdate=nand erase 0 0x00100000 &&"			\
+		"tftpboot $second_image && " \
+		"nand write $loadaddr 0 0x00020000 && " \
+		"tftpboot $third_image && " \
+		"nand write $loadaddr 0x00020000 0x001e0000\0" \
+	"usbupdate=usb start &&" \
+		"tftpboot $second_image && " \
+		"usb write $loadaddr 0 100 && " \
+		"tftpboot $third_image && " \
+		"usb write $loadaddr 100 f00\0" \
+	BOOT_IMAGES \
+	LINUXBOOT_ENV_SETTINGS \
+	BOOTENV
+
+#define CONFIG_SYS_BOOTMAPSZ			0x20000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)
+
+/* only for SPL */
+#define CONFIG_SPL_STACK		(0x00200000)
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS		0x20000
+
+/* subtract sizeof(struct image_header) */
+#define CONFIG_SYS_UBOOT_BASE			(0x130000 - 0x40)
+
+#define CONFIG_SPL_TARGET			"u-boot-with-spl.bin"
+#define CONFIG_SPL_MAX_FOOTPRINT		0x10000
+#define CONFIG_SPL_MAX_SIZE			0x10000
+#define CONFIG_SPL_BSS_MAX_SIZE			0x2000
+
+#define CONFIG_SPL_PAD_TO			0x20000
+
+#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
new file mode 100644
index 0000000..c0ba647
--- /dev/null
+++ b/include/configs/usb_a9263.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2013
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
+ * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Settings for Calao USB-A9263 board
+ *
+ * U-Boot image has to be less than 200704 bytes, otherwise at91bootstrap
+ * installed on board will not be able to load it properly.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_USB_A9263
+
+#define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Hardware drivers
+ */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT			20
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_BOOTCOMMAND	"nboot 21000000 0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h
new file mode 100644
index 0000000..128f02d
--- /dev/null
+++ b/include/configs/usbarmory.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * USB armory MkI board configuration settings
+ * http://inversepath.com/usbarmory
+ *
+ * Copyright (C) 2015, Inverse Path
+ * Andrej Rosano <andrej@inversepath.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_FSL_CLK
+
+#include <asm/arch/imx-regs.h>
+
+/* U-Boot environment */
+#define CONFIG_ENV_OFFSET	(6 * 64 * 1024)
+#define CONFIG_ENV_SIZE		(8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV	0
+
+/* U-Boot general configurations */
+#define CONFIG_SYS_CBSIZE	512
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* SD/MMC */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+/* USB */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+
+/* Fuse */
+#define CONFIG_FSL_IIM
+
+/* U-Boot memory offsets */
+#define CONFIG_LOADADDR		0x72000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Linux boot */
+#define CONFIG_HOSTNAME		"usbarmory"
+#define CONFIG_BOOTCOMMAND						\
+	"run distro_bootcmd; "						\
+	"setenv bootargs console=${console} ${bootargs_default}; "	\
+	"ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; "		\
+	"ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; "		\
+	"bootz ${kernel_addr_r} - ${fdt_addr_r}"
+
+#define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0)
+
+#include <config_distro_bootcmd.h>
+
+#define MEM_LAYOUT_ENV_SETTINGS			\
+	"kernel_addr_r=0x70800000\0"		\
+	"fdt_addr_r=0x71000000\0"		\
+	"scriptaddr=0x70800000\0"		\
+	"pxefile_addr_r=0x70800000\0"		\
+	"ramdisk_addr_r=0x73000000\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	MEM_LAYOUT_ENV_SETTINGS					\
+	"bootargs_default=root=/dev/mmcblk0p1 rootwait rw\0"	\
+	"fdtfile=imx53-usbarmory.dtb\0"				\
+	"console=ttymxc0,115200\0"				\
+	BOOTENV
+
+#ifndef CONFIG_CMDLINE
+#define USBARMORY_FIT_PATH	"/boot/usbarmory.itb"
+#define USBARMORY_FIT_ADDR	"0x70800000"
+#endif
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			CSD0_BASE_ADDR
+#define PHYS_SDRAM_SIZE			(gd->ram_size)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MEMTEST_START	0x70000000
+#define CONFIG_SYS_MEMTEST_END		0x90000000
+
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h
new file mode 100644
index 0000000..8c68372
--- /dev/null
+++ b/include/configs/vcoreiii.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef __VCOREIII_H
+#define __VCOREIII_H
+
+#include <linux/sizes.h>
+
+/* Onboard devices */
+
+#define CONFIG_SYS_MALLOC_LEN		0x1F0000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_INIT_SP_OFFSET       0x400000
+
+#if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL)
+#define CPU_CLOCK_RATE			416666666 /* Clock for the MIPS core */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	208333333
+#else
+#define CPU_CLOCK_RATE			500000000 /* Clock for the MIPS core */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)
+#endif
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_MIPS_TIMER_FREQ
+
+#define CONFIG_BOARD_TYPES
+
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_OFFSET		(1024 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(256 * 1024)
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET_REDUND      (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ)
+#define CONFIG_SYS_SDRAM_SIZE		(128 * SZ_1M)
+#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT)
+#define CONFIG_SYS_SDRAM_SIZE		(256 * SZ_1M)
+#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16)
+#define CONFIG_SYS_SDRAM_SIZE		(512 * SZ_1M)
+#else
+#error Unknown DDR size - please add!
+#endif
+
+#define CONFIG_CONS_INDEX		1
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M)
+
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
+#define VCOREIII_DEFAULT_MTD_ENV		    \
+	"mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"	    \
+	"mtdids="CONFIG_MTDIDS_DEFAULT"\0"
+#else
+#define VCOREIII_DEFAULT_MTD_ENV    /* Go away */
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN      (16 << 20)      /* Increase max gunzip size */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	VCOREIII_DEFAULT_MTD_ENV					\
+	"loadaddr=0x81000000\0"						\
+	"spi_image_off=0x00100000\0"					\
+	"console=ttyS0,115200\0"					\
+	"setup=setenv bootargs console=${console} ${mtdparts}"		\
+	"${bootargs_extra}\0"						\
+	"spiboot=run setup; sf probe; sf read ${loadaddr}"		\
+	"${spi_image_off} 0x600000; bootm ${loadaddr}\0"		\
+	"ubootfile=u-boot.bin\0"					\
+	"update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};"	\
+	"sf erase UBoot 0x100000;"					\
+	"sf write ${loadaddr} UBoot  ${filesize}\0"			\
+	"bootcmd=run spiboot\0"						\
+	""
+#endif				/* __VCOREIII_H */
diff --git a/include/configs/vct.h b/include/configs/vct.h
new file mode 100644
index 0000000..5710715
--- /dev/null
+++ b/include/configs/vct.h
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ */
+
+/*
+ * This file contains the configuration parameters for the VCT board
+ * family:
+ *
+ * vct_premium
+ * vct_premium_small
+ * vct_premium_onenand
+ * vct_premium_onenand_small
+ * vct_platinum
+ * vct_platinum_small
+ * vct_platinum_onenand
+ * vct_platinum_onenand_small
+ * vct_platinumavc
+ * vct_platinumavc_small
+ * vct_platinumavc_onenand
+ * vct_platinumavc_onenand_small
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CPU_CLOCK_RATE			324000000 /* Clock for the MIPS core */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* SDRAM is initialized by the bootstrap code */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 << 10)
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
+#define CONFIG_VCT_NOR
+#endif
+
+/*
+ * UART
+ */
+#ifdef CONFIG_VCT_PLATINUMAVC
+#define UART_1_BASE		0xBDC30000
+#else
+#define UART_1_BASE		0xBF89C000
+#endif
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		UART_1_BASE
+#define CONFIG_SYS_NS16550_CLK		921600
+
+/*
+ * SDRAM
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_MBYTES_SDRAM		128
+#define CONFIG_SYS_MEMTEST_START	0x80200000
+#define CONFIG_SYS_MEMTEST_END		0x80400000
+#define CONFIG_SYS_LOAD_ADDR		0x80400000	/* default load address */
+
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+#define CONFIG_NET_RETRY_COUNT		20
+#endif
+
+/*
+ * Commands
+ */
+#if defined(CONFIG_CMD_USB)
+
+/*
+ * USB/EHCI
+ */
+#define CONFIG_USB_EHCI_VCT		/* on VCT platform		*/
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size	*/
+#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
+
+/*
+ * FLASH and environment organization
+ */
+#if defined(CONFIG_VCT_NOR)
+#define CONFIG_FLASH_NOT_MEM_MAPPED
+
+/*
+ * We need special accessor functions for the CFI FLASH driver. This
+ * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
+ */
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+
+/*
+ * For the non-memory-mapped NOR FLASH, we need to define the
+ * NOR FLASH area. This can't be detected via the addr2info()
+ * function, since we check for flash access in the very early
+ * U-Boot code, before the NOR FLASH is detected.
+ */
+#define CONFIG_FLASH_BASE		0xb0000000
+#define CONFIG_FLASH_END		0xbfffffff
+
+/*
+ * CFI driver settings
+ */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
+
+#define CONFIG_SYS_FLASH_BASE		0xb0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+#endif /* CONFIG_VCT_NOR */
+
+#if defined(CONFIG_VCT_ONENAND)
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define	CONFIG_SYS_ONENAND_BASE		0x00000000	/* this is not real address */
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_ENV_ADDR			(128 << 10)	/* after compr. U-Boot image */
+#define	CONFIG_ENV_SIZE			(128 << 10)	/* erase size */
+#endif /* CONFIG_VCT_ONENAND */
+
+/*
+ * I2C/EEPROM
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	83000	/* 83 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7f
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define CONFIG_SYS_GPIO_I2C_SCL		11
+#define CONFIG_SYS_GPIO_I2C_SDA		10
+
+#ifndef __ASSEMBLY__
+int vct_gpio_dir(int pin, int dir);
+void vct_gpio_set(int pin, int val);
+int vct_gpio_get(int pin);
+#endif
+
+#define I2C_INIT	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
+#define I2C_ACTIVE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
+#define I2C_TRISTATE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
+#define I2C_READ	vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
+#define I2C_SDA(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
+#define I2C_SCL(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+/* CAT24WC32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last 5 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+#define CONFIG_BOOTCOMMAND	"run test3"
+
+/*
+ * UBI configuration
+ */
+
+/*
+ * We need a small, stripped down image to fit into the first 128k OneNAND
+ * erase block (gzipped). This image only needs basic commands for FLASH
+ * (NOR/OneNAND) usage and Linux kernel booting.
+ */
+#if defined(CONFIG_VCT_SMALL_IMAGE)
+#undef CONFIG_SYS_I2C_SOFT
+#undef CONFIG_SOURCE
+#undef CONFIG_TIMESTAMP
+#endif /* CONFIG_VCT_SMALL_IMAGE */
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
new file mode 100644
index 0000000..66f771d
--- /dev/null
+++ b/include/configs/ve8313.h
@@ -0,0 +1,272 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ */
+/*
+ * ve8313 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1
+
+#define CONFIG_PCI_INDIRECT_BRIDGE 1
+#define CONFIG_FSL_ELBC		1
+
+/*
+ * On-board devices
+ *
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000
+#define CONFIG_SYS_MEMTEST_END		0x07000000
+
+/*
+ * Device configurations
+ */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory*/
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * have the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE	128	/* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_AP \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ALL \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_10)
+				/* 0x80840102 */
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (3 << TIMING_CFG0_RRT_SHIFT) \
+				| (2 << TIMING_CFG0_WWT_SHIFT) \
+				| (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x0e720802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x26256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (5 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x029028c7 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03202000 */
+#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32)
+				/* 0x43080000 */
+#define CONFIG_SYS_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_MODE	((0x4440 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* 0x44400232 */
+#define CONFIG_SYS_DDR_MODE_2	0x8000C000
+
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/*0x02000000*/
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_NOMZ \
+				| DDRCDR_NZ_NOMZ \
+				| DDRCDR_M_ODR)
+				/* 0x73000002 */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		32	/* size in MB */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per dev */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+
+/*
+ * NAND settings
+ */
+#define CONFIG_SYS_NAND_BASE		0x61000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+
+
+
+/* Still needed for spl_minimal.c */
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+
+
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#endif
+
+/*
+ * TSEC
+ */
+
+#define CONFIG_TSEC1
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME	"TSEC1"
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x01
+#define TSEC1_FLAGS		0
+#define TSEC1_PHYIDX		0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC1"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x4000
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND	\
+			(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH	(0x01000000 | \
+				SICRH_ETSEC2_B | \
+				SICRH_ETSEC2_C | \
+				SICRH_ETSEC2_D | \
+				SICRH_ETSEC2_E | \
+				SICRH_ETSEC2_F | \
+				SICRH_ETSEC2_G | \
+				SICRH_TSOBI1 | \
+				SICRH_TSOBI2)
+				/* 0x010fff03 */
+#define CONFIG_SYS_SICRL	(SICRL_LBC | \
+				SICRL_SPI_A | \
+				SICRL_SPI_B | \
+				SICRL_SPI_C | \
+				SICRL_SPI_D | \
+				SICRL_ETSEC2_A)
+				/* 0x33fc0003) */
+
+#define CONFIG_NETDEV		eth0
+
+#define CONFIG_HOSTNAME		"ve8313"
+#define CONFIG_UBOOTPATH	ve8313/u-boot.bin
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" __stringify(CONFIG_NETDEV) "\0"			\
+	"ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0"			\
+	"u-boot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"u-boot_addr_r=100000\0"					\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off " __stringify(CONFIG_SYS_FLASH_BASE)	\
+		" +${filesize};"	\
+	"erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"	\
+	"cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" ${filesize};"							\
+	"protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/venice2.h b/include/configs/venice2.h
new file mode 100644
index 0000000..8ad872d
--- /dev/null
+++ b/include/configs/venice2.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Venice2"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+#include "tegra-common-usb-gadget.h"
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
new file mode 100644
index 0000000..09f90db
--- /dev/null
+++ b/include/configs/ventana.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include "tegra20-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Ventana"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_VENTANA
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
new file mode 100644
index 0000000..b2c14f9
--- /dev/null
+++ b/include/configs/vexpress_aemv8a.h
@@ -0,0 +1,222 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ */
+
+#ifndef __VEXPRESS_AEMV8A_H
+#define __VEXPRESS_AEMV8A_H
+
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
+#ifndef CONFIG_SEMIHOSTING
+#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
+#endif
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+/* Link Definitions */
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
+/* ATF loads u-boot here for BASE_FVP model */
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
+#elif CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)      /* Increase max gunzip size */
+
+/* CS register bases for the original memory map. */
+#define V2M_PA_CS0			0x00000000
+#define V2M_PA_CS1			0x14000000
+#define V2M_PA_CS2			0x18000000
+#define V2M_PA_CS3			0x1c000000
+#define V2M_PA_CS4			0x0c000000
+#define V2M_PA_CS5			0x10000000
+
+#define V2M_PERIPH_OFFSET(x)		(x << 16)
+#define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
+#define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
+#define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
+
+#define V2M_BASE			0x80000000
+
+/* Common peripherals relative to CS7. */
+#define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
+#define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
+#define V2M_KMI0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
+#define V2M_KMI1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
+
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define V2M_UART0			0x7ff80000
+#define V2M_UART1			0x7ff70000
+#else /* Not Juno */
+#define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
+#define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
+#define V2M_UART2			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
+#define V2M_UART3			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
+#endif
+
+#define V2M_WDT				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
+
+#define V2M_TIMER01			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
+#define V2M_TIMER23			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
+
+#define V2M_SERIAL_BUS_DVI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
+#define V2M_RTC				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
+
+#define V2M_CF				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
+
+#define V2M_CLCD			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
+
+/* System register offsets. */
+#define V2M_SYS_CFGDATA			(V2M_SYSREGS + 0x0a0)
+#define V2M_SYS_CFGCTRL			(V2M_SYSREGS + 0x0a4)
+#define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */
+
+/* Generic Interrupt Controller Definitions */
+#ifdef CONFIG_GICV3
+#define GICD_BASE			(0x2f000000)
+#define GICR_BASE			(0x2f100000)
+#else
+
+#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
+#define GICD_BASE			(0x2f000000)
+#define GICC_BASE			(0x2c000000)
+#elif CONFIG_TARGET_VEXPRESS64_JUNO
+#define GICD_BASE			(0x2C010000)
+#define GICC_BASE			(0x2C02f000)
+#endif
+#endif /* !CONFIG_GICV3 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))
+
+#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
+/* The Vexpress64 simulators use SMSC91C111 */
+#define CONFIG_SMC91111			1
+#define CONFIG_SMC91111_BASE		(0x01A000000)
+#endif
+
+/* PL011 Serial Configuration */
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_PL011_CLOCK		7273800
+#else
+#define CONFIG_PL011_CLOCK		24000000
+#endif
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
+/* Top 16MB reserved for secure world use */
+#define DRAM_SEC_SIZE		0x01000000
+#define PHYS_SDRAM_1_SIZE	0x80000000 - DRAM_SEC_SIZE
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define PHYS_SDRAM_2			(0x880000000)
+#define PHYS_SDRAM_2_SIZE		0x180000000
+#endif
+
+/* Enable memtest */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+
+/* Initial environment variables */
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+/*
+ * Defines where the kernel and FDT exist in NOR flash and where it will
+ * be copied into DRAM
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+				"kernel_name=norkern\0"	\
+				"kernel_alt_name=Image\0"	\
+				"kernel_addr=0x80080000\0" \
+				"initrd_name=ramdisk.img\0"	\
+				"initrd_addr=0x84000000\0"	\
+				"fdtfile=board.dtb\0" \
+				"fdt_alt_name=juno\0" \
+				"fdt_addr=0x83000000\0" \
+				"fdt_high=0xffffffffffffffff\0" \
+				"initrd_high=0xffffffffffffffff\0" \
+
+/* Copy the kernel and FDT to DRAM memory and boot */
+#define CONFIG_BOOTCOMMAND	"afs load ${kernel_name} ${kernel_addr} ; " \
+				"if test $? -eq 1; then "\
+				"  echo Loading ${kernel_alt_name} instead of "\
+				"${kernel_name}; "\
+				"  afs load ${kernel_alt_name} ${kernel_addr};"\
+				"fi ; "\
+				"afs load  ${fdtfile} ${fdt_addr} ; " \
+				"if test $? -eq 1; then "\
+				"  echo Loading ${fdt_alt_name} instead of "\
+				"${fdtfile}; "\
+				"  afs load ${fdt_alt_name} ${fdt_addr}; "\
+				"fi ; "\
+				"fdt addr ${fdt_addr}; fdt resize; " \
+				"if afs load  ${initrd_name} ${initrd_addr} ; "\
+				"then "\
+				"  setenv initrd_param ${initrd_addr}; "\
+				"  else setenv initrd_param -; "\
+				"fi ; " \
+				"booti ${kernel_addr} ${initrd_param} ${fdt_addr}"
+
+
+#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+				"kernel_name=Image\0"		\
+				"kernel_addr=0x80080000\0"	\
+				"initrd_name=ramdisk.img\0"	\
+				"initrd_addr=0x88000000\0"	\
+				"fdtfile=devtree.dtb\0"		\
+				"fdt_addr=0x83000000\0"		\
+				"fdt_high=0xffffffffffffffff\0"	\
+				"initrd_high=0xffffffffffffffff\0"
+
+#define CONFIG_BOOTCOMMAND	"smhload ${kernel_name} ${kernel_addr}; " \
+				"smhload ${fdtfile} ${fdt_addr}; " \
+				"smhload ${initrd_name} ${initrd_addr} "\
+				"initrd_end; " \
+				"fdt addr ${fdt_addr}; fdt resize; " \
+				"fdt chosen ${initrd_addr} ${initrd_end}; " \
+				"booti $kernel_addr - $fdt_addr"
+
+
+#endif
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
+#define CONFIG_SYS_FLASH_BASE		0x08000000
+/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+/* Store environment at top of flash in the same location as blank.img */
+/* in the Juno firmware. */
+#define CONFIG_ENV_ADDR			0x0BFC0000
+#define CONFIG_ENV_SECT_SIZE		0x00010000
+#else
+#define CONFIG_SYS_FLASH_BASE		0x0C000000
+/* 256 x 256KiB sectors */
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+/* Store environment at top of flash */
+#define CONFIG_ENV_ADDR			0x0FFC0000
+#define CONFIG_ENV_SECT_SIZE		0x00040000
+#endif
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
+#define FLASH_MAX_SECTOR_SIZE		0x00040000
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+
+#endif /* __VEXPRESS_AEMV8A_H */
diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h
new file mode 100644
index 0000000..4f8e635
--- /dev/null
+++ b/include/configs/vexpress_ca15_tc2.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 Linaro
+ * Andre Przywara, <andre.przywara@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ */
+
+#ifndef __VEXPRESS_CA15X2_TC2_h
+#define __VEXPRESS_CA15X2_TC2_h
+
+#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
+#include "vexpress_common.h"
+
+#define CONFIG_SYSFLAGS_ADDR	0x1c010030
+#define CONFIG_SMP_PEN_ADDR	CONFIG_SYSFLAGS_ADDR
+
+#endif
diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h
new file mode 100644
index 0000000..b8079e6
--- /dev/null
+++ b/include/configs/vexpress_ca5x2.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 Linaro
+ * Ryan Harkin, <ryan.harkin@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ */
+
+#ifndef __VEXPRESS_CA5X2_h
+#define __VEXPRESS_CA5X2_h
+
+#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
+#include "vexpress_common.h"
+
+#endif /* __VEXPRESS_CA5X2_h */
diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h
new file mode 100644
index 0000000..8157a58
--- /dev/null
+++ b/include/configs/vexpress_ca9x4.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 Linaro
+ * Ryan Harkin, <ryan.harkin@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ */
+
+#ifndef __VEXPRESS_CA9X4_H
+#define __VEXPRESS_CA9X4_H
+
+#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+#include "vexpress_common.h"
+
+#endif /* VEXPRESS_CA9X4_H */
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
new file mode 100644
index 0000000..47ea89d
--- /dev/null
+++ b/include/configs/vexpress_common.h
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 ARM Limited
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ */
+
+#ifndef __VEXPRESS_COMMON_H
+#define __VEXPRESS_COMMON_H
+
+/*
+ * Definitions copied from linux kernel:
+ * arch/arm/mach-vexpress/include/mach/motherboard.h
+ */
+#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+/* CS register bases for the original memory map. */
+#define V2M_PA_CS0		0x40000000
+#define V2M_PA_CS1		0x44000000
+#define V2M_PA_CS2		0x48000000
+#define V2M_PA_CS3		0x4c000000
+#define V2M_PA_CS7		0x10000000
+
+#define V2M_PERIPH_OFFSET(x)	(x << 12)
+#define V2M_SYSREGS		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
+#define V2M_SYSCTL		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
+#define V2M_SERIAL_BUS_PCI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
+
+#define V2M_BASE		0x60000000
+#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
+/* CS register bases for the extended memory map. */
+#define V2M_PA_CS0		0x08000000
+#define V2M_PA_CS1		0x0c000000
+#define V2M_PA_CS2		0x14000000
+#define V2M_PA_CS3		0x18000000
+#define V2M_PA_CS7		0x1c000000
+
+#define V2M_PERIPH_OFFSET(x)	(x << 16)
+#define V2M_SYSREGS		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
+#define V2M_SYSCTL		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
+#define V2M_SERIAL_BUS_PCI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
+
+#define V2M_BASE		0x80000000
+#endif
+
+/*
+ * Physical addresses, offset from V2M_PA_CS0-3
+ */
+#define V2M_NOR0		(V2M_PA_CS0)
+#define V2M_NOR1		(V2M_PA_CS1)
+#define V2M_SRAM		(V2M_PA_CS2)
+#define V2M_VIDEO_SRAM		(V2M_PA_CS3 + 0x00000000)
+#define V2M_ISP1761		(V2M_PA_CS3 + 0x03000000)
+
+/* Common peripherals relative to CS7. */
+#define V2M_AACI		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
+#define V2M_MMCI		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
+#define V2M_KMI0		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
+#define V2M_KMI1		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
+
+#define V2M_UART0		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
+#define V2M_UART1		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
+#define V2M_UART2		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
+#define V2M_UART3		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
+
+#define V2M_WDT			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
+
+#define V2M_TIMER01		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
+#define V2M_TIMER23		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
+
+#define V2M_SERIAL_BUS_DVI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
+#define V2M_RTC			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
+
+#define V2M_CF			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
+
+#define V2M_CLCD		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
+#define V2M_SIZE_CS7		V2M_PERIPH_OFFSET(32)
+
+/* System register offsets. */
+#define V2M_SYS_CFGDATA		(V2M_SYSREGS + 0x0a0)
+#define V2M_SYS_CFGCTRL		(V2M_SYSREGS + 0x0a4)
+#define V2M_SYS_CFGSTAT		(V2M_SYSREGS + 0x0a8)
+
+/*
+ * Configuration
+ */
+#define SYS_CFG_START		(1 << 31)
+#define SYS_CFG_WRITE		(1 << 30)
+#define SYS_CFG_OSC		(1 << 20)
+#define SYS_CFG_VOLT		(2 << 20)
+#define SYS_CFG_AMP		(3 << 20)
+#define SYS_CFG_TEMP		(4 << 20)
+#define SYS_CFG_RESET		(5 << 20)
+#define SYS_CFG_SCC		(6 << 20)
+#define SYS_CFG_MUXFPGA		(7 << 20)
+#define SYS_CFG_SHUTDOWN	(8 << 20)
+#define SYS_CFG_REBOOT		(9 << 20)
+#define SYS_CFG_DVIMODE		(11 << 20)
+#define SYS_CFG_POWER		(12 << 20)
+#define SYS_CFG_SITE_MB		(0 << 16)
+#define SYS_CFG_SITE_DB1	(1 << 16)
+#define SYS_CFG_SITE_DB2	(2 << 16)
+#define SYS_CFG_STACK(n)	((n) << 12)
+
+#define SYS_CFG_ERR		(1 << 1)
+#define SYS_CFG_COMPLETE	(1 << 0)
+
+/* Board info register */
+#define SYS_ID				V2M_SYSREGS
+#define CONFIG_REVISION_TAG		1
+
+#define CONFIG_SYS_MEMTEST_START	V2M_BASE
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_SYS_L2CACHE_OFF		1
+#define CONFIG_INITRD_TAG		1
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */
+
+#define SCTL_BASE			V2M_SYSCTL
+#define VEXPRESS_FLASHPROG_FLVPPEN	(1 << 0)
+
+#define CONFIG_SYS_TIMER_RATE		1000000
+#define CONFIG_SYS_TIMER_COUNTER	(V2M_TIMER01 + 0x4)
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+/* PL011 Serial Configuration */
+#define CONFIG_PL011_CLOCK		24000000
+#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
+					 (void *)CONFIG_SYS_SERIAL1}
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0		V2M_UART0
+#define CONFIG_SYS_SERIAL1		V2M_UART1
+
+#define CONFIG_ARM_PL180_MMCI
+#define CONFIG_ARM_PL180_MMCI_BASE	V2M_MMCI
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	127
+#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x8000)
+#define LINUX_BOOT_PARAM_ADDR		(V2M_BASE + 0x2000)
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_2			(((unsigned int)V2M_BASE) + \
+					((unsigned int)0x20000000))
+#define PHYS_SDRAM_1_SIZE		0x20000000	/* 512 MB */
+#define PHYS_SDRAM_2_SIZE		0x20000000	/* 512 MB */
+
+/* additions for new relocation code */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Basic environment settings */
+#define BOOT_TARGET_DEVICES(func) \
+        func(MMC, mmc, 1) \
+        func(MMC, mmc, 0) \
+        func(PXE, pxe, na) \
+        func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+#define CONFIG_PLATFORM_ENV_SETTINGS \
+		"loadaddr=0x80008000\0" \
+		"ramdisk_addr_r=0x61000000\0" \
+		"kernel_addr=0x44100000\0" \
+		"ramdisk_addr=0x44800000\0" \
+		"maxramdisk=0x1800000\0" \
+		"pxefile_addr_r=0x88000000\0" \
+		"scriptaddr=0x88000000\0" \
+		"kernel_addr_r=0x80008000\0"
+#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
+#define CONFIG_PLATFORM_ENV_SETTINGS \
+		"loadaddr=0xa0008000\0" \
+		"ramdisk_addr_r=0x81000000\0" \
+		"kernel_addr=0x0c100000\0" \
+		"ramdisk_addr=0x0c800000\0" \
+		"maxramdisk=0x1800000\0" \
+		"pxefile_addr_r=0xa8000000\0" \
+		"scriptaddr=0xa8000000\0" \
+		"kernel_addr_r=0xa0008000\0"
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+		CONFIG_PLATFORM_ENV_SETTINGS \
+                BOOTENV \
+		"console=ttyAMA0,38400n8\0" \
+		"dram=1024M\0" \
+		"root=/dev/sda1 rw\0" \
+		"mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
+			"24M@0x2000000(initrd)\0" \
+		"flashargs=setenv bootargs root=${root} console=${console} " \
+			"mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
+			"devtmpfs.mount=0  vmalloc=256M\0" \
+		"bootflash=run flashargs; " \
+			"cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
+			"bootm ${kernel_addr} ${ramdisk_addr_r}\0"
+
+/* FLASH and environment organization */
+#define PHYS_FLASH_SIZE			0x04000000	/* 64MB */
+#define CONFIG_SYS_FLASH_SIZE		0x04000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+#define CONFIG_SYS_FLASH_BASE0		V2M_NOR0
+#define CONFIG_SYS_FLASH_BASE1		V2M_NOR1
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE0
+
+/* Timeout values in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */
+
+/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT	259		/* Max sectors */
+#define FLASH_MAX_SECTOR_SIZE		0x00040000	/* 256 KB sectors */
+
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE			FLASH_MAX_SECTOR_SIZE
+
+/*
+ * Amount of flash used for environment:
+ * We don't know which end has the small erase blocks so we use the penultimate
+ * sector location for the environment
+ */
+#define CONFIG_ENV_SECT_SIZE		FLASH_MAX_SECTOR_SIZE
+#define CONFIG_ENV_OVERWRITE		1
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - \
+					(2 * CONFIG_ENV_SECT_SIZE))
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE1 + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE0, \
+					  CONFIG_SYS_FLASH_BASE1 }
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+
+#endif /* VEXPRESS_COMMON_H */
diff --git a/include/configs/veyron.h b/include/configs/veyron.h
new file mode 100644
index 0000000..2ab6d6c
--- /dev/null
+++ b/include/configs/veyron.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdin=serial,cros-ec-keyb\0" \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#include <configs/rk3288_common.h>
+
+#define CONFIG_KEYBOARD
+
+#endif
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
new file mode 100644
index 0000000..ba85bc9
--- /dev/null
+++ b/include/configs/vf610twr.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale Vybrid vf610twr board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_MACH_TYPE		4146
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* NAND support */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
+
+/* Dynamic MTD partition support */
+#endif
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+/* QSPI Configs*/
+
+#ifdef CONFIG_FSL_QSPI
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+#define CONFIG_SYS_FSL_QSPI_LE
+#endif
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_SPD_BUS_NUM		0
+
+
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+/* We boot from the gfxRAM area of the OCRAM. */
+#define CONFIG_BOARD_SIZE_LIMIT		520192
+
+/*
+ * We do have 128MB of memory on the Vybrid Tower board. Leave the last
+ * 16MB alone to avoid conflicts with Cortex-M4 firmwares running from
+ * DDR3. Hence, limit the memory range for image processing to 112MB
+ * using bootm_size. All of the following must be within this range.
+ * We have the default load at 32MB into DDR (for the kernel), FDT at
+ * 64MB and the ramdisk 512KB above that (allowing for hopefully never
+ * seen large trees). This allows a reasonable split between ramdisk
+ * and kernel size, where the ram disk can be a bit larger.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x07000000\0" \
+	"loadaddr=0x82000000\0" \
+	"kernel_addr_r=0x82000000\0" \
+	"fdt_addr=0x84000000\0" \
+	"fdt_addr_r=0x84000000\0" \
+	"rdaddr=0x84080000\0" \
+	"ramdisk_addr_r=0x84080000\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	MEM_LAYOUT_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttyLP1\0" \
+	"fdt_file=vf610-twr.dtb\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_SYS_MEMTEST_START	0x80010000
+#define CONFIG_SYS_MEMTEST_END		0x87C00000
+
+/* Physical memory map */
+#define PHYS_SDRAM			(0x80000000)
+#define PHYS_SDRAM_SIZE			(128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			(64 * 2048)
+#define CONFIG_ENV_SECT_SIZE		(64 * 2048)
+#define CONFIG_ENV_RANGE		(512 * 1024)
+#define CONFIG_ENV_OFFSET		0x180000
+#endif
+
+#endif
diff --git a/include/configs/vinco.h b/include/configs/vinco.h
new file mode 100644
index 0000000..eebb3f7
--- /dev/null
+++ b/include/configs/vinco.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration settings for the VInCo platform.
+ *
+ * Based on the settings for the SAMA5-EK board
+ * Copyright (C) 2014 Atmel
+ *		      Bo Shen <voice.shen@atmel.com>
+ * Copyright (C) 2015 Free Electrons
+ *		      Gregory CLEMENT gregory.clement@free-electrons.com
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "at91-sama5_common.h"
+
+/* The value in the common file is too far away for the VInCo platform */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		0xfc00c000
+#define CONFIG_USART_ID			30
+
+/* Timer */
+#define CONFIG_SYS_TIMER_COUNTER	0xfc06863c
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE           0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x4000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+/* SerialFlash */
+
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI0
+#define CONFIG_SPI_FLASH_STMICRO
+#endif
+
+/* MMC */
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define ATMEL_BASE_MMCI			0xfc000000
+#define CONFIG_SYS_MMC_CLK_OD		500000
+
+/* For generating MMC partitions */
+
+#endif
+
+/* USB device */
+
+/* Ethernet Hardware */
+#define CONFIG_PHY_SMSC
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+
+#ifdef CONFIG_SPI_BOOT
+/* bootstrap + u-boot + env + linux in serial flash */
+/* Use our own mapping for the VInCo platform */
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_OFFSET       0x10000
+#define CONFIG_ENV_SIZE         0x10000
+
+/* Update the bootcommand according to our mapping for the VInCo platform */
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND  "mmc dev 0 0;" \
+			    "mmc read ${loadaddr} ${k_offset} ${k_blksize};" \
+			    "mmc read ${oftaddr} ${dtb_offset} ${dtb_blksize};" \
+			    "bootz ${loadaddr} -  ${oftaddr}"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_start=0x20000\0" \
+	"kernel_size=0x800000\0" \
+	"mmcblksize=0x200\0" \
+	"oftaddr=0x21000000\0" \
+	"loadaddr=0x22000000\0" \
+	"update_uboot=tftp ${loadaddr} u-boot.bin;sf probe 0;" \
+	"sf erase 0x20000 0x4B000; sf write ${loadaddr} 0x20000 0x4B000\0" \
+	"create_partition=setexpr dtb_start ${kernel_start} + 0x400000;" \
+	"setexpr rootfs_start ${kernel_start} + ${kernel_size};" \
+	"setenv partitions 'name=kernel,size=${kernel_size}," \
+	"start=${kernel_start};name=rootfs,size=-';" \
+	"gpt write mmc 0 ${partitions} \0"\
+	"f2blk_size=setexpr fileblksize ${filesize} / ${mmcblksize};" \
+	"setexpr fileblksize ${fileblksize} + 1\0" \
+	"store_kernel=tftp ${loadaddr} zImage; run f2blk_size;" \
+	"setexpr k_blksize ${fileblksize};" \
+	"setexpr k_offset ${kernel_start} / ${mmcblksize};" \
+	"mmc write ${fileaddr} ${k_offset} ${fileblksize}\0" \
+	"store_dtb=tftp ${loadaddr} at91-vinco.dtb; run f2blk_size;" \
+	"setexpr dtb_blksize ${fileblksize};" \
+	"setexpr dtb_offset ${dtb_start} / ${mmcblksize};" \
+	"mmc write ${fileaddr} ${dtb_offset} ${fileblksize}\0" \
+	"store_rootfs=tftp ${loadaddr} vinco-gateway-image-vinco.ext4;" \
+	"setexpr rootfs_offset ${rootfs_start} / ${mmcblksize};" \
+	"mmc write ${fileaddr} ${rootfs_offset} ${fileblksize}\0" \
+	"bootdelay=0\0"
+
+#endif
+
+#endif
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
new file mode 100644
index 0000000..33f06c0
--- /dev/null
+++ b/include/configs/vining_2000.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * Configuration settings for the Samtec VIN|ING 2000 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000)
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+/* Network */
+#define CONFIG_FEC_MXC
+
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x0
+
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME                 "FEC"
+
+#define CONFIG_PHY_ATHEROS
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(4, 6)
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_IMX6_PWM_PER_CLK 66000000
+
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET_REDUND	(9 * SZ_64K)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0 /* USDHC4 eMMC */
+/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */
+#define CONFIG_SYS_MMC_ENV_PART		1 /* boot0 */
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
new file mode 100644
index 0000000..a4f2af4
--- /dev/null
+++ b/include/configs/vme8349.h
@@ -0,0 +1,333 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * esd vme8349 U-Boot configuration file
+ * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
+ *
+ * (C) Copyright 2006-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * reinhard.arlt@esd-electronics.de
+ * Based on the MPC8349EMDS config.
+ */
+
+/*
+ * vme8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+
+/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
+
+#undef CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM
+#define SPD_EEPROM_ADDRESS		0x54
+#define CONFIG_SYS_READ_SPD		vme8349_read_spd
+#define CONFIG_SYS_83XX_DDR_USES_CS0	/* esd; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* DDR is sys memory*/
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
+					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+#define CONFIG_SYS_DDRCDR		(DDRCDR_DHC_EN \
+					| DDRCDR_ODT \
+					| DDRCDR_Q_DRN)
+					/* 0x80080001 */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		128		/* flash size in MB */
+
+
+#define CONFIG_SYS_WINDOW1_BASE		0xf0000000
+
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device*/
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase TO (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write TO (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xF7000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000		/* size */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Malloc size */
+
+#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR + 0x4600)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
+
+#define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0xFIXME
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_GMII			/* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define CONFIG_PHY_M88E1111
+#define TSEC1_PHY_ADDR		0x08
+#define TSEC2_PHY_ADDR		0x10
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0xc0000)
+	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_RTC_BUS_NUM  0x01
+#define CONFIG_SYS_I2C_RTC_ADDR	0x32
+
+/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x000043f0
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Init Memory map for Linux*/
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR	0x00100000
+#define CONFIG_SYS_GPIO1_DAT	0x00100000
+
+#define CONFIG_SYS_GPIO2_PRELIM
+#define CONFIG_SYS_GPIO2_DIR	0x78900000
+#define CONFIG_SYS_GPIO2_DAT	0x70100000
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME		"VME8349"
+#define CONFIG_ROOTPATH		"/tftpboot/rootfs"
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_LOADADDR		800000	/* def location for tftp and bootm */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=vme8349\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"		\
+	"update=protect off fff00000 fff3ffff; "			\
+		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+	"upd=run load update\0"						\
+	"fdtaddr=780000\0"						\
+	"fdtfile=vme8349.dtb\0"						\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#ifndef __ASSEMBLY__
+int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
+		     unsigned char *buffer, int len);
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/vyasa-rk3288.h b/include/configs/vyasa-rk3288.h
new file mode 100644
index 0000000..3574a3b
--- /dev/null
+++ b/include/configs/vyasa-rk3288.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Amarula Solutions
+ *
+ * Configuration settings for Amarula Vyasa RK3288.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define ROCKCHIP_DEVICE_SETTINGS
+#include <configs/rk3288_common.h>
+
+#undef BOOT_TARGET_DEVICES
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+
+#define CONFIG_SYS_MMC_ENV_DEV 1
+
+#ifndef CONFIG_TPL_BUILD
+
+#define CONFIG_SPL_OS_BOOT
+
+/* Falcon Mode */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x0ffe5000
+#define CONFIG_CMD_SPL_WRITE_SIZE      (128 * SZ_1K)
+
+/* Falcon Mode - MMC support: args@16MB kernel@17MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR		0x8000	/* 16MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS		(CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR		0x8800	/* 17MB */
+#endif
+
+#endif
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
new file mode 100644
index 0000000..a0a78ea
--- /dev/null
+++ b/include/configs/wandboard.h
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Wandboard.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#include "imx6_spl.h"
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_WANDBOARD_IMX6
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* SATA Configs */
+
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+
+/* Framebuffer */
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc0\0" \
+	"splashpos=m,m\0" \
+	"splashimage=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdtfile=undefined\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_addr_r=0x18000000\0" \
+	"fdt_addr=0x18000000\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"finduuid=part uuid mmc 0:1 uuid\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"findfdt="\
+		"if test $board_name = D1 && test $board_rev = MX6QP ; then " \
+			"setenv fdtfile imx6qp-wandboard-revd1.dtb; fi; " \
+		"if test $board_name = D1 && test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \
+		"if test $board_name = D1 && test $board_rev = MX6DL ; then " \
+			"setenv fdtfile imx6dl-wandboard-revd1.dtb; fi; " \
+		"if test $board_name = C1 && test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-wandboard.dtb; fi; " \
+		"if test $board_name = C1 && test $board_rev = MX6DL ; then " \
+			"setenv fdtfile imx6dl-wandboard.dtb; fi; " \
+		"if test $board_name = B1 && test $board_rev = MX6Q ; then " \
+			"setenv fdtfile imx6q-wandboard-revb1.dtb; fi; " \
+		"if test $board_name = B1 && test $board_rev = MX6DL ; then " \
+			"setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine dtb to use; fi; \0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x13000000\0" \
+	"ramdiskaddr=0x13000000\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2) \
+	func(SATA, sata, 0) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#endif			       /* __CONFIG_H * */
diff --git a/include/configs/warp.h b/include/configs/warp.h
new file mode 100644
index 0000000..41fd6c7
--- /dev/null
+++ b/include/configs/warp.h
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 O.S. Systems Software LTDA.
+ * Copyright (C) 2014 Kynetics LLC.
+ * Copyright (C) 2014 Revolution Robotics, Inc.
+ *
+ * Author: Otavio Salvador <otavio@ossystems.com.br>
+ *
+ * Configuration settings for the WaRP Board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(35 * SZ_1M) /* Increase due to DFU */
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+
+/* Watchdog */
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_256M)
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OFFSET		(6 * SZ_64K)
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+/* VDD voltage 1.65 - 1.95 */
+#define CONFIG_SYS_SD_VOLTAGE		0x00000080
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1 /* Only OTG2 port enabled */
+#endif
+
+#define CONFIG_USBD_HS
+
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_MAX77696
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx6sl-warp.dtb\0" \
+	"fdt_addr=0x88000000\0" \
+	"initrd_addr=0x83800000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"finduuid=part uuid mmc 0:2 uuid\0" \
+	"dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=PARTUUID=${uuid} rootwait rw\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run finduuid; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
new file mode 100644
index 0000000..73541fe
--- /dev/null
+++ b/include/configs/warp7.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ *
+ * Configuration settings for the i.MX7S Warp board.
+ */
+
+#ifndef __WARP7_CONFIG_H
+#define __WARP7_CONFIG_H
+
+#include "mx7_common.h"
+#include <imximage.h>
+
+#define PHYS_SDRAM_SIZE			SZ_512M
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(35 * SZ_1M)
+
+/* MMC Config*/
+#define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC3_BASE_ADDR
+#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* Switch on SERIAL_TAG */
+#define CONFIG_SERIAL_TAG
+
+#define CONFIG_DFU_ENV_SETTINGS \
+	"dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \
+
+/* When booting with FIT specify the node entry containing boot.scr */
+#if defined(CONFIG_FIT)
+#define BOOT_SCR_STRING "source ${bootscriptaddr}:${bootscr_fitimage_name}\0"
+#else
+#define BOOT_SCR_STRING "source ${bootscriptaddr}\0"
+#endif
+
+#ifndef CONFIG_OPTEE_LOAD_ADDR
+#define CONFIG_OPTEE_LOAD_ADDR 0
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_DFU_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"bootscr_fitimage_name=bootscr\0" \
+	"script_signed=boot.scr.imx-signed\0" \
+	"bootscriptaddr=0x83200000\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"ethact=usb_ether\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx7s-warp.dtb\0" \
+	"fdt_addr=" __stringify(CONFIG_SYS_FDT_ADDR)"\0" \
+	"fdtovaddr=0x83100000\0" \
+	"optee_addr=" __stringify(CONFIG_OPTEE_LOAD_ADDR)"\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"rootpart=" __stringify(CONFIG_WARP7_ROOT_PART) "\0" \
+	"finduuid=part uuid mmc 0:${rootpart} uuid\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=PARTUUID=${uuid} rootwait rw\0" \
+	"ivt_offset=" __stringify(BOOTROM_IVT_HDR_OFFSET)"\0"\
+	"warp7_auth_or_fail=hab_auth_img_or_fail ${hab_ivt_addr} ${filesize} 0;\0" \
+	"do_bootscript_hab=" \
+		"if test ${hab_enabled} -eq 1; then " \
+			"setexpr hab_ivt_addr ${bootscriptaddr} - ${ivt_offset}; " \
+			"setenv script ${script_signed}; " \
+			"load mmc ${mmcdev}:${mmcpart} ${hab_ivt_addr} ${script}; " \
+			"run warp7_auth_or_fail; " \
+			"run bootscript; "\
+		"fi;\0" \
+	"loadbootscript=" \
+		"load mmc ${mmcdev}:${mmcpart} ${bootscriptaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		BOOT_SCR_STRING \
+	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run finduuid; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "run do_bootscript_hab;" \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "fi"
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x20000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* I2C configs */
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* environment organization */
+#define CONFIG_ENV_SIZE			SZ_8K
+
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		0
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_USBD_HS
+
+/* USB Device Firmware Update support */
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_16M
+#define DFU_DEFAULT_POLL_TIMEOUT	300
+
+#define CONFIG_USBNET_DEV_ADDR		"de:ad:be:af:00:01"
+
+/* Environment variable name to represent HAB enable state */
+#define HAB_ENABLED_ENVNAME		"hab_enabled"
+
+#endif
diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h
new file mode 100644
index 0000000..43de2e1
--- /dev/null
+++ b/include/configs/wb45n.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the WB45N CPU Module.
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK  32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK  12000000	/* 12 MHz crystal */
+
+#define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY	/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE   ATMEL_BASE_DBGU
+#define CONFIG_USART_ID     ATMEL_ID_SYS
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE       0x20000000
+#define CONFIG_SYS_SDRAM_SIZE       0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+    (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#define CONFIG_SYS_MAX_NAND_DEVICE  1
+#define CONFIG_SYS_NAND_BASE        0x40000000
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE    (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE    (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN  AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN   AT91_PIN_PD5
+
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT      20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_ETHADDR              C0:EE:40:00:00:00
+#define CONFIG_ENV_OVERWRITE        1
+
+/* System */
+#define CONFIG_SYS_LOAD_ADDR        0x22000000	/* load address */
+#define CONFIG_SYS_MEMTEST_START    CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END      0x23e00000
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET           0xa0000
+#define CONFIG_ENV_OFFSET_REDUND    0xc0000
+#define CONFIG_ENV_SIZE             0x20000	/* 1 block = 128 kB */
+
+#define CONFIG_BOOTCOMMAND  "nand read 0x22000000 0xe0000 0x280000; " \
+    "run _mtd; bootm"
+
+#define MTDIDS_DEFAULT      "nand0=atmel_nand"
+#define MTDPARTS_DEFAULT    "mtdparts=atmel_nand:" \
+                            "128K(at91bs)," \
+                            "512K(u-boot)," \
+                            "128K(u-boot-env)," \
+                            "128K(redund-env)," \
+                            "2560K(kernel-a)," \
+                            "2560K(kernel-b)," \
+                            "38912K(rootfs-a)," \
+                            "38912K(rootfs-b)," \
+                            "46208K(user)," \
+                            "512K(logs)"
+
+#else
+#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH'
+#endif
+
+#define CONFIG_BOOTARGS     "console=ttyS0,115200 earlyprintk " \
+                            "rw noinitrd mem=64M "              \
+                            "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6"
+
+#define CONFIG_EXTRA_ENV_SETTINGS       \
+    "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \
+    "autoload=no\0" \
+    "autostart=no\0" \
+    "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
+    "\0"
+
+#define CONFIG_SYS_CBSIZE   256
+#define CONFIG_SYS_MAXARGS  16
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN       (512 * 1024 + 0x1000)
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE         0x6000
+#define CONFIG_SPL_STACK            0x308000
+
+#define CONFIG_SPL_BSS_START_ADDR   0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE     0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE  0x80000
+
+#define CONFIG_SYS_MONITOR_LEN      (512 << 10)
+
+#define CONFIG_SYS_MASTER_CLOCK     132096000
+#define CONFIG_SYS_AT91_PLLA        0x20c73f03
+#define CONFIG_SYS_MCKR             0x1301
+#define CONFIG_SYS_MCKR_CSS         0x1302
+
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE   0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT  64
+#define CONFIG_SYS_NAND_OOBSIZE     64
+#define CONFIG_SYS_NAND_BLOCK_SIZE  0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
+
+#endif				/* __CONFIG_H__ */
diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h
new file mode 100644
index 0000000..6e471f6
--- /dev/null
+++ b/include/configs/wb50n.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the WB50N CPU Module.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000	/* from 12 MHz crystal */
+
+#define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE       ATMEL_BASE_DBGU
+#define CONFIG_USART_ID         ATMEL_ID_DBGU
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE       ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE       0x04000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR     0x310000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+    (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_MEMTEST_START    0x21000000
+#define CONFIG_SYS_MEMTEST_END      0x22000000
+
+/* NAND flash */
+#define CONFIG_SYS_MAX_NAND_DEVICE  1
+#define CONFIG_SYS_NAND_BASE        ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE    (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE    (1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT      20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_RGMII
+#define CONFIG_ETHADDR              C0:EE:40:00:00:00
+#define CONFIG_ENV_OVERWRITE        1
+
+#define CONFIG_SYS_LOAD_ADDR        0x22000000	/* load address */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+    "autoload=no\0" \
+    "autostart=no\0"
+
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_OFFSET_REDUND    0xC0000
+#define CONFIG_BOOTCOMMAND \
+    "nand read 0x22000000 0x000e0000 0x500000; " \
+    "bootm"
+
+#define CONFIG_BOOTARGS \
+    "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
+
+#define CONFIG_BAUDRATE             115200
+
+#define CONFIG_SYS_CBSIZE           1024
+#define CONFIG_SYS_MAXARGS          16
+#define CONFIG_SYS_PBSIZE \
+    (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN       (2 * 1024 * 1024)
+
+/* SPL */
+#define CONFIG_SPL_MAX_SIZE         0x10000
+#define CONFIG_SPL_BSS_START_ADDR   0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE     0x80000
+#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE  0x80000
+
+#define CONFIG_SYS_MONITOR_LEN      (512 << 10)
+
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE   0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT  64
+#define CONFIG_SYS_NAND_OOBSIZE     64
+#define CONFIG_SYS_NAND_BLOCK_SIZE  0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
+
+#endif
diff --git a/include/configs/woodburn.h b/include/configs/woodburn.h
new file mode 100644
index 0000000..7f9ddb5
--- /dev/null
+++ b/include/configs/woodburn.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include "woodburn_common.h"
+
+/* Set TEXT at the beginning of the NOR flash */
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
new file mode 100644
index 0000000..5ad3dab
--- /dev/null
+++ b/include/configs/woodburn_common.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ */
+
+#ifndef __WOODBURN_COMMON_CONFIG_H
+#define __WOODBURN_COMMON_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ	24000000
+#define CONFIG_SYS_FSL_CLK
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_FLEA3
+
+/* This is required to setup the ESDC controller */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_SPD_BUS_NUM		0
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
+#define CONFIG_POWER_FSL_MC13892
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
+#define CONFIG_RTC_MC13XXX
+
+/* mmc driver */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command definition
+ */
+
+#define CONFIG_NET_RETRY_COUNT	100
+
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1
+
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/*
+ * Physical Memory Map
+ */
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(LOW_LEVEL_SRAM_STACK - \
+						IRAM_BASE_ADDR - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(IRAM_BASE_ADDR + \
+					CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * CFI FLASH driver setup
+ */
+
+/* A non-standard buffered write algorithm */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+
+#define CONFIG_HOSTNAME "woodburn"
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"loadaddr=80800000\0"						\
+	"kernel_addr_r=80800000\0"					\
+	"hostname=" CONFIG_HOSTNAME "\0"			\
+	"bootfile=" CONFIG_HOSTNAME "/uImage\0"		\
+	"ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0"	\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
+	"net_self=if run net_self_load;then "				\
+		"run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
+		"else echo Images not loades;fi\0"			\
+	"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"		\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
+	"update=protect off ${uboot_addr} +80000;"			\
+		"erase ${uboot_addr} +80000;"				\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+	"bootcmd=run net_nfs\0"
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h
new file mode 100644
index 0000000..60d8a4b
--- /dev/null
+++ b/include/configs/woodburn_sd.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include "woodburn_common.h"
+
+/* Set TEXT in RAM */
+
+/*
+ * SPL
+ */
+
+#define CONFIG_SPL_MAX_SIZE		(64 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
new file mode 100644
index 0000000..e260a63
--- /dev/null
+++ b/include/configs/work_92105.h
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * WORK Microwave work_92105 board configuration file
+ *
+ * (C) Copyright 2014  DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ */
+
+#ifndef __CONFIG_WORK_92105_H__
+#define __CONFIG_WORK_92105_H__
+
+/* SoC and board defines */
+#include <linux/sizes.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Define work_92105 machine type by hand -- done only for compatibility
+ * with original board code
+ */
+#define CONFIG_MACH_TYPE		736
+
+#if !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_SYS_MALLOC_LEN		SZ_1M
+#define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
+#define CONFIG_SYS_SDRAM_SIZE		SZ_128M
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + SZ_32K)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - SZ_1M)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_32K)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_512K \
+					 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_SYS_LPC32XX_UART		5   /* UART5 - NS16550 */
+
+/*
+ * Ethernet Driver
+ */
+
+#define CONFIG_PHY_SMSC
+#define CONFIG_LPC32XX_ETH
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
+
+/*
+ * I2C driver
+ */
+
+#define CONFIG_SYS_I2C_LPC32XX
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SPEED 350000
+
+/*
+ * I2C EEPROM
+ */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/*
+ * I2C RTC
+ */
+
+#define CONFIG_RTC_DS1374
+
+/*
+ * U-Boot General Configurations
+ */
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * NAND chip timings for FIXME: which one?
+ */
+
+#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY  333333333
+#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY   10000000
+#define CONFIG_LPC32XX_NAND_MLC_NAND_TA      18181818
+#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH      31250000
+#define CONFIG_LPC32XX_NAND_MLC_RD_LOW       45454545
+#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH      40000000
+#define CONFIG_LPC32XX_NAND_MLC_WR_LOW       83333333
+
+/*
+ * NAND
+ */
+
+/* driver configuration */
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_MAX_NAND_CHIPS 1
+#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
+#define CONFIG_NAND_LPC32XX_MLC
+
+/*
+ * GPIO
+ */
+
+#define CONFIG_LPC32XX_GPIO
+
+/*
+ * SSP/SPI/DISPLAY
+ */
+
+#define CONFIG_LPC32XX_SSP_TIMEOUT 100000
+/*
+ * Environment
+ */
+
+#define CONFIG_ENV_SIZE			0x00020000
+#define CONFIG_ENV_OFFSET		0x00100000
+#define CONFIG_ENV_OFFSET_REDUND	0x00120000
+#define CONFIG_ENV_ADDR			0x80000100
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_LOADADDR			0x80008000
+
+/*
+ * SPL
+ */
+
+/* SPL will be executed at offset 0 */
+/* SPL will use SRAM as stack */
+#define CONFIG_SPL_STACK     0x0000FFF8
+/* Use the framework and generic lib */
+/* SPL will use serial */
+/* SPL will load U-Boot from NAND offset 0x40000 */
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS  0x00040000
+#define CONFIG_SPL_PAD_TO 0x20000
+/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
+#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST   CONFIG_SYS_TEXT_BASE
+
+/*
+ * Include SoC specific configuration
+ */
+#include <asm/arch/config.h>
+
+#endif  /* __CONFIG_WORK_92105_H__*/
diff --git a/include/configs/x530.h b/include/configs/x530.h
new file mode 100644
index 0000000..2269d1e
--- /dev/null
+++ b/include/configs/x530.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Allied Telesis Labs
+ */
+
+#ifndef _CONFIG_X530_H
+#define _CONFIG_X530_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#if !defined(CONFIG_DM_SERIAL)
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_COM1		MV_UART_CONSOLE_BASE
+#endif
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/*Console on UART0 */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_PCI
+
+/* NAND */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define BBT_CUSTOM_SCAN
+#define BBT_CUSTOM_SCAN_PAGE 0
+#define BBT_CUSTOM_SCAN_POSITION 2048
+
+/* SPI NOR flash default params, used by sf commands */
+
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)"
+#define MTDPARTS_MTDOOPS		"errlog"
+
+/* Partition support */
+
+/* Additional FS support/configuration */
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* NAND */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)
+
+#include <asm/arch/config.h>
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* Keep device tree and initrd in low memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0x10000000\0"		\
+	"initrd_high=0x10000000\0"
+
+#define CONFIG_SYS_LOAD_ADDR	0x1000000
+#define CONFIG_UBI_PART			user
+#define CONFIG_UBIFS_VOLUME		user
+
+/* SPL */
+
+/* Defines for SPL */
+#define CONFIG_SPL_SIZE			(140 << 10)
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x0030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + CONFIG_SPL_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+/* SPL related SPI defines */
+#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
+
+#endif /* _CONFIG_X530_H */
diff --git a/include/configs/x600.h b/include/configs/x600.h
new file mode 100644
index 0000000..d4bbdcd
--- /dev/null
+++ b/include/configs/x600.h
@@ -0,0 +1,238 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
+ * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
+ *
+ * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SPEAR600				/* SPEAr600 SoC */
+#define CONFIG_X600				/* on X600 board */
+
+#include <asm/arch/hardware.h>
+
+/* Timer, HZ specific defines */
+#define CONFIG_SYS_HZ_CLOCK			8300000
+
+#define CONFIG_SYS_FLASH_BASE			0xf8000000
+/* Reserve 8KiB for SPL */
+#define CONFIG_SPL_PAD_TO			8192	/* decimal for 'dd' */
+#define CONFIG_SYS_SPL_LEN			CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_UBOOT_BASE			(CONFIG_SYS_FLASH_BASE + \
+						 CONFIG_SYS_SPL_LEN)
+#define CONFIG_SYS_UBOOT_START			CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN			0x60000
+
+/* Serial Configuration (PL011) */
+#define CONFIG_SYS_SERIAL0			0xD0000000
+#define CONFIG_SYS_SERIAL1			0xD0080000
+#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1 }
+#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
+						  57600, 115200 }
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* NOR FLASH config options */
+#define CONFIG_ST_SMI
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
+#define CONFIG_SYS_FLASH_ADDR_BASE		{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT		128
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
+
+/* NAND FLASH config options */
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			CONFIG_FSMC_NAND_BASE
+#define CONFIG_MTD_ECC_SOFT
+#define CONFIG_SYS_FSMC_NAND_8BIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_ECC_BCH
+
+/* UBI/UBI config options */
+
+/* Ethernet config options */
+#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
+
+#define CONFIG_SPEAR_GPIO
+
+/* I2C config options */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_BASE			0xD0200000
+#define CONFIG_SYS_I2C_SPEED			400000
+#define CONFIG_SYS_I2C_SLAVE			0x02
+#define CONFIG_I2C_CHIPADDRESS			0x50
+
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/* FPGA config options */
+#define CONFIG_FPGA_COUNT	1
+
+/* USB EHCI options */
+#define CONFIG_USB_EHCI_SPEAR
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+
+/*
+ * U-Boot Environment placing definitions.
+ */
+#define CONFIG_ENV_SECT_SIZE			0x00010000
+#define CONFIG_ENV_ADDR				(CONFIG_SYS_MONITOR_BASE + \
+						 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE				0x02000
+#define CONFIG_ENV_ADDR_REDUND			(CONFIG_ENV_ADDR + \
+						 CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND			(CONFIG_ENV_SIZE)
+
+/* Miscellaneous configurable options */
+#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#define CONFIG_SYS_MEMTEST_START		0x00800000
+#define CONFIG_SYS_MEMTEST_END			0x04000000
+#define CONFIG_SYS_MALLOC_LEN			(8 << 20)
+#define CONFIG_SYS_LOAD_ADDR			0x00800000
+
+#define CONFIG_HOSTNAME				"x600"
+#define CONFIG_UBI_PART				ubi0
+#define CONFIG_UBIFS_VOLUME			rootfs
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr=1000000\0"						\
+	"u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0"		\
+	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};"					\
+		"erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
+		"cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
+		" ${filesize};"						\
+		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize}\0"					\
+	"upd=run load update\0"						\
+	"ubifs=" CONFIG_HOSTNAME "/ubifs.img\0"		\
+	"part=" __stringify(CONFIG_UBI_PART) "\0"			\
+	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"			\
+	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
+	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
+		" ${filesize}\0"					\
+	"upd_ubifs=run load_ubifs update_ubifs\0"			\
+	"init_ubifs=nand erase.part ubi0;ubi part ${part};"		\
+		"ubi create ${vol} 4000000\0"				\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk-4.2/arm\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"boot_part=0\0"							\
+	"altbootcmd=if test $boot_part -eq 0;then "			\
+			"echo Switching to partition 1!;"		\
+			"setenv boot_part 1;"				\
+		"else; "						\
+			"echo Switching to partition 0!;"		\
+			"setenv boot_part 0;"				\
+		"fi;"							\
+		"saveenv;boot\0"					\
+	"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} "		\
+		"root=ubi0:rootfs rootfstype=ubifs\0"			\
+	"kernel=" CONFIG_HOSTNAME "/uImage\0"		\
+	"kernel_fs=/boot/uImage \0"					\
+	"kernel_addr=1000000\0"						\
+	"dtb=" CONFIG_HOSTNAME "/"				\
+		CONFIG_HOSTNAME ".dtb\0"			\
+	"dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0"		\
+	"dtb_addr=1800000\0"						\
+	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
+	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcon=setenv bootargs ${bootargs} console=ttyAMA0,"		\
+		"${baudrate}\0"						\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"net_nfs=run load_dtb load_kernel; "				\
+		"run nfsargs addip addcon addmtd addmisc;"		\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"				\
+	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"		\
+		" addcon addmisc addmtd;"				\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0"	\
+	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"		\
+		"ubifsload ${dtb_addr} ${dtb_fs};\0"			\
+	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon "	\
+		"addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0"	\
+	"bootcmd=run nand_ubifs\0"					\
+	"\0"
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1				0x00000000
+#define PHYS_SDRAM_1_MAXSIZE			0x40000000
+
+#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
+#define CONFIG_SRAM_BASE			0xd2800000
+/* Preserve the last 2 lwords for the boot-counter */
+#define CONFIG_SRAM_SIZE			((8 << 10) - 0x8)
+#define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET		\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR			\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * SPL related defines
+ */
+#define CONFIG_SPL_MAX_SIZE		(CONFIG_SRAM_SIZE - 0xb00)
+#define	CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/spear"
+
+/*
+ * Please select/define only one of the following
+ * Each definition corresponds to a supported DDR chip.
+ * DDR configuration is based on the following selection
+ */
+#define CONFIG_DDR_MT47H64M16		1
+#define CONFIG_DDR_MT47H32M16		0
+#define CONFIG_DDR_MT47H128M8		0
+
+/*
+ * Synchronous/Asynchronous operation of DDR
+ *
+ * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
+ * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
+ * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
+ */
+#define CONFIG_DDR_2HCLK		1
+#define CONFIG_DDR_HCLK			0
+#define CONFIG_DDR_PLL2			0
+
+/*
+ * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
+ * or not. Modify/Add to only these macros to define new boot types
+ */
+#define USB_BOOT_SUPPORTED		0
+#define PCIE_BOOT_SUPPORTED		0
+#define SNOR_BOOT_SUPPORTED		1
+#define NAND_BOOT_SUPPORTED		1
+#define PNOR_BOOT_SUPPORTED		0
+#define TFTP_BOOT_SUPPORTED		0
+#define UART_BOOT_SUPPORTED		0
+#define SPI_BOOT_SUPPORTED		0
+#define I2C_BOOT_SUPPORTED		0
+#define MMC_BOOT_SUPPORTED		0
+
+#endif  /* __CONFIG_H */
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
new file mode 100644
index 0000000..5a33223
--- /dev/null
+++ b/include/configs/x86-chromebook.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#ifndef _X86_CHROMEBOOK_H
+#define _X86_CHROMEBOOK_H
+
+#define CONFIG_SYS_MONITOR_LEN			(1 << 20)
+
+#define CONFIG_X86_MRC_ADDR			0xfffa0000
+#define CONFIG_X86_REFCODE_ADDR			0xffea0000
+#define CONFIG_X86_REFCODE_RUN_ADDR		0
+
+#define CONFIG_PCI_MEM_BUS	0xe0000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_PREF_BUS	0xd0000000
+#define CONFIG_PCI_PREF_PHYS	CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x1000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0xefff
+
+#define CONFIG_BIOSEMU
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x003f8000
+
+#define CONFIG_STD_DEVICES_SETTINGS	"stdin=usbkbd,i8042-kbd,serial\0" \
+					"stdout=vidconsole,serial\0" \
+					"stderr=vidconsole,serial\0"
+
+#endif
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
new file mode 100644
index 0000000..54214f9
--- /dev/null
+++ b/include/configs/x86-common.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ */
+
+#include <asm/ibmpc.h>
+
+#ifndef __CONFIG_X86_COMMON_H
+#define __CONFIG_X86_COMMON_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PHYSMEM
+
+#define CONFIG_LMB
+
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+/* SATA AHCI storage */
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LBA48
+#define CONFIG_SYS_64BIT_LBA
+
+#endif
+
+/* Generic TPM interfaced through LPC bus */
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock Configuration
+ */
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
+#define CONFIG_SYS_ISA_IO      CONFIG_SYS_ISA_IO_BASE_ADDRESS
+
+/*-----------------------------------------------------------------------
+ * Serial Configuration
+ */
+#define CONFIG_SYS_NS16550_PORT_MAPPED
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+
+#ifndef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND	\
+	"ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE			115200
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE			512
+
+#define CONFIG_SYS_MEMTEST_START		0x00100000
+#define CONFIG_SYS_MEMTEST_END			0x01000000
+#define CONFIG_SYS_LOAD_ADDR			0x20000000
+
+/*-----------------------------------------------------------------------
+ * CPU Features
+ */
+
+#define CONFIG_SYS_STACK_SIZE			(32 * 1024)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN			0x200000
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * Environment configuration
+ */
+#define CONFIG_ENV_SIZE			0x01000
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ */
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/*-----------------------------------------------------------------------
+ * USB configuration
+ */
+
+#define CONFIG_TFTP_TSIZE
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Default environment */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_HOSTNAME		"x86"
+#define CONFIG_BOOTFILE		"bzImage"
+#define CONFIG_LOADADDR		0x1000000
+#define CONFIG_RAMDISK_ADDR	0x4000000
+#if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB)
+#define CONFIG_OTHBOOTARGS	"othbootargs=\0"
+#else
+#define CONFIG_OTHBOOTARGS	"othbootargs=acpi=off\0"
+#endif
+
+#if defined(CONFIG_DISTRO_DEFAULTS)
+#define DISTRO_BOOTENV		BOOTENV
+#else
+#define DISTRO_BOOTENV
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	DISTRO_BOOTENV					\
+	CONFIG_STD_DEVICES_SETTINGS			\
+	"pciconfighost=1\0"				\
+	"netdev=eth0\0"					\
+	"consoledev=ttyS0\0"				\
+	CONFIG_OTHBOOTARGS				\
+	"scriptaddr=0x7000000\0"			\
+	"kernel_addr_r=0x1000000\0"			\
+	"ramdisk_addr_r=0x4000000\0"			\
+	"ramdiskfile=initramfs.gz\0"
+
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftpboot $kernel_addr_r $bootfile;"		\
+	"tftpboot $ramdisk_addr_r $ramdiskfile;"	\
+	"zboot $kernel_addr_r 0 $ramdisk_addr_r $filesize"
+
+#define CONFIG_NFSBOOTCOMMAND				\
+	"setenv bootargs root=/dev/nfs rw "		\
+	"nfsroot=$serverip:$rootpath "			\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftpboot $kernel_addr_r $bootfile;"		\
+	"zboot $kernel_addr_r"
+
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h
new file mode 100644
index 0000000..afc4b82
--- /dev/null
+++ b/include/configs/xfi3.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ */
+#ifndef __CONFIGS_XFI3_H__
+#define __CONFIGS_XFI3_H__
+
+/* U-Boot Commands */
+
+/* Memory configuration */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_ENV_OVERWRITE
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* LCD */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_FONT_4X6
+#define CONFIG_VIDEO_MXS_MODE_SYSTEM
+#define CONFIG_SYS_BLACK_IN_WRITE
+#define LCD_BPP	LCD_COLOR16
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_NETCONSOLE
+#endif
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif	/* __CONFIGS_XFI3_H__ */
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
new file mode 100644
index 0000000..f426127
--- /dev/null
+++ b/include/configs/xilinx_versal.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Xilinx Versal
+ * (C) Copyright 2016 - 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * Based on Configuration for Xilinx ZynqMP
+ */
+
+#ifndef __XILINX_VERSAL_H
+#define __XILINX_VERSAL_H
+
+#define CONFIG_REMAKE_ELF
+
+/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE	0xF9000000
+#define GICR_BASE	0xF9080000
+
+#define CONFIG_SYS_MEMTEST_SCRATCH	0xfffc0000
+
+#define CONFIG_SYS_MEMTEST_START	0
+#define CONFIG_SYS_MEMTEST_END		1000
+
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
+#if CONFIG_COUNTER_FREQUENCY
+# define COUNTER_FREQUENCY	CONFIG_COUNTER_FREQUENCY
+#endif
+
+/* Serial setup */
+#define CONFIG_ARM_DCC
+#define CONFIG_CPU_ARMV8
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{ 4800, 9600, 19200, 38400, 57600, 115200 }
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_MAY_FAIL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR		0x8000000
+
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS		64
+
+#if defined(CONFIG_CMD_DFU)
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x1800000
+#define DFU_DEFAULT_POLL_TIMEOUT	300
+#define CONFIG_THOR_RESET_OFF
+#define DFU_ALT_INFO_RAM \
+	"dfu_ram_info=" \
+	"setenv dfu_alt_info " \
+	"Image ram $kernel_addr_r $kernel_size_r\\\\;" \
+	"system.dtb ram $fdt_addr_r $fdt_size_r\0" \
+	"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
+	"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
+
+#define DFU_ALT_INFO  \
+		DFU_ALT_INFO_RAM
+#endif
+
+#if !defined(DFU_ALT_INFO)
+# define DFU_ALT_INFO
+#endif
+
+/* Ethernet driver */
+#if defined(CONFIG_ZYNQ_GEM)
+# define CONFIG_NET_MULTI
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define PHY_ANEG_TIMEOUT       20000
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
+
+#define CONFIG_CLOCKS
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"fdt_high=10000000\0" \
+	"fdt_addr_r=0x40000000\0" \
+	"fdt_size_r=0x400000\0" \
+	"pxefile_addr_r=0x10000000\0" \
+	"kernel_addr_r=0x18000000\0" \
+	"kernel_size_r=0x10000000\0" \
+	"scriptaddr=0x20000000\0" \
+	"ramdisk_addr_r=0x02100000\0" \
+	"script_offset_f=0x7F80000\0" \
+	"script_size_f=0x80000\0"
+
+#if defined(CONFIG_MMC_SDHCI_ZYNQ)
+# define BOOT_TARGET_DEVICES_MMC(func)	func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+# define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL)
+# define BOOT_TARGET_DEVICES_XSPI(func)	func(XSPI, xspi, 0)
+#else
+# define BOOT_TARGET_DEVICES_XSPI(func)
+#endif
+
+#define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \
+	"bootcmd_xspi0=sf probe 0 0 0 && " \
+	"sf read $scriptaddr $script_offset_f $script_size_f && " \
+	"source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \
+	"xspi "
+
+#define BOOT_TARGET_DEVICES_JTAG(func)	func(JTAG, jtag, na)
+
+#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
+	"bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
+	"jtag "
+
+#define BOOT_TARGET_DEVICES_DFU_USB(func)  func(DFU_USB, dfu_usb, 0)
+
+#define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \
+	"bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \
+	"$script_size_f; dfu 0 ram 0 && source $scriptaddr; " \
+	"echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \
+	"dfu_usb "
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_JTAG(func) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_XSPI(func) \
+	BOOT_TARGET_DEVICES_DFU_USB(func) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTENV \
+	DFU_ALT_INFO
+#endif
+
+#endif /* __XILINX_VERSAL_H */
diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h
new file mode 100644
index 0000000..ee305e0
--- /dev/null
+++ b/include/configs/xilinx_versal_mini.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for Xilinx Versal MINI configuration
+ *
+ * (C) Copyright 2018-2019 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ */
+
+#ifndef __CONFIG_VERSAL_MINI_H
+#define __CONFIG_VERSAL_MINI_H
+
+#define CONFIG_SYS_MEMTEST_SCRATCH     0xfffc0000
+
+#define CONFIG_EXTRA_ENV_SETTINGS
+
+#include <configs/xilinx_versal.h>
+
+/* Undef unneeded configs */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+#undef CONFIG_CMD_ENV
+
+/* BOOTP options */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_MAY_FAIL
+
+#undef CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_CBSIZE		1024
+
+#endif /* __CONFIG_VERSAL_MINI_H */
diff --git a/include/configs/xilinx_versal_mini_qspi.h b/include/configs/xilinx_versal_mini_qspi.h
new file mode 100644
index 0000000..8572b8b
--- /dev/null
+++ b/include/configs/xilinx_versal_mini_qspi.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for Xilinx Versal QSPI Flash utility
+ *
+ * (C) Copyright 2018-2019 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+#ifndef __CONFIG_VERSAL_MINI_QSPI_H
+#define __CONFIG_VERSAL_MINI_QSPI_H
+
+#include <configs/xilinx_versal_mini.h>
+
+#undef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_TEXT_BASE + 0x20000)
+
+#endif /* __CONFIG_VERSAL_MINI_QSPI_H */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
new file mode 100644
index 0000000..ee1ceeb
--- /dev/null
+++ b/include/configs/xilinx_zynqmp.h
@@ -0,0 +1,265 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Xilinx ZynqMP
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * Based on Configuration for Versatile Express
+ */
+
+#ifndef __XILINX_ZYNQMP_H
+#define __XILINX_ZYNQMP_H
+
+#define CONFIG_REMAKE_ELF
+
+/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
+
+/* Generic Interrupt Controller Definitions */
+#define CONFIG_GICV2
+#define GICD_BASE	0xF9010000
+#define GICC_BASE	0xF9020000
+
+#ifndef CONFIG_SYS_MEMTEST_SCRATCH
+# define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0
+#define CONFIG_SYS_MEMTEST_END		1000
+
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
+#if !defined(COUNTER_FREQUENCY)
+# define COUNTER_FREQUENCY		100000000
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x2000000)
+
+/* Serial setup */
+#define CONFIG_ARM_DCC
+#define CONFIG_CPU_ARMV8
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{ 4800, 9600, 19200, 38400, 57600, 115200 }
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_MAY_FAIL
+
+#ifdef CONFIG_NAND_ARASAN
+# define CONFIG_SYS_MAX_NAND_DEVICE	1
+# define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+#define CONFIG_ZYNQMP_PSU_INIT_ENABLED
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR		0x8000000
+
+#if defined(CONFIG_ZYNQMP_USB)
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x1800000
+#define DFU_DEFAULT_POLL_TIMEOUT	300
+#define CONFIG_THOR_RESET_OFF
+#define DFU_ALT_INFO_RAM \
+	"dfu_ram_info=" \
+	"setenv dfu_alt_info " \
+	"Image ram $kernel_addr $kernel_size\\\\;" \
+	"system.dtb ram $fdt_addr $fdt_size\0" \
+	"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
+	"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
+
+#define DFU_ALT_INFO  \
+		DFU_ALT_INFO_RAM
+
+#ifndef CONFIG_SPL_BUILD
+# define PARTS_DEFAULT \
+	"partitions=uuid_disk=${uuid_gpt_disk};" \
+	"name=""boot"",size=16M,uuid=${uuid_gpt_boot};" \
+	"name=""Linux"",size=-M,uuid=${uuid_gpt_Linux}\0"
+#endif
+#endif
+
+#if !defined(DFU_ALT_INFO)
+# define DFU_ALT_INFO
+#endif
+
+#if !defined(PARTS_DEFAULT)
+# define PARTS_DEFAULT
+#endif
+
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_MAXARGS		64
+
+/* Ethernet driver */
+#if defined(CONFIG_ZYNQ_GEM)
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define PHY_ANEG_TIMEOUT       20000
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
+
+#define CONFIG_CLOCKS
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"fdt_high=10000000\0" \
+	"fdt_addr_r=0x40000000\0" \
+	"pxefile_addr_r=0x10000000\0" \
+	"kernel_addr_r=0x18000000\0" \
+	"scriptaddr=0x20000000\0" \
+	"ramdisk_addr_r=0x02100000\0" \
+	"script_offset_f=0x3e80000\0" \
+	"script_size_f=0x80000\0" \
+
+#if defined(CONFIG_MMC_SDHCI_ZYNQ)
+# define BOOT_TARGET_DEVICES_MMC(func)	func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+# define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#if defined(CONFIG_SATA_CEVA)
+# define BOOT_TARGET_DEVICES_SCSI(func)	func(SCSI, scsi, 0)
+#else
+# define BOOT_TARGET_DEVICES_SCSI(func)
+#endif
+
+#if defined(CONFIG_ZYNQMP_USB)
+# define BOOT_TARGET_DEVICES_USB(func)	func(USB, usb, 0) func(USB, usb, 1)
+#else
+# define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
+# define BOOT_TARGET_DEVICES_PXE(func)	func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#if defined(CONFIG_CMD_DHCP)
+# define BOOT_TARGET_DEVICES_DHCP(func)	func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
+#if defined(CONFIG_ZYNQMP_GQSPI)
+# define BOOT_TARGET_DEVICES_QSPI(func)	func(QSPI, qspi, 0)
+#else
+# define BOOT_TARGET_DEVICES_QSPI(func)
+#endif
+
+#if defined(CONFIG_NAND_ARASAN)
+# define BOOT_TARGET_DEVICES_NAND(func)	func(NAND, nand, 0)
+#else
+# define BOOT_TARGET_DEVICES_NAND(func)
+#endif
+
+#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \
+		       "sf read $scriptaddr $script_offset_f $script_size_f && " \
+		       "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "= nand info && " \
+		       "nand read $scriptaddr $script_offset_f $script_size_f && " \
+		       "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES_JTAG(func)	func(JTAG, jtag, na)
+
+#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \
+	"bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
+	"jtag "
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_JTAG(func) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_QSPI(func) \
+	BOOT_TARGET_DEVICES_NAND(func) \
+	BOOT_TARGET_DEVICES_USB(func) \
+	BOOT_TARGET_DEVICES_SCSI(func) \
+	BOOT_TARGET_DEVICES_PXE(func) \
+	BOOT_TARGET_DEVICES_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTENV \
+	DFU_ALT_INFO
+#endif
+
+/* SPL can't handle all huge variables - define just DFU */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU)
+#undef CONFIG_EXTRA_ENV_SETTINGS
+# define CONFIG_EXTRA_ENV_SETTINGS \
+	"dfu_alt_info_ram=uboot.bin ram 0x8000000 0x1000000;" \
+			  "atf-uboot.ub ram 0x10000000 0x1000000;" \
+			  "Image ram 0x80000 0x3f80000;" \
+			  "system.dtb ram 0x4000000 0x100000\0" \
+	"dfu_bufsiz=0x1000\0"
+#endif
+
+#define CONFIG_SPL_STACK		0xfffffffc
+#define CONFIG_SPL_MAX_SIZE		0x40000
+
+/* Just random location in OCM */
+#define CONFIG_SPL_BSS_START_ADDR	0x0
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
+# define CONFIG_SYS_SPI_KERNEL_OFFS	0x80000
+# define CONFIG_SYS_SPI_ARGS_OFFS	0xa0000
+# define CONFIG_SYS_SPI_ARGS_SIZE	0xa0000
+#endif
+
+/* u-boot is like dtb */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"u-boot.bin"
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x8000000
+
+/* ATF is my kernel image */
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"atf-uboot.ub"
+
+/* FIT load address for RAM boot */
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	0x10000000
+
+/* MMC support */
+#ifdef CONFIG_MMC_SDHCI_ZYNQ
+# define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0 /* unused */
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0 /* unused */
+# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0 /* unused */
+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+#endif
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU)
+# undef CONFIG_CMD_BOOTD
+# define CONFIG_SPL_ENV_SUPPORT
+# define CONFIG_SPL_HASH_SUPPORT
+# define CONFIG_ENV_MAX_ENTRIES	10
+#endif
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x20000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
+# error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#endif /* __XILINX_ZYNQMP_H */
diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h
new file mode 100644
index 0000000..a692289
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_mini.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Xilinx ZynqMP Flash utility
+ *
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+#ifndef __CONFIG_ZYNQMP_MINI_H
+#define __CONFIG_ZYNQMP_MINI_H
+
+#define CONFIG_SYS_MEMTEST_SCRATCH     0xfffc0000
+
+#define CONFIG_EXTRA_ENV_SETTINGS
+
+#include <configs/xilinx_zynqmp.h>
+
+/* Undef unneeded configs */
+#undef CONFIG_BOOTCOMMAND
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_SYS_MALLOC_LEN
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+#undef CONFIG_CMD_ENV
+#undef CONFIG_SYS_INIT_SP_ADDR
+
+/* BOOTP options */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_MAY_FAIL
+
+#endif /* __CONFIG_ZYNQMP_MINI_H */
diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h b/include/configs/xilinx_zynqmp_mini_emmc.h
new file mode 100644
index 0000000..a7ae30d
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_mini_emmc.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Xilinx ZynqMP eMMC Flash utility
+ *
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+#ifndef __CONFIG_ZYNQMP_MINI_EMMC_H
+#define __CONFIG_ZYNQMP_MINI_EMMC_H
+
+#include <configs/xilinx_zynqmp_mini.h>
+
+#define CONFIG_SYS_INIT_SP_ADDR	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN	0x800000
+
+#endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */
diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h
new file mode 100644
index 0000000..692f6e5
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_mini_nand.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Xilinx ZynqMP Nand Flash utility
+ *
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+#ifndef __CONFIG_ZYNQMP_MINI_NAND_H
+#define __CONFIG_ZYNQMP_MINI_NAND_H
+
+#include <configs/xilinx_zynqmp_mini.h>
+
+#define CONFIG_SYS_SDRAM_SIZE	0x1000000
+#define CONFIG_SYS_SDRAM_BASE	0x0
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x40000)
+#define CONFIG_SYS_MALLOC_LEN		0x800000
+
+#endif /* __CONFIG_ZYNQMP_MINI_NAND_H */
diff --git a/include/configs/xilinx_zynqmp_mini_qspi.h b/include/configs/xilinx_zynqmp_mini_qspi.h
new file mode 100644
index 0000000..129af6e
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_mini_qspi.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Xilinx ZynqMP QSPI Flash utility
+ *
+ * (C) Copyright 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+#ifndef __CONFIG_ZYNQMP_MINI_QSPI_H
+#define __CONFIG_ZYNQMP_MINI_QSPI_H
+
+#include <configs/xilinx_zynqmp_mini.h>
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_TEXT_BASE + 0x20000)
+#define CONFIG_SYS_MALLOC_LEN	0x2000
+
+#endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */
diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h
new file mode 100644
index 0000000..4eb3312
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_r5.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
+ */
+
+#ifndef __CONFIG_ZYNQMP_R5_H
+#define __CONFIG_ZYNQMP_R5_H
+
+#define CONFIG_EXTRA_ENV_SETTINGS
+
+/* CPU clock */
+#define CONFIG_CPU_FREQ_HZ	500000000
+
+/* Serial drivers */
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+# define CONFIG_ENV_SIZE	(128 << 10)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Boot configuration */
+#define CONFIG_SYS_LOAD_ADDR		0 /* default? */
+
+#define CONFIG_SYS_MAXARGS		32 /* max number of command args */
+
+#define CONFIG_SYS_MALLOC_LEN		0x1400000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
+
+#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* 0x0 - 0x40 is used for placing exception vectors */
+#define CONFIG_SYS_MEMTEST_START	0x40
+#define CONFIG_SYS_MEMTEST_END		0x100
+#define CONFIG_SYS_MEMTEST_SCRATCH	0
+
+#endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
new file mode 100644
index 0000000..23f0389
--- /dev/null
+++ b/include/configs/xpedite517x.h
@@ -0,0 +1,650 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * xpedite517x board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SYS_BOARD_NAME	"XPedite5170"
+#define CONFIG_SYS_FORM_3U_VPX	1
+#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
+#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
+#define CONFIG_ALTIVEC		1
+
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+/*
+ * DDR config
+ */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
+#define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
+#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
+
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xe0000000
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC86xx */
+
+/*
+ * L2CR setup
+ */
+#define CONFIG_SYS_L2
+#define L2_INIT		0
+#define L2_ENABLE	(L2CR_L2E)
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR		0xef000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+#define CONFIG_SYS_IMMR			CONFIG_SYS_CCSRBAR
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY |\
+					 CONFIG_SYS_POST_I2C)
+/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
+#define I2C_ADDR_IGNORE_LIST		{0x50}
+
+/*
+ * Memory map
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
+ * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
+ * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
+ * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
+ * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_4 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000	/* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST 	{CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_NAND_ACTL
+#define CONFIG_SYS_NAND_ACTL_ALE 	(1 << 14)	/* C_LA14 */
+#define CONFIG_SYS_NAND_ACTL_CLE 	(1 << 15)	/* C_LA15 */
+#define CONFIG_SYS_NAND_ACTL_NCE	0		/* NCE not controlled by ADDR */
+#define CONFIG_SYS_NAND_ACTL_DELAY	25
+#define CONFIG_JFFS2_NAND
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xf8000000
+#define CONFIG_SYS_FLASH_BASE2		0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff00000, 0xc0000}, \
+						  {0xf7f00000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY	0xfff00000	/* early monitor loc */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	|\
+				 BR_PS_16		|\
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		|\
+				 OR_GPCM_CSNT		|\
+				 OR_GPCM_XACS		|\
+				 OR_GPCM_ACS_DIV2	|\
+				 OR_GPCM_SCY_8		|\
+				 OR_GPCM_TRLX		|\
+				 OR_GPCM_EHTR		|\
+				 OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	|\
+				 BR_PS_16		|\
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	|\
+				 BR_PS_8		|\
+				 BR_V)
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		|\
+				 OR_GPCM_BCTLD		|\
+				 OR_GPCM_CSNT		|\
+				 OR_GPCM_ACS_DIV4	|\
+				 OR_GPCM_SCY_4		|\
+				 OR_GPCM_TRLX		|\
+				 OR_GPCM_EHTR)
+
+/* Optional NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	|\
+				 BR_PS_8		|\
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	100000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	100000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* PEX8518 slave I2C interface */
+#define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
+
+/* I2C DS1631 temperature sensor */
+#define CONFIG_SYS_I2C_LM90_ADDR	0x4c
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
+#define CONFIG_SYS_I2C_PCA9553_ADDR	0x62
+
+/*
+ * PU = pulled high, PD = pulled low
+ * I = input, O = output, IO = input/output
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
+
+/* PCA9557 @ 0x1c*/
+#define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
+#define CONFIG_SYS_PCA953X_PLUG_GPIO0		0x02 /* Samtec connector GPIO */
+#define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
+#define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
+#define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
+#define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
+#define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
+#define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; VPX Geographical address parity */
+#define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; VPX P1 SYSCON */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_VPX_GPIO0		0x01 /* PU; VPX P15 GPIO */
+#define CONFIG_SYS_PCA953X_VPX_GPIO1		0x02 /* PU; VPX P15 GPIO */
+#define CONFIG_SYS_PCA953X_VPX_GPIO2		0x04 /* PU; VPX P15 GPIO */
+#define CONFIG_SYS_PCA953X_VPX_GPIO3		0x08 /* PU; VPX P15 GPIO */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* PCIE1 - PEX8518 */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+/* PCIE2 - VPX P1 */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+/*
+ * BAT mappings
+ */
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL	(CONFIG_SYS_CCSRBAR_DEFAULT	|\
+					 BATL_PP_RW			|\
+					 BATL_CACHEINHIBIT		|\
+					 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU	(CONFIG_SYS_CCSRBAR_DEFAULT	|\
+					 BATU_BL_1M			|\
+					 BATU_VS			|\
+					 BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL	(CONFIG_SYS_CCSRBAR_DEFAULT	|\
+					 BATL_PP_RW			|\
+					 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU	CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
+/*
+ * BAT0		2G	Cacheable, non-guarded
+ * 0x0000_0000	2G	DDR
+ */
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
+
+/*
+ * BAT1		1G	Cache-inhibited, guarded
+ * 0x8000_0000	1G	PCI-Express 1 Memory
+ */
+#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCIE1_MEM_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCIE1_MEM_PHYS	|\
+				 BATU_BL_1G			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCIE1_MEM_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
+
+/*
+ * BAT2		512M	Cache-inhibited, guarded
+ * 0xc000_0000	512M	PCI-Express 2 Memory
+ */
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCIE2_MEM_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE2_MEM_PHYS	|\
+				 BATU_BL_512M			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCIE2_MEM_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+
+/*
+ * BAT3		1M	Cache-inhibited, guarded
+ * 0xe000_0000	1M	CCSR
+ */
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR		|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR		|\
+				 BATU_BL_1M			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR		|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
+
+/*
+ * BAT4		32M	Cache-inhibited, guarded
+ * 0xe200_0000	16M	PCI-Express 1 I/O
+ * 0xe300_0000	16M	PCI-Express 2 I/0
+ */
+#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE1_IO_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_PHYS	|\
+				 BATU_BL_32M			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE1_IO_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
+
+/*
+ * BAT5		128K	Cacheable, non-guarded
+ * 0xe400_1000	128K	Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR	|\
+				 BATL_PP_RW			|\
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR	|\
+				 BATU_BL_128K			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
+
+/*
+ * BAT6		256M	Cache-inhibited, guarded
+ * 0xf000_0000	256M	FLASH
+ */
+#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE2		|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE		|\
+				 BATU_BL_256M			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE		|\
+				 BATL_PP_RW			|\
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE			|\
+				 BATU_BL_1M			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY	|\
+				 BATL_PP_RW			|\
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
+/*
+ * BAT7		64M	Cache-inhibited, guarded
+ * 0xe800_0000	64K	NAND FLASH
+ * 0xe804_0000	128K	DUART Registers
+ */
+#define CONFIG_SYS_DBAT7L	(CONFIG_SYS_NAND_BASE		|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U 	(CONFIG_SYS_NAND_BASE		|\
+				 BATU_BL_512K			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_NAND_BASE		|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * Flash memory map:
+ * fffc0000 - ffffffff	Pri FDT (256KB)
+ * fff80000 - fffbffff	Pri U-Boot Environment (256 KB)
+ * fff00000 - fff7ffff	Pri U-Boot (512 KB)
+ * fef00000 - ffefffff	Pri OS image (16MB)
+ * f8000000 - feefffff	Pri OS Use/Filesystem (111MB)
+ *
+ * f7fc0000 - f7ffffff	Sec FDT (256KB)
+ * f7f80000 - f7fbffff	Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f7ffff	Sec U-Boot (512 KB)
+ * f6f00000 - f7efffff	Sec OS image (16MB)
+ * f0000000 - f6efffff	Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff00000)
+#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f00000)
+#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfffc0000)
+#define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7fc0000)
+#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=0x1e00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
new file mode 100644
index 0000000..21e91ee
--- /dev/null
+++ b/include/configs/xpedite520x.h
@@ -0,0 +1,450 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004-2008 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * xpedite520x board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SYS_BOARD_NAME	"XPedite5200"
+#define CONFIG_SYS_FORM_PMC_XMC	1
+
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCI1		1	/* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+/*
+ * DDR config
+ */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS		0x54
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_SYS_CCSRBAR		0xef000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
+					 CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_MAX1237_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
+					 CONFIG_SYS_I2C_RTC_ADDR}
+
+/*
+ * Memory map
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
+ * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
+ * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_ACTL
+#define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
+#define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
+#define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
+#define CONFIG_SYS_NAND_ACTL_DELAY	25
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_BASE2		0xf8000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xfbf40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
+				 OR_GPCM_ACS_DIV4	| \
+				 OR_GPCM_SCY_8)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 BR_PS_8		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
+				 OR_GPCM_BCTLD		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_ACS_DIV4	| \
+				 OR_GPCM_SCY_4		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 BR_PS_8		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x4000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11			1
+#define CONFIG_SYS_I2C_RTC_ADDR			0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR		2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
+#define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/* PCA957 @ 0x18 */
+#define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
+#define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
+#define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
+#define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
+#define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20
+#define CONFIG_SYS_PCA953X_MONARCH		0x40
+#define CONFIG_SYS_PCA953X_EREADY		0x80
+
+/* PCA957 @ 0x19 */
+#define CONFIG_SYS_PCA953X_P14_IO0		0x01
+#define CONFIG_SYS_PCA953X_P14_IO1		0x02
+#define CONFIG_SYS_PCA953X_P14_IO2		0x04
+#define CONFIG_SYS_PCA953X_P14_IO3		0x08
+#define CONFIG_SYS_PCA953X_P14_IO4		0x10
+#define CONFIG_SYS_PCA953X_P14_IO5		0x20
+#define CONFIG_SYS_PCA953X_P14_IO6		0x40
+#define CONFIG_SYS_PCA953X_P14_IO7		0x80
+
+/* 12-bit ADC used to measure CPU diode */
+#define CONFIG_SYS_I2C_MAX1237_ADDR		0x34
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define TSEC3_FLAGS		TSEC_GIGABIT
+#define TSEC3_PHY_ADDR		3
+#define TSEC3_PHYIDX		0
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_TSEC4	1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
+#define TSEC4_FLAGS		TSEC_GIGABIT
+#define TSEC4_PHY_ADDR		4
+#define TSEC4_PHYIDX		0
+#define CONFIG_HAS_ETH3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
+ *
+ * fbf80000 - fbffffff     Sec U-Boot (512 KB)
+ * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
+ * fbf00000 - fbf3ffff     Sec FDT (256KB)
+ * faf00000 - fbefffff     Sec OS image (16MB)
+ * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xfbf80000)
+#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	__stringify(0xfbf00000)
+#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	__stringify(0xfaf00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=0x1e00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
new file mode 100644
index 0000000..73e1fa3
--- /dev/null
+++ b/include/configs/xpedite537x.h
@@ -0,0 +1,500 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * xpedite537x board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SYS_BOARD_NAME	"XPedite5370"
+#define CONFIG_SYS_FORM_3U_VPX	1
+
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+/*
+ * Multicore config
+ */
+#define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */
+
+/*
+ * DDR config
+ */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
+#define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
+#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_SYS_CCSRBAR		0xef000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
+					 CONFIG_SYS_POST_I2C)
+/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
+#define I2C_ADDR_IGNORE_LIST		{0x50}
+
+/*
+ * Memory map
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
+ * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
+ * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
+ * 0xee00_0000	0xee00_ffff	Boot page translation	4K non-cacheable
+ * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
+ * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
+					 CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_NAND_FSL_ELBC
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xf8000000
+#define CONFIG_SYS_FLASH_BASE2		0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xf7f40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_XACS		| \
+				 OR_GPCM_ACS_DIV2	| \
+				 OR_GPCM_SCY_8		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR		| \
+				 OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
+				 OR_FCM_PGS	| \
+				 OR_FCM_CSCT	| \
+				 OR_FCM_CST	| \
+				 OR_FCM_CHT	| \
+				 OR_FCM_SCY_1	| \
+				 OR_FCM_TRLX	| \
+				 OR_FCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* PEX8518 slave I2C interface */
+#define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
+
+/* I2C DS1631 temperature sensor */
+#define CONFIG_SYS_I2C_LM90_ADDR	0x4c
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/*
+ * PU = pulled high, PD = pulled low
+ * I = input, O = output, IO = input/output
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
+#define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
+#define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */
+
+/* PCA9557 @ 0x1c*/
+#define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
+#define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
+#define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
+#define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
+#define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
+#define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
+#define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
+#define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
+#define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
+#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* PCIE1 - VPX P1 */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+/* PCIE2 - PEX8518 */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_TBI
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_ETHPRIME		"eTSEC2"
+
+/*
+ * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
+ * 1000mbps SGMII link
+ */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+		TBICR_PHY_RESET \
+		| TBICR_FULL_DUPLEX \
+		| TBICR_SPEED1_SET \
+		)
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
+ *
+ * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
+ * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f3ffff     Sec FDT (256KB)
+ * f6f00000 - f7efffff     Sec OS image (16MB)
+ * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=0x1e00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
new file mode 100644
index 0000000..e5a41ab
--- /dev/null
+++ b/include/configs/xpedite550x.h
@@ -0,0 +1,498 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * xpedite550x board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SYS_BOARD_NAME	"XPedite5500"
+#define CONFIG_SYS_FORM_PMC_XMC	1
+#define CONFIG_PRPMC_PCI_ALIAS	"pci0"	/* Processor PMC interface on pci0 */
+
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (PEX8112 or XMC) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+/*
+ * Multicore config
+ */
+#define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */
+
+/*
+ * DDR config
+ */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS			0x54
+#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_SYS_CCSRBAR		0xef000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
+					 CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_LM75_ADDR,	\
+					 CONFIG_SYS_I2C_LM90_ADDR,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR2,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR3,	\
+					 CONFIG_SYS_I2C_RTC_ADDR}
+
+/*
+ * Memory map
+ * 0x0000_0000 0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000 0xbfff_ffff	PCIe1 Mem		1G non-cacheable
+ * 0xe000_0000 0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000 0xe87f_ffff	PCIe1 IO		8M non-cacheable
+ * 0xee00_0000 0xee00_ffff	Boot page translation	4K non-cacheable
+ * 0xef00_0000 0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000 0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf000_0000 0xf7ff_ffff	NOR Flash 2		128M non-cacheable
+ * 0xf800_0000 0xffff_ffff	NOR Flash 1		128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
+					 CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_NAND_FSL_ELBC
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xf8000000
+#define CONFIG_SYS_FLASH_BASE2		0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xf7f40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_XACS		| \
+				 OR_GPCM_ACS_DIV2	| \
+				 OR_GPCM_SCY_8		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR		| \
+				 OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
+				 OR_FCM_PGS	| \
+				 OR_FCM_CSCT	| \
+				 OR_FCM_CST	| \
+				 OR_FCM_CHT	| \
+				 OR_FCM_SCY_1	| \
+				 OR_FCM_TRLX	| \
+				 OR_FCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C DS7505 temperature sensor */
+#define CONFIG_SYS_I2C_LM75_ADDR	0x48
+
+/* I2C ADT7461 temperature sensor */
+#define CONFIG_SYS_I2C_LM90_ADDR	0x4C
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/*
+ * GPIO pin definitions, PU = pulled high, PD = pulled low
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Write protection (0: disabled, 1: enabled) */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_XMC_GA0		0x01 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_GA1		0x02 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_GA2		0x04 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_WAKE		0x10 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_BIST		0x20 /* Enable XMC BIST */
+#define CONFIG_SYS_PCA953X_PMC_EREADY		0x40 /* PU; PMC PCI eready */
+#define CONFIG_SYS_PCA953X_PMC_MONARCH		0x80 /* PMC monarch mode enable */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_MC_GPIO0		0x01 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO1		0x02 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO2		0x04 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO3		0x08 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO4		0x10 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO5		0x20 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO6		0x40 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO7		0x80 /* PU; */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1 - PEX8112 or XMC, depending on build option */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_TBI
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_ETHPRIME		"eTSEC2"
+
+/*
+ * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
+ * 1000mbps SGMII link
+ */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+		TBICR_PHY_RESET \
+		| TBICR_FULL_DUPLEX \
+		| TBICR_SPEED1_SET \
+		)
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3		1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_PHY_ADDR		3
+#define TSEC3_PHYIDX		0
+#define CONFIG_HAS_ETH2
+
+/*
+ * USB
+ */
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
+ *
+ * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
+ * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f3ffff     Sec FDT (256KB)
+ * f6f00000 - f7efffff     Sec OS image (16MB)
+ * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=0x1e00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/include/configs/xpress.h b/include/configs/xpress.h
new file mode 100644
index 0000000..4cbf8aa
--- /dev/null
+++ b/include/configs/xpress.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * Configuration settings for the CCV xPress board
+ */
+#ifndef __XPRESS_CONFIG_H
+#define __XPRESS_CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/mach-imx/gpio.h>
+
+/* SPL options */
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 << 20)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		MX6UL_UART7_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* I2C configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C4		/* enable I2C bus 4 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			(128 << 20)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment is in stored in the eMMC boot partition */
+#define CONFIG_ENV_SIZE			(16 << 10)
+#define CONFIG_ENV_OFFSET		(512 << 10)
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART		1	/* boot parition */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC2 */
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_ENET_DEV		0
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x0
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_UBOOT_SECTOR_START	0x2
+#define CONFIG_UBOOT_SECTOR_COUNT	0x3fe
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc6\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=undefined\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"uboot=ccv/u-boot.imx\0"					\
+	"uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0"	\
+	"uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0"		\
+	"update_uboot=if tftp ${uboot}; then "				\
+		"if itest ${filesize} > 0; then "			\
+			"mmc dev 0 1;"					\
+			"setexpr blkc ${filesize} / 0x200;"		\
+			"setexpr blkc ${blkc} + 1;"			\
+			"if itest ${blkc} <= ${uboot_size}; then "	\
+				"mmc write ${loadaddr} ${uboot_start} "	\
+					"${blkc};"			\
+			"fi;"						\
+		"fi; fi;"						\
+		"setenv filesize; setenv blkc\0"			\
+	"update_bootpart=mmc bootbus 0 2 1 2;mmc partconf 0 1 1 0\0"
+
+#endif /* __XPRESS_CONFIG_H */
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h
new file mode 100644
index 0000000..2f20273
--- /dev/null
+++ b/include/configs/xtfpga.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2007-2013 Tensilica, Inc.
+ * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/core.h>
+#include <asm/addrspace.h>
+#include <asm/config.h>
+
+/*
+ * The 'xtfpga' board describes a set of very similar boards with only minimal
+ * differences.
+ */
+
+/*=====================*/
+/* Board and Processor */
+/*=====================*/
+
+#define CONFIG_XTFPGA
+
+/* FPGA CPU freq after init */
+#define CONFIG_SYS_CLK_FREQ		(gd->cpu_clk)
+
+/*===================*/
+/* RAM Layout        */
+/*===================*/
+
+#if XCHAL_HAVE_PTP_MMU
+#define CONFIG_SYS_MEMORY_BASE		\
+	(XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
+#define CONFIG_SYS_IO_BASE		0xf0000000
+#else
+#define CONFIG_SYS_MEMORY_BASE		0x60000000
+#define CONFIG_SYS_IO_BASE		0x90000000
+#define CONFIG_MAX_MEM_MAPPED		0x10000000
+#endif
+
+/* Onboard RAM sizes:
+ *
+ * LX60		0x04000000		  64 MB
+ * LX110	0x03000000		  48 MB
+ * LX200	0x06000000		  96 MB
+ * ML605	0x18000000		 384 MB
+ * KC705	0x38000000		 896 MB
+ *
+ * noMMU configurations can only see first 256MB of onboard memory.
+ */
+
+#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
+#define CONFIG_SYS_SDRAM_SIZE		CONFIG_BOARD_SDRAM_SIZE
+#else
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		MEMADDR(0x00000000)
+
+/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
+#ifdef CONFIG_XTFPGA_LX60
+# define CONFIG_SYS_MONITOR_LEN		0x00020000	/* 128KB */
+#else
+# define CONFIG_SYS_MONITOR_LEN		0x00040000	/* 256KB */
+#endif
+
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* heap  256KB */
+
+/* Linux boot param area in RAM (used only when booting linux) */
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64  << 10)
+
+/* Memory test is destructive so default must not overlap vectors or U-Boot*/
+#define CONFIG_SYS_MEMTEST_START	MEMADDR(0x01000000)
+#define CONFIG_SYS_MEMTEST_END		MEMADDR(0x02000000)
+
+/* Load address for stand-alone applications.
+ * MEMADDR cannot be used here, because the definition needs to be
+ * a plain number as it's used as -Ttext argument for ld in standalone
+ * example makefile.
+ * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually.
+ */
+#if XCHAL_HAVE_PTP_MMU
+#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR
+#define CONFIG_STANDALONE_LOAD_ADDR	0x00800000
+#else
+#define CONFIG_STANDALONE_LOAD_ADDR	0xd0800000
+#endif
+#else
+#define CONFIG_STANDALONE_LOAD_ADDR	0x60800000
+#endif
+
+#if defined(CONFIG_MAX_MEM_MAPPED) && \
+	CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_MEMORY_SIZE		CONFIG_MAX_MEM_MAPPED
+#else
+#define CONFIG_SYS_MEMORY_SIZE		CONFIG_SYS_SDRAM_SIZE
+#endif
+
+#define XTENSA_SYS_TEXT_ADDR		\
+	(MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN)
+
+/* Used by tftpboot; env var 'loadaddr' */
+#define CONFIG_SYS_LOAD_ADDR		MEMADDR(0x02000000)
+
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+
+#define CONFIG_BOARD_POSTCLK_INIT
+
+#define CONFIG_BOOTFILE			"uImage"
+	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE		1024
+	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*==============================*/
+/* U-Boot autoboot configuration */
+/*==============================*/
+
+
+/*=========================================*/
+/* FPGA Registers (board info and control) */
+/*=========================================*/
+
+/*
+ * These assume FPGA bitstreams from Tensilica release RB and up. Earlier
+ * releases may not provide any/all of these registers or at these offsets.
+ * Some of the FPGA registers are broken down into bitfields described by
+ * SHIFT left amount and field WIDTH (bits), and also by a bitMASK.
+ */
+
+/* Date of FPGA bitstream build in binary coded decimal (BCD) */
+#define CONFIG_SYS_FPGAREG_DATE		IOADDR(0x0D020000)
+#define FPGAREG_MTH_SHIFT		24		/* BCD month 1..12 */
+#define FPGAREG_MTH_WIDTH		8
+#define FPGAREG_MTH_MASK		0xFF000000
+#define FPGAREG_DAY_SHIFT		16		/* BCD day 1..31 */
+#define FPGAREG_DAY_WIDTH		8
+#define FPGAREG_DAY_MASK		0x00FF0000
+#define FPGAREG_YEAR_SHIFT		0		/* BCD year 2001..9999*/
+#define FPGAREG_YEAR_WIDTH		16
+#define FPGAREG_YEAR_MASK		0x0000FFFF
+
+/* FPGA core clock frequency in Hz (also input to UART) */
+#define CONFIG_SYS_FPGAREG_FREQ	IOADDR(0x0D020004)	/* CPU clock frequency*/
+
+/*
+ * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
+ *   Bits 0..5 set the lower 6 bits of the default ethernet MAC.
+ *   Bit 6 is reserved for future use by Tensilica.
+ *   Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to
+ *   the base of flash * (when on/1) or to the base of RAM (when off/0).
+ */
+#define CONFIG_SYS_FPGAREG_DIPSW	IOADDR(0x0D02000C)
+#define FPGAREG_MAC_SHIFT		0	/* Ethernet MAC bits 0..5 */
+#define FPGAREG_MAC_WIDTH		6
+#define FPGAREG_MAC_MASK		0x3f
+#define FPGAREG_BOOT_SHIFT		7	/* Boot ROM addr mapping */
+#define FPGAREG_BOOT_WIDTH		1
+#define FPGAREG_BOOT_MASK		0x80
+#define FPGAREG_BOOT_RAM		0
+#define FPGAREG_BOOT_FLASH		(1<<FPGAREG_BOOT_SHIFT)
+
+/* Force hard reset of board by writing a code to this register */
+#define CONFIG_SYS_FPGAREG_RESET	IOADDR(0x0D020010) /* Reset board .. */
+#define CONFIG_SYS_FPGAREG_RESET_CODE	0x0000DEAD   /*  by writing this code */
+
+/*====================*/
+/* Serial Driver Info */
+/*====================*/
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_COM1		IOADDR(0x0D050020) /* Base address */
+
+/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*======================*/
+/* Ethernet Driver Info */
+/*======================*/
+
+#define CONFIG_ETHBASE			00:50:C2:13:6f:00
+#define CONFIG_SYS_ETHOC_BASE		IOADDR(0x0d030000)
+#define CONFIG_SYS_ETHOC_BUFFER_ADDR	IOADDR(0x0D800000)
+
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#ifdef CONFIG_XTFPGA_LX60
+# define CONFIG_SYS_FLASH_SIZE		0x0040000	/* 4MB */
+# define CONFIG_SYS_FLASH_SECT_SZ	0x10000		/* block size 64KB */
+# define CONFIG_SYS_FLASH_PARMSECT_SZ	0x2000		/* param size  8KB */
+# define CONFIG_SYS_FLASH_BASE		IOADDR(0x08000000)
+# define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#elif defined(CONFIG_XTFPGA_KC705)
+# define CONFIG_SYS_FLASH_SIZE		0x8000000	/* 128MB */
+# define CONFIG_SYS_FLASH_SECT_SZ	0x20000		/* block size 128KB */
+# define CONFIG_SYS_FLASH_PARMSECT_SZ	0x8000		/* param size 32KB */
+# define CONFIG_SYS_FLASH_BASE		IOADDR(0x00000000)
+# define CONFIG_SYS_MONITOR_BASE	IOADDR(0x06000000)
+#else
+# define CONFIG_SYS_FLASH_SIZE		0x1000000	/* 16MB */
+# define CONFIG_SYS_FLASH_SECT_SZ	0x20000		/* block size 128KB */
+# define CONFIG_SYS_FLASH_PARMSECT_SZ	0x8000		/* param size 32KB */
+# define CONFIG_SYS_FLASH_BASE		IOADDR(0x08000000)
+# define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#endif
+#define CONFIG_SYS_MAX_FLASH_SECT	\
+	(CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \
+	 CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1)
+
+/*
+ * Put environment in top block (64kB)
+ * Another option would be to put env. in 2nd param block offs 8KB, size 8KB
+ */
+#define CONFIG_ENV_OFFSET    (CONFIG_SYS_FLASH_SIZE - CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SIZE	     CONFIG_SYS_FLASH_SECT_SZ
+
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h
new file mode 100644
index 0000000..77ff047
--- /dev/null
+++ b/include/configs/zc5202.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * Configuration settings for the E+L i.MX6Q DO82 board.
+ */
+
+#ifndef __EL_ZC5202_H
+#define __EL_ZC5202_H
+
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+#define CONSOLE_DEV		"ttymxc1"
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"
+
+#include "el6x_common.h"
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE				ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE			MII100
+#define CONFIG_ETHPRIME				"FEC"
+#define CONFIG_FEC_MXC_PHYADDR			0
+#define CONFIG_MV88E6352_SWITCH
+
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+
+#endif                         /*__EL6Q_CONFIG_H */
diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h
new file mode 100644
index 0000000..e4fe7a4
--- /dev/null
+++ b/include/configs/zc5601.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Stefano Babic <sbabic@denx.de>
+ *
+ * Configuration settings for the E+L i.MX6Q DO82 board.
+ */
+
+#ifndef __EL_ZC5601_H
+#define __EL_ZC5601_H
+
+
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+#define CONSOLE_DEV		"ttymxc1"
+#define CONFIG_MMCROOT			"/dev/mmcblk0p1"
+
+#include "el6x_common.h"
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE				ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE			RGMII
+#define CONFIG_ETHPRIME				"FEC"
+#define CONFIG_FEC_MXC_PHYADDR			0x10
+#define CONFIG_FEC_FIXED_SPEED			1000 /* No autoneg, fix Gb */
+
+#endif                         /*__EL6Q_CONFIG_H */
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
new file mode 100644
index 0000000..9d68376
--- /dev/null
+++ b/include/configs/zmx25.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (c) 2011 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * Configuation settings for the zmx25 board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_TIMER_RATE		32768
+#define CONFIG_SYS_TIMER_COUNTER	\
+	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_ZMX25
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"gs_fast_boot=setenv bootdelay 5\0" \
+	"gs_slow_boot=setenv bootdelay 10\0" \
+	"bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
+		"fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
+		"bootm 0x81000000; bootelf 0x81000000\0"
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * Serial
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x00
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+
+/*
+ * Additional command
+ */
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	MXC_EHCI_MODE_SERIAL
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
+#define CONFIG_EHCI_IS_TDI
+#endif /* CONFIG_CMD_USB */
+
+/* SDRAM */
+#define PHYS_SDRAM		0x80000000	/* start address of LPDDRRAM */
+#define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */
+
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR	0x78020000	/* end of internal SRAM */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		0xA0000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x00040000)
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_SIZE			(128 * 1024)
+
+/*
+ * CFI FLASH driver setup
+ */
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM + (512*1024))
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM + PHYS_SDRAM_SIZE)
+
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(0x400000 - 0x8000)
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
new file mode 100644
index 0000000..274cc19
--- /dev/null
+++ b/include/configs/zynq-common.h
@@ -0,0 +1,279 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ * (C) Copyright 2013 - 2018 Xilinx, Inc.
+ *
+ * Common configuration options for all Zynq boards.
+ */
+
+#ifndef __CONFIG_ZYNQ_COMMON_H
+#define __CONFIG_ZYNQ_COMMON_H
+
+/* CPU clock */
+#ifndef CONFIG_CPU_FREQ_HZ
+# define CONFIG_CPU_FREQ_HZ	800000000
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+/* Cache options */
+#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+# define CONFIG_SYS_L2_PL310
+# define CONFIG_SYS_PL310_BASE		0xf8f02000
+#endif
+
+#define ZYNQ_SCUTIMER_BASEADDR		0xF8F00600
+#define CONFIG_SYS_TIMERBASE		ZYNQ_SCUTIMER_BASEADDR
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+
+/* Serial drivers */
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CONFIG_ARM_DCC
+
+/* Ethernet driver */
+#if defined(CONFIG_ZYNQ_GEM)
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_BOOTP_MAY_FAIL
+#endif
+
+/* QSPI */
+
+/* NOR */
+#ifdef CONFIG_MTD_NOR_FLASH
+# define CONFIG_SYS_FLASH_BASE		0xE2000000
+# define CONFIG_SYS_FLASH_SIZE		(16 * 1024 * 1024)
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_MAX_FLASH_SECT	512
+# define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+# define CONFIG_SYS_FLASH_WRITE_TOUT	5000
+# define CONFIG_FLASH_SHOW_PROGRESS	10
+# undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
+#ifdef CONFIG_NAND_ZYNQ
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#endif
+
+#ifdef CONFIG_USB_EHCI_ZYNQ
+# define CONFIG_EHCI_IS_TDI
+
+# define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x600000
+# define DFU_DEFAULT_POLL_TIMEOUT	300
+# define CONFIG_THOR_RESET_OFF
+# define DFU_ALT_INFO_RAM \
+	"dfu_ram_info=" \
+	"setenv dfu_alt_info " \
+	"${kernel_image} ram 0x3000000 0x500000\\\\;" \
+	"${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
+	"${ramdisk_image} ram 0x2000000 0x600000\0" \
+	"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
+	"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
+
+# if defined(CONFIG_MMC_SDHCI_ZYNQ)
+#  define DFU_ALT_INFO_MMC \
+	"dfu_mmc_info=" \
+	"setenv dfu_alt_info " \
+	"${kernel_image} fat 0 1\\\\;" \
+	"${devicetree_image} fat 0 1\\\\;" \
+	"${ramdisk_image} fat 0 1\0" \
+	"dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
+	"thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
+
+#  define DFU_ALT_INFO	\
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_MMC
+# else
+#  define DFU_ALT_INFO	\
+	DFU_ALT_INFO_RAM
+# endif
+#endif
+
+#if !defined(DFU_ALT_INFO)
+# define DFU_ALT_INFO
+#endif
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* enable preboot to be loaded before CONFIG_BOOTDELAY */
+
+/* Boot configuration */
+#define CONFIG_SYS_LOAD_ADDR		0 /* default? */
+
+#ifdef CONFIG_SPL_BUILD
+#define BOOTENV
+#else
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#ifdef CONFIG_CMD_USB
+#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1)
+#else
+#define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
+#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
+#else
+#define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#if defined(CONFIG_CMD_DHCP)
+#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define BOOT_TARGET_DEVICES_DHCP(func)
+#endif
+
+#if defined(CONFIG_ZYNQ_QSPI)
+# define BOOT_TARGET_DEVICES_QSPI(func)	func(QSPI, qspi, na)
+#else
+# define BOOT_TARGET_DEVICES_QSPI(func)
+#endif
+
+#if defined(CONFIG_NAND_ZYNQ)
+# define BOOT_TARGET_DEVICES_NAND(func)	func(NAND, nand, na)
+#else
+# define BOOT_TARGET_DEVICES_NAND(func)
+#endif
+
+#if defined(CONFIG_MTD_NOR_FLASH)
+# define BOOT_TARGET_DEVICES_NOR(func)	func(NOR, nor, na)
+#else
+# define BOOT_TARGET_DEVICES_NOR(func)
+#endif
+
+#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+	"bootcmd_qspi=sf probe 0 0 0 && " \
+		      "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \
+		      "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
+	"qspi "
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+	"bootcmd_nand=nand info && " \
+		      "nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \
+		      "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+	"nand "
+
+#define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \
+	"script_offset_nor=0xE2FC0000\0"        \
+	"bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \
+		     "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \
+	"nor "
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_QSPI(func) \
+	BOOT_TARGET_DEVICES_NAND(func) \
+	BOOT_TARGET_DEVICES_NOR(func) \
+	BOOT_TARGET_DEVICES_USB(func) \
+	BOOT_TARGET_DEVICES_PXE(func) \
+	BOOT_TARGET_DEVICES_DHCP(func)
+
+#include <config_distro_bootcmd.h>
+#endif /* CONFIG_SPL_BUILD */
+
+/* Default environment */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0x20000000\0"		\
+	"initrd_high=0x20000000\0"	\
+	"scriptaddr=0x20000\0"	\
+	"script_offset_f=0xFC0000\0"	\
+	"script_size_f=0x40000\0"	\
+	"fdt_addr_r=0x1f00000\0"        \
+	"pxefile_addr_r=0x2000000\0"    \
+	"kernel_addr_r=0x2000000\0"     \
+	"scriptaddr=0x3000000\0"        \
+	"ramdisk_addr_r=0x3100000\0"    \
+	DFU_ALT_INFO \
+	BOOTENV
+#endif
+
+/* Miscellaneous configurable options */
+
+#define CONFIG_CLOCKS
+#define CONFIG_SYS_MAXARGS		32 /* max number of command args */
+#define CONFIG_SYS_CBSIZE		2048 /* Console I/O Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0
+#define CONFIG_SYS_MEMTEST_END		0x1000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN	(60 * 1024 * 1024)
+
+/* Boot FreeBSD/vxWorks from an ELF image */
+#define CONFIG_SYS_MMC_MAX_DEVICE	1
+
+/* MMC support */
+#ifdef CONFIG_MMC_SDHCI_ZYNQ
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot.img"
+#endif
+
+/* Address in RAM where the parameters must be copied by SPL. */
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x10000000
+
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME		"system.dtb"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME		"uImage"
+
+/* Not using MMC raw mode - just for compilation purpose */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0
+
+/* qspi mode is working fine */
+#ifdef CONFIG_ZYNQ_QSPI
+#define CONFIG_SYS_SPI_ARGS_OFFS	0x200000
+#define CONFIG_SYS_SPI_ARGS_SIZE	0x80000
+#define CONFIG_SYS_SPI_KERNEL_OFFS	(CONFIG_SYS_SPI_ARGS_OFFS + \
+					CONFIG_SYS_SPI_ARGS_SIZE)
+#endif
+
+/* SP location before relocation, must use scratch RAM */
+
+/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
+#define CONFIG_SPL_MAX_SIZE	0x30000
+
+/* On the top of OCM space */
+#define CONFIG_SYS_SPL_MALLOC_START	CONFIG_SPL_STACK_R_ADDR
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x2000000
+
+/*
+ * SPL stack position - and stack goes down
+ * 0xfffffe00 is used for putting wfi loop.
+ * Set it up as limit for now.
+ */
+#define CONFIG_SPL_STACK	0xfffffe00
+
+/* BSS setup */
+#define CONFIG_SPL_BSS_START_ADDR	0x100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000
+
+#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
+
+#endif /* __CONFIG_ZYNQ_COMMON_H */
diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h
new file mode 100644
index 0000000..917f35b
--- /dev/null
+++ b/include/configs/zynq_cse.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013 - 2017 Xilinx.
+ *
+ * Configuration settings for the Xilinx Zynq CSE board.
+ * See zynq-common.h for Zynq common configs
+ */
+
+#ifndef __CONFIG_ZYNQ_CSE_H
+#define __CONFIG_ZYNQ_CSE_H
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#include <configs/zynq-common.h>
+
+/* Undef unneeded configs */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+
+#undef CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_CBSIZE	1024
+
+#undef CONFIG_SYS_INIT_RAM_ADDR
+#undef CONFIG_SYS_INIT_RAM_SIZE
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFDE000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#undef CONFIG_SPL_BSS_START_ADDR
+#undef CONFIG_SPL_BSS_MAX_SIZE
+#define CONFIG_SPL_BSS_START_ADDR	0x20000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x8000
+
+#endif /* __CONFIG_ZYNQ_CSE_H */
diff --git a/include/console.h b/include/console.h
new file mode 100644
index 0000000..e935c60
--- /dev/null
+++ b/include/console.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __CONSOLE_H
+#define __CONSOLE_H
+
+extern char console_buffer[];
+
+/* common/console.c */
+int console_init_f(void);	/* Before relocation; uses the serial  stuff */
+int console_init_r(void);	/* After  relocation; uses the console stuff */
+int console_assign(int file, const char *devname);	/* Assign the console */
+int ctrlc(void);
+int had_ctrlc(void);	/* have we had a Control-C since last clear? */
+void clear_ctrlc(void);	/* clear the Control-C condition */
+int disable_ctrlc(int);	/* 1 to disable, 0 to enable Control-C detect */
+int confirm_yesno(void);        /*  1 if input is "y", "Y", "yes" or "YES" */
+
+/**
+ * console_record_init() - set up the console recording buffers
+ *
+ * This should be called as soon as malloc() is available so that the maximum
+ * amount of console output can be recorded.
+ */
+int console_record_init(void);
+
+/**
+ * console_record_reset() - reset the console recording buffers
+ *
+ * Removes any data in the buffers
+ */
+void console_record_reset(void);
+
+/**
+ * console_record_reset_enable() - reset and enable the console buffers
+ *
+ * This should be called to enable the console buffer.
+ */
+void console_record_reset_enable(void);
+
+/**
+ * console_announce_r() - print a U-Boot console on non-serial consoles
+ *
+ * When U-Boot starts up with a display it generally does not announce itself
+ * on the display. The banner is instead emitted on the UART before relocation.
+ * This function prints a banner on devices which (we assume) did not receive
+ * it before relocation.
+ *
+ * @return 0 (meaning no errors)
+ */
+int console_announce_r(void);
+
+/*
+ * CONSOLE multiplexing.
+ */
+#ifdef CONFIG_CONSOLE_MUX
+#include <iomux.h>
+#endif
+
+#endif
diff --git a/include/cortina.h b/include/cortina.h
new file mode 100644
index 0000000..ba7fafe
--- /dev/null
+++ b/include/cortina.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Cortina PHY drivers
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _CORTINA_H_
+#define _CORTINA_H_
+
+#define VILLA_GLOBAL_CHIP_ID_LSB     0x000
+#define VILLA_GLOBAL_CHIP_ID_MSB     0x001
+#define VILLA_GLOBAL_BIST_CONTROL    0x002
+#define VILLA_GLOBAL_BIST_STATUS     0x003
+#define VILLA_GLOBAL_LINE_SOFT_RESET 0x007
+#define VILLA_GLOBAL_HOST_SOFT_RESET 0x008
+#define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A
+#define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B
+#define VILLA_GLOBAL_MSEQCLKCTRL 0x00E
+#define VILLA_MSEQ_OPTIONS       0x1D0
+#define VILLA_MSEQ_PC		 0x1D3
+#define VILLA_MSEQ_BANKSELECT    0x1DF
+#define VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT     0x2DB
+#define VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT   0x36E
+#define VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER   0x403
+#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPA	0x404
+#define VILLA_LINE_SDS_COMMON_SRX0_RX_CPB	0x405
+#define VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL	0x369
+#define VILLA_MSEQ_ENABLE_MSB	0x194
+#define VILLA_MSEQ_SPARE21_LSB	0x226
+#define VILLA_MSEQ_RESET_COUNT_LSB  0x1E0
+#define VILLA_MSEQ_SPARE12_MSB  0x215
+#define VILLA_MSEQ_SPARE2_LSB   0x200
+#define VILLA_MSEQ_SPARE7_LSB   0x20A
+#define VILLA_MSEQ_SPARE9_LSB   0x20E
+#define VILLA_MSEQ_SPARE3_LSB   0x202
+#define VILLA_MSEQ_SPARE3_MSB   0x203
+#define VILLA_MSEQ_SPARE8_LSB   0x20C
+#define VILLA_MSEQ_SPARE8_MSB   0x20D
+#define VILLA_MSEQ_COEF8_FFE0_LSB 0x1E2
+#define VILLA_MSEQ_COEF8_FFE1_LSB 0x1E4
+#define VILLA_MSEQ_COEF8_FFE2_LSB 0x1E6
+#define VILLA_MSEQ_COEF8_FFE3_LSB 0x1E8
+#define VILLA_MSEQ_COEF8_FFE4_LSB 0x1EA
+#define VILLA_MSEQ_COEF8_FFE5_LSB 0x1EC
+#define VILLA_MSEQ_COEF8_DFE0_LSB 0x1F0
+#define VILLA_MSEQ_COEF8_DFE0N_LSB 0x1EE
+#define VILLA_MSEQ_COEF8_DFE1_LSB  0x1F2
+#define VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK 0x2E2
+#define VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB 0x360
+#define VILLA_MSEQ_POWER_DOWN_LSB  0x198
+#define VILLA_MSEQ_POWER_DOWN_MSB  0x199
+#define VILLA_MSEQ_CAL_RX_SLICER   0x1B8
+#define VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB 0x365
+#define VILLA_MSEQ_COEF_INIT_SEL  0x1AE
+#define VILLA_DSP_SDS_DSP_PRECODEDINITFFE21 0x26A
+#define VILLA_MSEQ_SERDES_PARAM_LSB 0x195
+#define VILLA_MSEQ_SPARE25_LSB	0x22E
+#define VILLA_MSEQ_SPARE23_LSB	0x22A
+#define VILLA_MSEQ_CAL_RX_DFE_EQ 0x1BA
+#define VILLA_GLOBAL_VILLA2_COMPATIBLE      0x030
+#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA  0x812
+#define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB  0x813
+#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427
+#define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428
+
+/* Cortina CS4223 */
+#define CS4223_EEPROM_STATUS  0x5001
+#define CS4223_EEPROM_FIRMWARE_LOADDONE  0x1
+
+#define mseq_edc_bist_done (0x1<<0)
+#define mseq_edc_bist_fail (0x1<<8)
+
+struct cortina_reg_config {
+	unsigned short reg_addr;
+	unsigned short reg_value;
+};
+#endif
diff --git a/include/cp1250.h b/include/cp1250.h
new file mode 100644
index 0000000..adacf8a
--- /dev/null
+++ b/include/cp1250.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Constant CP1250 contains the Unicode code points for characters 0x80 - 0xff
+ * of the code page 1250.
+ */
+#define CP1250 { \
+	0x20ac, 0x0000, 0x201a, 0x0000, \
+	0x201e, 0x2026, 0x2020, 0x2021, \
+	0x0000, 0x2030, 0x0160, 0x2039, \
+	0x015a, 0x0164, 0x017d, 0x0179, \
+	0x0000, 0x2018, 0x2019, 0x201c, \
+	0x201d, 0x2022, 0x2013, 0x2014, \
+	0x0000, 0x2122, 0x0161, 0x203a, \
+	0x015b, 0x0165, 0x017e, 0x017a, \
+	0x00a0, 0x02c7, 0x02d8, 0x0141, \
+	0x00a4, 0x0104, 0x00a6, 0x00a7, \
+	0x00a8, 0x00a9, 0x015e, 0x00ab, \
+	0x00ac, 0x00ad, 0x00ae, 0x017b, \
+	0x00b0, 0x00b1, 0x02db, 0x0142, \
+	0x00b4, 0x00b5, 0x00b6, 0x00b7, \
+	0x00b8, 0x0105, 0x015f, 0x00bb, \
+	0x013d, 0x02dd, 0x013e, 0x017c, \
+	0x0154, 0x00c1, 0x00c2, 0x0102, \
+	0x00c4, 0x0139, 0x0106, 0x00c7, \
+	0x010c, 0x00c9, 0x0118, 0x00cb, \
+	0x011a, 0x00cd, 0x00ce, 0x010e, \
+	0x0110, 0x0143, 0x0147, 0x00d3, \
+	0x00d4, 0x0150, 0x00d6, 0x00d7, \
+	0x0158, 0x016e, 0x00da, 0x0170, \
+	0x00dc, 0x00dd, 0x0162, 0x00df, \
+	0x0155, 0x00e1, 0x00e2, 0x0103, \
+	0x00e4, 0x013a, 0x0107, 0x00e7, \
+	0x010d, 0x00e9, 0x0119, 0x00eb, \
+	0x011b, 0x00ed, 0x00ee, 0x010f, \
+	0x0111, 0x0144, 0x0148, 0x00f3, \
+	0x00f4, 0x0151, 0x00f6, 0x00f7, \
+	0x0159, 0x016f, 0x00fa, 0x0171, \
+	0x00fc, 0x00fd, 0x0163, 0x02d9, \
+}
diff --git a/include/cp437.h b/include/cp437.h
new file mode 100644
index 0000000..0b2b971
--- /dev/null
+++ b/include/cp437.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Constant CP437 contains the Unicode code points for characters 0x80 - 0xff
+ * of the code page 437.
+ */
+#define CP437 { \
+	0x00c7, 0x00fc, 0x00e9, 0x00e2, \
+	0x00e4, 0x00e0, 0x00e5, 0x00e7, \
+	0x00ea, 0x00eb, 0x00e8, 0x00ef, \
+	0x00ee, 0x00ec, 0x00c4, 0x00c5, \
+	0x00c9, 0x00e6, 0x00c6, 0x00f4, \
+	0x00f6, 0x00f2, 0x00fb, 0x00f9, \
+	0x00ff, 0x00d6, 0x00dc, 0x00a2, \
+	0x00a3, 0x00a5, 0x20a7, 0x0192, \
+	0x00e1, 0x00ed, 0x00f3, 0x00fa, \
+	0x00f1, 0x00d1, 0x00aa, 0x00ba, \
+	0x00bf, 0x2310, 0x00ac, 0x00bd, \
+	0x00bc, 0x00a1, 0x00ab, 0x00bb, \
+	0x2591, 0x2592, 0x2593, 0x2502, \
+	0x2524, 0x2561, 0x2562, 0x2556, \
+	0x2555, 0x2563, 0x2551, 0x2557, \
+	0x255d, 0x255c, 0x255b, 0x2510, \
+	0x2514, 0x2534, 0x252c, 0x251c, \
+	0x2500, 0x253c, 0x255e, 0x255f, \
+	0x255a, 0x2554, 0x2569, 0x2566, \
+	0x2560, 0x2550, 0x256c, 0x2567, \
+	0x2568, 0x2564, 0x2565, 0x2559, \
+	0x2558, 0x2552, 0x2553, 0x256b, \
+	0x256a, 0x2518, 0x250c, 0x2588, \
+	0x2584, 0x258c, 0x2590, 0x2580, \
+	0x03b1, 0x00df, 0x0393, 0x03c0, \
+	0x03a3, 0x03c3, 0x00b5, 0x03c4, \
+	0x03a6, 0x0398, 0x03a9, 0x03b4, \
+	0x221e, 0x03c6, 0x03b5, 0x2229, \
+	0x2261, 0x00b1, 0x2265, 0x2264, \
+	0x2320, 0x2321, 0x00f7, 0x2248, \
+	0x00b0, 0x2219, 0x00b7, 0x221a, \
+	0x207f, 0x00b2, 0x25a0, 0x00a0, \
+}
diff --git a/include/cpsw.h b/include/cpsw.h
new file mode 100644
index 0000000..96ff254
--- /dev/null
+++ b/include/cpsw.h
@@ -0,0 +1,82 @@
+/*
+ * CPSW Ethernet Switch Driver
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPSW_H_
+#define _CPSW_H_
+
+/* reg offset */
+#define CPSW_HOST_PORT_OFFSET	0x108
+#define CPSW_SLAVE0_OFFSET	0x208
+#define CPSW_SLAVE1_OFFSET	0x308
+#define CPSW_SLAVE_SIZE		0x100
+#define CPSW_CPDMA_OFFSET	0x800
+#define CPSW_HW_STATS		0x900
+#define CPSW_STATERAM_OFFSET	0xa00
+#define CPSW_CPTS_OFFSET	0xc00
+#define CPSW_ALE_OFFSET		0xd00
+#define CPSW_SLIVER0_OFFSET	0xd80
+#define CPSW_SLIVER1_OFFSET	0xdc0
+#define CPSW_BD_OFFSET		0x2000
+#define CPSW_MDIO_DIV		0xff
+
+#define AM335X_GMII_SEL_OFFSET	0x630
+
+struct cpsw_slave_data {
+	u32		slave_reg_ofs;
+	u32		sliver_reg_ofs;
+	int		phy_addr;
+	int		phy_if;
+	int		phy_of_handle;
+};
+
+enum {
+	CPSW_CTRL_VERSION_1 = 0,
+	CPSW_CTRL_VERSION_2	/* am33xx like devices */
+};
+
+struct cpsw_platform_data {
+	u32	mdio_base;
+	u32	cpsw_base;
+	u32	mac_id;
+	u32	gmii_sel;
+	int	mdio_div;
+	int	channels;	/* number of cpdma channels (symmetric)	*/
+	u32	cpdma_reg_ofs;	/* cpdma register offset		*/
+	int	slaves;		/* number of slave cpgmac ports		*/
+	u32	ale_reg_ofs;	/* address lookup engine reg offset	*/
+	int	ale_entries;	/* ale table size			*/
+	u32	host_port_reg_ofs;	/* cpdma host port registers	*/
+	u32	hw_stats_reg_ofs;	/* cpsw hw stats counters	*/
+	u32	bd_ram_ofs;		/* Buffer Descriptor RAM offset */
+	u32	mac_control;
+	struct cpsw_slave_data	*slave_data;
+	void	(*control)(int enabled);
+	u32	host_port_num;
+	u32	active_slave;
+	bool	rmii_clock_external;
+	u8	version;
+	const char *phy_sel_compat;
+	u32	syscon_addr;
+	const char *macid_sel_compat;
+};
+
+int cpsw_register(struct cpsw_platform_data *data);
+int ti_cm_get_macid_addr(struct udevice *dev, int slave,
+			 struct cpsw_platform_data *data);
+void ti_cm_get_macid(struct udevice *dev, struct cpsw_platform_data *data,
+		     u8 *mac_addr);
+int cpsw_get_slave_phy_addr(struct udevice *dev, int slave);
+
+#endif /* _CPSW_H_  */
diff --git a/include/cpu.h b/include/cpu.h
new file mode 100644
index 0000000..28dd48f
--- /dev/null
+++ b/include/cpu.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __CPU_H
+#define __CPU_H
+
+/**
+ * struct cpu_platdata - platform data for a CPU
+ * @cpu_id:	   Platform-specific way of identifying the CPU.
+ * @ucode_version: Microcode version, if CPU_FEAT_UCODE is set
+ * @device_id:     Driver-defined device identifier
+ * @family:        DMTF CPU Family identifier
+ * @id:            DMTF CPU Processor identifier
+ * @timebase_freq: the current frequency at which the cpu timer timebase
+ *		   registers are updated (in Hz)
+ *
+ * This can be accessed with dev_get_parent_platdata() for any UCLASS_CPU
+ * device.
+ */
+struct cpu_platdata {
+	int cpu_id;
+	int ucode_version;
+	ulong device_id;
+	u16 family;
+	u32 id[2];
+	u32 timebase_freq;
+};
+
+/* CPU features - mostly just a placeholder for now */
+enum {
+	CPU_FEAT_L1_CACHE	= 0,	/* Supports level 1 cache */
+	CPU_FEAT_MMU		= 1,	/* Supports virtual memory */
+	CPU_FEAT_UCODE		= 2,	/* Requires/uses microcode */
+	CPU_FEAT_DEVICE_ID	= 3,	/* Provides a device ID */
+
+	CPU_FEAT_COUNT,
+};
+
+/**
+ * struct cpu_info - Information about a CPU
+ *
+ * @cpu_freq:	Current CPU frequency in Hz
+ * @features:	Flags for supported CPU features
+ */
+struct cpu_info {
+	ulong cpu_freq;
+	ulong features;
+};
+
+struct cpu_ops {
+	/**
+	 * get_desc() - Get a description string for a CPU
+	 *
+	 * @dev:	Device to check (UCLASS_CPU)
+	 * @buf:	Buffer to place string
+	 * @size:	Size of string space
+	 * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+	 */
+	int (*get_desc)(struct udevice *dev, char *buf, int size);
+
+	/**
+	 * get_info() - Get information about a CPU
+	 *
+	 * @dev:	Device to check (UCLASS_CPU)
+	 * @info:	Returns CPU info
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_info)(struct udevice *dev, struct cpu_info *info);
+
+	/**
+	 * get_count() - Get number of CPUs
+	 *
+	 * @dev:	Device to check (UCLASS_CPU)
+	 * @return CPU count if OK, -ve on error
+	 */
+	int (*get_count)(struct udevice *dev);
+
+	/**
+	 * get_vendor() - Get vendor name of a CPU
+	 *
+	 * @dev:	Device to check (UCLASS_CPU)
+	 * @buf:	Buffer to place string
+	 * @size:	Size of string space
+	 * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+	 */
+	int (*get_vendor)(struct udevice *dev, char *buf, int size);
+};
+
+#define cpu_get_ops(dev)        ((struct cpu_ops *)(dev)->driver->ops)
+
+/**
+ * cpu_get_desc() - Get a description string for a CPU
+ * @dev:	Device to check (UCLASS_CPU)
+ * @buf:	Buffer to place string
+ * @size:	Size of string space
+ *
+ * Return: 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+int cpu_get_desc(struct udevice *dev, char *buf, int size);
+
+/**
+ * cpu_get_info() - Get information about a CPU
+ * @dev:	Device to check (UCLASS_CPU)
+ * @info:	Returns CPU info
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int cpu_get_info(struct udevice *dev, struct cpu_info *info);
+
+/**
+ * cpu_get_count() - Get number of CPUs
+ * @dev:	Device to check (UCLASS_CPU)
+ *
+ * Return: CPU count if OK, -ve on error
+ */
+int cpu_get_count(struct udevice *dev);
+
+/**
+ * cpu_get_vendor() - Get vendor name of a CPU
+ * @dev:	Device to check (UCLASS_CPU)
+ * @buf:	Buffer to place string
+ * @size:	Size of string space
+ *
+ * Return: 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+int cpu_get_vendor(struct udevice *dev, char *buf, int size);
+
+/**
+ * cpu_probe_all() - Probe all available CPUs
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int cpu_probe_all(void);
+
+#endif
diff --git a/include/cramfs/cramfs_fs.h b/include/cramfs/cramfs_fs.h
new file mode 100644
index 0000000..e0c14f0
--- /dev/null
+++ b/include/cramfs/cramfs_fs.h
@@ -0,0 +1,100 @@
+#ifndef __CRAMFS_H
+#define __CRAMFS_H
+
+#define CRAMFS_MAGIC		0x28cd3d45	/* some random number */
+#define CRAMFS_SIGNATURE	"Compressed ROMFS"
+
+/*
+ * Width of various bitfields in struct cramfs_inode.
+ * Primarily used to generate warnings in mkcramfs.
+ */
+#define CRAMFS_MODE_WIDTH	16
+#define CRAMFS_UID_WIDTH	16
+#define CRAMFS_SIZE_WIDTH	24
+#define CRAMFS_GID_WIDTH	8
+#define CRAMFS_NAMELEN_WIDTH	6
+#define CRAMFS_OFFSET_WIDTH	26
+
+/*
+ * Since inode.namelen is a unsigned 6-bit number, the maximum cramfs
+ * path length is 63 << 2 = 252.
+ */
+#define CRAMFS_MAXPATHLEN (((1 << CRAMFS_NAMELEN_WIDTH) - 1) << 2)
+
+/*
+ * Reasonably terse representation of the inode data.
+ */
+struct cramfs_inode {
+	u32 mode:CRAMFS_MODE_WIDTH, uid:CRAMFS_UID_WIDTH;
+
+	/* SIZE for device files is i_rdev */
+	u32 size:CRAMFS_SIZE_WIDTH, gid:CRAMFS_GID_WIDTH;
+
+	/* NAMELEN is the length of the file name, divided by 4 and
+	   rounded up.	(cramfs doesn't support hard links.) */
+	/* OFFSET: For symlinks and non-empty regular files, this
+	   contains the offset (divided by 4) of the file data in
+	   compressed form (starting with an array of block pointers;
+	   see README).	 For non-empty directories it is the offset
+	   (divided by 4) of the inode of the first file in that
+	   directory.  For anything else, offset is zero. */
+	u32 namelen:CRAMFS_NAMELEN_WIDTH, offset:CRAMFS_OFFSET_WIDTH;
+};
+
+struct cramfs_info {
+	u32 crc;
+	u32 edition;
+	u32 blocks;
+	u32 files;
+};
+
+/*
+ * Superblock information at the beginning of the FS.
+ */
+struct cramfs_super {
+	u32 magic;			/* 0x28cd3d45 - random number */
+	u32 size;			/* length in bytes */
+	u32 flags;			/* feature flags */
+	u32 future;			/* reserved for future use */
+	u8 signature[16];		/* "Compressed ROMFS" */
+	struct cramfs_info fsid;	/* unique filesystem info */
+	u8 name[16];			/* user-defined name */
+	struct cramfs_inode root;	/* root inode data */
+};
+
+/*
+ * Feature flags
+ *
+ * 0x00000000 - 0x000000ff: features that work for all past kernels
+ * 0x00000100 - 0xffffffff: features that don't work for past kernels
+ */
+#define CRAMFS_FLAG_FSID_VERSION_2	0x00000001	/* fsid version #2 */
+#define CRAMFS_FLAG_SORTED_DIRS		0x00000002	/* sorted dirs */
+#define CRAMFS_FLAG_HOLES		0x00000100	/* support for holes */
+#define CRAMFS_FLAG_WRONG_SIGNATURE	0x00000200	/* reserved */
+#define CRAMFS_FLAG_SHIFTED_ROOT_OFFSET 0x00000400	/* shifted root fs */
+
+/*
+ * Valid values in super.flags.	 Currently we refuse to mount
+ * if (flags & ~CRAMFS_SUPPORTED_FLAGS).  Maybe that should be
+ * changed to test super.future instead.
+ */
+#define CRAMFS_SUPPORTED_FLAGS	( 0x000000ff \
+				| CRAMFS_FLAG_HOLES \
+				| CRAMFS_FLAG_WRONG_SIGNATURE \
+				| CRAMFS_FLAG_SHIFTED_ROOT_OFFSET )
+
+#define CRAMFS_16(x)	(x)
+#define CRAMFS_24(x)	(x)
+#define CRAMFS_32(x)	(x)
+#define CRAMFS_GET_NAMELEN(x)	((x)->namelen)
+#define CRAMFS_GET_OFFSET(x)	((x)->offset)
+#define CRAMFS_SET_OFFSET(x,y)	((x)->offset = (y))
+#define CRAMFS_SET_NAMELEN(x,y) ((x)->namelen = (y))
+
+/* Uncompression interfaces to the underlying zlib */
+int cramfs_uncompress_block(void *dst, void *src, int srclen);
+int cramfs_uncompress_init(void);
+int cramfs_uncompress_exit(void);
+
+#endif	/* __CRAMFS_H */
diff --git a/include/cros_ec.h b/include/cros_ec.h
new file mode 100644
index 0000000..f4b9b7a
--- /dev/null
+++ b/include/cros_ec.h
@@ -0,0 +1,489 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Chromium OS cros_ec driver
+ *
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef _CROS_EC_H
+#define _CROS_EC_H
+
+#include <linux/compiler.h>
+#include <ec_commands.h>
+#include <cros_ec_message.h>
+#include <asm/gpio.h>
+#include <dm/of_extra.h>
+
+/* Our configuration information */
+struct cros_ec_dev {
+	struct udevice *dev;		/* Transport device */
+	struct gpio_desc ec_int;	/* GPIO used as EC interrupt line */
+	int protocol_version;           /* Protocol version to use */
+	int optimise_flash_write;	/* Don't write erased flash blocks */
+
+	/*
+	 * These two buffers will always be dword-aligned and include enough
+	 * space for up to 7 word-alignment bytes also, so we can ensure that
+	 * the body of the message is always dword-aligned (64-bit).
+	 *
+	 * We use this alignment to keep ARM and x86 happy. Probably word
+	 * alignment would be OK, there might be a small performance advantage
+	 * to using dword.
+	 */
+	uint8_t din[ALIGN(MSG_BYTES + sizeof(int64_t), sizeof(int64_t))]
+		__aligned(sizeof(int64_t));
+	uint8_t dout[ALIGN(MSG_BYTES + sizeof(int64_t), sizeof(int64_t))]
+		__aligned(sizeof(int64_t));
+};
+
+/*
+ * Hard-code the number of columns we happen to know we have right now.  It
+ * would be more correct to call cros_ec_info() at startup and determine the
+ * actual number of keyboard cols from there.
+ */
+#define CROS_EC_KEYSCAN_COLS 13
+
+/* Information returned by a key scan */
+struct mbkp_keyscan {
+	uint8_t data[CROS_EC_KEYSCAN_COLS];
+};
+
+/* Holds information about the Chrome EC */
+struct fdt_cros_ec {
+	struct fmap_entry flash;	/* Address and size of EC flash */
+	/*
+	 * Byte value of erased flash, or -1 if not known. It is normally
+	 * 0xff but some flash devices use 0 (e.g. STM32Lxxx)
+	 */
+	int flash_erase_value;
+	struct fmap_entry region[EC_FLASH_REGION_COUNT];
+};
+
+/**
+ * Read the ID of the CROS-EC device
+ *
+ * The ID is a string identifying the CROS-EC device.
+ *
+ * @param dev		CROS-EC device
+ * @param id		Place to put the ID
+ * @param maxlen	Maximum length of the ID field
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_read_id(struct udevice *dev, char *id, int maxlen);
+
+/**
+ * Read a keyboard scan from the CROS-EC device
+ *
+ * Send a message requesting a keyboard scan and return the result
+ *
+ * @param dev		CROS-EC device
+ * @param scan		Place to put the scan results
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_scan_keyboard(struct udevice *dev, struct mbkp_keyscan *scan);
+
+/**
+ * Read which image is currently running on the CROS-EC device.
+ *
+ * @param dev		CROS-EC device
+ * @param image		Destination for image identifier
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_read_current_image(struct udevice *dev,
+			       enum ec_current_image *image);
+
+/**
+ * Read the hash of the CROS-EC device firmware.
+ *
+ * @param dev		CROS-EC device
+ * @param hash_offset	Offset in flash to read from
+ * @param hash		Destination for hash information
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_read_hash(struct udevice *dev, uint hash_offset,
+		      struct ec_response_vboot_hash *hash);
+
+/**
+ * Send a reboot command to the CROS-EC device.
+ *
+ * Note that some reboot commands (such as EC_REBOOT_COLD) also reboot the AP.
+ *
+ * @param dev		CROS-EC device
+ * @param cmd		Reboot command
+ * @param flags         Flags for reboot command (EC_REBOOT_FLAG_*)
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_reboot(struct udevice *dev, enum ec_reboot_cmd cmd, uint8_t flags);
+
+/**
+ * Check if the CROS-EC device has an interrupt pending.
+ *
+ * Read the status of the external interrupt connected to the CROS-EC device.
+ * If no external interrupt is configured, this always returns 1.
+ *
+ * @param dev		CROS-EC device
+ * @return 0 if no interrupt is pending
+ */
+int cros_ec_interrupt_pending(struct udevice *dev);
+
+enum {
+	CROS_EC_OK,
+	CROS_EC_ERR = 1,
+	CROS_EC_ERR_FDT_DECODE,
+	CROS_EC_ERR_CHECK_VERSION,
+	CROS_EC_ERR_READ_ID,
+	CROS_EC_ERR_DEV_INIT,
+};
+
+/**
+ * Initialise the Chromium OS EC driver
+ *
+ * @param blob		Device tree blob containing setup information
+ * @param cros_ecp        Returns pointer to the cros_ec device, or NULL if none
+ * @return 0 if we got an cros_ec device and all is well (or no cros_ec is
+ *	expected), -ve if we should have an cros_ec device but failed to find
+ *	one, or init failed (-CROS_EC_ERR_...).
+ */
+int cros_ec_init(const void *blob, struct udevice**cros_ecp);
+
+/**
+ * Read information about the keyboard matrix
+ *
+ * @param dev		CROS-EC device
+ * @param info		Place to put the info structure
+ */
+int cros_ec_info(struct udevice *dev, struct ec_response_mkbp_info *info);
+
+/**
+ * Read the host event flags
+ *
+ * @param dev		CROS-EC device
+ * @param events_ptr	Destination for event flags.  Not changed on error.
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_get_host_events(struct udevice *dev, uint32_t *events_ptr);
+
+/**
+ * Clear the specified host event flags
+ *
+ * @param dev		CROS-EC device
+ * @param events	Event flags to clear
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_clear_host_events(struct udevice *dev, uint32_t events);
+
+/**
+ * Get/set flash protection
+ *
+ * @param dev		CROS-EC device
+ * @param set_mask	Mask of flags to set; if 0, just retrieves existing
+ *                      protection state without changing it.
+ * @param set_flags	New flag values; only bits in set_mask are applied;
+ *                      ignored if set_mask=0.
+ * @param prot          Destination for updated protection state from EC.
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_flash_protect(struct udevice *dev, uint32_t set_mask,
+			  uint32_t set_flags,
+			  struct ec_response_flash_protect *resp);
+
+/**
+ * Notify EC of current boot mode
+ *
+ * @param dev		CROS-EC device
+ * @param vboot_mode    Verified boot mode
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_entering_mode(struct udevice *dev, int mode);
+
+/**
+ * Run internal tests on the cros_ec interface.
+ *
+ * @param dev		CROS-EC device
+ * @return 0 if ok, <0 if the test failed
+ */
+int cros_ec_test(struct udevice *dev);
+
+/**
+ * Update the EC RW copy.
+ *
+ * @param dev		CROS-EC device
+ * @param image		the content to write
+ * @param imafge_size	content length
+ * @return 0 if ok, <0 if the test failed
+ */
+int cros_ec_flash_update_rw(struct udevice *dev, const uint8_t  *image,
+			    int image_size);
+
+/**
+ * Return a pointer to the board's CROS-EC device
+ *
+ * @return pointer to CROS-EC device, or NULL if none is available
+ */
+struct udevice *board_get_cros_ec_dev(void);
+
+struct dm_cros_ec_ops {
+	int (*check_version)(struct udevice *dev);
+	int (*command)(struct udevice *dev, uint8_t cmd, int cmd_version,
+		       const uint8_t *dout, int dout_len,
+		       uint8_t **dinp, int din_len);
+	int (*packet)(struct udevice *dev, int out_bytes, int in_bytes);
+};
+
+#define dm_cros_ec_get_ops(dev) \
+		((struct dm_cros_ec_ops *)(dev)->driver->ops)
+
+int cros_ec_register(struct udevice *dev);
+
+/**
+ * Dump a block of data for a command.
+ *
+ * @param name	Name for data (e.g. 'in', 'out')
+ * @param cmd	Command number associated with data, or -1 for none
+ * @param data	Data block to dump
+ * @param len	Length of data block to dump
+ */
+void cros_ec_dump_data(const char *name, int cmd, const uint8_t *data, int len);
+
+/**
+ * Calculate a simple 8-bit checksum of a data block
+ *
+ * @param data	Data block to checksum
+ * @param size	Size of data block in bytes
+ * @return checksum value (0 to 255)
+ */
+int cros_ec_calc_checksum(const uint8_t *data, int size);
+
+int cros_ec_flash_erase(struct udevice *dev, uint32_t offset, uint32_t size);
+
+/**
+ * Read data from the flash
+ *
+ * Read an arbitrary amount of data from the EC flash, by repeatedly reading
+ * small blocks.
+ *
+ * The offset starts at 0. You can obtain the region information from
+ * cros_ec_flash_offset() to find out where to read for a particular region.
+ *
+ * @param dev		CROS-EC device
+ * @param data		Pointer to data buffer to read into
+ * @param offset	Offset within flash to read from
+ * @param size		Number of bytes to read
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_flash_read(struct udevice *dev, uint8_t *data, uint32_t offset,
+		       uint32_t size);
+
+/**
+ * Read back flash parameters
+ *
+ * This function reads back parameters of the flash as reported by the EC
+ *
+ * @param dev  Pointer to device
+ * @param info Pointer to output flash info struct
+ */
+int cros_ec_read_flashinfo(struct udevice *dev,
+			   struct ec_response_flash_info *info);
+
+/**
+ * Write data to the flash
+ *
+ * Write an arbitrary amount of data to the EC flash, by repeatedly writing
+ * small blocks.
+ *
+ * The offset starts at 0. You can obtain the region information from
+ * cros_ec_flash_offset() to find out where to write for a particular region.
+ *
+ * Attempting to write to the region where the EC is currently running from
+ * will result in an error.
+ *
+ * @param dev		CROS-EC device
+ * @param data		Pointer to data buffer to write
+ * @param offset	Offset within flash to write to.
+ * @param size		Number of bytes to write
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_flash_write(struct udevice *dev, const uint8_t *data,
+			uint32_t offset, uint32_t size);
+
+/**
+ * Obtain position and size of a flash region
+ *
+ * @param dev		CROS-EC device
+ * @param region	Flash region to query
+ * @param offset	Returns offset of flash region in EC flash
+ * @param size		Returns size of flash region
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_flash_offset(struct udevice *dev, enum ec_flash_region region,
+			 uint32_t *offset, uint32_t *size);
+
+/**
+ * Read/write non-volatile data from/to a CROS-EC device.
+ *
+ * @param dev		CROS-EC device
+ * @param block		Buffer of VbNvContext to be read/write
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_read_nvdata(struct udevice *dev, uint8_t *block, int size);
+int cros_ec_write_nvdata(struct udevice *dev, const uint8_t *block, int size);
+
+/**
+ * Read the version information for the EC images
+ *
+ * @param dev		CROS-EC device
+ * @param versionp	This is set to point to the version information
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_read_version(struct udevice *dev,
+			 struct ec_response_get_version **versionp);
+
+/**
+ * Read the build information for the EC
+ *
+ * @param dev		CROS-EC device
+ * @param versionp	This is set to point to the build string
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_read_build_info(struct udevice *dev, char **strp);
+
+/**
+ * Switch on/off a LDO / FET.
+ *
+ * @param dev		CROS-EC device
+ * @param index		index of the LDO/FET to switch
+ * @param state		new state of the LDO/FET : EC_LDO_STATE_ON|OFF
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_set_ldo(struct udevice *dev, uint8_t index, uint8_t state);
+
+/**
+ * Read back a LDO / FET current state.
+ *
+ * @param dev		CROS-EC device
+ * @param index		index of the LDO/FET to switch
+ * @param state		current state of the LDO/FET : EC_LDO_STATE_ON|OFF
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_get_ldo(struct udevice *dev, uint8_t index, uint8_t *state);
+
+/**
+ * Get access to the error reported when cros_ec_board_init() was called
+ *
+ * This permits delayed reporting of the EC error if it failed during
+ * early init.
+ *
+ * @return error (0 if there was no error, -ve if there was an error)
+ */
+int cros_ec_get_error(void);
+
+/**
+ * Returns information from the FDT about the Chrome EC flash
+ *
+ * @param dev		Device to read from
+ * @param config	Structure to use to return information
+ */
+int cros_ec_decode_ec_flash(struct udevice *dev, struct fdt_cros_ec *config);
+
+/**
+ * Check the current keyboard state, in case recovery mode is requested.
+ * This function is for sandbox only.
+ *
+ * @param ec		CROS-EC device
+ */
+void cros_ec_check_keyboard(struct udevice *dev);
+
+struct i2c_msg;
+/*
+ * Tunnel an I2C transfer to the EC
+ *
+ * @param dev		CROS-EC device
+ * @param port		The remote port on EC to use
+ * @param msg		List of messages to transfer
+ * @param nmsgs		Number of messages to transfer
+ */
+int cros_ec_i2c_tunnel(struct udevice *dev, int port, struct i2c_msg *msg,
+		       int nmsgs);
+
+/**
+ * cros_ec_get_events_b() - Get event mask B
+ *
+ * @return value of event mask, default value of 0 if it could not be read
+ */
+uint64_t cros_ec_get_events_b(struct udevice *dev);
+
+/**
+ * cros_ec_clear_events_b() - Clear even mask B
+ *
+ * Any pending events in the B range are cleared
+ *
+ * @return 0 if OK, -ve on error
+ */
+int cros_ec_clear_events_b(struct udevice *dev, uint64_t mask);
+
+/**
+ * cros_ec_efs_verify() - tell the EC to verify one of its images
+ *
+ * @param dev		CROS-EC device
+ * @param region	Flash region to query
+ * @return 0 if OK, -ve on error
+ */
+int cros_ec_efs_verify(struct udevice *dev, enum ec_flash_region region);
+
+/**
+ * cros_ec_battery_cutoff() - Request that the battery be cut off
+ *
+ * This tells the battery to stop supplying power. This is used before shipping
+ * a device to ensure that the battery remains charged while the device is
+ * shipped or sitting on the shelf waiting to be purchased.
+ *
+ * @param dev		CROS-EC device
+ * @param flags		Flags to use (EC_BATTERY_CUTOFF_FLAG_...)
+ * @return 0 if OK, -ve on error
+ */
+int cros_ec_battery_cutoff(struct udevice *dev, uint8_t flags);
+
+/**
+ * cros_ec_read_limit_power() - Check if power is limited by batter/charger
+ *
+ * Sometimes the battery is low and / or the device is connected to a charger
+ * that cannot supply much power.
+ *
+ * @param dev		CROS-EC device
+ * @param limit_powerp	Returns whether power is limited (0 or 1)
+ * @return 0 if OK, -ENOSYS if the EC does not support this comment, -EINVAL
+ *		if the EC returned an invalid response
+ */
+int cros_ec_read_limit_power(struct udevice *dev, int *limit_powerp);
+
+/**
+ * cros_ec_config_powerbtn() - Configure the behaviour of the power button
+ *
+ * @param dev		CROS-EC device
+ * @param flags		Flags to use (EC_POWER_BUTTON_...)
+ * @return 0 if OK, -ve on error
+ */
+int cros_ec_config_powerbtn(struct udevice *dev, uint32_t flags);
+
+/**
+ * cros_ec_get_lid_shutdown_mask() - Set the lid shutdown mask
+ *
+ * Determines whether a lid close event is reported
+ *
+ * @param dev		CROS-EC device
+ * @return shufdown mas if OK, -ve on error
+ */
+int cros_ec_get_lid_shutdown_mask(struct udevice *dev);
+
+/**
+ * cros_ec_set_lid_shutdown_mask() - Set the lid shutdown mask
+ *
+ * Set whether a lid close event is reported
+ *
+ * @param dev		CROS-EC device
+ * @param enable	true to enable reporting, false to disable
+ * @return shufdown mas if OK, -ve on error
+ */
+int cros_ec_set_lid_shutdown_mask(struct udevice *dev, int enable);
+
+#endif
diff --git a/include/cros_ec_message.h b/include/cros_ec_message.h
new file mode 100644
index 0000000..977951b
--- /dev/null
+++ b/include/cros_ec_message.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Chromium OS Matrix Keyboard Message Protocol definitions
+ *
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef _CROS_MESSAGE_H
+#define _CROS_MESSAGE_H
+
+/*
+ * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
+ *
+ * This is copied from the Chromium OS Open Source Embedded Controller code.
+ */
+enum {
+	/* The header byte, which follows the preamble */
+	MSG_HEADER	= 0xec,
+
+	MSG_HEADER_BYTES	= 3,
+	MSG_TRAILER_BYTES	= 2,
+	MSG_PROTO_BYTES		= MSG_HEADER_BYTES + MSG_TRAILER_BYTES,
+
+	/* Max length of messages */
+	MSG_BYTES		= EC_PROTO2_MAX_PARAM_SIZE + MSG_PROTO_BYTES,
+};
+
+#endif
diff --git a/include/ddr_spd.h b/include/ddr_spd.h
new file mode 100644
index 0000000..fe163da
--- /dev/null
+++ b/include/ddr_spd.h
@@ -0,0 +1,564 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _DDR_SPD_H_
+#define _DDR_SPD_H_
+
+/*
+ * Format from "JEDEC Standard No. 21-C,
+ * Appendix D: Rev 1.0: SPD's for DDR SDRAM
+ */
+typedef struct ddr1_spd_eeprom_s {
+	unsigned char info_size;   /*  0 # bytes written into serial memory */
+	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
+	unsigned char mem_type;    /*  2 Fundamental memory type */
+	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
+	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
+	unsigned char nrows;       /*  5 Number of DIMM Banks */
+	unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
+	unsigned char dataw_msb;   /*  7 ... Data Width continuation */
+	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
+	unsigned char clk_cycle;   /*  9 SDRAM Cycle time @ CL=X */
+	unsigned char clk_access;  /* 10 SDRAM Access from Clk @ CL=X (tAC) */
+	unsigned char config;      /* 11 DIMM Configuration type */
+	unsigned char refresh;     /* 12 Refresh Rate/Type */
+	unsigned char primw;       /* 13 Primary SDRAM Width */
+	unsigned char ecw;         /* 14 Error Checking SDRAM width */
+	unsigned char min_delay;   /* 15 for Back to Back Random Address */
+	unsigned char burstl;      /* 16 Burst Lengths Supported */
+	unsigned char nbanks;      /* 17 # of Banks on SDRAM Device */
+	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
+	unsigned char cs_lat;      /* 19 CS# Latency */
+	unsigned char write_lat;   /* 20 Write Latency (aka Write Recovery) */
+	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
+	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
+	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
+	unsigned char clk_access2; /* 24 SDRAM Access from
+					 Clk @ CL=X-0.5 (tAC) */
+	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-1 */
+	unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
+	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
+	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
+	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
+	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
+	unsigned char bank_dens;   /* 31 Density of each bank on module */
+	unsigned char ca_setup;    /* 32 Addr + Cmd Setup Time Before Clk */
+	unsigned char ca_hold;     /* 33 Addr + Cmd Hold Time After Clk */
+	unsigned char data_setup;  /* 34 Data Input Setup Time Before Strobe */
+	unsigned char data_hold;   /* 35 Data Input Hold Time After Strobe */
+	unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */
+	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
+	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
+	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
+	unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
+	unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
+	unsigned char res_46;      /* 46 Reserved */
+	unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */
+	unsigned char res_48_61[14]; /* 48-61 Reserved */
+	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
+	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
+	unsigned char mid[8];      /* 64-71 Mfr's JEDEC ID code per JEP-106 */
+	unsigned char mloc;        /* 72 Manufacturing Location */
+	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
+	unsigned char rev[2];      /* 91 Revision Code */
+	unsigned char mdate[2];    /* 93 Manufacturing Date */
+	unsigned char sernum[4];   /* 95 Assembly Serial Number */
+	unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
+
+} ddr1_spd_eeprom_t;
+
+/*
+ * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM",
+ * SPD Revision 1.2
+ */
+typedef struct ddr2_spd_eeprom_s {
+	unsigned char info_size;   /*  0 # bytes written into serial memory */
+	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
+	unsigned char mem_type;    /*  2 Fundamental memory type */
+	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
+	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
+	unsigned char mod_ranks;   /*  5 Number of DIMM Ranks */
+	unsigned char dataw;       /*  6 Module Data Width */
+	unsigned char res_7;       /*  7 Reserved */
+	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
+	unsigned char clk_cycle;   /*  9 SDRAM Cycle time @ CL=X */
+	unsigned char clk_access;  /* 10 SDRAM Access from Clk @ CL=X (tAC) */
+	unsigned char config;      /* 11 DIMM Configuration type */
+	unsigned char refresh;     /* 12 Refresh Rate/Type */
+	unsigned char primw;       /* 13 Primary SDRAM Width */
+	unsigned char ecw;         /* 14 Error Checking SDRAM width */
+	unsigned char res_15;      /* 15 Reserved */
+	unsigned char burstl;      /* 16 Burst Lengths Supported */
+	unsigned char nbanks;      /* 17 # of Banks on Each SDRAM Device */
+	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
+	unsigned char mech_char;   /* 19 DIMM Mechanical Characteristics */
+	unsigned char dimm_type;   /* 20 DIMM type information */
+	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
+	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
+	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-1 */
+	unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */
+	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-2 */
+	unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */
+	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
+	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
+	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
+	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
+	unsigned char rank_dens;   /* 31 Density of each rank on module */
+	unsigned char ca_setup;    /* 32 Addr+Cmd Setup Time Before Clk (tIS) */
+	unsigned char ca_hold;     /* 33 Addr+Cmd Hold Time After Clk (tIH) */
+	unsigned char data_setup;  /* 34 Data Input Setup Time
+					 Before Strobe (tDS) */
+	unsigned char data_hold;   /* 35 Data Input Hold Time
+					 After Strobe (tDH) */
+	unsigned char twr;         /* 36 Write Recovery time tWR */
+	unsigned char twtr;        /* 37 Int write to read delay tWTR */
+	unsigned char trtp;        /* 38 Int read to precharge delay tRTP */
+	unsigned char mem_probe;   /* 39 Mem analysis probe characteristics */
+	unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
+	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
+	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
+	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
+	unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
+	unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
+	unsigned char pll_relock;  /* 46 PLL Relock time */
+	unsigned char t_casemax;    /* 47 Tcasemax */
+	unsigned char psi_ta_dram;  /* 48 Thermal Resistance of DRAM Package from
+					 Top (Case) to Ambient (Psi T-A DRAM) */
+	unsigned char dt0_mode;    /* 49 DRAM Case Temperature Rise from Ambient
+					 due to Activate-Precharge/Mode Bits
+					 (DT0/Mode Bits) */
+	unsigned char dt2n_dt2q;   /* 50 DRAM Case Temperature Rise from Ambient
+					 due to Precharge/Quiet Standby
+					 (DT2N/DT2Q) */
+	unsigned char dt2p;        /* 51 DRAM Case Temperature Rise from Ambient
+					 due to Precharge Power-Down (DT2P) */
+	unsigned char dt3n;        /* 52 DRAM Case Temperature Rise from Ambient
+					 due to Active Standby (DT3N) */
+	unsigned char dt3pfast;    /* 53 DRAM Case Temperature Rise from Ambient
+					 due to Active Power-Down with
+					 Fast PDN Exit (DT3Pfast) */
+	unsigned char dt3pslow;    /* 54 DRAM Case Temperature Rise from Ambient
+					 due to Active Power-Down with Slow
+					 PDN Exit (DT3Pslow) */
+	unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient
+					 due to Page Open Burst Read/DT4R4W
+					 Mode Bit (DT4R/DT4R4W Mode Bit) */
+	unsigned char dt5b;        /* 56 DRAM Case Temperature Rise from Ambient
+					 due to Burst Refresh (DT5B) */
+	unsigned char dt7;         /* 57 DRAM Case Temperature Rise from Ambient
+					 due to Bank Interleave Reads with
+					 Auto-Precharge (DT7) */
+	unsigned char psi_ta_pll;  /* 58 Thermal Resistance of PLL Package form
+					 Top (Case) to Ambient (Psi T-A PLL) */
+	unsigned char psi_ta_reg;    /* 59 Thermal Reisitance of Register Package
+					 from Top (Case) to Ambient
+					 (Psi T-A Register) */
+	unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
+					 due to PLL Active (DT PLL Active) */
+	unsigned char dtregact;    /* 61 Register Case Temperature Rise from
+					 Ambient due to Register Active/Mode Bit
+					 (DT Register Active/Mode Bit) */
+	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
+	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
+	unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-106 */
+	unsigned char mloc;        /* 72 Manufacturing Location */
+	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
+	unsigned char rev[2];      /* 91 Revision Code */
+	unsigned char mdate[2];    /* 93 Manufacturing Date */
+	unsigned char sernum[4];   /* 95 Assembly Serial Number */
+	unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
+
+} ddr2_spd_eeprom_t;
+
+typedef struct ddr3_spd_eeprom_s {
+	/* General Section: Bytes 0-59 */
+	unsigned char info_size_crc;   /*  0 # bytes written into serial memory,
+					     CRC coverage */
+	unsigned char spd_rev;         /*  1 Total # bytes of SPD mem device */
+	unsigned char mem_type;        /*  2 Key Byte / Fundamental mem type */
+	unsigned char module_type;     /*  3 Key Byte / Module Type */
+	unsigned char density_banks;   /*  4 SDRAM Density and Banks */
+	unsigned char addressing;      /*  5 SDRAM Addressing */
+	unsigned char module_vdd;      /*  6 Module nominal voltage, VDD */
+	unsigned char organization;    /*  7 Module Organization */
+	unsigned char bus_width;       /*  8 Module Memory Bus Width */
+	unsigned char ftb_div;         /*  9 Fine Timebase (FTB)
+					     Dividend / Divisor */
+	unsigned char mtb_dividend;    /* 10 Medium Timebase (MTB) Dividend */
+	unsigned char mtb_divisor;     /* 11 Medium Timebase (MTB) Divisor */
+	unsigned char tck_min;         /* 12 SDRAM Minimum Cycle Time */
+	unsigned char res_13;          /* 13 Reserved */
+	unsigned char caslat_lsb;      /* 14 CAS Latencies Supported,
+					     Least Significant Byte */
+	unsigned char caslat_msb;      /* 15 CAS Latencies Supported,
+					     Most Significant Byte */
+	unsigned char taa_min;         /* 16 Min CAS Latency Time */
+	unsigned char twr_min;         /* 17 Min Write REcovery Time */
+	unsigned char trcd_min;        /* 18 Min RAS# to CAS# Delay Time */
+	unsigned char trrd_min;        /* 19 Min Row Active to
+					     Row Active Delay Time */
+	unsigned char trp_min;         /* 20 Min Row Precharge Delay Time */
+	unsigned char tras_trc_ext;    /* 21 Upper Nibbles for tRAS and tRC */
+	unsigned char tras_min_lsb;    /* 22 Min Active to Precharge
+					     Delay Time */
+	unsigned char trc_min_lsb;     /* 23 Min Active to Active/Refresh
+					     Delay Time, LSB */
+	unsigned char trfc_min_lsb;    /* 24 Min Refresh Recovery Delay Time */
+	unsigned char trfc_min_msb;    /* 25 Min Refresh Recovery Delay Time */
+	unsigned char twtr_min;        /* 26 Min Internal Write to
+					     Read Command Delay Time */
+	unsigned char trtp_min;        /* 27 Min Internal Read to Precharge
+					     Command Delay Time */
+	unsigned char tfaw_msb;        /* 28 Upper Nibble for tFAW */
+	unsigned char tfaw_min;        /* 29 Min Four Activate Window
+					     Delay Time*/
+	unsigned char opt_features;    /* 30 SDRAM Optional Features */
+	unsigned char therm_ref_opt;   /* 31 SDRAM Thermal and Refresh Opts */
+	unsigned char therm_sensor;    /* 32 Module Thermal Sensor */
+	unsigned char device_type;     /* 33 SDRAM device type */
+	int8_t fine_tck_min;	       /* 34 Fine offset for tCKmin */
+	int8_t fine_taa_min;	       /* 35 Fine offset for tAAmin */
+	int8_t fine_trcd_min;	       /* 36 Fine offset for tRCDmin */
+	int8_t fine_trp_min;	       /* 37 Fine offset for tRPmin */
+	int8_t fine_trc_min;	       /* 38 Fine offset for tRCmin */
+	unsigned char res_39_59[21];   /* 39-59 Reserved, General Section */
+
+	/* Module-Specific Section: Bytes 60-116 */
+	union {
+		struct {
+			/* 60 (Unbuffered) Module Nominal Height */
+			unsigned char mod_height;
+			/* 61 (Unbuffered) Module Maximum Thickness */
+			unsigned char mod_thickness;
+			/* 62 (Unbuffered) Reference Raw Card Used */
+			unsigned char ref_raw_card;
+			/* 63 (Unbuffered) Address Mapping from
+			      Edge Connector to DRAM */
+			unsigned char addr_mapping;
+			/* 64-116 (Unbuffered) Reserved */
+			unsigned char res_64_116[53];
+		} unbuffered;
+		struct {
+			/* 60 (Registered) Module Nominal Height */
+			unsigned char mod_height;
+			/* 61 (Registered) Module Maximum Thickness */
+			unsigned char mod_thickness;
+			/* 62 (Registered) Reference Raw Card Used */
+			unsigned char ref_raw_card;
+			/* 63 DIMM Module Attributes */
+			unsigned char modu_attr;
+			/* 64 RDIMM Thermal Heat Spreader Solution */
+			unsigned char thermal;
+			/* 65 Register Manufacturer ID Code, Least Significant Byte */
+			unsigned char reg_id_lo;
+			/* 66 Register Manufacturer ID Code, Most Significant Byte */
+			unsigned char reg_id_hi;
+			/* 67 Register Revision Number */
+			unsigned char reg_rev;
+			/* 68 Register Type */
+			unsigned char reg_type;
+			/* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */
+			unsigned char rcw[8];
+		} registered;
+		unsigned char uc[57]; /* 60-116 Module-Specific Section */
+	} mod_section;
+
+	/* Unique Module ID: Bytes 117-125 */
+	unsigned char mmid_lsb;        /* 117 Module MfgID Code LSB - JEP-106 */
+	unsigned char mmid_msb;        /* 118 Module MfgID Code MSB - JEP-106 */
+	unsigned char mloc;            /* 119 Mfg Location */
+	unsigned char mdate[2];        /* 120-121 Mfg Date */
+	unsigned char sernum[4];       /* 122-125 Module Serial Number */
+
+	/* CRC: Bytes 126-127 */
+	unsigned char crc[2];          /* 126-127 SPD CRC */
+
+	/* Other Manufacturer Fields and User Space: Bytes 128-255 */
+	unsigned char mpart[18];       /* 128-145 Mfg's Module Part Number */
+	unsigned char mrev[2];         /* 146-147 Module Revision Code */
+
+	unsigned char dmid_lsb;        /* 148 DRAM MfgID Code LSB - JEP-106 */
+	unsigned char dmid_msb;        /* 149 DRAM MfgID Code MSB - JEP-106 */
+
+	unsigned char msd[26];         /* 150-175 Mfg's Specific Data */
+	unsigned char cust[80];        /* 176-255 Open for Customer Use */
+
+} ddr3_spd_eeprom_t;
+
+/* From JEEC Standard No. 21-C release 23A */
+struct ddr4_spd_eeprom_s {
+	/* General Section: Bytes 0-127 */
+	uint8_t info_size_crc;		/*  0 # bytes */
+	uint8_t spd_rev;		/*  1 Total # bytes of SPD */
+	uint8_t mem_type;		/*  2 Key Byte / mem type */
+	uint8_t module_type;		/*  3 Key Byte / Module Type */
+	uint8_t density_banks;		/*  4 Density and Banks	*/
+	uint8_t addressing;		/*  5 Addressing */
+	uint8_t package_type;		/*  6 Package type */
+	uint8_t opt_feature;		/*  7 Optional features */
+	uint8_t thermal_ref;		/*  8 Thermal and refresh */
+	uint8_t oth_opt_features;	/*  9 Other optional features */
+	uint8_t res_10;			/* 10 Reserved */
+	uint8_t module_vdd;		/* 11 Module nominal voltage */
+	uint8_t organization;		/* 12 Module Organization */
+	uint8_t bus_width;		/* 13 Module Memory Bus Width */
+	uint8_t therm_sensor;		/* 14 Module Thermal Sensor */
+	uint8_t ext_type;		/* 15 Extended module type */
+	uint8_t res_16;
+	uint8_t timebases;		/* 17 MTb and FTB */
+	uint8_t tck_min;		/* 18 tCKAVGmin */
+	uint8_t tck_max;		/* 19 TCKAVGmax */
+	uint8_t caslat_b1;		/* 20 CAS latencies, 1st byte */
+	uint8_t caslat_b2;		/* 21 CAS latencies, 2nd byte */
+	uint8_t caslat_b3;		/* 22 CAS latencies, 3rd byte */
+	uint8_t caslat_b4;		/* 23 CAS latencies, 4th byte */
+	uint8_t taa_min;		/* 24 Min CAS Latency Time */
+	uint8_t trcd_min;		/* 25 Min RAS# to CAS# Delay Time */
+	uint8_t trp_min;		/* 26 Min Row Precharge Delay Time */
+	uint8_t tras_trc_ext;		/* 27 Upper Nibbles for tRAS and tRC */
+	uint8_t tras_min_lsb;		/* 28 tRASmin, lsb */
+	uint8_t trc_min_lsb;		/* 29 tRCmin, lsb */
+	uint8_t trfc1_min_lsb;		/* 30 Min Refresh Recovery Delay Time */
+	uint8_t trfc1_min_msb;		/* 31 Min Refresh Recovery Delay Time */
+	uint8_t trfc2_min_lsb;		/* 32 Min Refresh Recovery Delay Time */
+	uint8_t trfc2_min_msb;		/* 33 Min Refresh Recovery Delay Time */
+	uint8_t trfc4_min_lsb;		/* 34 Min Refresh Recovery Delay Time */
+	uint8_t trfc4_min_msb;		/* 35 Min Refresh Recovery Delay Time */
+	uint8_t tfaw_msb;		/* 36 Upper Nibble for tFAW */
+	uint8_t tfaw_min;		/* 37 tFAW, lsb */
+	uint8_t trrds_min;		/* 38 tRRD_Smin, MTB */
+	uint8_t trrdl_min;		/* 39 tRRD_Lmin, MTB */
+	uint8_t tccdl_min;		/* 40 tCCS_Lmin, MTB */
+	uint8_t res_41[60-41];		/* 41 Rserved */
+	uint8_t mapping[78-60];		/* 60~77 Connector to SDRAM bit map */
+	uint8_t res_78[117-78];		/* 78~116, Reserved */
+	int8_t fine_tccdl_min;		/* 117 Fine offset for tCCD_Lmin */
+	int8_t fine_trrdl_min;		/* 118 Fine offset for tRRD_Lmin */
+	int8_t fine_trrds_min;		/* 119 Fine offset for tRRD_Smin */
+	int8_t fine_trc_min;		/* 120 Fine offset for tRCmin */
+	int8_t fine_trp_min;		/* 121 Fine offset for tRPmin */
+	int8_t fine_trcd_min;		/* 122 Fine offset for tRCDmin */
+	int8_t fine_taa_min;		/* 123 Fine offset for tAAmin */
+	int8_t fine_tck_max;		/* 124 Fine offset for tCKAVGmax */
+	int8_t fine_tck_min;		/* 125 Fine offset for tCKAVGmin */
+	/* CRC: Bytes 126-127 */
+	uint8_t crc[2];			/* 126-127 SPD CRC */
+
+	/* Module-Specific Section: Bytes 128-255 */
+	union {
+		struct {
+			/* 128 (Unbuffered) Module Nominal Height */
+			uint8_t mod_height;
+			/* 129 (Unbuffered) Module Maximum Thickness */
+			uint8_t mod_thickness;
+			/* 130 (Unbuffered) Reference Raw Card Used */
+			uint8_t ref_raw_card;
+			/* 131 (Unbuffered) Address Mapping from
+			      Edge Connector to DRAM */
+			uint8_t addr_mapping;
+			/* 132~253 (Unbuffered) Reserved */
+			uint8_t res_132[254-132];
+			/* 254~255 CRC */
+			uint8_t crc[2];
+		} unbuffered;
+		struct {
+			/* 128 (Registered) Module Nominal Height */
+			uint8_t mod_height;
+			/* 129 (Registered) Module Maximum Thickness */
+			uint8_t mod_thickness;
+			/* 130 (Registered) Reference Raw Card Used */
+			uint8_t ref_raw_card;
+			/* 131 DIMM Module Attributes */
+			uint8_t modu_attr;
+			/* 132 RDIMM Thermal Heat Spreader Solution */
+			uint8_t thermal;
+			/* 133 Register Manufacturer ID Code, LSB */
+			uint8_t reg_id_lo;
+			/* 134 Register Manufacturer ID Code, MSB */
+			uint8_t reg_id_hi;
+			/* 135 Register Revision Number */
+			uint8_t reg_rev;
+			/* 136 Address mapping from register to DRAM */
+			u8 reg_map;
+			u8 ca_stren;
+			u8 clk_stren;
+			/* 139~253 Reserved */
+			u8 res_137[254 - 139];
+			/* 254~255 CRC */
+			uint8_t crc[2];
+		} registered;
+		struct {
+			/* 128 (Loadreduced) Module Nominal Height */
+			uint8_t mod_height;
+			/* 129 (Loadreduced) Module Maximum Thickness */
+			uint8_t mod_thickness;
+			/* 130 (Loadreduced) Reference Raw Card Used */
+			uint8_t ref_raw_card;
+			/* 131 DIMM Module Attributes */
+			uint8_t modu_attr;
+			/* 132 RDIMM Thermal Heat Spreader Solution */
+			uint8_t thermal;
+			/* 133 Register Manufacturer ID Code, LSB */
+			uint8_t reg_id_lo;
+			/* 134 Register Manufacturer ID Code, MSB */
+			uint8_t reg_id_hi;
+			/* 135 Register Revision Number */
+			uint8_t reg_rev;
+			/* 136 Address mapping from register to DRAM */
+			uint8_t reg_map;
+			/* 137 Register Output Drive Strength for CMD/Add*/
+			uint8_t reg_drv;
+			/* 138 Register Output Drive Strength for CK */
+			uint8_t reg_drv_ck;
+			/* 139 Data Buffer Revision Number */
+			uint8_t data_buf_rev;
+			/* 140 DRAM VrefDQ for Package Rank 0 */
+			uint8_t vrefqe_r0;
+			/* 141 DRAM VrefDQ for Package Rank 1 */
+			uint8_t vrefqe_r1;
+			/* 142 DRAM VrefDQ for Package Rank 2 */
+			uint8_t vrefqe_r2;
+			/* 143 DRAM VrefDQ for Package Rank 3 */
+			uint8_t vrefqe_r3;
+			/* 144 Data Buffer VrefDQ for DRAM Interface */
+			uint8_t data_intf;
+			/*
+			 * 145 Data Buffer MDQ Drive Strength and RTT
+			 * for data rate <= 1866
+			 */
+			uint8_t data_drv_1866;
+			/*
+			 * 146 Data Buffer MDQ Drive Strength and RTT
+			 * for 1866 < data rate <= 2400
+			 */
+			uint8_t data_drv_2400;
+			/*
+			 * 147 Data Buffer MDQ Drive Strength and RTT
+			 * for 2400 < data rate <= 3200
+			 */
+			uint8_t data_drv_3200;
+			/* 148 DRAM Drive Strength */
+			uint8_t dram_drv;
+			/*
+			 * 149 DRAM ODT (RTT_WR, RTT_NOM)
+			 * for data rate <= 1866
+			 */
+			uint8_t dram_odt_1866;
+			/*
+			 * 150 DRAM ODT (RTT_WR, RTT_NOM)
+			 * for 1866 < data rate <= 2400
+			 */
+			uint8_t dram_odt_2400;
+			/*
+			 * 151 DRAM ODT (RTT_WR, RTT_NOM)
+			 * for 2400 < data rate <= 3200
+			 */
+			uint8_t dram_odt_3200;
+			/*
+			 * 152 DRAM ODT (RTT_PARK)
+			 * for data rate <= 1866
+			 */
+			uint8_t dram_odt_park_1866;
+			/*
+			 * 153 DRAM ODT (RTT_PARK)
+			 * for 1866 < data rate <= 2400
+			 */
+			uint8_t dram_odt_park_2400;
+			/*
+			 * 154 DRAM ODT (RTT_PARK)
+			 * for 2400 < data rate <= 3200
+			 */
+			uint8_t dram_odt_park_3200;
+			uint8_t res_155[254-155];	/* Reserved */
+			/* 254~255 CRC */
+			uint8_t crc[2];
+		} loadreduced;
+		uint8_t uc[128]; /* 128-255 Module-Specific Section */
+	} mod_section;
+
+	uint8_t res_256[320-256];	/* 256~319 Reserved */
+
+	/* Module supplier's data: Byte 320~383 */
+	uint8_t mmid_lsb;		/* 320 Module MfgID Code LSB */
+	uint8_t mmid_msb;		/* 321 Module MfgID Code MSB */
+	uint8_t mloc;			/* 322 Mfg Location */
+	uint8_t mdate[2];		/* 323~324 Mfg Date */
+	uint8_t sernum[4];		/* 325~328 Module Serial Number */
+	uint8_t mpart[20];		/* 329~348 Mfg's Module Part Number */
+	uint8_t mrev;			/* 349 Module Revision Code */
+	uint8_t dmid_lsb;		/* 350 DRAM MfgID Code LSB */
+	uint8_t dmid_msb;		/* 351 DRAM MfgID Code MSB */
+	uint8_t stepping;		/* 352 DRAM stepping */
+	uint8_t msd[29];		/* 353~381 Mfg's Specific Data */
+	uint8_t res_382[2];		/* 382~383 Reserved */
+
+	uint8_t user[512-384];		/* 384~511 End User Programmable */
+};
+
+extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
+extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
+extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
+extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
+extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
+unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd);
+
+/*
+ * Byte 2 Fundamental Memory Types.
+ */
+#define SPD_MEMTYPE_FPM		(0x01)
+#define SPD_MEMTYPE_EDO		(0x02)
+#define SPD_MEMTYPE_PIPE_NIBBLE	(0x03)
+#define SPD_MEMTYPE_SDRAM	(0x04)
+#define SPD_MEMTYPE_ROM		(0x05)
+#define SPD_MEMTYPE_SGRAM	(0x06)
+#define SPD_MEMTYPE_DDR		(0x07)
+#define SPD_MEMTYPE_DDR2	(0x08)
+#define SPD_MEMTYPE_DDR2_FBDIMM	(0x09)
+#define SPD_MEMTYPE_DDR2_FBDIMM_PROBE	(0x0A)
+#define SPD_MEMTYPE_DDR3	(0x0B)
+#define SPD_MEMTYPE_DDR4	(0x0C)
+
+/* DIMM Type for DDR2 SPD (according to v1.3) */
+#define DDR2_SPD_DIMMTYPE_UNDEFINED	(0x00)
+#define DDR2_SPD_DIMMTYPE_RDIMM		(0x01)
+#define DDR2_SPD_DIMMTYPE_UDIMM		(0x02)
+#define DDR2_SPD_DIMMTYPE_SO_DIMM	(0x04)
+#define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM	(0x06)
+#define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM	(0x07)
+#define DDR2_SPD_DIMMTYPE_MICRO_DIMM	(0x08)
+#define DDR2_SPD_DIMMTYPE_MINI_RDIMM	(0x10)
+#define DDR2_SPD_DIMMTYPE_MINI_UDIMM	(0x20)
+
+/* Byte 3 Key Byte / Module Type for DDR3 SPD */
+#define DDR3_SPD_MODULETYPE_MASK	(0x0f)
+#define DDR3_SPD_MODULETYPE_RDIMM	(0x01)
+#define DDR3_SPD_MODULETYPE_UDIMM	(0x02)
+#define DDR3_SPD_MODULETYPE_SO_DIMM	(0x03)
+#define DDR3_SPD_MODULETYPE_MICRO_DIMM	(0x04)
+#define DDR3_SPD_MODULETYPE_MINI_RDIMM	(0x05)
+#define DDR3_SPD_MODULETYPE_MINI_UDIMM	(0x06)
+#define DDR3_SPD_MODULETYPE_MINI_CDIMM	(0x07)
+#define DDR3_SPD_MODULETYPE_72B_SO_UDIMM	(0x08)
+#define DDR3_SPD_MODULETYPE_72B_SO_RDIMM	(0x09)
+#define DDR3_SPD_MODULETYPE_72B_SO_CDIMM	(0x0A)
+#define DDR3_SPD_MODULETYPE_LRDIMM	(0x0B)
+#define DDR3_SPD_MODULETYPE_16B_SO_DIMM	(0x0C)
+#define DDR3_SPD_MODULETYPE_32B_SO_DIMM	(0x0D)
+
+/* DIMM Type for DDR4 SPD */
+#define DDR4_SPD_MODULETYPE_MASK	(0x0f)
+#define DDR4_SPD_MODULETYPE_EXT		(0x00)
+#define DDR4_SPD_MODULETYPE_RDIMM	(0x01)
+#define DDR4_SPD_MODULETYPE_UDIMM	(0x02)
+#define DDR4_SPD_MODULETYPE_SO_DIMM	(0x03)
+#define DDR4_SPD_MODULETYPE_LRDIMM	(0x04)
+#define DDR4_SPD_MODULETYPE_MINI_RDIMM	(0x05)
+#define DDR4_SPD_MODULETYPE_MINI_UDIMM	(0x06)
+#define DDR4_SPD_MODULETYPE_72B_SO_UDIMM	(0x08)
+#define DDR4_SPD_MODULETYPE_72B_SO_RDIMM	(0x09)
+#define DDR4_SPD_MODULETYPE_16B_SO_DIMM	(0x0C)
+#define DDR4_SPD_MODULETYPE_32B_SO_DIMM	(0x0D)
+
+#endif /* _DDR_SPD_H_ */
diff --git a/include/debug_uart.h b/include/debug_uart.h
new file mode 100644
index 0000000..cd70ae1
--- /dev/null
+++ b/include/debug_uart.h
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Early debug UART support
+ *
+ * (C) Copyright 2014 Google, Inc
+ * Writte by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _DEBUG_UART_H
+#define _DEBUG_UART_H
+
+/*
+ * The debug UART is intended for use very early in U-Boot to debug problems
+ * when an ICE or other debug mechanism is not available.
+ *
+ * To use it you should:
+ * - Make sure your UART supports this interface
+ * - Enable CONFIG_DEBUG_UART
+ * - Enable the CONFIG for your UART to tell it to provide this interface
+ *       (e.g. CONFIG_DEBUG_UART_NS16550)
+ * - Define the required settings as needed (see below)
+ * - Call debug_uart_init() before use
+ * - Call printch() to output a character
+ *
+ * Depending on your platform it may be possible to use this UART before a
+ * stack is available.
+ *
+ * If your UART does not support this interface you can probably add support
+ * quite easily. Remember that you cannot use driver model and it is preferred
+ * to use no stack.
+ *
+ * You must not use this UART once driver model is working and the serial
+ * drivers are up and running (done in serial_init()). Otherwise the drivers
+ * may conflict and you will get strange output.
+ *
+ *
+ * To enable the debug UART in your serial driver:
+ *
+ * - #include <debug_uart.h>
+ * - Define _debug_uart_init(), trying to avoid using the stack
+ * - Define _debug_uart_putc() as static inline (avoiding stack usage)
+ * - Immediately afterwards, add DEBUG_UART_FUNCS to define the rest of the
+ *     functionality (printch(), etc.)
+ *
+ * If your board needs additional init for the UART to work, enable
+ * CONFIG_DEBUG_UART_BOARD_INIT and write a function called
+ * board_debug_uart_init() to perform that init. When debug_uart_init() is
+ * called, the init will happen automatically.
+ */
+
+/**
+ * debug_uart_init() - Set up the debug UART ready for use
+ *
+ * This sets up the UART with the correct baud rate, etc.
+ *
+ * Available CONFIG is:
+ *
+ *    - CONFIG_DEBUG_UART_BASE: Base address of UART
+ *    - CONFIG_BAUDRATE: Requested baud rate
+ *    - CONFIG_DEBUG_UART_CLOCK: Input clock for UART
+ */
+void debug_uart_init(void);
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void);
+#else
+static inline void board_debug_uart_init(void)
+{
+}
+#endif
+
+/**
+ * printch() - Output a character to the debug UART
+ *
+ * @ch:		Character to output
+ */
+void printch(int ch);
+
+/**
+ * printascii() - Output an ASCII string to the debug UART
+ *
+ * @str:	String to output
+ */
+void printascii(const char *str);
+
+/**
+ * printhex2() - Output a 2-digit hex value
+ *
+ * @value:	Value to output
+ */
+void printhex2(uint value);
+
+/**
+ * printhex4() - Output a 4-digit hex value
+ *
+ * @value:	Value to output
+ */
+void printhex4(uint value);
+
+/**
+ * printhex8() - Output a 8-digit hex value
+ *
+ * @value:	Value to output
+ */
+void printhex8(uint value);
+
+/**
+ * printdec() - Output a decimalism value
+ *
+ * @value:	Value to output
+ */
+void printdec(uint value);
+
+#ifdef CONFIG_DEBUG_UART_ANNOUNCE
+#define _DEBUG_UART_ANNOUNCE	printascii("<debug_uart> ");
+#else
+#define _DEBUG_UART_ANNOUNCE
+#endif
+
+#define serial_dout(reg, value)	\
+	serial_out_shift((char *)com_port + \
+		((char *)reg - (char *)com_port) * \
+			(1 << CONFIG_DEBUG_UART_SHIFT), \
+		CONFIG_DEBUG_UART_SHIFT, value)
+#define serial_din(reg) \
+	serial_in_shift((char *)com_port + \
+		((char *)reg - (char *)com_port) * \
+			(1 << CONFIG_DEBUG_UART_SHIFT), \
+		CONFIG_DEBUG_UART_SHIFT)
+
+/*
+ * Now define some functions - this should be inserted into the serial driver
+ */
+#define DEBUG_UART_FUNCS \
+\
+	static inline void _printch(int ch) \
+	{ \
+		if (ch == '\n') \
+			_debug_uart_putc('\r'); \
+		_debug_uart_putc(ch); \
+	} \
+\
+	void printch(int ch) \
+	{ \
+		_printch(ch); \
+	} \
+\
+	void printascii(const char *str) \
+	{ \
+		while (*str) \
+			_printch(*str++); \
+	} \
+\
+	static inline void printhex1(uint digit) \
+	{ \
+		digit &= 0xf; \
+		_debug_uart_putc(digit > 9 ? digit - 10 + 'a' : digit + '0'); \
+	} \
+\
+	static inline void printhex(uint value, int digits) \
+	{ \
+		while (digits-- > 0) \
+			printhex1(value >> (4 * digits)); \
+	} \
+\
+	void printhex2(uint value) \
+	{ \
+		printhex(value, 2); \
+	} \
+\
+	void printhex4(uint value) \
+	{ \
+		printhex(value, 4); \
+	} \
+\
+	void printhex8(uint value) \
+	{ \
+		printhex(value, 8); \
+	} \
+\
+	void printdec(uint value) \
+	{ \
+		if (value > 10) { \
+			printdec(value / 10); \
+			value %= 10; \
+		} else if (value == 10) { \
+			_debug_uart_putc('1'); \
+			value = 0; \
+		} \
+		_debug_uart_putc('0' + value); \
+	} \
+\
+	void debug_uart_init(void) \
+	{ \
+		board_debug_uart_init(); \
+		_debug_uart_init(); \
+		_DEBUG_UART_ANNOUNCE \
+	} \
+
+#endif
diff --git a/include/dfu.h b/include/dfu.h
new file mode 100644
index 0000000..145a157
--- /dev/null
+++ b/include/dfu.h
@@ -0,0 +1,275 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * dfu.h - DFU flashable area description
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * authors: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
+ *	    Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __DFU_ENTITY_H_
+#define __DFU_ENTITY_H_
+
+#include <common.h>
+#include <linux/list.h>
+#include <mmc.h>
+#include <spi_flash.h>
+#include <linux/usb/composite.h>
+
+enum dfu_device_type {
+	DFU_DEV_MMC = 1,
+	DFU_DEV_ONENAND,
+	DFU_DEV_NAND,
+	DFU_DEV_RAM,
+	DFU_DEV_SF,
+};
+
+enum dfu_layout {
+	DFU_RAW_ADDR = 1,
+	DFU_FS_FAT,
+	DFU_FS_EXT2,
+	DFU_FS_EXT3,
+	DFU_FS_EXT4,
+	DFU_RAM_ADDR,
+};
+
+enum dfu_op {
+	DFU_OP_READ = 1,
+	DFU_OP_WRITE,
+	DFU_OP_SIZE,
+};
+
+struct mmc_internal_data {
+	int dev_num;
+
+	/* RAW programming */
+	unsigned int lba_start;
+	unsigned int lba_size;
+	unsigned int lba_blk_size;
+
+	/* eMMC HW partition access */
+	int hw_partition;
+
+	/* FAT/EXT */
+	unsigned int dev;
+	unsigned int part;
+};
+
+struct nand_internal_data {
+	/* RAW programming */
+	u64 start;
+	u64 size;
+
+	unsigned int dev;
+	unsigned int part;
+	/* for nand/ubi use */
+	unsigned int ubi;
+};
+
+struct ram_internal_data {
+	void		*start;
+	unsigned int	size;
+};
+
+struct sf_internal_data {
+	struct spi_flash *dev;
+
+	/* RAW programming */
+	u64 start;
+	u64 size;
+};
+
+#define DFU_NAME_SIZE			32
+#ifndef CONFIG_SYS_DFU_DATA_BUF_SIZE
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE		(1024*1024*8)	/* 8 MiB */
+#endif
+#ifndef CONFIG_SYS_DFU_MAX_FILE_SIZE
+#define CONFIG_SYS_DFU_MAX_FILE_SIZE CONFIG_SYS_DFU_DATA_BUF_SIZE
+#endif
+#ifndef DFU_DEFAULT_POLL_TIMEOUT
+#define DFU_DEFAULT_POLL_TIMEOUT 0
+#endif
+#ifndef DFU_MANIFEST_POLL_TIMEOUT
+#define DFU_MANIFEST_POLL_TIMEOUT	DFU_DEFAULT_POLL_TIMEOUT
+#endif
+
+struct dfu_entity {
+	char			name[DFU_NAME_SIZE];
+	int                     alt;
+	void                    *dev_private;
+	enum dfu_device_type    dev_type;
+	enum dfu_layout         layout;
+	unsigned long           max_buf_size;
+
+	union {
+		struct mmc_internal_data mmc;
+		struct nand_internal_data nand;
+		struct ram_internal_data ram;
+		struct sf_internal_data sf;
+	} data;
+
+	int (*get_medium_size)(struct dfu_entity *dfu, u64 *size);
+
+	int (*read_medium)(struct dfu_entity *dfu,
+			u64 offset, void *buf, long *len);
+
+	int (*write_medium)(struct dfu_entity *dfu,
+			u64 offset, void *buf, long *len);
+
+	int (*flush_medium)(struct dfu_entity *dfu);
+	unsigned int (*poll_timeout)(struct dfu_entity *dfu);
+
+	void (*free_entity)(struct dfu_entity *dfu);
+
+	struct list_head list;
+
+	/* on the fly state */
+	u32 crc;
+	u64 offset;
+	int i_blk_seq_num;
+	u8 *i_buf;
+	u8 *i_buf_start;
+	u8 *i_buf_end;
+	u64 r_left;
+	long b_left;
+
+	u32 bad_skip;	/* for nand use */
+
+	unsigned int inited:1;
+};
+
+#ifdef CONFIG_SET_DFU_ALT_INFO
+void set_dfu_alt_info(char *interface, char *devstr);
+#endif
+int dfu_config_entities(char *s, char *interface, char *devstr);
+void dfu_free_entities(void);
+void dfu_show_entities(void);
+int dfu_get_alt_number(void);
+const char *dfu_get_dev_type(enum dfu_device_type t);
+const char *dfu_get_layout(enum dfu_layout l);
+struct dfu_entity *dfu_get_entity(int alt);
+char *dfu_extract_token(char** e, int *n);
+void dfu_trigger_reset(void);
+int dfu_get_alt(char *name);
+int dfu_init_env_entities(char *interface, char *devstr);
+unsigned char *dfu_get_buf(struct dfu_entity *dfu);
+unsigned char *dfu_free_buf(void);
+unsigned long dfu_get_buf_size(void);
+bool dfu_usb_get_reset(void);
+
+int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
+int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
+int dfu_flush(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
+
+/*
+ * dfu_defer_flush - pointer to store dfu_entity for deferred flashing.
+ *		     It should be NULL when not used.
+ */
+extern struct dfu_entity *dfu_defer_flush;
+/**
+ * dfu_get_defer_flush - get current value of dfu_defer_flush pointer
+ *
+ * @return - value of the dfu_defer_flush pointer
+ */
+static inline struct dfu_entity *dfu_get_defer_flush(void)
+{
+	return dfu_defer_flush;
+}
+
+/**
+ * dfu_set_defer_flush - set the dfu_defer_flush pointer
+ *
+ * @param dfu - pointer to the dfu_entity, which should be written
+ */
+static inline void dfu_set_defer_flush(struct dfu_entity *dfu)
+{
+	dfu_defer_flush = dfu;
+}
+
+/**
+ * dfu_write_from_mem_addr - write data from memory to DFU managed medium
+ *
+ * This function adds support for writing data starting from fixed memory
+ * address (like $loadaddr) to dfu managed medium (e.g. NAND, MMC, file system)
+ *
+ * @param dfu - dfu entity to which we want to store data
+ * @param buf - fixed memory addres from where data starts
+ * @param size - number of bytes to write
+ *
+ * @return - 0 on success, other value on failure
+ */
+int dfu_write_from_mem_addr(struct dfu_entity *dfu, void *buf, int size);
+
+/* Device specific */
+#if CONFIG_IS_ENABLED(DFU_MMC)
+extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char *s);
+#else
+static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr,
+				      char *s)
+{
+	puts("MMC support not available!\n");
+	return -1;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DFU_NAND)
+extern int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s);
+#else
+static inline int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr,
+				       char *s)
+{
+	puts("NAND support not available!\n");
+	return -1;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DFU_RAM)
+extern int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr, char *s);
+#else
+static inline int dfu_fill_entity_ram(struct dfu_entity *dfu, char *devstr,
+				      char *s)
+{
+	puts("RAM support not available!\n");
+	return -1;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DFU_SF)
+extern int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr, char *s);
+#else
+static inline int dfu_fill_entity_sf(struct dfu_entity *dfu, char *devstr,
+				     char *s)
+{
+	puts("SF support not available!\n");
+	return -1;
+}
+#endif
+
+/**
+ * dfu_tftp_write - Write TFTP data to DFU medium
+ *
+ * This function is storing data received via TFTP on DFU supported medium.
+ *
+ * @param dfu_entity_name - name of DFU entity to write
+ * @param addr - address of data buffer to write
+ * @param len - number of bytes
+ * @param interface - destination DFU medium (e.g. "mmc")
+ * @param devstring - instance number of destination DFU medium (e.g. "1")
+ *
+ * @return 0 on success, otherwise error code
+ */
+#if CONFIG_IS_ENABLED(DFU_TFTP)
+int dfu_tftp_write(char *dfu_entity_name, unsigned int addr, unsigned int len,
+		   char *interface, char *devstring);
+#else
+static inline int dfu_tftp_write(char *dfu_entity_name, unsigned int addr,
+				 unsigned int len, char *interface,
+				 char *devstring)
+{
+	puts("TFTP write support for DFU not available!\n");
+	return -ENOSYS;
+}
+#endif
+
+int dfu_add(struct usb_configuration *c);
+#endif /* __DFU_ENTITY_H_ */
diff --git a/include/dialog_pmic.h b/include/dialog_pmic.h
new file mode 100644
index 0000000..fbfc536
--- /dev/null
+++ b/include/dialog_pmic.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * da9053 register declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ */
+
+#ifndef __DIALOG_PMIC_H__
+#define __DIALOG_PMIC_H__
+
+enum {
+	DA9053_PAGECON0_REG = 0,
+	DA9053_STATUSA_REG,
+	DA9053_STATUSB_REG,
+	DA9053_STATUSC_REG,
+	DA9053_STATUSD_REG,
+	DA9053_EVENTA_REG,
+	DA9053_EVENTB_REG,
+	DA9053_EVENTC_REG,
+	DA9053_EVENTD_REG,
+	DA9053_FAULTLOG_REG,
+	DA9053_IRQMASKA_REG,
+	DA9053_IRQMASKB_REG,
+	DA9053_IRQMASKC_REG,
+	DA9053_IRQMASKD_REG,
+	DA9053_CONTROLA_REG,
+	DA9053_CONTROLB_REG,
+	DA9053_CONTROLC_REG,
+	DA9053_CONTROLD_REG,
+	DA9053_PDDIS_REG,
+	DA9053_INTERFACE_REG,
+	DA9053_RESET_REG,
+	DA9053_GPIO0001_REG,
+	DA9053_GPIO0203_REG,
+	DA9053_GPIO0405_REG,
+	DA9053_GPIO0607_REG,
+	DA9053_GPIO0809_REG,
+	DA9053_GPIO1011_REG,
+	DA9053_GPIO1213_REG,
+	DA9053_GPIO1415_REG,
+	DA9053_ID01_REG,
+	DA9053_ID23_REG,
+	DA9053_ID45_REG,
+	DA9053_ID67_REG,
+	DA9053_ID89_REG,
+	DA9053_ID1011_REG,
+	DA9053_ID1213_REG,
+	DA9053_ID1415_REG,
+	DA9053_ID1617_REG,
+	DA9053_ID1819_REG,
+	DA9053_ID2021_REG,
+	DA9053_SEQSTATUS_REG,
+	DA9053_SEQA_REG,
+	DA9053_SEQB_REG,
+	DA9053_SEQTIMER_REG,
+	DA9053_BUCKA_REG,
+	DA9053_BUCKB_REG,
+	DA9053_BUCKCORE_REG,
+	DA9053_BUCKPRO_REG,
+	DA9053_BUCKMEM_REG,
+	DA9053_BUCKPERI_REG,
+	DA9053_LDO1_REG,
+	DA9053_LDO2_REG,
+	DA9053_LDO3_REG,
+	DA9053_LDO4_REG,
+	DA9053_LDO5_REG,
+	DA9053_LDO6_REG,
+	DA9053_LDO7_REG,
+	DA9053_LDO8_REG,
+	DA9053_LDO9_REG,
+	DA9053_LDO10_REG,
+	DA9053_SUPPLY_REG,
+	DA9053_PULLDOWN_REG,
+	DA9053_CHGBUCK_REG,
+	DA9053_WAITCONT_REG,
+	DA9053_ISET_REG,
+	DA9053_BATCHG_REG,
+	DA9053_CHGCONT_REG,
+	DA9053_INPUTCONT_REG,
+	DA9053_CHGTIME_REG,
+	DA9053_BBATCONT_REG,
+	DA9053_BOOST_REG,
+	DA9053_LEDCONT_REG,
+	DA9053_LEDMIN123_REG,
+	DA9053_LED1CONF_REG,
+	DA9053_LED2CONF_REG,
+	DA9053_LED3CONF_REG,
+	DA9053_LED1CONT_REG,
+	DA9053_LED2CONT_REG,
+	DA9053_LED3CONT_REG,
+	DA9053_LED4CONT_REG,
+	DA9053_LED5CONT_REG,
+	DA9053_ADCMAN_REG,
+	DA9053_ADCCONT_REG,
+	DA9053_ADCRESL_REG,
+	DA9053_ADCRESH_REG,
+	DA9053_VDDRES_REG,
+	DA9053_VDDMON_REG,
+	DA9053_ICHGAV_REG,
+	DA9053_ICHGTHD_REG,
+	DA9053_ICHGEND_REG,
+	DA9053_TBATRES_REG,
+	DA9053_TBATHIGHP_REG,
+	DA9053_TBATHIGHIN_REG,
+	DA9053_TBATLOW_REG,
+	DA9053_TOFFSET_REG,
+	DA9053_ADCIN4RES_REG,
+	DA9053_AUTO4HIGH_REG,
+	DA9053_AUTO4LOW_REG,
+	DA9053_ADCIN5RES_REG,
+	DA9053_AUTO5HIGH_REG,
+	DA9053_AUTO5LOW_REG,
+	DA9053_ADCIN6RES_REG,
+	DA9053_AUTO6HIGH_REG,
+	DA9053_AUTO6LOW_REG,
+	DA9053_TJUNCRES_REG,
+	DA9053_TSICONTA_REG,
+	DA9053_TSICONTB_REG,
+	DA9053_TSIXMSB_REG,
+	DA9053_TSIYMSB_REG,
+	DA9053_TSILSB_REG,
+	DA9053_TSIZMSB_REG,
+	DA9053_COUNTS_REG,
+	DA9053_COUNTMI_REG,
+	DA9053_COUNTH_REG,
+	DA9053_COUNTD_REG,
+	DA9053_COUNTMO_REG,
+	DA9053_COUNTY_REG,
+	DA9053_ALARMMI_REG,
+	DA9053_ALARMH_REG,
+	DA9053_ALARMD_REG,
+	DA9053_ALARMMO_REG,
+	DA9053_ALARMY_REG,
+	DA9053_SECONDA_REG,
+	DA9053_SECONDB_REG,
+	DA9053_SECONDC_REG,
+	DA9053_SECONDD_REG,
+	DA9053_PAGECON128_REG,
+	DA9053_CHIPID_REG,
+	DA9053_CONFIGID_REG,
+	DA9053_OTPCONT_REG,
+	DA9053_OSCTRIM_REG,
+	DA9053_GPID0_REG,
+	DA9053_GPID1_REG,
+	DA9053_GPID2_REG,
+	DA9053_GPID3_REG,
+	DA9053_GPID4_REG,
+	DA9053_GPID5_REG,
+	DA9053_GPID6_REG,
+	DA9053_GPID7_REG,
+	DA9053_GPID8_REG,
+	DA9053_GPID9_REG,
+	DIALOG_NUM_OF_REGS,
+};
+
+#define DA_BUCKCORE_VBCORE_1_250V		0x1E
+
+/* BUCKCORE REGISTER */
+#define DA9052_BUCKCORE_BCORECONF               (1 << 7)
+#define DA9052_BUCKCORE_BCOREEN                 (1 << 6)
+#define DA9052_BUCKCORE_VBCORE                  63
+
+/* SUPPLY REGISTER */
+#define DA9052_SUPPLY_VLOCK                     (1 << 7)
+#define DA9052_SUPPLY_VMEMSWEN                  (1 << 6)
+#define DA9052_SUPPLY_VPERISWEN                 (1 << 5)
+#define DA9052_SUPPLY_VLDO3GO                   (1 << 4)
+#define DA9052_SUPPLY_VLDO2GO                   (1 << 3)
+#define DA9052_SUPPLY_VBMEMGO                   (1 << 2)
+#define DA9052_SUPPLY_VBPROGO                   (1 << 1)
+#define DA9052_SUPPLY_VBCOREGO                  (1 << 0)
+
+#endif /* __DIALOG_PMIC_H__ */
diff --git a/include/display.h b/include/display.h
new file mode 100644
index 0000000..6629461
--- /dev/null
+++ b/include/display.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Google Inc.
+ */
+
+#ifndef _DISPLAY_H
+#define _DISPLAY_H
+
+struct udevice;
+struct display_timing;
+
+/**
+ * Display uclass platform data for each device
+ *
+ * @source_id:	ID for the source of the display data, typically a video
+ * controller
+ * @src_dev:	Source device providing the video
+ * @in_use:	Display is being used
+ */
+struct display_plat {
+	int source_id;
+	struct udevice *src_dev;
+	bool in_use;
+};
+
+/**
+ * display_read_timing() - Read timing information
+ *
+ * @dev:	Device to read from
+ * @return 0 if OK, -ve on error
+ */
+int display_read_timing(struct udevice *dev, struct display_timing *timing);
+
+/**
+ * display_port_enable() - Enable a display port device
+ *
+ * @dev:	Device to enable
+ * @panel_bpp:	Number of bits per pixel for panel
+ * @timing:	Display timings
+ * @return 0 if OK, -ve on error
+ */
+int display_enable(struct udevice *dev, int panel_bpp,
+		   const struct display_timing *timing);
+
+/**
+ * display_in_use() - Check if a display is in use by any device
+ *
+ * @return true if the device is in use (display_enable() has been called
+ * successfully), else false
+ */
+bool display_in_use(struct udevice *dev);
+
+struct dm_display_ops {
+	/**
+	 * read_timing() - Read information directly
+	 *
+	 * @dev:	Device to read from
+	 * @timing:	Display timings
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*read_timing)(struct udevice *dev, struct display_timing *timing);
+
+	/**
+	 * read_edid() - Read information from EDID
+	 *
+	 * @dev:	Device to read from
+	 * @buf:	Buffer to read into (should be EDID_SIZE bytes)
+	 * @buf_size:	Buffer size (should be EDID_SIZE)
+	 * @return number of bytes read, <=0 for error
+	 */
+	int (*read_edid)(struct udevice *dev, u8 *buf, int buf_size);
+
+	/**
+	 * enable() - Enable the display port device
+	 *
+	 * @dev:	Device to enable
+	 * @panel_bpp:	Number of bits per pixel for panel
+	 * @timing:	Display timings
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*enable)(struct udevice *dev, int panel_bpp,
+		      const struct display_timing *timing);
+
+	/**
+	 * mode_valid() - Check if mode is supported
+	 *
+	 * @dev:	Device to enable
+	 * @timing:	Display timings
+	 * @return true if supported, false if not
+	 */
+	bool (*mode_valid)(struct udevice *dev,
+			   const struct display_timing *timing);
+};
+
+#define display_get_ops(dev)	((struct dm_display_ops *)(dev)->driver->ops)
+
+#endif
diff --git a/include/display_options.h b/include/display_options.h
new file mode 100644
index 0000000..a0dabca
--- /dev/null
+++ b/include/display_options.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __DISPLAY_OPTIONS_H
+#define __DISPLAY_OPTIONS_H
+
+/**
+ * print_size() - Print a size with a suffix
+ *
+ * Print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB",
+ * xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string
+ * (like "\n")
+ *
+ * @size:	Size to print
+ * @suffix	String to print after the size
+ */
+void print_size(uint64_t size, const char *suffix);
+
+/**
+ * print_freq() - Print a frequency with a suffix
+ *
+ * Print frequencies as "x.xx GHz", "xxx KHz", etc as needed; allow for
+ * optional trailing string (like "\n")
+ *
+ * @freq:	Frequency to print in Hz
+ * @suffix	String to print after the frequency
+ */
+void print_freq(uint64_t freq, const char *suffix);
+
+/**
+ * print_buffer() - Print data buffer in hex and ascii form
+ *
+ * Data reads are buffered so that each memory address is only read once.
+ * This is useful when displaying the contents of volatile registers.
+ *
+ * @addr:	Starting address to display at start of line
+ * @data:	pointer to data buffer
+ * @width:	data value width.  May be 1, 2, or 4.
+ * @count:	number of values to display
+ * @linelen:	Number of values to print per line; specify 0 for default length
+ */
+int print_buffer(ulong addr, const void *data, uint width, uint count,
+		 uint linelen);
+
+/**
+ * display_options() - display the version string / build tag
+ *
+ * This displays the U-Boot version string. If a build tag is available this
+ * is displayed also.
+ */
+int display_options(void);
+
+/* Suggested length of the buffer to pass to display_options_get_banner() */
+#define DISPLAY_OPTIONS_BANNER_LENGTH	200
+
+/**
+ * display_options_get_banner() - Get the U-Boot banner as a string
+ *
+ * This returns the U-Boot banner string
+ *
+ * @newlines: true to include two newlines at the start
+ * @buf: place to put string
+ * @size: Size of buf (string is truncated to fit)
+ * @return buf
+ */
+char *display_options_get_banner(bool newlines, char *buf, int size);
+
+/* This function is used for testing only */
+char *display_options_get_banner_priv(bool newlines, const char *build_tag,
+				      char *buf, int size);
+
+#endif
diff --git a/include/div64.h b/include/div64.h
new file mode 100644
index 0000000..8b92d2b
--- /dev/null
+++ b/include/div64.h
@@ -0,0 +1,244 @@
+#ifndef _ASM_GENERIC_DIV64_H
+#define _ASM_GENERIC_DIV64_H
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
+ *
+ * Optimization for constant divisors on 32-bit machines:
+ * Copyright (C) 2006-2015 Nicolas Pitre
+ *
+ * The semantics of do_div() are:
+ *
+ * u32 do_div(u64 *n, u32 base)
+ * {
+ *	u32 remainder = *n % base;
+ *	*n = *n / base;
+ *	return remainder;
+ * }
+ *
+ * NOTE: macro parameter n is evaluated multiple times,
+ *       beware of side effects!
+ */
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+#if BITS_PER_LONG == 64
+
+# define do_div(n,base) ({					\
+	u32 __base = (base);				\
+	u32 __rem;						\
+	__rem = ((u64)(n)) % __base;			\
+	(n) = ((u64)(n)) / __base;				\
+	__rem;							\
+ })
+
+#elif BITS_PER_LONG == 32
+
+#include <linux/log2.h>
+
+/*
+ * If the divisor happens to be constant, we determine the appropriate
+ * inverse at compile time to turn the division into a few inline
+ * multiplications which ought to be much faster. And yet only if compiling
+ * with a sufficiently recent gcc version to perform proper 64-bit constant
+ * propagation.
+ *
+ * (It is unfortunate that gcc doesn't perform all this internally.)
+ */
+
+#ifndef __div64_const32_is_OK
+#define __div64_const32_is_OK (__GNUC__ >= 4)
+#endif
+
+#define __div64_const32(n, ___b)					\
+({									\
+	/*								\
+	 * Multiplication by reciprocal of b: n / b = n * (p / b) / p	\
+	 *								\
+	 * We rely on the fact that most of this code gets optimized	\
+	 * away at compile time due to constant propagation and only	\
+	 * a few multiplication instructions should remain.		\
+	 * Hence this monstrous macro (static inline doesn't always	\
+	 * do the trick here).						\
+	 */								\
+	u64 ___res, ___x, ___t, ___m, ___n = (n);			\
+	u32 ___p, ___bias;						\
+									\
+	/* determine MSB of b */					\
+	___p = 1 << ilog2(___b);					\
+									\
+	/* compute m = ((p << 64) + b - 1) / b */			\
+	___m = (~0ULL / ___b) * ___p;					\
+	___m += (((~0ULL % ___b + 1) * ___p) + ___b - 1) / ___b;	\
+									\
+	/* one less than the dividend with highest result */		\
+	___x = ~0ULL / ___b * ___b - 1;					\
+									\
+	/* test our ___m with res = m * x / (p << 64) */		\
+	___res = ((___m & 0xffffffff) * (___x & 0xffffffff)) >> 32;	\
+	___t = ___res += (___m & 0xffffffff) * (___x >> 32);		\
+	___res += (___x & 0xffffffff) * (___m >> 32);			\
+	___t = (___res < ___t) ? (1ULL << 32) : 0;			\
+	___res = (___res >> 32) + ___t;					\
+	___res += (___m >> 32) * (___x >> 32);				\
+	___res /= ___p;							\
+									\
+	/* Now sanitize and optimize what we've got. */			\
+	if (~0ULL % (___b / (___b & -___b)) == 0) {			\
+		/* special case, can be simplified to ... */		\
+		___n /= (___b & -___b);					\
+		___m = ~0ULL / (___b / (___b & -___b));			\
+		___p = 1;						\
+		___bias = 1;						\
+	} else if (___res != ___x / ___b) {				\
+		/*							\
+		 * We can't get away without a bias to compensate	\
+		 * for bit truncation errors.  To avoid it we'd need an	\
+		 * additional bit to represent m which would overflow	\
+		 * a 64-bit variable.					\
+		 *							\
+		 * Instead we do m = p / b and n / b = (n * m + m) / p.	\
+		 */							\
+		___bias = 1;						\
+		/* Compute m = (p << 64) / b */				\
+		___m = (~0ULL / ___b) * ___p;				\
+		___m += ((~0ULL % ___b + 1) * ___p) / ___b;		\
+	} else {							\
+		/*							\
+		 * Reduce m / p, and try to clear bit 31 of m when	\
+		 * possible, otherwise that'll need extra overflow	\
+		 * handling later.					\
+		 */							\
+		u32 ___bits = -(___m & -___m);			\
+		___bits |= ___m >> 32;					\
+		___bits = (~___bits) << 1;				\
+		/*							\
+		 * If ___bits == 0 then setting bit 31 is  unavoidable.	\
+		 * Simply apply the maximum possible reduction in that	\
+		 * case. Otherwise the MSB of ___bits indicates the	\
+		 * best reduction we should apply.			\
+		 */							\
+		if (!___bits) {						\
+			___p /= (___m & -___m);				\
+			___m /= (___m & -___m);				\
+		} else {						\
+			___p >>= ilog2(___bits);			\
+			___m >>= ilog2(___bits);			\
+		}							\
+		/* No bias needed. */					\
+		___bias = 0;						\
+	}								\
+									\
+	/*								\
+	 * Now we have a combination of 2 conditions:			\
+	 *								\
+	 * 1) whether or not we need to apply a bias, and		\
+	 *								\
+	 * 2) whether or not there might be an overflow in the cross	\
+	 *    product determined by (___m & ((1 << 63) | (1 << 31))).	\
+	 *								\
+	 * Select the best way to do (m_bias + m * n) / (1 << 64).	\
+	 * From now on there will be actual runtime code generated.	\
+	 */								\
+	___res = __arch_xprod_64(___m, ___n, ___bias);			\
+									\
+	___res /= ___p;							\
+})
+
+#ifndef __arch_xprod_64
+/*
+ * Default C implementation for __arch_xprod_64()
+ *
+ * Prototype: u64 __arch_xprod_64(const u64 m, u64 n, bool bias)
+ * Semantic:  retval = ((bias ? m : 0) + m * n) >> 64
+ *
+ * The product is a 128-bit value, scaled down to 64 bits.
+ * Assuming constant propagation to optimize away unused conditional code.
+ * Architectures may provide their own optimized assembly implementation.
+ */
+static inline u64 __arch_xprod_64(const u64 m, u64 n, bool bias)
+{
+	u32 m_lo = m;
+	u32 m_hi = m >> 32;
+	u32 n_lo = n;
+	u32 n_hi = n >> 32;
+	u64 res, tmp;
+
+	if (!bias) {
+		res = ((u64)m_lo * n_lo) >> 32;
+	} else if (!(m & ((1ULL << 63) | (1ULL << 31)))) {
+		/* there can't be any overflow here */
+		res = (m + (u64)m_lo * n_lo) >> 32;
+	} else {
+		res = m + (u64)m_lo * n_lo;
+		tmp = (res < m) ? (1ULL << 32) : 0;
+		res = (res >> 32) + tmp;
+	}
+
+	if (!(m & ((1ULL << 63) | (1ULL << 31)))) {
+		/* there can't be any overflow here */
+		res += (u64)m_lo * n_hi;
+		res += (u64)m_hi * n_lo;
+		res >>= 32;
+	} else {
+		tmp = res += (u64)m_lo * n_hi;
+		res += (u64)m_hi * n_lo;
+		tmp = (res < tmp) ? (1ULL << 32) : 0;
+		res = (res >> 32) + tmp;
+	}
+
+	res += (u64)m_hi * n_hi;
+
+	return res;
+}
+#endif
+
+#ifndef __div64_32
+extern u32 __div64_32(u64 *dividend, u32 divisor);
+#endif
+
+/* The unnecessary pointer compare is there
+ * to check for type safety (n must be 64bit)
+ */
+# define do_div(n,base) ({				\
+	u32 __base = (base);			\
+	u32 __rem;					\
+	(void)(((typeof((n)) *)0) == ((u64 *)0));	\
+	if (__builtin_constant_p(__base) &&		\
+	    is_power_of_2(__base)) {			\
+		__rem = (n) & (__base - 1);		\
+		(n) >>= ilog2(__base);			\
+	} else if (__div64_const32_is_OK &&		\
+		   __builtin_constant_p(__base) &&	\
+		   __base != 0) {			\
+		u32 __res_lo, __n_lo = (n);	\
+		(n) = __div64_const32(n, __base);	\
+		/* the remainder can be computed with 32-bit regs */ \
+		__res_lo = (n);				\
+		__rem = __n_lo - __res_lo * __base;	\
+	} else if (likely(((n) >> 32) == 0)) {		\
+		__rem = (u32)(n) % __base;		\
+		(n) = (u32)(n) / __base;		\
+	} else 						\
+		__rem = __div64_32(&(n), __base);	\
+	__rem;						\
+ })
+
+#else /* BITS_PER_LONG == ?? */
+
+# error do_div() does not yet support the C64
+
+#endif /* BITS_PER_LONG */
+
+/* Wrapper for do_div(). Doesn't modify dividend and returns
+ * the result, not remainder.
+ */
+static inline u64 lldiv(u64 dividend, u32 divisor)
+{
+	u64 __res = dividend;
+	do_div(__res, divisor);
+	return(__res);
+}
+
+#endif /* _ASM_GENERIC_DIV64_H */
diff --git a/include/dm-demo.h b/include/dm-demo.h
new file mode 100644
index 0000000..c9a82c7
--- /dev/null
+++ b/include/dm-demo.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ */
+
+#ifndef __DM_DEMO_H
+#define __DM_DEMO_H
+
+#include <dm.h>
+
+/**
+ * struct dm_demo_pdata - configuration data for demo instance
+ *
+ * @colour: Color of the demo
+ * @sides: Numbers of sides
+ * @default_char: Default ASCII character to output (65 = 'A')
+ */
+struct dm_demo_pdata {
+	const char *colour;
+	int sides;
+	int default_char;
+};
+
+struct demo_ops {
+	int (*hello)(struct udevice *dev, int ch);
+	int (*status)(struct udevice *dev, int *status);
+	int (*set_light)(struct udevice *dev, int light);
+	int (*get_light)(struct udevice *dev);
+};
+
+int demo_hello(struct udevice *dev, int ch);
+int demo_status(struct udevice *dev, int *status);
+int demo_set_light(struct udevice *dev, int light);
+int demo_get_light(struct udevice *dev);
+int demo_list(void);
+
+int demo_parse_dt(struct udevice *dev);
+
+#endif
diff --git a/include/dm.h b/include/dm.h
new file mode 100644
index 0000000..2e1afda
--- /dev/null
+++ b/include/dm.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ */
+
+#ifndef _DM_H_
+#define _DM_H_
+
+#include <dm/device.h>
+#include <dm/fdtaddr.h>
+#include <dm/ofnode.h>
+#include <dm/read.h>
+#include <dm/platdata.h>
+#include <dm/uclass.h>
+
+#endif
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
new file mode 100644
index 0000000..ee2b24a
--- /dev/null
+++ b/include/dm/device-internal.h
@@ -0,0 +1,219 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ */
+
+#ifndef _DM_DEVICE_INTERNAL_H
+#define _DM_DEVICE_INTERNAL_H
+
+#include <dm/ofnode.h>
+
+struct device_node;
+struct udevice;
+
+/**
+ * device_bind() - Create a device and bind it to a driver
+ *
+ * Called to set up a new device attached to a driver. The device will either
+ * have platdata, or a device tree node which can be used to create the
+ * platdata.
+ *
+ * Once bound a device exists but is not yet active until device_probe() is
+ * called.
+ *
+ * @parent: Pointer to device's parent, under which this driver will exist
+ * @drv: Device's driver
+ * @name: Name of device (e.g. device tree node name)
+ * @platdata: Pointer to data for this device - the structure is device-
+ * specific but may include the device's I/O address, etc.. This is NULL for
+ * devices which use device tree.
+ * @of_offset: Offset of device tree node for this device. This is -1 for
+ * devices which don't use device tree.
+ * @devp: if non-NULL, returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind(struct udevice *parent, const struct driver *drv,
+		const char *name, void *platdata, int of_offset,
+		struct udevice **devp);
+
+int device_bind_ofnode(struct udevice *parent, const struct driver *drv,
+		       const char *name, void *platdata, ofnode node,
+		       struct udevice **devp);
+
+/**
+ * device_bind_with_driver_data() - Create a device and bind it to a driver
+ *
+ * Called to set up a new device attached to a driver, in the case where the
+ * driver was matched to the device by means of a match table that provides
+ * driver_data.
+ *
+ * Once bound a device exists but is not yet active until device_probe() is
+ * called.
+ *
+ * @parent: Pointer to device's parent, under which this driver will exist
+ * @drv: Device's driver
+ * @name: Name of device (e.g. device tree node name)
+ * @driver_data: The driver_data field from the driver's match table.
+ * @node: Device tree node for this device. This is invalid for devices which
+ * don't use device tree.
+ * @devp: if non-NULL, returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind_with_driver_data(struct udevice *parent,
+				 const struct driver *drv, const char *name,
+				 ulong driver_data, ofnode node,
+				 struct udevice **devp);
+/**
+ * device_bind_by_name: Create a device and bind it to a driver
+ *
+ * This is a helper function used to bind devices which do not use device
+ * tree.
+ *
+ * @parent: Pointer to device's parent
+ * @pre_reloc_only: If true, bind the driver only if its DM_FLAG_PRE_RELOC flag
+ * is set. If false bind the driver always.
+ * @info: Name and platdata for this device
+ * @devp: if non-NULL, returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
+			const struct driver_info *info, struct udevice **devp);
+
+/**
+ * device_probe() - Probe a device, activating it
+ *
+ * Activate a device so that it is ready for use. All its parents are probed
+ * first.
+ *
+ * @dev: Pointer to device to probe
+ * @return 0 if OK, -ve on error
+ */
+int device_probe(struct udevice *dev);
+
+/**
+ * device_remove() - Remove a device, de-activating it
+ *
+ * De-activate a device so that it is no longer ready for use. All its
+ * children are deactivated first.
+ *
+ * @dev: Pointer to device to remove
+ * @flags: Flags for selective device removal (DM_REMOVE_...)
+ * @return 0 if OK, -ve on error (an error here is normally a very bad thing)
+ */
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+int device_remove(struct udevice *dev, uint flags);
+#else
+static inline int device_remove(struct udevice *dev, uint flags) { return 0; }
+#endif
+
+/**
+ * device_unbind() - Unbind a device, destroying it
+ *
+ * Unbind a device and remove all memory used by it
+ *
+ * @dev: Pointer to device to unbind
+ * @return 0 if OK, -ve on error
+ */
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+int device_unbind(struct udevice *dev);
+#else
+static inline int device_unbind(struct udevice *dev) { return 0; }
+#endif
+
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+void device_free(struct udevice *dev);
+#else
+static inline void device_free(struct udevice *dev) {}
+#endif
+
+/**
+ * device_chld_unbind() - Unbind all device's children from the device if bound
+ *			  to drv
+ *
+ * On error, the function continues to unbind all children, and reports the
+ * first error.
+ *
+ * @dev:	The device that is to be stripped of its children
+ * @drv:	The targeted driver
+ * @return 0 on success, -ve on error
+ */
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+int device_chld_unbind(struct udevice *dev, struct driver *drv);
+#else
+static inline int device_chld_unbind(struct udevice *dev, struct driver *drv)
+{
+	return 0;
+}
+#endif
+
+/**
+ * device_chld_remove() - Stop all device's children
+ * @dev:	The device whose children are to be removed
+ * @drv:	The targeted driver
+ * @flags:	Flag, if this functions is called in the pre-OS stage
+ * @return 0 on success, -ve on error
+ */
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+int device_chld_remove(struct udevice *dev, struct driver *drv,
+		       uint flags);
+#else
+static inline int device_chld_remove(struct udevice *dev, struct driver *drv,
+				     uint flags)
+{
+	return 0;
+}
+#endif
+
+/**
+ * simple_bus_translate() - translate a bus address to a system address
+ *
+ * This handles the 'ranges' property in a simple bus. It translates the
+ * device address @addr to a system address using this property.
+ *
+ * @dev:	Simple bus device (parent of target device)
+ * @addr:	Address to translate
+ * @return new address
+ */
+fdt_addr_t simple_bus_translate(struct udevice *dev, fdt_addr_t addr);
+
+/* Cast away any volatile pointer */
+#define DM_ROOT_NON_CONST		(((gd_t *)gd)->dm_root)
+#define DM_UCLASS_ROOT_NON_CONST	(((gd_t *)gd)->uclass_root)
+
+/* device resource management */
+#ifdef CONFIG_DEVRES
+
+/**
+ * devres_release_probe - Release managed resources allocated after probing
+ * @dev: Device to release resources for
+ *
+ * Release all resources allocated for @dev when it was probed or later.
+ * This function is called on driver removal.
+ */
+void devres_release_probe(struct udevice *dev);
+
+/**
+ * devres_release_all - Release all managed resources
+ * @dev: Device to release resources for
+ *
+ * Release all resources associated with @dev.  This function is
+ * called on driver unbinding.
+ */
+void devres_release_all(struct udevice *dev);
+
+#else /* ! CONFIG_DEVRES */
+
+static inline void devres_release_probe(struct udevice *dev)
+{
+}
+
+static inline void devres_release_all(struct udevice *dev)
+{
+}
+
+#endif /* ! CONFIG_DEVRES */
+#endif
diff --git a/include/dm/device.h b/include/dm/device.h
new file mode 100644
index 0000000..d7ad9d6
--- /dev/null
+++ b/include/dm/device.h
@@ -0,0 +1,1045 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ */
+
+#ifndef _DM_DEVICE_H
+#define _DM_DEVICE_H
+
+#include <dm/ofnode.h>
+#include <dm/uclass-id.h>
+#include <fdtdec.h>
+#include <linker_lists.h>
+#include <linux/compat.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/printk.h>
+
+struct driver_info;
+
+/* Driver is active (probed). Cleared when it is removed */
+#define DM_FLAG_ACTIVATED		(1 << 0)
+
+/* DM is responsible for allocating and freeing platdata */
+#define DM_FLAG_ALLOC_PDATA		(1 << 1)
+
+/* DM should init this device prior to relocation */
+#define DM_FLAG_PRE_RELOC		(1 << 2)
+
+/* DM is responsible for allocating and freeing parent_platdata */
+#define DM_FLAG_ALLOC_PARENT_PDATA	(1 << 3)
+
+/* DM is responsible for allocating and freeing uclass_platdata */
+#define DM_FLAG_ALLOC_UCLASS_PDATA	(1 << 4)
+
+/* Allocate driver private data on a DMA boundary */
+#define DM_FLAG_ALLOC_PRIV_DMA		(1 << 5)
+
+/* Device is bound */
+#define DM_FLAG_BOUND			(1 << 6)
+
+/* Device name is allocated and should be freed on unbind() */
+#define DM_FLAG_NAME_ALLOCED		(1 << 7)
+
+#define DM_FLAG_OF_PLATDATA		(1 << 8)
+
+/*
+ * Call driver remove function to stop currently active DMA transfers or
+ * give DMA buffers back to the HW / controller. This may be needed for
+ * some drivers to do some final stage cleanup before the OS is called
+ * (U-Boot exit)
+ */
+#define DM_FLAG_ACTIVE_DMA		(1 << 9)
+
+/*
+ * Call driver remove function to do some final configuration, before
+ * U-Boot exits and the OS is started
+ */
+#define DM_FLAG_OS_PREPARE		(1 << 10)
+
+/* DM does not enable/disable the power domains corresponding to this device */
+#define DM_FLAG_DEFAULT_PD_CTRL_OFF	(1 << 11)
+
+/*
+ * One or multiple of these flags are passed to device_remove() so that
+ * a selective device removal as specified by the remove-stage and the
+ * driver flags can be done.
+ */
+enum {
+	/* Normal remove, remove all devices */
+	DM_REMOVE_NORMAL     = 1 << 0,
+
+	/* Remove devices with active DMA */
+	DM_REMOVE_ACTIVE_DMA = DM_FLAG_ACTIVE_DMA,
+
+	/* Remove devices which need some final OS preparation steps */
+	DM_REMOVE_OS_PREPARE = DM_FLAG_OS_PREPARE,
+
+	/* Add more use cases here */
+
+	/* Remove devices with any active flag */
+	DM_REMOVE_ACTIVE_ALL = DM_REMOVE_ACTIVE_DMA | DM_REMOVE_OS_PREPARE,
+};
+
+/**
+ * struct udevice - An instance of a driver
+ *
+ * This holds information about a device, which is a driver bound to a
+ * particular port or peripheral (essentially a driver instance).
+ *
+ * A device will come into existence through a 'bind' call, either due to
+ * a U_BOOT_DEVICE() macro (in which case platdata is non-NULL) or a node
+ * in the device tree (in which case of_offset is >= 0). In the latter case
+ * we translate the device tree information into platdata in a function
+ * implemented by the driver ofdata_to_platdata method (called just before the
+ * probe method if the device has a device tree node.
+ *
+ * All three of platdata, priv and uclass_priv can be allocated by the
+ * driver, or you can use the auto_alloc_size members of struct driver and
+ * struct uclass_driver to have driver model do this automatically.
+ *
+ * @driver: The driver used by this device
+ * @name: Name of device, typically the FDT node name
+ * @platdata: Configuration data for this device
+ * @parent_platdata: The parent bus's configuration data for this device
+ * @uclass_platdata: The uclass's configuration data for this device
+ * @node: Reference to device tree node for this device
+ * @driver_data: Driver data word for the entry that matched this device with
+ *		its driver
+ * @parent: Parent of this device, or NULL for the top level device
+ * @priv: Private data for this device
+ * @uclass: Pointer to uclass for this device
+ * @uclass_priv: The uclass's private data for this device
+ * @parent_priv: The parent's private data for this device
+ * @uclass_node: Used by uclass to link its devices
+ * @child_head: List of children of this device
+ * @sibling_node: Next device in list of all devices
+ * @flags: Flags for this device DM_FLAG_...
+ * @req_seq: Requested sequence number for this device (-1 = any)
+ * @seq: Allocated sequence number for this device (-1 = none). This is set up
+ * when the device is probed and will be unique within the device's uclass.
+ * @devres_head: List of memory allocations associated with this device.
+ *		When CONFIG_DEVRES is enabled, devm_kmalloc() and friends will
+ *		add to this list. Memory so-allocated will be freed
+ *		automatically when the device is removed / unbound
+ */
+struct udevice {
+	const struct driver *driver;
+	const char *name;
+	void *platdata;
+	void *parent_platdata;
+	void *uclass_platdata;
+	ofnode node;
+	ulong driver_data;
+	struct udevice *parent;
+	void *priv;
+	struct uclass *uclass;
+	void *uclass_priv;
+	void *parent_priv;
+	struct list_head uclass_node;
+	struct list_head child_head;
+	struct list_head sibling_node;
+	uint32_t flags;
+	int req_seq;
+	int seq;
+#ifdef CONFIG_DEVRES
+	struct list_head devres_head;
+#endif
+};
+
+/* Maximum sequence number supported */
+#define DM_MAX_SEQ	999
+
+/* Returns the operations for a device */
+#define device_get_ops(dev)	(dev->driver->ops)
+
+/* Returns non-zero if the device is active (probed and not removed) */
+#define device_active(dev)	((dev)->flags & DM_FLAG_ACTIVATED)
+
+static inline int dev_of_offset(const struct udevice *dev)
+{
+	return ofnode_to_offset(dev->node);
+}
+
+static inline void dev_set_of_offset(struct udevice *dev, int of_offset)
+{
+	dev->node = offset_to_ofnode(of_offset);
+}
+
+static inline bool dev_has_of_node(struct udevice *dev)
+{
+	return ofnode_valid(dev->node);
+}
+
+/**
+ * struct udevice_id - Lists the compatible strings supported by a driver
+ * @compatible: Compatible string
+ * @data: Data for this compatible string
+ */
+struct udevice_id {
+	const char *compatible;
+	ulong data;
+};
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+#define of_match_ptr(_ptr)	(_ptr)
+#else
+#define of_match_ptr(_ptr)	NULL
+#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
+
+/**
+ * struct driver - A driver for a feature or peripheral
+ *
+ * This holds methods for setting up a new device, and also removing it.
+ * The device needs information to set itself up - this is provided either
+ * by platdata or a device tree node (which we find by looking up
+ * matching compatible strings with of_match).
+ *
+ * Drivers all belong to a uclass, representing a class of devices of the
+ * same type. Common elements of the drivers can be implemented in the uclass,
+ * or the uclass can provide a consistent interface to the drivers within
+ * it.
+ *
+ * @name: Device name
+ * @id: Identifies the uclass we belong to
+ * @of_match: List of compatible strings to match, and any identifying data
+ * for each.
+ * @bind: Called to bind a device to its driver
+ * @probe: Called to probe a device, i.e. activate it
+ * @remove: Called to remove a device, i.e. de-activate it
+ * @unbind: Called to unbind a device from its driver
+ * @ofdata_to_platdata: Called before probe to decode device tree data
+ * @child_post_bind: Called after a new child has been bound
+ * @child_pre_probe: Called before a child device is probed. The device has
+ * memory allocated but it has not yet been probed.
+ * @child_post_remove: Called after a child device is removed. The device
+ * has memory allocated but its device_remove() method has been called.
+ * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * to be allocated in the device's ->priv pointer. If zero, then the driver
+ * is responsible for allocating any data required.
+ * @platdata_auto_alloc_size: If non-zero this is the size of the
+ * platform data to be allocated in the device's ->platdata pointer.
+ * This is typically only useful for device-tree-aware drivers (those with
+ * an of_match), since drivers which use platdata will have the data
+ * provided in the U_BOOT_DEVICE() instantiation.
+ * @per_child_auto_alloc_size: Each device can hold private data owned by
+ * its parent. If required this will be automatically allocated if this
+ * value is non-zero.
+ * @per_child_platdata_auto_alloc_size: A bus likes to store information about
+ * its children. If non-zero this is the size of this data, to be allocated
+ * in the child's parent_platdata pointer.
+ * @ops: Driver-specific operations. This is typically a list of function
+ * pointers defined by the driver, to implement driver functions required by
+ * the uclass.
+ * @flags: driver flags - see DM_FLAGS_...
+ */
+struct driver {
+	char *name;
+	enum uclass_id id;
+	const struct udevice_id *of_match;
+	int (*bind)(struct udevice *dev);
+	int (*probe)(struct udevice *dev);
+	int (*remove)(struct udevice *dev);
+	int (*unbind)(struct udevice *dev);
+	int (*ofdata_to_platdata)(struct udevice *dev);
+	int (*child_post_bind)(struct udevice *dev);
+	int (*child_pre_probe)(struct udevice *dev);
+	int (*child_post_remove)(struct udevice *dev);
+	int priv_auto_alloc_size;
+	int platdata_auto_alloc_size;
+	int per_child_auto_alloc_size;
+	int per_child_platdata_auto_alloc_size;
+	const void *ops;	/* driver-specific operations */
+	uint32_t flags;
+};
+
+/* Declare a new U-Boot driver */
+#define U_BOOT_DRIVER(__name)						\
+	ll_entry_declare(struct driver, __name, driver)
+
+/* Get a pointer to a given driver */
+#define DM_GET_DRIVER(__name)						\
+	ll_entry_get(struct driver, __name, driver)
+
+/**
+ * dev_get_platdata() - Get the platform data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return platform data, or NULL if none
+ */
+void *dev_get_platdata(const struct udevice *dev);
+
+/**
+ * dev_get_parent_platdata() - Get the parent platform data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return parent's platform data, or NULL if none
+ */
+void *dev_get_parent_platdata(const struct udevice *dev);
+
+/**
+ * dev_get_uclass_platdata() - Get the uclass platform data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return uclass's platform data, or NULL if none
+ */
+void *dev_get_uclass_platdata(const struct udevice *dev);
+
+/**
+ * dev_get_priv() - Get the private data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return private data, or NULL if none
+ */
+void *dev_get_priv(const struct udevice *dev);
+
+/**
+ * dev_get_parent_priv() - Get the parent private data for a device
+ *
+ * The parent private data is data stored in the device but owned by the
+ * parent. For example, a USB device may have parent data which contains
+ * information about how to talk to the device over USB.
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return parent data, or NULL if none
+ */
+void *dev_get_parent_priv(const struct udevice *dev);
+
+/**
+ * dev_get_uclass_priv() - Get the private uclass data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return private uclass data for this device, or NULL if none
+ */
+void *dev_get_uclass_priv(const struct udevice *dev);
+
+/**
+ * struct dev_get_parent() - Get the parent of a device
+ *
+ * @child:	Child to check
+ * @return parent of child, or NULL if this is the root device
+ */
+struct udevice *dev_get_parent(const struct udevice *child);
+
+/**
+ * dev_get_driver_data() - get the driver data used to bind a device
+ *
+ * When a device is bound using a device tree node, it matches a
+ * particular compatible string in struct udevice_id. This function
+ * returns the associated data value for that compatible string. This is
+ * the 'data' field in struct udevice_id.
+ *
+ * As an example, consider this structure:
+ * static const struct udevice_id tegra_i2c_ids[] = {
+ *	{ .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
+ *	{ .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
+ *	{ .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
+ *	{ }
+ * };
+ *
+ * When driver model finds a driver for this it will store the 'data' value
+ * corresponding to the compatible string it matches. This function returns
+ * that value. This allows the driver to handle several variants of a device.
+ *
+ * For USB devices, this is the driver_info field in struct usb_device_id.
+ *
+ * @dev:	Device to check
+ * @return driver data (0 if none is provided)
+ */
+ulong dev_get_driver_data(const struct udevice *dev);
+
+/**
+ * dev_get_driver_ops() - get the device's driver's operations
+ *
+ * This checks that dev is not NULL, and returns the pointer to device's
+ * driver's operations.
+ *
+ * @dev:	Device to check
+ * @return void pointer to driver's operations or NULL for NULL-dev or NULL-ops
+ */
+const void *dev_get_driver_ops(const struct udevice *dev);
+
+/**
+ * device_get_uclass_id() - return the uclass ID of a device
+ *
+ * @dev:	Device to check
+ * @return uclass ID for the device
+ */
+enum uclass_id device_get_uclass_id(const struct udevice *dev);
+
+/**
+ * dev_get_uclass_name() - return the uclass name of a device
+ *
+ * This checks that dev is not NULL.
+ *
+ * @dev:	Device to check
+ * @return  pointer to the uclass name for the device
+ */
+const char *dev_get_uclass_name(const struct udevice *dev);
+
+/**
+ * device_get_child() - Get the child of a device by index
+ *
+ * Returns the numbered child, 0 being the first. This does not use
+ * sequence numbers, only the natural order.
+ *
+ * @dev:	Parent device to check
+ * @index:	Child index
+ * @devp:	Returns pointer to device
+ * @return 0 if OK, -ENODEV if no such device, other error if the device fails
+ *	   to probe
+ */
+int device_get_child(struct udevice *parent, int index, struct udevice **devp);
+
+/**
+ * device_get_child_count() - Get the available child count of a device
+ *
+ * Returns the number of children to a device.
+ *
+ * @parent:	Parent device to check
+ */
+int device_get_child_count(struct udevice *parent);
+
+/**
+ * device_find_child_by_seq() - Find a child device based on a sequence
+ *
+ * This searches for a device with the given seq or req_seq.
+ *
+ * For seq, if an active device has this sequence it will be returned.
+ * If there is no such device then this will return -ENODEV.
+ *
+ * For req_seq, if a device (whether activated or not) has this req_seq
+ * value, that device will be returned. This is a strong indication that
+ * the device will receive that sequence when activated.
+ *
+ * @parent: Parent device
+ * @seq_or_req_seq: Sequence number to find (0=first)
+ * @find_req_seq: true to find req_seq, false to find seq
+ * @devp: Returns pointer to device (there is only one per for each seq).
+ * Set to NULL if none is found
+ * @return 0 if OK, -ve on error
+ */
+int device_find_child_by_seq(struct udevice *parent, int seq_or_req_seq,
+			     bool find_req_seq, struct udevice **devp);
+
+/**
+ * device_get_child_by_seq() - Get a child device based on a sequence
+ *
+ * If an active device has this sequence it will be returned. If there is no
+ * such device then this will check for a device that is requesting this
+ * sequence.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @parent: Parent device
+ * @seq: Sequence number to find (0=first)
+ * @devp: Returns pointer to device (there is only one per for each seq)
+ * Set to NULL if none is found
+ * @return 0 if OK, -ve on error
+ */
+int device_get_child_by_seq(struct udevice *parent, int seq,
+			    struct udevice **devp);
+
+/**
+ * device_find_child_by_of_offset() - Find a child device based on FDT offset
+ *
+ * Locates a child device by its device tree offset.
+ *
+ * @parent: Parent device
+ * @of_offset: Device tree offset to find
+ * @devp: Returns pointer to device if found, otherwise this is set to NULL
+ * @return 0 if OK, -ve on error
+ */
+int device_find_child_by_of_offset(struct udevice *parent, int of_offset,
+				   struct udevice **devp);
+
+/**
+ * device_get_child_by_of_offset() - Get a child device based on FDT offset
+ *
+ * Locates a child device by its device tree offset.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @parent: Parent device
+ * @of_offset: Device tree offset to find
+ * @devp: Returns pointer to device if found, otherwise this is set to NULL
+ * @return 0 if OK, -ve on error
+ */
+int device_get_child_by_of_offset(struct udevice *parent, int of_offset,
+				  struct udevice **devp);
+
+/**
+ * device_find_global_by_ofnode() - Get a device based on ofnode
+ *
+ * Locates a device by its device tree ofnode, searching globally throughout
+ * the all driver model devices.
+ *
+ * The device is NOT probed
+ *
+ * @node: Device tree ofnode to find
+ * @devp: Returns pointer to device if found, otherwise this is set to NULL
+ * @return 0 if OK, -ve on error
+ */
+
+int device_find_global_by_ofnode(ofnode node, struct udevice **devp);
+
+/**
+ * device_get_global_by_ofnode() - Get a device based on ofnode
+ *
+ * Locates a device by its device tree ofnode, searching globally throughout
+ * the all driver model devices.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @node: Device tree ofnode to find
+ * @devp: Returns pointer to device if found, otherwise this is set to NULL
+ * @return 0 if OK, -ve on error
+ */
+int device_get_global_by_ofnode(ofnode node, struct udevice **devp);
+
+/**
+ * device_find_first_child() - Find the first child of a device
+ *
+ * @parent: Parent device to search
+ * @devp: Returns first child device, or NULL if none
+ * @return 0
+ */
+int device_find_first_child(struct udevice *parent, struct udevice **devp);
+
+/**
+ * device_find_next_child() - Find the next child of a device
+ *
+ * @devp: Pointer to previous child device on entry. Returns pointer to next
+ *		child device, or NULL if none
+ * @return 0
+ */
+int device_find_next_child(struct udevice **devp);
+
+/**
+ * device_find_first_inactive_child() - Find the first inactive child
+ *
+ * This is used to locate an existing child of a device which is of a given
+ * uclass.
+ *
+ * The device is NOT probed
+ *
+ * @parent:	Parent device to search
+ * @uclass_id:	Uclass to look for
+ * @devp:	Returns device found, if any
+ * @return 0 if found, else -ENODEV
+ */
+int device_find_first_inactive_child(struct udevice *parent,
+				     enum uclass_id uclass_id,
+				     struct udevice **devp);
+
+/**
+ * device_find_first_child_by_uclass() - Find the first child of a device in uc
+ *
+ * @parent: Parent device to search
+ * @uclass_id:	Uclass to look for
+ * @devp: Returns first child device in that uclass, if any
+ * @return 0 if found, else -ENODEV
+ */
+int device_find_first_child_by_uclass(struct udevice *parent,
+				      enum uclass_id uclass_id,
+				      struct udevice **devp);
+
+/**
+ * device_find_child_by_name() - Find a child by device name
+ *
+ * @parent:	Parent device to search
+ * @name:	Name to look for
+ * @devp:	Returns device found, if any
+ * @return 0 if found, else -ENODEV
+ */
+int device_find_child_by_name(struct udevice *parent, const char *name,
+			      struct udevice **devp);
+
+/**
+ * device_has_children() - check if a device has any children
+ *
+ * @dev:	Device to check
+ * @return true if the device has one or more children
+ */
+bool device_has_children(const struct udevice *dev);
+
+/**
+ * device_has_active_children() - check if a device has any active children
+ *
+ * @dev:	Device to check
+ * @return true if the device has one or more children and at least one of
+ * them is active (probed).
+ */
+bool device_has_active_children(struct udevice *dev);
+
+/**
+ * device_is_last_sibling() - check if a device is the last sibling
+ *
+ * This function can be useful for display purposes, when special action needs
+ * to be taken when displaying the last sibling. This can happen when a tree
+ * view of devices is being displayed.
+ *
+ * @dev:	Device to check
+ * @return true if there are no more siblings after this one - i.e. is it
+ * last in the list.
+ */
+bool device_is_last_sibling(struct udevice *dev);
+
+/**
+ * device_set_name() - set the name of a device
+ *
+ * This must be called in the device's bind() method and no later. Normally
+ * this is unnecessary but for probed devices which don't get a useful name
+ * this function can be helpful.
+ *
+ * The name is allocated and will be freed automatically when the device is
+ * unbound.
+ *
+ * @dev:	Device to update
+ * @name:	New name (this string is allocated new memory and attached to
+ *		the device)
+ * @return 0 if OK, -ENOMEM if there is not enough memory to allocate the
+ * string
+ */
+int device_set_name(struct udevice *dev, const char *name);
+
+/**
+ * device_set_name_alloced() - note that a device name is allocated
+ *
+ * This sets the DM_FLAG_NAME_ALLOCED flag for the device, so that when it is
+ * unbound the name will be freed. This avoids memory leaks.
+ *
+ * @dev:	Device to update
+ */
+void device_set_name_alloced(struct udevice *dev);
+
+/**
+ * device_is_compatible() - check if the device is compatible with the compat
+ *
+ * This allows to check whether the device is comaptible with the compat.
+ *
+ * @dev:	udevice pointer for which compatible needs to be verified.
+ * @compat:	Compatible string which needs to verified in the given
+ *		device
+ * @return true if OK, false if the compatible is not found
+ */
+bool device_is_compatible(struct udevice *dev, const char *compat);
+
+/**
+ * of_machine_is_compatible() - check if the machine is compatible with
+ *				the compat
+ *
+ * This allows to check whether the machine is comaptible with the compat.
+ *
+ * @compat:	Compatible string which needs to verified
+ * @return true if OK, false if the compatible is not found
+ */
+bool of_machine_is_compatible(const char *compat);
+
+/**
+ * dev_disable_by_path() - Disable a device given its device tree path
+ *
+ * @path:	The device tree path identifying the device to be disabled
+ * @return 0 on success, -ve on error
+ */
+int dev_disable_by_path(const char *path);
+
+/**
+ * dev_enable_by_path() - Enable a device given its device tree path
+ *
+ * @path:	The device tree path identifying the device to be enabled
+ * @return 0 on success, -ve on error
+ */
+int dev_enable_by_path(const char *path);
+
+/**
+ * device_is_on_pci_bus - Test if a device is on a PCI bus
+ *
+ * @dev:	device to test
+ * @return:	true if it is on a PCI bus, false otherwise
+ */
+static inline bool device_is_on_pci_bus(struct udevice *dev)
+{
+	return device_get_uclass_id(dev->parent) == UCLASS_PCI;
+}
+
+/**
+ * device_foreach_child_safe() - iterate through child devices safely
+ *
+ * This allows the @pos child to be removed in the loop if required.
+ *
+ * @pos: struct udevice * for the current device
+ * @next: struct udevice * for the next device
+ * @parent: parent device to scan
+ */
+#define device_foreach_child_safe(pos, next, parent)	\
+	list_for_each_entry_safe(pos, next, &parent->child_head, sibling_node)
+
+/**
+ * device_foreach_child() - iterate through child devices
+ *
+ * @pos: struct udevice * for the current device
+ * @parent: parent device to scan
+ */
+#define device_foreach_child(pos, parent)	\
+	list_for_each_entry(pos, &parent->child_head, sibling_node)
+
+/**
+ * dm_scan_fdt_dev() - Bind child device in a the device tree
+ *
+ * This handles device which have sub-nodes in the device tree. It scans all
+ * sub-nodes and binds drivers for each node where a driver can be found.
+ *
+ * If this is called prior to relocation, only pre-relocation devices will be
+ * bound (those marked with u-boot,dm-pre-reloc in the device tree, or where
+ * the driver has the DM_FLAG_PRE_RELOC flag set). Otherwise, all devices will
+ * be bound.
+ *
+ * @dev:	Device to scan
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_fdt_dev(struct udevice *dev);
+
+/* device resource management */
+typedef void (*dr_release_t)(struct udevice *dev, void *res);
+typedef int (*dr_match_t)(struct udevice *dev, void *res, void *match_data);
+
+#ifdef CONFIG_DEVRES
+
+#ifdef CONFIG_DEBUG_DEVRES
+void *__devres_alloc(dr_release_t release, size_t size, gfp_t gfp,
+		     const char *name);
+#define _devres_alloc(release, size, gfp) \
+	__devres_alloc(release, size, gfp, #release)
+#else
+void *_devres_alloc(dr_release_t release, size_t size, gfp_t gfp);
+#endif
+
+/**
+ * devres_alloc() - Allocate device resource data
+ * @release: Release function devres will be associated with
+ * @size: Allocation size
+ * @gfp: Allocation flags
+ *
+ * Allocate devres of @size bytes.  The allocated area is associated
+ * with @release.  The returned pointer can be passed to
+ * other devres_*() functions.
+ *
+ * RETURNS:
+ * Pointer to allocated devres on success, NULL on failure.
+ */
+#define devres_alloc(release, size, gfp) \
+	_devres_alloc(release, size, gfp | __GFP_ZERO)
+
+/**
+ * devres_free() - Free device resource data
+ * @res: Pointer to devres data to free
+ *
+ * Free devres created with devres_alloc().
+ */
+void devres_free(void *res);
+
+/**
+ * devres_add() - Register device resource
+ * @dev: Device to add resource to
+ * @res: Resource to register
+ *
+ * Register devres @res to @dev.  @res should have been allocated
+ * using devres_alloc().  On driver detach, the associated release
+ * function will be invoked and devres will be freed automatically.
+ */
+void devres_add(struct udevice *dev, void *res);
+
+/**
+ * devres_find() - Find device resource
+ * @dev: Device to lookup resource from
+ * @release: Look for resources associated with this release function
+ * @match: Match function (optional)
+ * @match_data: Data for the match function
+ *
+ * Find the latest devres of @dev which is associated with @release
+ * and for which @match returns 1.  If @match is NULL, it's considered
+ * to match all.
+ *
+ * @return pointer to found devres, NULL if not found.
+ */
+void *devres_find(struct udevice *dev, dr_release_t release,
+		  dr_match_t match, void *match_data);
+
+/**
+ * devres_get() - Find devres, if non-existent, add one atomically
+ * @dev: Device to lookup or add devres for
+ * @new_res: Pointer to new initialized devres to add if not found
+ * @match: Match function (optional)
+ * @match_data: Data for the match function
+ *
+ * Find the latest devres of @dev which has the same release function
+ * as @new_res and for which @match return 1.  If found, @new_res is
+ * freed; otherwise, @new_res is added atomically.
+ *
+ * @return ointer to found or added devres.
+ */
+void *devres_get(struct udevice *dev, void *new_res,
+		 dr_match_t match, void *match_data);
+
+/**
+ * devres_remove() - Find a device resource and remove it
+ * @dev: Device to find resource from
+ * @release: Look for resources associated with this release function
+ * @match: Match function (optional)
+ * @match_data: Data for the match function
+ *
+ * Find the latest devres of @dev associated with @release and for
+ * which @match returns 1.  If @match is NULL, it's considered to
+ * match all.  If found, the resource is removed atomically and
+ * returned.
+ *
+ * @return ointer to removed devres on success, NULL if not found.
+ */
+void *devres_remove(struct udevice *dev, dr_release_t release,
+		    dr_match_t match, void *match_data);
+
+/**
+ * devres_destroy() - Find a device resource and destroy it
+ * @dev: Device to find resource from
+ * @release: Look for resources associated with this release function
+ * @match: Match function (optional)
+ * @match_data: Data for the match function
+ *
+ * Find the latest devres of @dev associated with @release and for
+ * which @match returns 1.  If @match is NULL, it's considered to
+ * match all.  If found, the resource is removed atomically and freed.
+ *
+ * Note that the release function for the resource will not be called,
+ * only the devres-allocated data will be freed.  The caller becomes
+ * responsible for freeing any other data.
+ *
+ * @return 0 if devres is found and freed, -ENOENT if not found.
+ */
+int devres_destroy(struct udevice *dev, dr_release_t release,
+		   dr_match_t match, void *match_data);
+
+/**
+ * devres_release() - Find a device resource and destroy it, calling release
+ * @dev: Device to find resource from
+ * @release: Look for resources associated with this release function
+ * @match: Match function (optional)
+ * @match_data: Data for the match function
+ *
+ * Find the latest devres of @dev associated with @release and for
+ * which @match returns 1.  If @match is NULL, it's considered to
+ * match all.  If found, the resource is removed atomically, the
+ * release function called and the resource freed.
+ *
+ * @return 0 if devres is found and freed, -ENOENT if not found.
+ */
+int devres_release(struct udevice *dev, dr_release_t release,
+		   dr_match_t match, void *match_data);
+
+/* managed devm_k.alloc/kfree for device drivers */
+/**
+ * devm_kmalloc() - Resource-managed kmalloc
+ * @dev: Device to allocate memory for
+ * @size: Allocation size
+ * @gfp: Allocation gfp flags
+ *
+ * Managed kmalloc.  Memory allocated with this function is
+ * automatically freed on driver detach.  Like all other devres
+ * resources, guaranteed alignment is unsigned long long.
+ *
+ * @return pointer to allocated memory on success, NULL on failure.
+ */
+void *devm_kmalloc(struct udevice *dev, size_t size, gfp_t gfp);
+static inline void *devm_kzalloc(struct udevice *dev, size_t size, gfp_t gfp)
+{
+	return devm_kmalloc(dev, size, gfp | __GFP_ZERO);
+}
+static inline void *devm_kmalloc_array(struct udevice *dev,
+				       size_t n, size_t size, gfp_t flags)
+{
+	if (size != 0 && n > SIZE_MAX / size)
+		return NULL;
+	return devm_kmalloc(dev, n * size, flags);
+}
+static inline void *devm_kcalloc(struct udevice *dev,
+				 size_t n, size_t size, gfp_t flags)
+{
+	return devm_kmalloc_array(dev, n, size, flags | __GFP_ZERO);
+}
+
+/**
+ * devm_kfree() - Resource-managed kfree
+ * @dev: Device this memory belongs to
+ * @ptr: Memory to free
+ *
+ * Free memory allocated with devm_kmalloc().
+ */
+void devm_kfree(struct udevice *dev, void *ptr);
+
+#else /* ! CONFIG_DEVRES */
+
+static inline void *devres_alloc(dr_release_t release, size_t size, gfp_t gfp)
+{
+	return kzalloc(size, gfp);
+}
+
+static inline void devres_free(void *res)
+{
+	kfree(res);
+}
+
+static inline void devres_add(struct udevice *dev, void *res)
+{
+}
+
+static inline void *devres_find(struct udevice *dev, dr_release_t release,
+				dr_match_t match, void *match_data)
+{
+	return NULL;
+}
+
+static inline void *devres_get(struct udevice *dev, void *new_res,
+			       dr_match_t match, void *match_data)
+{
+	return NULL;
+}
+
+static inline void *devres_remove(struct udevice *dev, dr_release_t release,
+				  dr_match_t match, void *match_data)
+{
+	return NULL;
+}
+
+static inline int devres_destroy(struct udevice *dev, dr_release_t release,
+				 dr_match_t match, void *match_data)
+{
+	return 0;
+}
+
+static inline int devres_release(struct udevice *dev, dr_release_t release,
+				 dr_match_t match, void *match_data)
+{
+	return 0;
+}
+
+static inline void *devm_kmalloc(struct udevice *dev, size_t size, gfp_t gfp)
+{
+	return kmalloc(size, gfp);
+}
+
+static inline void *devm_kzalloc(struct udevice *dev, size_t size, gfp_t gfp)
+{
+	return kzalloc(size, gfp);
+}
+
+static inline void *devm_kmalloc_array(struct udevice *dev,
+				       size_t n, size_t size, gfp_t flags)
+{
+	/* TODO: add kmalloc_array() to linux/compat.h */
+	if (size != 0 && n > SIZE_MAX / size)
+		return NULL;
+	return kmalloc(n * size, flags);
+}
+
+static inline void *devm_kcalloc(struct udevice *dev,
+				 size_t n, size_t size, gfp_t flags)
+{
+	/* TODO: add kcalloc() to linux/compat.h */
+	return kmalloc(n * size, flags | __GFP_ZERO);
+}
+
+static inline void devm_kfree(struct udevice *dev, void *ptr)
+{
+	kfree(ptr);
+}
+
+#endif /* ! CONFIG_DEVRES */
+
+/*
+ * REVISIT:
+ * remove the following after resolving conflicts with <linux/compat.h>
+ */
+#ifdef dev_dbg
+#undef dev_dbg
+#endif
+#ifdef dev_vdbg
+#undef dev_vdbg
+#endif
+#ifdef dev_info
+#undef dev_info
+#endif
+#ifdef dev_err
+#undef dev_err
+#endif
+#ifdef dev_warn
+#undef dev_warn
+#endif
+
+/*
+ * REVISIT:
+ * print device name like Linux
+ */
+#define dev_printk(dev, fmt, ...)				\
+({								\
+	printk(fmt, ##__VA_ARGS__);				\
+})
+
+#define __dev_printk(level, dev, fmt, ...)			\
+({								\
+	if (level < CONFIG_VAL(LOGLEVEL))			\
+		dev_printk(dev, fmt, ##__VA_ARGS__);		\
+})
+
+#define dev_emerg(dev, fmt, ...) \
+	__dev_printk(0, dev, fmt, ##__VA_ARGS__)
+#define dev_alert(dev, fmt, ...) \
+	__dev_printk(1, dev, fmt, ##__VA_ARGS__)
+#define dev_crit(dev, fmt, ...) \
+	__dev_printk(2, dev, fmt, ##__VA_ARGS__)
+#define dev_err(dev, fmt, ...) \
+	__dev_printk(3, dev, fmt, ##__VA_ARGS__)
+#define dev_warn(dev, fmt, ...) \
+	__dev_printk(4, dev, fmt, ##__VA_ARGS__)
+#define dev_notice(dev, fmt, ...) \
+	__dev_printk(5, dev, fmt, ##__VA_ARGS__)
+#define dev_info(dev, fmt, ...) \
+	__dev_printk(6, dev, fmt, ##__VA_ARGS__)
+
+#ifdef DEBUG
+#define dev_dbg(dev, fmt, ...) \
+	__dev_printk(7, dev, fmt, ##__VA_ARGS__)
+#else
+#define dev_dbg(dev, fmt, ...)					\
+({								\
+	if (0)							\
+		__dev_printk(7, dev, fmt, ##__VA_ARGS__);	\
+})
+#endif
+
+#ifdef VERBOSE_DEBUG
+#define dev_vdbg	dev_dbg
+#else
+#define dev_vdbg(dev, fmt, ...)					\
+({								\
+	if (0)							\
+		__dev_printk(7, dev, fmt, ##__VA_ARGS__);	\
+})
+#endif
+
+#endif
diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h
new file mode 100644
index 0000000..959d3bc
--- /dev/null
+++ b/include/dm/fdtaddr.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ */
+
+#ifndef _DM_FDTADDR_H
+#define _DM_FDTADDR_H
+
+#include <fdtdec.h>
+
+struct udevice;
+
+/**
+ * devfdt_get_addr() - Get the reg property of a device
+ *
+ * @dev: Pointer to a device
+ *
+ * @return addr
+ */
+fdt_addr_t devfdt_get_addr(struct udevice *dev);
+
+/**
+ * devfdt_get_addr_ptr() - Return pointer to the address of the reg property
+ *                      of a device
+ *
+ * @dev: Pointer to a device
+ *
+ * @return Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_get_addr_ptr(struct udevice *dev);
+
+/**
+ * devfdt_remap_addr() - Return pointer to the memory-mapped I/O address
+ *                           of the reg property of a device
+ *
+ * @dev: Pointer to a device
+ *
+ * @return Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_remap_addr(struct udevice *dev);
+
+/**
+ * devfdt_remap_addr_index() - Return indexed pointer to the memory-mapped
+ *                                 I/O address of the reg property of a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ *	   and @index is used to select which one is required
+ *
+ * @dev: Pointer to a device
+ *
+ * @return Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_remap_addr_index(struct udevice *dev, int index);
+
+/**
+ * devfdt_remap_addr_name() - Get the reg property of a device, indexed by
+ *                            name, as a memory-mapped I/O pointer
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ *	  'reg-names' property providing named-based identification. @index
+ *	  indicates the value to search for in 'reg-names'.
+ *
+ * @dev: Pointer to a device
+ *
+ * @return Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_remap_addr_name(struct udevice *dev, const char *name);
+
+/**
+ * devfdt_map_physmem() - Read device address from reg property of the
+ *                     device node and map the address into CPU address
+ *                     space.
+ *
+ * @dev: Pointer to device
+ * @size: size of the memory to map
+ *
+ * @return  mapped address, or NULL if the device does not have reg
+ *          property.
+ */
+void *devfdt_map_physmem(struct udevice *dev, unsigned long size);
+
+/**
+ * devfdt_get_addr_index() - Get the indexed reg property of a device
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ *	   and @index is used to select which one is required
+ *
+ * @return addr
+ */
+fdt_addr_t devfdt_get_addr_index(struct udevice *dev, int index);
+
+/**
+ * devfdt_get_addr_size_index() - Get the indexed reg property of a device
+ *
+ * Returns the address and size specified in the 'reg' property of a device.
+ *
+ * @dev: Pointer to a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ *	   and @index is used to select which one is required
+ * @size: Pointer to size varible - this function returns the size
+ *        specified in the 'reg' property here
+ *
+ * @return addr
+ */
+fdt_addr_t devfdt_get_addr_size_index(struct udevice *dev, int index,
+				   fdt_size_t *size);
+
+/**
+ * devfdt_get_addr_name() - Get the reg property of a device, indexed by name
+ *
+ * @dev: Pointer to a device
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ *	  'reg-names' property providing named-based identification. @index
+ *	  indicates the value to search for in 'reg-names'.
+ *
+ * @return addr
+ */
+fdt_addr_t devfdt_get_addr_name(struct udevice *dev, const char *name);
+
+/**
+ * devfdt_get_addr_size_name() - Get the reg property and its size for a device,
+ *				 indexed by name
+ *
+ * Returns the address and size specified in the 'reg' property of a device.
+ *
+ * @dev: Pointer to a device
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ *	  'reg-names' property providing named-based identification. @index
+ *	  indicates the value to search for in 'reg-names'.
+ * @size: Pointer to size variable - this function returns the size
+ *        specified in the 'reg' property here
+ *
+ * @return addr
+ */
+fdt_addr_t devfdt_get_addr_size_name(struct udevice *dev, const char *name,
+				     fdt_size_t *size);
+
+/**
+ * devfdt_get_addr_pci() - Read an address and handle PCI address translation
+ *
+ * @dev: Device to read from
+ * @return address or FDT_ADDR_T_NONE if not found
+ */
+fdt_addr_t devfdt_get_addr_pci(struct udevice *dev);
+
+#endif
diff --git a/include/dm/lists.h b/include/dm/lists.h
new file mode 100644
index 0000000..810e244
--- /dev/null
+++ b/include/dm/lists.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ */
+
+#ifndef _DM_LISTS_H_
+#define _DM_LISTS_H_
+
+#include <dm/ofnode.h>
+#include <dm/uclass-id.h>
+
+/**
+ * lists_driver_lookup_name() - Return u_boot_driver corresponding to name
+ *
+ * This function returns a pointer to a driver given its name. This is used
+ * for binding a driver given its name and platdata.
+ *
+ * @name: Name of driver to look up
+ * @return pointer to driver, or NULL if not found
+ */
+struct driver *lists_driver_lookup_name(const char *name);
+
+/**
+ * lists_uclass_lookup() - Return uclass_driver based on ID of the class
+ * id:		ID of the class
+ *
+ * This function returns the pointer to uclass_driver, which is the class's
+ * base structure based on the ID of the class. Returns NULL on error.
+ */
+struct uclass_driver *lists_uclass_lookup(enum uclass_id id);
+
+/**
+ * lists_bind_drivers() - search for and bind all drivers to parent
+ *
+ * This searches the U_BOOT_DEVICE() structures and creates new devices for
+ * each one. The devices will have @parent as their parent.
+ *
+ * @parent: parent device (root)
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC flag.
+ * If false bind all drivers.
+ */
+int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only);
+
+/**
+ * lists_bind_fdt() - bind a device tree node
+ *
+ * This creates a new device bound to the given device tree node, with
+ * @parent as its parent.
+ *
+ * @parent: parent device (root)
+ * @node: device tree node to bind
+ * @devp: if non-NULL, returns a pointer to the bound device
+ * @pre_reloc_only: If true, bind only nodes with special devicetree properties,
+ * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers.
+ * @return 0 if device was bound, -EINVAL if the device tree is invalid,
+ * other -ve value on error
+ */
+int lists_bind_fdt(struct udevice *parent, ofnode node, struct udevice **devp,
+		   bool pre_reloc_only);
+
+/**
+ * device_bind_driver() - bind a device to a driver
+ *
+ * This binds a new device to a driver.
+ *
+ * @parent:	Parent device
+ * @drv_name:	Name of driver to attach to this parent
+ * @dev_name:	Name of the new device thus created
+ * @devp:	If non-NULL, returns the newly bound device
+ */
+int device_bind_driver(struct udevice *parent, const char *drv_name,
+		       const char *dev_name, struct udevice **devp);
+
+/**
+ * device_bind_driver_to_node() - bind a device to a driver for a node
+ *
+ * This binds a new device to a driver for a given device tree node. This
+ * should only be needed if the node lacks a compatible strings.
+ *
+ * @parent:	Parent device
+ * @drv_name:	Name of driver to attach to this parent
+ * @dev_name:	Name of the new device thus created
+ * @node:	Device tree node
+ * @devp:	If non-NULL, returns the newly bound device
+ */
+int device_bind_driver_to_node(struct udevice *parent, const char *drv_name,
+			       const char *dev_name, ofnode node,
+			       struct udevice **devp);
+
+#endif
diff --git a/include/dm/of.h b/include/dm/of.h
new file mode 100644
index 0000000..6bef73b
--- /dev/null
+++ b/include/dm/of.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _DM_OF_H
+#define _DM_OF_H
+
+#include <asm/u-boot.h>
+#include <asm/global_data.h>
+
+/* integer value within a device tree property which references another node */
+typedef u32 phandle;
+
+/**
+ * struct property: Device tree property
+ *
+ * @name: Property name
+ * @length: Length of property in bytes
+ * @value: Pointer to property value
+ * @next: Pointer to next property, or NULL if none
+ */
+struct property {
+	char *name;
+	int length;
+	void *value;
+	struct property *next;
+};
+
+/**
+ * struct device_node: Device tree node
+ *
+ * @name: Node name
+ * @type: Node type (value of device_type property) or "<NULL>" if none
+ * @phandle: Phandle value of this none, or 0 if none
+ * @full_name: Full path to node, e.g. "/bus@1/spi@1100"
+ * @properties: Pointer to head of list of properties, or NULL if none
+ * @parent: Pointer to parent node, or NULL if this is the root node
+ * @child: Pointer to head of child node list, or NULL if no children
+ * @sibling: Pointer to the next sibling node, or NULL if this is the last
+ */
+struct device_node {
+	const char *name;
+	const char *type;
+	phandle phandle;
+	const char *full_name;
+
+	struct property *properties;
+	struct device_node *parent;
+	struct device_node *child;
+	struct device_node *sibling;
+};
+
+#define OF_MAX_PHANDLE_ARGS 16
+
+/**
+ * struct of_phandle_args - structure to hold phandle and arguments
+ *
+ * This is used when decoding a phandle in a device tree property. Typically
+ * these look like this:
+ *
+ * wibble {
+ *    phandle = <5>;
+ * };
+ *
+ * ...
+ * some-prop = <&wibble 1 2 3>
+ *
+ * Here &node is the phandle of the node 'wibble', i.e. 5. There are three
+ * arguments: 1, 2, 3.
+ *
+ * So when decoding the phandle in some-prop, np will point to wibble,
+ * args_count will be 3 and the three arguments will be in args.
+ *
+ * @np: Node that the phandle refers to
+ * @args_count: Number of arguments
+ * @args: Argument values
+ */
+struct of_phandle_args {
+	struct device_node *np;
+	int args_count;
+	uint32_t args[OF_MAX_PHANDLE_ARGS];
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * of_live_active() - check if livetree is active
+ *
+ * @returns true if livetree is active, false it not
+ */
+#ifdef CONFIG_OF_LIVE
+static inline bool of_live_active(void)
+{
+	return gd->of_root != NULL;
+}
+#else
+static inline bool of_live_active(void)
+{
+	return false;
+}
+#endif
+
+#define OF_BAD_ADDR	((u64)-1)
+
+static inline const char *of_node_full_name(const struct device_node *np)
+{
+	return np ? np->full_name : "<no-node>";
+}
+
+/* Default #address and #size cells */
+#if !defined(OF_ROOT_NODE_ADDR_CELLS_DEFAULT)
+#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 2
+#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
+#endif
+
+/* Default string compare functions */
+#if !defined(of_compat_cmp)
+#define of_compat_cmp(s1, s2, l)	strcasecmp((s1), (s2))
+#define of_prop_cmp(s1, s2)		strcmp((s1), (s2))
+#define of_node_cmp(s1, s2)		strcasecmp((s1), (s2))
+#endif
+
+/* Helper to read a big number; size is in cells (not bytes) */
+static inline u64 of_read_number(const __be32 *cell, int size)
+{
+	u64 r = 0;
+	while (size--)
+		r = (r << 32) | be32_to_cpu(*(cell++));
+	return r;
+}
+
+/* Like of_read_number, but we want an unsigned long result */
+static inline unsigned long of_read_ulong(const __be32 *cell, int size)
+{
+	/* toss away upper bits if unsigned long is smaller than u64 */
+	return of_read_number(cell, size);
+}
+
+#endif
diff --git a/include/dm/of_access.h b/include/dm/of_access.h
new file mode 100644
index 0000000..13fedb7
--- /dev/null
+++ b/include/dm/of_access.h
@@ -0,0 +1,444 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Originally from Linux v4.9
+ * Copyright (C) 1996-2005 Paul Mackerras.
+ *
+ * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
+ * Updates for SPARC64 by David S. Miller
+ * Derived from PowerPC and Sparc prom.h files by Stephen Rothwell, IBM Corp.
+ *
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * Modified for U-Boot
+ * Copyright (c) 2017 Google, Inc
+ */
+
+#ifndef _DM_OF_ACCESS_H
+#define _DM_OF_ACCESS_H
+
+#include <dm/of.h>
+
+/**
+ * of_find_all_nodes - Get next node in global list
+ * @prev:	Previous node or NULL to start iteration
+ *		of_node_put() will be called on it
+ *
+ * Returns a node pointer with refcount incremented, use
+ * of_node_put() on it when done.
+ */
+struct device_node *of_find_all_nodes(struct device_node *prev);
+
+#define for_each_of_allnodes_from(from, dn) \
+	for (dn = of_find_all_nodes(from); dn; dn = of_find_all_nodes(dn))
+#define for_each_of_allnodes(dn) for_each_of_allnodes_from(NULL, dn)
+
+/* Dummy functions to mirror Linux. These are not used in U-Boot */
+#define of_node_get(x) (x)
+static inline void of_node_put(const struct device_node *np) { }
+
+/**
+ * of_n_addr_cells() - Get the number of address cells for a node
+ *
+ * This walks back up the tree to find the closest #address-cells property
+ * which controls the given node.
+ *
+ * @np: Node pointer to check
+ * @return number of address cells this node uses
+ */
+int of_n_addr_cells(const struct device_node *np);
+
+/**
+ * of_n_size_cells() - Get the number of size cells for a node
+ *
+ * This walks back up the tree to find the closest #size-cells property
+ * which controls the given node.
+ *
+ * @np: Node pointer to check
+ * @return number of size cells this node uses
+ */
+int of_n_size_cells(const struct device_node *np);
+
+/**
+ * of_simple_addr_cells() - Get the address cells property in a node
+ *
+ * This function matches fdt_address_cells().
+ *
+ * @np: Node pointer to check
+ * @return value of #address-cells property in this node, or 2 if none
+ */
+int of_simple_addr_cells(const struct device_node *np);
+
+/**
+ * of_simple_size_cells() - Get the size cells property in a node
+ *
+ * This function matches fdt_size_cells().
+ *
+ * @np: Node pointer to check
+ * @return value of #size-cells property in this node, or 2 if none
+ */
+int of_simple_size_cells(const struct device_node *np);
+
+/**
+ * of_find_property() - find a property in a node
+ *
+ * @np: Pointer to device node holding property
+ * @name: Name of property
+ * @lenp: If non-NULL, returns length of property
+ * @return pointer to property, or NULL if not found
+ */
+struct property *of_find_property(const struct device_node *np,
+				  const char *name, int *lenp);
+
+/**
+ * of_get_property() - get a property value
+ *
+ * Find a property with a given name for a given node and return the value.
+ *
+ * @np: Pointer to device node holding property
+ * @name: Name of property
+ * @lenp: If non-NULL, returns length of property
+ * @return pointer to property value, or NULL if not found
+ */
+const void *of_get_property(const struct device_node *np, const char *name,
+			    int *lenp);
+
+/**
+ * of_device_is_compatible() - Check if the node matches given constraints
+ * @device: pointer to node
+ * @compat: required compatible string, NULL or "" for any match
+ * @type: required device_type value, NULL or "" for any match
+ * @name: required node name, NULL or "" for any match
+ *
+ * Checks if the given @compat, @type and @name strings match the
+ * properties of the given @device. A constraints can be skipped by
+ * passing NULL or an empty string as the constraint.
+ *
+ * @return 0 for no match, and a positive integer on match. The return
+ * value is a relative score with larger values indicating better
+ * matches. The score is weighted for the most specific compatible value
+ * to get the highest score. Matching type is next, followed by matching
+ * name. Practically speaking, this results in the following priority
+ * order for matches:
+ *
+ * 1. specific compatible && type && name
+ * 2. specific compatible && type
+ * 3. specific compatible && name
+ * 4. specific compatible
+ * 5. general compatible && type && name
+ * 6. general compatible && type
+ * 7. general compatible && name
+ * 8. general compatible
+ * 9. type && name
+ * 10. type
+ * 11. name
+ */
+int of_device_is_compatible(const struct device_node *np, const char *compat,
+			    const char *type, const char *name);
+
+/**
+ * of_device_is_available() - check if a device is available for use
+ *
+ * @device: Node to check for availability
+ *
+ * @return true if the status property is absent or set to "okay", false
+ * otherwise
+ */
+bool of_device_is_available(const struct device_node *np);
+
+/**
+ * of_get_parent() - Get a node's parent, if any
+ *
+ * @node: Node to check
+ * @eturns a node pointer, or NULL if none
+ */
+struct device_node *of_get_parent(const struct device_node *np);
+
+/**
+ * of_find_node_opts_by_path() - Find a node matching a full OF path
+ *
+ * @path: Either the full path to match, or if the path does not start with
+ *	'/', the name of a property of the /aliases node (an alias). In the
+ *	case of an alias, the node matching the alias' value will be returned.
+ * @opts: Address of a pointer into which to store the start of an options
+ *	string appended to the end of the path with a ':' separator. Can be NULL
+ *
+ * Valid paths:
+ *	/foo/bar	Full path
+ *	foo		Valid alias
+ *	foo/bar		Valid alias + relative path
+ *
+ * @return a node pointer or NULL if not found
+ */
+struct device_node *of_find_node_opts_by_path(const char *path,
+					      const char **opts);
+
+static inline struct device_node *of_find_node_by_path(const char *path)
+{
+	return of_find_node_opts_by_path(path, NULL);
+}
+
+/**
+ * of_find_compatible_node() - find a node based on its compatible string
+ *
+ * Find a node based on type and one of the tokens in its "compatible" property
+ * @from: Node to start searching from or NULL. the node you pass will not be
+ *	searched, only the next one will; typically, you pass what the previous
+ *	call returned.
+ * @type: The type string to match "device_type" or NULL to ignore
+ * @compatible:	The string to match to one of the tokens in the device
+ *	"compatible" list.
+ * @return node pointer or NULL if not found
+ */
+struct device_node *of_find_compatible_node(struct device_node *from,
+				const char *type, const char *compatible);
+
+/**
+ * of_find_node_by_prop_value() - find a node with a given property value
+ *
+ * Find a node based on a property value.
+ * @from: Node to start searching from or NULL. the node you pass will not be
+ *	searched, only the next one will; typically, you pass what the previous
+ *	call returned.
+ * @propname: property name to check
+ * @propval: property value to search for
+ * @proplen: length of the value in propval
+ * @return node pointer or NULL if not found
+ */
+struct device_node *of_find_node_by_prop_value(struct device_node *from,
+					       const char *propname,
+					       const void *propval,
+					       int proplen);
+/**
+ * of_find_node_by_phandle() - Find a node given a phandle
+ *
+ * @handle:	phandle of the node to find
+ *
+ * @return node pointer, or NULL if not found
+ */
+struct device_node *of_find_node_by_phandle(phandle handle);
+
+/**
+ * of_read_u32() - Find and read a 32-bit integer from a property
+ *
+ * Search for a property in a device node and read a 32-bit value from
+ * it.
+ *
+ * @np:		device node from which the property value is to be read.
+ * @propname:	name of the property to be searched.
+ * @outp:	pointer to return value, modified only if return value is 0.
+ *
+ * @return 0 on success, -EINVAL if the property does not exist,
+ * -ENODATA if property does not have a value, and -EOVERFLOW if the
+ * property data isn't large enough.
+ */
+int of_read_u32(const struct device_node *np, const char *propname, u32 *outp);
+
+/**
+ * of_read_u64() - Find and read a 64-bit integer from a property
+ *
+ * Search for a property in a device node and read a 64-bit value from
+ * it.
+ *
+ * @np:		device node from which the property value is to be read.
+ * @propname:	name of the property to be searched.
+ * @outp:	pointer to return value, modified only if return value is 0.
+ *
+ * @return 0 on success, -EINVAL if the property does not exist,
+ * -ENODATA if property does not have a value, and -EOVERFLOW if the
+ * property data isn't large enough.
+ */
+int of_read_u64(const struct device_node *np, const char *propname, u64 *outp);
+
+/**
+ * of_read_u32_array() - Find and read an array of 32 bit integers
+ *
+ * Search for a property in a device node and read 32-bit value(s) from
+ * it.
+ *
+ * @np:		device node from which the property value is to be read.
+ * @propname:	name of the property to be searched.
+ * @out_values:	pointer to return value, modified only if return value is 0.
+ * @sz:		number of array elements to read
+ * @return 0 on success, -EINVAL if the property does not exist, -ENODATA
+ * if property does not have a value, and -EOVERFLOW is longer than sz.
+ */
+int of_read_u32_array(const struct device_node *np, const char *propname,
+		      u32 *out_values, size_t sz);
+
+/**
+ * of_property_match_string() - Find string in a list and return index
+ *
+ * This function searches a string list property and returns the index
+ * of a specific string value.
+ *
+ * @np: pointer to node containing string list property
+ * @propname: string list property name
+ * @string: pointer to string to search for in string list
+ * @return 0 on success, -EINVAL if the property does not exist, -ENODATA
+ * if property does not have a value, and -EOVERFLOW is longer than sz.
+ */
+int of_property_match_string(const struct device_node *np, const char *propname,
+			     const char *string);
+
+int of_property_read_string_helper(const struct device_node *np,
+				   const char *propname, const char **out_strs,
+				   size_t sz, int index);
+
+/**
+ * of_property_read_string_index() - Find and read a string from a multiple
+ * strings property.
+ * @np:		device node from which the property value is to be read.
+ * @propname:	name of the property to be searched.
+ * @index:	index of the string in the list of strings
+ * @out_string:	pointer to null terminated return string, modified only if
+ *		return value is 0.
+ *
+ * Search for a property in a device tree node and retrieve a null
+ * terminated string value (pointer to data, not a copy) in the list of strings
+ * contained in that property.
+ * Returns 0 on success, -EINVAL if the property does not exist, -ENODATA if
+ * property does not have a value, and -EILSEQ if the string is not
+ * null-terminated within the length of the property data.
+ *
+ * The out_string pointer is modified only if a valid string can be decoded.
+ */
+static inline int of_property_read_string_index(const struct device_node *np,
+						const char *propname,
+						int index, const char **output)
+{
+	int rc = of_property_read_string_helper(np, propname, output, 1, index);
+	return rc < 0 ? rc : 0;
+}
+
+/**
+ * of_property_count_strings() - Find and return the number of strings from a
+ * multiple strings property.
+ * @np:		device node from which the property value is to be read.
+ * @propname:	name of the property to be searched.
+ *
+ * Search for a property in a device tree node and retrieve the number of null
+ * terminated string contain in it. Returns the number of strings on
+ * success, -EINVAL if the property does not exist, -ENODATA if property
+ * does not have a value, and -EILSEQ if the string is not null-terminated
+ * within the length of the property data.
+ */
+static inline int of_property_count_strings(const struct device_node *np,
+					    const char *propname)
+{
+	return of_property_read_string_helper(np, propname, NULL, 0, 0);
+}
+
+/**
+ * of_parse_phandle - Resolve a phandle property to a device_node pointer
+ * @np: Pointer to device node holding phandle property
+ * @phandle_name: Name of property holding a phandle value
+ * @index: For properties holding a table of phandles, this is the index into
+ *         the table
+ *
+ * Returns the device_node pointer with refcount incremented.  Use
+ * of_node_put() on it when done.
+ */
+struct device_node *of_parse_phandle(const struct device_node *np,
+				     const char *phandle_name, int index);
+
+/**
+ * of_parse_phandle_with_args() - Find a node pointed by phandle in a list
+ *
+ * @np:		pointer to a device tree node containing a list
+ * @list_name:	property name that contains a list
+ * @cells_name:	property name that specifies phandles' arguments count
+ * @index:	index of a phandle to parse out
+ * @out_args:	optional pointer to output arguments structure (will be filled)
+ * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if
+ *	@list_name does not exist, -EINVAL if a phandle was not found,
+ *	@cells_name could not be found, the arguments were truncated or there
+ *	were too many arguments.
+ *
+ * This function is useful to parse lists of phandles and their arguments.
+ * Returns 0 on success and fills out_args, on error returns appropriate
+ * errno value.
+ *
+ * Caller is responsible to call of_node_put() on the returned out_args->np
+ * pointer.
+ *
+ * Example:
+ *
+ * phandle1: node1 {
+ *	#list-cells = <2>;
+ * }
+ *
+ * phandle2: node2 {
+ *	#list-cells = <1>;
+ * }
+ *
+ * node3 {
+ *	list = <&phandle1 1 2 &phandle2 3>;
+ * }
+ *
+ * To get a device_node of the `node2' node you may call this:
+ * of_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args);
+ */
+int of_parse_phandle_with_args(const struct device_node *np,
+			       const char *list_name, const char *cells_name,
+			       int index, struct of_phandle_args *out_args);
+
+/**
+ * of_count_phandle_with_args() - Count the number of phandle in a list
+ *
+ * @np:		pointer to a device tree node containing a list
+ * @list_name:	property name that contains a list
+ * @cells_name:	property name that specifies phandles' arguments count
+ * @return number of phandle found, -ENOENT if
+ *	@list_name does not exist, -EINVAL if a phandle was not found,
+ *	@cells_name could not be found, the arguments were truncated or there
+ *	were too many arguments.
+ *
+ * Returns number of phandle found on success, on error returns appropriate
+ * errno value.
+ *
+ */
+int of_count_phandle_with_args(const struct device_node *np,
+			       const char *list_name, const char *cells_name);
+
+/**
+ * of_alias_scan() - Scan all properties of the 'aliases' node
+ *
+ * The function scans all the properties of the 'aliases' node and populates
+ * the lookup table with the properties.  It returns the number of alias
+ * properties found, or an error code in case of failure.
+ *
+ * @return 9 if OK, -ENOMEM if not enough memory
+ */
+int of_alias_scan(void);
+
+/**
+ * of_alias_get_id - Get alias id for the given device_node
+ *
+ * Travels the lookup table to get the alias id for the given device_node and
+ * alias stem.
+ *
+ * @np:		Pointer to the given device_node
+ * @stem:	Alias stem of the given device_node
+ * @return alias ID, if found, else -ENODEV
+ */
+int of_alias_get_id(const struct device_node *np, const char *stem);
+
+/**
+ * of_alias_get_highest_id - Get highest alias id for the given stem
+ * @stem:	Alias stem to be examined
+ *
+ * The function travels the lookup table to get the highest alias id for the
+ * given alias stem.
+ * @return alias ID, if found, else -1
+ */
+int of_alias_get_highest_id(const char *stem);
+
+/**
+ * of_get_stdout() - Get node to use for stdout
+ *
+ * @return node referred to by stdout-path alias, or NULL if none
+ */
+struct device_node *of_get_stdout(void);
+
+#endif
diff --git a/include/dm/of_addr.h b/include/dm/of_addr.h
new file mode 100644
index 0000000..3fa1ffc
--- /dev/null
+++ b/include/dm/of_addr.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Taken from Linux v4.9 drivers/of/address.c
+ *
+ * Modified for U-Boot
+ * Copyright (c) 2017 Google, Inc
+ */
+
+#ifndef _DM_OF_ADDR_H
+#define _DM_OF_ADDR_H
+
+/**
+ * of_translate_address() - translate a device-tree address to a CPU address
+ *
+ * Translate an address from the device-tree into a CPU physical address,
+ * this walks up the tree and applies the various bus mappings on the  way.
+ *
+ * Note: We consider that crossing any level with #size-cells == 0 to mean
+ * that translation is impossible (that is we are not dealing with a value
+ * that can be mapped to a cpu physical address). This is not really specified
+ * that way, but this is traditionally the way IBM at least do things
+ *
+ * @np: node to check
+ * @in_addr: pointer to input address
+ * @return translated address or OF_BAD_ADDR on error
+ */
+u64 of_translate_address(const struct device_node *no, const __be32 *in_addr);
+
+/**
+ * of_translate_dma_address() - translate a device-tree DMA address to a CPU
+ *				address
+ *
+ * Translate a DMA address from the device-tree into a CPU physical address,
+ * this walks up the tree and applies the various bus mappings on the way.
+ *
+ * Note: We consider that crossing any level with #size-cells == 0 to mean
+ * that translation is impossible (that is we are not dealing with a value
+ * that can be mapped to a cpu physical address). This is not really specified
+ * that way, but this is traditionally the way IBM at least do things
+ *
+ * @np: node to check
+ * @in_addr: pointer to input DMA address
+ * @return translated DMA address or OF_BAD_ADDR on error
+ */
+u64 of_translate_dma_address(const struct device_node *no, const __be32 *in_addr);
+
+/**
+ * of_get_address() - obtain an address from a node
+ *
+ * Extract an address from a node, returns the region size and the address
+ * space flags too. The PCI version uses a BAR number instead of an absolute
+ * index.
+ *
+ * @np: Node to check
+ * @index: Index of address to read (0 = first)
+ * @size: place to put size on success
+ * @flags: place to put flags on success
+ * @return pointer to address which can be read
+ */
+const __be32 *of_get_address(const struct device_node *no, int index,
+			     u64 *size, unsigned int *flags);
+
+struct resource;
+
+/**
+ * of_address_to_resource() - translate device tree address to resource
+ *
+ * Note that if your address is a PIO address, the conversion will fail if
+ * the physical address can't be internally converted to an IO token with
+ * pci_address_to_pio(), that is because it's either called to early or it
+ * can't be matched to any host bridge IO space
+ *
+ * @np: node to check
+ * @index: index of address to read (0 = first)
+ * @r: place to put resource information
+ * @return 0 if OK, -ve on error
+ */
+int of_address_to_resource(const struct device_node *no, int index,
+			   struct resource *r);
+
+#endif
diff --git a/include/dm/of_extra.h b/include/dm/of_extra.h
new file mode 100644
index 0000000..ca15df2
--- /dev/null
+++ b/include/dm/of_extra.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _DM_OF_EXTRA_H
+#define _DM_OF_EXTRA_H
+
+#include <dm/ofnode.h>
+
+enum fmap_compress_t {
+	FMAP_COMPRESS_NONE,
+	FMAP_COMPRESS_LZ4,
+};
+
+enum fmap_hash_t {
+	FMAP_HASH_NONE,
+	FMAP_HASH_SHA1,
+	FMAP_HASH_SHA256,
+};
+
+/* A flash map entry, containing an offset and length */
+struct fmap_entry {
+	uint32_t offset;
+	uint32_t length;
+	uint32_t used;			/* Number of bytes used in region */
+	enum fmap_compress_t compress_algo;	/* Compression type */
+	uint32_t unc_length;			/* Uncompressed length */
+	enum fmap_hash_t hash_algo;		/* Hash algorithm */
+	const uint8_t *hash;			/* Hash value */
+	int hash_size;				/* Hash size */
+};
+
+/**
+ * Read a flash entry from the fdt
+ *
+ * @param node		Reference to node to read
+ * @param entry		Place to put offset and size of this node
+ * @return 0 if ok, -ve on error
+ */
+int ofnode_read_fmap_entry(ofnode node, struct fmap_entry *entry);
+
+/**
+ * ofnode_decode_region() - Decode a memory region from a node
+ *
+ * Look up a property in a node which contains a memory region address and
+ * size. Then return a pointer to this address.
+ *
+ * The property must hold one address with a length. This is only tested on
+ * 32-bit machines.
+ *
+ * @param node		ofnode to examine
+ * @param prop_name	name of property to find
+ * @param basep		Returns base address of region
+ * @param size		Returns size of region
+ * @return 0 if ok, -1 on error (property not found)
+ */
+int ofnode_decode_region(ofnode node, const char *prop_name, fdt_addr_t *basep,
+			 fdt_size_t *sizep);
+
+/**
+ * ofnode_decode_memory_region()- Decode a named region within a memory bank
+ *
+ * This function handles selection of a memory region. The region is
+ * specified as an offset/size within a particular type of memory.
+ *
+ * The properties used are:
+ *
+ *	<mem_type>-memory<suffix> for the name of the memory bank
+ *	<mem_type>-offset<suffix> for the offset in that bank
+ *
+ * The property value must have an offset and a size. The function checks
+ * that the region is entirely within the memory bank.5
+ *
+ * @param node		ofnode containing the properties (-1 for /config)
+ * @param mem_type	Type of memory to use, which is a name, such as
+ *			"u-boot" or "kernel".
+ * @param suffix	String to append to the memory/offset
+ *			property names
+ * @param basep		Returns base of region
+ * @param sizep		Returns size of region
+ * @return 0 if OK, -ive on error
+ */
+int ofnode_decode_memory_region(ofnode config_node, const char *mem_type,
+				const char *suffix, fdt_addr_t *basep,
+				fdt_size_t *sizep);
+
+#endif
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
new file mode 100644
index 0000000..5c4cbf0
--- /dev/null
+++ b/include/dm/ofnode.h
@@ -0,0 +1,853 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _DM_OFNODE_H
+#define _DM_OFNODE_H
+
+/* TODO(sjg@chromium.org): Drop fdtdec.h include */
+#include <fdtdec.h>
+#include <dm/of.h>
+
+/* Enable checks to protect against invalid calls */
+#undef OF_CHECKS
+
+struct resource;
+
+/**
+ * ofnode - reference to a device tree node
+ *
+ * This union can hold either a straightforward pointer to a struct device_node
+ * in the live device tree, or an offset within the flat device tree. In the
+ * latter case, the pointer value is just the integer offset within the flat DT.
+ *
+ * Thus we can reference nodes in both the live tree (once available) and the
+ * flat tree (until then). Functions are available to translate between an
+ * ofnode and either an offset or a struct device_node *.
+ *
+ * The reference can also hold a null offset, in which case the pointer value
+ * here is NULL. This corresponds to a struct device_node * value of
+ * NULL, or an offset of -1.
+ *
+ * There is no ambiguity as to whether ofnode holds an offset or a node
+ * pointer: when the live tree is active it holds a node pointer, otherwise it
+ * holds an offset. The value itself does not need to be unique and in theory
+ * the same value could point to a valid device node or a valid offset. We
+ * could arrange for a unique value to be used (e.g. by making the pointer
+ * point to an offset within the flat device tree in the case of an offset) but
+ * this increases code size slightly due to the subtraction. Since it offers no
+ * real benefit, the approach described here seems best.
+ *
+ * For now these points use constant types, since we don't allow writing
+ * the DT.
+ *
+ * @np: Pointer to device node, used for live tree
+ * @of_offset: Pointer into flat device tree, used for flat tree. Note that this
+ *	is not a really a pointer to a node: it is an offset value. See above.
+ */
+typedef union ofnode_union {
+	const struct device_node *np;	/* will be used for future live tree */
+	long of_offset;
+} ofnode;
+
+struct ofnode_phandle_args {
+	ofnode node;
+	int args_count;
+	uint32_t args[OF_MAX_PHANDLE_ARGS];
+};
+
+/**
+ * _ofnode_to_np() - convert an ofnode to a live DT node pointer
+ *
+ * This cannot be called if the reference contains an offset.
+ *
+ * @node: Reference containing struct device_node * (possibly invalid)
+ * @return pointer to device node (can be NULL)
+ */
+static inline const struct device_node *ofnode_to_np(ofnode node)
+{
+#ifdef OF_CHECKS
+	if (!of_live_active())
+		return NULL;
+#endif
+	return node.np;
+}
+
+/**
+ * ofnode_to_offset() - convert an ofnode to a flat DT offset
+ *
+ * This cannot be called if the reference contains a node pointer.
+ *
+ * @node: Reference containing offset (possibly invalid)
+ * @return DT offset (can be -1)
+ */
+static inline int ofnode_to_offset(ofnode node)
+{
+#ifdef OF_CHECKS
+	if (of_live_active())
+		return -1;
+#endif
+	return node.of_offset;
+}
+
+/**
+ * ofnode_valid() - check if an ofnode is valid
+ *
+ * @return true if the reference contains a valid ofnode, false if it is NULL
+ */
+static inline bool ofnode_valid(ofnode node)
+{
+	if (of_live_active())
+		return node.np != NULL;
+	else
+		return node.of_offset != -1;
+}
+
+/**
+ * offset_to_ofnode() - convert a DT offset to an ofnode
+ *
+ * @of_offset: DT offset (either valid, or -1)
+ * @return reference to the associated DT offset
+ */
+static inline ofnode offset_to_ofnode(int of_offset)
+{
+	ofnode node;
+
+	if (of_live_active())
+		node.np = NULL;
+	else
+		node.of_offset = of_offset;
+
+	return node;
+}
+
+/**
+ * np_to_ofnode() - convert a node pointer to an ofnode
+ *
+ * @np: Live node pointer (can be NULL)
+ * @return reference to the associated node pointer
+ */
+static inline ofnode np_to_ofnode(const struct device_node *np)
+{
+	ofnode node;
+
+	node.np = np;
+
+	return node;
+}
+
+/**
+ * ofnode_is_np() - check if a reference is a node pointer
+ *
+ * This function associated that if there is a valid live tree then all
+ * references will use it. This is because using the flat DT when the live tree
+ * is valid is not permitted.
+ *
+ * @node: reference to check (possibly invalid)
+ * @return true if the reference is a live node pointer, false if it is a DT
+ * offset
+ */
+static inline bool ofnode_is_np(ofnode node)
+{
+#ifdef OF_CHECKS
+	/*
+	 * Check our assumption that flat tree offsets are not used when a
+	 * live tree is in use.
+	 */
+	assert(!ofnode_valid(node) ||
+	       (of_live_active() ? _ofnode_to_np(node)
+				  : _ofnode_to_np(node)));
+#endif
+	return of_live_active() && ofnode_valid(node);
+}
+
+/**
+ * ofnode_equal() - check if two references are equal
+ *
+ * @return true if equal, else false
+ */
+static inline bool ofnode_equal(ofnode ref1, ofnode ref2)
+{
+	/* We only need to compare the contents */
+	return ref1.of_offset == ref2.of_offset;
+}
+
+/**
+ * ofnode_null() - Obtain a null ofnode
+ *
+ * This returns an ofnode which points to no node. It works both with the flat
+ * tree and livetree.
+ */
+static inline ofnode ofnode_null(void)
+{
+	ofnode node;
+
+	if (of_live_active())
+		node.np = NULL;
+	else
+		node.of_offset = -1;
+
+	return node;
+}
+
+/**
+ * ofnode_read_u32() - Read a 32-bit integer from a property
+ *
+ * @ref:	valid node reference to read property from
+ * @propname:	name of the property to read from
+ * @outp:	place to put value (if found)
+ * @return 0 if OK, -ve on error
+ */
+int ofnode_read_u32(ofnode node, const char *propname, u32 *outp);
+
+/**
+ * ofnode_read_s32() - Read a 32-bit integer from a property
+ *
+ * @ref:	valid node reference to read property from
+ * @propname:	name of the property to read from
+ * @outp:	place to put value (if found)
+ * @return 0 if OK, -ve on error
+ */
+static inline int ofnode_read_s32(ofnode node, const char *propname,
+				  s32 *out_value)
+{
+	return ofnode_read_u32(node, propname, (u32 *)out_value);
+}
+
+/**
+ * ofnode_read_u32_default() - Read a 32-bit integer from a property
+ *
+ * @ref:	valid node reference to read property from
+ * @propname:	name of the property to read from
+ * @def:	default value to return if the property has no value
+ * @return property value, or @def if not found
+ */
+u32 ofnode_read_u32_default(ofnode ref, const char *propname, u32 def);
+
+/**
+ * ofnode_read_s32_default() - Read a 32-bit integer from a property
+ *
+ * @ref:	valid node reference to read property from
+ * @propname:	name of the property to read from
+ * @def:	default value to return if the property has no value
+ * @return property value, or @def if not found
+ */
+int ofnode_read_s32_default(ofnode node, const char *propname, s32 def);
+
+/**
+ * ofnode_read_u64() - Read a 64-bit integer from a property
+ *
+ * @node:	valid node reference to read property from
+ * @propname:	name of the property to read from
+ * @outp:	place to put value (if found)
+ * @return 0 if OK, -ve on error
+ */
+int ofnode_read_u64(ofnode node, const char *propname, u64 *outp);
+
+/**
+ * ofnode_read_u64_default() - Read a 64-bit integer from a property
+ *
+ * @ref:	valid node reference to read property from
+ * @propname:	name of the property to read from
+ * @def:	default value to return if the property has no value
+ * @return property value, or @def if not found
+ */
+u64 ofnode_read_u64_default(ofnode node, const char *propname, u64 def);
+
+/**
+ * ofnode_read_string() - Read a string from a property
+ *
+ * @ref:	valid node reference to read property from
+ * @propname:	name of the property to read
+ * @return string from property value, or NULL if there is no such property
+ */
+const char *ofnode_read_string(ofnode node, const char *propname);
+
+/**
+ * ofnode_read_u32_array() - Find and read an array of 32 bit integers
+ *
+ * @node:	valid node reference to read property from
+ * @propname:	name of the property to read
+ * @out_values:	pointer to return value, modified only if return value is 0
+ * @sz:		number of array elements to read
+ * @return 0 if OK, -ve on error
+ *
+ * Search for a property in a device node and read 32-bit value(s) from
+ * it. Returns 0 on success, -EINVAL if the property does not exist,
+ * -ENODATA if property does not have a value, and -EOVERFLOW if the
+ * property data isn't large enough.
+ *
+ * The out_values is modified only if a valid u32 value can be decoded.
+ */
+int ofnode_read_u32_array(ofnode node, const char *propname,
+			  u32 *out_values, size_t sz);
+
+/**
+ * ofnode_read_bool() - read a boolean value from a property
+ *
+ * @node:	valid node reference to read property from
+ * @propname:	name of property to read
+ * @return true if property is present (meaning true), false if not present
+ */
+bool ofnode_read_bool(ofnode node, const char *propname);
+
+/**
+ * ofnode_find_subnode() - find a named subnode of a parent node
+ *
+ * @node:	valid reference to parent node
+ * @subnode_name: name of subnode to find
+ * @return reference to subnode (which can be invalid if there is no such
+ * subnode)
+ */
+ofnode ofnode_find_subnode(ofnode node, const char *subnode_name);
+
+/**
+ * ofnode_first_subnode() - find the first subnode of a parent node
+ *
+ * @node:	valid reference to a valid parent node
+ * @return reference to the first subnode (which can be invalid if the parent
+ * node has no subnodes)
+ */
+ofnode ofnode_first_subnode(ofnode node);
+
+/**
+ * ofnode_next_subnode() - find the next sibling of a subnode
+ *
+ * @node:	valid reference to previous node (sibling)
+ * @return reference to the next subnode (which can be invalid if the node
+ * has no more siblings)
+ */
+ofnode ofnode_next_subnode(ofnode node);
+
+/**
+ * ofnode_get_parent() - get the ofnode's parent (enclosing ofnode)
+ *
+ * @node: valid node to look up
+ * @return ofnode reference of the parent node
+ */
+ofnode ofnode_get_parent(ofnode node);
+
+/**
+ * ofnode_get_name() - get the name of a node
+ *
+ * @node: valid node to look up
+ * @return name of node
+ */
+const char *ofnode_get_name(ofnode node);
+
+/**
+ * ofnode_get_by_phandle() - get ofnode from phandle
+ *
+ * @phandle:	phandle to look up
+ * @return ofnode reference to the phandle
+ */
+ofnode ofnode_get_by_phandle(uint phandle);
+
+/**
+ * ofnode_read_size() - read the size of a property
+ *
+ * @node: node to check
+ * @propname: property to check
+ * @return size of property if present, or -EINVAL if not
+ */
+int ofnode_read_size(ofnode node, const char *propname);
+
+/**
+ * ofnode_get_addr_size_index() - get an address/size from a node
+ *				  based on index
+ *
+ * This reads the register address/size from a node based on index
+ *
+ * @node: node to read from
+ * @index: Index of address to read (0 for first)
+ * @size: Pointer to size of the address
+ * @return address, or FDT_ADDR_T_NONE if not present or invalid
+ */
+phys_addr_t ofnode_get_addr_size_index(ofnode node, int index,
+				       fdt_size_t *size);
+
+/**
+ * ofnode_get_addr_index() - get an address from a node
+ *
+ * This reads the register address from a node
+ *
+ * @node: node to read from
+ * @index: Index of address to read (0 for first)
+ * @return address, or FDT_ADDR_T_NONE if not present or invalid
+ */
+phys_addr_t ofnode_get_addr_index(ofnode node, int index);
+
+/**
+ * ofnode_get_addr() - get an address from a node
+ *
+ * This reads the register address from a node
+ *
+ * @node: node to read from
+ * @return address, or FDT_ADDR_T_NONE if not present or invalid
+ */
+phys_addr_t ofnode_get_addr(ofnode node);
+
+/**
+ * ofnode_stringlist_search() - find a string in a string list and return index
+ *
+ * Note that it is possible for this function to succeed on property values
+ * that are not NUL-terminated. That's because the function will stop after
+ * finding the first occurrence of @string. This can for example happen with
+ * small-valued cell properties, such as #address-cells, when searching for
+ * the empty string.
+ *
+ * @node: node to check
+ * @propname: name of the property containing the string list
+ * @string: string to look up in the string list
+ *
+ * @return:
+ *   the index of the string in the list of strings
+ *   -ENODATA if the property is not found
+ *   -EINVAL on some other error
+ */
+int ofnode_stringlist_search(ofnode node, const char *propname,
+			     const char *string);
+
+/**
+ * ofnode_read_string_index() - obtain an indexed string from a string list
+ *
+ * Note that this will successfully extract strings from properties with
+ * non-NUL-terminated values. For example on small-valued cell properties
+ * this function will return the empty string.
+ *
+ * If non-NULL, the length of the string (on success) or a negative error-code
+ * (on failure) will be stored in the integer pointer to by lenp.
+ *
+ * @node: node to check
+ * @propname: name of the property containing the string list
+ * @index: index of the string to return
+ * @lenp: return location for the string length or an error code on failure
+ *
+ * @return:
+ *   length of string, if found or -ve error value if not found
+ */
+int ofnode_read_string_index(ofnode node, const char *propname, int index,
+			     const char **outp);
+
+/**
+ * ofnode_read_string_count() - find the number of strings in a string list
+ *
+ * @node: node to check
+ * @propname: name of the property containing the string list
+ * @return:
+ *   number of strings in the list, or -ve error value if not found
+ */
+int ofnode_read_string_count(ofnode node, const char *property);
+
+/**
+ * ofnode_parse_phandle_with_args() - Find a node pointed by phandle in a list
+ *
+ * This function is useful to parse lists of phandles and their arguments.
+ * Returns 0 on success and fills out_args, on error returns appropriate
+ * errno value.
+ *
+ * Caller is responsible to call of_node_put() on the returned out_args->np
+ * pointer.
+ *
+ * Example:
+ *
+ * phandle1: node1 {
+ *	#list-cells = <2>;
+ * }
+ *
+ * phandle2: node2 {
+ *	#list-cells = <1>;
+ * }
+ *
+ * node3 {
+ *	list = <&phandle1 1 2 &phandle2 3>;
+ * }
+ *
+ * To get a device_node of the `node2' node you may call this:
+ * ofnode_parse_phandle_with_args(node3, "list", "#list-cells", 0, 1, &args);
+ *
+ * @node:	device tree node containing a list
+ * @list_name:	property name that contains a list
+ * @cells_name:	property name that specifies phandles' arguments count
+ * @cells_count: Cell count to use if @cells_name is NULL
+ * @index:	index of a phandle to parse out
+ * @out_args:	optional pointer to output arguments structure (will be filled)
+ * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if
+ *	@list_name does not exist, -EINVAL if a phandle was not found,
+ *	@cells_name could not be found, the arguments were truncated or there
+ *	were too many arguments.
+ */
+int ofnode_parse_phandle_with_args(ofnode node, const char *list_name,
+				   const char *cells_name, int cell_count,
+				   int index,
+				   struct ofnode_phandle_args *out_args);
+
+/**
+ * ofnode_count_phandle_with_args() - Count number of phandle in a list
+ *
+ * This function is useful to count phandles into a list.
+ * Returns number of phandle on success, on error returns appropriate
+ * errno value.
+ *
+ * @node:	device tree node containing a list
+ * @list_name:	property name that contains a list
+ * @cells_name:	property name that specifies phandles' arguments count
+ * @return number of phandle on success, -ENOENT if @list_name does not
+ *      exist, -EINVAL if a phandle was not found, @cells_name could not
+ *      be found.
+ */
+int ofnode_count_phandle_with_args(ofnode node, const char *list_name,
+				   const char *cells_name);
+
+/**
+ * ofnode_path() - find a node by full path
+ *
+ * @path: Full path to node, e.g. "/bus/spi@1"
+ * @return reference to the node found. Use ofnode_valid() to check if it exists
+ */
+ofnode ofnode_path(const char *path);
+
+/**
+ * ofnode_get_chosen_prop() - get the value of a chosen property
+ *
+ * This looks for a property within the /chosen node and returns its value
+ *
+ * @propname: Property name to look for
+ * @return property value if found, else NULL
+ */
+const char *ofnode_get_chosen_prop(const char *propname);
+
+/**
+ * ofnode_get_chosen_node() - get the chosen node
+ *
+ * @return the chosen node if present, else ofnode_null()
+ */
+ofnode ofnode_get_chosen_node(const char *name);
+
+struct display_timing;
+/**
+ * ofnode_decode_display_timing() - decode display timings
+ *
+ * Decode display timings from the supplied 'display-timings' node.
+ * See doc/device-tree-bindings/video/display-timing.txt for binding
+ * information.
+ *
+ * @node	'display-timing' node containing the timing subnodes
+ * @index	Index number to read (0=first timing subnode)
+ * @config	Place to put timings
+ * @return 0 if OK, -FDT_ERR_NOTFOUND if not found
+ */
+int ofnode_decode_display_timing(ofnode node, int index,
+				 struct display_timing *config);
+
+/**
+ * ofnode_get_property()- - get a pointer to the value of a node property
+ *
+ * @node: node to read
+ * @propname: property to read
+ * @lenp: place to put length on success
+ * @return pointer to property, or NULL if not found
+ */
+const void *ofnode_get_property(ofnode node, const char *propname, int *lenp);
+
+/**
+ * ofnode_is_available() - check if a node is marked available
+ *
+ * @node: node to check
+ * @return true if node's 'status' property is "okay" (or is missing)
+ */
+bool ofnode_is_available(ofnode node);
+
+/**
+ * ofnode_get_addr_size() - get address and size from a property
+ *
+ * This does no address translation. It simply reads an property that contains
+ * an address and a size value, one after the other.
+ *
+ * @node: node to read from
+ * @propname: property to read
+ * @sizep: place to put size value (on success)
+ * @return address value, or FDT_ADDR_T_NONE on error
+ */
+phys_addr_t ofnode_get_addr_size(ofnode node, const char *propname,
+				 phys_size_t *sizep);
+
+/**
+ * ofnode_read_u8_array_ptr() - find an 8-bit array
+ *
+ * Look up a property in a node and return a pointer to its contents as a
+ * byte array of given length. The property must have at least enough data
+ * for the array (count bytes). It may have more, but this will be ignored.
+ * The data is not copied.
+ *
+ * @node	node to examine
+ * @propname	name of property to find
+ * @sz		number of array elements
+ * @return pointer to byte array if found, or NULL if the property is not
+ *		found or there is not enough data
+ */
+const uint8_t *ofnode_read_u8_array_ptr(ofnode node, const char *propname,
+					size_t sz);
+
+/**
+ * ofnode_read_pci_addr() - look up a PCI address
+ *
+ * Look at an address property in a node and return the PCI address which
+ * corresponds to the given type in the form of fdt_pci_addr.
+ * The property must hold one fdt_pci_addr with a lengh.
+ *
+ * @node	node to examine
+ * @type	pci address type (FDT_PCI_SPACE_xxx)
+ * @propname	name of property to find
+ * @addr	returns pci address in the form of fdt_pci_addr
+ * @return 0 if ok, -ENOENT if the property did not exist, -EINVAL if the
+ *		format of the property was invalid, -ENXIO if the requested
+ *		address type was not found
+ */
+int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type,
+			 const char *propname, struct fdt_pci_addr *addr);
+
+/**
+ * ofnode_read_pci_vendev() - look up PCI vendor and device id
+ *
+ * Look at the compatible property of a device node that represents a PCI
+ * device and extract pci vendor id and device id from it.
+ *
+ * @param node		node to examine
+ * @param vendor	vendor id of the pci device
+ * @param device	device id of the pci device
+ * @return 0 if ok, negative on error
+ */
+int ofnode_read_pci_vendev(ofnode node, u16 *vendor, u16 *device);
+
+/**
+ * ofnode_read_addr_cells() - Get the number of address cells for a node
+ *
+ * This walks back up the tree to find the closest #address-cells property
+ * which controls the given node.
+ *
+ * @node: Node to check
+ * @return number of address cells this node uses
+ */
+int ofnode_read_addr_cells(ofnode node);
+
+/**
+ * ofnode_read_size_cells() - Get the number of size cells for a node
+ *
+ * This walks back up the tree to find the closest #size-cells property
+ * which controls the given node.
+ *
+ * @node: Node to check
+ * @return number of size cells this node uses
+ */
+int ofnode_read_size_cells(ofnode node);
+
+/**
+ * ofnode_read_simple_addr_cells() - Get the address cells property in a node
+ *
+ * This function matches fdt_address_cells().
+ *
+ * @np: Node pointer to check
+ * @return value of #address-cells property in this node, or 2 if none
+ */
+int ofnode_read_simple_addr_cells(ofnode node);
+
+/**
+ * ofnode_read_simple_size_cells() - Get the size cells property in a node
+ *
+ * This function matches fdt_size_cells().
+ *
+ * @np: Node pointer to check
+ * @return value of #size-cells property in this node, or 2 if none
+ */
+int ofnode_read_simple_size_cells(ofnode node);
+
+/**
+ * ofnode_pre_reloc() - check if a node should be bound before relocation
+ *
+ * Device tree nodes can be marked as needing-to-be-bound in the loader stages
+ * via special device tree properties.
+ *
+ * Before relocation this function can be used to check if nodes are required
+ * in either SPL or TPL stages.
+ *
+ * After relocation and jumping into the real U-Boot binary it is possible to
+ * determine if a node was bound in one of SPL/TPL stages.
+ *
+ * There are 4 settings currently in use
+ * - u-boot,dm-pre-proper: U-Boot proper pre-relocation only
+ * - u-boot,dm-pre-reloc: legacy and indicates any of TPL or SPL
+ *   Existing platforms only use it to indicate nodes needed in
+ *   SPL. Should probably be replaced by u-boot,dm-spl for
+ *   new platforms.
+ * - u-boot,dm-spl: SPL and U-Boot pre-relocation
+ * - u-boot,dm-tpl: TPL and U-Boot pre-relocation
+ *
+ * @node: node to check
+ * @return true if node is needed in SPL/TL, false otherwise
+ */
+bool ofnode_pre_reloc(ofnode node);
+
+/**
+ * ofnode_read_resource() - Read a resource from a node
+ *
+ * Read resource information from a node at the given index
+ *
+ * @node: Node to read from
+ * @index: Index of resource to read (0 = first)
+ * @res: Returns resource that was read, on success
+ * @return 0 if OK, -ve on error
+ */
+int ofnode_read_resource(ofnode node, uint index, struct resource *res);
+
+/**
+ * ofnode_read_resource_byname() - Read a resource from a node by name
+ *
+ * Read resource information from a node matching the given name. This uses a
+ * 'reg-names' string list property with the names matching the associated
+ * 'reg' property list.
+ *
+ * @node: Node to read from
+ * @name: Name of resource to read
+ * @res: Returns resource that was read, on success
+ * @return 0 if OK, -ve on error
+ */
+int ofnode_read_resource_byname(ofnode node, const char *name,
+				struct resource *res);
+
+/**
+ * ofnode_by_compatible() - Find the next compatible node
+ *
+ * Find the next node after @from that is compatible with @compat
+ *
+ * @from: ofnode to start from (use ofnode_null() to start at the beginning)
+ * @compat: Compatible string to match
+ * @return ofnode found, or ofnode_null() if none
+ */
+ofnode ofnode_by_compatible(ofnode from, const char *compat);
+
+/**
+ * ofnode_by_prop_value() - Find the next node with given property value
+ *
+ * Find the next node after @from that has a @propname with a value
+ * @propval and a length @proplen.
+ *
+ * @from: ofnode to start from (use ofnode_null() to start at the
+ * beginning) @propname: property name to check @propval: property value to
+ * search for @proplen: length of the value in propval @return ofnode
+ * found, or ofnode_null() if none
+ */
+ofnode ofnode_by_prop_value(ofnode from, const char *propname,
+			    const void *propval, int proplen);
+
+/**
+ * ofnode_for_each_subnode() - iterate over all subnodes of a parent
+ *
+ * @node:       child node (ofnode, lvalue)
+ * @parent:     parent node (ofnode)
+ *
+ * This is a wrapper around a for loop and is used like so:
+ *
+ *	ofnode node;
+ *
+ *	ofnode_for_each_subnode(node, parent) {
+ *		Use node
+ *		...
+ *	}
+ *
+ * Note that this is implemented as a macro and @node is used as
+ * iterator in the loop. The parent variable can be a constant or even a
+ * literal.
+ */
+#define ofnode_for_each_subnode(node, parent) \
+	for (node = ofnode_first_subnode(parent); \
+	     ofnode_valid(node); \
+	     node = ofnode_next_subnode(node))
+
+/**
+ * ofnode_translate_address() - Translate a device-tree address
+ *
+ * Translate an address from the device-tree into a CPU physical address. This
+ * function walks up the tree and applies the various bus mappings along the
+ * way.
+ *
+ * @ofnode: Device tree node giving the context in which to translate the
+ *          address
+ * @in_addr: pointer to the address to translate
+ * @return the translated address; OF_BAD_ADDR on error
+ */
+u64 ofnode_translate_address(ofnode node, const fdt32_t *in_addr);
+
+/**
+ * ofnode_translate_dma_address() - Translate a device-tree DMA address
+ *
+ * Translate a DMA address from the device-tree into a CPU physical address.
+ * This function walks up the tree and applies the various bus mappings along
+ * the way.
+ *
+ * @ofnode: Device tree node giving the context in which to translate the
+ *          DMA address
+ * @in_addr: pointer to the DMA address to translate
+ * @return the translated DMA address; OF_BAD_ADDR on error
+ */
+u64 ofnode_translate_dma_address(ofnode node, const fdt32_t *in_addr);
+
+/**
+ * ofnode_device_is_compatible() - check if the node is compatible with compat
+ *
+ * This allows to check whether the node is comaptible with the compat.
+ *
+ * @node:	Device tree node for which compatible needs to be verified.
+ * @compat:	Compatible string which needs to verified in the given node.
+ * @return true if OK, false if the compatible is not found
+ */
+int ofnode_device_is_compatible(ofnode node, const char *compat);
+
+/**
+ * ofnode_write_prop() - Set a property of a ofnode
+ *
+ * Note that the value passed to the function is *not* allocated by the
+ * function itself, but must be allocated by the caller if necessary.
+ *
+ * @node:	The node for whose property should be set
+ * @propname:	The name of the property to set
+ * @len:	The length of the new value of the property
+ * @value:	The new value of the property (must be valid prior to calling
+ *		the function)
+ * @return 0 if successful, -ve on error
+ */
+int ofnode_write_prop(ofnode node, const char *propname, int len,
+		      const void *value);
+
+/**
+ * ofnode_write_string() - Set a string property of a ofnode
+ *
+ * Note that the value passed to the function is *not* allocated by the
+ * function itself, but must be allocated by the caller if necessary.
+ *
+ * @node:	The node for whose string property should be set
+ * @propname:	The name of the string property to set
+ * @value:	The new value of the string property (must be valid prior to
+ *		calling the function)
+ * @return 0 if successful, -ve on error
+ */
+int ofnode_write_string(ofnode node, const char *propname, const char *value);
+
+/**
+ * ofnode_set_enabled() - Enable or disable a device tree node given by its
+ *			  ofnode
+ *
+ * This function effectively sets the node's "status" property to either "okay"
+ * or "disable", hence making it available for driver model initialization or
+ * not.
+ *
+ * @node:	The node to enable
+ * @value:	Flag that tells the function to either disable or enable the
+ *		node
+ * @return 0 if successful, -ve on error
+ */
+int ofnode_set_enabled(ofnode node, bool value);
+
+#endif
diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h
new file mode 100644
index 0000000..3eca34f
--- /dev/null
+++ b/include/dm/pinctrl.h
@@ -0,0 +1,457 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015  Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#ifndef __PINCTRL_H
+#define __PINCTRL_H
+
+#define PINNAME_SIZE	10
+#define PINMUX_SIZE	40
+
+/**
+ * struct pinconf_param - pin config parameters
+ *
+ * @property: property name in DT nodes
+ * @param: ID for this config parameter
+ * @default_value: default value for this config parameter used in case
+ *	no value is specified in DT nodes
+ */
+struct pinconf_param {
+	const char * const property;
+	unsigned int param;
+	u32 default_value;
+};
+
+/**
+ * struct pinctrl_ops - pin control operations, to be implemented by
+ * pin controller drivers.
+ *
+ * The @set_state is the only mandatory operation.  You can implement your
+ * pinctrl driver with its own @set_state.  In this case, the other callbacks
+ * are not required.  Otherwise, generic pinctrl framework is also available;
+ * use pinctrl_generic_set_state for @set_state, and implement other operations
+ * depending on your necessity.
+ *
+ * @get_pins_count: return number of selectable named pins available
+ *	in this driver.  (necessary to parse "pins" property in DTS)
+ * @get_pin_name: return the pin name of the pin selector,
+ *	called by the core to figure out which pin it shall do
+ *	operations to.  (necessary to parse "pins" property in DTS)
+ * @get_groups_count: return number of selectable named groups available
+ *	in this driver.  (necessary to parse "groups" property in DTS)
+ * @get_group_name: return the group name of the group selector,
+ *	called by the core to figure out which pin group it shall do
+ *	operations to.  (necessary to parse "groups" property in DTS)
+ * @get_functions_count: return number of selectable named functions available
+ *	in this driver.  (necessary for pin-muxing)
+ * @get_function_name: return the function name of the muxing selector,
+ *	called by the core to figure out which mux setting it shall map a
+ *	certain device to.  (necessary for pin-muxing)
+ * @pinmux_set: enable a certain muxing function with a certain pin.
+ *	The @func_selector selects a certain function whereas @pin_selector
+ *	selects a certain pin to be used. On simple controllers one of them
+ *	may be ignored.  (necessary for pin-muxing against a single pin)
+ * @pinmux_group_set: enable a certain muxing function with a certain pin
+ *	group.  The @func_selector selects a certain function whereas
+ *	@group_selector selects a certain set of pins to be used. On simple
+ *	controllers one of them may be ignored.
+ *	(necessary for pin-muxing against a pin group)
+ * @pinconf_num_params: number of driver-specific parameters to be parsed
+ *	from device trees  (necessary for pin-configuration)
+ * @pinconf_params: list of driver_specific parameters to be parsed from
+ *	device trees  (necessary for pin-configuration)
+ * @pinconf_set: configure an individual pin with a given parameter.
+ *	(necessary for pin-configuration against a single pin)
+ * @pinconf_group_set: configure all pins in a group with a given parameter.
+ *	(necessary for pin-configuration against a pin group)
+ * @set_state: do pinctrl operations specified by @config, a pseudo device
+ *	pointing a config node. (necessary for pinctrl_full)
+ * @set_state_simple: do needed pinctrl operations for a peripherl @periph.
+ *	(necessary for pinctrl_simple)
+ * @get_pin_muxing: display the muxing of a given pin.
+ * @gpio_request_enable: requests and enables GPIO on a certain pin.
+ *	Implement this only if you can mux every pin individually as GPIO. The
+ *	affected GPIO range is passed along with an offset(pin number) into that
+ *	specific GPIO range - function selectors and pin groups are orthogonal
+ *	to this, the core will however make sure the pins do not collide.
+ * @gpio_disable_free: free up GPIO muxing on a certain pin, the reverse of
+ *	@gpio_request_enable
+ */
+struct pinctrl_ops {
+	int (*get_pins_count)(struct udevice *dev);
+	const char *(*get_pin_name)(struct udevice *dev, unsigned selector);
+	int (*get_groups_count)(struct udevice *dev);
+	const char *(*get_group_name)(struct udevice *dev, unsigned selector);
+	int (*get_functions_count)(struct udevice *dev);
+	const char *(*get_function_name)(struct udevice *dev,
+					 unsigned selector);
+	int (*pinmux_set)(struct udevice *dev, unsigned pin_selector,
+			  unsigned func_selector);
+	int (*pinmux_group_set)(struct udevice *dev, unsigned group_selector,
+				unsigned func_selector);
+	unsigned int pinconf_num_params;
+	const struct pinconf_param *pinconf_params;
+	int (*pinconf_set)(struct udevice *dev, unsigned pin_selector,
+			   unsigned param, unsigned argument);
+	int (*pinconf_group_set)(struct udevice *dev, unsigned group_selector,
+				 unsigned param, unsigned argument);
+	int (*set_state)(struct udevice *dev, struct udevice *config);
+
+	/* for pinctrl-simple */
+	int (*set_state_simple)(struct udevice *dev, struct udevice *periph);
+	/**
+	 * request() - Request a particular pinctrl function
+	 *
+	 * This activates the selected function.
+	 *
+	 * @dev:	Device to adjust (UCLASS_PINCTRL)
+	 * @func:	Function number (driver-specific)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*request)(struct udevice *dev, int func, int flags);
+
+	/**
+	* get_periph_id() - get the peripheral ID for a device
+	*
+	* This generally looks at the peripheral's device tree node to work
+	* out the peripheral ID. The return value is normally interpreted as
+	* enum periph_id. so long as this is defined by the platform (which it
+	* should be).
+	*
+	* @dev:		Pinctrl device to use for decoding
+	* @periph:	Device to check
+	* @return peripheral ID of @periph, or -ENOENT on error
+	*/
+	int (*get_periph_id)(struct udevice *dev, struct udevice *periph);
+
+	/**
+	 * get_gpio_mux() - get the mux value for a particular GPIO
+	 *
+	 * This allows the raw mux value for a GPIO to be obtained. It is
+	 * useful for displaying the function being used by that GPIO, such
+	 * as with the 'gpio' command. This function is internal to the GPIO
+	 * subsystem and should not be used by generic code. Typically it is
+	 * used by a GPIO driver with knowledge of the SoC pinctrl setup.
+	 *
+	* @dev:		Pinctrl device to use
+	* @banknum:	GPIO bank number
+	* @index:	GPIO index within the bank
+	* @return mux value (SoC-specific, e.g. 0 for input, 1 for output)
+	 */
+	int (*get_gpio_mux)(struct udevice *dev, int banknum, int index);
+
+	/**
+	 * get_pin_muxing() - show pin muxing
+	 *
+	 * This allows to display the muxing of a given pin. It's useful for
+	 * debug purpose to know if a pin is configured as GPIO or as an
+	 * alternate function and which one.
+	 * Typically it is used by a PINCTRL driver with knowledge of the SoC
+	 * pinctrl setup.
+	 *
+	 * @dev:	Pinctrl device to use
+	 * @selector:	Pin selector
+	 * @buf		Pin's muxing description
+	 * @size	Pin's muxing description length
+	 * return 0 if OK, -ve on error
+	 */
+	 int (*get_pin_muxing)(struct udevice *dev, unsigned int selector,
+			       char *buf, int size);
+
+	/**
+	 * gpio_request_enable: requests and enables GPIO on a certain pin.
+	 *
+	 * @dev:	Pinctrl device to use
+	 * @selector:	Pin selector
+	 * return 0 if OK, -ve on error
+	 */
+	int (*gpio_request_enable)(struct udevice *dev, unsigned int selector);
+
+	/**
+	 * gpio_disable_free: free up GPIO muxing on a certain pin.
+	 *
+	 * @dev:	Pinctrl device to use
+	 * @selector:	Pin selector
+	 * return 0 if OK, -ve on error
+	 */
+	int (*gpio_disable_free)(struct udevice *dev, unsigned int selector);
+};
+
+#define pinctrl_get_ops(dev)	((struct pinctrl_ops *)(dev)->driver->ops)
+
+/**
+ * Generic pin configuration paramters
+ *
+ * enum pin_config_param - possible pin configuration parameters
+ * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
+ *	weakly drives the last value on a tristate bus, also known as a "bus
+ *	holder", "bus keeper" or "repeater". This allows another device on the
+ *	bus to change the value by driving the bus high or low and switching to
+ *	tristate. The argument is ignored.
+ * @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a
+ *	transition from say pull-up to pull-down implies that you disable
+ *	pull-up in the process, this setting disables all biasing.
+ * @PIN_CONFIG_BIAS_HIGH_IMPEDANCE: the pin will be set to a high impedance
+ *	mode, also know as "third-state" (tristate) or "high-Z" or "floating".
+ *	On output pins this effectively disconnects the pin, which is useful
+ *	if for example some other pin is going to drive the signal connected
+ *	to it for a while. Pins used for input are usually always high
+ *	impedance.
+ * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
+ *	impedance to GROUND). If the argument is != 0 pull-down is enabled,
+ *	if it is 0, pull-down is total, i.e. the pin is connected to GROUND.
+ * @PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: the pin will be pulled up or down based
+ *	on embedded knowledge of the controller hardware, like current mux
+ *	function. The pull direction and possibly strength too will normally
+ *	be decided completely inside the hardware block and not be readable
+ *	from the kernel side.
+ *	If the argument is != 0 pull up/down is enabled, if it is 0, the
+ *	configuration is ignored. The proper way to disable it is to use
+ *	@PIN_CONFIG_BIAS_DISABLE.
+ * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
+ *	impedance to VDD). If the argument is != 0 pull-up is enabled,
+ *	if it is 0, pull-up is total, i.e. the pin is connected to VDD.
+ * @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open
+ *	collector) which means it is usually wired with other output ports
+ *	which are then pulled up with an external resistor. Setting this
+ *	config will enable open drain mode, the argument is ignored.
+ * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source
+ *	(open emitter). Setting this config will enable open source mode, the
+ *	argument is ignored.
+ * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
+ *	low, this is the most typical case and is typically achieved with two
+ *	active transistors on the output. Setting this config will enable
+ *	push-pull mode, the argument is ignored.
+ * @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current
+ *	passed as argument. The argument is in mA.
+ * @PIN_CONFIG_DRIVE_STRENGTH_UA: the pin will sink or source at most the current
+ *	passed as argument. The argument is in uA.
+ * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
+ *	which means it will wait for signals to settle when reading inputs. The
+ *	argument gives the debounce time in usecs. Setting the
+ *	argument to zero turns debouncing off.
+ * @PIN_CONFIG_INPUT_ENABLE: enable the pin's input.  Note that this does not
+ *	affect the pin's ability to drive output.  1 enables input, 0 disables
+ *	input.
+ * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in
+ *	schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis,
+ *	the threshold value is given on a custom format as argument when
+ *	setting pins to this mode.
+ * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
+ *      If the argument != 0, schmitt-trigger mode is enabled. If it's 0,
+ *      schmitt-trigger mode is disabled.
+ * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
+ *	operation, if several modes of operation are supported these can be
+ *	passed in the argument on a custom form, else just use argument 1
+ *	to indicate low power mode, argument 0 turns low power mode off.
+ * @PIN_CONFIG_OUTPUT_ENABLE: this will enable the pin's output mode
+ *	without driving a value there. For most platforms this reduces to
+ *	enable the output buffers and then let the pin controller current
+ *	configuration (eg. the currently selected mux function) drive values on
+ *	the line. Use argument 1 to enable output mode, argument 0 to disable
+ *	it.
+ * @PIN_CONFIG_OUTPUT: this will configure the pin as an output and drive a
+ *	value on the line. Use argument 1 to indicate high level, argument 0 to
+ *	indicate low level. (Please see Documentation/driver-api/pinctl.rst,
+ *	section "GPIO mode pitfalls" for a discussion around this parameter.)
+ * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
+ *	supplies, the argument to this parameter (on a custom format) tells
+ *	the driver which alternative power source to use.
+ * @PIN_CONFIG_SLEEP_HARDWARE_STATE: indicate this is sleep related state.
+ * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
+ *	this parameter (on a custom format) tells the driver which alternative
+ *	slew rate to use.
+ * @PIN_CONFIG_SKEW_DELAY: if the pin has programmable skew rate (on inputs)
+ *	or latch delay (on outputs) this parameter (in a custom format)
+ *	specifies the clock skew or latch delay. It typically controls how
+ *	many double inverters are put in front of the line.
+ * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
+ *	you need to pass in custom configurations to the pin controller, use
+ *	PIN_CONFIG_END+1 as the base offset.
+ * @PIN_CONFIG_MAX: this is the maximum configuration value that can be
+ *	presented using the packed format.
+ */
+enum pin_config_param {
+	PIN_CONFIG_BIAS_BUS_HOLD,
+	PIN_CONFIG_BIAS_DISABLE,
+	PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
+	PIN_CONFIG_BIAS_PULL_DOWN,
+	PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
+	PIN_CONFIG_BIAS_PULL_UP,
+	PIN_CONFIG_DRIVE_OPEN_DRAIN,
+	PIN_CONFIG_DRIVE_OPEN_SOURCE,
+	PIN_CONFIG_DRIVE_PUSH_PULL,
+	PIN_CONFIG_DRIVE_STRENGTH,
+	PIN_CONFIG_DRIVE_STRENGTH_UA,
+	PIN_CONFIG_INPUT_DEBOUNCE,
+	PIN_CONFIG_INPUT_ENABLE,
+	PIN_CONFIG_INPUT_SCHMITT,
+	PIN_CONFIG_INPUT_SCHMITT_ENABLE,
+	PIN_CONFIG_LOW_POWER_MODE,
+	PIN_CONFIG_OUTPUT_ENABLE,
+	PIN_CONFIG_OUTPUT,
+	PIN_CONFIG_POWER_SOURCE,
+	PIN_CONFIG_SLEEP_HARDWARE_STATE,
+	PIN_CONFIG_SLEW_RATE,
+	PIN_CONFIG_SKEW_DELAY,
+	PIN_CONFIG_END = 0x7F,
+	PIN_CONFIG_MAX = 0xFF,
+};
+
+#if CONFIG_IS_ENABLED(PINCTRL_GENERIC)
+/**
+ * pinctrl_generic_set_state() - generic set_state operation
+ * Parse the DT node of @config and its children and handle generic properties
+ * such as "pins", "groups", "functions", and pin configuration parameters.
+ *
+ * @pctldev: pinctrl device
+ * @config: config device (pseudo device), pointing a config node in DTS
+ * @return: 0 on success, or negative error code on failure
+ */
+int pinctrl_generic_set_state(struct udevice *pctldev, struct udevice *config);
+#else
+static inline int pinctrl_generic_set_state(struct udevice *pctldev,
+					    struct udevice *config)
+{
+	return -EINVAL;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(PINCTRL)
+/**
+ * pinctrl_select_state() - set a device to a given state
+ *
+ * @dev: peripheral device
+ * @statename: state name, like "default"
+ * @return: 0 on success, or negative error code on failure
+ */
+int pinctrl_select_state(struct udevice *dev, const char *statename);
+#else
+static inline int pinctrl_select_state(struct udevice *dev,
+				       const char *statename)
+{
+	return -EINVAL;
+}
+#endif
+
+/**
+ * pinctrl_request() - Request a particular pinctrl function
+ *
+ * @dev:	Device to check (UCLASS_PINCTRL)
+ * @func:	Function number (driver-specific)
+ * @flags:	Flags (driver-specific)
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_request(struct udevice *dev, int func, int flags);
+
+/**
+ * pinctrl_request_noflags() - Request a particular pinctrl function
+ *
+ * This is similar to pinctrl_request() but uses 0 for @flags.
+ *
+ * @dev:	Device to check (UCLASS_PINCTRL)
+ * @func:	Function number (driver-specific)
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_request_noflags(struct udevice *dev, int func);
+
+/**
+ * pinctrl_get_periph_id() - get the peripheral ID for a device
+ *
+ * This generally looks at the peripheral's device tree node to work out the
+ * peripheral ID. The return value is normally interpreted as enum periph_id.
+ * so long as this is defined by the platform (which it should be).
+ *
+ * @dev:	Pinctrl device to use for decoding
+ * @periph:	Device to check
+ * @return peripheral ID of @periph, or -ENOENT on error
+ */
+int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph);
+
+/**
+ * pinctrl_decode_pin_config() - decode pin configuration flags
+ *
+ * This decodes some of the PIN_CONFIG values into flags, with each value
+ * being (1 << pin_cfg). This does not support things with values like the
+ * slew rate.
+ *
+ * @blob:	Device tree blob
+ * @node:	Node containing the PIN_CONFIG values
+ * @return decoded flag value, or -ve on error
+ */
+int pinctrl_decode_pin_config(const void *blob, int node);
+
+/**
+ * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO
+ *
+ * This allows the raw mux value for a GPIO to be obtained. It is
+ * useful for displaying the function being used by that GPIO, such
+ * as with the 'gpio' command. This function is internal to the GPIO
+ * subsystem and should not be used by generic code. Typically it is
+ * used by a GPIO driver with knowledge of the SoC pinctrl setup.
+ *
+ * @dev:	Pinctrl device to use
+ * @banknum:	GPIO bank number
+ * @index:	GPIO index within the bank
+ * @return mux value (SoC-specific, e.g. 0 for input, 1 for output)
+*/
+int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index);
+
+/**
+ * pinctrl_get_pin_muxing() - Returns the muxing description
+ *
+ * This allows to display the muxing description of the given pin for
+ * debug purpose
+ *
+ * @dev:	Pinctrl device to use
+ * @selector	Pin index within pin-controller
+ * @buf		Pin's muxing description
+ * @size	Pin's muxing description length
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_get_pin_muxing(struct udevice *dev, int selector, char *buf,
+			   int size);
+
+/**
+ * pinctrl_get_pins_count() - display pin-controller pins number
+ *
+ * This allows to know the number of pins owned by a given pin-controller
+ *
+ * @dev:	Pinctrl device to use
+ * @return pins number if OK, -ve on error
+ */
+int pinctrl_get_pins_count(struct udevice *dev);
+
+/**
+ * pinctrl_get_pin_name() - Returns the pin's name
+ *
+ * This allows to display the pin's name for debug purpose
+ *
+ * @dev:	Pinctrl device to use
+ * @selector	Pin index within pin-controller
+ * @buf		Pin's name
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_get_pin_name(struct udevice *dev, int selector, char *buf,
+			 int size);
+
+/**
+ * pinctrl_gpio_request() - request a single pin to be used as GPIO
+ *
+ * @dev: GPIO peripheral device
+ * @offset: the GPIO pin offset from the GPIO controller
+ * @return: 0 on success, or negative error code on failure
+ */
+int pinctrl_gpio_request(struct udevice *dev, unsigned offset);
+
+/**
+ * pinctrl_gpio_free() - free a single pin used as GPIO
+ *
+ * @dev: GPIO peripheral device
+ * @offset: the GPIO pin offset from the GPIO controller
+ * @return: 0 on success, or negative error code on failure
+ */
+int pinctrl_gpio_free(struct udevice *dev, unsigned offset);
+
+#endif /* __PINCTRL_H */
diff --git a/include/dm/platdata.h b/include/dm/platdata.h
new file mode 100644
index 0000000..c972fa6
--- /dev/null
+++ b/include/dm/platdata.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ */
+
+#ifndef _DM_PLATDATA_H
+#define _DM_PLATDATA_H
+
+#include <linker_lists.h>
+
+/**
+ * struct driver_info - Information required to instantiate a device
+ *
+ * NOTE: Avoid using this except in extreme circumstances, where device tree
+ * is not feasible (e.g. serial driver in SPL where <8KB of SRAM is
+ * available). U-Boot's driver model uses device tree for configuration.
+ *
+ * @name:	Driver name
+ * @platdata:	Driver-specific platform data
+ * @platdata_size: Size of platform data structure
+ */
+struct driver_info {
+	const char *name;
+	const void *platdata;
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	uint platdata_size;
+#endif
+};
+
+/**
+ * NOTE: Avoid using these except in extreme circumstances, where device tree
+ * is not feasible (e.g. serial driver in SPL where <8KB of SRAM is
+ * available). U-Boot's driver model uses device tree for configuration.
+ */
+#define U_BOOT_DEVICE(__name)						\
+	ll_entry_declare(struct driver_info, __name, driver_info)
+
+/* Declare a list of devices. The argument is a driver_info[] array */
+#define U_BOOT_DEVICES(__name)						\
+	ll_entry_declare_list(struct driver_info, __name, driver_info)
+
+#endif
diff --git a/include/dm/platform_data/lpc32xx_hsuart.h b/include/dm/platform_data/lpc32xx_hsuart.h
new file mode 100644
index 0000000..9bfd628
--- /dev/null
+++ b/include/dm/platform_data/lpc32xx_hsuart.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
+ */
+
+#ifndef _LPC32XX_HSUART_PLAT_H
+#define _LPC32XX_HSUART_PLAT_H
+
+/**
+ * struct lpc32xx_hsuart_platdata - NXP LPC32xx HSUART platform data
+ *
+ * @base:               Base register address
+ */
+struct lpc32xx_hsuart_platdata {
+	unsigned long base;
+};
+
+#endif
diff --git a/include/dm/platform_data/net_ethoc.h b/include/dm/platform_data/net_ethoc.h
new file mode 100644
index 0000000..855e999
--- /dev/null
+++ b/include/dm/platform_data/net_ethoc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Cadence Design Systems Inc.
+ */
+
+#ifndef _ETHOC_H
+#define _ETHOC_H
+
+#include <net.h>
+
+#ifdef CONFIG_DM_ETH
+
+struct ethoc_eth_pdata {
+	struct eth_pdata eth_pdata;
+	phys_addr_t packet_base;
+};
+
+#endif
+
+#endif /* _ETHOC_H */
diff --git a/include/dm/platform_data/pfe_dm_eth.h b/include/dm/platform_data/pfe_dm_eth.h
new file mode 100644
index 0000000..100a981
--- /dev/null
+++ b/include/dm/platform_data/pfe_dm_eth.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef __PFE_DM_ETH_H__
+#define __PFE_DM_ETH_H__
+#include <net.h>
+
+struct pfe_ddr_address {
+	void *ddr_pfe_baseaddr;
+	unsigned long ddr_pfe_phys_baseaddr;
+};
+
+struct pfe_eth_pdata {
+	struct eth_pdata pfe_eth_pdata_mac;
+	struct pfe_ddr_address pfe_ddr_addr;
+};
+#endif /* __PFE_DM_ETH_H__ */
diff --git a/include/dm/platform_data/serial_bcm283x_mu.h b/include/dm/platform_data/serial_bcm283x_mu.h
new file mode 100644
index 0000000..37f5174
--- /dev/null
+++ b/include/dm/platform_data/serial_bcm283x_mu.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Stephen Warren <swarren@wwwdotorg.org>
+ *
+ * Derived from pl01x code:
+ * Copyright (c) 2014 Google, Inc
+ */
+
+#ifndef __serial_bcm283x_mu_h
+#define __serial_bcm283x_mu_h
+
+/*
+ *Information about a serial port
+ *
+ * @base: Register base address
+ */
+struct bcm283x_mu_serial_platdata {
+	unsigned long base;
+	unsigned int clock;
+	bool skip_init;
+};
+
+#endif
diff --git a/include/dm/platform_data/serial_coldfire.h b/include/dm/platform_data/serial_coldfire.h
new file mode 100644
index 0000000..ba916fe
--- /dev/null
+++ b/include/dm/platform_data/serial_coldfire.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015  Angelo Dureghello <angelo@sysam.it>
+ */
+
+#ifndef __serial_coldfire_h
+#define __serial_coldfire_h
+
+/*
+ * struct coldfire_serial_platdata - information about a coldfire port
+ *
+ * @base:               Uart port base register address
+ * @port:               Uart port index, for cpu with pinmux for uart / gpio
+ * baudrtatre:          Uart port baudrate
+ */
+struct coldfire_serial_platdata {
+	unsigned long base;
+	int port;
+	int baudrate;
+};
+
+#endif /* __serial_coldfire_h */
diff --git a/include/dm/platform_data/serial_mxc.h b/include/dm/platform_data/serial_mxc.h
new file mode 100644
index 0000000..86cd3bc
--- /dev/null
+++ b/include/dm/platform_data/serial_mxc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc
+ */
+
+#ifndef __serial_mxc_h
+#define __serial_mxc_h
+
+/* Information about a serial port */
+struct mxc_serial_platdata {
+	struct mxc_uart *reg;  /* address of registers in physical memory */
+	bool use_dte;
+};
+
+#endif
diff --git a/include/dm/platform_data/serial_pl01x.h b/include/dm/platform_data/serial_pl01x.h
new file mode 100644
index 0000000..77d96c4
--- /dev/null
+++ b/include/dm/platform_data/serial_pl01x.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc
+ */
+
+#ifndef __serial_pl01x_h
+#define __serial_pl01x_h
+
+enum pl01x_type {
+	TYPE_PL010,
+	TYPE_PL011,
+};
+
+/*
+ *Information about a serial port
+ *
+ * @base: Register base address
+ * @type: Port type
+ * @clock: Input clock rate, used for calculating the baud rate divisor
+ * @skip_init: Don't attempt to change port configuration (also means @clock
+ * is ignored)
+ */
+struct pl01x_serial_platdata {
+	unsigned long base;
+	enum pl01x_type type;
+	unsigned int clock;
+	bool skip_init;
+};
+
+#endif
diff --git a/include/dm/platform_data/serial_pxa.h b/include/dm/platform_data/serial_pxa.h
new file mode 100644
index 0000000..408c008
--- /dev/null
+++ b/include/dm/platform_data/serial_pxa.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
+ */
+
+#ifndef __SERIAL_PXA_H
+#define __SERIAL_PXA_H
+
+/*
+ * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
+ * easily handle enabling of clock.
+ */
+#ifdef CONFIG_CPU_MONAHANS
+#define UART_CLK_BASE	CKENA_21_BTUART
+#define UART_CLK_REG	CKENA
+#define BTUART_INDEX	0
+#define FFUART_INDEX	1
+#define STUART_INDEX	2
+#elif CONFIG_CPU_PXA25X
+#define UART_CLK_BASE	(1 << 4)	/* HWUART */
+#define UART_CLK_REG	CKEN
+#define HWUART_INDEX	0
+#define STUART_INDEX	1
+#define FFUART_INDEX	2
+#define BTUART_INDEX	3
+#else /* PXA27x */
+#define UART_CLK_BASE	CKEN5_STUART
+#define UART_CLK_REG	CKEN
+#define STUART_INDEX	0
+#define FFUART_INDEX	1
+#define BTUART_INDEX	2
+#endif
+
+/*
+ * Only PXA250 has HWUART, to avoid poluting the code with more macros,
+ * artificially introduce this.
+ */
+#ifndef CONFIG_CPU_PXA25X
+#define HWUART_INDEX	0xff
+#endif
+
+/*
+ * struct pxa_serial_platdata - information about a PXA port
+ *
+ * @base:               Uart port base register address
+ * @port:               Uart port index, for cpu with pinmux for uart / gpio
+ * baudrtatre:          Uart port baudrate
+ */
+struct pxa_serial_platdata {
+	struct pxa_uart_regs *base;
+	int port;
+	int baudrate;
+};
+
+#endif /* __SERIAL_PXA_H */
diff --git a/include/dm/platform_data/serial_sh.h b/include/dm/platform_data/serial_sh.h
new file mode 100644
index 0000000..711435d
--- /dev/null
+++ b/include/dm/platform_data/serial_sh.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (c) 2014  Renesas Electronics Corporation
+ */
+
+#ifndef __serial_sh_h
+#define __serial_sh_h
+
+enum sh_clk_mode {
+	INT_CLK,
+	EXT_CLK,
+};
+
+enum sh_serial_type {
+	PORT_SCI,
+	PORT_SCIF,
+	PORT_SCIFA,
+	PORT_SCIFB,
+};
+
+/*
+ * Information about SCIF port
+ *
+ * @base:	Register base address
+ * @clk:	Input clock rate, used for calculating the baud rate divisor
+ * @clk_mode:	Clock mode, set internal (INT) or external (EXT)
+ * @type:	Type of SCIF
+ */
+struct sh_serial_platdata {
+	unsigned long base;
+	unsigned int clk;
+	enum sh_clk_mode clk_mode;
+	enum sh_serial_type type;
+};
+#endif /* __serial_sh_h */
diff --git a/include/dm/platform_data/spi_coldfire.h b/include/dm/platform_data/spi_coldfire.h
new file mode 100644
index 0000000..8ad8eae
--- /dev/null
+++ b/include/dm/platform_data/spi_coldfire.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018  Angelo Dureghello <angelo@sysam.it>
+ */
+
+#ifndef __spi_coldfire_h
+#define __spi_coldfire_h
+
+#define MAX_CTAR_REGS		8
+#define MAX_CTAR_FIELDS		8
+
+/*
+ * struct coldfire_spi_platdata - information about a coldfire spi module
+ *
+ * @regs_addr: base address for module registers
+ * @speed_hz: default SCK frequency
+ * @mode: default SPI mode
+ * @num_cs: number of DSPI chipselect signals
+ */
+struct coldfire_spi_platdata {
+	fdt_addr_t regs_addr;
+	uint speed_hz;
+	uint mode;
+	uint num_cs;
+	uint ctar[MAX_CTAR_REGS][MAX_CTAR_FIELDS];
+};
+
+#endif /* __spi_coldfire_h */
+
diff --git a/include/dm/platform_data/spi_davinci.h b/include/dm/platform_data/spi_davinci.h
new file mode 100644
index 0000000..fbc62c2
--- /dev/null
+++ b/include/dm/platform_data/spi_davinci.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __spi_davinci_h
+#define __spi_davinci_h
+
+struct davinci_spi_platdata {
+	struct davinci_spi_regs *regs;
+	u8 num_cs;	   /* total no. of CS available */
+};
+
+#endif /* __spi_davinci_h */
diff --git a/include/dm/platform_data/spi_pl022.h b/include/dm/platform_data/spi_pl022.h
new file mode 100644
index 0000000..63a58ee
--- /dev/null
+++ b/include/dm/platform_data/spi_pl022.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
+ *
+ * Structure for use with U_BOOT_DEVICE for pl022 SPI devices or to use
+ * in ofdata_to_platdata.
+ */
+
+#ifndef __spi_pl022_h
+#define __spi_pl022_h
+
+#include <fdtdec.h>
+
+struct pl022_spi_pdata {
+	fdt_addr_t addr;
+	fdt_size_t size;
+	unsigned int freq;
+};
+
+#endif /* __spi_pl022_h */
diff --git a/include/dm/read.h b/include/dm/read.h
new file mode 100644
index 0000000..d37fcb5
--- /dev/null
+++ b/include/dm/read.h
@@ -0,0 +1,892 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Function to read values from the device tree node attached to a udevice.
+ *
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _DM_READ_H
+#define _DM_READ_H
+
+#include <dm/fdtaddr.h>
+#include <dm/ofnode.h>
+#include <dm/uclass.h>
+
+struct resource;
+
+#if CONFIG_IS_ENABLED(OF_LIVE)
+static inline const struct device_node *dev_np(struct udevice *dev)
+{
+	return ofnode_to_np(dev->node);
+}
+#else
+static inline const struct device_node *dev_np(struct udevice *dev)
+{
+	return NULL;
+}
+#endif
+
+/**
+ * dev_ofnode() - get the DT node reference associated with a udevice
+ *
+ * @dev:	device to check
+ * @return reference of the the device's DT node
+ */
+static inline ofnode dev_ofnode(struct udevice *dev)
+{
+	return dev->node;
+}
+
+static inline bool dev_of_valid(struct udevice *dev)
+{
+	return ofnode_valid(dev_ofnode(dev));
+}
+
+#ifndef CONFIG_DM_DEV_READ_INLINE
+
+/**
+ * dev_read_u32() - read a 32-bit integer from a device's DT property
+ *
+ * @dev:	device to read DT property from
+ * @propname:	name of the property to read from
+ * @outp:	place to put value (if found)
+ * @return 0 if OK, -ve on error
+ */
+int dev_read_u32(struct udevice *dev, const char *propname, u32 *outp);
+
+/**
+ * dev_read_u32_default() - read a 32-bit integer from a device's DT property
+ *
+ * @dev:	device to read DT property from
+ * @propname:	name of the property to read from
+ * @def:	default value to return if the property has no value
+ * @return property value, or @def if not found
+ */
+int dev_read_u32_default(struct udevice *dev, const char *propname, int def);
+
+/**
+ * dev_read_s32() - read a signed 32-bit integer from a device's DT property
+ *
+ * @dev:	device to read DT property from
+ * @propname:	name of the property to read from
+ * @outp:	place to put value (if found)
+ * @return 0 if OK, -ve on error
+ */
+int dev_read_s32(struct udevice *dev, const char *propname, s32 *outp);
+
+/**
+ * dev_read_s32_default() - read a signed 32-bit int from a device's DT property
+ *
+ * @dev:	device to read DT property from
+ * @propname:	name of the property to read from
+ * @def:	default value to return if the property has no value
+ * @return property value, or @def if not found
+ */
+int dev_read_s32_default(struct udevice *dev, const char *propname, int def);
+
+/**
+ * dev_read_u32u() - read a 32-bit integer from a device's DT property
+ *
+ * This version uses a standard uint type.
+ *
+ * @dev:	device to read DT property from
+ * @propname:	name of the property to read from
+ * @outp:	place to put value (if found)
+ * @return 0 if OK, -ve on error
+ */
+int dev_read_u32u(struct udevice *dev, const char *propname, uint *outp);
+
+/**
+ * dev_read_u64() - read a 64-bit integer from a device's DT property
+ *
+ * @dev:        device to read DT property from
+ * @propname:   name of the property to read from
+ * @outp:       place to put value (if found)
+ * @return 0 if OK, -ve on error
+ */
+int dev_read_u64(struct udevice *dev, const char *propname, u64 *outp);
+
+/**
+ * dev_read_u64_default() - read a 64-bit integer from a device's DT property
+ *
+ * @dev:        device to read DT property from
+ * @propname:   name of the property to read from
+ * @def:        default value to return if the property has no value
+ * @return property value, or @def if not found
+ */
+u64 dev_read_u64_default(struct udevice *dev, const char *propname, u64 def);
+
+/**
+ * dev_read_string() - Read a string from a device's DT property
+ *
+ * @dev:	device to read DT property from
+ * @propname:	name of the property to read
+ * @return string from property value, or NULL if there is no such property
+ */
+const char *dev_read_string(struct udevice *dev, const char *propname);
+
+/**
+ * dev_read_bool() - read a boolean value from a device's DT property
+ *
+ * @dev:	device to read DT property from
+ * @propname:	name of property to read
+ * @return true if property is present (meaning true), false if not present
+ */
+bool dev_read_bool(struct udevice *dev, const char *propname);
+
+/**
+ * dev_read_subnode() - find a named subnode of a device
+ *
+ * @dev:	device whose DT node contains the subnode
+ * @subnode_name: name of subnode to find
+ * @return reference to subnode (which can be invalid if there is no such
+ * subnode)
+ */
+ofnode dev_read_subnode(struct udevice *dev, const char *subbnode_name);
+
+/**
+ * dev_read_size() - read the size of a property
+ *
+ * @dev: device to check
+ * @propname: property to check
+ * @return size of property if present, or -EINVAL if not
+ */
+int dev_read_size(struct udevice *dev, const char *propname);
+
+/**
+ * dev_read_addr_index() - Get the indexed reg property of a device
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ *	   and @index is used to select which one is required
+ *
+ * @return address or FDT_ADDR_T_NONE if not found
+ */
+fdt_addr_t dev_read_addr_index(struct udevice *dev, int index);
+
+/**
+ * dev_read_addr_size_index() - Get the indexed reg property of a device
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ *	   and @index is used to select which one is required
+ * @size: place to put size value (on success)
+ *
+ * @return address or FDT_ADDR_T_NONE if not found
+ */
+fdt_addr_t dev_read_addr_size_index(struct udevice *dev, int index,
+				    fdt_size_t *size);
+
+/**
+ * dev_remap_addr_index() - Get the indexed reg property of a device
+ *                               as a memory-mapped I/O pointer
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ *	   and @index is used to select which one is required
+ *
+ * @return pointer or NULL if not found
+ */
+void *dev_remap_addr_index(struct udevice *dev, int index);
+
+/**
+ * dev_read_addr_name() - Get the reg property of a device, indexed by name
+ *
+ * @dev: Device to read from
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ *	  'reg-names' property providing named-based identification. @index
+ *	  indicates the value to search for in 'reg-names'.
+ *
+ * @return address or FDT_ADDR_T_NONE if not found
+ */
+fdt_addr_t dev_read_addr_name(struct udevice *dev, const char* name);
+
+/**
+ * dev_read_addr_size_name() - Get the reg property of a device, indexed by name
+ *
+ * @dev: Device to read from
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ *	  'reg-names' property providing named-based identification. @index
+ *	  indicates the value to search for in 'reg-names'.
+ *  @size: place to put size value (on success)
+ *
+ * @return address or FDT_ADDR_T_NONE if not found
+ */
+fdt_addr_t dev_read_addr_size_name(struct udevice *dev, const char *name,
+				   fdt_size_t *size);
+
+/**
+ * dev_remap_addr_name() - Get the reg property of a device, indexed by name,
+ *                         as a memory-mapped I/O pointer
+ *
+ * @dev: Device to read from
+ * @name: the 'reg' property can hold a list of <addr, size> pairs, with the
+ *	  'reg-names' property providing named-based identification. @index
+ *	  indicates the value to search for in 'reg-names'.
+ *
+ * @return pointer or NULL if not found
+ */
+void *dev_remap_addr_name(struct udevice *dev, const char* name);
+
+/**
+ * dev_read_addr() - Get the reg property of a device
+ *
+ * @dev: Device to read from
+ *
+ * @return address or FDT_ADDR_T_NONE if not found
+ */
+fdt_addr_t dev_read_addr(struct udevice *dev);
+
+/**
+ * dev_read_addr_ptr() - Get the reg property of a device
+ *                       as a pointer
+ *
+ * @dev: Device to read from
+ *
+ * @return pointer or NULL if not found
+ */
+void *dev_read_addr_ptr(struct udevice *dev);
+
+/**
+ * dev_read_addr_pci() - Read an address and handle PCI address translation
+ *
+ * At present U-Boot does not have address translation logic for PCI in the
+ * livetree implementation (of_addr.c). This special function supports this for
+ * the flat tree implementation.
+ *
+ * This function should be removed (and code should use dev_read() instead)
+ * once:
+ *
+ * 1. PCI address translation is added; and either
+ * 2. everything uses livetree where PCI translation is used (which is feasible
+ *    in SPL and U-Boot proper) or PCI address translation is added to
+ *    fdtdec_get_addr() and friends.
+ *
+ * @dev: Device to read from
+ * @return address or FDT_ADDR_T_NONE if not found
+ */
+fdt_addr_t dev_read_addr_pci(struct udevice *dev);
+
+/**
+ * dev_remap_addr() - Get the reg property of a device as a
+ *                         memory-mapped I/O pointer
+ *
+ * @dev: Device to read from
+ *
+ * @return pointer or NULL if not found
+ */
+void *dev_remap_addr(struct udevice *dev);
+
+/**
+ * dev_read_addr_size() - get address and size from a device property
+ *
+ * This does no address translation. It simply reads an property that contains
+ * an address and a size value, one after the other.
+ *
+ * @dev: Device to read from
+ * @propname: property to read
+ * @sizep: place to put size value (on success)
+ * @return address value, or FDT_ADDR_T_NONE on error
+ */
+fdt_addr_t dev_read_addr_size(struct udevice *dev, const char *propname,
+				fdt_size_t *sizep);
+
+/**
+ * dev_read_name() - get the name of a device's node
+ *
+ * @dev: Device to read from
+ * @return name of node
+ */
+const char *dev_read_name(struct udevice *dev);
+
+/**
+ * dev_read_stringlist_search() - find string in a string list and return index
+ *
+ * Note that it is possible for this function to succeed on property values
+ * that are not NUL-terminated. That's because the function will stop after
+ * finding the first occurrence of @string. This can for example happen with
+ * small-valued cell properties, such as #address-cells, when searching for
+ * the empty string.
+ *
+ * @dev: device to check
+ * @propname: name of the property containing the string list
+ * @string: string to look up in the string list
+ *
+ * @return:
+ *   the index of the string in the list of strings
+ *   -ENODATA if the property is not found
+ *   -EINVAL on some other error
+ */
+int dev_read_stringlist_search(struct udevice *dev, const char *property,
+			  const char *string);
+
+/**
+ * dev_read_string_index() - obtain an indexed string from a string list
+ *
+ * @dev: device to examine
+ * @propname: name of the property containing the string list
+ * @index: index of the string to return
+ * @out: return location for the string
+ *
+ * @return:
+ *   length of string, if found or -ve error value if not found
+ */
+int dev_read_string_index(struct udevice *dev, const char *propname, int index,
+			  const char **outp);
+
+/**
+ * dev_read_string_count() - find the number of strings in a string list
+ *
+ * @dev: device to examine
+ * @propname: name of the property containing the string list
+ * @return:
+ *   number of strings in the list, or -ve error value if not found
+ */
+int dev_read_string_count(struct udevice *dev, const char *propname);
+/**
+ * dev_read_phandle_with_args() - Find a node pointed by phandle in a list
+ *
+ * This function is useful to parse lists of phandles and their arguments.
+ * Returns 0 on success and fills out_args, on error returns appropriate
+ * errno value.
+ *
+ * Caller is responsible to call of_node_put() on the returned out_args->np
+ * pointer.
+ *
+ * Example:
+ *
+ * phandle1: node1 {
+ *	#list-cells = <2>;
+ * }
+ *
+ * phandle2: node2 {
+ *	#list-cells = <1>;
+ * }
+ *
+ * node3 {
+ *	list = <&phandle1 1 2 &phandle2 3>;
+ * }
+ *
+ * To get a device_node of the `node2' node you may call this:
+ * dev_read_phandle_with_args(dev, "list", "#list-cells", 0, 1, &args);
+ *
+ * @dev:	device whose node containing a list
+ * @list_name:	property name that contains a list
+ * @cells_name:	property name that specifies phandles' arguments count
+ * @cells_count: Cell count to use if @cells_name is NULL
+ * @index:	index of a phandle to parse out
+ * @out_args:	optional pointer to output arguments structure (will be filled)
+ * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if
+ *	@list_name does not exist, -EINVAL if a phandle was not found,
+ *	@cells_name could not be found, the arguments were truncated or there
+ *	were too many arguments.
+ */
+int dev_read_phandle_with_args(struct udevice *dev, const char *list_name,
+				const char *cells_name, int cell_count,
+				int index,
+				struct ofnode_phandle_args *out_args);
+
+/**
+ * dev_count_phandle_with_args() - Return phandle number in a list
+ *
+ * This function is usefull to get phandle number contained in a property list.
+ * For example, this allows to allocate the right amount of memory to keep
+ * clock's reference contained into the "clocks" property.
+ *
+ *
+ * @dev:	device whose node containing a list
+ * @list_name:	property name that contains a list
+ * @cells_name:	property name that specifies phandles' arguments count
+ * @Returns number of phandle found on success, on error returns appropriate
+ * errno value.
+ */
+
+int dev_count_phandle_with_args(struct udevice *dev, const char *list_name,
+				const char *cells_name);
+
+/**
+ * dev_read_addr_cells() - Get the number of address cells for a device's node
+ *
+ * This walks back up the tree to find the closest #address-cells property
+ * which controls the given node.
+ *
+ * @dev: device to check
+ * @return number of address cells this node uses
+ */
+int dev_read_addr_cells(struct udevice *dev);
+
+/**
+ * dev_read_size_cells() - Get the number of size cells for a device's node
+ *
+ * This walks back up the tree to find the closest #size-cells property
+ * which controls the given node.
+ *
+ * @dev: device to check
+ * @return number of size cells this node uses
+ */
+int dev_read_size_cells(struct udevice *dev);
+
+/**
+ * dev_read_addr_cells() - Get the address cells property in a node
+ *
+ * This function matches fdt_address_cells().
+ *
+ * @dev: device to check
+ * @return number of address cells this node uses
+ */
+int dev_read_simple_addr_cells(struct udevice *dev);
+
+/**
+ * dev_read_size_cells() - Get the size cells property in a node
+ *
+ * This function matches fdt_size_cells().
+ *
+ * @dev: device to check
+ * @return number of size cells this node uses
+ */
+int dev_read_simple_size_cells(struct udevice *dev);
+
+/**
+ * dev_read_phandle() - Get the phandle from a device
+ *
+ * @dev: device to check
+ * @return phandle (1 or greater), or 0 if no phandle or other error
+ */
+int dev_read_phandle(struct udevice *dev);
+
+/**
+ * dev_read_prop()- - read a property from a device's node
+ *
+ * @dev: device to check
+ * @propname: property to read
+ * @lenp: place to put length on success
+ * @return pointer to property, or NULL if not found
+ */
+const void *dev_read_prop(struct udevice *dev, const char *propname, int *lenp);
+
+/**
+ * dev_read_alias_seq() - Get the alias sequence number of a node
+ *
+ * This works out whether a node is pointed to by an alias, and if so, the
+ * sequence number of that alias. Aliases are of the form <base><num> where
+ * <num> is the sequence number. For example spi2 would be sequence number 2.
+ *
+ * @dev: device to look up
+ * @devnump: set to the sequence number if one is found
+ * @return 0 if a sequence was found, -ve if not
+ */
+int dev_read_alias_seq(struct udevice *dev, int *devnump);
+
+/**
+ * dev_read_u32_array() - Find and read an array of 32 bit integers
+ *
+ * Search for a property in a device node and read 32-bit value(s) from
+ * it.
+ *
+ * The out_values is modified only if a valid u32 value can be decoded.
+ *
+ * @dev: device to look up
+ * @propname:	name of the property to read
+ * @out_values:	pointer to return value, modified only if return value is 0
+ * @sz:		number of array elements to read
+ * @return 0 on success, -EINVAL if the property does not exist, -ENODATA if
+ * property does not have a value, and -EOVERFLOW if the property data isn't
+ * large enough.
+ */
+int dev_read_u32_array(struct udevice *dev, const char *propname,
+		       u32 *out_values, size_t sz);
+
+/**
+ * dev_read_first_subnode() - find the first subnode of a device's node
+ *
+ * @dev: device to look up
+ * @return reference to the first subnode (which can be invalid if the device's
+ * node has no subnodes)
+ */
+ofnode dev_read_first_subnode(struct udevice *dev);
+
+/**
+ * ofnode_next_subnode() - find the next sibling of a subnode
+ *
+ * @node:	valid reference to previous node (sibling)
+ * @return reference to the next subnode (which can be invalid if the node
+ * has no more siblings)
+ */
+ofnode dev_read_next_subnode(ofnode node);
+
+/**
+ * dev_read_u8_array_ptr() - find an 8-bit array
+ *
+ * Look up a device's node property and return a pointer to its contents as a
+ * byte array of given length. The property must have at least enough data
+ * for the array (count bytes). It may have more, but this will be ignored.
+ * The data is not copied.
+ *
+ * @dev: device to look up
+ * @propname: name of property to find
+ * @sz: number of array elements
+ * @return pointer to byte array if found, or NULL if the property is not
+ *		found or there is not enough data
+ */
+const uint8_t *dev_read_u8_array_ptr(struct udevice *dev, const char *propname,
+				     size_t sz);
+
+/**
+ * dev_read_enabled() - check whether a node is enabled
+ *
+ * This looks for a 'status' property. If this exists, then returns 1 if
+ * the status is 'ok' and 0 otherwise. If there is no status property,
+ * it returns 1 on the assumption that anything mentioned should be enabled
+ * by default.
+ *
+ * @dev: device to examine
+ * @return integer value 0 (not enabled) or 1 (enabled)
+ */
+int dev_read_enabled(struct udevice *dev);
+
+/**
+ * dev_read_resource() - obtain an indexed resource from a device.
+ *
+ * @dev: device to examine
+ * @index index of the resource to retrieve (0 = first)
+ * @res returns the resource
+ * @return 0 if ok, negative on error
+ */
+int dev_read_resource(struct udevice *dev, uint index, struct resource *res);
+
+/**
+ * dev_read_resource_byname() - obtain a named resource from a device.
+ *
+ * @dev: device to examine
+ * @name: name of the resource to retrieve
+ * @res: returns the resource
+ * @return 0 if ok, negative on error
+ */
+int dev_read_resource_byname(struct udevice *dev, const char *name,
+			     struct resource *res);
+
+/**
+ * dev_translate_address() - Translate a device-tree address
+ *
+ * Translate an address from the device-tree into a CPU physical address.  This
+ * function walks up the tree and applies the various bus mappings along the
+ * way.
+ *
+ * @dev: device giving the context in which to translate the address
+ * @in_addr: pointer to the address to translate
+ * @return the translated address; OF_BAD_ADDR on error
+ */
+u64 dev_translate_address(struct udevice *dev, const fdt32_t *in_addr);
+
+/**
+ * dev_translate_dma_address() - Translate a device-tree DMA address
+ *
+ * Translate a DMA address from the device-tree into a CPU physical address.
+ * This function walks up the tree and applies the various bus mappings along
+ * the way.
+ *
+ * @dev: device giving the context in which to translate the DMA address
+ * @in_addr: pointer to the DMA address to translate
+ * @return the translated DMA address; OF_BAD_ADDR on error
+ */
+u64 dev_translate_dma_address(struct udevice *dev, const fdt32_t *in_addr);
+
+/**
+ * dev_read_alias_highest_id - Get highest alias id for the given stem
+ * @stem:	Alias stem to be examined
+ *
+ * The function travels the lookup table to get the highest alias id for the
+ * given alias stem.
+ * @return alias ID, if found, else -1
+ */
+int dev_read_alias_highest_id(const char *stem);
+
+#else /* CONFIG_DM_DEV_READ_INLINE is enabled */
+
+static inline int dev_read_u32(struct udevice *dev,
+			       const char *propname, u32 *outp)
+{
+	return ofnode_read_u32(dev_ofnode(dev), propname, outp);
+}
+
+static inline int dev_read_u32_default(struct udevice *dev,
+				       const char *propname, int def)
+{
+	return ofnode_read_u32_default(dev_ofnode(dev), propname, def);
+}
+
+static inline int dev_read_s32(struct udevice *dev,
+			       const char *propname, s32 *outp)
+{
+	return ofnode_read_s32(dev_ofnode(dev), propname, outp);
+}
+
+static inline int dev_read_s32_default(struct udevice *dev,
+				       const char *propname, int def)
+{
+	return ofnode_read_s32_default(dev_ofnode(dev), propname, def);
+}
+
+static inline int dev_read_u32u(struct udevice *dev,
+				const char *propname, uint *outp)
+{
+	u32 val;
+	int ret;
+
+	ret = ofnode_read_u32(dev_ofnode(dev), propname, &val);
+	if (ret)
+		return ret;
+	*outp = val;
+
+	return 0;
+}
+
+static inline int dev_read_u64(struct udevice *dev,
+			       const char *propname, u64 *outp)
+{
+	return ofnode_read_u64(dev_ofnode(dev), propname, outp);
+}
+
+static inline u64 dev_read_u64_default(struct udevice *dev,
+				       const char *propname, u64 def)
+{
+	return ofnode_read_u64_default(dev_ofnode(dev), propname, def);
+}
+
+static inline const char *dev_read_string(struct udevice *dev,
+					  const char *propname)
+{
+	return ofnode_read_string(dev_ofnode(dev), propname);
+}
+
+static inline bool dev_read_bool(struct udevice *dev, const char *propname)
+{
+	return ofnode_read_bool(dev_ofnode(dev), propname);
+}
+
+static inline ofnode dev_read_subnode(struct udevice *dev,
+				      const char *subbnode_name)
+{
+	return ofnode_find_subnode(dev_ofnode(dev), subbnode_name);
+}
+
+static inline int dev_read_size(struct udevice *dev, const char *propname)
+{
+	return ofnode_read_size(dev_ofnode(dev), propname);
+}
+
+static inline fdt_addr_t dev_read_addr_index(struct udevice *dev, int index)
+{
+	return devfdt_get_addr_index(dev, index);
+}
+
+static inline fdt_addr_t dev_read_addr_size_index(struct udevice *dev,
+						  int index,
+						  fdt_size_t *size)
+{
+	return devfdt_get_addr_size_index(dev, index, size);
+}
+
+static inline fdt_addr_t dev_read_addr_name(struct udevice *dev,
+					    const char *name)
+{
+	return devfdt_get_addr_name(dev, name);
+}
+
+static inline fdt_addr_t dev_read_addr_size_name(struct udevice *dev,
+						 const char *name,
+						 fdt_size_t *size)
+{
+	return devfdt_get_addr_size_name(dev, name, size);
+}
+
+static inline fdt_addr_t dev_read_addr(struct udevice *dev)
+{
+	return devfdt_get_addr(dev);
+}
+
+static inline void *dev_read_addr_ptr(struct udevice *dev)
+{
+	return devfdt_get_addr_ptr(dev);
+}
+
+static inline fdt_addr_t dev_read_addr_pci(struct udevice *dev)
+{
+	return devfdt_get_addr_pci(dev);
+}
+
+static inline void *dev_remap_addr(struct udevice *dev)
+{
+	return devfdt_remap_addr(dev);
+}
+
+static inline void *dev_remap_addr_index(struct udevice *dev, int index)
+{
+	return devfdt_remap_addr_index(dev, index);
+}
+
+static inline void *dev_remap_addr_name(struct udevice *dev, const char *name)
+{
+	return devfdt_remap_addr_name(dev, name);
+}
+
+static inline fdt_addr_t dev_read_addr_size(struct udevice *dev,
+					    const char *propname,
+					    fdt_size_t *sizep)
+{
+	return ofnode_get_addr_size(dev_ofnode(dev), propname, sizep);
+}
+
+static inline const char *dev_read_name(struct udevice *dev)
+{
+	return ofnode_get_name(dev_ofnode(dev));
+}
+
+static inline int dev_read_stringlist_search(struct udevice *dev,
+					     const char *propname,
+					     const char *string)
+{
+	return ofnode_stringlist_search(dev_ofnode(dev), propname, string);
+}
+
+static inline int dev_read_string_index(struct udevice *dev,
+					const char *propname, int index,
+					const char **outp)
+{
+	return ofnode_read_string_index(dev_ofnode(dev), propname, index, outp);
+}
+
+static inline int dev_read_string_count(struct udevice *dev,
+					const char *propname)
+{
+	return ofnode_read_string_count(dev_ofnode(dev), propname);
+}
+
+static inline int dev_read_phandle_with_args(struct udevice *dev,
+		const char *list_name, const char *cells_name, int cell_count,
+		int index, struct ofnode_phandle_args *out_args)
+{
+	return ofnode_parse_phandle_with_args(dev_ofnode(dev), list_name,
+					      cells_name, cell_count, index,
+					      out_args);
+}
+
+static inline int dev_count_phandle_with_args(struct udevice *dev,
+		const char *list_name, const char *cells_name)
+{
+	return ofnode_count_phandle_with_args(dev_ofnode(dev), list_name,
+					      cells_name);
+}
+
+static inline int dev_read_addr_cells(struct udevice *dev)
+{
+	/* NOTE: this call should walk up the parent stack */
+	return fdt_address_cells(gd->fdt_blob, dev_of_offset(dev));
+}
+
+static inline int dev_read_size_cells(struct udevice *dev)
+{
+	/* NOTE: this call should walk up the parent stack */
+	return fdt_size_cells(gd->fdt_blob, dev_of_offset(dev));
+}
+
+static inline int dev_read_simple_addr_cells(struct udevice *dev)
+{
+	return fdt_address_cells(gd->fdt_blob, dev_of_offset(dev));
+}
+
+static inline int dev_read_simple_size_cells(struct udevice *dev)
+{
+	return fdt_size_cells(gd->fdt_blob, dev_of_offset(dev));
+}
+
+static inline int dev_read_phandle(struct udevice *dev)
+{
+	return fdt_get_phandle(gd->fdt_blob, dev_of_offset(dev));
+}
+
+static inline const void *dev_read_prop(struct udevice *dev,
+					const char *propname, int *lenp)
+{
+	return ofnode_get_property(dev_ofnode(dev), propname, lenp);
+}
+
+static inline int dev_read_alias_seq(struct udevice *dev, int *devnump)
+{
+	return fdtdec_get_alias_seq(gd->fdt_blob, dev->uclass->uc_drv->name,
+				    dev_of_offset(dev), devnump);
+}
+
+static inline int dev_read_u32_array(struct udevice *dev, const char *propname,
+				     u32 *out_values, size_t sz)
+{
+	return ofnode_read_u32_array(dev_ofnode(dev), propname, out_values, sz);
+}
+
+static inline ofnode dev_read_first_subnode(struct udevice *dev)
+{
+	return ofnode_first_subnode(dev_ofnode(dev));
+}
+
+static inline ofnode dev_read_next_subnode(ofnode node)
+{
+	return ofnode_next_subnode(node);
+}
+
+static inline const uint8_t *dev_read_u8_array_ptr(struct udevice *dev,
+					const char *propname, size_t sz)
+{
+	return ofnode_read_u8_array_ptr(dev_ofnode(dev), propname, sz);
+}
+
+static inline int dev_read_enabled(struct udevice *dev)
+{
+	return fdtdec_get_is_enabled(gd->fdt_blob, dev_of_offset(dev));
+}
+
+static inline int dev_read_resource(struct udevice *dev, uint index,
+				    struct resource *res)
+{
+	return ofnode_read_resource(dev_ofnode(dev), index, res);
+}
+
+static inline int dev_read_resource_byname(struct udevice *dev,
+					   const char *name,
+					   struct resource *res)
+{
+	return ofnode_read_resource_byname(dev_ofnode(dev), name, res);
+}
+
+static inline u64 dev_translate_address(struct udevice *dev, const fdt32_t *in_addr)
+{
+	return ofnode_translate_address(dev_ofnode(dev), in_addr);
+}
+
+static inline u64 dev_translate_dma_address(struct udevice *dev, const fdt32_t *in_addr)
+{
+	return ofnode_translate_dma_address(dev_ofnode(dev), in_addr);
+}
+
+static inline int dev_read_alias_highest_id(const char *stem)
+{
+	return fdtdec_get_alias_highest_id(gd->fdt_blob, stem);
+}
+
+#endif /* CONFIG_DM_DEV_READ_INLINE */
+
+/**
+ * dev_for_each_subnode() - Helper function to iterate through subnodes
+ *
+ * This creates a for() loop which works through the subnodes in a device's
+ * device-tree node.
+ *
+ * @subnode: ofnode holding the current subnode
+ * @dev: device to use for interation (struct udevice *)
+ */
+#define dev_for_each_subnode(subnode, dev) \
+	for (subnode = dev_read_first_subnode(dev); \
+	     ofnode_valid(subnode); \
+	     subnode = ofnode_next_subnode(subnode))
+
+#endif
diff --git a/include/dm/root.h b/include/dm/root.h
new file mode 100644
index 0000000..c8d629b
--- /dev/null
+++ b/include/dm/root.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ */
+
+#ifndef _DM_ROOT_H_
+#define _DM_ROOT_H_
+
+struct udevice;
+
+/**
+ * dm_root() - Return pointer to the top of the driver tree
+ *
+ * This function returns pointer to the root node of the driver tree,
+ *
+ * @return pointer to root device, or NULL if not inited yet
+ */
+struct udevice *dm_root(void);
+
+struct global_data;
+/**
+ * dm_fixup_for_gd_move() - Handle global_data moving to a new place
+ *
+ * The uclass list is part of global_data. Due to the way lists work, moving
+ * the list will cause it to become invalid. This function fixes that up so
+ * that the uclass list will work correctly.
+ */
+void dm_fixup_for_gd_move(struct global_data *new_gd);
+
+/**
+ * dm_scan_platdata() - Scan all platform data and bind drivers
+ *
+ * This scans all available platdata and creates drivers for each
+ *
+ * @pre_reloc_only: If true, bind only drivers with the DM_FLAG_PRE_RELOC
+ * flag. If false bind all drivers.
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_platdata(bool pre_reloc_only);
+
+/**
+ * dm_scan_fdt() - Scan the device tree and bind drivers
+ *
+ * This scans the device tree and creates a driver for each node. Only
+ * the top-level subnodes are examined.
+ *
+ * @blob: Pointer to device tree blob
+ * @pre_reloc_only: If true, bind only nodes with special devicetree properties,
+ * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers.
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_fdt(const void *blob, bool pre_reloc_only);
+
+/**
+ * dm_extended_scan_fdt() - Scan the device tree and bind drivers
+ *
+ * This calls dm_scna_dft() which scans the device tree and creates a driver
+ * for each node. the top-level subnodes are examined and also all sub-nodes
+ * of "clocks" node.
+ *
+ * @blob: Pointer to device tree blob
+ * @pre_reloc_only: If true, bind only nodes with special devicetree properties,
+ * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers.
+ * @return 0 if OK, -ve on error
+ */
+int dm_extended_scan_fdt(const void *blob, bool pre_reloc_only);
+
+/**
+ * dm_scan_other() - Scan for other devices
+ *
+ * Some devices may not be visible to Driver Model. This weak function can
+ * be provided by boards which wish to create their own devices
+ * programmaticaly. They should do this by calling device_bind() on each
+ * device.
+ *
+ * @pre_reloc_only: If true, bind only nodes with special devicetree properties,
+ * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers.
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_other(bool pre_reloc_only);
+
+/**
+ * dm_init_and_scan() - Initialise Driver Model structures and scan for devices
+ *
+ * This function initialises the roots of the driver tree and uclass trees,
+ * then scans and binds available devices from platform data and the FDT.
+ * This calls dm_init() to set up Driver Model structures.
+ *
+ * @pre_reloc_only: If true, bind only nodes with special devicetree properties,
+ * or drivers with the DM_FLAG_PRE_RELOC flag. If false bind all drivers.
+ * @return 0 if OK, -ve on error
+ */
+int dm_init_and_scan(bool pre_reloc_only);
+
+/**
+ * dm_init() - Initialise Driver Model structures
+ *
+ * This function will initialize roots of driver tree and class tree.
+ * This needs to be called before anything uses the DM
+ *
+ * @of_live:	Enable live device tree
+ * @return 0 if OK, -ve on error
+ */
+int dm_init(bool of_live);
+
+/**
+ * dm_uninit - Uninitialise Driver Model structures
+ *
+ * All devices will be removed and unbound
+ * @return 0 if OK, -ve on error
+ */
+int dm_uninit(void);
+
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+/**
+ * dm_remove_devices_flags - Call remove function of all drivers with
+ *                           specific removal flags set to selectively
+ *                           remove drivers
+ *
+ * All devices with the matching flags set will be removed
+ *
+ * @flags: Flags for selective device removal
+ * @return 0 if OK, -ve on error
+ */
+int dm_remove_devices_flags(uint flags);
+#else
+static inline int dm_remove_devices_flags(uint flags) { return 0; }
+#endif
+
+#endif
diff --git a/include/dm/test.h b/include/dm/test.h
new file mode 100644
index 0000000..07385cd
--- /dev/null
+++ b/include/dm/test.h
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc.
+ */
+
+#ifndef __DM_TEST_H
+#define __DM_TEST_H
+
+#include <dm.h>
+#include <test/test.h>
+
+/**
+ * struct dm_test_cdata - configuration data for test instance
+ *
+ * @ping_add: Amonut to add each time we get a ping
+ * @base: Base address of this device
+ */
+struct dm_test_pdata {
+	int ping_add;
+	uint32_t base;
+};
+
+/**
+ * struct test_ops - Operations supported by the test device
+ *
+ * @ping: Ping operation
+ *	@dev: Device to operate on
+ *	@pingval: Value to ping the device with
+ *	@pingret: Returns resulting value from driver
+ *	@return 0 if OK, -ve on error
+ */
+struct test_ops {
+	int (*ping)(struct udevice *dev, int pingval, int *pingret);
+};
+
+/* Operations that our test driver supports */
+enum {
+	DM_TEST_OP_BIND = 0,
+	DM_TEST_OP_UNBIND,
+	DM_TEST_OP_PROBE,
+	DM_TEST_OP_REMOVE,
+
+	/* For uclass */
+	DM_TEST_OP_POST_BIND,
+	DM_TEST_OP_PRE_UNBIND,
+	DM_TEST_OP_PRE_PROBE,
+	DM_TEST_OP_POST_PROBE,
+	DM_TEST_OP_PRE_REMOVE,
+	DM_TEST_OP_INIT,
+	DM_TEST_OP_DESTROY,
+
+	DM_TEST_OP_COUNT,
+};
+
+/* Test driver types */
+enum {
+	DM_TEST_TYPE_FIRST = 0,
+	DM_TEST_TYPE_SECOND,
+};
+
+/* The number added to the ping total on each probe */
+#define DM_TEST_START_TOTAL	5
+
+/**
+ * struct dm_test_priv - private data for the test devices
+ */
+struct dm_test_priv {
+	int ping_total;
+	int op_count[DM_TEST_OP_COUNT];
+	int uclass_flag;
+	int uclass_total;
+	int uclass_postp;
+};
+
+/**
+ * struct dm_test_perdev_class_priv - private per-device data for test uclass
+ */
+struct dm_test_uclass_perdev_priv {
+	int base_add;
+};
+
+/**
+ * struct dm_test_uclass_priv - private data for test uclass
+ */
+struct dm_test_uclass_priv {
+	int total_add;
+};
+
+/**
+ * struct dm_test_parent_data - parent's information on each child
+ *
+ * @sum: Test value used to check parent data works correctly
+ * @flag: Used to track calling of parent operations
+ * @uclass_flag: Used to track calling of parent operations by uclass
+ */
+struct dm_test_parent_data {
+	int sum;
+	int flag;
+};
+
+/* Test values for test device's uclass platform data */
+enum {
+	TEST_UC_PDATA_INTVAL1 = 2,
+	TEST_UC_PDATA_INTVAL2 = 334,
+	TEST_UC_PDATA_INTVAL3 = 789452,
+};
+
+/**
+ * struct dm_test_uclass_platda - uclass's information on each device
+ *
+ * @intval1: set to TEST_UC_PDATA_INTVAL1 in .post_bind method of test uclass
+ * @intval2: set to TEST_UC_PDATA_INTVAL2 in .post_bind method of test uclass
+ * @intval3: set to TEST_UC_PDATA_INTVAL3 in .post_bind method of test uclass
+ */
+struct dm_test_perdev_uc_pdata {
+	int intval1;
+	int intval2;
+	int intval3;
+};
+
+/*
+ * Operation counts for the test driver, used to check that each method is
+ * called correctly
+ */
+extern int dm_testdrv_op_count[DM_TEST_OP_COUNT];
+
+extern struct unit_test_state global_dm_test_state;
+
+/*
+ * struct dm_test_state - Entire state of dm test system
+ *
+ * This is often abreviated to dms.
+ *
+ * @root: Root device
+ * @testdev: Test device
+ * @force_fail_alloc: Force all memory allocs to fail
+ * @skip_post_probe: Skip uclass post-probe processing
+ * @removed: Used to keep track of a device that was removed
+ */
+struct dm_test_state {
+	struct udevice *root;
+	struct udevice *testdev;
+	int force_fail_alloc;
+	int skip_post_probe;
+	struct udevice *removed;
+};
+
+/* Test flags for each test */
+enum {
+	DM_TESTF_SCAN_PDATA	= 1 << 0,	/* test needs platform data */
+	DM_TESTF_PROBE_TEST	= 1 << 1,	/* probe test uclass */
+	DM_TESTF_SCAN_FDT	= 1 << 2,	/* scan device tree */
+	DM_TESTF_FLAT_TREE	= 1 << 3,	/* test needs flat DT */
+	DM_TESTF_LIVE_TREE	= 1 << 4,	/* needs live device tree */
+};
+
+/* Declare a new driver model test */
+#define DM_TEST(_name, _flags)	UNIT_TEST(_name, _flags, dm_test)
+
+/* This platform data is needed in tests, so declare it here */
+struct sandbox_sdl_plat {
+	int xres;
+	int yres;
+	int bpix;
+	int rot;
+	const char *vidconsole_drv_name;
+	int font_size;
+};
+
+/* Declare ping methods for the drivers */
+int test_ping(struct udevice *dev, int pingval, int *pingret);
+int testfdt_ping(struct udevice *dev, int pingval, int *pingret);
+
+/**
+ * dm_check_operations() - Check that we can perform ping operations
+ *
+ * This checks that the ping operations work as expected for a device
+ *
+ * @dms: Overall test state
+ * @dev: Device to test
+ * @base: Base address, used to check ping return value
+ * @priv: Pointer to private test information
+ * @return 0 if OK, -ve on error
+ */
+int dm_check_operations(struct unit_test_state *uts, struct udevice *dev,
+			uint32_t base, struct dm_test_priv *priv);
+
+/**
+ * dm_check_devices() - check the devices respond to operations correctly
+ *
+ * @dms: Overall test state
+ * @num_devices: Number of test devices to check
+ * @return 0 if OK, -ve on error
+ */
+int dm_check_devices(struct unit_test_state *uts, int num_devices);
+
+/**
+ * dm_leak_check_start() - Prepare to check for a memory leak
+ *
+ * Call this before allocating memory to record the amount of memory being
+ * used.
+ *
+ * @dms: Overall test state
+ */
+void dm_leak_check_start(struct unit_test_state *uts);
+
+/**
+ * dm_leak_check_end() - Check that no memory has leaked
+ *
+ * Call this after dm_leak_check_start() and after you have hopefuilly freed
+ * all the memory that was allocated. This function will print an error if
+ * it sees a different amount of total memory allocated than before.
+ *
+ * @dms: Overall test state
+ */int dm_leak_check_end(struct unit_test_state *uts);
+
+#endif
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
new file mode 100644
index 0000000..0c563d8
--- /dev/null
+++ b/include/dm/uclass-id.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ */
+
+#ifndef _DM_UCLASS_ID_H
+#define _DM_UCLASS_ID_H
+
+/* TODO(sjg@chromium.org): this could be compile-time generated */
+enum uclass_id {
+	/* These are used internally by driver model */
+	UCLASS_ROOT = 0,
+	UCLASS_DEMO,
+	UCLASS_TEST,
+	UCLASS_TEST_FDT,
+	UCLASS_TEST_BUS,
+	UCLASS_TEST_PROBE,
+	UCLASS_TEST_DUMMY,
+	UCLASS_SPI_EMUL,	/* sandbox SPI device emulator */
+	UCLASS_I2C_EMUL,	/* sandbox I2C device emulator */
+	UCLASS_I2C_EMUL_PARENT,	/* parent for I2C device emulators */
+	UCLASS_PCI_EMUL,	/* sandbox PCI device emulator */
+	UCLASS_PCI_EMUL_PARENT,	/* parent for PCI device emulators */
+	UCLASS_USB_EMUL,	/* sandbox USB bus device emulator */
+	UCLASS_AXI_EMUL,	/* sandbox AXI bus device emulator */
+
+	/* U-Boot uclasses start here - in alphabetical order */
+	UCLASS_ADC,		/* Analog-to-digital converter */
+	UCLASS_AHCI,		/* SATA disk controller */
+	UCLASS_AUDIO_CODEC,	/* Audio codec with control and data path */
+	UCLASS_AXI,		/* AXI bus */
+	UCLASS_BLK,		/* Block device */
+	UCLASS_BOARD,		/* Device information from hardware */
+	UCLASS_BOOTCOUNT,       /* Bootcount backing store */
+	UCLASS_CACHE,		/* Cache controller */
+	UCLASS_CLK,		/* Clock source, e.g. used by peripherals */
+	UCLASS_CPU,		/* CPU, typically part of an SoC */
+	UCLASS_CROS_EC,		/* Chrome OS EC */
+	UCLASS_DISPLAY,		/* Display (e.g. DisplayPort, HDMI) */
+	UCLASS_DSI_HOST,	/* Display Serial Interface host */
+	UCLASS_DMA,		/* Direct Memory Access */
+	UCLASS_EFI,		/* EFI managed devices */
+	UCLASS_ETH,		/* Ethernet device */
+	UCLASS_FIRMWARE,	/* Firmware */
+	UCLASS_FS_FIRMWARE_LOADER,		/* Generic loader */
+	UCLASS_GPIO,		/* Bank of general-purpose I/O pins */
+	UCLASS_HWSPINLOCK,	/* Hardware semaphores */
+	UCLASS_I2C,		/* I2C bus */
+	UCLASS_I2C_EEPROM,	/* I2C EEPROM device */
+	UCLASS_I2C_GENERIC,	/* Generic I2C device */
+	UCLASS_I2C_MUX,		/* I2C multiplexer */
+	UCLASS_I2S,		/* I2S bus */
+	UCLASS_IDE,		/* IDE device */
+	UCLASS_IRQ,		/* Interrupt controller */
+	UCLASS_KEYBOARD,	/* Keyboard input device */
+	UCLASS_LED,		/* Light-emitting diode (LED) */
+	UCLASS_LPC,		/* x86 'low pin count' interface */
+	UCLASS_MAILBOX,		/* Mailbox controller */
+	UCLASS_MASS_STORAGE,	/* Mass storage device */
+	UCLASS_MDIO,		/* MDIO bus */
+	UCLASS_MDIO_MUX,	/* MDIO MUX/switch */
+	UCLASS_MISC,		/* Miscellaneous device */
+	UCLASS_MMC,		/* SD / MMC card or chip */
+	UCLASS_MOD_EXP,		/* RSA Mod Exp device */
+	UCLASS_MTD,		/* Memory Technology Device (MTD) device */
+	UCLASS_NOP,		/* No-op devices */
+	UCLASS_NORTHBRIDGE,	/* Intel Northbridge / SDRAM controller */
+	UCLASS_NVME,		/* NVM Express device */
+	UCLASS_PANEL,		/* Display panel, such as an LCD */
+	UCLASS_PANEL_BACKLIGHT,	/* Backlight controller for panel */
+	UCLASS_PCH,		/* x86 platform controller hub */
+	UCLASS_PCI,		/* PCI bus */
+	UCLASS_PCI_EP,		/* PCI endpoint device */
+	UCLASS_PCI_GENERIC,	/* Generic PCI bus device */
+	UCLASS_PHY,		/* Physical Layer (PHY) device */
+	UCLASS_PINCONFIG,	/* Pin configuration node device */
+	UCLASS_PINCTRL,		/* Pinctrl (pin muxing/configuration) device */
+	UCLASS_PMIC,		/* PMIC I/O device */
+	UCLASS_POWER_DOMAIN,	/* (SoC) Power domains */
+	UCLASS_PWM,		/* Pulse-width modulator */
+	UCLASS_PWRSEQ,		/* Power sequence device */
+	UCLASS_RAM,		/* RAM controller */
+	UCLASS_REGULATOR,	/* Regulator device */
+	UCLASS_REMOTEPROC,	/* Remote Processor device */
+	UCLASS_RESET,		/* Reset controller device */
+	UCLASS_RTC,		/* Real time clock device */
+	UCLASS_SCSI,		/* SCSI device */
+	UCLASS_SERIAL,		/* Serial UART */
+	UCLASS_SIMPLE_BUS,	/* Bus with child devices */
+	UCLASS_SMEM,		/* Shared memory interface */
+	UCLASS_SOUND,		/* Playing simple sounds */
+	UCLASS_SPI,		/* SPI bus */
+	UCLASS_SPI_FLASH,	/* SPI flash */
+	UCLASS_SPI_GENERIC,	/* Generic SPI flash target */
+	UCLASS_SPMI,		/* System Power Management Interface bus */
+	UCLASS_SYSCON,		/* System configuration device */
+	UCLASS_SYSRESET,	/* System reset device */
+	UCLASS_TEE,		/* Trusted Execution Environment device */
+	UCLASS_THERMAL,		/* Thermal sensor */
+	UCLASS_TIMER,		/* Timer device */
+	UCLASS_TPM,		/* Trusted Platform Module TIS interface */
+	UCLASS_UFS,		/* Universal Flash Storage */
+	UCLASS_USB,		/* USB bus */
+	UCLASS_USB_DEV_GENERIC,	/* USB generic device */
+	UCLASS_USB_HUB,		/* USB hub */
+	UCLASS_USB_GADGET_GENERIC,	/* USB generic device */
+	UCLASS_VIDEO,		/* Video or LCD device */
+	UCLASS_VIDEO_BRIDGE,	/* Video bridge, e.g. DisplayPort to LVDS */
+	UCLASS_VIDEO_CONSOLE,	/* Text console driver for video device */
+	UCLASS_VIDEO_OSD,	/* On-screen display */
+	UCLASS_VIRTIO,		/* VirtIO transport device */
+	UCLASS_W1,		/* Dallas 1-Wire bus */
+	UCLASS_W1_EEPROM,	/* one-wire EEPROMs */
+	UCLASS_WDT,		/* Watchdog Timer driver */
+
+	UCLASS_COUNT,
+	UCLASS_INVALID = -1,
+};
+
+#endif
diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h
new file mode 100644
index 0000000..6e3f15c
--- /dev/null
+++ b/include/dm/uclass-internal.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ */
+
+#ifndef _DM_UCLASS_INTERNAL_H
+#define _DM_UCLASS_INTERNAL_H
+
+#include <dm/ofnode.h>
+
+/**
+ * uclass_find_next_free_req_seq() - Get the next free req_seq number
+ *
+ * This returns the next free req_seq number. This is useful only if
+ * OF_CONTROL is not used. The next free req_seq number is simply the
+ * maximum req_seq of the uclass + 1.
+ * This allows assiging req_seq number in the binding order.
+ *
+ * @id:		Id number of the uclass
+ * @return	The next free req_seq number
+ */
+int uclass_find_next_free_req_seq(enum uclass_id id);
+
+/**
+ * uclass_get_device_tail() - handle the end of a get_device call
+ *
+ * This handles returning an error or probing a device as needed.
+ *
+ * @dev: Device that needs to be probed
+ * @ret: Error to return. If non-zero then the device is not probed
+ * @devp: Returns the value of 'dev' if there is no error
+ * @return ret, if non-zero, else the result of the device_probe() call
+ */
+int uclass_get_device_tail(struct udevice *dev, int ret, struct udevice **devp);
+
+/**
+ * dev_get_uclass_index() - Get uclass and index of device
+ * @dev:	- in - Device that we want the uclass/index of
+ * @ucp:	- out - A pointer to the uclass the device belongs to
+ *
+ * The device is not prepared for use - this is an internal function.
+ *
+ * @return the index of the device in the uclass list or -ENODEV if not found.
+ */
+int dev_get_uclass_index(struct udevice *dev, struct uclass **ucp);
+
+/**
+ * uclass_find_device() - Return n-th child of uclass
+ * @id:		Id number of the uclass
+ * @index:	Position of the child in uclass's list
+ * #devp:	Returns pointer to device, or NULL on error
+ *
+ * The device is not prepared for use - this is an internal function.
+ * The function uclass_get_device_tail() can be used to probe the device.
+ *
+ * @return the uclass pointer of a child at the given index or
+ * return NULL on error.
+ */
+int uclass_find_device(enum uclass_id id, int index, struct udevice **devp);
+
+/**
+ * uclass_find_first_device() - Return the first device in a uclass
+ * @id:		Id number of the uclass
+ * #devp:	Returns pointer to device, or NULL on error
+ *
+ * The device is not prepared for use - this is an internal function.
+ * The function uclass_get_device_tail() can be used to probe the device.
+ *
+ * @return 0 if OK (found or not found), -ve on error
+ */
+int uclass_find_first_device(enum uclass_id id, struct udevice **devp);
+
+/**
+ * uclass_find_next_device() - Return the next device in a uclass
+ * @devp: On entry, pointer to device to lookup. On exit, returns pointer
+ * to the next device in the same uclass, or NULL if none
+ *
+ * The device is not prepared for use - this is an internal function.
+ * The function uclass_get_device_tail() can be used to probe the device.
+ *
+ * @return 0 if OK (found or not found), -ve on error
+ */
+int uclass_find_next_device(struct udevice **devp);
+
+/**
+ * uclass_find_device_by_name() - Find uclass device based on ID and name
+ *
+ * This searches for a device with the exactly given name.
+ *
+ * The device is NOT probed, it is merely returned.
+ *
+ * @id: ID to look up
+ * @name: name of a device to find
+ * @devp: Returns pointer to device (the first one with the name)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_find_device_by_name(enum uclass_id id, const char *name,
+			       struct udevice **devp);
+
+/**
+ * uclass_find_device_by_seq() - Find uclass device based on ID and sequence
+ *
+ * This searches for a device with the given seq or req_seq.
+ *
+ * For seq, if an active device has this sequence it will be returned.
+ * If there is no such device then this will return -ENODEV.
+ *
+ * For req_seq, if a device (whether activated or not) has this req_seq
+ * value, that device will be returned. This is a strong indication that
+ * the device will receive that sequence when activated.
+ *
+ * The device is NOT probed, it is merely returned.
+ *
+ * @id: ID to look up
+ * @seq_or_req_seq: Sequence number to find (0=first)
+ * @find_req_seq: true to find req_seq, false to find seq
+ * @devp: Returns pointer to device (there is only one per for each seq)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_find_device_by_seq(enum uclass_id id, int seq_or_req_seq,
+			      bool find_req_seq, struct udevice **devp);
+
+/**
+ * uclass_find_device_by_of_offset() - Find a uclass device by device tree node
+ *
+ * This searches the devices in the uclass for one attached to the given
+ * device tree node.
+ *
+ * The device is NOT probed, it is merely returned.
+ *
+ * @id: ID to look up
+ * @node: Device tree offset to search for (if -ve then -ENODEV is returned)
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_find_device_by_of_offset(enum uclass_id id, int node,
+				    struct udevice **devp);
+
+/**
+ * uclass_find_device_by_of_node() - Find a uclass device by device tree node
+ *
+ * This searches the devices in the uclass for one attached to the given
+ * device tree node.
+ *
+ * The device is NOT probed, it is merely returned.
+ *
+ * @id: ID to look up
+ * @node: Device tree offset to search for (if NULL then -ENODEV is returned)
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_find_device_by_ofnode(enum uclass_id id, ofnode node,
+				 struct udevice **devp);
+
+/**
+ * uclass_find_device_by_phandle() - Find a uclass device by phandle
+ *
+ * This searches the devices in the uclass for one with the given phandle.
+ *
+ * The device is NOT probed, it is merely returned.
+ *
+ * @id: ID to look up
+ * @parent: Parent device containing the phandle pointer
+ * @name: Name of property in the parent device node
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ENOENT if there is no @name present in the node, other
+ *	-ve on error
+ */
+int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent,
+				  const char *name, struct udevice **devp);
+
+/**
+ * uclass_bind_device() - Associate device with a uclass
+ *
+ * Connect the device into uclass's list of devices.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_bind_device(struct udevice *dev);
+
+/**
+ * uclass_unbind_device() - Deassociate device with a uclass
+ *
+ * Disconnect the device from uclass's list of devices.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+int uclass_unbind_device(struct udevice *dev);
+#else
+static inline int uclass_unbind_device(struct udevice *dev) { return 0; }
+#endif
+
+/**
+ * uclass_pre_probe_device() - Deal with a device that is about to be probed
+ *
+ * Perform any pre-processing that is needed by the uclass before it can be
+ * probed. This includes the uclass' pre-probe() method and the parent
+ * uclass' child_pre_probe() method.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_pre_probe_device(struct udevice *dev);
+
+/**
+ * uclass_post_probe_device() - Deal with a device that has just been probed
+ *
+ * Perform any post-processing of a probed device that is needed by the
+ * uclass.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_post_probe_device(struct udevice *dev);
+
+/**
+ * uclass_pre_remove_device() - Handle a device which is about to be removed
+ *
+ * Perform any pre-processing of a device that is about to be removed.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+#if CONFIG_IS_ENABLED(DM_DEVICE_REMOVE)
+int uclass_pre_remove_device(struct udevice *dev);
+#else
+static inline int uclass_pre_remove_device(struct udevice *dev) { return 0; }
+#endif
+
+/**
+ * uclass_find() - Find uclass by its id
+ *
+ * @id:		Id to serach for
+ * @return pointer to uclass, or NULL if not found
+ */
+struct uclass *uclass_find(enum uclass_id key);
+
+/**
+ * uclass_destroy() - Destroy a uclass
+ *
+ * Destroy a uclass and all its devices
+ *
+ * @uc: uclass to destroy
+ * @return 0 on success, -ve on error
+ */
+int uclass_destroy(struct uclass *uc);
+
+#endif
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
new file mode 100644
index 0000000..484d166
--- /dev/null
+++ b/include/dm/uclass.h
@@ -0,0 +1,412 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ */
+
+#ifndef _DM_UCLASS_H
+#define _DM_UCLASS_H
+
+#include <dm/ofnode.h>
+#include <dm/uclass-id.h>
+#include <linker_lists.h>
+#include <linux/list.h>
+
+/**
+ * struct uclass - a U-Boot drive class, collecting together similar drivers
+ *
+ * A uclass provides an interface to a particular function, which is
+ * implemented by one or more drivers. Every driver belongs to a uclass even
+ * if it is the only driver in that uclass. An example uclass is GPIO, which
+ * provides the ability to change read inputs, set and clear outputs, etc.
+ * There may be drivers for on-chip SoC GPIO banks, I2C GPIO expanders and
+ * PMIC IO lines, all made available in a unified way through the uclass.
+ *
+ * @priv: Private data for this uclass
+ * @uc_drv: The driver for the uclass itself, not to be confused with a
+ * 'struct driver'
+ * @dev_head: List of devices in this uclass (devices are attached to their
+ * uclass when their bind method is called)
+ * @sibling_node: Next uclass in the linked list of uclasses
+ */
+struct uclass {
+	void *priv;
+	struct uclass_driver *uc_drv;
+	struct list_head dev_head;
+	struct list_head sibling_node;
+};
+
+struct driver;
+struct udevice;
+
+/* Members of this uclass sequence themselves with aliases */
+#define DM_UC_FLAG_SEQ_ALIAS			(1 << 0)
+
+/* Same as DM_FLAG_ALLOC_PRIV_DMA */
+#define DM_UC_FLAG_ALLOC_PRIV_DMA		(1 << 5)
+
+/**
+ * struct uclass_driver - Driver for the uclass
+ *
+ * A uclass_driver provides a consistent interface to a set of related
+ * drivers.
+ *
+ * @name: Name of uclass driver
+ * @id: ID number of this uclass
+ * @post_bind: Called after a new device is bound to this uclass
+ * @pre_unbind: Called before a device is unbound from this uclass
+ * @pre_probe: Called before a new device is probed
+ * @post_probe: Called after a new device is probed
+ * @pre_remove: Called before a device is removed
+ * @child_post_bind: Called after a child is bound to a device in this uclass
+ * @child_pre_probe: Called before a child in this uclass is probed
+ * @child_post_probe: Called after a child in this uclass is probed
+ * @init: Called to set up the uclass
+ * @destroy: Called to destroy the uclass
+ * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * to be allocated in the uclass's ->priv pointer. If zero, then the uclass
+ * driver is responsible for allocating any data required.
+ * @per_device_auto_alloc_size: Each device can hold private data owned
+ * by the uclass. If required this will be automatically allocated if this
+ * value is non-zero.
+ * @per_device_platdata_auto_alloc_size: Each device can hold platform data
+ * owned by the uclass as 'dev->uclass_platdata'. If the value is non-zero,
+ * then this will be automatically allocated.
+ * @per_child_auto_alloc_size: Each child device (of a parent in this
+ * uclass) can hold parent data for the device/uclass. This value is only
+ * used as a fallback if this member is 0 in the driver.
+ * @per_child_platdata_auto_alloc_size: A bus likes to store information about
+ * its children. If non-zero this is the size of this data, to be allocated
+ * in the child device's parent_platdata pointer. This value is only used as
+ * a fallback if this member is 0 in the driver.
+ * @ops: Uclass operations, providing the consistent interface to devices
+ * within the uclass.
+ * @flags: Flags for this uclass (DM_UC_...)
+ */
+struct uclass_driver {
+	const char *name;
+	enum uclass_id id;
+	int (*post_bind)(struct udevice *dev);
+	int (*pre_unbind)(struct udevice *dev);
+	int (*pre_probe)(struct udevice *dev);
+	int (*post_probe)(struct udevice *dev);
+	int (*pre_remove)(struct udevice *dev);
+	int (*child_post_bind)(struct udevice *dev);
+	int (*child_pre_probe)(struct udevice *dev);
+	int (*child_post_probe)(struct udevice *dev);
+	int (*init)(struct uclass *class);
+	int (*destroy)(struct uclass *class);
+	int priv_auto_alloc_size;
+	int per_device_auto_alloc_size;
+	int per_device_platdata_auto_alloc_size;
+	int per_child_auto_alloc_size;
+	int per_child_platdata_auto_alloc_size;
+	const void *ops;
+	uint32_t flags;
+};
+
+/* Declare a new uclass_driver */
+#define UCLASS_DRIVER(__name)						\
+	ll_entry_declare(struct uclass_driver, __name, uclass)
+
+/**
+ * uclass_get() - Get a uclass based on an ID, creating it if needed
+ *
+ * Every uclass is identified by an ID, a number from 0 to n-1 where n is
+ * the number of uclasses. This function allows looking up a uclass by its
+ * ID.
+ *
+ * @key: ID to look up
+ * @ucp: Returns pointer to uclass (there is only one per ID)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get(enum uclass_id key, struct uclass **ucp);
+
+/**
+ * uclass_get_name() - Get the name of a uclass driver
+ *
+ * @id: ID to look up
+ * @returns the name of the uclass driver for that ID, or NULL if none
+ */
+const char *uclass_get_name(enum uclass_id id);
+
+/**
+ * uclass_get_by_name() - Look up a uclass by its driver name
+ *
+ * @name: Name to look up
+ * @returns the associated uclass ID, or UCLASS_INVALID if not found
+ */
+enum uclass_id uclass_get_by_name(const char *name);
+
+/**
+ * uclass_get_device() - Get a uclass device based on an ID and index
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @index: Device number within that uclass (0=first)
+ * @devp: Returns pointer to device (there is only one per for each ID)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device(enum uclass_id id, int index, struct udevice **devp);
+
+/**
+ * uclass_get_device_by_name() - Get a uclass device by its name
+ *
+ * This searches the devices in the uclass for one with the exactly given name.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @name: name of a device to get
+ * @devp: Returns pointer to device (the first one with the name)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device_by_name(enum uclass_id id, const char *name,
+			      struct udevice **devp);
+
+/**
+ * uclass_get_device_by_seq() - Get a uclass device based on an ID and sequence
+ *
+ * If an active device has this sequence it will be returned. If there is no
+ * such device then this will check for a device that is requesting this
+ * sequence.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @seq: Sequence number to find (0=first)
+ * @devp: Returns pointer to device (there is only one for each seq)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device_by_seq(enum uclass_id id, int seq, struct udevice **devp);
+
+/**
+ * uclass_get_device_by_of_offset() - Get a uclass device by device tree node
+ *
+ * This searches the devices in the uclass for one attached to the given
+ * device tree node.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @node: Device tree offset to search for (if -ve then -ENODEV is returned)
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device_by_of_offset(enum uclass_id id, int node,
+				   struct udevice **devp);
+
+/**
+ * uclass_get_device_by_ofnode() - Get a uclass device by device tree node
+ *
+ * This searches the devices in the uclass for one attached to the given
+ * device tree node.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @np: Device tree node to search for (if NULL then -ENODEV is returned)
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device_by_ofnode(enum uclass_id id, ofnode node,
+				struct udevice **devp);
+
+/**
+ * uclass_get_device_by_phandle_id() - Get a uclass device by phandle id
+ *
+ * This searches the devices in the uclass for one with the given phandle id.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: uclass ID to look up
+ * @phandle_id: the phandle id to look up
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ENODEV if there is no device match the phandle, other
+ *	-ve on error
+ */
+int uclass_get_device_by_phandle_id(enum uclass_id id, uint phandle_id,
+				    struct udevice **devp);
+
+/**
+ * uclass_get_device_by_phandle() - Get a uclass device by phandle
+ *
+ * This searches the devices in the uclass for one with the given phandle.
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: uclass ID to look up
+ * @parent: Parent device containing the phandle pointer
+ * @name: Name of property in the parent device node
+ * @devp: Returns pointer to device (there is only one for each node)
+ * @return 0 if OK, -ENOENT if there is no @name present in the node, other
+ *	-ve on error
+ */
+int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent,
+				 const char *name, struct udevice **devp);
+
+/**
+ * uclass_get_device_by_driver() - Get a uclass device for a driver
+ *
+ * This searches the devices in the uclass for one that uses the given
+ * driver. Use DM_GET_DRIVER(name) for the @drv argument, where 'name' is
+ * the driver name - as used in U_BOOT_DRIVER(name).
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @drv: Driver to look for
+ * @devp: Returns pointer to the first device with that driver
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device_by_driver(enum uclass_id id, const struct driver *drv,
+				struct udevice **devp);
+
+/**
+ * uclass_first_device() - Get the first device in a uclass
+ *
+ * The device returned is probed if necessary, and ready for use
+ *
+ * This function is useful to start iterating through a list of devices which
+ * are functioning correctly and can be probed.
+ *
+ * @id: Uclass ID to look up
+ * @devp: Returns pointer to the first device in that uclass if no error
+ * occurred, or NULL if there is no first device, or an error occurred with
+ * that device.
+ * @return 0 if OK (found or not found), other -ve on error
+ */
+int uclass_first_device(enum uclass_id id, struct udevice **devp);
+
+/**
+ * uclass_first_device_err() - Get the first device in a uclass
+ *
+ * The device returned is probed if necessary, and ready for use
+ *
+ * @id: Uclass ID to look up
+ * @devp: Returns pointer to the first device in that uclass, or NULL if none
+ * @return 0 if found, -ENODEV if not found, other -ve on error
+ */
+int uclass_first_device_err(enum uclass_id id, struct udevice **devp);
+
+/**
+ * uclass_next_device() - Get the next device in a uclass
+ *
+ * The device returned is probed if necessary, and ready for use
+ *
+ * This function is useful to iterate through a list of devices which
+ * are functioning correctly and can be probed.
+ *
+ * @devp: On entry, pointer to device to lookup. On exit, returns pointer
+ * to the next device in the uclass if no error occurred, or NULL if there is
+ * no next device, or an error occurred with that next device.
+ * @return 0 if OK (found or not found), other -ve on error
+ */
+int uclass_next_device(struct udevice **devp);
+
+/**
+ * uclass_next_device_err() - Get the next device in a uclass
+ *
+ * The device returned is probed if necessary, and ready for use
+ *
+ * @devp: On entry, pointer to device to lookup. On exit, returns pointer
+ * to the next device in the uclass if no error occurred, or -ENODEV if
+ * there is no next device.
+ * @return 0 if found, -ENODEV if not found, other -ve on error
+ */
+int uclass_next_device_err(struct udevice **devp);
+
+/**
+ * uclass_first_device_check() - Get the first device in a uclass
+ *
+ * The device returned is probed if necessary, and ready for use
+ *
+ * This function is useful to start iterating through a list of devices which
+ * are functioning correctly and can be probed.
+ *
+ * @id: Uclass ID to look up
+ * @devp: Returns pointer to the first device in that uclass, or NULL if there
+ * is no first device
+ * @return 0 if OK (found or not found), other -ve on error. If an error occurs
+ * it is still possible to move to the next device.
+ */
+int uclass_first_device_check(enum uclass_id id, struct udevice **devp);
+
+/**
+ * uclass_next_device_check() - Get the next device in a uclass
+ *
+ * The device returned is probed if necessary, and ready for use
+ *
+ * This function is useful to start iterating through a list of devices which
+ * are functioning correctly and can be probed.
+ *
+ * @devp: On entry, pointer to device to lookup. On exit, returns pointer
+ * to the next device in the uclass if any
+ * @return 0 if OK (found or not found), other -ve on error. If an error occurs
+ * it is still possible to move to the next device.
+ */
+int uclass_next_device_check(struct udevice **devp);
+
+/**
+ * uclass_resolve_seq() - Resolve a device's sequence number
+ *
+ * On entry dev->seq is -1, and dev->req_seq may be -1 (to allocate a
+ * sequence number automatically, or >= 0 to select a particular number.
+ * If the requested sequence number is in use, then this device will
+ * be allocated another one.
+ *
+ * Note that the device's seq value is not changed by this function.
+ *
+ * @dev: Device for which to allocate sequence number
+ * @return sequence number allocated, or -ve on error
+ */
+int uclass_resolve_seq(struct udevice *dev);
+
+/**
+ * uclass_foreach_dev() - Helper function to iteration through devices
+ *
+ * This creates a for() loop which works through the available devices in
+ * a uclass in order from start to end.
+ *
+ * @pos: struct udevice * to hold the current device. Set to NULL when there
+ * are no more devices.
+ * @uc: uclass to scan
+ */
+#define uclass_foreach_dev(pos, uc)	\
+	list_for_each_entry(pos, &uc->dev_head, uclass_node)
+
+/**
+ * uclass_foreach_dev_safe() - Helper function to safely iteration through devs
+ *
+ * This creates a for() loop which works through the available devices in
+ * a uclass in order from start to end. Inside the loop, it is safe to remove
+ * @pos if required.
+ *
+ * @pos: struct udevice * to hold the current device. Set to NULL when there
+ * are no more devices.
+ * @next: struct udevice * to hold the next next
+ * @uc: uclass to scan
+ */
+#define uclass_foreach_dev_safe(pos, next, uc)	\
+	list_for_each_entry_safe(pos, next, &uc->dev_head, uclass_node)
+
+/**
+ * uclass_foreach_dev_probe() - Helper function to iteration through devices
+ * of given uclass
+ *
+ * This creates a for() loop which works through the available devices in
+ * a uclass in order from start to end. Devices are probed if necessary,
+ * and ready for use.
+ *
+ * @id: Uclass ID
+ * @dev: struct udevice * to hold the current device. Set to NULL when there
+ * are no more devices.
+ */
+#define uclass_foreach_dev_probe(id, dev)	\
+	for (int _ret = uclass_first_device_err(id, &dev); !_ret && dev; \
+	     _ret = uclass_next_device_err(&dev))
+
+#endif
diff --git a/include/dm/util.h b/include/dm/util.h
new file mode 100644
index 0000000..348c2ac
--- /dev/null
+++ b/include/dm/util.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ */
+
+#ifndef __DM_UTIL_H
+#define __DM_UTIL_H
+
+#ifdef CONFIG_DM_WARN
+void dm_warn(const char *fmt, ...);
+#else
+static inline void dm_warn(const char *fmt, ...)
+{
+}
+#endif
+
+struct list_head;
+
+/**
+ * list_count_items() - Count number of items in a list
+ *
+ * @param head:		Head of list
+ * @return number of items, or 0 if empty
+ */
+int list_count_items(struct list_head *head);
+
+/* Dump out a tree of all devices */
+void dm_dump_all(void);
+
+/* Dump out a list of uclasses and their devices */
+void dm_dump_uclass(void);
+
+#ifdef CONFIG_DEBUG_DEVRES
+/* Dump out a list of device resources */
+void dm_dump_devres(void);
+#else
+static inline void dm_dump_devres(void)
+{
+}
+#endif
+
+/**
+ * Check if an of node should be or was bound before relocation.
+ *
+ * Devicetree nodes can be marked as needed to be bound
+ * in the loader stages via special devicetree properties.
+ *
+ * Before relocation this function can be used to check if nodes
+ * are required in either SPL or TPL stages.
+ *
+ * After relocation and jumping into the real U-Boot binary
+ * it is possible to determine if a node was bound in one of
+ * SPL/TPL stages.
+ *
+ * There are 4 settings currently in use
+ * - u-boot,dm-pre-proper: U-Boot proper pre-relocation only
+ * - u-boot,dm-pre-reloc: legacy and indicates any of TPL or SPL
+ *   Existing platforms only use it to indicate nodes needed in
+ *   SPL. Should probably be replaced by u-boot,dm-spl for
+ *   existing platforms.
+ * - u-boot,dm-spl: SPL and U-Boot pre-relocation
+ * - u-boot,dm-tpl: TPL and U-Boot pre-relocation
+ * @node: of node
+ *
+ * Returns true if node is needed in SPL/TL, false otherwise.
+ */
+bool dm_ofnode_pre_reloc(ofnode node);
+
+#endif
diff --git a/include/dm9000.h b/include/dm9000.h
new file mode 100644
index 0000000..f780e51
--- /dev/null
+++ b/include/dm9000.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * NOTE:        DAVICOM DM9000 ethernet driver interface
+ *
+ * Authors:     Remy Bohmer <linux@bohmer.net>
+ */
+#ifndef __DM9000_H__
+#define __DM9000_H__
+
+/******************  function prototypes **********************/
+#if !defined(CONFIG_DM9000_NO_SROM)
+void dm9000_write_srom_word(int offset, u16 val);
+void dm9000_read_srom_word(int offset, u8 *to);
+#endif
+
+#endif /* __DM9000_H__ */
diff --git a/include/dma-uclass.h b/include/dma-uclass.h
new file mode 100644
index 0000000..31b43fb
--- /dev/null
+++ b/include/dma-uclass.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2015 - 2018 Texas Instruments Incorporated <www.ti.com>
+ * Written by Mugunthan V N <mugunthanvnm@ti.com>
+ *
+ */
+
+#ifndef _DMA_UCLASS_H
+#define _DMA_UCLASS_H
+
+/* See dma.h for background documentation. */
+
+#include <dma.h>
+
+struct ofnode_phandle_args;
+
+/*
+ * struct dma_ops - Driver model DMA operations
+ *
+ * The uclass interface is implemented by all DMA devices which use
+ * driver model.
+ */
+struct dma_ops {
+#ifdef CONFIG_DMA_CHANNELS
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) DMA specifier.
+	 *
+	 * The DMA core calls this function as the first step in implementing
+	 * a client's dma_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the DMA core will use a
+	 * default implementation, which assumes #dma-cells = <1>, and that
+	 * the DT cell contains a simple integer DMA Channel.
+	 *
+	 * At present, the DMA API solely supports device-tree. If this
+	 * changes, other xxx_xlate() functions may be added to support those
+	 * other mechanisms.
+	 *
+	 * @dma: The dma struct to hold the translation result.
+	 * @args:	The dma specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct dma *dma,
+			struct ofnode_phandle_args *args);
+	/**
+	 * request - Request a translated DMA.
+	 *
+	 * The DMA core calls this function as the second step in
+	 * implementing a client's dma_get_by_*() call, following a successful
+	 * xxx_xlate() call, or as the only step in implementing a client's
+	 * dma_request() call.
+	 *
+	 * @dma: The DMA struct to request; this has been filled in by
+	 *   a previoux xxx_xlate() function call, or by the caller of
+	 *   dma_request().
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct dma *dma);
+	/**
+	 * free - Free a previously requested dma.
+	 *
+	 * This is the implementation of the client dma_free() API.
+	 *
+	 * @dma: The DMA to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct dma *dma);
+	/**
+	 * enable() - Enable a DMA Channel.
+	 *
+	 * @dma: The DMA Channel to manipulate.
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*enable)(struct dma *dma);
+	/**
+	 * disable() - Disable a DMA Channel.
+	 *
+	 * @dma: The DMA Channel to manipulate.
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*disable)(struct dma *dma);
+	/**
+	 * prepare_rcv_buf() - Prepare/Add receive DMA buffer.
+	 *
+	 * @dma: The DMA Channel to manipulate.
+	 * @dst: The receive buffer pointer.
+	 * @size: The receive buffer size
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*prepare_rcv_buf)(struct dma *dma, void *dst, size_t size);
+	/**
+	 * receive() - Receive a DMA transfer.
+	 *
+	 * @dma: The DMA Channel to manipulate.
+	 * @dst: The destination pointer.
+	 * @metadata: DMA driver's specific data
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*receive)(struct dma *dma, void **dst, void *metadata);
+	/**
+	 * send() - Send a DMA transfer.
+	 *
+	 * @dma: The DMA Channel to manipulate.
+	 * @src: The source pointer.
+	 * @len: Length of the data to be sent (number of bytes).
+	 * @metadata: DMA driver's specific data
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*send)(struct dma *dma, void *src, size_t len, void *metadata);
+#endif /* CONFIG_DMA_CHANNELS */
+	/**
+	 * transfer() - Issue a DMA transfer. The implementation must
+	 *   wait until the transfer is done.
+	 *
+	 * @dev: The DMA device
+	 * @direction: direction of data transfer (should be one from
+	 *   enum dma_direction)
+	 * @dst: The destination pointer.
+	 * @src: The source pointer.
+	 * @len: Length of the data to be copied (number of bytes).
+	 * @return zero on success, or -ve error code.
+	 */
+	int (*transfer)(struct udevice *dev, int direction, void *dst,
+			void *src, size_t len);
+};
+
+#endif /* _DMA_UCLASS_H */
diff --git a/include/dma.h b/include/dma.h
new file mode 100644
index 0000000..d1c3d0d
--- /dev/null
+++ b/include/dma.h
@@ -0,0 +1,319 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ * Copyright (C) 2015 - 2018 Texas Instruments Incorporated <www.ti.com>
+ * Written by Mugunthan V N <mugunthanvnm@ti.com>
+ *
+ */
+
+#ifndef _DMA_H_
+#define _DMA_H_
+
+#include <linux/errno.h>
+#include <linux/types.h>
+
+/*
+ * enum dma_direction - dma transfer direction indicator
+ * @DMA_MEM_TO_MEM: Memcpy mode
+ * @DMA_MEM_TO_DEV: From Memory to Device
+ * @DMA_DEV_TO_MEM: From Device to Memory
+ * @DMA_DEV_TO_DEV: From Device to Device
+ */
+enum dma_direction {
+	DMA_MEM_TO_MEM,
+	DMA_MEM_TO_DEV,
+	DMA_DEV_TO_MEM,
+	DMA_DEV_TO_DEV,
+};
+
+#define DMA_SUPPORTS_MEM_TO_MEM	BIT(0)
+#define DMA_SUPPORTS_MEM_TO_DEV	BIT(1)
+#define DMA_SUPPORTS_DEV_TO_MEM	BIT(2)
+#define DMA_SUPPORTS_DEV_TO_DEV	BIT(3)
+
+/*
+ * struct dma_dev_priv - information about a device used by the uclass
+ *
+ * @supported: mode of transfers that DMA can support, should be
+ *	       one/multiple of DMA_SUPPORTS_*
+ */
+struct dma_dev_priv {
+	u32 supported;
+};
+
+#ifdef CONFIG_DMA_CHANNELS
+/**
+ * A DMA is a feature of computer systems that allows certain hardware
+ * subsystems to access main system memory, independent of the CPU.
+ * DMA channels are typically generated externally to the HW module
+ * consuming them, by an entity this API calls a DMA provider. This API
+ * provides a standard means for drivers to enable and disable DMAs, and to
+ * copy, send and receive data using DMA.
+ *
+ * A driver that implements UCLASS_DMA is a DMA provider. A provider will
+ * often implement multiple separate DMAs, since the hardware it manages
+ * often has this capability. dma_uclass.h describes the interface which
+ * DMA providers must implement.
+ *
+ * DMA consumers/clients are the HW modules driven by the DMA channels. This
+ * header file describes the API used by drivers for those HW modules.
+ *
+ * DMA consumer DMA_MEM_TO_DEV (transmit) usage example (based on networking).
+ * Note. dma_send() is sync operation always -  it'll start transfer and will
+ * poll for it to complete:
+ *	- get/request dma channel
+ *	struct dma dma_tx;
+ *	ret = dma_get_by_name(common->dev, "tx0", &dma_tx);
+ *	if (ret) ...
+ *
+ *	- enable dma channel
+ *	ret = dma_enable(&dma_tx);
+ *	if (ret) ...
+ *
+ *	- dma transmit DMA_MEM_TO_DEV.
+ *	struct ti_drv_packet_data packet_data;
+ *
+ *	packet_data.opt1 = val1;
+ *	packet_data.opt2 = val2;
+ *	ret = dma_send(&dma_tx, packet, length, &packet_data);
+ *	if (ret) ..
+ *
+ * DMA consumer DMA_DEV_TO_MEM (receive) usage example (based on networking).
+ * Note. dma_receive() is sync operation always - it'll start transfer
+ * (if required) and will poll for it to complete (or for any previously
+ * configured dev2mem transfer to complete):
+ *	- get/request dma channel
+ *	struct dma dma_rx;
+ *	ret = dma_get_by_name(common->dev, "rx0", &dma_rx);
+ *	if (ret) ...
+ *
+ *	- enable dma channel
+ *	ret = dma_enable(&dma_rx);
+ *	if (ret) ...
+ *
+ *	- dma receive DMA_DEV_TO_MEM.
+ *	struct ti_drv_packet_data packet_data;
+ *
+ *	len = dma_receive(&dma_rx, (void **)packet, &packet_data);
+ *	if (ret < 0) ...
+ *
+ * DMA consumer DMA_DEV_TO_MEM (receive) zero-copy usage example (based on
+ * networking). Networking subsystem allows to configure and use few receive
+ * buffers (dev2mem), as Networking RX DMA channels usually implemented
+ * as streaming interface
+ *	- get/request dma channel
+ *	struct dma dma_rx;
+ *	ret = dma_get_by_name(common->dev, "rx0", &dma_rx);
+ *	if (ret) ...
+ *
+ *	for (i = 0; i < RX_DESC_NUM; i++) {
+ *		ret = dma_prepare_rcv_buf(&dma_rx,
+ *					  net_rx_packets[i],
+ *					  RX_BUF_SIZE);
+ *		if (ret) ...
+ *	}
+ *
+ *	- enable dma channel
+ *	ret = dma_enable(&dma_rx);
+ *	if (ret) ...
+ *
+ *	- dma receive DMA_DEV_TO_MEM.
+ *	struct ti_drv_packet_data packet_data;
+ *
+ *	len = dma_receive(&dma_rx, (void **)packet, &packet_data);
+ *	if (ret < 0) ..
+ *
+ *	-- process packet --
+ *
+ *	- return buffer back to DAM channel
+ *	ret = dma_prepare_rcv_buf(&dma_rx,
+ *				  net_rx_packets[rx_next],
+ *				  RX_BUF_SIZE);
+ */
+
+struct udevice;
+
+/**
+ * struct dma - A handle to (allowing control of) a single DMA.
+ *
+ * Clients provide storage for DMA handles. The content of the structure is
+ * managed solely by the DMA API and DMA drivers. A DMA struct is
+ * initialized by "get"ing the DMA struct. The DMA struct is passed to all
+ * other DMA APIs to identify which DMA channel to operate upon.
+ *
+ * @dev: The device which implements the DMA channel.
+ * @id: The DMA channel ID within the provider.
+ *
+ * Currently, the DMA API assumes that a single integer ID is enough to
+ * identify and configure any DMA channel for any DMA provider. If this
+ * assumption becomes invalid in the future, the struct could be expanded to
+ * either (a) add more fields to allow DMA providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct dma {
+	struct udevice *dev;
+	/*
+	 * Written by of_xlate. We assume a single id is enough for now. In the
+	 * future, we might add more fields here.
+	 */
+	unsigned long id;
+};
+
+# if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DMA)
+/**
+ * dma_get_by_index - Get/request a DMA by integer index.
+ *
+ * This looks up and requests a DMA. The index is relative to the client
+ * device; each device is assumed to have n DMAs associated with it somehow,
+ * and this function finds and requests one of them. The mapping of client
+ * device DMA indices to provider DMAs may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the DMA to request, within the client's list of
+ *		DMA channels.
+ * @dma:	A pointer to a DMA struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int dma_get_by_index(struct udevice *dev, int index, struct dma *dma);
+
+/**
+ * dma_get_by_name - Get/request a DMA by name.
+ *
+ * This looks up and requests a DMA. The name is relative to the client
+ * device; each device is assumed to have n DMAs associated with it somehow,
+ * and this function finds and requests one of them. The mapping of client
+ * device DMA names to provider DMAs may be via device-tree properties,
+ * board-provided mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the DMA to request, within the client's list of
+ *		DMA channels.
+ * @dma:	A pointer to a DMA struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma);
+# else
+static inline int dma_get_by_index(struct udevice *dev, int index,
+				   struct dma *dma)
+{
+	return -ENOSYS;
+}
+
+static inline int dma_get_by_name(struct udevice *dev, const char *name,
+				  struct dma *dma)
+{
+	return -ENOSYS;
+}
+# endif
+
+/**
+ * dma_request - Request a DMA by provider-specific ID.
+ *
+ * This requests a DMA using a provider-specific ID. Generally, this function
+ * should not be used, since dma_get_by_index/name() provide an interface that
+ * better separates clients from intimate knowledge of DMA providers.
+ * However, this function may be useful in core SoC-specific code.
+ *
+ * @dev: The DMA provider device.
+ * @dma: A pointer to a DMA struct to initialize. The caller must
+ *	 have already initialized any field in this struct which the
+ *	 DMA provider uses to identify the DMA channel.
+ * @return 0 if OK, or a negative error code.
+ */
+int dma_request(struct udevice *dev, struct dma *dma);
+
+/**
+ * dma_free - Free a previously requested DMA.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int dma_free(struct dma *dma);
+
+/**
+ * dma_enable() - Enable (turn on) a DMA channel.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @return zero on success, or -ve error code.
+ */
+int dma_enable(struct dma *dma);
+
+/**
+ * dma_disable() - Disable (turn off) a DMA channel.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @return zero on success, or -ve error code.
+ */
+int dma_disable(struct dma *dma);
+
+/**
+ * dma_prepare_rcv_buf() - Prepare/add receive DMA buffer.
+ *
+ * It allows to implement zero-copy async DMA_DEV_TO_MEM (receive) transactions
+ * if supported by DMA providers.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @dst: The receive buffer pointer.
+ * @size: The receive buffer size
+ * @return zero on success, or -ve error code.
+ */
+int dma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size);
+
+/**
+ * dma_receive() - Receive a DMA transfer.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @dst: The destination pointer.
+ * @metadata: DMA driver's channel specific data
+ * @return length of received data on success, or zero - no data,
+ * or -ve error code.
+ */
+int dma_receive(struct dma *dma, void **dst, void *metadata);
+
+/**
+ * dma_send() - Send a DMA transfer.
+ *
+ * @dma: A DMA struct that was previously successfully requested by
+ *	 dma_request/get_by_*().
+ * @src: The source pointer.
+ * @len: Length of the data to be sent (number of bytes).
+ * @metadata: DMA driver's channel specific data
+ * @return zero on success, or -ve error code.
+ */
+int dma_send(struct dma *dma, void *src, size_t len, void *metadata);
+#endif /* CONFIG_DMA_CHANNELS */
+
+/*
+ * dma_get_device - get a DMA device which supports transfer
+ * type of transfer_type
+ *
+ * @transfer_type - transfer type should be one/multiple of
+ *		    DMA_SUPPORTS_*
+ * @devp - udevice pointer to return the found device
+ * @return - will return on success and devp will hold the
+ *	     pointer to the device
+ */
+int dma_get_device(u32 transfer_type, struct udevice **devp);
+
+/*
+ * dma_memcpy - try to use DMA to do a mem copy which will be
+ *		much faster than CPU mem copy
+ *
+ * @dst - destination pointer
+ * @src - souce pointer
+ * @len - data length to be copied
+ * @return - on successful transfer returns no of bytes
+	     transferred and on failure return error code.
+ */
+int dma_memcpy(void *dst, void *src, size_t len);
+
+#endif	/* _DMA_H_ */
diff --git a/include/dp83848.h b/include/dp83848.h
new file mode 100644
index 0000000..f1bc3d8
--- /dev/null
+++ b/include/dp83848.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * DP83848 ethernet Physical layer
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ */
+
+
+/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
+
+#define DP83848_CTL_REG		0x0	/* Basic Mode Control Reg */
+#define DP83848_STAT_REG		0x1	/* Basic Mode Status Reg */
+#define DP83848_PHYID1_REG		0x2	/* PHY Idendifier Reg 1 */
+#define DP83848_PHYID2_REG		0x3	/* PHY Idendifier Reg 2 */
+#define DP83848_ANA_REG			0x4	/* Auto_Neg Advt Reg  */
+#define DP83848_ANLPA_REG		0x5	/* Auto_neg Link Partner Ability Reg */
+#define DP83848_ANE_REG			0x6	/* Auto-neg Expansion Reg  */
+#define DP83848_PHY_STAT_REG		0x10	/* PHY Status Register  */
+#define DP83848_PHY_INTR_CTRL_REG	0x11	/* PHY Interrupt Control Register */
+#define DP83848_PHY_CTRL_REG		0x19	/* PHY Status Register  */
+
+/*--Bit definitions: DP83848_CTL_REG */
+#define DP83848_RESET		(1 << 15)  /* 1= S/W Reset */
+#define DP83848_LOOPBACK	(1 << 14)  /* 1=loopback Enabled */
+#define DP83848_SPEED_SELECT	(1 << 13)
+#define DP83848_AUTONEG		(1 << 12)
+#define DP83848_POWER_DOWN	(1 << 11)
+#define DP83848_ISOLATE		(1 << 10)
+#define DP83848_RESTART_AUTONEG	(1 << 9)
+#define DP83848_DUPLEX_MODE	(1 << 8)
+#define DP83848_COLLISION_TEST	(1 << 7)
+
+/*--Bit definitions: DP83848_STAT_REG */
+#define DP83848_100BASE_T4	(1 << 15)
+#define DP83848_100BASE_TX_FD	(1 << 14)
+#define DP83848_100BASE_TX_HD	(1 << 13)
+#define DP83848_10BASE_T_FD	(1 << 12)
+#define DP83848_10BASE_T_HD	(1 << 11)
+#define DP83848_MF_PREAMB_SUPPR	(1 << 6)
+#define DP83848_AUTONEG_COMP	(1 << 5)
+#define DP83848_RMT_FAULT	(1 << 4)
+#define DP83848_AUTONEG_ABILITY	(1 << 3)
+#define DP83848_LINK_STATUS	(1 << 2)
+#define DP83848_JABBER_DETECT	(1 << 1)
+#define DP83848_EXTEND_CAPAB	(1 << 0)
+
+/*--definitions: DP83848_PHYID1 */
+#define DP83848_PHYID1_OUI	0x2000
+#define DP83848_PHYID2_OUI	0x5c90
+
+/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
+#define DP83848_NP		(1 << 15)
+#define DP83848_ACK		(1 << 14)
+#define DP83848_RF		(1 << 13)
+#define DP83848_PAUSE		(1 << 10)
+#define DP83848_T4		(1 << 9)
+#define DP83848_TX_FDX		(1 << 8)
+#define DP83848_TX_HDX		(1 << 7)
+#define DP83848_10_FDX		(1 << 6)
+#define DP83848_10_HDX		(1 << 5)
+#define DP83848_AN_IEEE_802_3	0x0001
+
+/*--Bit definitions: DP83848_ANER */
+#define DP83848_PDF		(1 << 4)
+#define DP83848_LP_NP_ABLE	(1 << 3)
+#define DP83848_NP_ABLE		(1 << 2)
+#define DP83848_PAGE_RX		(1 << 1)
+#define DP83848_LP_AN_ABLE	(1 << 0)
+
+/*--Bit definitions: DP83848_PHY_STAT */
+#define DP83848_RX_ERR_LATCH		(1 << 13)
+#define DP83848_POLARITY_STAT		(1 << 12)
+#define DP83848_FALSE_CAR_SENSE		(1 << 11)
+#define DP83848_SIG_DETECT		(1 << 10)
+#define DP83848_DESCRAM_LOCK		(1 << 9)
+#define DP83848_PAGE_RCV		(1 << 8)
+#define DP83848_PHY_RMT_FAULT		(1 << 6)
+#define DP83848_JABBER			(1 << 5)
+#define DP83848_AUTONEG_COMPLETE	(1 << 4)
+#define DP83848_LOOPBACK_STAT		(1 << 3)
+#define DP83848_DUPLEX			(1 << 2)
+#define DP83848_SPEED			(1 << 1)
+#define DP83848_LINK			(1 << 0)
diff --git a/include/ds1722.h b/include/ds1722.h
new file mode 100644
index 0000000..e115696
--- /dev/null
+++ b/include/ds1722.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _DS1722_H_
+#define _DS1722_H_
+
+#define DS1722_RESOLUTION_8BIT	0x0
+#define DS1722_RESOLUTION_9BIT	0x1
+#define DS1722_RESOLUTION_10BIT	0x2
+#define DS1722_RESOLUTION_11BIT	0x3
+#define DS1722_RESOLUTION_12BIT	0x4
+
+int ds1722_probe(int dev);
+
+#endif /* _DS1722_H_ */
diff --git a/include/dsi_host.h b/include/dsi_host.h
new file mode 100644
index 0000000..9dfc7b3
--- /dev/null
+++ b/include/dsi_host.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
+ *
+ */
+
+#ifndef _DSI_HOST_H
+#define _DSI_HOST_H
+
+#include <mipi_dsi.h>
+
+struct dsi_host_ops {
+	/**
+	 * init() - initialized the dsi_host
+	 *
+	 * @dev: dsi host device
+	 * @device: DSI peripheral device
+	 * @timing: Display timings
+	 * @max_data_lanes: maximum number of data lines
+	 * @phy_ops: set of function pointers for performing physical operations
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*init)(struct udevice *dev,
+		    struct mipi_dsi_device *device,
+		    struct display_timing *timings,
+		    unsigned int max_data_lanes,
+		    const struct mipi_dsi_phy_ops *phy_ops);
+
+	/**
+	 * enable() - Enable the dsi_host
+	 *
+	 * @dev: dsi host device
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*enable)(struct udevice *dev);
+
+	/**
+	 * disable() - Disable the dsi_host
+	 *
+	 * @dev: dsi host device
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*disable)(struct udevice *dev);
+};
+
+#define dsi_host_get_ops(dev)	((struct dsi_host_ops *)(dev)->driver->ops)
+
+/**
+ * dsi_host_init
+ *
+ * @dev: dsi host device
+ * @device: DSI peripheral device
+ * @timing: Display timings
+ * @max_data_lanes: maximum number of data lines
+ * @phy_ops: set of function pointers for performing physical operations
+ * @return 0 if OK, -ve on error
+ */
+int dsi_host_init(struct udevice *dev,
+		  struct mipi_dsi_device *device,
+		  struct display_timing *timings,
+		  unsigned int max_data_lanes,
+		  const struct mipi_dsi_phy_ops *phy_ops);
+
+/**
+ * dsi_host_enable
+ *
+ * @dev:	dsi host device
+ * @return 0 if OK, -ve on error
+ */
+int dsi_host_enable(struct udevice *dev);
+
+#endif
diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h
new file mode 100644
index 0000000..2c00537
--- /dev/null
+++ b/include/dt-bindings/bus/ti-sysc.h
@@ -0,0 +1,22 @@
+/* TI sysc interconnect target module defines */
+
+/* Generic sysc found on omap2 and later, also known as type1 */
+#define SYSC_OMAP2_CLOCKACTIVITY	(3 << 8)
+#define SYSC_OMAP2_EMUFREE		(1 << 5)
+#define SYSC_OMAP2_ENAWAKEUP		(1 << 2)
+#define SYSC_OMAP2_SOFTRESET		(1 << 1)
+#define SYSC_OMAP2_AUTOIDLE		(1 << 0)
+
+/* Generic sysc found on omap4 and later, also known as type2 */
+#define SYSC_OMAP4_DMADISABLE		(1 << 16)
+#define SYSC_OMAP4_FREEEMU		(1 << 1)	/* Also known as EMUFREE */
+#define SYSC_OMAP4_SOFTRESET		(1 << 0)
+
+/* SmartReflex sysc found on 36xx and later */
+#define SYSC_OMAP3_SR_ENAWAKEUP		(1 << 26)
+
+/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
+#define SYSC_IDLE_FORCE			0
+#define SYSC_IDLE_NO			1
+#define SYSC_IDLE_SMART			2
+#define SYSC_IDLE_SMART_WKUP		3
diff --git a/include/dt-bindings/clk/mpc83xx-clk.h b/include/dt-bindings/clk/mpc83xx-clk.h
new file mode 100644
index 0000000..db4ea15
--- /dev/null
+++ b/include/dt-bindings/clk/mpc83xx-clk.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef DT_BINDINGS_MPC83XX_CLK_H
+#define DT_BINDINGS_MPC83XX_CLK_H
+#define MPC83XX_CLK_CORE	0
+#define MPC83XX_CLK_CSB		1
+#define MPC83XX_CLK_QE		2
+#define MPC83XX_CLK_BRG		3
+#define MPC83XX_CLK_LBIU	4
+#define MPC83XX_CLK_LCLK	5
+#define MPC83XX_CLK_MEM		6
+#define MPC83XX_CLK_MEM_SEC	7
+#define MPC83XX_CLK_ENC		8
+#define MPC83XX_CLK_I2C1	9
+#define MPC83XX_CLK_I2C2	10
+#define MPC83XX_CLK_TDM		11
+#define MPC83XX_CLK_SDHC	12
+#define MPC83XX_CLK_TSEC1	13
+#define MPC83XX_CLK_TSEC2	14
+#define MPC83XX_CLK_USBDR	15
+#define MPC83XX_CLK_USBMPH	16
+#define MPC83XX_CLK_PCIEXP1	17
+#define MPC83XX_CLK_PCIEXP2	18
+#define MPC83XX_CLK_SATA	19
+#define MPC83XX_CLK_DMAC	20
+#define MPC83XX_CLK_PCI		21
+/* Count */
+#define MPC83XX_CLK_COUNT	22
+#endif /* DT_BINDINGS_MPC83XX_CLK_H */
diff --git a/include/dt-bindings/clk/ti-dra7-atl.h b/include/dt-bindings/clk/ti-dra7-atl.h
new file mode 100644
index 0000000..42dd416
--- /dev/null
+++ b/include/dt-bindings/clk/ti-dra7-atl.h
@@ -0,0 +1,40 @@
+/*
+ * This header provides constants for DRA7 ATL (Audio Tracking Logic)
+ *
+ * The constants defined in this header are used in dts files
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Peter Ujfalusi <peter.ujfalusi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
+#define _DT_BINDINGS_CLK_DRA7_ATL_H
+
+#define DRA7_ATL_WS_MCASP1_FSR		0
+#define DRA7_ATL_WS_MCASP1_FSX		1
+#define DRA7_ATL_WS_MCASP2_FSR		2
+#define DRA7_ATL_WS_MCASP2_FSX		3
+#define DRA7_ATL_WS_MCASP3_FSX		4
+#define DRA7_ATL_WS_MCASP4_FSX		5
+#define DRA7_ATL_WS_MCASP5_FSX		6
+#define DRA7_ATL_WS_MCASP6_FSX		7
+#define DRA7_ATL_WS_MCASP7_FSX		8
+#define DRA7_ATL_WS_MCASP8_FSX		9
+#define DRA7_ATL_WS_MCASP8_AHCLKX	10
+#define DRA7_ATL_WS_XREF_CLK3		11
+#define DRA7_ATL_WS_XREF_CLK0		12
+#define DRA7_ATL_WS_XREF_CLK1		13
+#define DRA7_ATL_WS_XREF_CLK2		14
+#define DRA7_ATL_WS_OSC1_X1		15
+
+#endif
diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h
new file mode 100644
index 0000000..86a8806
--- /dev/null
+++ b/include/dt-bindings/clock/am3.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_AM3_H
+#define __DT_BINDINGS_CLK_AM3_H
+
+#define AM3_CLKCTRL_OFFSET	0x0
+#define AM3_CLKCTRL_INDEX(offset)	((offset) - AM3_CLKCTRL_OFFSET)
+
+/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
+
+/* l4_per clocks */
+#define AM3_L4_PER_CLKCTRL_OFFSET	0x14
+#define AM3_L4_PER_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
+#define AM3_CPGMAC0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x14)
+#define AM3_LCDC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x18)
+#define AM3_USB_OTG_HS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x1c)
+#define AM3_TPTC0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x24)
+#define AM3_EMIF_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x28)
+#define AM3_OCMCRAM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x2c)
+#define AM3_GPMC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x30)
+#define AM3_MCASP0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x34)
+#define AM3_UART6_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x38)
+#define AM3_MMC1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x3c)
+#define AM3_ELM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x40)
+#define AM3_I2C3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x44)
+#define AM3_I2C2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x48)
+#define AM3_SPI0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x4c)
+#define AM3_SPI1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x50)
+#define AM3_L4_LS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x60)
+#define AM3_MCASP1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x68)
+#define AM3_UART2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x6c)
+#define AM3_UART3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x70)
+#define AM3_UART4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x74)
+#define AM3_UART5_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x78)
+#define AM3_TIMER7_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x7c)
+#define AM3_TIMER2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x80)
+#define AM3_TIMER3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x84)
+#define AM3_TIMER4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x88)
+#define AM3_RNG_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x90)
+#define AM3_AES_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x94)
+#define AM3_SHAM_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xa0)
+#define AM3_GPIO2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xac)
+#define AM3_GPIO3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb0)
+#define AM3_GPIO4_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xb4)
+#define AM3_TPCC_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xbc)
+#define AM3_D_CAN0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc0)
+#define AM3_D_CAN1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xc4)
+#define AM3_EPWMSS1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xcc)
+#define AM3_EPWMSS0_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xd4)
+#define AM3_EPWMSS2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xd8)
+#define AM3_L3_INSTR_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xdc)
+#define AM3_L3_MAIN_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xe0)
+#define AM3_PRUSS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xe8)
+#define AM3_TIMER5_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xec)
+#define AM3_TIMER6_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf0)
+#define AM3_MMC2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf4)
+#define AM3_MMC3_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xf8)
+#define AM3_TPTC1_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0xfc)
+#define AM3_TPTC2_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x100)
+#define AM3_SPINLOCK_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x10c)
+#define AM3_MAILBOX_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x110)
+#define AM3_L4_HS_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x120)
+#define AM3_OCPWP_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x130)
+#define AM3_CLKDIV32K_CLKCTRL	AM3_L4_PER_CLKCTRL_INDEX(0x14c)
+
+/* l4_wkup clocks */
+#define AM3_L4_WKUP_CLKCTRL_OFFSET	0x4
+#define AM3_L4_WKUP_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
+#define AM3_CONTROL_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
+#define AM3_GPIO1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
+#define AM3_DEBUGSS_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
+#define AM3_WKUP_M3_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
+#define AM3_UART1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
+#define AM3_I2C1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
+#define AM3_ADC_TSC_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
+#define AM3_SMARTREFLEX0_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
+#define AM3_TIMER1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
+#define AM3_SMARTREFLEX1_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
+#define AM3_WD_TIMER2_CLKCTRL	AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
+
+/* mpu clocks */
+#define AM3_MPU_CLKCTRL_OFFSET	0x4
+#define AM3_MPU_CLKCTRL_INDEX(offset)	((offset) - AM3_MPU_CLKCTRL_OFFSET)
+#define AM3_MPU_CLKCTRL	AM3_MPU_CLKCTRL_INDEX(0x4)
+
+/* l4_rtc clocks */
+#define AM3_RTC_CLKCTRL	AM3_CLKCTRL_INDEX(0x0)
+
+/* gfx_l3 clocks */
+#define AM3_GFX_L3_CLKCTRL_OFFSET	0x4
+#define AM3_GFX_L3_CLKCTRL_INDEX(offset)	((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
+#define AM3_GFX_CLKCTRL	AM3_GFX_L3_CLKCTRL_INDEX(0x4)
+
+/* l4_cefuse clocks */
+#define AM3_L4_CEFUSE_CLKCTRL_OFFSET	0x20
+#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
+#define AM3_CEFUSE_CLKCTRL	AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
+
+/* XXX: Compatibility part end */
+
+/* l4ls clocks */
+#define AM3_L4LS_CLKCTRL_OFFSET	0x38
+#define AM3_L4LS_CLKCTRL_INDEX(offset)	((offset) - AM3_L4LS_CLKCTRL_OFFSET)
+#define AM3_L4LS_UART6_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x38)
+#define AM3_L4LS_MMC1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x3c)
+#define AM3_L4LS_ELM_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x40)
+#define AM3_L4LS_I2C3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x44)
+#define AM3_L4LS_I2C2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x48)
+#define AM3_L4LS_SPI0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x4c)
+#define AM3_L4LS_SPI1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x50)
+#define AM3_L4LS_L4_LS_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x60)
+#define AM3_L4LS_UART2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x6c)
+#define AM3_L4LS_UART3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x70)
+#define AM3_L4LS_UART4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x74)
+#define AM3_L4LS_UART5_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x78)
+#define AM3_L4LS_TIMER7_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x7c)
+#define AM3_L4LS_TIMER2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x80)
+#define AM3_L4LS_TIMER3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x84)
+#define AM3_L4LS_TIMER4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x88)
+#define AM3_L4LS_RNG_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x90)
+#define AM3_L4LS_GPIO2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xac)
+#define AM3_L4LS_GPIO3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb0)
+#define AM3_L4LS_GPIO4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb4)
+#define AM3_L4LS_D_CAN0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc0)
+#define AM3_L4LS_D_CAN1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc4)
+#define AM3_L4LS_EPWMSS1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xcc)
+#define AM3_L4LS_EPWMSS0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xd4)
+#define AM3_L4LS_EPWMSS2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xd8)
+#define AM3_L4LS_TIMER5_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xec)
+#define AM3_L4LS_TIMER6_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xf0)
+#define AM3_L4LS_MMC2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xf4)
+#define AM3_L4LS_SPINLOCK_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x10c)
+#define AM3_L4LS_MAILBOX_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x110)
+#define AM3_L4LS_OCPWP_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x130)
+
+/* l3s clocks */
+#define AM3_L3S_CLKCTRL_OFFSET	0x1c
+#define AM3_L3S_CLKCTRL_INDEX(offset)	((offset) - AM3_L3S_CLKCTRL_OFFSET)
+#define AM3_L3S_USB_OTG_HS_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x1c)
+#define AM3_L3S_GPMC_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x30)
+#define AM3_L3S_MCASP0_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x34)
+#define AM3_L3S_MCASP1_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x68)
+#define AM3_L3S_MMC3_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0xf8)
+
+/* l3 clocks */
+#define AM3_L3_CLKCTRL_OFFSET	0x24
+#define AM3_L3_CLKCTRL_INDEX(offset)	((offset) - AM3_L3_CLKCTRL_OFFSET)
+#define AM3_L3_TPTC0_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x24)
+#define AM3_L3_EMIF_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x28)
+#define AM3_L3_OCMCRAM_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x2c)
+#define AM3_L3_AES_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x94)
+#define AM3_L3_SHAM_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xa0)
+#define AM3_L3_TPCC_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xbc)
+#define AM3_L3_L3_INSTR_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xdc)
+#define AM3_L3_L3_MAIN_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xe0)
+#define AM3_L3_TPTC1_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xfc)
+#define AM3_L3_TPTC2_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x100)
+
+/* l4hs clocks */
+#define AM3_L4HS_CLKCTRL_OFFSET	0x120
+#define AM3_L4HS_CLKCTRL_INDEX(offset)	((offset) - AM3_L4HS_CLKCTRL_OFFSET)
+#define AM3_L4HS_L4_HS_CLKCTRL	AM3_L4HS_CLKCTRL_INDEX(0x120)
+
+/* pruss_ocp clocks */
+#define AM3_PRUSS_OCP_CLKCTRL_OFFSET	0xe8
+#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset)	((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
+#define AM3_PRUSS_OCP_PRUSS_CLKCTRL	AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
+
+/* cpsw_125mhz clocks */
+#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL	AM3_CLKCTRL_INDEX(0x14)
+
+/* lcdc clocks */
+#define AM3_LCDC_CLKCTRL_OFFSET	0x18
+#define AM3_LCDC_CLKCTRL_INDEX(offset)	((offset) - AM3_LCDC_CLKCTRL_OFFSET)
+#define AM3_LCDC_LCDC_CLKCTRL	AM3_LCDC_CLKCTRL_INDEX(0x18)
+
+/* clk_24mhz clocks */
+#define AM3_CLK_24MHZ_CLKCTRL_OFFSET	0x14c
+#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset)	((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
+#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL	AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
+
+/* l4_wkup clocks */
+#define AM3_L4_WKUP_CONTROL_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
+#define AM3_L4_WKUP_GPIO1_CLKCTRL	AM3_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_L4_WKUP_CLKCTRL	AM3_CLKCTRL_INDEX(0xc)
+#define AM3_L4_WKUP_UART1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb4)
+#define AM3_L4_WKUP_I2C1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb8)
+#define AM3_L4_WKUP_ADC_TSC_CLKCTRL	AM3_CLKCTRL_INDEX(0xbc)
+#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL	AM3_CLKCTRL_INDEX(0xc0)
+#define AM3_L4_WKUP_TIMER1_CLKCTRL	AM3_CLKCTRL_INDEX(0xc4)
+#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL	AM3_CLKCTRL_INDEX(0xc8)
+#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL	AM3_CLKCTRL_INDEX(0xd4)
+
+/* l3_aon clocks */
+#define AM3_L3_AON_CLKCTRL_OFFSET	0x14
+#define AM3_L3_AON_CLKCTRL_INDEX(offset)	((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
+#define AM3_L3_AON_DEBUGSS_CLKCTRL	AM3_L3_AON_CLKCTRL_INDEX(0x14)
+
+/* l4_wkup_aon clocks */
+#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET	0xb0
+#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
+#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL	AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
+
+/* mpu clocks */
+#define AM3_MPU_MPU_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
+
+/* l4_rtc clocks */
+#define AM3_L4_RTC_RTC_CLKCTRL	AM3_CLKCTRL_INDEX(0x0)
+
+/* gfx_l3 clocks */
+#define AM3_GFX_L3_GFX_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
+
+/* l4_cefuse clocks */
+#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL	AM3_CLKCTRL_INDEX(0x20)
+
+#endif
diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/ast2500-scu.h
new file mode 100644
index 0000000..4803abe
--- /dev/null
+++ b/include/dt-bindings/clock/ast2500-scu.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Google Inc.
+ */
+
+/* Core Clocks */
+#define PLL_HPLL	1
+#define PLL_DPLL	2
+#define PLL_D2PLL	3
+#define PLL_MPLL	4
+#define ARMCLK		5
+
+
+/* Bus Clocks, derived from core clocks */
+#define BCLK_PCLK	101
+#define BCLK_LHCLK	102
+#define BCLK_MACCLK	103
+#define BCLK_SDCLK	104
+#define BCLK_ARMCLK	105
+
+#define MCLK_DDR	201
+
+/* Special clocks */
+#define PCLK_UART1	501
+#define PCLK_UART2	502
+#define PCLK_UART3	503
+#define PCLK_UART4	504
+#define PCLK_UART5	505
+#define PCLK_MAC1	506
+#define PCLK_MAC2	507
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
new file mode 100644
index 0000000..ab3ee24
--- /dev/null
+++ b/include/dt-bindings/clock/at91.h
@@ -0,0 +1,23 @@
+/*
+ * This header provides constants for AT91 pmc status.
+ *
+ * The constants defined in this header are being used in dts.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AT91_H
+#define _DT_BINDINGS_CLK_AT91_H
+
+#define AT91_PMC_MOSCS		0		/* MOSCS Flag */
+#define AT91_PMC_LOCKA		1		/* PLLA Lock */
+#define AT91_PMC_LOCKB		2		/* PLLB Lock */
+#define AT91_PMC_MCKRDY		3		/* Master Clock */
+#define AT91_PMC_LOCKU		6		/* UPLL Lock */
+#define AT91_PMC_PCKRDY(id)	(8 + (id))	/* Programmable Clock */
+#define AT91_PMC_MOSCSELS	16		/* Main Oscillator Selection */
+#define AT91_PMC_MOSCRCS	17		/* Main On-Chip RC */
+#define AT91_PMC_CFDEV		18		/* Clock Failure Detector Event */
+#define AT91_PMC_GCKRDY		24		/* Generated Clocks */
+
+#endif
diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h
new file mode 100644
index 0000000..8ec4a26
--- /dev/null
+++ b/include/dt-bindings/clock/axg-aoclkc.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_CTS_OSCIN	11
+#define CLKID_AO_32K_PRE	12
+#define CLKID_AO_32K_DIV	13
+#define CLKID_AO_32K_SEL	14
+#define CLKID_AO_32K		15
+#define CLKID_AO_CTS_RTC_OSCIN	16
+
+#endif
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
new file mode 100644
index 0000000..75901c6
--- /dev/null
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2018 Baylibre SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
+#define __AXG_AUDIO_CLKC_BINDINGS_H
+
+#define AUD_CLKID_DDR_ARB		29
+#define AUD_CLKID_PDM			30
+#define AUD_CLKID_TDMIN_A		31
+#define AUD_CLKID_TDMIN_B		32
+#define AUD_CLKID_TDMIN_C		33
+#define AUD_CLKID_TDMIN_LB		34
+#define AUD_CLKID_TDMOUT_A		35
+#define AUD_CLKID_TDMOUT_B		36
+#define AUD_CLKID_TDMOUT_C		37
+#define AUD_CLKID_FRDDR_A		38
+#define AUD_CLKID_FRDDR_B		39
+#define AUD_CLKID_FRDDR_C		40
+#define AUD_CLKID_TODDR_A		41
+#define AUD_CLKID_TODDR_B		42
+#define AUD_CLKID_TODDR_C		43
+#define AUD_CLKID_LOOPBACK		44
+#define AUD_CLKID_SPDIFIN		45
+#define AUD_CLKID_SPDIFOUT		46
+#define AUD_CLKID_RESAMPLE		47
+#define AUD_CLKID_POWER_DETECT		48
+#define AUD_CLKID_MST_A_MCLK		49
+#define AUD_CLKID_MST_B_MCLK		50
+#define AUD_CLKID_MST_C_MCLK		51
+#define AUD_CLKID_MST_D_MCLK		52
+#define AUD_CLKID_MST_E_MCLK		53
+#define AUD_CLKID_MST_F_MCLK		54
+#define AUD_CLKID_SPDIFOUT_CLK		55
+#define AUD_CLKID_SPDIFIN_CLK		56
+#define AUD_CLKID_PDM_DCLK		57
+#define AUD_CLKID_PDM_SYSCLK		58
+#define AUD_CLKID_MST_A_SCLK		79
+#define AUD_CLKID_MST_B_SCLK		80
+#define AUD_CLKID_MST_C_SCLK		81
+#define AUD_CLKID_MST_D_SCLK		82
+#define AUD_CLKID_MST_E_SCLK		83
+#define AUD_CLKID_MST_F_SCLK		84
+#define AUD_CLKID_MST_A_LRCLK		86
+#define AUD_CLKID_MST_B_LRCLK		87
+#define AUD_CLKID_MST_C_LRCLK		88
+#define AUD_CLKID_MST_D_LRCLK		89
+#define AUD_CLKID_MST_E_LRCLK		90
+#define AUD_CLKID_MST_F_LRCLK		91
+#define AUD_CLKID_TDMIN_A_SCLK_SEL	116
+#define AUD_CLKID_TDMIN_B_SCLK_SEL	117
+#define AUD_CLKID_TDMIN_C_SCLK_SEL	118
+#define AUD_CLKID_TDMIN_LB_SCLK_SEL	119
+#define AUD_CLKID_TDMOUT_A_SCLK_SEL	120
+#define AUD_CLKID_TDMOUT_B_SCLK_SEL	121
+#define AUD_CLKID_TDMOUT_C_SCLK_SEL	122
+#define AUD_CLKID_TDMIN_A_SCLK		123
+#define AUD_CLKID_TDMIN_B_SCLK		124
+#define AUD_CLKID_TDMIN_C_SCLK		125
+#define AUD_CLKID_TDMIN_LB_SCLK		126
+#define AUD_CLKID_TDMOUT_A_SCLK		127
+#define AUD_CLKID_TDMOUT_B_SCLK		128
+#define AUD_CLKID_TDMOUT_C_SCLK		129
+#define AUD_CLKID_TDMIN_A_LRCLK		130
+#define AUD_CLKID_TDMIN_B_LRCLK		131
+#define AUD_CLKID_TDMIN_C_LRCLK		132
+#define AUD_CLKID_TDMIN_LB_LRCLK	133
+#define AUD_CLKID_TDMOUT_A_LRCLK	134
+#define AUD_CLKID_TDMOUT_B_LRCLK	135
+#define AUD_CLKID_TDMOUT_C_LRCLK	136
+#define AUD_CLKID_SPDIFOUT_B		151
+#define AUD_CLKID_SPDIFOUT_B_CLK	152
+#define AUD_CLKID_TDM_MCLK_PAD0		155
+#define AUD_CLKID_TDM_MCLK_PAD1		156
+#define AUD_CLKID_TDM_LRCLK_PAD0	157
+#define AUD_CLKID_TDM_LRCLK_PAD1	158
+#define AUD_CLKID_TDM_LRCLK_PAD2	159
+#define AUD_CLKID_TDM_SCLK_PAD0		160
+#define AUD_CLKID_TDM_SCLK_PAD1		161
+#define AUD_CLKID_TDM_SCLK_PAD2		162
+
+#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
new file mode 100644
index 0000000..fd1f938
--- /dev/null
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson-AXG clock tree IDs
+ *
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AXG_CLKC_H
+#define __AXG_CLKC_H
+
+#define CLKID_SYS_PLL				0
+#define CLKID_FIXED_PLL				1
+#define CLKID_FCLK_DIV2				2
+#define CLKID_FCLK_DIV3				3
+#define CLKID_FCLK_DIV4				4
+#define CLKID_FCLK_DIV5				5
+#define CLKID_FCLK_DIV7				6
+#define CLKID_GP0_PLL				7
+#define CLKID_CLK81				10
+#define CLKID_MPLL0				11
+#define CLKID_MPLL1				12
+#define CLKID_MPLL2				13
+#define CLKID_MPLL3				14
+#define CLKID_DDR				15
+#define CLKID_AUDIO_LOCKER			16
+#define CLKID_MIPI_DSI_HOST			17
+#define CLKID_ISA				18
+#define CLKID_PL301				19
+#define CLKID_PERIPHS				20
+#define CLKID_SPICC0				21
+#define CLKID_I2C				22
+#define CLKID_RNG0				23
+#define CLKID_UART0				24
+#define CLKID_MIPI_DSI_PHY			25
+#define CLKID_SPICC1				26
+#define CLKID_PCIE_A				27
+#define CLKID_PCIE_B				28
+#define CLKID_HIU_IFACE				29
+#define CLKID_ASSIST_MISC			30
+#define CLKID_SD_EMMC_B				31
+#define CLKID_SD_EMMC_C				32
+#define CLKID_DMA				33
+#define CLKID_SPI				34
+#define CLKID_AUDIO				35
+#define CLKID_ETH				36
+#define CLKID_UART1				37
+#define CLKID_G2D				38
+#define CLKID_USB0				39
+#define CLKID_USB1				40
+#define CLKID_RESET				41
+#define CLKID_USB				42
+#define CLKID_AHB_ARB0				43
+#define CLKID_EFUSE				44
+#define CLKID_BOOT_ROM				45
+#define CLKID_AHB_DATA_BUS			46
+#define CLKID_AHB_CTRL_BUS			47
+#define CLKID_USB1_DDR_BRIDGE			48
+#define CLKID_USB0_DDR_BRIDGE			49
+#define CLKID_MMC_PCLK				50
+#define CLKID_VPU_INTR				51
+#define CLKID_SEC_AHB_AHB3_BRIDGE		52
+#define CLKID_GIC				53
+#define CLKID_AO_MEDIA_CPU			54
+#define CLKID_AO_AHB_SRAM			55
+#define CLKID_AO_AHB_BUS			56
+#define CLKID_AO_IFACE				57
+#define CLKID_AO_I2C				58
+#define CLKID_SD_EMMC_B_CLK0			59
+#define CLKID_SD_EMMC_C_CLK0			60
+#define CLKID_HIFI_PLL				69
+#define CLKID_PCIE_CML_EN0			79
+#define CLKID_PCIE_CML_EN1			80
+#define CLKID_MIPI_ENABLE			81
+#define CLKID_GEN_CLK				84
+
+#endif /* __AXG_CLKC_H */
diff --git a/include/dt-bindings/clock/bcm2835-aux.h b/include/dt-bindings/clock/bcm2835-aux.h
new file mode 100644
index 0000000..bb79de3
--- /dev/null
+++ b/include/dt-bindings/clock/bcm2835-aux.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ */
+
+#define BCM2835_AUX_CLOCK_UART		0
+#define BCM2835_AUX_CLOCK_SPI1		1
+#define BCM2835_AUX_CLOCK_SPI2		2
+#define BCM2835_AUX_CLOCK_COUNT		3
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
new file mode 100644
index 0000000..2cec01f
--- /dev/null
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ */
+
+#define BCM2835_PLLA			0
+#define BCM2835_PLLB			1
+#define BCM2835_PLLC			2
+#define BCM2835_PLLD			3
+#define BCM2835_PLLH			4
+
+#define BCM2835_PLLA_CORE		5
+#define BCM2835_PLLA_PER		6
+#define BCM2835_PLLB_ARM		7
+#define BCM2835_PLLC_CORE0		8
+#define BCM2835_PLLC_CORE1		9
+#define BCM2835_PLLC_CORE2		10
+#define BCM2835_PLLC_PER		11
+#define BCM2835_PLLD_CORE		12
+#define BCM2835_PLLD_PER		13
+#define BCM2835_PLLH_RCAL		14
+#define BCM2835_PLLH_AUX		15
+#define BCM2835_PLLH_PIX		16
+
+#define BCM2835_CLOCK_TIMER		17
+#define BCM2835_CLOCK_OTP		18
+#define BCM2835_CLOCK_UART		19
+#define BCM2835_CLOCK_VPU		20
+#define BCM2835_CLOCK_V3D		21
+#define BCM2835_CLOCK_ISP		22
+#define BCM2835_CLOCK_H264		23
+#define BCM2835_CLOCK_VEC		24
+#define BCM2835_CLOCK_HSM		25
+#define BCM2835_CLOCK_SDRAM		26
+#define BCM2835_CLOCK_TSENS		27
+#define BCM2835_CLOCK_EMMC		28
+#define BCM2835_CLOCK_PERI_IMAGE	29
+#define BCM2835_CLOCK_PWM		30
+#define BCM2835_CLOCK_PCM		31
+
+#define BCM2835_PLLA_DSI0		32
+#define BCM2835_PLLA_CCP2		33
+#define BCM2835_PLLD_DSI0		34
+#define BCM2835_PLLD_DSI1		35
+
+#define BCM2835_CLOCK_AVEO		36
+#define BCM2835_CLOCK_DFT		37
+#define BCM2835_CLOCK_GP0		38
+#define BCM2835_CLOCK_GP1		39
+#define BCM2835_CLOCK_GP2		40
+#define BCM2835_CLOCK_SLIM		41
+#define BCM2835_CLOCK_SMI		42
+#define BCM2835_CLOCK_TEC		43
+#define BCM2835_CLOCK_DPI		44
+#define BCM2835_CLOCK_CAM0		45
+#define BCM2835_CLOCK_CAM1		46
+#define BCM2835_CLOCK_DSI0E		47
+#define BCM2835_CLOCK_DSI1E		48
+#define BCM2835_CLOCK_DSI0P		49
+#define BCM2835_CLOCK_DSI1P		50
diff --git a/include/dt-bindings/clock/bcm3380-clock.h b/include/dt-bindings/clock/bcm3380-clock.h
new file mode 100644
index 0000000..998d08f
--- /dev/null
+++ b/include/dt-bindings/clock/bcm3380-clock.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from Broadcom GPL Source Code:
+ *	Copyright (C) Broadcom Corporation
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM3380_H
+#define __DT_BINDINGS_CLOCK_BCM3380_H
+
+#define BCM3380_CLK0_DDR	0
+#define BCM3380_CLK0_FPM	1
+#define BCM3380_CLK0_CRYPTO	2
+#define BCM3380_CLK0_EPHY	3
+#define BCM3380_CLK0_PCIE	16
+#define BCM3380_CLK0_SPI	17
+#define BCM3380_CLK0_ENET0	18
+#define BCM3380_CLK0_ENET1	19
+#define BCM3380_CLK0_PCM	27
+
+#endif /* __DT_BINDINGS_CLOCK_BCM3380_H */
diff --git a/include/dt-bindings/clock/bcm6318-clock.h b/include/dt-bindings/clock/bcm6318-clock.h
new file mode 100644
index 0000000..3f10448
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6318-clock.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6318_H
+#define __DT_BINDINGS_CLOCK_BCM6318_H
+
+#define BCM6318_CLK_ADSL_ASB	0
+#define BCM6318_CLK_USB_ASB	1
+#define BCM6318_CLK_MIPS_ASB	2
+#define BCM6318_CLK_PCIE_ASB	3
+#define BCM6318_CLK_PHYMIPS_ASB	4
+#define BCM6318_CLK_ROBOSW_ASB	5
+#define BCM6318_CLK_SAR_ASB	6
+#define BCM6318_CLK_SDR_ASB	7
+#define BCM6318_CLK_SWREG_ASB	8
+#define BCM6318_CLK_PERIPH_ASB	9
+#define BCM6318_CLK_CPUBUS160	10
+#define BCM6318_CLK_ADSL	11
+#define BCM6318_CLK_SAR125	12
+#define BCM6318_CLK_MIPS	13
+#define BCM6318_CLK_PCIE	14
+#define BCM6318_CLK_ROBOSW250	16
+#define BCM6318_CLK_ROBOSW025	17
+#define BCM6318_CLK_SDR		19
+#define BCM6318_CLK_USB		20
+#define BCM6318_CLK_HSSPI	25
+#define BCM6318_CLK_PCIE25	27
+#define BCM6318_CLK_PHYMIPS	28
+#define BCM6318_CLK_AFE		29
+#define BCM6318_CLK_QPROC	30
+
+#define BCM6318_UCLK_ADSL	0
+#define BCM6318_UCLK_ARB	1
+#define BCM6318_UCLK_MIPS	2
+#define BCM6318_UCLK_PCIE	3
+#define BCM6318_UCLK_PERIPH	4
+#define BCM6318_UCLK_PHYMIPS	5
+#define BCM6318_UCLK_ROBOSW	6
+#define BCM6318_UCLK_SAR	7
+#define BCM6318_UCLK_SDR	8
+#define BCM6318_UCLK_USB	9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6318_H */
diff --git a/include/dt-bindings/clock/bcm63268-clock.h b/include/dt-bindings/clock/bcm63268-clock.h
new file mode 100644
index 0000000..2725dcd
--- /dev/null
+++ b/include/dt-bindings/clock/bcm63268-clock.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM63268_H
+#define __DT_BINDINGS_CLOCK_BCM63268_H
+
+#define BCM63268_CLK_GLESS	0
+#define BCM63268_CLK_VDSL_QPROC	1
+#define BCM63268_CLK_VDSL_AFE	2
+#define BCM63268_CLK_VDSL	3
+#define BCM63268_CLK_MIPS	4
+#define BCM63268_CLK_WLAN_OCP	5
+#define BCM63268_CLK_DECT	6
+#define BCM63268_CLK_FAP0	7
+#define BCM63268_CLK_FAP1	8
+#define BCM63268_CLK_SAR	9
+#define BCM63268_CLK_ROBOSW	10
+#define BCM63268_CLK_PCM	11
+#define BCM63268_CLK_USBD	12
+#define BCM63268_CLK_USBH	13
+#define BCM63268_CLK_IPSEC	14
+#define BCM63268_CLK_SPI	15
+#define BCM63268_CLK_HSSPI	16
+#define BCM63268_CLK_PCIE	17
+#define BCM63268_CLK_PHYMIPS	18
+#define BCM63268_CLK_GMAC	19
+#define BCM63268_CLK_NAND	20
+#define BCM63268_CLK_TBUS	27
+#define BCM63268_CLK_ROBOSW250	31
+
+#define BCM63268_TCLK_EPHY1	0
+#define BCM63268_TCLK_EPHY2	1
+#define BCM63268_TCLK_EPHY3	2
+#define BCM63268_TCLK_GPHY	3
+#define BCM63268_TCLK_DSL	4
+#define BCM63268_TCLK_WO_EPHY	5
+#define BCM63268_TCLK_WO_DSL	6
+#define BCM63268_TCLK_FAP1	11
+#define BCM63268_TCLK_FAP2	15
+#define BCM63268_TCLK_UTO_50	16
+#define BCM63268_TCLK_UTO_EXT	17
+#define BCM63268_TCLK_USB_REF	18
+#define BCM63268_TCLK_SW_RST	29
+#define BCM63268_TCLK_HW_RST	30
+#define BCM63268_TCLK_POR_RST	31
+
+#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */
diff --git a/include/dt-bindings/clock/bcm6328-clock.h b/include/dt-bindings/clock/bcm6328-clock.h
new file mode 100644
index 0000000..6f1e018
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6328-clock.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6328_H
+#define __DT_BINDINGS_CLOCK_BCM6328_H
+
+#define BCM6328_CLK_PHYMIPS	0
+#define BCM6328_CLK_ADSL_QPROC	1
+#define BCM6328_CLK_ADSL_AFE	2
+#define BCM6328_CLK_ADSL	3
+#define BCM6328_CLK_MIPS	4
+#define BCM6328_CLK_SAR		5
+#define BCM6328_CLK_PCM		6
+#define BCM6328_CLK_USBD	7
+#define BCM6328_CLK_USBH	8
+#define BCM6328_CLK_HSSPI	9
+#define BCM6328_CLK_PCIE	10
+#define BCM6328_CLK_ROBOSW	11
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */
diff --git a/include/dt-bindings/clock/bcm6338-clock.h b/include/dt-bindings/clock/bcm6338-clock.h
new file mode 100644
index 0000000..489aa1f
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6338-clock.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6338_H
+#define __DT_BINDINGS_CLOCK_BCM6338_H
+
+#define BCM6338_CLK_ADSL	0
+#define BCM6338_CLK_MPI		1
+#define BCM6338_CLK_SDRAM	2
+#define BCM6338_CLK_ENET	4
+#define BCM6338_CLK_SAR		5
+#define BCM6338_CLK_SPI		9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6338_H */
diff --git a/include/dt-bindings/clock/bcm6348-clock.h b/include/dt-bindings/clock/bcm6348-clock.h
new file mode 100644
index 0000000..c67a7fe
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6348-clock.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6348_H
+#define __DT_BINDINGS_CLOCK_BCM6348_H
+
+#define BCM6348_CLK_ADSL	0
+#define BCM6348_CLK_MPI		1
+#define BCM6348_CLK_SDRAM	2
+#define BCM6348_CLK_M2M		3
+#define BCM6348_CLK_ENET	4
+#define BCM6348_CLK_SAR		5
+#define BCM6348_CLK_USBS	6
+#define BCM6348_CLK_USBH	8
+#define BCM6348_CLK_SPI		9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */
diff --git a/include/dt-bindings/clock/bcm6358-clock.h b/include/dt-bindings/clock/bcm6358-clock.h
new file mode 100644
index 0000000..a7529bc
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6358-clock.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6358_H
+#define __DT_BINDINGS_CLOCK_BCM6358_H
+
+#define BCM6358_CLK_ENET	4
+#define BCM6358_CLK_ADSL	5
+#define BCM6358_CLK_PCM		8
+#define BCM6358_CLK_SPI		9
+#define BCM6358_CLK_USBS	10
+#define BCM6358_CLK_SAR		11
+#define BCM6358_CLK_EMUSB	17
+#define BCM6358_CLK_ENET0	18
+#define BCM6358_CLK_ENET1	19
+#define BCM6358_CLK_USBSU	20
+#define BCM6358_CLK_EPHY	21
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */
diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h
new file mode 100644
index 0000000..d3770c5
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6362-clock.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6362_H
+#define __DT_BINDINGS_CLOCK_BCM6362_H
+
+#define BCM6362_CLK_GLESS	0
+#define BCM6362_CLK_ADSL_QPROC	1
+#define BCM6362_CLK_ADSL_AFE	2
+#define BCM6362_CLK_ADSL	3
+#define BCM6362_CLK_MIPS	4
+#define BCM6362_CLK_WLAN_OCP	5
+#define BCM6362_CLK_SWPKT_USB	7
+#define BCM6362_CLK_SWPKT_SAR	8
+#define BCM6362_CLK_SAR		9
+#define BCM6362_CLK_ROBOSW	10
+#define BCM6362_CLK_PCM		11
+#define BCM6362_CLK_USBD	12
+#define BCM6362_CLK_USBH	13
+#define BCM6362_CLK_IPSEC	14
+#define BCM6362_CLK_SPI		15
+#define BCM6362_CLK_HSSPI	16
+#define BCM6362_CLK_PCIE	17
+#define BCM6362_CLK_FAP		18
+#define BCM6362_CLK_PHYMIPS	19
+#define BCM6362_CLK_NAND	20
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */
diff --git a/include/dt-bindings/clock/bcm6368-clock.h b/include/dt-bindings/clock/bcm6368-clock.h
new file mode 100644
index 0000000..0c85782
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6368-clock.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6368_H
+#define __DT_BINDINGS_CLOCK_BCM6368_H
+
+#define BCM6368_CLK_VDSL_QPROC		2
+#define BCM6368_CLK_VDSL_AFE		3
+#define BCM6368_CLK_VDSL_BONDING	4
+#define BCM6368_CLK_VDSL		5
+#define BCM6368_CLK_PHYMIPS		6
+#define BCM6368_CLK_SWPKT_USB		7
+#define BCM6368_CLK_SWPKT_SAR		8
+#define BCM6368_CLK_SPI			9
+#define BCM6368_CLK_USBD		10
+#define BCM6368_CLK_SAR			11
+#define BCM6368_CLK_ROBOSW		12
+#define BCM6368_CLK_UTOPIA		13
+#define BCM6368_CLK_PCM			14
+#define BCM6368_CLK_USBH		15
+#define BCM6368_CLK_GLESS		16
+#define BCM6368_CLK_NAND		17
+#define BCM6368_CLK_IPSEC		18
+#define BCM6368_CLK_USBH_IDDQ		19
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */
diff --git a/include/dt-bindings/clock/boston-clock.h b/include/dt-bindings/clock/boston-clock.h
new file mode 100644
index 0000000..0b39062
--- /dev/null
+++ b/include/dt-bindings/clock/boston-clock.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Imagination Technologies
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
+
+#define BOSTON_CLK_SYS 0
+#define BOSTON_CLK_CPU 1
+
+#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */
diff --git a/include/dt-bindings/clock/exynos7420-clk.h b/include/dt-bindings/clock/exynos7420-clk.h
new file mode 100644
index 0000000..10c5586
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7420-clk.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS			1
+#define DOUT_SCLK_BUS0_PLL		2
+#define DOUT_SCLK_BUS1_PLL		3
+#define DOUT_SCLK_CC_PLL		4
+#define DOUT_SCLK_MFC_PLL		5
+#define DOUT_ACLK_CCORE_133		6
+#define DOUT_ACLK_MSCL_532		7
+#define ACLK_MSCL_532			8
+#define DOUT_SCLK_AUD_PLL		9
+#define FOUT_AUD_PLL			10
+#define SCLK_AUD_PLL			11
+#define SCLK_MFC_PLL_B			12
+#define SCLK_MFC_PLL_A			13
+#define SCLK_BUS1_PLL_B			14
+#define SCLK_BUS1_PLL_A			15
+#define SCLK_BUS0_PLL_B			16
+#define SCLK_BUS0_PLL_A			17
+#define SCLK_CC_PLL_B			18
+#define SCLK_CC_PLL_A			19
+#define ACLK_CCORE_133			20
+#define ACLK_PERIS_66			21
+#define TOPC_NR_CLK			22
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1		1
+#define DOUT_ACLK_PERIC0		2
+#define CLK_SCLK_UART0			3
+#define CLK_SCLK_UART1			4
+#define CLK_SCLK_UART2			5
+#define CLK_SCLK_UART3			6
+#define CLK_SCLK_SPI0			7
+#define CLK_SCLK_SPI1			8
+#define CLK_SCLK_SPI2			9
+#define CLK_SCLK_SPI3			10
+#define CLK_SCLK_SPI4			11
+#define CLK_SCLK_SPDIF			12
+#define CLK_SCLK_PCM1			13
+#define CLK_SCLK_I2S1			14
+#define CLK_ACLK_PERIC0_66		15
+#define CLK_ACLK_PERIC1_66		16
+#define TOP0_NR_CLK			17
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200		1
+#define DOUT_ACLK_FSYS0_200		2
+#define DOUT_SCLK_MMC2			3
+#define DOUT_SCLK_MMC1			4
+#define DOUT_SCLK_MMC0			5
+#define CLK_SCLK_MMC2			6
+#define CLK_SCLK_MMC1			7
+#define CLK_SCLK_MMC0			8
+#define CLK_ACLK_FSYS0_200		9
+#define CLK_ACLK_FSYS1_200		10
+#define CLK_SCLK_PHY_FSYS1		11
+#define CLK_SCLK_PHY_FSYS1_26M		12
+#define MOUT_SCLK_UFSUNIPRO20		13
+#define DOUT_SCLK_UFSUNIPRO20		14
+#define CLK_SCLK_UFSUNIPRO20		15
+#define DOUT_SCLK_PHY_FSYS1		16
+#define DOUT_SCLK_PHY_FSYS1_26M		17
+#define TOP1_NR_CLK			18
+
+/* CCORE */
+#define PCLK_RTC			1
+#define CCORE_NR_CLK			2
+
+/* PERIC0 */
+#define PCLK_UART0			1
+#define SCLK_UART0			2
+#define PCLK_HSI2C0			3
+#define PCLK_HSI2C1			4
+#define PCLK_HSI2C4			5
+#define PCLK_HSI2C5			6
+#define PCLK_HSI2C9			7
+#define PCLK_HSI2C10			8
+#define PCLK_HSI2C11			9
+#define PCLK_PWM			10
+#define SCLK_PWM			11
+#define PCLK_ADCIF			12
+#define PERIC0_NR_CLK			13
+
+/* PERIC1 */
+#define PCLK_UART1			1
+#define PCLK_UART2			2
+#define PCLK_UART3			3
+#define SCLK_UART1			4
+#define SCLK_UART2			5
+#define SCLK_UART3			6
+#define PCLK_HSI2C2			7
+#define PCLK_HSI2C3			8
+#define PCLK_HSI2C6			9
+#define PCLK_HSI2C7			10
+#define PCLK_HSI2C8			11
+#define PCLK_SPI0			12
+#define PCLK_SPI1			13
+#define PCLK_SPI2			14
+#define PCLK_SPI3			15
+#define PCLK_SPI4			16
+#define SCLK_SPI0			17
+#define SCLK_SPI1			18
+#define SCLK_SPI2			19
+#define SCLK_SPI3			20
+#define SCLK_SPI4			21
+#define PCLK_I2S1			22
+#define PCLK_PCM1			23
+#define PCLK_SPDIF			24
+#define SCLK_I2S1			25
+#define SCLK_PCM1			26
+#define SCLK_SPDIF			27
+#define PERIC1_NR_CLK			28
+
+/* PERIS */
+#define PCLK_CHIPID			1
+#define SCLK_CHIPID			2
+#define PCLK_WDT			3
+#define PCLK_TMU			4
+#define SCLK_TMU			5
+#define PERIS_NR_CLK			6
+
+/* FSYS0 */
+#define ACLK_MMC2			1
+#define ACLK_AXIUS_USBDRD30X_FSYS0X	2
+#define ACLK_USBDRD300			3
+#define SCLK_USBDRD300_SUSPENDCLK	4
+#define SCLK_USBDRD300_REFCLK		5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY		8
+#define ACLK_PDMA0			9
+#define ACLK_PDMA1			10
+#define FSYS0_NR_CLK			11
+
+/* FSYS1 */
+#define ACLK_MMC1			1
+#define ACLK_MMC0			2
+#define PHYCLK_UFS20_TX0_SYMBOL		3
+#define PHYCLK_UFS20_RX0_SYMBOL		4
+#define PHYCLK_UFS20_RX1_SYMBOL		5
+#define ACLK_UFS20_LINK			6
+#define SCLK_UFSUNIPRO20_USER		7
+#define PHYCLK_UFS20_RX1_SYMBOL_USER	8
+#define PHYCLK_UFS20_RX0_SYMBOL_USER	9
+#define PHYCLK_UFS20_TX0_SYMBOL_USER	10
+#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY	11
+#define SCLK_COMBO_PHY_EMBEDDED_26M	12
+#define DOUT_PCLK_FSYS1			13
+#define PCLK_GPIO_FSYS1			14
+#define MOUT_FSYS1_PHYCLK_SEL1		15
+#define FSYS1_NR_CLK			16
+
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532		1
+#define DOUT_PCLK_MSCL			2
+#define ACLK_MSCL_0			3
+#define ACLK_MSCL_1			4
+#define ACLK_JPEG			5
+#define ACLK_G2D			6
+#define ACLK_LH_ASYNC_SI_MSCL_0		7
+#define ACLK_LH_ASYNC_SI_MSCL_1		8
+#define ACLK_AXI2ACEL_BRIDGE		9
+#define ACLK_XIU_MSCLX_0		10
+#define ACLK_XIU_MSCLX_1		11
+#define ACLK_QE_MSCL_0			12
+#define ACLK_QE_MSCL_1			13
+#define ACLK_QE_JPEG			14
+#define ACLK_QE_G2D			15
+#define ACLK_PPMU_MSCL_0		16
+#define ACLK_PPMU_MSCL_1		17
+#define ACLK_MSCLNP_133			18
+#define ACLK_AHB2APB_MSCL0P		19
+#define ACLK_AHB2APB_MSCL1P		20
+
+#define PCLK_MSCL_0			21
+#define PCLK_MSCL_1			22
+#define PCLK_JPEG			23
+#define PCLK_G2D			24
+#define PCLK_QE_MSCL_0			25
+#define PCLK_QE_MSCL_1			26
+#define PCLK_QE_JPEG			27
+#define PCLK_QE_G2D			28
+#define PCLK_PPMU_MSCL_0		29
+#define PCLK_PPMU_MSCL_1		30
+#define PCLK_AXI2ACEL_BRIDGE		31
+#define PCLK_PMU_MSCL			32
+#define MSCL_NR_CLK			33
+
+/* AUD */
+#define SCLK_I2S			1
+#define SCLK_PCM			2
+#define PCLK_I2S			3
+#define PCLK_PCM			4
+#define ACLK_ADMA			5
+#define AUD_NR_CLK			6
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h
new file mode 100644
index 0000000..e916e49
--- /dev/null
+++ b/include/dt-bindings/clock/g12a-aoclkc.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
+
+#define CLKID_AO_AHB		0
+#define CLKID_AO_IR_IN		1
+#define CLKID_AO_I2C_M0		2
+#define CLKID_AO_I2C_S0		3
+#define CLKID_AO_UART		4
+#define CLKID_AO_PROD_I2C	5
+#define CLKID_AO_UART2		6
+#define CLKID_AO_IR_OUT		7
+#define CLKID_AO_SAR_ADC	8
+#define CLKID_AO_MAILBOX	9
+#define CLKID_AO_M3		10
+#define CLKID_AO_AHB_SRAM	11
+#define CLKID_AO_RTI		12
+#define CLKID_AO_M4_FCLK	13
+#define CLKID_AO_M4_HCLK	14
+#define CLKID_AO_CLK81		15
+#define CLKID_AO_SAR_ADC_SEL	16
+#define CLKID_AO_SAR_ADC_CLK	18
+#define CLKID_AO_CTS_OSCIN	19
+#define CLKID_AO_32K		23
+#define CLKID_AO_CEC		27
+#define CLKID_AO_CTS_RTC_OSCIN	28
+
+#endif
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
new file mode 100644
index 0000000..0837c1a
--- /dev/null
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * Meson-G12A clock tree IDs
+ *
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __G12A_CLKC_H
+#define __G12A_CLKC_H
+
+#define CLKID_SYS_PLL				0
+#define CLKID_FIXED_PLL				1
+#define CLKID_FCLK_DIV2				2
+#define CLKID_FCLK_DIV3				3
+#define CLKID_FCLK_DIV4				4
+#define CLKID_FCLK_DIV5				5
+#define CLKID_FCLK_DIV7				6
+#define CLKID_GP0_PLL				7
+#define CLKID_CLK81				10
+#define CLKID_MPLL0				11
+#define CLKID_MPLL1				12
+#define CLKID_MPLL2				13
+#define CLKID_MPLL3				14
+#define CLKID_DDR				15
+#define CLKID_DOS				16
+#define CLKID_AUDIO_LOCKER			17
+#define CLKID_MIPI_DSI_HOST			18
+#define CLKID_ETH_PHY				19
+#define CLKID_ISA				20
+#define CLKID_PL301				21
+#define CLKID_PERIPHS				22
+#define CLKID_SPICC0				23
+#define CLKID_I2C				24
+#define CLKID_SANA				25
+#define CLKID_SD				26
+#define CLKID_RNG0				27
+#define CLKID_UART0				28
+#define CLKID_SPICC1				29
+#define CLKID_HIU_IFACE				30
+#define CLKID_MIPI_DSI_PHY			31
+#define CLKID_ASSIST_MISC			32
+#define CLKID_SD_EMMC_A				33
+#define CLKID_SD_EMMC_B				34
+#define CLKID_SD_EMMC_C				35
+#define CLKID_AUDIO_CODEC			36
+#define CLKID_AUDIO				37
+#define CLKID_ETH				38
+#define CLKID_DEMUX				39
+#define CLKID_AUDIO_IFIFO			40
+#define CLKID_ADC				41
+#define CLKID_UART1				42
+#define CLKID_G2D				43
+#define CLKID_RESET				44
+#define CLKID_PCIE_COMB				45
+#define CLKID_PARSER				46
+#define CLKID_USB				47
+#define CLKID_PCIE_PHY				48
+#define CLKID_AHB_ARB0				49
+#define CLKID_AHB_DATA_BUS			50
+#define CLKID_AHB_CTRL_BUS			51
+#define CLKID_HTX_HDCP22			52
+#define CLKID_HTX_PCLK				53
+#define CLKID_BT656				54
+#define CLKID_USB1_DDR_BRIDGE			55
+#define CLKID_MMC_PCLK				56
+#define CLKID_UART2				57
+#define CLKID_VPU_INTR				58
+#define CLKID_GIC				59
+#define CLKID_SD_EMMC_A_CLK0			60
+#define CLKID_SD_EMMC_B_CLK0			61
+#define CLKID_SD_EMMC_C_CLK0			62
+#define CLKID_HIFI_PLL				74
+#define CLKID_VCLK2_VENCI0			80
+#define CLKID_VCLK2_VENCI1			81
+#define CLKID_VCLK2_VENCP0			82
+#define CLKID_VCLK2_VENCP1			83
+#define CLKID_VCLK2_VENCT0			84
+#define CLKID_VCLK2_VENCT1			85
+#define CLKID_VCLK2_OTHER			86
+#define CLKID_VCLK2_ENCI			87
+#define CLKID_VCLK2_ENCP			88
+#define CLKID_DAC_CLK				89
+#define CLKID_AOCLK				90
+#define CLKID_IEC958				91
+#define CLKID_ENC480P				92
+#define CLKID_RNG1				93
+#define CLKID_VCLK2_ENCT			94
+#define CLKID_VCLK2_ENCL			95
+#define CLKID_VCLK2_VENCLMMC			96
+#define CLKID_VCLK2_VENCL			97
+#define CLKID_VCLK2_OTHER1			98
+#define CLKID_FCLK_DIV2P5			99
+#define CLKID_DMA				105
+#define CLKID_EFUSE				106
+#define CLKID_ROM_BOOT				107
+#define CLKID_RESET_SEC				108
+#define CLKID_SEC_AHB_APB3			109
+#define CLKID_VPU_0_SEL				110
+#define CLKID_VPU_0				112
+#define CLKID_VPU_1_SEL				113
+#define CLKID_VPU_1				115
+#define CLKID_VPU				116
+#define CLKID_VAPB_0_SEL			117
+#define CLKID_VAPB_0				119
+#define CLKID_VAPB_1_SEL			120
+#define CLKID_VAPB_1				122
+#define CLKID_VAPB_SEL				123
+#define CLKID_VAPB				124
+#define CLKID_HDMI_PLL				128
+#define CLKID_VID_PLL				129
+#define CLKID_VCLK				138
+#define CLKID_VCLK2				139
+#define CLKID_VCLK_DIV1				148
+#define CLKID_VCLK_DIV2				149
+#define CLKID_VCLK_DIV4				150
+#define CLKID_VCLK_DIV6				151
+#define CLKID_VCLK_DIV12			152
+#define CLKID_VCLK2_DIV1			153
+#define CLKID_VCLK2_DIV2			154
+#define CLKID_VCLK2_DIV4			155
+#define CLKID_VCLK2_DIV6			156
+#define CLKID_VCLK2_DIV12			157
+#define CLKID_CTS_ENCI				162
+#define CLKID_CTS_ENCP				163
+#define CLKID_CTS_VDAC				164
+#define CLKID_HDMI_TX				165
+#define CLKID_HDMI				168
+#define CLKID_MALI_0_SEL			169
+#define CLKID_MALI_0				171
+#define CLKID_MALI_1_SEL			172
+#define CLKID_MALI_1				174
+#define CLKID_MALI				175
+#define CLKID_MPLL_50M				177
+#define CLKID_CPU_CLK				187
+#define CLKID_PCIE_PLL				201
+#define CLKID_VDEC_1				204
+#define CLKID_VDEC_HEVC				207
+#define CLKID_VDEC_HEVCF			210
+#define CLKID_TS				212
+#define CLKID_CPUB_CLK				224
+#define CLKID_GP1_PLL				243
+#define CLKID_DSU_CLK				252
+#define CLKID_CPU1_CLK				253
+#define CLKID_CPU2_CLK				254
+#define CLKID_CPU3_CLK				255
+
+#endif /* __G12A_CLKC_H */
diff --git a/include/dt-bindings/clock/gxbb-aoclkc.h b/include/dt-bindings/clock/gxbb-aoclkc.h
new file mode 100644
index 0000000..9d15e22
--- /dev/null
+++ b/include/dt-bindings/clock/gxbb-aoclkc.h
@@ -0,0 +1,67 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution
+ * in the file called COPYING.
+ *
+ * BSD LICENSE
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_GXBB_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_CEC_32K	6
+
+#endif
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
new file mode 100644
index 0000000..8ba99a5
--- /dev/null
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * GXBB clock tree IDs
+ */
+
+#ifndef __GXBB_CLKC_H
+#define __GXBB_CLKC_H
+
+#define CLKID_SYS_PLL		0
+#define CLKID_HDMI_PLL		2
+#define CLKID_FIXED_PLL		3
+#define CLKID_FCLK_DIV2		4
+#define CLKID_FCLK_DIV3		5
+#define CLKID_FCLK_DIV4		6
+#define CLKID_FCLK_DIV5		7
+#define CLKID_FCLK_DIV7		8
+#define CLKID_GP0_PLL		9
+#define CLKID_CLK81		12
+#define CLKID_MPLL0		13
+#define CLKID_MPLL1		14
+#define CLKID_MPLL2		15
+#define CLKID_DDR		16
+#define CLKID_DOS		17
+#define CLKID_ISA		18
+#define CLKID_PL301		19
+#define CLKID_PERIPHS		20
+#define CLKID_SPICC		21
+#define CLKID_I2C		22
+#define CLKID_SAR_ADC		23
+#define CLKID_SMART_CARD	24
+#define CLKID_RNG0		25
+#define CLKID_UART0		26
+#define CLKID_SDHC		27
+#define CLKID_STREAM		28
+#define CLKID_ASYNC_FIFO	29
+#define CLKID_SDIO		30
+#define CLKID_ABUF		31
+#define CLKID_HIU_IFACE		32
+#define CLKID_ASSIST_MISC	33
+#define CLKID_SPI		34
+#define CLKID_ETH		36
+#define CLKID_I2S_SPDIF		35
+#define CLKID_DEMUX		37
+#define CLKID_AIU_GLUE		38
+#define CLKID_IEC958		39
+#define CLKID_I2S_OUT		40
+#define CLKID_AMCLK		41
+#define CLKID_AIFIFO2		42
+#define CLKID_MIXER		43
+#define CLKID_MIXER_IFACE	44
+#define CLKID_ADC		45
+#define CLKID_BLKMV		46
+#define CLKID_AIU		47
+#define CLKID_UART1		48
+#define CLKID_G2D		49
+#define CLKID_USB0		50
+#define CLKID_USB1		51
+#define CLKID_RESET		52
+#define CLKID_NAND		53
+#define CLKID_DOS_PARSER	54
+#define CLKID_USB		55
+#define CLKID_VDIN1		56
+#define CLKID_AHB_ARB0		57
+#define CLKID_EFUSE		58
+#define CLKID_BOOT_ROM		59
+#define CLKID_AHB_DATA_BUS	60
+#define CLKID_AHB_CTRL_BUS	61
+#define CLKID_HDMI_INTR_SYNC	62
+#define CLKID_HDMI_PCLK		63
+#define CLKID_USB1_DDR_BRIDGE	64
+#define CLKID_USB0_DDR_BRIDGE	65
+#define CLKID_MMC_PCLK		66
+#define CLKID_DVIN		67
+#define CLKID_UART2		68
+#define CLKID_SANA		69
+#define CLKID_VPU_INTR		70
+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
+#define CLKID_CLK81_A53		72
+#define CLKID_VCLK2_VENCI0	73
+#define CLKID_VCLK2_VENCI1	74
+#define CLKID_VCLK2_VENCP0	75
+#define CLKID_VCLK2_VENCP1	76
+#define CLKID_GCLK_VENCI_INT0	77
+#define CLKID_GCLK_VENCI_INT	78
+#define CLKID_DAC_CLK		79
+#define CLKID_AOCLK_GATE	80
+#define CLKID_IEC958_GATE	81
+#define CLKID_ENC480P		82
+#define CLKID_RNG1		83
+#define CLKID_GCLK_VENCI_INT1	84
+#define CLKID_VCLK2_VENCLMCC	85
+#define CLKID_VCLK2_VENCL	86
+#define CLKID_VCLK_OTHER	87
+#define CLKID_EDP		88
+#define CLKID_AO_MEDIA_CPU	89
+#define CLKID_AO_AHB_SRAM	90
+#define CLKID_AO_AHB_BUS	91
+#define CLKID_AO_IFACE		92
+#define CLKID_AO_I2C		93
+#define CLKID_SD_EMMC_A		94
+#define CLKID_SD_EMMC_B		95
+#define CLKID_SD_EMMC_C		96
+#define CLKID_SAR_ADC_CLK	97
+#define CLKID_SAR_ADC_SEL	98
+#define CLKID_MALI_0_SEL	100
+#define CLKID_MALI_0		102
+#define CLKID_MALI_1_SEL	103
+#define CLKID_MALI_1		105
+#define CLKID_MALI		106
+#define CLKID_CTS_AMCLK		107
+#define CLKID_CTS_MCLK_I958	110
+#define CLKID_CTS_I958		113
+#define CLKID_32K_CLK		114
+#define CLKID_SD_EMMC_A_CLK0	119
+#define CLKID_SD_EMMC_B_CLK0	122
+#define CLKID_SD_EMMC_C_CLK0	125
+#define CLKID_VPU_0_SEL		126
+#define CLKID_VPU_0		128
+#define CLKID_VPU_1_SEL		129
+#define CLKID_VPU_1		131
+#define CLKID_VPU		132
+#define CLKID_VAPB_0_SEL	133
+#define CLKID_VAPB_0		135
+#define CLKID_VAPB_1_SEL	136
+#define CLKID_VAPB_1		138
+#define CLKID_VAPB_SEL		139
+#define CLKID_VAPB		140
+
+#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h
new file mode 100644
index 0000000..e1374e1
--- /dev/null
+++ b/include/dt-bindings/clock/hi3660-clock.h
@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ */
+
+#ifndef __DTS_HI3660_CLOCK_H
+#define __DTS_HI3660_CLOCK_H
+
+/* fixed rate clocks */
+#define HI3660_CLKIN_SYS		0
+#define HI3660_CLKIN_REF		1
+#define HI3660_CLK_FLL_SRC		2
+#define HI3660_CLK_PPLL0		3
+#define HI3660_CLK_PPLL1		4
+#define HI3660_CLK_PPLL2		5
+#define HI3660_CLK_PPLL3		6
+#define HI3660_CLK_SCPLL		7
+#define HI3660_PCLK			8
+#define HI3660_CLK_UART0_DBG		9
+#define HI3660_CLK_UART6		10
+#define HI3660_OSC32K			11
+#define HI3660_OSC19M			12
+#define HI3660_CLK_480M			13
+#define HI3660_CLK_INV			14
+
+/* clk in crgctrl */
+#define HI3660_FACTOR_UART3		15
+#define HI3660_CLK_FACTOR_MMC		16
+#define HI3660_CLK_GATE_I2C0		17
+#define HI3660_CLK_GATE_I2C1		18
+#define HI3660_CLK_GATE_I2C2		19
+#define HI3660_CLK_GATE_I2C6		20
+#define HI3660_CLK_DIV_SYSBUS		21
+#define HI3660_CLK_DIV_320M		22
+#define HI3660_CLK_DIV_A53		23
+#define HI3660_CLK_GATE_SPI0		24
+#define HI3660_CLK_GATE_SPI2		25
+#define HI3660_PCIEPHY_REF		26
+#define HI3660_CLK_ABB_USB		27
+#define HI3660_HCLK_GATE_SDIO0		28
+#define HI3660_HCLK_GATE_SD		29
+#define HI3660_CLK_GATE_AOMM		30
+#define HI3660_PCLK_GPIO0		31
+#define HI3660_PCLK_GPIO1		32
+#define HI3660_PCLK_GPIO2		33
+#define HI3660_PCLK_GPIO3		34
+#define HI3660_PCLK_GPIO4		35
+#define HI3660_PCLK_GPIO5		36
+#define HI3660_PCLK_GPIO6		37
+#define HI3660_PCLK_GPIO7		38
+#define HI3660_PCLK_GPIO8		39
+#define HI3660_PCLK_GPIO9		40
+#define HI3660_PCLK_GPIO10		41
+#define HI3660_PCLK_GPIO11		42
+#define HI3660_PCLK_GPIO12		43
+#define HI3660_PCLK_GPIO13		44
+#define HI3660_PCLK_GPIO14		45
+#define HI3660_PCLK_GPIO15		46
+#define HI3660_PCLK_GPIO16		47
+#define HI3660_PCLK_GPIO17		48
+#define HI3660_PCLK_GPIO18		49
+#define HI3660_PCLK_GPIO19		50
+#define HI3660_PCLK_GPIO20		51
+#define HI3660_PCLK_GPIO21		52
+#define HI3660_CLK_GATE_SPI3		53
+#define HI3660_CLK_GATE_I2C7		54
+#define HI3660_CLK_GATE_I2C3		55
+#define HI3660_CLK_GATE_SPI1		56
+#define HI3660_CLK_GATE_UART1		57
+#define HI3660_CLK_GATE_UART2		58
+#define HI3660_CLK_GATE_UART4		59
+#define HI3660_CLK_GATE_UART5		60
+#define HI3660_CLK_GATE_I2C4		61
+#define HI3660_CLK_GATE_DMAC		62
+#define HI3660_PCLK_GATE_DSS		63
+#define HI3660_ACLK_GATE_DSS		64
+#define HI3660_CLK_GATE_LDI1		65
+#define HI3660_CLK_GATE_LDI0		66
+#define HI3660_CLK_GATE_VIVOBUS		67
+#define HI3660_CLK_GATE_EDC0		68
+#define HI3660_CLK_GATE_TXDPHY0_CFG	69
+#define HI3660_CLK_GATE_TXDPHY0_REF	70
+#define HI3660_CLK_GATE_TXDPHY1_CFG	71
+#define HI3660_CLK_GATE_TXDPHY1_REF	72
+#define HI3660_ACLK_GATE_USB3OTG	73
+#define HI3660_CLK_GATE_SPI4		74
+#define HI3660_CLK_GATE_SD		75
+#define HI3660_CLK_GATE_SDIO0		76
+#define HI3660_CLK_GATE_UFS_SUBSYS	77
+#define HI3660_PCLK_GATE_DSI0		78
+#define HI3660_PCLK_GATE_DSI1		79
+#define HI3660_ACLK_GATE_PCIE		80
+#define HI3660_PCLK_GATE_PCIE_SYS       81
+#define HI3660_CLK_GATE_PCIEAUX		82
+#define HI3660_PCLK_GATE_PCIE_PHY	83
+#define HI3660_CLK_ANDGT_LDI0		84
+#define HI3660_CLK_ANDGT_LDI1		85
+#define HI3660_CLK_ANDGT_EDC0		86
+#define HI3660_CLK_GATE_UFSPHY_GT	87
+#define HI3660_CLK_ANDGT_MMC		88
+#define HI3660_CLK_ANDGT_SD		89
+#define HI3660_CLK_A53HPM_ANDGT		90
+#define HI3660_CLK_ANDGT_SDIO		91
+#define HI3660_CLK_ANDGT_UART0		92
+#define HI3660_CLK_ANDGT_UART1		93
+#define HI3660_CLK_ANDGT_UARTH		94
+#define HI3660_CLK_ANDGT_SPI		95
+#define HI3660_CLK_VIVOBUS_ANDGT	96
+#define HI3660_CLK_AOMM_ANDGT		97
+#define HI3660_CLK_320M_PLL_GT		98
+#define HI3660_AUTODIV_EMMC0BUS		99
+#define HI3660_AUTODIV_SYSBUS		100
+#define HI3660_CLK_GATE_UFSPHY_CFG	101
+#define HI3660_CLK_GATE_UFSIO_REF	102
+#define HI3660_CLK_MUX_SYSBUS		103
+#define HI3660_CLK_MUX_UART0		104
+#define HI3660_CLK_MUX_UART1		105
+#define HI3660_CLK_MUX_UARTH		106
+#define HI3660_CLK_MUX_SPI		107
+#define HI3660_CLK_MUX_I2C		108
+#define HI3660_CLK_MUX_MMC_PLL		109
+#define HI3660_CLK_MUX_LDI1		110
+#define HI3660_CLK_MUX_LDI0		111
+#define HI3660_CLK_MUX_SD_PLL		112
+#define HI3660_CLK_MUX_SD_SYS		113
+#define HI3660_CLK_MUX_EDC0		114
+#define HI3660_CLK_MUX_SDIO_SYS		115
+#define HI3660_CLK_MUX_SDIO_PLL		116
+#define HI3660_CLK_MUX_VIVOBUS		117
+#define HI3660_CLK_MUX_A53HPM		118
+#define HI3660_CLK_MUX_320M		119
+#define HI3660_CLK_MUX_IOPERI		120
+#define HI3660_CLK_DIV_UART0		121
+#define HI3660_CLK_DIV_UART1		122
+#define HI3660_CLK_DIV_UARTH		123
+#define HI3660_CLK_DIV_MMC		124
+#define HI3660_CLK_DIV_SD		125
+#define HI3660_CLK_DIV_EDC0		126
+#define HI3660_CLK_DIV_LDI0		127
+#define HI3660_CLK_DIV_SDIO		128
+#define HI3660_CLK_DIV_LDI1		129
+#define HI3660_CLK_DIV_SPI		130
+#define HI3660_CLK_DIV_VIVOBUS		131
+#define HI3660_CLK_DIV_I2C		132
+#define HI3660_CLK_DIV_UFSPHY		133
+#define HI3660_CLK_DIV_CFGBUS		134
+#define HI3660_CLK_DIV_MMC0BUS		135
+#define HI3660_CLK_DIV_MMC1BUS		136
+#define HI3660_CLK_DIV_UFSPERI		137
+#define HI3660_CLK_DIV_AOMM		138
+#define HI3660_CLK_DIV_IOPERI		139
+#define HI3660_VENC_VOLT_HOLD		140
+#define HI3660_PERI_VOLT_HOLD		141
+#define HI3660_CLK_GATE_VENC		142
+#define HI3660_CLK_GATE_VDEC		143
+#define HI3660_CLK_ANDGT_VENC		144
+#define HI3660_CLK_ANDGT_VDEC		145
+#define HI3660_CLK_MUX_VENC		146
+#define HI3660_CLK_MUX_VDEC		147
+#define HI3660_CLK_DIV_VENC		148
+#define HI3660_CLK_DIV_VDEC		149
+#define HI3660_CLK_FAC_ISP_SNCLK	150
+#define HI3660_CLK_GATE_ISP_SNCLK0	151
+#define HI3660_CLK_GATE_ISP_SNCLK1	152
+#define HI3660_CLK_GATE_ISP_SNCLK2	153
+#define HI3660_CLK_ANGT_ISP_SNCLK	154
+#define HI3660_CLK_MUX_ISP_SNCLK	155
+#define HI3660_CLK_DIV_ISP_SNCLK	156
+
+/* clk in pmuctrl */
+#define HI3660_GATE_ABB_192		0
+
+/* clk in pctrl */
+#define HI3660_GATE_UFS_TCXO_EN		0
+#define HI3660_GATE_USB_TCXO_EN		1
+
+/* clk in sctrl */
+#define HI3660_PCLK_AO_GPIO0		0
+#define HI3660_PCLK_AO_GPIO1		1
+#define HI3660_PCLK_AO_GPIO2		2
+#define HI3660_PCLK_AO_GPIO3		3
+#define HI3660_PCLK_AO_GPIO4		4
+#define HI3660_PCLK_AO_GPIO5		5
+#define HI3660_PCLK_AO_GPIO6		6
+#define HI3660_PCLK_GATE_MMBUF		7
+#define HI3660_CLK_GATE_DSS_AXI_MM	8
+#define HI3660_PCLK_MMBUF_ANDGT		9
+#define HI3660_CLK_MMBUF_PLL_ANDGT	10
+#define HI3660_CLK_FLL_MMBUF_ANDGT	11
+#define HI3660_CLK_SYS_MMBUF_ANDGT	12
+#define HI3660_CLK_GATE_PCIEPHY_GT	13
+#define HI3660_ACLK_MUX_MMBUF		14
+#define HI3660_CLK_SW_MMBUF		15
+#define HI3660_CLK_DIV_AOBUS		16
+#define HI3660_PCLK_DIV_MMBUF		17
+#define HI3660_ACLK_DIV_MMBUF		18
+#define HI3660_CLK_DIV_PCIEPHY		19
+
+/* clk in iomcu */
+#define HI3660_CLK_I2C0_IOMCU		0
+#define HI3660_CLK_I2C1_IOMCU		1
+#define HI3660_CLK_I2C2_IOMCU		2
+#define HI3660_CLK_I2C6_IOMCU		3
+#define HI3660_CLK_IOMCU_PERI0		4
+
+/* clk in stub clock */
+#define HI3660_CLK_STUB_CLUSTER0	0
+#define HI3660_CLK_STUB_CLUSTER1	1
+#define HI3660_CLK_STUB_GPU		2
+#define HI3660_CLK_STUB_DDR		3
+#define HI3660_CLK_STUB_NUM		4
+
+#endif	/* __DTS_HI3660_CLOCK_H */
diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h
new file mode 100644
index 0000000..70ee383
--- /dev/null
+++ b/include/dt-bindings/clock/hi6220-clock.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Bintian Wang <bintian.wang@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_HI6220_H
+#define __DT_BINDINGS_CLOCK_HI6220_H
+
+/* clk in Hi6220 AO (always on) controller */
+#define HI6220_NONE_CLOCK	0
+
+/* fixed rate clocks */
+#define HI6220_REF32K		1
+#define HI6220_CLK_TCXO		2
+#define HI6220_MMC1_PAD		3
+#define HI6220_MMC2_PAD		4
+#define HI6220_MMC0_PAD		5
+#define HI6220_PLL_BBP		6
+#define HI6220_PLL_GPU		7
+#define HI6220_PLL1_DDR		8
+#define HI6220_PLL_SYS		9
+#define HI6220_PLL_SYS_MEDIA	10
+#define HI6220_DDR_SRC		11
+#define HI6220_PLL_MEDIA	12
+#define HI6220_PLL_DDR		13
+
+/* fixed factor clocks */
+#define HI6220_300M		14
+#define HI6220_150M		15
+#define HI6220_PICOPHY_SRC	16
+#define HI6220_MMC0_SRC_SEL	17
+#define HI6220_MMC1_SRC_SEL	18
+#define HI6220_MMC2_SRC_SEL	19
+#define HI6220_VPU_CODEC	20
+#define HI6220_MMC0_SMP		21
+#define HI6220_MMC1_SMP		22
+#define HI6220_MMC2_SMP		23
+
+/* gate clocks */
+#define HI6220_WDT0_PCLK	24
+#define HI6220_WDT1_PCLK	25
+#define HI6220_WDT2_PCLK	26
+#define HI6220_TIMER0_PCLK	27
+#define HI6220_TIMER1_PCLK	28
+#define HI6220_TIMER2_PCLK	29
+#define HI6220_TIMER3_PCLK	30
+#define HI6220_TIMER4_PCLK	31
+#define HI6220_TIMER5_PCLK	32
+#define HI6220_TIMER6_PCLK	33
+#define HI6220_TIMER7_PCLK	34
+#define HI6220_TIMER8_PCLK	35
+#define HI6220_UART0_PCLK	36
+
+#define HI6220_AO_NR_CLKS	37
+
+/* clk in Hi6220 systrl */
+/* gate clock */
+#define HI6220_MMC0_CLK		1
+#define HI6220_MMC0_CIUCLK	2
+#define HI6220_MMC1_CLK		3
+#define HI6220_MMC1_CIUCLK	4
+#define HI6220_MMC2_CLK		5
+#define HI6220_MMC2_CIUCLK	6
+#define HI6220_USBOTG_HCLK	7
+#define HI6220_CLK_PICOPHY	8
+#define HI6220_HIFI		9
+#define HI6220_DACODEC_PCLK	10
+#define HI6220_EDMAC_ACLK	11
+#define HI6220_CS_ATB		12
+#define HI6220_I2C0_CLK		13
+#define HI6220_I2C1_CLK		14
+#define HI6220_I2C2_CLK		15
+#define HI6220_I2C3_CLK		16
+#define HI6220_UART1_PCLK	17
+#define HI6220_UART2_PCLK	18
+#define HI6220_UART3_PCLK	19
+#define HI6220_UART4_PCLK	20
+#define HI6220_SPI_CLK		21
+#define HI6220_TSENSOR_CLK	22
+#define HI6220_MMU_CLK		23
+#define HI6220_HIFI_SEL		24
+#define HI6220_MMC0_SYSPLL	25
+#define HI6220_MMC1_SYSPLL	26
+#define HI6220_MMC2_SYSPLL	27
+#define HI6220_MMC0_SEL		28
+#define HI6220_MMC1_SEL		29
+#define HI6220_BBPPLL_SEL	30
+#define HI6220_MEDIA_PLL_SRC	31
+#define HI6220_MMC2_SEL		32
+#define HI6220_CS_ATB_SYSPLL	33
+
+/* mux clocks */
+#define HI6220_MMC0_SRC		34
+#define HI6220_MMC0_SMP_IN	35
+#define HI6220_MMC1_SRC		36
+#define HI6220_MMC1_SMP_IN	37
+#define HI6220_MMC2_SRC		38
+#define HI6220_MMC2_SMP_IN	39
+#define HI6220_HIFI_SRC		40
+#define HI6220_UART1_SRC	41
+#define HI6220_UART2_SRC	42
+#define HI6220_UART3_SRC	43
+#define HI6220_UART4_SRC	44
+#define HI6220_MMC0_MUX0	45
+#define HI6220_MMC1_MUX0	46
+#define HI6220_MMC2_MUX0	47
+#define HI6220_MMC0_MUX1	48
+#define HI6220_MMC1_MUX1	49
+#define HI6220_MMC2_MUX1	50
+
+/* divider clocks */
+#define HI6220_CLK_BUS		51
+#define HI6220_MMC0_DIV		52
+#define HI6220_MMC1_DIV		53
+#define HI6220_MMC2_DIV		54
+#define HI6220_HIFI_DIV		55
+#define HI6220_BBPPLL0_DIV	56
+#define HI6220_CS_DAPB		57
+#define HI6220_CS_ATB_DIV	58
+
+#define HI6220_SYS_NR_CLKS	59
+
+/* clk in Hi6220 media controller */
+/* gate clocks */
+#define HI6220_DSI_PCLK		1
+#define HI6220_G3D_PCLK		2
+#define HI6220_ACLK_CODEC_VPU	3
+#define HI6220_ISP_SCLK		4
+#define HI6220_ADE_CORE		5
+#define HI6220_MED_MMU		6
+#define HI6220_CFG_CSI4PHY	7
+#define HI6220_CFG_CSI2PHY	8
+#define HI6220_ISP_SCLK_GATE	9
+#define HI6220_ISP_SCLK_GATE1	10
+#define HI6220_ADE_CORE_GATE	11
+#define HI6220_CODEC_VPU_GATE	12
+#define HI6220_MED_SYSPLL	13
+
+/* mux clocks */
+#define HI6220_1440_1200	14
+#define HI6220_1000_1200	15
+#define HI6220_1000_1440	16
+
+/* divider clocks */
+#define HI6220_CODEC_JPEG	17
+#define HI6220_ISP_SCLK_SRC	18
+#define HI6220_ISP_SCLK1	19
+#define HI6220_ADE_CORE_SRC	20
+#define HI6220_ADE_PIX_SRC	21
+#define HI6220_G3D_CLK		22
+#define HI6220_CODEC_VPU_SRC	23
+
+#define HI6220_MEDIA_NR_CLKS	24
+
+/* clk in Hi6220 power controller */
+/* gate clocks */
+#define HI6220_PLL_GPU_GATE	1
+#define HI6220_PLL1_DDR_GATE	2
+#define HI6220_PLL_DDR_GATE	3
+#define HI6220_PLL_MEDIA_GATE	4
+#define HI6220_PLL0_BBP_GATE	5
+
+/* divider clocks */
+#define HI6220_DDRC_SRC		6
+#define HI6220_DDRC_AXI1	7
+
+#define HI6220_POWER_NR_CLKS	8
+#endif
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
new file mode 100644
index 0000000..136de24
--- /dev/null
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HISTB_CLOCK_H
+#define __DTS_HISTB_CLOCK_H
+
+/* clocks provided by core CRG */
+#define HISTB_OSC_CLK			0
+#define HISTB_APB_CLK			1
+#define HISTB_AHB_CLK			2
+#define HISTB_UART1_CLK			3
+#define HISTB_UART2_CLK			4
+#define HISTB_UART3_CLK			5
+#define HISTB_I2C0_CLK			6
+#define HISTB_I2C1_CLK			7
+#define HISTB_I2C2_CLK			8
+#define HISTB_I2C3_CLK			9
+#define HISTB_I2C4_CLK			10
+#define HISTB_I2C5_CLK			11
+#define HISTB_SPI0_CLK			12
+#define HISTB_SPI1_CLK			13
+#define HISTB_SPI2_CLK			14
+#define HISTB_SCI_CLK			15
+#define HISTB_FMC_CLK			16
+#define HISTB_MMC_BIU_CLK		17
+#define HISTB_MMC_CIU_CLK		18
+#define HISTB_MMC_DRV_CLK		19
+#define HISTB_MMC_SAMPLE_CLK		20
+#define HISTB_SDIO0_BIU_CLK		21
+#define HISTB_SDIO0_CIU_CLK		22
+#define HISTB_SDIO0_DRV_CLK		23
+#define HISTB_SDIO0_SAMPLE_CLK		24
+#define HISTB_PCIE_AUX_CLK		25
+#define HISTB_PCIE_PIPE_CLK		26
+#define HISTB_PCIE_SYS_CLK		27
+#define HISTB_PCIE_BUS_CLK		28
+#define HISTB_ETH0_MAC_CLK		29
+#define HISTB_ETH0_MACIF_CLK		30
+#define HISTB_ETH1_MAC_CLK		31
+#define HISTB_ETH1_MACIF_CLK		32
+#define HISTB_COMBPHY1_CLK		33
+#define HISTB_USB2_BUS_CLK		34
+#define HISTB_USB2_PHY_CLK		35
+#define HISTB_USB2_UTMI_CLK		36
+#define HISTB_USB2_12M_CLK		37
+#define HISTB_USB2_48M_CLK		38
+#define HISTB_USB2_OTG_UTMI_CLK		39
+#define HISTB_USB2_PHY1_REF_CLK		40
+#define HISTB_USB2_PHY2_REF_CLK		41
+#define HISTB_COMBPHY0_CLK		42
+#define HISTB_USB3_BUS_CLK		43
+#define HISTB_USB3_UTMI_CLK		44
+#define HISTB_USB3_PIPE_CLK		45
+#define HISTB_USB3_SUSPEND_CLK		46
+#define HISTB_USB3_BUS_CLK1		47
+#define HISTB_USB3_UTMI_CLK1		48
+#define HISTB_USB3_PIPE_CLK1		49
+#define HISTB_USB3_SUSPEND_CLK1		50
+
+/* clocks provided by mcu CRG */
+#define HISTB_MCE_CLK			1
+#define HISTB_IR_CLK			2
+#define HISTB_TIMER01_CLK		3
+#define HISTB_LEDC_CLK			4
+#define HISTB_UART0_CLK			5
+#define HISTB_LSADC_CLK			6
+
+#endif	/* __DTS_HISTB_CLOCK_H */
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
new file mode 100644
index 0000000..d382fc7
--- /dev/null
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX5_H
+#define __DT_BINDINGS_CLOCK_IMX5_H
+
+#define IMX5_CLK_DUMMY			0
+#define IMX5_CLK_CKIL			1
+#define IMX5_CLK_OSC			2
+#define IMX5_CLK_CKIH1			3
+#define IMX5_CLK_CKIH2			4
+#define IMX5_CLK_AHB			5
+#define IMX5_CLK_IPG			6
+#define IMX5_CLK_AXI_A			7
+#define IMX5_CLK_AXI_B			8
+#define IMX5_CLK_UART_PRED		9
+#define IMX5_CLK_UART_ROOT		10
+#define IMX5_CLK_ESDHC_A_PRED		11
+#define IMX5_CLK_ESDHC_B_PRED		12
+#define IMX5_CLK_ESDHC_C_SEL		13
+#define IMX5_CLK_ESDHC_D_SEL		14
+#define IMX5_CLK_EMI_SEL		15
+#define IMX5_CLK_EMI_SLOW_PODF		16
+#define IMX5_CLK_NFC_PODF		17
+#define IMX5_CLK_ECSPI_PRED		18
+#define IMX5_CLK_ECSPI_PODF		19
+#define IMX5_CLK_USBOH3_PRED		20
+#define IMX5_CLK_USBOH3_PODF		21
+#define IMX5_CLK_USB_PHY_PRED		22
+#define IMX5_CLK_USB_PHY_PODF		23
+#define IMX5_CLK_CPU_PODF		24
+#define IMX5_CLK_DI_PRED		25
+#define IMX5_CLK_TVE_SEL		27
+#define IMX5_CLK_UART1_IPG_GATE		28
+#define IMX5_CLK_UART1_PER_GATE		29
+#define IMX5_CLK_UART2_IPG_GATE		30
+#define IMX5_CLK_UART2_PER_GATE		31
+#define IMX5_CLK_UART3_IPG_GATE		32
+#define IMX5_CLK_UART3_PER_GATE		33
+#define IMX5_CLK_I2C1_GATE		34
+#define IMX5_CLK_I2C2_GATE		35
+#define IMX5_CLK_GPT_IPG_GATE		36
+#define IMX5_CLK_PWM1_IPG_GATE		37
+#define IMX5_CLK_PWM1_HF_GATE		38
+#define IMX5_CLK_PWM2_IPG_GATE		39
+#define IMX5_CLK_PWM2_HF_GATE		40
+#define IMX5_CLK_GPT_HF_GATE		41
+#define IMX5_CLK_FEC_GATE		42
+#define IMX5_CLK_USBOH3_PER_GATE	43
+#define IMX5_CLK_ESDHC1_IPG_GATE	44
+#define IMX5_CLK_ESDHC2_IPG_GATE	45
+#define IMX5_CLK_ESDHC3_IPG_GATE	46
+#define IMX5_CLK_ESDHC4_IPG_GATE	47
+#define IMX5_CLK_SSI1_IPG_GATE		48
+#define IMX5_CLK_SSI2_IPG_GATE		49
+#define IMX5_CLK_SSI3_IPG_GATE		50
+#define IMX5_CLK_ECSPI1_IPG_GATE	51
+#define IMX5_CLK_ECSPI1_PER_GATE	52
+#define IMX5_CLK_ECSPI2_IPG_GATE	53
+#define IMX5_CLK_ECSPI2_PER_GATE	54
+#define IMX5_CLK_CSPI_IPG_GATE		55
+#define IMX5_CLK_SDMA_GATE		56
+#define IMX5_CLK_EMI_SLOW_GATE		57
+#define IMX5_CLK_IPU_SEL		58
+#define IMX5_CLK_IPU_GATE		59
+#define IMX5_CLK_NFC_GATE		60
+#define IMX5_CLK_IPU_DI1_GATE		61
+#define IMX5_CLK_VPU_SEL		62
+#define IMX5_CLK_VPU_GATE		63
+#define IMX5_CLK_VPU_REFERENCE_GATE	64
+#define IMX5_CLK_UART4_IPG_GATE		65
+#define IMX5_CLK_UART4_PER_GATE		66
+#define IMX5_CLK_UART5_IPG_GATE		67
+#define IMX5_CLK_UART5_PER_GATE		68
+#define IMX5_CLK_TVE_GATE		69
+#define IMX5_CLK_TVE_PRED		70
+#define IMX5_CLK_ESDHC1_PER_GATE	71
+#define IMX5_CLK_ESDHC2_PER_GATE	72
+#define IMX5_CLK_ESDHC3_PER_GATE	73
+#define IMX5_CLK_ESDHC4_PER_GATE	74
+#define IMX5_CLK_USB_PHY_GATE		75
+#define IMX5_CLK_HSI2C_GATE		76
+#define IMX5_CLK_MIPI_HSC1_GATE		77
+#define IMX5_CLK_MIPI_HSC2_GATE		78
+#define IMX5_CLK_MIPI_ESC_GATE		79
+#define IMX5_CLK_MIPI_HSP_GATE		80
+#define IMX5_CLK_LDB_DI1_DIV_3_5	81
+#define IMX5_CLK_LDB_DI1_DIV		82
+#define IMX5_CLK_LDB_DI0_DIV_3_5	83
+#define IMX5_CLK_LDB_DI0_DIV		84
+#define IMX5_CLK_LDB_DI1_GATE		85
+#define IMX5_CLK_CAN2_SERIAL_GATE	86
+#define IMX5_CLK_CAN2_IPG_GATE		87
+#define IMX5_CLK_I2C3_GATE		88
+#define IMX5_CLK_LP_APM			89
+#define IMX5_CLK_PERIPH_APM		90
+#define IMX5_CLK_MAIN_BUS		91
+#define IMX5_CLK_AHB_MAX		92
+#define IMX5_CLK_AIPS_TZ1		93
+#define IMX5_CLK_AIPS_TZ2		94
+#define IMX5_CLK_TMAX1			95
+#define IMX5_CLK_TMAX2			96
+#define IMX5_CLK_TMAX3			97
+#define IMX5_CLK_SPBA			98
+#define IMX5_CLK_UART_SEL		99
+#define IMX5_CLK_ESDHC_A_SEL		100
+#define IMX5_CLK_ESDHC_B_SEL		101
+#define IMX5_CLK_ESDHC_A_PODF		102
+#define IMX5_CLK_ESDHC_B_PODF		103
+#define IMX5_CLK_ECSPI_SEL		104
+#define IMX5_CLK_USBOH3_SEL		105
+#define IMX5_CLK_USB_PHY_SEL		106
+#define IMX5_CLK_IIM_GATE		107
+#define IMX5_CLK_USBOH3_GATE		108
+#define IMX5_CLK_EMI_FAST_GATE		109
+#define IMX5_CLK_IPU_DI0_GATE		110
+#define IMX5_CLK_GPC_DVFS		111
+#define IMX5_CLK_PLL1_SW		112
+#define IMX5_CLK_PLL2_SW		113
+#define IMX5_CLK_PLL3_SW		114
+#define IMX5_CLK_IPU_DI0_SEL		115
+#define IMX5_CLK_IPU_DI1_SEL		116
+#define IMX5_CLK_TVE_EXT_SEL		117
+#define IMX5_CLK_MX51_MIPI		118
+#define IMX5_CLK_PLL4_SW		119
+#define IMX5_CLK_LDB_DI1_SEL		120
+#define IMX5_CLK_DI_PLL4_PODF		121
+#define IMX5_CLK_LDB_DI0_SEL		122
+#define IMX5_CLK_LDB_DI0_GATE		123
+#define IMX5_CLK_USB_PHY1_GATE		124
+#define IMX5_CLK_USB_PHY2_GATE		125
+#define IMX5_CLK_PER_LP_APM		126
+#define IMX5_CLK_PER_PRED1		127
+#define IMX5_CLK_PER_PRED2		128
+#define IMX5_CLK_PER_PODF		129
+#define IMX5_CLK_PER_ROOT		130
+#define IMX5_CLK_SSI_APM		131
+#define IMX5_CLK_SSI1_ROOT_SEL		132
+#define IMX5_CLK_SSI2_ROOT_SEL		133
+#define IMX5_CLK_SSI3_ROOT_SEL		134
+#define IMX5_CLK_SSI_EXT1_SEL		135
+#define IMX5_CLK_SSI_EXT2_SEL		136
+#define IMX5_CLK_SSI_EXT1_COM_SEL	137
+#define IMX5_CLK_SSI_EXT2_COM_SEL	138
+#define IMX5_CLK_SSI1_ROOT_PRED		139
+#define IMX5_CLK_SSI1_ROOT_PODF		140
+#define IMX5_CLK_SSI2_ROOT_PRED		141
+#define IMX5_CLK_SSI2_ROOT_PODF		142
+#define IMX5_CLK_SSI_EXT1_PRED		143
+#define IMX5_CLK_SSI_EXT1_PODF		144
+#define IMX5_CLK_SSI_EXT2_PRED		145
+#define IMX5_CLK_SSI_EXT2_PODF		146
+#define IMX5_CLK_SSI1_ROOT_GATE		147
+#define IMX5_CLK_SSI2_ROOT_GATE		148
+#define IMX5_CLK_SSI3_ROOT_GATE		149
+#define IMX5_CLK_SSI_EXT1_GATE		150
+#define IMX5_CLK_SSI_EXT2_GATE		151
+#define IMX5_CLK_EPIT1_IPG_GATE		152
+#define IMX5_CLK_EPIT1_HF_GATE		153
+#define IMX5_CLK_EPIT2_IPG_GATE		154
+#define IMX5_CLK_EPIT2_HF_GATE		155
+#define IMX5_CLK_CAN_SEL		156
+#define IMX5_CLK_CAN1_SERIAL_GATE	157
+#define IMX5_CLK_CAN1_IPG_GATE		158
+#define IMX5_CLK_OWIRE_GATE		159
+#define IMX5_CLK_GPU3D_SEL		160
+#define IMX5_CLK_GPU2D_SEL		161
+#define IMX5_CLK_GPU3D_GATE		162
+#define IMX5_CLK_GPU2D_GATE		163
+#define IMX5_CLK_GARB_GATE		164
+#define IMX5_CLK_CKO1_SEL		165
+#define IMX5_CLK_CKO1_PODF		166
+#define IMX5_CLK_CKO1			167
+#define IMX5_CLK_CKO2_SEL		168
+#define IMX5_CLK_CKO2_PODF		169
+#define IMX5_CLK_CKO2			170
+#define IMX5_CLK_SRTC_GATE		171
+#define IMX5_CLK_PATA_GATE		172
+#define IMX5_CLK_SATA_GATE		173
+#define IMX5_CLK_SPDIF_XTAL_SEL		174
+#define IMX5_CLK_SPDIF0_SEL		175
+#define IMX5_CLK_SPDIF1_SEL		176
+#define IMX5_CLK_SPDIF0_PRED		177
+#define IMX5_CLK_SPDIF0_PODF		178
+#define IMX5_CLK_SPDIF1_PRED		179
+#define IMX5_CLK_SPDIF1_PODF		180
+#define IMX5_CLK_SPDIF0_COM_SEL		181
+#define IMX5_CLK_SPDIF1_COM_SEL		182
+#define IMX5_CLK_SPDIF0_GATE		183
+#define IMX5_CLK_SPDIF1_GATE		184
+#define IMX5_CLK_SPDIF_IPG_GATE		185
+#define IMX5_CLK_OCRAM			186
+#define IMX5_CLK_SAHARA_IPG_GATE	187
+#define IMX5_CLK_SATA_REF		188
+#define IMX5_CLK_STEP_SEL		189
+#define IMX5_CLK_CPU_PODF_SEL		190
+#define IMX5_CLK_ARM			191
+#define IMX5_CLK_FIRI_PRED		192
+#define IMX5_CLK_FIRI_SEL		193
+#define IMX5_CLK_FIRI_PODF		194
+#define IMX5_CLK_FIRI_SERIAL_GATE	195
+#define IMX5_CLK_FIRI_IPG_GATE		196
+#define IMX5_CLK_CSI0_MCLK1_PRED	197
+#define IMX5_CLK_CSI0_MCLK1_SEL		198
+#define IMX5_CLK_CSI0_MCLK1_PODF	199
+#define IMX5_CLK_CSI0_MCLK1_GATE	200
+#define IMX5_CLK_IEEE1588_PRED		201
+#define IMX5_CLK_IEEE1588_SEL		202
+#define IMX5_CLK_IEEE1588_PODF		203
+#define IMX5_CLK_IEEE1588_GATE		204
+#define IMX5_CLK_END			205
+
+#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
new file mode 100644
index 0000000..2905033
--- /dev/null
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
+#define __DT_BINDINGS_CLOCK_IMX6QDL_H
+
+#define IMX6QDL_CLK_DUMMY			0
+#define IMX6QDL_CLK_CKIL			1
+#define IMX6QDL_CLK_CKIH			2
+#define IMX6QDL_CLK_OSC				3
+#define IMX6QDL_CLK_PLL2_PFD0_352M		4
+#define IMX6QDL_CLK_PLL2_PFD1_594M		5
+#define IMX6QDL_CLK_PLL2_PFD2_396M		6
+#define IMX6QDL_CLK_PLL3_PFD0_720M		7
+#define IMX6QDL_CLK_PLL3_PFD1_540M		8
+#define IMX6QDL_CLK_PLL3_PFD2_508M		9
+#define IMX6QDL_CLK_PLL3_PFD3_454M		10
+#define IMX6QDL_CLK_PLL2_198M			11
+#define IMX6QDL_CLK_PLL3_120M			12
+#define IMX6QDL_CLK_PLL3_80M			13
+#define IMX6QDL_CLK_PLL3_60M			14
+#define IMX6QDL_CLK_TWD				15
+#define IMX6QDL_CLK_STEP			16
+#define IMX6QDL_CLK_PLL1_SW			17
+#define IMX6QDL_CLK_PERIPH_PRE			18
+#define IMX6QDL_CLK_PERIPH2_PRE			19
+#define IMX6QDL_CLK_PERIPH_CLK2_SEL		20
+#define IMX6QDL_CLK_PERIPH2_CLK2_SEL		21
+#define IMX6QDL_CLK_AXI_SEL			22
+#define IMX6QDL_CLK_ESAI_SEL			23
+#define IMX6QDL_CLK_ASRC_SEL			24
+#define IMX6QDL_CLK_SPDIF_SEL			25
+#define IMX6QDL_CLK_GPU2D_AXI			26
+#define IMX6QDL_CLK_GPU3D_AXI			27
+#define IMX6QDL_CLK_GPU2D_CORE_SEL		28
+#define IMX6QDL_CLK_GPU3D_CORE_SEL		29
+#define IMX6QDL_CLK_GPU3D_SHADER_SEL		30
+#define IMX6QDL_CLK_IPU1_SEL			31
+#define IMX6QDL_CLK_IPU2_SEL			32
+#define IMX6QDL_CLK_LDB_DI0_SEL			33
+#define IMX6QDL_CLK_LDB_DI1_SEL			34
+#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL		35
+#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL		36
+#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL		37
+#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL		38
+#define IMX6QDL_CLK_IPU1_DI0_SEL		39
+#define IMX6QDL_CLK_IPU1_DI1_SEL		40
+#define IMX6QDL_CLK_IPU2_DI0_SEL		41
+#define IMX6QDL_CLK_IPU2_DI1_SEL		42
+#define IMX6QDL_CLK_HSI_TX_SEL			43
+#define IMX6QDL_CLK_PCIE_AXI_SEL		44
+#define IMX6QDL_CLK_SSI1_SEL			45
+#define IMX6QDL_CLK_SSI2_SEL			46
+#define IMX6QDL_CLK_SSI3_SEL			47
+#define IMX6QDL_CLK_USDHC1_SEL			48
+#define IMX6QDL_CLK_USDHC2_SEL			49
+#define IMX6QDL_CLK_USDHC3_SEL			50
+#define IMX6QDL_CLK_USDHC4_SEL			51
+#define IMX6QDL_CLK_ENFC_SEL			52
+#define IMX6QDL_CLK_EIM_SEL			53
+#define IMX6QDL_CLK_EIM_SLOW_SEL		54
+#define IMX6QDL_CLK_VDO_AXI_SEL			55
+#define IMX6QDL_CLK_VPU_AXI_SEL			56
+#define IMX6QDL_CLK_CKO1_SEL			57
+#define IMX6QDL_CLK_PERIPH			58
+#define IMX6QDL_CLK_PERIPH2			59
+#define IMX6QDL_CLK_PERIPH_CLK2			60
+#define IMX6QDL_CLK_PERIPH2_CLK2		61
+#define IMX6QDL_CLK_IPG				62
+#define IMX6QDL_CLK_IPG_PER			63
+#define IMX6QDL_CLK_ESAI_PRED			64
+#define IMX6QDL_CLK_ESAI_PODF			65
+#define IMX6QDL_CLK_ASRC_PRED			66
+#define IMX6QDL_CLK_ASRC_PODF			67
+#define IMX6QDL_CLK_SPDIF_PRED			68
+#define IMX6QDL_CLK_SPDIF_PODF			69
+#define IMX6QDL_CLK_CAN_ROOT			70
+#define IMX6QDL_CLK_ECSPI_ROOT			71
+#define IMX6QDL_CLK_GPU2D_CORE_PODF		72
+#define IMX6QDL_CLK_GPU3D_CORE_PODF		73
+#define IMX6QDL_CLK_GPU3D_SHADER		74
+#define IMX6QDL_CLK_IPU1_PODF			75
+#define IMX6QDL_CLK_IPU2_PODF			76
+#define IMX6QDL_CLK_LDB_DI0_PODF		77
+#define IMX6QDL_CLK_LDB_DI1_PODF		78
+#define IMX6QDL_CLK_IPU1_DI0_PRE		79
+#define IMX6QDL_CLK_IPU1_DI1_PRE		80
+#define IMX6QDL_CLK_IPU2_DI0_PRE		81
+#define IMX6QDL_CLK_IPU2_DI1_PRE		82
+#define IMX6QDL_CLK_HSI_TX_PODF			83
+#define IMX6QDL_CLK_SSI1_PRED			84
+#define IMX6QDL_CLK_SSI1_PODF			85
+#define IMX6QDL_CLK_SSI2_PRED			86
+#define IMX6QDL_CLK_SSI2_PODF			87
+#define IMX6QDL_CLK_SSI3_PRED			88
+#define IMX6QDL_CLK_SSI3_PODF			89
+#define IMX6QDL_CLK_UART_SERIAL_PODF		90
+#define IMX6QDL_CLK_USDHC1_PODF			91
+#define IMX6QDL_CLK_USDHC2_PODF			92
+#define IMX6QDL_CLK_USDHC3_PODF			93
+#define IMX6QDL_CLK_USDHC4_PODF			94
+#define IMX6QDL_CLK_ENFC_PRED			95
+#define IMX6QDL_CLK_ENFC_PODF			96
+#define IMX6QDL_CLK_EIM_PODF			97
+#define IMX6QDL_CLK_EIM_SLOW_PODF		98
+#define IMX6QDL_CLK_VPU_AXI_PODF		99
+#define IMX6QDL_CLK_CKO1_PODF			100
+#define IMX6QDL_CLK_AXI				101
+#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF		102
+#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF		103
+#define IMX6QDL_CLK_ARM				104
+#define IMX6QDL_CLK_AHB				105
+#define IMX6QDL_CLK_APBH_DMA			106
+#define IMX6QDL_CLK_ASRC			107
+#define IMX6QDL_CLK_CAN1_IPG			108
+#define IMX6QDL_CLK_CAN1_SERIAL			109
+#define IMX6QDL_CLK_CAN2_IPG			110
+#define IMX6QDL_CLK_CAN2_SERIAL			111
+#define IMX6QDL_CLK_ECSPI1			112
+#define IMX6QDL_CLK_ECSPI2			113
+#define IMX6QDL_CLK_ECSPI3			114
+#define IMX6QDL_CLK_ECSPI4			115
+#define IMX6Q_CLK_ECSPI5			116
+#define IMX6DL_CLK_I2C4				116
+#define IMX6QDL_CLK_ENET			117
+#define IMX6QDL_CLK_ESAI_EXTAL			118
+#define IMX6QDL_CLK_GPT_IPG			119
+#define IMX6QDL_CLK_GPT_IPG_PER			120
+#define IMX6QDL_CLK_GPU2D_CORE			121
+#define IMX6QDL_CLK_GPU3D_CORE			122
+#define IMX6QDL_CLK_HDMI_IAHB			123
+#define IMX6QDL_CLK_HDMI_ISFR			124
+#define IMX6QDL_CLK_I2C1			125
+#define IMX6QDL_CLK_I2C2			126
+#define IMX6QDL_CLK_I2C3			127
+#define IMX6QDL_CLK_IIM				128
+#define IMX6QDL_CLK_ENFC			129
+#define IMX6QDL_CLK_IPU1			130
+#define IMX6QDL_CLK_IPU1_DI0			131
+#define IMX6QDL_CLK_IPU1_DI1			132
+#define IMX6QDL_CLK_IPU2			133
+#define IMX6QDL_CLK_IPU2_DI0			134
+#define IMX6QDL_CLK_LDB_DI0			135
+#define IMX6QDL_CLK_LDB_DI1			136
+#define IMX6QDL_CLK_IPU2_DI1			137
+#define IMX6QDL_CLK_HSI_TX			138
+#define IMX6QDL_CLK_MLB				139
+#define IMX6QDL_CLK_MMDC_CH0_AXI		140
+#define IMX6QDL_CLK_MMDC_CH1_AXI		141
+#define IMX6QDL_CLK_OCRAM			142
+#define IMX6QDL_CLK_OPENVG_AXI			143
+#define IMX6QDL_CLK_PCIE_AXI			144
+#define IMX6QDL_CLK_PWM1			145
+#define IMX6QDL_CLK_PWM2			146
+#define IMX6QDL_CLK_PWM3			147
+#define IMX6QDL_CLK_PWM4			148
+#define IMX6QDL_CLK_PER1_BCH			149
+#define IMX6QDL_CLK_GPMI_BCH_APB		150
+#define IMX6QDL_CLK_GPMI_BCH			151
+#define IMX6QDL_CLK_GPMI_IO			152
+#define IMX6QDL_CLK_GPMI_APB			153
+#define IMX6QDL_CLK_SATA			154
+#define IMX6QDL_CLK_SDMA			155
+#define IMX6QDL_CLK_SPBA			156
+#define IMX6QDL_CLK_SSI1			157
+#define IMX6QDL_CLK_SSI2			158
+#define IMX6QDL_CLK_SSI3			159
+#define IMX6QDL_CLK_UART_IPG			160
+#define IMX6QDL_CLK_UART_SERIAL			161
+#define IMX6QDL_CLK_USBOH3			162
+#define IMX6QDL_CLK_USDHC1			163
+#define IMX6QDL_CLK_USDHC2			164
+#define IMX6QDL_CLK_USDHC3			165
+#define IMX6QDL_CLK_USDHC4			166
+#define IMX6QDL_CLK_VDO_AXI			167
+#define IMX6QDL_CLK_VPU_AXI			168
+#define IMX6QDL_CLK_CKO1			169
+#define IMX6QDL_CLK_PLL1_SYS			170
+#define IMX6QDL_CLK_PLL2_BUS			171
+#define IMX6QDL_CLK_PLL3_USB_OTG		172
+#define IMX6QDL_CLK_PLL4_AUDIO			173
+#define IMX6QDL_CLK_PLL5_VIDEO			174
+#define IMX6QDL_CLK_PLL8_MLB			175
+#define IMX6QDL_CLK_PLL7_USB_HOST		176
+#define IMX6QDL_CLK_PLL6_ENET			177
+#define IMX6QDL_CLK_SSI1_IPG			178
+#define IMX6QDL_CLK_SSI2_IPG			179
+#define IMX6QDL_CLK_SSI3_IPG			180
+#define IMX6QDL_CLK_ROM				181
+#define IMX6QDL_CLK_USBPHY1			182
+#define IMX6QDL_CLK_USBPHY2			183
+#define IMX6QDL_CLK_LDB_DI0_DIV_3_5		184
+#define IMX6QDL_CLK_LDB_DI1_DIV_3_5		185
+#define IMX6QDL_CLK_SATA_REF			186
+#define IMX6QDL_CLK_SATA_REF_100M		187
+#define IMX6QDL_CLK_PCIE_REF			188
+#define IMX6QDL_CLK_PCIE_REF_125M		189
+#define IMX6QDL_CLK_ENET_REF			190
+#define IMX6QDL_CLK_USBPHY1_GATE		191
+#define IMX6QDL_CLK_USBPHY2_GATE		192
+#define IMX6QDL_CLK_PLL4_POST_DIV		193
+#define IMX6QDL_CLK_PLL5_POST_DIV		194
+#define IMX6QDL_CLK_PLL5_VIDEO_DIV		195
+#define IMX6QDL_CLK_EIM_SLOW			196
+#define IMX6QDL_CLK_SPDIF			197
+#define IMX6QDL_CLK_CKO2_SEL			198
+#define IMX6QDL_CLK_CKO2_PODF			199
+#define IMX6QDL_CLK_CKO2			200
+#define IMX6QDL_CLK_CKO				201
+#define IMX6QDL_CLK_VDOA			202
+#define IMX6QDL_CLK_PLL4_AUDIO_DIV		203
+#define IMX6QDL_CLK_LVDS1_SEL			204
+#define IMX6QDL_CLK_LVDS2_SEL			205
+#define IMX6QDL_CLK_LVDS1_GATE			206
+#define IMX6QDL_CLK_LVDS2_GATE			207
+#define IMX6QDL_CLK_ESAI_IPG			208
+#define IMX6QDL_CLK_ESAI_MEM			209
+#define IMX6QDL_CLK_ASRC_IPG			210
+#define IMX6QDL_CLK_ASRC_MEM			211
+#define IMX6QDL_CLK_LVDS1_IN			212
+#define IMX6QDL_CLK_LVDS2_IN			213
+#define IMX6QDL_CLK_ANACLK1			214
+#define IMX6QDL_CLK_ANACLK2			215
+#define IMX6QDL_PLL1_BYPASS_SRC			216
+#define IMX6QDL_PLL2_BYPASS_SRC			217
+#define IMX6QDL_PLL3_BYPASS_SRC			218
+#define IMX6QDL_PLL4_BYPASS_SRC			219
+#define IMX6QDL_PLL5_BYPASS_SRC			220
+#define IMX6QDL_PLL6_BYPASS_SRC			221
+#define IMX6QDL_PLL7_BYPASS_SRC			222
+#define IMX6QDL_CLK_PLL1			223
+#define IMX6QDL_CLK_PLL2			224
+#define IMX6QDL_CLK_PLL3			225
+#define IMX6QDL_CLK_PLL4			226
+#define IMX6QDL_CLK_PLL5			227
+#define IMX6QDL_CLK_PLL6			228
+#define IMX6QDL_CLK_PLL7			229
+#define IMX6QDL_PLL1_BYPASS			230
+#define IMX6QDL_PLL2_BYPASS			231
+#define IMX6QDL_PLL3_BYPASS			232
+#define IMX6QDL_PLL4_BYPASS			233
+#define IMX6QDL_PLL5_BYPASS			234
+#define IMX6QDL_PLL6_BYPASS			235
+#define IMX6QDL_PLL7_BYPASS			236
+#define IMX6QDL_CLK_GPT_3M			237
+#define IMX6QDL_CLK_VIDEO_27M			238
+#define IMX6QDL_CLK_MIPI_CORE_CFG		239
+#define IMX6QDL_CLK_MIPI_IPG			240
+#define IMX6QDL_CLK_CAAM_MEM			241
+#define IMX6QDL_CLK_CAAM_ACLK			242
+#define IMX6QDL_CLK_CAAM_IPG			243
+#define IMX6QDL_CLK_SPDIF_GCLK			244
+#define IMX6QDL_CLK_UART_SEL			245
+#define IMX6QDL_CLK_IPG_PER_SEL			246
+#define IMX6QDL_CLK_ECSPI_SEL			247
+#define IMX6QDL_CLK_CAN_SEL			248
+#define IMX6QDL_CLK_MMDC_CH1_AXI_CG		249
+#define IMX6QDL_CLK_PRE0			250
+#define IMX6QDL_CLK_PRE1			251
+#define IMX6QDL_CLK_PRE2			252
+#define IMX6QDL_CLK_PRE3			253
+#define IMX6QDL_CLK_PRG0_AXI			254
+#define IMX6QDL_CLK_PRG1_AXI			255
+#define IMX6QDL_CLK_PRG0_APB			256
+#define IMX6QDL_CLK_PRG1_APB			257
+#define IMX6QDL_CLK_PRE_AXI			258
+#define IMX6QDL_CLK_END				259
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
new file mode 100644
index 0000000..e14573e
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
+#define __DT_BINDINGS_CLOCK_IMX6SL_H
+
+#define IMX6SL_CLK_DUMMY		0
+#define IMX6SL_CLK_CKIL			1
+#define IMX6SL_CLK_OSC			2
+#define IMX6SL_CLK_PLL1_SYS		3
+#define IMX6SL_CLK_PLL2_BUS		4
+#define IMX6SL_CLK_PLL3_USB_OTG		5
+#define IMX6SL_CLK_PLL4_AUDIO		6
+#define IMX6SL_CLK_PLL5_VIDEO		7
+#define IMX6SL_CLK_PLL6_ENET		8
+#define IMX6SL_CLK_PLL7_USB_HOST	9
+#define IMX6SL_CLK_USBPHY1		10
+#define IMX6SL_CLK_USBPHY2		11
+#define IMX6SL_CLK_USBPHY1_GATE		12
+#define IMX6SL_CLK_USBPHY2_GATE		13
+#define IMX6SL_CLK_PLL4_POST_DIV	14
+#define IMX6SL_CLK_PLL5_POST_DIV	15
+#define IMX6SL_CLK_PLL5_VIDEO_DIV	16
+#define IMX6SL_CLK_ENET_REF		17
+#define IMX6SL_CLK_PLL2_PFD0		18
+#define IMX6SL_CLK_PLL2_PFD1		19
+#define IMX6SL_CLK_PLL2_PFD2		20
+#define IMX6SL_CLK_PLL3_PFD0		21
+#define IMX6SL_CLK_PLL3_PFD1		22
+#define IMX6SL_CLK_PLL3_PFD2		23
+#define IMX6SL_CLK_PLL3_PFD3		24
+#define IMX6SL_CLK_PLL2_198M		25
+#define IMX6SL_CLK_PLL3_120M		26
+#define IMX6SL_CLK_PLL3_80M		27
+#define IMX6SL_CLK_PLL3_60M		28
+#define IMX6SL_CLK_STEP			29
+#define IMX6SL_CLK_PLL1_SW		30
+#define IMX6SL_CLK_OCRAM_ALT_SEL	31
+#define IMX6SL_CLK_OCRAM_SEL		32
+#define IMX6SL_CLK_PRE_PERIPH2_SEL	33
+#define IMX6SL_CLK_PRE_PERIPH_SEL	34
+#define IMX6SL_CLK_PERIPH2_CLK2_SEL	35
+#define IMX6SL_CLK_PERIPH_CLK2_SEL	36
+#define IMX6SL_CLK_CSI_SEL		37
+#define IMX6SL_CLK_LCDIF_AXI_SEL	38
+#define IMX6SL_CLK_USDHC1_SEL		39
+#define IMX6SL_CLK_USDHC2_SEL		40
+#define IMX6SL_CLK_USDHC3_SEL		41
+#define IMX6SL_CLK_USDHC4_SEL		42
+#define IMX6SL_CLK_SSI1_SEL		43
+#define IMX6SL_CLK_SSI2_SEL		44
+#define IMX6SL_CLK_SSI3_SEL		45
+#define IMX6SL_CLK_PERCLK_SEL		46
+#define IMX6SL_CLK_PXP_AXI_SEL		47
+#define IMX6SL_CLK_EPDC_AXI_SEL		48
+#define IMX6SL_CLK_GPU2D_OVG_SEL	49
+#define IMX6SL_CLK_GPU2D_SEL		50
+#define IMX6SL_CLK_LCDIF_PIX_SEL	51
+#define IMX6SL_CLK_EPDC_PIX_SEL		52
+#define IMX6SL_CLK_SPDIF0_SEL		53
+#define IMX6SL_CLK_SPDIF1_SEL		54
+#define IMX6SL_CLK_EXTERN_AUDIO_SEL	55
+#define IMX6SL_CLK_ECSPI_SEL		56
+#define IMX6SL_CLK_UART_SEL		57
+#define IMX6SL_CLK_PERIPH		58
+#define IMX6SL_CLK_PERIPH2		59
+#define IMX6SL_CLK_OCRAM_PODF		60
+#define IMX6SL_CLK_PERIPH_CLK2_PODF	61
+#define IMX6SL_CLK_PERIPH2_CLK2_PODF	62
+#define IMX6SL_CLK_IPG			63
+#define IMX6SL_CLK_CSI_PODF		64
+#define IMX6SL_CLK_LCDIF_AXI_PODF	65
+#define IMX6SL_CLK_USDHC1_PODF		66
+#define IMX6SL_CLK_USDHC2_PODF		67
+#define IMX6SL_CLK_USDHC3_PODF		68
+#define IMX6SL_CLK_USDHC4_PODF		69
+#define IMX6SL_CLK_SSI1_PRED		70
+#define IMX6SL_CLK_SSI1_PODF		71
+#define IMX6SL_CLK_SSI2_PRED		72
+#define IMX6SL_CLK_SSI2_PODF		73
+#define IMX6SL_CLK_SSI3_PRED		74
+#define IMX6SL_CLK_SSI3_PODF		75
+#define IMX6SL_CLK_PERCLK		76
+#define IMX6SL_CLK_PXP_AXI_PODF		77
+#define IMX6SL_CLK_EPDC_AXI_PODF	78
+#define IMX6SL_CLK_GPU2D_OVG_PODF	79
+#define IMX6SL_CLK_GPU2D_PODF		80
+#define IMX6SL_CLK_LCDIF_PIX_PRED	81
+#define IMX6SL_CLK_EPDC_PIX_PRED	82
+#define IMX6SL_CLK_LCDIF_PIX_PODF	83
+#define IMX6SL_CLK_EPDC_PIX_PODF	84
+#define IMX6SL_CLK_SPDIF0_PRED		85
+#define IMX6SL_CLK_SPDIF0_PODF		86
+#define IMX6SL_CLK_SPDIF1_PRED		87
+#define IMX6SL_CLK_SPDIF1_PODF		88
+#define IMX6SL_CLK_EXTERN_AUDIO_PRED	89
+#define IMX6SL_CLK_EXTERN_AUDIO_PODF	90
+#define IMX6SL_CLK_ECSPI_ROOT		91
+#define IMX6SL_CLK_UART_ROOT		92
+#define IMX6SL_CLK_AHB			93
+#define IMX6SL_CLK_MMDC_ROOT		94
+#define IMX6SL_CLK_ARM			95
+#define IMX6SL_CLK_ECSPI1		96
+#define IMX6SL_CLK_ECSPI2		97
+#define IMX6SL_CLK_ECSPI3		98
+#define IMX6SL_CLK_ECSPI4		99
+#define IMX6SL_CLK_EPIT1		100
+#define IMX6SL_CLK_EPIT2		101
+#define IMX6SL_CLK_EXTERN_AUDIO		102
+#define IMX6SL_CLK_GPT			103
+#define IMX6SL_CLK_GPT_SERIAL		104
+#define IMX6SL_CLK_GPU2D_OVG		105
+#define IMX6SL_CLK_I2C1			106
+#define IMX6SL_CLK_I2C2			107
+#define IMX6SL_CLK_I2C3			108
+#define IMX6SL_CLK_OCOTP		109
+#define IMX6SL_CLK_CSI			110
+#define IMX6SL_CLK_PXP_AXI		111
+#define IMX6SL_CLK_EPDC_AXI		112
+#define IMX6SL_CLK_LCDIF_AXI		113
+#define IMX6SL_CLK_LCDIF_PIX		114
+#define IMX6SL_CLK_EPDC_PIX		115
+#define IMX6SL_CLK_OCRAM		116
+#define IMX6SL_CLK_PWM1			117
+#define IMX6SL_CLK_PWM2			118
+#define IMX6SL_CLK_PWM3			119
+#define IMX6SL_CLK_PWM4			120
+#define IMX6SL_CLK_SDMA			121
+#define IMX6SL_CLK_SPDIF		122
+#define IMX6SL_CLK_SSI1			123
+#define IMX6SL_CLK_SSI2			124
+#define IMX6SL_CLK_SSI3			125
+#define IMX6SL_CLK_UART			126
+#define IMX6SL_CLK_UART_SERIAL		127
+#define IMX6SL_CLK_USBOH3		128
+#define IMX6SL_CLK_USDHC1		129
+#define IMX6SL_CLK_USDHC2		130
+#define IMX6SL_CLK_USDHC3		131
+#define IMX6SL_CLK_USDHC4		132
+#define IMX6SL_CLK_PLL4_AUDIO_DIV	133
+#define IMX6SL_CLK_SPBA			134
+#define IMX6SL_CLK_ENET			135
+#define IMX6SL_CLK_LVDS1_SEL		136
+#define IMX6SL_CLK_LVDS1_OUT		137
+#define IMX6SL_CLK_LVDS1_IN		138
+#define IMX6SL_CLK_ANACLK1		139
+#define IMX6SL_PLL1_BYPASS_SRC		140
+#define IMX6SL_PLL2_BYPASS_SRC		141
+#define IMX6SL_PLL3_BYPASS_SRC		142
+#define IMX6SL_PLL4_BYPASS_SRC		143
+#define IMX6SL_PLL5_BYPASS_SRC		144
+#define IMX6SL_PLL6_BYPASS_SRC		145
+#define IMX6SL_PLL7_BYPASS_SRC		146
+#define IMX6SL_CLK_PLL1			147
+#define IMX6SL_CLK_PLL2			148
+#define IMX6SL_CLK_PLL3			149
+#define IMX6SL_CLK_PLL4			150
+#define IMX6SL_CLK_PLL5			151
+#define IMX6SL_CLK_PLL6			152
+#define IMX6SL_CLK_PLL7			153
+#define IMX6SL_PLL1_BYPASS		154
+#define IMX6SL_PLL2_BYPASS		155
+#define IMX6SL_PLL3_BYPASS		156
+#define IMX6SL_PLL4_BYPASS		157
+#define IMX6SL_PLL5_BYPASS		158
+#define IMX6SL_PLL6_BYPASS		159
+#define IMX6SL_PLL7_BYPASS		160
+#define IMX6SL_CLK_SSI1_IPG		161
+#define IMX6SL_CLK_SSI2_IPG		162
+#define IMX6SL_CLK_SSI3_IPG		163
+#define IMX6SL_CLK_SPDIF_GCLK		164
+#define IMX6SL_CLK_END			165
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
new file mode 100644
index 0000000..39c2567
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sll-clock.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H
+#define __DT_BINDINGS_CLOCK_IMX6SLL_H
+
+#define IMX6SLL_CLK_DUMMY		0
+#define IMX6SLL_CLK_CKIL		1
+#define IMX6SLL_CLK_OSC			2
+#define IMX6SLL_PLL1_BYPASS_SRC		3
+#define IMX6SLL_PLL2_BYPASS_SRC		4
+#define IMX6SLL_PLL3_BYPASS_SRC		5
+#define IMX6SLL_PLL4_BYPASS_SRC		6
+#define IMX6SLL_PLL5_BYPASS_SRC		7
+#define IMX6SLL_PLL6_BYPASS_SRC		8
+#define IMX6SLL_PLL7_BYPASS_SRC		9
+#define IMX6SLL_CLK_PLL1		10
+#define IMX6SLL_CLK_PLL2		11
+#define IMX6SLL_CLK_PLL3		12
+#define IMX6SLL_CLK_PLL4		13
+#define IMX6SLL_CLK_PLL5		14
+#define IMX6SLL_CLK_PLL6		15
+#define IMX6SLL_CLK_PLL7		16
+#define IMX6SLL_PLL1_BYPASS		17
+#define IMX6SLL_PLL2_BYPASS		18
+#define IMX6SLL_PLL3_BYPASS		19
+#define IMX6SLL_PLL4_BYPASS		20
+#define IMX6SLL_PLL5_BYPASS		21
+#define IMX6SLL_PLL6_BYPASS		22
+#define IMX6SLL_PLL7_BYPASS		23
+#define IMX6SLL_CLK_PLL1_SYS		24
+#define IMX6SLL_CLK_PLL2_BUS		25
+#define IMX6SLL_CLK_PLL3_USB_OTG	26
+#define IMX6SLL_CLK_PLL4_AUDIO		27
+#define IMX6SLL_CLK_PLL5_VIDEO		28
+#define IMX6SLL_CLK_PLL6_ENET		29
+#define IMX6SLL_CLK_PLL7_USB_HOST	30
+#define IMX6SLL_CLK_USBPHY1		31
+#define IMX6SLL_CLK_USBPHY2		32
+#define IMX6SLL_CLK_USBPHY1_GATE	33
+#define IMX6SLL_CLK_USBPHY2_GATE	34
+#define IMX6SLL_CLK_PLL2_PFD0		35
+#define IMX6SLL_CLK_PLL2_PFD1		36
+#define IMX6SLL_CLK_PLL2_PFD2		37
+#define IMX6SLL_CLK_PLL2_PFD3		38
+#define IMX6SLL_CLK_PLL3_PFD0		39
+#define IMX6SLL_CLK_PLL3_PFD1		40
+#define IMX6SLL_CLK_PLL3_PFD2		41
+#define IMX6SLL_CLK_PLL3_PFD3		42
+#define IMX6SLL_CLK_PLL4_POST_DIV	43
+#define IMX6SLL_CLK_PLL4_AUDIO_DIV	44
+#define IMX6SLL_CLK_PLL5_POST_DIV	45
+#define IMX6SLL_CLK_PLL5_VIDEO_DIV	46
+#define IMX6SLL_CLK_PLL2_198M		47
+#define IMX6SLL_CLK_PLL3_120M		48
+#define IMX6SLL_CLK_PLL3_80M		49
+#define IMX6SLL_CLK_PLL3_60M		50
+#define IMX6SLL_CLK_STEP		51
+#define IMX6SLL_CLK_PLL1_SW		52
+#define IMX6SLL_CLK_AXI_ALT_SEL		53
+#define IMX6SLL_CLK_AXI_SEL		54
+#define IMX6SLL_CLK_PERIPH_PRE		55
+#define IMX6SLL_CLK_PERIPH2_PRE		56
+#define IMX6SLL_CLK_PERIPH_CLK2_SEL	57
+#define IMX6SLL_CLK_PERIPH2_CLK2_SEL	58
+#define IMX6SLL_CLK_PERCLK_SEL		59
+#define IMX6SLL_CLK_USDHC1_SEL		60
+#define IMX6SLL_CLK_USDHC2_SEL		61
+#define IMX6SLL_CLK_USDHC3_SEL		62
+#define IMX6SLL_CLK_SSI1_SEL		63
+#define IMX6SLL_CLK_SSI2_SEL		64
+#define IMX6SLL_CLK_SSI3_SEL		65
+#define IMX6SLL_CLK_PXP_SEL		66
+#define IMX6SLL_CLK_LCDIF_PRE_SEL	67
+#define IMX6SLL_CLK_LCDIF_SEL		68
+#define IMX6SLL_CLK_EPDC_PRE_SEL	69
+#define IMX6SLL_CLK_SPDIF_SEL		70
+#define IMX6SLL_CLK_ECSPI_SEL		71
+#define IMX6SLL_CLK_UART_SEL		72
+#define IMX6SLL_CLK_ARM			73
+#define IMX6SLL_CLK_PERIPH		74
+#define IMX6SLL_CLK_PERIPH2		75
+#define IMX6SLL_CLK_PERIPH2_CLK2	76
+#define IMX6SLL_CLK_PERIPH_CLK2		77
+#define IMX6SLL_CLK_MMDC_PODF		78
+#define IMX6SLL_CLK_AXI_PODF		79
+#define IMX6SLL_CLK_AHB			80
+#define IMX6SLL_CLK_IPG			81
+#define IMX6SLL_CLK_PERCLK		82
+#define IMX6SLL_CLK_USDHC1_PODF		83
+#define IMX6SLL_CLK_USDHC2_PODF		84
+#define IMX6SLL_CLK_USDHC3_PODF		85
+#define IMX6SLL_CLK_SSI1_PRED		86
+#define IMX6SLL_CLK_SSI2_PRED		87
+#define IMX6SLL_CLK_SSI3_PRED		88
+#define IMX6SLL_CLK_SSI1_PODF		89
+#define IMX6SLL_CLK_SSI2_PODF		90
+#define IMX6SLL_CLK_SSI3_PODF		91
+#define IMX6SLL_CLK_PXP_PODF		92
+#define IMX6SLL_CLK_LCDIF_PRED		93
+#define IMX6SLL_CLK_LCDIF_PODF		94
+#define IMX6SLL_CLK_EPDC_SEL		95
+#define IMX6SLL_CLK_EPDC_PODF		96
+#define IMX6SLL_CLK_SPDIF_PRED		97
+#define IMX6SLL_CLK_SPDIF_PODF		98
+#define IMX6SLL_CLK_ECSPI_PODF		99
+#define IMX6SLL_CLK_UART_PODF		100
+
+/* CCGR 0 */
+#define IMX6SLL_CLK_AIPSTZ1		101
+#define IMX6SLL_CLK_AIPSTZ2		102
+#define IMX6SLL_CLK_DCP			103
+#define IMX6SLL_CLK_UART2_IPG		104
+#define IMX6SLL_CLK_UART2_SERIAL	105
+
+/* CCGR 1 */
+#define IMX6SLL_CLK_ECSPI1		106
+#define IMX6SLL_CLK_ECSPI2		107
+#define IMX6SLL_CLK_ECSPI3		108
+#define IMX6SLL_CLK_ECSPI4		109
+#define IMX6SLL_CLK_UART3_IPG		110
+#define IMX6SLL_CLK_UART3_SERIAL	111
+#define IMX6SLL_CLK_UART4_IPG		112
+#define IMX6SLL_CLK_UART4_SERIAL	113
+#define IMX6SLL_CLK_EPIT1		114
+#define IMX6SLL_CLK_EPIT2		115
+#define IMX6SLL_CLK_GPT_BUS		116
+#define IMX6SLL_CLK_GPT_SERIAL		117
+
+/* CCGR2 */
+#define IMX6SLL_CLK_CSI			118
+#define IMX6SLL_CLK_I2C1		119
+#define IMX6SLL_CLK_I2C2		120
+#define IMX6SLL_CLK_I2C3		121
+#define IMX6SLL_CLK_OCOTP		122
+#define IMX6SLL_CLK_LCDIF_APB		123
+#define IMX6SLL_CLK_PXP			124
+
+/* CCGR3 */
+#define IMX6SLL_CLK_UART5_IPG		125
+#define IMX6SLL_CLK_UART5_SERIAL	126
+#define IMX6SLL_CLK_EPDC_AXI		127
+#define IMX6SLL_CLK_EPDC_PIX		128
+#define IMX6SLL_CLK_LCDIF_PIX		129
+#define IMX6SLL_CLK_WDOG1		130
+#define IMX6SLL_CLK_MMDC_P0_FAST	131
+#define IMX6SLL_CLK_MMDC_P0_IPG		132
+#define IMX6SLL_CLK_OCRAM		133
+
+/* CCGR4 */
+#define IMX6SLL_CLK_PWM1		134
+#define IMX6SLL_CLK_PWM2		135
+#define IMX6SLL_CLK_PWM3		136
+#define IMX6SLL_CLK_PWM4		137
+
+/* CCGR 5 */
+#define IMX6SLL_CLK_ROM			138
+#define IMX6SLL_CLK_SDMA		139
+#define IMX6SLL_CLK_KPP			140
+#define IMX6SLL_CLK_WDOG2		141
+#define IMX6SLL_CLK_SPBA		142
+#define IMX6SLL_CLK_SPDIF		143
+#define IMX6SLL_CLK_SPDIF_GCLK		144
+#define IMX6SLL_CLK_SSI1		145
+#define IMX6SLL_CLK_SSI1_IPG		146
+#define IMX6SLL_CLK_SSI2		147
+#define IMX6SLL_CLK_SSI2_IPG		148
+#define IMX6SLL_CLK_SSI3		149
+#define IMX6SLL_CLK_SSI3_IPG		150
+#define IMX6SLL_CLK_UART1_IPG		151
+#define IMX6SLL_CLK_UART1_SERIAL	152
+
+/* CCGR 6 */
+#define IMX6SLL_CLK_USBOH3		153
+#define IMX6SLL_CLK_USDHC1		154
+#define IMX6SLL_CLK_USDHC2		155
+#define IMX6SLL_CLK_USDHC3		156
+
+#define IMX6SLL_CLK_IPP_DI0		157
+#define IMX6SLL_CLK_IPP_DI1		158
+#define IMX6SLL_CLK_LDB_DI0_SEL		159
+#define IMX6SLL_CLK_LDB_DI0_DIV_3_5	160
+#define IMX6SLL_CLK_LDB_DI0_DIV_7	161
+#define IMX6SLL_CLK_LDB_DI0_DIV_SEL	162
+#define IMX6SLL_CLK_LDB_DI0		163
+#define IMX6SLL_CLK_LDB_DI1_SEL		164
+#define IMX6SLL_CLK_LDB_DI1_DIV_3_5	165
+#define IMX6SLL_CLK_LDB_DI1_DIV_7	166
+#define IMX6SLL_CLK_LDB_DI1_DIV_SEL	167
+#define IMX6SLL_CLK_LDB_DI1		168
+#define IMX6SLL_CLK_EXTERN_AUDIO_SEL    169
+#define IMX6SLL_CLK_EXTERN_AUDIO_PRED   170
+#define IMX6SLL_CLK_EXTERN_AUDIO_PODF   171
+#define IMX6SLL_CLK_EXTERN_AUDIO        172
+
+#define IMX6SLL_CLK_END			173
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
new file mode 100644
index 0000000..36f0324
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -0,0 +1,280 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
+#define __DT_BINDINGS_CLOCK_IMX6SX_H
+
+#define IMX6SX_CLK_DUMMY		0
+#define IMX6SX_CLK_CKIL			1
+#define IMX6SX_CLK_CKIH			2
+#define IMX6SX_CLK_OSC			3
+#define IMX6SX_CLK_PLL1_SYS		4
+#define IMX6SX_CLK_PLL2_BUS		5
+#define IMX6SX_CLK_PLL3_USB_OTG		6
+#define IMX6SX_CLK_PLL4_AUDIO		7
+#define IMX6SX_CLK_PLL5_VIDEO		8
+#define IMX6SX_CLK_PLL6_ENET		9
+#define IMX6SX_CLK_PLL7_USB_HOST	10
+#define IMX6SX_CLK_USBPHY1		11
+#define IMX6SX_CLK_USBPHY2		12
+#define IMX6SX_CLK_USBPHY1_GATE		13
+#define IMX6SX_CLK_USBPHY2_GATE		14
+#define IMX6SX_CLK_PCIE_REF		15
+#define IMX6SX_CLK_PCIE_REF_125M	16
+#define IMX6SX_CLK_ENET_REF		17
+#define IMX6SX_CLK_PLL2_PFD0		18
+#define IMX6SX_CLK_PLL2_PFD1		19
+#define IMX6SX_CLK_PLL2_PFD2		20
+#define IMX6SX_CLK_PLL2_PFD3		21
+#define IMX6SX_CLK_PLL3_PFD0		22
+#define IMX6SX_CLK_PLL3_PFD1		23
+#define IMX6SX_CLK_PLL3_PFD2		24
+#define IMX6SX_CLK_PLL3_PFD3		25
+#define IMX6SX_CLK_PLL2_198M		26
+#define IMX6SX_CLK_PLL3_120M		27
+#define IMX6SX_CLK_PLL3_80M		28
+#define IMX6SX_CLK_PLL3_60M		29
+#define IMX6SX_CLK_TWD			30
+#define IMX6SX_CLK_PLL4_POST_DIV	31
+#define IMX6SX_CLK_PLL4_AUDIO_DIV	32
+#define IMX6SX_CLK_PLL5_POST_DIV	33
+#define IMX6SX_CLK_PLL5_VIDEO_DIV	34
+#define IMX6SX_CLK_STEP			35
+#define IMX6SX_CLK_PLL1_SW		36
+#define IMX6SX_CLK_OCRAM_SEL		37
+#define IMX6SX_CLK_PERIPH_PRE		38
+#define IMX6SX_CLK_PERIPH2_PRE		39
+#define IMX6SX_CLK_PERIPH_CLK2_SEL	40
+#define IMX6SX_CLK_PERIPH2_CLK2_SEL	41
+#define IMX6SX_CLK_PCIE_AXI_SEL		42
+#define IMX6SX_CLK_GPU_AXI_SEL		43
+#define IMX6SX_CLK_GPU_CORE_SEL		44
+#define IMX6SX_CLK_EIM_SLOW_SEL		45
+#define IMX6SX_CLK_USDHC1_SEL		46
+#define IMX6SX_CLK_USDHC2_SEL		47
+#define IMX6SX_CLK_USDHC3_SEL		48
+#define IMX6SX_CLK_USDHC4_SEL		49
+#define IMX6SX_CLK_SSI1_SEL		50
+#define IMX6SX_CLK_SSI2_SEL		51
+#define IMX6SX_CLK_SSI3_SEL		52
+#define IMX6SX_CLK_QSPI1_SEL		53
+#define IMX6SX_CLK_PERCLK_SEL		54
+#define IMX6SX_CLK_VID_SEL		55
+#define IMX6SX_CLK_ESAI_SEL		56
+#define IMX6SX_CLK_LDB_DI0_DIV_SEL	57
+#define IMX6SX_CLK_LDB_DI1_DIV_SEL	58
+#define IMX6SX_CLK_CAN_SEL		59
+#define IMX6SX_CLK_UART_SEL		60
+#define IMX6SX_CLK_QSPI2_SEL		61
+#define IMX6SX_CLK_LDB_DI1_SEL		62
+#define IMX6SX_CLK_LDB_DI0_SEL		63
+#define IMX6SX_CLK_SPDIF_SEL		64
+#define IMX6SX_CLK_AUDIO_SEL		65
+#define IMX6SX_CLK_ENET_PRE_SEL		66
+#define IMX6SX_CLK_ENET_SEL		67
+#define IMX6SX_CLK_M4_PRE_SEL		68
+#define IMX6SX_CLK_M4_SEL		69
+#define IMX6SX_CLK_ECSPI_SEL		70
+#define IMX6SX_CLK_LCDIF1_PRE_SEL	71
+#define IMX6SX_CLK_LCDIF2_PRE_SEL	72
+#define IMX6SX_CLK_LCDIF1_SEL		73
+#define IMX6SX_CLK_LCDIF2_SEL		74
+#define IMX6SX_CLK_DISPLAY_SEL		75
+#define IMX6SX_CLK_CSI_SEL		76
+#define IMX6SX_CLK_CKO1_SEL		77
+#define IMX6SX_CLK_CKO2_SEL		78
+#define IMX6SX_CLK_CKO			79
+#define IMX6SX_CLK_PERIPH_CLK2		80
+#define IMX6SX_CLK_PERIPH2_CLK2		81
+#define IMX6SX_CLK_IPG			82
+#define IMX6SX_CLK_GPU_CORE_PODF	83
+#define IMX6SX_CLK_GPU_AXI_PODF		84
+#define IMX6SX_CLK_LCDIF1_PODF		85
+#define IMX6SX_CLK_QSPI1_PODF		86
+#define IMX6SX_CLK_EIM_SLOW_PODF	87
+#define IMX6SX_CLK_LCDIF2_PODF		88
+#define IMX6SX_CLK_PERCLK		89
+#define IMX6SX_CLK_VID_PODF		90
+#define IMX6SX_CLK_CAN_PODF		91
+#define IMX6SX_CLK_USDHC1_PODF		92
+#define IMX6SX_CLK_USDHC2_PODF		93
+#define IMX6SX_CLK_USDHC3_PODF		94
+#define IMX6SX_CLK_USDHC4_PODF		95
+#define IMX6SX_CLK_UART_PODF		96
+#define IMX6SX_CLK_ESAI_PRED		97
+#define IMX6SX_CLK_ESAI_PODF		98
+#define IMX6SX_CLK_SSI3_PRED		99
+#define IMX6SX_CLK_SSI3_PODF		100
+#define IMX6SX_CLK_SSI1_PRED		101
+#define IMX6SX_CLK_SSI1_PODF		102
+#define IMX6SX_CLK_QSPI2_PRED		103
+#define IMX6SX_CLK_QSPI2_PODF		104
+#define IMX6SX_CLK_SSI2_PRED		105
+#define IMX6SX_CLK_SSI2_PODF		106
+#define IMX6SX_CLK_SPDIF_PRED		107
+#define IMX6SX_CLK_SPDIF_PODF		108
+#define IMX6SX_CLK_AUDIO_PRED		109
+#define IMX6SX_CLK_AUDIO_PODF		110
+#define IMX6SX_CLK_ENET_PODF		111
+#define IMX6SX_CLK_M4_PODF		112
+#define IMX6SX_CLK_ECSPI_PODF		113
+#define IMX6SX_CLK_LCDIF1_PRED		114
+#define IMX6SX_CLK_LCDIF2_PRED		115
+#define IMX6SX_CLK_DISPLAY_PODF		116
+#define IMX6SX_CLK_CSI_PODF		117
+#define IMX6SX_CLK_LDB_DI0_DIV_3_5	118
+#define IMX6SX_CLK_LDB_DI0_DIV_7	119
+#define IMX6SX_CLK_LDB_DI1_DIV_3_5	120
+#define IMX6SX_CLK_LDB_DI1_DIV_7	121
+#define IMX6SX_CLK_CKO1_PODF		122
+#define IMX6SX_CLK_CKO2_PODF		123
+#define IMX6SX_CLK_PERIPH		124
+#define IMX6SX_CLK_PERIPH2		125
+#define IMX6SX_CLK_OCRAM		126
+#define IMX6SX_CLK_AHB			127
+#define IMX6SX_CLK_MMDC_PODF		128
+#define IMX6SX_CLK_ARM			129
+#define IMX6SX_CLK_AIPS_TZ1		130
+#define IMX6SX_CLK_AIPS_TZ2		131
+#define IMX6SX_CLK_APBH_DMA		132
+#define IMX6SX_CLK_ASRC_GATE		133
+#define IMX6SX_CLK_CAAM_MEM		134
+#define IMX6SX_CLK_CAAM_ACLK		135
+#define IMX6SX_CLK_CAAM_IPG		136
+#define IMX6SX_CLK_CAN1_IPG		137
+#define IMX6SX_CLK_CAN1_SERIAL		138
+#define IMX6SX_CLK_CAN2_IPG		139
+#define IMX6SX_CLK_CAN2_SERIAL		140
+#define IMX6SX_CLK_CPU_DEBUG		141
+#define IMX6SX_CLK_DCIC1		142
+#define IMX6SX_CLK_DCIC2		143
+#define IMX6SX_CLK_AIPS_TZ3		144
+#define IMX6SX_CLK_ECSPI1		145
+#define IMX6SX_CLK_ECSPI2		146
+#define IMX6SX_CLK_ECSPI3		147
+#define IMX6SX_CLK_ECSPI4		148
+#define IMX6SX_CLK_ECSPI5		149
+#define IMX6SX_CLK_EPIT1		150
+#define IMX6SX_CLK_EPIT2		151
+#define IMX6SX_CLK_ESAI_EXTAL		152
+#define IMX6SX_CLK_WAKEUP		153
+#define IMX6SX_CLK_GPT_BUS		154
+#define IMX6SX_CLK_GPT_SERIAL		155
+#define IMX6SX_CLK_GPU			156
+#define IMX6SX_CLK_OCRAM_S		157
+#define IMX6SX_CLK_CANFD		158
+#define IMX6SX_CLK_CSI			159
+#define IMX6SX_CLK_I2C1			160
+#define IMX6SX_CLK_I2C2			161
+#define IMX6SX_CLK_I2C3			162
+#define IMX6SX_CLK_OCOTP		163
+#define IMX6SX_CLK_IOMUXC		164
+#define IMX6SX_CLK_IPMUX1		165
+#define IMX6SX_CLK_IPMUX2		166
+#define IMX6SX_CLK_IPMUX3		167
+#define IMX6SX_CLK_TZASC1		168
+#define IMX6SX_CLK_LCDIF_APB		169
+#define IMX6SX_CLK_PXP_AXI		170
+#define IMX6SX_CLK_M4			171
+#define IMX6SX_CLK_ENET			172
+#define IMX6SX_CLK_DISPLAY_AXI		173
+#define IMX6SX_CLK_LCDIF2_PIX		174
+#define IMX6SX_CLK_LCDIF1_PIX		175
+#define IMX6SX_CLK_LDB_DI0		176
+#define IMX6SX_CLK_QSPI1		177
+#define IMX6SX_CLK_MLB			178
+#define IMX6SX_CLK_MMDC_P0_FAST		179
+#define IMX6SX_CLK_MMDC_P0_IPG		180
+#define IMX6SX_CLK_AXI			181
+#define IMX6SX_CLK_PCIE_AXI		182
+#define IMX6SX_CLK_QSPI2		183
+#define IMX6SX_CLK_PER1_BCH		184
+#define IMX6SX_CLK_PER2_MAIN		185
+#define IMX6SX_CLK_PWM1			186
+#define IMX6SX_CLK_PWM2			187
+#define IMX6SX_CLK_PWM3			188
+#define IMX6SX_CLK_PWM4			189
+#define IMX6SX_CLK_GPMI_BCH_APB		190
+#define IMX6SX_CLK_GPMI_BCH		191
+#define IMX6SX_CLK_GPMI_IO		192
+#define IMX6SX_CLK_GPMI_APB		193
+#define IMX6SX_CLK_ROM			194
+#define IMX6SX_CLK_SDMA			195
+#define IMX6SX_CLK_SPBA			196
+#define IMX6SX_CLK_SPDIF		197
+#define IMX6SX_CLK_SSI1_IPG		198
+#define IMX6SX_CLK_SSI2_IPG		199
+#define IMX6SX_CLK_SSI3_IPG		200
+#define IMX6SX_CLK_SSI1			201
+#define IMX6SX_CLK_SSI2			202
+#define IMX6SX_CLK_SSI3			203
+#define IMX6SX_CLK_UART_IPG		204
+#define IMX6SX_CLK_UART_SERIAL		205
+#define IMX6SX_CLK_SAI1			206
+#define IMX6SX_CLK_SAI2			207
+#define IMX6SX_CLK_USBOH3		208
+#define IMX6SX_CLK_USDHC1		209
+#define IMX6SX_CLK_USDHC2		210
+#define IMX6SX_CLK_USDHC3		211
+#define IMX6SX_CLK_USDHC4		212
+#define IMX6SX_CLK_EIM_SLOW		213
+#define IMX6SX_CLK_PWM8			214
+#define IMX6SX_CLK_VADC			215
+#define IMX6SX_CLK_GIS			216
+#define IMX6SX_CLK_I2C4			217
+#define IMX6SX_CLK_PWM5			218
+#define IMX6SX_CLK_PWM6			219
+#define IMX6SX_CLK_PWM7			220
+#define IMX6SX_CLK_CKO1			221
+#define IMX6SX_CLK_CKO2			222
+#define IMX6SX_CLK_IPP_DI0		223
+#define IMX6SX_CLK_IPP_DI1		224
+#define IMX6SX_CLK_ENET_AHB		225
+#define IMX6SX_CLK_OCRAM_PODF		226
+#define IMX6SX_CLK_GPT_3M		227
+#define IMX6SX_CLK_ENET_PTP		228
+#define IMX6SX_CLK_ENET_PTP_REF		229
+#define IMX6SX_CLK_ENET2_REF		230
+#define IMX6SX_CLK_ENET2_REF_125M	231
+#define IMX6SX_CLK_AUDIO		232
+#define IMX6SX_CLK_LVDS1_SEL		233
+#define IMX6SX_CLK_LVDS1_OUT		234
+#define IMX6SX_CLK_ASRC_IPG		235
+#define IMX6SX_CLK_ASRC_MEM		236
+#define IMX6SX_CLK_SAI1_IPG		237
+#define IMX6SX_CLK_SAI2_IPG		238
+#define IMX6SX_CLK_ESAI_IPG		239
+#define IMX6SX_CLK_ESAI_MEM		240
+#define IMX6SX_CLK_LVDS1_IN		241
+#define IMX6SX_CLK_ANACLK1		242
+#define IMX6SX_PLL1_BYPASS_SRC		243
+#define IMX6SX_PLL2_BYPASS_SRC		244
+#define IMX6SX_PLL3_BYPASS_SRC		245
+#define IMX6SX_PLL4_BYPASS_SRC		246
+#define IMX6SX_PLL5_BYPASS_SRC		247
+#define IMX6SX_PLL6_BYPASS_SRC		248
+#define IMX6SX_PLL7_BYPASS_SRC		249
+#define IMX6SX_CLK_PLL1			250
+#define IMX6SX_CLK_PLL2			251
+#define IMX6SX_CLK_PLL3			252
+#define IMX6SX_CLK_PLL4			253
+#define IMX6SX_CLK_PLL5			254
+#define IMX6SX_CLK_PLL6			255
+#define IMX6SX_CLK_PLL7			256
+#define IMX6SX_PLL1_BYPASS		257
+#define IMX6SX_PLL2_BYPASS		258
+#define IMX6SX_PLL3_BYPASS		259
+#define IMX6SX_PLL4_BYPASS		260
+#define IMX6SX_PLL5_BYPASS		261
+#define IMX6SX_PLL6_BYPASS		262
+#define IMX6SX_PLL7_BYPASS		263
+#define IMX6SX_CLK_SPDIF_GCLK		264
+#define IMX6SX_CLK_CLK_END		265
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h
new file mode 100644
index 0000000..7909433
--- /dev/null
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -0,0 +1,262 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
+#define __DT_BINDINGS_CLOCK_IMX6UL_H
+
+#define IMX6UL_CLK_DUMMY		0
+#define IMX6UL_CLK_CKIL			1
+#define IMX6UL_CLK_CKIH			2
+#define IMX6UL_CLK_OSC			3
+#define IMX6UL_PLL1_BYPASS_SRC		4
+#define IMX6UL_PLL2_BYPASS_SRC		5
+#define IMX6UL_PLL3_BYPASS_SRC		6
+#define IMX6UL_PLL4_BYPASS_SRC		7
+#define IMX6UL_PLL5_BYPASS_SRC		8
+#define IMX6UL_PLL6_BYPASS_SRC		9
+#define IMX6UL_PLL7_BYPASS_SRC		10
+#define IMX6UL_CLK_PLL1			11
+#define IMX6UL_CLK_PLL2			12
+#define IMX6UL_CLK_PLL3			13
+#define IMX6UL_CLK_PLL4			14
+#define IMX6UL_CLK_PLL5			15
+#define IMX6UL_CLK_PLL6			16
+#define IMX6UL_CLK_PLL7			17
+#define IMX6UL_PLL1_BYPASS		18
+#define IMX6UL_PLL2_BYPASS		19
+#define IMX6UL_PLL3_BYPASS		20
+#define IMX6UL_PLL4_BYPASS		21
+#define IMX6UL_PLL5_BYPASS		22
+#define IMX6UL_PLL6_BYPASS		23
+#define IMX6UL_PLL7_BYPASS		24
+#define IMX6UL_CLK_PLL1_SYS		25
+#define IMX6UL_CLK_PLL2_BUS		26
+#define IMX6UL_CLK_PLL3_USB_OTG		27
+#define IMX6UL_CLK_PLL4_AUDIO		28
+#define IMX6UL_CLK_PLL5_VIDEO		29
+#define IMX6UL_CLK_PLL6_ENET		30
+#define IMX6UL_CLK_PLL7_USB_HOST	31
+#define IMX6UL_CLK_USBPHY1		32
+#define IMX6UL_CLK_USBPHY2		33
+#define IMX6UL_CLK_USBPHY1_GATE		34
+#define IMX6UL_CLK_USBPHY2_GATE		35
+#define IMX6UL_CLK_PLL2_PFD0		36
+#define IMX6UL_CLK_PLL2_PFD1		37
+#define IMX6UL_CLK_PLL2_PFD2		38
+#define IMX6UL_CLK_PLL2_PFD3		39
+#define IMX6UL_CLK_PLL3_PFD0		40
+#define IMX6UL_CLK_PLL3_PFD1		41
+#define IMX6UL_CLK_PLL3_PFD2		42
+#define IMX6UL_CLK_PLL3_PFD3		43
+#define IMX6UL_CLK_ENET_REF		44
+#define IMX6UL_CLK_ENET2_REF		45
+#define IMX6UL_CLK_ENET2_REF_125M	46
+#define IMX6UL_CLK_ENET_PTP_REF		47
+#define IMX6UL_CLK_ENET_PTP		48
+#define IMX6UL_CLK_PLL4_POST_DIV	49
+#define IMX6UL_CLK_PLL4_AUDIO_DIV	50
+#define IMX6UL_CLK_PLL5_POST_DIV	51
+#define IMX6UL_CLK_PLL5_VIDEO_DIV	52
+#define IMX6UL_CLK_PLL2_198M		53
+#define IMX6UL_CLK_PLL3_80M		54
+#define IMX6UL_CLK_PLL3_60M		55
+#define IMX6UL_CLK_STEP			56
+#define IMX6UL_CLK_PLL1_SW		57
+#define IMX6UL_CLK_AXI_ALT_SEL		58
+#define IMX6UL_CLK_AXI_SEL		59
+#define IMX6UL_CLK_PERIPH_PRE		60
+#define IMX6UL_CLK_PERIPH2_PRE		61
+#define IMX6UL_CLK_PERIPH_CLK2_SEL	62
+#define IMX6UL_CLK_PERIPH2_CLK2_SEL	63
+#define IMX6UL_CLK_USDHC1_SEL		64
+#define IMX6UL_CLK_USDHC2_SEL		65
+#define IMX6UL_CLK_BCH_SEL		66
+#define IMX6UL_CLK_GPMI_SEL		67
+#define IMX6UL_CLK_EIM_SLOW_SEL		68
+#define IMX6UL_CLK_SPDIF_SEL		69
+#define IMX6UL_CLK_SAI1_SEL		70
+#define IMX6UL_CLK_SAI2_SEL		71
+#define IMX6UL_CLK_SAI3_SEL		72
+#define IMX6UL_CLK_LCDIF_PRE_SEL	73
+#define IMX6UL_CLK_SIM_PRE_SEL		74
+#define IMX6UL_CLK_LDB_DI0_SEL		75
+#define IMX6UL_CLK_LDB_DI1_SEL		76
+#define IMX6UL_CLK_ENFC_SEL		77
+#define IMX6UL_CLK_CAN_SEL		78
+#define IMX6UL_CLK_ECSPI_SEL		79
+#define IMX6UL_CLK_UART_SEL		80
+#define IMX6UL_CLK_QSPI1_SEL		81
+#define IMX6UL_CLK_PERCLK_SEL		82
+#define IMX6UL_CLK_LCDIF_SEL		83
+#define IMX6UL_CLK_SIM_SEL		84
+#define IMX6UL_CLK_PERIPH		85
+#define IMX6UL_CLK_PERIPH2		86
+#define IMX6UL_CLK_LDB_DI0_DIV_3_5	87
+#define IMX6UL_CLK_LDB_DI0_DIV_7	88
+#define IMX6UL_CLK_LDB_DI1_DIV_3_5	89
+#define IMX6UL_CLK_LDB_DI1_DIV_7	90
+#define IMX6UL_CLK_LDB_DI0_DIV_SEL	91
+#define IMX6UL_CLK_LDB_DI1_DIV_SEL	92
+#define IMX6UL_CLK_ARM			93
+#define IMX6UL_CLK_PERIPH_CLK2		94
+#define IMX6UL_CLK_PERIPH2_CLK2		95
+#define IMX6UL_CLK_AHB			96
+#define IMX6UL_CLK_MMDC_PODF		97
+#define IMX6UL_CLK_AXI_PODF		98
+#define IMX6UL_CLK_PERCLK		99
+#define IMX6UL_CLK_IPG			100
+#define IMX6UL_CLK_USDHC1_PODF		101
+#define IMX6UL_CLK_USDHC2_PODF		102
+#define IMX6UL_CLK_BCH_PODF		103
+#define IMX6UL_CLK_GPMI_PODF		104
+#define IMX6UL_CLK_EIM_SLOW_PODF	105
+#define IMX6UL_CLK_SPDIF_PRED		106
+#define IMX6UL_CLK_SPDIF_PODF		107
+#define IMX6UL_CLK_SAI1_PRED		108
+#define IMX6UL_CLK_SAI1_PODF		109
+#define IMX6UL_CLK_SAI2_PRED		110
+#define IMX6UL_CLK_SAI2_PODF		111
+#define IMX6UL_CLK_SAI3_PRED		112
+#define IMX6UL_CLK_SAI3_PODF		113
+#define IMX6UL_CLK_LCDIF_PRED		114
+#define IMX6UL_CLK_LCDIF_PODF		115
+#define IMX6UL_CLK_SIM_PODF		116
+#define IMX6UL_CLK_QSPI1_PDOF		117
+#define IMX6UL_CLK_ENFC_PRED		118
+#define IMX6UL_CLK_ENFC_PODF		119
+#define IMX6UL_CLK_CAN_PODF		120
+#define IMX6UL_CLK_ECSPI_PODF		121
+#define IMX6UL_CLK_UART_PODF		122
+#define IMX6UL_CLK_ADC1			123
+#define IMX6UL_CLK_ADC2			124
+#define IMX6UL_CLK_AIPSTZ1		125
+#define IMX6UL_CLK_AIPSTZ2		126
+#define IMX6UL_CLK_AIPSTZ3		127
+#define IMX6UL_CLK_APBHDMA		128
+#define IMX6UL_CLK_ASRC_IPG		129
+#define IMX6UL_CLK_ASRC_MEM		130
+#define IMX6UL_CLK_GPMI_BCH_APB		131
+#define IMX6UL_CLK_GPMI_BCH		132
+#define IMX6UL_CLK_GPMI_IO		133
+#define IMX6UL_CLK_GPMI_APB		134
+#define IMX6UL_CLK_CAAM_MEM		135
+#define IMX6UL_CLK_CAAM_ACLK		136
+#define IMX6UL_CLK_CAAM_IPG		137
+#define IMX6UL_CLK_CSI			138
+#define IMX6UL_CLK_ECSPI1		139
+#define IMX6UL_CLK_ECSPI2		140
+#define IMX6UL_CLK_ECSPI3		141
+#define IMX6UL_CLK_ECSPI4		142
+#define IMX6UL_CLK_EIM			143
+#define IMX6UL_CLK_ENET			144
+#define IMX6UL_CLK_ENET_AHB		145
+#define IMX6UL_CLK_EPIT1		146
+#define IMX6UL_CLK_EPIT2		147
+#define IMX6UL_CLK_CAN1_IPG		148
+#define IMX6UL_CLK_CAN1_SERIAL		149
+#define IMX6UL_CLK_CAN2_IPG		150
+#define IMX6UL_CLK_CAN2_SERIAL		151
+#define IMX6UL_CLK_GPT1_BUS		152
+#define IMX6UL_CLK_GPT1_SERIAL		153
+#define IMX6UL_CLK_GPT2_BUS		154
+#define IMX6UL_CLK_GPT2_SERIAL		155
+#define IMX6UL_CLK_I2C1			156
+#define IMX6UL_CLK_I2C2			157
+#define IMX6UL_CLK_I2C3			158
+#define IMX6UL_CLK_I2C4			159
+#define IMX6UL_CLK_IOMUXC		160
+#define IMX6UL_CLK_LCDIF_APB		161
+#define IMX6UL_CLK_LCDIF_PIX		162
+#define IMX6UL_CLK_MMDC_P0_FAST		163
+#define IMX6UL_CLK_MMDC_P0_IPG		164
+#define IMX6UL_CLK_OCOTP		165
+#define IMX6UL_CLK_OCRAM		166
+#define IMX6UL_CLK_PWM1			167
+#define IMX6UL_CLK_PWM2			168
+#define IMX6UL_CLK_PWM3			169
+#define IMX6UL_CLK_PWM4			170
+#define IMX6UL_CLK_PWM5			171
+#define IMX6UL_CLK_PWM6			172
+#define IMX6UL_CLK_PWM7			173
+#define IMX6UL_CLK_PWM8			174
+#define IMX6UL_CLK_PXP			175
+#define IMX6UL_CLK_QSPI			176
+#define IMX6UL_CLK_ROM			177
+#define IMX6UL_CLK_SAI1			178
+#define IMX6UL_CLK_SAI1_IPG		179
+#define IMX6UL_CLK_SAI2			180
+#define IMX6UL_CLK_SAI2_IPG		181
+#define IMX6UL_CLK_SAI3			182
+#define IMX6UL_CLK_SAI3_IPG		183
+#define IMX6UL_CLK_SDMA			184
+#define IMX6UL_CLK_SIM			185
+#define IMX6UL_CLK_SIM_S		186
+#define IMX6UL_CLK_SPBA			187
+#define IMX6UL_CLK_SPDIF		188
+#define IMX6UL_CLK_UART1_IPG		189
+#define IMX6UL_CLK_UART1_SERIAL		190
+#define IMX6UL_CLK_UART2_IPG		191
+#define IMX6UL_CLK_UART2_SERIAL		192
+#define IMX6UL_CLK_UART3_IPG		193
+#define IMX6UL_CLK_UART3_SERIAL		194
+#define IMX6UL_CLK_UART4_IPG		195
+#define IMX6UL_CLK_UART4_SERIAL		196
+#define IMX6UL_CLK_UART5_IPG		197
+#define IMX6UL_CLK_UART5_SERIAL		198
+#define IMX6UL_CLK_UART6_IPG		199
+#define IMX6UL_CLK_UART6_SERIAL		200
+#define IMX6UL_CLK_UART7_IPG		201
+#define IMX6UL_CLK_UART7_SERIAL		202
+#define IMX6UL_CLK_UART8_IPG		203
+#define IMX6UL_CLK_UART8_SERIAL		204
+#define IMX6UL_CLK_USBOH3		205
+#define IMX6UL_CLK_USDHC1		206
+#define IMX6UL_CLK_USDHC2		207
+#define IMX6UL_CLK_WDOG1		208
+#define IMX6UL_CLK_WDOG2		209
+#define IMX6UL_CLK_WDOG3		210
+#define IMX6UL_CLK_LDB_DI0		211
+#define IMX6UL_CLK_AXI			212
+#define IMX6UL_CLK_SPDIF_GCLK		213
+#define IMX6UL_CLK_GPT_3M		214
+#define IMX6UL_CLK_SIM2			215
+#define IMX6UL_CLK_SIM1			216
+#define IMX6UL_CLK_IPP_DI0		217
+#define IMX6UL_CLK_IPP_DI1		218
+#define IMX6UL_CA7_SECONDARY_SEL	219
+#define IMX6UL_CLK_PER_BCH		220
+#define IMX6UL_CLK_CSI_SEL		221
+#define IMX6UL_CLK_CSI_PODF		222
+#define IMX6UL_CLK_PLL3_120M		223
+#define IMX6UL_CLK_KPP			224
+#define IMX6ULL_CLK_ESAI_PRED		225
+#define IMX6ULL_CLK_ESAI_PODF		226
+#define IMX6ULL_CLK_ESAI_EXTAL		227
+#define IMX6ULL_CLK_ESAI_MEM		228
+#define IMX6ULL_CLK_ESAI_IPG		229
+#define IMX6ULL_CLK_DCP_CLK		230
+#define IMX6ULL_CLK_EPDC_PRE_SEL	231
+#define IMX6ULL_CLK_EPDC_SEL		232
+#define IMX6ULL_CLK_EPDC_PODF		233
+#define IMX6ULL_CLK_EPDC_ACLK		234
+#define IMX6ULL_CLK_EPDC_PIX		235
+#define IMX6ULL_CLK_ESAI_SEL		236
+#define IMX6UL_CLK_CKO1_SEL		237
+#define IMX6UL_CLK_CKO1_PODF		238
+#define IMX6UL_CLK_CKO1			239
+#define IMX6UL_CLK_CKO2_SEL		240
+#define IMX6UL_CLK_CKO2_PODF		241
+#define IMX6UL_CLK_CKO2			242
+#define IMX6UL_CLK_CKO			243
+#define IMX6UL_CLK_GPIO1		244
+#define IMX6UL_CLK_GPIO2		245
+#define IMX6UL_CLK_GPIO3		246
+#define IMX6UL_CLK_GPIO4		247
+#define IMX6UL_CLK_GPIO5		248
+#define IMX6UL_CLK_MMDC_P1_IPG		249
+
+#define IMX6UL_CLK_END			250
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
new file mode 100644
index 0000000..b2325d3
--- /dev/null
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -0,0 +1,459 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
+#define __DT_BINDINGS_CLOCK_IMX7D_H
+
+#define IMX7D_OSC_24M_CLK		0
+#define IMX7D_PLL_ARM_MAIN		1
+#define IMX7D_PLL_ARM_MAIN_CLK		2
+#define IMX7D_PLL_ARM_MAIN_SRC		3
+#define IMX7D_PLL_ARM_MAIN_BYPASS	4
+#define IMX7D_PLL_SYS_MAIN		5
+#define IMX7D_PLL_SYS_MAIN_CLK		6
+#define IMX7D_PLL_SYS_MAIN_SRC		7
+#define IMX7D_PLL_SYS_MAIN_BYPASS	8
+#define IMX7D_PLL_SYS_MAIN_480M		9
+#define IMX7D_PLL_SYS_MAIN_240M		10
+#define IMX7D_PLL_SYS_MAIN_120M		11
+#define IMX7D_PLL_SYS_MAIN_480M_CLK	12
+#define IMX7D_PLL_SYS_MAIN_240M_CLK	13
+#define IMX7D_PLL_SYS_MAIN_120M_CLK	14
+#define IMX7D_PLL_SYS_PFD0_392M_CLK	15
+#define IMX7D_PLL_SYS_PFD0_196M		16
+#define IMX7D_PLL_SYS_PFD0_196M_CLK	17
+#define IMX7D_PLL_SYS_PFD1_332M_CLK	18
+#define IMX7D_PLL_SYS_PFD1_166M		19
+#define IMX7D_PLL_SYS_PFD1_166M_CLK	20
+#define IMX7D_PLL_SYS_PFD2_270M_CLK	21
+#define IMX7D_PLL_SYS_PFD2_135M		22
+#define IMX7D_PLL_SYS_PFD2_135M_CLK	23
+#define IMX7D_PLL_SYS_PFD3_CLK		24
+#define IMX7D_PLL_SYS_PFD4_CLK		25
+#define IMX7D_PLL_SYS_PFD5_CLK		26
+#define IMX7D_PLL_SYS_PFD6_CLK		27
+#define IMX7D_PLL_SYS_PFD7_CLK		28
+#define IMX7D_PLL_ENET_MAIN		29
+#define IMX7D_PLL_ENET_MAIN_CLK		30
+#define IMX7D_PLL_ENET_MAIN_SRC		31
+#define IMX7D_PLL_ENET_MAIN_BYPASS	32
+#define IMX7D_PLL_ENET_MAIN_500M	33
+#define IMX7D_PLL_ENET_MAIN_250M	34
+#define IMX7D_PLL_ENET_MAIN_125M	35
+#define IMX7D_PLL_ENET_MAIN_100M	36
+#define IMX7D_PLL_ENET_MAIN_50M		37
+#define IMX7D_PLL_ENET_MAIN_40M		38
+#define IMX7D_PLL_ENET_MAIN_25M		39
+#define IMX7D_PLL_ENET_MAIN_500M_CLK	40
+#define IMX7D_PLL_ENET_MAIN_250M_CLK	41
+#define IMX7D_PLL_ENET_MAIN_125M_CLK	42
+#define IMX7D_PLL_ENET_MAIN_100M_CLK	43
+#define IMX7D_PLL_ENET_MAIN_50M_CLK	44
+#define IMX7D_PLL_ENET_MAIN_40M_CLK	45
+#define IMX7D_PLL_ENET_MAIN_25M_CLK	46
+#define IMX7D_PLL_DRAM_MAIN		47
+#define IMX7D_PLL_DRAM_MAIN_CLK		48
+#define IMX7D_PLL_DRAM_MAIN_SRC		49
+#define IMX7D_PLL_DRAM_MAIN_BYPASS	50
+#define IMX7D_PLL_DRAM_MAIN_533M	51
+#define IMX7D_PLL_DRAM_MAIN_533M_CLK	52
+#define IMX7D_PLL_AUDIO_MAIN		53
+#define IMX7D_PLL_AUDIO_MAIN_CLK	54
+#define IMX7D_PLL_AUDIO_MAIN_SRC	55
+#define IMX7D_PLL_AUDIO_MAIN_BYPASS	56
+#define IMX7D_PLL_VIDEO_MAIN_CLK	57
+#define IMX7D_PLL_VIDEO_MAIN		58
+#define IMX7D_PLL_VIDEO_MAIN_SRC	59
+#define IMX7D_PLL_VIDEO_MAIN_BYPASS	60
+#define IMX7D_USB_MAIN_480M_CLK		61
+#define IMX7D_ARM_A7_ROOT_CLK		62
+#define IMX7D_ARM_A7_ROOT_SRC		63
+#define IMX7D_ARM_A7_ROOT_CG		64
+#define IMX7D_ARM_A7_ROOT_DIV		65
+#define IMX7D_ARM_M4_ROOT_CLK		66
+#define IMX7D_ARM_M4_ROOT_SRC		67
+#define IMX7D_ARM_M4_ROOT_CG		68
+#define IMX7D_ARM_M4_ROOT_DIV		69
+#define IMX7D_ARM_M0_ROOT_CLK		70	/* unused */
+#define IMX7D_ARM_M0_ROOT_SRC		71	/* unused */
+#define IMX7D_ARM_M0_ROOT_CG		72	/* unused */
+#define IMX7D_ARM_M0_ROOT_DIV		73	/* unused */
+#define IMX7D_MAIN_AXI_ROOT_CLK		74
+#define IMX7D_MAIN_AXI_ROOT_SRC		75
+#define IMX7D_MAIN_AXI_ROOT_CG		76
+#define IMX7D_MAIN_AXI_ROOT_DIV		77
+#define IMX7D_DISP_AXI_ROOT_CLK		78
+#define IMX7D_DISP_AXI_ROOT_SRC		79
+#define IMX7D_DISP_AXI_ROOT_CG		80
+#define IMX7D_DISP_AXI_ROOT_DIV		81
+#define IMX7D_ENET_AXI_ROOT_CLK		82
+#define IMX7D_ENET_AXI_ROOT_SRC		83
+#define IMX7D_ENET_AXI_ROOT_CG		84
+#define IMX7D_ENET_AXI_ROOT_DIV		85
+#define IMX7D_NAND_USDHC_BUS_ROOT_CLK	86
+#define IMX7D_NAND_USDHC_BUS_ROOT_SRC	87
+#define IMX7D_NAND_USDHC_BUS_ROOT_CG	88
+#define IMX7D_NAND_USDHC_BUS_ROOT_DIV	89
+#define IMX7D_AHB_CHANNEL_ROOT_CLK	90
+#define IMX7D_AHB_CHANNEL_ROOT_SRC	91
+#define IMX7D_AHB_CHANNEL_ROOT_CG	92
+#define IMX7D_AHB_CHANNEL_ROOT_DIV	93
+#define IMX7D_DRAM_PHYM_ROOT_CLK	94
+#define IMX7D_DRAM_PHYM_ROOT_SRC	95
+#define IMX7D_DRAM_PHYM_ROOT_CG		96
+#define IMX7D_DRAM_PHYM_ROOT_DIV	97
+#define IMX7D_DRAM_ROOT_CLK		98
+#define IMX7D_DRAM_ROOT_SRC		99
+#define IMX7D_DRAM_ROOT_CG		100
+#define IMX7D_DRAM_ROOT_DIV		101
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK	102
+#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC	103
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CG	104
+#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV	105
+#define IMX7D_DRAM_ALT_ROOT_CLK		106
+#define IMX7D_DRAM_ALT_ROOT_SRC		107
+#define IMX7D_DRAM_ALT_ROOT_CG		108
+#define IMX7D_DRAM_ALT_ROOT_DIV		109
+#define IMX7D_USB_HSIC_ROOT_CLK		110
+#define IMX7D_USB_HSIC_ROOT_SRC		111
+#define IMX7D_USB_HSIC_ROOT_CG		112
+#define IMX7D_USB_HSIC_ROOT_DIV		113
+#define IMX7D_PCIE_CTRL_ROOT_CLK	114
+#define IMX7D_PCIE_CTRL_ROOT_SRC	115
+#define IMX7D_PCIE_CTRL_ROOT_CG		116
+#define IMX7D_PCIE_CTRL_ROOT_DIV	117
+#define IMX7D_PCIE_PHY_ROOT_CLK		118
+#define IMX7D_PCIE_PHY_ROOT_SRC		119
+#define IMX7D_PCIE_PHY_ROOT_CG		120
+#define IMX7D_PCIE_PHY_ROOT_DIV		121
+#define IMX7D_EPDC_PIXEL_ROOT_CLK	122
+#define IMX7D_EPDC_PIXEL_ROOT_SRC	123
+#define IMX7D_EPDC_PIXEL_ROOT_CG	124
+#define IMX7D_EPDC_PIXEL_ROOT_DIV	125
+#define IMX7D_LCDIF_PIXEL_ROOT_CLK	126
+#define IMX7D_LCDIF_PIXEL_ROOT_SRC	127
+#define IMX7D_LCDIF_PIXEL_ROOT_CG	128
+#define IMX7D_LCDIF_PIXEL_ROOT_DIV	129
+#define IMX7D_MIPI_DSI_ROOT_CLK		130
+#define IMX7D_MIPI_DSI_ROOT_SRC		131
+#define IMX7D_MIPI_DSI_ROOT_CG		132
+#define IMX7D_MIPI_DSI_ROOT_DIV		133
+#define IMX7D_MIPI_CSI_ROOT_CLK		134
+#define IMX7D_MIPI_CSI_ROOT_SRC		135
+#define IMX7D_MIPI_CSI_ROOT_CG		136
+#define IMX7D_MIPI_CSI_ROOT_DIV		137
+#define IMX7D_MIPI_DPHY_ROOT_CLK	138
+#define IMX7D_MIPI_DPHY_ROOT_SRC	139
+#define IMX7D_MIPI_DPHY_ROOT_CG		140
+#define IMX7D_MIPI_DPHY_ROOT_DIV	141
+#define IMX7D_SAI1_ROOT_CLK		142
+#define IMX7D_SAI1_ROOT_SRC		143
+#define IMX7D_SAI1_ROOT_CG		144
+#define IMX7D_SAI1_ROOT_DIV		145
+#define IMX7D_SAI2_ROOT_CLK		146
+#define IMX7D_SAI2_ROOT_SRC		147
+#define IMX7D_SAI2_ROOT_CG		148
+#define IMX7D_SAI2_ROOT_DIV		149
+#define IMX7D_SAI3_ROOT_CLK		150
+#define IMX7D_SAI3_ROOT_SRC		151
+#define IMX7D_SAI3_ROOT_CG		152
+#define IMX7D_SAI3_ROOT_DIV		153
+#define IMX7D_SPDIF_ROOT_CLK		154
+#define IMX7D_SPDIF_ROOT_SRC		155
+#define IMX7D_SPDIF_ROOT_CG		156
+#define IMX7D_SPDIF_ROOT_DIV		157
+#define IMX7D_ENET1_REF_ROOT_CLK	158
+#define IMX7D_ENET1_REF_ROOT_SRC	159
+#define IMX7D_ENET1_REF_ROOT_CG		160
+#define IMX7D_ENET1_REF_ROOT_DIV	161
+#define IMX7D_ENET1_TIME_ROOT_CLK	162
+#define IMX7D_ENET1_TIME_ROOT_SRC	163
+#define IMX7D_ENET1_TIME_ROOT_CG	164
+#define IMX7D_ENET1_TIME_ROOT_DIV	165
+#define IMX7D_ENET2_REF_ROOT_CLK	166
+#define IMX7D_ENET2_REF_ROOT_SRC	167
+#define IMX7D_ENET2_REF_ROOT_CG		168
+#define IMX7D_ENET2_REF_ROOT_DIV	169
+#define IMX7D_ENET2_TIME_ROOT_CLK	170
+#define IMX7D_ENET2_TIME_ROOT_SRC	171
+#define IMX7D_ENET2_TIME_ROOT_CG	172
+#define IMX7D_ENET2_TIME_ROOT_DIV	173
+#define IMX7D_ENET_PHY_REF_ROOT_CLK	174
+#define IMX7D_ENET_PHY_REF_ROOT_SRC	175
+#define IMX7D_ENET_PHY_REF_ROOT_CG	176
+#define IMX7D_ENET_PHY_REF_ROOT_DIV	177
+#define IMX7D_EIM_ROOT_CLK		178
+#define IMX7D_EIM_ROOT_SRC		179
+#define IMX7D_EIM_ROOT_CG		180
+#define IMX7D_EIM_ROOT_DIV		181
+#define IMX7D_NAND_ROOT_CLK		182
+#define IMX7D_NAND_ROOT_SRC		183
+#define IMX7D_NAND_ROOT_CG		184
+#define IMX7D_NAND_ROOT_DIV		185
+#define IMX7D_QSPI_ROOT_CLK		186
+#define IMX7D_QSPI_ROOT_SRC		187
+#define IMX7D_QSPI_ROOT_CG		188
+#define IMX7D_QSPI_ROOT_DIV		189
+#define IMX7D_USDHC1_ROOT_CLK		190
+#define IMX7D_USDHC1_ROOT_SRC		191
+#define IMX7D_USDHC1_ROOT_CG		192
+#define IMX7D_USDHC1_ROOT_DIV		193
+#define IMX7D_USDHC2_ROOT_CLK		194
+#define IMX7D_USDHC2_ROOT_SRC		195
+#define IMX7D_USDHC2_ROOT_CG		196
+#define IMX7D_USDHC2_ROOT_DIV		197
+#define IMX7D_USDHC3_ROOT_CLK		198
+#define IMX7D_USDHC3_ROOT_SRC		199
+#define IMX7D_USDHC3_ROOT_CG		200
+#define IMX7D_USDHC3_ROOT_DIV		201
+#define IMX7D_CAN1_ROOT_CLK		202
+#define IMX7D_CAN1_ROOT_SRC		203
+#define IMX7D_CAN1_ROOT_CG		204
+#define IMX7D_CAN1_ROOT_DIV		205
+#define IMX7D_CAN2_ROOT_CLK		206
+#define IMX7D_CAN2_ROOT_SRC		207
+#define IMX7D_CAN2_ROOT_CG		208
+#define IMX7D_CAN2_ROOT_DIV		209
+#define IMX7D_I2C1_ROOT_CLK		210
+#define IMX7D_I2C1_ROOT_SRC		211
+#define IMX7D_I2C1_ROOT_CG		212
+#define IMX7D_I2C1_ROOT_DIV		213
+#define IMX7D_I2C2_ROOT_CLK		214
+#define IMX7D_I2C2_ROOT_SRC		215
+#define IMX7D_I2C2_ROOT_CG		216
+#define IMX7D_I2C2_ROOT_DIV		217
+#define IMX7D_I2C3_ROOT_CLK		218
+#define IMX7D_I2C3_ROOT_SRC		219
+#define IMX7D_I2C3_ROOT_CG		220
+#define IMX7D_I2C3_ROOT_DIV		221
+#define IMX7D_I2C4_ROOT_CLK		222
+#define IMX7D_I2C4_ROOT_SRC		223
+#define IMX7D_I2C4_ROOT_CG		224
+#define IMX7D_I2C4_ROOT_DIV		225
+#define IMX7D_UART1_ROOT_CLK		226
+#define IMX7D_UART1_ROOT_SRC		227
+#define IMX7D_UART1_ROOT_CG		228
+#define IMX7D_UART1_ROOT_DIV		229
+#define IMX7D_UART2_ROOT_CLK		230
+#define IMX7D_UART2_ROOT_SRC		231
+#define IMX7D_UART2_ROOT_CG		232
+#define IMX7D_UART2_ROOT_DIV		233
+#define IMX7D_UART3_ROOT_CLK		234
+#define IMX7D_UART3_ROOT_SRC		235
+#define IMX7D_UART3_ROOT_CG		236
+#define IMX7D_UART3_ROOT_DIV		237
+#define IMX7D_UART4_ROOT_CLK		238
+#define IMX7D_UART4_ROOT_SRC		239
+#define IMX7D_UART4_ROOT_CG		240
+#define IMX7D_UART4_ROOT_DIV		241
+#define IMX7D_UART5_ROOT_CLK		242
+#define IMX7D_UART5_ROOT_SRC		243
+#define IMX7D_UART5_ROOT_CG		244
+#define IMX7D_UART5_ROOT_DIV		245
+#define IMX7D_UART6_ROOT_CLK		246
+#define IMX7D_UART6_ROOT_SRC		247
+#define IMX7D_UART6_ROOT_CG		248
+#define IMX7D_UART6_ROOT_DIV		249
+#define IMX7D_UART7_ROOT_CLK		250
+#define IMX7D_UART7_ROOT_SRC		251
+#define IMX7D_UART7_ROOT_CG		252
+#define IMX7D_UART7_ROOT_DIV		253
+#define IMX7D_ECSPI1_ROOT_CLK		254
+#define IMX7D_ECSPI1_ROOT_SRC		255
+#define IMX7D_ECSPI1_ROOT_CG		256
+#define IMX7D_ECSPI1_ROOT_DIV		257
+#define IMX7D_ECSPI2_ROOT_CLK		258
+#define IMX7D_ECSPI2_ROOT_SRC		259
+#define IMX7D_ECSPI2_ROOT_CG		260
+#define IMX7D_ECSPI2_ROOT_DIV		261
+#define IMX7D_ECSPI3_ROOT_CLK		262
+#define IMX7D_ECSPI3_ROOT_SRC		263
+#define IMX7D_ECSPI3_ROOT_CG		264
+#define IMX7D_ECSPI3_ROOT_DIV		265
+#define IMX7D_ECSPI4_ROOT_CLK		266
+#define IMX7D_ECSPI4_ROOT_SRC		267
+#define IMX7D_ECSPI4_ROOT_CG		268
+#define IMX7D_ECSPI4_ROOT_DIV		269
+#define IMX7D_PWM1_ROOT_CLK		270
+#define IMX7D_PWM1_ROOT_SRC		271
+#define IMX7D_PWM1_ROOT_CG		272
+#define IMX7D_PWM1_ROOT_DIV		273
+#define IMX7D_PWM2_ROOT_CLK		274
+#define IMX7D_PWM2_ROOT_SRC		275
+#define IMX7D_PWM2_ROOT_CG		276
+#define IMX7D_PWM2_ROOT_DIV		277
+#define IMX7D_PWM3_ROOT_CLK		278
+#define IMX7D_PWM3_ROOT_SRC		279
+#define IMX7D_PWM3_ROOT_CG		280
+#define IMX7D_PWM3_ROOT_DIV		281
+#define IMX7D_PWM4_ROOT_CLK		282
+#define IMX7D_PWM4_ROOT_SRC		283
+#define IMX7D_PWM4_ROOT_CG		284
+#define IMX7D_PWM4_ROOT_DIV		285
+#define IMX7D_FLEXTIMER1_ROOT_CLK	286
+#define IMX7D_FLEXTIMER1_ROOT_SRC	287
+#define IMX7D_FLEXTIMER1_ROOT_CG	288
+#define IMX7D_FLEXTIMER1_ROOT_DIV	289
+#define IMX7D_FLEXTIMER2_ROOT_CLK	290
+#define IMX7D_FLEXTIMER2_ROOT_SRC	291
+#define IMX7D_FLEXTIMER2_ROOT_CG	292
+#define IMX7D_FLEXTIMER2_ROOT_DIV	293
+#define IMX7D_SIM1_ROOT_CLK		294
+#define IMX7D_SIM1_ROOT_SRC		295
+#define IMX7D_SIM1_ROOT_CG		296
+#define IMX7D_SIM1_ROOT_DIV		297
+#define IMX7D_SIM2_ROOT_CLK		298
+#define IMX7D_SIM2_ROOT_SRC		299
+#define IMX7D_SIM2_ROOT_CG		300
+#define IMX7D_SIM2_ROOT_DIV		301
+#define IMX7D_GPT1_ROOT_CLK		302
+#define IMX7D_GPT1_ROOT_SRC		303
+#define IMX7D_GPT1_ROOT_CG		304
+#define IMX7D_GPT1_ROOT_DIV		305
+#define IMX7D_GPT2_ROOT_CLK		306
+#define IMX7D_GPT2_ROOT_SRC		307
+#define IMX7D_GPT2_ROOT_CG		308
+#define IMX7D_GPT2_ROOT_DIV		309
+#define IMX7D_GPT3_ROOT_CLK		310
+#define IMX7D_GPT3_ROOT_SRC		311
+#define IMX7D_GPT3_ROOT_CG		312
+#define IMX7D_GPT3_ROOT_DIV		313
+#define IMX7D_GPT4_ROOT_CLK		314
+#define IMX7D_GPT4_ROOT_SRC		315
+#define IMX7D_GPT4_ROOT_CG		316
+#define IMX7D_GPT4_ROOT_DIV		317
+#define IMX7D_TRACE_ROOT_CLK		318
+#define IMX7D_TRACE_ROOT_SRC		319
+#define IMX7D_TRACE_ROOT_CG		320
+#define IMX7D_TRACE_ROOT_DIV		321
+#define IMX7D_WDOG1_ROOT_CLK		322
+#define IMX7D_WDOG_ROOT_SRC		323
+#define IMX7D_WDOG_ROOT_CG		324
+#define IMX7D_WDOG_ROOT_DIV		325
+#define IMX7D_CSI_MCLK_ROOT_CLK		326
+#define IMX7D_CSI_MCLK_ROOT_SRC		327
+#define IMX7D_CSI_MCLK_ROOT_CG		328
+#define IMX7D_CSI_MCLK_ROOT_DIV		329
+#define IMX7D_AUDIO_MCLK_ROOT_CLK	330
+#define IMX7D_AUDIO_MCLK_ROOT_SRC	331
+#define IMX7D_AUDIO_MCLK_ROOT_CG	332
+#define IMX7D_AUDIO_MCLK_ROOT_DIV	333
+#define IMX7D_WRCLK_ROOT_CLK		334
+#define IMX7D_WRCLK_ROOT_SRC		335
+#define IMX7D_WRCLK_ROOT_CG		336
+#define IMX7D_WRCLK_ROOT_DIV		337
+#define IMX7D_CLKO1_ROOT_SRC		338
+#define IMX7D_CLKO1_ROOT_CG		339
+#define IMX7D_CLKO1_ROOT_DIV		340
+#define IMX7D_CLKO2_ROOT_SRC		341
+#define IMX7D_CLKO2_ROOT_CG		342
+#define IMX7D_CLKO2_ROOT_DIV		343
+#define IMX7D_MAIN_AXI_ROOT_PRE_DIV	344
+#define IMX7D_DISP_AXI_ROOT_PRE_DIV	345
+#define IMX7D_ENET_AXI_ROOT_PRE_DIV	346
+#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
+#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV	348
+#define IMX7D_USB_HSIC_ROOT_PRE_DIV	349
+#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV	350
+#define IMX7D_PCIE_PHY_ROOT_PRE_DIV	351
+#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV	352
+#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV	353
+#define IMX7D_MIPI_DSI_ROOT_PRE_DIV	354
+#define IMX7D_MIPI_CSI_ROOT_PRE_DIV	355
+#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV	356
+#define IMX7D_SAI1_ROOT_PRE_DIV		357
+#define IMX7D_SAI2_ROOT_PRE_DIV		358
+#define IMX7D_SAI3_ROOT_PRE_DIV		359
+#define IMX7D_SPDIF_ROOT_PRE_DIV	360
+#define IMX7D_ENET1_REF_ROOT_PRE_DIV	361
+#define IMX7D_ENET1_TIME_ROOT_PRE_DIV	362
+#define IMX7D_ENET2_REF_ROOT_PRE_DIV	363
+#define IMX7D_ENET2_TIME_ROOT_PRE_DIV	364
+#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
+#define IMX7D_EIM_ROOT_PRE_DIV		366
+#define IMX7D_NAND_ROOT_PRE_DIV		367
+#define IMX7D_QSPI_ROOT_PRE_DIV		368
+#define IMX7D_USDHC1_ROOT_PRE_DIV	369
+#define IMX7D_USDHC2_ROOT_PRE_DIV	370
+#define IMX7D_USDHC3_ROOT_PRE_DIV	371
+#define IMX7D_CAN1_ROOT_PRE_DIV		372
+#define IMX7D_CAN2_ROOT_PRE_DIV		373
+#define IMX7D_I2C1_ROOT_PRE_DIV		374
+#define IMX7D_I2C2_ROOT_PRE_DIV		375
+#define IMX7D_I2C3_ROOT_PRE_DIV		376
+#define IMX7D_I2C4_ROOT_PRE_DIV		377
+#define IMX7D_UART1_ROOT_PRE_DIV	378
+#define IMX7D_UART2_ROOT_PRE_DIV	379
+#define IMX7D_UART3_ROOT_PRE_DIV	380
+#define IMX7D_UART4_ROOT_PRE_DIV	381
+#define IMX7D_UART5_ROOT_PRE_DIV	382
+#define IMX7D_UART6_ROOT_PRE_DIV	383
+#define IMX7D_UART7_ROOT_PRE_DIV	384
+#define IMX7D_ECSPI1_ROOT_PRE_DIV	385
+#define IMX7D_ECSPI2_ROOT_PRE_DIV	386
+#define IMX7D_ECSPI3_ROOT_PRE_DIV	387
+#define IMX7D_ECSPI4_ROOT_PRE_DIV	388
+#define IMX7D_PWM1_ROOT_PRE_DIV		389
+#define IMX7D_PWM2_ROOT_PRE_DIV		390
+#define IMX7D_PWM3_ROOT_PRE_DIV		391
+#define IMX7D_PWM4_ROOT_PRE_DIV		392
+#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV	393
+#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV	394
+#define IMX7D_SIM1_ROOT_PRE_DIV		395
+#define IMX7D_SIM2_ROOT_PRE_DIV		396
+#define IMX7D_GPT1_ROOT_PRE_DIV		397
+#define IMX7D_GPT2_ROOT_PRE_DIV		398
+#define IMX7D_GPT3_ROOT_PRE_DIV		399
+#define IMX7D_GPT4_ROOT_PRE_DIV		400
+#define IMX7D_TRACE_ROOT_PRE_DIV	401
+#define IMX7D_WDOG_ROOT_PRE_DIV		402
+#define IMX7D_CSI_MCLK_ROOT_PRE_DIV	403
+#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV	404
+#define IMX7D_WRCLK_ROOT_PRE_DIV	405
+#define IMX7D_CLKO1_ROOT_PRE_DIV	406
+#define IMX7D_CLKO2_ROOT_PRE_DIV	407
+#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
+#define IMX7D_DRAM_ALT_ROOT_PRE_DIV	409
+#define IMX7D_LVDS1_IN_CLK		410
+#define IMX7D_LVDS1_OUT_SEL		411
+#define IMX7D_LVDS1_OUT_CLK		412
+#define IMX7D_CLK_DUMMY			413
+#define IMX7D_GPT_3M_CLK		414
+#define IMX7D_OCRAM_CLK			415
+#define IMX7D_OCRAM_S_CLK		416
+#define IMX7D_WDOG2_ROOT_CLK		417
+#define IMX7D_WDOG3_ROOT_CLK		418
+#define IMX7D_WDOG4_ROOT_CLK		419
+#define IMX7D_SDMA_CORE_CLK		420
+#define IMX7D_USB1_MAIN_480M_CLK	421
+#define IMX7D_USB_CTRL_CLK		422
+#define IMX7D_USB_PHY1_CLK		423
+#define IMX7D_USB_PHY2_CLK		424
+#define IMX7D_IPG_ROOT_CLK		425
+#define IMX7D_SAI1_IPG_CLK		426
+#define IMX7D_SAI2_IPG_CLK		427
+#define IMX7D_SAI3_IPG_CLK		428
+#define IMX7D_PLL_AUDIO_TEST_DIV	429
+#define IMX7D_PLL_AUDIO_POST_DIV	430
+#define IMX7D_PLL_VIDEO_TEST_DIV	431
+#define IMX7D_PLL_VIDEO_POST_DIV	432
+#define IMX7D_MU_ROOT_CLK		433
+#define IMX7D_SEMA4_HS_ROOT_CLK		434
+#define IMX7D_PLL_DRAM_TEST_DIV		435
+#define IMX7D_ADC_ROOT_CLK		436
+#define IMX7D_CLK_ARM			437
+#define IMX7D_CKIL			438
+#define IMX7D_OCOTP_CLK			439
+#define IMX7D_NAND_RAWNAND_CLK		440
+#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
+#define IMX7D_SNVS_CLK			442
+#define IMX7D_CAAM_CLK			443
+#define IMX7D_KPP_ROOT_CLK		444
+#define IMX7D_CLK_END			445
+#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
new file mode 100644
index 0000000..0a955df
--- /dev/null
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
+#define __DT_BINDINGS_CLOCK_IMX7ULP_H
+
+#define IMX7ULP_CLK_DUMMY		0
+#define IMX7ULP_CLK_CKIL		1
+#define IMX7ULP_CLK_OSC			2
+#define IMX7ULP_CLK_FIRC		3
+
+/* SCG1 */
+#define IMX7ULP_CLK_SPLL_PRE_SEL	4
+#define IMX7ULP_CLK_SPLL_PRE_DIV	5
+#define IMX7ULP_CLK_SPLL		6
+#define IMX7ULP_CLK_SPLL_POST_DIV1	7
+#define IMX7ULP_CLK_SPLL_POST_DIV2	8
+#define IMX7ULP_CLK_SPLL_PFD0		9
+#define IMX7ULP_CLK_SPLL_PFD1		10
+#define IMX7ULP_CLK_SPLL_PFD2		11
+#define IMX7ULP_CLK_SPLL_PFD3		12
+#define IMX7ULP_CLK_SPLL_PFD_SEL	13
+#define IMX7ULP_CLK_SPLL_SEL		14
+#define IMX7ULP_CLK_APLL_PRE_SEL	15
+#define IMX7ULP_CLK_APLL_PRE_DIV	16
+#define IMX7ULP_CLK_APLL		17
+#define IMX7ULP_CLK_APLL_POST_DIV1	18
+#define IMX7ULP_CLK_APLL_POST_DIV2	19
+#define IMX7ULP_CLK_APLL_PFD0		20
+#define IMX7ULP_CLK_APLL_PFD1		21
+#define IMX7ULP_CLK_APLL_PFD2		22
+#define IMX7ULP_CLK_APLL_PFD3		23
+#define IMX7ULP_CLK_APLL_PFD_SEL	24
+#define IMX7ULP_CLK_APLL_SEL		25
+#define IMX7ULP_CLK_UPLL		26
+#define IMX7ULP_CLK_SYS_SEL		27
+#define IMX7ULP_CLK_CORE_DIV		28
+#define IMX7ULP_CLK_BUS_DIV		29
+#define IMX7ULP_CLK_PLAT_DIV		30
+#define IMX7ULP_CLK_DDR_SEL		31
+#define IMX7ULP_CLK_DDR_DIV		32
+#define IMX7ULP_CLK_NIC_SEL		33
+#define IMX7ULP_CLK_NIC0_DIV		34
+#define IMX7ULP_CLK_GPU_DIV		35
+#define IMX7ULP_CLK_NIC1_DIV		36
+#define IMX7ULP_CLK_NIC1_BUS_DIV	37
+#define IMX7ULP_CLK_NIC1_EXT_DIV	38
+
+/* PCG2 */
+#define IMX7ULP_CLK_DMA1		39
+#define IMX7ULP_CLK_RGPIO2P1		40
+#define IMX7ULP_CLK_FLEXBUS		41
+#define IMX7ULP_CLK_SEMA42_1		42
+#define IMX7ULP_CLK_DMA_MUX1		43
+#define IMX7ULP_CLK_SNVS		44
+#define IMX7ULP_CLK_CAAM		45
+#define IMX7ULP_CLK_LPTPM4		46
+#define IMX7ULP_CLK_LPTPM5		47
+#define IMX7ULP_CLK_LPIT1		48
+#define IMX7ULP_CLK_LPSPI2		49
+#define IMX7ULP_CLK_LPSPI3		50
+#define IMX7ULP_CLK_LPI2C4		51
+#define IMX7ULP_CLK_LPI2C5		52
+#define IMX7ULP_CLK_LPUART4		53
+#define IMX7ULP_CLK_LPUART5		54
+#define IMX7ULP_CLK_FLEXIO1		55
+#define IMX7ULP_CLK_USB0		56
+#define IMX7ULP_CLK_USB1		57
+#define IMX7ULP_CLK_USB_PHY		58
+#define IMX7ULP_CLK_USB_PL301		59
+#define IMX7ULP_CLK_USDHC0		60
+#define IMX7ULP_CLK_USDHC1		61
+#define IMX7ULP_CLK_WDG1		62
+#define IMX7ULP_CLK_WDG2		63
+
+/* PCG3 */
+#define IMX7ULP_CLK_LPTPM6		64
+#define IMX7ULP_CLK_LPTPM7		65
+#define IMX7ULP_CLK_LPI2C6		66
+#define IMX7ULP_CLK_LPI2C7		67
+#define IMX7ULP_CLK_LPUART6		68
+#define IMX7ULP_CLK_LPUART7		69
+#define IMX7ULP_CLK_VIU			70
+#define IMX7ULP_CLK_DSI			71
+#define IMX7ULP_CLK_LCDIF		72
+#define IMX7ULP_CLK_MMDC		73
+#define IMX7ULP_CLK_PCTLC		74
+#define IMX7ULP_CLK_PCTLD		75
+#define IMX7ULP_CLK_PCTLE		76
+#define IMX7ULP_CLK_PCTLF		77
+#define IMX7ULP_CLK_GPU3D		78
+#define IMX7ULP_CLK_GPU2D		79
+
+#define IMX7ULP_CLK_MIPI_PLL		80
+#define IMX7ULP_CLK_SIRC		81
+
+#define IMX7ULP_CLK_SCG1_CLKOUT		82
+
+#define IMX7ULP_CLK_END			83
+
+/*cm4 clocks*/
+#define IMX7ULP_CM4_CLK_DUMMY		0
+#define IMX7ULP_CM4_CLK_CKIL		1
+#define IMX7ULP_CM4_CLK_OSC		2
+#define IMX7ULP_CM4_CLK_FIRC		3
+#define IMX7ULP_CM4_CLK_SIRC		4
+
+/* SCG0 */
+#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL	5
+#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV	6
+#define IMX7ULP_CM4_CLK_SPLL		7
+#define IMX7ULP_CM4_CLK_SPLL_VCO	8
+#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1	9
+#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2	10
+#define IMX7ULP_CM4_CLK_SPLL_PFD0	11
+#define IMX7ULP_CM4_CLK_SPLL_PFD1	12
+#define IMX7ULP_CM4_CLK_SPLL_PFD2	13
+#define IMX7ULP_CM4_CLK_SPLL_PFD3	14
+#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL	15
+#define IMX7ULP_CM4_CLK_SPLL_PFD	16
+#define IMX7ULP_CM4_CLK_SPLL_SEL	17
+#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL	18
+#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV	19
+#define IMX7ULP_CM4_CLK_APLL		20
+#define IMX7ULP_CM4_CLK_APLL_VCO	21
+#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1	22
+#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2	23
+#define IMX7ULP_CM4_CLK_APLL_PFD0	24
+#define IMX7ULP_CM4_CLK_APLL_PFD1	25
+#define IMX7ULP_CM4_CLK_APLL_PFD2	26
+#define IMX7ULP_CM4_CLK_APLL_PFD3	27
+#define IMX7ULP_CM4_CLK_APLL_PFD_SEL	28
+#define IMX7ULP_CM4_CLK_APLL_PFD	29
+#define IMX7ULP_CM4_CLK_APLL_SEL	30
+#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV	31
+#define IMX7ULP_CM4_CLK_SYS_SEL		32
+#define IMX7ULP_CM4_CLK_CORE_DIV	33
+#define IMX7ULP_CM4_CLK_BUS_DIV		34
+#define IMX7ULP_CM4_CLK_PLAT_DIV	35
+#define IMX7ULP_CM4_CLK_SLOW_DIV	36
+
+#define IMX7ULP_CM4_CLK_SAI0_SEL	37
+#define IMX7ULP_CM4_CLK_SAI0_DIV	38
+#define IMX7ULP_CM4_CLK_SAI0_ROOT	39
+#define IMX7ULP_CM4_CLK_SAI0_IPG	40
+#define IMX7ULP_CM4_CLK_SAI1_SEL	41
+#define IMX7ULP_CM4_CLK_SAI1_DIV	42
+#define IMX7ULP_CM4_CLK_SAI1_ROOT	43
+#define IMX7ULP_CM4_CLK_SAI1_IPG	44
+
+#define IMX7ULP_CLK_SCG0_CLKOUT		45
+
+#define IMX7ULP_CM4_CLK_END		46
+
+#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
new file mode 100644
index 0000000..07e6c68
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
+#define __DT_BINDINGS_CLOCK_IMX8MM_H
+
+#define IMX8MM_CLK_DUMMY			0
+#define IMX8MM_CLK_32K				1
+#define IMX8MM_CLK_24M				2
+#define IMX8MM_OSC_HDMI_CLK			3
+#define IMX8MM_CLK_EXT1				4
+#define IMX8MM_CLK_EXT2				5
+#define IMX8MM_CLK_EXT3				6
+#define IMX8MM_CLK_EXT4				7
+#define IMX8MM_AUDIO_PLL1_REF_SEL		8
+#define IMX8MM_AUDIO_PLL2_REF_SEL		9
+#define IMX8MM_VIDEO_PLL1_REF_SEL		10
+#define IMX8MM_DRAM_PLL_REF_SEL			11
+#define IMX8MM_GPU_PLL_REF_SEL			12
+#define IMX8MM_VPU_PLL_REF_SEL			13
+#define IMX8MM_ARM_PLL_REF_SEL			14
+#define IMX8MM_SYS_PLL1_REF_SEL			15
+#define IMX8MM_SYS_PLL2_REF_SEL			16
+#define IMX8MM_SYS_PLL3_REF_SEL			17
+#define IMX8MM_AUDIO_PLL1			18
+#define IMX8MM_AUDIO_PLL2			19
+#define IMX8MM_VIDEO_PLL1			20
+#define IMX8MM_DRAM_PLL				21
+#define IMX8MM_GPU_PLL				22
+#define IMX8MM_VPU_PLL				23
+#define IMX8MM_ARM_PLL				24
+#define IMX8MM_SYS_PLL1				25
+#define IMX8MM_SYS_PLL2				26
+#define IMX8MM_SYS_PLL3				27
+#define IMX8MM_AUDIO_PLL1_BYPASS		28
+#define IMX8MM_AUDIO_PLL2_BYPASS		29
+#define IMX8MM_VIDEO_PLL1_BYPASS		30
+#define IMX8MM_DRAM_PLL_BYPASS			31
+#define IMX8MM_GPU_PLL_BYPASS			32
+#define IMX8MM_VPU_PLL_BYPASS			33
+#define IMX8MM_ARM_PLL_BYPASS			34
+#define IMX8MM_SYS_PLL1_BYPASS			35
+#define IMX8MM_SYS_PLL2_BYPASS			36
+#define IMX8MM_SYS_PLL3_BYPASS			37
+#define IMX8MM_AUDIO_PLL1_OUT			38
+#define IMX8MM_AUDIO_PLL2_OUT			39
+#define IMX8MM_VIDEO_PLL1_OUT			40
+#define IMX8MM_DRAM_PLL_OUT			41
+#define IMX8MM_GPU_PLL_OUT			42
+#define IMX8MM_VPU_PLL_OUT			43
+#define IMX8MM_ARM_PLL_OUT			44
+#define IMX8MM_SYS_PLL1_OUT			45
+#define IMX8MM_SYS_PLL2_OUT			46
+#define IMX8MM_SYS_PLL3_OUT			47
+#define IMX8MM_SYS_PLL1_40M			48
+#define IMX8MM_SYS_PLL1_80M			49
+#define IMX8MM_SYS_PLL1_100M			50
+#define IMX8MM_SYS_PLL1_133M			51
+#define IMX8MM_SYS_PLL1_160M			52
+#define IMX8MM_SYS_PLL1_200M			53
+#define IMX8MM_SYS_PLL1_266M			54
+#define IMX8MM_SYS_PLL1_400M			55
+#define IMX8MM_SYS_PLL1_800M			56
+#define IMX8MM_SYS_PLL2_50M			57
+#define IMX8MM_SYS_PLL2_100M			58
+#define IMX8MM_SYS_PLL2_125M			59
+#define IMX8MM_SYS_PLL2_166M			60
+#define IMX8MM_SYS_PLL2_200M			61
+#define IMX8MM_SYS_PLL2_250M			62
+#define IMX8MM_SYS_PLL2_333M			63
+#define IMX8MM_SYS_PLL2_500M			64
+#define IMX8MM_SYS_PLL2_1000M			65
+
+/* core */
+#define IMX8MM_CLK_A53_SRC			66
+#define IMX8MM_CLK_M4_SRC			67
+#define IMX8MM_CLK_VPU_SRC			68
+#define IMX8MM_CLK_GPU3D_SRC			69
+#define IMX8MM_CLK_GPU2D_SRC			70
+#define IMX8MM_CLK_A53_CG			71
+#define IMX8MM_CLK_M4_CG			72
+#define IMX8MM_CLK_VPU_CG			73
+#define IMX8MM_CLK_GPU3D_CG			74
+#define IMX8MM_CLK_GPU2D_CG			75
+#define IMX8MM_CLK_A53_DIV			76
+#define IMX8MM_CLK_M4_DIV			77
+#define IMX8MM_CLK_VPU_DIV			78
+#define IMX8MM_CLK_GPU3D_DIV			79
+#define IMX8MM_CLK_GPU2D_DIV			80
+
+/* bus */
+#define IMX8MM_CLK_MAIN_AXI			81
+#define IMX8MM_CLK_ENET_AXI			82
+#define IMX8MM_CLK_NAND_USDHC_BUS		83
+#define IMX8MM_CLK_VPU_BUS			84
+#define IMX8MM_CLK_DISP_AXI			85
+#define IMX8MM_CLK_DISP_APB			86
+#define IMX8MM_CLK_DISP_RTRM			87
+#define IMX8MM_CLK_USB_BUS			88
+#define IMX8MM_CLK_GPU_AXI			89
+#define IMX8MM_CLK_GPU_AHB			90
+#define IMX8MM_CLK_NOC				91
+#define IMX8MM_CLK_NOC_APB			92
+
+#define IMX8MM_CLK_AHB				93
+#define IMX8MM_CLK_AUDIO_AHB			94
+#define IMX8MM_CLK_IPG_ROOT			95
+#define IMX8MM_CLK_IPG_AUDIO_ROOT		96
+
+#define IMX8MM_CLK_DRAM_ALT			97
+#define IMX8MM_CLK_DRAM_APB			98
+#define IMX8MM_CLK_VPU_G1			99
+#define IMX8MM_CLK_VPU_G2			100
+#define IMX8MM_CLK_DISP_DTRC			101
+#define IMX8MM_CLK_DISP_DC8000			102
+#define IMX8MM_CLK_PCIE1_CTRL			103
+#define IMX8MM_CLK_PCIE1_PHY			104
+#define IMX8MM_CLK_PCIE1_AUX			105
+#define IMX8MM_CLK_DC_PIXEL			106
+#define IMX8MM_CLK_LCDIF_PIXEL			107
+#define IMX8MM_CLK_SAI1				108
+#define IMX8MM_CLK_SAI2				109
+#define IMX8MM_CLK_SAI3				110
+#define IMX8MM_CLK_SAI4				111
+#define IMX8MM_CLK_SAI5				112
+#define IMX8MM_CLK_SAI6				113
+#define IMX8MM_CLK_SPDIF1			114
+#define IMX8MM_CLK_SPDIF2			115
+#define IMX8MM_CLK_ENET_REF			116
+#define IMX8MM_CLK_ENET_TIMER			117
+#define IMX8MM_CLK_ENET_PHY_REF			118
+#define IMX8MM_CLK_NAND				119
+#define IMX8MM_CLK_QSPI				120
+#define IMX8MM_CLK_USDHC1			121
+#define IMX8MM_CLK_USDHC2			122
+#define IMX8MM_CLK_I2C1				123
+#define IMX8MM_CLK_I2C2				124
+#define IMX8MM_CLK_I2C3				125
+#define IMX8MM_CLK_I2C4				126
+#define IMX8MM_CLK_UART1			127
+#define IMX8MM_CLK_UART2			128
+#define IMX8MM_CLK_UART3			129
+#define IMX8MM_CLK_UART4			130
+#define IMX8MM_CLK_USB_CORE_REF			131
+#define IMX8MM_CLK_USB_PHY_REF			132
+#define IMX8MM_CLK_ECSPI1			133
+#define IMX8MM_CLK_ECSPI2			134
+#define IMX8MM_CLK_PWM1				135
+#define IMX8MM_CLK_PWM2				136
+#define IMX8MM_CLK_PWM3				137
+#define IMX8MM_CLK_PWM4				138
+#define IMX8MM_CLK_GPT1				139
+#define IMX8MM_CLK_WDOG				140
+#define IMX8MM_CLK_WRCLK			141
+#define IMX8MM_CLK_DSI_CORE			142
+#define IMX8MM_CLK_DSI_PHY_REF			143
+#define IMX8MM_CLK_DSI_DBI			144
+#define IMX8MM_CLK_USDHC3			145
+#define IMX8MM_CLK_CSI1_CORE			146
+#define IMX8MM_CLK_CSI1_PHY_REF			147
+#define IMX8MM_CLK_CSI1_ESC			148
+#define IMX8MM_CLK_CSI2_CORE			149
+#define IMX8MM_CLK_CSI2_PHY_REF			150
+#define IMX8MM_CLK_CSI2_ESC			151
+#define IMX8MM_CLK_PCIE2_CTRL			152
+#define IMX8MM_CLK_PCIE2_PHY			153
+#define IMX8MM_CLK_PCIE2_AUX			154
+#define IMX8MM_CLK_ECSPI3			155
+#define IMX8MM_CLK_PDM				156
+#define IMX8MM_CLK_VPU_H1			157
+#define IMX8MM_CLK_CLKO1			158
+
+#define IMX8MM_CLK_ECSPI1_ROOT			159
+#define IMX8MM_CLK_ECSPI2_ROOT			160
+#define IMX8MM_CLK_ECSPI3_ROOT			161
+#define IMX8MM_CLK_ENET1_ROOT			162
+#define IMX8MM_CLK_GPT1_ROOT			163
+#define IMX8MM_CLK_I2C1_ROOT			164
+#define IMX8MM_CLK_I2C2_ROOT			165
+#define IMX8MM_CLK_I2C3_ROOT			166
+#define IMX8MM_CLK_I2C4_ROOT			167
+#define IMX8MM_CLK_OCOTP_ROOT			168
+#define IMX8MM_CLK_PCIE1_ROOT			169
+#define IMX8MM_CLK_PWM1_ROOT			170
+#define IMX8MM_CLK_PWM2_ROOT			171
+#define IMX8MM_CLK_PWM3_ROOT			172
+#define IMX8MM_CLK_PWM4_ROOT			173
+#define IMX8MM_CLK_QSPI_ROOT			174
+#define IMX8MM_CLK_NAND_ROOT			175
+#define IMX8MM_CLK_SAI1_ROOT			176
+#define IMX8MM_CLK_SAI1_IPG			177
+#define IMX8MM_CLK_SAI2_ROOT			178
+#define IMX8MM_CLK_SAI2_IPG			179
+#define IMX8MM_CLK_SAI3_ROOT			180
+#define IMX8MM_CLK_SAI3_IPG			181
+#define IMX8MM_CLK_SAI4_ROOT			182
+#define IMX8MM_CLK_SAI4_IPG			183
+#define IMX8MM_CLK_SAI5_ROOT			184
+#define IMX8MM_CLK_SAI5_IPG			185
+#define IMX8MM_CLK_SAI6_ROOT			186
+#define IMX8MM_CLK_SAI6_IPG			187
+#define IMX8MM_CLK_UART1_ROOT			188
+#define IMX8MM_CLK_UART2_ROOT			189
+#define IMX8MM_CLK_UART3_ROOT			190
+#define IMX8MM_CLK_UART4_ROOT			191
+#define IMX8MM_CLK_USB1_CTRL_ROOT		192
+#define IMX8MM_CLK_GPU3D_ROOT			193
+#define IMX8MM_CLK_USDHC1_ROOT			194
+#define IMX8MM_CLK_USDHC2_ROOT			195
+#define IMX8MM_CLK_WDOG1_ROOT			196
+#define IMX8MM_CLK_WDOG2_ROOT			197
+#define IMX8MM_CLK_WDOG3_ROOT			198
+#define IMX8MM_CLK_VPU_G1_ROOT			199
+#define IMX8MM_CLK_GPU_BUS_ROOT			200
+#define IMX8MM_CLK_VPU_H1_ROOT			201
+#define IMX8MM_CLK_VPU_G2_ROOT			202
+#define IMX8MM_CLK_PDM_ROOT			203
+#define IMX8MM_CLK_DISP_ROOT			204
+#define IMX8MM_CLK_DISP_AXI_ROOT		205
+#define IMX8MM_CLK_DISP_APB_ROOT		206
+#define IMX8MM_CLK_DISP_RTRM_ROOT		207
+#define IMX8MM_CLK_USDHC3_ROOT			208
+#define IMX8MM_CLK_TMU_ROOT			209
+#define IMX8MM_CLK_VPU_DEC_ROOT			210
+#define IMX8MM_CLK_SDMA1_ROOT			211
+#define IMX8MM_CLK_SDMA2_ROOT			212
+#define IMX8MM_CLK_SDMA3_ROOT			213
+#define IMX8MM_CLK_GPT_3M			214
+#define IMX8MM_CLK_ARM				215
+#define IMX8MM_CLK_PDM_IPG			216
+#define IMX8MM_CLK_GPU2D_ROOT			217
+#define IMX8MM_CLK_MU_ROOT			218
+#define IMX8MM_CLK_CSI1_ROOT			219
+
+#define IMX8MM_CLK_DRAM_CORE			220
+#define IMX8MM_CLK_DRAM_ALT_ROOT		221
+
+#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK	222
+
+#define IMX8MM_CLK_GPIO1_ROOT			223
+#define IMX8MM_CLK_GPIO2_ROOT			224
+#define IMX8MM_CLK_GPIO3_ROOT			225
+#define IMX8MM_CLK_GPIO4_ROOT			226
+#define IMX8MM_CLK_GPIO5_ROOT			227
+
+#define IMX8MM_CLK_SNVS_ROOT			228
+#define IMX8MM_CLK_GIC				229
+
+#define IMX8MM_CLK_END				230
+
+#endif
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
new file mode 100644
index 0000000..11dcafc
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -0,0 +1,612 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
+#define __DT_BINDINGS_CLOCK_IMX8MQ_H
+
+#define IMX8MQ_CLK_DUMMY		0
+#define IMX8MQ_CLK_32K			1
+#define IMX8MQ_CLK_25M			2
+#define IMX8MQ_CLK_27M			3
+#define IMX8MQ_CLK_EXT1			4
+#define IMX8MQ_CLK_EXT2			5
+#define IMX8MQ_CLK_EXT3			6
+#define IMX8MQ_CLK_EXT4			7
+
+/* ANAMIX PLL clocks */
+/* FRAC PLLs */
+/* ARM PLL */
+#define IMX8MQ_ARM_PLL_REF_SEL		8
+#define IMX8MQ_ARM_PLL_REF_DIV		9
+#define IMX8MQ_ARM_PLL			10
+#define IMX8MQ_ARM_PLL_BYPASS		11
+#define IMX8MQ_ARM_PLL_OUT		12
+
+/* GPU PLL */
+#define IMX8MQ_GPU_PLL_REF_SEL		13
+#define IMX8MQ_GPU_PLL_REF_DIV		14
+#define IMX8MQ_GPU_PLL			15
+#define IMX8MQ_GPU_PLL_BYPASS		16
+#define IMX8MQ_GPU_PLL_OUT		17
+
+/* VPU PLL */
+#define IMX8MQ_VPU_PLL_REF_SEL		18
+#define IMX8MQ_VPU_PLL_REF_DIV		19
+#define IMX8MQ_VPU_PLL			20
+#define IMX8MQ_VPU_PLL_BYPASS		21
+#define IMX8MQ_VPU_PLL_OUT		22
+
+/* AUDIO PLL1 */
+#define IMX8MQ_AUDIO_PLL1_REF_SEL	23
+#define IMX8MQ_AUDIO_PLL1_REF_DIV	24
+#define IMX8MQ_AUDIO_PLL1		25
+#define IMX8MQ_AUDIO_PLL1_BYPASS	26
+#define IMX8MQ_AUDIO_PLL1_OUT		27
+
+/* AUDIO PLL2 */
+#define IMX8MQ_AUDIO_PLL2_REF_SEL	28
+#define IMX8MQ_AUDIO_PLL2_REF_DIV	29
+#define IMX8MQ_AUDIO_PLL2		30
+#define IMX8MQ_AUDIO_PLL2_BYPASS	31
+#define IMX8MQ_AUDIO_PLL2_OUT		32
+
+/* VIDEO PLL1 */
+#define IMX8MQ_VIDEO_PLL1_REF_SEL	33
+#define IMX8MQ_VIDEO_PLL1_REF_DIV	34
+#define IMX8MQ_VIDEO_PLL1		35
+#define IMX8MQ_VIDEO_PLL1_BYPASS	36
+#define IMX8MQ_VIDEO_PLL1_OUT		37
+
+/* SYS1 PLL */
+#define IMX8MQ_SYS1_PLL1_REF_SEL	38
+#define IMX8MQ_SYS1_PLL1_REF_DIV	39
+#define IMX8MQ_SYS1_PLL1		40
+#define IMX8MQ_SYS1_PLL1_OUT		41
+#define IMX8MQ_SYS1_PLL1_OUT_DIV	42
+#define IMX8MQ_SYS1_PLL2		43
+#define IMX8MQ_SYS1_PLL2_DIV		44
+#define IMX8MQ_SYS1_PLL2_OUT		45
+
+/* SYS2 PLL */
+#define IMX8MQ_SYS2_PLL1_REF_SEL	46
+#define IMX8MQ_SYS2_PLL1_REF_DIV	47
+#define IMX8MQ_SYS2_PLL1		48
+#define IMX8MQ_SYS2_PLL1_OUT		49
+#define IMX8MQ_SYS2_PLL1_OUT_DIV	50
+#define IMX8MQ_SYS2_PLL2		51
+#define IMX8MQ_SYS2_PLL2_DIV		52
+#define IMX8MQ_SYS2_PLL2_OUT		53
+
+/* SYS3 PLL */
+#define IMX8MQ_SYS3_PLL1_REF_SEL	54
+#define IMX8MQ_SYS3_PLL1_REF_DIV	55
+#define IMX8MQ_SYS3_PLL1		56
+#define IMX8MQ_SYS3_PLL1_OUT		57
+#define IMX8MQ_SYS3_PLL1_OUT_DIV	58
+#define IMX8MQ_SYS3_PLL2		59
+#define IMX8MQ_SYS3_PLL2_DIV		60
+#define IMX8MQ_SYS3_PLL2_OUT		61
+
+/* DRAM PLL */
+#define IMX8MQ_DRAM_PLL1_REF_SEL	62
+#define IMX8MQ_DRAM_PLL1_REF_DIV	63
+#define IMX8MQ_DRAM_PLL1		64
+#define IMX8MQ_DRAM_PLL1_OUT		65
+#define IMX8MQ_DRAM_PLL1_OUT_DIV	66
+#define IMX8MQ_DRAM_PLL2		67
+#define IMX8MQ_DRAM_PLL2_DIV		68
+#define IMX8MQ_DRAM_PLL2_OUT		69
+
+/* SYS PLL DIV */
+#define IMX8MQ_SYS1_PLL_40M		70
+#define IMX8MQ_SYS1_PLL_80M		71
+#define IMX8MQ_SYS1_PLL_100M		72
+#define IMX8MQ_SYS1_PLL_133M		73
+#define IMX8MQ_SYS1_PLL_160M		74
+#define IMX8MQ_SYS1_PLL_200M		75
+#define IMX8MQ_SYS1_PLL_266M		76
+#define IMX8MQ_SYS1_PLL_400M		77
+#define IMX8MQ_SYS1_PLL_800M		78
+
+#define IMX8MQ_SYS2_PLL_50M		79
+#define IMX8MQ_SYS2_PLL_100M		80
+#define IMX8MQ_SYS2_PLL_125M		81
+#define IMX8MQ_SYS2_PLL_166M		82
+#define IMX8MQ_SYS2_PLL_200M		83
+#define IMX8MQ_SYS2_PLL_250M		84
+#define IMX8MQ_SYS2_PLL_333M		85
+#define IMX8MQ_SYS2_PLL_500M		86
+#define IMX8MQ_SYS2_PLL_1000M		87
+
+/* CCM ROOT clocks */
+/* A53 */
+#define IMX8MQ_CLK_A53_SRC		88
+#define IMX8MQ_CLK_A53_CG		89
+#define IMX8MQ_CLK_A53_DIV		90
+/* M4 */
+#define IMX8MQ_CLK_M4_SRC		91
+#define IMX8MQ_CLK_M4_CG		92
+#define IMX8MQ_CLK_M4_DIV		93
+/* VPU */
+#define IMX8MQ_CLK_VPU_SRC		94
+#define IMX8MQ_CLK_VPU_CG		95
+#define IMX8MQ_CLK_VPU_DIV		96
+/* GPU CORE */
+#define IMX8MQ_CLK_GPU_CORE_SRC		97
+#define IMX8MQ_CLK_GPU_CORE_CG		98
+#define IMX8MQ_CLK_GPU_CORE_DIV		99
+/* GPU SHADER */
+#define IMX8MQ_CLK_GPU_SHADER_SRC	100
+#define IMX8MQ_CLK_GPU_SHADER_CG	101
+#define IMX8MQ_CLK_GPU_SHADER_DIV	102
+
+/* BUS TYPE */
+/* MAIN AXI */
+#define IMX8MQ_CLK_MAIN_AXI_SRC		103
+#define IMX8MQ_CLK_MAIN_AXI_CG		104
+#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV	105
+#define IMX8MQ_CLK_MAIN_AXI_DIV		106
+/* ENET AXI */
+#define IMX8MQ_CLK_ENET_AXI_SRC		107
+#define IMX8MQ_CLK_ENET_AXI_CG		108
+#define IMX8MQ_CLK_ENET_AXI_PRE_DIV	109
+#define IMX8MQ_CLK_ENET_AXI_DIV		110
+/* NAND_USDHC_BUS */
+#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC		111
+#define IMX8MQ_CLK_NAND_USDHC_BUS_CG		112
+#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV	113
+#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV		114
+/* VPU BUS */
+#define IMX8MQ_CLK_VPU_BUS_SRC			115
+#define IMX8MQ_CLK_VPU_BUS_CG			116
+#define IMX8MQ_CLK_VPU_BUS_PRE_DIV		117
+#define IMX8MQ_CLK_VPU_BUS_DIV			118
+/* DISP_AXI */
+#define IMX8MQ_CLK_DISP_AXI_SRC			119
+#define IMX8MQ_CLK_DISP_AXI_CG			120
+#define IMX8MQ_CLK_DISP_AXI_PRE_DIV		121
+#define IMX8MQ_CLK_DISP_AXI_DIV			122
+/* DISP APB */
+#define IMX8MQ_CLK_DISP_APB_SRC			123
+#define IMX8MQ_CLK_DISP_APB_CG			124
+#define IMX8MQ_CLK_DISP_APB_PRE_DIV		125
+#define IMX8MQ_CLK_DISP_APB_DIV			126
+/* DISP RTRM */
+#define IMX8MQ_CLK_DISP_RTRM_SRC		127
+#define IMX8MQ_CLK_DISP_RTRM_CG			128
+#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV		129
+#define IMX8MQ_CLK_DISP_RTRM_DIV		130
+/* USB_BUS */
+#define IMX8MQ_CLK_USB_BUS_SRC			131
+#define IMX8MQ_CLK_USB_BUS_CG			132
+#define IMX8MQ_CLK_USB_BUS_PRE_DIV		133
+#define IMX8MQ_CLK_USB_BUS_DIV			134
+/* GPU_AXI */
+#define IMX8MQ_CLK_GPU_AXI_SRC			135
+#define IMX8MQ_CLK_GPU_AXI_CG			136
+#define IMX8MQ_CLK_GPU_AXI_PRE_DIV		137
+#define IMX8MQ_CLK_GPU_AXI_DIV			138
+/* GPU_AHB */
+#define IMX8MQ_CLK_GPU_AHB_SRC			139
+#define IMX8MQ_CLK_GPU_AHB_CG			140
+#define IMX8MQ_CLK_GPU_AHB_PRE_DIV		141
+#define IMX8MQ_CLK_GPU_AHB_DIV			142
+/* NOC */
+#define IMX8MQ_CLK_NOC_SRC			143
+#define IMX8MQ_CLK_NOC_CG			144
+#define IMX8MQ_CLK_NOC_PRE_DIV			145
+#define IMX8MQ_CLK_NOC_DIV			146
+/* NOC_APB */
+#define IMX8MQ_CLK_NOC_APB_SRC			147
+#define IMX8MQ_CLK_NOC_APB_CG			148
+#define IMX8MQ_CLK_NOC_APB_PRE_DIV		149
+#define IMX8MQ_CLK_NOC_APB_DIV			150
+
+/* AHB */
+#define IMX8MQ_CLK_AHB_SRC			151
+#define IMX8MQ_CLK_AHB_CG			152
+#define IMX8MQ_CLK_AHB_PRE_DIV			153
+#define IMX8MQ_CLK_AHB_DIV			154
+/* AUDIO AHB */
+#define IMX8MQ_CLK_AUDIO_AHB_SRC		155
+#define IMX8MQ_CLK_AUDIO_AHB_CG			156
+#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV		157
+#define IMX8MQ_CLK_AUDIO_AHB_DIV		158
+
+/* DRAM_ALT */
+#define IMX8MQ_CLK_DRAM_ALT_SRC			159
+#define IMX8MQ_CLK_DRAM_ALT_CG			160
+#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV		161
+#define IMX8MQ_CLK_DRAM_ALT_DIV			162
+/* DRAM APB */
+#define IMX8MQ_CLK_DRAM_APB_SRC			163
+#define IMX8MQ_CLK_DRAM_APB_CG			164
+#define IMX8MQ_CLK_DRAM_APB_PRE_DIV		165
+#define IMX8MQ_CLK_DRAM_APB_DIV			166
+/* VPU_G1 */
+#define IMX8MQ_CLK_VPU_G1_SRC			167
+#define IMX8MQ_CLK_VPU_G1_CG			168
+#define IMX8MQ_CLK_VPU_G1_PRE_DIV		169
+#define IMX8MQ_CLK_VPU_G1_DIV			170
+/* VPU_G2 */
+#define IMX8MQ_CLK_VPU_G2_SRC			171
+#define IMX8MQ_CLK_VPU_G2_CG			172
+#define IMX8MQ_CLK_VPU_G2_PRE_DIV		173
+#define IMX8MQ_CLK_VPU_G2_DIV			174
+/* DISP_DTRC */
+#define IMX8MQ_CLK_DISP_DTRC_SRC		175
+#define IMX8MQ_CLK_DISP_DTRC_CG			176
+#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV		177
+#define IMX8MQ_CLK_DISP_DTRC_DIV		178
+/* DISP_DC8000 */
+#define IMX8MQ_CLK_DISP_DC8000_SRC		179
+#define IMX8MQ_CLK_DISP_DC8000_CG		180
+#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV		181
+#define IMX8MQ_CLK_DISP_DC8000_DIV		182
+/* PCIE_CTRL */
+#define IMX8MQ_CLK_PCIE1_CTRL_SRC		183
+#define IMX8MQ_CLK_PCIE1_CTRL_CG		184
+#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV		185
+#define IMX8MQ_CLK_PCIE1_CTRL_DIV		186
+/* PCIE_PHY */
+#define IMX8MQ_CLK_PCIE1_PHY_SRC		187
+#define IMX8MQ_CLK_PCIE1_PHY_CG			188
+#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV		189
+#define IMX8MQ_CLK_PCIE1_PHY_DIV		190
+/* PCIE_AUX */
+#define IMX8MQ_CLK_PCIE1_AUX_SRC		191
+#define IMX8MQ_CLK_PCIE1_AUX_CG			192
+#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV		193
+#define IMX8MQ_CLK_PCIE1_AUX_DIV		194
+/* DC_PIXEL */
+#define IMX8MQ_CLK_DC_PIXEL_SRC			195
+#define IMX8MQ_CLK_DC_PIXEL_CG			196
+#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV		197
+#define IMX8MQ_CLK_DC_PIXEL_DIV			198
+/* LCDIF_PIXEL */
+#define IMX8MQ_CLK_LCDIF_PIXEL_SRC		199
+#define IMX8MQ_CLK_LCDIF_PIXEL_CG		200
+#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV		201
+#define IMX8MQ_CLK_LCDIF_PIXEL_DIV		202
+/* SAI1~6 */
+#define IMX8MQ_CLK_SAI1_SRC			203
+#define IMX8MQ_CLK_SAI1_CG			204
+#define IMX8MQ_CLK_SAI1_PRE_DIV			205
+#define IMX8MQ_CLK_SAI1_DIV			206
+
+#define IMX8MQ_CLK_SAI2_SRC			207
+#define IMX8MQ_CLK_SAI2_CG			208
+#define IMX8MQ_CLK_SAI2_PRE_DIV			209
+#define IMX8MQ_CLK_SAI2_DIV			210
+
+#define IMX8MQ_CLK_SAI3_SRC			211
+#define IMX8MQ_CLK_SAI3_CG			212
+#define IMX8MQ_CLK_SAI3_PRE_DIV			213
+#define IMX8MQ_CLK_SAI3_DIV			214
+
+#define IMX8MQ_CLK_SAI4_SRC			215
+#define IMX8MQ_CLK_SAI4_CG			216
+#define IMX8MQ_CLK_SAI4_PRE_DIV			217
+#define IMX8MQ_CLK_SAI4_DIV			218
+
+#define IMX8MQ_CLK_SAI5_SRC			219
+#define IMX8MQ_CLK_SAI5_CG			220
+#define IMX8MQ_CLK_SAI5_PRE_DIV			221
+#define IMX8MQ_CLK_SAI5_DIV			222
+
+#define IMX8MQ_CLK_SAI6_SRC			223
+#define IMX8MQ_CLK_SAI6_CG			224
+#define IMX8MQ_CLK_SAI6_PRE_DIV			225
+#define IMX8MQ_CLK_SAI6_DIV			226
+/* SPDIF1 */
+#define IMX8MQ_CLK_SPDIF1_SRC			227
+#define IMX8MQ_CLK_SPDIF1_CG			228
+#define IMX8MQ_CLK_SPDIF1_PRE_DIV		229
+#define IMX8MQ_CLK_SPDIF1_DIV			230
+/* SPDIF2 */
+#define IMX8MQ_CLK_SPDIF2_SRC			231
+#define IMX8MQ_CLK_SPDIF2_CG			232
+#define IMX8MQ_CLK_SPDIF2_PRE_DIV		233
+#define IMX8MQ_CLK_SPDIF2_DIV			234
+/* ENET_REF */
+#define IMX8MQ_CLK_ENET_REF_SRC			235
+#define IMX8MQ_CLK_ENET_REF_CG			236
+#define IMX8MQ_CLK_ENET_REF_PRE_DIV		237
+#define IMX8MQ_CLK_ENET_REF_DIV			238
+/* ENET_TIMER */
+#define IMX8MQ_CLK_ENET_TIMER_SRC		239
+#define IMX8MQ_CLK_ENET_TIMER_CG		240
+#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV		241
+#define IMX8MQ_CLK_ENET_TIMER_DIV		242
+/* ENET_PHY */
+#define IMX8MQ_CLK_ENET_PHY_REF_SRC		243
+#define IMX8MQ_CLK_ENET_PHY_REF_CG		244
+#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV		245
+#define IMX8MQ_CLK_ENET_PHY_REF_DIV		246
+/* NAND */
+#define IMX8MQ_CLK_NAND_SRC			247
+#define IMX8MQ_CLK_NAND_CG			248
+#define IMX8MQ_CLK_NAND_PRE_DIV			249
+#define IMX8MQ_CLK_NAND_DIV			250
+/* QSPI */
+#define IMX8MQ_CLK_QSPI_SRC			251
+#define IMX8MQ_CLK_QSPI_CG			252
+#define IMX8MQ_CLK_QSPI_PRE_DIV			253
+#define IMX8MQ_CLK_QSPI_DIV			254
+/* USDHC1 */
+#define IMX8MQ_CLK_USDHC1_SRC			255
+#define IMX8MQ_CLK_USDHC1_CG			256
+#define IMX8MQ_CLK_USDHC1_PRE_DIV		257
+#define IMX8MQ_CLK_USDHC1_DIV			258
+/* USDHC2 */
+#define IMX8MQ_CLK_USDHC2_SRC			259
+#define IMX8MQ_CLK_USDHC2_CG			260
+#define IMX8MQ_CLK_USDHC2_PRE_DIV		261
+#define IMX8MQ_CLK_USDHC2_DIV			262
+/* I2C1 */
+#define IMX8MQ_CLK_I2C1_SRC			263
+#define IMX8MQ_CLK_I2C1_CG			264
+#define IMX8MQ_CLK_I2C1_PRE_DIV			265
+#define IMX8MQ_CLK_I2C1_DIV			266
+/* I2C2 */
+#define IMX8MQ_CLK_I2C2_SRC			267
+#define IMX8MQ_CLK_I2C2_CG			268
+#define IMX8MQ_CLK_I2C2_PRE_DIV			269
+#define IMX8MQ_CLK_I2C2_DIV			270
+/* I2C3 */
+#define IMX8MQ_CLK_I2C3_SRC			271
+#define IMX8MQ_CLK_I2C3_CG			272
+#define IMX8MQ_CLK_I2C3_PRE_DIV			273
+#define IMX8MQ_CLK_I2C3_DIV			274
+/* I2C4 */
+#define IMX8MQ_CLK_I2C4_SRC			275
+#define IMX8MQ_CLK_I2C4_CG			276
+#define IMX8MQ_CLK_I2C4_PRE_DIV			277
+#define IMX8MQ_CLK_I2C4_DIV			278
+/* UART1 */
+#define IMX8MQ_CLK_UART1_SRC			279
+#define IMX8MQ_CLK_UART1_CG			280
+#define IMX8MQ_CLK_UART1_PRE_DIV		281
+#define IMX8MQ_CLK_UART1_DIV			282
+/* UART2 */
+#define IMX8MQ_CLK_UART2_SRC			283
+#define IMX8MQ_CLK_UART2_CG			284
+#define IMX8MQ_CLK_UART2_PRE_DIV		285
+#define IMX8MQ_CLK_UART2_DIV			286
+/* UART3 */
+#define IMX8MQ_CLK_UART3_SRC			287
+#define IMX8MQ_CLK_UART3_CG			288
+#define IMX8MQ_CLK_UART3_PRE_DIV		289
+#define IMX8MQ_CLK_UART3_DIV			290
+/* UART4 */
+#define IMX8MQ_CLK_UART4_SRC			291
+#define IMX8MQ_CLK_UART4_CG			292
+#define IMX8MQ_CLK_UART4_PRE_DIV		293
+#define IMX8MQ_CLK_UART4_DIV			294
+/* USB_CORE_REF */
+#define IMX8MQ_CLK_USB_CORE_REF_SRC		295
+#define IMX8MQ_CLK_USB_CORE_REF_CG		296
+#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV		297
+#define IMX8MQ_CLK_USB_CORE_REF_DIV		298
+/* USB_PHY_REF */
+#define IMX8MQ_CLK_USB_PHY_REF_SRC		299
+#define IMX8MQ_CLK_USB_PHY_REF_CG		300
+#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV		301
+#define IMX8MQ_CLK_USB_PHY_REF_DIV		302
+/* ECSPI1 */
+#define IMX8MQ_CLK_ECSPI1_SRC			303
+#define IMX8MQ_CLK_ECSPI1_CG			304
+#define IMX8MQ_CLK_ECSPI1_PRE_DIV		305
+#define IMX8MQ_CLK_ECSPI1_DIV			306
+/* ECSPI2 */
+#define IMX8MQ_CLK_ECSPI2_SRC			307
+#define IMX8MQ_CLK_ECSPI2_CG			308
+#define IMX8MQ_CLK_ECSPI2_PRE_DIV		309
+#define IMX8MQ_CLK_ECSPI2_DIV			310
+/* PWM1 */
+#define IMX8MQ_CLK_PWM1_SRC			311
+#define IMX8MQ_CLK_PWM1_CG			312
+#define IMX8MQ_CLK_PWM1_PRE_DIV			313
+#define IMX8MQ_CLK_PWM1_DIV			314
+/* PWM2 */
+#define IMX8MQ_CLK_PWM2_SRC			315
+#define IMX8MQ_CLK_PWM2_CG			316
+#define IMX8MQ_CLK_PWM2_PRE_DIV			317
+#define IMX8MQ_CLK_PWM2_DIV			318
+/* PWM3 */
+#define IMX8MQ_CLK_PWM3_SRC			319
+#define IMX8MQ_CLK_PWM3_CG			320
+#define IMX8MQ_CLK_PWM3_PRE_DIV			321
+#define IMX8MQ_CLK_PWM3_DIV			322
+/* PWM4 */
+#define IMX8MQ_CLK_PWM4_SRC			323
+#define IMX8MQ_CLK_PWM4_CG			324
+#define IMX8MQ_CLK_PWM4_PRE_DIV			325
+#define IMX8MQ_CLK_PWM4_DIV			326
+/* GPT1 */
+#define IMX8MQ_CLK_GPT1_SRC			327
+#define IMX8MQ_CLK_GPT1_CG			328
+#define IMX8MQ_CLK_GPT1_PRE_DIV			329
+#define IMX8MQ_CLK_GPT1_DIV			330
+/* WDOG */
+#define IMX8MQ_CLK_WDOG_SRC			331
+#define IMX8MQ_CLK_WDOG_CG			332
+#define IMX8MQ_CLK_WDOG_PRE_DIV			333
+#define IMX8MQ_CLK_WDOG_DIV			334
+/* WRCLK */
+#define IMX8MQ_CLK_WRCLK_SRC			335
+#define IMX8MQ_CLK_WRCLK_CG			336
+#define IMX8MQ_CLK_WRCLK_PRE_DIV		337
+#define IMX8MQ_CLK_WRCLK_DIV			338
+/* DSI_CORE */
+#define IMX8MQ_CLK_DSI_CORE_SRC			339
+#define IMX8MQ_CLK_DSI_CORE_CG			340
+#define IMX8MQ_CLK_DSI_CORE_PRE_DIV		341
+#define IMX8MQ_CLK_DSI_CORE_DIV			342
+/* DSI_PHY */
+#define IMX8MQ_CLK_DSI_PHY_REF_SRC		343
+#define IMX8MQ_CLK_DSI_PHY_REF_CG		344
+#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV		345
+#define IMX8MQ_CLK_DSI_PHY_REF_DIV		346
+/* DSI_DBI */
+#define IMX8MQ_CLK_DSI_DBI_SRC			347
+#define IMX8MQ_CLK_DSI_DBI_CG			348
+#define IMX8MQ_CLK_DSI_DBI_PRE_DIV		349
+#define IMX8MQ_CLK_DSI_DBI_DIV			350
+/*DSI_ESC */
+#define IMX8MQ_CLK_DSI_ESC_SRC			351
+#define IMX8MQ_CLK_DSI_ESC_CG			352
+#define IMX8MQ_CLK_DSI_ESC_PRE_DIV		353
+#define IMX8MQ_CLK_DSI_ESC_DIV			354
+/* CSI1_CORE */
+#define IMX8MQ_CLK_CSI1_CORE_SRC		355
+#define IMX8MQ_CLK_CSI1_CORE_CG			356
+#define  IMX8MQ_CLK_CSI1_CORE_PRE_DIV		357
+#define IMX8MQ_CLK_CSI1_CORE_DIV		358
+/* CSI1_PHY */
+#define IMX8MQ_CLK_CSI1_PHY_REF_SRC		359
+#define IMX8MQ_CLK_CSI1_PHY_REF_CG		360
+#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV		361
+#define IMX8MQ_CLK_CSI1_PHY_REF_DIV		362
+/* CSI_ESC */
+#define IMX8MQ_CLK_CSI1_ESC_SRC			363
+#define IMX8MQ_CLK_CSI1_ESC_CG			364
+#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV		365
+#define IMX8MQ_CLK_CSI1_ESC_DIV			366
+/* CSI2_CORE */
+#define IMX8MQ_CLK_CSI2_CORE_SRC		367
+#define IMX8MQ_CLK_CSI2_CORE_CG			368
+#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV		369
+#define IMX8MQ_CLK_CSI2_CORE_DIV		370
+/* CSI2_PHY */
+#define IMX8MQ_CLK_CSI2_PHY_REF_SRC		371
+#define IMX8MQ_CLK_CSI2_PHY_REF_CG		372
+#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV		373
+#define IMX8MQ_CLK_CSI2_PHY_REF_DIV		374
+/* CSI2_ESC */
+#define IMX8MQ_CLK_CSI2_ESC_SRC			375
+#define IMX8MQ_CLK_CSI2_ESC_CG			376
+#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV		377
+#define IMX8MQ_CLK_CSI2_ESC_DIV			378
+/* PCIE2_CTRL */
+#define IMX8MQ_CLK_PCIE2_CTRL_SRC		379
+#define IMX8MQ_CLK_PCIE2_CTRL_CG		380
+#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV		381
+#define IMX8MQ_CLK_PCIE2_CTRL_DIV		382
+/* PCIE2_PHY */
+#define IMX8MQ_CLK_PCIE2_PHY_SRC		383
+#define IMX8MQ_CLK_PCIE2_PHY_CG			384
+#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV		385
+#define IMX8MQ_CLK_PCIE2_PHY_DIV		386
+/* PCIE2_AUX */
+#define IMX8MQ_CLK_PCIE2_AUX_SRC		387
+#define IMX8MQ_CLK_PCIE2_AUX_CG			388
+#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV		389
+#define IMX8MQ_CLK_PCIE2_AUX_DIV		390
+/* ECSPI3 */
+#define IMX8MQ_CLK_ECSPI3_SRC			391
+#define IMX8MQ_CLK_ECSPI3_CG			392
+#define IMX8MQ_CLK_ECSPI3_PRE_DIV		393
+#define IMX8MQ_CLK_ECSPI3_DIV			394
+
+/* CCGR clocks */
+#define IMX8MQ_CLK_A53_ROOT			395
+#define IMX8MQ_CLK_DRAM_ROOT			396
+#define IMX8MQ_CLK_ECSPI1_ROOT			397
+#define IMX8MQ_CLK_ECSPI2_ROOT			398
+#define IMX8MQ_CLK_ECSPI3_ROOT			399
+#define IMX8MQ_CLK_ENET1_ROOT			400
+#define IMX8MQ_CLK_GPT1_ROOT			401
+#define IMX8MQ_CLK_I2C1_ROOT			402
+#define IMX8MQ_CLK_I2C2_ROOT			403
+#define IMX8MQ_CLK_I2C3_ROOT			404
+#define IMX8MQ_CLK_I2C4_ROOT			405
+#define IMX8MQ_CLK_M4_ROOT			406
+#define IMX8MQ_CLK_PCIE1_ROOT			407
+#define IMX8MQ_CLK_PCIE2_ROOT			408
+#define IMX8MQ_CLK_PWM1_ROOT			409
+#define IMX8MQ_CLK_PWM2_ROOT			410
+#define IMX8MQ_CLK_PWM3_ROOT			411
+#define IMX8MQ_CLK_PWM4_ROOT			412
+#define IMX8MQ_CLK_QSPI_ROOT			413
+#define IMX8MQ_CLK_SAI1_ROOT			414
+#define IMX8MQ_CLK_SAI2_ROOT			415
+#define IMX8MQ_CLK_SAI3_ROOT			416
+#define IMX8MQ_CLK_SAI4_ROOT			417
+#define IMX8MQ_CLK_SAI5_ROOT			418
+#define IMX8MQ_CLK_SAI6_ROOT			419
+#define IMX8MQ_CLK_UART1_ROOT			420
+#define IMX8MQ_CLK_UART2_ROOT			421
+#define IMX8MQ_CLK_UART3_ROOT			422
+#define IMX8MQ_CLK_UART4_ROOT			423
+#define IMX8MQ_CLK_USB1_CTRL_ROOT		424
+#define IMX8MQ_CLK_USB2_CTRL_ROOT		425
+#define IMX8MQ_CLK_USB1_PHY_ROOT		426
+#define IMX8MQ_CLK_USB2_PHY_ROOT		427
+#define IMX8MQ_CLK_USDHC1_ROOT			428
+#define IMX8MQ_CLK_USDHC2_ROOT			429
+#define IMX8MQ_CLK_WDOG1_ROOT			430
+#define IMX8MQ_CLK_WDOG2_ROOT			431
+#define IMX8MQ_CLK_WDOG3_ROOT			432
+#define IMX8MQ_CLK_GPU_ROOT			433
+#define IMX8MQ_CLK_HEVC_ROOT			434
+#define IMX8MQ_CLK_AVC_ROOT			435
+#define IMX8MQ_CLK_VP9_ROOT			436
+#define IMX8MQ_CLK_HEVC_INTER_ROOT		437
+#define IMX8MQ_CLK_DISP_ROOT			438
+#define IMX8MQ_CLK_HDMI_ROOT			439
+#define IMX8MQ_CLK_HDMI_PHY_ROOT		440
+#define IMX8MQ_CLK_VPU_DEC_ROOT			441
+#define IMX8MQ_CLK_CSI1_ROOT			442
+#define IMX8MQ_CLK_CSI2_ROOT			443
+#define IMX8MQ_CLK_RAWNAND_ROOT			444
+#define IMX8MQ_CLK_SDMA1_ROOT			445
+#define IMX8MQ_CLK_SDMA2_ROOT			446
+#define IMX8MQ_CLK_VPU_G1_ROOT			447
+#define IMX8MQ_CLK_VPU_G2_ROOT			448
+
+/* SCCG PLL GATE */
+#define IMX8MQ_SYS1_PLL_OUT			449
+#define IMX8MQ_SYS2_PLL_OUT			450
+#define IMX8MQ_SYS3_PLL_OUT			451
+#define IMX8MQ_DRAM_PLL_OUT			452
+
+#define IMX8MQ_GPT_3M_CLK			453
+
+#define IMX8MQ_CLK_IPG_ROOT			454
+#define IMX8MQ_CLK_IPG_AUDIO_ROOT		455
+#define IMX8MQ_CLK_SAI1_IPG			456
+#define IMX8MQ_CLK_SAI2_IPG			457
+#define IMX8MQ_CLK_SAI3_IPG			458
+#define IMX8MQ_CLK_SAI4_IPG			459
+#define IMX8MQ_CLK_SAI5_IPG			460
+#define IMX8MQ_CLK_SAI6_IPG			461
+
+/* DSI AHB/IPG clocks */
+/* rxesc clock */
+#define IMX8MQ_CLK_DSI_AHB_SRC                  462
+#define IMX8MQ_CLK_DSI_AHB_CG                   463
+#define IMX8MQ_CLK_DSI_AHB_PRE_DIV              464
+#define IMX8MQ_CLK_DSI_AHB_DIV                  465
+/* txesc clock */
+#define IMX8MQ_CLK_DSI_IPG_DIV                  466
+
+/* VIDEO2 PLL */
+#define IMX8MQ_VIDEO2_PLL1_REF_SEL		467
+#define IMX8MQ_VIDEO2_PLL1_REF_DIV		468
+#define IMX8MQ_VIDEO2_PLL1			469
+#define IMX8MQ_VIDEO2_PLL1_OUT			470
+#define IMX8MQ_VIDEO2_PLL1_OUT_DIV		471
+#define IMX8MQ_VIDEO2_PLL2			472
+#define IMX8MQ_VIDEO2_PLL2_DIV			473
+#define IMX8MQ_VIDEO2_PLL2_OUT			474
+#define IMX8MQ_CLK_TMU_ROOT			475
+
+#define IMX8MQ_CLK_END				476
+#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h
new file mode 100644
index 0000000..58de976
--- /dev/null
+++ b/include/dt-bindings/clock/imx8qm-clock.h
@@ -0,0 +1,846 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8QM_H
+#define __DT_BINDINGS_CLOCK_IMX8QM_H
+
+#define IMX8QM_CLK_DUMMY					0
+
+#define IMX8QM_A53_DIV						1
+#define IMX8QM_A53_CLK						2
+#define IMX8QM_A72_DIV						3
+#define IMX8QM_A72_CLK						4
+
+/* SC Clocks. */
+#define IMX8QM_SC_I2C_DIV					5
+#define IMX8QM_SC_I2C_CLK					6
+#define IMX8QM_SC_PID0_DIV					7
+#define IMX8QM_SC_PID0_CLK					8
+#define IMX8QM_SC_PIT_DIV					9
+#define IMX8QM_SC_PIT_CLK					10
+#define IMX8QM_SC_TPM_DIV					11
+#define IMX8QM_SC_TPM_CLK					12
+#define IMX8QM_SC_UART_DIV					13
+#define IMX8QM_SC_UART_CLK					14
+
+/* LSIO */
+#define IMX8QM_PWM0_DIV						15
+#define IMX8QM_PWM0_CLK						16
+#define IMX8QM_PWM1_DIV						17
+#define IMX8QM_PWM1_CLK						18
+#define IMX8QM_PWM2_DIV						19
+#define IMX8QM_PWM2_CLK						20
+#define IMX8QM_PWM3_DIV						21
+#define IMX8QM_PWM3_CLK						22
+#define IMX8QM_PWM4_DIV						23
+#define IMX8QM_PWM4_CLK						24
+#define IMX8QM_PWM5_DIV						26
+#define IMX8QM_PWM5_CLK						27
+#define IMX8QM_PWM6_DIV						28
+#define IMX8QM_PWM6_CLK						29
+#define IMX8QM_PWM7_DIV						30
+#define IMX8QM_PWM7_CLK						31
+#define IMX8QM_FSPI0_DIV					32
+#define IMX8QM_FSPI0_CLK					33
+#define IMX8QM_FSPI1_DIV					34
+#define IMX8QM_FSPI1_CLK					35
+#define IMX8QM_GPT0_DIV						36
+#define IMX8QM_GPT0_CLK						37
+#define IMX8QM_GPT1_DIV						38
+#define IMX8QM_GPT1_CLK						39
+#define IMX8QM_GPT2_DIV						40
+#define IMX8QM_GPT2_CLK						41
+#define IMX8QM_GPT3_DIV						42
+#define IMX8QM_GPT3_CLK						43
+#define IMX8QM_GPT4_DIV						44
+#define IMX8QM_GPT4_CLK						45
+
+/* Connectivity */
+#define IMX8QM_APBHDMA_CLK					46
+#define IMX8QM_GPMI_APB_CLK					47
+#define IMX8QM_GPMI_APB_BCH_CLK				48
+#define IMX8QM_GPMI_BCH_IO_DIV				49
+#define IMX8QM_GPMI_BCH_IO_CLK				50
+#define IMX8QM_GPMI_BCH_DIV				51
+#define IMX8QM_GPMI_BCH_CLK				52
+#define IMX8QM_SDHC0_IPG_CLK				53
+#define IMX8QM_SDHC0_DIV				54
+#define IMX8QM_SDHC0_CLK				55
+#define IMX8QM_SDHC1_IPG_CLK				56
+#define IMX8QM_SDHC1_DIV				57
+#define IMX8QM_SDHC1_CLK				58
+#define IMX8QM_SDHC2_IPG_CLK				59
+#define IMX8QM_SDHC2_DIV				60
+#define IMX8QM_SDHC2_CLK				61
+#define IMX8QM_USB2_OH_AHB_CLK				62
+#define IMX8QM_USB2_OH_IPG_S_CLK			63
+#define IMX8QM_USB2_OH_IPG_S_PL301_CLK			64
+#define IMX8QM_USB2_PHY_IPG_CLK				65
+#define IMX8QM_USB3_IPG_CLK				66
+#define IMX8QM_USB3_CORE_PCLK				67
+#define IMX8QM_USB3_PHY_CLK				68
+#define IMX8QM_USB3_ACLK_DIV				69
+#define IMX8QM_USB3_ACLK				70
+#define IMX8QM_USB3_BUS_DIV				71
+#define IMX8QM_USB3_BUS_CLK				72
+#define IMX8QM_USB3_LPM_DIV				73
+#define IMX8QM_USB3_LPM_CLK				74
+#define IMX8QM_ENET0_AHB_CLK				75
+#define IMX8QM_ENET0_IPG_S_CLK				76
+#define IMX8QM_ENET0_IPG_CLK				77
+#define IMX8QM_ENET0_RGMII_DIV				78
+#define IMX8QM_ENET0_RGMII_TX_CLK			79
+#define IMX8QM_ENET0_ROOT_DIV				80
+#define IMX8QM_ENET0_TX_CLK				81
+#define IMX8QM_ENET0_ROOT_CLK				82
+#define IMX8QM_ENET0_PTP_CLK				83
+#define IMX8QM_ENET0_BYPASS_DIV				84
+#define IMX8QM_ENET1_AHB_CLK				85
+#define IMX8QM_ENET1_IPG_S_CLK				86
+#define IMX8QM_ENET1_IPG_CLK				87
+#define IMX8QM_ENET1_RGMII_DIV				88
+#define IMX8QM_ENET1_RGMII_TX_CLK			89
+#define IMX8QM_ENET1_ROOT_DIV				90
+#define IMX8QM_ENET1_TX_CLK				91
+#define IMX8QM_ENET1_ROOT_CLK				92
+#define IMX8QM_ENET1_PTP_CLK				93
+#define IMX8QM_ENET1_BYPASS_DIV				94
+#define IMX8QM_MLB_CLK					95
+#define IMX8QM_MLB_HCLK					96
+#define IMX8QM_MLB_IPG_CLK				97
+#define IMX8QM_EDMA_CLK					98
+#define IMX8QM_EDMA_IPG_CLK				99
+
+/* DMA */
+#define IMX8QM_SPI0_IPG_CLK				100
+#define IMX8QM_SPI0_DIV					101
+#define IMX8QM_SPI0_CLK					102
+#define IMX8QM_SPI1_IPG_CLK				103
+#define IMX8QM_SPI1_DIV					104
+#define IMX8QM_SPI1_CLK					105
+#define IMX8QM_SPI2_IPG_CLK				106
+#define IMX8QM_SPI2_DIV					107
+#define IMX8QM_SPI2_CLK					108
+#define IMX8QM_SPI3_IPG_CLK				109
+#define IMX8QM_SPI3_DIV					110
+#define IMX8QM_SPI3_CLK					111
+#define IMX8QM_UART0_IPG_CLK				112
+#define IMX8QM_UART0_DIV				113
+#define IMX8QM_UART0_CLK				114
+#define IMX8QM_UART1_IPG_CLK				115
+#define IMX8QM_UART1_DIV				116
+#define IMX8QM_UART1_CLK				117
+#define IMX8QM_UART2_IPG_CLK				118
+#define IMX8QM_UART2_DIV				119
+#define IMX8QM_UART2_CLK				120
+#define IMX8QM_UART3_IPG_CLK				121
+#define IMX8QM_UART3_DIV				122
+#define IMX8QM_UART3_CLK				123
+#define IMX8QM_UART4_IPG_CLK				124
+#define IMX8QM_UART4_DIV				125
+#define IMX8QM_EMVSIM0_IPG_CLK				126
+#define IMX8QM_UART4_CLK				127
+#define IMX8QM_EMVSIM0_DIV				128
+#define IMX8QM_EMVSIM0_CLK				129
+#define IMX8QM_EMVSIM1_IPG_CLK				130
+#define IMX8QM_EMVSIM1_DIV				131
+#define IMX8QM_EMVSIM1_CLK				132
+#define IMX8QM_CAN0_IPG_CHI_CLK				133
+#define IMX8QM_CAN0_IPG_CLK				134
+#define IMX8QM_CAN0_DIV					135
+#define IMX8QM_CAN0_CLK					136
+#define IMX8QM_CAN1_IPG_CHI_CLK				137
+#define IMX8QM_CAN1_IPG_CLK				138
+#define IMX8QM_CAN1_DIV					139
+#define IMX8QM_CAN1_CLK					140
+#define IMX8QM_CAN2_IPG_CHI_CLK				141
+#define IMX8QM_CAN2_IPG_CLK				142
+#define IMX8QM_CAN2_DIV					143
+#define IMX8QM_CAN2_CLK					144
+#define IMX8QM_I2C0_IPG_CLK				145
+#define IMX8QM_I2C0_DIV					146
+#define IMX8QM_I2C0_CLK					147
+#define IMX8QM_I2C1_IPG_CLK				148
+#define IMX8QM_I2C1_DIV					149
+#define IMX8QM_I2C1_CLK					150
+#define IMX8QM_I2C2_IPG_CLK				151
+#define IMX8QM_I2C2_DIV					152
+#define IMX8QM_I2C2_CLK					153
+#define IMX8QM_I2C3_IPG_CLK				154
+#define IMX8QM_I2C3_DIV					155
+#define IMX8QM_I2C3_CLK					156
+#define IMX8QM_I2C4_IPG_CLK				157
+#define IMX8QM_I2C4_DIV					158
+#define IMX8QM_I2C4_CLK					159
+#define IMX8QM_FTM0_IPG_CLK				160
+#define IMX8QM_FTM0_DIV					161
+#define IMX8QM_FTM0_CLK					162
+#define IMX8QM_FTM1_IPG_CLK				163
+#define IMX8QM_FTM1_DIV					164
+#define IMX8QM_FTM1_CLK					165
+#define IMX8QM_ADC0_IPG_CLK				166
+#define IMX8QM_ADC0_DIV					167
+#define IMX8QM_ADC0_CLK					168
+#define IMX8QM_ADC1_IPG_CLK				169
+#define IMX8QM_ADC1_DIV					170
+#define IMX8QM_ADC1_CLK					171
+
+/* Audio */
+#define IMX8QM_AUD_PLL0_DIV				172
+#define IMX8QM_AUD_PLL0					173
+#define IMX8QM_AUD_PLL1_DIV				174
+#define IMX8QM_AUD_PLL1					175
+#define IMX8QM_AUD_AMIX_IPG				182
+#define IMX8QM_AUD_ESAI_0_IPG				183
+#define IMX8QM_AUD_ESAI_1_IPG				184
+#define IMX8QM_AUD_ESAI_0_EXTAL_IPG			185
+#define IMX8QM_AUD_ESAI_1_EXTAL_IPG			186
+#define IMX8QM_AUD_SAI_0_IPG				187
+#define IMX8QM_AUD_SAI_0_IPG_S				188
+#define IMX8QM_AUD_SAI_0_MCLK				189
+#define IMX8QM_AUD_SAI_1_IPG				190
+#define IMX8QM_AUD_SAI_1_IPG_S				191
+#define IMX8QM_AUD_SAI_1_MCLK				192
+#define IMX8QM_AUD_SAI_2_IPG				193
+#define IMX8QM_AUD_SAI_2_IPG_S				194
+#define IMX8QM_AUD_SAI_2_MCLK				195
+#define IMX8QM_AUD_SAI_3_IPG				196
+#define IMX8QM_AUD_SAI_3_IPG_S				197
+#define IMX8QM_AUD_SAI_3_MCLK				198
+#define IMX8QM_AUD_SAI_6_IPG				199
+#define IMX8QM_AUD_SAI_6_IPG_S				200
+#define IMX8QM_AUD_SAI_6_MCLK				201
+#define IMX8QM_AUD_SAI_7_IPG				202
+#define IMX8QM_AUD_SAI_7_IPG_S				203
+#define IMX8QM_AUD_SAI_7_MCLK				204
+#define IMX8QM_AUD_SAI_HDMIRX0_IPG			205
+#define IMX8QM_AUD_SAI_HDMIRX0_IPG_S			206
+#define IMX8QM_AUD_SAI_HDMIRX0_MCLK			207
+#define IMX8QM_AUD_SAI_HDMITX0_IPG			208
+#define IMX8QM_AUD_SAI_HDMITX0_IPG_S			209
+#define IMX8QM_AUD_SAI_HDMITX0_MCLK			210
+#define IMX8QM_AUD_MQS_IPG				211
+#define IMX8QM_AUD_MQS_HMCLK				212
+#define IMX8QM_AUD_GPT5_IPG_S				213
+#define IMX8QM_AUD_GPT5_CLKIN				214
+#define IMX8QM_AUD_GPT5_24M_CLK				215
+#define IMX8QM_AUD_GPT6_IPG_S				216
+#define IMX8QM_AUD_GPT6_CLKIN				217
+#define IMX8QM_AUD_GPT6_24M_CLK				218
+#define IMX8QM_AUD_GPT7_IPG_S				219
+#define IMX8QM_AUD_GPT7_CLKIN				220
+#define IMX8QM_AUD_GPT7_24M_CLK				221
+#define IMX8QM_AUD_GPT8_IPG_S				222
+#define IMX8QM_AUD_GPT8_CLKIN				223
+#define IMX8QM_AUD_GPT8_24M_CLK				224
+#define IMX8QM_AUD_GPT9_IPG_S				225
+#define IMX8QM_AUD_GPT9_CLKIN				226
+#define IMX8QM_AUD_GPT9_24M_CLK				227
+#define IMX8QM_AUD_GPT10_IPG_S				228
+#define IMX8QM_AUD_GPT10_CLKIN				229
+#define IMX8QM_AUD_GPT10_24M_CLK			230
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV		232
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK		233
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV		234
+#define IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK		235
+#define IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV		236
+#define IMX8QM_AUD_ACM_AUD_REC_CLK0_CLK		237
+#define IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV		238
+#define IMX8QM_AUD_ACM_AUD_REC_CLK1_CLK		239
+#define IMX8QM_AUD_MCLKOUT0				240
+#define IMX8QM_AUD_MCLKOUT1				241
+#define IMX8QM_AUD_SPDIF_0_TX_CLK			242
+#define IMX8QM_AUD_SPDIF_0_GCLKW			243
+#define IMX8QM_AUD_SPDIF_0_IPG_S			244
+#define IMX8QM_AUD_SPDIF_1_TX_CLK			245
+#define IMX8QM_AUD_SPDIF_1_GCLKW			246
+#define IMX8QM_AUD_SPDIF_1_IPG_S			247
+#define IMX8QM_AUD_ASRC_0_IPG				248
+#define IMX8QM_AUD_ASRC_0_MEM				249
+#define IMX8QM_AUD_ASRC_1_IPG				250
+#define IMX8QM_AUD_ASRC_1_MEM				251
+
+/* VPU */
+#define IMX8QM_VPU_CORE_DIV				252
+#define IMX8QM_VPU_CORE_CLK				253
+#define IMX8QM_VPU_UART_DIV				254
+#define IMX8QM_VPU_UART_CLK				255
+#define IMX8QM_VPU_DDR_DIV				256
+#define IMX8QM_VPU_DDR_CLK				257
+#define IMX8QM_VPU_SYS_DIV				258
+#define IMX8QM_VPU_SYS_CLK				259
+#define IMX8QM_VPU_XUVI_DIV				260
+#define IMX8QM_VPU_XUVI_CLK				261
+
+/* GPU Clocks. */
+#define IMX8QM_GPU0_CORE_DIV				262
+#define IMX8QM_GPU0_CORE_CLK				263
+#define IMX8QM_GPU0_SHADER_DIV				264
+#define IMX8QM_GPU0_SHADER_CLK				265
+#define IMX8QM_GPU1_CORE_DIV				266
+#define IMX8QM_GPU1_CORE_CLK				267
+#define IMX8QM_GPU1_SHADER_DIV				268
+#define IMX8QM_GPU1_SHADER_CLK				269
+
+/* MIPI CSI */
+#define IMX8QM_CSI0_IPG_CLK_S				270
+#define IMX8QM_CSI0_LIS_IPG_CLK				271
+#define IMX8QM_CSI0_APB_CLK				272
+#define IMX8QM_CSI0_I2C0_DIV				273
+#define IMX8QM_CSI0_I2C0_CLK				274
+#define IMX8QM_CSI0_PWM0_DIV				275
+#define IMX8QM_CSI0_PWM0_CLK				276
+#define IMX8QM_CSI0_CORE_DIV				277
+#define IMX8QM_CSI0_CORE_CLK				278
+#define IMX8QM_CSI0_ESC_DIV				279
+#define IMX8QM_CSI0_ESC_CLK				280
+#define IMX8QM_CSI1_IPG_CLK_S				281
+#define IMX8QM_CSI1_LIS_IPG_CLK				282
+#define IMX8QM_CSI1_APB_CLK				283
+#define IMX8QM_CSI1_I2C0_DIV				284
+#define IMX8QM_CSI1_I2C0_CLK				285
+#define IMX8QM_CSI1_PWM0_DIV				286
+#define IMX8QM_CSI1_PWM0_CLK				287
+#define IMX8QM_CSI1_CORE_DIV				288
+#define IMX8QM_CSI1_CORE_CLK				289
+#define IMX8QM_CSI1_ESC_DIV				290
+#define IMX8QM_CSI1_ESC_CLK				291
+
+/* Display */
+#define IMX8QM_DC0_PLL0_DIV				292
+#define IMX8QM_DC0_PLL0_CLK				293
+#define IMX8QM_DC0_PLL1_DIV				294
+#define IMX8QM_DC0_PLL1_CLK				295
+#define IMX8QM_DC0_DISP0_DIV				296
+#define IMX8QM_DC0_DISP0_CLK				297
+#define IMX8QM_DC0_DISP1_DIV				298
+#define IMX8QM_DC0_DISP1_CLK				299
+#define IMX8QM_DC0_BYPASS_0_DIV				300
+#define IMX8QM_DC0_BYPASS_1_DIV				301
+#define IMX8QM_DC0_IRIS_AXI_CLK				302
+#define IMX8AM_DC0_IRIS_MVPL_CLK			303
+#define IMX8QM_DC0_DISP0_MSI_CLK			304
+#define IMX8QM_DC0_LIS_IPG_CLK				305
+#define IMX8QM_DC0_PXL_CMB_APB_CLK			306
+#define IMX8QM_DC0_PRG0_RTRAM_CLK			307
+#define IMX8QM_DC0_PRG1_RTRAM_CLK			308
+#define IMX8QM_DC0_PRG2_RTRAM_CLK			309
+#define IMX8QM_DC0_PRG3_RTRAM_CLK			310
+#define IMX8QM_DC0_PRG4_RTRAM_CLK			311
+#define IMX8QM_DC0_PRG5_RTRAM_CLK			312
+#define IMX8QM_DC0_PRG6_RTRAM_CLK			313
+#define IMX8QM_DC0_PRG7_RTRAM_CLK			314
+#define IMX8QM_DC0_PRG8_RTRAM_CLK			315
+#define IMX8QM_DC0_PRG0_APB_CLK				316
+#define IMX8QM_DC0_PRG1_APB_CLK				317
+#define IMX8QM_DC0_PRG2_APB_CLK				318
+#define IMX8QM_DC0_PRG3_APB_CLK				319
+#define IMX8QM_DC0_PRG4_APB_CLK				320
+#define IMX8QM_DC0_PRG5_APB_CLK				321
+#define IMX8QM_DC0_PRG6_APB_CLK				322
+#define IMX8QM_DC0_PRG7_APB_CLK				323
+#define IMX8QM_DC0_PRG8_APB_CLK				324
+#define IMX8QM_DC0_DPR0_APB_CLK				325
+#define IMX8QM_DC0_DPR1_APB_CLK				326
+#define IMX8QM_DC0_RTRAM0_CLK				327
+#define IMX8QM_DC0_RTRAM1_CLK				328
+#define IMX8QM_DC1_PLL0_DIV				329
+#define IMX8QM_DC1_PLL0_CLK				330
+#define IMX8QM_DC1_PLL1_DIV				331
+#define IMX8QM_DC1_PLL1_CLK				332
+#define IMX8QM_DC1_DISP0_DIV				333
+#define IMX8QM_DC1_DISP0_CLK				334
+#define IMX8QM_DC1_BYPASS_0_DIV				335
+#define IMX8QM_DC1_BYPASS_1_DIV				336
+#define IMX8QM_DC1_DISP1_DIV				337
+#define IMX8QM_DC1_DISP1_CLK				338
+#define IMX8QM_DC1_IRIS_AXI_CLK				339
+#define IMX8AM_DC1_IRIS_MVPL_CLK			340
+#define IMX8QM_DC1_DISP0_MSI_CLK			341
+#define IMX8QM_DC1_LIS_IPG_CLK				342
+#define IMX8QM_DC1_PXL_CMB_APB_CLK			343
+#define IMX8QM_DC1_PRG0_RTRAM_CLK			344
+#define IMX8QM_DC1_PRG1_RTRAM_CLK			345
+#define IMX8QM_DC1_PRG2_RTRAM_CLK			346
+#define IMX8QM_DC1_PRG3_RTRAM_CLK			347
+#define IMX8QM_DC1_PRG4_RTRAM_CLK			348
+#define IMX8QM_DC1_PRG5_RTRAM_CLK			349
+#define IMX8QM_DC1_PRG6_RTRAM_CLK			350
+#define IMX8QM_DC1_PRG7_RTRAM_CLK			351
+#define IMX8QM_DC1_PRG8_RTRAM_CLK			352
+#define IMX8QM_DC1_PRG0_APB_CLK				353
+#define IMX8QM_DC1_PRG1_APB_CLK				354
+#define IMX8QM_DC1_PRG2_APB_CLK				355
+#define IMX8QM_DC1_PRG3_APB_CLK				356
+#define IMX8QM_DC1_PRG4_APB_CLK				357
+#define IMX8QM_DC1_PRG5_APB_CLK				358
+#define IMX8QM_DC1_PRG6_APB_CLK				359
+#define IMX8QM_DC1_PRG7_APB_CLK				360
+#define IMX8QM_DC1_PRG8_APB_CLK				361
+#define IMX8QM_DC1_DPR0_APB_CLK				362
+#define IMX8QM_DC1_DPR1_APB_CLK				363
+#define IMX8QM_DC1_RTRAM0_CLK				364
+#define IMX8QM_DC1_RTRAM1_CLK				365
+
+/* DRC */
+#define IMX8QM_DRC0_PLL0_DIV				366
+#define IMX8QM_DRC0_PLL0_CLK				367
+#define IMX8QM_DRC0_DIV					368
+#define IMX8QM_DRC0_CLK					369
+#define IMX8QM_DRC1_PLL0_DIV				370
+#define IMX8QM_DRC1_PLL0_CLK				371
+#define IMX8QM_DRC1_DIV					372
+#define IMX8QM_DRC1_CLK					373
+
+/* HDMI */
+#define IMX8QM_HDMI_AV_PLL_DIV				374
+#define IMX8QM_HDMI_AV_PLL_CLK				375
+#define IMX8QM_HDMI_I2S_BYPASS_CLK			376
+#define IMX8QM_HDMI_I2C0_DIV				377
+#define IMX8QM_HDMI_I2C0_CLK				378
+#define IMX8QM_HDMI_PXL_DIV				379
+#define IMX8QM_HDMI_PXL_CLK				380
+#define IMX8QM_HDMI_PXL_LINK_DIV			381
+#define IMX8QM_HDMI_PXL_LINK_CLK			382
+#define IMX8QM_HDMI_PXL_MUX_DIV				383
+#define IMX8QM_HDMI_PXL_MUX_CLK				384
+#define IMX8QM_HDMI_I2S_DIV				385
+#define IMX8QM_HDMI_I2S_CLK				386
+#define IMX8QM_HDMI_HDP_CORE_DIV			387
+#define IMX8QM_HDMI_HDP_CORE_CLK			388
+#define IMX8QM_HDMI_I2C_IPG_S_CLK			389
+#define IMX8QM_HDMI_I2C_IPG_CLK				390
+#define IMX8QM_HDMI_PWM_IPG_S_CLK			391
+#define IMX8QM_HDMI_PWM_IPG_CLK				392
+#define IMX8QM_HDMI_PWM_32K_CLK				393
+#define IMX8QM_HDMI_GPIO_IPG_CLK			394
+#define IMX8QM_HDMI_PXL_LINK_SLV_ODD_CLK		395
+#define IMX8QM_HDMI_PXL_LINK_SLV_EVEN_CLK		396
+#define IMX8QM_HDMI_LIS_IPG_CLK				397
+#define IMX8QM_HDMI_MSI_HCLK				398
+#define IMX8QM_HDMI_PXL_EVEN_CLK			399
+#define IMX8QM_HDMI_HDP_CLK				400
+#define IMX8QM_HDMI_PXL_DBL_CLK				401
+#define IMX8QM_HDMI_APB_CLK				402
+#define IMX8QM_HDMI_PXL_LPCG_CLK			403
+#define IMX8QM_HDMI_HDP_PHY_CLK				404
+#define IMX8QM_HDMI_IPG_DIV				405
+#define IMX8QM_HDMI_VIF_CLK				406
+#define IMX8QM_HDMI_DIG_PLL_DIV				407
+#define IMX8QM_HDMI_DIG_PLL_CLK				408
+#define IMX8QM_HDMI_APB_MUX_CSR_CLK			409
+#define IMX8QM_HDMI_APB_MUX_CTRL_CLK			410
+
+/* RX-HDMI */
+#define IMX8QM_HDMI_RX_I2S_BYPASS_CLK			411
+#define IMX8QM_HDMI_RX_BYPASS_CLK			412
+#define IMX8QM_HDMI_RX_SPDIF_BYPASS_CLK			413
+#define IMX8QM_HDMI_RX_I2C0_DIV				414
+#define IMX8QM_HDMI_RX_I2C0_CLK				415
+#define IMX8QM_HDMI_RX_SPDIF_DIV			416
+#define IMX8QM_HDMI_RX_SPDIF_CLK			417
+#define IMX8QM_HDMI_RX_HD_REF_DIV			418
+#define IMX8QM_HDMI_RX_HD_REF_CLK			419
+#define IMX8QM_HDMI_RX_HD_CORE_DIV			420
+#define IMX8QM_HDMI_RX_HD_CORE_CLK			421
+#define IMX8QM_HDMI_RX_PXL_DIV				422
+#define IMX8QM_HDMI_RX_PXL_CLK				423
+#define IMX8QM_HDMI_RX_I2S_DIV				424
+#define IMX8QM_HDMI_RX_I2S_CLK				425
+#define IMX8QM_HDMI_RX_PWM_DIV				426
+#define IMX8QM_HDMI_RX_PWM_CLK				427
+
+/* LVDS */
+#define IMX8QM_LVDS0_BYPASS_CLK				428
+#define IMX8QM_LVDS0_PIXEL_DIV				429
+#define IMX8QM_LVDS0_PIXEL_CLK				430
+#define IMX8QM_LVDS0_PHY_DIV				431
+#define IMX8QM_LVDS0_PHY_CLK				432
+#define IMX8QM_LVDS0_I2C0_IPG_CLK			433
+#define IMX8QM_LVDS0_I2C0_DIV				434
+#define IMX8QM_LVDS0_I2C0_CLK				435
+#define IMX8QM_LVDS0_I2C1_IPG_CLK			436
+#define IMX8QM_LVDS0_I2C1_DIV				437
+#define IMX8QM_LVDS0_I2C1_CLK				438
+#define IMX8QM_LVDS0_PWM0_IPG_CLK			439
+#define IMX8QM_LVDS0_PWM0_DIV				440
+#define IMX8QM_LVDS0_PWM0_CLK				441
+#define IMX8QM_LVDS0_GPIO_IPG_CLK			444
+#define IMX8QM_LVDS1_BYPASS_DIV				445
+#define IMX8QM_LVDS1_BYPASS_CLK				446
+#define IMX8QM_LVDS1_PIXEL_DIV				447
+#define IMX8QM_LVDS1_PIXEL_CLK				448
+#define IMX8QM_LVDS1_PHY_DIV				449
+#define IMX8QM_LVDS1_PHY_CLK				450
+#define IMX8QM_LVDS1_I2C0_IPG_CLK			451
+#define IMX8QM_LVDS1_I2C0_DIV				452
+#define IMX8QM_LVDS1_I2C0_CLK				453
+#define IMX8QM_LVDS1_I2C1_IPG_CLK			454
+#define IMX8QM_LVDS1_I2C1_DIV				455
+#define IMX8QM_LVDS1_I2C1_CLK				456
+#define IMX8QM_LVDS1_PWM0_IPG_CLK			457
+#define IMX8QM_LVDS1_PWM0_DIV				458
+#define IMX8QM_LVDS1_PWM0_CLK				459
+#define IMX8QM_LVDS1_GPIO_IPG_CLK			462
+
+/* MIPI */
+#define IMX8QM_MIPI0_BYPASS_CLK				465
+#define IMX8QM_MIPI0_I2C0_DIV				466
+#define IMX8QM_MIPI0_I2C0_CLK				467
+#define IMX8QM_MIPI0_I2C1_DIV				468
+#define IMX8QM_MIPI0_I2C1_CLK				469
+#define IMX8QM_MIPI0_PWM0_DIV				470
+#define IMX8QM_MIPI0_PWM0_CLK				471
+#define IMX8QM_MIPI0_DSI_TX_ESC_DIV			472
+#define IMX8QM_MIPI0_DSI_TX_ESC_CLK			473
+#define IMX8QM_MIPI0_DSI_RX_ESC_DIV			474
+#define IMX8QM_MIPI0_DSI_RX_ESC_CLK			475
+#define IMX8QM_MIPI0_PXL_DIV				476
+#define IMX8QM_MIPI0_PXL_CLK				477
+#define IMX8QM_MIPI1_BYPASS_CLK				479
+#define IMX8QM_MIPI1_I2C0_DIV				480
+#define IMX8QM_MIPI1_I2C0_CLK				481
+#define IMX8QM_MIPI1_I2C1_DIV				482
+#define IMX8QM_MIPI1_I2C1_CLK				483
+#define IMX8QM_MIPI1_PWM0_DIV				484
+#define IMX8QM_MIPI1_PWM0_CLK				485
+#define IMX8QM_MIPI1_DSI_TX_ESC_DIV			486
+#define IMX8QM_MIPI1_DSI_TX_ESC_CLK			487
+#define IMX8QM_MIPI1_DSI_RX_ESC_DIV			488
+#define IMX8QM_MIPI1_DSI_RX_ESC_CLK			489
+#define IMX8QM_MIPI1_PXL_DIV				490
+#define IMX8QM_MIPI1_PXL_CLK				491
+
+/* Imaging */
+#define IMX8QM_IMG_JPEG_ENC_IPG_CLK			492
+#define IMX8QM_IMG_JPEG_ENC_CLK				493
+#define IMX8QM_IMG_JPEG_DEC_IPG_CLK			494
+#define IMX8QM_IMG_JPEG_DEC_CLK				495
+#define IMX8QM_IMG_PXL_LINK_DC0_CLK			496
+#define IMX8QM_IMG_PXL_LINK_DC1_CLK			497
+#define IMX8QM_IMG_PXL_LINK_CSI0_CLK			498
+#define IMX8QM_IMG_PXL_LINK_CSI1_CLK			499
+#define IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK			500
+#define IMX8QM_IMG_PDMA_0_CLK				501
+#define IMX8QM_IMG_PDMA_1_CLK				502
+#define IMX8QM_IMG_PDMA_2_CLK				503
+#define IMX8QM_IMG_PDMA_3_CLK				504
+#define IMX8QM_IMG_PDMA_4_CLK				505
+#define IMX8QM_IMG_PDMA_5_CLK				506
+#define IMX8QM_IMG_PDMA_6_CLK				507
+#define IMX8QM_IMG_PDMA_7_CLK				508
+
+/* HSIO */
+#define IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK		509
+#define IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK		510
+#define IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK		511
+#define IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK		512
+#define IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK		513
+#define IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK		514
+#define IMX8QM_HSIO_PCIE_X1_PER_CLK			515
+#define IMX8QM_HSIO_PCIE_X2_PER_CLK			516
+#define IMX8QM_HSIO_SATA_PER_CLK			517
+#define IMX8QM_HSIO_PHY_X1_PER_CLK			518
+#define IMX8QM_HSIO_PHY_X2_PER_CLK			519
+#define IMX8QM_HSIO_MISC_PER_CLK			520
+#define IMX8QM_HSIO_PHY_X1_APB_CLK			521
+#define IMX8QM_HSIO_PHY_X2_APB_0_CLK		522
+#define IMX8QM_HSIO_PHY_X2_APB_1_CLK		523
+#define IMX8QM_HSIO_SATA_CLK				524
+#define IMX8QM_HSIO_GPIO_CLK				525
+#define IMX8QM_HSIO_PHY_X1_PCLK				526
+#define IMX8QM_HSIO_PHY_X2_PCLK_0			527
+#define IMX8QM_HSIO_PHY_X2_PCLK_1			528
+#define IMX8QM_HSIO_SATA_EPCS_RX_CLK		529
+#define IMX8QM_HSIO_SATA_EPCS_TX_CLK		530
+
+/* M4 */
+#define IMX8QM_M4_0_CORE_DIV				531
+#define IMX8QM_M4_0_CORE_CLK				532
+#define IMX8QM_M4_0_I2C_DIV				533
+#define IMX8QM_M4_0_I2C_CLK				534
+#define IMX8QM_M4_0_PIT_DIV				535
+#define IMX8QM_M4_0_PIT_CLK				536
+#define IMX8QM_M4_0_TPM_DIV				537
+#define IMX8QM_M4_0_TPM_CLK				538
+#define IMX8QM_M4_0_UART_DIV				539
+#define IMX8QM_M4_0_UART_CLK				540
+#define IMX8QM_M4_0_WDOG_DIV				541
+#define IMX8QM_M4_0_WDOG_CLK				542
+#define IMX8QM_M4_1_CORE_DIV				543
+#define IMX8QM_M4_1_CORE_CLK				544
+#define IMX8QM_M4_1_I2C_DIV				545
+#define IMX8QM_M4_1_I2C_CLK				546
+#define IMX8QM_M4_1_PIT_DIV				547
+#define IMX8QM_M4_1_PIT_CLK				548
+#define IMX8QM_M4_1_TPM_DIV				549
+#define IMX8QM_M4_1_TPM_CLK				550
+#define IMX8QM_M4_1_UART_DIV				551
+#define IMX8QM_M4_1_UART_CLK				552
+#define IMX8QM_M4_1_WDOG_DIV				553
+#define IMX8QM_M4_1_WDOG_CLK				554
+
+/* IPG clocks */
+#define IMX8QM_24MHZ					555
+#define IMX8QM_GPT_3M					556
+#define IMX8QM_IPG_DMA_CLK_ROOT				557
+#define IMX8QM_IPG_AUD_CLK_ROOT				558
+#define IMX8QM_IPG_CONN_CLK_ROOT			559
+#define IMX8QM_AHB_CONN_CLK_ROOT			560
+#define IMX8QM_AXI_CONN_CLK_ROOT			561
+#define IMX8QM_IPG_MIPI_CSI_CLK_ROOT			562
+#define IMX8QM_DC_AXI_EXT_CLK				563
+#define IMX8QM_DC_AXI_INT_CLK				564
+#define IMX8QM_DC_CFG_CLK				565
+#define IMX8QM_HDMI_IPG_CLK				566
+#define IMX8QM_LVDS_IPG_CLK				567
+#define IMX8QM_IMG_AXI_CLK				568
+#define IMX8QM_IMG_IPG_CLK				569
+#define IMX8QM_IMG_PXL_CLK				570
+#define IMX8QM_CSI0_I2C0_IPG_CLK			571
+#define IMX8QM_CSI0_PWM0_IPG_CLK			572
+#define IMX8QM_CSI1_I2C0_IPG_CLK			573
+#define IMX8QM_CSI1_PWM0_IPG_CLK			574
+#define IMX8QM_DC0_DPR0_B_CLK				575
+#define IMX8QM_DC0_DPR1_B_CLK				576
+#define IMX8QM_DC1_DPR0_B_CLK				577
+#define IMX8QM_DC1_DPR1_B_CLK				578
+#define IMX8QM_32KHZ					579
+#define IMX8QM_HSIO_AXI_CLK				580
+#define IMX8QM_HSIO_PER_CLK				581
+#define IMX8QM_HDMI_RX_GPIO_IPG_S_CLK			582
+#define IMX8QM_HDMI_RX_PWM_IPG_S_CLK			583
+#define IMX8QM_HDMI_RX_PWM_IPG_CLK			584
+#define IMX8QM_HDMI_RX_I2C_DIV_CLK			585
+#define IMX8QM_HDMI_RX_I2C_IPG_S_CLK			586
+#define IMX8QM_HDMI_RX_I2C_IPG_CLK			587
+#define IMX8QM_HDMI_RX_SINK_PCLK			588
+#define IMX8QM_HDMI_RX_SINK_SCLK			589
+#define IMX8QM_HDMI_RX_PXL_ENC_CLK			590
+#define IMX8QM_HDMI_RX_IPG_CLK				591
+
+/* ACM */
+#define IMX8QM_HDMI_RX_MCLK			592
+#define IMX8QM_EXT_AUD_MCLK0			593
+#define IMX8QM_EXT_AUD_MCLK1			594
+#define IMX8QM_ESAI0_RX_CLK			595
+#define IMX8QM_ESAI0_RX_HF_CLK			596
+#define IMX8QM_ESAI0_TX_CLK			597
+#define IMX8QM_ESAI0_TX_HF_CLK			598
+#define IMX8QM_ESAI1_RX_CLK			599
+#define IMX8QM_ESAI1_RX_HF_CLK			600
+#define IMX8QM_ESAI1_TX_CLK			601
+#define IMX8QM_ESAI1_TX_HF_CLK			602
+#define IMX8QM_SPDIF0_RX			603
+#define IMX8QM_SPDIF1_RX			604
+#define IMX8QM_SAI0_RX_BCLK			605
+#define IMX8QM_SAI0_TX_BCLK			606
+#define IMX8QM_SAI1_RX_BCLK			607
+#define IMX8QM_SAI1_TX_BCLK			608
+#define IMX8QM_SAI2_RX_BCLK			609
+#define IMX8QM_SAI3_RX_BCLK			610
+#define IMX8QM_HDMI_RX_SAI0_RX_BCLK		611
+#define IMX8QM_SAI6_RX_BCLK			612
+#define IMX8QM_HDMI_TX_SAI0_TX_BCLK		613
+
+#define IMX8QM_ACM_AUD_CLK0_SEL		614
+#define IMX8QM_ACM_AUD_CLK0_CLK		615
+#define IMX8QM_ACM_AUD_CLK1_SEL		616
+#define IMX8QM_ACM_AUD_CLK1_CLK		617
+#define IMX8QM_ACM_MCLKOUT0_SEL		618
+#define IMX8QM_ACM_MCLKOUT0_CLK		619
+#define IMX8QM_ACM_MCLKOUT1_SEL		620
+#define IMX8QM_ACM_MCLKOUT1_CLK		621
+#define IMX8QM_ACM_ASRC0_MUX_CLK_SEL		622
+#define IMX8QM_ACM_ASRC0_MUX_CLK_CLK		623
+#define IMX8QM_ACM_ASRC1_MUX_CLK_SEL		624
+#define IMX8QM_ACM_ASRC1_MUX_CLK_CLK		625
+#define IMX8QM_ACM_ESAI0_MCLK_SEL		626
+#define IMX8QM_ACM_ESAI0_MCLK_CLK		627
+#define IMX8QM_ACM_ESAI1_MCLK_SEL		628
+#define IMX8QM_ACM_ESAI1_MCLK_CLK		629
+#define IMX8QM_ACM_GPT0_MUX_CLK_SEL		630
+#define IMX8QM_ACM_GPT0_MUX_CLK_CLK		631
+#define IMX8QM_ACM_GPT1_MUX_CLK_SEL		632
+#define IMX8QM_ACM_GPT1_MUX_CLK_CLK		633
+#define IMX8QM_ACM_GPT2_MUX_CLK_SEL		634
+#define IMX8QM_ACM_GPT2_MUX_CLK_CLK		635
+#define IMX8QM_ACM_GPT3_MUX_CLK_SEL		636
+#define IMX8QM_ACM_GPT3_MUX_CLK_CLK		637
+#define IMX8QM_ACM_GPT4_MUX_CLK_SEL		638
+#define IMX8QM_ACM_GPT4_MUX_CLK_CLK		639
+#define IMX8QM_ACM_GPT5_MUX_CLK_SEL		640
+#define IMX8QM_ACM_GPT5_MUX_CLK_CLK		641
+#define IMX8QM_ACM_SAI0_MCLK_SEL		642
+#define IMX8QM_ACM_SAI0_MCLK_CLK		643
+#define IMX8QM_ACM_SAI1_MCLK_SEL		644
+#define IMX8QM_ACM_SAI1_MCLK_CLK		645
+#define IMX8QM_ACM_SAI2_MCLK_SEL		646
+#define IMX8QM_ACM_SAI2_MCLK_CLK		647
+#define IMX8QM_ACM_SAI3_MCLK_SEL		648
+#define IMX8QM_ACM_SAI3_MCLK_CLK		649
+#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_SEL	650
+#define IMX8QM_ACM_HDMI_RX_SAI0_MCLK_CLK	651
+#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL	652
+#define IMX8QM_ACM_HDMI_TX_SAI0_MCLK_CLK	653
+#define IMX8QM_ACM_SAI6_MCLK_SEL		654
+#define IMX8QM_ACM_SAI6_MCLK_CLK		655
+#define IMX8QM_ACM_SAI7_MCLK_SEL		656
+#define IMX8QM_ACM_SAI7_MCLK_CLK		657
+#define IMX8QM_ACM_SPDIF0_TX_CLK_SEL		658
+#define IMX8QM_ACM_SPDIF0_TX_CLK_CLK		659
+#define IMX8QM_ACM_SPDIF1_TX_CLK_SEL		660
+#define IMX8QM_ACM_SPDIF1_TX_CLK_CLK		661
+#define IMX8QM_ACM_MQS_TX_CLK_SEL		662
+#define IMX8QM_ACM_MQS_TX_CLK_CLK		663
+
+#define IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL	664
+#define IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK	665
+#define IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL	666
+#define IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK	667
+#define IMX8QM_ENET0_REF_50MHZ_CLK			668
+#define IMX8QM_ENET1_REF_50MHZ_CLK			669
+#define IMX8QM_ENET_25MHZ_CLK				670
+#define IMX8QM_ENET_125MHZ_CLK				671
+#define IMX8QM_ENET0_REF_DIV				672
+#define IMX8QM_ENET0_REF_CLK				673
+#define IMX8QM_ENET1_REF_DIV				674
+#define IMX8QM_ENET1_REF_CLK				675
+#define IMX8QM_ENET0_RMII_TX_CLK			676
+#define IMX8QM_ENET1_RMII_TX_CLK			677
+#define IMX8QM_ENET0_RMII_TX_SEL			678
+#define IMX8QM_ENET1_RMII_TX_SEL			679
+#define IMX8QM_ENET0_RMII_RX_CLK			680
+#define IMX8QM_ENET1_RMII_RX_CLK			681
+
+#define IMX8QM_KPP_CLK					683
+#define IMX8QM_GPT0_HF_CLK				684
+#define IMX8QM_GPT0_IPG_S_CLK				685
+#define IMX8QM_GPT0_IPG_SLV_CLK				686
+#define IMX8QM_GPT0_IPG_MSTR_CLK			687
+#define IMX8QM_GPT1_HF_CLK				688
+#define IMX8QM_GPT1_IPG_S_CLK				689
+#define IMX8QM_GPT1_IPG_SLV_CLK				690
+#define IMX8QM_GPT1_IPG_MSTR_CLK			691
+#define IMX8QM_GPT2_HF_CLK				692
+#define IMX8QM_GPT2_IPG_S_CLK				693
+#define IMX8QM_GPT2_IPG_SLV_CLK				694
+#define IMX8QM_GPT2_IPG_MSTR_CLK			695
+#define IMX8QM_GPT3_HF_CLK				696
+#define IMX8QM_GPT3_IPG_S_CLK				697
+#define IMX8QM_GPT3_IPG_SLV_CLK				698
+#define IMX8QM_GPT3_IPG_MSTR_CLK			699
+#define IMX8QM_GPT4_HF_CLK				700
+#define IMX8QM_GPT4_IPG_S_CLK				701
+#define IMX8QM_GPT4_IPG_SLV_CLK				702
+#define IMX8QM_GPT4_IPG_MSTR_CLK			703
+#define IMX8QM_PWM0_HF_CLK				704
+#define IMX8QM_PWM0_IPG_S_CLK				705
+#define IMX8QM_PWM0_IPG_SLV_CLK				706
+#define IMX8QM_PWM0_IPG_MSTR_CLK			707
+#define IMX8QM_PWM1_HF_CLK				708
+#define IMX8QM_PWM1_IPG_S_CLK				709
+#define IMX8QM_PWM1_IPG_SLV_CLK				710
+#define IMX8QM_PWM1_IPG_MSTR_CLK			711
+#define IMX8QM_PWM2_HF_CLK				712
+#define IMX8QM_PWM2_IPG_S_CLK				713
+#define IMX8QM_PWM2_IPG_SLV_CLK				714
+#define IMX8QM_PWM2_IPG_MSTR_CLK			715
+#define IMX8QM_PWM3_HF_CLK				716
+#define IMX8QM_PWM3_IPG_S_CLK				717
+#define IMX8QM_PWM3_IPG_SLV_CLK				718
+#define IMX8QM_PWM3_IPG_MSTR_CLK			719
+#define IMX8QM_PWM4_HF_CLK				720
+#define IMX8QM_PWM4_IPG_S_CLK				721
+#define IMX8QM_PWM4_IPG_SLV_CLK				722
+#define IMX8QM_PWM4_IPG_MSTR_CLK			723
+#define IMX8QM_PWM5_HF_CLK				724
+#define IMX8QM_PWM5_IPG_S_CLK				725
+#define IMX8QM_PWM5_IPG_SLV_CLK				726
+#define IMX8QM_PWM5_IPG_MSTR_CLK			727
+#define IMX8QM_PWM6_HF_CLK				728
+#define IMX8QM_PWM6_IPG_S_CLK				729
+#define IMX8QM_PWM6_IPG_SLV_CLK				730
+#define IMX8QM_PWM6_IPG_MSTR_CLK			731
+#define IMX8QM_PWM7_HF_CLK				732
+#define IMX8QM_PWM7_IPG_S_CLK				733
+#define IMX8QM_PWM7_IPG_SLV_CLK				734
+#define IMX8QM_PWM7_IPG_MSTR_CLK			735
+#define IMX8QM_FSPI0_HCLK				736
+#define IMX8QM_FSPI0_IPG_CLK				737
+#define IMX8QM_FSPI0_IPG_S_CLK				738
+#define IMX8QM_FSPI1_HCLK				736
+#define IMX8QM_FSPI1_IPG_CLK				737
+#define IMX8QM_FSPI1_IPG_S_CLK				738
+#define IMX8QM_GPIO0_IPG_S_CLK				739
+#define IMX8QM_GPIO1_IPG_S_CLK				740
+#define IMX8QM_GPIO2_IPG_S_CLK				741
+#define IMX8QM_GPIO3_IPG_S_CLK				742
+#define IMX8QM_GPIO4_IPG_S_CLK				743
+#define IMX8QM_GPIO5_IPG_S_CLK				744
+#define IMX8QM_GPIO6_IPG_S_CLK				745
+#define IMX8QM_GPIO7_IPG_S_CLK				746
+#define IMX8QM_ROMCP_CLK				747
+#define IMX8QM_ROMCP_REG_CLK				748
+#define IMX8QM_96KROM_CLK				749
+#define IMX8QM_OCRAM_MEM_CLK				750
+#define IMX8QM_OCRAM_CTRL_CLK				751
+#define IMX8QM_LSIO_BUS_CLK				752
+#define IMX8QM_LSIO_MEM_CLK				753
+#define IMX8QM_LVDS0_LIS_IPG_CLK			754
+#define IMX8QM_LVDS1_LIS_IPG_CLK			755
+#define IMX8QM_MIPI0_LIS_IPG_CLK			756
+#define IMX8QM_MIPI0_I2C0_IPG_S_CLK			757
+#define IMX8QM_MIPI0_I2C0_IPG_CLK			758
+#define IMX8QM_MIPI0_I2C1_IPG_S_CLK			759
+#define IMX8QM_MIPI0_I2C1_IPG_CLK			760
+#define IMX8QM_MIPI0_CLK_ROOT				761
+#define IMX8QM_MIPI1_LIS_IPG_CLK			762
+#define IMX8QM_MIPI1_I2C0_IPG_S_CLK			763
+#define IMX8QM_MIPI1_I2C0_IPG_CLK			764
+#define IMX8QM_MIPI1_I2C1_IPG_S_CLK			765
+#define IMX8QM_MIPI1_I2C1_IPG_CLK			766
+#define IMX8QM_MIPI1_CLK_ROOT				767
+#define IMX8QM_DC0_DISP0_SEL				768
+#define IMX8QM_DC0_DISP1_SEL				769
+#define IMX8QM_DC1_DISP0_SEL				770
+#define IMX8QM_DC1_DISP1_SEL				771
+
+/* CM40 */
+#define IMX8QM_CM40_IPG_CLK				772
+#define IMX8QM_CM40_I2C_DIV				773
+#define IMX8QM_CM40_I2C_CLK				774
+#define IMX8QM_CM40_I2C_IPG_CLK				775
+
+/* CM41 */
+#define IMX8QM_CM41_IPG_CLK				776
+#define IMX8QM_CM41_I2C_DIV				777
+#define IMX8QM_CM41_I2C_CLK				778
+#define IMX8QM_CM41_I2C_IPG_CLK				779
+
+#define IMX8QM_HDMI_PXL_SEL				780
+#define IMX8QM_HDMI_PXL_LINK_SEL			781
+#define IMX8QM_HDMI_PXL_MUX_SEL				782
+#define IMX8QM_HDMI_AV_PLL_BYPASS_CLK			783
+
+#define IMX8QM_HDMI_RX_PXL_SEL				784
+#define IMX8QM_HDMI_RX_HD_REF_SEL			785
+#define IMX8QM_HDMI_RX_HD_CORE_SEL			786
+#define IMX8QM_HDMI_RX_DIG_PLL_CLK			787
+
+#define IMX8QM_LSIO_MU5A_IPG_S_CLK			788
+#define IMX8QM_LSIO_MU5A_IPG_CLK			789
+#define IMX8QM_LSIO_MU6A_IPG_S_CLK			790
+#define IMX8QM_LSIO_MU6A_IPG_CLK			791
+
+/* DSP */
+#define IMX8QM_AUD_DSP_ADB_ACLK				792
+#define IMX8QM_AUD_DSP_IPG				793
+#define IMX8QM_AUD_DSP_CORE_CLK				794
+#define IMX8QM_AUD_OCRAM_IPG				795
+
+#define IMX8QM_CLK_END					796
+
+#endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */
diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h
new file mode 100644
index 0000000..d0334ea
--- /dev/null
+++ b/include/dt-bindings/clock/imx8qxp-clock.h
@@ -0,0 +1,583 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H
+#define __DT_BINDINGS_CLOCK_IMX8QXP_H
+
+#define IMX8QXP_CLK_DUMMY					0
+
+#define IMX8QXP_UART0_IPG_CLK					1
+#define IMX8QXP_UART0_DIV					2
+#define IMX8QXP_UART0_CLK					3
+
+#define IMX8QXP_IPG_DMA_CLK_ROOT				4
+
+/* GPU Clocks. */
+#define IMX8QXP_GPU0_CORE_DIV					5
+#define IMX8QXP_GPU0_CORE_CLK					6
+#define IMX8QXP_GPU0_SHADER_DIV					7
+#define IMX8QXP_GPU0_SHADER_CLK					8
+
+#define IMX8QXP_24MHZ						9
+#define IMX8QXP_GPT_3M						10
+#define IMX8QXP_32KHZ						11
+
+/* LSIO SS */
+#define IMX8QXP_LSIO_MEM_CLK					12
+#define IMX8QXP_LSIO_BUS_CLK					13
+#define IMX8QXP_LSIO_PWM0_DIV					14
+#define IMX8QXP_LSIO_PWM0_IPG_S_CLK				15
+#define IMX8QXP_LSIO_PWM0_IPG_SLV_CLK				16
+#define IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK				17
+#define IMX8QXP_LSIO_PWM0_HF_CLK				18
+#define IMX8QXP_LSIO_PWM0_CLK					19
+#define IMX8QXP_LSIO_PWM1_DIV					20
+#define IMX8QXP_LSIO_PWM1_IPG_S_CLK				21
+#define IMX8QXP_LSIO_PWM1_IPG_SLV_CLK				22
+#define IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK				23
+#define IMX8QXP_LSIO_PWM1_HF_CLK				24
+#define IMX8QXP_LSIO_PWM1_CLK					25
+#define IMX8QXP_LSIO_PWM2_DIV					26
+#define IMX8QXP_LSIO_PWM2_IPG_S_CLK				27
+#define IMX8QXP_LSIO_PWM2_IPG_SLV_CLK				28
+#define IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK				29
+#define IMX8QXP_LSIO_PWM2_HF_CLK				30
+#define IMX8QXP_LSIO_PWM2_CLK					31
+#define IMX8QXP_LSIO_PWM3_DIV					32
+#define IMX8QXP_LSIO_PWM3_IPG_S_CLK				33
+#define IMX8QXP_LSIO_PWM3_IPG_SLV_CLK				34
+#define IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK				35
+#define IMX8QXP_LSIO_PWM3_HF_CLK				36
+#define IMX8QXP_LSIO_PWM3_CLK					37
+#define IMX8QXP_LSIO_PWM4_DIV					38
+#define IMX8QXP_LSIO_PWM4_IPG_S_CLK				39
+#define IMX8QXP_LSIO_PWM4_IPG_SLV_CLK				40
+#define IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK				42
+#define IMX8QXP_LSIO_PWM4_HF_CLK				43
+#define IMX8QXP_LSIO_PWM4_CLK					44
+#define IMX8QXP_LSIO_PWM5_DIV					45
+#define IMX8QXP_LSIO_PWM5_IPG_S_CLK				46
+#define IMX8QXP_LSIO_PWM5_IPG_SLV_CLK				47
+#define IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK				48
+#define IMX8QXP_LSIO_PWM5_HF_CLK				49
+#define IMX8QXP_LSIO_PWM5_CLK					50
+#define IMX8QXP_LSIO_PWM6_DIV					51
+#define IMX8QXP_LSIO_PWM6_IPG_S_CLK				52
+#define IMX8QXP_LSIO_PWM6_IPG_SLV_CLK				53
+#define IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK				54
+#define IMX8QXP_LSIO_PWM6_HF_CLK				55
+#define IMX8QXP_LSIO_PWM6_CLK					56
+#define IMX8QXP_LSIO_PWM7_DIV					57
+#define IMX8QXP_LSIO_PWM7_IPG_S_CLK				58
+#define IMX8QXP_LSIO_PWM7_IPG_SLV_CLK				59
+#define IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK				60
+#define IMX8QXP_LSIO_PWM7_HF_CLK				61
+#define IMX8QXP_LSIO_PWM7_CLK					62
+#define IMX8QXP_LSIO_GPT0_DIV					63
+#define IMX8QXP_LSIO_GPT0_IPG_S_CLK				64
+#define IMX8QXP_LSIO_GPT0_IPG_SLV_CLK				65
+#define IMX8QXP_LSIO_GPT0_IPG_MSTR_CLK				66
+#define IMX8QXP_LSIO_GPT0_HF_CLK				67
+#define IMX8QXP_LSIO_GPT0_CLK					68
+#define IMX8QXP_LSIO_GPT1_DIV					69
+#define IMX8QXP_LSIO_GPT1_IPG_S_CLK				70
+#define IMX8QXP_LSIO_GPT1_IPG_SLV_CLK				71
+#define IMX8QXP_LSIO_GPT1_IPG_MSTR_CLK				72
+#define IMX8QXP_LSIO_GPT1_HF_CLK				73
+#define IMX8QXP_LSIO_GPT1_CLK					74
+#define IMX8QXP_LSIO_GPT2_DIV					75
+#define IMX8QXP_LSIO_GPT2_IPG_S_CLK				76
+#define IMX8QXP_LSIO_GPT2_IPG_SLV_CLK				77
+#define IMX8QXP_LSIO_GPT2_IPG_MSTR_CLK				78
+#define IMX8QXP_LSIO_GPT2_HF_CLK				79
+#define IMX8QXP_LSIO_GPT2_CLK					80
+#define IMX8QXP_LSIO_GPT3_DIV					81
+#define IMX8QXP_LSIO_GPT3_IPG_S_CLK				82
+#define IMX8QXP_LSIO_GPT3_IPG_SLV_CLK				83
+#define IMX8QXP_LSIO_GPT3_IPG_MSTR_CLK				84
+#define IMX8QXP_LSIO_GPT3_HF_CLK				85
+#define IMX8QXP_LSIO_GPT3_CLK					86
+#define IMX8QXP_LSIO_GPT4_DIV					87
+#define IMX8QXP_LSIO_GPT4_IPG_S_CLK				88
+#define IMX8QXP_LSIO_GPT4_IPG_SLV_CLK				89
+#define IMX8QXP_LSIO_GPT4_IPG_MSTR_CLK				90
+#define IMX8QXP_LSIO_GPT4_HF_CLK				91
+#define IMX8QXP_LSIO_GPT4_CLK					92
+#define IMX8QXP_LSIO_FSPI0_DIV					93
+#define IMX8QXP_LSIO_FSPI0_HCLK					94
+#define IMX8QXP_LSIO_FSPI0_IPG_S_CLK				95
+#define IMX8QXP_LSIO_FSPI0_IPG_CLK				96
+#define IMX8QXP_LSIO_FSPI0_CLK					97
+#define IMX8QXP_LSIO_FSPI1_DIV					98
+#define IMX8QXP_LSIO_FSPI1_HCLK					99
+#define IMX8QXP_LSIO_FSPI1_IPG_S_CLK				100
+#define IMX8QXP_LSIO_FSPI1_IPG_CLK				101
+#define IMX8QXP_LSIO_FSPI1_CLK					102
+#define IMX8QXP_LSIO_GPIO0_IPG_S_CLK				103
+#define IMX8QXP_LSIO_GPIO1_IPG_S_CLK				104
+#define IMX8QXP_LSIO_GPIO2_IPG_S_CLK				105
+#define IMX8QXP_LSIO_GPIO3_IPG_S_CLK				106
+#define IMX8QXP_LSIO_GPIO4_IPG_S_CLK				107
+#define IMX8QXP_LSIO_GPIO5_IPG_S_CLK				108
+#define IMX8QXP_LSIO_GPIO6_IPG_S_CLK				109
+#define IMX8QXP_LSIO_GPIO7_IPG_S_CLK				110
+#define IMX8QXP_LSIO_ROMCP_REG_CLK				111
+#define IMX8QXP_LSIO_ROMCP_CLK					112
+#define IMX8QXP_LSIO_96KROM_CLK					113
+#define IMX8QXP_LSIO_OCRAM_MEM_CLK				114
+#define IMX8QXP_LSIO_OCRAM_CTRL_CLK				115
+
+/* ADMA SS */
+#define IMX8QXP_UART1_IPG_CLK					116
+#define IMX8QXP_UART2_IPG_CLK					117
+#define IMX8QXP_UART3_IPG_CLK					118
+#define IMX8QXP_UART1_DIV					119
+#define IMX8QXP_UART2_DIV					120
+#define IMX8QXP_UART3_DIV					121
+#define IMX8QXP_UART1_CLK					122
+#define IMX8QXP_UART2_CLK					123
+#define IMX8QXP_UART3_CLK					124
+#define IMX8QXP_SPI0_IPG_CLK					125
+#define IMX8QXP_SPI1_IPG_CLK					126
+#define IMX8QXP_SPI2_IPG_CLK					127
+#define IMX8QXP_SPI3_IPG_CLK					128
+#define IMX8QXP_SPI0_DIV					129
+#define IMX8QXP_SPI1_DIV					130
+#define IMX8QXP_SPI2_DIV					131
+#define IMX8QXP_SPI3_DIV					132
+#define IMX8QXP_SPI0_CLK					133
+#define IMX8QXP_SPI1_CLK					134
+#define IMX8QXP_SPI2_CLK					135
+#define IMX8QXP_SPI3_CLK					136
+#define IMX8QXP_CAN0_IPG_CHI_CLK				137
+#define IMX8QXP_CAN1_IPG_CHI_CLK				138
+#define IMX8QXP_CAN2_IPG_CHI_CLK				139
+#define IMX8QXP_CAN0_IPG_CLK					140
+#define IMX8QXP_CAN1_IPG_CLK					141
+#define IMX8QXP_CAN2_IPG_CLK					142
+#define IMX8QXP_CAN0_DIV					143
+#define IMX8QXP_CAN1_DIV					144
+#define IMX8QXP_CAN2_DIV					145
+#define IMX8QXP_CAN0_CLK					146
+#define IMX8QXP_CAN1_CLK					147
+#define IMX8QXP_CAN2_CLK					148
+#define IMX8QXP_I2C0_IPG_CLK					149
+#define IMX8QXP_I2C1_IPG_CLK					150
+#define IMX8QXP_I2C2_IPG_CLK					151
+#define IMX8QXP_I2C3_IPG_CLK					152
+#define IMX8QXP_I2C0_DIV					153
+#define IMX8QXP_I2C1_DIV					154
+#define IMX8QXP_I2C2_DIV					155
+#define IMX8QXP_I2C3_DIV					156
+#define IMX8QXP_I2C0_CLK					157
+#define IMX8QXP_I2C1_CLK					158
+#define IMX8QXP_I2C2_CLK					159
+#define IMX8QXP_I2C3_CLK					160
+#define IMX8QXP_FTM0_IPG_CLK					161
+#define IMX8QXP_FTM1_IPG_CLK					162
+#define IMX8QXP_FTM0_DIV					163
+#define IMX8QXP_FTM1_DIV					164
+#define IMX8QXP_FTM0_CLK					165
+#define IMX8QXP_FTM1_CLK					166
+#define IMX8QXP_ADC0_IPG_CLK					167
+#define IMX8QXP_ADC0_DIV					168
+#define IMX8QXP_ADC0_CLK					169
+#define IMX8QXP_PWM_IPG_CLK					170
+#define IMX8QXP_PWM_DIV						171
+#define IMX8QXP_PWM_CLK						172
+#define IMX8QXP_LCD_IPG_CLK					173
+#define IMX8QXP_LCD_DIV						174
+#define IMX8QXP_LCD_CLK						175
+
+/* Connectivity SS */
+#define IMX8QXP_AXI_CONN_CLK_ROOT				176
+#define IMX8QXP_AHB_CONN_CLK_ROOT				177
+#define IMX8QXP_IPG_CONN_CLK_ROOT				178
+#define IMX8QXP_SDHC0_IPG_CLK					179
+#define IMX8QXP_SDHC1_IPG_CLK					180
+#define IMX8QXP_SDHC2_IPG_CLK					181
+#define IMX8QXP_SDHC0_DIV					182
+#define IMX8QXP_SDHC1_DIV					183
+#define IMX8QXP_SDHC2_DIV					184
+#define IMX8QXP_SDHC0_CLK					185
+#define IMX8QXP_SDHC1_CLK					186
+#define IMX8QXP_SDHC2_CLK					187
+#define IMX8QXP_ENET0_ROOT_DIV					188
+#define IMX8QXP_ENET0_REF_DIV					189
+#define IMX8QXP_ENET1_REF_DIV					190
+#define IMX8QXP_ENET0_BYPASS_DIV				191
+#define IMX8QXP_ENET0_RGMII_DIV					192
+#define IMX8QXP_ENET1_ROOT_DIV					193
+#define IMX8QXP_ENET1_BYPASS_DIV				194
+#define IMX8QXP_ENET1_RGMII_DIV					195
+#define IMX8QXP_ENET0_AHB_CLK					196
+#define IMX8QXP_ENET0_IPG_S_CLK					197
+#define IMX8QXP_ENET0_IPG_CLK					198
+#define IMX8QXP_ENET1_AHB_CLK					199
+#define IMX8QXP_ENET1_IPG_S_CLK					200
+#define IMX8QXP_ENET1_IPG_CLK					201
+#define IMX8QXP_ENET0_ROOT_CLK					202
+#define IMX8QXP_ENET1_ROOT_CLK					203
+#define IMX8QXP_ENET0_TX_CLK					204
+#define IMX8QXP_ENET1_TX_CLK					205
+#define IMX8QXP_ENET0_PTP_CLK					206
+#define IMX8QXP_ENET1_PTP_CLK					207
+#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL			208
+#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL			209
+#define IMX8QXP_ENET0_RMII_TX_SEL				210
+#define IMX8QXP_ENET1_RMII_TX_SEL				211
+#define IMX8QXP_ENET0_RGMII_TX_CLK				212
+#define IMX8QXP_ENET1_RGMII_TX_CLK				213
+#define IMX8QXP_ENET0_RMII_RX_CLK				214
+#define IMX8QXP_ENET1_RMII_RX_CLK				215
+#define IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK			216
+#define IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK			217
+#define IMX8QXP_ENET0_REF_50MHZ_CLK				218
+#define IMX8QXP_ENET1_REF_50MHZ_CLK				219
+#define IMX8QXP_GPMI_BCH_IO_DIV					220
+#define IMX8QXP_GPMI_BCH_DIV					221
+#define IMX8QXP_GPMI_APB_CLK					222
+#define IMX8QXP_GPMI_APB_BCH_CLK				223
+#define IMX8QXP_GPMI_BCH_IO_CLK					224
+#define IMX8QXP_GPMI_BCH_CLK					225
+#define IMX8QXP_APBHDMA_CLK					226
+#define IMX8QXP_USB3_ACLK_DIV					227
+#define IMX8QXP_USB3_BUS_DIV					228
+#define IMX8QXP_USB3_LPM_DIV					229
+#define IMX8QXP_USB3_IPG_CLK					230
+#define IMX8QXP_USB3_CORE_PCLK					231
+#define IMX8QXP_USB3_PHY_CLK					232
+#define IMX8QXP_USB3_ACLK					233
+#define IMX8QXP_USB3_BUS_CLK					234
+#define IMX8QXP_USB3_LPM_CLK					235
+#define IMX8QXP_USB2_OH_AHB_CLK					236
+#define IMX8QXP_USB2_OH_IPG_S_CLK				237
+#define IMX8QXP_USB2_OH_IPG_S_PL301_CLK				238
+#define IMX8QXP_USB2_PHY_IPG_CLK				239
+#define IMX8QXP_EDMA_CLK					240
+#define IMX8QXP_EDMA_IPG_CLK					241
+#define IMX8QXP_MLB_HCLK					242
+#define IMX8QXP_MLB_CLK						243
+#define IMX8QXP_MLB_IPG_CLK					244
+
+/* Display controller SS */
+/* DC part1 */
+#define IMX8QXP_DC_AXI_EXT_CLK					245
+#define IMX8QXP_DC_AXI_INT_CLK					246
+#define IMX8QXP_DC_CFG_CLK					247
+#define IMX8QXP_DC0_DISP0_CLK					248
+#define IMX8QXP_DC0_DISP1_CLK					249
+#define IMX8QXP_DC0_PRG0_RTRAM_CLK				250
+#define IMX8QXP_DC0_PRG0_APB_CLK				251
+#define IMX8QXP_DC0_PRG1_RTRAM_CLK				252
+#define IMX8QXP_DC0_PRG1_APB_CLK				253
+#define IMX8QXP_DC0_PRG2_RTRAM_CLK				254
+#define IMX8QXP_DC0_PRG2_APB_CLK				255
+#define IMX8QXP_DC0_PRG3_RTRAM_CLK				256
+#define IMX8QXP_DC0_PRG3_APB_CLK				257
+#define IMX8QXP_DC0_PRG4_RTRAM_CLK				258
+#define IMX8QXP_DC0_PRG4_APB_CLK				259
+#define IMX8QXP_DC0_PRG5_RTRAM_CLK				260
+#define IMX8QXP_DC0_PRG5_APB_CLK				261
+#define IMX8QXP_DC0_PRG6_RTRAM_CLK				262
+#define IMX8QXP_DC0_PRG6_APB_CLK				263
+#define IMX8QXP_DC0_PRG7_RTRAM_CLK				264
+#define IMX8QXP_DC0_PRG7_APB_CLK				265
+#define IMX8QXP_DC0_PRG8_RTRAM_CLK				266
+#define IMX8QXP_DC0_PRG8_APB_CLK				267
+#define IMX8QXP_DC0_DPR0_APB_CLK				268
+#define IMX8QXP_DC0_DPR0_B_CLK					269
+#define IMX8QXP_DC0_RTRAM0_CLK					270
+#define IMX8QXP_DC0_RTRAM1_CLK					271
+
+/* MIPI-LVDS part1 */
+#define IMX8QXP_MIPI_IPG_CLK					272
+#define IMX8QXP_MIPI0_I2C0_DIV					273
+#define IMX8QXP_MIPI0_I2C1_DIV					274
+#define IMX8QXP_MIPI0_I2C0_CLK					275
+#define IMX8QXP_MIPI0_I2C1_CLK					276
+#define IMX8QXP_MIPI0_I2C0_IPG_S_CLK				277
+#define IMX8QXP_MIPI0_I2C0_IPG_CLK				278
+#define IMX8QXP_MIPI0_I2C1_IPG_S_CLK				279
+#define IMX8QXP_MIPI0_I2C1_IPG_CLK				280
+#define IMX8QXP_MIPI0_PWM_IPG_S_CLK				281
+#define IMX8QXP_MIPI0_PWM_IPG_CLK				282
+#define IMX8QXP_MIPI0_PWM_32K_CLK				283
+#define IMX8QXP_MIPI0_GPIO_IPG_CLK				284
+
+#define IMX8QXP_IMG_JPEG_ENC_IPG_CLK				285
+#define IMX8QXP_IMG_JPEG_ENC_CLK				286
+#define IMX8QXP_IMG_JPEG_DEC_IPG_CLK				287
+#define IMX8QXP_IMG_JPEG_DEC_CLK				288
+#define IMX8QXP_IMG_PXL_LINK_DC0_CLK				289
+#define IMX8QXP_IMG_PXL_LINK_DC1_CLK				290
+#define IMX8QXP_IMG_PXL_LINK_CSI0_CLK				291
+#define IMX8QXP_IMG_PXL_LINK_CSI1_CLK				292
+#define IMX8QXP_IMG_PXL_LINK_HDMI_IN_CLK			293
+#define IMX8QXP_IMG_PDMA_0_CLK					294
+#define IMX8QXP_IMG_PDMA_1_CLK					295
+#define IMX8QXP_IMG_PDMA_2_CLK					296
+#define IMX8QXP_IMG_PDMA_3_CLK					297
+#define IMX8QXP_IMG_PDMA_4_CLK					298
+#define IMX8QXP_IMG_PDMA_5_CLK					299
+#define IMX8QXP_IMG_PDMA_6_CLK					300
+#define IMX8QXP_IMG_PDMA_7_CLK					301
+#define IMX8QXP_IMG_AXI_CLK					302
+#define IMX8QXP_IMG_IPG_CLK					303
+#define IMX8QXP_IMG_PXL_CLK					304
+
+#define IMX8QXP_CSI0_I2C0_DIV					305
+#define IMX8QXP_CSI0_PWM0_DIV					306
+#define IMX8QXP_CSI0_CORE_DIV					307
+#define IMX8QXP_CSI0_ESC_DIV					308
+#define IMX8QXP_CSI0_IPG_CLK_S					309
+#define IMX8QXP_CSI0_IPG_CLK					310
+#define IMX8QXP_CSI0_APB_CLK					311
+#define IMX8QXP_CSI0_I2C0_IPG_CLK				312
+#define IMX8QXP_CSI0_I2C0_CLK					313
+#define IMX8QXP_CSI0_PWM0_IPG_CLK				314
+#define IMX8QXP_CSI0_PWM0_CLK					315
+#define IMX8QXP_CSI0_CORE_CLK					316
+#define IMX8QXP_CSI0_ESC_CLK					317
+
+#define IMX8QXP_HSIO_AXI_CLK					318
+#define IMX8QXP_HSIO_PER_CLK					319
+#define IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK				320
+#define IMX8QXP_HSIO_PCIE_SLV_AXI_CLK				321
+#define IMX8QXP_HSIO_PCIE_DBI_AXI_CLK				322
+#define IMX8QXP_HSIO_PCIE_X1_PER_CLK				323
+#define IMX8QXP_HSIO_PHY_X1_PER_CLK				324
+#define IMX8QXP_HSIO_MISC_PER_CLK				325
+#define IMX8QXP_HSIO_PHY_X1_APB_CLK				326
+#define IMX8QXP_HSIO_GPIO_CLK					327
+#define IMX8QXP_HSIO_PHY_X1_PCLK				328
+
+#define IMX8QXP_A35_DIV						329
+
+/* ACM */
+#define IMX8QXP_EXT_AUD_MCLK0					330
+#define IMX8QXP_EXT_AUD_MCLK1					331
+#define IMX8QXP_ESAI0_RX_CLK					332
+#define IMX8QXP_ESAI0_RX_HF_CLK					333
+#define IMX8QXP_ESAI0_TX_CLK					334
+#define IMX8QXP_ESAI0_TX_HF_CLK					335
+#define IMX8QXP_SPDIF0_RX					336
+#define IMX8QXP_SAI0_RX_BCLK					337
+#define IMX8QXP_SAI0_TX_BCLK					338
+#define IMX8QXP_SAI1_RX_BCLK					339
+#define IMX8QXP_SAI1_TX_BCLK					340
+#define IMX8QXP_SAI2_RX_BCLK					341
+#define IMX8QXP_SAI3_RX_BCLK					342
+#define IMX8QXP_SAI4_RX_BCLK					343
+
+#define IMX8QXP_ACM_AUD_CLK0_SEL				344
+#define IMX8QXP_ACM_AUD_CLK0_CLK				345
+#define IMX8QXP_ACM_AUD_CLK1_SEL				346
+#define IMX8QXP_ACM_AUD_CLK1_CLK				347
+#define IMX8QXP_ACM_MCLKOUT0_SEL				348
+#define IMX8QXP_ACM_MCLKOUT0_CLK				349
+#define IMX8QXP_ACM_MCLKOUT1_SEL				350
+#define IMX8QXP_ACM_MCLKOUT1_CLK				351
+#define IMX8QXP_ACM_ESAI0_MCLK_SEL				352
+#define IMX8QXP_ACM_ESAI0_MCLK_CLK				353
+#define IMX8QXP_ACM_GPT0_MUX_CLK_SEL				354
+#define IMX8QXP_ACM_GPT0_MUX_CLK_CLK				355
+#define IMX8QXP_ACM_GPT1_MUX_CLK_SEL				356
+#define IMX8QXP_ACM_GPT1_MUX_CLK_CLK				357
+#define IMX8QXP_ACM_GPT2_MUX_CLK_SEL				358
+#define IMX8QXP_ACM_GPT2_MUX_CLK_CLK				359
+#define IMX8QXP_ACM_GPT3_MUX_CLK_SEL				360
+#define IMX8QXP_ACM_GPT3_MUX_CLK_CLK				361
+#define IMX8QXP_ACM_GPT4_MUX_CLK_SEL				362
+#define IMX8QXP_ACM_GPT4_MUX_CLK_CLK				363
+#define IMX8QXP_ACM_GPT5_MUX_CLK_SEL				364
+#define IMX8QXP_ACM_GPT5_MUX_CLK_CLK				365
+#define IMX8QXP_ACM_SAI0_MCLK_SEL				366
+#define IMX8QXP_ACM_SAI0_MCLK_CLK				367
+#define IMX8QXP_ACM_SAI1_MCLK_SEL				368
+#define IMX8QXP_ACM_SAI1_MCLK_CLK				369
+#define IMX8QXP_ACM_SAI2_MCLK_SEL				370
+#define IMX8QXP_ACM_SAI2_MCLK_CLK				371
+#define IMX8QXP_ACM_SAI3_MCLK_SEL				372
+#define IMX8QXP_ACM_SAI3_MCLK_CLK				373
+#define IMX8QXP_ACM_SAI4_MCLK_SEL				374
+#define IMX8QXP_ACM_SAI4_MCLK_CLK				375
+#define IMX8QXP_ACM_SAI5_MCLK_SEL				376
+#define IMX8QXP_ACM_SAI5_MCLK_CLK				377
+#define IMX8QXP_ACM_SPDIF0_TX_CLK_SEL				378
+#define IMX8QXP_ACM_SPDIF0_TX_CLK_CLK				379
+#define IMX8QXP_ACM_MQS_TX_CLK_SEL				380
+#define IMX8QXP_ACM_MQS_TX_CLK_CLK				381
+#define IMX8QXP_ACM_ASRC0_MUX_CLK_SEL				382
+#define IMX8QXP_ACM_ASRC1_MUX_CLK_SEL				383
+#define IMX8QXP_ACM_ASRC0_MUX_CLK_CLK				384
+#define IMX8QXP_ACM_ASRC1_MUX_CLK_CLK				385
+
+#define IMX8QXP_IPG_AUD_CLK_ROOT				386
+
+/* Audio */
+#define IMX8QXP_AUD_PLL0_DIV					387
+#define IMX8QXP_AUD_PLL0					388
+#define IMX8QXP_AUD_PLL1_DIV					389
+#define IMX8QXP_AUD_PLL1					390
+#define IMX8QXP_AUD_AMIX_IPG					391
+#define IMX8QXP_AUD_ESAI_0_IPG					392
+#define IMX8QXP_AUD_ESAI_0_EXTAL_IPG				393
+#define IMX8QXP_AUD_SAI_0_IPG					394
+#define IMX8QXP_AUD_SAI_0_MCLK					395
+#define IMX8QXP_AUD_SAI_1_IPG					396
+#define IMX8QXP_AUD_SAI_1_MCLK					397
+#define IMX8QXP_AUD_SAI_2_IPG					398
+#define IMX8QXP_AUD_SAI_2_MCLK					399
+#define IMX8QXP_AUD_SAI_3_IPG					400
+#define IMX8QXP_AUD_SAI_3_MCLK					401
+#define IMX8QXP_AUD_SAI_4_IPG					402
+#define IMX8QXP_AUD_SAI_4_MCLK					403
+#define IMX8QXP_AUD_SAI_5_IPG					404
+#define IMX8QXP_AUD_SAI_5_MCLK					405
+#define IMX8QXP_AUD_MQS_IPG					406
+#define IMX8QXP_AUD_MQS_HMCLK					407
+#define IMX8QXP_AUD_GPT5_IPG					408
+#define IMX8QXP_AUD_GPT5_CLKIN					409
+#define IMX8QXP_AUD_GPT6_IPG					410
+#define IMX8QXP_AUD_GPT6_CLKIN					411
+#define IMX8QXP_AUD_GPT7_IPG					412
+#define IMX8QXP_AUD_GPT7_CLKIN					413
+#define IMX8QXP_AUD_GPT8_IPG					414
+#define IMX8QXP_AUD_GPT8_CLKIN					415
+#define IMX8QXP_AUD_GPT9_IPG					416
+#define IMX8QXP_AUD_GPT9_CLKIN					417
+#define IMX8QXP_AUD_GPT10_IPG					418
+#define IMX8QXP_AUD_GPT10_CLKIN					419
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV			420
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK			421
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV			422
+#define IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK			423
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV			424
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK0_CLK			425
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV			426
+#define IMX8QXP_AUD_ACM_AUD_REC_CLK1_CLK			427
+#define IMX8QXP_AUD_MCLKOUT0					428
+#define IMX8QXP_AUD_MCLKOUT1					429
+#define IMX8QXP_AUD_SPDIF_0_TX_CLK				430
+#define IMX8QXP_AUD_SPDIF_0_GCLKW				431
+#define IMX8QXP_AUD_SPDIF_0_IPG					432
+#define IMX8QXP_AUD_ASRC_0_IPG					433
+#define IMX8QXP_AUD_ASRC_1_IPG					434
+#define IMX8QXP_AUD_DSP_ADB_ACLK				435
+#define IMX8QXP_AUD_DSP_IPG				        436
+#define IMX8QXP_AUD_DSP_CORE_CLK				437
+#define IMX8QXP_AUD_OCRAM_IPG					438
+
+/* DC part2 */
+#define IMX8QXP_DC0_DISP0_DIV					439
+#define IMX8QXP_DC0_DISP1_DIV					440
+#define IMX8QXP_DC0_BYPASS_0_DIV				441
+#define IMX8QXP_DC0_BYPASS_1_DIV				442
+#define IMX8QXP_DC0_PLL0_DIV					443
+#define IMX8QXP_DC0_PLL1_DIV					444
+#define IMX8QXP_DC0_PLL0_CLK					445
+#define IMX8QXP_DC0_PLL1_CLK					446
+
+/* MIPI-LVDS part2 */
+#define IMX8QXP_MIPI0_BYPASS_CLK				447
+#define IMX8QXP_MIPI0_PIXEL_DIV					448
+#define IMX8QXP_MIPI0_PIXEL_CLK					449
+#define IMX8QXP_MIPI0_LVDS_PIXEL_DIV				450
+#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK				451
+#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK				452
+#define IMX8QXP_MIPI0_LVDS_PHY_DIV				453
+#define IMX8QXP_MIPI0_LVDS_PHY_CLK				454
+#define IMX8QXP_MIPI0_DSI_TX_ESC_DIV				455
+#define IMX8QXP_MIPI0_DSI_RX_ESC_DIV				456
+#define IMX8QXP_MIPI0_DSI_TX_ESC_CLK				457
+#define IMX8QXP_MIPI0_DSI_RX_ESC_CLK				458
+#define IMX8QXP_MIPI0_LIS_IPG_CLK				459
+#define IMX8QXP_MIPI1_I2C0_DIV					460
+#define IMX8QXP_MIPI1_I2C1_DIV					461
+#define IMX8QXP_MIPI1_I2C0_CLK					462
+#define IMX8QXP_MIPI1_I2C1_CLK					463
+#define IMX8QXP_MIPI1_I2C0_IPG_S_CLK				464
+#define IMX8QXP_MIPI1_I2C0_IPG_CLK				465
+#define IMX8QXP_MIPI1_I2C1_IPG_S_CLK				466
+#define IMX8QXP_MIPI1_I2C1_IPG_CLK				467
+#define IMX8QXP_MIPI1_PWM_IPG_S_CLK				468
+#define IMX8QXP_MIPI1_PWM_IPG_CLK				469
+#define IMX8QXP_MIPI1_PWM_32K_CLK				470
+#define IMX8QXP_MIPI1_GPIO_IPG_CLK				471
+#define IMX8QXP_MIPI1_BYPASS_CLK				472
+#define IMX8QXP_MIPI1_PIXEL_DIV					473
+#define IMX8QXP_MIPI1_PIXEL_CLK					474
+#define IMX8QXP_MIPI1_LVDS_PIXEL_DIV				475
+#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK				476
+#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK				477
+#define IMX8QXP_MIPI1_LVDS_PHY_DIV				478
+#define IMX8QXP_MIPI1_LVDS_PHY_CLK				479
+#define IMX8QXP_MIPI1_DSI_TX_ESC_DIV				480
+#define IMX8QXP_MIPI1_DSI_RX_ESC_DIV				481
+#define IMX8QXP_MIPI1_DSI_TX_ESC_CLK				482
+#define IMX8QXP_MIPI1_DSI_RX_ESC_CLK				483
+
+#define IMX8QXP_MIPI1_LIS_IPG_CLK				484
+
+/* CM40 */
+#define IMX8QXP_CM40_IPG_CLK					485
+#define IMX8QXP_CM40_I2C_DIV					486
+#define IMX8QXP_CM40_I2C_CLK					487
+#define IMX8QXP_CM40_I2C_IPG_CLK				488
+
+/* VPU clocks. */
+#define IMX8QXP_VPU_ENC_CLK					489
+#define IMX8QXP_VPU_DEC_CLK					490
+
+/* MIPI-LVDS part3 */
+#define IMX8QXP_MIPI0_DSI_PLL_CLK				491
+#define IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK				492
+#define IMX8QXP_MIPI0_LVDS_PIXEL_SEL				493
+#define IMX8QXP_MIPI0_LVDS_PHY_SEL				494
+#define IMX8QXP_MIPI0_DSI_TX_ESC_SEL				495
+#define IMX8QXP_MIPI0_DSI_RX_ESC_SEL				496
+#define IMX8QXP_MIPI0_DSI_PHY_SEL				498
+#define IMX8QXP_MIPI0_DSI_PHY_DIV				499
+#define IMX8QXP_MIPI0_DSI_PHY_CLK				500
+#define IMX8QXP_MIPI1_DSI_PLL_CLK				501
+#define IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK				502
+#define IMX8QXP_MIPI1_LVDS_PIXEL_SEL				503
+#define IMX8QXP_MIPI1_LVDS_PHY_SEL				504
+#define IMX8QXP_MIPI1_DSI_TX_ESC_SEL				505
+#define IMX8QXP_MIPI1_DSI_RX_ESC_SEL				506
+#define IMX8QXP_MIPI1_DSI_PHY_SEL				507
+#define IMX8QXP_MIPI1_DSI_PHY_DIV				508
+#define IMX8QXP_MIPI1_DSI_PHY_CLK				509
+
+/* DC part3 */
+#define IMX8QXP_DC0_DPR1_APB_CLK				510
+#define IMX8QXP_DC0_DPR1_B_CLK					511
+
+#define	IMX8QXP_CONN_PLL0_CLK					512
+#define	IMX8QXP_CONN_PLL1_CLK					513
+#define IMX8QXP_SDHC0_SEL					514
+#define IMX8QXP_SDHC1_SEL					515
+#define IMX8QXP_SDHC2_SEL					516
+
+/* PARALLER CSI */
+#define IMX8QXP_PARALLEL_CSI_CLK_DPLL		517
+#define IMX8QXP_PARALLEL_CSI_CLK_SEL		518
+#define IMX8QXP_PARALLEL_CSI_PER_CLK_DIV	519
+#define IMX8QXP_PARALLEL_CSI_PIXEL_CLK		520
+#define IMX8QXP_PARALLEL_CSI_IPG_CLK		521
+#define IMX8QXP_PARALLEL_CSI_MCLK_DIV		522
+#define IMX8QXP_PARALLEL_CSI_MISC0_CLK		523
+
+#define IMX8QXP_MIPI0_PWM_DIV					524
+#define IMX8QXP_MIPI1_PWM_DIV					525
+#define IMX8QXP_MIPI0_PWM_CLK					526
+#define IMX8QXP_MIPI1_PWM_CLK					527
+
+#define IMX8QXP_LSIO_MU5A_IPG_S_CLK		528
+#define IMX8QXP_LSIO_MU5A_IPG_CLK		529
+
+#define IMX8QXP_CLK_END						530
+#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */
diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h
new file mode 100644
index 0000000..73214c5
--- /dev/null
+++ b/include/dt-bindings/clock/jz4780-cgu.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ *   - external clocks
+ *   - PLLs
+ *   - muxes/dividers in the order they appear in the jz4780 programmers manual
+ *   - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
+
+#define JZ4780_CLK_EXCLK	0
+#define JZ4780_CLK_RTCLK	1
+#define JZ4780_CLK_APLL		2
+#define JZ4780_CLK_MPLL		3
+#define JZ4780_CLK_EPLL		4
+#define JZ4780_CLK_VPLL		5
+#define JZ4780_CLK_OTGPHY	6
+#define JZ4780_CLK_SCLKA	7
+#define JZ4780_CLK_CPUMUX	8
+#define JZ4780_CLK_CPU		9
+#define JZ4780_CLK_L2CACHE	10
+#define JZ4780_CLK_AHB0		11
+#define JZ4780_CLK_AHB2PMUX	12
+#define JZ4780_CLK_AHB2		13
+#define JZ4780_CLK_PCLK		14
+#define JZ4780_CLK_DDR		15
+#define JZ4780_CLK_VPU		16
+#define JZ4780_CLK_I2SPLL	17
+#define JZ4780_CLK_I2S		18
+#define JZ4780_CLK_LCD0PIXCLK	19
+#define JZ4780_CLK_LCD1PIXCLK	20
+#define JZ4780_CLK_MSCMUX	21
+#define JZ4780_CLK_MSC0		22
+#define JZ4780_CLK_MSC1		23
+#define JZ4780_CLK_MSC2		24
+#define JZ4780_CLK_UHC		25
+#define JZ4780_CLK_SSIPLL	26
+#define JZ4780_CLK_SSI		27
+#define JZ4780_CLK_CIMMCLK	28
+#define JZ4780_CLK_PCMPLL	29
+#define JZ4780_CLK_PCM		30
+#define JZ4780_CLK_GPU		31
+#define JZ4780_CLK_HDMI		32
+#define JZ4780_CLK_BCH		33
+#define JZ4780_CLK_NEMC		34
+#define JZ4780_CLK_OTG0		35
+#define JZ4780_CLK_SSI0		36
+#define JZ4780_CLK_SMB0		37
+#define JZ4780_CLK_SMB1		38
+#define JZ4780_CLK_SCC		39
+#define JZ4780_CLK_AIC		40
+#define JZ4780_CLK_TSSI0	41
+#define JZ4780_CLK_OWI		42
+#define JZ4780_CLK_KBC		43
+#define JZ4780_CLK_SADC		44
+#define JZ4780_CLK_UART0	45
+#define JZ4780_CLK_UART1	46
+#define JZ4780_CLK_UART2	47
+#define JZ4780_CLK_UART3	48
+#define JZ4780_CLK_SSI1		49
+#define JZ4780_CLK_SSI2		50
+#define JZ4780_CLK_PDMA		51
+#define JZ4780_CLK_GPS		52
+#define JZ4780_CLK_MAC		53
+#define JZ4780_CLK_SMB2		54
+#define JZ4780_CLK_CIM		55
+#define JZ4780_CLK_LCD		56
+#define JZ4780_CLK_TVE		57
+#define JZ4780_CLK_IPU		58
+#define JZ4780_CLK_DDR0		59
+#define JZ4780_CLK_DDR1		60
+#define JZ4780_CLK_SMB3		61
+#define JZ4780_CLK_TSSI1	62
+#define JZ4780_CLK_COMPRESS	63
+#define JZ4780_CLK_AIC1		64
+#define JZ4780_CLK_GPVLC	65
+#define JZ4780_CLK_OTG1		66
+#define JZ4780_CLK_UART4	67
+#define JZ4780_CLK_AHBMON	68
+#define JZ4780_CLK_SMB4		69
+#define JZ4780_CLK_DES		70
+#define JZ4780_CLK_X2D		71
+#define JZ4780_CLK_CORE1	72
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h
new file mode 100644
index 0000000..997312e
--- /dev/null
+++ b/include/dt-bindings/clock/maxim,max77802.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77802 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77802_CLK_32K_AP		0
+#define MAX77802_CLK_32K_CP		1
+
+/* Total number of clocks. */
+#define MAX77802_CLKS_NUM		(MAX77802_CLK_32K_CP + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */
diff --git a/include/dt-bindings/clock/microchip,clock.h b/include/dt-bindings/clock/microchip,clock.h
new file mode 100644
index 0000000..ea6f161
--- /dev/null
+++ b/include/dt-bindings/clock/microchip,clock.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
+ *
+ */
+
+#ifndef __CLK_MICROCHIP_PIC32
+#define __CLK_MICROCHIP_PIC32
+
+/* clock output indices */
+#define BASECLK	0
+#define PLLCLK	1
+#define MPLL	2
+#define SYSCLK	3
+#define PB1CLK	4
+#define PB2CLK	5
+#define PB3CLK	6
+#define PB4CLK	7
+#define PB5CLK	8
+#define PB6CLK	9
+#define PB7CLK	10
+#define REF1CLK	11
+#define REF2CLK	12
+#define REF3CLK	13
+#define REF4CLK	14
+#define REF5CLK	15
+
+#endif	/* __CLK_MICROCHIP_PIC32 */
diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h
new file mode 100644
index 0000000..71ced15
--- /dev/null
+++ b/include/dt-bindings/clock/mt7623-clk.h
@@ -0,0 +1,413 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT2701_H
+#define _DT_BINDINGS_CLK_MT2701_H
+
+/* TOPCKGEN */
+#define CLK_TOP_FCLKS_OFF			0
+
+#define CLK_TOP_DPI				0
+#define CLK_TOP_DMPLL				1
+#define CLK_TOP_VENCPLL				2
+#define CLK_TOP_HDMI_0_PIX340M			3
+#define CLK_TOP_HDMI_0_DEEP340M			4
+#define CLK_TOP_HDMI_0_PLL340M			5
+#define CLK_TOP_HADDS2_FB			6
+#define CLK_TOP_WBG_DIG_416M			7
+#define CLK_TOP_DSI0_LNTC_DSI			8
+#define CLK_TOP_HDMI_SCL_RX			9
+#define CLK_TOP_32K_EXTERNAL			10
+#define CLK_TOP_HDMITX_CLKDIG_CTS		11
+#define CLK_TOP_AUD_EXT1			12
+#define CLK_TOP_AUD_EXT2			13
+#define CLK_TOP_NFI1X_PAD			14
+
+#define CLK_TOP_SYSPLL				15
+#define CLK_TOP_SYSPLL_D2			16
+#define CLK_TOP_SYSPLL_D3			17
+#define CLK_TOP_SYSPLL_D5			18
+#define CLK_TOP_SYSPLL_D7			19
+#define CLK_TOP_SYSPLL1_D2			20
+#define CLK_TOP_SYSPLL1_D4			21
+#define CLK_TOP_SYSPLL1_D8			22
+#define CLK_TOP_SYSPLL1_D16			23
+#define CLK_TOP_SYSPLL2_D2			24
+#define CLK_TOP_SYSPLL2_D4			25
+#define CLK_TOP_SYSPLL2_D8			26
+#define CLK_TOP_SYSPLL3_D2			27
+#define CLK_TOP_SYSPLL3_D4			28
+#define CLK_TOP_SYSPLL4_D2			29
+#define CLK_TOP_SYSPLL4_D4			30
+#define CLK_TOP_UNIVPLL				31
+#define CLK_TOP_UNIVPLL_D2			32
+#define CLK_TOP_UNIVPLL_D3			33
+#define CLK_TOP_UNIVPLL_D5			34
+#define CLK_TOP_UNIVPLL_D7			35
+#define CLK_TOP_UNIVPLL_D26			36
+#define CLK_TOP_UNIVPLL_D52			37
+#define CLK_TOP_UNIVPLL_D108			38
+#define CLK_TOP_USB_PHY48M			39
+#define CLK_TOP_UNIVPLL1_D2			40
+#define CLK_TOP_UNIVPLL1_D4			41
+#define CLK_TOP_UNIVPLL1_D8			42
+#define CLK_TOP_UNIVPLL2_D2			43
+#define CLK_TOP_UNIVPLL2_D4			44
+#define CLK_TOP_UNIVPLL2_D8			45
+#define CLK_TOP_UNIVPLL2_D16			46
+#define CLK_TOP_UNIVPLL2_D32			47
+#define CLK_TOP_UNIVPLL3_D2			48
+#define CLK_TOP_UNIVPLL3_D4			49
+#define CLK_TOP_UNIVPLL3_D8			50
+#define CLK_TOP_MSDCPLL				51
+#define CLK_TOP_MSDCPLL_D2			52
+#define CLK_TOP_MSDCPLL_D4			53
+#define CLK_TOP_MSDCPLL_D8			54
+#define CLK_TOP_MMPLL				55
+#define CLK_TOP_MMPLL_D2			56
+#define CLK_TOP_DMPLL_D2			57
+#define CLK_TOP_DMPLL_D4			58
+#define CLK_TOP_DMPLL_X2			59
+#define CLK_TOP_TVDPLL				60
+#define CLK_TOP_TVDPLL_D2			61
+#define CLK_TOP_TVDPLL_D4			62
+#define CLK_TOP_VDECPLL				63
+#define CLK_TOP_TVD2PLL				64
+#define CLK_TOP_TVD2PLL_D2			65
+#define CLK_TOP_MIPIPLL				66
+#define CLK_TOP_MIPIPLL_D2			67
+#define CLK_TOP_MIPIPLL_D4			68
+#define CLK_TOP_HDMIPLL				69
+#define CLK_TOP_HDMIPLL_D2			70
+#define CLK_TOP_HDMIPLL_D3			71
+#define CLK_TOP_ARMPLL_1P3G			72
+#define CLK_TOP_AUDPLL				73
+#define CLK_TOP_AUDPLL_D4			74
+#define CLK_TOP_AUDPLL_D8			75
+#define CLK_TOP_AUDPLL_D16			76
+#define CLK_TOP_AUDPLL_D24			77
+#define CLK_TOP_AUD1PLL_98M			78
+#define CLK_TOP_AUD2PLL_90M			79
+#define CLK_TOP_HADDS2PLL_98M			80
+#define CLK_TOP_HADDS2PLL_294M			81
+#define CLK_TOP_ETHPLL_500M			82
+#define CLK_TOP_CLK26M_D8			83
+#define CLK_TOP_32K_INTERNAL			84
+#define CLK_TOP_AXISEL_D4			85
+#define CLK_TOP_8BDAC				86
+
+#define CLK_TOP_AXI_SEL				87
+#define CLK_TOP_MEM_SEL				88
+#define CLK_TOP_DDRPHYCFG_SEL			89
+#define CLK_TOP_MM_SEL				90
+#define CLK_TOP_PWM_SEL				91
+#define CLK_TOP_VDEC_SEL			92
+#define CLK_TOP_MFG_SEL				93
+#define CLK_TOP_CAMTG_SEL			94
+#define CLK_TOP_UART_SEL			95
+#define CLK_TOP_SPI0_SEL			96
+#define CLK_TOP_USB20_SEL			97
+#define CLK_TOP_MSDC30_0_SEL			98
+#define CLK_TOP_MSDC30_1_SEL			99
+#define CLK_TOP_MSDC30_2_SEL			100
+#define CLK_TOP_AUDIO_SEL			101
+#define CLK_TOP_AUDINTBUS_SEL			102
+#define CLK_TOP_PMICSPI_SEL			103
+#define CLK_TOP_SCP_SEL				104
+#define CLK_TOP_DPI0_SEL			105
+#define CLK_TOP_DPI1_SEL			106
+#define CLK_TOP_TVE_SEL				107
+#define CLK_TOP_HDMI_SEL			108
+#define CLK_TOP_APLL_SEL			109
+#define CLK_TOP_RTC_SEL				110
+#define CLK_TOP_NFI2X_SEL			111
+#define CLK_TOP_EMMC_HCLK_SEL			112
+#define CLK_TOP_FLASH_SEL			113
+#define CLK_TOP_DI_SEL				114
+#define CLK_TOP_NR_SEL				115
+#define CLK_TOP_OSD_SEL				116
+#define CLK_TOP_HDMIRX_BIST_SEL			117
+#define CLK_TOP_INTDIR_SEL			118
+#define CLK_TOP_ASM_I_SEL			119
+#define CLK_TOP_ASM_M_SEL			120
+#define CLK_TOP_ASM_H_SEL			121
+#define CLK_TOP_MS_CARD_SEL			122
+#define CLK_TOP_ETHIF_SEL			123
+#define CLK_TOP_HDMIRX26_24_SEL			124
+#define CLK_TOP_MSDC30_3_SEL			125
+#define CLK_TOP_CMSYS_SEL			126
+#define CLK_TOP_SPI1_SEL			127
+#define CLK_TOP_SPI2_SEL			128
+#define CLK_TOP_8BDAC_SEL			129
+#define CLK_TOP_AUD2DVD_SEL			130
+#define CLK_TOP_PADMCLK_SEL			131
+#define CLK_TOP_AUD_MUX1_SEL			132
+#define CLK_TOP_AUD_MUX2_SEL			133
+#define CLK_TOP_AUDPLL_MUX_SEL			134
+#define CLK_TOP_AUD_K1_SRC_SEL			135
+#define CLK_TOP_AUD_K2_SRC_SEL			136
+#define CLK_TOP_AUD_K3_SRC_SEL			137
+#define CLK_TOP_AUD_K4_SRC_SEL			138
+#define CLK_TOP_AUD_K5_SRC_SEL			139
+#define CLK_TOP_AUD_K6_SRC_SEL			140
+
+#define CLK_TOP_AUD_EXTCK1_DIV			141
+#define CLK_TOP_AUD_EXTCK2_DIV			142
+#define CLK_TOP_AUD_MUX1_DIV			143
+#define CLK_TOP_AUD_MUX2_DIV			144
+#define CLK_TOP_AUD_K1_SRC_DIV			145
+#define CLK_TOP_AUD_K2_SRC_DIV			146
+#define CLK_TOP_AUD_K3_SRC_DIV			147
+#define CLK_TOP_AUD_K4_SRC_DIV			148
+#define CLK_TOP_AUD_K5_SRC_DIV			149
+#define CLK_TOP_AUD_K6_SRC_DIV			150
+#define CLK_TOP_AUD_48K_TIMING			151
+#define CLK_TOP_AUD_44K_TIMING			152
+#define CLK_TOP_AUD_I2S1_MCLK			153
+#define CLK_TOP_AUD_I2S2_MCLK			154
+#define CLK_TOP_AUD_I2S3_MCLK			155
+#define CLK_TOP_AUD_I2S4_MCLK			156
+#define CLK_TOP_AUD_I2S5_MCLK			157
+#define CLK_TOP_AUD_I2S6_MCLK			158
+#define CLK_TOP_NR				159
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL			0
+#define CLK_APMIXED_MAINPLL			1
+#define CLK_APMIXED_UNIVPLL			2
+#define CLK_APMIXED_MMPLL			3
+#define CLK_APMIXED_MSDCPLL			4
+#define CLK_APMIXED_TVDPLL			5
+#define CLK_APMIXED_AUD1PLL			6
+#define CLK_APMIXED_TRGPLL			7
+#define CLK_APMIXED_ETHPLL			8
+#define CLK_APMIXED_VDECPLL			9
+#define CLK_APMIXED_HADDS2PLL			10
+#define CLK_APMIXED_AUD2PLL			11
+#define CLK_APMIXED_TVD2PLL			12
+#define CLK_APMIXED_NR				13
+
+/* INFRACFG */
+#define CLK_INFRA_DBG				0
+#define CLK_INFRA_SMI				1
+#define CLK_INFRA_QAXI_CM4			2
+#define CLK_INFRA_AUD_SPLIN_B			3
+#define CLK_INFRA_AUDIO				4
+#define CLK_INFRA_EFUSE				5
+#define CLK_INFRA_L2C_SRAM			6
+#define CLK_INFRA_M4U				7
+#define CLK_INFRA_CONNMCU			8
+#define CLK_INFRA_TRNG				9
+#define CLK_INFRA_RAMBUFIF			10
+#define CLK_INFRA_CPUM				11
+#define CLK_INFRA_KP				12
+#define CLK_INFRA_CEC				13
+#define CLK_INFRA_IRRX				14
+#define CLK_INFRA_PMICSPI			15
+#define CLK_INFRA_PMICWRAP			16
+#define CLK_INFRA_DDCCI				17
+#define CLK_INFRA_CPUSEL			18
+#define CLK_INFRA_NR				19
+
+/* PERICFG */
+#define CLK_PERI_NFI				0
+#define CLK_PERI_THERM				1
+#define CLK_PERI_PWM1				2
+#define CLK_PERI_PWM2				3
+#define CLK_PERI_PWM3				4
+#define CLK_PERI_PWM4				5
+#define CLK_PERI_PWM5				6
+#define CLK_PERI_PWM6				7
+#define CLK_PERI_PWM7				8
+#define CLK_PERI_PWM				9
+#define CLK_PERI_USB0				10
+#define CLK_PERI_USB1				11
+#define CLK_PERI_AP_DMA				12
+#define CLK_PERI_MSDC30_0			13
+#define CLK_PERI_MSDC30_1			14
+#define CLK_PERI_MSDC30_2			15
+#define CLK_PERI_MSDC30_3			16
+#define CLK_PERI_MSDC50_3			17
+#define CLK_PERI_NLI				18
+#define CLK_PERI_UART0				19
+#define CLK_PERI_UART1				20
+#define CLK_PERI_UART2				21
+#define CLK_PERI_UART3				22
+#define CLK_PERI_BTIF				23
+#define CLK_PERI_I2C0				24
+#define CLK_PERI_I2C1				25
+#define CLK_PERI_I2C2				26
+#define CLK_PERI_I2C3				27
+#define CLK_PERI_AUXADC				28
+#define CLK_PERI_SPI0				39
+#define CLK_PERI_ETH				30
+#define CLK_PERI_USB0_MCU			31
+
+#define CLK_PERI_USB1_MCU			32
+#define CLK_PERI_USB_SLV			33
+#define CLK_PERI_GCPU				34
+#define CLK_PERI_NFI_ECC			35
+#define CLK_PERI_NFI_PAD			36
+#define CLK_PERI_FLASH				37
+#define CLK_PERI_HOST89_INT			38
+#define CLK_PERI_HOST89_SPI			39
+#define CLK_PERI_HOST89_DVD			40
+#define CLK_PERI_SPI1				41
+#define CLK_PERI_SPI2				42
+#define CLK_PERI_FCI				43
+#define CLK_PERI_NR				44
+
+/* AUDIO */
+#define CLK_AUD_AFE				0
+#define CLK_AUD_LRCK_DETECT			1
+#define CLK_AUD_I2S				2
+#define CLK_AUD_APLL_TUNER			3
+#define CLK_AUD_HDMI				4
+#define CLK_AUD_SPDF				5
+#define CLK_AUD_SPDF2				6
+#define CLK_AUD_APLL				7
+#define CLK_AUD_TML				8
+#define CLK_AUD_AHB_IDLE_EXT			9
+#define CLK_AUD_AHB_IDLE_INT			10
+
+#define CLK_AUD_I2SIN1				11
+#define CLK_AUD_I2SIN2				12
+#define CLK_AUD_I2SIN3				13
+#define CLK_AUD_I2SIN4				14
+#define CLK_AUD_I2SIN5				15
+#define CLK_AUD_I2SIN6				16
+#define CLK_AUD_I2SO1				17
+#define CLK_AUD_I2SO2				18
+#define CLK_AUD_I2SO3				19
+#define CLK_AUD_I2SO4				20
+#define CLK_AUD_I2SO5				21
+#define CLK_AUD_I2SO6				22
+#define CLK_AUD_ASRCI1				23
+#define CLK_AUD_ASRCI2				24
+#define CLK_AUD_ASRCO1				25
+#define CLK_AUD_ASRCO2				26
+#define CLK_AUD_ASRC11				27
+#define CLK_AUD_ASRC12				28
+#define CLK_AUD_HDMIRX				29
+#define CLK_AUD_INTDIR				30
+#define CLK_AUD_A1SYS				31
+#define CLK_AUD_A2SYS				32
+#define CLK_AUD_AFE_CONN			33
+#define CLK_AUD_AFE_PCMIF			34
+#define CLK_AUD_AFE_MRGIF			35
+
+#define CLK_AUD_MMIF_UL1			36
+#define CLK_AUD_MMIF_UL2			37
+#define CLK_AUD_MMIF_UL3			38
+#define CLK_AUD_MMIF_UL4			39
+#define CLK_AUD_MMIF_UL5			40
+#define CLK_AUD_MMIF_UL6			41
+#define CLK_AUD_MMIF_DL1			42
+#define CLK_AUD_MMIF_DL2			43
+#define CLK_AUD_MMIF_DL3			44
+#define CLK_AUD_MMIF_DL4			45
+#define CLK_AUD_MMIF_DL5			46
+#define CLK_AUD_MMIF_DL6			47
+#define CLK_AUD_MMIF_DLMCH			48
+#define CLK_AUD_MMIF_ARB1			49
+#define CLK_AUD_MMIF_AWB1			50
+#define CLK_AUD_MMIF_AWB2			51
+#define CLK_AUD_MMIF_DAI			52
+
+#define CLK_AUD_DMIC1				53
+#define CLK_AUD_DMIC2				54
+#define CLK_AUD_ASRCI3				55
+#define CLK_AUD_ASRCI4				56
+#define CLK_AUD_ASRCI5				57
+#define CLK_AUD_ASRCI6				58
+#define CLK_AUD_ASRCO3				59
+#define CLK_AUD_ASRCO4				60
+#define CLK_AUD_ASRCO5				61
+#define CLK_AUD_ASRCO6				62
+#define CLK_AUD_MEM_ASRC1			63
+#define CLK_AUD_MEM_ASRC2			64
+#define CLK_AUD_MEM_ASRC3			65
+#define CLK_AUD_MEM_ASRC4			66
+#define CLK_AUD_MEM_ASRC5			67
+#define CLK_AUD_DSD_ENC				68
+#define CLK_AUD_ASRC_BRG			60
+#define CLK_AUD_NR				70
+
+/* MMSYS */
+#define CLK_MM_SMI_COMMON			0
+#define CLK_MM_SMI_LARB0			1
+#define CLK_MM_CMDQ				2
+#define CLK_MM_MUTEX				3
+#define CLK_MM_DISP_COLOR			4
+#define CLK_MM_DISP_BLS				5
+#define CLK_MM_DISP_WDMA			6
+#define CLK_MM_DISP_RDMA			7
+#define CLK_MM_DISP_OVL				8
+#define CLK_MM_MDP_TDSHP			9
+#define CLK_MM_MDP_WROT				10
+#define CLK_MM_MDP_WDMA				11
+#define CLK_MM_MDP_RSZ1				12
+#define CLK_MM_MDP_RSZ0				13
+#define CLK_MM_MDP_RDMA				14
+#define CLK_MM_MDP_BLS_26M			15
+#define CLK_MM_CAM_MDP				16
+#define CLK_MM_FAKE_ENG				17
+#define CLK_MM_MUTEX_32K			18
+#define CLK_MM_DISP_RDMA1			19
+#define CLK_MM_DISP_UFOE			20
+
+#define CLK_MM_DSI_ENGINE			21
+#define CLK_MM_DSI_DIG				22
+#define CLK_MM_DPI_DIGL				23
+#define CLK_MM_DPI_ENGINE			24
+#define CLK_MM_DPI1_DIGL			25
+#define CLK_MM_DPI1_ENGINE			26
+#define CLK_MM_TVE_OUTPUT			27
+#define CLK_MM_TVE_INPUT			28
+#define CLK_MM_HDMI_PIXEL			29
+#define CLK_MM_HDMI_PLL				30
+#define CLK_MM_HDMI_AUDIO			31
+#define CLK_MM_HDMI_SPDIF			32
+#define CLK_MM_TVE_FMM				33
+#define CLK_MM_NR				34
+
+/* IMGSYS */
+#define CLK_IMG_SMI_COMM			0
+#define CLK_IMG_RESZ				1
+#define CLK_IMG_JPGDEC_SMI			2
+#define CLK_IMG_JPGDEC				3
+#define CLK_IMG_VENC_LT				4
+#define CLK_IMG_VENC				5
+#define CLK_IMG_NR				6
+
+/* VDEC */
+#define CLK_VDEC_CKGEN				0
+#define CLK_VDEC_LARB				1
+#define CLK_VDEC_NR				2
+
+/* HIFSYS */
+#define CLK_HIFSYS_USB0PHY			0
+#define CLK_HIFSYS_USB1PHY			1
+#define CLK_HIFSYS_PCIE0			2
+#define CLK_HIFSYS_PCIE1			3
+#define CLK_HIFSYS_PCIE2			4
+#define CLK_HIFSYS_NR				5
+
+/* ETHSYS */
+#define CLK_ETHSYS_HSDMA			0
+#define CLK_ETHSYS_ESW				1
+#define CLK_ETHSYS_GP2				2
+#define CLK_ETHSYS_GP1				3
+#define CLK_ETHSYS_PCM				4
+#define CLK_ETHSYS_GDMA				5
+#define CLK_ETHSYS_I2S				6
+#define CLK_ETHSYS_CRYPTO			7
+#define CLK_ETHSYS_NR				8
+
+/* G3DSYS */
+#define CLK_G3DSYS_CORE				0
+#define CLK_G3DSYS_NR				1
+
+#endif /* _DT_BINDINGS_CLK_MT2701_H */
diff --git a/include/dt-bindings/clock/mt7628-clk.h b/include/dt-bindings/clock/mt7628-clk.h
new file mode 100644
index 0000000..b5866fd
--- /dev/null
+++ b/include/dt-bindings/clock/mt7628-clk.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_MT7628_CLK_H_
+#define _DT_BINDINGS_MT7628_CLK_H_
+
+/* Base clocks */
+#define CLK_SYS				34
+#define CLK_CPU				33
+#define CLK_XTAL			32
+
+/* Peripheral clocks */
+#define CLK_PWM				31
+#define CLK_SDXC			30
+#define CLK_CRYPTO			29
+#define CLK_MIPS_CNT			28
+#define CLK_PCIE			26
+#define CLK_UPHY			25
+#define CLK_ETH				23
+#define CLK_UART2			20
+#define CLK_UART1			19
+#define CLK_SPI				18
+#define CLK_I2S				17
+#define CLK_I2C				16
+#define CLK_GDMA			14
+#define CLK_PIO				13
+#define CLK_UART0			12
+#define CLK_PCM				11
+#define CLK_MC				10
+#define CLK_INTC			9
+#define CLK_TIMER			8
+
+#endif /* _DT_BINDINGS_MT7628_CLK_H_ */
diff --git a/include/dt-bindings/clock/mt7629-clk.h b/include/dt-bindings/clock/mt7629-clk.h
new file mode 100644
index 0000000..0bbfbfa
--- /dev/null
+++ b/include/dt-bindings/clock/mt7629-clk.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT7629_H
+#define _DT_BINDINGS_CLK_MT7629_H
+
+/* TOPCKGEN */
+#define CLK_TOP_FCLKS_OFF		0
+
+#define CLK_TOP_TO_U2_PHY		0
+#define CLK_TOP_TO_U2_PHY_1P		1
+#define CLK_TOP_PCIE0_PIPE_EN		2
+#define CLK_TOP_PCIE1_PIPE_EN		3
+#define CLK_TOP_SSUSB_TX250M		4
+#define CLK_TOP_SSUSB_EQ_RX250M		5
+#define CLK_TOP_SSUSB_CDR_REF		6
+#define CLK_TOP_SSUSB_CDR_FB		7
+#define CLK_TOP_SATA_ASIC		8
+#define CLK_TOP_SATA_RBC		9
+
+#define CLK_TOP_TO_USB3_SYS		10
+#define CLK_TOP_P1_1MHZ			11
+#define CLK_TOP_4MHZ			12
+#define CLK_TOP_P0_1MHZ			13
+#define CLK_TOP_ETH_500M		14
+#define CLK_TOP_TXCLK_SRC_PRE		15
+#define CLK_TOP_RTC			16
+#define CLK_TOP_PWM_QTR_26M		17
+#define CLK_TOP_CPUM_TCK_IN		18
+#define CLK_TOP_TO_USB3_DA_TOP		19
+#define CLK_TOP_MEMPLL			20
+#define CLK_TOP_DMPLL			21
+#define CLK_TOP_DMPLL_D4		22
+#define CLK_TOP_DMPLL_D8		23
+#define CLK_TOP_SYSPLL_D2		24
+#define CLK_TOP_SYSPLL1_D2		25
+#define CLK_TOP_SYSPLL1_D4		26
+#define CLK_TOP_SYSPLL1_D8		27
+#define CLK_TOP_SYSPLL1_D16		28
+#define CLK_TOP_SYSPLL2_D2		29
+#define CLK_TOP_SYSPLL2_D4		30
+#define CLK_TOP_SYSPLL2_D8		31
+#define CLK_TOP_SYSPLL_D5		32
+#define CLK_TOP_SYSPLL3_D2		33
+#define CLK_TOP_SYSPLL3_D4		34
+#define CLK_TOP_SYSPLL_D7		35
+#define CLK_TOP_SYSPLL4_D2		36
+#define CLK_TOP_SYSPLL4_D4		37
+#define CLK_TOP_SYSPLL4_D16		38
+#define CLK_TOP_UNIVPLL			39
+#define CLK_TOP_UNIVPLL1_D2		40
+#define CLK_TOP_UNIVPLL1_D4		41
+#define CLK_TOP_UNIVPLL1_D8		42
+#define CLK_TOP_UNIVPLL_D3		43
+#define CLK_TOP_UNIVPLL2_D2		44
+#define CLK_TOP_UNIVPLL2_D4		45
+#define CLK_TOP_UNIVPLL2_D8		46
+#define CLK_TOP_UNIVPLL2_D16		47
+#define CLK_TOP_UNIVPLL_D5		48
+#define CLK_TOP_UNIVPLL3_D2		49
+#define CLK_TOP_UNIVPLL3_D4		50
+#define CLK_TOP_UNIVPLL3_D16		51
+#define CLK_TOP_UNIVPLL_D7		52
+#define CLK_TOP_UNIVPLL_D80_D4		53
+#define CLK_TOP_UNIV48M			54
+#define CLK_TOP_SGMIIPLL_D2		55
+#define CLK_TOP_CLKXTAL_D4		56
+#define CLK_TOP_HD_FAXI			57
+#define CLK_TOP_FAXI			58
+#define CLK_TOP_F_FAUD_INTBUS		59
+#define CLK_TOP_AP2WBHIF_HCLK		60
+#define CLK_TOP_10M_INFRAO		61
+#define CLK_TOP_MSDC30_1		62
+#define CLK_TOP_SPI			63
+#define CLK_TOP_SF			64
+#define CLK_TOP_FLASH			65
+#define CLK_TOP_TO_USB3_REF		66
+#define CLK_TOP_TO_USB3_MCU		67
+#define CLK_TOP_TO_USB3_DMA		68
+#define CLK_TOP_FROM_TOP_AHB		69
+#define CLK_TOP_FROM_TOP_AXI		70
+#define CLK_TOP_PCIE1_MAC_EN		71
+#define CLK_TOP_PCIE0_MAC_EN		72
+
+#define CLK_TOP_AXI_SEL			73
+#define CLK_TOP_MEM_SEL			74
+#define CLK_TOP_DDRPHYCFG_SEL		75
+#define CLK_TOP_ETH_SEL			76
+#define CLK_TOP_PWM_SEL			77
+#define CLK_TOP_F10M_REF_SEL		78
+#define CLK_TOP_NFI_INFRA_SEL		79
+#define CLK_TOP_FLASH_SEL		80
+#define CLK_TOP_UART_SEL		81
+#define CLK_TOP_SPI0_SEL		82
+#define CLK_TOP_SPI1_SEL		83
+#define CLK_TOP_MSDC50_0_SEL		84
+#define CLK_TOP_MSDC30_0_SEL		85
+#define CLK_TOP_MSDC30_1_SEL		86
+#define CLK_TOP_AP2WBMCU_SEL		87
+#define CLK_TOP_AP2WBHIF_SEL		88
+#define CLK_TOP_AUDIO_SEL		89
+#define CLK_TOP_AUD_INTBUS_SEL		90
+#define CLK_TOP_PMICSPI_SEL		91
+#define CLK_TOP_SCP_SEL			92
+#define CLK_TOP_ATB_SEL			93
+#define CLK_TOP_HIF_SEL			94
+#define CLK_TOP_SATA_SEL		95
+#define CLK_TOP_U2_SEL			96
+#define CLK_TOP_AUD1_SEL		97
+#define CLK_TOP_AUD2_SEL		98
+#define CLK_TOP_IRRX_SEL		99
+#define CLK_TOP_IRTX_SEL		100
+#define CLK_TOP_SATA_MCU_SEL		101
+#define CLK_TOP_PCIE0_MCU_SEL		102
+#define CLK_TOP_PCIE1_MCU_SEL		103
+#define CLK_TOP_SSUSB_MCU_SEL		104
+#define CLK_TOP_CRYPTO_SEL		105
+#define CLK_TOP_SGMII_REF_1_SEL		106
+#define CLK_TOP_10M_SEL			107
+#define CLK_TOP_NR_CLK			108
+
+/* INFRACFG */
+#define CLK_INFRA_MUX1_SEL		0
+#define CLK_INFRA_DBGCLK_PD		1
+#define CLK_INFRA_TRNG_PD		2
+#define CLK_INFRA_DEVAPC_PD		3
+#define CLK_INFRA_APXGPT_PD		4
+#define CLK_INFRA_SEJ_PD		5
+#define CLK_INFRA_NR_CLK		6
+
+/* PERICFG */
+#define CLK_PERIBUS_SEL			0
+#define CLK_PERI_PWM1_PD		1
+#define CLK_PERI_PWM2_PD		2
+#define CLK_PERI_PWM3_PD		3
+#define CLK_PERI_PWM4_PD		4
+#define CLK_PERI_PWM5_PD		5
+#define CLK_PERI_PWM6_PD		6
+#define CLK_PERI_PWM7_PD		7
+#define CLK_PERI_PWM_PD			8
+#define CLK_PERI_AP_DMA_PD		9
+#define CLK_PERI_MSDC30_1_PD		10
+#define CLK_PERI_UART0_PD		11
+#define CLK_PERI_UART1_PD		12
+#define CLK_PERI_UART2_PD		13
+#define CLK_PERI_UART3_PD		14
+#define CLK_PERI_BTIF_PD		15
+#define CLK_PERI_I2C0_PD		16
+#define CLK_PERI_SPI0_PD		17
+#define CLK_PERI_SNFI_PD		18
+#define CLK_PERI_NFI_PD			19
+#define CLK_PERI_NFIECC_PD		20
+#define CLK_PERI_FLASH_PD		21
+#define CLK_PERI_NR_CLK			22
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL		0
+#define CLK_APMIXED_MAINPLL		1
+#define CLK_APMIXED_UNIV2PLL		2
+#define CLK_APMIXED_ETH1PLL		3
+#define CLK_APMIXED_ETH2PLL		4
+#define CLK_APMIXED_SGMIPLL		5
+#define CLK_APMIXED_NR_CLK		6
+
+/* SSUSBSYS */
+#define CLK_SSUSB_U2_PHY_1P_EN		0
+#define CLK_SSUSB_U2_PHY_EN		1
+#define CLK_SSUSB_REF_EN		2
+#define CLK_SSUSB_SYS_EN		3
+#define CLK_SSUSB_MCU_EN		4
+#define CLK_SSUSB_DMA_EN		5
+#define CLK_SSUSB_NR_CLK		6
+
+/* PCIESYS */
+#define CLK_PCIE_P1_AUX_EN		0
+#define CLK_PCIE_P1_OBFF_EN		1
+#define CLK_PCIE_P1_AHB_EN		2
+#define CLK_PCIE_P1_AXI_EN		3
+#define CLK_PCIE_P1_MAC_EN		4
+#define CLK_PCIE_P1_PIPE_EN		5
+#define CLK_PCIE_P0_AUX_EN		6
+#define CLK_PCIE_P0_OBFF_EN		7
+#define CLK_PCIE_P0_AHB_EN		8
+#define CLK_PCIE_P0_AXI_EN		9
+#define CLK_PCIE_P0_MAC_EN		10
+#define CLK_PCIE_P0_PIPE_EN		11
+#define CLK_PCIE_NR_CLK			12
+
+/* ETHSYS */
+#define CLK_ETH_FE_EN			0
+#define CLK_ETH_GP2_EN			1
+#define CLK_ETH_GP1_EN			2
+#define CLK_ETH_GP0_EN			3
+#define CLK_ETH_ESW_EN			4
+#define CLK_ETH_NR_CLK			5
+
+/* SGMIISYS */
+#define CLK_SGMII_TX_EN			0
+#define CLK_SGMII_RX_EN			1
+#define CLK_SGMII_CDR_REF		2
+#define CLK_SGMII_CDR_FB		3
+#define CLK_SGMII_NR_CLK		4
+
+#endif /* _DT_BINDINGS_CLK_MT7629_H */
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
new file mode 100644
index 0000000..745b87f
--- /dev/null
+++ b/include/dt-bindings/clock/mt8516-clk.h
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 BayLibre, SAS
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8516_H
+#define _DT_BINDINGS_CLK_MT8516_H
+
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL	0
+#define CLK_APMIXED_MAINPLL	1
+#define CLK_APMIXED_UNIVPLL	2
+#define CLK_APMIXED_MMPLL	3
+#define CLK_APMIXED_APLL1	4
+#define CLK_APMIXED_APLL2	5
+#define CLK_APMIXED_NR_CLK	6
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL	0
+#define CLK_TOP_I2S_INFRA_BCK	1
+#define CLK_TOP_MEMPLL		2
+#define CLK_TOP_DMPLL		3
+#define CLK_TOP_MAINPLL_D2	4
+#define CLK_TOP_MAINPLL_D4	5
+#define CLK_TOP_MAINPLL_D8	6
+#define CLK_TOP_MAINPLL_D16	7
+#define CLK_TOP_MAINPLL_D11	8
+#define CLK_TOP_MAINPLL_D22	9
+#define CLK_TOP_MAINPLL_D3	10
+#define CLK_TOP_MAINPLL_D6	11
+#define CLK_TOP_MAINPLL_D12	12
+#define CLK_TOP_MAINPLL_D5	13
+#define CLK_TOP_MAINPLL_D10	14
+#define CLK_TOP_MAINPLL_D20	15
+#define CLK_TOP_MAINPLL_D40	16
+#define CLK_TOP_MAINPLL_D7	17
+#define CLK_TOP_MAINPLL_D14	18
+#define CLK_TOP_UNIVPLL_D2	19
+#define CLK_TOP_UNIVPLL_D4	20
+#define CLK_TOP_UNIVPLL_D8	21
+#define CLK_TOP_UNIVPLL_D16	22
+#define CLK_TOP_UNIVPLL_D3	23
+#define CLK_TOP_UNIVPLL_D6	24
+#define CLK_TOP_UNIVPLL_D12	25
+#define CLK_TOP_UNIVPLL_D24	26
+#define CLK_TOP_UNIVPLL_D5	27
+#define CLK_TOP_UNIVPLL_D20	28
+#define CLK_TOP_MMPLL380M	29
+#define CLK_TOP_MMPLL_D2	30
+#define CLK_TOP_MMPLL_200M	31
+#define CLK_TOP_USB_PHY48M	32
+#define CLK_TOP_APLL1		33
+#define CLK_TOP_APLL1_D2	34
+#define CLK_TOP_APLL1_D4	35
+#define CLK_TOP_APLL1_D8	36
+#define CLK_TOP_APLL2		37
+#define CLK_TOP_APLL2_D2	38
+#define CLK_TOP_APLL2_D4	39
+#define CLK_TOP_APLL2_D8	40
+#define CLK_TOP_CLK26M		41
+#define CLK_TOP_CLK26M_D2	42
+#define CLK_TOP_AHB_INFRA_D2	43
+#define CLK_TOP_NFI1X		44
+#define CLK_TOP_ETH_D2		45
+#define CLK_TOP_UART0_SEL	46
+#define CLK_TOP_GFMUX_EMI1X_SEL	47
+#define CLK_TOP_EMI_DDRPHY_SEL	48
+#define CLK_TOP_AHB_INFRA_SEL	49
+#define CLK_TOP_CSW_MUX_MFG_SEL	50
+#define CLK_TOP_MSDC0_SEL	51
+#define CLK_TOP_PWM_MM_SEL	52
+#define CLK_TOP_UART1_SEL	53
+#define CLK_TOP_MSDC1_SEL	54
+#define CLK_TOP_SPM_52M_SEL	55
+#define CLK_TOP_PMICSPI_SEL	56
+#define CLK_TOP_QAXI_AUD26M_SEL	57
+#define CLK_TOP_AUD_INTBUS_SEL	58
+#define CLK_TOP_NFI2X_PAD_SEL	59
+#define CLK_TOP_NFI1X_PAD_SEL	60
+#define CLK_TOP_MFG_MM_SEL	61
+#define CLK_TOP_DDRPHYCFG_SEL	62
+#define CLK_TOP_USB_78M_SEL	63
+#define CLK_TOP_SPINOR_SEL	64
+#define CLK_TOP_MSDC2_SEL	65
+#define CLK_TOP_ETH_SEL		66
+#define CLK_TOP_AXI_MFG_IN_SEL	67
+#define CLK_TOP_SLOW_MFG_SEL	68
+#define CLK_TOP_AUD1_SEL	69
+#define CLK_TOP_AUD2_SEL	70
+#define CLK_TOP_AUD_ENGEN1_SEL	71
+#define CLK_TOP_AUD_ENGEN2_SEL	72
+#define CLK_TOP_I2C_SEL		73
+#define CLK_TOP_AUD_I2S0_M_SEL	74
+#define CLK_TOP_AUD_I2S1_M_SEL	75
+#define CLK_TOP_AUD_I2S2_M_SEL	76
+#define CLK_TOP_AUD_I2S3_M_SEL	77
+#define CLK_TOP_AUD_I2S4_M_SEL	78
+#define CLK_TOP_AUD_I2S5_M_SEL	79
+#define CLK_TOP_AUD_SPDIF_B_SEL	80
+#define CLK_TOP_PWM_SEL		81
+#define CLK_TOP_SPI_SEL		82
+#define CLK_TOP_AUD_SPDIFIN_SEL	83
+#define CLK_TOP_UART2_SEL	84
+#define CLK_TOP_BSI_SEL		85
+#define CLK_TOP_DBG_ATCLK_SEL	86
+#define CLK_TOP_CSW_NFIECC_SEL	87
+#define CLK_TOP_NFIECC_SEL	88
+#define CLK_TOP_APLL12_CK_DIV0	89
+#define CLK_TOP_APLL12_CK_DIV1	90
+#define CLK_TOP_APLL12_CK_DIV2	91
+#define CLK_TOP_APLL12_CK_DIV3	92
+#define CLK_TOP_APLL12_CK_DIV4	93
+#define CLK_TOP_APLL12_CK_DIV4B	94
+#define CLK_TOP_APLL12_CK_DIV5	95
+#define CLK_TOP_APLL12_CK_DIV5B	96
+#define CLK_TOP_APLL12_CK_DIV6	97
+#define CLK_TOP_NR_CLK		98
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_PWM_MM		0
+#define CLK_TOP_MFG_MM		1
+#define CLK_TOP_SPM_52M		2
+#define CLK_TOP_THEM		3
+#define CLK_TOP_APDMA		4
+#define CLK_TOP_I2C0		5
+#define CLK_TOP_I2C1		6
+#define CLK_TOP_AUXADC1		7
+#define CLK_TOP_NFI		8
+#define CLK_TOP_NFIECC		9
+#define CLK_TOP_DEBUGSYS	10
+#define CLK_TOP_PWM		11
+#define CLK_TOP_UART0		12
+#define CLK_TOP_UART1		13
+#define CLK_TOP_BTIF		14
+#define CLK_TOP_USB		15
+#define CLK_TOP_FLASHIF_26M	16
+#define CLK_TOP_AUXADC2		17
+#define CLK_TOP_I2C2		18
+#define CLK_TOP_MSDC0		19
+#define CLK_TOP_MSDC1		20
+#define CLK_TOP_NFI2X		21
+#define CLK_TOP_PMICWRAP_AP	22
+#define CLK_TOP_SEJ		23
+#define CLK_TOP_MEMSLP_DLYER	24
+#define CLK_TOP_SPI		25
+#define CLK_TOP_APXGPT		26
+#define CLK_TOP_AUDIO		27
+#define CLK_TOP_PMICWRAP_MD	28
+#define CLK_TOP_PMICWRAP_CONN	29
+#define CLK_TOP_PMICWRAP_26M	30
+#define CLK_TOP_AUX_ADC		31
+#define CLK_TOP_AUX_TP		32
+#define CLK_TOP_MSDC2		33
+#define CLK_TOP_RBIST		34
+#define CLK_TOP_NFI_BUS		35
+#define CLK_TOP_GCE		36
+#define CLK_TOP_TRNG		37
+#define CLK_TOP_SEJ_13M		38
+#define CLK_TOP_AES		39
+#define CLK_TOP_PWM_B		40
+#define CLK_TOP_PWM1_FB		41
+#define CLK_TOP_PWM2_FB		42
+#define CLK_TOP_PWM3_FB		43
+#define CLK_TOP_PWM4_FB		44
+#define CLK_TOP_PWM5_FB		45
+#define CLK_TOP_USB_1P		46
+#define CLK_TOP_FLASHIF_FREERUN	47
+#define CLK_TOP_66M_ETH		48
+#define CLK_TOP_133M_ETH	49
+#define CLK_TOP_FETH_25M	50
+#define CLK_TOP_FETH_50M	51
+#define CLK_TOP_FLASHIF_AXI	52
+#define CLK_TOP_USBIF		53
+#define CLK_TOP_UART2		54
+#define CLK_TOP_BSI		55
+#define CLK_TOP_MSDC0_INFRA	56
+#define CLK_TOP_MSDC1_INFRA	57
+#define CLK_TOP_MSDC2_INFRA	58
+#define CLK_TOP_USB_78M		59
+#define CLK_TOP_RG_SPINOR	60
+#define CLK_TOP_RG_MSDC2	61
+#define CLK_TOP_RG_ETH		62
+#define CLK_TOP_RG_AXI_MFG	63
+#define CLK_TOP_RG_SLOW_MFG	64
+#define CLK_TOP_RG_AUD1		65
+#define CLK_TOP_RG_AUD2		66
+#define CLK_TOP_RG_AUD_ENGEN1	67
+#define CLK_TOP_RG_AUD_ENGEN2	68
+#define CLK_TOP_RG_I2C		69
+#define CLK_TOP_RG_PWM_INFRA	70
+#define CLK_TOP_RG_AUD_SPDIF_IN	71
+#define CLK_TOP_RG_UART2	72
+#define CLK_TOP_RG_BSI		73
+#define CLK_TOP_RG_DBG_ATCLK	74
+#define CLK_TOP_RG_NFIECC	75
+#define CLK_TOP_RG_APLL1_D2_EN	76
+#define CLK_TOP_RG_APLL1_D4_EN	77
+#define CLK_TOP_RG_APLL1_D8_EN	78
+#define CLK_TOP_RG_APLL2_D2_EN	79
+#define CLK_TOP_RG_APLL2_D4_EN	80
+#define CLK_TOP_RG_APLL2_D8_EN	81
+#define CLK_TOP_APLL12_DIV0	82
+#define CLK_TOP_APLL12_DIV1	83
+#define CLK_TOP_APLL12_DIV2	84
+#define CLK_TOP_APLL12_DIV3	85
+#define CLK_TOP_APLL12_DIV4	86
+#define CLK_TOP_APLL12_DIV4B	87
+#define CLK_TOP_APLL12_DIV5	88
+#define CLK_TOP_APLL12_DIV5B	89
+#define CLK_TOP_APLL12_DIV6	90
+
+/* INFRACFG */
+
+#define CLK_IFR_MUX1_SEL	0
+#define CLK_IFR_ETH_25M_SEL	1
+#define CLK_IFR_I2C0_SEL	2
+#define CLK_IFR_I2C1_SEL	3
+#define CLK_IFR_I2C2_SEL	4
+#define CLK_IFR_NR_CLK		5
+
+/* AUDIOTOP */
+
+#define CLK_AUD_AFE		0
+#define CLK_AUD_I2S		1
+#define CLK_AUD_22M		2
+#define CLK_AUD_24M		3
+#define CLK_AUD_INTDIR		4
+#define CLK_AUD_APLL2_TUNER	5
+#define CLK_AUD_APLL_TUNER	6
+#define CLK_AUD_HDMI		7
+#define CLK_AUD_SPDF		8
+#define CLK_AUD_ADC		9
+#define CLK_AUD_DAC		10
+#define CLK_AUD_DAC_PREDIS	11
+#define CLK_AUD_TML		12
+#define CLK_AUD_NR_CLK		13
+
+/* MFGCFG */
+
+#define CLK_MFG_BAXI		0
+#define CLK_MFG_BMEM		1
+#define CLK_MFG_BG3D		2
+#define CLK_MFG_B26M		3
+#define CLK_MFG_NR_CLK		4
+
+#endif /* _DT_BINDINGS_CLK_MT8516_H */
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
new file mode 100644
index 0000000..a267ac2
--- /dev/null
+++ b/include/dt-bindings/clock/r7s72100-clock.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
+#define __DT_BINDINGS_CLOCK_R7S72100_H__
+
+#define R7S72100_CLK_PLL	0
+#define R7S72100_CLK_I		1
+#define R7S72100_CLK_G		2
+
+/* MSTP2 */
+#define R7S72100_CLK_CORESIGHT	0
+
+/* MSTP3 */
+#define R7S72100_CLK_IEBUS	7
+#define R7S72100_CLK_IRDA	6
+#define R7S72100_CLK_LIN0	5
+#define R7S72100_CLK_LIN1	4
+#define R7S72100_CLK_MTU2	3
+#define R7S72100_CLK_CAN	2
+#define R7S72100_CLK_ADCPWR	1
+#define R7S72100_CLK_PWM	0
+
+/* MSTP4 */
+#define R7S72100_CLK_SCIF0	7
+#define R7S72100_CLK_SCIF1	6
+#define R7S72100_CLK_SCIF2	5
+#define R7S72100_CLK_SCIF3	4
+#define R7S72100_CLK_SCIF4	3
+#define R7S72100_CLK_SCIF5	2
+#define R7S72100_CLK_SCIF6	1
+#define R7S72100_CLK_SCIF7	0
+
+/* MSTP5 */
+#define R7S72100_CLK_SCI0	7
+#define R7S72100_CLK_SCI1	6
+#define R7S72100_CLK_SG0	5
+#define R7S72100_CLK_SG1	4
+#define R7S72100_CLK_SG2	3
+#define R7S72100_CLK_SG3	2
+#define R7S72100_CLK_OSTM0	1
+#define R7S72100_CLK_OSTM1	0
+
+/* MSTP6 */
+#define R7S72100_CLK_ADC	7
+#define R7S72100_CLK_CEU	6
+#define R7S72100_CLK_DOC0	5
+#define R7S72100_CLK_DOC1	4
+#define R7S72100_CLK_DRC0	3
+#define R7S72100_CLK_DRC1	2
+#define R7S72100_CLK_JCU	1
+#define R7S72100_CLK_RTC	0
+
+/* MSTP7 */
+#define R7S72100_CLK_VDEC0	7
+#define R7S72100_CLK_VDEC1	6
+#define R7S72100_CLK_ETHER	4
+#define R7S72100_CLK_NAND	3
+#define R7S72100_CLK_USB0	1
+#define R7S72100_CLK_USB1	0
+
+/* MSTP8 */
+#define R7S72100_CLK_IMR0	7
+#define R7S72100_CLK_IMR1	6
+#define R7S72100_CLK_IMRDISP	5
+#define R7S72100_CLK_MMCIF	4
+#define R7S72100_CLK_MLB	3
+#define R7S72100_CLK_ETHAVB	2
+#define R7S72100_CLK_SCUX	1
+
+/* MSTP9 */
+#define R7S72100_CLK_I2C0	7
+#define R7S72100_CLK_I2C1	6
+#define R7S72100_CLK_I2C2	5
+#define R7S72100_CLK_I2C3	4
+#define R7S72100_CLK_SPIBSC0	3
+#define R7S72100_CLK_SPIBSC1	2
+#define R7S72100_CLK_VDC50	1	/* and LVDS */
+#define R7S72100_CLK_VDC51	0
+
+/* MSTP10 */
+#define R7S72100_CLK_SPI0	7
+#define R7S72100_CLK_SPI1	6
+#define R7S72100_CLK_SPI2	5
+#define R7S72100_CLK_SPI3	4
+#define R7S72100_CLK_SPI4	3
+#define R7S72100_CLK_CDROM	2
+#define R7S72100_CLK_SPDIF	1
+#define R7S72100_CLK_RGPVG2	0
+
+/* MSTP11 */
+#define R7S72100_CLK_SSI0	5
+#define R7S72100_CLK_SSI1	4
+#define R7S72100_CLK_SSI2	3
+#define R7S72100_CLK_SSI3	2
+#define R7S72100_CLK_SSI4	1
+#define R7S72100_CLK_SSI5	0
+
+/* MSTP12 */
+#define R7S72100_CLK_SDHI00	3
+#define R7S72100_CLK_SDHI01	2
+#define R7S72100_CLK_SDHI10	1
+#define R7S72100_CLK_SDHI11	0
+
+/* MSTP13 */
+#define R7S72100_CLK_PIX1	2
+#define R7S72100_CLK_PIX0	1
+
+#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
new file mode 100644
index 0000000..20641fa
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_H__
+
+/* CPG */
+#define R8A7790_CLK_MAIN		0
+#define R8A7790_CLK_PLL0		1
+#define R8A7790_CLK_PLL1		2
+#define R8A7790_CLK_PLL3		3
+#define R8A7790_CLK_LB			4
+#define R8A7790_CLK_QSPI		5
+#define R8A7790_CLK_SDH			6
+#define R8A7790_CLK_SD0			7
+#define R8A7790_CLK_SD1			8
+#define R8A7790_CLK_Z			9
+#define R8A7790_CLK_RCAN		10
+#define R8A7790_CLK_ADSP		11
+
+/* MSTP0 */
+#define R8A7790_CLK_MSIOF0		0
+
+/* MSTP1 */
+#define R8A7790_CLK_VCP1		0
+#define R8A7790_CLK_VCP0		1
+#define R8A7790_CLK_VPC1		2
+#define R8A7790_CLK_VPC0		3
+#define R8A7790_CLK_JPU			6
+#define R8A7790_CLK_SSP1		9
+#define R8A7790_CLK_TMU1		11
+#define R8A7790_CLK_3DG			12
+#define R8A7790_CLK_2DDMAC		15
+#define R8A7790_CLK_FDP1_2		17
+#define R8A7790_CLK_FDP1_1		18
+#define R8A7790_CLK_FDP1_0		19
+#define R8A7790_CLK_TMU3		21
+#define R8A7790_CLK_TMU2		22
+#define R8A7790_CLK_CMT0		24
+#define R8A7790_CLK_TMU0		25
+#define R8A7790_CLK_VSP1_DU1		27
+#define R8A7790_CLK_VSP1_DU0		28
+#define R8A7790_CLK_VSP1_R		30
+#define R8A7790_CLK_VSP1_S		31
+
+/* MSTP2 */
+#define R8A7790_CLK_SCIFA2		2
+#define R8A7790_CLK_SCIFA1		3
+#define R8A7790_CLK_SCIFA0		4
+#define R8A7790_CLK_MSIOF2		5
+#define R8A7790_CLK_SCIFB0		6
+#define R8A7790_CLK_SCIFB1		7
+#define R8A7790_CLK_MSIOF1		8
+#define R8A7790_CLK_MSIOF3		15
+#define R8A7790_CLK_SCIFB2		16
+#define R8A7790_CLK_SYS_DMAC1		18
+#define R8A7790_CLK_SYS_DMAC0		19
+
+/* MSTP3 */
+#define R8A7790_CLK_IIC2		0
+#define R8A7790_CLK_TPU0		4
+#define R8A7790_CLK_MMCIF1		5
+#define R8A7790_CLK_SCIF2		10
+#define R8A7790_CLK_SDHI3		11
+#define R8A7790_CLK_SDHI2		12
+#define R8A7790_CLK_SDHI1		13
+#define R8A7790_CLK_SDHI0		14
+#define R8A7790_CLK_MMCIF0		15
+#define R8A7790_CLK_IIC0		18
+#define R8A7790_CLK_PCIEC		19
+#define R8A7790_CLK_IIC1		23
+#define R8A7790_CLK_SSUSB		28
+#define R8A7790_CLK_CMT1		29
+#define R8A7790_CLK_USBDMAC0		30
+#define R8A7790_CLK_USBDMAC1		31
+
+/* MSTP4 */
+#define R8A7790_CLK_IRQC		7
+#define R8A7790_CLK_INTC_SYS		8
+
+/* MSTP5 */
+#define R8A7790_CLK_AUDIO_DMAC1		1
+#define R8A7790_CLK_AUDIO_DMAC0		2
+#define R8A7790_CLK_ADSP_MOD		6
+#define R8A7790_CLK_THERMAL		22
+#define R8A7790_CLK_PWM			23
+
+/* MSTP7 */
+#define R8A7790_CLK_EHCI		3
+#define R8A7790_CLK_HSUSB		4
+#define R8A7790_CLK_HSCIF1		16
+#define R8A7790_CLK_HSCIF0		17
+#define R8A7790_CLK_SCIF1		20
+#define R8A7790_CLK_SCIF0		21
+#define R8A7790_CLK_DU2			22
+#define R8A7790_CLK_DU1			23
+#define R8A7790_CLK_DU0			24
+#define R8A7790_CLK_LVDS1		25
+#define R8A7790_CLK_LVDS0		26
+
+/* MSTP8 */
+#define R8A7790_CLK_MLB			2
+#define R8A7790_CLK_VIN3		8
+#define R8A7790_CLK_VIN2		9
+#define R8A7790_CLK_VIN1		10
+#define R8A7790_CLK_VIN0		11
+#define R8A7790_CLK_ETHERAVB		12
+#define R8A7790_CLK_ETHER		13
+#define R8A7790_CLK_SATA1		14
+#define R8A7790_CLK_SATA0		15
+
+/* MSTP9 */
+#define R8A7790_CLK_GPIO5		7
+#define R8A7790_CLK_GPIO4		8
+#define R8A7790_CLK_GPIO3		9
+#define R8A7790_CLK_GPIO2		10
+#define R8A7790_CLK_GPIO1		11
+#define R8A7790_CLK_GPIO0		12
+#define R8A7790_CLK_RCAN1		15
+#define R8A7790_CLK_RCAN0		16
+#define R8A7790_CLK_QSPI_MOD		17
+#define R8A7790_CLK_IICDVFS		26
+#define R8A7790_CLK_I2C3		28
+#define R8A7790_CLK_I2C2		29
+#define R8A7790_CLK_I2C1		30
+#define R8A7790_CLK_I2C0		31
+
+/* MSTP10 */
+#define R8A7790_CLK_SSI_ALL		5
+#define R8A7790_CLK_SSI9		6
+#define R8A7790_CLK_SSI8		7
+#define R8A7790_CLK_SSI7		8
+#define R8A7790_CLK_SSI6		9
+#define R8A7790_CLK_SSI5		10
+#define R8A7790_CLK_SSI4		11
+#define R8A7790_CLK_SSI3		12
+#define R8A7790_CLK_SSI2		13
+#define R8A7790_CLK_SSI1		14
+#define R8A7790_CLK_SSI0		15
+#define R8A7790_CLK_SCU_ALL		17
+#define R8A7790_CLK_SCU_DVC1		18
+#define R8A7790_CLK_SCU_DVC0		19
+#define R8A7790_CLK_SCU_CTU1_MIX1	20
+#define R8A7790_CLK_SCU_CTU0_MIX0	21
+#define R8A7790_CLK_SCU_SRC9		22
+#define R8A7790_CLK_SCU_SRC8		23
+#define R8A7790_CLK_SCU_SRC7		24
+#define R8A7790_CLK_SCU_SRC6		25
+#define R8A7790_CLK_SCU_SRC5		26
+#define R8A7790_CLK_SCU_SRC4		27
+#define R8A7790_CLK_SCU_SRC3		28
+#define R8A7790_CLK_SCU_SRC2		29
+#define R8A7790_CLK_SCU_SRC1		30
+#define R8A7790_CLK_SCU_SRC0		31
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
new file mode 100644
index 0000000..c5955b5
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7790 CPG Core Clocks */
+#define R8A7790_CLK_Z			0
+#define R8A7790_CLK_Z2			1
+#define R8A7790_CLK_ZG			2
+#define R8A7790_CLK_ZTR			3
+#define R8A7790_CLK_ZTRD2		4
+#define R8A7790_CLK_ZT			5
+#define R8A7790_CLK_ZX			6
+#define R8A7790_CLK_ZS			7
+#define R8A7790_CLK_HP			8
+#define R8A7790_CLK_I			9
+#define R8A7790_CLK_B			10
+#define R8A7790_CLK_LB			11
+#define R8A7790_CLK_P			12
+#define R8A7790_CLK_CL			13
+#define R8A7790_CLK_M2			14
+#define R8A7790_CLK_ADSP		15
+#define R8A7790_CLK_IMP			16
+#define R8A7790_CLK_ZB3			17
+#define R8A7790_CLK_ZB3D2		18
+#define R8A7790_CLK_DDR			19
+#define R8A7790_CLK_SDH			20
+#define R8A7790_CLK_SD0			21
+#define R8A7790_CLK_SD1			22
+#define R8A7790_CLK_SD2			23
+#define R8A7790_CLK_SD3			24
+#define R8A7790_CLK_MMC0		25
+#define R8A7790_CLK_MMC1		26
+#define R8A7790_CLK_MP			27
+#define R8A7790_CLK_SSP			28
+#define R8A7790_CLK_SSPRS		29
+#define R8A7790_CLK_QSPI		30
+#define R8A7790_CLK_CP			31
+#define R8A7790_CLK_RCAN		32
+#define R8A7790_CLK_R			33
+#define R8A7790_CLK_OSC			34
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
new file mode 100644
index 0000000..ef69213
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
+#define __DT_BINDINGS_CLOCK_R8A7791_H__
+
+/* CPG */
+#define R8A7791_CLK_MAIN		0
+#define R8A7791_CLK_PLL0		1
+#define R8A7791_CLK_PLL1		2
+#define R8A7791_CLK_PLL3		3
+#define R8A7791_CLK_LB			4
+#define R8A7791_CLK_QSPI		5
+#define R8A7791_CLK_SDH			6
+#define R8A7791_CLK_SD0			7
+#define R8A7791_CLK_Z			8
+#define R8A7791_CLK_RCAN		9
+#define R8A7791_CLK_ADSP		10
+
+/* MSTP0 */
+#define R8A7791_CLK_MSIOF0		0
+
+/* MSTP1 */
+#define R8A7791_CLK_VCP0		1
+#define R8A7791_CLK_VPC0		3
+#define R8A7791_CLK_JPU			6
+#define R8A7791_CLK_SSP1		9
+#define R8A7791_CLK_TMU1		11
+#define R8A7791_CLK_3DG			12
+#define R8A7791_CLK_2DDMAC		15
+#define R8A7791_CLK_FDP1_1		18
+#define R8A7791_CLK_FDP1_0		19
+#define R8A7791_CLK_TMU3		21
+#define R8A7791_CLK_TMU2		22
+#define R8A7791_CLK_CMT0		24
+#define R8A7791_CLK_TMU0		25
+#define R8A7791_CLK_VSP1_DU1		27
+#define R8A7791_CLK_VSP1_DU0		28
+#define R8A7791_CLK_VSP1_S		31
+
+/* MSTP2 */
+#define R8A7791_CLK_SCIFA2		2
+#define R8A7791_CLK_SCIFA1		3
+#define R8A7791_CLK_SCIFA0		4
+#define R8A7791_CLK_MSIOF2		5
+#define R8A7791_CLK_SCIFB0		6
+#define R8A7791_CLK_SCIFB1		7
+#define R8A7791_CLK_MSIOF1		8
+#define R8A7791_CLK_SCIFB2		16
+#define R8A7791_CLK_SYS_DMAC1		18
+#define R8A7791_CLK_SYS_DMAC0		19
+
+/* MSTP3 */
+#define R8A7791_CLK_TPU0		4
+#define R8A7791_CLK_SDHI2		11
+#define R8A7791_CLK_SDHI1		12
+#define R8A7791_CLK_SDHI0		14
+#define R8A7791_CLK_MMCIF0		15
+#define R8A7791_CLK_IIC0		18
+#define R8A7791_CLK_PCIEC		19
+#define R8A7791_CLK_IIC1		23
+#define R8A7791_CLK_SSUSB		28
+#define R8A7791_CLK_CMT1		29
+#define R8A7791_CLK_USBDMAC0		30
+#define R8A7791_CLK_USBDMAC1		31
+
+/* MSTP4 */
+#define R8A7791_CLK_IRQC		7
+#define R8A7791_CLK_INTC_SYS		8
+
+/* MSTP5 */
+#define R8A7791_CLK_AUDIO_DMAC1		1
+#define R8A7791_CLK_AUDIO_DMAC0		2
+#define R8A7791_CLK_ADSP_MOD		6
+#define R8A7791_CLK_THERMAL		22
+#define R8A7791_CLK_PWM			23
+
+/* MSTP7 */
+#define R8A7791_CLK_EHCI		3
+#define R8A7791_CLK_HSUSB		4
+#define R8A7791_CLK_HSCIF2		13
+#define R8A7791_CLK_SCIF5		14
+#define R8A7791_CLK_SCIF4		15
+#define R8A7791_CLK_HSCIF1		16
+#define R8A7791_CLK_HSCIF0		17
+#define R8A7791_CLK_SCIF3		18
+#define R8A7791_CLK_SCIF2		19
+#define R8A7791_CLK_SCIF1		20
+#define R8A7791_CLK_SCIF0		21
+#define R8A7791_CLK_DU1			23
+#define R8A7791_CLK_DU0			24
+#define R8A7791_CLK_LVDS0		26
+
+/* MSTP8 */
+#define R8A7791_CLK_IPMMU_SGX		0
+#define R8A7791_CLK_MLB			2
+#define R8A7791_CLK_VIN2		9
+#define R8A7791_CLK_VIN1		10
+#define R8A7791_CLK_VIN0		11
+#define R8A7791_CLK_ETHERAVB		12
+#define R8A7791_CLK_ETHER		13
+#define R8A7791_CLK_SATA1		14
+#define R8A7791_CLK_SATA0		15
+
+/* MSTP9 */
+#define R8A7791_CLK_GYROADC		1
+#define R8A7791_CLK_GPIO7		4
+#define R8A7791_CLK_GPIO6		5
+#define R8A7791_CLK_GPIO5		7
+#define R8A7791_CLK_GPIO4		8
+#define R8A7791_CLK_GPIO3		9
+#define R8A7791_CLK_GPIO2		10
+#define R8A7791_CLK_GPIO1		11
+#define R8A7791_CLK_GPIO0		12
+#define R8A7791_CLK_RCAN1		15
+#define R8A7791_CLK_RCAN0		16
+#define R8A7791_CLK_QSPI_MOD		17
+#define R8A7791_CLK_I2C5		25
+#define R8A7791_CLK_IICDVFS		26
+#define R8A7791_CLK_I2C4		27
+#define R8A7791_CLK_I2C3		28
+#define R8A7791_CLK_I2C2		29
+#define R8A7791_CLK_I2C1		30
+#define R8A7791_CLK_I2C0		31
+
+/* MSTP10 */
+#define R8A7791_CLK_SSI_ALL		5
+#define R8A7791_CLK_SSI9		6
+#define R8A7791_CLK_SSI8		7
+#define R8A7791_CLK_SSI7		8
+#define R8A7791_CLK_SSI6		9
+#define R8A7791_CLK_SSI5		10
+#define R8A7791_CLK_SSI4		11
+#define R8A7791_CLK_SSI3		12
+#define R8A7791_CLK_SSI2		13
+#define R8A7791_CLK_SSI1		14
+#define R8A7791_CLK_SSI0		15
+#define R8A7791_CLK_SCU_ALL		17
+#define R8A7791_CLK_SCU_DVC1		18
+#define R8A7791_CLK_SCU_DVC0		19
+#define R8A7791_CLK_SCU_CTU1_MIX1	20
+#define R8A7791_CLK_SCU_CTU0_MIX0	21
+#define R8A7791_CLK_SCU_SRC9		22
+#define R8A7791_CLK_SCU_SRC8		23
+#define R8A7791_CLK_SCU_SRC7		24
+#define R8A7791_CLK_SCU_SRC6		25
+#define R8A7791_CLK_SCU_SRC5		26
+#define R8A7791_CLK_SCU_SRC4		27
+#define R8A7791_CLK_SCU_SRC3		28
+#define R8A7791_CLK_SCU_SRC2		29
+#define R8A7791_CLK_SCU_SRC1		30
+#define R8A7791_CLK_SCU_SRC0		31
+
+/* MSTP11 */
+#define R8A7791_CLK_SCIFA3		6
+#define R8A7791_CLK_SCIFA4		7
+#define R8A7791_CLK_SCIFA5		8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
new file mode 100644
index 0000000..aadd06c
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7791-cpg-mssr.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7791 CPG Core Clocks */
+#define R8A7791_CLK_Z			0
+#define R8A7791_CLK_ZG			1
+#define R8A7791_CLK_ZTR			2
+#define R8A7791_CLK_ZTRD2		3
+#define R8A7791_CLK_ZT			4
+#define R8A7791_CLK_ZX			5
+#define R8A7791_CLK_ZS			6
+#define R8A7791_CLK_HP			7
+#define R8A7791_CLK_I			8
+#define R8A7791_CLK_B			9
+#define R8A7791_CLK_LB			10
+#define R8A7791_CLK_P			11
+#define R8A7791_CLK_CL			12
+#define R8A7791_CLK_M2			13
+#define R8A7791_CLK_ADSP		14
+#define R8A7791_CLK_ZB3			15
+#define R8A7791_CLK_ZB3D2		16
+#define R8A7791_CLK_DDR			17
+#define R8A7791_CLK_SDH			18
+#define R8A7791_CLK_SD0			19
+#define R8A7791_CLK_SD2			20
+#define R8A7791_CLK_SD3			21
+#define R8A7791_CLK_MMC0		22
+#define R8A7791_CLK_MP			23
+#define R8A7791_CLK_SSP			24
+#define R8A7791_CLK_SSPRS		25
+#define R8A7791_CLK_QSPI		26
+#define R8A7791_CLK_CP			27
+#define R8A7791_CLK_RCAN		28
+#define R8A7791_CLK_R			29
+#define R8A7791_CLK_OSC			30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h
new file mode 100644
index 0000000..5be90bc
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7792-clock.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
+#define __DT_BINDINGS_CLOCK_R8A7792_H__
+
+/* CPG */
+#define R8A7792_CLK_MAIN		0
+#define R8A7792_CLK_PLL0		1
+#define R8A7792_CLK_PLL1		2
+#define R8A7792_CLK_PLL3		3
+#define R8A7792_CLK_LB			4
+#define R8A7792_CLK_QSPI		5
+
+/* MSTP0 */
+#define R8A7792_CLK_MSIOF0		0
+
+/* MSTP1 */
+#define R8A7792_CLK_JPU			6
+#define R8A7792_CLK_TMU1		11
+#define R8A7792_CLK_TMU3		21
+#define R8A7792_CLK_TMU2		22
+#define R8A7792_CLK_CMT0		24
+#define R8A7792_CLK_TMU0		25
+#define R8A7792_CLK_VSP1DU1		27
+#define R8A7792_CLK_VSP1DU0		28
+#define R8A7792_CLK_VSP1_SY		31
+
+/* MSTP2 */
+#define R8A7792_CLK_MSIOF1		8
+#define R8A7792_CLK_SYS_DMAC1		18
+#define R8A7792_CLK_SYS_DMAC0		19
+
+/* MSTP3 */
+#define R8A7792_CLK_TPU0		4
+#define R8A7792_CLK_SDHI0		14
+#define R8A7792_CLK_CMT1		29
+
+/* MSTP4 */
+#define R8A7792_CLK_IRQC		7
+#define R8A7792_CLK_INTC_SYS		8
+
+/* MSTP5 */
+#define R8A7792_CLK_AUDIO_DMAC0		2
+#define R8A7792_CLK_THERMAL		22
+#define R8A7792_CLK_PWM			23
+
+/* MSTP7 */
+#define R8A7792_CLK_HSCIF1		16
+#define R8A7792_CLK_HSCIF0		17
+#define R8A7792_CLK_SCIF3		18
+#define R8A7792_CLK_SCIF2		19
+#define R8A7792_CLK_SCIF1		20
+#define R8A7792_CLK_SCIF0		21
+#define R8A7792_CLK_DU1			23
+#define R8A7792_CLK_DU0			24
+
+/* MSTP8 */
+#define R8A7792_CLK_VIN5		4
+#define R8A7792_CLK_VIN4		5
+#define R8A7792_CLK_VIN3		8
+#define R8A7792_CLK_VIN2		9
+#define R8A7792_CLK_VIN1		10
+#define R8A7792_CLK_VIN0		11
+#define R8A7792_CLK_ETHERAVB		12
+
+/* MSTP9 */
+#define R8A7792_CLK_GPIO7		4
+#define R8A7792_CLK_GPIO6		5
+#define R8A7792_CLK_GPIO5		7
+#define R8A7792_CLK_GPIO4		8
+#define R8A7792_CLK_GPIO3		9
+#define R8A7792_CLK_GPIO2		10
+#define R8A7792_CLK_GPIO1		11
+#define R8A7792_CLK_GPIO0		12
+#define R8A7792_CLK_GPIO11		13
+#define R8A7792_CLK_GPIO10		14
+#define R8A7792_CLK_CAN1		15
+#define R8A7792_CLK_CAN0		16
+#define R8A7792_CLK_QSPI_MOD		17
+#define R8A7792_CLK_GPIO9		19
+#define R8A7792_CLK_GPIO8		21
+#define R8A7792_CLK_I2C5		25
+#define R8A7792_CLK_IICDVFS		26
+#define R8A7792_CLK_I2C4		27
+#define R8A7792_CLK_I2C3		28
+#define R8A7792_CLK_I2C2		29
+#define R8A7792_CLK_I2C1		30
+#define R8A7792_CLK_I2C0		31
+
+/* MSTP10 */
+#define R8A7792_CLK_SSI_ALL		5
+#define R8A7792_CLK_SSI4		11
+#define R8A7792_CLK_SSI3		12
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
diff --git a/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
new file mode 100644
index 0000000..829c44d
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7792-cpg-mssr.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7792 CPG Core Clocks */
+#define R8A7792_CLK_Z			0
+#define R8A7792_CLK_ZG			1
+#define R8A7792_CLK_ZTR			2
+#define R8A7792_CLK_ZTRD2		3
+#define R8A7792_CLK_ZT			4
+#define R8A7792_CLK_ZX			5
+#define R8A7792_CLK_ZS			6
+#define R8A7792_CLK_HP			7
+#define R8A7792_CLK_I			8
+#define R8A7792_CLK_B			9
+#define R8A7792_CLK_LB			10
+#define R8A7792_CLK_P			11
+#define R8A7792_CLK_CL			12
+#define R8A7792_CLK_M2			13
+#define R8A7792_CLK_IMP			14
+#define R8A7792_CLK_ZB3			15
+#define R8A7792_CLK_ZB3D2		16
+#define R8A7792_CLK_DDR			17
+#define R8A7792_CLK_SD			18
+#define R8A7792_CLK_MP			19
+#define R8A7792_CLK_QSPI		20
+#define R8A7792_CLK_CP			21
+#define R8A7792_CLK_CPEX		22
+#define R8A7792_CLK_RCAN		23
+#define R8A7792_CLK_R			24
+#define R8A7792_CLK_OSC			25
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h
new file mode 100644
index 0000000..49c66d8
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7793-clock.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * r8a7793 clock definition
+ *
+ * Copyright (C) 2014  Renesas Electronics Corporation
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
+#define __DT_BINDINGS_CLOCK_R8A7793_H__
+
+/* CPG */
+#define R8A7793_CLK_MAIN		0
+#define R8A7793_CLK_PLL0		1
+#define R8A7793_CLK_PLL1		2
+#define R8A7793_CLK_PLL3		3
+#define R8A7793_CLK_LB			4
+#define R8A7793_CLK_QSPI		5
+#define R8A7793_CLK_SDH			6
+#define R8A7793_CLK_SD0			7
+#define R8A7793_CLK_Z			8
+#define R8A7793_CLK_RCAN		9
+#define R8A7793_CLK_ADSP		10
+
+/* MSTP0 */
+#define R8A7793_CLK_MSIOF0		0
+
+/* MSTP1 */
+#define R8A7793_CLK_VCP0		1
+#define R8A7793_CLK_VPC0		3
+#define R8A7793_CLK_SSP1		9
+#define R8A7793_CLK_TMU1		11
+#define R8A7793_CLK_3DG			12
+#define R8A7793_CLK_2DDMAC		15
+#define R8A7793_CLK_FDP1_1		18
+#define R8A7793_CLK_FDP1_0		19
+#define R8A7793_CLK_TMU3		21
+#define R8A7793_CLK_TMU2		22
+#define R8A7793_CLK_CMT0		24
+#define R8A7793_CLK_TMU0		25
+#define R8A7793_CLK_VSP1_DU1		27
+#define R8A7793_CLK_VSP1_DU0		28
+#define R8A7793_CLK_VSP1_S		31
+
+/* MSTP2 */
+#define R8A7793_CLK_SCIFA2		2
+#define R8A7793_CLK_SCIFA1		3
+#define R8A7793_CLK_SCIFA0		4
+#define R8A7793_CLK_MSIOF2		5
+#define R8A7793_CLK_SCIFB0		6
+#define R8A7793_CLK_SCIFB1		7
+#define R8A7793_CLK_MSIOF1		8
+#define R8A7793_CLK_SCIFB2		16
+#define R8A7793_CLK_SYS_DMAC1		18
+#define R8A7793_CLK_SYS_DMAC0		19
+
+/* MSTP3 */
+#define R8A7793_CLK_TPU0		4
+#define R8A7793_CLK_SDHI2		11
+#define R8A7793_CLK_SDHI1		12
+#define R8A7793_CLK_SDHI0		14
+#define R8A7793_CLK_MMCIF0		15
+#define R8A7793_CLK_IIC0		18
+#define R8A7793_CLK_PCIEC		19
+#define R8A7793_CLK_IIC1		23
+#define R8A7793_CLK_SSUSB		28
+#define R8A7793_CLK_CMT1		29
+#define R8A7793_CLK_USBDMAC0		30
+#define R8A7793_CLK_USBDMAC1		31
+
+/* MSTP4 */
+#define R8A7793_CLK_IRQC		7
+#define R8A7793_CLK_INTC_SYS		8
+
+/* MSTP5 */
+#define R8A7793_CLK_AUDIO_DMAC1		1
+#define R8A7793_CLK_AUDIO_DMAC0		2
+#define R8A7793_CLK_ADSP_MOD		6
+#define R8A7793_CLK_THERMAL		22
+#define R8A7793_CLK_PWM			23
+
+/* MSTP7 */
+#define R8A7793_CLK_EHCI		3
+#define R8A7793_CLK_HSUSB		4
+#define R8A7793_CLK_HSCIF2		13
+#define R8A7793_CLK_SCIF5		14
+#define R8A7793_CLK_SCIF4		15
+#define R8A7793_CLK_HSCIF1		16
+#define R8A7793_CLK_HSCIF0		17
+#define R8A7793_CLK_SCIF3		18
+#define R8A7793_CLK_SCIF2		19
+#define R8A7793_CLK_SCIF1		20
+#define R8A7793_CLK_SCIF0		21
+#define R8A7793_CLK_DU1			23
+#define R8A7793_CLK_DU0			24
+#define R8A7793_CLK_LVDS0		26
+
+/* MSTP8 */
+#define R8A7793_CLK_IPMMU_SGX		0
+#define R8A7793_CLK_VIN2		9
+#define R8A7793_CLK_VIN1		10
+#define R8A7793_CLK_VIN0		11
+#define R8A7793_CLK_ETHER		13
+#define R8A7793_CLK_SATA1		14
+#define R8A7793_CLK_SATA0		15
+
+/* MSTP9 */
+#define R8A7793_CLK_GPIO7		4
+#define R8A7793_CLK_GPIO6		5
+#define R8A7793_CLK_GPIO5		7
+#define R8A7793_CLK_GPIO4		8
+#define R8A7793_CLK_GPIO3		9
+#define R8A7793_CLK_GPIO2		10
+#define R8A7793_CLK_GPIO1		11
+#define R8A7793_CLK_GPIO0		12
+#define R8A7793_CLK_RCAN1		15
+#define R8A7793_CLK_RCAN0		16
+#define R8A7793_CLK_QSPI_MOD		17
+#define R8A7793_CLK_I2C5		25
+#define R8A7793_CLK_IICDVFS		26
+#define R8A7793_CLK_I2C4		27
+#define R8A7793_CLK_I2C3		28
+#define R8A7793_CLK_I2C2		29
+#define R8A7793_CLK_I2C1		30
+#define R8A7793_CLK_I2C0		31
+
+/* MSTP10 */
+#define R8A7793_CLK_SSI_ALL		5
+#define R8A7793_CLK_SSI9		6
+#define R8A7793_CLK_SSI8		7
+#define R8A7793_CLK_SSI7		8
+#define R8A7793_CLK_SSI6		9
+#define R8A7793_CLK_SSI5		10
+#define R8A7793_CLK_SSI4		11
+#define R8A7793_CLK_SSI3		12
+#define R8A7793_CLK_SSI2		13
+#define R8A7793_CLK_SSI1		14
+#define R8A7793_CLK_SSI0		15
+#define R8A7793_CLK_SCU_ALL		17
+#define R8A7793_CLK_SCU_DVC1		18
+#define R8A7793_CLK_SCU_DVC0		19
+#define R8A7793_CLK_SCU_CTU1_MIX1	20
+#define R8A7793_CLK_SCU_CTU0_MIX0	21
+#define R8A7793_CLK_SCU_SRC9		22
+#define R8A7793_CLK_SCU_SRC8		23
+#define R8A7793_CLK_SCU_SRC7		24
+#define R8A7793_CLK_SCU_SRC6		25
+#define R8A7793_CLK_SCU_SRC5		26
+#define R8A7793_CLK_SCU_SRC4		27
+#define R8A7793_CLK_SCU_SRC3		28
+#define R8A7793_CLK_SCU_SRC2		29
+#define R8A7793_CLK_SCU_SRC1		30
+#define R8A7793_CLK_SCU_SRC0		31
+
+/* MSTP11 */
+#define R8A7793_CLK_SCIFA3		6
+#define R8A7793_CLK_SCIFA4		7
+#define R8A7793_CLK_SCIFA5		8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */
diff --git a/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
new file mode 100644
index 0000000..d1ff646
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7793-cpg-mssr.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7793 CPG Core Clocks */
+#define R8A7793_CLK_Z			0
+#define R8A7793_CLK_ZG			1
+#define R8A7793_CLK_ZTR			2
+#define R8A7793_CLK_ZTRD2		3
+#define R8A7793_CLK_ZT			4
+#define R8A7793_CLK_ZX			5
+#define R8A7793_CLK_ZS			6
+#define R8A7793_CLK_HP			7
+#define R8A7793_CLK_I			8
+#define R8A7793_CLK_B			9
+#define R8A7793_CLK_LB			10
+#define R8A7793_CLK_P			11
+#define R8A7793_CLK_CL			12
+#define R8A7793_CLK_M2			13
+#define R8A7793_CLK_ADSP		14
+#define R8A7793_CLK_ZB3			15
+#define R8A7793_CLK_ZB3D2		16
+#define R8A7793_CLK_DDR			17
+#define R8A7793_CLK_SDH			18
+#define R8A7793_CLK_SD0			19
+#define R8A7793_CLK_SD2			20
+#define R8A7793_CLK_SD3			21
+#define R8A7793_CLK_MMC0		22
+#define R8A7793_CLK_MP			23
+#define R8A7793_CLK_SSP			24
+#define R8A7793_CLK_SSPRS		25
+#define R8A7793_CLK_QSPI		26
+#define R8A7793_CLK_CP			27
+#define R8A7793_CLK_RCAN		28
+#define R8A7793_CLK_R			29
+#define R8A7793_CLK_OSC			30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
new file mode 100644
index 0000000..649f005
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright 2013 Ideas On Board SPRL
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_H__
+
+/* CPG */
+#define R8A7794_CLK_MAIN		0
+#define R8A7794_CLK_PLL0		1
+#define R8A7794_CLK_PLL1		2
+#define R8A7794_CLK_PLL3		3
+#define R8A7794_CLK_LB			4
+#define R8A7794_CLK_QSPI		5
+#define R8A7794_CLK_SDH			6
+#define R8A7794_CLK_SD0			7
+#define R8A7794_CLK_RCAN		8
+
+/* MSTP0 */
+#define R8A7794_CLK_MSIOF0		0
+
+/* MSTP1 */
+#define R8A7794_CLK_VCP0		1
+#define R8A7794_CLK_VPC0		3
+#define R8A7794_CLK_TMU1		11
+#define R8A7794_CLK_3DG			12
+#define R8A7794_CLK_2DDMAC		15
+#define R8A7794_CLK_FDP1_0		19
+#define R8A7794_CLK_TMU3		21
+#define R8A7794_CLK_TMU2		22
+#define R8A7794_CLK_CMT0		24
+#define R8A7794_CLK_TMU0		25
+#define R8A7794_CLK_VSP1_DU0		28
+#define R8A7794_CLK_VSP1_S		31
+
+/* MSTP2 */
+#define R8A7794_CLK_SCIFA2		2
+#define R8A7794_CLK_SCIFA1		3
+#define R8A7794_CLK_SCIFA0		4
+#define R8A7794_CLK_MSIOF2		5
+#define R8A7794_CLK_SCIFB0		6
+#define R8A7794_CLK_SCIFB1		7
+#define R8A7794_CLK_MSIOF1		8
+#define R8A7794_CLK_SCIFB2		16
+#define R8A7794_CLK_SYS_DMAC1		18
+#define R8A7794_CLK_SYS_DMAC0		19
+
+/* MSTP3 */
+#define R8A7794_CLK_SDHI2		11
+#define R8A7794_CLK_SDHI1		12
+#define R8A7794_CLK_SDHI0		14
+#define R8A7794_CLK_MMCIF0		15
+#define R8A7794_CLK_IIC0		18
+#define R8A7794_CLK_IIC1		23
+#define R8A7794_CLK_CMT1		29
+#define R8A7794_CLK_USBDMAC0		30
+#define R8A7794_CLK_USBDMAC1		31
+
+/* MSTP4 */
+#define R8A7794_CLK_IRQC		7
+#define R8A7794_CLK_INTC_SYS		8
+
+/* MSTP5 */
+#define R8A7794_CLK_AUDIO_DMAC0		2
+#define R8A7794_CLK_PWM			23
+
+/* MSTP7 */
+#define R8A7794_CLK_EHCI		3
+#define R8A7794_CLK_HSUSB		4
+#define R8A7794_CLK_HSCIF2		13
+#define R8A7794_CLK_SCIF5		14
+#define R8A7794_CLK_SCIF4		15
+#define R8A7794_CLK_HSCIF1		16
+#define R8A7794_CLK_HSCIF0		17
+#define R8A7794_CLK_SCIF3		18
+#define R8A7794_CLK_SCIF2		19
+#define R8A7794_CLK_SCIF1		20
+#define R8A7794_CLK_SCIF0		21
+#define R8A7794_CLK_DU1			23
+#define R8A7794_CLK_DU0			24
+
+/* MSTP8 */
+#define R8A7794_CLK_VIN1		10
+#define R8A7794_CLK_VIN0		11
+#define R8A7794_CLK_ETHERAVB		12
+#define R8A7794_CLK_ETHER		13
+
+/* MSTP9 */
+#define R8A7794_CLK_GPIO6		5
+#define R8A7794_CLK_GPIO5		7
+#define R8A7794_CLK_GPIO4		8
+#define R8A7794_CLK_GPIO3		9
+#define R8A7794_CLK_GPIO2		10
+#define R8A7794_CLK_GPIO1		11
+#define R8A7794_CLK_GPIO0		12
+#define R8A7794_CLK_RCAN1		15
+#define R8A7794_CLK_RCAN0		16
+#define R8A7794_CLK_QSPI_MOD		17
+#define R8A7794_CLK_I2C5		25
+#define R8A7794_CLK_I2C4		27
+#define R8A7794_CLK_I2C3		28
+#define R8A7794_CLK_I2C2		29
+#define R8A7794_CLK_I2C1		30
+#define R8A7794_CLK_I2C0		31
+
+/* MSTP10 */
+#define R8A7794_CLK_SSI_ALL		5
+#define R8A7794_CLK_SSI9		6
+#define R8A7794_CLK_SSI8		7
+#define R8A7794_CLK_SSI7		8
+#define R8A7794_CLK_SSI6		9
+#define R8A7794_CLK_SSI5		10
+#define R8A7794_CLK_SSI4		11
+#define R8A7794_CLK_SSI3		12
+#define R8A7794_CLK_SSI2		13
+#define R8A7794_CLK_SSI1		14
+#define R8A7794_CLK_SSI0		15
+#define R8A7794_CLK_SCU_ALL		17
+#define R8A7794_CLK_SCU_DVC1		18
+#define R8A7794_CLK_SCU_DVC0		19
+#define R8A7794_CLK_SCU_CTU1_MIX1	20
+#define R8A7794_CLK_SCU_CTU0_MIX0	21
+#define R8A7794_CLK_SCU_SRC6		25
+#define R8A7794_CLK_SCU_SRC5		26
+#define R8A7794_CLK_SCU_SRC4		27
+#define R8A7794_CLK_SCU_SRC3		28
+#define R8A7794_CLK_SCU_SRC2		29
+#define R8A7794_CLK_SCU_SRC1		30
+
+/* MSTP11 */
+#define R8A7794_CLK_SCIFA3		6
+#define R8A7794_CLK_SCIFA4		7
+#define R8A7794_CLK_SCIFA5		8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
new file mode 100644
index 0000000..6314e23
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7794-cpg-mssr.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7794 CPG Core Clocks */
+#define R8A7794_CLK_Z2			0
+#define R8A7794_CLK_ZG			1
+#define R8A7794_CLK_ZTR			2
+#define R8A7794_CLK_ZTRD2		3
+#define R8A7794_CLK_ZT			4
+#define R8A7794_CLK_ZX			5
+#define R8A7794_CLK_ZS			6
+#define R8A7794_CLK_HP			7
+#define R8A7794_CLK_I			8
+#define R8A7794_CLK_B			9
+#define R8A7794_CLK_LB			10
+#define R8A7794_CLK_P			11
+#define R8A7794_CLK_CL			12
+#define R8A7794_CLK_CP			13
+#define R8A7794_CLK_M2			14
+#define R8A7794_CLK_ADSP		15
+#define R8A7794_CLK_ZB3			16
+#define R8A7794_CLK_ZB3D2		17
+#define R8A7794_CLK_DDR			18
+#define R8A7794_CLK_SDH			19
+#define R8A7794_CLK_SD0			20
+#define R8A7794_CLK_SD2			21
+#define R8A7794_CLK_SD3			22
+#define R8A7794_CLK_MMC0		23
+#define R8A7794_CLK_MP			24
+#define R8A7794_CLK_QSPI		25
+#define R8A7794_CLK_CPEX		26
+#define R8A7794_CLK_RCAN		27
+#define R8A7794_CLK_R			28
+#define R8A7794_CLK_OSC			29
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
new file mode 100644
index 0000000..92b3e2a
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7795 CPG Core Clocks */
+#define R8A7795_CLK_Z			0
+#define R8A7795_CLK_Z2			1
+#define R8A7795_CLK_ZR			2
+#define R8A7795_CLK_ZG			3
+#define R8A7795_CLK_ZTR			4
+#define R8A7795_CLK_ZTRD2		5
+#define R8A7795_CLK_ZT			6
+#define R8A7795_CLK_ZX			7
+#define R8A7795_CLK_S0D1		8
+#define R8A7795_CLK_S0D4		9
+#define R8A7795_CLK_S1D1		10
+#define R8A7795_CLK_S1D2		11
+#define R8A7795_CLK_S1D4		12
+#define R8A7795_CLK_S2D1		13
+#define R8A7795_CLK_S2D2		14
+#define R8A7795_CLK_S2D4		15
+#define R8A7795_CLK_S3D1		16
+#define R8A7795_CLK_S3D2		17
+#define R8A7795_CLK_S3D4		18
+#define R8A7795_CLK_LB			19
+#define R8A7795_CLK_CL			20
+#define R8A7795_CLK_ZB3			21
+#define R8A7795_CLK_ZB3D2		22
+#define R8A7795_CLK_CR			23
+#define R8A7795_CLK_CRD2		24
+#define R8A7795_CLK_SD0H		25
+#define R8A7795_CLK_SD0			26
+#define R8A7795_CLK_SD1H		27
+#define R8A7795_CLK_SD1			28
+#define R8A7795_CLK_SD2H		29
+#define R8A7795_CLK_SD2			30
+#define R8A7795_CLK_SD3H		31
+#define R8A7795_CLK_SD3			32
+#define R8A7795_CLK_SSP2		33
+#define R8A7795_CLK_SSP1		34
+#define R8A7795_CLK_SSPRS		35
+#define R8A7795_CLK_RPC			36
+#define R8A7795_CLK_RPCD2		37
+#define R8A7795_CLK_MSO			38
+#define R8A7795_CLK_CANFD		39
+#define R8A7795_CLK_HDMI		40
+#define R8A7795_CLK_CSI0		41
+/* CLK_CSIREF was removed */
+#define R8A7795_CLK_CP			43
+#define R8A7795_CLK_CPEX		44
+#define R8A7795_CLK_R			45
+#define R8A7795_CLK_OSC			46
+
+/* r8a7795 ES2.0 CPG Core Clocks */
+#define R8A7795_CLK_S0D2		47
+#define R8A7795_CLK_S0D3		48
+#define R8A7795_CLK_S0D6		49
+#define R8A7795_CLK_S0D8		50
+#define R8A7795_CLK_S0D12		51
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h
new file mode 100644
index 0000000..c0957cf
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7796-cpg-mssr.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7796 CPG Core Clocks */
+#define R8A7796_CLK_Z			0
+#define R8A7796_CLK_Z2			1
+#define R8A7796_CLK_ZR			2
+#define R8A7796_CLK_ZG			3
+#define R8A7796_CLK_ZTR			4
+#define R8A7796_CLK_ZTRD2		5
+#define R8A7796_CLK_ZT			6
+#define R8A7796_CLK_ZX			7
+#define R8A7796_CLK_S0D1		8
+#define R8A7796_CLK_S0D2		9
+#define R8A7796_CLK_S0D3		10
+#define R8A7796_CLK_S0D4		11
+#define R8A7796_CLK_S0D6		12
+#define R8A7796_CLK_S0D8		13
+#define R8A7796_CLK_S0D12		14
+#define R8A7796_CLK_S1D1		15
+#define R8A7796_CLK_S1D2		16
+#define R8A7796_CLK_S1D4		17
+#define R8A7796_CLK_S2D1		18
+#define R8A7796_CLK_S2D2		19
+#define R8A7796_CLK_S2D4		20
+#define R8A7796_CLK_S3D1		21
+#define R8A7796_CLK_S3D2		22
+#define R8A7796_CLK_S3D4		23
+#define R8A7796_CLK_LB			24
+#define R8A7796_CLK_CL			25
+#define R8A7796_CLK_ZB3			26
+#define R8A7796_CLK_ZB3D2		27
+#define R8A7796_CLK_ZB3D4		28
+#define R8A7796_CLK_CR			29
+#define R8A7796_CLK_CRD2		30
+#define R8A7796_CLK_SD0H		31
+#define R8A7796_CLK_SD0			32
+#define R8A7796_CLK_SD1H		33
+#define R8A7796_CLK_SD1			34
+#define R8A7796_CLK_SD2H		35
+#define R8A7796_CLK_SD2			36
+#define R8A7796_CLK_SD3H		37
+#define R8A7796_CLK_SD3			38
+#define R8A7796_CLK_SSP2		39
+#define R8A7796_CLK_SSP1		40
+#define R8A7796_CLK_SSPRS		41
+#define R8A7796_CLK_RPC			42
+#define R8A7796_CLK_RPCD2		43
+#define R8A7796_CLK_MSO			44
+#define R8A7796_CLK_CANFD		45
+#define R8A7796_CLK_HDMI		46
+#define R8A7796_CLK_CSI0		47
+/* CLK_CSIREF was removed */
+#define R8A7796_CLK_CP			49
+#define R8A7796_CLK_CPEX		50
+#define R8A7796_CLK_R			51
+#define R8A7796_CLK_OSC			52
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77965-cpg-mssr.h b/include/dt-bindings/clock/r8a77965-cpg-mssr.h
new file mode 100644
index 0000000..6d3b5a9
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77965-cpg-mssr.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77965 CPG Core Clocks */
+#define R8A77965_CLK_Z			0
+#define R8A77965_CLK_ZR			1
+#define R8A77965_CLK_ZG			2
+#define R8A77965_CLK_ZTR		3
+#define R8A77965_CLK_ZTRD2		4
+#define R8A77965_CLK_ZT			5
+#define R8A77965_CLK_ZX			6
+#define R8A77965_CLK_S0D1		7
+#define R8A77965_CLK_S0D2		8
+#define R8A77965_CLK_S0D3		9
+#define R8A77965_CLK_S0D4		10
+#define R8A77965_CLK_S0D6		11
+#define R8A77965_CLK_S0D8		12
+#define R8A77965_CLK_S0D12		13
+#define R8A77965_CLK_S1D1		14
+#define R8A77965_CLK_S1D2		15
+#define R8A77965_CLK_S1D4		16
+#define R8A77965_CLK_S2D1		17
+#define R8A77965_CLK_S2D2		18
+#define R8A77965_CLK_S2D4		19
+#define R8A77965_CLK_S3D1		20
+#define R8A77965_CLK_S3D2		21
+#define R8A77965_CLK_S3D4		22
+#define R8A77965_CLK_LB			23
+#define R8A77965_CLK_CL			24
+#define R8A77965_CLK_ZB3		25
+#define R8A77965_CLK_ZB3D2		26
+#define R8A77965_CLK_CR			27
+#define R8A77965_CLK_CRD2		28
+#define R8A77965_CLK_SD0H		29
+#define R8A77965_CLK_SD0		30
+#define R8A77965_CLK_SD1H		31
+#define R8A77965_CLK_SD1		32
+#define R8A77965_CLK_SD2H		33
+#define R8A77965_CLK_SD2		34
+#define R8A77965_CLK_SD3H		35
+#define R8A77965_CLK_SD3		36
+#define R8A77965_CLK_SSP2		37
+#define R8A77965_CLK_SSP1		38
+#define R8A77965_CLK_SSPRS		39
+#define R8A77965_CLK_RPC		40
+#define R8A77965_CLK_RPCD2		41
+#define R8A77965_CLK_MSO		42
+#define R8A77965_CLK_CANFD		43
+#define R8A77965_CLK_HDMI		44
+#define R8A77965_CLK_CSI0		45
+#define R8A77965_CLK_CP			46
+#define R8A77965_CLK_CPEX		47
+#define R8A77965_CLK_R			48
+#define R8A77965_CLK_OSC		49
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
new file mode 100644
index 0000000..4146395
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2017 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77970 CPG Core Clocks */
+#define R8A77970_CLK_Z2			0
+#define R8A77970_CLK_ZR			1
+#define R8A77970_CLK_ZTR		2
+#define R8A77970_CLK_ZTRD2		3
+#define R8A77970_CLK_ZT			4
+#define R8A77970_CLK_ZX			5
+#define R8A77970_CLK_S1D1		6
+#define R8A77970_CLK_S1D2		7
+#define R8A77970_CLK_S1D4		8
+#define R8A77970_CLK_S2D1		9
+#define R8A77970_CLK_S2D2		10
+#define R8A77970_CLK_S2D4		11
+#define R8A77970_CLK_LB			12
+#define R8A77970_CLK_CL			13
+#define R8A77970_CLK_ZB3		14
+#define R8A77970_CLK_ZB3D2		15
+#define R8A77970_CLK_DDR		16
+#define R8A77970_CLK_CR			17
+#define R8A77970_CLK_CRD2		18
+#define R8A77970_CLK_SD0H		19
+#define R8A77970_CLK_SD0		20
+#define R8A77970_CLK_RPC		21
+#define R8A77970_CLK_RPCD2		22
+#define R8A77970_CLK_MSO		23
+#define R8A77970_CLK_CANFD		24
+#define R8A77970_CLK_CSI0		25
+#define R8A77970_CLK_FRAY		26
+#define R8A77970_CLK_CP			27
+#define R8A77970_CLK_CPEX		28
+#define R8A77970_CLK_R			29
+#define R8A77970_CLK_OSC		30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77980-cpg-mssr.h b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
new file mode 100644
index 0000000..a4c0d76
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77980-cpg-mssr.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77980 CPG Core Clocks */
+#define R8A77980_CLK_Z2			0
+#define R8A77980_CLK_ZR			1
+#define R8A77980_CLK_ZTR		2
+#define R8A77980_CLK_ZTRD2		3
+#define R8A77980_CLK_ZT			4
+#define R8A77980_CLK_ZX			5
+#define R8A77980_CLK_S0D1		6
+#define R8A77980_CLK_S0D2		7
+#define R8A77980_CLK_S0D3		8
+#define R8A77980_CLK_S0D4		9
+#define R8A77980_CLK_S0D6		10
+#define R8A77980_CLK_S0D12		11
+#define R8A77980_CLK_S0D24		12
+#define R8A77980_CLK_S1D1		13
+#define R8A77980_CLK_S1D2		14
+#define R8A77980_CLK_S1D4		15
+#define R8A77980_CLK_S2D1		16
+#define R8A77980_CLK_S2D2		17
+#define R8A77980_CLK_S2D4		18
+#define R8A77980_CLK_S3D1		19
+#define R8A77980_CLK_S3D2		20
+#define R8A77980_CLK_S3D4		21
+#define R8A77980_CLK_LB			22
+#define R8A77980_CLK_CL			23
+#define R8A77980_CLK_ZB3		24
+#define R8A77980_CLK_ZB3D2		25
+#define R8A77980_CLK_ZB3D4		26
+#define R8A77980_CLK_SD0H		27
+#define R8A77980_CLK_SD0		28
+#define R8A77980_CLK_RPC		29
+#define R8A77980_CLK_RPCD2		30
+#define R8A77980_CLK_MSO		31
+#define R8A77980_CLK_CANFD		32
+#define R8A77980_CLK_CSI0		33
+#define R8A77980_CLK_CP			34
+#define R8A77980_CLK_CPEX		35
+#define R8A77980_CLK_R			36
+#define R8A77980_CLK_OSC		37
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
new file mode 100644
index 0000000..a596a48
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77990 CPG Core Clocks */
+#define R8A77990_CLK_Z2			0
+#define R8A77990_CLK_ZR			1
+#define R8A77990_CLK_ZG			2
+#define R8A77990_CLK_ZTR		3
+#define R8A77990_CLK_ZT			4
+#define R8A77990_CLK_ZX			5
+#define R8A77990_CLK_S0D1		6
+#define R8A77990_CLK_S0D3		7
+#define R8A77990_CLK_S0D6		8
+#define R8A77990_CLK_S0D12		9
+#define R8A77990_CLK_S0D24		10
+#define R8A77990_CLK_S1D1		11
+#define R8A77990_CLK_S1D2		12
+#define R8A77990_CLK_S1D4		13
+#define R8A77990_CLK_S2D1		14
+#define R8A77990_CLK_S2D2		15
+#define R8A77990_CLK_S2D4		16
+#define R8A77990_CLK_S3D1		17
+#define R8A77990_CLK_S3D2		18
+#define R8A77990_CLK_S3D4		19
+#define R8A77990_CLK_S0D6C		20
+#define R8A77990_CLK_S3D1C		21
+#define R8A77990_CLK_S3D2C		22
+#define R8A77990_CLK_S3D4C		23
+#define R8A77990_CLK_LB			24
+#define R8A77990_CLK_CL			25
+#define R8A77990_CLK_ZB3		26
+#define R8A77990_CLK_ZB3D2		27
+#define R8A77990_CLK_CR			28
+#define R8A77990_CLK_CRD2		29
+#define R8A77990_CLK_SD0H		30
+#define R8A77990_CLK_SD0		31
+#define R8A77990_CLK_SD1H		32
+#define R8A77990_CLK_SD1		33
+#define R8A77990_CLK_SD3H		34
+#define R8A77990_CLK_SD3		35
+#define R8A77990_CLK_RPC		36
+#define R8A77990_CLK_RPCD2		37
+#define R8A77990_CLK_ZA2		38
+#define R8A77990_CLK_ZA8		39
+#define R8A77990_CLK_Z2D		40
+#define R8A77990_CLK_CANFD		41
+#define R8A77990_CLK_MSO		42
+#define R8A77990_CLK_R			43
+#define R8A77990_CLK_OSC		44
+#define R8A77990_CLK_LV0		45
+#define R8A77990_CLK_LV1		46
+#define R8A77990_CLK_CSI0		47
+#define R8A77990_CLK_CP			48
+#define R8A77990_CLK_CPEX		49
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
new file mode 100644
index 0000000..fd701c4
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77995-cpg-mssr.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (C) 2017 Glider bvba
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a77995 CPG Core Clocks */
+#define R8A77995_CLK_Z2			0
+#define R8A77995_CLK_ZG			1
+#define R8A77995_CLK_ZTR		2
+#define R8A77995_CLK_ZT			3
+#define R8A77995_CLK_ZX			4
+#define R8A77995_CLK_S0D1		5
+#define R8A77995_CLK_S1D1		6
+#define R8A77995_CLK_S1D2		7
+#define R8A77995_CLK_S1D4		8
+#define R8A77995_CLK_S2D1		9
+#define R8A77995_CLK_S2D2		10
+#define R8A77995_CLK_S2D4		11
+#define R8A77995_CLK_S3D1		12
+#define R8A77995_CLK_S3D2		13
+#define R8A77995_CLK_S3D4		14
+#define R8A77995_CLK_S1D4C		15
+#define R8A77995_CLK_S3D1C		16
+#define R8A77995_CLK_S3D2C		17
+#define R8A77995_CLK_S3D4C		18
+#define R8A77995_CLK_LB			19
+#define R8A77995_CLK_CL			20
+#define R8A77995_CLK_ZB3		21
+#define R8A77995_CLK_ZB3D2		22
+#define R8A77995_CLK_CR			23
+#define R8A77995_CLK_CRD2		24
+#define R8A77995_CLK_SD0H		25
+#define R8A77995_CLK_SD0		26
+/* CLK_SSP2 was removed */
+/* CLK_SSP1 was removed */
+#define R8A77995_CLK_RPC		29
+#define R8A77995_CLK_RPCD2		30
+#define R8A77995_CLK_ZA2		31
+#define R8A77995_CLK_ZA8		32
+#define R8A77995_CLK_Z2D		33
+#define R8A77995_CLK_CANFD		34
+#define R8A77995_CLK_MSO		35
+#define R8A77995_CLK_R			36
+#define R8A77995_CLK_OSC		37
+#define R8A77995_CLK_LV0		38
+#define R8A77995_CLK_LV1		39
+#define R8A77995_CLK_CP			40
+#define R8A77995_CLK_CPEX		41
+
+#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h
new file mode 100644
index 0000000..569a3cc
--- /dev/null
+++ b/include/dt-bindings/clock/renesas-cpg-mssr.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
+
+#define CPG_CORE			0	/* Core Clock */
+#define CPG_MOD				1	/* Module Clock */
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h
new file mode 100644
index 0000000..2c0552d
--- /dev/null
+++ b/include/dt-bindings/clock/rk3036-cru.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_GPLL		3
+#define ARMCLK			4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU		64
+#define SCLK_SPI		65
+#define SCLK_SDMMC		68
+#define SCLK_SDIO		69
+#define SCLK_EMMC		71
+#define SCLK_NANDC		76
+#define SCLK_UART0		77
+#define SCLK_UART1		78
+#define SCLK_UART2		79
+#define SCLK_I2S		82
+#define SCLK_SPDIF		83
+#define SCLK_TIMER0		85
+#define SCLK_TIMER1		86
+#define SCLK_TIMER2		87
+#define SCLK_TIMER3		88
+#define SCLK_OTGPHY0		93
+#define SCLK_LCDC		100
+#define SCLK_HDMI		109
+#define SCLK_HEVC		111
+#define SCLK_I2S_OUT		113
+#define SCLK_SDMMC_DRV		114
+#define SCLK_SDIO_DRV		115
+#define SCLK_EMMC_DRV		117
+#define SCLK_SDMMC_SAMPLE	118
+#define SCLK_SDIO_SAMPLE	119
+#define SCLK_EMMC_SAMPLE	121
+#define SCLK_PVTM_CORE          123
+#define SCLK_PVTM_GPU           124
+#define SCLK_PVTM_VIDEO         125
+#define SCLK_MAC		151
+#define SCLK_MACREF		152
+#define SCLK_SFC		160
+
+#define DCLK_LCDC		190
+
+/* aclk gates */
+#define ACLK_DMAC2		194
+#define ACLK_LCDC		197
+#define ACLK_VIO		203
+#define ACLK_VCODEC		208
+#define ACLK_CPU		209
+#define ACLK_PERI		210
+
+/* pclk gates */
+#define PCLK_GPIO0		320
+#define PCLK_GPIO1		321
+#define PCLK_GPIO2		322
+#define PCLK_GRF		329
+#define PCLK_I2C0		332
+#define PCLK_I2C1		333
+#define PCLK_I2C2		334
+#define PCLK_SPI		338
+#define PCLK_UART0		341
+#define PCLK_UART1		342
+#define PCLK_UART2		343
+#define PCLK_PWM		350
+#define PCLK_TIMER		353
+#define PCLK_HDMI		360
+#define PCLK_CPU		362
+#define PCLK_PERI		363
+#define PCLK_DDRUPCTL		364
+#define PCLK_WDT		368
+
+/* hclk gates */
+#define HCLK_OTG0		449
+#define HCLK_OTG1		450
+#define HCLK_NANDC		453
+#define HCLK_SDMMC		456
+#define HCLK_SDIO		457
+#define HCLK_EMMC		459
+#define HCLK_I2S		462
+#define HCLK_LCDC		465
+#define HCLK_ROM		467
+#define HCLK_VIO_BUS		472
+#define HCLK_VCODEC		476
+#define HCLK_CPU		477
+#define HCLK_PERI		478
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0		0
+#define SRST_CORE1		1
+#define SRST_CORE0_DBG		4
+#define SRST_CORE1_DBG		5
+#define SRST_CORE0_POR		8
+#define SRST_CORE1_POR		9
+#define SRST_L2C		12
+#define SRST_TOPDBG		13
+#define SRST_STRC_SYS_A		14
+#define SRST_PD_CORE_NIU	15
+
+#define SRST_TIMER2		16
+#define SRST_CPUSYS_H		17
+#define SRST_AHB2APB_H		19
+#define SRST_TIMER3		20
+#define SRST_INTMEM		21
+#define SRST_ROM		22
+#define SRST_PERI_NIU		23
+#define SRST_I2S		24
+#define SRST_DDR_PLL		25
+#define SRST_GPU_DLL		26
+#define SRST_TIMER0		27
+#define SRST_TIMER1		28
+#define SRST_CORE_DLL		29
+#define SRST_EFUSE_P		30
+#define SRST_ACODEC_P		31
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_UART0		39
+#define SRST_UART1		40
+#define SRST_UART2		41
+#define SRST_I2C0		43
+#define SRST_I2C1		44
+#define SRST_I2C2		45
+#define SRST_SFC		47
+
+#define SRST_PWM0		48
+#define SRST_DAP		51
+#define SRST_DAP_SYS		52
+#define SRST_GRF		55
+#define SRST_PERIPHSYS_A	57
+#define SRST_PERIPHSYS_H	58
+#define SRST_PERIPHSYS_P	59
+#define SRST_CPU_PERI		61
+#define SRST_EMEM_PERI		62
+#define SRST_USB_PERI		63
+
+#define SRST_DMA2		64
+#define SRST_MAC		66
+#define SRST_NANDC		68
+#define SRST_USBOTG0		69
+#define SRST_OTGC0		71
+#define SRST_USBOTG1		72
+#define SRST_OTGC1		74
+#define SRST_DDRMSCH		79
+
+#define SRST_MMC0		81
+#define SRST_SDIO		82
+#define SRST_EMMC		83
+#define SRST_SPI0		84
+#define SRST_WDT		86
+#define SRST_DDRPHY		88
+#define SRST_DDRPHY_P		89
+#define SRST_DDRCTRL		90
+#define SRST_DDRCTRL_P		91
+
+#define SRST_HDMI_P		96
+#define SRST_VIO_BUS_H		99
+#define SRST_UTMI0		103
+#define SRST_UTMI1		104
+#define SRST_USBPOR		105
+
+#define SRST_VCODEC_A		112
+#define SRST_VCODEC_H		113
+#define SRST_VIO1_A		114
+#define SRST_HEVC		115
+#define SRST_VCODEC_NIU_A	116
+#define SRST_LCDC1_A		117
+#define SRST_LCDC1_H		118
+#define SRST_LCDC1_D		119
+#define SRST_GPU		120
+#define SRST_GPU_NIU_A		122
+
+#define SRST_DBG_P		131
+
+#endif
diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h
new file mode 100644
index 0000000..014eec5
--- /dev/null
+++ b/include/dt-bindings/clock/rk3066a-cru.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
+
+#include <dt-bindings/clock/rk3188-cru-common.h>
+
+/* soft-reset indices */
+#define SRST_SRST1		0
+#define SRST_SRST2		1
+
+#define SRST_L2MEM		18
+#define SRST_I2S0		23
+#define SRST_I2S1		24
+#define SRST_I2S2		25
+#define SRST_TIMER2		29
+
+#define SRST_GPIO4		36
+#define SRST_GPIO6		38
+
+#define SRST_TSADC		92
+
+#define SRST_HDMI		96
+#define SRST_HDMI_APB		97
+#define SRST_CIF1		111
+
+#endif
diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h
new file mode 100644
index 0000000..cfb3afb
--- /dev/null
+++ b/include/dt-bindings/clock/rk3128-cru.h
@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_GPLL		3
+#define ARMCLK			4
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU		64
+#define SCLK_SPI		65
+#define SCLK_SDMMC		68
+#define SCLK_SDIO		69
+#define SCLK_EMMC		71
+#define SCLK_NANDC		76
+#define SCLK_UART0		77
+#define SCLK_UART1		78
+#define SCLK_UART2		79
+#define SCLK_I2S		82
+#define SCLK_SPDIF		83
+#define SCLK_TIMER0		85
+#define SCLK_TIMER1		86
+#define SCLK_TIMER2		87
+#define SCLK_TIMER3		88
+#define SCLK_SARADC		91
+#define SCLK_OTGPHY0		93
+#define SCLK_LCDC		100
+#define SCLK_HDMI		109
+#define SCLK_HEVC		111
+#define SCLK_I2S_OUT		113
+#define SCLK_SDMMC_DRV		114
+#define SCLK_SDIO_DRV		115
+#define SCLK_EMMC_DRV		117
+#define SCLK_SDMMC_SAMPLE	118
+#define SCLK_SDIO_SAMPLE	119
+#define SCLK_EMMC_SAMPLE	121
+#define SCLK_PVTM_CORE          123
+#define SCLK_PVTM_GPU           124
+#define SCLK_PVTM_VIDEO         125
+#define SCLK_MAC		151
+#define SCLK_MACREF		152
+#define SCLK_SFC		160
+
+#define DCLK_LCDC		190
+
+/* aclk gates */
+#define ACLK_DMAC2		194
+#define ACLK_VIO0		197
+#define ACLK_VIO1		203
+#define ACLK_VCODEC		208
+#define ACLK_CPU		209
+#define ACLK_PERI		210
+
+/* pclk gates */
+#define PCLK_SARADC		318
+#define PCLK_GPIO0		320
+#define PCLK_GPIO1		321
+#define PCLK_GPIO2		322
+#define PCLK_GPIO3		323
+#define PCLK_GRF		329
+#define PCLK_I2C0		332
+#define PCLK_I2C1		333
+#define PCLK_I2C2		334
+#define PCLK_I2C3		335
+#define PCLK_SPI		338
+#define PCLK_UART0		341
+#define PCLK_UART1		342
+#define PCLK_UART2		343
+#define PCLK_PWM		350
+#define PCLK_TIMER		353
+#define PCLK_HDMI		360
+#define PCLK_CPU		362
+#define PCLK_PERI		363
+#define PCLK_DDRUPCTL		364
+#define PCLK_WDT		368
+
+/* hclk gates */
+#define HCLK_OTG0		449
+#define HCLK_OTG1		450
+#define HCLK_NANDC		453
+#define HCLK_SDMMC		456
+#define HCLK_SDIO		457
+#define HCLK_EMMC		459
+#define HCLK_I2S		462
+#define HCLK_LCDC		465
+#define HCLK_ROM		467
+#define HCLK_VIO_BUS		472
+#define HCLK_VCODEC		476
+#define HCLK_CPU		477
+#define HCLK_PERI		478
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0		0
+#define SRST_CORE1		1
+#define SRST_CORE0_DBG		4
+#define SRST_CORE1_DBG		5
+#define SRST_CORE0_POR		8
+#define SRST_CORE1_POR		9
+#define SRST_L2C		12
+#define SRST_TOPDBG		13
+#define SRST_STRC_SYS_A		14
+#define SRST_PD_CORE_NIU	15
+
+#define SRST_TIMER2		16
+#define SRST_CPUSYS_H		17
+#define SRST_AHB2APB_H		19
+#define SRST_TIMER3		20
+#define SRST_INTMEM		21
+#define SRST_ROM		22
+#define SRST_PERI_NIU		23
+#define SRST_I2S		24
+#define SRST_DDR_PLL		25
+#define SRST_GPU_DLL		26
+#define SRST_TIMER0		27
+#define SRST_TIMER1		28
+#define SRST_CORE_DLL		29
+#define SRST_EFUSE_P		30
+#define SRST_ACODEC_P		31
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_UART0		39
+#define SRST_UART1		40
+#define SRST_UART2		41
+#define SRST_I2C0		43
+#define SRST_I2C1		44
+#define SRST_I2C2		45
+#define SRST_SFC		47
+
+#define SRST_PWM0		48
+#define SRST_DAP		51
+#define SRST_DAP_SYS		52
+#define SRST_GRF		55
+#define SRST_PERIPHSYS_A	57
+#define SRST_PERIPHSYS_H	58
+#define SRST_PERIPHSYS_P	59
+#define SRST_CPU_PERI		61
+#define SRST_EMEM_PERI		62
+#define SRST_USB_PERI		63
+
+#define SRST_DMA2		64
+#define SRST_MAC		66
+#define SRST_NANDC		68
+#define SRST_USBOTG0		69
+#define SRST_OTGC0		71
+#define SRST_USBOTG1		72
+#define SRST_OTGC1		74
+#define SRST_DDRMSCH		79
+
+#define SRST_MMC0		81
+#define SRST_SDIO		82
+#define SRST_EMMC		83
+#define SRST_SPI0		84
+#define SRST_WDT		86
+#define SRST_SARADC		87
+#define SRST_DDRPHY		88
+#define SRST_DDRPHY_P		89
+#define SRST_DDRCTRL		90
+#define SRST_DDRCTRL_P		91
+
+#define SRST_HDMI_P		96
+#define SRST_VIO_BUS_H		99
+#define SRST_UTMI0		103
+#define SRST_UTMI1		104
+#define SRST_USBPOR		105
+
+#define SRST_VCODEC_A		112
+#define SRST_VCODEC_H		113
+#define SRST_VIO1_A		114
+#define SRST_HEVC		115
+#define SRST_VCODEC_NIU_A	116
+#define SRST_LCDC1_A		117
+#define SRST_LCDC1_H		118
+#define SRST_LCDC1_D		119
+#define SRST_GPU		120
+#define SRST_GPU_NIU_A		122
+
+#define SRST_DBG_P		131
+
+#endif
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
new file mode 100644
index 0000000..1e7931d
--- /dev/null
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
+
+/* core clocks from */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define CORE_PERI		5
+#define CORE_L2C		6
+#define ARMCLK			7
+
+/* sclk gates (special clocks) */
+#define SCLK_UART0		64
+#define SCLK_UART1		65
+#define SCLK_UART2		66
+#define SCLK_UART3		67
+#define SCLK_MAC		68
+#define SCLK_SPI0		69
+#define SCLK_SPI1		70
+#define SCLK_SARADC		71
+#define SCLK_SDMMC		72
+#define SCLK_SDIO		73
+#define SCLK_EMMC		74
+#define SCLK_I2S0		75
+#define SCLK_I2S1		76
+#define SCLK_I2S2		77
+#define SCLK_SPDIF		78
+#define SCLK_CIF0		79
+#define SCLK_CIF1		80
+#define SCLK_OTGPHY0		81
+#define SCLK_OTGPHY1		82
+#define SCLK_HSADC		83
+#define SCLK_TIMER0		84
+#define SCLK_TIMER1		85
+#define SCLK_TIMER2		86
+#define SCLK_TIMER3		87
+#define SCLK_TIMER4		88
+#define SCLK_TIMER5		89
+#define SCLK_TIMER6		90
+#define SCLK_JTAG		91
+#define SCLK_SMC		92
+#define SCLK_TSADC		93
+
+#define DCLK_LCDC0		190
+#define DCLK_LCDC1		191
+
+/* aclk gates */
+#define ACLK_DMA1		192
+#define ACLK_DMA2		193
+#define ACLK_GPS		194
+#define ACLK_LCDC0		195
+#define ACLK_LCDC1		196
+#define ACLK_GPU		197
+#define ACLK_SMC		198
+#define ACLK_CIF		199
+#define ACLK_IPP		200
+#define ACLK_RGA		201
+#define ACLK_CIF0		202
+#define ACLK_CPU		203
+#define ACLK_PERI		204
+
+/* pclk gates */
+#define PCLK_GRF		320
+#define PCLK_PMU		321
+#define PCLK_TIMER0		322
+#define PCLK_TIMER1		323
+#define PCLK_TIMER2		324
+#define PCLK_TIMER3		325
+#define PCLK_PWM01		326
+#define PCLK_PWM23		327
+#define PCLK_SPI0		328
+#define PCLK_SPI1		329
+#define PCLK_SARADC		330
+#define PCLK_WDT		331
+#define PCLK_UART0		332
+#define PCLK_UART1		333
+#define PCLK_UART2		334
+#define PCLK_UART3		335
+#define PCLK_I2C0		336
+#define PCLK_I2C1		337
+#define PCLK_I2C2		338
+#define PCLK_I2C3		339
+#define PCLK_I2C4		340
+#define PCLK_GPIO0		341
+#define PCLK_GPIO1		342
+#define PCLK_GPIO2		343
+#define PCLK_GPIO3		344
+#define PCLK_GPIO4		345
+#define PCLK_GPIO6		346
+#define PCLK_EFUSE		347
+#define PCLK_TZPC		348
+#define PCLK_TSADC		349
+#define PCLK_CPU		350
+#define PCLK_PERI		351
+#define PCLK_DDRUPCTL		352
+#define PCLK_PUBL		353
+
+/* hclk gates */
+#define HCLK_SDMMC		448
+#define HCLK_SDIO		449
+#define HCLK_EMMC		450
+#define HCLK_OTG0		451
+#define HCLK_EMAC		452
+#define HCLK_SPDIF		453
+#define HCLK_I2S0		454
+#define HCLK_I2S1		455
+#define HCLK_I2S2		456
+#define HCLK_OTG1		457
+#define HCLK_HSIC		458
+#define HCLK_HSADC		459
+#define HCLK_PIDF		460
+#define HCLK_LCDC0		461
+#define HCLK_LCDC1		462
+#define HCLK_ROM		463
+#define HCLK_CIF0		464
+#define HCLK_IPP		465
+#define HCLK_RGA		466
+#define HCLK_NANDC0		467
+#define HCLK_CPU		468
+#define HCLK_PERI		469
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_MCORE		2
+#define SRST_CORE0		3
+#define SRST_CORE1		4
+#define SRST_MCORE_DBG		7
+#define SRST_CORE0_DBG		8
+#define SRST_CORE1_DBG		9
+#define SRST_CORE0_WDT		12
+#define SRST_CORE1_WDT		13
+#define SRST_STRC_SYS		14
+#define SRST_L2C		15
+
+#define SRST_CPU_AHB		17
+#define SRST_AHB2APB		19
+#define SRST_DMA1		20
+#define SRST_INTMEM		21
+#define SRST_ROM		22
+#define SRST_SPDIF		26
+#define SRST_TIMER0		27
+#define SRST_TIMER1		28
+#define SRST_EFUSE		30
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_GPIO3		35
+
+#define SRST_UART0		39
+#define SRST_UART1		40
+#define SRST_UART2		41
+#define SRST_UART3		42
+#define SRST_I2C0		43
+#define SRST_I2C1		44
+#define SRST_I2C2		45
+#define SRST_I2C3		46
+#define SRST_I2C4		47
+
+#define SRST_PWM0		48
+#define SRST_PWM1		49
+#define SRST_DAP_PO		50
+#define SRST_DAP		51
+#define SRST_DAP_SYS		52
+#define SRST_TPIU_ATB		53
+#define SRST_PMU_APB		54
+#define SRST_GRF		55
+#define SRST_PMU		56
+#define SRST_PERI_AXI		57
+#define SRST_PERI_AHB		58
+#define SRST_PERI_APB		59
+#define SRST_PERI_NIU		60
+#define SRST_CPU_PERI		61
+#define SRST_EMEM_PERI		62
+#define SRST_USB_PERI		63
+
+#define SRST_DMA2		64
+#define SRST_SMC		65
+#define SRST_MAC		66
+#define SRST_NANC0		68
+#define SRST_USBOTG0		69
+#define SRST_USBPHY0		70
+#define SRST_OTGC0		71
+#define SRST_USBOTG1		72
+#define SRST_USBPHY1		73
+#define SRST_OTGC1		74
+#define SRST_HSADC		76
+#define SRST_PIDFILTER		77
+#define SRST_DDR_MSCH		79
+
+#define SRST_TZPC		80
+#define SRST_SDMMC		81
+#define SRST_SDIO		82
+#define SRST_EMMC		83
+#define SRST_SPI0		84
+#define SRST_SPI1		85
+#define SRST_WDT		86
+#define SRST_SARADC		87
+#define SRST_DDRPHY		88
+#define SRST_DDRPHY_APB		89
+#define SRST_DDRCTL		90
+#define SRST_DDRCTL_APB		91
+#define SRST_DDRPUB		93
+
+#define SRST_VIO0_AXI		98
+#define SRST_VIO0_AHB		99
+#define SRST_LCDC0_AXI		100
+#define SRST_LCDC0_AHB		101
+#define SRST_LCDC0_DCLK		102
+#define SRST_LCDC1_AXI		103
+#define SRST_LCDC1_AHB		104
+#define SRST_LCDC1_DCLK		105
+#define SRST_IPP_AXI		106
+#define SRST_IPP_AHB		107
+#define SRST_RGA_AXI		108
+#define SRST_RGA_AHB		109
+#define SRST_CIF0		110
+
+#define SRST_VCODEC_AXI		112
+#define SRST_VCODEC_AHB		113
+#define SRST_VIO1_AXI		114
+#define SRST_VCODEC_CPU		115
+#define SRST_VCODEC_NIU		116
+#define SRST_GPU		120
+#define SRST_GPU_NIU		122
+#define SRST_TFUN_ATB		125
+#define SRST_TFUN_APB		126
+#define SRST_CTI4_APB		127
+
+#define SRST_TPIU_APB		128
+#define SRST_TRACE		129
+#define SRST_CORE_DBG		130
+#define SRST_DBG_APB		131
+#define SRST_CTI0		132
+#define SRST_CTI0_APB		133
+#define SRST_CTI1		134
+#define SRST_CTI1_APB		135
+#define SRST_PTM_CORE0		136
+#define SRST_PTM_CORE1		137
+#define SRST_PTM0		138
+#define SRST_PTM0_ATB		139
+#define SRST_PTM1		140
+#define SRST_PTM1_ATB		141
+#define SRST_CTM		142
+#define SRST_TS			143
+
+#endif
diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h
new file mode 100644
index 0000000..1da306e
--- /dev/null
+++ b/include/dt-bindings/clock/rk3188-cru.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
+
+#include <dt-bindings/clock/rk3188-cru-common.h>
+
+/* soft-reset indices */
+#define SRST_PTM_CORE2		0
+#define SRST_PTM_CORE3		1
+#define SRST_CORE2		5
+#define SRST_CORE3		6
+#define SRST_CORE2_DBG		10
+#define SRST_CORE3_DBG		11
+
+#define SRST_TIMER2		16
+#define SRST_TIMER4		23
+#define SRST_I2S0		24
+#define SRST_TIMER5		25
+#define SRST_TIMER3		29
+#define SRST_TIMER6		31
+
+#define SRST_PTM3		36
+#define SRST_PTM3_ATB		37
+
+#define SRST_GPS		67
+#define SRST_HSICPHY		75
+#define SRST_TIMER		78
+
+#define SRST_PTM2		92
+#define SRST_CORE2_WDT		94
+#define SRST_CORE3_WDT		95
+
+#define SRST_PTM2_ATB		111
+
+#define SRST_HSIC		117
+#define SRST_CTI2		118
+#define SRST_CTI2_APB		119
+#define SRST_GPU_BRIDGE		121
+#define SRST_CTI3		123
+#define SRST_CTI3_APB		124
+
+#endif
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
new file mode 100644
index 0000000..1217d52
--- /dev/null
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -0,0 +1,237 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define ARMCLK			5
+
+/* sclk gates (special clocks) */
+#define SCLK_SPI0		65
+#define SCLK_NANDC		67
+#define SCLK_SDMMC		68
+#define SCLK_SDIO		69
+#define SCLK_EMMC		71
+#define SCLK_TSADC		72
+#define SCLK_UART0		77
+#define SCLK_UART1		78
+#define SCLK_UART2		79
+#define SCLK_I2S0		80
+#define SCLK_I2S1		81
+#define SCLK_I2S2		82
+#define SCLK_SPDIF		83
+#define SCLK_TIMER0		85
+#define SCLK_TIMER1		86
+#define SCLK_TIMER2		87
+#define SCLK_TIMER3		88
+#define SCLK_TIMER4		89
+#define SCLK_TIMER5		90
+#define SCLK_I2S_OUT		113
+#define SCLK_SDMMC_DRV		114
+#define SCLK_SDIO_DRV		115
+#define SCLK_EMMC_DRV		117
+#define SCLK_SDMMC_SAMPLE	118
+#define SCLK_SDIO_SAMPLE	119
+#define SCLK_EMMC_SAMPLE	121
+#define SCLK_VOP		122
+#define SCLK_HDMI_HDCP		123
+#define SCLK_MAC_SRC		124
+#define SCLK_MAC_EXTCLK		125
+#define SCLK_MAC		126
+#define SCLK_MAC_REFOUT		127
+#define SCLK_MAC_REF		128
+#define SCLK_MAC_RX		129
+#define SCLK_MAC_TX		130
+#define SCLK_MAC_PHY		131
+#define SCLK_MAC_OUT		132
+
+/* dclk gates */
+#define DCLK_VOP		190
+#define DCLK_HDMI_PHY		191
+
+/* aclk gates */
+#define ACLK_DMAC		194
+#define ACLK_PERI		210
+#define ACLK_VOP		211
+#define ACLK_GMAC		212
+
+/* pclk gates */
+#define PCLK_GPIO0		320
+#define PCLK_GPIO1		321
+#define PCLK_GPIO2		322
+#define PCLK_GPIO3		323
+#define PCLK_GRF		329
+#define PCLK_I2C0		332
+#define PCLK_I2C1		333
+#define PCLK_I2C2		334
+#define PCLK_I2C3		335
+#define PCLK_SPI0		338
+#define PCLK_UART0		341
+#define PCLK_UART1		342
+#define PCLK_UART2		343
+#define PCLK_TSADC		344
+#define PCLK_PWM		350
+#define PCLK_TIMER		353
+#define PCLK_PERI		363
+#define PCLK_HDMI_CTRL		364
+#define PCLK_HDMI_PHY		365
+#define PCLK_GMAC		367
+
+/* hclk gates */
+#define HCLK_I2S0_8CH		442
+#define HCLK_I2S1_8CH		443
+#define HCLK_I2S2_2CH		444
+#define HCLK_SPDIF_8CH		445
+#define HCLK_VOP		452
+#define HCLK_NANDC		453
+#define HCLK_SDMMC		456
+#define HCLK_SDIO		457
+#define HCLK_EMMC		459
+#define HCLK_PERI		478
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO		0
+#define SRST_CORE1_PO		1
+#define SRST_CORE2_PO		2
+#define SRST_CORE3_PO		3
+#define SRST_CORE0		4
+#define SRST_CORE1		5
+#define SRST_CORE2		6
+#define SRST_CORE3		7
+#define SRST_CORE0_DBG		8
+#define SRST_CORE1_DBG		9
+#define SRST_CORE2_DBG		10
+#define SRST_CORE3_DBG		11
+#define SRST_TOPDBG		12
+#define SRST_ACLK_CORE		13
+#define SRST_NOC		14
+#define SRST_L2C		15
+
+#define SRST_CPUSYS_H		18
+#define SRST_BUSSYS_H		19
+#define SRST_SPDIF		20
+#define SRST_INTMEM		21
+#define SRST_ROM		22
+#define SRST_OTG_ADP		23
+#define SRST_I2S0		24
+#define SRST_I2S1		25
+#define SRST_I2S2		26
+#define SRST_ACODEC_P		27
+#define SRST_DFIMON		28
+#define SRST_MSCH		29
+#define SRST_EFUSE1024		30
+#define SRST_EFUSE256		31
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_GPIO3		35
+#define SRST_PERIPH_NOC_A	36
+#define SRST_PERIPH_NOC_BUS_H	37
+#define SRST_PERIPH_NOC_P	38
+#define SRST_UART0		39
+#define SRST_UART1		40
+#define SRST_UART2		41
+#define SRST_PHYNOC		42
+#define SRST_I2C0		43
+#define SRST_I2C1		44
+#define SRST_I2C2		45
+#define SRST_I2C3		46
+
+#define SRST_PWM		48
+#define SRST_A53_GIC		49
+#define SRST_DAP		51
+#define SRST_DAP_NOC		52
+#define SRST_CRYPTO		53
+#define SRST_SGRF		54
+#define SRST_GRF		55
+#define SRST_GMAC		56
+#define SRST_PERIPH_NOC_H	58
+#define SRST_MACPHY		63
+
+#define SRST_DMA		64
+#define SRST_NANDC		68
+#define SRST_USBOTG		69
+#define SRST_OTGC		70
+#define SRST_USBHOST0		71
+#define SRST_HOST_CTRL0		72
+#define SRST_USBHOST1		73
+#define SRST_HOST_CTRL1		74
+#define SRST_USBHOST2		75
+#define SRST_HOST_CTRL2		76
+#define SRST_USBPOR0		77
+#define SRST_USBPOR1		78
+#define SRST_DDRMSCH		79
+
+#define SRST_SMART_CARD		80
+#define SRST_SDMMC		81
+#define SRST_SDIO		82
+#define SRST_EMMC		83
+#define SRST_SPI		84
+#define SRST_TSP_H		85
+#define SRST_TSP		86
+#define SRST_TSADC		87
+#define SRST_DDRPHY		88
+#define SRST_DDRPHY_P		89
+#define SRST_DDRCTRL		90
+#define SRST_DDRCTRL_P		91
+#define SRST_HOST0_ECHI		92
+#define SRST_HOST1_ECHI		93
+#define SRST_HOST2_ECHI		94
+#define SRST_VOP_NOC_A		95
+
+#define SRST_HDMI_P		96
+#define SRST_VIO_ARBI_H		97
+#define SRST_IEP_NOC_A		98
+#define SRST_VIO_NOC_H		99
+#define SRST_VOP_A		100
+#define SRST_VOP_H		101
+#define SRST_VOP_D		102
+#define SRST_UTMI0		103
+#define SRST_UTMI1		104
+#define SRST_UTMI2		105
+#define SRST_UTMI3		106
+#define SRST_RGA		107
+#define SRST_RGA_NOC_A		108
+#define SRST_RGA_A		109
+#define SRST_RGA_H		110
+#define SRST_HDCP_A		111
+
+#define SRST_VPU_A		112
+#define SRST_VPU_H		113
+#define SRST_VPU_NOC_A		116
+#define SRST_VPU_NOC_H		117
+#define SRST_RKVDEC_A		118
+#define SRST_RKVDEC_NOC_A	119
+#define SRST_RKVDEC_H		120
+#define SRST_RKVDEC_NOC_H	121
+#define SRST_RKVDEC_CORE	122
+#define SRST_RKVDEC_CABAC	123
+#define SRST_IEP_A		124
+#define SRST_IEP_H		125
+#define SRST_GPU_A		126
+#define SRST_GPU_NOC_A		127
+
+#define SRST_CORE_DBG		128
+#define SRST_DBG_P		129
+#define SRST_TIMER0		130
+#define SRST_TIMER1		131
+#define SRST_TIMER2		132
+#define SRST_TIMER3		133
+#define SRST_TIMER4		134
+#define SRST_TIMER5		135
+#define SRST_VIO_H2P		136
+#define SRST_HDMIPHY		139
+#define SRST_VDAC		140
+#define SRST_TIMER_6CH_P	141
+
+#endif
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
new file mode 100644
index 0000000..e368d76
--- /dev/null
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ */
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define PLL_NPLL		5
+#define ARMCLK			6
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU		64
+#define SCLK_SPI0		65
+#define SCLK_SPI1		66
+#define SCLK_SPI2		67
+#define SCLK_SDMMC		68
+#define SCLK_SDIO0		69
+#define SCLK_SDIO1		70
+#define SCLK_EMMC		71
+#define SCLK_TSADC		72
+#define SCLK_SARADC		73
+#define SCLK_PS2C		74
+#define SCLK_NANDC0		75
+#define SCLK_NANDC1		76
+#define SCLK_UART0		77
+#define SCLK_UART1		78
+#define SCLK_UART2		79
+#define SCLK_UART3		80
+#define SCLK_UART4		81
+#define SCLK_I2S0		82
+#define SCLK_SPDIF		83
+#define SCLK_SPDIF8CH		84
+#define SCLK_TIMER0		85
+#define SCLK_TIMER1		86
+#define SCLK_TIMER2		87
+#define SCLK_TIMER3		88
+#define SCLK_TIMER4		89
+#define SCLK_TIMER5		90
+#define SCLK_TIMER6		91
+#define SCLK_HSADC		92
+#define SCLK_OTGPHY0		93
+#define SCLK_OTGPHY1		94
+#define SCLK_OTGPHY2		95
+#define SCLK_OTG_ADP		96
+#define SCLK_HSICPHY480M	97
+#define SCLK_HSICPHY12M		98
+#define SCLK_MACREF		99
+#define SCLK_LCDC_PWM0		100
+#define SCLK_LCDC_PWM1		101
+#define SCLK_MAC_RX		102
+#define SCLK_MAC_TX		103
+#define SCLK_EDP_24M		104
+#define SCLK_EDP		105
+#define SCLK_RGA		106
+#define SCLK_ISP		107
+#define SCLK_ISP_JPE		108
+#define SCLK_HDMI_HDCP		109
+#define SCLK_HDMI_CEC		110
+#define SCLK_HEVC_CABAC		111
+#define SCLK_HEVC_CORE		112
+#define SCLK_I2S0_OUT		113
+#define SCLK_SDMMC_DRV		114
+#define SCLK_SDIO0_DRV		115
+#define SCLK_SDIO1_DRV		116
+#define SCLK_EMMC_DRV		117
+#define SCLK_SDMMC_SAMPLE	118
+#define SCLK_SDIO0_SAMPLE	119
+#define SCLK_SDIO1_SAMPLE	120
+#define SCLK_EMMC_SAMPLE	121
+#define SCLK_USBPHY480M_SRC	122
+#define SCLK_PVTM_CORE		123
+#define SCLK_PVTM_GPU		124
+
+#define SCLK_MAC_PLL		150
+#define SCLK_MAC		151
+#define SCLK_MACREF_OUT		152
+
+#define DCLK_VOP0		190
+#define DCLK_VOP1		191
+
+/* aclk gates */
+#define ACLK_GPU		192
+#define ACLK_DMAC1		193
+#define ACLK_DMAC2		194
+#define ACLK_MMU		195
+#define ACLK_GMAC		196
+#define ACLK_VOP0		197
+#define ACLK_VOP1		198
+#define ACLK_CRYPTO		199
+#define ACLK_RGA		200
+#define ACLK_RGA_NIU		201
+#define ACLK_IEP		202
+#define ACLK_VIO0_NIU		203
+#define ACLK_VIP		204
+#define ACLK_ISP		205
+#define ACLK_VIO1_NIU		206
+#define ACLK_HEVC		207
+#define ACLK_VCODEC		208
+#define ACLK_CPU		209
+#define ACLK_PERI		210
+
+/* pclk gates */
+#define PCLK_GPIO0		320
+#define PCLK_GPIO1		321
+#define PCLK_GPIO2		322
+#define PCLK_GPIO3		323
+#define PCLK_GPIO4		324
+#define PCLK_GPIO5		325
+#define PCLK_GPIO6		326
+#define PCLK_GPIO7		327
+#define PCLK_GPIO8		328
+#define PCLK_GRF		329
+#define PCLK_SGRF		330
+#define PCLK_PMU		331
+#define PCLK_I2C0		332
+#define PCLK_I2C1		333
+#define PCLK_I2C2		334
+#define PCLK_I2C3		335
+#define PCLK_I2C4		336
+#define PCLK_I2C5		337
+#define PCLK_SPI0		338
+#define PCLK_SPI1		339
+#define PCLK_SPI2		340
+#define PCLK_UART0		341
+#define PCLK_UART1		342
+#define PCLK_UART2		343
+#define PCLK_UART3		344
+#define PCLK_UART4		345
+#define PCLK_TSADC		346
+#define PCLK_SARADC		347
+#define PCLK_SIM		348
+#define PCLK_GMAC		349
+#define PCLK_PWM		350
+#define PCLK_RKPWM		351
+#define PCLK_PS2C		352
+#define PCLK_TIMER		353
+#define PCLK_TZPC		354
+#define PCLK_EDP_CTRL		355
+#define PCLK_MIPI_DSI0		356
+#define PCLK_MIPI_DSI1		357
+#define PCLK_MIPI_CSI		358
+#define PCLK_LVDS_PHY		359
+#define PCLK_HDMI_CTRL		360
+#define PCLK_VIO2_H2P		361
+#define PCLK_CPU		362
+#define PCLK_PERI		363
+#define PCLK_DDRUPCTL0		364
+#define PCLK_PUBL0		365
+#define PCLK_DDRUPCTL1		366
+#define PCLK_PUBL1		367
+#define PCLK_WDT		368
+
+/* hclk gates */
+#define HCLK_GPS		448
+#define HCLK_OTG0		449
+#define HCLK_USBHOST0		450
+#define HCLK_USBHOST1		451
+#define HCLK_HSIC		452
+#define HCLK_NANDC0		453
+#define HCLK_NANDC1		454
+#define HCLK_TSP		455
+#define HCLK_SDMMC		456
+#define HCLK_SDIO0		457
+#define HCLK_SDIO1		458
+#define HCLK_EMMC		459
+#define HCLK_HSADC		460
+#define HCLK_CRYPTO		461
+#define HCLK_I2S0		462
+#define HCLK_SPDIF		463
+#define HCLK_SPDIF8CH		464
+#define HCLK_VOP0		465
+#define HCLK_VOP1		466
+#define HCLK_ROM		467
+#define HCLK_IEP		468
+#define HCLK_ISP		469
+#define HCLK_RGA		470
+#define HCLK_VIO_AHB_ARBI	471
+#define HCLK_VIO_NIU		472
+#define HCLK_VIP		473
+#define HCLK_VIO2_H2P		474
+#define HCLK_HEVC		475
+#define HCLK_VCODEC		476
+#define HCLK_CPU		477
+#define HCLK_PERI		478
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0		0
+#define SRST_CORE1		1
+#define SRST_CORE2		2
+#define SRST_CORE3		3
+#define SRST_CORE0_PO		4
+#define SRST_CORE1_PO		5
+#define SRST_CORE2_PO		6
+#define SRST_CORE3_PO		7
+#define SRST_PDCORE_STRSYS	8
+#define SRST_PDBUS_STRSYS	9
+#define SRST_L2C		10
+#define SRST_TOPDBG		11
+#define SRST_CORE0_DBG		12
+#define SRST_CORE1_DBG		13
+#define SRST_CORE2_DBG		14
+#define SRST_CORE3_DBG		15
+
+#define SRST_PDBUG_AHB_ARBITOR	16
+#define SRST_EFUSE256		17
+#define SRST_DMAC1		18
+#define SRST_INTMEM		19
+#define SRST_ROM		20
+#define SRST_SPDIF8CH		21
+#define SRST_TIMER		22
+#define SRST_I2S0		23
+#define SRST_SPDIF		24
+#define SRST_TIMER0		25
+#define SRST_TIMER1		26
+#define SRST_TIMER2		27
+#define SRST_TIMER3		28
+#define SRST_TIMER4		29
+#define SRST_TIMER5		30
+#define SRST_EFUSE		31
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_GPIO3		35
+#define SRST_GPIO4		36
+#define SRST_GPIO5		37
+#define SRST_GPIO6		38
+#define SRST_GPIO7		39
+#define SRST_GPIO8		40
+#define SRST_I2C0		42
+#define SRST_I2C1		43
+#define SRST_I2C2		44
+#define SRST_I2C3		45
+#define SRST_I2C4		46
+#define SRST_I2C5		47
+
+#define SRST_DWPWM		48
+#define SRST_MMC_PERI		49
+#define SRST_PERIPH_MMU		50
+#define SRST_DAP		51
+#define SRST_DAP_SYS		52
+#define SRST_TPIU		53
+#define SRST_PMU_APB		54
+#define SRST_GRF		55
+#define SRST_PMU		56
+#define SRST_PERIPH_AXI		57
+#define SRST_PERIPH_AHB		58
+#define SRST_PERIPH_APB		59
+#define SRST_PERIPH_NIU		60
+#define SRST_PDPERI_AHB_ARBI	61
+#define SRST_EMEM		62
+#define SRST_USB_PERI		63
+
+#define SRST_DMAC2		64
+#define SRST_MAC		66
+#define SRST_GPS		67
+#define SRST_RKPWM		69
+#define SRST_CCP		71
+#define SRST_USBHOST0		72
+#define SRST_HSIC		73
+#define SRST_HSIC_AUX		74
+#define SRST_HSIC_PHY		75
+#define SRST_HSADC		76
+#define SRST_NANDC0		77
+#define SRST_NANDC1		78
+
+#define SRST_TZPC		80
+#define SRST_SPI0		83
+#define SRST_SPI1		84
+#define SRST_SPI2		85
+#define SRST_SARADC		87
+#define SRST_PDALIVE_NIU	88
+#define SRST_PDPMU_INTMEM	89
+#define SRST_PDPMU_NIU		90
+#define SRST_SGRF		91
+
+#define SRST_VIO_ARBI		96
+#define SRST_RGA_NIU		97
+#define SRST_VIO0_NIU_AXI	98
+#define SRST_VIO_NIU_AHB	99
+#define SRST_LCDC0_AXI		100
+#define SRST_LCDC0_AHB		101
+#define SRST_LCDC0_DCLK		102
+#define SRST_VIO1_NIU_AXI	103
+#define SRST_VIP		104
+#define SRST_RGA_CORE		105
+#define SRST_IEP_AXI		106
+#define SRST_IEP_AHB		107
+#define SRST_RGA_AXI		108
+#define SRST_RGA_AHB		109
+#define SRST_ISP		110
+#define SRST_EDP		111
+
+#define SRST_VCODEC_AXI		112
+#define SRST_VCODEC_AHB		113
+#define SRST_VIO_H2P		114
+#define SRST_MIPIDSI0		115
+#define SRST_MIPIDSI1		116
+#define SRST_MIPICSI		117
+#define SRST_LVDS_PHY		118
+#define SRST_LVDS_CON		119
+#define SRST_GPU		120
+#define SRST_HDMI		121
+#define SRST_CORE_PVTM		124
+#define SRST_GPU_PVTM		125
+
+#define SRST_MMC0		128
+#define SRST_SDIO0		129
+#define SRST_SDIO1		130
+#define SRST_EMMC		131
+#define SRST_USBOTG_AHB		132
+#define SRST_USBOTG_PHY		133
+#define SRST_USBOTG_CON		134
+#define SRST_USBHOST0_AHB	135
+#define SRST_USBHOST0_PHY	136
+#define SRST_USBHOST0_CON	137
+#define SRST_USBHOST1_AHB	138
+#define SRST_USBHOST1_PHY	139
+#define SRST_USBHOST1_CON	140
+#define SRST_USB_ADP		141
+#define SRST_ACC_EFUSE		142
+
+#define SRST_CORESIGHT		144
+#define SRST_PD_CORE_AHB_NOC	145
+#define SRST_PD_CORE_APB_NOC	146
+#define SRST_PD_CORE_MP_AXI	147
+#define SRST_GIC		148
+#define SRST_LCDC_PWM0		149
+#define SRST_LCDC_PWM1		150
+#define SRST_VIO0_H2P_BRG	151
+#define SRST_VIO1_H2P_BRG	152
+#define SRST_RGA_H2P_BRG	153
+#define SRST_HEVC		154
+#define SRST_TSADC		159
+
+#define SRST_DDRPHY0		160
+#define SRST_DDRPHY0_APB	161
+#define SRST_DDRCTRL0		162
+#define SRST_DDRCTRL0_APB	163
+#define SRST_DDRPHY0_CTRL	164
+#define SRST_DDRPHY1		165
+#define SRST_DDRPHY1_APB	166
+#define SRST_DDRCTRL1		167
+#define SRST_DDRCTRL1_APB	168
+#define SRST_DDRPHY1_CTRL	169
+#define SRST_DDRMSCH0		170
+#define SRST_DDRMSCH1		171
+#define SRST_CRYPTO		174
+#define SRST_C2C_HOST		175
+
+#define SRST_LCDC1_AXI		176
+#define SRST_LCDC1_AHB		177
+#define SRST_LCDC1_DCLK		178
+#define SRST_UART0		179
+#define SRST_UART1		180
+#define SRST_UART2		181
+#define SRST_UART3		182
+#define SRST_UART4		183
+#define SRST_SIMC		186
+#define SRST_PS2C		187
+#define SRST_TSP		188
+#define SRST_TSP_CLKIN0		189
+#define SRST_TSP_CLKIN1		190
+#define SRST_TSP_27M		191
diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h
new file mode 100644
index 0000000..cde61ed
--- /dev/null
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -0,0 +1,393 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
+
+/* core clocks */
+#define PLL_APLL		1
+#define PLL_DPLL		2
+#define PLL_CPLL		3
+#define PLL_GPLL		4
+#define PLL_NPLL		5
+#define ARMCLK			6
+
+/* sclk gates (special clocks) */
+#define SCLK_RTC32K		30
+#define SCLK_SDMMC_EXT		31
+#define SCLK_SPI		32
+#define SCLK_SDMMC		33
+#define SCLK_SDIO		34
+#define SCLK_EMMC		35
+#define SCLK_TSADC		36
+#define SCLK_SARADC		37
+#define SCLK_UART0		38
+#define SCLK_UART1		39
+#define SCLK_UART2		40
+#define SCLK_I2S0		41
+#define SCLK_I2S1		42
+#define SCLK_I2S2		43
+#define SCLK_I2S1_OUT		44
+#define SCLK_I2S2_OUT		45
+#define SCLK_SPDIF		46
+#define SCLK_TIMER0		47
+#define SCLK_TIMER1		48
+#define SCLK_TIMER2		49
+#define SCLK_TIMER3		50
+#define SCLK_TIMER4		51
+#define SCLK_TIMER5		52
+#define SCLK_WIFI		53
+#define SCLK_CIF_OUT		54
+#define SCLK_I2C0		55
+#define SCLK_I2C1		56
+#define SCLK_I2C2		57
+#define SCLK_I2C3		58
+#define SCLK_CRYPTO		59
+#define SCLK_PWM		60
+#define SCLK_PDM		61
+#define SCLK_EFUSE		62
+#define SCLK_OTP		63
+#define SCLK_DDRCLK		64
+#define SCLK_VDEC_CABAC		65
+#define SCLK_VDEC_CORE		66
+#define SCLK_VENC_DSP		67
+#define SCLK_VENC_CORE		68
+#define SCLK_RGA		69
+#define SCLK_HDMI_SFC		70
+#define SCLK_HDMI_CEC		71
+#define SCLK_USB3_REF		72
+#define SCLK_USB3_SUSPEND	73
+#define SCLK_SDMMC_DRV		74
+#define SCLK_SDIO_DRV		75
+#define SCLK_EMMC_DRV		76
+#define SCLK_SDMMC_EXT_DRV	77
+#define SCLK_SDMMC_SAMPLE	78
+#define SCLK_SDIO_SAMPLE	79
+#define SCLK_EMMC_SAMPLE	80
+#define SCLK_SDMMC_EXT_SAMPLE	81
+#define SCLK_VOP		82
+#define SCLK_MAC2PHY_RXTX	83
+#define SCLK_MAC2PHY_SRC	84
+#define SCLK_MAC2PHY_REF	85
+#define SCLK_MAC2PHY_OUT	86
+#define SCLK_MAC2IO_RX		87
+#define SCLK_MAC2IO_TX		88
+#define SCLK_MAC2IO_REFOUT	89
+#define SCLK_MAC2IO_REF		90
+#define SCLK_MAC2IO_OUT		91
+#define SCLK_TSP		92
+#define SCLK_HSADC_TSP		93
+#define SCLK_USB3PHY_REF	94
+#define SCLK_REF_USB3OTG	95
+#define SCLK_USB3OTG_REF	96
+#define SCLK_USB3OTG_SUSPEND	97
+#define SCLK_REF_USB3OTG_SRC	98
+#define SCLK_MAC2IO_SRC		99
+#define SCLK_MAC2IO		100
+#define SCLK_MAC2PHY		101
+#define SCLK_MAC2IO_EXT		102
+
+/* dclk gates */
+#define DCLK_LCDC		180
+#define DCLK_HDMIPHY		181
+#define HDMIPHY			182
+#define USB480M			183
+#define DCLK_LCDC_SRC		184
+
+/* aclk gates */
+#define ACLK_AXISRAM		190
+#define ACLK_VOP_PRE		191
+#define ACLK_USB3OTG		192
+#define ACLK_RGA_PRE		193
+#define ACLK_DMAC		194
+#define ACLK_GPU		195
+#define ACLK_BUS_PRE		196
+#define ACLK_PERI_PRE		197
+#define ACLK_RKVDEC_PRE		198
+#define ACLK_RKVDEC		199
+#define ACLK_RKVENC		200
+#define ACLK_VPU_PRE		201
+#define ACLK_VIO_PRE		202
+#define ACLK_VPU		203
+#define ACLK_VIO		204
+#define ACLK_VOP		205
+#define ACLK_GMAC		206
+#define ACLK_H265		207
+#define ACLK_H264		208
+#define ACLK_MAC2PHY		209
+#define ACLK_MAC2IO		210
+#define ACLK_DCF		211
+#define ACLK_TSP		212
+#define ACLK_PERI		213
+#define ACLK_RGA		214
+#define ACLK_IEP		215
+#define ACLK_CIF		216
+#define ACLK_HDCP		217
+
+/* pclk gates */
+#define PCLK_GPIO0		300
+#define PCLK_GPIO1		301
+#define PCLK_GPIO2		302
+#define PCLK_GPIO3		303
+#define PCLK_GRF		304
+#define PCLK_I2C0		305
+#define PCLK_I2C1		306
+#define PCLK_I2C2		307
+#define PCLK_I2C3		308
+#define PCLK_SPI		309
+#define PCLK_UART0		310
+#define PCLK_UART1		311
+#define PCLK_UART2		312
+#define PCLK_TSADC		313
+#define PCLK_PWM		314
+#define PCLK_TIMER		315
+#define PCLK_BUS_PRE		316
+#define PCLK_PERI_PRE		317
+#define PCLK_HDMI_CTRL		318
+#define PCLK_HDMI_PHY		319
+#define PCLK_GMAC		320
+#define PCLK_H265		321
+#define PCLK_MAC2PHY		322
+#define PCLK_MAC2IO		323
+#define PCLK_USB3PHY_OTG	324
+#define PCLK_USB3PHY_PIPE	325
+#define PCLK_USB3_GRF		326
+#define PCLK_USB2_GRF		327
+#define PCLK_HDMIPHY		328
+#define PCLK_DDR		329
+#define PCLK_PERI		330
+#define PCLK_HDMI		331
+#define PCLK_HDCP		332
+#define PCLK_DCF		333
+#define PCLK_SARADC		334
+
+/* hclk gates */
+#define HCLK_PERI		408
+#define HCLK_TSP		409
+#define HCLK_GMAC		410
+#define HCLK_I2S0_8CH		411
+#define HCLK_I2S1_8CH		413
+#define HCLK_I2S2_2CH		413
+#define HCLK_SPDIF_8CH		414
+#define HCLK_VOP		415
+#define HCLK_NANDC		416
+#define HCLK_SDMMC		417
+#define HCLK_SDIO		418
+#define HCLK_EMMC		419
+#define HCLK_SDMMC_EXT		420
+#define HCLK_RKVDEC_PRE		421
+#define HCLK_RKVDEC		422
+#define HCLK_RKVENC		423
+#define HCLK_VPU_PRE		424
+#define HCLK_VIO_PRE		425
+#define HCLK_VPU		426
+#define HCLK_VIO		427
+#define HCLK_BUS_PRE		428
+#define HCLK_PERI_PRE		429
+#define HCLK_H264		430
+#define HCLK_CIF		431
+#define HCLK_OTG_PMU		432
+#define HCLK_OTG		433
+#define HCLK_HOST0		434
+#define HCLK_HOST0_ARB		435
+#define HCLK_CRYPTO_MST		436
+#define HCLK_CRYPTO_SLV		437
+#define HCLK_PDM		438
+#define HCLK_IEP		439
+#define HCLK_RGA		440
+#define HCLK_HDCP		441
+
+#define CLK_NR_CLKS		(HCLK_HDCP + 1)
+
+#define CLKGRF_NR_CLKS		(SCLK_MAC2PHY + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO		0
+#define SRST_CORE1_PO		1
+#define SRST_CORE2_PO		2
+#define SRST_CORE3_PO		3
+#define SRST_CORE0		4
+#define SRST_CORE1		5
+#define SRST_CORE2		6
+#define SRST_CORE3		7
+#define SRST_CORE0_DBG		8
+#define SRST_CORE1_DBG		9
+#define SRST_CORE2_DBG		10
+#define SRST_CORE3_DBG		11
+#define SRST_TOPDBG		12
+#define SRST_CORE_NIU		13
+#define SRST_STRC_A		14
+#define SRST_L2C		15
+
+#define SRST_A53_GIC		18
+#define SRST_DAP		19
+#define SRST_PMU_P		21
+#define SRST_EFUSE		22
+#define SRST_BUSSYS_H		23
+#define SRST_BUSSYS_P		24
+#define SRST_SPDIF		25
+#define SRST_INTMEM		26
+#define SRST_ROM		27
+#define SRST_GPIO0		28
+#define SRST_GPIO1		29
+#define SRST_GPIO2		30
+#define SRST_GPIO3		31
+
+#define SRST_I2S0		32
+#define SRST_I2S1		33
+#define SRST_I2S2		34
+#define SRST_I2S0_H		35
+#define SRST_I2S1_H		36
+#define SRST_I2S2_H		37
+#define SRST_UART0		38
+#define SRST_UART1		39
+#define SRST_UART2		40
+#define SRST_UART0_P		41
+#define SRST_UART1_P		42
+#define SRST_UART2_P		43
+#define SRST_I2C0		44
+#define SRST_I2C1		45
+#define SRST_I2C2		46
+#define SRST_I2C3		47
+
+#define SRST_I2C0_P		48
+#define SRST_I2C1_P		49
+#define SRST_I2C2_P		50
+#define SRST_I2C3_P		51
+#define SRST_EFUSE_SE_P		52
+#define SRST_EFUSE_NS_P		53
+#define SRST_PWM0		54
+#define SRST_PWM0_P		55
+#define SRST_DMA		56
+#define SRST_TSP_A		57
+#define SRST_TSP_H		58
+#define SRST_TSP		59
+#define SRST_TSP_HSADC		60
+#define SRST_DCF_A		61
+#define SRST_DCF_P		62
+
+#define SRST_SCR		64
+#define SRST_SPI		65
+#define SRST_TSADC		66
+#define SRST_TSADC_P		67
+#define SRST_CRYPTO		68
+#define SRST_SGRF		69
+#define SRST_GRF		70
+#define SRST_USB_GRF		71
+#define SRST_TIMER_6CH_P	72
+#define SRST_TIMER0		73
+#define SRST_TIMER1		74
+#define SRST_TIMER2		75
+#define SRST_TIMER3		76
+#define SRST_TIMER4		77
+#define SRST_TIMER5		78
+#define SRST_USB3GRF		79
+
+#define SRST_PHYNIU		80
+#define SRST_HDMIPHY		81
+#define SRST_VDAC		82
+#define SRST_ACODEC_p		83
+#define SRST_SARADC		85
+#define SRST_SARADC_P		86
+#define SRST_GRF_DDR		87
+#define SRST_DFIMON		88
+#define SRST_MSCH		89
+#define SRST_DDRMSCH		91
+#define SRST_DDRCTRL		92
+#define SRST_DDRCTRL_P		93
+#define SRST_DDRPHY		94
+#define SRST_DDRPHY_P		95
+
+#define SRST_GMAC_NIU_A		96
+#define SRST_GMAC_NIU_P		97
+#define SRST_GMAC2PHY_A		98
+#define SRST_GMAC2IO_A		99
+#define SRST_MACPHY		100
+#define SRST_OTP_PHY		101
+#define SRST_GPU_A		102
+#define SRST_GPU_NIU_A		103
+#define SRST_SDMMCEXT		104
+#define SRST_PERIPH_NIU_A	105
+#define SRST_PERIHP_NIU_H	106
+#define SRST_PERIHP_P		107
+#define SRST_PERIPHSYS_H	108
+#define SRST_MMC0		109
+#define SRST_SDIO		110
+#define SRST_EMMC		111
+
+#define SRST_USB2OTG_H		112
+#define SRST_USB2OTG		113
+#define SRST_USB2OTG_ADP	114
+#define SRST_USB2HOST_H		115
+#define SRST_USB2HOST_ARB	116
+#define SRST_USB2HOST_AUX	117
+#define SRST_USB2HOST_EHCIPHY	118
+#define SRST_USB2HOST_UTMI	119
+#define SRST_USB3OTG		120
+#define SRST_USBPOR		121
+#define SRST_USB2OTG_UTMI	122
+#define SRST_USB2HOST_PHY_UTMI	123
+#define SRST_USB3OTG_UTMI	124
+#define SRST_USB3PHY_U2		125
+#define SRST_USB3PHY_U3		126
+#define SRST_USB3PHY_PIPE	127
+
+#define SRST_VIO_A		128
+#define SRST_VIO_BUS_H		129
+#define SRST_VIO_H2P_H		130
+#define SRST_VIO_ARBI_H		131
+#define SRST_VOP_NIU_A		132
+#define SRST_VOP_A		133
+#define SRST_VOP_H		134
+#define SRST_VOP_D		135
+#define SRST_RGA		136
+#define SRST_RGA_NIU_A		137
+#define SRST_RGA_A		138
+#define SRST_RGA_H		139
+#define SRST_IEP_A		140
+#define SRST_IEP_H		141
+#define SRST_HDMI		142
+#define SRST_HDMI_P		143
+
+#define SRST_HDCP_A		144
+#define SRST_HDCP		145
+#define SRST_HDCP_H		146
+#define SRST_CIF_A		147
+#define SRST_CIF_H		148
+#define SRST_CIF_P		149
+#define SRST_OTP_P		150
+#define SRST_OTP_SBPI		151
+#define SRST_OTP_USER		152
+#define SRST_DDRCTRL_A		153
+#define SRST_DDRSTDY_P		154
+#define SRST_DDRSTDY		155
+#define SRST_PDM_H		156
+#define SRST_PDM		157
+#define SRST_USB3PHY_OTG_P	158
+#define SRST_USB3PHY_PIPE_P	159
+
+#define SRST_VCODEC_A		160
+#define SRST_VCODEC_NIU_A	161
+#define SRST_VCODEC_H		162
+#define SRST_VCODEC_NIU_H	163
+#define SRST_VDEC_A		164
+#define SRST_VDEC_NIU_A		165
+#define SRST_VDEC_H		166
+#define SRST_VDEC_NIU_H		167
+#define SRST_VDEC_CORE		168
+#define SRST_VDEC_CABAC		169
+#define SRST_DDRPHYDIV		175
+
+#define SRST_RKVENC_NIU_A	176
+#define SRST_RKVENC_NIU_H	177
+#define SRST_RKVENC_H265_A	178
+#define SRST_RKVENC_H265_P	179
+#define SRST_RKVENC_H265_CORE	180
+#define SRST_RKVENC_H265_DSP	181
+#define SRST_RKVENC_H264_A	182
+#define SRST_RKVENC_H264_H	183
+#define SRST_RKVENC_INTMEM	184
+
+#endif
diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
new file mode 100644
index 0000000..9c5dd9b
--- /dev/null
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
+
+/* core clocks */
+#define PLL_APLLB		1
+#define PLL_APLLL		2
+#define PLL_DPLL		3
+#define PLL_CPLL		4
+#define PLL_GPLL		5
+#define PLL_NPLL		6
+#define ARMCLKB			7
+#define ARMCLKL			8
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU_CORE		64
+#define SCLK_SPI0		65
+#define SCLK_SPI1		66
+#define SCLK_SPI2		67
+#define SCLK_SDMMC		68
+#define SCLK_SDIO0		69
+#define SCLK_EMMC		71
+#define SCLK_TSADC		72
+#define SCLK_SARADC		73
+#define SCLK_NANDC0		75
+#define SCLK_UART0		77
+#define SCLK_UART1		78
+#define SCLK_UART2		79
+#define SCLK_UART3		80
+#define SCLK_UART4		81
+#define SCLK_I2S_8CH		82
+#define SCLK_SPDIF_8CH		83
+#define SCLK_I2S_2CH		84
+#define SCLK_TIMER0		85
+#define SCLK_TIMER1		86
+#define SCLK_TIMER2		87
+#define SCLK_TIMER3		88
+#define SCLK_TIMER4		89
+#define SCLK_TIMER5		90
+#define SCLK_TIMER6		91
+#define SCLK_OTGPHY0		93
+#define SCLK_OTG_ADP		96
+#define SCLK_HSICPHY480M	97
+#define SCLK_HSICPHY12M		98
+#define SCLK_MACREF		99
+#define SCLK_VOP0_PWM		100
+#define SCLK_MAC_RX		102
+#define SCLK_MAC_TX		103
+#define SCLK_EDP_24M		104
+#define SCLK_EDP		105
+#define SCLK_RGA		106
+#define SCLK_ISP		107
+#define SCLK_HDCP		108
+#define SCLK_HDMI_HDCP		109
+#define SCLK_HDMI_CEC		110
+#define SCLK_HEVC_CABAC		111
+#define SCLK_HEVC_CORE		112
+#define SCLK_I2S_8CH_OUT	113
+#define SCLK_SDMMC_DRV		114
+#define SCLK_SDIO0_DRV		115
+#define SCLK_EMMC_DRV		117
+#define SCLK_SDMMC_SAMPLE	118
+#define SCLK_SDIO0_SAMPLE	119
+#define SCLK_EMMC_SAMPLE	121
+#define SCLK_USBPHY480M		122
+#define SCLK_PVTM_CORE		123
+#define SCLK_PVTM_GPU		124
+#define SCLK_PVTM_PMU		125
+#define SCLK_SFC		126
+#define SCLK_MAC		127
+#define SCLK_MACREF_OUT		128
+
+#define DCLK_VOP		190
+#define MCLK_CRYPTO		191
+
+/* aclk gates */
+#define ACLK_GPU_MEM		192
+#define ACLK_GPU_CFG		193
+#define ACLK_DMAC_BUS		194
+#define ACLK_DMAC_PERI		195
+#define ACLK_PERI_MMU		196
+#define ACLK_GMAC		197
+#define ACLK_VOP		198
+#define ACLK_VOP_IEP		199
+#define ACLK_RGA		200
+#define ACLK_HDCP		201
+#define ACLK_IEP		202
+#define ACLK_VIO0_NOC		203
+#define ACLK_VIP		204
+#define ACLK_ISP		205
+#define ACLK_VIO1_NOC		206
+#define ACLK_VIDEO		208
+#define ACLK_BUS		209
+#define ACLK_PERI		210
+
+/* pclk gates */
+#define PCLK_GPIO0		320
+#define PCLK_GPIO1		321
+#define PCLK_GPIO2		322
+#define PCLK_GPIO3		323
+#define PCLK_PMUGRF		324
+#define PCLK_MAILBOX		325
+#define PCLK_GRF		329
+#define PCLK_SGRF		330
+#define PCLK_PMU		331
+#define PCLK_I2C0		332
+#define PCLK_I2C1		333
+#define PCLK_I2C2		334
+#define PCLK_I2C3		335
+#define PCLK_I2C4		336
+#define PCLK_I2C5		337
+#define PCLK_SPI0		338
+#define PCLK_SPI1		339
+#define PCLK_SPI2		340
+#define PCLK_UART0		341
+#define PCLK_UART1		342
+#define PCLK_UART2		343
+#define PCLK_UART3		344
+#define PCLK_UART4		345
+#define PCLK_TSADC		346
+#define PCLK_SARADC		347
+#define PCLK_SIM		348
+#define PCLK_GMAC		349
+#define PCLK_PWM0		350
+#define PCLK_PWM1		351
+#define PCLK_TIMER0		353
+#define PCLK_TIMER1		354
+#define PCLK_EDP_CTRL		355
+#define PCLK_MIPI_DSI0		356
+#define PCLK_MIPI_CSI		358
+#define PCLK_HDCP		359
+#define PCLK_HDMI_CTRL		360
+#define PCLK_VIO_H2P		361
+#define PCLK_BUS		362
+#define PCLK_PERI		363
+#define PCLK_DDRUPCTL		364
+#define PCLK_DDRPHY		365
+#define PCLK_ISP		366
+#define PCLK_VIP		367
+#define PCLK_WDT		368
+
+/* hclk gates */
+#define HCLK_SFC		448
+#define HCLK_OTG0		449
+#define HCLK_HOST0		450
+#define HCLK_HOST1		451
+#define HCLK_HSIC		452
+#define HCLK_NANDC0		453
+#define HCLK_TSP		455
+#define HCLK_SDMMC		456
+#define HCLK_SDIO0		457
+#define HCLK_EMMC		459
+#define HCLK_HSADC		460
+#define HCLK_CRYPTO		461
+#define HCLK_I2S_2CH		462
+#define HCLK_I2S_8CH		463
+#define HCLK_SPDIF		464
+#define HCLK_VOP		465
+#define HCLK_ROM		467
+#define HCLK_IEP		468
+#define HCLK_ISP		469
+#define HCLK_RGA		470
+#define HCLK_VIO_AHB_ARBI	471
+#define HCLK_VIO_NOC		472
+#define HCLK_VIP		473
+#define HCLK_VIO_H2P		474
+#define HCLK_VIO_HDCPMMU	475
+#define HCLK_VIDEO		476
+#define HCLK_BUS		477
+#define HCLK_PERI		478
+
+#define CLK_NR_CLKS		(HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE_B0		0
+#define SRST_CORE_B1		1
+#define SRST_CORE_B2		2
+#define SRST_CORE_B3		3
+#define SRST_CORE_B0_PO		4
+#define SRST_CORE_B1_PO		5
+#define SRST_CORE_B2_PO		6
+#define SRST_CORE_B3_PO		7
+#define SRST_L2_B		8
+#define SRST_ADB_B		9
+#define SRST_PD_CORE_B_NIU	10
+#define SRST_PDBUS_STRSYS	11
+#define SRST_SOCDBG_B		14
+#define SRST_CORE_B_DBG		15
+
+#define SRST_DMAC1		18
+#define SRST_INTMEM		19
+#define SRST_ROM		20
+#define SRST_SPDIF8CH		21
+#define SRST_I2S8CH		23
+#define SRST_MAILBOX		24
+#define SRST_I2S2CH		25
+#define SRST_EFUSE_256		26
+#define SRST_MCU_SYS		28
+#define SRST_MCU_PO		29
+#define SRST_MCU_NOC		30
+#define SRST_EFUSE		31
+
+#define SRST_GPIO0		32
+#define SRST_GPIO1		33
+#define SRST_GPIO2		34
+#define SRST_GPIO3		35
+#define SRST_GPIO4		36
+#define SRST_PMUGRF		41
+#define SRST_I2C0		42
+#define SRST_I2C1		43
+#define SRST_I2C2		44
+#define SRST_I2C3		45
+#define SRST_I2C4		46
+#define SRST_I2C5		47
+
+#define SRST_DWPWM		48
+#define SRST_MMC_PERI		49
+#define SRST_PERIPH_MMU		50
+#define SRST_GRF		55
+#define SRST_PMU		56
+#define SRST_PERIPH_AXI		57
+#define SRST_PERIPH_AHB		58
+#define SRST_PERIPH_APB		59
+#define SRST_PERIPH_NIU		60
+#define SRST_PDPERI_AHB_ARBI	61
+#define SRST_EMEM		62
+#define SRST_USB_PERI		63
+
+#define SRST_DMAC2		64
+#define SRST_MAC		66
+#define SRST_GPS		67
+#define SRST_RKPWM		69
+#define SRST_USBHOST0		72
+#define SRST_HSIC		73
+#define SRST_HSIC_AUX		74
+#define SRST_HSIC_PHY		75
+#define SRST_HSADC		76
+#define SRST_NANDC0		77
+#define SRST_SFC		79
+
+#define SRST_SPI0		83
+#define SRST_SPI1		84
+#define SRST_SPI2		85
+#define SRST_SARADC		87
+#define SRST_PDALIVE_NIU	88
+#define SRST_PDPMU_INTMEM	89
+#define SRST_PDPMU_NIU		90
+#define SRST_SGRF		91
+
+#define SRST_VIO_ARBI		96
+#define SRST_RGA_NIU		97
+#define SRST_VIO0_NIU_AXI	98
+#define SRST_VIO_NIU_AHB	99
+#define SRST_LCDC0_AXI		100
+#define SRST_LCDC0_AHB		101
+#define SRST_LCDC0_DCLK		102
+#define SRST_VIP		104
+#define SRST_RGA_CORE		105
+#define SRST_IEP_AXI		106
+#define SRST_IEP_AHB		107
+#define SRST_RGA_AXI		108
+#define SRST_RGA_AHB		109
+#define SRST_ISP		110
+#define SRST_EDP_24M		111
+
+#define SRST_VIDEO_AXI		112
+#define SRST_VIDEO_AHB		113
+#define SRST_MIPIDPHYTX		114
+#define SRST_MIPIDSI0		115
+#define SRST_MIPIDPHYRX		116
+#define SRST_MIPICSI		117
+#define SRST_GPU		120
+#define SRST_HDMI		121
+#define SRST_EDP		122
+#define SRST_PMU_PVTM		123
+#define SRST_CORE_PVTM		124
+#define SRST_GPU_PVTM		125
+#define SRST_GPU_SYS		126
+#define SRST_GPU_MEM_NIU	127
+
+#define SRST_MMC0		128
+#define SRST_SDIO0		129
+#define SRST_EMMC		131
+#define SRST_USBOTG_AHB		132
+#define SRST_USBOTG_PHY		133
+#define SRST_USBOTG_CON		134
+#define SRST_USBHOST0_AHB	135
+#define SRST_USBHOST0_PHY	136
+#define SRST_USBHOST0_CON	137
+#define SRST_USBOTG_UTMI	138
+#define SRST_USBHOST1_UTMI	139
+#define SRST_USB_ADP		141
+
+#define SRST_CORESIGHT		144
+#define SRST_PD_CORE_AHB_NOC	145
+#define SRST_PD_CORE_APB_NOC	146
+#define SRST_GIC		148
+#define SRST_LCDC_PWM0		149
+#define SRST_RGA_H2P_BRG	153
+#define SRST_VIDEO		154
+#define SRST_GPU_CFG_NIU	157
+#define SRST_TSADC		159
+
+#define SRST_DDRPHY0		160
+#define SRST_DDRPHY0_APB	161
+#define SRST_DDRCTRL0		162
+#define SRST_DDRCTRL0_APB	163
+#define SRST_VIDEO_NIU		165
+#define SRST_VIDEO_NIU_AHB	167
+#define SRST_DDRMSCH0		170
+#define SRST_PDBUS_AHB		173
+#define SRST_CRYPTO		174
+
+#define SRST_UART0		179
+#define SRST_UART1		180
+#define SRST_UART2		181
+#define SRST_UART3		182
+#define SRST_UART4		183
+#define SRST_SIMC		186
+#define SRST_TSP		188
+#define SRST_TSP_CLKIN0		189
+
+#define SRST_CORE_L0		192
+#define SRST_CORE_L1		193
+#define SRST_CORE_L2		194
+#define SRST_CORE_L3		195
+#define SRST_CORE_L0_PO		195
+#define SRST_CORE_L1_PO		197
+#define SRST_CORE_L2_PO		198
+#define SRST_CORE_L3_PO		199
+#define SRST_L2_L		200
+#define SRST_ADB_L		201
+#define SRST_PD_CORE_L_NIU	202
+#define SRST_CCI_SYS		203
+#define SRST_CCI_DDR		204
+#define SRST_CCI		205
+#define SRST_SOCDBG_L		206
+#define SRST_CORE_L_DBG		207
+
+#define SRST_CORE_B0_NC		208
+#define SRST_CORE_B0_PO_NC	209
+#define SRST_L2_B_NC		210
+#define SRST_ADB_B_NC		211
+#define SRST_PD_CORE_B_NIU_NC	212
+#define SRST_PDBUS_STRSYS_NC	213
+#define SRST_CORE_L0_NC		214
+#define SRST_CORE_L0_PO_NC	215
+#define SRST_L2_L_NC		216
+#define SRST_ADB_L_NC		217
+#define SRST_PD_CORE_L_NIU_NC	218
+#define SRST_CCI_SYS_NC		219
+#define SRST_CCI_DDR_NC		220
+#define SRST_CCI_NC		221
+#define SRST_TRACE_NC		222
+
+#define SRST_TIMER00		224
+#define SRST_TIMER01		225
+#define SRST_TIMER02		226
+#define SRST_TIMER03		227
+#define SRST_TIMER04		228
+#define SRST_TIMER05		229
+#define SRST_TIMER10		230
+#define SRST_TIMER11		231
+#define SRST_TIMER12		232
+#define SRST_TIMER13		233
+#define SRST_TIMER14		234
+#define SRST_TIMER15		235
+#define SRST_TIMER0_APB		236
+#define SRST_TIMER1_APB		237
+
+#endif
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
new file mode 100644
index 0000000..211faf8
--- /dev/null
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -0,0 +1,749 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
+
+/* core clocks */
+#define PLL_APLLL			1
+#define PLL_APLLB			2
+#define PLL_DPLL			3
+#define PLL_CPLL			4
+#define PLL_GPLL			5
+#define PLL_NPLL			6
+#define PLL_VPLL			7
+#define ARMCLKL				8
+#define ARMCLKB				9
+
+/* sclk gates (special clocks) */
+#define SCLK_I2C1			65
+#define SCLK_I2C2			66
+#define SCLK_I2C3			67
+#define SCLK_I2C5			68
+#define SCLK_I2C6			69
+#define SCLK_I2C7			70
+#define SCLK_SPI0			71
+#define SCLK_SPI1			72
+#define SCLK_SPI2			73
+#define SCLK_SPI4			74
+#define SCLK_SPI5			75
+#define SCLK_SDMMC			76
+#define SCLK_SDIO			77
+#define SCLK_EMMC			78
+#define SCLK_TSADC			79
+#define SCLK_SARADC			80
+#define SCLK_UART0			81
+#define SCLK_UART1			82
+#define SCLK_UART2			83
+#define SCLK_UART3			84
+#define SCLK_SPDIF_8CH			85
+#define SCLK_I2S0_8CH			86
+#define SCLK_I2S1_8CH			87
+#define SCLK_I2S2_8CH			88
+#define SCLK_I2S_8CH_OUT		89
+#define SCLK_TIMER00			90
+#define SCLK_TIMER01			91
+#define SCLK_TIMER02			92
+#define SCLK_TIMER03			93
+#define SCLK_TIMER04			94
+#define SCLK_TIMER05			95
+#define SCLK_TIMER06			96
+#define SCLK_TIMER07			97
+#define SCLK_TIMER08			98
+#define SCLK_TIMER09			99
+#define SCLK_TIMER10			100
+#define SCLK_TIMER11			101
+#define SCLK_MACREF			102
+#define SCLK_MAC_RX			103
+#define SCLK_MAC_TX			104
+#define SCLK_MAC			105
+#define SCLK_MACREF_OUT			106
+#define SCLK_VOP0_PWM			107
+#define SCLK_VOP1_PWM			108
+#define SCLK_RGA_CORE			109
+#define SCLK_ISP0			110
+#define SCLK_ISP1			111
+#define SCLK_HDMI_CEC			112
+#define SCLK_HDMI_SFR			113
+#define SCLK_DP_CORE			114
+#define SCLK_PVTM_CORE_L		115
+#define SCLK_PVTM_CORE_B		116
+#define SCLK_PVTM_GPU			117
+#define SCLK_PVTM_DDR			118
+#define SCLK_MIPIDPHY_REF		119
+#define SCLK_MIPIDPHY_CFG		120
+#define SCLK_HSICPHY			121
+#define SCLK_USBPHY480M			122
+#define SCLK_USB2PHY0_REF		123
+#define SCLK_USB2PHY1_REF		124
+#define SCLK_UPHY0_TCPDPHY_REF		125
+#define SCLK_UPHY0_TCPDCORE		126
+#define SCLK_UPHY1_TCPDPHY_REF		127
+#define SCLK_UPHY1_TCPDCORE		128
+#define SCLK_USB3OTG0_REF		129
+#define SCLK_USB3OTG1_REF		130
+#define SCLK_USB3OTG0_SUSPEND		131
+#define SCLK_USB3OTG1_SUSPEND		132
+#define SCLK_CRYPTO0			133
+#define SCLK_CRYPTO1			134
+#define SCLK_CCI_TRACE			135
+#define SCLK_CS				136
+#define SCLK_CIF_OUT			137
+#define SCLK_PCIEPHY_REF		138
+#define SCLK_PCIE_CORE			139
+#define SCLK_M0_PERILP			140
+#define SCLK_M0_PERILP_DEC		141
+#define SCLK_CM0S			142
+#define SCLK_DBG_NOC			143
+#define SCLK_DBG_PD_CORE_B		144
+#define SCLK_DBG_PD_CORE_L		145
+#define SCLK_DFIMON0_TIMER		146
+#define SCLK_DFIMON1_TIMER		147
+#define SCLK_INTMEM0			148
+#define SCLK_INTMEM1			149
+#define SCLK_INTMEM2			150
+#define SCLK_INTMEM3			151
+#define SCLK_INTMEM4			152
+#define SCLK_INTMEM5			153
+#define SCLK_SDMMC_DRV			154
+#define SCLK_SDMMC_SAMPLE		155
+#define SCLK_SDIO_DRV			156
+#define SCLK_SDIO_SAMPLE		157
+#define SCLK_VDU_CORE			158
+#define SCLK_VDU_CA			159
+#define SCLK_PCIE_PM			160
+#define SCLK_SPDIF_REC_DPTX		161
+#define SCLK_DPHY_PLL			162
+#define SCLK_DPHY_TX0_CFG		163
+#define SCLK_DPHY_TX1RX1_CFG		164
+#define SCLK_DPHY_RX0_CFG		165
+#define SCLK_RMII_SRC			166
+#define SCLK_PCIEPHY_REF100M		167
+#define SCLK_USBPHY0_480M_SRC		168
+#define SCLK_USBPHY1_480M_SRC		169
+#define SCLK_DDRCLK			170
+#define SCLK_TESTOUT2			171
+
+#define DCLK_VOP0			180
+#define DCLK_VOP1			181
+#define DCLK_VOP0_DIV			182
+#define DCLK_VOP1_DIV			183
+#define DCLK_M0_PERILP			184
+
+#define FCLK_CM0S			190
+
+/* aclk gates */
+#define ACLK_PERIHP			192
+#define ACLK_PERIHP_NOC			193
+#define ACLK_PERILP0			194
+#define ACLK_PERILP0_NOC		195
+#define ACLK_PERF_PCIE			196
+#define ACLK_PCIE			197
+#define ACLK_INTMEM			198
+#define ACLK_TZMA			199
+#define ACLK_DCF			200
+#define ACLK_CCI			201
+#define ACLK_CCI_NOC0			202
+#define ACLK_CCI_NOC1			203
+#define ACLK_CCI_GRF			204
+#define ACLK_CENTER			205
+#define ACLK_CENTER_MAIN_NOC		206
+#define ACLK_CENTER_PERI_NOC		207
+#define ACLK_GPU			208
+#define ACLK_PERF_GPU			209
+#define ACLK_GPU_GRF			210
+#define ACLK_DMAC0_PERILP		211
+#define ACLK_DMAC1_PERILP		212
+#define ACLK_GMAC			213
+#define ACLK_GMAC_NOC			214
+#define ACLK_PERF_GMAC			215
+#define ACLK_VOP0_NOC			216
+#define ACLK_VOP0			217
+#define ACLK_VOP1_NOC			218
+#define ACLK_VOP1			219
+#define ACLK_RGA			220
+#define ACLK_RGA_NOC			221
+#define ACLK_HDCP			222
+#define ACLK_HDCP_NOC			223
+#define ACLK_HDCP22			224
+#define ACLK_IEP			225
+#define ACLK_IEP_NOC			226
+#define ACLK_VIO			227
+#define ACLK_VIO_NOC			228
+#define ACLK_ISP0			229
+#define ACLK_ISP1			230
+#define ACLK_ISP0_NOC			231
+#define ACLK_ISP1_NOC			232
+#define ACLK_ISP0_WRAPPER		233
+#define ACLK_ISP1_WRAPPER		234
+#define ACLK_VCODEC			235
+#define ACLK_VCODEC_NOC			236
+#define ACLK_VDU			237
+#define ACLK_VDU_NOC			238
+#define ACLK_PERI			239
+#define ACLK_EMMC			240
+#define ACLK_EMMC_CORE			241
+#define ACLK_EMMC_NOC			242
+#define ACLK_EMMC_GRF			243
+#define ACLK_USB3			244
+#define ACLK_USB3_NOC			245
+#define ACLK_USB3OTG0			246
+#define ACLK_USB3OTG1			247
+#define ACLK_USB3_RKSOC_AXI_PERF	248
+#define ACLK_USB3_GRF			249
+#define ACLK_GIC			250
+#define ACLK_GIC_NOC			251
+#define ACLK_GIC_ADB400_CORE_L_2_GIC	252
+#define ACLK_GIC_ADB400_CORE_B_2_GIC	253
+#define ACLK_GIC_ADB400_GIC_2_CORE_L	254
+#define ACLK_GIC_ADB400_GIC_2_CORE_B	255
+#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
+#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
+#define ACLK_ADB400M_PD_CORE_L		258
+#define ACLK_ADB400M_PD_CORE_B		259
+#define ACLK_PERF_CORE_L		260
+#define ACLK_PERF_CORE_B		261
+#define ACLK_GIC_PRE			262
+#define ACLK_VOP0_PRE			263
+#define ACLK_VOP1_PRE			264
+
+/* pclk gates */
+#define PCLK_PERIHP			320
+#define PCLK_PERIHP_NOC			321
+#define PCLK_PERILP0			322
+#define PCLK_PERILP1			323
+#define PCLK_PERILP1_NOC		324
+#define PCLK_PERILP_SGRF		325
+#define PCLK_PERIHP_GRF			326
+#define PCLK_PCIE			327
+#define PCLK_SGRF			328
+#define PCLK_INTR_ARB			329
+#define PCLK_CENTER_MAIN_NOC		330
+#define PCLK_CIC			331
+#define PCLK_COREDBG_B			332
+#define PCLK_COREDBG_L			333
+#define PCLK_DBG_CXCS_PD_CORE_B		334
+#define PCLK_DCF			335
+#define PCLK_GPIO2			336
+#define PCLK_GPIO3			337
+#define PCLK_GPIO4			338
+#define PCLK_GRF			339
+#define PCLK_HSICPHY			340
+#define PCLK_I2C1			341
+#define PCLK_I2C2			342
+#define PCLK_I2C3			343
+#define PCLK_I2C5			344
+#define PCLK_I2C6			345
+#define PCLK_I2C7			346
+#define PCLK_SPI0			347
+#define PCLK_SPI1			348
+#define PCLK_SPI2			349
+#define PCLK_SPI4			350
+#define PCLK_SPI5			351
+#define PCLK_UART0			352
+#define PCLK_UART1			353
+#define PCLK_UART2			354
+#define PCLK_UART3			355
+#define PCLK_TSADC			356
+#define PCLK_SARADC			357
+#define PCLK_GMAC			358
+#define PCLK_GMAC_NOC			359
+#define PCLK_TIMER0			360
+#define PCLK_TIMER1			361
+#define PCLK_EDP			362
+#define PCLK_EDP_NOC			363
+#define PCLK_EDP_CTRL			364
+#define PCLK_VIO			365
+#define PCLK_VIO_NOC			366
+#define PCLK_VIO_GRF			367
+#define PCLK_MIPI_DSI0			368
+#define PCLK_MIPI_DSI1			369
+#define PCLK_HDCP			370
+#define PCLK_HDCP_NOC			371
+#define PCLK_HDMI_CTRL			372
+#define PCLK_DP_CTRL			373
+#define PCLK_HDCP22			374
+#define PCLK_GASKET			375
+#define PCLK_DDR			376
+#define PCLK_DDR_MON			377
+#define PCLK_DDR_SGRF			378
+#define PCLK_ISP1_WRAPPER		379
+#define PCLK_WDT			380
+#define PCLK_EFUSE1024NS		381
+#define PCLK_EFUSE1024S			382
+#define PCLK_PMU_INTR_ARB		383
+#define PCLK_MAILBOX0			384
+#define PCLK_USBPHY_MUX_G		385
+#define PCLK_UPHY0_TCPHY_G		386
+#define PCLK_UPHY0_TCPD_G		387
+#define PCLK_UPHY1_TCPHY_G		388
+#define PCLK_UPHY1_TCPD_G		389
+#define PCLK_ALIVE			390
+
+/* hclk gates */
+#define HCLK_PERIHP			448
+#define HCLK_PERILP0			449
+#define HCLK_PERILP1			450
+#define HCLK_PERILP0_NOC		451
+#define HCLK_PERILP1_NOC		452
+#define HCLK_M0_PERILP			453
+#define HCLK_M0_PERILP_NOC		454
+#define HCLK_AHB1TOM			455
+#define HCLK_HOST0			456
+#define HCLK_HOST0_ARB			457
+#define HCLK_HOST1			458
+#define HCLK_HOST1_ARB			459
+#define HCLK_HSIC			460
+#define HCLK_SD				461
+#define HCLK_SDMMC			462
+#define HCLK_SDMMC_NOC			463
+#define HCLK_M_CRYPTO0			464
+#define HCLK_M_CRYPTO1			465
+#define HCLK_S_CRYPTO0			466
+#define HCLK_S_CRYPTO1			467
+#define HCLK_I2S0_8CH			468
+#define HCLK_I2S1_8CH			469
+#define HCLK_I2S2_8CH			470
+#define HCLK_SPDIF			471
+#define HCLK_VOP0_NOC			472
+#define HCLK_VOP0			473
+#define HCLK_VOP1_NOC			474
+#define HCLK_VOP1			475
+#define HCLK_ROM			476
+#define HCLK_IEP			477
+#define HCLK_IEP_NOC			478
+#define HCLK_ISP0			479
+#define HCLK_ISP1			480
+#define HCLK_ISP0_NOC			481
+#define HCLK_ISP1_NOC			482
+#define HCLK_ISP0_WRAPPER		483
+#define HCLK_ISP1_WRAPPER		484
+#define HCLK_RGA			485
+#define HCLK_RGA_NOC			486
+#define HCLK_HDCP			487
+#define HCLK_HDCP_NOC			488
+#define HCLK_HDCP22			489
+#define HCLK_VCODEC			490
+#define HCLK_VCODEC_NOC			491
+#define HCLK_VDU			492
+#define HCLK_VDU_NOC			493
+#define HCLK_SDIO			494
+#define HCLK_SDIO_NOC			495
+#define HCLK_SDIOAUDIO_NOC		496
+
+#define CLK_NR_CLKS			(HCLK_SDIOAUDIO_NOC + 1)
+
+/* pmu-clocks indices */
+
+#define PLL_PPLL			1
+
+#define SCLK_32K_SUSPEND_PMU		2
+#define SCLK_SPI3_PMU			3
+#define SCLK_TIMER12_PMU		4
+#define SCLK_TIMER13_PMU		5
+#define SCLK_UART4_PMU			6
+#define SCLK_PVTM_PMU			7
+#define SCLK_WIFI_PMU			8
+#define SCLK_I2C0_PMU			9
+#define SCLK_I2C4_PMU			10
+#define SCLK_I2C8_PMU			11
+
+#define PCLK_SRC_PMU			19
+#define PCLK_PMU			20
+#define PCLK_PMUGRF_PMU			21
+#define PCLK_INTMEM1_PMU		22
+#define PCLK_GPIO0_PMU			23
+#define PCLK_GPIO1_PMU			24
+#define PCLK_SGRF_PMU			25
+#define PCLK_NOC_PMU			26
+#define PCLK_I2C0_PMU			27
+#define PCLK_I2C4_PMU			28
+#define PCLK_I2C8_PMU			29
+#define PCLK_RKPWM_PMU			30
+#define PCLK_SPI3_PMU			31
+#define PCLK_TIMER_PMU			32
+#define PCLK_MAILBOX_PMU		33
+#define PCLK_UART4_PMU			34
+#define PCLK_WDT_M0_PMU			35
+
+#define FCLK_CM0S_SRC_PMU		44
+#define FCLK_CM0S_PMU			45
+#define SCLK_CM0S_PMU			46
+#define HCLK_CM0S_PMU			47
+#define DCLK_CM0S_PMU			48
+#define PCLK_INTR_ARB_PMU		49
+#define HCLK_NOC_PMU			50
+
+#define CLKPMU_NR_CLKS			(HCLK_NOC_PMU + 1)
+
+/* soft-reset indices */
+
+/* cru_softrst_con0 */
+#define SRST_CORE_L0			0
+#define SRST_CORE_B0			1
+#define SRST_CORE_PO_L0			2
+#define SRST_CORE_PO_B0			3
+#define SRST_L2_L			4
+#define SRST_L2_B			5
+#define SRST_ADB_L			6
+#define SRST_ADB_B			7
+#define SRST_A_CCI			8
+#define SRST_A_CCIM0_NOC		9
+#define SRST_A_CCIM1_NOC		10
+#define SRST_DBG_NOC			11
+
+/* cru_softrst_con1 */
+#define SRST_CORE_L0_T			16
+#define SRST_CORE_L1			17
+#define SRST_CORE_L2			18
+#define SRST_CORE_L3			19
+#define SRST_CORE_PO_L0_T		20
+#define SRST_CORE_PO_L1			21
+#define SRST_CORE_PO_L2			22
+#define SRST_CORE_PO_L3			23
+#define SRST_A_ADB400_GIC2COREL		24
+#define SRST_A_ADB400_COREL2GIC		25
+#define SRST_P_DBG_L			26
+#define SRST_L2_L_T			28
+#define SRST_ADB_L_T			29
+#define SRST_A_RKPERF_L			30
+#define SRST_PVTM_CORE_L		31
+
+/* cru_softrst_con2 */
+#define SRST_CORE_B0_T			32
+#define SRST_CORE_B1			33
+#define SRST_CORE_PO_B0_T		36
+#define SRST_CORE_PO_B1			37
+#define SRST_A_ADB400_GIC2COREB		40
+#define SRST_A_ADB400_COREB2GIC		41
+#define SRST_P_DBG_B			42
+#define SRST_L2_B_T			43
+#define SRST_ADB_B_T			45
+#define SRST_A_RKPERF_B			46
+#define SRST_PVTM_CORE_B		47
+
+/* cru_softrst_con3 */
+#define SRST_A_CCI_T			50
+#define SRST_A_CCIM0_NOC_T		51
+#define SRST_A_CCIM1_NOC_T		52
+#define SRST_A_ADB400M_PD_CORE_B_T	53
+#define SRST_A_ADB400M_PD_CORE_L_T	54
+#define SRST_DBG_NOC_T			55
+#define SRST_DBG_CXCS			56
+#define SRST_CCI_TRACE			57
+#define SRST_P_CCI_GRF			58
+
+/* cru_softrst_con4 */
+#define SRST_A_CENTER_MAIN_NOC		64
+#define SRST_A_CENTER_PERI_NOC		65
+#define SRST_P_CENTER_MAIN		66
+#define SRST_P_DDRMON			67
+#define SRST_P_CIC			68
+#define SRST_P_CENTER_SGRF		69
+#define SRST_DDR0_MSCH			70
+#define SRST_DDRCFG0_MSCH		71
+#define SRST_DDR0			72
+#define SRST_DDRPHY0			73
+#define SRST_DDR1_MSCH			74
+#define SRST_DDRCFG1_MSCH		75
+#define SRST_DDR1			76
+#define SRST_DDRPHY1			77
+#define SRST_DDR_CIC			78
+#define SRST_PVTM_DDR			79
+
+/* cru_softrst_con5 */
+#define SRST_A_VCODEC_NOC		80
+#define SRST_A_VCODEC			81
+#define SRST_H_VCODEC_NOC		82
+#define SRST_H_VCODEC			83
+#define SRST_A_VDU_NOC			88
+#define SRST_A_VDU			89
+#define SRST_H_VDU_NOC			90
+#define SRST_H_VDU			91
+#define SRST_VDU_CORE			92
+#define SRST_VDU_CA			93
+
+/* cru_softrst_con6 */
+#define SRST_A_IEP_NOC			96
+#define SRST_A_VOP_IEP			97
+#define SRST_A_IEP			98
+#define SRST_H_IEP_NOC			99
+#define SRST_H_IEP			100
+#define SRST_A_RGA_NOC			102
+#define SRST_A_RGA			103
+#define SRST_H_RGA_NOC			104
+#define SRST_H_RGA			105
+#define SRST_RGA_CORE			106
+#define SRST_EMMC_NOC			108
+#define SRST_EMMC			109
+#define SRST_EMMC_GRF			110
+
+/* cru_softrst_con7 */
+#define SRST_A_PERIHP_NOC		112
+#define SRST_P_PERIHP_GRF		113
+#define SRST_H_PERIHP_NOC		114
+#define SRST_USBHOST0			115
+#define SRST_HOSTC0_AUX			116
+#define SRST_HOST0_ARB			117
+#define SRST_USBHOST1			118
+#define SRST_HOSTC1_AUX			119
+#define SRST_HOST1_ARB			120
+#define SRST_SDIO0			121
+#define SRST_SDMMC			122
+#define SRST_HSIC			123
+#define SRST_HSIC_AUX			124
+#define SRST_AHB1TOM			125
+#define SRST_P_PERIHP_NOC		126
+#define SRST_HSICPHY			127
+
+/* cru_softrst_con8 */
+#define SRST_A_PCIE			128
+#define SRST_P_PCIE			129
+#define SRST_PCIE_CORE			130
+#define SRST_PCIE_MGMT			131
+#define SRST_PCIE_MGMT_STICKY		132
+#define SRST_PCIE_PIPE			133
+#define SRST_PCIE_PM			134
+#define SRST_PCIEPHY			135
+#define SRST_A_GMAC_NOC			136
+#define SRST_A_GMAC			137
+#define SRST_P_GMAC_NOC			138
+#define SRST_P_GMAC_GRF			140
+#define SRST_HSICPHY_POR		142
+#define SRST_HSICPHY_UTMI		143
+
+/* cru_softrst_con9 */
+#define SRST_USB2PHY0_POR		144
+#define SRST_USB2PHY0_UTMI_PORT0	145
+#define SRST_USB2PHY0_UTMI_PORT1	146
+#define SRST_USB2PHY0_EHCIPHY		147
+#define SRST_UPHY0_PIPE_L00		148
+#define SRST_UPHY0			149
+#define SRST_UPHY0_TCPDPWRUP		150
+#define SRST_USB2PHY1_POR		152
+#define SRST_USB2PHY1_UTMI_PORT0	153
+#define SRST_USB2PHY1_UTMI_PORT1	154
+#define SRST_USB2PHY1_EHCIPHY		155
+#define SRST_UPHY1_PIPE_L00		156
+#define SRST_UPHY1			157
+#define SRST_UPHY1_TCPDPWRUP		158
+
+/* cru_softrst_con10 */
+#define SRST_A_PERILP0_NOC		160
+#define SRST_A_DCF			161
+#define SRST_GIC500			162
+#define SRST_DMAC0_PERILP0		163
+#define SRST_DMAC1_PERILP0		164
+#define SRST_TZMA			165
+#define SRST_INTMEM			166
+#define SRST_ADB400_MST0		167
+#define SRST_ADB400_MST1		168
+#define SRST_ADB400_SLV0		169
+#define SRST_ADB400_SLV1		170
+#define SRST_H_PERILP0			171
+#define SRST_H_PERILP0_NOC		172
+#define SRST_ROM			173
+#define SRST_CRYPTO_S			174
+#define SRST_CRYPTO_M			175
+
+/* cru_softrst_con11 */
+#define SRST_P_DCF			176
+#define SRST_CM0S_NOC			177
+#define SRST_CM0S			178
+#define SRST_CM0S_DBG			179
+#define SRST_CM0S_PO			180
+#define SRST_CRYPTO			181
+#define SRST_P_PERILP1_SGRF		182
+#define SRST_P_PERILP1_GRF		183
+#define SRST_CRYPTO1_S			184
+#define SRST_CRYPTO1_M			185
+#define SRST_CRYPTO1			186
+#define SRST_GIC_NOC			188
+#define SRST_SD_NOC			189
+#define SRST_SDIOAUDIO_BRG		190
+
+/* cru_softrst_con12 */
+#define SRST_H_PERILP1			192
+#define SRST_H_PERILP1_NOC		193
+#define SRST_H_I2S0_8CH			194
+#define SRST_H_I2S1_8CH			195
+#define SRST_H_I2S2_8CH			196
+#define SRST_H_SPDIF_8CH		197
+#define SRST_P_PERILP1_NOC		198
+#define SRST_P_EFUSE_1024		199
+#define SRST_P_EFUSE_1024S		200
+#define SRST_P_I2C0			201
+#define SRST_P_I2C1			202
+#define SRST_P_I2C2			203
+#define SRST_P_I2C3			204
+#define SRST_P_I2C4			205
+#define SRST_P_I2C5			206
+#define SRST_P_MAILBOX0			207
+
+/* cru_softrst_con13 */
+#define SRST_P_UART0			208
+#define SRST_P_UART1			209
+#define SRST_P_UART2			210
+#define SRST_P_UART3			211
+#define SRST_P_SARADC			212
+#define SRST_P_TSADC			213
+#define SRST_P_SPI0			214
+#define SRST_P_SPI1			215
+#define SRST_P_SPI2			216
+#define SRST_P_SPI4			217
+#define SRST_P_SPI5			218
+#define SRST_SPI0			219
+#define SRST_SPI1			220
+#define SRST_SPI2			221
+#define SRST_SPI4			222
+#define SRST_SPI5			223
+
+/* cru_softrst_con14 */
+#define SRST_I2S0_8CH			224
+#define SRST_I2S1_8CH			225
+#define SRST_I2S2_8CH			226
+#define SRST_SPDIF_8CH			227
+#define SRST_UART0			228
+#define SRST_UART1			229
+#define SRST_UART2			230
+#define SRST_UART3			231
+#define SRST_TSADC			232
+#define SRST_I2C0			233
+#define SRST_I2C1			234
+#define SRST_I2C2			235
+#define SRST_I2C3			236
+#define SRST_I2C4			237
+#define SRST_I2C5			238
+#define SRST_SDIOAUDIO_NOC		239
+
+/* cru_softrst_con15 */
+#define SRST_A_VIO_NOC			240
+#define SRST_A_HDCP_NOC			241
+#define SRST_A_HDCP			242
+#define SRST_H_HDCP_NOC			243
+#define SRST_H_HDCP			244
+#define SRST_P_HDCP_NOC			245
+#define SRST_P_HDCP			246
+#define SRST_P_HDMI_CTRL		247
+#define SRST_P_DP_CTRL			248
+#define SRST_S_DP_CTRL			249
+#define SRST_C_DP_CTRL			250
+#define SRST_P_MIPI_DSI0		251
+#define SRST_P_MIPI_DSI1		252
+#define SRST_DP_CORE			253
+#define SRST_DP_I2S			254
+
+/* cru_softrst_con16 */
+#define SRST_GASKET			256
+#define SRST_VIO_GRF			258
+#define SRST_DPTX_SPDIF_REC		259
+#define SRST_HDMI_CTRL			260
+#define SRST_HDCP_CTRL			261
+#define SRST_A_ISP0_NOC			262
+#define SRST_A_ISP1_NOC			263
+#define SRST_H_ISP0_NOC			266
+#define SRST_H_ISP1_NOC			267
+#define SRST_H_ISP0			268
+#define SRST_H_ISP1			269
+#define SRST_ISP0			270
+#define SRST_ISP1			271
+
+/* cru_softrst_con17 */
+#define SRST_A_VOP0_NOC			272
+#define SRST_A_VOP1_NOC			273
+#define SRST_A_VOP0			274
+#define SRST_A_VOP1			275
+#define SRST_H_VOP0_NOC			276
+#define SRST_H_VOP1_NOC			277
+#define SRST_H_VOP0			278
+#define SRST_H_VOP1			279
+#define SRST_D_VOP0			280
+#define SRST_D_VOP1			281
+#define SRST_VOP0_PWM			282
+#define SRST_VOP1_PWM			283
+#define SRST_P_EDP_NOC			284
+#define SRST_P_EDP_CTRL			285
+
+/* cru_softrst_con18 */
+#define SRST_A_GPU			288
+#define SRST_A_GPU_NOC			289
+#define SRST_A_GPU_GRF			290
+#define SRST_PVTM_GPU			291
+#define SRST_A_USB3_NOC			292
+#define SRST_A_USB3_OTG0		293
+#define SRST_A_USB3_OTG1		294
+#define SRST_A_USB3_GRF			295
+#define SRST_PMU			296
+
+/* cru_softrst_con19 */
+#define SRST_P_TIMER0_5			304
+#define SRST_TIMER0			305
+#define SRST_TIMER1			306
+#define SRST_TIMER2			307
+#define SRST_TIMER3			308
+#define SRST_TIMER4			309
+#define SRST_TIMER5			310
+#define SRST_P_TIMER6_11		311
+#define SRST_TIMER6			312
+#define SRST_TIMER7			313
+#define SRST_TIMER8			314
+#define SRST_TIMER9			315
+#define SRST_TIMER10			316
+#define SRST_TIMER11			317
+#define SRST_P_INTR_ARB_PMU		318
+#define SRST_P_ALIVE_SGRF		319
+
+/* cru_softrst_con20 */
+#define SRST_P_GPIO2			320
+#define SRST_P_GPIO3			321
+#define SRST_P_GPIO4			322
+#define SRST_P_GRF			323
+#define SRST_P_ALIVE_NOC		324
+#define SRST_P_WDT0			325
+#define SRST_P_WDT1			326
+#define SRST_P_INTR_ARB			327
+#define SRST_P_UPHY0_DPTX		328
+#define SRST_P_UPHY0_APB		330
+#define SRST_P_UPHY0_TCPHY		332
+#define SRST_P_UPHY1_TCPHY		333
+#define SRST_P_UPHY0_TCPDCTRL		334
+#define SRST_P_UPHY1_TCPDCTRL		335
+
+/* pmu soft-reset indices */
+
+/* pmu_cru_softrst_con0 */
+#define SRST_P_NOC			0
+#define SRST_P_INTMEM			1
+#define SRST_H_CM0S			2
+#define SRST_H_CM0S_NOC			3
+#define SRST_DBG_CM0S			4
+#define SRST_PO_CM0S			5
+#define SRST_P_SPI3			6
+#define SRST_SPI3			7
+#define SRST_P_TIMER_0_1		8
+#define SRST_P_TIMER_0			9
+#define SRST_P_TIMER_1			10
+#define SRST_P_UART4			11
+#define SRST_UART4			12
+#define SRST_P_WDT			13
+
+/* pmu_cru_softrst_con1 */
+#define SRST_P_I2C6			16
+#define SRST_P_I2C7			17
+#define SRST_P_I2C8			18
+#define SRST_P_MAILBOX			19
+#define SRST_P_RKPWM			20
+#define SRST_P_PMUGRF			21
+#define SRST_P_SGRF			22
+#define SRST_P_GPIO0			23
+#define SRST_P_GPIO1			24
+#define SRST_P_CRU			25
+#define SRST_P_INTR			26
+#define SRST_PVTM			27
+#define SRST_I2C6			28
+#define SRST_I2C7			29
+#define SRST_I2C8			30
+
+#endif
diff --git a/include/dt-bindings/clock/rockchip,rk808.h b/include/dt-bindings/clock/rockchip,rk808.h
new file mode 100644
index 0000000..1a87343
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk808.h
@@ -0,0 +1,11 @@
+/*
+ * This header provides constants clk index RK808 pmic clkout
+ */
+#ifndef _CLK_ROCKCHIP_RK808
+#define _CLK_ROCKCHIP_RK808
+
+/* CLOCKOUT index */
+#define RK808_CLKOUT0		0
+#define RK808_CLKOUT1		1
+
+#endif
diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h
new file mode 100644
index 0000000..10ed9d1
--- /dev/null
+++ b/include/dt-bindings/clock/rv1108-cru.h
@@ -0,0 +1,356 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
+ * Author: Shawn Lin <shawn.lin@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
+
+/* pll id */
+#define PLL_APLL			0
+#define PLL_DPLL			1
+#define PLL_GPLL			2
+#define ARMCLK				3
+
+/* sclk gates (special clocks) */
+#define SCLK_SPI0			65
+#define SCLK_NANDC			67
+#define SCLK_SDMMC			68
+#define SCLK_SDIO			69
+#define SCLK_EMMC			71
+#define SCLK_UART0			72
+#define SCLK_UART1			73
+#define SCLK_UART2			74
+#define SCLK_I2S0			75
+#define SCLK_I2S1			76
+#define SCLK_I2S2			77
+#define SCLK_TIMER0			78
+#define SCLK_TIMER1			79
+#define SCLK_SFC			80
+#define SCLK_SDMMC_DRV			81
+#define SCLK_SDIO_DRV			82
+#define SCLK_EMMC_DRV			83
+#define SCLK_SDMMC_SAMPLE		84
+#define SCLK_SDIO_SAMPLE		85
+#define SCLK_EMMC_SAMPLE		86
+#define SCLK_VENC_CORE			87
+#define SCLK_HEVC_CORE			88
+#define SCLK_HEVC_CABAC			89
+#define SCLK_PWM0_PMU			90
+#define SCLK_I2C0_PMU			91
+#define SCLK_WIFI			92
+#define SCLK_CIFOUT			93
+#define SCLK_MIPI_CSI_OUT		94
+#define SCLK_CIF0			95
+#define SCLK_CIF1			96
+#define SCLK_CIF2			97
+#define SCLK_CIF3			98
+#define SCLK_DSP			99
+#define SCLK_DSP_IOP			100
+#define SCLK_DSP_EPP			101
+#define SCLK_DSP_EDP			102
+#define SCLK_DSP_EDAP			103
+#define SCLK_CVBS_HOST			104
+#define SCLK_HDMI_SFR			105
+#define SCLK_HDMI_CEC			106
+#define SCLK_CRYPTO			107
+#define SCLK_SPI			108
+#define SCLK_SARADC			109
+#define SCLK_TSADC			110
+#define SCLK_MAC_PRE			111
+#define SCLK_MAC			112
+#define SCLK_MAC_RX			113
+#define SCLK_MAC_REF			114
+#define SCLK_MAC_REFOUT			115
+#define SCLK_DSP_PFM			116
+#define SCLK_RGA			117
+#define SCLK_I2C1			118
+#define SCLK_I2C2			119
+#define SCLK_I2C3			120
+#define SCLK_PWM			121
+#define SCLK_ISP			122
+#define SCLK_USBPHY			123
+#define SCLK_I2S0_SRC			124
+#define SCLK_I2S1_SRC			125
+#define SCLK_I2S2_SRC			126
+#define SCLK_UART0_SRC			127
+#define SCLK_UART1_SRC			128
+#define SCLK_UART2_SRC			129
+#define SCLK_MAC_TX			130
+#define SCLK_MACREF			131
+#define SCLK_MACREF_OUT			132
+
+#define DCLK_VOP_SRC			185
+#define DCLK_HDMIPHY			186
+#define DCLK_VOP			187
+
+/* aclk gates */
+#define ACLK_DMAC			192
+#define ACLK_PRE			193
+#define ACLK_CORE			194
+#define ACLK_ENMCORE			195
+#define ACLK_RKVENC			196
+#define ACLK_RKVDEC			197
+#define ACLK_VPU			198
+#define ACLK_CIF0			199
+#define ACLK_VIO0			200
+#define ACLK_VIO1			201
+#define ACLK_VOP			202
+#define ACLK_IEP			203
+#define ACLK_RGA			204
+#define ACLK_ISP			205
+#define ACLK_CIF1			206
+#define ACLK_CIF2			207
+#define ACLK_CIF3			208
+#define ACLK_PERI			209
+#define ACLK_GMAC			210
+
+/* pclk gates */
+#define PCLK_GPIO1			256
+#define PCLK_GPIO2			257
+#define PCLK_GPIO3			258
+#define PCLK_GRF			259
+#define PCLK_I2C1			260
+#define PCLK_I2C2			261
+#define PCLK_I2C3			262
+#define PCLK_SPI			263
+#define PCLK_SFC			264
+#define PCLK_UART0			265
+#define PCLK_UART1			266
+#define PCLK_UART2			267
+#define PCLK_TSADC			268
+#define PCLK_PWM			269
+#define PCLK_TIMER			270
+#define PCLK_PERI			271
+#define PCLK_GPIO0_PMU			272
+#define PCLK_I2C0_PMU			273
+#define PCLK_PWM0_PMU			274
+#define PCLK_ISP			275
+#define PCLK_VIO			276
+#define PCLK_MIPI_DSI			277
+#define PCLK_HDMI_CTRL			278
+#define PCLK_SARADC			279
+#define PCLK_DSP_CFG			280
+#define PCLK_BUS			281
+#define PCLK_EFUSE0			282
+#define PCLK_EFUSE1			283
+#define PCLK_WDT			284
+#define PCLK_GMAC			285
+
+/* hclk gates */
+#define HCLK_I2S0_8CH			320
+#define HCLK_I2S1_2CH			321
+#define HCLK_I2S2_2CH			322
+#define HCLK_NANDC			323
+#define HCLK_SDMMC			324
+#define HCLK_SDIO			325
+#define HCLK_EMMC			326
+#define HCLK_PERI			327
+#define HCLK_SFC			328
+#define HCLK_RKVENC			329
+#define HCLK_RKVDEC			330
+#define HCLK_CIF0			331
+#define HCLK_VIO			332
+#define HCLK_VOP			333
+#define HCLK_IEP			334
+#define HCLK_RGA			335
+#define HCLK_ISP			336
+#define HCLK_CRYPTO_MST			337
+#define HCLK_CRYPTO_SLV			338
+#define HCLK_HOST0			339
+#define HCLK_OTG			340
+#define HCLK_CIF1			341
+#define HCLK_CIF2			342
+#define HCLK_CIF3			343
+#define HCLK_BUS			344
+#define HCLK_VPU			345
+
+#define CLK_NR_CLKS			(HCLK_VPU + 1)
+
+/* reset id */
+#define SRST_CORE_PO_AD			0
+#define SRST_CORE_AD			1
+#define SRST_L2_AD			2
+#define SRST_CPU_NIU_AD			3
+#define SRST_CORE_PO			4
+#define SRST_CORE			5
+#define SRST_L2				6
+#define SRST_CORE_DBG			8
+#define PRST_DBG			9
+#define RST_DAP				10
+#define PRST_DBG_NIU			11
+#define ARST_STRC_SYS_AD		15
+
+#define SRST_DDRPHY_CLKDIV		16
+#define SRST_DDRPHY			17
+#define PRST_DDRPHY			18
+#define PRST_HDMIPHY			19
+#define PRST_VDACPHY			20
+#define PRST_VADCPHY			21
+#define PRST_MIPI_CSI_PHY		22
+#define PRST_MIPI_DSI_PHY		23
+#define PRST_ACODEC			24
+#define ARST_BUS_NIU			25
+#define PRST_TOP_NIU			26
+#define ARST_INTMEM			27
+#define HRST_ROM			28
+#define ARST_DMAC			29
+#define SRST_MSCH_NIU			30
+#define PRST_MSCH_NIU			31
+
+#define PRST_DDRUPCTL			32
+#define NRST_DDRUPCTL			33
+#define PRST_DDRMON			34
+#define HRST_I2S0_8CH			35
+#define MRST_I2S0_8CH			36
+#define HRST_I2S1_2CH			37
+#define MRST_IS21_2CH			38
+#define HRST_I2S2_2CH			39
+#define MRST_I2S2_2CH			40
+#define HRST_CRYPTO			41
+#define SRST_CRYPTO			42
+#define PRST_SPI			43
+#define SRST_SPI			44
+#define PRST_UART0			45
+#define PRST_UART1			46
+#define PRST_UART2			47
+
+#define SRST_UART0			48
+#define SRST_UART1			49
+#define SRST_UART2			50
+#define PRST_I2C1			51
+#define PRST_I2C2			52
+#define PRST_I2C3			53
+#define SRST_I2C1			54
+#define SRST_I2C2			55
+#define SRST_I2C3			56
+#define PRST_PWM1			58
+#define SRST_PWM1			60
+#define PRST_WDT			61
+#define PRST_GPIO1			62
+#define PRST_GPIO2			63
+
+#define PRST_GPIO3			64
+#define PRST_GRF			65
+#define PRST_EFUSE			66
+#define PRST_EFUSE512			67
+#define PRST_TIMER0			68
+#define SRST_TIMER0			69
+#define SRST_TIMER1			70
+#define PRST_TSADC			71
+#define SRST_TSADC			72
+#define PRST_SARADC			73
+#define SRST_SARADC			74
+#define HRST_SYSBUS			75
+#define PRST_USBGRF			76
+
+#define ARST_PERIPH_NIU			80
+#define HRST_PERIPH_NIU			81
+#define PRST_PERIPH_NIU			82
+#define HRST_PERIPH			83
+#define HRST_SDMMC			84
+#define HRST_SDIO			85
+#define HRST_EMMC			86
+#define HRST_NANDC			87
+#define NRST_NANDC			88
+#define HRST_SFC			89
+#define SRST_SFC			90
+#define ARST_GMAC			91
+#define HRST_OTG			92
+#define SRST_OTG			93
+#define SRST_OTG_ADP			94
+#define HRST_HOST0			95
+
+#define HRST_HOST0_AUX			96
+#define HRST_HOST0_ARB			97
+#define SRST_HOST0_EHCIPHY		98
+#define SRST_HOST0_UTMI			99
+#define SRST_USBPOR			100
+#define SRST_UTMI0			101
+#define SRST_UTMI1			102
+
+#define ARST_VIO0_NIU			102
+#define ARST_VIO1_NIU			103
+#define HRST_VIO_NIU			104
+#define PRST_VIO_NIU			105
+#define ARST_VOP			106
+#define HRST_VOP			107
+#define DRST_VOP			108
+#define ARST_IEP			109
+#define HRST_IEP			110
+#define ARST_RGA			111
+#define HRST_RGA			112
+#define SRST_RGA			113
+#define PRST_CVBS			114
+#define PRST_HDMI			115
+#define SRST_HDMI			116
+#define PRST_MIPI_DSI			117
+
+#define ARST_ISP_NIU			118
+#define HRST_ISP_NIU			119
+#define HRST_ISP			120
+#define SRST_ISP			121
+#define ARST_VIP0			122
+#define HRST_VIP0			123
+#define PRST_VIP0			124
+#define ARST_VIP1			125
+#define HRST_VIP1			126
+#define PRST_VIP1			127
+#define ARST_VIP2			128
+#define HRST_VIP2			129
+#define PRST_VIP2			120
+#define ARST_VIP3			121
+#define HRST_VIP3			122
+#define PRST_VIP4			123
+
+#define PRST_CIF1TO4			124
+#define SRST_CVBS_CLK			125
+#define HRST_CVBS			126
+
+#define ARST_VPU_NIU			140
+#define HRST_VPU_NIU			141
+#define ARST_VPU			142
+#define HRST_VPU			143
+#define ARST_RKVDEC_NIU			144
+#define HRST_RKVDEC_NIU			145
+#define ARST_RKVDEC			146
+#define HRST_RKVDEC			147
+#define SRST_RKVDEC_CABAC		148
+#define SRST_RKVDEC_CORE		149
+#define ARST_RKVENC_NIU			150
+#define HRST_RKVENC_NIU			151
+#define ARST_RKVENC			152
+#define HRST_RKVENC			153
+#define SRST_RKVENC_CORE		154
+
+#define SRST_DSP_CORE			156
+#define SRST_DSP_SYS			157
+#define SRST_DSP_GLOBAL			158
+#define SRST_DSP_OECM			159
+#define PRST_DSP_IOP_NIU		160
+#define ARST_DSP_EPP_NIU		161
+#define ARST_DSP_EDP_NIU		162
+#define PRST_DSP_DBG_NIU		163
+#define PRST_DSP_CFG_NIU		164
+#define PRST_DSP_GRF			165
+#define PRST_DSP_MAILBOX		166
+#define PRST_DSP_INTC			167
+#define PRST_DSP_PFM_MON		169
+#define SRST_DSP_PFM_MON		170
+#define ARST_DSP_EDAP_NIU		171
+
+#define SRST_PMU			172
+#define SRST_PMU_I2C0			173
+#define PRST_PMU_I2C0			174
+#define PRST_PMU_GPIO0			175
+#define PRST_PMU_INTMEM			176
+#define PRST_PMU_PWM0			177
+#define SRST_PMU_PWM0			178
+#define PRST_PMU_GRF			179
+#define SRST_PMU_NIU			180
+#define SRST_PMU_PVTM			181
+#define ARST_DSP_EDP_PERF		184
+#define ARST_DSP_EPP_PERF		185
+
+#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */
diff --git a/include/dt-bindings/clock/s900_cmu.h b/include/dt-bindings/clock/s900_cmu.h
new file mode 100644
index 0000000..2685a6d
--- /dev/null
+++ b/include/dt-bindings/clock/s900_cmu.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_S900_CMU_H_
+#define _DT_BINDINGS_CLOCK_S900_CMU_H_
+
+/* Module Clock ID */
+#define CLOCK_DDRCH1				0
+#define CLOCK_DMAC				1
+#define CLOCK_DDRCH0				2
+#define CLOCK_BROM				3
+#define CLOCK_NANDC0				4
+#define CLOCK_SD0				5
+#define CLOCK_SD1				6
+#define CLOCK_SD2				7
+#define CLOCK_DE				8
+#define CLOCK_LVDS				9
+#define CLOCK_EDP				10
+#define CLOCK_NANDC1				11
+#define CLOCK_DSI				12
+#define CLOCK_CSI0				13
+#define CLOCK_BISP				14
+#define CLOCK_CSI1				15
+#define CLOCK_SD3				16
+#define CLOCK_I2C4				17
+#define CLOCK_GPIO				18
+#define CLOCK_DMM				19
+#define CLOCK_I2STX				20
+#define CLOCK_I2SRX				21
+#define CLOCK_HDMIA				22
+#define CLOCK_SPDIF				23
+#define CLOCK_PCM0				24
+#define CLOCK_VDE				25
+#define CLOCK_VCE				26
+#define CLOCK_HDE				27
+#define CLOCK_SHARESRAM				28
+#define CLOCK_CMU_DDR1				29
+#define CLOCK_GPU3D				30
+#define CLOCK_CMUDDR0				31
+#define CLOCK_SPEED				32
+#define CLOCK_I2C5				33
+#define CLOCK_THERMAL				34
+#define CLOCK_HDMI				35
+#define CLOCK_PWM4				36
+#define CLOCK_PWM5				37
+#define CLOCK_UART0				38
+#define CLOCK_UART1				39
+#define CLOCK_UART2				40
+#define CLOCK_IRC				41
+#define CLOCK_SPI0				42
+#define CLOCK_SPI1				43
+#define CLOCK_SPI2				44
+#define CLOCK_SPI3				45
+#define CLOCK_I2C0				46
+#define CLOCK_I2C1				47
+#define CLOCK_PCM1				48
+#define CLOCK_IMX				49
+#define CLOCK_UART6				50
+#define CLOCK_UART3				51
+#define CLOCK_UART4				52
+#define CLOCK_UART5				53
+#define CLOCK_ETHERNET				54
+#define CLOCK_PWM0				55
+#define CLOCK_PWM1				56
+#define CLOCK_PWM2				57
+#define CLOCK_PWM3				58
+#define CLOCK_TIMER				59
+#define CLOCK_SE				60
+#define CLOCK_HDCP2TX				61
+#define CLOCK_I2C2				62
+#define CLOCK_I2C3				63
+
+#endif
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h
new file mode 100644
index 0000000..6a0b70a
--- /dev/null
+++ b/include/dt-bindings/clock/sifive-fu540-prci.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
+#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
+
+/* Clock indexes for use by Device Tree data and the PRCI driver */
+
+#define PRCI_CLK_COREPLL	       0
+#define PRCI_CLK_DDRPLL		       1
+#define PRCI_CLK_GEMGXLPLL	       2
+#define PRCI_CLK_TLCLK		       3
+
+#endif
diff --git a/include/dt-bindings/clock/snps,hsdk-cgu.h b/include/dt-bindings/clock/snps,hsdk-cgu.h
new file mode 100644
index 0000000..2cfe34e
--- /dev/null
+++ b/include/dt-bindings/clock/snps,hsdk-cgu.h
@@ -0,0 +1,42 @@
+/*
+ * Synopsys HSDK SDP CGU clock driver dts bindings
+ *
+ * Copyright (C) 2017 Synopsys
+ * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __DT_BINDINGS_CLK_HSDK_CGU_H_
+#define __DT_BINDINGS_CLK_HSDK_CGU_H_
+
+#define CLK_ARC_PLL		0
+#define CLK_ARC			1
+#define CLK_DDR_PLL		2
+#define CLK_SYS_PLL		3
+#define CLK_SYS_APB		4
+#define CLK_SYS_AXI		5
+#define CLK_SYS_ETH		6
+#define CLK_SYS_USB		7
+#define CLK_SYS_SDIO		8
+#define CLK_SYS_HDMI		9
+#define CLK_SYS_GFX_CORE	10
+#define CLK_SYS_GFX_DMA		11
+#define CLK_SYS_GFX_CFG		12
+#define CLK_SYS_DMAC_CORE	13
+#define CLK_SYS_DMAC_CFG	14
+#define CLK_SYS_SDIO_REF	15
+#define CLK_SYS_SPI_REF		16
+#define CLK_SYS_I2C_REF		17
+#define CLK_SYS_UART_REF	18
+#define CLK_SYS_EBI_REF		19
+#define CLK_TUN_PLL		20
+#define CLK_TUN_TUN		21
+#define CLK_TUN_ROM		22
+#define CLK_TUN_PWM		23
+#define CLK_HDMI_PLL		24
+#define CLK_HDMI		25
+
+#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */
diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
new file mode 100644
index 0000000..082edd9
--- /dev/null
+++ b/include/dt-bindings/clock/stih407-clks.h
@@ -0,0 +1,90 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH407
+#define _DT_BINDINGS_CLK_STIH407
+
+/* CLOCKGEN A0 */
+#define CLK_IC_LMI0		0
+#define CLK_IC_LMI1		1
+
+/* CLOCKGEN C0 */
+#define CLK_ICN_GPU		0
+#define CLK_FDMA		1
+#define CLK_NAND		2
+#define CLK_HVA			3
+#define CLK_PROC_STFE		4
+#define CLK_PROC_TP		5
+#define CLK_RX_ICN_DMU		6
+#define CLK_RX_ICN_DISP_0	6
+#define CLK_RX_ICN_DISP_1	6
+#define CLK_RX_ICN_HVA		7
+#define CLK_RX_ICN_TS		7
+#define CLK_ICN_CPU		8
+#define CLK_TX_ICN_DMU		9
+#define CLK_TX_ICN_HVA		9
+#define CLK_TX_ICN_TS		9
+#define CLK_ICN_COMPO		9
+#define CLK_MMC_0		10
+#define CLK_MMC_1		11
+#define CLK_JPEGDEC		12
+#define CLK_ICN_REG		13
+#define CLK_TRACE_A9		13
+#define CLK_PTI_STM		13
+#define CLK_EXT2F_A9		13
+#define CLK_IC_BDISP_0		14
+#define CLK_IC_BDISP_1		15
+#define CLK_PP_DMU		16
+#define CLK_VID_DMU		17
+#define CLK_DSS_LPC		18
+#define CLK_ST231_AUD_0		19
+#define CLK_ST231_GP_0		19
+#define CLK_ST231_GP_1		20
+#define CLK_ST231_DMU		21
+#define CLK_ICN_LMI		22
+#define CLK_TX_ICN_DISP_0	23
+#define CLK_TX_ICN_DISP_1	23
+#define CLK_ICN_SBC		24
+#define CLK_STFE_FRC2		25
+#define CLK_ETH_PHY		26
+#define CLK_ETH_REF_PHYCLK	27
+#define CLK_FLASH_PROMIP	28
+#define CLK_MAIN_DISP		29
+#define CLK_AUX_DISP		30
+#define CLK_COMPO_DVP		31
+
+/* CLOCKGEN D0 */
+#define CLK_PCM_0		0
+#define CLK_PCM_1		1
+#define CLK_PCM_2		2
+#define CLK_SPDIFF		3
+
+/* CLOCKGEN D2 */
+#define CLK_PIX_MAIN_DISP	0
+#define CLK_PIX_PIP		1
+#define CLK_PIX_GDP1		2
+#define CLK_PIX_GDP2		3
+#define CLK_PIX_GDP3		4
+#define CLK_PIX_GDP4		5
+#define CLK_PIX_AUX_DISP	6
+#define CLK_DENC		7
+#define CLK_PIX_HDDAC		8
+#define CLK_HDDAC		9
+#define CLK_SDDAC		10
+#define CLK_PIX_DVO		11
+#define CLK_DVO			12
+#define CLK_PIX_HDMI		13
+#define CLK_TMDS_HDMI		14
+#define CLK_REF_HDMIPHY		15
+
+/* CLOCKGEN D3 */
+#define CLK_STFE_FRC1		0
+#define CLK_TSOUT_0		1
+#define CLK_TSOUT_1		2
+#define CLK_MCHI		3
+#define CLK_VSENS_COMPO		4
+#define CLK_FRC1_REMOTE		5
+#define CLK_LPC_0		6
+#define CLK_LPC_1		7
+#endif
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
new file mode 100644
index 0000000..2097a4b
--- /dev/null
+++ b/include/dt-bindings/clock/stih410-clks.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH410 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH410
+#define _DT_BINDINGS_CLK_STIH410
+
+#include "stih407-clks.h"
+
+/* STiH410 introduces new clock outputs compared to STiH407 */
+
+/* CLOCKGEN C0 */
+#define CLK_TX_ICN_HADES	32
+#define CLK_RX_ICN_HADES	33
+#define CLK_ICN_REG_16		34
+#define CLK_PP_HADES		35
+#define CLK_CLUST_HADES		36
+#define CLK_HWPE_HADES		37
+#define CLK_FC_HADES		38
+
+/* CLOCKGEN D0 */
+#define CLK_PCMR10_MASTER	4
+#define CLK_USB2_PHY		5
+
+#endif
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
new file mode 100644
index 0000000..58d8b51
--- /dev/null
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -0,0 +1,60 @@
+/*
+ * stm32fx-clock.h
+ *
+ * Copyright (C) 2016 STMicroelectronics
+ * Author: Gabriel Fernandez for STMicroelectronics.
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+/*
+ * List of clocks wich are not derived from system clock (SYSCLOCK)
+ *
+ * The index of these clocks is the secondary index of DT bindings
+ * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
+ *
+ * e.g:
+	<assigned-clocks = <&rcc 1 CLK_LSE>;
+*/
+
+#ifndef _DT_BINDINGS_CLK_STMFX_H
+#define _DT_BINDINGS_CLK_STMFX_H
+
+#define SYSTICK			0
+#define FCLK			1
+#define CLK_LSI			2
+#define CLK_LSE			3
+#define CLK_HSE_RTC		4
+#define CLK_RTC			5
+#define PLL_VCO_I2S		6
+#define PLL_VCO_SAI		7
+#define CLK_LCD			8
+#define CLK_I2S			9
+#define CLK_SAI1		10
+#define CLK_SAI2		11
+#define CLK_I2SQ_PDIV		12
+#define CLK_SAIQ_PDIV		13
+#define CLK_HSI			14
+#define CLK_SYSCLK		15
+#define CLK_F469_DSI		16
+
+#define END_PRIMARY_CLK		17
+
+#define CLK_HDMI_CEC		16
+#define CLK_SPDIF		17
+#define CLK_USART1		18
+#define CLK_USART2		19
+#define CLK_USART3		20
+#define CLK_UART4		21
+#define CLK_UART5		22
+#define CLK_USART6		23
+#define CLK_UART7		24
+#define CLK_UART8		25
+#define CLK_I2C1		26
+#define CLK_I2C2		27
+#define CLK_I2C3		28
+#define CLK_I2C4		29
+#define CLK_LPTIMER		30
+
+#define END_PRIMARY_CLK_F7	31
+
+#endif
diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h
new file mode 100644
index 0000000..4d87e7e
--- /dev/null
+++ b/include/dt-bindings/clock/stm32h7-clks.h
@@ -0,0 +1,167 @@
+/* SYS, CORE AND BUS CLOCKS */
+#define SYS_D1CPRE 0
+#define HCLK 1
+#define PCLK1 2
+#define PCLK2 3
+#define PCLK3 4
+#define PCLK4 5
+#define HSI_DIV 6
+#define HSE_1M 7
+#define I2S_CKIN 8
+#define CK_DSI_PHY 9
+#define HSE_CK 10
+#define LSE_CK 11
+#define CSI_KER_DIV122 12
+#define RTC_CK 13
+#define CPU_SYSTICK 14
+
+/* OSCILLATOR BANK */
+#define OSC_BANK 18
+#define HSI_CK 18
+#define HSI_KER_CK 19
+#define CSI_CK 20
+#define CSI_KER_CK 21
+#define RC48_CK 22
+#define LSI_CK 23
+
+/* MCLOCK BANK */
+#define MCLK_BANK 28
+#define PER_CK 28
+#define PLLSRC 29
+#define SYS_CK 30
+#define TRACEIN_CK 31
+
+/* ODF BANK */
+#define ODF_BANK 32
+#define PLL1_P 32
+#define PLL1_Q 33
+#define PLL1_R 34
+#define PLL2_P 35
+#define PLL2_Q 36
+#define PLL2_R 37
+#define PLL3_P 38
+#define PLL3_Q 39
+#define PLL3_R 40
+
+/* MCO BANK */
+#define MCO_BANK 41
+#define MCO1 41
+#define MCO2 42
+
+/* PERIF BANK */
+#define PERIF_BANK 50
+#define D1SRAM1_CK 50
+#define ITCM_CK 51
+#define DTCM2_CK 52
+#define DTCM1_CK 53
+#define FLITF_CK 54
+#define JPGDEC_CK 55
+#define DMA2D_CK 56
+#define MDMA_CK 57
+#define USB2ULPI_CK 58
+#define USB1ULPI_CK 59
+#define ETH1RX_CK 60
+#define ETH1TX_CK 61
+#define ETH1MAC_CK 62
+#define ART_CK 63
+#define DMA2_CK 64
+#define DMA1_CK 65
+#define D2SRAM3_CK 66
+#define D2SRAM2_CK 67
+#define D2SRAM1_CK 68
+#define HASH_CK 69
+#define CRYPT_CK 70
+#define CAMITF_CK 71
+#define BKPRAM_CK 72
+#define HSEM_CK 73
+#define BDMA_CK 74
+#define CRC_CK 75
+#define GPIOK_CK 76
+#define GPIOJ_CK 77
+#define GPIOI_CK 78
+#define GPIOH_CK 79
+#define GPIOG_CK 80
+#define GPIOF_CK 81
+#define GPIOE_CK 82
+#define GPIOD_CK 83
+#define GPIOC_CK 84
+#define GPIOB_CK 85
+#define GPIOA_CK 86
+#define WWDG1_CK 87
+#define DAC12_CK 88
+#define WWDG2_CK 89
+#define TIM14_CK 90
+#define TIM13_CK 91
+#define TIM12_CK 92
+#define TIM7_CK 93
+#define TIM6_CK 94
+#define TIM5_CK 95
+#define TIM4_CK 96
+#define TIM3_CK 97
+#define TIM2_CK 98
+#define MDIOS_CK 99
+#define OPAMP_CK 100
+#define CRS_CK 101
+#define TIM17_CK 102
+#define TIM16_CK 103
+#define TIM15_CK 104
+#define TIM8_CK 105
+#define TIM1_CK 106
+#define TMPSENS_CK 107
+#define RTCAPB_CK 108
+#define VREF_CK 109
+#define COMP12_CK 110
+#define SYSCFG_CK 111
+/* must be equal to last peripheral clock index */
+#define LAST_PERIF_BANK SYSCFG_CK
+
+/* KERNEL BANK */
+#define KERN_BANK 120
+#define SDMMC1_CK 120
+#define QUADSPI_CK 121
+#define FMC_CK 122
+#define USB2OTG_CK 123
+#define USB1OTG_CK 124
+#define ADC12_CK 125
+#define SDMMC2_CK 126
+#define RNG_CK 127
+#define ADC3_CK 128
+#define DSI_CK 129
+#define LTDC_CK 130
+#define USART8_CK 131
+#define USART7_CK 132
+#define HDMICEC_CK 133
+#define I2C3_CK 134
+#define I2C2_CK 135
+#define I2C1_CK 136
+#define UART5_CK 137
+#define UART4_CK 138
+#define USART3_CK 139
+#define USART2_CK 140
+#define SPDIFRX_CK 141
+#define SPI3_CK 142
+#define SPI2_CK 143
+#define LPTIM1_CK 144
+#define FDCAN_CK 145
+#define SWP_CK 146
+#define HRTIM_CK 147
+#define DFSDM1_CK 148
+#define SAI3_CK 149
+#define SAI2_CK 150
+#define SAI1_CK 151
+#define SPI5_CK 152
+#define SPI4_CK 153
+#define SPI1_CK 154
+#define USART6_CK 155
+#define USART1_CK 156
+#define SAI4B_CK 157
+#define SAI4A_CK 158
+#define LPTIM5_CK 159
+#define LPTIM4_CK 160
+#define LPTIM3_CK 161
+#define LPTIM2_CK 162
+#define I2C4_CK 163
+#define SPI6_CK 164
+#define LPUART1_CK 165
+
+#define STM32H7_MAX_CLKS 166
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
new file mode 100644
index 0000000..4cdaf13
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
+#define _DT_BINDINGS_STM32MP1_CLKS_H_
+
+/* OSCILLATOR clocks */
+#define CK_HSE		0
+#define CK_CSI		1
+#define CK_LSI		2
+#define CK_LSE		3
+#define CK_HSI		4
+#define CK_HSE_DIV2	5
+
+/* Bus clocks */
+#define TIM2		6
+#define TIM3		7
+#define TIM4		8
+#define TIM5		9
+#define TIM6		10
+#define TIM7		11
+#define TIM12		12
+#define TIM13		13
+#define TIM14		14
+#define LPTIM1		15
+#define SPI2		16
+#define SPI3		17
+#define USART2		18
+#define USART3		19
+#define UART4		20
+#define UART5		21
+#define UART7		22
+#define UART8		23
+#define I2C1		24
+#define I2C2		25
+#define I2C3		26
+#define I2C5		27
+#define SPDIF		28
+#define CEC		29
+#define DAC12		30
+#define MDIO		31
+#define TIM1		32
+#define TIM8		33
+#define TIM15		34
+#define TIM16		35
+#define TIM17		36
+#define SPI1		37
+#define SPI4		38
+#define SPI5		39
+#define USART6		40
+#define SAI1		41
+#define SAI2		42
+#define SAI3		43
+#define DFSDM		44
+#define FDCAN		45
+#define LPTIM2		46
+#define LPTIM3		47
+#define LPTIM4		48
+#define LPTIM5		49
+#define SAI4		50
+#define SYSCFG		51
+#define VREF		52
+#define TMPSENS		53
+#define PMBCTRL		54
+#define HDP		55
+#define LTDC		56
+#define DSI		57
+#define IWDG2		58
+#define USBPHY		59
+#define STGENRO		60
+#define SPI6		61
+#define I2C4		62
+#define I2C6		63
+#define USART1		64
+#define RTCAPB		65
+#define TZC1		66
+#define TZPC		67
+#define IWDG1		68
+#define BSEC		69
+#define STGEN		70
+#define DMA1		71
+#define DMA2		72
+#define DMAMUX		73
+#define ADC12		74
+#define USBO		75
+#define SDMMC3		76
+#define DCMI		77
+#define CRYP2		78
+#define HASH2		79
+#define RNG2		80
+#define CRC2		81
+#define HSEM		82
+#define IPCC		83
+#define GPIOA		84
+#define GPIOB		85
+#define GPIOC		86
+#define GPIOD		87
+#define GPIOE		88
+#define GPIOF		89
+#define GPIOG		90
+#define GPIOH		91
+#define GPIOI		92
+#define GPIOJ		93
+#define GPIOK		94
+#define GPIOZ		95
+#define CRYP1		96
+#define HASH1		97
+#define RNG1		98
+#define BKPSRAM		99
+#define MDMA		100
+#define GPU		101
+#define ETHCK		102
+#define ETHTX		103
+#define ETHRX		104
+#define ETHMAC		105
+#define FMC		106
+#define QSPI		107
+#define SDMMC1		108
+#define SDMMC2		109
+#define CRC1		110
+#define USBH		111
+#define ETHSTP		112
+#define TZC2		113
+
+/* Kernel clocks */
+#define SDMMC1_K	118
+#define SDMMC2_K	119
+#define SDMMC3_K	120
+#define FMC_K		121
+#define QSPI_K		122
+#define ETHCK_K		123
+#define RNG1_K		124
+#define RNG2_K		125
+#define GPU_K		126
+#define USBPHY_K	127
+#define STGEN_K		128
+#define SPDIF_K		129
+#define SPI1_K		130
+#define SPI2_K		131
+#define SPI3_K		132
+#define SPI4_K		133
+#define SPI5_K		134
+#define SPI6_K		135
+#define CEC_K		136
+#define I2C1_K		137
+#define I2C2_K		138
+#define I2C3_K		139
+#define I2C4_K		140
+#define I2C5_K		141
+#define I2C6_K		142
+#define LPTIM1_K	143
+#define LPTIM2_K	144
+#define LPTIM3_K	145
+#define LPTIM4_K	146
+#define LPTIM5_K	147
+#define USART1_K	148
+#define USART2_K	149
+#define USART3_K	150
+#define UART4_K		151
+#define UART5_K		152
+#define USART6_K	153
+#define UART7_K		154
+#define UART8_K		155
+#define DFSDM_K		156
+#define FDCAN_K		157
+#define SAI1_K		158
+#define SAI2_K		159
+#define SAI3_K		160
+#define SAI4_K		161
+#define ADC12_K		162
+#define DSI_K		163
+#define DSI_PX		164
+#define ADFSDM_K	165
+#define USBO_K		166
+#define LTDC_PX		167
+#define DAC12_K		168
+#define ETHPTP_K	169
+
+/* PLL */
+#define PLL1		176
+#define PLL2		177
+#define PLL3		178
+#define PLL4		179
+
+/* ODF */
+#define PLL1_P		180
+#define PLL1_Q		181
+#define PLL1_R		182
+#define PLL2_P		183
+#define PLL2_Q		184
+#define PLL2_R		185
+#define PLL3_P		186
+#define PLL3_Q		187
+#define PLL3_R		188
+#define PLL4_P		189
+#define PLL4_Q		190
+#define PLL4_R		191
+
+/* AUX */
+#define RTC		192
+
+/* MCLK */
+#define CK_PER		193
+#define CK_MPU		194
+#define CK_AXI		195
+#define CK_MCU		196
+
+/* Time base */
+#define TIM2_K		197
+#define TIM3_K		198
+#define TIM4_K		199
+#define TIM5_K		200
+#define TIM6_K		201
+#define TIM7_K		202
+#define TIM12_K		203
+#define TIM13_K		204
+#define TIM14_K		205
+#define TIM1_K		206
+#define TIM8_K		207
+#define TIM15_K		208
+#define TIM16_K		209
+#define TIM17_K		210
+
+/* MCO clocks */
+#define CK_MCO1		211
+#define CK_MCO2		212
+
+/* TRACE & DEBUG clocks */
+#define CK_DBG		214
+#define CK_TRACE	215
+
+/* DDR */
+#define DDRC1		220
+#define DDRC1LP		221
+#define DDRC2		222
+#define DDRC2LP		223
+#define DDRPHYC		224
+#define DDRPHYCLP	225
+#define DDRCAPB		226
+#define DDRCAPBLP	227
+#define AXIDCG		228
+#define DDRPHYCAPB	229
+#define DDRPHYCAPBLP	230
+#define DDRPERFM	231
+
+#define STM32MP1_LAST_CLK 232
+
+#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
diff --git a/include/dt-bindings/clock/stm32mp1-clksrc.h b/include/dt-bindings/clock/stm32mp1-clksrc.h
new file mode 100644
index 0000000..002ad53
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp1-clksrc.h
@@ -0,0 +1,284 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
+#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
+
+/* PLL output is enable when x=1, with x=p,q or r */
+#define PQR(p, q, r)	(((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
+
+/* st,clksrc: mandatory clock source */
+
+#define CLK_MPU_HSI		0x00000200
+#define CLK_MPU_HSE		0x00000201
+#define CLK_MPU_PLL1P		0x00000202
+#define CLK_MPU_PLL1P_DIV	0x00000203
+
+#define CLK_AXI_HSI		0x00000240
+#define CLK_AXI_HSE		0x00000241
+#define CLK_AXI_PLL2P		0x00000242
+
+#define CLK_MCU_HSI		0x00000480
+#define CLK_MCU_HSE		0x00000481
+#define CLK_MCU_CSI		0x00000482
+#define CLK_MCU_PLL3P		0x00000483
+
+#define CLK_PLL12_HSI		0x00000280
+#define CLK_PLL12_HSE		0x00000281
+
+#define CLK_PLL3_HSI		0x00008200
+#define CLK_PLL3_HSE		0x00008201
+#define CLK_PLL3_CSI		0x00008202
+
+#define CLK_PLL4_HSI		0x00008240
+#define CLK_PLL4_HSE		0x00008241
+#define CLK_PLL4_CSI		0x00008242
+#define CLK_PLL4_I2SCKIN	0x00008243
+
+#define CLK_RTC_DISABLED	0x00001400
+#define CLK_RTC_LSE		0x00001401
+#define CLK_RTC_LSI		0x00001402
+#define CLK_RTC_HSE		0x00001403
+
+#define CLK_MCO1_HSI		0x00008000
+#define CLK_MCO1_HSE		0x00008001
+#define CLK_MCO1_CSI		0x00008002
+#define CLK_MCO1_LSI		0x00008003
+#define CLK_MCO1_LSE		0x00008004
+#define CLK_MCO1_DISABLED	0x0000800F
+
+#define CLK_MCO2_MPU		0x00008040
+#define CLK_MCO2_AXI		0x00008041
+#define CLK_MCO2_MCU		0x00008042
+#define CLK_MCO2_PLL4P		0x00008043
+#define CLK_MCO2_HSE		0x00008044
+#define CLK_MCO2_HSI		0x00008045
+#define CLK_MCO2_DISABLED	0x0000804F
+
+/* st,pkcs: peripheral kernel clock source */
+
+#define CLK_I2C12_PCLK1		0x00008C00
+#define CLK_I2C12_PLL4R		0x00008C01
+#define CLK_I2C12_HSI		0x00008C02
+#define CLK_I2C12_CSI		0x00008C03
+#define CLK_I2C12_DISABLED	0x00008C07
+
+#define CLK_I2C35_PCLK1		0x00008C40
+#define CLK_I2C35_PLL4R		0x00008C41
+#define CLK_I2C35_HSI		0x00008C42
+#define CLK_I2C35_CSI		0x00008C43
+#define CLK_I2C35_DISABLED	0x00008C47
+
+#define CLK_I2C46_PCLK5		0x00000C00
+#define CLK_I2C46_PLL3Q		0x00000C01
+#define CLK_I2C46_HSI		0x00000C02
+#define CLK_I2C46_CSI		0x00000C03
+#define CLK_I2C46_DISABLED	0x00000C07
+
+#define CLK_SAI1_PLL4Q		0x00008C80
+#define CLK_SAI1_PLL3Q		0x00008C81
+#define CLK_SAI1_I2SCKIN	0x00008C82
+#define CLK_SAI1_CKPER		0x00008C83
+#define CLK_SAI1_PLL3R		0x00008C84
+#define CLK_SAI1_DISABLED	0x00008C87
+
+#define CLK_SAI2_PLL4Q		0x00008CC0
+#define CLK_SAI2_PLL3Q		0x00008CC1
+#define CLK_SAI2_I2SCKIN	0x00008CC2
+#define CLK_SAI2_CKPER		0x00008CC3
+#define CLK_SAI2_SPDIF		0x00008CC4
+#define CLK_SAI2_PLL3R		0x00008CC5
+#define CLK_SAI2_DISABLED	0x00008CC7
+
+#define CLK_SAI3_PLL4Q		0x00008D00
+#define CLK_SAI3_PLL3Q		0x00008D01
+#define CLK_SAI3_I2SCKIN	0x00008D02
+#define CLK_SAI3_CKPER		0x00008D03
+#define CLK_SAI3_PLL3R		0x00008D04
+#define CLK_SAI3_DISABLED	0x00008D07
+
+#define CLK_SAI4_PLL4Q		0x00008D40
+#define CLK_SAI4_PLL3Q		0x00008D41
+#define CLK_SAI4_I2SCKIN	0x00008D42
+#define CLK_SAI4_CKPER		0x00008D43
+#define CLK_SAI4_PLL3R		0x00008D44
+#define CLK_SAI4_DISABLED	0x00008D47
+
+#define CLK_SPI2S1_PLL4P	0x00008D80
+#define CLK_SPI2S1_PLL3Q	0x00008D81
+#define CLK_SPI2S1_I2SCKIN	0x00008D82
+#define CLK_SPI2S1_CKPER	0x00008D83
+#define CLK_SPI2S1_PLL3R	0x00008D84
+#define CLK_SPI2S1_DISABLED	0x00008D87
+
+#define CLK_SPI2S23_PLL4P	0x00008DC0
+#define CLK_SPI2S23_PLL3Q	0x00008DC1
+#define CLK_SPI2S23_I2SCKIN	0x00008DC2
+#define CLK_SPI2S23_CKPER	0x00008DC3
+#define CLK_SPI2S23_PLL3R	0x00008DC4
+#define CLK_SPI2S23_DISABLED	0x00008DC7
+
+#define CLK_SPI45_PCLK2		0x00008E00
+#define CLK_SPI45_PLL4Q		0x00008E01
+#define CLK_SPI45_HSI		0x00008E02
+#define CLK_SPI45_CSI		0x00008E03
+#define CLK_SPI45_HSE		0x00008E04
+#define CLK_SPI45_DISABLED	0x00008E07
+
+#define CLK_SPI6_PCLK5		0x00000C40
+#define CLK_SPI6_PLL4Q		0x00000C41
+#define CLK_SPI6_HSI		0x00000C42
+#define CLK_SPI6_CSI		0x00000C43
+#define CLK_SPI6_HSE		0x00000C44
+#define CLK_SPI6_PLL3Q		0x00000C45
+#define CLK_SPI6_DISABLED	0x00000C47
+
+#define CLK_UART6_PCLK2		0x00008E40
+#define CLK_UART6_PLL4Q		0x00008E41
+#define CLK_UART6_HSI		0x00008E42
+#define CLK_UART6_CSI		0x00008E43
+#define CLK_UART6_HSE		0x00008E44
+#define CLK_UART6_DISABLED	0x00008E47
+
+#define CLK_UART24_PCLK1	0x00008E80
+#define CLK_UART24_PLL4Q	0x00008E81
+#define CLK_UART24_HSI		0x00008E82
+#define CLK_UART24_CSI		0x00008E83
+#define CLK_UART24_HSE		0x00008E84
+#define CLK_UART24_DISABLED	0x00008E87
+
+#define CLK_UART35_PCLK1	0x00008EC0
+#define CLK_UART35_PLL4Q	0x00008EC1
+#define CLK_UART35_HSI		0x00008EC2
+#define CLK_UART35_CSI		0x00008EC3
+#define CLK_UART35_HSE		0x00008EC4
+#define CLK_UART35_DISABLED	0x00008EC7
+
+#define CLK_UART78_PCLK1	0x00008F00
+#define CLK_UART78_PLL4Q	0x00008F01
+#define CLK_UART78_HSI		0x00008F02
+#define CLK_UART78_CSI		0x00008F03
+#define CLK_UART78_HSE		0x00008F04
+#define CLK_UART78_DISABLED	0x00008F07
+
+#define CLK_UART1_PCLK5		0x00000C80
+#define CLK_UART1_PLL3Q		0x00000C81
+#define CLK_UART1_HSI		0x00000C82
+#define CLK_UART1_CSI		0x00000C83
+#define CLK_UART1_PLL4Q		0x00000C84
+#define CLK_UART1_HSE		0x00000C85
+#define CLK_UART1_DISABLED	0x00000C87
+
+#define CLK_SDMMC12_HCLK6	0x00008F40
+#define CLK_SDMMC12_PLL3R	0x00008F41
+#define CLK_SDMMC12_PLL4P	0x00008F42
+#define CLK_SDMMC12_HSI		0x00008F43
+#define CLK_SDMMC12_DISABLED	0x00008F47
+
+#define CLK_SDMMC3_HCLK2	0x00008F80
+#define CLK_SDMMC3_PLL3R	0x00008F81
+#define CLK_SDMMC3_PLL4P	0x00008F82
+#define CLK_SDMMC3_HSI		0x00008F83
+#define CLK_SDMMC3_DISABLED	0x00008F87
+
+#define CLK_ETH_PLL4P		0x00008FC0
+#define CLK_ETH_PLL3Q		0x00008FC1
+#define CLK_ETH_DISABLED	0x00008FC3
+
+#define CLK_QSPI_ACLK		0x00009000
+#define CLK_QSPI_PLL3R		0x00009001
+#define CLK_QSPI_PLL4P		0x00009002
+#define CLK_QSPI_CKPER		0x00009003
+
+#define CLK_FMC_ACLK		0x00009040
+#define CLK_FMC_PLL3R		0x00009041
+#define CLK_FMC_PLL4P		0x00009042
+#define CLK_FMC_CKPER		0x00009043
+
+#define CLK_FDCAN_HSE		0x000090C0
+#define CLK_FDCAN_PLL3Q		0x000090C1
+#define CLK_FDCAN_PLL4Q		0x000090C2
+#define CLK_FDCAN_PLL4R		0x000090C3
+
+#define CLK_SPDIF_PLL4P		0x00009140
+#define CLK_SPDIF_PLL3Q		0x00009141
+#define CLK_SPDIF_HSI		0x00009142
+#define CLK_SPDIF_DISABLED	0x00009143
+
+#define CLK_CEC_LSE		0x00009180
+#define CLK_CEC_LSI		0x00009181
+#define CLK_CEC_CSI_DIV122	0x00009182
+#define CLK_CEC_DISABLED	0x00009183
+
+#define CLK_USBPHY_HSE		0x000091C0
+#define CLK_USBPHY_PLL4R	0x000091C1
+#define CLK_USBPHY_HSE_DIV2	0x000091C2
+#define CLK_USBPHY_DISABLED	0x000091C3
+
+#define CLK_USBO_PLL4R		0x800091C0
+#define CLK_USBO_USBPHY		0x800091C1
+
+#define CLK_RNG1_CSI		0x00000CC0
+#define CLK_RNG1_PLL4R		0x00000CC1
+#define CLK_RNG1_LSE		0x00000CC2
+#define CLK_RNG1_LSI		0x00000CC3
+
+#define CLK_RNG2_CSI		0x00009200
+#define CLK_RNG2_PLL4R		0x00009201
+#define CLK_RNG2_LSE		0x00009202
+#define CLK_RNG2_LSI		0x00009203
+
+#define CLK_CKPER_HSI		0x00000D00
+#define CLK_CKPER_CSI		0x00000D01
+#define CLK_CKPER_HSE		0x00000D02
+#define CLK_CKPER_DISABLED	0x00000D03
+
+#define CLK_STGEN_HSI		0x00000D40
+#define CLK_STGEN_HSE		0x00000D41
+#define CLK_STGEN_DISABLED	0x00000D43
+
+#define CLK_DSI_DSIPLL		0x00009240
+#define CLK_DSI_PLL4P		0x00009241
+
+#define CLK_ADC_PLL4R		0x00009280
+#define CLK_ADC_CKPER		0x00009281
+#define CLK_ADC_PLL3Q		0x00009282
+#define CLK_ADC_DISABLED	0x00009283
+
+#define CLK_LPTIM45_PCLK3	0x000092C0
+#define CLK_LPTIM45_PLL4P	0x000092C1
+#define CLK_LPTIM45_PLL3Q	0x000092C2
+#define CLK_LPTIM45_LSE		0x000092C3
+#define CLK_LPTIM45_LSI		0x000092C4
+#define CLK_LPTIM45_CKPER	0x000092C5
+#define CLK_LPTIM45_DISABLED	0x000092C7
+
+#define CLK_LPTIM23_PCLK3	0x00009300
+#define CLK_LPTIM23_PLL4Q	0x00009301
+#define CLK_LPTIM23_CKPER	0x00009302
+#define CLK_LPTIM23_LSE		0x00009303
+#define CLK_LPTIM23_LSI		0x00009304
+#define CLK_LPTIM23_DISABLED	0x00009307
+
+#define CLK_LPTIM1_PCLK1	0x00009340
+#define CLK_LPTIM1_PLL4P	0x00009341
+#define CLK_LPTIM1_PLL3Q	0x00009342
+#define CLK_LPTIM1_LSE		0x00009343
+#define CLK_LPTIM1_LSI		0x00009344
+#define CLK_LPTIM1_CKPER	0x00009345
+#define CLK_LPTIM1_DISABLED	0x00009347
+
+/* define for st,pll /csg */
+#define SSCG_MODE_CENTER_SPREAD	0
+#define SSCG_MODE_DOWN_SPREAD	1
+
+/* define for st,drive */
+#define LSEDRV_LOWEST		0
+#define LSEDRV_MEDIUM_LOW	1
+#define LSEDRV_MEDIUM_HIGH	2
+#define LSEDRV_HIGHEST		3
+
+#endif
diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h
new file mode 100644
index 0000000..e4fa61b
--- /dev/null
+++ b/include/dt-bindings/clock/sun4i-a10-ccu.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
+#define _DT_BINDINGS_CLK_SUN4I_A10_H_
+
+#define CLK_HOSC		1
+#define CLK_PLL_VIDEO0_2X	9
+#define CLK_PLL_VIDEO1_2X	18
+#define CLK_CPU			20
+
+/* AHB Gates */
+#define CLK_AHB_OTG		26
+#define CLK_AHB_EHCI0		27
+#define CLK_AHB_OHCI0		28
+#define CLK_AHB_EHCI1		29
+#define CLK_AHB_OHCI1		30
+#define CLK_AHB_SS		31
+#define CLK_AHB_DMA		32
+#define CLK_AHB_BIST		33
+#define CLK_AHB_MMC0		34
+#define CLK_AHB_MMC1		35
+#define CLK_AHB_MMC2		36
+#define CLK_AHB_MMC3		37
+#define CLK_AHB_MS		38
+#define CLK_AHB_NAND		39
+#define CLK_AHB_SDRAM		40
+#define CLK_AHB_ACE		41
+#define CLK_AHB_EMAC		42
+#define CLK_AHB_TS		43
+#define CLK_AHB_SPI0		44
+#define CLK_AHB_SPI1		45
+#define CLK_AHB_SPI2		46
+#define CLK_AHB_SPI3		47
+#define CLK_AHB_PATA		48
+#define CLK_AHB_SATA		49
+#define CLK_AHB_GPS		50
+#define CLK_AHB_HSTIMER		51
+#define CLK_AHB_VE		52
+#define CLK_AHB_TVD		53
+#define CLK_AHB_TVE0		54
+#define CLK_AHB_TVE1		55
+#define CLK_AHB_LCD0		56
+#define CLK_AHB_LCD1		57
+#define CLK_AHB_CSI0		58
+#define CLK_AHB_CSI1		59
+#define CLK_AHB_HDMI0		60
+#define CLK_AHB_HDMI1		61
+#define CLK_AHB_DE_BE0		62
+#define CLK_AHB_DE_BE1		63
+#define CLK_AHB_DE_FE0		64
+#define CLK_AHB_DE_FE1		65
+#define CLK_AHB_GMAC		66
+#define CLK_AHB_MP		67
+#define CLK_AHB_GPU		68
+
+/* APB0 Gates */
+#define CLK_APB0_CODEC		69
+#define CLK_APB0_SPDIF		70
+#define CLK_APB0_I2S0		71
+#define CLK_APB0_AC97		72
+#define CLK_APB0_I2S1		73
+#define CLK_APB0_PIO		74
+#define CLK_APB0_IR0		75
+#define CLK_APB0_IR1		76
+#define CLK_APB0_I2S2		77
+#define CLK_APB0_KEYPAD		78
+
+/* APB1 Gates */
+#define CLK_APB1_I2C0		79
+#define CLK_APB1_I2C1		80
+#define CLK_APB1_I2C2		81
+#define CLK_APB1_I2C3		82
+#define CLK_APB1_CAN		83
+#define CLK_APB1_SCR		84
+#define CLK_APB1_PS20		85
+#define CLK_APB1_PS21		86
+#define CLK_APB1_I2C4		87
+#define CLK_APB1_UART0		88
+#define CLK_APB1_UART1		89
+#define CLK_APB1_UART2		90
+#define CLK_APB1_UART3		91
+#define CLK_APB1_UART4		92
+#define CLK_APB1_UART5		93
+#define CLK_APB1_UART6		94
+#define CLK_APB1_UART7		95
+
+/* IP clocks */
+#define CLK_NAND		96
+#define CLK_MS			97
+#define CLK_MMC0		98
+#define CLK_MMC0_OUTPUT		99
+#define CLK_MMC0_SAMPLE		100
+#define CLK_MMC1		101
+#define CLK_MMC1_OUTPUT		102
+#define CLK_MMC1_SAMPLE		103
+#define CLK_MMC2		104
+#define CLK_MMC2_OUTPUT		105
+#define CLK_MMC2_SAMPLE		106
+#define CLK_MMC3		107
+#define CLK_MMC3_OUTPUT		108
+#define CLK_MMC3_SAMPLE		109
+#define CLK_TS			110
+#define CLK_SS			111
+#define CLK_SPI0		112
+#define CLK_SPI1		113
+#define CLK_SPI2		114
+#define CLK_PATA		115
+#define CLK_IR0			116
+#define CLK_IR1			117
+#define CLK_I2S0		118
+#define CLK_AC97		119
+#define CLK_SPDIF		120
+#define CLK_KEYPAD		121
+#define CLK_SATA		122
+#define CLK_USB_OHCI0		123
+#define CLK_USB_OHCI1		124
+#define CLK_USB_PHY		125
+#define CLK_GPS			126
+#define CLK_SPI3		127
+#define CLK_I2S1		128
+#define CLK_I2S2		129
+
+/* DRAM Gates */
+#define CLK_DRAM_VE		130
+#define CLK_DRAM_CSI0		131
+#define CLK_DRAM_CSI1		132
+#define CLK_DRAM_TS		133
+#define CLK_DRAM_TVD		134
+#define CLK_DRAM_TVE0		135
+#define CLK_DRAM_TVE1		136
+#define CLK_DRAM_OUT		137
+#define CLK_DRAM_DE_FE1		138
+#define CLK_DRAM_DE_FE0		139
+#define CLK_DRAM_DE_BE0		140
+#define CLK_DRAM_DE_BE1		141
+#define CLK_DRAM_MP		142
+#define CLK_DRAM_ACE		143
+
+/* Display Engine Clocks */
+#define CLK_DE_BE0		144
+#define CLK_DE_BE1		145
+#define CLK_DE_FE0		146
+#define CLK_DE_FE1		147
+#define CLK_DE_MP		148
+#define CLK_TCON0_CH0		149
+#define CLK_TCON1_CH0		150
+#define CLK_CSI_SCLK		151
+#define CLK_TVD_SCLK2		152
+#define CLK_TVD			153
+#define CLK_TCON0_CH1_SCLK2	154
+#define CLK_TCON0_CH1		155
+#define CLK_TCON1_CH1_SCLK2	156
+#define CLK_TCON1_CH1		157
+#define CLK_CSI0		158
+#define CLK_CSI1		159
+#define CLK_CODEC		160
+#define CLK_VE			161
+#define CLK_AVS			162
+#define CLK_ACE			163
+#define CLK_HDMI		164
+#define CLK_GPU			165
+
+#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
diff --git a/include/dt-bindings/clock/sun4i-a10-pll2.h b/include/dt-bindings/clock/sun4i-a10-pll2.h
new file mode 100644
index 0000000..071c811
--- /dev/null
+++ b/include/dt-bindings/clock/sun4i-a10-pll2.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
+#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_
+
+#define SUN4I_A10_PLL2_1X	0
+#define SUN4I_A10_PLL2_2X	1
+#define SUN4I_A10_PLL2_4X	2
+#define SUN4I_A10_PLL2_8X	3
+
+#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
new file mode 100644
index 0000000..d66432c
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
+#define _DT_BINDINGS_CLK_SUN50I_A64_H_
+
+#define CLK_PLL_PERIPH0		11
+
+#define CLK_BUS_MIPI_DSI	28
+#define CLK_BUS_CE		29
+#define CLK_BUS_DMA		30
+#define CLK_BUS_MMC0		31
+#define CLK_BUS_MMC1		32
+#define CLK_BUS_MMC2		33
+#define CLK_BUS_NAND		34
+#define CLK_BUS_DRAM		35
+#define CLK_BUS_EMAC		36
+#define CLK_BUS_TS		37
+#define CLK_BUS_HSTIMER		38
+#define CLK_BUS_SPI0		39
+#define CLK_BUS_SPI1		40
+#define CLK_BUS_OTG		41
+#define CLK_BUS_EHCI0		42
+#define CLK_BUS_EHCI1		43
+#define CLK_BUS_OHCI0		44
+#define CLK_BUS_OHCI1		45
+#define CLK_BUS_VE		46
+#define CLK_BUS_TCON0		47
+#define CLK_BUS_TCON1		48
+#define CLK_BUS_DEINTERLACE	49
+#define CLK_BUS_CSI		50
+#define CLK_BUS_HDMI		51
+#define CLK_BUS_DE		52
+#define CLK_BUS_GPU		53
+#define CLK_BUS_MSGBOX		54
+#define CLK_BUS_SPINLOCK	55
+#define CLK_BUS_CODEC		56
+#define CLK_BUS_SPDIF		57
+#define CLK_BUS_PIO		58
+#define CLK_BUS_THS		59
+#define CLK_BUS_I2S0		60
+#define CLK_BUS_I2S1		61
+#define CLK_BUS_I2S2		62
+#define CLK_BUS_I2C0		63
+#define CLK_BUS_I2C1		64
+#define CLK_BUS_I2C2		65
+#define CLK_BUS_SCR		66
+#define CLK_BUS_UART0		67
+#define CLK_BUS_UART1		68
+#define CLK_BUS_UART2		69
+#define CLK_BUS_UART3		70
+#define CLK_BUS_UART4		71
+#define CLK_BUS_DBG		72
+#define CLK_THS			73
+#define CLK_NAND		74
+#define CLK_MMC0		75
+#define CLK_MMC1		76
+#define CLK_MMC2		77
+#define CLK_TS			78
+#define CLK_CE			79
+#define CLK_SPI0		80
+#define CLK_SPI1		81
+#define CLK_I2S0		82
+#define CLK_I2S1		83
+#define CLK_I2S2		84
+#define CLK_SPDIF		85
+#define CLK_USB_PHY0		86
+#define CLK_USB_PHY1		87
+#define CLK_USB_HSIC		88
+#define CLK_USB_HSIC_12M	89
+
+#define CLK_USB_OHCI0		91
+
+#define CLK_USB_OHCI1		93
+
+#define CLK_DRAM_VE		95
+#define CLK_DRAM_CSI		96
+#define CLK_DRAM_DEINTERLACE	97
+#define CLK_DRAM_TS		98
+#define CLK_DE			99
+#define CLK_TCON0		100
+#define CLK_TCON1		101
+#define CLK_DEINTERLACE		102
+#define CLK_CSI_MISC		103
+#define CLK_CSI_SCLK		104
+#define CLK_CSI_MCLK		105
+#define CLK_VE			106
+#define CLK_AC_DIG		107
+#define CLK_AC_DIG_4X		108
+#define CLK_AVS			109
+#define CLK_HDMI		110
+#define CLK_HDMI_DDC		111
+
+#define CLK_DSI_DPHY		113
+#define CLK_GPU			114
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */
diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h
new file mode 100644
index 0000000..a1545cd
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-h6-ccu.h
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_H_
+
+#define CLK_PLL_PERIPH0		3
+
+#define CLK_CPUX		21
+
+#define CLK_APB1		26
+
+#define CLK_DE			29
+#define CLK_BUS_DE		30
+#define CLK_DEINTERLACE		31
+#define CLK_BUS_DEINTERLACE	32
+#define CLK_GPU			33
+#define CLK_BUS_GPU		34
+#define CLK_CE			35
+#define CLK_BUS_CE		36
+#define CLK_VE			37
+#define CLK_BUS_VE		38
+#define CLK_EMCE		39
+#define CLK_BUS_EMCE		40
+#define CLK_VP9			41
+#define CLK_BUS_VP9		42
+#define CLK_BUS_DMA		43
+#define CLK_BUS_MSGBOX		44
+#define CLK_BUS_SPINLOCK	45
+#define CLK_BUS_HSTIMER		46
+#define CLK_AVS			47
+#define CLK_BUS_DBG		48
+#define CLK_BUS_PSI		49
+#define CLK_BUS_PWM		50
+#define CLK_BUS_IOMMU		51
+
+#define CLK_MBUS_DMA		53
+#define CLK_MBUS_VE		54
+#define CLK_MBUS_CE		55
+#define CLK_MBUS_TS		56
+#define CLK_MBUS_NAND		57
+#define CLK_MBUS_CSI		58
+#define CLK_MBUS_DEINTERLACE	59
+
+#define CLK_NAND0		61
+#define CLK_NAND1		62
+#define CLK_BUS_NAND		63
+#define CLK_MMC0		64
+#define CLK_MMC1		65
+#define CLK_MMC2		66
+#define CLK_BUS_MMC0		67
+#define CLK_BUS_MMC1		68
+#define CLK_BUS_MMC2		69
+#define CLK_BUS_UART0		70
+#define CLK_BUS_UART1		71
+#define CLK_BUS_UART2		72
+#define CLK_BUS_UART3		73
+#define CLK_BUS_I2C0		74
+#define CLK_BUS_I2C1		75
+#define CLK_BUS_I2C2		76
+#define CLK_BUS_I2C3		77
+#define CLK_BUS_SCR0		78
+#define CLK_BUS_SCR1		79
+#define CLK_SPI0		80
+#define CLK_SPI1		81
+#define CLK_BUS_SPI0		82
+#define CLK_BUS_SPI1		83
+#define CLK_BUS_EMAC		84
+#define CLK_TS			85
+#define CLK_BUS_TS		86
+#define CLK_IR_TX		87
+#define CLK_BUS_IR_TX		88
+#define CLK_BUS_THS		89
+#define CLK_I2S3		90
+#define CLK_I2S0		91
+#define CLK_I2S1		92
+#define CLK_I2S2		93
+#define CLK_BUS_I2S0		94
+#define CLK_BUS_I2S1		95
+#define CLK_BUS_I2S2		96
+#define CLK_BUS_I2S3		97
+#define CLK_SPDIF		98
+#define CLK_BUS_SPDIF		99
+#define CLK_DMIC		100
+#define CLK_BUS_DMIC		101
+#define CLK_AUDIO_HUB		102
+#define CLK_BUS_AUDIO_HUB	103
+#define CLK_USB_OHCI0		104
+#define CLK_USB_PHY0		105
+#define CLK_USB_PHY1		106
+#define CLK_USB_OHCI3		107
+#define CLK_USB_PHY3		108
+#define CLK_USB_HSIC_12M	109
+#define CLK_USB_HSIC		110
+#define CLK_BUS_OHCI0		111
+#define CLK_BUS_OHCI3		112
+#define CLK_BUS_EHCI0		113
+#define CLK_BUS_XHCI		114
+#define CLK_BUS_EHCI3		115
+#define CLK_BUS_OTG		116
+#define CLK_PCIE_REF_100M	117
+#define CLK_PCIE_REF		118
+#define CLK_PCIE_REF_OUT	119
+#define CLK_PCIE_MAXI		120
+#define CLK_PCIE_AUX		121
+#define CLK_BUS_PCIE		122
+#define CLK_HDMI		123
+#define CLK_HDMI_SLOW		124
+#define CLK_HDMI_CEC		125
+#define CLK_BUS_HDMI		126
+#define CLK_BUS_TCON_TOP	127
+#define CLK_TCON_LCD0		128
+#define CLK_BUS_TCON_LCD0	129
+#define CLK_TCON_TV0		130
+#define CLK_BUS_TCON_TV0	131
+#define CLK_CSI_CCI		132
+#define CLK_CSI_TOP		133
+#define CLK_CSI_MCLK		134
+#define CLK_BUS_CSI		135
+#define CLK_HDCP		136
+#define CLK_BUS_HDCP		137
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
new file mode 100644
index 0000000..7613613
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
+
+#define CLK_AR100		0
+
+#define CLK_R_APB1		2
+
+#define CLK_R_APB1_TIMER	4
+#define CLK_R_APB1_TWD		5
+#define CLK_R_APB1_PWM		6
+#define CLK_R_APB2_UART		7
+#define CLK_R_APB2_I2C		8
+#define CLK_R_APB1_IR		9
+#define CLK_R_APB1_W1		10
+
+#define CLK_IR			11
+#define CLK_W1			12
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h
new file mode 100644
index 0000000..81f34d4
--- /dev/null
+++ b/include/dt-bindings/clock/sun5i-ccu.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2016 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN5I_H_
+#define _DT_BINDINGS_CLK_SUN5I_H_
+
+#define CLK_HOSC		1
+
+#define CLK_PLL_VIDEO0_2X	9
+
+#define CLK_PLL_VIDEO1_2X	16
+#define CLK_CPU			17
+
+#define CLK_AHB_OTG		23
+#define CLK_AHB_EHCI		24
+#define CLK_AHB_OHCI		25
+#define CLK_AHB_SS		26
+#define CLK_AHB_DMA		27
+#define CLK_AHB_BIST		28
+#define CLK_AHB_MMC0		29
+#define CLK_AHB_MMC1		30
+#define CLK_AHB_MMC2		31
+#define CLK_AHB_NAND		32
+#define CLK_AHB_SDRAM		33
+#define CLK_AHB_EMAC		34
+#define CLK_AHB_TS		35
+#define CLK_AHB_SPI0		36
+#define CLK_AHB_SPI1		37
+#define CLK_AHB_SPI2		38
+#define CLK_AHB_GPS		39
+#define CLK_AHB_HSTIMER		40
+#define CLK_AHB_VE		41
+#define CLK_AHB_TVE		42
+#define CLK_AHB_LCD		43
+#define CLK_AHB_CSI		44
+#define CLK_AHB_HDMI		45
+#define CLK_AHB_DE_BE		46
+#define CLK_AHB_DE_FE		47
+#define CLK_AHB_IEP		48
+#define CLK_AHB_GPU		49
+#define CLK_APB0_CODEC		50
+#define CLK_APB0_SPDIF		51
+#define CLK_APB0_I2S		52
+#define CLK_APB0_PIO		53
+#define CLK_APB0_IR		54
+#define CLK_APB0_KEYPAD		55
+#define CLK_APB1_I2C0		56
+#define CLK_APB1_I2C1		57
+#define CLK_APB1_I2C2		58
+#define CLK_APB1_UART0		59
+#define CLK_APB1_UART1		60
+#define CLK_APB1_UART2		61
+#define CLK_APB1_UART3		62
+#define CLK_NAND		63
+#define CLK_MMC0		64
+#define CLK_MMC1		65
+#define CLK_MMC2		66
+#define CLK_TS			67
+#define CLK_SS			68
+#define CLK_SPI0		69
+#define CLK_SPI1		70
+#define CLK_SPI2		71
+#define CLK_IR			72
+#define CLK_I2S			73
+#define CLK_SPDIF		74
+#define CLK_KEYPAD		75
+#define CLK_USB_OHCI		76
+#define CLK_USB_PHY0		77
+#define CLK_USB_PHY1		78
+#define CLK_GPS			79
+#define CLK_DRAM_VE		80
+#define CLK_DRAM_CSI		81
+#define CLK_DRAM_TS		82
+#define CLK_DRAM_TVE		83
+#define CLK_DRAM_DE_FE		84
+#define CLK_DRAM_DE_BE		85
+#define CLK_DRAM_ACE		86
+#define CLK_DRAM_IEP		87
+#define CLK_DE_BE		88
+#define CLK_DE_FE		89
+#define CLK_TCON_CH0		90
+
+#define CLK_TCON_CH1		92
+#define CLK_CSI			93
+#define CLK_VE			94
+#define CLK_CODEC		95
+#define CLK_AVS			96
+#define CLK_HDMI		97
+#define CLK_GPU			98
+
+#define CLK_IEP			100
+
+#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h
new file mode 100644
index 0000000..c5d1334
--- /dev/null
+++ b/include/dt-bindings/clock/sun6i-a31-ccu.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
+#define _DT_BINDINGS_CLK_SUN6I_A31_H_
+
+#define CLK_PLL_VIDEO0_2X	7
+
+#define CLK_PLL_PERIPH		10
+
+#define CLK_PLL_VIDEO1_2X	13
+
+#define CLK_CPU			18
+
+#define CLK_AHB1_MIPIDSI	23
+#define CLK_AHB1_SS		24
+#define CLK_AHB1_DMA		25
+#define CLK_AHB1_MMC0		26
+#define CLK_AHB1_MMC1		27
+#define CLK_AHB1_MMC2		28
+#define CLK_AHB1_MMC3		29
+#define CLK_AHB1_NAND1		30
+#define CLK_AHB1_NAND0		31
+#define CLK_AHB1_SDRAM		32
+#define CLK_AHB1_EMAC		33
+#define CLK_AHB1_TS		34
+#define CLK_AHB1_HSTIMER	35
+#define CLK_AHB1_SPI0		36
+#define CLK_AHB1_SPI1		37
+#define CLK_AHB1_SPI2		38
+#define CLK_AHB1_SPI3		39
+#define CLK_AHB1_OTG		40
+#define CLK_AHB1_EHCI0		41
+#define CLK_AHB1_EHCI1		42
+#define CLK_AHB1_OHCI0		43
+#define CLK_AHB1_OHCI1		44
+#define CLK_AHB1_OHCI2		45
+#define CLK_AHB1_VE		46
+#define CLK_AHB1_LCD0		47
+#define CLK_AHB1_LCD1		48
+#define CLK_AHB1_CSI		49
+#define CLK_AHB1_HDMI		50
+#define CLK_AHB1_BE0		51
+#define CLK_AHB1_BE1		52
+#define CLK_AHB1_FE0		53
+#define CLK_AHB1_FE1		54
+#define CLK_AHB1_MP		55
+#define CLK_AHB1_GPU		56
+#define CLK_AHB1_DEU0		57
+#define CLK_AHB1_DEU1		58
+#define CLK_AHB1_DRC0		59
+#define CLK_AHB1_DRC1		60
+
+#define CLK_APB1_CODEC		61
+#define CLK_APB1_SPDIF		62
+#define CLK_APB1_DIGITAL_MIC	63
+#define CLK_APB1_PIO		64
+#define CLK_APB1_DAUDIO0	65
+#define CLK_APB1_DAUDIO1	66
+
+#define CLK_APB2_I2C0		67
+#define CLK_APB2_I2C1		68
+#define CLK_APB2_I2C2		69
+#define CLK_APB2_I2C3		70
+#define CLK_APB2_UART0		71
+#define CLK_APB2_UART1		72
+#define CLK_APB2_UART2		73
+#define CLK_APB2_UART3		74
+#define CLK_APB2_UART4		75
+#define CLK_APB2_UART5		76
+
+#define CLK_NAND0		77
+#define CLK_NAND1		78
+#define CLK_MMC0		79
+#define CLK_MMC0_SAMPLE		80
+#define CLK_MMC0_OUTPUT		81
+#define CLK_MMC1		82
+#define CLK_MMC1_SAMPLE		83
+#define CLK_MMC1_OUTPUT		84
+#define CLK_MMC2		85
+#define CLK_MMC2_SAMPLE		86
+#define CLK_MMC2_OUTPUT		87
+#define CLK_MMC3		88
+#define CLK_MMC3_SAMPLE		89
+#define CLK_MMC3_OUTPUT		90
+#define CLK_TS			91
+#define CLK_SS			92
+#define CLK_SPI0		93
+#define CLK_SPI1		94
+#define CLK_SPI2		95
+#define CLK_SPI3		96
+#define CLK_DAUDIO0		97
+#define CLK_DAUDIO1		98
+#define CLK_SPDIF		99
+#define CLK_USB_PHY0		100
+#define CLK_USB_PHY1		101
+#define CLK_USB_PHY2		102
+#define CLK_USB_OHCI0		103
+#define CLK_USB_OHCI1		104
+#define CLK_USB_OHCI2		105
+
+#define CLK_DRAM_VE		110
+#define CLK_DRAM_CSI_ISP	111
+#define CLK_DRAM_TS		112
+#define CLK_DRAM_DRC0		113
+#define CLK_DRAM_DRC1		114
+#define CLK_DRAM_DEU0		115
+#define CLK_DRAM_DEU1		116
+#define CLK_DRAM_FE0		117
+#define CLK_DRAM_FE1		118
+#define CLK_DRAM_BE0		119
+#define CLK_DRAM_BE1		120
+#define CLK_DRAM_MP		121
+
+#define CLK_BE0			122
+#define CLK_BE1			123
+#define CLK_FE0			124
+#define CLK_FE1			125
+#define CLK_MP			126
+#define CLK_LCD0_CH0		127
+#define CLK_LCD1_CH0		128
+#define CLK_LCD0_CH1		129
+#define CLK_LCD1_CH1		130
+#define CLK_CSI0_SCLK		131
+#define CLK_CSI0_MCLK		132
+#define CLK_CSI1_MCLK		133
+#define CLK_VE			134
+#define CLK_CODEC		135
+#define CLK_AVS			136
+#define CLK_DIGITAL_MIC		137
+#define CLK_HDMI		138
+#define CLK_HDMI_DDC		139
+#define CLK_PS			140
+
+#define CLK_MIPI_DSI		143
+#define CLK_MIPI_DSI_DPHY	144
+#define CLK_MIPI_CSI_DPHY	145
+#define CLK_IEP_DRC0		146
+#define CLK_IEP_DRC1		147
+#define CLK_IEP_DEU0		148
+#define CLK_IEP_DEU1		149
+#define CLK_GPU_CORE		150
+#define CLK_GPU_MEMORY		151
+#define CLK_GPU_HYD		152
+#define CLK_ATS			153
+#define CLK_TRACE		154
+
+#define CLK_OUT_A		155
+#define CLK_OUT_B		156
+#define CLK_OUT_C		157
+
+#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */
diff --git a/include/dt-bindings/clock/sun7i-a20-ccu.h b/include/dt-bindings/clock/sun7i-a20-ccu.h
new file mode 100644
index 0000000..045a517
--- /dev/null
+++ b/include/dt-bindings/clock/sun7i-a20-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_
+#define _DT_BINDINGS_CLK_SUN7I_A20_H_
+
+#include <dt-bindings/clock/sun4i-a10-ccu.h>
+
+#define CLK_MBUS		166
+#define CLK_HDMI1_SLOW		167
+#define CLK_HDMI1		168
+#define CLK_OUT_A		169
+#define CLK_OUT_B		170
+
+#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */
diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
new file mode 100644
index 0000000..f8222b6
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
+#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
+
+#define CLK_CPUX		18
+
+#define CLK_BUS_MIPI_DSI	23
+#define CLK_BUS_SS		24
+#define CLK_BUS_DMA		25
+#define CLK_BUS_MMC0		26
+#define CLK_BUS_MMC1		27
+#define CLK_BUS_MMC2		28
+#define CLK_BUS_NAND		29
+#define CLK_BUS_DRAM		30
+#define CLK_BUS_HSTIMER		31
+#define CLK_BUS_SPI0		32
+#define CLK_BUS_SPI1		33
+#define CLK_BUS_OTG		34
+#define CLK_BUS_EHCI		35
+#define CLK_BUS_OHCI		36
+#define CLK_BUS_VE		37
+#define CLK_BUS_LCD		38
+#define CLK_BUS_CSI		39
+#define CLK_BUS_DE_BE		40
+#define CLK_BUS_DE_FE		41
+#define CLK_BUS_GPU		42
+#define CLK_BUS_MSGBOX		43
+#define CLK_BUS_SPINLOCK	44
+#define CLK_BUS_DRC		45
+#define CLK_BUS_SAT		46
+#define CLK_BUS_CODEC		47
+#define CLK_BUS_PIO		48
+#define CLK_BUS_I2S0		49
+#define CLK_BUS_I2S1		50
+#define CLK_BUS_I2C0		51
+#define CLK_BUS_I2C1		52
+#define CLK_BUS_I2C2		53
+#define CLK_BUS_UART0		54
+#define CLK_BUS_UART1		55
+#define CLK_BUS_UART2		56
+#define CLK_BUS_UART3		57
+#define CLK_BUS_UART4		58
+#define CLK_NAND		59
+#define CLK_MMC0		60
+#define CLK_MMC0_SAMPLE		61
+#define CLK_MMC0_OUTPUT		62
+#define CLK_MMC1		63
+#define CLK_MMC1_SAMPLE		64
+#define CLK_MMC1_OUTPUT		65
+#define CLK_MMC2		66
+#define CLK_MMC2_SAMPLE		67
+#define CLK_MMC2_OUTPUT		68
+#define CLK_SS			69
+#define CLK_SPI0		70
+#define CLK_SPI1		71
+#define CLK_I2S0		72
+#define CLK_I2S1		73
+#define CLK_USB_PHY0		74
+#define CLK_USB_PHY1		75
+#define CLK_USB_HSIC		76
+#define CLK_USB_HSIC_12M	77
+#define CLK_USB_OHCI		78
+
+#define CLK_DRAM_VE		80
+#define CLK_DRAM_CSI		81
+#define CLK_DRAM_DRC		82
+#define CLK_DRAM_DE_FE		83
+#define CLK_DRAM_DE_BE		84
+#define CLK_DE_BE		85
+#define CLK_DE_FE		86
+#define CLK_LCD_CH0		87
+#define CLK_LCD_CH1		88
+#define CLK_CSI_SCLK		89
+#define CLK_CSI_MCLK		90
+#define CLK_VE			91
+#define CLK_AC_DIG		92
+#define CLK_AC_DIG_4X		93
+#define CLK_AVS			94
+
+#define CLK_DSI_SCLK		96
+#define CLK_DSI_DPHY		97
+#define CLK_DRC			98
+#define CLK_GPU			99
+#define CLK_ATS			100
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */
diff --git a/include/dt-bindings/clock/sun8i-a83t-ccu.h b/include/dt-bindings/clock/sun8i-a83t-ccu.h
new file mode 100644
index 0000000..78af508
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-a83t-ccu.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
+
+#define CLK_PLL_PERIPH		6
+
+#define CLK_PLL_DE		9
+
+#define CLK_C0CPUX		11
+#define CLK_C1CPUX		12
+
+#define CLK_BUS_MIPI_DSI	19
+#define CLK_BUS_SS		20
+#define CLK_BUS_DMA		21
+#define CLK_BUS_MMC0		22
+#define CLK_BUS_MMC1		23
+#define CLK_BUS_MMC2		24
+#define CLK_BUS_NAND		25
+#define CLK_BUS_DRAM		26
+#define CLK_BUS_EMAC		27
+#define CLK_BUS_HSTIMER		28
+#define CLK_BUS_SPI0		29
+#define CLK_BUS_SPI1		30
+#define CLK_BUS_OTG		31
+#define CLK_BUS_EHCI0		32
+#define CLK_BUS_EHCI1		33
+#define CLK_BUS_OHCI0		34
+
+#define CLK_BUS_VE		35
+#define CLK_BUS_TCON0		36
+#define CLK_BUS_TCON1		37
+#define CLK_BUS_CSI		38
+#define CLK_BUS_HDMI		39
+#define CLK_BUS_DE		40
+#define CLK_BUS_GPU		41
+#define CLK_BUS_MSGBOX		42
+#define CLK_BUS_SPINLOCK	43
+
+#define CLK_BUS_SPDIF		44
+#define CLK_BUS_PIO		45
+#define CLK_BUS_I2S0		46
+#define CLK_BUS_I2S1		47
+#define CLK_BUS_I2S2		48
+#define CLK_BUS_TDM		49
+
+#define CLK_BUS_I2C0		50
+#define CLK_BUS_I2C1		51
+#define CLK_BUS_I2C2		52
+#define CLK_BUS_UART0		53
+#define CLK_BUS_UART1		54
+#define CLK_BUS_UART2		55
+#define CLK_BUS_UART3		56
+#define CLK_BUS_UART4		57
+
+#define CLK_NAND		59
+#define CLK_MMC0		60
+#define CLK_MMC0_SAMPLE		61
+#define CLK_MMC0_OUTPUT		62
+#define CLK_MMC1		63
+#define CLK_MMC1_SAMPLE		64
+#define CLK_MMC1_OUTPUT		65
+#define CLK_MMC2		66
+#define CLK_MMC2_SAMPLE		67
+#define CLK_MMC2_OUTPUT		68
+#define CLK_SS			69
+#define CLK_SPI0		70
+#define CLK_SPI1		71
+#define CLK_I2S0		72
+#define CLK_I2S1		73
+#define CLK_I2S2		74
+#define CLK_TDM			75
+#define CLK_SPDIF		76
+#define CLK_USB_PHY0		77
+#define CLK_USB_PHY1		78
+#define CLK_USB_HSIC		79
+#define CLK_USB_HSIC_12M	80
+#define CLK_USB_OHCI0		81
+
+#define CLK_DRAM_VE		83
+#define CLK_DRAM_CSI		84
+
+#define CLK_TCON0		85
+#define CLK_TCON1		86
+#define CLK_CSI_MISC		87
+#define CLK_MIPI_CSI		88
+#define CLK_CSI_MCLK		89
+#define CLK_CSI_SCLK		90
+#define CLK_VE			91
+#define CLK_AVS			92
+#define CLK_HDMI		93
+#define CLK_HDMI_SLOW		94
+
+#define CLK_MIPI_DSI0		96
+#define CLK_MIPI_DSI1		97
+#define CLK_GPU_CORE		98
+#define CLK_GPU_MEMORY		99
+#define CLK_GPU_HYD		100
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun8i-de2.h b/include/dt-bindings/clock/sun8i-de2.h
new file mode 100644
index 0000000..3bed63b
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-de2.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
+
+#define CLK_BUS_MIXER0		0
+#define CLK_BUS_MIXER1		1
+#define CLK_BUS_WB		2
+
+#define CLK_MIXER0		6
+#define CLK_MIXER1		7
+#define CLK_WB			8
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
new file mode 100644
index 0000000..efb7ba2
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
+#define _DT_BINDINGS_CLK_SUN8I_H3_H_
+
+#define CLK_CPUX		14
+
+#define CLK_BUS_CE		20
+#define CLK_BUS_DMA		21
+#define CLK_BUS_MMC0		22
+#define CLK_BUS_MMC1		23
+#define CLK_BUS_MMC2		24
+#define CLK_BUS_NAND		25
+#define CLK_BUS_DRAM		26
+#define CLK_BUS_EMAC		27
+#define CLK_BUS_TS		28
+#define CLK_BUS_HSTIMER		29
+#define CLK_BUS_SPI0		30
+#define CLK_BUS_SPI1		31
+#define CLK_BUS_OTG		32
+#define CLK_BUS_EHCI0		33
+#define CLK_BUS_EHCI1		34
+#define CLK_BUS_EHCI2		35
+#define CLK_BUS_EHCI3		36
+#define CLK_BUS_OHCI0		37
+#define CLK_BUS_OHCI1		38
+#define CLK_BUS_OHCI2		39
+#define CLK_BUS_OHCI3		40
+#define CLK_BUS_VE		41
+#define CLK_BUS_TCON0		42
+#define CLK_BUS_TCON1		43
+#define CLK_BUS_DEINTERLACE	44
+#define CLK_BUS_CSI		45
+#define CLK_BUS_TVE		46
+#define CLK_BUS_HDMI		47
+#define CLK_BUS_DE		48
+#define CLK_BUS_GPU		49
+#define CLK_BUS_MSGBOX		50
+#define CLK_BUS_SPINLOCK	51
+#define CLK_BUS_CODEC		52
+#define CLK_BUS_SPDIF		53
+#define CLK_BUS_PIO		54
+#define CLK_BUS_THS		55
+#define CLK_BUS_I2S0		56
+#define CLK_BUS_I2S1		57
+#define CLK_BUS_I2S2		58
+#define CLK_BUS_I2C0		59
+#define CLK_BUS_I2C1		60
+#define CLK_BUS_I2C2		61
+#define CLK_BUS_UART0		62
+#define CLK_BUS_UART1		63
+#define CLK_BUS_UART2		64
+#define CLK_BUS_UART3		65
+#define CLK_BUS_SCR		66
+#define CLK_BUS_EPHY		67
+#define CLK_BUS_DBG		68
+
+#define CLK_THS			69
+#define CLK_NAND		70
+#define CLK_MMC0		71
+#define CLK_MMC0_SAMPLE		72
+#define CLK_MMC0_OUTPUT		73
+#define CLK_MMC1		74
+#define CLK_MMC1_SAMPLE		75
+#define CLK_MMC1_OUTPUT		76
+#define CLK_MMC2		77
+#define CLK_MMC2_SAMPLE		78
+#define CLK_MMC2_OUTPUT		79
+#define CLK_TS			80
+#define CLK_CE			81
+#define CLK_SPI0		82
+#define CLK_SPI1		83
+#define CLK_I2S0		84
+#define CLK_I2S1		85
+#define CLK_I2S2		86
+#define CLK_SPDIF		87
+#define CLK_USB_PHY0		88
+#define CLK_USB_PHY1		89
+#define CLK_USB_PHY2		90
+#define CLK_USB_PHY3		91
+#define CLK_USB_OHCI0		92
+#define CLK_USB_OHCI1		93
+#define CLK_USB_OHCI2		94
+#define CLK_USB_OHCI3		95
+
+#define CLK_DRAM_VE		97
+#define CLK_DRAM_CSI		98
+#define CLK_DRAM_DEINTERLACE	99
+#define CLK_DRAM_TS		100
+#define CLK_DE			101
+#define CLK_TCON0		102
+#define CLK_TVE			103
+#define CLK_DEINTERLACE		104
+#define CLK_CSI_MISC		105
+#define CLK_CSI_SCLK		106
+#define CLK_CSI_MCLK		107
+#define CLK_VE			108
+#define CLK_AC_DIG		109
+#define CLK_AVS			110
+#define CLK_HDMI		111
+#define CLK_HDMI_DDC		112
+
+#define CLK_GPU			114
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h
new file mode 100644
index 0000000..779d20a
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-r-ccu.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
+
+#define CLK_AR100		0
+
+#define CLK_APB0_PIO		3
+#define CLK_APB0_IR		4
+#define CLK_APB0_TIMER		5
+#define CLK_APB0_RSB		6
+#define CLK_APB0_UART		7
+/* 8 is reserved for CLK_APB0_W1 on A31 */
+#define CLK_APB0_I2C		9
+#define CLK_APB0_TWD		10
+
+#define CLK_IR			11
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h
new file mode 100644
index 0000000..4fa5f69
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
+#define _DT_BINDINGS_CLK_SUN8I_R40_H_
+
+#define CLK_CPU			24
+
+#define CLK_BUS_MIPI_DSI	29
+#define CLK_BUS_CE		30
+#define CLK_BUS_DMA		31
+#define CLK_BUS_MMC0		32
+#define CLK_BUS_MMC1		33
+#define CLK_BUS_MMC2		34
+#define CLK_BUS_MMC3		35
+#define CLK_BUS_NAND		36
+#define CLK_BUS_DRAM		37
+#define CLK_BUS_EMAC		38
+#define CLK_BUS_TS		39
+#define CLK_BUS_HSTIMER		40
+#define CLK_BUS_SPI0		41
+#define CLK_BUS_SPI1		42
+#define CLK_BUS_SPI2		43
+#define CLK_BUS_SPI3		44
+#define CLK_BUS_SATA		45
+#define CLK_BUS_OTG		46
+#define CLK_BUS_EHCI0		47
+#define CLK_BUS_EHCI1		48
+#define CLK_BUS_EHCI2		49
+#define CLK_BUS_OHCI0		50
+#define CLK_BUS_OHCI1		51
+#define CLK_BUS_OHCI2		52
+#define CLK_BUS_VE		53
+#define CLK_BUS_MP		54
+#define CLK_BUS_DEINTERLACE	55
+#define CLK_BUS_CSI0		56
+#define CLK_BUS_CSI1		57
+#define CLK_BUS_HDMI1		58
+#define CLK_BUS_HDMI0		59
+#define CLK_BUS_DE		60
+#define CLK_BUS_TVE0		61
+#define CLK_BUS_TVE1		62
+#define CLK_BUS_TVE_TOP		63
+#define CLK_BUS_GMAC		64
+#define CLK_BUS_GPU		65
+#define CLK_BUS_TVD0		66
+#define CLK_BUS_TVD1		67
+#define CLK_BUS_TVD2		68
+#define CLK_BUS_TVD3		69
+#define CLK_BUS_TVD_TOP		70
+#define CLK_BUS_TCON_LCD0	71
+#define CLK_BUS_TCON_LCD1	72
+#define CLK_BUS_TCON_TV0	73
+#define CLK_BUS_TCON_TV1	74
+#define CLK_BUS_TCON_TOP	75
+#define CLK_BUS_CODEC		76
+#define CLK_BUS_SPDIF		77
+#define CLK_BUS_AC97		78
+#define CLK_BUS_PIO		79
+#define CLK_BUS_IR0		80
+#define CLK_BUS_IR1		81
+#define CLK_BUS_THS		82
+#define CLK_BUS_KEYPAD		83
+#define CLK_BUS_I2S0		84
+#define CLK_BUS_I2S1		85
+#define CLK_BUS_I2S2		86
+#define CLK_BUS_I2C0		87
+#define CLK_BUS_I2C1		88
+#define CLK_BUS_I2C2		89
+#define CLK_BUS_I2C3		90
+#define CLK_BUS_CAN		91
+#define CLK_BUS_SCR		92
+#define CLK_BUS_PS20		93
+#define CLK_BUS_PS21		94
+#define CLK_BUS_I2C4		95
+#define CLK_BUS_UART0		96
+#define CLK_BUS_UART1		97
+#define CLK_BUS_UART2		98
+#define CLK_BUS_UART3		99
+#define CLK_BUS_UART4		100
+#define CLK_BUS_UART5		101
+#define CLK_BUS_UART6		102
+#define CLK_BUS_UART7		103
+#define CLK_BUS_DBG		104
+
+#define CLK_THS			105
+#define CLK_NAND		106
+#define CLK_MMC0		107
+#define CLK_MMC1		108
+#define CLK_MMC2		109
+#define CLK_MMC3		110
+#define CLK_TS			111
+#define CLK_CE			112
+#define CLK_SPI0		113
+#define CLK_SPI1		114
+#define CLK_SPI2		115
+#define CLK_SPI3		116
+#define CLK_I2S0		117
+#define CLK_I2S1		118
+#define CLK_I2S2		119
+#define CLK_AC97		120
+#define CLK_SPDIF		121
+#define CLK_KEYPAD		122
+#define CLK_SATA		123
+#define CLK_USB_PHY0		124
+#define CLK_USB_PHY1		125
+#define CLK_USB_PHY2		126
+#define CLK_USB_OHCI0		127
+#define CLK_USB_OHCI1		128
+#define CLK_USB_OHCI2		129
+#define CLK_IR0			130
+#define CLK_IR1			131
+
+#define CLK_DRAM_VE		133
+#define CLK_DRAM_CSI0		134
+#define CLK_DRAM_CSI1		135
+#define CLK_DRAM_TS		136
+#define CLK_DRAM_TVD		137
+#define CLK_DRAM_MP		138
+#define CLK_DRAM_DEINTERLACE	139
+#define CLK_DE			140
+#define CLK_MP			141
+#define CLK_TCON_LCD0		142
+#define CLK_TCON_LCD1		143
+#define CLK_TCON_TV0		144
+#define CLK_TCON_TV1		145
+#define CLK_DEINTERLACE		146
+#define CLK_CSI1_MCLK		147
+#define CLK_CSI_SCLK		148
+#define CLK_CSI0_MCLK		149
+#define CLK_VE			150
+#define CLK_CODEC		151
+#define CLK_AVS			152
+#define CLK_HDMI		153
+#define CLK_HDMI_SLOW		154
+
+#define CLK_DSI_DPHY		156
+#define CLK_TVE0		157
+#define CLK_TVE1		158
+#define CLK_TVD0		159
+#define CLK_TVD1		160
+#define CLK_TVD2		161
+#define CLK_TVD3		162
+#define CLK_GPU			163
+#define CLK_OUTA		164
+#define CLK_OUTB		165
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */
diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h
new file mode 100644
index 0000000..25164d7
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-tcon-top.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+
+#define CLK_TCON_TOP_TV0	0
+#define CLK_TCON_TOP_TV1	1
+#define CLK_TCON_TOP_DSI	2
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */
diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
new file mode 100644
index 0000000..c0d5d55
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun8i-h3-ccu.h, which is:
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_
+#define _DT_BINDINGS_CLK_SUN8I_V3S_H_
+
+#define CLK_CPU			14
+
+#define CLK_BUS_CE		20
+#define CLK_BUS_DMA		21
+#define CLK_BUS_MMC0		22
+#define CLK_BUS_MMC1		23
+#define CLK_BUS_MMC2		24
+#define CLK_BUS_DRAM		25
+#define CLK_BUS_EMAC		26
+#define CLK_BUS_HSTIMER		27
+#define CLK_BUS_SPI0		28
+#define CLK_BUS_OTG		29
+#define CLK_BUS_EHCI0		30
+#define CLK_BUS_OHCI0		31
+#define CLK_BUS_VE		32
+#define CLK_BUS_TCON0		33
+#define CLK_BUS_CSI		34
+#define CLK_BUS_DE		35
+#define CLK_BUS_CODEC		36
+#define CLK_BUS_PIO		37
+#define CLK_BUS_I2C0		38
+#define CLK_BUS_I2C1		39
+#define CLK_BUS_UART0		40
+#define CLK_BUS_UART1		41
+#define CLK_BUS_UART2		42
+#define CLK_BUS_EPHY		43
+#define CLK_BUS_DBG		44
+
+#define CLK_MMC0		45
+#define CLK_MMC0_SAMPLE		46
+#define CLK_MMC0_OUTPUT		47
+#define CLK_MMC1		48
+#define CLK_MMC1_SAMPLE		49
+#define CLK_MMC1_OUTPUT		50
+#define CLK_MMC2		51
+#define CLK_MMC2_SAMPLE		52
+#define CLK_MMC2_OUTPUT		53
+#define CLK_CE			54
+#define CLK_SPI0		55
+#define CLK_USB_PHY0		56
+#define CLK_USB_OHCI0		57
+
+#define CLK_DRAM_VE		59
+#define CLK_DRAM_CSI		60
+#define CLK_DRAM_EHCI		61
+#define CLK_DRAM_OHCI		62
+#define CLK_DE			63
+#define CLK_TCON0		64
+#define CLK_CSI_MISC		65
+#define CLK_CSI0_MCLK		66
+#define CLK_CSI1_SCLK		67
+#define CLK_CSI1_MCLK		68
+#define CLK_VE			69
+#define CLK_AC_DIG		70
+#define CLK_AVS			71
+
+#define CLK_MIPI_CSI		73
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
diff --git a/include/dt-bindings/clock/sun9i-a80-ccu.h b/include/dt-bindings/clock/sun9i-a80-ccu.h
new file mode 100644
index 0000000..6ea1492
--- /dev/null
+++ b/include/dt-bindings/clock/sun9i-a80-ccu.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
+#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
+
+#define CLK_PLL_AUDIO		2
+#define CLK_PLL_PERIPH0		3
+
+#define CLK_C0CPUX		12
+#define CLK_C1CPUX		13
+
+#define CLK_OUT_A		27
+#define CLK_OUT_B		28
+
+#define CLK_NAND0_0		29
+#define CLK_NAND0_1		30
+#define CLK_NAND1_0		31
+#define CLK_NAND1_1		32
+#define CLK_MMC0		33
+#define CLK_MMC0_SAMPLE		34
+#define CLK_MMC0_OUTPUT		35
+#define CLK_MMC1		36
+#define CLK_MMC1_SAMPLE		37
+#define CLK_MMC1_OUTPUT		38
+#define CLK_MMC2		39
+#define CLK_MMC2_SAMPLE		40
+#define CLK_MMC2_OUTPUT		41
+#define CLK_MMC3		42
+#define CLK_MMC3_SAMPLE		43
+#define CLK_MMC3_OUTPUT		44
+#define CLK_TS			45
+#define CLK_SS			46
+#define CLK_SPI0		47
+#define CLK_SPI1		48
+#define CLK_SPI2		49
+#define CLK_SPI3		50
+#define CLK_I2S0		51
+#define CLK_I2S1		52
+#define CLK_SPDIF		53
+#define CLK_SDRAM		54
+#define CLK_DE			55
+#define CLK_EDP			56
+#define CLK_MP			57
+#define CLK_LCD0		58
+#define CLK_LCD1		59
+#define CLK_MIPI_DSI0		60
+#define CLK_MIPI_DSI1		61
+#define CLK_HDMI		62
+#define CLK_HDMI_SLOW		63
+#define CLK_MIPI_CSI		64
+#define CLK_CSI_ISP		65
+#define CLK_CSI_MISC		66
+#define CLK_CSI0_MCLK		67
+#define CLK_CSI1_MCLK		68
+#define CLK_FD			69
+#define CLK_VE			70
+#define CLK_AVS			71
+#define CLK_GPU_CORE		72
+#define CLK_GPU_MEMORY		73
+#define CLK_GPU_AXI		74
+#define CLK_SATA		75
+#define CLK_AC97		76
+#define CLK_MIPI_HSI		77
+#define CLK_GPADC		78
+#define CLK_CIR_TX		79
+
+#define CLK_BUS_FD		80
+#define CLK_BUS_VE		81
+#define CLK_BUS_GPU_CTRL	82
+#define CLK_BUS_SS		83
+#define CLK_BUS_MMC		84
+#define CLK_BUS_NAND0		85
+#define CLK_BUS_NAND1		86
+#define CLK_BUS_SDRAM		87
+#define CLK_BUS_MIPI_HSI	88
+#define CLK_BUS_SATA		89
+#define CLK_BUS_TS		90
+#define CLK_BUS_SPI0		91
+#define CLK_BUS_SPI1		92
+#define CLK_BUS_SPI2		93
+#define CLK_BUS_SPI3		94
+
+#define CLK_BUS_OTG		95
+#define CLK_BUS_USB		96
+#define CLK_BUS_GMAC		97
+#define CLK_BUS_MSGBOX		98
+#define CLK_BUS_SPINLOCK	99
+#define CLK_BUS_HSTIMER		100
+#define CLK_BUS_DMA		101
+
+#define CLK_BUS_LCD0		102
+#define CLK_BUS_LCD1		103
+#define CLK_BUS_EDP		104
+#define CLK_BUS_CSI		105
+#define CLK_BUS_HDMI		106
+#define CLK_BUS_DE		107
+#define CLK_BUS_MP		108
+#define CLK_BUS_MIPI_DSI	109
+
+#define CLK_BUS_SPDIF		110
+#define CLK_BUS_PIO		111
+#define CLK_BUS_AC97		112
+#define CLK_BUS_I2S0		113
+#define CLK_BUS_I2S1		114
+#define CLK_BUS_LRADC		115
+#define CLK_BUS_GPADC		116
+#define CLK_BUS_TWD		117
+#define CLK_BUS_CIR_TX		118
+
+#define CLK_BUS_I2C0		119
+#define CLK_BUS_I2C1		120
+#define CLK_BUS_I2C2		121
+#define CLK_BUS_I2C3		122
+#define CLK_BUS_I2C4		123
+#define CLK_BUS_UART0		124
+#define CLK_BUS_UART1		125
+#define CLK_BUS_UART2		126
+#define CLK_BUS_UART3		127
+#define CLK_BUS_UART4		128
+#define CLK_BUS_UART5		129
+
+#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun9i-a80-de.h b/include/dt-bindings/clock/sun9i-a80-de.h
new file mode 100644
index 0000000..3dad6c3
--- /dev/null
+++ b/include/dt-bindings/clock/sun9i-a80-de.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
+#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
+
+#define CLK_FE0			0
+#define CLK_FE1			1
+#define CLK_FE2			2
+#define CLK_IEP_DEU0		3
+#define CLK_IEP_DEU1		4
+#define CLK_BE0			5
+#define CLK_BE1			6
+#define CLK_BE2			7
+#define CLK_IEP_DRC0		8
+#define CLK_IEP_DRC1		9
+#define CLK_MERGE		10
+
+#define CLK_DRAM_FE0		11
+#define CLK_DRAM_FE1		12
+#define CLK_DRAM_FE2		13
+#define CLK_DRAM_DEU0		14
+#define CLK_DRAM_DEU1		15
+#define CLK_DRAM_BE0		16
+#define CLK_DRAM_BE1		17
+#define CLK_DRAM_BE2		18
+#define CLK_DRAM_DRC0		19
+#define CLK_DRAM_DRC1		20
+
+#define CLK_BUS_FE0		21
+#define CLK_BUS_FE1		22
+#define CLK_BUS_FE2		23
+#define CLK_BUS_DEU0		24
+#define CLK_BUS_DEU1		25
+#define CLK_BUS_BE0		26
+#define CLK_BUS_BE1		27
+#define CLK_BUS_BE2		28
+#define CLK_BUS_DRC0		29
+#define CLK_BUS_DRC1		30
+
+#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */
diff --git a/include/dt-bindings/clock/sun9i-a80-usb.h b/include/dt-bindings/clock/sun9i-a80-usb.h
new file mode 100644
index 0000000..783a60d
--- /dev/null
+++ b/include/dt-bindings/clock/sun9i-a80-usb.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_
+#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_
+
+#define CLK_BUS_HCI0	0
+#define CLK_USB_OHCI0	1
+#define CLK_BUS_HCI1	2
+#define CLK_BUS_HCI2	3
+#define CLK_USB_OHCI2	4
+
+#define CLK_USB0_PHY	5
+#define CLK_USB1_HSIC	6
+#define CLK_USB1_PHY	7
+#define CLK_USB2_HSIC	8
+#define CLK_USB2_PHY	9
+#define CLK_USB_HSIC	10
+
+#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
new file mode 100644
index 0000000..534c03f
--- /dev/null
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -0,0 +1,343 @@
+/*
+ * This header provides constants for binding nvidia,tegra114-car.
+ *
+ * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 160 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+/* 3 */
+#define TEGRA114_CLK_RTC 4
+#define TEGRA114_CLK_TIMER 5
+#define TEGRA114_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA114_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA114_CLK_I2S1 11
+#define TEGRA114_CLK_I2C1 12
+#define TEGRA114_CLK_NDFLASH 13
+#define TEGRA114_CLK_SDMMC1 14
+#define TEGRA114_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA114_CLK_PWM 17
+#define TEGRA114_CLK_I2S2 18
+#define TEGRA114_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA114_CLK_GR2D 21
+#define TEGRA114_CLK_USBD 22
+#define TEGRA114_CLK_ISP 23
+#define TEGRA114_CLK_GR3D 24
+/* 25 */
+#define TEGRA114_CLK_DISP2 26
+#define TEGRA114_CLK_DISP1 27
+#define TEGRA114_CLK_HOST1X 28
+#define TEGRA114_CLK_VCP 29
+#define TEGRA114_CLK_I2S0 30
+/* 31 */
+
+#define TEGRA114_CLK_MC 32
+/* 33 */
+#define TEGRA114_CLK_APBDMA 34
+/* 35 */
+#define TEGRA114_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA114_CLK_KFUSE 40
+#define TEGRA114_CLK_SBC1 41
+#define TEGRA114_CLK_NOR 42
+/* 43 */
+#define TEGRA114_CLK_SBC2 44
+/* 45 */
+#define TEGRA114_CLK_SBC3 46
+#define TEGRA114_CLK_I2C5 47
+#define TEGRA114_CLK_DSIA 48
+/* 49 */
+#define TEGRA114_CLK_MIPI 50
+#define TEGRA114_CLK_HDMI 51
+#define TEGRA114_CLK_CSI 52
+/* 53 */
+#define TEGRA114_CLK_I2C2 54
+#define TEGRA114_CLK_UARTC 55
+#define TEGRA114_CLK_MIPI_CAL 56
+#define TEGRA114_CLK_EMC 57
+#define TEGRA114_CLK_USB2 58
+#define TEGRA114_CLK_USB3 59
+/* 60 */
+#define TEGRA114_CLK_VDE 61
+#define TEGRA114_CLK_BSEA 62
+#define TEGRA114_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA114_CLK_UARTD 65
+/* 66 */
+#define TEGRA114_CLK_I2C3 67
+#define TEGRA114_CLK_SBC4 68
+#define TEGRA114_CLK_SDMMC3 69
+/* 70 */
+#define TEGRA114_CLK_OWR 71
+/* 72 */
+#define TEGRA114_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA114_CLK_LA 76
+#define TEGRA114_CLK_TRACE 77
+#define TEGRA114_CLK_SOC_THERM 78
+#define TEGRA114_CLK_DTV 79
+#define TEGRA114_CLK_NDSPEED 80
+#define TEGRA114_CLK_I2CSLOW 81
+#define TEGRA114_CLK_DSIB 82
+#define TEGRA114_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA114_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA114_CLK_MSENC 91
+#define TEGRA114_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA114_CLK_MSELECT 99
+#define TEGRA114_CLK_TSENSOR 100
+#define TEGRA114_CLK_I2S3 101
+#define TEGRA114_CLK_I2S4 102
+#define TEGRA114_CLK_I2C4 103
+#define TEGRA114_CLK_SBC5 104
+#define TEGRA114_CLK_SBC6 105
+#define TEGRA114_CLK_D_AUDIO 106
+#define TEGRA114_CLK_APBIF 107
+#define TEGRA114_CLK_DAM0 108
+#define TEGRA114_CLK_DAM1 109
+#define TEGRA114_CLK_DAM2 110
+#define TEGRA114_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA114_CLK_AUDIO0_2X 113
+#define TEGRA114_CLK_AUDIO1_2X 114
+#define TEGRA114_CLK_AUDIO2_2X 115
+#define TEGRA114_CLK_AUDIO3_2X 116
+#define TEGRA114_CLK_AUDIO4_2X 117
+#define TEGRA114_CLK_SPDIF_2X 118
+#define TEGRA114_CLK_ACTMON 119
+#define TEGRA114_CLK_EXTERN1 120
+#define TEGRA114_CLK_EXTERN2 121
+#define TEGRA114_CLK_EXTERN3 122
+/* 123 */
+/* 124 */
+#define TEGRA114_CLK_HDA 125
+/* 126 */
+#define TEGRA114_CLK_SE 127
+
+#define TEGRA114_CLK_HDA2HDMI 128
+/* 129 */
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/*      xusb_host_src and xusb_ss_src) */
+#define TEGRA114_CLK_CILAB 144
+#define TEGRA114_CLK_CILCD 145
+#define TEGRA114_CLK_CILE 146
+#define TEGRA114_CLK_DSIALP 147
+#define TEGRA114_CLK_DSIBLP 148
+/* 149 */
+#define TEGRA114_CLK_DDS 150
+/* 151 */
+#define TEGRA114_CLK_DP2 152
+#define TEGRA114_CLK_AMX 153
+#define TEGRA114_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA114_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+/* 166 */
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+/* 171 */
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+/* 176 */
+/* 177 */
+/* 178 */
+/* 179 */
+/* 180 */
+/* 181 */
+/* 182 */
+/* 183 */
+/* 184 */
+/* 185 */
+/* 186 */
+/* 187 */
+/* 188 */
+/* 189 */
+/* 190 */
+/* 191 */
+
+#define TEGRA114_CLK_UARTB 192
+#define TEGRA114_CLK_VFIR 193
+#define TEGRA114_CLK_SPDIF_IN 194
+#define TEGRA114_CLK_SPDIF_OUT 195
+#define TEGRA114_CLK_VI 196
+#define TEGRA114_CLK_VI_SENSOR 197
+#define TEGRA114_CLK_FUSE 198
+#define TEGRA114_CLK_FUSE_BURN 199
+#define TEGRA114_CLK_CLK_32K 200
+#define TEGRA114_CLK_CLK_M 201
+#define TEGRA114_CLK_CLK_M_DIV2 202
+#define TEGRA114_CLK_CLK_M_DIV4 203
+#define TEGRA114_CLK_PLL_REF 204
+#define TEGRA114_CLK_PLL_C 205
+#define TEGRA114_CLK_PLL_C_OUT1 206
+#define TEGRA114_CLK_PLL_C2 207
+#define TEGRA114_CLK_PLL_C3 208
+#define TEGRA114_CLK_PLL_M 209
+#define TEGRA114_CLK_PLL_M_OUT1 210
+#define TEGRA114_CLK_PLL_P 211
+#define TEGRA114_CLK_PLL_P_OUT1 212
+#define TEGRA114_CLK_PLL_P_OUT2 213
+#define TEGRA114_CLK_PLL_P_OUT3 214
+#define TEGRA114_CLK_PLL_P_OUT4 215
+#define TEGRA114_CLK_PLL_A 216
+#define TEGRA114_CLK_PLL_A_OUT0 217
+#define TEGRA114_CLK_PLL_D 218
+#define TEGRA114_CLK_PLL_D_OUT0 219
+#define TEGRA114_CLK_PLL_D2 220
+#define TEGRA114_CLK_PLL_D2_OUT0 221
+#define TEGRA114_CLK_PLL_U 222
+#define TEGRA114_CLK_PLL_U_480M 223
+
+#define TEGRA114_CLK_PLL_U_60M 224
+#define TEGRA114_CLK_PLL_U_48M 225
+#define TEGRA114_CLK_PLL_U_12M 226
+#define TEGRA114_CLK_PLL_X 227
+#define TEGRA114_CLK_PLL_X_OUT0 228
+#define TEGRA114_CLK_PLL_RE_VCO 229
+#define TEGRA114_CLK_PLL_RE_OUT 230
+#define TEGRA114_CLK_PLL_E_OUT0 231
+#define TEGRA114_CLK_SPDIF_IN_SYNC 232
+#define TEGRA114_CLK_I2S0_SYNC 233
+#define TEGRA114_CLK_I2S1_SYNC 234
+#define TEGRA114_CLK_I2S2_SYNC 235
+#define TEGRA114_CLK_I2S3_SYNC 236
+#define TEGRA114_CLK_I2S4_SYNC 237
+#define TEGRA114_CLK_VIMCLK_SYNC 238
+#define TEGRA114_CLK_AUDIO0 239
+#define TEGRA114_CLK_AUDIO1 240
+#define TEGRA114_CLK_AUDIO2 241
+#define TEGRA114_CLK_AUDIO3 242
+#define TEGRA114_CLK_AUDIO4 243
+#define TEGRA114_CLK_SPDIF 244
+#define TEGRA114_CLK_CLK_OUT_1 245
+#define TEGRA114_CLK_CLK_OUT_2 246
+#define TEGRA114_CLK_CLK_OUT_3 247
+#define TEGRA114_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA114_CLK_XUSB_HOST_SRC 252
+#define TEGRA114_CLK_XUSB_FALCON_SRC 253
+#define TEGRA114_CLK_XUSB_FS_SRC 254
+#define TEGRA114_CLK_XUSB_SS_SRC 255
+
+#define TEGRA114_CLK_XUSB_DEV_SRC 256
+#define TEGRA114_CLK_XUSB_DEV 257
+#define TEGRA114_CLK_XUSB_HS_SRC 258
+#define TEGRA114_CLK_SCLK 259
+#define TEGRA114_CLK_HCLK 260
+#define TEGRA114_CLK_PCLK 261
+#define TEGRA114_CLK_CCLK_G 262
+#define TEGRA114_CLK_CCLK_LP 263
+#define TEGRA114_CLK_DFLL_REF 264
+#define TEGRA114_CLK_DFLL_SOC 265
+/* 266 */
+/* 267 */
+/* 268 */
+/* 269 */
+/* 270 */
+/* 271 */
+/* 272 */
+/* 273 */
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA114_CLK_AUDIO0_MUX 300
+#define TEGRA114_CLK_AUDIO1_MUX 301
+#define TEGRA114_CLK_AUDIO2_MUX 302
+#define TEGRA114_CLK_AUDIO3_MUX 303
+#define TEGRA114_CLK_AUDIO4_MUX 304
+#define TEGRA114_CLK_SPDIF_MUX 305
+#define TEGRA114_CLK_CLK_OUT_1_MUX 306
+#define TEGRA114_CLK_CLK_OUT_2_MUX 307
+#define TEGRA114_CLK_CLK_OUT_3_MUX 308
+#define TEGRA114_CLK_DSIA_MUX 309
+#define TEGRA114_CLK_DSIB_MUX 310
+#define TEGRA114_CLK_XUSB_SS_DIV2 311
+#define TEGRA114_CLK_CLK_MAX 312
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
new file mode 100644
index 0000000..a215609
--- /dev/null
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -0,0 +1,345 @@
+/*
+ * This header provides constants for binding nvidia,tegra124-car or
+ * nvidia,tegra132-car.
+ *
+ * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 185 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
+#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+#define TEGRA124_CLK_ISPB 3
+#define TEGRA124_CLK_RTC 4
+#define TEGRA124_CLK_TIMER 5
+#define TEGRA124_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA124_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA124_CLK_I2S1 11
+#define TEGRA124_CLK_I2C1 12
+/* 13 */
+#define TEGRA124_CLK_SDMMC1 14
+#define TEGRA124_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA124_CLK_PWM 17
+#define TEGRA124_CLK_I2S2 18
+/* 20 (register bit affects vi and vi_sensor) */
+/* 21 */
+#define TEGRA124_CLK_USBD 22
+#define TEGRA124_CLK_ISP 23
+/* 26 */
+/* 25 */
+#define TEGRA124_CLK_DISP2 26
+#define TEGRA124_CLK_DISP1 27
+#define TEGRA124_CLK_HOST1X 28
+#define TEGRA124_CLK_VCP 29
+#define TEGRA124_CLK_I2S0 30
+/* 31 */
+
+#define TEGRA124_CLK_MC 32
+/* 33 */
+#define TEGRA124_CLK_APBDMA 34
+/* 35 */
+#define TEGRA124_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA124_CLK_KFUSE 40
+#define TEGRA124_CLK_SBC1 41
+#define TEGRA124_CLK_NOR 42
+/* 43 */
+#define TEGRA124_CLK_SBC2 44
+/* 45 */
+#define TEGRA124_CLK_SBC3 46
+#define TEGRA124_CLK_I2C5 47
+#define TEGRA124_CLK_DSIA 48
+/* 49 */
+#define TEGRA124_CLK_MIPI 50
+#define TEGRA124_CLK_HDMI 51
+#define TEGRA124_CLK_CSI 52
+/* 53 */
+#define TEGRA124_CLK_I2C2 54
+#define TEGRA124_CLK_UARTC 55
+#define TEGRA124_CLK_MIPI_CAL 56
+#define TEGRA124_CLK_EMC 57
+#define TEGRA124_CLK_USB2 58
+#define TEGRA124_CLK_USB3 59
+/* 60 */
+#define TEGRA124_CLK_VDE 61
+#define TEGRA124_CLK_BSEA 62
+#define TEGRA124_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA124_CLK_UARTD 65
+/* 66 */
+#define TEGRA124_CLK_I2C3 67
+#define TEGRA124_CLK_SBC4 68
+#define TEGRA124_CLK_SDMMC3 69
+#define TEGRA124_CLK_PCIE 70
+#define TEGRA124_CLK_OWR 71
+#define TEGRA124_CLK_AFI 72
+#define TEGRA124_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA124_CLK_LA 76
+#define TEGRA124_CLK_TRACE 77
+#define TEGRA124_CLK_SOC_THERM 78
+#define TEGRA124_CLK_DTV 79
+/* 80 */
+#define TEGRA124_CLK_I2CSLOW 81
+#define TEGRA124_CLK_DSIB 82
+#define TEGRA124_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA124_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA124_CLK_MSENC 91
+#define TEGRA124_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA124_CLK_MSELECT 99
+#define TEGRA124_CLK_TSENSOR 100
+#define TEGRA124_CLK_I2S3 101
+#define TEGRA124_CLK_I2S4 102
+#define TEGRA124_CLK_I2C4 103
+#define TEGRA124_CLK_SBC5 104
+#define TEGRA124_CLK_SBC6 105
+#define TEGRA124_CLK_D_AUDIO 106
+#define TEGRA124_CLK_APBIF 107
+#define TEGRA124_CLK_DAM0 108
+#define TEGRA124_CLK_DAM1 109
+#define TEGRA124_CLK_DAM2 110
+#define TEGRA124_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA124_CLK_AUDIO0_2X 113
+#define TEGRA124_CLK_AUDIO1_2X 114
+#define TEGRA124_CLK_AUDIO2_2X 115
+#define TEGRA124_CLK_AUDIO3_2X 116
+#define TEGRA124_CLK_AUDIO4_2X 117
+#define TEGRA124_CLK_SPDIF_2X 118
+#define TEGRA124_CLK_ACTMON 119
+#define TEGRA124_CLK_EXTERN1 120
+#define TEGRA124_CLK_EXTERN2 121
+#define TEGRA124_CLK_EXTERN3 122
+#define TEGRA124_CLK_SATA_OOB 123
+#define TEGRA124_CLK_SATA 124
+#define TEGRA124_CLK_HDA 125
+/* 126 */
+#define TEGRA124_CLK_SE 127
+
+#define TEGRA124_CLK_HDA2HDMI 128
+#define TEGRA124_CLK_SATA_COLD 129
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/*      xusb_host_src and xusb_ss_src) */
+#define TEGRA124_CLK_CILAB 144
+#define TEGRA124_CLK_CILCD 145
+#define TEGRA124_CLK_CILE 146
+#define TEGRA124_CLK_DSIALP 147
+#define TEGRA124_CLK_DSIBLP 148
+#define TEGRA124_CLK_ENTROPY 149
+#define TEGRA124_CLK_DDS 150
+/* 151 */
+#define TEGRA124_CLK_DP2 152
+#define TEGRA124_CLK_AMX 153
+#define TEGRA124_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA124_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+#define TEGRA124_CLK_I2C6 166
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+#define TEGRA124_CLK_VIM2_CLK 171
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+#define TEGRA124_CLK_HDMI_AUDIO 176
+#define TEGRA124_CLK_CLK72MHZ 177
+#define TEGRA124_CLK_VIC03 178
+/* 179 */
+#define TEGRA124_CLK_ADX1 180
+#define TEGRA124_CLK_DPAUX 181
+#define TEGRA124_CLK_SOR0 182
+/* 183 */
+#define TEGRA124_CLK_GPU 184
+#define TEGRA124_CLK_AMX1 185
+/* 186 */
+/* 187 */
+/* 188 */
+/* 189 */
+/* 190 */
+/* 191 */
+#define TEGRA124_CLK_UARTB 192
+#define TEGRA124_CLK_VFIR 193
+#define TEGRA124_CLK_SPDIF_IN 194
+#define TEGRA124_CLK_SPDIF_OUT 195
+#define TEGRA124_CLK_VI 196
+#define TEGRA124_CLK_VI_SENSOR 197
+#define TEGRA124_CLK_FUSE 198
+#define TEGRA124_CLK_FUSE_BURN 199
+#define TEGRA124_CLK_CLK_32K 200
+#define TEGRA124_CLK_CLK_M 201
+#define TEGRA124_CLK_CLK_M_DIV2 202
+#define TEGRA124_CLK_CLK_M_DIV4 203
+#define TEGRA124_CLK_PLL_REF 204
+#define TEGRA124_CLK_PLL_C 205
+#define TEGRA124_CLK_PLL_C_OUT1 206
+#define TEGRA124_CLK_PLL_C2 207
+#define TEGRA124_CLK_PLL_C3 208
+#define TEGRA124_CLK_PLL_M 209
+#define TEGRA124_CLK_PLL_M_OUT1 210
+#define TEGRA124_CLK_PLL_P 211
+#define TEGRA124_CLK_PLL_P_OUT1 212
+#define TEGRA124_CLK_PLL_P_OUT2 213
+#define TEGRA124_CLK_PLL_P_OUT3 214
+#define TEGRA124_CLK_PLL_P_OUT4 215
+#define TEGRA124_CLK_PLL_A 216
+#define TEGRA124_CLK_PLL_A_OUT0 217
+#define TEGRA124_CLK_PLL_D 218
+#define TEGRA124_CLK_PLL_D_OUT0 219
+#define TEGRA124_CLK_PLL_D2 220
+#define TEGRA124_CLK_PLL_D2_OUT0 221
+#define TEGRA124_CLK_PLL_U 222
+#define TEGRA124_CLK_PLL_U_480M 223
+
+#define TEGRA124_CLK_PLL_U_60M 224
+#define TEGRA124_CLK_PLL_U_48M 225
+#define TEGRA124_CLK_PLL_U_12M 226
+/* 227 */
+/* 228 */
+#define TEGRA124_CLK_PLL_RE_VCO 229
+#define TEGRA124_CLK_PLL_RE_OUT 230
+#define TEGRA124_CLK_PLL_E 231
+#define TEGRA124_CLK_SPDIF_IN_SYNC 232
+#define TEGRA124_CLK_I2S0_SYNC 233
+#define TEGRA124_CLK_I2S1_SYNC 234
+#define TEGRA124_CLK_I2S2_SYNC 235
+#define TEGRA124_CLK_I2S3_SYNC 236
+#define TEGRA124_CLK_I2S4_SYNC 237
+#define TEGRA124_CLK_VIMCLK_SYNC 238
+#define TEGRA124_CLK_AUDIO0 239
+#define TEGRA124_CLK_AUDIO1 240
+#define TEGRA124_CLK_AUDIO2 241
+#define TEGRA124_CLK_AUDIO3 242
+#define TEGRA124_CLK_AUDIO4 243
+#define TEGRA124_CLK_SPDIF 244
+#define TEGRA124_CLK_CLK_OUT_1 245
+#define TEGRA124_CLK_CLK_OUT_2 246
+#define TEGRA124_CLK_CLK_OUT_3 247
+#define TEGRA124_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA124_CLK_XUSB_HOST_SRC 252
+#define TEGRA124_CLK_XUSB_FALCON_SRC 253
+#define TEGRA124_CLK_XUSB_FS_SRC 254
+#define TEGRA124_CLK_XUSB_SS_SRC 255
+
+#define TEGRA124_CLK_XUSB_DEV_SRC 256
+#define TEGRA124_CLK_XUSB_DEV 257
+#define TEGRA124_CLK_XUSB_HS_SRC 258
+#define TEGRA124_CLK_SCLK 259
+#define TEGRA124_CLK_HCLK 260
+#define TEGRA124_CLK_PCLK 261
+/* 262 */
+/* 263 */
+#define TEGRA124_CLK_DFLL_REF 264
+#define TEGRA124_CLK_DFLL_SOC 265
+#define TEGRA124_CLK_VI_SENSOR2 266
+#define TEGRA124_CLK_PLL_P_OUT5 267
+#define TEGRA124_CLK_CML0 268
+#define TEGRA124_CLK_CML1 269
+#define TEGRA124_CLK_PLL_C4 270
+#define TEGRA124_CLK_PLL_DP 271
+#define TEGRA124_CLK_PLL_E_MUX 272
+#define TEGRA124_CLK_PLL_D_DSI_OUT 273
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA124_CLK_AUDIO0_MUX 300
+#define TEGRA124_CLK_AUDIO1_MUX 301
+#define TEGRA124_CLK_AUDIO2_MUX 302
+#define TEGRA124_CLK_AUDIO3_MUX 303
+#define TEGRA124_CLK_AUDIO4_MUX 304
+#define TEGRA124_CLK_SPDIF_MUX 305
+#define TEGRA124_CLK_CLK_OUT_1_MUX 306
+#define TEGRA124_CLK_CLK_OUT_2_MUX 307
+#define TEGRA124_CLK_CLK_OUT_3_MUX 308
+/* 309 */
+/* 310 */
+#define TEGRA124_CLK_SOR0_LVDS 311
+#define TEGRA124_CLK_XUSB_SS_DIV2 312
+
+#define TEGRA124_CLK_PLL_M_UD 313
+#define TEGRA124_CLK_PLL_C_UD 314
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
new file mode 100644
index 0000000..2860737
--- /dev/null
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -0,0 +1,19 @@
+/*
+ * This header provides Tegra124-specific constants for binding
+ * nvidia,tegra124-car.
+ */
+
+#include <dt-bindings/clock/tegra124-car-common.h>
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
+
+#define TEGRA124_CLK_PLL_X		227
+#define TEGRA124_CLK_PLL_X_OUT0		228
+
+#define TEGRA124_CLK_CCLK_G		262
+#define TEGRA124_CLK_CCLK_LP		263
+
+#define TEGRA124_CLK_CLK_MAX		315
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/clock/tegra186-clock.h b/include/dt-bindings/clock/tegra186-clock.h
new file mode 100644
index 0000000..f73d320
--- /dev/null
+++ b/include/dt-bindings/clock/tegra186-clock.h
@@ -0,0 +1,940 @@
+/** @file */
+
+#ifndef _MACH_T186_CLK_T186_H
+#define _MACH_T186_CLK_T186_H
+
+/**
+ * @defgroup clock_ids Clock Identifiers
+ * @{
+ *   @defgroup extern_input external input clocks
+ *   @{
+ *     @def TEGRA186_CLK_OSC
+ *     @def TEGRA186_CLK_CLK_32K
+ *     @def TEGRA186_CLK_DTV_INPUT
+ *     @def TEGRA186_CLK_SOR0_PAD_CLKOUT
+ *     @def TEGRA186_CLK_SOR1_PAD_CLKOUT
+ *     @def TEGRA186_CLK_I2S1_SYNC_INPUT
+ *     @def TEGRA186_CLK_I2S2_SYNC_INPUT
+ *     @def TEGRA186_CLK_I2S3_SYNC_INPUT
+ *     @def TEGRA186_CLK_I2S4_SYNC_INPUT
+ *     @def TEGRA186_CLK_I2S5_SYNC_INPUT
+ *     @def TEGRA186_CLK_I2S6_SYNC_INPUT
+ *     @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
+ *   @}
+ *
+ *   @defgroup extern_output external output clocks
+ *   @{
+ *     @def TEGRA186_CLK_EXTPERIPH1
+ *     @def TEGRA186_CLK_EXTPERIPH2
+ *     @def TEGRA186_CLK_EXTPERIPH3
+ *     @def TEGRA186_CLK_EXTPERIPH4
+ *   @}
+ *
+ *   @defgroup display_clks display related clocks
+ *   @{
+ *     @def TEGRA186_CLK_CEC
+ *     @def TEGRA186_CLK_DSIC
+ *     @def TEGRA186_CLK_DSIC_LP
+ *     @def TEGRA186_CLK_DSID
+ *     @def TEGRA186_CLK_DSID_LP
+ *     @def TEGRA186_CLK_DPAUX1
+ *     @def TEGRA186_CLK_DPAUX
+ *     @def TEGRA186_CLK_HDA2HDMICODEC
+ *     @def TEGRA186_CLK_NVDISPLAY_DISP
+ *     @def TEGRA186_CLK_NVDISPLAY_DSC
+ *     @def TEGRA186_CLK_NVDISPLAY_P0
+ *     @def TEGRA186_CLK_NVDISPLAY_P1
+ *     @def TEGRA186_CLK_NVDISPLAY_P2
+ *     @def TEGRA186_CLK_NVDISPLAYHUB
+ *     @def TEGRA186_CLK_SOR_SAFE
+ *     @def TEGRA186_CLK_SOR0
+ *     @def TEGRA186_CLK_SOR0_OUT
+ *     @def TEGRA186_CLK_SOR1
+ *     @def TEGRA186_CLK_SOR1_OUT
+ *     @def TEGRA186_CLK_DSI
+ *     @def TEGRA186_CLK_MIPI_CAL
+ *     @def TEGRA186_CLK_DSIA_LP
+ *     @def TEGRA186_CLK_DSIB
+ *     @def TEGRA186_CLK_DSIB_LP
+ *   @}
+ *
+ *   @defgroup camera_clks camera related clocks
+ *   @{
+ *     @def TEGRA186_CLK_NVCSI
+ *     @def TEGRA186_CLK_NVCSILP
+ *     @def TEGRA186_CLK_VI
+ *   @}
+ *
+ *   @defgroup audio_clks audio related clocks
+ *   @{
+ *     @def TEGRA186_CLK_ACLK
+ *     @def TEGRA186_CLK_ADSP
+ *     @def TEGRA186_CLK_ADSPNEON
+ *     @def TEGRA186_CLK_AHUB
+ *     @def TEGRA186_CLK_APE
+ *     @def TEGRA186_CLK_APB2APE
+ *     @def TEGRA186_CLK_AUD_MCLK
+ *     @def TEGRA186_CLK_DMIC1
+ *     @def TEGRA186_CLK_DMIC2
+ *     @def TEGRA186_CLK_DMIC3
+ *     @def TEGRA186_CLK_DMIC4
+ *     @def TEGRA186_CLK_DSPK1
+ *     @def TEGRA186_CLK_DSPK2
+ *     @def TEGRA186_CLK_HDA
+ *     @def TEGRA186_CLK_HDA2CODEC_2X
+ *     @def TEGRA186_CLK_I2S1
+ *     @def TEGRA186_CLK_I2S2
+ *     @def TEGRA186_CLK_I2S3
+ *     @def TEGRA186_CLK_I2S4
+ *     @def TEGRA186_CLK_I2S5
+ *     @def TEGRA186_CLK_I2S6
+ *     @def TEGRA186_CLK_MAUD
+ *     @def TEGRA186_CLK_PLL_A_OUT0
+ *     @def TEGRA186_CLK_SPDIF_DOUBLER
+ *     @def TEGRA186_CLK_SPDIF_IN
+ *     @def TEGRA186_CLK_SPDIF_OUT
+ *     @def TEGRA186_CLK_SYNC_DMIC1
+ *     @def TEGRA186_CLK_SYNC_DMIC2
+ *     @def TEGRA186_CLK_SYNC_DMIC3
+ *     @def TEGRA186_CLK_SYNC_DMIC4
+ *     @def TEGRA186_CLK_SYNC_DMIC5
+ *     @def TEGRA186_CLK_SYNC_DSPK1
+ *     @def TEGRA186_CLK_SYNC_DSPK2
+ *     @def TEGRA186_CLK_SYNC_I2S1
+ *     @def TEGRA186_CLK_SYNC_I2S2
+ *     @def TEGRA186_CLK_SYNC_I2S3
+ *     @def TEGRA186_CLK_SYNC_I2S4
+ *     @def TEGRA186_CLK_SYNC_I2S5
+ *     @def TEGRA186_CLK_SYNC_I2S6
+ *     @def TEGRA186_CLK_SYNC_SPDIF
+ *   @}
+ *
+ *   @defgroup uart_clks UART clocks
+ *   @{
+ *     @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
+ *     @def TEGRA186_CLK_UARTA
+ *     @def TEGRA186_CLK_UARTB
+ *     @def TEGRA186_CLK_UARTC
+ *     @def TEGRA186_CLK_UARTD
+ *     @def TEGRA186_CLK_UARTE
+ *     @def TEGRA186_CLK_UARTF
+ *     @def TEGRA186_CLK_UARTG
+ *     @def TEGRA186_CLK_UART_FST_MIPI_CAL
+ *   @}
+ *
+ *   @defgroup i2c_clks I2C clocks
+ *   @{
+ *     @def TEGRA186_CLK_AON_I2C_SLOW
+ *     @def TEGRA186_CLK_I2C1
+ *     @def TEGRA186_CLK_I2C2
+ *     @def TEGRA186_CLK_I2C3
+ *     @def TEGRA186_CLK_I2C4
+ *     @def TEGRA186_CLK_I2C5
+ *     @def TEGRA186_CLK_I2C6
+ *     @def TEGRA186_CLK_I2C8
+ *     @def TEGRA186_CLK_I2C9
+ *     @def TEGRA186_CLK_I2C1
+ *     @def TEGRA186_CLK_I2C12
+ *     @def TEGRA186_CLK_I2C13
+ *     @def TEGRA186_CLK_I2C14
+ *     @def TEGRA186_CLK_I2C_SLOW
+ *     @def TEGRA186_CLK_VI_I2C
+ *   @}
+ *
+ *   @defgroup spi_clks SPI clocks
+ *   @{
+ *     @def TEGRA186_CLK_SPI1
+ *     @def TEGRA186_CLK_SPI2
+ *     @def TEGRA186_CLK_SPI3
+ *     @def TEGRA186_CLK_SPI4
+ *   @}
+ *
+ *   @defgroup storage storage related clocks
+ *   @{
+ *     @def TEGRA186_CLK_SATA
+ *     @def TEGRA186_CLK_SATA_OOB
+ *     @def TEGRA186_CLK_SATA_IOBIST
+ *     @def TEGRA186_CLK_SDMMC_LEGACY_TM
+ *     @def TEGRA186_CLK_SDMMC1
+ *     @def TEGRA186_CLK_SDMMC2
+ *     @def TEGRA186_CLK_SDMMC3
+ *     @def TEGRA186_CLK_SDMMC4
+ *     @def TEGRA186_CLK_QSPI
+ *     @def TEGRA186_CLK_QSPI_OUT
+ *     @def TEGRA186_CLK_UFSDEV_REF
+ *     @def TEGRA186_CLK_UFSHC
+ *   @}
+ *
+ *   @defgroup pwm_clks PWM clocks
+ *   @{
+ *     @def TEGRA186_CLK_PWM1
+ *     @def TEGRA186_CLK_PWM2
+ *     @def TEGRA186_CLK_PWM3
+ *     @def TEGRA186_CLK_PWM4
+ *     @def TEGRA186_CLK_PWM5
+ *     @def TEGRA186_CLK_PWM6
+ *     @def TEGRA186_CLK_PWM7
+ *     @def TEGRA186_CLK_PWM8
+ *   @}
+ *
+ *   @defgroup plls PLLs and related clocks
+ *   @{
+ *     @def TEGRA186_CLK_PLLREFE_OUT_GATED
+ *     @def TEGRA186_CLK_PLLREFE_OUT1
+ *     @def TEGRA186_CLK_PLLD_OUT1
+ *     @def TEGRA186_CLK_PLLP_OUT0
+ *     @def TEGRA186_CLK_PLLP_OUT5
+ *     @def TEGRA186_CLK_PLLA
+ *     @def TEGRA186_CLK_PLLE_PWRSEQ
+ *     @def TEGRA186_CLK_PLLA_OUT1
+ *     @def TEGRA186_CLK_PLLREFE_REF
+ *     @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
+ *     @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
+ *     @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
+ *     @def TEGRA186_CLK_PLLREFE_PEX
+ *     @def TEGRA186_CLK_PLLREFE_IDDQ
+ *     @def TEGRA186_CLK_PLLC_OUT_AON
+ *     @def TEGRA186_CLK_PLLC_OUT_ISP
+ *     @def TEGRA186_CLK_PLLC_OUT_VE
+ *     @def TEGRA186_CLK_PLLC4_OUT
+ *     @def TEGRA186_CLK_PLLREFE_OUT
+ *     @def TEGRA186_CLK_PLLREFE_PLL_REF
+ *     @def TEGRA186_CLK_PLLE
+ *     @def TEGRA186_CLK_PLLC
+ *     @def TEGRA186_CLK_PLLP
+ *     @def TEGRA186_CLK_PLLD
+ *     @def TEGRA186_CLK_PLLD2
+ *     @def TEGRA186_CLK_PLLREFE_VCO
+ *     @def TEGRA186_CLK_PLLC2
+ *     @def TEGRA186_CLK_PLLC3
+ *     @def TEGRA186_CLK_PLLDP
+ *     @def TEGRA186_CLK_PLLC4_VCO
+ *     @def TEGRA186_CLK_PLLA1
+ *     @def TEGRA186_CLK_PLLNVCSI
+ *     @def TEGRA186_CLK_PLLDISPHUB
+ *     @def TEGRA186_CLK_PLLD3
+ *     @def TEGRA186_CLK_PLLBPMPCAM
+ *     @def TEGRA186_CLK_PLLAON
+ *     @def TEGRA186_CLK_PLLU
+ *     @def TEGRA186_CLK_PLLC4_VCO_DIV2
+ *     @def TEGRA186_CLK_PLL_REF
+ *     @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
+ *     @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
+ *     @def TEGRA186_CLK_PLL_U_48M
+ *     @def TEGRA186_CLK_PLL_U_480M
+ *     @def TEGRA186_CLK_PLLC4_OUT0
+ *     @def TEGRA186_CLK_PLLC4_OUT1
+ *     @def TEGRA186_CLK_PLLC4_OUT2
+ *     @def TEGRA186_CLK_PLLC4_OUT_MUX
+ *     @def TEGRA186_CLK_DFLLDISP_DIV
+ *     @def TEGRA186_CLK_PLLDISPHUB_DIV
+ *     @def TEGRA186_CLK_PLLP_DIV8
+ *   @}
+ *
+ *   @defgroup nafll_clks NAFLL clock sources
+ *   @{
+ *     @def TEGRA186_CLK_NAFLL_AXI_CBB
+ *     @def TEGRA186_CLK_NAFLL_BCPU
+ *     @def TEGRA186_CLK_NAFLL_BPMP
+ *     @def TEGRA186_CLK_NAFLL_DISP
+ *     @def TEGRA186_CLK_NAFLL_GPU
+ *     @def TEGRA186_CLK_NAFLL_ISP
+ *     @def TEGRA186_CLK_NAFLL_MCPU
+ *     @def TEGRA186_CLK_NAFLL_NVDEC
+ *     @def TEGRA186_CLK_NAFLL_NVENC
+ *     @def TEGRA186_CLK_NAFLL_NVJPG
+ *     @def TEGRA186_CLK_NAFLL_SCE
+ *     @def TEGRA186_CLK_NAFLL_SE
+ *     @def TEGRA186_CLK_NAFLL_TSEC
+ *     @def TEGRA186_CLK_NAFLL_TSECB
+ *     @def TEGRA186_CLK_NAFLL_VI
+ *     @def TEGRA186_CLK_NAFLL_VIC
+ *   @}
+ *
+ *   @defgroup mphy MPHY related clocks
+ *   @{
+ *     @def TEGRA186_CLK_MPHY_L0_RX_SYMB
+ *     @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
+ *     @def TEGRA186_CLK_MPHY_L0_TX_SYMB
+ *     @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
+ *     @def TEGRA186_CLK_MPHY_L0_RX_ANA
+ *     @def TEGRA186_CLK_MPHY_L1_RX_ANA
+ *     @def TEGRA186_CLK_MPHY_IOBIST
+ *     @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
+ *     @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
+ *   @}
+ *
+ *   @defgroup eavb EAVB related clocks
+ *   @{
+ *     @def TEGRA186_CLK_EQOS_AXI
+ *     @def TEGRA186_CLK_EQOS_PTP_REF
+ *     @def TEGRA186_CLK_EQOS_RX
+ *     @def TEGRA186_CLK_EQOS_RX_INPUT
+ *     @def TEGRA186_CLK_EQOS_TX
+ *   @}
+ *
+ *   @defgroup usb USB related clocks
+ *   @{
+ *     @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
+ *     @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
+ *     @def TEGRA186_CLK_HSIC_TRK
+ *     @def TEGRA186_CLK_USB2_TRK
+ *     @def TEGRA186_CLK_USB2_HSIC_TRK
+ *     @def TEGRA186_CLK_XUSB_CORE_SS
+ *     @def TEGRA186_CLK_XUSB_CORE_DEV
+ *     @def TEGRA186_CLK_XUSB_FALCON
+ *     @def TEGRA186_CLK_XUSB_FS
+ *     @def TEGRA186_CLK_XUSB
+ *     @def TEGRA186_CLK_XUSB_DEV
+ *     @def TEGRA186_CLK_XUSB_HOST
+ *     @def TEGRA186_CLK_XUSB_SS
+ *   @}
+ *
+ *   @defgroup bigblock compute block related clocks
+ *   @{
+ *     @def TEGRA186_CLK_GPCCLK
+ *     @def TEGRA186_CLK_GPC2CLK
+ *     @def TEGRA186_CLK_GPU
+ *     @def TEGRA186_CLK_HOST1X
+ *     @def TEGRA186_CLK_ISP
+ *     @def TEGRA186_CLK_NVDEC
+ *     @def TEGRA186_CLK_NVENC
+ *     @def TEGRA186_CLK_NVJPG
+ *     @def TEGRA186_CLK_SE
+ *     @def TEGRA186_CLK_TSEC
+ *     @def TEGRA186_CLK_TSECB
+ *     @def TEGRA186_CLK_VIC
+ *   @}
+ *
+ *   @defgroup can CAN bus related clocks
+ *   @{
+ *     @def TEGRA186_CLK_CAN1
+ *     @def TEGRA186_CLK_CAN1_HOST
+ *     @def TEGRA186_CLK_CAN2
+ *     @def TEGRA186_CLK_CAN2_HOST
+ *   @}
+ *
+ *   @defgroup system basic system clocks
+ *   @{
+ *     @def TEGRA186_CLK_ACTMON
+ *     @def TEGRA186_CLK_AON_APB
+ *     @def TEGRA186_CLK_AON_CPU_NIC
+ *     @def TEGRA186_CLK_AON_NIC
+ *     @def TEGRA186_CLK_AXI_CBB
+ *     @def TEGRA186_CLK_BPMP_APB
+ *     @def TEGRA186_CLK_BPMP_CPU_NIC
+ *     @def TEGRA186_CLK_BPMP_NIC_RATE
+ *     @def TEGRA186_CLK_CLK_M
+ *     @def TEGRA186_CLK_EMC
+ *     @def TEGRA186_CLK_MSS_ENCRYPT
+ *     @def TEGRA186_CLK_SCE_APB
+ *     @def TEGRA186_CLK_SCE_CPU_NIC
+ *     @def TEGRA186_CLK_SCE_NIC
+ *     @def TEGRA186_CLK_TSC
+ *   @}
+ *
+ *   @defgroup pcie_clks PCIe related clocks
+ *   @{
+ *     @def TEGRA186_CLK_AFI
+ *     @def TEGRA186_CLK_PCIE
+ *     @def TEGRA186_CLK_PCIE2_IOBIST
+ *     @def TEGRA186_CLK_PCIERX0
+ *     @def TEGRA186_CLK_PCIERX1
+ *     @def TEGRA186_CLK_PCIERX2
+ *     @def TEGRA186_CLK_PCIERX3
+ *     @def TEGRA186_CLK_PCIERX4
+ *   @}
+ */
+
+/** @brief output of gate CLK_ENB_FUSE */
+#define TEGRA186_CLK_FUSE 0
+/**
+ * @brief It's not what you think
+ * @details output of gate CLK_ENB_GPU. This output connects to the GPU
+ * pwrclk. @warning: This is almost certainly not the clock you think
+ * it is. If you're looking for the clock of the graphics engine, see
+ * TEGRA186_GPCCLK
+ */
+#define TEGRA186_CLK_GPU 1
+/** @brief output of gate CLK_ENB_PCIE */
+#define TEGRA186_CLK_PCIE 3
+/** @brief output of the divider IPFS_CLK_DIVISOR */
+#define TEGRA186_CLK_AFI 4
+/** @brief output of gate CLK_ENB_PCIE2_IOBIST */
+#define TEGRA186_CLK_PCIE2_IOBIST 5
+/** @brief output of gate CLK_ENB_PCIERX0*/
+#define TEGRA186_CLK_PCIERX0 6
+/** @brief output of gate CLK_ENB_PCIERX1*/
+#define TEGRA186_CLK_PCIERX1 7
+/** @brief output of gate CLK_ENB_PCIERX2*/
+#define TEGRA186_CLK_PCIERX2 8
+/** @brief output of gate CLK_ENB_PCIERX3*/
+#define TEGRA186_CLK_PCIERX3 9
+/** @brief output of gate CLK_ENB_PCIERX4*/
+#define TEGRA186_CLK_PCIERX4 10
+/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
+#define TEGRA186_CLK_PLLC_OUT_ISP 11
+/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
+#define TEGRA186_CLK_PLLC_OUT_VE 12
+/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
+#define TEGRA186_CLK_PLLC_OUT_AON 13
+/** @brief output of gate CLK_ENB_SOR_SAFE */
+#define TEGRA186_CLK_SOR_SAFE 39
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
+#define TEGRA186_CLK_I2S2 42
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
+#define TEGRA186_CLK_I2S3 43
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
+#define TEGRA186_CLK_SPDIF_IN 44
+/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
+#define TEGRA186_CLK_SPDIF_DOUBLER 45
+/**  @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
+#define TEGRA186_CLK_SPI3 46
+/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
+#define TEGRA186_CLK_I2C1 47
+/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
+#define TEGRA186_CLK_I2C5 48
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
+#define TEGRA186_CLK_SPI1 49
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
+#define TEGRA186_CLK_ISP 50
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
+#define TEGRA186_CLK_VI 51
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
+#define TEGRA186_CLK_SDMMC1 52
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
+#define TEGRA186_CLK_SDMMC2 53
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
+#define TEGRA186_CLK_SDMMC4 54
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
+#define TEGRA186_CLK_UARTA 55
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
+#define TEGRA186_CLK_UARTB 56
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
+#define TEGRA186_CLK_HOST1X 57
+/**
+ * @brief controls the EMC clock frequency.
+ * @details Doing a clk_set_rate on this clock will select the
+ * appropriate clock source, program the source rate and execute a
+ * specific sequence to switch to the new clock source for both memory
+ * controllers. This can be used to control the balance between memory
+ * throughput and memory controller power.
+ */
+#define TEGRA186_CLK_EMC 58
+/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
+#define TEGRA186_CLK_EXTPERIPH4 73
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
+#define TEGRA186_CLK_SPI4 74
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
+#define TEGRA186_CLK_I2C3 75
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
+#define TEGRA186_CLK_SDMMC3 76
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
+#define TEGRA186_CLK_UARTD 77
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
+#define TEGRA186_CLK_I2S1 79
+/** output of gate CLK_ENB_DTV */
+#define TEGRA186_CLK_DTV 80
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
+#define TEGRA186_CLK_TSEC 81
+/** @brief output of gate CLK_ENB_DP2 */
+#define TEGRA186_CLK_DP2 82
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
+#define TEGRA186_CLK_I2S4 84
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
+#define TEGRA186_CLK_I2S5 85
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
+#define TEGRA186_CLK_I2C4 86
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
+#define TEGRA186_CLK_AHUB 87
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
+#define TEGRA186_CLK_HDA2CODEC_2X 88
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
+#define TEGRA186_CLK_EXTPERIPH1 89
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
+#define TEGRA186_CLK_EXTPERIPH2 90
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
+#define TEGRA186_CLK_EXTPERIPH3 91
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
+#define TEGRA186_CLK_I2C_SLOW 92
+/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
+#define TEGRA186_CLK_SOR1 93
+/** @brief output of gate CLK_ENB_CEC */
+#define TEGRA186_CLK_CEC 94
+/** @brief output of gate CLK_ENB_DPAUX1 */
+#define TEGRA186_CLK_DPAUX1 95
+/** @brief output of gate CLK_ENB_DPAUX */
+#define TEGRA186_CLK_DPAUX 96
+/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
+#define TEGRA186_CLK_SOR0 97
+/** @brief output of gate CLK_ENB_HDA2HDMICODEC */
+#define TEGRA186_CLK_HDA2HDMICODEC 98
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
+#define TEGRA186_CLK_SATA 99
+/** @brief output of gate CLK_ENB_SATA_OOB */
+#define TEGRA186_CLK_SATA_OOB 100
+/** @brief output of gate CLK_ENB_SATA_IOBIST */
+#define TEGRA186_CLK_SATA_IOBIST 101
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
+#define TEGRA186_CLK_HDA 102
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
+#define TEGRA186_CLK_SE 103
+/** @brief output of gate CLK_ENB_APB2APE */
+#define TEGRA186_CLK_APB2APE 104
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
+#define TEGRA186_CLK_APE 105
+/** @brief output of gate CLK_ENB_IQC1 */
+#define TEGRA186_CLK_IQC1 106
+/** @brief output of gate CLK_ENB_IQC2 */
+#define TEGRA186_CLK_IQC2 107
+/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
+#define TEGRA186_CLK_PLLREFE_OUT 108
+/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
+#define TEGRA186_CLK_PLLREFE_PLL_REF 109
+/** @brief output of gate CLK_ENB_PLLC4_OUT */
+#define TEGRA186_CLK_PLLC4_OUT 110
+/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB 111
+/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_DEV 112
+/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_HOST 113
+/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_SS 114
+/** @brief output of gate CLK_ENB_DSI */
+#define TEGRA186_CLK_DSI 115
+/** @brief output of gate CLK_ENB_MIPI_CAL */
+#define TEGRA186_CLK_MIPI_CAL 116
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
+#define TEGRA186_CLK_DSIA_LP 117
+/** @brief output of gate CLK_ENB_DSIB */
+#define TEGRA186_CLK_DSIB 118
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
+#define TEGRA186_CLK_DSIB_LP 119
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
+#define TEGRA186_CLK_DMIC1 122
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
+#define TEGRA186_CLK_DMIC2 123
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
+#define TEGRA186_CLK_AUD_MCLK 124
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
+#define TEGRA186_CLK_I2C6 125
+/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
+#define TEGRA186_CLK_UART_FST_MIPI_CAL 126
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
+#define TEGRA186_CLK_VIC 127
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
+#define TEGRA186_CLK_SDMMC_LEGACY_TM 128
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
+#define TEGRA186_CLK_NVDEC 129
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
+#define TEGRA186_CLK_NVJPG 130
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
+#define TEGRA186_CLK_NVENC 131
+/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
+#define TEGRA186_CLK_QSPI 132
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
+#define TEGRA186_CLK_VI_I2C 133
+/** @brief output of gate CLK_ENB_HSIC_TRK */
+#define TEGRA186_CLK_HSIC_TRK 134
+/** @brief output of gate CLK_ENB_USB2_TRK */
+#define TEGRA186_CLK_USB2_TRK 135
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
+#define TEGRA186_CLK_MAUD 136
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
+#define TEGRA186_CLK_TSECB 137
+/** @brief output of gate CLK_ENB_ADSP */
+#define TEGRA186_CLK_ADSP 138
+/** @brief output of gate CLK_ENB_ADSPNEON */
+#define TEGRA186_CLK_ADSPNEON 139
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
+#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
+/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
+#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
+#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
+/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
+#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
+/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
+#define TEGRA186_CLK_MPHY_L0_RX_ANA 144
+/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
+#define TEGRA186_CLK_MPHY_L1_RX_ANA 145
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
+#define TEGRA186_CLK_MPHY_IOBIST 146
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
+#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
+#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
+#define TEGRA186_CLK_AXI_CBB 149
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
+#define TEGRA186_CLK_DMIC3 150
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
+#define TEGRA186_CLK_DMIC4 151
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
+#define TEGRA186_CLK_DSPK1 152
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
+#define TEGRA186_CLK_DSPK2 153
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
+#define TEGRA186_CLK_I2S6 154
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
+#define TEGRA186_CLK_NVDISPLAY_P0 155
+/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
+#define TEGRA186_CLK_NVDISPLAY_DISP 156
+/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
+#define TEGRA186_CLK_NVDISPLAY_DSC 157
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
+#define TEGRA186_CLK_NVDISPLAYHUB 158
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
+#define TEGRA186_CLK_NVDISPLAY_P1 159
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
+#define TEGRA186_CLK_NVDISPLAY_P2 160
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
+#define TEGRA186_CLK_TACH 166
+/** @brief output of gate CLK_ENB_EQOS */
+#define TEGRA186_CLK_EQOS_AXI 167
+/** @brief output of gate CLK_ENB_EQOS_RX */
+#define TEGRA186_CLK_EQOS_RX 168
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
+#define TEGRA186_CLK_UFSHC 178
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
+#define TEGRA186_CLK_UFSDEV_REF 179
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
+#define TEGRA186_CLK_NVCSI 180
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
+#define TEGRA186_CLK_NVCSILP 181
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
+#define TEGRA186_CLK_I2C7 182
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
+#define TEGRA186_CLK_I2C9 183
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
+#define TEGRA186_CLK_I2C12 184
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
+#define TEGRA186_CLK_I2C13 185
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
+#define TEGRA186_CLK_I2C14 186
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
+#define TEGRA186_CLK_PWM1 187
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
+#define TEGRA186_CLK_PWM2 188
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
+#define TEGRA186_CLK_PWM3 189
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
+#define TEGRA186_CLK_PWM5 190
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
+#define TEGRA186_CLK_PWM6 191
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
+#define TEGRA186_CLK_PWM7 192
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
+#define TEGRA186_CLK_PWM8 193
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
+#define TEGRA186_CLK_UARTE 194
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
+#define TEGRA186_CLK_UARTF 195
+/** @deprecated */
+#define TEGRA186_CLK_DBGAPB 196
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
+#define TEGRA186_CLK_BPMP_CPU_NIC 197
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
+#define TEGRA186_CLK_BPMP_APB 199
+/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
+#define TEGRA186_CLK_ACTMON 201
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
+#define TEGRA186_CLK_AON_CPU_NIC 208
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
+#define TEGRA186_CLK_CAN1 210
+/** @brief output of gate CLK_ENB_CAN1_HOST */
+#define TEGRA186_CLK_CAN1_HOST 211
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
+#define TEGRA186_CLK_CAN2 212
+/** @brief output of gate CLK_ENB_CAN2_HOST */
+#define TEGRA186_CLK_CAN2_HOST 213
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
+#define TEGRA186_CLK_AON_APB 214
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
+#define TEGRA186_CLK_UARTC 215
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
+#define TEGRA186_CLK_UARTG 216
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
+#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
+#define TEGRA186_CLK_I2C2 218
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
+#define TEGRA186_CLK_I2C8 219
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
+#define TEGRA186_CLK_I2C10 220
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
+#define TEGRA186_CLK_AON_I2C_SLOW 221
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
+#define TEGRA186_CLK_SPI2 222
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
+#define TEGRA186_CLK_DMIC5 223
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
+#define TEGRA186_CLK_AON_TOUCH 224
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
+#define TEGRA186_CLK_PWM4 225
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
+#define TEGRA186_CLK_TSC 226
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
+#define TEGRA186_CLK_MSS_ENCRYPT 227
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
+#define TEGRA186_CLK_SCE_CPU_NIC 228
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
+#define TEGRA186_CLK_SCE_APB 230
+/** @brief output of gate CLK_ENB_DSIC */
+#define TEGRA186_CLK_DSIC 231
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
+#define TEGRA186_CLK_DSIC_LP 232
+/** @brief output of gate CLK_ENB_DSID */
+#define TEGRA186_CLK_DSID 233
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
+#define TEGRA186_CLK_DSID_LP 234
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
+#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
+#define TEGRA186_CLK_SPDIF_OUT 238
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
+#define TEGRA186_CLK_EQOS_PTP_REF 239
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
+#define TEGRA186_CLK_EQOS_TX 240
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
+#define TEGRA186_CLK_USB2_HSIC_TRK 241
+/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_CORE_SS 242
+/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_CORE_DEV 243
+/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_FALCON 244
+/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
+#define TEGRA186_CLK_XUSB_FS 245
+/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
+#define TEGRA186_CLK_PLL_A_OUT0 246
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
+#define TEGRA186_CLK_SYNC_I2S1 247
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
+#define TEGRA186_CLK_SYNC_I2S2 248
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
+#define TEGRA186_CLK_SYNC_I2S3 249
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
+#define TEGRA186_CLK_SYNC_I2S4 250
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
+#define TEGRA186_CLK_SYNC_I2S5 251
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
+#define TEGRA186_CLK_SYNC_I2S6 252
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
+#define TEGRA186_CLK_SYNC_DSPK1 253
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
+#define TEGRA186_CLK_SYNC_DSPK2 254
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
+#define TEGRA186_CLK_SYNC_DMIC1 255
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
+#define TEGRA186_CLK_SYNC_DMIC2 256
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
+#define TEGRA186_CLK_SYNC_DMIC3 257
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
+#define TEGRA186_CLK_SYNC_DMIC4 259
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
+#define TEGRA186_CLK_SYNC_SPDIF 260
+/** @brief output of gate CLK_ENB_PLLREFE_OUT */
+#define TEGRA186_CLK_PLLREFE_OUT_GATED 261
+/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
+  *      * VCO/pdiv defined by this clock object
+  *      * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
+  */
+#define TEGRA186_CLK_PLLREFE_OUT1 262
+#define TEGRA186_CLK_PLLD_OUT1 267
+/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
+#define TEGRA186_CLK_PLLP_OUT0 269
+/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
+#define TEGRA186_CLK_PLLP_OUT5 270
+/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
+#define TEGRA186_CLK_PLLA 271
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
+#define TEGRA186_CLK_ACLK 273
+/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
+#define TEGRA186_CLK_PLL_U_48M 274
+/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
+#define TEGRA186_CLK_PLL_U_480M 275
+/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
+#define TEGRA186_CLK_PLLC4_OUT0 276
+/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
+#define TEGRA186_CLK_PLLC4_OUT1 277
+/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
+#define TEGRA186_CLK_PLLC4_OUT2 278
+/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
+#define TEGRA186_CLK_PLLC4_OUT_MUX 279
+/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
+#define TEGRA186_CLK_DFLLDISP_DIV 284
+/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
+#define TEGRA186_CLK_PLLDISPHUB_DIV 285
+/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
+#define TEGRA186_CLK_PLLP_DIV8 286
+/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
+#define TEGRA186_CLK_BPMP_NIC 287
+/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
+#define TEGRA186_CLK_PLL_A_OUT1 288
+/** @deprecated */
+#define TEGRA186_CLK_GPC2CLK 289
+/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
+#define TEGRA186_CLK_KFUSE 293
+/**
+ * @brief controls the PLLE hardware sequencer.
+ * @details This clock only has enable and disable methods. When the
+ * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
+ * hw based on the control signals from the PCIe, SATA and XUSB
+ * clocks. When the PLLE hw sequencer is disabled, the state of PLLE
+ * is controlled by sw using clk_enable/clk_disable on
+ * TEGRA186_CLK_PLLE.
+ */
+#define TEGRA186_CLK_PLLE_PWRSEQ 294
+/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
+#define TEGRA186_CLK_PLLREFE_REF 295
+/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
+#define TEGRA186_CLK_SOR0_OUT 296
+/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
+#define TEGRA186_CLK_SOR1_OUT 297
+/** @brief fixed /5 divider.  Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
+#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
+/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
+#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
+#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
+/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
+#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
+/** @brief controls the UPHY_PLL0 hardware sqeuencer */
+#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
+/** @brief controls the UPHY_PLL1 hardware sqeuencer */
+#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
+/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
+#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
+/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
+#define TEGRA186_CLK_PLLREFE_PEX 307
+/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
+#define TEGRA186_CLK_PLLREFE_IDDQ 308
+/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
+#define TEGRA186_CLK_QSPI_OUT 309
+/**
+ * @brief GPC2CLK-div-2
+ * @details fixed /2 divider. Output frequency is
+ * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
+ * frequency at which the GPU graphics engine runs. */
+#define TEGRA186_CLK_GPCCLK 310
+/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
+#define TEGRA186_CLK_AON_NIC 450
+/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
+#define TEGRA186_CLK_SCE_NIC 451
+/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
+#define TEGRA186_CLK_PLLE 512
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
+#define TEGRA186_CLK_PLLC 513
+/** Fixed 408MHz PLL for use by peripheral clocks */
+#define TEGRA186_CLK_PLLP 516
+/** @deprecated */
+#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
+#define TEGRA186_CLK_PLLD 518
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
+#define TEGRA186_CLK_PLLD2 519
+/**
+ * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
+ * @details Note that this clock only controls the VCO output, before
+ * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
+ * information.
+ */
+#define TEGRA186_CLK_PLLREFE_VCO 520
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
+#define TEGRA186_CLK_PLLC2 521
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
+#define TEGRA186_CLK_PLLC3 522
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
+#define TEGRA186_CLK_PLLDP 523
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
+#define TEGRA186_CLK_PLLC4_VCO 524
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
+#define TEGRA186_CLK_PLLA1 525
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
+#define TEGRA186_CLK_PLLNVCSI 526
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
+#define TEGRA186_CLK_PLLDISPHUB 527
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
+#define TEGRA186_CLK_PLLD3 528
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
+#define TEGRA186_CLK_PLLBPMPCAM 531
+/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
+#define TEGRA186_CLK_PLLAON 532
+/** Fixed frequency 960MHz PLL for USB and EAVB */
+#define TEGRA186_CLK_PLLU 533
+/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
+#define TEGRA186_CLK_PLLC4_VCO_DIV2 535
+/** @brief NAFLL clock source for AXI_CBB */
+#define TEGRA186_CLK_NAFLL_AXI_CBB 564
+/** @brief NAFLL clock source for BPMP */
+#define TEGRA186_CLK_NAFLL_BPMP 565
+/** @brief NAFLL clock source for ISP */
+#define TEGRA186_CLK_NAFLL_ISP 566
+/** @brief NAFLL clock source for NVDEC */
+#define TEGRA186_CLK_NAFLL_NVDEC 567
+/** @brief NAFLL clock source for NVENC */
+#define TEGRA186_CLK_NAFLL_NVENC 568
+/** @brief NAFLL clock source for NVJPG */
+#define TEGRA186_CLK_NAFLL_NVJPG 569
+/** @brief NAFLL clock source for SCE */
+#define TEGRA186_CLK_NAFLL_SCE 570
+/** @brief NAFLL clock source for SE */
+#define TEGRA186_CLK_NAFLL_SE 571
+/** @brief NAFLL clock source for TSEC */
+#define TEGRA186_CLK_NAFLL_TSEC 572
+/** @brief NAFLL clock source for TSECB */
+#define TEGRA186_CLK_NAFLL_TSECB 573
+/** @brief NAFLL clock source for VI */
+#define TEGRA186_CLK_NAFLL_VI 574
+/** @brief NAFLL clock source for VIC */
+#define TEGRA186_CLK_NAFLL_VIC 575
+/** @brief NAFLL clock source for DISP */
+#define TEGRA186_CLK_NAFLL_DISP 576
+/** @brief NAFLL clock source for GPU */
+#define TEGRA186_CLK_NAFLL_GPU 577
+/** @brief NAFLL clock source for M-CPU cluster */
+#define TEGRA186_CLK_NAFLL_MCPU 578
+/** @brief NAFLL clock source for B-CPU cluster */
+#define TEGRA186_CLK_NAFLL_BCPU 579
+/** @brief input from Tegra's CLK_32K_IN pad */
+#define TEGRA186_CLK_CLK_32K 608
+/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
+#define TEGRA186_CLK_CLK_M 609
+/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
+#define TEGRA186_CLK_PLL_REF 610
+/** @brief input from Tegra's XTAL_IN */
+#define TEGRA186_CLK_OSC 612
+/** @brief clock recovered from EAVB input */
+#define TEGRA186_CLK_EQOS_RX_INPUT 613
+/** @brief clock recovered from DTV input */
+#define TEGRA186_CLK_DTV_INPUT 614
+/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
+#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
+/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
+#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
+/** @brief clock recovered from I2S1 input */
+#define TEGRA186_CLK_I2S1_SYNC_INPUT 617
+/** @brief clock recovered from I2S2 input */
+#define TEGRA186_CLK_I2S2_SYNC_INPUT 618
+/** @brief clock recovered from I2S3 input */
+#define TEGRA186_CLK_I2S3_SYNC_INPUT 619
+/** @brief clock recovered from I2S4 input */
+#define TEGRA186_CLK_I2S4_SYNC_INPUT 620
+/** @brief clock recovered from I2S5 input */
+#define TEGRA186_CLK_I2S5_SYNC_INPUT 621
+/** @brief clock recovered from I2S6 input */
+#define TEGRA186_CLK_I2S6_SYNC_INPUT 622
+/** @brief clock recovered from SPDIFIN input */
+#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
+
+/**
+ * @brief subject to change
+ * @details maximum clock identifier value plus one.
+ */
+#define TEGRA186_CLK_CLK_MAX 624
+
+/** @} */
+
+#endif
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
new file mode 100644
index 0000000..04500b2
--- /dev/null
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -0,0 +1,158 @@
+/*
+ * This header provides constants for binding nvidia,tegra20-car.
+ *
+ * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 95 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
+
+#define TEGRA20_CLK_CPU 0
+/* 1 */
+/* 2 */
+#define TEGRA20_CLK_AC97 3
+#define TEGRA20_CLK_RTC 4
+#define TEGRA20_CLK_TIMER 5
+#define TEGRA20_CLK_UARTA 6
+/* 7 (register bit affects uart2 and vfir) */
+#define TEGRA20_CLK_GPIO 8
+#define TEGRA20_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA20_CLK_I2S1 11
+#define TEGRA20_CLK_I2C1 12
+#define TEGRA20_CLK_NDFLASH 13
+#define TEGRA20_CLK_SDMMC1 14
+#define TEGRA20_CLK_SDMMC4 15
+#define TEGRA20_CLK_TWC 16
+#define TEGRA20_CLK_PWM 17
+#define TEGRA20_CLK_I2S2 18
+#define TEGRA20_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA20_CLK_GR2D 21
+#define TEGRA20_CLK_USBD 22
+#define TEGRA20_CLK_ISP 23
+#define TEGRA20_CLK_GR3D 24
+#define TEGRA20_CLK_IDE 25
+#define TEGRA20_CLK_DISP2 26
+#define TEGRA20_CLK_DISP1 27
+#define TEGRA20_CLK_HOST1X 28
+#define TEGRA20_CLK_VCP 29
+/* 30 */
+#define TEGRA20_CLK_CACHE2 31
+
+#define TEGRA20_CLK_MC 32
+#define TEGRA20_CLK_AHBDMA 33
+#define TEGRA20_CLK_APBDMA 34
+/* 35 */
+#define TEGRA20_CLK_KBC 36
+#define TEGRA20_CLK_STAT_MON 37
+#define TEGRA20_CLK_PMC 38
+#define TEGRA20_CLK_FUSE 39
+#define TEGRA20_CLK_KFUSE 40
+#define TEGRA20_CLK_SBC1 41
+#define TEGRA20_CLK_NOR 42
+#define TEGRA20_CLK_SPI 43
+#define TEGRA20_CLK_SBC2 44
+#define TEGRA20_CLK_XIO 45
+#define TEGRA20_CLK_SBC3 46
+#define TEGRA20_CLK_DVC 47
+#define TEGRA20_CLK_DSI 48
+/* 49 (register bit affects tvo and cve) */
+#define TEGRA20_CLK_MIPI 50
+#define TEGRA20_CLK_HDMI 51
+#define TEGRA20_CLK_CSI 52
+#define TEGRA20_CLK_TVDAC 53
+#define TEGRA20_CLK_I2C2 54
+#define TEGRA20_CLK_UARTC 55
+/* 56 */
+#define TEGRA20_CLK_EMC 57
+#define TEGRA20_CLK_USB2 58
+#define TEGRA20_CLK_USB3 59
+#define TEGRA20_CLK_MPE 60
+#define TEGRA20_CLK_VDE 61
+#define TEGRA20_CLK_BSEA 62
+#define TEGRA20_CLK_BSEV 63
+
+#define TEGRA20_CLK_SPEEDO 64
+#define TEGRA20_CLK_UARTD 65
+#define TEGRA20_CLK_UARTE 66
+#define TEGRA20_CLK_I2C3 67
+#define TEGRA20_CLK_SBC4 68
+#define TEGRA20_CLK_SDMMC3 69
+#define TEGRA20_CLK_PEX 70
+#define TEGRA20_CLK_OWR 71
+#define TEGRA20_CLK_AFI 72
+#define TEGRA20_CLK_CSITE 73
+/* 74 */
+#define TEGRA20_CLK_AVPUCQ 75
+#define TEGRA20_CLK_LA 76
+/* 77 */
+/* 78 */
+/* 79 */
+/* 80 */
+/* 81 */
+/* 82 */
+/* 83 */
+#define TEGRA20_CLK_IRAMA 84
+#define TEGRA20_CLK_IRAMB 85
+#define TEGRA20_CLK_IRAMC 86
+#define TEGRA20_CLK_IRAMD 87
+#define TEGRA20_CLK_CRAM2 88
+#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
+#define TEGRA20_CLK_CLK_D 90
+/* 91 */
+#define TEGRA20_CLK_CSUS 92
+#define TEGRA20_CLK_CDEV2 93
+#define TEGRA20_CLK_CDEV1 94
+/* 95 */
+
+#define TEGRA20_CLK_UARTB 96
+#define TEGRA20_CLK_VFIR 97
+#define TEGRA20_CLK_SPDIF_IN 98
+#define TEGRA20_CLK_SPDIF_OUT 99
+#define TEGRA20_CLK_VI 100
+#define TEGRA20_CLK_VI_SENSOR 101
+#define TEGRA20_CLK_TVO 102
+#define TEGRA20_CLK_CVE 103
+#define TEGRA20_CLK_OSC 104
+#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
+#define TEGRA20_CLK_CLK_M 106
+#define TEGRA20_CLK_SCLK 107
+#define TEGRA20_CLK_CCLK 108
+#define TEGRA20_CLK_HCLK 109
+#define TEGRA20_CLK_PCLK 110
+#define TEGRA20_CLK_BLINK 111
+#define TEGRA20_CLK_PLL_A 112
+#define TEGRA20_CLK_PLL_A_OUT0 113
+#define TEGRA20_CLK_PLL_C 114
+#define TEGRA20_CLK_PLL_C_OUT1 115
+#define TEGRA20_CLK_PLL_D 116
+#define TEGRA20_CLK_PLL_D_OUT0 117
+#define TEGRA20_CLK_PLL_E 118
+#define TEGRA20_CLK_PLL_M 119
+#define TEGRA20_CLK_PLL_M_OUT1 120
+#define TEGRA20_CLK_PLL_P 121
+#define TEGRA20_CLK_PLL_P_OUT1 122
+#define TEGRA20_CLK_PLL_P_OUT2 123
+#define TEGRA20_CLK_PLL_P_OUT3 124
+#define TEGRA20_CLK_PLL_P_OUT4 125
+#define TEGRA20_CLK_PLL_S 126
+#define TEGRA20_CLK_PLL_U 127
+
+#define TEGRA20_CLK_PLL_X 128
+#define TEGRA20_CLK_COP 129 /* a/k/a avp */
+#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
+#define TEGRA20_CLK_PLL_REF 131
+#define TEGRA20_CLK_TWD 132
+#define TEGRA20_CLK_CLK_MAX 133
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
new file mode 100644
index 0000000..bd3530e
--- /dev/null
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -0,0 +1,401 @@
+/*
+ * This header provides constants for binding nvidia,tegra210-car.
+ *
+ * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 224 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 224 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+#define TEGRA210_CLK_ISPB 3
+#define TEGRA210_CLK_RTC 4
+#define TEGRA210_CLK_TIMER 5
+#define TEGRA210_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+#define TEGRA210_CLK_GPIO 8
+#define TEGRA210_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA210_CLK_I2S1 11
+#define TEGRA210_CLK_I2C1 12
+/* 13 */
+#define TEGRA210_CLK_SDMMC1 14
+#define TEGRA210_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA210_CLK_PWM 17
+#define TEGRA210_CLK_I2S2 18
+/* 19 */
+/* 20 (register bit affects vi and vi_sensor) */
+/* 21 */
+#define TEGRA210_CLK_USBD 22
+#define TEGRA210_CLK_ISP 23
+/* 24 */
+/* 25 */
+#define TEGRA210_CLK_DISP2 26
+#define TEGRA210_CLK_DISP1 27
+#define TEGRA210_CLK_HOST1X 28
+/* 29 */
+#define TEGRA210_CLK_I2S0 30
+/* 31 */
+
+#define TEGRA210_CLK_MC 32
+#define TEGRA210_CLK_AHBDMA 33
+#define TEGRA210_CLK_APBDMA 34
+/* 35 */
+/* 36 */
+/* 37 */
+#define TEGRA210_CLK_PMC 38
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA210_CLK_KFUSE 40
+#define TEGRA210_CLK_SBC1 41
+/* 42 */
+/* 43 */
+#define TEGRA210_CLK_SBC2 44
+/* 45 */
+#define TEGRA210_CLK_SBC3 46
+#define TEGRA210_CLK_I2C5 47
+#define TEGRA210_CLK_DSIA 48
+/* 49 */
+/* 50 */
+/* 51 */
+#define TEGRA210_CLK_CSI 52
+/* 53 */
+#define TEGRA210_CLK_I2C2 54
+#define TEGRA210_CLK_UARTC 55
+#define TEGRA210_CLK_MIPI_CAL 56
+#define TEGRA210_CLK_EMC 57
+#define TEGRA210_CLK_USB2 58
+/* 59 */
+/* 60 */
+/* 61 */
+/* 62 */
+#define TEGRA210_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA210_CLK_UARTD 65
+/* 66 */
+#define TEGRA210_CLK_I2C3 67
+#define TEGRA210_CLK_SBC4 68
+#define TEGRA210_CLK_SDMMC3 69
+#define TEGRA210_CLK_PCIE 70
+#define TEGRA210_CLK_OWR 71
+#define TEGRA210_CLK_AFI 72
+#define TEGRA210_CLK_CSITE 73
+/* 74 */
+/* 75 */
+/* 76 */
+/* 77 */
+#define TEGRA210_CLK_SOC_THERM 78
+#define TEGRA210_CLK_DTV 79
+/* 80 */
+#define TEGRA210_CLK_I2CSLOW 81
+#define TEGRA210_CLK_DSIB 82
+#define TEGRA210_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA210_CLK_XUSB_HOST 89
+/* 90 */
+/* 91 */
+#define TEGRA210_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA210_CLK_MSELECT 99
+#define TEGRA210_CLK_TSENSOR 100
+#define TEGRA210_CLK_I2S3 101
+#define TEGRA210_CLK_I2S4 102
+#define TEGRA210_CLK_I2C4 103
+/* 104 */
+/* 105 */
+#define TEGRA210_CLK_D_AUDIO 106
+#define TEGRA210_CLK_APB2APE 107
+/* 108 */
+/* 109 */
+/* 110 */
+#define TEGRA210_CLK_HDA2CODEC_2X 111
+/* 112 */
+/* 113 */
+/* 114 */
+/* 115 */
+/* 116 */
+/* 117 */
+#define TEGRA210_CLK_SPDIF_2X 118
+#define TEGRA210_CLK_ACTMON 119
+#define TEGRA210_CLK_EXTERN1 120
+#define TEGRA210_CLK_EXTERN2 121
+#define TEGRA210_CLK_EXTERN3 122
+#define TEGRA210_CLK_SATA_OOB 123
+#define TEGRA210_CLK_SATA 124
+#define TEGRA210_CLK_HDA 125
+/* 126 */
+/* 127 */
+
+#define TEGRA210_CLK_HDA2HDMI 128
+/* 129 */
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
+#define TEGRA210_CLK_XUSB_GATE 143
+#define TEGRA210_CLK_CILAB 144
+#define TEGRA210_CLK_CILCD 145
+#define TEGRA210_CLK_CILE 146
+#define TEGRA210_CLK_DSIALP 147
+#define TEGRA210_CLK_DSIBLP 148
+#define TEGRA210_CLK_ENTROPY 149
+/* 150 */
+/* 151 */
+/* 152 */
+/* 153 */
+/* 154 */
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA210_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+#define TEGRA210_CLK_DMIC1 161
+#define TEGRA210_CLK_DMIC2 162
+/* 163 */
+/* 164 */
+/* 165 */
+#define TEGRA210_CLK_I2C6 166
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+#define TEGRA210_CLK_VIM2_CLK 171
+/* 172 */
+#define TEGRA210_CLK_MIPIBIF 173
+/* 174 */
+/* 175 */
+/* 176 */
+#define TEGRA210_CLK_CLK72MHZ 177
+#define TEGRA210_CLK_VIC03 178
+/* 179 */
+/* 180 */
+#define TEGRA210_CLK_DPAUX 181
+#define TEGRA210_CLK_SOR0 182
+#define TEGRA210_CLK_SOR1 183
+#define TEGRA210_CLK_GPU 184
+#define TEGRA210_CLK_DBGAPB 185
+/* 186 */
+#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
+/* 188 */
+#define TEGRA210_CLK_PLL_G_REF 189
+/* 190 */
+/* 191 */
+
+/* 192 */
+#define TEGRA210_CLK_SDMMC_LEGACY 193
+#define TEGRA210_CLK_NVDEC 194
+#define TEGRA210_CLK_NVJPG 195
+/* 196 */
+#define TEGRA210_CLK_DMIC3 197
+#define TEGRA210_CLK_APE 198
+/* 199 */
+/* 200 */
+/* 201 */
+#define TEGRA210_CLK_MAUD 202
+/* 203 */
+/* 204 */
+/* 205 */
+#define TEGRA210_CLK_TSECB 206
+#define TEGRA210_CLK_DPAUX1 207
+#define TEGRA210_CLK_VI_I2C 208
+#define TEGRA210_CLK_HSIC_TRK 209
+#define TEGRA210_CLK_USB2_TRK 210
+#define TEGRA210_CLK_QSPI 211
+#define TEGRA210_CLK_UARTAPE 212
+/* 213 */
+/* 214 */
+/* 215 */
+/* 216 */
+/* 217 */
+/* 218 */
+#define TEGRA210_CLK_NVENC 219
+/* 220 */
+/* 221 */
+#define TEGRA210_CLK_SOR_SAFE 222
+#define TEGRA210_CLK_PLL_P_OUT_CPU 223
+
+
+#define TEGRA210_CLK_UARTB 224
+#define TEGRA210_CLK_VFIR 225
+#define TEGRA210_CLK_SPDIF_IN 226
+#define TEGRA210_CLK_SPDIF_OUT 227
+#define TEGRA210_CLK_VI 228
+#define TEGRA210_CLK_VI_SENSOR 229
+#define TEGRA210_CLK_FUSE 230
+#define TEGRA210_CLK_FUSE_BURN 231
+#define TEGRA210_CLK_CLK_32K 232
+#define TEGRA210_CLK_CLK_M 233
+#define TEGRA210_CLK_CLK_M_DIV2 234
+#define TEGRA210_CLK_CLK_M_DIV4 235
+#define TEGRA210_CLK_PLL_REF 236
+#define TEGRA210_CLK_PLL_C 237
+#define TEGRA210_CLK_PLL_C_OUT1 238
+#define TEGRA210_CLK_PLL_C2 239
+#define TEGRA210_CLK_PLL_C3 240
+#define TEGRA210_CLK_PLL_M 241
+#define TEGRA210_CLK_PLL_M_OUT1 242
+#define TEGRA210_CLK_PLL_P 243
+#define TEGRA210_CLK_PLL_P_OUT1 244
+#define TEGRA210_CLK_PLL_P_OUT2 245
+#define TEGRA210_CLK_PLL_P_OUT3 246
+#define TEGRA210_CLK_PLL_P_OUT4 247
+#define TEGRA210_CLK_PLL_A 248
+#define TEGRA210_CLK_PLL_A_OUT0 249
+#define TEGRA210_CLK_PLL_D 250
+#define TEGRA210_CLK_PLL_D_OUT0 251
+#define TEGRA210_CLK_PLL_D2 252
+#define TEGRA210_CLK_PLL_D2_OUT0 253
+#define TEGRA210_CLK_PLL_U 254
+#define TEGRA210_CLK_PLL_U_480M 255
+
+#define TEGRA210_CLK_PLL_U_60M 256
+#define TEGRA210_CLK_PLL_U_48M 257
+/* 258 */
+#define TEGRA210_CLK_PLL_X 259
+#define TEGRA210_CLK_PLL_X_OUT0 260
+#define TEGRA210_CLK_PLL_RE_VCO 261
+#define TEGRA210_CLK_PLL_RE_OUT 262
+#define TEGRA210_CLK_PLL_E 263
+#define TEGRA210_CLK_SPDIF_IN_SYNC 264
+#define TEGRA210_CLK_I2S0_SYNC 265
+#define TEGRA210_CLK_I2S1_SYNC 266
+#define TEGRA210_CLK_I2S2_SYNC 267
+#define TEGRA210_CLK_I2S3_SYNC 268
+#define TEGRA210_CLK_I2S4_SYNC 269
+#define TEGRA210_CLK_VIMCLK_SYNC 270
+#define TEGRA210_CLK_AUDIO0 271
+#define TEGRA210_CLK_AUDIO1 272
+#define TEGRA210_CLK_AUDIO2 273
+#define TEGRA210_CLK_AUDIO3 274
+#define TEGRA210_CLK_AUDIO4 275
+#define TEGRA210_CLK_SPDIF 276
+#define TEGRA210_CLK_CLK_OUT_1 277
+#define TEGRA210_CLK_CLK_OUT_2 278
+#define TEGRA210_CLK_CLK_OUT_3 279
+#define TEGRA210_CLK_BLINK 280
+/* 281 */
+/* 282 */
+/* 283 */
+#define TEGRA210_CLK_XUSB_HOST_SRC 284
+#define TEGRA210_CLK_XUSB_FALCON_SRC 285
+#define TEGRA210_CLK_XUSB_FS_SRC 286
+#define TEGRA210_CLK_XUSB_SS_SRC 287
+
+#define TEGRA210_CLK_XUSB_DEV_SRC 288
+#define TEGRA210_CLK_XUSB_DEV 289
+#define TEGRA210_CLK_XUSB_HS_SRC 290
+#define TEGRA210_CLK_SCLK 291
+#define TEGRA210_CLK_HCLK 292
+#define TEGRA210_CLK_PCLK 293
+#define TEGRA210_CLK_CCLK_G 294
+#define TEGRA210_CLK_CCLK_LP 295
+#define TEGRA210_CLK_DFLL_REF 296
+#define TEGRA210_CLK_DFLL_SOC 297
+#define TEGRA210_CLK_VI_SENSOR2 298
+#define TEGRA210_CLK_PLL_P_OUT5 299
+#define TEGRA210_CLK_CML0 300
+#define TEGRA210_CLK_CML1 301
+#define TEGRA210_CLK_PLL_C4 302
+#define TEGRA210_CLK_PLL_DP 303
+#define TEGRA210_CLK_PLL_E_MUX 304
+#define TEGRA210_CLK_PLL_MB 305
+#define TEGRA210_CLK_PLL_A1 306
+#define TEGRA210_CLK_PLL_D_DSI_OUT 307
+#define TEGRA210_CLK_PLL_C4_OUT0 308
+#define TEGRA210_CLK_PLL_C4_OUT1 309
+#define TEGRA210_CLK_PLL_C4_OUT2 310
+#define TEGRA210_CLK_PLL_C4_OUT3 311
+#define TEGRA210_CLK_PLL_U_OUT 312
+#define TEGRA210_CLK_PLL_U_OUT1 313
+#define TEGRA210_CLK_PLL_U_OUT2 314
+#define TEGRA210_CLK_USB2_HSIC_TRK 315
+#define TEGRA210_CLK_PLL_P_OUT_HSIO 316
+#define TEGRA210_CLK_PLL_P_OUT_XUSB 317
+#define TEGRA210_CLK_XUSB_SSP_SRC 318
+#define TEGRA210_CLK_PLL_RE_OUT1 319
+/* 320 */
+/* 321 */
+/* 322 */
+/* 323 */
+/* 324 */
+/* 325 */
+/* 326 */
+/* 327 */
+/* 328 */
+/* 329 */
+/* 330 */
+/* 331 */
+/* 332 */
+/* 333 */
+/* 334 */
+/* 335 */
+/* 336 */
+/* 337 */
+/* 338 */
+/* 339 */
+/* 340 */
+/* 341 */
+/* 342 */
+/* 343 */
+/* 344 */
+/* 345 */
+/* 346 */
+/* 347 */
+/* 348 */
+/* 349 */
+
+#define TEGRA210_CLK_AUDIO0_MUX 350
+#define TEGRA210_CLK_AUDIO1_MUX 351
+#define TEGRA210_CLK_AUDIO2_MUX 352
+#define TEGRA210_CLK_AUDIO3_MUX 353
+#define TEGRA210_CLK_AUDIO4_MUX 354
+#define TEGRA210_CLK_SPDIF_MUX 355
+#define TEGRA210_CLK_CLK_OUT_1_MUX 356
+#define TEGRA210_CLK_CLK_OUT_2_MUX 357
+#define TEGRA210_CLK_CLK_OUT_3_MUX 358
+#define TEGRA210_CLK_DSIA_MUX 359
+#define TEGRA210_CLK_DSIB_MUX 360
+#define TEGRA210_CLK_SOR0_LVDS 361
+#define TEGRA210_CLK_XUSB_SS_DIV2 362
+
+#define TEGRA210_CLK_PLL_M_UD 363
+#define TEGRA210_CLK_PLL_C_UD 364
+#define TEGRA210_CLK_SCLK_MUX 365
+
+#define TEGRA210_CLK_CLK_MAX 366
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
new file mode 100644
index 0000000..889e49b
--- /dev/null
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -0,0 +1,273 @@
+/*
+ * This header provides constants for binding nvidia,tegra30-car.
+ *
+ * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 160 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
+
+#define TEGRA30_CLK_CPU 0
+/* 1 */
+/* 2 */
+/* 3 */
+#define TEGRA30_CLK_RTC 4
+#define TEGRA30_CLK_TIMER 5
+#define TEGRA30_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+#define TEGRA30_CLK_GPIO 8
+#define TEGRA30_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA30_CLK_I2S1 11
+#define TEGRA30_CLK_I2C1 12
+#define TEGRA30_CLK_NDFLASH 13
+#define TEGRA30_CLK_SDMMC1 14
+#define TEGRA30_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA30_CLK_PWM 17
+#define TEGRA30_CLK_I2S2 18
+#define TEGRA30_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA30_CLK_GR2D 21
+#define TEGRA30_CLK_USBD 22
+#define TEGRA30_CLK_ISP 23
+#define TEGRA30_CLK_GR3D 24
+/* 25 */
+#define TEGRA30_CLK_DISP2 26
+#define TEGRA30_CLK_DISP1 27
+#define TEGRA30_CLK_HOST1X 28
+#define TEGRA30_CLK_VCP 29
+#define TEGRA30_CLK_I2S0 30
+#define TEGRA30_CLK_COP_CACHE 31
+
+#define TEGRA30_CLK_MC 32
+#define TEGRA30_CLK_AHBDMA 33
+#define TEGRA30_CLK_APBDMA 34
+/* 35 */
+#define TEGRA30_CLK_KBC 36
+#define TEGRA30_CLK_STATMON 37
+#define TEGRA30_CLK_PMC 38
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA30_CLK_KFUSE 40
+#define TEGRA30_CLK_SBC1 41
+#define TEGRA30_CLK_NOR 42
+/* 43 */
+#define TEGRA30_CLK_SBC2 44
+/* 45 */
+#define TEGRA30_CLK_SBC3 46
+#define TEGRA30_CLK_I2C5 47
+#define TEGRA30_CLK_DSIA 48
+/* 49 (register bit affects cve and tvo) */
+#define TEGRA30_CLK_MIPI 50
+#define TEGRA30_CLK_HDMI 51
+#define TEGRA30_CLK_CSI 52
+#define TEGRA30_CLK_TVDAC 53
+#define TEGRA30_CLK_I2C2 54
+#define TEGRA30_CLK_UARTC 55
+/* 56 */
+#define TEGRA30_CLK_EMC 57
+#define TEGRA30_CLK_USB2 58
+#define TEGRA30_CLK_USB3 59
+#define TEGRA30_CLK_MPE 60
+#define TEGRA30_CLK_VDE 61
+#define TEGRA30_CLK_BSEA 62
+#define TEGRA30_CLK_BSEV 63
+
+#define TEGRA30_CLK_SPEEDO 64
+#define TEGRA30_CLK_UARTD 65
+#define TEGRA30_CLK_UARTE 66
+#define TEGRA30_CLK_I2C3 67
+#define TEGRA30_CLK_SBC4 68
+#define TEGRA30_CLK_SDMMC3 69
+#define TEGRA30_CLK_PCIE 70
+#define TEGRA30_CLK_OWR 71
+#define TEGRA30_CLK_AFI 72
+#define TEGRA30_CLK_CSITE 73
+/* 74 */
+#define TEGRA30_CLK_AVPUCQ 75
+#define TEGRA30_CLK_LA 76
+/* 77 */
+/* 78 */
+#define TEGRA30_CLK_DTV 79
+#define TEGRA30_CLK_NDSPEED 80
+#define TEGRA30_CLK_I2CSLOW 81
+#define TEGRA30_CLK_DSIB 82
+/* 83 */
+#define TEGRA30_CLK_IRAMA 84
+#define TEGRA30_CLK_IRAMB 85
+#define TEGRA30_CLK_IRAMC 86
+#define TEGRA30_CLK_IRAMD 87
+#define TEGRA30_CLK_CRAM2 88
+/* 89 */
+#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
+/* 91 */
+#define TEGRA30_CLK_CSUS 92
+#define TEGRA30_CLK_CDEV2 93
+#define TEGRA30_CLK_CDEV1 94
+/* 95 */
+
+#define TEGRA30_CLK_CPU_G 96
+#define TEGRA30_CLK_CPU_LP 97
+#define TEGRA30_CLK_GR3D2 98
+#define TEGRA30_CLK_MSELECT 99
+#define TEGRA30_CLK_TSENSOR 100
+#define TEGRA30_CLK_I2S3 101
+#define TEGRA30_CLK_I2S4 102
+#define TEGRA30_CLK_I2C4 103
+#define TEGRA30_CLK_SBC5 104
+#define TEGRA30_CLK_SBC6 105
+#define TEGRA30_CLK_D_AUDIO 106
+#define TEGRA30_CLK_APBIF 107
+#define TEGRA30_CLK_DAM0 108
+#define TEGRA30_CLK_DAM1 109
+#define TEGRA30_CLK_DAM2 110
+#define TEGRA30_CLK_HDA2CODEC_2X 111
+#define TEGRA30_CLK_ATOMICS 112
+#define TEGRA30_CLK_AUDIO0_2X 113
+#define TEGRA30_CLK_AUDIO1_2X 114
+#define TEGRA30_CLK_AUDIO2_2X 115
+#define TEGRA30_CLK_AUDIO3_2X 116
+#define TEGRA30_CLK_AUDIO4_2X 117
+#define TEGRA30_CLK_SPDIF_2X 118
+#define TEGRA30_CLK_ACTMON 119
+#define TEGRA30_CLK_EXTERN1 120
+#define TEGRA30_CLK_EXTERN2 121
+#define TEGRA30_CLK_EXTERN3 122
+#define TEGRA30_CLK_SATA_OOB 123
+#define TEGRA30_CLK_SATA 124
+#define TEGRA30_CLK_HDA 125
+/* 126 */
+#define TEGRA30_CLK_SE 127
+
+#define TEGRA30_CLK_HDA2HDMI 128
+#define TEGRA30_CLK_SATA_COLD 129
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 */
+/* 144 */
+/* 145 */
+/* 146 */
+/* 147 */
+/* 148 */
+/* 149 */
+/* 150 */
+/* 151 */
+/* 152 */
+/* 153 */
+/* 154 */
+/* 155 */
+/* 156 */
+/* 157 */
+/* 158 */
+/* 159 */
+
+#define TEGRA30_CLK_UARTB 160
+#define TEGRA30_CLK_VFIR 161
+#define TEGRA30_CLK_SPDIF_IN 162
+#define TEGRA30_CLK_SPDIF_OUT 163
+#define TEGRA30_CLK_VI 164
+#define TEGRA30_CLK_VI_SENSOR 165
+#define TEGRA30_CLK_FUSE 166
+#define TEGRA30_CLK_FUSE_BURN 167
+#define TEGRA30_CLK_CVE 168
+#define TEGRA30_CLK_TVO 169
+#define TEGRA30_CLK_CLK_32K 170
+#define TEGRA30_CLK_CLK_M 171
+#define TEGRA30_CLK_CLK_M_DIV2 172
+#define TEGRA30_CLK_CLK_M_DIV4 173
+#define TEGRA30_CLK_PLL_REF 174
+#define TEGRA30_CLK_PLL_C 175
+#define TEGRA30_CLK_PLL_C_OUT1 176
+#define TEGRA30_CLK_PLL_M 177
+#define TEGRA30_CLK_PLL_M_OUT1 178
+#define TEGRA30_CLK_PLL_P 179
+#define TEGRA30_CLK_PLL_P_OUT1 180
+#define TEGRA30_CLK_PLL_P_OUT2 181
+#define TEGRA30_CLK_PLL_P_OUT3 182
+#define TEGRA30_CLK_PLL_P_OUT4 183
+#define TEGRA30_CLK_PLL_A 184
+#define TEGRA30_CLK_PLL_A_OUT0 185
+#define TEGRA30_CLK_PLL_D 186
+#define TEGRA30_CLK_PLL_D_OUT0 187
+#define TEGRA30_CLK_PLL_D2 188
+#define TEGRA30_CLK_PLL_D2_OUT0 189
+#define TEGRA30_CLK_PLL_U 190
+#define TEGRA30_CLK_PLL_X 191
+
+#define TEGRA30_CLK_PLL_X_OUT0 192
+#define TEGRA30_CLK_PLL_E 193
+#define TEGRA30_CLK_SPDIF_IN_SYNC 194
+#define TEGRA30_CLK_I2S0_SYNC 195
+#define TEGRA30_CLK_I2S1_SYNC 196
+#define TEGRA30_CLK_I2S2_SYNC 197
+#define TEGRA30_CLK_I2S3_SYNC 198
+#define TEGRA30_CLK_I2S4_SYNC 199
+#define TEGRA30_CLK_VIMCLK_SYNC 200
+#define TEGRA30_CLK_AUDIO0 201
+#define TEGRA30_CLK_AUDIO1 202
+#define TEGRA30_CLK_AUDIO2 203
+#define TEGRA30_CLK_AUDIO3 204
+#define TEGRA30_CLK_AUDIO4 205
+#define TEGRA30_CLK_SPDIF 206
+#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
+#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
+#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
+#define TEGRA30_CLK_SCLK 210
+#define TEGRA30_CLK_BLINK 211
+#define TEGRA30_CLK_CCLK_G 212
+#define TEGRA30_CLK_CCLK_LP 213
+#define TEGRA30_CLK_TWD 214
+#define TEGRA30_CLK_CML0 215
+#define TEGRA30_CLK_CML1 216
+#define TEGRA30_CLK_HCLK 217
+#define TEGRA30_CLK_PCLK 218
+/* 219 */
+/* 220 */
+/* 221 */
+/* 222 */
+/* 223 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA30_CLK_CLK_OUT_1_MUX 300
+#define TEGRA30_CLK_CLK_OUT_2_MUX 301
+#define TEGRA30_CLK_CLK_OUT_3_MUX 302
+#define TEGRA30_CLK_AUDIO0_MUX 303
+#define TEGRA30_CLK_AUDIO1_MUX 304
+#define TEGRA30_CLK_AUDIO2_MUX 305
+#define TEGRA30_CLK_AUDIO3_MUX 306
+#define TEGRA30_CLK_AUDIO4_MUX 307
+#define TEGRA30_CLK_SPDIF_MUX 308
+#define TEGRA30_CLK_CLK_MAX 309
+
+#endif	/* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
new file mode 100644
index 0000000..cdc4c0b
--- /dev/null
+++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Xilinx Zynq MPSoC Firmware layer
+ *
+ *  Copyright (C) 2014-2018 Xilinx, Inc.
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
+#define _DT_BINDINGS_CLK_ZYNQMP_H
+
+#define IOPLL			0
+#define RPLL			1
+#define APLL			2
+#define DPLL			3
+#define VPLL			4
+#define IOPLL_TO_FPD		5
+#define RPLL_TO_FPD		6
+#define APLL_TO_LPD		7
+#define DPLL_TO_LPD		8
+#define VPLL_TO_LPD		9
+#define ACPU			10
+#define ACPU_HALF		11
+#define DBF_FPD			12
+#define DBF_LPD			13
+#define DBG_TRACE		14
+#define DBG_TSTMP		15
+#define DP_VIDEO_REF		16
+#define DP_AUDIO_REF		17
+#define DP_STC_REF		18
+#define GDMA_REF		19
+#define DPDMA_REF		20
+#define DDR_REF			21
+#define SATA_REF		22
+#define PCIE_REF		23
+#define GPU_REF			24
+#define GPU_PP0_REF		25
+#define GPU_PP1_REF		26
+#define TOPSW_MAIN		27
+#define TOPSW_LSBUS		28
+#define GTGREF0_REF		29
+#define LPD_SWITCH		30
+#define LPD_LSBUS		31
+#define USB0_BUS_REF		32
+#define USB1_BUS_REF		33
+#define USB3_DUAL_REF		34
+#define USB0			35
+#define USB1			36
+#define CPU_R5			37
+#define CPU_R5_CORE		38
+#define CSU_SPB			39
+#define CSU_PLL			40
+#define PCAP			41
+#define IOU_SWITCH		42
+#define GEM_TSU_REF		43
+#define GEM_TSU			44
+#define GEM0_TX			45
+#define GEM1_TX			46
+#define GEM2_TX			47
+#define GEM3_TX			48
+#define GEM0_RX			49
+#define GEM1_RX			50
+#define GEM2_RX			51
+#define GEM3_RX			52
+#define QSPI_REF		53
+#define SDIO0_REF		54
+#define SDIO1_REF		55
+#define UART0_REF		56
+#define UART1_REF		57
+#define SPI0_REF		58
+#define SPI1_REF		59
+#define NAND_REF		60
+#define I2C0_REF		61
+#define I2C1_REF		62
+#define CAN0_REF		63
+#define CAN1_REF		64
+#define CAN0			65
+#define CAN1			66
+#define DLL_REF			67
+#define ADMA_REF		68
+#define TIMESTAMP_REF		69
+#define AMS_REF			70
+#define PL0_REF			71
+#define PL1_REF			72
+#define PL2_REF			73
+#define PL3_REF			74
+#define WDT			75
+#define IOPLL_INT		76
+#define IOPLL_PRE_SRC		77
+#define IOPLL_HALF		78
+#define IOPLL_INT_MUX		79
+#define IOPLL_POST_SRC		80
+#define RPLL_INT		81
+#define RPLL_PRE_SRC		82
+#define RPLL_HALF		83
+#define RPLL_INT_MUX		84
+#define RPLL_POST_SRC		85
+#define APLL_INT		86
+#define APLL_PRE_SRC		87
+#define APLL_HALF		88
+#define APLL_INT_MUX		89
+#define APLL_POST_SRC		90
+#define DPLL_INT		91
+#define DPLL_PRE_SRC		92
+#define DPLL_HALF		93
+#define DPLL_INT_MUX		94
+#define DPLL_POST_SRC		95
+#define VPLL_INT		96
+#define VPLL_PRE_SRC		97
+#define VPLL_HALF		98
+#define VPLL_INT_MUX		99
+#define VPLL_POST_SRC		100
+#define CAN0_MIO		101
+#define CAN1_MIO		102
+#define ACPU_FULL		103
+#define GEM0_REF		104
+#define GEM1_REF		105
+#define GEM2_REF		106
+#define GEM3_REF		107
+#define GEM0_REF_UNG		108
+#define GEM1_REF_UNG		109
+#define GEM2_REF_UNG		110
+#define GEM3_REF_UNG		111
+#define LPD_WDT			112
+
+#endif
diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h
new file mode 100644
index 0000000..4f7e282
--- /dev/null
+++ b/include/dt-bindings/comphy/comphy_data.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ */
+
+#ifndef _COMPHY_DATA_H_
+#define _COMPHY_DATA_H_
+
+#define PHY_SPEED_1_25G			0
+#define PHY_SPEED_1_5G			1
+#define PHY_SPEED_2_5G			2
+#define PHY_SPEED_3G			3
+#define PHY_SPEED_3_125G		4
+#define PHY_SPEED_5G			5
+#define PHY_SPEED_5_15625G		6
+#define PHY_SPEED_6G			7
+#define PHY_SPEED_6_25G			8
+#define PHY_SPEED_10_3125G		9
+#define PHY_SPEED_MAX			10
+#define PHY_SPEED_INVALID		0xff
+
+#define PHY_TYPE_UNCONNECTED		0
+#define PHY_TYPE_PEX0			1
+#define PHY_TYPE_PEX1			2
+#define PHY_TYPE_PEX2			3
+#define PHY_TYPE_PEX3			4
+#define PHY_TYPE_SATA0			5
+#define PHY_TYPE_SATA1			6
+#define PHY_TYPE_SATA2			7
+#define PHY_TYPE_SATA3			8
+#define PHY_TYPE_SGMII0			9
+#define PHY_TYPE_SGMII1			10
+#define PHY_TYPE_SGMII2			11
+#define PHY_TYPE_SGMII3			12
+#define PHY_TYPE_QSGMII			13
+#define PHY_TYPE_USB3_HOST0		14
+#define PHY_TYPE_USB3_HOST1		15
+#define PHY_TYPE_USB3_DEVICE		16
+#define PHY_TYPE_XAUI0			17
+#define PHY_TYPE_XAUI1			18
+#define PHY_TYPE_XAUI2			19
+#define PHY_TYPE_XAUI3			20
+#define PHY_TYPE_RXAUI0			21
+#define PHY_TYPE_RXAUI1			22
+#define PHY_TYPE_SFI			23
+#define PHY_TYPE_IGNORE			24
+#define PHY_TYPE_MAX			25
+#define PHY_TYPE_INVALID		0xff
+
+#define PHY_POLARITY_NO_INVERT		0
+#define PHY_POLARITY_TXD_INVERT		1
+#define PHY_POLARITY_RXD_INVERT		2
+#define PHY_POLARITY_ALL_INVERT		\
+	(PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)
+
+#define UTMI_PHY_TO_USB3_HOST0		0
+#define UTMI_PHY_TO_USB3_HOST1		1
+#define UTMI_PHY_TO_USB3_DEVICE0	2
+#define UTMI_PHY_INVALID		0xff
+
+#endif /* _COMPHY_DATA_H_ */
+
diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h
new file mode 100644
index 0000000..ab6cbba
--- /dev/null
+++ b/include/dt-bindings/dma/at91.h
@@ -0,0 +1,52 @@
+/*
+ * This header provides macros for at91 dma bindings.
+ *
+ * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __DT_BINDINGS_AT91_DMA_H__
+#define __DT_BINDINGS_AT91_DMA_H__
+
+/* ---------- HDMAC ---------- */
+
+/*
+ * Source and/or destination peripheral ID
+ */
+#define AT91_DMA_CFG_PER_ID_MASK	(0xff)
+#define AT91_DMA_CFG_PER_ID(id)		(id & AT91_DMA_CFG_PER_ID_MASK)
+
+/*
+ * FIFO configuration: it defines when a request is serviced.
+ */
+#define AT91_DMA_CFG_FIFOCFG_OFFSET	(8)
+#define AT91_DMA_CFG_FIFOCFG_MASK	(0xf << AT91_DMA_CFG_FIFOCFG_OFFSET)
+#define AT91_DMA_CFG_FIFOCFG_HALF	(0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* half FIFO (default behavior) */
+#define AT91_DMA_CFG_FIFOCFG_ALAP	(0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* largest defined AHB burst */
+#define AT91_DMA_CFG_FIFOCFG_ASAP	(0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* single AHB access */
+
+
+/* ---------- XDMAC ---------- */
+#define AT91_XDMAC_DT_MEM_IF_MASK	(0x1)
+#define AT91_XDMAC_DT_MEM_IF_OFFSET	(13)
+#define AT91_XDMAC_DT_MEM_IF(mem_if)	(((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \
+					<< AT91_XDMAC_DT_MEM_IF_OFFSET)
+#define AT91_XDMAC_DT_GET_MEM_IF(cfg)	(((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
+					& AT91_XDMAC_DT_MEM_IF_MASK)
+
+#define AT91_XDMAC_DT_PER_IF_MASK	(0x1)
+#define AT91_XDMAC_DT_PER_IF_OFFSET	(14)
+#define AT91_XDMAC_DT_PER_IF(per_if)	(((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \
+					<< AT91_XDMAC_DT_PER_IF_OFFSET)
+#define AT91_XDMAC_DT_GET_PER_IF(cfg)	(((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
+					& AT91_XDMAC_DT_PER_IF_MASK)
+
+#define AT91_XDMAC_DT_PERID_MASK	(0x7f)
+#define AT91_XDMAC_DT_PERID_OFFSET	(24)
+#define AT91_XDMAC_DT_PERID(perid)	(((perid) & AT91_XDMAC_DT_PERID_MASK) \
+					<< AT91_XDMAC_DT_PERID_OFFSET)
+#define AT91_XDMAC_DT_GET_PERID(cfg)	(((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
+					& AT91_XDMAC_DT_PERID_MASK)
+
+#endif /* __DT_BINDINGS_AT91_DMA_H__ */
diff --git a/include/dt-bindings/dma/bcm6318-dma.h b/include/dt-bindings/dma/bcm6318-dma.h
new file mode 100644
index 0000000..ad7c5ac
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6318-dma.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+ */
+
+#ifndef __DT_BINDINGS_DMA_BCM6318_H
+#define __DT_BINDINGS_DMA_BCM6318_H
+
+#define BCM6318_DMA_ENETSW_RX	0
+#define BCM6318_DMA_ENETSW_TX	1
+
+#endif /* __DT_BINDINGS_DMA_BCM6318_H */
diff --git a/include/dt-bindings/dma/bcm63268-dma.h b/include/dt-bindings/dma/bcm63268-dma.h
new file mode 100644
index 0000000..7d02711
--- /dev/null
+++ b/include/dt-bindings/dma/bcm63268-dma.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+ */
+
+#ifndef __DT_BINDINGS_DMA_BCM63268_H
+#define __DT_BINDINGS_DMA_BCM63268_H
+
+#define BCM63268_DMA_ENETSW_RX	0
+#define BCM63268_DMA_ENETSW_TX	1
+
+#endif /* __DT_BINDINGS_DMA_BCM63268_H */
diff --git a/include/dt-bindings/dma/bcm6328-dma.h b/include/dt-bindings/dma/bcm6328-dma.h
new file mode 100644
index 0000000..7494df2
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6328-dma.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+ */
+
+#ifndef __DT_BINDINGS_DMA_BCM6328_H
+#define __DT_BINDINGS_DMA_BCM6328_H
+
+#define BCM6328_DMA_ENETSW_RX	0
+#define BCM6328_DMA_ENETSW_TX	1
+
+#endif /* __DT_BINDINGS_DMA_BCM6328_H */
diff --git a/include/dt-bindings/dma/bcm6338-dma.h b/include/dt-bindings/dma/bcm6338-dma.h
new file mode 100644
index 0000000..f2e0b20
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6338-dma.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+ */
+
+#ifndef __DT_BINDINGS_DMA_BCM6338_H
+#define __DT_BINDINGS_DMA_BCM6338_H
+
+#define BCM6338_DMA_ENET_RX	0
+#define BCM6338_DMA_ENET_TX	1
+
+#endif /* __DT_BINDINGS_DMA_BCM6338_H */
diff --git a/include/dt-bindings/dma/bcm6348-dma.h b/include/dt-bindings/dma/bcm6348-dma.h
new file mode 100644
index 0000000..36c2ffd
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6348-dma.h
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+ */
+
+#ifndef __DT_BINDINGS_DMA_BCM6348_H
+#define __DT_BINDINGS_DMA_BCM6348_H
+
+#define BCM6348_DMA_ENET0_RX	0
+#define BCM6348_DMA_ENET0_TX	1
+#define BCM6348_DMA_ENET1_RX	2
+#define BCM6348_DMA_ENET1_TX	3
+
+#endif /* __DT_BINDINGS_DMA_BCM6348_H */
diff --git a/include/dt-bindings/dma/bcm6358-dma.h b/include/dt-bindings/dma/bcm6358-dma.h
new file mode 100644
index 0000000..3118b9d
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6358-dma.h
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+ */
+
+#ifndef __DT_BINDINGS_DMA_BCM6358_H
+#define __DT_BINDINGS_DMA_BCM6358_H
+
+#define BCM6358_DMA_ENET0_RX	0
+#define BCM6358_DMA_ENET0_TX	1
+#define BCM6358_DMA_ENET1_RX	2
+#define BCM6358_DMA_ENET1_TX	3
+
+#endif /* __DT_BINDINGS_DMA_BCM6358_H */
diff --git a/include/dt-bindings/dma/bcm6362-dma.h b/include/dt-bindings/dma/bcm6362-dma.h
new file mode 100644
index 0000000..1e62236
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6362-dma.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+ */
+
+#ifndef __DT_BINDINGS_DMA_BCM6362_H
+#define __DT_BINDINGS_DMA_BCM6362_H
+
+#define BCM6362_DMA_ENETSW_RX	0
+#define BCM6362_DMA_ENETSW_TX	1
+
+#endif /* __DT_BINDINGS_DMA_BCM6362_H */
diff --git a/include/dt-bindings/dma/bcm6368-dma.h b/include/dt-bindings/dma/bcm6368-dma.h
new file mode 100644
index 0000000..36c6caa
--- /dev/null
+++ b/include/dt-bindings/dma/bcm6368-dma.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+ */
+
+#ifndef __DT_BINDINGS_DMA_BCM6368_H
+#define __DT_BINDINGS_DMA_BCM6368_H
+
+#define BCM6368_DMA_ENETSW_RX	0
+#define BCM6368_DMA_ENETSW_TX	1
+
+#endif /* __DT_BINDINGS_DMA_BCM6368_H */
diff --git a/include/dt-bindings/dma/k3-udma.h b/include/dt-bindings/dma/k3-udma.h
new file mode 100644
index 0000000..670e123
--- /dev/null
+++ b/include/dt-bindings/dma/k3-udma.h
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ */
+
+#ifndef __DT_TI_UDMA_H
+#define __DT_TI_UDMA_H
+
+#define UDMA_TR_MODE		0
+#define UDMA_PKT_MODE		1
+
+#define UDMA_DIR_TX		0
+#define UDMA_DIR_RX		1
+
+#define PSIL_STATIC_TR_NONE	0
+#define PSIL_STATIC_TR_XY	1
+#define PSIL_STATIC_TR_MCAN	2
+
+#define UDMA_PDMA_TR_XY(id)				\
+	ti,psil-config##id {				\
+		linux,udma-mode = <UDMA_TR_MODE>;	\
+		statictr-type = <PSIL_STATIC_TR_XY>;	\
+	}
+
+#define UDMA_PDMA_PKT_XY(id)				\
+	ti,psil-config##id {				\
+		linux,udma-mode = <UDMA_PKT_MODE>;	\
+		statictr-type = <PSIL_STATIC_TR_XY>;	\
+	}
+
+#endif /* __DT_TI_UDMA_H */
diff --git a/include/dt-bindings/dma/sun4i-a10.h b/include/dt-bindings/dma/sun4i-a10.h
new file mode 100644
index 0000000..8caba9e
--- /dev/null
+++ b/include/dt-bindings/dma/sun4i-a10.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2014 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __DT_BINDINGS_DMA_SUN4I_A10_H_
+#define __DT_BINDINGS_DMA_SUN4I_A10_H_
+
+#define SUN4I_DMA_NORMAL	0
+#define SUN4I_DMA_DEDICATED	1
+
+#endif /* __DT_BINDINGS_DMA_SUN4I_A10_H_ */
diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h
new file mode 100644
index 0000000..2cc10ae
--- /dev/null
+++ b/include/dt-bindings/gpio/gpio.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_GPIO_H
+#define _DT_BINDINGS_GPIO_GPIO_H
+
+/* Bit 0 express polarity */
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+/* Bit 1 express single-endedness */
+#define GPIO_PUSH_PULL 0
+#define GPIO_SINGLE_ENDED 2
+
+/* Bit 2 express Open drain or open source */
+#define GPIO_LINE_OPEN_SOURCE 0
+#define GPIO_LINE_OPEN_DRAIN 4
+
+/*
+ * Open Drain/Collector is the combination of single-ended open drain interface.
+ * Open Source/Emitter is the combination of single-ended open source interface.
+ */
+#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
+#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
+
+/* Bit 3 express GPIO suspend/resume and reset persistence */
+#define GPIO_PERSISTENT 0
+#define GPIO_TRANSITORY 8
+
+#endif
diff --git a/include/dt-bindings/gpio/meson-axg-gpio.h b/include/dt-bindings/gpio/meson-axg-gpio.h
new file mode 100644
index 0000000..25bb1ff
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-axg-gpio.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen <xingyu.chen@amlogic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_MESON_AXG_GPIO_H
+#define _DT_BINDINGS_MESON_AXG_GPIO_H
+
+/* First GPIO chip */
+#define GPIOAO_0	0
+#define GPIOAO_1	1
+#define GPIOAO_2	2
+#define GPIOAO_3	3
+#define GPIOAO_4	4
+#define GPIOAO_5	5
+#define GPIOAO_6	6
+#define GPIOAO_7	7
+#define GPIOAO_8	8
+#define GPIOAO_9	9
+#define GPIOAO_10	10
+#define GPIOAO_11	11
+#define GPIOAO_12	12
+#define GPIOAO_13	13
+#define GPIO_TEST_N 14
+
+/* Second GPIO chip */
+#define GPIOZ_0		0
+#define GPIOZ_1		1
+#define GPIOZ_2		2
+#define GPIOZ_3		3
+#define GPIOZ_4		4
+#define GPIOZ_5		5
+#define GPIOZ_6		6
+#define GPIOZ_7		7
+#define GPIOZ_8		8
+#define GPIOZ_9		9
+#define GPIOZ_10	10
+#define BOOT_0		11
+#define BOOT_1		12
+#define BOOT_2		13
+#define BOOT_3		14
+#define BOOT_4		15
+#define BOOT_5		16
+#define BOOT_6		17
+#define BOOT_7		18
+#define BOOT_8		19
+#define BOOT_9		20
+#define BOOT_10		21
+#define BOOT_11		22
+#define BOOT_12		23
+#define BOOT_13		24
+#define BOOT_14		25
+#define GPIOA_0	    26
+#define GPIOA_1		27
+#define GPIOA_2		28
+#define GPIOA_3		29
+#define GPIOA_4		30
+#define GPIOA_5		31
+#define GPIOA_6		32
+#define GPIOA_7		33
+#define GPIOA_8		34
+#define GPIOA_9		35
+#define GPIOA_10	36
+#define GPIOA_11	37
+#define GPIOA_12	38
+#define GPIOA_13	39
+#define GPIOA_14	40
+#define GPIOA_15	41
+#define GPIOA_16	42
+#define GPIOA_17	43
+#define GPIOA_18	44
+#define GPIOA_19	45
+#define GPIOA_20	46
+#define GPIOX_0		47
+#define GPIOX_1		48
+#define GPIOX_2		49
+#define GPIOX_3		50
+#define GPIOX_4		51
+#define GPIOX_5		52
+#define GPIOX_6		53
+#define GPIOX_7		54
+#define GPIOX_8		55
+#define GPIOX_9		56
+#define GPIOX_10	57
+#define GPIOX_11	58
+#define GPIOX_12	59
+#define GPIOX_13	60
+#define GPIOX_14	61
+#define GPIOX_15	62
+#define GPIOX_16	63
+#define GPIOX_17	64
+#define GPIOX_18	65
+#define GPIOX_19	66
+#define GPIOX_20	67
+#define GPIOX_21	68
+#define GPIOX_22	69
+#define GPIOY_0		70
+#define GPIOY_1		71
+#define GPIOY_2		72
+#define GPIOY_3		73
+#define GPIOY_4		74
+#define GPIOY_5		75
+#define GPIOY_6		76
+#define GPIOY_7		77
+#define GPIOY_8		78
+#define GPIOY_9		79
+#define GPIOY_10	80
+#define GPIOY_11	81
+#define GPIOY_12	82
+#define GPIOY_13	83
+#define GPIOY_14	84
+#define GPIOY_15	85
+
+#endif /* _DT_BINDINGS_MESON_AXG_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h
new file mode 100644
index 0000000..f7bd693
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-g12a-gpio.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen <xingyu.chen@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
+#define _DT_BINDINGS_MESON_G12A_GPIO_H
+
+/* First GPIO chip */
+#define GPIOAO_0	0
+#define GPIOAO_1	1
+#define GPIOAO_2	2
+#define GPIOAO_3	3
+#define GPIOAO_4	4
+#define GPIOAO_5	5
+#define GPIOAO_6	6
+#define GPIOAO_7	7
+#define GPIOAO_8	8
+#define GPIOAO_9	9
+#define GPIOAO_10	10
+#define GPIOAO_11	11
+#define GPIOE_0		12
+#define GPIOE_1		13
+#define GPIOE_2		14
+
+/* Second GPIO chip */
+#define GPIOZ_0		0
+#define GPIOZ_1		1
+#define GPIOZ_2		2
+#define GPIOZ_3		3
+#define GPIOZ_4		4
+#define GPIOZ_5		5
+#define GPIOZ_6		6
+#define GPIOZ_7		7
+#define GPIOZ_8		8
+#define GPIOZ_9		9
+#define GPIOZ_10	10
+#define GPIOZ_11	11
+#define GPIOZ_12	12
+#define GPIOZ_13	13
+#define GPIOZ_14	14
+#define GPIOZ_15	15
+#define GPIOH_0		16
+#define GPIOH_1		17
+#define GPIOH_2		18
+#define GPIOH_3		19
+#define GPIOH_4		20
+#define GPIOH_5		21
+#define GPIOH_6		22
+#define GPIOH_7		23
+#define GPIOH_8		24
+#define BOOT_0		25
+#define BOOT_1		26
+#define BOOT_2		27
+#define BOOT_3		28
+#define BOOT_4		29
+#define BOOT_5		30
+#define BOOT_6		31
+#define BOOT_7		32
+#define BOOT_8		33
+#define BOOT_9		34
+#define BOOT_10		35
+#define BOOT_11		36
+#define BOOT_12		37
+#define BOOT_13		38
+#define BOOT_14		39
+#define BOOT_15		40
+#define GPIOC_0		41
+#define GPIOC_1		42
+#define GPIOC_2		43
+#define GPIOC_3		44
+#define GPIOC_4		45
+#define GPIOC_5		46
+#define GPIOC_6		47
+#define GPIOC_7		48
+#define GPIOA_0		49
+#define GPIOA_1		50
+#define GPIOA_2		51
+#define GPIOA_3		52
+#define GPIOA_4		53
+#define GPIOA_5		54
+#define GPIOA_6		55
+#define GPIOA_7		56
+#define GPIOA_8		57
+#define GPIOA_9		58
+#define GPIOA_10	59
+#define GPIOA_11	60
+#define GPIOA_12	61
+#define GPIOA_13	62
+#define GPIOA_14	63
+#define GPIOA_15	64
+#define GPIOX_0		65
+#define GPIOX_1		66
+#define GPIOX_2		67
+#define GPIOX_3		68
+#define GPIOX_4		69
+#define GPIOX_5		70
+#define GPIOX_6		71
+#define GPIOX_7		72
+#define GPIOX_8		73
+#define GPIOX_9		74
+#define GPIOX_10	75
+#define GPIOX_11	76
+#define GPIOX_12	77
+#define GPIOX_13	78
+#define GPIOX_14	79
+#define GPIOX_15	80
+#define GPIOX_16	81
+#define GPIOX_17	82
+#define GPIOX_18	83
+#define GPIOX_19	84
+
+#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h
new file mode 100644
index 0000000..43a68a1
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-gxbb-gpio.h
@@ -0,0 +1,154 @@
+/*
+ * GPIO definitions for Amlogic Meson GXBB SoCs
+ *
+ * Copyright (C) 2016 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_MESON_GXBB_GPIO_H
+#define _DT_BINDINGS_MESON_GXBB_GPIO_H
+
+#define	GPIOAO_0	0
+#define	GPIOAO_1	1
+#define	GPIOAO_2	2
+#define	GPIOAO_3	3
+#define	GPIOAO_4	4
+#define	GPIOAO_5	5
+#define	GPIOAO_6	6
+#define	GPIOAO_7	7
+#define	GPIOAO_8	8
+#define	GPIOAO_9	9
+#define	GPIOAO_10	10
+#define	GPIOAO_11	11
+#define	GPIOAO_12	12
+#define	GPIOAO_13	13
+#define	GPIO_TEST_N	14
+
+#define	GPIOZ_0		0
+#define	GPIOZ_1		1
+#define	GPIOZ_2		2
+#define	GPIOZ_3		3
+#define	GPIOZ_4		4
+#define	GPIOZ_5		5
+#define	GPIOZ_6		6
+#define	GPIOZ_7		7
+#define	GPIOZ_8		8
+#define	GPIOZ_9		9
+#define	GPIOZ_10	10
+#define	GPIOZ_11	11
+#define	GPIOZ_12	12
+#define	GPIOZ_13	13
+#define	GPIOZ_14	14
+#define	GPIOZ_15	15
+#define	GPIOH_0		16
+#define	GPIOH_1		17
+#define	GPIOH_2		18
+#define	GPIOH_3		19
+#define	BOOT_0		20
+#define	BOOT_1		21
+#define	BOOT_2		22
+#define	BOOT_3		23
+#define	BOOT_4		24
+#define	BOOT_5		25
+#define	BOOT_6		26
+#define	BOOT_7		27
+#define	BOOT_8		28
+#define	BOOT_9		29
+#define	BOOT_10		30
+#define	BOOT_11		31
+#define	BOOT_12		32
+#define	BOOT_13		33
+#define	BOOT_14		34
+#define	BOOT_15		35
+#define	BOOT_16		36
+#define	BOOT_17		37
+#define	CARD_0		38
+#define	CARD_1		39
+#define	CARD_2		40
+#define	CARD_3		41
+#define	CARD_4		42
+#define	CARD_5		43
+#define	CARD_6		44
+#define	GPIODV_0	45
+#define	GPIODV_1	46
+#define	GPIODV_2	47
+#define	GPIODV_3	48
+#define	GPIODV_4	49
+#define	GPIODV_5	50
+#define	GPIODV_6	51
+#define	GPIODV_7	52
+#define	GPIODV_8	53
+#define	GPIODV_9	54
+#define	GPIODV_10	55
+#define	GPIODV_11	56
+#define	GPIODV_12	57
+#define	GPIODV_13	58
+#define	GPIODV_14	59
+#define	GPIODV_15	60
+#define	GPIODV_16	61
+#define	GPIODV_17	62
+#define	GPIODV_18	63
+#define	GPIODV_19	64
+#define	GPIODV_20	65
+#define	GPIODV_21	66
+#define	GPIODV_22	67
+#define	GPIODV_23	68
+#define	GPIODV_24	69
+#define	GPIODV_25	70
+#define	GPIODV_26	71
+#define	GPIODV_27	72
+#define	GPIODV_28	73
+#define	GPIODV_29	74
+#define	GPIOY_0		75
+#define	GPIOY_1		76
+#define	GPIOY_2		77
+#define	GPIOY_3		78
+#define	GPIOY_4		79
+#define	GPIOY_5		80
+#define	GPIOY_6		81
+#define	GPIOY_7		82
+#define	GPIOY_8		83
+#define	GPIOY_9		84
+#define	GPIOY_10	85
+#define	GPIOY_11	86
+#define	GPIOY_12	87
+#define	GPIOY_13	88
+#define	GPIOY_14	89
+#define	GPIOY_15	90
+#define	GPIOY_16	91
+#define	GPIOX_0		92
+#define	GPIOX_1		93
+#define	GPIOX_2		94
+#define	GPIOX_3		95
+#define	GPIOX_4		96
+#define	GPIOX_5		97
+#define	GPIOX_6		98
+#define	GPIOX_7		99
+#define	GPIOX_8		100
+#define	GPIOX_9		101
+#define	GPIOX_10	102
+#define	GPIOX_11	103
+#define	GPIOX_12	104
+#define	GPIOX_13	105
+#define	GPIOX_14	106
+#define	GPIOX_15	107
+#define	GPIOX_16	108
+#define	GPIOX_17	109
+#define	GPIOX_18	110
+#define	GPIOX_19	111
+#define	GPIOX_20	112
+#define	GPIOX_21	113
+#define	GPIOX_22	114
+#define	GPIOCLK_0	115
+#define	GPIOCLK_1	116
+#define	GPIOCLK_2	117
+#define	GPIOCLK_3	118
+
+#endif
diff --git a/include/dt-bindings/gpio/meson-gxl-gpio.h b/include/dt-bindings/gpio/meson-gxl-gpio.h
new file mode 100644
index 0000000..01f2a2a
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-gxl-gpio.h
@@ -0,0 +1,131 @@
+/*
+ * GPIO definitions for Amlogic Meson GXL SoCs
+ *
+ * Copyright (C) 2016 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_MESON_GXL_GPIO_H
+#define _DT_BINDINGS_MESON_GXL_GPIO_H
+
+#define	GPIOAO_0	0
+#define	GPIOAO_1	1
+#define	GPIOAO_2	2
+#define	GPIOAO_3	3
+#define	GPIOAO_4	4
+#define	GPIOAO_5	5
+#define	GPIOAO_6	6
+#define	GPIOAO_7	7
+#define	GPIOAO_8	8
+#define	GPIOAO_9	9
+#define	GPIO_TEST_N	10
+
+#define	GPIOZ_0		0
+#define	GPIOZ_1		1
+#define	GPIOZ_2		2
+#define	GPIOZ_3		3
+#define	GPIOZ_4		4
+#define	GPIOZ_5		5
+#define	GPIOZ_6		6
+#define	GPIOZ_7		7
+#define	GPIOZ_8		8
+#define	GPIOZ_9		9
+#define	GPIOZ_10	10
+#define	GPIOZ_11	11
+#define	GPIOZ_12	12
+#define	GPIOZ_13	13
+#define	GPIOZ_14	14
+#define	GPIOZ_15	15
+#define	GPIOH_0		16
+#define	GPIOH_1		17
+#define	GPIOH_2		18
+#define	GPIOH_3		19
+#define	GPIOH_4		20
+#define	GPIOH_5		21
+#define	GPIOH_6		22
+#define	GPIOH_7		23
+#define	GPIOH_8		24
+#define	GPIOH_9		25
+#define	BOOT_0		26
+#define	BOOT_1		27
+#define	BOOT_2		28
+#define	BOOT_3		29
+#define	BOOT_4		30
+#define	BOOT_5		31
+#define	BOOT_6		32
+#define	BOOT_7		33
+#define	BOOT_8		34
+#define	BOOT_9		35
+#define	BOOT_10		36
+#define	BOOT_11		37
+#define	BOOT_12		38
+#define	BOOT_13		39
+#define	BOOT_14		40
+#define	BOOT_15		41
+#define	CARD_0		42
+#define	CARD_1		43
+#define	CARD_2		44
+#define	CARD_3		45
+#define	CARD_4		46
+#define	CARD_5		47
+#define	CARD_6		48
+#define	GPIODV_0	49
+#define	GPIODV_1	50
+#define	GPIODV_2	51
+#define	GPIODV_3	52
+#define	GPIODV_4	53
+#define	GPIODV_5	54
+#define	GPIODV_6	55
+#define	GPIODV_7	56
+#define	GPIODV_8	57
+#define	GPIODV_9	58
+#define	GPIODV_10	59
+#define	GPIODV_11	60
+#define	GPIODV_12	61
+#define	GPIODV_13	62
+#define	GPIODV_14	63
+#define	GPIODV_15	64
+#define	GPIODV_16	65
+#define	GPIODV_17	66
+#define	GPIODV_18	67
+#define	GPIODV_19	68
+#define	GPIODV_20	69
+#define	GPIODV_21	70
+#define	GPIODV_22	71
+#define	GPIODV_23	72
+#define	GPIODV_24	73
+#define	GPIODV_25	74
+#define	GPIODV_26	75
+#define	GPIODV_27	76
+#define	GPIODV_28	77
+#define	GPIODV_29	78
+#define	GPIOX_0		79
+#define	GPIOX_1		80
+#define	GPIOX_2		81
+#define	GPIOX_3		82
+#define	GPIOX_4		83
+#define	GPIOX_5		84
+#define	GPIOX_6		85
+#define	GPIOX_7		86
+#define	GPIOX_8		87
+#define	GPIOX_9		88
+#define	GPIOX_10	89
+#define	GPIOX_11	90
+#define	GPIOX_12	91
+#define	GPIOX_13	92
+#define	GPIOX_14	93
+#define	GPIOX_15	94
+#define	GPIOX_16	95
+#define	GPIOX_17	96
+#define	GPIOX_18	97
+#define	GPIOCLK_0	98
+#define	GPIOCLK_1	99
+
+#endif
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
new file mode 100644
index 0000000..a1c09e8
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra-gpio.h
@@ -0,0 +1,51 @@
+/*
+ * This header provides constants for binding nvidia,tegra*-gpio.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define TEGRA_GPIO_PORT_A 0
+#define TEGRA_GPIO_PORT_B 1
+#define TEGRA_GPIO_PORT_C 2
+#define TEGRA_GPIO_PORT_D 3
+#define TEGRA_GPIO_PORT_E 4
+#define TEGRA_GPIO_PORT_F 5
+#define TEGRA_GPIO_PORT_G 6
+#define TEGRA_GPIO_PORT_H 7
+#define TEGRA_GPIO_PORT_I 8
+#define TEGRA_GPIO_PORT_J 9
+#define TEGRA_GPIO_PORT_K 10
+#define TEGRA_GPIO_PORT_L 11
+#define TEGRA_GPIO_PORT_M 12
+#define TEGRA_GPIO_PORT_N 13
+#define TEGRA_GPIO_PORT_O 14
+#define TEGRA_GPIO_PORT_P 15
+#define TEGRA_GPIO_PORT_Q 16
+#define TEGRA_GPIO_PORT_R 17
+#define TEGRA_GPIO_PORT_S 18
+#define TEGRA_GPIO_PORT_T 19
+#define TEGRA_GPIO_PORT_U 20
+#define TEGRA_GPIO_PORT_V 21
+#define TEGRA_GPIO_PORT_W 22
+#define TEGRA_GPIO_PORT_X 23
+#define TEGRA_GPIO_PORT_Y 24
+#define TEGRA_GPIO_PORT_Z 25
+#define TEGRA_GPIO_PORT_AA 26
+#define TEGRA_GPIO_PORT_BB 27
+#define TEGRA_GPIO_PORT_CC 28
+#define TEGRA_GPIO_PORT_DD 29
+#define TEGRA_GPIO_PORT_EE 30
+#define TEGRA_GPIO_PORT_FF 31
+
+#define TEGRA_GPIO(port, offset) \
+	((TEGRA_GPIO_PORT_##port * 8) + offset)
+
+#endif
diff --git a/include/dt-bindings/gpio/tegra186-gpio.h b/include/dt-bindings/gpio/tegra186-gpio.h
new file mode 100644
index 0000000..83a19dc
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra186-gpio.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * This header provides constants for binding nvidia,tegra186-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA_MAIN_GPIO_PORT_A 0
+#define TEGRA_MAIN_GPIO_PORT_B 1
+#define TEGRA_MAIN_GPIO_PORT_C 2
+#define TEGRA_MAIN_GPIO_PORT_D 3
+#define TEGRA_MAIN_GPIO_PORT_E 4
+#define TEGRA_MAIN_GPIO_PORT_F 5
+#define TEGRA_MAIN_GPIO_PORT_G 6
+#define TEGRA_MAIN_GPIO_PORT_H 7
+#define TEGRA_MAIN_GPIO_PORT_I 8
+#define TEGRA_MAIN_GPIO_PORT_J 9
+#define TEGRA_MAIN_GPIO_PORT_K 10
+#define TEGRA_MAIN_GPIO_PORT_L 11
+#define TEGRA_MAIN_GPIO_PORT_M 12
+#define TEGRA_MAIN_GPIO_PORT_N 13
+#define TEGRA_MAIN_GPIO_PORT_O 14
+#define TEGRA_MAIN_GPIO_PORT_P 15
+#define TEGRA_MAIN_GPIO_PORT_Q 16
+#define TEGRA_MAIN_GPIO_PORT_R 17
+#define TEGRA_MAIN_GPIO_PORT_T 18
+#define TEGRA_MAIN_GPIO_PORT_X 19
+#define TEGRA_MAIN_GPIO_PORT_Y 20
+#define TEGRA_MAIN_GPIO_PORT_BB 21
+#define TEGRA_MAIN_GPIO_PORT_CC 22
+
+#define TEGRA_MAIN_GPIO(port, offset) \
+	((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA_AON_GPIO_PORT_S 0
+#define TEGRA_AON_GPIO_PORT_U 1
+#define TEGRA_AON_GPIO_PORT_V 2
+#define TEGRA_AON_GPIO_PORT_W 3
+#define TEGRA_AON_GPIO_PORT_Z 4
+#define TEGRA_AON_GPIO_PORT_AA 5
+#define TEGRA_AON_GPIO_PORT_EE 6
+#define TEGRA_AON_GPIO_PORT_FF 7
+
+#define TEGRA_AON_GPIO(port, offset) \
+	((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
+
+#endif
diff --git a/include/dt-bindings/gpio/uniphier-gpio.h b/include/dt-bindings/gpio/uniphier-gpio.h
new file mode 100644
index 0000000..9f0ad17
--- /dev/null
+++ b/include/dt-bindings/gpio/uniphier-gpio.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2017 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ */
+
+#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H
+#define _DT_BINDINGS_GPIO_UNIPHIER_H
+
+#define UNIPHIER_GPIO_LINES_PER_BANK	8
+
+#define UNIPHIER_GPIO_IRQ_OFFSET	((UNIPHIER_GPIO_LINES_PER_BANK) * 15)
+
+#define UNIPHIER_GPIO_PORT(bank, line)	\
+			((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))
+
+#define UNIPHIER_GPIO_IRQ(n)		((UNIPHIER_GPIO_IRQ_OFFSET) + (n))
+
+#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */
diff --git a/include/dt-bindings/gpio/x86-gpio.h b/include/dt-bindings/gpio/x86-gpio.h
new file mode 100644
index 0000000..3998a8e
--- /dev/null
+++ b/include/dt-bindings/gpio/x86-gpio.h
@@ -0,0 +1,43 @@
+/*
+ * This header provides constants for binding intel,x86-pinctrl.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_X86_GPIO_H
+#define _DT_BINDINGS_GPIO_X86_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define GPIO_MODE_NATIVE	0
+#define GPIO_MODE_GPIO		1
+
+#define GPIO_MODE_FUNC0	0
+#define GPIO_MODE_FUNC1	1
+#define GPIO_MODE_FUNC2	2
+#define GPIO_MODE_FUNC3	3
+#define GPIO_MODE_FUNC4	4
+#define GPIO_MODE_FUNC5	5
+#define GPIO_MODE_FUNC6	6
+
+#define PIN_INPUT	0
+#define PIN_OUTPUT	1
+
+#define PIN_INPUT_NOPULL	0
+#define PIN_INPUT_PULLUP	1
+#define PIN_INPUT_PULLDOWN	2
+
+#define PULL_STR_2K		0
+#define PULL_STR_20K	2
+
+#define ROUTE_SCI	0
+#define ROUTE_SMI	1
+
+#define OWNER_ACPI	0
+#define OWNER_GPIO	1
+
+#define PIRQ_APIC_MASK	0
+#define PIRQ_APIC_ROUTE	1
+
+#define TRIGGER_EDGE	0
+#define TRIGGER_LEVEL	1
+
+#endif
diff --git a/include/dt-bindings/input/input.h b/include/dt-bindings/input/input.h
new file mode 100644
index 0000000..a214133
--- /dev/null
+++ b/include/dt-bindings/input/input.h
@@ -0,0 +1,17 @@
+/*
+ * This header provides constants for most input bindings.
+ *
+ * Most input bindings include key code, matrix key code format.
+ * In most cases, key code and matrix key code format uses
+ * the standard values/macro defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INPUT_INPUT_H
+#define _DT_BINDINGS_INPUT_INPUT_H
+
+#include "linux-event-codes.h"
+
+#define MATRIX_KEY(row, col, code)	\
+	((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))
+
+#endif /* _DT_BINDINGS_INPUT_INPUT_H */
diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h
new file mode 100644
index 0000000..87cf351
--- /dev/null
+++ b/include/dt-bindings/input/linux-event-codes.h
@@ -0,0 +1,805 @@
+/*
+ * Input event codes
+ *
+ *    *** IMPORTANT ***
+ * This file is not only included from C-code but also from devicetree source
+ * files. As such this file MUST only contain comments and defines.
+ *
+ * Copyright (c) 1999-2002 Vojtech Pavlik
+ * Copyright (c) 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#ifndef _UAPI_INPUT_EVENT_CODES_H
+#define _UAPI_INPUT_EVENT_CODES_H
+
+/*
+ * Device properties and quirks
+ */
+
+#define INPUT_PROP_POINTER		0x00	/* needs a pointer */
+#define INPUT_PROP_DIRECT		0x01	/* direct input devices */
+#define INPUT_PROP_BUTTONPAD		0x02	/* has button(s) under pad */
+#define INPUT_PROP_SEMI_MT		0x03	/* touch rectangle only */
+#define INPUT_PROP_TOPBUTTONPAD		0x04	/* softbuttons at top of pad */
+#define INPUT_PROP_POINTING_STICK	0x05	/* is a pointing stick */
+#define INPUT_PROP_ACCELEROMETER	0x06	/* has accelerometer */
+
+#define INPUT_PROP_MAX			0x1f
+#define INPUT_PROP_CNT			(INPUT_PROP_MAX + 1)
+
+/*
+ * Event types
+ */
+
+#define EV_SYN			0x00
+#define EV_KEY			0x01
+#define EV_REL			0x02
+#define EV_ABS			0x03
+#define EV_MSC			0x04
+#define EV_SW			0x05
+#define EV_LED			0x11
+#define EV_SND			0x12
+#define EV_REP			0x14
+#define EV_FF			0x15
+#define EV_PWR			0x16
+#define EV_FF_STATUS		0x17
+#define EV_MAX			0x1f
+#define EV_CNT			(EV_MAX+1)
+
+/*
+ * Synchronization events.
+ */
+
+#define SYN_REPORT		0
+#define SYN_CONFIG		1
+#define SYN_MT_REPORT		2
+#define SYN_DROPPED		3
+#define SYN_MAX			0xf
+#define SYN_CNT			(SYN_MAX+1)
+
+/*
+ * Keys and buttons
+ *
+ * Most of the keys/buttons are modeled after USB HUT 1.12
+ * (see http://www.usb.org/developers/hidpage).
+ * Abbreviations in the comments:
+ * AC - Application Control
+ * AL - Application Launch Button
+ * SC - System Control
+ */
+
+#define KEY_RESERVED		0
+#define KEY_ESC			1
+#define KEY_1			2
+#define KEY_2			3
+#define KEY_3			4
+#define KEY_4			5
+#define KEY_5			6
+#define KEY_6			7
+#define KEY_7			8
+#define KEY_8			9
+#define KEY_9			10
+#define KEY_0			11
+#define KEY_MINUS		12
+#define KEY_EQUAL		13
+#define KEY_BACKSPACE		14
+#define KEY_TAB			15
+#define KEY_Q			16
+#define KEY_W			17
+#define KEY_E			18
+#define KEY_R			19
+#define KEY_T			20
+#define KEY_Y			21
+#define KEY_U			22
+#define KEY_I			23
+#define KEY_O			24
+#define KEY_P			25
+#define KEY_LEFTBRACE		26
+#define KEY_RIGHTBRACE		27
+#define KEY_ENTER		28
+#define KEY_LEFTCTRL		29
+#define KEY_A			30
+#define KEY_S			31
+#define KEY_D			32
+#define KEY_F			33
+#define KEY_G			34
+#define KEY_H			35
+#define KEY_J			36
+#define KEY_K			37
+#define KEY_L			38
+#define KEY_SEMICOLON		39
+#define KEY_APOSTROPHE		40
+#define KEY_GRAVE		41
+#define KEY_LEFTSHIFT		42
+#define KEY_BACKSLASH		43
+#define KEY_Z			44
+#define KEY_X			45
+#define KEY_C			46
+#define KEY_V			47
+#define KEY_B			48
+#define KEY_N			49
+#define KEY_M			50
+#define KEY_COMMA		51
+#define KEY_DOT			52
+#define KEY_SLASH		53
+#define KEY_RIGHTSHIFT		54
+#define KEY_KPASTERISK		55
+#define KEY_LEFTALT		56
+#define KEY_SPACE		57
+#define KEY_CAPSLOCK		58
+#define KEY_F1			59
+#define KEY_F2			60
+#define KEY_F3			61
+#define KEY_F4			62
+#define KEY_F5			63
+#define KEY_F6			64
+#define KEY_F7			65
+#define KEY_F8			66
+#define KEY_F9			67
+#define KEY_F10			68
+#define KEY_NUMLOCK		69
+#define KEY_SCROLLLOCK		70
+#define KEY_KP7			71
+#define KEY_KP8			72
+#define KEY_KP9			73
+#define KEY_KPMINUS		74
+#define KEY_KP4			75
+#define KEY_KP5			76
+#define KEY_KP6			77
+#define KEY_KPPLUS		78
+#define KEY_KP1			79
+#define KEY_KP2			80
+#define KEY_KP3			81
+#define KEY_KP0			82
+#define KEY_KPDOT		83
+
+#define KEY_ZENKAKUHANKAKU	85
+#define KEY_102ND		86
+#define KEY_F11			87
+#define KEY_F12			88
+#define KEY_RO			89
+#define KEY_KATAKANA		90
+#define KEY_HIRAGANA		91
+#define KEY_HENKAN		92
+#define KEY_KATAKANAHIRAGANA	93
+#define KEY_MUHENKAN		94
+#define KEY_KPJPCOMMA		95
+#define KEY_KPENTER		96
+#define KEY_RIGHTCTRL		97
+#define KEY_KPSLASH		98
+#define KEY_SYSRQ		99
+#define KEY_RIGHTALT		100
+#define KEY_LINEFEED		101
+#define KEY_HOME		102
+#define KEY_UP			103
+#define KEY_PAGEUP		104
+#define KEY_LEFT		105
+#define KEY_RIGHT		106
+#define KEY_END			107
+#define KEY_DOWN		108
+#define KEY_PAGEDOWN		109
+#define KEY_INSERT		110
+#define KEY_DELETE		111
+#define KEY_MACRO		112
+#define KEY_MUTE		113
+#define KEY_VOLUMEDOWN		114
+#define KEY_VOLUMEUP		115
+#define KEY_POWER		116	/* SC System Power Down */
+#define KEY_KPEQUAL		117
+#define KEY_KPPLUSMINUS		118
+#define KEY_PAUSE		119
+#define KEY_SCALE		120	/* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA		121
+#define KEY_HANGEUL		122
+#define KEY_HANGUEL		KEY_HANGEUL
+#define KEY_HANJA		123
+#define KEY_YEN			124
+#define KEY_LEFTMETA		125
+#define KEY_RIGHTMETA		126
+#define KEY_COMPOSE		127
+
+#define KEY_STOP		128	/* AC Stop */
+#define KEY_AGAIN		129
+#define KEY_PROPS		130	/* AC Properties */
+#define KEY_UNDO		131	/* AC Undo */
+#define KEY_FRONT		132
+#define KEY_COPY		133	/* AC Copy */
+#define KEY_OPEN		134	/* AC Open */
+#define KEY_PASTE		135	/* AC Paste */
+#define KEY_FIND		136	/* AC Search */
+#define KEY_CUT			137	/* AC Cut */
+#define KEY_HELP		138	/* AL Integrated Help Center */
+#define KEY_MENU		139	/* Menu (show menu) */
+#define KEY_CALC		140	/* AL Calculator */
+#define KEY_SETUP		141
+#define KEY_SLEEP		142	/* SC System Sleep */
+#define KEY_WAKEUP		143	/* System Wake Up */
+#define KEY_FILE		144	/* AL Local Machine Browser */
+#define KEY_SENDFILE		145
+#define KEY_DELETEFILE		146
+#define KEY_XFER		147
+#define KEY_PROG1		148
+#define KEY_PROG2		149
+#define KEY_WWW			150	/* AL Internet Browser */
+#define KEY_MSDOS		151
+#define KEY_COFFEE		152	/* AL Terminal Lock/Screensaver */
+#define KEY_SCREENLOCK		KEY_COFFEE
+#define KEY_ROTATE_DISPLAY	153	/* Display orientation for e.g. tablets */
+#define KEY_DIRECTION		KEY_ROTATE_DISPLAY
+#define KEY_CYCLEWINDOWS	154
+#define KEY_MAIL		155
+#define KEY_BOOKMARKS		156	/* AC Bookmarks */
+#define KEY_COMPUTER		157
+#define KEY_BACK		158	/* AC Back */
+#define KEY_FORWARD		159	/* AC Forward */
+#define KEY_CLOSECD		160
+#define KEY_EJECTCD		161
+#define KEY_EJECTCLOSECD	162
+#define KEY_NEXTSONG		163
+#define KEY_PLAYPAUSE		164
+#define KEY_PREVIOUSSONG	165
+#define KEY_STOPCD		166
+#define KEY_RECORD		167
+#define KEY_REWIND		168
+#define KEY_PHONE		169	/* Media Select Telephone */
+#define KEY_ISO			170
+#define KEY_CONFIG		171	/* AL Consumer Control Configuration */
+#define KEY_HOMEPAGE		172	/* AC Home */
+#define KEY_REFRESH		173	/* AC Refresh */
+#define KEY_EXIT		174	/* AC Exit */
+#define KEY_MOVE		175
+#define KEY_EDIT		176
+#define KEY_SCROLLUP		177
+#define KEY_SCROLLDOWN		178
+#define KEY_KPLEFTPAREN		179
+#define KEY_KPRIGHTPAREN	180
+#define KEY_NEW			181	/* AC New */
+#define KEY_REDO		182	/* AC Redo/Repeat */
+
+#define KEY_F13			183
+#define KEY_F14			184
+#define KEY_F15			185
+#define KEY_F16			186
+#define KEY_F17			187
+#define KEY_F18			188
+#define KEY_F19			189
+#define KEY_F20			190
+#define KEY_F21			191
+#define KEY_F22			192
+#define KEY_F23			193
+#define KEY_F24			194
+
+#define KEY_PLAYCD		200
+#define KEY_PAUSECD		201
+#define KEY_PROG3		202
+#define KEY_PROG4		203
+#define KEY_DASHBOARD		204	/* AL Dashboard */
+#define KEY_SUSPEND		205
+#define KEY_CLOSE		206	/* AC Close */
+#define KEY_PLAY		207
+#define KEY_FASTFORWARD		208
+#define KEY_BASSBOOST		209
+#define KEY_PRINT		210	/* AC Print */
+#define KEY_HP			211
+#define KEY_CAMERA		212
+#define KEY_SOUND		213
+#define KEY_QUESTION		214
+#define KEY_EMAIL		215
+#define KEY_CHAT		216
+#define KEY_SEARCH		217
+#define KEY_CONNECT		218
+#define KEY_FINANCE		219	/* AL Checkbook/Finance */
+#define KEY_SPORT		220
+#define KEY_SHOP		221
+#define KEY_ALTERASE		222
+#define KEY_CANCEL		223	/* AC Cancel */
+#define KEY_BRIGHTNESSDOWN	224
+#define KEY_BRIGHTNESSUP	225
+#define KEY_MEDIA		226
+
+#define KEY_SWITCHVIDEOMODE	227	/* Cycle between available video
+					   outputs (Monitor/LCD/TV-out/etc) */
+#define KEY_KBDILLUMTOGGLE	228
+#define KEY_KBDILLUMDOWN	229
+#define KEY_KBDILLUMUP		230
+
+#define KEY_SEND		231	/* AC Send */
+#define KEY_REPLY		232	/* AC Reply */
+#define KEY_FORWARDMAIL		233	/* AC Forward Msg */
+#define KEY_SAVE		234	/* AC Save */
+#define KEY_DOCUMENTS		235
+
+#define KEY_BATTERY		236
+
+#define KEY_BLUETOOTH		237
+#define KEY_WLAN		238
+#define KEY_UWB			239
+
+#define KEY_UNKNOWN		240
+
+#define KEY_VIDEO_NEXT		241	/* drive next video source */
+#define KEY_VIDEO_PREV		242	/* drive previous video source */
+#define KEY_BRIGHTNESS_CYCLE	243	/* brightness up, after max is min */
+#define KEY_BRIGHTNESS_AUTO	244	/* Set Auto Brightness: manual
+					  brightness control is off,
+					  rely on ambient */
+#define KEY_BRIGHTNESS_ZERO	KEY_BRIGHTNESS_AUTO
+#define KEY_DISPLAY_OFF		245	/* display device to off state */
+
+#define KEY_WWAN		246	/* Wireless WAN (LTE, UMTS, GSM, etc.) */
+#define KEY_WIMAX		KEY_WWAN
+#define KEY_RFKILL		247	/* Key that controls all radios */
+
+#define KEY_MICMUTE		248	/* Mute / unmute the microphone */
+
+/* Code 255 is reserved for special needs of AT keyboard driver */
+
+#define BTN_MISC		0x100
+#define BTN_0			0x100
+#define BTN_1			0x101
+#define BTN_2			0x102
+#define BTN_3			0x103
+#define BTN_4			0x104
+#define BTN_5			0x105
+#define BTN_6			0x106
+#define BTN_7			0x107
+#define BTN_8			0x108
+#define BTN_9			0x109
+
+#define BTN_MOUSE		0x110
+#define BTN_LEFT		0x110
+#define BTN_RIGHT		0x111
+#define BTN_MIDDLE		0x112
+#define BTN_SIDE		0x113
+#define BTN_EXTRA		0x114
+#define BTN_FORWARD		0x115
+#define BTN_BACK		0x116
+#define BTN_TASK		0x117
+
+#define BTN_JOYSTICK		0x120
+#define BTN_TRIGGER		0x120
+#define BTN_THUMB		0x121
+#define BTN_THUMB2		0x122
+#define BTN_TOP			0x123
+#define BTN_TOP2		0x124
+#define BTN_PINKIE		0x125
+#define BTN_BASE		0x126
+#define BTN_BASE2		0x127
+#define BTN_BASE3		0x128
+#define BTN_BASE4		0x129
+#define BTN_BASE5		0x12a
+#define BTN_BASE6		0x12b
+#define BTN_DEAD		0x12f
+
+#define BTN_GAMEPAD		0x130
+#define BTN_SOUTH		0x130
+#define BTN_A			BTN_SOUTH
+#define BTN_EAST		0x131
+#define BTN_B			BTN_EAST
+#define BTN_C			0x132
+#define BTN_NORTH		0x133
+#define BTN_X			BTN_NORTH
+#define BTN_WEST		0x134
+#define BTN_Y			BTN_WEST
+#define BTN_Z			0x135
+#define BTN_TL			0x136
+#define BTN_TR			0x137
+#define BTN_TL2			0x138
+#define BTN_TR2			0x139
+#define BTN_SELECT		0x13a
+#define BTN_START		0x13b
+#define BTN_MODE		0x13c
+#define BTN_THUMBL		0x13d
+#define BTN_THUMBR		0x13e
+
+#define BTN_DIGI		0x140
+#define BTN_TOOL_PEN		0x140
+#define BTN_TOOL_RUBBER		0x141
+#define BTN_TOOL_BRUSH		0x142
+#define BTN_TOOL_PENCIL		0x143
+#define BTN_TOOL_AIRBRUSH	0x144
+#define BTN_TOOL_FINGER		0x145
+#define BTN_TOOL_MOUSE		0x146
+#define BTN_TOOL_LENS		0x147
+#define BTN_TOOL_QUINTTAP	0x148	/* Five fingers on trackpad */
+#define BTN_TOUCH		0x14a
+#define BTN_STYLUS		0x14b
+#define BTN_STYLUS2		0x14c
+#define BTN_TOOL_DOUBLETAP	0x14d
+#define BTN_TOOL_TRIPLETAP	0x14e
+#define BTN_TOOL_QUADTAP	0x14f	/* Four fingers on trackpad */
+
+#define BTN_WHEEL		0x150
+#define BTN_GEAR_DOWN		0x150
+#define BTN_GEAR_UP		0x151
+
+#define KEY_OK			0x160
+#define KEY_SELECT		0x161
+#define KEY_GOTO		0x162
+#define KEY_CLEAR		0x163
+#define KEY_POWER2		0x164
+#define KEY_OPTION		0x165
+#define KEY_INFO		0x166	/* AL OEM Features/Tips/Tutorial */
+#define KEY_TIME		0x167
+#define KEY_VENDOR		0x168
+#define KEY_ARCHIVE		0x169
+#define KEY_PROGRAM		0x16a	/* Media Select Program Guide */
+#define KEY_CHANNEL		0x16b
+#define KEY_FAVORITES		0x16c
+#define KEY_EPG			0x16d
+#define KEY_PVR			0x16e	/* Media Select Home */
+#define KEY_MHP			0x16f
+#define KEY_LANGUAGE		0x170
+#define KEY_TITLE		0x171
+#define KEY_SUBTITLE		0x172
+#define KEY_ANGLE		0x173
+#define KEY_ZOOM		0x174
+#define KEY_MODE		0x175
+#define KEY_KEYBOARD		0x176
+#define KEY_SCREEN		0x177
+#define KEY_PC			0x178	/* Media Select Computer */
+#define KEY_TV			0x179	/* Media Select TV */
+#define KEY_TV2			0x17a	/* Media Select Cable */
+#define KEY_VCR			0x17b	/* Media Select VCR */
+#define KEY_VCR2		0x17c	/* VCR Plus */
+#define KEY_SAT			0x17d	/* Media Select Satellite */
+#define KEY_SAT2		0x17e
+#define KEY_CD			0x17f	/* Media Select CD */
+#define KEY_TAPE		0x180	/* Media Select Tape */
+#define KEY_RADIO		0x181
+#define KEY_TUNER		0x182	/* Media Select Tuner */
+#define KEY_PLAYER		0x183
+#define KEY_TEXT		0x184
+#define KEY_DVD			0x185	/* Media Select DVD */
+#define KEY_AUX			0x186
+#define KEY_MP3			0x187
+#define KEY_AUDIO		0x188	/* AL Audio Browser */
+#define KEY_VIDEO		0x189	/* AL Movie Browser */
+#define KEY_DIRECTORY		0x18a
+#define KEY_LIST		0x18b
+#define KEY_MEMO		0x18c	/* Media Select Messages */
+#define KEY_CALENDAR		0x18d
+#define KEY_RED			0x18e
+#define KEY_GREEN		0x18f
+#define KEY_YELLOW		0x190
+#define KEY_BLUE		0x191
+#define KEY_CHANNELUP		0x192	/* Channel Increment */
+#define KEY_CHANNELDOWN		0x193	/* Channel Decrement */
+#define KEY_FIRST		0x194
+#define KEY_LAST		0x195	/* Recall Last */
+#define KEY_AB			0x196
+#define KEY_NEXT		0x197
+#define KEY_RESTART		0x198
+#define KEY_SLOW		0x199
+#define KEY_SHUFFLE		0x19a
+#define KEY_BREAK		0x19b
+#define KEY_PREVIOUS		0x19c
+#define KEY_DIGITS		0x19d
+#define KEY_TEEN		0x19e
+#define KEY_TWEN		0x19f
+#define KEY_VIDEOPHONE		0x1a0	/* Media Select Video Phone */
+#define KEY_GAMES		0x1a1	/* Media Select Games */
+#define KEY_ZOOMIN		0x1a2	/* AC Zoom In */
+#define KEY_ZOOMOUT		0x1a3	/* AC Zoom Out */
+#define KEY_ZOOMRESET		0x1a4	/* AC Zoom */
+#define KEY_WORDPROCESSOR	0x1a5	/* AL Word Processor */
+#define KEY_EDITOR		0x1a6	/* AL Text Editor */
+#define KEY_SPREADSHEET		0x1a7	/* AL Spreadsheet */
+#define KEY_GRAPHICSEDITOR	0x1a8	/* AL Graphics Editor */
+#define KEY_PRESENTATION	0x1a9	/* AL Presentation App */
+#define KEY_DATABASE		0x1aa	/* AL Database App */
+#define KEY_NEWS		0x1ab	/* AL Newsreader */
+#define KEY_VOICEMAIL		0x1ac	/* AL Voicemail */
+#define KEY_ADDRESSBOOK		0x1ad	/* AL Contacts/Address Book */
+#define KEY_MESSENGER		0x1ae	/* AL Instant Messaging */
+#define KEY_DISPLAYTOGGLE	0x1af	/* Turn display (LCD) on and off */
+#define KEY_BRIGHTNESS_TOGGLE	KEY_DISPLAYTOGGLE
+#define KEY_SPELLCHECK		0x1b0   /* AL Spell Check */
+#define KEY_LOGOFF		0x1b1   /* AL Logoff */
+
+#define KEY_DOLLAR		0x1b2
+#define KEY_EURO		0x1b3
+
+#define KEY_FRAMEBACK		0x1b4	/* Consumer - transport controls */
+#define KEY_FRAMEFORWARD	0x1b5
+#define KEY_CONTEXT_MENU	0x1b6	/* GenDesc - system context menu */
+#define KEY_MEDIA_REPEAT	0x1b7	/* Consumer - transport control */
+#define KEY_10CHANNELSUP	0x1b8	/* 10 channels up (10+) */
+#define KEY_10CHANNELSDOWN	0x1b9	/* 10 channels down (10-) */
+#define KEY_IMAGES		0x1ba	/* AL Image Browser */
+
+#define KEY_DEL_EOL		0x1c0
+#define KEY_DEL_EOS		0x1c1
+#define KEY_INS_LINE		0x1c2
+#define KEY_DEL_LINE		0x1c3
+
+#define KEY_FN			0x1d0
+#define KEY_FN_ESC		0x1d1
+#define KEY_FN_F1		0x1d2
+#define KEY_FN_F2		0x1d3
+#define KEY_FN_F3		0x1d4
+#define KEY_FN_F4		0x1d5
+#define KEY_FN_F5		0x1d6
+#define KEY_FN_F6		0x1d7
+#define KEY_FN_F7		0x1d8
+#define KEY_FN_F8		0x1d9
+#define KEY_FN_F9		0x1da
+#define KEY_FN_F10		0x1db
+#define KEY_FN_F11		0x1dc
+#define KEY_FN_F12		0x1dd
+#define KEY_FN_1		0x1de
+#define KEY_FN_2		0x1df
+#define KEY_FN_D		0x1e0
+#define KEY_FN_E		0x1e1
+#define KEY_FN_F		0x1e2
+#define KEY_FN_S		0x1e3
+#define KEY_FN_B		0x1e4
+
+#define KEY_BRL_DOT1		0x1f1
+#define KEY_BRL_DOT2		0x1f2
+#define KEY_BRL_DOT3		0x1f3
+#define KEY_BRL_DOT4		0x1f4
+#define KEY_BRL_DOT5		0x1f5
+#define KEY_BRL_DOT6		0x1f6
+#define KEY_BRL_DOT7		0x1f7
+#define KEY_BRL_DOT8		0x1f8
+#define KEY_BRL_DOT9		0x1f9
+#define KEY_BRL_DOT10		0x1fa
+
+#define KEY_NUMERIC_0		0x200	/* used by phones, remote controls, */
+#define KEY_NUMERIC_1		0x201	/* and other keypads */
+#define KEY_NUMERIC_2		0x202
+#define KEY_NUMERIC_3		0x203
+#define KEY_NUMERIC_4		0x204
+#define KEY_NUMERIC_5		0x205
+#define KEY_NUMERIC_6		0x206
+#define KEY_NUMERIC_7		0x207
+#define KEY_NUMERIC_8		0x208
+#define KEY_NUMERIC_9		0x209
+#define KEY_NUMERIC_STAR	0x20a
+#define KEY_NUMERIC_POUND	0x20b
+#define KEY_NUMERIC_A		0x20c	/* Phone key A - HUT Telephony 0xb9 */
+#define KEY_NUMERIC_B		0x20d
+#define KEY_NUMERIC_C		0x20e
+#define KEY_NUMERIC_D		0x20f
+
+#define KEY_CAMERA_FOCUS	0x210
+#define KEY_WPS_BUTTON		0x211	/* WiFi Protected Setup key */
+
+#define KEY_TOUCHPAD_TOGGLE	0x212	/* Request switch touchpad on or off */
+#define KEY_TOUCHPAD_ON		0x213
+#define KEY_TOUCHPAD_OFF	0x214
+
+#define KEY_CAMERA_ZOOMIN	0x215
+#define KEY_CAMERA_ZOOMOUT	0x216
+#define KEY_CAMERA_UP		0x217
+#define KEY_CAMERA_DOWN		0x218
+#define KEY_CAMERA_LEFT		0x219
+#define KEY_CAMERA_RIGHT	0x21a
+
+#define KEY_ATTENDANT_ON	0x21b
+#define KEY_ATTENDANT_OFF	0x21c
+#define KEY_ATTENDANT_TOGGLE	0x21d	/* Attendant call on or off */
+#define KEY_LIGHTS_TOGGLE	0x21e	/* Reading light on or off */
+
+#define BTN_DPAD_UP		0x220
+#define BTN_DPAD_DOWN		0x221
+#define BTN_DPAD_LEFT		0x222
+#define BTN_DPAD_RIGHT		0x223
+
+#define KEY_ALS_TOGGLE		0x230	/* Ambient light sensor */
+
+#define KEY_BUTTONCONFIG		0x240	/* AL Button Configuration */
+#define KEY_TASKMANAGER		0x241	/* AL Task/Project Manager */
+#define KEY_JOURNAL		0x242	/* AL Log/Journal/Timecard */
+#define KEY_CONTROLPANEL		0x243	/* AL Control Panel */
+#define KEY_APPSELECT		0x244	/* AL Select Task/Application */
+#define KEY_SCREENSAVER		0x245	/* AL Screen Saver */
+#define KEY_VOICECOMMAND		0x246	/* Listening Voice Command */
+
+#define KEY_BRIGHTNESS_MIN		0x250	/* Set Brightness to Minimum */
+#define KEY_BRIGHTNESS_MAX		0x251	/* Set Brightness to Maximum */
+
+#define KEY_KBDINPUTASSIST_PREV		0x260
+#define KEY_KBDINPUTASSIST_NEXT		0x261
+#define KEY_KBDINPUTASSIST_PREVGROUP		0x262
+#define KEY_KBDINPUTASSIST_NEXTGROUP		0x263
+#define KEY_KBDINPUTASSIST_ACCEPT		0x264
+#define KEY_KBDINPUTASSIST_CANCEL		0x265
+
+#define BTN_TRIGGER_HAPPY		0x2c0
+#define BTN_TRIGGER_HAPPY1		0x2c0
+#define BTN_TRIGGER_HAPPY2		0x2c1
+#define BTN_TRIGGER_HAPPY3		0x2c2
+#define BTN_TRIGGER_HAPPY4		0x2c3
+#define BTN_TRIGGER_HAPPY5		0x2c4
+#define BTN_TRIGGER_HAPPY6		0x2c5
+#define BTN_TRIGGER_HAPPY7		0x2c6
+#define BTN_TRIGGER_HAPPY8		0x2c7
+#define BTN_TRIGGER_HAPPY9		0x2c8
+#define BTN_TRIGGER_HAPPY10		0x2c9
+#define BTN_TRIGGER_HAPPY11		0x2ca
+#define BTN_TRIGGER_HAPPY12		0x2cb
+#define BTN_TRIGGER_HAPPY13		0x2cc
+#define BTN_TRIGGER_HAPPY14		0x2cd
+#define BTN_TRIGGER_HAPPY15		0x2ce
+#define BTN_TRIGGER_HAPPY16		0x2cf
+#define BTN_TRIGGER_HAPPY17		0x2d0
+#define BTN_TRIGGER_HAPPY18		0x2d1
+#define BTN_TRIGGER_HAPPY19		0x2d2
+#define BTN_TRIGGER_HAPPY20		0x2d3
+#define BTN_TRIGGER_HAPPY21		0x2d4
+#define BTN_TRIGGER_HAPPY22		0x2d5
+#define BTN_TRIGGER_HAPPY23		0x2d6
+#define BTN_TRIGGER_HAPPY24		0x2d7
+#define BTN_TRIGGER_HAPPY25		0x2d8
+#define BTN_TRIGGER_HAPPY26		0x2d9
+#define BTN_TRIGGER_HAPPY27		0x2da
+#define BTN_TRIGGER_HAPPY28		0x2db
+#define BTN_TRIGGER_HAPPY29		0x2dc
+#define BTN_TRIGGER_HAPPY30		0x2dd
+#define BTN_TRIGGER_HAPPY31		0x2de
+#define BTN_TRIGGER_HAPPY32		0x2df
+#define BTN_TRIGGER_HAPPY33		0x2e0
+#define BTN_TRIGGER_HAPPY34		0x2e1
+#define BTN_TRIGGER_HAPPY35		0x2e2
+#define BTN_TRIGGER_HAPPY36		0x2e3
+#define BTN_TRIGGER_HAPPY37		0x2e4
+#define BTN_TRIGGER_HAPPY38		0x2e5
+#define BTN_TRIGGER_HAPPY39		0x2e6
+#define BTN_TRIGGER_HAPPY40		0x2e7
+
+/* We avoid low common keys in module aliases so they don't get huge. */
+#define KEY_MIN_INTERESTING	KEY_MUTE
+#define KEY_MAX			0x2ff
+#define KEY_CNT			(KEY_MAX+1)
+
+/*
+ * Relative axes
+ */
+
+#define REL_X			0x00
+#define REL_Y			0x01
+#define REL_Z			0x02
+#define REL_RX			0x03
+#define REL_RY			0x04
+#define REL_RZ			0x05
+#define REL_HWHEEL		0x06
+#define REL_DIAL		0x07
+#define REL_WHEEL		0x08
+#define REL_MISC		0x09
+#define REL_MAX			0x0f
+#define REL_CNT			(REL_MAX+1)
+
+/*
+ * Absolute axes
+ */
+
+#define ABS_X			0x00
+#define ABS_Y			0x01
+#define ABS_Z			0x02
+#define ABS_RX			0x03
+#define ABS_RY			0x04
+#define ABS_RZ			0x05
+#define ABS_THROTTLE		0x06
+#define ABS_RUDDER		0x07
+#define ABS_WHEEL		0x08
+#define ABS_GAS			0x09
+#define ABS_BRAKE		0x0a
+#define ABS_HAT0X		0x10
+#define ABS_HAT0Y		0x11
+#define ABS_HAT1X		0x12
+#define ABS_HAT1Y		0x13
+#define ABS_HAT2X		0x14
+#define ABS_HAT2Y		0x15
+#define ABS_HAT3X		0x16
+#define ABS_HAT3Y		0x17
+#define ABS_PRESSURE		0x18
+#define ABS_DISTANCE		0x19
+#define ABS_TILT_X		0x1a
+#define ABS_TILT_Y		0x1b
+#define ABS_TOOL_WIDTH		0x1c
+
+#define ABS_VOLUME		0x20
+
+#define ABS_MISC		0x28
+
+#define ABS_MT_SLOT		0x2f	/* MT slot being modified */
+#define ABS_MT_TOUCH_MAJOR	0x30	/* Major axis of touching ellipse */
+#define ABS_MT_TOUCH_MINOR	0x31	/* Minor axis (omit if circular) */
+#define ABS_MT_WIDTH_MAJOR	0x32	/* Major axis of approaching ellipse */
+#define ABS_MT_WIDTH_MINOR	0x33	/* Minor axis (omit if circular) */
+#define ABS_MT_ORIENTATION	0x34	/* Ellipse orientation */
+#define ABS_MT_POSITION_X	0x35	/* Center X touch position */
+#define ABS_MT_POSITION_Y	0x36	/* Center Y touch position */
+#define ABS_MT_TOOL_TYPE	0x37	/* Type of touching device */
+#define ABS_MT_BLOB_ID		0x38	/* Group a set of packets as a blob */
+#define ABS_MT_TRACKING_ID	0x39	/* Unique ID of initiated contact */
+#define ABS_MT_PRESSURE		0x3a	/* Pressure on contact area */
+#define ABS_MT_DISTANCE		0x3b	/* Contact hover distance */
+#define ABS_MT_TOOL_X		0x3c	/* Center X tool position */
+#define ABS_MT_TOOL_Y		0x3d	/* Center Y tool position */
+
+
+#define ABS_MAX			0x3f
+#define ABS_CNT			(ABS_MAX+1)
+
+/*
+ * Switch events
+ */
+
+#define SW_LID			0x00  /* set = lid shut */
+#define SW_TABLET_MODE		0x01  /* set = tablet mode */
+#define SW_HEADPHONE_INSERT	0x02  /* set = inserted */
+#define SW_RFKILL_ALL		0x03  /* rfkill master switch, type "any"
+					 set = radio enabled */
+#define SW_RADIO		SW_RFKILL_ALL	/* deprecated */
+#define SW_MICROPHONE_INSERT	0x04  /* set = inserted */
+#define SW_DOCK			0x05  /* set = plugged into dock */
+#define SW_LINEOUT_INSERT	0x06  /* set = inserted */
+#define SW_JACK_PHYSICAL_INSERT 0x07  /* set = mechanical switch set */
+#define SW_VIDEOOUT_INSERT	0x08  /* set = inserted */
+#define SW_CAMERA_LENS_COVER	0x09  /* set = lens covered */
+#define SW_KEYPAD_SLIDE		0x0a  /* set = keypad slide out */
+#define SW_FRONT_PROXIMITY	0x0b  /* set = front proximity sensor active */
+#define SW_ROTATE_LOCK		0x0c  /* set = rotate locked/disabled */
+#define SW_LINEIN_INSERT	0x0d  /* set = inserted */
+#define SW_MUTE_DEVICE		0x0e  /* set = device disabled */
+#define SW_MAX			0x0f
+#define SW_CNT			(SW_MAX+1)
+
+/*
+ * Misc events
+ */
+
+#define MSC_SERIAL		0x00
+#define MSC_PULSELED		0x01
+#define MSC_GESTURE		0x02
+#define MSC_RAW			0x03
+#define MSC_SCAN		0x04
+#define MSC_TIMESTAMP		0x05
+#define MSC_MAX			0x07
+#define MSC_CNT			(MSC_MAX+1)
+
+/*
+ * LEDs
+ */
+
+#define LED_NUML		0x00
+#define LED_CAPSL		0x01
+#define LED_SCROLLL		0x02
+#define LED_COMPOSE		0x03
+#define LED_KANA		0x04
+#define LED_SLEEP		0x05
+#define LED_SUSPEND		0x06
+#define LED_MUTE		0x07
+#define LED_MISC		0x08
+#define LED_MAIL		0x09
+#define LED_CHARGING		0x0a
+#define LED_MAX			0x0f
+#define LED_CNT			(LED_MAX+1)
+
+/*
+ * Autorepeat values
+ */
+
+#define REP_DELAY		0x00
+#define REP_PERIOD		0x01
+#define REP_MAX			0x01
+#define REP_CNT			(REP_MAX+1)
+
+/*
+ * Sounds
+ */
+
+#define SND_CLICK		0x00
+#define SND_BELL		0x01
+#define SND_TONE		0x02
+#define SND_MAX			0x07
+#define SND_CNT			(SND_MAX+1)
+
+#endif
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
new file mode 100644
index 0000000..1ea1b70
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -0,0 +1,22 @@
+/*
+ * This header provides constants for the ARM GIC.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* interrupt specific cell 0 */
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+/*
+ * Interrupt specifier cell 2.
+ * The flaggs in irq.h are valid, plus those below.
+ */
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
+
+#endif
diff --git a/include/dt-bindings/interrupt-controller/irq-st.h b/include/dt-bindings/interrupt-controller/irq-st.h
new file mode 100644
index 0000000..6baa9ad
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/irq-st.h
@@ -0,0 +1,30 @@
+/*
+ *  include/linux/irqchip/irq-st.h
+ *
+ *  Copyright (C) 2014 STMicroelectronics All Rights Reserved
+ *
+ *  Author: Lee Jones <lee.jones@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H
+
+#define ST_IRQ_SYSCFG_EXT_0		0
+#define ST_IRQ_SYSCFG_EXT_1		1
+#define ST_IRQ_SYSCFG_EXT_2		2
+#define ST_IRQ_SYSCFG_CTI_0		3
+#define ST_IRQ_SYSCFG_CTI_1		4
+#define ST_IRQ_SYSCFG_PMU_0		5
+#define ST_IRQ_SYSCFG_PMU_1		6
+#define ST_IRQ_SYSCFG_pl310_L2		7
+#define ST_IRQ_SYSCFG_DISABLED		0xFFFFFFFF
+
+#define ST_IRQ_SYSCFG_EXT_1_INV		0x1
+#define ST_IRQ_SYSCFG_EXT_2_INV		0x2
+#define ST_IRQ_SYSCFG_EXT_3_INV		0x4
+
+#endif
diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h
new file mode 100644
index 0000000..33a1003
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/irq.h
@@ -0,0 +1,19 @@
+/*
+ * This header provides constants for most IRQ bindings.
+ *
+ * Most IRQ bindings include a flags cell as part of the IRQ specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+
+#define IRQ_TYPE_NONE		0
+#define IRQ_TYPE_EDGE_RISING	1
+#define IRQ_TYPE_EDGE_FALLING	2
+#define IRQ_TYPE_EDGE_BOTH	(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH	4
+#define IRQ_TYPE_LEVEL_LOW	8
+
+#endif
diff --git a/include/dt-bindings/interrupt-controller/mips-gic.h b/include/dt-bindings/interrupt-controller/mips-gic.h
new file mode 100644
index 0000000..cf35a57
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/mips-gic.h
@@ -0,0 +1,9 @@
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define GIC_SHARED 0
+#define GIC_LOCAL 1
+
+#endif
diff --git a/include/dt-bindings/interrupt-router/intel-irq.h b/include/dt-bindings/interrupt-router/intel-irq.h
new file mode 100644
index 0000000..2d1e671
--- /dev/null
+++ b/include/dt-bindings/interrupt-router/intel-irq.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _DT_BINDINGS_INTEL_IRQ_H_
+#define _DT_BINDINGS_INTEL_IRQ_H_
+
+/* PCI interrupt pin */
+#define INTA			1
+#define INTB			2
+#define INTC			3
+#define INTD			4
+
+/* PIRQs */
+#define PIRQA			0
+#define PIRQB			1
+#define PIRQC			2
+#define PIRQD			3
+#define PIRQE			4
+#define PIRQF			5
+#define PIRQG			6
+#define PIRQH			7
+
+/* PCI bdf encoding */
+#ifndef PCI_BDF
+#define PCI_BDF(b, d, f)	((b) << 16 | (d) << 11 | (f) << 8)
+#endif
+
+#endif /* _DT_BINDINGS_INTEL_IRQ_H_ */
diff --git a/include/dt-bindings/leds/leds-netxbig.h b/include/dt-bindings/leds/leds-netxbig.h
new file mode 100644
index 0000000..92658b0
--- /dev/null
+++ b/include/dt-bindings/leds/leds-netxbig.h
@@ -0,0 +1,18 @@
+/*
+ * This header provides constants for netxbig LED bindings.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _DT_BINDINGS_LEDS_NETXBIG_H
+#define _DT_BINDINGS_LEDS_NETXBIG_H
+
+#define NETXBIG_LED_OFF		0
+#define NETXBIG_LED_ON		1
+#define NETXBIG_LED_SATA	2
+#define NETXBIG_LED_TIMER1	3
+#define NETXBIG_LED_TIMER2	4
+
+#endif /* _DT_BINDINGS_LEDS_NETXBIG_H */
diff --git a/include/dt-bindings/leds/leds-ns2.h b/include/dt-bindings/leds/leds-ns2.h
new file mode 100644
index 0000000..fd61574
--- /dev/null
+++ b/include/dt-bindings/leds/leds-ns2.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _DT_BINDINGS_LEDS_NS2_H
+#define _DT_BINDINGS_LEDS_NS2_H
+
+#define NS_V2_LED_OFF	0
+#define NS_V2_LED_ON	1
+#define NS_V2_LED_SATA	2
+
+#endif
diff --git a/include/dt-bindings/leds/leds-pca9532.h b/include/dt-bindings/leds/leds-pca9532.h
new file mode 100644
index 0000000..4d917aa
--- /dev/null
+++ b/include/dt-bindings/leds/leds-pca9532.h
@@ -0,0 +1,18 @@
+/*
+ * This header provides constants for pca9532 LED bindings.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _DT_BINDINGS_LEDS_PCA9532_H
+#define _DT_BINDINGS_LEDS_PCA9532_H
+
+#define PCA9532_TYPE_NONE         0
+#define PCA9532_TYPE_LED          1
+#define PCA9532_TYPE_N2100_BEEP   2
+#define PCA9532_TYPE_GPIO         3
+#define PCA9532_LED_TIMER2        4
+
+#endif /* _DT_BINDINGS_LEDS_PCA9532_H */
diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h
new file mode 100644
index 0000000..b486432
--- /dev/null
+++ b/include/dt-bindings/mailbox/tegra186-hsp.h
@@ -0,0 +1,19 @@
+/*
+ * This header provides constants for binding nvidia,tegra186-hsp.
+ *
+ * The number with HSP_DB_MASTER prefix indicates the bit that is
+ * associated with a master ID in the doorbell registers.
+ */
+
+#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
+#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
+
+#define HSP_MBOX_TYPE_DB 0x0
+#define HSP_MBOX_TYPE_SM 0x1
+#define HSP_MBOX_TYPE_SS 0x2
+#define HSP_MBOX_TYPE_AS 0x3
+
+#define HSP_DB_MASTER_CCPLEX 17
+#define HSP_DB_MASTER_BPMP 19
+
+#endif
diff --git a/include/dt-bindings/media/omap3-isp.h b/include/dt-bindings/media/omap3-isp.h
new file mode 100644
index 0000000..4e42084
--- /dev/null
+++ b/include/dt-bindings/media/omap3-isp.h
@@ -0,0 +1,22 @@
+/*
+ * include/dt-bindings/media/omap3-isp.h
+ *
+ * Copyright (C) 2015 Sakari Ailus
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_OMAP3_ISP_H__
+#define __DT_BINDINGS_OMAP3_ISP_H__
+
+#define OMAP3ISP_PHY_TYPE_COMPLEX_IO   0
+#define OMAP3ISP_PHY_TYPE_CSIPHY       1
+
+#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */
diff --git a/include/dt-bindings/memory/mpc83xx-sdram.h b/include/dt-bindings/memory/mpc83xx-sdram.h
new file mode 100644
index 0000000..7d4ce01
--- /dev/null
+++ b/include/dt-bindings/memory/mpc83xx-sdram.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018
+ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef DT_BINDINGS_MPC83XX_SDRAM_H
+#define DT_BINDINGS_MPC83XX_SDRAM_H
+
+/* DDR Control Driver register */
+
+#define DSO_DISABLE	0
+#define DSO_ENABLE	1
+
+#define DSO_P_IMPEDANCE_HIGHEST_Z	0x0
+#define DSO_P_IMPEDANCE_MUCH_HIGHER_Z	0x8
+#define DSO_P_IMPEDANCE_HIGHER_Z	0xC
+#define DSO_P_IMPEDANCE_NOMINAL		0xE
+#define DSO_P_IMPEDANCE_LOWER_Z		0xF
+
+#define DSO_N_IMPEDANCE_HIGHEST_Z	0x0
+#define DSO_N_IMPEDANCE_MUCH_HIGHER_Z	0x8
+#define DSO_N_IMPEDANCE_HIGHER_Z	0xC
+#define DSO_N_IMPEDANCE_NOMINAL		0xE
+#define DSO_N_IMPEDANCE_LOWER_Z		0xF
+
+#define ODT_TERMINATION_75_OHM		0
+#define ODT_TERMINATION_150_OHM		1
+
+#define DDR_TYPE_DDR2_1_8_VOLT		0
+#define DDR_TYPE_DDR1_2_5_VOLT		1
+
+#define MVREF_SEL_EXTERNAL		0
+#define MVREF_SEL_INTERNAL_GVDD		1
+
+#define M_ODR_ENABLE			0
+#define M_ODR_DISABLE			1
+
+/* CS config register */
+
+#define AUTO_PRECHARGE_ENABLE	0x00800000
+#define AUTO_PRECHARGE_DISABLE	0x00000000
+
+#define ODT_RD_NEVER		0x00000000
+#define ODT_RD_ONLY_CURRENT	0x00100000
+#define ODT_RD_ONLY_OTHER_CS	0x00200000
+#define ODT_RD_ONLY_OTHER_DIMM	0x00300000
+#define ODT_RD_ALL		0x00400000
+
+#define ODT_WR_NEVER		0x00000000
+#define ODT_WR_ONLY_CURRENT	0x00010000
+#define ODT_WR_ONLY_OTHER_CS	0x00020000
+#define ODT_WR_ONLY_OTHER_DIMM	0x00030000
+#define ODT_WR_ALL		0x00040000
+
+/* DDR SDRAM Clock Control register */
+
+#define CLOCK_ADJUST_025	0x01000000
+#define CLOCK_ADJUST_05		0x02000000
+#define CLOCK_ADJUST_075	0x03000000
+#define CLOCK_ADJUST_1		0x04000000
+
+#define CASLAT_20		0x3	/* CAS latency = 2.0 */
+#define CASLAT_25		0x4	/* CAS latency = 2.5 */
+#define CASLAT_30		0x5	/* CAS latency = 3.0 */
+#define CASLAT_35		0x6	/* CAS latency = 3.5 */
+#define CASLAT_40		0x7	/* CAS latency = 4.0 */
+#define CASLAT_45		0x8	/* CAS latency = 4.5 */
+#define CASLAT_50		0x9	/* CAS latency = 5.0 */
+#define CASLAT_55		0xa	/* CAS latency = 5.5 */
+#define CASLAT_60		0xb	/* CAS latency = 6.0 */
+#define CASLAT_65		0xc	/* CAS latency = 6.5 */
+#define CASLAT_70		0xd	/* CAS latency = 7.0 */
+#define CASLAT_75		0xe	/* CAS latency = 7.5 */
+#define CASLAT_80		0xf	/* CAS latency = 8.0 */
+
+/* DDR SDRAM Timing Configuration 2 register */
+
+#define READ_LAT_PLUS_1		0x0
+#define READ_LAT		0x2
+#define READ_LAT_PLUS_1_4	0x3
+#define READ_LAT_PLUS_1_2	0x4
+#define READ_LAT_PLUS_3_4	0x5
+#define READ_LAT_PLUS_5_4	0x7
+#define READ_LAT_PLUS_3_2	0x8
+#define READ_LAT_PLUS_7_4	0x9
+#define READ_LAT_PLUS_2		0xA
+#define READ_LAT_PLUS_9_4	0xB
+#define READ_LAT_PLUS_5_2	0xC
+#define READ_LAT_PLUS_11_4	0xD
+#define READ_LAT_PLUS_3		0xE
+#define READ_LAT_PLUS_13_4	0xF
+#define READ_LAT_PLUS_7_2	0x10
+#define READ_LAT_PLUS_15_4	0x11
+#define READ_LAT_PLUS_4		0x12
+#define READ_LAT_PLUS_17_4	0x13
+#define READ_LAT_PLUS_9_2	0x14
+#define READ_LAT_PLUS_19_4	0x15
+
+#define CLOCK_DELAY_0		0x0
+#define CLOCK_DELAY_1_4		0x1
+#define CLOCK_DELAY_1_2		0x2
+#define CLOCK_DELAY_3_4		0x3
+#define CLOCK_DELAY_1		0x4
+#define CLOCK_DELAY_5_4		0x5
+#define CLOCK_DELAY_3_2		0x6
+
+/* DDR SDRAM Control Configuration */
+
+#define SREN_DISABLE	0x0
+#define SREN_ENABLE	0x1
+
+#define ECC_DISABLE	0x0
+#define ECC_ENABLE	0x1
+
+#define RD_DISABLE	0x0
+#define RD_ENABLE	0x1
+
+#define TYPE_DDR1	0x2
+#define TYPE_DDR2	0x3
+
+#define DYN_PWR_DISABLE		0x0
+#define DYN_PWR_ENABLE		0x1
+
+#define DATA_BUS_WIDTH_16	0x1
+#define DATA_BUS_WIDTH_32	0x2
+
+#define NCAP_DISABLE	0x0
+#define NCAP_ENABLE	0x1
+
+#define TIMING_1T	0x0
+#define TIMING_2T	0x1
+
+#define INTERLEAVE_NONE		0x0
+#define INTERLEAVE_1_AND_2	0x1
+
+#define PRECHARGE_MA_10		0x0
+#define PRECHARGE_MA_8		0x1
+
+#define STRENGTH_FULL		0x0
+#define STRENGTH_HALF		0x1
+
+#define INITIALIZATION_DONT_BYPASS	0x0
+#define INITIALIZATION_BYPASS		0x1
+
+/* DDR SDRAM Control Configuration 2 register */
+
+#define MODE_NORMAL	0x0
+#define MODE_REFRESH	0x1
+
+#define DLL_RESET_ENABLE	0x0
+#define DLL_RESET_DISABLE	0x1
+
+#define DQS_TRUE	0x0
+
+#define ODT_ASSERT_NEVER	0x0
+#define ODT_ASSERT_WRITES	0x1
+#define ODT_ASSERT_READS	0x2
+#define ODT_ASSERT_ALWAYS	0x3
+
+#endif
diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
new file mode 100644
index 0000000..b06ffde
--- /dev/null
+++ b/include/dt-bindings/memory/rk3368-dmc.h
@@ -0,0 +1,30 @@
+#ifndef DT_BINDINGS_RK3368_DMC_H
+#define DT_BINDINGS_RK3368_DMC_H
+
+#define DMC_MSCH_CBDR       0x0
+#define DMC_MSCH_CBRD       0x1
+#define DMC_MSCH_CRBD       0x2
+
+#define DDR3_800D 0
+#define DDR3_800E 1
+#define DDR3_1066E 2
+#define DDR3_1066F 3
+#define DDR3_1066G 4
+#define DDR3_1333F 5
+#define DDR3_1333G 6
+#define DDR3_1333H 7
+#define DDR3_1333J 8
+#define DDR3_1600G 9
+#define DDR3_1600H 10
+#define DDR3_1600J 11
+#define DDR3_1600K 12
+#define DDR3_1866J 13
+#define DDR3_1866K 14
+#define DDR3_1866L 15
+#define DDR3_1866M 16
+#define DDR3_2133K 17
+#define DDR3_2133L 18
+#define DDR3_2133M 19
+#define DDR3_2133N 20
+
+#endif
diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h
new file mode 100644
index 0000000..ab91d2b
--- /dev/null
+++ b/include/dt-bindings/memory/stm32-sdram.h
@@ -0,0 +1,46 @@
+#ifndef DT_BINDINGS_STM32_SDRAM_H
+#define DT_BINDINGS_STM32_SDRAM_H
+
+#define NO_COL_8	0x0
+#define NO_COL_9	0x1
+#define NO_COL_10	0x2
+#define NO_COL_11	0x3
+
+#define NO_ROW_11	0x0
+#define NO_ROW_12	0x1
+#define NO_ROW_13	0x2
+
+#define MWIDTH_8	0x0
+#define MWIDTH_16	0x1
+#define MWIDTH_32	0x2
+#define BANKS_2		0x0
+#define BANKS_4		0x1
+#define CAS_1		0x1
+#define CAS_2		0x2
+#define CAS_3		0x3
+#define SDCLK_DIS	0x0
+#define SDCLK_2		0x2
+#define SDCLK_3		0x3
+#define RD_BURST_EN	0x1
+#define RD_BURST_DIS	0x0
+#define RD_PIPE_DL_0	0x0
+#define RD_PIPE_DL_1	0x1
+#define RD_PIPE_DL_2	0x2
+
+/* Timing = value +1 cycles */
+#define TMRD_1		(1 - 1)
+#define TMRD_2		(2 - 1)
+#define TMRD_3		(3 - 1)
+#define TXSR_1		(1 - 1)
+#define TXSR_6		(6 - 1)
+#define TXSR_7		(7 - 1)
+#define TRAS_1		(1 - 1)
+#define TRAS_4		(4 - 1)
+#define TRC_6		(6 - 1)
+#define TWR_1		(1 - 1)
+#define TWR_2		(2 - 1)
+#define TRP_2		(2 - 1)
+#define TRCD_1		(1 - 1)
+#define TRCD_2		(2 - 1)
+
+#endif
diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h
new file mode 100644
index 0000000..8f48985
--- /dev/null
+++ b/include/dt-bindings/memory/tegra114-mc.h
@@ -0,0 +1,25 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA114_MC_H
+
+#define TEGRA_SWGROUP_PTC	0
+#define TEGRA_SWGROUP_DC	1
+#define TEGRA_SWGROUP_DCB	2
+#define TEGRA_SWGROUP_EPP	3
+#define TEGRA_SWGROUP_G2	4
+#define TEGRA_SWGROUP_AVPC	5
+#define TEGRA_SWGROUP_NV	6
+#define TEGRA_SWGROUP_HDA	7
+#define TEGRA_SWGROUP_HC	8
+#define TEGRA_SWGROUP_MSENC	9
+#define TEGRA_SWGROUP_PPCS	10
+#define TEGRA_SWGROUP_VDE	11
+#define TEGRA_SWGROUP_MPCORELP	12
+#define TEGRA_SWGROUP_MPCORE	13
+#define TEGRA_SWGROUP_VI	14
+#define TEGRA_SWGROUP_ISP	15
+#define TEGRA_SWGROUP_XUSB_HOST	16
+#define TEGRA_SWGROUP_XUSB_DEV	17
+#define TEGRA_SWGROUP_EMUCIF	18
+#define TEGRA_SWGROUP_TSEC	19
+
+#endif
diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h
new file mode 100644
index 0000000..7d8ee79
--- /dev/null
+++ b/include/dt-bindings/memory/tegra124-mc.h
@@ -0,0 +1,31 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
+
+#define TEGRA_SWGROUP_PTC	0
+#define TEGRA_SWGROUP_DC	1
+#define TEGRA_SWGROUP_DCB	2
+#define TEGRA_SWGROUP_AFI	3
+#define TEGRA_SWGROUP_AVPC	4
+#define TEGRA_SWGROUP_HDA	5
+#define TEGRA_SWGROUP_HC	6
+#define TEGRA_SWGROUP_MSENC	7
+#define TEGRA_SWGROUP_PPCS	8
+#define TEGRA_SWGROUP_SATA	9
+#define TEGRA_SWGROUP_VDE	10
+#define TEGRA_SWGROUP_MPCORELP	11
+#define TEGRA_SWGROUP_MPCORE	12
+#define TEGRA_SWGROUP_ISP2	13
+#define TEGRA_SWGROUP_XUSB_HOST	14
+#define TEGRA_SWGROUP_XUSB_DEV	15
+#define TEGRA_SWGROUP_ISP2B	16
+#define TEGRA_SWGROUP_TSEC	17
+#define TEGRA_SWGROUP_A9AVP	18
+#define TEGRA_SWGROUP_GPU	19
+#define TEGRA_SWGROUP_SDMMC1A	20
+#define TEGRA_SWGROUP_SDMMC2A	21
+#define TEGRA_SWGROUP_SDMMC3A	22
+#define TEGRA_SWGROUP_SDMMC4A	23
+#define TEGRA_SWGROUP_VIC	24
+#define TEGRA_SWGROUP_VI	25
+
+#endif
diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
new file mode 100644
index 0000000..d1731bc
--- /dev/null
+++ b/include/dt-bindings/memory/tegra210-mc.h
@@ -0,0 +1,36 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
+
+#define TEGRA_SWGROUP_PTC	0
+#define TEGRA_SWGROUP_DC	1
+#define TEGRA_SWGROUP_DCB	2
+#define TEGRA_SWGROUP_AFI	3
+#define TEGRA_SWGROUP_AVPC	4
+#define TEGRA_SWGROUP_HDA	5
+#define TEGRA_SWGROUP_HC	6
+#define TEGRA_SWGROUP_NVENC	7
+#define TEGRA_SWGROUP_PPCS	8
+#define TEGRA_SWGROUP_SATA	9
+#define TEGRA_SWGROUP_MPCORE	10
+#define TEGRA_SWGROUP_ISP2	11
+#define TEGRA_SWGROUP_XUSB_HOST	12
+#define TEGRA_SWGROUP_XUSB_DEV	13
+#define TEGRA_SWGROUP_ISP2B	14
+#define TEGRA_SWGROUP_TSEC	15
+#define TEGRA_SWGROUP_A9AVP	16
+#define TEGRA_SWGROUP_GPU	17
+#define TEGRA_SWGROUP_SDMMC1A	18
+#define TEGRA_SWGROUP_SDMMC2A	19
+#define TEGRA_SWGROUP_SDMMC3A	20
+#define TEGRA_SWGROUP_SDMMC4A	21
+#define TEGRA_SWGROUP_VIC	22
+#define TEGRA_SWGROUP_VI	23
+#define TEGRA_SWGROUP_NVDEC	24
+#define TEGRA_SWGROUP_APE	25
+#define TEGRA_SWGROUP_NVJPG	26
+#define TEGRA_SWGROUP_SE	27
+#define TEGRA_SWGROUP_AXIAP	28
+#define TEGRA_SWGROUP_ETR	29
+#define TEGRA_SWGROUP_TSECB	30
+
+#endif
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h
new file mode 100644
index 0000000..502beb0
--- /dev/null
+++ b/include/dt-bindings/memory/tegra30-mc.h
@@ -0,0 +1,24 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
+
+#define TEGRA_SWGROUP_PTC	0
+#define TEGRA_SWGROUP_DC	1
+#define TEGRA_SWGROUP_DCB	2
+#define TEGRA_SWGROUP_EPP	3
+#define TEGRA_SWGROUP_G2	4
+#define TEGRA_SWGROUP_MPE	5
+#define TEGRA_SWGROUP_VI	6
+#define TEGRA_SWGROUP_AFI	7
+#define TEGRA_SWGROUP_AVPC	8
+#define TEGRA_SWGROUP_NV	9
+#define TEGRA_SWGROUP_NV2	10
+#define TEGRA_SWGROUP_HDA	11
+#define TEGRA_SWGROUP_HC	12
+#define TEGRA_SWGROUP_PPCS	13
+#define TEGRA_SWGROUP_SATA	14
+#define TEGRA_SWGROUP_VDE	15
+#define TEGRA_SWGROUP_MPCORELP	16
+#define TEGRA_SWGROUP_MPCORE	17
+#define TEGRA_SWGROUP_ISP	18
+
+#endif
diff --git a/include/dt-bindings/mfd/st,stpmic1.h b/include/dt-bindings/mfd/st,stpmic1.h
new file mode 100644
index 0000000..b2d6c83
--- /dev/null
+++ b/include/dt-bindings/mfd/st,stpmic1.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Philippe Peurichard <philippe.peurichard@st.com>,
+ * Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
+ */
+
+#ifndef __DT_BINDINGS_STPMIC1_H__
+#define __DT_BINDINGS_STPMIC1_H__
+
+/* IRQ definitions */
+#define IT_PONKEY_F	0
+#define IT_PONKEY_R	1
+#define IT_WAKEUP_F	2
+#define IT_WAKEUP_R	3
+#define IT_VBUS_OTG_F	4
+#define IT_VBUS_OTG_R	5
+#define IT_SWOUT_F	6
+#define IT_SWOUT_R	7
+
+#define IT_CURLIM_BUCK1	8
+#define IT_CURLIM_BUCK2	9
+#define IT_CURLIM_BUCK3	10
+#define IT_CURLIM_BUCK4	11
+#define IT_OCP_OTG	12
+#define IT_OCP_SWOUT	13
+#define IT_OCP_BOOST	14
+#define IT_OVP_BOOST	15
+
+#define IT_CURLIM_LDO1	16
+#define IT_CURLIM_LDO2	17
+#define IT_CURLIM_LDO3	18
+#define IT_CURLIM_LDO4	19
+#define IT_CURLIM_LDO5	20
+#define IT_CURLIM_LDO6	21
+#define IT_SHORT_SWOTG	22
+#define IT_SHORT_SWOUT	23
+
+#define IT_TWARN_F	24
+#define IT_TWARN_R	25
+#define IT_VINLOW_F	26
+#define IT_VINLOW_R	27
+#define IT_SWIN_F	30
+#define IT_SWIN_R	31
+
+#endif /* __DT_BINDINGS_STPMIC1_H__ */
diff --git a/include/dt-bindings/mfd/st-lpc.h b/include/dt-bindings/mfd/st-lpc.h
new file mode 100644
index 0000000..d05894a
--- /dev/null
+++ b/include/dt-bindings/mfd/st-lpc.h
@@ -0,0 +1,16 @@
+/*
+ * This header provides shared DT/Driver defines for ST's LPC device
+ *
+ * Copyright (C) 2014 STMicroelectronics -- All Rights Reserved
+ *
+ * Author: Lee Jones <lee.jones@linaro.org> for STMicroelectronics
+ */
+
+#ifndef __DT_BINDINGS_ST_LPC_H__
+#define __DT_BINDINGS_ST_LPC_H__
+
+#define ST_LPC_MODE_RTC		0
+#define ST_LPC_MODE_WDT		1
+#define ST_LPC_MODE_CLKSRC	2
+
+#endif /* __DT_BINDINGS_ST_LPC_H__ */
diff --git a/include/dt-bindings/mfd/stm32f4-rcc.h b/include/dt-bindings/mfd/stm32f4-rcc.h
new file mode 100644
index 0000000..36448a5
--- /dev/null
+++ b/include/dt-bindings/mfd/stm32f4-rcc.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for the STM32F4 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32F4_RCC_H
+#define _DT_BINDINGS_MFD_STM32F4_RCC_H
+
+/* AHB1 */
+#define STM32F4_RCC_AHB1_GPIOA	0
+#define STM32F4_RCC_AHB1_GPIOB	1
+#define STM32F4_RCC_AHB1_GPIOC	2
+#define STM32F4_RCC_AHB1_GPIOD	3
+#define STM32F4_RCC_AHB1_GPIOE	4
+#define STM32F4_RCC_AHB1_GPIOF	5
+#define STM32F4_RCC_AHB1_GPIOG	6
+#define STM32F4_RCC_AHB1_GPIOH	7
+#define STM32F4_RCC_AHB1_GPIOI	8
+#define STM32F4_RCC_AHB1_GPIOJ	9
+#define STM32F4_RCC_AHB1_GPIOK	10
+#define STM32F4_RCC_AHB1_CRC	12
+#define STM32F4_RCC_AHB1_BKPSRAM	18
+#define STM32F4_RCC_AHB1_CCMDATARAM	20
+#define STM32F4_RCC_AHB1_DMA1	21
+#define STM32F4_RCC_AHB1_DMA2	22
+#define STM32F4_RCC_AHB1_DMA2D	23
+#define STM32F4_RCC_AHB1_ETHMAC	25
+#define STM32F4_RCC_AHB1_ETHMACTX	26
+#define STM32F4_RCC_AHB1_ETHMACRX	27
+#define STM32F4_RCC_AHB1_ETHMACPTP	28
+#define STM32F4_RCC_AHB1_OTGHS		29
+#define STM32F4_RCC_AHB1_OTGHSULPI	30
+
+#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
+#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
+
+/* AHB2 */
+#define STM32F4_RCC_AHB2_DCMI	0
+#define STM32F4_RCC_AHB2_CRYP	4
+#define STM32F4_RCC_AHB2_HASH	5
+#define STM32F4_RCC_AHB2_RNG	6
+#define STM32F4_RCC_AHB2_OTGFS	7
+
+#define STM32F4_AHB2_RESET(bit)	(STM32F4_RCC_AHB2_##bit + (0x14 * 8))
+#define STM32F4_AHB2_CLOCK(bit)	(STM32F4_RCC_AHB2_##bit + 0x20)
+
+/* AHB3 */
+#define STM32F4_RCC_AHB3_FMC	0
+#define STM32F4_RCC_AHB3_QSPI	1
+
+#define STM32F4_AHB3_RESET(bit)	(STM32F4_RCC_AHB3_##bit + (0x18 * 8))
+#define STM32F4_AHB3_CLOCK(bit)	(STM32F4_RCC_AHB3_##bit + 0x40)
+
+/* APB1 */
+#define STM32F4_RCC_APB1_TIM2	0
+#define STM32F4_RCC_APB1_TIM3	1
+#define STM32F4_RCC_APB1_TIM4	2
+#define STM32F4_RCC_APB1_TIM5	3
+#define STM32F4_RCC_APB1_TIM6	4
+#define STM32F4_RCC_APB1_TIM7	5
+#define STM32F4_RCC_APB1_TIM12	6
+#define STM32F4_RCC_APB1_TIM13	7
+#define STM32F4_RCC_APB1_TIM14	8
+#define STM32F4_RCC_APB1_WWDG	11
+#define STM32F4_RCC_APB1_SPI2	14
+#define STM32F4_RCC_APB1_SPI3	15
+#define STM32F4_RCC_APB1_UART2	17
+#define STM32F4_RCC_APB1_UART3	18
+#define STM32F4_RCC_APB1_UART4	19
+#define STM32F4_RCC_APB1_UART5	20
+#define STM32F4_RCC_APB1_I2C1	21
+#define STM32F4_RCC_APB1_I2C2	22
+#define STM32F4_RCC_APB1_I2C3	23
+#define STM32F4_RCC_APB1_CAN1	25
+#define STM32F4_RCC_APB1_CAN2	26
+#define STM32F4_RCC_APB1_PWR	28
+#define STM32F4_RCC_APB1_DAC	29
+#define STM32F4_RCC_APB1_UART7	30
+#define STM32F4_RCC_APB1_UART8	31
+
+#define STM32F4_APB1_RESET(bit)	(STM32F4_RCC_APB1_##bit + (0x20 * 8))
+#define STM32F4_APB1_CLOCK(bit)	(STM32F4_RCC_APB1_##bit + 0x80)
+
+/* APB2 */
+#define STM32F4_RCC_APB2_TIM1	0
+#define STM32F4_RCC_APB2_TIM8	1
+#define STM32F4_RCC_APB2_USART1	4
+#define STM32F4_RCC_APB2_USART6	5
+#define STM32F4_RCC_APB2_ADC1	8
+#define STM32F4_RCC_APB2_ADC2	9
+#define STM32F4_RCC_APB2_ADC3	10
+#define STM32F4_RCC_APB2_SDIO	11
+#define STM32F4_RCC_APB2_SPI1	12
+#define STM32F4_RCC_APB2_SPI4	13
+#define STM32F4_RCC_APB2_SYSCFG	14
+#define STM32F4_RCC_APB2_TIM9	16
+#define STM32F4_RCC_APB2_TIM10	17
+#define STM32F4_RCC_APB2_TIM11	18
+#define STM32F4_RCC_APB2_SPI5	20
+#define STM32F4_RCC_APB2_SPI6	21
+#define STM32F4_RCC_APB2_SAI1	22
+#define STM32F4_RCC_APB2_LTDC	26
+#define STM32F4_RCC_APB2_DSI	27
+
+#define STM32F4_APB2_RESET(bit)	(STM32F4_RCC_APB2_##bit + (0x24 * 8))
+#define STM32F4_APB2_CLOCK(bit)	(STM32F4_RCC_APB2_##bit + 0xA0)
+
+#endif /* _DT_BINDINGS_MFD_STM32F4_RCC_H */
diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h
new file mode 100644
index 0000000..c9087f5
--- /dev/null
+++ b/include/dt-bindings/mfd/stm32f7-rcc.h
@@ -0,0 +1,114 @@
+/*
+ * This header provides constants for the STM32F7 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
+#define _DT_BINDINGS_MFD_STM32F7_RCC_H
+
+/* AHB1 */
+#define STM32F7_RCC_AHB1_GPIOA		0
+#define STM32F7_RCC_AHB1_GPIOB		1
+#define STM32F7_RCC_AHB1_GPIOC		2
+#define STM32F7_RCC_AHB1_GPIOD		3
+#define STM32F7_RCC_AHB1_GPIOE		4
+#define STM32F7_RCC_AHB1_GPIOF		5
+#define STM32F7_RCC_AHB1_GPIOG		6
+#define STM32F7_RCC_AHB1_GPIOH		7
+#define STM32F7_RCC_AHB1_GPIOI		8
+#define STM32F7_RCC_AHB1_GPIOJ		9
+#define STM32F7_RCC_AHB1_GPIOK		10
+#define STM32F7_RCC_AHB1_CRC		12
+#define STM32F7_RCC_AHB1_BKPSRAM	18
+#define STM32F7_RCC_AHB1_DTCMRAM	20
+#define STM32F7_RCC_AHB1_DMA1		21
+#define STM32F7_RCC_AHB1_DMA2		22
+#define STM32F7_RCC_AHB1_DMA2D		23
+#define STM32F7_RCC_AHB1_ETHMAC		25
+#define STM32F7_RCC_AHB1_ETHMACTX	26
+#define STM32F7_RCC_AHB1_ETHMACRX	27
+#define STM32FF_RCC_AHB1_ETHMACPTP	28
+#define STM32F7_RCC_AHB1_OTGHS		29
+#define STM32F7_RCC_AHB1_OTGHSULPI	30
+
+#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
+#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
+
+
+/* AHB2 */
+#define STM32F7_RCC_AHB2_DCMI		0
+#define STM32F7_RCC_AHB2_CRYP		4
+#define STM32F7_RCC_AHB2_HASH		5
+#define STM32F7_RCC_AHB2_RNG		6
+#define STM32F7_RCC_AHB2_OTGFS		7
+
+#define STM32F7_AHB2_RESET(bit)	(STM32F7_RCC_AHB2_##bit + (0x14 * 8))
+#define STM32F7_AHB2_CLOCK(bit)	(STM32F7_RCC_AHB2_##bit + 0x20)
+
+/* AHB3 */
+#define STM32F7_RCC_AHB3_FMC		0
+#define STM32F7_RCC_AHB3_QSPI		1
+
+#define STM32F7_AHB3_RESET(bit)	(STM32F7_RCC_AHB3_##bit + (0x18 * 8))
+#define STM32F7_AHB3_CLOCK(bit)	(STM32F7_RCC_AHB3_##bit + 0x40)
+
+/* APB1 */
+#define STM32F7_RCC_APB1_TIM2		0
+#define STM32F7_RCC_APB1_TIM3		1
+#define STM32F7_RCC_APB1_TIM4		2
+#define STM32F7_RCC_APB1_TIM5		3
+#define STM32F7_RCC_APB1_TIM6		4
+#define STM32F7_RCC_APB1_TIM7		5
+#define STM32F7_RCC_APB1_TIM12		6
+#define STM32F7_RCC_APB1_TIM13		7
+#define STM32F7_RCC_APB1_TIM14		8
+#define STM32F7_RCC_APB1_LPTIM1		9
+#define STM32F7_RCC_APB1_WWDG		11
+#define STM32F7_RCC_APB1_SPI2		14
+#define STM32F7_RCC_APB1_SPI3		15
+#define STM32F7_RCC_APB1_SPDIFRX	16
+#define STM32F7_RCC_APB1_UART2		17
+#define STM32F7_RCC_APB1_UART3		18
+#define STM32F7_RCC_APB1_UART4		19
+#define STM32F7_RCC_APB1_UART5		20
+#define STM32F7_RCC_APB1_I2C1		21
+#define STM32F7_RCC_APB1_I2C2		22
+#define STM32F7_RCC_APB1_I2C3		23
+#define STM32F7_RCC_APB1_I2C4		24
+#define STM32F7_RCC_APB1_CAN1		25
+#define STM32F7_RCC_APB1_CAN2		26
+#define STM32F7_RCC_APB1_CEC		27
+#define STM32F7_RCC_APB1_PWR		28
+#define STM32F7_RCC_APB1_DAC		29
+#define STM32F7_RCC_APB1_UART7		30
+#define STM32F7_RCC_APB1_UART8		31
+
+#define STM32F7_APB1_RESET(bit)	(STM32F7_RCC_APB1_##bit + (0x20 * 8))
+#define STM32F7_APB1_CLOCK(bit)	(STM32F7_RCC_APB1_##bit + 0x80)
+
+/* APB2 */
+#define STM32F7_RCC_APB2_TIM1		0
+#define STM32F7_RCC_APB2_TIM8		1
+#define STM32F7_RCC_APB2_USART1		4
+#define STM32F7_RCC_APB2_USART6		5
+#define STM32F7_RCC_APB2_SDMMC2		7
+#define STM32F7_RCC_APB2_ADC1		8
+#define STM32F7_RCC_APB2_ADC2		9
+#define STM32F7_RCC_APB2_ADC3		10
+#define STM32F7_RCC_APB2_SDMMC1		11
+#define STM32F7_RCC_APB2_SPI1		12
+#define STM32F7_RCC_APB2_SPI4		13
+#define STM32F7_RCC_APB2_SYSCFG		14
+#define STM32F7_RCC_APB2_TIM9		16
+#define STM32F7_RCC_APB2_TIM10		17
+#define STM32F7_RCC_APB2_TIM11		18
+#define STM32F7_RCC_APB2_SPI5		20
+#define STM32F7_RCC_APB2_SPI6		21
+#define STM32F7_RCC_APB2_SAI1		22
+#define STM32F7_RCC_APB2_SAI2		23
+#define STM32F7_RCC_APB2_LTDC		26
+#define STM32F7_RCC_APB2_DSI		27
+
+#define STM32F7_APB2_RESET(bit)	(STM32F7_RCC_APB2_##bit + (0x24 * 8))
+#define STM32F7_APB2_CLOCK(bit)	(STM32F7_RCC_APB2_##bit + 0xA0)
+
+#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */
diff --git a/include/dt-bindings/mfd/stm32h7-rcc.h b/include/dt-bindings/mfd/stm32h7-rcc.h
new file mode 100644
index 0000000..b96b3c3
--- /dev/null
+++ b/include/dt-bindings/mfd/stm32h7-rcc.h
@@ -0,0 +1,138 @@
+/*
+ * This header provides constants for the STM32H7 RCC IP
+ */
+
+#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H
+#define _DT_BINDINGS_MFD_STM32H7_RCC_H
+
+/* AHB3 */
+#define STM32H7_RCC_AHB3_MDMA		0
+#define STM32H7_RCC_AHB3_DMA2D		4
+#define STM32H7_RCC_AHB3_JPGDEC		5
+#define STM32H7_RCC_AHB3_FMC		12
+#define STM32H7_RCC_AHB3_QUADSPI	14
+#define STM32H7_RCC_AHB3_SDMMC1		16
+#define STM32H7_RCC_AHB3_CPU1		31
+
+#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
+
+/* AHB1 */
+#define STM32H7_RCC_AHB1_DMA1		0
+#define STM32H7_RCC_AHB1_DMA2		1
+#define STM32H7_RCC_AHB1_ADC12		5
+#define STM32H7_RCC_AHB1_ART		14
+#define STM32H7_RCC_AHB1_ETH1MAC	15
+#define STM32H7_RCC_AHB1_USB1OTG	25
+#define STM32H7_RCC_AHB1_USB2OTG	27
+#define STM32H7_RCC_AHB1_CPU2		31
+
+#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
+
+/* AHB2 */
+#define STM32H7_RCC_AHB2_CAMITF		0
+#define STM32H7_RCC_AHB2_CRYPT		4
+#define STM32H7_RCC_AHB2_HASH		5
+#define STM32H7_RCC_AHB2_RNG		6
+#define STM32H7_RCC_AHB2_SDMMC2		9
+
+#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
+
+/* AHB4 */
+#define STM32H7_RCC_AHB4_GPIOA		0
+#define STM32H7_RCC_AHB4_GPIOB		1
+#define STM32H7_RCC_AHB4_GPIOC		2
+#define STM32H7_RCC_AHB4_GPIOD		3
+#define STM32H7_RCC_AHB4_GPIOE		4
+#define STM32H7_RCC_AHB4_GPIOF		5
+#define STM32H7_RCC_AHB4_GPIOG		6
+#define STM32H7_RCC_AHB4_GPIOH		7
+#define STM32H7_RCC_AHB4_GPIOI		8
+#define STM32H7_RCC_AHB4_GPIOJ		9
+#define STM32H7_RCC_AHB4_GPIOK		10
+#define STM32H7_RCC_AHB4_CRC		19
+#define STM32H7_RCC_AHB4_BDMA		21
+#define STM32H7_RCC_AHB4_ADC3		24
+#define STM32H7_RCC_AHB4_HSEM		25
+
+#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
+
+
+/* APB3 */
+#define STM32H7_RCC_APB3_LTDC		3
+#define STM32H7_RCC_APB3_DSI		4
+
+#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8))
+
+/* APB1L */
+#define STM32H7_RCC_APB1L_TIM2		0
+#define STM32H7_RCC_APB1L_TIM3		1
+#define STM32H7_RCC_APB1L_TIM4		2
+#define STM32H7_RCC_APB1L_TIM5		3
+#define STM32H7_RCC_APB1L_TIM6		4
+#define STM32H7_RCC_APB1L_TIM7		5
+#define STM32H7_RCC_APB1L_TIM12		6
+#define STM32H7_RCC_APB1L_TIM13		7
+#define STM32H7_RCC_APB1L_TIM14		8
+#define STM32H7_RCC_APB1L_LPTIM1	9
+#define STM32H7_RCC_APB1L_SPI2		14
+#define STM32H7_RCC_APB1L_SPI3		15
+#define STM32H7_RCC_APB1L_SPDIF_RX	16
+#define STM32H7_RCC_APB1L_USART2	17
+#define STM32H7_RCC_APB1L_USART3	18
+#define STM32H7_RCC_APB1L_UART4		19
+#define STM32H7_RCC_APB1L_UART5		20
+#define STM32H7_RCC_APB1L_I2C1		21
+#define STM32H7_RCC_APB1L_I2C2		22
+#define STM32H7_RCC_APB1L_I2C3		23
+#define STM32H7_RCC_APB1L_HDMICEC	27
+#define STM32H7_RCC_APB1L_DAC12		29
+#define STM32H7_RCC_APB1L_USART7	30
+#define STM32H7_RCC_APB1L_USART8	31
+
+#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8))
+
+/* APB1H */
+#define STM32H7_RCC_APB1H_CRS		1
+#define STM32H7_RCC_APB1H_SWP		2
+#define STM32H7_RCC_APB1H_OPAMP		4
+#define STM32H7_RCC_APB1H_MDIOS		5
+#define STM32H7_RCC_APB1H_FDCAN		8
+
+#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8))
+
+/* APB2 */
+#define STM32H7_RCC_APB2_TIM1		0
+#define STM32H7_RCC_APB2_TIM8		1
+#define STM32H7_RCC_APB2_USART1		4
+#define STM32H7_RCC_APB2_USART6		5
+#define STM32H7_RCC_APB2_SPI1		12
+#define STM32H7_RCC_APB2_SPI4		13
+#define STM32H7_RCC_APB2_TIM15		16
+#define STM32H7_RCC_APB2_TIM16		17
+#define STM32H7_RCC_APB2_TIM17		18
+#define STM32H7_RCC_APB2_SPI5		20
+#define STM32H7_RCC_APB2_SAI1		22
+#define STM32H7_RCC_APB2_SAI2		23
+#define STM32H7_RCC_APB2_SAI3		24
+#define STM32H7_RCC_APB2_DFSDM1		28
+#define STM32H7_RCC_APB2_HRTIM		29
+
+#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8))
+
+/* APB4 */
+#define STM32H7_RCC_APB4_SYSCFG		1
+#define STM32H7_RCC_APB4_LPUART1	3
+#define STM32H7_RCC_APB4_SPI6		5
+#define STM32H7_RCC_APB4_I2C4		7
+#define STM32H7_RCC_APB4_LPTIM2		9
+#define STM32H7_RCC_APB4_LPTIM3		10
+#define STM32H7_RCC_APB4_LPTIM4		11
+#define STM32H7_RCC_APB4_LPTIM5		12
+#define STM32H7_RCC_APB4_COMP12		14
+#define STM32H7_RCC_APB4_VREF		15
+#define STM32H7_RCC_APB4_SAI4		21
+#define STM32H7_RCC_APB4_TMPSENS	26
+
+#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8))
+
+#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */
diff --git a/include/dt-bindings/mrc/quark.h b/include/dt-bindings/mrc/quark.h
new file mode 100644
index 0000000..c763e74
--- /dev/null
+++ b/include/dt-bindings/mrc/quark.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Intel Quark MRC bindings include several properties
+ * as part of an Intel Quark MRC node. In most cases,
+ * the value of these properties uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_QRK_MRC_H_
+#define _DT_BINDINGS_QRK_MRC_H_
+
+/* MRC platform data flags */
+#define MRC_FLAG_ECC_EN		0x00000001
+#define MRC_FLAG_SCRAMBLE_EN	0x00000002
+#define MRC_FLAG_MEMTEST_EN	0x00000004
+/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
+#define MRC_FLAG_TOP_TREE_EN	0x00000008
+/* If set ODR signal is asserted to DRAM devices on writes */
+#define MRC_FLAG_WR_ODT_EN	0x00000010
+
+/* DRAM width */
+#define DRAM_WIDTH_X8		0
+#define DRAM_WIDTH_X16		1
+#define DRAM_WIDTH_X32		2
+
+/* DRAM speed */
+#define DRAM_FREQ_800		0
+#define DRAM_FREQ_1066		1
+
+/* DRAM type */
+#define DRAM_TYPE_DDR3		0
+#define DRAM_TYPE_DDR3L		1
+
+/* DRAM rank mask */
+#define DRAM_RANK(n)		(1 << (n))
+
+/* DRAM channel mask */
+#define DRAM_CHANNEL(n)		(1 << (n))
+
+/* DRAM channel width */
+#define DRAM_CHANNEL_WIDTH_X8	0
+#define DRAM_CHANNEL_WIDTH_X16	1
+#define DRAM_CHANNEL_WIDTH_X32	2
+
+/* DRAM address mode */
+#define DRAM_ADDR_MODE0		0
+#define DRAM_ADDR_MODE1		1
+#define DRAM_ADDR_MODE2		2
+
+/* DRAM refresh rate */
+#define DRAM_REFRESH_RATE_195US	1
+#define DRAM_REFRESH_RATE_39US	2
+#define DRAM_REFRESH_RATE_785US	3
+
+/* DRAM SR temprature range */
+#define DRAM_SRT_RANGE_NORMAL	0
+#define DRAM_SRT_RANGE_EXTENDED	1
+
+/* DRAM ron value */
+#define DRAM_RON_34OHM		0
+#define DRAM_RON_40OHM		1
+
+/* DRAM rtt nom value */
+#define DRAM_RTT_NOM_40OHM	0
+#define DRAM_RTT_NOM_60OHM	1
+#define DRAM_RTT_NOM_120OHM	2
+
+/* DRAM rd odt value */
+#define DRAM_RD_ODT_OFF		0
+#define DRAM_RD_ODT_60OHM	1
+#define DRAM_RD_ODT_120OHM	2
+#define DRAM_RD_ODT_180OHM	3
+
+/* DRAM density */
+#define DRAM_DENSITY_512M	0
+#define DRAM_DENSITY_1G		1
+#define DRAM_DENSITY_2G		2
+#define DRAM_DENSITY_4G		3
+
+#endif /* _DT_BINDINGS_QRK_MRC_H_ */
diff --git a/include/dt-bindings/mscc/jr2_data.h b/include/dt-bindings/mscc/jr2_data.h
new file mode 100644
index 0000000..2f06fc5
--- /dev/null
+++ b/include/dt-bindings/mscc/jr2_data.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _JR2_DATA_H_
+#define _JR2_DATA_H_
+
+#define SERDES1G(x)     (x)
+#define SERDES1G_MAX    SERDES1G(10)
+#define SERDES6G(x)     (SERDES1G_MAX + 1 + (x))
+#define SERDES6G_MAX    SERDES6G(17)
+#define SERDES_MAX      (SERDES6G_MAX + 1)
+
+/* similar with phy_interface_t */
+#define PHY_MODE_SGMII  2
+#define PHY_MODE_QSGMII 4
+
+#endif
diff --git a/include/dt-bindings/mscc/luton_data.h b/include/dt-bindings/mscc/luton_data.h
new file mode 100644
index 0000000..e488567
--- /dev/null
+++ b/include/dt-bindings/mscc/luton_data.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#ifndef _LUTON_DATA_H_
+#define _LUTON_DATA_H_
+
+#define SERDES6G(x)     (x)
+#define SERDES6G_MAX    SERDES6G(5)
+#define SERDES_MAX      (SERDES6G_MAX)
+
+/* similar with phy_interface_t */
+#define PHY_MODE_SGMII  2
+#define PHY_MODE_QSGMII 4
+
+#endif
diff --git a/include/dt-bindings/mscc/ocelot_data.h b/include/dt-bindings/mscc/ocelot_data.h
new file mode 100644
index 0000000..7a5a1bf
--- /dev/null
+++ b/include/dt-bindings/mscc/ocelot_data.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#ifndef _OCELOT_DATA_H_
+#define _OCELOT_DATA_H_
+
+#define SERDES1G(x)     (x)
+#define SERDES1G_MAX    SERDES1G(7)
+#define SERDES6G(x)     (SERDES1G_MAX + 1 + (x))
+#define SERDES6G_MAX    SERDES6G(11)
+#define SERDES_MAX      (SERDES6G_MAX + 1)
+
+/* similar with phy_interface_t */
+#define PHY_MODE_SGMII  2
+#define PHY_MODE_QSGMII 4
+
+#endif
diff --git a/include/dt-bindings/mscc/serval_data.h b/include/dt-bindings/mscc/serval_data.h
new file mode 100644
index 0000000..b374fda
--- /dev/null
+++ b/include/dt-bindings/mscc/serval_data.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#ifndef _SERVAL_DATA_H_
+#define _SERVAL_DATA_H_
+
+#define SERDES1G(x)     (x)
+#define SERDES1G_MAX    SERDES1G(9)
+#define SERDES6G(x)     (SERDES1G_MAX + 1 + (x))
+#define SERDES6G_MAX    SERDES6G(11)
+#define SERDES_MAX      (SERDES6G_MAX + 1)
+
+/* similar with phy_interface_t */
+#define PHY_MODE_SGMII  2
+#define PHY_MODE_QSGMII 4
+
+#endif
diff --git a/include/dt-bindings/net/microchip-lan78xx.h b/include/dt-bindings/net/microchip-lan78xx.h
new file mode 100644
index 0000000..0742ff0
--- /dev/null
+++ b/include/dt-bindings/net/microchip-lan78xx.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H
+#define _DT_BINDINGS_MICROCHIP_LAN78XX_H
+
+/* LED modes for LAN7800/LAN7850 embedded PHY */
+
+#define LAN78XX_LINK_ACTIVITY           0
+#define LAN78XX_LINK_1000_ACTIVITY      1
+#define LAN78XX_LINK_100_ACTIVITY       2
+#define LAN78XX_LINK_10_ACTIVITY        3
+#define LAN78XX_LINK_100_1000_ACTIVITY  4
+#define LAN78XX_LINK_10_1000_ACTIVITY   5
+#define LAN78XX_LINK_10_100_ACTIVITY    6
+#define LAN78XX_DUPLEX_COLLISION        8
+#define LAN78XX_COLLISION               9
+#define LAN78XX_ACTIVITY                10
+#define LAN78XX_AUTONEG_FAULT           12
+#define LAN78XX_FORCE_LED_OFF           14
+#define LAN78XX_FORCE_LED_ON            15
+
+#endif
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
new file mode 100644
index 0000000..85d08f6
--- /dev/null
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * TI DP83867 PHY drivers
+ *
+ */
+
+#ifndef _DT_BINDINGS_TI_DP83867_H
+#define _DT_BINDINGS_TI_DP83867_H
+
+/* PHY CTRL bits */
+#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB	0x00
+#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB	0x01
+#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB	0x02
+#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB	0x03
+
+/* RGMIIDCTL internal delay for rx and tx */
+#define DP83867_RGMIIDCTL_250_PS	0x0
+#define DP83867_RGMIIDCTL_500_PS	0x1
+#define DP83867_RGMIIDCTL_750_PS	0x2
+#define DP83867_RGMIIDCTL_1_NS		0x3
+#define DP83867_RGMIIDCTL_1_25_NS	0x4
+#define DP83867_RGMIIDCTL_1_50_NS	0x5
+#define DP83867_RGMIIDCTL_1_75_NS	0x6
+#define DP83867_RGMIIDCTL_2_00_NS	0x7
+#define DP83867_RGMIIDCTL_2_25_NS	0x8
+#define DP83867_RGMIIDCTL_2_50_NS	0x9
+#define DP83867_RGMIIDCTL_2_75_NS	0xa
+#define DP83867_RGMIIDCTL_3_00_NS	0xb
+#define DP83867_RGMIIDCTL_3_25_NS	0xc
+#define DP83867_RGMIIDCTL_3_50_NS	0xd
+#define DP83867_RGMIIDCTL_3_75_NS	0xe
+#define DP83867_RGMIIDCTL_4_00_NS	0xf
+
+/* IO_MUX_CFG - Clock output selection */
+#define DP83867_CLK_O_SEL_CHN_A_RCLK		0x0
+#define DP83867_CLK_O_SEL_CHN_B_RCLK		0x1
+#define DP83867_CLK_O_SEL_CHN_C_RCLK		0x2
+#define DP83867_CLK_O_SEL_CHN_D_RCLK		0x3
+#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5	0x4
+#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5	0x5
+#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5	0x6
+#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5	0x7
+#define DP83867_CLK_O_SEL_CHN_A_TCLK		0x8
+#define DP83867_CLK_O_SEL_CHN_B_TCLK		0x9
+#define DP83867_CLK_O_SEL_CHN_C_TCLK		0xA
+#define DP83867_CLK_O_SEL_CHN_D_TCLK		0xB
+#define DP83867_CLK_O_SEL_REF_CLK		0xC
+
+#endif
diff --git a/include/dt-bindings/phy/phy-am654-serdes.h b/include/dt-bindings/phy/phy-am654-serdes.h
new file mode 100644
index 0000000..e8d9017
--- /dev/null
+++ b/include/dt-bindings/phy/phy-am654-serdes.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for AM654 SERDES.
+ */
+
+#ifndef _DT_BINDINGS_AM654_SERDES
+#define _DT_BINDINGS_AM654_SERDES
+
+#define AM654_SERDES_CMU_REFCLK	0
+#define AM654_SERDES_LO_REFCLK	1
+#define AM654_SERDES_RO_REFCLK	2
+
+#endif /* _DT_BINDINGS_AM654_SERDES */
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
new file mode 100644
index 0000000..6c90193
--- /dev/null
+++ b/include/dt-bindings/phy/phy.h
@@ -0,0 +1,19 @@
+/*
+ *
+ * This header provides constants for the phy framework
+ *
+ * Copyright (C) 2014 STMicroelectronics
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com>
+ * License terms:  GNU General Public License (GPL), version 2
+ */
+
+#ifndef _DT_BINDINGS_PHY
+#define _DT_BINDINGS_PHY
+
+#define PHY_NONE		0
+#define PHY_TYPE_SATA		1
+#define PHY_TYPE_PCIE		2
+#define PHY_TYPE_USB2		3
+#define PHY_TYPE_USB3		4
+
+#endif /* _DT_BINDINGS_PHY */
diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h
new file mode 100644
index 0000000..226f772
--- /dev/null
+++ b/include/dt-bindings/pinctrl/am33xx.h
@@ -0,0 +1,43 @@
+/*
+ * This header provides constants specific to AM33XX pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
+#define _DT_BINDINGS_PINCTRL_AM33XX_H
+
+#include <dt-bindings/pinctrl/omap.h>
+
+/* am33xx specific mux bit defines */
+#undef PULL_ENA
+#undef INPUT_EN
+
+#define PULL_DISABLE		(1 << 3)
+#define INPUT_EN		(1 << 5)
+#define SLEWCTRL_SLOW		(1 << 6)
+#define SLEWCTRL_FAST		0
+
+/* update macro depending on INPUT_EN and PULL_ENA */
+#undef PIN_OUTPUT
+#undef PIN_OUTPUT_PULLUP
+#undef PIN_OUTPUT_PULLDOWN
+#undef PIN_INPUT
+#undef PIN_INPUT_PULLUP
+#undef PIN_INPUT_PULLDOWN
+
+#define PIN_OUTPUT		(PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP	(PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	0
+#define PIN_INPUT		(INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP	(INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(INPUT_EN)
+
+/* undef non-existing modes */
+#undef PIN_OFF_NONE
+#undef PIN_OFF_OUTPUT_HIGH
+#undef PIN_OFF_OUTPUT_LOW
+#undef PIN_OFF_INPUT_PULLUP
+#undef PIN_OFF_INPUT_PULLDOWN
+#undef PIN_OFF_WAKEUPENABLE
+
+#endif
+
diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h
new file mode 100644
index 0000000..292c2eb
--- /dev/null
+++ b/include/dt-bindings/pinctrl/am43xx.h
@@ -0,0 +1,39 @@
+/*
+ * This header provides constants specific to AM43XX pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H
+#define _DT_BINDINGS_PINCTRL_AM43XX_H
+
+#define MUX_MODE0	0
+#define MUX_MODE1	1
+#define MUX_MODE2	2
+#define MUX_MODE3	3
+#define MUX_MODE4	4
+#define MUX_MODE5	5
+#define MUX_MODE6	6
+#define MUX_MODE7	7
+#define MUX_MODE8	8
+
+#define PULL_DISABLE		(1 << 16)
+#define PULL_UP			(1 << 17)
+#define INPUT_EN		(1 << 18)
+#define SLEWCTRL_SLOW		(1 << 19)
+#define SLEWCTRL_FAST		0
+#define DS0_PULL_UP_DOWN_EN	(1 << 27)
+#define WAKEUP_ENABLE		(1 << 29)
+
+#define PIN_OUTPUT		(PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP	(PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	0
+#define PIN_INPUT		(INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP	(INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(INPUT_EN)
+
+/*
+ * Macro to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define AM4372_IOPAD(pa, val)	(((pa) & 0xffff) - 0x0800) (val)
+
+#endif
diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h
new file mode 100644
index 0000000..616f5ce
--- /dev/null
+++ b/include/dt-bindings/pinctrl/at91.h
@@ -0,0 +1,46 @@
+/*
+ * This header provides constants for most at91 pinctrl bindings.
+ *
+ * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef __DT_BINDINGS_AT91_PINCTRL_H__
+#define __DT_BINDINGS_AT91_PINCTRL_H__
+
+#define AT91_PINCTRL_NONE		(0 << 0)
+#define AT91_PINCTRL_PULL_UP		(1 << 0)
+#define AT91_PINCTRL_MULTI_DRIVE	(1 << 1)
+#define AT91_PINCTRL_DEGLITCH		(1 << 2)
+#define AT91_PINCTRL_PULL_DOWN		(1 << 3)
+#define AT91_PINCTRL_DIS_SCHMIT		(1 << 4)
+#define AT91_PINCTRL_OUTPUT		(1 << 7)
+#define AT91_PINCTRL_OUTPUT_VAL(x)	((x & 0x1) << 8)
+#define AT91_PINCTRL_SLEWRATE		(1 << 9)
+#define AT91_PINCTRL_DEBOUNCE		(1 << 16)
+#define AT91_PINCTRL_DEBOUNCE_VAL(x)	(x << 17)
+
+#define AT91_PINCTRL_PULL_UP_DEGLITCH	(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
+
+#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT		(0x0 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_LOW			(0x1 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_MED			(0x2 << 5)
+#define AT91_PINCTRL_DRIVE_STRENGTH_HI			(0x3 << 5)
+
+#define AT91_PINCTRL_SLEWRATE_DIS	(0x0 << 9)
+#define AT91_PINCTRL_SLEWRATE_ENA	(0x1 << 9)
+
+#define AT91_PIOA	0
+#define AT91_PIOB	1
+#define AT91_PIOC	2
+#define AT91_PIOD	3
+#define AT91_PIOE	4
+
+#define AT91_PERIPH_GPIO	0
+#define AT91_PERIPH_A		1
+#define AT91_PERIPH_B		2
+#define AT91_PERIPH_C		3
+#define AT91_PERIPH_D		4
+
+#endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */
diff --git a/include/dt-bindings/pinctrl/bcm2835.h b/include/dt-bindings/pinctrl/bcm2835.h
new file mode 100644
index 0000000..b5b2654
--- /dev/null
+++ b/include/dt-bindings/pinctrl/bcm2835.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Header providing constants for bcm2835 pinctrl bindings.
+ *
+ * Copyright (C) 2015 Stefan Wahren <stefan.wahren@i2se.com>
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__
+#define __DT_BINDINGS_PINCTRL_BCM2835_H__
+
+/* brcm,function property */
+#define BCM2835_FSEL_GPIO_IN	0
+#define BCM2835_FSEL_GPIO_OUT	1
+#define BCM2835_FSEL_ALT5	2
+#define BCM2835_FSEL_ALT4	3
+#define BCM2835_FSEL_ALT0	4
+#define BCM2835_FSEL_ALT1	5
+#define BCM2835_FSEL_ALT2	6
+#define BCM2835_FSEL_ALT3	7
+
+/* brcm,pull property */
+#define BCM2835_PUD_OFF		0
+#define BCM2835_PUD_DOWN	1
+#define BCM2835_PUD_UP		2
+
+#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
new file mode 100644
index 0000000..18ec5df
--- /dev/null
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -0,0 +1,80 @@
+/*
+ * This header provides constants for DRA pinctrl bindings.
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_DRA_H
+#define _DT_BINDINGS_PINCTRL_DRA_H
+
+/* DRA7 mux mode options for each pin. See TRM for options */
+#define MUX_MODE0	0x0
+#define MUX_MODE1	0x1
+#define MUX_MODE2	0x2
+#define MUX_MODE3	0x3
+#define MUX_MODE4	0x4
+#define MUX_MODE5	0x5
+#define MUX_MODE6	0x6
+#define MUX_MODE7	0x7
+#define MUX_MODE8	0x8
+#define MUX_MODE9	0x9
+#define MUX_MODE10	0xa
+#define MUX_MODE11	0xb
+#define MUX_MODE12	0xc
+#define MUX_MODE13	0xd
+#define MUX_MODE14	0xe
+#define MUX_MODE15	0xf
+
+/* Certain pins need virtual mode, but note: they may glitch */
+#define MUX_VIRTUAL_MODE0	(MODE_SELECT | (0x0 << 4))
+#define MUX_VIRTUAL_MODE1	(MODE_SELECT | (0x1 << 4))
+#define MUX_VIRTUAL_MODE2	(MODE_SELECT | (0x2 << 4))
+#define MUX_VIRTUAL_MODE3	(MODE_SELECT | (0x3 << 4))
+#define MUX_VIRTUAL_MODE4	(MODE_SELECT | (0x4 << 4))
+#define MUX_VIRTUAL_MODE5	(MODE_SELECT | (0x5 << 4))
+#define MUX_VIRTUAL_MODE6	(MODE_SELECT | (0x6 << 4))
+#define MUX_VIRTUAL_MODE7	(MODE_SELECT | (0x7 << 4))
+#define MUX_VIRTUAL_MODE8	(MODE_SELECT | (0x8 << 4))
+#define MUX_VIRTUAL_MODE9	(MODE_SELECT | (0x9 << 4))
+#define MUX_VIRTUAL_MODE10	(MODE_SELECT | (0xa << 4))
+#define MUX_VIRTUAL_MODE11	(MODE_SELECT | (0xb << 4))
+#define MUX_VIRTUAL_MODE12	(MODE_SELECT | (0xc << 4))
+#define MUX_VIRTUAL_MODE13	(MODE_SELECT | (0xd << 4))
+#define MUX_VIRTUAL_MODE14	(MODE_SELECT | (0xe << 4))
+#define MUX_VIRTUAL_MODE15	(MODE_SELECT | (0xf << 4))
+
+#define MODE_SELECT		(1 << 8)
+
+#define PULL_ENA		(0 << 16)
+#define PULL_DIS		(1 << 16)
+#define PULL_UP			(1 << 17)
+#define INPUT_EN		(1 << 18)
+#define SLEWCONTROL		(1 << 19)
+#define WAKEUP_EN		(1 << 24)
+#define WAKEUP_EVENT		(1 << 25)
+
+/* Active pin states */
+#define PIN_OUTPUT		(0 | PULL_DIS)
+#define PIN_OUTPUT_PULLUP	(PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(0)
+#define PIN_INPUT		(INPUT_EN | PULL_DIS)
+#define PIN_INPUT_SLEW		(INPUT_EN | SLEWCONTROL)
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
+/*
+ * Macro to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define DRA7XX_CORE_IOPAD(pa, val)	(((pa) & 0xffff) - 0x3400) (val)
+
+/* DRA7 IODELAY configuration parameters */
+#define A_DELAY_PS(val)			((val) & 0xffff)
+#define G_DELAY_PS(val)			((val) & 0xffff)
+#endif
+
diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
new file mode 100644
index 0000000..0359bfd
--- /dev/null
+++ b/include/dt-bindings/pinctrl/hisi.h
@@ -0,0 +1,74 @@
+/*
+ * This header provides constants for hisilicon pinctrl bindings.
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ * Copyright (c) 2015 Linaro Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_HISI_H
+#define _DT_BINDINGS_PINCTRL_HISI_H
+
+/* iomg bit definition */
+#define MUX_M0		0
+#define MUX_M1		1
+#define MUX_M2		2
+#define MUX_M3		3
+#define MUX_M4		4
+#define MUX_M5		5
+#define MUX_M6		6
+#define MUX_M7		7
+
+/* iocg bit definition */
+#define PULL_MASK	(3)
+#define PULL_DIS	(0)
+#define PULL_UP		(1 << 0)
+#define PULL_DOWN	(1 << 1)
+
+/* drive strength definition */
+#define DRIVE_MASK	(7 << 4)
+#define DRIVE1_02MA	(0 << 4)
+#define DRIVE1_04MA	(1 << 4)
+#define DRIVE1_08MA	(2 << 4)
+#define DRIVE1_10MA	(3 << 4)
+#define DRIVE2_02MA	(0 << 4)
+#define DRIVE2_04MA	(1 << 4)
+#define DRIVE2_08MA	(2 << 4)
+#define DRIVE2_10MA	(3 << 4)
+#define DRIVE3_04MA	(0 << 4)
+#define DRIVE3_08MA	(1 << 4)
+#define DRIVE3_12MA	(2 << 4)
+#define DRIVE3_16MA	(3 << 4)
+#define DRIVE3_20MA	(4 << 4)
+#define DRIVE3_24MA	(5 << 4)
+#define DRIVE3_32MA	(6 << 4)
+#define DRIVE3_40MA	(7 << 4)
+#define DRIVE4_02MA	(0 << 4)
+#define DRIVE4_04MA	(2 << 4)
+#define DRIVE4_08MA	(4 << 4)
+#define DRIVE4_10MA	(6 << 4)
+
+/* drive strength definition for hi3660 */
+#define DRIVE6_MASK	(15 << 4)
+#define DRIVE6_04MA	(0 << 4)
+#define DRIVE6_12MA	(4 << 4)
+#define DRIVE6_19MA	(8 << 4)
+#define DRIVE6_27MA	(10 << 4)
+#define DRIVE6_32MA	(15 << 4)
+#define DRIVE7_02MA	(0 << 4)
+#define DRIVE7_04MA	(1 << 4)
+#define DRIVE7_06MA	(2 << 4)
+#define DRIVE7_08MA	(3 << 4)
+#define DRIVE7_10MA	(4 << 4)
+#define DRIVE7_12MA	(5 << 4)
+#define DRIVE7_14MA	(6 << 4)
+#define DRIVE7_16MA	(7 << 4)
+#endif
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
new file mode 100644
index 0000000..ce0cd38
--- /dev/null
+++ b/include/dt-bindings/pinctrl/k3.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for TI K3-AM65 pinctrl bindings.
+ *
+ * Copyright (C) 2018 Texas Instruments
+ */
+#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
+#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
+
+#define PULL_DISABLE		(1 << 16)
+#define PULL_UP			(1 << 17)
+#define INPUT_EN		(1 << 18)
+#define SLEWCTRL_200MHZ		0
+#define SLEWCTRL_150MHZ		(1 << 19)
+#define SLEWCTRL_100MHZ		(2 << 19)
+#define SLEWCTRL_50MHZ		(3 << 19)
+#define TX_DIS			(1 << 21)
+#define ISO_OVR			(1 << 22)
+#define ISO_BYPASS		(1 << 23)
+#define DS_EN			(1 << 24)
+#define DS_INPUT		(1 << 25)
+#define DS_FORCE_OUT_HIGH	(1 << 26)
+#define DS_PULL_UP_DOWN_EN	0
+#define DS_PULL_UP_DOWN_DIS	(1 << 27)
+#define DS_PULL_UP_SEL		(1 << 28)
+#define WAKEUP_ENABLE		(1 << 29)
+
+#define PIN_OUTPUT		(PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP	(PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	0
+#define PIN_INPUT		(INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP	(INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(INPUT_EN)
+
+#define AM65X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM65X_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
+#define J721E_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define J721E_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
+#endif
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
new file mode 100644
index 0000000..58fe28f
--- /dev/null
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for OMAP pinctrl bindings.
+ *
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009-2010 Texas Instruments
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
+#define _DT_BINDINGS_PINCTRL_OMAP_H
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define MUX_MODE0	0
+#define MUX_MODE1	1
+#define MUX_MODE2	2
+#define MUX_MODE3	3
+#define MUX_MODE4	4
+#define MUX_MODE5	5
+#define MUX_MODE6	6
+#define MUX_MODE7	7
+
+/* 24xx/34xx mux bit defines */
+#define PULL_ENA		(1 << 3)
+#define PULL_UP			(1 << 4)
+#define ALTELECTRICALSEL	(1 << 5)
+
+/* 34xx specific mux bit defines */
+#define INPUT_EN		(1 << 8)
+#define OFF_EN			(1 << 9)
+#define OFFOUT_EN		(1 << 10)
+#define OFFOUT_VAL		(1 << 11)
+#define OFF_PULL_EN		(1 << 12)
+#define OFF_PULL_UP		(1 << 13)
+#define WAKEUP_EN		(1 << 14)
+
+/* 44xx specific mux bit defines */
+#define WAKEUP_EVENT		(1 << 15)
+
+/* Active pin states */
+#define PIN_OUTPUT		0
+#define PIN_OUTPUT_PULLUP	(PIN_OUTPUT | PULL_ENA | PULL_UP)
+#define PIN_OUTPUT_PULLDOWN	(PIN_OUTPUT | PULL_ENA)
+#define PIN_INPUT		INPUT_EN
+#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
+
+/* Off mode states */
+#define PIN_OFF_NONE		0
+#define PIN_OFF_OUTPUT_HIGH	(OFF_EN | OFFOUT_EN | OFFOUT_VAL)
+#define PIN_OFF_OUTPUT_LOW	(OFF_EN | OFFOUT_EN)
+#define PIN_OFF_INPUT_PULLUP	(OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
+#define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFF_PULL_EN)
+#define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
+
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
+#define OMAP2430_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3430_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
+#define OMAP3630_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
+#define OMAP3_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
+#define DM814X_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define DM816X_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define AM33XX_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+
+/*
+ * Macros to allow using the offset from the padconf physical address
+ * instead  of the offset from padconf base.
+ */
+#define OMAP_PADCONF_OFFSET(offset, base_offset)	((offset) - (base_offset))
+
+#define OMAP4_IOPAD(offset, val)	OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+#define OMAP5_IOPAD(offset, val)	OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+
+/*
+ * Define some commonly used pins configured by the boards.
+ * Note that some boards use alternative pins, so check
+ * the schematics before using these.
+ */
+#define OMAP3_UART1_RX		0x152
+#define OMAP3_UART2_RX		0x14a
+#define OMAP3_UART3_RX		0x16e
+#define OMAP4_UART2_RX		0xdc
+#define OMAP4_UART3_RX		0x104
+#define OMAP4_UART4_RX		0x11c
+
+#endif
+
diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h
new file mode 100644
index 0000000..e980fd5
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pads-imx8qm.h
@@ -0,0 +1,961 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef SC_PADS_H
+#define SC_PADS_H
+
+#define SC_P_SIM0_CLK                            0	/* DMA.SIM0.CLK, LSIO.GPIO0.IO00 */
+#define SC_P_SIM0_RST                            1	/* DMA.SIM0.RST, LSIO.GPIO0.IO01 */
+#define SC_P_SIM0_IO                             2	/* DMA.SIM0.IO, LSIO.GPIO0.IO02 */
+#define SC_P_SIM0_PD                             3	/* DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */
+#define SC_P_SIM0_POWER_EN                       4	/* DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */
+#define SC_P_SIM0_GPIO0_00                       5	/* DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM           6	/*  */
+#define SC_P_M40_I2C0_SCL                        7	/* M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */
+#define SC_P_M40_I2C0_SDA                        8	/* M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */
+#define SC_P_M40_GPIO0_00                        9	/* M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */
+#define SC_P_M40_GPIO0_01                        10	/* M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */
+#define SC_P_M41_I2C0_SCL                        11	/* M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */
+#define SC_P_M41_I2C0_SDA                        12	/* M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */
+#define SC_P_M41_GPIO0_00                        13	/* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
+#define SC_P_M41_GPIO0_01                        14	/* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
+#define SC_P_GPT0_CLK                            15	/* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
+#define SC_P_GPT0_CAPTURE                        16	/* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */
+#define SC_P_GPT0_COMPARE                        17	/* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
+#define SC_P_GPT1_CLK                            18	/* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
+#define SC_P_GPT1_CAPTURE                        19	/* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */
+#define SC_P_GPT1_COMPARE                        20	/* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
+#define SC_P_UART0_RX                            21	/* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
+#define SC_P_UART0_TX                            22	/* DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */
+#define SC_P_UART0_RTS_B                         23	/* DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */
+#define SC_P_UART0_CTS_B                         24	/* DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */
+#define SC_P_UART1_TX                            25	/* DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */
+#define SC_P_UART1_RX                            26	/* DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */
+#define SC_P_UART1_RTS_B                         27	/* DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */
+#define SC_P_UART1_CTS_B                         28	/* DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        29	/*  */
+#define SC_P_SCU_PMIC_MEMC_ON                    30	/* SCU.GPIO0.IOXX_PMIC_MEMC_ON */
+#define SC_P_SCU_WDOG_OUT                        31	/* SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SDA                        32	/* SCU.PMIC_I2C.SDA */
+#define SC_P_PMIC_I2C_SCL                        33	/* SCU.PMIC_I2C.SCL */
+#define SC_P_PMIC_EARLY_WARNING                  34	/* SCU.PMIC_EARLY_WARNING */
+#define SC_P_PMIC_INT_B                          35	/* SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00                        36	/* SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */
+#define SC_P_SCU_GPIO0_01                        37	/* SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */
+#define SC_P_SCU_GPIO0_02                        38	/* SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */
+#define SC_P_SCU_GPIO0_03                        39	/* SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */
+#define SC_P_SCU_GPIO0_04                        40	/* SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */
+#define SC_P_SCU_GPIO0_05                        41	/* SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */
+#define SC_P_SCU_GPIO0_06                        42	/* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
+#define SC_P_SCU_GPIO0_07                        43	/* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
+#define SC_P_SCU_BOOT_MODE0                      44	/* SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1                      45	/* SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2                      46	/* SCU.DSC.BOOT_MODE2 */
+#define SC_P_SCU_BOOT_MODE3                      47	/* SCU.DSC.BOOT_MODE3 */
+#define SC_P_SCU_BOOT_MODE4                      48	/* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
+#define SC_P_SCU_BOOT_MODE5                      49	/* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
+#define SC_P_LVDS0_GPIO00                        50	/* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
+#define SC_P_LVDS0_GPIO01                        51	/* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
+#define SC_P_LVDS0_I2C0_SCL                      52	/* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
+#define SC_P_LVDS0_I2C0_SDA                      53	/* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
+#define SC_P_LVDS0_I2C1_SCL                      54	/* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
+#define SC_P_LVDS0_I2C1_SDA                      55	/* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
+#define SC_P_LVDS1_GPIO00                        56	/* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
+#define SC_P_LVDS1_GPIO01                        57	/* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
+#define SC_P_LVDS1_I2C0_SCL                      58	/* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
+#define SC_P_LVDS1_I2C0_SDA                      59	/* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
+#define SC_P_LVDS1_I2C1_SCL                      60	/* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
+#define SC_P_LVDS1_I2C1_SDA                      61	/* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO      62	/*  */
+#define SC_P_MIPI_DSI0_I2C0_SCL                  63	/* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
+#define SC_P_MIPI_DSI0_I2C0_SDA                  64	/* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
+#define SC_P_MIPI_DSI0_GPIO0_00                  65	/* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */
+#define SC_P_MIPI_DSI0_GPIO0_01                  66	/* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
+#define SC_P_MIPI_DSI1_I2C0_SCL                  67	/* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
+#define SC_P_MIPI_DSI1_I2C0_SDA                  68	/* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
+#define SC_P_MIPI_DSI1_GPIO0_00                  69	/* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */
+#define SC_P_MIPI_DSI1_GPIO0_01                  70	/* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO   71	/*  */
+#define SC_P_MIPI_CSI0_MCLK_OUT                  72	/* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
+#define SC_P_MIPI_CSI0_I2C0_SCL                  73	/* MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_CSI0_I2C0_SDA                  74	/* MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_CSI0_GPIO0_00                  75	/* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_CSI0_GPIO0_01                  76	/* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_CSI1_MCLK_OUT                  77	/* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_CSI1_GPIO0_00                  78	/* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_CSI1_GPIO0_01                  79	/* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_CSI1_I2C0_SCL                  80	/* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
+#define SC_P_MIPI_CSI1_I2C0_SDA                  81	/* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
+#define SC_P_HDMI_TX0_TS_SCL                     82	/* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
+#define SC_P_HDMI_TX0_TS_SDA                     83	/* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
+#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO          84	/*  */
+#define SC_P_ESAI1_FSR                           85	/* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
+#define SC_P_ESAI1_FST                           86	/* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
+#define SC_P_ESAI1_SCKR                          87	/* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
+#define SC_P_ESAI1_SCKT                          88	/* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */
+#define SC_P_ESAI1_TX0                           89	/* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
+#define SC_P_ESAI1_TX1                           90	/* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
+#define SC_P_ESAI1_TX2_RX3                       91	/* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
+#define SC_P_ESAI1_TX3_RX2                       92	/* AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */
+#define SC_P_ESAI1_TX4_RX1                       93	/* AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */
+#define SC_P_ESAI1_TX5_RX0                       94	/* AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */
+#define SC_P_SPDIF0_RX                           95	/* AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */
+#define SC_P_SPDIF0_TX                           96	/* AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */
+#define SC_P_SPDIF0_EXT_CLK                      97	/* AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */
+#define SC_P_SPI3_SCK                            98	/* DMA.SPI3.SCK, LSIO.GPIO2.IO17 */
+#define SC_P_SPI3_SDO                            99	/* DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */
+#define SC_P_SPI3_SDI                            100	/* DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */
+#define SC_P_SPI3_CS0                            101	/* DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */
+#define SC_P_SPI3_CS1                            102	/* DMA.SPI3.CS1, LSIO.GPIO2.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       103	/*  */
+#define SC_P_ESAI0_FSR                           104	/* AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */
+#define SC_P_ESAI0_FST                           105	/* AUD.ESAI0.FST, LSIO.GPIO2.IO23 */
+#define SC_P_ESAI0_SCKR                          106	/* AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */
+#define SC_P_ESAI0_SCKT                          107	/* AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */
+#define SC_P_ESAI0_TX0                           108	/* AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */
+#define SC_P_ESAI0_TX1                           109	/* AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */
+#define SC_P_ESAI0_TX2_RX3                       110	/* AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */
+#define SC_P_ESAI0_TX3_RX2                       111	/* AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */
+#define SC_P_ESAI0_TX4_RX1                       112	/* AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */
+#define SC_P_ESAI0_TX5_RX0                       113	/* AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */
+#define SC_P_MCLK_IN0                            114	/* AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */
+#define SC_P_MCLK_OUT0                           115	/* AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC       116	/*  */
+#define SC_P_SPI0_SCK                            117	/* DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */
+#define SC_P_SPI0_SDO                            118	/* DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */
+#define SC_P_SPI0_SDI                            119	/* DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */
+#define SC_P_SPI0_CS0                            120	/* DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */
+#define SC_P_SPI0_CS1                            121	/* DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */
+#define SC_P_SPI2_SCK                            122	/* DMA.SPI2.SCK, LSIO.GPIO3.IO07 */
+#define SC_P_SPI2_SDO                            123	/* DMA.SPI2.SDO, LSIO.GPIO3.IO08 */
+#define SC_P_SPI2_SDI                            124	/* DMA.SPI2.SDI, LSIO.GPIO3.IO09 */
+#define SC_P_SPI2_CS0                            125	/* DMA.SPI2.CS0, LSIO.GPIO3.IO10 */
+#define SC_P_SPI2_CS1                            126	/* DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */
+#define SC_P_SAI1_RXC                            127	/* AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */
+#define SC_P_SAI1_RXD                            128	/* AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */
+#define SC_P_SAI1_RXFS                           129	/* AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */
+#define SC_P_SAI1_TXC                            130	/* AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */
+#define SC_P_SAI1_TXD                            131	/* AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */
+#define SC_P_SAI1_TXFS                           132	/* AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       133	/*  */
+#define SC_P_ADC_IN7                             134	/* DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */
+#define SC_P_ADC_IN6                             135	/* DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */
+#define SC_P_ADC_IN5                             136	/* DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */
+#define SC_P_ADC_IN4                             137	/* DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */
+#define SC_P_ADC_IN3                             138	/* DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */
+#define SC_P_ADC_IN2                             139	/* DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */
+#define SC_P_ADC_IN1                             140	/* DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */
+#define SC_P_ADC_IN0                             141	/* DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */
+#define SC_P_MLB_SIG                             142	/* CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */
+#define SC_P_MLB_CLK                             143	/* CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */
+#define SC_P_MLB_DATA                            144	/* CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT       145	/*  */
+#define SC_P_FLEXCAN0_RX                         146	/* DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */
+#define SC_P_FLEXCAN0_TX                         147	/* DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */
+#define SC_P_FLEXCAN1_RX                         148	/* DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */
+#define SC_P_FLEXCAN1_TX                         149	/* DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */
+#define SC_P_FLEXCAN2_RX                         150	/* DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */
+#define SC_P_FLEXCAN2_TX                         151	/* DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR       152	/*  */
+#define SC_P_USB_SS3_TC0                         153	/* DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1                         154	/* DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2                         155	/* DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3                         156	/* DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            157	/*  */
+#define SC_P_USDHC1_RESET_B                      158	/* CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */
+#define SC_P_USDHC1_VSELECT                      159	/* CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */
+#define SC_P_USDHC2_RESET_B                      160	/* CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */
+#define SC_P_USDHC2_VSELECT                      161	/* CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */
+#define SC_P_USDHC2_WP                           162	/* CONN.USDHC2.WP, LSIO.GPIO4.IO11 */
+#define SC_P_USDHC2_CD_B                         163	/* CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       164	/*  */
+#define SC_P_ENET0_MDIO                          165	/* CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */
+#define SC_P_ENET0_MDC                           166	/* CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */
+#define SC_P_ENET0_REFCLK_125M_25M               167	/* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */
+#define SC_P_ENET1_REFCLK_125M_25M               168	/* CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */
+#define SC_P_ENET1_MDIO                          169	/* CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */
+#define SC_P_ENET1_MDC                           170	/* CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        171	/*  */
+#define SC_P_QSPI1A_SS0_B                        172	/* LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */
+#define SC_P_QSPI1A_SS1_B                        173	/* LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */
+#define SC_P_QSPI1A_SCLK                         174	/* LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */
+#define SC_P_QSPI1A_DQS                          175	/* LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_QSPI1A_DATA3                        176	/* LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */
+#define SC_P_QSPI1A_DATA2                        177	/* LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */
+#define SC_P_QSPI1A_DATA1                        178	/* LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */
+#define SC_P_QSPI1A_DATA0                        179	/* LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1         180	/*  */
+#define SC_P_QSPI0A_DATA0                        181	/* LSIO.QSPI0A.DATA0 */
+#define SC_P_QSPI0A_DATA1                        182	/* LSIO.QSPI0A.DATA1 */
+#define SC_P_QSPI0A_DATA2                        183	/* LSIO.QSPI0A.DATA2 */
+#define SC_P_QSPI0A_DATA3                        184	/* LSIO.QSPI0A.DATA3 */
+#define SC_P_QSPI0A_DQS                          185	/* LSIO.QSPI0A.DQS */
+#define SC_P_QSPI0A_SS0_B                        186	/* LSIO.QSPI0A.SS0_B */
+#define SC_P_QSPI0A_SS1_B                        187	/* LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */
+#define SC_P_QSPI0A_SCLK                         188	/* LSIO.QSPI0A.SCLK */
+#define SC_P_QSPI0B_SCLK                         189	/* LSIO.QSPI0B.SCLK */
+#define SC_P_QSPI0B_DATA0                        190	/* LSIO.QSPI0B.DATA0 */
+#define SC_P_QSPI0B_DATA1                        191	/* LSIO.QSPI0B.DATA1 */
+#define SC_P_QSPI0B_DATA2                        192	/* LSIO.QSPI0B.DATA2 */
+#define SC_P_QSPI0B_DATA3                        193	/* LSIO.QSPI0B.DATA3 */
+#define SC_P_QSPI0B_DQS                          194	/* LSIO.QSPI0B.DQS */
+#define SC_P_QSPI0B_SS0_B                        195	/* LSIO.QSPI0B.SS0_B */
+#define SC_P_QSPI0B_SS1_B                        196	/* LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0         197	/*  */
+#define SC_P_PCIE_CTRL0_CLKREQ_B                 198	/* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */
+#define SC_P_PCIE_CTRL0_WAKE_B                   199	/* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */
+#define SC_P_PCIE_CTRL0_PERST_B                  200	/* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */
+#define SC_P_PCIE_CTRL1_CLKREQ_B                 201	/* HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */
+#define SC_P_PCIE_CTRL1_WAKE_B                   202	/* HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */
+#define SC_P_PCIE_CTRL1_PERST_B                  203	/* HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       204	/*  */
+#define SC_P_USB_HSIC0_DATA                      205	/* CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */
+#define SC_P_USB_HSIC0_STROBE                    206	/* CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */
+#define SC_P_CALIBRATION_0_HSIC                  207	/*  */
+#define SC_P_CALIBRATION_1_HSIC                  208	/*  */
+#define SC_P_EMMC0_CLK                           209	/* CONN.EMMC0.CLK, CONN.NAND.READY_B */
+#define SC_P_EMMC0_CMD                           210	/* CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */
+#define SC_P_EMMC0_DATA0                         211	/* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */
+#define SC_P_EMMC0_DATA1                         212	/* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */
+#define SC_P_EMMC0_DATA2                         213	/* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */
+#define SC_P_EMMC0_DATA3                         214	/* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */
+#define SC_P_EMMC0_DATA4                         215	/* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */
+#define SC_P_EMMC0_DATA5                         216	/* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */
+#define SC_P_EMMC0_DATA6                         217	/* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */
+#define SC_P_EMMC0_DATA7                         218	/* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */
+#define SC_P_EMMC0_STROBE                        219	/* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */
+#define SC_P_EMMC0_RESET_B                       220	/* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX        221	/*  */
+#define SC_P_USDHC1_CLK                          222	/* CONN.USDHC1.CLK, AUD.MQS.R */
+#define SC_P_USDHC1_CMD                          223	/* CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */
+#define SC_P_USDHC1_DATA0                        224	/* CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */
+#define SC_P_USDHC1_DATA1                        225	/* CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */
+#define SC_P_CTL_NAND_RE_P_N                     226	/*  */
+#define SC_P_USDHC1_DATA2                        227	/* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
+#define SC_P_USDHC1_DATA3                        228	/* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
+#define SC_P_CTL_NAND_DQS_P_N                    229	/*  */
+#define SC_P_USDHC1_DATA4                        230	/* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */
+#define SC_P_USDHC1_DATA5                        231	/* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
+#define SC_P_USDHC1_DATA6                        232	/* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
+#define SC_P_USDHC1_DATA7                        233	/* CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */
+#define SC_P_USDHC1_STROBE                       234	/* CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2         235	/*  */
+#define SC_P_USDHC2_CLK                          236	/* CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */
+#define SC_P_USDHC2_CMD                          237	/* CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */
+#define SC_P_USDHC2_DATA0                        238	/* CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */
+#define SC_P_USDHC2_DATA1                        239	/* CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */
+#define SC_P_USDHC2_DATA2                        240	/* CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */
+#define SC_P_USDHC2_DATA3                        241	/* CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         242	/*  */
+#define SC_P_ENET0_RGMII_TXC                     243	/* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */
+#define SC_P_ENET0_RGMII_TX_CTL                  244	/* CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */
+#define SC_P_ENET0_RGMII_TXD0                    245	/* CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */
+#define SC_P_ENET0_RGMII_TXD1                    246	/* CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */
+#define SC_P_ENET0_RGMII_TXD2                    247	/* CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */
+#define SC_P_ENET0_RGMII_TXD3                    248	/* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
+#define SC_P_ENET0_RGMII_RXC                     249	/* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
+#define SC_P_ENET0_RGMII_RX_CTL                  250	/* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */
+#define SC_P_ENET0_RGMII_RXD0                    251	/* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
+#define SC_P_ENET0_RGMII_RXD1                    252	/* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
+#define SC_P_ENET0_RGMII_RXD2                    253	/* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
+#define SC_P_ENET0_RGMII_RXD3                    254	/* CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB    255	/*  */
+#define SC_P_ENET1_RGMII_TXC                     256	/* CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */
+#define SC_P_ENET1_RGMII_TX_CTL                  257	/* CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */
+#define SC_P_ENET1_RGMII_TXD0                    258	/* CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */
+#define SC_P_ENET1_RGMII_TXD1                    259	/* CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */
+#define SC_P_ENET1_RGMII_TXD2                    260	/* CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */
+#define SC_P_ENET1_RGMII_TXD3                    261	/* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
+#define SC_P_ENET1_RGMII_RXC                     262	/* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
+#define SC_P_ENET1_RGMII_RX_CTL                  263	/* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */
+#define SC_P_ENET1_RGMII_RXD0                    264	/* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
+#define SC_P_ENET1_RGMII_RXD1                    265	/* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
+#define SC_P_ENET1_RGMII_RXD2                    266	/* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
+#define SC_P_ENET1_RGMII_RXD3                    267	/* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA    268	/*  */
+/*@}*/
+
+/*!
+ * @name Pad Mux Definitions
+ * format: name padid padmux
+ */
+/*@{*/
+#define SC_P_SIM0_CLK_DMA_SIM0_CLK                              SC_P_SIM0_CLK                      0
+#define SC_P_SIM0_CLK_LSIO_GPIO0_IO00                           SC_P_SIM0_CLK                      3
+#define SC_P_SIM0_RST_DMA_SIM0_RST                              SC_P_SIM0_RST                      0
+#define SC_P_SIM0_RST_LSIO_GPIO0_IO01                           SC_P_SIM0_RST                      3
+#define SC_P_SIM0_IO_DMA_SIM0_IO                                SC_P_SIM0_IO                       0
+#define SC_P_SIM0_IO_LSIO_GPIO0_IO02                            SC_P_SIM0_IO                       3
+#define SC_P_SIM0_PD_DMA_SIM0_PD                                SC_P_SIM0_PD                       0
+#define SC_P_SIM0_PD_DMA_I2C3_SCL                               SC_P_SIM0_PD                       1
+#define SC_P_SIM0_PD_LSIO_GPIO0_IO03                            SC_P_SIM0_PD                       3
+#define SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN                    SC_P_SIM0_POWER_EN                 0
+#define SC_P_SIM0_POWER_EN_DMA_I2C3_SDA                         SC_P_SIM0_POWER_EN                 1
+#define SC_P_SIM0_POWER_EN_LSIO_GPIO0_IO04                      SC_P_SIM0_POWER_EN                 3
+#define SC_P_SIM0_GPIO0_00_DMA_SIM0_POWER_EN                    SC_P_SIM0_GPIO0_00                 0
+#define SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05                      SC_P_SIM0_GPIO0_00                 3
+#define SC_P_M40_I2C0_SCL_M40_I2C0_SCL                          SC_P_M40_I2C0_SCL                  0
+#define SC_P_M40_I2C0_SCL_M40_UART0_RX                          SC_P_M40_I2C0_SCL                  1
+#define SC_P_M40_I2C0_SCL_M40_GPIO0_IO02                        SC_P_M40_I2C0_SCL                  2
+#define SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06                       SC_P_M40_I2C0_SCL                  3
+#define SC_P_M40_I2C0_SDA_M40_I2C0_SDA                          SC_P_M40_I2C0_SDA                  0
+#define SC_P_M40_I2C0_SDA_M40_UART0_TX                          SC_P_M40_I2C0_SDA                  1
+#define SC_P_M40_I2C0_SDA_M40_GPIO0_IO03                        SC_P_M40_I2C0_SDA                  2
+#define SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07                       SC_P_M40_I2C0_SDA                  3
+#define SC_P_M40_GPIO0_00_M40_GPIO0_IO00                        SC_P_M40_GPIO0_00                  0
+#define SC_P_M40_GPIO0_00_M40_TPM0_CH0                          SC_P_M40_GPIO0_00                  1
+#define SC_P_M40_GPIO0_00_DMA_UART4_RX                          SC_P_M40_GPIO0_00                  2
+#define SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08                       SC_P_M40_GPIO0_00                  3
+#define SC_P_M40_GPIO0_01_M40_GPIO0_IO01                        SC_P_M40_GPIO0_01                  0
+#define SC_P_M40_GPIO0_01_M40_TPM0_CH1                          SC_P_M40_GPIO0_01                  1
+#define SC_P_M40_GPIO0_01_DMA_UART4_TX                          SC_P_M40_GPIO0_01                  2
+#define SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09                       SC_P_M40_GPIO0_01                  3
+#define SC_P_M41_I2C0_SCL_M41_I2C0_SCL                          SC_P_M41_I2C0_SCL                  0
+#define SC_P_M41_I2C0_SCL_M41_UART0_RX                          SC_P_M41_I2C0_SCL                  1
+#define SC_P_M41_I2C0_SCL_M41_GPIO0_IO02                        SC_P_M41_I2C0_SCL                  2
+#define SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10                       SC_P_M41_I2C0_SCL                  3
+#define SC_P_M41_I2C0_SDA_M41_I2C0_SDA                          SC_P_M41_I2C0_SDA                  0
+#define SC_P_M41_I2C0_SDA_M41_UART0_TX                          SC_P_M41_I2C0_SDA                  1
+#define SC_P_M41_I2C0_SDA_M41_GPIO0_IO03                        SC_P_M41_I2C0_SDA                  2
+#define SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11                       SC_P_M41_I2C0_SDA                  3
+#define SC_P_M41_GPIO0_00_M41_GPIO0_IO00                        SC_P_M41_GPIO0_00                  0
+#define SC_P_M41_GPIO0_00_M41_TPM0_CH0                          SC_P_M41_GPIO0_00                  1
+#define SC_P_M41_GPIO0_00_DMA_UART3_RX                          SC_P_M41_GPIO0_00                  2
+#define SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12                       SC_P_M41_GPIO0_00                  3
+#define SC_P_M41_GPIO0_01_M41_GPIO0_IO01                        SC_P_M41_GPIO0_01                  0
+#define SC_P_M41_GPIO0_01_M41_TPM0_CH1                          SC_P_M41_GPIO0_01                  1
+#define SC_P_M41_GPIO0_01_DMA_UART3_TX                          SC_P_M41_GPIO0_01                  2
+#define SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13                       SC_P_M41_GPIO0_01                  3
+#define SC_P_GPT0_CLK_LSIO_GPT0_CLK                             SC_P_GPT0_CLK                      0
+#define SC_P_GPT0_CLK_DMA_I2C1_SCL                              SC_P_GPT0_CLK                      1
+#define SC_P_GPT0_CLK_LSIO_KPP0_COL4                            SC_P_GPT0_CLK                      2
+#define SC_P_GPT0_CLK_LSIO_GPIO0_IO14                           SC_P_GPT0_CLK                      3
+#define SC_P_GPT0_CAPTURE_LSIO_GPT0_CAPTURE                     SC_P_GPT0_CAPTURE                  0
+#define SC_P_GPT0_CAPTURE_DMA_I2C1_SDA                          SC_P_GPT0_CAPTURE                  1
+#define SC_P_GPT0_CAPTURE_LSIO_KPP0_COL5                        SC_P_GPT0_CAPTURE                  2
+#define SC_P_GPT0_CAPTURE_LSIO_GPIO0_IO15                       SC_P_GPT0_CAPTURE                  3
+#define SC_P_GPT0_COMPARE_LSIO_GPT0_COMPARE                     SC_P_GPT0_COMPARE                  0
+#define SC_P_GPT0_COMPARE_LSIO_PWM3_OUT                         SC_P_GPT0_COMPARE                  1
+#define SC_P_GPT0_COMPARE_LSIO_KPP0_COL6                        SC_P_GPT0_COMPARE                  2
+#define SC_P_GPT0_COMPARE_LSIO_GPIO0_IO16                       SC_P_GPT0_COMPARE                  3
+#define SC_P_GPT1_CLK_LSIO_GPT1_CLK                             SC_P_GPT1_CLK                      0
+#define SC_P_GPT1_CLK_DMA_I2C2_SCL                              SC_P_GPT1_CLK                      1
+#define SC_P_GPT1_CLK_LSIO_KPP0_COL7                            SC_P_GPT1_CLK                      2
+#define SC_P_GPT1_CLK_LSIO_GPIO0_IO17                           SC_P_GPT1_CLK                      3
+#define SC_P_GPT1_CAPTURE_LSIO_GPT1_CAPTURE                     SC_P_GPT1_CAPTURE                  0
+#define SC_P_GPT1_CAPTURE_DMA_I2C2_SDA                          SC_P_GPT1_CAPTURE                  1
+#define SC_P_GPT1_CAPTURE_LSIO_KPP0_ROW4                        SC_P_GPT1_CAPTURE                  2
+#define SC_P_GPT1_CAPTURE_LSIO_GPIO0_IO18                       SC_P_GPT1_CAPTURE                  3
+#define SC_P_GPT1_COMPARE_LSIO_GPT1_COMPARE                     SC_P_GPT1_COMPARE                  0
+#define SC_P_GPT1_COMPARE_LSIO_PWM2_OUT                         SC_P_GPT1_COMPARE                  1
+#define SC_P_GPT1_COMPARE_LSIO_KPP0_ROW5                        SC_P_GPT1_COMPARE                  2
+#define SC_P_GPT1_COMPARE_LSIO_GPIO0_IO19                       SC_P_GPT1_COMPARE                  3
+#define SC_P_UART0_RX_DMA_UART0_RX                              SC_P_UART0_RX                      0
+#define SC_P_UART0_RX_SCU_UART0_RX                              SC_P_UART0_RX                      1
+#define SC_P_UART0_RX_LSIO_GPIO0_IO20                           SC_P_UART0_RX                      3
+#define SC_P_UART0_TX_DMA_UART0_TX                              SC_P_UART0_TX                      0
+#define SC_P_UART0_TX_SCU_UART0_TX                              SC_P_UART0_TX                      1
+#define SC_P_UART0_TX_LSIO_GPIO0_IO21                           SC_P_UART0_TX                      3
+#define SC_P_UART0_RTS_B_DMA_UART0_RTS_B                        SC_P_UART0_RTS_B                   0
+#define SC_P_UART0_RTS_B_LSIO_PWM0_OUT                          SC_P_UART0_RTS_B                   1
+#define SC_P_UART0_RTS_B_DMA_UART2_RX                           SC_P_UART0_RTS_B                   2
+#define SC_P_UART0_RTS_B_LSIO_GPIO0_IO22                        SC_P_UART0_RTS_B                   3
+#define SC_P_UART0_CTS_B_DMA_UART0_CTS_B                        SC_P_UART0_CTS_B                   0
+#define SC_P_UART0_CTS_B_LSIO_PWM1_OUT                          SC_P_UART0_CTS_B                   1
+#define SC_P_UART0_CTS_B_DMA_UART2_TX                           SC_P_UART0_CTS_B                   2
+#define SC_P_UART0_CTS_B_LSIO_GPIO0_IO23                        SC_P_UART0_CTS_B                   3
+#define SC_P_UART1_TX_DMA_UART1_TX                              SC_P_UART1_TX                      0
+#define SC_P_UART1_TX_DMA_SPI3_SCK                              SC_P_UART1_TX                      1
+#define SC_P_UART1_TX_LSIO_GPIO0_IO24                           SC_P_UART1_TX                      3
+#define SC_P_UART1_RX_DMA_UART1_RX                              SC_P_UART1_RX                      0
+#define SC_P_UART1_RX_DMA_SPI3_SDO                              SC_P_UART1_RX                      1
+#define SC_P_UART1_RX_LSIO_GPIO0_IO25                           SC_P_UART1_RX                      3
+#define SC_P_UART1_RTS_B_DMA_UART1_RTS_B                        SC_P_UART1_RTS_B                   0
+#define SC_P_UART1_RTS_B_DMA_SPI3_SDI                           SC_P_UART1_RTS_B                   1
+#define SC_P_UART1_RTS_B_DMA_UART1_CTS_B                        SC_P_UART1_RTS_B                   2
+#define SC_P_UART1_RTS_B_LSIO_GPIO0_IO26                        SC_P_UART1_RTS_B                   3
+#define SC_P_UART1_CTS_B_DMA_UART1_CTS_B                        SC_P_UART1_CTS_B                   0
+#define SC_P_UART1_CTS_B_DMA_SPI3_CS0                           SC_P_UART1_CTS_B                   1
+#define SC_P_UART1_CTS_B_DMA_UART1_RTS_B                        SC_P_UART1_CTS_B                   2
+#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO27                        SC_P_UART1_CTS_B                   3
+#define SC_P_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON       SC_P_SCU_PMIC_MEMC_ON              0
+#define SC_P_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT                    SC_P_SCU_WDOG_OUT                  0
+#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA                      SC_P_PMIC_I2C_SDA                  0
+#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL                      SC_P_PMIC_I2C_SCL                  0
+#define SC_P_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING          SC_P_PMIC_EARLY_WARNING            0
+#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B                      SC_P_PMIC_INT_B                    0
+#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00                        SC_P_SCU_GPIO0_00                  0
+#define SC_P_SCU_GPIO0_00_SCU_UART0_RX                          SC_P_SCU_GPIO0_00                  1
+#define SC_P_SCU_GPIO0_00_LSIO_GPIO0_IO28                       SC_P_SCU_GPIO0_00                  3
+#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01                        SC_P_SCU_GPIO0_01                  0
+#define SC_P_SCU_GPIO0_01_SCU_UART0_TX                          SC_P_SCU_GPIO0_01                  1
+#define SC_P_SCU_GPIO0_01_LSIO_GPIO0_IO29                       SC_P_SCU_GPIO0_01                  3
+#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IO02                        SC_P_SCU_GPIO0_02                  0
+#define SC_P_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON           SC_P_SCU_GPIO0_02                  1
+#define SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30                       SC_P_SCU_GPIO0_02                  3
+#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IO03                        SC_P_SCU_GPIO0_03                  0
+#define SC_P_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON           SC_P_SCU_GPIO0_03                  1
+#define SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31                       SC_P_SCU_GPIO0_03                  3
+#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IO04                        SC_P_SCU_GPIO0_04                  0
+#define SC_P_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON            SC_P_SCU_GPIO0_04                  1
+#define SC_P_SCU_GPIO0_04_LSIO_GPIO1_IO00                       SC_P_SCU_GPIO0_04                  3
+#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IO05                        SC_P_SCU_GPIO0_05                  0
+#define SC_P_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON            SC_P_SCU_GPIO0_05                  1
+#define SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01                       SC_P_SCU_GPIO0_05                  3
+#define SC_P_SCU_GPIO0_06_SCU_GPIO0_IO06                        SC_P_SCU_GPIO0_06                  0
+#define SC_P_SCU_GPIO0_06_SCU_TPM0_CH0                          SC_P_SCU_GPIO0_06                  1
+#define SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02                       SC_P_SCU_GPIO0_06                  3
+#define SC_P_SCU_GPIO0_07_SCU_GPIO0_IO07                        SC_P_SCU_GPIO0_07                  0
+#define SC_P_SCU_GPIO0_07_SCU_TPM0_CH1                          SC_P_SCU_GPIO0_07                  1
+#define SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K          SC_P_SCU_GPIO0_07                  2
+#define SC_P_SCU_GPIO0_07_LSIO_GPIO1_IO03                       SC_P_SCU_GPIO0_07                  3
+#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0                  SC_P_SCU_BOOT_MODE0                0
+#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1                  SC_P_SCU_BOOT_MODE1                0
+#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2                  SC_P_SCU_BOOT_MODE2                0
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3                  SC_P_SCU_BOOT_MODE3                0
+#define SC_P_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4                  SC_P_SCU_BOOT_MODE4                0
+#define SC_P_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL                    SC_P_SCU_BOOT_MODE4                1
+#define SC_P_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5                  SC_P_SCU_BOOT_MODE5                0
+#define SC_P_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA                    SC_P_SCU_BOOT_MODE5                1
+#define SC_P_LVDS0_GPIO00_LVDS0_GPIO0_IO00                      SC_P_LVDS0_GPIO00                  0
+#define SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT                        SC_P_LVDS0_GPIO00                  1
+#define SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04                       SC_P_LVDS0_GPIO00                  3
+#define SC_P_LVDS0_GPIO01_LVDS0_GPIO0_IO01                      SC_P_LVDS0_GPIO01                  0
+#define SC_P_LVDS0_GPIO01_LSIO_GPIO1_IO05                       SC_P_LVDS0_GPIO01                  3
+#define SC_P_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL                      SC_P_LVDS0_I2C0_SCL                0
+#define SC_P_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02                    SC_P_LVDS0_I2C0_SCL                1
+#define SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06                     SC_P_LVDS0_I2C0_SCL                3
+#define SC_P_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA                      SC_P_LVDS0_I2C0_SDA                0
+#define SC_P_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03                    SC_P_LVDS0_I2C0_SDA                1
+#define SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07                     SC_P_LVDS0_I2C0_SDA                3
+#define SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL                      SC_P_LVDS0_I2C1_SCL                0
+#define SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX                        SC_P_LVDS0_I2C1_SCL                1
+#define SC_P_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08                     SC_P_LVDS0_I2C1_SCL                3
+#define SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA                      SC_P_LVDS0_I2C1_SDA                0
+#define SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX                        SC_P_LVDS0_I2C1_SDA                1
+#define SC_P_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09                     SC_P_LVDS0_I2C1_SDA                3
+#define SC_P_LVDS1_GPIO00_LVDS1_GPIO0_IO00                      SC_P_LVDS1_GPIO00                  0
+#define SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT                        SC_P_LVDS1_GPIO00                  1
+#define SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10                       SC_P_LVDS1_GPIO00                  3
+#define SC_P_LVDS1_GPIO01_LVDS1_GPIO0_IO01                      SC_P_LVDS1_GPIO01                  0
+#define SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11                       SC_P_LVDS1_GPIO01                  3
+#define SC_P_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL                      SC_P_LVDS1_I2C0_SCL                0
+#define SC_P_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02                    SC_P_LVDS1_I2C0_SCL                1
+#define SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12                     SC_P_LVDS1_I2C0_SCL                3
+#define SC_P_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA                      SC_P_LVDS1_I2C0_SDA                0
+#define SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03                    SC_P_LVDS1_I2C0_SDA                1
+#define SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13                     SC_P_LVDS1_I2C0_SDA                3
+#define SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL                      SC_P_LVDS1_I2C1_SCL                0
+#define SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX                        SC_P_LVDS1_I2C1_SCL                1
+#define SC_P_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14                     SC_P_LVDS1_I2C1_SCL                3
+#define SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA                      SC_P_LVDS1_I2C1_SDA                0
+#define SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX                        SC_P_LVDS1_I2C1_SDA                1
+#define SC_P_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15                     SC_P_LVDS1_I2C1_SDA                3
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL              SC_P_MIPI_DSI0_I2C0_SCL            0
+#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16                 SC_P_MIPI_DSI0_I2C0_SCL            3
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA              SC_P_MIPI_DSI0_I2C0_SDA            0
+#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17                 SC_P_MIPI_DSI0_I2C0_SDA            3
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00            SC_P_MIPI_DSI0_GPIO0_00            0
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT              SC_P_MIPI_DSI0_GPIO0_00            1
+#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18                 SC_P_MIPI_DSI0_GPIO0_00            3
+#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01            SC_P_MIPI_DSI0_GPIO0_01            0
+#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19                 SC_P_MIPI_DSI0_GPIO0_01            3
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL              SC_P_MIPI_DSI1_I2C0_SCL            0
+#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20                 SC_P_MIPI_DSI1_I2C0_SCL            3
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA              SC_P_MIPI_DSI1_I2C0_SDA            0
+#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21                 SC_P_MIPI_DSI1_I2C0_SDA            3
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00            SC_P_MIPI_DSI1_GPIO0_00            0
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT              SC_P_MIPI_DSI1_GPIO0_00            1
+#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22                 SC_P_MIPI_DSI1_GPIO0_00            3
+#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01            SC_P_MIPI_DSI1_GPIO0_01            0
+#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23                 SC_P_MIPI_DSI1_GPIO0_01            3
+#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT          SC_P_MIPI_CSI0_MCLK_OUT            0
+#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24                 SC_P_MIPI_CSI0_MCLK_OUT            3
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL              SC_P_MIPI_CSI0_I2C0_SCL            0
+#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25                 SC_P_MIPI_CSI0_I2C0_SCL            3
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA              SC_P_MIPI_CSI0_I2C0_SDA            0
+#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26                 SC_P_MIPI_CSI0_I2C0_SDA            3
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00            SC_P_MIPI_CSI0_GPIO0_00            0
+#define SC_P_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL                    SC_P_MIPI_CSI0_GPIO0_00            1
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL              SC_P_MIPI_CSI0_GPIO0_00            2
+#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27                 SC_P_MIPI_CSI0_GPIO0_00            3
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01            SC_P_MIPI_CSI0_GPIO0_01            0
+#define SC_P_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA                    SC_P_MIPI_CSI0_GPIO0_01            1
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA              SC_P_MIPI_CSI0_GPIO0_01            2
+#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28                 SC_P_MIPI_CSI0_GPIO0_01            3
+#define SC_P_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT          SC_P_MIPI_CSI1_MCLK_OUT            0
+#define SC_P_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29                 SC_P_MIPI_CSI1_MCLK_OUT            3
+#define SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00            SC_P_MIPI_CSI1_GPIO0_00            0
+#define SC_P_MIPI_CSI1_GPIO0_00_DMA_UART4_RX                    SC_P_MIPI_CSI1_GPIO0_00            1
+#define SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30                 SC_P_MIPI_CSI1_GPIO0_00            3
+#define SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01            SC_P_MIPI_CSI1_GPIO0_01            0
+#define SC_P_MIPI_CSI1_GPIO0_01_DMA_UART4_TX                    SC_P_MIPI_CSI1_GPIO0_01            1
+#define SC_P_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31                 SC_P_MIPI_CSI1_GPIO0_01            3
+#define SC_P_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL              SC_P_MIPI_CSI1_I2C0_SCL            0
+#define SC_P_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00                 SC_P_MIPI_CSI1_I2C0_SCL            3
+#define SC_P_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA              SC_P_MIPI_CSI1_I2C0_SDA            0
+#define SC_P_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01                 SC_P_MIPI_CSI1_I2C0_SDA            3
+#define SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL                  SC_P_HDMI_TX0_TS_SCL               0
+#define SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL                       SC_P_HDMI_TX0_TS_SCL               1
+#define SC_P_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02                    SC_P_HDMI_TX0_TS_SCL               3
+#define SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA                  SC_P_HDMI_TX0_TS_SDA               0
+#define SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA                       SC_P_HDMI_TX0_TS_SDA               1
+#define SC_P_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03                    SC_P_HDMI_TX0_TS_SDA               3
+#define SC_P_ESAI1_FSR_AUD_ESAI1_FSR                            SC_P_ESAI1_FSR                     0
+#define SC_P_ESAI1_FSR_LSIO_GPIO2_IO04                          SC_P_ESAI1_FSR                     3
+#define SC_P_ESAI1_FST_AUD_ESAI1_FST                            SC_P_ESAI1_FST                     0
+#define SC_P_ESAI1_FST_AUD_SPDIF0_EXT_CLK                       SC_P_ESAI1_FST                     1
+#define SC_P_ESAI1_FST_LSIO_GPIO2_IO05                          SC_P_ESAI1_FST                     3
+#define SC_P_ESAI1_SCKR_AUD_ESAI1_SCKR                          SC_P_ESAI1_SCKR                    0
+#define SC_P_ESAI1_SCKR_LSIO_GPIO2_IO06                         SC_P_ESAI1_SCKR                    3
+#define SC_P_ESAI1_SCKT_AUD_ESAI1_SCKT                          SC_P_ESAI1_SCKT                    0
+#define SC_P_ESAI1_SCKT_AUD_SAI2_RXC                            SC_P_ESAI1_SCKT                    1
+#define SC_P_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK                      SC_P_ESAI1_SCKT                    2
+#define SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07                         SC_P_ESAI1_SCKT                    3
+#define SC_P_ESAI1_TX0_AUD_ESAI1_TX0                            SC_P_ESAI1_TX0                     0
+#define SC_P_ESAI1_TX0_AUD_SAI2_RXD                             SC_P_ESAI1_TX0                     1
+#define SC_P_ESAI1_TX0_AUD_SPDIF0_RX                            SC_P_ESAI1_TX0                     2
+#define SC_P_ESAI1_TX0_LSIO_GPIO2_IO08                          SC_P_ESAI1_TX0                     3
+#define SC_P_ESAI1_TX1_AUD_ESAI1_TX1                            SC_P_ESAI1_TX1                     0
+#define SC_P_ESAI1_TX1_AUD_SAI2_RXFS                            SC_P_ESAI1_TX1                     1
+#define SC_P_ESAI1_TX1_AUD_SPDIF0_TX                            SC_P_ESAI1_TX1                     2
+#define SC_P_ESAI1_TX1_LSIO_GPIO2_IO09                          SC_P_ESAI1_TX1                     3
+#define SC_P_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3                    SC_P_ESAI1_TX2_RX3                 0
+#define SC_P_ESAI1_TX2_RX3_AUD_SPDIF0_RX                        SC_P_ESAI1_TX2_RX3                 1
+#define SC_P_ESAI1_TX2_RX3_LSIO_GPIO2_IO10                      SC_P_ESAI1_TX2_RX3                 3
+#define SC_P_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2                    SC_P_ESAI1_TX3_RX2                 0
+#define SC_P_ESAI1_TX3_RX2_AUD_SPDIF0_TX                        SC_P_ESAI1_TX3_RX2                 1
+#define SC_P_ESAI1_TX3_RX2_LSIO_GPIO2_IO11                      SC_P_ESAI1_TX3_RX2                 3
+#define SC_P_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1                    SC_P_ESAI1_TX4_RX1                 0
+#define SC_P_ESAI1_TX4_RX1_LSIO_GPIO2_IO12                      SC_P_ESAI1_TX4_RX1                 3
+#define SC_P_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0                    SC_P_ESAI1_TX5_RX0                 0
+#define SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13                      SC_P_ESAI1_TX5_RX0                 3
+#define SC_P_SPDIF0_RX_AUD_SPDIF0_RX                            SC_P_SPDIF0_RX                     0
+#define SC_P_SPDIF0_RX_AUD_MQS_R                                SC_P_SPDIF0_RX                     1
+#define SC_P_SPDIF0_RX_AUD_ACM_MCLK_IN1                         SC_P_SPDIF0_RX                     2
+#define SC_P_SPDIF0_RX_LSIO_GPIO2_IO14                          SC_P_SPDIF0_RX                     3
+#define SC_P_SPDIF0_TX_AUD_SPDIF0_TX                            SC_P_SPDIF0_TX                     0
+#define SC_P_SPDIF0_TX_AUD_MQS_L                                SC_P_SPDIF0_TX                     1
+#define SC_P_SPDIF0_TX_AUD_ACM_MCLK_OUT1                        SC_P_SPDIF0_TX                     2
+#define SC_P_SPDIF0_TX_LSIO_GPIO2_IO15                          SC_P_SPDIF0_TX                     3
+#define SC_P_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK                  SC_P_SPDIF0_EXT_CLK                0
+#define SC_P_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0                    SC_P_SPDIF0_EXT_CLK                1
+#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16                     SC_P_SPDIF0_EXT_CLK                3
+#define SC_P_SPI3_SCK_DMA_SPI3_SCK                              SC_P_SPI3_SCK                      0
+#define SC_P_SPI3_SCK_LSIO_GPIO2_IO17                           SC_P_SPI3_SCK                      3
+#define SC_P_SPI3_SDO_DMA_SPI3_SDO                              SC_P_SPI3_SDO                      0
+#define SC_P_SPI3_SDO_DMA_FTM_CH0                               SC_P_SPI3_SDO                      1
+#define SC_P_SPI3_SDO_LSIO_GPIO2_IO18                           SC_P_SPI3_SDO                      3
+#define SC_P_SPI3_SDI_DMA_SPI3_SDI                              SC_P_SPI3_SDI                      0
+#define SC_P_SPI3_SDI_DMA_FTM_CH1                               SC_P_SPI3_SDI                      1
+#define SC_P_SPI3_SDI_LSIO_GPIO2_IO19                           SC_P_SPI3_SDI                      3
+#define SC_P_SPI3_CS0_DMA_SPI3_CS0                              SC_P_SPI3_CS0                      0
+#define SC_P_SPI3_CS0_DMA_FTM_CH2                               SC_P_SPI3_CS0                      1
+#define SC_P_SPI3_CS0_LSIO_GPIO2_IO20                           SC_P_SPI3_CS0                      3
+#define SC_P_SPI3_CS1_DMA_SPI3_CS1                              SC_P_SPI3_CS1                      0
+#define SC_P_SPI3_CS1_LSIO_GPIO2_IO21                           SC_P_SPI3_CS1                      3
+#define SC_P_ESAI0_FSR_AUD_ESAI0_FSR                            SC_P_ESAI0_FSR                     0
+#define SC_P_ESAI0_FSR_LSIO_GPIO2_IO22                          SC_P_ESAI0_FSR                     3
+#define SC_P_ESAI0_FST_AUD_ESAI0_FST                            SC_P_ESAI0_FST                     0
+#define SC_P_ESAI0_FST_LSIO_GPIO2_IO23                          SC_P_ESAI0_FST                     3
+#define SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR                          SC_P_ESAI0_SCKR                    0
+#define SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24                         SC_P_ESAI0_SCKR                    3
+#define SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT                          SC_P_ESAI0_SCKT                    0
+#define SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25                         SC_P_ESAI0_SCKT                    3
+#define SC_P_ESAI0_TX0_AUD_ESAI0_TX0                            SC_P_ESAI0_TX0                     0
+#define SC_P_ESAI0_TX0_LSIO_GPIO2_IO26                          SC_P_ESAI0_TX0                     3
+#define SC_P_ESAI0_TX1_AUD_ESAI0_TX1                            SC_P_ESAI0_TX1                     0
+#define SC_P_ESAI0_TX1_LSIO_GPIO2_IO27                          SC_P_ESAI0_TX1                     3
+#define SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3                    SC_P_ESAI0_TX2_RX3                 0
+#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28                      SC_P_ESAI0_TX2_RX3                 3
+#define SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2                    SC_P_ESAI0_TX3_RX2                 0
+#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29                      SC_P_ESAI0_TX3_RX2                 3
+#define SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1                    SC_P_ESAI0_TX4_RX1                 0
+#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30                      SC_P_ESAI0_TX4_RX1                 3
+#define SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0                    SC_P_ESAI0_TX5_RX0                 0
+#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31                      SC_P_ESAI0_TX5_RX0                 3
+#define SC_P_MCLK_IN0_AUD_ACM_MCLK_IN0                          SC_P_MCLK_IN0                      0
+#define SC_P_MCLK_IN0_AUD_ESAI0_RX_HF_CLK                       SC_P_MCLK_IN0                      1
+#define SC_P_MCLK_IN0_AUD_ESAI1_RX_HF_CLK                       SC_P_MCLK_IN0                      2
+#define SC_P_MCLK_IN0_LSIO_GPIO3_IO00                           SC_P_MCLK_IN0                      3
+#define SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0                        SC_P_MCLK_OUT0                     0
+#define SC_P_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK                      SC_P_MCLK_OUT0                     1
+#define SC_P_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK                      SC_P_MCLK_OUT0                     2
+#define SC_P_MCLK_OUT0_LSIO_GPIO3_IO01                          SC_P_MCLK_OUT0                     3
+#define SC_P_SPI0_SCK_DMA_SPI0_SCK                              SC_P_SPI0_SCK                      0
+#define SC_P_SPI0_SCK_AUD_SAI0_RXC                              SC_P_SPI0_SCK                      1
+#define SC_P_SPI0_SCK_LSIO_GPIO3_IO02                           SC_P_SPI0_SCK                      3
+#define SC_P_SPI0_SDO_DMA_SPI0_SDO                              SC_P_SPI0_SDO                      0
+#define SC_P_SPI0_SDO_AUD_SAI0_TXD                              SC_P_SPI0_SDO                      1
+#define SC_P_SPI0_SDO_LSIO_GPIO3_IO03                           SC_P_SPI0_SDO                      3
+#define SC_P_SPI0_SDI_DMA_SPI0_SDI                              SC_P_SPI0_SDI                      0
+#define SC_P_SPI0_SDI_AUD_SAI0_RXD                              SC_P_SPI0_SDI                      1
+#define SC_P_SPI0_SDI_LSIO_GPIO3_IO04                           SC_P_SPI0_SDI                      3
+#define SC_P_SPI0_CS0_DMA_SPI0_CS0                              SC_P_SPI0_CS0                      0
+#define SC_P_SPI0_CS0_AUD_SAI0_RXFS                             SC_P_SPI0_CS0                      1
+#define SC_P_SPI0_CS0_LSIO_GPIO3_IO05                           SC_P_SPI0_CS0                      3
+#define SC_P_SPI0_CS1_DMA_SPI0_CS1                              SC_P_SPI0_CS1                      0
+#define SC_P_SPI0_CS1_AUD_SAI0_TXC                              SC_P_SPI0_CS1                      1
+#define SC_P_SPI0_CS1_LSIO_GPIO3_IO06                           SC_P_SPI0_CS1                      3
+#define SC_P_SPI2_SCK_DMA_SPI2_SCK                              SC_P_SPI2_SCK                      0
+#define SC_P_SPI2_SCK_LSIO_GPIO3_IO07                           SC_P_SPI2_SCK                      3
+#define SC_P_SPI2_SDO_DMA_SPI2_SDO                              SC_P_SPI2_SDO                      0
+#define SC_P_SPI2_SDO_LSIO_GPIO3_IO08                           SC_P_SPI2_SDO                      3
+#define SC_P_SPI2_SDI_DMA_SPI2_SDI                              SC_P_SPI2_SDI                      0
+#define SC_P_SPI2_SDI_LSIO_GPIO3_IO09                           SC_P_SPI2_SDI                      3
+#define SC_P_SPI2_CS0_DMA_SPI2_CS0                              SC_P_SPI2_CS0                      0
+#define SC_P_SPI2_CS0_LSIO_GPIO3_IO10                           SC_P_SPI2_CS0                      3
+#define SC_P_SPI2_CS1_DMA_SPI2_CS1                              SC_P_SPI2_CS1                      0
+#define SC_P_SPI2_CS1_AUD_SAI0_TXFS                             SC_P_SPI2_CS1                      1
+#define SC_P_SPI2_CS1_LSIO_GPIO3_IO11                           SC_P_SPI2_CS1                      3
+#define SC_P_SAI1_RXC_AUD_SAI1_RXC                              SC_P_SAI1_RXC                      0
+#define SC_P_SAI1_RXC_AUD_SAI0_TXD                              SC_P_SAI1_RXC                      1
+#define SC_P_SAI1_RXC_LSIO_GPIO3_IO12                           SC_P_SAI1_RXC                      3
+#define SC_P_SAI1_RXD_AUD_SAI1_RXD                              SC_P_SAI1_RXD                      0
+#define SC_P_SAI1_RXD_AUD_SAI0_TXFS                             SC_P_SAI1_RXD                      1
+#define SC_P_SAI1_RXD_LSIO_GPIO3_IO13                           SC_P_SAI1_RXD                      3
+#define SC_P_SAI1_RXFS_AUD_SAI1_RXFS                            SC_P_SAI1_RXFS                     0
+#define SC_P_SAI1_RXFS_AUD_SAI0_RXD                             SC_P_SAI1_RXFS                     1
+#define SC_P_SAI1_RXFS_LSIO_GPIO3_IO14                          SC_P_SAI1_RXFS                     3
+#define SC_P_SAI1_TXC_AUD_SAI1_TXC                              SC_P_SAI1_TXC                      0
+#define SC_P_SAI1_TXC_AUD_SAI0_TXC                              SC_P_SAI1_TXC                      1
+#define SC_P_SAI1_TXC_LSIO_GPIO3_IO15                           SC_P_SAI1_TXC                      3
+#define SC_P_SAI1_TXD_AUD_SAI1_TXD                              SC_P_SAI1_TXD                      0
+#define SC_P_SAI1_TXD_AUD_SAI1_RXC                              SC_P_SAI1_TXD                      1
+#define SC_P_SAI1_TXD_LSIO_GPIO3_IO16                           SC_P_SAI1_TXD                      3
+#define SC_P_SAI1_TXFS_AUD_SAI1_TXFS                            SC_P_SAI1_TXFS                     0
+#define SC_P_SAI1_TXFS_AUD_SAI1_RXFS                            SC_P_SAI1_TXFS                     1
+#define SC_P_SAI1_TXFS_LSIO_GPIO3_IO17                          SC_P_SAI1_TXFS                     3
+#define SC_P_ADC_IN7_DMA_ADC1_IN3                               SC_P_ADC_IN7                       0
+#define SC_P_ADC_IN7_DMA_SPI1_CS1                               SC_P_ADC_IN7                       1
+#define SC_P_ADC_IN7_LSIO_KPP0_ROW3                             SC_P_ADC_IN7                       2
+#define SC_P_ADC_IN7_LSIO_GPIO3_IO25                            SC_P_ADC_IN7                       3
+#define SC_P_ADC_IN6_DMA_ADC1_IN2                               SC_P_ADC_IN6                       0
+#define SC_P_ADC_IN6_DMA_SPI1_CS0                               SC_P_ADC_IN6                       1
+#define SC_P_ADC_IN6_LSIO_KPP0_ROW2                             SC_P_ADC_IN6                       2
+#define SC_P_ADC_IN6_LSIO_GPIO3_IO24                            SC_P_ADC_IN6                       3
+#define SC_P_ADC_IN5_DMA_ADC1_IN1                               SC_P_ADC_IN5                       0
+#define SC_P_ADC_IN5_DMA_SPI1_SDI                               SC_P_ADC_IN5                       1
+#define SC_P_ADC_IN5_LSIO_KPP0_ROW1                             SC_P_ADC_IN5                       2
+#define SC_P_ADC_IN5_LSIO_GPIO3_IO23                            SC_P_ADC_IN5                       3
+#define SC_P_ADC_IN4_DMA_ADC1_IN0                               SC_P_ADC_IN4                       0
+#define SC_P_ADC_IN4_DMA_SPI1_SDO                               SC_P_ADC_IN4                       1
+#define SC_P_ADC_IN4_LSIO_KPP0_ROW0                             SC_P_ADC_IN4                       2
+#define SC_P_ADC_IN4_LSIO_GPIO3_IO22                            SC_P_ADC_IN4                       3
+#define SC_P_ADC_IN3_DMA_ADC0_IN3                               SC_P_ADC_IN3                       0
+#define SC_P_ADC_IN3_DMA_SPI1_SCK                               SC_P_ADC_IN3                       1
+#define SC_P_ADC_IN3_LSIO_KPP0_COL3                             SC_P_ADC_IN3                       2
+#define SC_P_ADC_IN3_LSIO_GPIO3_IO21                            SC_P_ADC_IN3                       3
+#define SC_P_ADC_IN2_DMA_ADC0_IN2                               SC_P_ADC_IN2                       0
+#define SC_P_ADC_IN2_LSIO_KPP0_COL2                             SC_P_ADC_IN2                       2
+#define SC_P_ADC_IN2_LSIO_GPIO3_IO20                            SC_P_ADC_IN2                       3
+#define SC_P_ADC_IN1_DMA_ADC0_IN1                               SC_P_ADC_IN1                       0
+#define SC_P_ADC_IN1_LSIO_KPP0_COL1                             SC_P_ADC_IN1                       2
+#define SC_P_ADC_IN1_LSIO_GPIO3_IO19                            SC_P_ADC_IN1                       3
+#define SC_P_ADC_IN0_DMA_ADC0_IN0                               SC_P_ADC_IN0                       0
+#define SC_P_ADC_IN0_LSIO_KPP0_COL0                             SC_P_ADC_IN0                       2
+#define SC_P_ADC_IN0_LSIO_GPIO3_IO18                            SC_P_ADC_IN0                       3
+#define SC_P_MLB_SIG_CONN_MLB_SIG                               SC_P_MLB_SIG                       0
+#define SC_P_MLB_SIG_AUD_SAI3_RXC                               SC_P_MLB_SIG                       1
+#define SC_P_MLB_SIG_LSIO_GPIO3_IO26                            SC_P_MLB_SIG                       3
+#define SC_P_MLB_CLK_CONN_MLB_CLK                               SC_P_MLB_CLK                       0
+#define SC_P_MLB_CLK_AUD_SAI3_RXFS                              SC_P_MLB_CLK                       1
+#define SC_P_MLB_CLK_LSIO_GPIO3_IO27                            SC_P_MLB_CLK                       3
+#define SC_P_MLB_DATA_CONN_MLB_DATA                             SC_P_MLB_DATA                      0
+#define SC_P_MLB_DATA_AUD_SAI3_RXD                              SC_P_MLB_DATA                      1
+#define SC_P_MLB_DATA_LSIO_GPIO3_IO28                           SC_P_MLB_DATA                      3
+#define SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX                        SC_P_FLEXCAN0_RX                   0
+#define SC_P_FLEXCAN0_RX_LSIO_GPIO3_IO29                        SC_P_FLEXCAN0_RX                   3
+#define SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX                        SC_P_FLEXCAN0_TX                   0
+#define SC_P_FLEXCAN0_TX_LSIO_GPIO3_IO30                        SC_P_FLEXCAN0_TX                   3
+#define SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX                        SC_P_FLEXCAN1_RX                   0
+#define SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31                        SC_P_FLEXCAN1_RX                   3
+#define SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX                        SC_P_FLEXCAN1_TX                   0
+#define SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00                        SC_P_FLEXCAN1_TX                   3
+#define SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX                        SC_P_FLEXCAN2_RX                   0
+#define SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01                        SC_P_FLEXCAN2_RX                   3
+#define SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX                        SC_P_FLEXCAN2_TX                   0
+#define SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02                        SC_P_FLEXCAN2_TX                   3
+#define SC_P_USB_SS3_TC0_DMA_I2C1_SCL                           SC_P_USB_SS3_TC0                   0
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR                      SC_P_USB_SS3_TC0                   1
+#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03                        SC_P_USB_SS3_TC0                   3
+#define SC_P_USB_SS3_TC1_DMA_I2C1_SCL                           SC_P_USB_SS3_TC1                   0
+#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR                      SC_P_USB_SS3_TC1                   1
+#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04                        SC_P_USB_SS3_TC1                   3
+#define SC_P_USB_SS3_TC2_DMA_I2C1_SDA                           SC_P_USB_SS3_TC2                   0
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC                       SC_P_USB_SS3_TC2                   1
+#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05                        SC_P_USB_SS3_TC2                   3
+#define SC_P_USB_SS3_TC3_DMA_I2C1_SDA                           SC_P_USB_SS3_TC3                   0
+#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC                       SC_P_USB_SS3_TC3                   1
+#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06                        SC_P_USB_SS3_TC3                   3
+#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B                 SC_P_USDHC1_RESET_B                0
+#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07                     SC_P_USDHC1_RESET_B                3
+#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT                 SC_P_USDHC1_VSELECT                0
+#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08                     SC_P_USDHC1_VSELECT                3
+#define SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B                 SC_P_USDHC2_RESET_B                0
+#define SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09                     SC_P_USDHC2_RESET_B                3
+#define SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT                 SC_P_USDHC2_VSELECT                0
+#define SC_P_USDHC2_VSELECT_LSIO_GPIO4_IO10                     SC_P_USDHC2_VSELECT                3
+#define SC_P_USDHC2_WP_CONN_USDHC2_WP                           SC_P_USDHC2_WP                     0
+#define SC_P_USDHC2_WP_LSIO_GPIO4_IO11                          SC_P_USDHC2_WP                     3
+#define SC_P_USDHC2_CD_B_CONN_USDHC2_CD_B                       SC_P_USDHC2_CD_B                   0
+#define SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12                        SC_P_USDHC2_CD_B                   3
+#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO                         SC_P_ENET0_MDIO                    0
+#define SC_P_ENET0_MDIO_DMA_I2C4_SDA                            SC_P_ENET0_MDIO                    1
+#define SC_P_ENET0_MDIO_LSIO_GPIO4_IO13                         SC_P_ENET0_MDIO                    3
+#define SC_P_ENET0_MDC_CONN_ENET0_MDC                           SC_P_ENET0_MDC                     0
+#define SC_P_ENET0_MDC_DMA_I2C4_SCL                             SC_P_ENET0_MDC                     1
+#define SC_P_ENET0_MDC_LSIO_GPIO4_IO14                          SC_P_ENET0_MDC                     3
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M   SC_P_ENET0_REFCLK_125M_25M         0
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS               SC_P_ENET0_REFCLK_125M_25M         1
+#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15              SC_P_ENET0_REFCLK_125M_25M         3
+#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M   SC_P_ENET1_REFCLK_125M_25M         0
+#define SC_P_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS               SC_P_ENET1_REFCLK_125M_25M         1
+#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16              SC_P_ENET1_REFCLK_125M_25M         3
+#define SC_P_ENET1_MDIO_CONN_ENET1_MDIO                         SC_P_ENET1_MDIO                    0
+#define SC_P_ENET1_MDIO_DMA_I2C4_SDA                            SC_P_ENET1_MDIO                    1
+#define SC_P_ENET1_MDIO_LSIO_GPIO4_IO17                         SC_P_ENET1_MDIO                    3
+#define SC_P_ENET1_MDC_CONN_ENET1_MDC                           SC_P_ENET1_MDC                     0
+#define SC_P_ENET1_MDC_DMA_I2C4_SCL                             SC_P_ENET1_MDC                     1
+#define SC_P_ENET1_MDC_LSIO_GPIO4_IO18                          SC_P_ENET1_MDC                     3
+#define SC_P_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B                     SC_P_QSPI1A_SS0_B                  0
+#define SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19                       SC_P_QSPI1A_SS0_B                  3
+#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B                     SC_P_QSPI1A_SS1_B                  0
+#define SC_P_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2                     SC_P_QSPI1A_SS1_B                  1
+#define SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20                       SC_P_QSPI1A_SS1_B                  3
+#define SC_P_QSPI1A_SCLK_LSIO_QSPI1A_SCLK                       SC_P_QSPI1A_SCLK                   0
+#define SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21                        SC_P_QSPI1A_SCLK                   3
+#define SC_P_QSPI1A_DQS_LSIO_QSPI1A_DQS                         SC_P_QSPI1A_DQS                    0
+#define SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22                         SC_P_QSPI1A_DQS                    3
+#define SC_P_QSPI1A_DATA3_LSIO_QSPI1A_DATA3                     SC_P_QSPI1A_DATA3                  0
+#define SC_P_QSPI1A_DATA3_DMA_I2C1_SDA                          SC_P_QSPI1A_DATA3                  1
+#define SC_P_QSPI1A_DATA3_CONN_USB_OTG1_OC                      SC_P_QSPI1A_DATA3                  2
+#define SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23                       SC_P_QSPI1A_DATA3                  3
+#define SC_P_QSPI1A_DATA2_LSIO_QSPI1A_DATA2                     SC_P_QSPI1A_DATA2                  0
+#define SC_P_QSPI1A_DATA2_DMA_I2C1_SCL                          SC_P_QSPI1A_DATA2                  1
+#define SC_P_QSPI1A_DATA2_CONN_USB_OTG2_PWR                     SC_P_QSPI1A_DATA2                  2
+#define SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24                       SC_P_QSPI1A_DATA2                  3
+#define SC_P_QSPI1A_DATA1_LSIO_QSPI1A_DATA1                     SC_P_QSPI1A_DATA1                  0
+#define SC_P_QSPI1A_DATA1_DMA_I2C1_SDA                          SC_P_QSPI1A_DATA1                  1
+#define SC_P_QSPI1A_DATA1_CONN_USB_OTG2_OC                      SC_P_QSPI1A_DATA1                  2
+#define SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25                       SC_P_QSPI1A_DATA1                  3
+#define SC_P_QSPI1A_DATA0_LSIO_QSPI1A_DATA0                     SC_P_QSPI1A_DATA0                  0
+#define SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26                       SC_P_QSPI1A_DATA0                  3
+#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0                     SC_P_QSPI0A_DATA0                  0
+#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1                     SC_P_QSPI0A_DATA1                  0
+#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2                     SC_P_QSPI0A_DATA2                  0
+#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3                     SC_P_QSPI0A_DATA3                  0
+#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS                         SC_P_QSPI0A_DQS                    0
+#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B                     SC_P_QSPI0A_SS0_B                  0
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B                     SC_P_QSPI0A_SS1_B                  0
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2                     SC_P_QSPI0A_SS1_B                  1
+#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK                       SC_P_QSPI0A_SCLK                   0
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK                       SC_P_QSPI0B_SCLK                   0
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0                     SC_P_QSPI0B_DATA0                  0
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1                     SC_P_QSPI0B_DATA1                  0
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2                     SC_P_QSPI0B_DATA2                  0
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3                     SC_P_QSPI0B_DATA3                  0
+#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS                         SC_P_QSPI0B_DQS                    0
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B                     SC_P_QSPI0B_SS0_B                  0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B                     SC_P_QSPI0B_SS1_B                  0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2                     SC_P_QSPI0B_SS1_B                  1
+#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B            SC_P_PCIE_CTRL0_CLKREQ_B           0
+#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27                SC_P_PCIE_CTRL0_CLKREQ_B           3
+#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B                SC_P_PCIE_CTRL0_WAKE_B             0
+#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28                  SC_P_PCIE_CTRL0_WAKE_B             3
+#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B              SC_P_PCIE_CTRL0_PERST_B            0
+#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29                 SC_P_PCIE_CTRL0_PERST_B            3
+#define SC_P_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B            SC_P_PCIE_CTRL1_CLKREQ_B           0
+#define SC_P_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA                   SC_P_PCIE_CTRL1_CLKREQ_B           1
+#define SC_P_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC               SC_P_PCIE_CTRL1_CLKREQ_B           2
+#define SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30                SC_P_PCIE_CTRL1_CLKREQ_B           3
+#define SC_P_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B                SC_P_PCIE_CTRL1_WAKE_B             0
+#define SC_P_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL                     SC_P_PCIE_CTRL1_WAKE_B             1
+#define SC_P_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR                SC_P_PCIE_CTRL1_WAKE_B             2
+#define SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31                  SC_P_PCIE_CTRL1_WAKE_B             3
+#define SC_P_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B              SC_P_PCIE_CTRL1_PERST_B            0
+#define SC_P_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL                    SC_P_PCIE_CTRL1_PERST_B            1
+#define SC_P_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR               SC_P_PCIE_CTRL1_PERST_B            2
+#define SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00                 SC_P_PCIE_CTRL1_PERST_B            3
+#define SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA                 SC_P_USB_HSIC0_DATA                0
+#define SC_P_USB_HSIC0_DATA_DMA_I2C1_SDA                        SC_P_USB_HSIC0_DATA                1
+#define SC_P_USB_HSIC0_DATA_LSIO_GPIO5_IO01                     SC_P_USB_HSIC0_DATA                3
+#define SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE             SC_P_USB_HSIC0_STROBE              0
+#define SC_P_USB_HSIC0_STROBE_DMA_I2C1_SCL                      SC_P_USB_HSIC0_STROBE              1
+#define SC_P_USB_HSIC0_STROBE_LSIO_GPIO5_IO02                   SC_P_USB_HSIC0_STROBE              3
+#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK                           SC_P_EMMC0_CLK                     0
+#define SC_P_EMMC0_CLK_CONN_NAND_READY_B                        SC_P_EMMC0_CLK                     1
+#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD                           SC_P_EMMC0_CMD                     0
+#define SC_P_EMMC0_CMD_CONN_NAND_DQS                            SC_P_EMMC0_CMD                     1
+#define SC_P_EMMC0_CMD_AUD_MQS_R                                SC_P_EMMC0_CMD                     2
+#define SC_P_EMMC0_CMD_LSIO_GPIO5_IO03                          SC_P_EMMC0_CMD                     3
+#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0                       SC_P_EMMC0_DATA0                   0
+#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00                       SC_P_EMMC0_DATA0                   1
+#define SC_P_EMMC0_DATA0_LSIO_GPIO5_IO04                        SC_P_EMMC0_DATA0                   3
+#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1                       SC_P_EMMC0_DATA1                   0
+#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01                       SC_P_EMMC0_DATA1                   1
+#define SC_P_EMMC0_DATA1_LSIO_GPIO5_IO05                        SC_P_EMMC0_DATA1                   3
+#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2                       SC_P_EMMC0_DATA2                   0
+#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02                       SC_P_EMMC0_DATA2                   1
+#define SC_P_EMMC0_DATA2_LSIO_GPIO5_IO06                        SC_P_EMMC0_DATA2                   3
+#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3                       SC_P_EMMC0_DATA3                   0
+#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03                       SC_P_EMMC0_DATA3                   1
+#define SC_P_EMMC0_DATA3_LSIO_GPIO5_IO07                        SC_P_EMMC0_DATA3                   3
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4                       SC_P_EMMC0_DATA4                   0
+#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04                       SC_P_EMMC0_DATA4                   1
+#define SC_P_EMMC0_DATA4_LSIO_GPIO5_IO08                        SC_P_EMMC0_DATA4                   3
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5                       SC_P_EMMC0_DATA5                   0
+#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05                       SC_P_EMMC0_DATA5                   1
+#define SC_P_EMMC0_DATA5_LSIO_GPIO5_IO09                        SC_P_EMMC0_DATA5                   3
+#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6                       SC_P_EMMC0_DATA6                   0
+#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06                       SC_P_EMMC0_DATA6                   1
+#define SC_P_EMMC0_DATA6_LSIO_GPIO5_IO10                        SC_P_EMMC0_DATA6                   3
+#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7                       SC_P_EMMC0_DATA7                   0
+#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07                       SC_P_EMMC0_DATA7                   1
+#define SC_P_EMMC0_DATA7_LSIO_GPIO5_IO11                        SC_P_EMMC0_DATA7                   3
+#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE                     SC_P_EMMC0_STROBE                  0
+#define SC_P_EMMC0_STROBE_CONN_NAND_CLE                         SC_P_EMMC0_STROBE                  1
+#define SC_P_EMMC0_STROBE_LSIO_GPIO5_IO12                       SC_P_EMMC0_STROBE                  3
+#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B                   SC_P_EMMC0_RESET_B                 0
+#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B                       SC_P_EMMC0_RESET_B                 1
+#define SC_P_EMMC0_RESET_B_CONN_USDHC1_VSELECT                  SC_P_EMMC0_RESET_B                 2
+#define SC_P_EMMC0_RESET_B_LSIO_GPIO5_IO13                      SC_P_EMMC0_RESET_B                 3
+#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK                         SC_P_USDHC1_CLK                    0
+#define SC_P_USDHC1_CLK_AUD_MQS_R                               SC_P_USDHC1_CLK                    1
+#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD                         SC_P_USDHC1_CMD                    0
+#define SC_P_USDHC1_CMD_AUD_MQS_L                               SC_P_USDHC1_CMD                    1
+#define SC_P_USDHC1_CMD_LSIO_GPIO5_IO14                         SC_P_USDHC1_CMD                    3
+#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0                     SC_P_USDHC1_DATA0                  0
+#define SC_P_USDHC1_DATA0_CONN_NAND_RE_N                        SC_P_USDHC1_DATA0                  1
+#define SC_P_USDHC1_DATA0_LSIO_GPIO5_IO15                       SC_P_USDHC1_DATA0                  3
+#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1                     SC_P_USDHC1_DATA1                  0
+#define SC_P_USDHC1_DATA1_CONN_NAND_RE_P                        SC_P_USDHC1_DATA1                  1
+#define SC_P_USDHC1_DATA1_LSIO_GPIO5_IO16                       SC_P_USDHC1_DATA1                  3
+#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2                     SC_P_USDHC1_DATA2                  0
+#define SC_P_USDHC1_DATA2_CONN_NAND_DQS_N                       SC_P_USDHC1_DATA2                  1
+#define SC_P_USDHC1_DATA2_LSIO_GPIO5_IO17                       SC_P_USDHC1_DATA2                  3
+#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3                     SC_P_USDHC1_DATA3                  0
+#define SC_P_USDHC1_DATA3_CONN_NAND_DQS_P                       SC_P_USDHC1_DATA3                  1
+#define SC_P_USDHC1_DATA3_LSIO_GPIO5_IO18                       SC_P_USDHC1_DATA3                  3
+#define SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4                     SC_P_USDHC1_DATA4                  0
+#define SC_P_USDHC1_DATA4_CONN_NAND_CE0_B                       SC_P_USDHC1_DATA4                  1
+#define SC_P_USDHC1_DATA4_AUD_MQS_R                             SC_P_USDHC1_DATA4                  2
+#define SC_P_USDHC1_DATA4_LSIO_GPIO5_IO19                       SC_P_USDHC1_DATA4                  3
+#define SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5                     SC_P_USDHC1_DATA5                  0
+#define SC_P_USDHC1_DATA5_CONN_NAND_RE_B                        SC_P_USDHC1_DATA5                  1
+#define SC_P_USDHC1_DATA5_AUD_MQS_L                             SC_P_USDHC1_DATA5                  2
+#define SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20                       SC_P_USDHC1_DATA5                  3
+#define SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6                     SC_P_USDHC1_DATA6                  0
+#define SC_P_USDHC1_DATA6_CONN_NAND_WE_B                        SC_P_USDHC1_DATA6                  1
+#define SC_P_USDHC1_DATA6_CONN_USDHC1_WP                        SC_P_USDHC1_DATA6                  2
+#define SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21                       SC_P_USDHC1_DATA6                  3
+#define SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7                     SC_P_USDHC1_DATA7                  0
+#define SC_P_USDHC1_DATA7_CONN_NAND_ALE                         SC_P_USDHC1_DATA7                  1
+#define SC_P_USDHC1_DATA7_CONN_USDHC1_CD_B                      SC_P_USDHC1_DATA7                  2
+#define SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22                       SC_P_USDHC1_DATA7                  3
+#define SC_P_USDHC1_STROBE_CONN_USDHC1_STROBE                   SC_P_USDHC1_STROBE                 0
+#define SC_P_USDHC1_STROBE_CONN_NAND_CE1_B                      SC_P_USDHC1_STROBE                 1
+#define SC_P_USDHC1_STROBE_CONN_USDHC1_RESET_B                  SC_P_USDHC1_STROBE                 2
+#define SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23                      SC_P_USDHC1_STROBE                 3
+#define SC_P_USDHC2_CLK_CONN_USDHC2_CLK                         SC_P_USDHC2_CLK                    0
+#define SC_P_USDHC2_CLK_AUD_MQS_R                               SC_P_USDHC2_CLK                    1
+#define SC_P_USDHC2_CLK_LSIO_GPIO5_IO24                         SC_P_USDHC2_CLK                    3
+#define SC_P_USDHC2_CMD_CONN_USDHC2_CMD                         SC_P_USDHC2_CMD                    0
+#define SC_P_USDHC2_CMD_AUD_MQS_L                               SC_P_USDHC2_CMD                    1
+#define SC_P_USDHC2_CMD_LSIO_GPIO5_IO25                         SC_P_USDHC2_CMD                    3
+#define SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0                     SC_P_USDHC2_DATA0                  0
+#define SC_P_USDHC2_DATA0_DMA_UART4_RX                          SC_P_USDHC2_DATA0                  1
+#define SC_P_USDHC2_DATA0_LSIO_GPIO5_IO26                       SC_P_USDHC2_DATA0                  3
+#define SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1                     SC_P_USDHC2_DATA1                  0
+#define SC_P_USDHC2_DATA1_DMA_UART4_TX                          SC_P_USDHC2_DATA1                  1
+#define SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27                       SC_P_USDHC2_DATA1                  3
+#define SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2                     SC_P_USDHC2_DATA2                  0
+#define SC_P_USDHC2_DATA2_DMA_UART4_CTS_B                       SC_P_USDHC2_DATA2                  1
+#define SC_P_USDHC2_DATA2_LSIO_GPIO5_IO28                       SC_P_USDHC2_DATA2                  3
+#define SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3                     SC_P_USDHC2_DATA3                  0
+#define SC_P_USDHC2_DATA3_DMA_UART4_RTS_B                       SC_P_USDHC2_DATA3                  1
+#define SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29                       SC_P_USDHC2_DATA3                  3
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC               SC_P_ENET0_RGMII_TXC               0
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT             SC_P_ENET0_RGMII_TXC               1
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN              SC_P_ENET0_RGMII_TXC               2
+#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO5_IO30                    SC_P_ENET0_RGMII_TXC               3
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL         SC_P_ENET0_RGMII_TX_CTL            0
+#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31                 SC_P_ENET0_RGMII_TX_CTL            3
+#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0             SC_P_ENET0_RGMII_TXD0              0
+#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00                   SC_P_ENET0_RGMII_TXD0              3
+#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1             SC_P_ENET0_RGMII_TXD1              0
+#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01                   SC_P_ENET0_RGMII_TXD1              3
+#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2             SC_P_ENET0_RGMII_TXD2              0
+#define SC_P_ENET0_RGMII_TXD2_DMA_UART3_TX                      SC_P_ENET0_RGMII_TXD2              1
+#define SC_P_ENET0_RGMII_TXD2_VPU_TSI_S1_VID                    SC_P_ENET0_RGMII_TXD2              2
+#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02                   SC_P_ENET0_RGMII_TXD2              3
+#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3             SC_P_ENET0_RGMII_TXD3              0
+#define SC_P_ENET0_RGMII_TXD3_DMA_UART3_RTS_B                   SC_P_ENET0_RGMII_TXD3              1
+#define SC_P_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC                   SC_P_ENET0_RGMII_TXD3              2
+#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03                   SC_P_ENET0_RGMII_TXD3              3
+#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC               SC_P_ENET0_RGMII_RXC               0
+#define SC_P_ENET0_RGMII_RXC_DMA_UART3_CTS_B                    SC_P_ENET0_RGMII_RXC               1
+#define SC_P_ENET0_RGMII_RXC_VPU_TSI_S1_DATA                    SC_P_ENET0_RGMII_RXC               2
+#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO6_IO04                    SC_P_ENET0_RGMII_RXC               3
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL         SC_P_ENET0_RGMII_RX_CTL            0
+#define SC_P_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID                  SC_P_ENET0_RGMII_RX_CTL            2
+#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05                 SC_P_ENET0_RGMII_RX_CTL            3
+#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0             SC_P_ENET0_RGMII_RXD0              0
+#define SC_P_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC                   SC_P_ENET0_RGMII_RXD0              2
+#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06                   SC_P_ENET0_RGMII_RXD0              3
+#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1             SC_P_ENET0_RGMII_RXD1              0
+#define SC_P_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA                   SC_P_ENET0_RGMII_RXD1              2
+#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07                   SC_P_ENET0_RGMII_RXD1              3
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2             SC_P_ENET0_RGMII_RXD2              0
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER             SC_P_ENET0_RGMII_RXD2              1
+#define SC_P_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK                    SC_P_ENET0_RGMII_RXD2              2
+#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08                   SC_P_ENET0_RGMII_RXD2              3
+#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3             SC_P_ENET0_RGMII_RXD3              0
+#define SC_P_ENET0_RGMII_RXD3_DMA_UART3_RX                      SC_P_ENET0_RGMII_RXD3              1
+#define SC_P_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK                    SC_P_ENET0_RGMII_RXD3              2
+#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09                   SC_P_ENET0_RGMII_RXD3              3
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC               SC_P_ENET1_RGMII_TXC               0
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT             SC_P_ENET1_RGMII_TXC               1
+#define SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN              SC_P_ENET1_RGMII_TXC               2
+#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10                    SC_P_ENET1_RGMII_TXC               3
+#define SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL         SC_P_ENET1_RGMII_TX_CTL            0
+#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11                 SC_P_ENET1_RGMII_TX_CTL            3
+#define SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0             SC_P_ENET1_RGMII_TXD0              0
+#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12                   SC_P_ENET1_RGMII_TXD0              3
+#define SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1             SC_P_ENET1_RGMII_TXD1              0
+#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13                   SC_P_ENET1_RGMII_TXD1              3
+#define SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2             SC_P_ENET1_RGMII_TXD2              0
+#define SC_P_ENET1_RGMII_TXD2_DMA_UART3_TX                      SC_P_ENET1_RGMII_TXD2              1
+#define SC_P_ENET1_RGMII_TXD2_VPU_TSI_S1_VID                    SC_P_ENET1_RGMII_TXD2              2
+#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14                   SC_P_ENET1_RGMII_TXD2              3
+#define SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3             SC_P_ENET1_RGMII_TXD3              0
+#define SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B                   SC_P_ENET1_RGMII_TXD3              1
+#define SC_P_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC                   SC_P_ENET1_RGMII_TXD3              2
+#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15                   SC_P_ENET1_RGMII_TXD3              3
+#define SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC               SC_P_ENET1_RGMII_RXC               0
+#define SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B                    SC_P_ENET1_RGMII_RXC               1
+#define SC_P_ENET1_RGMII_RXC_VPU_TSI_S1_DATA                    SC_P_ENET1_RGMII_RXC               2
+#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO6_IO16                    SC_P_ENET1_RGMII_RXC               3
+#define SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL         SC_P_ENET1_RGMII_RX_CTL            0
+#define SC_P_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID                  SC_P_ENET1_RGMII_RX_CTL            2
+#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17                 SC_P_ENET1_RGMII_RX_CTL            3
+#define SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0             SC_P_ENET1_RGMII_RXD0              0
+#define SC_P_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC                   SC_P_ENET1_RGMII_RXD0              2
+#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18                   SC_P_ENET1_RGMII_RXD0              3
+#define SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1             SC_P_ENET1_RGMII_RXD1              0
+#define SC_P_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA                   SC_P_ENET1_RGMII_RXD1              2
+#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19                   SC_P_ENET1_RGMII_RXD1              3
+#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2             SC_P_ENET1_RGMII_RXD2              0
+#define SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER             SC_P_ENET1_RGMII_RXD2              1
+#define SC_P_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK                    SC_P_ENET1_RGMII_RXD2              2
+#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20                   SC_P_ENET1_RGMII_RXD2              3
+#define SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3             SC_P_ENET1_RGMII_RXD3              0
+#define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX                      SC_P_ENET1_RGMII_RXD3              1
+#define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK                    SC_P_ENET1_RGMII_RXD3              2
+#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21                   SC_P_ENET1_RGMII_RXD3              3
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB              0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA              0
+
+#endif				/* SC_PADS_H */
diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
new file mode 100644
index 0000000..41f4fe5
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
@@ -0,0 +1,757 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef _SC_PADS_H
+#define _SC_PADS_H
+
+#define SC_P_PCIE_CTRL0_PERST_B                  0	/* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
+#define SC_P_PCIE_CTRL0_CLKREQ_B                 1	/* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
+#define SC_P_PCIE_CTRL0_WAKE_B                   2	/* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       3	/*  */
+#define SC_P_USB_SS3_TC0                         4	/* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
+#define SC_P_USB_SS3_TC1                         5	/* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
+#define SC_P_USB_SS3_TC2                         6	/* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
+#define SC_P_USB_SS3_TC3                         7	/* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            8	/*  */
+#define SC_P_EMMC0_CLK                           9	/* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
+#define SC_P_EMMC0_CMD                           10	/* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
+#define SC_P_EMMC0_DATA0                         11	/* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
+#define SC_P_EMMC0_DATA1                         12	/* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
+#define SC_P_EMMC0_DATA2                         13	/* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
+#define SC_P_EMMC0_DATA3                         14	/* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0       15	/*  */
+#define SC_P_EMMC0_DATA4                         16	/* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
+#define SC_P_EMMC0_DATA5                         17	/* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
+#define SC_P_EMMC0_DATA6                         18	/* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
+#define SC_P_EMMC0_DATA7                         19	/* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
+#define SC_P_EMMC0_STROBE                        20	/* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
+#define SC_P_EMMC0_RESET_B                       21	/* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1       22	/*  */
+#define SC_P_USDHC1_RESET_B                      23	/* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
+#define SC_P_USDHC1_VSELECT                      24	/* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
+#define SC_P_CTL_NAND_RE_P_N                     25	/*  */
+#define SC_P_USDHC1_WP                           26	/* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
+#define SC_P_USDHC1_CD_B                         27	/* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
+#define SC_P_CTL_NAND_DQS_P_N                    28	/*  */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       29	/*  */
+#define SC_P_USDHC1_CLK                          30	/* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
+#define SC_P_USDHC1_CMD                          31	/* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
+#define SC_P_USDHC1_DATA0                        32	/* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
+#define SC_P_USDHC1_DATA1                        33	/* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
+#define SC_P_USDHC1_DATA2                        34	/* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
+#define SC_P_USDHC1_DATA3                        35	/* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3         36	/*  */
+#define SC_P_ENET0_RGMII_TXC                     37	/* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
+#define SC_P_ENET0_RGMII_TX_CTL                  38	/* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
+#define SC_P_ENET0_RGMII_TXD0                    39	/* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
+#define SC_P_ENET0_RGMII_TXD1                    40	/* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
+#define SC_P_ENET0_RGMII_TXD2                    41	/* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
+#define SC_P_ENET0_RGMII_TXD3                    42	/* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0   43	/*  */
+#define SC_P_ENET0_RGMII_RXC                     44	/* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
+#define SC_P_ENET0_RGMII_RX_CTL                  45	/* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
+#define SC_P_ENET0_RGMII_RXD0                    46	/* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
+#define SC_P_ENET0_RGMII_RXD1                    47	/* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
+#define SC_P_ENET0_RGMII_RXD2                    48	/* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
+#define SC_P_ENET0_RGMII_RXD3                    49	/* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1   50	/*  */
+#define SC_P_ENET0_REFCLK_125M_25M               51	/* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
+#define SC_P_ENET0_MDIO                          52	/* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
+#define SC_P_ENET0_MDC                           53	/* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        54	/*  */
+#define SC_P_ESAI0_FSR                           55	/* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
+#define SC_P_ESAI0_FST                           56	/* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
+#define SC_P_ESAI0_SCKR                          57	/* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
+#define SC_P_ESAI0_SCKT                          58	/* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
+#define SC_P_ESAI0_TX0                           59	/* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
+#define SC_P_ESAI0_TX1                           60	/* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
+#define SC_P_ESAI0_TX2_RX3                       61	/* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
+#define SC_P_ESAI0_TX3_RX2                       62	/* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
+#define SC_P_ESAI0_TX4_RX1                       63	/* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
+#define SC_P_ESAI0_TX5_RX0                       64	/* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
+#define SC_P_SPDIF0_RX                           65	/* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
+#define SC_P_SPDIF0_TX                           66	/* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
+#define SC_P_SPDIF0_EXT_CLK                      67	/* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       68	/*  */
+#define SC_P_SPI3_SCK                            69	/* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
+#define SC_P_SPI3_SDO                            70	/* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
+#define SC_P_SPI3_SDI                            71	/* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
+#define SC_P_SPI3_CS0                            72	/* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
+#define SC_P_SPI3_CS1                            73	/* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
+#define SC_P_MCLK_IN1                            74	/* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
+#define SC_P_MCLK_IN0                            75	/* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
+#define SC_P_MCLK_OUT0                           76	/* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
+#define SC_P_UART1_TX                            77	/* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
+#define SC_P_UART1_RX                            78	/* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
+#define SC_P_UART1_RTS_B                         79	/* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
+#define SC_P_UART1_CTS_B                         80	/* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK       81	/*  */
+#define SC_P_SAI0_TXD                            82	/* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
+#define SC_P_SAI0_TXC                            83	/* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
+#define SC_P_SAI0_RXD                            84	/* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
+#define SC_P_SAI0_TXFS                           85	/* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
+#define SC_P_SAI1_RXD                            86	/* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
+#define SC_P_SAI1_RXC                            87	/* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
+#define SC_P_SAI1_RXFS                           88	/* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
+#define SC_P_SPI2_CS0                            89	/* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
+#define SC_P_SPI2_SDO                            90	/* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
+#define SC_P_SPI2_SDI                            91	/* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
+#define SC_P_SPI2_SCK                            92	/* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
+#define SC_P_SPI0_SCK                            93	/* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
+#define SC_P_SPI0_SDI                            94	/* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
+#define SC_P_SPI0_SDO                            95	/* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
+#define SC_P_SPI0_CS1                            96	/* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
+#define SC_P_SPI0_CS0                            97	/* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       98	/*  */
+#define SC_P_ADC_IN1                             99	/* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
+#define SC_P_ADC_IN0                             100	/* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
+#define SC_P_ADC_IN3                             101	/* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
+#define SC_P_ADC_IN2                             102	/* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
+#define SC_P_ADC_IN5                             103	/* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
+#define SC_P_ADC_IN4                             104	/* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
+#define SC_P_FLEXCAN0_RX                         105	/* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
+#define SC_P_FLEXCAN0_TX                         106	/* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
+#define SC_P_FLEXCAN1_RX                         107	/* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
+#define SC_P_FLEXCAN1_TX                         108	/* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
+#define SC_P_FLEXCAN2_RX                         109	/* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
+#define SC_P_FLEXCAN2_TX                         110	/* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
+#define SC_P_UART0_RX                            111	/* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
+#define SC_P_UART0_TX                            112	/* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
+#define SC_P_UART2_TX                            113	/* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
+#define SC_P_UART2_RX                            114	/* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        115	/*  */
+#define SC_P_MIPI_DSI0_I2C0_SCL                  116	/* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
+#define SC_P_MIPI_DSI0_I2C0_SDA                  117	/* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
+#define SC_P_MIPI_DSI0_GPIO0_00                  118	/* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
+#define SC_P_MIPI_DSI0_GPIO0_01                  119	/* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
+#define SC_P_MIPI_DSI1_I2C0_SCL                  120	/* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
+#define SC_P_MIPI_DSI1_I2C0_SDA                  121	/* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
+#define SC_P_MIPI_DSI1_GPIO0_00                  122	/* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
+#define SC_P_MIPI_DSI1_GPIO0_01                  123	/* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO   124	/*  */
+#define SC_P_JTAG_TRST_B                         125	/* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SCL                        126	/* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
+#define SC_P_PMIC_I2C_SDA                        127	/* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
+#define SC_P_PMIC_INT_B                          128	/* SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00                        129	/* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
+#define SC_P_SCU_GPIO0_01                        130	/* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
+#define SC_P_SCU_PMIC_STANDBY                    131	/* SCU.DSC.PMIC_STANDBY */
+#define SC_P_SCU_BOOT_MODE0                      132	/* SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE1                      133	/* SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE2                      134	/* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
+#define SC_P_SCU_BOOT_MODE3                      135	/* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
+#define SC_P_CSI_D00                             136	/* CI_PI.D02, ADMA.SAI0.RXC */
+#define SC_P_CSI_D01                             137	/* CI_PI.D03, ADMA.SAI0.RXD */
+#define SC_P_CSI_D02                             138	/* CI_PI.D04, ADMA.SAI0.RXFS */
+#define SC_P_CSI_D03                             139	/* CI_PI.D05, ADMA.SAI2.RXC */
+#define SC_P_CSI_D04                             140	/* CI_PI.D06, ADMA.SAI2.RXD */
+#define SC_P_CSI_D05                             141	/* CI_PI.D07, ADMA.SAI2.RXFS */
+#define SC_P_CSI_D06                             142	/* CI_PI.D08, ADMA.SAI3.RXC */
+#define SC_P_CSI_D07                             143	/* CI_PI.D09, ADMA.SAI3.RXD */
+#define SC_P_CSI_HSYNC                           144	/* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
+#define SC_P_CSI_VSYNC                           145	/* CI_PI.VSYNC, CI_PI.D01 */
+#define SC_P_CSI_PCLK                            146	/* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
+#define SC_P_CSI_MCLK                            147	/* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
+#define SC_P_CSI_EN                              148	/* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
+#define SC_P_CSI_RESET                           149	/* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD       150	/*  */
+#define SC_P_MIPI_CSI0_MCLK_OUT                  151	/* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
+#define SC_P_MIPI_CSI0_I2C0_SCL                  152	/* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
+#define SC_P_MIPI_CSI0_I2C0_SDA                  153	/* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
+#define SC_P_MIPI_CSI0_GPIO0_01                  154	/* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
+#define SC_P_MIPI_CSI0_GPIO0_00                  155	/* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
+#define SC_P_QSPI0A_DATA0                        156	/* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
+#define SC_P_QSPI0A_DATA1                        157	/* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
+#define SC_P_QSPI0A_DATA2                        158	/* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
+#define SC_P_QSPI0A_DATA3                        159	/* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
+#define SC_P_QSPI0A_DQS                          160	/* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
+#define SC_P_QSPI0A_SS0_B                        161	/* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
+#define SC_P_QSPI0A_SS1_B                        162	/* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
+#define SC_P_QSPI0A_SCLK                         163	/* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A        164	/*  */
+#define SC_P_QSPI0B_SCLK                         165	/* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
+#define SC_P_QSPI0B_DATA0                        166	/* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
+#define SC_P_QSPI0B_DATA1                        167	/* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
+#define SC_P_QSPI0B_DATA2                        168	/* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
+#define SC_P_QSPI0B_DATA3                        169	/* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
+#define SC_P_QSPI0B_DQS                          170	/* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
+#define SC_P_QSPI0B_SS0_B                        171	/* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
+#define SC_P_QSPI0B_SS1_B                        172	/* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B        173	/*  */
+/*@}*/
+
+/*!
+ * @name Pad Mux Definitions
+ * format: name padid padmux
+ */
+/*@{*/
+#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B              SC_P_PCIE_CTRL0_PERST_B            0
+#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00                 SC_P_PCIE_CTRL0_PERST_B            4
+#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B            SC_P_PCIE_CTRL0_CLKREQ_B           0
+#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01                SC_P_PCIE_CTRL0_CLKREQ_B           4
+#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B                SC_P_PCIE_CTRL0_WAKE_B             0
+#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02                  SC_P_PCIE_CTRL0_WAKE_B             4
+#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL                          SC_P_USB_SS3_TC0                   0
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR                      SC_P_USB_SS3_TC0                   1
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR                      SC_P_USB_SS3_TC0                   2
+#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03                        SC_P_USB_SS3_TC0                   4
+#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL                          SC_P_USB_SS3_TC1                   0
+#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR                      SC_P_USB_SS3_TC1                   1
+#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04                        SC_P_USB_SS3_TC1                   4
+#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA                          SC_P_USB_SS3_TC2                   0
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC                       SC_P_USB_SS3_TC2                   1
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC                       SC_P_USB_SS3_TC2                   2
+#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05                        SC_P_USB_SS3_TC2                   4
+#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA                          SC_P_USB_SS3_TC3                   0
+#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC                       SC_P_USB_SS3_TC3                   1
+#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06                        SC_P_USB_SS3_TC3                   4
+#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK                           SC_P_EMMC0_CLK                     0
+#define SC_P_EMMC0_CLK_CONN_NAND_READY_B                        SC_P_EMMC0_CLK                     1
+#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07                          SC_P_EMMC0_CLK                     4
+#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD                           SC_P_EMMC0_CMD                     0
+#define SC_P_EMMC0_CMD_CONN_NAND_DQS                            SC_P_EMMC0_CMD                     1
+#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08                          SC_P_EMMC0_CMD                     4
+#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0                       SC_P_EMMC0_DATA0                   0
+#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00                       SC_P_EMMC0_DATA0                   1
+#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09                        SC_P_EMMC0_DATA0                   4
+#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1                       SC_P_EMMC0_DATA1                   0
+#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01                       SC_P_EMMC0_DATA1                   1
+#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10                        SC_P_EMMC0_DATA1                   4
+#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2                       SC_P_EMMC0_DATA2                   0
+#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02                       SC_P_EMMC0_DATA2                   1
+#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11                        SC_P_EMMC0_DATA2                   4
+#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3                       SC_P_EMMC0_DATA3                   0
+#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03                       SC_P_EMMC0_DATA3                   1
+#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12                        SC_P_EMMC0_DATA3                   4
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4                       SC_P_EMMC0_DATA4                   0
+#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04                       SC_P_EMMC0_DATA4                   1
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_WP                          SC_P_EMMC0_DATA4                   3
+#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13                        SC_P_EMMC0_DATA4                   4
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5                       SC_P_EMMC0_DATA5                   0
+#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05                       SC_P_EMMC0_DATA5                   1
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT                     SC_P_EMMC0_DATA5                   3
+#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14                        SC_P_EMMC0_DATA5                   4
+#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6                       SC_P_EMMC0_DATA6                   0
+#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06                       SC_P_EMMC0_DATA6                   1
+#define SC_P_EMMC0_DATA6_CONN_MLB_CLK                           SC_P_EMMC0_DATA6                   3
+#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15                        SC_P_EMMC0_DATA6                   4
+#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7                       SC_P_EMMC0_DATA7                   0
+#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07                       SC_P_EMMC0_DATA7                   1
+#define SC_P_EMMC0_DATA7_CONN_MLB_SIG                           SC_P_EMMC0_DATA7                   3
+#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16                        SC_P_EMMC0_DATA7                   4
+#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE                     SC_P_EMMC0_STROBE                  0
+#define SC_P_EMMC0_STROBE_CONN_NAND_CLE                         SC_P_EMMC0_STROBE                  1
+#define SC_P_EMMC0_STROBE_CONN_MLB_DATA                         SC_P_EMMC0_STROBE                  3
+#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17                       SC_P_EMMC0_STROBE                  4
+#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B                   SC_P_EMMC0_RESET_B                 0
+#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B                       SC_P_EMMC0_RESET_B                 1
+#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18                      SC_P_EMMC0_RESET_B                 4
+#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B                 SC_P_USDHC1_RESET_B                0
+#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N                      SC_P_USDHC1_RESET_B                1
+#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK                       SC_P_USDHC1_RESET_B                2
+#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19                     SC_P_USDHC1_RESET_B                4
+#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT                 SC_P_USDHC1_VSELECT                0
+#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P                      SC_P_USDHC1_VSELECT                1
+#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO                       SC_P_USDHC1_VSELECT                2
+#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B                      SC_P_USDHC1_VSELECT                3
+#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20                     SC_P_USDHC1_VSELECT                4
+#define SC_P_USDHC1_WP_CONN_USDHC1_WP                           SC_P_USDHC1_WP                     0
+#define SC_P_USDHC1_WP_CONN_NAND_DQS_N                          SC_P_USDHC1_WP                     1
+#define SC_P_USDHC1_WP_ADMA_SPI2_SDI                            SC_P_USDHC1_WP                     2
+#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21                          SC_P_USDHC1_WP                     4
+#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B                       SC_P_USDHC1_CD_B                   0
+#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P                        SC_P_USDHC1_CD_B                   1
+#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0                          SC_P_USDHC1_CD_B                   2
+#define SC_P_USDHC1_CD_B_CONN_NAND_DQS                          SC_P_USDHC1_CD_B                   3
+#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22                        SC_P_USDHC1_CD_B                   4
+#define SC_P_USDHC1_CLK_CONN_USDHC1_CLK                         SC_P_USDHC1_CLK                    0
+#define SC_P_USDHC1_CLK_ADMA_UART3_RX                           SC_P_USDHC1_CLK                    2
+#define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23                         SC_P_USDHC1_CLK                    4
+#define SC_P_USDHC1_CMD_CONN_USDHC1_CMD                         SC_P_USDHC1_CMD                    0
+#define SC_P_USDHC1_CMD_CONN_NAND_CE0_B                         SC_P_USDHC1_CMD                    1
+#define SC_P_USDHC1_CMD_ADMA_MQS_R                              SC_P_USDHC1_CMD                    2
+#define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24                         SC_P_USDHC1_CMD                    4
+#define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0                     SC_P_USDHC1_DATA0                  0
+#define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B                       SC_P_USDHC1_DATA0                  1
+#define SC_P_USDHC1_DATA0_ADMA_MQS_L                            SC_P_USDHC1_DATA0                  2
+#define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25                       SC_P_USDHC1_DATA0                  4
+#define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1                     SC_P_USDHC1_DATA1                  0
+#define SC_P_USDHC1_DATA1_CONN_NAND_RE_B                        SC_P_USDHC1_DATA1                  1
+#define SC_P_USDHC1_DATA1_ADMA_UART3_TX                         SC_P_USDHC1_DATA1                  2
+#define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26                       SC_P_USDHC1_DATA1                  4
+#define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2                     SC_P_USDHC1_DATA2                  0
+#define SC_P_USDHC1_DATA2_CONN_NAND_WE_B                        SC_P_USDHC1_DATA2                  1
+#define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B                      SC_P_USDHC1_DATA2                  2
+#define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27                       SC_P_USDHC1_DATA2                  4
+#define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3                     SC_P_USDHC1_DATA3                  0
+#define SC_P_USDHC1_DATA3_CONN_NAND_ALE                         SC_P_USDHC1_DATA3                  1
+#define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B                      SC_P_USDHC1_DATA3                  2
+#define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28                       SC_P_USDHC1_DATA3                  4
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC               SC_P_ENET0_RGMII_TXC               0
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT             SC_P_ENET0_RGMII_TXC               1
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN              SC_P_ENET0_RGMII_TXC               2
+#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B                    SC_P_ENET0_RGMII_TXC               3
+#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29                    SC_P_ENET0_RGMII_TXC               4
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL         SC_P_ENET0_RGMII_TX_CTL            0
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B             SC_P_ENET0_RGMII_TX_CTL            3
+#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30                 SC_P_ENET0_RGMII_TX_CTL            4
+#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0             SC_P_ENET0_RGMII_TXD0              0
+#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT               SC_P_ENET0_RGMII_TXD0              3
+#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31                   SC_P_ENET0_RGMII_TXD0              4
+#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1             SC_P_ENET0_RGMII_TXD1              0
+#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP                    SC_P_ENET0_RGMII_TXD1              3
+#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00                   SC_P_ENET0_RGMII_TXD1              4
+#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2             SC_P_ENET0_RGMII_TXD2              0
+#define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK                      SC_P_ENET0_RGMII_TXD2              1
+#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B                   SC_P_ENET0_RGMII_TXD2              2
+#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B                  SC_P_ENET0_RGMII_TXD2              3
+#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01                   SC_P_ENET0_RGMII_TXD2              4
+#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3             SC_P_ENET0_RGMII_TXD3              0
+#define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG                      SC_P_ENET0_RGMII_TXD3              1
+#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B                    SC_P_ENET0_RGMII_TXD3              2
+#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02                   SC_P_ENET0_RGMII_TXD3              4
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD              SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0	0
+#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC               SC_P_ENET0_RGMII_RXC               0
+#define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA                      SC_P_ENET0_RGMII_RXC               1
+#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B                     SC_P_ENET0_RGMII_RXC               2
+#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK                    SC_P_ENET0_RGMII_RXC               3
+#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03                    SC_P_ENET0_RGMII_RXC               4
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL         SC_P_ENET0_RGMII_RX_CTL            0
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD                 SC_P_ENET0_RGMII_RX_CTL            3
+#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04                 SC_P_ENET0_RGMII_RX_CTL            4
+#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0             SC_P_ENET0_RGMII_RXD0              0
+#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0                 SC_P_ENET0_RGMII_RXD0              3
+#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05                   SC_P_ENET0_RGMII_RXD0              4
+#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1             SC_P_ENET0_RGMII_RXD1              0
+#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1                 SC_P_ENET0_RGMII_RXD1              3
+#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06                   SC_P_ENET0_RGMII_RXD1              4
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2             SC_P_ENET0_RGMII_RXD2              0
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER             SC_P_ENET0_RGMII_RXD2              1
+#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2                 SC_P_ENET0_RGMII_RXD2              3
+#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07                   SC_P_ENET0_RGMII_RXD2              4
+#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3             SC_P_ENET0_RGMII_RXD3              0
+#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE                     SC_P_ENET0_RGMII_RXD3              2
+#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3                 SC_P_ENET0_RGMII_RXD3              3
+#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08                   SC_P_ENET0_RGMII_RXD3              4
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD              SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1	0
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M   SC_P_ENET0_REFCLK_125M_25M         0
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS               SC_P_ENET0_REFCLK_125M_25M         1
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS               SC_P_ENET0_REFCLK_125M_25M         2
+#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09              SC_P_ENET0_REFCLK_125M_25M         4
+#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO                         SC_P_ENET0_MDIO                    0
+#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA                           SC_P_ENET0_MDIO                    1
+#define SC_P_ENET0_MDIO_CONN_ENET1_MDIO                         SC_P_ENET0_MDIO                    2
+#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10                         SC_P_ENET0_MDIO                    4
+#define SC_P_ENET0_MDC_CONN_ENET0_MDC                           SC_P_ENET0_MDC                     0
+#define SC_P_ENET0_MDC_ADMA_I2C3_SCL                            SC_P_ENET0_MDC                     1
+#define SC_P_ENET0_MDC_CONN_ENET1_MDC                           SC_P_ENET0_MDC                     2
+#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11                          SC_P_ENET0_MDC                     4
+#define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR                           SC_P_ESAI0_FSR                     0
+#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT                   SC_P_ESAI0_FSR                     1
+#define SC_P_ESAI0_FSR_ADMA_LCDIF_D00                           SC_P_ESAI0_FSR                     2
+#define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC                     SC_P_ESAI0_FSR                     3
+#define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN                    SC_P_ESAI0_FSR                     4
+#define SC_P_ESAI0_FST_ADMA_ESAI0_FST                           SC_P_ESAI0_FST                     0
+#define SC_P_ESAI0_FST_CONN_MLB_CLK                             SC_P_ESAI0_FST                     1
+#define SC_P_ESAI0_FST_ADMA_LCDIF_D01                           SC_P_ESAI0_FST                     2
+#define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2                    SC_P_ESAI0_FST                     3
+#define SC_P_ESAI0_FST_LSIO_GPIO0_IO01                          SC_P_ESAI0_FST                     4
+#define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR                         SC_P_ESAI0_SCKR                    0
+#define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02                          SC_P_ESAI0_SCKR                    2
+#define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL                 SC_P_ESAI0_SCKR                    3
+#define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02                         SC_P_ESAI0_SCKR                    4
+#define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT                         SC_P_ESAI0_SCKT                    0
+#define SC_P_ESAI0_SCKT_CONN_MLB_SIG                            SC_P_ESAI0_SCKT                    1
+#define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03                          SC_P_ESAI0_SCKT                    2
+#define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3                   SC_P_ESAI0_SCKT                    3
+#define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03                         SC_P_ESAI0_SCKT                    4
+#define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0                           SC_P_ESAI0_TX0                     0
+#define SC_P_ESAI0_TX0_CONN_MLB_DATA                            SC_P_ESAI0_TX0                     1
+#define SC_P_ESAI0_TX0_ADMA_LCDIF_D04                           SC_P_ESAI0_TX0                     2
+#define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC                     SC_P_ESAI0_TX0                     3
+#define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04                          SC_P_ESAI0_TX0                     4
+#define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1                           SC_P_ESAI0_TX1                     0
+#define SC_P_ESAI0_TX1_ADMA_LCDIF_D05                           SC_P_ESAI0_TX1                     2
+#define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3                    SC_P_ESAI0_TX1                     3
+#define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05                          SC_P_ESAI0_TX1                     4
+#define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3                   SC_P_ESAI0_TX2_RX3                 0
+#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER                SC_P_ESAI0_TX2_RX3                 1
+#define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06                       SC_P_ESAI0_TX2_RX3                 2
+#define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2                SC_P_ESAI0_TX2_RX3                 3
+#define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06                      SC_P_ESAI0_TX2_RX3                 4
+#define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2                   SC_P_ESAI0_TX3_RX2                 0
+#define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07                       SC_P_ESAI0_TX3_RX2                 2
+#define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1                SC_P_ESAI0_TX3_RX2                 3
+#define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07                      SC_P_ESAI0_TX3_RX2                 4
+#define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1                   SC_P_ESAI0_TX4_RX1                 0
+#define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08                       SC_P_ESAI0_TX4_RX1                 2
+#define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0                SC_P_ESAI0_TX4_RX1                 3
+#define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08                      SC_P_ESAI0_TX4_RX1                 4
+#define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0                   SC_P_ESAI0_TX5_RX0                 0
+#define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09                       SC_P_ESAI0_TX5_RX0                 2
+#define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1                SC_P_ESAI0_TX5_RX0                 3
+#define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09                      SC_P_ESAI0_TX5_RX0                 4
+#define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX                           SC_P_SPDIF0_RX                     0
+#define SC_P_SPDIF0_RX_ADMA_MQS_R                               SC_P_SPDIF0_RX                     1
+#define SC_P_SPDIF0_RX_ADMA_LCDIF_D10                           SC_P_SPDIF0_RX                     2
+#define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0                    SC_P_SPDIF0_RX                     3
+#define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10                          SC_P_SPDIF0_RX                     4
+#define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX                           SC_P_SPDIF0_TX                     0
+#define SC_P_SPDIF0_TX_ADMA_MQS_L                               SC_P_SPDIF0_TX                     1
+#define SC_P_SPDIF0_TX_ADMA_LCDIF_D11                           SC_P_SPDIF0_TX                     2
+#define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL                  SC_P_SPDIF0_TX                     3
+#define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11                          SC_P_SPDIF0_TX                     4
+#define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK                 SC_P_SPDIF0_EXT_CLK                0
+#define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12                      SC_P_SPDIF0_EXT_CLK                2
+#define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M          SC_P_SPDIF0_EXT_CLK                3
+#define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12                     SC_P_SPDIF0_EXT_CLK                4
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD			SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
+#define SC_P_SPI3_SCK_ADMA_SPI3_SCK                             SC_P_SPI3_SCK                      0
+#define SC_P_SPI3_SCK_ADMA_LCDIF_D13                            SC_P_SPI3_SCK                      2
+#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13                           SC_P_SPI3_SCK                      4
+#define SC_P_SPI3_SDO_ADMA_SPI3_SDO                             SC_P_SPI3_SDO                      0
+#define SC_P_SPI3_SDO_ADMA_LCDIF_D14                            SC_P_SPI3_SDO                      2
+#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14                           SC_P_SPI3_SDO                      4
+#define SC_P_SPI3_SDI_ADMA_SPI3_SDI                             SC_P_SPI3_SDI                      0
+#define SC_P_SPI3_SDI_ADMA_LCDIF_D15                            SC_P_SPI3_SDI                      2
+#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15                           SC_P_SPI3_SDI                      4
+#define SC_P_SPI3_CS0_ADMA_SPI3_CS0                             SC_P_SPI3_CS0                      0
+#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1                        SC_P_SPI3_CS0                      1
+#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC                          SC_P_SPI3_CS0                      2
+#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16                           SC_P_SPI3_CS0                      4
+#define SC_P_SPI3_CS1_ADMA_SPI3_CS1                             SC_P_SPI3_CS1                      0
+#define SC_P_SPI3_CS1_ADMA_I2C3_SCL                             SC_P_SPI3_CS1                      1
+#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET                          SC_P_SPI3_CS1                      2
+#define SC_P_SPI3_CS1_ADMA_SPI2_CS0                             SC_P_SPI3_CS1                      3
+#define SC_P_SPI3_CS1_ADMA_LCDIF_D16                            SC_P_SPI3_CS1                      4
+#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1                         SC_P_MCLK_IN1                      0
+#define SC_P_MCLK_IN1_ADMA_I2C3_SDA                             SC_P_MCLK_IN1                      1
+#define SC_P_MCLK_IN1_ADMA_LCDIF_EN                             SC_P_MCLK_IN1                      2
+#define SC_P_MCLK_IN1_ADMA_SPI2_SCK                             SC_P_MCLK_IN1                      3
+#define SC_P_MCLK_IN1_ADMA_LCDIF_D17                            SC_P_MCLK_IN1                      4
+#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0                         SC_P_MCLK_IN0                      0
+#define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK                      SC_P_MCLK_IN0                      1
+#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC                          SC_P_MCLK_IN0                      2
+#define SC_P_MCLK_IN0_ADMA_SPI2_SDI                             SC_P_MCLK_IN0                      3
+#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19                           SC_P_MCLK_IN0                      4
+#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0                       SC_P_MCLK_OUT0                     0
+#define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK                     SC_P_MCLK_OUT0                     1
+#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK                           SC_P_MCLK_OUT0                     2
+#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO                            SC_P_MCLK_OUT0                     3
+#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20                          SC_P_MCLK_OUT0                     4
+#define SC_P_UART1_TX_ADMA_UART1_TX                             SC_P_UART1_TX                      0
+#define SC_P_UART1_TX_LSIO_PWM0_OUT                             SC_P_UART1_TX                      1
+#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE                         SC_P_UART1_TX                      2
+#define SC_P_UART1_TX_LSIO_GPIO0_IO21                           SC_P_UART1_TX                      4
+#define SC_P_UART1_RX_ADMA_UART1_RX                             SC_P_UART1_RX                      0
+#define SC_P_UART1_RX_LSIO_PWM1_OUT                             SC_P_UART1_RX                      1
+#define SC_P_UART1_RX_LSIO_GPT0_COMPARE                         SC_P_UART1_RX                      2
+#define SC_P_UART1_RX_LSIO_GPT1_CLK                             SC_P_UART1_RX                      3
+#define SC_P_UART1_RX_LSIO_GPIO0_IO22                           SC_P_UART1_RX                      4
+#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B                       SC_P_UART1_RTS_B                   0
+#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT                          SC_P_UART1_RTS_B                   1
+#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16                         SC_P_UART1_RTS_B                   2
+#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE                      SC_P_UART1_RTS_B                   3
+#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK                          SC_P_UART1_RTS_B                   4
+#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B                       SC_P_UART1_CTS_B                   0
+#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT                          SC_P_UART1_CTS_B                   1
+#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17                         SC_P_UART1_CTS_B                   2
+#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE                      SC_P_UART1_CTS_B                   3
+#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24                        SC_P_UART1_CTS_B                   4
+#define SC_P_SAI0_TXD_ADMA_SAI0_TXD                             SC_P_SAI0_TXD                      0
+#define SC_P_SAI0_TXD_ADMA_SAI1_RXC                             SC_P_SAI0_TXD                      1
+#define SC_P_SAI0_TXD_ADMA_SPI1_SDO                             SC_P_SAI0_TXD                      2
+#define SC_P_SAI0_TXD_ADMA_LCDIF_D18                            SC_P_SAI0_TXD                      3
+#define SC_P_SAI0_TXD_LSIO_GPIO0_IO25                           SC_P_SAI0_TXD                      4
+#define SC_P_SAI0_TXC_ADMA_SAI0_TXC                             SC_P_SAI0_TXC                      0
+#define SC_P_SAI0_TXC_ADMA_SAI1_TXD                             SC_P_SAI0_TXC                      1
+#define SC_P_SAI0_TXC_ADMA_SPI1_SDI                             SC_P_SAI0_TXC                      2
+#define SC_P_SAI0_TXC_ADMA_LCDIF_D19                            SC_P_SAI0_TXC                      3
+#define SC_P_SAI0_TXC_LSIO_GPIO0_IO26                           SC_P_SAI0_TXC                      4
+#define SC_P_SAI0_RXD_ADMA_SAI0_RXD                             SC_P_SAI0_RXD                      0
+#define SC_P_SAI0_RXD_ADMA_SAI1_RXFS                            SC_P_SAI0_RXD                      1
+#define SC_P_SAI0_RXD_ADMA_SPI1_CS0                             SC_P_SAI0_RXD                      2
+#define SC_P_SAI0_RXD_ADMA_LCDIF_D20                            SC_P_SAI0_RXD                      3
+#define SC_P_SAI0_RXD_LSIO_GPIO0_IO27                           SC_P_SAI0_RXD                      4
+#define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS                           SC_P_SAI0_TXFS                     0
+#define SC_P_SAI0_TXFS_ADMA_SPI2_CS1                            SC_P_SAI0_TXFS                     1
+#define SC_P_SAI0_TXFS_ADMA_SPI1_SCK                            SC_P_SAI0_TXFS                     2
+#define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28                          SC_P_SAI0_TXFS                     4
+#define SC_P_SAI1_RXD_ADMA_SAI1_RXD                             SC_P_SAI1_RXD                      0
+#define SC_P_SAI1_RXD_ADMA_SAI0_RXFS                            SC_P_SAI1_RXD                      1
+#define SC_P_SAI1_RXD_ADMA_SPI1_CS1                             SC_P_SAI1_RXD                      2
+#define SC_P_SAI1_RXD_ADMA_LCDIF_D21                            SC_P_SAI1_RXD                      3
+#define SC_P_SAI1_RXD_LSIO_GPIO0_IO29                           SC_P_SAI1_RXD                      4
+#define SC_P_SAI1_RXC_ADMA_SAI1_RXC                             SC_P_SAI1_RXC                      0
+#define SC_P_SAI1_RXC_ADMA_SAI1_TXC                             SC_P_SAI1_RXC                      1
+#define SC_P_SAI1_RXC_ADMA_LCDIF_D22                            SC_P_SAI1_RXC                      3
+#define SC_P_SAI1_RXC_LSIO_GPIO0_IO30                           SC_P_SAI1_RXC                      4
+#define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS                           SC_P_SAI1_RXFS                     0
+#define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS                           SC_P_SAI1_RXFS                     1
+#define SC_P_SAI1_RXFS_ADMA_LCDIF_D23                           SC_P_SAI1_RXFS                     3
+#define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31                          SC_P_SAI1_RXFS                     4
+#define SC_P_SPI2_CS0_ADMA_SPI2_CS0                             SC_P_SPI2_CS0                      0
+#define SC_P_SPI2_CS0_LSIO_GPIO1_IO00                           SC_P_SPI2_CS0                      4
+#define SC_P_SPI2_SDO_ADMA_SPI2_SDO                             SC_P_SPI2_SDO                      0
+#define SC_P_SPI2_SDO_LSIO_GPIO1_IO01                           SC_P_SPI2_SDO                      4
+#define SC_P_SPI2_SDI_ADMA_SPI2_SDI                             SC_P_SPI2_SDI                      0
+#define SC_P_SPI2_SDI_LSIO_GPIO1_IO02                           SC_P_SPI2_SDI                      4
+#define SC_P_SPI2_SCK_ADMA_SPI2_SCK                             SC_P_SPI2_SCK                      0
+#define SC_P_SPI2_SCK_LSIO_GPIO1_IO03                           SC_P_SPI2_SCK                      4
+#define SC_P_SPI0_SCK_ADMA_SPI0_SCK                             SC_P_SPI0_SCK                      0
+#define SC_P_SPI0_SCK_ADMA_SAI0_TXC                             SC_P_SPI0_SCK                      1
+#define SC_P_SPI0_SCK_M40_I2C0_SCL                              SC_P_SPI0_SCK                      2
+#define SC_P_SPI0_SCK_M40_GPIO0_IO00                            SC_P_SPI0_SCK                      3
+#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04                           SC_P_SPI0_SCK                      4
+#define SC_P_SPI0_SDI_ADMA_SPI0_SDI                             SC_P_SPI0_SDI                      0
+#define SC_P_SPI0_SDI_ADMA_SAI0_TXD                             SC_P_SPI0_SDI                      1
+#define SC_P_SPI0_SDI_M40_TPM0_CH0                              SC_P_SPI0_SDI                      2
+#define SC_P_SPI0_SDI_M40_GPIO0_IO02                            SC_P_SPI0_SDI                      3
+#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05                           SC_P_SPI0_SDI                      4
+#define SC_P_SPI0_SDO_ADMA_SPI0_SDO                             SC_P_SPI0_SDO                      0
+#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS                            SC_P_SPI0_SDO                      1
+#define SC_P_SPI0_SDO_M40_I2C0_SDA                              SC_P_SPI0_SDO                      2
+#define SC_P_SPI0_SDO_M40_GPIO0_IO01                            SC_P_SPI0_SDO                      3
+#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06                           SC_P_SPI0_SDO                      4
+#define SC_P_SPI0_CS1_ADMA_SPI0_CS1                             SC_P_SPI0_CS1                      0
+#define SC_P_SPI0_CS1_ADMA_SAI0_RXC                             SC_P_SPI0_CS1                      1
+#define SC_P_SPI0_CS1_ADMA_SAI1_TXD                             SC_P_SPI0_CS1                      2
+#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT                         SC_P_SPI0_CS1                      3
+#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07                           SC_P_SPI0_CS1                      4
+#define SC_P_SPI0_CS0_ADMA_SPI0_CS0                             SC_P_SPI0_CS0                      0
+#define SC_P_SPI0_CS0_ADMA_SAI0_RXD                             SC_P_SPI0_CS0                      1
+#define SC_P_SPI0_CS0_M40_TPM0_CH1                              SC_P_SPI0_CS0                      2
+#define SC_P_SPI0_CS0_M40_GPIO0_IO03                            SC_P_SPI0_CS0                      3
+#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08                           SC_P_SPI0_CS0                      4
+#define SC_P_ADC_IN1_ADMA_ADC_IN1                               SC_P_ADC_IN1                       0
+#define SC_P_ADC_IN1_M40_I2C0_SDA                               SC_P_ADC_IN1                       1
+#define SC_P_ADC_IN1_M40_GPIO0_IO01                             SC_P_ADC_IN1                       2
+#define SC_P_ADC_IN1_LSIO_GPIO1_IO09                            SC_P_ADC_IN1                       4
+#define SC_P_ADC_IN0_ADMA_ADC_IN0                               SC_P_ADC_IN0                       0
+#define SC_P_ADC_IN0_M40_I2C0_SCL                               SC_P_ADC_IN0                       1
+#define SC_P_ADC_IN0_M40_GPIO0_IO00                             SC_P_ADC_IN0                       2
+#define SC_P_ADC_IN0_LSIO_GPIO1_IO10                            SC_P_ADC_IN0                       4
+#define SC_P_ADC_IN3_ADMA_ADC_IN3                               SC_P_ADC_IN3                       0
+#define SC_P_ADC_IN3_M40_UART0_TX                               SC_P_ADC_IN3                       1
+#define SC_P_ADC_IN3_M40_GPIO0_IO03                             SC_P_ADC_IN3                       2
+#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0                         SC_P_ADC_IN3                       3
+#define SC_P_ADC_IN3_LSIO_GPIO1_IO11                            SC_P_ADC_IN3                       4
+#define SC_P_ADC_IN2_ADMA_ADC_IN2                               SC_P_ADC_IN2                       0
+#define SC_P_ADC_IN2_M40_UART0_RX                               SC_P_ADC_IN2                       1
+#define SC_P_ADC_IN2_M40_GPIO0_IO02                             SC_P_ADC_IN2                       2
+#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0                          SC_P_ADC_IN2                       3
+#define SC_P_ADC_IN2_LSIO_GPIO1_IO12                            SC_P_ADC_IN2                       4
+#define SC_P_ADC_IN5_ADMA_ADC_IN5                               SC_P_ADC_IN5                       0
+#define SC_P_ADC_IN5_M40_TPM0_CH1                               SC_P_ADC_IN5                       1
+#define SC_P_ADC_IN5_M40_GPIO0_IO05                             SC_P_ADC_IN5                       2
+#define SC_P_ADC_IN5_LSIO_GPIO1_IO13                            SC_P_ADC_IN5                       4
+#define SC_P_ADC_IN4_ADMA_ADC_IN4                               SC_P_ADC_IN4                       0
+#define SC_P_ADC_IN4_M40_TPM0_CH0                               SC_P_ADC_IN4                       1
+#define SC_P_ADC_IN4_M40_GPIO0_IO04                             SC_P_ADC_IN4                       2
+#define SC_P_ADC_IN4_LSIO_GPIO1_IO14                            SC_P_ADC_IN4                       4
+#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX                       SC_P_FLEXCAN0_RX                   0
+#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC                          SC_P_FLEXCAN0_RX                   1
+#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B                       SC_P_FLEXCAN0_RX                   2
+#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC                          SC_P_FLEXCAN0_RX                   3
+#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15                        SC_P_FLEXCAN0_RX                   4
+#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX                       SC_P_FLEXCAN0_TX                   0
+#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD                          SC_P_FLEXCAN0_TX                   1
+#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B                       SC_P_FLEXCAN0_TX                   2
+#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS                         SC_P_FLEXCAN0_TX                   3
+#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16                        SC_P_FLEXCAN0_TX                   4
+#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX                       SC_P_FLEXCAN1_RX                   0
+#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS                         SC_P_FLEXCAN1_RX                   1
+#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2                           SC_P_FLEXCAN1_RX                   2
+#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD                          SC_P_FLEXCAN1_RX                   3
+#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17                        SC_P_FLEXCAN1_RX                   4
+#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX                       SC_P_FLEXCAN1_TX                   0
+#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC                          SC_P_FLEXCAN1_TX                   1
+#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0                      SC_P_FLEXCAN1_TX                   2
+#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD                          SC_P_FLEXCAN1_TX                   3
+#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18                        SC_P_FLEXCAN1_TX                   4
+#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX                       SC_P_FLEXCAN2_RX                   0
+#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD                          SC_P_FLEXCAN2_RX                   1
+#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX                          SC_P_FLEXCAN2_RX                   2
+#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS                         SC_P_FLEXCAN2_RX                   3
+#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19                        SC_P_FLEXCAN2_RX                   4
+#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX                       SC_P_FLEXCAN2_TX                   0
+#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS                         SC_P_FLEXCAN2_TX                   1
+#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX                          SC_P_FLEXCAN2_TX                   2
+#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC                          SC_P_FLEXCAN2_TX                   3
+#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20                        SC_P_FLEXCAN2_TX                   4
+#define SC_P_UART0_RX_ADMA_UART0_RX                             SC_P_UART0_RX                      0
+#define SC_P_UART0_RX_ADMA_MQS_R                                SC_P_UART0_RX                      1
+#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX                          SC_P_UART0_RX                      2
+#define SC_P_UART0_RX_SCU_UART0_RX                              SC_P_UART0_RX                      3
+#define SC_P_UART0_RX_LSIO_GPIO1_IO21                           SC_P_UART0_RX                      4
+#define SC_P_UART0_TX_ADMA_UART0_TX                             SC_P_UART0_TX                      0
+#define SC_P_UART0_TX_ADMA_MQS_L                                SC_P_UART0_TX                      1
+#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX                          SC_P_UART0_TX                      2
+#define SC_P_UART0_TX_SCU_UART0_TX                              SC_P_UART0_TX                      3
+#define SC_P_UART0_TX_LSIO_GPIO1_IO22                           SC_P_UART0_TX                      4
+#define SC_P_UART2_TX_ADMA_UART2_TX                             SC_P_UART2_TX                      0
+#define SC_P_UART2_TX_ADMA_FTM_CH1                              SC_P_UART2_TX                      1
+#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX                          SC_P_UART2_TX                      2
+#define SC_P_UART2_TX_LSIO_GPIO1_IO23                           SC_P_UART2_TX                      4
+#define SC_P_UART2_RX_ADMA_UART2_RX                             SC_P_UART2_RX                      0
+#define SC_P_UART2_RX_ADMA_FTM_CH0                              SC_P_UART2_RX                      1
+#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX                          SC_P_UART2_RX                      2
+#define SC_P_UART2_RX_LSIO_GPIO1_IO24                           SC_P_UART2_RX                      4
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL              SC_P_MIPI_DSI0_I2C0_SCL            0
+#define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02            SC_P_MIPI_DSI0_I2C0_SCL            1
+#define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25                 SC_P_MIPI_DSI0_I2C0_SCL            4
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA              SC_P_MIPI_DSI0_I2C0_SDA            0
+#define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03            SC_P_MIPI_DSI0_I2C0_SDA            1
+#define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26                 SC_P_MIPI_DSI0_I2C0_SDA            4
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00            SC_P_MIPI_DSI0_GPIO0_00            0
+#define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL                   SC_P_MIPI_DSI0_GPIO0_00            1
+#define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT              SC_P_MIPI_DSI0_GPIO0_00            2
+#define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27                 SC_P_MIPI_DSI0_GPIO0_00            4
+#define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01            SC_P_MIPI_DSI0_GPIO0_01            0
+#define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA                   SC_P_MIPI_DSI0_GPIO0_01            1
+#define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28                 SC_P_MIPI_DSI0_GPIO0_01            4
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL              SC_P_MIPI_DSI1_I2C0_SCL            0
+#define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02            SC_P_MIPI_DSI1_I2C0_SCL            1
+#define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29                 SC_P_MIPI_DSI1_I2C0_SCL            4
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA              SC_P_MIPI_DSI1_I2C0_SDA            0
+#define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03            SC_P_MIPI_DSI1_I2C0_SDA            1
+#define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30                 SC_P_MIPI_DSI1_I2C0_SDA            4
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00            SC_P_MIPI_DSI1_GPIO0_00            0
+#define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL                   SC_P_MIPI_DSI1_GPIO0_00            1
+#define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT              SC_P_MIPI_DSI1_GPIO0_00            2
+#define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31                 SC_P_MIPI_DSI1_GPIO0_00            4
+#define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01            SC_P_MIPI_DSI1_GPIO0_01            0
+#define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA                   SC_P_MIPI_DSI1_GPIO0_01            1
+#define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00                 SC_P_MIPI_DSI1_GPIO0_01            4
+#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B                        SC_P_JTAG_TRST_B                   0
+#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT                     SC_P_JTAG_TRST_B                   1
+#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL                      SC_P_PMIC_I2C_SCL                  0
+#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON            SC_P_PMIC_I2C_SCL                  1
+#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01                       SC_P_PMIC_I2C_SCL                  4
+#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA                      SC_P_PMIC_I2C_SDA                  0
+#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON            SC_P_PMIC_I2C_SDA                  1
+#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02                       SC_P_PMIC_I2C_SDA                  4
+#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B                      SC_P_PMIC_INT_B                    0
+#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00                        SC_P_SCU_GPIO0_00                  0
+#define SC_P_SCU_GPIO0_00_SCU_UART0_RX                          SC_P_SCU_GPIO0_00                  1
+#define SC_P_SCU_GPIO0_00_M40_UART0_RX                          SC_P_SCU_GPIO0_00                  2
+#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX                         SC_P_SCU_GPIO0_00                  3
+#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03                       SC_P_SCU_GPIO0_00                  4
+#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01                        SC_P_SCU_GPIO0_01                  0
+#define SC_P_SCU_GPIO0_01_SCU_UART0_TX                          SC_P_SCU_GPIO0_01                  1
+#define SC_P_SCU_GPIO0_01_M40_UART0_TX                          SC_P_SCU_GPIO0_01                  2
+#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX                         SC_P_SCU_GPIO0_01                  3
+#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT                    SC_P_SCU_GPIO0_01                  4
+#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY              SC_P_SCU_PMIC_STANDBY              0
+#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0                  SC_P_SCU_BOOT_MODE0                0
+#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1                  SC_P_SCU_BOOT_MODE1                0
+#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2                  SC_P_SCU_BOOT_MODE2                0
+#define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA                    SC_P_SCU_BOOT_MODE2                1
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3                  SC_P_SCU_BOOT_MODE3                0
+#define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL                    SC_P_SCU_BOOT_MODE3                1
+#define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K        SC_P_SCU_BOOT_MODE3                3
+#define SC_P_CSI_D00_CI_PI_D02                                  SC_P_CSI_D00                       0
+#define SC_P_CSI_D00_ADMA_SAI0_RXC                              SC_P_CSI_D00                       2
+#define SC_P_CSI_D01_CI_PI_D03                                  SC_P_CSI_D01                       0
+#define SC_P_CSI_D01_ADMA_SAI0_RXD                              SC_P_CSI_D01                       2
+#define SC_P_CSI_D02_CI_PI_D04                                  SC_P_CSI_D02                       0
+#define SC_P_CSI_D02_ADMA_SAI0_RXFS                             SC_P_CSI_D02                       2
+#define SC_P_CSI_D03_CI_PI_D05                                  SC_P_CSI_D03                       0
+#define SC_P_CSI_D03_ADMA_SAI2_RXC                              SC_P_CSI_D03                       2
+#define SC_P_CSI_D04_CI_PI_D06                                  SC_P_CSI_D04                       0
+#define SC_P_CSI_D04_ADMA_SAI2_RXD                              SC_P_CSI_D04                       2
+#define SC_P_CSI_D05_CI_PI_D07                                  SC_P_CSI_D05                       0
+#define SC_P_CSI_D05_ADMA_SAI2_RXFS                             SC_P_CSI_D05                       2
+#define SC_P_CSI_D06_CI_PI_D08                                  SC_P_CSI_D06                       0
+#define SC_P_CSI_D06_ADMA_SAI3_RXC                              SC_P_CSI_D06                       2
+#define SC_P_CSI_D07_CI_PI_D09                                  SC_P_CSI_D07                       0
+#define SC_P_CSI_D07_ADMA_SAI3_RXD                              SC_P_CSI_D07                       2
+#define SC_P_CSI_HSYNC_CI_PI_HSYNC                              SC_P_CSI_HSYNC                     0
+#define SC_P_CSI_HSYNC_CI_PI_D00                                SC_P_CSI_HSYNC                     1
+#define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS                           SC_P_CSI_HSYNC                     2
+#define SC_P_CSI_VSYNC_CI_PI_VSYNC                              SC_P_CSI_VSYNC                     0
+#define SC_P_CSI_VSYNC_CI_PI_D01                                SC_P_CSI_VSYNC                     1
+#define SC_P_CSI_PCLK_CI_PI_PCLK                                SC_P_CSI_PCLK                      0
+#define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL                        SC_P_CSI_PCLK                      1
+#define SC_P_CSI_PCLK_ADMA_SPI1_SCK                             SC_P_CSI_PCLK                      3
+#define SC_P_CSI_PCLK_LSIO_GPIO3_IO00                           SC_P_CSI_PCLK                      4
+#define SC_P_CSI_MCLK_CI_PI_MCLK                                SC_P_CSI_MCLK                      0
+#define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA                        SC_P_CSI_MCLK                      1
+#define SC_P_CSI_MCLK_ADMA_SPI1_SDO                             SC_P_CSI_MCLK                      3
+#define SC_P_CSI_MCLK_LSIO_GPIO3_IO01                           SC_P_CSI_MCLK                      4
+#define SC_P_CSI_EN_CI_PI_EN                                    SC_P_CSI_EN                        0
+#define SC_P_CSI_EN_CI_PI_I2C_SCL                               SC_P_CSI_EN                        1
+#define SC_P_CSI_EN_ADMA_I2C3_SCL                               SC_P_CSI_EN                        2
+#define SC_P_CSI_EN_ADMA_SPI1_SDI                               SC_P_CSI_EN                        3
+#define SC_P_CSI_EN_LSIO_GPIO3_IO02                             SC_P_CSI_EN                        4
+#define SC_P_CSI_RESET_CI_PI_RESET                              SC_P_CSI_RESET                     0
+#define SC_P_CSI_RESET_CI_PI_I2C_SDA                            SC_P_CSI_RESET                     1
+#define SC_P_CSI_RESET_ADMA_I2C3_SDA                            SC_P_CSI_RESET                     2
+#define SC_P_CSI_RESET_ADMA_SPI1_CS0                            SC_P_CSI_RESET                     3
+#define SC_P_CSI_RESET_LSIO_GPIO3_IO03                          SC_P_CSI_RESET                     4
+#define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT          SC_P_MIPI_CSI0_MCLK_OUT            0
+#define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04                 SC_P_MIPI_CSI0_MCLK_OUT            4
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL              SC_P_MIPI_CSI0_I2C0_SCL            0
+#define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02            SC_P_MIPI_CSI0_I2C0_SCL            1
+#define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05                 SC_P_MIPI_CSI0_I2C0_SCL            4
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA              SC_P_MIPI_CSI0_I2C0_SDA            0
+#define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03            SC_P_MIPI_CSI0_I2C0_SDA            1
+#define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06                 SC_P_MIPI_CSI0_I2C0_SDA            4
+#define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01            SC_P_MIPI_CSI0_GPIO0_01            0
+#define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA                   SC_P_MIPI_CSI0_GPIO0_01            1
+#define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07                 SC_P_MIPI_CSI0_GPIO0_01            4
+#define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00            SC_P_MIPI_CSI0_GPIO0_00            0
+#define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL                   SC_P_MIPI_CSI0_GPIO0_00            1
+#define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08                 SC_P_MIPI_CSI0_GPIO0_00            4
+#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0                     SC_P_QSPI0A_DATA0                  0
+#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09                       SC_P_QSPI0A_DATA0                  4
+#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1                     SC_P_QSPI0A_DATA1                  0
+#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10                       SC_P_QSPI0A_DATA1                  4
+#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2                     SC_P_QSPI0A_DATA2                  0
+#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11                       SC_P_QSPI0A_DATA2                  4
+#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3                     SC_P_QSPI0A_DATA3                  0
+#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12                       SC_P_QSPI0A_DATA3                  4
+#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS                         SC_P_QSPI0A_DQS                    0
+#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13                         SC_P_QSPI0A_DQS                    4
+#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B                     SC_P_QSPI0A_SS0_B                  0
+#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14                       SC_P_QSPI0A_SS0_B                  4
+#define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B                     SC_P_QSPI0A_SS1_B                  0
+#define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15                       SC_P_QSPI0A_SS1_B                  4
+#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK                       SC_P_QSPI0A_SCLK                   0
+#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16                        SC_P_QSPI0A_SCLK                   4
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK                       SC_P_QSPI0B_SCLK                   0
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK                       SC_P_QSPI0B_SCLK                   1
+#define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0                         SC_P_QSPI0B_SCLK                   2
+#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17                        SC_P_QSPI0B_SCLK                   4
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0                     SC_P_QSPI0B_DATA0                  0
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0                     SC_P_QSPI0B_DATA0                  1
+#define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1                        SC_P_QSPI0B_DATA0                  2
+#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18                       SC_P_QSPI0B_DATA0                  4
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1                     SC_P_QSPI0B_DATA1                  0
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1                     SC_P_QSPI0B_DATA1                  1
+#define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2                        SC_P_QSPI0B_DATA1                  2
+#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19                       SC_P_QSPI0B_DATA1                  4
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2                     SC_P_QSPI0B_DATA2                  0
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2                     SC_P_QSPI0B_DATA2                  1
+#define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3                        SC_P_QSPI0B_DATA2                  2
+#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20                       SC_P_QSPI0B_DATA2                  4
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3                     SC_P_QSPI0B_DATA3                  0
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3                     SC_P_QSPI0B_DATA3                  1
+#define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0                        SC_P_QSPI0B_DATA3                  2
+#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21                       SC_P_QSPI0B_DATA3                  4
+#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS                         SC_P_QSPI0B_DQS                    0
+#define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS                         SC_P_QSPI0B_DQS                    1
+#define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1                          SC_P_QSPI0B_DQS                    2
+#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22                         SC_P_QSPI0B_DQS                    4
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B                     SC_P_QSPI0B_SS0_B                  0
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B                     SC_P_QSPI0B_SS0_B                  1
+#define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2                        SC_P_QSPI0B_SS0_B                  2
+#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23                       SC_P_QSPI0B_SS0_B                  4
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B                     SC_P_QSPI0B_SS1_B                  0
+#define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B                     SC_P_QSPI0B_SS1_B                  1
+#define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3                        SC_P_QSPI0B_SS1_B                  2
+#define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24                       SC_P_QSPI0B_SS1_B                  4
+
+#endif				/* _SC_PADS_H */
diff --git a/include/dt-bindings/pinctrl/pinctrl-snapdragon.h b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h
new file mode 100644
index 0000000..615affb
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-snapdragon.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * This header provides constants for Qualcomm Snapdragon pinctrl bindings.
+ *
+ * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
+#define _DT_BINDINGS_PINCTRL_SNAPDRAGON_H
+
+/* GPIO Drive Strength */
+#define DRIVE_STRENGTH_2MA        0
+#define DRIVE_STRENGTH_4MA        1
+#define DRIVE_STRENGTH_6MA        2
+#define DRIVE_STRENGTH_8MA        3
+#define DRIVE_STRENGTH_10MA       4
+#define DRIVE_STRENGTH_12MA       5
+#define DRIVE_STRENGTH_14MA       6
+#define DRIVE_STRENGTH_16MA       7
+
+#endif
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
new file mode 100644
index 0000000..914d56d
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
@@ -0,0 +1,7 @@
+#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H
+#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1
+
+#define TEGRA_XUSB_PADCTL_PCIE 0
+#define TEGRA_XUSB_PADCTL_SATA 1
+
+#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
new file mode 100644
index 0000000..c9b5740
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for Tegra pinctrl bindings.
+ *
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
+#define _DT_BINDINGS_PINCTRL_TEGRA_H
+
+/*
+ * Enable/disable for diffeent dt properties. This is applicable for
+ * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
+ * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
+ */
+#define TEGRA_PIN_DISABLE				0
+#define TEGRA_PIN_ENABLE				1
+
+#define TEGRA_PIN_PULL_NONE				0
+#define TEGRA_PIN_PULL_DOWN				1
+#define TEGRA_PIN_PULL_UP				2
+
+/* Low power mode driver */
+#define TEGRA_PIN_LP_DRIVE_DIV_8			0
+#define TEGRA_PIN_LP_DRIVE_DIV_4			1
+#define TEGRA_PIN_LP_DRIVE_DIV_2			2
+#define TEGRA_PIN_LP_DRIVE_DIV_1			3
+
+/* Rising/Falling slew rate */
+#define TEGRA_PIN_SLEW_RATE_FASTEST			0
+#define TEGRA_PIN_SLEW_RATE_FAST			1
+#define TEGRA_PIN_SLEW_RATE_SLOW			2
+#define TEGRA_PIN_SLEW_RATE_SLOWEST			3
+
+#endif
diff --git a/include/dt-bindings/pinctrl/pins-imx8mq.h b/include/dt-bindings/pinctrl/pins-imx8mq.h
new file mode 100644
index 0000000..0e1d67d
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pins-imx8mq.h
@@ -0,0 +1,632 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DTS_IMX8MQ_PINFUNC_H
+#define __DTS_IMX8MQ_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ               0x014 0x27C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ                        0x018 0x280 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF                                    0x01C 0x284 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B                                    0x020 0x288 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B                        0x024 0x28C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0                                   0x028 0x290 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT          0x028 0x290 0x4C0 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K                          0x028 0x290 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1                       0x028 0x290 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL                                    0x028 0x290 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1                                   0x02C 0x294 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT                                    0x02C 0x294 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M                          0x02C 0x294 0x4BC 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2                       0x02C 0x294 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE                                  0x02C 0x294 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2                                   0x030 0x298 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B                                0x030 0x298 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY                              0x030 0x298 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B                                    0x030 0x298 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3                                   0x034 0x29C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT                              0x034 0x29C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0                            0x034 0x29C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK                              0x034 0x29C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE                                    0x034 0x29C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4                                   0x038 0x2A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT                              0x038 0x2A0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1                            0x038 0x2A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV                           0x038 0x2A0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG                            0x038 0x2A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5                                   0x03C 0x2A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI                                      0x03C 0x2A4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY                     0x03C 0x2A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT                       0x03C 0x2A4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG                            0x03C 0x2A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6                                   0x040 0x2A8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC                                   0x040 0x2A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B                                 0x040 0x2A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3                       0x040 0x2A8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG                            0x040 0x2A8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7                                   0x044 0x2AC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO                                  0x044 0x2AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP                                   0x044 0x2AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4                       0x044 0x2AC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG                            0x044 0x2AC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8                                   0x048 0x2B0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN                        0x048 0x2B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B                              0x048 0x2B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT                           0x048 0x2B0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG                              0x048 0x2B0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9                                   0x04C 0x2B4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT                       0x04C 0x2B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0                            0x04C 0x2B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP                           0x04C 0x2B4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG                           0x04C 0x2B4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10                                  0x050 0x2B8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID                                 0x050 0x2B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED             0x050 0x2B8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11                                  0x054 0x2BC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID                                 0x054 0x2BC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY                     0x054 0x2BC 0x4BC 0x5 0x1
+#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0                           0x054 0x2BC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS                    0x054 0x2BC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12                                  0x058 0x2C0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR                                0x058 0x2C0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1                            0x058 0x2C0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1                           0x058 0x2C0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0                          0x058 0x2C0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13                                  0x05C 0x2C4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC                                 0x05C 0x2C4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT                                    0x05C 0x2C4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2                           0x05C 0x2C4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1                          0x05C 0x2C4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14                                  0x060 0x2C8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR                                0x060 0x2C8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT                                    0x060 0x2C8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1                          0x060 0x2C8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2                          0x060 0x2C8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15                                  0x064 0x2CC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC                                 0x064 0x2CC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT                                    0x064 0x2CC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2                          0x064 0x2CC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB                             0x064 0x2CC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC                                     0x068 0x2D0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16                                    0x068 0x2D0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO                                   0x06C 0x2D4 0x4C0 0x0 0x1
+#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17                                   0x06C 0x2D4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3                               0x070 0x2D8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18                                    0x070 0x2D8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2                               0x074 0x2DC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK                                  0x074 0x2DC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19                                    0x074 0x2DC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1                               0x078 0x2E0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20                                    0x078 0x2E0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0                               0x07C 0x2E4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21                                    0x07C 0x2E4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL                         0x080 0x2E8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22                                 0x080 0x2E8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC                               0x084 0x2EC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER                                   0x084 0x2EC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23                                    0x084 0x2EC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL                         0x088 0x2F0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24                                 0x088 0x2F0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC                               0x08C 0x2F4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER                                   0x08C 0x2F4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25                                    0x08C 0x2F4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0                               0x090 0x2F8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26                                    0x090 0x2F8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1                               0x094 0x2FC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27                                    0x094 0x2FC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2                               0x098 0x300 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28                                    0x098 0x300 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3                               0x09C 0x304 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29                                    0x09C 0x304 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK                                     0x0A0 0x308 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0                                      0x0A0 0x308 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD                                     0x0A4 0x30C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1                                      0x0A4 0x30C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0                                 0x0A8 0x310 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x31  0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1                                 0x0AC 0x314 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3                                    0x0AC 0x314 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2                                 0x0B0 0x318 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4                                    0x0B0 0x318 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3                                 0x0B4 0x31C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5                                    0x0B4 0x31C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4                                 0x0B8 0x320 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6                                    0x0B8 0x320 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5                                 0x0BC 0x324 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7                                    0x0BC 0x324 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6                                 0x0C0 0x328 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8                                    0x0C0 0x328 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7                                 0x0C4 0x32C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9                                    0x0C4 0x32C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B                             0x0C8 0x330 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10                                 0x0C8 0x330 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE                               0x0CC 0x334 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11                                  0x0CC 0x334 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B                                   0x0D0 0x338 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12                                    0x0D0 0x338 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK                                     0x0D4 0x33C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13                                     0x0D4 0x33C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0                          0x0D4 0x33C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0                               0x0D4 0x33C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD                                     0x0D8 0x340 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14                                     0x0D8 0x340 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1                          0x0D8 0x340 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1                               0x0D8 0x340 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0                                 0x0DC 0x344 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15                                   0x0DC 0x344 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2                        0x0DC 0x344 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2                             0x0DC 0x344 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1                                 0x0E0 0x348 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16                                   0x0E0 0x348 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT                            0x0E0 0x348 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3                             0x0E0 0x348 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2                                 0x0E4 0x34C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17                                   0x0E4 0x34C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP                            0x0E4 0x34C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4                             0x0E4 0x34C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3                                 0x0E8 0x350 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18                                   0x0E8 0x350 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET                     0x0E8 0x350 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B                             0x0EC 0x354 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19                                 0x0EC 0x354 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET                  0x0EC 0x354 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP                                       0x0F0 0x358 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20                                      0x0F0 0x358 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK                                 0x0F0 0x358 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE                                   0x0F4 0x35C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK                                   0x0F4 0x35C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0                                     0x0F4 0x35C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0                                  0x0F4 0x35C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B                               0x0F8 0x360 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B                                0x0F8 0x360 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1                                   0x0F8 0x360 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1                                0x0F8 0x360 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B                               0x0FC 0x364 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B                                0x0FC 0x364 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2                                   0x0FC 0x364 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2                                0x0FC 0x364 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B                               0x100 0x368 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B                                0x100 0x368 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3                                   0x100 0x368 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3                                0x100 0x368 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B                               0x104 0x36C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B                                0x104 0x36C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4                                   0x104 0x36C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0                                0x104 0x36C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE                                   0x108 0x370 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK                                   0x108 0x370 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5                                     0x108 0x370 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1                                  0x108 0x370 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00                             0x10C 0x374 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0                               0x10C 0x374 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6                                  0x10C 0x374 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2                               0x10C 0x374 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01                             0x110 0x378 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1                               0x110 0x378 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7                                  0x110 0x378 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3                               0x110 0x378 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02                             0x114 0x37C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2                               0x114 0x37C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8                                  0x114 0x37C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4                               0x114 0x37C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03                             0x118 0x380 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3                               0x118 0x380 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9                                  0x118 0x380 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5                               0x118 0x380 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04                             0x11C 0x384 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0                               0x11C 0x384 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10                                 0x11C 0x384 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6                               0x11C 0x384 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05                             0x120 0x388 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1                               0x120 0x388 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11                                 0x120 0x388 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7                               0x120 0x388 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06                             0x124 0x38C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2                               0x124 0x38C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12                                 0x124 0x38C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8                               0x124 0x38C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07                             0x128 0x390 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3                               0x128 0x390 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13                                 0x128 0x390 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9                               0x128 0x390 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS                                   0x12C 0x394 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS                                    0x12C 0x394 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14                                    0x12C 0x394 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10                                 0x12C 0x394 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B                                 0x130 0x398 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS                                   0x130 0x398 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15                                   0x130 0x398 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11                                0x130 0x398 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B                           0x134 0x39C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16                                0x134 0x39C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12                             0x134 0x39C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B                                 0x138 0x3A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17                                   0x138 0x3A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13                                0x138 0x3A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B                                 0x13C 0x3A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18                                   0x13C 0x3A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14                                0x13C 0x3A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC                                 0x140 0x3A8 0x4E4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0                                0x140 0x3A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19                                   0x140 0x3A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK                                  0x144 0x3AC 0x4D0 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1                                 0x144 0x3AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20                                    0x144 0x3AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0                                0x148 0x3B0 0x4D4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2                                0x148 0x3B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21                                   0x148 0x3B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1                                0x14C 0x3B4 0x4D8 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3                                0x14C 0x3B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC                                 0x14C 0x3B4 0x4CC 0x2 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC                                 0x14C 0x3B4 0x4EC 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22                                   0x14C 0x3B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2                                0x150 0x3B8 0x4DC 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4                                0x150 0x3B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC                                 0x150 0x3B8 0x4CC 0x2 0x1
+#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK                                 0x150 0x3B8 0x4E8 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23                                   0x150 0x3B8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3                                0x154 0x3BC 0x4E0 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5                                0x154 0x3BC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC                                 0x154 0x3BC 0x4CC 0x2 0x2
+#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0                                0x154 0x3BC 0x000 0x3 0x0
+#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24                                   0x154 0x3BC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK                                    0x158 0x3C0 0x52C 0x0 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK                                 0x158 0x3C0 0x4C8 0x1 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK                                    0x158 0x3C0 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25                                   0x158 0x3C0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK                      0x158 0x3C0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC                                 0x15C 0x3C4 0x4C4 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC                                 0x15C 0x3C4 0x4E4 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK                          0x15C 0x3C4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0                                    0x15C 0x3C4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15                                0x15C 0x3C4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK                                  0x160 0x3C8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK                                  0x160 0x3C8 0x4D0 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL                           0x160 0x3C8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1                                     0x160 0x3C8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16                                 0x160 0x3C8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0                                0x164 0x3CC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0                                0x164 0x3CC 0x4D4 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0                             0x164 0x3CC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2                                    0x164 0x3CC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0                       0x164 0x3CC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17                                0x164 0x3CC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1                                0x168 0x3D0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1                                0x168 0x3D0 0x4D8 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1                             0x168 0x3D0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3                                    0x168 0x3D0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1                       0x168 0x3D0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18                                0x168 0x3D0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2                                0x16C 0x3D4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2                                0x16C 0x3D4 0x4DC 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2                             0x16C 0x3D4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4                                    0x16C 0x3D4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2                       0x16C 0x3D4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19                                0x16C 0x3D4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3                                0x170 0x3D8 0x4E0 0x0 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3                                0x170 0x3D8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3                             0x170 0x3D8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5                                    0x170 0x3D8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3                       0x170 0x3D8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20                                0x170 0x3D8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4                                0x174 0x3DC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK                                 0x174 0x3DC 0x51C 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK                                 0x174 0x3DC 0x510 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4                             0x174 0x3DC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6                                    0x174 0x3DC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4                       0x174 0x3DC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21                                0x174 0x3DC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5                                0x178 0x3E0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0                                0x178 0x3E0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0                                0x178 0x3E0 0x514 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC                                 0x178 0x3E0 0x4C4 0x3 0x1
+#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5                             0x178 0x3E0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7                                    0x178 0x3E0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5                       0x178 0x3E0 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22                                0x178 0x3E0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6                                0x17C 0x3E4 0x520 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC                                 0x17C 0x3E4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC                                 0x17C 0x3E4 0x518 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6                             0x17C 0x3E4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8                                    0x17C 0x3E4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6                       0x17C 0x3E4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23                                0x17C 0x3E4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7                                0x180 0x3E8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK                                    0x180 0x3E8 0x530 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC                                 0x180 0x3E8 0x4CC 0x2 0x4
+#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4                                0x180 0x3E8 0x000 0x3 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7                             0x180 0x3E8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9                                    0x180 0x3E8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7                       0x180 0x3E8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24                                0x180 0x3E8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC                                 0x184 0x3EC 0x4CC 0x0 0x3
+#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC                                 0x184 0x3EC 0x4EC 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO                             0x184 0x3EC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10                                   0x184 0x3EC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25                                0x184 0x3EC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK                                  0x188 0x3F0 0x4C8 0x0 0x1
+#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK                                  0x188 0x3F0 0x4E8 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI                              0x188 0x3F0 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11                                    0x188 0x3F0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26                                 0x188 0x3F0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0                                0x18C 0x3F4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0                                0x18C 0x3F4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8                             0x18C 0x3F4 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12                                   0x18C 0x3F4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8                       0x18C 0x3F4 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27                                0x18C 0x3F4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1                                0x190 0x3F8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1                                0x190 0x3F8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9                             0x190 0x3F8 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13                                   0x190 0x3F8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9                       0x190 0x3F8 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28                                0x190 0x3F8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2                                0x194 0x3FC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2                                0x194 0x3FC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10                            0x194 0x3FC 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14                                   0x194 0x3FC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10                      0x194 0x3FC 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29                                0x194 0x3FC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3                                0x198 0x400 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3                                0x198 0x400 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11                            0x198 0x400 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15                                   0x198 0x400 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11                      0x198 0x400 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30                                0x198 0x400 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4                                0x19C 0x404 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK                                 0x19C 0x404 0x510 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK                                 0x19C 0x404 0x51C 0x2 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12                            0x19C 0x404 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16                                   0x19C 0x404 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12                      0x19C 0x404 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31                                0x19C 0x404 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5                                0x1A0 0x408 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0                                0x1A0 0x408 0x514 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0                                0x1A0 0x408 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13                            0x1A0 0x408 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17                                   0x1A0 0x408 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13                      0x1A0 0x408 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0                                0x1A0 0x408 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6                                0x1A4 0x40C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC                                 0x1A4 0x40C 0x518 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC                                 0x1A4 0x40C 0x520 0x2 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14                            0x1A4 0x40C 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18                                   0x1A4 0x40C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14                      0x1A4 0x40C 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1                                0x1A4 0x40C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7                                0x1A8 0x410 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK                                    0x1A8 0x410 0x530 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15                            0x1A8 0x410 0x000 0x4 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19                                   0x1A8 0x410 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15                      0x1A8 0x410 0x000 0x6 0x0
+#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2                                0x1A8 0x410 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK                                    0x1AC 0x414 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK                                    0x1AC 0x414 0x52C 0x1 0x1
+#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK                                 0x1AC 0x414 0x4C8 0x2 0x2
+#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20                                   0x1AC 0x414 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP                                  0x1AC 0x414 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC                                 0x1B0 0x418 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC                                 0x1B0 0x418 0x4EC 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21                                   0x1B0 0x418 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0                                 0x1B0 0x418 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK                                  0x1B4 0x41C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK                                  0x1B4 0x41C 0x4E8 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22                                    0x1B4 0x41C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1                                  0x1B4 0x41C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0                                0x1B8 0x420 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0                                0x1B8 0x420 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23                                   0x1B8 0x420 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2                                 0x1B8 0x420 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC                                 0x1BC 0x424 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1                                0x1BC 0x424 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24                                   0x1BC 0x424 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE                                 0x1BC 0x424 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK                                  0x1C0 0x428 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2                                 0x1C0 0x428 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25                                    0x1C0 0x428 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT                               0x1C0 0x428 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0                                0x1C4 0x42C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3                                0x1C4 0x42C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26                                   0x1C4 0x42C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK                                    0x1C4 0x42C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK                                    0x1C8 0x430 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK                                    0x1C8 0x430 0x52C 0x1 0x2
+#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27                                   0x1C8 0x430 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR                              0x1C8 0x430 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC                                 0x1CC 0x434 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1                                0x1CC 0x434 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC                                 0x1CC 0x434 0x4E4 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28                                   0x1CC 0x434 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0                                0x1CC 0x434 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK                                  0x1D0 0x438 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2                                 0x1D0 0x438 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK                                  0x1D0 0x438 0x4D0 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29                                    0x1D0 0x438 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1                                 0x1D0 0x438 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0                                 0x1D4 0x43C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1                                 0x1D4 0x43C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0                                 0x1D4 0x43C 0x4D4 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30                                    0x1D4 0x43C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0                                  0x1D4 0x43C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC                                 0x1D8 0x440 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK                                     0x1D8 0x440 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1                                0x1D8 0x440 0x4D8 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31                                   0x1D8 0x440 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1                                 0x1D8 0x440 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK                                  0x1DC 0x444 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2                                 0x1DC 0x444 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2                                 0x1DC 0x444 0x4DC 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0                                     0x1DC 0x444 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2                                  0x1DC 0x444 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0                                 0x1E0 0x448 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3                                 0x1E0 0x448 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3                                 0x1E0 0x448 0x4E0 0x2 0x2
+#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1                                     0x1E0 0x448 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3                                  0x1E0 0x448 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK                                    0x1E4 0x44C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT                                     0x1E4 0x44C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK                                    0x1E4 0x44C 0x52C 0x2 0x3
+#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2                                    0x1E4 0x44C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4                                 0x1E4 0x44C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT                                    0x1E8 0x450 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT                                      0x1E8 0x450 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3                                     0x1E8 0x450 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5                                  0x1E8 0x450 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN                                     0x1EC 0x454 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT                                      0x1EC 0x454 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4                                     0x1EC 0x454 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6                                  0x1EC 0x454 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK                           0x1F0 0x458 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT                                 0x1F0 0x458 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5                                0x1F0 0x458 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7                             0x1F0 0x458 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK                                0x1F4 0x45C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX                               0x1F4 0x45C 0x504 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX                               0x1F4 0x45C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6                                  0x1F4 0x45C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8                               0x1F4 0x45C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI                                0x1F8 0x460 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX                               0x1F8 0x460 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX                               0x1F8 0x460 0x504 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7                                  0x1F8 0x460 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9                               0x1F8 0x460 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO                                0x1FC 0x464 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B                            0x1FC 0x464 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B                            0x1FC 0x464 0x500 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8                                  0x1FC 0x464 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10                              0x1FC 0x464 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0                                  0x200 0x468 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B                             0x200 0x468 0x500 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B                             0x200 0x468 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9                                   0x200 0x468 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11                               0x200 0x468 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK                                0x204 0x46C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX                               0x204 0x46C 0x50C 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX                               0x204 0x46C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10                                 0x204 0x46C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12                              0x204 0x46C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI                                0x208 0x470 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX                               0x208 0x470 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX                               0x208 0x470 0x50C 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11                                 0x208 0x470 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13                              0x208 0x470 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO                                0x20C 0x474 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B                            0x20C 0x474 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B                            0x20C 0x474 0x508 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12                                 0x20C 0x474 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14                              0x20C 0x474 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0                                  0x210 0x478 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B                             0x210 0x478 0x508 0x1 0x1
+#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B                             0x210 0x478 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13                                  0x210 0x478 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15                               0x210 0x478 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL                                      0x214 0x47C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC                                     0x214 0x47C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14                                    0x214 0x47C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16                                 0x214 0x47C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA                                      0x218 0x480 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO                                    0x218 0x480 0x4C0 0x1 0x2
+#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15                                    0x218 0x480 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17                                 0x218 0x480 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL                                      0x21C 0x484 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN                          0x21C 0x484 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16                                    0x21C 0x484 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18                                 0x21C 0x484 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA                                      0x220 0x488 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT                         0x220 0x488 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17                                    0x220 0x488 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19                                 0x220 0x488 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL                                      0x224 0x48C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT                                      0x224 0x48C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK                                      0x224 0x48C 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18                                    0x224 0x48C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20                                 0x224 0x48C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA                                      0x228 0x490 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT                                      0x228 0x490 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK                                      0x228 0x490 0x000 0x2 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19                                    0x228 0x490 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21                                 0x228 0x490 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL                                      0x22C 0x494 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT                                      0x22C 0x494 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B                                0x22C 0x494 0x524 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20                                    0x22C 0x494 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22                                 0x22C 0x494 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA                                      0x230 0x498 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT                                      0x230 0x498 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B                                0x230 0x498 0x528 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21                                    0x230 0x498 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23                                 0x230 0x498 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX                                 0x234 0x49C 0x4F4 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX                                 0x234 0x49C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK                                  0x234 0x49C 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22                                   0x234 0x49C 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24                                0x234 0x49C 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX                                 0x238 0x4A0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX                                 0x238 0x4A0 0x4F4 0x0 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI                                  0x238 0x4A0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23                                   0x238 0x4A0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25                                0x238 0x4A0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX                                 0x23C 0x4A4 0x4FC 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX                                 0x23C 0x4A4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO                                  0x23C 0x4A4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24                                   0x23C 0x4A4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26                                0x23C 0x4A4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX                                 0x240 0x4A8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX                                 0x240 0x4A8 0x4FC 0x0 0x1
+#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0                                   0x240 0x4A8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25                                   0x240 0x4A8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27                                0x240 0x4A8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX                                 0x244 0x4AC 0x504 0x0 0x2
+#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX                                 0x244 0x4AC 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B                              0x244 0x4AC 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B                              0x244 0x4AC 0x4F0 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26                                   0x244 0x4AC 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28                                0x244 0x4AC 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX                                 0x248 0x4B0 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX                                 0x248 0x4B0 0x504 0x0 0x3
+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B                              0x248 0x4B0 0x4F0 0x1 0x1
+#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B                              0x248 0x4B0 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27                                   0x248 0x4B0 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29                                0x248 0x4B0 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX                                 0x24C 0x4B4 0x50C 0x0 0x2
+#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX                                 0x24C 0x4B4 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B                              0x24C 0x4B4 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B                              0x24C 0x4B4 0x4F8 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B                               0x24C 0x4B4 0x524 0x2 0x1
+#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28                                   0x24C 0x4B4 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30                                0x24C 0x4B4 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX                                 0x250 0x4B8 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX                                 0x250 0x4B8 0x50C 0x0 0x3
+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B                              0x250 0x4B8 0x4F8 0x1 0x1
+#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B                              0x250 0x4B8 0x000 0x1 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B                               0x250 0x4B8 0x528 0x2 0x1
+#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29                                   0x250 0x4B8 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31                                0x250 0x4B8 0x000 0x7 0x0
+#define MX8MQ_IOMUXC_TEST_MODE                                              0x000 0x254 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_BOOT_MODE0                                             0x000 0x258 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_BOOT_MODE1                                             0x000 0x25C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_MOD                                               0x000 0x260 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TRST_B                                            0x000 0x264 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TDI                                               0x000 0x268 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TMS                                               0x000 0x26C 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TCK                                               0x000 0x270 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_JTAG_TDO                                               0x000 0x274 0x000 0x0 0x0
+#define MX8MQ_IOMUXC_RTC                                                    0x000 0x278 0x000 0x0 0x0
+
+#endif /* __DTS_IMX8MQ_PINFUNC_H */
diff --git a/include/dt-bindings/pinctrl/r7s72100-pinctrl.h b/include/dt-bindings/pinctrl/r7s72100-pinctrl.h
new file mode 100644
index 0000000..31ee376
--- /dev/null
+++ b/include/dt-bindings/pinctrl/r7s72100-pinctrl.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Defines macros and constants for Renesas RZ/A1 pin controller pin
+ * muxing functions.
+ */
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
+#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
+
+#define RZA1_PINS_PER_PORT	16
+
+/*
+ * Create the pin index from its bank and position numbers and store in
+ * the upper 16 bits the alternate function identifier
+ */
+#define RZA1_PINMUX(b, p, f)	\
+	((b) * RZA1_PINS_PER_PORT + (p) | ((f) << 16))
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */
diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
new file mode 100644
index 0000000..1c28d6c
--- /dev/null
+++ b/include/dt-bindings/pinctrl/rockchip.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Header providing constants for Rockchip pinctrl bindings.
+ *
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ */
+
+#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
+#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
+
+#define RK_GPIO0	0
+#define RK_GPIO1	1
+#define RK_GPIO2	2
+#define RK_GPIO3	3
+#define RK_GPIO4	4
+#define RK_GPIO6	6
+
+#define RK_PA0		0
+#define RK_PA1		1
+#define RK_PA2		2
+#define RK_PA3		3
+#define RK_PA4		4
+#define RK_PA5		5
+#define RK_PA6		6
+#define RK_PA7		7
+#define RK_PB0		8
+#define RK_PB1		9
+#define RK_PB2		10
+#define RK_PB3		11
+#define RK_PB4		12
+#define RK_PB5		13
+#define RK_PB6		14
+#define RK_PB7		15
+#define RK_PC0		16
+#define RK_PC1		17
+#define RK_PC2		18
+#define RK_PC3		19
+#define RK_PC4		20
+#define RK_PC5		21
+#define RK_PC6		22
+#define RK_PC7		23
+#define RK_PD0		24
+#define RK_PD1		25
+#define RK_PD2		26
+#define RK_PD3		27
+#define RK_PD4		28
+#define RK_PD5		29
+#define RK_PD6		30
+#define RK_PD7		31
+
+#define RK_FUNC_GPIO	0
+#define RK_FUNC_1	1
+#define RK_FUNC_2	2
+#define RK_FUNC_3	3
+#define RK_FUNC_4	4
+#define RK_FUNC_5	5
+#define RK_FUNC_6	6
+
+#endif
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
new file mode 100644
index 0000000..e6fb8ad
--- /dev/null
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Torgue Alexandre <alexandre.torgue@st.com> for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32_PINFUNC_H
+#define _DT_BINDINGS_STM32_PINFUNC_H
+
+/*  define PIN modes */
+#define GPIO	0x0
+#define AF0	0x1
+#define AF1	0x2
+#define AF2	0x3
+#define AF3	0x4
+#define AF4	0x5
+#define AF5	0x6
+#define AF6	0x7
+#define AF7	0x8
+#define AF8	0x9
+#define AF9	0xa
+#define AF10	0xb
+#define AF11	0xc
+#define AF12	0xd
+#define AF13	0xe
+#define AF14	0xf
+#define AF15	0x10
+#define ANALOG	0x11
+
+/* define Pins number*/
+#define PIN_NO(port, line)	(((port) - 'A') * 0x10 + (line))
+
+#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
+
+/*  package information */
+#define STM32MP_PKG_AA	0x1
+#define STM32MP_PKG_AB	0x2
+#define STM32MP_PKG_AC	0x4
+#define STM32MP_PKG_AD	0x8
+
+#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
+
diff --git a/include/dt-bindings/pinctrl/sun4i-a10.h b/include/dt-bindings/pinctrl/sun4i-a10.h
new file mode 100644
index 0000000..f7553c1
--- /dev/null
+++ b/include/dt-bindings/pinctrl/sun4i-a10.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2014 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this file; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_SUN4I_A10_H_
+#define __DT_BINDINGS_PINCTRL_SUN4I_A10_H_
+
+#define SUN4I_PINCTRL_10_MA	0
+#define SUN4I_PINCTRL_20_MA	1
+#define SUN4I_PINCTRL_30_MA	2
+#define SUN4I_PINCTRL_40_MA	3
+
+#define SUN4I_PINCTRL_NO_PULL	0
+#define SUN4I_PINCTRL_PULL_UP	1
+#define SUN4I_PINCTRL_PULL_DOWN	2
+
+#endif /* __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ */
diff --git a/include/dt-bindings/pmic/sandbox_pmic.h b/include/dt-bindings/pmic/sandbox_pmic.h
new file mode 100644
index 0000000..749c0d1
--- /dev/null
+++ b/include/dt-bindings/pmic/sandbox_pmic.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2015 Samsung Electronics
+ *  Przemyslaw Marczak  <p.marczak@samsung.com>
+ */
+
+#ifndef _DT_BINDINGS_SANDBOX_PMIC_H_
+#define _DT_BINDINGS_SANDBOX_PMIC_H_
+
+/*
+ * Sandbox PMIC - prepare reset values
+ * To provide the default (reset) values as in the real hardware,
+ * the registers are set in i2c pmic emul driver's probe() method.
+ * The default values are defined as below.
+ */
+
+/* Buck operation mode IDs */
+#define BUCK_OM_OFF	0
+#define BUCK_OM_ON	1
+#define BUCK_OM_PWM	2
+#define BUCK_OM_COUNT	3
+
+/* Ldo operation mode IDs */
+#define LDO_OM_OFF	0
+#define LDO_OM_ON	1
+#define LDO_OM_SLEEP	2
+#define LDO_OM_STANDBY	3
+#define LDO_OM_COUNT	4
+
+/* [Value uV/uA]/[Mode ID] to register */
+#define VAL2REG(min, step, val)		(((val) - (min)) / (step))
+#define VAL2OMREG(x)			(x)
+
+#endif
diff --git a/include/dt-bindings/power-domain/bcm6318-power-domain.h b/include/dt-bindings/power-domain/bcm6318-power-domain.h
new file mode 100644
index 0000000..b213cae
--- /dev/null
+++ b/include/dt-bindings/power-domain/bcm6318-power-domain.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6318_H
+#define __DT_BINDINGS_POWER_DOMAIN_BCM6318_H
+
+#define BCM6318_PWR_PCIE	0
+#define BCM6318_PWR_USB		1
+
+#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6318_H */
diff --git a/include/dt-bindings/power-domain/bcm63268-power-domain.h b/include/dt-bindings/power-domain/bcm63268-power-domain.h
new file mode 100644
index 0000000..7208506
--- /dev/null
+++ b/include/dt-bindings/power-domain/bcm63268-power-domain.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM63268_H
+#define __DT_BINDINGS_POWER_DOMAIN_BCM63268_H
+
+#define BCM63268_PWR_SAR	0
+#define BCM63268_PWR_IPSEC	1
+#define BCM63268_PWR_MIPS	2
+#define BCM63268_PWR_DECT	3
+#define BCM63268_PWR_USBH	4
+#define BCM63268_PWR_USBD	5
+#define BCM63268_PWR_ROBOSW	6
+#define BCM63268_PWR_PCM	7
+#define BCM63268_PWR_PERIPH	8
+#define BCM63268_PWR_VDSL_PHY	9
+#define BCM63268_PWR_VDSL_MIPS	10
+#define BCM63268_PWR_FAP	11
+#define BCM63268_PWR_PCIE	12
+#define BCM63268_PWR_WLAN_PADS	13
+
+#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM63268_H */
diff --git a/include/dt-bindings/power-domain/bcm6328-power-domain.h b/include/dt-bindings/power-domain/bcm6328-power-domain.h
new file mode 100644
index 0000000..6b4b199
--- /dev/null
+++ b/include/dt-bindings/power-domain/bcm6328-power-domain.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6328_H
+#define __DT_BINDINGS_POWER_DOMAIN_BCM6328_H
+
+#define BCM6328_PWR_ADSL2_MIPS	0
+#define BCM6328_PWR_ADSL2_PHY	1
+#define BCM6328_PWR_ADSL2_AFE	2
+#define BCM6328_PWR_SAR		3
+#define BCM6328_PWR_PCM		4
+#define BCM6328_PWR_USBD	5
+#define BCM6328_PWR_USBH	6
+#define BCM6328_PWR_PCIE	7
+#define BCM6328_PWR_ROBOSW	8
+#define BCM6328_PWR_EPHY	9
+
+#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6328_H */
diff --git a/include/dt-bindings/power-domain/bcm6362-power-domain.h b/include/dt-bindings/power-domain/bcm6362-power-domain.h
new file mode 100644
index 0000000..1a708a9
--- /dev/null
+++ b/include/dt-bindings/power-domain/bcm6362-power-domain.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
+#define __DT_BINDINGS_POWER_DOMAIN_BCM6362_H
+
+#define BCM6362_PWR_SAR		0
+#define BCM6362_PWR_IPSEC	1
+#define BCM6362_PWR_MIPS	2
+#define BCM6362_PWR_DECT	3
+#define BCM6362_PWR_USBH	4
+#define BCM6362_PWR_USBD	5
+#define BCM6362_PWR_ROBOSW	6
+#define BCM6362_PWR_PCM		7
+#define BCM6362_PWR_PERIPH	8
+#define BCM6362_PWR_ADSL_PHY	9
+#define BCM6362_PWR_GMII_PADS	10
+#define BCM6362_PWR_FAP		11
+#define BCM6362_PWR_PCIE	12
+#define BCM6362_PWR_WLAN_PADS	13
+
+#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6362_H */
diff --git a/include/dt-bindings/power-domain/rk3288.h b/include/dt-bindings/power-domain/rk3288.h
new file mode 100644
index 0000000..ca68c11
--- /dev/null
+++ b/include/dt-bindings/power-domain/rk3288.h
@@ -0,0 +1,11 @@
+#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
+#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__
+
+/* RK3288 power domain index */
+#define RK3288_PD_GPU          0
+#define RK3288_PD_VIO          1
+#define RK3288_PD_VIDEO        2
+#define RK3288_PD_HEVC         3
+#define RK3288_PD_PERI         4
+
+#endif
diff --git a/include/dt-bindings/power/imx7-power.h b/include/dt-bindings/power/imx7-power.h
new file mode 100644
index 0000000..3a181e4
--- /dev/null
+++ b/include/dt-bindings/power/imx7-power.h
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (C) 2017 Impinj
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_IMX7_POWER_H__
+#define __DT_BINDINGS_IMX7_POWER_H__
+
+#define IMX7_POWER_DOMAIN_MIPI_PHY		0
+#define IMX7_POWER_DOMAIN_PCIE_PHY		1
+#define IMX7_POWER_DOMAIN_USB_HSIC_PHY		2
+
+#endif
diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h
new file mode 100755
index 0000000..8a513bd
--- /dev/null
+++ b/include/dt-bindings/power/imx8mq-power.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ *  Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__
+#define __DT_BINDINGS_IMX8MQ_POWER_H__
+
+#define IMX8M_POWER_DOMAIN_MIPI		0
+#define IMX8M_POWER_DOMAIN_PCIE1	1
+#define IMX8M_POWER_DOMAIN_USB_OTG1	2
+#define IMX8M_POWER_DOMAIN_USB_OTG2	3
+#define IMX8M_POWER_DOMAIN_DDR1		4
+#define IMX8M_POWER_DOMAIN_GPU		5
+#define IMX8M_POWER_DOMAIN_VPU		6
+#define IMX8M_POWER_DOMAIN_DISP		7
+#define IMX8M_POWER_DOMAIN_MIPI_CSI1	8
+#define IMX8M_POWER_DOMAIN_MIPI_CSI2	9
+#define IMX8M_POWER_DOMAIN_PCIE2	10
+
+#endif
diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h
new file mode 100644
index 0000000..bb5e67a
--- /dev/null
+++ b/include/dt-bindings/power/meson-g12a-power.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_MESON_G12A_POWER_H
+#define _DT_BINDINGS_MESON_G12A_POWER_H
+
+#define PWRC_G12A_VPU_ID		0
+#define PWRC_G12A_ETH_ID		1
+
+#endif
diff --git a/include/dt-bindings/power/meson-sm1-power.h b/include/dt-bindings/power/meson-sm1-power.h
new file mode 100644
index 0000000..a020ab0
--- /dev/null
+++ b/include/dt-bindings/power/meson-sm1-power.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (c) 2019 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_MESON_SM1_POWER_H
+#define _DT_BINDINGS_MESON_SM1_POWER_H
+
+#define PWRC_SM1_VPU_ID		0
+#define PWRC_SM1_NNA_ID		1
+#define PWRC_SM1_USB_ID		2
+#define PWRC_SM1_PCIE_ID	3
+#define PWRC_SM1_GE2D_ID	4
+#define PWRC_SM1_AUDIO_ID	5
+#define PWRC_SM1_ETH_ID		6
+
+#endif
diff --git a/include/dt-bindings/power/mt7623-power.h b/include/dt-bindings/power/mt7623-power.h
new file mode 100644
index 0000000..0e73bb4
--- /dev/null
+++ b/include/dt-bindings/power/mt7623-power.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MT7623_POWER_H
+#define _DT_BINDINGS_MT7623_POWER_H
+
+#define MT7623_POWER_DOMAIN_CONN	0
+#define MT7623_POWER_DOMAIN_DISP	1
+#define MT7623_POWER_DOMAIN_MFG		2
+#define MT7623_POWER_DOMAIN_VDEC	3
+#define MT7623_POWER_DOMAIN_ISP		4
+#define MT7623_POWER_DOMAIN_BDP		5
+#define MT7623_POWER_DOMAIN_ETH		6
+#define MT7623_POWER_DOMAIN_HIF		7
+#define MT7623_POWER_DOMAIN_IFR_MSC	8
+
+#endif /* _DT_BINDINGS_MT7623_POWER_H */
diff --git a/include/dt-bindings/power/mt7629-power.h b/include/dt-bindings/power/mt7629-power.h
new file mode 100644
index 0000000..c7e6130
--- /dev/null
+++ b/include/dt-bindings/power/mt7629-power.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MT7629_POWER_H
+#define _DT_BINDINGS_MT7629_POWER_H
+
+#define MT7629_POWER_DOMAIN_ETHSYS	0
+#define MT7629_POWER_DOMAIN_HIF0	1
+#define MT7629_POWER_DOMAIN_HIF1	2
+
+#endif /* _DT_BINDINGS_MT7629_POWER_H */
diff --git a/include/dt-bindings/power/r8a7790-sysc.h b/include/dt-bindings/power/r8a7790-sysc.h
new file mode 100644
index 0000000..6af4e99
--- /dev/null
+++ b/include/dt-bindings/power/r8a7790-sysc.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7790_PD_CA15_CPU0		 0
+#define R8A7790_PD_CA15_CPU1		 1
+#define R8A7790_PD_CA15_CPU2		 2
+#define R8A7790_PD_CA15_CPU3		 3
+#define R8A7790_PD_CA7_CPU0		 5
+#define R8A7790_PD_CA7_CPU1		 6
+#define R8A7790_PD_CA7_CPU2		 7
+#define R8A7790_PD_CA7_CPU3		 8
+#define R8A7790_PD_CA15_SCU		12
+#define R8A7790_PD_SH_4A		16
+#define R8A7790_PD_RGX			20
+#define R8A7790_PD_CA7_SCU		21
+#define R8A7790_PD_IMP			24
+
+/* Always-on power area */
+#define R8A7790_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7791-sysc.h b/include/dt-bindings/power/r8a7791-sysc.h
new file mode 100644
index 0000000..1403baa
--- /dev/null
+++ b/include/dt-bindings/power/r8a7791-sysc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7791_PD_CA15_CPU0		 0
+#define R8A7791_PD_CA15_CPU1		 1
+#define R8A7791_PD_CA15_SCU		12
+#define R8A7791_PD_SH_4A		16
+#define R8A7791_PD_SGX			20
+
+/* Always-on power area */
+#define R8A7791_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7792-sysc.h b/include/dt-bindings/power/r8a7792-sysc.h
new file mode 100644
index 0000000..74f4a78
--- /dev/null
+++ b/include/dt-bindings/power/r8a7792-sysc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7792_PD_CA15_CPU0		0
+#define R8A7792_PD_CA15_CPU1		1
+#define R8A7792_PD_CA15_SCU		12
+#define R8A7792_PD_SGX			20
+#define R8A7792_PD_IMP			24
+
+/* Always-on power area */
+#define R8A7792_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7793-sysc.h b/include/dt-bindings/power/r8a7793-sysc.h
new file mode 100644
index 0000000..b5693df
--- /dev/null
+++ b/include/dt-bindings/power/r8a7793-sysc.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ *
+ * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
+ */
+
+#define R8A7793_PD_CA15_CPU0		 0
+#define R8A7793_PD_CA15_CPU1		 1
+#define R8A7793_PD_CA15_SCU		12
+#define R8A7793_PD_SH_4A		16
+#define R8A7793_PD_SGX			20
+
+/* Always-on power area */
+#define R8A7793_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7794-sysc.h b/include/dt-bindings/power/r8a7794-sysc.h
new file mode 100644
index 0000000..862241c
--- /dev/null
+++ b/include/dt-bindings/power/r8a7794-sysc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7794_PD_CA7_CPU0		 5
+#define R8A7794_PD_CA7_CPU1		 6
+#define R8A7794_PD_SH_4A		16
+#define R8A7794_PD_SGX			20
+#define R8A7794_PD_CA7_SCU		21
+
+/* Always-on power area */
+#define R8A7794_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h
new file mode 100644
index 0000000..ad679ee
--- /dev/null
+++ b/include/dt-bindings/power/r8a7795-sysc.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7795_PD_CA57_CPU0		 0
+#define R8A7795_PD_CA57_CPU1		 1
+#define R8A7795_PD_CA57_CPU2		 2
+#define R8A7795_PD_CA57_CPU3		 3
+#define R8A7795_PD_CA53_CPU0		 5
+#define R8A7795_PD_CA53_CPU1		 6
+#define R8A7795_PD_CA53_CPU2		 7
+#define R8A7795_PD_CA53_CPU3		 8
+#define R8A7795_PD_A3VP			 9
+#define R8A7795_PD_CA57_SCU		12
+#define R8A7795_PD_CR7			13
+#define R8A7795_PD_A3VC			14
+#define R8A7795_PD_3DG_A		17
+#define R8A7795_PD_3DG_B		18
+#define R8A7795_PD_3DG_C		19
+#define R8A7795_PD_3DG_D		20
+#define R8A7795_PD_CA53_SCU		21
+#define R8A7795_PD_3DG_E		22
+#define R8A7795_PD_A3IR			24
+#define R8A7795_PD_A2VC0		25	/* ES1.x only */
+#define R8A7795_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A7795_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a7796-sysc.h b/include/dt-bindings/power/r8a7796-sysc.h
new file mode 100644
index 0000000..5b4daab
--- /dev/null
+++ b/include/dt-bindings/power/r8a7796-sysc.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2016 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7796_PD_CA57_CPU0		 0
+#define R8A7796_PD_CA57_CPU1		 1
+#define R8A7796_PD_CA53_CPU0		 5
+#define R8A7796_PD_CA53_CPU1		 6
+#define R8A7796_PD_CA53_CPU2		 7
+#define R8A7796_PD_CA53_CPU3		 8
+#define R8A7796_PD_CA57_SCU		12
+#define R8A7796_PD_CR7			13
+#define R8A7796_PD_A3VC			14
+#define R8A7796_PD_3DG_A		17
+#define R8A7796_PD_3DG_B		18
+#define R8A7796_PD_CA53_SCU		21
+#define R8A7796_PD_A3IR			24
+#define R8A7796_PD_A2VC0		25
+#define R8A7796_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A7796_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h
new file mode 100644
index 0000000..de82d8a
--- /dev/null
+++ b/include/dt-bindings/power/r8a77965-sysc.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77965_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77965_PD_CA57_CPU0		 0
+#define R8A77965_PD_CA57_CPU1		 1
+#define R8A77965_PD_A3VP		 9
+#define R8A77965_PD_CA57_SCU		12
+#define R8A77965_PD_CR7			13
+#define R8A77965_PD_A3VC		14
+#define R8A77965_PD_3DG_A		17
+#define R8A77965_PD_3DG_B		18
+#define R8A77965_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A77965_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h
new file mode 100644
index 0000000..85cc5f2
--- /dev/null
+++ b/include/dt-bindings/power/r8a77970-sysc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2017 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77970_PD_CA53_CPU0		 5
+#define R8A77970_PD_CA53_CPU1		 6
+#define R8A77970_PD_CA53_SCU		21
+#define R8A77970_PD_A2IR0		23
+#define R8A77970_PD_A3IR		24
+#define R8A77970_PD_A2IR1		27
+#define R8A77970_PD_A2DP		28
+#define R8A77970_PD_A2CN		29
+#define R8A77970_PD_A2SC0		30
+#define R8A77970_PD_A2SC1		31
+
+/* Always-on power area */
+#define R8A77970_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77980-sysc.h b/include/dt-bindings/power/r8a77980-sysc.h
new file mode 100644
index 0000000..e12c858
--- /dev/null
+++ b/include/dt-bindings/power/r8a77980-sysc.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77980_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77980_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77980_PD_A2SC2		0
+#define R8A77980_PD_A2SC3		1
+#define R8A77980_PD_A2SC4		2
+#define R8A77980_PD_A2DP0		3
+#define R8A77980_PD_A2DP1		4
+#define R8A77980_PD_CA53_CPU0		5
+#define R8A77980_PD_CA53_CPU1		6
+#define R8A77980_PD_CA53_CPU2		7
+#define R8A77980_PD_CA53_CPU3		8
+#define R8A77980_PD_A2CN		10
+#define R8A77980_PD_A3VIP0		11
+#define R8A77980_PD_A2IR5		12
+#define R8A77980_PD_CR7			13
+#define R8A77980_PD_A2IR4		15
+#define R8A77980_PD_CA53_SCU		21
+#define R8A77980_PD_A2IR0		23
+#define R8A77980_PD_A3IR		24
+#define R8A77980_PD_A3VIP1		25
+#define R8A77980_PD_A3VIP2		26
+#define R8A77980_PD_A2IR1		27
+#define R8A77980_PD_A2IR2		28
+#define R8A77980_PD_A2IR3		29
+#define R8A77980_PD_A2SC0		30
+#define R8A77980_PD_A2SC1		31
+
+/* Always-on power area */
+#define R8A77980_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A77980_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77990-sysc.h b/include/dt-bindings/power/r8a77990-sysc.h
new file mode 100644
index 0000000..944d85b
--- /dev/null
+++ b/include/dt-bindings/power/r8a77990-sysc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77990_PD_CA53_CPU0		5
+#define R8A77990_PD_CA53_CPU1		6
+#define R8A77990_PD_CR7			13
+#define R8A77990_PD_A3VC		14
+#define R8A77990_PD_3DG_A		17
+#define R8A77990_PD_3DG_B		18
+#define R8A77990_PD_CA53_SCU		21
+#define R8A77990_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A77990_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */
diff --git a/include/dt-bindings/power/r8a77995-sysc.h b/include/dt-bindings/power/r8a77995-sysc.h
new file mode 100644
index 0000000..09d0ed5
--- /dev/null
+++ b/include/dt-bindings/power/r8a77995-sysc.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2017 Glider bvba
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A77995_PD_CA53_CPU0		 5
+#define R8A77995_PD_CA53_SCU		21
+
+/* Always-on power area */
+#define R8A77995_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */
diff --git a/include/dt-bindings/power/raspberrypi-power.h b/include/dt-bindings/power/raspberrypi-power.h
new file mode 100644
index 0000000..b3ff8e0
--- /dev/null
+++ b/include/dt-bindings/power/raspberrypi-power.h
@@ -0,0 +1,41 @@
+/*
+ *  Copyright © 2015 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
+#define _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H
+
+/* These power domain indices are the firmware interface's indices
+ * minus one.
+ */
+#define RPI_POWER_DOMAIN_I2C0		0
+#define RPI_POWER_DOMAIN_I2C1		1
+#define RPI_POWER_DOMAIN_I2C2		2
+#define RPI_POWER_DOMAIN_VIDEO_SCALER	3
+#define RPI_POWER_DOMAIN_VPU1		4
+#define RPI_POWER_DOMAIN_HDMI		5
+#define RPI_POWER_DOMAIN_USB		6
+#define RPI_POWER_DOMAIN_VEC		7
+#define RPI_POWER_DOMAIN_JPEG		8
+#define RPI_POWER_DOMAIN_H264		9
+#define RPI_POWER_DOMAIN_V3D		10
+#define RPI_POWER_DOMAIN_ISP		11
+#define RPI_POWER_DOMAIN_UNICAM0	12
+#define RPI_POWER_DOMAIN_UNICAM1	13
+#define RPI_POWER_DOMAIN_CCP2RX		14
+#define RPI_POWER_DOMAIN_CSI2		15
+#define RPI_POWER_DOMAIN_CPI		16
+#define RPI_POWER_DOMAIN_DSI0		17
+#define RPI_POWER_DOMAIN_DSI1		18
+#define RPI_POWER_DOMAIN_TRANSPOSER	19
+#define RPI_POWER_DOMAIN_CCP2TX		20
+#define RPI_POWER_DOMAIN_CDP		21
+#define RPI_POWER_DOMAIN_ARM		22
+
+#define RPI_POWER_DOMAIN_COUNT		23
+
+#endif /* _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H */
diff --git a/include/dt-bindings/power/rk3399-power.h b/include/dt-bindings/power/rk3399-power.h
new file mode 100644
index 0000000..168b3bf
--- /dev/null
+++ b/include/dt-bindings/power/rk3399-power.h
@@ -0,0 +1,53 @@
+#ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__
+#define __DT_BINDINGS_POWER_RK3399_POWER_H__
+
+/* VD_CORE_L */
+#define RK3399_PD_A53_L0	0
+#define RK3399_PD_A53_L1	1
+#define RK3399_PD_A53_L2	2
+#define RK3399_PD_A53_L3	3
+#define RK3399_PD_SCU_L		4
+
+/* VD_CORE_B */
+#define RK3399_PD_A72_B0	5
+#define RK3399_PD_A72_B1	6
+#define RK3399_PD_SCU_B		7
+
+/* VD_LOGIC */
+#define RK3399_PD_TCPD0		8
+#define RK3399_PD_TCPD1		9
+#define RK3399_PD_CCI		10
+#define RK3399_PD_CCI0		11
+#define RK3399_PD_CCI1		12
+#define RK3399_PD_PERILP	13
+#define RK3399_PD_PERIHP	14
+#define RK3399_PD_VIO		15
+#define RK3399_PD_VO		16
+#define RK3399_PD_VOPB		17
+#define RK3399_PD_VOPL		18
+#define RK3399_PD_ISP0		19
+#define RK3399_PD_ISP1		20
+#define RK3399_PD_HDCP		21
+#define RK3399_PD_GMAC		22
+#define RK3399_PD_EMMC		23
+#define RK3399_PD_USB3		24
+#define RK3399_PD_EDP		25
+#define RK3399_PD_GIC		26
+#define RK3399_PD_SD		27
+#define RK3399_PD_SDIOAUDIO	28
+#define RK3399_PD_ALIVE		29
+
+/* VD_CENTER */
+#define RK3399_PD_CENTER	30
+#define RK3399_PD_VCODEC	31
+#define RK3399_PD_VDU		32
+#define RK3399_PD_RGA		33
+#define RK3399_PD_IEP		34
+
+/* VD_GPU */
+#define RK3399_PD_GPU		35
+
+/* VD_PMU */
+#define RK3399_PD_PMU		36
+
+#endif
diff --git a/include/dt-bindings/power/tegra186-powergate.h b/include/dt-bindings/power/tegra186-powergate.h
new file mode 100644
index 0000000..17e7549
--- /dev/null
+++ b/include/dt-bindings/power/tegra186-powergate.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
+#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H
+
+#define TEGRA186_POWER_DOMAIN_AUD	0
+#define TEGRA186_POWER_DOMAIN_DFD	1
+#define TEGRA186_POWER_DOMAIN_DISP	2
+#define TEGRA186_POWER_DOMAIN_DISPB	3
+#define TEGRA186_POWER_DOMAIN_DISPC	4
+#define TEGRA186_POWER_DOMAIN_ISPA	5
+#define TEGRA186_POWER_DOMAIN_NVDEC	6
+#define TEGRA186_POWER_DOMAIN_NVJPG	7
+#define TEGRA186_POWER_DOMAIN_MPE	8
+#define TEGRA186_POWER_DOMAIN_PCX	9
+#define TEGRA186_POWER_DOMAIN_SAX	10
+#define TEGRA186_POWER_DOMAIN_VE	11
+#define TEGRA186_POWER_DOMAIN_VIC	12
+#define TEGRA186_POWER_DOMAIN_XUSBA	13
+#define TEGRA186_POWER_DOMAIN_XUSBB	14
+#define TEGRA186_POWER_DOMAIN_XUSBC	15
+#define TEGRA186_POWER_DOMAIN_GPU	43
+#define TEGRA186_POWER_DOMAIN_MAX	44
+
+#endif
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
new file mode 100644
index 0000000..0d9a412
--- /dev/null
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
+#define _DT_BINDINGS_ZYNQMP_POWER_H
+
+#define		PD_USB_0	22
+#define		PD_USB_1	23
+#define		PD_TTC_0	24
+#define		PD_TTC_1	25
+#define		PD_TTC_2	26
+#define		PD_TTC_3	27
+#define		PD_SATA		28
+#define		PD_ETH_0	29
+#define		PD_ETH_1	30
+#define		PD_ETH_2	31
+#define		PD_ETH_3	32
+#define		PD_UART_0	33
+#define		PD_UART_1	34
+#define		PD_SPI_0	35
+#define		PD_SPI_1	36
+#define		PD_I2C_0	37
+#define		PD_I2C_1	38
+#define		PD_SD_0		39
+#define		PD_SD_1		40
+#define		PD_DP		41
+#define		PD_GDMA		42
+#define		PD_ADMA		43
+#define		PD_NAND		44
+#define		PD_QSPI		45
+#define		PD_GPIO		46
+#define		PD_CAN_0	47
+#define		PD_CAN_1	48
+#define		PD_GPU		58
+#define		PD_PCIE		59
+
+#endif
diff --git a/include/dt-bindings/pwm/pwm.h b/include/dt-bindings/pwm/pwm.h
new file mode 100644
index 0000000..96f49e8
--- /dev/null
+++ b/include/dt-bindings/pwm/pwm.h
@@ -0,0 +1,14 @@
+/*
+ * This header provides constants for most PWM bindings.
+ *
+ * Most PWM bindings can include a flags cell as part of the PWM specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_PWM_PWM_H
+#define _DT_BINDINGS_PWM_PWM_H
+
+#define PWM_POLARITY_INVERTED			(1 << 0)
+
+#endif
diff --git a/include/dt-bindings/regulator/maxim,max77802.h b/include/dt-bindings/regulator/maxim,max77802.h
new file mode 100644
index 0000000..cf28631
--- /dev/null
+++ b/include/dt-bindings/regulator/maxim,max77802.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for the Maxim 77802 PMIC regulators
+ */
+
+#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
+#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
+
+/* Regulator operating modes */
+#define MAX77802_OPMODE_LP	1
+#define MAX77802_OPMODE_NORMAL	3
+
+#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */
diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 0000000..acb0bbf
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET		0
+#define CPU1_RESET		1
+#define WDS_RESET		2
+#define SCUPER_RESET		3
+
+/* PER0MODRST */
+#define EMAC0_RESET		32
+#define EMAC1_RESET		33
+#define EMAC2_RESET		34
+#define USB0_RESET		35
+#define USB1_RESET		36
+#define NAND_RESET		37
+#define QSPI_RESET		38
+#define SDMMC_RESET		39
+#define EMAC0_OCP_RESET		40
+#define EMAC1_OCP_RESET		41
+#define EMAC2_OCP_RESET		42
+#define USB0_OCP_RESET		43
+#define USB1_OCP_RESET		44
+#define NAND_OCP_RESET		45
+#define QSPI_OCP_RESET		46
+#define SDMMC_OCP_RESET		47
+#define DMA_RESET		48
+#define SPIM0_RESET		49
+#define SPIM1_RESET		50
+#define SPIS0_RESET		51
+#define SPIS1_RESET		52
+#define DMA_OCP_RESET		53
+#define EMAC_PTP_RESET		54
+/* 55 is empty*/
+#define DMAIF0_RESET		56
+#define DMAIF1_RESET		57
+#define DMAIF2_RESET		58
+#define DMAIF3_RESET		59
+#define DMAIF4_RESET		60
+#define DMAIF5_RESET		61
+#define DMAIF6_RESET		62
+#define DMAIF7_RESET		63
+
+/* PER1MODRST */
+#define L4WD0_RESET		64
+#define L4WD1_RESET		65
+#define L4SYSTIMER0_RESET	66
+#define L4SYSTIMER1_RESET	67
+#define SPTIMER0_RESET		68
+#define SPTIMER1_RESET		69
+/* 70-71 is reserved */
+#define I2C0_RESET		72
+#define I2C1_RESET		73
+#define I2C2_RESET		74
+#define I2C3_RESET		75
+#define I2C4_RESET		76
+/* 77-79 is reserved */
+#define UART0_RESET		80
+#define UART1_RESET		81
+/* 82-87 is reserved */
+#define GPIO0_RESET		88
+#define GPIO1_RESET		89
+#define GPIO2_RESET		90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET		96
+#define LWHPS2FPGA_RESET	97
+#define FPGA2HPS_RESET		98
+#define F2SSDRAM0_RESET		99
+#define F2SSDRAM1_RESET		100
+#define F2SSDRAM2_RESET		101
+#define DDRSCH_RESET		102
+
+/* SYSMODRST*/
+#define ROM_RESET		128
+#define OCRAM_RESET		129
+/* 130 is reserved */
+#define FPGAMGR_RESET		131
+#define S2F_RESET		132
+#define SYSDBG_RESET		133
+#define OCRAM_OCP_RESET		134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET	160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET		163
+#define TIMESTAMPCOLD_RESET	164
+#define TAPCOLD_RESET		165
+#define HMCCOLD_RESET		166
+#define IOMGRCOLD_RESET		167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET		192
+
+/* DBGMODRST */
+#define DBG_RESET		224
+#endif
diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h
new file mode 100644
index 0000000..1fdcf8a
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016-2018 Intel Corporation. All rights reserved
+ * Copyright (C) 2016 Altera Corporation. All rights reserved
+ * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
+
+/* MPUMODRST */
+#define CPU0_RESET		0
+#define CPU1_RESET		1
+#define CPU2_RESET		2
+#define CPU3_RESET		3
+
+/* PER0MODRST */
+#define EMAC0_RESET		32
+#define EMAC1_RESET		33
+#define EMAC2_RESET		34
+#define USB0_RESET		35
+#define USB1_RESET		36
+#define NAND_RESET		37
+/* 38 is empty */
+#define SDMMC_RESET		39
+#define EMAC0_OCP_RESET		40
+#define EMAC1_OCP_RESET		41
+#define EMAC2_OCP_RESET		42
+#define USB0_OCP_RESET		43
+#define USB1_OCP_RESET		44
+#define NAND_OCP_RESET		45
+/* 46 is empty */
+#define SDMMC_OCP_RESET		47
+#define DMA_RESET		48
+#define SPIM0_RESET		49
+#define SPIM1_RESET		50
+#define SPIS0_RESET		51
+#define SPIS1_RESET		52
+#define DMA_OCP_RESET		53
+#define EMAC_PTP_RESET		54
+/* 55 is empty*/
+#define DMAIF0_RESET		56
+#define DMAIF1_RESET		57
+#define DMAIF2_RESET		58
+#define DMAIF3_RESET		59
+#define DMAIF4_RESET		60
+#define DMAIF5_RESET		61
+#define DMAIF6_RESET		62
+#define DMAIF7_RESET		63
+
+/* PER1MODRST */
+#define WATCHDOG0_RESET		64
+#define WATCHDOG1_RESET		65
+#define WATCHDOG2_RESET		66
+#define WATCHDOG3_RESET		67
+#define L4SYSTIMER0_RESET	68
+#define L4SYSTIMER1_RESET	69
+#define SPTIMER0_RESET		70
+#define SPTIMER1_RESET		71
+#define I2C0_RESET		72
+#define I2C1_RESET		73
+#define I2C2_RESET		74
+#define I2C3_RESET		75
+#define I2C4_RESET		76
+/* 77-79 is empty */
+#define UART0_RESET		80
+#define UART1_RESET		81
+/* 82-87 is empty */
+#define GPIO0_RESET		88
+#define GPIO1_RESET		89
+
+/* BRGMODRST */
+#define SOC2FPGA_RESET		96
+#define LWHPS2FPGA_RESET	97
+#define FPGA2SOC_RESET		98
+#define F2SSDRAM0_RESET		99
+#define F2SSDRAM1_RESET		100
+#define F2SSDRAM2_RESET		101
+#define DDRSCH_RESET		102
+
+/* COLDMODRST */
+#define CPUPO0_RESET		160
+#define CPUPO1_RESET		161
+#define CPUPO2_RESET		162
+#define CPUPO3_RESET		163
+/* 164-167 is empty */
+#define L2_RESET		168
+
+/* DBGMODRST */
+#define DBG_RESET		224
+#define CSDAP_RESET		225
+
+/* TAPMODRST */
+#define TAP_RESET		256
+
+#endif
diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h
new file mode 100644
index 0000000..5b7ad73
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+
+/* MPUMODRST */
+#define CPU0_RESET		0
+#define CPU1_RESET		1
+#define WDS_RESET		2
+#define SCUPER_RESET		3
+#define L2_RESET		4
+
+/* PERMODRST */
+#define EMAC0_RESET		32
+#define EMAC1_RESET		33
+#define USB0_RESET		34
+#define USB1_RESET		35
+#define NAND_RESET		36
+#define QSPI_RESET		37
+#define L4WD0_RESET		38
+#define L4WD1_RESET		39
+#define OSC1TIMER0_RESET	40
+#define OSC1TIMER1_RESET	41
+#define SPTIMER0_RESET		42
+#define SPTIMER1_RESET		43
+#define I2C0_RESET		44
+#define I2C1_RESET		45
+#define I2C2_RESET		46
+#define I2C3_RESET		47
+#define UART0_RESET		48
+#define UART1_RESET		49
+#define SPIM0_RESET		50
+#define SPIM1_RESET		51
+#define SPIS0_RESET		52
+#define SPIS1_RESET		53
+#define SDMMC_RESET		54
+#define CAN0_RESET		55
+#define CAN1_RESET		56
+#define GPIO0_RESET		57
+#define GPIO1_RESET		58
+#define GPIO2_RESET		59
+#define DMA_RESET		60
+#define SDR_RESET		61
+
+/* PER2MODRST */
+#define DMAIF0_RESET		64
+#define DMAIF1_RESET		65
+#define DMAIF2_RESET		66
+#define DMAIF3_RESET		67
+#define DMAIF4_RESET		68
+#define DMAIF5_RESET		69
+#define DMAIF6_RESET		70
+#define DMAIF7_RESET		71
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET		96
+#define LWHPS2FPGA_RESET	97
+#define FPGA2HPS_RESET		98
+
+/* MISCMODRST*/
+#define ROM_RESET		128
+#define OCRAM_RESET		129
+#define SYSMGR_RESET		130
+#define SYSMGRCOLD_RESET	131
+#define FPGAMGR_RESET		132
+#define ACPIDMAP_RESET		133
+#define S2F_RESET		134
+#define S2FCOLD_RESET		135
+#define NRSTPIN_RESET		136
+#define TIMESTAMPCOLD_RESET	137
+#define CLKMGRCOLD_RESET	138
+#define SCANMGR_RESET		139
+#define FRZCTRLCOLD_RESET	140
+#define SYSDBG_RESET		141
+#define DBG_RESET		142
+#define TAPCOLD_RESET		143
+#define SDRCOLD_RESET		144
+
+#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
new file mode 100644
index 0000000..05c3636
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ *
+ * Copyright (c) 2018 Baylibre SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
+#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
+
+#define AXG_ARB_TODDR_A	0
+#define AXG_ARB_TODDR_B	1
+#define AXG_ARB_TODDR_C	2
+#define AXG_ARB_FRDDR_A	3
+#define AXG_ARB_FRDDR_B	4
+#define AXG_ARB_FRDDR_C	5
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
new file mode 100644
index 0000000..ad6f55d
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-axg-reset.h
@@ -0,0 +1,124 @@
+/*
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2017 Amlogic, inc.
+ * Author: Yixun Lan <yixun.lan@amlogic.com>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD)
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
+
+/*	RESET0					*/
+#define RESET_HIU			0
+#define RESET_PCIE_A			1
+#define RESET_PCIE_B			2
+#define RESET_DDR_TOP			3
+/*					4	*/
+#define RESET_VIU			5
+#define RESET_PCIE_PHY			6
+#define RESET_PCIE_APB			7
+/*					8	*/
+/*					9	*/
+#define RESET_VENC			10
+#define RESET_ASSIST			11
+/*					12	*/
+#define RESET_VCBUS			13
+/*					14	*/
+/*					15	*/
+#define RESET_GIC			16
+#define RESET_CAPB3_DECODE		17
+/*					18-21	*/
+#define RESET_SYS_CPU_CAPB3		22
+#define RESET_CBUS_CAPB3		23
+#define RESET_AHB_CNTL			24
+#define RESET_AHB_DATA			25
+#define RESET_VCBUS_CLK81		26
+#define RESET_MMC			27
+/*					28-31	*/
+/*	RESET1					*/
+/*					32	*/
+/*					33	*/
+#define RESET_USB_OTG			34
+#define RESET_DDR			35
+#define RESET_AO_RESET			36
+/*					37	*/
+#define RESET_AHB_SRAM			38
+/*					39	*/
+/*					40	*/
+#define RESET_DMA			41
+#define RESET_ISA			42
+#define RESET_ETHERNET			43
+/*					44	*/
+#define RESET_SD_EMMC_B			45
+#define RESET_SD_EMMC_C			46
+#define RESET_ROM_BOOT			47
+#define RESET_SYS_CPU_0			48
+#define RESET_SYS_CPU_1			49
+#define RESET_SYS_CPU_2			50
+#define RESET_SYS_CPU_3			51
+#define RESET_SYS_CPU_CORE_0		52
+#define RESET_SYS_CPU_CORE_1		53
+#define RESET_SYS_CPU_CORE_2		54
+#define RESET_SYS_CPU_CORE_3		55
+#define RESET_SYS_PLL_DIV		56
+#define RESET_SYS_CPU_AXI		57
+#define RESET_SYS_CPU_L2		58
+#define RESET_SYS_CPU_P			59
+#define RESET_SYS_CPU_MBIST		60
+/*					61-63	*/
+/*	RESET2					*/
+/*					64	*/
+/*					65	*/
+#define RESET_AUDIO			66
+/*					67	*/
+#define RESET_MIPI_HOST			68
+#define RESET_AUDIO_LOCKER		69
+#define RESET_GE2D			70
+/*					71-76	*/
+#define RESET_AO_CPU_RESET		77
+/*					78-95	*/
+/*	RESET3					*/
+#define RESET_RING_OSCILLATOR		96
+/*					97-127	*/
+/*	RESET4					*/
+/*					128	*/
+/*					129	*/
+#define RESET_MIPI_PHY			130
+/*					131-140	*/
+#define RESET_VENCL			141
+#define RESET_I2C_MASTER_2		142
+#define RESET_I2C_MASTER_1		143
+/*					144-159	*/
+/*	RESET5					*/
+/*					160-191	*/
+/*	RESET6					*/
+#define RESET_PERIPHS_GENERAL		192
+#define RESET_PERIPHS_SPICC		193
+/*					194	*/
+/*					195	*/
+#define RESET_PERIPHS_I2C_MASTER_0	196
+/*					197-200	*/
+#define RESET_PERIPHS_UART_0		201
+#define RESET_PERIPHS_UART_1		202
+/*					203-204	*/
+#define RESET_PERIPHS_SPI_0		205
+#define RESET_PERIPHS_I2C_MASTER_3	206
+/*					207-223	*/
+/*	RESET7					*/
+#define RESET_USB_DDR_0			224
+#define RESET_USB_DDR_1			225
+#define RESET_USB_DDR_2			226
+#define RESET_USB_DDR_3			227
+/*					228	*/
+#define RESET_DEVICE_MMC_ARB		229
+/*					230	*/
+#define RESET_VID_LOCK			231
+#define RESET_A9_DMC_PIPEL		232
+#define RESET_DMC_VPU_PIPEL		233
+/*					234-255	*/
+
+#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
new file mode 100644
index 0000000..14b78da
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
+
+#define AUD_RESET_PDM		0
+#define AUD_RESET_TDMIN_A	1
+#define AUD_RESET_TDMIN_B	2
+#define AUD_RESET_TDMIN_C	3
+#define AUD_RESET_TDMIN_LB	4
+#define AUD_RESET_LOOPBACK	5
+#define AUD_RESET_TODDR_A	6
+#define AUD_RESET_TODDR_B	7
+#define AUD_RESET_TODDR_C	8
+#define AUD_RESET_FRDDR_A	9
+#define AUD_RESET_FRDDR_B	10
+#define AUD_RESET_FRDDR_C	11
+#define AUD_RESET_TDMOUT_A	12
+#define AUD_RESET_TDMOUT_B	13
+#define AUD_RESET_TDMOUT_C	14
+#define AUD_RESET_SPDIFOUT	15
+#define AUD_RESET_SPDIFOUT_B	16
+#define AUD_RESET_SPDIFIN	17
+#define AUD_RESET_EQDRC		18
+#define AUD_RESET_RESAMPLE	19
+#define AUD_RESET_DDRARB	20
+#define AUD_RESET_POWDET	21
+#define AUD_RESET_TORAM		22
+#define AUD_RESET_TOACODEC	23
+#define AUD_RESET_TOHDMITX	24
+#define AUD_RESET_CLKTREE	25
+
+#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
new file mode 100644
index 0000000..6d487c5
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
+
+/*	RESET0					*/
+#define RESET_HIU			0
+/*					1	*/
+#define RESET_DOS			2
+/*					3-4	*/
+#define RESET_VIU			5
+#define RESET_AFIFO			6
+#define RESET_VID_PLL_DIV		7
+/*					8-9	*/
+#define RESET_VENC			10
+#define RESET_ASSIST			11
+#define RESET_PCIE_CTRL_A		12
+#define RESET_VCBUS			13
+#define RESET_PCIE_PHY			14
+#define RESET_PCIE_APB			15
+#define RESET_GIC			16
+#define RESET_CAPB3_DECODE		17
+/*					18	*/
+#define RESET_HDMITX_CAPB3		19
+#define RESET_DVALIN_CAPB3		20
+#define RESET_DOS_CAPB3			21
+/*					22	*/
+#define RESET_CBUS_CAPB3		23
+#define RESET_AHB_CNTL			24
+#define RESET_AHB_DATA			25
+#define RESET_VCBUS_CLK81		26
+/*					27-31	*/
+/*	RESET1					*/
+/*					32	*/
+#define RESET_DEMUX			33
+#define RESET_USB			34
+#define RESET_DDR			35
+/*					36	*/
+#define RESET_BT656			37
+#define RESET_AHB_SRAM			38
+/*					39	*/
+#define RESET_PARSER			40
+/*					41	*/
+#define RESET_ISA			42
+#define RESET_ETHERNET			43
+#define RESET_SD_EMMC_A			44
+#define RESET_SD_EMMC_B			45
+#define RESET_SD_EMMC_C			46
+/*					47	*/
+#define RESET_USB_PHY20			48
+#define RESET_USB_PHY21			49
+/*					50-60	*/
+#define RESET_AUDIO_CODEC		61
+/*					62-63	*/
+/*	RESET2					*/
+/*					64	*/
+#define RESET_AUDIO			65
+#define RESET_HDMITX_PHY		66
+/*					67	*/
+#define RESET_MIPI_DSI_HOST		68
+#define RESET_ALOCKER			69
+#define RESET_GE2D			70
+#define RESET_PARSER_REG		71
+#define RESET_PARSER_FETCH		72
+#define RESET_CTL			73
+#define RESET_PARSER_TOP		74
+/*					75-77	*/
+#define RESET_DVALIN			78
+#define RESET_HDMITX			79
+/*					80-95	*/
+/*	RESET3					*/
+/*					96-95	*/
+#define RESET_DEMUX_TOP			105
+#define RESET_DEMUX_DES_PL		106
+#define RESET_DEMUX_S2P_0		107
+#define RESET_DEMUX_S2P_1		108
+#define RESET_DEMUX_0			109
+#define RESET_DEMUX_1			110
+#define RESET_DEMUX_2			111
+/*					112-127	*/
+/*	RESET4					*/
+/*					128-129	*/
+#define RESET_MIPI_DSI_PHY		130
+/*					131-132	*/
+#define RESET_RDMA			133
+#define RESET_VENCI			134
+#define RESET_VENCP			135
+/*					136	*/
+#define RESET_VDAC			137
+/*					138-139 */
+#define RESET_VDI6			140
+#define RESET_VENCL			141
+#define RESET_I2C_M1			142
+#define RESET_I2C_M2			143
+/*					144-159	*/
+/*	RESET5					*/
+/*					160-191	*/
+/*	RESET6					*/
+#define RESET_GEN			192
+#define RESET_SPICC0			193
+#define RESET_SC			194
+#define RESET_SANA_3			195
+#define RESET_I2C_M0			196
+#define RESET_TS_PLL			197
+#define RESET_SPICC1			198
+#define RESET_STREAM			199
+#define RESET_TS_CPU			200
+#define RESET_UART0			201
+#define RESET_UART1_2			202
+#define RESET_ASYNC0			203
+#define RESET_ASYNC1			204
+#define RESET_SPIFC0			205
+#define RESET_I2C_M3			206
+/*					207-223	*/
+/*	RESET7					*/
+#define RESET_USB_DDR_0			224
+#define RESET_USB_DDR_1			225
+#define RESET_USB_DDR_2			226
+#define RESET_USB_DDR_3			227
+#define RESET_TS_GPU			228
+#define RESET_DEVICE_MMC_ARB		229
+#define RESET_DVALIN_DMC_PIPL		230
+#define RESET_VID_LOCK			231
+#define RESET_NIC_DMC_PIPL		232
+#define RESET_DMC_VPU_PIPL		233
+#define RESET_GE2D_DMC_PIPL		234
+#define RESET_HCODEC_DMC_PIPL		235
+#define RESET_WAVE420_DMC_PIPL		236
+#define RESET_HEVCF_DMC_PIPL		237
+/*					238-255	*/
+
+#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
new file mode 100644
index 0000000..524d607
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h
@@ -0,0 +1,210 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution
+ * in the file called COPYING.
+ *
+ * BSD LICENSE
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
+
+/*	RESET0					*/
+#define RESET_HIU			0
+/*					1	*/
+#define RESET_DOS_RESET			2
+#define RESET_DDR_TOP			3
+#define RESET_DCU_RESET			4
+#define RESET_VIU			5
+#define RESET_AIU			6
+#define RESET_VID_PLL_DIV		7
+/*					8	*/
+#define RESET_PMUX			9
+#define RESET_VENC			10
+#define RESET_ASSIST			11
+#define RESET_AFIFO2			12
+#define RESET_VCBUS			13
+/*					14	*/
+/*					15	*/
+#define RESET_GIC			16
+#define RESET_CAPB3_DECODE		17
+#define RESET_NAND_CAPB3		18
+#define RESET_HDMITX_CAPB3		19
+#define RESET_MALI_CAPB3		20
+#define RESET_DOS_CAPB3			21
+#define RESET_SYS_CPU_CAPB3		22
+#define RESET_CBUS_CAPB3		23
+#define RESET_AHB_CNTL			24
+#define RESET_AHB_DATA			25
+#define RESET_VCBUS_CLK81		26
+#define RESET_MMC			27
+#define RESET_MIPI_0			28
+#define RESET_MIPI_1			29
+#define RESET_MIPI_2			30
+#define RESET_MIPI_3			31
+/*	RESET1					*/
+#define RESET_CPPM			32
+#define RESET_DEMUX			33
+#define RESET_USB_OTG			34
+#define RESET_DDR			35
+#define RESET_AO_RESET			36
+#define RESET_BT656			37
+#define RESET_AHB_SRAM			38
+/*					39	*/
+#define RESET_PARSER			40
+#define RESET_BLKMV			41
+#define RESET_ISA			42
+#define RESET_ETHERNET			43
+#define RESET_SD_EMMC_A			44
+#define RESET_SD_EMMC_B			45
+#define RESET_SD_EMMC_C			46
+#define RESET_ROM_BOOT			47
+#define RESET_SYS_CPU_0			48
+#define RESET_SYS_CPU_1			49
+#define RESET_SYS_CPU_2			50
+#define RESET_SYS_CPU_3			51
+#define RESET_SYS_CPU_CORE_0		52
+#define RESET_SYS_CPU_CORE_1		53
+#define RESET_SYS_CPU_CORE_2		54
+#define RESET_SYS_CPU_CORE_3		55
+#define RESET_SYS_PLL_DIV		56
+#define RESET_SYS_CPU_AXI		57
+#define RESET_SYS_CPU_L2		58
+#define RESET_SYS_CPU_P			59
+#define RESET_SYS_CPU_MBIST		60
+/*					61	*/
+/*					62	*/
+/*					63	*/
+/*	RESET2					*/
+#define RESET_VD_RMEM			64
+#define RESET_AUDIN			65
+#define RESET_HDMI_TX			66
+/*					67	*/
+/*					68	*/
+/*					69	*/
+#define RESET_GE2D			70
+#define RESET_PARSER_REG		71
+#define RESET_PARSER_FETCH		72
+#define RESET_PARSER_CTL		73
+#define RESET_PARSER_TOP		74
+/*					75	*/
+/*					76	*/
+#define RESET_AO_CPU_RESET		77
+#define RESET_MALI			78
+#define RESET_HDMI_SYSTEM_RESET		79
+/*					80-95	*/
+/*	RESET3					*/
+#define RESET_RING_OSCILLATOR		96
+#define RESET_SYS_CPU			97
+#define RESET_EFUSE			98
+#define RESET_SYS_CPU_BVCI		99
+#define RESET_AIFIFO			100
+#define RESET_TVFE			101
+#define RESET_AHB_BRIDGE_CNTL		102
+/*					103	*/
+#define RESET_AUDIO_DAC			104
+#define RESET_DEMUX_TOP			105
+#define RESET_DEMUX_DES			106
+#define RESET_DEMUX_S2P_0		107
+#define RESET_DEMUX_S2P_1		108
+#define RESET_DEMUX_RESET_0		109
+#define RESET_DEMUX_RESET_1		110
+#define RESET_DEMUX_RESET_2		111
+/*					112-127	*/
+/*	RESET4					*/
+/*					128	*/
+/*					129	*/
+/*					130	*/
+/*					131	*/
+#define RESET_DVIN_RESET		132
+#define RESET_RDMA			133
+#define RESET_VENCI			134
+#define RESET_VENCP			135
+/*					136	*/
+#define RESET_VDAC			137
+#define RESET_RTC			138
+/*					139	*/
+#define RESET_VDI6			140
+#define RESET_VENCL			141
+#define RESET_I2C_MASTER_2		142
+#define RESET_I2C_MASTER_1		143
+/*					144-159	*/
+/*	RESET5					*/
+/*					160-191	*/
+/*	RESET6					*/
+#define RESET_PERIPHS_GENERAL		192
+#define RESET_PERIPHS_SPICC		193
+#define RESET_PERIPHS_SMART_CARD	194
+#define RESET_PERIPHS_SAR_ADC		195
+#define RESET_PERIPHS_I2C_MASTER_0	196
+#define RESET_SANA			197
+/*					198	*/
+#define RESET_PERIPHS_STREAM_INTERFACE	199
+#define RESET_PERIPHS_SDIO		200
+#define RESET_PERIPHS_UART_0		201
+#define RESET_PERIPHS_UART_1_2		202
+#define RESET_PERIPHS_ASYNC_0		203
+#define RESET_PERIPHS_ASYNC_1		204
+#define RESET_PERIPHS_SPI_0		205
+#define RESET_PERIPHS_SDHC		206
+#define RESET_UART_SLIP			207
+/*					208-223	*/
+/*	RESET7					*/
+#define RESET_USB_DDR_0			224
+#define RESET_USB_DDR_1			225
+#define RESET_USB_DDR_2			226
+#define RESET_USB_DDR_3			227
+/*					228	*/
+#define RESET_DEVICE_MMC_ARB		229
+/*					230	*/
+#define RESET_VID_LOCK			231
+#define RESET_A9_DMC_PIPEL		232
+/*					233-255	*/
+
+#endif
diff --git a/include/dt-bindings/reset/ast2500-reset.h b/include/dt-bindings/reset/ast2500-reset.h
new file mode 100644
index 0000000..d1b6b23
--- /dev/null
+++ b/include/dt-bindings/reset/ast2500-reset.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 Google, Inc
+ */
+
+#ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
+#define _ABI_MACH_ASPEED_AST2500_RESET_H_
+
+/*
+ * The values are intentionally layed out as flags in
+ * WDT reset parameter.
+ */
+
+#define AST_RESET_SOC			0
+#define AST_RESET_CHIP			1
+#define AST_RESET_CPU			(1 << 1)
+#define AST_RESET_ARM			(1 << 2)
+#define AST_RESET_COPROC		(1 << 3)
+#define AST_RESET_SDRAM			(1 << 4)
+#define AST_RESET_AHB			(1 << 5)
+#define AST_RESET_I2C			(1 << 6)
+#define AST_RESET_MAC1			(1 << 7)
+#define AST_RESET_MAC2			(1 << 8)
+#define AST_RESET_GCRT			(1 << 9)
+#define AST_RESET_USB20			(1 << 10)
+#define AST_RESET_USB11_HOST		(1 << 11)
+#define AST_RESET_USB11_HID		(1 << 12)
+#define AST_RESET_VIDEO			(1 << 13)
+#define AST_RESET_HAC			(1 << 14)
+#define AST_RESET_LPC			(1 << 15)
+#define AST_RESET_SDIO			(1 << 16)
+#define AST_RESET_MIC			(1 << 17)
+#define AST_RESET_CRT2D			(1 << 18)
+#define AST_RESET_PWM			(1 << 19)
+#define AST_RESET_PECI			(1 << 20)
+#define AST_RESET_JTAG			(1 << 21)
+#define AST_RESET_ADC			(1 << 22)
+#define AST_RESET_GPIO			(1 << 23)
+#define AST_RESET_MCTP			(1 << 24)
+#define AST_RESET_XDMA			(1 << 25)
+#define AST_RESET_SPI			(1 << 26)
+#define AST_RESET_MISC			(1 << 27)
+
+#endif  /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h
new file mode 100644
index 0000000..d342c0b
--- /dev/null
+++ b/include/dt-bindings/reset/axg-aoclkc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE		0
+#define RESET_AO_I2C_MASTER	1
+#define RESET_AO_I2C_SLAVE	2
+#define RESET_AO_UART1		3
+#define RESET_AO_UART2		4
+#define RESET_AO_IR_BLASTER	5
+
+#endif
diff --git a/include/dt-bindings/reset/bcm3380-reset.h b/include/dt-bindings/reset/bcm3380-reset.h
new file mode 100644
index 0000000..4cbf4d2
--- /dev/null
+++ b/include/dt-bindings/reset/bcm3380-reset.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from Broadcom GPL Source Code:
+ *	Copyright (C) Broadcom Corporation
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM3380_H
+#define __DT_BINDINGS_RESET_BCM3380_H
+
+#define BCM3380_RST0_SPI	0
+#define BCM3380_RST0_PCM	13
+
+#endif /* __DT_BINDINGS_RESET_BCM3380_H */
diff --git a/include/dt-bindings/reset/bcm6318-reset.h b/include/dt-bindings/reset/bcm6318-reset.h
new file mode 100644
index 0000000..1422500
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6318-reset.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6318_H
+#define __DT_BINDINGS_RESET_BCM6318_H
+
+#define BCM6318_RST_SPI		0
+#define BCM6318_RST_EPHY	1
+#define BCM6318_RST_SAR		2
+#define BCM6318_RST_ENETSW	3
+#define BCM6318_RST_USBD	4
+#define BCM6318_RST_USBH	5
+#define BCM6318_RST_PCIE_CORE	6
+#define BCM6318_RST_PCIE	7
+#define BCM6318_RST_PCIE_EXT	8
+#define BCM6318_RST_PCIE_HARD	9
+#define BCM6318_RST_ADSL	10
+#define BCM6318_RST_PHYMIPS	11
+#define BCM6318_RST_HOSTMIPS	11
+
+#endif /* __DT_BINDINGS_RESET_BCM6318_H */
diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h
new file mode 100644
index 0000000..a45abed
--- /dev/null
+++ b/include/dt-bindings/reset/bcm63268-reset.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM63268_H
+#define __DT_BINDINGS_RESET_BCM63268_H
+
+#define BCM63268_RST_SPI	0
+#define BCM63268_RST_IPSEC	1
+#define BCM63268_RST_EPHY	2
+#define BCM63268_RST_SAR	3
+#define BCM63268_RST_ENETSW	4
+#define BCM63268_RST_USBS	5
+#define BCM63268_RST_USBH	6
+#define BCM63268_RST_PCM	7
+#define BCM63268_RST_PCIE_CORE	8
+#define BCM63268_RST_PCIE	9
+#define BCM63268_RST_PCIE_EXT	10
+#define BCM63268_RST_WLAN_SHIM	11
+#define BCM63268_RST_DDR_PHY	12
+#define BCM63268_RST_FAP0	13
+#define BCM63268_RST_WLAN_UBUS	14
+#define BCM63268_RST_DECT	15
+#define BCM63268_RST_FAP1	16
+#define BCM63268_RST_PCIE_HARD	17
+#define BCM63268_RST_GPHY	18
+
+#endif /* __DT_BINDINGS_RESET_BCM63268_H */
diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h
new file mode 100644
index 0000000..f2dd4f7
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6328-reset.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6328_H
+#define __DT_BINDINGS_RESET_BCM6328_H
+
+#define BCM6328_RST_SPI		0
+#define BCM6328_RST_EPHY	1
+#define BCM6328_RST_SAR		2
+#define BCM6328_RST_ENETSW	3
+#define BCM6328_RST_USBS	4
+#define BCM6328_RST_USBH	5
+#define BCM6328_RST_PCM		6
+#define BCM6328_RST_PCIE_CORE	7
+#define BCM6328_RST_PCIE	8
+#define BCM6328_RST_PCIE_EXT	9
+#define BCM6328_RST_PCIE_HARD	10
+
+#endif /* __DT_BINDINGS_RESET_BCM6328_H */
diff --git a/include/dt-bindings/reset/bcm6338-reset.h b/include/dt-bindings/reset/bcm6338-reset.h
new file mode 100644
index 0000000..4aec7a4
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6338-reset.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6338_H
+#define __DT_BINDINGS_RESET_BCM6338_H
+
+#define BCM6338_RST_SPI		0
+#define BCM6338_RST_ENET	2
+#define BCM6338_RST_USBH	3
+#define BCM6338_RST_USBS	4
+#define BCM6338_RST_ADSL	5
+#define BCM6338_RST_DMAMEM	6
+#define BCM6338_RST_SAR		7
+#define BCM6338_RST_ACLC	8
+#define BCM6338_RST_ADSL_MIPS	10
+
+#endif /* __DT_BINDINGS_RESET_BCM6338_H */
diff --git a/include/dt-bindings/reset/bcm6348-reset.h b/include/dt-bindings/reset/bcm6348-reset.h
new file mode 100644
index 0000000..b298c18
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6348-reset.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6348_H
+#define __DT_BINDINGS_RESET_BCM6348_H
+
+#define BCM6348_RST_SPI		0
+#define BCM6348_RST_ENET	2
+#define BCM6348_RST_USBH	3
+#define BCM6348_RST_USBS	4
+#define BCM6348_RST_ADSL	5
+#define BCM6348_RST_DMAMEM	6
+#define BCM6348_RST_SAR		7
+#define BCM6348_RST_ACLC	8
+#define BCM6348_RST_ADSL_MIPS	10
+
+#endif /* __DT_BINDINGS_RESET_BCM6348_H */
diff --git a/include/dt-bindings/reset/bcm6358-reset.h b/include/dt-bindings/reset/bcm6358-reset.h
new file mode 100644
index 0000000..075706e
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6358-reset.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6358_H
+#define __DT_BINDINGS_RESET_BCM6358_H
+
+#define BCM6358_RST_SPI		0
+#define BCM6358_RST_ENET	2
+#define BCM6358_RST_MPI		3
+#define BCM6358_RST_EPHY	6
+#define BCM6358_RST_SAR		7
+#define BCM6358_RST_USBH	12
+#define BCM6358_RST_PCM		13
+#define BCM6358_RST_ADSL	14
+
+#endif /* __DT_BINDINGS_RESET_BCM6358_H */
diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h
new file mode 100644
index 0000000..8202e49
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6362-reset.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6362_H
+#define __DT_BINDINGS_RESET_BCM6362_H
+
+#define BCM6362_RST_SPI		0
+#define BCM6362_RST_IPSEC	1
+#define BCM6362_RST_EPHY	2
+#define BCM6362_RST_SAR		3
+#define BCM6362_RST_ENETSW	4
+#define BCM6362_RST_USBD	5
+#define BCM6362_RST_USBH	6
+#define BCM6362_RST_PCM		7
+#define BCM6362_RST_PCIE_CORE	8
+#define BCM6362_RST_PCIE	9
+#define BCM6362_RST_PCIE_EXT	10
+#define BCM6362_RST_WLAN_SHIM	11
+#define BCM6362_RST_DDR_PHY	12
+#define BCM6362_RST_FAP		13
+#define BCM6362_RST_WLAN_UBUS	14
+
+#endif /* __DT_BINDINGS_RESET_BCM6362_H */
diff --git a/include/dt-bindings/reset/bcm6368-reset.h b/include/dt-bindings/reset/bcm6368-reset.h
new file mode 100644
index 0000000..0038a7c
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6368-reset.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 �lvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6368_H
+#define __DT_BINDINGS_RESET_BCM6368_H
+
+#define BCM6368_RST_SPI		0
+#define BCM6368_RST_MPI		3
+#define BCM6368_RST_IPSEC	4
+#define BCM6368_RST_EPHY	6
+#define BCM6368_RST_SAR		7
+#define BCM6368_RST_SWITCH	10
+#define BCM6368_RST_USBD	11
+#define BCM6368_RST_USBH	12
+#define BCM6368_RST_PCM		13
+
+#endif /* __DT_BINDINGS_RESET_BCM6368_H */
diff --git a/include/dt-bindings/reset/g12a-aoclkc.h b/include/dt-bindings/reset/g12a-aoclkc.h
new file mode 100644
index 0000000..bd2e233
--- /dev/null
+++ b/include/dt-bindings/reset/g12a-aoclkc.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK
+
+#define RESET_AO_IR_IN		0
+#define RESET_AO_UART		1
+#define RESET_AO_I2C_M		2
+#define RESET_AO_I2C_S		3
+#define RESET_AO_SAR_ADC	4
+#define RESET_AO_UART2		5
+#define RESET_AO_IR_OUT		6
+
+#endif
diff --git a/include/dt-bindings/reset/gxbb-aoclkc.h b/include/dt-bindings/reset/gxbb-aoclkc.h
new file mode 100644
index 0000000..9e3fd60
--- /dev/null
+++ b/include/dt-bindings/reset/gxbb-aoclkc.h
@@ -0,0 +1,66 @@
+/*
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ * The full GNU General Public License is included in this distribution
+ * in the file called COPYING.
+ *
+ * BSD LICENSE
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *   * Neither the name of Intel Corporation nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK
+
+#define RESET_AO_REMOTE		0
+#define RESET_AO_I2C_MASTER	1
+#define RESET_AO_I2C_SLAVE	2
+#define RESET_AO_UART1		3
+#define RESET_AO_UART2		4
+#define RESET_AO_IR_BLASTER	5
+
+#endif
diff --git a/include/dt-bindings/reset/imx7-reset.h b/include/dt-bindings/reset/imx7-reset.h
new file mode 100644
index 0000000..bb92452
--- /dev/null
+++ b/include/dt-bindings/reset/imx7-reset.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2017 Impinj, Inc.
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ */
+
+#ifndef DT_BINDING_RESET_IMX7_H
+#define DT_BINDING_RESET_IMX7_H
+
+#define IMX7_RESET_A7_CORE_POR_RESET0	0
+#define IMX7_RESET_A7_CORE_POR_RESET1	1
+#define IMX7_RESET_A7_CORE_RESET0	2
+#define IMX7_RESET_A7_CORE_RESET1	3
+#define IMX7_RESET_A7_DBG_RESET0	4
+#define IMX7_RESET_A7_DBG_RESET1	5
+#define IMX7_RESET_A7_ETM_RESET0	6
+#define IMX7_RESET_A7_ETM_RESET1	7
+#define IMX7_RESET_A7_SOC_DBG_RESET	8
+#define IMX7_RESET_A7_L2RESET		9
+#define IMX7_RESET_SW_M4C_RST		10
+#define IMX7_RESET_SW_M4P_RST		11
+#define IMX7_RESET_EIM_RST		12
+#define IMX7_RESET_HSICPHY_PORT_RST	13
+#define IMX7_RESET_USBPHY1_POR		14
+#define IMX7_RESET_USBPHY1_PORT_RST	15
+#define IMX7_RESET_USBPHY2_POR		16
+#define IMX7_RESET_USBPHY2_PORT_RST	17
+#define IMX7_RESET_MIPI_PHY_MRST	18
+#define IMX7_RESET_MIPI_PHY_SRST	19
+
+/*
+ * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
+ * and PCIEPHY_G_RST
+ */
+#define IMX7_RESET_PCIEPHY		20
+#define IMX7_RESET_PCIEPHY_PERST	21
+
+/*
+ * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
+ * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
+ * of as one
+ */
+#define IMX7_RESET_PCIE_CTRL_APPS_EN	22
+#define IMX7_RESET_DDRC_PRST		23
+#define IMX7_RESET_DDRC_CORE_RST	24
+
+#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25
+
+#define IMX7_RESET_NUM			26
+
+#endif
diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h
new file mode 100755
index 0000000..9a30108
--- /dev/null
+++ b/include/dt-bindings/reset/imx8mq-reset.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ */
+
+#ifndef DT_BINDING_RESET_IMX8MQ_H
+#define DT_BINDING_RESET_IMX8MQ_H
+
+#define IMX8MQ_RESET_A53_CORE_POR_RESET0	0
+#define IMX8MQ_RESET_A53_CORE_POR_RESET1	1
+#define IMX8MQ_RESET_A53_CORE_POR_RESET2	2
+#define IMX8MQ_RESET_A53_CORE_POR_RESET3	3
+#define IMX8MQ_RESET_A53_CORE_RESET0		4
+#define IMX8MQ_RESET_A53_CORE_RESET1		5
+#define IMX8MQ_RESET_A53_CORE_RESET2		6
+#define IMX8MQ_RESET_A53_CORE_RESET3		7
+#define IMX8MQ_RESET_A53_DBG_RESET0		8
+#define IMX8MQ_RESET_A53_DBG_RESET1		9
+#define IMX8MQ_RESET_A53_DBG_RESET2		10
+#define IMX8MQ_RESET_A53_DBG_RESET3		11
+#define IMX8MQ_RESET_A53_ETM_RESET0		12
+#define IMX8MQ_RESET_A53_ETM_RESET1		13
+#define IMX8MQ_RESET_A53_ETM_RESET2		14
+#define IMX8MQ_RESET_A53_ETM_RESET3		15
+#define IMX8MQ_RESET_A53_SOC_DBG_RESET		16
+#define IMX8MQ_RESET_A53_L2RESET		17
+#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST	18
+#define IMX8MQ_RESET_OTG1_PHY_RESET		19
+#define IMX8MQ_RESET_OTG2_PHY_RESET		20
+#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N	21
+#define IMX8MQ_RESET_MIPI_DSI_RESET_N		22
+#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N	23
+#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N	24
+#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N	25
+#define IMX8MQ_RESET_PCIEPHY			26
+#define IMX8MQ_RESET_PCIEPHY_PERST		27
+#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN		28
+#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF	29
+#define IMX8MQ_RESET_HDMI_PHY_APB_RESET		30	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_DISP_RESET			31
+#define IMX8MQ_RESET_GPU_RESET			32
+#define IMX8MQ_RESET_VPU_RESET			33
+#define IMX8MQ_RESET_PCIEPHY2			34	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_PCIEPHY2_PERST		35	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN		36	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF	37	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET	38	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET	39	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET	40	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET	41	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET	42	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET	43	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_DDRC1_PRST			44
+#define IMX8MQ_RESET_DDRC1_CORE_RESET		45
+#define IMX8MQ_RESET_DDRC1_PHY_RESET		46
+#define IMX8MQ_RESET_DDRC2_PRST			47	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_DDRC2_CORE_RESET		48	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_DDRC2_PHY_RESET		49	/* i.MX8MM does NOT support */
+
+#define IMX8MQ_RESET_NUM			50
+
+#endif
diff --git a/include/dt-bindings/reset/mt7623-reset.h b/include/dt-bindings/reset/mt7623-reset.h
new file mode 100644
index 0000000..a859a5b
--- /dev/null
+++ b/include/dt-bindings/reset/mt7623-reset.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MTK_RESET_H_
+#define _DT_BINDINGS_MTK_RESET_H_
+
+/* ETHSYS resets */
+#define ETHSYS_PPE_RST			31
+#define ETHSYS_GMAC_RST			23
+#define ETHSYS_FE_RST			6
+#define ETHSYS_MCM_RST			2
+#define ETHSYS_SYS_RST			0
+
+/* HIFSYS resets */
+#define HIFSYS_PCIE2_RST		26
+#define HIFSYS_PCIE1_RST		25
+#define HIFSYS_PCIE0_RST		24
+#define HIFSYS_UPHY1_RST		22
+#define HIFSYS_UPHY0_RST		21
+#define HIFSYS_UHOST1_RST		4
+#define HIFSYS_UHOST0_RST		3
+
+#endif /* _DT_BINDINGS_MTK_RESET_H_ */
diff --git a/include/dt-bindings/reset/mt7628-reset.h b/include/dt-bindings/reset/mt7628-reset.h
new file mode 100644
index 0000000..2a674c1
--- /dev/null
+++ b/include/dt-bindings/reset/mt7628-reset.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_MT7628_RESET_H_
+#define _DT_BINDINGS_MT7628_RESET_H_
+
+#define MT7628_PWM_RST			31
+#define MT7628_SDXC_RST			30
+#define MT7628_CRYPTO_RST		29
+#define MT7628_AUX_STCK_RST		28
+#define MT7628_PCIE_RST			26
+#define MT7628_EPHY_RST			24
+#define MT7628_ETH_RST			23
+#define MT7628_UPHY_RST			22
+#define MT7628_UART2_RST		20
+#define MT7628_UART1_RST		19
+#define MT7628_SPI_RST			18
+#define MT7628_I2S_RST			17
+#define MT7628_I2C_RST			16
+#define MT7628_GDMA_RST			14
+#define MT7628_PIO_RST			13
+#define MT7628_UART0_RST		12
+#define MT7628_PCM_RST			11
+#define MT7628_MC_RST			10
+#define MT7628_INT_RST			9
+#define MT7628_TIMER_RST		8
+#define MT7628_HIF_RST			5
+#define MT7628_WIFI_RST			4
+#define MT7628_SPIS_RST			3
+#define MT7628_SYS_RST			0
+
+#endif /* _DT_BINDINGS_MT7628_RESET_H_ */
diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h
new file mode 100644
index 0000000..8f1634f
--- /dev/null
+++ b/include/dt-bindings/reset/mt7629-reset.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MTK_RESET_H_
+#define _DT_BINDINGS_MTK_RESET_H_
+
+/* PCIe Subsystem resets */
+#define PCIE1_CORE_RST			19
+#define PCIE1_MMIO_RST			20
+#define PCIE1_HRST			21
+#define PCIE1_USER_RST			22
+#define PCIE1_PIPE_RST			23
+#define PCIE0_CORE_RST			27
+#define PCIE0_MMIO_RST			28
+#define PCIE0_HRST			29
+#define PCIE0_USER_RST			30
+#define PCIE0_PIPE_RST			31
+
+/* SSUSB Subsystem resets */
+#define SSUSB_PHY_PWR_RST		3
+#define SSUSB_MAC_PWR_RST		4
+
+/* ETH Subsystem resets */
+#define ETHSYS_SYS_RST			0
+#define ETHSYS_MCM_RST			2
+#define ETHSYS_HSDMA_RST		5
+#define ETHSYS_FE_RST			6
+#define ETHSYS_ESW_RST			16
+#define ETHSYS_GMAC_RST			23
+#define ETHSYS_EPHY_RST			24
+#define ETHSYS_CRYPTO_RST		29
+#define ETHSYS_PPE_RST			31
+
+#endif /* _DT_BINDINGS_MTK_RESET_H_ */
diff --git a/include/dt-bindings/reset/stih407-resets.h b/include/dt-bindings/reset/stih407-resets.h
new file mode 100644
index 0000000..4ab3a1c
--- /dev/null
+++ b/include/dt-bindings/reset/stih407-resets.h
@@ -0,0 +1,65 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH407
+
+/* Powerdown requests control 0 */
+#define STIH407_EMISS_POWERDOWN		0
+#define STIH407_NAND_POWERDOWN		1
+
+/* Synp GMAC PowerDown */
+#define STIH407_ETH1_POWERDOWN		2
+
+/* Powerdown requests control 1 */
+#define STIH407_USB3_POWERDOWN		3
+#define STIH407_USB2_PORT1_POWERDOWN	4
+#define STIH407_USB2_PORT0_POWERDOWN	5
+#define STIH407_PCIE1_POWERDOWN		6
+#define STIH407_PCIE0_POWERDOWN		7
+#define STIH407_SATA1_POWERDOWN		8
+#define STIH407_SATA0_POWERDOWN		9
+
+/* Reset defines */
+#define STIH407_ETH1_SOFTRESET		0
+#define STIH407_MMC1_SOFTRESET		1
+#define STIH407_PICOPHY_SOFTRESET	2
+#define STIH407_IRB_SOFTRESET		3
+#define STIH407_PCIE0_SOFTRESET		4
+#define STIH407_PCIE1_SOFTRESET		5
+#define STIH407_SATA0_SOFTRESET		6
+#define STIH407_SATA1_SOFTRESET		7
+#define STIH407_MIPHY0_SOFTRESET	8
+#define STIH407_MIPHY1_SOFTRESET	9
+#define STIH407_MIPHY2_SOFTRESET	10
+#define STIH407_SATA0_PWR_SOFTRESET	11
+#define STIH407_SATA1_PWR_SOFTRESET	12
+#define STIH407_DELTA_SOFTRESET		13
+#define STIH407_BLITTER_SOFTRESET	14
+#define STIH407_HDTVOUT_SOFTRESET	15
+#define STIH407_HDQVDP_SOFTRESET	16
+#define STIH407_VDP_AUX_SOFTRESET	17
+#define STIH407_COMPO_SOFTRESET		18
+#define STIH407_HDMI_TX_PHY_SOFTRESET	19
+#define STIH407_JPEG_DEC_SOFTRESET	20
+#define STIH407_VP8_DEC_SOFTRESET	21
+#define STIH407_GPU_SOFTRESET		22
+#define STIH407_HVA_SOFTRESET		23
+#define STIH407_ERAM_HVA_SOFTRESET	24
+#define STIH407_LPM_SOFTRESET		25
+#define STIH407_KEYSCAN_SOFTRESET	26
+#define STIH407_USB2_PORT0_SOFTRESET	27
+#define STIH407_USB2_PORT1_SOFTRESET	28
+#define STIH407_ST231_AUD_SOFTRESET	29
+#define STIH407_ST231_DMU_SOFTRESET	30
+#define STIH407_ST231_GP0_SOFTRESET	31
+#define STIH407_ST231_GP1_SOFTRESET	32
+
+/* Picophy reset defines */
+#define STIH407_PICOPHY0_RESET		0
+#define STIH407_PICOPHY1_RESET		1
+#define STIH407_PICOPHY2_RESET		2
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h
new file mode 100644
index 0000000..f0c3aae
--- /dev/null
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
+ */
+
+#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
+#define _DT_BINDINGS_STM32MP1_RESET_H_
+
+#define LTDC_R		3072
+#define DSI_R		3076
+#define DDRPERFM_R	3080
+#define USBPHY_R	3088
+#define SPI6_R		3136
+#define I2C4_R		3138
+#define I2C6_R		3139
+#define USART1_R	3140
+#define STGEN_R		3156
+#define GPIOZ_R		3200
+#define CRYP1_R		3204
+#define HASH1_R		3205
+#define RNG1_R		3206
+#define AXIM_R		3216
+#define GPU_R		3269
+#define ETHMAC_R	3274
+#define FMC_R		3276
+#define QSPI_R		3278
+#define SDMMC1_R	3280
+#define SDMMC2_R	3281
+#define CRC1_R		3284
+#define USBH_R		3288
+#define MDMA_R		3328
+#define MCU_R		8225
+#define TIM2_R		19456
+#define TIM3_R		19457
+#define TIM4_R		19458
+#define TIM5_R		19459
+#define TIM6_R		19460
+#define TIM7_R		19461
+#define TIM12_R		16462
+#define TIM13_R		16463
+#define TIM14_R		16464
+#define LPTIM1_R	19465
+#define SPI2_R		19467
+#define SPI3_R		19468
+#define USART2_R	19470
+#define USART3_R	19471
+#define UART4_R		19472
+#define UART5_R		19473
+#define UART7_R		19474
+#define UART8_R		19475
+#define I2C1_R		19477
+#define I2C2_R		19478
+#define I2C3_R		19479
+#define I2C5_R		19480
+#define SPDIF_R		19482
+#define CEC_R		19483
+#define DAC12_R		19485
+#define MDIO_R		19847
+#define TIM1_R		19520
+#define TIM8_R		19521
+#define TIM15_R		19522
+#define TIM16_R		19523
+#define TIM17_R		19524
+#define SPI1_R		19528
+#define SPI4_R		19529
+#define SPI5_R		19530
+#define USART6_R	19533
+#define SAI1_R		19536
+#define SAI2_R		19537
+#define SAI3_R		19538
+#define DFSDM_R		19540
+#define FDCAN_R		19544
+#define LPTIM2_R	19584
+#define LPTIM3_R	19585
+#define LPTIM4_R	19586
+#define LPTIM5_R	19587
+#define SAI4_R		19592
+#define SYSCFG_R	19595
+#define VREF_R		19597
+#define TMPSENS_R	19600
+#define PMBCTRL_R	19601
+#define DMA1_R		19648
+#define DMA2_R		19649
+#define DMAMUX_R	19650
+#define ADC12_R		19653
+#define USBO_R		19656
+#define SDMMC3_R	19664
+#define CAMITF_R	19712
+#define CRYP2_R		19716
+#define HASH2_R		19717
+#define RNG2_R		19718
+#define CRC2_R		19719
+#define HSEM_R		19723
+#define MBOX_R		19724
+#define GPIOA_R		19776
+#define GPIOB_R		19777
+#define GPIOC_R		19778
+#define GPIOD_R		19779
+#define GPIOE_R		19780
+#define GPIOF_R		19781
+#define GPIOG_R		19782
+#define GPIOH_R		19783
+#define GPIOI_R		19784
+#define GPIOJ_R		19785
+#define GPIOK_R		19786
+
+#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
diff --git a/include/dt-bindings/reset/sun4i-a10-ccu.h b/include/dt-bindings/reset/sun4i-a10-ccu.h
new file mode 100644
index 0000000..5f4480b
--- /dev/null
+++ b/include/dt-bindings/reset/sun4i-a10-ccu.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN4I_A10_H
+#define _DT_BINDINGS_RST_SUN4I_A10_H
+
+#define	RST_USB_PHY0		1
+#define	RST_USB_PHY1		2
+#define	RST_USB_PHY2		3
+#define	RST_GPS			4
+#define	RST_DE_BE0		5
+#define	RST_DE_BE1		6
+#define	RST_DE_FE0		7
+#define	RST_DE_FE1		8
+#define	RST_DE_MP		9
+#define	RST_TVE0		10
+#define	RST_TCON0		11
+#define	RST_TVE1		12
+#define	RST_TCON1		13
+#define	RST_CSI0		14
+#define	RST_CSI1		15
+#define	RST_VE			16
+#define	RST_ACE			17
+#define	RST_LVDS		18
+#define	RST_GPU			19
+#define	RST_HDMI_H		20
+#define	RST_HDMI_SYS		21
+#define	RST_HDMI_AUDIO_DMA	22
+
+#endif /* DT_BINDINGS_RST_SUN4I_A10_H */
diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h b/include/dt-bindings/reset/sun50i-a64-ccu.h
new file mode 100644
index 0000000..db60b29
--- /dev/null
+++ b/include/dt-bindings/reset/sun50i-a64-ccu.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
+#define _DT_BINDINGS_RST_SUN50I_A64_H_
+
+#define RST_USB_PHY0		0
+#define RST_USB_PHY1		1
+#define RST_USB_HSIC		2
+#define RST_DRAM		3
+#define RST_MBUS		4
+#define RST_BUS_MIPI_DSI	5
+#define RST_BUS_CE		6
+#define RST_BUS_DMA		7
+#define RST_BUS_MMC0		8
+#define RST_BUS_MMC1		9
+#define RST_BUS_MMC2		10
+#define RST_BUS_NAND		11
+#define RST_BUS_DRAM		12
+#define RST_BUS_EMAC		13
+#define RST_BUS_TS		14
+#define RST_BUS_HSTIMER		15
+#define RST_BUS_SPI0		16
+#define RST_BUS_SPI1		17
+#define RST_BUS_OTG		18
+#define RST_BUS_EHCI0		19
+#define RST_BUS_EHCI1		20
+#define RST_BUS_OHCI0		21
+#define RST_BUS_OHCI1		22
+#define RST_BUS_VE		23
+#define RST_BUS_TCON0		24
+#define RST_BUS_TCON1		25
+#define RST_BUS_DEINTERLACE	26
+#define RST_BUS_CSI		27
+#define RST_BUS_HDMI0		28
+#define RST_BUS_HDMI1		29
+#define RST_BUS_DE		30
+#define RST_BUS_GPU		31
+#define RST_BUS_MSGBOX		32
+#define RST_BUS_SPINLOCK	33
+#define RST_BUS_DBG		34
+#define RST_BUS_LVDS		35
+#define RST_BUS_CODEC		36
+#define RST_BUS_SPDIF		37
+#define RST_BUS_THS		38
+#define RST_BUS_I2S0		39
+#define RST_BUS_I2S1		40
+#define RST_BUS_I2S2		41
+#define RST_BUS_I2C0		42
+#define RST_BUS_I2C1		43
+#define RST_BUS_I2C2		44
+#define RST_BUS_SCR		45
+#define RST_BUS_UART0		46
+#define RST_BUS_UART1		47
+#define RST_BUS_UART2		48
+#define RST_BUS_UART3		49
+#define RST_BUS_UART4		50
+
+#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */
diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h
new file mode 100644
index 0000000..81106f4
--- /dev/null
+++ b/include/dt-bindings/reset/sun50i-h6-ccu.h
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
+#define _DT_BINDINGS_RESET_SUN50I_H6_H_
+
+#define RST_MBUS		0
+#define RST_BUS_DE		1
+#define RST_BUS_DEINTERLACE	2
+#define RST_BUS_GPU		3
+#define RST_BUS_CE		4
+#define RST_BUS_VE		5
+#define RST_BUS_EMCE		6
+#define RST_BUS_VP9		7
+#define RST_BUS_DMA		8
+#define RST_BUS_MSGBOX		9
+#define RST_BUS_SPINLOCK	10
+#define RST_BUS_HSTIMER		11
+#define RST_BUS_DBG		12
+#define RST_BUS_PSI		13
+#define RST_BUS_PWM		14
+#define RST_BUS_IOMMU		15
+#define RST_BUS_DRAM		16
+#define RST_BUS_NAND		17
+#define RST_BUS_MMC0		18
+#define RST_BUS_MMC1		19
+#define RST_BUS_MMC2		20
+#define RST_BUS_UART0		21
+#define RST_BUS_UART1		22
+#define RST_BUS_UART2		23
+#define RST_BUS_UART3		24
+#define RST_BUS_I2C0		25
+#define RST_BUS_I2C1		26
+#define RST_BUS_I2C2		27
+#define RST_BUS_I2C3		28
+#define RST_BUS_SCR0		29
+#define RST_BUS_SCR1		30
+#define RST_BUS_SPI0		31
+#define RST_BUS_SPI1		32
+#define RST_BUS_EMAC		33
+#define RST_BUS_TS		34
+#define RST_BUS_IR_TX		35
+#define RST_BUS_THS		36
+#define RST_BUS_I2S0		37
+#define RST_BUS_I2S1		38
+#define RST_BUS_I2S2		39
+#define RST_BUS_I2S3		40
+#define RST_BUS_SPDIF		41
+#define RST_BUS_DMIC		42
+#define RST_BUS_AUDIO_HUB	43
+#define RST_USB_PHY0		44
+#define RST_USB_PHY1		45
+#define RST_USB_PHY3		46
+#define RST_USB_HSIC		47
+#define RST_BUS_OHCI0		48
+#define RST_BUS_OHCI3		49
+#define RST_BUS_EHCI0		50
+#define RST_BUS_XHCI		51
+#define RST_BUS_EHCI3		52
+#define RST_BUS_OTG		53
+#define RST_BUS_PCIE		54
+#define RST_PCIE_POWERUP	55
+#define RST_BUS_HDMI		56
+#define RST_BUS_HDMI_SUB	57
+#define RST_BUS_TCON_TOP	58
+#define RST_BUS_TCON_LCD0	59
+#define RST_BUS_TCON_TV0	60
+#define RST_BUS_CSI		61
+#define RST_BUS_HDCP		62
+
+#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */
diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
new file mode 100644
index 0000000..01c84db
--- /dev/null
+++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
+
+#define RST_R_APB1_TIMER	0
+#define RST_R_APB1_TWD		1
+#define RST_R_APB1_PWM		2
+#define RST_R_APB2_UART		3
+#define RST_R_APB2_I2C		4
+#define RST_R_APB1_IR		5
+#define RST_R_APB1_W1		6
+
+#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun5i-ccu.h b/include/dt-bindings/reset/sun5i-ccu.h
new file mode 100644
index 0000000..c2b9726
--- /dev/null
+++ b/include/dt-bindings/reset/sun5i-ccu.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2016 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _RST_SUN5I_H_
+#define _RST_SUN5I_H_
+
+#define RST_USB_PHY0	0
+#define RST_USB_PHY1	1
+#define RST_GPS		2
+#define RST_DE_BE	3
+#define RST_DE_FE	4
+#define RST_TVE		5
+#define RST_LCD		6
+#define RST_CSI		7
+#define RST_VE		8
+#define RST_GPU		9
+#define RST_IEP		10
+
+#endif /* _RST_SUN5I_H_ */
diff --git a/include/dt-bindings/reset/sun6i-a31-ccu.h b/include/dt-bindings/reset/sun6i-a31-ccu.h
new file mode 100644
index 0000000..fbff365
--- /dev/null
+++ b/include/dt-bindings/reset/sun6i-a31-ccu.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_
+#define _DT_BINDINGS_RST_SUN6I_A31_H_
+
+#define RST_USB_PHY0		0
+#define RST_USB_PHY1		1
+#define RST_USB_PHY2		2
+
+#define RST_AHB1_MIPI_DSI	3
+#define RST_AHB1_SS		4
+#define RST_AHB1_DMA		5
+#define RST_AHB1_MMC0		6
+#define RST_AHB1_MMC1		7
+#define RST_AHB1_MMC2		8
+#define RST_AHB1_MMC3		9
+#define RST_AHB1_NAND1		10
+#define RST_AHB1_NAND0		11
+#define RST_AHB1_SDRAM		12
+#define RST_AHB1_EMAC		13
+#define RST_AHB1_TS		14
+#define RST_AHB1_HSTIMER	15
+#define RST_AHB1_SPI0		16
+#define RST_AHB1_SPI1		17
+#define RST_AHB1_SPI2		18
+#define RST_AHB1_SPI3		19
+#define RST_AHB1_OTG		20
+#define RST_AHB1_EHCI0		21
+#define RST_AHB1_EHCI1		22
+#define RST_AHB1_OHCI0		23
+#define RST_AHB1_OHCI1		24
+#define RST_AHB1_OHCI2		25
+#define RST_AHB1_VE		26
+#define RST_AHB1_LCD0		27
+#define RST_AHB1_LCD1		28
+#define RST_AHB1_CSI		29
+#define RST_AHB1_HDMI		30
+#define RST_AHB1_BE0		31
+#define RST_AHB1_BE1		32
+#define RST_AHB1_FE0		33
+#define RST_AHB1_FE1		34
+#define RST_AHB1_MP		35
+#define RST_AHB1_GPU		36
+#define RST_AHB1_DEU0		37
+#define RST_AHB1_DEU1		38
+#define RST_AHB1_DRC0		39
+#define RST_AHB1_DRC1		40
+#define RST_AHB1_LVDS		41
+
+#define RST_APB1_CODEC		42
+#define RST_APB1_SPDIF		43
+#define RST_APB1_DIGITAL_MIC	44
+#define RST_APB1_DAUDIO0	45
+#define RST_APB1_DAUDIO1	46
+#define RST_APB2_I2C0		47
+#define RST_APB2_I2C1		48
+#define RST_APB2_I2C2		49
+#define RST_APB2_I2C3		50
+#define RST_APB2_UART0		51
+#define RST_APB2_UART1		52
+#define RST_APB2_UART2		53
+#define RST_APB2_UART3		54
+#define RST_APB2_UART4		55
+#define RST_APB2_UART5		56
+
+#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */
diff --git a/include/dt-bindings/reset/sun8i-a23-a33-ccu.h b/include/dt-bindings/reset/sun8i-a23-a33-ccu.h
new file mode 100644
index 0000000..6121f2b
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-a23-a33-ccu.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_
+#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_
+
+#define RST_USB_PHY0		0
+#define RST_USB_PHY1		1
+#define RST_USB_HSIC		2
+#define RST_MBUS		3
+#define RST_BUS_MIPI_DSI	4
+#define RST_BUS_SS		5
+#define RST_BUS_DMA		6
+#define RST_BUS_MMC0		7
+#define RST_BUS_MMC1		8
+#define RST_BUS_MMC2		9
+#define RST_BUS_NAND		10
+#define RST_BUS_DRAM		11
+#define RST_BUS_HSTIMER		12
+#define RST_BUS_SPI0		13
+#define RST_BUS_SPI1		14
+#define RST_BUS_OTG		15
+#define RST_BUS_EHCI		16
+#define RST_BUS_OHCI		17
+#define RST_BUS_VE		18
+#define RST_BUS_LCD		19
+#define RST_BUS_CSI		20
+#define RST_BUS_DE_BE		21
+#define RST_BUS_DE_FE		22
+#define RST_BUS_GPU		23
+#define RST_BUS_MSGBOX		24
+#define RST_BUS_SPINLOCK	25
+#define RST_BUS_DRC		26
+#define RST_BUS_SAT		27
+#define RST_BUS_LVDS		28
+#define RST_BUS_CODEC		29
+#define RST_BUS_I2S0		30
+#define RST_BUS_I2S1		31
+#define RST_BUS_I2C0		32
+#define RST_BUS_I2C1		33
+#define RST_BUS_I2C2		34
+#define RST_BUS_UART0		35
+#define RST_BUS_UART1		36
+#define RST_BUS_UART2		37
+#define RST_BUS_UART3		38
+#define RST_BUS_UART4		39
+
+#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */
diff --git a/include/dt-bindings/reset/sun8i-a83t-ccu.h b/include/dt-bindings/reset/sun8i-a83t-ccu.h
new file mode 100644
index 0000000..784f6e1
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-a83t-ccu.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
+#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
+
+#define RST_USB_PHY0		0
+#define RST_USB_PHY1		1
+#define RST_USB_HSIC		2
+
+#define RST_DRAM		3
+#define RST_MBUS		4
+
+#define RST_BUS_MIPI_DSI	5
+#define RST_BUS_SS		6
+#define RST_BUS_DMA		7
+#define RST_BUS_MMC0		8
+#define RST_BUS_MMC1		9
+#define RST_BUS_MMC2		10
+#define RST_BUS_NAND		11
+#define RST_BUS_DRAM		12
+#define RST_BUS_EMAC		13
+#define RST_BUS_HSTIMER		14
+#define RST_BUS_SPI0		15
+#define RST_BUS_SPI1		16
+#define RST_BUS_OTG		17
+#define RST_BUS_EHCI0		18
+#define RST_BUS_EHCI1		19
+#define RST_BUS_OHCI0		20
+
+#define RST_BUS_VE		21
+#define RST_BUS_TCON0		22
+#define RST_BUS_TCON1		23
+#define RST_BUS_CSI		24
+#define RST_BUS_HDMI0		25
+#define RST_BUS_HDMI1		26
+#define RST_BUS_DE		27
+#define RST_BUS_GPU		28
+#define RST_BUS_MSGBOX		29
+#define RST_BUS_SPINLOCK	30
+
+#define RST_BUS_LVDS		31
+
+#define RST_BUS_SPDIF		32
+#define RST_BUS_I2S0		33
+#define RST_BUS_I2S1		34
+#define RST_BUS_I2S2		35
+#define RST_BUS_TDM		36
+
+#define RST_BUS_I2C0		37
+#define RST_BUS_I2C1		38
+#define RST_BUS_I2C2		39
+#define RST_BUS_UART0		40
+#define RST_BUS_UART1		41
+#define RST_BUS_UART2		42
+#define RST_BUS_UART3		43
+#define RST_BUS_UART4		44
+
+#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun8i-de2.h b/include/dt-bindings/reset/sun8i-de2.h
new file mode 100644
index 0000000..9526017
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-de2.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_
+#define _DT_BINDINGS_RESET_SUN8I_DE2_H_
+
+#define RST_MIXER0	0
+#define RST_MIXER1	1
+#define RST_WB		2
+
+#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */
diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sun8i-h3-ccu.h
new file mode 100644
index 0000000..6b7af80
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-h3-ccu.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_
+#define _DT_BINDINGS_RST_SUN8I_H3_H_
+
+#define RST_USB_PHY0		0
+#define RST_USB_PHY1		1
+#define RST_USB_PHY2		2
+#define RST_USB_PHY3		3
+
+#define RST_MBUS		4
+
+#define RST_BUS_CE		5
+#define RST_BUS_DMA		6
+#define RST_BUS_MMC0		7
+#define RST_BUS_MMC1		8
+#define RST_BUS_MMC2		9
+#define RST_BUS_NAND		10
+#define RST_BUS_DRAM		11
+#define RST_BUS_EMAC		12
+#define RST_BUS_TS		13
+#define RST_BUS_HSTIMER		14
+#define RST_BUS_SPI0		15
+#define RST_BUS_SPI1		16
+#define RST_BUS_OTG		17
+#define RST_BUS_EHCI0		18
+#define RST_BUS_EHCI1		19
+#define RST_BUS_EHCI2		20
+#define RST_BUS_EHCI3		21
+#define RST_BUS_OHCI0		22
+#define RST_BUS_OHCI1		23
+#define RST_BUS_OHCI2		24
+#define RST_BUS_OHCI3		25
+#define RST_BUS_VE		26
+#define RST_BUS_TCON0		27
+#define RST_BUS_TCON1		28
+#define RST_BUS_DEINTERLACE	29
+#define RST_BUS_CSI		30
+#define RST_BUS_TVE		31
+#define RST_BUS_HDMI0		32
+#define RST_BUS_HDMI1		33
+#define RST_BUS_DE		34
+#define RST_BUS_GPU		35
+#define RST_BUS_MSGBOX		36
+#define RST_BUS_SPINLOCK	37
+#define RST_BUS_DBG		38
+#define RST_BUS_EPHY		39
+#define RST_BUS_CODEC		40
+#define RST_BUS_SPDIF		41
+#define RST_BUS_THS		42
+#define RST_BUS_I2S0		43
+#define RST_BUS_I2S1		44
+#define RST_BUS_I2S2		45
+#define RST_BUS_I2C0		46
+#define RST_BUS_I2C1		47
+#define RST_BUS_I2C2		48
+#define RST_BUS_UART0		49
+#define RST_BUS_UART1		50
+#define RST_BUS_UART2		51
+#define RST_BUS_UART3		52
+#define RST_BUS_SCR		53
+
+#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h
new file mode 100644
index 0000000..4ba64f3
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-r-ccu.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_
+#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_
+
+#define RST_APB0_IR		0
+#define RST_APB0_TIMER		1
+#define RST_APB0_RSB		2
+#define RST_APB0_UART		3
+/* 4 is reserved for RST_APB0_W1 on A31 */
+#define RST_APB0_I2C		5
+
+#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun8i-r40-ccu.h b/include/dt-bindings/reset/sun8i-r40-ccu.h
new file mode 100644
index 0000000..c5ebcf6
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-r40-ccu.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_
+#define _DT_BINDINGS_RST_SUN8I_R40_H_
+
+#define RST_USB_PHY0		0
+#define RST_USB_PHY1		1
+#define RST_USB_PHY2		2
+
+#define RST_DRAM		3
+#define RST_MBUS		4
+
+#define RST_BUS_MIPI_DSI	5
+#define RST_BUS_CE		6
+#define RST_BUS_DMA		7
+#define RST_BUS_MMC0		8
+#define RST_BUS_MMC1		9
+#define RST_BUS_MMC2		10
+#define RST_BUS_MMC3		11
+#define RST_BUS_NAND		12
+#define RST_BUS_DRAM		13
+#define RST_BUS_EMAC		14
+#define RST_BUS_TS		15
+#define RST_BUS_HSTIMER		16
+#define RST_BUS_SPI0		17
+#define RST_BUS_SPI1		18
+#define RST_BUS_SPI2		19
+#define RST_BUS_SPI3		20
+#define RST_BUS_SATA		21
+#define RST_BUS_OTG		22
+#define RST_BUS_EHCI0		23
+#define RST_BUS_EHCI1		24
+#define RST_BUS_EHCI2		25
+#define RST_BUS_OHCI0		26
+#define RST_BUS_OHCI1		27
+#define RST_BUS_OHCI2		28
+#define RST_BUS_VE		29
+#define RST_BUS_MP		30
+#define RST_BUS_DEINTERLACE	31
+#define RST_BUS_CSI0		32
+#define RST_BUS_CSI1		33
+#define RST_BUS_HDMI0		34
+#define RST_BUS_HDMI1		35
+#define RST_BUS_DE		36
+#define RST_BUS_TVE0		37
+#define RST_BUS_TVE1		38
+#define RST_BUS_TVE_TOP		39
+#define RST_BUS_GMAC		40
+#define RST_BUS_GPU		41
+#define RST_BUS_TVD0		42
+#define RST_BUS_TVD1		43
+#define RST_BUS_TVD2		44
+#define RST_BUS_TVD3		45
+#define RST_BUS_TVD_TOP		46
+#define RST_BUS_TCON_LCD0	47
+#define RST_BUS_TCON_LCD1	48
+#define RST_BUS_TCON_TV0	49
+#define RST_BUS_TCON_TV1	50
+#define RST_BUS_TCON_TOP	51
+#define RST_BUS_DBG		52
+#define RST_BUS_LVDS		53
+#define RST_BUS_CODEC		54
+#define RST_BUS_SPDIF		55
+#define RST_BUS_AC97		56
+#define RST_BUS_IR0		57
+#define RST_BUS_IR1		58
+#define RST_BUS_THS		59
+#define RST_BUS_KEYPAD		60
+#define RST_BUS_I2S0		61
+#define RST_BUS_I2S1		62
+#define RST_BUS_I2S2		63
+#define RST_BUS_I2C0		64
+#define RST_BUS_I2C1		65
+#define RST_BUS_I2C2		66
+#define RST_BUS_I2C3		67
+#define RST_BUS_CAN		68
+#define RST_BUS_SCR		69
+#define RST_BUS_PS20		70
+#define RST_BUS_PS21		71
+#define RST_BUS_I2C4		72
+#define RST_BUS_UART0		73
+#define RST_BUS_UART1		74
+#define RST_BUS_UART2		75
+#define RST_BUS_UART3		76
+#define RST_BUS_UART4		77
+#define RST_BUS_UART5		78
+#define RST_BUS_UART6		79
+#define RST_BUS_UART7		80
+
+#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */
diff --git a/include/dt-bindings/reset/sun8i-v3s-ccu.h b/include/dt-bindings/reset/sun8i-v3s-ccu.h
new file mode 100644
index 0000000..b58ef21
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-v3s-ccu.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun8i-v3s-ccu.h, which is
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_
+#define _DT_BINDINGS_RST_SUN8I_V3S_H_
+
+#define RST_USB_PHY0		0
+
+#define RST_MBUS		1
+
+#define RST_BUS_CE		5
+#define RST_BUS_DMA		6
+#define RST_BUS_MMC0		7
+#define RST_BUS_MMC1		8
+#define RST_BUS_MMC2		9
+#define RST_BUS_DRAM		11
+#define RST_BUS_EMAC		12
+#define RST_BUS_HSTIMER		14
+#define RST_BUS_SPI0		15
+#define RST_BUS_OTG		17
+#define RST_BUS_EHCI0		18
+#define RST_BUS_OHCI0		22
+#define RST_BUS_VE		26
+#define RST_BUS_TCON0		27
+#define RST_BUS_CSI		30
+#define RST_BUS_DE		34
+#define RST_BUS_DBG		38
+#define RST_BUS_EPHY		39
+#define RST_BUS_CODEC		40
+#define RST_BUS_I2C0		46
+#define RST_BUS_I2C1		47
+#define RST_BUS_UART0		49
+#define RST_BUS_UART1		50
+#define RST_BUS_UART2		51
+
+#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/reset/sun9i-a80-ccu.h b/include/dt-bindings/reset/sun9i-a80-ccu.h
new file mode 100644
index 0000000..4b8df4b
--- /dev/null
+++ b/include/dt-bindings/reset/sun9i-a80-ccu.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_
+#define _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_
+
+#define RST_BUS_FD		0
+#define RST_BUS_VE		1
+#define RST_BUS_GPU_CTRL	2
+#define RST_BUS_SS		3
+#define RST_BUS_MMC		4
+#define RST_BUS_NAND0		5
+#define RST_BUS_NAND1		6
+#define RST_BUS_SDRAM		7
+#define RST_BUS_SATA		8
+#define RST_BUS_TS		9
+#define RST_BUS_SPI0		10
+#define RST_BUS_SPI1		11
+#define RST_BUS_SPI2		12
+#define RST_BUS_SPI3		13
+
+#define RST_BUS_OTG		14
+#define RST_BUS_OTG_PHY		15
+#define RST_BUS_MIPI_HSI	16
+#define RST_BUS_GMAC		17
+#define RST_BUS_MSGBOX		18
+#define RST_BUS_SPINLOCK	19
+#define RST_BUS_HSTIMER		20
+#define RST_BUS_DMA		21
+
+#define RST_BUS_LCD0		22
+#define RST_BUS_LCD1		23
+#define RST_BUS_EDP		24
+#define RST_BUS_LVDS		25
+#define RST_BUS_CSI		26
+#define RST_BUS_HDMI0		27
+#define RST_BUS_HDMI1		28
+#define RST_BUS_DE		29
+#define RST_BUS_MP		30
+#define RST_BUS_GPU		31
+#define RST_BUS_MIPI_DSI	32
+
+#define RST_BUS_SPDIF		33
+#define RST_BUS_AC97		34
+#define RST_BUS_I2S0		35
+#define RST_BUS_I2S1		36
+#define RST_BUS_LRADC		37
+#define RST_BUS_GPADC		38
+#define RST_BUS_CIR_TX		39
+
+#define RST_BUS_I2C0		40
+#define RST_BUS_I2C1		41
+#define RST_BUS_I2C2		42
+#define RST_BUS_I2C3		43
+#define RST_BUS_I2C4		44
+#define RST_BUS_UART0		45
+#define RST_BUS_UART1		46
+#define RST_BUS_UART2		47
+#define RST_BUS_UART3		48
+#define RST_BUS_UART4		49
+#define RST_BUS_UART5		50
+
+#endif /* _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ */
diff --git a/include/dt-bindings/reset/sun9i-a80-de.h b/include/dt-bindings/reset/sun9i-a80-de.h
new file mode 100644
index 0000000..2050727
--- /dev/null
+++ b/include/dt-bindings/reset/sun9i-a80-de.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN9I_A80_DE_H_
+#define _DT_BINDINGS_RESET_SUN9I_A80_DE_H_
+
+#define RST_FE0		0
+#define RST_FE1		1
+#define RST_FE2		2
+#define RST_DEU0	3
+#define RST_DEU1	4
+#define RST_BE0		5
+#define RST_BE1		6
+#define RST_BE2		7
+#define RST_DRC0	8
+#define RST_DRC1	9
+#define RST_MERGE	10
+
+#endif /* _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ */
diff --git a/include/dt-bindings/reset/sun9i-a80-usb.h b/include/dt-bindings/reset/sun9i-a80-usb.h
new file mode 100644
index 0000000..ee49286
--- /dev/null
+++ b/include/dt-bindings/reset/sun9i-a80-usb.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN9I_A80_USB_H_
+#define _DT_BINDINGS_RESET_SUN9I_A80_USB_H_
+
+#define RST_USB0_HCI	0
+#define RST_USB1_HCI	1
+#define RST_USB2_HCI	2
+
+#define RST_USB0_PHY	3
+#define RST_USB1_HSIC	4
+#define RST_USB1_PHY	5
+#define RST_USB2_HSIC	6
+#define RST_USB2_PHY	7
+
+#endif /* _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ */
diff --git a/include/dt-bindings/reset/tegra124-car.h b/include/dt-bindings/reset/tegra124-car.h
new file mode 100644
index 0000000..070e4f6
--- /dev/null
+++ b/include/dt-bindings/reset/tegra124-car.h
@@ -0,0 +1,12 @@
+/*
+ * This header provides Tegra124-specific constants for binding
+ * nvidia,tegra124-car.
+ */
+
+#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H
+#define _DT_BINDINGS_RESET_TEGRA124_CAR_H
+
+#define TEGRA124_RESET(x)		(6 * 32 + (x))
+#define TEGRA124_RST_DFLL_DVCO		TEGRA124_RESET(0)
+
+#endif	/* _DT_BINDINGS_RESET_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/reset/tegra186-reset.h b/include/dt-bindings/reset/tegra186-reset.h
new file mode 100644
index 0000000..7efec92
--- /dev/null
+++ b/include/dt-bindings/reset/tegra186-reset.h
@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.
+ */
+
+#ifndef _ABI_MACH_T186_RESET_T186_H_
+#define _ABI_MACH_T186_RESET_T186_H_
+
+#define TEGRA186_RESET_ACTMON			0
+#define TEGRA186_RESET_AFI			1
+#define TEGRA186_RESET_CEC			2
+#define TEGRA186_RESET_CSITE			3
+#define TEGRA186_RESET_DP2			4
+#define TEGRA186_RESET_DPAUX			5
+#define TEGRA186_RESET_DSI			6
+#define TEGRA186_RESET_DSIB			7
+#define TEGRA186_RESET_DTV			8
+#define TEGRA186_RESET_DVFS			9
+#define TEGRA186_RESET_ENTROPY			10
+#define TEGRA186_RESET_EXTPERIPH1		11
+#define TEGRA186_RESET_EXTPERIPH2		12
+#define TEGRA186_RESET_EXTPERIPH3		13
+#define TEGRA186_RESET_GPU			14
+#define TEGRA186_RESET_HDA			15
+#define TEGRA186_RESET_HDA2CODEC_2X		16
+#define TEGRA186_RESET_HDA2HDMICODEC		17
+#define TEGRA186_RESET_HOST1X			18
+#define TEGRA186_RESET_I2C1			19
+#define TEGRA186_RESET_I2C2			20
+#define TEGRA186_RESET_I2C3			21
+#define TEGRA186_RESET_I2C4			22
+#define TEGRA186_RESET_I2C5			23
+#define TEGRA186_RESET_I2C6			24
+#define TEGRA186_RESET_ISP			25
+#define TEGRA186_RESET_KFUSE			26
+#define TEGRA186_RESET_LA			27
+#define TEGRA186_RESET_MIPI_CAL			28
+#define TEGRA186_RESET_PCIE			29
+#define TEGRA186_RESET_PCIEXCLK			30
+#define TEGRA186_RESET_SATA			31
+#define TEGRA186_RESET_SATACOLD			32
+#define TEGRA186_RESET_SDMMC1			33
+#define TEGRA186_RESET_SDMMC2			34
+#define TEGRA186_RESET_SDMMC3			35
+#define TEGRA186_RESET_SDMMC4			36
+#define TEGRA186_RESET_SE			37
+#define TEGRA186_RESET_SOC_THERM		38
+#define TEGRA186_RESET_SOR0			39
+#define TEGRA186_RESET_SPI1			40
+#define TEGRA186_RESET_SPI2			41
+#define TEGRA186_RESET_SPI3			42
+#define TEGRA186_RESET_SPI4			43
+#define TEGRA186_RESET_TMR			44
+#define TEGRA186_RESET_TRIG_SYS			45
+#define TEGRA186_RESET_TSEC			46
+#define TEGRA186_RESET_UARTA			47
+#define TEGRA186_RESET_UARTB			48
+#define TEGRA186_RESET_UARTC			49
+#define TEGRA186_RESET_UARTD			50
+#define TEGRA186_RESET_VI			51
+#define TEGRA186_RESET_VIC			52
+#define TEGRA186_RESET_XUSB_DEV			53
+#define TEGRA186_RESET_XUSB_HOST		54
+#define TEGRA186_RESET_XUSB_PADCTL		55
+#define TEGRA186_RESET_XUSB_SS			56
+#define TEGRA186_RESET_AON_APB			57
+#define TEGRA186_RESET_AXI_CBB			58
+#define TEGRA186_RESET_BPMP_APB			59
+#define TEGRA186_RESET_CAN1			60
+#define TEGRA186_RESET_CAN2			61
+#define TEGRA186_RESET_DMIC5			62
+#define TEGRA186_RESET_DSIC			63
+#define TEGRA186_RESET_DSID			64
+#define TEGRA186_RESET_EMC_EMC			65
+#define TEGRA186_RESET_EMC_MEM			66
+#define TEGRA186_RESET_EMCSB_EMC		67
+#define TEGRA186_RESET_EMCSB_MEM		68
+#define TEGRA186_RESET_EQOS			69
+#define TEGRA186_RESET_GPCDMA			70
+#define TEGRA186_RESET_GPIO_CTL0		71
+#define TEGRA186_RESET_GPIO_CTL1		72
+#define TEGRA186_RESET_GPIO_CTL2		73
+#define TEGRA186_RESET_GPIO_CTL3		74
+#define TEGRA186_RESET_GPIO_CTL4		75
+#define TEGRA186_RESET_GPIO_CTL5		76
+#define TEGRA186_RESET_I2C10			77
+#define TEGRA186_RESET_I2C12			78
+#define TEGRA186_RESET_I2C13			79
+#define TEGRA186_RESET_I2C14			80
+#define TEGRA186_RESET_I2C7			81
+#define TEGRA186_RESET_I2C8			82
+#define TEGRA186_RESET_I2C9			83
+#define TEGRA186_RESET_JTAG2AXI			84
+#define TEGRA186_RESET_MPHY_IOBIST		85
+#define TEGRA186_RESET_MPHY_L0_RX		86
+#define TEGRA186_RESET_MPHY_L0_TX		87
+#define TEGRA186_RESET_NVCSI			88
+#define TEGRA186_RESET_NVDISPLAY0_HEAD0		89
+#define TEGRA186_RESET_NVDISPLAY0_HEAD1		90
+#define TEGRA186_RESET_NVDISPLAY0_HEAD2		91
+#define TEGRA186_RESET_NVDISPLAY0_MISC		92
+#define TEGRA186_RESET_NVDISPLAY0_WGRP0		93
+#define TEGRA186_RESET_NVDISPLAY0_WGRP1		94
+#define TEGRA186_RESET_NVDISPLAY0_WGRP2		95
+#define TEGRA186_RESET_NVDISPLAY0_WGRP3		96
+#define TEGRA186_RESET_NVDISPLAY0_WGRP4		97
+#define TEGRA186_RESET_NVDISPLAY0_WGRP5		98
+#define TEGRA186_RESET_PWM1			99
+#define TEGRA186_RESET_PWM2			100
+#define TEGRA186_RESET_PWM3			101
+#define TEGRA186_RESET_PWM4			102
+#define TEGRA186_RESET_PWM5			103
+#define TEGRA186_RESET_PWM6			104
+#define TEGRA186_RESET_PWM7			105
+#define TEGRA186_RESET_PWM8			106
+#define TEGRA186_RESET_SCE_APB			107
+#define TEGRA186_RESET_SOR1			108
+#define TEGRA186_RESET_TACH			109
+#define TEGRA186_RESET_TSC			110
+#define TEGRA186_RESET_UARTF			111
+#define TEGRA186_RESET_UARTG			112
+#define TEGRA186_RESET_UFSHC			113
+#define TEGRA186_RESET_UFSHC_AXI_M		114
+#define TEGRA186_RESET_UPHY			115
+#define TEGRA186_RESET_ADSP			116
+#define TEGRA186_RESET_ADSPDBG			117
+#define TEGRA186_RESET_ADSPINTF			118
+#define TEGRA186_RESET_ADSPNEON			119
+#define TEGRA186_RESET_ADSPPERIPH		120
+#define TEGRA186_RESET_ADSPSCU			121
+#define TEGRA186_RESET_ADSPWDT			122
+#define TEGRA186_RESET_APE			123
+#define TEGRA186_RESET_DPAUX1			124
+#define TEGRA186_RESET_NVDEC			125
+#define TEGRA186_RESET_NVENC			126
+#define TEGRA186_RESET_NVJPG			127
+#define TEGRA186_RESET_PEX_USB_UPHY		128
+#define TEGRA186_RESET_QSPI			129
+#define TEGRA186_RESET_TSECB			130
+#define TEGRA186_RESET_VI_I2C			131
+#define TEGRA186_RESET_UARTE			132
+#define TEGRA186_RESET_TOP_GTE			133
+#define TEGRA186_RESET_SHSP			134
+#define TEGRA186_RESET_PEX_USB_UPHY_L5		135
+#define TEGRA186_RESET_PEX_USB_UPHY_L4		136
+#define TEGRA186_RESET_PEX_USB_UPHY_L3		137
+#define TEGRA186_RESET_PEX_USB_UPHY_L2		138
+#define TEGRA186_RESET_PEX_USB_UPHY_L1		139
+#define TEGRA186_RESET_PEX_USB_UPHY_L0		140
+#define TEGRA186_RESET_PEX_USB_UPHY_PLL1	141
+#define TEGRA186_RESET_PEX_USB_UPHY_PLL0	142
+#define TEGRA186_RESET_TSCTNVI			143
+#define TEGRA186_RESET_EXTPERIPH4		144
+#define TEGRA186_RESET_DSIPADCTL		145
+#define TEGRA186_RESET_AUD_MCLK			146
+#define TEGRA186_RESET_MPHY_CLK_CTL		147
+#define TEGRA186_RESET_MPHY_L1_RX		148
+#define TEGRA186_RESET_MPHY_L1_TX		149
+#define TEGRA186_RESET_UFSHC_LP			150
+#define TEGRA186_RESET_BPMP_NIC			151
+#define TEGRA186_RESET_BPMP_NSYSPORESET		152
+#define TEGRA186_RESET_BPMP_NRESET		153
+#define TEGRA186_RESET_BPMP_DBGRESETN		154
+#define TEGRA186_RESET_BPMP_PRESETDBGN		155
+#define TEGRA186_RESET_BPMP_PM			156
+#define TEGRA186_RESET_BPMP_CVC			157
+#define TEGRA186_RESET_BPMP_DMA			158
+#define TEGRA186_RESET_BPMP_HSP			159
+#define TEGRA186_RESET_TSCTNBPMP		160
+#define TEGRA186_RESET_BPMP_TKE			161
+#define TEGRA186_RESET_BPMP_GTE			162
+#define TEGRA186_RESET_BPMP_PM_ACTMON		163
+#define TEGRA186_RESET_AON_NIC			164
+#define TEGRA186_RESET_AON_NSYSPORESET		165
+#define TEGRA186_RESET_AON_NRESET		166
+#define TEGRA186_RESET_AON_DBGRESETN		167
+#define TEGRA186_RESET_AON_PRESETDBGN		168
+#define TEGRA186_RESET_AON_ACTMON		169
+#define TEGRA186_RESET_AOPM			170
+#define TEGRA186_RESET_AOVC			171
+#define TEGRA186_RESET_AON_DMA			172
+#define TEGRA186_RESET_AON_GPIO			173
+#define TEGRA186_RESET_AON_HSP			174
+#define TEGRA186_RESET_TSCTNAON			175
+#define TEGRA186_RESET_AON_TKE			176
+#define TEGRA186_RESET_AON_GTE			177
+#define TEGRA186_RESET_SCE_NIC			178
+#define TEGRA186_RESET_SCE_NSYSPORESET		179
+#define TEGRA186_RESET_SCE_NRESET		180
+#define TEGRA186_RESET_SCE_DBGRESETN		181
+#define TEGRA186_RESET_SCE_PRESETDBGN		182
+#define TEGRA186_RESET_SCE_ACTMON		183
+#define TEGRA186_RESET_SCE_PM			184
+#define TEGRA186_RESET_SCE_DMA			185
+#define TEGRA186_RESET_SCE_HSP			186
+#define TEGRA186_RESET_TSCTNSCE			187
+#define TEGRA186_RESET_SCE_TKE			188
+#define TEGRA186_RESET_SCE_GTE			189
+#define TEGRA186_RESET_SCE_CFG			190
+#define TEGRA186_RESET_ADSP_ALL			191
+/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */
+#define TEGRA186_RESET_UFSHC_LP_SEQ		192
+#define TEGRA186_RESET_SIZE			193
+
+#endif
diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h
new file mode 100644
index 0000000..884fd91
--- /dev/null
+++ b/include/dt-bindings/reset/ti-syscon.h
@@ -0,0 +1,38 @@
+/*
+ * TI Syscon Reset definitions
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__
+#define __DT_BINDINGS_RESET_TI_SYSCON_H__
+
+/*
+ * The reset does not support the feature and corresponding
+ * values are not valid
+ */
+#define ASSERT_NONE	(1 << 0)
+#define DEASSERT_NONE	(1 << 1)
+#define STATUS_NONE	(1 << 2)
+
+/* When set this function is activated by setting(vs clearing) this bit */
+#define ASSERT_SET	(1 << 3)
+#define DEASSERT_SET	(1 << 4)
+#define STATUS_SET	(1 << 5)
+
+/* The following are the inverse of the above and are added for consistency */
+#define ASSERT_CLEAR	(0 << 3)
+#define DEASSERT_CLEAR	(0 << 4)
+#define STATUS_CLEAR	(0 << 5)
+
+#endif
diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
new file mode 100644
index 0000000..d44525b
--- /dev/null
+++ b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
+#define _DT_BINDINGS_ZYNQMP_RESETS_H
+
+#define		ZYNQMP_RESET_PCIE_CFG		0
+#define		ZYNQMP_RESET_PCIE_BRIDGE	1
+#define		ZYNQMP_RESET_PCIE_CTRL		2
+#define		ZYNQMP_RESET_DP			3
+#define		ZYNQMP_RESET_SWDT_CRF		4
+#define		ZYNQMP_RESET_AFI_FM5		5
+#define		ZYNQMP_RESET_AFI_FM4		6
+#define		ZYNQMP_RESET_AFI_FM3		7
+#define		ZYNQMP_RESET_AFI_FM2		8
+#define		ZYNQMP_RESET_AFI_FM1		9
+#define		ZYNQMP_RESET_AFI_FM0		10
+#define		ZYNQMP_RESET_GDMA		11
+#define		ZYNQMP_RESET_GPU_PP1		12
+#define		ZYNQMP_RESET_GPU_PP0		13
+#define		ZYNQMP_RESET_GPU		14
+#define		ZYNQMP_RESET_GT			15
+#define		ZYNQMP_RESET_SATA		16
+#define		ZYNQMP_RESET_ACPU3_PWRON	17
+#define		ZYNQMP_RESET_ACPU2_PWRON	18
+#define		ZYNQMP_RESET_ACPU1_PWRON	19
+#define		ZYNQMP_RESET_ACPU0_PWRON	20
+#define		ZYNQMP_RESET_APU_L2		21
+#define		ZYNQMP_RESET_ACPU3		22
+#define		ZYNQMP_RESET_ACPU2		23
+#define		ZYNQMP_RESET_ACPU1		24
+#define		ZYNQMP_RESET_ACPU0		25
+#define		ZYNQMP_RESET_DDR		26
+#define		ZYNQMP_RESET_APM_FPD		27
+#define		ZYNQMP_RESET_SOFT		28
+#define		ZYNQMP_RESET_GEM0		29
+#define		ZYNQMP_RESET_GEM1		30
+#define		ZYNQMP_RESET_GEM2		31
+#define		ZYNQMP_RESET_GEM3		32
+#define		ZYNQMP_RESET_QSPI		33
+#define		ZYNQMP_RESET_UART0		34
+#define		ZYNQMP_RESET_UART1		35
+#define		ZYNQMP_RESET_SPI0		36
+#define		ZYNQMP_RESET_SPI1		37
+#define		ZYNQMP_RESET_SDIO0		38
+#define		ZYNQMP_RESET_SDIO1		39
+#define		ZYNQMP_RESET_CAN0		40
+#define		ZYNQMP_RESET_CAN1		41
+#define		ZYNQMP_RESET_I2C0		42
+#define		ZYNQMP_RESET_I2C1		43
+#define		ZYNQMP_RESET_TTC0		44
+#define		ZYNQMP_RESET_TTC1		45
+#define		ZYNQMP_RESET_TTC2		46
+#define		ZYNQMP_RESET_TTC3		47
+#define		ZYNQMP_RESET_SWDT_CRL		48
+#define		ZYNQMP_RESET_NAND		49
+#define		ZYNQMP_RESET_ADMA		50
+#define		ZYNQMP_RESET_GPIO		51
+#define		ZYNQMP_RESET_IOU_CC		52
+#define		ZYNQMP_RESET_TIMESTAMP		53
+#define		ZYNQMP_RESET_RPU_R50		54
+#define		ZYNQMP_RESET_RPU_R51		55
+#define		ZYNQMP_RESET_RPU_AMBA		56
+#define		ZYNQMP_RESET_OCM		57
+#define		ZYNQMP_RESET_RPU_PGE		58
+#define		ZYNQMP_RESET_USB0_CORERESET	59
+#define		ZYNQMP_RESET_USB1_CORERESET	60
+#define		ZYNQMP_RESET_USB0_HIBERRESET	61
+#define		ZYNQMP_RESET_USB1_HIBERRESET	62
+#define		ZYNQMP_RESET_USB0_APB		63
+#define		ZYNQMP_RESET_USB1_APB		64
+#define		ZYNQMP_RESET_IPI		65
+#define		ZYNQMP_RESET_APM_LPD		66
+#define		ZYNQMP_RESET_RTC		67
+#define		ZYNQMP_RESET_SYSMON		68
+#define		ZYNQMP_RESET_AFI_FM6		69
+#define		ZYNQMP_RESET_LPD_SWDT		70
+#define		ZYNQMP_RESET_FPD		71
+#define		ZYNQMP_RESET_RPU_DBG1		72
+#define		ZYNQMP_RESET_RPU_DBG0		73
+#define		ZYNQMP_RESET_DBG_LPD		74
+#define		ZYNQMP_RESET_DBG_FPD		75
+#define		ZYNQMP_RESET_APLL		76
+#define		ZYNQMP_RESET_DPLL		77
+#define		ZYNQMP_RESET_VPLL		78
+#define		ZYNQMP_RESET_IOPLL		79
+#define		ZYNQMP_RESET_RPLL		80
+#define		ZYNQMP_RESET_GPO3_PL_0		81
+#define		ZYNQMP_RESET_GPO3_PL_1		82
+#define		ZYNQMP_RESET_GPO3_PL_2		83
+#define		ZYNQMP_RESET_GPO3_PL_3		84
+#define		ZYNQMP_RESET_GPO3_PL_4		85
+#define		ZYNQMP_RESET_GPO3_PL_5		86
+#define		ZYNQMP_RESET_GPO3_PL_6		87
+#define		ZYNQMP_RESET_GPO3_PL_7		88
+#define		ZYNQMP_RESET_GPO3_PL_8		89
+#define		ZYNQMP_RESET_GPO3_PL_9		90
+#define		ZYNQMP_RESET_GPO3_PL_10		91
+#define		ZYNQMP_RESET_GPO3_PL_11		92
+#define		ZYNQMP_RESET_GPO3_PL_12		93
+#define		ZYNQMP_RESET_GPO3_PL_13		94
+#define		ZYNQMP_RESET_GPO3_PL_14		95
+#define		ZYNQMP_RESET_GPO3_PL_15		96
+#define		ZYNQMP_RESET_GPO3_PL_16		97
+#define		ZYNQMP_RESET_GPO3_PL_17		98
+#define		ZYNQMP_RESET_GPO3_PL_18		99
+#define		ZYNQMP_RESET_GPO3_PL_19		100
+#define		ZYNQMP_RESET_GPO3_PL_20		101
+#define		ZYNQMP_RESET_GPO3_PL_21		102
+#define		ZYNQMP_RESET_GPO3_PL_22		103
+#define		ZYNQMP_RESET_GPO3_PL_23		104
+#define		ZYNQMP_RESET_GPO3_PL_24		105
+#define		ZYNQMP_RESET_GPO3_PL_25		106
+#define		ZYNQMP_RESET_GPO3_PL_26		107
+#define		ZYNQMP_RESET_GPO3_PL_27		108
+#define		ZYNQMP_RESET_GPO3_PL_28		109
+#define		ZYNQMP_RESET_GPO3_PL_29		110
+#define		ZYNQMP_RESET_GPO3_PL_30		111
+#define		ZYNQMP_RESET_GPO3_PL_31		112
+#define		ZYNQMP_RESET_RPU_LS		113
+#define		ZYNQMP_RESET_PS_ONLY		114
+#define		ZYNQMP_RESET_PL			115
+#define		ZYNQMP_RESET_PS_PL0		116
+#define		ZYNQMP_RESET_PS_PL1		117
+#define		ZYNQMP_RESET_PS_PL2		118
+#define		ZYNQMP_RESET_PS_PL3		119
+
+#endif
diff --git a/include/dt-bindings/soc/bcm2835-pm.h b/include/dt-bindings/soc/bcm2835-pm.h
new file mode 100644
index 0000000..153d75b
--- /dev/null
+++ b/include/dt-bindings/soc/bcm2835-pm.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+
+#ifndef _DT_BINDINGS_ARM_BCM2835_PM_H
+#define _DT_BINDINGS_ARM_BCM2835_PM_H
+
+#define BCM2835_POWER_DOMAIN_GRAFX		0
+#define BCM2835_POWER_DOMAIN_GRAFX_V3D		1
+#define BCM2835_POWER_DOMAIN_IMAGE		2
+#define BCM2835_POWER_DOMAIN_IMAGE_PERI		3
+#define BCM2835_POWER_DOMAIN_IMAGE_ISP		4
+#define BCM2835_POWER_DOMAIN_IMAGE_H264		5
+#define BCM2835_POWER_DOMAIN_USB		6
+#define BCM2835_POWER_DOMAIN_DSI0		7
+#define BCM2835_POWER_DOMAIN_DSI1		8
+#define BCM2835_POWER_DOMAIN_CAM0		9
+#define BCM2835_POWER_DOMAIN_CAM1		10
+#define BCM2835_POWER_DOMAIN_CCP2TX		11
+#define BCM2835_POWER_DOMAIN_HDMI		12
+
+#define BCM2835_POWER_DOMAIN_COUNT		13
+
+#define BCM2835_RESET_V3D			0
+#define BCM2835_RESET_ISP			1
+#define BCM2835_RESET_H264			2
+
+#define BCM2835_RESET_COUNT			3
+
+#endif /* _DT_BINDINGS_ARM_BCM2835_PM_H */
diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h
new file mode 100644
index 0000000..682b608
--- /dev/null
+++ b/include/dt-bindings/soc/imx8_pd.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __DT_BINDINGS_IMX8_PD_H
+#define __DT_BINDINGS_IMX8_PD_H
+
+/*!
+ * These defines are used to indicate a resource. Resources include peripherals
+ * and bus masters (but not memory regions). Note items from list should
+ * never be changed or removed (only added to at the end of the list).
+ */
+#define PD_DC_0                     dc0_power_domain
+#define PD_DC_0_PLL_0               dc0_pll0
+#define PD_DC_0_PLL_1               dc0_pll1
+#define PD_LVDS0                    lvds0_power_domain
+#define PD_LVDS0_I2C0               lvds0_i2c0
+#define PD_LVDS0_I2C1               lvds0_i2c1
+#define PD_LVDS0_PWM                lvds0_pwm
+#define PD_LVDS0_PWM                lvds0_pwm
+#define PD_LVDS0_GPIO               lvds0_gpio
+#define PD_DC_1                     dc1_power_domain
+#define PD_DC_1_PLL_0               dc1_pll0
+#define PD_DC_1_PLL_1               dc1_pll1
+#define PD_LVDS1                    lvds1_power_domain
+#define PD_LVDS1_I2C0               lvds1_i2c0
+#define PD_LVDS1_I2C1               lvds1_i2c1
+#define PD_LVDS1_PWM                lvds1_pwm
+#define PD_LVDS1_GPIO               lvds1_gpio
+
+#define PD_DMA                      dma_power_domain
+#define PD_DMA_SPI_0                dma_spi0
+#define PD_DMA_SPI_1                dma_spi1
+#define PD_DMA_SPI_2                dma_spi2
+#define PD_DMA_SPI_3                dma_spi3
+#define PD_DMA_UART0                dma_lpuart0
+#define PD_DMA_UART1                dma_lpuart1
+#define PD_DMA_UART2                dma_lpuart2
+#define PD_DMA_UART3                dma_lpuart3
+#define PD_DMA_UART4                dma_lpuart4
+#define PD_DMA_EMVSIM_0             dma_emvsim0
+#define PD_DMA_EMVSIM_1             dma_emvsim1
+#define PD_DMA_I2C_0                dma_lpi2c0
+#define PD_DMA_I2C_1                dma_lpi2c1
+#define PD_DMA_I2C_2                dma_lpi2c2
+#define PD_DMA_I2C_3                dma_lpi2c3
+#define PD_DMA_I2C_4                dma_lpi2c4
+#define PD_DMA_ADC_0                dma_adc0
+#define PD_DMA_ADC_1                dma_adc1
+#define PD_DMA_FTM_0                dma_ftm0
+#define PD_DMA_FTM_1                dma_ftm1
+#define PD_DMA_CAN_0                dma_flexcan0
+#define PD_DMA_CAN_1                dma_flexcan1
+#define PD_DMA_CAN_2                dma_flexcan2
+#define PD_DMA_PWM_0                dma_pwm0
+#define PD_DMA_LCD_0                dma_lcd0
+
+#define PD_HSIO                     hsio_power_domain
+#define PD_HSIO_PCIE_A              hsio_pcie0
+#define PD_HSIO_PCIE_B              hsio_pcie1
+#define PD_HSIO_SATA_0              hsio_sata0
+#define PD_HSIO_GPIO                hsio_gpio
+
+#define PD_LCD_0                    lcd0_power_domain
+#define PD_LCD_0_I2C_0              lcd0_i2c0
+#define PD_LCD_0_I2C_1              lcd0_i2c1
+#define PD_LCD_PWM_0                lcd0_pwm0
+
+#define PD_LSIO                     lsio_power_domain
+#define PD_LSIO_GPIO_0              lsio_gpio0
+#define PD_LSIO_GPIO_1              lsio_gpio1
+#define PD_LSIO_GPIO_2              lsio_gpio2
+#define PD_LSIO_GPIO_3              lsio_gpio3
+#define PD_LSIO_GPIO_4              lsio_gpio4
+#define PD_LSIO_GPIO_5              lsio_gpio5
+#define PD_LSIO_GPIO_6              lsio_gpio6
+#define PD_LSIO_GPIO_7              lsio_gpio7
+#define PD_LSIO_GPT_0               lsio_gpt0
+#define PD_LSIO_GPT_1               lsio_gpt1
+#define PD_LSIO_GPT_2               lsio_gpt2
+#define PD_LSIO_GPT_3               lsio_gpt3
+#define PD_LSIO_GPT_4               lsio_gpt4
+#define PD_LSIO_KPP                 lsio_kpp
+#define PD_LSIO_FSPI_0              lsio_fspi0
+#define PD_LSIO_FSPI_1              lsio_fspi1
+#define PD_LSIO_PWM_0               lsio_pwm0
+#define PD_LSIO_PWM_1               lsio_pwm1
+#define PD_LSIO_PWM_2               lsio_pwm2
+#define PD_LSIO_PWM_3               lsio_pwm3
+#define PD_LSIO_PWM_4               lsio_pwm4
+#define PD_LSIO_PWM_5               lsio_pwm5
+#define PD_LSIO_PWM_6               lsio_pwm6
+#define PD_LSIO_PWM_7               lsio_pwm7
+
+#define PD_CONN                     connectivity_power_domain
+#define PD_CONN_SDHC_0              conn_sdhc0
+#define PD_CONN_SDHC_1              conn_sdhc1
+#define PD_CONN_SDHC_2              conn_sdhc2
+#define PD_CONN_ENET_0              conn_enet0
+#define PD_CONN_ENET_1              conn_enet1
+#define PD_CONN_MLB_0               conn_mlb0
+#define PD_CONN_DMA_4_CH0           conn_dma4_ch0
+#define PD_CONN_DMA_4_CH1           conn_dma4_ch1
+#define PD_CONN_DMA_4_CH2           conn_dma4_ch2
+#define PD_CONN_DMA_4_CH3           conn_dma4_ch3
+#define PD_CONN_DMA_4_CH4           conn_dma4_ch4
+#define PD_CONN_USB_0               conn_usb0
+#define PD_CONN_USB_1               conn_usb1
+#define PD_CONN_USB_0_PHY           conn_usb0_phy
+#define PD_CONN_USB_2               conn_usb2
+#define PD_CONN_USB_2_PHY           conn_usb2_phy
+#define PD_CONN_NAND                conn_nand
+
+#define PD_AUDIO                    audio_power_domain
+#define PD_AUD_SAI_0                audio_sai0
+#define PD_AUD_SAI_1                audio_sai1
+#define PD_AUD_SAI_2                audio_sai2
+#define PD_AUD_ASRC_0               audio_asrc0
+#define PD_AUD_ASRC_1               audio_asrc1
+#define PD_AUD_ESAI_0               audio_esai0
+#define PD_AUD_ESAI_1               audio_esai1
+#define PD_AUD_SPDIF_0              audio_spdif0
+#define PD_AUD_SPDIF_1              audio_spdif1
+#define PD_AUD_SAI_3                audio_sai3
+#define PD_AUD_SAI_4                audio_sai4
+#define PD_AUD_SAI_5                audio_sai5
+#define PD_AUD_SAI_6                audio_sai6
+#define PD_AUD_SAI_7                audio_sai7
+#define PD_AUD_GPT_5                audio_gpt5
+#define PD_AUD_GPT_6                audio_gpt6
+#define PD_AUD_GPT_7                audio_gpt7
+#define PD_AUD_GPT_8                audio_gpt8
+#define PD_AUD_GPT_9                audio_gpt9
+#define PD_AUD_GPT_10               audio_gpt10
+#define PD_AUD_AMIX                 audio_amix
+#define PD_AUD_MQS_0                audio_mqs0
+#define PD_AUD_HIFI                 audio_hifi
+#define PD_AUD_OCRAM                audio_ocram
+#define PD_AUD_MCLK_OUT_0           audio_mclkout0
+#define PD_AUD_MCLK_OUT_1           audio_mclkout1
+#define PD_AUD_AUDIO_PLL_0          audio_audiopll0
+#define PD_AUD_AUDIO_PLL_1          audio_audiopll1
+#define PD_AUD_AUDIO_CLK_0          audio_audioclk0
+#define PD_AUD_AUDIO_CLK_1          audio_audioclk1
+
+#define PD_IMAGING                  imaging_power_domain
+#define PD_IMAGING_JPEG_DEC         imaging_jpeg_dec
+#define PD_IMAGING_JPEG_ENC         imaging_jpeg_enc
+#define PD_IMAGING_PDMA0            PD_IMAGING
+#define PD_IMAGING_PDMA1            imaging_pdma1
+#define PD_IMAGING_PDMA2            imaging_pdma2
+#define PD_IMAGING_PDMA3            imaging_pdma3
+#define PD_IMAGING_PDMA4            imaging_pdma4
+#define PD_IMAGING_PDMA5            imaging_pdma5
+#define PD_IMAGING_PDMA6            imaging_pdma6
+#define PD_IMAGING_PDMA7            imaging_pdma7
+
+#define PD_MIPI_0_DSI               mipi0_dsi_power_domain
+#define PD_MIPI_0_DSI_I2C0          mipi0_dsi_i2c0
+#define PD_MIPI_0_DSI_I2C1          mipi0_dsi_i2c1
+#define PD_MIPI_0_DSI_PWM0          mipi0_dsi_pwm0
+#define PD_MIPI_1_DSI               mipi1_dsi_power_domain
+#define PD_MIPI_1_DSI_I2C0          mipi1_dsi_i2c0
+#define PD_MIPI_1_DSI_I2C1          mipi1_dsi_i2c1
+#define PD_MIPI_1_DSI_PWM0          mipi1_dsi_pwm0
+
+#define PD_MIPI_CSI0                mipi_csi0_power_domain
+#define PD_MIPI_CSI0_PWM            mipi_csi0_pwm
+#define PD_MIPI_CSI0_I2C            mipi_csi0_i2c
+#define PD_MIPI_CSI1                mipi_csi1_power_domain
+#define PD_MIPI_CSI1_PWM_0          mipi_csi1_pwm
+#define PD_MIPI_CSI1_I2C_0          mipi_csi1_i2c
+
+#define PD_HDMI                     hdmi_power_domain
+#define PD_HDMI_I2C_0               hdmi_i2c
+#define PD_HDMI_PWM_0               hdmi_pwm
+#define PD_HDMI_GPIO_0              hdmi_gpio
+
+#define PD_HDMI_RX                  hdmi_rx_power_domain
+#define PD_HDMI_RX_I2C              hdmi_rx_i2c
+#define PD_HDMI_RX_PWM              hdmi_rx_pwm
+
+#define PD_CM40                     cm40_power_domain
+#define PD_CM40_I2C                 cm40_i2c
+#define PD_CM40_INTMUX              cm40_intmux
+
+#endif /* __DT_BINDINGS_IMX8_PD_H */
diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h
new file mode 100644
index 0000000..4870eb9
--- /dev/null
+++ b/include/dt-bindings/soc/imx_rsrc.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef DT_BINDINGS_RSCRC_IMX_H
+#define DT_BINDINGS_RSCRC_IMX_H
+
+/*!
+ * These defines are used to indicate a resource. Resources include peripherals
+ * and bus masters (but not memory regions). Note items from list should
+ * never be changed or removed (only added to at the end of the list).
+ */
+#define SC_R_A53                        0
+#define SC_R_A53_0                      1
+#define SC_R_A53_1                      2
+#define SC_R_A53_2                      3
+#define SC_R_A53_3                      4
+#define SC_R_A72                        5
+#define SC_R_A72_0                      6
+#define SC_R_A72_1                      7
+#define SC_R_A72_2                      8
+#define SC_R_A72_3                      9
+#define SC_R_CCI                        10
+#define SC_R_DB                         11
+#define SC_R_DRC_0                      12
+#define SC_R_DRC_1                      13
+#define SC_R_GIC_SMMU                   14
+#define SC_R_IRQSTR_M4_0                15
+#define SC_R_IRQSTR_M4_1                16
+#define SC_R_SMMU                       17
+#define SC_R_GIC                        18
+#define SC_R_DC_0_BLIT0                 19
+#define SC_R_DC_0_BLIT1                 20
+#define SC_R_DC_0_BLIT2                 21
+#define SC_R_DC_0_BLIT_OUT              22
+#define SC_R_DC_0_CAPTURE0              23
+#define SC_R_DC_0_CAPTURE1              24
+#define SC_R_DC_0_WARP                  25
+#define SC_R_DC_0_INTEGRAL0             26
+#define SC_R_DC_0_INTEGRAL1             27
+#define SC_R_DC_0_VIDEO0                28
+#define SC_R_DC_0_VIDEO1                29
+#define SC_R_DC_0_FRAC0                 30
+#define SC_R_DC_0_FRAC1                 31
+#define SC_R_DC_0                       32
+#define SC_R_GPU_2_PID0                 33
+#define SC_R_DC_0_PLL_0                 34
+#define SC_R_DC_0_PLL_1                 35
+#define SC_R_DC_1_BLIT0                 36
+#define SC_R_DC_1_BLIT1                 37
+#define SC_R_DC_1_BLIT2                 38
+#define SC_R_DC_1_BLIT_OUT              39
+#define SC_R_DC_1_CAPTURE0              40
+#define SC_R_DC_1_CAPTURE1              41
+#define SC_R_DC_1_WARP                  42
+#define SC_R_DC_1_INTEGRAL0             43
+#define SC_R_DC_1_INTEGRAL1             44
+#define SC_R_DC_1_VIDEO0                45
+#define SC_R_DC_1_VIDEO1                46
+#define SC_R_DC_1_FRAC0                 47
+#define SC_R_DC_1_FRAC1                 48
+#define SC_R_DC_1                       49
+#define SC_R_GPU_3_PID0                 50
+#define SC_R_DC_1_PLL_0                 51
+#define SC_R_DC_1_PLL_1                 52
+#define SC_R_SPI_0                      53
+#define SC_R_SPI_1                      54
+#define SC_R_SPI_2                      55
+#define SC_R_SPI_3                      56
+#define SC_R_UART_0                     57
+#define SC_R_UART_1                     58
+#define SC_R_UART_2                     59
+#define SC_R_UART_3                     60
+#define SC_R_UART_4                     61
+#define SC_R_EMVSIM_0                   62
+#define SC_R_EMVSIM_1                   63
+#define SC_R_DMA_0_CH0                  64
+#define SC_R_DMA_0_CH1                  65
+#define SC_R_DMA_0_CH2                  66
+#define SC_R_DMA_0_CH3                  67
+#define SC_R_DMA_0_CH4                  68
+#define SC_R_DMA_0_CH5                  69
+#define SC_R_DMA_0_CH6                  70
+#define SC_R_DMA_0_CH7                  71
+#define SC_R_DMA_0_CH8                  72
+#define SC_R_DMA_0_CH9                  73
+#define SC_R_DMA_0_CH10                 74
+#define SC_R_DMA_0_CH11                 75
+#define SC_R_DMA_0_CH12                 76
+#define SC_R_DMA_0_CH13                 77
+#define SC_R_DMA_0_CH14                 78
+#define SC_R_DMA_0_CH15                 79
+#define SC_R_DMA_0_CH16                 80
+#define SC_R_DMA_0_CH17                 81
+#define SC_R_DMA_0_CH18                 82
+#define SC_R_DMA_0_CH19                 83
+#define SC_R_DMA_0_CH20                 84
+#define SC_R_DMA_0_CH21                 85
+#define SC_R_DMA_0_CH22                 86
+#define SC_R_DMA_0_CH23                 87
+#define SC_R_DMA_0_CH24                 88
+#define SC_R_DMA_0_CH25                 89
+#define SC_R_DMA_0_CH26                 90
+#define SC_R_DMA_0_CH27                 91
+#define SC_R_DMA_0_CH28                 92
+#define SC_R_DMA_0_CH29                 93
+#define SC_R_DMA_0_CH30                 94
+#define SC_R_DMA_0_CH31                 95
+#define SC_R_I2C_0                      96
+#define SC_R_I2C_1                      97
+#define SC_R_I2C_2                      98
+#define SC_R_I2C_3                      99
+#define SC_R_I2C_4                      100
+#define SC_R_ADC_0                      101
+#define SC_R_ADC_1                      102
+#define SC_R_FTM_0                      103
+#define SC_R_FTM_1                      104
+#define SC_R_CAN_0                      105
+#define SC_R_CAN_1                      106
+#define SC_R_CAN_2                      107
+#define SC_R_DMA_1_CH0                  108
+#define SC_R_DMA_1_CH1                  109
+#define SC_R_DMA_1_CH2                  110
+#define SC_R_DMA_1_CH3                  111
+#define SC_R_DMA_1_CH4                  112
+#define SC_R_DMA_1_CH5                  113
+#define SC_R_DMA_1_CH6                  114
+#define SC_R_DMA_1_CH7                  115
+#define SC_R_DMA_1_CH8                  116
+#define SC_R_DMA_1_CH9                  117
+#define SC_R_DMA_1_CH10                 118
+#define SC_R_DMA_1_CH11                 119
+#define SC_R_DMA_1_CH12                 120
+#define SC_R_DMA_1_CH13                 121
+#define SC_R_DMA_1_CH14                 122
+#define SC_R_DMA_1_CH15                 123
+#define SC_R_DMA_1_CH16                 124
+#define SC_R_DMA_1_CH17                 125
+#define SC_R_DMA_1_CH18                 126
+#define SC_R_DMA_1_CH19                 127
+#define SC_R_DMA_1_CH20                 128
+#define SC_R_DMA_1_CH21                 129
+#define SC_R_DMA_1_CH22                 130
+#define SC_R_DMA_1_CH23                 131
+#define SC_R_DMA_1_CH24                 132
+#define SC_R_DMA_1_CH25                 133
+#define SC_R_DMA_1_CH26                 134
+#define SC_R_DMA_1_CH27                 135
+#define SC_R_DMA_1_CH28                 136
+#define SC_R_DMA_1_CH29                 137
+#define SC_R_DMA_1_CH30                 138
+#define SC_R_DMA_1_CH31                 139
+#define SC_R_UNUSED1                    140
+#define SC_R_UNUSED2                    141
+#define SC_R_UNUSED3                    142
+#define SC_R_UNUSED4                    143
+#define SC_R_GPU_0_PID0                 144
+#define SC_R_GPU_0_PID1                 145
+#define SC_R_GPU_0_PID2                 146
+#define SC_R_GPU_0_PID3                 147
+#define SC_R_GPU_1_PID0                 148
+#define SC_R_GPU_1_PID1                 149
+#define SC_R_GPU_1_PID2                 150
+#define SC_R_GPU_1_PID3                 151
+#define SC_R_PCIE_A                     152
+#define SC_R_SERDES_0                   153
+#define SC_R_MATCH_0                    154
+#define SC_R_MATCH_1                    155
+#define SC_R_MATCH_2                    156
+#define SC_R_MATCH_3                    157
+#define SC_R_MATCH_4                    158
+#define SC_R_MATCH_5                    159
+#define SC_R_MATCH_6                    160
+#define SC_R_MATCH_7                    161
+#define SC_R_MATCH_8                    162
+#define SC_R_MATCH_9                    163
+#define SC_R_MATCH_10                   164
+#define SC_R_MATCH_11                   165
+#define SC_R_MATCH_12                   166
+#define SC_R_MATCH_13                   167
+#define SC_R_MATCH_14                   168
+#define SC_R_PCIE_B                     169
+#define SC_R_SATA_0                     170
+#define SC_R_SERDES_1                   171
+#define SC_R_HSIO_GPIO                  172
+#define SC_R_MATCH_15                   173
+#define SC_R_MATCH_16                   174
+#define SC_R_MATCH_17                   175
+#define SC_R_MATCH_18                   176
+#define SC_R_MATCH_19                   177
+#define SC_R_MATCH_20                   178
+#define SC_R_MATCH_21                   179
+#define SC_R_MATCH_22                   180
+#define SC_R_MATCH_23                   181
+#define SC_R_MATCH_24                   182
+#define SC_R_MATCH_25                   183
+#define SC_R_MATCH_26                   184
+#define SC_R_MATCH_27                   185
+#define SC_R_MATCH_28                   186
+#define SC_R_LCD_0                      187
+#define SC_R_LCD_0_PWM_0                188
+#define SC_R_LCD_0_I2C_0                189
+#define SC_R_LCD_0_I2C_1                190
+#define SC_R_PWM_0                      191
+#define SC_R_PWM_1                      192
+#define SC_R_PWM_2                      193
+#define SC_R_PWM_3                      194
+#define SC_R_PWM_4                      195
+#define SC_R_PWM_5                      196
+#define SC_R_PWM_6                      197
+#define SC_R_PWM_7                      198
+#define SC_R_GPIO_0                     199
+#define SC_R_GPIO_1                     200
+#define SC_R_GPIO_2                     201
+#define SC_R_GPIO_3                     202
+#define SC_R_GPIO_4                     203
+#define SC_R_GPIO_5                     204
+#define SC_R_GPIO_6                     205
+#define SC_R_GPIO_7                     206
+#define SC_R_GPT_0                      207
+#define SC_R_GPT_1                      208
+#define SC_R_GPT_2                      209
+#define SC_R_GPT_3                      210
+#define SC_R_GPT_4                      211
+#define SC_R_KPP                        212
+#define SC_R_MU_0A                      213
+#define SC_R_MU_1A                      214
+#define SC_R_MU_2A                      215
+#define SC_R_MU_3A                      216
+#define SC_R_MU_4A                      217
+#define SC_R_MU_5A                      218
+#define SC_R_MU_6A                      219
+#define SC_R_MU_7A                      220
+#define SC_R_MU_8A                      221
+#define SC_R_MU_9A                      222
+#define SC_R_MU_10A                     223
+#define SC_R_MU_11A                     224
+#define SC_R_MU_12A                     225
+#define SC_R_MU_13A                     226
+#define SC_R_MU_5B                      227
+#define SC_R_MU_6B                      228
+#define SC_R_MU_7B                      229
+#define SC_R_MU_8B                      230
+#define SC_R_MU_9B                      231
+#define SC_R_MU_10B                     232
+#define SC_R_MU_11B                     233
+#define SC_R_MU_12B                     234
+#define SC_R_MU_13B                     235
+#define SC_R_ROM_0                      236
+#define SC_R_FSPI_0                     237
+#define SC_R_FSPI_1                     238
+#define SC_R_IEE                        239
+#define SC_R_IEE_R0                     240
+#define SC_R_IEE_R1                     241
+#define SC_R_IEE_R2                     242
+#define SC_R_IEE_R3                     243
+#define SC_R_IEE_R4                     244
+#define SC_R_IEE_R5                     245
+#define SC_R_IEE_R6                     246
+#define SC_R_IEE_R7                     247
+#define SC_R_SDHC_0                     248
+#define SC_R_SDHC_1                     249
+#define SC_R_SDHC_2                     250
+#define SC_R_ENET_0                     251
+#define SC_R_ENET_1                     252
+#define SC_R_MLB_0                      253
+#define SC_R_DMA_2_CH0                  254
+#define SC_R_DMA_2_CH1                  255
+#define SC_R_DMA_2_CH2                  256
+#define SC_R_DMA_2_CH3                  257
+#define SC_R_DMA_2_CH4                  258
+#define SC_R_USB_0                      259
+#define SC_R_USB_1                      260
+#define SC_R_USB_0_PHY                  261
+#define SC_R_USB_2                      262
+#define SC_R_USB_2_PHY                  263
+#define SC_R_DTCP                       264
+#define SC_R_NAND                       265
+#define SC_R_LVDS_0                     266
+#define SC_R_LVDS_0_PWM_0               267
+#define SC_R_LVDS_0_I2C_0               268
+#define SC_R_LVDS_0_I2C_1               269
+#define SC_R_LVDS_1                     270
+#define SC_R_LVDS_1_PWM_0               271
+#define SC_R_LVDS_1_I2C_0               272
+#define SC_R_LVDS_1_I2C_1               273
+#define SC_R_LVDS_2                     274
+#define SC_R_LVDS_2_PWM_0               275
+#define SC_R_LVDS_2_I2C_0               276
+#define SC_R_LVDS_2_I2C_1               277
+#define SC_R_M4_0_PID0                  278
+#define SC_R_M4_0_PID1                  279
+#define SC_R_M4_0_PID2                  280
+#define SC_R_M4_0_PID3                  281
+#define SC_R_M4_0_PID4                  282
+#define SC_R_M4_0_RGPIO                 283
+#define SC_R_M4_0_SEMA42                284
+#define SC_R_M4_0_TPM                   285
+#define SC_R_M4_0_PIT                   286
+#define SC_R_M4_0_UART                  287
+#define SC_R_M4_0_I2C                   288
+#define SC_R_M4_0_INTMUX                289
+#define SC_R_M4_0_SIM                   290
+#define SC_R_M4_0_WDOG                  291
+#define SC_R_M4_0_MU_0B                 292
+#define SC_R_M4_0_MU_0A0                293
+#define SC_R_M4_0_MU_0A1                294
+#define SC_R_M4_0_MU_0A2                295
+#define SC_R_M4_0_MU_0A3                296
+#define SC_R_M4_0_MU_1A                 297
+#define SC_R_M4_1_PID0                  298
+#define SC_R_M4_1_PID1                  299
+#define SC_R_M4_1_PID2                  300
+#define SC_R_M4_1_PID3                  301
+#define SC_R_M4_1_PID4                  302
+#define SC_R_M4_1_RGPIO                 303
+#define SC_R_M4_1_SEMA42                304
+#define SC_R_M4_1_TPM                   305
+#define SC_R_M4_1_PIT                   306
+#define SC_R_M4_1_UART                  307
+#define SC_R_M4_1_I2C                   308
+#define SC_R_M4_1_INTMUX                309
+#define SC_R_M4_1_SIM                   310
+#define SC_R_M4_1_WDOG                  311
+#define SC_R_M4_1_MU_0B                 312
+#define SC_R_M4_1_MU_0A0                313
+#define SC_R_M4_1_MU_0A1                314
+#define SC_R_M4_1_MU_0A2                315
+#define SC_R_M4_1_MU_0A3                316
+#define SC_R_M4_1_MU_1A                 317
+#define SC_R_SAI_0                      318
+#define SC_R_SAI_1                      319
+#define SC_R_SAI_2                      320
+#define SC_R_IRQSTR_SCU2                321
+#define SC_R_IRQSTR_DSP                 322
+#define SC_R_UNUSED5                    323
+#define SC_R_OCRAM                      324
+#define SC_R_AUDIO_PLL_0                325
+#define SC_R_PI_0                       326
+#define SC_R_PI_0_PWM_0                 327
+#define SC_R_PI_0_PWM_1                 328
+#define SC_R_PI_0_I2C_0                 329
+#define SC_R_PI_0_PLL                   330
+#define SC_R_PI_1                       331
+#define SC_R_PI_1_PWM_0                 332
+#define SC_R_PI_1_PWM_1                 333
+#define SC_R_PI_1_I2C_0                 334
+#define SC_R_PI_1_PLL                   335
+#define SC_R_SC_PID0                    336
+#define SC_R_SC_PID1                    337
+#define SC_R_SC_PID2                    338
+#define SC_R_SC_PID3                    339
+#define SC_R_SC_PID4                    340
+#define SC_R_SC_SEMA42                  341
+#define SC_R_SC_TPM                     342
+#define SC_R_SC_PIT                     343
+#define SC_R_SC_UART                    344
+#define SC_R_SC_I2C                     345
+#define SC_R_SC_MU_0B                   346
+#define SC_R_SC_MU_0A0                  347
+#define SC_R_SC_MU_0A1                  348
+#define SC_R_SC_MU_0A2                  349
+#define SC_R_SC_MU_0A3                  350
+#define SC_R_SC_MU_1A                   351
+#define SC_R_SYSCNT_RD                  352
+#define SC_R_SYSCNT_CMP                 353
+#define SC_R_DEBUG                      354
+#define SC_R_SYSTEM                     355
+#define SC_R_SNVS                       356
+#define SC_R_OTP                        357
+#define SC_R_VPU_PID0                   358
+#define SC_R_VPU_PID1                   359
+#define SC_R_VPU_PID2                   360
+#define SC_R_VPU_PID3                   361
+#define SC_R_VPU_PID4                   362
+#define SC_R_VPU_PID5                   363
+#define SC_R_VPU_PID6                   364
+#define SC_R_VPU_PID7                   365
+#define SC_R_VPU_UART                   366
+#define SC_R_VPUCORE                    367
+#define SC_R_VPUCORE_0                  368
+#define SC_R_VPUCORE_1                  369
+#define SC_R_VPUCORE_2                  370
+#define SC_R_VPUCORE_3                  371
+#define SC_R_DMA_4_CH0                  372
+#define SC_R_DMA_4_CH1                  373
+#define SC_R_DMA_4_CH2                  374
+#define SC_R_DMA_4_CH3                  375
+#define SC_R_DMA_4_CH4                  376
+#define SC_R_ISI_CH0                    377
+#define SC_R_ISI_CH1                    378
+#define SC_R_ISI_CH2                    379
+#define SC_R_ISI_CH3                    380
+#define SC_R_ISI_CH4                    381
+#define SC_R_ISI_CH5                    382
+#define SC_R_ISI_CH6                    383
+#define SC_R_ISI_CH7                    384
+#define SC_R_MJPEG_DEC_S0               385
+#define SC_R_MJPEG_DEC_S1               386
+#define SC_R_MJPEG_DEC_S2               387
+#define SC_R_MJPEG_DEC_S3               388
+#define SC_R_MJPEG_ENC_S0               389
+#define SC_R_MJPEG_ENC_S1               390
+#define SC_R_MJPEG_ENC_S2               391
+#define SC_R_MJPEG_ENC_S3               392
+#define SC_R_MIPI_0                     393
+#define SC_R_MIPI_0_PWM_0               394
+#define SC_R_MIPI_0_I2C_0               395
+#define SC_R_MIPI_0_I2C_1               396
+#define SC_R_MIPI_1                     397
+#define SC_R_MIPI_1_PWM_0               398
+#define SC_R_MIPI_1_I2C_0               399
+#define SC_R_MIPI_1_I2C_1               400
+#define SC_R_CSI_0                      401
+#define SC_R_CSI_0_PWM_0                402
+#define SC_R_CSI_0_I2C_0                403
+#define SC_R_CSI_1                      404
+#define SC_R_CSI_1_PWM_0                405
+#define SC_R_CSI_1_I2C_0                406
+#define SC_R_HDMI                       407
+#define SC_R_HDMI_I2S                   408
+#define SC_R_HDMI_I2C_0                 409
+#define SC_R_HDMI_PLL_0                 410
+#define SC_R_HDMI_RX                    411
+#define SC_R_HDMI_RX_BYPASS             412
+#define SC_R_HDMI_RX_I2C_0              413
+#define SC_R_ASRC_0                     414
+#define SC_R_ESAI_0                     415
+#define SC_R_SPDIF_0                    416
+#define SC_R_SPDIF_1                    417
+#define SC_R_SAI_3                      418
+#define SC_R_SAI_4                      419
+#define SC_R_SAI_5                      420
+#define SC_R_GPT_5                      421
+#define SC_R_GPT_6                      422
+#define SC_R_GPT_7                      423
+#define SC_R_GPT_8                      424
+#define SC_R_GPT_9                      425
+#define SC_R_GPT_10                     426
+#define SC_R_DMA_2_CH5                  427
+#define SC_R_DMA_2_CH6                  428
+#define SC_R_DMA_2_CH7                  429
+#define SC_R_DMA_2_CH8                  430
+#define SC_R_DMA_2_CH9                  431
+#define SC_R_DMA_2_CH10                 432
+#define SC_R_DMA_2_CH11                 433
+#define SC_R_DMA_2_CH12                 434
+#define SC_R_DMA_2_CH13                 435
+#define SC_R_DMA_2_CH14                 436
+#define SC_R_DMA_2_CH15                 437
+#define SC_R_DMA_2_CH16                 438
+#define SC_R_DMA_2_CH17                 439
+#define SC_R_DMA_2_CH18                 440
+#define SC_R_DMA_2_CH19                 441
+#define SC_R_DMA_2_CH20                 442
+#define SC_R_DMA_2_CH21                 443
+#define SC_R_DMA_2_CH22                 444
+#define SC_R_DMA_2_CH23                 445
+#define SC_R_DMA_2_CH24                 446
+#define SC_R_DMA_2_CH25                 447
+#define SC_R_DMA_2_CH26                 448
+#define SC_R_DMA_2_CH27                 449
+#define SC_R_DMA_2_CH28                 450
+#define SC_R_DMA_2_CH29                 451
+#define SC_R_DMA_2_CH30                 452
+#define SC_R_DMA_2_CH31                 453
+#define SC_R_ASRC_1                     454
+#define SC_R_ESAI_1                     455
+#define SC_R_SAI_6                      456
+#define SC_R_SAI_7                      457
+#define SC_R_AMIX                       458
+#define SC_R_MQS_0                      459
+#define SC_R_DMA_3_CH0                  460
+#define SC_R_DMA_3_CH1                  461
+#define SC_R_DMA_3_CH2                  462
+#define SC_R_DMA_3_CH3                  463
+#define SC_R_DMA_3_CH4                  464
+#define SC_R_DMA_3_CH5                  465
+#define SC_R_DMA_3_CH6                  466
+#define SC_R_DMA_3_CH7                  467
+#define SC_R_DMA_3_CH8                  468
+#define SC_R_DMA_3_CH9                  469
+#define SC_R_DMA_3_CH10                 470
+#define SC_R_DMA_3_CH11                 471
+#define SC_R_DMA_3_CH12                 472
+#define SC_R_DMA_3_CH13                 473
+#define SC_R_DMA_3_CH14                 474
+#define SC_R_DMA_3_CH15                 475
+#define SC_R_DMA_3_CH16                 476
+#define SC_R_DMA_3_CH17                 477
+#define SC_R_DMA_3_CH18                 478
+#define SC_R_DMA_3_CH19                 479
+#define SC_R_DMA_3_CH20                 480
+#define SC_R_DMA_3_CH21                 481
+#define SC_R_DMA_3_CH22                 482
+#define SC_R_DMA_3_CH23                 483
+#define SC_R_DMA_3_CH24                 484
+#define SC_R_DMA_3_CH25                 485
+#define SC_R_DMA_3_CH26                 486
+#define SC_R_DMA_3_CH27                 487
+#define SC_R_DMA_3_CH28                 488
+#define SC_R_DMA_3_CH29                 489
+#define SC_R_DMA_3_CH30                 490
+#define SC_R_DMA_3_CH31                 491
+#define SC_R_AUDIO_PLL_1                492
+#define SC_R_AUDIO_CLK_0                493
+#define SC_R_AUDIO_CLK_1                494
+#define SC_R_MCLK_OUT_0                 495
+#define SC_R_MCLK_OUT_1                 496
+#define SC_R_PMIC_0                     497
+#define SC_R_PMIC_1                     498
+#define SC_R_SECO                       499
+#define SC_R_CAAM_JR1                   500
+#define SC_R_CAAM_JR2                   501
+#define SC_R_CAAM_JR3                   502
+#define SC_R_SECO_MU_2                  503
+#define SC_R_SECO_MU_3                  504
+#define SC_R_SECO_MU_4                  505
+#define SC_R_HDMI_RX_PWM_0              506
+#define SC_R_A35                        507
+#define SC_R_A35_0                      508
+#define SC_R_A35_1                      509
+#define SC_R_A35_2                      510
+#define SC_R_A35_3                      511
+#define SC_R_DSP                        512
+#define SC_R_DSP_RAM                    513
+#define SC_R_CAAM_JR1_OUT               514
+#define SC_R_CAAM_JR2_OUT               515
+#define SC_R_CAAM_JR3_OUT               516
+#define SC_R_VPU_DEC_0                  517
+#define SC_R_VPU_ENC_0                  518
+#define SC_R_CAAM_JR0                   519
+#define SC_R_CAAM_JR0_OUT               520
+#define SC_R_PMIC_2                     521
+#define SC_R_DBLOGIC                    522
+#define SC_R_HDMI_PLL_1                 523
+#define SC_R_BOARD_R0                   524
+#define SC_R_BOARD_R1                   525
+#define SC_R_BOARD_R2                   526
+#define SC_R_BOARD_R3                   527
+#define SC_R_BOARD_R4                   528
+#define SC_R_BOARD_R5                   529
+#define SC_R_BOARD_R6                   530
+#define SC_R_BOARD_R7                   531
+#define SC_R_MJPEG_DEC_MP               532
+#define SC_R_MJPEG_ENC_MP               533
+#define SC_R_VPU_TS_0                   534
+#define SC_R_VPU_MU_0                   535
+#define SC_R_VPU_MU_1                   536
+#define SC_R_VPU_MU_2                   537
+#define SC_R_VPU_MU_3                   538
+#define SC_R_VPU_ENC_1                  539
+#define SC_R_VPU                        540
+#define SC_R_LAST                       541
+
+#endif /* DT_BINDINGS_RSCRC_IMX_H */
diff --git a/include/dt-bindings/soc/ti,sci_pm_domain.h b/include/dt-bindings/soc/ti,sci_pm_domain.h
new file mode 100644
index 0000000..8f2a736
--- /dev/null
+++ b/include/dt-bindings/soc/ti,sci_pm_domain.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
+#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
+
+#define TI_SCI_PD_EXCLUSIVE	1
+#define TI_SCI_PD_SHARED	0
+
+#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */
diff --git a/include/dt-bindings/sound/azalia.h b/include/dt-bindings/sound/azalia.h
new file mode 100644
index 0000000..10ace3e
--- /dev/null
+++ b/include/dt-bindings/sound/azalia.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Intel HDA audio codec config. This is a mechanicm to configure codecs when
+ * using Intel HDA audio.
+ *
+ * Copyright 2018 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __AZALIA_H
+#define __AZALIA_H
+
+#define AZALIA_CODEC_SHIFT		28
+#define AZALIA_NID_SHIFT		20
+#define AZALIA_VERB_SHIFT		8
+
+/* Supported opcodes */
+#define AZALIA_OPCODE_CONFIG_DEFAULT	0x71c
+#define AZALIA_OPCODE_IMPL_ID		0x720
+#define AZALIA_OPCODE_READ_PARAM	0xf00
+
+#define AZALIA_PARAM_VENDOR_ID		0
+
+/* Generate the register value to write a particular byte of a 32-bit value */
+#define AZALIA_SET_BYTE(codec, nid, opcode, val, byte)		\
+	((codec) << AZALIA_CODEC_SHIFT |			\
+	 (nid) << AZALIA_NID_SHIFT |			\
+	 ((opcode) + (byte)) << AZALIA_VERB_SHIFT |		\
+	 (((val) >> ((byte) * 8)) & 0xff))
+
+/* Generate the register value to write all bytes of a 32-bit value */
+#define AZALIA_WORD(codec, nid, opcode, val)			\
+	 (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) |	\
+	  AZALIA_SET_BYTE(codec, nid, opcode, val, 1) |		\
+	  AZALIA_SET_BYTE(codec, nid, opcode, val, 2) |		\
+	  AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
+
+#define AZALIA_PIN_CFG(codec, nid, val)				\
+	 AZALIA_WORD(codec, nid, AZALIA_OPCODE_CONFIG_DEFAULT, val)
+
+#define AZALIA_SUBVENDOR(codec, val)				\
+	 AZALIA_WORD(codec, 1, AZALIA_OPCODE_IMPL_ID, val)
+
+#endif /* __AZALIA_H */
diff --git a/include/dt-bindings/sound/meson-g12a-tohdmitx.h b/include/dt-bindings/sound/meson-g12a-tohdmitx.h
new file mode 100644
index 0000000..c5e1f48
--- /dev/null
+++ b/include/dt-bindings/sound/meson-g12a-tohdmitx.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_MESON_G12A_TOHDMITX_H
+#define __DT_MESON_G12A_TOHDMITX_H
+
+#define TOHDMITX_I2S_IN_A	0
+#define TOHDMITX_I2S_IN_B	1
+#define TOHDMITX_I2S_IN_C	2
+#define TOHDMITX_I2S_OUT	3
+#define TOHDMITX_SPDIF_IN_A	4
+#define TOHDMITX_SPDIF_IN_B	5
+#define TOHDMITX_SPDIF_OUT	6
+
+#endif /* __DT_MESON_G12A_TOHDMITX_H */
diff --git a/include/dt-bindings/sound/tlv320aic31xx-micbias.h b/include/dt-bindings/sound/tlv320aic31xx-micbias.h
new file mode 100644
index 0000000..f5cb772
--- /dev/null
+++ b/include/dt-bindings/sound/tlv320aic31xx-micbias.h
@@ -0,0 +1,8 @@
+#ifndef __DT_TLV320AIC31XX_MICBIAS_H
+#define __DT_TLV320AIC31XX_MICBIAS_H
+
+#define MICBIAS_2_0V		1
+#define MICBIAS_2_5V		2
+#define MICBIAS_AVDDV		3
+
+#endif /* __DT_TLV320AIC31XX_MICBIAS_H */
diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
new file mode 100644
index 0000000..729ab9f
--- /dev/null
+++ b/include/dt-bindings/thermal/tegra124-soctherm.h
@@ -0,0 +1,14 @@
+/*
+ * This header provides constants for binding nvidia,tegra124-soctherm.
+ */
+
+#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
+#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H
+
+#define TEGRA124_SOCTHERM_SENSOR_CPU 0
+#define TEGRA124_SOCTHERM_SENSOR_MEM 1
+#define TEGRA124_SOCTHERM_SENSOR_GPU 2
+#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
+#define TEGRA124_SOCTHERM_SENSOR_NUM 4
+
+#endif
diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h
new file mode 100644
index 0000000..b5e6b00
--- /dev/null
+++ b/include/dt-bindings/thermal/thermal.h
@@ -0,0 +1,17 @@
+/*
+ * This header provides constants for most thermal bindings.
+ *
+ * Copyright (C) 2013 Texas Instruments
+ *	Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef _DT_BINDINGS_THERMAL_THERMAL_H
+#define _DT_BINDINGS_THERMAL_THERMAL_H
+
+/* On cooling devices upper and lower limits */
+#define THERMAL_NO_LIMIT		(~0)
+
+#endif
+
diff --git a/include/dt-bindings/video/rk3288.h b/include/dt-bindings/video/rk3288.h
new file mode 100644
index 0000000..7bfd247
--- /dev/null
+++ b/include/dt-bindings/video/rk3288.h
@@ -0,0 +1,11 @@
+#ifndef __DT_BINDINGS_VIDEO_RK3288_H__
+#define __DT_BINDINGS_VIDEO_RK3288_H__
+
+#define LVDS_OUTPUT_RGB     0
+#define LVDS_OUTPUT_SINGLE  1
+#define LVDS_OUTPUT_DUAL    2
+
+#define LVDS_FORMAT_VESA    0
+#define LVDS_FORMAT_JEIDA   1
+
+#endif
diff --git a/include/dt-structs.h b/include/dt-structs.h
new file mode 100644
index 0000000..924d51f
--- /dev/null
+++ b/include/dt-structs.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ */
+
+#ifndef __DT_STRUCTS
+#define __DT_STRUCTS
+
+/* These structures may only be used in SPL */
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct phandle_0_arg {
+	const void *node;
+	int arg[0];
+};
+
+struct phandle_1_arg {
+	const void *node;
+	int arg[1];
+};
+
+struct phandle_2_arg {
+	const void *node;
+	int arg[2];
+};
+#include <generated/dt-structs-gen.h>
+#endif
+
+#endif
diff --git a/include/dt_table.h b/include/dt_table.h
new file mode 100644
index 0000000..7fb16e9
--- /dev/null
+++ b/include/dt_table.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * This is from the Android Project,
+ * Repository: https://android.googlesource.com/platform/system/libufdt
+ * File: utils/src/dt_table.h
+ * Commit: 2626d8b9e4d8e8c6cc67ceb1dc4e05a47779785c
+ * Copyright (C) 2017 The Android Open Source Project
+ */
+
+#ifndef DT_TABLE_H
+#define DT_TABLE_H
+
+#include <linux/types.h>
+
+#define DT_TABLE_MAGIC			0xd7b7ab1e
+#define DT_TABLE_DEFAULT_PAGE_SIZE	2048
+#define DT_TABLE_DEFAULT_VERSION	0
+
+struct dt_table_header {
+	u32 magic;		/* DT_TABLE_MAGIC */
+	u32 total_size;		/* includes dt_table_header + all dt_table_entry
+				 * and all dtb/dtbo
+				 */
+	u32 header_size;	/* sizeof(dt_table_header) */
+
+	u32 dt_entry_size;	/* sizeof(dt_table_entry) */
+	u32 dt_entry_count;	/* number of dt_table_entry */
+	u32 dt_entries_offset;	/* offset to the first dt_table_entry
+				 * from head of dt_table_header.
+				 * The value will be equal to header_size if
+				 * no padding is appended
+				 */
+	u32 page_size;		/* flash page size we assume */
+	u32 version;            /* DTBO image version, the current version is 0.
+				 * The version will be incremented when the
+				 * dt_table_header struct is updated.
+				 */
+};
+
+struct dt_table_entry {
+	u32 dt_size;
+	u32 dt_offset;		/* offset from head of dt_table_header */
+
+	u32 id;			/* optional, must be zero if unused */
+	u32 rev;		/* optional, must be zero if unused */
+	u32 custom[4];		/* optional, must be zero if unused */
+};
+
+#endif
diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h
new file mode 100644
index 0000000..8acae38
--- /dev/null
+++ b/include/dw_hdmi.h
@@ -0,0 +1,560 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ */
+
+#ifndef _DW_HDMI_H
+#define _DW_HDMI_H
+
+#include <edid.h>
+
+#define HDMI_EDID_BLOCK_SIZE            128
+
+/* Identification Registers */
+#define HDMI_DESIGN_ID                          0x0000
+#define HDMI_REVISION_ID                        0x0001
+#define HDMI_PRODUCT_ID0                        0x0002
+#define HDMI_PRODUCT_ID1                        0x0003
+#define HDMI_CONFIG0_ID                         0x0004
+#define HDMI_CONFIG1_ID                         0x0005
+#define HDMI_CONFIG2_ID                         0x0006
+#define HDMI_CONFIG3_ID                         0x0007
+
+/* Interrupt Registers */
+#define HDMI_IH_FC_STAT0                        0x0100
+#define HDMI_IH_FC_STAT1                        0x0101
+#define HDMI_IH_FC_STAT2                        0x0102
+#define HDMI_IH_AS_STAT0                        0x0103
+#define HDMI_IH_PHY_STAT0                       0x0104
+#define HDMI_IH_I2CM_STAT0                      0x0105
+#define HDMI_IH_CEC_STAT0                       0x0106
+#define HDMI_IH_VP_STAT0                        0x0107
+#define HDMI_IH_I2CMPHY_STAT0                   0x0108
+#define HDMI_IH_AHBDMAAUD_STAT0                 0x0109
+
+#define HDMI_IH_MUTE_FC_STAT0                   0x0180
+#define HDMI_IH_MUTE_FC_STAT1                   0x0181
+#define HDMI_IH_MUTE_FC_STAT2                   0x0182
+#define HDMI_IH_MUTE_AS_STAT0                   0x0183
+#define HDMI_IH_MUTE_PHY_STAT0                  0x0184
+#define HDMI_IH_MUTE_I2CM_STAT0                 0x0185
+#define HDMI_IH_MUTE_CEC_STAT0                  0x0186
+#define HDMI_IH_MUTE_VP_STAT0                   0x0187
+#define HDMI_IH_MUTE_I2CMPHY_STAT0              0x0188
+#define HDMI_IH_MUTE_AHBDMAAUD_STAT0            0x0189
+#define HDMI_IH_MUTE                            0x01FF
+
+/* Video Sample Registers */
+#define HDMI_TX_INVID0                          0x0200
+#define HDMI_TX_INSTUFFING                      0x0201
+#define HDMI_TX_GYDATA0                         0x0202
+#define HDMI_TX_GYDATA1                         0x0203
+#define HDMI_TX_RCRDATA0                        0x0204
+#define HDMI_TX_RCRDATA1                        0x0205
+#define HDMI_TX_BCBDATA0                        0x0206
+#define HDMI_TX_BCBDATA1                        0x0207
+
+/* Video Packetizer Registers */
+#define HDMI_VP_STATUS                          0x0800
+#define HDMI_VP_PR_CD                           0x0801
+#define HDMI_VP_STUFF                           0x0802
+#define HDMI_VP_REMAP                           0x0803
+#define HDMI_VP_CONF                            0x0804
+#define HDMI_VP_STAT                            0x0805
+#define HDMI_VP_INT                             0x0806
+#define HDMI_VP_MASK                            0x0807
+#define HDMI_VP_POL                             0x0808
+
+/* Frame Composer Registers */
+#define HDMI_FC_INVIDCONF                       0x1000
+#define HDMI_FC_INHACTV0                        0x1001
+#define HDMI_FC_INHACTV1                        0x1002
+#define HDMI_FC_INHBLANK0                       0x1003
+#define HDMI_FC_INHBLANK1                       0x1004
+#define HDMI_FC_INVACTV0                        0x1005
+#define HDMI_FC_INVACTV1                        0x1006
+#define HDMI_FC_INVBLANK                        0x1007
+#define HDMI_FC_HSYNCINDELAY0                   0x1008
+#define HDMI_FC_HSYNCINDELAY1                   0x1009
+#define HDMI_FC_HSYNCINWIDTH0                   0x100A
+#define HDMI_FC_HSYNCINWIDTH1                   0x100B
+#define HDMI_FC_VSYNCINDELAY                    0x100C
+#define HDMI_FC_VSYNCINWIDTH                    0x100D
+#define HDMI_FC_INFREQ0                         0x100E
+#define HDMI_FC_INFREQ1                         0x100F
+#define HDMI_FC_INFREQ2                         0x1010
+#define HDMI_FC_CTRLDUR                         0x1011
+#define HDMI_FC_EXCTRLDUR                       0x1012
+#define HDMI_FC_EXCTRLSPAC                      0x1013
+#define HDMI_FC_CH0PREAM                        0x1014
+#define HDMI_FC_CH1PREAM                        0x1015
+#define HDMI_FC_CH2PREAM                        0x1016
+#define HDMI_FC_AVICONF3                        0x1017
+#define HDMI_FC_GCP                             0x1018
+#define HDMI_FC_AVICONF0                        0x1019
+#define HDMI_FC_AVICONF1                        0x101A
+#define HDMI_FC_AVICONF2                        0x101B
+#define HDMI_FC_AVIVID                          0x101C
+#define HDMI_FC_AVIETB0                         0x101D
+#define HDMI_FC_AVIETB1                         0x101E
+#define HDMI_FC_AVISBB0                         0x101F
+#define HDMI_FC_AVISBB1                         0x1020
+#define HDMI_FC_AVIELB0                         0x1021
+#define HDMI_FC_AVIELB1                         0x1022
+#define HDMI_FC_AVISRB0                         0x1023
+#define HDMI_FC_AVISRB1                         0x1024
+#define HDMI_FC_AUDICONF0                       0x1025
+#define HDMI_FC_AUDICONF1                       0x1026
+#define HDMI_FC_AUDICONF2                       0x1027
+#define HDMI_FC_AUDICONF3                       0x1028
+#define HDMI_FC_VSDIEEEID0                      0x1029
+#define HDMI_FC_VSDSIZE                         0x102A
+
+/* HDMI Source PHY Registers */
+#define HDMI_PHY_CONF0                          0x3000
+#define HDMI_PHY_TST0                           0x3001
+#define HDMI_PHY_TST1                           0x3002
+#define HDMI_PHY_TST2                           0x3003
+#define HDMI_PHY_STAT0                          0x3004
+#define HDMI_PHY_INT0                           0x3005
+#define HDMI_PHY_MASK0                          0x3006
+#define HDMI_PHY_POL0                           0x3007
+
+/* HDMI Master PHY Registers */
+#define HDMI_PHY_I2CM_SLAVE_ADDR                0x3020
+#define HDMI_PHY_I2CM_ADDRESS_ADDR              0x3021
+#define HDMI_PHY_I2CM_DATAO_1_ADDR              0x3022
+#define HDMI_PHY_I2CM_DATAO_0_ADDR              0x3023
+#define HDMI_PHY_I2CM_DATAI_1_ADDR              0x3024
+#define HDMI_PHY_I2CM_DATAI_0_ADDR              0x3025
+#define HDMI_PHY_I2CM_OPERATION_ADDR            0x3026
+#define HDMI_PHY_I2CM_INT_ADDR                  0x3027
+#define HDMI_PHY_I2CM_CTLINT_ADDR               0x3028
+#define HDMI_PHY_I2CM_DIV_ADDR                  0x3029
+#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR             0x302a
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR        0x302b
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR        0x302c
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR        0x302d
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR        0x302e
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR        0x302f
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR        0x3030
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR        0x3031
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR        0x3032
+
+/* Audio Sampler Registers */
+#define HDMI_AUD_CONF0                          0x3100
+#define HDMI_AUD_CONF1                          0x3101
+#define HDMI_AUD_INT                            0x3102
+#define HDMI_AUD_CONF2                          0x3103
+#define HDMI_AUD_INT1                           0x3104
+#define HDMI_AUD_N1                             0x3200
+#define HDMI_AUD_N2                             0x3201
+#define HDMI_AUD_N3                             0x3202
+#define HDMI_AUD_CTS1                           0x3203
+#define HDMI_AUD_CTS2                           0x3204
+#define HDMI_AUD_CTS3                           0x3205
+#define HDMI_AUD_INPUTCLKFS                     0x3206
+#define HDMI_AUD_SPDIFINT			0x3302
+#define HDMI_AUD_CONF0_HBR                      0x3400
+#define HDMI_AUD_HBR_STATUS                     0x3401
+#define HDMI_AUD_HBR_INT                        0x3402
+#define HDMI_AUD_HBR_POL                        0x3403
+#define HDMI_AUD_HBR_MASK                       0x3404
+
+/* Main Controller Registers */
+#define HDMI_MC_SFRDIV                          0x4000
+#define HDMI_MC_CLKDIS                          0x4001
+#define HDMI_MC_SWRSTZ                          0x4002
+#define HDMI_MC_OPCTRL                          0x4003
+#define HDMI_MC_FLOWCTRL                        0x4004
+#define HDMI_MC_PHYRSTZ                         0x4005
+#define HDMI_MC_LOCKONCLOCK                     0x4006
+#define HDMI_MC_HEACPHY_RST                     0x4007
+
+/* Color Space  Converter Registers */
+#define HDMI_CSC_CFG                            0x4100
+#define HDMI_CSC_SCALE                          0x4101
+#define HDMI_CSC_COEF_A1_MSB                    0x4102
+#define HDMI_CSC_COEF_A1_LSB                    0x4103
+#define HDMI_CSC_COEF_A2_MSB                    0x4104
+#define HDMI_CSC_COEF_A2_LSB                    0x4105
+#define HDMI_CSC_COEF_A3_MSB                    0x4106
+#define HDMI_CSC_COEF_A3_LSB                    0x4107
+#define HDMI_CSC_COEF_A4_MSB                    0x4108
+#define HDMI_CSC_COEF_A4_LSB                    0x4109
+#define HDMI_CSC_COEF_B1_MSB                    0x410A
+#define HDMI_CSC_COEF_B1_LSB                    0x410B
+#define HDMI_CSC_COEF_B2_MSB                    0x410C
+#define HDMI_CSC_COEF_B2_LSB                    0x410D
+#define HDMI_CSC_COEF_B3_MSB                    0x410E
+#define HDMI_CSC_COEF_B3_LSB                    0x410F
+#define HDMI_CSC_COEF_B4_MSB                    0x4110
+#define HDMI_CSC_COEF_B4_LSB                    0x4111
+#define HDMI_CSC_COEF_C1_MSB                    0x4112
+#define HDMI_CSC_COEF_C1_LSB                    0x4113
+#define HDMI_CSC_COEF_C2_MSB                    0x4114
+#define HDMI_CSC_COEF_C2_LSB                    0x4115
+#define HDMI_CSC_COEF_C3_MSB                    0x4116
+#define HDMI_CSC_COEF_C3_LSB                    0x4117
+#define HDMI_CSC_COEF_C4_MSB                    0x4118
+#define HDMI_CSC_COEF_C4_LSB                    0x4119
+
+/* I2C Master Registers (E-DDC) */
+#define HDMI_I2CM_SLAVE                         0x7E00
+#define HDMI_I2CM_ADDRESS                       0x7E01
+#define HDMI_I2CM_DATAO                         0x7E02
+#define HDMI_I2CM_DATAI                         0x7E03
+#define HDMI_I2CM_OPERATION                     0x7E04
+#define HDMI_I2CM_INT                           0x7E05
+#define HDMI_I2CM_CTLINT                        0x7E06
+#define HDMI_I2CM_DIV                           0x7E07
+#define HDMI_I2CM_SEGADDR                       0x7E08
+#define HDMI_I2CM_SOFTRSTZ                      0x7E09
+#define HDMI_I2CM_SEGPTR                        0x7E0A
+#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR            0x7E0B
+#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR            0x7E0C
+#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR            0x7E0D
+#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR            0x7E0E
+#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR            0x7E0F
+#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR            0x7E10
+#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR            0x7E11
+#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR            0x7E12
+#define HDMI_I2CM_BUF0                          0x7E20
+
+enum {
+	/* HDMI PHY registers define */
+	PHY_OPMODE_PLLCFG = 0x06,
+	PHY_CKCALCTRL = 0x05,
+	PHY_CKSYMTXCTRL = 0x09,
+	PHY_VLEVCTRL = 0x0e,
+	PHY_PLLCURRCTRL = 0x10,
+	PHY_PLLPHBYCTRL = 0x13,
+	PHY_PLLGMPCTRL = 0x15,
+	PHY_PLLCLKBISTPHASE = 0x17,
+	PHY_TXTERM = 0x19,
+
+	/* ih_phy_stat0 field values */
+	HDMI_IH_PHY_STAT0_HPD = 0x1,
+
+	/* ih_mute field values */
+	HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
+	HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
+
+	/* tx_invid0 field values */
+	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
+	HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
+	HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
+
+	/* tx_instuffing field values */
+	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
+	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
+	HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
+
+	/* vp_pr_cd field values */
+	HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
+	HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
+	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
+
+	/* vp_stuff field values */
+	HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
+	HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
+	HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
+	HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
+	HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
+	HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
+	HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
+	HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
+
+	/* vp_conf field values */
+	HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
+	HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
+	HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
+	HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_PR_EN_MASK = 0x10,
+	HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
+	HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
+	HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
+	HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
+	HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
+	HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
+
+	/* vp_remap field values */
+	HDMI_VP_REMAP_YCC422_16BIT = 0x0,
+
+	/* fc_invidconf field values */
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
+	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
+	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
+	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
+	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
+	HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
+	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
+	HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
+	HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
+
+
+	/* fc_aviconf0-fc_aviconf3 field values */
+	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
+	HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
+	HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
+	HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
+	HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
+	HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
+	HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
+	HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
+	HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
+	HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
+	HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
+
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
+	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
+	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
+	HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
+	HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
+	HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
+	HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
+	HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
+
+	HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
+	HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
+	HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
+	HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
+	HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
+	HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
+	HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
+	HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
+	HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
+	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
+	HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
+	HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
+	HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
+
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
+	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
+	HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
+	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
+	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
+
+	/* fc_gcp field values*/
+	HDMI_FC_GCP_SET_AVMUTE = 0x02,
+	HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
+
+	/* phy_conf0 field values */
+	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
+	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
+	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
+	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
+	HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
+	HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
+	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
+	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
+	HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
+	HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
+	HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
+	HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
+	HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
+
+	/* phy_tst0 field values */
+	HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
+	HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
+
+	/* phy_stat0 field values */
+	HDMI_PHY_HPD = 0x02,
+	HDMI_PHY_TX_PHY_LOCK = 0x01,
+
+	/* phy_i2cm_slave_addr field values */
+	HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
+
+	/* phy_i2cm_operation_addr field values */
+	HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
+
+	/* hdmi_phy_i2cm_int_addr */
+	HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
+
+	/* hdmi_phy_i2cm_ctlint_addr */
+	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
+	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
+
+	/* aud_conf0 field values */
+	HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
+	HDMI_AUD_CONF0_I2S_SELECT = 0x20,
+	HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
+	HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
+	HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
+	HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
+
+	/* aud_conf0 field values */
+	HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
+	HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
+
+	/* aud_n3 field values */
+	HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
+	HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
+
+	/* aud_cts3 field values */
+	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
+	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
+	HDMI_AUD_CTS3_N_SHIFT_1 = 0,
+	HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
+	HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
+	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
+	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
+	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
+	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
+	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
+
+	/* aud_inputclkfs filed values */
+	HDMI_AUD_INPUTCLKFS_128 = 0x0,
+
+	/* mc_clkdis field values */
+	HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
+	HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
+	HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
+	HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
+	HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
+	HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
+	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
+
+	/* mc_swrstz field values */
+	HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
+	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
+
+	/* mc_flowctrl field values */
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
+	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
+
+	/* mc_phyrstz field values */
+	HDMI_MC_PHYRSTZ_ASSERT = 0x0,
+	HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
+
+	/* mc_heacphy_rst field values */
+	HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
+
+	/* i2cm filed values */
+	HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
+	HDMI_I2CM_SEGADDR_DDC = 0x30,
+	HDMI_I2CM_OP_RD8_EXT = 0x2,
+	HDMI_I2CM_OP_RD8 = 0x1,
+	HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
+	HDMI_I2CM_DIV_FAST_MODE = 0x8,
+	HDMI_I2CM_DIV_STD_MODE = 0x0,
+	HDMI_I2CM_SOFTRSTZ_MASK = 0x1,
+
+	/* CSC_CFG field values */
+	HDMI_CSC_CFG_INTMODE_MASK = 0x30,
+	HDMI_CSC_CFG_INTMODE_OFFSET = 4,
+	HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
+	HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
+	HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
+	HDMI_CSC_CFG_DECMODE_MASK = 0x3,
+	HDMI_CSC_CFG_DECMODE_OFFSET = 0,
+	HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
+	HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
+
+	/* CSC_SCALE field values */
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
+	HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
+	HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
+};
+
+struct hdmi_mpll_config {
+	u64 mpixelclock;
+	/* Mode of Operation and PLL Dividers Control Register */
+	u32 cpce;
+	/* PLL Gmp Control Register */
+	u32 gmp;
+	/* PLL Current Control Register */
+	u32 curr;
+};
+
+struct hdmi_phy_config {
+	u64 mpixelclock;
+	u32 sym_ctr;    /* clock symbol and transmitter control */
+	u32 term;       /* transmission termination value */
+	u32 vlev_ctr;   /* voltage level control */
+};
+
+struct hdmi_vmode {
+	bool mdataenablepolarity;
+
+	unsigned int mpixelclock;
+	unsigned int mpixelrepetitioninput;
+	unsigned int mpixelrepetitionoutput;
+};
+
+struct hdmi_data_info {
+	unsigned int enc_in_bus_format;
+	unsigned int enc_out_bus_format;
+	unsigned int enc_in_encoding;
+	unsigned int enc_out_encoding;
+	unsigned int pix_repet_factor;
+	unsigned int hdcp_enable;
+	struct hdmi_vmode video_mode;
+};
+
+struct dw_hdmi {
+	ulong ioaddr;
+	const struct hdmi_mpll_config *mpll_cfg;
+	const struct hdmi_phy_config *phy_cfg;
+	u8 i2c_clk_high;
+	u8 i2c_clk_low;
+	u8 reg_io_width;
+	struct hdmi_data_info hdmi_data;
+	struct udevice *ddc_bus;
+
+	int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
+	void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset);
+	u8 (*read_reg)(struct dw_hdmi *hdmi, int offset);
+};
+
+int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);
+int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi);
+void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
+
+int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
+int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
+void dw_hdmi_init(struct dw_hdmi *hdmi);
+
+#endif
diff --git a/include/dwc3-omap-uboot.h b/include/dwc3-omap-uboot.h
new file mode 100644
index 0000000..7c982e3
--- /dev/null
+++ b/include/dwc3-omap-uboot.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* include/dwc3_omap_uboot.h
+ *
+ * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Designware SuperSpeed OMAP Glue uboot init
+ */
+
+#ifndef __DWC3_OMAP_UBOOT_H_
+#define __DWC3_OMAP_UBOOT_H_
+
+#include <linux/usb/dwc3-omap.h>
+
+enum omap_dwc3_vbus_id_status {
+	OMAP_DWC3_ID_FLOAT,
+	OMAP_DWC3_ID_GROUND,
+	OMAP_DWC3_VBUS_OFF,
+	OMAP_DWC3_VBUS_VALID,
+};
+
+struct dwc3_omap_device {
+	void *base;
+	int index;
+	enum dwc3_omap_utmi_mode utmi_mode;
+	enum omap_dwc3_vbus_id_status vbus_id_status;
+};
+
+int dwc3_omap_uboot_init(struct dwc3_omap_device *dev);
+void dwc3_omap_uboot_exit(int index);
+int dwc3_omap_uboot_interrupt_status(int index);
+#endif /* __DWC3_OMAP_UBOOT_H_ */
diff --git a/include/dwc3-sti-glue.h b/include/dwc3-sti-glue.h
new file mode 100644
index 0000000..e2856f1
--- /dev/null
+++ b/include/dwc3-sti-glue.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef __DWC3_STI_UBOOT_H_
+#define __DWC3_STI_UBOOT_H_
+
+/* glue registers */
+#define CLKRST_CTRL		0x00
+#define AUX_CLK_EN		BIT(0)
+#define SW_PIPEW_RESET_N	BIT(4)
+#define EXT_CFG_RESET_N		BIT(8)
+
+#define XHCI_REVISION		BIT(12)
+
+#define USB2_VBUS_MNGMNT_SEL1	0x2C
+#define USB2_VBUS_UTMIOTG	0x1
+
+#define SEL_OVERRIDE_VBUSVALID(n)	((n) << 0)
+#define SEL_OVERRIDE_POWERPRESENT(n)	((n) << 4)
+#define SEL_OVERRIDE_BVALID(n)		((n) << 8)
+
+/* Static DRD configuration */
+#define USB3_CONTROL_MASK		0xf77
+
+#define USB3_DEVICE_NOT_HOST		BIT(0)
+#define USB3_FORCE_VBUSVALID		BIT(1)
+#define USB3_DELAY_VBUSVALID		BIT(2)
+#define USB3_SEL_FORCE_OPMODE		BIT(4)
+#define USB3_FORCE_OPMODE(n)		((n) << 5)
+#define USB3_SEL_FORCE_DPPULLDOWN2	BIT(8)
+#define USB3_FORCE_DPPULLDOWN2		BIT(9)
+#define USB3_SEL_FORCE_DMPULLDOWN2	BIT(10)
+#define USB3_FORCE_DMPULLDOWN2		BIT(11)
+
+int sti_dwc3_init(enum usb_dr_mode mode);
+
+#endif /* __DWC3_STI_UBOOT_H_ */
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
new file mode 100644
index 0000000..9941cc3
--- /dev/null
+++ b/include/dwc3-uboot.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* include/dwc3-uboot.h
+ *
+ * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Designware SuperSpeed USB uboot init
+ */
+
+#ifndef __DWC3_UBOOT_H_
+#define __DWC3_UBOOT_H_
+
+#include <linux/usb/otg.h>
+
+struct dwc3_device {
+	unsigned long base;
+	enum usb_dr_mode dr_mode;
+	u32 maximum_speed;
+	unsigned tx_fifo_resize:1;
+	unsigned has_lpm_erratum;
+	u8 lpm_nyet_threshold;
+	unsigned is_utmi_l1_suspend;
+	u8 hird_threshold;
+	unsigned disable_scramble_quirk;
+	unsigned u2exit_lfps_quirk;
+	unsigned u2ss_inp3_quirk;
+	unsigned req_p1p2p3_quirk;
+	unsigned del_p1p2p3_quirk;
+	unsigned del_phy_power_chg_quirk;
+	unsigned lfps_filter_quirk;
+	unsigned rx_detect_poll_quirk;
+	unsigned dis_u3_susphy_quirk;
+	unsigned dis_u2_susphy_quirk;
+	unsigned tx_de_emphasis_quirk;
+	unsigned tx_de_emphasis;
+	int index;
+};
+
+int dwc3_uboot_init(struct dwc3_device *dev);
+void dwc3_uboot_exit(int index);
+void dwc3_uboot_handle_interrupt(int index);
+
+struct phy;
+#if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
+int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys);
+int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys);
+#else
+static inline int dwc3_setup_phy(struct udevice *dev, struct phy **array,
+				 int *num_phys)
+{
+	return -ENOTSUPP;
+}
+
+static inline int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys,
+				    int num_phys)
+{
+	return -ENOTSUPP;
+}
+#endif
+
+#endif /* __DWC3_UBOOT_H_ */
diff --git a/include/dwc_ahsata.h b/include/dwc_ahsata.h
new file mode 100644
index 0000000..2aa9342
--- /dev/null
+++ b/include/dwc_ahsata.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __DWC_AHSATA_H__
+#define __DWC_AHSATA_H__
+
+int dwc_ahsata_bus_reset(struct udevice *dev);
+int dwc_ahsata_probe(struct udevice *dev);
+int dwc_ahsata_scan(struct udevice *dev);
+int dwc_ahsata_port_status(struct udevice *dev, int port);
+
+#endif
diff --git a/include/dwmmc.h b/include/dwmmc.h
new file mode 100644
index 0000000..f06720d
--- /dev/null
+++ b/include/dwmmc.h
@@ -0,0 +1,309 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ */
+
+#ifndef __DWMMC_HW_H
+#define __DWMMC_HW_H
+
+#include <asm/io.h>
+#include <mmc.h>
+
+#define DWMCI_CTRL		0x000
+#define	DWMCI_PWREN		0x004
+#define DWMCI_CLKDIV		0x008
+#define DWMCI_CLKSRC		0x00C
+#define DWMCI_CLKENA		0x010
+#define DWMCI_TMOUT		0x014
+#define DWMCI_CTYPE		0x018
+#define DWMCI_BLKSIZ		0x01C
+#define DWMCI_BYTCNT		0x020
+#define DWMCI_INTMASK		0x024
+#define DWMCI_CMDARG		0x028
+#define DWMCI_CMD		0x02C
+#define DWMCI_RESP0		0x030
+#define DWMCI_RESP1		0x034
+#define DWMCI_RESP2		0x038
+#define DWMCI_RESP3		0x03C
+#define DWMCI_MINTSTS		0x040
+#define DWMCI_RINTSTS		0x044
+#define DWMCI_STATUS		0x048
+#define DWMCI_FIFOTH		0x04C
+#define DWMCI_CDETECT		0x050
+#define DWMCI_WRTPRT		0x054
+#define DWMCI_GPIO		0x058
+#define DWMCI_TCMCNT		0x05C
+#define DWMCI_TBBCNT		0x060
+#define DWMCI_DEBNCE		0x064
+#define DWMCI_USRID		0x068
+#define DWMCI_VERID		0x06C
+#define DWMCI_HCON		0x070
+#define DWMCI_UHS_REG		0x074
+#define DWMCI_BMOD		0x080
+#define DWMCI_PLDMND		0x084
+#define DWMCI_DBADDR		0x088
+#define DWMCI_IDSTS		0x08C
+#define DWMCI_IDINTEN		0x090
+#define DWMCI_DSCADDR		0x094
+#define DWMCI_BUFADDR		0x098
+#define DWMCI_DATA		0x200
+
+/* Interrupt Mask register */
+#define DWMCI_INTMSK_ALL	0xffffffff
+#define DWMCI_INTMSK_RE		(1 << 1)
+#define DWMCI_INTMSK_CDONE	(1 << 2)
+#define DWMCI_INTMSK_DTO	(1 << 3)
+#define DWMCI_INTMSK_TXDR	(1 << 4)
+#define DWMCI_INTMSK_RXDR	(1 << 5)
+#define DWMCI_INTMSK_RCRC	(1 << 6)
+#define DWMCI_INTMSK_DCRC	(1 << 7)
+#define DWMCI_INTMSK_RTO	(1 << 8)
+#define DWMCI_INTMSK_DRTO	(1 << 9)
+#define DWMCI_INTMSK_HTO	(1 << 10)
+#define DWMCI_INTMSK_FRUN	(1 << 11)
+#define DWMCI_INTMSK_HLE	(1 << 12)
+#define DWMCI_INTMSK_SBE	(1 << 13)
+#define DWMCI_INTMSK_ACD	(1 << 14)
+#define DWMCI_INTMSK_EBE	(1 << 15)
+
+/* Raw interrupt Regsiter */
+#define DWMCI_DATA_ERR	(DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
+			DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
+#define DWMCI_DATA_TOUT	(DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
+/* CTRL register */
+#define DWMCI_CTRL_RESET	(1 << 0)
+#define DWMCI_CTRL_FIFO_RESET	(1 << 1)
+#define DWMCI_CTRL_DMA_RESET	(1 << 2)
+#define DWMCI_DMA_EN		(1 << 5)
+#define DWMCI_CTRL_SEND_AS_CCSD	(1 << 10)
+#define DWMCI_IDMAC_EN		(1 << 25)
+#define DWMCI_RESET_ALL		(DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
+				DWMCI_CTRL_DMA_RESET)
+
+/* CMD register */
+#define DWMCI_CMD_RESP_EXP	(1 << 6)
+#define DWMCI_CMD_RESP_LENGTH	(1 << 7)
+#define DWMCI_CMD_CHECK_CRC	(1 << 8)
+#define DWMCI_CMD_DATA_EXP	(1 << 9)
+#define DWMCI_CMD_RW		(1 << 10)
+#define DWMCI_CMD_SEND_STOP	(1 << 12)
+#define DWMCI_CMD_ABORT_STOP	(1 << 14)
+#define DWMCI_CMD_PRV_DAT_WAIT	(1 << 13)
+#define DWMCI_CMD_UPD_CLK	(1 << 21)
+#define DWMCI_CMD_USE_HOLD_REG	(1 << 29)
+#define DWMCI_CMD_START		(1 << 31)
+
+/* CLKENA register */
+#define DWMCI_CLKEN_ENABLE	(1 << 0)
+#define DWMCI_CLKEN_LOW_PWR	(1 << 16)
+
+/* Card-type registe */
+#define DWMCI_CTYPE_1BIT	0
+#define DWMCI_CTYPE_4BIT	(1 << 0)
+#define DWMCI_CTYPE_8BIT	(1 << 16)
+
+/* Status Register */
+#define DWMCI_FIFO_EMPTY	(1 << 2)
+#define DWMCI_FIFO_FULL		(1 << 3)
+#define DWMCI_BUSY		(1 << 9)
+#define DWMCI_FIFO_MASK		0x1fff
+#define DWMCI_FIFO_SHIFT	17
+
+/* FIFOTH Register */
+#define MSIZE(x)		((x) << 28)
+#define RX_WMARK(x)		((x) << 16)
+#define TX_WMARK(x)		(x)
+#define RX_WMARK_SHIFT		16
+#define RX_WMARK_MASK		(0xfff << RX_WMARK_SHIFT)
+
+#define DWMCI_IDMAC_OWN		(1 << 31)
+#define DWMCI_IDMAC_CH		(1 << 4)
+#define DWMCI_IDMAC_FS		(1 << 3)
+#define DWMCI_IDMAC_LD		(1 << 2)
+
+/*  Bus Mode Register */
+#define DWMCI_BMOD_IDMAC_RESET	(1 << 0)
+#define DWMCI_BMOD_IDMAC_FB	(1 << 1)
+#define DWMCI_BMOD_IDMAC_EN	(1 << 7)
+
+/* UHS register */
+#define DWMCI_DDR_MODE	(1 << 16)
+
+/* Internal IDMAC interrupt defines */
+#define DWMCI_IDINTEN_RI		BIT(1)
+#define DWMCI_IDINTEN_TI		BIT(0)
+
+#define DWMCI_IDINTEN_MASK	(DWMCI_IDINTEN_TI | \
+				 DWMCI_IDINTEN_RI)
+
+/* quirks */
+#define DWMCI_QUIRK_DISABLE_SMU		(1 << 0)
+
+/**
+ * struct dwmci_host - Information about a designware MMC host
+ *
+ * @name:	Device name
+ * @ioaddr:	Base I/O address of controller
+ * @quirks:	Quick flags - see DWMCI_QUIRK_...
+ * @caps:	Capabilities - see MMC_MODE_...
+ * @bus_hz:	Bus speed in Hz, if @get_mmc_clk() is NULL
+ * @div:	Arbitrary clock divider value for use by controller
+ * @dev_index:	Arbitrary device index for use by controller
+ * @dev_id:	Arbitrary device ID for use by controller
+ * @buswidth:	Bus width in bits (8 or 4)
+ * @fifoth_val:	Value for FIFOTH register (or 0 to leave unset)
+ * @mmc:	Pointer to generic MMC structure for this device
+ * @priv:	Private pointer for use by controller
+ */
+struct dwmci_host {
+	const char *name;
+	void *ioaddr;
+	unsigned int quirks;
+	unsigned int caps;
+	unsigned int version;
+	unsigned int clock;
+	unsigned int bus_hz;
+	unsigned int div;
+	int dev_index;
+	int dev_id;
+	int buswidth;
+	u32 fifoth_val;
+	struct mmc *mmc;
+	void *priv;
+
+	void (*clksel)(struct dwmci_host *host);
+	void (*board_init)(struct dwmci_host *host);
+
+	/**
+	 * Get / set a particular MMC clock frequency
+	 *
+	 * This is used to request the current clock frequency of the clock
+	 * that drives the DWMMC peripheral. The caller will then use this
+	 * information to work out the divider it needs to achieve the
+	 * required MMC bus clock frequency. If you want to handle the
+	 * clock external to DWMMC, use @freq to select the frequency and
+	 * return that value too. Then DWMMC will put itself in bypass mode.
+	 *
+	 * @host:	DWMMC host
+	 * @freq:	Frequency the host is trying to achieve
+	 */
+	unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
+#ifndef CONFIG_BLK
+	struct mmc_config cfg;
+#endif
+
+	/* use fifo mode to read and write data */
+	bool fifo_mode;
+};
+
+struct dwmci_idmac {
+	u32 flags;
+	u32 cnt;
+	u32 addr;
+	u32 next_addr;
+} __aligned(ARCH_DMA_MINALIGN);
+
+static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
+{
+	writel(val, host->ioaddr + reg);
+}
+
+static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
+{
+	writew(val, host->ioaddr + reg);
+}
+
+static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
+{
+	writeb(val, host->ioaddr + reg);
+}
+static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
+{
+	return readl(host->ioaddr + reg);
+}
+
+static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
+{
+	return readw(host->ioaddr + reg);
+}
+
+static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
+{
+	return readb(host->ioaddr + reg);
+}
+
+#ifdef CONFIG_BLK
+/**
+ * dwmci_setup_cfg() - Set up the configuration for DWMMC
+ *
+ * This is used to set up a DWMMC device when you are using CONFIG_BLK.
+ *
+ * This should be called from your MMC driver's probe() method once you have
+ * the information required.
+ *
+ * Generally your driver will have a platform data structure which holds both
+ * the configuration (struct mmc_config) and the MMC device info (struct mmc).
+ * For example:
+ *
+ * struct rockchip_mmc_plat {
+ *	struct mmc_config cfg;
+ *	struct mmc mmc;
+ * };
+ *
+ * ...
+ *
+ * Inside U_BOOT_DRIVER():
+ *	.platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
+ *
+ * To access platform data:
+ *	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+ *
+ * See rockchip_dw_mmc.c for an example.
+ *
+ * @cfg:	Configuration structure to fill in (generally &plat->mmc)
+ * @host:	DWMMC host
+ * @max_clk:	Maximum supported clock speed in HZ (e.g. 150000000)
+ * @min_clk:	Minimum supported clock speed in HZ (e.g. 400000)
+ */
+void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
+		u32 max_clk, u32 min_clk);
+
+/**
+ * dwmci_bind() - Set up a new MMC block device
+ *
+ * This is used to set up a DWMMC block device when you are using CONFIG_BLK.
+ * It should be called from your driver's bind() method.
+ *
+ * See rockchip_dw_mmc.c for an example.
+ *
+ * @dev:	Device to set up
+ * @mmc:	Pointer to mmc structure (normally &plat->mmc)
+ * @cfg:	Empty configuration structure (generally &plat->cfg). This is
+ *		normally all zeroes at this point. The only purpose of passing
+ *		this in is to set mmc->cfg to it.
+ * @return 0 if OK, -ve if the block device could not be created
+ */
+int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
+
+#else
+/**
+ * add_dwmci() - Add a new DWMMC interface
+ *
+ * This is used when you are not using CONFIG_BLK. Convert your driver over!
+ *
+ * @host:	DWMMC host structure
+ * @max_clk:	Maximum supported clock speed in HZ (e.g. 150000000)
+ * @min_clk:	Minimum supported clock speed in HZ (e.g. 400000)
+ * @return 0 if OK, -ve on error
+ */
+int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
+#endif /* !CONFIG_BLK */
+
+#ifdef CONFIG_DM_MMC
+/* Export the operations to drivers */
+int dwmci_probe(struct udevice *dev);
+extern const struct dm_mmc_ops dm_dwmci_ops;
+#endif
+
+#endif	/* __DWMMC_HW_H */
diff --git a/include/e500.h b/include/e500.h
new file mode 100644
index 0000000..1acf778
--- /dev/null
+++ b/include/e500.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2003 Motorola,Inc.
+ * Xianghua Xiao(x.xiao@motorola.com)
+ */
+
+#ifndef	__E500_H__
+#define __E500_H__
+
+#ifndef __ASSEMBLY__
+
+typedef struct
+{
+	unsigned long freq_processor[CONFIG_MAX_CPUS];
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+	unsigned long freq_processor_dsp[CONFIG_MAX_DSP_CPUS];
+#endif
+	unsigned long freq_systembus;
+	unsigned long freq_ddrbus;
+	unsigned long freq_localbus;
+	unsigned long freq_qe;
+	unsigned long freq_sdhc;
+#ifdef CONFIG_SYS_DPAA_FMAN
+	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	unsigned long freq_qman;
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	unsigned long freq_pme;
+#endif
+#ifdef CONFIG_SYS_CPRI
+	unsigned long freq_cpri;
+#endif
+#ifdef CONFIG_SYS_MAPLE
+	unsigned long freq_maple;
+	unsigned long freq_maple_ulb;
+	unsigned long freq_maple_etvpe;
+#endif
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+	unsigned char diff_sysclk;
+#endif
+} MPC85xx_SYS_INFO;
+
+#endif  /* _ASMLANGUAGE */
+
+#define RESET_VECTOR	0xfffffffc
+
+#endif	/* __E500_H__ */
diff --git a/include/ec_commands.h b/include/ec_commands.h
new file mode 100644
index 0000000..444ba61
--- /dev/null
+++ b/include/ec_commands.h
@@ -0,0 +1,4605 @@
+/* Copyright (c) 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Host communication command constants for Chrome EC */
+
+#ifndef __CROS_EC_COMMANDS_H
+#define __CROS_EC_COMMANDS_H
+
+/*
+ * Protocol overview
+ *
+ * request:  CMD [ P0 P1 P2 ... Pn S ]
+ * response: ERR [ P0 P1 P2 ... Pn S ]
+ *
+ * where the bytes are defined as follow :
+ *      - CMD is the command code. (defined by EC_CMD_ constants)
+ *      - ERR is the error code. (defined by EC_RES_ constants)
+ *      - Px is the optional payload.
+ *        it is not sent if the error code is not success.
+ *        (defined by ec_params_ and ec_response_ structures)
+ *      - S is the checksum which is the sum of all payload bytes.
+ *
+ * On LPC, CMD and ERR are sent/received at EC_LPC_ADDR_KERNEL|USER_CMD
+ * and the payloads are sent/received at EC_LPC_ADDR_KERNEL|USER_PARAM.
+ * On I2C, all bytes are sent serially in the same message.
+ */
+
+/*
+ * Current version of this protocol
+ *
+ * TODO(crosbug.com/p/11223): This is effectively useless; protocol is
+ * determined in other ways.  Remove this once the kernel code no longer
+ * depends on it.
+ */
+#define EC_PROTO_VERSION          0x00000002
+
+/* Command version mask */
+#define EC_VER_MASK(version) (1UL << (version))
+
+/* I/O addresses for ACPI commands */
+#define EC_LPC_ADDR_ACPI_DATA  0x62
+#define EC_LPC_ADDR_ACPI_CMD   0x66
+
+/* I/O addresses for host command */
+#define EC_LPC_ADDR_HOST_DATA  0x200
+#define EC_LPC_ADDR_HOST_CMD   0x204
+
+/* I/O addresses for host command args and params */
+/* Protocol version 2 */
+#define EC_LPC_ADDR_HOST_ARGS    0x800  /* And 0x801, 0x802, 0x803 */
+#define EC_LPC_ADDR_HOST_PARAM   0x804  /* For version 2 params; size is
+					 * EC_PROTO2_MAX_PARAM_SIZE */
+/* Protocol version 3 */
+#define EC_LPC_ADDR_HOST_PACKET  0x800  /* Offset of version 3 packet */
+#define EC_LPC_HOST_PACKET_SIZE  0x100  /* Max size of version 3 packet */
+
+/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
+ * and they tell the kernel that so we have to think of it as two parts. */
+#define EC_HOST_CMD_REGION0    0x800
+#define EC_HOST_CMD_REGION1    0x880
+#define EC_HOST_CMD_REGION_SIZE 0x80
+
+/* EC command register bit functions */
+#define EC_LPC_CMDR_DATA	(1 << 0)  /* Data ready for host to read */
+#define EC_LPC_CMDR_PENDING	(1 << 1)  /* Write pending to EC */
+#define EC_LPC_CMDR_BUSY	(1 << 2)  /* EC is busy processing a command */
+#define EC_LPC_CMDR_CMD		(1 << 3)  /* Last host write was a command */
+#define EC_LPC_CMDR_ACPI_BRST	(1 << 4)  /* Burst mode (not used) */
+#define EC_LPC_CMDR_SCI		(1 << 5)  /* SCI event is pending */
+#define EC_LPC_CMDR_SMI		(1 << 6)  /* SMI event is pending */
+
+/* MEC uses 0x800/0x804 as register/index pair, thus an 8-byte resource */
+#define MEC_EMI_BASE		0x800
+#define MEC_EMI_SIZE		8
+
+#define EC_LPC_ADDR_MEMMAP       0x900
+#define EC_MEMMAP_SIZE         255 /* ACPI IO buffer max is 255 bytes */
+#define EC_MEMMAP_TEXT_MAX     8   /* Size of a string in the memory map */
+
+/* The offset address of each type of data in mapped memory. */
+#define EC_MEMMAP_TEMP_SENSOR      0x00 /* Temp sensors 0x00 - 0x0f */
+#define EC_MEMMAP_FAN              0x10 /* Fan speeds 0x10 - 0x17 */
+#define EC_MEMMAP_TEMP_SENSOR_B    0x18 /* More temp sensors 0x18 - 0x1f */
+#define EC_MEMMAP_ID               0x20 /* 0x20 == 'E', 0x21 == 'C' */
+#define EC_MEMMAP_ID_VERSION       0x22 /* Version of data in 0x20 - 0x2f */
+#define EC_MEMMAP_THERMAL_VERSION  0x23 /* Version of data in 0x00 - 0x1f */
+#define EC_MEMMAP_BATTERY_VERSION  0x24 /* Version of data in 0x40 - 0x7f */
+#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */
+#define EC_MEMMAP_EVENTS_VERSION   0x26 /* Version of data in 0x34 - 0x3f */
+#define EC_MEMMAP_HOST_CMD_FLAGS   0x27 /* Host cmd interface flags (8 bits) */
+/* Unused 0x28 - 0x2f */
+#define EC_MEMMAP_SWITCHES         0x30	/* 8 bits */
+/* Unused 0x31 - 0x33 */
+#define EC_MEMMAP_HOST_EVENTS      0x34 /* 32 bits */
+/* Reserve 0x38 - 0x3f for additional host event-related stuff */
+/* Battery values are all 32 bits */
+#define EC_MEMMAP_BATT_VOLT        0x40 /* Battery Present Voltage */
+#define EC_MEMMAP_BATT_RATE        0x44 /* Battery Present Rate */
+#define EC_MEMMAP_BATT_CAP         0x48 /* Battery Remaining Capacity */
+#define EC_MEMMAP_BATT_FLAG        0x4c /* Battery State, defined below */
+#define EC_MEMMAP_BATT_DCAP        0x50 /* Battery Design Capacity */
+#define EC_MEMMAP_BATT_DVLT        0x54 /* Battery Design Voltage */
+#define EC_MEMMAP_BATT_LFCC        0x58 /* Battery Last Full Charge Capacity */
+#define EC_MEMMAP_BATT_CCNT        0x5c /* Battery Cycle Count */
+/* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */
+#define EC_MEMMAP_BATT_MFGR        0x60 /* Battery Manufacturer String */
+#define EC_MEMMAP_BATT_MODEL       0x68 /* Battery Model Number String */
+#define EC_MEMMAP_BATT_SERIAL      0x70 /* Battery Serial Number String */
+#define EC_MEMMAP_BATT_TYPE        0x78 /* Battery Type String */
+#define EC_MEMMAP_ALS              0x80 /* ALS readings in lux (2 X 16 bits) */
+/* Unused 0x84 - 0x8f */
+#define EC_MEMMAP_ACC_STATUS       0x90 /* Accelerometer status (8 bits )*/
+/* Unused 0x91 */
+#define EC_MEMMAP_ACC_DATA         0x92 /* Accelerometers data 0x92 - 0x9f */
+/* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */
+/* 0x94 - 0x99: 1st Accelerometer */
+/* 0x9a - 0x9f: 2nd Accelerometer */
+#define EC_MEMMAP_GYRO_DATA        0xa0 /* Gyroscope data 0xa0 - 0xa5 */
+/* Unused 0xa6 - 0xdf */
+
+/*
+ * ACPI is unable to access memory mapped data at or above this offset due to
+ * limitations of the ACPI protocol. Do not place data in the range 0xe0 - 0xfe
+ * which might be needed by ACPI.
+ */
+#define EC_MEMMAP_NO_ACPI 0xe0
+
+/* Define the format of the accelerometer mapped memory status byte. */
+#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK  0x0f
+#define EC_MEMMAP_ACC_STATUS_BUSY_BIT        (1 << 4)
+#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT    (1 << 7)
+
+/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */
+#define EC_TEMP_SENSOR_ENTRIES     16
+/*
+ * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B.
+ *
+ * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2.
+ */
+#define EC_TEMP_SENSOR_B_ENTRIES      8
+
+/* Special values for mapped temperature sensors */
+#define EC_TEMP_SENSOR_NOT_PRESENT    0xff
+#define EC_TEMP_SENSOR_ERROR          0xfe
+#define EC_TEMP_SENSOR_NOT_POWERED    0xfd
+#define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc
+/*
+ * The offset of temperature value stored in mapped memory.  This allows
+ * reporting a temperature range of 200K to 454K = -73C to 181C.
+ */
+#define EC_TEMP_SENSOR_OFFSET      200
+
+/*
+ * Number of ALS readings at EC_MEMMAP_ALS
+ */
+#define EC_ALS_ENTRIES             2
+
+/*
+ * The default value a temperature sensor will return when it is present but
+ * has not been read this boot.  This is a reasonable number to avoid
+ * triggering alarms on the host.
+ */
+#define EC_TEMP_SENSOR_DEFAULT     (296 - EC_TEMP_SENSOR_OFFSET)
+
+#define EC_FAN_SPEED_ENTRIES       4       /* Number of fans at EC_MEMMAP_FAN */
+#define EC_FAN_SPEED_NOT_PRESENT   0xffff  /* Entry not present */
+#define EC_FAN_SPEED_STALLED       0xfffe  /* Fan stalled */
+
+/* Battery bit flags at EC_MEMMAP_BATT_FLAG. */
+#define EC_BATT_FLAG_AC_PRESENT   0x01
+#define EC_BATT_FLAG_BATT_PRESENT 0x02
+#define EC_BATT_FLAG_DISCHARGING  0x04
+#define EC_BATT_FLAG_CHARGING     0x08
+#define EC_BATT_FLAG_LEVEL_CRITICAL 0x10
+
+/* Switch flags at EC_MEMMAP_SWITCHES */
+#define EC_SWITCH_LID_OPEN               0x01
+#define EC_SWITCH_POWER_BUTTON_PRESSED   0x02
+#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
+/* Was recovery requested via keyboard; now unused. */
+#define EC_SWITCH_IGNORE1		 0x08
+/* Recovery requested via dedicated signal (from servo board) */
+#define EC_SWITCH_DEDICATED_RECOVERY     0x10
+/* Was fake developer mode switch; now unused.  Remove in next refactor. */
+#define EC_SWITCH_IGNORE0                0x20
+
+/* Host command interface flags */
+/* Host command interface supports LPC args (LPC interface only) */
+#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED  0x01
+/* Host command interface supports version 3 protocol */
+#define EC_HOST_CMD_FLAG_VERSION_3   0x02
+
+/* Wireless switch flags */
+#define EC_WIRELESS_SWITCH_ALL       ~0x00  /* All flags */
+#define EC_WIRELESS_SWITCH_WLAN       0x01  /* WLAN radio */
+#define EC_WIRELESS_SWITCH_BLUETOOTH  0x02  /* Bluetooth radio */
+#define EC_WIRELESS_SWITCH_WWAN       0x04  /* WWAN power */
+#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08  /* WLAN power */
+
+/*****************************************************************************/
+/*
+ * ACPI commands
+ *
+ * These are valid ONLY on the ACPI command/data port.
+ */
+
+/*
+ * ACPI Read Embedded Controller
+ *
+ * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*).
+ *
+ * Use the following sequence:
+ *
+ *    - Write EC_CMD_ACPI_READ to EC_LPC_ADDR_ACPI_CMD
+ *    - Wait for EC_LPC_CMDR_PENDING bit to clear
+ *    - Write address to EC_LPC_ADDR_ACPI_DATA
+ *    - Wait for EC_LPC_CMDR_DATA bit to set
+ *    - Read value from EC_LPC_ADDR_ACPI_DATA
+ */
+#define EC_CMD_ACPI_READ 0x0080
+
+/*
+ * ACPI Write Embedded Controller
+ *
+ * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*).
+ *
+ * Use the following sequence:
+ *
+ *    - Write EC_CMD_ACPI_WRITE to EC_LPC_ADDR_ACPI_CMD
+ *    - Wait for EC_LPC_CMDR_PENDING bit to clear
+ *    - Write address to EC_LPC_ADDR_ACPI_DATA
+ *    - Wait for EC_LPC_CMDR_PENDING bit to clear
+ *    - Write value to EC_LPC_ADDR_ACPI_DATA
+ */
+#define EC_CMD_ACPI_WRITE 0x0081
+
+/*
+ * ACPI Burst Enable Embedded Controller
+ *
+ * This enables burst mode on the EC to allow the host to issue several
+ * commands back-to-back. While in this mode, writes to mapped multi-byte
+ * data are locked out to ensure data consistency.
+ */
+#define EC_CMD_ACPI_BURST_ENABLE 0x0082
+
+/*
+ * ACPI Burst Disable Embedded Controller
+ *
+ * This disables burst mode on the EC and stops preventing EC writes to mapped
+ * multi-byte data.
+ */
+#define EC_CMD_ACPI_BURST_DISABLE 0x0083
+
+/*
+ * ACPI Query Embedded Controller
+ *
+ * This clears the lowest-order bit in the currently pending host events, and
+ * sets the result code to the 1-based index of the bit (event 0x00000001 = 1,
+ * event 0x80000000 = 32), or 0 if no event was pending.
+ */
+#define EC_CMD_ACPI_QUERY_EVENT 0x0084
+
+/* Valid addresses in ACPI memory space, for read/write commands */
+
+/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */
+#define EC_ACPI_MEM_VERSION            0x00
+/*
+ * Test location; writing value here updates test compliment byte to (0xff -
+ * value).
+ */
+#define EC_ACPI_MEM_TEST               0x01
+/* Test compliment; writes here are ignored. */
+#define EC_ACPI_MEM_TEST_COMPLIMENT    0x02
+
+/* Keyboard backlight brightness percent (0 - 100) */
+#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
+/* DPTF Target Fan Duty (0-100, 0xff for auto/none) */
+#define EC_ACPI_MEM_FAN_DUTY           0x04
+
+/*
+ * DPTF temp thresholds. Any of the EC's temp sensors can have up to two
+ * independent thresholds attached to them. The current value of the ID
+ * register determines which sensor is affected by the THRESHOLD and COMMIT
+ * registers. The THRESHOLD register uses the same EC_TEMP_SENSOR_OFFSET scheme
+ * as the memory-mapped sensors. The COMMIT register applies those settings.
+ *
+ * The spec does not mandate any way to read back the threshold settings
+ * themselves, but when a threshold is crossed the AP needs a way to determine
+ * which sensor(s) are responsible. Each reading of the ID register clears and
+ * returns one sensor ID that has crossed one of its threshold (in either
+ * direction) since the last read. A value of 0xFF means "no new thresholds
+ * have tripped". Setting or enabling the thresholds for a sensor will clear
+ * the unread event count for that sensor.
+ */
+#define EC_ACPI_MEM_TEMP_ID            0x05
+#define EC_ACPI_MEM_TEMP_THRESHOLD     0x06
+#define EC_ACPI_MEM_TEMP_COMMIT        0x07
+/*
+ * Here are the bits for the COMMIT register:
+ *   bit 0 selects the threshold index for the chosen sensor (0/1)
+ *   bit 1 enables/disables the selected threshold (0 = off, 1 = on)
+ * Each write to the commit register affects one threshold.
+ */
+#define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK (1 << 0)
+#define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK (1 << 1)
+/*
+ * Example:
+ *
+ * Set the thresholds for sensor 2 to 50 C and 60 C:
+ *   write 2 to [0x05]      --  select temp sensor 2
+ *   write 0x7b to [0x06]   --  C_TO_K(50) - EC_TEMP_SENSOR_OFFSET
+ *   write 0x2 to [0x07]    --  enable threshold 0 with this value
+ *   write 0x85 to [0x06]   --  C_TO_K(60) - EC_TEMP_SENSOR_OFFSET
+ *   write 0x3 to [0x07]    --  enable threshold 1 with this value
+ *
+ * Disable the 60 C threshold, leaving the 50 C threshold unchanged:
+ *   write 2 to [0x05]      --  select temp sensor 2
+ *   write 0x1 to [0x07]    --  disable threshold 1
+ */
+
+/* DPTF battery charging current limit */
+#define EC_ACPI_MEM_CHARGING_LIMIT     0x08
+
+/* Charging limit is specified in 64 mA steps */
+#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA   64
+/* Value to disable DPTF battery charging limit */
+#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED  0xff
+
+/*
+ * Report device orientation
+ *   bit 0 device is tablet mode
+ */
+#define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09
+#define EC_ACPI_MEM_DEVICE_TABLET_MODE 0x01
+
+/*
+ * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf.  This data
+ * is read-only from the AP.  Added in EC_ACPI_MEM_VERSION 2.
+ */
+#define EC_ACPI_MEM_MAPPED_BEGIN   0x20
+#define EC_ACPI_MEM_MAPPED_SIZE    0xe0
+
+/* Current version of ACPI memory address space */
+#define EC_ACPI_MEM_VERSION_CURRENT 2
+
+
+/*
+ * This header file is used in coreboot both in C and ACPI code.  The ACPI code
+ * is pre-processed to handle constants but the ASL compiler is unable to
+ * handle actual C code so keep it separate.
+ */
+#ifndef __ACPI__
+
+/*
+ * Define __packed if someone hasn't beat us to it.  Linux kernel style
+ * checking prefers __packed over __attribute__((packed)).
+ */
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+
+#ifndef __aligned
+#define __aligned(x) __attribute__((aligned(x)))
+#endif
+
+/*
+ * Attributes for EC request and response packets.  Just defining __packed
+ * results in inefficient assembly code on ARM, if the structure is actually
+ * 32-bit aligned, as it should be for all buffers.
+ *
+ * Be very careful when adding these to existing structures.  They will round
+ * up the structure size to the specified boundary.
+ *
+ * Also be very careful to make that if a structure is included in some other
+ * parent structure that the alignment will still be true given the packing of
+ * the parent structure.  This is particularly important if the sub-structure
+ * will be passed as a pointer to another function, since that function will
+ * not know about the misaligment caused by the parent structure's packing.
+ *
+ * Also be very careful using __packed - particularly when nesting non-packed
+ * structures inside packed ones.  In fact, DO NOT use __packed directly;
+ * always use one of these attributes.
+ *
+ * Once everything is annotated properly, the following search strings should
+ * not return ANY matches in this file other than right here:
+ *
+ * "__packed" - generates inefficient code; all sub-structs must also be packed
+ *
+ * "struct [^_]" - all structs should be annotated, except for structs that are
+ * members of other structs/unions (and their original declarations should be
+ * annotated).
+ */
+#ifdef CONFIG_HOSTCMD_ALIGNED
+
+/*
+ * Packed structures where offset and size are always aligned to 1, 2, or 4
+ * byte boundary.
+ */
+#define __ec_align1 __packed
+#define __ec_align2 __packed __aligned(2)
+#define __ec_align4 __packed __aligned(4)
+
+/*
+ * Packed structure which must be under-aligned, because its size is not a
+ * 4-byte multiple.  This is sub-optimal because it forces byte-wise access
+ * of all multi-byte fields in it, even though they are themselves aligned.
+ *
+ * In theory, we could duplicate the structure with __aligned(4) for accessing
+ * its members, but use the __packed version for sizeof().
+ */
+#define __ec_align_size1 __packed
+
+/*
+ * Packed structure which must be under-aligned, because its offset inside a
+ * parent structure is not a 4-byte multiple.
+ */
+#define __ec_align_offset1 __packed
+#define __ec_align_offset2 __packed __aligned(2)
+
+/*
+ * Structures which are complicated enough that I'm skipping them on the first
+ * pass.  They are effectively unchanged from their previous definitions.
+ *
+ * TODO(rspangler): Figure out what to do with these.  It's likely necessary
+ * to work out the size and offset of each member and add explicit padding to
+ * maintain those.
+ */
+#define __ec_todo_packed __packed
+#define __ec_todo_unpacked
+
+#else  /* !CONFIG_HOSTCMD_ALIGNED */
+
+/*
+ * Packed structures make no assumption about alignment, so they do inefficient
+ * byte-wise reads.
+ */
+#define __ec_align1 __packed
+#define __ec_align2 __packed
+#define __ec_align4 __packed
+#define __ec_align_size1 __packed
+#define __ec_align_offset1 __packed
+#define __ec_align_offset2 __packed
+#define __ec_todo_packed __packed
+#define __ec_todo_unpacked
+
+#endif  /* !CONFIG_HOSTCMD_ALIGNED */
+
+/* LPC command status byte masks */
+/* EC has written a byte in the data register and host hasn't read it yet */
+#define EC_LPC_STATUS_TO_HOST     0x01
+/* Host has written a command/data byte and the EC hasn't read it yet */
+#define EC_LPC_STATUS_FROM_HOST   0x02
+/* EC is processing a command */
+#define EC_LPC_STATUS_PROCESSING  0x04
+/* Last write to EC was a command, not data */
+#define EC_LPC_STATUS_LAST_CMD    0x08
+/* EC is in burst mode */
+#define EC_LPC_STATUS_BURST_MODE  0x10
+/* SCI event is pending (requesting SCI query) */
+#define EC_LPC_STATUS_SCI_PENDING 0x20
+/* SMI event is pending (requesting SMI query) */
+#define EC_LPC_STATUS_SMI_PENDING 0x40
+/* (reserved) */
+#define EC_LPC_STATUS_RESERVED    0x80
+
+/*
+ * EC is busy.  This covers both the EC processing a command, and the host has
+ * written a new command but the EC hasn't picked it up yet.
+ */
+#define EC_LPC_STATUS_BUSY_MASK \
+	(EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING)
+
+/* Host command response codes (16-bit).  Note that response codes should be
+ * stored in a uint16_t rather than directly in a value of this type.
+ */
+enum ec_status {
+	EC_RES_SUCCESS = 0,
+	EC_RES_INVALID_COMMAND = 1,
+	EC_RES_ERROR = 2,
+	EC_RES_INVALID_PARAM = 3,
+	EC_RES_ACCESS_DENIED = 4,
+	EC_RES_INVALID_RESPONSE = 5,
+	EC_RES_INVALID_VERSION = 6,
+	EC_RES_INVALID_CHECKSUM = 7,
+	EC_RES_IN_PROGRESS = 8,		/* Accepted, command in progress */
+	EC_RES_UNAVAILABLE = 9,		/* No response available */
+	EC_RES_TIMEOUT = 10,		/* We got a timeout */
+	EC_RES_OVERFLOW = 11,		/* Table / data overflow */
+	EC_RES_INVALID_HEADER = 12,     /* Header contains invalid data */
+	EC_RES_REQUEST_TRUNCATED = 13,  /* Didn't get the entire request */
+	EC_RES_RESPONSE_TOO_BIG = 14,   /* Response was too big to handle */
+	EC_RES_BUS_ERROR = 15,		/* Communications bus error */
+	EC_RES_BUSY = 16		/* Up but too busy.  Should retry */
+};
+
+/*
+ * Host event codes.  Note these are 1-based, not 0-based, because ACPI query
+ * EC command uses code 0 to mean "no event pending".  We explicitly specify
+ * each value in the enum listing so they won't change if we delete/insert an
+ * item or rearrange the list (it needs to be stable across platforms, not
+ * just within a single compiled instance).
+ */
+enum host_event_code {
+	EC_HOST_EVENT_LID_CLOSED = 1,
+	EC_HOST_EVENT_LID_OPEN = 2,
+	EC_HOST_EVENT_POWER_BUTTON = 3,
+	EC_HOST_EVENT_AC_CONNECTED = 4,
+	EC_HOST_EVENT_AC_DISCONNECTED = 5,
+	EC_HOST_EVENT_BATTERY_LOW = 6,
+	EC_HOST_EVENT_BATTERY_CRITICAL = 7,
+	EC_HOST_EVENT_BATTERY = 8,
+	EC_HOST_EVENT_THERMAL_THRESHOLD = 9,
+	/* Event generated by a device attached to the EC */
+	EC_HOST_EVENT_DEVICE = 10,
+	EC_HOST_EVENT_THERMAL = 11,
+	EC_HOST_EVENT_USB_CHARGER = 12,
+	EC_HOST_EVENT_KEY_PRESSED = 13,
+	/*
+	 * EC has finished initializing the host interface.  The host can check
+	 * for this event following sending a EC_CMD_REBOOT_EC command to
+	 * determine when the EC is ready to accept subsequent commands.
+	 */
+	EC_HOST_EVENT_INTERFACE_READY = 14,
+	/* Keyboard recovery combo has been pressed */
+	EC_HOST_EVENT_KEYBOARD_RECOVERY = 15,
+
+	/* Shutdown due to thermal overload */
+	EC_HOST_EVENT_THERMAL_SHUTDOWN = 16,
+	/* Shutdown due to battery level too low */
+	EC_HOST_EVENT_BATTERY_SHUTDOWN = 17,
+
+	/* Suggest that the AP throttle itself */
+	EC_HOST_EVENT_THROTTLE_START = 18,
+	/* Suggest that the AP resume normal speed */
+	EC_HOST_EVENT_THROTTLE_STOP = 19,
+
+	/* Hang detect logic detected a hang and host event timeout expired */
+	EC_HOST_EVENT_HANG_DETECT = 20,
+	/* Hang detect logic detected a hang and warm rebooted the AP */
+	EC_HOST_EVENT_HANG_REBOOT = 21,
+
+	/* PD MCU triggering host event */
+	EC_HOST_EVENT_PD_MCU = 22,
+
+	/* Battery Status flags have changed */
+	EC_HOST_EVENT_BATTERY_STATUS = 23,
+
+	/* EC encountered a panic, triggering a reset */
+	EC_HOST_EVENT_PANIC = 24,
+
+	/* Keyboard fastboot combo has been pressed */
+	EC_HOST_EVENT_KEYBOARD_FASTBOOT = 25,
+
+	/* EC RTC event occurred */
+	EC_HOST_EVENT_RTC = 26,
+
+	/* Emulate MKBP event */
+	EC_HOST_EVENT_MKBP = 27,
+
+	/* EC desires to change state of host-controlled USB mux */
+	EC_HOST_EVENT_USB_MUX = 28,
+
+	/* TABLET/LAPTOP mode event*/
+	EC_HOST_EVENT_MODE_CHANGE = 29,
+
+	/* Keyboard recovery combo with hardware reinitialization */
+	EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30,
+
+	/*
+	 * Reserve this last bit to indicate that at least one bit in a
+	 * secondary host event word is set.  See crbug.com/633646.
+	 */
+	EC_HOST_EVENT_EXTENDED = 31,
+
+	/*
+	 * The high bit of the event mask is not used as a host event code.  If
+	 * it reads back as set, then the entire event mask should be
+	 * considered invalid by the host.  This can happen when reading the
+	 * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is
+	 * not initialized on the EC, or improperly configured on the host.
+	 */
+	EC_HOST_EVENT_INVALID = 32
+};
+/* Host event mask */
+#define EC_HOST_EVENT_MASK(event_code) (1ULL << ((event_code) - 1))
+
+/* Arguments at EC_LPC_ADDR_HOST_ARGS */
+struct __ec_align4 ec_lpc_host_args {
+	uint8_t flags;
+	uint8_t command_version;
+	uint8_t data_size;
+	/*
+	 * Checksum; sum of command + flags + command_version + data_size +
+	 * all params/response data bytes.
+	 */
+	uint8_t checksum;
+};
+
+/* Flags for ec_lpc_host_args.flags */
+/*
+ * Args are from host.  Data area at EC_LPC_ADDR_HOST_PARAM contains command
+ * params.
+ *
+ * If EC gets a command and this flag is not set, this is an old-style command.
+ * Command version is 0 and params from host are at EC_LPC_ADDR_OLD_PARAM with
+ * unknown length.  EC must respond with an old-style response (that is,
+ * without setting EC_HOST_ARGS_FLAG_TO_HOST).
+ */
+#define EC_HOST_ARGS_FLAG_FROM_HOST 0x01
+/*
+ * Args are from EC.  Data area at EC_LPC_ADDR_HOST_PARAM contains response.
+ *
+ * If EC responds to a command and this flag is not set, this is an old-style
+ * response.  Command version is 0 and response data from EC is at
+ * EC_LPC_ADDR_OLD_PARAM with unknown length.
+ */
+#define EC_HOST_ARGS_FLAG_TO_HOST   0x02
+
+/*****************************************************************************/
+/*
+ * Byte codes returned by EC over SPI interface.
+ *
+ * These can be used by the AP to debug the EC interface, and to determine
+ * when the EC is not in a state where it will ever get around to responding
+ * to the AP.
+ *
+ * Example of sequence of bytes read from EC for a current good transfer:
+ *   1. -                  - AP asserts chip select (CS#)
+ *   2. EC_SPI_OLD_READY   - AP sends first byte(s) of request
+ *   3. -                  - EC starts handling CS# interrupt
+ *   4. EC_SPI_RECEIVING   - AP sends remaining byte(s) of request
+ *   5. EC_SPI_PROCESSING  - EC starts processing request; AP is clocking in
+ *                           bytes looking for EC_SPI_FRAME_START
+ *   6. -                  - EC finishes processing and sets up response
+ *   7. EC_SPI_FRAME_START - AP reads frame byte
+ *   8. (response packet)  - AP reads response packet
+ *   9. EC_SPI_PAST_END    - Any additional bytes read by AP
+ *   10 -                  - AP deasserts chip select
+ *   11 -                  - EC processes CS# interrupt and sets up DMA for
+ *                           next request
+ *
+ * If the AP is waiting for EC_SPI_FRAME_START and sees any value other than
+ * the following byte values:
+ *   EC_SPI_OLD_READY
+ *   EC_SPI_RX_READY
+ *   EC_SPI_RECEIVING
+ *   EC_SPI_PROCESSING
+ *
+ * Then the EC found an error in the request, or was not ready for the request
+ * and lost data.  The AP should give up waiting for EC_SPI_FRAME_START,
+ * because the EC is unable to tell when the AP is done sending its request.
+ */
+
+/*
+ * Framing byte which precedes a response packet from the EC.  After sending a
+ * request, the AP will clock in bytes until it sees the framing byte, then
+ * clock in the response packet.
+ */
+#define EC_SPI_FRAME_START    0xec
+
+/*
+ * Padding bytes which are clocked out after the end of a response packet.
+ */
+#define EC_SPI_PAST_END       0xed
+
+/*
+ * EC is ready to receive, and has ignored the byte sent by the AP.  EC expects
+ * that the AP will send a valid packet header (starting with
+ * EC_COMMAND_PROTOCOL_3) in the next 32 bytes.
+ */
+#define EC_SPI_RX_READY       0xf8
+
+/*
+ * EC has started receiving the request from the AP, but hasn't started
+ * processing it yet.
+ */
+#define EC_SPI_RECEIVING      0xf9
+
+/* EC has received the entire request from the AP and is processing it. */
+#define EC_SPI_PROCESSING     0xfa
+
+/*
+ * EC received bad data from the AP, such as a packet header with an invalid
+ * length.  EC will ignore all data until chip select deasserts.
+ */
+#define EC_SPI_RX_BAD_DATA    0xfb
+
+/*
+ * EC received data from the AP before it was ready.  That is, the AP asserted
+ * chip select and started clocking data before the EC was ready to receive it.
+ * EC will ignore all data until chip select deasserts.
+ */
+#define EC_SPI_NOT_READY      0xfc
+
+/*
+ * EC was ready to receive a request from the AP.  EC has treated the byte sent
+ * by the AP as part of a request packet, or (for old-style ECs) is processing
+ * a fully received packet but is not ready to respond yet.
+ */
+#define EC_SPI_OLD_READY      0xfd
+
+/*****************************************************************************/
+
+/*
+ * Protocol version 2 for I2C and SPI send a request this way:
+ *
+ *	0	EC_CMD_VERSION0 + (command version)
+ *	1	Command number
+ *	2	Length of params = N
+ *	3..N+2	Params, if any
+ *	N+3	8-bit checksum of bytes 0..N+2
+ *
+ * The corresponding response is:
+ *
+ *	0	Result code (EC_RES_*)
+ *	1	Length of params = M
+ *	2..M+1	Params, if any
+ *	M+2	8-bit checksum of bytes 0..M+1
+ */
+#define EC_PROTO2_REQUEST_HEADER_BYTES 3
+#define EC_PROTO2_REQUEST_TRAILER_BYTES 1
+#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES +	\
+				    EC_PROTO2_REQUEST_TRAILER_BYTES)
+
+#define EC_PROTO2_RESPONSE_HEADER_BYTES 2
+#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
+#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES +	\
+				     EC_PROTO2_RESPONSE_TRAILER_BYTES)
+
+/* Parameter length was limited by the LPC interface */
+#define EC_PROTO2_MAX_PARAM_SIZE 0xfc
+
+/* Maximum request and response packet sizes for protocol version 2 */
+#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD +	\
+				    EC_PROTO2_MAX_PARAM_SIZE)
+#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD +	\
+				     EC_PROTO2_MAX_PARAM_SIZE)
+
+/*****************************************************************************/
+
+/*
+ * Value written to legacy command port / prefix byte to indicate protocol
+ * 3+ structs are being used.  Usage is bus-dependent.
+ */
+#define EC_COMMAND_PROTOCOL_3 0xda
+
+#define EC_HOST_REQUEST_VERSION 3
+
+/* Version 3 request from host */
+struct __ec_align4 ec_host_request {
+	/* Structure version (=3)
+	 *
+	 * EC will return EC_RES_INVALID_HEADER if it receives a header with a
+	 * version it doesn't know how to parse.
+	 */
+	uint8_t struct_version;
+
+	/*
+	 * Checksum of request and data; sum of all bytes including checksum
+	 * should total to 0.
+	 */
+	uint8_t checksum;
+
+	/* Command code */
+	uint16_t command;
+
+	/* Command version */
+	uint8_t command_version;
+
+	/* Unused byte in current protocol version; set to 0 */
+	uint8_t reserved;
+
+	/* Length of data which follows this header */
+	uint16_t data_len;
+};
+
+#define EC_HOST_RESPONSE_VERSION 3
+
+/* Version 3 response from EC */
+struct __ec_align4 ec_host_response {
+	/* Structure version (=3) */
+	uint8_t struct_version;
+
+	/*
+	 * Checksum of response and data; sum of all bytes including checksum
+	 * should total to 0.
+	 */
+	uint8_t checksum;
+
+	/* Result code (EC_RES_*) */
+	uint16_t result;
+
+	/* Length of data which follows this header */
+	uint16_t data_len;
+
+	/* Unused bytes in current protocol version; set to 0 */
+	uint16_t reserved;
+};
+
+/*****************************************************************************/
+/*
+ * Notes on commands:
+ *
+ * Each command is an 16-bit command value.  Commands which take params or
+ * return response data specify structures for that data.  If no structure is
+ * specified, the command does not input or output data, respectively.
+ * Parameter/response length is implicit in the structs.  Some underlying
+ * communication protocols (I2C, SPI) may add length or checksum headers, but
+ * those are implementation-dependent and not defined here.
+ *
+ * All commands MUST be #defined to be 4-digit UPPER CASE hex values
+ * (e.g., 0x00AB, not 0xab) for CONFIG_HOSTCMD_SECTION_SORTED to work.
+ */
+
+/*****************************************************************************/
+/* General / test commands */
+
+/*
+ * Get protocol version, used to deal with non-backward compatible protocol
+ * changes.
+ */
+#define EC_CMD_PROTO_VERSION 0x0000
+
+struct __ec_align4 ec_response_proto_version {
+	uint32_t version;
+};
+
+/*
+ * Hello.  This is a simple command to test the EC is responsive to
+ * commands.
+ */
+#define EC_CMD_HELLO 0x0001
+
+struct __ec_align4 ec_params_hello {
+	uint32_t in_data;  /* Pass anything here */
+};
+
+struct __ec_align4 ec_response_hello {
+	uint32_t out_data;  /* Output will be in_data + 0x01020304 */
+};
+
+/* Get version number */
+#define EC_CMD_GET_VERSION 0x0002
+
+enum ec_current_image {
+	EC_IMAGE_UNKNOWN = 0,
+	EC_IMAGE_RO,
+	EC_IMAGE_RW
+};
+
+struct __ec_align4 ec_response_get_version {
+	/* Null-terminated version strings for RO, RW */
+	char version_string_ro[32];
+	char version_string_rw[32];
+	char reserved[32];       /* Was previously RW-B string */
+	uint32_t current_image;  /* One of ec_current_image */
+};
+
+/* Read test */
+#define EC_CMD_READ_TEST 0x0003
+
+struct __ec_align4 ec_params_read_test {
+	uint32_t offset;   /* Starting value for read buffer */
+	uint32_t size;     /* Size to read in bytes */
+};
+
+struct __ec_align4 ec_response_read_test {
+	uint32_t data[32];
+};
+
+/*
+ * Get build information
+ *
+ * Response is null-terminated string.
+ */
+#define EC_CMD_GET_BUILD_INFO 0x0004
+
+/* Get chip info */
+#define EC_CMD_GET_CHIP_INFO 0x0005
+
+struct __ec_align4 ec_response_get_chip_info {
+	/* Null-terminated strings */
+	char vendor[32];
+	char name[32];
+	char revision[32];  /* Mask version */
+};
+
+/* Get board HW version */
+#define EC_CMD_GET_BOARD_VERSION 0x0006
+
+struct __ec_align2 ec_response_board_version {
+	uint16_t board_version;  /* A monotonously incrementing number. */
+};
+
+/*
+ * Read memory-mapped data.
+ *
+ * This is an alternate interface to memory-mapped data for bus protocols
+ * which don't support direct-mapped memory - I2C, SPI, etc.
+ *
+ * Response is params.size bytes of data.
+ */
+#define EC_CMD_READ_MEMMAP 0x0007
+
+struct __ec_align1 ec_params_read_memmap {
+	uint8_t offset;   /* Offset in memmap (EC_MEMMAP_*) */
+	uint8_t size;     /* Size to read in bytes */
+};
+
+/* Read versions supported for a command */
+#define EC_CMD_GET_CMD_VERSIONS 0x0008
+
+struct __ec_align1 ec_params_get_cmd_versions {
+	uint8_t cmd;      /* Command to check */
+};
+
+struct __ec_align2 ec_params_get_cmd_versions_v1 {
+	uint16_t cmd;     /* Command to check */
+};
+
+struct __ec_align4 ec_response_get_cmd_versions {
+	/*
+	 * Mask of supported versions; use EC_VER_MASK() to compare with a
+	 * desired version.
+	 */
+	uint32_t version_mask;
+};
+
+/*
+ * Check EC communications status (busy). This is needed on i2c/spi but not
+ * on lpc since it has its own out-of-band busy indicator.
+ *
+ * lpc must read the status from the command register. Attempting this on
+ * lpc will overwrite the args/parameter space and corrupt its data.
+ */
+#define EC_CMD_GET_COMMS_STATUS		0x0009
+
+/* Avoid using ec_status which is for return values */
+enum ec_comms_status {
+	EC_COMMS_STATUS_PROCESSING	= 1 << 0,	/* Processing cmd */
+};
+
+struct __ec_align4 ec_response_get_comms_status {
+	uint32_t flags;		/* Mask of enum ec_comms_status */
+};
+
+/* Fake a variety of responses, purely for testing purposes. */
+#define EC_CMD_TEST_PROTOCOL		0x000A
+
+/* Tell the EC what to send back to us. */
+struct __ec_align4 ec_params_test_protocol {
+	uint32_t ec_result;
+	uint32_t ret_len;
+	uint8_t buf[32];
+};
+
+/* Here it comes... */
+struct __ec_align4 ec_response_test_protocol {
+	uint8_t buf[32];
+};
+
+/* Get protocol information */
+#define EC_CMD_GET_PROTOCOL_INFO	0x000B
+
+/* Flags for ec_response_get_protocol_info.flags */
+/* EC_RES_IN_PROGRESS may be returned if a command is slow */
+#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0)
+
+struct __ec_align4 ec_response_get_protocol_info {
+	/* Fields which exist if at least protocol version 3 supported */
+
+	/* Bitmask of protocol versions supported (1 << n means version n)*/
+	uint32_t protocol_versions;
+
+	/* Maximum request packet size, in bytes */
+	uint16_t max_request_packet_size;
+
+	/* Maximum response packet size, in bytes */
+	uint16_t max_response_packet_size;
+
+	/* Flags; see EC_PROTOCOL_INFO_* */
+	uint32_t flags;
+};
+
+
+/*****************************************************************************/
+/* Get/Set miscellaneous values */
+
+/* The upper byte of .flags tells what to do (nothing means "get") */
+#define EC_GSV_SET        0x80000000
+
+/* The lower three bytes of .flags identifies the parameter, if that has
+   meaning for an individual command. */
+#define EC_GSV_PARAM_MASK 0x00ffffff
+
+struct __ec_align4 ec_params_get_set_value {
+	uint32_t flags;
+	uint32_t value;
+};
+
+struct __ec_align4 ec_response_get_set_value {
+	uint32_t flags;
+	uint32_t value;
+};
+
+/* More than one command can use these structs to get/set parameters. */
+#define EC_CMD_GSV_PAUSE_IN_S5	0x000C
+
+/*****************************************************************************/
+/* List the features supported by the firmware */
+#define EC_CMD_GET_FEATURES  0x000D
+
+/* Supported features */
+enum ec_feature_code {
+	/*
+	 * This image contains a limited set of features. Another image
+	 * in RW partition may support more features.
+	 */
+	EC_FEATURE_LIMITED = 0,
+	/*
+	 * Commands for probing/reading/writing/erasing the flash in the
+	 * EC are present.
+	 */
+	EC_FEATURE_FLASH = 1,
+	/*
+	 * Can control the fan speed directly.
+	 */
+	EC_FEATURE_PWM_FAN = 2,
+	/*
+	 * Can control the intensity of the keyboard backlight.
+	 */
+	EC_FEATURE_PWM_KEYB = 3,
+	/*
+	 * Support Google lightbar, introduced on Pixel.
+	 */
+	EC_FEATURE_LIGHTBAR = 4,
+	/* Control of LEDs  */
+	EC_FEATURE_LED = 5,
+	/* Exposes an interface to control gyro and sensors.
+	 * The host goes through the EC to access these sensors.
+	 * In addition, the EC may provide composite sensors, like lid angle.
+	 */
+	EC_FEATURE_MOTION_SENSE = 6,
+	/* The keyboard is controlled by the EC */
+	EC_FEATURE_KEYB = 7,
+	/* The AP can use part of the EC flash as persistent storage. */
+	EC_FEATURE_PSTORE = 8,
+	/* The EC monitors BIOS port 80h, and can return POST codes. */
+	EC_FEATURE_PORT80 = 9,
+	/*
+	 * Thermal management: include TMP specific commands.
+	 * Higher level than direct fan control.
+	 */
+	EC_FEATURE_THERMAL = 10,
+	/* Can switch the screen backlight on/off */
+	EC_FEATURE_BKLIGHT_SWITCH = 11,
+	/* Can switch the wifi module on/off */
+	EC_FEATURE_WIFI_SWITCH = 12,
+	/* Monitor host events, through for example SMI or SCI */
+	EC_FEATURE_HOST_EVENTS = 13,
+	/* The EC exposes GPIO commands to control/monitor connected devices. */
+	EC_FEATURE_GPIO = 14,
+	/* The EC can send i2c messages to downstream devices. */
+	EC_FEATURE_I2C = 15,
+	/* Command to control charger are included */
+	EC_FEATURE_CHARGER = 16,
+	/* Simple battery support. */
+	EC_FEATURE_BATTERY = 17,
+	/*
+	 * Support Smart battery protocol
+	 * (Common Smart Battery System Interface Specification)
+	 */
+	EC_FEATURE_SMART_BATTERY = 18,
+	/* EC can detect when the host hangs. */
+	EC_FEATURE_HANG_DETECT = 19,
+	/* Report power information, for pit only */
+	EC_FEATURE_PMU = 20,
+	/* Another Cros EC device is present downstream of this one */
+	EC_FEATURE_SUB_MCU = 21,
+	/* Support USB Power delivery (PD) commands */
+	EC_FEATURE_USB_PD = 22,
+	/* Control USB multiplexer, for audio through USB port for instance. */
+	EC_FEATURE_USB_MUX = 23,
+	/* Motion Sensor code has an internal software FIFO */
+	EC_FEATURE_MOTION_SENSE_FIFO = 24,
+	/* Support temporary secure vstore */
+	EC_FEATURE_VSTORE = 25,
+	/* EC decides on USB-C SS mux state, muxes configured by host */
+	EC_FEATURE_USBC_SS_MUX_VIRTUAL = 26,
+	/* EC has RTC feature that can be controlled by host commands */
+	EC_FEATURE_RTC = 27,
+	/* The MCU exposes a Fingerprint sensor */
+	EC_FEATURE_FINGERPRINT = 28,
+	/* The MCU exposes a Touchpad */
+	EC_FEATURE_TOUCHPAD = 29,
+	/* The MCU has RWSIG task enabled */
+	EC_FEATURE_RWSIG = 30,
+	/* EC has device events support */
+	EC_FEATURE_DEVICE_EVENT = 31,
+	/* EC supports the unified wake masks for LPC/eSPI systems */
+	EC_FEATURE_UNIFIED_WAKE_MASKS = 32,
+};
+
+#define EC_FEATURE_MASK_0(event_code) (1UL << (event_code % 32))
+#define EC_FEATURE_MASK_1(event_code) (1UL << (event_code - 32))
+struct __ec_align4 ec_response_get_features {
+	uint32_t flags[2];
+};
+
+/*****************************************************************************/
+/* Get the board's SKU ID from EC */
+#define EC_CMD_GET_SKU_ID 0x000E
+
+/* Set SKU ID from AP */
+#define EC_CMD_SET_SKU_ID 0x000F
+
+struct __ec_align4 ec_sku_id_info {
+	uint32_t sku_id;
+};
+
+/*****************************************************************************/
+/* Flash commands */
+
+/* Get flash info */
+#define EC_CMD_FLASH_INFO 0x0010
+#define EC_VER_FLASH_INFO 2
+
+/* Version 0 returns these fields */
+struct __ec_align4 ec_response_flash_info {
+	/* Usable flash size, in bytes */
+	uint32_t flash_size;
+	/*
+	 * Write block size.  Write offset and size must be a multiple
+	 * of this.
+	 */
+	uint32_t write_block_size;
+	/*
+	 * Erase block size.  Erase offset and size must be a multiple
+	 * of this.
+	 */
+	uint32_t erase_block_size;
+	/*
+	 * Protection block size.  Protection offset and size must be a
+	 * multiple of this.
+	 */
+	uint32_t protect_block_size;
+};
+
+/* Flags for version 1+ flash info command */
+/* EC flash erases bits to 0 instead of 1 */
+#define EC_FLASH_INFO_ERASE_TO_0 (1 << 0)
+
+/* Flash must be selected for read/write/erase operations to succeed.  This may
+ * be necessary on a chip where write/erase can be corrupted by other board
+ * activity, or where the chip needs to enable some sort of programming voltage,
+ * or where the read/write/erase operations require cleanly suspending other
+ * chip functionality. */
+#define EC_FLASH_INFO_SELECT_REQUIRED (1 << 1)
+
+/*
+ * Version 1 returns the same initial fields as version 0, with additional
+ * fields following.
+ *
+ * gcc anonymous structs don't seem to get along with the __packed directive;
+ * if they did we'd define the version 0 structure as a sub-structure of this
+ * one.
+ *
+ * Version 2 supports flash banks of different sizes:
+ * The caller specified the number of banks it has preallocated
+ * (num_banks_desc)
+ * The EC returns the number of banks describing the flash memory.
+ * It adds banks descriptions up to num_banks_desc.
+ */
+struct __ec_align4 ec_response_flash_info_1 {
+	/* Version 0 fields; see above for description */
+	uint32_t flash_size;
+	uint32_t write_block_size;
+	uint32_t erase_block_size;
+	uint32_t protect_block_size;
+
+	/* Version 1 adds these fields: */
+	/*
+	 * Ideal write size in bytes.  Writes will be fastest if size is
+	 * exactly this and offset is a multiple of this.  For example, an EC
+	 * may have a write buffer which can do half-page operations if data is
+	 * aligned, and a slower word-at-a-time write mode.
+	 */
+	uint32_t write_ideal_size;
+
+	/* Flags; see EC_FLASH_INFO_* */
+	uint32_t flags;
+};
+
+struct __ec_align4 ec_params_flash_info_2 {
+	/* Number of banks to describe */
+	uint16_t num_banks_desc;
+	/* Reserved; set 0; ignore on read */
+	uint8_t reserved[2];
+};
+
+struct ec_flash_bank {
+	/* Number of sector is in this bank. */
+	uint16_t count;
+	/* Size in power of 2 of each sector (8 --> 256 bytes) */
+	uint8_t size_exp;
+	/* Minimal write size for the sectors in this bank */
+	uint8_t write_size_exp;
+	/* Erase size for the sectors in this bank */
+	uint8_t erase_size_exp;
+	/* Size for write protection, usually identical to erase size. */
+	uint8_t protect_size_exp;
+	/* Reserved; set 0; ignore on read */
+	uint8_t reserved[2];
+};
+
+struct __ec_align4 ec_response_flash_info_2 {
+	/* Total flash in the EC. */
+	uint32_t flash_size;
+	/* Flags; see EC_FLASH_INFO_* */
+	uint32_t flags;
+	/* Maximum size to use to send data to write to the EC. */
+	uint32_t write_ideal_size;
+	/* Number of banks present in the EC. */
+	uint16_t num_banks_total;
+	/* Number of banks described in banks array. */
+	uint16_t num_banks_desc;
+	struct ec_flash_bank banks[0];
+};
+
+/*
+ * Read flash
+ *
+ * Response is params.size bytes of data.
+ */
+#define EC_CMD_FLASH_READ 0x0011
+
+struct __ec_align4 ec_params_flash_read {
+	uint32_t offset;   /* Byte offset to read */
+	uint32_t size;     /* Size to read in bytes */
+};
+
+/* Write flash */
+#define EC_CMD_FLASH_WRITE 0x0012
+#define EC_VER_FLASH_WRITE 1
+
+/* Version 0 of the flash command supported only 64 bytes of data */
+#define EC_FLASH_WRITE_VER0_SIZE 64
+
+struct __ec_align4 ec_params_flash_write {
+	uint32_t offset;   /* Byte offset to write */
+	uint32_t size;     /* Size to write in bytes */
+	/* Followed by data to write */
+};
+
+/* Erase flash */
+#define EC_CMD_FLASH_ERASE 0x0013
+
+/* v0 */
+struct __ec_align4 ec_params_flash_erase {
+	uint32_t offset;   /* Byte offset to erase */
+	uint32_t size;     /* Size to erase in bytes */
+};
+
+
+#define EC_VER_FLASH_WRITE 1
+/* v1 add async erase:
+ * subcommands can returns:
+ * EC_RES_SUCCESS : erased (see ERASE_SECTOR_ASYNC case below).
+ * EC_RES_INVALID_PARAM : offset/size are not aligned on a erase boundary.
+ * EC_RES_ERROR : other errors.
+ * EC_RES_BUSY : an existing erase operation is in progress.
+ * EC_RES_ACCESS_DENIED: Trying to erase running image.
+ *
+ * When ERASE_SECTOR_ASYNC returns EC_RES_SUCCESS, the operation is just
+ * properly queued. The user must call ERASE_GET_RESULT subcommand to get
+ * the proper result.
+ * When ERASE_GET_RESULT returns EC_RES_BUSY, the caller must wait and send
+ * ERASE_GET_RESULT again to get the result of ERASE_SECTOR_ASYNC.
+ * ERASE_GET_RESULT command may timeout on EC where flash access is not
+ * permitted while erasing. (For instance, STM32F4).
+ */
+enum ec_flash_erase_cmd {
+	FLASH_ERASE_SECTOR,     /* Erase and wait for result */
+	FLASH_ERASE_SECTOR_ASYNC,  /* Erase and return immediately. */
+	FLASH_ERASE_GET_RESULT,  /* Ask for last erase result */
+};
+
+struct __ec_align4 ec_params_flash_erase_v1 {
+	/* One of ec_flash_erase_cmd. */
+	uint8_t  cmd;
+	/* Pad byte; currently always contains 0 */
+	uint8_t  reserved;
+	/* No flags defined yet; set to 0 */
+	uint16_t flag;
+	/* Same as v0 parameters. */
+	struct ec_params_flash_erase params;
+};
+
+/*
+ * Get/set flash protection.
+ *
+ * If mask!=0, sets/clear the requested bits of flags.  Depending on the
+ * firmware write protect GPIO, not all flags will take effect immediately;
+ * some flags require a subsequent hard reset to take effect.  Check the
+ * returned flags bits to see what actually happened.
+ *
+ * If mask=0, simply returns the current flags state.
+ */
+#define EC_CMD_FLASH_PROTECT 0x0015
+#define EC_VER_FLASH_PROTECT 1  /* Command version 1 */
+
+/* Flags for flash protection */
+/* RO flash code protected when the EC boots */
+#define EC_FLASH_PROTECT_RO_AT_BOOT         (1 << 0)
+/*
+ * RO flash code protected now.  If this bit is set, at-boot status cannot
+ * be changed.
+ */
+#define EC_FLASH_PROTECT_RO_NOW             (1 << 1)
+/* Entire flash code protected now, until reboot. */
+#define EC_FLASH_PROTECT_ALL_NOW            (1 << 2)
+/* Flash write protect GPIO is asserted now */
+#define EC_FLASH_PROTECT_GPIO_ASSERTED      (1 << 3)
+/* Error - at least one bank of flash is stuck locked, and cannot be unlocked */
+#define EC_FLASH_PROTECT_ERROR_STUCK        (1 << 4)
+/*
+ * Error - flash protection is in inconsistent state.  At least one bank of
+ * flash which should be protected is not protected.  Usually fixed by
+ * re-requesting the desired flags, or by a hard reset if that fails.
+ */
+#define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5)
+/* Entire flash code protected when the EC boots */
+#define EC_FLASH_PROTECT_ALL_AT_BOOT        (1 << 6)
+/* RW flash code protected when the EC boots */
+#define EC_FLASH_PROTECT_RW_AT_BOOT         (1 << 7)
+/* RW flash code protected now. */
+#define EC_FLASH_PROTECT_RW_NOW             (1 << 8)
+/* Rollback information flash region protected when the EC boots */
+#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT   (1 << 9)
+/* Rollback information flash region protected now */
+#define EC_FLASH_PROTECT_ROLLBACK_NOW       (1 << 10)
+
+struct __ec_align4 ec_params_flash_protect {
+	uint32_t mask;   /* Bits in flags to apply */
+	uint32_t flags;  /* New flags to apply */
+};
+
+struct __ec_align4 ec_response_flash_protect {
+	/* Current value of flash protect flags */
+	uint32_t flags;
+	/*
+	 * Flags which are valid on this platform.  This allows the caller
+	 * to distinguish between flags which aren't set vs. flags which can't
+	 * be set on this platform.
+	 */
+	uint32_t valid_flags;
+	/* Flags which can be changed given the current protection state */
+	uint32_t writable_flags;
+};
+
+/*
+ * Note: commands 0x14 - 0x19 version 0 were old commands to get/set flash
+ * write protect.  These commands may be reused with version > 0.
+ */
+
+/* Get the region offset/size */
+#define EC_CMD_FLASH_REGION_INFO 0x0016
+#define EC_VER_FLASH_REGION_INFO 1
+
+enum ec_flash_region {
+	/* Region which holds read-only EC image */
+	EC_FLASH_REGION_RO = 0,
+	/* Region which holds active rewritable EC image */
+	EC_FLASH_REGION_ACTIVE,
+	/*
+	 * Region which should be write-protected in the factory (a superset of
+	 * EC_FLASH_REGION_RO)
+	 */
+	EC_FLASH_REGION_WP_RO,
+	/* Region which holds updatable image */
+	EC_FLASH_REGION_UPDATE,
+	/* Number of regions */
+	EC_FLASH_REGION_COUNT,
+};
+
+struct __ec_align4 ec_params_flash_region_info {
+	uint32_t region;  /* enum ec_flash_region */
+};
+
+struct __ec_align4 ec_response_flash_region_info {
+	uint32_t offset;
+	uint32_t size;
+};
+
+/* Read/write VbNvContext */
+#define EC_CMD_VBNV_CONTEXT 0x0017
+#define EC_VER_VBNV_CONTEXT 1
+#define EC_VBNV_BLOCK_SIZE 16
+#define EC_VBNV_BLOCK_SIZE_V2 64
+
+enum ec_vbnvcontext_op {
+	EC_VBNV_CONTEXT_OP_READ,
+	EC_VBNV_CONTEXT_OP_WRITE,
+};
+
+struct __ec_align4 ec_params_vbnvcontext {
+	uint32_t op;
+	uint8_t block[EC_VBNV_BLOCK_SIZE_V2];
+};
+
+struct __ec_align4 ec_response_vbnvcontext {
+	uint8_t block[EC_VBNV_BLOCK_SIZE_V2];
+};
+
+
+/* Get SPI flash information */
+#define EC_CMD_FLASH_SPI_INFO 0x0018
+
+struct __ec_align1 ec_response_flash_spi_info {
+	/* JEDEC info from command 0x9F (manufacturer, memory type, size) */
+	uint8_t jedec[3];
+
+	/* Pad byte; currently always contains 0 */
+	uint8_t reserved0;
+
+	/* Manufacturer / device ID from command 0x90 */
+	uint8_t mfr_dev_id[2];
+
+	/* Status registers from command 0x05 and 0x35 */
+	uint8_t sr1, sr2;
+};
+
+
+/* Select flash during flash operations */
+#define EC_CMD_FLASH_SELECT 0x0019
+
+struct __ec_align4 ec_params_flash_select {
+	/* 1 to select flash, 0 to deselect flash */
+	uint8_t select;
+};
+
+/*****************************************************************************/
+/* PWM commands */
+
+/* Get fan target RPM */
+#define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x0020
+
+struct __ec_align4 ec_response_pwm_get_fan_rpm {
+	uint32_t rpm;
+};
+
+/* Set target fan RPM */
+#define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x0021
+
+/* Version 0 of input params */
+struct __ec_align4 ec_params_pwm_set_fan_target_rpm_v0 {
+	uint32_t rpm;
+};
+
+/* Version 1 of input params */
+struct __ec_align_size1 ec_params_pwm_set_fan_target_rpm_v1 {
+	uint32_t rpm;
+	uint8_t fan_idx;
+};
+
+/* Get keyboard backlight */
+/* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */
+#define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x0022
+
+struct __ec_align1 ec_response_pwm_get_keyboard_backlight {
+	uint8_t percent;
+	uint8_t enabled;
+};
+
+/* Set keyboard backlight */
+/* OBSOLETE - Use EC_CMD_PWM_SET_DUTY */
+#define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x0023
+
+struct __ec_align1 ec_params_pwm_set_keyboard_backlight {
+	uint8_t percent;
+};
+
+/* Set target fan PWM duty cycle */
+#define EC_CMD_PWM_SET_FAN_DUTY 0x0024
+
+/* Version 0 of input params */
+struct __ec_align4 ec_params_pwm_set_fan_duty_v0 {
+	uint32_t percent;
+};
+
+/* Version 1 of input params */
+struct __ec_align_size1 ec_params_pwm_set_fan_duty_v1 {
+	uint32_t percent;
+	uint8_t fan_idx;
+};
+
+#define EC_CMD_PWM_SET_DUTY 0x0025
+/* 16 bit duty cycle, 0xffff = 100% */
+#define EC_PWM_MAX_DUTY 0xffff
+
+enum ec_pwm_type {
+	/* All types, indexed by board-specific enum pwm_channel */
+	EC_PWM_TYPE_GENERIC = 0,
+	/* Keyboard backlight */
+	EC_PWM_TYPE_KB_LIGHT,
+	/* Display backlight */
+	EC_PWM_TYPE_DISPLAY_LIGHT,
+	EC_PWM_TYPE_COUNT,
+};
+
+struct __ec_align4 ec_params_pwm_set_duty {
+	uint16_t duty;     /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
+	uint8_t pwm_type;  /* ec_pwm_type */
+	uint8_t index;     /* Type-specific index, or 0 if unique */
+};
+
+#define EC_CMD_PWM_GET_DUTY 0x0026
+
+struct __ec_align1 ec_params_pwm_get_duty {
+	uint8_t pwm_type;  /* ec_pwm_type */
+	uint8_t index;     /* Type-specific index, or 0 if unique */
+};
+
+struct __ec_align2 ec_response_pwm_get_duty {
+	uint16_t duty;     /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
+};
+
+/*****************************************************************************/
+/*
+ * Lightbar commands. This looks worse than it is. Since we only use one HOST
+ * command to say "talk to the lightbar", we put the "and tell it to do X" part
+ * into a subcommand. We'll make separate structs for subcommands with
+ * different input args, so that we know how much to expect.
+ */
+#define EC_CMD_LIGHTBAR_CMD 0x0028
+
+struct __ec_todo_unpacked rgb_s {
+	uint8_t r, g, b;
+};
+
+#define LB_BATTERY_LEVELS 4
+/* List of tweakable parameters. NOTE: It's __packed so it can be sent in a
+ * host command, but the alignment is the same regardless. Keep it that way.
+ */
+struct __ec_todo_packed lightbar_params_v0 {
+	/* Timing */
+	int32_t google_ramp_up;
+	int32_t google_ramp_down;
+	int32_t s3s0_ramp_up;
+	int32_t s0_tick_delay[2];		/* AC=0/1 */
+	int32_t s0a_tick_delay[2];		/* AC=0/1 */
+	int32_t s0s3_ramp_down;
+	int32_t s3_sleep_for;
+	int32_t s3_ramp_up;
+	int32_t s3_ramp_down;
+
+	/* Oscillation */
+	uint8_t new_s0;
+	uint8_t osc_min[2];			/* AC=0/1 */
+	uint8_t osc_max[2];			/* AC=0/1 */
+	uint8_t w_ofs[2];			/* AC=0/1 */
+
+	/* Brightness limits based on the backlight and AC. */
+	uint8_t bright_bl_off_fixed[2];		/* AC=0/1 */
+	uint8_t bright_bl_on_min[2];		/* AC=0/1 */
+	uint8_t bright_bl_on_max[2];		/* AC=0/1 */
+
+	/* Battery level thresholds */
+	uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
+
+	/* Map [AC][battery_level] to color index */
+	uint8_t s0_idx[2][LB_BATTERY_LEVELS];	/* AP is running */
+	uint8_t s3_idx[2][LB_BATTERY_LEVELS];	/* AP is sleeping */
+
+	/* Color palette */
+	struct rgb_s color[8];			/* 0-3 are Google colors */
+};
+
+struct __ec_todo_packed lightbar_params_v1 {
+	/* Timing */
+	int32_t google_ramp_up;
+	int32_t google_ramp_down;
+	int32_t s3s0_ramp_up;
+	int32_t s0_tick_delay[2];		/* AC=0/1 */
+	int32_t s0a_tick_delay[2];		/* AC=0/1 */
+	int32_t s0s3_ramp_down;
+	int32_t s3_sleep_for;
+	int32_t s3_ramp_up;
+	int32_t s3_ramp_down;
+	int32_t s5_ramp_up;
+	int32_t s5_ramp_down;
+	int32_t tap_tick_delay;
+	int32_t tap_gate_delay;
+	int32_t tap_display_time;
+
+	/* Tap-for-battery params */
+	uint8_t tap_pct_red;
+	uint8_t tap_pct_green;
+	uint8_t tap_seg_min_on;
+	uint8_t tap_seg_max_on;
+	uint8_t tap_seg_osc;
+	uint8_t tap_idx[3];
+
+	/* Oscillation */
+	uint8_t osc_min[2];			/* AC=0/1 */
+	uint8_t osc_max[2];			/* AC=0/1 */
+	uint8_t w_ofs[2];			/* AC=0/1 */
+
+	/* Brightness limits based on the backlight and AC. */
+	uint8_t bright_bl_off_fixed[2];		/* AC=0/1 */
+	uint8_t bright_bl_on_min[2];		/* AC=0/1 */
+	uint8_t bright_bl_on_max[2];		/* AC=0/1 */
+
+	/* Battery level thresholds */
+	uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
+
+	/* Map [AC][battery_level] to color index */
+	uint8_t s0_idx[2][LB_BATTERY_LEVELS];	/* AP is running */
+	uint8_t s3_idx[2][LB_BATTERY_LEVELS];	/* AP is sleeping */
+
+	/* s5: single color pulse on inhibited power-up */
+	uint8_t s5_idx;
+
+	/* Color palette */
+	struct rgb_s color[8];			/* 0-3 are Google colors */
+};
+
+/* Lightbar command params v2
+ * crbug.com/467716
+ *
+ * lightbar_parms_v1 was too big for i2c, therefore in v2, we split them up by
+ * logical groups to make it more manageable ( < 120 bytes).
+ *
+ * NOTE: Each of these groups must be less than 120 bytes.
+ */
+
+struct __ec_todo_packed lightbar_params_v2_timing {
+	/* Timing */
+	int32_t google_ramp_up;
+	int32_t google_ramp_down;
+	int32_t s3s0_ramp_up;
+	int32_t s0_tick_delay[2];		/* AC=0/1 */
+	int32_t s0a_tick_delay[2];		/* AC=0/1 */
+	int32_t s0s3_ramp_down;
+	int32_t s3_sleep_for;
+	int32_t s3_ramp_up;
+	int32_t s3_ramp_down;
+	int32_t s5_ramp_up;
+	int32_t s5_ramp_down;
+	int32_t tap_tick_delay;
+	int32_t tap_gate_delay;
+	int32_t tap_display_time;
+};
+
+struct __ec_todo_packed lightbar_params_v2_tap {
+	/* Tap-for-battery params */
+	uint8_t tap_pct_red;
+	uint8_t tap_pct_green;
+	uint8_t tap_seg_min_on;
+	uint8_t tap_seg_max_on;
+	uint8_t tap_seg_osc;
+	uint8_t tap_idx[3];
+};
+
+struct __ec_todo_packed lightbar_params_v2_oscillation {
+	/* Oscillation */
+	uint8_t osc_min[2];			/* AC=0/1 */
+	uint8_t osc_max[2];			/* AC=0/1 */
+	uint8_t w_ofs[2];			/* AC=0/1 */
+};
+
+struct __ec_todo_packed lightbar_params_v2_brightness {
+	/* Brightness limits based on the backlight and AC. */
+	uint8_t bright_bl_off_fixed[2];		/* AC=0/1 */
+	uint8_t bright_bl_on_min[2];		/* AC=0/1 */
+	uint8_t bright_bl_on_max[2];		/* AC=0/1 */
+};
+
+struct __ec_todo_packed lightbar_params_v2_thresholds {
+	/* Battery level thresholds */
+	uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
+};
+
+struct __ec_todo_packed lightbar_params_v2_colors {
+	/* Map [AC][battery_level] to color index */
+	uint8_t s0_idx[2][LB_BATTERY_LEVELS];	/* AP is running */
+	uint8_t s3_idx[2][LB_BATTERY_LEVELS];	/* AP is sleeping */
+
+	/* s5: single color pulse on inhibited power-up */
+	uint8_t s5_idx;
+
+	/* Color palette */
+	struct rgb_s color[8];			/* 0-3 are Google colors */
+};
+
+/* Lightbyte program. */
+#define EC_LB_PROG_LEN 192
+struct __ec_todo_unpacked lightbar_program {
+	uint8_t size;
+	uint8_t data[EC_LB_PROG_LEN];
+};
+
+struct __ec_todo_packed ec_params_lightbar {
+	uint8_t cmd;		      /* Command (see enum lightbar_command) */
+	union {
+		struct __ec_todo_unpacked {
+			/* no args */
+		} dump, off, on, init, get_seq, get_params_v0, get_params_v1,
+			version, get_brightness, get_demo, suspend, resume,
+			get_params_v2_timing, get_params_v2_tap,
+			get_params_v2_osc, get_params_v2_bright,
+			get_params_v2_thlds, get_params_v2_colors;
+
+		struct __ec_todo_unpacked {
+			uint8_t num;
+		} set_brightness, seq, demo;
+
+		struct __ec_todo_unpacked {
+			uint8_t ctrl, reg, value;
+		} reg;
+
+		struct __ec_todo_unpacked {
+			uint8_t led, red, green, blue;
+		} set_rgb;
+
+		struct __ec_todo_unpacked {
+			uint8_t led;
+		} get_rgb;
+
+		struct __ec_todo_unpacked {
+			uint8_t enable;
+		} manual_suspend_ctrl;
+
+		struct lightbar_params_v0 set_params_v0;
+		struct lightbar_params_v1 set_params_v1;
+
+		struct lightbar_params_v2_timing set_v2par_timing;
+		struct lightbar_params_v2_tap set_v2par_tap;
+		struct lightbar_params_v2_oscillation set_v2par_osc;
+		struct lightbar_params_v2_brightness set_v2par_bright;
+		struct lightbar_params_v2_thresholds set_v2par_thlds;
+		struct lightbar_params_v2_colors set_v2par_colors;
+
+		struct lightbar_program set_program;
+	};
+};
+
+struct __ec_todo_packed ec_response_lightbar {
+	union {
+		struct __ec_todo_unpacked {
+			struct __ec_todo_unpacked {
+				uint8_t reg;
+				uint8_t ic0;
+				uint8_t ic1;
+			} vals[23];
+		} dump;
+
+		struct __ec_todo_unpacked {
+			uint8_t num;
+		} get_seq, get_brightness, get_demo;
+
+		struct lightbar_params_v0 get_params_v0;
+		struct lightbar_params_v1 get_params_v1;
+
+
+		struct lightbar_params_v2_timing get_params_v2_timing;
+		struct lightbar_params_v2_tap get_params_v2_tap;
+		struct lightbar_params_v2_oscillation get_params_v2_osc;
+		struct lightbar_params_v2_brightness get_params_v2_bright;
+		struct lightbar_params_v2_thresholds get_params_v2_thlds;
+		struct lightbar_params_v2_colors get_params_v2_colors;
+
+		struct __ec_todo_unpacked {
+			uint32_t num;
+			uint32_t flags;
+		} version;
+
+		struct __ec_todo_unpacked {
+			uint8_t red, green, blue;
+		} get_rgb;
+
+		struct __ec_todo_unpacked {
+			/* no return params */
+		} off, on, init, set_brightness, seq, reg, set_rgb,
+			demo, set_params_v0, set_params_v1,
+			set_program, manual_suspend_ctrl, suspend, resume,
+			set_v2par_timing, set_v2par_tap,
+			set_v2par_osc, set_v2par_bright, set_v2par_thlds,
+			set_v2par_colors;
+	};
+};
+
+/* Lightbar commands */
+enum lightbar_command {
+	LIGHTBAR_CMD_DUMP = 0,
+	LIGHTBAR_CMD_OFF = 1,
+	LIGHTBAR_CMD_ON = 2,
+	LIGHTBAR_CMD_INIT = 3,
+	LIGHTBAR_CMD_SET_BRIGHTNESS = 4,
+	LIGHTBAR_CMD_SEQ = 5,
+	LIGHTBAR_CMD_REG = 6,
+	LIGHTBAR_CMD_SET_RGB = 7,
+	LIGHTBAR_CMD_GET_SEQ = 8,
+	LIGHTBAR_CMD_DEMO = 9,
+	LIGHTBAR_CMD_GET_PARAMS_V0 = 10,
+	LIGHTBAR_CMD_SET_PARAMS_V0 = 11,
+	LIGHTBAR_CMD_VERSION = 12,
+	LIGHTBAR_CMD_GET_BRIGHTNESS = 13,
+	LIGHTBAR_CMD_GET_RGB = 14,
+	LIGHTBAR_CMD_GET_DEMO = 15,
+	LIGHTBAR_CMD_GET_PARAMS_V1 = 16,
+	LIGHTBAR_CMD_SET_PARAMS_V1 = 17,
+	LIGHTBAR_CMD_SET_PROGRAM = 18,
+	LIGHTBAR_CMD_MANUAL_SUSPEND_CTRL = 19,
+	LIGHTBAR_CMD_SUSPEND = 20,
+	LIGHTBAR_CMD_RESUME = 21,
+	LIGHTBAR_CMD_GET_PARAMS_V2_TIMING = 22,
+	LIGHTBAR_CMD_SET_PARAMS_V2_TIMING = 23,
+	LIGHTBAR_CMD_GET_PARAMS_V2_TAP = 24,
+	LIGHTBAR_CMD_SET_PARAMS_V2_TAP = 25,
+	LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION = 26,
+	LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION = 27,
+	LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS = 28,
+	LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS = 29,
+	LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS = 30,
+	LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31,
+	LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32,
+	LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33,
+	LIGHTBAR_NUM_CMDS
+};
+
+/*****************************************************************************/
+/* LED control commands */
+
+#define EC_CMD_LED_CONTROL 0x0029
+
+enum ec_led_id {
+	/* LED to indicate battery state of charge */
+	EC_LED_ID_BATTERY_LED = 0,
+	/*
+	 * LED to indicate system power state (on or in suspend).
+	 * May be on power button or on C-panel.
+	 */
+	EC_LED_ID_POWER_LED,
+	/* LED on power adapter or its plug */
+	EC_LED_ID_ADAPTER_LED,
+	/* LED to indicate left side */
+	EC_LED_ID_LEFT_LED,
+	/* LED to indicate right side */
+	EC_LED_ID_RIGHT_LED,
+	/* LED to indicate recovery mode with HW_REINIT */
+	EC_LED_ID_RECOVERY_HW_REINIT_LED,
+	/* LED to indicate sysrq debug mode. */
+	EC_LED_ID_SYSRQ_DEBUG_LED,
+
+	EC_LED_ID_COUNT
+};
+
+/* LED control flags */
+#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */
+#define EC_LED_FLAGS_AUTO  (1 << 1) /* Switch LED back to automatic control */
+
+enum ec_led_colors {
+	EC_LED_COLOR_RED = 0,
+	EC_LED_COLOR_GREEN,
+	EC_LED_COLOR_BLUE,
+	EC_LED_COLOR_YELLOW,
+	EC_LED_COLOR_WHITE,
+	EC_LED_COLOR_AMBER,
+
+	EC_LED_COLOR_COUNT
+};
+
+struct __ec_align1 ec_params_led_control {
+	uint8_t led_id;     /* Which LED to control */
+	uint8_t flags;      /* Control flags */
+
+	uint8_t brightness[EC_LED_COLOR_COUNT];
+};
+
+struct __ec_align1 ec_response_led_control {
+	/*
+	 * Available brightness value range.
+	 *
+	 * Range 0 means color channel not present.
+	 * Range 1 means on/off control.
+	 * Other values means the LED is control by PWM.
+	 */
+	uint8_t brightness_range[EC_LED_COLOR_COUNT];
+};
+
+/*****************************************************************************/
+/* Verified boot commands */
+
+/*
+ * Note: command code 0x29 version 0 was VBOOT_CMD in Link EVT; it may be
+ * reused for other purposes with version > 0.
+ */
+
+/* Verified boot hash command */
+#define EC_CMD_VBOOT_HASH 0x002A
+
+struct __ec_align4 ec_params_vboot_hash {
+	uint8_t cmd;             /* enum ec_vboot_hash_cmd */
+	uint8_t hash_type;       /* enum ec_vboot_hash_type */
+	uint8_t nonce_size;      /* Nonce size; may be 0 */
+	uint8_t reserved0;       /* Reserved; set 0 */
+	uint32_t offset;         /* Offset in flash to hash */
+	uint32_t size;           /* Number of bytes to hash */
+	uint8_t nonce_data[64];  /* Nonce data; ignored if nonce_size=0 */
+};
+
+struct __ec_align4 ec_response_vboot_hash {
+	uint8_t status;          /* enum ec_vboot_hash_status */
+	uint8_t hash_type;       /* enum ec_vboot_hash_type */
+	uint8_t digest_size;     /* Size of hash digest in bytes */
+	uint8_t reserved0;       /* Ignore; will be 0 */
+	uint32_t offset;         /* Offset in flash which was hashed */
+	uint32_t size;           /* Number of bytes hashed */
+	uint8_t hash_digest[64]; /* Hash digest data */
+};
+
+enum ec_vboot_hash_cmd {
+	EC_VBOOT_HASH_GET = 0,       /* Get current hash status */
+	EC_VBOOT_HASH_ABORT = 1,     /* Abort calculating current hash */
+	EC_VBOOT_HASH_START = 2,     /* Start computing a new hash */
+	EC_VBOOT_HASH_RECALC = 3,    /* Synchronously compute a new hash */
+};
+
+enum ec_vboot_hash_type {
+	EC_VBOOT_HASH_TYPE_SHA256 = 0, /* SHA-256 */
+};
+
+enum ec_vboot_hash_status {
+	EC_VBOOT_HASH_STATUS_NONE = 0, /* No hash (not started, or aborted) */
+	EC_VBOOT_HASH_STATUS_DONE = 1, /* Finished computing a hash */
+	EC_VBOOT_HASH_STATUS_BUSY = 2, /* Busy computing a hash */
+};
+
+/*
+ * Special values for offset for EC_VBOOT_HASH_START and EC_VBOOT_HASH_RECALC.
+ * If one of these is specified, the EC will automatically update offset and
+ * size to the correct values for the specified image (RO or RW).
+ */
+#define EC_VBOOT_HASH_OFFSET_RO		0xfffffffe
+#define EC_VBOOT_HASH_OFFSET_ACTIVE	0xfffffffd
+#define EC_VBOOT_HASH_OFFSET_UPDATE	0xfffffffc
+
+/*****************************************************************************/
+/*
+ * Motion sense commands. We'll make separate structs for sub-commands with
+ * different input args, so that we know how much to expect.
+ */
+#define EC_CMD_MOTION_SENSE_CMD 0x002B
+
+/* Motion sense commands */
+enum motionsense_command {
+	/*
+	 * Dump command returns all motion sensor data including motion sense
+	 * module flags and individual sensor flags.
+	 */
+	MOTIONSENSE_CMD_DUMP = 0,
+
+	/*
+	 * Info command returns data describing the details of a given sensor,
+	 * including enum motionsensor_type, enum motionsensor_location, and
+	 * enum motionsensor_chip.
+	 */
+	MOTIONSENSE_CMD_INFO = 1,
+
+	/*
+	 * EC Rate command is a setter/getter command for the EC sampling rate
+	 * in milliseconds.
+	 * It is per sensor, the EC run sample task  at the minimum of all
+	 * sensors EC_RATE.
+	 * For sensors without hardware FIFO, EC_RATE should be equals to 1/ODR
+	 * to collect all the sensor samples.
+	 * For sensor with hardware FIFO, EC_RATE is used as the maximal delay
+	 * to process of all motion sensors in milliseconds.
+	 */
+	MOTIONSENSE_CMD_EC_RATE = 2,
+
+	/*
+	 * Sensor ODR command is a setter/getter command for the output data
+	 * rate of a specific motion sensor in millihertz.
+	 */
+	MOTIONSENSE_CMD_SENSOR_ODR = 3,
+
+	/*
+	 * Sensor range command is a setter/getter command for the range of
+	 * a specified motion sensor in +/-G's or +/- deg/s.
+	 */
+	MOTIONSENSE_CMD_SENSOR_RANGE = 4,
+
+	/*
+	 * Setter/getter command for the keyboard wake angle. When the lid
+	 * angle is greater than this value, keyboard wake is disabled in S3,
+	 * and when the lid angle goes less than this value, keyboard wake is
+	 * enabled. Note, the lid angle measurement is an approximate,
+	 * un-calibrated value, hence the wake angle isn't exact.
+	 */
+	MOTIONSENSE_CMD_KB_WAKE_ANGLE = 5,
+
+	/*
+	 * Returns a single sensor data.
+	 */
+	MOTIONSENSE_CMD_DATA = 6,
+
+	/*
+	 * Return sensor fifo info.
+	 */
+	MOTIONSENSE_CMD_FIFO_INFO = 7,
+
+	/*
+	 * Insert a flush element in the fifo and return sensor fifo info.
+	 * The host can use that element to synchronize its operation.
+	 */
+	MOTIONSENSE_CMD_FIFO_FLUSH = 8,
+
+	/*
+	 * Return a portion of the fifo.
+	 */
+	MOTIONSENSE_CMD_FIFO_READ = 9,
+
+	/*
+	 * Perform low level calibration.
+	 * On sensors that support it, ask to do offset calibration.
+	 */
+	MOTIONSENSE_CMD_PERFORM_CALIB = 10,
+
+	/*
+	 * Sensor Offset command is a setter/getter command for the offset
+	 * used for calibration.
+	 * The offsets can be calculated by the host, or via
+	 * PERFORM_CALIB command.
+	 */
+	MOTIONSENSE_CMD_SENSOR_OFFSET = 11,
+
+	/*
+	 * List available activities for a MOTION sensor.
+	 * Indicates if they are enabled or disabled.
+	 */
+	MOTIONSENSE_CMD_LIST_ACTIVITIES = 12,
+
+	/*
+	 * Activity management
+	 * Enable/Disable activity recognition.
+	 */
+	MOTIONSENSE_CMD_SET_ACTIVITY = 13,
+
+	/*
+	 * Lid Angle
+	 */
+	MOTIONSENSE_CMD_LID_ANGLE = 14,
+
+	/*
+	 * Allow the FIFO to trigger interrupt via MKBP events.
+	 * By default the FIFO does not send interrupt to process the FIFO
+	 * until the AP is ready or it is coming from a wakeup sensor.
+	 */
+	MOTIONSENSE_CMD_FIFO_INT_ENABLE = 15,
+
+	/*
+	 * Spoof the readings of the sensors.  The spoofed readings can be set
+	 * to arbitrary values, or will lock to the last read actual values.
+	 */
+	MOTIONSENSE_CMD_SPOOF = 16,
+
+	/* Number of motionsense sub-commands. */
+	MOTIONSENSE_NUM_CMDS
+};
+
+/* List of motion sensor types. */
+enum motionsensor_type {
+	MOTIONSENSE_TYPE_ACCEL = 0,
+	MOTIONSENSE_TYPE_GYRO = 1,
+	MOTIONSENSE_TYPE_MAG = 2,
+	MOTIONSENSE_TYPE_PROX = 3,
+	MOTIONSENSE_TYPE_LIGHT = 4,
+	MOTIONSENSE_TYPE_ACTIVITY = 5,
+	MOTIONSENSE_TYPE_BARO = 6,
+	MOTIONSENSE_TYPE_MAX,
+};
+
+/* List of motion sensor locations. */
+enum motionsensor_location {
+	MOTIONSENSE_LOC_BASE = 0,
+	MOTIONSENSE_LOC_LID = 1,
+	MOTIONSENSE_LOC_MAX,
+};
+
+/* List of motion sensor chips. */
+enum motionsensor_chip {
+	MOTIONSENSE_CHIP_KXCJ9 = 0,
+	MOTIONSENSE_CHIP_LSM6DS0 = 1,
+	MOTIONSENSE_CHIP_BMI160 = 2,
+	MOTIONSENSE_CHIP_SI1141 = 3,
+	MOTIONSENSE_CHIP_SI1142 = 4,
+	MOTIONSENSE_CHIP_SI1143 = 5,
+	MOTIONSENSE_CHIP_KX022 = 6,
+	MOTIONSENSE_CHIP_L3GD20H = 7,
+	MOTIONSENSE_CHIP_BMA255 = 8,
+	MOTIONSENSE_CHIP_BMP280 = 9,
+	MOTIONSENSE_CHIP_OPT3001 = 10,
+};
+
+struct __ec_todo_packed ec_response_motion_sensor_data {
+	/* Flags for each sensor. */
+	uint8_t flags;
+	/* sensor number the data comes from */
+	uint8_t sensor_num;
+	/* Each sensor is up to 3-axis. */
+	union {
+		int16_t             data[3];
+		struct __ec_todo_packed {
+			uint16_t    reserved;
+			uint32_t    timestamp;
+		};
+		struct __ec_todo_unpacked {
+			uint8_t     activity; /* motionsensor_activity */
+			uint8_t     state;
+			int16_t     add_info[2];
+		};
+	};
+};
+
+/* Note: used in ec_response_get_next_data */
+struct __ec_todo_packed ec_response_motion_sense_fifo_info {
+	/* Size of the fifo */
+	uint16_t size;
+	/* Amount of space used in the fifo */
+	uint16_t count;
+	/* Timestamp recorded in us */
+	uint32_t timestamp;
+	/* Total amount of vector lost */
+	uint16_t total_lost;
+	/* Lost events since the last fifo_info, per sensors */
+	uint16_t lost[0];
+};
+
+struct __ec_todo_packed ec_response_motion_sense_fifo_data {
+	uint32_t number_data;
+	struct ec_response_motion_sensor_data data[0];
+};
+
+/* List supported activity recognition */
+enum motionsensor_activity {
+	MOTIONSENSE_ACTIVITY_RESERVED = 0,
+	MOTIONSENSE_ACTIVITY_SIG_MOTION = 1,
+	MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2,
+};
+
+struct __ec_todo_unpacked ec_motion_sense_activity {
+	uint8_t sensor_num;
+	uint8_t activity; /* one of enum motionsensor_activity */
+	uint8_t enable;   /* 1: enable, 0: disable */
+	uint8_t reserved;
+	uint16_t parameters[3]; /* activity dependent parameters */
+};
+
+/* Module flag masks used for the dump sub-command. */
+#define MOTIONSENSE_MODULE_FLAG_ACTIVE (1<<0)
+
+/* Sensor flag masks used for the dump sub-command. */
+#define MOTIONSENSE_SENSOR_FLAG_PRESENT (1<<0)
+
+/*
+ * Flush entry for synchronization.
+ * data contains time stamp
+ */
+#define MOTIONSENSE_SENSOR_FLAG_FLUSH (1<<0)
+#define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP (1<<1)
+#define MOTIONSENSE_SENSOR_FLAG_WAKEUP (1<<2)
+#define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE (1<<3)
+
+/*
+ * Send this value for the data element to only perform a read. If you
+ * send any other value, the EC will interpret it as data to set and will
+ * return the actual value set.
+ */
+#define EC_MOTION_SENSE_NO_VALUE -1
+
+#define EC_MOTION_SENSE_INVALID_CALIB_TEMP 0x8000
+
+/* MOTIONSENSE_CMD_SENSOR_OFFSET subcommand flag */
+/* Set Calibration information */
+#define MOTION_SENSE_SET_OFFSET 1
+
+#define LID_ANGLE_UNRELIABLE 500
+
+enum motionsense_spoof_mode {
+	/* Disable spoof mode. */
+	MOTIONSENSE_SPOOF_MODE_DISABLE = 0,
+
+	/* Enable spoof mode, but use provided component values. */
+	MOTIONSENSE_SPOOF_MODE_CUSTOM,
+
+	/* Enable spoof mode, but use the current sensor values. */
+	MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT,
+
+	/* Query the current spoof mode status for the sensor. */
+	MOTIONSENSE_SPOOF_MODE_QUERY,
+};
+
+struct __ec_todo_packed ec_params_motion_sense {
+	uint8_t cmd;
+	union {
+		/* Used for MOTIONSENSE_CMD_DUMP */
+		struct __ec_todo_unpacked {
+			/*
+			 * Maximal number of sensor the host is expecting.
+			 * 0 means the host is only interested in the number
+			 * of sensors controlled by the EC.
+			 */
+			uint8_t max_sensor_count;
+		} dump;
+
+		/*
+		 * Used for MOTIONSENSE_CMD_KB_WAKE_ANGLE.
+		 */
+		struct __ec_todo_unpacked {
+			/* Data to set or EC_MOTION_SENSE_NO_VALUE to read.
+			 * kb_wake_angle: angle to wakup AP.
+			 */
+			int16_t data;
+		} kb_wake_angle;
+
+		/* Used for MOTIONSENSE_CMD_INFO, MOTIONSENSE_CMD_DATA
+		 * and MOTIONSENSE_CMD_PERFORM_CALIB. */
+		struct __ec_todo_unpacked {
+			uint8_t sensor_num;
+		} info, info_3, data, fifo_flush, perform_calib,
+				list_activities;
+
+		/*
+		 * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR
+		 * and MOTIONSENSE_CMD_SENSOR_RANGE.
+		 */
+		struct __ec_todo_unpacked {
+			uint8_t sensor_num;
+
+			/* Rounding flag, true for round-up, false for down. */
+			uint8_t roundup;
+
+			uint16_t reserved;
+
+			/* Data to set or EC_MOTION_SENSE_NO_VALUE to read. */
+			int32_t data;
+		} ec_rate, sensor_odr, sensor_range;
+
+		/* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */
+		struct __ec_todo_packed {
+			uint8_t sensor_num;
+
+			/*
+			 * bit 0: If set (MOTION_SENSE_SET_OFFSET), set
+			 * the calibration information in the EC.
+			 * If unset, just retrieve calibration information.
+			 */
+			uint16_t flags;
+
+			/*
+			 * Temperature at calibration, in units of 0.01 C
+			 * 0x8000: invalid / unknown.
+			 * 0x0: 0C
+			 * 0x7fff: +327.67C
+			 */
+			int16_t temp;
+
+			/*
+			 * Offset for calibration.
+			 * Unit:
+			 * Accelerometer: 1/1024 g
+			 * Gyro:          1/1024 deg/s
+			 * Compass:       1/16 uT
+			 */
+			int16_t offset[3];
+		} sensor_offset;
+
+		/* Used for MOTIONSENSE_CMD_FIFO_INFO */
+		struct __ec_todo_unpacked {
+		} fifo_info;
+
+		/* Used for MOTIONSENSE_CMD_FIFO_READ */
+		struct __ec_todo_unpacked {
+			/*
+			 * Number of expected vector to return.
+			 * EC may return less or 0 if none available.
+			 */
+			uint32_t max_data_vector;
+		} fifo_read;
+
+		struct ec_motion_sense_activity set_activity;
+
+		/* Used for MOTIONSENSE_CMD_LID_ANGLE */
+		struct __ec_todo_unpacked {
+		} lid_angle;
+
+		/* Used for MOTIONSENSE_CMD_FIFO_INT_ENABLE */
+		struct __ec_todo_unpacked {
+			/*
+			 * 1: enable, 0 disable fifo,
+			 * EC_MOTION_SENSE_NO_VALUE return value.
+			 */
+			int8_t enable;
+		} fifo_int_enable;
+
+		/* Used for MOTIONSENSE_CMD_SPOOF */
+		struct __ec_todo_packed {
+			uint8_t sensor_id;
+
+			/* See enum motionsense_spoof_mode. */
+			uint8_t spoof_enable;
+
+			/* Ignored, used for alignment. */
+			uint8_t reserved;
+
+			/* Individual component values to spoof. */
+			int16_t components[3];
+		} spoof;
+	};
+};
+
+struct __ec_todo_packed ec_response_motion_sense {
+	union {
+		/* Used for MOTIONSENSE_CMD_DUMP */
+		struct __ec_todo_unpacked {
+			/* Flags representing the motion sensor module. */
+			uint8_t module_flags;
+
+			/* Number of sensors managed directly by the EC */
+			uint8_t sensor_count;
+
+			/*
+			 * sensor data is truncated if response_max is too small
+			 * for holding all the data.
+			 */
+			struct ec_response_motion_sensor_data sensor[0];
+		} dump;
+
+		/* Used for MOTIONSENSE_CMD_INFO. */
+		struct __ec_todo_unpacked {
+			/* Should be element of enum motionsensor_type. */
+			uint8_t type;
+
+			/* Should be element of enum motionsensor_location. */
+			uint8_t location;
+
+			/* Should be element of enum motionsensor_chip. */
+			uint8_t chip;
+		} info;
+
+		/* Used for MOTIONSENSE_CMD_INFO version 3 */
+		struct __ec_todo_unpacked {
+			/* Should be element of enum motionsensor_type. */
+			uint8_t type;
+
+			/* Should be element of enum motionsensor_location. */
+			uint8_t location;
+
+			/* Should be element of enum motionsensor_chip. */
+			uint8_t chip;
+
+			/* Minimum sensor sampling frequency */
+			uint32_t min_frequency;
+
+			/* Maximum sensor sampling frequency */
+			uint32_t max_frequency;
+
+			/* Max number of sensor events that could be in fifo */
+			uint32_t fifo_max_event_count;
+		} info_3;
+
+		/* Used for MOTIONSENSE_CMD_DATA */
+		struct ec_response_motion_sensor_data data;
+
+		/*
+		 * Used for MOTIONSENSE_CMD_EC_RATE, MOTIONSENSE_CMD_SENSOR_ODR,
+		 * MOTIONSENSE_CMD_SENSOR_RANGE,
+		 * MOTIONSENSE_CMD_KB_WAKE_ANGLE,
+		 * MOTIONSENSE_CMD_FIFO_INT_ENABLE and
+		 * MOTIONSENSE_CMD_SPOOF.
+		 */
+		struct __ec_todo_unpacked {
+			/* Current value of the parameter queried. */
+			int32_t ret;
+		} ec_rate, sensor_odr, sensor_range, kb_wake_angle,
+		  fifo_int_enable, spoof;
+
+		/* Used for MOTIONSENSE_CMD_SENSOR_OFFSET */
+		struct __ec_todo_unpacked  {
+			int16_t temp;
+			int16_t offset[3];
+		} sensor_offset, perform_calib;
+
+		struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush;
+
+		struct ec_response_motion_sense_fifo_data fifo_read;
+
+		struct __ec_todo_packed {
+			uint16_t reserved;
+			uint32_t enabled;
+			uint32_t disabled;
+		} list_activities;
+
+		struct __ec_todo_unpacked {
+		} set_activity;
+
+		/* Used for MOTIONSENSE_CMD_LID_ANGLE */
+		struct __ec_todo_unpacked {
+			/*
+			 * Angle between 0 and 360 degree if available,
+			 * LID_ANGLE_UNRELIABLE otherwise.
+			 */
+			uint16_t value;
+		} lid_angle;
+	};
+};
+
+/*****************************************************************************/
+/* Force lid open command */
+
+/* Make lid event always open */
+#define EC_CMD_FORCE_LID_OPEN 0x002C
+
+struct __ec_align1 ec_params_force_lid_open {
+	uint8_t enabled;
+};
+
+/*****************************************************************************/
+/* Configure the behavior of the power button */
+#define EC_CMD_CONFIG_POWER_BUTTON 0x002D
+
+enum ec_config_power_button_flags {
+	/* Enable/Disable power button pulses for x86 devices */
+	EC_POWER_BUTTON_ENABLE_PULSE = (1 << 0),
+};
+
+struct __ec_align1 ec_params_config_power_button {
+	/* See enum ec_config_power_button_flags */
+	uint8_t flags;
+};
+
+/*****************************************************************************/
+/* USB charging control commands */
+
+/* Set USB port charging mode */
+#define EC_CMD_USB_CHARGE_SET_MODE 0x0030
+
+struct __ec_align1 ec_params_usb_charge_set_mode {
+	uint8_t usb_port_id;
+	uint8_t mode;
+};
+
+/*****************************************************************************/
+/* Persistent storage for host */
+
+/* Maximum bytes that can be read/written in a single command */
+#define EC_PSTORE_SIZE_MAX 64
+
+/* Get persistent storage info */
+#define EC_CMD_PSTORE_INFO 0x0040
+
+struct __ec_align4 ec_response_pstore_info {
+	/* Persistent storage size, in bytes */
+	uint32_t pstore_size;
+	/* Access size; read/write offset and size must be a multiple of this */
+	uint32_t access_size;
+};
+
+/*
+ * Read persistent storage
+ *
+ * Response is params.size bytes of data.
+ */
+#define EC_CMD_PSTORE_READ 0x0041
+
+struct __ec_align4 ec_params_pstore_read {
+	uint32_t offset;   /* Byte offset to read */
+	uint32_t size;     /* Size to read in bytes */
+};
+
+/* Write persistent storage */
+#define EC_CMD_PSTORE_WRITE 0x0042
+
+struct __ec_align4 ec_params_pstore_write {
+	uint32_t offset;   /* Byte offset to write */
+	uint32_t size;     /* Size to write in bytes */
+	uint8_t data[EC_PSTORE_SIZE_MAX];
+};
+
+/*****************************************************************************/
+/* Real-time clock */
+
+/* RTC params and response structures */
+struct __ec_align4 ec_params_rtc {
+	uint32_t time;
+};
+
+struct __ec_align4 ec_response_rtc {
+	uint32_t time;
+};
+
+/* These use ec_response_rtc */
+#define EC_CMD_RTC_GET_VALUE 0x0044
+#define EC_CMD_RTC_GET_ALARM 0x0045
+
+/* These all use ec_params_rtc */
+#define EC_CMD_RTC_SET_VALUE 0x0046
+#define EC_CMD_RTC_SET_ALARM 0x0047
+
+/* Pass as time param to SET_ALARM to clear the current alarm */
+#define EC_RTC_ALARM_CLEAR 0
+
+/*****************************************************************************/
+/* Port80 log access */
+
+/* Maximum entries that can be read/written in a single command */
+#define EC_PORT80_SIZE_MAX 32
+
+/* Get last port80 code from previous boot */
+#define EC_CMD_PORT80_LAST_BOOT 0x0048
+#define EC_CMD_PORT80_READ 0x0048
+
+enum ec_port80_subcmd {
+	EC_PORT80_GET_INFO = 0,
+	EC_PORT80_READ_BUFFER,
+};
+
+struct __ec_todo_packed ec_params_port80_read {
+	uint16_t subcmd;
+	union {
+		struct __ec_todo_unpacked {
+			uint32_t offset;
+			uint32_t num_entries;
+		} read_buffer;
+	};
+};
+
+struct __ec_todo_packed ec_response_port80_read {
+	union {
+		struct __ec_todo_unpacked {
+			uint32_t writes;
+			uint32_t history_size;
+			uint32_t last_boot;
+		} get_info;
+		struct __ec_todo_unpacked {
+			uint16_t codes[EC_PORT80_SIZE_MAX];
+		} data;
+	};
+};
+
+struct __ec_align2 ec_response_port80_last_boot {
+	uint16_t code;
+};
+
+/*****************************************************************************/
+/* Temporary secure storage for host verified boot use */
+
+/* Number of bytes in a vstore slot */
+#define EC_VSTORE_SLOT_SIZE 64
+
+/* Maximum number of vstore slots */
+#define EC_VSTORE_SLOT_MAX 32
+
+/* Get persistent storage info */
+#define EC_CMD_VSTORE_INFO 0x0049
+struct __ec_align_size1 ec_response_vstore_info {
+	/* Indicates which slots are locked */
+	uint32_t slot_locked;
+	/* Total number of slots available */
+	uint8_t slot_count;
+};
+
+/*
+ * Read temporary secure storage
+ *
+ * Response is EC_VSTORE_SLOT_SIZE bytes of data.
+ */
+#define EC_CMD_VSTORE_READ 0x004A
+
+struct __ec_align1 ec_params_vstore_read {
+	uint8_t slot; /* Slot to read from */
+};
+
+struct __ec_align1 ec_response_vstore_read {
+	uint8_t data[EC_VSTORE_SLOT_SIZE];
+};
+
+/*
+ * Write temporary secure storage and lock it.
+ */
+#define EC_CMD_VSTORE_WRITE 0x004B
+
+struct __ec_align1 ec_params_vstore_write {
+	uint8_t slot; /* Slot to write to */
+	uint8_t data[EC_VSTORE_SLOT_SIZE];
+};
+
+/*****************************************************************************/
+/* Thermal engine commands. Note that there are two implementations. We'll
+ * reuse the command number, but the data and behavior is incompatible.
+ * Version 0 is what originally shipped on Link.
+ * Version 1 separates the CPU thermal limits from the fan control.
+ */
+
+#define EC_CMD_THERMAL_SET_THRESHOLD 0x0050
+#define EC_CMD_THERMAL_GET_THRESHOLD 0x0051
+
+/* The version 0 structs are opaque. You have to know what they are for
+ * the get/set commands to make any sense.
+ */
+
+/* Version 0 - set */
+struct __ec_align2 ec_params_thermal_set_threshold {
+	uint8_t sensor_type;
+	uint8_t threshold_id;
+	uint16_t value;
+};
+
+/* Version 0 - get */
+struct __ec_align1 ec_params_thermal_get_threshold {
+	uint8_t sensor_type;
+	uint8_t threshold_id;
+};
+
+struct __ec_align2 ec_response_thermal_get_threshold {
+	uint16_t value;
+};
+
+
+/* The version 1 structs are visible. */
+enum ec_temp_thresholds {
+	EC_TEMP_THRESH_WARN = 0,
+	EC_TEMP_THRESH_HIGH,
+	EC_TEMP_THRESH_HALT,
+
+	EC_TEMP_THRESH_COUNT
+};
+
+/*
+ * Thermal configuration for one temperature sensor. Temps are in degrees K.
+ * Zero values will be silently ignored by the thermal task.
+ *
+ * Note that this structure is a sub-structure of
+ * ec_params_thermal_set_threshold_v1, but maintains its alignment there.
+ */
+struct __ec_align4 ec_thermal_config {
+	uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */
+	uint32_t temp_fan_off;		/* no active cooling needed */
+	uint32_t temp_fan_max;		/* max active cooling needed */
+};
+
+/* Version 1 - get config for one sensor. */
+struct __ec_align4 ec_params_thermal_get_threshold_v1 {
+	uint32_t sensor_num;
+};
+/* This returns a struct ec_thermal_config */
+
+/* Version 1 - set config for one sensor.
+ * Use read-modify-write for best results! */
+struct __ec_align4 ec_params_thermal_set_threshold_v1 {
+	uint32_t sensor_num;
+	struct ec_thermal_config cfg;
+};
+/* This returns no data */
+
+/****************************************************************************/
+
+/* Toggle automatic fan control */
+#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052
+
+/* Version 1 of input params */
+struct __ec_align1 ec_params_auto_fan_ctrl_v1 {
+	uint8_t fan_idx;
+};
+
+/* Get/Set TMP006 calibration data */
+#define EC_CMD_TMP006_GET_CALIBRATION 0x0053
+#define EC_CMD_TMP006_SET_CALIBRATION 0x0054
+
+/*
+ * The original TMP006 calibration only needed four params, but now we need
+ * more. Since the algorithm is nothing but magic numbers anyway, we'll leave
+ * the params opaque. The v1 "get" response will include the algorithm number
+ * and how many params it requires. That way we can change the EC code without
+ * needing to update this file. We can also use a different algorithm on each
+ * sensor.
+ */
+
+/* This is the same struct for both v0 and v1. */
+struct __ec_align1 ec_params_tmp006_get_calibration {
+	uint8_t index;
+};
+
+/* Version 0 */
+struct __ec_align4 ec_response_tmp006_get_calibration_v0 {
+	float s0;
+	float b0;
+	float b1;
+	float b2;
+};
+
+struct __ec_align4 ec_params_tmp006_set_calibration_v0 {
+	uint8_t index;
+	uint8_t reserved[3];
+	float s0;
+	float b0;
+	float b1;
+	float b2;
+};
+
+/* Version 1 */
+struct __ec_align4 ec_response_tmp006_get_calibration_v1 {
+	uint8_t algorithm;
+	uint8_t num_params;
+	uint8_t reserved[2];
+	float val[0];
+};
+
+struct __ec_align4 ec_params_tmp006_set_calibration_v1 {
+	uint8_t index;
+	uint8_t algorithm;
+	uint8_t num_params;
+	uint8_t reserved;
+	float val[0];
+};
+
+
+/* Read raw TMP006 data */
+#define EC_CMD_TMP006_GET_RAW 0x0055
+
+struct __ec_align1 ec_params_tmp006_get_raw {
+	uint8_t index;
+};
+
+struct __ec_align4 ec_response_tmp006_get_raw {
+	int32_t t;  /* In 1/100 K */
+	int32_t v;  /* In nV */
+};
+
+/*****************************************************************************/
+/* MKBP - Matrix KeyBoard Protocol */
+
+/*
+ * Read key state
+ *
+ * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for
+ * expected response size.
+ *
+ * NOTE: This has been superseded by EC_CMD_MKBP_GET_NEXT_EVENT.  If you wish
+ * to obtain the instantaneous state, use EC_CMD_MKBP_INFO with the type
+ * EC_MKBP_INFO_CURRENT and event EC_MKBP_EVENT_KEY_MATRIX.
+ */
+#define EC_CMD_MKBP_STATE 0x0060
+
+/*
+ * Provide information about various MKBP things.  See enum ec_mkbp_info_type.
+ */
+#define EC_CMD_MKBP_INFO 0x0061
+
+struct __ec_align_size1 ec_response_mkbp_info {
+	uint32_t rows;
+	uint32_t cols;
+	/* Formerly "switches", which was 0. */
+	uint8_t reserved;
+};
+
+struct __ec_align1 ec_params_mkbp_info {
+	uint8_t info_type;
+	uint8_t event_type;
+};
+
+enum ec_mkbp_info_type {
+	/*
+	 * Info about the keyboard matrix: number of rows and columns.
+	 *
+	 * Returns struct ec_response_mkbp_info.
+	 */
+	EC_MKBP_INFO_KBD = 0,
+
+	/*
+	 * For buttons and switches, info about which specifically are
+	 * supported.  event_type must be set to one of the values in enum
+	 * ec_mkbp_event.
+	 *
+	 * For EC_MKBP_EVENT_BUTTON and EC_MKBP_EVENT_SWITCH, returns a 4 byte
+	 * bitmask indicating which buttons or switches are present.  See the
+	 * bit inidices below.
+	 */
+	EC_MKBP_INFO_SUPPORTED = 1,
+
+	/*
+	 * Instantaneous state of buttons and switches.
+	 *
+	 * event_type must be set to one of the values in enum ec_mkbp_event.
+	 *
+	 * For EC_MKBP_EVENT_KEY_MATRIX, returns uint8_t key_matrix[13]
+	 * indicating the current state of the keyboard matrix.
+	 *
+	 * For EC_MKBP_EVENT_HOST_EVENT, return uint32_t host_event, the raw
+	 * event state.
+	 *
+	 * For EC_MKBP_EVENT_BUTTON, returns uint32_t buttons, indicating the
+	 * state of supported buttons.
+	 *
+	 * For EC_MKBP_EVENT_SWITCH, returns uint32_t switches, indicating the
+	 * state of supported switches.
+	 */
+	EC_MKBP_INFO_CURRENT = 2,
+};
+
+/* Simulate key press */
+#define EC_CMD_MKBP_SIMULATE_KEY 0x0062
+
+struct __ec_align1 ec_params_mkbp_simulate_key {
+	uint8_t col;
+	uint8_t row;
+	uint8_t pressed;
+};
+
+/* Configure keyboard scanning */
+#define EC_CMD_MKBP_SET_CONFIG 0x0064
+#define EC_CMD_MKBP_GET_CONFIG 0x0065
+
+/* flags */
+enum mkbp_config_flags {
+	EC_MKBP_FLAGS_ENABLE = 1,	/* Enable keyboard scanning */
+};
+
+enum mkbp_config_valid {
+	EC_MKBP_VALID_SCAN_PERIOD		= 1 << 0,
+	EC_MKBP_VALID_POLL_TIMEOUT		= 1 << 1,
+	EC_MKBP_VALID_MIN_POST_SCAN_DELAY	= 1 << 3,
+	EC_MKBP_VALID_OUTPUT_SETTLE		= 1 << 4,
+	EC_MKBP_VALID_DEBOUNCE_DOWN		= 1 << 5,
+	EC_MKBP_VALID_DEBOUNCE_UP		= 1 << 6,
+	EC_MKBP_VALID_FIFO_MAX_DEPTH		= 1 << 7,
+};
+
+/*
+ * Configuration for our key scanning algorithm.
+ *
+ * Note that this is used as a sub-structure of
+ * ec_{params/response}_mkbp_get_config.
+ */
+struct __ec_align_size1 ec_mkbp_config {
+	uint32_t valid_mask;		/* valid fields */
+	uint8_t flags;		/* some flags (enum mkbp_config_flags) */
+	uint8_t valid_flags;		/* which flags are valid */
+	uint16_t scan_period_us;	/* period between start of scans */
+	/* revert to interrupt mode after no activity for this long */
+	uint32_t poll_timeout_us;
+	/*
+	 * minimum post-scan relax time. Once we finish a scan we check
+	 * the time until we are due to start the next one. If this time is
+	 * shorter this field, we use this instead.
+	 */
+	uint16_t min_post_scan_delay_us;
+	/* delay between setting up output and waiting for it to settle */
+	uint16_t output_settle_us;
+	uint16_t debounce_down_us;	/* time for debounce on key down */
+	uint16_t debounce_up_us;	/* time for debounce on key up */
+	/* maximum depth to allow for fifo (0 = no keyscan output) */
+	uint8_t fifo_max_depth;
+};
+
+struct __ec_align_size1 ec_params_mkbp_set_config {
+	struct ec_mkbp_config config;
+};
+
+struct __ec_align_size1 ec_response_mkbp_get_config {
+	struct ec_mkbp_config config;
+};
+
+/* Run the key scan emulation */
+#define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066
+
+enum ec_keyscan_seq_cmd {
+	EC_KEYSCAN_SEQ_STATUS = 0,	/* Get status information */
+	EC_KEYSCAN_SEQ_CLEAR = 1,	/* Clear sequence */
+	EC_KEYSCAN_SEQ_ADD = 2,		/* Add item to sequence */
+	EC_KEYSCAN_SEQ_START = 3,	/* Start running sequence */
+	EC_KEYSCAN_SEQ_COLLECT = 4,	/* Collect sequence summary data */
+};
+
+enum ec_collect_flags {
+	/*
+	 * Indicates this scan was processed by the EC. Due to timing, some
+	 * scans may be skipped.
+	 */
+	EC_KEYSCAN_SEQ_FLAG_DONE	= 1 << 0,
+};
+
+struct __ec_align1 ec_collect_item {
+	uint8_t flags;		/* some flags (enum ec_collect_flags) */
+};
+
+struct __ec_todo_packed ec_params_keyscan_seq_ctrl {
+	uint8_t cmd;	/* Command to send (enum ec_keyscan_seq_cmd) */
+	union {
+		struct __ec_align1 {
+			uint8_t active;		/* still active */
+			uint8_t num_items;	/* number of items */
+			/* Current item being presented */
+			uint8_t cur_item;
+		} status;
+		struct __ec_todo_unpacked {
+			/*
+			 * Absolute time for this scan, measured from the
+			 * start of the sequence.
+			 */
+			uint32_t time_us;
+			uint8_t scan[0];	/* keyscan data */
+		} add;
+		struct __ec_align1 {
+			uint8_t start_item;	/* First item to return */
+			uint8_t num_items;	/* Number of items to return */
+		} collect;
+	};
+};
+
+struct __ec_todo_packed ec_result_keyscan_seq_ctrl {
+	union {
+		struct __ec_todo_unpacked {
+			uint8_t num_items;	/* Number of items */
+			/* Data for each item */
+			struct ec_collect_item item[0];
+		} collect;
+	};
+};
+
+/*
+ * Get the next pending MKBP event.
+ *
+ * Returns EC_RES_UNAVAILABLE if there is no event pending.
+ */
+#define EC_CMD_GET_NEXT_EVENT 0x0067
+
+enum ec_mkbp_event {
+	/* Keyboard matrix changed. The event data is the new matrix state. */
+	EC_MKBP_EVENT_KEY_MATRIX = 0,
+
+	/* New host event. The event data is 4 bytes of host event flags. */
+	EC_MKBP_EVENT_HOST_EVENT = 1,
+
+	/* New Sensor FIFO data. The event data is fifo_info structure. */
+	EC_MKBP_EVENT_SENSOR_FIFO = 2,
+
+	/* The state of the non-matrixed buttons have changed. */
+	EC_MKBP_EVENT_BUTTON = 3,
+
+	/* The state of the switches have changed. */
+	EC_MKBP_EVENT_SWITCH = 4,
+
+	/* New Fingerprint sensor event, the event data is fp_events bitmap. */
+	EC_MKBP_EVENT_FINGERPRINT = 5,
+
+	/*
+	 * Sysrq event: send emulated sysrq. The event data is sysrq,
+	 * corresponding to the key to be pressed.
+	 */
+	EC_MKBP_EVENT_SYSRQ = 6,
+
+	/* Number of MKBP events */
+	EC_MKBP_EVENT_COUNT,
+};
+
+union __ec_align_offset1 ec_response_get_next_data {
+	uint8_t key_matrix[13];
+
+	/* Unaligned */
+	uint32_t host_event;
+
+	struct __ec_todo_unpacked {
+		/* For aligning the fifo_info */
+		uint8_t reserved[3];
+		struct ec_response_motion_sense_fifo_info info;
+	} sensor_fifo;
+
+	uint32_t buttons;
+
+	uint32_t switches;
+
+	uint32_t fp_events;
+
+	uint32_t sysrq;
+};
+
+struct __ec_align1 ec_response_get_next_event {
+	uint8_t event_type;
+	/* Followed by event data if any */
+	union ec_response_get_next_data data;
+};
+
+/* Bit indices for buttons and switches.*/
+/* Buttons */
+#define EC_MKBP_POWER_BUTTON	0
+#define EC_MKBP_VOL_UP		1
+#define EC_MKBP_VOL_DOWN	2
+#define EC_MKBP_RECOVERY	3
+
+/* Switches */
+#define EC_MKBP_LID_OPEN	0
+#define EC_MKBP_TABLET_MODE	1
+
+/* Run keyboard factory test scanning */
+#define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068
+
+struct __ec_align2 ec_response_keyboard_factory_test {
+	uint16_t shorted;	/* Keyboard pins are shorted */
+};
+
+/* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */
+#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF)
+#define EC_MKBP_FP_FINGER_DOWN          (1 << 29)
+#define EC_MKBP_FP_FINGER_UP            (1 << 30)
+#define EC_MKBP_FP_IMAGE_READY          (1 << 31)
+
+/*****************************************************************************/
+/* Temperature sensor commands */
+
+/* Read temperature sensor info */
+#define EC_CMD_TEMP_SENSOR_GET_INFO 0x0070
+
+struct __ec_align1 ec_params_temp_sensor_get_info {
+	uint8_t id;
+};
+
+struct __ec_align1 ec_response_temp_sensor_get_info {
+	char sensor_name[32];
+	uint8_t sensor_type;
+};
+
+/*****************************************************************************/
+
+/*
+ * Note: host commands 0x80 - 0x87 are reserved to avoid conflict with ACPI
+ * commands accidentally sent to the wrong interface.  See the ACPI section
+ * below.
+ */
+
+/*****************************************************************************/
+/* Host event commands */
+
+
+/* Obsolete. New implementation should use EC_CMD_PROGRAM_HOST_EVENT instead */
+/*
+ * Host event mask params and response structures, shared by all of the host
+ * event commands below.
+ */
+struct __ec_align4 ec_params_host_event_mask {
+	uint32_t mask;
+};
+
+struct __ec_align4 ec_response_host_event_mask {
+	uint32_t mask;
+};
+
+/* These all use ec_response_host_event_mask */
+#define EC_CMD_HOST_EVENT_GET_B         0x0087
+#define EC_CMD_HOST_EVENT_GET_SMI_MASK  0x0088
+#define EC_CMD_HOST_EVENT_GET_SCI_MASK  0x0089
+#define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D
+
+/* These all use ec_params_host_event_mask */
+#define EC_CMD_HOST_EVENT_SET_SMI_MASK  0x008A
+#define EC_CMD_HOST_EVENT_SET_SCI_MASK  0x008B
+#define EC_CMD_HOST_EVENT_CLEAR         0x008C
+#define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E
+#define EC_CMD_HOST_EVENT_CLEAR_B       0x008F
+
+/*
+ * Unified host event programming interface - Should be used by newer versions
+ * of BIOS/OS to program host events and masks
+ */
+
+struct __ec_align4 ec_params_host_event {
+
+	/* Action requested by host - one of enum ec_host_event_action. */
+	uint8_t action;
+
+	/*
+	 * Mask type that the host requested the action on - one of
+	 * enum ec_host_event_mask_type.
+	 */
+	uint8_t mask_type;
+
+	/* Set to 0, ignore on read */
+	uint16_t reserved;
+
+	/* Value to be used in case of set operations. */
+	uint64_t value;
+};
+
+/*
+ * Response structure returned by EC_CMD_HOST_EVENT.
+ * Update the value on a GET request. Set to 0 on GET/CLEAR
+ */
+
+struct __ec_align4 ec_response_host_event {
+
+	/* Mask value in case of get operation */
+	uint64_t value;
+};
+
+enum ec_host_event_action {
+	/*
+	 * params.value is ignored. Value of mask_type populated
+	 * in response.value
+	 */
+	EC_HOST_EVENT_GET,
+
+	/* Bits in params.value are set */
+	EC_HOST_EVENT_SET,
+
+	/* Bits in params.value are cleared */
+	EC_HOST_EVENT_CLEAR,
+};
+
+enum ec_host_event_mask_type {
+
+	/* Main host event copy */
+	EC_HOST_EVENT_MAIN,
+
+	/* Copy B of host events */
+	EC_HOST_EVENT_B,
+
+	/* SCI Mask */
+	EC_HOST_EVENT_SCI_MASK,
+
+	/* SMI Mask */
+	EC_HOST_EVENT_SMI_MASK,
+
+	/* Mask of events that should be always reported in hostevents */
+	EC_HOST_EVENT_ALWAYS_REPORT_MASK,
+
+	/* Active wake mask */
+	EC_HOST_EVENT_ACTIVE_WAKE_MASK,
+
+	/* Lazy wake mask for S0ix */
+	EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX,
+
+	/* Lazy wake mask for S3 */
+	EC_HOST_EVENT_LAZY_WAKE_MASK_S3,
+
+	/* Lazy wake mask for S5 */
+	EC_HOST_EVENT_LAZY_WAKE_MASK_S5,
+};
+
+#define EC_CMD_HOST_EVENT       0x00A4
+
+/*****************************************************************************/
+/* Switch commands */
+
+/* Enable/disable LCD backlight */
+#define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x0090
+
+struct __ec_align1 ec_params_switch_enable_backlight {
+	uint8_t enabled;
+};
+
+/* Enable/disable WLAN/Bluetooth */
+#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x0091
+#define EC_VER_SWITCH_ENABLE_WIRELESS 1
+
+/* Version 0 params; no response */
+struct __ec_align1 ec_params_switch_enable_wireless_v0 {
+	uint8_t enabled;
+};
+
+/* Version 1 params */
+struct __ec_align1 ec_params_switch_enable_wireless_v1 {
+	/* Flags to enable now */
+	uint8_t now_flags;
+
+	/* Which flags to copy from now_flags */
+	uint8_t now_mask;
+
+	/*
+	 * Flags to leave enabled in S3, if they're on at the S0->S3
+	 * transition.  (Other flags will be disabled by the S0->S3
+	 * transition.)
+	 */
+	uint8_t suspend_flags;
+
+	/* Which flags to copy from suspend_flags */
+	uint8_t suspend_mask;
+};
+
+/* Version 1 response */
+struct __ec_align1 ec_response_switch_enable_wireless_v1 {
+	/* Flags to enable now */
+	uint8_t now_flags;
+
+	/* Flags to leave enabled in S3 */
+	uint8_t suspend_flags;
+};
+
+/*****************************************************************************/
+/* GPIO commands. Only available on EC if write protect has been disabled. */
+
+/* Set GPIO output value */
+#define EC_CMD_GPIO_SET 0x0092
+
+struct __ec_align1 ec_params_gpio_set {
+	char name[32];
+	uint8_t val;
+};
+
+/* Get GPIO value */
+#define EC_CMD_GPIO_GET 0x0093
+
+/* Version 0 of input params and response */
+struct __ec_align1 ec_params_gpio_get {
+	char name[32];
+};
+
+struct __ec_align1 ec_response_gpio_get {
+	uint8_t val;
+};
+
+/* Version 1 of input params and response */
+struct __ec_align1 ec_params_gpio_get_v1 {
+	uint8_t subcmd;
+	union {
+		struct __ec_align1 {
+			char name[32];
+		} get_value_by_name;
+		struct __ec_align1 {
+			uint8_t index;
+		} get_info;
+	};
+};
+
+struct __ec_todo_packed ec_response_gpio_get_v1 {
+	union {
+		struct __ec_align1 {
+			uint8_t val;
+		} get_value_by_name, get_count;
+		struct __ec_todo_unpacked {
+			uint8_t val;
+			char name[32];
+			uint32_t flags;
+		} get_info;
+	};
+};
+
+enum gpio_get_subcmd {
+	EC_GPIO_GET_BY_NAME = 0,
+	EC_GPIO_GET_COUNT = 1,
+	EC_GPIO_GET_INFO = 2,
+};
+
+/*****************************************************************************/
+/* I2C commands. Only available when flash write protect is unlocked. */
+
+/*
+ * CAUTION: These commands are deprecated, and are not supported anymore in EC
+ * builds >= 8398.0.0 (see crosbug.com/p/23570).
+ *
+ * Use EC_CMD_I2C_PASSTHRU instead.
+ */
+
+/* Read I2C bus */
+#define EC_CMD_I2C_READ 0x0094
+
+struct __ec_align_size1 ec_params_i2c_read {
+	uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
+	uint8_t read_size; /* Either 8 or 16. */
+	uint8_t port;
+	uint8_t offset;
+};
+
+struct __ec_align2 ec_response_i2c_read {
+	uint16_t data;
+};
+
+/* Write I2C bus */
+#define EC_CMD_I2C_WRITE 0x0095
+
+struct __ec_align_size1 ec_params_i2c_write {
+	uint16_t data;
+	uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
+	uint8_t write_size; /* Either 8 or 16. */
+	uint8_t port;
+	uint8_t offset;
+};
+
+/*****************************************************************************/
+/* Charge state commands. Only available when flash write protect unlocked. */
+
+/* Force charge state machine to stop charging the battery or force it to
+ * discharge the battery.
+ */
+#define EC_CMD_CHARGE_CONTROL 0x0096
+#define EC_VER_CHARGE_CONTROL 1
+
+enum ec_charge_control_mode {
+	CHARGE_CONTROL_NORMAL = 0,
+	CHARGE_CONTROL_IDLE,
+	CHARGE_CONTROL_DISCHARGE,
+};
+
+struct __ec_align4 ec_params_charge_control {
+	uint32_t mode;  /* enum charge_control_mode */
+};
+
+/*****************************************************************************/
+/* Console commands. Only available when flash write protect is unlocked. */
+
+/* Snapshot console output buffer for use by EC_CMD_CONSOLE_READ. */
+#define EC_CMD_CONSOLE_SNAPSHOT 0x0097
+
+/*
+ * Read data from the saved snapshot. If the subcmd parameter is
+ * CONSOLE_READ_NEXT, this will return data starting from the beginning of
+ * the latest snapshot. If it is CONSOLE_READ_RECENT, it will start from the
+ * end of the previous snapshot.
+ *
+ * The params are only looked at in version >= 1 of this command. Prior
+ * versions will just default to CONSOLE_READ_NEXT behavior.
+ *
+ * Response is null-terminated string.  Empty string, if there is no more
+ * remaining output.
+ */
+#define EC_CMD_CONSOLE_READ 0x0098
+
+enum ec_console_read_subcmd {
+	CONSOLE_READ_NEXT = 0,
+	CONSOLE_READ_RECENT
+};
+
+struct __ec_align1 ec_params_console_read_v1 {
+	uint8_t subcmd; /* enum ec_console_read_subcmd */
+};
+
+/*****************************************************************************/
+
+/*
+ * Cut off battery power immediately or after the host has shut down.
+ *
+ * return EC_RES_INVALID_COMMAND if unsupported by a board/battery.
+ *	  EC_RES_SUCCESS if the command was successful.
+ *	  EC_RES_ERROR if the cut off command failed.
+ */
+#define EC_CMD_BATTERY_CUT_OFF 0x0099
+
+#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN	(1 << 0)
+
+struct __ec_align1 ec_params_battery_cutoff {
+	uint8_t flags;
+};
+
+/*****************************************************************************/
+/* USB port mux control. */
+
+/*
+ * Switch USB mux or return to automatic switching.
+ */
+#define EC_CMD_USB_MUX 0x009A
+
+struct __ec_align1 ec_params_usb_mux {
+	uint8_t mux;
+};
+
+/*****************************************************************************/
+/* LDOs / FETs control. */
+
+enum ec_ldo_state {
+	EC_LDO_STATE_OFF = 0,	/* the LDO / FET is shut down */
+	EC_LDO_STATE_ON = 1,	/* the LDO / FET is ON / providing power */
+};
+
+/*
+ * Switch on/off a LDO.
+ */
+#define EC_CMD_LDO_SET 0x009B
+
+struct __ec_align1 ec_params_ldo_set {
+	uint8_t index;
+	uint8_t state;
+};
+
+/*
+ * Get LDO state.
+ */
+#define EC_CMD_LDO_GET 0x009C
+
+struct __ec_align1 ec_params_ldo_get {
+	uint8_t index;
+};
+
+struct __ec_align1 ec_response_ldo_get {
+	uint8_t state;
+};
+
+/*****************************************************************************/
+/* Power info. */
+
+/*
+ * Get power info.
+ */
+#define EC_CMD_POWER_INFO 0x009D
+
+struct __ec_align4 ec_response_power_info {
+	uint32_t usb_dev_type;
+	uint16_t voltage_ac;
+	uint16_t voltage_system;
+	uint16_t current_system;
+	uint16_t usb_current_limit;
+};
+
+/*****************************************************************************/
+/* I2C passthru command */
+
+#define EC_CMD_I2C_PASSTHRU 0x009E
+
+/* Read data; if not present, message is a write */
+#define EC_I2C_FLAG_READ	(1 << 15)
+
+/* Mask for address */
+#define EC_I2C_ADDR_MASK	0x3ff
+
+#define EC_I2C_STATUS_NAK	(1 << 0) /* Transfer was not acknowledged */
+#define EC_I2C_STATUS_TIMEOUT	(1 << 1) /* Timeout during transfer */
+
+/* Any error */
+#define EC_I2C_STATUS_ERROR	(EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
+
+struct __ec_align2 ec_params_i2c_passthru_msg {
+	uint16_t addr_flags;	/* I2C slave address (7 or 10 bits) and flags */
+	uint16_t len;		/* Number of bytes to read or write */
+};
+
+struct __ec_align2 ec_params_i2c_passthru {
+	uint8_t port;		/* I2C port number */
+	uint8_t num_msgs;	/* Number of messages */
+	struct ec_params_i2c_passthru_msg msg[];
+	/* Data to write for all messages is concatenated here */
+};
+
+struct __ec_align1 ec_response_i2c_passthru {
+	uint8_t i2c_status;	/* Status flags (EC_I2C_STATUS_...) */
+	uint8_t num_msgs;	/* Number of messages processed */
+	uint8_t data[];		/* Data read by messages concatenated here */
+};
+
+/*****************************************************************************/
+/* Power button hang detect */
+
+#define EC_CMD_HANG_DETECT 0x009F
+
+/* Reasons to start hang detection timer */
+/* Power button pressed */
+#define EC_HANG_START_ON_POWER_PRESS  (1 << 0)
+
+/* Lid closed */
+#define EC_HANG_START_ON_LID_CLOSE    (1 << 1)
+
+ /* Lid opened */
+#define EC_HANG_START_ON_LID_OPEN     (1 << 2)
+
+/* Start of AP S3->S0 transition (booting or resuming from suspend) */
+#define EC_HANG_START_ON_RESUME       (1 << 3)
+
+/* Reasons to cancel hang detection */
+
+/* Power button released */
+#define EC_HANG_STOP_ON_POWER_RELEASE (1 << 8)
+
+/* Any host command from AP received */
+#define EC_HANG_STOP_ON_HOST_COMMAND  (1 << 9)
+
+/* Stop on end of AP S0->S3 transition (suspending or shutting down) */
+#define EC_HANG_STOP_ON_SUSPEND       (1 << 10)
+
+/*
+ * If this flag is set, all the other fields are ignored, and the hang detect
+ * timer is started.  This provides the AP a way to start the hang timer
+ * without reconfiguring any of the other hang detect settings.  Note that
+ * you must previously have configured the timeouts.
+ */
+#define EC_HANG_START_NOW             (1 << 30)
+
+/*
+ * If this flag is set, all the other fields are ignored (including
+ * EC_HANG_START_NOW).  This provides the AP a way to stop the hang timer
+ * without reconfiguring any of the other hang detect settings.
+ */
+#define EC_HANG_STOP_NOW              (1 << 31)
+
+struct __ec_align4 ec_params_hang_detect {
+	/* Flags; see EC_HANG_* */
+	uint32_t flags;
+
+	/* Timeout in msec before generating host event, if enabled */
+	uint16_t host_event_timeout_msec;
+
+	/* Timeout in msec before generating warm reboot, if enabled */
+	uint16_t warm_reboot_timeout_msec;
+};
+
+/*****************************************************************************/
+/* Commands for battery charging */
+
+/*
+ * This is the single catch-all host command to exchange data regarding the
+ * charge state machine (v2 and up).
+ */
+#define EC_CMD_CHARGE_STATE 0x00A0
+
+/* Subcommands for this host command */
+enum charge_state_command {
+	CHARGE_STATE_CMD_GET_STATE,
+	CHARGE_STATE_CMD_GET_PARAM,
+	CHARGE_STATE_CMD_SET_PARAM,
+	CHARGE_STATE_NUM_CMDS
+};
+
+/*
+ * Known param numbers are defined here. Ranges are reserved for board-specific
+ * params, which are handled by the particular implementations.
+ */
+enum charge_state_params {
+	CS_PARAM_CHG_VOLTAGE,	      /* charger voltage limit */
+	CS_PARAM_CHG_CURRENT,	      /* charger current limit */
+	CS_PARAM_CHG_INPUT_CURRENT,   /* charger input current limit */
+	CS_PARAM_CHG_STATUS,	      /* charger-specific status */
+	CS_PARAM_CHG_OPTION,	      /* charger-specific options */
+	CS_PARAM_LIMIT_POWER,	      /*
+				       * Check if power is limited due to
+				       * low battery and / or a weak external
+				       * charger. READ ONLY.
+				       */
+	/* How many so far? */
+	CS_NUM_BASE_PARAMS,
+
+	/* Range for CONFIG_CHARGER_PROFILE_OVERRIDE params */
+	CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000,
+	CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff,
+
+	/* Other custom param ranges go here... */
+};
+
+struct __ec_todo_packed ec_params_charge_state {
+	uint8_t cmd;				/* enum charge_state_command */
+	union {
+		struct __ec_align1 {
+			/* no args */
+		} get_state;
+
+		struct __ec_todo_unpacked {
+			uint32_t param;		/* enum charge_state_param */
+		} get_param;
+
+		struct __ec_todo_unpacked {
+			uint32_t param;		/* param to set */
+			uint32_t value;		/* value to set */
+		} set_param;
+	};
+};
+
+struct __ec_align4 ec_response_charge_state {
+	union {
+		struct __ec_align4 {
+			int ac;
+			int chg_voltage;
+			int chg_current;
+			int chg_input_current;
+			int batt_state_of_charge;
+		} get_state;
+
+		struct __ec_align4 {
+			uint32_t value;
+		} get_param;
+		struct __ec_align4 {
+			/* no return values */
+		} set_param;
+	};
+};
+
+
+/*
+ * Set maximum battery charging current.
+ */
+#define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1
+
+struct __ec_align4 ec_params_current_limit {
+	uint32_t limit; /* in mA */
+};
+
+/*
+ * Set maximum external voltage / current.
+ */
+#define EC_CMD_EXTERNAL_POWER_LIMIT 0x00A2
+
+/* Command v0 is used only on Spring and is obsolete + unsupported */
+struct __ec_align2 ec_params_external_power_limit_v1 {
+	uint16_t current_lim; /* in mA, or EC_POWER_LIMIT_NONE to clear limit */
+	uint16_t voltage_lim; /* in mV, or EC_POWER_LIMIT_NONE to clear limit */
+};
+
+#define EC_POWER_LIMIT_NONE 0xffff
+
+/*
+ * Set maximum voltage & current of a dedicated charge port
+ */
+#define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3
+
+struct __ec_align2 ec_params_dedicated_charger_limit {
+	uint16_t current_lim; /* in mA */
+	uint16_t voltage_lim; /* in mV */
+};
+
+/*****************************************************************************/
+/* Hibernate/Deep Sleep Commands */
+
+/* Set the delay before going into hibernation. */
+#define EC_CMD_HIBERNATION_DELAY 0x00A8
+
+struct __ec_align4 ec_params_hibernation_delay {
+	/*
+	 * Seconds to wait in G3 before hibernate.  Pass in 0 to read the
+	 * current settings without changing them.
+	 */
+	uint32_t seconds;
+};
+
+struct __ec_align4 ec_response_hibernation_delay {
+	/*
+	 * The current time in seconds in which the system has been in the G3
+	 * state.  This value is reset if the EC transitions out of G3.
+	 */
+	uint32_t time_g3;
+
+	/*
+	 * The current time remaining in seconds until the EC should hibernate.
+	 * This value is also reset if the EC transitions out of G3.
+	 */
+	uint32_t time_remaining;
+
+	/*
+	 * The current time in seconds that the EC should wait in G3 before
+	 * hibernating.
+	 */
+	uint32_t hibernate_delay;
+};
+
+/* Inform the EC when entering a sleep state */
+#define EC_CMD_HOST_SLEEP_EVENT 0x00A9
+
+enum host_sleep_event {
+	HOST_SLEEP_EVENT_S3_SUSPEND   = 1,
+	HOST_SLEEP_EVENT_S3_RESUME    = 2,
+	HOST_SLEEP_EVENT_S0IX_SUSPEND = 3,
+	HOST_SLEEP_EVENT_S0IX_RESUME  = 4
+};
+
+struct __ec_align1 ec_params_host_sleep_event {
+	uint8_t sleep_event;
+};
+
+/*****************************************************************************/
+/* Device events */
+#define EC_CMD_DEVICE_EVENT 0x00AA
+
+enum ec_device_event {
+	EC_DEVICE_EVENT_TRACKPAD,
+	EC_DEVICE_EVENT_DSP,
+	EC_DEVICE_EVENT_WIFI,
+};
+
+enum ec_device_event_param {
+	/* Get and clear pending device events */
+	EC_DEVICE_EVENT_PARAM_GET_CURRENT_EVENTS,
+	/* Get device event mask */
+	EC_DEVICE_EVENT_PARAM_GET_ENABLED_EVENTS,
+	/* Set device event mask */
+	EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS,
+};
+
+#define EC_DEVICE_EVENT_MASK(event_code) (1UL << (event_code % 32))
+
+struct __ec_align_size1 ec_params_device_event {
+	uint32_t event_mask;
+	uint8_t param;
+};
+
+struct __ec_align4 ec_response_device_event {
+	uint32_t event_mask;
+};
+
+/*****************************************************************************/
+/* Smart battery pass-through */
+
+/* Get / Set 16-bit smart battery registers */
+#define EC_CMD_SB_READ_WORD   0x00B0
+#define EC_CMD_SB_WRITE_WORD  0x00B1
+
+/* Get / Set string smart battery parameters
+ * formatted as SMBUS "block".
+ */
+#define EC_CMD_SB_READ_BLOCK  0x00B2
+#define EC_CMD_SB_WRITE_BLOCK 0x00B3
+
+struct __ec_align1 ec_params_sb_rd {
+	uint8_t reg;
+};
+
+struct __ec_align2 ec_response_sb_rd_word {
+	uint16_t value;
+};
+
+struct __ec_align1 ec_params_sb_wr_word {
+	uint8_t reg;
+	uint16_t value;
+};
+
+struct __ec_align1 ec_response_sb_rd_block {
+	uint8_t data[32];
+};
+
+struct __ec_align1 ec_params_sb_wr_block {
+	uint8_t reg;
+	uint16_t data[32];
+};
+
+/*****************************************************************************/
+/* Battery vendor parameters
+ *
+ * Get or set vendor-specific parameters in the battery. Implementations may
+ * differ between boards or batteries. On a set operation, the response
+ * contains the actual value set, which may be rounded or clipped from the
+ * requested value.
+ */
+
+#define EC_CMD_BATTERY_VENDOR_PARAM 0x00B4
+
+enum ec_battery_vendor_param_mode {
+	BATTERY_VENDOR_PARAM_MODE_GET = 0,
+	BATTERY_VENDOR_PARAM_MODE_SET,
+};
+
+struct __ec_align_size1 ec_params_battery_vendor_param {
+	uint32_t param;
+	uint32_t value;
+	uint8_t mode;
+};
+
+struct __ec_align4 ec_response_battery_vendor_param {
+	uint32_t value;
+};
+
+/*****************************************************************************/
+/*
+ * Smart Battery Firmware Update Commands
+ */
+#define EC_CMD_SB_FW_UPDATE 0x00B5
+
+enum ec_sb_fw_update_subcmd {
+	EC_SB_FW_UPDATE_PREPARE  = 0x0,
+	EC_SB_FW_UPDATE_INFO     = 0x1, /*query sb info */
+	EC_SB_FW_UPDATE_BEGIN    = 0x2, /*check if protected */
+	EC_SB_FW_UPDATE_WRITE    = 0x3, /*check if protected */
+	EC_SB_FW_UPDATE_END      = 0x4,
+	EC_SB_FW_UPDATE_STATUS   = 0x5,
+	EC_SB_FW_UPDATE_PROTECT  = 0x6,
+	EC_SB_FW_UPDATE_MAX      = 0x7,
+};
+
+#define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32
+#define SB_FW_UPDATE_CMD_STATUS_SIZE 2
+#define SB_FW_UPDATE_CMD_INFO_SIZE 8
+
+struct __ec_align4 ec_sb_fw_update_header {
+	uint16_t subcmd;  /* enum ec_sb_fw_update_subcmd */
+	uint16_t fw_id;   /* firmware id */
+};
+
+struct __ec_align4 ec_params_sb_fw_update {
+	struct ec_sb_fw_update_header hdr;
+	union {
+		/* EC_SB_FW_UPDATE_PREPARE  = 0x0 */
+		/* EC_SB_FW_UPDATE_INFO     = 0x1 */
+		/* EC_SB_FW_UPDATE_BEGIN    = 0x2 */
+		/* EC_SB_FW_UPDATE_END      = 0x4 */
+		/* EC_SB_FW_UPDATE_STATUS   = 0x5 */
+		/* EC_SB_FW_UPDATE_PROTECT  = 0x6 */
+		struct __ec_align4 {
+			/* no args */
+		} dummy;
+
+		/* EC_SB_FW_UPDATE_WRITE    = 0x3 */
+		struct __ec_align4 {
+			uint8_t  data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE];
+		} write;
+	};
+};
+
+struct __ec_align1 ec_response_sb_fw_update {
+	union {
+		/* EC_SB_FW_UPDATE_INFO     = 0x1 */
+		struct __ec_align1 {
+			uint8_t data[SB_FW_UPDATE_CMD_INFO_SIZE];
+		} info;
+
+		/* EC_SB_FW_UPDATE_STATUS   = 0x5 */
+		struct __ec_align1 {
+			uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE];
+		} status;
+	};
+};
+
+/*
+ * Entering Verified Boot Mode Command
+ * Default mode is VBOOT_MODE_NORMAL if EC did not receive this command.
+ * Valid Modes are: normal, developer, and recovery.
+ */
+#define EC_CMD_ENTERING_MODE 0x00B6
+
+struct __ec_align4 ec_params_entering_mode {
+	int vboot_mode;
+};
+
+#define VBOOT_MODE_NORMAL    0
+#define VBOOT_MODE_DEVELOPER 1
+#define VBOOT_MODE_RECOVERY  2
+
+/*****************************************************************************/
+/*
+ * I2C passthru protection command: Protects I2C tunnels against access on
+ * certain addresses (board-specific).
+ */
+#define EC_CMD_I2C_PASSTHRU_PROTECT 0x00B7
+
+enum ec_i2c_passthru_protect_subcmd {
+	EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0x0,
+	EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1,
+};
+
+struct __ec_align1 ec_params_i2c_passthru_protect {
+	uint8_t subcmd;
+	uint8_t port;		/* I2C port number */
+};
+
+struct __ec_align1 ec_response_i2c_passthru_protect {
+	uint8_t status;		/* Status flags (0: unlocked, 1: locked) */
+};
+
+/*****************************************************************************/
+/* System commands */
+
+/*
+ * TODO(crosbug.com/p/23747): This is a confusing name, since it doesn't
+ * necessarily reboot the EC.  Rename to "image" or something similar?
+ */
+#define EC_CMD_REBOOT_EC 0x00D2
+
+/* Command */
+enum ec_reboot_cmd {
+	EC_REBOOT_CANCEL = 0,        /* Cancel a pending reboot */
+	EC_REBOOT_JUMP_RO = 1,       /* Jump to RO without rebooting */
+	EC_REBOOT_JUMP_RW = 2,       /* Jump to RW without rebooting */
+	/* (command 3 was jump to RW-B) */
+	EC_REBOOT_COLD = 4,          /* Cold-reboot */
+	EC_REBOOT_DISABLE_JUMP = 5,  /* Disable jump until next reboot */
+	EC_REBOOT_HIBERNATE = 6,     /* Hibernate EC */
+	EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_OFF flag */
+};
+
+/* Flags for ec_params_reboot_ec.reboot_flags */
+#define EC_REBOOT_FLAG_RESERVED0      (1 << 0)  /* Was recovery request */
+#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1)  /* Reboot after AP shutdown */
+#define EC_REBOOT_FLAG_SWITCH_RW_SLOT (1 << 2)  /* Switch RW slot */
+
+struct __ec_align1 ec_params_reboot_ec {
+	uint8_t cmd;           /* enum ec_reboot_cmd */
+	uint8_t flags;         /* See EC_REBOOT_FLAG_* */
+};
+
+/*
+ * Get information on last EC panic.
+ *
+ * Returns variable-length platform-dependent panic information.  See panic.h
+ * for details.
+ */
+#define EC_CMD_GET_PANIC_INFO 0x00D3
+
+/*****************************************************************************/
+/*
+ * Special commands
+ *
+ * These do not follow the normal rules for commands.  See each command for
+ * details.
+ */
+
+/*
+ * Reboot NOW
+ *
+ * This command will work even when the EC LPC interface is busy, because the
+ * reboot command is processed at interrupt level.  Note that when the EC
+ * reboots, the host will reboot too, so there is no response to this command.
+ *
+ * Use EC_CMD_REBOOT_EC to reboot the EC more politely.
+ */
+#define EC_CMD_REBOOT 0x00D1  /* Think "die" */
+
+/*
+ * Resend last response (not supported on LPC).
+ *
+ * Returns EC_RES_UNAVAILABLE if there is no response available - for example,
+ * there was no previous command, or the previous command's response was too
+ * big to save.
+ */
+#define EC_CMD_RESEND_RESPONSE 0x00DB
+
+/*
+ * This header byte on a command indicate version 0. Any header byte less
+ * than this means that we are talking to an old EC which doesn't support
+ * versioning. In that case, we assume version 0.
+ *
+ * Header bytes greater than this indicate a later version. For example,
+ * EC_CMD_VERSION0 + 1 means we are using version 1.
+ *
+ * The old EC interface must not use commands 0xdc or higher.
+ */
+#define EC_CMD_VERSION0 0x00DC
+
+/*****************************************************************************/
+/*
+ * PD commands
+ *
+ * These commands are for PD MCU communication.
+ */
+
+/* EC to PD MCU exchange status command */
+#define EC_CMD_PD_EXCHANGE_STATUS 0x0100
+#define EC_VER_PD_EXCHANGE_STATUS 2
+
+enum pd_charge_state {
+	PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */
+	PD_CHARGE_NONE,          /* No charging allowed */
+	PD_CHARGE_5V,            /* 5V charging only */
+	PD_CHARGE_MAX            /* Charge at max voltage */
+};
+
+/* Status of EC being sent to PD */
+#define EC_STATUS_HIBERNATING	(1 << 0)
+
+struct __ec_align1 ec_params_pd_status {
+	uint8_t status;       /* EC status */
+	int8_t batt_soc;      /* battery state of charge */
+	uint8_t charge_state; /* charging state (from enum pd_charge_state) */
+};
+
+/* Status of PD being sent back to EC */
+#define PD_STATUS_HOST_EVENT      (1 << 0) /* Forward host event to AP */
+#define PD_STATUS_IN_RW           (1 << 1) /* Running RW image */
+#define PD_STATUS_JUMPED_TO_IMAGE (1 << 2) /* Current image was jumped to */
+#define PD_STATUS_TCPC_ALERT_0    (1 << 3) /* Alert active in port 0 TCPC */
+#define PD_STATUS_TCPC_ALERT_1    (1 << 4) /* Alert active in port 1 TCPC */
+#define PD_STATUS_TCPC_ALERT_2    (1 << 5) /* Alert active in port 2 TCPC */
+#define PD_STATUS_TCPC_ALERT_3    (1 << 6) /* Alert active in port 3 TCPC */
+#define PD_STATUS_EC_INT_ACTIVE  (PD_STATUS_TCPC_ALERT_0 | \
+				      PD_STATUS_TCPC_ALERT_1 | \
+				      PD_STATUS_HOST_EVENT)
+struct __ec_align_size1 ec_response_pd_status {
+	uint32_t curr_lim_ma;       /* input current limit */
+	uint16_t status;            /* PD MCU status */
+	int8_t active_charge_port;  /* active charging port */
+};
+
+/* AP to PD MCU host event status command, cleared on read */
+#define EC_CMD_PD_HOST_EVENT_STATUS 0x0104
+
+/* PD MCU host event status bits */
+#define PD_EVENT_UPDATE_DEVICE     (1 << 0)
+#define PD_EVENT_POWER_CHANGE      (1 << 1)
+#define PD_EVENT_IDENTITY_RECEIVED (1 << 2)
+#define PD_EVENT_DATA_SWAP         (1 << 3)
+struct __ec_align4 ec_response_host_event_status {
+	uint32_t status;      /* PD MCU host event status */
+};
+
+/* Set USB type-C port role and muxes */
+#define EC_CMD_USB_PD_CONTROL 0x0101
+
+enum usb_pd_control_role {
+	USB_PD_CTRL_ROLE_NO_CHANGE = 0,
+	USB_PD_CTRL_ROLE_TOGGLE_ON = 1, /* == AUTO */
+	USB_PD_CTRL_ROLE_TOGGLE_OFF = 2,
+	USB_PD_CTRL_ROLE_FORCE_SINK = 3,
+	USB_PD_CTRL_ROLE_FORCE_SOURCE = 4,
+	USB_PD_CTRL_ROLE_COUNT
+};
+
+enum usb_pd_control_mux {
+	USB_PD_CTRL_MUX_NO_CHANGE = 0,
+	USB_PD_CTRL_MUX_NONE = 1,
+	USB_PD_CTRL_MUX_USB = 2,
+	USB_PD_CTRL_MUX_DP = 3,
+	USB_PD_CTRL_MUX_DOCK = 4,
+	USB_PD_CTRL_MUX_AUTO = 5,
+	USB_PD_CTRL_MUX_COUNT
+};
+
+enum usb_pd_control_swap {
+	USB_PD_CTRL_SWAP_NONE = 0,
+	USB_PD_CTRL_SWAP_DATA = 1,
+	USB_PD_CTRL_SWAP_POWER = 2,
+	USB_PD_CTRL_SWAP_VCONN = 3,
+	USB_PD_CTRL_SWAP_COUNT
+};
+
+struct __ec_align1 ec_params_usb_pd_control {
+	uint8_t port;
+	uint8_t role;
+	uint8_t mux;
+	uint8_t swap;
+};
+
+#define PD_CTRL_RESP_ENABLED_COMMS      (1 << 0) /* Communication enabled */
+#define PD_CTRL_RESP_ENABLED_CONNECTED  (1 << 1) /* Device connected */
+#define PD_CTRL_RESP_ENABLED_PD_CAPABLE (1 << 2) /* Partner is PD capable */
+
+#define PD_CTRL_RESP_ROLE_POWER         (1 << 0) /* 0=SNK/1=SRC */
+#define PD_CTRL_RESP_ROLE_DATA          (1 << 1) /* 0=UFP/1=DFP */
+#define PD_CTRL_RESP_ROLE_VCONN         (1 << 2) /* Vconn status */
+#define PD_CTRL_RESP_ROLE_DR_POWER      (1 << 3) /* Partner is dualrole power */
+#define PD_CTRL_RESP_ROLE_DR_DATA       (1 << 4) /* Partner is dualrole data */
+#define PD_CTRL_RESP_ROLE_USB_COMM      (1 << 5) /* Partner USB comm capable */
+#define PD_CTRL_RESP_ROLE_EXT_POWERED   (1 << 6) /* Partner externally powerd */
+
+struct __ec_align1 ec_response_usb_pd_control {
+	uint8_t enabled;
+	uint8_t role;
+	uint8_t polarity;
+	uint8_t state;
+};
+
+struct __ec_align1 ec_response_usb_pd_control_v1 {
+	uint8_t enabled;
+	uint8_t role;
+	uint8_t polarity;
+	char state[32];
+};
+
+#define EC_CMD_USB_PD_PORTS 0x0102
+
+/* Maximum number of PD ports on a device, num_ports will be <= this */
+#define EC_USB_PD_MAX_PORTS 8
+
+struct __ec_align1 ec_response_usb_pd_ports {
+	uint8_t num_ports;
+};
+
+#define EC_CMD_USB_PD_POWER_INFO 0x0103
+
+#define PD_POWER_CHARGING_PORT 0xff
+struct __ec_align1 ec_params_usb_pd_power_info {
+	uint8_t port;
+};
+
+enum usb_chg_type {
+	USB_CHG_TYPE_NONE,
+	USB_CHG_TYPE_PD,
+	USB_CHG_TYPE_C,
+	USB_CHG_TYPE_PROPRIETARY,
+	USB_CHG_TYPE_BC12_DCP,
+	USB_CHG_TYPE_BC12_CDP,
+	USB_CHG_TYPE_BC12_SDP,
+	USB_CHG_TYPE_OTHER,
+	USB_CHG_TYPE_VBUS,
+	USB_CHG_TYPE_UNKNOWN,
+};
+enum usb_power_roles {
+	USB_PD_PORT_POWER_DISCONNECTED,
+	USB_PD_PORT_POWER_SOURCE,
+	USB_PD_PORT_POWER_SINK,
+	USB_PD_PORT_POWER_SINK_NOT_CHARGING,
+};
+
+struct __ec_align2 usb_chg_measures {
+	uint16_t voltage_max;
+	uint16_t voltage_now;
+	uint16_t current_max;
+	uint16_t current_lim;
+};
+
+struct __ec_align4 ec_response_usb_pd_power_info {
+	uint8_t role;
+	uint8_t type;
+	uint8_t dualrole;
+	uint8_t reserved1;
+	struct usb_chg_measures meas;
+	uint32_t max_power;
+};
+
+/* Write USB-PD device FW */
+#define EC_CMD_USB_PD_FW_UPDATE 0x0110
+
+enum usb_pd_fw_update_cmds {
+	USB_PD_FW_REBOOT,
+	USB_PD_FW_FLASH_ERASE,
+	USB_PD_FW_FLASH_WRITE,
+	USB_PD_FW_ERASE_SIG,
+};
+
+struct __ec_align4 ec_params_usb_pd_fw_update {
+	uint16_t dev_id;
+	uint8_t cmd;
+	uint8_t port;
+	uint32_t size;     /* Size to write in bytes */
+	/* Followed by data to write */
+};
+
+/* Write USB-PD Accessory RW_HASH table entry */
+#define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111
+/* RW hash is first 20 bytes of SHA-256 of RW section */
+#define PD_RW_HASH_SIZE 20
+struct __ec_align1 ec_params_usb_pd_rw_hash_entry {
+	uint16_t dev_id;
+	uint8_t dev_rw_hash[PD_RW_HASH_SIZE];
+	uint8_t reserved;        /* For alignment of current_image
+				  * TODO(rspangler) but it's not aligned!
+				  * Should have been reserved[2]. */
+	uint32_t current_image;  /* One of ec_current_image */
+};
+
+/* Read USB-PD Accessory info */
+#define EC_CMD_USB_PD_DEV_INFO 0x0112
+
+struct __ec_align1 ec_params_usb_pd_info_request {
+	uint8_t port;
+};
+
+/* Read USB-PD Device discovery info */
+#define EC_CMD_USB_PD_DISCOVERY 0x0113
+struct __ec_align_size1 ec_params_usb_pd_discovery_entry {
+	uint16_t vid;  /* USB-IF VID */
+	uint16_t pid;  /* USB-IF PID */
+	uint8_t ptype; /* product type (hub,periph,cable,ama) */
+};
+
+/* Override default charge behavior */
+#define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114
+
+/* Negative port parameters have special meaning */
+enum usb_pd_override_ports {
+	OVERRIDE_DONT_CHARGE = -2,
+	OVERRIDE_OFF = -1,
+	/* [0, CONFIG_USB_PD_PORT_COUNT): Port# */
+};
+
+struct __ec_align2 ec_params_charge_port_override {
+	int16_t override_port; /* Override port# */
+};
+
+/* Read (and delete) one entry of PD event log */
+#define EC_CMD_PD_GET_LOG_ENTRY 0x0115
+
+struct __ec_align4 ec_response_pd_log {
+	uint32_t timestamp; /* relative timestamp in milliseconds */
+	uint8_t type;       /* event type : see PD_EVENT_xx below */
+	uint8_t size_port;  /* [7:5] port number [4:0] payload size in bytes */
+	uint16_t data;      /* type-defined data payload */
+	uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */
+};
+
+
+/* The timestamp is the microsecond counter shifted to get about a ms. */
+#define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */
+
+#define PD_LOG_SIZE_MASK  0x1f
+#define PD_LOG_PORT_MASK  0xe0
+#define PD_LOG_PORT_SHIFT    5
+#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \
+				      ((size) & PD_LOG_SIZE_MASK))
+#define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT)
+#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK)
+
+/* PD event log : entry types */
+/* PD MCU events */
+#define PD_EVENT_MCU_BASE       0x00
+#define PD_EVENT_MCU_CHARGE             (PD_EVENT_MCU_BASE+0)
+#define PD_EVENT_MCU_CONNECT            (PD_EVENT_MCU_BASE+1)
+/* Reserved for custom board event */
+#define PD_EVENT_MCU_BOARD_CUSTOM       (PD_EVENT_MCU_BASE+2)
+/* PD generic accessory events */
+#define PD_EVENT_ACC_BASE       0x20
+#define PD_EVENT_ACC_RW_FAIL   (PD_EVENT_ACC_BASE+0)
+#define PD_EVENT_ACC_RW_ERASE  (PD_EVENT_ACC_BASE+1)
+/* PD power supply events */
+#define PD_EVENT_PS_BASE        0x40
+#define PD_EVENT_PS_FAULT      (PD_EVENT_PS_BASE+0)
+/* PD video dongles events */
+#define PD_EVENT_VIDEO_BASE     0x60
+#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0)
+#define PD_EVENT_VIDEO_CODEC   (PD_EVENT_VIDEO_BASE+1)
+/* Returned in the "type" field, when there is no entry available */
+#define PD_EVENT_NO_ENTRY       0xff
+
+/*
+ * PD_EVENT_MCU_CHARGE event definition :
+ * the payload is "struct usb_chg_measures"
+ * the data field contains the port state flags as defined below :
+ */
+/* Port partner is a dual role device */
+#define CHARGE_FLAGS_DUAL_ROLE         (1 << 15)
+/* Port is the pending override port */
+#define CHARGE_FLAGS_DELAYED_OVERRIDE  (1 << 14)
+/* Port is the override port */
+#define CHARGE_FLAGS_OVERRIDE          (1 << 13)
+/* Charger type */
+#define CHARGE_FLAGS_TYPE_SHIFT               3
+#define CHARGE_FLAGS_TYPE_MASK       (0xf << CHARGE_FLAGS_TYPE_SHIFT)
+/* Power delivery role */
+#define CHARGE_FLAGS_ROLE_MASK         (7 <<  0)
+
+/*
+ * PD_EVENT_PS_FAULT data field flags definition :
+ */
+#define PS_FAULT_OCP                          1
+#define PS_FAULT_FAST_OCP                     2
+#define PS_FAULT_OVP                          3
+#define PS_FAULT_DISCH                        4
+
+/*
+ * PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info".
+ */
+struct __ec_align4 mcdp_version {
+	uint8_t major;
+	uint8_t minor;
+	uint16_t build;
+};
+
+struct __ec_align4 mcdp_info {
+	uint8_t family[2];
+	uint8_t chipid[2];
+	struct mcdp_version irom;
+	struct mcdp_version fw;
+};
+
+/* struct mcdp_info field decoding */
+#define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1])
+#define MCDP_FAMILY(family) ((family[0] << 8) | family[1])
+
+/* Get/Set USB-PD Alternate mode info */
+#define EC_CMD_USB_PD_GET_AMODE 0x0116
+struct __ec_align_size1 ec_params_usb_pd_get_mode_request {
+	uint16_t svid_idx; /* SVID index to get */
+	uint8_t port;      /* port */
+};
+
+struct __ec_align4 ec_params_usb_pd_get_mode_response {
+	uint16_t svid;   /* SVID */
+	uint16_t opos;    /* Object Position */
+	uint32_t vdo[6]; /* Mode VDOs */
+};
+
+#define EC_CMD_USB_PD_SET_AMODE 0x0117
+
+enum pd_mode_cmd {
+	PD_EXIT_MODE = 0,
+	PD_ENTER_MODE = 1,
+	/* Not a command.  Do NOT remove. */
+	PD_MODE_CMD_COUNT,
+};
+
+struct __ec_align4 ec_params_usb_pd_set_mode_request {
+	uint32_t cmd;  /* enum pd_mode_cmd */
+	uint16_t svid; /* SVID to set */
+	uint8_t opos;  /* Object Position */
+	uint8_t port;  /* port */
+};
+
+/* Ask the PD MCU to record a log of a requested type */
+#define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118
+
+struct __ec_align1 ec_params_pd_write_log_entry {
+	uint8_t type; /* event type : see PD_EVENT_xx above */
+	uint8_t port; /* port#, or 0 for events unrelated to a given port */
+};
+
+
+/* Control USB-PD chip */
+#define EC_CMD_PD_CONTROL 0x0119
+
+enum ec_pd_control_cmd {
+	PD_SUSPEND = 0,      /* Suspend the PD chip (EC: stop talking to PD) */
+	PD_RESUME,           /* Resume the PD chip (EC: start talking to PD) */
+	PD_RESET,            /* Force reset the PD chip */
+	PD_CONTROL_DISABLE   /* Disable further calls to this command */
+};
+
+struct __ec_align1 ec_params_pd_control {
+	uint8_t chip;         /* chip id (should be 0) */
+	uint8_t subcmd;
+};
+
+/* Get info about USB-C SS muxes */
+#define EC_CMD_USB_PD_MUX_INFO 0x011A
+
+struct __ec_align1 ec_params_usb_pd_mux_info {
+	uint8_t port; /* USB-C port number */
+};
+
+/* Flags representing mux state */
+#define USB_PD_MUX_USB_ENABLED       (1 << 0)
+#define USB_PD_MUX_DP_ENABLED        (1 << 1)
+#define USB_PD_MUX_POLARITY_INVERTED (1 << 2)
+#define USB_PD_MUX_HPD_IRQ           (1 << 3)
+
+struct __ec_align1 ec_response_usb_pd_mux_info {
+	uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */
+};
+
+#define EC_CMD_PD_CHIP_INFO		0x011B
+
+struct __ec_align1 ec_params_pd_chip_info {
+	uint8_t port;	/* USB-C port number */
+	uint8_t renew;	/* Force renewal */
+};
+
+struct __ec_align2 ec_response_pd_chip_info {
+	uint16_t vendor_id;
+	uint16_t product_id;
+	uint16_t device_id;
+	union {
+		uint8_t fw_version_string[8];
+		uint64_t fw_version_number;
+	};
+};
+
+/* Run RW signature verification and get status */
+#define EC_CMD_RWSIG_CHECK_STATUS	0x011C
+
+struct __ec_align4 ec_response_rwsig_check_status {
+	uint32_t status;
+};
+
+/* For controlling RWSIG task */
+#define EC_CMD_RWSIG_ACTION	0x011D
+
+enum rwsig_action {
+	RWSIG_ACTION_ABORT = 0,		/* Abort RWSIG and prevent jumping */
+	RWSIG_ACTION_CONTINUE = 1,	/* Jump to RW immediately */
+};
+
+struct __ec_align4 ec_params_rwsig_action {
+	uint32_t action;
+};
+
+/* Run verification on a slot */
+#define EC_CMD_EFS_VERIFY	0x011E
+
+struct __ec_align1 ec_params_efs_verify {
+	uint8_t region;		/* enum ec_flash_region */
+};
+
+/*
+ * Retrieve info from Cros Board Info store. Response is based on the data
+ * type. Integers return a uint32. Strings return a string, using the response
+ * size to determine how big it is.
+ */
+#define EC_CMD_GET_CROS_BOARD_INFO	0x011F
+/*
+ * Write info into Cros Board Info on EEPROM. Write fails if the board has
+ * hardware write-protect enabled.
+ */
+#define EC_CMD_SET_CROS_BOARD_INFO	0x0120
+
+enum cbi_data_tag {
+	CBI_TAG_BOARD_VERSION = 0, /* uint16_t or uint8_t[] = {minor,major} */
+	CBI_TAG_OEM_ID = 1,        /* uint8_t */
+	CBI_TAG_SKU_ID = 2,        /* uint8_t */
+	CBI_TAG_COUNT,
+};
+
+/*
+ * Flags to control read operation
+ *
+ * RELOAD:  Invalidate cache and read data from EEPROM. Useful to verify
+ *          write was successful without reboot.
+ */
+#define CBI_GET_RELOAD		(1 << 0)
+
+struct __ec_align4 ec_params_get_cbi {
+	uint32_t type;		/* enum cbi_data_tag */
+	uint32_t flag;		/* CBI_GET_* */
+};
+
+/*
+ * Flags to control write behavior.
+ *
+ * NO_SYNC: Makes EC update data in RAM but skip writing to EEPROM. It's
+ *          useful when writing multiple fields in a row.
+ * INIT:    Needs to be set when creating a new CBI from scratch. All fields
+ *          will be initialized to zero first.
+ */
+#define CBI_SET_NO_SYNC		(1 << 0)
+#define CBI_SET_INIT		(1 << 1)
+
+struct __ec_align1 ec_params_set_cbi {
+	uint32_t tag;		/* enum cbi_data_tag */
+	uint32_t flag;		/* CBI_SET_* */
+	uint32_t size;		/* Data size */
+	uint8_t data[];		/* For string and raw data */
+};
+
+/*****************************************************************************/
+/* The command range 0x200-0x2FF is reserved for Rotor. */
+
+/*****************************************************************************/
+/*
+ * Reserve a range of host commands for the CR51 firmware.
+ */
+#define EC_CMD_CR51_BASE 0x0300
+#define EC_CMD_CR51_LAST 0x03FF
+
+/*****************************************************************************/
+/* Fingerprint MCU commands: range 0x0400-0x040x */
+
+/* Fingerprint SPI sensor passthru command: prototyping ONLY */
+#define EC_CMD_FP_PASSTHRU 0x0400
+
+#define EC_FP_FLAG_NOT_COMPLETE 0x1
+
+struct __ec_align2 ec_params_fp_passthru {
+	uint16_t len;		/* Number of bytes to write then read */
+	uint16_t flags;		/* EC_FP_FLAG_xxx */
+	uint8_t data[];		/* Data to send */
+};
+
+/* Fingerprint sensor configuration command: prototyping ONLY */
+#define EC_CMD_FP_SENSOR_CONFIG 0x0401
+
+#define EC_FP_SENSOR_CONFIG_MAX_REGS 16
+
+struct __ec_align2 ec_params_fp_sensor_config {
+	uint8_t count;		/* Number of setup registers */
+	/*
+	 * the value to send to each of the 'count' setup registers
+	 * is stored in the 'data' array for 'len' bytes just after
+	 * the previous one.
+	 */
+	uint8_t len[EC_FP_SENSOR_CONFIG_MAX_REGS];
+	uint8_t data[];
+};
+
+/* Configure the Fingerprint MCU behavior */
+#define EC_CMD_FP_MODE 0x0402
+
+/* Put the sensor in its lowest power mode */
+#define FP_MODE_DEEPSLEEP     (1<<0)
+/* Wait to see a finger on the sensor */
+#define FP_MODE_FINGER_DOWN   (1<<1)
+/* Poll until the finger has left the sensor */
+#define FP_MODE_FINGER_UP     (1<<2)
+/* Capture the current finger image */
+#define FP_MODE_CAPTURE       (1<<3)
+/* special value: don't change anything just read back current mode */
+#define FP_MODE_DONT_CHANGE   (1<<31)
+
+struct __ec_align4 ec_params_fp_mode {
+	uint32_t mode; /* as defined by FP_MODE_ constants */
+	/* TBD */
+};
+
+struct __ec_align4 ec_response_fp_mode {
+	uint32_t mode; /* as defined by FP_MODE_ constants */
+	/* TBD */
+};
+
+/* Retrieve Fingerprint sensor information */
+#define EC_CMD_FP_INFO 0x0403
+
+struct __ec_align2 ec_response_fp_info {
+	/* Sensor identification */
+	uint32_t vendor_id;
+	uint32_t product_id;
+	uint32_t model_id;
+	uint32_t version;
+	/* Image frame characteristics */
+	uint32_t frame_size;
+	uint32_t pixel_format; /* using V4L2_PIX_FMT_ */
+	uint16_t width;
+	uint16_t height;
+	uint16_t bpp;
+};
+
+/* Get the last captured finger frame: TODO: will be AES-encrypted */
+#define EC_CMD_FP_FRAME 0x0404
+
+struct __ec_align4 ec_params_fp_frame {
+	uint32_t offset;
+	uint32_t size;
+};
+
+/*****************************************************************************/
+/* Touchpad MCU commands: range 0x0500-0x05FF */
+
+/* Perform touchpad self test */
+#define EC_CMD_TP_SELF_TEST 0x0500
+
+/* Get number of frame types, and the size of each type */
+#define EC_CMD_TP_FRAME_INFO 0x0501
+
+struct __ec_align4 ec_response_tp_frame_info {
+	uint32_t n_frames;
+	uint32_t frame_sizes[0];
+};
+
+/* Create a snapshot of current frame readings */
+#define EC_CMD_TP_FRAME_SNAPSHOT 0x0502
+
+/* Read the frame */
+#define EC_CMD_TP_FRAME_GET 0x0503
+
+struct __ec_align4 ec_params_tp_frame_get {
+	uint32_t frame_index;
+	uint32_t offset;
+	uint32_t size;
+};
+
+/*****************************************************************************/
+/*
+ * Reserve a range of host commands for board-specific, experimental, or
+ * special purpose features. These can be (re)used without updating this file.
+ *
+ * CAUTION: Don't go nuts with this. Shipping products should document ALL
+ * their EC commands for easier development, testing, debugging, and support.
+ *
+ * All commands MUST be #defined to be 4-digit UPPER CASE hex values
+ * (e.g., 0x00AB, not 0xab) for CONFIG_HOSTCMD_SECTION_SORTED to work.
+ *
+ * In your experimental code, you may want to do something like this:
+ *
+ *   #define EC_CMD_MAGIC_FOO 0x0000
+ *   #define EC_CMD_MAGIC_BAR 0x0001
+ *   #define EC_CMD_MAGIC_HEY 0x0002
+ *
+ *   DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_FOO, magic_foo_handler,
+ *      EC_VER_MASK(0);
+ *
+ *   DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_BAR, magic_bar_handler,
+ *      EC_VER_MASK(0);
+ *
+ *   DECLARE_PRIVATE_HOST_COMMAND(EC_CMD_MAGIC_HEY, magic_hey_handler,
+ *      EC_VER_MASK(0);
+ */
+#define EC_CMD_BOARD_SPECIFIC_BASE 0x3E00
+#define EC_CMD_BOARD_SPECIFIC_LAST 0x3FFF
+
+/*
+ * Given the private host command offset, calculate the true private host
+ * command value.
+ */
+#define EC_PRIVATE_HOST_COMMAND_VALUE(command) \
+	(EC_CMD_BOARD_SPECIFIC_BASE + (command))
+
+/*****************************************************************************/
+/*
+ * Passthru commands
+ *
+ * Some platforms have sub-processors chained to each other.  For example.
+ *
+ *     AP <--> EC <--> PD MCU
+ *
+ * The top 2 bits of the command number are used to indicate which device the
+ * command is intended for.  Device 0 is always the device receiving the
+ * command; other device mapping is board-specific.
+ *
+ * When a device receives a command to be passed to a sub-processor, it passes
+ * it on with the device number set back to 0.  This allows the sub-processor
+ * to remain blissfully unaware of whether the command originated on the next
+ * device up the chain, or was passed through from the AP.
+ *
+ * In the above example, if the AP wants to send command 0x0002 to the PD MCU,
+ *     AP sends command 0x4002 to the EC
+ *     EC sends command 0x0002 to the PD MCU
+ *     EC forwards PD MCU response back to the AP
+ */
+
+/* Offset and max command number for sub-device n */
+#define EC_CMD_PASSTHRU_OFFSET(n) (0x4000 * (n))
+#define EC_CMD_PASSTHRU_MAX(n) (EC_CMD_PASSTHRU_OFFSET(n) + 0x3fff)
+
+/*****************************************************************************/
+/*
+ * Deprecated constants. These constants have been renamed for clarity. The
+ * meaning and size has not changed. Programs that use the old names should
+ * switch to the new names soon, as the old names may not be carried forward
+ * forever.
+ */
+#define EC_HOST_PARAM_SIZE      EC_PROTO2_MAX_PARAM_SIZE
+#define EC_LPC_ADDR_OLD_PARAM   EC_HOST_CMD_REGION1
+#define EC_OLD_PARAM_SIZE       EC_HOST_CMD_REGION_SIZE
+
+#endif  /* !__ACPI__ && !__KERNEL__ */
+
+#endif  /* __CROS_EC_COMMANDS_H */
diff --git a/include/edid.h b/include/edid.h
new file mode 100644
index 0000000..2562733
--- /dev/null
+++ b/include/edid.h
@@ -0,0 +1,345 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * (C) Copyright 2010
+ * Petr Stetiar <ynezz@true.cz>
+ *
+ * Contains stolen code from ddcprobe project which is:
+ * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com>
+ */
+
+#ifndef __EDID_H_
+#define __EDID_H_
+
+#include <linux/types.h>
+
+/* Size of the EDID data */
+#define EDID_SIZE	128
+#define EDID_EXT_SIZE	256
+
+/* OUI of HDMI vendor specific data block */
+#define HDMI_IEEE_OUI 0x000c03
+
+#define GET_BIT(_x, _pos) \
+	(((_x) >> (_pos)) & 1)
+#define GET_BITS(_x, _pos_msb, _pos_lsb) \
+	(((_x) >> (_pos_lsb)) & ((1 << ((_pos_msb) - (_pos_lsb) + 1)) - 1))
+
+/* Aspect ratios used in EDID info. */
+enum edid_aspect {
+	ASPECT_625 = 0,
+	ASPECT_75,
+	ASPECT_8,
+	ASPECT_5625,
+};
+
+/* Detailed timing information used in EDID v1.x */
+struct edid_detailed_timing {
+	unsigned char pixel_clock[2];
+#define EDID_DETAILED_TIMING_PIXEL_CLOCK(_x) \
+	(((((uint32_t)(_x).pixel_clock[1]) << 8) + \
+	 (_x).pixel_clock[0]) * 10000)
+	unsigned char horizontal_active;
+	unsigned char horizontal_blanking;
+	unsigned char horizontal_active_blanking_hi;
+#define EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(_x) \
+	((GET_BITS((_x).horizontal_active_blanking_hi, 7, 4) << 8) + \
+	 (_x).horizontal_active)
+#define EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(_x) \
+	((GET_BITS((_x).horizontal_active_blanking_hi, 3, 0) << 8) + \
+	 (_x).horizontal_blanking)
+	unsigned char vertical_active;
+	unsigned char vertical_blanking;
+	unsigned char vertical_active_blanking_hi;
+#define EDID_DETAILED_TIMING_VERTICAL_ACTIVE(_x) \
+	((GET_BITS((_x).vertical_active_blanking_hi, 7, 4) << 8) + \
+	 (_x).vertical_active)
+#define EDID_DETAILED_TIMING_VERTICAL_BLANKING(_x) \
+	((GET_BITS((_x).vertical_active_blanking_hi, 3, 0) << 8) + \
+	 (_x).vertical_blanking)
+	unsigned char hsync_offset;
+	unsigned char hsync_pulse_width;
+	unsigned char vsync_offset_pulse_width;
+	unsigned char hsync_vsync_offset_pulse_width_hi;
+#define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \
+	((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 7, 6) << 8) + \
+	 (_x).hsync_offset)
+#define EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(_x) \
+	((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 5, 4) << 8) + \
+	 (_x).hsync_pulse_width)
+#define EDID_DETAILED_TIMING_VSYNC_OFFSET(_x) \
+	((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 3, 2) << 4) + \
+	 GET_BITS((_x).vsync_offset_pulse_width, 7, 4))
+#define EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(_x) \
+	((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 1, 0) << 4) + \
+	 GET_BITS((_x).vsync_offset_pulse_width, 3, 0))
+	unsigned char himage_size;
+	unsigned char vimage_size;
+	unsigned char himage_vimage_size_hi;
+#define EDID_DETAILED_TIMING_HIMAGE_SIZE(_x) \
+	((GET_BITS((_x).himage_vimage_size_hi, 7, 4) << 8) + (_x).himage_size)
+#define EDID_DETAILED_TIMING_VIMAGE_SIZE(_x) \
+	((GET_BITS((_x).himage_vimage_size_hi, 3, 0) << 8) + (_x).vimage_size)
+	unsigned char hborder;
+	unsigned char vborder;
+	unsigned char flags;
+#define EDID_DETAILED_TIMING_FLAG_INTERLACED(_x) \
+	GET_BIT((_x).flags, 7)
+#define EDID_DETAILED_TIMING_FLAG_STEREO(_x) \
+	GET_BITS((_x).flags, 6, 5)
+#define EDID_DETAILED_TIMING_FLAG_DIGITAL_COMPOSITE(_x) \
+	GET_BITS((_x).flags, 4, 3)
+#define EDID_DETAILED_TIMING_FLAG_POLARITY(_x) \
+	GET_BITS((_x).flags, 2, 1)
+#define EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(_x) \
+	GET_BIT((_x).flags, 2)
+#define EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(_x) \
+	GET_BIT((_x).flags, 1)
+#define EDID_DETAILED_TIMING_FLAG_INTERLEAVED(_x) \
+	GET_BIT((_x).flags, 0)
+} __attribute__ ((__packed__));
+
+enum edid_monitor_descriptor_types {
+	EDID_MONITOR_DESCRIPTOR_SERIAL = 0xff,
+	EDID_MONITOR_DESCRIPTOR_ASCII = 0xfe,
+	EDID_MONITOR_DESCRIPTOR_RANGE = 0xfd,
+	EDID_MONITOR_DESCRIPTOR_NAME = 0xfc,
+};
+
+struct edid_monitor_descriptor {
+	uint16_t zero_flag_1;
+	unsigned char zero_flag_2;
+	unsigned char type;
+	unsigned char zero_flag_3;
+	union {
+		char string[13];
+		struct {
+			unsigned char vertical_min;
+			unsigned char vertical_max;
+			unsigned char horizontal_min;
+			unsigned char horizontal_max;
+			unsigned char pixel_clock_max;
+			unsigned char gtf_data[8];
+		} range_data;
+	} data;
+} __attribute__ ((__packed__));
+
+struct edid1_info {
+	unsigned char header[8];
+	unsigned char manufacturer_name[2];
+#define EDID1_INFO_MANUFACTURER_NAME_ZERO(_x) \
+	GET_BIT(((_x).manufacturer_name[0]), 7)
+#define EDID1_INFO_MANUFACTURER_NAME_CHAR1(_x) \
+	GET_BITS(((_x).manufacturer_name[0]), 6, 2)
+#define EDID1_INFO_MANUFACTURER_NAME_CHAR2(_x) \
+	((GET_BITS(((_x).manufacturer_name[0]), 1, 0) << 3) + \
+	 GET_BITS(((_x).manufacturer_name[1]), 7, 5))
+#define EDID1_INFO_MANUFACTURER_NAME_CHAR3(_x) \
+	GET_BITS(((_x).manufacturer_name[1]), 4, 0)
+	unsigned char product_code[2];
+#define EDID1_INFO_PRODUCT_CODE(_x) \
+	(((uint16_t)(_x).product_code[1] << 8) + (_x).product_code[0])
+	unsigned char serial_number[4];
+#define EDID1_INFO_SERIAL_NUMBER(_x) \
+	(((uint32_t)(_x).serial_number[3] << 24) + \
+	 ((_x).serial_number[2] << 16) + ((_x).serial_number[1] << 8) + \
+	 (_x).serial_number[0])
+	unsigned char week;
+	unsigned char year;
+	unsigned char version;
+	unsigned char revision;
+	unsigned char video_input_definition;
+#define EDID1_INFO_VIDEO_INPUT_DIGITAL(_x) \
+	GET_BIT(((_x).video_input_definition), 7)
+#define EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(_x) \
+	GET_BITS(((_x).video_input_definition), 6, 5)
+#define EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(_x) \
+	GET_BIT(((_x).video_input_definition), 4)
+#define EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(_x) \
+	GET_BIT(((_x).video_input_definition), 3)
+#define EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(_x) \
+	GET_BIT(((_x).video_input_definition), 2)
+#define EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(_x) \
+	GET_BIT(((_x).video_input_definition), 1)
+#define EDID1_INFO_VIDEO_INPUT_SERRATION_V(_x) \
+	GET_BIT(((_x).video_input_definition), 0)
+	unsigned char max_size_horizontal;
+	unsigned char max_size_vertical;
+	unsigned char gamma;
+	unsigned char feature_support;
+#define EDID1_INFO_FEATURE_STANDBY(_x) \
+	GET_BIT(((_x).feature_support), 7)
+#define EDID1_INFO_FEATURE_SUSPEND(_x) \
+	GET_BIT(((_x).feature_support), 6)
+#define EDID1_INFO_FEATURE_ACTIVE_OFF(_x) \
+	GET_BIT(((_x).feature_support), 5)
+#define EDID1_INFO_FEATURE_DISPLAY_TYPE(_x) \
+	GET_BITS(((_x).feature_support), 4, 3)
+#define EDID1_INFO_FEATURE_RGB(_x) \
+	GET_BIT(((_x).feature_support), 2)
+#define EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(_x) \
+	GET_BIT(((_x).feature_support), 1)
+#define EDID1_INFO_FEATURE_DEFAULT_GTF_SUPPORT(_x) \
+	GET_BIT(((_x).feature_support), 0)
+	unsigned char color_characteristics[10];
+	unsigned char established_timings[3];
+#define EDID1_INFO_ESTABLISHED_TIMING_720X400_70(_x) \
+	GET_BIT(((_x).established_timings[0]), 7)
+#define EDID1_INFO_ESTABLISHED_TIMING_720X400_88(_x) \
+	GET_BIT(((_x).established_timings[0]), 6)
+#define EDID1_INFO_ESTABLISHED_TIMING_640X480_60(_x) \
+	GET_BIT(((_x).established_timings[0]), 5)
+#define EDID1_INFO_ESTABLISHED_TIMING_640X480_67(_x) \
+	GET_BIT(((_x).established_timings[0]), 4)
+#define EDID1_INFO_ESTABLISHED_TIMING_640X480_72(_x) \
+	GET_BIT(((_x).established_timings[0]), 3)
+#define EDID1_INFO_ESTABLISHED_TIMING_640X480_75(_x) \
+	GET_BIT(((_x).established_timings[0]), 2)
+#define EDID1_INFO_ESTABLISHED_TIMING_800X600_56(_x) \
+	GET_BIT(((_x).established_timings[0]), 1)
+#define EDID1_INFO_ESTABLISHED_TIMING_800X600_60(_x) \
+	GET_BIT(((_x).established_timings[0]), 0)
+#define EDID1_INFO_ESTABLISHED_TIMING_800X600_72(_x) \
+	GET_BIT(((_x).established_timings[1]), 7)
+#define EDID1_INFO_ESTABLISHED_TIMING_800X600_75(_x) \
+	GET_BIT(((_x).established_timings[1]), 6)
+#define EDID1_INFO_ESTABLISHED_TIMING_832X624_75(_x) \
+	GET_BIT(((_x).established_timings[1]), 5)
+#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(_x) \
+	GET_BIT(((_x).established_timings[1]), 4)
+#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(_x) \
+	GET_BIT(((_x).established_timings[1]), 3)
+#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(_x) \
+	GET_BIT(((_x).established_timings[1]), 2)
+#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(_x) \
+	GET_BIT(((_x).established_timings[1]), 1)
+#define EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(_x) \
+	GET_BIT(((_x).established_timings[1]), 0)
+#define EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(_x) \
+	GET_BIT(((_x).established_timings[2]), 7)
+	struct {
+		unsigned char xresolution;
+		unsigned char aspect_vfreq;
+	} __attribute__((__packed__)) standard_timings[8];
+#define EDID1_INFO_STANDARD_TIMING_XRESOLUTION(_x, _i) \
+	(((_x).standard_timings[_i]).xresolution)
+#define EDID1_INFO_STANDARD_TIMING_ASPECT(_x, _i) \
+	GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 7, 6)
+#define EDID1_INFO_STANDARD_TIMING_VFREQ(_x, _i) \
+	GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 5, 0)
+	union {
+		unsigned char timing[72];
+		struct edid_monitor_descriptor descriptor[4];
+	} monitor_details;
+	unsigned char extension_flag;
+	unsigned char checksum;
+} __attribute__ ((__packed__));
+
+enum edid_cea861_db_types {
+	EDID_CEA861_DB_AUDIO = 0x01,
+	EDID_CEA861_DB_VIDEO = 0x02,
+	EDID_CEA861_DB_VENDOR = 0x03,
+	EDID_CEA861_DB_SPEAKER = 0x04,
+};
+
+struct edid_cea861_info {
+	unsigned char extension_tag;
+#define EDID_CEA861_EXTENSION_TAG	0x02
+	unsigned char revision;
+	unsigned char dtd_offset;
+	unsigned char dtd_count;
+#define EDID_CEA861_SUPPORTS_UNDERSCAN(_x) \
+	GET_BIT(((_x).dtd_count), 7)
+#define EDID_CEA861_SUPPORTS_BASIC_AUDIO(_x) \
+	GET_BIT(((_x).dtd_count), 6)
+#define EDID_CEA861_SUPPORTS_YUV444(_x) \
+	GET_BIT(((_x).dtd_count), 5)
+#define EDID_CEA861_SUPPORTS_YUV422(_x) \
+	GET_BIT(((_x).dtd_count), 4)
+#define EDID_CEA861_DTD_COUNT(_x) \
+	GET_BITS(((_x).dtd_count), 3, 0)
+	unsigned char data[124];
+#define EDID_CEA861_DB_TYPE(_x, offset) \
+	GET_BITS((_x).data[offset], 7, 5)
+#define EDID_CEA861_DB_LEN(_x, offset) \
+	GET_BITS((_x).data[offset], 4, 0)
+} __attribute__ ((__packed__));
+
+/**
+ * Print the EDID info.
+ *
+ * @param edid_info	The EDID info to be printed
+ */
+void edid_print_info(struct edid1_info *edid_info);
+
+/**
+ * Check the EDID info.
+ *
+ * @param info  The EDID info to be checked
+ * @return 0 on valid, or -1 on invalid
+ */
+int edid_check_info(struct edid1_info *info);
+
+/**
+ * Check checksum of a 128 bytes EDID data block
+ *
+ * @param edid_block	EDID block data
+ *
+ * @return 0 on success, or a negative errno on error
+ */
+int edid_check_checksum(u8 *edid_block);
+
+/**
+ * Get the horizontal and vertical rate ranges of the monitor.
+ *
+ * @param edid	The EDID info
+ * @param hmin	Returns the minimum horizontal rate
+ * @param hmax	Returns the maxium horizontal rate
+ * @param vmin	Returns the minimum vertical rate
+ * @param vmax	Returns the maxium vertical rate
+ * @return 0 on success, or -1 on error
+ */
+int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin,
+		    unsigned int *hmax, unsigned int *vmin,
+		    unsigned int *vmax);
+
+struct display_timing;
+
+/**
+ * edid_get_timing_validate() - Get basic digital display parameters with
+ * mode selection callback
+ *
+ * @param buf		Buffer containing EDID data
+ * @param buf_size	Size of buffer in bytes
+ * @param timing	Place to put preferring timing information
+ * @param panel_bits_per_colourp	Place to put the number of bits per
+ *			colour supported by the panel. This will be set to
+ *			-1 if not available
+ * @param mode_valid	Callback validating mode, returning true is mode is
+ *			supported, false otherwise.
+ * @parem valid_priv	Pointer to private data for mode_valid callback
+ * @return 0 if timings are OK, -ve on error
+ */
+int edid_get_timing_validate(u8 *buf, int buf_size,
+			     struct display_timing *timing,
+			     int *panel_bits_per_colourp,
+			     bool (*mode_valid)(void *priv,
+					const struct display_timing *timing),
+			     void *mode_valid_priv);
+
+/**
+ * edid_get_timing() - Get basic digital display parameters
+ *
+ * @param buf		Buffer containing EDID data
+ * @param buf_size	Size of buffer in bytes
+ * @param timing	Place to put preferring timing information
+ * @param panel_bits_per_colourp	Place to put the number of bits per
+ *			colour supported by the panel. This will be set to
+ *			-1 if not available
+ * @return 0 if timings are OK, -ve on error
+ */
+int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing,
+		    int *panel_bits_per_colourp);
+
+#endif /* __EDID_H_ */
diff --git a/include/eeprom_field.h b/include/eeprom_field.h
new file mode 100644
index 0000000..05c0d14
--- /dev/null
+++ b/include/eeprom_field.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ */
+
+#ifndef _FIELD_
+#define _FIELD_
+
+#define PRINT_FIELD_SEGMENT	"%-30s"
+
+struct eeprom_field {
+	char *name;
+	int size;
+	unsigned char *buf;
+
+	void (*print)(const struct eeprom_field *eeprom_field);
+	int (*update)(struct eeprom_field *eeprom_field, char *value);
+};
+
+void eeprom_field_print_bin(const struct eeprom_field *field);
+int eeprom_field_update_bin(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_bin_rev(const struct eeprom_field *field);
+int eeprom_field_update_bin_rev(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_mac(const struct eeprom_field *field);
+int eeprom_field_update_mac(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_ascii(const struct eeprom_field *field);
+int eeprom_field_update_ascii(struct eeprom_field *field, char *value);
+
+void eeprom_field_print_reserved(const struct eeprom_field *field);
+int eeprom_field_update_reserved(struct eeprom_field *field, char *value);
+
+#endif
diff --git a/include/eeprom_layout.h b/include/eeprom_layout.h
new file mode 100644
index 0000000..730d963
--- /dev/null
+++ b/include/eeprom_layout.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009-2016 CompuLab, Ltd.
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ */
+
+#ifndef _LAYOUT_
+#define _LAYOUT_
+
+#define RESERVED_FIELDS			NULL
+#define LAYOUT_VERSION_UNRECOGNIZED	-1
+#define LAYOUT_VERSION_AUTODETECT	-2
+
+struct eeprom_layout {
+	struct eeprom_field *fields;
+	int num_of_fields;
+	int layout_version;
+	unsigned char *data;
+	int data_size;
+	void (*print)(const struct eeprom_layout *eeprom_layout);
+	int (*update)(struct eeprom_layout *eeprom_layout, char *field_name,
+		      char *new_data);
+};
+
+void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf,
+			 unsigned int buf_size, int layout_version);
+__weak void __eeprom_layout_assign(struct eeprom_layout *layout,
+				   int layout_version);
+
+#endif
diff --git a/include/efi.h b/include/efi.h
new file mode 100644
index 0000000..5f415a9
--- /dev/null
+++ b/include/efi.h
@@ -0,0 +1,490 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Extensible Firmware Interface
+ * Based on 'Extensible Firmware Interface Specification' version 0.9,
+ * April 30, 1999
+ *
+ * Copyright (C) 1999 VA Linux Systems
+ * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
+ * Copyright (C) 1999, 2002-2003 Hewlett-Packard Co.
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
+ *	Stephane Eranian <eranian@hpl.hp.com>
+ *
+ * From include/linux/efi.h in kernel 4.1 with some additions/subtractions
+ */
+
+#ifndef _EFI_H
+#define _EFI_H
+
+#include <linux/linkage.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+/*
+ * EFI on x86_64 uses the Microsoft ABI which is not the default for GCC.
+ *
+ * There are two scenarios for EFI on x86_64: building a 64-bit EFI stub
+ * codes (CONFIG_EFI_STUB_64BIT) and building a 64-bit U-Boot (CONFIG_X86_64).
+ * Either needs to be properly built with the '-m64' compiler flag, and hence
+ * it is enough to only check the compiler provided define __x86_64__ here.
+ */
+#ifdef __x86_64__
+#define EFIAPI __attribute__((ms_abi))
+#define efi_va_list __builtin_ms_va_list
+#define efi_va_start __builtin_ms_va_start
+#define efi_va_arg __builtin_va_arg
+#define efi_va_end __builtin_ms_va_end
+#else
+#define EFIAPI asmlinkage
+#define efi_va_list va_list
+#define efi_va_start va_start
+#define efi_va_arg va_arg
+#define efi_va_end va_end
+#endif /* __x86_64__ */
+
+#define EFI32_LOADER_SIGNATURE	"EL32"
+#define EFI64_LOADER_SIGNATURE	"EL64"
+
+struct efi_device_path;
+
+typedef struct {
+	u8 b[16];
+} efi_guid_t __attribute__((aligned(8)));
+
+#define EFI_BITS_PER_LONG	(sizeof(long) * 8)
+
+/* Bit mask for EFI status code with error */
+#define EFI_ERROR_MASK (1UL << (EFI_BITS_PER_LONG - 1))
+/* Status codes returned by EFI protocols */
+#define EFI_SUCCESS			0
+#define EFI_LOAD_ERROR			(EFI_ERROR_MASK | 1)
+#define EFI_INVALID_PARAMETER		(EFI_ERROR_MASK | 2)
+#define EFI_UNSUPPORTED			(EFI_ERROR_MASK | 3)
+#define EFI_BAD_BUFFER_SIZE		(EFI_ERROR_MASK | 4)
+#define EFI_BUFFER_TOO_SMALL		(EFI_ERROR_MASK | 5)
+#define EFI_NOT_READY			(EFI_ERROR_MASK | 6)
+#define EFI_DEVICE_ERROR		(EFI_ERROR_MASK | 7)
+#define EFI_WRITE_PROTECTED		(EFI_ERROR_MASK | 8)
+#define EFI_OUT_OF_RESOURCES		(EFI_ERROR_MASK | 9)
+#define EFI_VOLUME_CORRUPTED		(EFI_ERROR_MASK | 10)
+#define EFI_VOLUME_FULL			(EFI_ERROR_MASK | 11)
+#define EFI_NO_MEDIA			(EFI_ERROR_MASK | 12)
+#define EFI_MEDIA_CHANGED		(EFI_ERROR_MASK | 13)
+#define EFI_NOT_FOUND			(EFI_ERROR_MASK | 14)
+#define EFI_ACCESS_DENIED		(EFI_ERROR_MASK | 15)
+#define EFI_NO_RESPONSE			(EFI_ERROR_MASK | 16)
+#define EFI_NO_MAPPING			(EFI_ERROR_MASK | 17)
+#define EFI_TIMEOUT			(EFI_ERROR_MASK | 18)
+#define EFI_NOT_STARTED			(EFI_ERROR_MASK | 19)
+#define EFI_ALREADY_STARTED		(EFI_ERROR_MASK | 20)
+#define EFI_ABORTED			(EFI_ERROR_MASK | 21)
+#define EFI_ICMP_ERROR			(EFI_ERROR_MASK | 22)
+#define EFI_TFTP_ERROR			(EFI_ERROR_MASK | 23)
+#define EFI_PROTOCOL_ERROR		(EFI_ERROR_MASK | 24)
+#define EFI_INCOMPATIBLE_VERSION	(EFI_ERROR_MASK | 25)
+#define EFI_SECURITY_VIOLATION		(EFI_ERROR_MASK | 26)
+#define EFI_CRC_ERROR			(EFI_ERROR_MASK | 27)
+#define EFI_END_OF_MEDIA		(EFI_ERROR_MASK | 28)
+#define EFI_END_OF_FILE			(EFI_ERROR_MASK | 31)
+#define EFI_INVALID_LANGUAGE		(EFI_ERROR_MASK | 32)
+#define EFI_COMPROMISED_DATA		(EFI_ERROR_MASK | 33)
+#define EFI_IP_ADDRESS_CONFLICT		(EFI_ERROR_MASK | 34)
+#define EFI_HTTP_ERROR			(EFI_ERROR_MASK | 35)
+
+#define EFI_WARN_DELETE_FAILURE	2
+
+typedef unsigned long efi_status_t;
+typedef u64 efi_physical_addr_t;
+typedef u64 efi_virtual_addr_t;
+typedef struct efi_object *efi_handle_t;
+
+#define EFI_GUID(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
+	{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, \
+		((a) >> 24) & 0xff, \
+		(b) & 0xff, ((b) >> 8) & 0xff, \
+		(c) & 0xff, ((c) >> 8) & 0xff, \
+		(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) } }
+
+/* Generic EFI table header */
+struct efi_table_hdr {
+	u64 signature;
+	u32 revision;
+	u32 headersize;
+	u32 crc32;
+	u32 reserved;
+};
+
+/* Enumeration of memory types introduced in UEFI */
+enum efi_mem_type {
+	EFI_RESERVED_MEMORY_TYPE,
+	/*
+	 * The code portions of a loaded application.
+	 * (Note that UEFI OS loaders are UEFI applications.)
+	 */
+	EFI_LOADER_CODE,
+	/*
+	 * The data portions of a loaded application and
+	 * the default data allocation type used by an application
+	 * to allocate pool memory.
+	 */
+	EFI_LOADER_DATA,
+	/* The code portions of a loaded Boot Services Driver */
+	EFI_BOOT_SERVICES_CODE,
+	/*
+	 * The data portions of a loaded Boot Services Driver and
+	 * the default data allocation type used by a Boot Services
+	 * Driver to allocate pool memory.
+	 */
+	EFI_BOOT_SERVICES_DATA,
+	/* The code portions of a loaded Runtime Services Driver */
+	EFI_RUNTIME_SERVICES_CODE,
+	/*
+	 * The data portions of a loaded Runtime Services Driver and
+	 * the default data allocation type used by a Runtime Services
+	 * Driver to allocate pool memory.
+	 */
+	EFI_RUNTIME_SERVICES_DATA,
+	/* Free (unallocated) memory */
+	EFI_CONVENTIONAL_MEMORY,
+	/* Memory in which errors have been detected */
+	EFI_UNUSABLE_MEMORY,
+	/* Memory that holds the ACPI tables */
+	EFI_ACPI_RECLAIM_MEMORY,
+	/* Address space reserved for use by the firmware */
+	EFI_ACPI_MEMORY_NVS,
+	/*
+	 * Used by system firmware to request that a memory-mapped IO region
+	 * be mapped by the OS to a virtual address so it can be accessed by
+	 * EFI runtime services.
+	 */
+	EFI_MMAP_IO,
+	/*
+	 * System memory-mapped IO region that is used to translate
+	 * memory cycles to IO cycles by the processor.
+	 */
+	EFI_MMAP_IO_PORT,
+	/*
+	 * Address space reserved by the firmware for code that is
+	 * part of the processor.
+	 */
+	EFI_PAL_CODE,
+	/*
+	 * Non-volatile memory.
+	 */
+	EFI_PERSISTENT_MEMORY_TYPE,
+
+	EFI_MAX_MEMORY_TYPE,
+	EFI_TABLE_END,	/* For efi_build_mem_table() */
+};
+
+/* Attribute values */
+#define EFI_MEMORY_UC		((u64)0x0000000000000001ULL)	/* uncached */
+#define EFI_MEMORY_WC		((u64)0x0000000000000002ULL)	/* write-coalescing */
+#define EFI_MEMORY_WT		((u64)0x0000000000000004ULL)	/* write-through */
+#define EFI_MEMORY_WB		((u64)0x0000000000000008ULL)	/* write-back */
+#define EFI_MEMORY_UCE		((u64)0x0000000000000010ULL)	/* uncached, exported */
+#define EFI_MEMORY_WP		((u64)0x0000000000001000ULL)	/* write-protect */
+#define EFI_MEMORY_RP		((u64)0x0000000000002000ULL)	/* read-protect */
+#define EFI_MEMORY_XP		((u64)0x0000000000004000ULL)	/* execute-protect */
+#define EFI_MEMORY_NV		((u64)0x0000000000008000ULL)	/* non-volatile */
+#define EFI_MEMORY_MORE_RELIABLE \
+				((u64)0x0000000000010000ULL)	/* higher reliability */
+#define EFI_MEMORY_RO		((u64)0x0000000000020000ULL)	/* read-only */
+#define EFI_MEMORY_RUNTIME	((u64)0x8000000000000000ULL)	/* range requires runtime mapping */
+#define EFI_MEM_DESC_VERSION	1
+
+#define EFI_PAGE_SHIFT		12
+#define EFI_PAGE_SIZE		(1ULL << EFI_PAGE_SHIFT)
+#define EFI_PAGE_MASK		(EFI_PAGE_SIZE - 1)
+
+struct efi_mem_desc {
+	u32 type;
+	u32 reserved;
+	efi_physical_addr_t physical_start;
+	efi_virtual_addr_t virtual_start;
+	u64 num_pages;
+	u64 attribute;
+};
+
+#define EFI_MEMORY_DESCRIPTOR_VERSION 1
+
+/* Allocation types for calls to boottime->allocate_pages*/
+#define EFI_ALLOCATE_ANY_PAGES		0
+#define EFI_ALLOCATE_MAX_ADDRESS	1
+#define EFI_ALLOCATE_ADDRESS		2
+#define EFI_MAX_ALLOCATE_TYPE		3
+
+/* Types and defines for Time Services */
+#define EFI_TIME_ADJUST_DAYLIGHT 0x1
+#define EFI_TIME_IN_DAYLIGHT     0x2
+#define EFI_UNSPECIFIED_TIMEZONE 0x07ff
+
+struct efi_time {
+	u16 year;
+	u8 month;
+	u8 day;
+	u8 hour;
+	u8 minute;
+	u8 second;
+	u8 pad1;
+	u32 nanosecond;
+	s16 timezone;
+	u8 daylight;
+	u8 pad2;
+};
+
+struct efi_time_cap {
+	u32 resolution;
+	u32 accuracy;
+	u8 sets_to_zero;
+};
+
+enum efi_locate_search_type {
+	ALL_HANDLES,
+	BY_REGISTER_NOTIFY,
+	BY_PROTOCOL
+};
+
+struct efi_open_protocol_info_entry {
+	efi_handle_t agent_handle;
+	efi_handle_t controller_handle;
+	u32 attributes;
+	u32 open_count;
+};
+
+enum efi_entry_t {
+	EFIET_END,	/* Signals this is the last (empty) entry */
+	EFIET_MEMORY_MAP,
+	EFIET_GOP_MODE,
+	EFIET_SYS_TABLE,
+
+	/* Number of entries */
+	EFIET_MEMORY_COUNT,
+};
+
+#define EFI_TABLE_VERSION	1
+
+/**
+ * struct efi_info_hdr - Header for the EFI info table
+ *
+ * @version:	EFI_TABLE_VERSION
+ * @hdr_size:	Size of this struct in bytes
+ * @total_size:	Total size of this header plus following data
+ * @spare:	Spare space for expansion
+ */
+struct efi_info_hdr {
+	u32 version;
+	u32 hdr_size;
+	u32 total_size;
+	u32 spare[5];
+};
+
+/**
+ * struct efi_entry_hdr - Header for a table entry
+ *
+ * @type:	enum eft_entry_t
+ * @size	size of entry bytes excluding header and padding
+ * @addr:	address of this entry (0 if it follows the header )
+ * @link:	size of entry including header and padding
+ * @spare1:	Spare space for expansion
+ * @spare2:	Spare space for expansion
+ */
+struct efi_entry_hdr {
+	u32 type;
+	u32 size;
+	u64 addr;
+	u32 link;
+	u32 spare1;
+	u64 spare2;
+};
+
+/**
+ * struct efi_entry_memmap - a memory map table passed to U-Boot
+ *
+ * @version:	EFI's memory map table version
+ * @desc_size:	EFI's size of each memory descriptor
+ * @spare:	Spare space for expansion
+ * @desc:	An array of descriptors, each @desc_size bytes apart
+ */
+struct efi_entry_memmap {
+	u32 version;
+	u32 desc_size;
+	u64 spare;
+	struct efi_mem_desc desc[];
+};
+
+/**
+ * struct efi_entry_gopmode - a GOP mode table passed to U-Boot
+ *
+ * @fb_base:	EFI's framebuffer base address
+ * @fb_size:	EFI's framebuffer size
+ * @info_size:	GOP mode info structure size
+ * @info:	Start address of the GOP mode info structure
+ */
+struct efi_entry_gopmode {
+	efi_physical_addr_t fb_base;
+	/*
+	 * Not like the ones in 'struct efi_gop_mode' which are 'unsigned
+	 * long', @fb_size and @info_size have to be 'u64' here. As the EFI
+	 * stub codes may have different bit size from the U-Boot payload,
+	 * using 'long' will cause mismatch between the producer (stub) and
+	 * the consumer (payload).
+	 */
+	u64 fb_size;
+	u64 info_size;
+	/*
+	 * We cannot directly use 'struct efi_gop_mode_info info[]' here as
+	 * it causes compiler to complain: array type has incomplete element
+	 * type 'struct efi_gop_mode_info'.
+	 */
+	struct /* efi_gop_mode_info */ {
+		u32 version;
+		u32 width;
+		u32 height;
+		u32 pixel_format;
+		u32 pixel_bitmask[4];
+		u32 pixels_per_scanline;
+	} info[];
+};
+
+/**
+ * struct efi_entry_systable - system table passed to U-Boot
+ *
+ * @sys_table:	EFI system table address
+ */
+struct efi_entry_systable {
+	efi_physical_addr_t sys_table;
+};
+
+static inline struct efi_mem_desc *efi_get_next_mem_desc(
+		struct efi_entry_memmap *map, struct efi_mem_desc *desc)
+{
+	return (struct efi_mem_desc *)((ulong)desc + map->desc_size);
+}
+
+struct efi_priv {
+	efi_handle_t parent_image;
+	struct efi_device_path *device_path;
+	struct efi_system_table *sys_table;
+	struct efi_boot_services *boot;
+	struct efi_runtime_services *run;
+	bool use_pool_for_malloc;
+	unsigned long ram_base;
+	unsigned int image_data_type;
+	struct efi_info_hdr *info;
+	unsigned int info_size;
+	void *next_hdr;
+};
+
+/* Base address of the EFI image */
+extern char image_base[];
+
+/* Start and end of U-Boot image (for payload) */
+extern char _binary_u_boot_bin_start[], _binary_u_boot_bin_end[];
+
+/*
+ * Variable Attributes
+ */
+#define EFI_VARIABLE_NON_VOLATILE       0x0000000000000001
+#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x0000000000000002
+#define EFI_VARIABLE_RUNTIME_ACCESS     0x0000000000000004
+#define EFI_VARIABLE_HARDWARE_ERROR_RECORD 0x0000000000000008
+#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 0x0000000000000010
+#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS 0x0000000000000020
+#define EFI_VARIABLE_APPEND_WRITE	0x0000000000000040
+
+#define EFI_VARIABLE_MASK	(EFI_VARIABLE_NON_VOLATILE | \
+				EFI_VARIABLE_BOOTSERVICE_ACCESS | \
+				EFI_VARIABLE_RUNTIME_ACCESS | \
+				EFI_VARIABLE_HARDWARE_ERROR_RECORD | \
+				EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS | \
+				EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS | \
+				EFI_VARIABLE_APPEND_WRITE)
+
+/**
+ * efi_get_sys_table() - Get access to the main EFI system table
+ *
+ * @return pointer to EFI system table
+ */
+
+struct efi_system_table *efi_get_sys_table(void);
+
+/**
+ * efi_get_ram_base() - Find the base of RAM
+ *
+ * This is used when U-Boot is built as an EFI application.
+ *
+ * @return the base of RAM as known to U-Boot
+ */
+unsigned long efi_get_ram_base(void);
+
+/**
+ * efi_init() - Set up ready for use of EFI boot services
+ *
+ * @priv:	Pointer to our private EFI structure to fill in
+ * @banner:	Banner to display when starting
+ * @image:	The image handle passed to efi_main()
+ * @sys_table:	The EFI system table pointer passed to efi_main()
+ */
+int efi_init(struct efi_priv *priv, const char *banner, efi_handle_t image,
+	     struct efi_system_table *sys_table);
+
+/**
+ * efi_malloc() - Allocate some memory from EFI
+ *
+ * @priv:	Pointer to private EFI structure
+ * @size:	Number of bytes to allocate
+ * @retp:	Return EFI status result
+ * @return pointer to memory allocated, or NULL on error
+ */
+void *efi_malloc(struct efi_priv *priv, int size, efi_status_t *retp);
+
+/**
+ * efi_free() - Free memory allocated from EFI
+ *
+ * @priv:	Pointer to private EFI structure
+ * @ptr:	Pointer to memory to free
+ */
+void efi_free(struct efi_priv *priv, void *ptr);
+
+/**
+ * efi_puts() - Write out a string to the EFI console
+ *
+ * @priv:	Pointer to private EFI structure
+ * @str:	String to write (note this is a ASCII, not unicode)
+ */
+void efi_puts(struct efi_priv *priv, const char *str);
+
+/**
+ * efi_putc() - Write out a character to the EFI console
+ *
+ * @priv:	Pointer to private EFI structure
+ * @ch:		Character to write (note this is not unicode)
+ */
+void efi_putc(struct efi_priv *priv, const char ch);
+
+/**
+ * efi_info_get() - get an entry from an EFI table
+ *
+ * @type:	Entry type to search for
+ * @datap:	Returns pointer to entry data
+ * @sizep:	Returns pointer to entry size
+ * @return 0 if OK, -ENODATA if there is no table, -ENOENT if there is no entry
+ * of the requested type, -EPROTONOSUPPORT if the table has the wrong version
+ */
+int efi_info_get(enum efi_entry_t type, void **datap, int *sizep);
+
+/**
+ * efi_build_mem_table() - make a sorted copy of the memory table
+ *
+ * @map:	Pointer to EFI memory map table
+ * @size:	Size of table in bytes
+ * @skip_bs:	True to skip boot-time memory and merge it with conventional
+ *		memory. This will significantly reduce the number of table
+ *		entries.
+ * @return pointer to the new table. It should be freed with free() by the
+ *	   caller
+ */
+void *efi_build_mem_table(struct efi_entry_memmap *map, int size, bool skip_bs);
+
+#endif /* _LINUX_EFI_H */
diff --git a/include/efi_api.h b/include/efi_api.h
new file mode 100644
index 0000000..2239617
--- /dev/null
+++ b/include/efi_api.h
@@ -0,0 +1,1619 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Extensible Firmware Interface
+ * Based on 'Extensible Firmware Interface Specification' version 0.9,
+ * April 30, 1999
+ *
+ * Copyright (C) 1999 VA Linux Systems
+ * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
+ * Copyright (C) 1999, 2002-2003 Hewlett-Packard Co.
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
+ *	Stephane Eranian <eranian@hpl.hp.com>
+ *
+ * From include/linux/efi.h in kernel 4.1 with some additions/subtractions
+ */
+
+#ifndef _EFI_API_H
+#define _EFI_API_H
+
+#include <efi.h>
+#include <charset.h>
+
+#ifdef CONFIG_EFI_LOADER
+#include <asm/setjmp.h>
+#endif
+
+/* UEFI spec version 2.8 */
+#define EFI_SPECIFICATION_VERSION (2 << 16 | 80)
+
+/* Types and defines for EFI CreateEvent */
+enum efi_timer_delay {
+	EFI_TIMER_STOP = 0,
+	EFI_TIMER_PERIODIC = 1,
+	EFI_TIMER_RELATIVE = 2
+};
+
+#define efi_intn_t ssize_t
+#define efi_uintn_t size_t
+typedef void *efi_hii_handle_t;
+typedef u16 *efi_string_t;
+typedef u16 efi_string_id_t;
+typedef u32 efi_hii_font_style_t;
+typedef u16 efi_question_id_t;
+typedef u16 efi_image_id_t;
+typedef u16 efi_form_id_t;
+
+#define EVT_TIMER				0x80000000
+#define EVT_RUNTIME				0x40000000
+#define EVT_NOTIFY_WAIT				0x00000100
+#define EVT_NOTIFY_SIGNAL			0x00000200
+#define EVT_SIGNAL_EXIT_BOOT_SERVICES		0x00000201
+#define EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE	0x60000202
+
+#define TPL_APPLICATION		0x04
+#define TPL_CALLBACK		0x08
+#define TPL_NOTIFY		0x10
+#define TPL_HIGH_LEVEL		0x1F
+
+struct efi_event;
+
+/* EFI Boot Services table */
+#define EFI_BOOT_SERVICES_SIGNATURE 0x56524553544f4f42
+struct efi_boot_services {
+	struct efi_table_hdr hdr;
+	efi_status_t (EFIAPI *raise_tpl)(efi_uintn_t new_tpl);
+	void (EFIAPI *restore_tpl)(efi_uintn_t old_tpl);
+
+	efi_status_t (EFIAPI *allocate_pages)(int, int, efi_uintn_t,
+					      efi_physical_addr_t *);
+	efi_status_t (EFIAPI *free_pages)(efi_physical_addr_t, efi_uintn_t);
+	efi_status_t (EFIAPI *get_memory_map)(efi_uintn_t *memory_map_size,
+					      struct efi_mem_desc *desc,
+					      efi_uintn_t *key,
+					      efi_uintn_t *desc_size,
+					      u32 *desc_version);
+	efi_status_t (EFIAPI *allocate_pool)(int, efi_uintn_t, void **);
+	efi_status_t (EFIAPI *free_pool)(void *);
+
+	efi_status_t (EFIAPI *create_event)(uint32_t type,
+			efi_uintn_t notify_tpl,
+			void (EFIAPI *notify_function) (
+					struct efi_event *event,
+					void *context),
+			void *notify_context, struct efi_event **event);
+	efi_status_t (EFIAPI *set_timer)(struct efi_event *event,
+					 enum efi_timer_delay type,
+					 uint64_t trigger_time);
+	efi_status_t (EFIAPI *wait_for_event)(efi_uintn_t number_of_events,
+					      struct efi_event **event,
+					      efi_uintn_t *index);
+	efi_status_t (EFIAPI *signal_event)(struct efi_event *event);
+	efi_status_t (EFIAPI *close_event)(struct efi_event *event);
+	efi_status_t (EFIAPI *check_event)(struct efi_event *event);
+#define EFI_NATIVE_INTERFACE	0x00000000
+	efi_status_t (EFIAPI *install_protocol_interface)(
+			efi_handle_t *handle, const efi_guid_t *protocol,
+			int protocol_interface_type, void *protocol_interface);
+	efi_status_t (EFIAPI *reinstall_protocol_interface)(
+			efi_handle_t handle, const efi_guid_t *protocol,
+			void *old_interface, void *new_interface);
+	efi_status_t (EFIAPI *uninstall_protocol_interface)(
+			efi_handle_t handle, const efi_guid_t *protocol,
+			void *protocol_interface);
+	efi_status_t (EFIAPI *handle_protocol)(
+			efi_handle_t handle, const efi_guid_t *protocol,
+			void **protocol_interface);
+	void *reserved;
+	efi_status_t (EFIAPI *register_protocol_notify)(
+			const efi_guid_t *protocol, struct efi_event *event,
+			void **registration);
+	efi_status_t (EFIAPI *locate_handle)(
+			enum efi_locate_search_type search_type,
+			const efi_guid_t *protocol, void *search_key,
+			efi_uintn_t *buffer_size, efi_handle_t *buffer);
+	efi_status_t (EFIAPI *locate_device_path)(const efi_guid_t *protocol,
+			struct efi_device_path **device_path,
+			efi_handle_t *device);
+	efi_status_t (EFIAPI *install_configuration_table)(
+			efi_guid_t *guid, void *table);
+
+	efi_status_t (EFIAPI *load_image)(bool boot_policiy,
+			efi_handle_t parent_image,
+			struct efi_device_path *file_path, void *source_buffer,
+			efi_uintn_t source_size, efi_handle_t *image);
+	efi_status_t (EFIAPI *start_image)(efi_handle_t handle,
+					   efi_uintn_t *exitdata_size,
+					   u16 **exitdata);
+	efi_status_t (EFIAPI *exit)(efi_handle_t handle,
+				    efi_status_t exit_status,
+				    efi_uintn_t exitdata_size, u16 *exitdata);
+	efi_status_t (EFIAPI *unload_image)(efi_handle_t image_handle);
+	efi_status_t (EFIAPI *exit_boot_services)(efi_handle_t image_handle,
+						  efi_uintn_t map_key);
+
+	efi_status_t (EFIAPI *get_next_monotonic_count)(u64 *count);
+	efi_status_t (EFIAPI *stall)(unsigned long usecs);
+	efi_status_t (EFIAPI *set_watchdog_timer)(unsigned long timeout,
+			uint64_t watchdog_code, unsigned long data_size,
+			uint16_t *watchdog_data);
+	efi_status_t(EFIAPI *connect_controller)(efi_handle_t controller_handle,
+			efi_handle_t *driver_image_handle,
+			struct efi_device_path *remaining_device_path,
+			bool recursive);
+	efi_status_t (EFIAPI *disconnect_controller)(
+			efi_handle_t controller_handle,
+			efi_handle_t driver_image_handle,
+			efi_handle_t child_handle);
+#define EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL  0x00000001
+#define EFI_OPEN_PROTOCOL_GET_PROTOCOL        0x00000002
+#define EFI_OPEN_PROTOCOL_TEST_PROTOCOL       0x00000004
+#define EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER 0x00000008
+#define EFI_OPEN_PROTOCOL_BY_DRIVER           0x00000010
+#define EFI_OPEN_PROTOCOL_EXCLUSIVE           0x00000020
+	efi_status_t (EFIAPI *open_protocol)(efi_handle_t handle,
+			const efi_guid_t *protocol, void **interface,
+			efi_handle_t agent_handle,
+			efi_handle_t controller_handle, u32 attributes);
+	efi_status_t (EFIAPI *close_protocol)(
+			efi_handle_t handle, const efi_guid_t *protocol,
+			efi_handle_t agent_handle,
+			efi_handle_t controller_handle);
+	efi_status_t(EFIAPI *open_protocol_information)(efi_handle_t handle,
+			const efi_guid_t *protocol,
+			struct efi_open_protocol_info_entry **entry_buffer,
+			efi_uintn_t *entry_count);
+	efi_status_t (EFIAPI *protocols_per_handle)(efi_handle_t handle,
+			efi_guid_t ***protocol_buffer,
+			efi_uintn_t *protocols_buffer_count);
+	efi_status_t (EFIAPI *locate_handle_buffer) (
+			enum efi_locate_search_type search_type,
+			const efi_guid_t *protocol, void *search_key,
+			efi_uintn_t *no_handles, efi_handle_t **buffer);
+	efi_status_t (EFIAPI *locate_protocol)(const efi_guid_t *protocol,
+			void *registration, void **protocol_interface);
+	efi_status_t (EFIAPI *install_multiple_protocol_interfaces)(
+			efi_handle_t *handle, ...);
+	efi_status_t (EFIAPI *uninstall_multiple_protocol_interfaces)(
+			efi_handle_t handle, ...);
+	efi_status_t (EFIAPI *calculate_crc32)(const void *data,
+					       efi_uintn_t data_size,
+					       u32 *crc32);
+	void (EFIAPI *copy_mem)(void *destination, const void *source,
+			size_t length);
+	void (EFIAPI *set_mem)(void *buffer, size_t size, uint8_t value);
+	efi_status_t (EFIAPI *create_event_ex)(
+				uint32_t type, efi_uintn_t notify_tpl,
+				void (EFIAPI *notify_function) (
+					struct efi_event *event,
+					void *context),
+				void *notify_context,
+				efi_guid_t *event_group,
+				struct efi_event **event);
+};
+
+/* Types and defines for EFI ResetSystem */
+enum efi_reset_type {
+	EFI_RESET_COLD = 0,
+	EFI_RESET_WARM = 1,
+	EFI_RESET_SHUTDOWN = 2,
+	EFI_RESET_PLATFORM_SPECIFIC = 3,
+};
+
+/* EFI Runtime Services table */
+#define EFI_RUNTIME_SERVICES_SIGNATURE	0x56524553544e5552ULL
+
+#define CAPSULE_FLAGS_PERSIST_ACROSS_RESET	0x00010000
+#define CAPSULE_FLAGS_POPULATE_SYSTEM_TABLE	0x00020000
+#define CAPSULE_FLAGS_INITIATE_RESET		0x00040000
+
+struct efi_capsule_header {
+	efi_guid_t *capsule_guid;
+	u32 header_size;
+	u32 flags;
+	u32 capsule_image_size;
+};
+
+#define EFI_RT_SUPPORTED_GET_TIME			0x0001
+#define EFI_RT_SUPPORTED_SET_TIME			0x0002
+#define EFI_RT_SUPPORTED_GET_WAKEUP_TIME		0x0004
+#define EFI_RT_SUPPORTED_SET_WAKEUP_TIME		0x0008
+#define EFI_RT_SUPPORTED_GET_VARIABLE			0x0010
+#define EFI_RT_SUPPORTED_GET_NEXT_VARIABLE_NAME		0x0020
+#define EFI_RT_SUPPORTED_SET_VARIABLE			0x0040
+#define EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP	0x0080
+#define EFI_RT_SUPPORTED_CONVERT_POINTER		0x0100
+#define EFI_RT_SUPPORTED_GET_NEXT_HIGH_MONOTONIC_COUNT	0x0200
+#define EFI_RT_SUPPORTED_RESET_SYSTEM			0x0400
+#define EFI_RT_SUPPORTED_UPDATE_CAPSULE			0x0800
+#define EFI_RT_SUPPORTED_QUERY_CAPSULE_CAPABILITIES	0x1000
+#define EFI_RT_SUPPORTED_QUERY_VARIABLE_INFO		0x2000
+
+struct efi_runtime_services {
+	struct efi_table_hdr hdr;
+	efi_status_t (EFIAPI *get_time)(struct efi_time *time,
+			struct efi_time_cap *capabilities);
+	efi_status_t (EFIAPI *set_time)(struct efi_time *time);
+	efi_status_t (EFIAPI *get_wakeup_time)(char *enabled, char *pending,
+			struct efi_time *time);
+	efi_status_t (EFIAPI *set_wakeup_time)(char enabled,
+			struct efi_time *time);
+	efi_status_t (EFIAPI *set_virtual_address_map)(
+			efi_uintn_t memory_map_size,
+			efi_uintn_t descriptor_size,
+			uint32_t descriptor_version,
+			struct efi_mem_desc *virtmap);
+	efi_status_t (EFIAPI *convert_pointer)(
+			efi_uintn_t debug_disposition, void **address);
+	efi_status_t (EFIAPI *get_variable)(u16 *variable_name,
+					    const efi_guid_t *vendor,
+					    u32 *attributes,
+					    efi_uintn_t *data_size, void *data);
+	efi_status_t (EFIAPI *get_next_variable_name)(
+			efi_uintn_t *variable_name_size,
+			u16 *variable_name, const efi_guid_t *vendor);
+	efi_status_t (EFIAPI *set_variable)(u16 *variable_name,
+					    const efi_guid_t *vendor,
+					    u32 attributes,
+					    efi_uintn_t data_size,
+					    const void *data);
+	efi_status_t (EFIAPI *get_next_high_mono_count)(
+			uint32_t *high_count);
+	void (EFIAPI *reset_system)(enum efi_reset_type reset_type,
+				    efi_status_t reset_status,
+				    unsigned long data_size, void *reset_data);
+	efi_status_t (EFIAPI *update_capsule)(
+			struct efi_capsule_header **capsule_header_array,
+			efi_uintn_t capsule_count,
+			u64 scatter_gather_list);
+	efi_status_t (EFIAPI *query_capsule_caps)(
+			struct efi_capsule_header **capsule_header_array,
+			efi_uintn_t capsule_count,
+			u64 *maximum_capsule_size,
+			u32 *reset_type);
+	efi_status_t (EFIAPI *query_variable_info)(
+			u32 attributes,
+			u64 *maximum_variable_storage_size,
+			u64 *remaining_variable_storage_size,
+			u64 *maximum_variable_size);
+};
+
+/* EFI event group GUID definitions */
+#define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \
+	EFI_GUID(0x27abf055, 0xb1b8, 0x4c26, 0x80, 0x48, \
+		 0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf)
+
+#define EFI_EVENT_GROUP_VIRTUAL_ADDRESS_CHANGE \
+	EFI_GUID(0x13fa7698, 0xc831, 0x49c7, 0x87, 0xea, \
+		 0x8f, 0x43, 0xfc, 0xc2, 0x51, 0x96)
+
+#define EFI_EVENT_GROUP_MEMORY_MAP_CHANGE \
+	EFI_GUID(0x78bee926, 0x692f, 0x48fd, 0x9e, 0xdb, \
+		 0x01, 0x42, 0x2e, 0xf0, 0xd7, 0xab)
+
+#define EFI_EVENT_GROUP_READY_TO_BOOT \
+	EFI_GUID(0x7ce88fb3, 0x4bd7, 0x4679, 0x87, 0xa8, \
+		 0xa8, 0xd8, 0xde, 0xe5, 0x0d, 0x2b)
+
+#define EFI_EVENT_GROUP_RESET_SYSTEM \
+	EFI_GUID(0x62da6a56, 0x13fb, 0x485a, 0xa8, 0xda, \
+		 0xa3, 0xdd, 0x79, 0x12, 0xcb, 0x6b)
+
+/* EFI Configuration Table and GUID definitions */
+#define NULL_GUID \
+	EFI_GUID(0x00000000, 0x0000, 0x0000, 0x00, 0x00, \
+		 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
+
+#define EFI_GLOBAL_VARIABLE_GUID \
+	EFI_GUID(0x8be4df61, 0x93ca, 0x11d2, 0xaa, 0x0d, \
+		 0x00, 0xe0, 0x98, 0x03, 0x2b, 0x8c)
+
+#define EFI_FDT_GUID \
+	EFI_GUID(0xb1b621d5, 0xf19c, 0x41a5, \
+		 0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0)
+
+#define EFI_ACPI_TABLE_GUID \
+	EFI_GUID(0x8868e871, 0xe4f1, 0x11d3, \
+		 0xbc, 0x22, 0x00, 0x80, 0xc7, 0x3c, 0x88, 0x81)
+
+#define SMBIOS_TABLE_GUID \
+	EFI_GUID(0xeb9d2d31, 0x2d88, 0x11d3,  \
+		 0x9a, 0x16, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
+struct efi_configuration_table {
+	efi_guid_t guid;
+	void *table;
+} __packed;
+
+#define EFI_SYSTEM_TABLE_SIGNATURE ((u64)0x5453595320494249ULL)
+
+struct efi_system_table {
+	struct efi_table_hdr hdr;
+	u16 *fw_vendor;   /* physical addr of wchar_t vendor string */
+	u32 fw_revision;
+	efi_handle_t con_in_handle;
+	struct efi_simple_text_input_protocol *con_in;
+	efi_handle_t con_out_handle;
+	struct efi_simple_text_output_protocol *con_out;
+	efi_handle_t stderr_handle;
+	struct efi_simple_text_output_protocol *std_err;
+	struct efi_runtime_services *runtime;
+	struct efi_boot_services *boottime;
+	efi_uintn_t nr_tables;
+	struct efi_configuration_table *tables;
+};
+
+#define EFI_LOADED_IMAGE_PROTOCOL_GUID \
+	EFI_GUID(0x5b1b31a1, 0x9562, 0x11d2, \
+		 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
+#define EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL_GUID \
+	EFI_GUID(0xbc62157e, 0x3e33, 0x4fec, \
+		 0x99, 0x20, 0x2d, 0x3b, 0x36, 0xd7, 0x50, 0xdf)
+
+#define EFI_LOADED_IMAGE_PROTOCOL_REVISION 0x1000
+
+struct efi_loaded_image {
+	u32 revision;
+	void *parent_handle;
+	struct efi_system_table *system_table;
+	efi_handle_t device_handle;
+	struct efi_device_path *file_path;
+	void *reserved;
+	u32 load_options_size;
+	void *load_options;
+	void *image_base;
+	aligned_u64 image_size;
+	unsigned int image_code_type;
+	unsigned int image_data_type;
+	efi_status_t (EFIAPI *unload)(efi_handle_t image_handle);
+};
+
+#define EFI_DEVICE_PATH_PROTOCOL_GUID \
+	EFI_GUID(0x09576e91, 0x6d3f, 0x11d2, \
+		 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
+#define DEVICE_PATH_TYPE_END			0x7f
+#  define DEVICE_PATH_SUB_TYPE_INSTANCE_END	0x01
+#  define DEVICE_PATH_SUB_TYPE_END		0xff
+
+struct efi_device_path {
+	u8 type;
+	u8 sub_type;
+	u16 length;
+} __packed;
+
+struct efi_mac_addr {
+	u8 addr[32];
+} __packed;
+
+#define DEVICE_PATH_TYPE_HARDWARE_DEVICE	0x01
+#  define DEVICE_PATH_SUB_TYPE_MEMORY		0x03
+#  define DEVICE_PATH_SUB_TYPE_VENDOR		0x04
+
+struct efi_device_path_memory {
+	struct efi_device_path dp;
+	u32 memory_type;
+	u64 start_address;
+	u64 end_address;
+} __packed;
+
+struct efi_device_path_vendor {
+	struct efi_device_path dp;
+	efi_guid_t guid;
+	u8 vendor_data[];
+} __packed;
+
+#define DEVICE_PATH_TYPE_ACPI_DEVICE		0x02
+#  define DEVICE_PATH_SUB_TYPE_ACPI_DEVICE	0x01
+
+#define EFI_PNP_ID(ID)				(u32)(((ID) << 16) | 0x41D0)
+#define EISA_PNP_ID(ID)				EFI_PNP_ID(ID)
+#define EISA_PNP_NUM(ID)			((ID) >> 16)
+
+struct efi_device_path_acpi_path {
+	struct efi_device_path dp;
+	u32 hid;
+	u32 uid;
+} __packed;
+
+#define DEVICE_PATH_TYPE_MESSAGING_DEVICE	0x03
+#  define DEVICE_PATH_SUB_TYPE_MSG_ATAPI	0x01
+#  define DEVICE_PATH_SUB_TYPE_MSG_SCSI		0x02
+#  define DEVICE_PATH_SUB_TYPE_MSG_USB		0x05
+#  define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR	0x0b
+#  define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS	0x0f
+#  define DEVICE_PATH_SUB_TYPE_MSG_NVME		0x17
+#  define DEVICE_PATH_SUB_TYPE_MSG_SD		0x1a
+#  define DEVICE_PATH_SUB_TYPE_MSG_MMC		0x1d
+
+struct efi_device_path_atapi {
+	struct efi_device_path dp;
+	u8 primary_secondary;
+	u8 slave_master;
+	u16 logical_unit_number;
+} __packed;
+
+struct efi_device_path_scsi {
+	struct efi_device_path dp;
+	u16 target_id;
+	u16 logical_unit_number;
+} __packed;
+
+struct efi_device_path_usb {
+	struct efi_device_path dp;
+	u8 parent_port_number;
+	u8 usb_interface;
+} __packed;
+
+struct efi_device_path_mac_addr {
+	struct efi_device_path dp;
+	struct efi_mac_addr mac;
+	u8 if_type;
+} __packed;
+
+struct efi_device_path_usb_class {
+	struct efi_device_path dp;
+	u16 vendor_id;
+	u16 product_id;
+	u8 device_class;
+	u8 device_subclass;
+	u8 device_protocol;
+} __packed;
+
+struct efi_device_path_sd_mmc_path {
+	struct efi_device_path dp;
+	u8 slot_number;
+} __packed;
+
+struct efi_device_path_nvme {
+	struct efi_device_path dp;
+	u32 ns_id;
+	u8 eui64[8];
+} __packed;
+
+#define DEVICE_PATH_TYPE_MEDIA_DEVICE		0x04
+#  define DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH	0x01
+#  define DEVICE_PATH_SUB_TYPE_CDROM_PATH	0x02
+#  define DEVICE_PATH_SUB_TYPE_FILE_PATH	0x04
+
+struct efi_device_path_hard_drive_path {
+	struct efi_device_path dp;
+	u32 partition_number;
+	u64 partition_start;
+	u64 partition_end;
+	u8 partition_signature[16];
+	u8 partmap_type;
+	u8 signature_type;
+} __packed;
+
+struct efi_device_path_cdrom_path {
+	struct efi_device_path dp;
+	u32 boot_entry;
+	u64 partition_start;
+	u64 partition_size;
+} __packed;
+
+struct efi_device_path_file_path {
+	struct efi_device_path dp;
+	u16 str[];
+} __packed;
+
+#define EFI_BLOCK_IO_PROTOCOL_GUID \
+	EFI_GUID(0x964e5b21, 0x6459, 0x11d2, \
+		 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
+struct efi_block_io_media {
+	u32 media_id;
+	char removable_media;
+	char media_present;
+	char logical_partition;
+	char read_only;
+	char write_caching;
+	u8 pad[3];
+	u32 block_size;
+	u32 io_align;
+	u8 pad2[4];
+	u64 last_block;
+	/* Added in revision 2 of the protocol */
+	u64 lowest_aligned_lba;
+	u32 logical_blocks_per_physical_block;
+	/* Added in revision 3 of the protocol */
+	u32 optimal_transfer_length_granualarity;
+};
+
+#define EFI_BLOCK_IO_PROTOCOL_REVISION2	0x00020001
+#define EFI_BLOCK_IO_PROTOCOL_REVISION3	0x0002001f
+
+struct efi_block_io {
+	u64 revision;
+	struct efi_block_io_media *media;
+	efi_status_t (EFIAPI *reset)(struct efi_block_io *this,
+			char extended_verification);
+	efi_status_t (EFIAPI *read_blocks)(struct efi_block_io *this,
+			u32 media_id, u64 lba, efi_uintn_t buffer_size,
+			void *buffer);
+	efi_status_t (EFIAPI *write_blocks)(struct efi_block_io *this,
+			u32 media_id, u64 lba, efi_uintn_t buffer_size,
+			void *buffer);
+	efi_status_t (EFIAPI *flush_blocks)(struct efi_block_io *this);
+};
+
+struct simple_text_output_mode {
+	s32 max_mode;
+	s32 mode;
+	s32 attribute;
+	s32 cursor_column;
+	s32 cursor_row;
+	bool cursor_visible;
+};
+
+#define EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID \
+	EFI_GUID(0x387477c2, 0x69c7, 0x11d2, \
+		 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
+#define EFI_BLACK                0x00
+#define EFI_BLUE                 0x01
+#define EFI_GREEN                0x02
+#define EFI_CYAN                 0x03
+#define EFI_RED                  0x04
+#define EFI_MAGENTA              0x05
+#define EFI_BROWN                0x06
+#define EFI_LIGHTGRAY            0x07
+#define EFI_BRIGHT               0x08
+#define EFI_DARKGRAY             0x08
+#define EFI_LIGHTBLUE            0x09
+#define EFI_LIGHTGREEN           0x0a
+#define EFI_LIGHTCYAN            0x0b
+#define EFI_LIGHTRED             0x0c
+#define EFI_LIGHTMAGENTA         0x0d
+#define EFI_YELLOW               0x0e
+#define EFI_WHITE                0x0f
+#define EFI_BACKGROUND_BLACK     0x00
+#define EFI_BACKGROUND_BLUE      0x10
+#define EFI_BACKGROUND_GREEN     0x20
+#define EFI_BACKGROUND_CYAN      0x30
+#define EFI_BACKGROUND_RED       0x40
+#define EFI_BACKGROUND_MAGENTA   0x50
+#define EFI_BACKGROUND_BROWN     0x60
+#define EFI_BACKGROUND_LIGHTGRAY 0x70
+
+/* extract foreground color from EFI attribute */
+#define EFI_ATTR_FG(attr)        ((attr) & 0x07)
+/* treat high bit of FG as bright/bold (similar to edk2) */
+#define EFI_ATTR_BOLD(attr)      (((attr) >> 3) & 0x01)
+/* extract background color from EFI attribute */
+#define EFI_ATTR_BG(attr)        (((attr) >> 4) & 0x7)
+
+struct efi_simple_text_output_protocol {
+	efi_status_t (EFIAPI *reset)(
+			struct efi_simple_text_output_protocol *this,
+			char extended_verification);
+	efi_status_t (EFIAPI *output_string)(
+			struct efi_simple_text_output_protocol *this,
+			const efi_string_t str);
+	efi_status_t (EFIAPI *test_string)(
+			struct efi_simple_text_output_protocol *this,
+			const efi_string_t str);
+	efi_status_t(EFIAPI *query_mode)(
+			struct efi_simple_text_output_protocol *this,
+			unsigned long mode_number, unsigned long *columns,
+			unsigned long *rows);
+	efi_status_t(EFIAPI *set_mode)(
+			struct efi_simple_text_output_protocol *this,
+			unsigned long mode_number);
+	efi_status_t(EFIAPI *set_attribute)(
+			struct efi_simple_text_output_protocol *this,
+			unsigned long attribute);
+	efi_status_t(EFIAPI *clear_screen) (
+			struct efi_simple_text_output_protocol *this);
+	efi_status_t(EFIAPI *set_cursor_position) (
+			struct efi_simple_text_output_protocol *this,
+			unsigned long column, unsigned long row);
+	efi_status_t(EFIAPI *enable_cursor)(
+			struct efi_simple_text_output_protocol *this,
+			bool enable);
+	struct simple_text_output_mode *mode;
+};
+
+#define EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL_GUID \
+	EFI_GUID(0xdd9e7534, 0x7762, 0x4698, \
+		 0x8c, 0x14, 0xf5, 0x85, 0x17, 0xa6, 0x25, 0xaa)
+
+struct efi_input_key {
+	u16 scan_code;
+	s16 unicode_char;
+};
+
+#define EFI_SHIFT_STATE_INVALID		0x00000000
+#define EFI_RIGHT_SHIFT_PRESSED		0x00000001
+#define EFI_LEFT_SHIFT_PRESSED		0x00000002
+#define EFI_RIGHT_CONTROL_PRESSED	0x00000004
+#define EFI_LEFT_CONTROL_PRESSED	0x00000008
+#define EFI_RIGHT_ALT_PRESSED		0x00000010
+#define EFI_LEFT_ALT_PRESSED		0x00000020
+#define EFI_RIGHT_LOGO_PRESSED		0x00000040
+#define EFI_LEFT_LOGO_PRESSED		0x00000080
+#define EFI_MENU_KEY_PRESSED		0x00000100
+#define EFI_SYS_REQ_PRESSED		0x00000200
+#define EFI_SHIFT_STATE_VALID		0x80000000
+
+#define EFI_TOGGLE_STATE_INVALID	0x00
+#define EFI_SCROLL_LOCK_ACTIVE		0x01
+#define EFI_NUM_LOCK_ACTIVE		0x02
+#define EFI_CAPS_LOCK_ACTIVE		0x04
+#define EFI_KEY_STATE_EXPOSED		0x40
+#define EFI_TOGGLE_STATE_VALID		0x80
+
+struct efi_key_state {
+	u32 key_shift_state;
+	u8 key_toggle_state;
+};
+
+struct efi_key_data {
+	struct efi_input_key key;
+	struct efi_key_state key_state;
+};
+
+struct efi_simple_text_input_ex_protocol {
+	efi_status_t (EFIAPI *reset) (
+		struct efi_simple_text_input_ex_protocol *this,
+		bool extended_verification);
+	efi_status_t (EFIAPI *read_key_stroke_ex) (
+		struct efi_simple_text_input_ex_protocol *this,
+		struct efi_key_data *key_data);
+	struct efi_event *wait_for_key_ex;
+	efi_status_t (EFIAPI *set_state) (
+		struct efi_simple_text_input_ex_protocol *this,
+		u8 *key_toggle_state);
+	efi_status_t (EFIAPI *register_key_notify) (
+		struct efi_simple_text_input_ex_protocol *this,
+		struct efi_key_data *key_data,
+		efi_status_t (EFIAPI *key_notify_function)(
+			struct efi_key_data *key_data),
+		void **notify_handle);
+	efi_status_t (EFIAPI *unregister_key_notify) (
+		struct efi_simple_text_input_ex_protocol *this,
+		void *notification_handle);
+};
+
+#define EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID \
+	EFI_GUID(0x387477c1, 0x69c7, 0x11d2, \
+		 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
+struct efi_simple_text_input_protocol {
+	efi_status_t(EFIAPI *reset)(struct efi_simple_text_input_protocol *this,
+				    bool extended_verification);
+	efi_status_t(EFIAPI *read_key_stroke)(
+			struct efi_simple_text_input_protocol *this,
+			struct efi_input_key *key);
+	struct efi_event *wait_for_key;
+};
+
+#define EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID \
+	EFI_GUID(0x8b843e20, 0x8132, 0x4852, \
+		 0x90, 0xcc, 0x55, 0x1a, 0x4e, 0x4a, 0x7f, 0x1c)
+
+struct efi_device_path_to_text_protocol {
+	uint16_t *(EFIAPI *convert_device_node_to_text)(
+			struct efi_device_path *device_node,
+			bool display_only,
+			bool allow_shortcuts);
+	uint16_t *(EFIAPI *convert_device_path_to_text)(
+			struct efi_device_path *device_path,
+			bool display_only,
+			bool allow_shortcuts);
+};
+
+#define EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID \
+	EFI_GUID(0x0379be4e, 0xd706, 0x437d, \
+		 0xb0, 0x37, 0xed, 0xb8, 0x2f, 0xb7, 0x72, 0xa4)
+
+struct efi_device_path_utilities_protocol {
+	efi_uintn_t (EFIAPI *get_device_path_size)(
+		const struct efi_device_path *device_path);
+	struct efi_device_path *(EFIAPI *duplicate_device_path)(
+		const struct efi_device_path *device_path);
+	struct efi_device_path *(EFIAPI *append_device_path)(
+		const struct efi_device_path *src1,
+		const struct efi_device_path *src2);
+	struct efi_device_path *(EFIAPI *append_device_node)(
+		const struct efi_device_path *device_path,
+		const struct efi_device_path *device_node);
+	struct efi_device_path *(EFIAPI *append_device_path_instance)(
+		const struct efi_device_path *device_path,
+		const struct efi_device_path *device_path_instance);
+	struct efi_device_path *(EFIAPI *get_next_device_path_instance)(
+		struct efi_device_path **device_path_instance,
+		efi_uintn_t *device_path_instance_size);
+	bool (EFIAPI *is_device_path_multi_instance)(
+		const struct efi_device_path *device_path);
+	struct efi_device_path *(EFIAPI *create_device_node)(
+		uint8_t node_type,
+		uint8_t node_sub_type,
+		uint16_t node_length);
+};
+
+/*
+ * Human Interface Infrastructure (HII)
+ */
+struct efi_hii_package_list_header {
+	efi_guid_t package_list_guid;
+	u32 package_length;
+} __packed;
+
+/**
+ * struct efi_hii_package_header - EFI HII package header
+ *
+ * @fields:	'fields' replaces the bit-fields defined in the EFI
+ *		specification to to avoid possible compiler incompatibilities::
+ *
+ *		u32 length:24;
+ *		u32 type:8;
+ */
+struct efi_hii_package_header {
+	u32 fields;
+} __packed;
+
+#define __EFI_HII_PACKAGE_LEN_SHIFT	0
+#define __EFI_HII_PACKAGE_TYPE_SHIFT	24
+#define __EFI_HII_PACKAGE_LEN_MASK	0xffffff
+#define __EFI_HII_PACKAGE_TYPE_MASK	0xff
+
+#define EFI_HII_PACKAGE_TYPE_ALL          0x00
+#define EFI_HII_PACKAGE_TYPE_GUID         0x01
+#define EFI_HII_PACKAGE_FORMS             0x02
+#define EFI_HII_PACKAGE_STRINGS           0x04
+#define EFI_HII_PACKAGE_FONTS             0x05
+#define EFI_HII_PACKAGE_IMAGES            0x06
+#define EFI_HII_PACKAGE_SIMPLE_FONTS      0x07
+#define EFI_HII_PACKAGE_DEVICE_PATH       0x08
+#define EFI_HII_PACKAGE_KEYBOARD_LAYOUT   0x09
+#define EFI_HII_PACKAGE_ANIMATIONS        0x0A
+#define EFI_HII_PACKAGE_END               0xDF
+#define EFI_HII_PACKAGE_TYPE_SYSTEM_BEGIN 0xE0
+#define EFI_HII_PACKAGE_TYPE_SYSTEM_END   0xFF
+
+/*
+ * HII GUID package
+ */
+struct efi_hii_guid_package {
+	struct efi_hii_package_header header;
+	efi_guid_t guid;
+	char data[];
+} __packed;
+
+/*
+ * HII string package
+ */
+struct efi_hii_strings_package {
+	struct efi_hii_package_header header;
+	u32 header_size;
+	u32 string_info_offset;
+	u16 language_window[16];
+	efi_string_id_t language_name;
+	u8  language[];
+} __packed;
+
+struct efi_hii_string_block {
+	u8 block_type;
+	/* u8 block_body[]; */
+} __packed;
+
+#define EFI_HII_SIBT_END               0x00
+#define EFI_HII_SIBT_STRING_SCSU       0x10
+#define EFI_HII_SIBT_STRING_SCSU_FONT  0x11
+#define EFI_HII_SIBT_STRINGS_SCSU      0x12
+#define EFI_HII_SIBT_STRINGS_SCSU_FONT 0x13
+#define EFI_HII_SIBT_STRING_UCS2       0x14
+#define EFI_HII_SIBT_STRING_UCS2_FONT  0x15
+#define EFI_HII_SIBT_STRINGS_UCS2      0x16
+#define EFI_HII_SIBT_STRINGS_UCS2_FONT 0x17
+#define EFI_HII_SIBT_DUPLICATE         0x20
+#define EFI_HII_SIBT_SKIP2             0x21
+#define EFI_HII_SIBT_SKIP1             0x22
+#define EFI_HII_SIBT_EXT1              0x30
+#define EFI_HII_SIBT_EXT2              0x31
+#define EFI_HII_SIBT_EXT4              0x32
+#define EFI_HII_SIBT_FONT              0x40
+
+struct efi_hii_sibt_string_ucs2_block {
+	struct efi_hii_string_block header;
+	u16 string_text[];
+} __packed;
+
+static inline struct efi_hii_string_block *
+efi_hii_sibt_string_ucs2_block_next(struct efi_hii_sibt_string_ucs2_block *blk)
+{
+	return ((void *)blk) + sizeof(*blk) +
+		(u16_strlen(blk->string_text) + 1) * 2;
+}
+
+/*
+ * HII forms package
+ * TODO: full scope of definitions
+ */
+struct efi_hii_time {
+	u8 hour;
+	u8 minute;
+	u8 second;
+};
+
+struct efi_hii_date {
+	u16 year;
+	u8 month;
+	u8 day;
+};
+
+struct efi_hii_ref {
+	efi_question_id_t question_id;
+	efi_form_id_t form_id;
+	efi_guid_t form_set_guid;
+	efi_string_id_t device_path;
+};
+
+union efi_ifr_type_value {
+	u8 u8;				// EFI_IFR_TYPE_NUM_SIZE_8
+	u16 u16;			// EFI_IFR_TYPE_NUM_SIZE_16
+	u32 u32;			// EFI_IFR_TYPE_NUM_SIZE_32
+	u64 u64;			// EFI_IFR_TYPE_NUM_SIZE_64
+	bool b;				// EFI_IFR_TYPE_BOOLEAN
+	struct efi_hii_time time;	// EFI_IFR_TYPE_TIME
+	struct efi_hii_date date;	// EFI_IFR_TYPE_DATE
+	efi_string_id_t string;	// EFI_IFR_TYPE_STRING, EFI_IFR_TYPE_ACTION
+	struct efi_hii_ref ref;		// EFI_IFR_TYPE_REF
+	// u8 buffer[];			// EFI_IFR_TYPE_BUFFER
+};
+
+#define EFI_IFR_TYPE_NUM_SIZE_8		0x00
+#define EFI_IFR_TYPE_NUM_SIZE_16	0x01
+#define EFI_IFR_TYPE_NUM_SIZE_32	0x02
+#define EFI_IFR_TYPE_NUM_SIZE_64	0x03
+#define EFI_IFR_TYPE_BOOLEAN		0x04
+#define EFI_IFR_TYPE_TIME		0x05
+#define EFI_IFR_TYPE_DATE		0x06
+#define EFI_IFR_TYPE_STRING		0x07
+#define EFI_IFR_TYPE_OTHER		0x08
+#define EFI_IFR_TYPE_UNDEFINED		0x09
+#define EFI_IFR_TYPE_ACTION		0x0A
+#define EFI_IFR_TYPE_BUFFER		0x0B
+#define EFI_IFR_TYPE_REF		0x0C
+#define EFI_IFR_OPTION_DEFAULT		0x10
+#define EFI_IFR_OPTION_DEFAULT_MFG	0x20
+
+#define EFI_IFR_ONE_OF_OPTION_OP	0x09
+
+struct efi_ifr_op_header {
+	u8 opCode;
+	u8 length:7;
+	u8 scope:1;
+};
+
+struct efi_ifr_one_of_option {
+	struct efi_ifr_op_header header;
+	efi_string_id_t option;
+	u8 flags;
+	u8 type;
+	union efi_ifr_type_value value;
+};
+
+typedef efi_uintn_t efi_browser_action_t;
+
+#define EFI_BROWSER_ACTION_REQUEST_NONE			0
+#define EFI_BROWSER_ACTION_REQUEST_RESET		1
+#define EFI_BROWSER_ACTION_REQUEST_SUBMIT		2
+#define EFI_BROWSER_ACTION_REQUEST_EXIT			3
+#define EFI_BROWSER_ACTION_REQUEST_FORM_SUBMIT_EXIT	4
+#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD_EXIT	5
+#define EFI_BROWSER_ACTION_REQUEST_FORM_APPLY		6
+#define EFI_BROWSER_ACTION_REQUEST_FORM_DISCARD		7
+#define EFI_BROWSER_ACTION_REQUEST_RECONNECT		8
+
+typedef efi_uintn_t efi_browser_action_request_t;
+
+#define EFI_BROWSER_ACTION_CHANGING			0
+#define EFI_BROWSER_ACTION_CHANGED			1
+#define EFI_BROWSER_ACTION_RETRIEVE			2
+#define EFI_BROWSER_ACTION_FORM_OPEN			3
+#define EFI_BROWSER_ACTION_FORM_CLOSE			4
+#define EFI_BROWSER_ACTION_SUBMITTED			5
+#define EFI_BROWSER_ACTION_DEFAULT_STANDARD		0x1000
+#define EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING	0x1001
+#define EFI_BROWSER_ACTION_DEFAULT_SAFE			0x1002
+#define EFI_BROWSER_ACTION_DEFAULT_PLATFORM		0x2000
+#define EFI_BROWSER_ACTION_DEFAULT_HARDWARE		0x3000
+#define EFI_BROWSER_ACTION_DEFAULT_FIRMWARE		0x4000
+
+/*
+ * HII keyboard package
+ */
+typedef enum {
+	EFI_KEY_LCTRL, EFI_KEY_A0, EFI_KEY_LALT, EFI_KEY_SPACE_BAR,
+	EFI_KEY_A2, EFI_KEY_A3, EFI_KEY_A4, EFI_KEY_RCTRL, EFI_KEY_LEFT_ARROW,
+	EFI_KEY_DOWN_ARROW, EFI_KEY_RIGHT_ARROW, EFI_KEY_ZERO,
+	EFI_KEY_PERIOD, EFI_KEY_ENTER, EFI_KEY_LSHIFT, EFI_KEY_B0,
+	EFI_KEY_B1, EFI_KEY_B2, EFI_KEY_B3, EFI_KEY_B4, EFI_KEY_B5, EFI_KEY_B6,
+	EFI_KEY_B7, EFI_KEY_B8, EFI_KEY_B9, EFI_KEY_B10, EFI_KEY_RSHIFT,
+	EFI_KEY_UP_ARROW, EFI_KEY_ONE, EFI_KEY_TWO, EFI_KEY_THREE,
+	EFI_KEY_CAPS_LOCK, EFI_KEY_C1, EFI_KEY_C2, EFI_KEY_C3, EFI_KEY_C4,
+	EFI_KEY_C5, EFI_KEY_C6, EFI_KEY_C7, EFI_KEY_C8, EFI_KEY_C9,
+	EFI_KEY_C10, EFI_KEY_C11, EFI_KEY_C12, EFI_KEY_FOUR, EFI_KEY_FIVE,
+	EFI_KEY_SIX, EFI_KEY_PLUS, EFI_KEY_TAB, EFI_KEY_D1, EFI_KEY_D2,
+	EFI_KEY_D3, EFI_KEY_D4, EFI_KEY_D5, EFI_KEY_D6, EFI_KEY_D7, EFI_KEY_D8,
+	EFI_KEY_D9, EFI_KEY_D10, EFI_KEY_D11, EFI_KEY_D12, EFI_KEY_D13,
+	EFI_KEY_DEL, EFI_KEY_END, EFI_KEY_PG_DN, EFI_KEY_SEVEN, EFI_KEY_EIGHT,
+	EFI_KEY_NINE, EFI_KEY_E0, EFI_KEY_E1, EFI_KEY_E2, EFI_KEY_E3,
+	EFI_KEY_E4, EFI_KEY_E5, EFI_KEY_E6, EFI_KEY_E7, EFI_KEY_E8, EFI_KEY_E9,
+	EFI_KEY_E10, EFI_KEY_E11, EFI_KEY_E12, EFI_KEY_BACK_SPACE,
+	EFI_KEY_INS, EFI_KEY_HOME, EFI_KEY_PG_UP, EFI_KEY_NLCK, EFI_KEY_SLASH,
+	EFI_KEY_ASTERISK, EFI_KEY_MINUS, EFI_KEY_ESC, EFI_KEY_F1, EFI_KEY_F2,
+	EFI_KEY_F3, EFI_KEY_F4, EFI_KEY_F5, EFI_KEY_F6, EFI_KEY_F7, EFI_KEY_F8,
+	EFI_KEY_F9, EFI_KEY_F10, EFI_KEY_F11, EFI_KEY_F12, EFI_KEY_PRINT,
+	EFI_KEY_SLCK, EFI_KEY_PAUSE,
+} efi_key;
+
+struct efi_key_descriptor {
+	u32 key;
+	u16 unicode;
+	u16 shifted_unicode;
+	u16 alt_gr_unicode;
+	u16 shifted_alt_gr_unicode;
+	u16 modifier;
+	u16 affected_attribute;
+} __packed;
+
+struct efi_hii_keyboard_layout {
+	u16 layout_length;
+	efi_guid_t guid;
+	u32 layout_descriptor_string_offset;
+	u8 descriptor_count;
+	struct efi_key_descriptor descriptors[];
+} __packed;
+
+struct efi_hii_keyboard_package {
+	struct efi_hii_package_header header;
+	u16 layout_count;
+	struct efi_hii_keyboard_layout layout[];
+} __packed;
+
+/*
+ * HII protocols
+ */
+#define EFI_HII_STRING_PROTOCOL_GUID \
+	EFI_GUID(0x0fd96974, 0x23aa, 0x4cdc, \
+		 0xb9, 0xcb, 0x98, 0xd1, 0x77, 0x50, 0x32, 0x2a)
+
+struct efi_font_info {
+	efi_hii_font_style_t font_style;
+	u16 font_size;
+	u16 font_name[1];
+};
+
+struct efi_hii_string_protocol {
+	efi_status_t(EFIAPI *new_string)(
+		const struct efi_hii_string_protocol *this,
+		efi_hii_handle_t package_list,
+		efi_string_id_t *string_id,
+		const u8 *language,
+		const u16 *language_name,
+		const efi_string_t string,
+		const struct efi_font_info *string_font_info);
+	efi_status_t(EFIAPI *get_string)(
+		const struct efi_hii_string_protocol *this,
+		const u8 *language,
+		efi_hii_handle_t package_list,
+		efi_string_id_t string_id,
+		efi_string_t string,
+		efi_uintn_t *string_size,
+		struct efi_font_info **string_font_info);
+	efi_status_t(EFIAPI *set_string)(
+		const struct efi_hii_string_protocol *this,
+		efi_hii_handle_t package_list,
+		efi_string_id_t string_id,
+		const u8 *language,
+		const efi_string_t string,
+		const struct efi_font_info *string_font_info);
+	efi_status_t(EFIAPI *get_languages)(
+		const struct efi_hii_string_protocol *this,
+		efi_hii_handle_t package_list,
+		u8 *languages,
+		efi_uintn_t *languages_size);
+	efi_status_t(EFIAPI *get_secondary_languages)(
+		const struct efi_hii_string_protocol *this,
+		efi_hii_handle_t package_list,
+		const u8 *primary_language,
+		u8 *secondary_languages,
+		efi_uintn_t *secondary_languages_size);
+};
+
+#define EFI_HII_DATABASE_PROTOCOL_GUID	     \
+	EFI_GUID(0xef9fc172, 0xa1b2, 0x4693, \
+		 0xb3, 0x27, 0x6d, 0x32, 0xfc, 0x41, 0x60, 0x42)
+
+struct efi_hii_database_protocol {
+	efi_status_t(EFIAPI *new_package_list)(
+		const struct efi_hii_database_protocol *this,
+		const struct efi_hii_package_list_header *package_list,
+		const efi_handle_t driver_handle,
+		efi_hii_handle_t *handle);
+	efi_status_t(EFIAPI *remove_package_list)(
+		const struct efi_hii_database_protocol *this,
+		efi_hii_handle_t handle);
+	efi_status_t(EFIAPI *update_package_list)(
+		const struct efi_hii_database_protocol *this,
+		efi_hii_handle_t handle,
+		const struct efi_hii_package_list_header *package_list);
+	efi_status_t(EFIAPI *list_package_lists)(
+		const struct efi_hii_database_protocol *this,
+		u8 package_type,
+		const efi_guid_t *package_guid,
+		efi_uintn_t *handle_buffer_length,
+		efi_hii_handle_t *handle);
+	efi_status_t(EFIAPI *export_package_lists)(
+		const struct efi_hii_database_protocol *this,
+		efi_hii_handle_t handle,
+		efi_uintn_t *buffer_size,
+		struct efi_hii_package_list_header *buffer);
+	efi_status_t(EFIAPI *register_package_notify)(
+		const struct efi_hii_database_protocol *this,
+		u8 package_type,
+		const efi_guid_t *package_guid,
+		const void *package_notify_fn,
+		efi_uintn_t notify_type,
+		efi_handle_t *notify_handle);
+	efi_status_t(EFIAPI *unregister_package_notify)(
+		const struct efi_hii_database_protocol *this,
+		efi_handle_t notification_handle
+		);
+	efi_status_t(EFIAPI *find_keyboard_layouts)(
+		const struct efi_hii_database_protocol *this,
+		u16 *key_guid_buffer_length,
+		efi_guid_t *key_guid_buffer);
+	efi_status_t(EFIAPI *get_keyboard_layout)(
+		const struct efi_hii_database_protocol *this,
+		efi_guid_t *key_guid,
+		u16 *keyboard_layout_length,
+		struct efi_hii_keyboard_layout *keyboard_layout);
+	efi_status_t(EFIAPI *set_keyboard_layout)(
+		const struct efi_hii_database_protocol *this,
+		efi_guid_t *key_guid);
+	efi_status_t(EFIAPI *get_package_list_handle)(
+		const struct efi_hii_database_protocol *this,
+		efi_hii_handle_t package_list_handle,
+		efi_handle_t *driver_handle);
+};
+
+#define EFI_HII_CONFIG_ROUTING_PROTOCOL_GUID \
+	EFI_GUID(0x587e72d7, 0xcc50, 0x4f79, \
+		 0x82, 0x09, 0xca, 0x29, 0x1f, 0xc1, 0xa1, 0x0f)
+
+struct efi_hii_config_routing_protocol {
+	efi_status_t(EFIAPI *extract_config)(
+		const struct efi_hii_config_routing_protocol *this,
+		const efi_string_t request,
+		efi_string_t *progress,
+		efi_string_t *results);
+	efi_status_t(EFIAPI *export_config)(
+		const struct efi_hii_config_routing_protocol *this,
+		efi_string_t *results);
+	efi_status_t(EFIAPI *route_config)(
+		const struct efi_hii_config_routing_protocol *this,
+		const efi_string_t configuration,
+		efi_string_t *progress);
+	efi_status_t(EFIAPI *block_to_config)(
+		const struct efi_hii_config_routing_protocol *this,
+		const efi_string_t config_request,
+		const uint8_t *block,
+		const efi_uintn_t block_size,
+		efi_string_t *config,
+		efi_string_t *progress);
+	efi_status_t(EFIAPI *config_to_block)(
+		const struct efi_hii_config_routing_protocol *this,
+		const efi_string_t config_resp,
+		const uint8_t *block,
+		const efi_uintn_t *block_size,
+		efi_string_t *progress);
+	efi_status_t(EFIAPI *get_alt_config)(
+		const struct efi_hii_config_routing_protocol *this,
+		const efi_string_t config_resp,
+		const efi_guid_t *guid,
+		const efi_string_t name,
+		const struct efi_device_path *device_path,
+		const efi_string_t alt_cfg_id,
+		efi_string_t *alt_cfg_resp);
+};
+
+#define EFI_HII_CONFIG_ACCESS_PROTOCOL_GUID \
+	EFI_GUID(0x330d4706, 0xf2a0, 0x4e4f, \
+		 0xa3, 0x69, 0xb6, 0x6f, 0xa8, 0xd5, 0x43, 0x85)
+
+struct efi_hii_config_access_protocol {
+	efi_status_t(EFIAPI *extract_config_access)(
+		const struct efi_hii_config_access_protocol *this,
+		const efi_string_t request,
+		efi_string_t *progress,
+		efi_string_t *results);
+	efi_status_t(EFIAPI *route_config_access)(
+		const struct efi_hii_config_access_protocol *this,
+		const efi_string_t configuration,
+		efi_string_t *progress);
+	efi_status_t(EFIAPI *form_callback)(
+		const struct efi_hii_config_access_protocol *this,
+		efi_browser_action_t action,
+		efi_question_id_t question_id,
+		u8 type,
+		union efi_ifr_type_value *value,
+		efi_browser_action_request_t *action_request);
+};
+
+#define EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID \
+	EFI_GUID(0x9042a9de, 0x23dc, 0x4a38, \
+		 0x96, 0xfb, 0x7a, 0xde, 0xd0, 0x80, 0x51, 0x6a)
+
+#define EFI_GOT_RGBA8		0
+#define EFI_GOT_BGRA8		1
+#define EFI_GOT_BITMASK		2
+
+struct efi_gop_mode_info {
+	u32 version;
+	u32 width;
+	u32 height;
+	u32 pixel_format;
+	u32 pixel_bitmask[4];
+	u32 pixels_per_scanline;
+};
+
+struct efi_gop_mode {
+	u32 max_mode;
+	u32 mode;
+	struct efi_gop_mode_info *info;
+	unsigned long info_size;
+	efi_physical_addr_t fb_base;
+	unsigned long fb_size;
+};
+
+struct efi_gop_pixel {
+	u8 blue;
+	u8 green;
+	u8 red;
+	u8 reserved;
+};
+
+#define EFI_BLT_VIDEO_FILL		0
+#define EFI_BLT_VIDEO_TO_BLT_BUFFER	1
+#define EFI_BLT_BUFFER_TO_VIDEO		2
+#define EFI_BLT_VIDEO_TO_VIDEO		3
+
+struct efi_gop {
+	efi_status_t (EFIAPI *query_mode)(struct efi_gop *this, u32 mode_number,
+					  efi_uintn_t *size_of_info,
+					  struct efi_gop_mode_info **info);
+	efi_status_t (EFIAPI *set_mode)(struct efi_gop *this, u32 mode_number);
+	efi_status_t (EFIAPI *blt)(struct efi_gop *this,
+				   struct efi_gop_pixel *buffer,
+				   u32 operation, efi_uintn_t sx,
+				   efi_uintn_t sy, efi_uintn_t dx,
+				   efi_uintn_t dy, efi_uintn_t width,
+				   efi_uintn_t height, efi_uintn_t delta);
+	struct efi_gop_mode *mode;
+};
+
+#define EFI_SIMPLE_NETWORK_PROTOCOL_GUID \
+	EFI_GUID(0xa19832b9, 0xac25, 0x11d3, \
+		 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
+struct efi_mac_address {
+	char mac_addr[32];
+};
+
+struct efi_ip_address {
+	u8 ip_addr[16];
+} __attribute__((aligned(4)));
+
+enum efi_simple_network_state {
+	EFI_NETWORK_STOPPED,
+	EFI_NETWORK_STARTED,
+	EFI_NETWORK_INITIALIZED,
+};
+
+struct efi_simple_network_mode {
+	enum efi_simple_network_state state;
+	u32 hwaddr_size;
+	u32 media_header_size;
+	u32 max_packet_size;
+	u32 nvram_size;
+	u32 nvram_access_size;
+	u32 receive_filter_mask;
+	u32 receive_filter_setting;
+	u32 max_mcast_filter_count;
+	u32 mcast_filter_count;
+	struct efi_mac_address mcast_filter[16];
+	struct efi_mac_address current_address;
+	struct efi_mac_address broadcast_address;
+	struct efi_mac_address permanent_address;
+	u8 if_type;
+	u8 mac_changeable;
+	u8 multitx_supported;
+	u8 media_present_supported;
+	u8 media_present;
+};
+
+/* receive_filters bit mask */
+#define EFI_SIMPLE_NETWORK_RECEIVE_UNICAST               0x01
+#define EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST             0x02
+#define EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST             0x04
+#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS           0x08
+#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST 0x10
+
+/* interrupt status bit mask */
+#define EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT	0x01
+#define EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT	0x02
+#define EFI_SIMPLE_NETWORK_COMMAND_INTERRUPT	0x04
+#define EFI_SIMPLE_NETWORK_SOFTWARE_INTERRUPT	0x08
+
+/* revision of the simple network protocol */
+#define EFI_SIMPLE_NETWORK_PROTOCOL_REVISION	0x00010000
+
+struct efi_simple_network {
+	u64 revision;
+	efi_status_t (EFIAPI *start)(struct efi_simple_network *this);
+	efi_status_t (EFIAPI *stop)(struct efi_simple_network *this);
+	efi_status_t (EFIAPI *initialize)(struct efi_simple_network *this,
+			ulong extra_rx, ulong extra_tx);
+	efi_status_t (EFIAPI *reset)(struct efi_simple_network *this,
+			int extended_verification);
+	efi_status_t (EFIAPI *shutdown)(struct efi_simple_network *this);
+	efi_status_t (EFIAPI *receive_filters)(struct efi_simple_network *this,
+			u32 enable, u32 disable, int reset_mcast_filter,
+			ulong mcast_filter_count,
+			struct efi_mac_address *mcast_filter);
+	efi_status_t (EFIAPI *station_address)(struct efi_simple_network *this,
+			int reset, struct efi_mac_address *new_mac);
+	efi_status_t (EFIAPI *statistics)(struct efi_simple_network *this,
+			int reset, ulong *stat_size, void *stat_table);
+	efi_status_t (EFIAPI *mcastiptomac)(struct efi_simple_network *this,
+			int ipv6, struct efi_ip_address *ip,
+			struct efi_mac_address *mac);
+	efi_status_t (EFIAPI *nvdata)(struct efi_simple_network *this,
+			int read_write, ulong offset, ulong buffer_size,
+			char *buffer);
+	efi_status_t (EFIAPI *get_status)(struct efi_simple_network *this,
+			u32 *int_status, void **txbuf);
+	efi_status_t (EFIAPI *transmit)(struct efi_simple_network *this,
+			size_t header_size, size_t buffer_size, void *buffer,
+			struct efi_mac_address *src_addr,
+			struct efi_mac_address *dest_addr, u16 *protocol);
+	efi_status_t (EFIAPI *receive)(struct efi_simple_network *this,
+			size_t *header_size, size_t *buffer_size, void *buffer,
+			struct efi_mac_address *src_addr,
+			struct efi_mac_address *dest_addr, u16 *protocol);
+	struct efi_event *wait_for_packet;
+	struct efi_simple_network_mode *mode;
+	/* private fields */
+	u32 int_status;
+};
+
+#define EFI_PXE_BASE_CODE_PROTOCOL_GUID \
+	EFI_GUID(0x03c4e603, 0xac28, 0x11d3, \
+		 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
+#define EFI_PXE_BASE_CODE_PROTOCOL_REVISION 0x00010000
+#define EFI_PXE_BASE_CODE_MAX_IPCNT 8
+
+struct efi_pxe_packet {
+	u8 packet[1472];
+};
+
+struct efi_pxe_mode {
+	u8 started;
+	u8 ipv6_available;
+	u8 ipv6_supported;
+	u8 using_ipv6;
+	u8 bis_supported;
+	u8 bis_detected;
+	u8 auto_arp;
+	u8 send_guid;
+	u8 dhcp_discover_valid;
+	u8 dhcp_ack_received;
+	u8 proxy_offer_received;
+	u8 pxe_discover_valid;
+	u8 pxe_reply_received;
+	u8 pxe_bis_reply_received;
+	u8 icmp_error_received;
+	u8 tftp_error_received;
+	u8 make_callbacks;
+	u8 ttl;
+	u8 tos;
+	u8 pad;
+	struct efi_ip_address station_ip;
+	struct efi_ip_address subnet_mask;
+	struct efi_pxe_packet dhcp_discover;
+	struct efi_pxe_packet dhcp_ack;
+	struct efi_pxe_packet proxy_offer;
+	struct efi_pxe_packet pxe_discover;
+	struct efi_pxe_packet pxe_reply;
+};
+
+struct efi_pxe_base_code_srvlist {
+	u16 type;
+	u8 accept_any_response;
+	u8 reserved;
+	struct efi_ip_address ip_addr;
+};
+
+struct efi_pxe_base_code_discover_info {
+	u8 use_m_cast;
+	u8 use_b_cast;
+	u8 use_u_cast;
+	u8 must_use_list;
+	struct efi_ip_address server_m_cast_ip;
+	u16 ip_cnt;
+	struct efi_pxe_base_code_srvlist srv_list[];
+};
+
+struct efi_pxe_base_code_mtftp_info {
+	struct efi_ip_address m_cast_ip;
+	u16 cport;
+	u16 sport;
+	u16 listen_timeout;
+	u16 transit_timeout;
+};
+
+struct efi_pxe_base_code_filter {
+	u8 filters;
+	u8 ip_cnt;
+	u16 reserved;
+	struct efi_ip_address ip_list[EFI_PXE_BASE_CODE_MAX_IPCNT];
+};
+
+struct efi_pxe_base_code_dhcpv4_packet {
+	u8 bootp_op_code;
+	u8 bootp_hw_type;
+	u8 bootp_addr_len;
+	u8 bootp_gate_hops;
+	u32 bootp_ident;
+	u16 bootp_seconds;
+	u16 bootp_flags;
+	u8 bootp_ci_addr[4];
+	u8 bootp_yi_addr[4];
+	u8 bootp_si_addr[4];
+	u8 bootp_gi_addr[4];
+	u8 bootp_hw_addr[16];
+	u8 bootp_srv_name[64];
+	u8 bootp_boot_file[128];
+	u32 dhcp_magick;
+	u8 dhcp_options[56];
+};
+
+struct efi_pxe_base_code_dhcpv6_packet {
+	u8 message_type;
+	u8 transaction_id[3];
+	u8 dhcp_options[1024];
+};
+
+typedef union {
+	u8 raw[1472];
+	struct efi_pxe_base_code_dhcpv4_packet dhcpv4;
+	struct efi_pxe_base_code_dhcpv6_packet dhcpv6;
+} EFI_PXE_BASE_CODE_PACKET;
+
+struct efi_pxe_base_code_protocol {
+	u64 revision;
+	efi_status_t (EFIAPI *start)(struct efi_pxe_base_code_protocol *this,
+				     u8 use_ipv6);
+	efi_status_t (EFIAPI *stop)(struct efi_pxe_base_code_protocol *this);
+	efi_status_t (EFIAPI *dhcp)(struct efi_pxe_base_code_protocol *this,
+				    u8 sort_offers);
+	efi_status_t (EFIAPI *discover)(
+				struct efi_pxe_base_code_protocol *this,
+				u16 type, u16 *layer, u8 bis,
+				struct efi_pxe_base_code_discover_info *info);
+	efi_status_t (EFIAPI *mtftp)(
+				struct efi_pxe_base_code_protocol *this,
+				u32 operation, void *buffer_ptr,
+				u8 overwrite, efi_uintn_t *buffer_size,
+				struct efi_ip_address server_ip, char *filename,
+				struct efi_pxe_base_code_mtftp_info *info,
+				u8 dont_use_buffer);
+	efi_status_t (EFIAPI *udp_write)(
+				struct efi_pxe_base_code_protocol *this,
+				u16 op_flags, struct efi_ip_address *dest_ip,
+				u16 *dest_port,
+				struct efi_ip_address *gateway_ip,
+				struct efi_ip_address *src_ip, u16 *src_port,
+				efi_uintn_t *header_size, void *header_ptr,
+				efi_uintn_t *buffer_size, void *buffer_ptr);
+	efi_status_t (EFIAPI *udp_read)(
+				struct efi_pxe_base_code_protocol *this,
+				u16 op_flags, struct efi_ip_address *dest_ip,
+				u16 *dest_port, struct efi_ip_address *src_ip,
+				u16 *src_port, efi_uintn_t *header_size,
+				void *header_ptr, efi_uintn_t *buffer_size,
+				void *buffer_ptr);
+	efi_status_t (EFIAPI *set_ip_filter)(
+				struct efi_pxe_base_code_protocol *this,
+				struct efi_pxe_base_code_filter *new_filter);
+	efi_status_t (EFIAPI *arp)(struct efi_pxe_base_code_protocol *this,
+				   struct efi_ip_address *ip_addr,
+				   struct efi_mac_address *mac_addr);
+	efi_status_t (EFIAPI *set_parameters)(
+				struct efi_pxe_base_code_protocol *this,
+				u8 *new_auto_arp, u8 *new_send_guid,
+				u8 *new_ttl, u8 *new_tos,
+				u8 *new_make_callback);
+	efi_status_t (EFIAPI *set_station_ip)(
+				struct efi_pxe_base_code_protocol *this,
+				struct efi_ip_address *new_station_ip,
+				struct efi_ip_address *new_subnet_mask);
+	efi_status_t (EFIAPI *set_packets)(
+				struct efi_pxe_base_code_protocol *this,
+				u8 *new_dhcp_discover_valid,
+				u8 *new_dhcp_ack_received,
+				u8 *new_proxy_offer_received,
+				u8 *new_pxe_discover_valid,
+				u8 *new_pxe_reply_received,
+				u8 *new_pxe_bis_reply_received,
+				EFI_PXE_BASE_CODE_PACKET *new_dchp_discover,
+				EFI_PXE_BASE_CODE_PACKET *new_dhcp_acc,
+				EFI_PXE_BASE_CODE_PACKET *new_proxy_offer,
+				EFI_PXE_BASE_CODE_PACKET *new_pxe_discover,
+				EFI_PXE_BASE_CODE_PACKET *new_pxe_reply,
+				EFI_PXE_BASE_CODE_PACKET *new_pxe_bis_reply);
+	struct efi_pxe_mode *mode;
+};
+
+#define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID \
+	EFI_GUID(0x964e5b22, 0x6459, 0x11d2, \
+		 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+#define EFI_FILE_PROTOCOL_REVISION	0x00010000
+#define EFI_FILE_PROTOCOL_REVISION2	0x00020000
+#define EFI_FILE_PROTOCOL_LATEST_REVISION EFI_FILE_PROTOCOL_REVISION2
+
+struct efi_file_io_token {
+	struct efi_event *event;
+	efi_status_t status;
+	efi_uintn_t buffer_size;
+	void *buffer;};
+
+struct efi_file_handle {
+	u64 rev;
+	efi_status_t (EFIAPI *open)(struct efi_file_handle *file,
+			struct efi_file_handle **new_handle,
+			u16 *file_name, u64 open_mode, u64 attributes);
+	efi_status_t (EFIAPI *close)(struct efi_file_handle *file);
+	efi_status_t (EFIAPI *delete)(struct efi_file_handle *file);
+	efi_status_t (EFIAPI *read)(struct efi_file_handle *file,
+			efi_uintn_t *buffer_size, void *buffer);
+	efi_status_t (EFIAPI *write)(struct efi_file_handle *file,
+			efi_uintn_t *buffer_size, void *buffer);
+	efi_status_t (EFIAPI *getpos)(struct efi_file_handle *file,
+				      u64 *pos);
+	efi_status_t (EFIAPI *setpos)(struct efi_file_handle *file,
+				      u64 pos);
+	efi_status_t (EFIAPI *getinfo)(struct efi_file_handle *file,
+			const efi_guid_t *info_type, efi_uintn_t *buffer_size,
+			void *buffer);
+	efi_status_t (EFIAPI *setinfo)(struct efi_file_handle *file,
+			const efi_guid_t *info_type, efi_uintn_t buffer_size,
+			void *buffer);
+	efi_status_t (EFIAPI *flush)(struct efi_file_handle *file);
+	efi_status_t (EFIAPI *open_ex)(struct efi_file_handle *file,
+			struct efi_file_handle **new_handle,
+			u16 *file_name, u64 open_mode, u64 attributes,
+			struct efi_file_io_token *token);
+	efi_status_t (EFIAPI *read_ex)(struct efi_file_handle *file,
+			struct efi_file_io_token *token);
+	efi_status_t (EFIAPI *write_ex)(struct efi_file_handle *file,
+			struct efi_file_io_token *token);
+	efi_status_t (EFIAPI *flush_ex)(struct efi_file_handle *file,
+			struct efi_file_io_token *token);
+};
+
+#define EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION 0x00010000
+
+struct efi_simple_file_system_protocol {
+	u64 rev;
+	efi_status_t (EFIAPI *open_volume)(struct efi_simple_file_system_protocol *this,
+			struct efi_file_handle **root);
+};
+
+#define EFI_FILE_INFO_GUID \
+	EFI_GUID(0x9576e92, 0x6d3f, 0x11d2, \
+		 0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
+#define EFI_FILE_SYSTEM_INFO_GUID \
+	EFI_GUID(0x09576e93, 0x6d3f, 0x11d2, \
+		 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b)
+
+#define EFI_FILE_SYSTEM_VOLUME_LABEL_ID \
+	EFI_GUID(0xdb47d7d3, 0xfe81, 0x11d3, \
+		 0x9a, 0x35, 0x00, 0x90, 0x27, 0x3f, 0xC1, 0x4d)
+
+#define EFI_FILE_MODE_READ	0x0000000000000001
+#define EFI_FILE_MODE_WRITE	0x0000000000000002
+#define EFI_FILE_MODE_CREATE	0x8000000000000000
+
+#define EFI_FILE_READ_ONLY	0x0000000000000001
+#define EFI_FILE_HIDDEN		0x0000000000000002
+#define EFI_FILE_SYSTEM		0x0000000000000004
+#define EFI_FILE_RESERVED	0x0000000000000008
+#define EFI_FILE_DIRECTORY	0x0000000000000010
+#define EFI_FILE_ARCHIVE	0x0000000000000020
+#define EFI_FILE_VALID_ATTR	0x0000000000000037
+
+struct efi_file_info {
+	u64 size;
+	u64 file_size;
+	u64 physical_size;
+	struct efi_time create_time;
+	struct efi_time last_access_time;
+	struct efi_time modification_time;
+	u64 attribute;
+	u16 file_name[0];
+};
+
+struct efi_file_system_info {
+	u64 size;
+	u8 read_only;
+	u64 volume_size;
+	u64 free_space;
+	u32 block_size;
+	u16 volume_label[0];
+};
+
+#define EFI_DRIVER_BINDING_PROTOCOL_GUID \
+	EFI_GUID(0x18a031ab, 0xb443, 0x4d1a,\
+		 0xa5, 0xc0, 0x0c, 0x09, 0x26, 0x1e, 0x9f, 0x71)
+struct efi_driver_binding_protocol {
+	efi_status_t (EFIAPI * supported)(
+			struct efi_driver_binding_protocol *this,
+			efi_handle_t controller_handle,
+			struct efi_device_path *remaining_device_path);
+	efi_status_t (EFIAPI * start)(
+			struct efi_driver_binding_protocol *this,
+			efi_handle_t controller_handle,
+			struct efi_device_path *remaining_device_path);
+	efi_status_t (EFIAPI * stop)(
+			struct efi_driver_binding_protocol *this,
+			efi_handle_t controller_handle,
+			efi_uintn_t number_of_children,
+			efi_handle_t *child_handle_buffer);
+	u32 version;
+	efi_handle_t image_handle;
+	efi_handle_t driver_binding_handle;
+};
+
+/* Deprecated version of the Unicode collation protocol */
+#define EFI_UNICODE_COLLATION_PROTOCOL_GUID \
+	EFI_GUID(0x1d85cd7f, 0xf43d, 0x11d2, \
+		 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+/* Current version of the Unicode collation protocol */
+#define EFI_UNICODE_COLLATION_PROTOCOL2_GUID \
+	EFI_GUID(0xa4c751fc, 0x23ae, 0x4c3e, \
+		 0x92, 0xe9, 0x49, 0x64, 0xcf, 0x63, 0xf3, 0x49)
+struct efi_unicode_collation_protocol {
+	efi_intn_t (EFIAPI *stri_coll)(
+		struct efi_unicode_collation_protocol *this, u16 *s1, u16 *s2);
+	bool (EFIAPI *metai_match)(struct efi_unicode_collation_protocol *this,
+				   const u16 *string, const u16 *patter);
+	void (EFIAPI *str_lwr)(struct efi_unicode_collation_protocol
+			       *this, u16 *string);
+	void (EFIAPI *str_upr)(struct efi_unicode_collation_protocol *this,
+			       u16 *string);
+	void (EFIAPI *fat_to_str)(struct efi_unicode_collation_protocol *this,
+				  efi_uintn_t fat_size, char *fat, u16 *string);
+	bool (EFIAPI *str_to_fat)(struct efi_unicode_collation_protocol *this,
+				  const u16 *string, efi_uintn_t fat_size,
+				  char *fat);
+	char *supported_languages;
+};
+
+/* Boot manager load options */
+#define LOAD_OPTION_ACTIVE		0x00000001
+#define LOAD_OPTION_FORCE_RECONNECT	0x00000002
+#define LOAD_OPTION_HIDDEN		0x00000008
+/* All values 0x00000200-0x00001F00 are reserved */
+#define LOAD_OPTION_CATEGORY		0x00001F00
+#define LOAD_OPTION_CATEGORY_BOOT	0x00000000
+#define LOAD_OPTION_CATEGORY_APP	0x00000100
+
+#endif
diff --git a/include/efi_driver.h b/include/efi_driver.h
new file mode 100644
index 0000000..840483a
--- /dev/null
+++ b/include/efi_driver.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  EFI application loader
+ *
+ *  Copyright (c) 2017 Heinrich Schuchardt
+ */
+
+#ifndef _EFI_DRIVER_H
+#define _EFI_DRIVER_H 1
+
+#include <common.h>
+#include <dm.h>
+#include <efi_loader.h>
+
+/*
+ * Operations supported by an EFI driver with respect to the EFI uclass
+ *
+ * @protocol		The GUID of the protocol which is consumed by the
+ *			driver. This GUID is used by the EFI uclass in the
+ *			supports() and start() methods of the
+ *			EFI_DRIVER_BINDING_PROTOCOL.
+ * @child_protocol	Protocol supported by the child handles generated by
+ *			the EFI driver.
+ * @bind		Function called by the EFI uclass to attach the
+ *			driver to EFI driver to a handle.
+ */
+struct efi_driver_ops {
+	const efi_guid_t *protocol;
+	const efi_guid_t *child_protocol;
+	int (*bind)(efi_handle_t handle, void *interface);
+};
+
+/*
+ * This structure adds internal fields to the driver binding protocol.
+ */
+struct efi_driver_binding_extended_protocol {
+	struct efi_driver_binding_protocol bp;
+	const struct efi_driver_ops *ops;
+};
+
+#endif /* _EFI_DRIVER_H */
diff --git a/include/efi_loader.h b/include/efi_loader.h
new file mode 100644
index 0000000..381da80
--- /dev/null
+++ b/include/efi_loader.h
@@ -0,0 +1,672 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  EFI application loader
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ */
+
+#ifndef _EFI_LOADER_H
+#define _EFI_LOADER_H 1
+
+#include <common.h>
+#include <part_efi.h>
+#include <efi_api.h>
+
+static inline int guidcmp(const void *g1, const void *g2)
+{
+	return memcmp(g1, g2, sizeof(efi_guid_t));
+}
+
+/* No need for efi loader support in SPL */
+#if CONFIG_IS_ENABLED(EFI_LOADER)
+
+#include <linux/list.h>
+
+/* Maximum number of configuration tables */
+#define EFI_MAX_CONFIGURATION_TABLES 16
+
+/* GUID used by the root node */
+#define U_BOOT_GUID \
+	EFI_GUID(0xe61d73b9, 0xa384, 0x4acc, \
+		 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3, 0x62, 0x8b)
+/* GUID used as host device on sandbox */
+#define U_BOOT_HOST_DEV_GUID \
+	EFI_GUID(0xbbe4e671, 0x5773, 0x4ea1, \
+		 0x9a, 0xab, 0x3a, 0x7d, 0xbf, 0x40, 0xc4, 0x82)
+
+/* Root node */
+extern efi_handle_t efi_root;
+
+int __efi_entry_check(void);
+int __efi_exit_check(void);
+const char *__efi_nesting(void);
+const char *__efi_nesting_inc(void);
+const char *__efi_nesting_dec(void);
+
+/*
+ * Enter the u-boot world from UEFI:
+ */
+#define EFI_ENTRY(format, ...) do { \
+	assert(__efi_entry_check()); \
+	debug("%sEFI: Entry %s(" format ")\n", __efi_nesting_inc(), \
+		__func__, ##__VA_ARGS__); \
+	} while(0)
+
+/*
+ * Exit the u-boot world back to UEFI:
+ */
+#define EFI_EXIT(ret) ({ \
+	typeof(ret) _r = ret; \
+	debug("%sEFI: Exit: %s: %u\n", __efi_nesting_dec(), \
+		__func__, (u32)((uintptr_t) _r & ~EFI_ERROR_MASK)); \
+	assert(__efi_exit_check()); \
+	_r; \
+	})
+
+/*
+ * Call non-void UEFI function from u-boot and retrieve return value:
+ */
+#define EFI_CALL(exp) ({ \
+	debug("%sEFI: Call: %s\n", __efi_nesting_inc(), #exp); \
+	assert(__efi_exit_check()); \
+	typeof(exp) _r = exp; \
+	assert(__efi_entry_check()); \
+	debug("%sEFI: %lu returned by %s\n", __efi_nesting_dec(), \
+	      (unsigned long)((uintptr_t)_r & ~EFI_ERROR_MASK), #exp); \
+	_r; \
+})
+
+/*
+ * Call void UEFI function from u-boot:
+ */
+#define EFI_CALL_VOID(exp) do { \
+	debug("%sEFI: Call: %s\n", __efi_nesting_inc(), #exp); \
+	assert(__efi_exit_check()); \
+	exp; \
+	assert(__efi_entry_check()); \
+	debug("%sEFI: Return From: %s\n", __efi_nesting_dec(), #exp); \
+	} while(0)
+
+/*
+ * Write an indented message with EFI prefix
+ */
+#define EFI_PRINT(format, ...) ({ \
+	debug("%sEFI: " format, __efi_nesting(), \
+		##__VA_ARGS__); \
+	})
+
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define EFI_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
+#else
+/* Just use the greatest cache flush alignment requirement I'm aware of */
+#define EFI_CACHELINE_SIZE 128
+#endif
+
+/* Key identifying current memory map */
+extern efi_uintn_t efi_memory_map_key;
+
+extern struct efi_runtime_services efi_runtime_services;
+extern struct efi_system_table systab;
+
+extern struct efi_simple_text_output_protocol efi_con_out;
+extern struct efi_simple_text_input_protocol efi_con_in;
+extern struct efi_console_control_protocol efi_console_control;
+extern const struct efi_device_path_to_text_protocol efi_device_path_to_text;
+/* implementation of the EFI_DEVICE_PATH_UTILITIES_PROTOCOL */
+extern const struct efi_device_path_utilities_protocol
+					efi_device_path_utilities;
+/* deprecated version of the EFI_UNICODE_COLLATION_PROTOCOL */
+extern const struct efi_unicode_collation_protocol
+					efi_unicode_collation_protocol;
+/* current version of the EFI_UNICODE_COLLATION_PROTOCOL */
+extern const struct efi_unicode_collation_protocol
+					efi_unicode_collation_protocol2;
+extern const struct efi_hii_config_routing_protocol efi_hii_config_routing;
+extern const struct efi_hii_config_access_protocol efi_hii_config_access;
+extern const struct efi_hii_database_protocol efi_hii_database;
+extern const struct efi_hii_string_protocol efi_hii_string;
+
+uint16_t *efi_dp_str(struct efi_device_path *dp);
+
+/* GUID of the U-Boot root node */
+extern const efi_guid_t efi_u_boot_guid;
+#ifdef CONFIG_SANDBOX
+/* GUID of U-Boot host device on sandbox */
+extern const efi_guid_t efi_guid_host_dev;
+#endif
+/* GUID of the EFI_BLOCK_IO_PROTOCOL */
+extern const efi_guid_t efi_block_io_guid;
+extern const efi_guid_t efi_global_variable_guid;
+extern const efi_guid_t efi_guid_console_control;
+extern const efi_guid_t efi_guid_device_path;
+/* GUID of the EFI_DRIVER_BINDING_PROTOCOL */
+extern const efi_guid_t efi_guid_driver_binding_protocol;
+/* event group ExitBootServices() invoked */
+extern const efi_guid_t efi_guid_event_group_exit_boot_services;
+/* event group SetVirtualAddressMap() invoked */
+extern const efi_guid_t efi_guid_event_group_virtual_address_change;
+/* event group memory map changed */
+extern const efi_guid_t efi_guid_event_group_memory_map_change;
+/* event group boot manager about to boot */
+extern const efi_guid_t efi_guid_event_group_ready_to_boot;
+/* event group ResetSystem() invoked (before ExitBootServices) */
+extern const efi_guid_t efi_guid_event_group_reset_system;
+/* GUID of the device tree table */
+extern const efi_guid_t efi_guid_fdt;
+extern const efi_guid_t efi_guid_loaded_image;
+extern const efi_guid_t efi_guid_loaded_image_device_path;
+extern const efi_guid_t efi_guid_device_path_to_text_protocol;
+extern const efi_guid_t efi_simple_file_system_protocol_guid;
+extern const efi_guid_t efi_file_info_guid;
+/* GUID for file system information */
+extern const efi_guid_t efi_file_system_info_guid;
+extern const efi_guid_t efi_guid_device_path_utilities_protocol;
+/* GUID of the deprecated Unicode collation protocol */
+extern const efi_guid_t efi_guid_unicode_collation_protocol;
+/* GUID of the Unicode collation protocol */
+extern const efi_guid_t efi_guid_unicode_collation_protocol2;
+extern const efi_guid_t efi_guid_hii_config_routing_protocol;
+extern const efi_guid_t efi_guid_hii_config_access_protocol;
+extern const efi_guid_t efi_guid_hii_database_protocol;
+extern const efi_guid_t efi_guid_hii_string_protocol;
+
+extern unsigned int __efi_runtime_start, __efi_runtime_stop;
+extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
+
+/**
+ * struct efi_open_protocol_info_item - open protocol info item
+ *
+ * When a protocol is opened a open protocol info entry is created.
+ * These are maintained in a list.
+ *
+ * @link:	link to the list of open protocol info entries of a protocol
+ * @info:	information about the opening of a protocol
+ */
+struct efi_open_protocol_info_item {
+	struct list_head link;
+	struct efi_open_protocol_info_entry info;
+};
+
+/**
+ * struct efi_handler - single protocol interface of a handle
+ *
+ * When the UEFI payload wants to open a protocol on an object to get its
+ * interface (usually a struct with callback functions), this struct maps the
+ * protocol GUID to the respective protocol interface
+ *
+ * @link:		link to the list of protocols of a handle
+ * @guid:		GUID of the protocol
+ * @protocol_interface:	protocol interface
+ * @open_infos		link to the list of open protocol info items
+ */
+struct efi_handler {
+	struct list_head link;
+	const efi_guid_t *guid;
+	void *protocol_interface;
+	struct list_head open_infos;
+};
+
+/**
+ * enum efi_object_type - type of EFI object
+ *
+ * In UnloadImage we must be able to identify if the handle relates to a
+ * started image.
+ */
+enum efi_object_type {
+	EFI_OBJECT_TYPE_UNDEFINED = 0,
+	EFI_OBJECT_TYPE_U_BOOT_FIRMWARE,
+	EFI_OBJECT_TYPE_LOADED_IMAGE,
+	EFI_OBJECT_TYPE_STARTED_IMAGE,
+};
+
+/**
+ * struct efi_object - dereferenced EFI handle
+ *
+ * @link:	pointers to put the handle into a linked list
+ * @protocols:	linked list with the protocol interfaces installed on this
+ *		handle
+ *
+ * UEFI offers a flexible and expandable object model. The objects in the UEFI
+ * API are devices, drivers, and loaded images. struct efi_object is our storage
+ * structure for these objects.
+ *
+ * When including this structure into a larger structure always put it first so
+ * that when deleting a handle the whole encompassing structure can be freed.
+ *
+ * A pointer to this structure is referred to as a handle. Typedef efi_handle_t
+ * has been created for such pointers.
+ */
+struct efi_object {
+	/* Every UEFI object is part of a global object list */
+	struct list_head link;
+	/* The list of protocols */
+	struct list_head protocols;
+	enum efi_object_type type;
+};
+
+/**
+ * struct efi_loaded_image_obj - handle of a loaded image
+ *
+ * @header:		EFI object header
+ * @exit_status:	exit status passed to Exit()
+ * @exit_data_size:	exit data size passed to Exit()
+ * @exit_data:		exit data passed to Exit()
+ * @exit_jmp:		long jump buffer for returning form started image
+ * @entry:		entry address of the relocated image
+ */
+struct efi_loaded_image_obj {
+	struct efi_object header;
+	efi_status_t exit_status;
+	efi_uintn_t *exit_data_size;
+	u16 **exit_data;
+	struct jmp_buf_data exit_jmp;
+	EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
+				     struct efi_system_table *st);
+	u16 image_type;
+};
+
+/**
+ * struct efi_event
+ *
+ * @link:		Link to list of all events
+ * @queue_link:		Link to the list of queued events
+ * @type:		Type of event, see efi_create_event
+ * @notify_tpl:		Task priority level of notifications
+ * @nofify_function:	Function to call when the event is triggered
+ * @notify_context:	Data to be passed to the notify function
+ * @group:		Event group
+ * @trigger_time:	Period of the timer
+ * @trigger_next:	Next time to trigger the timer
+ * @trigger_type:	Type of timer, see efi_set_timer
+ * @is_signaled:	The event occurred. The event is in the signaled state.
+ */
+struct efi_event {
+	struct list_head link;
+	struct list_head queue_link;
+	uint32_t type;
+	efi_uintn_t notify_tpl;
+	void (EFIAPI *notify_function)(struct efi_event *event, void *context);
+	void *notify_context;
+	const efi_guid_t *group;
+	u64 trigger_next;
+	u64 trigger_time;
+	enum efi_timer_delay trigger_type;
+	bool is_signaled;
+};
+
+/* This list contains all UEFI objects we know of */
+extern struct list_head efi_obj_list;
+/* List of all events */
+extern struct list_head efi_events;
+
+/**
+ * struct efi_protocol_notification - handle for notified protocol
+ *
+ * When a protocol interface is installed for which an event was registered with
+ * the RegisterProtocolNotify() service this structure is used to hold the
+ * handle on which the protocol interface was installed.
+ *
+ * @link:	link to list of all handles notified for this event
+ * @handle:	handle on which the notified protocol interface was installed
+ */
+struct efi_protocol_notification {
+	struct list_head link;
+	efi_handle_t handle;
+};
+
+/**
+ * efi_register_notify_event - event registered by RegisterProtocolNotify()
+ *
+ * The address of this structure serves as registration value.
+ *
+ * @link:	link to list of all registered events
+ * @event:	registered event. The same event may registered for multiple
+ *		GUIDs.
+ * @protocol:	protocol for which the event is registered
+ * @handles:	linked list of all handles on which the notified protocol was
+ *		installed
+ */
+struct efi_register_notify_event {
+	struct list_head link;
+	struct efi_event *event;
+	efi_guid_t protocol;
+	struct list_head handles;
+};
+
+/* List of all events registered by RegisterProtocolNotify() */
+extern struct list_head efi_register_notify_events;
+
+/* Initialize efi execution environment */
+efi_status_t efi_init_obj_list(void);
+/* Initialize variable services */
+efi_status_t efi_init_variables(void);
+/* Notify ExitBootServices() is called */
+void efi_variables_boot_exit_notify(void);
+/* Called by bootefi to initialize root node */
+efi_status_t efi_root_node_register(void);
+/* Called by bootefi to initialize runtime */
+efi_status_t efi_initialize_system_table(void);
+/* efi_runtime_detach() - detach unimplemented runtime functions */
+void efi_runtime_detach(void);
+/* Called by bootefi to make console interface available */
+efi_status_t efi_console_register(void);
+/* Called by bootefi to make all disk storage accessible as EFI objects */
+efi_status_t efi_disk_register(void);
+/* Create handles and protocols for the partitions of a block device */
+int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
+			       const char *if_typename, int diskid,
+			       const char *pdevname);
+/* Called by bootefi to make GOP (graphical) interface available */
+efi_status_t efi_gop_register(void);
+/* Called by bootefi to make the network interface available */
+efi_status_t efi_net_register(void);
+/* Called by bootefi to make the watchdog available */
+efi_status_t efi_watchdog_register(void);
+/* Called by bootefi to make SMBIOS tables available */
+/**
+ * efi_acpi_register() - write out ACPI tables
+ *
+ * Called by bootefi to make ACPI tables available
+ *
+ * @return 0 if OK, -ENOMEM if no memory is available for the tables
+ */
+efi_status_t efi_acpi_register(void);
+/**
+ * efi_smbios_register() - write out SMBIOS tables
+ *
+ * Called by bootefi to make SMBIOS tables available
+ *
+ * @return 0 if OK, -ENOMEM if no memory is available for the tables
+ */
+efi_status_t efi_smbios_register(void);
+
+struct efi_simple_file_system_protocol *
+efi_fs_from_path(struct efi_device_path *fp);
+
+/* Called by networking code to memorize the dhcp ack package */
+void efi_net_set_dhcp_ack(void *pkt, int len);
+/* Called by efi_set_watchdog_timer to reset the timer */
+efi_status_t efi_set_watchdog(unsigned long timeout);
+
+/* Called from places to check whether a timer expired */
+void efi_timer_check(void);
+/* PE loader implementation */
+efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, void *efi,
+			 struct efi_loaded_image *loaded_image_info);
+/* Called once to store the pristine gd pointer */
+void efi_save_gd(void);
+/* Special case handler for error/abort that just tries to dtrt to get
+ * back to u-boot world */
+void efi_restore_gd(void);
+/* Call this to relocate the runtime section to an address space */
+void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map);
+/* Call this to set the current device name */
+void efi_set_bootdev(const char *dev, const char *devnr, const char *path);
+/* Add a new object to the object list. */
+void efi_add_handle(efi_handle_t obj);
+/* Create handle */
+efi_status_t efi_create_handle(efi_handle_t *handle);
+/* Delete handle */
+void efi_delete_handle(efi_handle_t obj);
+/* Call this to validate a handle and find the EFI object for it */
+struct efi_object *efi_search_obj(const efi_handle_t handle);
+/* Load image */
+efi_status_t EFIAPI efi_load_image(bool boot_policy,
+				   efi_handle_t parent_image,
+				   struct efi_device_path *file_path,
+				   void *source_buffer,
+				   efi_uintn_t source_size,
+				   efi_handle_t *image_handle);
+/* Start image */
+efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle,
+				    efi_uintn_t *exit_data_size,
+				    u16 **exit_data);
+/* Unload image */
+efi_status_t EFIAPI efi_unload_image(efi_handle_t image_handle);
+/* Find a protocol on a handle */
+efi_status_t efi_search_protocol(const efi_handle_t handle,
+				 const efi_guid_t *protocol_guid,
+				 struct efi_handler **handler);
+/* Install new protocol on a handle */
+efi_status_t efi_add_protocol(const efi_handle_t handle,
+			      const efi_guid_t *protocol,
+			      void *protocol_interface);
+/* Delete protocol from a handle */
+efi_status_t efi_remove_protocol(const efi_handle_t handle,
+				 const efi_guid_t *protocol,
+				 void *protocol_interface);
+/* Delete all protocols from a handle */
+efi_status_t efi_remove_all_protocols(const efi_handle_t handle);
+/* Install multiple protocol interfaces */
+efi_status_t EFIAPI efi_install_multiple_protocol_interfaces
+				(efi_handle_t *handle, ...);
+/* Call this to create an event */
+efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl,
+			      void (EFIAPI *notify_function) (
+					struct efi_event *event,
+					void *context),
+			      void *notify_context, efi_guid_t *group,
+			      struct efi_event **event);
+/* Call this to set a timer */
+efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type,
+			   uint64_t trigger_time);
+/* Call this to signal an event */
+void efi_signal_event(struct efi_event *event);
+
+/* open file system: */
+struct efi_simple_file_system_protocol *efi_simple_file_system(
+		struct blk_desc *desc, int part, struct efi_device_path *dp);
+
+/* open file from device-path: */
+struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp);
+
+/**
+ * efi_size_in_pages() - convert size in bytes to size in pages
+ *
+ * This macro returns the number of EFI memory pages required to hold 'size'
+ * bytes.
+ *
+ * @size:	size in bytes
+ * Return:	size in pages
+ */
+#define efi_size_in_pages(size) ((size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT)
+/* Generic EFI memory allocator, call this to get memory */
+void *efi_alloc(uint64_t len, int memory_type);
+/* More specific EFI memory allocator, called by EFI payloads */
+efi_status_t efi_allocate_pages(int type, int memory_type, efi_uintn_t pages,
+				uint64_t *memory);
+/* EFI memory free function. */
+efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages);
+/* EFI memory allocator for small allocations */
+efi_status_t efi_allocate_pool(int pool_type, efi_uintn_t size,
+			       void **buffer);
+/* EFI pool memory free function. */
+efi_status_t efi_free_pool(void *buffer);
+/* Returns the EFI memory map */
+efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size,
+				struct efi_mem_desc *memory_map,
+				efi_uintn_t *map_key,
+				efi_uintn_t *descriptor_size,
+				uint32_t *descriptor_version);
+/* Adds a range into the EFI memory map */
+efi_status_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
+				bool overlap_only_ram);
+/* Adds a conventional range into the EFI memory map */
+efi_status_t efi_add_conventional_memory_map(u64 ram_start, u64 ram_end,
+					     u64 ram_top);
+
+/* Called by board init to initialize the EFI drivers */
+efi_status_t efi_driver_init(void);
+/* Called by board init to initialize the EFI memory map */
+int efi_memory_init(void);
+/* Adds new or overrides configuration table entry to the system table */
+efi_status_t efi_install_configuration_table(const efi_guid_t *guid, void *table);
+/* Sets up a loaded image */
+efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path,
+				    struct efi_device_path *file_path,
+				    struct efi_loaded_image_obj **handle_ptr,
+				    struct efi_loaded_image **info_ptr);
+/* Print information about all loaded images */
+void efi_print_image_infos(void *pc);
+
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+extern void *efi_bounce_buffer;
+#define EFI_LOADER_BOUNCE_BUFFER_SIZE (64 * 1024 * 1024)
+#endif
+
+
+struct efi_device_path *efi_dp_next(const struct efi_device_path *dp);
+int efi_dp_match(const struct efi_device_path *a,
+		 const struct efi_device_path *b);
+struct efi_object *efi_dp_find_obj(struct efi_device_path *dp,
+				   struct efi_device_path **rem);
+/* get size of the first device path instance excluding end node */
+efi_uintn_t efi_dp_instance_size(const struct efi_device_path *dp);
+/* size of multi-instance device path excluding end node */
+efi_uintn_t efi_dp_size(const struct efi_device_path *dp);
+struct efi_device_path *efi_dp_dup(const struct efi_device_path *dp);
+struct efi_device_path *efi_dp_append(const struct efi_device_path *dp1,
+				      const struct efi_device_path *dp2);
+struct efi_device_path *efi_dp_append_node(const struct efi_device_path *dp,
+					   const struct efi_device_path *node);
+/* Create a device path node of given type, sub-type, length */
+struct efi_device_path *efi_dp_create_device_node(const u8 type,
+						  const u8 sub_type,
+						  const u16 length);
+/* Append device path instance */
+struct efi_device_path *efi_dp_append_instance(
+		const struct efi_device_path *dp,
+		const struct efi_device_path *dpi);
+/* Get next device path instance */
+struct efi_device_path *efi_dp_get_next_instance(struct efi_device_path **dp,
+						 efi_uintn_t *size);
+/* Check if a device path contains muliple instances */
+bool efi_dp_is_multi_instance(const struct efi_device_path *dp);
+
+struct efi_device_path *efi_dp_from_dev(struct udevice *dev);
+struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part);
+/* Create a device node for a block device partition. */
+struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part);
+struct efi_device_path *efi_dp_from_file(struct blk_desc *desc, int part,
+					 const char *path);
+struct efi_device_path *efi_dp_from_eth(void);
+struct efi_device_path *efi_dp_from_mem(uint32_t mem_type,
+					uint64_t start_address,
+					uint64_t end_address);
+/* Determine the last device path node that is not the end node. */
+const struct efi_device_path *efi_dp_last_node(
+			const struct efi_device_path *dp);
+efi_status_t efi_dp_split_file_path(struct efi_device_path *full_path,
+				    struct efi_device_path **device_path,
+				    struct efi_device_path **file_path);
+efi_status_t efi_dp_from_name(const char *dev, const char *devnr,
+			      const char *path,
+			      struct efi_device_path **device,
+			      struct efi_device_path **file);
+
+#define EFI_DP_TYPE(_dp, _type, _subtype) \
+	(((_dp)->type == DEVICE_PATH_TYPE_##_type) && \
+	 ((_dp)->sub_type == DEVICE_PATH_SUB_TYPE_##_subtype))
+
+/*
+ * Use these to indicate that your code / data should go into the EFI runtime
+ * section and thus still be available when the OS is running
+ */
+#define __efi_runtime_data __attribute__ ((section (".data.efi_runtime")))
+#define __efi_runtime __attribute__ ((section (".text.efi_runtime")))
+
+/* Indicate supported runtime services */
+efi_status_t efi_init_runtime_supported(void);
+
+/* Update CRC32 in table header */
+void __efi_runtime efi_update_table_header_crc32(struct efi_table_hdr *table);
+
+/* Call this with mmio_ptr as the _pointer_ to a pointer to an MMIO region
+ * to make it available at runtime */
+efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len);
+
+/* Boards may provide the functions below to implement RTS functionality */
+
+void __efi_runtime EFIAPI efi_reset_system(
+			enum efi_reset_type reset_type,
+			efi_status_t reset_status,
+			unsigned long data_size, void *reset_data);
+
+/* Architecture specific initialization of the EFI subsystem */
+efi_status_t efi_reset_system_init(void);
+
+efi_status_t __efi_runtime EFIAPI efi_get_time(
+			struct efi_time *time,
+			struct efi_time_cap *capabilities);
+
+efi_status_t __efi_runtime EFIAPI efi_set_time(struct efi_time *time);
+
+#ifdef CONFIG_CMD_BOOTEFI_SELFTEST
+/*
+ * Entry point for the tests of the EFI API.
+ * It is called by 'bootefi selftest'
+ */
+efi_status_t EFIAPI efi_selftest(efi_handle_t image_handle,
+				 struct efi_system_table *systab);
+#endif
+
+efi_status_t EFIAPI efi_get_variable(u16 *variable_name,
+				     const efi_guid_t *vendor, u32 *attributes,
+				     efi_uintn_t *data_size, void *data);
+efi_status_t EFIAPI efi_get_next_variable_name(efi_uintn_t *variable_name_size,
+					       u16 *variable_name,
+					       const efi_guid_t *vendor);
+efi_status_t EFIAPI efi_set_variable(u16 *variable_name,
+				     const efi_guid_t *vendor, u32 attributes,
+				     efi_uintn_t data_size, const void *data);
+
+efi_status_t EFIAPI efi_query_variable_info(
+			u32 attributes, u64 *maximum_variable_storage_size,
+			u64 *remaining_variable_storage_size,
+			u64 *maximum_variable_size);
+
+/*
+ * See section 3.1.3 in the v2.7 UEFI spec for more details on
+ * the layout of EFI_LOAD_OPTION.  In short it is:
+ *
+ *    typedef struct _EFI_LOAD_OPTION {
+ *        UINT32 Attributes;
+ *        UINT16 FilePathListLength;
+ *        // CHAR16 Description[];   <-- variable length, NULL terminated
+ *        // EFI_DEVICE_PATH_PROTOCOL FilePathList[];
+ *						 <-- FilePathListLength bytes
+ *        // UINT8 OptionalData[];
+ *    } EFI_LOAD_OPTION;
+ */
+struct efi_load_option {
+	u32 attributes;
+	u16 file_path_length;
+	u16 *label;
+	struct efi_device_path *file_path;
+	const u8 *optional_data;
+};
+
+void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data);
+unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data);
+efi_status_t efi_bootmgr_load(efi_handle_t *handle);
+
+#else /* CONFIG_IS_ENABLED(EFI_LOADER) */
+
+/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
+#define __efi_runtime_data
+#define __efi_runtime
+static inline efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len)
+{
+	return EFI_SUCCESS;
+}
+
+/* No loader configured, stub out EFI_ENTRY */
+static inline void efi_restore_gd(void) { }
+static inline void efi_set_bootdev(const char *dev, const char *devnr,
+				   const char *path) { }
+static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
+static inline void efi_print_image_infos(void *pc) { }
+
+#endif /* CONFIG_IS_ENABLED(EFI_LOADER) */
+
+#endif /* _EFI_LOADER_H */
diff --git a/include/efi_selftest.h b/include/efi_selftest.h
new file mode 100644
index 0000000..eaee188
--- /dev/null
+++ b/include/efi_selftest.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  EFI application loader
+ *
+ *  Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+#ifndef _EFI_SELFTEST_H
+#define _EFI_SELFTEST_H
+
+#include <common.h>
+#include <efi.h>
+#include <efi_api.h>
+#include <efi_loader.h>
+#include <linker_lists.h>
+
+#define EFI_ST_SUCCESS 0
+#define EFI_ST_FAILURE 1
+#define EFI_ST_SUCCESS_STR L"SUCCESS"
+/*
+ * Prints a message.
+ */
+#define efi_st_printf(...) \
+	(efi_st_printc(-1, __VA_ARGS__))
+
+/*
+ * Prints an error message.
+ *
+ * @...	format string followed by fields to print
+ */
+#define efi_st_error(...) \
+	(efi_st_printc(EFI_LIGHTRED, "%s(%u):\nERROR: ", __FILE__, __LINE__), \
+	efi_st_printc(EFI_LIGHTRED, __VA_ARGS__))
+
+/*
+ * Prints a TODO message.
+ *
+ * @...	format string followed by fields to print
+ */
+#define efi_st_todo(...) \
+	(efi_st_printc(EFI_YELLOW, "%s(%u):\nTODO: ", __FILE__, __LINE__), \
+	efi_st_printc(EFI_YELLOW, __VA_ARGS__)) \
+
+/*
+ * A test may be setup and executed at boottime,
+ * it may be setup at boottime and executed at runtime,
+ * or it may be setup and executed at runtime.
+ */
+enum efi_test_phase {
+	EFI_EXECUTE_BEFORE_BOOTTIME_EXIT = 1,
+	EFI_SETUP_BEFORE_BOOTTIME_EXIT,
+	EFI_SETUP_AFTER_BOOTTIME_EXIT,
+};
+
+extern struct efi_simple_text_output_protocol *con_out;
+extern struct efi_simple_text_input_protocol *con_in;
+
+/*
+ * Exit the boot services.
+ *
+ * The size of the memory map is determined.
+ * Pool memory is allocated to copy the memory map.
+ * The memory amp is copied and the map key is obtained.
+ * The map key is used to exit the boot services.
+ */
+void efi_st_exit_boot_services(void);
+
+/*
+ * Print a colored message
+ *
+ * @color	color, see constants in efi_api.h, use -1 for no color
+ * @fmt		printf format
+ * @...		arguments to be printed
+ *		on return position of terminating zero word
+ */
+void efi_st_printc(int color, const char *fmt, ...)
+		 __attribute__ ((format (__printf__, 2, 3)));
+
+/**
+ * efi_st_translate_char() - translate a unicode character to a string
+ *
+ * @code:	unicode character
+ * Return:	string
+ */
+u16 *efi_st_translate_char(u16 code);
+
+/**
+ * efi_st_translate_code() - translate a scan code to a human readable string
+ *
+ * @code:	unicode character
+ * Return:	string
+ */
+u16 *efi_st_translate_code(u16 code);
+
+/*
+ * Compare an u16 string to a char string.
+ *
+ * @buf1:	u16 string
+ * @buf2:	char string
+ * @return:	0 if both buffers contain the same bytes
+ */
+int efi_st_strcmp_16_8(const u16 *buf1, const char *buf2);
+
+/*
+ * Reads an Unicode character from the input device.
+ *
+ * @return: Unicode character
+ */
+u16 efi_st_get_key(void);
+
+/**
+ * struct efi_unit_test - EFI unit test
+ *
+ * An efi_unit_test provides a interface to an EFI unit test.
+ *
+ * @name:	name of unit test
+ * @phase:	specifies when setup and execute are executed
+ * @setup:	set up the unit test
+ * @teardown:	tear down the unit test
+ * @execute:	execute the unit test
+ * @on_request:	test is only executed on request
+ */
+struct efi_unit_test {
+	const char *name;
+	const enum efi_test_phase phase;
+	int (*setup)(const efi_handle_t handle,
+		     const struct efi_system_table *systable);
+	int (*execute)(void);
+	int (*teardown)(void);
+	bool on_request;
+};
+
+/* Declare a new EFI unit test */
+#define EFI_UNIT_TEST(__name)						\
+	ll_entry_declare(struct efi_unit_test, __name, efi_unit_test)
+
+#endif /* _EFI_SELFTEST_H */
diff --git a/include/elf.h b/include/elf.h
new file mode 100644
index 0000000..81f4019
--- /dev/null
+++ b/include/elf.h
@@ -0,0 +1,697 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 1995, 1996, 2001, 2002
+ * Erik Theisen.  All rights reserved.
+ */
+
+/* This is the ELF ABI header file formerly known as "elf_abi.h" */
+
+#ifndef _ELF_H
+#define _ELF_H
+
+#ifndef __ASSEMBLER__
+#include "compiler.h"
+
+/* This version doesn't work for 64-bit ABIs - Erik */
+
+/* These typedefs need to be handled better */
+typedef uint32_t	Elf32_Addr;	/* Unsigned program address */
+typedef uint32_t	Elf32_Off;	/* Unsigned file offset */
+typedef int32_t		Elf32_Sword;	/* Signed large integer */
+typedef uint32_t	Elf32_Word;	/* Unsigned large integer */
+typedef uint16_t	Elf32_Half;	/* Unsigned medium integer */
+
+/* 64-bit ELF base types */
+typedef uint64_t	Elf64_Addr;
+typedef uint16_t	Elf64_Half;
+typedef int16_t		Elf64_SHalf;
+typedef uint64_t	Elf64_Off;
+typedef int32_t		Elf64_Sword;
+typedef uint32_t	Elf64_Word;
+typedef uint64_t	Elf64_Xword;
+typedef int64_t		Elf64_Sxword;
+
+/* e_ident[] identification indexes */
+#define EI_MAG0		0		/* file ID */
+#define EI_MAG1		1		/* file ID */
+#define EI_MAG2		2		/* file ID */
+#define EI_MAG3		3		/* file ID */
+#define EI_CLASS	4		/* file class */
+#define EI_DATA		5		/* data encoding */
+#define EI_VERSION	6		/* ELF header version */
+#define EI_OSABI	7		/* OS/ABI specific ELF extensions */
+#define EI_ABIVERSION	8		/* ABI target version */
+#define EI_PAD		9		/* start of pad bytes */
+#define EI_NIDENT	16		/* Size of e_ident[] */
+
+/* e_ident[] magic number */
+#define	ELFMAG0		0x7f		/* e_ident[EI_MAG0] */
+#define	ELFMAG1		'E'		/* e_ident[EI_MAG1] */
+#define	ELFMAG2		'L'		/* e_ident[EI_MAG2] */
+#define	ELFMAG3		'F'		/* e_ident[EI_MAG3] */
+#define	ELFMAG		"\177ELF"	/* magic */
+#define	SELFMAG		4		/* size of magic */
+
+/* e_ident[] file class */
+#define	ELFCLASSNONE	0		/* invalid */
+#define	ELFCLASS32	1		/* 32-bit objs */
+#define	ELFCLASS64	2		/* 64-bit objs */
+#define	ELFCLASSNUM	3		/* number of classes */
+
+/* e_ident[] data encoding */
+#define ELFDATANONE	0		/* invalid */
+#define ELFDATA2LSB	1		/* Little-Endian */
+#define ELFDATA2MSB	2		/* Big-Endian */
+#define ELFDATANUM	3		/* number of data encode defines */
+
+/* e_ident[] OS/ABI specific ELF extensions */
+#define ELFOSABI_NONE		0	/* No extension specified */
+#define ELFOSABI_HPUX		1	/* Hewlett-Packard HP-UX */
+#define ELFOSABI_NETBSD		2	/* NetBSD */
+#define ELFOSABI_LINUX		3	/* Linux */
+#define ELFOSABI_SOLARIS	6	/* Sun Solaris */
+#define ELFOSABI_AIX		7	/* AIX */
+#define ELFOSABI_IRIX		8	/* IRIX */
+#define ELFOSABI_FREEBSD	9	/* FreeBSD */
+#define ELFOSABI_TRU64		10	/* Compaq TRU64 UNIX */
+#define ELFOSABI_MODESTO	11	/* Novell Modesto */
+#define ELFOSABI_OPENBSD	12	/* OpenBSD */
+/* 64-255 Architecture-specific value range */
+
+/* e_ident[] ABI Version */
+#define ELFABIVERSION		0
+
+/* e_ident */
+#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \
+		      (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \
+		      (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \
+		      (ehdr).e_ident[EI_MAG3] == ELFMAG3)
+
+/* ELF Header */
+typedef struct {
+	unsigned char	e_ident[EI_NIDENT]; /* ELF Identification */
+	Elf32_Half	e_type;		/* object file type */
+	Elf32_Half	e_machine;	/* machine */
+	Elf32_Word	e_version;	/* object file version */
+	Elf32_Addr	e_entry;	/* virtual entry point */
+	Elf32_Off	e_phoff;	/* program header table offset */
+	Elf32_Off	e_shoff;	/* section header table offset */
+	Elf32_Word	e_flags;	/* processor-specific flags */
+	Elf32_Half	e_ehsize;	/* ELF header size */
+	Elf32_Half	e_phentsize;	/* program header entry size */
+	Elf32_Half	e_phnum;	/* number of program header entries */
+	Elf32_Half	e_shentsize;	/* section header entry size */
+	Elf32_Half	e_shnum;	/* number of section header entries */
+	Elf32_Half	e_shstrndx;	/* section header table's "section
+					   header string table" entry offset */
+} Elf32_Ehdr;
+
+typedef struct {
+	unsigned char	e_ident[EI_NIDENT]; /* ELF Identification */
+	Elf64_Half	e_type;		/* object file type */
+	Elf64_Half	e_machine;	/* machine */
+	Elf64_Word	e_version;	/* object file version */
+	Elf64_Addr	e_entry;	/* virtual entry point */
+	Elf64_Off	e_phoff;	/* program header table offset */
+	Elf64_Off	e_shoff;	/* section header table offset */
+	Elf64_Word	e_flags;	/* processor-specific flags */
+	Elf64_Half	e_ehsize;	/* ELF header size */
+	Elf64_Half	e_phentsize;	/* program header entry size */
+	Elf64_Half	e_phnum;	/* number of program header entries */
+	Elf64_Half	e_shentsize;	/* section header entry size */
+	Elf64_Half	e_shnum;	/* number of section header entries */
+	Elf64_Half	e_shstrndx;	/* section header table's "section
+					   header string table" entry offset */
+} Elf64_Ehdr;
+
+/* e_type */
+#define ET_NONE		0		/* No file type */
+#define ET_REL		1		/* relocatable file */
+#define ET_EXEC		2		/* executable file */
+#define ET_DYN		3		/* shared object file */
+#define ET_CORE		4		/* core file */
+#define ET_NUM		5		/* number of types */
+#define ET_LOOS		0xfe00		/* reserved range for operating */
+#define ET_HIOS		0xfeff		/* system specific e_type */
+#define ET_LOPROC	0xff00		/* reserved range for processor */
+#define ET_HIPROC	0xffff		/* specific e_type */
+
+/* e_machine */
+#define EM_NONE		0		/* No Machine */
+#define EM_M32		1		/* AT&T WE 32100 */
+#define EM_SPARC	2		/* SPARC */
+#define EM_386		3		/* Intel 80386 */
+#define EM_68K		4		/* Motorola 68000 */
+#define EM_88K		5		/* Motorola 88000 */
+#if 0
+#define EM_486		6		/* RESERVED - was Intel 80486 */
+#endif
+#define EM_860		7		/* Intel 80860 */
+#define EM_MIPS		8		/* MIPS R3000 Big-Endian only */
+#define EM_S370		9		/* IBM System/370 Processor */
+#define EM_MIPS_RS4_BE	10		/* MIPS R4000 Big-Endian */
+#if 0
+#define EM_SPARC64	11		/* RESERVED - was SPARC v9
+					     64-bit unoffical */
+#endif
+/* RESERVED 11-14 for future use */
+#define EM_PARISC	15		/* HPPA */
+/* RESERVED 16 for future use */
+#define EM_VPP500	17		/* Fujitsu VPP500 */
+#define EM_SPARC32PLUS	18		/* Enhanced instruction set SPARC */
+#define EM_960		19		/* Intel 80960 */
+#define EM_PPC		20		/* PowerPC */
+#define EM_PPC64	21		/* 64-bit PowerPC */
+#define EM_S390		22		/* IBM System/390 Processor */
+/* RESERVED 23-35 for future use */
+#define EM_V800		36		/* NEC V800 */
+#define EM_FR20		37		/* Fujitsu FR20 */
+#define EM_RH32		38		/* TRW RH-32 */
+#define EM_RCE		39		/* Motorola RCE */
+#define EM_ARM		40		/* Advanced Risc Machines ARM */
+#define EM_ALPHA	41		/* Digital Alpha */
+#define EM_SH		42		/* Hitachi SH */
+#define EM_SPARCV9	43		/* SPARC Version 9 */
+#define EM_TRICORE	44		/* Siemens TriCore embedded processor */
+#define EM_ARC		45		/* Argonaut RISC Core */
+#define EM_H8_300	46		/* Hitachi H8/300 */
+#define EM_H8_300H	47		/* Hitachi H8/300H */
+#define EM_H8S		48		/* Hitachi H8S */
+#define EM_H8_500	49		/* Hitachi H8/500 */
+#define EM_IA_64	50		/* Intel Merced */
+#define EM_MIPS_X	51		/* Stanford MIPS-X */
+#define EM_COLDFIRE	52		/* Motorola Coldfire */
+#define EM_68HC12	53		/* Motorola M68HC12 */
+#define EM_MMA		54		/* Fujitsu MMA Multimedia Accelerator*/
+#define EM_PCP		55		/* Siemens PCP */
+#define EM_NCPU		56		/* Sony nCPU embeeded RISC */
+#define EM_NDR1		57		/* Denso NDR1 microprocessor */
+#define EM_STARCORE	58		/* Motorola Start*Core processor */
+#define EM_ME16		59		/* Toyota ME16 processor */
+#define EM_ST100	60		/* STMicroelectronic ST100 processor */
+#define EM_TINYJ	61		/* Advanced Logic Corp. Tinyj emb.fam*/
+#define EM_X86_64	62		/* AMD x86-64 */
+#define EM_PDSP		63		/* Sony DSP Processor */
+/* RESERVED 64,65 for future use */
+#define EM_FX66		66		/* Siemens FX66 microcontroller */
+#define EM_ST9PLUS	67		/* STMicroelectronics ST9+ 8/16 mc */
+#define EM_ST7		68		/* STmicroelectronics ST7 8 bit mc */
+#define EM_68HC16	69		/* Motorola MC68HC16 microcontroller */
+#define EM_68HC11	70		/* Motorola MC68HC11 microcontroller */
+#define EM_68HC08	71		/* Motorola MC68HC08 microcontroller */
+#define EM_68HC05	72		/* Motorola MC68HC05 microcontroller */
+#define EM_SVX		73		/* Silicon Graphics SVx */
+#define EM_ST19		74		/* STMicroelectronics ST19 8 bit mc */
+#define EM_VAX		75		/* Digital VAX */
+#define EM_CHRIS	76		/* Axis Communications embedded proc. */
+#define EM_JAVELIN	77		/* Infineon Technologies emb. proc. */
+#define EM_FIREPATH	78		/* Element 14 64-bit DSP Processor */
+#define EM_ZSP		79		/* LSI Logic 16-bit DSP Processor */
+#define EM_MMIX		80		/* Donald Knuth's edu 64-bit proc. */
+#define EM_HUANY	81		/* Harvard University mach-indep objs */
+#define EM_PRISM	82		/* SiTera Prism */
+#define EM_AVR		83		/* Atmel AVR 8-bit microcontroller */
+#define EM_FR30		84		/* Fujitsu FR30 */
+#define EM_D10V		85		/* Mitsubishi DV10V */
+#define EM_D30V		86		/* Mitsubishi DV30V */
+#define EM_V850		87		/* NEC v850 */
+#define EM_M32R		88		/* Mitsubishi M32R */
+#define EM_MN10300	89		/* Matsushita MN10200 */
+#define EM_MN10200	90		/* Matsushita MN10200 */
+#define EM_PJ		91		/* picoJava */
+#define EM_NUM		92		/* number of machine types */
+
+/* Version */
+#define EV_NONE		0		/* Invalid */
+#define EV_CURRENT	1		/* Current */
+#define EV_NUM		2		/* number of versions */
+
+/* Section Header */
+typedef struct {
+	Elf32_Word	sh_name;	/* name - index into section header
+					   string table section */
+	Elf32_Word	sh_type;	/* type */
+	Elf32_Word	sh_flags;	/* flags */
+	Elf32_Addr	sh_addr;	/* address */
+	Elf32_Off	sh_offset;	/* file offset */
+	Elf32_Word	sh_size;	/* section size */
+	Elf32_Word	sh_link;	/* section header table index link */
+	Elf32_Word	sh_info;	/* extra information */
+	Elf32_Word	sh_addralign;	/* address alignment */
+	Elf32_Word	sh_entsize;	/* section entry size */
+} Elf32_Shdr;
+
+typedef struct {
+	Elf64_Word	sh_name;	/* name - index into section header
+					   string table section */
+	Elf64_Word	sh_type;	/* type */
+	Elf64_Xword	sh_flags;	/* flags */
+	Elf64_Addr	sh_addr;	/* address */
+	Elf64_Off	sh_offset;	/* file offset */
+	Elf64_Xword	sh_size;	/* section size */
+	Elf64_Word	sh_link;	/* section header table index link */
+	Elf64_Word	sh_info;	/* extra information */
+	Elf64_Xword	sh_addralign;	/* address alignment */
+	Elf64_Xword	sh_entsize;	/* section entry size */
+} Elf64_Shdr;
+
+/* Special Section Indexes */
+#define SHN_UNDEF	0		/* undefined */
+#define SHN_LORESERVE	0xff00		/* lower bounds of reserved indexes */
+#define SHN_LOPROC	0xff00		/* reserved range for processor */
+#define SHN_HIPROC	0xff1f		/* specific section indexes */
+#define SHN_LOOS	0xff20		/* reserved range for operating */
+#define SHN_HIOS	0xff3f		/* specific semantics */
+#define SHN_ABS		0xfff1		/* absolute value */
+#define SHN_COMMON	0xfff2		/* common symbol */
+#define SHN_XINDEX	0xffff		/* Index is an extra table */
+#define SHN_HIRESERVE	0xffff		/* upper bounds of reserved indexes */
+
+/* sh_type */
+#define SHT_NULL	0		/* inactive */
+#define SHT_PROGBITS	1		/* program defined information */
+#define SHT_SYMTAB	2		/* symbol table section */
+#define SHT_STRTAB	3		/* string table section */
+#define SHT_RELA	4		/* relocation section with addends*/
+#define SHT_HASH	5		/* symbol hash table section */
+#define SHT_DYNAMIC	6		/* dynamic section */
+#define SHT_NOTE	7		/* note section */
+#define SHT_NOBITS	8		/* no space section */
+#define SHT_REL		9		/* relation section without addends */
+#define SHT_SHLIB	10		/* reserved - purpose unknown */
+#define SHT_DYNSYM	11		/* dynamic symbol table section */
+#define SHT_INIT_ARRAY	14		/* Array of constructors */
+#define SHT_FINI_ARRAY	15		/* Array of destructors */
+#define SHT_PREINIT_ARRAY 16		/* Array of pre-constructors */
+#define SHT_GROUP	17		/* Section group */
+#define SHT_SYMTAB_SHNDX 18		/* Extended section indeces */
+#define SHT_NUM		19		/* number of section types */
+#define SHT_LOOS	0x60000000	/* Start OS-specific */
+#define SHT_HIOS	0x6fffffff	/* End OS-specific */
+#define SHT_LOPROC	0x70000000	/* reserved range for processor */
+#define SHT_HIPROC	0x7fffffff	/* specific section header types */
+#define SHT_LOUSER	0x80000000	/* reserved range for application */
+#define SHT_HIUSER	0xffffffff	/* specific indexes */
+
+/* Section names */
+#define ELF_BSS		".bss"		/* uninitialized data */
+#define ELF_COMMENT	".comment"	/* version control information */
+#define ELF_DATA	".data"		/* initialized data */
+#define ELF_DATA1	".data1"	/* initialized data */
+#define ELF_DEBUG	".debug"	/* debug */
+#define ELF_DYNAMIC	".dynamic"	/* dynamic linking information */
+#define ELF_DYNSTR	".dynstr"	/* dynamic string table */
+#define ELF_DYNSYM	".dynsym"	/* dynamic symbol table */
+#define ELF_FINI	".fini"		/* termination code */
+#define ELF_FINI_ARRAY	".fini_array"	/* Array of destructors */
+#define ELF_GOT		".got"		/* global offset table */
+#define ELF_HASH	".hash"		/* symbol hash table */
+#define ELF_INIT	".init"		/* initialization code */
+#define ELF_INIT_ARRAY	".init_array"	/* Array of constuctors */
+#define ELF_INTERP	".interp"	/* Pathname of program interpreter */
+#define ELF_LINE	".line"		/* Symbolic line numnber information */
+#define ELF_NOTE	".note"		/* Contains note section */
+#define ELF_PLT		".plt"		/* Procedure linkage table */
+#define ELF_PREINIT_ARRAY ".preinit_array" /* Array of pre-constructors */
+#define ELF_REL_DATA	".rel.data"	/* relocation data */
+#define ELF_REL_FINI	".rel.fini"	/* relocation termination code */
+#define ELF_REL_INIT	".rel.init"	/* relocation initialization code */
+#define ELF_REL_DYN	".rel.dyn"	/* relocaltion dynamic link info */
+#define ELF_REL_RODATA	".rel.rodata"	/* relocation read-only data */
+#define ELF_REL_TEXT	".rel.text"	/* relocation code */
+#define ELF_RODATA	".rodata"	/* read-only data */
+#define ELF_RODATA1	".rodata1"	/* read-only data */
+#define ELF_SHSTRTAB	".shstrtab"	/* section header string table */
+#define ELF_STRTAB	".strtab"	/* string table */
+#define ELF_SYMTAB	".symtab"	/* symbol table */
+#define ELF_SYMTAB_SHNDX ".symtab_shndx"/* symbol table section index */
+#define ELF_TBSS	".tbss"		/* thread local uninit data */
+#define ELF_TDATA	".tdata"	/* thread local init data */
+#define ELF_TDATA1	".tdata1"	/* thread local init data */
+#define ELF_TEXT	".text"		/* code */
+
+/* Section Attribute Flags - sh_flags */
+#define SHF_WRITE	0x1		/* Writable */
+#define SHF_ALLOC	0x2		/* occupies memory */
+#define SHF_EXECINSTR	0x4		/* executable */
+#define SHF_MERGE	0x10		/* Might be merged */
+#define SHF_STRINGS	0x20		/* Contains NULL terminated strings */
+#define SHF_INFO_LINK	0x40		/* sh_info contains SHT index */
+#define SHF_LINK_ORDER	0x80		/* Preserve order after combining*/
+#define SHF_OS_NONCONFORMING 0x100	/* Non-standard OS specific handling */
+#define SHF_GROUP	0x200		/* Member of section group */
+#define SHF_TLS		0x400		/* Thread local storage */
+#define SHF_MASKOS	0x0ff00000	/* OS specific */
+#define SHF_MASKPROC	0xf0000000	/* reserved bits for processor */
+					/* specific section attributes */
+
+/* Section Group Flags */
+#define GRP_COMDAT	0x1		/* COMDAT group */
+#define GRP_MASKOS	0x0ff00000	/* Mask OS specific flags */
+#define GRP_MASKPROC	0xf0000000	/* Mask processor specific flags */
+
+/* Symbol Table Entry */
+typedef struct {
+	Elf32_Word	st_name;	/* name - index into string table */
+	Elf32_Addr	st_value;	/* symbol value */
+	Elf32_Word	st_size;	/* symbol size */
+	unsigned char	st_info;	/* type and binding */
+	unsigned char	st_other;	/* 0 - no defined meaning */
+	Elf32_Half	st_shndx;	/* section header index */
+} Elf32_Sym;
+
+/* Symbol table index */
+#define STN_UNDEF	0		/* undefined */
+
+/* Extract symbol info - st_info */
+#define ELF32_ST_BIND(x)	((x) >> 4)
+#define ELF32_ST_TYPE(x)	(((unsigned int) x) & 0xf)
+#define ELF32_ST_INFO(b,t)	(((b) << 4) + ((t) & 0xf))
+#define ELF32_ST_VISIBILITY(x)	((x) & 0x3)
+
+/* Symbol Binding - ELF32_ST_BIND - st_info */
+#define STB_LOCAL	0		/* Local symbol */
+#define STB_GLOBAL	1		/* Global symbol */
+#define STB_WEAK	2		/* like global - lower precedence */
+#define STB_NUM		3		/* number of symbol bindings */
+#define STB_LOOS	10		/* reserved range for operating */
+#define STB_HIOS	12		/* system specific symbol bindings */
+#define STB_LOPROC	13		/* reserved range for processor */
+#define STB_HIPROC	15		/* specific symbol bindings */
+
+/* Symbol type - ELF32_ST_TYPE - st_info */
+#define STT_NOTYPE	0		/* not specified */
+#define STT_OBJECT	1		/* data object */
+#define STT_FUNC	2		/* function */
+#define STT_SECTION	3		/* section */
+#define STT_FILE	4		/* file */
+#define STT_NUM		5		/* number of symbol types */
+#define STT_TLS		6		/* Thread local storage symbol */
+#define STT_LOOS	10		/* reserved range for operating */
+#define STT_HIOS	12		/* system specific symbol types */
+#define STT_LOPROC	13		/* reserved range for processor */
+#define STT_HIPROC	15		/* specific symbol types */
+
+/* Symbol visibility - ELF32_ST_VISIBILITY - st_other */
+#define STV_DEFAULT	0		/* Normal visibility rules */
+#define STV_INTERNAL	1		/* Processor specific hidden class */
+#define STV_HIDDEN	2		/* Symbol unavailable in other mods */
+#define STV_PROTECTED	3		/* Not preemptible, not exported */
+
+/* Relocation entry with implicit addend */
+typedef struct {
+	Elf32_Addr	r_offset;	/* offset of relocation */
+	Elf32_Word	r_info;		/* symbol table index and type */
+} Elf32_Rel;
+
+/* Relocation entry with explicit addend */
+typedef struct {
+	Elf32_Addr	r_offset;	/* offset of relocation */
+	Elf32_Word	r_info;		/* symbol table index and type */
+	Elf32_Sword	r_addend;
+} Elf32_Rela;
+
+typedef struct {
+	Elf64_Addr r_offset;	/* Location at which to apply the action */
+	Elf64_Xword r_info;	/* index and type of relocation */
+} Elf64_Rel;
+
+typedef struct {
+	Elf64_Addr r_offset;	/* Location at which to apply the action */
+	Elf64_Xword r_info;	/* index and type of relocation */
+	Elf64_Sxword r_addend;	/* Constant addend used to compute value */
+} Elf64_Rela;
+
+/* Extract relocation info - r_info */
+#define ELF32_R_SYM(i)		((i) >> 8)
+#define ELF32_R_TYPE(i)		((unsigned char) (i))
+#define ELF32_R_INFO(s,t)	(((s) << 8) + (unsigned char)(t))
+
+/* Program Header */
+typedef struct {
+	Elf32_Word	p_type;		/* segment type */
+	Elf32_Off	p_offset;	/* segment offset */
+	Elf32_Addr	p_vaddr;	/* virtual address of segment */
+	Elf32_Addr	p_paddr;	/* physical address of segment */
+	Elf32_Word	p_filesz;	/* number of bytes in file for seg */
+	Elf32_Word	p_memsz;	/* number of bytes in mem. for seg */
+	Elf32_Word	p_flags;	/* flags */
+	Elf32_Word	p_align;	/* memory alignment */
+} Elf32_Phdr;
+
+typedef struct {
+	Elf64_Word	p_type;		/* segment type */
+	Elf64_Word	p_flags;	/* flags */
+	Elf64_Off	p_offset;	/* segment offset */
+	Elf64_Addr	p_vaddr;	/* virtual address of segment */
+	Elf64_Addr	p_paddr;	/* physical address of segment */
+	Elf64_Xword	p_filesz;	/* number of bytes in file for seg */
+	Elf64_Xword	p_memsz;	/* number of bytes in mem. for seg */
+	Elf64_Xword	p_align;	/* memory alignment */
+} Elf64_Phdr;
+
+/* Segment types - p_type */
+#define PT_NULL		0		/* unused */
+#define PT_LOAD		1		/* loadable segment */
+#define PT_DYNAMIC	2		/* dynamic linking section */
+#define PT_INTERP	3		/* the RTLD */
+#define PT_NOTE		4		/* auxiliary information */
+#define PT_SHLIB	5		/* reserved - purpose undefined */
+#define PT_PHDR		6		/* program header */
+#define PT_TLS		7		/* Thread local storage template */
+#define PT_NUM		8		/* Number of segment types */
+#define PT_LOOS		0x60000000	/* reserved range for operating */
+#define PT_HIOS		0x6fffffff	/* system specific segment types */
+#define PT_LOPROC	0x70000000	/* reserved range for processor */
+#define PT_HIPROC	0x7fffffff	/* specific segment types */
+
+/* Segment flags - p_flags */
+#define PF_X		0x1		/* Executable */
+#define PF_W		0x2		/* Writable */
+#define PF_R		0x4		/* Readable */
+#define PF_MASKOS	0x0ff00000	/* OS specific segment flags */
+#define PF_MASKPROC	0xf0000000	/* reserved bits for processor */
+					/* specific segment flags */
+/* Dynamic structure */
+typedef struct {
+	Elf32_Sword	d_tag;		/* controls meaning of d_val */
+	union {
+		Elf32_Word	d_val;	/* Multiple meanings - see d_tag */
+		Elf32_Addr	d_ptr;	/* program virtual address */
+	} d_un;
+} Elf32_Dyn;
+
+extern Elf32_Dyn	_DYNAMIC[];
+
+typedef struct {
+	Elf64_Sxword d_tag;		/* entry tag value */
+	union {
+		Elf64_Xword d_val;
+		Elf64_Addr d_ptr;
+	} d_un;
+} Elf64_Dyn;
+
+#define ELF64_R_SYM(i)			((i) >> 32)
+#define ELF64_R_TYPE(i)			((i) & 0xffffffff)
+
+/* Dynamic Array Tags - d_tag */
+#define DT_NULL		0		/* marks end of _DYNAMIC array */
+#define DT_NEEDED	1		/* string table offset of needed lib */
+#define DT_PLTRELSZ	2		/* size of relocation entries in PLT */
+#define DT_PLTGOT	3		/* address PLT/GOT */
+#define DT_HASH		4		/* address of symbol hash table */
+#define DT_STRTAB	5		/* address of string table */
+#define DT_SYMTAB	6		/* address of symbol table */
+#define DT_RELA		7		/* address of relocation table */
+#define DT_RELASZ	8		/* size of relocation table */
+#define DT_RELAENT	9		/* size of relocation entry */
+#define DT_STRSZ	10		/* size of string table */
+#define DT_SYMENT	11		/* size of symbol table entry */
+#define DT_INIT		12		/* address of initialization func */
+#define DT_FINI		13		/* address of termination function */
+#define DT_SONAME	14		/* string table offset of shared obj */
+#define DT_RPATH	15		/* string table offset of library
+					   search path */
+#define DT_SYMBOLIC	16		/* start sym search in shared obj */
+#define DT_REL		17		/* address of rel. tbl. w addends */
+#define DT_RELSZ	18		/* size of DT_REL relocation table */
+#define DT_RELENT	19		/* size of DT_REL relocation entry */
+#define DT_PLTREL	20		/* PLT referenced relocation entry */
+#define DT_DEBUG	21		/* bugger */
+#define DT_TEXTREL	22		/* Allow rel. mod. to unwritable seg */
+#define DT_JMPREL	23		/* add. of PLT's relocation entries */
+#define DT_BIND_NOW	24		/* Process relocations of object */
+#define DT_INIT_ARRAY	25		/* Array with addresses of init fct */
+#define DT_FINI_ARRAY	26		/* Array with addresses of fini fct */
+#define DT_INIT_ARRAYSZ	27		/* Size in bytes of DT_INIT_ARRAY */
+#define DT_FINI_ARRAYSZ	28		/* Size in bytes of DT_FINI_ARRAY */
+#define DT_RUNPATH	29		/* Library search path */
+#define DT_FLAGS	30		/* Flags for the object being loaded */
+#define DT_ENCODING	32		/* Start of encoded range */
+#define DT_PREINIT_ARRAY 32		/* Array with addresses of preinit fct*/
+#define DT_PREINIT_ARRAYSZ 33		/* size in bytes of DT_PREINIT_ARRAY */
+#define DT_NUM		34		/* Number used */
+#define DT_LOOS		0x60000000	/* reserved range for OS */
+#define DT_HIOS		0x6fffffff	/* specific dynamic array tags */
+#define DT_LOPROC	0x70000000	/* reserved range for processor */
+#define DT_HIPROC	0x7fffffff	/* specific dynamic array tags */
+
+/* Dynamic Tag Flags - d_un.d_val */
+#define DF_ORIGIN	0x01		/* Object may use DF_ORIGIN */
+#define DF_SYMBOLIC	0x02		/* Symbol resolutions starts here */
+#define DF_TEXTREL	0x04		/* Object contains text relocations */
+#define DF_BIND_NOW	0x08		/* No lazy binding for this object */
+#define DF_STATIC_TLS	0x10		/* Static thread local storage */
+
+/* Standard ELF hashing function */
+unsigned long elf_hash(const unsigned char *name);
+
+#define ELF_TARG_VER	1	/* The ver for which this code is intended */
+
+#endif /* __ASSEMBLER */
+
+/* ELF register definitions */
+#define R_386_NONE	0
+#define R_386_32	1
+#define R_386_PC32	2
+#define R_386_GOT32	3
+#define R_386_PLT32	4
+#define R_386_COPY	5
+#define R_386_GLOB_DAT	6
+#define R_386_JMP_SLOT	7
+#define R_386_RELATIVE	8
+#define R_386_GOTOFF	9
+#define R_386_GOTPC	10
+#define R_386_NUM	11
+
+/* x86-64 relocation types */
+#define R_X86_64_NONE		0	/* No reloc */
+#define R_X86_64_64		1	/* Direct 64 bit  */
+#define R_X86_64_PC32		2	/* PC relative 32 bit signed */
+#define R_X86_64_GOT32		3	/* 32 bit GOT entry */
+#define R_X86_64_PLT32		4	/* 32 bit PLT address */
+#define R_X86_64_COPY		5	/* Copy symbol at runtime */
+#define R_X86_64_GLOB_DAT	6	/* Create GOT entry */
+#define R_X86_64_JUMP_SLOT	7	/* Create PLT entry */
+#define R_X86_64_RELATIVE	8	/* Adjust by program base */
+/* 32 bit signed pc relative offset to GOT */
+#define R_X86_64_GOTPCREL	9
+#define R_X86_64_32		10	/* Direct 32 bit zero extended */
+#define R_X86_64_32S		11	/* Direct 32 bit sign extended */
+#define R_X86_64_16		12	/* Direct 16 bit zero extended */
+#define R_X86_64_PC16		13	/* 16 bit sign extended pc relative */
+#define R_X86_64_8		14	/* Direct 8 bit sign extended  */
+#define R_X86_64_PC8		15	/* 8 bit sign extended pc relative */
+
+#define R_X86_64_NUM		16
+
+/*
+ * XXX - PowerPC defines really don't belong in here,
+ * but we'll put them in for simplicity.
+ */
+
+/* Values for Elf32/64_Ehdr.e_flags */
+#define EF_PPC_EMB		0x80000000	/* PowerPC embedded flag */
+
+#define EF_PPC64_ELFV1_ABI	0x00000001
+#define EF_PPC64_ELFV2_ABI	0x00000002
+
+/* Cygnus local bits below */
+#define EF_PPC_RELOCATABLE	0x00010000	/* PowerPC -mrelocatable flag*/
+#define EF_PPC_RELOCATABLE_LIB	0x00008000	/* PowerPC -mrelocatable-lib
+						   flag */
+
+/* PowerPC relocations defined by the ABIs */
+#define R_PPC_NONE		0
+#define R_PPC_ADDR32		1	/* 32bit absolute address */
+#define R_PPC_ADDR24		2	/* 26bit address, 2 bits ignored */
+#define R_PPC_ADDR16		3	/* 16bit absolute address */
+#define R_PPC_ADDR16_LO		4	/* lower 16bit of absolute address */
+#define R_PPC_ADDR16_HI		5	/* high 16bit of absolute address */
+#define R_PPC_ADDR16_HA		6	/* adjusted high 16bit */
+#define R_PPC_ADDR14		7	/* 16bit address, 2 bits ignored */
+#define R_PPC_ADDR14_BRTAKEN	8
+#define R_PPC_ADDR14_BRNTAKEN	9
+#define R_PPC_REL24		10	/* PC relative 26 bit */
+#define R_PPC_REL14		11	/* PC relative 16 bit */
+#define R_PPC_REL14_BRTAKEN	12
+#define R_PPC_REL14_BRNTAKEN	13
+#define R_PPC_GOT16		14
+#define R_PPC_GOT16_LO		15
+#define R_PPC_GOT16_HI		16
+#define R_PPC_GOT16_HA		17
+#define R_PPC_PLTREL24		18
+#define R_PPC_COPY		19
+#define R_PPC_GLOB_DAT		20
+#define R_PPC_JMP_SLOT		21
+#define R_PPC_RELATIVE		22
+#define R_PPC_LOCAL24PC		23
+#define R_PPC_UADDR32		24
+#define R_PPC_UADDR16		25
+#define R_PPC_REL32		26
+#define R_PPC_PLT32		27
+#define R_PPC_PLTREL32		28
+#define R_PPC_PLT16_LO		29
+#define R_PPC_PLT16_HI		30
+#define R_PPC_PLT16_HA		31
+#define R_PPC_SDAREL16		32
+#define R_PPC_SECTOFF		33
+#define R_PPC_SECTOFF_LO	34
+#define R_PPC_SECTOFF_HI	35
+#define R_PPC_SECTOFF_HA	36
+/* Keep this the last entry */
+#define R_PPC_NUM		37
+
+/*
+ * The remaining relocs are from the Embedded ELF ABI, and are not
+ * in the SVR4 ELF ABI.
+ */
+#define R_PPC_EMB_NADDR32	101
+#define R_PPC_EMB_NADDR16	102
+#define R_PPC_EMB_NADDR16_LO	103
+#define R_PPC_EMB_NADDR16_HI	104
+#define R_PPC_EMB_NADDR16_HA	105
+#define R_PPC_EMB_SDAI16	106
+#define R_PPC_EMB_SDA2I16	107
+#define R_PPC_EMB_SDA2REL	108
+#define R_PPC_EMB_SDA21		109	/* 16 bit offset in SDA */
+#define R_PPC_EMB_MRKREF	110
+#define R_PPC_EMB_RELSEC16	111
+#define R_PPC_EMB_RELST_LO	112
+#define R_PPC_EMB_RELST_HI	113
+#define R_PPC_EMB_RELST_HA	114
+#define R_PPC_EMB_BIT_FLD	115
+#define R_PPC_EMB_RELSDA	116	/* 16 bit relative offset in SDA */
+
+/* Diab tool relocations */
+#define R_PPC_DIAB_SDA21_LO	180	/* like EMB_SDA21, but lower 16 bit */
+#define R_PPC_DIAB_SDA21_HI	181	/* like EMB_SDA21, but high 16 bit */
+#define R_PPC_DIAB_SDA21_HA	182	/* like EMB_SDA21, adjusted high 16 */
+#define R_PPC_DIAB_RELSDA_LO	183	/* like EMB_RELSDA, but lower 16 bit */
+#define R_PPC_DIAB_RELSDA_HI	184	/* like EMB_RELSDA, but high 16 bit */
+#define R_PPC_DIAB_RELSDA_HA	185	/* like EMB_RELSDA, adjusted high 16 */
+
+/*
+ * This is a phony reloc to handle any old fashioned TOC16 references
+ * that may still be in object files.
+ */
+#define R_PPC_TOC16		255
+
+ /* ARM relocs */
+#define R_ARM_NONE		0	/* No reloc */
+#define R_ARM_RELATIVE		23	/* Adjust by program base */
+
+/* AArch64 relocs */
+#define R_AARCH64_NONE		0	/* No relocation */
+#define R_AARCH64_RELATIVE	1027	/* Adjust by program base */
+
+/* RISC-V relocations */
+#define R_RISCV_32		1
+#define R_RISCV_64		2
+#define R_RISCV_RELATIVE	3
+
+#ifndef __ASSEMBLER__
+int valid_elf_image(unsigned long addr);
+#endif
+
+#endif /* _ELF_H */
diff --git a/include/env.h b/include/env.h
new file mode 100644
index 0000000..b72239f
--- /dev/null
+++ b/include/env.h
@@ -0,0 +1,336 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common environment functions and definitions
+ *
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __ENV_H
+#define __ENV_H
+
+#include <compiler.h>
+#include <stdbool.h>
+#include <linux/types.h>
+
+struct environment_s;
+
+/* Value for environment validity */
+enum env_valid {
+	ENV_INVALID,	/* No valid environment */
+	ENV_VALID,	/* First or only environment is valid */
+	ENV_REDUND,	/* Redundant environment is valid */
+};
+
+/** enum env_op - environment callback operation */
+enum env_op {
+	env_op_create,
+	env_op_delete,
+	env_op_overwrite,
+};
+
+/** struct env_clbk_tbl - declares a new callback */
+struct env_clbk_tbl {
+	const char *name;		/* Callback name */
+	int (*callback)(const char *name, const char *value, enum env_op op,
+			int flags);
+};
+
+/*
+ * Define a callback that can be associated with variables.
+ * when associated through the ".callbacks" environment variable, the callback
+ * will be executed any time the variable is inserted, overwritten, or deleted.
+ *
+ * For SPL these are silently dropped to reduce code size, since environment
+ * callbacks are not supported with SPL.
+ */
+#ifdef CONFIG_SPL_BUILD
+#define U_BOOT_ENV_CALLBACK(name, callback) \
+	static inline __maybe_unused void _u_boot_env_noop_##name(void) \
+	{ \
+		(void)callback; \
+	}
+#else
+#define U_BOOT_ENV_CALLBACK(name, callback) \
+	ll_entry_declare(struct env_clbk_tbl, name, env_clbk) = \
+	{#name, callback}
+#endif
+
+/** enum env_redund_flags - Flags for the redundand_environment */
+enum env_redund_flags {
+	ENV_REDUND_OBSOLETE = 0,
+	ENV_REDUND_ACTIVE = 1,
+};
+
+/**
+ * env_get_id() - Gets a sequence number for the environment
+ *
+ * This value increments every time the environment changes, so can be used an
+ * an indication of this
+ *
+ * @return environment ID
+ */
+int env_get_id(void);
+
+/**
+ * env_init() - Set up the pre-relocation environment
+ *
+ * This locates the environment or uses the default if nothing is available.
+ * This must be called before env_get() will work.
+ *
+ * @return 0 if OK, -ENODEV if no environment drivers are enabled
+ */
+int env_init(void);
+
+/**
+ * env_relocate() - Set up the post-relocation environment
+ *
+ * This loads the environment into RAM so that it can be modified. This is
+ * called after relocation, before the environment is used
+ */
+void env_relocate(void);
+
+/**
+ * env_match() - Match a name / name=value pair
+ *
+ * This is used prior to relocation for finding envrionment variables
+ *
+ * @name: A simple 'name', or a 'name=value' pair.
+ * @index: The environment index for a 'name2=value2' pair.
+ * @return index for the value if the names match, else -1.
+ */
+int env_match(unsigned char *name, int index);
+
+/**
+ * env_get() - Look up the value of an environment variable
+ *
+ * In U-Boot proper this can be called before relocation (which is when the
+ * environment is loaded from storage, i.e. GD_FLG_ENV_READY is 0). In that
+ * case this function calls env_get_f().
+ *
+ * @varname:	Variable to look up
+ * @return value of variable, or NULL if not found
+ */
+char *env_get(const char *varname);
+
+/**
+ * env_get_f() - Look up the value of an environment variable (early)
+ *
+ * This function is called from env_get() if the environment has not been
+ * loaded yet (GD_FLG_ENV_READY flag is 0). Some environment locations will
+ * support reading the value (slowly) and some will not.
+ *
+ * @varname:	Variable to look up
+ * @return value of variable, or NULL if not found
+ */
+int env_get_f(const char *name, char *buf, unsigned int len);
+
+/**
+ * env_get_yesno() - Read an environment variable as a boolean
+ *
+ * @return 1 if yes/true (Y/y/T/t), -1 if variable does not exist (i.e. default
+ *	to true), 0 if otherwise
+ */
+int env_get_yesno(const char *var);
+
+/**
+ * env_set() - set an environment variable
+ *
+ * This sets or deletes the value of an environment variable. For setting the
+ * value the variable is created if it does not already exist.
+ *
+ * @varname: Variable to adjust
+ * @value: Value to set for the variable, or NULL or "" to delete the variable
+ * @return 0 if OK, 1 on error
+ */
+int env_set(const char *varname, const char *value);
+
+/**
+ * env_get_ulong() - Return an environment variable as an integer value
+ *
+ * Most U-Boot environment variables store hex values. For those which store
+ * (e.g.) base-10 integers, this function can be used to read the value.
+ *
+ * @name:	Variable to look up
+ * @base:	Base to use (e.g. 10 for base 10, 2 for binary)
+ * @default_val: Default value to return if no value is found
+ * @return the value found, or @default_val if none
+ */
+ulong env_get_ulong(const char *name, int base, ulong default_val);
+
+/**
+ * env_set_ulong() - set an environment variable to an integer
+ *
+ * @varname: Variable to adjust
+ * @value: Value to set for the variable (will be converted to a string)
+ * @return 0 if OK, 1 on error
+ */
+int env_set_ulong(const char *varname, ulong value);
+
+/**
+ * env_get_hex() - Return an environment variable as a hex value
+ *
+ * Decode an environment as a hex number (it may or may not have a 0x
+ * prefix). If the environment variable cannot be found, or does not start
+ * with hex digits, the default value is returned.
+ *
+ * @varname:		Variable to decode
+ * @default_val:	Value to return on error
+ */
+ulong env_get_hex(const char *varname, ulong default_val);
+
+/**
+ * env_set_hex() - set an environment variable to a hex value
+ *
+ * @varname: Variable to adjust
+ * @value: Value to set for the variable (will be converted to a hex string)
+ * @return 0 if OK, 1 on error
+ */
+int env_set_hex(const char *varname, ulong value);
+
+/**
+ * env_set_addr - Set an environment variable to an address in hex
+ *
+ * @varname:	Environment variable to set
+ * @addr:	Value to set it to
+ * @return 0 if ok, 1 on error
+ */
+static inline int env_set_addr(const char *varname, const void *addr)
+{
+	return env_set_hex(varname, (ulong)addr);
+}
+
+/**
+ * env_complete() - return an auto-complete for environment variables
+ *
+ * @var: partial name to auto-complete
+ * @maxv: Maximum number of matches to return
+ * @cmdv: Returns a list of possible matches
+ * @maxsz: Size of buffer to use for matches
+ * @buf: Buffer to use for matches
+ * @dollar_comp: non-zero to wrap each match in ${...}
+ * @return number of matches found (in @cmdv)
+ */
+int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf,
+		 bool dollar_comp);
+
+/**
+ * eth_env_get_enetaddr() - Get an ethernet address from the environmnet
+ *
+ * @name: Environment variable to get (e.g. "ethaddr")
+ * @enetaddr: Place to put MAC address (6 bytes)
+ * @return 0 if OK, 1 on error
+ */
+int eth_env_get_enetaddr(const char *name, uint8_t *enetaddr);
+
+/**
+ * eth_env_set_enetaddr() - Set an ethernet address in the environmnet
+ *
+ * @name: Environment variable to set (e.g. "ethaddr")
+ * @enetaddr: Pointer to MAC address to put into the variable (6 bytes)
+ * @return 0 if OK, 1 on error
+ */
+int eth_env_set_enetaddr(const char *name, const uint8_t *enetaddr);
+
+/**
+ * env_fix_drivers() - Updates envdriver as per relocation
+ */
+void env_fix_drivers(void);
+
+/**
+ * env_set_default_vars() - reset variables to their default value
+ *
+ * This resets individual variables to their value in the default environment
+ *
+ * @nvars: Number of variables to set/reset
+ * @vars: List of variables to set/reset
+ * @flags: Flags controlling matching (H_... - see search.h)
+ */
+int env_set_default_vars(int nvars, char *const vars[], int flags);
+
+/**
+ * env_load() - Load the environment from storage
+ *
+ * @return 0 if OK, -ve on error
+ */
+int env_load(void);
+
+/**
+ * env_save() - Save the environment to storage
+ *
+ * @return 0 if OK, -ve on error
+ */
+int env_save(void);
+
+/**
+ * env_erase() - Erase the environment on storage
+ *
+ * @return 0 if OK, -ve on error
+ */
+int env_erase(void);
+
+/**
+ * env_import() - Import from a binary representation into hash table
+ *
+ * This imports the environment from a buffer. The format for each variable is
+ * var=value\0 with a double \0 at the end of the buffer.
+ *
+ * @buf: Buffer containing the environment (struct environemnt_s *)
+ * @check: non-zero to check the CRC at the start of the environment, 0 to
+ *	ignore it
+ * @return 0 if imported successfully, -ENOMSG if the CRC was bad, -EIO if
+ *	something else went wrong
+ */
+int env_import(const char *buf, int check);
+
+/**
+ * env_export() - Export the environment to a buffer
+ *
+ * Export from hash table into binary representation
+ *
+ * @env_out: Buffer to contain the environment (must be large enough!)
+ * @return 0 if OK, 1 on error
+ */
+int env_export(struct environment_s *env_out);
+
+/**
+ * env_import_redund() - Select and import one of two redundant environments
+ *
+ * @buf1: First environment (struct environemnt_s *)
+ * @buf1_read_fail: 0 if buf1 is valid, non-zero if invalid
+ * @buf2: Second environment (struct environemnt_s *)
+ * @buf2_read_fail: 0 if buf2 is valid, non-zero if invalid
+ * @return 0 if OK, -EIO if no environment is valid, -ENOMSG if the CRC was bad
+ */
+int env_import_redund(const char *buf1, int buf1_read_fail,
+		      const char *buf2, int buf2_read_fail);
+
+/**
+ * env_get_default() - Look up a variable from the default environment
+ *
+ * @name: Variable to look up
+ * @return value if found, NULL if not found in default environment
+ */
+char *env_get_default(const char *name);
+
+/* [re]set to the default environment */
+void env_set_default(const char *s, int flags);
+
+/**
+ * env_get_char() - Get a character from the early environment
+ *
+ * This reads from the pre-relocation environment
+ *
+ * @index: Index of character to read (0 = first)
+ * @return character read, or -ve on error
+ */
+int env_get_char(int index);
+
+/**
+ * env_reloc() - Relocate the 'env' sub-commands
+ *
+ * This is used for those unfortunate archs with crappy toolchains
+ */
+void env_reloc(void);
+
+#endif
diff --git a/include/env_attr.h b/include/env_attr.h
new file mode 100644
index 0000000..e0846cc
--- /dev/null
+++ b/include/env_attr.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Joe Hershberger, National Instruments, joe.hershberger@ni.com
+ */
+
+#ifndef __ENV_ATTR_H__
+#define __ENV_ATTR_H__
+
+#define ENV_ATTR_LIST_DELIM	','
+#define ENV_ATTR_SEP		':'
+
+/*
+ * env_attr_walk takes as input an "attr_list" that takes the form:
+ *	attributes = [^,:\s]*
+ *	entry = name[:attributes]
+ *	list = entry[,list]
+ * It will call the "callback" function with the "name" and "attributes"
+ * The callback may return a non-0 to abort the list walk.
+ * This return value will be passed through to the caller.
+ * 0 is returned on success.
+ */
+int env_attr_walk(const char *attr_list,
+	int (*callback)(const char *name, const char *attributes, void *priv),
+	void *priv);
+
+/*
+ * env_attr_lookup takes as input an "attr_list" with the same form as above.
+ * It also takes as input a "name" to look for.
+ * If the name is found in the list, it's value is copied into "attributes".
+ * There is no protection on attributes being too small for the value.
+ * It returns -1 if attributes is NULL, 1 if "name" is not found, 2 if
+ * "attr_list" is NULL.
+ * Returns 0 on success.
+ */
+int env_attr_lookup(const char *attr_list, const char *name, char *attributes);
+
+#endif /* __ENV_ATTR_H__ */
diff --git a/include/env_callback.h b/include/env_callback.h
new file mode 100644
index 0000000..74da20e
--- /dev/null
+++ b/include/env_callback.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Joe Hershberger, National Instruments, joe.hershberger@ni.com
+ */
+
+#ifndef __ENV_CALLBACK_H__
+#define __ENV_CALLBACK_H__
+
+#include <env_flags.h>
+#include <linker_lists.h>
+#include <search.h>
+
+#define ENV_CALLBACK_VAR ".callbacks"
+
+/* Board configs can define additional static callback bindings */
+#ifndef CONFIG_ENV_CALLBACK_LIST_STATIC
+#define CONFIG_ENV_CALLBACK_LIST_STATIC
+#endif
+
+#ifdef CONFIG_SILENT_CONSOLE
+#define SILENT_CALLBACK "silent:silent,"
+#else
+#define SILENT_CALLBACK
+#endif
+
+#ifdef CONFIG_SPLASHIMAGE_GUARD
+#define SPLASHIMAGE_CALLBACK "splashimage:splashimage,"
+#else
+#define SPLASHIMAGE_CALLBACK
+#endif
+
+#ifdef CONFIG_REGEX
+#define ENV_DOT_ESCAPE "\\"
+#else
+#define ENV_DOT_ESCAPE
+#endif
+
+#ifdef CONFIG_CMD_DNS
+#define DNS_CALLBACK "dnsip:dnsip,"
+#else
+#define DNS_CALLBACK
+#endif
+
+#ifdef CONFIG_NET
+#define NET_CALLBACKS \
+	"bootfile:bootfile," \
+	"ipaddr:ipaddr," \
+	"gatewayip:gatewayip," \
+	"netmask:netmask," \
+	"serverip:serverip," \
+	"nvlan:nvlan," \
+	"vlan:vlan," \
+	DNS_CALLBACK \
+	"eth" ETHADDR_WILDCARD "addr:ethaddr,"
+#else
+#define NET_CALLBACKS
+#endif
+
+/*
+ * This list of callback bindings is static, but may be overridden by defining
+ * a new association in the ".callbacks" environment variable.
+ */
+#define ENV_CALLBACK_LIST_STATIC ENV_DOT_ESCAPE ENV_CALLBACK_VAR ":callbacks," \
+	ENV_DOT_ESCAPE ENV_FLAGS_VAR ":flags," \
+	"baudrate:baudrate," \
+	NET_CALLBACKS \
+	"loadaddr:loadaddr," \
+	SILENT_CALLBACK \
+	SPLASHIMAGE_CALLBACK \
+	"stdin:console,stdout:console,stderr:console," \
+	"serial#:serialno," \
+	CONFIG_ENV_CALLBACK_LIST_STATIC
+
+void env_callback_init(struct env_entry *var_entry);
+
+#endif /* __ENV_CALLBACK_H__ */
diff --git a/include/env_default.h b/include/env_default.h
new file mode 100644
index 0000000..56a8bae
--- /dev/null
+++ b/include/env_default.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ */
+
+#include <env_callback.h>
+
+#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
+env_t embedded_environment __UBOOT_ENV_SECTION__(environment) = {
+	ENV_CRC,	/* CRC Sum */
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+	1,		/* Flags: valid */
+#endif
+	{
+#elif defined(DEFAULT_ENV_INSTANCE_STATIC)
+static char default_environment[] = {
+#else
+const uchar default_environment[] = {
+#endif
+#ifndef CONFIG_USE_DEFAULT_ENV_FILE
+#ifdef	CONFIG_ENV_CALLBACK_LIST_DEFAULT
+	ENV_CALLBACK_VAR "=" CONFIG_ENV_CALLBACK_LIST_DEFAULT "\0"
+#endif
+#ifdef	CONFIG_ENV_FLAGS_LIST_DEFAULT
+	ENV_FLAGS_VAR "=" CONFIG_ENV_FLAGS_LIST_DEFAULT "\0"
+#endif
+#ifdef	CONFIG_USE_BOOTARGS
+	"bootargs="	CONFIG_BOOTARGS			"\0"
+#endif
+#ifdef	CONFIG_BOOTCOMMAND
+	"bootcmd="	CONFIG_BOOTCOMMAND		"\0"
+#endif
+#ifdef	CONFIG_RAMBOOTCOMMAND
+	"ramboot="	CONFIG_RAMBOOTCOMMAND		"\0"
+#endif
+#ifdef	CONFIG_NFSBOOTCOMMAND
+	"nfsboot="	CONFIG_NFSBOOTCOMMAND		"\0"
+#endif
+#if defined(CONFIG_BOOTDELAY)
+	"bootdelay="	__stringify(CONFIG_BOOTDELAY)	"\0"
+#endif
+#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
+	"baudrate="	__stringify(CONFIG_BAUDRATE)	"\0"
+#endif
+#ifdef	CONFIG_LOADS_ECHO
+	"loads_echo="	__stringify(CONFIG_LOADS_ECHO)	"\0"
+#endif
+#ifdef	CONFIG_ETHPRIME
+	"ethprime="	CONFIG_ETHPRIME			"\0"
+#endif
+#ifdef	CONFIG_IPADDR
+	"ipaddr="	__stringify(CONFIG_IPADDR)	"\0"
+#endif
+#ifdef	CONFIG_SERVERIP
+	"serverip="	__stringify(CONFIG_SERVERIP)	"\0"
+#endif
+#ifdef	CONFIG_SYS_AUTOLOAD
+	"autoload="	CONFIG_SYS_AUTOLOAD		"\0"
+#endif
+#ifdef	CONFIG_PREBOOT
+	"preboot="	CONFIG_PREBOOT			"\0"
+#endif
+#ifdef	CONFIG_ROOTPATH
+	"rootpath="	CONFIG_ROOTPATH			"\0"
+#endif
+#ifdef	CONFIG_GATEWAYIP
+	"gatewayip="	__stringify(CONFIG_GATEWAYIP)	"\0"
+#endif
+#ifdef	CONFIG_NETMASK
+	"netmask="	__stringify(CONFIG_NETMASK)	"\0"
+#endif
+#ifdef	CONFIG_HOSTNAME
+	"hostname="	CONFIG_HOSTNAME	"\0"
+#endif
+#ifdef	CONFIG_BOOTFILE
+	"bootfile="	CONFIG_BOOTFILE			"\0"
+#endif
+#ifdef	CONFIG_LOADADDR
+	"loadaddr="	__stringify(CONFIG_LOADADDR)	"\0"
+#endif
+#ifdef	CONFIG_CLOCKS_IN_MHZ
+	"clocks_in_mhz=1\0"
+#endif
+#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
+	"pcidelay="	__stringify(CONFIG_PCI_BOOTDELAY)"\0"
+#endif
+#ifdef	CONFIG_ENV_VARS_UBOOT_CONFIG
+	"arch="		CONFIG_SYS_ARCH			"\0"
+#ifdef CONFIG_SYS_CPU
+	"cpu="		CONFIG_SYS_CPU			"\0"
+#endif
+#ifdef CONFIG_SYS_BOARD
+	"board="	CONFIG_SYS_BOARD		"\0"
+	"board_name="	CONFIG_SYS_BOARD		"\0"
+#endif
+#ifdef CONFIG_SYS_VENDOR
+	"vendor="	CONFIG_SYS_VENDOR		"\0"
+#endif
+#ifdef CONFIG_SYS_SOC
+	"soc="		CONFIG_SYS_SOC			"\0"
+#endif
+#endif
+#if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0)
+	"bootlimit="	__stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0"
+#endif
+#ifdef	CONFIG_EXTRA_ENV_SETTINGS
+	CONFIG_EXTRA_ENV_SETTINGS
+#endif
+	"\0"
+#else /* CONFIG_USE_DEFAULT_ENV_FILE */
+#include "generated/defaultenv_autogenerated.h"
+#endif
+#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
+	}
+#endif
+};
diff --git a/include/env_flags.h b/include/env_flags.h
new file mode 100644
index 0000000..725841a
--- /dev/null
+++ b/include/env_flags.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Joe Hershberger, National Instruments, joe.hershberger@ni.com
+ */
+
+#ifndef __ENV_FLAGS_H__
+#define __ENV_FLAGS_H__
+
+enum env_flags_vartype {
+	env_flags_vartype_string,
+	env_flags_vartype_decimal,
+	env_flags_vartype_hex,
+	env_flags_vartype_bool,
+#ifdef CONFIG_CMD_NET
+	env_flags_vartype_ipaddr,
+	env_flags_vartype_macaddr,
+#endif
+	env_flags_vartype_end
+};
+
+enum env_flags_varaccess {
+	env_flags_varaccess_any,
+	env_flags_varaccess_readonly,
+	env_flags_varaccess_writeonce,
+	env_flags_varaccess_changedefault,
+	env_flags_varaccess_end
+};
+
+#define ENV_FLAGS_VAR ".flags"
+#define ENV_FLAGS_ATTR_MAX_LEN 2
+#define ENV_FLAGS_VARTYPE_LOC 0
+#define ENV_FLAGS_VARACCESS_LOC 1
+
+#ifndef CONFIG_ENV_FLAGS_LIST_STATIC
+#define CONFIG_ENV_FLAGS_LIST_STATIC ""
+#endif
+
+#ifdef CONFIG_NET
+#ifdef CONFIG_REGEX
+#define ETHADDR_WILDCARD "\\d*"
+#else
+#define ETHADDR_WILDCARD
+#endif
+#ifdef CONFIG_ENV_OVERWRITE
+#define ETHADDR_FLAGS "eth" ETHADDR_WILDCARD "addr:ma,"
+#else
+#ifdef CONFIG_OVERWRITE_ETHADDR_ONCE
+#define ETHADDR_FLAGS "eth" ETHADDR_WILDCARD "addr:mc,"
+#else
+#define ETHADDR_FLAGS "eth" ETHADDR_WILDCARD "addr:mo,"
+#endif
+#endif
+#define NET_FLAGS \
+	"ipaddr:i," \
+	"gatewayip:i," \
+	"netmask:i," \
+	"serverip:i," \
+	"nvlan:d," \
+	"vlan:d," \
+	"dnsip:i,"
+#else
+#define ETHADDR_FLAGS
+#define NET_FLAGS
+#endif
+
+#ifndef CONFIG_ENV_OVERWRITE
+#define SERIAL_FLAGS "serial#:so,"
+#else
+#define SERIAL_FLAGS ""
+#endif
+
+#define ENV_FLAGS_LIST_STATIC \
+	ETHADDR_FLAGS \
+	NET_FLAGS \
+	SERIAL_FLAGS \
+	CONFIG_ENV_FLAGS_LIST_STATIC
+
+#ifdef CONFIG_CMD_ENV_FLAGS
+/*
+ * Print the whole list of available type flags.
+ */
+void env_flags_print_vartypes(void);
+/*
+ * Print the whole list of available access flags.
+ */
+void env_flags_print_varaccess(void);
+/*
+ * Return the name of the type.
+ */
+const char *env_flags_get_vartype_name(enum env_flags_vartype type);
+/*
+ * Return the name of the access.
+ */
+const char *env_flags_get_varaccess_name(enum env_flags_varaccess access);
+#endif
+
+/*
+ * Parse the flags string from a .flags attribute list into the vartype enum.
+ */
+enum env_flags_vartype env_flags_parse_vartype(const char *flags);
+/*
+ * Parse the flags string from a .flags attribute list into the varaccess enum.
+ */
+enum env_flags_varaccess env_flags_parse_varaccess(const char *flags);
+/*
+ * Parse the binary flags from a hash table entry into the varaccess enum.
+ */
+enum env_flags_varaccess env_flags_parse_varaccess_from_binflags(int binflags);
+
+#ifdef CONFIG_CMD_NET
+/*
+ * Check if a string has the format of an Ethernet MAC address
+ */
+int eth_validate_ethaddr_str(const char *addr);
+#endif
+
+#ifdef USE_HOSTCC
+/*
+ * Look up the type of a variable directly from the .flags var.
+ */
+enum env_flags_vartype env_flags_get_type(const char *name);
+/*
+ * Look up the access of a variable directly from the .flags var.
+ */
+enum env_flags_varaccess env_flags_get_access(const char *name);
+/*
+ * Validate the newval for its type to conform with the requirements defined by
+ * its flags (directly looked at the .flags var).
+ */
+int env_flags_validate_type(const char *name, const char *newval);
+/*
+ * Validate the newval for its access to conform with the requirements defined
+ * by its flags (directly looked at the .flags var).
+ */
+int env_flags_validate_access(const char *name, int check_mask);
+/*
+ * Validate that the proposed access to variable "name" is valid according to
+ * the defined flags for that variable, if any.
+ */
+int env_flags_validate_varaccess(const char *name, int check_mask);
+/*
+ * Validate the parameters passed to "env set" for type compliance
+ */
+int env_flags_validate_env_set_params(char *name, char *const val[], int count);
+
+#else /* !USE_HOSTCC */
+
+#include <env.h>
+#include <search.h>
+
+/*
+ * When adding a variable to the environment, initialize the flags for that
+ * variable.
+ */
+void env_flags_init(struct env_entry *var_entry);
+
+/*
+ * Validate the newval for to conform with the requirements defined by its flags
+ */
+int env_flags_validate(const struct env_entry *item, const char *newval,
+		       enum env_op op, int flag);
+
+#endif /* USE_HOSTCC */
+
+/*
+ * These are the binary flags used in the environment entry->flags variable to
+ * decribe properties of veriables in the table
+ */
+#define ENV_FLAGS_VARTYPE_BIN_MASK			0x00000007
+/* The actual variable type values use the enum value (within the mask) */
+#define ENV_FLAGS_VARACCESS_PREVENT_DELETE		0x00000008
+#define ENV_FLAGS_VARACCESS_PREVENT_CREATE		0x00000010
+#define ENV_FLAGS_VARACCESS_PREVENT_OVERWR		0x00000020
+#define ENV_FLAGS_VARACCESS_PREVENT_NONDEF_OVERWR	0x00000040
+#define ENV_FLAGS_VARACCESS_BIN_MASK			0x00000078
+
+#endif /* __ENV_FLAGS_H__ */
diff --git a/include/env_internal.h b/include/env_internal.h
new file mode 100644
index 0000000..88c36b3
--- /dev/null
+++ b/include/env_internal.h
@@ -0,0 +1,278 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Internal environment header file. This includes direct access to environment
+ * information such as its size and offset, direct access to the default
+ * environment and embedded environment (if used). It also provides environment
+ * drivers with various declarations.
+ *
+ * It should not be included by board files, drivers and code other than that
+ * related to the environment implementation.
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef _ENV_INTERNAL_H_
+#define _ENV_INTERNAL_H_
+
+#include <linux/kconfig.h>
+
+/**************************************************************************
+ *
+ * The "environment" is stored as a list of '\0' terminated
+ * "name=value" strings. The end of the list is marked by a double
+ * '\0'. New entries are always added at the end. Deleting an entry
+ * shifts the remaining entries to the front. Replacing an entry is a
+ * combination of deleting the old value and adding the new one.
+ *
+ * The environment is preceded by a 32 bit CRC over the data part.
+ *
+ *************************************************************************/
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef	CONFIG_ENV_ADDR
+#  define	CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef	CONFIG_ENV_OFFSET
+#  define	CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+# endif
+# if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND)
+#  define	CONFIG_ENV_ADDR_REDUND	\
+		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
+# endif
+# if defined(CONFIG_ENV_SECT_SIZE) || defined(CONFIG_ENV_SIZE)
+#  ifndef	CONFIG_ENV_SECT_SIZE
+#   define	CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#  endif
+#  ifndef	CONFIG_ENV_SIZE
+#   define	CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+#  endif
+# else
+#  error "Both CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE undefined"
+# endif
+# if defined(CONFIG_ENV_ADDR_REDUND) && !defined(CONFIG_ENV_SIZE_REDUND)
+#  define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+# endif
+# if	(CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) &&		\
+	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) <=			\
+	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#  define ENV_IS_EMBEDDED
+# endif
+# if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
+#  define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+# ifdef CONFIG_ENV_IS_EMBEDDED
+#  error "do not define CONFIG_ENV_IS_EMBEDDED in your board config"
+#  error "it is calculated automatically for you"
+# endif
+#endif	/* CONFIG_ENV_IS_IN_FLASH */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+# ifdef CONFIG_ENV_OFFSET_REDUND
+#  define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_NAND)
+# if defined(CONFIG_ENV_OFFSET_OOB)
+#  ifdef CONFIG_ENV_OFFSET_REDUND
+#   error "CONFIG_ENV_OFFSET_REDUND is not supported when CONFIG_ENV_OFFSET_OOB"
+#   error "is set"
+#  endif
+extern unsigned long nand_env_oob_offset;
+#  define CONFIG_ENV_OFFSET nand_env_oob_offset
+# else
+#  ifndef CONFIG_ENV_OFFSET
+#   error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND"
+#  endif
+#  ifdef CONFIG_ENV_OFFSET_REDUND
+#   define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#  endif
+# endif /* CONFIG_ENV_OFFSET_OOB */
+# ifndef CONFIG_ENV_SIZE
+#  error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_NAND"
+# endif
+#endif /* CONFIG_ENV_IS_IN_NAND */
+
+#if defined(CONFIG_ENV_IS_IN_UBI)
+# ifndef CONFIG_ENV_UBI_PART
+#  error "Need to define CONFIG_ENV_UBI_PART when using CONFIG_ENV_IS_IN_UBI"
+# endif
+# ifndef CONFIG_ENV_UBI_VOLUME
+#  error "Need to define CONFIG_ENV_UBI_VOLUME when using CONFIG_ENV_IS_IN_UBI"
+# endif
+# if defined(CONFIG_ENV_UBI_IS_VOLUME_REDUND)
+#  define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+# ifndef CONFIG_ENV_SIZE
+#  error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_UBI"
+# endif
+# ifndef CONFIG_CMD_UBI
+#  error "Need to define CONFIG_CMD_UBI when using CONFIG_ENV_IS_IN_UBI"
+# endif
+#endif /* CONFIG_ENV_IS_IN_UBI */
+
+/* Embedded env is only supported for some flash types */
+#ifdef CONFIG_ENV_IS_EMBEDDED
+# if	!defined(CONFIG_ENV_IS_IN_FLASH)	&& \
+	!defined(CONFIG_ENV_IS_IN_NAND)		&& \
+	!defined(CONFIG_ENV_IS_IN_ONENAND)	&& \
+	!defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#  error "CONFIG_ENV_IS_EMBEDDED not supported for your flash type"
+# endif
+#endif
+
+/*
+ * For the flash types where embedded env is supported, but it cannot be
+ * calculated automatically (i.e. NAND), take the board opt-in.
+ */
+#if defined(CONFIG_ENV_IS_EMBEDDED) && !defined(ENV_IS_EMBEDDED)
+# define ENV_IS_EMBEDDED
+#endif
+
+/* The build system likes to know if the env is embedded */
+#ifdef DO_DEPS_ONLY
+# ifdef ENV_IS_EMBEDDED
+#  ifndef CONFIG_ENV_IS_EMBEDDED
+#   define CONFIG_ENV_IS_EMBEDDED
+#  endif
+# endif
+#endif
+
+#include "compiler.h"
+
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# define ENV_HEADER_SIZE	(sizeof(uint32_t) + 1)
+#else
+# define ENV_HEADER_SIZE	(sizeof(uint32_t))
+#endif
+
+#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
+
+/*
+ * If the environment is in RAM, allocate extra space for it in the malloc
+ * region.
+ */
+#if defined(CONFIG_ENV_IS_EMBEDDED)
+#define TOTAL_MALLOC_LEN	CONFIG_SYS_MALLOC_LEN
+#elif (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE < CONFIG_SYS_MONITOR_BASE) || \
+      (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) || \
+      defined(CONFIG_ENV_IS_IN_NVRAM)
+#define	TOTAL_MALLOC_LEN	(CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
+#else
+#define	TOTAL_MALLOC_LEN	CONFIG_SYS_MALLOC_LEN
+#endif
+
+typedef struct environment_s {
+	uint32_t	crc;		/* CRC32 over data bytes	*/
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+	unsigned char	flags;		/* active/obsolete flags ENVF_REDUND_ */
+#endif
+	unsigned char	data[ENV_SIZE]; /* Environment data		*/
+} env_t;
+
+#ifdef ENV_IS_EMBEDDED
+extern env_t embedded_environment;
+#endif /* ENV_IS_EMBEDDED */
+
+extern const unsigned char default_environment[];
+
+#ifndef DO_DEPS_ONLY
+
+#include <env_attr.h>
+#include <env_callback.h>
+#include <env_flags.h>
+#include <search.h>
+
+enum env_location {
+	ENVL_UNKNOWN,
+	ENVL_EEPROM,
+	ENVL_EXT4,
+	ENVL_FAT,
+	ENVL_FLASH,
+	ENVL_MMC,
+	ENVL_NAND,
+	ENVL_NVRAM,
+	ENVL_ONENAND,
+	ENVL_REMOTE,
+	ENVL_SPI_FLASH,
+	ENVL_UBI,
+	ENVL_NOWHERE,
+
+	ENVL_COUNT,
+};
+
+/* value for the various operations we want to perform on the env */
+enum env_operation {
+	ENVOP_GET_CHAR,	/* we want to call the get_char function */
+	ENVOP_INIT,	/* we want to call the init function */
+	ENVOP_LOAD,	/* we want to call the load function */
+	ENVOP_SAVE,	/* we want to call the save function */
+	ENVOP_ERASE,	/* we want to call the erase function */
+};
+
+struct env_driver {
+	const char *name;
+	enum env_location location;
+
+	/**
+	 * load() - Load the environment from storage
+	 *
+	 * This method is optional. If not provided, no environment will be
+	 * loaded.
+	 *
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*load)(void);
+
+	/**
+	 * save() - Save the environment to storage
+	 *
+	 * This method is required for 'saveenv' to work.
+	 *
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*save)(void);
+
+	/**
+	 * erase() - Erase the environment on storage
+	 *
+	 * This method is optional and required for 'eraseenv' to work.
+	 *
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*erase)(void);
+
+	/**
+	 * init() - Set up the initial pre-relocation environment
+	 *
+	 * This method is optional.
+	 *
+	 * @return 0 if OK, -ENOENT if no initial environment could be found,
+	 * other -ve on error
+	 */
+	int (*init)(void);
+};
+
+/* Declare a new environment location driver */
+#define U_BOOT_ENV_LOCATION(__name)					\
+	ll_entry_declare(struct env_driver, __name, env_driver)
+
+/* Declare the name of a location */
+#ifdef CONFIG_CMD_SAVEENV
+#define ENV_NAME(_name) .name = _name,
+#else
+#define ENV_NAME(_name)
+#endif
+
+#ifdef CONFIG_CMD_SAVEENV
+#define env_save_ptr(x) x
+#else
+#define env_save_ptr(x) NULL
+#endif
+
+extern struct hsearch_data env_htab;
+
+#endif /* DO_DEPS_ONLY */
+
+#endif /* _ENV_INTERNAL_H_ */
diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h
new file mode 100644
index 0000000..684a744
--- /dev/null
+++ b/include/environment/ti/boot.h
@@ -0,0 +1,219 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Boot related environment variable definitions on TI boards.
+ *
+ * (C) Copyright 2017 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ */
+
+#ifndef __TI_BOOT_H
+#define __TI_BOOT_H
+
+#ifndef CONSOLEDEV
+#define CONSOLEDEV "ttyS2"
+#endif
+
+#define VBMETA_PART_SIZE		(64 * 1024)
+
+#if defined(CONFIG_LIBAVB)
+#define VBMETA_PART \
+	"name=vbmeta,size=" __stringify(VBMETA_PART_SIZE) \
+	",uuid=${uuid_gpt_vbmeta};"
+#else
+#define VBMETA_PART			""
+#endif
+
+#if defined(CONFIG_CMD_AB_SELECT)
+#define COMMON_PARTS \
+	"name=boot_a,size=20M,uuid=${uuid_gpt_boot_a};" \
+	"name=boot_b,size=20M,uuid=${uuid_gpt_boot_b};" \
+	"name=system_a,size=1024M,uuid=${uuid_gpt_system_a};" \
+	"name=system_b,size=1024M,uuid=${uuid_gpt_system_b};"
+#else
+#define COMMON_PARTS \
+	"name=boot,size=20M,uuid=${uuid_gpt_boot};" \
+	"name=system,size=1024M,uuid=${uuid_gpt_system};"
+#endif
+
+#ifndef PARTS_DEFAULT
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+	/* Linux partitions */ \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader};" \
+	"name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \
+	/* Android partitions */ \
+	"partitions_android=" \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
+	"name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader};" \
+	"name=uboot-env,start=2432K,size=256K,uuid=${uuid_gpt_reserved};" \
+	"name=misc,size=128K,uuid=${uuid_gpt_misc};" \
+	"name=recovery,size=40M,uuid=${uuid_gpt_recovery};" \
+	COMMON_PARTS \
+	"name=vendor,size=256M,uuid=${uuid_gpt_vendor};" \
+	VBMETA_PART \
+	"name=userdata,size=-,uuid=${uuid_gpt_userdata}"
+#endif /* PARTS_DEFAULT */
+
+#if defined(CONFIG_CMD_AVB)
+#define AVB_VERIFY_CHECK "if run avb_verify; then " \
+				"echo AVB verification OK.;" \
+				"set bootargs $bootargs $avb_bootargs;" \
+			"else " \
+				"echo AVB verification failed.;" \
+			"exit; fi;"
+#define AVB_VERIFY_CMD "avb_verify=avb init 1; avb verify;\0"
+#else
+#define AVB_VERIFY_CHECK ""
+#define AVB_VERIFY_CMD ""
+#endif
+
+#define CONTROL_PARTITION "misc"
+
+#if defined(CONFIG_CMD_AB_SELECT)
+#define AB_SELECT \
+	"if part number mmc 1 " CONTROL_PARTITION " control_part_number; " \
+	"then " \
+		"echo " CONTROL_PARTITION \
+			" partition number:${control_part_number};" \
+		"ab_select slot_name mmc ${mmcdev}:${control_part_number};" \
+	"else " \
+		"echo " CONTROL_PARTITION " partition not found;" \
+		"exit;" \
+	"fi;" \
+	"setenv slot_suffix _${slot_name};" \
+	"if part number mmc ${mmcdev} system${slot_suffix} " \
+	"system_part_number; then " \
+		"setenv bootargs_ab " \
+		"ro root=/dev/mmcblk${mmcdev}p${system_part_number} " \
+		"rootwait init=/init skip_initramfs " \
+		"androidboot.slot_suffix=${slot_suffix};" \
+		"echo A/B cmdline addition: ${bootargs_ab};" \
+		"setenv bootargs ${bootargs} ${bootargs_ab};" \
+	"else " \
+		"echo system${slot_suffix} partition not found;" \
+	"fi;"
+#else
+#define AB_SELECT ""
+#endif
+
+#define FASTBOOT_CMD \
+	"echo Booting into fastboot ...; " \
+	"fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; "
+
+#define DEFAULT_COMMON_BOOT_TI_ARGS \
+	"console=" CONSOLEDEV ",115200n8\0" \
+	"fdtfile=undefined\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
+	AVB_VERIFY_CMD \
+	"partitions=" PARTS_DEFAULT "\0" \
+	"optargs=\0" \
+	"dofastboot=0\0" \
+	"emmc_linux_boot=" \
+		"echo Trying to boot Linux from eMMC ...; " \
+		"setenv mmcdev 1; " \
+		"setenv bootpart 1:2; " \
+		"setenv mmcroot /dev/mmcblk0p2 rw; " \
+		"run mmcboot;\0" \
+	"emmc_android_boot=" \
+		"if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \
+		CONTROL_PARTITION "; then " \
+			"if bcb test command = bootonce-bootloader; then " \
+				"echo BCB: Bootloader boot...; " \
+				"bcb clear command; bcb store; " \
+				FASTBOOT_CMD \
+			"elif bcb test command = boot-recovery; then " \
+				"echo BCB: Recovery boot...; " \
+				"echo Warning: recovery is not implemented; " \
+				"echo Performing normal boot for now...; " \
+				"bcb clear command; bcb store; " \
+				"run emmc_android_normal_boot; " \
+			"else " \
+				"echo BCB: Normal boot requested...; " \
+				"run emmc_android_normal_boot; " \
+			"fi; " \
+		"else " \
+			"echo Warning: BCB is corrupted or does not exist; " \
+			"echo Performing normal boot...; " \
+			"run emmc_android_normal_boot; " \
+		"fi;\0" \
+	"emmc_android_normal_boot=" \
+		"echo Trying to boot Android from eMMC ...; " \
+		"run update_to_fit; " \
+		"setenv eval_bootargs setenv bootargs $bootargs; " \
+		"run eval_bootargs; " \
+		"setenv mmcdev 1; " \
+		"setenv machid fe6; " \
+		"mmc dev $mmcdev; " \
+		"mmc rescan; " \
+		AVB_VERIFY_CHECK \
+		AB_SELECT \
+		"if part start mmc ${mmcdev} boot${slot_suffix} boot_start; " \
+		"then " \
+			"part size mmc ${mmcdev} boot${slot_suffix} " \
+				"boot_size; " \
+			"mmc read ${loadaddr} ${boot_start} ${boot_size}; " \
+			"bootm ${loadaddr}#${fdtfile}; " \
+		"else " \
+			"echo boot${slot_suffix} partition not found; " \
+		"fi;\0"
+
+#ifdef CONFIG_OMAP54XX
+
+#define DEFAULT_FDT_TI_ARGS \
+	"findfdt="\
+		"if test $board_name = omap5_uevm; then " \
+			"setenv fdtfile omap5-uevm.dtb; fi; " \
+		"if test $board_name = dra7xx; then " \
+			"setenv fdtfile dra7-evm.dtb; fi;" \
+		"if test $board_name = dra72x-revc; then " \
+			"setenv fdtfile dra72-evm-revc.dtb; fi;" \
+		"if test $board_name = dra72x; then " \
+			"setenv fdtfile dra72-evm.dtb; fi;" \
+		"if test $board_name = dra71x; then " \
+			"setenv fdtfile dra71-evm.dtb; fi;" \
+		"if test $board_name = dra76x_acd; then " \
+			"setenv fdtfile dra76-evm.dtb; fi;" \
+		"if test $board_name = beagle_x15; then " \
+			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+		"if test $board_name = beagle_x15_revb1; then " \
+			"setenv fdtfile am57xx-beagle-x15-revb1.dtb; fi;" \
+		"if test $board_name = beagle_x15_revc; then " \
+			"setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \
+		"if test $board_name = am572x_idk; then " \
+			"setenv fdtfile am572x-idk.dtb; fi;" \
+		"if test $board_name = am574x_idk; then " \
+			"setenv fdtfile am574x-idk.dtb; fi;" \
+		"if test $board_name = am57xx_evm; then " \
+			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+		"if test $board_name = am57xx_evm_reva3; then " \
+			"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
+		"if test $board_name = am571x_idk; then " \
+			"setenv fdtfile am571x-idk.dtb; fi;" \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0"
+
+#define CONFIG_BOOTCOMMAND \
+	"if test ${dofastboot} -eq 1; then " \
+		"echo Boot fastboot requested, resetting dofastboot ...;" \
+		"setenv dofastboot 0; saveenv;" \
+		FASTBOOT_CMD \
+	"fi;" \
+	"if test ${boot_fit} -eq 1; then "	\
+		"run update_to_fit;"	\
+	"fi;"	\
+	"run findfdt; " \
+	"run envboot; " \
+	"run mmcboot;" \
+	"run emmc_linux_boot; " \
+	"run emmc_android_boot; " \
+	""
+
+#endif /* CONFIG_OMAP54XX */
+
+#endif /* __TI_BOOT_H */
diff --git a/include/environment/ti/dfu.h b/include/environment/ti/dfu.h
new file mode 100644
index 0000000..9f7ea03
--- /dev/null
+++ b/include/environment/ti/dfu.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for DFU on TI boards.
+ */
+
+#ifndef __TI_DFU_H
+#define __TI_DFU_H
+
+#define DFU_ALT_INFO_MMC \
+	"dfu_alt_info_mmc=" \
+	"boot part 0 1;" \
+	"rootfs part 0 2;" \
+	"MLO fat 0 1;" \
+	"MLO.raw raw 0x100 0x100;" \
+	"u-boot.img.raw raw 0x300 0x1000;" \
+	"u-env.raw raw 0x1300 0x200;" \
+	"spl-os-args.raw raw 0x1500 0x200;" \
+	"spl-os-image.raw raw 0x1700 0x6900;" \
+	"spl-os-args fat 0 1;" \
+	"spl-os-image fat 0 1;" \
+	"u-boot.img fat 0 1;" \
+	"uEnv.txt fat 0 1\0"
+
+#define DFU_ALT_INFO_EMMC \
+	"dfu_alt_info_emmc=" \
+	"rawemmc raw 0 3751936;" \
+	"boot part 1 1;" \
+	"rootfs part 1 2;" \
+	"MLO fat 1 1;" \
+	"MLO.raw raw 0x100 0x100;" \
+	"u-boot.img.raw raw 0x300 0x1000;" \
+	"u-env.raw raw 0x1300 0x200;" \
+	"spl-os-args.raw raw 0x1500 0x200;" \
+	"spl-os-image.raw raw 0x1700 0x6900;" \
+	"spl-os-args fat 1 1;" \
+	"spl-os-image fat 1 1;" \
+	"u-boot.img fat 1 1;" \
+	"uEnv.txt fat 1 1\0"
+
+#ifdef CONFIG_NAND
+#define DFU_ALT_INFO_NAND \
+	"dfu_alt_info_nand=" \
+	"SPL part 0 1;" \
+	"SPL.backup1 part 0 2;" \
+	"SPL.backup2 part 0 3;" \
+	"SPL.backup3 part 0 4;" \
+	"u-boot part 0 5;" \
+	"u-boot-spl-os part 0 6;" \
+	"kernel part 0 8;" \
+	"rootfs part 0 9\0"
+#else
+#define DFU_ALT_INFO_NAND ""
+#endif
+
+#define DFU_ALT_INFO_RAM \
+	"dfu_alt_info_ram=" \
+	"kernel ram 0x80200000 0x4000000;" \
+	"fdt ram 0x80f80000 0x80000;" \
+	"ramdisk ram 0x81000000 0x4000000\0"
+
+#define DFU_ALT_INFO_QSPI_XIP \
+	"dfu_alt_info_qspi=" \
+	"u-boot.bin raw 0x0 0x080000;" \
+	"u-boot.backup raw 0x080000 0x080000;" \
+	"u-boot-spl-os raw 0x100000 0x010000;" \
+	"u-boot-env raw 0x110000 0x010000;" \
+	"u-boot-env.backup raw 0x120000 0x010000;" \
+	"kernel raw 0x130000 0x800000\0"
+
+#define DFU_ALT_INFO_QSPI \
+	"dfu_alt_info_qspi=" \
+	"MLO raw 0x0 0x040000;" \
+	"u-boot.img raw 0x040000 0x0100000;" \
+	"u-boot-spl-os raw 0x140000 0x080000;" \
+	"u-boot-env raw 0x1C0000 0x010000;" \
+	"u-boot-env.backup raw 0x1D0000 0x010000;" \
+	"kernel raw 0x1E0000 0x800000\0"
+
+#endif /* __TI_DFU_H */
diff --git a/include/environment/ti/k3_rproc.h b/include/environment/ti/k3_rproc.h
new file mode 100644
index 0000000..3418cb4
--- /dev/null
+++ b/include/environment/ti/k3_rproc.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * rproc environment variable definitions for various TI K3 SoCs.
+ */
+
+#ifndef __TI_RPROC_H
+#define __TI_RPROC_H
+
+/*
+ * should contain a list of <rproc_id fw_name> tuplies,
+ * override in board config files with the actual list
+ */
+#define DEFAULT_RPROCS ""
+
+#ifdef CONFIG_CMD_REMOTEPROC
+#define EXTRA_ENV_RPROC_SETTINGS					\
+	"dorprocboot=0\0"						\
+	"boot_rprocs="							\
+		"if test ${dorprocboot} -eq 1 && test ${boot} = mmc; then "\
+			"rproc init;"					\
+			"run boot_rprocs_mmc;"				\
+		"fi;\0"							\
+	"rproc_load_and_boot_one="					\
+		"if load mmc ${bootpart} $loadaddr ${rproc_fw}; then "	\
+			"if rproc load ${rproc_id} ${loadaddr} ${filesize}; then "\
+				"rproc start ${rproc_id};"		\
+			"fi;"						\
+		"fi\0"							\
+	"boot_rprocs_mmc="						\
+		"env set rproc_id;"					\
+		"env set rproc_fw;"					\
+		"for i in ${rproc_fw_binaries} ; do "			\
+			"if test -z \"${rproc_id}\" ; then "		\
+				"env set rproc_id $i;"			\
+			"else "						\
+				"env set rproc_fw $i;"			\
+				"run rproc_load_and_boot_one;"		\
+				"env set rproc_id;"			\
+				"env set rproc_fw;"			\
+			"fi;"						\
+		"done\0"						\
+	"rproc_fw_binaries="						\
+		DEFAULT_RPROCS						\
+		"\0"
+#else
+#define EXTRA_ENV_RPROC_SETTINGS					\
+	"boot_rprocs= \0"
+#endif /* CONFIG_CMD_REMOTEPROC */
+
+#endif /* __TI_RPROC_H */
diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h
new file mode 100644
index 0000000..bb4af0a
--- /dev/null
+++ b/include/environment/ti/mmc.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for MMC/SD on TI boards.
+ */
+
+#ifndef __TI_MMC_H
+#define __TI_MMC_H
+
+#define DEFAULT_MMC_TI_ARGS \
+	"mmcdev=0\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"finduuid=part uuid mmc ${bootpart} uuid\0" \
+	"args_mmc=run finduuid;setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=PARTUUID=${uuid} rw " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"bootenvfile=uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}\0" \
+	"loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"envboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootscript; then " \
+				"run bootscript;" \
+			"else " \
+				"if run loadbootenv; then " \
+					"echo Loaded env from ${bootenvfile};" \
+					"run importbootenv;" \
+				"fi;" \
+				"if test -n $uenvcmd; then " \
+					"echo Running uenvcmd ...;" \
+					"run uenvcmd;" \
+				"fi;" \
+			"fi;" \
+		"fi;\0" \
+	"mmcloados=run args_mmc; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"devnum=${mmcdev}; " \
+		"setenv devtype mmc; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadimage; then " \
+				"if test ${boot_fit} -eq 1; then " \
+					"run loadfit; " \
+				"else " \
+					"run mmcloados;" \
+				"fi;" \
+			"fi;" \
+		"fi;\0"
+
+#endif /* __TI_MMC_H */
diff --git a/include/environment/ti/nand.h b/include/environment/ti/nand.h
new file mode 100644
index 0000000..f838cb3
--- /dev/null
+++ b/include/environment/ti/nand.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for NAND on TI boards.
+ */
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
+		"nand read ${loadaddr} NAND.kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#else
+#define NANDARGS ""
+#endif
+
diff --git a/include/environment/ti/spi.h b/include/environment/ti/spi.h
new file mode 100644
index 0000000..1681dc8
--- /dev/null
+++ b/include/environment/ti/spi.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for SPI on TI boards.
+ */
+
+#ifndef __TI_SPI_H
+#define __TI_SPI_H
+
+#define KEYSTONE_SPI0_MTD_PARTS "spi0.0:1m(u-boot-spl)ro,-(misc);\0"
+#define KEYSTONE_SPI1_MTD_PARTS "spi1.0:1m(u-boot-spl)ro,-(misc);\0"
+
+#endif
diff --git a/include/environment/ti/ufs.h b/include/environment/ti/ufs.h
new file mode 100644
index 0000000..d457e20
--- /dev/null
+++ b/include/environment/ti/ufs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Environment variable definitions for UFS on TI boards.
+ */
+
+#ifndef __TI_UFS_H
+#define __TI_UFS_H
+
+#define DEFAULT_UFS_TI_ARGS \
+	"scsirootfstype=ext4 rootwait\0" \
+	"ufs_finduuid=part uuid scsi ${bootpart} uuid\0" \
+	"args_ufs=setenv devtype scsi;setenv bootpart 1:1;" \
+	"run ufs_finduuid;setenv bootargs console = ${console} " \
+		"${optargs}" \
+		"root=PARTUUID=${uuid} rw " \
+		"rootfstype=${scsirootfstype};" \
+		"setenv devtype scsi;" \
+		"setenv bootpart 1:1\0" \
+	"init_ufs=ufs init; scsi scan; run args_ufs\0" \
+	"get_kern_ufs=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${name_kern}\0" \
+	"get_fdt_ufs=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"get_overlay_ufs=" \
+		"fdt address ${fdtaddr};" \
+		"fdt resize 0x100000;" \
+		"for overlay in $name_overlays;" \
+		"do;" \
+		"load scsi ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && " \
+		"fdt apply ${overlayaddr};" \
+		"done;\0"
+
+#endif
diff --git a/include/errno.h b/include/errno.h
new file mode 100644
index 0000000..ccb7869
--- /dev/null
+++ b/include/errno.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ */
+#ifndef _ERRNO_H
+#define _ERRNO_H
+
+#include <linux/errno.h>
+
+extern int errno;
+
+#define __set_errno(val) do { errno = val; } while (0)
+
+#ifdef CONFIG_ERRNO_STR
+const char *errno_str(int errno);
+#else
+static inline const char *errno_str(int errno)
+{
+	return 0;
+}
+#endif
+#endif /* _ERRNO_H */
diff --git a/include/ethsw.h b/include/ethsw.h
new file mode 100644
index 0000000..04e002d
--- /dev/null
+++ b/include/ethsw.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * Ethernet Switch commands
+ */
+
+#ifndef _CMD_ETHSW_H_
+#define _CMD_ETHSW_H_
+
+#define ETHSW_MAX_CMD_PARAMS 20
+#define ETHSW_CMD_PORT_ALL -1
+#define ETHSW_CMD_VLAN_ALL -1
+#define ETHSW_CMD_AGGR_GRP_NONE -1
+
+/* IDs used to track keywords in a command */
+enum ethsw_keyword_id {
+	ethsw_id_key_end = -1,
+	ethsw_id_help,
+	ethsw_id_show,
+	ethsw_id_port,
+	ethsw_id_enable,
+	ethsw_id_disable,
+	ethsw_id_statistics,
+	ethsw_id_clear,
+	ethsw_id_learning,
+	ethsw_id_auto,
+	ethsw_id_vlan,
+	ethsw_id_fdb,
+	ethsw_id_add,
+	ethsw_id_del,
+	ethsw_id_flush,
+	ethsw_id_pvid,
+	ethsw_id_untagged,
+	ethsw_id_all,
+	ethsw_id_none,
+	ethsw_id_egress,
+	ethsw_id_tag,
+	ethsw_id_classified,
+	ethsw_id_shared,
+	ethsw_id_private,
+	ethsw_id_ingress,
+	ethsw_id_filtering,
+	ethsw_id_aggr,
+	ethsw_id_count,	/* keep last */
+};
+
+enum ethsw_keyword_opt_id {
+	ethsw_id_port_no = ethsw_id_count + 1,
+	ethsw_id_vlan_no,
+	ethsw_id_pvid_no,
+	ethsw_id_add_del_no,
+	ethsw_id_add_del_mac,
+	ethsw_id_aggr_no,
+	ethsw_id_count_all,	/* keep last */
+};
+
+struct ethsw_command_def {
+	int cmd_to_keywords[ETHSW_MAX_CMD_PARAMS];
+	int cmd_keywords_nr;
+	int port;
+	int vid;
+	int aggr_grp;
+	uchar ethaddr[6];
+	int (*cmd_function)(struct ethsw_command_def *parsed_cmd);
+};
+
+/* Structure to be created and initialized by an Ethernet Switch driver */
+struct ethsw_command_func {
+	const char *ethsw_name;
+	int (*port_enable)(struct ethsw_command_def *parsed_cmd);
+	int (*port_disable)(struct ethsw_command_def *parsed_cmd);
+	int (*port_show)(struct ethsw_command_def *parsed_cmd);
+	int (*port_stats)(struct ethsw_command_def *parsed_cmd);
+	int (*port_stats_clear)(struct ethsw_command_def *parsed_cmd);
+	int (*port_learn)(struct ethsw_command_def *parsed_cmd);
+	int (*port_learn_show)(struct ethsw_command_def *parsed_cmd);
+	int (*fdb_show)(struct ethsw_command_def *parsed_cmd);
+	int (*fdb_flush)(struct ethsw_command_def *parsed_cmd);
+	int (*fdb_entry_add)(struct ethsw_command_def *parsed_cmd);
+	int (*fdb_entry_del)(struct ethsw_command_def *parsed_cmd);
+	int (*pvid_show)(struct ethsw_command_def *parsed_cmd);
+	int (*pvid_set)(struct ethsw_command_def *parsed_cmd);
+	int (*vlan_show)(struct ethsw_command_def *parsed_cmd);
+	int (*vlan_set)(struct ethsw_command_def *parsed_cmd);
+	int (*port_untag_show)(struct ethsw_command_def *parsed_cmd);
+	int (*port_untag_set)(struct ethsw_command_def *parsed_cmd);
+	int (*port_egr_vlan_show)(struct ethsw_command_def *parsed_cmd);
+	int (*port_egr_vlan_set)(struct ethsw_command_def *parsed_cmd);
+	int (*vlan_learn_show)(struct ethsw_command_def *parsed_cmd);
+	int (*vlan_learn_set)(struct ethsw_command_def *parsed_cmd);
+	int (*port_ingr_filt_show)(struct ethsw_command_def *parsed_cmd);
+	int (*port_ingr_filt_set)(struct ethsw_command_def *parsed_cmd);
+	int (*port_aggr_show)(struct ethsw_command_def *parsed_cmd);
+	int (*port_aggr_set)(struct ethsw_command_def *parsed_cmd);
+};
+
+int ethsw_define_functions(const struct ethsw_command_func *cmd_func);
+
+#endif /* _CMD_ETHSW_H_ */
diff --git a/include/exception.h b/include/exception.h
new file mode 100644
index 0000000..fc02490
--- /dev/null
+++ b/include/exception.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * The 'exception' command can be used for testing exception handling.
+ *
+ * Copyright (c) 2018, Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+static int do_exception(cmd_tbl_t *cmdtp, int flag, int argc,
+			char * const argv[])
+{
+	cmd_tbl_t *cp;
+
+	if (argc != 2)
+		return CMD_RET_USAGE;
+
+	/* drop sub-command parameter */
+	argc--;
+	argv++;
+
+	cp = find_cmd_tbl(argv[0], cmd_sub, ARRAY_SIZE(cmd_sub));
+
+	if (cp)
+		return cp->cmd(cmdtp, flag, argc, argv);
+
+	return CMD_RET_USAGE;
+}
+
+static int exception_complete(int argc, char * const argv[], char last_char,
+			      int maxv, char *cmdv[])
+{
+	int len = 0;
+	int i = 0;
+	cmd_tbl_t *cmdtp;
+
+	switch (argc) {
+	case 1:
+		break;
+	case 2:
+		len = strlen(argv[1]);
+		break;
+	default:
+		return 0;
+	}
+	for (cmdtp = cmd_sub; cmdtp != cmd_sub + ARRAY_SIZE(cmd_sub); cmdtp++) {
+		if (i >= maxv - 1)
+			return i;
+		if (!strncmp(argv[1], cmdtp->name, len))
+			cmdv[i++] = cmdtp->name;
+	}
+	cmdv[i] = NULL;
+	return i;
+}
+
+U_BOOT_CMD_COMPLETE(
+	exception, 2, 0, do_exception,
+	"Forces an exception to occur",
+	exception_help_text, exception_complete
+);
diff --git a/include/exports.h b/include/exports.h
new file mode 100644
index 0000000..147a00f
--- /dev/null
+++ b/include/exports.h
@@ -0,0 +1,65 @@
+#ifndef __EXPORTS_H__
+#define __EXPORTS_H__
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_PHY_AQUANTIA
+#include <env.h>
+#include <phy_interface.h>
+#endif
+
+struct spi_slave;
+
+/* These are declarations of exported functions available in C code */
+unsigned long get_version(void);
+int  getc(void);
+int  tstc(void);
+void putc(const char);
+void puts(const char*);
+int printf(const char* fmt, ...);
+void install_hdlr(int, interrupt_handler_t, void*);
+void free_hdlr(int);
+void *malloc(size_t);
+#if !CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE)
+void free(void*);
+#endif
+void __udelay(unsigned long);
+unsigned long get_timer(unsigned long);
+int vprintf(const char *, va_list);
+unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base);
+int strict_strtoul(const char *cp, unsigned int base, unsigned long *res);
+char *env_get(const char *name);
+int env_set(const char *varname, const char *value);
+long simple_strtol(const char *cp, char **endp, unsigned int base);
+int strcmp(const char *cs, const char *ct);
+unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
+unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
+#if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C)
+int i2c_write (uchar, uint, int , uchar* , int);
+int i2c_read (uchar, uint, int , uchar* , int);
+#endif
+#ifdef CONFIG_PHY_AQUANTIA
+struct mii_dev *mdio_get_current_dev(void);
+struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
+		phy_interface_t interface);
+struct phy_device *mdio_phydev_for_ethname(const char *ethname);
+int miiphy_set_current_dev(const char *devname);
+#endif
+
+void app_startup(char * const *);
+
+#endif    /* ifndef __ASSEMBLY__ */
+
+struct jt_funcs {
+#define EXPORT_FUNC(impl, res, func, ...) res(*func)(__VA_ARGS__);
+#include <_exports.h>
+#undef EXPORT_FUNC
+};
+
+
+#define XF_VERSION	9
+
+#if defined(CONFIG_X86)
+extern gd_t *global_data;
+#endif
+
+#endif	/* __EXPORTS_H__ */
diff --git a/include/ext4fs.h b/include/ext4fs.h
new file mode 100644
index 0000000..34585d4
--- /dev/null
+++ b/include/ext4fs.h
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Ext4 Extent data structures are taken from  original ext4 fs code
+ * as found in the linux kernel.
+ *
+ * Copyright (c) 2003-2006, Cluster File Systems, Inc, info@clusterfs.com
+ * Written by Alex Tomas <alex@clusterfs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __EXT4__
+#define __EXT4__
+#include <ext_common.h>
+
+#define EXT4_INDEX_FL		0x00001000 /* Inode uses hash tree index */
+#define EXT4_EXTENTS_FL		0x00080000 /* Inode uses extents */
+#define EXT4_EXT_MAGIC			0xf30a
+#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM	0x0010
+#define EXT4_FEATURE_RO_COMPAT_METADATA_CSUM 0x0400
+#define EXT4_FEATURE_INCOMPAT_EXTENTS	0x0040
+#define EXT4_FEATURE_INCOMPAT_64BIT	0x0080
+#define EXT4_INDIRECT_BLOCKS		12
+
+#define EXT4_BG_INODE_UNINIT		0x0001
+#define EXT4_BG_BLOCK_UNINIT		0x0002
+#define EXT4_BG_INODE_ZEROED		0x0004
+
+/*
+ * ext4_inode has i_block array (60 bytes total).
+ * The first 12 bytes store ext4_extent_header;
+ * the remainder stores an array of ext4_extent.
+ */
+
+/*
+ * This is the extent on-disk structure.
+ * It's used at the bottom of the tree.
+ */
+struct ext4_extent {
+	__le32	ee_block;	/* first logical block extent covers */
+	__le16	ee_len;		/* number of blocks covered by extent */
+	__le16	ee_start_hi;	/* high 16 bits of physical block */
+	__le32	ee_start_lo;	/* low 32 bits of physical block */
+};
+
+/*
+ * This is index on-disk structure.
+ * It's used at all the levels except the bottom.
+ */
+struct ext4_extent_idx {
+	__le32	ei_block;	/* index covers logical blocks from 'block' */
+	__le32	ei_leaf_lo;	/* pointer to the physical block of the next *
+				 * level. leaf or next index could be there */
+	__le16	ei_leaf_hi;	/* high 16 bits of physical block */
+	__u16	ei_unused;
+};
+
+/* Each block (leaves and indexes), even inode-stored has header. */
+struct ext4_extent_header {
+	__le16	eh_magic;	/* probably will support different formats */
+	__le16	eh_entries;	/* number of valid entries */
+	__le16	eh_max;		/* capacity of store in entries */
+	__le16	eh_depth;	/* has tree real underlying blocks? */
+	__le32	eh_generation;	/* generation of the tree */
+};
+
+struct ext_filesystem {
+	/* Total Sector of partition */
+	uint64_t total_sect;
+	/* Block size  of partition */
+	uint32_t blksz;
+	/* Inode size of partition */
+	uint32_t inodesz;
+	/* Sectors per Block */
+	uint32_t sect_perblk;
+	/* Group Descriptor size */
+	uint16_t gdsize;
+	/* Group Descriptor Block Number */
+	uint32_t gdtable_blkno;
+	/* Total block groups of partition */
+	uint32_t no_blkgrp;
+	/* No of blocks required for bgdtable */
+	uint32_t no_blk_pergdt;
+	/* Superblock */
+	struct ext2_sblock *sb;
+	/* Block group descritpor table */
+	char *gdtable;
+
+	/* Block Bitmap Related */
+	unsigned char **blk_bmaps;
+	long int curr_blkno;
+	uint16_t first_pass_bbmap;
+
+	/* Inode Bitmap Related */
+	unsigned char **inode_bmaps;
+	int curr_inode_no;
+	uint16_t first_pass_ibmap;
+
+	/* Journal Related */
+
+	/* Block Device Descriptor */
+	struct blk_desc *dev_desc;
+};
+
+struct ext_block_cache {
+	char *buf;
+	lbaint_t block;
+	int size;
+};
+
+extern struct ext2_data *ext4fs_root;
+extern struct ext2fs_node *ext4fs_file;
+
+#if defined(CONFIG_EXT4_WRITE)
+extern struct ext2_inode *g_parent_inode;
+extern int gd_index;
+extern int gindex;
+
+int ext4fs_init(void);
+void ext4fs_deinit(void);
+int ext4fs_filename_unlink(char *filename);
+int ext4fs_write(const char *fname, const char *buffer,
+				 unsigned long sizebytes, int type);
+int ext4_write_file(const char *filename, void *buf, loff_t offset, loff_t len,
+		    loff_t *actwrite);
+int ext4fs_create_link(const char *target, const char *fname);
+#endif
+
+struct ext_filesystem *get_fs(void);
+int ext4fs_open(const char *filename, loff_t *len);
+int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread);
+int ext4fs_mount(unsigned part_length);
+void ext4fs_close(void);
+void ext4fs_reinit_global(void);
+int ext4fs_ls(const char *dirname);
+int ext4fs_exists(const char *filename);
+int ext4fs_size(const char *filename, loff_t *size);
+void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
+int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf);
+void ext4fs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
+long int read_allocated_block(struct ext2_inode *inode, int fileblock,
+			      struct ext_block_cache *cache);
+int ext4fs_probe(struct blk_desc *fs_dev_desc,
+		 disk_partition_t *fs_partition);
+int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
+		   loff_t *actread);
+int ext4_read_superblock(char *buffer);
+int ext4fs_uuid(char *uuid_str);
+void ext_cache_init(struct ext_block_cache *cache);
+void ext_cache_fini(struct ext_block_cache *cache);
+int ext_cache_read(struct ext_block_cache *cache, lbaint_t block, int size);
+#endif
diff --git a/include/ext_common.h b/include/ext_common.h
new file mode 100644
index 0000000..1c10c50
--- /dev/null
+++ b/include/ext_common.h
@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Data structures and headers for ext4 support have been taken from
+ * ext2 ls load support in Uboot
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB  --  GRand Unified Bootloader
+ * Copyright (C) 2003, 2004  Free Software Foundation, Inc.
+ */
+
+#ifndef __EXT_COMMON__
+#define __EXT_COMMON__
+#include <command.h>
+#define SECTOR_SIZE		0x200
+#define LOG2_SECTOR_SIZE	9
+
+/* Magic value used to identify an ext2 filesystem.  */
+#define	EXT2_MAGIC			0xEF53
+/* Amount of indirect blocks in an inode.  */
+#define INDIRECT_BLOCKS			12
+/* Maximum lenght of a pathname.  */
+#define EXT2_PATH_MAX				4096
+/* Maximum nesting of symlinks, used to prevent a loop.  */
+#define	EXT2_MAX_SYMLINKCNT		8
+
+/* Filetype used in directory entry.  */
+#define	FILETYPE_UNKNOWN		0
+#define	FILETYPE_REG			1
+#define	FILETYPE_DIRECTORY		2
+#define	FILETYPE_SYMLINK		7
+
+/* Filetype information as used in inodes.  */
+#define FILETYPE_INO_MASK		0170000
+#define FILETYPE_INO_REG		0100000
+#define FILETYPE_INO_DIRECTORY		0040000
+#define FILETYPE_INO_SYMLINK		0120000
+#define EXT2_ROOT_INO			2 /* Root inode */
+
+/* The size of an ext2 block in bytes.  */
+#define EXT2_BLOCK_SIZE(data)	   (1 << LOG2_BLOCK_SIZE(data))
+
+/* Log2 size of ext2 block in bytes.  */
+#define LOG2_BLOCK_SIZE(data)	   (le32_to_cpu		   \
+				    (data->sblock.log2_block_size) \
+				    + EXT2_MIN_BLOCK_LOG_SIZE)
+
+#define EXT2_FT_DIR	2
+#define SUCCESS	1
+
+/* Macro-instructions used to manage several block sizes  */
+#define EXT2_MIN_BLOCK_LOG_SIZE	10 /* 1024 */
+#define EXT2_MAX_BLOCK_LOG_SIZE	16 /* 65536 */
+#define EXT2_MIN_BLOCK_SIZE		(1 << EXT2_MIN_BLOCK_LOG_SIZE)
+#define EXT2_MAX_BLOCK_SIZE		(1 << EXT2_MAX_BLOCK_LOG_SIZE)
+
+/* The ext2 superblock.  */
+struct ext2_sblock {
+	__le32 total_inodes;
+	__le32 total_blocks;
+	__le32 reserved_blocks;
+	__le32 free_blocks;
+	__le32 free_inodes;
+	__le32 first_data_block;
+	__le32 log2_block_size;
+	__le32 log2_fragment_size;
+	__le32 blocks_per_group;
+	__le32 fragments_per_group;
+	__le32 inodes_per_group;
+	__le32 mtime;
+	__le32 utime;
+	__le16 mnt_count;
+	__le16 max_mnt_count;
+	__le16 magic;
+	__le16 fs_state;
+	__le16 error_handling;
+	__le16 minor_revision_level;
+	__le32 lastcheck;
+	__le32 checkinterval;
+	__le32 creator_os;
+	__le32 revision_level;
+	__le16 uid_reserved;
+	__le16 gid_reserved;
+	__le32 first_inode;
+	__le16 inode_size;
+	__le16 block_group_number;
+	__le32 feature_compatibility;
+	__le32 feature_incompat;
+	__le32 feature_ro_compat;
+	__le32 unique_id[4];
+	char volume_name[16];
+	char last_mounted_on[64];
+	__le32 compression_info;
+	uint8_t prealloc_blocks;
+	uint8_t prealloc_dir_blocks;
+	__le16 reserved_gdt_blocks;
+	uint8_t journal_uuid[16];
+	__le32 journal_inode;
+	__le32 journal_dev;
+	__le32 last_orphan;
+	__le32 hash_seed[4];
+	uint8_t default_hash_version;
+	uint8_t journal_backup_type;
+	__le16 descriptor_size;
+	__le32 default_mount_options;
+	__le32 first_meta_block_group;
+	__le32 mkfs_time;
+	__le32 journal_blocks[17];
+	__le32 total_blocks_high;
+	__le32 reserved_blocks_high;
+	__le32 free_blocks_high;
+	__le16 min_extra_inode_size;
+	__le16 want_extra_inode_size;
+	__le32 flags;
+	__le16 raid_stride;
+	__le16 mmp_interval;
+	__le64 mmp_block;
+	__le32 raid_stripe_width;
+	uint8_t log2_groups_per_flex;
+	uint8_t checksum_type;
+};
+
+struct ext2_block_group {
+	__le32 block_id;	/* Blocks bitmap block */
+	__le32 inode_id;	/* Inodes bitmap block */
+	__le32 inode_table_id;	/* Inodes table block */
+	__le16 free_blocks;	/* Free blocks count */
+	__le16 free_inodes;	/* Free inodes count */
+	__le16 used_dir_cnt;	/* Directories count */
+	__le16 bg_flags;
+	__le32 bg_exclude_bitmap;
+	__le16 bg_block_id_csum;
+	__le16 bg_inode_id_csum;
+	__le16 bg_itable_unused; /* Unused inodes count */
+	__le16 bg_checksum;	/* crc16(s_uuid+group_num+group_desc)*/
+	/* following fields only exist if descriptor size is 64 */
+	__le32 block_id_high;
+	__le32 inode_id_high;
+	__le32 inode_table_id_high;
+	__le16 free_blocks_high;
+	__le16 free_inodes_high;
+	__le16 used_dir_cnt_high;
+	__le16 bg_itable_unused_high;
+	__le32 bg_exclude_bitmap_high;
+	__le16 bg_block_id_csum_high;
+	__le16 bg_inode_id_csum_high;
+	__le32 bg_reserved;
+};
+
+/* The ext2 inode. */
+struct ext2_inode {
+	__le16 mode;
+	__le16 uid;
+	__le32 size;
+	__le32 atime;
+	__le32 ctime;
+	__le32 mtime;
+	__le32 dtime;
+	__le16 gid;
+	__le16 nlinks;
+	__le32 blockcnt;	/* Blocks of either 512 or block_size bytes */
+	__le32 flags;
+	__le32 osd1;
+	union {
+		struct datablocks {
+			__le32 dir_blocks[INDIRECT_BLOCKS];
+			__le32 indir_block;
+			__le32 double_indir_block;
+			__le32 triple_indir_block;
+		} blocks;
+		char symlink[60];
+		char inline_data[60];
+	} b;
+	__le32 version;
+	__le32 acl;
+	__le32 size_high;	/* previously dir_acl, but never used */
+	__le32 fragment_addr;
+	__le32 osd2[3];
+};
+
+/* The header of an ext2 directory entry. */
+struct ext2_dirent {
+	__le32 inode;
+	__le16 direntlen;
+	__u8 namelen;
+	__u8 filetype;
+};
+
+struct ext2fs_node {
+	struct ext2_data *data;
+	struct ext2_inode inode;
+	int ino;
+	int inode_read;
+};
+
+/* Information about a "mounted" ext2 filesystem. */
+struct ext2_data {
+	struct ext2_sblock sblock;
+	struct ext2_inode *inode;
+	struct ext2fs_node diropen;
+};
+
+extern lbaint_t part_offset;
+
+int do_ext2ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ext2load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc,
+					char *const argv[]);
+int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc,
+				char *const argv[]);
+#endif
diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h
new file mode 100644
index 0000000..484bd36
--- /dev/null
+++ b/include/exynos_lcd.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * exynos_lcd.h - Exynos LCD Controller structures
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef _EXYNOS_LCD_H_
+#define _EXYNOS_LCD_H_
+
+enum {
+	FIMD_RGB_INTERFACE = 1,
+	FIMD_CPU_INTERFACE = 2,
+};
+
+enum exynos_fb_rgb_mode_t {
+	MODE_RGB_P = 0,
+	MODE_BGR_P = 1,
+	MODE_RGB_S = 2,
+	MODE_BGR_S = 3,
+};
+
+typedef struct vidinfo {
+	ushort vl_col;		/* Number of columns (i.e. 640) */
+	ushort vl_row;		/* Number of rows (i.e. 480) */
+	ushort vl_rot;		/* Rotation of Display (0, 1, 2, 3) */
+	ushort vl_width;	/* Width of display area in millimeters */
+	ushort vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char vl_freq;		/* Frequency */
+	u_char vl_clkp;		/* Clock polarity */
+	u_char vl_oep;		/* Output Enable polarity */
+	u_char vl_hsp;		/* Horizontal Sync polarity */
+	u_char vl_vsp;		/* Vertical Sync polarity */
+	u_char vl_dp;		/* Data polarity */
+	u_char vl_bpix;		/* Bits per pixel */
+
+	/* Horizontal control register. Timing from data sheet */
+	u_char vl_hspw;		/* Horz sync pulse width */
+	u_char vl_hfpd;		/* Wait before of line */
+	u_char vl_hbpd;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u_char	vl_vspw;	/* Vertical sync pulse width */
+	u_char	vl_vfpd;	/* Wait before of frame */
+	u_char	vl_vbpd;	/* Wait end of frame */
+	u_char  vl_cmd_allow_len; /* Wait end of frame */
+
+	unsigned int win_id;
+	unsigned int init_delay;
+	unsigned int power_on_delay;
+	unsigned int reset_delay;
+	unsigned int interface_mode;
+	unsigned int mipi_enabled;
+	unsigned int dp_enabled;
+	unsigned int cs_setup;
+	unsigned int wr_setup;
+	unsigned int wr_act;
+	unsigned int wr_hold;
+	unsigned int logo_on;
+	unsigned int logo_width;
+	unsigned int logo_height;
+	int logo_x_offset;
+	int logo_y_offset;
+	unsigned long logo_addr;
+	unsigned int rgb_mode;
+	unsigned int resolution;
+
+	/* parent clock name(MPLL, EPLL or VPLL) */
+	unsigned int pclk_name;
+	/* ratio value for source clock from parent clock. */
+	unsigned int sclk_div;
+
+	unsigned int dual_lcd_enabled;
+	struct exynos_fb *reg;
+	struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
+} vidinfo_t;
+
+#endif
diff --git a/include/faraday/ftahbc020s.h b/include/faraday/ftahbc020s.h
new file mode 100644
index 0000000..e628156
--- /dev/null
+++ b/include/faraday/ftahbc020s.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
+#ifndef __FTAHBC020S_H
+#define __FTAHBC202S_H
+
+/* Registers Offsets */
+
+/*
+ * AHB Slave BSR, offset: n * 4, n=0~31
+ */
+#ifndef __ASSEMBLY__
+struct ftahbc02s {
+	unsigned int	s_bsr[32];	/* 0x00-0x7c - Slave n Base/Size Reg */
+	unsigned int	pcr;		/* 0x80	- Priority Ctrl Reg */
+	unsigned int	tcrg;		/* 0x84	- Transfer Ctrl Reg */
+	unsigned int	cr;		/* 0x88	- Ctrl Reg */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
+ */
+#define FTAHBC020S_SLAVE_BSR_BASE(x)	(((x) & 0xfff) << 20)
+#define FTAHBC020S_SLAVE_BSR_SIZE(x)	(((x) & 0xf) << 16)
+/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */
+#define FTAHBC020S_BSR_SIZE(x)		(ffs(x) - 1)	/* size of Addr Space */
+
+/*
+ * FTAHBC020S_PCR - Priority Control Register
+ */
+#define FTAHBC020S_PCR_PLEVEL_(x)	(1 << (x))	/* x: 1-15 */
+
+/*
+ * FTAHBC020S_CR - Interrupt Control Register
+ */
+#define FTAHBC020S_CR_INTSTS	(1 << 24)
+#define FTAHBC020S_CR_RESP(x)	(((x) & 0x3) << 20)
+#define FTAHBC020S_CR_INTSMASK	(1 << 16)
+#define FTAHBC020S_CR_REMAP	(1 << 0)
+
+#endif	/* __FTAHBC020S_H */
diff --git a/include/faraday/ftpci100.h b/include/faraday/ftpci100.h
new file mode 100644
index 0000000..b4a43f8
--- /dev/null
+++ b/include/faraday/ftpci100.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
+ *
+ * Copyright (C) 2010 Andes Technology Corporation
+ * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#ifndef __FTPCI100_H
+#define __FTPCI100_H
+
+/* AHB Control Registers */
+struct ftpci100_ahbc {
+	unsigned int iosize;		/* 0x00 - I/O Space Size Signal */
+	unsigned int prot;		/* 0x04 - AHB Protection */
+	unsigned int rsved[8];		/* 0x08-0x24 - Reserved */
+	unsigned int conf;		/* 0x28 - PCI Configuration */
+	unsigned int data;		/* 0x2c - PCI Configuration DATA */
+};
+
+/*
+ * FTPCI100_IOSIZE_REG's constant definitions
+ */
+#define FTPCI100_BASE_IO_SIZE(x)	(ffs(x) - 1)	/* 1M - 2048M */
+
+/*
+ * PCI Configuration Register
+ */
+#define PCI_INT_MASK			0x4c
+#define PCI_MEM_BASE_SIZE1		0x50
+#define PCI_MEM_BASE_SIZE2		0x54
+#define PCI_MEM_BASE_SIZE3		0x58
+
+/*
+ * PCI_INT_MASK's bit definitions
+ */
+#define PCI_INTA_ENABLE			(1 << 22)
+#define PCI_INTB_ENABLE			(1 << 23)
+#define PCI_INTC_ENABLE			(1 << 24)
+#define PCI_INTD_ENABLE			(1 << 25)
+
+/*
+ * PCI_MEM_BASE_SIZE1's constant definitions
+ */
+#define FTPCI100_BASE_ADR_SIZE(x)	((ffs(x) - 1) << 16)	/* 1M - 2048M */
+
+#define FTPCI100_MAX_FUNCTIONS		20
+#define PCI_IRQ_LINES			4
+
+#define MAX_BUS_NUM			256
+#define MAX_DEV_NUM			32
+#define MAX_FUN_NUM			8
+
+#define PCI_MAX_BAR_PER_FUNC		6
+
+/*
+ * PCI_MEM_SIZE
+ */
+#define FTPCI100_MEM_SIZE(x)		(ffs(x) << 24)
+
+/* This definition is used by pci_ftpci_init() */
+#define FTPCI100_BRIDGE_VENDORID		0x159b
+#define FTPCI100_BRIDGE_DEVICEID		0x4321
+
+void pci_ftpci_init(void);
+
+struct pcibar {
+	unsigned int size;
+	unsigned int addr;
+};
+
+struct pci_config {
+	unsigned int bus;
+	unsigned int dev;				/* device */
+	unsigned int func;
+	unsigned int pin;
+	unsigned short v_id;				/* vendor id */
+	unsigned short d_id;				/* device id */
+	struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1];
+};
+
+#endif
diff --git a/include/faraday/ftpmu010.h b/include/faraday/ftpmu010.h
new file mode 100644
index 0000000..8fc81f9
--- /dev/null
+++ b/include/faraday/ftpmu010.h
@@ -0,0 +1,234 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ */
+
+/*
+ * Power Management Unit
+ */
+#ifndef __FTPMU010_H
+#define __FTPMU010_H
+
+#ifndef __ASSEMBLY__
+struct ftpmu010 {
+	unsigned int	IDNMBR0;	/* 0x00 */
+	unsigned int	reserved0;	/* 0x04 */
+	unsigned int	OSCC;		/* 0x08 */
+	unsigned int	PMODE;		/* 0x0C */
+	unsigned int	PMCR;		/* 0x10 */
+	unsigned int	PED;		/* 0x14 */
+	unsigned int	PEDSR;		/* 0x18 */
+	unsigned int	reserved1;	/* 0x1C */
+	unsigned int	PMSR;		/* 0x20 */
+	unsigned int	PGSR;		/* 0x24 */
+	unsigned int	MFPSR;		/* 0x28 */
+	unsigned int	MISC;		/* 0x2C */
+	unsigned int	PDLLCR0;	/* 0x30 */
+	unsigned int	PDLLCR1;	/* 0x34 */
+	unsigned int	AHBMCLKOFF;	/* 0x38 */
+	unsigned int	APBMCLKOFF;	/* 0x3C */
+	unsigned int	DCSRCR0;	/* 0x40 */
+	unsigned int	DCSRCR1;	/* 0x44 */
+	unsigned int	DCSRCR2;	/* 0x48 */
+	unsigned int	SDRAMHTC;	/* 0x4C */
+	unsigned int	PSPR0;		/* 0x50 */
+	unsigned int	PSPR1;		/* 0x54 */
+	unsigned int	PSPR2;		/* 0x58 */
+	unsigned int	PSPR3;		/* 0x5C */
+	unsigned int	PSPR4;		/* 0x60 */
+	unsigned int	PSPR5;		/* 0x64 */
+	unsigned int	PSPR6;		/* 0x68 */
+	unsigned int	PSPR7;		/* 0x6C */
+	unsigned int	PSPR8;		/* 0x70 */
+	unsigned int	PSPR9;		/* 0x74 */
+	unsigned int	PSPR10;		/* 0x78 */
+	unsigned int	PSPR11;		/* 0x7C */
+	unsigned int	PSPR12;		/* 0x80 */
+	unsigned int	PSPR13;		/* 0x84 */
+	unsigned int	PSPR14;		/* 0x88 */
+	unsigned int	PSPR15;		/* 0x8C */
+	unsigned int	AHBDMA_RACCS;	/* 0x90 */
+	unsigned int	reserved2;	/* 0x94 */
+	unsigned int	reserved3;	/* 0x98 */
+	unsigned int	JSS;		/* 0x9C */
+	unsigned int	CFC_RACC;	/* 0xA0 */
+	unsigned int	SSP1_RACC;	/* 0xA4 */
+	unsigned int	UART1TX_RACC;	/* 0xA8 */
+	unsigned int	UART1RX_RACC;	/* 0xAC */
+	unsigned int	UART2TX_RACC;	/* 0xB0 */
+	unsigned int	UART2RX_RACC;	/* 0xB4 */
+	unsigned int	SDC_RACC;	/* 0xB8 */
+	unsigned int	I2SAC97_RACC;	/* 0xBC */
+	unsigned int	IRDATX_RACC;	/* 0xC0 */
+	unsigned int	reserved4;	/* 0xC4 */
+	unsigned int	USBD_RACC;	/* 0xC8 */
+	unsigned int	IRDARX_RACC;	/* 0xCC */
+	unsigned int	IRDA_RACC;	/* 0xD0 */
+	unsigned int	ED0_RACC;	/* 0xD4 */
+	unsigned int	ED1_RACC;	/* 0xD8 */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * ID Number 0 Register
+ */
+#define FTPMU010_ID_A320A	0x03200000
+#define FTPMU010_ID_A320C	0x03200010
+#define FTPMU010_ID_A320D	0x03200030
+
+/*
+ * OSC Control Register
+ */
+#define FTPMU010_OSCC_OSCH_TRI		(1 << 11)
+#define FTPMU010_OSCC_OSCH_STABLE	(1 << 9)
+#define FTPMU010_OSCC_OSCH_OFF		(1 << 8)
+
+#define FTPMU010_OSCC_OSCL_TRI		(1 << 3)
+#define FTPMU010_OSCC_OSCL_RTCLSEL	(1 << 2)
+#define FTPMU010_OSCC_OSCL_STABLE	(1 << 1)
+#define FTPMU010_OSCC_OSCL_OFF		(1 << 0)
+
+/*
+ * Power Mode Register
+ */
+#define FTPMU010_PMODE_DIVAHBCLK_MASK	(0x7 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_2	(0x0 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_3	(0x1 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_4	(0x2 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_6	(0x3 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_8	(0x4 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK(pmode)	(((pmode) >> 4) & 0x7)
+#define FTPMU010_PMODE_FCS		(1 << 2)
+#define FTPMU010_PMODE_TURBO		(1 << 1)
+#define FTPMU010_PMODE_SLEEP		(1 << 0)
+
+/*
+ * Power Manager Status Register
+ */
+#define FTPMU010_PMSR_SMR	(1 << 10)
+
+#define FTPMU010_PMSR_RDH	(1 << 2)
+#define FTPMU010_PMSR_PH	(1 << 1)
+#define FTPMU010_PMSR_CKEHLOW	(1 << 0)
+
+/*
+ * Multi-Function Port Setting Register
+ */
+#define FTPMU010_MFPSR_DEBUGSEL		(1 << 17)
+#define FTPMU010_MFPSR_DMA0PINSEL	(1 << 16)
+#define FTPMU010_MFPSR_DMA1PINSEL	(1 << 15)
+#define FTPMU010_MFPSR_MODEMPINSEL	(1 << 14)
+#define FTPMU010_MFPSR_AC97CLKOUTSEL	(1 << 13)
+#define FTPMU010_MFPSR_PWM1PINSEL	(1 << 11)
+#define FTPMU010_MFPSR_PWM0PINSEL	(1 << 10)
+#define FTPMU010_MFPSR_IRDACLKSEL	(1 << 9)
+#define FTPMU010_MFPSR_UARTCLKSEL	(1 << 8)
+#define FTPMU010_MFPSR_SSPCLKSEL	(1 << 6)
+#define FTPMU010_MFPSR_I2SCLKSEL	(1 << 5)
+#define FTPMU010_MFPSR_AC97CLKSEL	(1 << 4)
+#define FTPMU010_MFPSR_AC97PINSEL	(1 << 3)
+#define FTPMU010_MFPSR_TRIAHBDIS	(1 << 1)
+#define FTPMU010_MFPSR_TRIAHBDBG	(1 << 0)
+
+/*
+ * PLL/DLL Control Register 0
+ * Note:
+ *  1. FTPMU010_PDLLCR0_HCLKOUTDIS:
+ *	Datasheet indicated it starts at bit #21 which was wrong.
+ *  2. FTPMU010_PDLLCR0_DLLFRAG:
+ * 	Datasheet indicated it has 2 bit which was wrong.
+ */
+#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0)	(((cr0) & 0xf) << 20)
+#define FTPMU010_PDLLCR0_DLLFRAG(cr0)		(1 << 19)
+#define FTPMU010_PDLLCR0_DLLSTSEL		(1 << 18)
+#define FTPMU010_PDLLCR0_DLLSTABLE		(1 << 17)
+#define FTPMU010_PDLLCR0_DLLDIS			(1 << 16)
+#define FTPMU010_PDLLCR0_PLL1FRANG(cr0)		(((cr0) & 0x3) << 12)
+#define FTPMU010_PDLLCR0_PLL1NS(cr0)		(((cr0) & 0x1ff) << 3)
+#define FTPMU010_PDLLCR0_PLL1STSEL		(1 << 2)
+#define FTPMU010_PDLLCR0_PLL1STABLE		(1 << 1)
+#define FTPMU010_PDLLCR0_PLL1DIS		(1 << 0)
+
+/*
+ * SDRAM Signal Hold Time Control Register
+ */
+#define FTPMU010_SDRAMHTC_RCLK_DLY(x)		(((x) & 0xf) << 28)
+#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x)	(((x) & 0xf) << 24)
+#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x)	(((x) & 0xf) << 20)
+#define FTPMU010_SDRAMHTC_EBICTRL_DCSR		(1 << 18)
+#define FTPMU010_SDRAMHTC_EBIDATA_DCSR		(1 << 17)
+#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR		(1 << 16)
+#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR		(1 << 15)
+#define FTPMU010_SDRAMHTC_CKE_DCSR		(1 << 14)
+#define FTPMU010_SDRAMHTC_DQM_DCSR		(1 << 13)
+#define FTPMU010_SDRAMHTC_SDCLK_DCSR		(1 << 12)
+
+#ifndef __ASSEMBLY__
+void ftpmu010_32768osc_enable(void);
+void ftpmu010_dlldis_disable(void);
+void ftpmu010_mfpsr_diselect_dev(unsigned int dev);
+void ftpmu010_mfpsr_select_dev(unsigned int dev);
+void ftpmu010_sdram_clk_disable(unsigned int cr0);
+void ftpmu010_sdramhtc_set(unsigned int val);
+#endif
+
+#ifdef __ASSEMBLY__
+#define FTPMU010_IDNMBR0	0x00
+#define FTPMU010_reserved0	0x04
+#define FTPMU010_OSCC		0x08
+#define FTPMU010_PMODE		0x0C
+#define FTPMU010_PMCR		0x10
+#define FTPMU010_PED		0x14
+#define FTPMU010_PEDSR		0x18
+#define FTPMU010_reserved1	0x1C
+#define FTPMU010_PMSR		0x20
+#define FTPMU010_PGSR		0x24
+#define FTPMU010_MFPSR		0x28
+#define FTPMU010_MISC		0x2C
+#define FTPMU010_PDLLCR0	0x30
+#define FTPMU010_PDLLCR1	0x34
+#define FTPMU010_AHBMCLKOFF	0x38
+#define FTPMU010_APBMCLKOFF	0x3C
+#define FTPMU010_DCSRCR0	0x40
+#define FTPMU010_DCSRCR1	0x44
+#define FTPMU010_DCSRCR2	0x48
+#define FTPMU010_SDRAMHTC	0x4C
+#define FTPMU010_PSPR0		0x50
+#define FTPMU010_PSPR1		0x54
+#define FTPMU010_PSPR2		0x58
+#define FTPMU010_PSPR3		0x5C
+#define FTPMU010_PSPR4		0x60
+#define FTPMU010_PSPR5		0x64
+#define FTPMU010_PSPR6		0x68
+#define FTPMU010_PSPR7		0x6C
+#define FTPMU010_PSPR8		0x70
+#define FTPMU010_PSPR9		0x74
+#define FTPMU010_PSPR10		0x78
+#define FTPMU010_PSPR11		0x7C
+#define FTPMU010_PSPR12		0x80
+#define FTPMU010_PSPR13		0x84
+#define FTPMU010_PSPR14		0x88
+#define FTPMU010_PSPR15		0x8C
+#define FTPMU010_AHBDMA_RACCS	0x90
+#define FTPMU010_reserved2	0x94
+#define FTPMU010_reserved3	0x98
+#define FTPMU010_JSS		0x9C
+#define FTPMU010_CFC_RACC	0xA0
+#define FTPMU010_SSP1_RACC	0xA4
+#define FTPMU010_UART1TX_RACC	0xA8
+#define FTPMU010_UART1RX_RACC	0xAC
+#define FTPMU010_UART2TX_RACC	0xB0
+#define FTPMU010_UART2RX_RACC	0xB4
+#define FTPMU010_SDC_RACC	0xB8
+#define FTPMU010_I2SAC97_RACC	0xBC
+#define FTPMU010_IRDATX_RACC	0xC0
+#define FTPMU010_reserved4	0xC4
+#define FTPMU010_USBD_RACC	0xC8
+#define FTPMU010_IRDARX_RACC	0xCC
+#define FTPMU010_IRDA_RACC	0xD0
+#define FTPMU010_ED0_RACC	0xD4
+#define FTPMU010_ED1_RACC	0xD8
+#endif /* __ASSEMBLY__ */
+
+#endif	/* __FTPMU010_H */
diff --git a/include/faraday/ftsdc010.h b/include/faraday/ftsdc010.h
new file mode 100644
index 0000000..d3a359a
--- /dev/null
+++ b/include/faraday/ftsdc010.h
@@ -0,0 +1,245 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Faraday FTSDC010 Secure Digital Memory Card Host Controller
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ */
+
+#ifndef __FTSDC010_H
+#define __FTSDC010_H
+
+#ifndef __ASSEMBLY__
+
+/* sd controller register */
+struct ftsdc010_mmc {
+	unsigned int	cmd;		/* 0x00 - command reg		*/
+	unsigned int	argu;		/* 0x04 - argument reg		*/
+	unsigned int	rsp0;		/* 0x08 - response reg0		*/
+	unsigned int	rsp1;		/* 0x0c - response reg1		*/
+	unsigned int	rsp2;		/* 0x10 - response reg2		*/
+	unsigned int	rsp3;		/* 0x14 - response reg3		*/
+	unsigned int	rsp_cmd;	/* 0x18 - responded cmd reg	*/
+	unsigned int	dcr;		/* 0x1c - data control reg	*/
+	unsigned int	dtr;		/* 0x20 - data timer reg	*/
+	unsigned int	dlr;		/* 0x24 - data length reg	*/
+	unsigned int	status;		/* 0x28 - status reg		*/
+	unsigned int	clr;		/* 0x2c - clear reg		*/
+	unsigned int	int_mask;	/* 0x30 - intrrupt mask reg	*/
+	unsigned int	pcr;		/* 0x34 - power control reg	*/
+	unsigned int	ccr;		/* 0x38 - clock contorl reg	*/
+	unsigned int	bwr;		/* 0x3c - bus width reg		*/
+	unsigned int	dwr;		/* 0x40 - data window reg	*/
+#ifndef CONFIG_FTSDC010_SDIO
+	unsigned int	feature;	/* 0x44 - feature reg		*/
+	unsigned int	rev;		/* 0x48 - revision reg		*/
+#else
+	unsigned int	mmc_intr_time;	/* 0x44 - MMC int resp time reg	*/
+	unsigned int	gpo;		/* 0x48 - gerenal purpose output */
+	unsigned int	reserved[8];	/* 0x50 - 0x68 reserved		*/
+	unsigned int	sdio_ctrl1;	/* 0x6c - SDIO control reg 1	*/
+	unsigned int	sdio_ctrl2;	/* 0x70 - SDIO control reg 2	*/
+	unsigned int	sdio_status;	/* 0x74 - SDIO status regi	*/
+	unsigned int	reserved1[9];	/* 0x78 - 0x98	reserved	*/
+	unsigned int	feature;	/* 0x9c - feature reg		*/
+	unsigned int	rev;		/* 0xa0 - revision reg		*/
+#endif /* CONFIG_FTSDC010_SDIO */
+};
+
+struct mmc_host {
+	struct ftsdc010_mmc *reg;
+	unsigned int version;		/* SDHCI spec. version */
+	unsigned int clock;		/* Current clock (MHz) */
+	unsigned int fifo_len;		/* bytes */
+	unsigned int last_opcode;	/* Last OP Code */
+	unsigned int card_type;		/* Card type */
+};
+
+/* functions */
+int ftsdc010_mmc_init(int dev_index);
+
+#endif	/* __ASSEMBLY__ */
+
+/* global defines */
+#define FTSDC010_CMD_RETRY			0x100000
+#define FTSDC010_PIO_RETRY			100	/* pio retry times */
+#define FTSDC010_DELAY_UNIT			100	/* 100 us */
+
+/* define from Linux kernel - include/linux/mmc/card.h */
+#define MMC_TYPE_SDIO				2	/* SDIO card */
+
+/* define for mmc layer */
+#define MMC_DATA_BOTH_DIR			(MMC_DATA_WRITE | MMC_DATA_READ)
+
+/* this part is strange */
+#define FTSDC010_SDIO_CTRL1_REG			0x0000006C
+#define FTSDC010_SDIO_CTRL2_REG			0x0000006C
+#define FTSDC010_SDIO_STATUS_REG		0x00000070
+
+/* 0x00 - command register */
+#define FTSDC010_CMD_IDX(x)			(((x) & 0x3f) << 0)
+#define FTSDC010_CMD_NEED_RSP			(1 << 6)
+#define FTSDC010_CMD_LONG_RSP			(1 << 7)
+#define FTSDC010_CMD_APP_CMD			(1 << 8)
+#define FTSDC010_CMD_CMD_EN			(1 << 9)
+#define FTSDC010_CMD_SDC_RST			(1 << 10)
+#define FTSDC010_CMD_MMC_INT_STOP		(1 << 11)
+
+/* 0x18 - responded command register */
+#define FTSDC010_RSP_CMD_IDX(x)			(((x) >> 0) & 0x3f)
+#define FTSDC010_RSP_CMD_APP			(1 << 6)
+
+/* 0x1c - data control register */
+#define FTSDC010_DCR_BLK_SIZE(x)		(((x) & 0xf) << 0)
+#define FTSDC010_DCR_DATA_WRITE			(1 << 4)
+#define FTSDC010_DCR_DMA_EN			(1 << 5)
+#define FTSDC010_DCR_DATA_EN			(1 << 6)
+#ifdef CONFIG_FTSDC010_SDIO
+#define FTSDC010_DCR_FIFOTH			(1 << 7)
+#define FTSDC010_DCR_DMA_TYPE(x)		(((x) & 0x3) << 8)
+#define FTSDC010_DCR_FIFO_RST			(1 << 10)
+#endif /* CONFIG_FTSDC010_SDIO */
+
+#define FTSDC010_DCR_DMA_TYPE_1			0x0	/* Single r/w	*/
+#define FTSDC010_DCR_DMA_TYPE_4			0x1	/* Burst 4 r/w	*/
+#define FTSDC010_DCR_DMA_TYPE_8			0x2	/* Burst 8 r/w	*/
+
+#define FTSDC010_DCR_BLK_BYTES(x)		(ffs(x) - 1)	/* 1B - 2048B */
+
+/* CPRM related define */
+#define FTSDC010_CPRM_DATA_CHANGE_ENDIAN_EN	0x000008
+#define FTSDC010_CPRM_DATA_SWAP_HL_EN		0x000010
+
+/* 0x28 - status register */
+#define FTSDC010_STATUS_RSP_CRC_FAIL		(1 << 0)
+#define FTSDC010_STATUS_DATA_CRC_FAIL		(1 << 1)
+#define FTSDC010_STATUS_RSP_TIMEOUT		(1 << 2)
+#define FTSDC010_STATUS_DATA_TIMEOUT		(1 << 3)
+#define FTSDC010_STATUS_RSP_CRC_OK		(1 << 4)
+#define FTSDC010_STATUS_DATA_CRC_OK		(1 << 5)
+#define FTSDC010_STATUS_CMD_SEND		(1 << 6)
+#define FTSDC010_STATUS_DATA_END		(1 << 7)
+#define FTSDC010_STATUS_FIFO_URUN		(1 << 8)
+#define FTSDC010_STATUS_FIFO_ORUN		(1 << 9)
+#define FTSDC010_STATUS_CARD_CHANGE		(1 << 10)
+#define FTSDC010_STATUS_CARD_DETECT		(1 << 11)
+#define FTSDC010_STATUS_WRITE_PROT		(1 << 12)
+#ifdef CONFIG_FTSDC010_SDIO
+#define FTSDC010_STATUS_CP_READY		(1 << 13) /* reserved ? */
+#define FTSDC010_STATUS_CP_BUF_READY		(1 << 14) /* reserved ? */
+#define FTSDC010_STATUS_PLAIN_TEXT_READY	(1 << 15) /* reserved ? */
+#define FTSDC010_STATUS_SDIO_IRPT		(1 << 16) /* SDIO card intr */
+#define FTSDC010_STATUS_DATA0_STATUS		(1 << 17)
+#endif /* CONFIG_FTSDC010_SDIO */
+#define FTSDC010_STATUS_RSP_ERROR	\
+	(FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_RSP_TIMEOUT)
+#define FTSDC010_STATUS_RSP_MASK	\
+	(FTSDC010_STATUS_RSP_ERROR | FTSDC010_STATUS_RSP_CRC_OK)
+#define FTSDC010_STATUS_DATA_ERROR	\
+	(FTSDC010_STATUS_DATA_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT)
+#define FTSDC010_STATUS_DATA_MASK	\
+	(FTSDC010_STATUS_DATA_ERROR | FTSDC010_STATUS_DATA_CRC_OK \
+	| FTSDC010_STATUS_DATA_END)
+
+/* 0x2c - clear register */
+#define FTSDC010_CLR_RSP_CRC_FAIL		(1 << 0)
+#define FTSDC010_CLR_DATA_CRC_FAIL		(1 << 1)
+#define FTSDC010_CLR_RSP_TIMEOUT		(1 << 2)
+#define FTSDC010_CLR_DATA_TIMEOUT		(1 << 3)
+#define FTSDC010_CLR_RSP_CRC_OK			(1 << 4)
+#define FTSDC010_CLR_DATA_CRC_OK		(1 << 5)
+#define FTSDC010_CLR_CMD_SEND			(1 << 6)
+#define FTSDC010_CLR_DATA_END			(1 << 7)
+#define FTSDC010_STATUS_FIFO_URUN		(1 << 8) /* reserved ? */
+#define FTSDC010_STATUS_FIFO_ORUN		(1 << 9) /* reserved ? */
+#define FTSDC010_CLR_CARD_CHANGE		(1 << 10)
+#ifdef CONFIG_FTSDC010_SDIO
+#define FTSDC010_CLR_SDIO_IRPT			(1 << 16)
+#endif /* CONFIG_FTSDC010_SDIO */
+
+/* 0x30 - interrupt mask register */
+#define FTSDC010_INT_MASK_RSP_CRC_FAIL		(1 << 0)
+#define FTSDC010_INT_MASK_DATA_CRC_FAIL		(1 << 1)
+#define FTSDC010_INT_MASK_RSP_TIMEOUT		(1 << 2)
+#define FTSDC010_INT_MASK_DATA_TIMEOUT		(1 << 3)
+#define FTSDC010_INT_MASK_RSP_CRC_OK		(1 << 4)
+#define FTSDC010_INT_MASK_DATA_CRC_OK		(1 << 5)
+#define FTSDC010_INT_MASK_CMD_SEND		(1 << 6)
+#define FTSDC010_INT_MASK_DATA_END		(1 << 7)
+#define FTSDC010_INT_MASK_FIFO_URUN		(1 << 8)
+#define FTSDC010_INT_MASK_FIFO_ORUN		(1 << 9)
+#define FTSDC010_INT_MASK_CARD_CHANGE		(1 << 10)
+#ifdef CONFIG_FTSDC010_SDIO
+#define FTSDC010_INT_MASK_CP_READY		(1 << 13)
+#define FTSDC010_INT_MASK_CP_BUF_READY		(1 << 14)
+#define FTSDC010_INT_MASK_PLAIN_TEXT_READY	(1 << 15)
+#define FTSDC010_INT_MASK_SDIO_IRPT		(1 << 16)
+#define FTSDC010_STATUS_DATA0_STATUS		(1 << 17)
+#endif /* CONFIG_FTSDC010_SDIO */
+
+/* ? */
+#define FTSDC010_CARD_INSERT			0x0
+#define FTSDC010_CARD_REMOVE			FTSDC010_STATUS_REG_CARD_DETECT
+
+/* 0x34 - power control register */
+#define FTSDC010_PCR_POWER(x)			(((x) & 0xf) << 0)
+#define FTSDC010_PCR_POWER_ON			(1 << 4)
+
+/* 0x38 - clock control register */
+#define FTSDC010_CCR_CLK_DIV(x)			(((x) & 0x7f) << 0)
+#define FTSDC010_CCR_CLK_SD			(1 << 7) /* 0: MMC, 1: SD */
+#define FTSDC010_CCR_CLK_DIS			(1 << 8)
+#define FTSDC010_CCR_CLK_HISPD			(1 << 9) /* high speed */
+
+/* card type */
+#define FTSDC010_CARD_TYPE_SD			FTSDC010_CLOCK_REG_CARD_TYPE
+#define FTSDC010_CARD_TYPE_MMC			0x0
+
+/* 0x3c - bus width register */
+#define FTSDC010_BWR_MODE_1BIT      (1 << 0) /* 1 bit mode enabled */
+#define FTSDC010_BWR_MODE_8BIT      (1 << 1) /* 8 bit mode enabled */
+#define FTSDC010_BWR_MODE_4BIT      (1 << 2) /* 4 bit mode enabled */
+#define FTSDC010_BWR_MODE_MASK      (7 << 0)
+#define FTSDC010_BWR_MODE_SHIFT     (0)
+#define FTSDC010_BWR_CAPS_1BIT      (0 << 3) /* 1 bits mode supported */
+#define FTSDC010_BWR_CAPS_4BIT      (1 << 3) /* 1,4 bits mode supported */
+#define FTSDC010_BWR_CAPS_8BIT      (2 << 3) /* 1,4,8 bits mode supported */
+#define FTSDC010_BWR_CAPS_MASK      (3 << 3)
+#define FTSDC010_BWR_CAPS_SHIFT     (3)
+#define FTSDC010_BWR_CARD_DETECT    (1 << 5)
+
+/* 0x44 or 0x9c - feature register */
+#define FTSDC010_FEATURE_FIFO_DEPTH(x)		(((x) >> 0) & 0xff)
+#define FTSDC010_FEATURE_CPRM_FUNCTION		(1 << 8)
+
+#define FTSDC010_FIFO_DEPTH_4			0x04
+#define FTSDC010_FIFO_DEPTH_8			0x08
+#define FTSDC010_FIFO_DEPTH_16			0x10
+
+/* 0x48 or 0xa0 - revision register */
+#define FTSDC010_REV_REVISION(x)		(((x) & 0xff) >> 0)
+#define FTSDC010_REV_MINOR(x)			(((x) & 0xff00) >> 8)
+#define FTSDC010_REV_MAJOR(x)			(((x) & 0xffff0000) >> 16)
+
+#ifdef CONFIG_FTSDC010_SDIO
+/* 0x44 - general purpose output */
+#define FTSDC010_GPO_PORT(x)			(((x) & 0xf) << 0)
+
+/* 0x6c - sdio control register 1 */
+#define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x)	(((x) & 0xfff) << 0)
+#define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE	(1 << 12)
+#define FTSDC010_SDIO_CTRL1_READ_WAIT_EN	(1 << 13)
+#define FTSDC010_SDIO_CTRL1_SDIO_ENABLE		(1 << 14)
+#define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x)	(((x) & 0x1ff) << 15)
+
+/* 0x70 - sdio control register 2 */
+#define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT	(1 << 0)
+#define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT	(1 << 1)
+
+/* 0x74 - sdio status register */
+#define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x)	(((x) >> 0) & 0x1ffff)
+#define FTSDC010_SDIO_STATUS_FIFO_REMAIN_NO(x)	(((x) >> 17) & 0xef)
+
+#endif /* CONFIG_FTSDC010_SDIO */
+
+#endif /* __FTSDC010_H */
diff --git a/include/faraday/ftsdmc020.h b/include/faraday/ftsdmc020.h
new file mode 100644
index 0000000..d74da16
--- /dev/null
+++ b/include/faraday/ftsdmc020.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ */
+
+/*
+ * SDRAM Controller
+ */
+#ifndef __FTSDMC020_H
+#define __FTSDMC020_H
+
+#define FTSDMC020_OFFSET_TP0		0x00
+#define FTSDMC020_OFFSET_TP1		0x04
+#define FTSDMC020_OFFSET_CR		0x08
+#define FTSDMC020_OFFSET_BANK0_BSR	0x0C
+#define FTSDMC020_OFFSET_BANK1_BSR	0x10
+#define FTSDMC020_OFFSET_BANK2_BSR	0x14
+#define FTSDMC020_OFFSET_BANK3_BSR	0x18
+#define FTSDMC020_OFFSET_BANK4_BSR	0x1C
+#define FTSDMC020_OFFSET_BANK5_BSR	0x20
+#define FTSDMC020_OFFSET_BANK6_BSR	0x24
+#define FTSDMC020_OFFSET_BANK7_BSR	0x28
+#define FTSDMC020_OFFSET_ACR		0x34
+
+/*
+ * Timing Parametet 0 Register
+ */
+#define FTSDMC020_TP0_TCL(x)	((x) & 0x3)
+#define FTSDMC020_TP0_TWR(x)	(((x) & 0x3) << 4)
+#define FTSDMC020_TP0_TRF(x)	(((x) & 0xf) << 8)
+#define FTSDMC020_TP0_TRCD(x)	(((x) & 0x7) << 12)
+#define FTSDMC020_TP0_TRP(x)	(((x) & 0xf) << 16)
+#define FTSDMC020_TP0_TRAS(x)	(((x) & 0xf) << 20)
+
+/*
+ * Timing Parametet 1 Register
+ */
+#define FTSDMC020_TP1_REF_INTV(x)	((x) & 0xffff)
+#define FTSDMC020_TP1_INI_REFT(x)	(((x) & 0xf) << 16)
+#define FTSDMC020_TP1_INI_PREC(x)	(((x) & 0xf) << 20)
+
+/*
+ * Configuration Register
+ */
+#define FTSDMC020_CR_SREF	(1 << 0)
+#define FTSDMC020_CR_PWDN	(1 << 1)
+#define FTSDMC020_CR_ISMR	(1 << 2)
+#define FTSDMC020_CR_IREF	(1 << 3)
+#define FTSDMC020_CR_IPREC	(1 << 4)
+#define FTSDMC020_CR_REFTYPE	(1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC020_BANK_ENABLE		(1 << 28)
+
+#define FTSDMC020_BANK_BASE(addr)	(((addr) >> 20) << 16)
+
+#define FTSDMC020_BANK_DDW_X4		(0 << 12)
+#define FTSDMC020_BANK_DDW_X8		(1 << 12)
+#define FTSDMC020_BANK_DDW_X16		(2 << 12)
+#define FTSDMC020_BANK_DDW_X32		(3 << 12)
+
+#define FTSDMC020_BANK_DSZ_16M		(0 << 8)
+#define FTSDMC020_BANK_DSZ_64M		(1 << 8)
+#define FTSDMC020_BANK_DSZ_128M		(2 << 8)
+#define FTSDMC020_BANK_DSZ_256M		(3 << 8)
+
+#define FTSDMC020_BANK_MBW_8		(0 << 4)
+#define FTSDMC020_BANK_MBW_16		(1 << 4)
+#define FTSDMC020_BANK_MBW_32		(2 << 4)
+
+#define FTSDMC020_BANK_SIZE_1M		0x0
+#define FTSDMC020_BANK_SIZE_2M		0x1
+#define FTSDMC020_BANK_SIZE_4M		0x2
+#define FTSDMC020_BANK_SIZE_8M		0x3
+#define FTSDMC020_BANK_SIZE_16M		0x4
+#define FTSDMC020_BANK_SIZE_32M		0x5
+#define FTSDMC020_BANK_SIZE_64M		0x6
+#define FTSDMC020_BANK_SIZE_128M	0x7
+#define FTSDMC020_BANK_SIZE_256M	0x8
+
+/*
+ * Arbiter Control Register
+ */
+#define FTSDMC020_ACR_TOC(x)	((x) & 0x1f)
+#define FTSDMC020_ACR_TOE	(1 << 8)
+
+#endif	/* __FTSDMC020_H */
diff --git a/include/faraday/ftsdmc021.h b/include/faraday/ftsdmc021.h
new file mode 100644
index 0000000..3c979ce
--- /dev/null
+++ b/include/faraday/ftsdmc021.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <macpaul@andestech.com>
+ */
+
+/*
+ * FTSDMC021 - SDRAM Controller
+ */
+#ifndef __FTSDMC021_H
+#define __FTSDMC021_H
+
+#ifndef __ASSEMBLY__
+struct ftsdmc021 {
+	unsigned int	tp1;		/* 0x00 - SDRAM Timing Parameter 1 */
+	unsigned int	tp2;		/* 0x04 - SDRAM Timing Parameter 2 */
+	unsigned int	cr1;		/* 0x08 - SDRAM Configuration Reg 1 */
+	unsigned int	cr2;		/* 0x0c - SDRAM Configuration Reg 2 */
+	unsigned int	bank0_bsr;	/* 0x10 - Ext. Bank Base/Size Reg 0 */
+	unsigned int	bank1_bsr;	/* 0x14 - Ext. Bank Base/Size Reg 1 */
+	unsigned int	bank2_bsr;	/* 0x18 - Ext. Bank Base/Size Reg 2 */
+	unsigned int	bank3_bsr;	/* 0x1c - Ext. Bank Base/Size Reg 3 */
+	unsigned int	bank4_bsr;	/* 0x20 - Ext. Bank Base/Size Reg 4 */
+	unsigned int	bank5_bsr;	/* 0x24 - Ext. Bank Base/Size Reg 5 */
+	unsigned int	bank6_bsr;	/* 0x28 - Ext. Bank Base/Size Reg 6 */
+	unsigned int	bank7_bsr;	/* 0x2c - Ext. Bank Base/Size Reg 7 */
+	unsigned int	ragr;		/* 0x30 - Read Arbitration Group Reg */
+	unsigned int	frr;		/* 0x34 - Flush Request Register */
+	unsigned int	ebisr;		/* 0x38 - EBI Support Register	*/
+	unsigned int	rsved[25];	/* 0x3c-0x9c - Reserved		*/
+	unsigned int	crr;		/* 0x100 - Controller Revision Reg */
+	unsigned int	cfr;		/* 0x104 - Controller Feature Reg */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Timing Parameter 1 Register
+ */
+#define FTSDMC021_TP1_TCL(x)	((x) & 0x3)		/* CAS Latency */
+#define FTSDMC021_TP1_TWR(x)	(((x) & 0x3) << 4)	/* W-Recovery Time */
+#define FTSDMC021_TP1_TRF(x)	(((x) & 0xf) << 8)	/* Auto-Refresh Cycle */
+#define FTSDMC021_TP1_TRCD(x)	(((x) & 0x7) << 12)	/* RAS-to-CAS Delay */
+#define FTSDMC021_TP1_TRP(x)	(((x) & 0xf) << 16)	/* Precharge Cycle */
+#define FTSDMC021_TP1_TRAS(x)	(((x) & 0xf) << 20)
+
+/*
+ * Timing Parameter 2 Register
+ */
+#define FTSDMC021_TP2_REF_INTV(x)	((x) & 0xffff)	/* Refresh interval */
+/* b(16:19) - Initial Refresh Times */
+#define FTSDMC021_TP2_INI_REFT(x)	(((x) & 0xf) << 16)
+/* b(20:23) - Initial Pre-Charge Times */
+#define FTSDMC021_TP2_INI_PREC(x)	(((x) & 0xf) << 20)
+
+/*
+ * SDRAM Configuration Register 1
+ */
+#define FTSDMC021_CR1_BNKSIZE(x)	((x) & 0xf)		/* Bank Size  */
+#define FTSDMC021_CR1_MBW(x)		(((x) & 0x3) << 4)	/* Bus Width  */
+#define FTSDMC021_CR1_DSZ(x)		(((x) & 0x7) << 8)	/* SDRAM Size */
+#define FTSDMC021_CR1_DDW(x)		(((x) & 0x3) << 12)	/* Data Width */
+/* b(16) MA2T: Double Memory Address Cycle Enable */
+#define FTSDMC021_CR1_MA2T(x)		(1 << 16)
+/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
+#define FTSDMC021_BANK_SIZE(x)		(ffs(x) - 1)
+
+/*
+ * Configuration Register 2
+ */
+#define FTSDMC021_CR2_SREF	(1 << 0)	/* Self-Refresh Mode */
+#define FTSDMC021_CR2_PWDN	(1 << 1)	/* Power Down Operation Mode */
+#define FTSDMC021_CR2_ISMR	(1 << 2)	/* Start Set-Mode-Register */
+#define FTSDMC021_CR2_IREF	(1 << 3)	/* Init Refresh Start Flag */
+#define FTSDMC021_CR2_IPREC	(1 << 4)	/* Init Pre-Charge Start Flag */
+#define FTSDMC021_CR2_REFTYPE	(1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC021_BANK_ENABLE		(1 << 12)
+
+/* 12-bit base address of external bank.
+ * Default value is 0x800.
+ * The 12-bit equals to the haddr[31:20] of AHB address bus. */
+#define FTSDMC021_BANK_BASE(x)		((x) & 0xfff)
+
+/*
+ * Read Arbitration Grant Window Register
+ */
+#define FTSDMC021_RAGR_CH1GW(x)		(((x) & 0xff) << 0)
+#define FTSDMC021_RAGR_CH2GW(x)		(((x) & 0xff) << 4)
+#define FTSDMC021_RAGR_CH3GW(x)		(((x) & 0xff) << 8)
+#define FTSDMC021_RAGR_CH4GW(x)		(((x) & 0xff) << 12)
+#define FTSDMC021_RAGR_CH5GW(x)		(((x) & 0xff) << 16)
+#define FTSDMC021_RAGR_CH6GW(x)		(((x) & 0xff) << 20)
+#define FTSDMC021_RAGR_CH7GW(x)		(((x) & 0xff) << 24)
+#define FTSDMC021_RAGR_CH8GW(x)		(((x) & 0xff) << 28)
+
+/*
+ * Flush Request Register
+ */
+#define FTSDMC021_FRR_FLUSHCHN(x)	(((x) & 0x7) << 0)
+#define FTSDMC021_FRR_FLUSHCMPLT	(1 << 3)	/* Flush Req Flag */
+
+/*
+ * External Bus Interface Support Register (EBISR)
+ */
+#define FTSDMC021_EBISR_MR(x)		((x) & 0xfff)	/* Far-end mode	*/
+#define FTSDMC021_EBISR_PRSMR		(1 << 12)	/* Pre-SMR	*/
+#define FTSDMC021_EBISR_POPREC		(1 << 13)
+#define FTSDMC021_EBISR_POSMR		(1 << 14)	/* Post-SMR	*/
+
+/*
+ * Controller Revision Register (CRR, Read Only)
+ */
+#define FTSDMC021_CRR_REV_VER		(((x) >> 0) & 0xff)
+#define FTSDMC021_CRR_MINOR_VER		(((x) >> 8) & 0xff)
+#define FTSDMC021_CRR_MAJOR_VER		(((x) >> 16) & 0xff)
+
+/*
+ * Controller Feature Register (CFR, Read Only)
+ */
+#define FTSDMC021_CFR_EBNK		(((x) >> 0) & 0xf)
+#define FTSDMC021_CFR_CHN		(((x) >> 8) & 0xf)
+#define FTSDMC021_CFR_EBI		(((x) >> 16) & 0x1)
+#define FTSDMC021_CFR_CH1_FDEPTH	(((x) >> 24) & 0x1)
+#define FTSDMC021_CFR_CH2_FDEPTH	(((x) >> 25) & 0x1)
+#define FTSDMC021_CFR_CH3_FDEPTH	(((x) >> 26) & 0x1)
+#define FTSDMC021_CFR_CH4_FDEPTH	(((x) >> 27) & 0x1)
+#define FTSDMC021_CFR_CH5_FDEPTH	(((x) >> 28) & 0x1)
+#define FTSDMC021_CFR_CH6_FDEPTH	(((x) >> 29) & 0x1)
+#define FTSDMC021_CFR_CH7_FDEPTH	(((x) >> 30) & 0x1)
+#define FTSDMC021_CFR_CH8_FDEPTH	(((x) >> 31) & 0x1)
+
+#endif	/* __FTSDMC021_H */
diff --git a/include/faraday/ftsmc020.h b/include/faraday/ftsmc020.h
new file mode 100644
index 0000000..f902a79
--- /dev/null
+++ b/include/faraday/ftsmc020.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ */
+
+/*
+ * Static Memory Controller
+ */
+#ifndef __FTSMC020_H
+#define __FTSMC020_H
+
+#ifndef __ASSEMBLY__
+
+struct ftsmc020_bank {
+	unsigned int    cr;
+	unsigned int    tpr;
+};
+
+struct ftsmc020 {
+	struct ftsmc020_bank bank[4];	/* 0x00 - 0x1c */
+	unsigned int	pad[8];		/* 0x20 - 0x3c */
+	unsigned int	ssr;		/* 0x40 */
+};
+
+void ftsmc020_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Memory Bank Configuration Register
+ */
+#define FTSMC020_BANK_ENABLE	(1 << 28)
+#define FTSMC020_BANK_BASE(x)	((x) & 0x0fff1000)
+
+#define FTSMC020_BANK_WPROT	(1 << 11)
+
+#define FTSMC020_BANK_TYPE1	(1 << 10)
+#define FTSMC020_BANK_TYPE2	(1 << 9)
+#define FTSMC020_BANK_TYPE3	(1 << 8)
+
+#define FTSMC020_BANK_SIZE_32K	(0xb << 4)
+#define FTSMC020_BANK_SIZE_64K	(0xc << 4)
+#define FTSMC020_BANK_SIZE_128K	(0xd << 4)
+#define FTSMC020_BANK_SIZE_256K	(0xe << 4)
+#define FTSMC020_BANK_SIZE_512K	(0xf << 4)
+#define FTSMC020_BANK_SIZE_1M	(0x0 << 4)
+#define FTSMC020_BANK_SIZE_2M	(0x1 << 4)
+#define FTSMC020_BANK_SIZE_4M	(0x2 << 4)
+#define FTSMC020_BANK_SIZE_8M	(0x3 << 4)
+#define FTSMC020_BANK_SIZE_16M	(0x4 << 4)
+#define FTSMC020_BANK_SIZE_32M	(0x5 << 4)
+#define FTSMC020_BANK_SIZE_64M	(0x6 << 4)
+
+#define FTSMC020_BANK_MBW_8	(0x0 << 0)
+#define FTSMC020_BANK_MBW_16	(0x1 << 0)
+#define FTSMC020_BANK_MBW_32	(0x2 << 0)
+
+/*
+ * Memory Bank Timing Parameter Register
+ */
+#define FTSMC020_TPR_ETRNA(x)	(((x) & 0xf) << 28)
+#define FTSMC020_TPR_EATI(x)	(((x) & 0xf) << 24)
+#define FTSMC020_TPR_RBE	(1 << 20)
+#define FTSMC020_TPR_AST(x)	(((x) & 0x3) << 18)
+#define FTSMC020_TPR_CTW(x)	(((x) & 0x3) << 16)
+#define FTSMC020_TPR_ATI(x)	(((x) & 0xf) << 12)
+#define FTSMC020_TPR_AT2(x)	(((x) & 0x3) << 8)
+#define FTSMC020_TPR_WTC(x)	(((x) & 0x3) << 6)
+#define FTSMC020_TPR_AHT(x)	(((x) & 0x3) << 4)
+#define FTSMC020_TPR_TRNA(x)	(((x) & 0xf) << 0)
+
+#endif	/* __FTSMC020_H */
diff --git a/include/faraday/fttmr010.h b/include/faraday/fttmr010.h
new file mode 100644
index 0000000..ec1c989
--- /dev/null
+++ b/include/faraday/fttmr010.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ */
+
+/*
+ * Timer
+ */
+#ifndef __FTTMR010_H
+#define __FTTMR010_H
+
+struct fttmr010 {
+	unsigned int	timer1_counter;		/* 0x00 */
+	unsigned int	timer1_load;		/* 0x04 */
+	unsigned int	timer1_match1;		/* 0x08 */
+	unsigned int	timer1_match2;		/* 0x0c */
+	unsigned int	timer2_counter;		/* 0x10 */
+	unsigned int	timer2_load;		/* 0x14 */
+	unsigned int	timer2_match1;		/* 0x18 */
+	unsigned int	timer2_match2;		/* 0x1c */
+	unsigned int	timer3_counter;		/* 0x20 */
+	unsigned int	timer3_load;		/* 0x24 */
+	unsigned int	timer3_match1;		/* 0x28 */
+	unsigned int	timer3_match2;		/* 0x2c */
+	unsigned int	cr;			/* 0x30 */
+	unsigned int	interrupt_state;	/* 0x34 */
+	unsigned int	interrupt_mask;		/* 0x38 */
+};
+
+/*
+ * Timer Control Register
+ */
+#define FTTMR010_TM3_UPDOWN	(1 << 11)
+#define FTTMR010_TM2_UPDOWN	(1 << 10)
+#define FTTMR010_TM1_UPDOWN	(1 << 9)
+#define FTTMR010_TM3_OFENABLE	(1 << 8)
+#define FTTMR010_TM3_CLOCK	(1 << 7)
+#define FTTMR010_TM3_ENABLE	(1 << 6)
+#define FTTMR010_TM2_OFENABLE	(1 << 5)
+#define FTTMR010_TM2_CLOCK	(1 << 4)
+#define FTTMR010_TM2_ENABLE	(1 << 3)
+#define FTTMR010_TM1_OFENABLE	(1 << 2)
+#define FTTMR010_TM1_CLOCK	(1 << 1)
+#define FTTMR010_TM1_ENABLE	(1 << 0)
+
+/*
+ * Timer Interrupt State & Mask Registers
+ */
+#define FTTMR010_TM3_OVERFLOW	(1 << 8)
+#define FTTMR010_TM3_MATCH2	(1 << 7)
+#define FTTMR010_TM3_MATCH1	(1 << 6)
+#define FTTMR010_TM2_OVERFLOW	(1 << 5)
+#define FTTMR010_TM2_MATCH2	(1 << 4)
+#define FTTMR010_TM2_MATCH1	(1 << 3)
+#define FTTMR010_TM1_OVERFLOW	(1 << 2)
+#define FTTMR010_TM1_MATCH2	(1 << 1)
+#define FTTMR010_TM1_MATCH1	(1 << 0)
+
+#endif	/* __FTTMR010_H */
diff --git a/include/faraday/ftwdt010_wdt.h b/include/faraday/ftwdt010_wdt.h
new file mode 100644
index 0000000..20bf6d3
--- /dev/null
+++ b/include/faraday/ftwdt010_wdt.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Watchdog driver for the FTWDT010 Watch Dog Driver
+ *
+ * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com)
+ * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu>
+ * Based on SoftDog driver by Alan Cox <alan@redhat.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * 27/11/2004 Initial release, Faraday.
+ * 12/01/2011 Port to u-boot, Macpaul Lin.
+ */
+
+#ifndef __FTWDT010_H
+#define __FTWDT010_H
+
+struct ftwdt010_wdt {
+	unsigned int	wdcounter;	/* Counter Reg		- 0x00 */
+	unsigned int	wdload;		/* Counter Auto Reload Reg - 0x04 */
+	unsigned int	wdrestart;	/* Counter Restart Reg	- 0x08 */
+	unsigned int	wdcr;		/* Control Reg		- 0x0c */
+	unsigned int	wdstatus;	/* Status Reg		- 0x10 */
+	unsigned int	wdclear;	/* Timer Clear		- 0x14 */
+	unsigned int	wdintrlen;	/* Interrupt Length	- 0x18 */
+};
+
+/*
+ * WDLOAD - Counter Auto Reload Register
+ *   The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default.
+ *   Which means in a 66MHz system, the period of Watch Dog timer reset is
+ *   one second.
+ */
+#define FTWDT010_WDLOAD(x)		((x) & 0xffffffff)
+
+/*
+ * WDRESTART - Watch Dog Timer Counter Restart Register
+ *   If writing 0x5AB9 to WDRESTART register, Watch Dog timer will
+ *   automatically reload WDLOAD to WDCOUNTER and restart counting.
+ */
+#define FTWDT010_WDRESTART_MAGIC	0x5AB9
+
+/* WDCR - Watch Dog Timer Control Register */
+#define FTWDT010_WDCR_ENABLE		(1 << 0)
+#define FTWDT010_WDCR_RST		(1 << 1)
+#define FTWDT010_WDCR_INTR		(1 << 2)
+/* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */
+#define FTWDT010_WDCR_EXT		(1 << 3)
+/* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK.
+ *  The clock source PCLK cannot be gated when system sleeps, even if
+ *  WDCLOCK bit is turned on.
+ *
+ *  Faraday's Watch Dog timer can be driven by an external clock. The
+ *  programmer just needs to write one to WdCR[WdClock] bit.
+ *
+ *  Note: There is a limitation between EXTCLK and PCLK:
+ *  EXTCLK cycle time / PCLK cycle time > 2.
+ *  If the system does not need an external clock,
+ *  just keep WdCR[WdClock] bit in its default value.
+ */
+#define FTWDT010_WDCR_CLOCK		(1 << 4)
+
+/*
+ * WDSTATUS - Watch Dog Timer Status Register
+ *   This bit is set when the counter reaches Zero
+ */
+#define FTWDT010_WDSTATUS(x)		((x) & 0x1)
+
+/*
+ * WDCLEAR - Watch Dog Timer Clear Register
+ *   Writing one to this register will clear WDSTATUS.
+ */
+#define FTWDT010_WDCLEAR		(1 << 0)
+
+/*
+ * WDINTRLEN - Watch Dog Timer Interrupt Length
+ *   This register controls the duration length of wd_rst, wd_intr and wd_ext.
+ *   The default value is 0xFF.
+ */
+#define FTWDT010_WDINTRLEN(x)		((x) & 0xff)
+
+/*
+ * Variable timeout should be set in ms.
+ * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms.
+ * WDLOAD = timeout * TIMEOUT_FACTOR.
+ */
+#define FTWDT010_TIMEOUT_FACTOR		(CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */
+
+void ftwdt010_wdt_reset(void);
+void ftwdt010_wdt_disable(void);
+
+#endif /* __FTWDT010_H */
diff --git a/include/fastboot-internal.h b/include/fastboot-internal.h
new file mode 100644
index 0000000..bf2f2b3
--- /dev/null
+++ b/include/fastboot-internal.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _FASTBOOT_INTERNAL_H_
+#define _FASTBOOT_INTERNAL_H_
+
+/**
+ * fastboot_buf_addr - base address of the fastboot download buffer
+ */
+extern void *fastboot_buf_addr;
+
+/**
+ * fastboot_buf_size - size of the fastboot download buffer
+ */
+extern u32 fastboot_buf_size;
+
+/**
+ * fastboot_progress_callback - callback executed during long operations
+ */
+extern void (*fastboot_progress_callback)(const char *msg);
+
+/**
+ * fastboot_getvar() - Writes variable indicated by cmd_parameter to response.
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ *
+ * Look up cmd_parameter first as an environment variable of the form
+ * fastboot.<cmd_parameter>, if that exists return use its value to set
+ * response.
+ *
+ * Otherwise lookup the name of variable and execute the appropriate
+ * function to return the requested value.
+ */
+void fastboot_getvar(char *cmd_parameter, char *response);
+
+#endif
diff --git a/include/fastboot.h b/include/fastboot.h
new file mode 100644
index 0000000..1933b1d
--- /dev/null
+++ b/include/fastboot.h
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008 - 2009
+ * Windriver, <www.windriver.com>
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * Copyright 2011 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+ *
+ * Copyright 2014 Linaro, Ltd.
+ * Rob Herring <robh@kernel.org>
+ */
+#ifndef _FASTBOOT_H_
+#define _FASTBOOT_H_
+
+#define FASTBOOT_VERSION	"0.4"
+
+/* The 64 defined bytes plus \0 */
+#define FASTBOOT_COMMAND_LEN	(64 + 1)
+#define FASTBOOT_RESPONSE_LEN	(64 + 1)
+
+/**
+ * All known commands to fastboot
+ */
+enum {
+	FASTBOOT_COMMAND_GETVAR = 0,
+	FASTBOOT_COMMAND_DOWNLOAD,
+#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
+	FASTBOOT_COMMAND_FLASH,
+	FASTBOOT_COMMAND_ERASE,
+#endif
+	FASTBOOT_COMMAND_BOOT,
+	FASTBOOT_COMMAND_CONTINUE,
+	FASTBOOT_COMMAND_REBOOT,
+	FASTBOOT_COMMAND_REBOOT_BOOTLOADER,
+	FASTBOOT_COMMAND_SET_ACTIVE,
+#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT)
+	FASTBOOT_COMMAND_OEM_FORMAT,
+#endif
+
+	FASTBOOT_COMMAND_COUNT
+};
+
+/**
+ * fastboot_response() - Writes a response of the form "$tag$reason".
+ *
+ * @tag: The first part of the response
+ * @response: Pointer to fastboot response buffer
+ * @format: printf style format string
+ */
+void fastboot_response(const char *tag, char *response,
+		       const char *format, ...)
+	__attribute__ ((format (__printf__, 3, 4)));
+
+/**
+ * fastboot_fail() - Write a FAIL response of the form "FAIL$reason".
+ *
+ * @reason: Pointer to returned reason string
+ * @response: Pointer to fastboot response buffer
+ */
+void fastboot_fail(const char *reason, char *response);
+
+/**
+ * fastboot_okay() - Write an OKAY response of the form "OKAY$reason".
+ *
+ * @reason: Pointer to returned reason string, or NULL to send a bare "OKAY"
+ * @response: Pointer to fastboot response buffer
+ */
+void fastboot_okay(const char *reason, char *response);
+
+/**
+ * fastboot_set_reboot_flag() - Set flag to indicate reboot-bootloader
+ *
+ * Set flag which indicates that we should reboot into the bootloader
+ * following the reboot that fastboot executes after this function.
+ *
+ * This function should be overridden in your board file with one
+ * which sets whatever flag your board specific Android bootloader flow
+ * requires in order to re-enter the bootloader.
+ */
+int fastboot_set_reboot_flag(void);
+
+/**
+ * fastboot_set_progress_callback() - set progress callback
+ *
+ * @progress: Pointer to progress callback
+ *
+ * Set a callback which is invoked periodically during long running operations
+ * (flash and erase). This can be used (for example) by the UDP transport to
+ * send INFO responses to keep the client alive whilst those commands are
+ * executing.
+ */
+void fastboot_set_progress_callback(void (*progress)(const char *msg));
+
+/*
+ * fastboot_init() - initialise new fastboot protocol session
+ *
+ * @buf_addr: Pointer to download buffer, or NULL for default
+ * @buf_size: Size of download buffer, or zero for default
+ */
+void fastboot_init(void *buf_addr, u32 buf_size);
+
+/**
+ * fastboot_boot() - Execute fastboot boot command
+ *
+ * If ${fastboot_bootcmd} is set, run that command to execute the boot
+ * process, if that returns, then exit the fastboot server and return
+ * control to the caller.
+ *
+ * Otherwise execute "bootm <fastboot_buf_addr>", if that fails, reset
+ * the board.
+ */
+void fastboot_boot(void);
+
+/**
+ * fastboot_handle_command() - Handle fastboot command
+ *
+ * @cmd_string: Pointer to command string
+ * @response: Pointer to fastboot response buffer
+ *
+ * Return: Executed command, or -1 if not recognized
+ */
+int fastboot_handle_command(char *cmd_string, char *response);
+
+/**
+ * fastboot_data_remaining() - return bytes remaining in current transfer
+ *
+ * Return: Number of bytes left in the current download
+ */
+u32 fastboot_data_remaining(void);
+
+/**
+ * fastboot_data_download() - Copy image data to fastboot_buf_addr.
+ *
+ * @fastboot_data: Pointer to received fastboot data
+ * @fastboot_data_len: Length of received fastboot data
+ * @response: Pointer to fastboot response buffer
+ *
+ * Copies image data from fastboot_data to fastboot_buf_addr. Writes to
+ * response. fastboot_bytes_received is updated to indicate the number
+ * of bytes that have been transferred.
+ */
+void fastboot_data_download(const void *fastboot_data,
+			    unsigned int fastboot_data_len, char *response);
+
+/**
+ * fastboot_data_complete() - Mark current transfer complete
+ *
+ * @response: Pointer to fastboot response buffer
+ *
+ * Set image_size and ${filesize} to the total size of the downloaded image.
+ */
+void fastboot_data_complete(char *response);
+
+#endif /* _FASTBOOT_H_ */
diff --git a/include/fat.h b/include/fat.h
new file mode 100644
index 0000000..bc139f8
--- /dev/null
+++ b/include/fat.h
@@ -0,0 +1,209 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg
+ *
+ * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6
+ * 2003-03-10 - kharris@nexus-tech.net - ported to u-boot
+ */
+
+#ifndef _FAT_H_
+#define _FAT_H_
+
+#include <asm/byteorder.h>
+#include <fs.h>
+
+/* Maximum Long File Name length supported here is 128 UTF-16 code units */
+#define VFAT_MAXLEN_BYTES	256 /* Maximum LFN buffer in bytes */
+#define VFAT_MAXSEQ		9   /* Up to 9 of 13 2-byte UTF-16 entries */
+#define PREFETCH_BLOCKS		2
+
+#define MAX_CLUSTSIZE	CONFIG_FS_FAT_MAX_CLUSTSIZE
+
+#define DIRENTSPERBLOCK	(mydata->sect_size / sizeof(dir_entry))
+#define DIRENTSPERCLUST	((mydata->clust_size * mydata->sect_size) / \
+			 sizeof(dir_entry))
+
+#define FATBUFBLOCKS	6
+#define FATBUFSIZE	(mydata->sect_size * FATBUFBLOCKS)
+#define FAT12BUFSIZE	((FATBUFSIZE*2)/3)
+#define FAT16BUFSIZE	(FATBUFSIZE/2)
+#define FAT32BUFSIZE	(FATBUFSIZE/4)
+
+/* Maximum number of entry for long file name according to spec */
+#define MAX_LFN_SLOT	20
+
+/* Filesystem identifiers */
+#define FAT12_SIGN	"FAT12   "
+#define FAT16_SIGN	"FAT16   "
+#define FAT32_SIGN	"FAT32   "
+#define SIGNLEN		8
+
+/* File attributes */
+#define ATTR_RO	1
+#define ATTR_HIDDEN	2
+#define ATTR_SYS	4
+#define ATTR_VOLUME	8
+#define ATTR_DIR	16
+#define ATTR_ARCH	32
+
+#define ATTR_VFAT	(ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME)
+
+#define DELETED_FLAG	((char)0xe5) /* Marks deleted files when in name[0] */
+#define aRING		0x05	     /* Used as special character in name[0] */
+
+/*
+ * Indicates that the entry is the last long entry in a set of long
+ * dir entries
+ */
+#define LAST_LONG_ENTRY_MASK	0x40
+
+#define ISDIRDELIM(c)	((c) == '/' || (c) == '\\')
+
+#define FSTYPE_NONE	(-1)
+
+#if defined(__linux__) && defined(__KERNEL__)
+#define FAT2CPU16	le16_to_cpu
+#define FAT2CPU32	le32_to_cpu
+#else
+#if __LITTLE_ENDIAN
+#define FAT2CPU16(x)	(x)
+#define FAT2CPU32(x)	(x)
+#else
+#define FAT2CPU16(x)	((((x) & 0x00ff) << 8) | (((x) & 0xff00) >> 8))
+#define FAT2CPU32(x)	((((x) & 0x000000ff) << 24)  |	\
+			 (((x) & 0x0000ff00) << 8)  |	\
+			 (((x) & 0x00ff0000) >> 8)  |	\
+			 (((x) & 0xff000000) >> 24))
+#endif
+#endif
+
+#define START(dent)	(FAT2CPU16((dent)->start) \
+			+ (mydata->fatsize != 32 ? 0 : \
+			  (FAT2CPU16((dent)->starthi) << 16)))
+#define IS_LAST_CLUST(x, fatsize) ((x) >= ((fatsize) != 32 ? \
+					((fatsize) != 16 ? 0xff8 : 0xfff8) : \
+					0xffffff8))
+#define CHECK_CLUST(x, fatsize) ((x) <= 1 || \
+				(x) >= ((fatsize) != 32 ? \
+					((fatsize) != 16 ? 0xff0 : 0xfff0) : \
+					0xffffff0))
+
+typedef struct boot_sector {
+	__u8	ignored[3];	/* Bootstrap code */
+	char	system_id[8];	/* Name of fs */
+	__u8	sector_size[2];	/* Bytes/sector */
+	__u8	cluster_size;	/* Sectors/cluster */
+	__u16	reserved;	/* Number of reserved sectors */
+	__u8	fats;		/* Number of FATs */
+	__u8	dir_entries[2];	/* Number of root directory entries */
+	__u8	sectors[2];	/* Number of sectors */
+	__u8	media;		/* Media code */
+	__u16	fat_length;	/* Sectors/FAT */
+	__u16	secs_track;	/* Sectors/track */
+	__u16	heads;		/* Number of heads */
+	__u32	hidden;		/* Number of hidden sectors */
+	__u32	total_sect;	/* Number of sectors (if sectors == 0) */
+
+	/* FAT32 only */
+	__u32	fat32_length;	/* Sectors/FAT */
+	__u16	flags;		/* Bit 8: fat mirroring, low 4: active fat */
+	__u8	version[2];	/* Filesystem version */
+	__u32	root_cluster;	/* First cluster in root directory */
+	__u16	info_sector;	/* Filesystem info sector */
+	__u16	backup_boot;	/* Backup boot sector */
+	__u16	reserved2[6];	/* Unused */
+} boot_sector;
+
+typedef struct volume_info
+{
+	__u8 drive_number;	/* BIOS drive number */
+	__u8 reserved;		/* Unused */
+	__u8 ext_boot_sign;	/* 0x29 if fields below exist (DOS 3.3+) */
+	__u8 volume_id[4];	/* Volume ID number */
+	char volume_label[11];	/* Volume label */
+	char fs_type[8];	/* Typically FAT12, FAT16, or FAT32 */
+	/* Boot code comes next, all but 2 bytes to fill up sector */
+	/* Boot sign comes last, 2 bytes */
+} volume_info;
+
+/* see dir_entry::lcase: */
+#define CASE_LOWER_BASE	8	/* base (name) is lower case */
+#define CASE_LOWER_EXT	16	/* extension is lower case */
+
+typedef struct dir_entry {
+	char	name[8],ext[3];	/* Name and extension */
+	__u8	attr;		/* Attribute bits */
+	__u8	lcase;		/* Case for name and ext (CASE_LOWER_x) */
+	__u8	ctime_ms;	/* Creation time, milliseconds */
+	__u16	ctime;		/* Creation time */
+	__u16	cdate;		/* Creation date */
+	__u16	adate;		/* Last access date */
+	__u16	starthi;	/* High 16 bits of cluster in FAT32 */
+	__u16	time,date,start;/* Time, date and first cluster */
+	__u32	size;		/* File size in bytes */
+} dir_entry;
+
+typedef struct dir_slot {
+	__u8	id;		/* Sequence number for slot */
+	__u8	name0_4[10];	/* First 5 characters in name */
+	__u8	attr;		/* Attribute byte */
+	__u8	reserved;	/* Unused */
+	__u8	alias_checksum;/* Checksum for 8.3 alias */
+	__u8	name5_10[12];	/* 6 more characters in name */
+	__u16	start;		/* Unused */
+	__u8	name11_12[4];	/* Last 2 characters in name */
+} dir_slot;
+
+/*
+ * Private filesystem parameters
+ *
+ * Note: FAT buffer has to be 32 bit aligned
+ * (see FAT32 accesses)
+ */
+typedef struct {
+	__u8	*fatbuf;	/* Current FAT buffer */
+	int	fatsize;	/* Size of FAT in bits */
+	__u32	fatlength;	/* Length of FAT in sectors */
+	__u16	fat_sect;	/* Starting sector of the FAT */
+	__u8	fat_dirty;      /* Set if fatbuf has been modified */
+	__u32	rootdir_sect;	/* Start sector of root directory */
+	__u16	sect_size;	/* Size of sectors in bytes */
+	__u16	clust_size;	/* Size of clusters in sectors */
+	int	data_begin;	/* The sector of the first cluster, can be negative */
+	int	fatbufnum;	/* Used by get_fatent, init to -1 */
+	int	rootdir_size;	/* Size of root dir for non-FAT32 */
+	__u32	root_cluster;	/* First cluster of root dir for FAT32 */
+	u32	total_sect;	/* Number of sectors */
+	int	fats;		/* Number of FATs */
+} fsdata;
+
+static inline u32 clust_to_sect(fsdata *fsdata, u32 clust)
+{
+	return fsdata->data_begin + clust * fsdata->clust_size;
+}
+
+static inline u32 sect_to_clust(fsdata *fsdata, int sect)
+{
+	return (sect - fsdata->data_begin) / fsdata->clust_size;
+}
+
+int file_fat_detectfs(void);
+int fat_exists(const char *filename);
+int fat_size(const char *filename, loff_t *size);
+int file_fat_read_at(const char *filename, loff_t pos, void *buffer,
+		     loff_t maxsize, loff_t *actread);
+int file_fat_read(const char *filename, void *buffer, int maxsize);
+int fat_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
+int fat_register_device(struct blk_desc *dev_desc, int part_no);
+
+int file_fat_write(const char *filename, void *buf, loff_t offset, loff_t len,
+		   loff_t *actwrite);
+int fat_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
+		  loff_t *actread);
+int fat_opendir(const char *filename, struct fs_dir_stream **dirsp);
+int fat_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp);
+void fat_closedir(struct fs_dir_stream *dirs);
+int fat_unlink(const char *filename);
+int fat_mkdir(const char *dirname);
+void fat_close(void);
+#endif /* _FAT_H_ */
diff --git a/include/fb_mmc.h b/include/fb_mmc.h
new file mode 100644
index 0000000..95db001
--- /dev/null
+++ b/include/fb_mmc.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#ifndef _FB_MMC_H_
+#define _FB_MMC_H_
+
+/**
+ * fastboot_mmc_get_part_info() - Lookup eMMC partion by name
+ *
+ * @part_name: Named partition to lookup
+ * @dev_desc: Pointer to returned blk_desc pointer
+ * @part_info: Pointer to returned disk_partition_t
+ * @response: Pointer to fastboot response buffer
+ */
+int fastboot_mmc_get_part_info(const char *part_name,
+			       struct blk_desc **dev_desc,
+			       disk_partition_t *part_info, char *response);
+
+/**
+ * fastboot_mmc_flash_write() - Write image to eMMC for fastboot
+ *
+ * @cmd: Named partition to write image to
+ * @download_buffer: Pointer to image data
+ * @download_bytes: Size of image data
+ * @response: Pointer to fastboot response buffer
+ */
+void fastboot_mmc_flash_write(const char *cmd, void *download_buffer,
+			      u32 download_bytes, char *response);
+/**
+ * fastboot_mmc_flash_erase() - Erase eMMC for fastboot
+ *
+ * @cmd: Named partition to erase
+ * @response: Pointer to fastboot response buffer
+ */
+void fastboot_mmc_erase(const char *cmd, char *response);
+#endif
diff --git a/include/fb_nand.h b/include/fb_nand.h
new file mode 100644
index 0000000..6d7999f
--- /dev/null
+++ b/include/fb_nand.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Broadcom Corporation.
+ * Copyright 2015 Free Electrons.
+ */
+
+#ifndef _FB_NAND_H_
+#define _FB_NAND_H_
+
+#include <jffs2/load_kernel.h>
+
+/**
+ * fastboot_nand_get_part_info() - Lookup NAND partion by name
+ *
+ * @part_name: Named device to lookup
+ * @part_info: Pointer to returned part_info pointer
+ * @response: Pointer to fastboot response buffer
+ */
+int fastboot_nand_get_part_info(const char *part_name,
+				struct part_info **part_info, char *response);
+
+/**
+ * fastboot_nand_flash_write() - Write image to NAND for fastboot
+ *
+ * @cmd: Named device to write image to
+ * @download_buffer: Pointer to image data
+ * @download_bytes: Size of image data
+ * @response: Pointer to fastboot response buffer
+ */
+void fastboot_nand_flash_write(const char *cmd, void *download_buffer,
+			       u32 download_bytes, char *response);
+
+/**
+ * fastboot_nand_flash_erase() - Erase NAND for fastboot
+ *
+ * @cmd: Named device to erase
+ * @response: Pointer to fastboot response buffer
+ */
+void fastboot_nand_erase(const char *cmd, char *response);
+#endif
diff --git a/include/fdt.h b/include/fdt.h
new file mode 100644
index 0000000..b97b3f2
--- /dev/null
+++ b/include/fdt.h
@@ -0,0 +1 @@
+#include "../scripts/dtc/libfdt/fdt.h"
diff --git a/include/fdt_simplefb.h b/include/fdt_simplefb.h
new file mode 100644
index 0000000..7cc305e
--- /dev/null
+++ b/include/fdt_simplefb.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Simplefb device tree support
+ *
+ * (C) Copyright 2015
+ * Stephen Warren <swarren@wwwdotorg.org>
+ */
+
+#ifndef _FDT_SIMPLEFB_H_
+#define _FDT_SIMPLEFB_H_
+int lcd_dt_simplefb_add_node(void *blob);
+int lcd_dt_simplefb_enable_existing_node(void *blob);
+#endif
diff --git a/include/fdt_support.h b/include/fdt_support.h
new file mode 100644
index 0000000..cefb2b2
--- /dev/null
+++ b/include/fdt_support.h
@@ -0,0 +1,337 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
+ */
+
+#ifndef __FDT_SUPPORT_H
+#define __FDT_SUPPORT_H
+
+#ifdef CONFIG_OF_LIBFDT
+
+#include <linux/libfdt.h>
+
+u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
+				const char *prop, const u32 dflt);
+u32 fdt_getprop_u32_default(const void *fdt, const char *path,
+				const char *prop, const u32 dflt);
+
+/**
+ * Add data to the root of the FDT before booting the OS.
+ *
+ * See doc/device-tree-bindings/root.txt
+ *
+ * @param fdt		FDT address in memory
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int fdt_root(void *fdt);
+
+/**
+ * Add chosen data the FDT before booting the OS.
+ *
+ * In particular, this adds the kernel command line (bootargs) to the FDT.
+ *
+ * @param fdt		FDT address in memory
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int fdt_chosen(void *fdt);
+
+/**
+ * Add initrd information to the FDT before booting the OS.
+ *
+ * @param fdt		FDT address in memory
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end);
+
+void do_fixup_by_path(void *fdt, const char *path, const char *prop,
+		      const void *val, int len, int create);
+void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
+			  u32 val, int create);
+
+static inline void do_fixup_by_path_string(void *fdt, const char *path,
+					   const char *prop, const char *status)
+{
+	do_fixup_by_path(fdt, path, prop, status, strlen(status) + 1, 1);
+}
+
+void do_fixup_by_prop(void *fdt,
+		      const char *pname, const void *pval, int plen,
+		      const char *prop, const void *val, int len,
+		      int create);
+void do_fixup_by_prop_u32(void *fdt,
+			  const char *pname, const void *pval, int plen,
+			  const char *prop, u32 val, int create);
+void do_fixup_by_compat(void *fdt, const char *compat,
+			const char *prop, const void *val, int len, int create);
+void do_fixup_by_compat_u32(void *fdt, const char *compat,
+			    const char *prop, u32 val, int create);
+/**
+ * Setup the memory node in the DT. Creates one if none was existing before.
+ * Calls fdt_fixup_memory_banks() to populate a single reg pair covering the
+ * whole memory.
+ *
+ * @param blob		FDT blob to update
+ * @param start		Begin of DRAM mapping in physical memory
+ * @param size		Size of the single memory bank
+ * @return 0 if ok, or -1 or -FDT_ERR_... on error
+ */
+int fdt_fixup_memory(void *blob, u64 start, u64 size);
+
+/**
+ * Fill the DT memory node with multiple memory banks.
+ * Creates the node if none was existing before.
+ * If banks is 0, it will not touch the existing reg property. This allows
+ * boards to not mess with the existing DT setup, which may have been
+ * filled in properly before.
+ *
+ * @param blob		FDT blob to update
+ * @param start		Array of size <banks> to hold the start addresses.
+ * @param size		Array of size <banks> to hold the size of each region.
+ * @param banks		Number of memory banks to create. If 0, the reg
+ *			property will be left untouched.
+ * @return 0 if ok, or -1 or -FDT_ERR_... on error
+ */
+#ifdef CONFIG_ARCH_FIXUP_FDT_MEMORY
+int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks);
+#else
+static inline int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[],
+					 int banks)
+{
+	return 0;
+}
+#endif
+
+void fdt_fixup_ethernet(void *fdt);
+int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
+			 const void *val, int len, int create);
+void fdt_fixup_qe_firmware(void *fdt);
+
+/**
+ * Update native-mode property of display-timings node to the phandle
+ * of the timings matching a display by name (case insensitive).
+ *
+ * see kernel Documentation/devicetree/bindings/video/display-timing.txt
+ *
+ * @param blob		FDT blob to update
+ * @param path		path within dt
+ * @param display	name of display timing to match
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int fdt_fixup_display(void *blob, const char *path, const char *display);
+
+#if defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL)
+void fsl_fdt_fixup_dr_usb(void *blob, bd_t *bd);
+#else
+static inline void fsl_fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
+#endif /* defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL) */
+
+#if defined(CONFIG_SYS_FSL_SEC_COMPAT)
+void fdt_fixup_crypto_node(void *blob, int sec_rev);
+#else
+static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
+#endif
+
+/**
+ * Record information about a processed loadable in /fit-images (creating
+ * /fit-images if necessary).
+ *
+ * @param blob		FDT blob to update
+ * @param index	        index of this loadable
+ * @param name          name of the loadable
+ * @param load_addr     address the loadable was loaded to
+ * @param size          number of bytes loaded
+ * @param entry_point   entry point (if specified, otherwise pass -1)
+ * @param type          type (if specified, otherwise pass NULL)
+ * @param os            os-type (if specified, otherwise pass NULL)
+ * @return 0 if ok, or -1 or -FDT_ERR_... on error
+ */
+int fdt_record_loadable(void *blob, u32 index, const char *name,
+			uintptr_t load_addr, u32 size, uintptr_t entry_point,
+			const char *type, const char *os);
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
+#endif
+
+int fdt_find_or_add_subnode(void *fdt, int parentoffset, const char *name);
+
+/**
+ * Add board-specific data to the FDT before booting the OS.
+ *
+ * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space.
+ * This function is called if CONFIG_OF_BOARD_SETUP is defined
+ *
+ * @param blob		FDT blob to update
+ * @param bd_t		Pointer to board data
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int ft_board_setup(void *blob, bd_t *bd);
+
+/*
+ * The keystone2 SOC requires all 32 bit aliased addresses to be converted
+ * to their 36 physical format. This has to happen after all fdt nodes
+ * are added or modified by the image_setup_libfdt(). The ft_board_setup_ex()
+ * called at the end of the image_setup_libfdt() is to do that convertion.
+ */
+void ft_board_setup_ex(void *blob, bd_t *bd);
+void ft_cpu_setup(void *blob, bd_t *bd);
+void ft_pci_setup(void *blob, bd_t *bd);
+
+/**
+ * Add system-specific data to the FDT before booting the OS.
+ *
+ * Use CONFIG_SYS_FDT_PAD to ensure there is sufficient space.
+ * This function is called if CONFIG_OF_SYSTEM_SETUP is defined
+ *
+ * @param blob		FDT blob to update
+ * @param bd_t		Pointer to board data
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int ft_system_setup(void *blob, bd_t *bd);
+
+void set_working_fdt_addr(ulong addr);
+
+/**
+ * shrink down the given blob to minimum size + some extrasize if required
+ *
+ * @param blob		FDT blob to update
+ * @param extrasize	additional bytes needed
+ * @return 0 if ok, or -FDT_ERR_... on error
+ */
+int fdt_shrink_to_minimum(void *blob, uint extrasize);
+int fdt_increase_size(void *fdt, int add_len);
+
+int fdt_fixup_nor_flash_size(void *blob);
+
+struct node_info;
+#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
+void fdt_fixup_mtdparts(void *fdt, const struct node_info *node_info,
+			int node_info_size);
+#else
+static inline void fdt_fixup_mtdparts(void *fdt,
+				      const struct node_info *node_info,
+				      int node_info_size)
+{
+}
+#endif
+
+void fdt_del_node_and_alias(void *blob, const char *alias);
+
+/**
+ * Translate an address from the DT into a CPU physical address
+ *
+ * The translation relies on the "ranges" property.
+ *
+ * @param blob		Pointer to device tree blob
+ * @param node_offset	Node DT offset
+ * @param in_addr	Pointer to the address to translate
+ * @return translated address or OF_BAD_ADDR on error
+ */
+u64 fdt_translate_address(const void *blob, int node_offset,
+			  const __be32 *in_addr);
+/**
+ * Translate a DMA address from the DT into a CPU physical address
+ *
+ * The translation relies on the "dma-ranges" property.
+ *
+ * @param blob		Pointer to device tree blob
+ * @param node_offset	Node DT offset
+ * @param in_addr	Pointer to the DMA address to translate
+ * @return translated DMA address or OF_BAD_ADDR on error
+ */
+u64 fdt_translate_dma_address(const void *blob, int node_offset,
+			      const __be32 *in_addr);
+
+int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
+					phys_addr_t compat_off);
+int fdt_alloc_phandle(void *blob);
+int fdt_set_phandle(void *fdt, int nodeoffset, uint32_t phandle);
+unsigned int fdt_create_phandle(void *fdt, int nodeoffset);
+int fdt_add_edid(void *blob, const char *compat, unsigned char *buf);
+
+int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
+			      u64 addr);
+u64 fdt_get_base_address(const void *fdt, int node);
+int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr,
+		   uint64_t *addr, uint64_t *len);
+
+enum fdt_status {
+	FDT_STATUS_OKAY,
+	FDT_STATUS_DISABLED,
+	FDT_STATUS_FAIL,
+	FDT_STATUS_FAIL_ERROR_CODE,
+};
+int fdt_set_node_status(void *fdt, int nodeoffset,
+			enum fdt_status status, unsigned int error_code);
+static inline int fdt_status_okay(void *fdt, int nodeoffset)
+{
+	return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_OKAY, 0);
+}
+static inline int fdt_status_disabled(void *fdt, int nodeoffset)
+{
+	return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_DISABLED, 0);
+}
+static inline int fdt_status_fail(void *fdt, int nodeoffset)
+{
+	return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_FAIL, 0);
+}
+
+int fdt_set_status_by_alias(void *fdt, const char *alias,
+			    enum fdt_status status, unsigned int error_code);
+static inline int fdt_status_okay_by_alias(void *fdt, const char *alias)
+{
+	return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_OKAY, 0);
+}
+static inline int fdt_status_disabled_by_alias(void *fdt, const char *alias)
+{
+	return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_DISABLED, 0);
+}
+static inline int fdt_status_fail_by_alias(void *fdt, const char *alias)
+{
+	return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_FAIL, 0);
+}
+
+/* Helper to read a big number; size is in cells (not bytes) */
+static inline u64 fdt_read_number(const fdt32_t *cell, int size)
+{
+	u64 r = 0;
+	while (size--)
+		r = (r << 32) | fdt32_to_cpu(*(cell++));
+	return r;
+}
+
+void fdt_support_default_count_cells(const void *blob, int parentoffset,
+					int *addrc, int *sizec);
+int ft_verify_fdt(void *fdt);
+int arch_fixup_memory_node(void *blob);
+
+int fdt_setup_simplefb_node(void *fdt, int node, u64 base_address, u32 width,
+			    u32 height, u32 stride, const char *format);
+
+int fdt_overlay_apply_verbose(void *fdt, void *fdto);
+
+/**
+ * fdt_get_cells_len() - Get the length of a type of cell in top-level nodes
+ *
+ * Returns the length of the cell type in bytes (4 or 8).
+ *
+ * @blob: Pointer to device tree blob
+ * @nr_cells_name: Name to lookup, e.g. "#address-cells"
+ */
+int fdt_get_cells_len(const void *blob, char *nr_cells_name);
+
+#endif /* ifdef CONFIG_OF_LIBFDT */
+
+#ifdef USE_HOSTCC
+int fdtdec_get_int(const void *blob, int node, const char *prop_name,
+		int default_val);
+#endif
+#ifdef CONFIG_FMAN_ENET
+int fdt_update_ethernet_dt(void *blob);
+#endif
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *blob);
+#endif
+#endif /* ifndef __FDT_SUPPORT_H */
diff --git a/include/fdtdec.h b/include/fdtdec.h
new file mode 100644
index 0000000..f1e58f9
--- /dev/null
+++ b/include/fdtdec.h
@@ -0,0 +1,1217 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __fdtdec_h
+#define __fdtdec_h
+
+/*
+ * This file contains convenience functions for decoding useful and
+ * enlightening information from FDTs. It is intended to be used by device
+ * drivers and board-specific code within U-Boot. It aims to reduce the
+ * amount of FDT munging required within U-Boot itself, so that driver code
+ * changes to support FDT are minimized.
+ */
+
+#include <linux/libfdt.h>
+#include <pci.h>
+
+/*
+ * A typedef for a physical address. Note that fdt data is always big
+ * endian even on a litle endian machine.
+ */
+typedef phys_addr_t fdt_addr_t;
+typedef phys_size_t fdt_size_t;
+
+#ifdef CONFIG_PHYS_64BIT
+#define FDT_ADDR_T_NONE (-1U)
+#define fdt_addr_to_cpu(reg) be64_to_cpu(reg)
+#define fdt_size_to_cpu(reg) be64_to_cpu(reg)
+#define cpu_to_fdt_addr(reg) cpu_to_be64(reg)
+#define cpu_to_fdt_size(reg) cpu_to_be64(reg)
+typedef fdt64_t fdt_val_t;
+#else
+#define FDT_ADDR_T_NONE (-1U)
+#define fdt_addr_to_cpu(reg) be32_to_cpu(reg)
+#define fdt_size_to_cpu(reg) be32_to_cpu(reg)
+#define cpu_to_fdt_addr(reg) cpu_to_be32(reg)
+#define cpu_to_fdt_size(reg) cpu_to_be32(reg)
+typedef fdt32_t fdt_val_t;
+#endif
+
+/* Information obtained about memory from the FDT */
+struct fdt_memory {
+	fdt_addr_t start;
+	fdt_addr_t end;
+};
+
+struct bd_info;
+
+#ifdef CONFIG_SPL_BUILD
+#define SPL_BUILD	1
+#else
+#define SPL_BUILD	0
+#endif
+
+#ifdef CONFIG_OF_PRIOR_STAGE
+extern phys_addr_t prior_stage_fdt_address;
+#endif
+
+/*
+ * Information about a resource. start is the first address of the resource
+ * and end is the last address (inclusive). The length of the resource will
+ * be equal to: end - start + 1.
+ */
+struct fdt_resource {
+	fdt_addr_t start;
+	fdt_addr_t end;
+};
+
+enum fdt_pci_space {
+	FDT_PCI_SPACE_CONFIG = 0,
+	FDT_PCI_SPACE_IO = 0x01000000,
+	FDT_PCI_SPACE_MEM32 = 0x02000000,
+	FDT_PCI_SPACE_MEM64 = 0x03000000,
+	FDT_PCI_SPACE_MEM32_PREF = 0x42000000,
+	FDT_PCI_SPACE_MEM64_PREF = 0x43000000,
+};
+
+#define FDT_PCI_ADDR_CELLS	3
+#define FDT_PCI_SIZE_CELLS	2
+#define FDT_PCI_REG_SIZE	\
+	((FDT_PCI_ADDR_CELLS + FDT_PCI_SIZE_CELLS) * sizeof(u32))
+
+/*
+ * The Open Firmware spec defines PCI physical address as follows:
+ *
+ *          bits# 31 .... 24 23 .... 16 15 .... 08 07 .... 00
+ *
+ * phys.hi  cell:  npt000ss   bbbbbbbb   dddddfff   rrrrrrrr
+ * phys.mid cell:  hhhhhhhh   hhhhhhhh   hhhhhhhh   hhhhhhhh
+ * phys.lo  cell:  llllllll   llllllll   llllllll   llllllll
+ *
+ * where:
+ *
+ * n:        is 0 if the address is relocatable, 1 otherwise
+ * p:        is 1 if addressable region is prefetchable, 0 otherwise
+ * t:        is 1 if the address is aliased (for non-relocatable I/O) below 1MB
+ *           (for Memory), or below 64KB (for relocatable I/O)
+ * ss:       is the space code, denoting the address space
+ * bbbbbbbb: is the 8-bit Bus Number
+ * ddddd:    is the 5-bit Device Number
+ * fff:      is the 3-bit Function Number
+ * rrrrrrrr: is the 8-bit Register Number
+ * hhhhhhhh: is a 32-bit unsigned number
+ * llllllll: is a 32-bit unsigned number
+ */
+struct fdt_pci_addr {
+	u32	phys_hi;
+	u32	phys_mid;
+	u32	phys_lo;
+};
+
+/**
+ * Compute the size of a resource.
+ *
+ * @param res	the resource to operate on
+ * @return the size of the resource
+ */
+static inline fdt_size_t fdt_resource_size(const struct fdt_resource *res)
+{
+	return res->end - res->start + 1;
+}
+
+/**
+ * Compat types that we know about and for which we might have drivers.
+ * Each is named COMPAT_<dir>_<filename> where <dir> is the directory
+ * within drivers.
+ */
+enum fdt_compat_id {
+	COMPAT_UNKNOWN,
+	COMPAT_NVIDIA_TEGRA20_EMC,	/* Tegra20 memory controller */
+	COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
+	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
+	COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
+					/* Tegra124 XUSB pad controller */
+	COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
+					/* Tegra210 XUSB pad controller */
+	COMPAT_SMSC_LAN9215,		/* SMSC 10/100 Ethernet LAN9215 */
+	COMPAT_SAMSUNG_EXYNOS5_SROMC,	/* Exynos5 SROMC */
+	COMPAT_SAMSUNG_EXYNOS_USB_PHY,	/* Exynos phy controller for usb2.0 */
+	COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */
+	COMPAT_SAMSUNG_EXYNOS_TMU,	/* Exynos TMU */
+	COMPAT_SAMSUNG_EXYNOS_MIPI_DSI,	/* Exynos mipi dsi */
+	COMPAT_SAMSUNG_EXYNOS_DWMMC,	/* Exynos DWMMC controller */
+	COMPAT_GENERIC_SPI_FLASH,	/* Generic SPI Flash chip */
+	COMPAT_SAMSUNG_EXYNOS_SYSMMU,	/* Exynos sysmmu */
+	COMPAT_INTEL_MICROCODE,		/* Intel microcode update */
+	COMPAT_INTEL_QRK_MRC,		/* Intel Quark MRC */
+	COMPAT_ALTERA_SOCFPGA_DWMAC,	/* SoCFPGA Ethernet controller */
+	COMPAT_ALTERA_SOCFPGA_DWMMC,	/* SoCFPGA DWMMC controller */
+	COMPAT_ALTERA_SOCFPGA_DWC2USB,	/* SoCFPGA DWC2 USB controller */
+	COMPAT_INTEL_BAYTRAIL_FSP,	/* Intel Bay Trail FSP */
+	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
+	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
+	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller */
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock initialization */
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* SoCFPGA pinctrl-single */
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,          /* SoCFPGA hps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,        /* SoCFPGA lwhps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,          /* SoCFPGA fpga2hps bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,           /* SoCFPGA fpga2SDRAM0 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,           /* SoCFPGA fpga2SDRAM1 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,           /* SoCFPGA fpga2SDRAM2 bridge */
+	COMPAT_ALTERA_SOCFPGA_FPGA0,		/* SOCFPGA FPGA manager */
+	COMPAT_ALTERA_SOCFPGA_NOC,		/* SOCFPGA Arria 10 NOC */
+	COMPAT_ALTERA_SOCFPGA_CLK_INIT,		/* SOCFPGA Arria 10 clk init */
+
+	COMPAT_COUNT,
+};
+
+#define MAX_PHANDLE_ARGS 16
+struct fdtdec_phandle_args {
+	int node;
+	int args_count;
+	uint32_t args[MAX_PHANDLE_ARGS];
+};
+
+/**
+ * fdtdec_parse_phandle_with_args() - Find a node pointed by phandle in a list
+ *
+ * This function is useful to parse lists of phandles and their arguments.
+ *
+ * Example:
+ *
+ * phandle1: node1 {
+ *	#list-cells = <2>;
+ * }
+ *
+ * phandle2: node2 {
+ *	#list-cells = <1>;
+ * }
+ *
+ * node3 {
+ *	list = <&phandle1 1 2 &phandle2 3>;
+ * }
+ *
+ * To get a device_node of the `node2' node you may call this:
+ * fdtdec_parse_phandle_with_args(blob, node3, "list", "#list-cells", 0, 1,
+ *				  &args);
+ *
+ * (This function is a modified version of __of_parse_phandle_with_args() from
+ * Linux 3.18)
+ *
+ * @blob:	Pointer to device tree
+ * @src_node:	Offset of device tree node containing a list
+ * @list_name:	property name that contains a list
+ * @cells_name:	property name that specifies the phandles' arguments count,
+ *		or NULL to use @cells_count
+ * @cells_count: Cell count to use if @cells_name is NULL
+ * @index:	index of a phandle to parse out
+ * @out_args:	optional pointer to output arguments structure (will be filled)
+ * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if
+ *	@list_name does not exist, a phandle was not found, @cells_name
+ *	could not be found, the arguments were truncated or there were too
+ *	many arguments.
+ *
+ */
+int fdtdec_parse_phandle_with_args(const void *blob, int src_node,
+				   const char *list_name,
+				   const char *cells_name,
+				   int cell_count, int index,
+				   struct fdtdec_phandle_args *out_args);
+
+/**
+ * Find the next numbered alias for a peripheral. This is used to enumerate
+ * all the peripherals of a certain type.
+ *
+ * Do the first call with *upto = 0. Assuming /aliases/<name>0 exists then
+ * this function will return a pointer to the node the alias points to, and
+ * then update *upto to 1. Next time you call this function, the next node
+ * will be returned.
+ *
+ * All nodes returned will match the compatible ID, as it is assumed that
+ * all peripherals use the same driver.
+ *
+ * @param blob		FDT blob to use
+ * @param name		Root name of alias to search for
+ * @param id		Compatible ID to look for
+ * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more
+ */
+int fdtdec_next_alias(const void *blob, const char *name,
+		enum fdt_compat_id id, int *upto);
+
+/**
+ * Find the compatible ID for a given node.
+ *
+ * Generally each node has at least one compatible string attached to it.
+ * This function looks through our list of known compatible strings and
+ * returns the corresponding ID which matches the compatible string.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Node containing compatible string to find
+ * @return compatible ID, or COMPAT_UNKNOWN if we cannot find a match
+ */
+enum fdt_compat_id fdtdec_lookup(const void *blob, int node);
+
+/**
+ * Find the next compatible node for a peripheral.
+ *
+ * Do the first call with node = 0. This function will return a pointer to
+ * the next compatible node. Next time you call this function, pass the
+ * value returned, and the next node will be provided.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Start node for search
+ * @param id		Compatible ID to look for (enum fdt_compat_id)
+ * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more
+ */
+int fdtdec_next_compatible(const void *blob, int node,
+		enum fdt_compat_id id);
+
+/**
+ * Find the next compatible subnode for a peripheral.
+ *
+ * Do the first call with node set to the parent and depth = 0. This
+ * function will return the offset of the next compatible node. Next time
+ * you call this function, pass the node value returned last time, with
+ * depth unchanged, and the next node will be provided.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Start node for search
+ * @param id		Compatible ID to look for (enum fdt_compat_id)
+ * @param depthp	Current depth (set to 0 before first call)
+ * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more
+ */
+int fdtdec_next_compatible_subnode(const void *blob, int node,
+		enum fdt_compat_id id, int *depthp);
+
+/*
+ * Look up an address property in a node and return the parsed address, and
+ * optionally the parsed size.
+ *
+ * This variant assumes a known and fixed number of cells are used to
+ * represent the address and size.
+ *
+ * You probably don't want to use this function directly except to parse
+ * non-standard properties, and never to parse the "reg" property. Instead,
+ * use one of the "auto" variants below, which automatically honor the
+ * #address-cells and #size-cells properties in the parent node.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @param index	which address to retrieve from a list of addresses. Often 0.
+ * @param na	the number of cells used to represent an address
+ * @param ns	the number of cells used to represent a size
+ * @param sizep	a pointer to store the size into. Use NULL if not required
+ * @param translate	Indicates whether to translate the returned value
+ *			using the parent node's ranges property.
+ * @return address, if found, or FDT_ADDR_T_NONE if not
+ */
+fdt_addr_t fdtdec_get_addr_size_fixed(const void *blob, int node,
+		const char *prop_name, int index, int na, int ns,
+		fdt_size_t *sizep, bool translate);
+
+/*
+ * Look up an address property in a node and return the parsed address, and
+ * optionally the parsed size.
+ *
+ * This variant automatically determines the number of cells used to represent
+ * the address and size by parsing the provided parent node's #address-cells
+ * and #size-cells properties.
+ *
+ * @param blob	FDT blob
+ * @param parent	parent node of @node
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @param index	which address to retrieve from a list of addresses. Often 0.
+ * @param sizep	a pointer to store the size into. Use NULL if not required
+ * @param translate	Indicates whether to translate the returned value
+ *			using the parent node's ranges property.
+ * @return address, if found, or FDT_ADDR_T_NONE if not
+ */
+fdt_addr_t fdtdec_get_addr_size_auto_parent(const void *blob, int parent,
+		int node, const char *prop_name, int index, fdt_size_t *sizep,
+		bool translate);
+
+/*
+ * Look up an address property in a node and return the parsed address, and
+ * optionally the parsed size.
+ *
+ * This variant automatically determines the number of cells used to represent
+ * the address and size by parsing the parent node's #address-cells
+ * and #size-cells properties. The parent node is automatically found.
+ *
+ * The automatic parent lookup implemented by this function is slow.
+ * Consequently, fdtdec_get_addr_size_auto_parent() should be used where
+ * possible.
+ *
+ * @param blob	FDT blob
+ * @param parent	parent node of @node
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @param index	which address to retrieve from a list of addresses. Often 0.
+ * @param sizep	a pointer to store the size into. Use NULL if not required
+ * @param translate	Indicates whether to translate the returned value
+ *			using the parent node's ranges property.
+ * @return address, if found, or FDT_ADDR_T_NONE if not
+ */
+fdt_addr_t fdtdec_get_addr_size_auto_noparent(const void *blob, int node,
+		const char *prop_name, int index, fdt_size_t *sizep,
+		bool translate);
+
+/*
+ * Look up an address property in a node and return the parsed address.
+ *
+ * This variant hard-codes the number of cells used to represent the address
+ * and size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t). It also
+ * always returns the first address value in the property (index 0).
+ *
+ * Use of this function is not recommended due to the hard-coding of cell
+ * counts. There is no programmatic validation that these hard-coded values
+ * actually match the device tree content in any way at all. This assumption
+ * can be satisfied by manually ensuring CONFIG_PHYS_64BIT is appropriately
+ * set in the U-Boot build and exercising strict control over DT content to
+ * ensure use of matching #address-cells/#size-cells properties. However, this
+ * approach is error-prone; those familiar with DT will not expect the
+ * assumption to exist, and could easily invalidate it. If the assumption is
+ * invalidated, this function will not report the issue, and debugging will
+ * be required. Instead, use fdtdec_get_addr_size_auto_parent().
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @return address, if found, or FDT_ADDR_T_NONE if not
+ */
+fdt_addr_t fdtdec_get_addr(const void *blob, int node,
+		const char *prop_name);
+
+/*
+ * Look up an address property in a node and return the parsed address, and
+ * optionally the parsed size.
+ *
+ * This variant hard-codes the number of cells used to represent the address
+ * and size based on sizeof(fdt_addr_t) and sizeof(fdt_size_t). It also
+ * always returns the first address value in the property (index 0).
+ *
+ * Use of this function is not recommended due to the hard-coding of cell
+ * counts. There is no programmatic validation that these hard-coded values
+ * actually match the device tree content in any way at all. This assumption
+ * can be satisfied by manually ensuring CONFIG_PHYS_64BIT is appropriately
+ * set in the U-Boot build and exercising strict control over DT content to
+ * ensure use of matching #address-cells/#size-cells properties. However, this
+ * approach is error-prone; those familiar with DT will not expect the
+ * assumption to exist, and could easily invalidate it. If the assumption is
+ * invalidated, this function will not report the issue, and debugging will
+ * be required. Instead, use fdtdec_get_addr_size_auto_parent().
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @param sizep	a pointer to store the size into. Use NULL if not required
+ * @return address, if found, or FDT_ADDR_T_NONE if not
+ */
+fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
+		const char *prop_name, fdt_size_t *sizep);
+
+/**
+ * Look at the compatible property of a device node that represents a PCI
+ * device and extract pci vendor id and device id from it.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param vendor	vendor id of the pci device
+ * @param device	device id of the pci device
+ * @return 0 if ok, negative on error
+ */
+int fdtdec_get_pci_vendev(const void *blob, int node,
+		u16 *vendor, u16 *device);
+
+/**
+ * Look at the pci address of a device node that represents a PCI device
+ * and return base address of the pci device's registers.
+ *
+ * @param dev		device to examine
+ * @param addr		pci address in the form of fdt_pci_addr
+ * @param bar		returns base address of the pci device's registers
+ * @return 0 if ok, negative on error
+ */
+int fdtdec_get_pci_bar32(struct udevice *dev, struct fdt_pci_addr *addr,
+			 u32 *bar);
+
+/**
+ * Look up a 32-bit integer property in a node and return it. The property
+ * must have at least 4 bytes of data. The value of the first cell is
+ * returned.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @param default_val	default value to return if the property is not found
+ * @return integer value, if found, or default_val if not
+ */
+s32 fdtdec_get_int(const void *blob, int node, const char *prop_name,
+		s32 default_val);
+
+/**
+ * Unsigned version of fdtdec_get_int. The property must have at least
+ * 4 bytes of data. The value of the first cell is returned.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @param default_val	default value to return if the property is not found
+ * @return unsigned integer value, if found, or default_val if not
+ */
+unsigned int fdtdec_get_uint(const void *blob, int node, const char *prop_name,
+			unsigned int default_val);
+
+/**
+ * Get a variable-sized number from a property
+ *
+ * This reads a number from one or more cells.
+ *
+ * @param ptr	Pointer to property
+ * @param cells	Number of cells containing the number
+ * @return the value in the cells
+ */
+u64 fdtdec_get_number(const fdt32_t *ptr, unsigned int cells);
+
+/**
+ * Look up a 64-bit integer property in a node and return it. The property
+ * must have at least 8 bytes of data (2 cells). The first two cells are
+ * concatenated to form a 8 bytes value, where the first cell is top half and
+ * the second cell is bottom half.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @param default_val	default value to return if the property is not found
+ * @return integer value, if found, or default_val if not
+ */
+uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
+		uint64_t default_val);
+
+/**
+ * Checks whether a node is enabled.
+ * This looks for a 'status' property. If this exists, then returns 1 if
+ * the status is 'ok' and 0 otherwise. If there is no status property,
+ * it returns 1 on the assumption that anything mentioned should be enabled
+ * by default.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @return integer value 0 (not enabled) or 1 (enabled)
+ */
+int fdtdec_get_is_enabled(const void *blob, int node);
+
+/**
+ * Make sure we have a valid fdt available to control U-Boot.
+ *
+ * If not, a message is printed to the console if the console is ready.
+ *
+ * @return 0 if all ok, -1 if not
+ */
+int fdtdec_prepare_fdt(void);
+
+/**
+ * Checks that we have a valid fdt available to control U-Boot.
+
+ * However, if not then for the moment nothing is done, since this function
+ * is called too early to panic().
+ *
+ * @returns 0
+ */
+int fdtdec_check_fdt(void);
+
+/**
+ * Find the nodes for a peripheral and return a list of them in the correct
+ * order. This is used to enumerate all the peripherals of a certain type.
+ *
+ * To use this, optionally set up a /aliases node with alias properties for
+ * a peripheral. For example, for usb you could have:
+ *
+ * aliases {
+ *		usb0 = "/ehci@c5008000";
+ *		usb1 = "/ehci@c5000000";
+ * };
+ *
+ * Pass "usb" as the name to this function and will return a list of two
+ * nodes offsets: /ehci@c5008000 and ehci@c5000000.
+ *
+ * All nodes returned will match the compatible ID, as it is assumed that
+ * all peripherals use the same driver.
+ *
+ * If no alias node is found, then the node list will be returned in the
+ * order found in the fdt. If the aliases mention a node which doesn't
+ * exist, then this will be ignored. If nodes are found with no aliases,
+ * they will be added in any order.
+ *
+ * If there is a gap in the aliases, then this function return a 0 node at
+ * that position. The return value will also count these gaps.
+ *
+ * This function checks node properties and will not return nodes which are
+ * marked disabled (status = "disabled").
+ *
+ * @param blob		FDT blob to use
+ * @param name		Root name of alias to search for
+ * @param id		Compatible ID to look for
+ * @param node_list	Place to put list of found nodes
+ * @param maxcount	Maximum number of nodes to find
+ * @return number of nodes found on success, FDT_ERR_... on error
+ */
+int fdtdec_find_aliases_for_id(const void *blob, const char *name,
+			enum fdt_compat_id id, int *node_list, int maxcount);
+
+/*
+ * This function is similar to fdtdec_find_aliases_for_id() except that it
+ * adds to the node_list that is passed in. Any 0 elements are considered
+ * available for allocation - others are considered already used and are
+ * skipped.
+ *
+ * You can use this by calling fdtdec_find_aliases_for_id() with an
+ * uninitialised array, then setting the elements that are returned to -1,
+ * say, then calling this function, perhaps with a different compat id.
+ * Any elements you get back that are >0 are new nodes added by the call
+ * to this function.
+ *
+ * Note that if you have some nodes with aliases and some without, you are
+ * sailing close to the wind. The call to fdtdec_find_aliases_for_id() with
+ * one compat_id may fill in positions for which you have aliases defined
+ * for another compat_id. When you later call *this* function with the second
+ * compat_id, the alias positions may already be used. A debug warning may
+ * be generated in this case, but it is safest to define aliases for all
+ * nodes when you care about the ordering.
+ */
+int fdtdec_add_aliases_for_id(const void *blob, const char *name,
+			enum fdt_compat_id id, int *node_list, int maxcount);
+
+/**
+ * Get the alias sequence number of a node
+ *
+ * This works out whether a node is pointed to by an alias, and if so, the
+ * sequence number of that alias. Aliases are of the form <base><num> where
+ * <num> is the sequence number. For example spi2 would be sequence number
+ * 2.
+ *
+ * @param blob		Device tree blob (if NULL, then error is returned)
+ * @param base		Base name for alias (before the underscore)
+ * @param node		Node to look up
+ * @param seqp		This is set to the sequence number if one is found,
+ *			but otherwise the value is left alone
+ * @return 0 if a sequence was found, -ve if not
+ */
+int fdtdec_get_alias_seq(const void *blob, const char *base, int node,
+			 int *seqp);
+
+/**
+ * Get the highest alias number for susbystem.
+ *
+ * It parses all aliases and find out highest recorded alias for subsystem.
+ * Aliases are of the form <base><num> where <num> is the sequence number.
+ *
+ * @param blob		Device tree blob (if NULL, then error is returned)
+ * @param base		Base name for alias susbystem (before the number)
+ *
+ * @return 0 highest alias ID, -1 if not found
+ */
+int fdtdec_get_alias_highest_id(const void *blob, const char *base);
+
+/**
+ * Get a property from the /chosen node
+ *
+ * @param blob		Device tree blob (if NULL, then NULL is returned)
+ * @param name		Property name to look up
+ * @return Value of property, or NULL if it does not exist
+ */
+const char *fdtdec_get_chosen_prop(const void *blob, const char *name);
+
+/**
+ * Get the offset of the given /chosen node
+ *
+ * This looks up a property in /chosen containing the path to another node,
+ * then finds the offset of that node.
+ *
+ * @param blob		Device tree blob (if NULL, then error is returned)
+ * @param name		Property name, e.g. "stdout-path"
+ * @return Node offset referred to by that chosen node, or -ve FDT_ERR_...
+ */
+int fdtdec_get_chosen_node(const void *blob, const char *name);
+
+/*
+ * Get the name for a compatible ID
+ *
+ * @param id		Compatible ID to look for
+ * @return compatible string for that id
+ */
+const char *fdtdec_get_compatible(enum fdt_compat_id id);
+
+/* Look up a phandle and follow it to its node. Then return the offset
+ * of that node.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @return node offset if found, -ve error code on error
+ */
+int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name);
+
+/**
+ * Look up a property in a node and return its contents in an integer
+ * array of given length. The property must have at least enough data for
+ * the array (4*count bytes). It may have more, but this will be ignored.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param array		array to fill with data
+ * @param count		number of array elements
+ * @return 0 if ok, or -FDT_ERR_NOTFOUND if the property is not found,
+ *		or -FDT_ERR_BADLAYOUT if not enough data
+ */
+int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
+		u32 *array, int count);
+
+/**
+ * Look up a property in a node and return its contents in an integer
+ * array of given length. The property must exist but may have less data that
+ * expected (4*count bytes). It may have more, but this will be ignored.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param array		array to fill with data
+ * @param count		number of array elements
+ * @return number of array elements if ok, or -FDT_ERR_NOTFOUND if the
+ *		property is not found
+ */
+int fdtdec_get_int_array_count(const void *blob, int node,
+			       const char *prop_name, u32 *array, int count);
+
+/**
+ * Look up a property in a node and return a pointer to its contents as a
+ * unsigned int array of given length. The property must have at least enough
+ * data for the array ('count' cells). It may have more, but this will be
+ * ignored. The data is not copied.
+ *
+ * Note that you must access elements of the array with fdt32_to_cpu(),
+ * since the elements will be big endian even on a little endian machine.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param count		number of array elements
+ * @return pointer to array if found, or NULL if the property is not
+ *		found or there is not enough data
+ */
+const u32 *fdtdec_locate_array(const void *blob, int node,
+			       const char *prop_name, int count);
+
+/**
+ * Look up a boolean property in a node and return it.
+ *
+ * A boolean properly is true if present in the device tree and false if not
+ * present, regardless of its value.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @return 1 if the properly is present; 0 if it isn't present
+ */
+int fdtdec_get_bool(const void *blob, int node, const char *prop_name);
+
+/*
+ * Count child nodes of one parent node.
+ *
+ * @param blob	FDT blob
+ * @param node	parent node
+ * @return number of child node; 0 if there is not child node
+ */
+int fdtdec_get_child_count(const void *blob, int node);
+
+/**
+ * Look in the FDT for a config item with the given name and return its value
+ * as a 32-bit integer. The property must have at least 4 bytes of data. The
+ * value of the first cell is returned.
+ *
+ * @param blob		FDT blob to use
+ * @param prop_name	Node property name
+ * @param default_val	default value to return if the property is not found
+ * @return integer value, if found, or default_val if not
+ */
+int fdtdec_get_config_int(const void *blob, const char *prop_name,
+		int default_val);
+
+/**
+ * Look in the FDT for a config item with the given name
+ * and return whether it exists.
+ *
+ * @param blob		FDT blob
+ * @param prop_name	property name to look up
+ * @return 1, if it exists, or 0 if not
+ */
+int fdtdec_get_config_bool(const void *blob, const char *prop_name);
+
+/**
+ * Look in the FDT for a config item with the given name and return its value
+ * as a string.
+ *
+ * @param blob          FDT blob
+ * @param prop_name     property name to look up
+ * @returns property string, NULL on error.
+ */
+char *fdtdec_get_config_string(const void *blob, const char *prop_name);
+
+/*
+ * Look up a property in a node and return its contents in a byte
+ * array of given length. The property must have at least enough data for
+ * the array (count bytes). It may have more, but this will be ignored.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param array		array to fill with data
+ * @param count		number of array elements
+ * @return 0 if ok, or -FDT_ERR_MISSING if the property is not found,
+ *		or -FDT_ERR_BADLAYOUT if not enough data
+ */
+int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
+		u8 *array, int count);
+
+/**
+ * Look up a property in a node and return a pointer to its contents as a
+ * byte array of given length. The property must have at least enough data
+ * for the array (count bytes). It may have more, but this will be ignored.
+ * The data is not copied.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param count		number of array elements
+ * @return pointer to byte array if found, or NULL if the property is not
+ *		found or there is not enough data
+ */
+const u8 *fdtdec_locate_byte_array(const void *blob, int node,
+			     const char *prop_name, int count);
+
+/**
+ * Obtain an indexed resource from a device property.
+ *
+ * @param fdt		FDT blob
+ * @param node		node to examine
+ * @param property	name of the property to parse
+ * @param index		index of the resource to retrieve
+ * @param res		returns the resource
+ * @return 0 if ok, negative on error
+ */
+int fdt_get_resource(const void *fdt, int node, const char *property,
+		     unsigned int index, struct fdt_resource *res);
+
+/**
+ * Obtain a named resource from a device property.
+ *
+ * Look up the index of the name in a list of strings and return the resource
+ * at that index.
+ *
+ * @param fdt		FDT blob
+ * @param node		node to examine
+ * @param property	name of the property to parse
+ * @param prop_names	name of the property containing the list of names
+ * @param name		the name of the entry to look up
+ * @param res		returns the resource
+ */
+int fdt_get_named_resource(const void *fdt, int node, const char *property,
+			   const char *prop_names, const char *name,
+			   struct fdt_resource *res);
+
+/* Display timings from linux include/video/display_timing.h */
+enum display_flags {
+	DISPLAY_FLAGS_HSYNC_LOW		= 1 << 0,
+	DISPLAY_FLAGS_HSYNC_HIGH	= 1 << 1,
+	DISPLAY_FLAGS_VSYNC_LOW		= 1 << 2,
+	DISPLAY_FLAGS_VSYNC_HIGH	= 1 << 3,
+
+	/* data enable flag */
+	DISPLAY_FLAGS_DE_LOW		= 1 << 4,
+	DISPLAY_FLAGS_DE_HIGH		= 1 << 5,
+	/* drive data on pos. edge */
+	DISPLAY_FLAGS_PIXDATA_POSEDGE	= 1 << 6,
+	/* drive data on neg. edge */
+	DISPLAY_FLAGS_PIXDATA_NEGEDGE	= 1 << 7,
+	DISPLAY_FLAGS_INTERLACED	= 1 << 8,
+	DISPLAY_FLAGS_DOUBLESCAN	= 1 << 9,
+	DISPLAY_FLAGS_DOUBLECLK		= 1 << 10,
+};
+
+/*
+ * A single signal can be specified via a range of minimal and maximal values
+ * with a typical value, that lies somewhere inbetween.
+ */
+struct timing_entry {
+	u32 min;
+	u32 typ;
+	u32 max;
+};
+
+/*
+ * Single "mode" entry. This describes one set of signal timings a display can
+ * have in one setting. This struct can later be converted to struct videomode
+ * (see include/video/videomode.h). As each timing_entry can be defined as a
+ * range, one struct display_timing may become multiple struct videomodes.
+ *
+ * Example: hsync active high, vsync active low
+ *
+ *				    Active Video
+ * Video  ______________________XXXXXXXXXXXXXXXXXXXXXX_____________________
+ *	  |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync..
+ *	  |	     |	 porch  |		     |	 porch	 |
+ *
+ * HSync _|¯¯¯¯¯¯¯¯¯¯|___________________________________________|¯¯¯¯¯¯¯¯¯
+ *
+ * VSync ¯|__________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_________
+ */
+struct display_timing {
+	struct timing_entry pixelclock;
+
+	struct timing_entry hactive;		/* hor. active video */
+	struct timing_entry hfront_porch;	/* hor. front porch */
+	struct timing_entry hback_porch;	/* hor. back porch */
+	struct timing_entry hsync_len;		/* hor. sync len */
+
+	struct timing_entry vactive;		/* ver. active video */
+	struct timing_entry vfront_porch;	/* ver. front porch */
+	struct timing_entry vback_porch;	/* ver. back porch */
+	struct timing_entry vsync_len;		/* ver. sync len */
+
+	enum display_flags flags;		/* display flags */
+	bool hdmi_monitor;			/* is hdmi monitor? */
+};
+
+/**
+ * fdtdec_decode_display_timing() - decode display timings
+ *
+ * Decode display timings from the supplied 'display-timings' node.
+ * See doc/device-tree-bindings/video/display-timing.txt for binding
+ * information.
+ *
+ * @param blob		FDT blob
+ * @param node		'display-timing' node containing the timing subnodes
+ * @param index		Index number to read (0=first timing subnode)
+ * @param config	Place to put timings
+ * @return 0 if OK, -FDT_ERR_NOTFOUND if not found
+ */
+int fdtdec_decode_display_timing(const void *blob, int node, int index,
+				 struct display_timing *config);
+
+/**
+ * fdtdec_setup_mem_size_base_fdt() - decode and setup gd->ram_size and
+ * gd->ram_start
+ *
+ * Decode the /memory 'reg' property to determine the size and start of the
+ * first memory bank, populate the global data with the size and start of the
+ * first bank of memory.
+ *
+ * This function should be called from a boards dram_init(). This helper
+ * function allows for boards to query the device tree for DRAM size and start
+ * address instead of hard coding the value in the case where the memory size
+ * and start address cannot be detected automatically.
+ *
+ * @param blob		FDT blob
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_mem_size_base_fdt(const void *blob);
+
+/**
+ * fdtdec_setup_mem_size_base() - decode and setup gd->ram_size and
+ * gd->ram_start
+ *
+ * Decode the /memory 'reg' property to determine the size and start of the
+ * first memory bank, populate the global data with the size and start of the
+ * first bank of memory.
+ *
+ * This function should be called from a boards dram_init(). This helper
+ * function allows for boards to query the device tree for DRAM size and start
+ * address instead of hard coding the value in the case where the memory size
+ * and start address cannot be detected automatically.
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_mem_size_base(void);
+
+/**
+ * fdtdec_setup_memory_banksize_fdt() - decode and populate gd->bd->bi_dram
+ *
+ * Decode the /memory 'reg' property to determine the address and size of the
+ * memory banks. Use this data to populate the global data board info with the
+ * phys address and size of memory banks.
+ *
+ * This function should be called from a boards dram_init_banksize(). This
+ * helper function allows for boards to query the device tree for memory bank
+ * information instead of hard coding the information in cases where it cannot
+ * be detected automatically.
+ *
+ * @param blob		FDT blob
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_memory_banksize_fdt(const void *blob);
+
+/**
+ * fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram
+ *
+ * Decode the /memory 'reg' property to determine the address and size of the
+ * memory banks. Use this data to populate the global data board info with the
+ * phys address and size of memory banks.
+ *
+ * This function should be called from a boards dram_init_banksize(). This
+ * helper function allows for boards to query the device tree for memory bank
+ * information instead of hard coding the information in cases where it cannot
+ * be detected automatically.
+ *
+ * @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
+ * invalid
+ */
+int fdtdec_setup_memory_banksize(void);
+
+/**
+ * fdtdec_set_ethernet_mac_address() - set MAC address for default interface
+ *
+ * Looks up the default interface via the "ethernet" alias (in the /aliases
+ * node) and stores the given MAC in its "local-mac-address" property. This
+ * is useful on platforms that store the MAC address in a custom location.
+ * Board code can call this in the late init stage to make sure that the
+ * interface device tree node has the right MAC address configured for the
+ * Ethernet uclass to pick it up.
+ *
+ * Typically the FDT passed into this function will be U-Boot's control DTB.
+ * Given that a lot of code may be holding offsets to various nodes in that
+ * tree, this code will only set the "local-mac-address" property in-place,
+ * which means that it needs to exist and have space for the 6-byte address.
+ * This ensures that the operation is non-destructive and does not invalidate
+ * offsets that other drivers may be using.
+ *
+ * @param fdt FDT blob
+ * @param mac buffer containing the MAC address to set
+ * @param size size of MAC address
+ * @return 0 on success or a negative error code on failure
+ */
+int fdtdec_set_ethernet_mac_address(void *fdt, const u8 *mac, size_t size);
+
+/**
+ * fdtdec_set_phandle() - sets the phandle of a given node
+ *
+ * @param blob		FDT blob
+ * @param node		offset in the FDT blob of the node whose phandle is to
+ *			be set
+ * @param phandle	phandle to set for the given node
+ * @return 0 on success or a negative error code on failure
+ */
+static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle)
+{
+	return fdt_setprop_u32(blob, node, "phandle", phandle);
+}
+
+/**
+ * fdtdec_add_reserved_memory() - add or find a reserved-memory node
+ *
+ * If a reserved-memory node already exists for the given carveout, a phandle
+ * for that node will be returned. Otherwise a new node will be created and a
+ * phandle corresponding to it will be returned.
+ *
+ * See Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+ * for details on how to use reserved memory regions.
+ *
+ * As an example, consider the following code snippet:
+ *
+ *     struct fdt_memory fb = {
+ *         .start = 0x92cb3000,
+ *         .end = 0x934b2fff,
+ *     };
+ *     uint32_t phandle;
+ *
+ *     fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle);
+ *
+ * This results in the following subnode being added to the top-level
+ * /reserved-memory node:
+ *
+ *     reserved-memory {
+ *         #address-cells = <0x00000002>;
+ *         #size-cells = <0x00000002>;
+ *         ranges;
+ *
+ *         framebuffer@92cb3000 {
+ *             reg = <0x00000000 0x92cb3000 0x00000000 0x00800000>;
+ *             phandle = <0x0000004d>;
+ *         };
+ *     };
+ *
+ * If the top-level /reserved-memory node does not exist, it will be created.
+ * The phandle returned from the function call can be used to reference this
+ * reserved memory region from other nodes.
+ *
+ * See fdtdec_set_carveout() for a more elaborate example.
+ *
+ * @param blob		FDT blob
+ * @param basename	base name of the node to create
+ * @param carveout	information about the carveout region
+ * @param phandlep	return location for the phandle of the carveout region
+ * @return 0 on success or a negative error code on failure
+ */
+int fdtdec_add_reserved_memory(void *blob, const char *basename,
+			       const struct fdt_memory *carveout,
+			       uint32_t *phandlep);
+
+/**
+ * fdtdec_get_carveout() - reads a carveout from an FDT
+ *
+ * Reads information about a carveout region from an FDT. The carveout is a
+ * referenced by its phandle that is read from a given property in a given
+ * node.
+ *
+ * @param blob		FDT blob
+ * @param node		name of a node
+ * @param name		name of the property in the given node that contains
+ *			the phandle for the carveout
+ * @param index		index of the phandle for which to read the carveout
+ * @param carveout	return location for the carveout information
+ * @return 0 on success or a negative error code on failure
+ */
+int fdtdec_get_carveout(const void *blob, const char *node, const char *name,
+			unsigned int index, struct fdt_memory *carveout);
+
+/**
+ * fdtdec_set_carveout() - sets a carveout region for a given node
+ *
+ * Sets a carveout region for a given node. If a reserved-memory node already
+ * exists for the carveout, the phandle for that node will be reused. If no
+ * such node exists, a new one will be created and a phandle to it stored in
+ * a specified property of the given node.
+ *
+ * As an example, consider the following code snippet:
+ *
+ *     const char *node = "/host1x@50000000/dc@54240000";
+ *     struct fdt_memory fb = {
+ *         .start = 0x92cb3000,
+ *         .end = 0x934b2fff,
+ *     };
+ *
+ *     fdtdec_set_carveout(fdt, node, "memory-region", 0, "framebuffer", &fb);
+ *
+ * dc@54200000 is a display controller and was set up by the bootloader to
+ * scan out the framebuffer specified by "fb". This would cause the following
+ * reserved memory region to be added:
+ *
+ *     reserved-memory {
+ *         #address-cells = <0x00000002>;
+ *         #size-cells = <0x00000002>;
+ *         ranges;
+ *
+ *         framebuffer@92cb3000 {
+ *             reg = <0x00000000 0x92cb3000 0x00000000 0x00800000>;
+ *             phandle = <0x0000004d>;
+ *         };
+ *     };
+ *
+ * A "memory-region" property will also be added to the node referenced by the
+ * offset parameter.
+ *
+ *     host1x@50000000 {
+ *         ...
+ *
+ *         dc@54240000 {
+ *             ...
+ *             memory-region = <0x0000004d>;
+ *             ...
+ *         };
+ *
+ *         ...
+ *     };
+ *
+ * @param blob		FDT blob
+ * @param node		name of the node to add the carveout to
+ * @param prop_name	name of the property in which to store the phandle of
+ *			the carveout
+ * @param index		index of the phandle to store
+ * @param name		base name of the reserved-memory node to create
+ * @param carveout	information about the carveout to add
+ * @return 0 on success or a negative error code on failure
+ */
+int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name,
+			unsigned int index, const char *name,
+			const struct fdt_memory *carveout);
+
+/**
+ * Set up the device tree ready for use
+ */
+int fdtdec_setup(void);
+
+#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
+/**
+ * fdtdec_resetup()  - Set up the device tree again
+ *
+ * The main difference with fdtdec_setup() is that it returns if the fdt has
+ * changed because a better match has been found.
+ * This is typically used for boards that rely on a DM driver to detect the
+ * board type. This function sould be called by the board code after the stuff
+ * needed by board_fit_config_name_match() to operate porperly is available.
+ * If this functions signals that a rescan is necessary, the board code must
+ * unbind all the drivers using dm_uninit() and then rescan the DT with
+ * dm_init_and_scan().
+ *
+ * @param rescan Returns a flag indicating that fdt has changed and rescanning
+ *               the fdt is required
+ *
+ * @return 0 if OK, -ve on error
+ */
+int fdtdec_resetup(int *rescan);
+#endif
+
+/**
+ * Board-specific FDT initialization. Returns the address to a device tree blob.
+ * Called when CONFIG_OF_BOARD is defined, or if CONFIG_OF_SEPARATE is defined
+ * and the board implements it.
+ */
+void *board_fdt_blob_setup(void);
+
+/*
+ * Decode the size of memory
+ *
+ * RAM size is normally set in a /memory node and consists of a list of
+ * (base, size) cells in the 'reg' property. This information is used to
+ * determine the total available memory as well as the address and size
+ * of each bank.
+ *
+ * Optionally the memory configuration can vary depending on a board id,
+ * typically read from strapping resistors or an EEPROM on the board.
+ *
+ * Finally, memory size can be detected (within certain limits) by probing
+ * the available memory. It is safe to do so within the limits provides by
+ * the board's device tree information. This makes it possible to produce
+ * boards with different memory sizes, where the device tree specifies the
+ * maximum memory configuration, and the smaller memory configuration is
+ * probed.
+ *
+ * This function decodes that information, returning the memory base address,
+ * size and bank information. See the memory.txt binding for full
+ * documentation.
+ *
+ * @param blob		Device tree blob
+ * @param area		Name of node to check (NULL means "/memory")
+ * @param board_id	Board ID to look up
+ * @param basep		Returns base address of first memory bank (NULL to
+ *			ignore)
+ * @param sizep		Returns total memory size (NULL to ignore)
+ * @param bd		Updated with the memory bank information (NULL to skip)
+ * @return 0 if OK, -ve on error
+ */
+int fdtdec_decode_ram_size(const void *blob, const char *area, int board_id,
+			   phys_addr_t *basep, phys_size_t *sizep,
+			   struct bd_info *bd);
+
+#endif
diff --git a/include/fis.h b/include/fis.h
new file mode 100644
index 0000000..419807f
--- /dev/null
+++ b/include/fis.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ *		Dave Liu <daveliu@freescale.com>
+ */
+
+#ifndef __FIS_H__
+#define __FIS_H__
+/*
+* Register - Host to Device FIS
+*/
+typedef struct sata_fis_h2d {
+	u8 fis_type;
+	u8 pm_port_c;
+	u8 command;
+	u8 features;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 device;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 features_exp;
+	u8 sector_count;
+	u8 sector_count_exp;
+	u8 res1;
+	u8 control;
+	u8 res2[4];
+} __attribute__ ((packed)) sata_fis_h2d_t;
+
+/*
+* Register - Host to Device FIS for read/write FPDMA queued
+*/
+typedef struct sata_fis_h2d_ncq {
+	u8 fis_type;
+	u8 pm_port_c;
+	u8 command;
+	u8 sector_count_low;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 device;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 sector_count_high;
+	u8 tag;
+	u8 res1;
+	u8 res2;
+	u8 control;
+	u8 res3[4];
+} __attribute__ ((packed)) sata_fis_h2d_ncq_t;
+
+/*
+* Register - Device to Host FIS
+*/
+typedef struct sata_fis_d2h {
+	u8 fis_type;
+	u8 pm_port_i;
+	u8 status;
+	u8 error;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 device;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 res1;
+	u8 sector_count;
+	u8 sector_count_exp;
+	u8 res2[2];
+	u8 res3[4];
+} __attribute__ ((packed)) sata_fis_d2h_t;
+
+/*
+* DMA Setup - Device to Host or Host to Device FIS
+*/
+typedef struct sata_fis_dma_setup {
+	u8 fis_type;
+	u8 pm_port_dir_int_act;
+	u8 res1;
+	u8 res2;
+	u32 dma_buffer_id_low;
+	u32 dma_buffer_id_high;
+	u32 res3;
+	u32 dma_buffer_offset;
+	u32 dma_transfer_count;
+	u32 res4;
+} __attribute__ ((packed)) sata_fis_dma_setup_t;
+
+/*
+* PIO Setup - Device to Host FIS
+*/
+typedef struct sata_fis_pio_setup {
+	u8 fis_type;
+	u8 pm_port_dir_int;
+	u8 status;
+	u8 error;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 res1;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 res2;
+	u8 sector_count;
+	u8 sector_count_exp;
+	u8 res3;
+	u8 e_status;
+	u16 transfer_count;
+	u16 res4;
+} __attribute__ ((packed)) sata_fis_pio_setup_t;
+
+/*
+* Data - Host to Device or Device to Host FIS
+*/
+typedef struct sata_fis_data {
+	u8 fis_type;
+	u8 pm_port;
+	u8 res1;
+	u8 res2;
+	u32 data[2048];
+} __attribute__ ((packed)) sata_fis_data_t;
+
+/* fis_type - SATA FIS type
+ */
+enum sata_fis_type {
+	SATA_FIS_TYPE_REGISTER_H2D		= 0x27,
+	SATA_FIS_TYPE_REGISTER_D2H		= 0x34,
+	SATA_FIS_TYPE_DMA_ACT_D2H		= 0x39,
+	SATA_FIS_TYPE_DMA_SETUP_BI		= 0x41,
+	SATA_FIS_TYPE_DATA_BI			= 0x46,
+	SATA_FIS_TYPE_BIST_ACT_BI		= 0x58,
+	SATA_FIS_TYPE_PIO_SETUP_D2H		= 0x5F,
+	SATA_FIS_TYPE_SET_DEVICE_BITS_D2H	= 0xA1,
+};
+
+#endif	/* __FIS_H__ */
diff --git a/include/flash.h b/include/flash.h
new file mode 100644
index 0000000..70ab435
--- /dev/null
+++ b/include/flash.h
@@ -0,0 +1,508 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef _FLASH_H_
+#define _FLASH_H_
+
+#ifndef CONFIG_SYS_MAX_FLASH_SECT
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH Info: contains chip specific data, per FLASH bank
+ */
+
+typedef struct {
+	ulong	size;			/* total bank size in bytes		*/
+	ushort	sector_count;		/* number of erase units		*/
+	ulong	flash_id;		/* combined device & manufacturer code	*/
+	ulong	start[CONFIG_SYS_MAX_FLASH_SECT];   /* virtual sector start address */
+	uchar	protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status	*/
+#ifdef CONFIG_SYS_FLASH_CFI
+	uchar	portwidth;		/* the width of the port		*/
+	uchar	chipwidth;		/* the width of the chip		*/
+	ushort	buffer_size;		/* # of bytes in write buffer		*/
+	ulong	erase_blk_tout;		/* maximum block erase timeout		*/
+	ulong	write_tout;		/* maximum write timeout		*/
+	ulong	buffer_write_tout;	/* maximum buffer write timeout		*/
+	ushort	vendor;			/* the primary vendor id		*/
+	ushort	cmd_reset;		/* vendor specific reset command	*/
+	uchar   cmd_erase_sector;	/* vendor specific erase sect. command	*/
+	ushort	interface;		/* used for x8/x16 adjustments		*/
+	ushort	legacy_unlock;		/* support Intel legacy (un)locking	*/
+	ushort	manufacturer_id;	/* manufacturer id			*/
+	ushort	device_id;		/* device id				*/
+	ushort	device_id2;		/* extended device id			*/
+	ushort	ext_addr;		/* extended query table address		*/
+	ushort	cfi_version;		/* cfi version				*/
+	ushort	cfi_offset;		/* offset for cfi query			*/
+	ulong   addr_unlock1;		/* unlock address 1 for AMD flash roms  */
+	ulong   addr_unlock2;		/* unlock address 2 for AMD flash roms  */
+	uchar   sr_supported;		/* status register supported            */
+	const char *name;		/* human-readable name	                */
+#endif
+#ifdef CONFIG_MTD
+	struct mtd_info *mtd;
+#endif
+#ifdef CONFIG_CFI_FLASH			/* DM-specific parts */
+	struct udevice *dev;
+	phys_addr_t base;
+#endif
+} flash_info_t;
+
+extern flash_info_t flash_info[]; /* info for FLASH chips	*/
+
+typedef unsigned long flash_sect_t;
+
+/*
+ * Values for the width of the port
+ */
+#define FLASH_CFI_8BIT		0x01
+#define FLASH_CFI_16BIT		0x02
+#define FLASH_CFI_32BIT		0x04
+#define FLASH_CFI_64BIT		0x08
+/*
+ * Values for the width of the chip
+ */
+#define FLASH_CFI_BY8		0x01
+#define FLASH_CFI_BY16		0x02
+#define FLASH_CFI_BY32		0x04
+#define FLASH_CFI_BY64		0x08
+/*
+ * Values for the flash device interface
+ */
+#define FLASH_CFI_X8		0x00
+#define FLASH_CFI_X16		0x01
+#define FLASH_CFI_X8X16		0x02
+#define FLASH_CFI_X16X32	0x05
+
+/* convert between bit value and numeric value */
+#define CFI_FLASH_SHIFT_WIDTH	3
+
+/* Prototypes */
+
+extern unsigned long flash_init (void);
+extern void flash_print_info (flash_info_t *);
+extern int flash_erase	(flash_info_t *, int, int);
+extern int flash_sect_erase (ulong addr_first, ulong addr_last);
+extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
+extern int flash_sect_roundb (ulong *addr);
+extern unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect);
+extern void flash_set_verbose(uint);
+
+/* common/flash.c */
+extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
+extern int flash_write (char *, ulong, ulong);
+extern flash_info_t *addr2info (ulong);
+extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+
+/* drivers/mtd/cfi_mtd.c */
+#ifdef CONFIG_FLASH_CFI_MTD
+extern int cfi_mtd_init(void);
+#endif
+
+/* board/?/flash.c */
+#if defined(CONFIG_SYS_FLASH_PROTECTION)
+extern int flash_real_protect(flash_info_t *info, long sector, int prot);
+extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len);
+extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len);
+#endif	/* CONFIG_SYS_FLASH_PROTECTION */
+
+#ifdef CONFIG_FLASH_CFI_LEGACY
+extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info);
+extern int jedec_flash_match(flash_info_t *info, ulong base);
+#define CFI_CMDSET_AMD_LEGACY		0xFFF0
+#endif
+
+/*-----------------------------------------------------------------------
+ * return codes from flash_write():
+ */
+#define ERR_OK				0
+#define ERR_TIMEOUT			1
+#define ERR_NOT_ERASED			2
+#define ERR_PROTECTED			4
+#define ERR_INVAL			8
+#define ERR_ALIGN			16
+#define ERR_UNKNOWN_FLASH_VENDOR	32
+#define ERR_UNKNOWN_FLASH_TYPE		64
+#define ERR_PROG_ERROR			128
+#define ERR_ABORTED			256
+
+/*-----------------------------------------------------------------------
+ * Protection Flags for flash_protect():
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+#define	FLAG_PROTECT_INVALID	0x03
+/*-----------------------------------------------------------------------
+ * Set Environment according to label:
+ */
+#define	FLAG_SETENV		0x80
+
+/*-----------------------------------------------------------------------
+ * Device IDs
+ */
+
+/* Manufacturers inside bank 0 have ids like 0x00xx00xx */
+#define AMD_MANUFACT	0x00010001	/* AMD	   manuf. ID in D23..D16, D7..D0 */
+#define FUJ_MANUFACT	0x00040004	/* FUJITSU manuf. ID in D23..D16, D7..D0 */
+#define ATM_MANUFACT	0x001F001F	/* ATMEL */
+#define STM_MANUFACT	0x00200020	/* STM (Thomson) manuf. ID in D23.. -"- */
+#define SST_MANUFACT	0x00BF00BF	/* SST	   manuf. ID in D23..D16, D7..D0 */
+#define MT_MANUFACT	0x00890089	/* MT	   manuf. ID in D23..D16, D7..D0 */
+#define INTEL_MANUFACT	0x00890089	/* INTEL   manuf. ID in D23..D16, D7..D0 */
+#define INTEL_ALT_MANU	0x00B000B0	/* alternate INTEL namufacturer ID	*/
+#define MX_MANUFACT	0x00C200C2	/* MXIC	   manuf. ID in D23..D16, D7..D0 */
+#define TOSH_MANUFACT	0x00980098	/* TOSHIBA manuf. ID in D23..D16, D7..D0 */
+#define MT2_MANUFACT	0x002C002C	/* alternate MICRON manufacturer ID*/
+#define EXCEL_MANUFACT	0x004A004A	/* Excel Semiconductor			*/
+#define AMIC_MANUFACT	0x00370037	/* AMIC    manuf. ID in D23..D16, D7..D0 */
+#define WINB_MANUFACT	0x00DA00DA	/* Winbond manuf. ID in D23..D16, D7..D0 */
+#define EON_ALT_MANU	0x001C001C	/* EON     manuf. ID in D23..D16, D7..D0 */
+
+/* Manufacturers inside bank 1 have ids like 0x01xx01xx */
+#define EON_MANUFACT	0x011C011C	/* EON     manuf. ID in D23..D16, D7..D0 */
+
+/* Manufacturers inside bank 2 have ids like 0x02xx02xx */
+
+					/* Micron Technologies (INTEL compat.)	*/
+#define MT_ID_28F400_T	0x44704470	/* 28F400B3 ID ( 4 M, top boot sector)	*/
+#define MT_ID_28F400_B	0x44714471	/* 28F400B3 ID ( 4 M, bottom boot sect) */
+
+#define AMD_ID_LV040B	0x4F		/* 29LV040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define AMD_ID_F033C	0xA3		/* 29LV033C ID				*/
+					/* 32 Mbit, 4Mbits x 8,			*/
+					/* 64 64K x 8 uniform sectors		*/
+#define AMD_ID_F065D	0x93		/* 29LV065D ID				*/
+					/* 64 Mbit, 8Mbits x 8,			*/
+					/* 126 64K x 8 uniform sectors		*/
+#define ATM_ID_LV040	0x13		/* 29LV040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define AMD_ID_F040B	0xA4		/* 29F040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define STM_ID_M29W040B 0xE3		/* M29W040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define AMD_ID_F080B	0xD5		/* 29F080  ID  ( 1 M)			*/
+					/* 8 Mbit, 512K x 16,			*/
+					/* 8 64K x 16 uniform sectors		*/
+#define AMD_ID_F016D	0xAD		/* 29F016  ID  ( 2 M x 8)		*/
+#define AMD_ID_F032B	0x41		/* 29F032  ID  ( 4 M x 8)		*/
+#define AMD_ID_LV116DT	0xC7		/* 29LV116DT   ( 2 M x 8, top boot sect) */
+#define AMD_ID_LV116DB	0x4C		/* 29LV116DB   ( 2 M x 8, bottom boot sect) */
+#define AMD_ID_LV016B	0xc8		/* 29LV016 ID  ( 2 M x 8)		*/
+
+#define AMD_ID_PL160CB	0x22452245	/* 29PL160CB ID (16 M, bottom boot sect */
+
+#define AMD_ID_LV400T	0x22B922B9	/* 29LV400T ID ( 4 M, top boot sector)	*/
+#define AMD_ID_LV400B	0x22BA22BA	/* 29LV400B ID ( 4 M, bottom boot sect) */
+
+#define AMD_ID_LV033C	0xA3		/* 29LV033C ID ( 4 M x 8)		*/
+#define AMD_ID_LV065D	0x93		/* 29LV065D ID ( 8 M x 8)		*/
+
+#define AMD_ID_LV800T	0x22DA22DA	/* 29LV800T ID ( 8 M, top boot sector)	*/
+#define AMD_ID_LV800B	0x225B225B	/* 29LV800B ID ( 8 M, bottom boot sect) */
+
+#define AMD_ID_LV160T	0x22C422C4	/* 29LV160T ID (16 M, top boot sector)	*/
+#define AMD_ID_LV160B	0x22492249	/* 29LV160B ID (16 M, bottom boot sect) */
+
+#define AMD_ID_DL163T	0x22282228	/* 29DL163T ID (16 M, top boot sector)	*/
+#define AMD_ID_DL163B	0x222B222B	/* 29DL163B ID (16 M, bottom boot sect) */
+
+#define AMD_ID_LV320T	0x22F622F6	/* 29LV320T ID (32 M, top boot sector)	*/
+#define MX_ID_LV320T	0x22A722A7	/* 29LV320T by Macronix, AMD compatible */
+#define AMD_ID_LV320B	0x22F922F9	/* 29LV320B ID (32 M, bottom boot sect) */
+#define MX_ID_LV320B	0x22A822A8	/* 29LV320B by Macronix, AMD compatible */
+
+#define AMD_ID_DL322T	0x22552255	/* 29DL322T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL322B	0x22562256	/* 29DL322B ID (32 M, bottom boot sect) */
+#define AMD_ID_DL323T	0x22502250	/* 29DL323T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL323B	0x22532253	/* 29DL323B ID (32 M, bottom boot sect) */
+#define AMD_ID_DL324T	0x225C225C	/* 29DL324T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL324B	0x225F225F	/* 29DL324B ID (32 M, bottom boot sect) */
+
+#define AMD_ID_DL640	0x227E227E	/* 29DL640D ID (64 M, dual boot sectors)*/
+#define AMD_ID_MIRROR	0x227E227E	/* 1st ID word for MirrorBit family */
+#define AMD_ID_DL640G_2 0x22022202	/* 2nd ID word for AM29DL640G  at 0x38 */
+#define AMD_ID_DL640G_3 0x22012201	/* 3rd ID word for AM29DL640G  at 0x3c */
+#define AMD_ID_LV640U_2 0x220C220C	/* 2nd ID word for AM29LV640M  at 0x38 */
+#define AMD_ID_LV640U_3 0x22012201	/* 3rd ID word for AM29LV640M  at 0x3c */
+#define AMD_ID_LV640MT_2 0x22102210	/* 2nd ID word for AM29LV640MT at 0x38 */
+#define AMD_ID_LV640MT_3 0x22012201	/* 3rd ID word for AM29LV640MT at 0x3c */
+#define AMD_ID_LV640MB_2 0x22102210	/* 2nd ID word for AM29LV640MB at 0x38 */
+#define AMD_ID_LV640MB_3 0x22002200	/* 3rd ID word for AM29LV640MB at 0x3c */
+#define AMD_ID_LV128U_2 0x22122212	/* 2nd ID word for AM29LV128M  at 0x38 */
+#define AMD_ID_LV128U_3 0x22002200	/* 3rd ID word for AM29LV128M  at 0x3c */
+#define AMD_ID_LV256U_2 0x22122212	/* 2nd ID word for AM29LV256M  at 0x38 */
+#define AMD_ID_LV256U_3 0x22012201	/* 3rd ID word for AM29LV256M  at 0x3c */
+#define AMD_ID_GL064M_2 0x22132213	/* 2nd ID word for S29GL064M-R6 */
+#define AMD_ID_GL064M_3 0x22012201	/* 3rd ID word for S29GL064M-R6 */
+#define AMD_ID_GL064MT_2 0x22102210	/* 2nd ID word for S29GL064M-R3 (top boot sector) */
+#define AMD_ID_GL064MT_3 0x22012201	/* 3rd ID word for S29GL064M-R3 (top boot sector) */
+#define AMD_ID_GL128N_2	0x22212221	/* 2nd ID word for S29GL128N */
+#define AMD_ID_GL128N_3	0x22012201	/* 3rd ID word for S29GL128N */
+
+
+#define AMD_ID_LV320B_2 0x221A221A	/* 2d ID word for AM29LV320MB at 0x38 */
+#define AMD_ID_LV320B_3 0x22002200	/* 3d ID word for AM29LV320MB at 0x3c */
+
+#define AMD_ID_LV640U	0x22D722D7	/* 29LV640U ID (64 M, uniform sectors)	*/
+#define AMD_ID_LV650U	0x22D722D7	/* 29LV650U ID (64 M, uniform sectors)	*/
+
+#define ATM_ID_BV1614	0x000000C0	/* 49BV1614  ID */
+#define ATM_ID_BV1614A	0x000000C8	/* 49BV1614A ID */
+#define ATM_ID_BV6416	0x000000D6	/* 49BV6416  ID */
+
+#define FUJI_ID_29F800BA  0x22582258	/* MBM29F800BA ID  (8M) */
+#define FUJI_ID_29F800TA  0x22D622D6	/* MBM29F800TA ID  (8M) */
+#define FUJI_ID_29LV650UE 0x22d722d7	/* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */
+
+#define SST_ID_xF200A	0x27892789	/* 39xF200A ID ( 2M = 128K x 16 )	*/
+#define SST_ID_xF400A	0x27802780	/* 39xF400A ID ( 4M = 256K x 16 )	*/
+#define SST_ID_xF800A	0x27812781	/* 39xF800A ID ( 8M = 512K x 16 )	*/
+#define SST_ID_xF160A	0x27822782	/* 39xF800A ID (16M =	1M x 16 )	*/
+#define SST_ID_xF1601	0x234B234B	/* 39xF1601 ID (16M =	1M x 16 )	*/
+#define SST_ID_xF1602	0x234A234A	/* 39xF1602 ID (16M =	1M x 16 )	*/
+#define SST_ID_xF3201	0x235B235B	/* 39xF3201 ID (32M =	2M x 16 )	*/
+#define SST_ID_xF3202	0x235A235A	/* 39xF3202 ID (32M =	2M x 16 )	*/
+#define SST_ID_xF6401	0x236B236B	/* 39xF6401 ID (64M =	4M x 16 )	*/
+#define SST_ID_xF6402	0x236A236A	/* 39xF6402 ID (64M =	4M x 16 )	*/
+#define SST_ID_xF020	0xBFD6BFD6	/* 39xF020 ID (256KB = 2Mbit x 8)	*/
+#define SST_ID_xF040	0xBFD7BFD7	/* 39xF040 ID (512KB = 4Mbit x 8)	*/
+
+#define STM_ID_F040B	0xE2		/* M29F040B ID ( 4M = 512K x 8	)	*/
+					/* 8 64K x 8 uniform sectors		*/
+
+#define STM_ID_x800AB	0x005B005B	/* M29W800AB ID (8M = 512K x 16 )	*/
+#define STM_ID_29W320DT 0x22CA22CA	/* M29W320DT ID (32 M, top boot sector) */
+#define STM_ID_29W320DB 0x22CB22CB	/* M29W320DB ID (32 M, bottom boot sect)	*/
+#define STM_ID_29W320ET 0x22562256	/* M29W320ET ID (32 M, top boot sector) */
+#define STM_ID_29W320EB 0x22572257	/* M29W320EB ID (32 M, bottom boot sect)*/
+#define STM_ID_29W040B	0x00E300E3	/* M29W040B ID (4M = 512K x 8)	*/
+#define FLASH_PSD4256GV 0x00E9		/* PSD4256 Flash and CPLD combination	*/
+
+#define INTEL_ID_28F016S    0x66a066a0	/* 28F016S[VS] ID (16M = 512k x 16)	*/
+#define INTEL_ID_28F800B3T  0x88928892	/*  8M = 512K x 16 top boot sector	*/
+#define INTEL_ID_28F800B3B  0x88938893	/*  8M = 512K x 16 bottom boot sector	*/
+#define INTEL_ID_28F160B3T  0x88908890	/*  16M = 1M x 16 top boot sector	*/
+#define INTEL_ID_28F160B3B  0x88918891	/*  16M = 1M x 16 bottom boot sector	*/
+#define INTEL_ID_28F320B3T  0x88968896	/*  32M = 2M x 16 top boot sector	*/
+#define INTEL_ID_28F320B3B  0x88978897	/*  32M = 2M x 16 bottom boot sector	*/
+#define INTEL_ID_28F640B3T  0x88988898	/*  64M = 4M x 16 top boot sector	*/
+#define INTEL_ID_28F640B3B  0x88998899	/*  64M = 4M x 16 bottom boot sector	*/
+#define INTEL_ID_28F160F3B  0x88F488F4	/*  16M = 1M x 16 bottom boot sector	*/
+
+#define INTEL_ID_28F800C3T  0x88C088C0	/*  8M = 512K x 16 top boot sector	*/
+#define INTEL_ID_28F800C3B  0x88C188C1	/*  8M = 512K x 16 bottom boot sector	*/
+#define INTEL_ID_28F160C3T  0x88C288C2	/*  16M = 1M x 16 top boot sector	*/
+#define INTEL_ID_28F160C3B  0x88C388C3	/*  16M = 1M x 16 bottom boot sector	*/
+#define INTEL_ID_28F320C3T  0x88C488C4	/*  32M = 2M x 16 top boot sector	*/
+#define INTEL_ID_28F320C3B  0x88C588C5	/*  32M = 2M x 16 bottom boot sector	*/
+#define INTEL_ID_28F640C3T  0x88CC88CC	/*  64M = 4M x 16 top boot sector	*/
+#define INTEL_ID_28F640C3B  0x88CD88CD	/*  64M = 4M x 16 bottom boot sector	*/
+
+#define INTEL_ID_28F128J3   0x89188918	/*  16M = 8M x 16 x 128 */
+#define INTEL_ID_28F320J5   0x00140014	/*  32M = 128K x  32	*/
+#define INTEL_ID_28F640J5   0x00150015	/*  64M = 128K x  64	*/
+#define INTEL_ID_28F320J3A  0x00160016	/*  32M = 128K x  32	*/
+#define INTEL_ID_28F640J3A  0x00170017	/*  64M = 128K x  64	*/
+#define INTEL_ID_28F128J3A  0x00180018	/* 128M = 128K x 128	*/
+#define INTEL_ID_28F256J3A  0x001D001D	/* 256M = 128K x 256	*/
+#define INTEL_ID_28F256L18T 0x880D880D	/* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F64K3    0x88018801	/*  64M =  32K x 255 + 32k x 4 */
+#define INTEL_ID_28F128K3   0x88028802	/* 128M =  64K x 255 + 32k x 4 */
+#define INTEL_ID_28F256K3   0x88038803	/* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F64P30T  0x88178817	/*  64M =  32K x 255 + 32k x 4 */
+#define INTEL_ID_28F64P30B  0x881A881A	/*  64M =  32K x 255 + 32k x 4 */
+#define INTEL_ID_28F128P30T 0x88188818	/* 128M =  64K x 255 + 32k x 4 */
+#define INTEL_ID_28F128P30B 0x881B881B	/* 128M =  64K x 255 + 32k x 4 */
+#define INTEL_ID_28F256P30T 0x88198819	/* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F256P30B 0x881C881C	/* 256M = 128K x 255 + 32k x 4 */
+
+#define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)	*/
+#define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)	*/
+
+/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
+#define SHARP_ID_28F016SCL  0xAAAAAAAA	/* LH28F016SCT-L95 2Mx8, 32 64k blocks	*/
+#define SHARP_ID_28F016SCZ  0xA0A0A0A0	/* LH28F016SCT-Z4  2Mx8, 32 64k blocks	*/
+#define SHARP_ID_28F008SC   0xA6A6A6A6	/* LH28F008SCT-L12 1Mx8, 16 64k blocks	*/
+					/* LH28F008SCR-L85 1Mx8, 16 64k blocks	*/
+
+#define TOSH_ID_FVT160	0xC2		/* TC58FVT160 ID (16 M, top )		*/
+#define TOSH_ID_FVB160	0x43		/* TC58FVT160 ID (16 M, bottom )	*/
+#define NUMONYX_256MBIT	0x8922		/* Numonyx P33/30 256MBit 65nm	*/
+
+/*-----------------------------------------------------------------------
+ * Internal FLASH identification codes
+ *
+ * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
+ */
+
+#define FLASH_AM040	0x0001		/* AMD Am29F040B, Am29LV040B		*/
+					/* Bright Micro BM29F040		*/
+					/* Fujitsu MBM29F040A			*/
+					/* STM M29W040B				*/
+					/* SGS Thomson M29F040B			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define FLASH_AM400T	0x0002		/* AMD AM29LV400			*/
+#define FLASH_AM400B	0x0003
+#define FLASH_AM800T	0x0004		/* AMD AM29LV800			*/
+#define FLASH_AM800B	0x0005
+#define FLASH_AM116DT	0x0026		/* AMD AM29LV116DT (2Mx8bit) */
+#define FLASH_AM116DB	0x0027		/* AMD AM29LV116DB (2Mx8bit) */
+#define FLASH_AM160T	0x0006		/* AMD AM29LV160			*/
+#define FLASH_AM160LV	0x0046		/* AMD29LV160DB (2M = 2Mx8bit ) */
+#define FLASH_AM160B	0x0007
+#define FLASH_AM320T	0x0008		/* AMD AM29LV320			*/
+#define FLASH_AM320B	0x0009
+
+#define FLASH_AM080	0x000A		/* AMD Am29F080B			*/
+					/* 16 64K x 8 uniform sectors		*/
+
+#define FLASH_AMDL322T	0x0010		/* AMD AM29DL322			*/
+#define FLASH_AMDL322B	0x0011
+#define FLASH_AMDL323T	0x0012		/* AMD AM29DL323			*/
+#define FLASH_AMDL323B	0x0013
+#define FLASH_AMDL324T	0x0014		/* AMD AM29DL324			*/
+#define FLASH_AMDL324B	0x0015
+
+#define FLASH_AMDLV033C 0x0018
+#define FLASH_AMDLV065D 0x001A
+
+#define FLASH_AMDL640	0x0016		/* AMD AM29DL640D			*/
+#define FLASH_AMD016	0x0018		/* AMD AM29F016D			*/
+#define FLASH_AMDL640MB 0x0019		/* AMD AM29LV640MB (64M, bottom boot sect)*/
+#define FLASH_AMDL640MT 0x001A		/* AMD AM29LV640MT (64M, top boot sect) */
+
+#define FLASH_SST200A	0x0040		/* SST 39xF200A ID (  2M = 128K x 16 )	*/
+#define FLASH_SST400A	0x0042		/* SST 39xF400A ID (  4M = 256K x 16 )	*/
+#define FLASH_SST800A	0x0044		/* SST 39xF800A ID (  8M = 512K x 16 )	*/
+#define FLASH_SST160A	0x0046		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
+#define FLASH_SST320	0x0048		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
+#define FLASH_SST640	0x004A		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
+#define FLASH_SST020	0x0024		/* SST 39xF020 ID (256KB = 2Mbit x 8 )	*/
+#define FLASH_SST040	0x000E		/* SST 39xF040 ID (512KB = 4Mbit x 8 )	*/
+
+#define FLASH_STM800AB	0x0051		/* STM M29WF800AB  (  8M = 512K x 16 )	*/
+#define FLASH_STMW320DT 0x0052		/* STM M29W320DT   (32 M, top boot sector)	*/
+#define FLASH_STMW320DB 0x0053		/* STM M29W320DB   (32 M, bottom boot sect)*/
+#define FLASH_STM320DB	0x00CB		/* STM M29W320DB (4M = 64K x 64, bottom)*/
+#define FLASH_STM800DT	0x00D7		/* STM M29W800DT (1M = 64K x 16, top)	*/
+#define FLASH_STM800DB	0x005B		/* STM M29W800DB (1M = 64K x 16, bottom)*/
+
+#define FLASH_MCHP100T	0x0060		/* MCHP internal (1M = 64K x 16) */
+#define FLASH_MCHP100B	0x0061		/* MCHP internal (1M = 64K x 16) */
+
+#define FLASH_28F400_T	0x0062		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
+#define FLASH_28F400_B	0x0063		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
+
+#define FLASH_INTEL800T 0x0074		/* INTEL 28F800B3T (  8M = 512K x 16 )	*/
+#define FLASH_INTEL800B 0x0075		/* INTEL 28F800B3B (  8M = 512K x 16 )	*/
+#define FLASH_INTEL160T 0x0076		/* INTEL 28F160B3T ( 16M =  1 M x 16 )	*/
+#define FLASH_INTEL160B 0x0077		/* INTEL 28F160B3B ( 16M =  1 M x 16 )	*/
+#define FLASH_INTEL320T 0x0078		/* INTEL 28F320B3T ( 32M =  2 M x 16 )	*/
+#define FLASH_INTEL320B 0x0079		/* INTEL 28F320B3B ( 32M =  2 M x 16 )	*/
+#define FLASH_INTEL640T 0x007A		/* INTEL 28F320B3T ( 64M =  4 M x 16 )	*/
+#define FLASH_INTEL640B 0x007B		/* INTEL 28F320B3B ( 64M =  4 M x 16 )	*/
+
+#define FLASH_28F008S5	0x0080		/* Intel 28F008S5  (  1M =  64K x 16 )	*/
+#define FLASH_28F016SV	0x0081		/* Intel 28F016SV  ( 16M = 512k x 32 )	*/
+#define FLASH_28F800_B	0x0083		/* Intel E28F800B  (  1M = ? )		*/
+#define FLASH_AM29F800B 0x0084		/* AMD Am29F800BB  (  1M = ? )		*/
+#define FLASH_28F320J5	0x0085		/* Intel 28F320J5  (  4M = 128K x 32 )	*/
+#define FLASH_28F160S3	0x0086		/* Intel 28F160S3  ( 16M = 512K x 32 )	*/
+#define FLASH_28F320S3	0x0088		/* Intel 28F320S3  ( 32M = 512K x 64 )	*/
+#define FLASH_AM640U	0x0090		/* AMD Am29LV640U  ( 64M = 4M x 16 )	*/
+#define FLASH_AM033C	0x0091		/* AMD AM29LV033   ( 32M = 4M x 8 )	*/
+#define FLASH_LH28F016SCT 0x0092	/* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
+#define FLASH_28F160F3B 0x0093		/* Intel 28F160F3B ( 16M = 1M x 16 )	*/
+#define FLASH_AM065D	0x0093
+
+#define FLASH_28F640J5	0x0099		/* INTEL 28F640J5  ( 64M = 128K x  64)	*/
+
+#define FLASH_28F800C3T 0x009A		/* Intel 28F800C3T (  8M = 512K x 16 )	*/
+#define FLASH_28F800C3B 0x009B		/* Intel 28F800C3B (  8M = 512K x 16 )	*/
+#define FLASH_28F160C3T 0x009C		/* Intel 28F160C3T ( 16M = 1M x 16 )	*/
+#define FLASH_28F160C3B 0x009D		/* Intel 28F160C3B ( 16M = 1M x 16 )	*/
+#define FLASH_28F320C3T 0x009E		/* Intel 28F320C3T ( 32M = 2M x 16 )	*/
+#define FLASH_28F320C3B 0x009F		/* Intel 28F320C3B ( 32M = 2M x 16 )	*/
+#define FLASH_28F640C3T 0x00A0		/* Intel 28F640C3T ( 64M = 4M x 16 )	*/
+#define FLASH_28F640C3B 0x00A1		/* Intel 28F640C3B ( 64M = 4M x 16 )	*/
+#define FLASH_AMLV320U	0x00A2		/* AMD 29LV320M	   ( 32M = 2M x 16 )	*/
+
+#define FLASH_AM033	0x00A3		/* AMD AmL033C90V1   (32M = 4M x 8)	*/
+#define FLASH_AM065	0x0093		/* AMD AmL065DU12RI  (64M = 8M x 8)	*/
+#define FLASH_AT040	0x00A5		/* Amtel AT49LV040   (4M = 512K x 8)	*/
+
+#define FLASH_AMLV640U	0x00A4		/* AMD 29LV640M	   ( 64M = 4M x 16 )	*/
+#define FLASH_AMLV128U	0x00A6		/* AMD 29LV128M	   ( 128M = 8M x 16 )	*/
+#define FLASH_AMLV320B	0x00A7		/* AMD 29LV320MB   ( 32M = 2M x 16 )	*/
+#define FLASH_AMLV320T	0x00A8		/* AMD 29LV320MT   ( 32M = 2M x 16 )	*/
+#define FLASH_AMLV256U	0x00AA		/* AMD 29LV256M	   ( 256M = 16M x 16 )	*/
+#define FLASH_MXLV320B	0x00AB		/* MX  29LV320MB   ( 32M = 2M x 16 )	*/
+#define FLASH_MXLV320T	0x00AC		/* MX  29LV320MT   ( 32M = 2M x 16 )	*/
+#define FLASH_28F256L18T 0x00B0		/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
+#define FLASH_AMDL163T	0x00B2		/* AMD AM29DL163T (2M x 16 )			*/
+#define FLASH_AMDL163B	0x00B3
+#define FLASH_28F64K3	0x00B4		/* Intel 28F64K3   (  64M)		*/
+#define FLASH_28F128K3	0x00B6		/* Intel 28F128K3  ( 128M = 8M x 16 )	*/
+#define FLASH_28F256K3	0x00B8		/* Intel 28F256K3  ( 256M = 16M x 16 )	*/
+
+#define FLASH_28F320J3A 0x00C0		/* INTEL 28F320J3A ( 32M = 128K x  32)	*/
+#define FLASH_28F640J3A 0x00C2		/* INTEL 28F640J3A ( 64M = 128K x  64)	*/
+#define FLASH_28F128J3A 0x00C4		/* INTEL 28F128J3A (128M = 128K x 128)	*/
+#define FLASH_28F256J3A 0x00C6		/* INTEL 28F256J3A (256M = 128K x 256)	*/
+
+#define FLASH_FUJLV650	0x00D0		/* Fujitsu MBM 29LV650UE/651UE		*/
+#define FLASH_MT28S4M16LC 0x00E1	/* Micron MT28S4M16LC			*/
+#define FLASH_S29GL064M 0x00F0		/* Spansion S29GL064M-R6		*/
+#define FLASH_S29GL128N 0x00F1		/* Spansion S29GL128N			*/
+
+#define FLASH_STM32	0x00F2		/* STM32 Embedded Flash */
+
+#define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
+
+
+/* manufacturer offsets
+ */
+#define FLASH_MAN_AMD	0x00000000	/* AMD					*/
+#define FLASH_MAN_FUJ	0x00010000	/* Fujitsu				*/
+#define FLASH_MAN_BM	0x00020000	/* Bright Microelectronics		*/
+#define FLASH_MAN_MX	0x00030000	/* MXIC					*/
+#define FLASH_MAN_STM	0x00040000
+#define FLASH_MAN_TOSH	0x00050000	/* Toshiba				*/
+#define FLASH_MAN_EXCEL 0x00060000	/* Excel Semiconductor			*/
+#define FLASH_MAN_SST	0x00100000
+#define FLASH_MAN_INTEL 0x00300000
+#define FLASH_MAN_MT	0x00400000
+#define FLASH_MAN_SHARP 0x00500000
+#define FLASH_MAN_ATM	0x00600000
+#define FLASH_MAN_CFI	0x01000000
+#define FLASH_MAN_MCHP	0x02000000	/* Microchip Technology		*/
+
+#define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type	information	*/
+#define FLASH_VENDMASK	0xFFFF0000	/* extract FLASH vendor information	*/
+
+#define FLASH_AMD_COMP	0x000FFFFF	/* Up to this ID, FLASH is compatible	*/
+					/* with AMD, Fujitsu and SST		*/
+					/* (JEDEC standard commands ?)		*/
+
+#define FLASH_BTYPE	0x0001		/* mask for bottom boot sector type	*/
+
+/*-----------------------------------------------------------------------
+ * Timeout constants:
+ *
+ * We can't find any specifications for maximum chip erase times,
+ * so these values are guestimates.
+ */
+#define FLASH_ERASE_TIMEOUT	120000	/* timeout for erasing in ms		*/
+#define FLASH_WRITE_TIMEOUT	500	/* timeout for writes  in ms		*/
+
+#endif /* _FLASH_H_ */
diff --git a/include/fm_eth.h b/include/fm_eth.h
new file mode 100644
index 0000000..729ad63
--- /dev/null
+++ b/include/fm_eth.h
@@ -0,0 +1,219 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
+ */
+
+#ifndef __FM_ETH_H__
+#define __FM_ETH_H__
+
+#include <common.h>
+#include <phy.h>
+#include <asm/types.h>
+
+enum fm_port {
+	FM1_DTSEC1,
+	FM1_DTSEC2,
+	FM1_DTSEC3,
+	FM1_DTSEC4,
+	FM1_DTSEC5,
+	FM1_DTSEC6,
+	FM1_DTSEC9,
+	FM1_DTSEC10,
+	FM1_10GEC1,
+	FM1_10GEC2,
+	FM1_10GEC3,
+	FM1_10GEC4,
+	FM2_DTSEC1,
+	FM2_DTSEC2,
+	FM2_DTSEC3,
+	FM2_DTSEC4,
+	FM2_DTSEC5,
+	FM2_DTSEC6,
+	FM2_DTSEC9,
+	FM2_DTSEC10,
+	FM2_10GEC1,
+	FM2_10GEC2,
+	NUM_FM_PORTS,
+};
+
+enum fm_eth_type {
+	FM_ETH_1G_E,
+	FM_ETH_10G_E,
+};
+
+/* Historically, on FMan v3 platforms, the first MDIO bus has been used for
+ * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the
+ * TGEC name).
+ *
+ * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus,
+ * and no TGEC ports are present on-board.
+ */
+#ifdef CONFIG_SYS_FMAN_V3
+#ifdef CONFIG_TARGET_LS1046AFRWY
+#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#else
+#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
+#endif
+#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#if (CONFIG_SYS_NUM_FMAN == 2)
+#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
+#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
+#endif
+#else
+#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
+#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
+#endif
+
+#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
+#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
+
+/* Fman ethernet info struct */
+#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
+	.fm		= idx,						\
+	.phy_regs	= (void *)pregs,				\
+	.enet_if	= PHY_INTERFACE_MODE_NONE,			\
+
+#ifdef CONFIG_SYS_FMAN_V3
+#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_1G_E,					\
+	.port		= FM##idx##_DTSEC##n,				\
+	.rx_port_id	= RX_PORT_1G_BASE + n - 1,			\
+	.tx_port_id	= TX_PORT_1G_BASE + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, memac[n-1]),\
+}
+
+#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_10G_E,					\
+	.port		= FM##idx##_10GEC##n,				\
+	.rx_port_id	= RX_PORT_10G_BASE2 + n - 1,			\
+	.tx_port_id	= TX_PORT_10G_BASE2 + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				 offsetof(struct ccsr_fman, memac[n-1]),\
+}
+#else
+#if (CONFIG_SYS_NUM_FMAN == 2)
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_10G_E,					\
+	.port		= FM##idx##_10GEC##n,				\
+	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
+	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, memac[n-1+8]),\
+}
+#else
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_10G_E,					\
+	.port		= FM##idx##_10GEC##n,				\
+	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
+	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, memac[n-1+8]),\
+}
+#endif
+#endif
+
+#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
+#define FM_TGEC_INFO_INITIALIZER2(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_10G_E,					\
+	.port		= FM##idx##_10GEC##n,				\
+	.rx_port_id	= RX_PORT_10G_BASE2 + n - 3,			\
+	.tx_port_id	= TX_PORT_10G_BASE2 + n - 3,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, memac[n-1-2]),\
+}
+#endif
+
+#else
+#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_1G_E,					\
+	.port		= FM##idx##_DTSEC##n,				\
+	.rx_port_id	= RX_PORT_1G_BASE + n - 1,			\
+	.tx_port_id	= TX_PORT_1G_BASE + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, mac_1g[n-1]),\
+}
+
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_10G_E,					\
+	.port		= FM##idx##_10GEC##n,				\
+	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
+	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, mac_10g[n-1]),\
+}
+#endif
+struct fm_eth_info {
+	u8 enabled;
+	u8 fm;
+	u8 num;
+	u8 phy_addr;
+	int index;
+	u16 rx_port_id;
+	u16 tx_port_id;
+	enum fm_port port;
+	enum fm_eth_type type;
+	void *phy_regs;
+	phy_interface_t enet_if;
+	u32 compat_offset;
+	struct mii_dev *bus;
+};
+
+struct tgec_mdio_info {
+	struct tgec_mdio_controller *regs;
+	char *name;
+};
+
+struct memac_mdio_info {
+	struct memac_mdio_controller *regs;
+	char *name;
+};
+
+int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
+int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info);
+
+int fm_standard_init(bd_t *bis);
+void fman_enet_init(void);
+void fdt_fixup_fman_ethernet(void *fdt);
+phy_interface_t fm_info_get_enet_if(enum fm_port port);
+void fm_info_set_phy_address(enum fm_port port, int address);
+int fm_info_get_phy_address(enum fm_port port);
+void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
+void fm_disable_port(enum fm_port port);
+void fm_enable_port(enum fm_port port);
+void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
+		unsigned int port_num, int phy_base_addr);
+int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
+		unsigned int port_num, unsigned regnum);
+
+#endif
diff --git a/include/fpga.h b/include/fpga.h
new file mode 100644
index 0000000..ec51443
--- /dev/null
+++ b/include/fpga.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ */
+
+#include <linux/types.h>	       /* for ulong typedef */
+
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+#ifndef CONFIG_MAX_FPGA_DEVICES
+#define CONFIG_MAX_FPGA_DEVICES		5
+#endif
+
+/* fpga_xxxx function return value definitions */
+#define FPGA_SUCCESS		0
+#define FPGA_FAIL		1
+
+/* device numbers must be non-negative */
+#define FPGA_INVALID_DEVICE	-1
+
+#define FPGA_ENC_USR_KEY	1
+#define FPGA_NO_ENC_OR_NO_AUTH	2
+
+/* root data type defintions */
+typedef enum {			/* typedef fpga_type */
+	fpga_min_type,		/* range check value */
+	fpga_xilinx,		/* Xilinx Family) */
+	fpga_altera,		/* unimplemented */
+	fpga_lattice,		/* Lattice family */
+	fpga_undefined		/* invalid range check value */
+} fpga_type;			/* end, typedef fpga_type */
+
+typedef struct {		/* typedef fpga_desc */
+	fpga_type devtype;	/* switch value to select sub-functions */
+	void *devdesc;		/* real device descriptor */
+} fpga_desc;			/* end, typedef fpga_desc */
+
+typedef struct {                /* typedef fpga_desc */
+	unsigned int blocksize;
+	char *interface;
+	char *dev_part;
+	const char *filename;
+	int fstype;
+} fpga_fs_info;
+
+struct fpga_secure_info {
+	u8 *userkey_addr;
+	u8 authflag;
+	u8 encflag;
+};
+
+typedef enum {
+	BIT_FULL = 0,
+	BIT_PARTIAL,
+	BIT_NONE = 0xFF,
+} bitstream_type;
+
+/* root function definitions */
+void fpga_init(void);
+int fpga_add(fpga_type devtype, void *desc);
+int fpga_count(void);
+const fpga_desc *const fpga_get_desc(int devnum);
+int fpga_is_partial_data(int devnum, size_t img_len);
+int fpga_load(int devnum, const void *buf, size_t bsize,
+	      bitstream_type bstype);
+int fpga_fsload(int devnum, const void *buf, size_t size,
+		fpga_fs_info *fpga_fsinfo);
+int fpga_loads(int devnum, const void *buf, size_t size,
+	       struct fpga_secure_info *fpga_sec_info);
+int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
+		       bitstream_type bstype);
+int fpga_dump(int devnum, const void *buf, size_t bsize);
+int fpga_info(int devnum);
+const fpga_desc *const fpga_validate(int devnum, const void *buf,
+				     size_t bsize, char *fn);
+
+#endif	/* _FPGA_H_ */
diff --git a/include/fs.h b/include/fs.h
new file mode 100644
index 0000000..742a535
--- /dev/null
+++ b/include/fs.h
@@ -0,0 +1,235 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ */
+#ifndef _FS_H
+#define _FS_H
+
+#include <common.h>
+
+#define FS_TYPE_ANY	0
+#define FS_TYPE_FAT	1
+#define FS_TYPE_EXT	2
+#define FS_TYPE_SANDBOX	3
+#define FS_TYPE_UBIFS	4
+#define FS_TYPE_BTRFS	5
+
+/*
+ * Tell the fs layer which block device an partition to use for future
+ * commands. This also internally identifies the filesystem that is present
+ * within the partition. The identification process may be limited to a
+ * specific filesystem type by passing FS_* in the fstype parameter.
+ *
+ * Returns 0 on success.
+ * Returns non-zero if there is an error accessing the disk or partition, or
+ * no known filesystem type could be recognized on it.
+ */
+int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype);
+
+/*
+ * fs_set_blk_dev_with_part - Set current block device + partition
+ *
+ * Similar to fs_set_blk_dev(), but useful for cases where you already
+ * know the blk_desc and part number.
+ *
+ * Returns 0 on success.
+ * Returns non-zero if invalid partition or error accessing the disk.
+ */
+int fs_set_blk_dev_with_part(struct blk_desc *desc, int part);
+
+/**
+ * fs_close() - Unset current block device and partition
+ *
+ * fs_close() closes the connection to a file system opened with either
+ * fs_set_blk_dev() or fs_set_dev_with_part().
+ *
+ * Many file functions implicitly call fs_close(), e.g. fs_closedir(),
+ * fs_exist(), fs_ln(), fs_ls(), fs_mkdir(), fs_read(), fs_size(), fs_write(),
+ * fs_unlink().
+ */
+void fs_close(void);
+
+/**
+ * fs_get_type() - Get type of current filesystem
+ *
+ * Return: filesystem type
+ *
+ * Returns filesystem type representing the current filesystem, or
+ * FS_TYPE_ANY for any unrecognised filesystem.
+ */
+int fs_get_type(void);
+
+/**
+ * fs_get_type_name() - Get type of current filesystem
+ *
+ * Return: Pointer to filesystem name
+ *
+ * Returns a string describing the current filesystem, or the sentinel
+ * "unsupported" for any unrecognised filesystem.
+ */
+const char *fs_get_type_name(void);
+
+/*
+ * Print the list of files on the partition previously set by fs_set_blk_dev(),
+ * in directory "dirname".
+ *
+ * Returns 0 on success. Returns non-zero on error.
+ */
+int fs_ls(const char *dirname);
+
+/*
+ * Determine whether a file exists
+ *
+ * Returns 1 if the file exists, 0 if it doesn't exist.
+ */
+int fs_exists(const char *filename);
+
+/*
+ * fs_size - Determine a file's size
+ *
+ * @filename: Name of the file
+ * @size: Size of file
+ * @return 0 if ok with valid *size, negative on error
+ */
+int fs_size(const char *filename, loff_t *size);
+
+/**
+ * fs_read() - read file from the partition previously set by fs_set_blk_dev()
+ *
+ * Note that not all filesystem drivers support either or both of offset != 0
+ * and len != 0.
+ *
+ * @filename:	full path of the file to read from
+ * @addr:	address of the buffer to write to
+ * @offset:	offset in the file from where to start reading
+ * @len:	the number of bytes to read. Use 0 to read entire file.
+ * @actread:	returns the actual number of bytes read
+ * Return:	0 if OK with valid *actread, -1 on error conditions
+ */
+int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
+	    loff_t *actread);
+
+/**
+ * fs_write() - write file to the partition previously set by fs_set_blk_dev()
+ *
+ * Note that not all filesystem drivers support offset != 0.
+ *
+ * @filename:	full path of the file to write to
+ * @addr:	address of the buffer to read from
+ * @offset:	offset in the file from where to start writing
+ * @len:	the number of bytes to write
+ * @actwrite:	returns the actual number of bytes written
+ * Return:	0 if OK with valid *actwrite, -1 on error conditions
+ */
+int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
+	     loff_t *actwrite);
+
+/*
+ * Directory entry types, matches the subset of DT_x in posix readdir()
+ * which apply to u-boot.
+ */
+#define FS_DT_DIR  4         /* directory */
+#define FS_DT_REG  8         /* regular file */
+#define FS_DT_LNK  10        /* symbolic link */
+
+/*
+ * A directory entry, returned by fs_readdir().  Returns information
+ * about the file/directory at the current directory entry position.
+ */
+struct fs_dirent {
+	unsigned type;       /* one of FS_DT_x (not a mask) */
+	loff_t size;         /* size in bytes */
+	char name[256];
+};
+
+/* Note: fs_dir_stream should be treated as opaque to the user of fs layer */
+struct fs_dir_stream {
+	/* private to fs. layer: */
+	struct blk_desc *desc;
+	int part;
+};
+
+/*
+ * fs_opendir - Open a directory
+ *
+ * @filename: the path to directory to open
+ * @return a pointer to the directory stream or NULL on error and errno
+ *    set appropriately
+ */
+struct fs_dir_stream *fs_opendir(const char *filename);
+
+/*
+ * fs_readdir - Read the next directory entry in the directory stream.
+ *
+ * Works in an analogous way to posix readdir().  The previously returned
+ * directory entry is no longer valid after calling fs_readdir() again.
+ * After fs_closedir() is called, the returned directory entry is no
+ * longer valid.
+ *
+ * @dirs: the directory stream
+ * @return the next directory entry (only valid until next fs_readdir() or
+ *    fs_closedir() call, do not attempt to free()) or NULL if the end of
+ *    the directory is reached.
+ */
+struct fs_dirent *fs_readdir(struct fs_dir_stream *dirs);
+
+/*
+ * fs_closedir - close a directory stream
+ *
+ * @dirs: the directory stream
+ */
+void fs_closedir(struct fs_dir_stream *dirs);
+
+/*
+ * fs_unlink - delete a file or directory
+ *
+ * If a given name is a directory, it will be deleted only if it's empty
+ *
+ * @filename: Name of file or directory to delete
+ * @return 0 on success, -1 on error conditions
+ */
+int fs_unlink(const char *filename);
+
+/*
+ * fs_mkdir - Create a directory
+ *
+ * @filename: Name of directory to create
+ * @return 0 on success, -1 on error conditions
+ */
+int fs_mkdir(const char *filename);
+
+/*
+ * Common implementation for various filesystem commands, optionally limited
+ * to a specific filesystem type via the fstype parameter.
+ */
+int do_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		int fstype);
+int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		int fstype);
+int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		int fstype);
+int file_exists(const char *dev_type, const char *dev_part, const char *file,
+		int fstype);
+int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		int fstype);
+int do_rm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		int fstype);
+int do_mkdir(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		int fstype);
+int do_ln(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+	  int fstype);
+
+/*
+ * Determine the UUID of the specified filesystem and print it. Optionally it is
+ * possible to store the UUID directly in env.
+ */
+int do_fs_uuid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		int fstype);
+
+/*
+ * Determine the type of the specified filesystem and print it. Optionally it is
+ * possible to store the type directly in env.
+ */
+int do_fs_type(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+#endif /* _FS_H */
diff --git a/include/fs_internal.h b/include/fs_internal.h
new file mode 100644
index 0000000..96d2603
--- /dev/null
+++ b/include/fs_internal.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * 2017 by Marek Behun <marek.behun@nic.cz>
+ *
+ * Derived from code in ext4/dev.c, which was based on reiserfs/dev.c
+ */
+
+#ifndef __U_BOOT_FS_INTERNAL_H__
+#define __U_BOOT_FS_INTERNAL_H__
+
+#include <part.h>
+
+int fs_devread(struct blk_desc *, disk_partition_t *, lbaint_t, int, int,
+	       char *);
+
+#endif /* __U_BOOT_FS_INTERNAL_H__ */
diff --git a/include/fs_loader.h b/include/fs_loader.h
new file mode 100644
index 0000000..b728c06
--- /dev/null
+++ b/include/fs_loader.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+#ifndef _FS_LOADER_H_
+#define _FS_LOADER_H_
+
+#include <dm.h>
+
+/**
+ * struct phandle_part - A place for storing phandle of node and its partition
+ *
+ * This holds information about a phandle of the block device, and its
+ * partition where the firmware would be loaded from.
+ *
+ * @phandle: Phandle of storage device node
+ * @partition: Partition of block device
+ */
+struct phandle_part {
+	u32 phandle;
+	u32 partition;
+};
+
+/**
+ * struct phandle_part - A place for storing all supported storage devices
+ *
+ * This holds information about all supported storage devices for driver use.
+ *
+ * @phandlepart: Attribute data for block device.
+ * @mtdpart: MTD partition for ubi partition.
+ * @ubivol: UBI volume-name for ubifsmount.
+ */
+struct device_platdata {
+	struct phandle_part phandlepart;
+	char *mtdpart;
+	char *ubivol;
+};
+
+/**
+ * request_firmware_into_buf - Load firmware into a previously allocated buffer.
+ * @dev: An instance of a driver.
+ * @name: Name of firmware file.
+ * @buf: Address of buffer to load firmware into.
+ * @size: Size of buffer.
+ * @offset: Offset of a file for start reading into buffer.
+ *
+ * The firmware is loaded directly into the buffer pointed to by @buf.
+ *
+ * Return: Size of total read, negative value when error.
+ */
+int request_firmware_into_buf(struct udevice *dev,
+			      const char *name,
+			      void *buf, size_t size, u32 offset);
+#endif
diff --git a/include/fsl-mc/fsl_dpaa_fd.h b/include/fsl-mc/fsl_dpaa_fd.h
new file mode 100644
index 0000000..159756f
--- /dev/null
+++ b/include/fsl-mc/fsl_dpaa_fd.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ */
+#ifndef __FSL_DPAA_FD_H
+#define __FSL_DPAA_FD_H
+
+/* Place-holder for FDs, we represent it via the simplest form that we need for
+ * now. Different overlays may be needed to support different options, etc. (It
+ * is impractical to define One True Struct, because the resulting encoding
+ * routines (lots of read-modify-writes) would be worst-case performance whether
+ * or not circumstances required them.) */
+struct dpaa_fd {
+	union {
+		u32 words[8];
+		struct dpaa_fd_simple {
+			u32 addr_lo;
+			u32 addr_hi;
+			u32 len;
+			/* offset in the MS 16 bits, BPID in the LS 16 bits */
+			u32 bpid_offset;
+			u32 frc; /* frame context */
+			/* "err", "va", "cbmt", "asal", [...] */
+			u32 ctrl;
+			/* flow context */
+			u32 flc_lo;
+			u32 flc_hi;
+		} simple;
+	};
+};
+
+enum dpaa_fd_format {
+	dpaa_fd_single = 0,
+	dpaa_fd_list,
+	dpaa_fd_sg
+};
+
+static inline u64 ldpaa_fd_get_addr(const struct dpaa_fd *fd)
+{
+	return (u64)((((uint64_t)fd->simple.addr_hi) << 32)
+				+ fd->simple.addr_lo);
+}
+
+static inline void ldpaa_fd_set_addr(struct dpaa_fd *fd, u64 addr)
+{
+	fd->simple.addr_hi = upper_32_bits(addr);
+	fd->simple.addr_lo = lower_32_bits(addr);
+}
+
+static inline u32 ldpaa_fd_get_len(const struct dpaa_fd *fd)
+{
+	return fd->simple.len;
+}
+
+static inline void ldpaa_fd_set_len(struct dpaa_fd *fd, u32 len)
+{
+	fd->simple.len = len;
+}
+
+static inline uint16_t ldpaa_fd_get_offset(const struct dpaa_fd *fd)
+{
+	return (uint16_t)(fd->simple.bpid_offset >> 16) & 0x0FFF;
+}
+
+static inline void ldpaa_fd_set_offset(struct dpaa_fd *fd, uint16_t offset)
+{
+	fd->simple.bpid_offset &= 0xF000FFFF;
+	fd->simple.bpid_offset |= (u32)offset << 16;
+}
+
+static inline uint16_t ldpaa_fd_get_bpid(const struct dpaa_fd *fd)
+{
+	return (uint16_t)(fd->simple.bpid_offset & 0xFFFF);
+}
+
+static inline void ldpaa_fd_set_bpid(struct dpaa_fd *fd, uint16_t bpid)
+{
+	fd->simple.bpid_offset &= 0xFFFF0000;
+	fd->simple.bpid_offset |= (u32)bpid;
+}
+
+/* When frames are dequeued, the FDs show up inside "dequeue" result structures
+ * (if at all, not all dequeue results contain valid FDs). This structure type
+ * is intentionally defined without internal detail, and the only reason it
+ * isn't declared opaquely (without size) is to allow the user to provide
+ * suitably-sized (and aligned) memory for these entries. */
+struct ldpaa_dq {
+	uint32_t dont_manipulate_directly[16];
+};
+
+/* Parsing frame dequeue results */
+#define LDPAA_DQ_STAT_FQEMPTY       0x80
+#define LDPAA_DQ_STAT_HELDACTIVE    0x40
+#define LDPAA_DQ_STAT_FORCEELIGIBLE 0x20
+#define LDPAA_DQ_STAT_VALIDFRAME    0x10
+#define LDPAA_DQ_STAT_ODPVALID      0x04
+#define LDPAA_DQ_STAT_VOLATILE      0x02
+#define LDPAA_DQ_STAT_EXPIRED       0x01
+uint32_t ldpaa_dq_flags(const struct ldpaa_dq *);
+static inline int ldpaa_dq_is_pull(const struct ldpaa_dq *dq)
+{
+	return (int)(ldpaa_dq_flags(dq) & LDPAA_DQ_STAT_VOLATILE);
+}
+static inline int ldpaa_dq_is_pull_complete(
+					const struct ldpaa_dq *dq)
+{
+	return (int)(ldpaa_dq_flags(dq) & LDPAA_DQ_STAT_EXPIRED);
+}
+/* seqnum/odpid are valid only if VALIDFRAME and ODPVALID flags are TRUE */
+uint16_t ldpaa_dq_seqnum(const struct ldpaa_dq *);
+uint16_t ldpaa_dq_odpid(const struct ldpaa_dq *);
+uint32_t ldpaa_dq_fqid(const struct ldpaa_dq *);
+uint32_t ldpaa_dq_byte_count(const struct ldpaa_dq *);
+uint32_t ldpaa_dq_frame_count(const struct ldpaa_dq *);
+uint32_t ldpaa_dq_fqd_ctx_hi(const struct ldpaa_dq *);
+uint32_t ldpaa_dq_fqd_ctx_lo(const struct ldpaa_dq *);
+/* get the Frame Descriptor */
+const struct dpaa_fd *ldpaa_dq_fd(const struct ldpaa_dq *);
+
+#endif /* __FSL_DPAA_FD_H */
diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h
new file mode 100644
index 0000000..2278ac9
--- /dev/null
+++ b/include/fsl-mc/fsl_dpbp.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+/*!
+ *  @file    fsl_dpbp.h
+ *  @brief   Data Path Buffer Pool API
+ */
+#ifndef __FSL_DPBP_H
+#define __FSL_DPBP_H
+
+/* DPBP Version */
+#define DPBP_VER_MAJOR				3
+#define DPBP_VER_MINOR				3
+
+/* Command IDs */
+#define DPBP_CMDID_CLOSE				0x8001
+#define DPBP_CMDID_OPEN					0x8041
+#define DPBP_CMDID_CREATE				0x9041
+#define DPBP_CMDID_DESTROY				0x9841
+#define DPBP_CMDID_GET_API_VERSION			0xa041
+
+#define DPBP_CMDID_ENABLE				0x0021
+#define DPBP_CMDID_DISABLE				0x0031
+#define DPBP_CMDID_GET_ATTR				0x0041
+#define DPBP_CMDID_RESET				0x0051
+#define DPBP_CMDID_IS_ENABLED				0x0061
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPBP_CMD_OPEN(cmd, dpbp_id) \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    dpbp_id)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPBP_RSP_GET_ATTRIBUTES(cmd, attr) \
+do { \
+	MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->bpid); \
+	MC_RSP_OP(cmd, 0, 32, 32, int,	    attr->id);\
+} while (0)
+
+/* Data Path Buffer Pool API
+ * Contains initialization APIs and runtime control APIs for DPBP
+ */
+
+struct fsl_mc_io;
+
+/**
+ * dpbp_open() - Open a control session for the specified object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpbp_id:	DPBP unique ID
+ * @token:	Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpbp_create function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_open(struct fsl_mc_io	*mc_io,
+	      uint32_t		cmd_flags,
+	      int		dpbp_id,
+	      uint16_t		*token);
+
+/**
+ * dpbp_close() - Close the control session of the object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_close(struct fsl_mc_io	*mc_io,
+	       uint32_t		cmd_flags,
+	       uint16_t	token);
+
+/**
+ * struct dpbp_cfg - Structure representing DPBP configuration
+ * @options:	place holder
+ */
+struct dpbp_cfg {
+	uint32_t options;
+};
+
+/**
+ * dpbp_create() - Create the DPBP object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg:	Configuration structure
+ * @token:	Returned token; use in subsequent API calls
+ *
+ * Create the DPBP object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpbp_open function to get an authentication
+ * token first.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_create(struct fsl_mc_io	*mc_io,
+		uint16_t		dprc_token,
+		uint32_t		cmd_flags,
+		const struct dpbp_cfg	*cfg,
+		uint32_t		*obj_id);
+
+/**
+ * dpbp_destroy() - Destroy the DPBP object and release all its resources.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ *
+ * Return:	'0' on Success; error code otherwise.
+ */
+int dpbp_destroy(struct fsl_mc_io	*mc_io,
+		 uint16_t		dprc_token,
+		 uint32_t		cmd_flags,
+		 uint32_t		obj_id);
+
+/**
+ * dpbp_enable() - Enable the DPBP.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_enable(struct fsl_mc_io	*mc_io,
+		uint32_t		cmd_flags,
+		uint16_t		token);
+
+/**
+ * dpbp_disable() - Disable the DPBP.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_disable(struct fsl_mc_io	*mc_io,
+		 uint32_t		cmd_flags,
+		 uint16_t		token);
+
+/**
+ * dpbp_is_enabled() - Check if the DPBP is enabled.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ * @en:		Returns '1' if object is enabled; '0' otherwise
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_is_enabled(struct fsl_mc_io	*mc_io,
+		    uint32_t		cmd_flags,
+		    uint16_t		token,
+		    int		*en);
+
+/**
+ * dpbp_reset() - Reset the DPBP, returns the object to initial state.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_reset(struct fsl_mc_io	*mc_io,
+	       uint32_t		cmd_flags,
+	       uint16_t	token);
+
+
+/**
+ * struct dpbp_attr - Structure representing DPBP attributes
+ * @id:		DPBP object ID
+ * @version:	DPBP version
+ * @bpid:	Hardware buffer pool ID; should be used as an argument in
+ *		acquire/release operations on buffers
+ */
+struct dpbp_attr {
+	uint32_t id;
+	uint16_t bpid;
+};
+
+/**
+ * dpbp_get_attributes - Retrieve DPBP attributes.
+ *
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPBP object
+ * @attr:	Returned object's attributes
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_get_attributes(struct fsl_mc_io	*mc_io,
+			uint32_t	cmd_flags,
+			uint16_t		token,
+			struct dpbp_attr	*attr);
+
+/**
+ * dpbp_get_api_version - Retrieve DPBP Major and Minor version info.
+ *
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver:	DPBP major version
+ * @minor_ver:	DPBP minor version
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpbp_get_api_version(struct fsl_mc_io *mc_io,
+			 u32 cmd_flags,
+			 u16 *major_ver,
+			 u16 *minor_ver);
+
+/** @} */
+
+#endif /* __FSL_DPBP_H */
diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h
new file mode 100644
index 0000000..7788e19
--- /dev/null
+++ b/include/fsl-mc/fsl_dpio.h
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _FSL_DPIO_H
+#define _FSL_DPIO_H
+
+/* DPIO Version */
+#define DPIO_VER_MAJOR				4
+#define DPIO_VER_MINOR				2
+
+/* Command IDs */
+#define DPIO_CMDID_CLOSE					0x8001
+#define DPIO_CMDID_OPEN						0x8031
+#define DPIO_CMDID_CREATE					0x9031
+#define DPIO_CMDID_DESTROY					0x9831
+#define DPIO_CMDID_GET_API_VERSION				0xa031
+
+#define DPIO_CMDID_ENABLE					0x0021
+#define DPIO_CMDID_DISABLE					0x0031
+#define DPIO_CMDID_GET_ATTR					0x0041
+#define DPIO_CMDID_RESET					0x0051
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPIO_CMD_OPEN(cmd, dpio_id) \
+	MC_CMD_OP(cmd, 0, 0,  32, int,     dpio_id)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPIO_CMD_CREATE(cmd, cfg) \
+do { \
+	MC_CMD_OP(cmd, 0, 16, 2,  enum dpio_channel_mode,	\
+					   cfg->channel_mode);\
+	MC_CMD_OP(cmd, 0, 32, 8,  uint8_t, cfg->num_priorities);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPIO_RSP_GET_ATTR(cmd, attr) \
+do { \
+	MC_RSP_OP(cmd, 0, 0,  32, int,	    attr->id);\
+	MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_portal_id);\
+	MC_RSP_OP(cmd, 0, 48, 8,  uint8_t,  attr->num_priorities);\
+	MC_RSP_OP(cmd, 0, 56, 4,  enum dpio_channel_mode, attr->channel_mode);\
+	MC_RSP_OP(cmd, 1, 0,  64, uint64_t, attr->qbman_portal_ce_offset);\
+	MC_RSP_OP(cmd, 2, 0,  64, uint64_t, attr->qbman_portal_ci_offset);\
+	MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\
+} while (0)
+
+/* Data Path I/O Portal API
+ * Contains initialization APIs and runtime control APIs for DPIO
+ */
+
+struct fsl_mc_io;
+
+/**
+ * dpio_open() - Open a control session for the specified object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpio_id:	DPIO unique ID
+ * @token:	Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpio_create() function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpio_open(struct fsl_mc_io	*mc_io,
+	      uint32_t		cmd_flags,
+	      uint32_t		dpio_id,
+	      uint16_t		*token);
+
+/**
+ * dpio_close() - Close the control session of the object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPIO object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpio_close(struct fsl_mc_io	*mc_io,
+	       uint32_t		cmd_flags,
+	       uint16_t		token);
+
+/**
+ * enum dpio_channel_mode - DPIO notification channel mode
+ * @DPIO_NO_CHANNEL: No support for notification channel
+ * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a
+ *	dedicated channel in the DPIO; user should point the queue's
+ *	destination in the relevant interface to this DPIO
+ */
+enum dpio_channel_mode {
+	DPIO_NO_CHANNEL = 0,
+	DPIO_LOCAL_CHANNEL = 1,
+};
+
+/**
+ * struct dpio_cfg - Structure representing DPIO configuration
+ * @channel_mode: Notification channel mode
+ * @num_priorities: Number of priorities for the notification channel (1-8);
+ *			relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
+ */
+struct dpio_cfg {
+	enum dpio_channel_mode	channel_mode;
+	uint8_t		num_priorities;
+};
+
+/**
+ * dpio_create() - Create the DPIO object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @token:	Authentication token.
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg:	Configuration structure
+ * @obj_id:	Returned obj_id; use in subsequent API calls
+ *
+ * Create the DPIO object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ *
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpio_open() function to get an authentication
+ * token first.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpio_create(struct fsl_mc_io	*mc_io,
+		uint16_t		token,
+		uint32_t		cmd_flags,
+		const struct dpio_cfg	*cfg,
+		uint32_t		*obj_id);
+
+/**
+ * dpio_destroy() - Destroy the DPIO object and release all its resources.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @token:	Authentication token.
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @obj_id:	Object ID of DPIO
+ *
+ * Return:	'0' on Success; Error code otherwise
+ */
+int dpio_destroy(struct fsl_mc_io	*mc_io,
+		 uint16_t		token,
+		 uint32_t		cmd_flags,
+		 uint32_t		obj_id);
+
+/**
+ * dpio_enable() - Enable the DPIO, allow I/O portal operations.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPIO object
+ *
+ * Return:	'0' on Success; Error code otherwise
+ */
+int dpio_enable(struct fsl_mc_io	*mc_io,
+		uint32_t		cmd_flags,
+		uint16_t		token);
+
+/**
+ * dpio_disable() - Disable the DPIO, stop any I/O portal operation.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPIO object
+ *
+ * Return:	'0' on Success; Error code otherwise
+ */
+int dpio_disable(struct fsl_mc_io	*mc_io,
+		 uint32_t		cmd_flags,
+		 uint16_t		token);
+
+/**
+ * dpio_reset() - Reset the DPIO, returns the object to initial state.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPIO object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpio_reset(struct fsl_mc_io	*mc_io,
+	       uint32_t			cmd_flags,
+	       uint16_t		token);
+
+/**
+ * struct dpio_attr - Structure representing DPIO attributes
+ * @id: DPIO object ID
+ * @version: DPIO version
+ * @qbman_portal_ce_offset: offset of the software portal cache-enabled area
+ * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area
+ * @qbman_portal_id: Software portal ID
+ * @channel_mode: Notification channel mode
+ * @num_priorities: Number of priorities for the notification channel (1-8);
+ *			relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
+ * @qbman_version: QBMAN version
+ */
+struct dpio_attr {
+	uint32_t id;
+	uint64_t qbman_portal_ce_offset;
+	uint64_t qbman_portal_ci_offset;
+	uint16_t qbman_portal_id;
+	enum dpio_channel_mode channel_mode;
+	uint8_t num_priorities;
+	uint32_t		qbman_version;
+};
+
+/**
+ * dpio_get_attributes() - Retrieve DPIO attributes
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPIO object
+ * @attr:	Returned object's attributes
+ *
+ * Return:	'0' on Success; Error code otherwise
+ */
+int dpio_get_attributes(struct fsl_mc_io	*mc_io,
+			uint32_t		cmd_flags,
+			uint16_t		token,
+			struct dpio_attr	*attr);
+
+/**
+ * dpio_get_api_version - Retrieve DPIO Major and Minor version info.
+ *
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver:	DPIO major version
+ * @minor_ver:	DPIO minor version
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpio_get_api_version(struct fsl_mc_io *mc_io,
+			 u32 cmd_flags,
+			 u16 *major_ver,
+			 u16 *minor_ver);
+
+#endif /* _FSL_DPIO_H */
diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h
new file mode 100644
index 0000000..1cea123
--- /dev/null
+++ b/include/fsl-mc/fsl_dpmac.h
@@ -0,0 +1,476 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ */
+
+#ifndef __FSL_DPMAC_H
+#define __FSL_DPMAC_H
+
+/* DPMAC Version */
+#define DPMAC_VER_MAJOR				4
+#define DPMAC_VER_MINOR				2
+
+/* Command IDs */
+#define DPMAC_CMDID_CLOSE			0x8001
+#define DPMAC_CMDID_OPEN			0x80c1
+#define DPMAC_CMDID_CREATE			0x90c1
+#define DPMAC_CMDID_DESTROY			0x98c1
+#define DPMAC_CMDID_GET_API_VERSION             0xa0c1
+
+#define DPMAC_CMDID_GET_ATTR			0x0041
+#define DPMAC_CMDID_RESET			0x0051
+
+#define DPMAC_CMDID_MDIO_READ			0x0c01
+#define DPMAC_CMDID_MDIO_WRITE			0x0c11
+#define DPMAC_CMDID_GET_LINK_CFG		0x0c21
+#define DPMAC_CMDID_SET_LINK_STATE		0x0c31
+#define DPMAC_CMDID_GET_COUNTER			0x0c41
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_CREATE(cmd, cfg) \
+	MC_CMD_OP(cmd, 0, 0,  16, uint16_t,      cfg->mac_id)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_OPEN(cmd, dpmac_id) \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    dpmac_id)
+
+/*                cmd, param, offset, width, type,	arg_name */
+#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \
+do { \
+	MC_RSP_OP(cmd, 0, 0,  32, int,			attr->phy_id);\
+	MC_RSP_OP(cmd, 0, 32, 32, int,			attr->id);\
+	MC_RSP_OP(cmd, 1, 32,  8, enum dpmac_link_type,	attr->link_type);\
+	MC_RSP_OP(cmd, 1, 40,  8, enum dpmac_eth_if,	attr->eth_if);\
+	MC_RSP_OP(cmd, 2, 0,  32, uint32_t,		attr->max_rate);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_MDIO_READ(cmd, cfg) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  8,  uint8_t,  cfg->phy_addr); \
+	MC_CMD_OP(cmd, 0, 8,  8,  uint8_t,  cfg->reg); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMAC_RSP_MDIO_READ(cmd, data) \
+	MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  8,  uint8_t,  cfg->phy_addr); \
+	MC_CMD_OP(cmd, 0, 8,  8,  uint8_t,  cfg->reg); \
+	MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \
+do { \
+	MC_RSP_OP(cmd, 0, 0,  64, uint64_t, cfg->options); \
+	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, cfg->rate); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  64, uint64_t, cfg->options); \
+	MC_CMD_OP(cmd, 1, 0,  32, uint32_t, cfg->rate); \
+	MC_CMD_OP(cmd, 2, 0,  1,  int,      cfg->up); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMAC_CMD_GET_COUNTER(cmd, type) \
+	MC_CMD_OP(cmd, 1, 0,  64, enum dpmac_counter, type)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPMAC_RSP_GET_COUNTER(cmd, counter) \
+	MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter)
+
+/* Data Path MAC API
+ * Contains initialization APIs and runtime control APIs for DPMAC
+ */
+
+struct fsl_mc_io;
+
+/**
+ * dpmac_open() - Open a control session for the specified object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpmac_id:	DPMAC unique ID
+ * @token:	Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpmac_create function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_open(struct fsl_mc_io	*mc_io,
+	       uint32_t		cmd_flags,
+	       int			dpmac_id,
+	       uint16_t		*token);
+
+/**
+ * dpmac_close() - Close the control session of the object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPMAC object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_close(struct fsl_mc_io	*mc_io,
+		uint32_t		cmd_flags,
+		uint16_t		token);
+
+/**
+ * enum dpmac_link_type -  DPMAC link type
+ * @DPMAC_LINK_TYPE_NONE: No link
+ * @DPMAC_LINK_TYPE_FIXED: Link is fixed type
+ * @DPMAC_LINK_TYPE_PHY: Link by PHY ID
+ * @DPMAC_LINK_TYPE_BACKPLANE: Backplane link type
+ */
+enum dpmac_link_type {
+	DPMAC_LINK_TYPE_NONE,
+	DPMAC_LINK_TYPE_FIXED,
+	DPMAC_LINK_TYPE_PHY,
+	DPMAC_LINK_TYPE_BACKPLANE
+};
+
+/**
+ * enum dpmac_eth_if - DPMAC Ethrnet interface
+ * @DPMAC_ETH_IF_MII: MII interface
+ * @DPMAC_ETH_IF_RMII: RMII interface
+ * @DPMAC_ETH_IF_SMII: SMII interface
+ * @DPMAC_ETH_IF_GMII: GMII interface
+ * @DPMAC_ETH_IF_RGMII: RGMII interface
+ * @DPMAC_ETH_IF_SGMII: SGMII interface
+ * @DPMAC_ETH_IF_QSGMII: QSGMII interface
+ * @DPMAC_ETH_IF_XAUI: XAUI interface
+ * @DPMAC_ETH_IF_XFI: XFI interface
+ */
+enum dpmac_eth_if {
+	DPMAC_ETH_IF_MII,
+	DPMAC_ETH_IF_RMII,
+	DPMAC_ETH_IF_SMII,
+	DPMAC_ETH_IF_GMII,
+	DPMAC_ETH_IF_RGMII,
+	DPMAC_ETH_IF_SGMII,
+	DPMAC_ETH_IF_QSGMII,
+	DPMAC_ETH_IF_XAUI,
+	DPMAC_ETH_IF_XFI
+};
+
+/**
+ * struct dpmac_cfg - Structure representing DPMAC configuration
+ * @mac_id:	Represents the Hardware MAC ID; in case of multiple WRIOP,
+ *		the MAC IDs are continuous.
+ *		For example:  2 WRIOPs, 16 MACs in each:
+ *				MAC IDs for the 1st WRIOP: 1-16,
+ *				MAC IDs for the 2nd WRIOP: 17-32.
+ */
+struct dpmac_cfg {
+	int mac_id;
+};
+
+/**
+ * dpmac_create() - Create the DPMAC object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @token:	Authentication token.
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg:	Configuration structure
+ * @obj_id:	Returned obj_id; use in subsequent API calls
+ *
+ * Create the DPMAC object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpmac_open function to get an authentication
+ * token first.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_create(struct fsl_mc_io	*mc_io,
+		 uint16_t		token,
+		 uint32_t		cmd_flags,
+		 const struct dpmac_cfg	*cfg,
+		 uint32_t		*obj_id);
+
+/**
+ * dpmac_destroy() - Destroy the DPMAC object and release all its resources.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @token:	Authentication token.
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @obj_id:	DPMAC object id
+ *
+ * Return:	'0' on Success; error code otherwise.
+ */
+int dpmac_destroy(struct fsl_mc_io	*mc_io,
+		  uint16_t		token,
+		  uint32_t		cmd_flags,
+		  uint32_t		obj_id);
+
+/* DPMAC IRQ Index and Events */
+
+/* IRQ index */
+#define DPMAC_IRQ_INDEX						0
+/* IRQ event - indicates a change in link state */
+#define DPMAC_IRQ_EVENT_LINK_CFG_REQ		0x00000001
+/* irq event - Indicates that the link state changed */
+#define DPMAC_IRQ_EVENT_LINK_CHANGED		0x00000002
+
+/**
+ * struct dpmac_attr - Structure representing DPMAC attributes
+ * @id:		DPMAC object ID
+ * @phy_id:	PHY ID
+ * @link_type: link type
+ * @eth_if: Ethernet interface
+ * @max_rate: Maximum supported rate - in Mbps
+ * @version:	DPMAC version
+ */
+struct dpmac_attr {
+	int			id;
+	int			phy_id;
+	enum dpmac_link_type	link_type;
+	enum dpmac_eth_if	eth_if;
+	uint32_t		max_rate;
+};
+
+/**
+ * dpmac_get_attributes - Retrieve DPMAC attributes.
+ *
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPMAC object
+ * @attr:	Returned object's attributes
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_get_attributes(struct fsl_mc_io	*mc_io,
+			 uint32_t		cmd_flags,
+			 uint16_t		token,
+			 struct dpmac_attr	*attr);
+
+/**
+ * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters
+ * @phy_addr: MDIO device address
+ * @reg: Address of the register within the Clause 45 PHY device from which data
+ *	is to be read
+ * @data: Data read/write from/to MDIO
+ */
+struct dpmac_mdio_cfg {
+	uint8_t		phy_addr;
+	uint8_t		reg;
+	uint16_t	data;
+};
+
+/**
+ * dpmac_mdio_read() - Perform MDIO read transaction
+ * @mc_io:	Pointer to opaque I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPMAC object
+ * @cfg:	Structure with MDIO transaction parameters
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_mdio_read(struct fsl_mc_io		*mc_io,
+		    uint32_t			cmd_flags,
+		    uint16_t			token,
+		    struct dpmac_mdio_cfg	*cfg);
+
+/**
+ * dpmac_mdio_write() - Perform MDIO write transaction
+ * @mc_io:	Pointer to opaque I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPMAC object
+ * @cfg:	Structure with MDIO transaction parameters
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_mdio_write(struct fsl_mc_io		*mc_io,
+		     uint32_t			cmd_flags,
+		     uint16_t			token,
+		     struct dpmac_mdio_cfg	*cfg);
+
+/* DPMAC link configuration/state options */
+
+/* Enable auto-negotiation */
+#define DPMAC_LINK_OPT_AUTONEG		0x0000000000000001ULL
+/* Enable half-duplex mode */
+#define DPMAC_LINK_OPT_HALF_DUPLEX	0x0000000000000002ULL
+/* Enable pause frames */
+#define DPMAC_LINK_OPT_PAUSE		0x0000000000000004ULL
+/* Enable a-symmetric pause frames */
+#define DPMAC_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
+
+/**
+ * struct dpmac_link_cfg - Structure representing DPMAC link configuration
+ * @rate: Link's rate - in Mbps
+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
+ */
+struct dpmac_link_cfg {
+	uint32_t rate;
+	uint64_t options;
+};
+
+/**
+ * dpmac_get_link_cfg() - Get Ethernet link configuration
+ * @mc_io:	Pointer to opaque I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPMAC object
+ * @cfg:	Returned structure with the link configuration
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_get_link_cfg(struct fsl_mc_io	*mc_io,
+		       uint32_t		cmd_flags,
+		       uint16_t		token,
+		       struct dpmac_link_cfg	*cfg);
+
+/**
+ * struct dpmac_link_state - DPMAC link configuration request
+ * @rate: Rate in Mbps
+ * @options: Enable/Disable DPMAC link cfg features (bitmap)
+ * @up: Link state
+ */
+struct dpmac_link_state {
+	uint32_t	rate;
+	uint64_t	options;
+	int		up;
+};
+
+/**
+ * dpmac_set_link_state() - Set the Ethernet link status
+ * @mc_io:	Pointer to opaque I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPMAC object
+ * @link_state:	Link state configuration
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpmac_set_link_state(struct fsl_mc_io		*mc_io,
+			 uint32_t			cmd_flags,
+			 uint16_t			token,
+			 struct dpmac_link_state	*link_state);
+
+/**
+ * enum dpni_counter - DPNI counter types
+ * @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_127: counts 65- to 127-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_255: counts 128- to 255-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_511: counts 256- to 511-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1023: counts 512- to 1023-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1518: counts 1024- to 1518-octet frame, good or bad.
+ * @DPMAC_CNT_ING_FRAME_1519_MAX: counts 1519-octet frame and larger
+ *				  (up to max frame length specified),
+ *				  good or bad.
+ * @DPMAC_CNT_ING_FRAG: counts packet which is shorter than 64 octets received
+ *			with a wrong CRC
+ * @DPMAC_CNT_ING_JABBER: counts packet longer than the maximum frame length
+ *			  specified, with a bad frame check sequence.
+ * @DPMAC_CNT_ING_FRAME_DISCARD: counts dropped packet due to internal errors.
+ *				 Occurs when a receive FIFO overflows.
+ *				 Includes also packets truncated as a result of
+ *				 the receive FIFO overflow.
+ * @DPMAC_CNT_ING_ALIGN_ERR: counts frame with an alignment error
+ *			     (optional used for wrong SFD)
+ * @DPMAC_CNT_EGR_UNDERSIZED: counts packet transmitted that was less than 64
+ *			      octets long with a good CRC.
+ * @DPMAC_CNT_ING_OVERSIZED: counts packet longer than the maximum frame length
+ *			     specified, with a good frame check sequence.
+ * @DPMAC_CNT_ING_VALID_PAUSE_FRAME: counts valid pause frame (regular and PFC).
+ * @DPMAC_CNT_EGR_VALID_PAUSE_FRAME: counts valid pause frame transmitted
+ *				     (regular and PFC).
+ * @DPMAC_CNT_ING_BYTE: counts octet received except preamble for all valid
+ *				frames and valid pause frames.
+ * @DPMAC_CNT_ING_MCAST_FRAME: counts received multicast frame
+ * @DPMAC_CNT_ING_BCAST_FRAME: counts received broadcast frame
+ * @DPMAC_CNT_ING_ALL_FRAME: counts each good or bad packet received.
+ * @DPMAC_CNT_ING_UCAST_FRAME: counts received unicast frame
+ * @DPMAC_CNT_ING_ERR_FRAME: counts frame received with an error
+ *			     (except for undersized/fragment frame)
+ * @DPMAC_CNT_EGR_BYTE: counts octet transmitted except preamble for all valid
+ *			frames and valid pause frames transmitted.
+ * @DPMAC_CNT_EGR_MCAST_FRAME: counts transmitted multicast frame
+ * @DPMAC_CNT_EGR_BCAST_FRAME: counts transmitted broadcast frame
+ * @DPMAC_CNT_EGR_UCAST_FRAME: counts transmitted unicast frame
+ * @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error
+ * @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including
+ *			      pause frames.
+ */
+enum dpmac_counter {
+	DPMAC_CNT_ING_FRAME_64,
+	DPMAC_CNT_ING_FRAME_127,
+	DPMAC_CNT_ING_FRAME_255,
+	DPMAC_CNT_ING_FRAME_511,
+	DPMAC_CNT_ING_FRAME_1023,
+	DPMAC_CNT_ING_FRAME_1518,
+	DPMAC_CNT_ING_FRAME_1519_MAX,
+	DPMAC_CNT_ING_FRAG,
+	DPMAC_CNT_ING_JABBER,
+	DPMAC_CNT_ING_FRAME_DISCARD,
+	DPMAC_CNT_ING_ALIGN_ERR,
+	DPMAC_CNT_EGR_UNDERSIZED,
+	DPMAC_CNT_ING_OVERSIZED,
+	DPMAC_CNT_ING_VALID_PAUSE_FRAME,
+	DPMAC_CNT_EGR_VALID_PAUSE_FRAME,
+	DPMAC_CNT_ING_BYTE,
+	DPMAC_CNT_ING_MCAST_FRAME,
+	DPMAC_CNT_ING_BCAST_FRAME,
+	DPMAC_CNT_ING_ALL_FRAME,
+	DPMAC_CNT_ING_UCAST_FRAME,
+	DPMAC_CNT_ING_ERR_FRAME,
+	DPMAC_CNT_EGR_BYTE,
+	DPMAC_CNT_EGR_MCAST_FRAME,
+	DPMAC_CNT_EGR_BCAST_FRAME,
+	DPMAC_CNT_EGR_UCAST_FRAME,
+	DPMAC_CNT_EGR_ERR_FRAME,
+	DPMAC_CNT_ING_GOOD_FRAME
+};
+
+/**
+ * dpmac_get_counter() - Read a specific DPMAC counter
+ * @mc_io:	Pointer to opaque I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPMAC object
+ * @type:	The requested counter
+ * @counter:	Returned counter value
+ *
+ * Return:	The requested counter; '0' otherwise.
+ */
+int dpmac_get_counter(struct fsl_mc_io		*mc_io,
+		      uint32_t			cmd_flags,
+		      uint16_t			token,
+		      enum dpmac_counter	 type,
+		      uint64_t			*counter);
+/**
+ * dpmac_get_api_version - Retrieve DPMAC Major and Minor version info.
+ *
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver:	DPMAC major version
+ * @minor_ver:	DPMAC minor version
+ *
+ * Return:     '0' on Success; Error code otherwise.
+ */
+int dpmac_get_api_version(struct fsl_mc_io *mc_io,
+			  uint32_t cmd_flags,
+			  uint16_t *major_ver,
+			  uint16_t *minor_ver);
+
+#endif /* __FSL_DPMAC_H */
diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h
new file mode 100644
index 0000000..2148601
--- /dev/null
+++ b/include/fsl-mc/fsl_dpmng.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Copyright 2013-2015 Freescale Semiconductor Inc.
+ */
+#ifndef __FSL_DPMNG_H
+#define __FSL_DPMNG_H
+
+/* Management Complex General API
+ * Contains general API for the Management Complex firmware
+ */
+
+struct fsl_mc_io;
+
+/**
+ * Management Complex firmware version information
+ */
+#define MC_VER_MAJOR 9
+#define MC_VER_MINOR 0
+
+/**
+ * struct mc_versoin
+ * @major: Major version number: incremented on API compatibility changes
+ * @minor: Minor version number: incremented on API additions (that are
+ *		backward compatible); reset when major version is incremented
+ * @revision: Internal revision number: incremented on implementation changes
+ *		and/or bug fixes that have no impact on API
+ */
+struct mc_version {
+	uint32_t major;
+	uint32_t minor;
+	uint32_t revision;
+};
+
+/**
+ * mc_get_version() - Retrieves the Management Complex firmware
+ *			version information
+ * @mc_io:		Pointer to opaque I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @mc_ver_info:	Returned version information structure
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int mc_get_version(struct fsl_mc_io	*mc_io,
+		   uint32_t		cmd_flags,
+		   struct mc_version	*mc_ver_info);
+
+#endif /* __FSL_DPMNG_H */
diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h
new file mode 100644
index 0000000..96d81d9
--- /dev/null
+++ b/include/fsl-mc/fsl_dpni.h
@@ -0,0 +1,1326 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+#ifndef _FSL_DPNI_H
+#define _FSL_DPNI_H
+
+/* DPNI Version */
+#define DPNI_VER_MAJOR				7
+#define DPNI_VER_MINOR				3
+
+/* Command IDs */
+#define DPNI_CMDID_OPEN				0x8011
+#define DPNI_CMDID_CLOSE			0x8001
+#define DPNI_CMDID_CREATE			0x9011
+#define DPNI_CMDID_DESTROY			0x9811
+#define DPNI_CMDID_GET_API_VERSION              0xa011
+
+#define DPNI_CMDID_ENABLE			0x0021
+#define DPNI_CMDID_DISABLE			0x0031
+#define DPNI_CMDID_GET_ATTR			0x0041
+#define DPNI_CMDID_RESET			0x0051
+
+#define DPNI_CMDID_SET_POOLS			0x2002
+#define DPNI_CMDID_SET_BUFFER_LAYOUT		0x2651
+#define DPNI_CMDID_GET_BUFFER_LAYOUT		0x2641
+#define DPNI_CMDID_SET_ERRORS_BEHAVIOR		0x20B1
+
+#define DPNI_CMDID_GET_QDID			0x2101
+#define DPNI_CMDID_GET_TX_DATA_OFFSET		0x2121
+#define DPNI_CMDID_GET_LINK_STATE		0x2151
+#define DPNI_CMDID_SET_LINK_CFG			0x21A1
+
+#define DPNI_CMDID_SET_PRIM_MAC			0x2241
+#define DPNI_CMDID_GET_PRIM_MAC			0x2251
+#define DPNI_CMDID_ADD_MAC_ADDR			0x2261
+#define DPNI_CMDID_REMOVE_MAC_ADDR		0x2271
+
+#define DPNI_CMDID_GET_STATISTICS		0x25D1
+#define DPNI_CMDID_RESET_STATISTICS		0x25E1
+#define DPNI_CMDID_GET_QUEUE			0x25F1
+#define DPNI_CMDID_SET_QUEUE			0x2601
+#define DPNI_CMDID_SET_TX_CONFIRMATION_MODE	0x2661
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_OPEN(cmd, dpni_id) \
+	MC_CMD_OP(cmd,	 0,	0,	32,	int,	dpni_id)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_PREP_CFG(param, cfg) \
+do { \
+	MC_PREP_OP(param, 0, 0,   32, uint16_t, cfg->adv.options); \
+	MC_PREP_OP(param, 0, 32,   8, uint16_t, cfg->adv.num_queues); \
+	MC_PREP_OP(param, 0, 40,   8, uint16_t, cfg->adv.num_tcs); \
+	MC_PREP_OP(param, 0, 48,   8, uint16_t, cfg->adv.mac_entries); \
+	MC_PREP_OP(param, 1, 0,   8, uint16_t, cfg->adv.vlan_entries); \
+	MC_PREP_OP(param, 1, 16,   8, uint16_t, cfg->adv.qos_entries); \
+	MC_PREP_OP(param, 1, 32,   16, uint16_t, cfg->adv.fs_entries); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_EXT_CFG(param, cfg) \
+do { \
+	MC_EXT_OP(param, 0, 0,   32, uint16_t, cfg->adv.options); \
+	MC_EXT_OP(param, 0, 32,   8, uint16_t, cfg->adv.num_queues); \
+	MC_EXT_OP(param, 0, 40,   8, uint16_t, cfg->adv.num_tcs); \
+	MC_EXT_OP(param, 0, 48,   8, uint16_t, cfg->adv.mac_entries); \
+	MC_EXT_OP(param, 1, 0,   8, uint16_t, cfg->adv.vlan_entries); \
+	MC_EXT_OP(param, 1, 16,   8, uint16_t, cfg->adv.qos_entries); \
+	MC_EXT_OP(param, 1, 32,   16, uint16_t, cfg->adv.fs_entries); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_CREATE(cmd, cfg) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,	32,	uint32_t,  cfg->adv.options); \
+	MC_CMD_OP(cmd, 0, 32,	8,	uint8_t,   cfg->adv.num_queues); \
+	MC_CMD_OP(cmd, 0, 40,	8,	uint8_t,   cfg->adv.num_tcs); \
+	MC_CMD_OP(cmd, 0, 48,	8,	uint8_t,   cfg->adv.mac_entries); \
+	MC_CMD_OP(cmd, 1, 0,	8,	uint8_t,   cfg->adv.vlan_entries); \
+	MC_CMD_OP(cmd, 1, 16,	8,	uint8_t,   cfg->adv.qos_entries); \
+	MC_CMD_OP(cmd, 1, 32,	16,	uint8_t,   cfg->adv.fs_entries); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_POOLS(cmd, cfg) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  8,  uint8_t,  cfg->num_dpbp); \
+	MC_CMD_OP(cmd, 0, 8,  1,  int,      cfg->pools[0].backup_pool); \
+	MC_CMD_OP(cmd, 0, 9,  1,  int,      cfg->pools[1].backup_pool); \
+	MC_CMD_OP(cmd, 0, 10, 1,  int,      cfg->pools[2].backup_pool); \
+	MC_CMD_OP(cmd, 0, 11, 1,  int,      cfg->pools[3].backup_pool); \
+	MC_CMD_OP(cmd, 0, 12, 1,  int,      cfg->pools[4].backup_pool); \
+	MC_CMD_OP(cmd, 0, 13, 1,  int,      cfg->pools[5].backup_pool); \
+	MC_CMD_OP(cmd, 0, 14, 1,  int,      cfg->pools[6].backup_pool); \
+	MC_CMD_OP(cmd, 0, 15, 1,  int,      cfg->pools[7].backup_pool); \
+	MC_CMD_OP(cmd, 0, 32, 32, int,      cfg->pools[0].dpbp_id); \
+	MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\
+	MC_CMD_OP(cmd, 1, 0,  32, int,      cfg->pools[1].dpbp_id); \
+	MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\
+	MC_CMD_OP(cmd, 1, 32, 32, int,      cfg->pools[2].dpbp_id); \
+	MC_CMD_OP(cmd, 5, 0,  16, uint16_t, cfg->pools[2].buffer_size);\
+	MC_CMD_OP(cmd, 2, 0,  32, int,      cfg->pools[3].dpbp_id); \
+	MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\
+	MC_CMD_OP(cmd, 2, 32, 32, int,      cfg->pools[4].dpbp_id); \
+	MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\
+	MC_CMD_OP(cmd, 3, 0,  32, int,      cfg->pools[5].dpbp_id); \
+	MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\
+	MC_CMD_OP(cmd, 3, 32, 32, int,      cfg->pools[6].dpbp_id); \
+	MC_CMD_OP(cmd, 6, 0,  16, uint16_t, cfg->pools[6].buffer_size);\
+	MC_CMD_OP(cmd, 4, 0,  32, int,      cfg->pools[7].dpbp_id); \
+	MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_GET_ATTR(cmd, attr) \
+do { \
+	MC_RSP_OP(cmd, 0, 0,  32, int,	    attr->options);\
+	MC_RSP_OP(cmd, 0, 32,  8,  uint8_t,  attr->max_num_queues); \
+	MC_RSP_OP(cmd, 0, 40,  8,  uint8_t,  attr->max_num_tcs); \
+	MC_RSP_OP(cmd, 0, 48,  8,  uint8_t,  attr->max_mac_entries); \
+	MC_RSP_OP(cmd, 1,  0,  8,  uint8_t,  attr->max_vlan_entries); \
+	MC_RSP_OP(cmd, 1, 16,  8,  uint8_t,  attr->max_qos_entries); \
+	MC_RSP_OP(cmd, 1, 32, 16,  uint16_t,  attr->max_fs_entries); \
+	MC_RSP_OP(cmd, 2,  0,  8,  uint8_t,  attr->max_qos_key_size); \
+	MC_RSP_OP(cmd, 2,  8,  8,  uint8_t,  attr->max_fs_key_size); \
+	MC_RSP_OP(cmd, 2, 16, 16,  uint16_t,  attr->wriop_version); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, uint32_t, cfg->errors); \
+	MC_CMD_OP(cmd, 0, 32, 4,  enum dpni_error_action, cfg->error_action); \
+	MC_CMD_OP(cmd, 0, 36, 1,  int,      cfg->set_frame_annotation); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, queue) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  8, enum dpni_queue_type, queue); \
+	MC_CMD_OP(cmd, 1, 0,  16, uint16_t, layout->private_data_size); \
+	MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_align); \
+	MC_CMD_OP(cmd, 0, 32, 16, uint16_t, layout->options); \
+	MC_CMD_OP(cmd, 0, 48,  1,  int,	    layout->pass_timestamp); \
+	MC_CMD_OP(cmd, 0, 49,  1,  int,	    layout->pass_parser_result); \
+	MC_CMD_OP(cmd, 0, 50,  1,  int,	    layout->pass_frame_status); \
+	MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_head_room); \
+	MC_CMD_OP(cmd, 1, 48, 16, uint16_t, layout->data_tail_room); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_GET_QDID(cmd, qdid) \
+	MC_RSP_OP(cmd, 0, 0,  16, uint16_t, qdid)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_GET_TX_DATA_OFFSET(cmd, data_offset) \
+	MC_RSP_OP(cmd, 0, 0,  16, uint16_t, data_offset)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \
+do { \
+	MC_CMD_OP(cmd, 1, 0,  32, uint32_t, cfg->rate);\
+	MC_CMD_OP(cmd, 2, 0,  64, uint64_t, cfg->options);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_GET_LINK_STATE(cmd, state) \
+do { \
+	MC_RSP_OP(cmd, 0, 32,  1, int,      state->up);\
+	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, state->rate);\
+	MC_RSP_OP(cmd, 2, 0,  64, uint64_t, state->options);\
+} while (0)
+
+
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \
+do { \
+	MC_CMD_OP(cmd, 0, 16, 8,  uint8_t,  mac_addr[5]); \
+	MC_CMD_OP(cmd, 0, 24, 8,  uint8_t,  mac_addr[4]); \
+	MC_CMD_OP(cmd, 0, 32, 8,  uint8_t,  mac_addr[3]); \
+	MC_CMD_OP(cmd, 0, 40, 8,  uint8_t,  mac_addr[2]); \
+	MC_CMD_OP(cmd, 0, 48, 8,  uint8_t,  mac_addr[1]); \
+	MC_CMD_OP(cmd, 0, 56, 8,  uint8_t,  mac_addr[0]); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr) \
+do { \
+	MC_RSP_OP(cmd, 0, 16, 8,  uint8_t,  mac_addr[5]); \
+	MC_RSP_OP(cmd, 0, 24, 8,  uint8_t,  mac_addr[4]); \
+	MC_RSP_OP(cmd, 0, 32, 8,  uint8_t,  mac_addr[3]); \
+	MC_RSP_OP(cmd, 0, 40, 8,  uint8_t,  mac_addr[2]); \
+	MC_RSP_OP(cmd, 0, 48, 8,  uint8_t,  mac_addr[1]); \
+	MC_RSP_OP(cmd, 0, 56, 8,  uint8_t,  mac_addr[0]); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr) \
+do { \
+	MC_CMD_OP(cmd, 0, 16, 8,  uint8_t,  mac_addr[5]); \
+	MC_CMD_OP(cmd, 0, 24, 8,  uint8_t,  mac_addr[4]); \
+	MC_CMD_OP(cmd, 0, 32, 8,  uint8_t,  mac_addr[3]); \
+	MC_CMD_OP(cmd, 0, 40, 8,  uint8_t,  mac_addr[2]); \
+	MC_CMD_OP(cmd, 0, 48, 8,  uint8_t,  mac_addr[1]); \
+	MC_CMD_OP(cmd, 0, 56, 8,  uint8_t,  mac_addr[0]); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr) \
+do { \
+	MC_CMD_OP(cmd, 0, 16, 8,  uint8_t,  mac_addr[5]); \
+	MC_CMD_OP(cmd, 0, 24, 8,  uint8_t,  mac_addr[4]); \
+	MC_CMD_OP(cmd, 0, 32, 8,  uint8_t,  mac_addr[3]); \
+	MC_CMD_OP(cmd, 0, 40, 8,  uint8_t,  mac_addr[2]); \
+	MC_CMD_OP(cmd, 0, 48, 8,  uint8_t,  mac_addr[1]); \
+	MC_CMD_OP(cmd, 0, 56, 8,  uint8_t,  mac_addr[0]); \
+} while (0)
+
+#define DPNI_CMD_GET_QUEUE(cmd, type, tc, index) \
+do { \
+	MC_CMD_OP(cmd, 0,  0,  8, enum dpni_queue_type, type); \
+	MC_CMD_OP(cmd, 0,  8,  8, uint8_t, tc); \
+	MC_CMD_OP(cmd, 0, 16,  8, uint8_t, index); \
+} while (0)
+
+#define DPNI_RSP_GET_QUEUE(cmd, queue) \
+do { \
+	MC_RSP_OP(cmd, 1,  0, 32, uint32_t, (queue)->destination.id); \
+	MC_RSP_OP(cmd, 1, 56,  4, enum dpni_dest, (queue)->destination.type); \
+	MC_RSP_OP(cmd, 1, 62,  1, char, (queue)->destination.stash_ctrl); \
+	MC_RSP_OP(cmd, 1, 63,  1, char, (queue)->destination.hold_active); \
+	MC_RSP_OP(cmd, 2,  0, 64, uint64_t, (queue)->flc); \
+	MC_RSP_OP(cmd, 3,  0, 64, uint64_t, (queue)->user_context); \
+	MC_RSP_OP(cmd, 4,  0, 32, uint32_t, (queue)->fqid); \
+	MC_RSP_OP(cmd, 4, 32, 16, uint16_t, (queue)->qdbin); \
+} while (0)
+
+#define DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue) \
+do { \
+	MC_CMD_OP(cmd, 0,  0,  8, enum dpni_queue_type, type); \
+	MC_CMD_OP(cmd, 0,  8,  8, uint8_t, tc); \
+	MC_CMD_OP(cmd, 0, 16,  8, uint8_t, index); \
+	MC_CMD_OP(cmd, 0, 24,  8, uint8_t, (queue)->options); \
+	MC_CMD_OP(cmd, 1,  0, 32, uint32_t, (queue)->destination.id); \
+	MC_CMD_OP(cmd, 1, 56,  4, enum dpni_dest, (queue)->destination.type); \
+	MC_CMD_OP(cmd, 1, 62,  1, char, (queue)->destination.stash_ctrl); \
+	MC_CMD_OP(cmd, 1, 63,  1, char, (queue)->destination.hold_active); \
+	MC_CMD_OP(cmd, 1,  0, 32, uint32_t, (queue)->destination.id); \
+	MC_CMD_OP(cmd, 2,  0, 64, uint64_t, (queue)->flc); \
+	MC_CMD_OP(cmd, 3,  0, 64, uint64_t, (queue)->user_context); \
+} while (0)
+
+/*			cmd, param, offset, width, type, arg_name */
+#define DPNI_CMD_GET_STATISTICS(cmd, page) \
+	MC_CMD_OP(cmd, 0, 0, 8, uint8_t, page)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPNI_RSP_GET_STATISTICS(cmd, stat) \
+do { \
+	MC_RSP_OP(cmd, 0, 0, 64, uint64_t, (stat)->counter0); \
+	MC_RSP_OP(cmd, 1, 0, 64, uint64_t, (stat)->counter1); \
+	MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (stat)->counter2); \
+	MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (stat)->counter3); \
+	MC_RSP_OP(cmd, 4, 0, 64, uint64_t, (stat)->counter4); \
+	MC_RSP_OP(cmd, 5, 0, 64, uint64_t, (stat)->counter5); \
+	MC_RSP_OP(cmd, 6, 0, 64, uint64_t, (stat)->counter6); \
+} while (0)
+
+enum net_prot {
+	NET_PROT_NONE = 0,
+	NET_PROT_PAYLOAD,
+	NET_PROT_ETH,
+	NET_PROT_VLAN,
+	NET_PROT_IPV4,
+	NET_PROT_IPV6,
+	NET_PROT_IP,
+	NET_PROT_TCP,
+	NET_PROT_UDP,
+	NET_PROT_UDP_LITE,
+	NET_PROT_IPHC,
+	NET_PROT_SCTP,
+	NET_PROT_SCTP_CHUNK_DATA,
+	NET_PROT_PPPOE,
+	NET_PROT_PPP,
+	NET_PROT_PPPMUX,
+	NET_PROT_PPPMUX_SUBFRM,
+	NET_PROT_L2TPV2,
+	NET_PROT_L2TPV3_CTRL,
+	NET_PROT_L2TPV3_SESS,
+	NET_PROT_LLC,
+	NET_PROT_LLC_SNAP,
+	NET_PROT_NLPID,
+	NET_PROT_SNAP,
+	NET_PROT_MPLS,
+	NET_PROT_IPSEC_AH,
+	NET_PROT_IPSEC_ESP,
+	NET_PROT_UDP_ENC_ESP, /* RFC 3948 */
+	NET_PROT_MACSEC,
+	NET_PROT_GRE,
+	NET_PROT_MINENCAP,
+	NET_PROT_DCCP,
+	NET_PROT_ICMP,
+	NET_PROT_IGMP,
+	NET_PROT_ARP,
+	NET_PROT_CAPWAP_DATA,
+	NET_PROT_CAPWAP_CTRL,
+	NET_PROT_RFC2684,
+	NET_PROT_ICMPV6,
+	NET_PROT_FCOE,
+	NET_PROT_FIP,
+	NET_PROT_ISCSI,
+	NET_PROT_GTP,
+	NET_PROT_USER_DEFINED_L2,
+	NET_PROT_USER_DEFINED_L3,
+	NET_PROT_USER_DEFINED_L4,
+	NET_PROT_USER_DEFINED_L5,
+	NET_PROT_USER_DEFINED_SHIM1,
+	NET_PROT_USER_DEFINED_SHIM2,
+
+	NET_PROT_DUMMY_LAST
+};
+
+/**
+ * Data Path Network Interface API
+ * Contains initialization APIs and runtime control APIs for DPNI
+ */
+
+struct fsl_mc_io;
+
+/* General DPNI macros */
+
+/* Maximum number of traffic classes */
+#define DPNI_MAX_TC				8
+/* Maximum number of buffer pools per DPNI */
+#define DPNI_MAX_DPBP				8
+
+/* All traffic classes considered; see dpni_set_rx_flow() */
+#define DPNI_ALL_TCS				(uint8_t)(-1)
+/* All flows within traffic class considered; see dpni_set_rx_flow() */
+#define DPNI_ALL_TC_FLOWS			(uint16_t)(-1)
+/* Generate new flow ID; see dpni_set_tx_flow() */
+#define DPNI_NEW_FLOW_ID			(uint16_t)(-1)
+/* use for common tx-conf queue; see dpni_set_tx_conf_<x>() */
+#define DPNI_COMMON_TX_CONF			(uint16_t)(-1)
+
+/**
+ * dpni_open() - Open a control session for the specified object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @dpni_id:	DPNI unique ID
+ * @token:	Returned token; use in subsequent API calls
+ *
+ * This function can be used to open a control session for an
+ * already created object; an object may have been declared in
+ * the DPL or by calling the dpni_create() function.
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent commands for
+ * this specific object.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_open(struct fsl_mc_io	*mc_io,
+	      uint32_t		cmd_flags,
+	      int		dpni_id,
+	      uint16_t		*token);
+
+/**
+ * dpni_close() - Close the control session of the object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_close(struct fsl_mc_io	*mc_io,
+	       uint32_t		cmd_flags,
+	       uint16_t		token);
+
+/* DPNI configuration options */
+
+/**
+ * Allow different distribution key profiles for different traffic classes;
+ * if not set, a single key profile is assumed
+ */
+#define DPNI_OPT_ALLOW_DIST_KEY_PER_TC		0x00000001
+
+/**
+ * Disable all non-error transmit confirmation; error frames are reported
+ * back to a common Tx error queue
+ */
+#define DPNI_OPT_TX_CONF_DISABLED		0x00000002
+
+/* Disable per-sender private Tx confirmation/error queue */
+#define DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED	0x00000004
+
+/**
+ * Support distribution based on hashed key;
+ * allows statistical distribution over receive queues in a traffic class
+ */
+#define DPNI_OPT_DIST_HASH			0x00000010
+
+/**
+ * Support distribution based on flow steering;
+ * allows explicit control of distribution over receive queues in a traffic
+ * class
+ */
+#define DPNI_OPT_DIST_FS			0x00000020
+
+/* Unicast filtering support */
+#define DPNI_OPT_UNICAST_FILTER			0x00000080
+/* Multicast filtering support */
+#define DPNI_OPT_MULTICAST_FILTER		0x00000100
+/* VLAN filtering support */
+#define DPNI_OPT_VLAN_FILTER			0x00000200
+/* Support IP reassembly on received packets */
+#define DPNI_OPT_IPR				0x00000800
+/* Support IP fragmentation on transmitted packets */
+#define DPNI_OPT_IPF				0x00001000
+/* VLAN manipulation support */
+#define DPNI_OPT_VLAN_MANIPULATION		0x00010000
+/* Support masking of QoS lookup keys */
+#define DPNI_OPT_QOS_MASK_SUPPORT		0x00020000
+/* Support masking of Flow Steering lookup keys */
+#define DPNI_OPT_FS_MASK_SUPPORT		0x00040000
+
+/**
+ * enum dpni_queue_type - Identifies a type of queue targeted by the command
+ * @DPNI_QUEUE_RX: Rx queue
+ * @DPNI_QUEUE_TX: Tx queue
+ * @DPNI_QUEUE_TX_CONFIRM: Tx confirmation queue
+ * @DPNI_QUEUE_RX_ERR: Rx error queue
+ */
+enum dpni_queue_type {
+	DPNI_QUEUE_RX,
+	DPNI_QUEUE_TX,
+	DPNI_QUEUE_TX_CONFIRM,
+	DPNI_QUEUE_RX_ERR,
+};
+
+struct dpni_cfg {
+		uint8_t mac_addr[6];
+	struct {
+		uint32_t		options;
+		uint16_t		fs_entries;
+		uint8_t			num_queues;
+		uint8_t			num_tcs;
+		uint8_t			mac_entries;
+		uint8_t			vlan_entries;
+		uint8_t			qos_entries;
+	} adv;
+};
+
+/**
+ * struct dpni_extended_cfg - Structure representing extended DPNI configuration
+ * @tc_cfg: TCs configuration
+ * @ipr_cfg: IP reassembly configuration
+ */
+struct dpni_extended_cfg {
+	/**
+	 * struct tc_cfg - TC configuration
+	 * @max_dist: Maximum distribution size for Rx traffic class;
+	 *	supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96,
+	 *	112,128,192,224,256,384,448,512,768,896,1024;
+	 *	value '0' will be treated as '1'.
+	 *	other unsupported values will be round down to the nearest
+	 *	supported value.
+	 * @max_fs_entries: Maximum FS entries for Rx traffic class;
+	 *	'0' means no support for this TC;
+	 */
+	struct {
+		uint16_t	max_dist;
+		uint16_t	max_fs_entries;
+	} tc_cfg[DPNI_MAX_TC];
+	/**
+	 * struct ipr_cfg - Structure representing IP reassembly configuration
+	 * @max_reass_frm_size: Maximum size of the reassembled frame
+	 * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments
+	 * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments
+	 * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly
+	 *		process
+	 * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly
+	 *		process
+	 */
+	struct {
+		uint16_t max_reass_frm_size;
+		uint16_t min_frag_size_ipv4;
+		uint16_t min_frag_size_ipv6;
+		uint16_t max_open_frames_ipv4;
+		uint16_t max_open_frames_ipv6;
+	} ipr_cfg;
+};
+
+/**
+ * dpni_prepare_cfg() - function prepare parameters
+ * @cfg: cfg structure
+ * @cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA
+ *
+ * This function has to be called before dpni_create()
+ */
+int dpni_prepare_cfg(const struct dpni_cfg	*cfg,
+		     uint8_t			*cfg_buf);
+/**
+ * dpni_create() - Create the DPNI object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @token:	Authentication token.
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @cfg:	Configuration structure
+ * @obj_id:	Returned obj_id; use in subsequent API calls
+ *
+ * Create the DPNI object, allocate required resources and
+ * perform required initialization.
+ *
+ * The object can be created either by declaring it in the
+ * DPL file, or by calling this function.
+ *
+ * This function returns a unique authentication token,
+ * associated with the specific object ID and the specific MC
+ * portal; this token must be used in all subsequent calls to
+ * this specific object. For objects that are created using the
+ * DPL file, call dpni_open() function to get an authentication
+ * token first.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_create(struct fsl_mc_io	*mc_io,
+		uint16_t		token,
+		uint32_t		cmd_flags,
+		const struct dpni_cfg	*cfg,
+		uint32_t		*obj_id);
+
+/**
+ * dpni_destroy() - Destroy the DPNI object and release all its resources.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @token:	Authentication token.
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @obj_id:	Returned obj_id; use in subsequent API calls
+ *
+ * Return:	'0' on Success; error code otherwise.
+ */
+int dpni_destroy(struct fsl_mc_io	*mc_io,
+		 uint16_t		token,
+		 uint32_t		cmd_flags,
+		 uint32_t		obj_id);
+
+/**
+ * struct dpni_pools_cfg - Structure representing buffer pools configuration
+ * @num_dpbp: Number of DPBPs
+ * @pools: Array of buffer pools parameters; The number of valid entries
+ *	must match 'num_dpbp' value
+ */
+struct dpni_pools_cfg {
+	uint8_t num_dpbp;
+	/**
+	 * struct pools - Buffer pools parameters
+	 * @dpbp_id: DPBP object ID
+	 * @buffer_size: Buffer size
+	 * @backup_pool: Backup pool
+	 */
+	struct {
+		int		dpbp_id;
+		uint16_t	buffer_size;
+		int		backup_pool;
+	} pools[DPNI_MAX_DPBP];
+};
+
+/**
+ * dpni_set_pools() - Set buffer pools configuration
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @cfg:	Buffer pools configuration
+ *
+ * mandatory for DPNI operation
+ * warning:Allowed only when DPNI is disabled
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_set_pools(struct fsl_mc_io		*mc_io,
+		   uint32_t			cmd_flags,
+		   uint16_t			token,
+		   const struct dpni_pools_cfg	*cfg);
+
+/**
+ * dpni_enable() - Enable the DPNI, allow sending and receiving frames.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:		Token of DPNI object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_enable(struct fsl_mc_io	*mc_io,
+		uint32_t		cmd_flags,
+		uint16_t		token);
+
+/**
+ * dpni_disable() - Disable the DPNI, stop sending and receiving frames.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_disable(struct fsl_mc_io	*mc_io,
+		 uint32_t		cmd_flags,
+		 uint16_t		token);
+
+
+/**
+ * dpni_reset() - Reset the DPNI, returns the object to initial state.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_reset(struct fsl_mc_io	*mc_io,
+	       uint32_t		cmd_flags,
+	       uint16_t		token);
+
+/**
+ * struct dpni_attr - Structure representing DPNI attributes
+ * @options: Mask of available options; reflects the value as was given in
+ *		object's creation
+ * @max_num_queues: Number of queues available (for both Tx and Rx)
+ * @max_num_tcs: Maximum number of traffic classes (for both Tx and Rx)
+ * @max_mac_entries: Maximum number of traffic classes (for both Tx and Rx)
+ * @max_unicast_filters: Maximum number of unicast filters
+ * @max_multicast_filters: Maximum number of multicast filters
+ * @max_vlan_entries: Maximum number of VLAN filters
+ * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in QoS table
+ * @max_fs_entries: declares the maximum entries in flow steering table
+ * @max_qos_key_size: Maximum key size for the QoS look-up
+ * @max_fs_key_size: Maximum key size for the flow steering
+ * @wriop_version: Indicates revision of WRIOP hardware block
+ */
+struct dpni_attr {
+	uint32_t id;
+	uint32_t options;
+	uint8_t max_num_queues;
+	uint8_t max_num_tcs;
+	uint8_t max_mac_entries;
+	uint8_t max_vlan_entries;
+	uint8_t max_qos_entries;
+	uint16_t max_fs_entries;
+	uint8_t max_qos_key_size;
+	uint8_t max_fs_key_size;
+	uint16_t wriop_version;
+};
+
+/**
+ * dpni_get_attributes() - Retrieve DPNI attributes.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @attr:	Object's attributes
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_attributes(struct fsl_mc_io	*mc_io,
+			uint32_t		cmd_flags,
+			uint16_t		token,
+			struct dpni_attr	*attr);
+
+/**
+ * dpni_extract_cfg() - extract the parameters
+ * @cfg: cfg structure
+ * @cfg_buf: 256 bytes of DMA-able memory
+ *
+ * This function has to be called after dpni_get_attributes()
+ */
+int dpni_extract_cfg(struct dpni_cfg	*cfg,
+		     const uint8_t	*cfg_buf);
+
+/**
+ * DPNI errors
+ */
+
+/**
+ * Extract out of frame header error
+ */
+#define DPNI_ERROR_EOFHE	0x00020000
+/**
+ * Frame length error
+ */
+#define DPNI_ERROR_FLE		0x00002000
+/**
+ * Frame physical error
+ */
+#define DPNI_ERROR_FPE		0x00001000
+/**
+ * Parsing header error
+ */
+#define DPNI_ERROR_PHE		0x00000020
+/**
+ * Parser L3 checksum error
+ */
+#define DPNI_ERROR_L3CE		0x00000004
+/**
+ * Parser L3 checksum error
+ */
+#define DPNI_ERROR_L4CE		0x00000001
+
+/**
+ * enum dpni_error_action - Defines DPNI behavior for errors
+ * @DPNI_ERROR_ACTION_DISCARD: Discard the frame
+ * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow
+ * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue
+ */
+enum dpni_error_action {
+	DPNI_ERROR_ACTION_DISCARD = 0,
+	DPNI_ERROR_ACTION_CONTINUE = 1,
+	DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2
+};
+
+/**
+ * struct dpni_error_cfg - Structure representing DPNI errors treatment
+ * @errors: Errors mask; use 'DPNI_ERROR__<X>
+ * @error_action: The desired action for the errors mask
+ * @set_frame_annotation: Set to '1' to mark the errors in frame annotation
+ *		status (FAS); relevant only for the non-discard action
+ */
+struct dpni_error_cfg {
+	uint32_t		errors;
+	enum dpni_error_action	error_action;
+	int			set_frame_annotation;
+};
+
+/**
+ * dpni_set_errors_behavior() - Set errors behavior
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @cfg:	Errors configuration
+ *
+ * this function may be called numerous times with different
+ * error masks
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_set_errors_behavior(struct fsl_mc_io		*mc_io,
+			     uint32_t			cmd_flags,
+			     uint16_t			token,
+			     struct dpni_error_cfg	*cfg);
+
+/* DPNI buffer layout modification options */
+
+/* Select to modify the time-stamp setting */
+#define DPNI_BUF_LAYOUT_OPT_TIMESTAMP		0x00000001
+/* Select to modify the parser-result setting; not applicable for Tx */
+#define DPNI_BUF_LAYOUT_OPT_PARSER_RESULT	0x00000002
+/* Select to modify the frame-status setting */
+#define DPNI_BUF_LAYOUT_OPT_FRAME_STATUS	0x00000004
+/* Select to modify the private-data-size setting */
+#define DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE	0x00000008
+/* Select to modify the data-alignment setting */
+#define DPNI_BUF_LAYOUT_OPT_DATA_ALIGN		0x00000010
+/* Select to modify the data-head-room setting */
+#define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM	0x00000020
+/*!< Select to modify the data-tail-room setting */
+#define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM	0x00000040
+
+/**
+ * struct dpni_buffer_layout - Structure representing DPNI buffer layout
+ * @options: Flags representing the suggested modifications to the buffer
+ *		layout; Use any combination of 'DPNI_BUF_LAYOUT_OPT_<X>' flags
+ * @pass_timestamp: Pass timestamp value
+ * @pass_parser_result: Pass parser results
+ * @pass_frame_status: Pass frame status
+ * @private_data_size: Size kept for private data (in bytes)
+ * @data_align: Data alignment
+ * @data_head_room: Data head room
+ * @data_tail_room: Data tail room
+ */
+struct dpni_buffer_layout {
+	uint16_t options;
+	int pass_timestamp;
+	int pass_parser_result;
+	int pass_frame_status;
+	uint16_t private_data_size;
+	uint16_t data_align;
+	uint16_t data_head_room;
+	uint16_t data_tail_room;
+};
+
+/**
+ * dpni_get_buffer_layout() - Retrieve buffer layout attributes.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @layout:	Returns buffer layout attributes
+ * @type:	DPNI queue type
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_buffer_layout(struct fsl_mc_io			*mc_io,
+			   uint32_t				cmd_flags,
+			   uint16_t				token,
+			   const struct dpni_buffer_layout	*layout,
+			   enum dpni_queue_type			type);
+
+/**
+ * dpni_set_buffer_layout() - Set buffer layout configuration.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @layout:	Buffer layout configuration
+ * @type:	DPNI queue type
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ *
+ * @warning	Allowed only when DPNI is disabled
+ */
+int dpni_set_buffer_layout(struct fsl_mc_io			*mc_io,
+			   uint32_t				cmd_flags,
+			   uint16_t				token,
+			   const struct dpni_buffer_layout	*layout,
+			   enum dpni_queue_type			type);
+
+/**
+ * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used
+ *			for enqueue operations
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @qdid:	Returned virtual QDID value that should be used as an argument
+ *			in all enqueue operations
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_qdid(struct fsl_mc_io	*mc_io,
+		  uint32_t		cmd_flags,
+		  uint16_t		token,
+		  uint16_t		*qdid);
+
+/**
+ * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer)
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @data_offset: Tx data offset (from start of buffer)
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_tx_data_offset(struct fsl_mc_io	*mc_io,
+			    uint32_t		cmd_flags,
+			    uint16_t		token,
+			    uint16_t		*data_offset);
+
+/* Enable auto-negotiation */
+#define DPNI_LINK_OPT_AUTONEG		0x0000000000000001ULL
+/* Enable half-duplex mode */
+#define DPNI_LINK_OPT_HALF_DUPLEX	0x0000000000000002ULL
+/* Enable pause frames */
+#define DPNI_LINK_OPT_PAUSE		0x0000000000000004ULL
+/* Enable a-symmetric pause frames */
+#define DPNI_LINK_OPT_ASYM_PAUSE	0x0000000000000008ULL
+
+/**
+ * struct - Structure representing DPNI link configuration
+ * @rate: Rate
+ * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values
+ */
+struct dpni_link_cfg {
+	uint32_t rate;
+	uint64_t options;
+};
+
+/**
+ * dpni_set_link_cfg() - set the link configuration.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @cfg:	Link configuration
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_set_link_cfg(struct fsl_mc_io			*mc_io,
+		      uint32_t				cmd_flags,
+		      uint16_t				token,
+		      const struct dpni_link_cfg	*cfg);
+
+/**
+ * struct dpni_link_state - Structure representing DPNI link state
+ * @rate: Rate
+ * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values
+ * @up: Link state; '0' for down, '1' for up
+ */
+struct dpni_link_state {
+	uint32_t rate;
+	uint64_t options;
+	int up;
+};
+
+/**
+ * dpni_get_link_state() - Return the link state (either up or down)
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @state:	Returned link state;
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_link_state(struct fsl_mc_io	*mc_io,
+			uint32_t		cmd_flags,
+			uint16_t		token,
+			struct dpni_link_state	*state);
+
+/**
+ * dpni_set_primary_mac_addr() - Set the primary MAC address
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @mac_addr:	MAC address to set as primary address
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io,
+			      uint32_t		cmd_flags,
+			      uint16_t		token,
+			      const uint8_t	mac_addr[6]);
+
+/**
+ * dpni_get_primary_mac_addr() - Get the primary MAC address
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @mac_addr:	Returned MAC address
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_primary_mac_addr(struct fsl_mc_io	*mc_io,
+			      uint32_t		cmd_flags,
+			      uint16_t		token,
+			      uint8_t		mac_addr[6]);
+
+/**
+ * dpni_add_mac_addr() - Add MAC address filter
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @mac_addr:	MAC address to add
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_add_mac_addr(struct fsl_mc_io	*mc_io,
+		      uint32_t		cmd_flags,
+		      uint16_t		token,
+		      const uint8_t	mac_addr[6]);
+
+/**
+ * dpni_remove_mac_addr() - Remove MAC address filter
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @mac_addr:	MAC address to remove
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_remove_mac_addr(struct fsl_mc_io	*mc_io,
+			 uint32_t		cmd_flags,
+			 uint16_t		token,
+			 const uint8_t		mac_addr[6]);
+
+/**
+ * enum dpni_dest - DPNI destination types
+ * @DPNI_DEST_NONE: Unassigned destination; The queue is set in parked mode and
+ *		does not generate FQDAN notifications; user is expected to
+ *		dequeue from the queue based on polling or other user-defined
+ *		method
+ * @DPNI_DEST_DPIO: The queue is set in schedule mode and generates FQDAN
+ *		notifications to the specified DPIO; user is expected to dequeue
+ *		from the queue only after notification is received
+ * @DPNI_DEST_DPCON: The queue is set in schedule mode and does not generate
+ *		FQDAN notifications, but is connected to the specified DPCON
+ *		object; user is expected to dequeue from the DPCON channel
+ */
+enum dpni_dest {
+	DPNI_DEST_NONE = 0,
+	DPNI_DEST_DPIO = 1,
+	DPNI_DEST_DPCON = 2
+};
+
+/**
+ * struct dpni_dest_cfg - Structure representing DPNI destination parameters
+ * @dest_type: Destination type
+ * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type
+ * @priority: Priority selection within the DPIO or DPCON channel; valid values
+ *		are 0-1 or 0-7, depending on the number of priorities in that
+ *		channel; not relevant for 'DPNI_DEST_NONE' option
+ */
+struct dpni_dest_cfg {
+	enum dpni_dest dest_type;
+	int dest_id;
+	uint8_t priority;
+};
+
+/**
+ * enum dpni_flc_type - DPNI FLC types
+ * @DPNI_FLC_USER_DEFINED: select the FLC to be used for user defined value
+ * @DPNI_FLC_STASH: select the FLC to be used for stash control
+ */
+enum dpni_flc_type {
+	DPNI_FLC_USER_DEFINED = 0,
+	DPNI_FLC_STASH = 1,
+};
+
+/**
+ * enum dpni_stash_size - DPNI FLC stashing size
+ * @DPNI_STASH_SIZE_0B: no stash
+ * @DPNI_STASH_SIZE_64B: stashes 64 bytes
+ * @DPNI_STASH_SIZE_128B: stashes 128 bytes
+ * @DPNI_STASH_SIZE_192B: stashes 192 bytes
+ */
+enum dpni_stash_size {
+	DPNI_STASH_SIZE_0B = 0,
+	DPNI_STASH_SIZE_64B = 1,
+	DPNI_STASH_SIZE_128B = 2,
+	DPNI_STASH_SIZE_192B = 3,
+};
+
+/* DPNI FLC stash options */
+
+/* stashes the whole annotation area (up to 192 bytes) */
+#define DPNI_FLC_STASH_FRAME_ANNOTATION	0x00000001
+
+/**
+ * struct dpni_flc_cfg - Structure representing DPNI FLC configuration
+ * @flc_type: FLC type
+ * @options: Mask of available options;
+ *	use 'DPNI_FLC_STASH_<X>' values
+ * @frame_data_size: Size of frame data to be stashed
+ * @flow_context_size: Size of flow context to be stashed
+ * @flow_context: 1. In case flc_type is 'DPNI_FLC_USER_DEFINED':
+ *			this value will be provided in the frame descriptor
+ *			(FD[FLC])
+ *		  2. In case flc_type is 'DPNI_FLC_STASH':
+ *			this value will be I/O virtual address of the
+ *			flow-context;
+ *			Must be cacheline-aligned and DMA-able memory
+ */
+struct dpni_flc_cfg {
+	enum dpni_flc_type flc_type;
+	uint32_t options;
+	enum dpni_stash_size frame_data_size;
+	enum dpni_stash_size flow_context_size;
+	uint64_t flow_context;
+};
+
+/* DPNI queue modification options */
+
+/* Select to modify the user's context associated with the queue */
+#define DPNI_QUEUE_OPT_USER_CTX		0x00000001
+/* Select to modify the queue's destination */
+#define DPNI_QUEUE_OPT_DEST		0x00000002
+/** Select to modify the flow-context parameters;
+ * not applicable for Tx-conf/Err queues as the FD comes from the user
+ */
+#define DPNI_QUEUE_OPT_FLC		0x00000004
+/* Select to modify the queue's order preservation */
+#define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008
+/* Select to modify the queue's tail-drop threshold */
+#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010
+
+/**
+ * struct dpni_queue_cfg - Structure representing queue configuration
+ * @options: Flags representing the suggested modifications to the queue;
+ *		Use any combination of 'DPNI_QUEUE_OPT_<X>' flags
+ * @user_ctx: User context value provided in the frame descriptor of each
+ *		dequeued frame; valid only if 'DPNI_QUEUE_OPT_USER_CTX'
+ *		is contained in 'options'
+ * @dest_cfg: Queue destination parameters;
+ *		valid only if 'DPNI_QUEUE_OPT_DEST' is contained in 'options'
+ * @flc_cfg: Flow context configuration; in case the TC's distribution
+ *		is either NONE or HASH the FLC's settings of flow#0 are used.
+ *		in the case of FS (flow-steering) the flow's FLC settings
+ *		are used.
+ *		valid only if 'DPNI_QUEUE_OPT_FLC' is contained in 'options'
+ * @order_preservation_en: enable/disable order preservation;
+ *		valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained
+ *		in 'options'
+ * @tail_drop_threshold: set the queue's tail drop threshold in bytes;
+ *		'0' value disable the threshold; maximum value is 0xE000000;
+ *		valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained
+ *		in 'options'
+ */
+struct dpni_queue_cfg {
+	uint32_t options;
+	uint64_t user_ctx;
+	struct dpni_dest_cfg dest_cfg;
+	struct dpni_flc_cfg flc_cfg;
+	int order_preservation_en;
+	uint32_t tail_drop_threshold;
+};
+
+/**
+ * struct dpni_queue_attr - Structure representing queue attributes
+ * @user_ctx: User context value provided in the frame descriptor of each
+ *	dequeued frame
+ * @dest_cfg: Queue destination configuration
+ * @flc_cfg: Flow context configuration
+ * @order_preservation_en: enable/disable order preservation
+ * @tail_drop_threshold: queue's tail drop threshold in bytes;
+ * @fqid: Virtual fqid value to be used for dequeue operations
+ */
+struct dpni_queue_attr {
+	uint64_t user_ctx;
+	struct dpni_dest_cfg dest_cfg;
+	struct dpni_flc_cfg flc_cfg;
+	int order_preservation_en;
+	uint32_t tail_drop_threshold;
+	uint32_t fqid;
+};
+
+/* DPNI Tx flow modification options */
+
+/* Select to modify the settings for dedicate Tx confirmation/error */
+#define DPNI_TX_FLOW_OPT_TX_CONF_ERROR	0x00000001
+/*!< Select to modify the L3 checksum generation setting */
+#define DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN	0x00000010
+/*!< Select to modify the L4 checksum generation setting */
+#define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN	0x00000020
+
+/**
+ * dpni_get_api_version - Retrieve DPNI Major and Minor version info.
+ *
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver:	DPNI major version
+ * @minor_ver:	DPNI minor version
+ *
+ * Return:     '0' on Success; Error code otherwise.
+ */
+int dpni_get_api_version(struct fsl_mc_io *mc_io,
+			 u32 cmd_flags,
+			 u16 *major_ver,
+			 u16 *minor_ver);
+
+/**
+ * enum dpni_confirmation_mode - Defines DPNI options supported for Tx
+ * confirmation
+ * @DPNI_CONF_AFFINE: For each Tx queue set associated with a sender there is
+ * an affine Tx Confirmation queue
+ * @DPNI_CONF_SINGLE: All Tx queues are associated with a single Tx
+ * confirmation queue
+ * @DPNI_CONF_DISABLE: Tx frames are not confirmed.  This must be associated
+ * with proper FD set-up to have buffers release to a Buffer Pool, otherwise
+ * buffers will be leaked.
+ */
+enum dpni_confirmation_mode {
+	DPNI_CONF_AFFINE,
+	DPNI_CONF_SINGLE,
+	DPNI_CONF_DISABLE,
+};
+
+struct dpni_tx_confirmation_mode {
+	uint32_t pad;
+	uint8_t confirmation_mode;
+};
+
+/**
+ * struct dpni_queue - Queue structure
+ * @fqid:  FQID used for enqueueing to and/or configuration of this specific FQ
+ * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. Only relevant
+ *         for Tx queues.
+ * @flc:   FLC value for traffic dequeued from this queue.
+ * @user_context:    User data, presented to the user along with any frames
+ *                   from this queue. Not relevant for Tx queues.
+ */
+struct dpni_queue {
+	/**
+	* struct destination - Destination structure
+	* @id:   ID of the destination, only relevant if DEST_TYPE is > 0.
+	*        Identifies either a DPIO or a DPCON object. Not relevant for Tx
+	*        queues.
+	* @type: May be one of the following:
+	*         0 - No destination, queue can be manually queried, but won't
+	*             push traffic or notifications to a DPIO;
+	*         1 - The destination is DPIO. When traffic becomes available in
+	*             the queue a FQDAN (FQ data available notification) will be
+	*             generated to selected DPIO;
+	*         2 - The destination is a DPCON. The queue is associated with a
+	*             DPCON object for purpose of scheduling between multiple
+	*             queues. The DPCON may be independently configured to
+	*             generate notifications. Not relevant for Tx queues.
+	* @hold_active: Hold active
+	*/
+	struct {
+		uint32_t id;
+		enum dpni_dest type;
+		char hold_active;
+		char stash_ctrl;
+	} destination;
+	uint8_t  options;
+	uint32_t fqid;
+	uint16_t qdbin;
+	uint64_t flc;
+	uint64_t user_context;
+};
+
+/**
+ * dpni_set_queue() - Set queue parameters
+ * @mc_io:      Pointer to MC portal's I/O object
+ * @cmd_flags:  Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:      Token of DPNI object
+ * @type:       Type of queue
+ * @tc:         Traffic class, in range 0 to NUM_TCS - 1
+ * @index:      Selects the specific queue out of the set allocated for the same
+ *              TC. Value must be in range 0 to NUM_QUEUES - 1
+ * @queue:      Queue structure
+ *
+ * Return:     '0' on Success; Error code otherwise.
+ */
+int dpni_set_queue(struct fsl_mc_io		*mc_io,
+		   uint32_t			cmd_flags,
+		   uint16_t			token,
+		   enum dpni_queue_type		type,
+		   uint8_t			tc,
+		   uint8_t			index,
+		   const struct dpni_queue	*queue);
+
+/**
+ * dpni_get_queue() - Get queue parameters
+ * @mc_io:      Pointer to MC portal's I/O object
+ * @cmd_flags:  Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:      Token of DPNI object
+ * @type:       Type of queue
+ * @tc:         Traffic class, in range 0 to NUM_TCS - 1
+ * @index:      Selects the specific queue out of the set allocated for the same
+ *              TC. Value must be in range 0 to NUM_QUEUES - 1
+ * @queue:      Queue structure
+ *
+ * Return:      '0' on Success; Error code otherwise.
+ */
+int dpni_get_queue(struct fsl_mc_io		*mc_io,
+		   uint32_t			cmd_flags,
+		   uint16_t			token,
+		   enum dpni_queue_type		type,
+		   uint8_t			tc,
+		   uint8_t			index,
+		   struct dpni_queue		*queue);
+
+/**
+ * dpni_set_tx_confirmation_mode() - Set TX conf mode
+ * @mc_io:      Pointer to MC portal's I/O object
+ * @cmd_flags:  Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:      Token of DPNI object
+ * @mode:       DPNI confirmation mode type
+ *
+ * Return:      '0' on Success; Error code otherwise.
+ */
+int dpni_set_tx_confirmation_mode(struct fsl_mc_io	*mc_io,
+				  uint32_t		cmd_flags,
+				  uint16_t		token,
+				  enum dpni_confirmation_mode mode);
+struct dpni_statistics {
+	/**
+	 * Page_0 statistics structure
+	 * @ingress_all_frames: Ingress frame count
+	 * @ingress_all_bytes: Ingress byte count
+	 * @ingress_multicast_frames: Ingress multicast frame count
+	 * @ingress_multicast_bytes: Ingress multicast byte count
+	 * @ingress_broadcast_frames: Ingress broadcast frame count
+	 * @ingress_broadcast_bytes: Ingress broadcast byte count
+	 *
+	 * Page_1 statistics structure
+	 * @egress_all_frames: Egress frame count
+	 * @egress_all_bytes: Egress byte count
+	 * @egress_multicast_frames: Egress multicast frame count
+	 * @egress_multicast_bytes: Egress multicast byte count
+	 * @egress_broadcast_frames: Egress broadcast frame count
+	 * @egress_broadcast_bytes: Egress broadcast byte count
+	 *
+	 * Page_2 statistics structure
+	 * @ingress_filtered_frames: Ingress filtered frame count
+	 * @ingress_discarded_frames: Ingress discarded frame count
+	 * @ingress_nobuffer_discards: Ingress discarded frame count due to
+	 *  lack of buffers.
+	 * @egress_discarded_frames: Egress discarded frame count
+	 * @egress_confirmed_frames: Egress confirmed frame count
+	 */
+
+	uint64_t counter0;
+	uint64_t counter1;
+	uint64_t counter2;
+	uint64_t counter3;
+	uint64_t counter4;
+	uint64_t counter5;
+	uint64_t counter6;
+};
+
+/**
+ * dpni_get_statistics() - Get DPNI statistics
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ * @page:	Selects the statistics page to retrieve, see DPNI_GET_STATISTICS
+ *		output. Pages are numbered 0 to 2.
+ * @stat:	Structure containing the statistics
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_get_statistics(struct fsl_mc_io *mc_io,
+			uint32_t cmd_flags,
+			uint16_t token,
+			uint8_t page,
+			struct dpni_statistics *stat);
+
+/**
+ * dpni_reset_statistics() - Clears DPNI statistics
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPNI object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dpni_reset_statistics(struct fsl_mc_io *mc_io,
+			  uint32_t cmd_flags,
+			  uint16_t token);
+#endif /* _FSL_DPNI_H */
diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h
new file mode 100644
index 0000000..950ecb0
--- /dev/null
+++ b/include/fsl-mc/fsl_dprc.h
@@ -0,0 +1,957 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale Layerscape MC I/O wrapper
+ *
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+#ifndef _FSL_DPRC_H
+#define _FSL_DPRC_H
+
+/* DPRC Version */
+#define DPRC_VER_MAJOR				6
+#define DPRC_VER_MINOR				1
+
+/* Command IDs */
+#define DPRC_CMDID_CLOSE			0x8001
+#define DPRC_CMDID_OPEN				0x8051
+#define DPRC_CMDID_CREATE			0x9051
+
+#define DPRC_CMDID_GET_ATTR			0x0041
+#define DPRC_CMDID_RESET_CONT			0x0051
+#define DPRC_CMDID_GET_API_VERSION              0xa051
+
+#define DPRC_CMDID_CREATE_CONT			0x1511
+#define DPRC_CMDID_DESTROY_CONT			0x1521
+#define DPRC_CMDID_GET_CONT_ID			0x8301
+#define DPRC_CMDID_GET_OBJ_COUNT		0x1591
+#define DPRC_CMDID_GET_OBJ			0x15A1
+#define DPRC_CMDID_GET_RES_COUNT		0x15B1
+#define DPRC_CMDID_GET_RES_IDS			0x15C1
+#define DPRC_CMDID_GET_OBJ_REG			0x15E1
+
+#define DPRC_CMDID_CONNECT			0x1671
+#define DPRC_CMDID_DISCONNECT			0x1681
+#define DPRC_CMDID_GET_CONNECTION		0x16C1
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_GET_CONTAINER_ID(cmd, container_id) \
+	MC_RSP_OP(cmd, 0, 0,  32,  int,	    container_id)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_OPEN(cmd, container_id) \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    container_id)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_CREATE_CONTAINER(cmd, cfg) \
+do { \
+	MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \
+	MC_CMD_OP(cmd, 0, 0,  32, uint32_t, cfg->options); \
+	MC_CMD_OP(cmd, 1, 32, 32, int,	    cfg->portal_id); \
+	MC_CMD_OP(cmd, 2, 0,  8,  char,	    cfg->label[0]);\
+	MC_CMD_OP(cmd, 2, 8,  8,  char,	    cfg->label[1]);\
+	MC_CMD_OP(cmd, 2, 16, 8,  char,	    cfg->label[2]);\
+	MC_CMD_OP(cmd, 2, 24, 8,  char,	    cfg->label[3]);\
+	MC_CMD_OP(cmd, 2, 32, 8,  char,	    cfg->label[4]);\
+	MC_CMD_OP(cmd, 2, 40, 8,  char,	    cfg->label[5]);\
+	MC_CMD_OP(cmd, 2, 48, 8,  char,	    cfg->label[6]);\
+	MC_CMD_OP(cmd, 2, 56, 8,  char,	    cfg->label[7]);\
+	MC_CMD_OP(cmd, 3, 0,  8,  char,	    cfg->label[8]);\
+	MC_CMD_OP(cmd, 3, 8,  8,  char,	    cfg->label[9]);\
+	MC_CMD_OP(cmd, 3, 16, 8,  char,	    cfg->label[10]);\
+	MC_CMD_OP(cmd, 3, 24, 8,  char,	    cfg->label[11]);\
+	MC_CMD_OP(cmd, 3, 32, 8,  char,	    cfg->label[12]);\
+	MC_CMD_OP(cmd, 3, 40, 8,  char,	    cfg->label[13]);\
+	MC_CMD_OP(cmd, 3, 48, 8,  char,	    cfg->label[14]);\
+	MC_CMD_OP(cmd, 3, 56, 8,  char,	    cfg->label[15]);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_CREATE_CONTAINER(cmd, child_container_id, child_portal_offset)\
+do { \
+	MC_RSP_OP(cmd, 1, 0,  32, int,	   child_container_id); \
+	MC_RSP_OP(cmd, 2, 0,  64, uint64_t, child_portal_offset);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    child_container_id)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    child_container_id)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_GET_ATTRIBUTES(cmd, attr) \
+do { \
+	MC_RSP_OP(cmd, 0, 0,  32, int,	    attr->container_id); \
+	MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->icid); \
+	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, attr->options);\
+	MC_RSP_OP(cmd, 1, 32, 32, int,      attr->portal_id); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_GET_OBJ_COUNT(cmd, obj_count) \
+	MC_RSP_OP(cmd, 0, 32, 32, int,      obj_count)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_GET_OBJ(cmd, obj_index) \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    obj_index)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_GET_OBJ(cmd, obj_desc) \
+do { \
+	MC_RSP_OP(cmd, 0, 32, 32, int,	    obj_desc->id); \
+	MC_RSP_OP(cmd, 1, 0,  16, uint16_t, obj_desc->vendor); \
+	MC_RSP_OP(cmd, 1, 16, 8,  uint8_t,  obj_desc->irq_count); \
+	MC_RSP_OP(cmd, 1, 24, 8,  uint8_t,  obj_desc->region_count); \
+	MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\
+	MC_RSP_OP(cmd, 2, 0,  16, uint16_t, obj_desc->ver_major);\
+	MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\
+	MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \
+	MC_RSP_OP(cmd, 3, 0,  8,  char,	    obj_desc->type[0]);\
+	MC_RSP_OP(cmd, 3, 8,  8,  char,	    obj_desc->type[1]);\
+	MC_RSP_OP(cmd, 3, 16, 8,  char,	    obj_desc->type[2]);\
+	MC_RSP_OP(cmd, 3, 24, 8,  char,	    obj_desc->type[3]);\
+	MC_RSP_OP(cmd, 3, 32, 8,  char,	    obj_desc->type[4]);\
+	MC_RSP_OP(cmd, 3, 40, 8,  char,	    obj_desc->type[5]);\
+	MC_RSP_OP(cmd, 3, 48, 8,  char,	    obj_desc->type[6]);\
+	MC_RSP_OP(cmd, 3, 56, 8,  char,	    obj_desc->type[7]);\
+	MC_RSP_OP(cmd, 4, 0,  8,  char,	    obj_desc->type[8]);\
+	MC_RSP_OP(cmd, 4, 8,  8,  char,	    obj_desc->type[9]);\
+	MC_RSP_OP(cmd, 4, 16, 8,  char,	    obj_desc->type[10]);\
+	MC_RSP_OP(cmd, 4, 24, 8,  char,	    obj_desc->type[11]);\
+	MC_RSP_OP(cmd, 4, 32, 8,  char,	    obj_desc->type[12]);\
+	MC_RSP_OP(cmd, 4, 40, 8,  char,	    obj_desc->type[13]);\
+	MC_RSP_OP(cmd, 4, 48, 8,  char,	    obj_desc->type[14]);\
+	MC_RSP_OP(cmd, 4, 56, 8,  char,	    obj_desc->type[15]);\
+	MC_RSP_OP(cmd, 5, 0,  8,  char,	    obj_desc->label[0]);\
+	MC_RSP_OP(cmd, 5, 8,  8,  char,	    obj_desc->label[1]);\
+	MC_RSP_OP(cmd, 5, 16, 8,  char,	    obj_desc->label[2]);\
+	MC_RSP_OP(cmd, 5, 24, 8,  char,	    obj_desc->label[3]);\
+	MC_RSP_OP(cmd, 5, 32, 8,  char,	    obj_desc->label[4]);\
+	MC_RSP_OP(cmd, 5, 40, 8,  char,	    obj_desc->label[5]);\
+	MC_RSP_OP(cmd, 5, 48, 8,  char,	    obj_desc->label[6]);\
+	MC_RSP_OP(cmd, 5, 56, 8,  char,	    obj_desc->label[7]);\
+	MC_RSP_OP(cmd, 6, 0,  8,  char,	    obj_desc->label[8]);\
+	MC_RSP_OP(cmd, 6, 8,  8,  char,	    obj_desc->label[9]);\
+	MC_RSP_OP(cmd, 6, 16, 8,  char,	    obj_desc->label[10]);\
+	MC_RSP_OP(cmd, 6, 24, 8,  char,	    obj_desc->label[11]);\
+	MC_RSP_OP(cmd, 6, 32, 8,  char,	    obj_desc->label[12]);\
+	MC_RSP_OP(cmd, 6, 40, 8,  char,	    obj_desc->label[13]);\
+	MC_RSP_OP(cmd, 6, 48, 8,  char,	    obj_desc->label[14]);\
+	MC_RSP_OP(cmd, 6, 56, 8,  char,	    obj_desc->label[15]);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    obj_id);\
+	MC_CMD_OP(cmd, 1, 0,  8,  char,     obj_type[0]);\
+	MC_CMD_OP(cmd, 1, 8,  8,  char,	    obj_type[1]);\
+	MC_CMD_OP(cmd, 1, 16, 8,  char,	    obj_type[2]);\
+	MC_CMD_OP(cmd, 1, 24, 8,  char,	    obj_type[3]);\
+	MC_CMD_OP(cmd, 1, 32, 8,  char,	    obj_type[4]);\
+	MC_CMD_OP(cmd, 1, 40, 8,  char,	    obj_type[5]);\
+	MC_CMD_OP(cmd, 1, 48, 8,  char,	    obj_type[6]);\
+	MC_CMD_OP(cmd, 1, 56, 8,  char,	    obj_type[7]);\
+	MC_CMD_OP(cmd, 2, 0,  8,  char,	    obj_type[8]);\
+	MC_CMD_OP(cmd, 2, 8,  8,  char,	    obj_type[9]);\
+	MC_CMD_OP(cmd, 2, 16, 8,  char,	    obj_type[10]);\
+	MC_CMD_OP(cmd, 2, 24, 8,  char,	    obj_type[11]);\
+	MC_CMD_OP(cmd, 2, 32, 8,  char,	    obj_type[12]);\
+	MC_CMD_OP(cmd, 2, 40, 8,  char,	    obj_type[13]);\
+	MC_CMD_OP(cmd, 2, 48, 8,  char,     obj_type[14]);\
+	MC_CMD_OP(cmd, 2, 56, 8,  char,	    obj_type[15]);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc) \
+do { \
+	MC_RSP_OP(cmd, 0, 32, 32, int,	    obj_desc->id); \
+	MC_RSP_OP(cmd, 1, 0,  16, uint16_t, obj_desc->vendor); \
+	MC_RSP_OP(cmd, 1, 16, 8,  uint8_t,  obj_desc->irq_count); \
+	MC_RSP_OP(cmd, 1, 24, 8,  uint8_t,  obj_desc->region_count); \
+	MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\
+	MC_RSP_OP(cmd, 2, 0,  16, uint16_t, obj_desc->ver_major);\
+	MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\
+	MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \
+	MC_RSP_OP(cmd, 3, 0,  8,  char,	    obj_desc->type[0]);\
+	MC_RSP_OP(cmd, 3, 8,  8,  char,	    obj_desc->type[1]);\
+	MC_RSP_OP(cmd, 3, 16, 8,  char,	    obj_desc->type[2]);\
+	MC_RSP_OP(cmd, 3, 24, 8,  char,	    obj_desc->type[3]);\
+	MC_RSP_OP(cmd, 3, 32, 8,  char,	    obj_desc->type[4]);\
+	MC_RSP_OP(cmd, 3, 40, 8,  char,	    obj_desc->type[5]);\
+	MC_RSP_OP(cmd, 3, 48, 8,  char,	    obj_desc->type[6]);\
+	MC_RSP_OP(cmd, 3, 56, 8,  char,	    obj_desc->type[7]);\
+	MC_RSP_OP(cmd, 4, 0,  8,  char,	    obj_desc->type[8]);\
+	MC_RSP_OP(cmd, 4, 8,  8,  char,	    obj_desc->type[9]);\
+	MC_RSP_OP(cmd, 4, 16, 8,  char,	    obj_desc->type[10]);\
+	MC_RSP_OP(cmd, 4, 24, 8,  char,	    obj_desc->type[11]);\
+	MC_RSP_OP(cmd, 4, 32, 8,  char,	    obj_desc->type[12]);\
+	MC_RSP_OP(cmd, 4, 40, 8,  char,	    obj_desc->type[13]);\
+	MC_RSP_OP(cmd, 4, 48, 8,  char,	    obj_desc->type[14]);\
+	MC_RSP_OP(cmd, 4, 56, 8,  char,	    obj_desc->type[15]);\
+	MC_RSP_OP(cmd, 5, 0,  8,  char,	    obj_desc->label[0]);\
+	MC_RSP_OP(cmd, 5, 8,  8,  char,	    obj_desc->label[1]);\
+	MC_RSP_OP(cmd, 5, 16, 8,  char,	    obj_desc->label[2]);\
+	MC_RSP_OP(cmd, 5, 24, 8,  char,	    obj_desc->label[3]);\
+	MC_RSP_OP(cmd, 5, 32, 8,  char,	    obj_desc->label[4]);\
+	MC_RSP_OP(cmd, 5, 40, 8,  char,	    obj_desc->label[5]);\
+	MC_RSP_OP(cmd, 5, 48, 8,  char,	    obj_desc->label[6]);\
+	MC_RSP_OP(cmd, 5, 56, 8,  char,	    obj_desc->label[7]);\
+	MC_RSP_OP(cmd, 6, 0,  8,  char,	    obj_desc->label[8]);\
+	MC_RSP_OP(cmd, 6, 8,  8,  char,	    obj_desc->label[9]);\
+	MC_RSP_OP(cmd, 6, 16, 8,  char,	    obj_desc->label[10]);\
+	MC_RSP_OP(cmd, 6, 24, 8,  char,	    obj_desc->label[11]);\
+	MC_RSP_OP(cmd, 6, 32, 8,  char,	    obj_desc->label[12]);\
+	MC_RSP_OP(cmd, 6, 40, 8,  char,	    obj_desc->label[13]);\
+	MC_RSP_OP(cmd, 6, 48, 8,  char,	    obj_desc->label[14]);\
+	MC_RSP_OP(cmd, 6, 56, 8,  char,	    obj_desc->label[15]);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_GET_RES_COUNT(cmd, type) \
+do { \
+	MC_CMD_OP(cmd, 1, 0,  8,  char,	    type[0]);\
+	MC_CMD_OP(cmd, 1, 8,  8,  char,	    type[1]);\
+	MC_CMD_OP(cmd, 1, 16, 8,  char,	    type[2]);\
+	MC_CMD_OP(cmd, 1, 24, 8,  char,	    type[3]);\
+	MC_CMD_OP(cmd, 1, 32, 8,  char,	    type[4]);\
+	MC_CMD_OP(cmd, 1, 40, 8,  char,	    type[5]);\
+	MC_CMD_OP(cmd, 1, 48, 8,  char,	    type[6]);\
+	MC_CMD_OP(cmd, 1, 56, 8,  char,	    type[7]);\
+	MC_CMD_OP(cmd, 2, 0,  8,  char,	    type[8]);\
+	MC_CMD_OP(cmd, 2, 8,  8,  char,	    type[9]);\
+	MC_CMD_OP(cmd, 2, 16, 8,  char,	    type[10]);\
+	MC_CMD_OP(cmd, 2, 24, 8,  char,	    type[11]);\
+	MC_CMD_OP(cmd, 2, 32, 8,  char,	    type[12]);\
+	MC_CMD_OP(cmd, 2, 40, 8,  char,	    type[13]);\
+	MC_CMD_OP(cmd, 2, 48, 8,  char,	    type[14]);\
+	MC_CMD_OP(cmd, 2, 56, 8,  char,	    type[15]);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_GET_RES_COUNT(cmd, res_count) \
+	MC_RSP_OP(cmd, 0, 0,  32, int,	    res_count)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_GET_RES_IDS(cmd, range_desc, type) \
+do { \
+	MC_CMD_OP(cmd, 0, 42, 7,  enum dprc_iter_status, \
+					    range_desc->iter_status); \
+	MC_CMD_OP(cmd, 1, 0,  32, int,	    range_desc->base_id); \
+	MC_CMD_OP(cmd, 1, 32, 32, int,	    range_desc->last_id);\
+	MC_CMD_OP(cmd, 2, 0,  8,  char,	    type[0]);\
+	MC_CMD_OP(cmd, 2, 8,  8,  char,	    type[1]);\
+	MC_CMD_OP(cmd, 2, 16, 8,  char,	    type[2]);\
+	MC_CMD_OP(cmd, 2, 24, 8,  char,	    type[3]);\
+	MC_CMD_OP(cmd, 2, 32, 8,  char,	    type[4]);\
+	MC_CMD_OP(cmd, 2, 40, 8,  char,     type[5]);\
+	MC_CMD_OP(cmd, 2, 48, 8,  char,	    type[6]);\
+	MC_CMD_OP(cmd, 2, 56, 8,  char,	    type[7]);\
+	MC_CMD_OP(cmd, 3, 0,  8,  char,	    type[8]);\
+	MC_CMD_OP(cmd, 3, 8,  8,  char,	    type[9]);\
+	MC_CMD_OP(cmd, 3, 16, 8,  char,	    type[10]);\
+	MC_CMD_OP(cmd, 3, 24, 8,  char,	    type[11]);\
+	MC_CMD_OP(cmd, 3, 32, 8,  char,	    type[12]);\
+	MC_CMD_OP(cmd, 3, 40, 8,  char,	    type[13]);\
+	MC_CMD_OP(cmd, 3, 48, 8,  char,	    type[14]);\
+	MC_CMD_OP(cmd, 3, 56, 8,  char,	    type[15]);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_GET_RES_IDS(cmd, range_desc) \
+do { \
+	MC_RSP_OP(cmd, 0, 42, 7,  enum dprc_iter_status, \
+					    range_desc->iter_status);\
+	MC_RSP_OP(cmd, 1, 0,  32, int,	    range_desc->base_id); \
+	MC_RSP_OP(cmd, 1, 32, 32, int,	    range_desc->last_id);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    obj_id); \
+	MC_CMD_OP(cmd, 0, 48, 8,  uint8_t,  region_index);\
+	MC_CMD_OP(cmd, 3, 0,  8,  char,	    obj_type[0]);\
+	MC_CMD_OP(cmd, 3, 8,  8,  char,	    obj_type[1]);\
+	MC_CMD_OP(cmd, 3, 16, 8,  char,	    obj_type[2]);\
+	MC_CMD_OP(cmd, 3, 24, 8,  char,	    obj_type[3]);\
+	MC_CMD_OP(cmd, 3, 32, 8,  char,	    obj_type[4]);\
+	MC_CMD_OP(cmd, 3, 40, 8,  char,	    obj_type[5]);\
+	MC_CMD_OP(cmd, 3, 48, 8,  char,	    obj_type[6]);\
+	MC_CMD_OP(cmd, 3, 56, 8,  char,	    obj_type[7]);\
+	MC_CMD_OP(cmd, 4, 0,  8,  char,	    obj_type[8]);\
+	MC_CMD_OP(cmd, 4, 8,  8,  char,	    obj_type[9]);\
+	MC_CMD_OP(cmd, 4, 16, 8,  char,	    obj_type[10]);\
+	MC_CMD_OP(cmd, 4, 24, 8,  char,	    obj_type[11]);\
+	MC_CMD_OP(cmd, 4, 32, 8,  char,	    obj_type[12]);\
+	MC_CMD_OP(cmd, 4, 40, 8,  char,	    obj_type[13]);\
+	MC_CMD_OP(cmd, 4, 48, 8,  char,	    obj_type[14]);\
+	MC_CMD_OP(cmd, 4, 56, 8,  char,	    obj_type[15]);\
+} while (0)
+
+/*	param, offset, width,	type,		arg_name */
+#define DPRC_RSP_GET_OBJ_REGION(cmd, region_desc) \
+do { \
+	MC_RSP_OP(cmd, 1, 0,  32, uint32_t, region_desc->base_offset);\
+	MC_RSP_OP(cmd, 2, 0,  32, uint32_t, region_desc->size); \
+	MC_RSP_OP(cmd, 2, 32, 4,  enum dprc_region_type, region_desc->type);\
+	MC_RSP_OP(cmd, 3, 0,  32, uint32_t, region_desc->flags);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_SET_OBJ_LABEL(cmd, obj_type, obj_id, label) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,      obj_id); \
+	MC_CMD_OP(cmd, 1, 0,  8,  char,	    label[0]);\
+	MC_CMD_OP(cmd, 1, 8,  8,  char,	    label[1]);\
+	MC_CMD_OP(cmd, 1, 16, 8,  char,	    label[2]);\
+	MC_CMD_OP(cmd, 1, 24, 8,  char,	    label[3]);\
+	MC_CMD_OP(cmd, 1, 32, 8,  char,	    label[4]);\
+	MC_CMD_OP(cmd, 1, 40, 8,  char,	    label[5]);\
+	MC_CMD_OP(cmd, 1, 48, 8,  char,	    label[6]);\
+	MC_CMD_OP(cmd, 1, 56, 8,  char,	    label[7]);\
+	MC_CMD_OP(cmd, 2, 0,  8,  char,	    label[8]);\
+	MC_CMD_OP(cmd, 2, 8,  8,  char,	    label[9]);\
+	MC_CMD_OP(cmd, 2, 16, 8,  char,	    label[10]);\
+	MC_CMD_OP(cmd, 2, 24, 8,  char,	    label[11]);\
+	MC_CMD_OP(cmd, 2, 32, 8,  char,	    label[12]);\
+	MC_CMD_OP(cmd, 2, 40, 8,  char,	    label[13]);\
+	MC_CMD_OP(cmd, 2, 48, 8,  char,	    label[14]);\
+	MC_CMD_OP(cmd, 2, 56, 8,  char,	    label[15]);\
+	MC_CMD_OP(cmd, 3, 0,  8,  char,	    obj_type[0]);\
+	MC_CMD_OP(cmd, 3, 8,  8,  char,	    obj_type[1]);\
+	MC_CMD_OP(cmd, 3, 16, 8,  char,	    obj_type[2]);\
+	MC_CMD_OP(cmd, 3, 24, 8,  char,	    obj_type[3]);\
+	MC_CMD_OP(cmd, 3, 32, 8,  char,	    obj_type[4]);\
+	MC_CMD_OP(cmd, 3, 40, 8,  char,	    obj_type[5]);\
+	MC_CMD_OP(cmd, 3, 48, 8,  char,	    obj_type[6]);\
+	MC_CMD_OP(cmd, 3, 56, 8,  char,	    obj_type[7]);\
+	MC_CMD_OP(cmd, 4, 0,  8,  char,	    obj_type[8]);\
+	MC_CMD_OP(cmd, 4, 8,  8,  char,	    obj_type[9]);\
+	MC_CMD_OP(cmd, 4, 16, 8,  char,	    obj_type[10]);\
+	MC_CMD_OP(cmd, 4, 24, 8,  char,	    obj_type[11]);\
+	MC_CMD_OP(cmd, 4, 32, 8,  char,	    obj_type[12]);\
+	MC_CMD_OP(cmd, 4, 40, 8,  char,	    obj_type[13]);\
+	MC_CMD_OP(cmd, 4, 48, 8,  char,	    obj_type[14]);\
+	MC_CMD_OP(cmd, 4, 56, 8,  char,	    obj_type[15]);\
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,      endpoint1->id); \
+	MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \
+	MC_CMD_OP(cmd, 1, 0,  32, int,	    endpoint2->id); \
+	MC_CMD_OP(cmd, 1, 32, 32, int, endpoint2->if_id); \
+	MC_CMD_OP(cmd, 2, 0,  8,  char,     endpoint1->type[0]); \
+	MC_CMD_OP(cmd, 2, 8,  8,  char,	    endpoint1->type[1]); \
+	MC_CMD_OP(cmd, 2, 16, 8,  char,	    endpoint1->type[2]); \
+	MC_CMD_OP(cmd, 2, 24, 8,  char,	    endpoint1->type[3]); \
+	MC_CMD_OP(cmd, 2, 32, 8,  char,	    endpoint1->type[4]); \
+	MC_CMD_OP(cmd, 2, 40, 8,  char,	    endpoint1->type[5]); \
+	MC_CMD_OP(cmd, 2, 48, 8,  char,	    endpoint1->type[6]); \
+	MC_CMD_OP(cmd, 2, 56, 8,  char,	    endpoint1->type[7]); \
+	MC_CMD_OP(cmd, 3, 0,  8,  char,	    endpoint1->type[8]); \
+	MC_CMD_OP(cmd, 3, 8,  8,  char,	    endpoint1->type[9]); \
+	MC_CMD_OP(cmd, 3, 16, 8,  char,	    endpoint1->type[10]); \
+	MC_CMD_OP(cmd, 3, 24, 8,  char,	    endpoint1->type[11]); \
+	MC_CMD_OP(cmd, 3, 32, 8,  char,     endpoint1->type[12]); \
+	MC_CMD_OP(cmd, 3, 40, 8,  char,	    endpoint1->type[13]); \
+	MC_CMD_OP(cmd, 3, 48, 8,  char,	    endpoint1->type[14]); \
+	MC_CMD_OP(cmd, 3, 56, 8,  char,	    endpoint1->type[15]); \
+	MC_CMD_OP(cmd, 4, 0,  32, uint32_t, cfg->max_rate); \
+	MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->committed_rate); \
+	MC_CMD_OP(cmd, 5, 0,  8,  char,	    endpoint2->type[0]); \
+	MC_CMD_OP(cmd, 5, 8,  8,  char,	    endpoint2->type[1]); \
+	MC_CMD_OP(cmd, 5, 16, 8,  char,	    endpoint2->type[2]); \
+	MC_CMD_OP(cmd, 5, 24, 8,  char,	    endpoint2->type[3]); \
+	MC_CMD_OP(cmd, 5, 32, 8,  char,	    endpoint2->type[4]); \
+	MC_CMD_OP(cmd, 5, 40, 8,  char,	    endpoint2->type[5]); \
+	MC_CMD_OP(cmd, 5, 48, 8,  char,	    endpoint2->type[6]); \
+	MC_CMD_OP(cmd, 5, 56, 8,  char,	    endpoint2->type[7]); \
+	MC_CMD_OP(cmd, 6, 0,  8,  char,	    endpoint2->type[8]); \
+	MC_CMD_OP(cmd, 6, 8,  8,  char,	    endpoint2->type[9]); \
+	MC_CMD_OP(cmd, 6, 16, 8,  char,	    endpoint2->type[10]); \
+	MC_CMD_OP(cmd, 6, 24, 8,  char,	    endpoint2->type[11]); \
+	MC_CMD_OP(cmd, 6, 32, 8,  char,	    endpoint2->type[12]); \
+	MC_CMD_OP(cmd, 6, 40, 8,  char,	    endpoint2->type[13]); \
+	MC_CMD_OP(cmd, 6, 48, 8,  char,	    endpoint2->type[14]); \
+	MC_CMD_OP(cmd, 6, 56, 8,  char,	    endpoint2->type[15]); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_DISCONNECT(cmd, endpoint) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    endpoint->id); \
+	MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint->if_id); \
+	MC_CMD_OP(cmd, 1, 0,  8,  char,	    endpoint->type[0]); \
+	MC_CMD_OP(cmd, 1, 8,  8,  char,	    endpoint->type[1]); \
+	MC_CMD_OP(cmd, 1, 16, 8,  char,	    endpoint->type[2]); \
+	MC_CMD_OP(cmd, 1, 24, 8,  char,	    endpoint->type[3]); \
+	MC_CMD_OP(cmd, 1, 32, 8,  char,	    endpoint->type[4]); \
+	MC_CMD_OP(cmd, 1, 40, 8,  char,	    endpoint->type[5]); \
+	MC_CMD_OP(cmd, 1, 48, 8,  char,	    endpoint->type[6]); \
+	MC_CMD_OP(cmd, 1, 56, 8,  char,	    endpoint->type[7]); \
+	MC_CMD_OP(cmd, 2, 0,  8,  char,	    endpoint->type[8]); \
+	MC_CMD_OP(cmd, 2, 8,  8,  char,	    endpoint->type[9]); \
+	MC_CMD_OP(cmd, 2, 16, 8,  char,	    endpoint->type[10]); \
+	MC_CMD_OP(cmd, 2, 24, 8,  char,	    endpoint->type[11]); \
+	MC_CMD_OP(cmd, 2, 32, 8,  char,	    endpoint->type[12]); \
+	MC_CMD_OP(cmd, 2, 40, 8,  char,	    endpoint->type[13]); \
+	MC_CMD_OP(cmd, 2, 48, 8,  char,	    endpoint->type[14]); \
+	MC_CMD_OP(cmd, 2, 56, 8,  char,	    endpoint->type[15]); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_CMD_GET_CONNECTION(cmd, endpoint1) \
+do { \
+	MC_CMD_OP(cmd, 0, 0,  32, int,	    endpoint1->id); \
+	MC_CMD_OP(cmd, 0, 32, 32, int,	    endpoint1->if_id); \
+	MC_CMD_OP(cmd, 1, 0,  8,  char,     endpoint1->type[0]); \
+	MC_CMD_OP(cmd, 1, 8,  8,  char,	    endpoint1->type[1]); \
+	MC_CMD_OP(cmd, 1, 16, 8,  char,	    endpoint1->type[2]); \
+	MC_CMD_OP(cmd, 1, 24, 8,  char,	    endpoint1->type[3]); \
+	MC_CMD_OP(cmd, 1, 32, 8,  char,	    endpoint1->type[4]); \
+	MC_CMD_OP(cmd, 1, 40, 8,  char,	    endpoint1->type[5]); \
+	MC_CMD_OP(cmd, 1, 48, 8,  char,	    endpoint1->type[6]); \
+	MC_CMD_OP(cmd, 1, 56, 8,  char,	    endpoint1->type[7]); \
+	MC_CMD_OP(cmd, 2, 0,  8,  char,	    endpoint1->type[8]); \
+	MC_CMD_OP(cmd, 2, 8,  8,  char,	    endpoint1->type[9]); \
+	MC_CMD_OP(cmd, 2, 16, 8,  char,	    endpoint1->type[10]); \
+	MC_CMD_OP(cmd, 2, 24, 8,  char,	    endpoint1->type[11]); \
+	MC_CMD_OP(cmd, 2, 32, 8,  char,     endpoint1->type[12]); \
+	MC_CMD_OP(cmd, 2, 40, 8,  char,	    endpoint1->type[13]); \
+	MC_CMD_OP(cmd, 2, 48, 8,  char,	    endpoint1->type[14]); \
+	MC_CMD_OP(cmd, 2, 56, 8,  char,	    endpoint1->type[15]); \
+} while (0)
+
+/*                cmd, param, offset, width, type, arg_name */
+#define DPRC_RSP_GET_CONNECTION(cmd, endpoint2, state) \
+do { \
+	MC_RSP_OP(cmd, 3, 0,  32, int,	    endpoint2->id); \
+	MC_RSP_OP(cmd, 3, 32, 16, uint16_t, endpoint2->if_id); \
+	MC_RSP_OP(cmd, 4, 0,  8,  char,	    endpoint2->type[0]); \
+	MC_RSP_OP(cmd, 4, 8,  8,  char,	    endpoint2->type[1]); \
+	MC_RSP_OP(cmd, 4, 16, 8,  char,	    endpoint2->type[2]); \
+	MC_RSP_OP(cmd, 4, 24, 8,  char,	    endpoint2->type[3]); \
+	MC_RSP_OP(cmd, 4, 32, 8,  char,	    endpoint2->type[4]); \
+	MC_RSP_OP(cmd, 4, 40, 8,  char,	    endpoint2->type[5]); \
+	MC_RSP_OP(cmd, 4, 48, 8,  char,	    endpoint2->type[6]); \
+	MC_RSP_OP(cmd, 4, 56, 8,  char,	    endpoint2->type[7]); \
+	MC_RSP_OP(cmd, 5, 0,  8,  char,	    endpoint2->type[8]); \
+	MC_RSP_OP(cmd, 5, 8,  8,  char,	    endpoint2->type[9]); \
+	MC_RSP_OP(cmd, 5, 16, 8,  char,	    endpoint2->type[10]); \
+	MC_RSP_OP(cmd, 5, 24, 8,  char,	    endpoint2->type[11]); \
+	MC_RSP_OP(cmd, 5, 32, 8,  char,	    endpoint2->type[12]); \
+	MC_RSP_OP(cmd, 5, 40, 8,  char,	    endpoint2->type[13]); \
+	MC_RSP_OP(cmd, 5, 48, 8,  char,	    endpoint2->type[14]); \
+	MC_RSP_OP(cmd, 5, 56, 8,  char,	    endpoint2->type[15]); \
+	MC_RSP_OP(cmd, 6, 0,  32, int,	    state); \
+} while (0)
+
+/* Data Path Resource Container API
+ * Contains DPRC API for managing and querying DPAA resources
+ */
+
+struct fsl_mc_io;
+
+/**
+ * Set this value as the icid value in dprc_cfg structure when creating a
+ * container, in case the ICID is not selected by the user and should be
+ * allocated by the DPRC from the pool of ICIDs.
+ */
+#define DPRC_GET_ICID_FROM_POOL			(uint16_t)(~(0))
+
+/**
+ * Set this value as the portal_id value in dprc_cfg structure when creating a
+ * container, in case the portal ID is not specifically selected by the
+ * user and should be allocated by the DPRC from the pool of portal ids.
+ */
+#define DPRC_GET_PORTAL_ID_FROM_POOL	(int)(~(0))
+
+/**
+ * dprc_get_container_id() - Get container ID associated with a given portal.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @container_id:	Requested container ID
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_get_container_id(struct fsl_mc_io	*mc_io,
+			  uint32_t		cmd_flags,
+			  int			*container_id);
+
+/**
+ * dprc_open() - Open DPRC object for use
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @container_id: Container ID to open
+ * @token:	Returned token of DPRC object
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ *
+ * @warning	Required before any operation on the object.
+ */
+int dprc_open(struct fsl_mc_io	*mc_io,
+	      uint32_t		cmd_flags,
+	      int		container_id,
+	      uint16_t		*token);
+
+/**
+ * dprc_close() - Close the control session of the object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ *
+ * After this function is called, no further operations are
+ * allowed on the object without opening a new control session.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_close(struct fsl_mc_io	*mc_io,
+	       uint32_t		cmd_flags,
+	       uint16_t		token);
+
+/**
+ * Container general options
+ *
+ * These options may be selected at container creation by the container creator
+ * and can be retrieved using dprc_get_attributes()
+ */
+
+/* Spawn Policy Option allowed - Indicates that the new container is allowed
+ * to spawn and have its own child containers.
+ */
+#define DPRC_CFG_OPT_SPAWN_ALLOWED		0x00000001
+
+/* General Container allocation policy - Indicates that the new container is
+ * allowed to allocate requested resources from its parent container; if not
+ * set, the container is only allowed to use resources in its own pools; Note
+ * that this is a container's global policy, but the parent container may
+ * override it and set specific quota per resource type.
+ */
+#define DPRC_CFG_OPT_ALLOC_ALLOWED		0x00000002
+
+/* Object initialization allowed - software context associated with this
+ * container is allowed to invoke object initialization operations.
+ */
+#define DPRC_CFG_OPT_OBJ_CREATE_ALLOWED		0x00000004
+
+/* Topology change allowed - software context associated with this
+ * container is allowed to invoke topology operations, such as attach/detach
+ * of network objects.
+ */
+#define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED	0x00000008
+
+
+/* AIOP - Indicates that container belongs to AIOP. */
+#define DPRC_CFG_OPT_AIOP			0x00000020
+
+/* IRQ Config - Indicates that the container allowed to configure its IRQs.*/
+#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED		0x00000040
+
+/**
+ * struct dprc_cfg - Container configuration options
+ * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free
+ *		ICID value is allocated by the DPRC
+ * @portal_id: Portal ID; if set to 'DPRC_GET_PORTAL_ID_FROM_POOL', a free
+ *		portal ID is allocated by the DPRC
+ * @options: Combination of 'DPRC_CFG_OPT_<X>' options
+ * @label: Object's label
+ */
+struct dprc_cfg {
+	uint16_t icid;
+	int portal_id;
+	uint64_t options;
+	char label[16];
+};
+
+/**
+ * dprc_create_container() - Create child container
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @cfg:	Child container configuration
+ * @child_container_id:	Returned child container ID
+ * @child_portal_offset: Returned child portal offset from MC portal base
+ *
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_create_container(struct fsl_mc_io	*mc_io,
+			  uint32_t		cmd_flags,
+			  uint16_t		token,
+			  struct dprc_cfg	*cfg,
+			  int			*child_container_id,
+			  uint64_t		*child_portal_offset);
+
+/**
+ * dprc_destroy_container() - Destroy child container.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @child_container_id:	ID of the container to destroy
+ *
+ * This function terminates the child container, so following this call the
+ * child container ID becomes invalid.
+ *
+ * Notes:
+ * - All resources and objects of the destroyed container are returned to the
+ * parent container or destroyed if were created be the destroyed container.
+ * - This function destroy all the child containers of the specified
+ *   container prior to destroying the container itself.
+ *
+ * warning: Only the parent container is allowed to destroy a child policy
+ *		Container 0 can't be destroyed
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ *
+ */
+int dprc_destroy_container(struct fsl_mc_io	*mc_io,
+			   uint32_t		cmd_flags,
+			   uint16_t		token,
+			   int			child_container_id);
+
+/**
+ * dprc_reset_container - Reset child container.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @child_container_id:	ID of the container to reset
+ *
+ * In case a software context crashes or becomes non-responsive, the parent
+ * may wish to reset its resources container before the software context is
+ * restarted.
+ *
+ * This routine informs all objects assigned to the child container that the
+ * container is being reset, so they may perform any cleanup operations that are
+ * needed. All objects handles that were owned by the child container shall be
+ * closed.
+ *
+ * Note that such request may be submitted even if the child software context
+ * has not crashed, but the resulting object cleanup operations will not be
+ * aware of that.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_reset_container(struct fsl_mc_io	*mc_io,
+			 uint32_t		cmd_flags,
+			 uint16_t		token,
+			 int			child_container_id);
+
+/**
+ * struct dprc_attributes - Container attributes
+ * @container_id: Container's ID
+ * @icid: Container's ICID
+ * @portal_id: Container's portal ID
+ * @options: Container's options as set at container's creation
+ * @version: DPRC version
+ */
+struct dprc_attributes {
+	int container_id;
+	uint16_t icid;
+	int portal_id;
+	uint64_t options;
+};
+
+/**
+ * dprc_get_attributes() - Obtains container attributes
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @attributes:	Returned container attributes
+ *
+ * Return:     '0' on Success; Error code otherwise.
+ */
+int dprc_get_attributes(struct fsl_mc_io	*mc_io,
+			uint32_t		cmd_flags,
+			uint16_t		token,
+			struct dprc_attributes	*attributes);
+
+/**
+ * dprc_get_obj_count() - Obtains the number of objects in the DPRC
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @obj_count:	Number of objects assigned to the DPRC
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_get_obj_count(struct fsl_mc_io	*mc_io,
+		       uint32_t		cmd_flags,
+		       uint16_t		token,
+		       int			*obj_count);
+
+/* Objects Attributes Flags */
+
+/* Opened state - Indicates that an object is open by at least one owner */
+#define DPRC_OBJ_STATE_OPEN		0x00000001
+/* Plugged state - Indicates that the object is plugged */
+#define DPRC_OBJ_STATE_PLUGGED		0x00000002
+
+/**
+ * Shareability flag - Object flag indicating no memory shareability.
+ *  the object generates memory accesses that are non coherent with other
+ *  masters;
+ *  user is responsible for proper memory handling through IOMMU configuration.
+ */
+#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY		0x0001
+
+/**
+ * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj()
+ * @type: Type of object: NULL terminated string
+ * @id: ID of logical object resource
+ * @vendor: Object vendor identifier
+ * @ver_major: Major version number
+ * @ver_minor:  Minor version number
+ * @irq_count: Number of interrupts supported by the object
+ * @region_count: Number of mappable regions supported by the object
+ * @state: Object state: combination of DPRC_OBJ_STATE_ states
+ * @label: Object label
+ * @flags: Object's flags
+ */
+struct dprc_obj_desc {
+	char type[16];
+	int id;
+	uint16_t vendor;
+	uint16_t ver_major;
+	uint16_t ver_minor;
+	uint8_t irq_count;
+	uint8_t region_count;
+	uint32_t state;
+	char label[16];
+	uint16_t	flags;
+};
+
+/**
+ * dprc_get_obj() - Get general information on an object
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @obj_index:	Index of the object to be queried (< obj_count)
+ * @obj_desc:	Returns the requested object descriptor
+ *
+ * The object descriptors are retrieved one by one by incrementing
+ * obj_index up to (not including) the value of obj_count returned
+ * from dprc_get_obj_count(). dprc_get_obj_count() must
+ * be called prior to dprc_get_obj().
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_get_obj(struct fsl_mc_io	*mc_io,
+		 uint32_t		cmd_flags,
+		 uint16_t		token,
+		 int			obj_index,
+		 struct dprc_obj_desc	*obj_desc);
+
+/**
+ * dprc_get_res_count() - Obtains the number of free resources that are
+ *		assigned to this container, by pool type
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @type:	pool type
+ * @res_count:	Returned number of free resources of the given
+ *			resource type that are assigned to this DPRC
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_get_res_count(struct fsl_mc_io *mc_io,
+		       uint32_t	cmd_flags,
+		       uint16_t		token,
+		       char		*type,
+		       int		*res_count);
+
+/**
+ * enum dprc_iter_status - Iteration status
+ * @DPRC_ITER_STATUS_FIRST: Perform first iteration
+ * @DPRC_ITER_STATUS_MORE: Indicates more/next iteration is needed
+ * @DPRC_ITER_STATUS_LAST: Indicates last iteration
+ */
+enum dprc_iter_status {
+	DPRC_ITER_STATUS_FIRST = 0,
+	DPRC_ITER_STATUS_MORE = 1,
+	DPRC_ITER_STATUS_LAST = 2
+};
+
+/**
+ * struct dprc_res_ids_range_desc - Resource ID range descriptor
+ * @base_id: Base resource ID of this range
+ * @last_id: Last resource ID of this range
+ * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at
+ *	first iteration; while the returned marker is DPRC_ITER_STATUS_MORE,
+ *	additional iterations are needed, until the returned marker is
+ *	DPRC_ITER_STATUS_LAST
+ */
+struct dprc_res_ids_range_desc {
+	int base_id;
+	int last_id;
+	enum dprc_iter_status iter_status;
+};
+
+/**
+ * dprc_get_res_ids() - Obtains IDs of free resources in the container
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @type:	pool type
+ * @range_desc:	range descriptor
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_get_res_ids(struct fsl_mc_io			*mc_io,
+		     uint32_t				cmd_flags,
+		     uint16_t				token,
+		     char				*type,
+		     struct dprc_res_ids_range_desc	*range_desc);
+
+/* Region flags */
+/* Cacheable - Indicates that region should be mapped as cacheable */
+#define DPRC_REGION_CACHEABLE	0x00000001
+
+/**
+ * enum dprc_region_type - Region type
+ * @DPRC_REGION_TYPE_MC_PORTAL: MC portal region
+ * @DPRC_REGION_TYPE_QBMAN_PORTAL: Qbman portal region
+ */
+enum dprc_region_type {
+	DPRC_REGION_TYPE_MC_PORTAL,
+	DPRC_REGION_TYPE_QBMAN_PORTAL
+};
+
+/**
+ * struct dprc_region_desc - Mappable region descriptor
+ * @base_offset: Region offset from region's base address.
+ *	For DPMCP and DPRC objects, region base is offset from SoC MC portals
+ *	base address; For DPIO, region base is offset from SoC QMan portals
+ *	base address
+ * @size: Region size (in bytes)
+ * @flags: Region attributes
+ * @type: Portal region type
+ */
+struct dprc_region_desc {
+	uint32_t base_offset;
+	uint32_t size;
+	uint32_t flags;
+	enum dprc_region_type type;
+};
+
+/**
+ * dprc_get_obj_region() - Get region information for a specified object.
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @obj_type:	Object type as returned in dprc_get_obj()
+ * @obj_id:	Unique object instance as returned in dprc_get_obj()
+ * @region_index: The specific region to query
+ * @region_desc:  Returns the requested region descriptor
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_get_obj_region(struct fsl_mc_io	*mc_io,
+			uint32_t		cmd_flags,
+			uint16_t		token,
+			char			*obj_type,
+			int			obj_id,
+			uint8_t			region_index,
+			struct dprc_region_desc	*region_desc);
+/**
+ * struct dprc_endpoint - Endpoint description for link connect/disconnect
+ *			operations
+ * @type: Endpoint object type: NULL terminated string
+ * @id: Endpoint object ID
+ * @if_id: Interface ID; should be set for endpoints with multiple
+ *		interfaces ("dpsw", "dpdmux"); for others, always set to 0
+ */
+struct dprc_endpoint {
+	char		type[16];
+	int		id;
+	uint16_t	if_id;
+};
+
+/**
+ * struct dprc_connection_cfg - Connection configuration.
+ *				Used for virtual connections only
+ * @committed_rate: Committed rate (Mbits/s)
+ * @max_rate: Maximum rate (Mbits/s)
+ */
+struct dprc_connection_cfg {
+	uint32_t committed_rate;
+	uint32_t max_rate;
+};
+
+/**
+ * dprc_connect() - Connect two endpoints to create a network link between them
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @endpoint1:	Endpoint 1 configuration parameters
+ * @endpoint2:	Endpoint 2 configuration parameters
+ * @cfg: Connection configuration. The connection configuration is ignored for
+ *	connections made to DPMAC objects, where rate is retrieved from the
+ *	MAC configuration.
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_connect(struct fsl_mc_io			*mc_io,
+		 uint32_t				cmd_flags,
+		 uint16_t				token,
+		 const struct dprc_endpoint		*endpoint1,
+		 const struct dprc_endpoint		*endpoint2,
+		 const struct dprc_connection_cfg	*cfg);
+
+/**
+ * dprc_disconnect() - Disconnect one endpoint to remove its network connection
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token:	Token of DPRC object
+ * @endpoint:	Endpoint configuration parameters
+ *
+ * Return:	'0' on Success; Error code otherwise.
+ */
+int dprc_disconnect(struct fsl_mc_io		*mc_io,
+		    uint32_t			cmd_flags,
+		    uint16_t			token,
+		    const struct dprc_endpoint	*endpoint);
+
+/**
+* dprc_get_connection() - Get connected endpoint and link status if connection
+*			exists.
+* @mc_io:	Pointer to MC portal's I/O object
+* @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+* @token:	Token of DPRC object
+* @endpoint1:	Endpoint 1 configuration parameters
+* @endpoint2:	Returned endpoint 2 configuration parameters
+* @state:	Returned link state:
+*           1 - link is up;
+*           0 - link is down;
+*           -1 - no connection (endpoint2 information is irrelevant)
+*
+* Return:     '0' on Success; -ENAVAIL if connection does not exist.
+*/
+int dprc_get_connection(struct fsl_mc_io		*mc_io,
+			uint32_t			cmd_flags,
+			uint16_t			token,
+			const struct dprc_endpoint	*endpoint1,
+			struct dprc_endpoint		*endpoint2,
+			int				*state);
+
+/**
+ * dprc_get_api_version - Retrieve DPRC Major and Minor version info.
+ *
+ * @mc_io:	Pointer to MC portal's I/O object
+ * @cmd_flags:	Command flags; one or more of 'MC_CMD_FLAG_'
+ * @major_ver:	DPRC major version
+ * @minor_ver:	DPRC minor version
+ *
+ * Return:     '0' on Success; Error code otherwise.
+ */
+int dprc_get_api_version(struct fsl_mc_io *mc_io,
+			 u32 cmd_flags,
+			 u16 *major_ver,
+			 u16 *minor_ver);
+
+#endif /* _FSL_DPRC_H */
diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h
new file mode 100644
index 0000000..a4d7d85
--- /dev/null
+++ b/include/fsl-mc/fsl_mc.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ */
+
+#ifndef __FSL_MC_H__
+#define __FSL_MC_H__
+
+#include <common.h>
+
+#define MC_CCSR_BASE_ADDR \
+	((struct mc_ccsr_registers __iomem *)0x8340000)
+
+#define GCR1_P1_STOP		BIT(31)
+#define GCR1_P2_STOP		BIT(30)
+#define GCR1_P1_DE_RST		BIT(23)
+#define GCR1_P2_DE_RST		BIT(22)
+#define GCR1_M1_DE_RST		BIT(15)
+#define GCR1_M2_DE_RST		BIT(14)
+#define GCR1_M_ALL_DE_RST	(GCR1_M1_DE_RST | GCR1_M2_DE_RST)
+#define GSR_FS_MASK		0x3fffffff
+
+#define SOC_MC_PORTALS_BASE_ADDR    ((void __iomem *)0x00080C000000)
+#define SOC_QBMAN_PORTALS_BASE_ADDR ((void __iomem *)0x000818000000)
+#define SOC_MC_PORTAL_STRIDE	    0x10000
+
+#define SOC_MC_PORTAL_ADDR(_portal_id) \
+	((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
+	 (_portal_id) * SOC_MC_PORTAL_STRIDE))
+
+#define MC_PORTAL_OFFSET_TO_PORTAL_ID(_portal_offset) \
+	((_portal_offset) / SOC_MC_PORTAL_STRIDE)
+
+struct mc_ccsr_registers {
+	u32 reg_gcr1;
+	u32 reserved1;
+	u32 reg_gsr;
+	u32 reserved2;
+	u32 reg_sicbalr;
+	u32 reg_sicbahr;
+	u32 reg_sicapr;
+	u32 reserved3;
+	u32 reg_mcfbalr;
+	u32 reg_mcfbahr;
+	u32 reg_mcfapr;
+	u32 reserved4[0x2f1];
+	u32 reg_psr;
+	u32 reserved5;
+	u32 reg_brr[2];
+	u32 reserved6[0x80];
+	u32 reg_error[];
+};
+
+void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
+int get_mc_boot_status(void);
+int get_dpl_apply_status(void);
+int is_lazy_dpl_addr_valid(void);
+void fdt_fixup_mc_ddr(u64 *base, u64 *size);
+#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
+int get_aiop_apply_status(void);
+#endif
+u64 mc_get_dram_addr(void);
+unsigned long mc_get_dram_block_size(void);
+int fsl_mc_ldpaa_init(bd_t *bis);
+int fsl_mc_ldpaa_exit(bd_t *bd);
+void mc_env_boot(void);
+#endif
diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h
new file mode 100644
index 0000000..591cda9
--- /dev/null
+++ b/include/fsl-mc/fsl_mc_cmd.h
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+#ifndef __FSL_MC_CMD_H
+#define __FSL_MC_CMD_H
+
+#define MC_CMD_NUM_OF_PARAMS	7
+
+#define MAKE_UMASK64(_width) \
+	((uint64_t)((_width) < 64 ? ((uint64_t)1 << (_width)) - 1 : -1))
+
+static inline uint64_t mc_enc(int lsoffset, int width, uint64_t val)
+{
+	return (uint64_t)(((uint64_t)val & MAKE_UMASK64(width)) << lsoffset);
+}
+static inline uint64_t mc_dec(uint64_t val, int lsoffset, int width)
+{
+	return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width));
+}
+
+struct mc_command {
+	uint64_t header;
+	uint64_t params[MC_CMD_NUM_OF_PARAMS];
+};
+
+struct mc_rsp_create {
+	__le32 object_id;
+};
+
+struct mc_rsp_api_ver {
+	__le16 major_ver;
+	__le16 minor_ver;
+};
+
+enum mc_cmd_status {
+	MC_CMD_STATUS_OK = 0x0, /*!< Completed successfully */
+	MC_CMD_STATUS_READY = 0x1, /*!< Ready to be processed */
+	MC_CMD_STATUS_AUTH_ERR = 0x3, /*!< Authentication error */
+	MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /*!< No privilege */
+	MC_CMD_STATUS_DMA_ERR = 0x5, /*!< DMA or I/O error */
+	MC_CMD_STATUS_CONFIG_ERR = 0x6, /*!< Configuration error */
+	MC_CMD_STATUS_TIMEOUT = 0x7, /*!< Operation timed out */
+	MC_CMD_STATUS_NO_RESOURCE = 0x8, /*!< No resources */
+	MC_CMD_STATUS_NO_MEMORY = 0x9, /*!< No memory available */
+	MC_CMD_STATUS_BUSY = 0xA, /*!< Device is busy */
+	MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /*!< Unsupported operation */
+	MC_CMD_STATUS_INVALID_STATE = 0xC /*!< Invalid state */
+};
+
+/*
+ * MC command flags
+ */
+
+/* High priority flag */
+#define MC_CMD_FLAG_PRI		0x00008000
+/* No flags */
+#define MC_CMD_NO_FLAGS		0x00000000
+/* Command completion flag */
+#define MC_CMD_FLAG_INTR_DIS	0x01000000
+
+
+#define MC_CMD_HDR_CMDID_O	48	/* Command ID field offset */
+#define MC_CMD_HDR_CMDID_S	16	/* Command ID field size */
+#define MC_CMD_HDR_STATUS_O	16	/* Status field offset */
+#define MC_CMD_HDR_TOKEN_O	32	/* Token field offset */
+#define MC_CMD_HDR_TOKEN_S	16	/* Token field size */
+#define MC_CMD_HDR_STATUS_S	8	/* Status field size*/
+#define MC_CMD_HDR_FLAGS_O	0	/* Flags field offset */
+#define MC_CMD_HDR_FLAGS_S	32	/* Flags field size*/
+#define MC_CMD_HDR_FLAGS_MASK	0x0000FFFF /* Command flags mask */
+
+#define MC_CMD_HDR_READ_STATUS(_hdr) \
+	((enum mc_cmd_status)mc_dec((_hdr), \
+		MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S))
+
+#define MC_CMD_HDR_READ_TOKEN(_hdr) \
+	((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S))
+
+#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \
+	((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg)))
+
+#define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \
+	(_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width)))
+
+#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \
+	((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
+
+#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \
+	(_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width)))
+
+/*                cmd, param, offset, width, type, arg_name */
+#define MC_CMD_READ_OBJ_ID(cmd, obj_id) \
+	MC_RSP_OP(cmd, 0, 0,  32,  uint32_t,	    obj_id)
+
+/* cmd, param, offset, width, type, arg_name */
+#define CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id) \
+	MC_CMD_OP(cmd, 0, 0,  32,  uint32_t,  object_id)
+
+static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id,
+					    uint32_t cmd_flags,
+					    uint16_t token)
+{
+	uint64_t hdr = 0;
+
+	hdr = mc_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id);
+	hdr |= mc_enc(MC_CMD_HDR_FLAGS_O, MC_CMD_HDR_FLAGS_S,
+		       (cmd_flags & MC_CMD_HDR_FLAGS_MASK));
+	hdr |= mc_enc(MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S, token);
+	hdr |= mc_enc(MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S,
+		       MC_CMD_STATUS_READY);
+
+	return hdr;
+}
+
+/**
+ * mc_write_command - writes a command to a Management Complex (MC) portal
+ *
+ * @portal: pointer to an MC portal
+ * @cmd: pointer to a filled command
+ */
+static inline void mc_write_command(struct mc_command __iomem *portal,
+				    struct mc_command *cmd)
+{
+	int i;
+
+	/* copy command parameters into the portal */
+	for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
+		writeq(cmd->params[i], &portal->params[i]);
+
+	/* submit the command by writing the header */
+	writeq(cmd->header, &portal->header);
+}
+
+/**
+ * mc_read_response - reads the response for the last MC command from a
+ * Management Complex (MC) portal
+ *
+ * @portal: pointer to an MC portal
+ * @resp: pointer to command response buffer
+ *
+ * Returns MC_CMD_STATUS_OK on Success; Error code otherwise.
+ */
+static inline enum mc_cmd_status mc_read_response(
+					struct mc_command __iomem *portal,
+					struct mc_command *resp)
+{
+	int i;
+	enum mc_cmd_status status;
+
+	/* Copy command response header from MC portal: */
+	resp->header = readq(&portal->header);
+	status = MC_CMD_HDR_READ_STATUS(resp->header);
+	if (status != MC_CMD_STATUS_OK)
+		return status;
+
+	/* Copy command response data from MC portal: */
+	for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
+		resp->params[i] = readq(&portal->params[i]);
+
+	return status;
+}
+
+/**
+ * mc_read_version - read version of the given cmd
+ *
+ * @cmd: pointer to a filled command
+ * @major_version: major version value for the given cmd
+ * @minor_version: minor version value for the given cmd
+ */
+static inline void mc_cmd_read_api_version(struct mc_command *cmd,
+					   u16 *major_ver,
+					   u16 *minor_ver)
+{
+	struct mc_rsp_api_ver *rsp_params;
+
+	rsp_params = (struct mc_rsp_api_ver *)cmd->params;
+	*major_ver = le16_to_cpu(rsp_params->major_ver);
+	*minor_ver = le16_to_cpu(rsp_params->minor_ver);
+}
+
+#endif /* __FSL_MC_CMD_H */
diff --git a/include/fsl-mc/fsl_mc_private.h b/include/fsl-mc/fsl_mc_private.h
new file mode 100644
index 0000000..ba0bc37
--- /dev/null
+++ b/include/fsl-mc/fsl_mc_private.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _FSL_MC_PRIVATE_H_
+#define _FSL_MC_PRIVATE_H_
+
+#include <errno.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <linux/compat.h>
+#include <linux/types.h>
+#include <linux/stringify.h>
+#include <phy.h>
+
+#include <fsl-mc/fsl_mc_sys.h>
+#include <fsl-mc/fsl_mc_cmd.h>
+#include <fsl-mc/fsl_dprc.h>
+#include <fsl-mc/fsl_dpbp.h>
+#include <fsl-mc/fsl_dpni.h>
+
+extern struct fsl_mc_io *dflt_mc_io;
+
+/**
+ * struct dpbp_node - DPBP strucuture
+ * @uint16_t handle: DPBP object handle
+ * @struct dpbp_attr: DPBP attribute
+ */
+struct fsl_dpbp_obj {
+	uint32_t dpbp_id;
+	uint16_t dpbp_handle;
+	struct dpbp_attr dpbp_attr;
+};
+
+extern struct fsl_dpbp_obj *dflt_dpbp;
+
+/**
+ * struct fsl_dpio_obj - DPIO strucuture
+ * @int dpio_id: DPIO id
+ * @struct qbman_swp *sw_portal: SW portal object
+ */
+struct fsl_dpio_obj {
+	uint32_t dpio_id;
+	uint16_t dpio_handle;
+	struct qbman_swp *sw_portal; /** SW portal object */
+};
+
+extern struct fsl_dpio_obj *dflt_dpio;
+
+/**
+ * struct dpni_node - DPNI strucuture
+ * @int dpni_id: DPNI id
+ * @uint16_t handle: DPNI object handle
+ * @struct dpni_attr: DPNI attributes
+ * @struct dpni_buffer_layout: DPNI buffer layout
+ */
+struct fsl_dpni_obj {
+	uint32_t dpni_id;
+	uint16_t dpni_handle;
+	struct dpni_attr dpni_attrs;
+	struct dpni_buffer_layout buf_layout;
+};
+
+extern struct fsl_dpni_obj *dflt_dpni;
+
+int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr);
+int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if);
+int mc_apply_dpl(u64 mc_dpl_addr);
+#endif /* _FSL_MC_PRIVATE_H_ */
diff --git a/include/fsl-mc/fsl_mc_sys.h b/include/fsl-mc/fsl_mc_sys.h
new file mode 100644
index 0000000..9fb8164
--- /dev/null
+++ b/include/fsl-mc/fsl_mc_sys.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale Layerscape Management Complex (MC) Environment-specific code
+ *
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_MC_SYS_H
+#define _FSL_MC_SYS_H
+
+#include <asm/io.h>
+
+struct mc_command;
+
+/*
+ * struct mc_portal_wrapper - MC command portal wrapper object
+ */
+struct fsl_mc_io {
+	struct mc_command __iomem *mmio_regs;
+};
+
+int mc_send_command(struct fsl_mc_io *mc_io,
+		    struct mc_command *cmd);
+
+#endif /* _FSL_MC_SYS_H */
diff --git a/include/fsl-mc/fsl_qbman_base.h b/include/fsl-mc/fsl_qbman_base.h
new file mode 100644
index 0000000..7818fc2
--- /dev/null
+++ b/include/fsl-mc/fsl_qbman_base.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ */
+
+#ifndef _FSL_QBMAN_BASE_H
+#define _FSL_QBMAN_BASE_H
+
+/* Descriptor for a QBMan instance on the SoC. On partitions/targets that do not
+ * control this QBMan instance, these values may simply be place-holders. The
+ * idea is simply that we be able to distinguish between them, eg. so that SWP
+ * descriptors can identify which QBMan instance they belong to. */
+struct qbman_block_desc {
+	void *ccsr_reg_bar; /* CCSR register map */
+	int irq_rerr;  /* Recoverable error interrupt line */
+	int irq_nrerr; /* Non-recoverable error interrupt line */
+};
+
+/* Descriptor for a QBMan software portal, expressed in terms that make sense to
+ * the user context. Ie. on MC, this information is likely to be true-physical,
+ * and instantiated statically at compile-time. On GPP, this information is
+ * likely to be obtained via "discovery" over a partition's "layerscape bus"
+ * (ie. in response to a MC portal command), and would take into account any
+ * virtualisation of the GPP user's address space and/or interrupt numbering. */
+struct qbman_swp_desc {
+	const struct qbman_block_desc *block; /* The QBMan instance */
+	void *cena_bar; /* Cache-enabled portal register map */
+	void *cinh_bar; /* Cache-inhibited portal register map */
+};
+
+/* Driver object for managing a QBMan portal */
+struct qbman_swp;
+
+/* Place-holder for FDs, we represent it via the simplest form that we need for
+ * now. Different overlays may be needed to support different options, etc. (It
+ * is impractical to define One True Struct, because the resulting encoding
+ * routines (lots of read-modify-writes) would be worst-case performance whether
+ * or not circumstances required them.)
+ *
+ * Note, as with all data-structures exchanged between software and hardware (be
+ * they located in the portal register map or DMA'd to and from main-memory),
+ * the driver ensures that the caller of the driver API sees the data-structures
+ * in host-endianness. "struct qbman_fd" is no exception. The 32-bit words
+ * contained within this structure are represented in host-endianness, even if
+ * hardware always treats them as little-endian. As such, if any of these fields
+ * are interpreted in a binary (rather than numerical) fashion by hardware
+ * blocks (eg. accelerators), then the user should be careful. We illustrate
+ * with an example;
+ *
+ * Suppose the desired behaviour of an accelerator is controlled by the "frc"
+ * field of the FDs that are sent to it. Suppose also that the behaviour desired
+ * by the user corresponds to an "frc" value which is expressed as the literal
+ * sequence of bytes 0xfe, 0xed, 0xab, and 0xba. So "frc" should be the 32-bit
+ * value in which 0xfe is the first byte and 0xba is the last byte, and as
+ * hardware is little-endian, this amounts to a 32-bit "value" of 0xbaabedfe. If
+ * the software is little-endian also, this can simply be achieved by setting
+ * frc=0xbaabedfe. On the other hand, if software is big-endian, it should set
+ * frc=0xfeedabba! The best away of avoiding trouble with this sort of thing is
+ * to treat the 32-bit words as numerical values, in which the offset of a field
+ * from the beginning of the first byte (as required or generated by hardware)
+ * is numerically encoded by a left-shift (ie. by raising the field to a
+ * corresponding power of 2).  Ie. in the current example, software could set
+ * "frc" in the following way, and it would work correctly on both little-endian
+ * and big-endian operation;
+ *    fd.frc = (0xfe << 0) | (0xed << 8) | (0xab << 16) | (0xba << 24);
+ */
+struct qbman_fd {
+	union {
+		uint32_t words[8];
+		struct qbman_fd_simple {
+			uint32_t addr_lo;
+			uint32_t addr_hi;
+			uint32_t len;
+			/* offset in the MS 16 bits, BPID in the LS 16 bits */
+			uint32_t bpid_offset;
+			uint32_t frc; /* frame context */
+			/* "err", "va", "cbmt", "asal", [...] */
+			uint32_t ctrl;
+			/* flow context */
+			uint32_t flc_lo;
+			uint32_t flc_hi;
+		} simple;
+	};
+};
+
+#endif /* !_FSL_QBMAN_BASE_H */
diff --git a/include/fsl-mc/fsl_qbman_portal.h b/include/fsl-mc/fsl_qbman_portal.h
new file mode 100644
index 0000000..ee0e4aa
--- /dev/null
+++ b/include/fsl-mc/fsl_qbman_portal.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor
+ */
+
+#ifndef _FSL_QBMAN_PORTAL_H
+#define _FSL_QBMAN_PORTAL_H
+
+#include <fsl-mc/fsl_qbman_base.h>
+
+/* Create and destroy a functional object representing the given QBMan portal
+ * descriptor. */
+struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *);
+
+	/************/
+	/* Dequeues */
+	/************/
+
+/* See the QBMan driver API documentation for details on the enqueue
+ * mechanisms. NB: the use of a 'ldpaa_' prefix for this type is because it is
+ * primarily used by the "DPIO" layer that sits above (and hides) the QBMan
+ * driver. The structure is defined in the DPIO interface, but to avoid circular
+ * dependencies we just pre/re-declare it here opaquely. */
+struct ldpaa_dq;
+
+
+/* ------------------- */
+/* Pull-mode dequeuing */
+/* ------------------- */
+
+struct qbman_pull_desc {
+	uint32_t dont_manipulate_directly[6];
+};
+
+/* Clear the contents of a descriptor to default/starting state. */
+void qbman_pull_desc_clear(struct qbman_pull_desc *);
+/* If not called, or if called with 'storage' as NULL, the result pull dequeues
+ * will produce results to DQRR. If 'storage' is non-NULL, then results are
+ * produced to the given memory location (using the physical/DMA address which
+ * the caller provides in 'storage_phys'), and 'stash' controls whether or not
+ * those writes to main-memory express a cache-warming attribute. */
+void qbman_pull_desc_set_storage(struct qbman_pull_desc *,
+				 struct ldpaa_dq *storage,
+				 dma_addr_t storage_phys,
+				 int stash);
+/* numframes must be between 1 and 16, inclusive */
+void qbman_pull_desc_set_numframes(struct qbman_pull_desc *, uint8_t numframes);
+/* token is the value that shows up in the dequeue results that can be used to
+ * detect when the results have been published, and is not really used when
+ * dequeue results go to DQRR. The easiest technique is to zero result "storage"
+ * before issuing a pull dequeue, and use any non-zero 'token' value. */
+void qbman_pull_desc_set_token(struct qbman_pull_desc *, uint8_t token);
+/* Exactly one of the following descriptor "actions" should be set. (Calling any
+ * one of these will replace the effect of any prior call to one of these.)
+ * - pull dequeue from the given frame queue (FQ)
+ * - pull dequeue from any FQ in the given work queue (WQ)
+ * - pull dequeue from any FQ in any WQ in the given channel
+ */
+void qbman_pull_desc_set_fq(struct qbman_pull_desc *, uint32_t fqid);
+
+/* Issue the pull dequeue command */
+int qbman_swp_pull(struct qbman_swp *, struct qbman_pull_desc *);
+
+/* -------------------------------- */
+/* Polling DQRR for dequeue results */
+/* -------------------------------- */
+
+/* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry
+ * only once, so repeated calls can return a sequence of DQRR entries, without
+ * requiring they be consumed immediately or in any particular order. */
+const struct ldpaa_dq *qbman_swp_dqrr_next(struct qbman_swp *);
+/* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */
+void qbman_swp_dqrr_consume(struct qbman_swp *, const struct ldpaa_dq *);
+
+/* ------------------------------------------------- */
+/* Polling user-provided storage for dequeue results */
+/* ------------------------------------------------- */
+
+/* Only used for user-provided storage of dequeue results, not DQRR. Prior to
+ * being used, the storage must set "oldtoken", so that the driver notices when
+ * hardware has filled it in with results using a "newtoken". NB, for efficiency
+ * purposes, the driver will perform any required endianness conversion to
+ * ensure that the user's dequeue result storage is in host-endian format
+ * (whether or not that is the same as the little-endian format that hardware
+ * DMA'd to the user's storage). As such, once the user has called
+ * qbman_dq_entry_has_newtoken() and been returned a valid dequeue result, they
+ * should not call it again on the same memory location (except of course if
+ * another dequeue command has been executed to produce a new result to that
+ * location).
+ */
+void qbman_dq_entry_set_oldtoken(struct ldpaa_dq *,
+				 unsigned int num_entries,
+				 uint8_t oldtoken);
+int qbman_dq_entry_has_newtoken(struct qbman_swp *,
+				const struct ldpaa_dq *,
+				uint8_t newtoken);
+
+/* -------------------------------------------------------- */
+/* Parsing dequeue entries (DQRR and user-provided storage) */
+/* -------------------------------------------------------- */
+
+/* DQRR entries may contain non-dequeue results, ie. notifications */
+int qbman_dq_entry_is_DQ(const struct ldpaa_dq *);
+
+	/************/
+	/* Enqueues */
+	/************/
+
+struct qbman_eq_desc {
+	uint32_t dont_manipulate_directly[8];
+};
+
+
+/* Clear the contents of a descriptor to default/starting state. */
+void qbman_eq_desc_clear(struct qbman_eq_desc *);
+/* Exactly one of the following descriptor "actions" should be set. (Calling
+ * any one of these will replace the effect of any prior call to one of these.)
+ * - enqueue without order-restoration
+ * - enqueue with order-restoration
+ * - fill a hole in the order-restoration sequence, without any enqueue
+ * - advance NESN (Next Expected Sequence Number), without any enqueue
+ * 'respond_success' indicates whether an enqueue response should be DMA'd
+ * after success (otherwise a response is DMA'd only after failure).
+ * 'incomplete' indicates that other fragments of the same 'seqnum' are yet to
+ * be enqueued.
+ */
+void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *, int respond_success);
+void qbman_eq_desc_set_response(struct qbman_eq_desc *,
+				dma_addr_t storage_phys,
+				int stash);
+/* token is the value that shows up in an enqueue response that can be used to
+ * detect when the results have been published. The easiest technique is to zero
+ * result "storage" before issuing an enqueue, and use any non-zero 'token'
+ * value. */
+void qbman_eq_desc_set_token(struct qbman_eq_desc *, uint8_t token);
+/* Exactly one of the following descriptor "targets" should be set. (Calling any
+ * one of these will replace the effect of any prior call to one of these.)
+ * - enqueue to a frame queue
+ * - enqueue to a queuing destination
+ * Note, that none of these will have any affect if the "action" type has been
+ * set to "orp_hole" or "orp_nesn".
+ */
+void qbman_eq_desc_set_fq(struct qbman_eq_desc *, uint32_t fqid);
+void qbman_eq_desc_set_qd(struct qbman_eq_desc *, uint32_t qdid,
+			  uint32_t qd_bin, uint32_t qd_prio);
+
+/* Issue an enqueue command. ('fd' should only be NULL if the "action" of the
+ * descriptor is "orp_hole" or "orp_nesn".) */
+int qbman_swp_enqueue(struct qbman_swp *, const struct qbman_eq_desc *,
+		      const struct qbman_fd *fd);
+
+	/*******************/
+	/* Buffer releases */
+	/*******************/
+
+struct qbman_release_desc {
+	uint32_t dont_manipulate_directly[1];
+};
+
+/* Clear the contents of a descriptor to default/starting state. */
+void qbman_release_desc_clear(struct qbman_release_desc *);
+/* Set the ID of the buffer pool to release to */
+void qbman_release_desc_set_bpid(struct qbman_release_desc *, uint32_t bpid);
+/* Issue a release command. 'num_buffers' must be less than 8. */
+int qbman_swp_release(struct qbman_swp *, const struct qbman_release_desc *,
+		      const uint64_t *buffers, unsigned int num_buffers);
+
+	/*******************/
+	/* Buffer acquires */
+	/*******************/
+
+int qbman_swp_acquire(struct qbman_swp *, uint32_t bpid, uint64_t *buffers,
+		      unsigned int num_buffers);
+#endif /* !_FSL_QBMAN_PORTAL_H */
diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h
new file mode 100644
index 0000000..b55c39c
--- /dev/null
+++ b/include/fsl-mc/ldpaa_wriop.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Freescale Semiconductor
+ */
+
+#ifndef __LDPAA_WRIOP_H
+#define __LDPAA_WRIOP_H
+
+#include <phy.h>
+
+#define DEFAULT_WRIOP_MDIO1_NAME "FSL_MDIO0"
+#define DEFAULT_WRIOP_MDIO2_NAME "FSL_MDIO1"
+#define WRIOP_MAX_PHY_NUM        2
+
+enum wriop_port {
+	WRIOP1_DPMAC1 = 1,
+	WRIOP1_DPMAC2,
+	WRIOP1_DPMAC3,
+	WRIOP1_DPMAC4,
+	WRIOP1_DPMAC5,
+	WRIOP1_DPMAC6,
+	WRIOP1_DPMAC7,
+	WRIOP1_DPMAC8,
+	WRIOP1_DPMAC9,
+	WRIOP1_DPMAC10,
+	WRIOP1_DPMAC11,
+	WRIOP1_DPMAC12,
+	WRIOP1_DPMAC13,
+	WRIOP1_DPMAC14,
+	WRIOP1_DPMAC15,
+	WRIOP1_DPMAC16,
+	WRIOP1_DPMAC17,
+	WRIOP1_DPMAC18,
+	WRIOP1_DPMAC19,
+	WRIOP1_DPMAC20,
+	WRIOP1_DPMAC21,
+	WRIOP1_DPMAC22,
+	WRIOP1_DPMAC23,
+	WRIOP1_DPMAC24,
+	NUM_WRIOP_PORTS,
+};
+
+struct wriop_dpmac_info {
+	u8 enabled;
+	u8 id;
+	u8 board_mux;
+	int phy_addr[WRIOP_MAX_PHY_NUM];
+	phy_interface_t enet_if;
+	struct phy_device *phydev[WRIOP_MAX_PHY_NUM];
+	struct mii_dev *bus;
+};
+
+extern struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
+
+void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl);
+void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if);
+int wriop_disable_dpmac(int dpmac_id);
+int wriop_enable_dpmac(int dpmac_id);
+int wriop_is_enabled_dpmac(int dpmac_id);
+int wriop_set_mdio(int dpmac_id, struct mii_dev *bus);
+struct mii_dev *wriop_get_mdio(int dpmac_id);
+int wriop_set_phy_address(int dpmac_id, int phy_num, int address);
+int wriop_get_phy_address(int dpmac_id, int phy_num);
+int wriop_set_phy_dev(int dpmac_id, int phy_num, struct phy_device *phydev);
+struct phy_device *wriop_get_phy_dev(int dpmac_id, int phy_num);
+phy_interface_t wriop_get_enet_if(int dpmac_id);
+
+void wriop_dpmac_disable(int dpmac_id);
+void wriop_dpmac_enable(int dpmac_id);
+phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl);
+void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl);
+void wriop_init_rgmii(void);
+#endif	/* __LDPAA_WRIOP_H */
diff --git a/include/fsl_csu.h b/include/fsl_csu.h
new file mode 100644
index 0000000..0e59ac3
--- /dev/null
+++ b/include/fsl_csu.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ */
+
+#ifndef __FSL_CSU_H__
+#define __FSL_CSU_H__
+
+enum csu_cslx_access {
+	CSU_NS_SUP_R = 0x08,
+	CSU_NS_SUP_W = 0x80,
+	CSU_NS_SUP_RW = 0x88,
+	CSU_NS_USER_R = 0x04,
+	CSU_NS_USER_W = 0x40,
+	CSU_NS_USER_RW = 0x44,
+	CSU_S_SUP_R = 0x02,
+	CSU_S_SUP_W = 0x20,
+	CSU_S_SUP_RW = 0x22,
+	CSU_S_USER_R = 0x01,
+	CSU_S_USER_W = 0x10,
+	CSU_S_USER_RW = 0x11,
+	CSU_ALL_RW = 0xff,
+};
+
+struct csu_ns_dev {
+	unsigned long ind;
+	uint32_t val;
+};
+
+void enable_layerscape_ns_access(void);
+void set_devices_ns_access(unsigned long, u16 val);
+void set_pcie_ns_access(int pcie, u16 val);
+
+#endif
diff --git a/include/fsl_dcu_fb.h b/include/fsl_dcu_fb.h
new file mode 100644
index 0000000..7a5347a
--- /dev/null
+++ b/include/fsl_dcu_fb.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ */
+#include <linux/fb.h>
+
+int fsl_dcu_init(struct fb_info *fbinfo,
+		 unsigned int xres,
+		 unsigned int yres,
+		 unsigned int pixel_format);
+
+int fsl_dcu_fixedfb_setup(void *blob);
+
+/* Prototypes for external board-specific functions */
+int platform_dcu_init(struct fb_info *fbinfo,
+		      unsigned int xres,
+		      unsigned int yres,
+		      const char *port,
+		      struct fb_videomode *dcu_fb_videomode);
+unsigned int dcu_set_pixel_clock(unsigned int pixclock);
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
new file mode 100644
index 0000000..2476f40
--- /dev/null
+++ b/include/fsl_ddr.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef FSL_DDR_MAIN_H
+#define FSL_DDR_MAIN_H
+
+#include <fsl_ddrc_version.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+#include <common_timing_params.h>
+
+#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
+/* All controllers are for main memory */
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	CONFIG_SYS_NUM_DDR_CTLRS
+#endif
+
+#ifdef CONFIG_SYS_FSL_DDR_LE
+#define ddr_in32(a)	in_le32(a)
+#define ddr_out32(a, v)	out_le32(a, v)
+#define ddr_setbits32(a, v)	setbits_le32(a, v)
+#define ddr_clrbits32(a, v)	clrbits_le32(a, v)
+#define ddr_clrsetbits32(a, clear, set)	clrsetbits_le32(a, clear, set)
+#else
+#define ddr_in32(a)	in_be32(a)
+#define ddr_out32(a, v)	out_be32(a, v)
+#define ddr_setbits32(a, v)	setbits_be32(a, v)
+#define ddr_clrbits32(a, v)	clrbits_be32(a, v)
+#define ddr_clrsetbits32(a, clear, set)	clrsetbits_be32(a, clear, set)
+#endif
+
+u32 fsl_ddr_get_version(unsigned int ctrl_num);
+
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
+/*
+ * Bind the main DDR setup driver's generic names
+ * to this specific DDR technology.
+ */
+static __inline__ int
+compute_dimm_parameters(const unsigned int ctrl_num,
+			const generic_spd_eeprom_t *spd,
+			dimm_params_t *pdimm,
+			unsigned int dimm_number)
+{
+	return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
+}
+#endif
+
+/*
+ * Data Structures
+ *
+ * All data structures have to be on the stack
+ */
+#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
+
+typedef struct {
+	generic_spd_eeprom_t
+	   spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
+	struct dimm_params_s
+	   dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
+	memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
+	common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
+	fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
+	unsigned int first_ctrl;
+	unsigned int num_ctrls;
+	unsigned long long mem_base;
+	unsigned int dimm_slots_per_ctrl;
+	int (*board_need_mem_reset)(void);
+	void (*board_mem_reset)(void);
+	void (*board_mem_de_reset)(void);
+} fsl_ddr_info_t;
+
+/* Compute steps */
+#define STEP_GET_SPD                 (1 << 0)
+#define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
+#define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
+#define STEP_GATHER_OPTS             (1 << 3)
+#define STEP_ASSIGN_ADDRESSES        (1 << 4)
+#define STEP_COMPUTE_REGS            (1 << 5)
+#define STEP_PROGRAM_REGS            (1 << 6)
+#define STEP_ALL                     0xFFF
+
+unsigned long long
+fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
+				       unsigned int size_only);
+const char *step_to_string(unsigned int step);
+
+unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
+			       const memctl_options_t *popts,
+			       fsl_ddr_cfg_regs_t *ddr,
+			       const common_timing_params_t *common_dimm,
+			       const dimm_params_t *dimm_parameters,
+			       unsigned int dbw_capacity_adjust,
+			       unsigned int size_only);
+unsigned int compute_lowest_common_dimm_parameters(
+				const unsigned int ctrl_num,
+				const dimm_params_t *dimm_params,
+				common_timing_params_t *outpdimm,
+				unsigned int number_of_dimms);
+unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
+				memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num);
+void check_interleaving_options(fsl_ddr_info_t *pinfo);
+
+unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
+unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
+unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
+void fsl_ddr_set_lawbar(
+		const common_timing_params_t *memctl_common_params,
+		unsigned int memctl_interleaved,
+		unsigned int ctrl_num);
+void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
+				 unsigned int last_ctrl);
+
+int fsl_ddr_interactive_env_var_exists(void);
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+		     unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
+void board_add_ram_info(int use_default);
+
+/* processor specific function */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+				   unsigned int ctrl_num, int step);
+void remove_unused_controllers(fsl_ddr_info_t *info);
+
+/* board specific function */
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			unsigned int controller_number,
+			unsigned int dimm_number);
+void update_spd_address(unsigned int ctrl_num,
+			unsigned int slot,
+			unsigned int *addr);
+
+void erratum_a009942_check_cpo(void);
+#endif
diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h
new file mode 100644
index 0000000..58b42b8
--- /dev/null
+++ b/include/fsl_ddr_dimm_params.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2008-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP Semiconductor
+ */
+
+#ifndef DDR2_DIMM_PARAMS_H
+#define DDR2_DIMM_PARAMS_H
+
+#define EDC_DATA_PARITY	1
+#define EDC_ECC		2
+#define EDC_AC_PARITY	4
+
+/* Parameters for a DDR dimm computed from the SPD */
+typedef struct dimm_params_s {
+
+	/* DIMM organization parameters */
+	char mpart[19];		/* guaranteed null terminated */
+
+	unsigned int n_ranks;
+	unsigned int die_density;
+	unsigned long long rank_density;
+	unsigned long long capacity;
+	unsigned int data_width;
+	unsigned int primary_sdram_width;
+	unsigned int ec_sdram_width;
+	unsigned int registered_dimm;
+	unsigned int package_3ds;	/* number of dies in 3DS DIMM */
+	unsigned int device_width;	/* x4, x8, x16 components */
+
+	/* SDRAM device parameters */
+	unsigned int n_row_addr;
+	unsigned int n_col_addr;
+	unsigned int edc_config;	/* 0 = none, 1 = parity, 2 = ECC */
+#ifdef CONFIG_SYS_FSL_DDR4
+	unsigned int bank_addr_bits;
+	unsigned int bank_group_bits;
+#else
+	unsigned int n_banks_per_sdram_device;
+#endif
+	unsigned int burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
+
+	/* used in computing base address of DIMMs */
+	unsigned long long base_address;
+	/* mirrored DIMMs */
+	unsigned int mirrored_dimm;	/* only for ddr3 */
+
+	/* DIMM timing parameters */
+
+	int mtb_ps;	/* medium timebase ps */
+	int ftb_10th_ps; /* fine timebase, in 1/10 ps */
+	int taa_ps;	/* minimum CAS latency time */
+	int tfaw_ps;	/* four active window delay */
+
+	/*
+	 * SDRAM clock periods
+	 * The range for these are 1000-10000 so a short should be sufficient
+	 */
+	int tckmin_x_ps;
+	int tckmin_x_minus_1_ps;
+	int tckmin_x_minus_2_ps;
+	int tckmax_ps;
+
+	/* SPD-defined CAS latencies */
+	unsigned int caslat_x;
+	unsigned int caslat_x_minus_1;
+	unsigned int caslat_x_minus_2;
+
+	unsigned int caslat_lowest_derated;	/* Derated CAS latency */
+
+	/* basic timing parameters */
+	int trcd_ps;
+	int trp_ps;
+	int tras_ps;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+	int trfc1_ps;
+	int trfc2_ps;
+	int trfc4_ps;
+	int trrds_ps;
+	int trrdl_ps;
+	int tccdl_ps;
+	int trfc_slr_ps;
+#else
+	int twr_ps;	/* maximum = 63750 ps */
+	int trfc_ps;	/* max = 255 ns + 256 ns + .75 ns
+				       = 511750 ps */
+	int trrd_ps;	/* maximum = 63750 ps */
+	int twtr_ps;	/* maximum = 63750 ps */
+	int trtp_ps;	/* byte 38, spd->trtp */
+#endif
+
+	int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+
+	int refresh_rate_ps;
+	int extended_op_srt;
+
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
+	int tis_ps;	/* byte 32, spd->ca_setup */
+	int tih_ps;	/* byte 33, spd->ca_hold */
+	int tds_ps;	/* byte 34, spd->data_setup */
+	int tdh_ps;	/* byte 35, spd->data_hold */
+	int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
+	int tqhs_ps;	/* byte 45, spd->tqhs */
+#endif
+
+	/* DDR3 & DDR4 RDIMM */
+	unsigned char rcw[16];	/* Register Control Word 0-15 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	unsigned int dq_mapping[18];
+	unsigned int dq_mapping_ors;
+#endif
+} dimm_params_t;
+
+unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
+					 const generic_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number);
+
+#endif
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
new file mode 100644
index 0000000..56c9db2
--- /dev/null
+++ b/include/fsl_ddr_sdram.h
@@ -0,0 +1,490 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2008-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP Semiconductor
+ */
+
+#ifndef FSL_DDR_MEMCTL_H
+#define FSL_DDR_MEMCTL_H
+
+/*
+ * Pick a basic DDR Technology.
+ */
+#include <ddr_spd.h>
+#include <fsl_ddrc_version.h>
+
+#define SDRAM_TYPE_DDR1		2
+#define SDRAM_TYPE_DDR2		3
+#define SDRAM_TYPE_LPDDR1	6
+#define SDRAM_TYPE_DDR3		7
+#define SDRAM_TYPE_DDR4		5
+
+#define DDR_BL4		4	/* burst length 4 */
+#define DDR_BC4		DDR_BL4	/* burst chop for ddr3 */
+#define DDR_OTF		6	/* on-the-fly BC4 and BL8 */
+#define DDR_BL8		8	/* burst length 8 */
+
+#define DDR3_RTT_OFF		0
+#define DDR3_RTT_60_OHM		1 /* RTT_Nom = RZQ/4 */
+#define DDR3_RTT_120_OHM	2 /* RTT_Nom = RZQ/2 */
+#define DDR3_RTT_40_OHM		3 /* RTT_Nom = RZQ/6 */
+#define DDR3_RTT_20_OHM		4 /* RTT_Nom = RZQ/12 */
+#define DDR3_RTT_30_OHM		5 /* RTT_Nom = RZQ/8 */
+
+#define DDR4_RTT_OFF		0
+#define DDR4_RTT_60_OHM		1	/* RZQ/4 */
+#define DDR4_RTT_120_OHM	2	/* RZQ/2 */
+#define DDR4_RTT_40_OHM		3	/* RZQ/6 */
+#define DDR4_RTT_240_OHM	4	/* RZQ/1 */
+#define DDR4_RTT_48_OHM		5	/* RZQ/5 */
+#define DDR4_RTT_80_OHM		6	/* RZQ/3 */
+#define DDR4_RTT_34_OHM		7	/* RZQ/7 */
+
+#define DDR2_RTT_OFF		0
+#define DDR2_RTT_75_OHM		1
+#define DDR2_RTT_150_OHM	2
+#define DDR2_RTT_50_OHM		3
+
+#if defined(CONFIG_SYS_FSL_DDR1)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
+typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR1
+#endif
+#elif defined(CONFIG_SYS_FSL_DDR2)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)
+typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
+#endif
+#elif defined(CONFIG_SYS_FSL_DDR3)
+typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
+#endif
+#elif defined(CONFIG_SYS_FSL_DDR4)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
+typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR4
+#endif
+#endif	/* #if defined(CONFIG_SYS_FSL_DDR1) */
+
+#define FSL_DDR_ODT_NEVER		0x0
+#define FSL_DDR_ODT_CS			0x1
+#define FSL_DDR_ODT_ALL_OTHER_CS	0x2
+#define FSL_DDR_ODT_OTHER_DIMM		0x3
+#define FSL_DDR_ODT_ALL			0x4
+#define FSL_DDR_ODT_SAME_DIMM		0x5
+#define FSL_DDR_ODT_CS_AND_OTHER_DIMM	0x6
+#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM	0x7
+
+/* define bank(chip select) interleaving mode */
+#define FSL_DDR_CS0_CS1			0x40
+#define FSL_DDR_CS2_CS3			0x20
+#define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
+#define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
+
+/* define memory controller interleaving mode */
+#define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
+#define FSL_DDR_PAGE_INTERLEAVING	0x1
+#define FSL_DDR_BANK_INTERLEAVING	0x2
+#define FSL_DDR_SUPERBANK_INTERLEAVING	0x3
+#define FSL_DDR_256B_INTERLEAVING	0x8
+#define FSL_DDR_3WAY_1KB_INTERLEAVING	0xA
+#define FSL_DDR_3WAY_4KB_INTERLEAVING	0xC
+#define FSL_DDR_3WAY_8KB_INTERLEAVING	0xD
+/* placeholder for 4-way interleaving */
+#define FSL_DDR_4WAY_1KB_INTERLEAVING	0x1A
+#define FSL_DDR_4WAY_4KB_INTERLEAVING	0x1C
+#define FSL_DDR_4WAY_8KB_INTERLEAVING	0x1D
+
+#define SDRAM_CS_CONFIG_EN		0x80000000
+
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN		0x80000000
+#define SDRAM_CFG_SREN			0x40000000
+#define SDRAM_CFG_ECC_EN		0x20000000
+#define SDRAM_CFG_RD_EN			0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
+#define SDRAM_CFG_DYN_PWR		0x00200000
+#define SDRAM_CFG_DBW_MASK		0x00180000
+#define SDRAM_CFG_DBW_SHIFT		19
+#define SDRAM_CFG_32_BE			0x00080000
+#define SDRAM_CFG_16_BE			0x00100000
+#define SDRAM_CFG_8_BE			0x00040000
+#define SDRAM_CFG_NCAP			0x00020000
+#define SDRAM_CFG_2T_EN			0x00008000
+#define SDRAM_CFG_BI			0x00000001
+
+#define SDRAM_CFG2_FRC_SR		0x80000000
+#define SDRAM_CFG2_D_INIT		0x00000010
+#define SDRAM_CFG2_AP_EN		0x00000020
+#define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
+#define SDRAM_CFG2_ODT_NEVER		0
+#define SDRAM_CFG2_ODT_ONLY_WRITE	1
+#define SDRAM_CFG2_ODT_ONLY_READ	2
+#define SDRAM_CFG2_ODT_ALWAYS		3
+
+#define SDRAM_INTERVAL_BSTOPRE	0x3FFF
+#define TIMING_CFG_2_CPO_MASK	0x0F800000
+
+#if defined(CONFIG_SYS_FSL_DDR_VER) && \
+	(CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
+#define RD_TO_PRE_MASK		0xf
+#define RD_TO_PRE_SHIFT		13
+#define WR_DATA_DELAY_MASK	0xf
+#define WR_DATA_DELAY_SHIFT	9
+#else
+#define RD_TO_PRE_MASK		0x7
+#define RD_TO_PRE_SHIFT		13
+#define WR_DATA_DELAY_MASK	0x7
+#define WR_DATA_DELAY_SHIFT	10
+#endif
+
+/* DDR_EOR register */
+#define DDR_EOR_RD_REOD_DIS	0x07000000
+#define DDR_EOR_WD_REOD_DIS	0x00100000
+
+/* DDR_MD_CNTL */
+#define MD_CNTL_MD_EN		0x80000000
+#define MD_CNTL_CS_SEL_CS0	0x00000000
+#define MD_CNTL_CS_SEL_CS1	0x10000000
+#define MD_CNTL_CS_SEL_CS2	0x20000000
+#define MD_CNTL_CS_SEL_CS3	0x30000000
+#define MD_CNTL_CS_SEL_CS0_CS1	0x40000000
+#define MD_CNTL_CS_SEL_CS2_CS3	0x50000000
+#define MD_CNTL_MD_SEL_MR	0x00000000
+#define MD_CNTL_MD_SEL_EMR	0x01000000
+#define MD_CNTL_MD_SEL_EMR2	0x02000000
+#define MD_CNTL_MD_SEL_EMR3	0x03000000
+#define MD_CNTL_SET_REF		0x00800000
+#define MD_CNTL_SET_PRE		0x00400000
+#define MD_CNTL_CKE_CNTL_LOW	0x00100000
+#define MD_CNTL_CKE_CNTL_HIGH	0x00200000
+#define MD_CNTL_WRCW		0x00080000
+#define MD_CNTL_MD_VALUE(x)	(x & 0x0000FFFF)
+#define MD_CNTL_CS_SEL(x)	(((x) & 0x7) << 28)
+#define MD_CNTL_MD_SEL(x)	(((x) & 0xf) << 24)
+
+/* DDR_CDR1 */
+#define DDR_CDR1_DHC_EN	0x80000000
+#define DDR_CDR1_V0PT9_EN	0x40000000
+#define DDR_CDR1_ODT_SHIFT	17
+#define DDR_CDR1_ODT_MASK	0x6
+#define DDR_CDR2_ODT_MASK	0x1
+#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
+#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+#define DDR_CDR2_VREF_OVRD(x)	(0x00008080 | ((((x) - 37) & 0x3F) << 8))
+#define DDR_CDR2_VREF_TRAIN_EN	0x00000080
+#define DDR_CDR2_VREF_RANGE_2	0x00000040
+
+/* DDR ERR_DISABLE */
+#define DDR_ERR_DISABLE_APED	(1 << 8)  /* Address parity error disable */
+
+/* Mode Registers */
+#define DDR_MR5_CA_PARITY_LAT_4_CLK	0x1 /* for DDR4-1600/1866/2133 */
+#define DDR_MR5_CA_PARITY_LAT_5_CLK	0x2 /* for DDR4-2400 */
+
+/* DEBUG_26 register */
+#define DDR_CAS_TO_PRE_SUB_MASK  0x0000f000 /* CAS to preamble subtract value */
+#define DDR_CAS_TO_PRE_SUB_SHIFT 12
+
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS	(1 << 10) /* Transmit Bit Deskew Disable */
+
+
+#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
+	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
+#ifdef CONFIG_SYS_FSL_DDR3L
+#define DDR_CDR_ODT_OFF		0x0
+#define DDR_CDR_ODT_120ohm	0x1
+#define DDR_CDR_ODT_200ohm	0x2
+#define DDR_CDR_ODT_75ohm	0x3
+#define DDR_CDR_ODT_60ohm	0x5
+#define DDR_CDR_ODT_46ohm	0x7
+#elif defined(CONFIG_SYS_FSL_DDR4)
+#define DDR_CDR_ODT_OFF		0x0
+#define DDR_CDR_ODT_100ohm	0x1
+#define DDR_CDR_ODT_120OHM	0x2
+#define DDR_CDR_ODT_80ohm	0x3
+#define DDR_CDR_ODT_60ohm	0x4
+#define DDR_CDR_ODT_40ohm	0x5
+#define DDR_CDR_ODT_50ohm	0x6
+#define DDR_CDR_ODT_30ohm	0x7
+#else
+#define DDR_CDR_ODT_OFF		0x0
+#define DDR_CDR_ODT_120ohm	0x1
+#define DDR_CDR_ODT_180ohm	0x2
+#define DDR_CDR_ODT_75ohm	0x3
+#define DDR_CDR_ODT_110ohm	0x4
+#define DDR_CDR_ODT_60hm	0x5
+#define DDR_CDR_ODT_70ohm	0x6
+#define DDR_CDR_ODT_47ohm	0x7
+#endif /* DDR3L */
+#else
+#define DDR_CDR_ODT_75ohm	0x0
+#define DDR_CDR_ODT_55ohm	0x1
+#define DDR_CDR_ODT_60ohm	0x2
+#define DDR_CDR_ODT_50ohm	0x3
+#define DDR_CDR_ODT_150ohm	0x4
+#define DDR_CDR_ODT_43ohm	0x5
+#define DDR_CDR_ODT_120ohm	0x6
+#endif
+
+#define DDR_INIT_ADDR_EXT_UIA	(1 << 31)
+
+/* Record of register values computed */
+typedef struct fsl_ddr_cfg_regs_s {
+	struct {
+		unsigned int bnds;
+		unsigned int config;
+		unsigned int config_2;
+	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
+	unsigned int timing_cfg_3;
+	unsigned int timing_cfg_0;
+	unsigned int timing_cfg_1;
+	unsigned int timing_cfg_2;
+	unsigned int ddr_sdram_cfg;
+	unsigned int ddr_sdram_cfg_2;
+	unsigned int ddr_sdram_cfg_3;
+	unsigned int ddr_sdram_mode;
+	unsigned int ddr_sdram_mode_2;
+	unsigned int ddr_sdram_mode_3;
+	unsigned int ddr_sdram_mode_4;
+	unsigned int ddr_sdram_mode_5;
+	unsigned int ddr_sdram_mode_6;
+	unsigned int ddr_sdram_mode_7;
+	unsigned int ddr_sdram_mode_8;
+	unsigned int ddr_sdram_mode_9;
+	unsigned int ddr_sdram_mode_10;
+	unsigned int ddr_sdram_mode_11;
+	unsigned int ddr_sdram_mode_12;
+	unsigned int ddr_sdram_mode_13;
+	unsigned int ddr_sdram_mode_14;
+	unsigned int ddr_sdram_mode_15;
+	unsigned int ddr_sdram_mode_16;
+	unsigned int ddr_sdram_md_cntl;
+	unsigned int ddr_sdram_interval;
+	unsigned int ddr_data_init;
+	unsigned int ddr_sdram_clk_cntl;
+	unsigned int ddr_init_addr;
+	unsigned int ddr_init_ext_addr;
+	unsigned int timing_cfg_4;
+	unsigned int timing_cfg_5;
+	unsigned int timing_cfg_6;
+	unsigned int timing_cfg_7;
+	unsigned int timing_cfg_8;
+	unsigned int timing_cfg_9;
+	unsigned int ddr_zq_cntl;
+	unsigned int ddr_wrlvl_cntl;
+	unsigned int ddr_wrlvl_cntl_2;
+	unsigned int ddr_wrlvl_cntl_3;
+	unsigned int ddr_sr_cntr;
+	unsigned int ddr_sdram_rcw_1;
+	unsigned int ddr_sdram_rcw_2;
+	unsigned int ddr_sdram_rcw_3;
+	unsigned int ddr_sdram_rcw_4;
+	unsigned int ddr_sdram_rcw_5;
+	unsigned int ddr_sdram_rcw_6;
+	unsigned int dq_map_0;
+	unsigned int dq_map_1;
+	unsigned int dq_map_2;
+	unsigned int dq_map_3;
+	unsigned int ddr_eor;
+	unsigned int ddr_cdr1;
+	unsigned int ddr_cdr2;
+	unsigned int err_disable;
+	unsigned int err_int_en;
+	unsigned int debug[64];
+} fsl_ddr_cfg_regs_t;
+
+typedef struct memctl_options_partial_s {
+	unsigned int all_dimms_ecc_capable;
+	unsigned int all_dimms_tckmax_ps;
+	unsigned int all_dimms_burst_lengths_bitmask;
+	unsigned int all_dimms_registered;
+	unsigned int all_dimms_unbuffered;
+	/*	unsigned int lowest_common_spd_caslat; */
+	unsigned int all_dimms_minimum_trcd_ps;
+} memctl_options_partial_t;
+
+#define DDR_DATA_BUS_WIDTH_64 0
+#define DDR_DATA_BUS_WIDTH_32 1
+#define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0	0x04000001
+/*
+ * Generalized parameters for memory controller configuration,
+ * might be a little specific to the FSL memory controller
+ */
+typedef struct memctl_options_s {
+	/*
+	 * Memory organization parameters
+	 *
+	 * if DIMM is present in the system
+	 * where DIMMs are with respect to chip select
+	 * where chip selects are with respect to memory boundaries
+	 */
+	unsigned int registered_dimm_en;    /* use registered DIMM support */
+
+	/* Options local to a Chip Select */
+	struct cs_local_opts_s {
+		unsigned int auto_precharge;
+		unsigned int odt_rd_cfg;
+		unsigned int odt_wr_cfg;
+		unsigned int odt_rtt_norm;
+		unsigned int odt_rtt_wr;
+	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
+
+	/* Special configurations for chip select */
+	unsigned int memctl_interleaving;
+	unsigned int memctl_interleaving_mode;
+	unsigned int ba_intlv_ctl;
+	unsigned int addr_hash;
+
+	/* Operational mode parameters */
+	unsigned int ecc_mode;	 /* Use ECC? */
+	/* Initialize ECC using memory controller? */
+	unsigned int ecc_init_using_memctl;
+	unsigned int dqs_config;	/* Use DQS? maybe only with DDR2? */
+	/* SREN - self-refresh during sleep */
+	unsigned int self_refresh_in_sleep;
+	/* SR_IE - Self-refresh interrupt enable */
+	unsigned int self_refresh_interrupt_en;
+	unsigned int dynamic_power;	/* DYN_PWR */
+	/* memory data width to use (16-bit, 32-bit, 64-bit) */
+	unsigned int data_bus_width;
+	unsigned int burst_length;	/* BL4, OTF and BL8 */
+	/* On-The-Fly Burst Chop enable */
+	unsigned int otf_burst_chop_en;
+	/* mirrior DIMMs for DDR3 */
+	unsigned int mirrored_dimm;
+	unsigned int quad_rank_present;
+	unsigned int ap_en;	/* address parity enable for RDIMM/DDR4-UDIMM */
+	unsigned int x4_en;	/* enable x4 devices */
+	unsigned int package_3ds;
+
+	/* Global Timing Parameters */
+	unsigned int cas_latency_override;
+	unsigned int cas_latency_override_value;
+	unsigned int use_derated_caslat;
+	unsigned int additive_latency_override;
+	unsigned int additive_latency_override_value;
+
+	unsigned int clk_adjust;		/* */
+	unsigned int cpo_override;		/* override timing_cfg_2[CPO]*/
+	unsigned int cpo_sample;		/* optimize debug_29[24:31] */
+	unsigned int write_data_delay;		/* DQS adjust */
+
+	unsigned int cswl_override;
+	unsigned int wrlvl_override;
+	unsigned int wrlvl_sample;		/* Write leveling */
+	unsigned int wrlvl_start;
+	unsigned int wrlvl_ctl_2;
+	unsigned int wrlvl_ctl_3;
+
+	unsigned int half_strength_driver_enable;
+	unsigned int twot_en;
+	unsigned int threet_en;
+	unsigned int bstopre;
+	unsigned int tfaw_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
+
+	/* Rtt impedance */
+	unsigned int rtt_override;		/* rtt_override enable */
+	unsigned int rtt_override_value;	/* that is Rtt_Nom for DDR3 */
+	unsigned int rtt_wr_override_value;	/* this is Rtt_WR for DDR3 */
+
+	/* Automatic self refresh */
+	unsigned int auto_self_refresh_en;
+	unsigned int sr_it;
+	/* ZQ calibration */
+	unsigned int zq_en;
+	/* Write leveling */
+	unsigned int wrlvl_en;
+	/* RCW override for RDIMM */
+	unsigned int rcw_override;
+	unsigned int rcw_1;
+	unsigned int rcw_2;
+	unsigned int rcw_3;
+	/* control register 1 */
+	unsigned int ddr_cdr1;
+	unsigned int ddr_cdr2;
+
+	unsigned int trwt_override;
+	unsigned int trwt;			/* read-to-write turnaround */
+} memctl_options_t;
+
+phys_size_t fsl_ddr_sdram(void);
+phys_size_t fsl_ddr_sdram_size(void);
+phys_size_t fsl_other_ddr_sdram(unsigned long long base,
+				unsigned int first_ctrl,
+				unsigned int num_ctrls,
+				unsigned int dimm_slots_per_ctrl,
+				int (*board_need_reset)(void),
+				void (*board_reset)(void),
+				void (*board_de_reset)(void));
+extern int fsl_use_spd(void);
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+			     unsigned int ctrl_num, int step);
+u32 fsl_ddr_get_intl3r(void);
+void print_ddr_info(unsigned int start_ctrl);
+
+static void __board_assert_mem_reset(void)
+{
+}
+
+static void __board_deassert_mem_reset(void)
+{
+}
+
+void board_assert_mem_reset(void)
+	__attribute__((weak, alias("__board_assert_mem_reset")));
+
+void board_deassert_mem_reset(void)
+	__attribute__((weak, alias("__board_deassert_mem_reset")));
+
+static int __board_need_mem_reset(void)
+{
+	return 0;
+}
+
+int board_need_mem_reset(void)
+	__attribute__((weak, alias("__board_need_mem_reset")));
+
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void);
+bool is_warm_boot(void);
+int fsl_dp_resume(void);
+#endif
+
+/*
+ * The 85xx boards have a common prototype for fixed_sdram so put the
+ * declaration here.
+ */
+#ifdef CONFIG_MPC85xx
+extern phys_size_t fixed_sdram(void);
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+
+typedef struct fixed_ddr_parm{
+	int min_freq;
+	int max_freq;
+	fsl_ddr_cfg_regs_t *ddr_settings;
+} fixed_ddr_parm_t;
+
+/**
+ * fsl_initdram() - Set up the SDRAM
+ *
+ * @return 0 if OK, -ve on error
+ */
+int fsl_initdram(void);
+
+#endif
diff --git a/include/fsl_ddrc_version.h b/include/fsl_ddrc_version.h
new file mode 100644
index 0000000..7c1d041
--- /dev/null
+++ b/include/fsl_ddrc_version.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_DDRC_VER_H
+#define __FSL_DDRC_VER_H
+
+/*
+ * Only the versions with distinct features or registers are listed here.
+ */
+#define FSL_DDR_VER_4_4 44
+#define FSL_DDR_VER_4_6 46
+#define FSL_DDR_VER_4_7	47
+#define FSL_DDR_VER_5_0	50
+
+#endif /* __FSL_DDRC_VER_H */
diff --git a/include/fsl_devdis.h b/include/fsl_devdis.h
new file mode 100644
index 0000000..1f1b033
--- /dev/null
+++ b/include/fsl_devdis.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_DEVDIS_H_
+#define __FSL_DEVDIS_H_
+
+struct devdis_table {
+	char name[32];
+	u32 offset;
+	u32 mask;
+};
+
+void device_disable(const struct devdis_table *tbl, uint32_t num);
+
+#endif
diff --git a/include/fsl_diu_fb.h b/include/fsl_diu_fb.h
new file mode 100644
index 0000000..139851b
--- /dev/null
+++ b/include/fsl_diu_fb.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2007, 2011 Freescale Semiconductor, Inc.
+ * Authors: York Sun <yorksun@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ */
+
+int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix);
+
+/* Prototypes for external board-specific functions */
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port);
+void diu_set_pixel_clock(unsigned int pixclock);
diff --git a/include/fsl_dspi.h b/include/fsl_dspi.h
new file mode 100644
index 0000000..114f63b
--- /dev/null
+++ b/include/fsl_dspi.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale DSPI Module Defines
+ *
+ * Copyright (C) 2004-2007, 2015 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ * Chao Fu (B44548@freesacle.com)
+ * Haikun Wang (B53464@freescale.com)
+ */
+
+#ifndef _FSL_DSPI_H_
+#define _FSL_DSPI_H_
+
+/* DMA Serial Peripheral Interface (DSPI) */
+struct dspi {
+	u32 mcr;	/* 0x00 */
+	u32 resv0;	/* 0x04 */
+	u32 tcr;	/* 0x08 */
+	u32 ctar[8];	/* 0x0C - 0x28 */
+	u32 sr;		/* 0x2C */
+	u32 irsr;	/* 0x30 */
+	u32 tfr;	/* 0x34 - PUSHR */
+	u32 rfr;	/* 0x38 - POPR */
+#ifdef CONFIG_MCF547x_8x
+	u32 tfdr[4];	/* 0x3C */
+	u8 resv2[0x30];	/* 0x40 */
+	u32 rfdr[4];	/* 0x7C */
+#else
+	u32 tfdr[16];	/* 0x3C */
+	u32 rfdr[16];	/* 0x7C */
+#endif
+};
+
+/* Module configuration */
+#define DSPI_MCR_MSTR			0x80000000
+#define DSPI_MCR_CSCK			0x40000000
+#define DSPI_MCR_DCONF(x)		(((x) & 0x03) << 28)
+#define DSPI_MCR_FRZ			0x08000000
+#define DSPI_MCR_MTFE			0x04000000
+#define DSPI_MCR_PCSSE			0x02000000
+#define DSPI_MCR_ROOE			0x01000000
+#define DSPI_MCR_PCSIS(x)		(1 << (16 + (x)))
+#define DSPI_MCR_PCSIS_MASK		(0xff << 16)
+#define DSPI_MCR_CSIS7			0x00800000
+#define DSPI_MCR_CSIS6			0x00400000
+#define DSPI_MCR_CSIS5			0x00200000
+#define DSPI_MCR_CSIS4			0x00100000
+#define DSPI_MCR_CSIS3			0x00080000
+#define DSPI_MCR_CSIS2			0x00040000
+#define DSPI_MCR_CSIS1			0x00020000
+#define DSPI_MCR_CSIS0			0x00010000
+#define DSPI_MCR_DOZE			0x00008000
+#define DSPI_MCR_MDIS			0x00004000
+#define DSPI_MCR_DTXF			0x00002000
+#define DSPI_MCR_DRXF			0x00001000
+#define DSPI_MCR_CTXF			0x00000800
+#define DSPI_MCR_CRXF			0x00000400
+#define DSPI_MCR_SMPL_PT(x)		(((x) & 0x03) << 8)
+#define DSPI_MCR_FCPCS			0x00000001
+#define DSPI_MCR_PES			0x00000001
+#define DSPI_MCR_HALT			0x00000001
+
+/* Transfer count */
+#define DSPI_TCR_SPI_TCNT(x)		(((x) & 0x0000FFFF) << 16)
+
+/* Clock and transfer attributes */
+#define DSPI_CTAR(x)			(0x0c + (x * 4))
+#define DSPI_CTAR_DBR			0x80000000
+#define DSPI_CTAR_TRSZ(x)		(((x) & 0x0F) << 27)
+#define DSPI_CTAR_CPOL			0x04000000
+#define DSPI_CTAR_CPHA			0x02000000
+#define DSPI_CTAR_LSBFE			0x01000000
+#define DSPI_CTAR_PCSSCK(x)		(((x) & 0x03) << 22)
+#define DSPI_CTAR_PCSSCK_7CLK		0x00A00000
+#define DSPI_CTAR_PCSSCK_5CLK		0x00800000
+#define DSPI_CTAR_PCSSCK_3CLK		0x00400000
+#define DSPI_CTAR_PCSSCK_1CLK		0x00000000
+#define DSPI_CTAR_PASC(x)		(((x) & 0x03) << 20)
+#define DSPI_CTAR_PASC_7CLK		0x00300000
+#define DSPI_CTAR_PASC_5CLK		0x00200000
+#define DSPI_CTAR_PASC_3CLK		0x00100000
+#define DSPI_CTAR_PASC_1CLK		0x00000000
+#define DSPI_CTAR_PDT(x)		(((x) & 0x03) << 18)
+#define DSPI_CTAR_PDT_7CLK		0x000A0000
+#define DSPI_CTAR_PDT_5CLK		0x00080000
+#define DSPI_CTAR_PDT_3CLK		0x00040000
+#define DSPI_CTAR_PDT_1CLK		0x00000000
+#define DSPI_CTAR_PBR(x)		(((x) & 0x03) << 16)
+#define DSPI_CTAR_PBR_7CLK		0x00030000
+#define DSPI_CTAR_PBR_5CLK		0x00020000
+#define DSPI_CTAR_PBR_3CLK		0x00010000
+#define DSPI_CTAR_PBR_1CLK		0x00000000
+#define DSPI_CTAR_CSSCK(x)		(((x) & 0x0F) << 12)
+#define DSPI_CTAR_ASC(x)		(((x) & 0x0F) << 8)
+#define DSPI_CTAR_DT(x)			(((x) & 0x0F) << 4)
+#define DSPI_CTAR_BR(x)			((x) & 0x0F)
+
+/* Status */
+#define DSPI_SR_TCF			0x80000000
+#define DSPI_SR_TXRXS			0x40000000
+#define DSPI_SR_EOQF			0x10000000
+#define DSPI_SR_TFUF			0x08000000
+#define DSPI_SR_TFFF			0x02000000
+#define DSPI_SR_RFOF			0x00080000
+#define DSPI_SR_RFDF			0x00020000
+#define DSPI_SR_TXCTR(x)		(((x) & 0x0000F000) >> 12)
+#define DSPI_SR_TXPTR(x)		(((x) & 0x00000F00) >> 8)
+#define DSPI_SR_RXCTR(x)		(((x) & 0x000000F0) >> 4)
+#define DSPI_SR_RXPTR(x)		((x) & 0x0000000F)
+
+/* DMA/interrupt request selct and enable */
+#define DSPI_IRSR_TCFE			0x80000000
+#define DSPI_IRSR_EOQFE			0x10000000
+#define DSPI_IRSR_TFUFE			0x08000000
+#define DSPI_IRSR_TFFFE			0x02000000
+#define DSPI_IRSR_TFFFS			0x01000000
+#define DSPI_IRSR_RFOFE			0x00080000
+#define DSPI_IRSR_RFDFE			0x00020000
+#define DSPI_IRSR_RFDFS			0x00010000
+
+/* Transfer control - 32-bit access */
+#define DSPI_TFR_PCS(x)			(((1 << x) & 0x0000003f) << 16)
+#define DSPI_TFR_CONT			0x80000000
+#define DSPI_TFR_CTAS(x)		(((x) & 0x07) << 28)
+#define DSPI_TFR_EOQ			0x08000000
+#define DSPI_TFR_CTCNT			0x04000000
+#define DSPI_TFR_CS7			0x00800000
+#define DSPI_TFR_CS6			0x00400000
+#define DSPI_TFR_CS5			0x00200000
+#define DSPI_TFR_CS4			0x00100000
+#define DSPI_TFR_CS3			0x00080000
+#define DSPI_TFR_CS2			0x00040000
+#define DSPI_TFR_CS1			0x00020000
+#define DSPI_TFR_CS0			0x00010000
+
+/* Transfer Fifo */
+#define DSPI_TFR_TXDATA(x)		((x) & 0x0000FFFF)
+
+/* Bit definitions and macros for DRFR */
+#define DSPI_RFR_RXDATA(x)		((x) & 0x0000FFFF)
+
+/* Bit definitions and macros for DTFDR group */
+#define DSPI_TFDR_TXDATA(x)		((x) & 0x0000FFFF)
+#define DSPI_TFDR_TXCMD(x)		(((x) & 0x0000FFFF) << 16)
+
+/* Bit definitions and macros for DRFDR group */
+#define DSPI_RFDR_RXDATA(x)		((x) & 0x0000FFFF)
+
+#endif				/* _FSL_DSPI_H_ */
diff --git a/include/fsl_dtsec.h b/include/fsl_dtsec.h
new file mode 100644
index 0000000..ccd6572
--- /dev/null
+++ b/include/fsl_dtsec.h
@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __DTSEC_H__
+#define __DTSEC_H__
+
+#include <asm/types.h>
+
+struct dtsec {
+	u32	tsec_id;	/* controller ID and version */
+	u32	tsec_id2;	/* controller ID and configuration */
+	u32	ievent;		/* interrupt event */
+	u32	imask;		/* interrupt mask */
+	u32	res0;
+	u32	ecntrl;		/* ethernet control and configuration */
+	u32	ptv;		/* pause time value */
+	u32	tbipa;		/* TBI PHY address */
+	u32	res1[8];
+	u32	tctrl;		/* Transmit control register */
+	u32	res2[3];
+	u32	rctrl;		/* Receive control register */
+	u32	res3[11];
+	u32	igaddr[8];	/* Individual group address */
+	u32	gaddr[8];	/* group address */
+	u32	res4[16];
+	u32	maccfg1;	/* MAC configuration register 1 */
+	u32	maccfg2;	/* MAC configuration register 2 */
+	u32	ipgifg;		/* inter-packet/inter-frame gap */
+	u32	hafdup;		/* half-duplex control */
+	u32	maxfrm;		/* Maximum frame size */
+	u32	res5[3];
+	u32	miimcfg;	/* MII management configuration */
+	u32	miimcom;	/* MII management command */
+	u32	miimadd;	/* MII management address */
+	u32	miimcon;	/* MII management control */
+	u32	miimstat;	/* MII management status */
+	u32	miimind;	/* MII management indicator */
+	u32	res6;
+	u32	ifstat;		/* Interface status */
+	u32	macstnaddr1;	/* MAC station address 1 */
+	u32	macstnaddr2;	/* MAC station address 2 */
+	u32	res7[46];
+	/* transmit and receive counter */
+	u32	tr64;		/* Tx and Rx 64 bytes frame */
+	u32	tr127;		/* Tx and Rx 65 to 127 bytes frame */
+	u32	tr255;		/* Tx and Rx 128 to 255 bytes frame */
+	u32	tr511;		/* Tx and Rx 256 to 511 bytes frame */
+	u32	tr1k;		/* Tx and Rx 512 to 1023 bytes frame */
+	u32	trmax;		/* Tx and Rx 1024 to 1518 bytes frame */
+	u32	trmgv;		/* Tx and Rx 1519 to 1522 good VLAN frame */
+	/* receive counters */
+	u32	rbyt;		/* Receive byte counter */
+	u32	rpkt;		/* Receive packet counter */
+	u32	rfcs;		/* Receive FCS error */
+	u32	rmca;		/* Receive multicast packet */
+	u32	rbca;		/* Receive broadcast packet */
+	u32	rxcf;		/* Receive control frame */
+	u32	rxpf;		/* Receive pause frame */
+	u32	rxuo;		/* Receive unknown OP code */
+	u32	raln;		/* Receive alignment error */
+	u32	rflr;		/* Receive frame length error */
+	u32	rcde;		/* Receive code error */
+	u32	rcse;		/* Receive carrier sense error */
+	u32	rund;		/* Receive undersize packet */
+	u32	rovr;		/* Receive oversize packet */
+	u32	rfrg;		/* Receive fragments counter */
+	u32	rjbr;		/* Receive jabber counter */
+	u32	rdrp;		/* Receive drop counter */
+	/* transmit counters */
+	u32	tbyt;		/* Transmit byte counter */
+	u32	tpkt;		/* Transmit packet */
+	u32	tmca;		/* Transmit multicast packet */
+	u32	tbca;		/* Transmit broadcast packet */
+	u32	txpf;		/* Transmit pause control frame */
+	u32	tdfr;		/* Transmit deferral packet */
+	u32	tedf;		/* Transmit excessive deferral pkt */
+	u32	tscl;		/* Transmit single collision pkt */
+	u32	tmcl;		/* Transmit multiple collision pkt */
+	u32	tlcl;		/* Transmit late collision pkt */
+	u32	txcl;		/* Transmit excessive collision */
+	u32	tncl;		/* Transmit total collision */
+	u32	res8;
+	u32	tdrp;		/* Transmit drop frame */
+	u32	tjbr;		/* Transmit jabber frame */
+	u32	tfcs;		/* Transmit FCS error */
+	u32	txcf;		/* Transmit control frame */
+	u32	tovr;		/* Transmit oversize frame */
+	u32	tund;		/* Transmit undersize frame */
+	u32	tfrg;		/* Transmit fragments frame */
+	/* counter controls */
+	u32	car1;		/* carry register 1 */
+	u32	car2;		/* carry register 2 */
+	u32	cam1;		/* carry register 1 mask */
+	u32	cam2;		/* carry register 2 mask */
+	u32	res9[80];
+};
+
+
+/* TBI register addresses */
+#define TBI_CR			0x00
+#define TBI_SR			0x01
+#define TBI_ANA			0x04
+#define TBI_ANLPBPA		0x05
+#define TBI_ANEX		0x06
+#define TBI_TBICON		0x11
+
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT	0x0020
+#define TBIANA_ASYMMETRIC_PAUSE 0x0100
+#define TBIANA_SYMMETRIC_PAUSE  0x0080
+#define TBIANA_HALF_DUPLEX	0x0040
+#define TBIANA_FULL_DUPLEX	0x0020
+#define TBICR_PHY_RESET		0x8000
+#define TBICR_ANEG_ENABLE	0x1000
+#define TBICR_RESTART_ANEG	0x0200
+#define TBICR_FULL_DUPLEX	0x0100
+#define TBICR_SPEED1_SET	0x0040
+
+/* IEVENT - interrupt events register */
+#define IEVENT_BABR	0x80000000 /* Babbling receive error */
+#define IEVENT_RXC	0x40000000 /* pause control frame received */
+#define IEVENT_MSRO	0x04000000 /* MIB counter overflow */
+#define IEVENT_GTSC	0x02000000 /* Graceful transmit stop complete */
+#define IEVENT_BABT	0x01000000 /* Babbling transmit error */
+#define IEVENT_TXC	0x00800000 /* control frame transmitted */
+#define IEVENT_TXE	0x00400000 /* Transmit channel error */
+#define IEVENT_LC	0x00040000 /* Late collision occurred */
+#define IEVENT_CRL	0x00020000 /* Collision retry exceed limit */
+#define IEVENT_XFUN	0x00010000 /* Transmit FIFO underrun */
+#define IEVENT_ABRT	0x00008000 /* Transmit packet abort */
+#define IEVENT_MMRD	0x00000400 /* MII management read complete */
+#define IEVENT_MMWR	0x00000200 /* MII management write complete */
+#define IEVENT_GRSC	0x00000100 /* Graceful stop complete */
+#define IEVENT_TDPE	0x00000002 /* Internal data parity error on Tx */
+#define IEVENT_RDPE	0x00000001 /* Internal data parity error on Rx */
+
+#define IEVENT_CLEAR_ALL	0xffffffff
+
+/* IMASK - interrupt mask register */
+#define IMASK_BREN	0x80000000 /* Babbling receive enable */
+#define IMASK_RXCEN	0x40000000 /* receive control enable */
+#define IMASK_MSROEN	0x04000000 /* MIB counter overflow enable */
+#define IMASK_GTSCEN	0x02000000 /* Graceful Tx stop complete enable */
+#define IMASK_BTEN	0x01000000 /* Babbling transmit error enable */
+#define IMASK_TXCEN	0x00800000 /* control frame transmitted enable */
+#define IMASK_TXEEN	0x00400000 /* Transmit channel error enable */
+#define IMASK_LCEN	0x00040000 /* Late collision interrupt enable */
+#define IMASK_CRLEN	0x00020000 /* Collision retry exceed limit */
+#define IMASK_XFUNEN	0x00010000 /* Transmit FIFO underrun enable */
+#define IMASK_ABRTEN	0x00008000 /* Transmit packet abort enable */
+#define IMASK_MMRDEN	0x00000400 /* MII management read complete enable */
+#define IMASK_MMWREN	0x00000200 /* MII management write complete enable */
+#define IMASK_GRSCEN	0x00000100 /* Graceful stop complete interrupt enable */
+#define IMASK_TDPEEN	0x00000002 /* Internal data parity error on Tx enable */
+#define IMASK_RDPEEN	0x00000001 /* Internal data parity error on Rx enable */
+
+#define IMASK_MASK_ALL	0x00000000
+
+/* ECNTRL - ethernet control register */
+#define ECNTRL_CFG_RO	0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */
+#define ECNTRL_CLRCNT	0x00004000 /* clear all statistics */
+#define ECNTRL_AUTOZ	0x00002000 /* auto zero MIB counter */
+#define ECNTRL_STEN	0x00001000 /* enable internal counters to update */
+#define ECNTRL_GMIIM	0x00000040 /* 1- GMII or RGMII interface mode */
+#define ECNTRL_TBIM	0x00000020 /* 1- Ten-bit interface mode */
+#define ECNTRL_RPM	0x00000010 /* 1- RGMII reduced-pin mode */
+#define ECNTRL_R100M	0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
+				      0- RGMII 10 Mbps, SGMII 10 Mbps */
+#define ECNTRL_SGMIIM	0x00000002 /* 1- SGMII interface mode */
+#define ECNTRL_TBIM	0x00000020 /* 1- TBI Interface mode (for SGMII) */
+
+#define ECNTRL_DEFAULT	(ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM)
+
+/* TCTRL - Transmit control register */
+#define TCTRL_THDF	0x00000800 /* Transmit half-duplex flow control */
+#define TCTRL_TTSE	0x00000040 /* Transmit time-stamp enable */
+#define TCTRL_GTS	0x00000020 /* Graceful transmit stop */
+#define TCTRL_RFC_PAUSE	0x00000010 /* Receive flow control pause frame */
+
+/* RCTRL - Receive control register */
+#define RCTRL_PAL_MASK	0x001f0000 /* packet alignment padding length */
+#define RCTRL_PAL_SHIFT	16
+#define RCTRL_CFA	0x00008000 /* control frame accept enable */
+#define RCTRL_GHTX	0x00000800 /* group address hash table extend */
+#define RCTRL_RTSE	0x00000040 /* receive 1588 time-stamp enable */
+#define RCTRL_GRS	0x00000020 /* graceful receive stop */
+#define RCTRL_BC_REJ	0x00000010 /* broadcast frame reject */
+#define RCTRL_BC_MPROM	0x00000008 /* all multicast/broadcast frames received */
+#define RCTRL_RSF	0x00000004 /* receive short frame(17~63 bytes) enable */
+#define RCTRL_EMEN	0x00000002 /* Exact match MAC address enable */
+#define RCTRL_UPROM	0x00000001 /* all unicast frame received */
+
+/* MACCFG1 - MAC configuration 1 register */
+#define MACCFG1_SOFT_RST	0x80000000 /* place the MAC in reset */
+#define MACCFG1_RST_RXMAC	0x00080000 /* reset receive MAC control block */
+#define MACCFG1_RST_TXMAC	0x00040000 /* reet transmit MAC control block */
+#define MACCFG1_RST_RXFUN	0x00020000 /* reset receive function block */
+#define MACCFG1_RST_TXFUN	0x00010000 /* reset transmit function block */
+#define MACCFG1_LOOPBACK	0x00000100 /* MAC loopback */
+#define MACCFG1_RX_FLOW		0x00000020 /* Receive flow */
+#define MACCFG1_TX_FLOW		0x00000010 /* Transmit flow */
+#define MACCFG1_SYNC_RXEN	0x00000008 /* Frame reception enabled */
+#define MACCFG1_RX_EN		0x00000004 /* Rx enable */
+#define MACCFG1_SYNC_TXEN	0x00000002 /* Frame transmission is enabled */
+#define MACCFG1_TX_EN		0x00000001 /* Tx enable */
+#define MACCFG1_RXTX_EN		(MACCFG1_RX_EN | MACCFG1_TX_EN)
+
+/* MACCFG2 - MAC configuration 2 register */
+#define MACCFG2_PRE_LEN_MASK	0x0000f000 /* preamble length */
+#define MACCFG2_PRE_LEN(x)	((x << 12) & MACCFG2_PRE_LEN_MASK)
+#define MACCFG2_IF_MODE_MASK	0x00000300
+#define MACCFG2_IF_MODE_NIBBLE	0x00000100 /* MII, 10/100 Mbps MII/RMII */
+#define MACCFG2_IF_MODE_BYTE	0x00000200 /* GMII/TBI, 1000 GMII/TBI */
+#define MACCFG2_PRE_RX_EN	0x00000080 /* receive preamble enable */
+#define MACCFG2_PRE_TX_EN	0x00000040 /* tx preable enable */
+#define MACCFG2_HUGE_FRAME	0x00000020 /* >= max frame len enable */
+#define MACCFG2_LEN_CHECK	0x00000010 /* MAC check frame's length Rx */
+#define MACCFG2_MAG_EN		0x00000008 /* magic packet enable */
+#define MACCFG2_PAD_CRC		0x00000004 /* pad and append CRC */
+#define MACCFG2_CRC_EN		0x00000002 /* MAC appends a CRC on all frames */
+#define MACCFG2_FULL_DUPLEX	0x00000001 /* Full deplex mode */
+
+struct fsl_enet_mac;
+
+void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs,
+		int max_rx_len);
+
+#endif
diff --git a/include/fsl_errata.h b/include/fsl_errata.h
new file mode 100644
index 0000000..88f4268
--- /dev/null
+++ b/include/fsl_errata.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013 - 2015  Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_ERRATA_H
+#define _FSL_ERRATA_H
+
+#include <common.h>
+#if defined(CONFIG_PPC)
+#include <asm/processor.h>
+#elif defined(CONFIG_ARCH_LS1021A)
+#include <asm/arch-ls102xa/immap_ls102xa.h>
+#elif defined(CONFIG_FSL_LAYERSCAPE)
+#include <asm/arch/soc.h>
+#endif
+
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
+static inline bool has_erratum_a006379(void)
+{
+	u32 svr = get_svr();
+	if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
+	    ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
+	    ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) ||
+	    ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
+	    ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
+	    ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
+	    ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1))
+		return true;
+
+	return false;
+}
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+static inline bool has_erratum_a007186(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+	case SVR_T4240:
+		return IS_SVR_REV(svr, 2, 0);
+	case SVR_T4160:
+		return IS_SVR_REV(svr, 2, 0);
+	case SVR_B4860:
+		return IS_SVR_REV(svr, 2, 0);
+	case SVR_B4420:
+		return IS_SVR_REV(svr, 2, 0);
+	case SVR_T2081:
+	case SVR_T2080:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+	}
+
+	return false;
+}
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
+static inline bool has_erratum_a008378(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+
+	switch (soc) {
+#ifdef CONFIG_ARCH_LS1021A
+	case SOC_VER_LS1020:
+	case SOC_VER_LS1021:
+	case SOC_VER_LS1022:
+	case SOC_VER_SLS1020:
+		return IS_SVR_REV(svr, 1, 0);
+#endif
+#ifdef CONFIG_PPC
+	case SVR_T1023:
+	case SVR_T1024:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_T1020:
+	case SVR_T1022:
+	case SVR_T1040:
+	case SVR_T1042:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+	default:
+		return false;
+	}
+}
+#endif
+
+#endif /*  _FSL_ERRATA_H */
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
new file mode 100644
index 0000000..33dcbee
--- /dev/null
+++ b/include/fsl_esdhc.h
@@ -0,0 +1,219 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * FSL SD/MMC Defines
+ *-------------------------------------------------------------------
+ *
+ * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
+ */
+
+#ifndef  __FSL_ESDHC_H__
+#define	__FSL_ESDHC_H__
+
+#include <linux/errno.h>
+#include <asm/byteorder.h>
+
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
+#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+#include "../board/freescale/common/qixis.h"
+#endif
+
+/* FSL eSDHC-specific constants */
+#define SYSCTL			0x0002e02c
+#define SYSCTL_INITA		0x08000000
+#define SYSCTL_TIMEOUT_MASK	0x000f0000
+#define SYSCTL_CLOCK_MASK	0x0000fff0
+#define SYSCTL_CKEN		0x00000008
+#define SYSCTL_PEREN		0x00000004
+#define SYSCTL_HCKEN		0x00000002
+#define SYSCTL_IPGEN		0x00000001
+#define SYSCTL_RSTA		0x01000000
+#define SYSCTL_RSTC		0x02000000
+#define SYSCTL_RSTD		0x04000000
+
+#define IRQSTAT			0x0002e030
+#define IRQSTAT_DMAE		(0x10000000)
+#define IRQSTAT_AC12E		(0x01000000)
+#define IRQSTAT_DEBE		(0x00400000)
+#define IRQSTAT_DCE		(0x00200000)
+#define IRQSTAT_DTOE		(0x00100000)
+#define IRQSTAT_CIE		(0x00080000)
+#define IRQSTAT_CEBE		(0x00040000)
+#define IRQSTAT_CCE		(0x00020000)
+#define IRQSTAT_CTOE		(0x00010000)
+#define IRQSTAT_CINT		(0x00000100)
+#define IRQSTAT_CRM		(0x00000080)
+#define IRQSTAT_CINS		(0x00000040)
+#define IRQSTAT_BRR		(0x00000020)
+#define IRQSTAT_BWR		(0x00000010)
+#define IRQSTAT_DINT		(0x00000008)
+#define IRQSTAT_BGE		(0x00000004)
+#define IRQSTAT_TC		(0x00000002)
+#define IRQSTAT_CC		(0x00000001)
+
+#define CMD_ERR		(IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
+#define DATA_ERR	(IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
+				IRQSTAT_DMAE)
+#define DATA_COMPLETE	(IRQSTAT_TC | IRQSTAT_DINT)
+
+#define IRQSTATEN		0x0002e034
+#define IRQSTATEN_DMAE		(0x10000000)
+#define IRQSTATEN_AC12E		(0x01000000)
+#define IRQSTATEN_DEBE		(0x00400000)
+#define IRQSTATEN_DCE		(0x00200000)
+#define IRQSTATEN_DTOE		(0x00100000)
+#define IRQSTATEN_CIE		(0x00080000)
+#define IRQSTATEN_CEBE		(0x00040000)
+#define IRQSTATEN_CCE		(0x00020000)
+#define IRQSTATEN_CTOE		(0x00010000)
+#define IRQSTATEN_CINT		(0x00000100)
+#define IRQSTATEN_CRM		(0x00000080)
+#define IRQSTATEN_CINS		(0x00000040)
+#define IRQSTATEN_BRR		(0x00000020)
+#define IRQSTATEN_BWR		(0x00000010)
+#define IRQSTATEN_DINT		(0x00000008)
+#define IRQSTATEN_BGE		(0x00000004)
+#define IRQSTATEN_TC		(0x00000002)
+#define IRQSTATEN_CC		(0x00000001)
+
+#define ESDHCCTL		0x0002e40c
+#define ESDHCCTL_PCS		(0x00080000)
+
+#define PRSSTAT			0x0002e024
+#define PRSSTAT_DAT0		(0x01000000)
+#define PRSSTAT_CLSL		(0x00800000)
+#define PRSSTAT_WPSPL		(0x00080000)
+#define PRSSTAT_CDPL		(0x00040000)
+#define PRSSTAT_CINS		(0x00010000)
+#define PRSSTAT_BREN		(0x00000800)
+#define PRSSTAT_BWEN		(0x00000400)
+#define PRSSTAT_SDSTB		(0X00000008)
+#define PRSSTAT_DLA		(0x00000004)
+#define PRSSTAT_CICHB		(0x00000002)
+#define PRSSTAT_CIDHB		(0x00000001)
+
+#define PROCTL			0x0002e028
+#define PROCTL_INIT		0x00000020
+#define PROCTL_DTW_4		0x00000002
+#define PROCTL_DTW_8		0x00000004
+#define PROCTL_D3CD		0x00000008
+
+#define CMDARG			0x0002e008
+
+#define XFERTYP			0x0002e00c
+#define XFERTYP_CMD(x)		((x & 0x3f) << 24)
+#define XFERTYP_CMDTYP_NORMAL	0x0
+#define XFERTYP_CMDTYP_SUSPEND	0x00400000
+#define XFERTYP_CMDTYP_RESUME	0x00800000
+#define XFERTYP_CMDTYP_ABORT	0x00c00000
+#define XFERTYP_DPSEL		0x00200000
+#define XFERTYP_CICEN		0x00100000
+#define XFERTYP_CCCEN		0x00080000
+#define XFERTYP_RSPTYP_NONE	0
+#define XFERTYP_RSPTYP_136	0x00010000
+#define XFERTYP_RSPTYP_48	0x00020000
+#define XFERTYP_RSPTYP_48_BUSY	0x00030000
+#define XFERTYP_MSBSEL		0x00000020
+#define XFERTYP_DTDSEL		0x00000010
+#define XFERTYP_DDREN		0x00000008
+#define XFERTYP_AC12EN		0x00000004
+#define XFERTYP_BCEN		0x00000002
+#define XFERTYP_DMAEN		0x00000001
+
+#define CINS_TIMEOUT		1000
+#define PIO_TIMEOUT		500
+
+#define DSADDR		0x2e004
+
+#define CMDRSP0		0x2e010
+#define CMDRSP1		0x2e014
+#define CMDRSP2		0x2e018
+#define CMDRSP3		0x2e01c
+
+#define DATPORT		0x2e020
+
+#define WML		0x2e044
+#define WML_WRITE	0x00010000
+#ifdef CONFIG_FSL_SDHC_V2_3
+#define WML_RD_WML_MAX		0x80
+#define WML_WR_WML_MAX		0x80
+#define WML_RD_WML_MAX_VAL	0x0
+#define WML_WR_WML_MAX_VAL	0x0
+#define WML_RD_WML_MASK		0x7f
+#define WML_WR_WML_MASK		0x7f0000
+#else
+#define WML_RD_WML_MAX		0x10
+#define WML_WR_WML_MAX		0x80
+#define WML_RD_WML_MAX_VAL	0x10
+#define WML_WR_WML_MAX_VAL	0x80
+#define WML_RD_WML_MASK	0xff
+#define WML_WR_WML_MASK	0xff0000
+#endif
+
+#define BLKATTR		0x2e004
+#define BLKATTR_CNT(x)	((x & 0xffff) << 16)
+#define BLKATTR_SIZE(x)	(x & 0x1fff)
+#define MAX_BLK_CNT	0x7fff	/* so malloc will have enough room with 32M */
+
+#define ESDHC_HOSTCAPBLT_VS18	0x04000000
+#define ESDHC_HOSTCAPBLT_VS30	0x02000000
+#define ESDHC_HOSTCAPBLT_VS33	0x01000000
+#define ESDHC_HOSTCAPBLT_SRS	0x00800000
+#define ESDHC_HOSTCAPBLT_DMAS	0x00400000
+#define ESDHC_HOSTCAPBLT_HSS	0x00200000
+
+struct fsl_esdhc_cfg {
+	phys_addr_t esdhc_base;
+	u32	sdhc_clk;
+	u8	max_bus_width;
+	int	wp_enable;
+	int	vs18_enable; /* Use 1.8V if set to 1 */
+	struct mmc_config cfg;
+};
+
+/* Select the correct accessors depending on endianess */
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32		in_le32
+#define esdhc_write32		out_le32
+#define esdhc_clrsetbits32	clrsetbits_le32
+#define esdhc_clrbits32		clrbits_le32
+#define esdhc_setbits32		setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32            in_be32
+#define esdhc_write32           out_be32
+#define esdhc_clrsetbits32      clrsetbits_be32
+#define esdhc_clrbits32         clrbits_be32
+#define esdhc_setbits32         setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
+#define esdhc_read32		in_le32
+#define esdhc_write32		out_le32
+#define esdhc_clrsetbits32	clrsetbits_le32
+#define esdhc_clrbits32		clrbits_le32
+#define esdhc_setbits32		setbits_le32
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define esdhc_read32		in_be32
+#define esdhc_write32		out_be32
+#define esdhc_clrsetbits32	clrsetbits_be32
+#define esdhc_clrbits32		clrbits_be32
+#define esdhc_setbits32		setbits_be32
+#else
+#error "Endianess is not defined: please fix to continue"
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+int fsl_esdhc_mmc_init(bd_t *bis);
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
+void fdt_fixup_esdhc(void *blob, bd_t *bd);
+#ifdef MMC_SUPPORTS_TUNING
+static inline int fsl_esdhc_execute_tuning(struct udevice *dev,
+					   uint32_t opcode) {return 0; }
+#endif
+#else
+static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
+static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif /* CONFIG_FSL_ESDHC */
+void __noreturn mmc_boot(void);
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
+
+#endif  /* __FSL_ESDHC_H__ */
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
new file mode 100644
index 0000000..33c6d52
--- /dev/null
+++ b/include/fsl_esdhc_imx.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * FSL SD/MMC Defines
+ *-------------------------------------------------------------------
+ *
+ * Copyright 2019 NXP
+ * Yangbo Lu <yangbo.lu@nxp.com>
+ *
+ * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
+ */
+
+#ifndef __FSL_ESDHC_IMX_H__
+#define __FSL_ESDHC_IMX_H__
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/byteorder.h>
+
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
+/* FSL eSDHC-specific constants */
+#define SYSCTL			0x0002e02c
+#define SYSCTL_INITA		0x08000000
+#define SYSCTL_TIMEOUT_MASK	0x000f0000
+#define SYSCTL_CLOCK_MASK	0x0000fff0
+#if !defined(CONFIG_FSL_USDHC)
+#define SYSCTL_CKEN		0x00000008
+#define SYSCTL_PEREN		0x00000004
+#define SYSCTL_HCKEN		0x00000002
+#define SYSCTL_IPGEN		0x00000001
+#endif
+#define SYSCTL_RSTA		0x01000000
+#define SYSCTL_RSTC		0x02000000
+#define SYSCTL_RSTD		0x04000000
+
+#define VENDORSPEC_CKEN		0x00004000
+#define VENDORSPEC_PEREN	0x00002000
+#define VENDORSPEC_HCKEN	0x00001000
+#define VENDORSPEC_IPGEN	0x00000800
+#define VENDORSPEC_INIT		0x20007809
+
+#define IRQSTAT			0x0002e030
+#define IRQSTAT_DMAE		(0x10000000)
+#define IRQSTAT_AC12E		(0x01000000)
+#define IRQSTAT_DEBE		(0x00400000)
+#define IRQSTAT_DCE		(0x00200000)
+#define IRQSTAT_DTOE		(0x00100000)
+#define IRQSTAT_CIE		(0x00080000)
+#define IRQSTAT_CEBE		(0x00040000)
+#define IRQSTAT_CCE		(0x00020000)
+#define IRQSTAT_CTOE		(0x00010000)
+#define IRQSTAT_CINT		(0x00000100)
+#define IRQSTAT_CRM		(0x00000080)
+#define IRQSTAT_CINS		(0x00000040)
+#define IRQSTAT_BRR		(0x00000020)
+#define IRQSTAT_BWR		(0x00000010)
+#define IRQSTAT_DINT		(0x00000008)
+#define IRQSTAT_BGE		(0x00000004)
+#define IRQSTAT_TC		(0x00000002)
+#define IRQSTAT_CC		(0x00000001)
+
+#define CMD_ERR		(IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
+#define DATA_ERR	(IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
+				IRQSTAT_DMAE)
+#define DATA_COMPLETE	(IRQSTAT_TC | IRQSTAT_DINT)
+
+#define IRQSTATEN		0x0002e034
+#define IRQSTATEN_DMAE		(0x10000000)
+#define IRQSTATEN_AC12E		(0x01000000)
+#define IRQSTATEN_DEBE		(0x00400000)
+#define IRQSTATEN_DCE		(0x00200000)
+#define IRQSTATEN_DTOE		(0x00100000)
+#define IRQSTATEN_CIE		(0x00080000)
+#define IRQSTATEN_CEBE		(0x00040000)
+#define IRQSTATEN_CCE		(0x00020000)
+#define IRQSTATEN_CTOE		(0x00010000)
+#define IRQSTATEN_CINT		(0x00000100)
+#define IRQSTATEN_CRM		(0x00000080)
+#define IRQSTATEN_CINS		(0x00000040)
+#define IRQSTATEN_BRR		(0x00000020)
+#define IRQSTATEN_BWR		(0x00000010)
+#define IRQSTATEN_DINT		(0x00000008)
+#define IRQSTATEN_BGE		(0x00000004)
+#define IRQSTATEN_TC		(0x00000002)
+#define IRQSTATEN_CC		(0x00000001)
+
+#define ESDHCCTL		0x0002e40c
+#define ESDHCCTL_PCS		(0x00080000)
+
+#define PRSSTAT			0x0002e024
+#define PRSSTAT_DAT0		(0x01000000)
+#define PRSSTAT_CLSL		(0x00800000)
+#define PRSSTAT_WPSPL		(0x00080000)
+#define PRSSTAT_CDPL		(0x00040000)
+#define PRSSTAT_CINS		(0x00010000)
+#define PRSSTAT_BREN		(0x00000800)
+#define PRSSTAT_BWEN		(0x00000400)
+#define PRSSTAT_SDSTB		(0X00000008)
+#define PRSSTAT_DLA		(0x00000004)
+#define PRSSTAT_CICHB		(0x00000002)
+#define PRSSTAT_CIDHB		(0x00000001)
+
+#define PROCTL			0x0002e028
+#define PROCTL_INIT		0x00000020
+#define PROCTL_DTW_4		0x00000002
+#define PROCTL_DTW_8		0x00000004
+#define PROCTL_D3CD		0x00000008
+
+#define CMDARG			0x0002e008
+
+#define XFERTYP			0x0002e00c
+#define XFERTYP_CMD(x)		((x & 0x3f) << 24)
+#define XFERTYP_CMDTYP_NORMAL	0x0
+#define XFERTYP_CMDTYP_SUSPEND	0x00400000
+#define XFERTYP_CMDTYP_RESUME	0x00800000
+#define XFERTYP_CMDTYP_ABORT	0x00c00000
+#define XFERTYP_DPSEL		0x00200000
+#define XFERTYP_CICEN		0x00100000
+#define XFERTYP_CCCEN		0x00080000
+#define XFERTYP_RSPTYP_NONE	0
+#define XFERTYP_RSPTYP_136	0x00010000
+#define XFERTYP_RSPTYP_48	0x00020000
+#define XFERTYP_RSPTYP_48_BUSY	0x00030000
+#define XFERTYP_MSBSEL		0x00000020
+#define XFERTYP_DTDSEL		0x00000010
+#define XFERTYP_DDREN		0x00000008
+#define XFERTYP_AC12EN		0x00000004
+#define XFERTYP_BCEN		0x00000002
+#define XFERTYP_DMAEN		0x00000001
+
+#define CINS_TIMEOUT		1000
+#define PIO_TIMEOUT		500
+
+#define DSADDR		0x2e004
+
+#define CMDRSP0		0x2e010
+#define CMDRSP1		0x2e014
+#define CMDRSP2		0x2e018
+#define CMDRSP3		0x2e01c
+
+#define DATPORT		0x2e020
+
+#define WML		0x2e044
+#define WML_WRITE	0x00010000
+#ifdef CONFIG_FSL_SDHC_V2_3
+#define WML_RD_WML_MAX		0x80
+#define WML_WR_WML_MAX		0x80
+#define WML_RD_WML_MAX_VAL	0x0
+#define WML_WR_WML_MAX_VAL	0x0
+#define WML_RD_WML_MASK		0x7f
+#define WML_WR_WML_MASK		0x7f0000
+#else
+#define WML_RD_WML_MAX		0x10
+#define WML_WR_WML_MAX		0x80
+#define WML_RD_WML_MAX_VAL	0x10
+#define WML_WR_WML_MAX_VAL	0x80
+#define WML_RD_WML_MASK	0xff
+#define WML_WR_WML_MASK	0xff0000
+#endif
+
+#define BLKATTR		0x2e004
+#define BLKATTR_CNT(x)	((x & 0xffff) << 16)
+#define BLKATTR_SIZE(x)	(x & 0x1fff)
+#define MAX_BLK_CNT	0x7fff	/* so malloc will have enough room with 32M */
+
+#define ESDHC_HOSTCAPBLT_VS18	0x04000000
+#define ESDHC_HOSTCAPBLT_VS30	0x02000000
+#define ESDHC_HOSTCAPBLT_VS33	0x01000000
+#define ESDHC_HOSTCAPBLT_SRS	0x00800000
+#define ESDHC_HOSTCAPBLT_DMAS	0x00400000
+#define ESDHC_HOSTCAPBLT_HSS	0x00200000
+
+#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
+
+/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
+#define	MIX_CTRL_DDREN		BIT(3)
+#define MIX_CTRL_DTDSEL_READ	BIT(4)
+#define	MIX_CTRL_AC23EN		BIT(7)
+#define	MIX_CTRL_EXE_TUNE	BIT(22)
+#define	MIX_CTRL_SMPCLK_SEL	BIT(23)
+#define	MIX_CTRL_AUTO_TUNE_EN	BIT(24)
+#define	MIX_CTRL_FBCLK_SEL	BIT(25)
+#define	MIX_CTRL_HS400_EN	BIT(26)
+#define	MIX_CTRL_HS400_ES	BIT(27)
+/* Bits 3 and 6 are not SDHCI standard definitions */
+#define	MIX_CTRL_SDHCI_MASK	0xb7
+/* Tuning bits */
+#define	MIX_CTRL_TUNING_MASK	0x03c00000
+
+/* strobe dll register */
+#define ESDHC_STROBE_DLL_CTRL		0x70
+#define ESDHC_STROBE_DLL_CTRL_ENABLE	BIT(0)
+#define ESDHC_STROBE_DLL_CTRL_RESET	BIT(1)
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT	0x7
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT	3
+
+#define ESDHC_STROBE_DLL_STATUS		0x74
+#define ESDHC_STROBE_DLL_STS_REF_LOCK	BIT(1)
+#define ESDHC_STROBE_DLL_STS_SLV_LOCK	0x1
+#define ESDHC_STROBE_DLL_CLK_FREQ	100000000
+
+#define ESDHC_STD_TUNING_EN             BIT(24)
+/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
+#define ESDHC_TUNING_START_TAP_DEFAULT	0x1
+#define ESDHC_TUNING_START_TAP_MASK	0xff
+#define ESDHC_TUNING_STEP_MASK		0x00070000
+#define ESDHC_TUNING_STEP_SHIFT		16
+
+#define	ESDHC_FLAG_MULTIBLK_NO_INT	BIT(1)
+#define	ESDHC_FLAG_ENGCM07207		BIT(2)
+#define	ESDHC_FLAG_USDHC		BIT(3)
+#define	ESDHC_FLAG_MAN_TUNING		BIT(4)
+#define	ESDHC_FLAG_STD_TUNING		BIT(5)
+#define	ESDHC_FLAG_HAVE_CAP1		BIT(6)
+#define	ESDHC_FLAG_ERR004536		BIT(7)
+#define	ESDHC_FLAG_HS200		BIT(8)
+#define	ESDHC_FLAG_HS400		BIT(9)
+#define	ESDHC_FLAG_ERR010450		BIT(10)
+#define	ESDHC_FLAG_HS400_ES		BIT(11)
+
+struct fsl_esdhc_cfg {
+	phys_addr_t esdhc_base;
+	u32	sdhc_clk;
+	u8	max_bus_width;
+	int	wp_enable;
+	int	vs18_enable; /* Use 1.8V if set to 1 */
+	struct mmc_config cfg;
+};
+
+/* Select the correct accessors depending on endianess */
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32		in_le32
+#define esdhc_write32		out_le32
+#define esdhc_clrsetbits32	clrsetbits_le32
+#define esdhc_clrbits32		clrbits_le32
+#define esdhc_setbits32		setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32            in_be32
+#define esdhc_write32           out_be32
+#define esdhc_clrsetbits32      clrsetbits_be32
+#define esdhc_clrbits32         clrbits_be32
+#define esdhc_setbits32         setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
+#define esdhc_read32		in_le32
+#define esdhc_write32		out_le32
+#define esdhc_clrsetbits32	clrsetbits_le32
+#define esdhc_clrbits32		clrbits_le32
+#define esdhc_setbits32		setbits_le32
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define esdhc_read32		in_be32
+#define esdhc_write32		out_be32
+#define esdhc_clrsetbits32	clrsetbits_be32
+#define esdhc_clrbits32		clrbits_be32
+#define esdhc_setbits32		setbits_be32
+#else
+#error "Endianess is not defined: please fix to continue"
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+int fsl_esdhc_mmc_init(bd_t *bis);
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
+void fdt_fixup_esdhc(void *blob, bd_t *bd);
+#else
+static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
+static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif /* CONFIG_FSL_ESDHC_IMX */
+void __noreturn mmc_boot(void);
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
+
+#endif  /* __FSL_ESDHC_IMX_H__ */
diff --git a/include/fsl_fman.h b/include/fsl_fman.h
new file mode 100644
index 0000000..74acdb2
--- /dev/null
+++ b/include/fsl_fman.h
@@ -0,0 +1,463 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MPC85xx Internal Memory Map
+ *
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_FMAN_H__
+#define __FSL_FMAN_H__
+
+#include <asm/types.h>
+
+typedef struct fm_bmi_common {
+	u32	fmbm_init;	/* BMI initialization */
+	u32	fmbm_cfg1;	/* BMI configuration1 */
+	u32	fmbm_cfg2;	/* BMI configuration2 */
+	u32	res0[0x5];
+	u32	fmbm_ievr;	/* interrupt event register */
+	u32	fmbm_ier;	/* interrupt enable register */
+	u32	fmbm_ifr;	/* interrupt force register */
+	u32	res1[0x5];
+	u32	fmbm_arb[0x8];	/* BMI arbitration */
+	u32	res2[0x28];
+	u32	fmbm_gde;	/* global debug enable */
+	u32	fmbm_pp[0x3f];	/* BMI port parameters */
+	u32	res3;
+	u32	fmbm_pfs[0x3f];	/* BMI port FIFO size */
+	u32	res4;
+	u32	fmbm_ppid[0x3f];/* port partition ID */
+} fm_bmi_common_t;
+
+typedef struct fm_qmi_common {
+	u32	fmqm_gc;	/* general configuration register */
+	u32	res0;
+	u32	fmqm_eie;	/* error interrupt event register */
+	u32	fmqm_eien;	/* error interrupt enable register */
+	u32	fmqm_eif;	/* error interrupt force register */
+	u32	fmqm_ie;	/* interrupt event register */
+	u32	fmqm_ien;	/* interrupt enable register */
+	u32	fmqm_if;	/* interrupt force register */
+	u32	fmqm_gs;	/* global status register */
+	u32	fmqm_ts;	/* task status register */
+	u32	fmqm_etfc;	/* enqueue total frame counter */
+	u32	fmqm_dtfc;	/* dequeue total frame counter */
+	u32	fmqm_dc0;	/* dequeue counter 0 */
+	u32	fmqm_dc1;	/* dequeue counter 1 */
+	u32	fmqm_dc2;	/* dequeue counter 2 */
+	u32	fmqm_dc3;	/* dequeue counter 3 */
+	u32	fmqm_dfnoc;	/* dequeue FQID not override counter */
+	u32	fmqm_dfcc;	/* dequeue FQID from context counter */
+	u32	fmqm_dffc;	/* dequeue FQID from FD counter */
+	u32	fmqm_dcc;	/* dequeue confirm counter */
+	u32	res1[0xc];
+	u32	fmqm_dtrc;	/* debug trap configuration register */
+	u32	fmqm_efddd;	/* enqueue frame descriptor dynamic debug */
+	u32	res3[0x2];
+	u32	res4[0xdc];	/* missing debug regs */
+} fm_qmi_common_t;
+
+typedef struct fm_bmi {
+	u8	res[1024];
+} fm_bmi_t;
+
+typedef struct fm_qmi {
+	u8	res[1024];
+} fm_qmi_t;
+
+struct fm_bmi_rx_port {
+	u32 fmbm_rcfg;	/* Rx configuration */
+	u32 fmbm_rst;	/* Rx status */
+	u32 fmbm_rda;	/* Rx DMA attributes */
+	u32 fmbm_rfp;	/* Rx FIFO parameters */
+	u32 fmbm_rfed;	/* Rx frame end data */
+	u32 fmbm_ricp;	/* Rx internal context parameters */
+	u32 fmbm_rim;	/* Rx internal margins */
+	u32 fmbm_rebm;	/* Rx external buffer margins */
+	u32 fmbm_rfne;	/* Rx frame next engine */
+	u32 fmbm_rfca;	/* Rx frame command attributes */
+	u32 fmbm_rfpne;	/* Rx frame parser next engine */
+	u32 fmbm_rpso;	/* Rx parse start offset */
+	u32 fmbm_rpp;	/* Rx policer profile */
+	u32 fmbm_rccb;	/* Rx coarse classification base */
+	u32 res1[0x2];
+	u32 fmbm_rprai[0x8];	/* Rx parse results array Initialization */
+	u32 fmbm_rfqid;		/* Rx frame queue ID */
+	u32 fmbm_refqid;	/* Rx error frame queue ID */
+	u32 fmbm_rfsdm;		/* Rx frame status discard mask */
+	u32 fmbm_rfsem;		/* Rx frame status error mask */
+	u32 fmbm_rfene;		/* Rx frame enqueue next engine */
+	u32 res2[0x23];
+	u32 fmbm_ebmpi[0x8];	/* buffer manager pool information */
+	u32 fmbm_acnt[0x8];	/* allocate counter */
+	u32 res3[0x8];
+	u32 fmbm_cgm[0x8];	/* congestion group map */
+	u32 fmbm_mpd;		/* BMan pool depletion */
+	u32 res4[0x1F];
+	u32 fmbm_rstc;		/* Rx statistics counters */
+	u32 fmbm_rfrc;		/* Rx frame counters */
+	u32 fmbm_rfbc;		/* Rx bad frames counter */
+	u32 fmbm_rlfc;		/* Rx large frames counter */
+	u32 fmbm_rffc;		/* Rx filter frames counter */
+	u32 fmbm_rfdc;		/* Rx frame discard counter */
+	u32 fmbm_rfldec;	/* Rx frames list DMA error counter */
+	u32 fmbm_rodc;		/* Rx out of buffers discard counter */
+	u32 fmbm_rbdc;		/* Rx buffers deallocate counter */
+	u32 res5[0x17];
+	u32 fmbm_rpc;		/* Rx performance counters */
+	u32 fmbm_rpcp;		/* Rx performance count parameters */
+	u32 fmbm_rccn;		/* Rx cycle counter */
+	u32 fmbm_rtuc;		/* Rx tasks utilization counter */
+	u32 fmbm_rrquc;		/* Rx receive queue utilization counter */
+	u32 fmbm_rduc;		/* Rx DMA utilization counter */
+	u32 fmbm_rfuc;		/* Rx FIFO utilization counter */
+	u32 fmbm_rpac;		/* Rx pause activation counter */
+	u32 res6[0x18];
+	u32 fmbm_rdbg;		/* Rx debug configuration */
+};
+
+/* FMBM_RCFG - Rx configuration */
+#define FMBM_RCFG_EN		0x80000000 /* port is enabled to receive data */
+#define FMBM_RCFG_FDOVR		0x02000000 /* frame discard override */
+#define FMBM_RCFG_IM		0x01000000 /* independent mode */
+
+/* FMBM_RST - Rx status */
+#define FMBM_RST_BSY		0x80000000 /* Rx port is busy */
+
+/* FMBM_RFCA - Rx frame command attributes */
+#define FMBM_RFCA_ORDER		0x80000000
+#define FMBM_RFCA_MR_MASK	0x003f0000
+#define FMBM_RFCA_MR(x)		((x << 16) & FMBM_RFCA_MR_MASK)
+
+/* FMBM_RSTC - Rx statistics */
+#define FMBM_RSTC_EN		0x80000000 /* statistics counters enable */
+
+struct fm_bmi_tx_port {
+	u32 fmbm_tcfg;	/* Tx configuration */
+	u32 fmbm_tst;	/* Tx status */
+	u32 fmbm_tda;	/* Tx DMA attributes */
+	u32 fmbm_tfp;	/* Tx FIFO parameters */
+	u32 fmbm_tfed;	/* Tx frame end data */
+	u32 fmbm_ticp;	/* Tx internal context parameters */
+	u32 fmbm_tfne;	/* Tx frame next engine */
+	u32 fmbm_tfca;	/* Tx frame command attributes */
+	u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */
+	u32 fmbm_tfeqid;/* Tx error frame queue ID */
+	u32 fmbm_tfene;	/* Tx frame enqueue next engine */
+	u32 fmbm_trlmts;/* Tx rate limiter scale */
+	u32 fmbm_trlmt;	/* Tx rate limiter */
+	u32 res0[0x73];
+	u32 fmbm_tstc;	/* Tx statistics counters */
+	u32 fmbm_tfrc;	/* Tx frame counter */
+	u32 fmbm_tfdc;	/* Tx frames discard counter */
+	u32 fmbm_tfledc;/* Tx frame length error discard counter */
+	u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */
+	u32 fmbm_tbdc;	/* Tx buffers deallocate counter */
+	u32 res1[0x1a];
+	u32 fmbm_tpc;	/* Tx performance counters */
+	u32 fmbm_tpcp;	/* Tx performance count parameters */
+	u32 fmbm_tccn;	/* Tx cycle counter */
+	u32 fmbm_ttuc;	/* Tx tasks utilization counter */
+	u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */
+	u32 fmbm_tduc;	/* Tx DMA utilization counter */
+	u32 fmbm_tfuc;	/* Tx FIFO utilization counter */
+	u32 res2[0x19];
+	u32 fmbm_tdcfg;	/* Tx debug configuration */
+};
+
+/* FMBM_TCFG - Tx configuration */
+#define FMBM_TCFG_EN	0x80000000 /* port is enabled to transmit data */
+#define FMBM_TCFG_IM	0x01000000 /* independent mode enable */
+
+/* FMBM_TST - Tx status */
+#define FMBM_TST_BSY		0x80000000 /* Tx port is busy */
+
+/* FMBM_TFCA - Tx frame command attributes */
+#define FMBM_TFCA_ORDER		0x80000000
+#define FMBM_TFCA_MR_MASK	0x003f0000
+#define FMBM_TFCA_MR(x)		((x << 16) & FMBM_TFCA_MR_MASK)
+
+/* FMBM_TSTC - Tx statistics counters */
+#define FMBM_TSTC_EN		0x80000000
+
+/* FMBM_INIT - BMI initialization register */
+#define FMBM_INIT_START		0x80000000 /* init internal buffers */
+
+/* FMBM_CFG1 - BMI configuration 1 */
+#define FMBM_CFG1_FBPS_MASK	0x03ff0000 /* Free buffer pool size */
+#define FMBM_CFG1_FBPS_SHIFT	16
+#define FMBM_CFG1_FBPO_MASK	0x000003ff /* Free buffer pool offset */
+
+/* FMBM_IEVR - interrupt event */
+#define FMBM_IEVR_PEC		0x80000000 /* pipeline table ECC err detected */
+#define FMBM_IEVR_LEC		0x40000000 /* linked list RAM ECC error */
+#define FMBM_IEVR_SEC		0x20000000 /* statistics count RAM ECC error */
+#define FMBM_IEVR_CLEAR_ALL	(FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC)
+
+/* FMBM_IER - interrupt enable */
+#define FMBM_IER_PECE		0x80000000 /* PEC interrupt enable */
+#define FMBM_IER_LECE		0x40000000 /* LEC interrupt enable */
+#define FMBM_IER_SECE		0x20000000 /* SEC interrupt enable */
+
+#define FMBM_IER_DISABLE_ALL	0x00000000
+
+/* FMBM_PP - BMI Port Parameters */
+#define FMBM_PP_MXT_MASK	0x3f000000 /* Max # tasks */
+#define FMBM_PP_MXT(x)		(((x-1) << 24) & FMBM_PP_MXT_MASK)
+#define FMBM_PP_MXD_MASK	0x00000f00 /* Max DMA */
+#define FMBM_PP_MXD(x)		(((x-1) << 8) & FMBM_PP_MXD_MASK)
+
+/* FMBM_PFS - BMI Port FIFO Size */
+#define FMBM_PFS_IFSZ_MASK	0x000003ff /* Internal Fifo Size */
+#define FMBM_PFS_IFSZ(x)	(x & FMBM_PFS_IFSZ_MASK)
+
+/* FMQM_GC - global configuration */
+#define FMQM_GC_ENQ_EN		0x80000000 /* enqueue enable */
+#define FMQM_GC_DEQ_EN		0x40000000 /* dequeue enable */
+#define FMQM_GC_STEN		0x10000000 /* enable global stat counters */
+#define FMQM_GC_ENQ_THR_MASK	0x00003f00 /* max number of enqueue Tnum */
+#define FMQM_GC_ENQ(x)		((x << 8) &  FMQM_GC_ENQ_THR_MAS)
+#define FMQM_GC_DEQ_THR_MASK	0x0000003f /* max number of dequeue Tnum */
+#define FMQM_GC_DEQ(x)		(x & FMQM_GC_DEQ_THR_MASK)
+
+/* FMQM_EIE - error interrupt event register */
+#define FMQM_EIE_DEE		0x80000000 /* double-bit ECC error */
+#define FMQM_EIE_DFUPE		0x40000000 /* dequeue from unknown PortID */
+#define FMQM_EIE_CLEAR_ALL	(FMQM_EIE_DEE | FMQM_EIE_DFUPE)
+
+/* FMQM_EIEN - error interrupt enable register */
+#define FMQM_EIEN_DEEN		0x80000000 /* double-bit ECC error */
+#define FMQM_EIEN_DFUPEN	0x40000000 /* dequeue from unknown PortID */
+#define FMQM_EIEN_DISABLE_ALL	0x00000000
+
+/* FMQM_IE - interrupt event register */
+#define FMQM_IE_SEE		0x80000000 /* single-bit ECC error detected */
+#define FMQM_IE_CLEAR_ALL	FMQM_IE_SEE
+
+/* FMQM_IEN - interrupt enable register */
+#define FMQM_IEN_SEE		0x80000000 /* single-bit ECC err IRQ enable */
+#define FMQM_IEN_DISABLE_ALL	0x00000000
+
+/* NIA - next invoked action */
+#define NIA_ENG_RISC		0x00000000
+#define NIA_ENG_MASK		0x007c0000
+
+/* action code */
+#define NIA_RISC_AC_CC		0x00000006
+#define NIA_RISC_AC_IM_TX	0x00000008 /* independent mode Tx */
+#define NIA_RISC_AC_IM_RX	0x0000000a /* independent mode Rx */
+#define NIA_RISC_AC_HC		0x0000000c
+
+typedef struct fm_parser {
+	u8	res[1024];
+} fm_parser_t;
+
+typedef struct fm_policer {
+	u8	res[4*1024];
+} fm_policer_t;
+
+typedef struct fm_keygen {
+	u8	res[4*1024];
+} fm_keygen_t;
+
+typedef struct fm_dma {
+	u32	fmdmsr;		/* status register */
+	u32	fmdmmr;		/* mode register */
+	u32	fmdmtr;		/* bus threshold register */
+	u32	fmdmhy;		/* bus hysteresis register */
+	u32	fmdmsetr;	/* SOS emergency threshold register */
+	u32	fmdmtah;	/* transfer bus address high register */
+	u32	fmdmtal;	/* transfer bus address low register */
+	u32	fmdmtcid;	/* transfer bus communication ID register */
+	u32	fmdmra;		/* DMA bus internal ram address register */
+	u32	fmdmrd;		/* DMA bus internal ram data register */
+	u32	res0[0xb];
+	u32	fmdmdcr;	/* debug counter */
+	u32	fmdmemsr;	/* emrgency smoother register */
+	u32	res1;
+	u32	fmdmplr[32];	/* FM DMA PID-LIODN # register */
+	u32	res[0x3c8];
+} fm_dma_t;
+
+/* FMDMSR - Fman DMA status register */
+#define FMDMSR_CMDQNE		0x10000000 /* command queue not empty */
+#define FMDMSR_BER		0x08000000 /* bus err event occurred on bus */
+#define FMDMSR_RDB_ECC		0x04000000 /* read buffer ECC error */
+#define FMDMSR_WRB_SECC		0x02000000 /* write buf ECC err sys side */
+#define FMDMSR_WRB_FECC		0x01000000 /* write buf ECC err Fman side */
+#define FMDMSR_DPEXT_SECC	0x00800000 /* DP external ECC err sys side */
+#define FMDMSR_DPEXT_FECC	0x00400000 /* DP external ECC err Fman side */
+#define FMDMSR_DPDAT_SECC	0x00200000 /* DP data ECC err on sys side */
+#define FMDMSR_DPDAT_FECC	0x00100000 /* DP data ECC err on Fman side */
+#define FMDMSR_SPDAT_FECC	0x00080000 /* SP data ECC error Fman side */
+
+#define FMDMSR_CLEAR_ALL	(FMDMSR_BER | FMDMSR_RDB_ECC \
+				| FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \
+				| FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \
+				| FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \
+				| FMDMSR_SPDAT_FECC)
+
+/* FMDMMR - FMan DMA mode register */
+#define FMDMMR_SBER		0x10000000 /* stop the DMA if a bus error */
+
+typedef struct fm_fpm {
+	u32	fpmtnc;		/* TNUM control */
+	u32	fpmprc;		/* Port_ID control */
+	u32	res0;
+	u32	fpmflc;		/* flush control */
+	u32	fpmdis1;	/* dispatch thresholds1 */
+	u32	fpmdis2;	/* dispatch thresholds2 */
+	u32	fmepi;		/* error pending interrupts */
+	u32	fmrie;		/* rams interrupt enable */
+	u32	fpmfcevent[0x4];/* FMan controller event 0-3 */
+	u32	res1[0x4];
+	u32	fpmfcmask[0x4];	/* FMan controller mask 0-3 */
+	u32	res2[0x4];
+	u32	fpmtsc1;	/* timestamp control1 */
+	u32	fpmtsc2;	/* timestamp control2 */
+	u32	fpmtsp;		/* time stamp */
+	u32	fpmtsf;		/* time stamp fraction */
+	u32	fpmrcr;		/* rams control and event */
+	u32	res3[0x3];
+	u32	fpmdrd[0x4];	/* data_ram data 0-3 */
+	u32	res4[0xc];
+	u32	fpmdra;		/* data ram access */
+	u32	fm_ip_rev_1;	/* IP block revision 1 */
+	u32	fm_ip_rev_2;	/* IP block revision 2 */
+	u32	fmrstc;		/* reset command */
+	u32	fmcld;		/* classifier debug control */
+	u32	fmnpi;		/* normal pending interrupts */
+	u32	res5;
+	u32	fmfpee;		/* event and enable */
+	u32	fpmcev[0x4];	/* CPU event 0-3 */
+	u32	res6[0x4];
+	u32	fmfp_ps[0x40];	/* port status */
+	u32	res7[0x260];
+	u32	fpmts[0x80];	/* task status */
+	u32	res8[0xa0];
+} fm_fpm_t;
+
+/* FMFP_PRC - FPM Port_ID Control Register */
+#define FMFPPRC_PORTID_MASK	0x3f000000
+#define FMFPPRC_PORTID_SHIFT	24
+#define FMFPPRC_ORA_SHIFT	16
+#define FMFPPRC_RISC1		0x00000001
+#define FMFPPRC_RISC2		0x00000002
+#define FMFPPRC_RISC_ALL	(FMFPPRC_RISC1 | FMFPPRC_RSIC2)
+
+/* FPM Flush Control Register */
+#define FMFP_FLC_DISP_LIM_NONE	0x00000000 /* no dispatch limitation */
+
+/* FMFP_EE - FPM event and enable register */
+#define FMFPEE_DECC		0x80000000 /* double ECC err on FPM ram */
+#define FMFPEE_STL		0x40000000 /* stall of task ... */
+#define FMFPEE_SECC		0x20000000 /* single ECC error */
+#define FMFPEE_RFM		0x00010000 /* release FMan */
+#define FMFPEE_DECC_EN		0x00008000 /* double ECC interrupt enable */
+#define FMFPEE_STL_EN		0x00004000 /* stall of task interrupt enable */
+#define FMFPEE_SECC_EN		0x00002000 /* single ECC err interrupt enable */
+#define FMFPEE_EHM		0x00000008 /* external halt enable */
+#define FMFPEE_UEC		0x00000004 /* FMan is not halted */
+#define FMFPEE_CER		0x00000002 /* only errornous task stalled */
+#define FMFPEE_DER		0x00000001 /* DMA error is just reported */
+
+#define FMFPEE_CLEAR_EVENT	(FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \
+				 FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \
+				 FMFPEE_DER | FMFPEE_RFM)
+
+/* FMFP_RCR - FMan Rams Control and Event */
+#define FMFP_RCR_MDEC		0x00008000 /* double ECC error in muram */
+#define FMFP_RCR_IDEC		0x00004000 /* double ECC error in iram */
+
+typedef struct fm_imem {
+	u32	iadd;		/* instruction address register */
+	u32	idata;		/* instruction data register */
+	u32	itcfg;		/* timing config register */
+	u32	iready;		/* ready register */
+	u8	res[0xff0];
+} fm_imem_t;
+#define IRAM_IADD_AIE		0x80000000 /* address auto increase enable */
+#define IRAM_READY		0x80000000 /* ready to use */
+
+typedef struct fm_soft_parser {
+	u8	res[4*1024];
+} fm_soft_parser_t;
+
+typedef struct fm_dtesc {
+	u8	res[4*1024];
+} fm_dtsec_t;
+
+typedef struct fm_mdio {
+	u8	res0[0x120];
+	u32	miimcfg;	/* MII management configuration reg */
+	u32	miimcom;	/* MII management command reg */
+	u32	miimadd;	/* MII management address reg */
+	u32	miimcon;	/* MII management control reg */
+	u32	miimstat;	/* MII management status reg  */
+	u32	miimind;	/* MII management indication reg */
+	u8	res1[0x1000 - 0x138];
+} fm_mdio_t;
+
+typedef struct fm_10gec {
+	u8	res[4*1024];
+} fm_10gec_t;
+
+typedef struct fm_10gec_mdio {
+	u8	res[4*1024];
+} fm_10gec_mdio_t;
+
+typedef struct fm_memac {
+	u8	res[4*1024];
+} fm_memac_t;
+
+typedef struct fm_memac_mdio {
+	u8	res[4*1024];
+} fm_memac_mdio_t;
+
+typedef struct fm_1588 {
+	u8	res[4*1024];
+} fm_1588_t;
+
+typedef struct ccsr_fman {
+	u8			muram[0x80000];
+	fm_bmi_common_t		fm_bmi_common;
+	fm_qmi_common_t		fm_qmi_common;
+	u8			res0[2048];
+	struct {
+		fm_bmi_t	fm_bmi;
+		fm_qmi_t	fm_qmi;
+		fm_parser_t	fm_parser;
+		u8		res[1024];
+	} port[63];
+	fm_policer_t		fm_policer;
+	fm_keygen_t		fm_keygen;
+	fm_dma_t		fm_dma;
+	fm_fpm_t		fm_fpm;
+	fm_imem_t		fm_imem;
+	u8			res1[8*1024];
+	fm_soft_parser_t	fm_soft_parser;
+	u8			res2[96*1024];
+#ifdef CONFIG_SYS_FMAN_V3
+	struct {
+		fm_memac_t		fm_memac;
+		fm_memac_mdio_t		fm_memac_mdio;
+	} memac[10];
+	u8			res4[32*1024];
+	fm_memac_mdio_t		fm_dedicated_mdio[2];
+#else
+	struct {
+		fm_dtsec_t	fm_dtesc;
+		fm_mdio_t	fm_mdio;
+	} mac_1g[8];		/* support up to 8 1g controllers */
+	struct {
+		fm_10gec_t		fm_10gec;
+		fm_10gec_mdio_t		fm_10gec_mdio;
+	} mac_10g[1];
+	u8			res4[48*1024];
+#endif
+	fm_1588_t		fm_1588;
+	u8			res5[4*1024];
+} ccsr_fman_t;
+
+void fdt_fixup_fman_firmware(void *blob);
+#endif /*__FSL_FMAN_H__*/
diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h
new file mode 100644
index 0000000..3edcc39
--- /dev/null
+++ b/include/fsl_ifc.h
@@ -0,0 +1,1058 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
+ */
+
+#ifndef __FSL_IFC_H
+#define __FSL_IFC_H
+
+#ifdef CONFIG_FSL_IFC
+#include <config.h>
+#include <common.h>
+#ifdef CONFIG_ARM
+#include <asm/arch/soc.h>
+#endif
+
+#define FSL_IFC_V1_1_0	0x01010000
+#define FSL_IFC_V2_0_0	0x02000000
+
+#ifdef CONFIG_SYS_FSL_IFC_LE
+#define ifc_in32(a)       in_le32(a)
+#define ifc_out32(a, v)   out_le32(a, v)
+#define ifc_in16(a)       in_le16(a)
+#define ifc_out16(a, v)   out_le16(a, v)
+#elif defined(CONFIG_SYS_FSL_IFC_BE)
+#define ifc_in32(a)       in_be32(a)
+#define ifc_out32(a, v)   out_be32(a, v)
+#define ifc_in16(a)       in_be16(a)
+#define ifc_out16(a, v)   out_be16(a, v)
+#else
+#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
+#endif
+
+
+/*
+ * CSPR - Chip Select Property Register
+ */
+#define CSPR_BA				0xFFFF0000
+#define CSPR_BA_SHIFT			16
+#define CSPR_PORT_SIZE			0x00000180
+#define CSPR_PORT_SIZE_SHIFT		7
+/* Port Size 8 bit */
+#define CSPR_PORT_SIZE_8		0x00000080
+/* Port Size 16 bit */
+#define CSPR_PORT_SIZE_16		0x00000100
+/* Port Size 32 bit */
+#define CSPR_PORT_SIZE_32		0x00000180
+/* Write Protect */
+#define CSPR_WP				0x00000040
+#define CSPR_WP_SHIFT			6
+/* Machine Select */
+#define CSPR_MSEL			0x00000006
+#define CSPR_MSEL_SHIFT			1
+/* NOR */
+#define CSPR_MSEL_NOR			0x00000000
+/* NAND */
+#define CSPR_MSEL_NAND			0x00000002
+/* GPCM */
+#define CSPR_MSEL_GPCM			0x00000004
+/* Bank Valid */
+#define CSPR_V				0x00000001
+#define CSPR_V_SHIFT			0
+
+/* Convert an address into the right format for the CSPR Registers */
+#define CSPR_PHYS_ADDR(x)		(((uint64_t)x) & 0xffff0000)
+
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK			0xFFFF0000
+#define IFC_AMASK_SHIFT			16
+#define IFC_AMASK(n)			(IFC_AMASK_MASK << \
+					(LOG2(n) - IFC_AMASK_SHIFT))
+
+/*
+ * Chip Select Option Register IFC_NAND Machine
+ */
+/* Enable ECC Encoder */
+#define CSOR_NAND_ECC_ENC_EN		0x80000000
+#define CSOR_NAND_ECC_MODE_MASK		0x30000000
+/* 4 bit correction per 520 Byte sector */
+#define CSOR_NAND_ECC_MODE_4		0x00000000
+/* 8 bit correction per 528 Byte sector */
+#define CSOR_NAND_ECC_MODE_8		0x10000000
+/* Enable ECC Decoder */
+#define CSOR_NAND_ECC_DEC_EN		0x04000000
+/* Row Address Length */
+#define CSOR_NAND_RAL_MASK		0x01800000
+#define CSOR_NAND_RAL_SHIFT		20
+#define CSOR_NAND_RAL_1			0x00000000
+#define CSOR_NAND_RAL_2			0x00800000
+#define CSOR_NAND_RAL_3			0x01000000
+#define CSOR_NAND_RAL_4			0x01800000
+/* Page Size 512b, 2k, 4k */
+#define CSOR_NAND_PGS_MASK		0x00180000
+#define CSOR_NAND_PGS_SHIFT		16
+#define CSOR_NAND_PGS_512		0x00000000
+#define CSOR_NAND_PGS_2K		0x00080000
+#define CSOR_NAND_PGS_4K		0x00100000
+#define CSOR_NAND_PGS_8K		0x00180000
+/* Spare region Size */
+#define CSOR_NAND_SPRZ_MASK		0x0000E000
+#define CSOR_NAND_SPRZ_SHIFT		13
+#define CSOR_NAND_SPRZ_16		0x00000000
+#define CSOR_NAND_SPRZ_64		0x00002000
+#define CSOR_NAND_SPRZ_128		0x00004000
+#define CSOR_NAND_SPRZ_210		0x00006000
+#define CSOR_NAND_SPRZ_218		0x00008000
+#define CSOR_NAND_SPRZ_224		0x0000A000
+#define CSOR_NAND_SPRZ_CSOR_EXT	0x0000C000
+/* Pages Per Block */
+#define CSOR_NAND_PB_MASK		0x00000700
+#define CSOR_NAND_PB_SHIFT		8
+#define CSOR_NAND_PB(n)		((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NAND_TRHZ_MASK		0x0000001C
+#define CSOR_NAND_TRHZ_SHIFT		2
+#define CSOR_NAND_TRHZ_20		0x00000000
+#define CSOR_NAND_TRHZ_40		0x00000004
+#define CSOR_NAND_TRHZ_60		0x00000008
+#define CSOR_NAND_TRHZ_80		0x0000000C
+#define CSOR_NAND_TRHZ_100		0x00000010
+/* Buffer control disable */
+#define CSOR_NAND_BCTLD			0x00000001
+
+/*
+ * Chip Select Option Register - NOR Flash Mode
+ */
+/* Enable Address shift Mode */
+#define CSOR_NOR_ADM_SHFT_MODE_EN	0x80000000
+/* Page Read Enable from NOR device */
+#define CSOR_NOR_PGRD_EN		0x10000000
+/* AVD Toggle Enable during Burst Program */
+#define CSOR_NOR_AVD_TGL_PGM_EN		0x01000000
+/* Address Data Multiplexing Shift */
+#define CSOR_NOR_ADM_MASK		0x0003E000
+#define CSOR_NOR_ADM_SHIFT_SHIFT	13
+#define CSOR_NOR_ADM_SHIFT(n)	((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
+/* Type of the NOR device hooked */
+#define CSOR_NOR_NOR_MODE_AYSNC_NOR	0x00000000
+#define CSOR_NOR_NOR_MODE_AVD_NOR	0x00000020
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NOR_TRHZ_MASK		0x0000001C
+#define CSOR_NOR_TRHZ_SHIFT		2
+#define CSOR_NOR_TRHZ_20		0x00000000
+#define CSOR_NOR_TRHZ_40		0x00000004
+#define CSOR_NOR_TRHZ_60		0x00000008
+#define CSOR_NOR_TRHZ_80		0x0000000C
+#define CSOR_NOR_TRHZ_100		0x00000010
+/* Buffer control disable */
+#define CSOR_NOR_BCTLD			0x00000001
+
+/*
+ * Chip Select Option Register - GPCM Mode
+ */
+/* GPCM Mode - Normal */
+#define CSOR_GPCM_GPMODE_NORMAL		0x00000000
+/* GPCM Mode - GenericASIC */
+#define CSOR_GPCM_GPMODE_ASIC		0x80000000
+/* Parity Mode odd/even */
+#define CSOR_GPCM_PARITY_EVEN		0x40000000
+/* Parity Checking enable/disable */
+#define CSOR_GPCM_PAR_EN		0x20000000
+/* GPCM Timeout Count */
+#define CSOR_GPCM_GPTO_MASK		0x0F000000
+#define CSOR_GPCM_GPTO_SHIFT		24
+#define CSOR_GPCM_GPTO(n)	((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
+/* GPCM External Access Termination mode for read access */
+#define CSOR_GPCM_RGETA_EXT		0x00080000
+/* GPCM External Access Termination mode for write access */
+#define CSOR_GPCM_WGETA_EXT		0x00040000
+/* Address Data Multiplexing Shift */
+#define CSOR_GPCM_ADM_MASK		0x0003E000
+#define CSOR_GPCM_ADM_SHIFT_SHIFT	13
+#define CSOR_GPCM_ADM_SHIFT(n)	((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
+/* Generic ASIC Parity error indication delay */
+#define CSOR_GPCM_GAPERRD_MASK		0x00000180
+#define CSOR_GPCM_GAPERRD_SHIFT		7
+#define CSOR_GPCM_GAPERRD(n)	(((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_GPCM_TRHZ_MASK		0x0000001C
+#define CSOR_GPCM_TRHZ_20		0x00000000
+#define CSOR_GPCM_TRHZ_40		0x00000004
+#define CSOR_GPCM_TRHZ_60		0x00000008
+#define CSOR_GPCM_TRHZ_80		0x0000000C
+#define CSOR_GPCM_TRHZ_100		0x00000010
+/* Buffer control disable */
+#define CSOR_GPCM_BCTLD			0x00000001
+
+/*
+ * Flash Timing Registers (FTIM0 - FTIM2_CSn)
+ */
+/*
+ * FTIM0 - NAND Flash Mode
+ */
+#define FTIM0_NAND			0x7EFF3F3F
+#define FTIM0_NAND_TCCST_SHIFT	25
+#define FTIM0_NAND_TCCST(n)	((n) << FTIM0_NAND_TCCST_SHIFT)
+#define FTIM0_NAND_TWP_SHIFT	16
+#define FTIM0_NAND_TWP(n)	((n) << FTIM0_NAND_TWP_SHIFT)
+#define FTIM0_NAND_TWCHT_SHIFT	8
+#define FTIM0_NAND_TWCHT(n)	((n) << FTIM0_NAND_TWCHT_SHIFT)
+#define FTIM0_NAND_TWH_SHIFT	0
+#define FTIM0_NAND_TWH(n)	((n) << FTIM0_NAND_TWH_SHIFT)
+/*
+ * FTIM1 - NAND Flash Mode
+ */
+#define FTIM1_NAND			0xFFFF3FFF
+#define FTIM1_NAND_TADLE_SHIFT	24
+#define FTIM1_NAND_TADLE(n)	((n) << FTIM1_NAND_TADLE_SHIFT)
+#define FTIM1_NAND_TWBE_SHIFT	16
+#define FTIM1_NAND_TWBE(n)	((n) << FTIM1_NAND_TWBE_SHIFT)
+#define FTIM1_NAND_TRR_SHIFT	8
+#define FTIM1_NAND_TRR(n)	((n) << FTIM1_NAND_TRR_SHIFT)
+#define FTIM1_NAND_TRP_SHIFT	0
+#define FTIM1_NAND_TRP(n)	((n) << FTIM1_NAND_TRP_SHIFT)
+/*
+ * FTIM2 - NAND Flash Mode
+ */
+#define FTIM2_NAND			0x1FE1F8FF
+#define FTIM2_NAND_TRAD_SHIFT	21
+#define FTIM2_NAND_TRAD(n)	((n) << FTIM2_NAND_TRAD_SHIFT)
+#define FTIM2_NAND_TREH_SHIFT	11
+#define FTIM2_NAND_TREH(n)	((n) << FTIM2_NAND_TREH_SHIFT)
+#define FTIM2_NAND_TWHRE_SHIFT	0
+#define FTIM2_NAND_TWHRE(n)	((n) << FTIM2_NAND_TWHRE_SHIFT)
+/*
+ * FTIM3 - NAND Flash Mode
+ */
+#define FTIM3_NAND			0xFF000000
+#define FTIM3_NAND_TWW_SHIFT	24
+#define FTIM3_NAND_TWW(n)	((n) << FTIM3_NAND_TWW_SHIFT)
+
+/*
+ * FTIM0 - NOR Flash Mode
+ */
+#define FTIM0_NOR			0xF03F3F3F
+#define FTIM0_NOR_TACSE_SHIFT	28
+#define FTIM0_NOR_TACSE(n)	((n) << FTIM0_NOR_TACSE_SHIFT)
+#define FTIM0_NOR_TEADC_SHIFT	16
+#define FTIM0_NOR_TEADC(n)	((n) << FTIM0_NOR_TEADC_SHIFT)
+#define FTIM0_NOR_TAVDS_SHIFT	8
+#define FTIM0_NOR_TAVDS(n)	((n) << FTIM0_NOR_TAVDS_SHIFT)
+#define FTIM0_NOR_TEAHC_SHIFT	0
+#define FTIM0_NOR_TEAHC(n)	((n) << FTIM0_NOR_TEAHC_SHIFT)
+/*
+ * FTIM1 - NOR Flash Mode
+ */
+#define FTIM1_NOR			0xFF003F3F
+#define FTIM1_NOR_TACO_SHIFT	24
+#define FTIM1_NOR_TACO(n)	((n) << FTIM1_NOR_TACO_SHIFT)
+#define FTIM1_NOR_TRAD_NOR_SHIFT	8
+#define FTIM1_NOR_TRAD_NOR(n)	((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
+#define FTIM1_NOR_TSEQRAD_NOR_SHIFT	0
+#define FTIM1_NOR_TSEQRAD_NOR(n)	((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
+/*
+ * FTIM2 - NOR Flash Mode
+ */
+#define FTIM2_NOR			0x0F3CFCFF
+#define FTIM2_NOR_TCS_SHIFT		24
+#define FTIM2_NOR_TCS(n)	((n) << FTIM2_NOR_TCS_SHIFT)
+#define FTIM2_NOR_TCH_SHIFT		18
+#define FTIM2_NOR_TCH(n)	((n) << FTIM2_NOR_TCH_SHIFT)
+#define FTIM2_NOR_TWPH_SHIFT	10
+#define FTIM2_NOR_TWPH(n)	((n) << FTIM2_NOR_TWPH_SHIFT)
+#define FTIM2_NOR_TWP_SHIFT		0
+#define FTIM2_NOR_TWP(n)	((n) << FTIM2_NOR_TWP_SHIFT)
+
+/*
+ * FTIM0 - Normal GPCM Mode
+ */
+#define FTIM0_GPCM			0xF03F3F3F
+#define FTIM0_GPCM_TACSE_SHIFT	28
+#define FTIM0_GPCM_TACSE(n)	((n) << FTIM0_GPCM_TACSE_SHIFT)
+#define FTIM0_GPCM_TEADC_SHIFT	16
+#define FTIM0_GPCM_TEADC(n)	((n) << FTIM0_GPCM_TEADC_SHIFT)
+#define FTIM0_GPCM_TAVDS_SHIFT	8
+#define FTIM0_GPCM_TAVDS(n)	((n) << FTIM0_GPCM_TAVDS_SHIFT)
+#define FTIM0_GPCM_TEAHC_SHIFT	0
+#define FTIM0_GPCM_TEAHC(n)	((n) << FTIM0_GPCM_TEAHC_SHIFT)
+/*
+ * FTIM1 - Normal GPCM Mode
+ */
+#define FTIM1_GPCM			0xFF003F00
+#define FTIM1_GPCM_TACO_SHIFT	24
+#define FTIM1_GPCM_TACO(n)	((n) << FTIM1_GPCM_TACO_SHIFT)
+#define FTIM1_GPCM_TRAD_SHIFT	8
+#define FTIM1_GPCM_TRAD(n)	((n) << FTIM1_GPCM_TRAD_SHIFT)
+/*
+ * FTIM2 - Normal GPCM Mode
+ */
+#define FTIM2_GPCM			0x0F3C00FF
+#define FTIM2_GPCM_TCS_SHIFT	24
+#define FTIM2_GPCM_TCS(n)	((n) << FTIM2_GPCM_TCS_SHIFT)
+#define FTIM2_GPCM_TCH_SHIFT	18
+#define FTIM2_GPCM_TCH(n)	((n) << FTIM2_GPCM_TCH_SHIFT)
+#define FTIM2_GPCM_TWP_SHIFT	0
+#define FTIM2_GPCM_TWP(n)	((n) << FTIM2_GPCM_TWP_SHIFT)
+
+/*
+ * Ready Busy Status Register (RB_STAT)
+ */
+/* CSn is READY */
+#define IFC_RB_STAT_READY_CS0		0x80000000
+#define IFC_RB_STAT_READY_CS1		0x40000000
+#define IFC_RB_STAT_READY_CS2		0x20000000
+#define IFC_RB_STAT_READY_CS3		0x10000000
+
+/*
+ * General Control Register (GCR)
+ */
+#define IFC_GCR_MASK			0x8000F800
+/* reset all IFC hardware */
+#define IFC_GCR_SOFT_RST_ALL		0x80000000
+/* Turnaroud Time of external buffer */
+#define IFC_GCR_TBCTL_TRN_TIME		0x0000F800
+#define IFC_GCR_TBCTL_TRN_TIME_SHIFT	11
+
+/*
+ * Common Event and Error Status Register (CM_EVTER_STAT)
+ */
+/* Chip select error */
+#define IFC_CM_EVTER_STAT_CSER		0x80000000
+
+/*
+ * Common Event and Error Enable Register (CM_EVTER_EN)
+ */
+/* Chip select error checking enable */
+#define IFC_CM_EVTER_EN_CSEREN		0x80000000
+
+/*
+ * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
+ */
+/* Chip select error interrupt enable */
+#define IFC_CM_EVTER_INTR_EN_CSERIREN	0x80000000
+
+/*
+ * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
+ */
+/* transaction type of error Read/Write */
+#define IFC_CM_ERATTR0_ERTYP_READ	0x80000000
+#define IFC_CM_ERATTR0_ERAID		0x0FF00000
+#define IFC_CM_ERATTR0_ESRCID		0x0000FF00
+
+/*
+ * Clock Control Register (CCR)
+ */
+#define IFC_CCR_MASK			0x0F0F8800
+/* Clock division ratio */
+#define IFC_CCR_CLK_DIV_MASK		0x0F000000
+#define IFC_CCR_CLK_DIV_SHIFT		24
+#define IFC_CCR_CLK_DIV(n)		((n-1) << IFC_CCR_CLK_DIV_SHIFT)
+/* IFC Clock Delay */
+#define IFC_CCR_CLK_DLY_MASK		0x000F0000
+#define IFC_CCR_CLK_DLY_SHIFT		16
+#define IFC_CCR_CLK_DLY(n)		((n) << IFC_CCR_CLK_DLY_SHIFT)
+/* Invert IFC clock before sending out */
+#define IFC_CCR_INV_CLK_EN		0x00008000
+/* Fedback IFC Clock */
+#define IFC_CCR_FB_IFC_CLK_SEL		0x00000800
+
+/*
+ * Clock Status Register (CSR)
+ */
+/* Clk is stable */
+#define IFC_CSR_CLK_STAT_STABLE		0x80000000
+
+/*
+ * IFC_NAND Machine Specific Registers
+ */
+/*
+ * NAND Configuration Register (NCFGR)
+ */
+/* Auto Boot Mode */
+#define IFC_NAND_NCFGR_BOOT		0x80000000
+/* SRAM INIT EN */
+#define IFC_NAND_SRAM_INIT_EN		0x20000000
+/* Addressing Mode-ROW0+n/COL0 */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC0	0x00000000
+/* Addressing Mode-ROW0+n/COL0+n */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC1	0x00400000
+/* Number of loop iterations of FIR sequences for multi page operations */
+#define IFC_NAND_NCFGR_NUM_LOOP_MASK	0x0000F000
+#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT	12
+#define IFC_NAND_NCFGR_NUM_LOOP(n)	((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
+/* Number of wait cycles */
+#define IFC_NAND_NCFGR_NUM_WAIT_MASK	0x000000FF
+#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT	0
+
+/*
+ * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
+ */
+/* General purpose FCM flash command bytes CMD0-CMD7 */
+#define IFC_NAND_FCR0_CMD0		0xFF000000
+#define IFC_NAND_FCR0_CMD0_SHIFT	24
+#define IFC_NAND_FCR0_CMD1		0x00FF0000
+#define IFC_NAND_FCR0_CMD1_SHIFT	16
+#define IFC_NAND_FCR0_CMD2		0x0000FF00
+#define IFC_NAND_FCR0_CMD2_SHIFT	8
+#define IFC_NAND_FCR0_CMD3		0x000000FF
+#define IFC_NAND_FCR0_CMD3_SHIFT	0
+#define IFC_NAND_FCR1_CMD4		0xFF000000
+#define IFC_NAND_FCR1_CMD4_SHIFT	24
+#define IFC_NAND_FCR1_CMD5		0x00FF0000
+#define IFC_NAND_FCR1_CMD5_SHIFT	16
+#define IFC_NAND_FCR1_CMD6		0x0000FF00
+#define IFC_NAND_FCR1_CMD6_SHIFT	8
+#define IFC_NAND_FCR1_CMD7		0x000000FF
+#define IFC_NAND_FCR1_CMD7_SHIFT	0
+
+/*
+ * Flash ROW and COL Address Register (ROWn, COLn)
+ */
+/* Main/spare region locator */
+#define IFC_NAND_COL_MS			0x80000000
+/* Column Address */
+#define IFC_NAND_COL_CA_MASK		0x00000FFF
+
+/*
+ * NAND Flash Byte Count Register (NAND_BC)
+ */
+/* Byte Count for read/Write */
+#define IFC_NAND_BC			0x000001FF
+
+/*
+ * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
+ */
+/* NAND Machine specific opcodes OP0-OP14*/
+#define IFC_NAND_FIR0_OP0		0xFC000000
+#define IFC_NAND_FIR0_OP0_SHIFT		26
+#define IFC_NAND_FIR0_OP1		0x03F00000
+#define IFC_NAND_FIR0_OP1_SHIFT		20
+#define IFC_NAND_FIR0_OP2		0x000FC000
+#define IFC_NAND_FIR0_OP2_SHIFT		14
+#define IFC_NAND_FIR0_OP3		0x00003F00
+#define IFC_NAND_FIR0_OP3_SHIFT		8
+#define IFC_NAND_FIR0_OP4		0x000000FC
+#define IFC_NAND_FIR0_OP4_SHIFT		2
+#define IFC_NAND_FIR1_OP5		0xFC000000
+#define IFC_NAND_FIR1_OP5_SHIFT		26
+#define IFC_NAND_FIR1_OP6		0x03F00000
+#define IFC_NAND_FIR1_OP6_SHIFT		20
+#define IFC_NAND_FIR1_OP7		0x000FC000
+#define IFC_NAND_FIR1_OP7_SHIFT		14
+#define IFC_NAND_FIR1_OP8		0x00003F00
+#define IFC_NAND_FIR1_OP8_SHIFT		8
+#define IFC_NAND_FIR1_OP9		0x000000FC
+#define IFC_NAND_FIR1_OP9_SHIFT		2
+#define IFC_NAND_FIR2_OP10		0xFC000000
+#define IFC_NAND_FIR2_OP10_SHIFT	26
+#define IFC_NAND_FIR2_OP11		0x03F00000
+#define IFC_NAND_FIR2_OP11_SHIFT	20
+#define IFC_NAND_FIR2_OP12		0x000FC000
+#define IFC_NAND_FIR2_OP12_SHIFT	14
+#define IFC_NAND_FIR2_OP13		0x00003F00
+#define IFC_NAND_FIR2_OP13_SHIFT	8
+#define IFC_NAND_FIR2_OP14		0x000000FC
+#define IFC_NAND_FIR2_OP14_SHIFT	2
+
+/*
+ * Instruction opcodes to be programmed
+ * in FIR registers- 6bits
+ */
+enum ifc_nand_fir_opcodes {
+	IFC_FIR_OP_NOP,
+	IFC_FIR_OP_CA0,
+	IFC_FIR_OP_CA1,
+	IFC_FIR_OP_CA2,
+	IFC_FIR_OP_CA3,
+	IFC_FIR_OP_RA0,
+	IFC_FIR_OP_RA1,
+	IFC_FIR_OP_RA2,
+	IFC_FIR_OP_RA3,
+	IFC_FIR_OP_CMD0,
+	IFC_FIR_OP_CMD1,
+	IFC_FIR_OP_CMD2,
+	IFC_FIR_OP_CMD3,
+	IFC_FIR_OP_CMD4,
+	IFC_FIR_OP_CMD5,
+	IFC_FIR_OP_CMD6,
+	IFC_FIR_OP_CMD7,
+	IFC_FIR_OP_CW0,
+	IFC_FIR_OP_CW1,
+	IFC_FIR_OP_CW2,
+	IFC_FIR_OP_CW3,
+	IFC_FIR_OP_CW4,
+	IFC_FIR_OP_CW5,
+	IFC_FIR_OP_CW6,
+	IFC_FIR_OP_CW7,
+	IFC_FIR_OP_WBCD,
+	IFC_FIR_OP_RBCD,
+	IFC_FIR_OP_BTRD,
+	IFC_FIR_OP_RDSTAT,
+	IFC_FIR_OP_NWAIT,
+	IFC_FIR_OP_WFR,
+	IFC_FIR_OP_SBRD,
+	IFC_FIR_OP_UA,
+	IFC_FIR_OP_RB,
+};
+
+/*
+ * NAND Chip Select Register (NAND_CSEL)
+ */
+#define IFC_NAND_CSEL			0x0C000000
+#define IFC_NAND_CSEL_SHIFT		26
+#define IFC_NAND_CSEL_CS0		0x00000000
+#define IFC_NAND_CSEL_CS1		0x04000000
+#define IFC_NAND_CSEL_CS2		0x08000000
+#define IFC_NAND_CSEL_CS3		0x0C000000
+
+/*
+ * NAND Operation Sequence Start (NANDSEQ_STRT)
+ */
+/* NAND Flash Operation Start */
+#define IFC_NAND_SEQ_STRT_FIR_STRT	0x80000000
+/* Automatic Erase */
+#define IFC_NAND_SEQ_STRT_AUTO_ERS	0x00800000
+/* Automatic Program */
+#define IFC_NAND_SEQ_STRT_AUTO_PGM	0x00100000
+/* Automatic Copyback */
+#define IFC_NAND_SEQ_STRT_AUTO_CPB	0x00020000
+/* Automatic Read Operation */
+#define IFC_NAND_SEQ_STRT_AUTO_RD	0x00004000
+/* Automatic Status Read */
+#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD	0x00000800
+
+/*
+ * NAND Event and Error Status Register (NAND_EVTER_STAT)
+ */
+/* Operation Complete */
+#define IFC_NAND_EVTER_STAT_OPC		0x80000000
+/* Flash Timeout Error */
+#define IFC_NAND_EVTER_STAT_FTOER	0x08000000
+/* Write Protect Error */
+#define IFC_NAND_EVTER_STAT_WPER	0x04000000
+/* ECC Error */
+#define IFC_NAND_EVTER_STAT_ECCER	0x02000000
+/* RCW Load Done */
+#define IFC_NAND_EVTER_STAT_RCW_DN	0x00008000
+/* Boot Loadr Done */
+#define IFC_NAND_EVTER_STAT_BOOT_DN	0x00004000
+/* Bad Block Indicator search select */
+#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE	0x00000800
+
+/*
+ * NAND Flash Page Read Completion Event Status Register
+ * (PGRDCMPL_EVT_STAT)
+ */
+#define PGRDCMPL_EVT_STAT_MASK		0xFFFF0000
+/* Small Page 0-15 Done */
+#define PGRDCMPL_EVT_STAT_SECTION_SP(n)	(1 << (31 - (n)))
+/* Large Page(2K) 0-3 Done */
+#define PGRDCMPL_EVT_STAT_LP_2K(n)	(0xF << (28 - (n)*4))
+/* Large Page(4K) 0-1 Done */
+#define PGRDCMPL_EVT_STAT_LP_4K(n)	(0xFF << (24 - (n)*8))
+
+/*
+ * NAND Event and Error Enable Register (NAND_EVTER_EN)
+ */
+/* Operation complete event enable */
+#define IFC_NAND_EVTER_EN_OPC_EN	0x80000000
+/* Page read complete event enable */
+#define IFC_NAND_EVTER_EN_PGRDCMPL_EN	0x20000000
+/* Flash Timeout error enable */
+#define IFC_NAND_EVTER_EN_FTOER_EN	0x08000000
+/* Write Protect error enable */
+#define IFC_NAND_EVTER_EN_WPER_EN	0x04000000
+/* ECC error logging enable */
+#define IFC_NAND_EVTER_EN_ECCER_EN	0x02000000
+
+/*
+ * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
+ */
+/* Enable interrupt for operation complete */
+#define IFC_NAND_EVTER_INTR_OPCIR_EN		0x80000000
+/* Enable interrupt for Page read complete */
+#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN	0x20000000
+/* Enable interrupt for Flash timeout error */
+#define IFC_NAND_EVTER_INTR_FTOERIR_EN		0x08000000
+/* Enable interrupt for Write protect error */
+#define IFC_NAND_EVTER_INTR_WPERIR_EN		0x04000000
+/* Enable interrupt for ECC error*/
+#define IFC_NAND_EVTER_INTR_ECCERIR_EN		0x02000000
+
+/*
+ * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
+ */
+#define IFC_NAND_ERATTR0_MASK		0x0C080000
+/* Error on CS0-3 for NAND */
+#define IFC_NAND_ERATTR0_ERCS_CS0	0x00000000
+#define IFC_NAND_ERATTR0_ERCS_CS1	0x04000000
+#define IFC_NAND_ERATTR0_ERCS_CS2	0x08000000
+#define IFC_NAND_ERATTR0_ERCS_CS3	0x0C000000
+/* Transaction type of error Read/Write */
+#define IFC_NAND_ERATTR0_ERTTYPE_READ	0x00080000
+
+/*
+ * NAND Flash Status Register (NAND_FSR)
+ */
+/* First byte of data read from read status op */
+#define IFC_NAND_NFSR_RS0		0xFF000000
+/* Second byte of data read from read status op */
+#define IFC_NAND_NFSR_RS1		0x00FF0000
+
+/*
+ * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
+ */
+/* Number of ECC errors on sector n (n = 0-15) */
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT	24
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT	16
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT	8
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT	0
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT	24
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT	16
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT	8
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT	0
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT	24
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT	16
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT	8
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT	0
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT	24
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT	16
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT	8
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT	0
+
+/*
+ * NAND Control Register (NANDCR)
+ */
+#define IFC_NAND_NCR_FTOCNT_MASK	0x1E000000
+#define IFC_NAND_NCR_FTOCNT_SHIFT	25
+#define IFC_NAND_NCR_FTOCNT(n)	((LOG2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
+
+/*
+ * NAND_AUTOBOOT_TRGR
+ */
+/* Trigger RCW load */
+#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD	0x80000000
+/* Trigget Auto Boot */
+#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD	0x20000000
+
+/*
+ * NAND_MDR
+ */
+/* 1st read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA0		0xFF000000
+/* 2nd read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA1		0x00FF0000
+
+/*
+ * NOR Machine Specific Registers
+ */
+/*
+ * NOR Event and Error Status Register (NOR_EVTER_STAT)
+ */
+/* NOR Command Sequence Operation Complete */
+#define IFC_NOR_EVTER_STAT_OPC_NOR	0x80000000
+/* Write Protect Error */
+#define IFC_NOR_EVTER_STAT_WPER		0x04000000
+/* Command Sequence Timeout Error */
+#define IFC_NOR_EVTER_STAT_STOER	0x01000000
+
+/*
+ * NOR Event and Error Enable Register (NOR_EVTER_EN)
+ */
+/* NOR Command Seq complete event enable */
+#define IFC_NOR_EVTER_EN_OPCEN_NOR	0x80000000
+/* Write Protect Error Checking Enable */
+#define IFC_NOR_EVTER_EN_WPEREN		0x04000000
+/* Timeout Error Enable */
+#define IFC_NOR_EVTER_EN_STOEREN	0x01000000
+
+/*
+ * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
+ */
+/* Enable interrupt for OPC complete */
+#define IFC_NOR_EVTER_INTR_OPCEN_NOR	0x80000000
+/* Enable interrupt for write protect error */
+#define IFC_NOR_EVTER_INTR_WPEREN	0x04000000
+/* Enable interrupt for timeout error */
+#define IFC_NOR_EVTER_INTR_STOEREN	0x01000000
+
+/*
+ * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_NOR_ERATTR0_ERSRCID		0xFF000000
+/* AXI ID for error transation */
+#define IFC_NOR_ERATTR0_ERAID		0x000FF000
+/* Chip select corresponds to NOR error */
+#define IFC_NOR_ERATTR0_ERCS_CS0	0x00000000
+#define IFC_NOR_ERATTR0_ERCS_CS1	0x00000010
+#define IFC_NOR_ERATTR0_ERCS_CS2	0x00000020
+#define IFC_NOR_ERATTR0_ERCS_CS3	0x00000030
+/* Type of transaction read/write */
+#define IFC_NOR_ERATTR0_ERTYPE_READ	0x00000001
+
+/*
+ * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
+ */
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP	0x000F0000
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER	0x00000F00
+
+/*
+ * NOR Control Register (NORCR)
+ */
+#define IFC_NORCR_MASK			0x0F0F0000
+/* No. of Address/Data Phase */
+#define IFC_NORCR_NUM_PHASE_MASK	0x0F000000
+#define IFC_NORCR_NUM_PHASE_SHIFT	24
+#define IFC_NORCR_NUM_PHASE(n)	((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
+/* Sequence Timeout Count */
+#define IFC_NORCR_STOCNT_MASK		0x000F0000
+#define IFC_NORCR_STOCNT_SHIFT		16
+#define IFC_NORCR_STOCNT(n)	((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
+
+/*
+ * GPCM Machine specific registers
+ */
+/*
+ * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
+ */
+/* Timeout error */
+#define IFC_GPCM_EVTER_STAT_TOER	0x04000000
+/* Parity error */
+#define IFC_GPCM_EVTER_STAT_PER		0x01000000
+
+/*
+ * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
+ */
+/* Timeout error enable */
+#define IFC_GPCM_EVTER_EN_TOER_EN	0x04000000
+/* Parity error enable */
+#define IFC_GPCM_EVTER_EN_PER_EN	0x01000000
+
+/*
+ * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
+ */
+/* Enable Interrupt for timeout error */
+#define IFC_GPCM_EEIER_TOERIR_EN	0x04000000
+/* Enable Interrupt for Parity error */
+#define IFC_GPCM_EEIER_PERIR_EN		0x01000000
+
+/*
+ * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERSRCID	0xFF000000
+/* AXI ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERAID		0x000FF000
+/* Chip select corresponds to GPCM error */
+#define IFC_GPCM_ERATTR0_ERCS_CS0	0x00000000
+#define IFC_GPCM_ERATTR0_ERCS_CS1	0x00000040
+#define IFC_GPCM_ERATTR0_ERCS_CS2	0x00000080
+#define IFC_GPCM_ERATTR0_ERCS_CS3	0x000000C0
+/* Type of transaction read/Write */
+#define IFC_GPCM_ERATTR0_ERTYPE_READ	0x00000001
+
+/*
+ * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
+ */
+/* On which beat of address/data parity error is observed */
+#define IFC_GPCM_ERATTR2_PERR_BEAT		0x00000C00
+/* Parity Error on byte */
+#define IFC_GPCM_ERATTR2_PERR_BYTE		0x000000F0
+/* Parity Error reported in addr or data phase */
+#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE	0x00000001
+
+/*
+ * GPCM Status Register (GPCM_STAT)
+ */
+#define IFC_GPCM_STAT_BSY		0x80000000  /* GPCM is busy */
+
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+
+extern void print_ifc_regs(void);
+extern void init_early_memctl_regs(void);
+void init_final_memctl_regs(void);
+
+#define IFC_RREGS_4KOFFSET	(4*1024)
+#define IFC_RREGS_64KOFFSET	(64*1024)
+
+#define IFC_FCM_BASE_ADDR \
+	((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR)
+
+#define get_ifc_cspr_ext(i)	\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext))
+#define get_ifc_cspr(i)		\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr))
+#define get_ifc_csor_ext(i)	\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext))
+#define get_ifc_csor(i)		\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor))
+#define get_ifc_amask(i)	\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask))
+#define get_ifc_ftim(i, j)	\
+		(ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j]))
+#define set_ifc_cspr_ext(i, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
+#define set_ifc_cspr(i, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v))
+#define set_ifc_csor_ext(i, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v))
+#define set_ifc_csor(i, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v))
+#define set_ifc_amask(i, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v))
+#define set_ifc_ftim(i, j, v)	\
+		(ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v))
+
+enum ifc_chip_sel {
+	IFC_CS0,
+	IFC_CS1,
+	IFC_CS2,
+	IFC_CS3,
+	IFC_CS4,
+	IFC_CS5,
+	IFC_CS6,
+	IFC_CS7,
+};
+
+enum ifc_ftims {
+	IFC_FTIM0,
+	IFC_FTIM1,
+	IFC_FTIM2,
+	IFC_FTIM3,
+};
+
+/*
+ * IFC Controller NAND Machine registers
+ */
+struct fsl_ifc_nand {
+	u32 ncfgr;
+	u32 res1[0x4];
+	u32 nand_fcr0;
+	u32 nand_fcr1;
+	u32 res2[0x8];
+	u32 row0;
+	u32 res3;
+	u32 col0;
+	u32 res4;
+	u32 row1;
+	u32 res5;
+	u32 col1;
+	u32 res6;
+	u32 row2;
+	u32 res7;
+	u32 col2;
+	u32 res8;
+	u32 row3;
+	u32 res9;
+	u32 col3;
+	u32 res10[0x24];
+	u32 nand_fbcr;
+	u32 res11;
+	u32 nand_fir0;
+	u32 nand_fir1;
+	u32 nand_fir2;
+	u32 res12[0x10];
+	u32 nand_csel;
+	u32 res13;
+	u32 nandseq_strt;
+	u32 res14;
+	u32 nand_evter_stat;
+	u32 res15;
+	u32 pgrdcmpl_evt_stat;
+	u32 res16[0x2];
+	u32 nand_evter_en;
+	u32 res17[0x2];
+	u32 nand_evter_intr_en;
+	u32 nand_vol_addr_stat;
+	u32 res18;
+	u32 nand_erattr0;
+	u32 nand_erattr1;
+	u32 res19[0x10];
+	u32 nand_fsr;
+	u32 res20[0x1];
+	u32 nand_eccstat[8];
+	u32 res21[0x1c];
+	u32 nanndcr;
+	u32 res22[0x2];
+	u32 nand_autoboot_trgr;
+	u32 res23;
+	u32 nand_mdr;
+	u32 res24[0x1c];
+	u32 nand_dll_lowcfg0;
+	u32 nand_dll_lowcfg1;
+	u32 res25;
+	u32 nand_dll_lowstat;
+	u32 res26[0x3C];
+};
+
+/*
+ * IFC controller NOR Machine registers
+ */
+struct fsl_ifc_nor {
+	u32 nor_evter_stat;
+	u32 res1[0x2];
+	u32 nor_evter_en;
+	u32 res2[0x2];
+	u32 nor_evter_intr_en;
+	u32 res3[0x2];
+	u32 nor_erattr0;
+	u32 nor_erattr1;
+	u32 nor_erattr2;
+	u32 res4[0x4];
+	u32 norcr;
+	u32 res5[0xEF];
+};
+
+/*
+ * IFC controller GPCM Machine registers
+ */
+struct fsl_ifc_gpcm {
+	u32 gpcm_evter_stat;
+	u32 res1[0x2];
+	u32 gpcm_evter_en;
+	u32 res2[0x2];
+	u32 gpcm_evter_intr_en;
+	u32 res3[0x2];
+	u32 gpcm_erattr0;
+	u32 gpcm_erattr1;
+	u32 gpcm_erattr2;
+	u32 gpcm_stat;
+};
+
+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define IFC_CSPR_REG_LEN	148
+#define IFC_AMASK_REG_LEN	144
+#define IFC_CSOR_REG_LEN	144
+#define IFC_FTIM_REG_LEN	576
+
+#define IFC_CSPR_USED_LEN	sizeof(struct fsl_ifc_cspr) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_AMASK_USED_LEN	sizeof(struct fsl_ifc_amask) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_CSOR_USED_LEN	sizeof(struct fsl_ifc_csor) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_FTIM_USED_LEN	sizeof(struct fsl_ifc_ftim) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#else
+#error IFC BANK count not vaild
+#endif
+#else
+#error IFC BANK count not defined
+#endif
+
+struct fsl_ifc_cspr {
+	u32 cspr_ext;
+	u32 cspr;
+	u32 res;
+};
+
+struct fsl_ifc_amask {
+	u32 amask;
+	u32 res[0x2];
+};
+
+struct fsl_ifc_csor {
+	u32 csor;
+	u32 csor_ext;
+	u32 res;
+};
+
+struct fsl_ifc_ftim {
+	u32 ftim[4];
+	u32 res[0x8];
+};
+
+/*
+ * IFC Controller Global Registers
+ * FCM - Flash control machine
+ */
+
+struct fsl_ifc_fcm {
+	u32 ifc_rev;
+	u32 res1[0x2];
+	struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
+	struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
+	struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
+	struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
+	u32 rb_stat;
+	u32 rb_map;
+	u32 wp_map;
+	u32 ifc_gcr;
+	u32 res7[0x2];
+	u32 cm_evter_stat;
+	u32 res8[0x2];
+	u32 cm_evter_en;
+	u32 res9[0x2];
+	u32 cm_evter_intr_en;
+	u32 res10[0x2];
+	u32 cm_erattr0;
+	u32 cm_erattr1;
+	u32 res11[0x2];
+	u32 ifc_ccr;
+	u32 ifc_csr;
+	u32 ddr_ccr_low;
+};
+
+struct fsl_ifc_runtime {
+	struct fsl_ifc_nand ifc_nand;
+	struct fsl_ifc_nor ifc_nor;
+	struct fsl_ifc_gpcm ifc_gpcm;
+};
+
+struct fsl_ifc {
+	struct fsl_ifc_fcm *gregs;
+	struct fsl_ifc_runtime *rregs;
+};
+
+struct ifc_regs {
+	const char *name;
+	u32 pr;
+	u32 pr_ext;
+	u32 amask;
+	u32 or;
+	u32 ftim[4];
+	u32 or_ext;
+	u32 pr_final;
+	u32 amask_final;
+};
+
+struct ifc_regs_info {
+	struct ifc_regs *regs;
+	u32 cs_size;
+};
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#undef CSPR_MSEL_NOR
+#define CSPR_MSEL_NOR	CSPR_MSEL_GPCM
+#endif
+#endif /* CONFIG_FSL_IFC */
+
+#endif /* __ASSEMBLY__ */
+#endif /* __FSL_IFC_H */
diff --git a/include/fsl_immap.h b/include/fsl_immap.h
new file mode 100644
index 0000000..5297c0b
--- /dev/null
+++ b/include/fsl_immap.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_IMMAP_H
+#define __FSL_IMMAP_H
+/*
+ * DDR memory controller registers
+ * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx.
+ */
+struct ccsr_ddr {
+	u32	cs0_bnds;		/* Chip Select 0 Memory Bounds */
+	u8	res_04[4];
+	u32	cs1_bnds;		/* Chip Select 1 Memory Bounds */
+	u8	res_0c[4];
+	u32	cs2_bnds;		/* Chip Select 2 Memory Bounds */
+	u8	res_14[4];
+	u32	cs3_bnds;		/* Chip Select 3 Memory Bounds */
+	u8	res_1c[100];
+	u32	cs0_config;		/* Chip Select Configuration */
+	u32	cs1_config;		/* Chip Select Configuration */
+	u32	cs2_config;		/* Chip Select Configuration */
+	u32	cs3_config;		/* Chip Select Configuration */
+	u8	res_90[48];
+	u32	cs0_config_2;		/* Chip Select Configuration 2 */
+	u32	cs1_config_2;		/* Chip Select Configuration 2 */
+	u32	cs2_config_2;		/* Chip Select Configuration 2 */
+	u32	cs3_config_2;		/* Chip Select Configuration 2 */
+	u8	res_d0[48];
+	u32	timing_cfg_3;		/* SDRAM Timing Configuration 3 */
+	u32	timing_cfg_0;		/* SDRAM Timing Configuration 0 */
+	u32	timing_cfg_1;		/* SDRAM Timing Configuration 1 */
+	u32	timing_cfg_2;		/* SDRAM Timing Configuration 2 */
+	u32	sdram_cfg;		/* SDRAM Control Configuration */
+	u32	sdram_cfg_2;		/* SDRAM Control Configuration 2 */
+	u32	sdram_mode;		/* SDRAM Mode Configuration */
+	u32	sdram_mode_2;		/* SDRAM Mode Configuration 2 */
+	u32	sdram_md_cntl;		/* SDRAM Mode Control */
+	u32	sdram_interval;		/* SDRAM Interval Configuration */
+	u32	sdram_data_init;	/* SDRAM Data initialization */
+	u8	res_12c[4];
+	u32	sdram_clk_cntl;		/* SDRAM Clock Control */
+	u8	res_134[20];
+	u32	init_addr;		/* training init addr */
+	u32	init_ext_addr;		/* training init extended addr */
+	u8	res_150[16];
+	u32	timing_cfg_4;		/* SDRAM Timing Configuration 4 */
+	u32	timing_cfg_5;		/* SDRAM Timing Configuration 5 */
+	u32	timing_cfg_6;		/* SDRAM Timing Configuration 6 */
+	u32	timing_cfg_7;		/* SDRAM Timing Configuration 7 */
+	u32	ddr_zq_cntl;		/* ZQ calibration control*/
+	u32	ddr_wrlvl_cntl;		/* write leveling control*/
+	u8	reg_178[4];
+	u32	ddr_sr_cntr;		/* self refresh counter */
+	u32	ddr_sdram_rcw_1;	/* Control Words 1 */
+	u32	ddr_sdram_rcw_2;	/* Control Words 2 */
+	u8	reg_188[8];
+	u32	ddr_wrlvl_cntl_2;	/* write leveling control 2 */
+	u32	ddr_wrlvl_cntl_3;	/* write leveling control 3 */
+	u8	res_198[0x1a0-0x198];
+	u32	ddr_sdram_rcw_3;
+	u32	ddr_sdram_rcw_4;
+	u32	ddr_sdram_rcw_5;
+	u32	ddr_sdram_rcw_6;
+	u8	res_1b0[0x200-0x1b0];
+	u32	sdram_mode_3;		/* SDRAM Mode Configuration 3 */
+	u32	sdram_mode_4;		/* SDRAM Mode Configuration 4 */
+	u32	sdram_mode_5;		/* SDRAM Mode Configuration 5 */
+	u32	sdram_mode_6;		/* SDRAM Mode Configuration 6 */
+	u32	sdram_mode_7;		/* SDRAM Mode Configuration 7 */
+	u32	sdram_mode_8;		/* SDRAM Mode Configuration 8 */
+	u8	res_218[0x220-0x218];
+	u32	sdram_mode_9;		/* SDRAM Mode Configuration 9 */
+	u32	sdram_mode_10;		/* SDRAM Mode Configuration 10 */
+	u32	sdram_mode_11;		/* SDRAM Mode Configuration 11 */
+	u32	sdram_mode_12;		/* SDRAM Mode Configuration 12 */
+	u32	sdram_mode_13;		/* SDRAM Mode Configuration 13 */
+	u32	sdram_mode_14;		/* SDRAM Mode Configuration 14 */
+	u32	sdram_mode_15;		/* SDRAM Mode Configuration 15 */
+	u32	sdram_mode_16;		/* SDRAM Mode Configuration 16 */
+	u8	res_240[0x250-0x240];
+	u32	timing_cfg_8;		/* SDRAM Timing Configuration 8 */
+	u32	timing_cfg_9;		/* SDRAM Timing Configuration 9 */
+	u8	res_258[0x260-0x258];
+	u32	sdram_cfg_3;
+	u8	res_264[0x400-0x264];
+	u32	dq_map_0;
+	u32	dq_map_1;
+	u32	dq_map_2;
+	u32	dq_map_3;
+	u8	res_410[0xb20-0x410];
+	u32	ddr_dsr1;		/* Debug Status 1 */
+	u32	ddr_dsr2;		/* Debug Status 2 */
+	u32	ddr_cdr1;		/* Control Driver 1 */
+	u32	ddr_cdr2;		/* Control Driver 2 */
+	u8	res_b30[200];
+	u32	ip_rev1;		/* IP Block Revision 1 */
+	u32	ip_rev2;		/* IP Block Revision 2 */
+	u32	eor;			/* Enhanced Optimization Register */
+	u8	res_c04[252];
+	u32	mtcr;			/* Memory Test Control Register */
+	u8	res_d04[28];
+	u32	mtp1;			/* Memory Test Pattern 1 */
+	u32	mtp2;			/* Memory Test Pattern 2 */
+	u32	mtp3;			/* Memory Test Pattern 3 */
+	u32	mtp4;			/* Memory Test Pattern 4 */
+	u32	mtp5;			/* Memory Test Pattern 5 */
+	u32	mtp6;			/* Memory Test Pattern 6 */
+	u32	mtp7;			/* Memory Test Pattern 7 */
+	u32	mtp8;			/* Memory Test Pattern 8 */
+	u32	mtp9;			/* Memory Test Pattern 9 */
+	u32	mtp10;			/* Memory Test Pattern 10 */
+	u8	res_d48[184];
+	u32	data_err_inject_hi;	/* Data Path Err Injection Mask High */
+	u32	data_err_inject_lo;	/* Data Path Err Injection Mask Low */
+	u32	ecc_err_inject;		/* Data Path Err Injection Mask ECC */
+	u8	res_e0c[20];
+	u32	capture_data_hi;	/* Data Path Read Capture High */
+	u32	capture_data_lo;	/* Data Path Read Capture Low */
+	u32	capture_ecc;		/* Data Path Read Capture ECC */
+	u8	res_e2c[20];
+	u32	err_detect;		/* Error Detect */
+	u32	err_disable;		/* Error Disable */
+	u32	err_int_en;
+	u32	capture_attributes;	/* Error Attrs Capture */
+	u32	capture_address;	/* Error Addr Capture */
+	u32	capture_ext_address;	/* Error Extended Addr Capture */
+	u32	err_sbe;		/* Single-Bit ECC Error Management */
+	u8	res_e5c[164];
+	u32     debug[64];		/* debug_1 to debug_64 */
+};
+
+#ifdef CONFIG_SYS_FSL_HAS_CCI400
+#define CCI400_CTRLORD_TERM_BARRIER	0x00000008
+#define CCI400_CTRLORD_EN_BARRIER	0
+#define CCI400_SHAORD_NON_SHAREABLE	0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN	0x00000002
+#define CCI400_SNOOP_REQ_EN		0x00000001
+
+/* CCI-400 registers */
+struct ccsr_cci400 {
+	u32 ctrl_ord;			/* Control Override */
+	u32 spec_ctrl;			/* Speculation Control */
+	u32 secure_access;		/* Secure Access */
+	u32 status;			/* Status */
+	u32 impr_err;			/* Imprecise Error */
+	u8 res_14[0x100 - 0x14];
+	u32 pmcr;			/* Performance Monitor Control */
+	u8 res_104[0xfd0 - 0x104];
+	u32 pid[8];			/* Peripheral ID */
+	u32 cid[4];			/* Component ID */
+	struct {
+		u32 snoop_ctrl;		/* Snoop Control */
+		u32 sha_ord;		/* Shareable Override */
+		u8 res_1008[0x1100 - 0x1008];
+		u32 rc_qos_ord;		/* read channel QoS Value Override */
+		u32 wc_qos_ord;		/* read channel QoS Value Override */
+		u8 res_1108[0x110c - 0x1108];
+		u32 qos_ctrl;		/* QoS Control */
+		u32 max_ot;		/* Max OT */
+		u8 res_1114[0x1130 - 0x1114];
+		u32 target_lat;		/* Target Latency */
+		u32 latency_regu;	/* Latency Regulation */
+		u32 qos_range;		/* QoS Range */
+		u8 res_113c[0x2000 - 0x113c];
+	} slave[5];			/* Slave Interface */
+	u8 res_6000[0x9004 - 0x6000];
+	u32 cycle_counter;		/* Cycle counter */
+	u32 count_ctrl;			/* Count Control */
+	u32 overflow_status;		/* Overflow Flag Status */
+	u8 res_9010[0xa000 - 0x9010];
+	struct {
+		u32 event_select;	/* Event Select */
+		u32 event_count;	/* Event Count */
+		u32 counter_ctrl;	/* Counter Control */
+		u32 overflow_status;	/* Overflow Flag Status */
+		u8 res_a010[0xb000 - 0xa010];
+	} pcounter[4];			/* Performance Counter */
+	u8 res_e004[0x10000 - 0xe004];
+};
+#endif
+
+#endif /* __FSL_IMMAP_H */
diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
new file mode 100644
index 0000000..fc517d4
--- /dev/null
+++ b/include/fsl_lpuart.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ */
+
+#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8)
+struct lpuart_fsl_reg32 {
+	u32 verid;
+	u32 param;
+	u32 global;
+	u32 pincfg;
+	u32 baud;
+	u32 stat;
+	u32 ctrl;
+	u32 data;
+	u32 match;
+	u32 modir;
+	u32 fifo;
+	u32 water;
+};
+#else
+struct lpuart_fsl_reg32 {
+	u32 baud;
+	u32 stat;
+	u32 ctrl;
+	u32 data;
+	u32 match;
+	u32 modir;
+	u32 fifo;
+	u32 water;
+};
+#endif
+
+struct lpuart_fsl {
+	u8 ubdh;
+	u8 ubdl;
+	u8 uc1;
+	u8 uc2;
+	u8 us1;
+	u8 us2;
+	u8 uc3;
+	u8 ud;
+	u8 uma1;
+	u8 uma2;
+	u8 uc4;
+	u8 uc5;
+	u8 ued;
+	u8 umodem;
+	u8 uir;
+	u8 reserved;
+	u8 upfifo;
+	u8 ucfifo;
+	u8 usfifo;
+	u8 utwfifo;
+	u8 utcfifo;
+	u8 urwfifo;
+	u8 urcfifo;
+	u8 rsvd[28];
+};
+
+/* Used on i.MX7ULP */
+#define LPUART_BAUD_BOTHEDGE_MASK	(0x20000)
+#define LPUART_BAUD_OSR_MASK		(0x1F000000)
+#define LPUART_BAUD_OSR_SHIFT		(24)
+#define LPUART_BAUD_OSR(x)		((((uint32_t)(x)) << 24) & 0x1F000000)
+#define LPUART_BAUD_SBR_MASK		(0x1FFF)
+#define LPUART_BAUD_SBR_SHIFT		(0U)
+#define LPUART_BAUD_SBR(x)		(((uint32_t)(x)) & 0x1FFF)
+#define LPUART_BAUD_M10_MASK		(0x20000000U)
+#define LPUART_BAUD_SBNS_MASK		(0x2000U)
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
new file mode 100644
index 0000000..b87346c
--- /dev/null
+++ b/include/fsl_mdio.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
+ *	Jun-jie Zhang <b18070@freescale.com>
+ *	Mingkai Hu <Mingkai.hu@freescale.com>
+ */
+
+#ifndef __FSL_PHY_H__
+#define __FSL_PHY_H__
+
+#include <net.h>
+#include <miiphy.h>
+
+struct tsec_mii_mng {
+	u32 miimcfg;		/* MII management configuration reg */
+	u32 miimcom;		/* MII management command reg */
+	u32 miimadd;		/* MII management address reg */
+	u32 miimcon;		/* MII management control reg */
+	u32 miimstat;		/* MII management status reg  */
+	u32 miimind;		/* MII management indication reg */
+	u32 ifstat;		/* Interface Status Register */
+};
+
+int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
+
+/* PHY register offsets */
+#define PHY_EXT_PAGE_ACCESS	0x1f
+
+/* MII Management Configuration Register */
+#define MIIMCFG_RESET_MGMT		0x80000000
+#define MIIMCFG_MGMT_CLOCK_SELECT	0x00000007
+#define MIIMCFG_INIT_VALUE		0x00000003
+
+/* MII Management Command Register */
+#define MIIMCOM_READ_CYCLE	0x00000001
+#define MIIMCOM_SCAN_CYCLE	0x00000002
+
+/* MII Management Address Register */
+#define MIIMADD_PHY_ADDR_SHIFT	8
+
+/* MII Management Indicator Register */
+#define MIIMIND_BUSY		0x00000001
+#define MIIMIND_NOTVALID	0x00000004
+
+void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
+		int dev_addr, int reg, int value);
+int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
+		int dev_addr, int regnum);
+int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
+int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
+		u16 value);
+int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
+		int regnum, u16 value);
+int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
+		int regnum);
+
+struct fsl_pq_mdio_info {
+	struct tsec_mii_mng __iomem *regs;
+	char *name;
+};
+int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
+
+#endif /* __FSL_PHY_H__ */
diff --git a/include/fsl_memac.h b/include/fsl_memac.h
new file mode 100644
index 0000000..d067f15
--- /dev/null
+++ b/include/fsl_memac.h
@@ -0,0 +1,264 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *	Roy Zang <tie-fei.zang@freescale.com>
+ */
+
+#ifndef __MEMAC_H__
+#define __MEMAC_H__
+
+#include <phy.h>
+
+struct memac {
+	/* memac general control and status registers */
+	u32	res_0[2];
+	u32	command_config;	/* Control and configuration register */
+	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
+	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
+	u32	maxfrm;		/* Maximum frame length register */
+	u32	res_18[5];
+	u32	hashtable_ctrl;	/* Hash table control register */
+	u32	res_30[4];
+	u32	ievent;		/* Interrupt event register */
+	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
+	u32	res_48;
+	u32	imask;		/* interrupt mask register */
+	u32	res_50;
+	u32	cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
+	u32	cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
+	u32	rx_pause_status;	/* Receive pause status register */
+	u32	res_78[2];
+	u32	mac_addr[14];	/* MAC address */
+	u32	lpwake_timer;	/* EEE low power wakeup timer register */
+	u32	sleep_timer;	/* Transmit EEE Low Power Timer register */
+	u32	res_c0[8];
+	u32	statn_config;	/* Statistics configuration register */
+	u32	res_e4[7];
+
+	/* memac statistics counter registers */
+	u32	rx_eoct_l;	/* Rx ethernet octests lower */
+	u32	rx_eoct_u;	/* Rx ethernet octests upper */
+	u32	rx_oct_l;	/* Rx octests lower */
+	u32	rx_oct_u;	/* Rx octests upper */
+	u32	rx_align_err_l;	/* Rx alignment error lower */
+	u32	rx_align_err_u;	/* Rx alignment error upper */
+	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
+	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
+	u32	rx_frame_l;	/* Rx frame counter lower */
+	u32	rx_frame_u;	/* Rx frame counter upper */
+	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
+	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
+	u32	rx_vlan_l;	/* Rx VLAN frame lower */
+	u32	rx_vlan_u;	/* Rx VLAN frame upper */
+	u32	rx_err_l;	/* Rx frame error lower */
+	u32	rx_err_u;	/* Rx frame error upper */
+	u32	rx_uni_l;	/* Rx unicast frame lower */
+	u32	rx_uni_u;	/* Rx unicast frame upper */
+	u32	rx_multi_l;	/* Rx multicast frame lower */
+	u32	rx_multi_u;	/* Rx multicast frame upper */
+	u32	rx_brd_l;	/* Rx broadcast frame lower */
+	u32	rx_brd_u;	/* Rx broadcast frame upper */
+	u32	rx_drop_l;	/* Rx dropped packets lower */
+	u32	rx_drop_u;	/* Rx dropped packets upper */
+	u32	rx_pkt_l;	/* Rx packets lower */
+	u32	rx_pkt_u;	/* Rx packets upper */
+	u32	rx_undsz_l;	/* Rx undersized packet lower */
+	u32	rx_undsz_u;	/* Rx undersized packet upper */
+	u32	rx_64_l;	/* Rx 64 oct packet lower */
+	u32	rx_64_u;	/* Rx 64 oct packet upper */
+	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
+	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
+	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
+	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
+	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
+	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
+	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
+	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
+	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
+	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
+	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
+	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
+	u32	rx_oversz_l;	/* Rx oversized packet lower */
+	u32	rx_oversz_u;	/* Rx oversized packet upper */
+	u32	rx_jabber_l;	/* Rx Jabber packet lower */
+	u32	rx_jabber_u;	/* Rx Jabber packet upper */
+	u32	rx_frag_l;	/* Rx Fragment packet lower */
+	u32	rx_frag_u;	/* Rx Fragment packet upper */
+	u32	rx_cnp_l;	/* Rx control packet lower */
+	u32	rx_cnp_u;	/* Rx control packet upper */
+	u32	rx_drntp_l;	/* Rx dripped not truncated packet lower */
+	u32	rx_drntp_u;	/* Rx dripped not truncated packet upper */
+	u32	res_1d0[0xc];
+
+	u32	tx_eoct_l;	/* Tx ethernet octests lower */
+	u32	tx_eoct_u;	/* Tx ethernet octests upper */
+	u32	tx_oct_l;	/* Tx octests lower */
+	u32	tx_oct_u;	/* Tx octests upper */
+	u32	res_210[0x2];
+	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
+	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
+	u32	tx_frame_l;	/* Tx frame counter lower */
+	u32	tx_frame_u;	/* Tx frame counter upper */
+	u32	tx_frame_crc_err_l; /* Tx frame check sequence error lower */
+	u32	tx_frame_crc_err_u; /* Tx frame check sequence error upper */
+	u32	tx_vlan_l;	/* Tx VLAN frame lower */
+	u32	tx_vlan_u;	/* Tx VLAN frame upper */
+	u32	tx_frame_err_l;	/* Tx frame error lower */
+	u32	tx_frame_err_u;	/* Tx frame error upper */
+	u32	tx_uni_l;	/* Tx unicast frame lower */
+	u32	tx_uni_u;	/* Tx unicast frame upper */
+	u32	tx_multi_l;	/* Tx multicast frame lower */
+	u32	tx_multi_u;	/* Tx multicast frame upper */
+	u32	tx_brd_l;	/* Tx broadcast frame lower */
+	u32	tx_brd_u;	/* Tx broadcast frame upper */
+	u32	res_258[0x2];
+	u32	tx_pkt_l;	/* Tx packets lower */
+	u32	tx_pkt_u;	/* Tx packets upper */
+	u32	tx_undsz_l;	/* Tx undersized packet lower */
+	u32	tx_undsz_u;	/* Tx undersized packet upper */
+	u32	tx_64_l;	/* Tx 64 oct packet lower */
+	u32	tx_64_u;	/* Tx 64 oct packet upper */
+	u32	tx_127_l;	/* Tx 65 to 127 oct packet lower */
+	u32	tx_127_u;	/* Tx 65 to 127 oct packet upper */
+	u32	tx_255_l;	/* Tx 128 to 255 oct packet lower */
+	u32	tx_255_u;	/* Tx 128 to 255 oct packet upper */
+	u32	tx_511_l;	/* Tx 256 to 511 oct packet lower */
+	u32	tx_511_u;	/* Tx 256 to 511 oct packet upper */
+	u32	tx_1023_l;	/* Tx 512 to 1023 oct packet lower */
+	u32	tx_1023_u;	/* Tx 512 to 1023 oct packet upper */
+	u32	tx_1518_l;	/* Tx 1024 to 1518 oct packet lower */
+	u32	tx_1518_u;	/* Tx 1024 to 1518 oct packet upper */
+	u32	tx_1519_l;	/* Tx 1519 to max oct packet lower */
+	u32	tx_1519_u;	/* Tx 1519 to max oct packet upper */
+	u32	res_2a8[0x6];
+	u32	tx_cnp_l;	/* Tx control packet lower */
+	u32	tx_cnp_u;	/* Tx control packet upper */
+	u32	res_2c8[0xe];
+
+	/* Line interface control register */
+	u32 if_mode;		/* interface mode control */
+	u32 if_status;		/* interface status */
+	u32 res_308[0xe];
+
+	/* HiGig/2 Register */
+	u32 hg_config;	/* HiGig2 control and configuration */
+	u32 res_344[0x3];
+	u32 hg_pause_quanta;	/* HiGig2 pause quanta */
+	u32 res_354[0x3];
+	u32 hg_pause_thresh;	/* HiGig2 pause quanta threshold */
+	u32 res_364[0x3];
+	u32 hgrx_pause_status;	/* HiGig2 rx pause quanta status */
+	u32 hg_fifos_status;	/* HiGig2 fifos status */
+	u32 rhm;	/* Rx HiGig2 message counter register */
+	u32 thm;/* Tx HiGig2 message counter register */
+	u32 res_380[0x320];
+};
+
+/* COMMAND_CONFIG - command and configuration register */
+#define MEMAC_CMD_CFG_RX_EN		0x00000002 /* MAC Rx path enable */
+#define MEMAC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
+#define MEMAC_CMD_CFG_RXTX_EN	(MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
+#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */
+
+/* HASHTABLE_CTRL - Hashtable control register */
+#define HASHTABLE_CTRL_MCAST_EN	0x00000200 /* enable mulitcast Rx hash */
+#define HASHTABLE_CTRL_ADDR_MASK	0x000001ff
+
+/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
+#define TX_IPG_LENGTH_IPG_LEN_MASK	0x000003ff
+
+/* IMASK - interrupt mask register */
+#define IMASK_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event mask */
+#define IMASK_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion mask */
+#define IMASK_REM_FAULT		0x00004000 /* remote fault mask */
+#define IMASK_LOC_FAULT		0x00002000 /* local fault mask */
+#define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
+#define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
+#define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
+#define IMASK_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow mask */
+#define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
+#define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
+#define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
+#define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
+#define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
+#define IMASK_RX_LEN_ER		0x00000004 /* Rx payload length error mask */
+#define IMASK_RX_CRC_ER		0x00000002 /* Rx CRC error mask */
+#define IMASK_RX_ALIGN_ER	0x00000001 /* Rx alignment error mask */
+
+#define IMASK_MASK_ALL		0x00000000
+
+/* IEVENT - interrupt event register */
+#define IEVENT_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event */
+#define IEVENT_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion */
+#define IEVENT_REM_FAULT	0x00004000 /* remote fault */
+#define IEVENT_LOC_FAULT	0x00002000 /* local fault */
+#define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
+#define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
+#define IEVENT_TX_ER		0x00000200 /* Tx frame error */
+#define IEVENT_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow */
+#define IEVENT_RX_ECC_ER	0x00000080 /* Rx frame ECC error */
+#define IEVENT_RX_JAB_FRM	0x00000040 /* Rx jabber frame */
+#define IEVENT_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame */
+#define IEVENT_RX_RUNT_FRM	0x00000010 /* Rx runt frame */
+#define IEVENT_RX_FRAG_FRM	0x00000008 /* Rx fragment frame */
+#define IEVENT_RX_LEN_ER	0x00000004 /* Rx payload length error */
+#define IEVENT_RX_CRC_ER	0x00000002 /* Rx CRC error */
+#define IEVENT_RX_ALIGN_ER	0x00000001 /* Rx alignment error */
+
+#define IEVENT_CLEAR_ALL	0xffffffff
+
+/* IF_MODE - Interface Mode Register */
+#define IF_MODE_EN_AUTO	0x00008000 /* 1 - Enable automatic speed selection */
+#define IF_MODE_SETSP_100M	0x00000000 /* 00 - 100Mbps RGMII */
+#define IF_MODE_SETSP_10M	0x00002000 /* 01 - 10Mbps RGMII */
+#define IF_MODE_SETSP_1000M	0x00004000 /* 10 - 1000Mbps RGMII */
+#define IF_MODE_SETSP_MASK	0x00006000 /* setsp mask bits */
+#define IF_MODE_XGMII	0x00000000 /* 00- XGMII(10) interface mode */
+#define IF_MODE_GMII		0x00000002 /* 10- GMII interface mode */
+#define IF_MODE_MASK	0x00000003 /* mask for mode interface mode */
+#define IF_MODE_RG		0x00000004 /* 1- RGMII */
+#define IF_MODE_RM		0x00000008 /* 1- RGMII */
+
+#define IF_DEFAULT	(IF_GMII)
+
+/* Internal PHY Registers - SGMII */
+#define PHY_SGMII_CR_PHY_RESET      0x8000
+#define PHY_SGMII_CR_RESET_AN       0x0200
+#define PHY_SGMII_CR_DEF_VAL        0x1140
+#define PHY_SGMII_IF_SPEED_GIGABIT  0x0008
+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
+#define PHY_SGMII_IF_MODE_AN        0x0002
+#define PHY_SGMII_IF_MODE_SGMII     0x0001
+
+struct memac_mdio_controller {
+	u32	res0[0xc];
+	u32	mdio_stat;	/* MDIO configuration and status */
+	u32	mdio_ctl;	/* MDIO control */
+	u32	mdio_data;	/* MDIO data */
+	u32	mdio_addr;	/* MDIO address */
+};
+
+#define MDIO_STAT_CLKDIV(x)	(((x>>1) & 0xff) << 8)
+#define MDIO_STAT_BSY		(1 << 0)
+#define MDIO_STAT_RD_ER		(1 << 1)
+#define MDIO_STAT_PRE		(1 << 5)
+#define MDIO_STAT_ENC		(1 << 6)
+#define MDIO_STAT_HOLD_15_CLK	(7 << 2)
+#define MDIO_STAT_NEG		(1 << 23)
+
+#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
+#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
+#define MDIO_CTL_PRE_DIS	(1 << 10)
+#define MDIO_CTL_SCAN_EN	(1 << 11)
+#define MDIO_CTL_POST_INC	(1 << 14)
+#define MDIO_CTL_READ		(1 << 15)
+
+#define MDIO_DATA(x)		(x & 0xffff)
+#define MDIO_DATA_BSY		(1 << 31)
+
+struct fsl_enet_mac;
+
+void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs,
+		int max_rx_len);
+
+#endif
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
new file mode 100644
index 0000000..05fb41f
--- /dev/null
+++ b/include/fsl_mmdc.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef FSL_MMDC_H
+#define FSL_MMDC_H
+
+/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
+#define MPWLGCR_HW_WL_EN		(1 << 0)
+
+/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
+#define MPPDCMPR2_MPR_COMPARE_EN	(1 << 0)
+
+
+/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN	(1 << 28)
+
+/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
+#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN	(1 << 4)
+
+/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
+#define MMDC_MAPSR_PWR_SAV_CTRL_STAT	0x00001067
+
+/* MMDC Core Refresh Control Register (MMDC_MDREF) */
+#define MDREF_START_REFRESH	(1 << 0)
+
+/* MMDC Core Special Command Register (MDSCR) */
+#define CMD_ADDR_MSB_MR_OP(x)	(x << 24)
+#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
+#define MDSCR_DISABLE_CFG_REQ   (0 << 15)
+#define MDSCR_ENABLE_CON_REQ	(1 << 15)
+#define MDSCR_CON_ACK		(1 << 14)
+#define MDSCR_WL_EN		(1 << 9)
+#define	CMD_NORMAL		(0 << 4)
+#define	CMD_PRECHARGE		(1 << 4)
+#define	CMD_AUTO_REFRESH	(2 << 4)
+#define	CMD_LOAD_MODE_REG	(3 << 4)
+#define	CMD_ZQ_CALIBRATION	(4 << 4)
+#define	CMD_PRECHARGE_BANK_OPEN	(5 << 4)
+#define	CMD_MRR			(6 << 4)
+#define CMD_BANK_ADDR_0		0x0
+#define CMD_BANK_ADDR_1		0x1
+#define CMD_BANK_ADDR_2		0x2
+#define CMD_BANK_ADDR_3		0x3
+#define CMD_BANK_ADDR_4		0x4
+#define CMD_BANK_ADDR_5		0x5
+#define CMD_BANK_ADDR_6		0x6
+#define CMD_BANK_ADDR_7		0x7
+
+/* MMDC Core Control Register (MDCTL) */
+#define MDCTL_SDE0		(1 << 31)
+#define MDCTL_SDE1		(1 << 30)
+
+/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
+#define MPZQHWCTRL_ZQ_HW_FORCE	(1 << 16)
+
+/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
+#define MMDC_MPMUR0_FRC_MSR	(1 << 11)
+
+/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
+/* default 64 for a quarter cycle delay */
+#define MMDC_MPRDDLCTL_DEFAULT_DELAY	0x40404040
+
+/* MMDC Registers */
+struct mmdc_regs {
+	u32 mdctl;
+	u32 mdpdc;
+	u32 mdotc;
+	u32 mdcfg0;
+	u32 mdcfg1;
+	u32 mdcfg2;
+	u32 mdmisc;
+	u32 mdscr;
+	u32 mdref;
+	u32 res1[2];
+	u32 mdrwd;
+	u32 mdor;
+	u32 mdmrr;
+	u32 mdcfg3lp;
+	u32 mdmr4;
+	u32 mdasp;
+	u32 res2[239];
+	u32 maarcr;
+	u32 mapsr;
+	u32 maexidr0;
+	u32 maexidr1;
+	u32 madpcr0;
+	u32 madpcr1;
+	u32 madpsr0;
+	u32 madpsr1;
+	u32 madpsr2;
+	u32 madpsr3;
+	u32 madpsr4;
+	u32 madpsr5;
+	u32 masbs0;
+	u32 masbs1;
+	u32 res3[2];
+	u32 magenp;
+	u32 res4[239];
+	u32 mpzqhwctrl;
+	u32 mpzqswctrl;
+	u32 mpwlgcr;
+	u32 mpwldectrl0;
+	u32 mpwldectrl1;
+	u32 mpwldlst;
+	u32 mpodtctrl;
+	u32 mprddqby0dl;
+	u32 mprddqby1dl;
+	u32 mprddqby2dl;
+	u32 mprddqby3dl;
+	u32 mpwrdqby0dl;
+	u32 mpwrdqby1dl;
+	u32 mpwrdqby2dl;
+	u32 mpwrdqby3dl;
+	u32 mpdgctrl0;
+	u32 mpdgctrl1;
+	u32 mpdgdlst0;
+	u32 mprddlctl;
+	u32 mprddlst;
+	u32 mpwrdlctl;
+	u32 mpwrdlst;
+	u32 mpsdctrl;
+	u32 mpzqlp2ctl;
+	u32 mprddlhwctl;
+	u32 mpwrdlhwctl;
+	u32 mprddlhwst0;
+	u32 mprddlhwst1;
+	u32 mpwrdlhwst0;
+	u32 mpwrdlhwst1;
+	u32 mpwlhwerr;
+	u32 mpdghwst0;
+	u32 mpdghwst1;
+	u32 mpdghwst2;
+	u32 mpdghwst3;
+	u32 mppdcmpr1;
+	u32 mppdcmpr2;
+	u32 mpswdar0;
+	u32 mpswdrdr0;
+	u32 mpswdrdr1;
+	u32 mpswdrdr2;
+	u32 mpswdrdr3;
+	u32 mpswdrdr4;
+	u32 mpswdrdr5;
+	u32 mpswdrdr6;
+	u32 mpswdrdr7;
+	u32 mpmur0;
+	u32 mpwrcadl;
+	u32 mpdccr;
+};
+
+struct fsl_mmdc_info {
+	u32 mdctl;
+	u32 mdpdc;
+	u32 mdotc;
+	u32 mdcfg0;
+	u32 mdcfg1;
+	u32 mdcfg2;
+	u32 mdmisc;
+	u32 mdref;
+	u32 mdrwd;
+	u32 mdor;
+	u32 mdasp;
+	u32 mpodtctrl;
+	u32 mpzqhwctrl;
+	u32 mprddlctl;
+};
+
+void mmdc_init(const struct fsl_mmdc_info *);
+
+#endif /* FSL_MMDC_H */
diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h
new file mode 100644
index 0000000..132db81
--- /dev/null
+++ b/include/fsl_pmic.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_PMIC_H__
+#define __FSL_PMIC_H__
+
+/*
+ * The registers of different PMIC has the same meaning
+ * but the bit positions of the fields can differ or
+ * some fields has a meaning only on some devices.
+ * You have to check with the internal SPI bitmap
+ * (see Freescale Documentation) to set the registers
+ * for the device you are using
+ */
+enum {
+	REG_INT_STATUS0 = 0,
+	REG_INT_MASK0,
+	REG_INT_SENSE0,
+	REG_INT_STATUS1,
+	REG_INT_MASK1,
+	REG_INT_SENSE1,
+	REG_PU_MODE_S,
+	REG_IDENTIFICATION,
+	REG_UNUSED0,
+	REG_ACC0,
+	REG_ACC1,		/*10 */
+	REG_UNUSED1,
+	REG_UNUSED2,
+	REG_POWER_CTL0,
+	REG_POWER_CTL1,
+	REG_POWER_CTL2,
+	REG_REGEN_ASSIGN,
+	REG_UNUSED3,
+	REG_MEM_A,
+	REG_MEM_B,
+	REG_RTC_TIME,		/*20 */
+	REG_RTC_ALARM,
+	REG_RTC_DAY,
+	REG_RTC_DAY_ALARM,
+	REG_SW_0,
+	REG_SW_1,
+	REG_SW_2,
+	REG_SW_3,
+	REG_SW_4,
+	REG_SW_5,
+	REG_SETTING_0,		/*30 */
+	REG_SETTING_1,
+	REG_MODE_0,
+	REG_MODE_1,
+	REG_POWER_MISC,
+	REG_UNUSED4,
+	REG_UNUSED5,
+	REG_UNUSED6,
+	REG_UNUSED7,
+	REG_UNUSED8,
+	REG_UNUSED9,		/*40 */
+	REG_UNUSED10,
+	REG_UNUSED11,
+	REG_ADC0,
+	REG_ADC1,
+	REG_ADC2,
+	REG_ADC3,
+	REG_ADC4,
+	REG_CHARGE,
+	REG_USB0,
+	REG_USB1,		/*50 */
+	REG_LED_CTL0,
+	REG_LED_CTL1,
+	REG_LED_CTL2,
+	REG_LED_CTL3,
+	REG_UNUSED12,
+	REG_UNUSED13,
+	REG_TRIM0,
+	REG_TRIM1,
+	REG_TEST0,
+	REG_TEST1,		/*60 */
+	REG_TEST2,
+	REG_TEST3,
+	REG_TEST4,
+	PMIC_NUM_OF_REGS,
+};
+
+/* REG_POWER_MISC */
+#define GPO1EN		(1 << 6)
+#define GPO1STBY	(1 << 7)
+#define GPO2EN		(1 << 8)
+#define GPO2STBY	(1 << 9)
+#define GPO3EN		(1 << 10)
+#define GPO3STBY	(1 << 11)
+#define GPO4EN		(1 << 12)
+#define GPO4STBY	(1 << 13)
+#define PWGT1SPIEN	(1 << 15)
+#define PWGT2SPIEN	(1 << 16)
+#define PWUP		(1 << 21)
+
+/* Power Control 0 */
+#define COINCHEN	(1 << 23)
+#define BATTDETEN	(1 << 19)
+
+/* Interrupt status 1 */
+#define RTCRSTI		(1 << 7)
+
+/* MC34708 Definitions */
+#define SWx_VOLT_MASK_MC34708	0x3F
+#define SWx_1_110V_MC34708	0x24
+#define SWx_1_250V_MC34708	0x30
+#define SWx_1_300V_MC34708	0x34
+#define TIMER_MASK_MC34708	0x300
+#define TIMER_4S_MC34708	0x100
+#define VUSBSEL_MC34708		(1 << 2)
+#define VUSBEN_MC34708		(1 << 3)
+#define SWBST_CTRL		31
+#define SWBST_AUTO		0x8
+
+#define MC34708_REG_SW12_OPMODE	28
+
+#define MC34708_SW1AMODE_MASK	0x00000f
+#define MC34708_SW1AMHMODE	0x000010
+#define MC34708_SW1AUOMODE	0x000020
+#define MC34708_SW1DVSSPEED	0x0000c0
+#define MC34708_SW2MODE_MASK	0x03c000
+#define MC34708_SW2MHMODE	0x040000
+#define MC34708_SW2UOMODE	0x080000
+#define MC34708_SW2DVSSPEED	0x300000
+#define MC34708_PLLEN		0x400000
+#define MC34708_PLLX		0x800000
+
+#define MC34708_REG_SW345_OPMODE	29
+
+#define MC34708_SW3MODE_MASK	0x00000f
+#define MC34708_SW3MHMODE	0x000010
+#define MC34708_SW3UOMODE	0x000020
+#define MC34708_SW4AMODE_MASK	0x0003c0
+#define MC34708_SW4AMHMODE	0x000400
+#define MC34708_SW4AUOMODE	0x000800
+#define MC34708_SW4BMODE_MASK	0x00f000
+#define MC34708_SW4BMHMODE	0x010000
+#define MC34708_SW4BUOMODE	0x020000
+#define MC34708_SW5MODE_MASK	0x3c0000
+#define MC34708_SW5MHMODE	0x400000
+#define MC34708_SW5UOMODE	0x800000
+
+#define SW_MODE_OFFOFF		0x00
+#define SW_MODE_PWMOFF		0x01
+#define SW_MODE_PFMOFF		0x03
+#define SW_MODE_APSOFF		0x04
+#define SW_MODE_PWMPWM		0x05
+#define SW_MODE_PWMAPS		0x06
+#define SW_MODE_APSAPS		0x08
+#define SW_MODE_APSPFM		0x0c
+#define SW_MODE_PWMPFM		0x0d
+#define SW_MODE_PFMPFM		0x0f
+
+#define MC34708_TRANSFER_SIZE 3
+#endif
diff --git a/include/fsl_qbman.h b/include/fsl_qbman.h
new file mode 100644
index 0000000..4687eb9
--- /dev/null
+++ b/include/fsl_qbman.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef __FSL_QBMAN_H__
+#define __FSL_QBMAN_H__
+void fdt_fixup_qportals(void *blob);
+void fdt_fixup_bportals(void *blob);
+void inhibit_portals(void __iomem *addr, int max_portals,
+		     int arch_max_portals, int portal_cinh_size);
+void setup_qbman_portals(void);
+
+struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	u8	res0[0x200];
+#else
+	struct {
+		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
+		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
+		u32	res;
+		u32	qcsp_dd_cfg;	/* 0xc - SW Portal Dynamic Debug cfg */
+	} qcsp[32];
+#endif
+	/* Not actually reserved, but irrelevant to u-boot */
+	u8	res[0xbf8 - 0x200];
+	u32	ip_rev_1;
+	u32	ip_rev_2;
+	u32	fqd_bare;	/* FQD Extended Base Addr Register */
+	u32	fqd_bar;	/* FQD Base Addr Register */
+	u8	res1[0x8];
+	u32	fqd_ar;		/* FQD Attributes Register */
+	u8	res2[0xc];
+	u32	pfdr_bare;	/* PFDR Extended Base Addr Register */
+	u32	pfdr_bar;	/* PFDR Base Addr Register */
+	u8	res3[0x8];
+	u32	pfdr_ar;	/* PFDR Attributes Register */
+	u8	res4[0x4c];
+	u32	qcsp_bare;	/* QCSP Extended Base Addr Register */
+	u32	qcsp_bar;	/* QCSP Base Addr Register */
+	u8	res5[0x78];
+	u32	ci_sched_cfg;	/* Initiator Scheduling Configuration */
+	u32	srcidr;		/* Source ID Register */
+	u32	liodnr;		/* LIODN Register */
+	u8	res6[4];
+	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
+	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
+	u8	res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	struct {
+		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
+		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
+		u32	res;
+		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg*/
+	} qcsp[50];
+#endif
+};
+
+struct ccsr_bman {
+	/* Not actually reserved, but irrelevant to u-boot */
+	u8	res[0xbf8];
+	u32	ip_rev_1;
+	u32	ip_rev_2;
+	u32	fbpr_bare;	/* FBPR Extended Base Addr Register */
+	u32	fbpr_bar;	/* FBPR Base Addr Register */
+	u8	res1[0x8];
+	u32	fbpr_ar;	/* FBPR Attributes Register */
+	u8	res2[0xf0];
+	u32	srcidr;		/* Source ID Register */
+	u32	liodnr;		/* LIODN Register */
+	u8	res7[0x2f4];
+};
+
+#endif /* __FSL_QBMAN_H__ */
diff --git a/include/fsl_qe.h b/include/fsl_qe.h
new file mode 100644
index 0000000..d4eba82
--- /dev/null
+++ b/include/fsl_qe.h
@@ -0,0 +1,298 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ */
+
+#ifndef __QE_H__
+#define __QE_H__
+
+#include "common.h"
+#ifdef CONFIG_U_QE
+#include <linux/immap_qe.h>
+#endif
+
+#define QE_NUM_OF_BRGS	16
+#define UCC_MAX_NUM	8
+
+#define QE_DATAONLY_BASE	0
+#define QE_DATAONLY_SIZE	(QE_MURAM_SIZE - QE_DATAONLY_BASE)
+
+/* QE threads SNUM
+*/
+typedef enum qe_snum_state {
+	QE_SNUM_STATE_USED,   /* used */
+	QE_SNUM_STATE_FREE    /* free */
+} qe_snum_state_e;
+
+typedef struct qe_snum {
+	u8		num;   /* snum	*/
+	qe_snum_state_e	state; /* state */
+} qe_snum_t;
+
+/* QE RISC allocation
+*/
+#define	QE_RISC_ALLOCATION_RISC1	0x1  /* RISC 1 */
+#define	QE_RISC_ALLOCATION_RISC2	0x2  /* RISC 2 */
+#define	QE_RISC_ALLOCATION_RISC3	0x4  /* RISC 3 */
+#define	QE_RISC_ALLOCATION_RISC4	0x8  /* RISC 4 */
+#define	QE_RISC_ALLOCATION_RISC1_AND_RISC2 	(QE_RISC_ALLOCATION_RISC1 | \
+						 QE_RISC_ALLOCATION_RISC2)
+#define	QE_RISC_ALLOCATION_FOUR_RISCS	(QE_RISC_ALLOCATION_RISC1 | \
+					 QE_RISC_ALLOCATION_RISC2 | \
+					 QE_RISC_ALLOCATION_RISC3 | \
+					 QE_RISC_ALLOCATION_RISC4)
+
+/* QE CECR commands for UCC fast.
+*/
+#define QE_CR_FLG			0x00010000
+#define QE_RESET			0x80000000
+#define QE_INIT_TX_RX			0x00000000
+#define QE_INIT_RX			0x00000001
+#define QE_INIT_TX			0x00000002
+#define QE_ENTER_HUNT_MODE		0x00000003
+#define QE_STOP_TX			0x00000004
+#define QE_GRACEFUL_STOP_TX		0x00000005
+#define QE_RESTART_TX			0x00000006
+#define QE_SWITCH_COMMAND		0x00000007
+#define QE_SET_GROUP_ADDRESS		0x00000008
+#define QE_INSERT_CELL			0x00000009
+#define QE_ATM_TRANSMIT			0x0000000a
+#define QE_CELL_POOL_GET		0x0000000b
+#define QE_CELL_POOL_PUT		0x0000000c
+#define QE_IMA_HOST_CMD			0x0000000d
+#define QE_ATM_MULTI_THREAD_INIT	0x00000011
+#define QE_ASSIGN_PAGE			0x00000012
+#define QE_START_FLOW_CONTROL		0x00000014
+#define QE_STOP_FLOW_CONTROL		0x00000015
+#define QE_ASSIGN_PAGE_TO_DEVICE	0x00000016
+#define QE_GRACEFUL_STOP_RX		0x0000001a
+#define QE_RESTART_RX			0x0000001b
+
+/* QE CECR Sub Block Code - sub block code of QE command.
+*/
+#define QE_CR_SUBBLOCK_INVALID		0x00000000
+#define QE_CR_SUBBLOCK_USB		0x03200000
+#define QE_CR_SUBBLOCK_UCCFAST1		0x02000000
+#define QE_CR_SUBBLOCK_UCCFAST2		0x02200000
+#define QE_CR_SUBBLOCK_UCCFAST3		0x02400000
+#define QE_CR_SUBBLOCK_UCCFAST4		0x02600000
+#define QE_CR_SUBBLOCK_UCCFAST5		0x02800000
+#define QE_CR_SUBBLOCK_UCCFAST6		0x02a00000
+#define QE_CR_SUBBLOCK_UCCFAST7		0x02c00000
+#define QE_CR_SUBBLOCK_UCCFAST8		0x02e00000
+#define QE_CR_SUBBLOCK_UCCSLOW1		0x00000000
+#define QE_CR_SUBBLOCK_UCCSLOW2		0x00200000
+#define QE_CR_SUBBLOCK_UCCSLOW3		0x00400000
+#define QE_CR_SUBBLOCK_UCCSLOW4		0x00600000
+#define QE_CR_SUBBLOCK_UCCSLOW5		0x00800000
+#define QE_CR_SUBBLOCK_UCCSLOW6		0x00a00000
+#define QE_CR_SUBBLOCK_UCCSLOW7		0x00c00000
+#define QE_CR_SUBBLOCK_UCCSLOW8		0x00e00000
+#define QE_CR_SUBBLOCK_MCC1		0x03800000
+#define QE_CR_SUBBLOCK_MCC2		0x03a00000
+#define QE_CR_SUBBLOCK_MCC3		0x03000000
+#define QE_CR_SUBBLOCK_IDMA1		0x02800000
+#define QE_CR_SUBBLOCK_IDMA2		0x02a00000
+#define QE_CR_SUBBLOCK_IDMA3		0x02c00000
+#define QE_CR_SUBBLOCK_IDMA4		0x02e00000
+#define QE_CR_SUBBLOCK_HPAC		0x01e00000
+#define QE_CR_SUBBLOCK_SPI1		0x01400000
+#define QE_CR_SUBBLOCK_SPI2		0x01600000
+#define QE_CR_SUBBLOCK_RAND		0x01c00000
+#define QE_CR_SUBBLOCK_TIMER		0x01e00000
+#define QE_CR_SUBBLOCK_GENERAL		0x03c00000
+
+/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
+*/
+#define QE_CR_PROTOCOL_UNSPECIFIED	0x00 /* For all other protocols */
+#define QE_CR_PROTOCOL_HDLC_TRANSPARENT	0x00
+#define QE_CR_PROTOCOL_ATM_POS		0x0A
+#define QE_CR_PROTOCOL_ETHERNET		0x0C
+#define QE_CR_PROTOCOL_L2_SWITCH	0x0D
+#define QE_CR_PROTOCOL_SHIFT		6
+
+/* QE ASSIGN PAGE command
+*/
+#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT	17
+
+/* Communication Direction.
+*/
+typedef enum comm_dir {
+	COMM_DIR_NONE		= 0,
+	COMM_DIR_RX		= 1,
+	COMM_DIR_TX		= 2,
+	COMM_DIR_RX_AND_TX	= 3
+} comm_dir_e;
+
+/* Clocks and BRG's
+*/
+typedef enum qe_clock {
+	QE_CLK_NONE = 0,
+	QE_BRG1,     /* Baud Rate Generator  1 */
+	QE_BRG2,     /* Baud Rate Generator  2 */
+	QE_BRG3,     /* Baud Rate Generator  3 */
+	QE_BRG4,     /* Baud Rate Generator  4 */
+	QE_BRG5,     /* Baud Rate Generator  5 */
+	QE_BRG6,     /* Baud Rate Generator  6 */
+	QE_BRG7,     /* Baud Rate Generator  7 */
+	QE_BRG8,     /* Baud Rate Generator  8 */
+	QE_BRG9,     /* Baud Rate Generator  9 */
+	QE_BRG10,    /* Baud Rate Generator 10 */
+	QE_BRG11,    /* Baud Rate Generator 11 */
+	QE_BRG12,    /* Baud Rate Generator 12 */
+	QE_BRG13,    /* Baud Rate Generator 13 */
+	QE_BRG14,    /* Baud Rate Generator 14 */
+	QE_BRG15,    /* Baud Rate Generator 15 */
+	QE_BRG16,    /* Baud Rate Generator 16 */
+	QE_CLK1,     /* Clock  1	       */
+	QE_CLK2,     /* Clock  2	       */
+	QE_CLK3,     /* Clock  3	       */
+	QE_CLK4,     /* Clock  4	       */
+	QE_CLK5,     /* Clock  5	       */
+	QE_CLK6,     /* Clock  6	       */
+	QE_CLK7,     /* Clock  7	       */
+	QE_CLK8,     /* Clock  8	       */
+	QE_CLK9,     /* Clock  9	       */
+	QE_CLK10,    /* Clock 10	       */
+	QE_CLK11,    /* Clock 11	       */
+	QE_CLK12,    /* Clock 12	       */
+	QE_CLK13,    /* Clock 13	       */
+	QE_CLK14,    /* Clock 14	       */
+	QE_CLK15,    /* Clock 15	       */
+	QE_CLK16,    /* Clock 16	       */
+	QE_CLK17,    /* Clock 17	       */
+	QE_CLK18,    /* Clock 18	       */
+	QE_CLK19,    /* Clock 19	       */
+	QE_CLK20,    /* Clock 20	       */
+	QE_CLK21,    /* Clock 21	       */
+	QE_CLK22,    /* Clock 22	       */
+	QE_CLK23,    /* Clock 23	       */
+	QE_CLK24,    /* Clock 24	       */
+	QE_CLK_DUMMY
+} qe_clock_e;
+
+/* QE CMXGCR register
+*/
+#define QE_CMXGCR_MII_ENET_MNG_MASK	0x00007000
+#define QE_CMXGCR_MII_ENET_MNG_SHIFT	12
+
+/* QE CMXUCR registers
+ */
+#define QE_CMXUCR_TX_CLK_SRC_MASK	0x0000000F
+
+/* QE BRG configuration register
+*/
+#define QE_BRGC_ENABLE			0x00010000
+#define QE_BRGC_DIVISOR_SHIFT		1
+#define QE_BRGC_DIVISOR_MAX		0xFFF
+#define QE_BRGC_DIV16			1
+
+/* QE SDMA registers
+*/
+#define QE_SDSR_BER1			0x02000000
+#define QE_SDSR_BER2			0x01000000
+
+#define QE_SDMR_GLB_1_MSK		0x80000000
+#define QE_SDMR_ADR_SEL			0x20000000
+#define QE_SDMR_BER1_MSK		0x02000000
+#define QE_SDMR_BER2_MSK		0x01000000
+#define QE_SDMR_EB1_MSK			0x00800000
+#define QE_SDMR_ER1_MSK			0x00080000
+#define QE_SDMR_ER2_MSK			0x00040000
+#define QE_SDMR_CEN_MASK		0x0000E000
+#define QE_SDMR_SBER_1			0x00000200
+#define QE_SDMR_SBER_2			0x00000200
+#define QE_SDMR_EB1_PR_MASK		0x000000C0
+#define QE_SDMR_ER1_PR			0x00000008
+
+#define QE_SDMR_CEN_SHIFT		13
+#define QE_SDMR_EB1_PR_SHIFT		6
+
+#define QE_SDTM_MSNUM_SHIFT		24
+
+#define QE_SDEBCR_BA_MASK		0x01FFFFFF
+
+/* Communication Processor */
+#define QE_CP_CERCR_MEE		0x8000	/* Multi-user RAM ECC enable */
+#define QE_CP_CERCR_IEE		0x4000	/* Instruction RAM ECC enable */
+#define QE_CP_CERCR_CIR		0x0800	/* Common instruction RAM */
+
+/* I-RAM */
+#define QE_IRAM_IADD_AIE	0x80000000	/* Auto Increment Enable */
+#define QE_IRAM_IADD_BADDR	0x00080000	/* Base Address */
+#define QE_IRAM_READY		0x80000000
+
+/* Structure that defines QE firmware binary files.
+ *
+ * See doc/README.qe_firmware for a description of these fields.
+ */
+struct qe_firmware {
+	struct qe_header {
+		u32 length;	/* Length of the entire structure, in bytes */
+		u8 magic[3];	/* Set to { 'Q', 'E', 'F' } */
+		u8 version;	/* Version of this layout. First ver is '1' */
+	} header;
+	u8 id[62];		/* Null-terminated identifier string */
+	u8 split;		/* 0 = shared I-RAM, 1 = split I-RAM */
+	u8 count;		/* Number of microcode[] structures */
+	struct {
+		u16 model;	/* The SOC model  */
+		u8 major;	/* The SOC revision major */
+		u8 minor;	/* The SOC revision minor */
+	} __attribute__ ((packed)) soc;
+	u8 padding[4];		/* Reserved, for alignment */
+	u64 extended_modes;	/* Extended modes */
+	u32 vtraps[8];		/* Virtual trap addresses */
+	u8 reserved[4];		/* Reserved, for future expansion */
+	struct qe_microcode {
+		u8 id[32];	/* Null-terminated identifier */
+		u32 traps[16];	/* Trap addresses, 0 == ignore */
+		u32 eccr;	/* The value for the ECCR register */
+		u32 iram_offset;/* Offset into I-RAM for the code */
+		u32 count;	/* Number of 32-bit words of the code */
+		u32 code_offset;/* Offset of the actual microcode */
+		u8 major;	/* The microcode version major */
+		u8 minor;	/* The microcode version minor */
+		u8 revision;	/* The microcode version revision */
+		u8 padding;	/* Reserved, for alignment */
+		u8 reserved[4];	/* Reserved, for future expansion */
+	} __attribute__ ((packed)) microcode[1];
+	/* All microcode binaries should be located here */
+	/* CRC32 should be located here, after the microcode binaries */
+} __attribute__ ((packed));
+
+struct qe_firmware_info {
+	char id[64];		/* Firmware name */
+	u32 vtraps[8];		/* Virtual trap addresses */
+	u64 extended_modes;	/* Extended modes */
+};
+
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
+void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
+uint qe_muram_alloc(uint size, uint align);
+void *qe_muram_addr(uint offset);
+int qe_get_snum(void);
+void qe_put_snum(u8 snum);
+void qe_init(uint qe_base);
+void qe_reset(void);
+void qe_assign_page(uint snum, uint para_ram_base);
+int qe_set_brg(uint brg, uint rate);
+int qe_set_mii_clk_src(int ucc_num);
+int qe_upload_firmware(const struct qe_firmware *firmware);
+struct qe_firmware_info *qe_get_firmware_info(void);
+void ft_qe_setup(void *blob);
+void qe_init(uint qe_base);
+void qe_reset(void);
+
+#ifdef CONFIG_U_QE
+void u_qe_init(void);
+int u_qe_upload_firmware(const struct qe_firmware *firmware);
+void u_qe_resume(void);
+int u_qe_firmware_resume(const struct qe_firmware *firmware,
+			 qe_map_t *qe_immrr);
+#endif
+
+#endif /* __QE_H__ */
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
new file mode 100644
index 0000000..be08a2b
--- /dev/null
+++ b/include/fsl_sec.h
@@ -0,0 +1,322 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_SEC_H
+#define __FSL_SEC_H
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYS_FSL_SEC_LE
+#define sec_in32(a)       in_le32(a)
+#define sec_out32(a, v)   out_le32(a, v)
+#define sec_in16(a)       in_le16(a)
+#define sec_clrbits32     clrbits_le32
+#define sec_setbits32     setbits_le32
+#elif defined(CONFIG_SYS_FSL_SEC_BE)
+#define sec_in32(a)       in_be32(a)
+#define sec_out32(a, v)   out_be32(a, v)
+#define sec_in16(a)       in_be16(a)
+#define sec_clrbits32     clrbits_be32
+#define sec_setbits32     setbits_be32
+#elif defined(CONFIG_SYS_FSL_HAS_SEC)
+#error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
+#endif
+
+/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+/* RNG4 TRNG test registers */
+struct rng4tst {
+#define RTMCTL_PRGM 0x00010000	/* 1 -> program mode, 0 -> run mode */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC     0 /* use von Neumann data in
+						    both entropy shifter and
+						    statistical checker */
+#define RTMCTL_SAMP_MODE_RAW_ES_SC             1 /* use raw data in both
+						    entropy shifter and
+						    statistical checker */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
+						    entropy shifter, raw data
+						    in statistical checker */
+#define RTMCTL_SAMP_MODE_INVALID               3 /* invalid combination */
+	u32 rtmctl;		/* misc. control register */
+	u32 rtscmisc;		/* statistical check misc. register */
+	u32 rtpkrrng;		/* poker range register */
+#define RTSDCTL_ENT_DLY_MIN	3200
+#define RTSDCTL_ENT_DLY_MAX	12800
+	union {
+		u32 rtpkrmax;	/* PRGM=1: poker max. limit register */
+		u32 rtpkrsq;	/* PRGM=0: poker square calc. result register */
+	};
+#define RTSDCTL_ENT_DLY_SHIFT 16
+#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
+	u32 rtsdctl;		/* seed control register */
+	union {
+		u32 rtsblim;	/* PRGM=1: sparse bit limit register */
+		u32 rttotsam;	/* PRGM=0: total samples register */
+	};
+	u32 rtfreqmin;		/* frequency count min. limit register */
+#define RTFRQMAX_DISABLE       (1 << 20)
+	union {
+		u32 rtfreqmax;	/* PRGM=1: freq. count max. limit register */
+		u32 rtfreqcnt;	/* PRGM=0: freq. count register */
+	};
+	u32 rsvd1[40];
+#define RNG_STATE0_HANDLE_INSTANTIATED	0x00000001
+#define RNG_STATE1_HANDLE_INSTANTIATED	0x00000002
+#define RNG_STATE_HANDLE_MASK	\
+	(RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
+	u32 rdsta;		/*RNG DRNG Status Register*/
+	u32 rsvd2[15];
+};
+
+typedef struct ccsr_sec {
+	u32	res0;
+	u32	mcfgr;		/* Master CFG Register */
+	u8	res1[0x4];
+	u32	scfgr;
+	struct {
+		u32	ms;	/* Job Ring LIODN Register, MS */
+		u32	ls;	/* Job Ring LIODN Register, LS */
+	} jrliodnr[4];
+	u8	res2[0x2c];
+	u32	jrstartr;	/* Job Ring Start Register */
+	struct {
+		u32	ms;	/* RTIC LIODN Register, MS */
+		u32	ls;	/* RTIC LIODN Register, LS */
+	} rticliodnr[4];
+	u8	res3[0x1c];
+	u32	decorr;		/* DECO Request Register */
+	struct {
+		u32	ms;	/* DECO LIODN Register, MS */
+		u32	ls;	/* DECO LIODN Register, LS */
+	} decoliodnr[8];
+	u8	res4[0x40];
+	u32	dar;		/* DECO Avail Register */
+	u32	drr;		/* DECO Reset Register */
+	u8	res5[0x4d8];
+	struct rng4tst rng;	/* RNG Registers */
+	u8	res6[0x8a0];
+	u32	crnr_ms;	/* CHA Revision Number Register, MS */
+	u32	crnr_ls;	/* CHA Revision Number Register, LS */
+	u32	ctpr_ms;	/* Compile Time Parameters Register, MS */
+	u32	ctpr_ls;	/* Compile Time Parameters Register, LS */
+	u8	res7[0x10];
+	u32	far_ms;		/* Fault Address Register, MS */
+	u32	far_ls;		/* Fault Address Register, LS */
+	u32	falr;		/* Fault Address LIODN Register */
+	u32	fadr;		/* Fault Address Detail Register */
+	u8	res8[0x4];
+	u32	csta;		/* CAAM Status Register */
+	u32	smpart;		/* Secure Memory Partition Parameters */
+	u32	smvid;		/* Secure Memory Version ID */
+	u32	rvid;		/* Run Time Integrity Checking Version ID Reg.*/
+	u32	ccbvid;		/* CHA Cluster Block Version ID Register */
+	u32	chavid_ms;	/* CHA Version ID Register, MS */
+	u32	chavid_ls;	/* CHA Version ID Register, LS */
+	u32	chanum_ms;	/* CHA Number Register, MS */
+	u32	chanum_ls;	/* CHA Number Register, LS */
+	u32	secvid_ms;	/* SEC Version ID Register, MS */
+	u32	secvid_ls;	/* SEC Version ID Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+	u8	res9[0x6f020];
+#else
+	u8	res9[0x6020];
+#endif
+	u32	qilcr_ms;	/* Queue Interface LIODN CFG Register, MS */
+	u32	qilcr_ls;	/* Queue Interface LIODN CFG Register, LS */
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+	u8	res10[0x8ffd8];
+#else
+	u8	res10[0x8fd8];
+#endif
+} ccsr_sec_t;
+
+#define SEC_CTPR_MS_AXI_LIODN		0x08000000
+#define SEC_CTPR_MS_QI			0x02000000
+#define SEC_CTPR_MS_VIRT_EN_INCL	0x00000001
+#define SEC_CTPR_MS_VIRT_EN_POR		0x00000002
+#define SEC_RVID_MA			0x0f000000
+#define SEC_CHANUM_MS_JRNUM_MASK	0xf0000000
+#define SEC_CHANUM_MS_JRNUM_SHIFT	28
+#define SEC_CHANUM_MS_DECONUM_MASK	0x0f000000
+#define SEC_CHANUM_MS_DECONUM_SHIFT	24
+#define SEC_SECVID_MS_IPID_MASK	0xffff0000
+#define SEC_SECVID_MS_IPID_SHIFT	16
+#define SEC_SECVID_MS_MAJ_REV_MASK	0x0000ff00
+#define SEC_SECVID_MS_MAJ_REV_SHIFT	8
+#define SEC_CCBVID_ERA_MASK		0xff000000
+#define SEC_CCBVID_ERA_SHIFT		24
+#define SEC_SCFGR_RDBENABLE		0x00000400
+#define SEC_SCFGR_VIRT_EN		0x00008000
+#define SEC_CHAVID_LS_RNG_SHIFT		16
+#define SEC_CHAVID_RNG_LS_MASK		0x000f0000
+
+#define CONFIG_JRSTARTR_JR0		0x00000001
+
+struct jr_regs {
+#if defined(CONFIG_SYS_FSL_SEC_LE) && \
+	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
+	u32 irba_l;
+	u32 irba_h;
+#else
+	u32 irba_h;
+	u32 irba_l;
+#endif
+	u32 rsvd1;
+	u32 irs;
+	u32 rsvd2;
+	u32 irsa;
+	u32 rsvd3;
+	u32 irja;
+#if defined(CONFIG_SYS_FSL_SEC_LE) && \
+	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
+	u32 orba_l;
+	u32 orba_h;
+#else
+	u32 orba_h;
+	u32 orba_l;
+#endif
+	u32 rsvd4;
+	u32 ors;
+	u32 rsvd5;
+	u32 orjr;
+	u32 rsvd6;
+	u32 orsf;
+	u32 rsvd7;
+	u32 jrsta;
+	u32 rsvd8;
+	u32 jrint;
+	u32 jrcfg0;
+	u32 jrcfg1;
+	u32 rsvd9;
+	u32 irri;
+	u32 rsvd10;
+	u32 orwi;
+	u32 rsvd11;
+	u32 jrcr;
+};
+
+/*
+ * Scatter Gather Entry - Specifies the the Scatter Gather Format
+ * related information
+ */
+struct sg_entry {
+#if defined(CONFIG_SYS_FSL_SEC_LE) && \
+	!(defined(CONFIG_MX6) || defined(CONFIG_MX7))
+	uint32_t addr_lo;	/* Memory Address - lo */
+	uint32_t addr_hi;	/* Memory Address of start of buffer - hi */
+#else
+	uint32_t addr_hi;	/* Memory Address of start of buffer - hi */
+	uint32_t addr_lo;	/* Memory Address - lo */
+#endif
+
+	uint32_t len_flag;	/* Length of the data in the frame */
+#define SG_ENTRY_LENGTH_MASK	0x3FFFFFFF
+#define SG_ENTRY_EXTENSION_BIT	0x80000000
+#define SG_ENTRY_FINAL_BIT	0x40000000
+	uint32_t bpid_offset;
+#define SG_ENTRY_BPID_MASK	0x00FF0000
+#define SG_ENTRY_BPID_SHIFT	16
+#define SG_ENTRY_OFFSET_MASK	0x00001FFF
+#define SG_ENTRY_OFFSET_SHIFT	0
+};
+
+#define BLOB_SIZE(x)		((x) + 32 + 16) /* Blob buffer size */
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7)
+/* Job Ring Base Address */
+#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
+/* Secure Memory Offset varies accross versions */
+#define SM_V1_OFFSET 0x0f4
+#define SM_V2_OFFSET 0xa00
+/*Secure Memory Versioning */
+#define SMVID_V2 0x20105
+#define SM_VERSION(x)  (x < SMVID_V2 ? 1 : 2)
+#define SM_OFFSET(x)  (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
+/* CAAM Job Ring 0 Registers */
+/* Secure Memory Partition Owner register */
+#define SMCSJR_PO		(3 << 6)
+/* JR Allocation Error */
+#define SMCSJR_AERR		(3 << 12)
+/* Secure memory partition 0 page 0 owner register */
+#define CAAM_SMPO_0	    (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
+/* Secure memory command register */
+#define CAAM_SMCJR(v, jr)   (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
+/* Secure memory command status register */
+#define CAAM_SMCSJR(v, jr)  (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
+/* Secure memory access permissions register */
+#define CAAM_SMAPJR(v, jr, y) \
+	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
+/* Secure memory access group 2 register */
+#define CAAM_SMAG2JR(v, jr, y) \
+	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
+/* Secure memory access group 1 register */
+#define CAAM_SMAG1JR(v, jr, y)  \
+	(JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
+
+/* Commands and macros for secure memory */
+#define SM_CMD(v)		(v == 1 ? 0x0 : 0x1E4)
+#define SM_STATUS(v)		(v == 1 ? 0x8 : 0x1EC)
+#define SM_PERM(v)		(v == 1 ?  0x10 : 0x4)
+#define SM_GROUP2(v)		(v == 1 ? 0x14 : 0x8)
+#define SM_GROUP1(v)		(v == 1 ? 0x18 : 0xC)
+#define CMD_PAGE_ALLOC		0x1
+#define CMD_PAGE_DEALLOC	0x2
+#define CMD_PART_DEALLOC	0x3
+#define CMD_INQUIRY		0x5
+#define CMD_COMPLETE		(3 << 14)
+#define PAGE_AVAILABLE		0
+#define PAGE_OWNED		(3 << 6)
+#define PAGE(x)			(x << 16)
+#define PARTITION(x)		(x << 8)
+#define PARTITION_OWNER(x)	(0x3 << (x*2))
+
+/* Address of secure 4kbyte pages */
+#define SEC_MEM_PAGE0		CAAM_ARB_BASE_ADDR
+#define SEC_MEM_PAGE1		(CAAM_ARB_BASE_ADDR + 0x1000)
+#define SEC_MEM_PAGE2		(CAAM_ARB_BASE_ADDR + 0x2000)
+#define SEC_MEM_PAGE3		(CAAM_ARB_BASE_ADDR + 0x3000)
+
+#define JR_MID			2               /* Matches ROM configuration */
+#define KS_G1			(1 << JR_MID)   /* CAAM only */
+#define PERM			0x0000B008      /* Clear on release, lock SMAP
+						 * lock SMAG group 1 Blob */
+
+/* HAB WRAPPED KEY header */
+#define WRP_HDR_SIZE		0x08
+#define HDR_TAG			0x81
+#define HDR_PAR			0x41
+/* HAB WRAPPED KEY Data */
+#define HAB_MOD			0x66
+#define HAB_ALG			0x55
+#define HAB_FLG			0x00
+
+/* Partition and Page IDs */
+#define PARTITION_1	1
+#define PAGE_1			1
+
+#define ERROR_IN_PAGE_ALLOC	1
+#define ECONSTRJDESC   -1
+
+#endif
+
+/* blob_dek:
+ * Encapsulates the src in a secure blob and stores it dst
+ * @src: reference to the plaintext
+ * @dst: reference to the output adrress
+ * @len: size in bytes of src
+ * @return: 0 on success, error otherwise
+ */
+int blob_dek(const u8 *src, u8 *dst, u8 len);
+
+#if defined(CONFIG_ARCH_C29X)
+int sec_init_idx(uint8_t);
+#endif
+int sec_init(void);
+#endif
+
+#endif /* __FSL_SEC_H */
diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h
new file mode 100644
index 0000000..fb838db
--- /dev/null
+++ b/include/fsl_sec_mon.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __FSL_SEC_MON_H
+#define __FSL_SEC_MON_H
+
+#include <common.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYS_FSL_SEC_MON_LE
+#define sec_mon_in32(a)       in_le32(a)
+#define sec_mon_out32(a, v)   out_le32(a, v)
+#define sec_mon_in16(a)       in_le16(a)
+#define sec_mon_clrbits32     clrbits_le32
+#define sec_mon_setbits32     setbits_le32
+#elif defined(CONFIG_SYS_FSL_SEC_MON_BE)
+#define sec_mon_in32(a)       in_be32(a)
+#define sec_mon_out32(a, v)   out_be32(a, v)
+#define sec_mon_in16(a)       in_be16(a)
+#define sec_mon_clrbits32     clrbits_be32
+#define sec_mon_setbits32     setbits_be32
+#else
+#error Neither CONFIG_SYS_FSL_SEC_MON_LE nor CONFIG_SYS_FSL_SEC_MON_BE defined
+#endif
+
+struct ccsr_sec_mon_regs {
+	u8 reserved0[0x04];
+	u32 hp_com;	/* 0x04 SEC_MON_HP Command Register */
+	u8 reserved2[0x0c];
+	u32 hp_stat;	/* 0x08 SEC_MON_HP Status Register */
+};
+
+#define HPCOMR_SW_SV		0x100	/* Security Violation bit */
+#define HPCOMR_SW_FSV		0x200	/* Fatal Security Violation bit */
+#define HPCOMR_SSM_ST		0x1	/* SSM_ST field in SEC_MON command */
+#define HPCOMR_SSM_ST_DIS	0x2	/* Disable Secure to Trusted State */
+#define HPCOMR_SSM_SFNS_DIS	0x4	/* Disable Soft Fail to Non-Secure */
+#define HPSR_SSM_ST_CHECK	0x900	/* SEC_MON is in check state */
+#define HPSR_SSM_ST_NON_SECURE	0xb00	/* SEC_MON is in non secure state */
+#define HPSR_SSM_ST_TRUST	0xd00	/* SEC_MON is in trusted state */
+#define HPSR_SSM_ST_SOFT_FAIL	0x300	/* SEC_MON is in soft fail state */
+#define HPSR_SSM_ST_SECURE	0xf00	/* SEC_MON is in secure state */
+#define HPSR_SSM_ST_MASK	0xf00	/* Mask for SSM_ST field */
+
+/*
+ * SEC_MON read. This specifies the possible reads
+ * from the SEC_MON
+ */
+enum {
+	SEC_MON_SSM_ST,
+	SEC_MON_SW_FSV,
+	SEC_MON_SW_SV,
+};
+
+/* Transition SEC_MON state */
+int set_sec_mon_state(u32 state);
+
+#endif /* __FSL_SEC_MON_H */
diff --git a/include/fsl_secboot_err.h b/include/fsl_secboot_err.h
new file mode 100644
index 0000000..bc9dab2
--- /dev/null
+++ b/include/fsl_secboot_err.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_SECBOOT_ERR_H
+#define _FSL_SECBOOT_ERR_H
+
+#define ERROR_ESBC_PAMU_INIT					0x100000
+#define ERROR_ESBC_SEC_RESET					0x200000
+#define ERROR_ESBC_SEC_INIT					0x400000
+#define ERROR_ESBC_SEC_DEQ					0x800000
+#define ERROR_ESBC_SEC_DEQ_TO					0x1000000
+#define ERROR_ESBC_SEC_ENQ					0x2000000
+#define ERROR_ESBC_SEC_JOBQ_STATUS				0x4000000
+#define ERROR_ESBC_CLIENT_CPUID_NO_MATCH			0x1
+#define ERROR_ESBC_CLIENT_HDR_LOC				0x2
+#define ERROR_ESBC_CLIENT_HEADER_BARKER				0x4
+#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN			0x8
+#define ERROR_ESBC_CLIENT_HEADER_SIG_LEN			0x10
+#define ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED			0x11
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY		0x12
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM		0x13
+#define ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN		0x14
+#define ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED			0x15
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY		0x16
+#define ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM		0x17
+#define ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN		0x18
+#define ERROR_IE_TABLE_NOT_FOUND				0x19
+#define ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN	0x20
+#define ERROR_KEY_TABLE_NOT_FOUND				0x21
+#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1			0x40
+#define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2			0x80
+#define ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD			0x100
+#define ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP			0x200
+#define ERROR_ESBC_CLIENT_HASH_COMPARE_KEY			0x400
+#define ERROR_ESBC_CLIENT_HASH_COMPARE_EM			0x800
+#define ERROR_ESBC_CLIENT_SSM_TRUSTSTS				0x1000
+#define ERROR_ESBC_CLIENT_BAD_ADDRESS				0x2000
+#define ERROR_ESBC_CLIENT_MISC					0x4000
+#define ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD			0x8000
+#define ERROR_ESBC_CLIENT_HEADER_SG				0x10000
+#define ERROR_ESBC_CLIENT_HEADER_IMG_SIZE			0x20000
+#define ERROR_ESBC_WRONG_CMD					0x40000
+#define ERROR_ESBC_MISSING_BOOTM				0x80000
+#define ERROR_ESBC_CLIENT_MAX					0x0
+
+struct fsl_secboot_errcode {
+	int errcode;
+	const char *name;
+};
+
+static const struct fsl_secboot_errcode fsl_secboot_errcodes[] = {
+	{ ERROR_ESBC_PAMU_INIT,
+		"Error in initializing PAMU"},
+	{ ERROR_ESBC_SEC_RESET,
+		"Error in resetting Job ring of SEC"},
+	{ ERROR_ESBC_SEC_INIT,
+		"Error in initializing SEC"},
+	{ ERROR_ESBC_SEC_ENQ,
+		"Error in enqueue operation by SEC"},
+	{ ERROR_ESBC_SEC_DEQ_TO,
+		"Dequeue operation by SEC is timed out"},
+	{ ERROR_ESBC_SEC_DEQ,
+		"Error in dequeue operation by SEC"},
+	{ ERROR_ESBC_SEC_JOBQ_STATUS,
+		"Error in status of the job submitted to SEC"},
+	{ ERROR_ESBC_CLIENT_CPUID_NO_MATCH,
+		"Current core is not boot core i.e core0" },
+	{ ERROR_ESBC_CLIENT_HDR_LOC,
+		"Header address not in allowed memory range" },
+	{ ERROR_ESBC_CLIENT_HEADER_BARKER,
+		"Wrong barker code in header" },
+	{ ERROR_ESBC_CLIENT_HEADER_KEY_LEN,
+		"Wrong public key length in header" },
+	{ ERROR_ESBC_CLIENT_HEADER_SIG_LEN,
+		"Wrong signature length in header" },
+	{ ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN,
+		"Public key length not twice of signature length" },
+	{ ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1,
+		"Public key Modulus most significant bit not set" },
+	{ ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2,
+		"Public key Modulus in header not odd" },
+	{ ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD,
+		"Signature not less than modulus" },
+	{ ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP,
+		"Entry point not in allowed space or one of the SG entries" },
+	{ ERROR_ESBC_CLIENT_HASH_COMPARE_KEY,
+		"Public key hash comparison failed" },
+	{ ERROR_ESBC_CLIENT_HASH_COMPARE_EM,
+		"RSA verification failed" },
+	{ ERROR_ESBC_CLIENT_SSM_TRUSTSTS,
+		"SNVS not in TRUSTED state" },
+	{ ERROR_ESBC_CLIENT_BAD_ADDRESS,
+		"Bad address error" },
+	{ ERROR_ESBC_CLIENT_MISC,
+		"Miscallaneous error" },
+	{ ERROR_ESBC_CLIENT_HEADER_SG,
+		"No SG support"  },
+	{ ERROR_ESBC_CLIENT_HEADER_IMG_SIZE,
+		"Invalid Image size"  },
+	{ ERROR_ESBC_WRONG_CMD,
+		"Unknown cmd/Wrong arguments. Core in infinite loop"},
+	{ ERROR_ESBC_MISSING_BOOTM,
+		"Bootm command missing from bootscript" },
+	{ ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED,
+		"Selected key is revoked" },
+	{ ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY,
+		"Wrong key entry" },
+	{ ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM,
+		"Wrong key is selected" },
+	{ ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN,
+		"Wrong srk public key len in header" },
+	{ ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED,
+		"Selected IE key is revoked" },
+	{ ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY,
+		"Wrong key entry in IE Table" },
+	{ ERROR_ESBC_CLIENT_HEADER_INVALID_IE_KEY_NUM,
+		"Wrong IE key is selected" },
+	{ ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN,
+		"Wrong IE public key len in header" },
+	{ ERROR_IE_TABLE_NOT_FOUND,
+		"Information about IE Table missing" },
+	{ ERROR_KEY_TABLE_NOT_FOUND,
+		"No Key/ Key Table Found in header"},
+	{ ERROR_ESBC_CLIENT_MAX, "NULL" }
+};
+
+void fsl_secboot_handle_error(int error);
+#endif
diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h
new file mode 100644
index 0000000..613814d
--- /dev/null
+++ b/include/fsl_sfp.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_SFP_SNVS_
+#define _FSL_SFP_SNVS_
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_SYS_FSL_SRK_LE
+#define srk_in32(a)       in_le32(a)
+#else
+#define srk_in32(a)       in_be32(a)
+#endif
+
+#ifdef CONFIG_SYS_FSL_SFP_LE
+#define sfp_in32(a)       in_le32(a)
+#define sfp_out32(a, v)   out_le32(a, v)
+#define sfp_in16(a)       in_le16(a)
+#elif defined(CONFIG_SYS_FSL_SFP_BE)
+#define sfp_in32(a)       in_be32(a)
+#define sfp_out32(a, v)   out_be32(a, v)
+#define sfp_in16(a)       in_be16(a)
+#else
+#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined
+#endif
+
+/* Number of SRKH registers */
+#define NUM_SRKH_REGS	8
+
+#if	defined(CONFIG_SYS_FSL_SFP_VER_3_2) ||	\
+	defined(CONFIG_SYS_FSL_SFP_VER_3_4)
+struct ccsr_sfp_regs {
+	u32 ospr;		/* 0x200 */
+	u32 ospr1;		/* 0x204 */
+	u32 reserved1[4];
+	u32 fswpr;		/* 0x218 FSL Section Write Protect */
+	u32 fsl_uid;		/* 0x21c FSL UID 0 */
+	u32 fsl_uid_1;		/* 0x220 FSL UID 0 */
+	u32 reserved2[12];
+	u32 srk_hash[8];	/* 0x254 Super Root Key Hash */
+	u32 oem_uid;		/* 0x274 OEM UID 0*/
+	u32 oem_uid_1;		/* 0x278 OEM UID 1*/
+	u32 oem_uid_2;		/* 0x27c OEM UID 2*/
+	u32 oem_uid_3;		/* 0x280 OEM UID 3*/
+	u32 oem_uid_4;		/* 0x284 OEM UID 4*/
+	u32 reserved3[8];
+};
+#elif defined(CONFIG_SYS_FSL_SFP_VER_3_0)
+struct ccsr_sfp_regs {
+	u32 ospr;		/* 0x200 */
+	u32 reserved0[14];
+	u32 srk_hash[NUM_SRKH_REGS];	/* 0x23c Super Root Key Hash */
+	u32 oem_uid;		/* 0x9c OEM Unique ID */
+	u8 reserved2[0x04];
+	u32 ovpr;			/* 0xA4  Intent To Secure */
+	u8 reserved4[0x08];
+	u32 fsl_uid;		/* 0xB0  FSL Unique ID */
+	u8 reserved5[0x04];
+	u32 fsl_spfr0;		/* Scratch Pad Fuse Register 0 */
+	u32 fsl_spfr1;		/* Scratch Pad Fuse Register 1 */
+
+};
+#else
+struct ccsr_sfp_regs {
+	u8 reserved0[0x40];
+	u32 ospr;	/* 0x40  OEM Security Policy Register */
+	u8 reserved2[0x38];
+	u32 srk_hash[8];	/* 0x7c  Super Root Key Hash */
+	u32 oem_uid;	/* 0x9c  OEM Unique ID */
+	u8 reserved4[0x4];
+	u32 ovpr;	/* 0xA4  OEM Validation Policy Register */
+	u8 reserved8[0x8];
+	u32 fsl_uid;	/* 0xB0  FSL Unique ID */
+};
+#endif
+
+#define ITS_MASK	0x00000004
+#define ITS_BIT		2
+
+#if defined(CONFIG_SYS_FSL_SFP_VER_3_4)
+#define OSPR_KEY_REVOC_SHIFT    9
+#define OSPR_KEY_REVOC_MASK     0x0000fe00
+#else
+#define OSPR_KEY_REVOC_SHIFT    13
+#define OSPR_KEY_REVOC_MASK     0x0000e000
+#endif /* CONFIG_SYS_FSL_SFP_VER_3_4 */
+
+#endif
diff --git a/include/fsl_tgec.h b/include/fsl_tgec.h
new file mode 100644
index 0000000..59cd856
--- /dev/null
+++ b/include/fsl_tgec.h
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *	Dave Liu <daveliu@freescale.com>
+ */
+
+#ifndef __TGEC_H__
+#define __TGEC_H__
+
+#include <phy.h>
+
+struct tgec {
+	/* 10GEC general control and status registers */
+	u32	tgec_id;	/* Controller ID register */
+	u32	res0;
+	u32	command_config;	/* Control and configuration register */
+	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
+	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
+	u32	maxfrm;		/* Maximum frame length register */
+	u32	pause_quant;	/* Pause quanta register */
+	u32	res1[4];
+	u32	hashtable_ctrl;	/* Hash table control register */
+	u32	res2[4];
+	u32	status;		/* MAC status register */
+	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
+	u32	mac_addr_2;	/* Lower 32 bits of the 2nd 48-bit MAC addr */
+	u32	mac_addr_3;	/* Upper 16 bits of the 2nd 48-bit MAC addr */
+	u32	res3[4];
+	u32	imask;		/* Interrupt mask register */
+	u32	ievent;		/* Interrupt event register */
+	u32	res4[6];
+	/* 10GEC statistics counter registers */
+	u32	tx_frame_u;	/* Tx frame counter upper */
+	u32	tx_frame_l;	/* Tx frame counter lower */
+	u32	rx_frame_u;	/* Rx frame counter upper */
+	u32	rx_frame_l;	/* Rx frame counter lower */
+	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
+	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
+	u32	rx_align_err_u;	/* Rx alignment error upper */
+	u32	rx_align_err_l;	/* Rx alignment error lower */
+	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
+	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
+	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
+	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
+	u32	rx_long_err_u;	/* Rx too long frame error upper */
+	u32	rx_long_err_l;	/* Rx too long frame error lower */
+	u32	rx_frame_err_u;	/* Rx frame length error upper */
+	u32	rx_frame_err_l;	/* Rx frame length error lower */
+	u32	tx_vlan_u;	/* Tx VLAN frame upper */
+	u32	tx_vlan_l;	/* Tx VLAN frame lower */
+	u32	rx_vlan_u;	/* Rx VLAN frame upper */
+	u32	rx_vlan_l;	/* Rx VLAN frame lower */
+	u32	tx_oct_u;	/* Tx octets upper */
+	u32	tx_oct_l;	/* Tx octets lower */
+	u32	rx_oct_u;	/* Rx octets upper */
+	u32	rx_oct_l;	/* Rx octets lower */
+	u32	rx_uni_u;	/* Rx unicast frame upper */
+	u32	rx_uni_l;	/* Rx unicast frame lower */
+	u32	rx_multi_u;	/* Rx multicast frame upper */
+	u32	rx_multi_l;	/* Rx multicast frame lower */
+	u32	rx_brd_u;	/* Rx broadcast frame upper */
+	u32	rx_brd_l;	/* Rx broadcast frame lower */
+	u32	tx_frame_err_u;	/* Tx frame error upper */
+	u32	tx_frame_err_l;	/* Tx frame error lower */
+	u32	tx_uni_u;	/* Tx unicast frame upper */
+	u32	tx_uni_l;	/* Tx unicast frame lower */
+	u32	tx_multi_u;	/* Tx multicast frame upper */
+	u32	tx_multi_l;	/* Tx multicast frame lower */
+	u32	tx_brd_u;	/* Tx broadcast frame upper */
+	u32	tx_brd_l;	/* Tx broadcast frame lower */
+	u32	rx_drop_u;	/* Rx dropped packets upper */
+	u32	rx_drop_l;	/* Rx dropped packets lower */
+	u32	rx_eoct_u;	/* Rx ethernet octets upper */
+	u32	rx_eoct_l;	/* Rx ethernet octets lower */
+	u32	rx_pkt_u;	/* Rx packets upper */
+	u32	rx_pkt_l;	/* Rx packets lower */
+	u32	tx_undsz_u;	/* Undersized packet upper */
+	u32	tx_undsz_l;	/* Undersized packet lower */
+	u32	rx_64_u;	/* Rx 64 oct packet upper */
+	u32	rx_64_l;	/* Rx 64 oct packet lower */
+	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
+	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
+	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
+	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
+	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
+	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
+	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
+	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
+	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
+	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
+	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
+	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
+	u32	tx_oversz_u;	/* oversized packet upper */
+	u32	tx_oversz_l;	/* oversized packet lower */
+	u32	tx_jabber_u;	/* Jabber packet upper */
+	u32	tx_jabber_l;	/* Jabber packet lower */
+	u32	tx_frag_u;	/* Fragment packet upper */
+	u32	tx_frag_l;	/* Fragment packet lower */
+	u32	rx_err_u;	/* Rx frame error upper */
+	u32	rx_err_l;	/* Rx frame error lower */
+	u32	res5[0x39a];
+};
+
+/* EC10G_ID - 10-gigabit ethernet MAC controller ID */
+#define EC10G_ID_VER_MASK	0x0000ff00
+#define EC10G_ID_VER_SHIFT	8
+#define EC10G_ID_REV_MASK	0x000000ff
+
+/* COMMAND_CONFIG - command and configuration register */
+#define TGEC_CMD_CFG_EN_TIMESTAMP	0x00100000 /* enable IEEE1588 */
+#define TGEC_CMD_CFG_TX_ADDR_INS_SEL	0x00080000 /* Tx mac addr w/ second */
+#define TGEC_CMD_CFG_NO_LEN_CHK		0x00020000 /* payload len chk disable */
+#define TGEC_CMD_CFG_SEND_IDLE		0x00010000 /* send XGMII idle seqs */
+#define TGEC_CMD_CFG_RX_ER_DISC		0x00004000 /* Rx err frm discard enb */
+#define TGEC_CMD_CFG_CMD_FRM_EN		0x00002000 /* CMD frame RX enable */
+#define TGEC_CMD_CFG_STAT_CLR		0x00001000 /* clear stats */
+#define TGEC_CMD_CFG_TX_ADDR_INS	0x00000200 /* overwrite src MAC addr */
+#define TGEC_CMD_CFG_PAUSE_IGNORE	0x00000100 /* ignore pause frames */
+#define TGEC_CMD_CFG_PAUSE_FWD		0x00000080 /* fwd pause frames */
+#define TGEC_CMD_CFG_CRC_FWD		0x00000040 /* fwd Rx CRC frames */
+#define TGEC_CMD_CFG_PAD_EN		0x00000020 /* MAC remove Rx padding */
+#define TGEC_CMD_CFG_PROM_EN		0x00000010 /* promiscuous mode enable */
+#define TGEC_CMD_CFG_WAN_MODE		0x00000008 /* WAN mode enable */
+#define TGEC_CMD_CFG_RX_EN		0x00000002 /* MAC Rx path enable */
+#define TGEC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
+#define TGEC_CMD_CFG_RXTX_EN	(TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN)
+
+/* HASHTABLE_CTRL - Hashtable control register */
+#define HASHTABLE_CTRL_MCAST_EN	0x00000200 /* enable mulitcast Rx hash */
+#define HASHTABLE_CTRL_ADDR_MASK	0x000001ff
+
+/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
+#define TX_IPG_LENGTH_IPG_LEN_MASK	0x000003ff
+
+/* IMASK - interrupt mask register */
+#define IMASK_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event mask */
+#define IMASK_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion mask */
+#define IMASK_REM_FAULT		0x00004000 /* remote fault mask */
+#define IMASK_LOC_FAULT		0x00002000 /* local fault mask */
+#define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
+#define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
+#define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
+#define IMASK_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow mask */
+#define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
+#define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
+#define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
+#define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
+#define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
+#define IMASK_RX_LEN_ER		0x00000004 /* Rx payload length error mask */
+#define IMASK_RX_CRC_ER		0x00000002 /* Rx CRC error mask */
+#define IMASK_RX_ALIGN_ER	0x00000001 /* Rx alignment error mask */
+
+#define IMASK_MASK_ALL		0x00000000
+
+/* IEVENT - interrupt event register */
+#define IEVENT_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event */
+#define IEVENT_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion */
+#define IEVENT_REM_FAULT	0x00004000 /* remote fault */
+#define IEVENT_LOC_FAULT	0x00002000 /* local fault */
+#define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
+#define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
+#define IEVENT_TX_ER		0x00000200 /* Tx frame error */
+#define IEVENT_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow */
+#define IEVENT_RX_ECC_ER	0x00000080 /* Rx frame ECC error */
+#define IEVENT_RX_JAB_FRM	0x00000040 /* Rx jabber frame */
+#define IEVENT_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame */
+#define IEVENT_RX_RUNT_FRM	0x00000010 /* Rx runt frame */
+#define IEVENT_RX_FRAG_FRM	0x00000008 /* Rx fragment frame */
+#define IEVENT_RX_LEN_ER	0x00000004 /* Rx payload length error */
+#define IEVENT_RX_CRC_ER	0x00000002 /* Rx CRC error */
+#define IEVENT_RX_ALIGN_ER	0x00000001 /* Rx alignment error */
+
+#define IEVENT_CLEAR_ALL	0xffffffff
+
+struct tgec_mdio_controller {
+	u32	res0[0xc];
+	u32	mdio_stat;	/* MDIO configuration and status */
+	u32	mdio_ctl;	/* MDIO control */
+	u32	mdio_data;	/* MDIO data */
+	u32	mdio_addr;	/* MDIO address */
+};
+
+#define MDIO_STAT_CLKDIV(x)	(((x>>1) & 0xff) << 8)
+#define MDIO_STAT_BSY		(1 << 0)
+#define MDIO_STAT_RD_ER		(1 << 1)
+#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
+#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
+#define MDIO_CTL_PRE_DIS	(1 << 10)
+#define MDIO_CTL_SCAN_EN	(1 << 11)
+#define MDIO_CTL_POST_INC	(1 << 14)
+#define MDIO_CTL_READ		(1 << 15)
+
+#define MDIO_DATA(x)		(x & 0xffff)
+#define MDIO_DATA_BSY		(1 << 31)
+
+struct fsl_enet_mac;
+
+void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs,
+		int max_rx_len);
+
+#endif
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
new file mode 100644
index 0000000..c0f076b
--- /dev/null
+++ b/include/fsl_usb.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Freescale USB Controller
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _ASM_FSL_USB_H_
+#define _ASM_FSL_USB_H_
+
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+struct ccsr_usb_port_ctrl {
+	u32	ctrl;
+	u32	drvvbuscfg;
+	u32	pwrfltcfg;
+	u32	sts;
+	u8	res_14[0xc];
+	u32	bistcfg;
+	u32	biststs;
+	u32	abistcfg;
+	u32	abiststs;
+	u8	res_30[0x10];
+	u32	xcvrprg;
+	u32	anaprg;
+	u32	anadrv;
+	u32	anasts;
+};
+
+struct ccsr_usb_phy {
+	u32	id;
+	struct ccsr_usb_port_ctrl port1;
+	u8	res_50[0xc];
+	u32	tvr;
+	u32	pllprg[4];
+	u8	res_70[0x4];
+	u32	anaccfg;
+	u32	dbg;
+	u8	res_7c[0x4];
+	struct ccsr_usb_port_ctrl port2;
+	u8	res_dc[0x334];
+};
+
+#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
+#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20)
+#endif
+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
+#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
+
+#define INC_DCNT_THRESHOLD_25MV        (0 << 4)
+#define INC_DCNT_THRESHOLD_50MV        (1 << 4)
+#define DEC_DCNT_THRESHOLD_25MV        (2 << 4)
+#define DEC_DCNT_THRESHOLD_50MV        (3 << 4)
+#else
+struct ccsr_usb_phy {
+	u32     config1;
+	u32     config2;
+	u32     config3;
+	u32     config4;
+	u32     config5;
+	u32     status1;
+	u32	usb_enable_override;
+	u8	res[0xe4];
+};
+#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
+#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
+#endif
+
+/* USB Erratum Checking code */
+#if defined(CONFIG_PPC) || defined(CONFIG_ARM)
+bool has_dual_phy(void);
+bool has_erratum_a005275(void);
+bool has_erratum_a006261(void);
+bool has_erratum_a007075(void);
+bool has_erratum_a007798(void);
+bool has_erratum_a007792(void);
+bool has_erratum_a005697(void);
+bool has_erratum_a004477(void);
+bool has_erratum_a008751(void);
+bool has_erratum_a010151(void);
+#endif
+#endif /*_ASM_FSL_USB_H_ */
diff --git a/include/fsl_validate.h b/include/fsl_validate.h
new file mode 100644
index 0000000..c7b3ffc
--- /dev/null
+++ b/include/fsl_validate.h
@@ -0,0 +1,283 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _FSL_VALIDATE_H_
+#define _FSL_VALIDATE_H_
+
+#include <fsl_sec.h>
+#include <fsl_sec_mon.h>
+#include <command.h>
+#include <linux/types.h>
+
+#define WORD_SIZE 4
+
+/* Minimum and maximum size of RSA signature length in bits */
+#define KEY_SIZE       4096
+#define KEY_SIZE_BYTES (KEY_SIZE/8)
+#define KEY_SIZE_WORDS (KEY_SIZE_BYTES/(WORD_SIZE))
+
+extern struct jobring jr;
+
+/* Barker code size in bytes */
+#define ESBC_BARKER_LEN	4	/* barker code length in ESBC uboot client */
+				/* header */
+
+/* No-error return values */
+#define ESBC_VALID_HDR	0	/* header is valid */
+
+/* Maximum number of SG entries allowed */
+#define MAX_SG_ENTRIES	8
+
+/* Different Header Struct for LS-CH3 */
+#ifdef CONFIG_ESBC_HDR_LS
+struct fsl_secboot_img_hdr {
+	u8 barker[ESBC_BARKER_LEN];	/* barker code */
+	u32 srk_tbl_off;
+	struct {
+		u8 num_srk;
+		u8 srk_sel;
+		u8 reserve;
+	} len_kr;
+	u8 ie_flag;
+
+	u32 uid_flag;
+
+	u32 psign;		/* signature offset */
+	u32 sign_len;		/* length of the signature in bytes */
+
+	u64 pimg64;		/* 64 bit pointer to ESBC Image */
+	u32 img_size;		/* ESBC client image size in bytes */
+	u32 ie_key_sel;
+
+	u32 fsl_uid_0;
+	u32 fsl_uid_1;
+	u32 oem_uid_0;
+	u32 oem_uid_1;
+	u32 oem_uid_2;
+	u32 oem_uid_3;
+	u32 oem_uid_4;
+	u32 reserved1[3];
+};
+
+#ifdef CONFIG_KEY_REVOCATION
+/* Srk table and key revocation check */
+#define UNREVOCABLE_KEY	8
+#define ALIGN_REVOC_KEY 7
+#define MAX_KEY_ENTRIES 8
+#endif
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#define IE_FLAG_MASK 0x1
+#define SCRATCH_IE_LOW_ADR 13
+#define SCRATCH_IE_HIGH_ADR 14
+#endif
+
+#else /* CONFIG_ESBC_HDR_LS */
+
+/*
+ * ESBC uboot client header structure.
+ * The struct contain the following fields
+ * barker code
+ * public key offset
+ * pub key length
+ * signature offset
+ * length of the signature
+ * ptr to SG table
+ * no of entries in SG table
+ * esbc ptr
+ * size of esbc
+ * esbc entry point
+ * Scatter gather flag
+ * UID flag
+ * FSL UID
+ * OEM UID
+ * Here, pub key is modulus concatenated with exponent
+ * of equal length
+ */
+struct fsl_secboot_img_hdr {
+	u8 barker[ESBC_BARKER_LEN];	/* barker code */
+	union {
+		u32 pkey;		/* public key offset */
+#ifdef CONFIG_KEY_REVOCATION
+		u32 srk_tbl_off;
+#endif
+	};
+
+	union {
+		u32 key_len;		/* pub key length in bytes */
+#ifdef CONFIG_KEY_REVOCATION
+		struct {
+			u32 srk_table_flag:8;
+			u32 srk_sel:8;
+			u32 num_srk:16;
+		} len_kr;
+#endif
+	};
+
+	u32 psign;		/* signature offset */
+	u32 sign_len;		/* length of the signature in bytes */
+	union {
+		u32 psgtable;	/* ptr to SG table */
+#ifndef CONFIG_ESBC_ADDR_64BIT
+		u32 pimg;	/* ptr to ESBC client image */
+#endif
+	};
+	union {
+		u32 sg_entries;	/* no of entries in SG table */
+		u32 img_size;	/* ESBC client image size in bytes */
+	};
+	u32 img_start;		/* ESBC client entry point */
+	u32 sg_flag;		/* Scatter gather flag */
+	u32 uid_flag;
+	u32 fsl_uid_0;
+	u32 oem_uid_0;
+	u32 reserved1[2];
+	u32 fsl_uid_1;
+	u32 oem_uid_1;
+	union {
+		u32 reserved2[2];
+#ifdef CONFIG_ESBC_ADDR_64BIT
+		u64 pimg64;	/* 64 bit pointer to ESBC Image */
+#endif
+	};
+	u32 ie_flag;
+	u32 ie_key_sel;
+};
+
+#ifdef CONFIG_KEY_REVOCATION
+/* Srk table and key revocation check */
+#define SRK_FLAG	0x01
+#define UNREVOCABLE_KEY	4
+#define ALIGN_REVOC_KEY 3
+#define MAX_KEY_ENTRIES 4
+#endif
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+#define IE_FLAG_MASK 0xFFFFFFFF
+#endif
+
+#endif /* CONFIG_ESBC_HDR_LS */
+
+
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+struct ie_key_table {
+	u32 key_len;
+	u8 pkey[2 * KEY_SIZE_BYTES];
+};
+
+struct ie_key_info {
+	uint32_t key_revok;
+	uint32_t num_keys;
+	struct ie_key_table ie_key_tbl[32];
+};
+#endif
+
+#ifdef CONFIG_KEY_REVOCATION
+struct srk_table {
+	u32 key_len;
+	u8 pkey[2 * KEY_SIZE_BYTES];
+};
+#endif
+
+/*
+ * SG table.
+ */
+#if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET)
+/*
+ * This struct contains the following fields
+ * length of the segment
+ * source address
+ */
+struct fsl_secboot_sg_table {
+	u32 len;		/* length of the segment in bytes */
+	u32 src_addr;		/* ptr to the data segment */
+};
+#else
+/*
+ * This struct contains the following fields
+ * length of the segment
+ * Destination Target ID
+ * source address
+ * destination address
+ */
+struct fsl_secboot_sg_table {
+	u32 len;
+	u32 trgt_id;
+	u32 src_addr;
+	u32 dst_addr;
+};
+#endif
+
+/* ESBC global structure.
+ * Data to be used across verification of different images.
+ * Stores follwoing Data:
+ * IE Table
+ */
+struct fsl_secboot_glb {
+#if defined(CONFIG_FSL_ISBC_KEY_EXT)
+	uintptr_t ie_addr;
+	struct ie_key_info ie_tbl;
+#endif
+};
+/*
+ * ESBC private structure.
+ * Private structure used by ESBC to store following fields
+ * ESBC client key
+ * ESBC client key hash
+ * ESBC client Signature
+ * Encoded hash recovered from signature
+ * Encoded hash of ESBC client header plus ESBC client image
+ */
+struct fsl_secboot_img_priv {
+	uint32_t hdr_location;
+	uintptr_t ie_addr;
+	u32 key_len;
+	struct fsl_secboot_img_hdr hdr;
+
+	u8 img_key[2 * KEY_SIZE_BYTES];	/* ESBC client key */
+	u8 img_key_hash[32];	/* ESBC client key hash */
+
+#ifdef CONFIG_KEY_REVOCATION
+	struct srk_table srk_tbl[MAX_KEY_ENTRIES];
+#endif
+	u8 img_sign[KEY_SIZE_BYTES];		/* ESBC client signature */
+
+	u8 img_encoded_hash[KEY_SIZE_BYTES];	/* EM wrt RSA PKCSv1.5  */
+						/* Includes hash recovered after
+						 * signature verification
+						 */
+
+	u8 img_encoded_hash_second[KEY_SIZE_BYTES];/* EM' wrt RSA PKCSv1.5 */
+						/* Includes hash of
+						 * ESBC client header plus
+						 * ESBC client image
+						 */
+
+	struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES];	/* SG table */
+	uintptr_t ehdrloc;	/* ESBC Header location */
+	uintptr_t *img_addr_ptr;	/* ESBC Image Location */
+	uint32_t img_size;	/* ESBC Image Size */
+};
+
+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc,
+				char * const argv[]);
+
+int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str,
+	uintptr_t *img_addr_ptr);
+int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,
+	char * const argv[]);
+int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc,
+	char * const argv[]);
+
+int fsl_check_boot_mode_secure(void);
+int fsl_setenv_chain_of_trust(void);
+
+/*
+ * This function is used to validate the main U-boot binary from
+ * SPL just before passing control to it using QorIQ Trust
+ * Architecture header (appended to U-boot image).
+ */
+void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr);
+#endif
diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h
new file mode 100644
index 0000000..655f22e
--- /dev/null
+++ b/include/fsl_wdog.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Freescale Semiconductor, Inc.
+ */
+
+struct watchdog_regs {
+	u16	wcr;	/* Control */
+	u16	wsr;	/* Service */
+	u16	wrsr;	/* Reset Status */
+};
+
+#define WCR_WDZST	0x01
+#define WCR_WDBG	0x02
+#define WCR_WDE		0x04
+#define WCR_WDT		0x08
+#define WCR_SRS		0x10
+#define WCR_WDA 	0x20
+#define SET_WCR_WT(x)	(x << 8)
+#define WCR_WT_MSK	SET_WCR_WT(0xFF)
diff --git a/include/fuse.h b/include/fuse.h
new file mode 100644
index 0000000..d48dcdf
--- /dev/null
+++ b/include/fuse.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009-2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the mpc512x iim code:
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
+ */
+
+#ifndef _FUSE_H_
+#define _FUSE_H_
+
+/*
+ * Read/Sense/Program/Override interface:
+ *   bank:    Fuse bank
+ *   word:    Fuse word within the bank
+ *   val:     Value to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int fuse_read(u32 bank, u32 word, u32 *val);
+int fuse_sense(u32 bank, u32 word, u32 *val);
+int fuse_prog(u32 bank, u32 word, u32 val);
+int fuse_override(u32 bank, u32 word, u32 val);
+
+#endif	/* _FUSE_H_ */
diff --git a/include/g_dnl.h b/include/g_dnl.h
new file mode 100644
index 0000000..6d461c7
--- /dev/null
+++ b/include/g_dnl.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __G_DOWNLOAD_H_
+#define __G_DOWNLOAD_H_
+
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+#include <linker_lists.h>
+
+/*
+ * @usb_fname: unescaped USB function name
+ * @callback_ptr: bind callback, one per function name
+ */
+#define DECLARE_GADGET_BIND_CALLBACK(usb_fname, callback_ptr) \
+	ll_entry_declare(struct g_dnl_bind_callback, \
+			__usb_function_name_##usb_fname, \
+			g_dnl_bind_callbacks) = { \
+				.usb_function_name = #usb_fname, \
+				.fptr = callback_ptr \
+			}
+
+typedef int (*g_dnl_bind_callback_f)(struct usb_configuration *);
+
+/* used in Gadget downloader callback linker list */
+struct g_dnl_bind_callback {
+	const char *usb_function_name;
+	g_dnl_bind_callback_f fptr;
+};
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *, const char *);
+int g_dnl_get_board_bcd_device_number(int gcnum);
+int g_dnl_board_usb_cable_connected(void);
+int g_dnl_register(const char *s);
+void g_dnl_unregister(void);
+void g_dnl_set_serialnumber(char *);
+
+bool g_dnl_detach(void);
+void g_dnl_trigger_detach(void);
+void g_dnl_clear_detach(void);
+int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget);
+
+#endif /* __G_DOWNLOAD_H_ */
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
new file mode 100644
index 0000000..6d38a83
--- /dev/null
+++ b/include/gdsys_fpga.h
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#ifndef __GDSYS_FPGA_H
+#define __GDSYS_FPGA_H
+
+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
+int init_func_fpga(void);
+
+enum {
+	FPGA_STATE_DONE_FAILED = 1 << 0,
+	FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+	FPGA_STATE_PLATFORM = 1 << 2,
+};
+
+int get_fpga_state(unsigned dev);
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
+
+extern struct ihs_fpga *fpga_ptr[];
+
+#define FPGA_SET_REG(ix, fld, val) \
+	fpga_set_reg((ix), \
+		     &fpga_ptr[ix]->fld, \
+		     offsetof(struct ihs_fpga, fld), \
+		     val)
+
+#define FPGA_GET_REG(ix, fld, val) \
+	fpga_get_reg((ix), \
+		     &fpga_ptr[ix]->fld, \
+		     offsetof(struct ihs_fpga, fld), \
+		     val)
+#endif
+
+struct ihs_gpio {
+	u16 read;
+	u16 clear;
+	u16 set;
+};
+
+struct ihs_i2c {
+	u16 interrupt_status;
+	u16 interrupt_enable;
+	u16 write_mailbox_ext;
+	u16 write_mailbox;
+	u16 read_mailbox_ext;
+	u16 read_mailbox;
+};
+
+struct ihs_osd {
+	u16 version;
+	u16 features;
+	u16 control;
+	u16 xy_size;
+	u16 xy_scale;
+	u16 x_pos;
+	u16 y_pos;
+};
+
+struct ihs_mdio {
+	u16 control;
+	u16 address_data;
+	u16 rx_data;
+};
+
+struct ihs_io_ep {
+	u16 transmit_data;
+	u16 rx_tx_control;
+	u16 receive_data;
+	u16 rx_tx_status;
+	u16 reserved;
+	u16 device_address;
+	u16 target_address;
+};
+
+#ifdef CONFIG_NEO
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_features;	/* 0x0004 */
+	u16 fpga_version;	/* 0x0006 */
+	u16 reserved_0[8187];	/* 0x0008 */
+	u16 reflection_high;	/* 0x3ffe */
+};
+#endif
+
+#if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP)
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_version;	/* 0x0004 */
+	u16 fpga_features;	/* 0x0006 */
+	u16 reserved_0[1];	/* 0x0008 */
+	u16 top_interrupt;	/* 0x000a */
+	u16 reserved_1[2];	/* 0x000c */
+	u16 control;		/* 0x0010 */
+	u16 extended_control;	/* 0x0012 */
+	struct ihs_gpio gpio;	/* 0x0014 */
+	u16 mpc3w_control;	/* 0x001a */
+	u16 reserved_2[2];	/* 0x001c */
+	struct ihs_io_ep ep;	/* 0x0020 */
+	u16 reserved_3[9];	/* 0x002e */
+	struct ihs_i2c i2c0;	/* 0x0040 */
+	u16 reserved_4[10];	/* 0x004c */
+	u16 mc_int;		/* 0x0060 */
+	u16 mc_int_en;		/* 0x0062 */
+	u16 mc_status;		/* 0x0064 */
+	u16 mc_control;		/* 0x0066 */
+	u16 mc_tx_data;		/* 0x0068 */
+	u16 mc_tx_address;	/* 0x006a */
+	u16 mc_tx_cmd;		/* 0x006c */
+	u16 mc_res;		/* 0x006e */
+	u16 mc_rx_cmd_status;	/* 0x0070 */
+	u16 mc_rx_data;		/* 0x0072 */
+	u16 reserved_5[69];	/* 0x0074 */
+	u16 reflection_high;	/* 0x00fe */
+	struct ihs_osd osd0;	/* 0x0100 */
+#ifdef CONFIG_SYS_OSD_DH
+	u16 reserved_6[57];	/* 0x010e */
+	struct ihs_osd osd1;	/* 0x0180 */
+	u16 reserved_7[9];	/* 0x018e */
+	struct ihs_i2c i2c1;	/* 0x01a0 */
+	u16 reserved_8[1834];	/* 0x01ac */
+	u16 videomem0[2048];	/* 0x1000 */
+	u16 videomem1[2048];	/* 0x2000 */
+#else
+	u16 reserved_6[889];	/* 0x010e */
+	u16 videomem0[2048];	/* 0x0800 */
+#endif
+};
+#endif
+
+#ifdef CONFIG_STRIDER_CPU
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_version;	/* 0x0004 */
+	u16 fpga_features;	/* 0x0006 */
+	u16 reserved_0[1];	/* 0x0008 */
+	u16 top_interrupt;	/* 0x000a */
+	u16 reserved_1[3];	/* 0x000c */
+	u16 extended_control;	/* 0x0012 */
+	struct ihs_gpio gpio;	/* 0x0014 */
+	u16 mpc3w_control;	/* 0x001a */
+	u16 reserved_2[2];	/* 0x001c */
+	struct ihs_io_ep ep;	/* 0x0020 */
+	u16 reserved_3[9];	/* 0x002e */
+	u16 mc_int;		/* 0x0040 */
+	u16 mc_int_en;		/* 0x0042 */
+	u16 mc_status;		/* 0x0044 */
+	u16 mc_control;		/* 0x0046 */
+	u16 mc_tx_data;		/* 0x0048 */
+	u16 mc_tx_address;	/* 0x004a */
+	u16 mc_tx_cmd;		/* 0x004c */
+	u16 mc_res;		/* 0x004e */
+	u16 mc_rx_cmd_status;	/* 0x0050 */
+	u16 mc_rx_data;		/* 0x0052 */
+	u16 reserved_4[62];	/* 0x0054 */
+	struct ihs_i2c i2c0;	/* 0x00d0 */
+};
+#endif
+
+#ifdef CONFIG_STRIDER_CON
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_version;	/* 0x0004 */
+	u16 fpga_features;	/* 0x0006 */
+	u16 reserved_0[1];	/* 0x0008 */
+	u16 top_interrupt;	/* 0x000a */
+	u16 reserved_1[4];	/* 0x000c */
+	struct ihs_gpio gpio;	/* 0x0014 */
+	u16 mpc3w_control;	/* 0x001a */
+	u16 reserved_2[2];	/* 0x001c */
+	struct ihs_io_ep ep;	/* 0x0020 */
+	u16 reserved_3[9];	/* 0x002e */
+	struct ihs_i2c i2c0;	/* 0x0040 */
+	u16 reserved_4[10];	/* 0x004c */
+	u16 mc_int;		/* 0x0060 */
+	u16 mc_int_en;		/* 0x0062 */
+	u16 mc_status;		/* 0x0064 */
+	u16 mc_control;		/* 0x0066 */
+	u16 mc_tx_data;		/* 0x0068 */
+	u16 mc_tx_address;	/* 0x006a */
+	u16 mc_tx_cmd;		/* 0x006c */
+	u16 mc_res;		/* 0x006e */
+	u16 mc_rx_cmd_status;	/* 0x0070 */
+	u16 mc_rx_data;		/* 0x0072 */
+	u16 reserved_5[70];	/* 0x0074 */
+	struct ihs_osd osd0;	/* 0x0100 */
+	u16 reserved_6[889];	/* 0x010e */
+	u16 videomem0[2048];	/* 0x0800 */
+};
+#endif
+
+#endif
diff --git a/include/generic-phy.h b/include/generic-phy.h
new file mode 100644
index 0000000..947c582
--- /dev/null
+++ b/include/generic-phy.h
@@ -0,0 +1,276 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ * Written by Jean-Jacques Hiblot  <jjhiblot@ti.com>
+ */
+
+#ifndef __GENERIC_PHY_H
+#define __GENERIC_PHY_H
+
+struct ofnode_phandle_args;
+
+/**
+ * struct phy - A handle to (allowing control of) a single phy port.
+ *
+ * Clients provide storage for phy handles. The content of the structure is
+ * managed solely by the PHY API and PHY drivers. A phy struct is
+ * initialized by "get"ing the phy struct. The phy struct is passed to all
+ * other phy APIs to identify which PHY port to operate upon.
+ *
+ * @dev: The device which implements the PHY port.
+ * @id: The PHY ID within the provider.
+ *
+ */
+struct phy {
+	struct udevice *dev;
+	unsigned long id;
+};
+
+/*
+ * struct udevice_ops - set of function pointers for phy operations
+ * @init: operation to be performed for initializing phy (optional)
+ * @exit: operation to be performed while exiting (optional)
+ * @reset: reset the phy (optional).
+ * @power_on: powering on the phy (optional)
+ * @power_off: powering off the phy (optional)
+ */
+struct phy_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) phy specifier.
+	 *
+	 * The PHY core calls this function as the first step in implementing
+	 * a client's generic_phy_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the PHY core will use a
+	 * default implementation, which assumes #phy-cells = <0> or
+	 * #phy-cells = <1>, and in the later case that the DT cell
+	 * contains a simple integer PHY port ID.
+	 *
+	 * @phy:	The phy struct to hold the translation result.
+	 * @args:	The phy specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int	(*of_xlate)(struct phy *phy, struct ofnode_phandle_args *args);
+
+	/**
+	 * init - initialize the hardware.
+	 *
+	 * Hardware intialization should not be done in during probe() but
+	 * should be implemented in this init() function. It could be starting
+	 * PLL, taking a controller out of reset, routing, etc. This function
+	 * is typically called only once per PHY port.
+	 * If power_on() is not implemented, it must power up the phy.
+	 *
+	 * @phy:	the PHY port to initialize
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int	(*init)(struct phy *phy);
+
+	/**
+	* exit - de-initialize the PHY device
+	*
+	* Hardware de-intialization should be done here. Every step done in
+	* init() should be undone here.
+	* This could be used to suspend the phy to reduce power consumption or
+	* to put the phy in a known condition before booting the OS (though it
+	* is NOT called automatically before booting the OS)
+	* If power_off() is not implemented, it must power down the phy.
+	*
+	* @phy:	PHY port to be de-initialized
+	* @return 0 if OK, or a negative error code
+	*/
+	int	(*exit)(struct phy *phy);
+
+	/**
+	* reset - resets a PHY device without shutting down
+	*
+	* @phy:	PHY port to be reset
+	*
+	* During runtime, the PHY may need to be reset in order to
+	* re-establish connection etc without being shut down or exit.
+	*
+	* @return 0 if OK, or a negative error code
+	*/
+	int	(*reset)(struct phy *phy);
+
+	/**
+	* power_on - power on a PHY device
+	*
+	* @phy:	PHY port to be powered on
+	*
+	* During runtime, the PHY may need to be powered on or off several
+	* times. This function is used to power on the PHY. It relies on the
+	* setup done in init(). If init() is not implemented, it must take care
+	* of setting up the context (PLLs, ...)
+	*
+	* @return 0 if OK, or a negative error code
+	*/
+	int	(*power_on)(struct phy *phy);
+
+	/**
+	* power_off - power off a PHY device
+	*
+	* @phy:	PHY port to be powered off
+	*
+	* During runtime, the PHY may need to be powered on or off several
+	* times. This function is used to power off the PHY. Except if
+	* init()/deinit() are not implemented, it must not de-initialize
+	* everything.
+	*
+	* @return 0 if OK, or a negative error code
+	*/
+	int	(*power_off)(struct phy *phy);
+};
+
+#ifdef CONFIG_PHY
+
+/**
+ * generic_phy_init() - initialize the PHY port
+ *
+ * @phy:	the PHY port to initialize
+ * @return 0 if OK, or a negative error code
+ */
+int generic_phy_init(struct phy *phy);
+
+/**
+ * generic_phy_init() - de-initialize the PHY device
+ *
+ * @phy:	PHY port to be de-initialized
+ * @return 0 if OK, or a negative error code
+ */
+int generic_phy_exit(struct phy *phy);
+
+/**
+ * generic_phy_reset() - resets a PHY device without shutting down
+ *
+ * @phy:	PHY port to be reset
+ *@return 0 if OK, or a negative error code
+ */
+int generic_phy_reset(struct phy *phy);
+
+/**
+ * generic_phy_power_on() - power on a PHY device
+ *
+ * @phy:	PHY port to be powered on
+ * @return 0 if OK, or a negative error code
+ */
+int generic_phy_power_on(struct phy *phy);
+
+/**
+ * generic_phy_power_off() - power off a PHY device
+ *
+ * @phy:	PHY port to be powered off
+ * @return 0 if OK, or a negative error code
+ */
+int generic_phy_power_off(struct phy *phy);
+
+
+/**
+ * generic_phy_get_by_index() - Get a PHY device by integer index.
+ *
+ * @user:	the client device
+ * @index:	The index in the list of available PHYs
+ * @phy:	A pointer to the PHY port
+ *
+ * This looks up a PHY device for a client device based on its position in the
+ * list of the possible PHYs.
+ *
+ * example:
+ * usb1: usb_otg_ss@xxx {
+ *       compatible = "xxx";
+ *       reg = <xxx>;
+ *   .
+ *   .
+ *   phys = <&usb2_phy>, <&usb3_phy>;
+ *   .
+ *   .
+ * };
+ * the USB2 phy can be accessed by passing index '0' and the USB3 phy can
+ * be accessed by passing index '1'
+ *
+ * @return 0 if OK, or a negative error code
+ */
+int generic_phy_get_by_index(struct udevice *user, int index,
+			     struct phy *phy);
+
+/**
+ * generic_phy_get_by_name() - Get a PHY device by its name.
+ *
+ * @user:	the client device
+ * @phy_name:	The name of the PHY in the list of possible PHYs
+ * @phy:	A pointer to the PHY port
+ *
+ * This looks up a PHY device for a client device in the
+ * list of the possible PHYs based on its name.
+ *
+ * example:
+ * usb1: usb_otg_ss@xxx {
+ *       compatible = "xxx";
+ *       reg = <xxx>;
+ *   .
+ *   .
+ *   phys = <&usb2_phy>, <&usb3_phy>;
+ *   phy-names = "usb2phy", "usb3phy";
+ *   .
+ *   .
+ * };
+ * the USB3 phy can be accessed using "usb3phy", and USB2 by using "usb2phy"
+ *
+ * @return 0 if OK, or a negative error code
+ */
+int generic_phy_get_by_name(struct udevice *user, const char *phy_name,
+			    struct phy *phy);
+
+#else /* CONFIG_PHY */
+
+static inline int generic_phy_init(struct phy *phy)
+{
+	return 0;
+}
+
+static inline int generic_phy_exit(struct phy *phy)
+{
+	return 0;
+}
+
+static inline int generic_phy_reset(struct phy *phy)
+{
+	return 0;
+}
+
+static inline int generic_phy_power_on(struct phy *phy)
+{
+	return 0;
+}
+
+static inline int generic_phy_power_off(struct phy *phy)
+{
+	return 0;
+}
+
+static inline int generic_phy_get_by_index(struct udevice *user, int index,
+			     struct phy *phy)
+{
+	return 0;
+}
+
+static inline int generic_phy_get_by_name(struct udevice *user, const char *phy_name,
+			    struct phy *phy)
+{
+	return 0;
+}
+
+#endif /* CONFIG_PHY */
+
+/**
+ * generic_phy_valid() - check if PHY port is valid
+ *
+ * @phy:	the PHY port to check
+ * @return TRUE if valid, or FALSE
+ */
+static inline bool generic_phy_valid(struct phy *phy)
+{
+	return phy->dev != NULL;
+}
+
+#endif /*__GENERIC_PHY_H */
diff --git a/include/gt64120.h b/include/gt64120.h
new file mode 100644
index 0000000..0b577f3
--- /dev/null
+++ b/include/gt64120.h
@@ -0,0 +1,538 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2000, 2004, 2005  MIPS Technologies, Inc.
+ *	All rights reserved.
+ *	Authors: Carsten Langgaard <carstenl@mips.com>
+ *		 Maciej W. Rozycki <macro@mips.com>
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef _ASM_GT64120_H
+#define _ASM_GT64120_H
+
+#define MSK(n)			((1 << (n)) - 1)
+
+/*
+ *  Register offset addresses
+ */
+/* CPU Configuration.  */
+#define GT_CPU_OFS		0x000
+
+#define GT_MULTI_OFS		0x120
+
+/* CPU Address Decode.	*/
+#define GT_SCS10LD_OFS		0x008
+#define GT_SCS10HD_OFS		0x010
+#define GT_SCS32LD_OFS		0x018
+#define GT_SCS32HD_OFS		0x020
+#define GT_CS20LD_OFS		0x028
+#define GT_CS20HD_OFS		0x030
+#define GT_CS3BOOTLD_OFS	0x038
+#define GT_CS3BOOTHD_OFS	0x040
+#define GT_PCI0IOLD_OFS		0x048
+#define GT_PCI0IOHD_OFS		0x050
+#define GT_PCI0M0LD_OFS		0x058
+#define GT_PCI0M0HD_OFS		0x060
+#define GT_ISD_OFS		0x068
+
+#define GT_PCI0M1LD_OFS		0x080
+#define GT_PCI0M1HD_OFS		0x088
+#define GT_PCI1IOLD_OFS		0x090
+#define GT_PCI1IOHD_OFS		0x098
+#define GT_PCI1M0LD_OFS		0x0a0
+#define GT_PCI1M0HD_OFS		0x0a8
+#define GT_PCI1M1LD_OFS		0x0b0
+#define GT_PCI1M1HD_OFS		0x0b8
+#define GT_PCI1M1LD_OFS		0x0b0
+#define GT_PCI1M1HD_OFS		0x0b8
+
+#define GT_SCS10AR_OFS		0x0d0
+#define GT_SCS32AR_OFS		0x0d8
+#define GT_CS20R_OFS		0x0e0
+#define GT_CS3BOOTR_OFS		0x0e8
+
+#define GT_PCI0IOREMAP_OFS	0x0f0
+#define GT_PCI0M0REMAP_OFS	0x0f8
+#define GT_PCI0M1REMAP_OFS	0x100
+#define GT_PCI1IOREMAP_OFS	0x108
+#define GT_PCI1M0REMAP_OFS	0x110
+#define GT_PCI1M1REMAP_OFS	0x118
+
+/* CPU Error Report.  */
+#define GT_CPUERR_ADDRLO_OFS	0x070
+#define GT_CPUERR_ADDRHI_OFS	0x078
+
+#define GT_CPUERR_DATALO_OFS	0x128			/* GT-64120A only  */
+#define GT_CPUERR_DATAHI_OFS	0x130			/* GT-64120A only  */
+#define GT_CPUERR_PARITY_OFS	0x138			/* GT-64120A only  */
+
+/* CPU Sync Barrier.  */
+#define GT_PCI0SYNC_OFS		0x0c0
+#define GT_PCI1SYNC_OFS		0x0c8
+
+/* SDRAM and Device Address Decode.  */
+#define GT_SCS0LD_OFS		0x400
+#define GT_SCS0HD_OFS		0x404
+#define GT_SCS1LD_OFS		0x408
+#define GT_SCS1HD_OFS		0x40c
+#define GT_SCS2LD_OFS		0x410
+#define GT_SCS2HD_OFS		0x414
+#define GT_SCS3LD_OFS		0x418
+#define GT_SCS3HD_OFS		0x41c
+#define GT_CS0LD_OFS		0x420
+#define GT_CS0HD_OFS		0x424
+#define GT_CS1LD_OFS		0x428
+#define GT_CS1HD_OFS		0x42c
+#define GT_CS2LD_OFS		0x430
+#define GT_CS2HD_OFS		0x434
+#define GT_CS3LD_OFS		0x438
+#define GT_CS3HD_OFS		0x43c
+#define GT_BOOTLD_OFS		0x440
+#define GT_BOOTHD_OFS		0x444
+
+#define GT_ADERR_OFS		0x470
+
+/* SDRAM Configuration.	 */
+#define GT_SDRAM_CFG_OFS	0x448
+
+#define GT_SDRAM_OPMODE_OFS	0x474
+#define GT_SDRAM_BM_OFS		0x478
+#define GT_SDRAM_ADDRDECODE_OFS 0x47c
+
+/* SDRAM Parameters.  */
+#define GT_SDRAM_B0_OFS		0x44c
+#define GT_SDRAM_B1_OFS		0x450
+#define GT_SDRAM_B2_OFS		0x454
+#define GT_SDRAM_B3_OFS		0x458
+
+/* Device Parameters.  */
+#define GT_DEV_B0_OFS		0x45c
+#define GT_DEV_B1_OFS		0x460
+#define GT_DEV_B2_OFS		0x464
+#define GT_DEV_B3_OFS		0x468
+#define GT_DEV_BOOT_OFS		0x46c
+
+/* ECC.	 */
+#define GT_ECC_ERRDATALO	0x480			/* GT-64120A only  */
+#define GT_ECC_ERRDATAHI	0x484			/* GT-64120A only  */
+#define GT_ECC_MEM		0x488			/* GT-64120A only  */
+#define GT_ECC_CALC		0x48c			/* GT-64120A only  */
+#define GT_ECC_ERRADDR		0x490			/* GT-64120A only  */
+
+/* DMA Record.	*/
+#define GT_DMA0_CNT_OFS		0x800
+#define GT_DMA1_CNT_OFS		0x804
+#define GT_DMA2_CNT_OFS		0x808
+#define GT_DMA3_CNT_OFS		0x80c
+#define GT_DMA0_SA_OFS		0x810
+#define GT_DMA1_SA_OFS		0x814
+#define GT_DMA2_SA_OFS		0x818
+#define GT_DMA3_SA_OFS		0x81c
+#define GT_DMA0_DA_OFS		0x820
+#define GT_DMA1_DA_OFS		0x824
+#define GT_DMA2_DA_OFS		0x828
+#define GT_DMA3_DA_OFS		0x82c
+#define GT_DMA0_NEXT_OFS	0x830
+#define GT_DMA1_NEXT_OFS	0x834
+#define GT_DMA2_NEXT_OFS	0x838
+#define GT_DMA3_NEXT_OFS	0x83c
+
+#define GT_DMA0_CUR_OFS		0x870
+#define GT_DMA1_CUR_OFS		0x874
+#define GT_DMA2_CUR_OFS		0x878
+#define GT_DMA3_CUR_OFS		0x87c
+
+/* DMA Channel Control.	 */
+#define GT_DMA0_CTRL_OFS	0x840
+#define GT_DMA1_CTRL_OFS	0x844
+#define GT_DMA2_CTRL_OFS	0x848
+#define GT_DMA3_CTRL_OFS	0x84c
+
+/* DMA Arbiter.	 */
+#define GT_DMA_ARB_OFS		0x860
+
+/* Timer/Counter.  */
+#define GT_TC0_OFS		0x850
+#define GT_TC1_OFS		0x854
+#define GT_TC2_OFS		0x858
+#define GT_TC3_OFS		0x85c
+
+#define GT_TC_CONTROL_OFS	0x864
+
+/* PCI Internal.  */
+#define GT_PCI0_CMD_OFS		0xc00
+#define GT_PCI0_TOR_OFS		0xc04
+#define GT_PCI0_BS_SCS10_OFS	0xc08
+#define GT_PCI0_BS_SCS32_OFS	0xc0c
+#define GT_PCI0_BS_CS20_OFS	0xc10
+#define GT_PCI0_BS_CS3BT_OFS	0xc14
+
+#define GT_PCI1_IACK_OFS	0xc30
+#define GT_PCI0_IACK_OFS	0xc34
+
+#define GT_PCI0_BARE_OFS	0xc3c
+#define GT_PCI0_PREFMBR_OFS	0xc40
+
+#define GT_PCI0_SCS10_BAR_OFS	0xc48
+#define GT_PCI0_SCS32_BAR_OFS	0xc4c
+#define GT_PCI0_CS20_BAR_OFS	0xc50
+#define GT_PCI0_CS3BT_BAR_OFS	0xc54
+#define GT_PCI0_SSCS10_BAR_OFS	0xc58
+#define GT_PCI0_SSCS32_BAR_OFS	0xc5c
+
+#define GT_PCI0_SCS3BT_BAR_OFS	0xc64
+
+#define GT_PCI1_CMD_OFS		0xc80
+#define GT_PCI1_TOR_OFS		0xc84
+#define GT_PCI1_BS_SCS10_OFS	0xc88
+#define GT_PCI1_BS_SCS32_OFS	0xc8c
+#define GT_PCI1_BS_CS20_OFS	0xc90
+#define GT_PCI1_BS_CS3BT_OFS	0xc94
+
+#define GT_PCI1_BARE_OFS	0xcbc
+#define GT_PCI1_PREFMBR_OFS	0xcc0
+
+#define GT_PCI1_SCS10_BAR_OFS	0xcc8
+#define GT_PCI1_SCS32_BAR_OFS	0xccc
+#define GT_PCI1_CS20_BAR_OFS	0xcd0
+#define GT_PCI1_CS3BT_BAR_OFS	0xcd4
+#define GT_PCI1_SSCS10_BAR_OFS	0xcd8
+#define GT_PCI1_SSCS32_BAR_OFS	0xcdc
+
+#define GT_PCI1_SCS3BT_BAR_OFS	0xce4
+
+#define GT_PCI1_CFGADDR_OFS	0xcf0
+#define GT_PCI1_CFGDATA_OFS	0xcf4
+#define GT_PCI0_CFGADDR_OFS	0xcf8
+#define GT_PCI0_CFGDATA_OFS	0xcfc
+
+/* Interrupts.	*/
+#define GT_INTRCAUSE_OFS	0xc18
+#define GT_INTRMASK_OFS		0xc1c
+
+#define GT_PCI0_ICMASK_OFS	0xc24
+#define GT_PCI0_SERR0MASK_OFS	0xc28
+
+#define GT_CPU_INTSEL_OFS	0xc70
+#define GT_PCI0_INTSEL_OFS	0xc74
+
+#define GT_HINTRCAUSE_OFS	0xc98
+#define GT_HINTRMASK_OFS	0xc9c
+
+#define GT_PCI0_HICMASK_OFS	0xca4
+#define GT_PCI1_SERR1MASK_OFS	0xca8
+
+
+/*
+ * I2O Support Registers
+ */
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x01c
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE		0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE		0x02c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE			0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE		0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x06c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x07c
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1c10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1c14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1c18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1c1c
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1c20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1c24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1c28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1c2c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1c30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1c34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1c40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1c44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE			0x1c50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE		0x1c54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c6c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c7c
+
+/*
+ *  Register encodings
+ */
+#define GT_CPU_ENDIAN_SHF	12
+#define GT_CPU_ENDIAN_MSK	(MSK(1) << GT_CPU_ENDIAN_SHF)
+#define GT_CPU_ENDIAN_BIT	GT_CPU_ENDIAN_MSK
+#define GT_CPU_WR_SHF		16
+#define GT_CPU_WR_MSK		(MSK(1) << GT_CPU_WR_SHF)
+#define GT_CPU_WR_BIT		GT_CPU_WR_MSK
+#define GT_CPU_WR_DXDXDXDX	0
+#define GT_CPU_WR_DDDD		1
+
+
+#define GT_PCI_DCRM_SHF		21
+#define GT_PCI_LD_SHF		0
+#define GT_PCI_LD_MSK		(MSK(15) << GT_PCI_LD_SHF)
+#define GT_PCI_HD_SHF		0
+#define GT_PCI_HD_MSK		(MSK(7) << GT_PCI_HD_SHF)
+#define GT_PCI_REMAP_SHF	0
+#define GT_PCI_REMAP_MSK	(MSK(11) << GT_PCI_REMAP_SHF)
+
+
+#define GT_CFGADDR_CFGEN_SHF	31
+#define GT_CFGADDR_CFGEN_MSK	(MSK(1) << GT_CFGADDR_CFGEN_SHF)
+#define GT_CFGADDR_CFGEN_BIT	GT_CFGADDR_CFGEN_MSK
+
+#define GT_CFGADDR_BUSNUM_SHF	16
+#define GT_CFGADDR_BUSNUM_MSK	(MSK(8) << GT_CFGADDR_BUSNUM_SHF)
+
+#define GT_CFGADDR_DEVNUM_SHF	11
+#define GT_CFGADDR_DEVNUM_MSK	(MSK(5) << GT_CFGADDR_DEVNUM_SHF)
+
+#define GT_CFGADDR_FUNCNUM_SHF	8
+#define GT_CFGADDR_FUNCNUM_MSK	(MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
+
+#define GT_CFGADDR_REGNUM_SHF	2
+#define GT_CFGADDR_REGNUM_MSK	(MSK(6) << GT_CFGADDR_REGNUM_SHF)
+
+
+#define GT_SDRAM_BM_ORDER_SHF	2
+#define GT_SDRAM_BM_ORDER_MSK	(MSK(1) << GT_SDRAM_BM_ORDER_SHF)
+#define GT_SDRAM_BM_ORDER_BIT	GT_SDRAM_BM_ORDER_MSK
+#define GT_SDRAM_BM_ORDER_SUB	1
+#define GT_SDRAM_BM_ORDER_LIN	0
+
+#define GT_SDRAM_BM_RSVD_ALL1	0xffb
+
+
+#define GT_SDRAM_ADDRDECODE_ADDR_SHF	0
+#define GT_SDRAM_ADDRDECODE_ADDR_MSK	(MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
+#define GT_SDRAM_ADDRDECODE_ADDR_0	0
+#define GT_SDRAM_ADDRDECODE_ADDR_1	1
+#define GT_SDRAM_ADDRDECODE_ADDR_2	2
+#define GT_SDRAM_ADDRDECODE_ADDR_3	3
+#define GT_SDRAM_ADDRDECODE_ADDR_4	4
+#define GT_SDRAM_ADDRDECODE_ADDR_5	5
+#define GT_SDRAM_ADDRDECODE_ADDR_6	6
+#define GT_SDRAM_ADDRDECODE_ADDR_7	7
+
+
+#define GT_SDRAM_B0_CASLAT_SHF		0
+#define GT_SDRAM_B0_CASLAT_MSK		(MSK(2) << GT_SDRAM_B0__SHF)
+#define GT_SDRAM_B0_CASLAT_2		1
+#define GT_SDRAM_B0_CASLAT_3		2
+
+#define GT_SDRAM_B0_FTDIS_SHF		2
+#define GT_SDRAM_B0_FTDIS_MSK		(MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
+#define GT_SDRAM_B0_FTDIS_BIT		GT_SDRAM_B0_FTDIS_MSK
+
+#define GT_SDRAM_B0_SRASPRCHG_SHF	3
+#define GT_SDRAM_B0_SRASPRCHG_MSK	(MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
+#define GT_SDRAM_B0_SRASPRCHG_BIT	GT_SDRAM_B0_SRASPRCHG_MSK
+#define GT_SDRAM_B0_SRASPRCHG_2		0
+#define GT_SDRAM_B0_SRASPRCHG_3		1
+
+#define GT_SDRAM_B0_B0COMPAB_SHF	4
+#define GT_SDRAM_B0_B0COMPAB_MSK	(MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
+#define GT_SDRAM_B0_B0COMPAB_BIT	GT_SDRAM_B0_B0COMPAB_MSK
+
+#define GT_SDRAM_B0_64BITINT_SHF	5
+#define GT_SDRAM_B0_64BITINT_MSK	(MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
+#define GT_SDRAM_B0_64BITINT_BIT	GT_SDRAM_B0_64BITINT_MSK
+#define GT_SDRAM_B0_64BITINT_2		0
+#define GT_SDRAM_B0_64BITINT_4		1
+
+#define GT_SDRAM_B0_BW_SHF		6
+#define GT_SDRAM_B0_BW_MSK		(MSK(1) << GT_SDRAM_B0_BW_SHF)
+#define GT_SDRAM_B0_BW_BIT		GT_SDRAM_B0_BW_MSK
+#define GT_SDRAM_B0_BW_32		0
+#define GT_SDRAM_B0_BW_64		1
+
+#define GT_SDRAM_B0_BLODD_SHF		7
+#define GT_SDRAM_B0_BLODD_MSK		(MSK(1) << GT_SDRAM_B0_BLODD_SHF)
+#define GT_SDRAM_B0_BLODD_BIT		GT_SDRAM_B0_BLODD_MSK
+
+#define GT_SDRAM_B0_PAR_SHF		8
+#define GT_SDRAM_B0_PAR_MSK		(MSK(1) << GT_SDRAM_B0_PAR_SHF)
+#define GT_SDRAM_B0_PAR_BIT		GT_SDRAM_B0_PAR_MSK
+
+#define GT_SDRAM_B0_BYPASS_SHF		9
+#define GT_SDRAM_B0_BYPASS_MSK		(MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
+#define GT_SDRAM_B0_BYPASS_BIT		GT_SDRAM_B0_BYPASS_MSK
+
+#define GT_SDRAM_B0_SRAS2SCAS_SHF	10
+#define GT_SDRAM_B0_SRAS2SCAS_MSK	(MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
+#define GT_SDRAM_B0_SRAS2SCAS_BIT	GT_SDRAM_B0_SRAS2SCAS_MSK
+#define GT_SDRAM_B0_SRAS2SCAS_2		0
+#define GT_SDRAM_B0_SRAS2SCAS_3		1
+
+#define GT_SDRAM_B0_SIZE_SHF		11
+#define GT_SDRAM_B0_SIZE_MSK		(MSK(1) << GT_SDRAM_B0_SIZE_SHF)
+#define GT_SDRAM_B0_SIZE_BIT		GT_SDRAM_B0_SIZE_MSK
+#define GT_SDRAM_B0_SIZE_16M		0
+#define GT_SDRAM_B0_SIZE_64M		1
+
+#define GT_SDRAM_B0_EXTPAR_SHF		12
+#define GT_SDRAM_B0_EXTPAR_MSK		(MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
+#define GT_SDRAM_B0_EXTPAR_BIT		GT_SDRAM_B0_EXTPAR_MSK
+
+#define GT_SDRAM_B0_BLEN_SHF		13
+#define GT_SDRAM_B0_BLEN_MSK		(MSK(1) << GT_SDRAM_B0_BLEN_SHF)
+#define GT_SDRAM_B0_BLEN_BIT		GT_SDRAM_B0_BLEN_MSK
+#define GT_SDRAM_B0_BLEN_8		0
+#define GT_SDRAM_B0_BLEN_4		1
+
+
+#define GT_SDRAM_CFG_REFINT_SHF		0
+#define GT_SDRAM_CFG_REFINT_MSK		(MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
+
+#define GT_SDRAM_CFG_NINTERLEAVE_SHF	14
+#define GT_SDRAM_CFG_NINTERLEAVE_MSK	(MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
+#define GT_SDRAM_CFG_NINTERLEAVE_BIT	GT_SDRAM_CFG_NINTERLEAVE_MSK
+
+#define GT_SDRAM_CFG_RMW_SHF		15
+#define GT_SDRAM_CFG_RMW_MSK		(MSK(1) << GT_SDRAM_CFG_RMW_SHF)
+#define GT_SDRAM_CFG_RMW_BIT		GT_SDRAM_CFG_RMW_MSK
+
+#define GT_SDRAM_CFG_NONSTAGREF_SHF	16
+#define GT_SDRAM_CFG_NONSTAGREF_MSK	(MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
+#define GT_SDRAM_CFG_NONSTAGREF_BIT	GT_SDRAM_CFG_NONSTAGREF_MSK
+
+#define GT_SDRAM_CFG_DUPCNTL_SHF	19
+#define GT_SDRAM_CFG_DUPCNTL_MSK	(MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
+#define GT_SDRAM_CFG_DUPCNTL_BIT	GT_SDRAM_CFG_DUPCNTL_MSK
+
+#define GT_SDRAM_CFG_DUPBA_SHF		20
+#define GT_SDRAM_CFG_DUPBA_MSK		(MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
+#define GT_SDRAM_CFG_DUPBA_BIT		GT_SDRAM_CFG_DUPBA_MSK
+
+#define GT_SDRAM_CFG_DUPEOT0_SHF	21
+#define GT_SDRAM_CFG_DUPEOT0_MSK	(MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
+#define GT_SDRAM_CFG_DUPEOT0_BIT	GT_SDRAM_CFG_DUPEOT0_MSK
+
+#define GT_SDRAM_CFG_DUPEOT1_SHF	22
+#define GT_SDRAM_CFG_DUPEOT1_MSK	(MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
+#define GT_SDRAM_CFG_DUPEOT1_BIT	GT_SDRAM_CFG_DUPEOT1_MSK
+
+#define GT_SDRAM_OPMODE_OP_SHF		0
+#define GT_SDRAM_OPMODE_OP_MSK		(MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
+#define GT_SDRAM_OPMODE_OP_NORMAL	0
+#define GT_SDRAM_OPMODE_OP_NOP		1
+#define GT_SDRAM_OPMODE_OP_PRCHG	2
+#define GT_SDRAM_OPMODE_OP_MODE		3
+#define GT_SDRAM_OPMODE_OP_CBR		4
+
+#define GT_TC_CONTROL_ENTC0_SHF		0
+#define GT_TC_CONTROL_ENTC0_MSK		(MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
+#define GT_TC_CONTROL_ENTC0_BIT		GT_TC_CONTROL_ENTC0_MSK
+#define GT_TC_CONTROL_SELTC0_SHF	1
+#define GT_TC_CONTROL_SELTC0_MSK	(MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
+#define GT_TC_CONTROL_SELTC0_BIT	GT_TC_CONTROL_SELTC0_MSK
+
+
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF	0
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK	\
+	(MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT	GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_SWSCS32DIS_SHF	1
+#define GT_PCI0_BARE_SWSCS32DIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
+#define GT_PCI0_BARE_SWSCS32DIS_BIT	GT_PCI0_BARE_SWSCS32DIS_MSK
+
+#define GT_PCI0_BARE_SWSCS10DIS_SHF	2
+#define GT_PCI0_BARE_SWSCS10DIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
+#define GT_PCI0_BARE_SWSCS10DIS_BIT	GT_PCI0_BARE_SWSCS10DIS_MSK
+
+#define GT_PCI0_BARE_INTIODIS_SHF	3
+#define GT_PCI0_BARE_INTIODIS_MSK	(MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
+#define GT_PCI0_BARE_INTIODIS_BIT	GT_PCI0_BARE_INTIODIS_MSK
+
+#define GT_PCI0_BARE_INTMEMDIS_SHF	4
+#define GT_PCI0_BARE_INTMEMDIS_MSK	(MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
+#define GT_PCI0_BARE_INTMEMDIS_BIT	GT_PCI0_BARE_INTMEMDIS_MSK
+
+#define GT_PCI0_BARE_CS3BOOTDIS_SHF	5
+#define GT_PCI0_BARE_CS3BOOTDIS_MSK	(MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_CS3BOOTDIS_BIT	GT_PCI0_BARE_CS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_CS20DIS_SHF	6
+#define GT_PCI0_BARE_CS20DIS_MSK	(MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
+#define GT_PCI0_BARE_CS20DIS_BIT	GT_PCI0_BARE_CS20DIS_MSK
+
+#define GT_PCI0_BARE_SCS32DIS_SHF	7
+#define GT_PCI0_BARE_SCS32DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
+#define GT_PCI0_BARE_SCS32DIS_BIT	GT_PCI0_BARE_SCS32DIS_MSK
+
+#define GT_PCI0_BARE_SCS10DIS_SHF	8
+#define GT_PCI0_BARE_SCS10DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
+#define GT_PCI0_BARE_SCS10DIS_BIT	GT_PCI0_BARE_SCS10DIS_MSK
+
+
+#define GT_INTRCAUSE_MASABORT0_SHF	18
+#define GT_INTRCAUSE_MASABORT0_MSK	(MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
+#define GT_INTRCAUSE_MASABORT0_BIT	GT_INTRCAUSE_MASABORT0_MSK
+
+#define GT_INTRCAUSE_TARABORT0_SHF	19
+#define GT_INTRCAUSE_TARABORT0_MSK	(MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
+#define GT_INTRCAUSE_TARABORT0_BIT	GT_INTRCAUSE_TARABORT0_MSK
+
+
+#define GT_PCI0_CFGADDR_REGNUM_SHF	2
+#define GT_PCI0_CFGADDR_REGNUM_MSK	(MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
+#define GT_PCI0_CFGADDR_FUNCTNUM_SHF	8
+#define GT_PCI0_CFGADDR_FUNCTNUM_MSK	(MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
+#define GT_PCI0_CFGADDR_DEVNUM_SHF	11
+#define GT_PCI0_CFGADDR_DEVNUM_MSK	(MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
+#define GT_PCI0_CFGADDR_BUSNUM_SHF	16
+#define GT_PCI0_CFGADDR_BUSNUM_MSK	(MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_SHF	31
+#define GT_PCI0_CFGADDR_CONFIGEN_MSK	(MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_BIT	GT_PCI0_CFGADDR_CONFIGEN_MSK
+
+#define GT_PCI0_CMD_MBYTESWAP_SHF	0
+#define GT_PCI0_CMD_MBYTESWAP_MSK	(MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
+#define GT_PCI0_CMD_MBYTESWAP_BIT	GT_PCI0_CMD_MBYTESWAP_MSK
+#define GT_PCI0_CMD_MWORDSWAP_SHF	10
+#define GT_PCI0_CMD_MWORDSWAP_MSK	(MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
+#define GT_PCI0_CMD_MWORDSWAP_BIT	GT_PCI0_CMD_MWORDSWAP_MSK
+#define GT_PCI0_CMD_SBYTESWAP_SHF	16
+#define GT_PCI0_CMD_SBYTESWAP_MSK	(MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
+#define GT_PCI0_CMD_SBYTESWAP_BIT	GT_PCI0_CMD_SBYTESWAP_MSK
+#define GT_PCI0_CMD_SWORDSWAP_SHF	11
+#define GT_PCI0_CMD_SWORDSWAP_MSK	(MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
+#define GT_PCI0_CMD_SWORDSWAP_BIT	GT_PCI0_CMD_SWORDSWAP_MSK
+
+#define GT_INTR_T0EXP_SHF		8
+#define GT_INTR_T0EXP_MSK		(MSK(1) << GT_INTR_T0EXP_SHF)
+#define GT_INTR_T0EXP_BIT		GT_INTR_T0EXP_MSK
+#define GT_INTR_RETRYCTR0_SHF		20
+#define GT_INTR_RETRYCTR0_MSK		(MSK(1) << GT_INTR_RETRYCTR0_SHF)
+#define GT_INTR_RETRYCTR0_BIT		GT_INTR_RETRYCTR0_MSK
+
+/*
+ *  Misc
+ */
+#define GT_DEF_PCI0_IO_BASE	0x10000000
+#define GT_DEF_PCI0_IO_SIZE	0x02000000
+#define GT_DEF_PCI0_MEM0_BASE	0x12000000
+#define GT_DEF_PCI0_MEM0_SIZE	0x02000000
+#define GT_DEF_BASE		0x14000000
+
+#define GT_MAX_BANKSIZE		(256 * 1024 * 1024)	/* Max 256MB bank  */
+#define GT_LATTIM_MIN		6			/* Minimum lat	*/
+
+#endif /* _ASM_GT64120_H */
diff --git a/include/gzip.h b/include/gzip.h
new file mode 100644
index 0000000..2e34067
--- /dev/null
+++ b/include/gzip.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __GZIP_H
+#define __GZIP_H
+
+/**
+ * gzip_parse_header() - Parse a header from a gzip file
+ *
+ * This returns the length of the header.
+ *
+ * @src: Pointer to gzip file
+ * @len: Length of data
+ * @return length of header in bytes, or -1 if not enough data
+ */
+int gzip_parse_header(const unsigned char *src, unsigned long len);
+
+/**
+ * gunzip() - Decompress gzipped data
+ *
+ * @dst: Destination for uncompressed data
+ * @dstlen: Size of destination buffer
+ * @src: Source data to decompress
+ * @lenp: Returns length of uncompressed data
+ * @return 0 if OK, -1 on error
+ */
+int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp);
+
+/**
+ * zunzip() - Uncompress blocks compressed with zlib without headers
+ *
+ * @dst: Destination for uncompressed data
+ * @dstlen: Size of destination buffer
+ * @src: Source data to decompress
+ * @lenp: On entry, length data at @src. On exit, number of bytes used from @src
+ * @stoponerr: 0 to continue when a decode error is found, 1 to stop
+ * @offset: start offset within the src buffer
+ * @return 0 if OK, -1 on error
+ */
+int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
+	   int stoponerr, int offset);
+
+/**
+ * gzwrite progress indicators: defined weak to allow board-specific
+ * overrides:
+ *
+ *	gzwrite_progress_init called on startup
+ *	gzwrite_progress called during decompress/write loop
+ *	gzwrite_progress_finish called at end of loop to
+ *		indicate success (retcode=0) or failure
+ */
+void gzwrite_progress_init(u64 expected_size);
+
+void gzwrite_progress(int iteration, u64 bytes_written, u64 total_bytes);
+
+void gzwrite_progress_finish(int retcode, u64 totalwritten, u64 totalsize,
+			     u32 expected_crc, u32 calculated_crc);
+
+/**
+ * gzwrite() - decompress and write gzipped image from memory to block device
+ *
+ * @src:	compressed image address
+ * @len:	compressed image length in bytes
+ * @dev:	block device descriptor
+ * @szwritebuf:	bytes per write (pad to erase size)
+ * @startoffs:	offset in bytes of first write
+ * @szexpected:	expected uncompressed length, may be zero to use gzip trailer
+ *		for files under 4GiB
+ * @return 0 if OK, -1 on error
+ */
+int gzwrite(unsigned char *src, int len, struct blk_desc *dev, ulong szwritebuf,
+	    u64 startoffs, u64 szexpected);
+
+/**
+ * gzip()- Compress data into a buffer using the gzip algorithm
+ *
+ * @dst: Destination buffer for compressed data
+ * @lenp: On entry, space available in destination buffer (in bytes). On exit,
+ *	number of bytes used in the buffer
+ * @src: Source data to compress
+ * @srclen: Size of source data
+ * @return 0 if OK, -1 on error
+ */
+int gzip(void *dst, unsigned long *lenp, unsigned char *src, ulong srclen);
+
+/**
+ * zzip() - Compress blocks with zlib
+ *
+ * @dst: Destination for compressed data
+ * @lenp: On entry, length data at @dst. On exit, number of bytes written to
+ *	@dst
+ * @src: Source data to compress
+ * @srclen: Size of source data
+ * @stoponerr: 0 to continue when a decode error is found, 1 to stop
+ * @func: Some sort of function that is called to do something. !ADD DOCS HERE!
+ */
+int zzip(void *dst, ulong *lenp, unsigned char *src, ulong srclen,
+	 int stoponerr, int (*func)(ulong, ulong));
+
+#endif
diff --git a/include/handoff.h b/include/handoff.h
new file mode 100644
index 0000000..75d19b1
--- /dev/null
+++ b/include/handoff.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Passing basic information from SPL to U-Boot proper
+ *
+ * Copyright 2018 Google, Inc
+ */
+
+#ifndef __HANDOFF_H
+#define __HANDOFF_H
+
+#if CONFIG_IS_ENABLED(HANDOFF)
+
+#include <asm/handoff.h>
+
+/**
+ * struct spl_handoff - information passed from SPL to U-Boot proper
+ *
+ * @ram_size: Value to use for gd->ram_size
+ */
+struct spl_handoff {
+	struct arch_spl_handoff arch;
+	u64 ram_size;
+#ifdef CONFIG_NR_DRAM_BANKS
+	struct {
+		u64 start;
+		u64 size;
+	} ram_bank[CONFIG_NR_DRAM_BANKS];
+#endif
+};
+
+void handoff_save_dram(struct spl_handoff *ho);
+void handoff_load_dram_size(struct spl_handoff *ho);
+void handoff_load_dram_banks(struct spl_handoff *ho);
+
+/**
+ * handoff_arch_save() - Save arch-specific info into the handoff area
+ *
+ * This is defined to an empty function by default, but arch-specific code can
+ * define it to write to spi_handoff->arch. It is called from
+ * write_spl_handoff().
+ *
+ * @ho: Handoff area to fill in
+ * @return 0 if OK, -ve on error
+ */
+int handoff_arch_save(struct spl_handoff *ho);
+
+#endif
+
+#endif
diff --git a/include/hash.h b/include/hash.h
new file mode 100644
index 0000000..f4019a9
--- /dev/null
+++ b/include/hash.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef _HASH_H
+#define _HASH_H
+
+/*
+ * Maximum digest size for all algorithms we support. Having this value
+ * avoids a malloc() or C99 local declaration in common/cmd_hash.c.
+ */
+#define HASH_MAX_DIGEST_SIZE	32
+
+enum {
+	HASH_FLAG_VERIFY	= 1 << 0,	/* Enable verify mode */
+	HASH_FLAG_ENV		= 1 << 1,	/* Allow env vars */
+};
+
+struct hash_algo {
+	const char *name;			/* Name of algorithm */
+	int digest_size;			/* Length of digest */
+	/**
+	 * hash_func_ws: Generic hashing function
+	 *
+	 * This is the generic prototype for a hashing function. We only
+	 * have the watchdog version at present.
+	 *
+	 * @input:	Input buffer
+	 * @ilen:	Input buffer length
+	 * @output:	Checksum result (length depends on algorithm)
+	 * @chunk_sz:	Trigger watchdog after processing this many bytes
+	 */
+	void (*hash_func_ws)(const unsigned char *input, unsigned int ilen,
+		unsigned char *output, unsigned int chunk_sz);
+	int chunk_size;				/* Watchdog chunk size */
+	/*
+	 * hash_init: Create the context for progressive hashing
+	 *
+	 * @algo: Pointer to the hash_algo struct
+	 * @ctxp: Pointer to the pointer of the context for hashing
+	 * @return 0 if ok, -1 on error
+	 */
+	int (*hash_init)(struct hash_algo *algo, void **ctxp);
+	/*
+	 * hash_update: Perform hashing on the given buffer
+	 *
+	 * The context is freed by this function if an error occurs.
+	 *
+	 * @algo: Pointer to the hash_algo struct
+	 * @ctx: Pointer to the context for hashing
+	 * @buf: Pointer to the buffer being hashed
+	 * @size: Size of the buffer being hashed
+	 * @is_last: 1 if this is the last update; 0 otherwise
+	 * @return 0 if ok, -1 on error
+	 */
+	int (*hash_update)(struct hash_algo *algo, void *ctx, const void *buf,
+			   unsigned int size, int is_last);
+	/*
+	 * hash_finish: Write the hash result to the given buffer
+	 *
+	 * The context is freed by this function.
+	 *
+	 * @algo: Pointer to the hash_algo struct
+	 * @ctx: Pointer to the context for hashing
+	 * @dest_buf: Pointer to the buffer for the result
+	 * @size: Size of the buffer for the result
+	 * @return 0 if ok, -ENOSPC if size of the result buffer is too small
+	 *   or -1 on other errors
+	 */
+	int (*hash_finish)(struct hash_algo *algo, void *ctx, void *dest_buf,
+			   int size);
+};
+
+#ifndef USE_HOSTCC
+/**
+ * hash_command: Process a hash command for a particular algorithm
+ *
+ * This common function is used to implement specific hash commands.
+ *
+ * @algo_name:		Hash algorithm being used (lower case!)
+ * @flags:		Flags value (HASH_FLAG_...)
+ * @cmdtp:		Pointer to command table entry
+ * @flag:		Some flags normally 0 (see CMD_FLAG_.. above)
+ * @argc:		Number of arguments (arg 0 must be the command text)
+ * @argv:		Arguments
+ */
+int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
+		 int argc, char * const argv[]);
+
+/**
+ * hash_block() - Hash a block according to the requested algorithm
+ *
+ * The caller probably knows the hash length for the chosen algorithm, but
+ * in order to provide a general interface, and output_size parameter is
+ * provided.
+ *
+ * @algo_name:		Hash algorithm to use
+ * @data:		Data to hash
+ * @len:		Lengh of data to hash in bytes
+ * @output:		Place to put hash value
+ * @output_size:	On entry, pointer to the number of bytes available in
+ *			output. On exit, pointer to the number of bytes used.
+ *			If NULL, then it is assumed that the caller has
+ *			allocated enough space for the hash. This is possible
+ *			since the caller is selecting the algorithm.
+ * @return 0 if ok, -ve on error: -EPROTONOSUPPORT for an unknown algorithm,
+ * -ENOSPC if the output buffer is not large enough.
+ */
+int hash_block(const char *algo_name, const void *data, unsigned int len,
+	       uint8_t *output, int *output_size);
+
+#endif /* !USE_HOSTCC */
+
+/**
+ * hash_lookup_algo() - Look up the hash_algo struct for an algorithm
+ *
+ * The function returns the pointer to the struct or -EPROTONOSUPPORT if the
+ * algorithm is not available.
+ *
+ * @algo_name: Hash algorithm to look up
+ * @algop: Pointer to the hash_algo struct if found
+ *
+ * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm.
+ */
+int hash_lookup_algo(const char *algo_name, struct hash_algo **algop);
+
+/**
+ * hash_progressive_lookup_algo() - Look up hash_algo for prog. hash support
+ *
+ * The function returns the pointer to the struct or -EPROTONOSUPPORT if the
+ * algorithm is not available with progressive hash support.
+ *
+ * @algo_name: Hash algorithm to look up
+ * @algop: Pointer to the hash_algo struct if found
+ *
+ * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm.
+ */
+int hash_progressive_lookup_algo(const char *algo_name,
+				 struct hash_algo **algop);
+
+/**
+ * hash_parse_string() - Parse hash string into a binary array
+ *
+ * The function parses a hash string into a binary array that
+ * can for example easily be used to compare to hash values.
+ *
+ * @algo_name: Hash algorithm to look up
+ * @str: Hash string to get parsed
+ * @result: Binary array of the parsed hash string
+ *
+ * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm.
+ */
+int hash_parse_string(const char *algo_name, const char *str, uint8_t *result);
+
+#endif
diff --git a/include/hda_codec.h b/include/hda_codec.h
new file mode 100644
index 0000000..56de571
--- /dev/null
+++ b/include/hda_codec.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Support for Intel High-Definition Audio codec
+ *
+ * Copyright 2018 Google LLC
+ *
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef __HDA_CODEC_H_
+#define __HDA_CODEC_H_
+
+struct hda_regs;
+
+/**
+ * struct hda_codec_priv - Private data required by the HDA codec
+ *
+ * @regs: HDA registers
+ * @beep_nid: Node ID of beep node (>0)
+ */
+struct hda_codec_priv {
+	struct hda_regs *regs;
+	uint beep_nid;
+};
+
+/**
+ *  hda_wait_for_ready() - Wait for the codec to indicate it is ready
+ *
+ * @regs: HDA registers
+ * @return 0 if OK -ETIMEDOUT if codec did not respond in time
+ */
+int hda_wait_for_ready(struct hda_regs *regs);
+
+/**
+ *  hda_wait_for_valid() - Wait for the codec to accept the last command
+ *
+ * @regs: HDA registers
+ * @return 0 if OK -ETIMEDOUT if codec did not respond in time
+ */
+int hda_wait_for_valid(struct hda_regs *regs);
+
+/**
+ * hda_codec_detect() - Detect which codecs are present
+ *
+ * @regs: HDA registers
+ * @return bit mask of active codecs (0 if none)
+ * @return 0 if OK, -ve on error
+ */
+int hda_codec_detect(struct hda_regs *regs);
+
+/**
+ * hda_codecs_init() - Init all codecs
+ *
+ * @dev: Sound device
+ * @regs: HDA registers
+ * @codec_mask: Mask of codecs to init (bits 3:0)
+ * @return 0 if OK, -ve on error
+ */
+int hda_codecs_init(struct udevice *dev, struct hda_regs *regs, u32 codec_mask);
+
+/**
+ * hda_codec_start_beep() - Start beeping
+ *
+ * This tells the sound hardware to start a beep. It will continue until stopped
+ * by sound_stop_beep().
+ *
+ * @dev: Sound device
+ * @frequency_hz: Beep frequency in hertz
+ * @return if OK, -ve on error
+ */
+int hda_codec_start_beep(struct udevice *dev, int frequency_hz);
+
+/**
+ * hda_codec_stop_beep() - Stop beeping
+ *
+ * This tells the sound hardware to stop a previously started beep.
+ *
+ * @dev: Sound device
+ * @return if OK, -ve on error
+ */
+int hda_codec_stop_beep(struct udevice *dev);
+
+/**
+ * hda_codec_init() - Set up the HDA codec base address
+ *
+ * This should be called at the start of the probe() method.
+ *
+ * @dev: Sound device
+ * @return 0 if OK, -ve on error
+ */
+int hda_codec_init(struct udevice *dev);
+
+/**
+ * hda_codec_finish_init() - Finish setting up the HDA codec base address
+ *
+ * This should be called at the end of the probe() method.
+ *
+ * @dev: Sound device
+ * @return 0 if OK, -ve on error
+ */
+int hda_codec_finish_init(struct udevice *dev);
+
+#endif /* __HDA_CODEC_H_ */
diff --git a/include/hexdump.h b/include/hexdump.h
new file mode 100644
index 0000000..f7b76ff
--- /dev/null
+++ b/include/hexdump.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ *
+ */
+
+#ifndef HEXDUMP_H
+#define HEXDUMP_H
+
+#include <linux/ctype.h>
+#include <linux/types.h>
+
+enum {
+	DUMP_PREFIX_NONE,
+	DUMP_PREFIX_ADDRESS,
+	DUMP_PREFIX_OFFSET
+};
+
+extern const char hex_asc[];
+#define hex_asc_lo(x)	hex_asc[((x) & 0x0f)]
+#define hex_asc_hi(x)	hex_asc[((x) & 0xf0) >> 4]
+
+static inline char *hex_byte_pack(char *buf, u8 byte)
+{
+	*buf++ = hex_asc_hi(byte);
+	*buf++ = hex_asc_lo(byte);
+	return buf;
+}
+
+/**
+ * hex_to_bin - convert a hex digit to its real value
+ * @ch: ascii character represents hex digit
+ *
+ * hex_to_bin() converts one hex digit to its actual value or -1 in case of bad
+ * input.
+ */
+static inline int hex_to_bin(char ch)
+{
+	if ((ch >= '0') && (ch <= '9'))
+		return ch - '0';
+	ch = tolower(ch);
+	if ((ch >= 'a') && (ch <= 'f'))
+		return ch - 'a' + 10;
+	return -1;
+}
+
+/**
+ * hex2bin - convert an ascii hexadecimal string to its binary representation
+ * @dst: binary result
+ * @src: ascii hexadecimal string
+ * @count: result length
+ *
+ * Return 0 on success, -1 in case of bad input.
+ */
+static inline int hex2bin(u8 *dst, const char *src, size_t count)
+{
+	while (count--) {
+		int hi = hex_to_bin(*src++);
+		int lo = hex_to_bin(*src++);
+
+		if ((hi < 0) || (lo < 0))
+			return -1;
+
+		*dst++ = (hi << 4) | lo;
+	}
+	return 0;
+}
+
+/**
+ * bin2hex - convert binary data to an ascii hexadecimal string
+ * @dst: ascii hexadecimal result
+ * @src: binary data
+ * @count: binary data length
+ */
+static inline char *bin2hex(char *dst, const void *src, size_t count)
+{
+	const unsigned char *_src = src;
+
+	while (count--)
+		dst = hex_byte_pack(dst, *_src++);
+	return dst;
+}
+
+int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize,
+		       char *linebuf, size_t linebuflen, bool ascii);
+void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize,
+		    int groupsize, const void *buf, size_t len, bool ascii);
+void print_hex_dump_bytes(const char *prefix_str, int prefix_type,
+			  const void *buf, size_t len);
+
+#endif /* HEXDUMP_H */
diff --git a/include/hw_sha.h b/include/hw_sha.h
new file mode 100644
index 0000000..991e496
--- /dev/null
+++ b/include/hw_sha.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Header file for SHA hardware acceleration
+ *
+ * Copyright (c) 2012  Samsung Electronics
+ */
+#ifndef __HW_SHA_H
+#define __HW_SHA_H
+#include <hash.h>
+
+/**
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr	A pointer to the input buffer
+ * @param bufleni	Byte length of input buffer
+ * @param out_addr	A pointer to the output buffer. When complete
+ *			32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ *			should allocate at least 32 bytes at pOut in advance.
+ * @param chunk_size	chunk size for sha256
+ */
+void hw_sha256(const uchar * in_addr, uint buflen,
+			uchar * out_addr, uint chunk_size);
+
+/**
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr	A pointer to the input buffer
+ * @param bufleni	Byte length of input buffer
+ * @param out_addr	A pointer to the output buffer. When complete
+ *			32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ *			should allocate at least 32 bytes at pOut in advance.
+ * @param chunk_size	chunk_size for sha1
+ */
+void hw_sha1(const uchar * in_addr, uint buflen,
+			uchar * out_addr, uint chunk_size);
+
+/*
+ * Create the context for sha progressive hashing using h/w acceleration
+ *
+ * @algo: Pointer to the hash_algo struct
+ * @ctxp: Pointer to the pointer of the context for hashing
+ * @return 0 if ok, -ve on error
+ */
+int hw_sha_init(struct hash_algo *algo, void **ctxp);
+
+/*
+ * Update buffer for sha progressive hashing using h/w acceleration
+ *
+ * The context is freed by this function if an error occurs.
+ *
+ * @algo: Pointer to the hash_algo struct
+ * @ctx: Pointer to the context for hashing
+ * @buf: Pointer to the buffer being hashed
+ * @size: Size of the buffer being hashed
+ * @is_last: 1 if this is the last update; 0 otherwise
+ * @return 0 if ok, -ve on error
+ */
+int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf,
+		     unsigned int size, int is_last);
+
+/*
+ * Copy sha hash result at destination location
+ *
+ * The context is freed after completion of hash operation or after an error.
+ *
+ * @algo: Pointer to the hash_algo struct
+ * @ctx: Pointer to the context for hashing
+ * @dest_buf: Pointer to the destination buffer where hash is to be copied
+ * @size: Size of the buffer being hashed
+ * @return 0 if ok, -ve on error
+ */
+int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf,
+		     int size);
+
+#endif
diff --git a/include/hwconfig.h b/include/hwconfig.h
new file mode 100644
index 0000000..cf47210
--- /dev/null
+++ b/include/hwconfig.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * An inteface for configuring a hardware via u-boot environment.
+ *
+ * Copyright (c) 2009  MontaVista Software, Inc.
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ */
+
+#ifndef _HWCONFIG_H
+#define _HWCONFIG_H
+
+#include <linux/types.h>
+#include <linux/errno.h>
+
+#ifdef CONFIG_HWCONFIG
+
+extern int hwconfig_f(const char *opt, char *buf);
+extern const char *hwconfig_arg_f(const char *opt, size_t *arglen, char *buf);
+extern int hwconfig_arg_cmp_f(const char *opt, const char *arg, char *buf);
+extern int hwconfig_sub_f(const char *opt, const char *subopt, char *buf);
+extern const char *hwconfig_subarg_f(const char *opt, const char *subopt,
+				     size_t *subarglen, char *buf);
+extern int hwconfig_subarg_cmp_f(const char *opt, const char *subopt,
+				 const char *subarg, char *buf);
+#else
+
+static inline int hwconfig_f(const char *opt, char *buf)
+{
+	return -ENOSYS;
+}
+
+static inline const char *hwconfig_arg_f(const char *opt, size_t *arglen,
+					 char *buf)
+{
+	*arglen = 0;
+	return "";
+}
+
+static inline int hwconfig_arg_cmp_f(const char *opt, const char *arg,
+				     char *buf)
+{
+	return -ENOSYS;
+}
+
+static inline int hwconfig_sub_f(const char *opt, const char *subopt, char *buf)
+{
+	return -ENOSYS;
+}
+
+static inline const char *hwconfig_subarg_f(const char *opt, const char *subopt,
+					    size_t *subarglen, char *buf)
+{
+	*subarglen = 0;
+	return "";
+}
+
+static inline int hwconfig_subarg_cmp_f(const char *opt, const char *subopt,
+					const char *subarg, char *buf)
+{
+	return -ENOSYS;
+}
+
+#endif /* CONFIG_HWCONFIG */
+
+static inline int hwconfig(const char *opt)
+{
+	return hwconfig_f(opt, NULL);
+}
+
+static inline const char *hwconfig_arg(const char *opt, size_t *arglen)
+{
+	return hwconfig_arg_f(opt, arglen, NULL);
+}
+
+static inline int hwconfig_arg_cmp(const char *opt, const char *arg)
+{
+	return hwconfig_arg_cmp_f(opt, arg, NULL);
+}
+
+static inline int hwconfig_sub(const char *opt, const char *subopt)
+{
+	return hwconfig_sub_f(opt, subopt, NULL);
+}
+
+static inline const char *hwconfig_subarg(const char *opt, const char *subopt,
+					  size_t *subarglen)
+{
+	return hwconfig_subarg_f(opt, subopt, subarglen, NULL);
+}
+
+static inline int hwconfig_subarg_cmp(const char *opt, const char *subopt,
+				      const char *subarg)
+{
+	return hwconfig_subarg_cmp_f(opt, subopt, subarg, NULL);
+}
+
+#endif /* _HWCONFIG_H */
diff --git a/include/hwspinlock.h b/include/hwspinlock.h
new file mode 100644
index 0000000..99389c1
--- /dev/null
+++ b/include/hwspinlock.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _HWSPINLOCK_H_
+#define _HWSPINLOCK_H_
+
+/**
+ * Implement a hwspinlock uclass.
+ * Hardware spinlocks are used to perform hardware protection of
+ * critical sections and synchronisation between multiprocessors.
+ */
+
+struct udevice;
+
+/**
+ * struct hwspinlock - A handle to (allowing control of) a single hardware
+ * spinlock.
+ *
+ * @dev: The device which implements the hardware spinlock.
+ * @id: The hardware spinlock ID within the provider.
+ */
+struct hwspinlock {
+	struct udevice *dev;
+	unsigned long id;
+};
+
+#if CONFIG_IS_ENABLED(DM_HWSPINLOCK)
+
+/**
+ * hwspinlock_get_by_index - Get a hardware spinlock by integer index
+ *
+ * This looks up and request a hardware spinlock. The index is relative to the
+ * client device; each device is assumed to have n hardware spinlock associated
+ * with it somehow, and this function finds and requests one of them.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the hardware spinlock to request, within the
+ *		client's list of hardware spinlock.
+ * @hws:	A pointer to a hardware spinlock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int hwspinlock_get_by_index(struct udevice *dev,
+			    int index, struct hwspinlock *hws);
+
+/**
+ * Lock the hardware spinlock
+ *
+ * @hws:	A hardware spinlock struct that previously requested by
+ *		hwspinlock_get_by_index
+ * @timeout:	Timeout value in msecs
+ * @return: 0 if OK, -ETIMEDOUT if timeout, -ve on other errors
+ */
+int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout);
+
+/**
+ * Unlock the hardware spinlock
+ *
+ * @hws:	A hardware spinlock struct that previously requested by
+ *		hwspinlock_get_by_index
+ * @return: 0 if OK, -ve on error
+ */
+int hwspinlock_unlock(struct hwspinlock *hws);
+
+#else
+
+static inline int hwspinlock_get_by_index(struct udevice *dev,
+					  int index,
+					  struct hwspinlock *hws)
+{
+	return -ENOSYS;
+}
+
+static inline int hwspinlock_lock_timeout(struct hwspinlock *hws,
+					  int timeout)
+{
+	return -ENOSYS;
+}
+
+static inline int hwspinlock_unlock(struct hwspinlock *hws)
+{
+	return -ENOSYS;
+}
+
+#endif /* CONFIG_DM_HWSPINLOCK */
+
+struct ofnode_phandle_args;
+
+/**
+ * struct hwspinlock_ops - Driver model hwspinlock operations
+ *
+ * The uclass interface is implemented by all hwspinlock devices which use
+ * driver model.
+ */
+struct hwspinlock_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) hardware specifier.
+	 *
+	 * The hardware core calls this function as the first step in
+	 * implementing a client's hwspinlock_get_by_*() call.
+	 *
+	 * @hws:	The hardware spinlock struct to hold the translation
+	 *			result.
+	 * @args:	The hardware spinlock specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct hwspinlock *hws,
+			struct ofnode_phandle_args *args);
+
+	/**
+	 * Lock the hardware spinlock
+	 *
+	 * @dev:	hwspinlock Device
+	 * @index:	index of the lock to be used
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*lock)(struct udevice *dev, int index);
+
+	/**
+	 * Unlock the hardware spinlock
+	 *
+	 * @dev:	hwspinlock Device
+	 * @index:	index of the lock to be unlocked
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*unlock)(struct udevice *dev, int index);
+
+	/**
+	 * Relax - optional
+	 *       Platform-specific relax method, called by hwspinlock core
+	 *       while spinning on a lock, between two successive call to
+	 *       lock
+	 *
+	 * @dev:	hwspinlock Device
+	 */
+	void (*relax)(struct udevice *dev);
+};
+
+#endif /* _HWSPINLOCK_H_ */
diff --git a/include/i2c.h b/include/i2c.h
new file mode 100644
index 0000000..33570f5
--- /dev/null
+++ b/include/i2c.h
@@ -0,0 +1,872 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2009 - 2013 Heiko Schocher <hs@denx.de>
+ * Changes for multibus/multiadapter I2C support.
+ *
+ * (C) Copyright 2001
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ *
+ * The original I2C interface was
+ *   (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
+ *   AIRVENT SAM s.p.a - RIMINI(ITALY)
+ * but has been changed substantially.
+ */
+
+#ifndef _I2C_H_
+#define _I2C_H_
+
+/*
+ * For now there are essentially two parts to this file - driver model
+ * here at the top, and the older code below (with CONFIG_SYS_I2C being
+ * most recent). The plan is to migrate everything to driver model.
+ * The driver model structures and API are separate as they are different
+ * enough as to be incompatible for compilation purposes.
+ */
+
+enum dm_i2c_chip_flags {
+	DM_I2C_CHIP_10BIT	= 1 << 0, /* Use 10-bit addressing */
+	DM_I2C_CHIP_RD_ADDRESS	= 1 << 1, /* Send address for each read byte */
+	DM_I2C_CHIP_WR_ADDRESS	= 1 << 2, /* Send address for each write byte */
+};
+
+struct udevice;
+/**
+ * struct dm_i2c_chip - information about an i2c chip
+ *
+ * An I2C chip is a device on the I2C bus. It sits at a particular address
+ * and normally supports 7-bit or 10-bit addressing.
+ *
+ * To obtain this structure, use dev_get_parent_platdata(dev) where dev is
+ * the chip to examine.
+ *
+ * @chip_addr:	Chip address on bus
+ * @offset_len: Length of offset in bytes. A single byte offset can
+ *		represent up to 256 bytes. A value larger than 1 may be
+ *		needed for larger devices.
+ * @flags:	Flags for this chip (dm_i2c_chip_flags)
+ * @emul: Emulator for this chip address (only used for emulation)
+ */
+struct dm_i2c_chip {
+	uint chip_addr;
+	uint offset_len;
+	uint flags;
+#ifdef CONFIG_SANDBOX
+	struct udevice *emul;
+	bool test_mode;
+#endif
+};
+
+/**
+ * struct dm_i2c_bus- information about an i2c bus
+ *
+ * An I2C bus contains 0 or more chips on it, each at its own address. The
+ * bus can operate at different speeds (measured in Hz, typically 100KHz
+ * or 400KHz).
+ *
+ * To obtain this structure, use dev_get_uclass_priv(bus) where bus is the
+ * I2C bus udevice.
+ *
+ * @speed_hz: Bus speed in hertz (typically 100000)
+ * @max_transaction_bytes: Maximal size of single I2C transfer
+ */
+struct dm_i2c_bus {
+	int speed_hz;
+	int max_transaction_bytes;
+};
+
+/*
+ * Not all of these flags are implemented in the U-Boot API
+ */
+enum dm_i2c_msg_flags {
+	I2C_M_TEN		= 0x0010, /* ten-bit chip address */
+	I2C_M_RD		= 0x0001, /* read data, from slave to master */
+	I2C_M_STOP		= 0x8000, /* send stop after this message */
+	I2C_M_NOSTART		= 0x4000, /* no start before this message */
+	I2C_M_REV_DIR_ADDR	= 0x2000, /* invert polarity of R/W bit */
+	I2C_M_IGNORE_NAK	= 0x1000, /* continue after NAK */
+	I2C_M_NO_RD_ACK		= 0x0800, /* skip the Ack bit on reads */
+	I2C_M_RECV_LEN		= 0x0400, /* length is first received byte */
+};
+
+/**
+ * struct i2c_msg - an I2C message
+ *
+ * @addr:	Slave address
+ * @flags:	Flags (see enum dm_i2c_msg_flags)
+ * @len:	Length of buffer in bytes, may be 0 for a probe
+ * @buf:	Buffer to send/receive, or NULL if no data
+ */
+struct i2c_msg {
+	uint addr;
+	uint flags;
+	uint len;
+	u8 *buf;
+};
+
+/**
+ * struct i2c_msg_list - a list of I2C messages
+ *
+ * This is called i2c_rdwr_ioctl_data in Linux but the name does not seem
+ * appropriate in U-Boot.
+ *
+ * @msg:	Pointer to i2c_msg array
+ * @nmsgs:	Number of elements in the array
+ */
+struct i2c_msg_list {
+	struct i2c_msg *msgs;
+	uint nmsgs;
+};
+
+/**
+ * dm_i2c_read() - read bytes from an I2C chip
+ *
+ * To obtain an I2C device (called a 'chip') given the I2C bus address you
+ * can use i2c_get_chip(). To obtain a bus by bus number use
+ * uclass_get_device_by_seq(UCLASS_I2C, <bus number>).
+ *
+ * To set the address length of a devce use i2c_set_addr_len(). It
+ * defaults to 1.
+ *
+ * @dev:	Chip to read from
+ * @offset:	Offset within chip to start reading
+ * @buffer:	Place to put data
+ * @len:	Number of bytes to read
+ *
+ * @return 0 on success, -ve on failure
+ */
+int dm_i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len);
+
+/**
+ * dm_i2c_write() - write bytes to an I2C chip
+ *
+ * See notes for dm_i2c_read() above.
+ *
+ * @dev:	Chip to write to
+ * @offset:	Offset within chip to start writing
+ * @buffer:	Buffer containing data to write
+ * @len:	Number of bytes to write
+ *
+ * @return 0 on success, -ve on failure
+ */
+int dm_i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer,
+		 int len);
+
+/**
+ * dm_i2c_probe() - probe a particular chip address
+ *
+ * This can be useful to check for the existence of a chip on the bus.
+ * It is typically implemented by writing the chip address to the bus
+ * and checking that the chip replies with an ACK.
+ *
+ * @bus:	Bus to probe
+ * @chip_addr:	7-bit address to probe (10-bit and others are not supported)
+ * @chip_flags:	Flags for the probe (see enum dm_i2c_chip_flags)
+ * @devp:	Returns the device found, or NULL if none
+ * @return 0 if a chip was found at that address, -ve if not
+ */
+int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags,
+		 struct udevice **devp);
+
+/**
+ * dm_i2c_reg_read() - Read a value from an I2C register
+ *
+ * This reads a single value from the given address in an I2C chip
+ *
+ * @dev:	Device to use for transfer
+ * @addr:	Address to read from
+ * @return value read, or -ve on error
+ */
+int dm_i2c_reg_read(struct udevice *dev, uint offset);
+
+/**
+ * dm_i2c_reg_write() - Write a value to an I2C register
+ *
+ * This writes a single value to the given address in an I2C chip
+ *
+ * @dev:	Device to use for transfer
+ * @addr:	Address to write to
+ * @val:	Value to write (normally a byte)
+ * @return 0 on success, -ve on error
+ */
+int dm_i2c_reg_write(struct udevice *dev, uint offset, unsigned int val);
+
+/**
+ * dm_i2c_xfer() - Transfer messages over I2C
+ *
+ * This transfers a raw message. It is best to use dm_i2c_reg_read/write()
+ * instead.
+ *
+ * @dev:	Device to use for transfer
+ * @msg:	List of messages to transfer
+ * @nmsgs:	Number of messages to transfer
+ * @return 0 on success, -ve on error
+ */
+int dm_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs);
+
+/**
+ * dm_i2c_set_bus_speed() - set the speed of a bus
+ *
+ * @bus:	Bus to adjust
+ * @speed:	Requested speed in Hz
+ * @return 0 if OK, -EINVAL for invalid values
+ */
+int dm_i2c_set_bus_speed(struct udevice *bus, unsigned int speed);
+
+/**
+ * dm_i2c_get_bus_speed() - get the speed of a bus
+ *
+ * @bus:	Bus to check
+ * @return speed of selected I2C bus in Hz, -ve on error
+ */
+int dm_i2c_get_bus_speed(struct udevice *bus);
+
+/**
+ * i2c_set_chip_flags() - set flags for a chip
+ *
+ * Typically addresses are 7 bits, but for 10-bit addresses you should set
+ * flags to DM_I2C_CHIP_10BIT. All accesses will then use 10-bit addressing.
+ *
+ * @dev:	Chip to adjust
+ * @flags:	New flags
+ * @return 0 if OK, -EINVAL if value is unsupported, other -ve value on error
+ */
+int i2c_set_chip_flags(struct udevice *dev, uint flags);
+
+/**
+ * i2c_get_chip_flags() - get flags for a chip
+ *
+ * @dev:	Chip to check
+ * @flagsp:	Place to put flags
+ * @return 0 if OK, other -ve value on error
+ */
+int i2c_get_chip_flags(struct udevice *dev, uint *flagsp);
+
+/**
+ * i2c_set_offset_len() - set the offset length for a chip
+ *
+ * The offset used to access a chip may be up to 4 bytes long. Typically it
+ * is only 1 byte, which is enough for chips with 256 bytes of memory or
+ * registers. The default value is 1, but you can call this function to
+ * change it.
+ *
+ * @offset_len:	New offset length value (typically 1 or 2)
+ */
+int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len);
+
+/**
+ * i2c_get_offset_len() - get the offset length for a chip
+ *
+ * @return:	Current offset length value (typically 1 or 2)
+ */
+int i2c_get_chip_offset_len(struct udevice *dev);
+
+/**
+ * i2c_deblock() - recover a bus that is in an unknown state
+ *
+ * See the deblock() method in 'struct dm_i2c_ops' for full information
+ *
+ * @bus:	Bus to recover
+ * @return 0 if OK, -ve on error
+ */
+int i2c_deblock(struct udevice *bus);
+
+/**
+ * struct dm_i2c_ops - driver operations for I2C uclass
+ *
+ * Drivers should support these operations unless otherwise noted. These
+ * operations are intended to be used by uclass code, not directly from
+ * other code.
+ */
+struct dm_i2c_ops {
+	/**
+	 * xfer() - transfer a list of I2C messages
+	 *
+	 * @bus:	Bus to read from
+	 * @msg:	List of messages to transfer
+	 * @nmsgs:	Number of messages in the list
+	 * @return 0 if OK, -EREMOTEIO if the slave did not ACK a byte,
+	 *	-ECOMM if the speed cannot be supported, -EPROTO if the chip
+	 *	flags cannot be supported, other -ve value on some other error
+	 */
+	int (*xfer)(struct udevice *bus, struct i2c_msg *msg, int nmsgs);
+
+	/**
+	 * probe_chip() - probe for the presense of a chip address
+	 *
+	 * This function is optional. If omitted, the uclass will send a zero
+	 * length message instead.
+	 *
+	 * @bus:	Bus to probe
+	 * @chip_addr:	Chip address to probe
+	 * @chip_flags:	Probe flags (enum dm_i2c_chip_flags)
+	 * @return 0 if chip was found, -EREMOTEIO if not, -ENOSYS to fall back
+	 * to default probem other -ve value on error
+	 */
+	int (*probe_chip)(struct udevice *bus, uint chip_addr, uint chip_flags);
+
+	/**
+	 * set_bus_speed() - set the speed of a bus (optional)
+	 *
+	 * The bus speed value will be updated by the uclass if this function
+	 * does not return an error. This method is optional - if it is not
+	 * provided then the driver can read the speed from
+	 * dev_get_uclass_priv(bus)->speed_hz
+	 *
+	 * @bus:	Bus to adjust
+	 * @speed:	Requested speed in Hz
+	 * @return 0 if OK, -EINVAL for invalid values
+	 */
+	int (*set_bus_speed)(struct udevice *bus, unsigned int speed);
+
+	/**
+	 * get_bus_speed() - get the speed of a bus (optional)
+	 *
+	 * Normally this can be provided by the uclass, but if you want your
+	 * driver to check the bus speed by looking at the hardware, you can
+	 * implement that here. This method is optional. This method would
+	 * normally be expected to return dev_get_uclass_priv(bus)->speed_hz.
+	 *
+	 * @bus:	Bus to check
+	 * @return speed of selected I2C bus in Hz, -ve on error
+	 */
+	int (*get_bus_speed)(struct udevice *bus);
+
+	/**
+	 * set_flags() - set the flags for a chip (optional)
+	 *
+	 * This is generally implemented by the uclass, but drivers can
+	 * check the value to ensure that unsupported options are not used.
+	 * This method is optional. If provided, this method will always be
+	 * called when the flags change.
+	 *
+	 * @dev:	Chip to adjust
+	 * @flags:	New flags value
+	 * @return 0 if OK, -EINVAL if value is unsupported
+	 */
+	int (*set_flags)(struct udevice *dev, uint flags);
+
+	/**
+	 * deblock() - recover a bus that is in an unknown state
+	 *
+	 * I2C is a synchronous protocol and resets of the processor in the
+	 * middle of an access can block the I2C Bus until a powerdown of
+	 * the full unit is done. This is because slaves can be stuck
+	 * waiting for addition bus transitions for a transaction that will
+	 * never complete. Resetting the I2C master does not help. The only
+	 * way is to force the bus through a series of transitions to make
+	 * sure that all slaves are done with the transaction. This method
+	 * performs this 'deblocking' if support by the driver.
+	 *
+	 * This method is optional.
+	 */
+	int (*deblock)(struct udevice *bus);
+};
+
+#define i2c_get_ops(dev)	((struct dm_i2c_ops *)(dev)->driver->ops)
+
+/**
+ * struct i2c_mux_ops - operations for an I2C mux
+ *
+ * The current mux state is expected to be stored in the mux itself since
+ * it is the only thing that knows how to make things work. The mux can
+ * record the current state and then avoid switching unless it is necessary.
+ * So select() can be skipped if the mux is already in the correct state.
+ * Also deselect() can be made a nop if required.
+ */
+struct i2c_mux_ops {
+	/**
+	 * select() - select one of of I2C buses attached to a mux
+	 *
+	 * This will be called when there is no bus currently selected by the
+	 * mux. This method does not need to deselect the old bus since
+	 * deselect() will be already have been called if necessary.
+	 *
+	 * @mux:	Mux device
+	 * @bus:	I2C bus to select
+	 * @channel:	Channel number correponding to the bus to select
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*select)(struct udevice *mux, struct udevice *bus, uint channel);
+
+	/**
+	 * deselect() - select one of of I2C buses attached to a mux
+	 *
+	 * This is used to deselect the currently selected I2C bus.
+	 *
+	 * @mux:	Mux device
+	 * @bus:	I2C bus to deselect
+	 * @channel:	Channel number correponding to the bus to deselect
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*deselect)(struct udevice *mux, struct udevice *bus, uint channel);
+};
+
+#define i2c_mux_get_ops(dev)	((struct i2c_mux_ops *)(dev)->driver->ops)
+
+/**
+ * i2c_get_chip() - get a device to use to access a chip on a bus
+ *
+ * This returns the device for the given chip address. The device can then
+ * be used with calls to i2c_read(), i2c_write(), i2c_probe(), etc.
+ *
+ * @bus:	Bus to examine
+ * @chip_addr:	Chip address for the new device
+ * @offset_len:	Length of a register offset in bytes (normally 1)
+ * @devp:	Returns pointer to new device if found or -ENODEV if not
+ *		found
+ */
+int i2c_get_chip(struct udevice *bus, uint chip_addr, uint offset_len,
+		 struct udevice **devp);
+
+/**
+ * i2c_get_chip_for_busnum() - get a device to use to access a chip on
+ *			       a bus number
+ *
+ * This returns the device for the given chip address on a particular bus
+ * number.
+ *
+ * @busnum:	Bus number to examine
+ * @chip_addr:	Chip address for the new device
+ * @offset_len:	Length of a register offset in bytes (normally 1)
+ * @devp:	Returns pointer to new device if found or -ENODEV if not
+ *		found
+ */
+int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len,
+			    struct udevice **devp);
+
+/**
+ * i2c_chip_ofdata_to_platdata() - Decode standard I2C platform data
+ *
+ * This decodes the chip address from a device tree node and puts it into
+ * its dm_i2c_chip structure. This should be called in your driver's
+ * ofdata_to_platdata() method.
+ *
+ * @blob:	Device tree blob
+ * @node:	Node offset to read from
+ * @spi:	Place to put the decoded information
+ */
+int i2c_chip_ofdata_to_platdata(struct udevice *dev, struct dm_i2c_chip *chip);
+
+/**
+ * i2c_dump_msgs() - Dump a list of I2C messages
+ *
+ * This may be useful for debugging.
+ *
+ * @msg:	Message list to dump
+ * @nmsgs:	Number of messages
+ */
+void i2c_dump_msgs(struct i2c_msg *msg, int nmsgs);
+
+/**
+ * i2c_emul_find() - Find an emulator for an i2c sandbox device
+ *
+ * This looks at the device's 'emul' phandle
+ *
+ * @dev: Device to find an emulator for
+ * @emulp: Returns the associated emulator, if found *
+ * @return 0 if OK, -ENOENT or -ENODEV if not found
+ */
+int i2c_emul_find(struct udevice *dev, struct udevice **emulp);
+
+/**
+ * i2c_emul_get_device() - Find the device being emulated
+ *
+ * Given an emulator this returns the associated device
+ *
+ * @emul: Emulator for the device
+ * @return device that @emul is emulating
+ */
+struct udevice *i2c_emul_get_device(struct udevice *emul);
+
+#ifndef CONFIG_DM_I2C
+
+/*
+ * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
+ *
+ * The implementation MUST NOT use static or global variables if the
+ * I2C routines are used to read SDRAM configuration information
+ * because this is done before the memories are initialized. Limited
+ * use of stack-based variables are OK (the initial stack size is
+ * limited).
+ *
+ * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
+ */
+
+/*
+ * Configuration items.
+ */
+#define I2C_RXTX_LEN	128	/* maximum tx/rx buffer length */
+
+#if !defined(CONFIG_SYS_I2C_MAX_HOPS)
+/* no muxes used bus = i2c adapters */
+#define CONFIG_SYS_I2C_DIRECT_BUS	1
+#define CONFIG_SYS_I2C_MAX_HOPS		0
+#define CONFIG_SYS_NUM_I2C_BUSES	ll_entry_count(struct i2c_adapter, i2c)
+#else
+/* we use i2c muxes */
+#undef CONFIG_SYS_I2C_DIRECT_BUS
+#endif
+
+/* define the I2C bus number for RTC and DTT if not already done */
+#if !defined(CONFIG_SYS_RTC_BUS_NUM)
+#define CONFIG_SYS_RTC_BUS_NUM		0
+#endif
+#if !defined(CONFIG_SYS_SPD_BUS_NUM)
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#endif
+
+struct i2c_adapter {
+	void		(*init)(struct i2c_adapter *adap, int speed,
+				int slaveaddr);
+	int		(*probe)(struct i2c_adapter *adap, uint8_t chip);
+	int		(*read)(struct i2c_adapter *adap, uint8_t chip,
+				uint addr, int alen, uint8_t *buffer,
+				int len);
+	int		(*write)(struct i2c_adapter *adap, uint8_t chip,
+				uint addr, int alen, uint8_t *buffer,
+				int len);
+	uint		(*set_bus_speed)(struct i2c_adapter *adap,
+				uint speed);
+	int		speed;
+	int		waitdelay;
+	int		slaveaddr;
+	int		init_done;
+	int		hwadapnr;
+	char		*name;
+};
+
+#define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
+		_set_speed, _speed, _slaveaddr, _hwadapnr, _name) \
+	{ \
+		.init		=	_init, \
+		.probe		=	_probe, \
+		.read		=	_read, \
+		.write		=	_write, \
+		.set_bus_speed	=	_set_speed, \
+		.speed		=	_speed, \
+		.slaveaddr	=	_slaveaddr, \
+		.init_done	=	0, \
+		.hwadapnr	=	_hwadapnr, \
+		.name		=	#_name \
+};
+
+#define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \
+			_set_speed, _speed, _slaveaddr, _hwadapnr) \
+	ll_entry_declare(struct i2c_adapter, _name, i2c) = \
+	U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
+		 _set_speed, _speed, _slaveaddr, _hwadapnr, _name);
+
+struct i2c_adapter *i2c_get_adapter(int index);
+
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+struct i2c_mux {
+	int	id;
+	char	name[16];
+};
+
+struct i2c_next_hop {
+	struct i2c_mux		mux;
+	uint8_t		chip;
+	uint8_t		channel;
+};
+
+struct i2c_bus_hose {
+	int	adapter;
+	struct i2c_next_hop	next_hop[CONFIG_SYS_I2C_MAX_HOPS];
+};
+#define I2C_NULL_HOP	{{-1, ""}, 0, 0}
+extern struct i2c_bus_hose	i2c_bus[];
+
+#define I2C_ADAPTER(bus)	i2c_bus[bus].adapter
+#else
+#define I2C_ADAPTER(bus)	bus
+#endif
+#define	I2C_BUS			gd->cur_i2c_bus
+
+#define	I2C_ADAP_NR(bus)	i2c_get_adapter(I2C_ADAPTER(bus))
+#define	I2C_ADAP		I2C_ADAP_NR(gd->cur_i2c_bus)
+#define I2C_ADAP_HWNR		(I2C_ADAP->hwadapnr)
+
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+#define I2C_MUX_PCA9540_ID	1
+#define I2C_MUX_PCA9540		{I2C_MUX_PCA9540_ID, "PCA9540B"}
+#define I2C_MUX_PCA9542_ID	2
+#define I2C_MUX_PCA9542		{I2C_MUX_PCA9542_ID, "PCA9542A"}
+#define I2C_MUX_PCA9544_ID	3
+#define I2C_MUX_PCA9544		{I2C_MUX_PCA9544_ID, "PCA9544A"}
+#define I2C_MUX_PCA9547_ID	4
+#define I2C_MUX_PCA9547		{I2C_MUX_PCA9547_ID, "PCA9547A"}
+#define I2C_MUX_PCA9548_ID	5
+#define I2C_MUX_PCA9548		{I2C_MUX_PCA9548_ID, "PCA9548"}
+#endif
+
+#ifndef I2C_SOFT_DECLARATIONS
+# if (defined(CONFIG_AT91RM9200) || \
+	defined(CONFIG_AT91SAM9260) ||  defined(CONFIG_AT91SAM9261) || \
+	defined(CONFIG_AT91SAM9263))
+#  define I2C_SOFT_DECLARATIONS	at91_pio_t *pio	= (at91_pio_t *) ATMEL_BASE_PIOA;
+# else
+#  define I2C_SOFT_DECLARATIONS
+# endif
+#endif
+
+/*
+ * Many boards/controllers/drivers don't support an I2C slave interface so
+ * provide a default slave address for them for use in common code.  A real
+ * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
+ * support a slave interface.
+ */
+#ifndef	CONFIG_SYS_I2C_SLAVE
+#define	CONFIG_SYS_I2C_SLAVE	0xfe
+#endif
+
+/*
+ * Initialization, must be called once on start up, may be called
+ * repeatedly to change the speed and slave addresses.
+ */
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+void i2c_early_init_f(void);
+#endif
+void i2c_init(int speed, int slaveaddr);
+void i2c_init_board(void);
+
+#ifdef CONFIG_SYS_I2C
+/*
+ * i2c_get_bus_num:
+ *
+ *  Returns index of currently active I2C bus.  Zero-based.
+ */
+unsigned int i2c_get_bus_num(void);
+
+/*
+ * i2c_set_bus_num:
+ *
+ *  Change the active I2C bus.  Subsequent read/write calls will
+ *  go to this one.
+ *
+ *	bus - bus index, zero based
+ *
+ *	Returns: 0 on success, not 0 on failure
+ *
+ */
+int i2c_set_bus_num(unsigned int bus);
+
+/*
+ * i2c_init_all():
+ *
+ * Initializes all I2C adapters in the system. All i2c_adap structures must
+ * be initialized beforehead with function pointers and data, including
+ * speed and slaveaddr. Returns 0 on success, non-0 on failure.
+ */
+void i2c_init_all(void);
+
+/*
+ * Probe the given I2C chip address.  Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+int i2c_probe(uint8_t chip);
+
+/*
+ * Read/Write interface:
+ *   chip:    I2C chip address, range 0..127
+ *   addr:    Memory (register) address within the chip
+ *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
+ *              memories, 0 for register type devices with only one
+ *              register)
+ *   buffer:  Where to read/write the data
+ *   len:     How many bytes to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uint8_t chip, unsigned int addr, int alen,
+				uint8_t *buffer, int len);
+
+int i2c_write(uint8_t chip, unsigned int addr, int alen,
+				uint8_t *buffer, int len);
+
+/*
+ * Utility routines to read/write registers.
+ */
+uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);
+
+void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);
+
+/*
+ * i2c_set_bus_speed:
+ *
+ *  Change the speed of the active I2C bus
+ *
+ *	speed - bus speed in Hz
+ *
+ *	Returns: new bus speed
+ *
+ */
+unsigned int i2c_set_bus_speed(unsigned int speed);
+
+/*
+ * i2c_get_bus_speed:
+ *
+ *  Returns speed of currently active I2C bus in Hz
+ */
+
+unsigned int i2c_get_bus_speed(void);
+
+#else
+
+/*
+ * Probe the given I2C chip address.  Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+int i2c_probe(uchar chip);
+
+/*
+ * Read/Write interface:
+ *   chip:    I2C chip address, range 0..127
+ *   addr:    Memory (register) address within the chip
+ *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
+ *              memories, 0 for register type devices with only one
+ *              register)
+ *   buffer:  Where to read/write the data
+ *   len:     How many bytes to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
+
+/*
+ * Utility routines to read/write registers.
+ */
+static inline u8 i2c_reg_read(u8 addr, u8 reg)
+{
+	u8 buf;
+
+#ifdef DEBUG
+	printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
+#endif
+
+	i2c_read(addr, reg, 1, &buf, 1);
+
+	return buf;
+}
+
+static inline void i2c_reg_write(u8 addr, u8 reg, u8 val)
+{
+#ifdef DEBUG
+	printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n",
+	       __func__, addr, reg, val);
+#endif
+
+	i2c_write(addr, reg, 1, &val, 1);
+}
+
+/*
+ * Functions for setting the current I2C bus and its speed
+ */
+
+/*
+ * i2c_set_bus_num:
+ *
+ *  Change the active I2C bus.  Subsequent read/write calls will
+ *  go to this one.
+ *
+ *	bus - bus index, zero based
+ *
+ *	Returns: 0 on success, not 0 on failure
+ *
+ */
+int i2c_set_bus_num(unsigned int bus);
+
+/*
+ * i2c_get_bus_num:
+ *
+ *  Returns index of currently active I2C bus.  Zero-based.
+ */
+
+unsigned int i2c_get_bus_num(void);
+
+/*
+ * i2c_set_bus_speed:
+ *
+ *  Change the speed of the active I2C bus
+ *
+ *	speed - bus speed in Hz
+ *
+ *	Returns: 0 on success, not 0 on failure
+ *
+ */
+int i2c_set_bus_speed(unsigned int);
+
+/*
+ * i2c_get_bus_speed:
+ *
+ *  Returns speed of currently active I2C bus in Hz
+ */
+
+unsigned int i2c_get_bus_speed(void);
+#endif /* CONFIG_SYS_I2C */
+
+/*
+ * only for backwardcompatibility, should go away if we switched
+ * completely to new multibus support.
+ */
+#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
+# if !defined(CONFIG_SYS_MAX_I2C_BUS)
+#  define CONFIG_SYS_MAX_I2C_BUS		2
+# endif
+# define I2C_MULTI_BUS				1
+#else
+# define CONFIG_SYS_MAX_I2C_BUS		1
+# define I2C_MULTI_BUS				0
+#endif
+
+/* NOTE: These two functions MUST be always_inline to avoid code growth! */
+static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
+static inline unsigned int I2C_GET_BUS(void)
+{
+	return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
+}
+
+static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
+static inline void I2C_SET_BUS(unsigned int bus)
+{
+	if (I2C_MULTI_BUS)
+		i2c_set_bus_num(bus);
+}
+
+/* Multi I2C definitions */
+enum {
+	I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
+	I2C_8, I2C_9, I2C_10,
+};
+
+/**
+ * Get FDT values for i2c bus.
+ *
+ * @param blob  Device tree blbo
+ * @return the number of I2C bus
+ */
+void board_i2c_init(const void *blob);
+
+/**
+ * Find the I2C bus number by given a FDT I2C node.
+ *
+ * @param blob  Device tree blbo
+ * @param node  FDT I2C node to find
+ * @return the number of I2C bus (zero based), or -1 on error
+ */
+int i2c_get_bus_num_fdt(int node);
+
+/**
+ * Reset the I2C bus represented by the given a FDT I2C node.
+ *
+ * @param blob  Device tree blbo
+ * @param node  FDT I2C node to find
+ * @return 0 if port was reset, -1 if not found
+ */
+int i2c_reset_port_fdt(const void *blob, int node);
+
+#endif /* !CONFIG_DM_I2C */
+
+#endif	/* _I2C_H_ */
diff --git a/include/i2c_eeprom.h b/include/i2c_eeprom.h
new file mode 100644
index 0000000..0fcdf38
--- /dev/null
+++ b/include/i2c_eeprom.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc
+ */
+
+#ifndef __I2C_EEPROM
+#define __I2C_EEPROM
+
+struct i2c_eeprom_ops {
+	int (*read)(struct udevice *dev, int offset, uint8_t *buf, int size);
+	int (*write)(struct udevice *dev, int offset, const uint8_t *buf,
+		     int size);
+};
+
+struct i2c_eeprom {
+	/* The EEPROM's page size in byte */
+	unsigned long pagesize;
+	/* The EEPROM's page width in bits (pagesize = 2^pagewidth) */
+	unsigned pagewidth;
+};
+
+/*
+ * i2c_eeprom_read() - read bytes from an I2C EEPROM chip
+ *
+ * @dev:	Chip to read from
+ * @offset:	Offset within chip to start reading
+ * @buf:	Place to put data
+ * @size:	Number of bytes to read
+ *
+ * @return 0 on success, -ve on failure
+ */
+int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size);
+
+/*
+ * i2c_eeprom_write() - write bytes to an I2C EEPROM chip
+ *
+ * @dev:	Chip to write to
+ * @offset:	Offset within chip to start writing
+ * @buf:	Buffer containing data to write
+ * @size:	Number of bytes to write
+ *
+ * @return 0 on success, -ve on failure
+ */
+int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size);
+
+#endif
diff --git a/include/i2s.h b/include/i2s.h
new file mode 100644
index 0000000..7760aab
--- /dev/null
+++ b/include/i2s.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ */
+
+#ifndef __I2S_H__
+#define __I2S_H__
+
+/*
+ * DAI hardware audio formats.
+ *
+ * Describes the physical PCM data formating and clocking. Add new formats
+ * to the end.
+ */
+#define SND_SOC_DAIFMT_I2S		1 /* I2S mode */
+#define SND_SOC_DAIFMT_RIGHT_J		2 /* Right Justified mode */
+#define SND_SOC_DAIFMT_LEFT_J		3 /* Left Justified mode */
+#define SND_SOC_DAIFMT_DSP_A		4 /* L data MSB after FRM LRC */
+#define SND_SOC_DAIFMT_DSP_B		5 /* L data MSB during FRM LRC */
+#define SND_SOC_DAIFMT_AC97		6 /* AC97 */
+#define SND_SOC_DAIFMT_PDM		7 /* Pulse density modulation */
+
+/* left and right justified also known as MSB and LSB respectively */
+#define SND_SOC_DAIFMT_MSB		SND_SOC_DAIFMT_LEFT_J
+#define SND_SOC_DAIFMT_LSB		SND_SOC_DAIFMT_RIGHT_J
+
+/*
+ * DAI hardware signal inversions.
+ *
+ * Specifies whether the DAI can also support inverted clocks for the specified
+ * format.
+ */
+#define SND_SOC_DAIFMT_NB_NF	(1 << 8) /* normal bit clock + frame */
+#define SND_SOC_DAIFMT_NB_IF	(2 << 8) /* normal BCLK + inv FRM */
+#define SND_SOC_DAIFMT_IB_NF	(3 << 8) /* invert BCLK + nor FRM */
+#define SND_SOC_DAIFMT_IB_IF	(4 << 8) /* invert BCLK + FRM */
+
+/*
+ * DAI hardware clock masters.
+ *
+ * This is wrt the codec, the inverse is true for the interface
+ * i.e. if the codec is clk and FRM master then the interface is
+ * clk and frame slave.
+ */
+#define SND_SOC_DAIFMT_CBM_CFM	(1 << 12) /* codec clk & FRM master */
+#define SND_SOC_DAIFMT_CBS_CFM	(2 << 12) /* codec clk slave & FRM master */
+#define SND_SOC_DAIFMT_CBM_CFS	(3 << 12) /* codec clk master & frame slave */
+#define SND_SOC_DAIFMT_CBS_CFS	(4 << 12) /* codec clk & FRM slave */
+
+#define SND_SOC_DAIFMT_FORMAT_MASK	0x000f
+#define SND_SOC_DAIFMT_CLOCK_MASK	0x00f0
+#define SND_SOC_DAIFMT_INV_MASK		0x0f00
+#define SND_SOC_DAIFMT_MASTER_MASK	0xf000
+
+/*
+ * Master Clock Directions
+ */
+#define SND_SOC_CLOCK_IN		0
+#define SND_SOC_CLOCK_OUT		1
+
+/* I2S Tx Control */
+#define I2S_TX_ON	1
+#define I2S_TX_OFF	0
+
+#define FIFO_LENGTH	64
+
+/* I2s Registers */
+struct i2s_reg {
+	unsigned int con;	/* base + 0 , Control register */
+	unsigned int mod;	/* Mode register */
+	unsigned int fic;	/* FIFO control register */
+	unsigned int psr;	/* Reserved */
+	unsigned int txd;	/* Transmit data register */
+	unsigned int rxd;	/* Receive Data Register */
+};
+
+/* This structure stores the i2s related information */
+struct i2s_uc_priv {
+	unsigned int rfs;		/* LR clock frame size */
+	unsigned int bfs;		/* Bit clock frame size */
+	unsigned int audio_pll_clk;	/* Audio pll frequency in Hz */
+	unsigned int samplingrate;	/* sampling rate */
+	unsigned int bitspersample;	/* bits per sample */
+	unsigned int channels;		/* audio channels */
+	unsigned int base_address;	/* I2S Register Base */
+	unsigned int id;		/* I2S controller id */
+};
+
+/* Operations for i2s devices */
+struct i2s_ops {
+	/**
+	 * tx_data() - Transmit audio data
+	 *
+	 * @dev: I2C device
+	 * @data: Data buffer to play
+	 * @data_size: Size of data buffer in bytes
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*tx_data)(struct udevice *dev, void *data, uint data_size);
+};
+
+#define i2s_get_ops(dev)	((struct i2s_ops *)(dev)->driver->ops)
+
+/**
+ * i2s_tx_data() - Transmit audio data
+ *
+ * @dev: I2C device
+ * @data: Data buffer to play
+ * @data_size: Size of data buffer in bytes
+ * @return 0 if OK, -ve on error
+ */
+int i2s_tx_data(struct udevice *dev, void *data, uint data_size);
+
+/*
+ * Sends the given data through i2s tx
+ *
+ * @param pi2s_tx	pointer of i2s transmitter parameter structure.
+ * @param data		address of the data buffer
+ * @param data_size	size of the data (in bytes)
+ * @return		int value 0 for success, -1 in case of error
+ */
+int i2s_transfer_tx_data(struct i2s_uc_priv *pi2s_tx, void *data,
+			 uint data_size);
+
+#endif /* __I2S_H__ */
diff --git a/include/i8042.h b/include/i8042.h
new file mode 100644
index 0000000..8d69fa1
--- /dev/null
+++ b/include/i8042.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ */
+
+/* i8042.h - Intel 8042 keyboard driver header */
+
+#ifndef _I8042_H_
+#define _I8042_H_
+
+/* defines */
+
+#define I8042_DATA_REG	0x60	/* keyboard i/o buffer */
+#define I8042_STS_REG	0x64	/* keyboard status read */
+#define I8042_CMD_REG	0x64	/* keyboard ctrl write */
+
+/* Status register bit defines */
+#define STATUS_OBF	(1 << 0)
+#define STATUS_IBF	(1 << 1)
+
+/* Configuration byte bit defines */
+#define CONFIG_KIRQ_EN	(1 << 0)
+#define CONFIG_MIRQ_EN	(1 << 1)
+#define CONFIG_SET_BIST	(1 << 2)
+#define CONFIG_KCLK_DIS	(1 << 4)
+#define CONFIG_MCLK_DIS	(1 << 5)
+#define CONFIG_AT_TRANS	(1 << 6)
+
+/* i8042 commands */
+#define CMD_RD_CONFIG	0x20	/* read configuration byte */
+#define CMD_WR_CONFIG	0x60	/* write configuration byte */
+#define CMD_SELF_TEST	0xaa	/* controller self-test */
+#define CMD_KBD_DIS	0xad	/* keyboard disable */
+#define CMD_KBD_EN	0xae	/* keyboard enable */
+#define CMD_SET_KBD_LED	0xed	/* set keyboard led */
+#define CMD_DRAIN_OUTPUT 0xf4   /* drain output buffer */
+#define CMD_RESET_KBD	0xff	/* reset keyboard */
+
+/* i8042 command result */
+#define KBC_TEST_OK	0x55
+#define KBD_ACK		0xfa
+#define KBD_POR		0xaa
+
+/* keyboard scan codes */
+
+#define KBD_US		0	/* default US layout */
+#define KBD_GER		1	/* german layout */
+
+#define KBD_TIMEOUT	1000	/* 1 sec */
+#define KBD_RESET_TRIES	3
+
+#define AS		0	/* normal character index */
+#define SH		1	/* shift index */
+#define CN		2	/* control index */
+#define NM		3	/* numeric lock index */
+#define AK		4	/* right alt key */
+#define CP		5	/* capslock index */
+#define ST		6	/* stop output index */
+#define EX		7	/* extended code index */
+#define ES		8	/* escape and extended code index */
+
+#define NORMAL		0x0000	/* normal key */
+#define STP		0x0001	/* scroll lock stop output*/
+#define NUM		0x0002	/* numeric lock */
+#define CAPS		0x0004	/* capslock */
+#define SHIFT		0x0008	/* shift */
+#define CTRL		0x0010	/* control*/
+#define EXT		0x0020	/* extended scan code 0xe0 */
+#define ESC		0x0040	/* escape key press */
+#define E1		0x0080	/* extended scan code 0xe1 */
+#define BRK		0x0100	/* make break flag for keyboard */
+#define ALT		0x0200	/* right alt */
+
+#endif /* _I8042_H_ */
diff --git a/include/ide.h b/include/ide.h
new file mode 100644
index 0000000..1b37d67
--- /dev/null
+++ b/include/ide.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef	_IDE_H
+#define _IDE_H
+
+#include <blk.h>
+
+#define IDE_BUS(dev)	(dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
+
+#define	ATA_CURR_BASE(dev)	(CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
+extern ulong ide_bus_offset[];
+
+/*
+ * Function Prototypes
+ */
+
+void ide_init(void);
+struct blk_desc;
+struct udevice;
+#ifdef CONFIG_BLK
+ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+	       void *buffer);
+ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		const void *buffer);
+#else
+ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+	       void *buffer);
+ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
+		const void *buffer);
+#endif
+
+#ifdef CONFIG_IDE_PREINIT
+int ide_preinit(void);
+#endif
+
+#if defined(CONFIG_OF_IDE_FIXUP)
+int ide_device_present(int dev);
+#endif
+
+#if defined(CONFIG_IDE_AHB)
+unsigned char ide_read_register(int dev, unsigned int port);
+void ide_write_register(int dev, unsigned int port, unsigned char val);
+void ide_read_data(int dev, ulong *sect_buf, int words);
+void ide_write_data(int dev, const ulong *sect_buf, int words);
+#endif
+
+/*
+ * I/O function overrides
+ */
+unsigned char ide_inb(int dev, int port);
+void ide_outb(int dev, int port, unsigned char val);
+void ide_input_swap_data(int dev, ulong *sect_buf, int words);
+void ide_input_data(int dev, ulong *sect_buf, int words);
+void ide_output_data(int dev, const ulong *sect_buf, int words);
+void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts);
+void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts);
+
+void ide_led(uchar led, uchar status);
+
+/**
+ * board_start_ide() - Start up the board IDE interfac
+ *
+ * @return 0 if ok
+ */
+int board_start_ide(void);
+
+#endif /* _IDE_H */
diff --git a/include/image-android-dt.h b/include/image-android-dt.h
new file mode 100644
index 0000000..9a3aa8f
--- /dev/null
+++ b/include/image-android-dt.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ */
+
+#ifndef IMAGE_ANDROID_DT_H
+#define IMAGE_ANDROID_DT_H
+
+#include <linux/types.h>
+
+bool android_dt_check_header(ulong hdr_addr);
+bool android_dt_get_fdt_by_index(ulong hdr_addr, u32 index, ulong *addr,
+				 u32 *size);
+
+#if !defined(CONFIG_SPL_BUILD)
+void android_dt_print_contents(ulong hdr_addr);
+#endif
+
+#endif /* IMAGE_ANDROID_DT_H */
diff --git a/include/image-sparse.h b/include/image-sparse.h
new file mode 100644
index 0000000..234c237
--- /dev/null
+++ b/include/image-sparse.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#include <part.h>
+#include <sparse_format.h>
+
+#define ROUNDUP(x, y)	(((x) + ((y) - 1)) & ~((y) - 1))
+
+struct sparse_storage {
+	lbaint_t	blksz;
+	lbaint_t	start;
+	lbaint_t	size;
+	void		*priv;
+
+	lbaint_t	(*write)(struct sparse_storage *info,
+				 lbaint_t blk,
+				 lbaint_t blkcnt,
+				 const void *buffer);
+
+	lbaint_t	(*reserve)(struct sparse_storage *info,
+				 lbaint_t blk,
+				 lbaint_t blkcnt);
+
+	void		(*mssg)(const char *str, char *response);
+};
+
+static inline int is_sparse_image(void *buf)
+{
+	sparse_header_t *s_header = (sparse_header_t *)buf;
+
+	if ((le32_to_cpu(s_header->magic) == SPARSE_HEADER_MAGIC) &&
+	    (le16_to_cpu(s_header->major_version) == 1))
+		return 1;
+
+	return 0;
+}
+
+int write_sparse_image(struct sparse_storage *info, const char *part_name,
+		       void *data, char *response);
diff --git a/include/image.h b/include/image.h
new file mode 100644
index 0000000..c1065c0
--- /dev/null
+++ b/include/image.h
@@ -0,0 +1,1422 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __IMAGE_H__
+#define __IMAGE_H__
+
+#include "compiler.h"
+#include <asm/byteorder.h>
+#include <stdbool.h>
+
+/* Define this to avoid #ifdefs later on */
+struct lmb;
+struct fdt_region;
+
+#ifdef USE_HOSTCC
+#include <sys/types.h>
+
+/* new uImage format support enabled on host */
+#define IMAGE_ENABLE_FIT	1
+#define IMAGE_ENABLE_OF_LIBFDT	1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT 1
+#define CONFIG_FIT_ENABLE_SHA256_SUPPORT
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+
+#define IMAGE_ENABLE_IGNORE	0
+#define IMAGE_INDENT_STRING	""
+
+#else
+
+#include <lmb.h>
+#include <asm/u-boot.h>
+#include <command.h>
+
+/* Take notice of the 'ignore' property for hashes */
+#define IMAGE_ENABLE_IGNORE	1
+#define IMAGE_INDENT_STRING	"   "
+
+#define IMAGE_ENABLE_FIT	CONFIG_IS_ENABLED(FIT)
+#define IMAGE_ENABLE_OF_LIBFDT	CONFIG_IS_ENABLED(OF_LIBFDT)
+
+#endif /* USE_HOSTCC */
+
+#if IMAGE_ENABLE_FIT
+#include <hash.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+# ifdef CONFIG_SPL_BUILD
+#  ifdef CONFIG_SPL_CRC32_SUPPORT
+#   define IMAGE_ENABLE_CRC32	1
+#  endif
+#  ifdef CONFIG_SPL_MD5_SUPPORT
+#   define IMAGE_ENABLE_MD5	1
+#  endif
+#  ifdef CONFIG_SPL_SHA1_SUPPORT
+#   define IMAGE_ENABLE_SHA1	1
+#  endif
+# else
+#  define IMAGE_ENABLE_CRC32	1
+#  define IMAGE_ENABLE_MD5	1
+#  define IMAGE_ENABLE_SHA1	1
+# endif
+
+#ifndef IMAGE_ENABLE_CRC32
+#define IMAGE_ENABLE_CRC32	0
+#endif
+
+#ifndef IMAGE_ENABLE_MD5
+#define IMAGE_ENABLE_MD5	0
+#endif
+
+#ifndef IMAGE_ENABLE_SHA1
+#define IMAGE_ENABLE_SHA1	0
+#endif
+
+#if defined(CONFIG_FIT_ENABLE_SHA256_SUPPORT) || \
+	defined(CONFIG_SPL_SHA256_SUPPORT)
+#define IMAGE_ENABLE_SHA256	1
+#else
+#define IMAGE_ENABLE_SHA256	0
+#endif
+
+#endif /* IMAGE_ENABLE_FIT */
+
+#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
+# define IMAGE_BOOT_GET_CMDLINE		1
+#else
+# define IMAGE_BOOT_GET_CMDLINE		0
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+# define IMAGE_OF_BOARD_SETUP		1
+#else
+# define IMAGE_OF_BOARD_SETUP		0
+#endif
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+# define IMAGE_OF_SYSTEM_SETUP	1
+#else
+# define IMAGE_OF_SYSTEM_SETUP	0
+#endif
+
+enum ih_category {
+	IH_ARCH,
+	IH_COMP,
+	IH_OS,
+	IH_TYPE,
+
+	IH_COUNT,
+};
+
+/*
+ * Operating System Codes
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
+ */
+enum {
+	IH_OS_INVALID		= 0,	/* Invalid OS	*/
+	IH_OS_OPENBSD,			/* OpenBSD	*/
+	IH_OS_NETBSD,			/* NetBSD	*/
+	IH_OS_FREEBSD,			/* FreeBSD	*/
+	IH_OS_4_4BSD,			/* 4.4BSD	*/
+	IH_OS_LINUX,			/* Linux	*/
+	IH_OS_SVR4,			/* SVR4		*/
+	IH_OS_ESIX,			/* Esix		*/
+	IH_OS_SOLARIS,			/* Solaris	*/
+	IH_OS_IRIX,			/* Irix		*/
+	IH_OS_SCO,			/* SCO		*/
+	IH_OS_DELL,			/* Dell		*/
+	IH_OS_NCR,			/* NCR		*/
+	IH_OS_LYNXOS,			/* LynxOS	*/
+	IH_OS_VXWORKS,			/* VxWorks	*/
+	IH_OS_PSOS,			/* pSOS		*/
+	IH_OS_QNX,			/* QNX		*/
+	IH_OS_U_BOOT,			/* Firmware	*/
+	IH_OS_RTEMS,			/* RTEMS	*/
+	IH_OS_ARTOS,			/* ARTOS	*/
+	IH_OS_UNITY,			/* Unity OS	*/
+	IH_OS_INTEGRITY,		/* INTEGRITY	*/
+	IH_OS_OSE,			/* OSE		*/
+	IH_OS_PLAN9,			/* Plan 9	*/
+	IH_OS_OPENRTOS,		/* OpenRTOS	*/
+	IH_OS_ARM_TRUSTED_FIRMWARE,     /* ARM Trusted Firmware */
+	IH_OS_TEE,			/* Trusted Execution Environment */
+	IH_OS_OPENSBI,			/* RISC-V OpenSBI */
+
+	IH_OS_COUNT,
+};
+
+/*
+ * CPU Architecture Codes (supported by Linux)
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
+ */
+enum {
+	IH_ARCH_INVALID		= 0,	/* Invalid CPU	*/
+	IH_ARCH_ALPHA,			/* Alpha	*/
+	IH_ARCH_ARM,			/* ARM		*/
+	IH_ARCH_I386,			/* Intel x86	*/
+	IH_ARCH_IA64,			/* IA64		*/
+	IH_ARCH_MIPS,			/* MIPS		*/
+	IH_ARCH_MIPS64,			/* MIPS	 64 Bit */
+	IH_ARCH_PPC,			/* PowerPC	*/
+	IH_ARCH_S390,			/* IBM S390	*/
+	IH_ARCH_SH,			/* SuperH	*/
+	IH_ARCH_SPARC,			/* Sparc	*/
+	IH_ARCH_SPARC64,		/* Sparc 64 Bit */
+	IH_ARCH_M68K,			/* M68K		*/
+	IH_ARCH_NIOS,			/* Nios-32	*/
+	IH_ARCH_MICROBLAZE,		/* MicroBlaze   */
+	IH_ARCH_NIOS2,			/* Nios-II	*/
+	IH_ARCH_BLACKFIN,		/* Blackfin	*/
+	IH_ARCH_AVR32,			/* AVR32	*/
+	IH_ARCH_ST200,			/* STMicroelectronics ST200  */
+	IH_ARCH_SANDBOX,		/* Sandbox architecture (test only) */
+	IH_ARCH_NDS32,			/* ANDES Technology - NDS32  */
+	IH_ARCH_OPENRISC,		/* OpenRISC 1000  */
+	IH_ARCH_ARM64,			/* ARM64	*/
+	IH_ARCH_ARC,			/* Synopsys DesignWare ARC */
+	IH_ARCH_X86_64,			/* AMD x86_64, Intel and Via */
+	IH_ARCH_XTENSA,			/* Xtensa	*/
+	IH_ARCH_RISCV,			/* RISC-V */
+
+	IH_ARCH_COUNT,
+};
+
+/*
+ * Image Types
+ *
+ * "Standalone Programs" are directly runnable in the environment
+ *	provided by U-Boot; it is expected that (if they behave
+ *	well) you can continue to work in U-Boot after return from
+ *	the Standalone Program.
+ * "OS Kernel Images" are usually images of some Embedded OS which
+ *	will take over control completely. Usually these programs
+ *	will install their own set of exception handlers, device
+ *	drivers, set up the MMU, etc. - this means, that you cannot
+ *	expect to re-enter U-Boot except by resetting the CPU.
+ * "RAMDisk Images" are more or less just data blocks, and their
+ *	parameters (address, size) are passed to an OS kernel that is
+ *	being started.
+ * "Multi-File Images" contain several images, typically an OS
+ *	(Linux) kernel image and one or more data images like
+ *	RAMDisks. This construct is useful for instance when you want
+ *	to boot over the network using BOOTP etc., where the boot
+ *	server provides just a single image file, but you want to get
+ *	for instance an OS kernel and a RAMDisk image.
+ *
+ *	"Multi-File Images" start with a list of image sizes, each
+ *	image size (in bytes) specified by an "uint32_t" in network
+ *	byte order. This list is terminated by an "(uint32_t)0".
+ *	Immediately after the terminating 0 follow the images, one by
+ *	one, all aligned on "uint32_t" boundaries (size rounded up to
+ *	a multiple of 4 bytes - except for the last file).
+ *
+ * "Firmware Images" are binary images containing firmware (like
+ *	U-Boot or FPGA images) which usually will be programmed to
+ *	flash memory.
+ *
+ * "Script files" are command sequences that will be executed by
+ *	U-Boot's command interpreter; this feature is especially
+ *	useful when you configure U-Boot to use a real shell (hush)
+ *	as command interpreter (=> Shell Scripts).
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
+ */
+
+enum {
+	IH_TYPE_INVALID		= 0,	/* Invalid Image		*/
+	IH_TYPE_STANDALONE,		/* Standalone Program		*/
+	IH_TYPE_KERNEL,			/* OS Kernel Image		*/
+	IH_TYPE_RAMDISK,		/* RAMDisk Image		*/
+	IH_TYPE_MULTI,			/* Multi-File Image		*/
+	IH_TYPE_FIRMWARE,		/* Firmware Image		*/
+	IH_TYPE_SCRIPT,			/* Script file			*/
+	IH_TYPE_FILESYSTEM,		/* Filesystem Image (any type)	*/
+	IH_TYPE_FLATDT,			/* Binary Flat Device Tree Blob	*/
+	IH_TYPE_KWBIMAGE,		/* Kirkwood Boot Image		*/
+	IH_TYPE_IMXIMAGE,		/* Freescale IMXBoot Image	*/
+	IH_TYPE_UBLIMAGE,		/* Davinci UBL Image		*/
+	IH_TYPE_OMAPIMAGE,		/* TI OMAP Config Header Image	*/
+	IH_TYPE_AISIMAGE,		/* TI Davinci AIS Image		*/
+	/* OS Kernel Image, can run from any load address */
+	IH_TYPE_KERNEL_NOLOAD,
+	IH_TYPE_PBLIMAGE,		/* Freescale PBL Boot Image	*/
+	IH_TYPE_MXSIMAGE,		/* Freescale MXSBoot Image	*/
+	IH_TYPE_GPIMAGE,		/* TI Keystone GPHeader Image	*/
+	IH_TYPE_ATMELIMAGE,		/* ATMEL ROM bootable Image	*/
+	IH_TYPE_SOCFPGAIMAGE,		/* Altera SOCFPGA CV/AV Preloader */
+	IH_TYPE_X86_SETUP,		/* x86 setup.bin Image		*/
+	IH_TYPE_LPC32XXIMAGE,		/* x86 setup.bin Image		*/
+	IH_TYPE_LOADABLE,		/* A list of typeless images	*/
+	IH_TYPE_RKIMAGE,		/* Rockchip Boot Image		*/
+	IH_TYPE_RKSD,			/* Rockchip SD card		*/
+	IH_TYPE_RKSPI,			/* Rockchip SPI image		*/
+	IH_TYPE_ZYNQIMAGE,		/* Xilinx Zynq Boot Image */
+	IH_TYPE_ZYNQMPIMAGE,		/* Xilinx ZynqMP Boot Image */
+	IH_TYPE_ZYNQMPBIF,		/* Xilinx ZynqMP Boot Image (bif) */
+	IH_TYPE_FPGA,			/* FPGA Image */
+	IH_TYPE_VYBRIDIMAGE,	/* VYBRID .vyb Image */
+	IH_TYPE_TEE,            /* Trusted Execution Environment OS Image */
+	IH_TYPE_FIRMWARE_IVT,		/* Firmware Image with HABv4 IVT */
+	IH_TYPE_PMMC,            /* TI Power Management Micro-Controller Firmware */
+	IH_TYPE_STM32IMAGE,		/* STMicroelectronics STM32 Image */
+	IH_TYPE_SOCFPGAIMAGE_V1,	/* Altera SOCFPGA A10 Preloader	*/
+	IH_TYPE_MTKIMAGE,		/* MediaTek BootROM loadable Image */
+	IH_TYPE_IMX8MIMAGE,		/* Freescale IMX8MBoot Image	*/
+	IH_TYPE_IMX8IMAGE,		/* Freescale IMX8Boot Image	*/
+	IH_TYPE_COPRO,			/* Coprocessor Image for remoteproc*/
+
+	IH_TYPE_COUNT,			/* Number of image types */
+};
+
+/*
+ * Compression Types
+ *
+ * The following are exposed to uImage header.
+ * New IDs *MUST* be appended at the end of the list and *NEVER*
+ * inserted for backward compatibility.
+ */
+enum {
+	IH_COMP_NONE		= 0,	/*  No	 Compression Used	*/
+	IH_COMP_GZIP,			/* gzip	 Compression Used	*/
+	IH_COMP_BZIP2,			/* bzip2 Compression Used	*/
+	IH_COMP_LZMA,			/* lzma  Compression Used	*/
+	IH_COMP_LZO,			/* lzo   Compression Used	*/
+	IH_COMP_LZ4,			/* lz4   Compression Used	*/
+
+	IH_COMP_COUNT,
+};
+
+#define LZ4F_MAGIC	0x184D2204	/* LZ4 Magic Number		*/
+#define IH_MAGIC	0x27051956	/* Image Magic Number		*/
+#define IH_NMLEN		32	/* Image Name Length		*/
+
+/* Reused from common.h */
+#define ROUND(a, b)		(((a) + (b) - 1) & ~((b) - 1))
+
+/*
+ * Legacy format image header,
+ * all data in network byte order (aka natural aka bigendian).
+ */
+typedef struct image_header {
+	__be32		ih_magic;	/* Image Header Magic Number	*/
+	__be32		ih_hcrc;	/* Image Header CRC Checksum	*/
+	__be32		ih_time;	/* Image Creation Timestamp	*/
+	__be32		ih_size;	/* Image Data Size		*/
+	__be32		ih_load;	/* Data	 Load  Address		*/
+	__be32		ih_ep;		/* Entry Point Address		*/
+	__be32		ih_dcrc;	/* Image Data CRC Checksum	*/
+	uint8_t		ih_os;		/* Operating System		*/
+	uint8_t		ih_arch;	/* CPU architecture		*/
+	uint8_t		ih_type;	/* Image Type			*/
+	uint8_t		ih_comp;	/* Compression Type		*/
+	uint8_t		ih_name[IH_NMLEN];	/* Image Name		*/
+} image_header_t;
+
+typedef struct image_info {
+	ulong		start, end;		/* start/end of blob */
+	ulong		image_start, image_len; /* start of image within blob, len of image */
+	ulong		load;			/* load addr for the image */
+	uint8_t		comp, type, os;		/* compression, type of image, os type */
+	uint8_t		arch;			/* CPU architecture */
+} image_info_t;
+
+/*
+ * Legacy and FIT format headers used by do_bootm() and do_bootm_<os>()
+ * routines.
+ */
+typedef struct bootm_headers {
+	/*
+	 * Legacy os image header, if it is a multi component image
+	 * then boot_get_ramdisk() and get_fdt() will attempt to get
+	 * data from second and third component accordingly.
+	 */
+	image_header_t	*legacy_hdr_os;		/* image header pointer */
+	image_header_t	legacy_hdr_os_copy;	/* header copy */
+	ulong		legacy_hdr_valid;
+
+#if IMAGE_ENABLE_FIT
+	const char	*fit_uname_cfg;	/* configuration node unit name */
+
+	void		*fit_hdr_os;	/* os FIT image header */
+	const char	*fit_uname_os;	/* os subimage node unit name */
+	int		fit_noffset_os;	/* os subimage node offset */
+
+	void		*fit_hdr_rd;	/* init ramdisk FIT image header */
+	const char	*fit_uname_rd;	/* init ramdisk subimage node unit name */
+	int		fit_noffset_rd;	/* init ramdisk subimage node offset */
+
+	void		*fit_hdr_fdt;	/* FDT blob FIT image header */
+	const char	*fit_uname_fdt;	/* FDT blob subimage node unit name */
+	int		fit_noffset_fdt;/* FDT blob subimage node offset */
+
+	void		*fit_hdr_setup;	/* x86 setup FIT image header */
+	const char	*fit_uname_setup; /* x86 setup subimage node name */
+	int		fit_noffset_setup;/* x86 setup subimage node offset */
+#endif
+
+#ifndef USE_HOSTCC
+	image_info_t	os;		/* os image info */
+	ulong		ep;		/* entry point of OS */
+
+	ulong		rd_start, rd_end;/* ramdisk start/end */
+
+	char		*ft_addr;	/* flat dev tree address */
+	ulong		ft_len;		/* length of flat device tree */
+
+	ulong		initrd_start;
+	ulong		initrd_end;
+	ulong		cmdline_start;
+	ulong		cmdline_end;
+	bd_t		*kbd;
+#endif
+
+	int		verify;		/* env_get("verify")[0] != 'n' */
+
+#define	BOOTM_STATE_START	(0x00000001)
+#define	BOOTM_STATE_FINDOS	(0x00000002)
+#define	BOOTM_STATE_FINDOTHER	(0x00000004)
+#define	BOOTM_STATE_LOADOS	(0x00000008)
+#define	BOOTM_STATE_RAMDISK	(0x00000010)
+#define	BOOTM_STATE_FDT		(0x00000020)
+#define	BOOTM_STATE_OS_CMDLINE	(0x00000040)
+#define	BOOTM_STATE_OS_BD_T	(0x00000080)
+#define	BOOTM_STATE_OS_PREP	(0x00000100)
+#define	BOOTM_STATE_OS_FAKE_GO	(0x00000200)	/* 'Almost' run the OS */
+#define	BOOTM_STATE_OS_GO	(0x00000400)
+	int		state;
+
+#ifdef CONFIG_LMB
+	struct lmb	lmb;		/* for memory mgmt */
+#endif
+} bootm_headers_t;
+
+extern bootm_headers_t images;
+
+/*
+ * Some systems (for example LWMON) have very short watchdog periods;
+ * we must make sure to split long operations like memmove() or
+ * checksum calculations into reasonable chunks.
+ */
+#ifndef CHUNKSZ
+#define CHUNKSZ (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_CRC32
+#define CHUNKSZ_CRC32 (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_MD5
+#define CHUNKSZ_MD5 (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_SHA1
+#define CHUNKSZ_SHA1 (64 * 1024)
+#endif
+
+#define uimage_to_cpu(x)		be32_to_cpu(x)
+#define cpu_to_uimage(x)		cpu_to_be32(x)
+
+/*
+ * Translation table for entries of a specific type; used by
+ * get_table_entry_id() and get_table_entry_name().
+ */
+typedef struct table_entry {
+	int	id;
+	char	*sname;		/* short (input) name to find table entry */
+	char	*lname;		/* long (output) name to print for messages */
+} table_entry_t;
+
+/*
+ * get_table_entry_id() scans the translation table trying to find an
+ * entry that matches the given short name. If a matching entry is
+ * found, it's id is returned to the caller.
+ */
+int get_table_entry_id(const table_entry_t *table,
+		const char *table_name, const char *name);
+/*
+ * get_table_entry_name() scans the translation table trying to find
+ * an entry that matches the given id. If a matching entry is found,
+ * its long name is returned to the caller.
+ */
+char *get_table_entry_name(const table_entry_t *table, char *msg, int id);
+
+const char *genimg_get_os_name(uint8_t os);
+
+/**
+ * genimg_get_os_short_name() - get the short name for an OS
+ *
+ * @param os	OS (IH_OS_...)
+ * @return OS short name, or "unknown" if unknown
+ */
+const char *genimg_get_os_short_name(uint8_t comp);
+
+const char *genimg_get_arch_name(uint8_t arch);
+
+/**
+ * genimg_get_arch_short_name() - get the short name for an architecture
+ *
+ * @param arch	Architecture type (IH_ARCH_...)
+ * @return architecture short name, or "unknown" if unknown
+ */
+const char *genimg_get_arch_short_name(uint8_t arch);
+
+const char *genimg_get_type_name(uint8_t type);
+
+/**
+ * genimg_get_type_short_name() - get the short name for an image type
+ *
+ * @param type	Image type (IH_TYPE_...)
+ * @return image short name, or "unknown" if unknown
+ */
+const char *genimg_get_type_short_name(uint8_t type);
+
+const char *genimg_get_comp_name(uint8_t comp);
+
+/**
+ * genimg_get_comp_short_name() - get the short name for a compression method
+ *
+ * @param comp	compression method (IH_COMP_...)
+ * @return compression method short name, or "unknown" if unknown
+ */
+const char *genimg_get_comp_short_name(uint8_t comp);
+
+/**
+ * genimg_get_cat_name() - Get the name of an item in a category
+ *
+ * @category:	Category of item
+ * @id:		Item ID
+ * @return name of item, or "Unknown ..." if unknown
+ */
+const char *genimg_get_cat_name(enum ih_category category, uint id);
+
+/**
+ * genimg_get_cat_short_name() - Get the short name of an item in a category
+ *
+ * @category:	Category of item
+ * @id:		Item ID
+ * @return short name of item, or "Unknown ..." if unknown
+ */
+const char *genimg_get_cat_short_name(enum ih_category category, uint id);
+
+/**
+ * genimg_get_cat_count() - Get the number of items in a category
+ *
+ * @category:	Category to check
+ * @return the number of items in the category (IH_xxx_COUNT)
+ */
+int genimg_get_cat_count(enum ih_category category);
+
+/**
+ * genimg_get_cat_desc() - Get the description of a category
+ *
+ * @return the description of a category, e.g. "architecture". This
+ * effectively converts the enum to a string.
+ */
+const char *genimg_get_cat_desc(enum ih_category category);
+
+int genimg_get_os_id(const char *name);
+int genimg_get_arch_id(const char *name);
+int genimg_get_type_id(const char *name);
+int genimg_get_comp_id(const char *name);
+void genimg_print_size(uint32_t size);
+
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \
+	defined(USE_HOSTCC)
+#define IMAGE_ENABLE_TIMESTAMP 1
+#else
+#define IMAGE_ENABLE_TIMESTAMP 0
+#endif
+void genimg_print_time(time_t timestamp);
+
+/* What to do with a image load address ('load = <> 'in the FIT) */
+enum fit_load_op {
+	FIT_LOAD_IGNORED,	/* Ignore load address */
+	FIT_LOAD_OPTIONAL,	/* Can be provided, but optional */
+	FIT_LOAD_OPTIONAL_NON_ZERO,	/* Optional, a value of 0 is ignored */
+	FIT_LOAD_REQUIRED,	/* Must be provided */
+};
+
+int boot_get_setup(bootm_headers_t *images, uint8_t arch, ulong *setup_start,
+		   ulong *setup_len);
+
+#ifndef USE_HOSTCC
+/* Image format types, returned by _get_format() routine */
+#define IMAGE_FORMAT_INVALID	0x00
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
+#define IMAGE_FORMAT_LEGACY	0x01	/* legacy image_header based format */
+#endif
+#define IMAGE_FORMAT_FIT	0x02	/* new, libfdt based format */
+#define IMAGE_FORMAT_ANDROID	0x03	/* Android boot image */
+
+ulong genimg_get_kernel_addr_fit(char * const img_addr,
+			         const char **fit_uname_config,
+			         const char **fit_uname_kernel);
+ulong genimg_get_kernel_addr(char * const img_addr);
+int genimg_get_format(const void *img_addr);
+int genimg_has_config(bootm_headers_t *images);
+
+int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
+		uint8_t arch, const ulong *ld_start, ulong * const ld_len);
+int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
+		uint8_t arch, ulong *rd_start, ulong *rd_end);
+
+/**
+ * boot_get_loadable - routine to load a list of binaries to memory
+ * @argc: Ignored Argument
+ * @argv: Ignored Argument
+ * @images: pointer to the bootm images structure
+ * @arch: expected architecture for the image
+ * @ld_start: Ignored Argument
+ * @ld_len: Ignored Argument
+ *
+ * boot_get_loadable() will take the given FIT configuration, and look
+ * for a field named "loadables".  Loadables, is a list of elements in
+ * the FIT given as strings.  exe:
+ *   loadables = "linux_kernel", "fdt-2";
+ * this function will attempt to parse each string, and load the
+ * corresponding element from the FIT into memory.  Once placed,
+ * no aditional actions are taken.
+ *
+ * @return:
+ *     0, if only valid images or no images are found
+ *     error code, if an error occurs during fit_image_load
+ */
+int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images,
+		uint8_t arch, const ulong *ld_start, ulong * const ld_len);
+#endif /* !USE_HOSTCC */
+
+int boot_get_setup_fit(bootm_headers_t *images, uint8_t arch,
+		       ulong *setup_start, ulong *setup_len);
+
+/**
+ * boot_get_fdt_fit() - load a DTB from a FIT file (applying overlays)
+ *
+ * This deals with all aspects of loading an DTB from a FIT.
+ * The correct base image based on configuration will be selected, and
+ * then any overlays specified will be applied (as present in fit_uname_configp).
+ *
+ * @param images	Boot images structure
+ * @param addr		Address of FIT in memory
+ * @param fit_unamep	On entry this is the requested image name
+ *			(e.g. "kernel") or NULL to use the default. On exit
+ *			points to the selected image name
+ * @param fit_uname_configp	On entry this is the requested configuration
+ *			name (e.g. "conf-1") or NULL to use the default. On
+ *			exit points to the selected configuration name.
+ * @param arch		Expected architecture (IH_ARCH_...)
+ * @param datap		Returns address of loaded image
+ * @param lenp		Returns length of loaded image
+ *
+ * @return node offset of base image, or -ve error code on error
+ */
+int boot_get_fdt_fit(bootm_headers_t *images, ulong addr,
+		   const char **fit_unamep, const char **fit_uname_configp,
+		   int arch, ulong *datap, ulong *lenp);
+
+/**
+ * fit_image_load() - load an image from a FIT
+ *
+ * This deals with all aspects of loading an image from a FIT, including
+ * selecting the right image based on configuration, verifying it, printing
+ * out progress messages, checking the type/arch/os and optionally copying it
+ * to the right load address.
+ *
+ * The property to look up is defined by image_type.
+ *
+ * @param images	Boot images structure
+ * @param addr		Address of FIT in memory
+ * @param fit_unamep	On entry this is the requested image name
+ *			(e.g. "kernel") or NULL to use the default. On exit
+ *			points to the selected image name
+ * @param fit_uname_configp	On entry this is the requested configuration
+ *			name (e.g. "conf-1") or NULL to use the default. On
+ *			exit points to the selected configuration name.
+ * @param arch		Expected architecture (IH_ARCH_...)
+ * @param image_type	Required image type (IH_TYPE_...). If this is
+ *			IH_TYPE_KERNEL then we allow IH_TYPE_KERNEL_NOLOAD
+ *			also.
+ * @param bootstage_id	ID of starting bootstage to use for progress updates.
+ *			This will be added to the BOOTSTAGE_SUB values when
+ *			calling bootstage_mark()
+ * @param load_op	Decribes what to do with the load address
+ * @param datap		Returns address of loaded image
+ * @param lenp		Returns length of loaded image
+ * @return node offset of image, or -ve error code on error
+ */
+int fit_image_load(bootm_headers_t *images, ulong addr,
+		   const char **fit_unamep, const char **fit_uname_configp,
+		   int arch, int image_type, int bootstage_id,
+		   enum fit_load_op load_op, ulong *datap, ulong *lenp);
+
+#ifndef USE_HOSTCC
+/**
+ * fit_get_node_from_config() - Look up an image a FIT by type
+ *
+ * This looks in the selected conf- node (images->fit_uname_cfg) for a
+ * particular image type (e.g. "kernel") and then finds the image that is
+ * referred to.
+ *
+ * For example, for something like:
+ *
+ * images {
+ *	kernel {
+ *		...
+ *	};
+ * };
+ * configurations {
+ *	conf-1 {
+ *		kernel = "kernel";
+ *	};
+ * };
+ *
+ * the function will return the node offset of the kernel@1 node, assuming
+ * that conf-1 is the chosen configuration.
+ *
+ * @param images	Boot images structure
+ * @param prop_name	Property name to look up (FIT_..._PROP)
+ * @param addr		Address of FIT in memory
+ */
+int fit_get_node_from_config(bootm_headers_t *images, const char *prop_name,
+			ulong addr);
+
+int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
+		 bootm_headers_t *images,
+		 char **of_flat_tree, ulong *of_size);
+void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
+int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size);
+
+int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
+		  ulong *initrd_start, ulong *initrd_end);
+int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end);
+#ifdef CONFIG_SYS_BOOT_GET_KBD
+int boot_get_kbd(struct lmb *lmb, bd_t **kbd);
+#endif /* CONFIG_SYS_BOOT_GET_KBD */
+#endif /* !USE_HOSTCC */
+
+/*******************************************************************/
+/* Legacy format specific code (prefixed with image_) */
+/*******************************************************************/
+static inline uint32_t image_get_header_size(void)
+{
+	return (sizeof(image_header_t));
+}
+
+#define image_get_hdr_l(f) \
+	static inline uint32_t image_get_##f(const image_header_t *hdr) \
+	{ \
+		return uimage_to_cpu(hdr->ih_##f); \
+	}
+image_get_hdr_l(magic)		/* image_get_magic */
+image_get_hdr_l(hcrc)		/* image_get_hcrc */
+image_get_hdr_l(time)		/* image_get_time */
+image_get_hdr_l(size)		/* image_get_size */
+image_get_hdr_l(load)		/* image_get_load */
+image_get_hdr_l(ep)		/* image_get_ep */
+image_get_hdr_l(dcrc)		/* image_get_dcrc */
+
+#define image_get_hdr_b(f) \
+	static inline uint8_t image_get_##f(const image_header_t *hdr) \
+	{ \
+		return hdr->ih_##f; \
+	}
+image_get_hdr_b(os)		/* image_get_os */
+image_get_hdr_b(arch)		/* image_get_arch */
+image_get_hdr_b(type)		/* image_get_type */
+image_get_hdr_b(comp)		/* image_get_comp */
+
+static inline char *image_get_name(const image_header_t *hdr)
+{
+	return (char *)hdr->ih_name;
+}
+
+static inline uint32_t image_get_data_size(const image_header_t *hdr)
+{
+	return image_get_size(hdr);
+}
+
+/**
+ * image_get_data - get image payload start address
+ * @hdr: image header
+ *
+ * image_get_data() returns address of the image payload. For single
+ * component images it is image data start. For multi component
+ * images it points to the null terminated table of sub-images sizes.
+ *
+ * returns:
+ *     image payload data start address
+ */
+static inline ulong image_get_data(const image_header_t *hdr)
+{
+	return ((ulong)hdr + image_get_header_size());
+}
+
+static inline uint32_t image_get_image_size(const image_header_t *hdr)
+{
+	return (image_get_size(hdr) + image_get_header_size());
+}
+static inline ulong image_get_image_end(const image_header_t *hdr)
+{
+	return ((ulong)hdr + image_get_image_size(hdr));
+}
+
+#define image_set_hdr_l(f) \
+	static inline void image_set_##f(image_header_t *hdr, uint32_t val) \
+	{ \
+		hdr->ih_##f = cpu_to_uimage(val); \
+	}
+image_set_hdr_l(magic)		/* image_set_magic */
+image_set_hdr_l(hcrc)		/* image_set_hcrc */
+image_set_hdr_l(time)		/* image_set_time */
+image_set_hdr_l(size)		/* image_set_size */
+image_set_hdr_l(load)		/* image_set_load */
+image_set_hdr_l(ep)		/* image_set_ep */
+image_set_hdr_l(dcrc)		/* image_set_dcrc */
+
+#define image_set_hdr_b(f) \
+	static inline void image_set_##f(image_header_t *hdr, uint8_t val) \
+	{ \
+		hdr->ih_##f = val; \
+	}
+image_set_hdr_b(os)		/* image_set_os */
+image_set_hdr_b(arch)		/* image_set_arch */
+image_set_hdr_b(type)		/* image_set_type */
+image_set_hdr_b(comp)		/* image_set_comp */
+
+static inline void image_set_name(image_header_t *hdr, const char *name)
+{
+	strncpy(image_get_name(hdr), name, IH_NMLEN);
+}
+
+int image_check_hcrc(const image_header_t *hdr);
+int image_check_dcrc(const image_header_t *hdr);
+#ifndef USE_HOSTCC
+ulong env_get_bootm_low(void);
+phys_size_t env_get_bootm_size(void);
+phys_size_t env_get_bootm_mapsize(void);
+#endif
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz);
+
+static inline int image_check_magic(const image_header_t *hdr)
+{
+	return (image_get_magic(hdr) == IH_MAGIC);
+}
+static inline int image_check_type(const image_header_t *hdr, uint8_t type)
+{
+	return (image_get_type(hdr) == type);
+}
+static inline int image_check_arch(const image_header_t *hdr, uint8_t arch)
+{
+	return (image_get_arch(hdr) == arch) ||
+		(image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64);
+}
+static inline int image_check_os(const image_header_t *hdr, uint8_t os)
+{
+	return (image_get_os(hdr) == os);
+}
+
+ulong image_multi_count(const image_header_t *hdr);
+void image_multi_getimg(const image_header_t *hdr, ulong idx,
+			ulong *data, ulong *len);
+
+void image_print_contents(const void *hdr);
+
+#ifndef USE_HOSTCC
+static inline int image_check_target_arch(const image_header_t *hdr)
+{
+#ifndef IH_ARCH_DEFAULT
+# error "please define IH_ARCH_DEFAULT in your arch asm/u-boot.h"
+#endif
+	return image_check_arch(hdr, IH_ARCH_DEFAULT);
+}
+#endif /* USE_HOSTCC */
+
+/**
+ * image_decomp() - decompress an image
+ *
+ * @comp:	Compression algorithm that is used (IH_COMP_...)
+ * @load:	Destination load address in U-Boot memory
+ * @image_start Image start address (where we are decompressing from)
+ * @type:	OS type (IH_OS_...)
+ * @load_bug:	Place to decompress to
+ * @image_buf:	Address to decompress from
+ * @image_len:	Number of bytes in @image_buf to decompress
+ * @unc_len:	Available space for decompression
+ * @return 0 if OK, -ve on error (BOOTM_ERR_...)
+ */
+int image_decomp(int comp, ulong load, ulong image_start, int type,
+		 void *load_buf, void *image_buf, ulong image_len,
+		 uint unc_len, ulong *load_end);
+
+/**
+ * Set up properties in the FDT
+ *
+ * This sets up properties in the FDT that is to be passed to linux.
+ *
+ * @images:	Images information
+ * @blob:	FDT to update
+ * @of_size:	Size of the FDT
+ * @lmb:	Points to logical memory block structure
+ * @return 0 if ok, <0 on failure
+ */
+int image_setup_libfdt(bootm_headers_t *images, void *blob,
+		       int of_size, struct lmb *lmb);
+
+/**
+ * Set up the FDT to use for booting a kernel
+ *
+ * This performs ramdisk setup, sets up the FDT if required, and adds
+ * paramters to the FDT if libfdt is available.
+ *
+ * @param images	Images information
+ * @return 0 if ok, <0 on failure
+ */
+int image_setup_linux(bootm_headers_t *images);
+
+/**
+ * bootz_setup() - Extract stat and size of a Linux xImage
+ *
+ * @image: Address of image
+ * @start: Returns start address of image
+ * @end : Returns end address of image
+ * @return 0 if OK, 1 if the image was not recognised
+ */
+int bootz_setup(ulong image, ulong *start, ulong *end);
+
+/**
+ * Return the correct start address and size of a Linux aarch64 Image.
+ *
+ * @image: Address of image
+ * @start: Returns start address of image
+ * @size : Returns size image
+ * @force_reloc: Ignore image->ep field, always place image to RAM start
+ * @return 0 if OK, 1 if the image was not recognised
+ */
+int booti_setup(ulong image, ulong *relocated_addr, ulong *size,
+		bool force_reloc);
+
+/*******************************************************************/
+/* New uImage format specific code (prefixed with fit_) */
+/*******************************************************************/
+
+#define FIT_IMAGES_PATH		"/images"
+#define FIT_CONFS_PATH		"/configurations"
+
+/* hash/signature node */
+#define FIT_HASH_NODENAME	"hash"
+#define FIT_ALGO_PROP		"algo"
+#define FIT_VALUE_PROP		"value"
+#define FIT_IGNORE_PROP		"uboot-ignore"
+#define FIT_SIG_NODENAME	"signature"
+
+/* image node */
+#define FIT_DATA_PROP		"data"
+#define FIT_DATA_POSITION_PROP	"data-position"
+#define FIT_DATA_OFFSET_PROP	"data-offset"
+#define FIT_DATA_SIZE_PROP	"data-size"
+#define FIT_TIMESTAMP_PROP	"timestamp"
+#define FIT_DESC_PROP		"description"
+#define FIT_ARCH_PROP		"arch"
+#define FIT_TYPE_PROP		"type"
+#define FIT_OS_PROP		"os"
+#define FIT_COMP_PROP		"compression"
+#define FIT_ENTRY_PROP		"entry"
+#define FIT_LOAD_PROP		"load"
+
+/* configuration node */
+#define FIT_KERNEL_PROP		"kernel"
+#define FIT_RAMDISK_PROP	"ramdisk"
+#define FIT_FDT_PROP		"fdt"
+#define FIT_LOADABLE_PROP	"loadables"
+#define FIT_DEFAULT_PROP	"default"
+#define FIT_SETUP_PROP		"setup"
+#define FIT_FPGA_PROP		"fpga"
+#define FIT_FIRMWARE_PROP	"firmware"
+#define FIT_STANDALONE_PROP	"standalone"
+
+#define FIT_MAX_HASH_LEN	HASH_MAX_DIGEST_SIZE
+
+#if IMAGE_ENABLE_FIT
+/* cmdline argument format parsing */
+int fit_parse_conf(const char *spec, ulong addr_curr,
+		ulong *addr, const char **conf_name);
+int fit_parse_subimage(const char *spec, ulong addr_curr,
+		ulong *addr, const char **image_name);
+
+int fit_get_subimage_count(const void *fit, int images_noffset);
+void fit_print_contents(const void *fit);
+void fit_image_print(const void *fit, int noffset, const char *p);
+
+/**
+ * fit_get_end - get FIT image size
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     size of the FIT image (blob) in memory
+ */
+static inline ulong fit_get_size(const void *fit)
+{
+	return fdt_totalsize(fit);
+}
+
+/**
+ * fit_get_end - get FIT image end
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     end address of the FIT image (blob) in memory
+ */
+ulong fit_get_end(const void *fit);
+
+/**
+ * fit_get_name - get FIT node name
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     NULL, on error
+ *     pointer to node name, on success
+ */
+static inline const char *fit_get_name(const void *fit_hdr,
+		int noffset, int *len)
+{
+	return fdt_get_name(fit_hdr, noffset, len);
+}
+
+int fit_get_desc(const void *fit, int noffset, char **desc);
+int fit_get_timestamp(const void *fit, int noffset, time_t *timestamp);
+
+int fit_image_get_node(const void *fit, const char *image_uname);
+int fit_image_get_os(const void *fit, int noffset, uint8_t *os);
+int fit_image_get_arch(const void *fit, int noffset, uint8_t *arch);
+int fit_image_get_type(const void *fit, int noffset, uint8_t *type);
+int fit_image_get_comp(const void *fit, int noffset, uint8_t *comp);
+int fit_image_get_load(const void *fit, int noffset, ulong *load);
+int fit_image_get_entry(const void *fit, int noffset, ulong *entry);
+int fit_image_get_data(const void *fit, int noffset,
+				const void **data, size_t *size);
+int fit_image_get_data_offset(const void *fit, int noffset, int *data_offset);
+int fit_image_get_data_position(const void *fit, int noffset,
+				int *data_position);
+int fit_image_get_data_size(const void *fit, int noffset, int *data_size);
+int fit_image_get_data_and_size(const void *fit, int noffset,
+				const void **data, size_t *size);
+
+int fit_image_hash_get_algo(const void *fit, int noffset, char **algo);
+int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
+				int *value_len);
+
+int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
+
+/**
+ * fit_add_verification_data() - add verification data to FIT image nodes
+ *
+ * @keydir:	Directory containing keys
+ * @kwydest:	FDT blob to write public key information to
+ * @fit:	Pointer to the FIT format image header
+ * @comment:	Comment to add to signature nodes
+ * @require_keys: Mark all keys as 'required'
+ * @engine_id:	Engine to use for signing
+ * @cmdname:	Command name used when reporting errors
+ *
+ * Adds hash values for all component images in the FIT blob.
+ * Hashes are calculated for all component images which have hash subnodes
+ * with algorithm property set to one of the supported hash algorithms.
+ *
+ * Also add signatures if signature nodes are present.
+ *
+ * returns
+ *     0, on success
+ *     libfdt error code, on failure
+ */
+int fit_add_verification_data(const char *keydir, void *keydest, void *fit,
+			      const char *comment, int require_keys,
+			      const char *engine_id, const char *cmdname);
+
+int fit_image_verify_with_data(const void *fit, int image_noffset,
+			       const void *data, size_t size);
+int fit_image_verify(const void *fit, int noffset);
+int fit_config_verify(const void *fit, int conf_noffset);
+int fit_all_image_verify(const void *fit);
+int fit_image_check_os(const void *fit, int noffset, uint8_t os);
+int fit_image_check_arch(const void *fit, int noffset, uint8_t arch);
+int fit_image_check_type(const void *fit, int noffset, uint8_t type);
+int fit_image_check_comp(const void *fit, int noffset, uint8_t comp);
+int fit_check_format(const void *fit);
+
+int fit_conf_find_compat(const void *fit, const void *fdt);
+int fit_conf_get_node(const void *fit, const char *conf_uname);
+int fit_conf_get_prop_node_count(const void *fit, int noffset,
+		const char *prop_name);
+int fit_conf_get_prop_node_index(const void *fit, int noffset,
+		const char *prop_name, int index);
+
+/**
+ * fit_conf_get_prop_node() - Get node refered to by a configuration
+ * @fit:	FIT to check
+ * @noffset:	Offset of conf@xxx node to check
+ * @prop_name:	Property to read from the conf node
+ *
+ * The conf- nodes contain references to other nodes, using properties
+ * like 'kernel = "kernel"'. Given such a property name (e.g. "kernel"),
+ * return the offset of the node referred to (e.g. offset of node
+ * "/images/kernel".
+ */
+int fit_conf_get_prop_node(const void *fit, int noffset,
+		const char *prop_name);
+
+int fit_check_ramdisk(const void *fit, int os_noffset,
+		uint8_t arch, int verify);
+
+int calculate_hash(const void *data, int data_len, const char *algo,
+			uint8_t *value, int *value_len);
+
+/*
+ * At present we only support signing on the host, and verification on the
+ * device
+ */
+#if defined(USE_HOSTCC)
+# if defined(CONFIG_FIT_SIGNATURE)
+#  define IMAGE_ENABLE_SIGN	1
+#  define IMAGE_ENABLE_VERIFY	1
+#  include <openssl/evp.h>
+# else
+#  define IMAGE_ENABLE_SIGN	0
+#  define IMAGE_ENABLE_VERIFY	0
+# endif
+#else
+# define IMAGE_ENABLE_SIGN	0
+# define IMAGE_ENABLE_VERIFY	CONFIG_IS_ENABLED(FIT_SIGNATURE)
+#endif
+
+#ifdef USE_HOSTCC
+void *image_get_host_blob(void);
+void image_set_host_blob(void *host_blob);
+# define gd_fdt_blob()		image_get_host_blob()
+#else
+# define gd_fdt_blob()		(gd->fdt_blob)
+#endif
+
+#ifdef CONFIG_FIT_BEST_MATCH
+#define IMAGE_ENABLE_BEST_MATCH	1
+#else
+#define IMAGE_ENABLE_BEST_MATCH	0
+#endif
+
+/* Information passed to the signing routines */
+struct image_sign_info {
+	const char *keydir;		/* Directory conaining keys */
+	const char *keyname;		/* Name of key to use */
+	void *fit;			/* Pointer to FIT blob */
+	int node_offset;		/* Offset of signature node */
+	const char *name;		/* Algorithm name */
+	struct checksum_algo *checksum;	/* Checksum algorithm information */
+	struct padding_algo *padding;	/* Padding algorithm information */
+	struct crypto_algo *crypto;	/* Crypto algorithm information */
+	const void *fdt_blob;		/* FDT containing public keys */
+	int required_keynode;		/* Node offset of key to use: -1=any */
+	const char *require_keys;	/* Value for 'required' property */
+	const char *engine_id;		/* Engine to use for signing */
+};
+#endif /* Allow struct image_region to always be defined for rsa.h */
+
+/* A part of an image, used for hashing */
+struct image_region {
+	const void *data;
+	int size;
+};
+
+#if IMAGE_ENABLE_FIT
+
+#if IMAGE_ENABLE_VERIFY
+# include <u-boot/rsa-checksum.h>
+#endif
+struct checksum_algo {
+	const char *name;
+	const int checksum_len;
+	const int der_len;
+	const uint8_t *der_prefix;
+#if IMAGE_ENABLE_SIGN
+	const EVP_MD *(*calculate_sign)(void);
+#endif
+	int (*calculate)(const char *name,
+			 const struct image_region region[],
+			 int region_count, uint8_t *checksum);
+};
+
+struct crypto_algo {
+	const char *name;		/* Name of algorithm */
+	const int key_len;
+
+	/**
+	 * sign() - calculate and return signature for given input data
+	 *
+	 * @info:	Specifies key and FIT information
+	 * @data:	Pointer to the input data
+	 * @data_len:	Data length
+	 * @sigp:	Set to an allocated buffer holding the signature
+	 * @sig_len:	Set to length of the calculated hash
+	 *
+	 * This computes input data signature according to selected algorithm.
+	 * Resulting signature value is placed in an allocated buffer, the
+	 * pointer is returned as *sigp. The length of the calculated
+	 * signature is returned via the sig_len pointer argument. The caller
+	 * should free *sigp.
+	 *
+	 * @return: 0, on success, -ve on error
+	 */
+	int (*sign)(struct image_sign_info *info,
+		    const struct image_region region[],
+		    int region_count, uint8_t **sigp, uint *sig_len);
+
+	/**
+	 * add_verify_data() - Add verification information to FDT
+	 *
+	 * Add public key information to the FDT node, suitable for
+	 * verification at run-time. The information added depends on the
+	 * algorithm being used.
+	 *
+	 * @info:	Specifies key and FIT information
+	 * @keydest:	Destination FDT blob for public key data
+	 * @return: 0, on success, -ve on error
+	 */
+	int (*add_verify_data)(struct image_sign_info *info, void *keydest);
+
+	/**
+	 * verify() - Verify a signature against some data
+	 *
+	 * @info:	Specifies key and FIT information
+	 * @data:	Pointer to the input data
+	 * @data_len:	Data length
+	 * @sig:	Signature
+	 * @sig_len:	Number of bytes in signature
+	 * @return 0 if verified, -ve on error
+	 */
+	int (*verify)(struct image_sign_info *info,
+		      const struct image_region region[], int region_count,
+		      uint8_t *sig, uint sig_len);
+};
+
+struct padding_algo {
+	const char *name;
+	int (*verify)(struct image_sign_info *info,
+		      uint8_t *pad, int pad_len,
+		      const uint8_t *hash, int hash_len);
+};
+
+/**
+ * image_get_checksum_algo() - Look up a checksum algorithm
+ *
+ * @param full_name	Name of algorithm in the form "checksum,crypto"
+ * @return pointer to algorithm information, or NULL if not found
+ */
+struct checksum_algo *image_get_checksum_algo(const char *full_name);
+
+/**
+ * image_get_crypto_algo() - Look up a cryptosystem algorithm
+ *
+ * @param full_name	Name of algorithm in the form "checksum,crypto"
+ * @return pointer to algorithm information, or NULL if not found
+ */
+struct crypto_algo *image_get_crypto_algo(const char *full_name);
+
+/**
+ * image_get_padding_algo() - Look up a padding algorithm
+ *
+ * @param name		Name of padding algorithm
+ * @return pointer to algorithm information, or NULL if not found
+ */
+struct padding_algo *image_get_padding_algo(const char *name);
+
+/**
+ * fit_image_verify_required_sigs() - Verify signatures marked as 'required'
+ *
+ * @fit:		FIT to check
+ * @image_noffset:	Offset of image node to check
+ * @data:		Image data to check
+ * @size:		Size of image data
+ * @sig_blob:		FDT containing public keys
+ * @no_sigsp:		Returns 1 if no signatures were required, and
+ *			therefore nothing was checked. The caller may wish
+ *			to fall back to other mechanisms, or refuse to
+ *			boot.
+ * @return 0 if all verified ok, <0 on error
+ */
+int fit_image_verify_required_sigs(const void *fit, int image_noffset,
+		const char *data, size_t size, const void *sig_blob,
+		int *no_sigsp);
+
+/**
+ * fit_image_check_sig() - Check a single image signature node
+ *
+ * @fit:		FIT to check
+ * @noffset:		Offset of signature node to check
+ * @data:		Image data to check
+ * @size:		Size of image data
+ * @required_keynode:	Offset in the control FDT of the required key node,
+ *			if any. If this is given, then the image wil not
+ *			pass verification unless that key is used. If this is
+ *			-1 then any signature will do.
+ * @err_msgp:		In the event of an error, this will be pointed to a
+ *			help error string to display to the user.
+ * @return 0 if all verified ok, <0 on error
+ */
+int fit_image_check_sig(const void *fit, int noffset, const void *data,
+		size_t size, int required_keynode, char **err_msgp);
+
+/**
+ * fit_region_make_list() - Make a list of regions to hash
+ *
+ * Given a list of FIT regions (offset, size) provided by libfdt, create
+ * a list of regions (void *, size) for use by the signature creationg
+ * and verification code.
+ *
+ * @fit:		FIT image to process
+ * @fdt_regions:	Regions as returned by libfdt
+ * @count:		Number of regions returned by libfdt
+ * @region:		Place to put list of regions (NULL to allocate it)
+ * @return pointer to list of regions, or NULL if out of memory
+ */
+struct image_region *fit_region_make_list(const void *fit,
+		struct fdt_region *fdt_regions, int count,
+		struct image_region *region);
+
+static inline int fit_image_check_target_arch(const void *fdt, int node)
+{
+#ifndef USE_HOSTCC
+	return fit_image_check_arch(fdt, node, IH_ARCH_DEFAULT);
+#else
+	return 0;
+#endif
+}
+
+#ifdef CONFIG_FIT_VERBOSE
+#define fit_unsupported(msg)	printf("! %s:%d " \
+				"FIT images not supported for '%s'\n", \
+				__FILE__, __LINE__, (msg))
+
+#define fit_unsupported_reset(msg)	printf("! %s:%d " \
+				"FIT images not supported for '%s' " \
+				"- must reset board to recover!\n", \
+				__FILE__, __LINE__, (msg))
+#else
+#define fit_unsupported(msg)
+#define fit_unsupported_reset(msg)
+#endif /* CONFIG_FIT_VERBOSE */
+#endif /* CONFIG_FIT */
+
+#if defined(CONFIG_ANDROID_BOOT_IMAGE)
+struct andr_img_hdr;
+int android_image_check_header(const struct andr_img_hdr *hdr);
+int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
+			     ulong *os_data, ulong *os_len);
+int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
+			      ulong *rd_data, ulong *rd_len);
+int android_image_get_second(const struct andr_img_hdr *hdr,
+			      ulong *second_data, ulong *second_len);
+ulong android_image_get_end(const struct andr_img_hdr *hdr);
+ulong android_image_get_kload(const struct andr_img_hdr *hdr);
+ulong android_image_get_kcomp(const struct andr_img_hdr *hdr);
+void android_print_contents(const struct andr_img_hdr *hdr);
+
+#endif /* CONFIG_ANDROID_BOOT_IMAGE */
+
+/**
+ * board_fit_config_name_match() - Check for a matching board name
+ *
+ * This is used when SPL loads a FIT containing multiple device tree files
+ * and wants to work out which one to use. The description of each one is
+ * passed to this function. The description comes from the 'description' field
+ * in each (FDT) image node.
+ *
+ * @name: Device tree description
+ * @return 0 if this device tree should be used, non-zero to try the next
+ */
+int board_fit_config_name_match(const char *name);
+
+#if defined(CONFIG_SPL_FIT_IMAGE_POST_PROCESS) || \
+	defined(CONFIG_FIT_IMAGE_POST_PROCESS)
+/**
+ * board_fit_image_post_process() - Do any post-process on FIT binary data
+ *
+ * This is used to do any sort of image manipulation, verification, decryption
+ * etc. in a platform or board specific way. Obviously, anything done here would
+ * need to be comprehended in how the images were prepared before being injected
+ * into the FIT creation (i.e. the binary blobs would have been pre-processed
+ * before being added to the FIT image).
+ *
+ * @image: pointer to the image start pointer
+ * @size: pointer to the image size
+ * @return no return value (failure should be handled internally)
+ */
+void board_fit_image_post_process(void **p_image, size_t *p_size);
+#endif /* CONFIG_SPL_FIT_IMAGE_POST_PROCESS */
+
+#define FDT_ERROR	((ulong)(-1))
+
+ulong fdt_getprop_u32(const void *fdt, int node, const char *prop);
+
+/**
+ * fit_find_config_node() - Find the node for the best DTB in a FIT image
+ *
+ * A FIT image contains one or more DTBs. This function parses the
+ * configurations described in the FIT images and returns the node of
+ * the first matching DTB. To check if a DTB matches a board, this function
+ * calls board_fit_config_name_match(). If no matching DTB is found, it returns
+ * the node described by the default configuration if it exists.
+ *
+ * @fdt: pointer to flat device tree
+ * @return the node if found, -ve otherwise
+ */
+int fit_find_config_node(const void *fdt);
+
+/**
+ * Mapping of image types to function handlers to be invoked on the associated
+ * loaded images
+ *
+ * @type: Type of image, I.E. IH_TYPE_*
+ * @handler: Function to call on loaded image
+ */
+struct fit_loadable_tbl {
+	int type;
+	/**
+	 * handler() - Process a loaded image
+	 *
+	 * @data: Pointer to start of loaded image data
+	 * @size: Size of loaded image data
+	 */
+	void (*handler)(ulong data, size_t size);
+};
+
+/*
+ * Define a FIT loadable image type handler
+ *
+ * _type is a valid uimage_type ID as defined in the "Image Type" enum above
+ * _handler is the handler function to call after this image type is loaded
+ */
+#define U_BOOT_FIT_LOADABLE_HANDLER(_type, _handler) \
+	ll_entry_declare(struct fit_loadable_tbl, _function, fit_loadable) = { \
+		.type = _type, \
+		.handler = _handler, \
+	}
+
+#endif	/* __IMAGE_H__ */
diff --git a/include/imx8image.h b/include/imx8image.h
new file mode 100644
index 0000000..68ec9f5
--- /dev/null
+++ b/include/imx8image.h
@@ -0,0 +1,273 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#ifndef _IMX8IMAGE_H_
+#define _IMX8IMAGE_H_
+
+#include <image.h>
+#include <inttypes.h>
+#include "imagetool.h"
+#include "linux/kernel.h"
+
+#define __packed   __attribute__((packed))
+
+#define IV_MAX_LEN			32
+#define HASH_MAX_LEN			64
+#define MAX_NUM_IMGS			6
+#define MAX_NUM_SRK_RECORDS		4
+
+#define IVT_HEADER_TAG_B0		0x87
+#define IVT_VERSION_B0			0x00
+
+#define IMG_FLAG_HASH_SHA256		0x000
+#define IMG_FLAG_HASH_SHA384		0x100
+#define IMG_FLAG_HASH_SHA512		0x200
+
+#define IMG_FLAG_ENCRYPTED_MASK		0x400
+#define IMG_FLAG_ENCRYPTED_SHIFT	0x0A
+
+#define IMG_FLAG_BOOTFLAGS_MASK		0xFFFF0000
+#define IMG_FLAG_BOOTFLAGS_SHIFT	0x10
+
+#define IMG_ARRAY_ENTRY_SIZE		128
+#define HEADER_IMG_ARRAY_OFFSET		0x10
+
+#define HASH_TYPE_SHA_256		256
+#define HASH_TYPE_SHA_384		384
+#define HASH_TYPE_SHA_512		512
+
+#define IMAGE_HASH_ALGO_DEFAULT		384
+#define IMAGE_PADDING_DEFAULT		0x1000
+
+#define DCD_ENTRY_ADDR_IN_SCFW		0x240
+
+#define CONTAINER_ALIGNMENT		0x400
+#define CONTAINER_FLAGS_DEFAULT		0x10
+#define CONTAINER_FUSE_DEFAULT		0x0
+
+#define SIGNATURE_BLOCK_HEADER_LENGTH	0x10
+
+#define MAX_NUM_OF_CONTAINER		2
+
+#define FIRST_CONTAINER_HEADER_LENGTH	0x400
+
+#define BOOT_IMG_META_MU_RID_SHIFT	10
+#define BOOT_IMG_META_PART_ID_SHIFT	20
+
+#define IMAGE_A35_DEFAULT_META(PART)	(((PART == 0) ? \
+					 PARTITION_ID_AP : PART) << \
+					 BOOT_IMG_META_PART_ID_SHIFT | \
+					 SC_R_MU_0A << \
+					 BOOT_IMG_META_MU_RID_SHIFT | \
+					 SC_R_A35_0)
+
+#define IMAGE_A53_DEFAULT_META(PART)	(((PART == 0) ? \
+					 PARTITION_ID_AP : PART) << \
+					 BOOT_IMG_META_PART_ID_SHIFT | \
+					 SC_R_MU_0A << \
+					 BOOT_IMG_META_MU_RID_SHIFT | \
+					 SC_R_A53_0)
+
+#define IMAGE_A72_DEFAULT_META(PART)	(((PART == 0) ? \
+					 PARTITION_ID_AP : PART) << \
+					 BOOT_IMG_META_PART_ID_SHIFT | \
+					 SC_R_MU_0A << \
+					 BOOT_IMG_META_MU_RID_SHIFT | \
+					 SC_R_A72_0)
+
+#define IMAGE_M4_0_DEFAULT_META(PART)	(((PART == 0) ? \
+					 PARTITION_ID_M4 : PART) << \
+					 BOOT_IMG_META_PART_ID_SHIFT | \
+					 SC_R_M4_0_MU_1A << \
+					 BOOT_IMG_META_MU_RID_SHIFT | \
+					 SC_R_M4_0_PID0)
+
+#define IMAGE_M4_1_DEFAULT_META(PART)	(((PART == 0) ? \
+					 PARTITION_ID_M4 : PART) << \
+					 BOOT_IMG_META_PART_ID_SHIFT | \
+					 SC_R_M4_1_MU_1A << \
+					 BOOT_IMG_META_MU_RID_SHIFT | \
+					 SC_R_M4_1_PID0)
+
+#define CONTAINER_IMAGE_ARRAY_START_OFFSET	0x2000
+
+typedef struct {
+	uint8_t version;
+	uint16_t length;
+	uint8_t tag;
+	uint16_t srk_table_offset;
+	uint16_t cert_offset;
+	uint16_t blob_offset;
+	uint16_t signature_offset;
+	uint32_t reserved;
+} __packed sig_blk_hdr_t;
+
+typedef struct {
+	uint32_t offset;
+	uint32_t size;
+	uint64_t dst;
+	uint64_t entry;
+	uint32_t hab_flags;
+	uint32_t meta;
+	uint8_t hash[HASH_MAX_LEN];
+	uint8_t iv[IV_MAX_LEN];
+} __packed boot_img_t;
+
+typedef struct {
+	uint8_t version;
+	uint16_t length;
+	uint8_t tag;
+	uint32_t flags;
+	uint16_t sw_version;
+	uint8_t fuse_version;
+	uint8_t num_images;
+	uint16_t sig_blk_offset;
+	uint16_t reserved;
+	boot_img_t img[MAX_NUM_IMGS];
+	sig_blk_hdr_t sig_blk_hdr;
+	uint32_t sigblk_size;
+	uint32_t padding;
+} __packed flash_header_v3_t;
+
+typedef struct {
+	flash_header_v3_t fhdr[MAX_NUM_OF_CONTAINER];
+}  __packed imx_header_v3_t;
+
+struct image_array {
+	char *name;
+	unsigned int core_type;
+	unsigned int core_id;
+	unsigned int load_addr;
+};
+
+enum imx8image_cmd {
+	CMD_INVALID,
+	CMD_BOOT_FROM,
+	CMD_FUSE_VERSION,
+	CMD_SW_VERSION,
+	CMD_MSG_BLOCK,
+	CMD_FILEOFF,
+	CMD_FLAG,
+	CMD_APPEND,
+	CMD_PARTITION,
+	CMD_SOC_TYPE,
+	CMD_CONTAINER,
+	CMD_IMAGE,
+	CMD_DATA
+};
+
+enum imx8image_core_type {
+	CFG_CORE_INVALID,
+	CFG_SCU,
+	CFG_M40,
+	CFG_M41,
+	CFG_A35,
+	CFG_A53,
+	CFG_A72
+};
+
+enum imx8image_fld_types {
+	CFG_INVALID = -1,
+	CFG_COMMAND,
+	CFG_CORE_TYPE,
+	CFG_IMAGE_NAME,
+	CFG_LOAD_ADDR
+};
+
+typedef enum SOC_TYPE {
+	NONE = 0,
+	QX,
+	QM
+} soc_type_t;
+
+typedef enum option_type {
+	NO_IMG = 0,
+	DCD,
+	SCFW,
+	SECO,
+	M40,
+	M41,
+	AP,
+	OUTPUT,
+	SCD,
+	CSF,
+	FLAG,
+	DEVICE,
+	NEW_CONTAINER,
+	APPEND,
+	DATA,
+	PARTITION,
+	FILEOFF,
+	MSG_BLOCK
+} option_type_t;
+
+typedef struct {
+	option_type_t option;
+	char *filename;
+	uint64_t src;
+	uint64_t dst;
+	uint64_t entry;
+	uint64_t ext;
+} image_t;
+
+#define CORE_SC         1
+#define CORE_CM4_0      2
+#define CORE_CM4_1      3
+#define CORE_CA53       4
+#define CORE_CA35       4
+#define CORE_CA72       5
+#define CORE_SECO       6
+
+#define SC_R_OTP	357U
+#define SC_R_DEBUG	354U
+#define SC_R_ROM_0	236U
+
+#define MSG_DEBUG_EN	SC_R_DEBUG
+#define MSG_FUSE	SC_R_OTP
+#define MSG_FIELD	SC_R_ROM_0
+
+#define IMG_TYPE_CSF     0x01   /* CSF image type */
+#define IMG_TYPE_SCD     0x02   /* SCD image type */
+#define IMG_TYPE_EXEC    0x03   /* Executable image type */
+#define IMG_TYPE_DATA    0x04   /* Data image type */
+#define IMG_TYPE_DCD_DDR 0x05   /* DCD/DDR image type */
+#define IMG_TYPE_SECO    0x06   /* SECO image type */
+#define IMG_TYPE_PROV    0x07   /* Provisioning image type */
+#define IMG_TYPE_DEK     0x08   /* DEK validation type */
+
+#define IMG_TYPE_SHIFT   0
+#define IMG_TYPE_MASK    0x1f
+#define IMG_TYPE(x)      (((x) & IMG_TYPE_MASK) >> IMG_TYPE_SHIFT)
+
+#define BOOT_IMG_FLAGS_CORE_MASK		0xF
+#define BOOT_IMG_FLAGS_CORE_SHIFT		0x04
+#define BOOT_IMG_FLAGS_CPU_RID_MASK		0x3FF0
+#define BOOT_IMG_FLAGS_CPU_RID_SHIFT		4
+#define BOOT_IMG_FLAGS_MU_RID_MASK		0xFFC000
+#define BOOT_IMG_FLAGS_MU_RID_SHIFT		14
+#define BOOT_IMG_FLAGS_PARTITION_ID_MASK	0x1F000000
+#define BOOT_IMG_FLAGS_PARTITION_ID_SHIFT	24
+
+/* Resource id used in scfw */
+#define SC_R_A35_0		508
+#define SC_R_A53_0		1
+#define SC_R_A72_0		6
+#define SC_R_MU_0A		213
+#define SC_R_M4_0_PID0		278
+#define SC_R_M4_0_MU_1A		297
+#define SC_R_M4_1_PID0		298
+#define SC_R_M4_1_MU_1A		317
+#define PARTITION_ID_M4		0
+#define PARTITION_ID_AP		1
+
+#define IMG_STACK_SIZE	32
+
+#define append(p, s, l) do { \
+	memcpy((p), (uint8_t *)(s), (l)); (p) += (l); \
+	} while (0)
+
+#endif
diff --git a/include/imx_lpi2c.h b/include/imx_lpi2c.h
new file mode 100644
index 0000000..3ce9eda
--- /dev/null
+++ b/include/imx_lpi2c.h
@@ -0,0 +1,523 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductors, Inc.
+ *
+ * I2CLP driver for i.MX
+ *
+ */
+#ifndef __IMX_LPI2C_H__
+#define __IMX_LPI2C_H__
+
+#include <clk.h>
+
+struct imx_lpi2c_bus {
+	int index;
+	ulong base;
+	ulong driver_data;
+	int speed;
+	struct i2c_pads_info *pads_info;
+	struct udevice *bus;
+	struct clk per_clk;
+	struct clk ipg_clk;
+};
+
+struct imx_lpi2c_reg {
+	u32 verid;
+	u32 param;
+	u8  reserved_0[8];
+	u32 mcr;
+	u32 msr;
+	u32 mier;
+	u32 mder;
+	u32 mcfgr0;
+	u32 mcfgr1;
+	u32 mcfgr2;
+	u32 mcfgr3;
+	u8  reserved_1[16];
+	u32 mdmr;
+	u8  reserved_2[4];
+	u32 mccr0;
+	u8  reserved_3[4];
+	u32 mccr1;
+	u8  reserved_4[4];
+	u32 mfcr;
+	u32 mfsr;
+	u32 mtdr;
+	u8  reserved_5[12];
+	u32 mrdr;
+	u8  reserved_6[156];
+	u32 scr;
+	u32 ssr;
+	u32 sier;
+	u32 sder;
+	u8  reserved_7[4];
+	u32 scfgr1;
+	u32 scfgr2;
+	u8  reserved_8[20];
+	u32 samr;
+	u8  reserved_9[12];
+	u32 sasr;
+	u32 star;
+	u8  reserved_10[8];
+	u32 stdr;
+	u8  reserved_11[12];
+	u32 srdr;
+};
+
+typedef enum lpi2c_status {
+	LPI2C_SUCESS = 0,
+	LPI2C_END_PACKET_ERR,
+	LPI2C_STOP_ERR,
+	LPI2C_NAK_ERR,
+	LPI2C_ARB_LOST_ERR,
+	LPI2C_FIFO_ERR,
+	LPI2C_PIN_LOW_TIMEOUT_ERR,
+	LPI2C_DATA_MATCH_ERR,
+	LPI2C_BUSY,
+	LPI2C_IDLE,
+	LPI2C_BIT_ERR,
+	LPI2C_NO_TRANS_PROG,
+	LPI2C_DMA_REQ_FAIL,
+} lpi2c_status_t;
+
+/* ----------------------------------------------------------------------------
+   -- LPI2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+#define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
+#define LPI2C_VERID_FEATURE_SHIFT                (0U)
+#define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
+#define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
+#define LPI2C_VERID_MINOR_SHIFT                  (16U)
+#define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
+#define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
+#define LPI2C_VERID_MAJOR_SHIFT                  (24U)
+#define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
+
+/*! @name PARAM - Parameter Register */
+#define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
+#define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
+#define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
+#define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
+#define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
+#define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
+
+/*! @name MCR - Master Control Register */
+#define LPI2C_MCR_MEN_MASK                       (0x1U)
+#define LPI2C_MCR_MEN_SHIFT                      (0U)
+#define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
+#define LPI2C_MCR_RST_MASK                       (0x2U)
+#define LPI2C_MCR_RST_SHIFT                      (1U)
+#define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
+#define LPI2C_MCR_DOZEN_MASK                     (0x4U)
+#define LPI2C_MCR_DOZEN_SHIFT                    (2U)
+#define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
+#define LPI2C_MCR_DBGEN_MASK                     (0x8U)
+#define LPI2C_MCR_DBGEN_SHIFT                    (3U)
+#define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
+#define LPI2C_MCR_RTF_MASK                       (0x100U)
+#define LPI2C_MCR_RTF_SHIFT                      (8U)
+#define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
+#define LPI2C_MCR_RRF_MASK                       (0x200U)
+#define LPI2C_MCR_RRF_SHIFT                      (9U)
+#define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
+
+/*! @name MSR - Master Status Register */
+#define LPI2C_MSR_TDF_MASK                       (0x1U)
+#define LPI2C_MSR_TDF_SHIFT                      (0U)
+#define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
+#define LPI2C_MSR_RDF_MASK                       (0x2U)
+#define LPI2C_MSR_RDF_SHIFT                      (1U)
+#define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
+#define LPI2C_MSR_EPF_MASK                       (0x100U)
+#define LPI2C_MSR_EPF_SHIFT                      (8U)
+#define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
+#define LPI2C_MSR_SDF_MASK                       (0x200U)
+#define LPI2C_MSR_SDF_SHIFT                      (9U)
+#define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
+#define LPI2C_MSR_NDF_MASK                       (0x400U)
+#define LPI2C_MSR_NDF_SHIFT                      (10U)
+#define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
+#define LPI2C_MSR_ALF_MASK                       (0x800U)
+#define LPI2C_MSR_ALF_SHIFT                      (11U)
+#define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
+#define LPI2C_MSR_FEF_MASK                       (0x1000U)
+#define LPI2C_MSR_FEF_SHIFT                      (12U)
+#define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
+#define LPI2C_MSR_PLTF_MASK                      (0x2000U)
+#define LPI2C_MSR_PLTF_SHIFT                     (13U)
+#define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
+#define LPI2C_MSR_DMF_MASK                       (0x4000U)
+#define LPI2C_MSR_DMF_SHIFT                      (14U)
+#define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
+#define LPI2C_MSR_MBF_MASK                       (0x1000000U)
+#define LPI2C_MSR_MBF_SHIFT                      (24U)
+#define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
+#define LPI2C_MSR_BBF_MASK                       (0x2000000U)
+#define LPI2C_MSR_BBF_SHIFT                      (25U)
+#define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
+
+/*! @name MIER - Master Interrupt Enable Register */
+#define LPI2C_MIER_TDIE_MASK                     (0x1U)
+#define LPI2C_MIER_TDIE_SHIFT                    (0U)
+#define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
+#define LPI2C_MIER_RDIE_MASK                     (0x2U)
+#define LPI2C_MIER_RDIE_SHIFT                    (1U)
+#define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
+#define LPI2C_MIER_EPIE_MASK                     (0x100U)
+#define LPI2C_MIER_EPIE_SHIFT                    (8U)
+#define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
+#define LPI2C_MIER_SDIE_MASK                     (0x200U)
+#define LPI2C_MIER_SDIE_SHIFT                    (9U)
+#define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
+#define LPI2C_MIER_NDIE_MASK                     (0x400U)
+#define LPI2C_MIER_NDIE_SHIFT                    (10U)
+#define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
+#define LPI2C_MIER_ALIE_MASK                     (0x800U)
+#define LPI2C_MIER_ALIE_SHIFT                    (11U)
+#define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
+#define LPI2C_MIER_FEIE_MASK                     (0x1000U)
+#define LPI2C_MIER_FEIE_SHIFT                    (12U)
+#define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
+#define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
+#define LPI2C_MIER_PLTIE_SHIFT                   (13U)
+#define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
+#define LPI2C_MIER_DMIE_MASK                     (0x4000U)
+#define LPI2C_MIER_DMIE_SHIFT                    (14U)
+#define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
+
+/*! @name MDER - Master DMA Enable Register */
+#define LPI2C_MDER_TDDE_MASK                     (0x1U)
+#define LPI2C_MDER_TDDE_SHIFT                    (0U)
+#define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
+#define LPI2C_MDER_RDDE_MASK                     (0x2U)
+#define LPI2C_MDER_RDDE_SHIFT                    (1U)
+#define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
+
+/*! @name MCFGR0 - Master Configuration Register 0 */
+#define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
+#define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
+#define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
+#define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
+#define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
+#define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
+#define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
+#define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
+#define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
+#define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
+#define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
+#define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
+#define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
+#define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
+#define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
+
+/*! @name MCFGR1 - Master Configuration Register 1 */
+#define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
+#define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
+#define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
+#define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
+#define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
+#define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
+#define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
+#define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
+#define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
+#define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
+#define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
+#define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
+#define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
+#define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
+#define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
+#define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
+#define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
+#define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
+
+/*! @name MCFGR2 - Master Configuration Register 2 */
+#define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
+#define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
+#define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
+#define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
+#define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
+#define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
+#define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
+#define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
+#define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
+
+/*! @name MCFGR3 - Master Configuration Register 3 */
+#define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
+#define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
+#define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
+
+/*! @name MDMR - Master Data Match Register */
+#define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
+#define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
+#define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
+#define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
+#define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
+#define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
+
+/*! @name MCCR0 - Master Clock Configuration Register 0 */
+#define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
+#define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
+#define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
+#define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
+#define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
+#define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
+#define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
+#define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
+#define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
+#define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
+#define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
+#define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
+
+/*! @name MCCR1 - Master Clock Configuration Register 1 */
+#define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
+#define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
+#define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
+#define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
+#define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
+#define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
+#define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
+#define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
+#define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
+#define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
+#define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
+#define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
+
+/*! @name MFCR - Master FIFO Control Register */
+#define LPI2C_MFCR_TXWATER_MASK                  (0xFFU)
+#define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
+#define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
+#define LPI2C_MFCR_RXWATER_MASK                  (0xFF0000U)
+#define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
+#define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
+
+/*! @name MFSR - Master FIFO Status Register */
+#define LPI2C_MFSR_TXCOUNT_MASK                  (0xFFU)
+#define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
+#define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
+#define LPI2C_MFSR_RXCOUNT_MASK                  (0xFF0000U)
+#define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
+#define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
+
+/*! @name MTDR - Master Transmit Data Register */
+#define LPI2C_MTDR_DATA_MASK                     (0xFFU)
+#define LPI2C_MTDR_DATA_SHIFT                    (0U)
+#define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
+#define LPI2C_MTDR_CMD_MASK                      (0x700U)
+#define LPI2C_MTDR_CMD_SHIFT                     (8U)
+#define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
+
+/*! @name MRDR - Master Receive Data Register */
+#define LPI2C_MRDR_DATA_MASK                     (0xFFU)
+#define LPI2C_MRDR_DATA_SHIFT                    (0U)
+#define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
+#define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
+#define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
+#define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
+
+/*! @name SCR - Slave Control Register */
+#define LPI2C_SCR_SEN_MASK                       (0x1U)
+#define LPI2C_SCR_SEN_SHIFT                      (0U)
+#define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
+#define LPI2C_SCR_RST_MASK                       (0x2U)
+#define LPI2C_SCR_RST_SHIFT                      (1U)
+#define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
+#define LPI2C_SCR_FILTEN_MASK                    (0x10U)
+#define LPI2C_SCR_FILTEN_SHIFT                   (4U)
+#define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
+#define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
+#define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
+#define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
+#define LPI2C_SCR_RTF_MASK                       (0x100U)
+#define LPI2C_SCR_RTF_SHIFT                      (8U)
+#define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
+#define LPI2C_SCR_RRF_MASK                       (0x200U)
+#define LPI2C_SCR_RRF_SHIFT                      (9U)
+#define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
+
+/*! @name SSR - Slave Status Register */
+#define LPI2C_SSR_TDF_MASK                       (0x1U)
+#define LPI2C_SSR_TDF_SHIFT                      (0U)
+#define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
+#define LPI2C_SSR_RDF_MASK                       (0x2U)
+#define LPI2C_SSR_RDF_SHIFT                      (1U)
+#define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
+#define LPI2C_SSR_AVF_MASK                       (0x4U)
+#define LPI2C_SSR_AVF_SHIFT                      (2U)
+#define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
+#define LPI2C_SSR_TAF_MASK                       (0x8U)
+#define LPI2C_SSR_TAF_SHIFT                      (3U)
+#define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
+#define LPI2C_SSR_RSF_MASK                       (0x100U)
+#define LPI2C_SSR_RSF_SHIFT                      (8U)
+#define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
+#define LPI2C_SSR_SDF_MASK                       (0x200U)
+#define LPI2C_SSR_SDF_SHIFT                      (9U)
+#define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
+#define LPI2C_SSR_BEF_MASK                       (0x400U)
+#define LPI2C_SSR_BEF_SHIFT                      (10U)
+#define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
+#define LPI2C_SSR_FEF_MASK                       (0x800U)
+#define LPI2C_SSR_FEF_SHIFT                      (11U)
+#define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
+#define LPI2C_SSR_AM0F_MASK                      (0x1000U)
+#define LPI2C_SSR_AM0F_SHIFT                     (12U)
+#define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
+#define LPI2C_SSR_AM1F_MASK                      (0x2000U)
+#define LPI2C_SSR_AM1F_SHIFT                     (13U)
+#define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
+#define LPI2C_SSR_GCF_MASK                       (0x4000U)
+#define LPI2C_SSR_GCF_SHIFT                      (14U)
+#define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
+#define LPI2C_SSR_SARF_MASK                      (0x8000U)
+#define LPI2C_SSR_SARF_SHIFT                     (15U)
+#define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
+#define LPI2C_SSR_SBF_MASK                       (0x1000000U)
+#define LPI2C_SSR_SBF_SHIFT                      (24U)
+#define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
+#define LPI2C_SSR_BBF_MASK                       (0x2000000U)
+#define LPI2C_SSR_BBF_SHIFT                      (25U)
+#define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
+
+/*! @name SIER - Slave Interrupt Enable Register */
+#define LPI2C_SIER_TDIE_MASK                     (0x1U)
+#define LPI2C_SIER_TDIE_SHIFT                    (0U)
+#define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
+#define LPI2C_SIER_RDIE_MASK                     (0x2U)
+#define LPI2C_SIER_RDIE_SHIFT                    (1U)
+#define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
+#define LPI2C_SIER_AVIE_MASK                     (0x4U)
+#define LPI2C_SIER_AVIE_SHIFT                    (2U)
+#define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
+#define LPI2C_SIER_TAIE_MASK                     (0x8U)
+#define LPI2C_SIER_TAIE_SHIFT                    (3U)
+#define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
+#define LPI2C_SIER_RSIE_MASK                     (0x100U)
+#define LPI2C_SIER_RSIE_SHIFT                    (8U)
+#define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
+#define LPI2C_SIER_SDIE_MASK                     (0x200U)
+#define LPI2C_SIER_SDIE_SHIFT                    (9U)
+#define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
+#define LPI2C_SIER_BEIE_MASK                     (0x400U)
+#define LPI2C_SIER_BEIE_SHIFT                    (10U)
+#define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
+#define LPI2C_SIER_FEIE_MASK                     (0x800U)
+#define LPI2C_SIER_FEIE_SHIFT                    (11U)
+#define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
+#define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
+#define LPI2C_SIER_AM0IE_SHIFT                   (12U)
+#define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
+#define LPI2C_SIER_AM1F_MASK                     (0x2000U)
+#define LPI2C_SIER_AM1F_SHIFT                    (13U)
+#define LPI2C_SIER_AM1F(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
+#define LPI2C_SIER_GCIE_MASK                     (0x4000U)
+#define LPI2C_SIER_GCIE_SHIFT                    (14U)
+#define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
+#define LPI2C_SIER_SARIE_MASK                    (0x8000U)
+#define LPI2C_SIER_SARIE_SHIFT                   (15U)
+#define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
+
+/*! @name SDER - Slave DMA Enable Register */
+#define LPI2C_SDER_TDDE_MASK                     (0x1U)
+#define LPI2C_SDER_TDDE_SHIFT                    (0U)
+#define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
+#define LPI2C_SDER_RDDE_MASK                     (0x2U)
+#define LPI2C_SDER_RDDE_SHIFT                    (1U)
+#define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
+#define LPI2C_SDER_AVDE_MASK                     (0x4U)
+#define LPI2C_SDER_AVDE_SHIFT                    (2U)
+#define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
+
+/*! @name SCFGR1 - Slave Configuration Register 1 */
+#define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
+#define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
+#define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
+#define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
+#define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
+#define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
+#define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
+#define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
+#define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
+#define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
+#define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
+#define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
+#define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
+#define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
+#define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
+#define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
+#define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
+#define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
+#define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
+#define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
+#define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
+#define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
+#define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
+#define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
+#define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
+#define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
+#define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
+#define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
+#define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
+#define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
+#define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
+#define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
+#define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
+
+/*! @name SCFGR2 - Slave Configuration Register 2 */
+#define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
+#define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
+#define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
+#define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
+#define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
+#define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
+#define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
+#define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
+#define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
+#define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
+#define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
+#define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
+
+/*! @name SAMR - Slave Address Match Register */
+#define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
+#define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
+#define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
+#define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
+#define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
+#define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
+
+/*! @name SASR - Slave Address Status Register */
+#define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
+#define LPI2C_SASR_RADDR_SHIFT                   (0U)
+#define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
+#define LPI2C_SASR_ANV_MASK                      (0x4000U)
+#define LPI2C_SASR_ANV_SHIFT                     (14U)
+#define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
+
+/*! @name STAR - Slave Transmit ACK Register */
+#define LPI2C_STAR_TXNACK_MASK                   (0x1U)
+#define LPI2C_STAR_TXNACK_SHIFT                  (0U)
+#define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
+
+/*! @name STDR - Slave Transmit Data Register */
+#define LPI2C_STDR_DATA_MASK                     (0xFFU)
+#define LPI2C_STDR_DATA_SHIFT                    (0U)
+#define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
+
+/*! @name SRDR - Slave Receive Data Register */
+#define LPI2C_SRDR_DATA_MASK                     (0xFFU)
+#define LPI2C_SRDR_DATA_SHIFT                    (0U)
+#define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
+#define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
+#define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
+#define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
+#define LPI2C_SRDR_SOF_MASK                      (0x8000U)
+#define LPI2C_SRDR_SOF_SHIFT                     (15U)
+#define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
+
+#endif /* __ASM_ARCH_IMX_I2C_H__ */
diff --git a/include/imx_sip.h b/include/imx_sip.h
new file mode 100644
index 0000000..139ff61
--- /dev/null
+++ b/include/imx_sip.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef _IMX_SIP_H__
+#define _IMX_SIP_H_
+
+#define IMX_SIP_GPC		0xC2000000
+#define  IMX_SIP_GPC_PM_DOMAIN	0x03
+
+#define IMX_SIP_SRC		0xC2000005
+#define IMX_SIP_SRC_M4_START	0x00
+#define IMX_SIP_SRC_M4_STARTED	0x01
+
+#endif
diff --git a/include/imx_thermal.h b/include/imx_thermal.h
new file mode 100644
index 0000000..6f32cb5
--- /dev/null
+++ b/include/imx_thermal.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *
+ * (C) Copyright 2014 Freescale Semiconductor, Inc
+ */
+
+#ifndef _IMX_THERMAL_H_
+#define _IMX_THERMAL_H_
+
+/* CPU Temperature Grades */
+#define TEMP_COMMERCIAL         0
+#define TEMP_EXTCOMMERCIAL      1
+#define TEMP_INDUSTRIAL         2
+#define TEMP_AUTOMOTIVE         3
+
+struct imx_thermal_plat {
+	void *regs;
+	int fuse_bank;
+	int fuse_word;
+};
+
+#endif	/* _IMX_THERMAL_H_ */
diff --git a/include/imximage.h b/include/imximage.h
new file mode 100644
index 0000000..544babb
--- /dev/null
+++ b/include/imximage.h
@@ -0,0 +1,219 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ */
+
+#ifndef _IMXIMAGE_H_
+#define _IMXIMAGE_H_
+
+#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
+#define MAX_PLUGIN_CODE_SIZE (64 * 1024)
+#define MAX_HW_CFG_SIZE_V1 60  /* Max number of registers imx can set for v1 */
+#define APP_CODE_BARKER	0xB1
+#define DCD_BARKER	0xB17219E9
+
+/* Specify the offset of the IVT in the IMX header as expected by BootROM */
+#define BOOTROM_IVT_HDR_OFFSET	0xC00
+
+/*
+ * NOTE: This file must be kept in sync with arch/arm/include/asm/\
+ *       mach-imx/imximage.cfg because tools/imximage.c can not
+ *       cross-include headers from arch/arm/ and vice-versa.
+ */
+#define CMD_DATA_STR	"DATA"
+
+/* Initial Vector Table Offset */
+#define FLASH_OFFSET_UNDEFINED	0xFFFFFFFF
+#define FLASH_OFFSET_STANDARD	0x400
+#define FLASH_OFFSET_NAND	FLASH_OFFSET_STANDARD
+#define FLASH_OFFSET_SD		FLASH_OFFSET_STANDARD
+#define FLASH_OFFSET_SPI	FLASH_OFFSET_STANDARD
+#define FLASH_OFFSET_ONENAND	0x100
+#define FLASH_OFFSET_NOR	0x1000
+#define FLASH_OFFSET_SATA	FLASH_OFFSET_STANDARD
+#define FLASH_OFFSET_QSPI	0x1000
+#define FLASH_OFFSET_FLEXSPI	0x1000
+
+/* Initial Load Region Size */
+#define FLASH_LOADSIZE_UNDEFINED	0xFFFFFFFF
+#define FLASH_LOADSIZE_STANDARD		0x1000
+#define FLASH_LOADSIZE_NAND		FLASH_LOADSIZE_STANDARD
+#define FLASH_LOADSIZE_SD		FLASH_LOADSIZE_STANDARD
+#define FLASH_LOADSIZE_SPI		FLASH_LOADSIZE_STANDARD
+#define FLASH_LOADSIZE_ONENAND		0x400
+#define FLASH_LOADSIZE_NOR		0x0 /* entire image */
+#define FLASH_LOADSIZE_SATA		FLASH_LOADSIZE_STANDARD
+#define FLASH_LOADSIZE_QSPI		0x0 /* entire image */
+
+/* Command tags and parameters */
+#define IVT_HEADER_TAG			0xD1
+#define IVT_VERSION			0x40
+#define IVT_VERSION_V3			0x41
+#define DCD_HEADER_TAG			0xD2
+#define DCD_VERSION			0x40
+#define DCD_WRITE_DATA_COMMAND_TAG	0xCC
+#define DCD_WRITE_DATA_PARAM		0x4
+#define DCD_WRITE_CLR_BIT_PARAM		0xC
+#define DCD_WRITE_SET_BIT_PARAM		0x1C
+#define DCD_CHECK_DATA_COMMAND_TAG	0xCF
+#define DCD_CHECK_BITS_SET_PARAM	0x14
+#define DCD_CHECK_BITS_CLR_PARAM	0x04
+
+#ifndef __ASSEMBLY__
+enum imximage_cmd {
+	CMD_INVALID,
+	CMD_IMAGE_VERSION,
+	CMD_BOOT_FROM,
+	CMD_BOOT_OFFSET,
+	CMD_WRITE_DATA,
+	CMD_WRITE_CLR_BIT,
+	CMD_WRITE_SET_BIT,
+	CMD_CHECK_BITS_SET,
+	CMD_CHECK_BITS_CLR,
+	CMD_CSF,
+	CMD_PLUGIN,
+	/* Follwoing on i.MX8MQ/MM */
+	CMD_FIT,
+	CMD_SIGNED_HDMI,
+	CMD_LOADER,
+	CMD_SECOND_LOADER,
+	CMD_DDR_FW,
+};
+
+enum imximage_fld_types {
+	CFG_INVALID = -1,
+	CFG_COMMAND,
+	CFG_REG_SIZE,
+	CFG_REG_ADDRESS,
+	CFG_REG_VALUE
+};
+
+enum imximage_version {
+	IMXIMAGE_VER_INVALID = -1,
+	IMXIMAGE_V1 = 1,
+	IMXIMAGE_V2,
+	IMXIMAGE_V3
+};
+
+typedef struct {
+	uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
+	uint32_t addr; /* Address to write to */
+	uint32_t value; /* Data to write */
+} dcd_type_addr_data_t;
+
+typedef struct {
+	uint32_t barker; /* Barker for sanity check */
+	uint32_t length; /* Device configuration length (without preamble) */
+} dcd_preamble_t;
+
+typedef struct {
+	dcd_preamble_t preamble;
+	dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
+} dcd_v1_t;
+
+typedef struct {
+	uint32_t app_code_jump_vector;
+	uint32_t app_code_barker;
+	uint32_t app_code_csf;
+	uint32_t dcd_ptr_ptr;
+	uint32_t super_root_key;
+	uint32_t dcd_ptr;
+	uint32_t app_dest_ptr;
+} flash_header_v1_t;
+
+typedef struct {
+	uint32_t length; 	/* Length of data to be read from flash */
+} flash_cfg_parms_t;
+
+typedef struct {
+	flash_header_v1_t fhdr;
+	dcd_v1_t dcd_table;
+	flash_cfg_parms_t ext_header;
+} imx_header_v1_t;
+
+typedef struct {
+	uint32_t addr;
+	uint32_t value;
+} dcd_addr_data_t;
+
+typedef struct {
+	uint8_t tag;
+	uint16_t length;
+	uint8_t version;
+} __attribute__((packed)) ivt_header_t;
+
+typedef struct {
+	uint8_t tag;
+	uint16_t length;
+	uint8_t param;
+} __attribute__((packed)) write_dcd_command_t;
+
+struct dcd_v2_cmd {
+	write_dcd_command_t write_dcd_command;
+	dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
+};
+
+typedef struct {
+	ivt_header_t header;
+	struct dcd_v2_cmd dcd_cmd;
+	uint32_t padding[1]; /* end up on an 8-byte boundary */
+} dcd_v2_t;
+
+typedef struct {
+	uint32_t start;
+	uint32_t size;
+	uint32_t plugin;
+} boot_data_t;
+
+typedef struct {
+	ivt_header_t header;
+	uint32_t entry;
+	uint32_t reserved1;
+	uint32_t dcd_ptr;
+	uint32_t boot_data_ptr;
+	uint32_t self;
+	uint32_t csf;
+	uint32_t reserved2;
+} flash_header_v2_t;
+
+typedef struct {
+	flash_header_v2_t fhdr;
+	boot_data_t boot_data;
+	union {
+		dcd_v2_t dcd_table;
+		char plugin_code[MAX_PLUGIN_CODE_SIZE];
+	} data;
+} imx_header_v2_t;
+
+typedef struct {
+	flash_header_v2_t fhdr;
+	boot_data_t boot_data;
+	uint32_t padding[5];
+} imx_header_v3_t;
+
+/* The header must be aligned to 4k on MX53 for NAND boot */
+struct imx_header {
+	union {
+		imx_header_v1_t hdr_v1;
+		imx_header_v2_t hdr_v2;
+	} header;
+};
+
+typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
+					char *name, int lineno,
+					int fld, uint32_t value,
+					uint32_t off);
+
+typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+					int32_t cmd);
+
+typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
+					uint32_t dcd_len,
+					char *name, int lineno);
+
+typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+		uint32_t entry_point, uint32_t flash_offset);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _IMXIMAGE_H_ */
diff --git a/include/init.h b/include/init.h
new file mode 100644
index 0000000..afc953d
--- /dev/null
+++ b/include/init.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copy the startup prototype, previously defined in common.h
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef __INIT_H_
+#define __INIT_H_	1
+
+#ifndef __ASSEMBLY__		/* put C only stuff in this section */
+
+/*
+ * Function Prototypes
+ */
+
+/* common/board_f.c */
+void board_init_f(ulong dummy);
+
+/**
+ * arch_cpu_init() - basic cpu-dependent setup for an architecture
+ *
+ * This is called after early malloc is available. It should handle any
+ * CPU- or SoC- specific init needed to continue the init sequence. See
+ * board_f.c for where it is called. If this is not provided, a default
+ * version (which does nothing) will be used.
+ *
+ * Return: 0 on success, otherwise error
+ */
+int arch_cpu_init(void);
+
+/**
+ * arch_cpu_init_dm() - init CPU after driver model is available
+ *
+ * This is called immediately after driver model is available before
+ * relocation. This is similar to arch_cpu_init() but is able to reference
+ * devices
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int arch_cpu_init_dm(void);
+
+/**
+ * mach_cpu_init() - SoC/machine dependent CPU setup
+ *
+ * This is called after arch_cpu_init(). It should handle any
+ * SoC or machine specific init needed to continue the init sequence. See
+ * board_f.c for where it is called. If this is not provided, a default
+ * version (which does nothing) will be used.
+ *
+ * Return: 0 on success, otherwise error
+ */
+int mach_cpu_init(void);
+
+/**
+ * arch_fsp_init() - perform firmware support package init
+ *
+ * Where U-Boot relies on binary blobs to handle part of the system init, this
+ * function can be used to set up the blobs. This is used on some Intel
+ * platforms.
+ *
+ * Return: 0
+ */
+int arch_fsp_init(void);
+
+int dram_init(void);
+
+/**
+ * dram_init_banksize() - Set up DRAM bank sizes
+ *
+ * This can be implemented by boards to set up the DRAM bank information in
+ * gd->bd->bi_dram(). It is called just before relocation, after dram_init()
+ * is called.
+ *
+ * If this is not provided, a default implementation will try to set up a
+ * single bank. It will do this if CONFIG_NR_DRAM_BANKS and
+ * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of
+ * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to
+ * get_effective_memsize().
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int dram_init_banksize(void);
+
+/**
+ * arch_reserve_stacks() - Reserve all necessary stacks
+ *
+ * This is used in generic board init sequence in common/board_f.c. Each
+ * architecture could provide this function to tailor the required stacks.
+ *
+ * On entry gd->start_addr_sp is pointing to the suggested top of the stack.
+ * The callee ensures gd->start_add_sp is 16-byte aligned, so architectures
+ * require only this can leave it untouched.
+ *
+ * On exit gd->start_addr_sp and gd->irq_sp should be set to the respective
+ * positions of the stack. The stack pointer(s) will be set to this later.
+ * gd->irq_sp is only required, if the architecture needs it.
+ *
+ * Return: 0 if no error
+ */
+int arch_reserve_stacks(void);
+
+/**
+ * init_cache_f_r() - Turn on the cache in preparation for relocation
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int init_cache_f_r(void);
+
+#if !CONFIG_IS_ENABLED(CPU)
+/**
+ * print_cpuinfo() - Display information about the CPU
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int print_cpuinfo(void);
+#endif
+int timer_init(void);
+int reserve_mmu(void);
+int misc_init_f(void);
+
+#if defined(CONFIG_DTB_RESELECT)
+int embedded_dtb_select(void);
+#endif
+
+/* common/init/board_init.c */
+extern ulong monitor_flash_len;
+
+/**
+ * ulong board_init_f_alloc_reserve - allocate reserved area
+ * @top: top of the reserve area, growing down.
+ *
+ * This function is called by each architecture very early in the start-up
+ * code to allow the C runtime to reserve space on the stack for writable
+ * 'globals' such as GD and the malloc arena.
+ *
+ * Return: bottom of reserved area
+ */
+ulong board_init_f_alloc_reserve(ulong top);
+
+/**
+ * board_init_f_init_reserve - initialize the reserved area(s)
+ * @base:	top from which reservation was done
+ *
+ * This function is called once the C runtime has allocated the reserved
+ * area on the stack. It must initialize the GD at the base of that area.
+ */
+void board_init_f_init_reserve(ulong base);
+
+/**
+ * arch_setup_gd() - Set up the global_data pointer
+ * @gd_ptr: Pointer to global data
+ *
+ * This pointer is special in some architectures and cannot easily be assigned
+ * to. For example on x86 it is implemented by adding a specific record to its
+ * Global Descriptor Table! So we we provide a function to carry out this task.
+ * For most architectures this can simply be:
+ *
+ *    gd = gd_ptr;
+ */
+void arch_setup_gd(gd_t *gd_ptr);
+
+/* common/board_r.c */
+void board_init_r(gd_t *id, ulong dest_addr) __attribute__ ((noreturn));
+
+int cpu_init_r(void);
+int last_stage_init(void);
+int mac_read_from_eeprom(void);
+int set_cpu_clk_info(void);
+int update_flash_size(int flash_size);
+int arch_early_init_r(void);
+void pci_init(void);
+int misc_init_r(void);
+#if defined(CONFIG_VID)
+int init_func_vid(void);
+#endif
+
+/* common/board_info.c */
+int checkboard(void);
+int show_board_info(void);
+
+#endif	/* __ASSEMBLY__ */
+/* Put only stuff here that the assembler can digest */
+
+#endif	/* __INIT_H_ */
diff --git a/include/initcall.h b/include/initcall.h
new file mode 100644
index 0000000..b5acdd0
--- /dev/null
+++ b/include/initcall.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __INITCALL_H
+#define __INITCALL_H
+
+typedef int (*init_fnc_t)(void);
+
+/*
+ * To enable debugging. add #define DEBUG at the top of the including file.
+ *
+ * To find a symbol, use grep on u-boot.map
+ */
+static inline int initcall_run_list(const init_fnc_t init_sequence[])
+{
+	const init_fnc_t *init_fnc_ptr;
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		unsigned long reloc_ofs = 0;
+		int ret;
+
+		/*
+		 * Sandbox is relocated by the OS, so symbols always appear at
+		 * the relocated address.
+		 */
+		if (IS_ENABLED(CONFIG_SANDBOX) || (gd->flags & GD_FLG_RELOC))
+			reloc_ofs = gd->reloc_off;
+#ifdef CONFIG_EFI_APP
+		reloc_ofs = (unsigned long)image_base;
+#endif
+		if (reloc_ofs)
+			debug("initcall: %p (relocated to %p)\n",
+					(char *)*init_fnc_ptr - reloc_ofs,
+					(char *)*init_fnc_ptr);
+		else
+			debug("initcall: %p\n", (char *)*init_fnc_ptr - reloc_ofs);
+
+		ret = (*init_fnc_ptr)();
+		if (ret) {
+			printf("initcall sequence %p failed at call %p (err=%d)\n",
+			       init_sequence,
+			       (char *)*init_fnc_ptr - reloc_ofs, ret);
+			return -1;
+		}
+	}
+	return 0;
+}
+
+#endif
diff --git a/include/input.h b/include/input.h
new file mode 100644
index 0000000..3285a3f
--- /dev/null
+++ b/include/input.h
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keyboard input helper functions (too small to be called a layer)
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef _INPUT_H
+#define _INPUT_H
+
+enum {
+	INPUT_MAX_MODIFIERS	= 4,
+	INPUT_BUFFER_LEN	= 16,
+};
+
+enum {
+	/* Keyboard LEDs */
+	INPUT_LED_SCROLL	= 1 << 0,
+	INPUT_LED_NUM		= 1 << 1,
+	INPUT_LED_CAPS		= 1 << 2,
+};
+
+/*
+ * This table translates key codes to ASCII. Most of the entries are ASCII
+ * codes, but entries after KEY_FIRST_MOD indicate that this key is a
+ * modifier key, like shift, ctrl. KEY_FIRST_MOD + MOD_SHIFT is the shift
+ * key, for example.
+ */
+struct input_key_xlate {
+	/* keycode of the modifiers which select this table, -1 if none */
+	int left_keycode;
+	int right_keycode;
+	const uchar *xlate;	/* keycode to ASCII table */
+	int num_entries;	/* number of entries in this table */
+};
+
+struct input_config {
+	struct udevice *dev;
+	uchar fifo[INPUT_BUFFER_LEN];
+	int fifo_in, fifo_out;
+
+	/* Which modifiers are active (1 bit for each MOD_... value) */
+	uchar modifiers;
+	uchar flags;		/* active state keys (FLAGS_...) */
+	uchar leds;		/* active LEDs (INPUT_LED_...) */
+	uchar leds_changed;	/* LEDs that just changed */
+	uchar num_tables;	/* number of modifier tables */
+	int prev_keycodes[INPUT_BUFFER_LEN];	/* keys held last time */
+	int num_prev_keycodes;	/* number of prev keys */
+	struct input_key_xlate table[INPUT_MAX_MODIFIERS];
+
+	/**
+	 * Function the input helper calls to scan the keyboard
+	 *
+	 * @param config	Input state
+	 * @return 0 if no keys read, otherwise number of keys read, or 1 if
+	 *		unknown
+	 */
+	int (*read_keys)(struct input_config *config);
+	bool allow_repeats;		/* Don't filter out repeats */
+	unsigned int next_repeat_ms;	/* Next time we repeat a key */
+	unsigned int repeat_delay_ms;	/* Time before autorepeat starts */
+	unsigned int repeat_rate_ms;	/* Autorepeat rate in ms */
+};
+
+struct stdio_dev;
+
+/**
+ * Convert a list of key codes into ASCII and send them
+ *
+ * @param config	Input state
+ * @param keycode	List of key codes to examine
+ * @param num_keycodes	Number of key codes
+ * @return number of ascii characters sent, or 0 if none, or -1 for an
+ *	internal error
+ */
+int input_send_keycodes(struct input_config *config, int keycode[], int count);
+
+/**
+ * Add a new keycode to an existing list of keycodes
+ *
+ * This can be used to handle keyboards which do their own scanning. An
+ * internal list of depressed keys is maintained by the input library. Then
+ * this function is called to add a new key to the list (when a 'make code' is
+ * received), or remove a key (when a 'break code' is received).
+ *
+ * This function looks after maintenance of the list of active keys, and calls
+ * input_send_keycodes() with its updated list.
+ *
+ * @param config	Input state
+ * @param new_keycode	New keycode to add/remove
+ * @param release	true if this key was released, false if depressed
+ * @return number of ascii characters sent, or 0 if none, or -1 for an
+ *	internal error
+ */
+int input_add_keycode(struct input_config *config, int new_keycode,
+		      bool release);
+
+/**
+ * Add a new key translation table to the input
+ *
+ * @param config	Input state
+ * @param left_keycode	Key to hold to get into this table
+ * @param right_keycode	Another key to hold to get into this table
+ * @param xlate		Conversion table from key codes to ASCII
+ * @param num_entries	Number of entries in xlate table
+ */
+int input_add_table(struct input_config *config, int left_keycode,
+		    int right_keycode, const uchar *xlate, int num_entries);
+
+/**
+ * Test if keys are available to be read
+ *
+ * @param config	Input state
+ * @return 0 if no keys available, 1 if keys are available
+ */
+int input_tstc(struct input_config *config);
+
+/**
+ * Read a key
+ *
+ * TODO: U-Boot wants 0 for no key, but Ctrl-@ is a valid key...
+ *
+ * @param config	Input state
+ * @return key, or 0 if no key, or -1 if error
+ */
+int input_getc(struct input_config *config);
+
+/**
+ * Register a new device with stdio and switch to it if wanted
+ *
+ * @param dev	Pointer to device
+ * @return 0 if ok, -1 on error
+ */
+int input_stdio_register(struct stdio_dev *dev);
+
+/**
+ * Set up the keyboard autorepeat delays
+ *
+ * @param repeat_delay_ms	Delay before key auto-repeat starts (in ms)
+ * @param repeat_rate_ms	Delay between successive key repeats (in ms)
+ */
+void input_set_delays(struct input_config *config, int repeat_delay_ms,
+	       int repeat_rate_ms);
+
+/**
+ * Tell the input layer whether to allow the caller to determine repeats
+ *
+ * Generally the input library handles processing of a list of scanned keys.
+ * Repeated keys need to be generated based on a timer in this case, since all
+ * that is provided is a list of keys current depressed.
+ *
+ * Keyboards which do their own scanning will resend codes when they want to
+ * inject a repeating key. This function can be called at start-up to select
+ * this behaviour.
+ *
+ * @param config	Input state
+ * @param allow_repeats	true to repeat depressed keys every time
+ *			input_send_keycodes() is called, false to do normal
+ *			keyboard repeat processing with a timer.
+ */
+void input_allow_repeats(struct input_config *config, bool allow_repeats);
+
+/**
+ * Check if keyboard LEDs need to be updated
+ *
+ * This can be called after input_tstc() to see if keyboard LEDs need
+ * updating.
+ *
+ * @param config	Input state
+ * @return -1 if no LEDs need updating, other value if they do
+ */
+int input_leds_changed(struct input_config *config);
+
+/**
+ * Set up the key map tables
+ *
+ * This must be called after input_init() or keycode decoding will not work.
+ *
+ * @param config	Input state
+ * @param german	true to use German keyboard layout, false for US
+ * @return 0 if ok, -1 on error
+ */
+int input_add_tables(struct input_config *config, bool german);
+
+/**
+ * Set up the input handler with basic key maps.
+ *
+ * @param config	Input state
+ * @param leds		Initial LED value (INPUT_LED_ mask), 0 suggested
+ * @return 0 if ok, -1 on error
+ */
+int input_init(struct input_config *config, int leds);
+
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+extern int overwrite_console(void);
+#define OVERWRITE_CONSOLE overwrite_console()
+#else
+#define OVERWRITE_CONSOLE 0
+#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
+
+#endif
diff --git a/include/inttypes.h b/include/inttypes.h
new file mode 100644
index 0000000..dcb6785
--- /dev/null
+++ b/include/inttypes.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 1997-2001, 2004, 2007 Free Software Foundation, Inc.
+ *
+ * This file is taken from the GNU C Library v2.15, with the unimplemented
+ * functions removed and a few style fixes.
+ */
+
+/*
+ *	ISO C99: 7.8 Format conversion of integer types	<inttypes.h>
+ */
+
+#ifndef _INTTYPES_H
+#define _INTTYPES_H	1
+
+#include <linux/compiler.h>
+
+/* Get a definition for wchar_t.  But we must not define wchar_t itself.  */
+#ifndef ____gwchar_t_defined
+# ifdef __cplusplus
+#  define __gwchar_t wchar_t
+# elif defined __WCHAR_TYPE__
+typedef __WCHAR_TYPE__ __gwchar_t;
+# else
+#  define __need_wchar_t
+#  include <linux/stddef.h>
+typedef wchar_t __gwchar_t;
+# endif
+# define ____gwchar_t_defined	1
+#endif
+
+/*
+ * The ISO C99 standard specifies that these macros must only be defined if
+ * explicitly requested
+ */
+#if !defined __cplusplus || defined __STDC_FORMAT_MACROS
+
+/* linux/types.h always uses long long for 64-bit and long for uintptr_t */
+# define __PRI64_PREFIX	"ll"
+# define __PRIPTR_PREFIX	"l"
+
+/* Macros for printing format specifiers.  */
+
+/* Decimal notation.  */
+# define PRId8		"d"
+# define PRId16		"d"
+# define PRId32		"d"
+# define PRId64		__PRI64_PREFIX "d"
+
+# define PRIdLEAST8	"d"
+# define PRIdLEAST16	"d"
+# define PRIdLEAST32	"d"
+# define PRIdLEAST64	__PRI64_PREFIX "d"
+
+# define PRIdFAST8	"d"
+# define PRIdFAST16	__PRIPTR_PREFIX "d"
+# define PRIdFAST32	__PRIPTR_PREFIX "d"
+# define PRIdFAST64	__PRI64_PREFIX "d"
+
+# define PRIi8		"i"
+# define PRIi16		"i"
+# define PRIi32		"i"
+# define PRIi64		__PRI64_PREFIX "i"
+
+# define PRIiLEAST8	"i"
+# define PRIiLEAST16	"i"
+# define PRIiLEAST32	"i"
+# define PRIiLEAST64	__PRI64_PREFIX "i"
+
+# define PRIiFAST8	"i"
+# define PRIiFAST16	__PRIPTR_PREFIX "i"
+# define PRIiFAST32	__PRIPTR_PREFIX "i"
+# define PRIiFAST64	__PRI64_PREFIX "i"
+
+/* Octal notation.  */
+# define PRIo8		"o"
+# define PRIo16		"o"
+# define PRIo32		"o"
+# define PRIo64		__PRI64_PREFIX "o"
+
+# define PRIoLEAST8	"o"
+# define PRIoLEAST16	"o"
+# define PRIoLEAST32	"o"
+# define PRIoLEAST64	__PRI64_PREFIX "o"
+
+# define PRIoFAST8	"o"
+# define PRIoFAST16	__PRIPTR_PREFIX "o"
+# define PRIoFAST32	__PRIPTR_PREFIX "o"
+# define PRIoFAST64	__PRI64_PREFIX "o"
+
+/* Unsigned integers.  */
+# define PRIu8		"u"
+# define PRIu16		"u"
+# define PRIu32		"u"
+# define PRIu64		__PRI64_PREFIX "u"
+
+# define PRIuLEAST8	"u"
+# define PRIuLEAST16	"u"
+# define PRIuLEAST32	"u"
+# define PRIuLEAST64	__PRI64_PREFIX "u"
+
+# define PRIuFAST8	"u"
+# define PRIuFAST16	__PRIPTR_PREFIX "u"
+# define PRIuFAST32	__PRIPTR_PREFIX "u"
+# define PRIuFAST64	__PRI64_PREFIX "u"
+
+/* lowercase hexadecimal notation.  */
+# define PRIx8		"x"
+# define PRIx16		"x"
+# define PRIx32		"x"
+# define PRIx64		__PRI64_PREFIX "x"
+
+# define PRIxLEAST8	"x"
+# define PRIxLEAST16	"x"
+# define PRIxLEAST32	"x"
+# define PRIxLEAST64	__PRI64_PREFIX "x"
+
+# define PRIxFAST8	"x"
+# define PRIxFAST16	__PRIPTR_PREFIX "x"
+# define PRIxFAST32	__PRIPTR_PREFIX "x"
+# define PRIxFAST64	__PRI64_PREFIX "x"
+
+/* UPPERCASE hexadecimal notation.  */
+# define PRIX8		"X"
+# define PRIX16		"X"
+# define PRIX32		"X"
+# define PRIX64		__PRI64_PREFIX "X"
+
+# define PRIXLEAST8	"X"
+# define PRIXLEAST16	"X"
+# define PRIXLEAST32	"X"
+# define PRIXLEAST64	__PRI64_PREFIX "X"
+
+# define PRIXFAST8	"X"
+# define PRIXFAST16	__PRIPTR_PREFIX "X"
+# define PRIXFAST32	__PRIPTR_PREFIX "X"
+# define PRIXFAST64	__PRI64_PREFIX "X"
+
+/* Macros for printing `intmax_t' and `uintmax_t'.  */
+# define PRIdMAX	__PRI64_PREFIX "d"
+# define PRIiMAX	__PRI64_PREFIX "i"
+# define PRIoMAX	__PRI64_PREFIX "o"
+# define PRIuMAX	__PRI64_PREFIX "u"
+# define PRIxMAX	__PRI64_PREFIX "x"
+# define PRIXMAX	__PRI64_PREFIX "X"
+
+/* Macros for printing `intptr_t' and `uintptr_t'.  */
+# define PRIdPTR	__PRIPTR_PREFIX "d"
+# define PRIiPTR	__PRIPTR_PREFIX "i"
+# define PRIoPTR	__PRIPTR_PREFIX "o"
+# define PRIuPTR	__PRIPTR_PREFIX "u"
+# define PRIxPTR	__PRIPTR_PREFIX "x"
+# define PRIXPTR	__PRIPTR_PREFIX "X"
+
+/* Macros for scanning format specifiers.  */
+
+/* Signed decimal notation.  */
+# define SCNd8		"hhd"
+# define SCNd16		"hd"
+# define SCNd32		"d"
+# define SCNd64		__PRI64_PREFIX "d"
+
+# define SCNdLEAST8	"hhd"
+# define SCNdLEAST16	"hd"
+# define SCNdLEAST32	"d"
+# define SCNdLEAST64	__PRI64_PREFIX "d"
+
+# define SCNdFAST8	"hhd"
+# define SCNdFAST16	__PRIPTR_PREFIX "d"
+# define SCNdFAST32	__PRIPTR_PREFIX "d"
+# define SCNdFAST64	__PRI64_PREFIX "d"
+
+/* Signed decimal notation.  */
+# define SCNi8		"hhi"
+# define SCNi16		"hi"
+# define SCNi32		"i"
+# define SCNi64		__PRI64_PREFIX "i"
+
+# define SCNiLEAST8	"hhi"
+# define SCNiLEAST16	"hi"
+# define SCNiLEAST32	"i"
+# define SCNiLEAST64	__PRI64_PREFIX "i"
+
+# define SCNiFAST8	"hhi"
+# define SCNiFAST16	__PRIPTR_PREFIX "i"
+# define SCNiFAST32	__PRIPTR_PREFIX "i"
+# define SCNiFAST64	__PRI64_PREFIX "i"
+
+/* Unsigned decimal notation.  */
+# define SCNu8		"hhu"
+# define SCNu16		"hu"
+# define SCNu32		"u"
+# define SCNu64		__PRI64_PREFIX "u"
+
+# define SCNuLEAST8	"hhu"
+# define SCNuLEAST16	"hu"
+# define SCNuLEAST32	"u"
+# define SCNuLEAST64	__PRI64_PREFIX "u"
+
+# define SCNuFAST8	"hhu"
+# define SCNuFAST16	__PRIPTR_PREFIX "u"
+# define SCNuFAST32	__PRIPTR_PREFIX "u"
+# define SCNuFAST64	__PRI64_PREFIX "u"
+
+/* Octal notation.  */
+# define SCNo8		"hho"
+# define SCNo16		"ho"
+# define SCNo32		"o"
+# define SCNo64		__PRI64_PREFIX "o"
+
+# define SCNoLEAST8	"hho"
+# define SCNoLEAST16	"ho"
+# define SCNoLEAST32	"o"
+# define SCNoLEAST64	__PRI64_PREFIX "o"
+
+# define SCNoFAST8	"hho"
+# define SCNoFAST16	__PRIPTR_PREFIX "o"
+# define SCNoFAST32	__PRIPTR_PREFIX "o"
+# define SCNoFAST64	__PRI64_PREFIX "o"
+
+/* Hexadecimal notation.  */
+# define SCNx8		"hhx"
+# define SCNx16		"hx"
+# define SCNx32		"x"
+# define SCNx64		__PRI64_PREFIX "x"
+
+# define SCNxLEAST8	"hhx"
+# define SCNxLEAST16	"hx"
+# define SCNxLEAST32	"x"
+# define SCNxLEAST64	__PRI64_PREFIX "x"
+
+# define SCNxFAST8	"hhx"
+# define SCNxFAST16	__PRIPTR_PREFIX "x"
+# define SCNxFAST32	__PRIPTR_PREFIX "x"
+# define SCNxFAST64	__PRI64_PREFIX "x"
+
+/* Macros for scanning `intmax_t' and `uintmax_t'.  */
+# define SCNdMAX	__PRI64_PREFIX "d"
+# define SCNiMAX	__PRI64_PREFIX "i"
+# define SCNoMAX	__PRI64_PREFIX "o"
+# define SCNuMAX	__PRI64_PREFIX "u"
+# define SCNxMAX	__PRI64_PREFIX "x"
+
+/* Macros for scanning `intptr_t' and `uintptr_t'.  */
+# define SCNdPTR	__PRIPTR_PREFIX "d"
+# define SCNiPTR	__PRIPTR_PREFIX "i"
+# define SCNoPTR	__PRIPTR_PREFIX "o"
+# define SCNuPTR	__PRIPTR_PREFIX "u"
+# define SCNxPTR	__PRIPTR_PREFIX "x"
+
+#endif	/* C++ && format macros */
+
+#if __WORDSIZE == 64
+
+/* We have to define the `uintmax_t' type using `ldiv_t'.  */
+typedef struct {
+	long int quot;		/* Quotient.  */
+	long int rem;		/* Remainder.  */
+} imaxdiv_t;
+
+#else
+
+/* We have to define the `uintmax_t' type using `lldiv_t'.  */
+typedef struct {
+	long long int quot;		/* Quotient.  */
+	long long int rem;		/* Remainder.  */
+} imaxdiv_t;
+
+#endif
+
+#endif /* inttypes.h */
diff --git a/include/iomux.h b/include/iomux.h
new file mode 100644
index 0000000..e6e1097
--- /dev/null
+++ b/include/iomux.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ */
+
+#ifndef _IO_MUX_H
+#define _IO_MUX_H
+
+#include <stdio_dev.h>
+
+/*
+ * Stuff required to support console multiplexing.
+ */
+
+/*
+ * Pointers to devices used for each file type.  Defined in console.c
+ * but storage is allocated in iomux.c.
+ */
+extern struct stdio_dev **console_devices[MAX_FILES];
+/*
+ * The count of devices assigned to each FILE.  Defined in console.c
+ * and populated in iomux.c.
+ */
+extern int cd_count[MAX_FILES];
+
+int iomux_doenv(const int, const char *);
+void iomux_printdevs(const int);
+struct stdio_dev *search_device(int, const char *);
+
+#endif /* _IO_MUX_H */
diff --git a/include/ioports.h b/include/ioports.h
new file mode 100644
index 0000000..1cd3ceb
--- /dev/null
+++ b/include/ioports.h
@@ -0,0 +1,62 @@
+/*
+ * definitions for MPC8xxx I/O Ports
+ *
+ * Murray.Jensen@cmst.csiro.au, 20-Oct-00
+ */
+
+/*
+ * this structure mirrors the layout of the five port registers in
+ * the internal memory map
+ */
+typedef struct {
+    unsigned int pdir;		/* Port Data Direction Register (35-3) */
+    unsigned int ppar;		/* Port Pin Assignment Register (35-4) */
+    unsigned int psor;		/* Port Special Options Register (35-5) */
+    unsigned int podr;		/* Port Open Drain Register (35-2) */
+    unsigned int pdat;		/* Port Data Register (35-3) */
+} ioport_t;
+
+/*
+ * this macro calculates the address within the internal
+ * memory map (im) of the set of registers for a port (idx)
+ *
+ * the internal memory map aligns the above structure on
+ * a 0x20 byte boundary
+ */
+#ifdef CONFIG_MPC85xx
+#define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20))
+#else
+#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
+#endif
+
+/*
+ * this structure provides configuration
+ * information for one port pin
+ */
+typedef struct {
+    unsigned char conf:1;	/* if 1, configure this port */
+    unsigned char ppar:1;	/* Port Pin Assignment Register (35-4) */
+    unsigned char psor:1;	/* Port Special Options Register (35-2) */
+    unsigned char pdir:1;	/* Port Data Direction Register (35-3) */
+    unsigned char podr:1;	/* Port Open Drain Register (35-2) */
+    unsigned char pdat:1;	/* Port Data Register (35-2) */
+} iop_conf_t;
+
+/*
+ * a table that contains configuration information for all 32 pins
+ *
+ * NOTE: in the second dimension of this table, index 0 refers to pin 31
+ * and index 31 refers to pin 0. this made the code in the table look more
+ * like the table in the 8260UM (and in the hymod manuals).
+ */
+extern const iop_conf_t iop_conf_tab[4][32];
+
+typedef struct {
+	unsigned char	port;
+	unsigned char	pin;
+	int		dir;
+	int		open_drain;
+	int		assign;
+} qe_iop_conf_t;
+
+#define QE_IOP_TAB_END	(-1)
diff --git a/include/iotrace.h b/include/iotrace.h
new file mode 100644
index 0000000..380da1f
--- /dev/null
+++ b/include/iotrace.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2014 Google, Inc.
+ */
+
+#ifndef __IOTRACE_H
+#define __IOTRACE_H
+
+//#include <common.h>
+#include <linux/types.h>
+
+/* Support up to the machine word length for now */
+typedef ulong iovalue_t;
+
+enum iotrace_flags {
+	IOT_8 = 0,
+	IOT_16,
+	IOT_32,
+
+	IOT_READ = 0 << 3,
+	IOT_WRITE = 1 << 3,
+};
+
+/**
+ * struct iotrace_record - Holds a single I/O trace record
+ *
+ * @flags: I/O access type
+ * @timestamp: Timestamp of access
+ * @addr: Address of access
+ * @value: Value written or read
+ */
+struct iotrace_record {
+	enum iotrace_flags flags;
+	u64 timestamp;
+	phys_addr_t addr;
+	iovalue_t value;
+};
+
+/*
+ * This file is designed to be included in arch/<arch>/include/asm/io.h.
+ * It redirects all IO access through a tracing/checksumming feature for
+ * testing purposes.
+ */
+
+#if defined(CONFIG_IO_TRACE) && !defined(IOTRACE_IMPL) && \
+	!defined(CONFIG_SPL_BUILD)
+
+#undef readl
+#define readl(addr)	iotrace_readl((const void *)(addr))
+
+#undef writel
+#define writel(val, addr)	iotrace_writel(val, (void *)(addr))
+
+#undef readw
+#define readw(addr)	iotrace_readw((const void *)(addr))
+
+#undef writew
+#define writew(val, addr)	iotrace_writew(val, (void *)(addr))
+
+#undef readb
+#define readb(addr)	iotrace_readb((const void *)(uintptr_t)addr)
+
+#undef writeb
+#define writeb(val, addr)	iotrace_writeb(val, (void *)(uintptr_t)addr)
+
+#endif
+
+/* Tracing functions which mirror their io.h counterparts */
+u32 iotrace_readl(const void *ptr);
+void iotrace_writel(ulong value, void *ptr);
+u16 iotrace_readw(const void *ptr);
+void iotrace_writew(ulong value, void *ptr);
+u8 iotrace_readb(const void *ptr);
+void iotrace_writeb(ulong value, void *ptr);
+
+/**
+ * iotrace_reset_checksum() - Reset the iotrace checksum
+ */
+void iotrace_reset_checksum(void);
+
+/**
+ * iotrace_get_checksum() - Get the current checksum value
+ *
+ * @return currect checksum value
+ */
+u32 iotrace_get_checksum(void);
+
+/**
+ * iotrace_set_region() - Set whether iotrace is limited to a specific
+ * io region.
+ *
+ * Defines the address and size of the limited region.
+ *
+ * @start: address of the beginning of the region
+ * @size: size of the region in bytes.
+ */
+void iotrace_set_region(ulong start, ulong size);
+
+/**
+ * iotrace_reset_region() - Reset the region limit
+ */
+void iotrace_reset_region(void);
+
+/**
+ * iotrace_get_region() - Get region information
+ *
+ * @start: Returns start address of region
+ * @size: Returns size of region in bytes
+ */
+void iotrace_get_region(ulong *start, ulong *size);
+
+/**
+ * iotrace_set_enabled() - Set whether iotracing is enabled or not
+ *
+ * This controls whether the checksum is updated and a trace record added
+ * for each I/O access.
+ *
+ * @enable: true to enable iotracing, false to disable
+ */
+void iotrace_set_enabled(int enable);
+
+/**
+ * iotrace_get_enabled() - Get whether iotracing is enabled or not
+ *
+ * @return true if enabled, false if disabled
+ */
+int iotrace_get_enabled(void);
+
+/**
+ * iotrace_set_buffer() - Set position and size of iotrace buffer
+ *
+ * Defines where the iotrace buffer goes, and resets the output pointer to
+ * the start of the buffer.
+ *
+ * The buffer can be 0 size in which case the checksum is updated but no
+ * trace records are writen. If the buffer is exhausted, the offset will
+ * continue to increase but not new data will be written.
+ *
+ * @start: Start address of buffer
+ * @size: Size of buffer in bytes
+ */
+void iotrace_set_buffer(ulong start, ulong size);
+
+/**
+ * iotrace_get_buffer() - Get buffer information
+ *
+ * @start: Returns start address of buffer
+ * @size: Returns actual size of buffer in bytes
+ * @needed_size: Returns needed size of buffer in bytes
+ * @offset: Returns the byte offset where the next output trace record will
+ * @count: Returns the number of trace records recorded
+ * be written (or would be if the buffer was large enough)
+ */
+void iotrace_get_buffer(ulong *start, ulong *size, ulong *needed_size, ulong *offset, ulong *count);
+
+#endif /* __IOTRACE_H */
diff --git a/include/ipu_pixfmt.h b/include/ipu_pixfmt.h
new file mode 100644
index 0000000..866ead0
--- /dev/null
+++ b/include/ipu_pixfmt.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Based on Linux IPU driver for MX51 (ipu.h):
+ *
+ * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __IPU_PIXFMT_H__
+#define __IPU_PIXFMT_H__
+
+#include <linux/list.h>
+#include <linux/fb.h>
+
+/*  IPU Pixel format definitions */
+#define fourcc(a, b, c, d)\
+	(((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+
+/*
+ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
+ * the same used by V4L2 API.
+ */
+
+#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')
+#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')
+#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')
+#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')
+
+#define IPU_PIX_FMT_RGB332  fourcc('R', 'G', 'B', '1')	/*<  8  RGB-3-3-2    */
+#define IPU_PIX_FMT_RGB555  fourcc('R', 'G', 'B', 'O')	/*< 16  RGB-5-5-5    */
+#define IPU_PIX_FMT_RGB565  fourcc('R', 'G', 'B', 'P')	/*< 1 6  RGB-5-6-5   */
+#define IPU_PIX_FMT_RGB666  fourcc('R', 'G', 'B', '6')	/*< 18  RGB-6-6-6    */
+#define IPU_PIX_FMT_BGR666  fourcc('B', 'G', 'R', '6')	/*< 18  BGR-6-6-6    */
+#define IPU_PIX_FMT_BGR24   fourcc('B', 'G', 'R', '3')	/*< 24  BGR-8-8-8    */
+#define IPU_PIX_FMT_RGB24   fourcc('R', 'G', 'B', '3')	/*< 24  RGB-8-8-8    */
+#define IPU_PIX_FMT_BGR32   fourcc('B', 'G', 'R', '4')	/*< 32  BGR-8-8-8-8  */
+#define IPU_PIX_FMT_BGRA32  fourcc('B', 'G', 'R', 'A')	/*< 32  BGR-8-8-8-8  */
+#define IPU_PIX_FMT_RGB32   fourcc('R', 'G', 'B', '4')	/*< 32  RGB-8-8-8-8  */
+#define IPU_PIX_FMT_RGBA32  fourcc('R', 'G', 'B', 'A')	/*< 32  RGB-8-8-8-8  */
+#define IPU_PIX_FMT_ABGR32  fourcc('A', 'B', 'G', 'R')	/*< 32  ABGR-8-8-8-8 */
+
+/* YUV Interleaved Formats */
+#define IPU_PIX_FMT_YUYV    fourcc('Y', 'U', 'Y', 'V')	/*< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_UYVY    fourcc('U', 'Y', 'V', 'Y')	/*< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_Y41P    fourcc('Y', '4', '1', 'P')	/*< 12 YUV 4:1:1 */
+#define IPU_PIX_FMT_YUV444  fourcc('Y', '4', '4', '4')	/*< 24 YUV 4:4:4 */
+
+/* two planes -- one Y, one Cb + Cr interleaved  */
+#define IPU_PIX_FMT_NV12    fourcc('N', 'V', '1', '2') /* 12  Y/CbCr 4:2:0  */
+
+#define IPU_PIX_FMT_GREY    fourcc('G', 'R', 'E', 'Y')	/*< 8  Greyscale */
+#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9')	/*< 9  YVU 4:1:0 */
+#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9')	/*< 9  YUV 4:1:0 */
+#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2')	/*< 12 YVU 4:2:0 */
+#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0')	/*< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2')	/*< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6')	/*< 16 YVU 4:2:2 */
+#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P')	/*< 16 YUV 4:2:2 */
+
+int ipuv3_fb_init(struct fb_videomode const *mode,
+		  uint8_t disp,
+		  uint32_t pixfmt);
+void ipuv3_fb_shutdown(void);
+
+#endif
diff --git a/include/key_matrix.h b/include/key_matrix.h
new file mode 100644
index 0000000..519722f
--- /dev/null
+++ b/include/key_matrix.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keyboard matrix helper functions
+ *
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef _KEY_MATRIX_H
+#define _KEY_MATRIX_H
+
+#include <common.h>
+
+/* Information about a matrix keyboard */
+struct key_matrix {
+	/* Dimensions of the keyboard matrix, in rows and columns */
+	int num_rows;
+	int num_cols;
+	int key_count;	/* number of keys in the matrix (= rows * cols) */
+
+	/*
+	 * Information about keycode mappings. The plain_keycode array must
+	 * exist but fn may be NULL in which case it is not decoded.
+	 */
+	const u8 *plain_keycode;        /* key code for each row / column */
+	const u8 *fn_keycode;           /* ...when Fn held down */
+	int fn_pos;                     /* position of Fn key in key (or -1) */
+	int ghost_filter;		/* non-zero to enable ghost filter */
+};
+
+/* Information about a particular key (row, column pair) in the matrix */
+struct key_matrix_key {
+	uint8_t row;	/* row number (0 = first) */
+	uint8_t col;	/* column number (0 = first) */
+	uint8_t valid;	/* 1 if valid, 0 to ignore this */
+};
+
+/**
+ * Decode a set of pressed keys into key codes
+ *
+ * Given a list of keys that are pressed, this converts this list into
+ * a list of key codes. Each of the keys has a valid flag, which can be
+ * used to mark a particular key as invalid (so that it is ignored).
+ *
+ * The plain keymap is used, unless the Fn key is detected along the way,
+ * at which point we switch to the Fn key map.
+ *
+ * If key ghosting is detected, we simply ignore the keys and return 0.
+ *
+ * @param config        Keyboard matrix config
+ * @param keys		List of keys to process (each is row, col)
+ * @param num_keys	Number of keys to process
+ * @param keycode	Returns a list of key codes, decoded from input
+ * @param max_keycodes	Size of key codes array (suggest 8)
+ *
+ */
+int key_matrix_decode(struct key_matrix *config, struct key_matrix_key *keys,
+		      int num_keys, int keycode[], int max_keycodes);
+
+/**
+ * Read the keyboard configuration out of the fdt.
+ *
+ * Decode properties of named "linux,<type>keymap" where <type> is either
+ * empty, or "fn-". Then set up the plain key map (and the FN keymap if
+ * present).
+ *
+ * @param config        Keyboard matrix config
+ * @param blob          FDT blob
+ * @param node          Node containing compatible data
+ * @return 0 if ok, -1 on error
+ */
+int key_matrix_decode_fdt(struct udevice *dev, struct key_matrix *config);
+
+/**
+ * Set up a new key matrix.
+ *
+ * @param config	Keyboard matrix config
+ * @param rows		Number of rows in key matrix
+ * @param cols		Number of columns in key matrix
+ * @param ghost_filter	Non-zero to enable ghost filtering
+ * @return 0 if ok, -1 on error
+ */
+int key_matrix_init(struct key_matrix *config, int rows, int cols,
+		    int ghost_filter);
+
+#endif
diff --git a/include/keyboard.h b/include/keyboard.h
new file mode 100644
index 0000000..7561954
--- /dev/null
+++ b/include/keyboard.h
@@ -0,0 +1,79 @@
+#ifndef __KEYBOARD_H
+#define __KEYBOARD_H
+
+#include <input.h>
+#include <stdio_dev.h>
+
+/**
+ * struct keyboard_priv - information about a keyboard, for the uclass
+ *
+ * @sdev:	stdio device
+ * @input:	input configuration (the driver may use this if desired)
+ */
+struct keyboard_priv {
+	struct stdio_dev sdev;
+
+	/*
+	 * This is set up by the uclass but will only be used if the driver
+	 * sets input.dev to its device pointer (it is initially NULL).
+	 */
+	struct input_config input;
+};
+
+/**
+ * struct keyboard_ops - keyboard device operations
+ */
+struct keyboard_ops {
+	/**
+	 * start() - enable the keyboard ready for use
+	 *
+	 * @dev:	Device to enable
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*start)(struct udevice *dev);
+
+	/**
+	 * stop() - disable the keyboard when no-longer needed
+	 *
+	 * @dev:	Device to disable
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*stop)(struct udevice *dev);
+
+	/**
+	 * tstc() - check if a key is available
+	 *
+	 * @dev:	Device to check
+	 * @return 0 if no key is available, 1 if a key is available, -ve on
+	 *	   error
+	 */
+	int (*tstc)(struct udevice *dev);
+
+	/**
+	 * getc() - get a key
+	 *
+	 * TODO(sjg@chromium.org): At present this method may wait if it calls
+	 * input_getc().
+	 *
+	 * @dev:	Device to read from
+	 * @return -EAGAIN if no key is available, otherwise key value read
+	 *	   (as ASCII).
+	 */
+	int (*getc)(struct udevice *dev);
+
+	/**
+	 * update_leds() - update keyboard LEDs
+	 *
+	 * This is called when the LEDs have changed and need to be updated.
+	 * For example, if 'caps lock' is pressed then this method will be
+	 * called with the new LED value.
+	 *
+	 * @dev:	Device to update
+	 * @leds:	New LED mask (see INPUT_LED_... in input.h)
+	 */
+	int (*update_leds)(struct udevice *dev, int leds);
+};
+
+#define keyboard_get_ops(dev)	((struct keyboard_ops *)(dev)->driver->ops)
+
+#endif /* __KEYBOARD_H */
diff --git a/include/kgdb.h b/include/kgdb.h
new file mode 100644
index 0000000..b6ba742
--- /dev/null
+++ b/include/kgdb.h
@@ -0,0 +1,70 @@
+#ifndef __KGDB_H__
+#define __KGDB_H__
+
+#include <asm/ptrace.h>
+
+#define KGDBERR_BADPARAMS	1
+#define KGDBERR_NOTHEXDIG	2
+#define KGDBERR_MEMFAULT	3
+#define KGDBERR_NOSPACE		4
+#define KGDBERR_ALIGNFAULT	5
+
+#define KGDBDATA_MAXREGS	8
+#define KGDBDATA_MAXPRIV	8
+
+#define KGDBEXIT_TYPEMASK	0xff
+
+#define KGDBEXIT_KILL		0
+#define KGDBEXIT_CONTINUE	1
+#define KGDBEXIT_SINGLE		2
+
+#define KGDBEXIT_WITHADDR	0x100
+
+typedef
+	struct {
+		int num;
+		unsigned long val;
+	}
+kgdb_reg;
+
+typedef
+	struct {
+		int sigval;
+		int extype;
+		unsigned long exaddr;
+		int nregs;
+		kgdb_reg regs[KGDBDATA_MAXREGS];
+		unsigned long private[KGDBDATA_MAXPRIV];
+	}
+kgdb_data;
+
+/* these functions are provided by the generic kgdb support */
+extern void kgdb_init(void);
+extern void kgdb_error(int);
+extern int kgdb_output_string(const char *, unsigned int);
+extern void breakpoint(void);
+
+/* these functions are provided by the platform specific kgdb support */
+extern void kgdb_flush_cache_range(void *, void *);
+extern void kgdb_flush_cache_all(void);
+extern int kgdb_setjmp(long *);
+extern void kgdb_longjmp(long *, int);
+extern void kgdb_enter(struct pt_regs *, kgdb_data *);
+extern void kgdb_exit(struct pt_regs *, kgdb_data *);
+extern int kgdb_getregs(struct pt_regs *, char *, int);
+extern void kgdb_putreg(struct pt_regs *, int, char *, int);
+extern void kgdb_putregs(struct pt_regs *, char *, int);
+extern int kgdb_trap(struct pt_regs *);
+extern void kgdb_breakpoint(int argc, char * const argv[]);
+
+/* these functions are provided by the platform serial driver */
+extern void kgdb_serial_init(void);
+extern int getDebugChar(void);
+extern void putDebugChar(int);
+extern void putDebugStr(const char *);
+extern void kgdb_interruptible(int);
+
+/* this is referenced in the trap handler for the platform */
+extern int (*debugger_exception_handler)(struct pt_regs *);
+
+#endif /* __KGDB_H__ */
diff --git a/include/linker_lists.h b/include/linker_lists.h
new file mode 100644
index 0000000..d775d04
--- /dev/null
+++ b/include/linker_lists.h
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/linker_lists.h
+ *
+ * Implementation of linker-generated arrays
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ */
+
+#ifndef __LINKER_LISTS_H__
+#define __LINKER_LISTS_H__
+
+#include <linux/compiler.h>
+
+/*
+ * There is no use in including this from ASM files.
+ * So just don't define anything when included from ASM.
+ */
+
+#if !defined(__ASSEMBLY__)
+
+/**
+ * llsym() - Access a linker-generated array entry
+ * @_type:	Data type of the entry
+ * @_name:	Name of the entry
+ * @_list:	name of the list. Should contain only characters allowed
+ *		in a C variable name!
+ */
+#define llsym(_type, _name, _list) \
+		((_type *)&_u_boot_list_2_##_list##_2_##_name)
+
+/**
+ * ll_entry_declare() - Declare linker-generated array entry
+ * @_type:	Data type of the entry
+ * @_name:	Name of the entry
+ * @_list:	name of the list. Should contain only characters allowed
+ *		in a C variable name!
+ *
+ * This macro declares a variable that is placed into a linker-generated
+ * array. This is a basic building block for more advanced use of linker-
+ * generated arrays. The user is expected to build their own macro wrapper
+ * around this one.
+ *
+ * A variable declared using this macro must be compile-time initialized.
+ *
+ * Special precaution must be made when using this macro:
+ *
+ * 1) The _type must not contain the "static" keyword, otherwise the
+ *    entry is generated and can be iterated but is listed in the map
+ *    file and cannot be retrieved by name.
+ *
+ * 2) In case a section is declared that contains some array elements AND
+ *    a subsection of this section is declared and contains some elements,
+ *    it is imperative that the elements are of the same type.
+ *
+ * 3) In case an outer section is declared that contains some array elements
+ *    AND an inner subsection of this section is declared and contains some
+ *    elements, then when traversing the outer section, even the elements of
+ *    the inner sections are present in the array.
+ *
+ * Example:
+ *
+ * ::
+ *
+ *   ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub) = {
+ *           .x = 3,
+ *           .y = 4,
+ *   };
+ */
+#define ll_entry_declare(_type, _name, _list)				\
+	_type _u_boot_list_2_##_list##_2_##_name __aligned(4)		\
+			__attribute__((unused,				\
+			section(".u_boot_list_2_"#_list"_2_"#_name)))
+
+/**
+ * ll_entry_declare_list() - Declare a list of link-generated array entries
+ * @_type:	Data type of each entry
+ * @_name:	Name of the entry
+ * @_list:	name of the list. Should contain only characters allowed
+ *		in a C variable name!
+ *
+ * This is like ll_entry_declare() but creates multiple entries. It should
+ * be assigned to an array.
+ *
+ * ::
+ *
+ *   ll_entry_declare_list(struct my_sub_cmd, my_sub_cmd, cmd_sub) = {
+ *        { .x = 3, .y = 4 },
+ *        { .x = 8, .y = 2 },
+ *        { .x = 1, .y = 7 }
+ *   };
+ */
+#define ll_entry_declare_list(_type, _name, _list)			\
+	_type _u_boot_list_2_##_list##_2_##_name[] __aligned(4)		\
+			__attribute__((unused,				\
+			section(".u_boot_list_2_"#_list"_2_"#_name)))
+
+/*
+ * We need a 0-byte-size type for iterator symbols, and the compiler
+ * does not allow defining objects of C type 'void'. Using an empty
+ * struct is allowed by the compiler, but causes gcc versions 4.4 and
+ * below to complain about aliasing. Therefore we use the next best
+ * thing: zero-sized arrays, which are both 0-byte-size and exempt from
+ * aliasing warnings.
+ */
+
+/**
+ * ll_entry_start() - Point to first entry of linker-generated array
+ * @_type:	Data type of the entry
+ * @_list:	Name of the list in which this entry is placed
+ *
+ * This function returns ``(_type *)`` pointer to the very first entry of a
+ * linker-generated array placed into subsection of .u_boot_list section
+ * specified by _list argument.
+ *
+ * Since this macro defines an array start symbol, its leftmost index
+ * must be 2 and its rightmost index must be 1.
+ *
+ * Example:
+ *
+ * ::
+ *
+ *   struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub);
+ */
+#define ll_entry_start(_type, _list)					\
+({									\
+	static char start[0] __aligned(4) __attribute__((unused,	\
+		section(".u_boot_list_2_"#_list"_1")));			\
+	(_type *)&start;						\
+})
+
+/**
+ * ll_entry_end() - Point after last entry of linker-generated array
+ * @_type:	Data type of the entry
+ * @_list:	Name of the list in which this entry is placed
+ *		(with underscores instead of dots)
+ *
+ * This function returns ``(_type *)`` pointer after the very last entry of
+ * a linker-generated array placed into subsection of .u_boot_list
+ * section specified by _list argument.
+ *
+ * Since this macro defines an array end symbol, its leftmost index
+ * must be 2 and its rightmost index must be 3.
+ *
+ * Example:
+ *
+ * ::
+ *
+ *   struct my_sub_cmd *msc = ll_entry_end(struct my_sub_cmd, cmd_sub);
+ */
+#define ll_entry_end(_type, _list)					\
+({									\
+	static char end[0] __aligned(4) __attribute__((unused,		\
+		section(".u_boot_list_2_"#_list"_3")));			\
+	(_type *)&end;							\
+})
+/**
+ * ll_entry_count() - Return the number of elements in linker-generated array
+ * @_type:	Data type of the entry
+ * @_list:	Name of the list of which the number of elements is computed
+ *
+ * This function returns the number of elements of a linker-generated array
+ * placed into subsection of .u_boot_list section specified by _list
+ * argument. The result is of an unsigned int type.
+ *
+ * Example:
+ *
+ * ::
+ *
+ *   int i;
+ *   const unsigned int count = ll_entry_count(struct my_sub_cmd, cmd_sub);
+ *   struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub);
+ *   for (i = 0; i < count; i++, msc++)
+ *           printf("Entry %i, x=%i y=%i\n", i, msc->x, msc->y);
+ */
+#define ll_entry_count(_type, _list)					\
+	({								\
+		_type *start = ll_entry_start(_type, _list);		\
+		_type *end = ll_entry_end(_type, _list);		\
+		unsigned int _ll_result = end - start;			\
+		_ll_result;						\
+	})
+
+/**
+ * ll_entry_get() - Retrieve entry from linker-generated array by name
+ * @_type:	Data type of the entry
+ * @_name:	Name of the entry
+ * @_list:	Name of the list in which this entry is placed
+ *
+ * This function returns a pointer to a particular entry in linker-generated
+ * array identified by the subsection of u_boot_list where the entry resides
+ * and it's name.
+ *
+ * Example:
+ *
+ * ::
+ *
+ *   ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub) = {
+ *           .x = 3,
+ *           .y = 4,
+ *   };
+ *   ...
+ *   struct my_sub_cmd *c = ll_entry_get(struct my_sub_cmd, my_sub_cmd, cmd_sub);
+ */
+#define ll_entry_get(_type, _name, _list)				\
+	({								\
+		extern _type _u_boot_list_2_##_list##_2_##_name;	\
+		_type *_ll_result =					\
+			&_u_boot_list_2_##_list##_2_##_name;		\
+		_ll_result;						\
+	})
+
+/**
+ * ll_start() - Point to first entry of first linker-generated array
+ * @_type:	Data type of the entry
+ *
+ * This function returns ``(_type *)`` pointer to the very first entry of
+ * the very first linker-generated array.
+ *
+ * Since this macro defines the start of the linker-generated arrays,
+ * its leftmost index must be 1.
+ *
+ * Example:
+ *
+ * ::
+ *
+ *   struct my_sub_cmd *msc = ll_start(struct my_sub_cmd);
+ */
+#define ll_start(_type)							\
+({									\
+	static char start[0] __aligned(4) __attribute__((unused,	\
+		section(".u_boot_list_1")));				\
+	(_type *)&start;						\
+})
+
+/**
+ * ll_end() - Point after last entry of last linker-generated array
+ * @_type:	Data type of the entry
+ *
+ * This function returns ``(_type *)`` pointer after the very last entry of
+ * the very last linker-generated array.
+ *
+ * Since this macro defines the end of the linker-generated arrays,
+ * its leftmost index must be 3.
+ *
+ * Example:
+ *
+ * ::
+ *
+ *   struct my_sub_cmd *msc = ll_end(struct my_sub_cmd);
+ */
+#define ll_end(_type)							\
+({									\
+	static char end[0] __aligned(4) __attribute__((unused,		\
+		section(".u_boot_list_3")));				\
+	(_type *)&end;							\
+})
+
+#endif /* __ASSEMBLY__ */
+
+#endif	/* __LINKER_LISTS_H__ */
diff --git a/include/linux/apm_bios.h b/include/linux/apm_bios.h
new file mode 100644
index 0000000..3dabc3f
--- /dev/null
+++ b/include/linux/apm_bios.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _LINUX_APM_H
+#define _LINUX_APM_H
+
+/*
+ * Include file for the interface to an APM BIOS
+ * Copyright 1994-2001 Stephen Rothwell (sfr@canb.auug.org.au)
+ */
+
+#include <linux/types.h>
+
+typedef unsigned short	apm_event_t;
+typedef unsigned short	apm_eventinfo_t;
+
+struct apm_bios_info {
+	__u16	version;
+	__u16	cseg;
+	__u32	offset;
+	__u16	cseg_16;
+	__u16	dseg;
+	__u16	flags;
+	__u16	cseg_len;
+	__u16	cseg_16_len;
+	__u16	dseg_len;
+};
+
+#ifdef __KERNEL__
+
+#define APM_CS		(GDT_ENTRY_APMBIOS_BASE * 8)
+#define APM_CS_16	(APM_CS + 8)
+#define APM_DS		(APM_CS_16 + 8)
+
+/* Results of APM Installation Check */
+#define APM_16_BIT_SUPPORT	0x0001
+#define APM_32_BIT_SUPPORT	0x0002
+#define APM_IDLE_SLOWS_CLOCK	0x0004
+#define APM_BIOS_DISABLED      	0x0008
+#define APM_BIOS_DISENGAGED     0x0010
+
+/*
+ * Data for APM that is persistent across module unload/load
+ */
+struct apm_info {
+	struct apm_bios_info	bios;
+	unsigned short		connection_version;
+	int			get_power_status_broken;
+	int			get_power_status_swabinminutes;
+	int			allow_ints;
+	int			forbid_idle;
+	int			realmode_power_off;
+	int			disabled;
+};
+
+/*
+ * The APM function codes
+ */
+#define	APM_FUNC_INST_CHECK	0x5300
+#define	APM_FUNC_REAL_CONN	0x5301
+#define	APM_FUNC_16BIT_CONN	0x5302
+#define	APM_FUNC_32BIT_CONN	0x5303
+#define	APM_FUNC_DISCONN	0x5304
+#define	APM_FUNC_IDLE		0x5305
+#define	APM_FUNC_BUSY		0x5306
+#define	APM_FUNC_SET_STATE	0x5307
+#define	APM_FUNC_ENABLE_PM	0x5308
+#define	APM_FUNC_RESTORE_BIOS	0x5309
+#define	APM_FUNC_GET_STATUS	0x530a
+#define	APM_FUNC_GET_EVENT	0x530b
+#define	APM_FUNC_GET_STATE	0x530c
+#define	APM_FUNC_ENABLE_DEV_PM	0x530d
+#define	APM_FUNC_VERSION	0x530e
+#define	APM_FUNC_ENGAGE_PM	0x530f
+#define	APM_FUNC_GET_CAP	0x5310
+#define	APM_FUNC_RESUME_TIMER	0x5311
+#define	APM_FUNC_RESUME_ON_RING	0x5312
+#define	APM_FUNC_TIMER		0x5313
+
+/*
+ * Function code for APM_FUNC_RESUME_TIMER
+ */
+#define	APM_FUNC_DISABLE_TIMER	0
+#define	APM_FUNC_GET_TIMER	1
+#define	APM_FUNC_SET_TIMER	2
+
+/*
+ * Function code for APM_FUNC_RESUME_ON_RING
+ */
+#define	APM_FUNC_DISABLE_RING	0
+#define	APM_FUNC_ENABLE_RING	1
+#define	APM_FUNC_GET_RING	2
+
+/*
+ * Function code for APM_FUNC_TIMER_STATUS
+ */
+#define	APM_FUNC_TIMER_DISABLE	0
+#define	APM_FUNC_TIMER_ENABLE	1
+#define	APM_FUNC_TIMER_GET	2
+
+/*
+ * in arch/i386/kernel/setup.c
+ */
+extern struct apm_info	apm_info;
+
+#endif	/* __KERNEL__ */
+
+/*
+ * Power states
+ */
+#define APM_STATE_READY		0x0000
+#define APM_STATE_STANDBY	0x0001
+#define APM_STATE_SUSPEND	0x0002
+#define APM_STATE_OFF		0x0003
+#define APM_STATE_BUSY		0x0004
+#define APM_STATE_REJECT	0x0005
+#define APM_STATE_OEM_SYS	0x0020
+#define APM_STATE_OEM_DEV	0x0040
+
+#define APM_STATE_DISABLE	0x0000
+#define APM_STATE_ENABLE	0x0001
+
+#define APM_STATE_DISENGAGE	0x0000
+#define APM_STATE_ENGAGE	0x0001
+
+/*
+ * Events (results of Get PM Event)
+ */
+#define APM_SYS_STANDBY		0x0001
+#define APM_SYS_SUSPEND		0x0002
+#define APM_NORMAL_RESUME	0x0003
+#define APM_CRITICAL_RESUME	0x0004
+#define APM_LOW_BATTERY		0x0005
+#define APM_POWER_STATUS_CHANGE	0x0006
+#define APM_UPDATE_TIME		0x0007
+#define APM_CRITICAL_SUSPEND	0x0008
+#define APM_USER_STANDBY	0x0009
+#define APM_USER_SUSPEND	0x000a
+#define APM_STANDBY_RESUME	0x000b
+#define APM_CAPABILITY_CHANGE	0x000c
+
+/*
+ * Error codes
+ */
+#define APM_SUCCESS		0x00
+#define APM_DISABLED		0x01
+#define APM_CONNECTED		0x02
+#define APM_NOT_CONNECTED	0x03
+#define APM_16_CONNECTED	0x05
+#define APM_16_UNSUPPORTED	0x06
+#define APM_32_CONNECTED	0x07
+#define APM_32_UNSUPPORTED	0x08
+#define APM_BAD_DEVICE		0x09
+#define APM_BAD_PARAM		0x0a
+#define APM_NOT_ENGAGED		0x0b
+#define APM_BAD_FUNCTION	0x0c
+#define APM_RESUME_DISABLED	0x0d
+#define APM_NO_ERROR		0x53
+#define APM_BAD_STATE		0x60
+#define APM_NO_EVENTS		0x80
+#define APM_NOT_PRESENT		0x86
+
+/*
+ * APM Device IDs
+ */
+#define APM_DEVICE_BIOS		0x0000
+#define APM_DEVICE_ALL		0x0001
+#define APM_DEVICE_DISPLAY	0x0100
+#define APM_DEVICE_STORAGE	0x0200
+#define APM_DEVICE_PARALLEL	0x0300
+#define APM_DEVICE_SERIAL	0x0400
+#define APM_DEVICE_NETWORK	0x0500
+#define APM_DEVICE_PCMCIA	0x0600
+#define APM_DEVICE_BATTERY	0x8000
+#define APM_DEVICE_OEM		0xe000
+#define APM_DEVICE_OLD_ALL	0xffff
+#define APM_DEVICE_CLASS	0x00ff
+#define APM_DEVICE_MASK		0xff00
+
+#ifdef __KERNEL__
+/*
+ * This is the "All Devices" ID communicated to the BIOS
+ */
+#define APM_DEVICE_BALL		((apm_info.connection_version > 0x0100) ? \
+				 APM_DEVICE_ALL : APM_DEVICE_OLD_ALL)
+#endif
+
+/*
+ * Battery status
+ */
+#define APM_MAX_BATTERIES	2
+
+/*
+ * APM defined capability bit flags
+ */
+#define APM_CAP_GLOBAL_STANDBY		0x0001
+#define APM_CAP_GLOBAL_SUSPEND		0x0002
+#define APM_CAP_RESUME_STANDBY_TIMER	0x0004 /* Timer resume from standby */
+#define APM_CAP_RESUME_SUSPEND_TIMER	0x0008 /* Timer resume from suspend */
+#define APM_CAP_RESUME_STANDBY_RING	0x0010 /* Resume on Ring fr standby */
+#define APM_CAP_RESUME_SUSPEND_RING	0x0020 /* Resume on Ring fr suspend */
+#define APM_CAP_RESUME_STANDBY_PCMCIA	0x0040 /* Resume on PCMCIA Ring	*/
+#define APM_CAP_RESUME_SUSPEND_PCMCIA	0x0080 /* Resume on PCMCIA Ring	*/
+
+/*
+ * ioctl operations
+ */
+#include <linux/ioctl.h>
+
+#define APM_IOC_STANDBY		_IO('A', 1)
+#define APM_IOC_SUSPEND		_IO('A', 2)
+
+#endif	/* LINUX_APM_H */
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
new file mode 100644
index 0000000..2d1e6cc
--- /dev/null
+++ b/include/linux/arm-smccc.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015, Linaro Limited
+ */
+#ifndef __LINUX_ARM_SMCCC_H
+#define __LINUX_ARM_SMCCC_H
+
+/*
+ * This file provides common defines for ARM SMC Calling Convention as
+ * specified in
+ * http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
+ */
+
+#define ARM_SMCCC_STD_CALL		0
+#define ARM_SMCCC_FAST_CALL		1
+#define ARM_SMCCC_TYPE_SHIFT		31
+
+#define ARM_SMCCC_SMC_32		0
+#define ARM_SMCCC_SMC_64		1
+#define ARM_SMCCC_CALL_CONV_SHIFT	30
+
+#define ARM_SMCCC_OWNER_MASK		0x3F
+#define ARM_SMCCC_OWNER_SHIFT		24
+
+#define ARM_SMCCC_FUNC_MASK		0xFFFF
+
+#define ARM_SMCCC_IS_FAST_CALL(smc_val)	\
+	((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT))
+#define ARM_SMCCC_IS_64(smc_val) \
+	((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT))
+#define ARM_SMCCC_FUNC_NUM(smc_val)	((smc_val) & ARM_SMCCC_FUNC_MASK)
+#define ARM_SMCCC_OWNER_NUM(smc_val) \
+	(((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK)
+
+#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \
+	(((type) << ARM_SMCCC_TYPE_SHIFT) | \
+	((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \
+	(((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \
+	((func_num) & ARM_SMCCC_FUNC_MASK))
+
+#define ARM_SMCCC_OWNER_ARCH		0
+#define ARM_SMCCC_OWNER_CPU		1
+#define ARM_SMCCC_OWNER_SIP		2
+#define ARM_SMCCC_OWNER_OEM		3
+#define ARM_SMCCC_OWNER_STANDARD	4
+#define ARM_SMCCC_OWNER_TRUSTED_APP	48
+#define ARM_SMCCC_OWNER_TRUSTED_APP_END	49
+#define ARM_SMCCC_OWNER_TRUSTED_OS	50
+#define ARM_SMCCC_OWNER_TRUSTED_OS_END	63
+
+#define ARM_SMCCC_QUIRK_NONE		0
+#define ARM_SMCCC_QUIRK_QCOM_A6		1 /* Save/restore register a6 */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/linkage.h>
+#include <linux/types.h>
+/**
+ * struct arm_smccc_res - Result from SMC/HVC call
+ * @a0-a3 result values from registers 0 to 3
+ */
+struct arm_smccc_res {
+	unsigned long a0;
+	unsigned long a1;
+	unsigned long a2;
+	unsigned long a3;
+};
+
+/**
+ * struct arm_smccc_quirk - Contains quirk information
+ * @id: quirk identification
+ * @state: quirk specific information
+ * @a6: Qualcomm quirk entry for returning post-smc call contents of a6
+ */
+struct arm_smccc_quirk {
+	int	id;
+	union {
+		unsigned long a6;
+	} state;
+};
+
+/**
+ * __arm_smccc_smc() - make SMC calls
+ * @a0-a7: arguments passed in registers 0 to 7
+ * @res: result values from registers 0 to 3
+ * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required.
+ *
+ * This function is used to make SMC calls following SMC Calling Convention.
+ * The content of the supplied param are copied to registers 0 to 7 prior
+ * to the SMC instruction. The return values are updated with the content
+ * from register 0 to 3 on return from the SMC instruction.  An optional
+ * quirk structure provides vendor specific behavior.
+ */
+asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1,
+			unsigned long a2, unsigned long a3, unsigned long a4,
+			unsigned long a5, unsigned long a6, unsigned long a7,
+			struct arm_smccc_res *res, struct arm_smccc_quirk *quirk);
+
+/**
+ * __arm_smccc_hvc() - make HVC calls
+ * @a0-a7: arguments passed in registers 0 to 7
+ * @res: result values from registers 0 to 3
+ * @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required.
+ *
+ * This function is used to make HVC calls following SMC Calling
+ * Convention.  The content of the supplied param are copied to registers 0
+ * to 7 prior to the HVC instruction. The return values are updated with
+ * the content from register 0 to 3 on return from the HVC instruction.  An
+ * optional quirk structure provides vendor specific behavior.
+ */
+asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
+			unsigned long a2, unsigned long a3, unsigned long a4,
+			unsigned long a5, unsigned long a6, unsigned long a7,
+			struct arm_smccc_res *res, struct arm_smccc_quirk *quirk);
+
+#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL)
+
+#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__)
+
+#define arm_smccc_hvc(...) __arm_smccc_hvc(__VA_ARGS__, NULL)
+
+#define arm_smccc_hvc_quirk(...) __arm_smccc_hvc(__VA_ARGS__)
+
+#endif /*__ASSEMBLY__*/
+#endif /*__LINUX_ARM_SMCCC_H*/
diff --git a/include/linux/bch.h b/include/linux/bch.h
new file mode 100644
index 0000000..1305d2c
--- /dev/null
+++ b/include/linux/bch.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Generic binary BCH encoding/decoding library
+ *
+ * Copyright © 2011 Parrot S.A.
+ *
+ * Author: Ivan Djelic <ivan.djelic@parrot.com>
+ *
+ * Description:
+ *
+ * This library provides runtime configurable encoding/decoding of binary
+ * Bose-Chaudhuri-Hocquenghem (BCH) codes.
+*/
+#ifndef _BCH_H
+#define _BCH_H
+
+#include <linux/types.h>
+
+/**
+ * struct bch_control - BCH control structure
+ * @m:          Galois field order
+ * @n:          maximum codeword size in bits (= 2^m-1)
+ * @t:          error correction capability in bits
+ * @ecc_bits:   ecc exact size in bits, i.e. generator polynomial degree (<=m*t)
+ * @ecc_bytes:  ecc max size (m*t bits) in bytes
+ * @a_pow_tab:  Galois field GF(2^m) exponentiation lookup table
+ * @a_log_tab:  Galois field GF(2^m) log lookup table
+ * @mod8_tab:   remainder generator polynomial lookup tables
+ * @ecc_buf:    ecc parity words buffer
+ * @ecc_buf2:   ecc parity words buffer
+ * @xi_tab:     GF(2^m) base for solving degree 2 polynomial roots
+ * @syn:        syndrome buffer
+ * @cache:      log-based polynomial representation buffer
+ * @elp:        error locator polynomial
+ * @poly_2t:    temporary polynomials of degree 2t
+ */
+struct bch_control {
+	unsigned int    m;
+	unsigned int    n;
+	unsigned int    t;
+	unsigned int    ecc_bits;
+	unsigned int    ecc_bytes;
+/* private: */
+	uint16_t       *a_pow_tab;
+	uint16_t       *a_log_tab;
+	uint32_t       *mod8_tab;
+	uint32_t       *ecc_buf;
+	uint32_t       *ecc_buf2;
+	unsigned int   *xi_tab;
+	unsigned int   *syn;
+	int            *cache;
+	struct gf_poly *elp;
+	struct gf_poly *poly_2t[4];
+};
+
+struct bch_control *init_bch(int m, int t, unsigned int prim_poly);
+
+void free_bch(struct bch_control *bch);
+
+void encode_bch(struct bch_control *bch, const uint8_t *data,
+		unsigned int len, uint8_t *ecc);
+
+int decode_bch(struct bch_control *bch, const uint8_t *data, unsigned int len,
+	       const uint8_t *recv_ecc, const uint8_t *calc_ecc,
+	       const unsigned int *syn, unsigned int *errloc);
+
+#endif /* _BCH_H */
diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
new file mode 100644
index 0000000..8b9d6ff
--- /dev/null
+++ b/include/linux/bitfield.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2014 Felix Fietkau <nbd@nbd.name>
+ * Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _LINUX_BITFIELD_H
+#define _LINUX_BITFIELD_H
+
+#include <linux/bug.h>
+
+/*
+ * Bitfield access macros
+ *
+ * FIELD_{GET,PREP} macros take as first parameter shifted mask
+ * from which they extract the base mask and shift amount.
+ * Mask must be a compilation time constant.
+ *
+ * Example:
+ *
+ *  #define REG_FIELD_A  GENMASK(6, 0)
+ *  #define REG_FIELD_B  BIT(7)
+ *  #define REG_FIELD_C  GENMASK(15, 8)
+ *  #define REG_FIELD_D  GENMASK(31, 16)
+ *
+ * Get:
+ *  a = FIELD_GET(REG_FIELD_A, reg);
+ *  b = FIELD_GET(REG_FIELD_B, reg);
+ *
+ * Set:
+ *  reg = FIELD_PREP(REG_FIELD_A, 1) |
+ *	  FIELD_PREP(REG_FIELD_B, 0) |
+ *	  FIELD_PREP(REG_FIELD_C, c) |
+ *	  FIELD_PREP(REG_FIELD_D, 0x40);
+ *
+ * Modify:
+ *  reg &= ~REG_FIELD_C;
+ *  reg |= FIELD_PREP(REG_FIELD_C, c);
+ */
+
+#define __bf_shf(x) (__builtin_ffsll(x) - 1)
+
+#define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx)			\
+	({								\
+		BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask),		\
+				 _pfx "mask is not constant");		\
+		BUILD_BUG_ON_MSG(!(_mask), _pfx "mask is zero");	\
+		BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ?		\
+				 ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
+				 _pfx "value too large for the field"); \
+		BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull,		\
+				 _pfx "type of reg too small for mask"); \
+		__BUILD_BUG_ON_NOT_POWER_OF_2((_mask) +			\
+					      (1ULL << __bf_shf(_mask))); \
+	})
+
+/**
+ * FIELD_FIT() - check if value fits in the field
+ * @_mask: shifted mask defining the field's length and position
+ * @_val:  value to test against the field
+ *
+ * Return: true if @_val can fit inside @_mask, false if @_val is too big.
+ */
+#define FIELD_FIT(_mask, _val)						\
+	({								\
+		__BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_FIT: ");	\
+		!((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \
+	})
+
+/**
+ * FIELD_PREP() - prepare a bitfield element
+ * @_mask: shifted mask defining the field's length and position
+ * @_val:  value to put in the field
+ *
+ * FIELD_PREP() masks and shifts up the value.  The result should
+ * be combined with other fields of the bitfield using logical OR.
+ */
+#define FIELD_PREP(_mask, _val)						\
+	({								\
+		__BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");	\
+		((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask);	\
+	})
+
+/**
+ * FIELD_GET() - extract a bitfield element
+ * @_mask: shifted mask defining the field's length and position
+ * @_reg:  32bit value of entire bitfield
+ *
+ * FIELD_GET() extracts the field specified by @_mask from the
+ * bitfield passed in as @_reg by masking and shifting it down.
+ */
+#define FIELD_GET(_mask, _reg)						\
+	({								\
+		__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: ");	\
+		(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask));	\
+	})
+
+#endif
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
new file mode 100644
index 0000000..4a54ae0
--- /dev/null
+++ b/include/linux/bitmap.h
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+#ifndef __LINUX_BITMAP_H
+#define __LINUX_BITMAP_H
+
+#include <asm/types.h>
+#include <linux/types.h>
+#include <linux/bitops.h>
+
+#define small_const_nbits(nbits) \
+	(__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG)
+
+static inline void bitmap_zero(unsigned long *dst, int nbits)
+{
+	if (small_const_nbits(nbits)) {
+		*dst = 0UL;
+	} else {
+		int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
+
+		memset(dst, 0, len);
+	}
+}
+
+#endif /* __LINUX_BITMAP_H */
diff --git a/include/linux/bitops.h b/include/linux/bitops.h
new file mode 100644
index 0000000..259df43
--- /dev/null
+++ b/include/linux/bitops.h
@@ -0,0 +1,207 @@
+#ifndef _LINUX_BITOPS_H
+#define _LINUX_BITOPS_H
+
+#include <asm/types.h>
+#include <asm-generic/bitsperlong.h>
+#include <linux/compiler.h>
+
+#ifdef	__KERNEL__
+#define BIT(nr)			(1UL << (nr))
+#define BIT_ULL(nr)		(1ULL << (nr))
+#define BIT_MASK(nr)		(1UL << ((nr) % BITS_PER_LONG))
+#define BIT_WORD(nr)		((nr) / BITS_PER_LONG)
+#define BIT_ULL_MASK(nr)	(1ULL << ((nr) % BITS_PER_LONG_LONG))
+#define BIT_ULL_WORD(nr)	((nr) / BITS_PER_LONG_LONG)
+#define BITS_PER_BYTE		8
+#define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+#endif
+
+/*
+ * Create a contiguous bitmask starting at bit position @l and ending at
+ * position @h. For example
+ * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000.
+ */
+#ifdef CONFIG_SANDBOX
+#define GENMASK(h, l) \
+	(((~0UL) << (l)) & (~0UL >> (CONFIG_SANDBOX_BITS_PER_LONG - 1 - (h))))
+#else
+#define GENMASK(h, l) \
+	(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
+#endif
+
+#define GENMASK_ULL(h, l) \
+	(((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+static inline int generic_ffs(int x)
+{
+	int r = 1;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff)) {
+		x >>= 16;
+		r += 16;
+	}
+	if (!(x & 0xff)) {
+		x >>= 8;
+		r += 8;
+	}
+	if (!(x & 0xf)) {
+		x >>= 4;
+		r += 4;
+	}
+	if (!(x & 3)) {
+		x >>= 2;
+		r += 2;
+	}
+	if (!(x & 1)) {
+		x >>= 1;
+		r += 1;
+	}
+	return r;
+}
+
+/**
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static inline int generic_fls(int x)
+{
+	int r = 32;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff0000u)) {
+		x <<= 16;
+		r -= 16;
+	}
+	if (!(x & 0xff000000u)) {
+		x <<= 8;
+		r -= 8;
+	}
+	if (!(x & 0xf0000000u)) {
+		x <<= 4;
+		r -= 4;
+	}
+	if (!(x & 0xc0000000u)) {
+		x <<= 2;
+		r -= 2;
+	}
+	if (!(x & 0x80000000u)) {
+		x <<= 1;
+		r -= 1;
+	}
+	return r;
+}
+
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+static inline unsigned int generic_hweight32(unsigned int w)
+{
+	unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555);
+	res = (res & 0x33333333) + ((res >> 2) & 0x33333333);
+	res = (res & 0x0F0F0F0F) + ((res >> 4) & 0x0F0F0F0F);
+	res = (res & 0x00FF00FF) + ((res >> 8) & 0x00FF00FF);
+	return (res & 0x0000FFFF) + ((res >> 16) & 0x0000FFFF);
+}
+
+static inline unsigned int generic_hweight16(unsigned int w)
+{
+	unsigned int res = (w & 0x5555) + ((w >> 1) & 0x5555);
+	res = (res & 0x3333) + ((res >> 2) & 0x3333);
+	res = (res & 0x0F0F) + ((res >> 4) & 0x0F0F);
+	return (res & 0x00FF) + ((res >> 8) & 0x00FF);
+}
+
+static inline unsigned int generic_hweight8(unsigned int w)
+{
+	unsigned int res = (w & 0x55) + ((w >> 1) & 0x55);
+	res = (res & 0x33) + ((res >> 2) & 0x33);
+	return (res & 0x0F) + ((res >> 4) & 0x0F);
+}
+
+#include <asm/bitops.h>
+
+/* linux/include/asm-generic/bitops/non-atomic.h */
+
+#ifndef PLATFORM__SET_BIT
+# define __set_bit generic_set_bit
+#endif
+
+#ifndef PLATFORM__CLEAR_BIT
+# define __clear_bit generic_clear_bit
+#endif
+
+#ifndef PLATFORM_FFS
+# define ffs generic_ffs
+#endif
+
+#ifndef PLATFORM_FLS
+# define fls generic_fls
+#endif
+
+static inline unsigned fls_long(unsigned long l)
+{
+	if (sizeof(l) == 4)
+		return fls(l);
+	return fls64(l);
+}
+
+/**
+ * __ffs64 - find first set bit in a 64 bit word
+ * @word: The 64 bit word
+ *
+ * On 64 bit arches this is a synomyn for __ffs
+ * The result is not defined if no bits are set, so check that @word
+ * is non-zero before calling this.
+ */
+static inline unsigned long __ffs64(u64 word)
+{
+#if BITS_PER_LONG == 32
+	if (((u32)word) == 0UL)
+		return __ffs((u32)(word >> 32)) + 32;
+#elif BITS_PER_LONG != 64
+#error BITS_PER_LONG not 32 or 64
+#endif
+	return __ffs((unsigned long)word);
+}
+
+/**
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void generic_set_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p  |= mask;
+}
+
+static inline void generic_clear_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p &= ~mask;
+}
+
+#endif
diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h
new file mode 100644
index 0000000..8ec9411
--- /dev/null
+++ b/include/linux/bitrev.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _LINUX_BITREV_H
+#define _LINUX_BITREV_H
+
+#include <linux/types.h>
+
+#ifdef CONFIG_HAVE_ARCH_BITREVERSE
+#include <asm/bitrev.h>
+
+#define __bitrev32 __arch_bitrev32
+#define __bitrev16 __arch_bitrev16
+#define __bitrev8 __arch_bitrev8
+
+#else
+extern u8 const byte_rev_table[256];
+static inline u8 __bitrev8(u8 byte)
+{
+	return byte_rev_table[byte];
+}
+
+static inline u16 __bitrev16(u16 x)
+{
+	return (__bitrev8(x & 0xff) << 8) | __bitrev8(x >> 8);
+}
+
+static inline u32 __bitrev32(u32 x)
+{
+	return (__bitrev16(x & 0xffff) << 16) | __bitrev16(x >> 16);
+}
+
+#endif /* CONFIG_HAVE_ARCH_BITREVERSE */
+
+#define __bitrev8x4(x)	(__bitrev32(swab32(x)))
+
+#define __constant_bitrev32(x)		\
+({					\
+	u32 __x = x;			\
+	__x = (__x >> 16) | (__x << 16);\
+	__x = ((__x & (u32)0xFF00FF00UL) >> 8) | ((__x & (u32)0x00FF00FFUL) << 8);	\
+	__x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << 4);	\
+	__x = ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << 2);	\
+	__x = ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << 1);	\
+	__x;				\
+})
+
+#define __constant_bitrev16(x)		\
+({					\
+	u16 __x = x;			\
+	__x = (__x >> 8) | (__x << 8);	\
+	__x = ((__x & (u16)0xF0F0U) >> 4) | ((__x & (u16)0x0F0FU) << 4); \
+	__x = ((__x & (u16)0xCCCCU) >> 2) | ((__x & (u16)0x3333U) << 2); \
+	__x = ((__x & (u16)0xAAAAU) >> 1) | ((__x & (u16)0x5555U) << 1); \
+	__x;				\
+})
+
+#define __constant_bitrev8x4(x)		\
+({					\
+	u32 __x = x;			\
+	__x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << 4);	\
+	__x = ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << 2);	\
+	__x = ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << 1);	\
+	__x;				\
+})
+
+#define __constant_bitrev8(x)		\
+({					\
+	u8 __x = x;			\
+	__x = (__x >> 4) | (__x << 4);	\
+	__x = ((__x & (u8)0xCCU) >> 2) | ((__x & (u8)0x33U) << 2);	\
+	__x = ((__x & (u8)0xAAU) >> 1) | ((__x & (u8)0x55U) << 1);	\
+	__x;				\
+})
+
+#define bitrev32(x)			\
+({					\
+	u32 __x = x;			\
+	__builtin_constant_p(__x) ?	\
+	__constant_bitrev32(__x) :	\
+	__bitrev32(__x);		\
+})
+
+#define bitrev16(x)			\
+({					\
+	u16 __x = x;			\
+	__builtin_constant_p(__x) ?	\
+	__constant_bitrev16(__x) :	\
+	__bitrev16(__x);		\
+})
+
+#define bitrev8x4(x)			\
+({					\
+	u32 __x = x;			\
+	__builtin_constant_p(__x) ?	\
+	__constant_bitrev8x4(__x) :	\
+	__bitrev8x4(__x);		\
+})
+
+#define bitrev8(x)			\
+({					\
+	u8 __x = x;			\
+	__builtin_constant_p(__x) ?	\
+	__constant_bitrev8(__x) :	\
+	__bitrev8(__x)	;		\
+})
+#endif /* _LINUX_BITREV_H */
diff --git a/include/linux/bug.h b/include/linux/bug.h
new file mode 100644
index 0000000..29f8416
--- /dev/null
+++ b/include/linux/bug.h
@@ -0,0 +1,52 @@
+#ifndef _LINUX_BUG_H
+#define _LINUX_BUG_H
+
+#include <vsprintf.h> /* for panic() */
+#include <linux/build_bug.h>
+#include <linux/compiler.h>
+#include <linux/printk.h>
+
+#define BUG() do { \
+	printk("BUG at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
+	panic("BUG!"); \
+} while (0)
+
+#define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while (0)
+
+#define WARN_ON(condition) ({						\
+	int __ret_warn_on = !!(condition);				\
+	if (unlikely(__ret_warn_on))					\
+		printk("WARNING at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
+	unlikely(__ret_warn_on);					\
+})
+
+#define WARN(condition, format...) ({                   \
+	int __ret_warn_on = !!(condition);              \
+	if (unlikely(__ret_warn_on))                    \
+		printf(format);                  \
+	unlikely(__ret_warn_on);                    \
+})
+
+#define WARN_ON_ONCE(condition)	({				\
+	static bool __warned;					\
+	int __ret_warn_once = !!(condition);			\
+								\
+	if (unlikely(__ret_warn_once && !__warned)) {		\
+		__warned = true;				\
+		WARN_ON(1);					\
+	}							\
+	unlikely(__ret_warn_once);				\
+})
+
+#define WARN_ONCE(condition, format...) ({          \
+	static bool __warned;     \
+	int __ret_warn_once = !!(condition);            \
+								\
+	if (unlikely(__ret_warn_once && !__warned)) {       \
+		__warned = true;                \
+		WARN(1, format);                \
+	}                           \
+	unlikely(__ret_warn_once);              \
+})
+
+#endif	/* _LINUX_BUG_H */
diff --git a/include/linux/build_bug.h b/include/linux/build_bug.h
new file mode 100644
index 0000000..b7d22d6
--- /dev/null
+++ b/include/linux/build_bug.h
@@ -0,0 +1,84 @@
+#ifndef _LINUX_BUILD_BUG_H
+#define _LINUX_BUILD_BUG_H
+
+#include <linux/compiler.h>
+
+#ifdef __CHECKER__
+#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) (0)
+#define BUILD_BUG_ON_NOT_POWER_OF_2(n) (0)
+#define BUILD_BUG_ON_ZERO(e) (0)
+#define BUILD_BUG_ON_NULL(e) ((void *)0)
+#define BUILD_BUG_ON_INVALID(e) (0)
+#define BUILD_BUG_ON_MSG(cond, msg) (0)
+#define BUILD_BUG_ON(condition) (0)
+#define BUILD_BUG() (0)
+#else /* __CHECKER__ */
+
+/* Force a compilation error if a constant expression is not a power of 2 */
+#define __BUILD_BUG_ON_NOT_POWER_OF_2(n)	\
+	BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
+#define BUILD_BUG_ON_NOT_POWER_OF_2(n)			\
+	BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0))
+
+/*
+ * Force a compilation error if condition is true, but also produce a
+ * result (of value 0 and type size_t), so the expression can be used
+ * e.g. in a structure initializer (or where-ever else comma expressions
+ * aren't permitted).
+ */
+#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); }))
+#define BUILD_BUG_ON_NULL(e) ((void *)sizeof(struct { int:(-!!(e)); }))
+
+/*
+ * BUILD_BUG_ON_INVALID() permits the compiler to check the validity of the
+ * expression but avoids the generation of any code, even if that expression
+ * has side-effects.
+ */
+#define BUILD_BUG_ON_INVALID(e) ((void)(sizeof((__force long)(e))))
+
+/**
+ * BUILD_BUG_ON_MSG - break compile if a condition is true & emit supplied
+ *		      error message.
+ * @condition: the condition which the compiler should know is false.
+ *
+ * See BUILD_BUG_ON for description.
+ */
+#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
+
+/**
+ * BUILD_BUG_ON - break compile if a condition is true.
+ * @condition: the condition which the compiler should know is false.
+ *
+ * If you have some code which relies on certain constants being equal, or
+ * some other compile-time-evaluated condition, you should use BUILD_BUG_ON to
+ * detect if someone changes it.
+ *
+ * The implementation uses gcc's reluctance to create a negative array, but gcc
+ * (as of 4.4) only emits that error for obvious cases (e.g. not arguments to
+ * inline functions).  Luckily, in 4.3 they added the "error" function
+ * attribute just for this type of case.  Thus, we use a negative sized array
+ * (should always create an error on gcc versions older than 4.4) and then call
+ * an undefined function with the error attribute (should always create an
+ * error on gcc 4.3 and later).  If for some reason, neither creates a
+ * compile-time error, we'll still have a link-time error, which is harder to
+ * track down.
+ */
+#ifndef __OPTIMIZE__
+#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+#else
+#define BUILD_BUG_ON(condition) \
+	BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
+#endif
+
+/**
+ * BUILD_BUG - break compile if used.
+ *
+ * If you have some code that you expect the compiler to eliminate at
+ * build time, you should use BUILD_BUG to detect if it is
+ * unexpectedly used.
+ */
+#define BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed")
+
+#endif	/* __CHECKER__ */
+
+#endif	/* _LINUX_BUILD_BUG_H */
diff --git a/include/linux/byteorder/big_endian.h b/include/linux/byteorder/big_endian.h
new file mode 100644
index 0000000..aaf7757
--- /dev/null
+++ b/include/linux/byteorder/big_endian.h
@@ -0,0 +1,110 @@
+#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H
+#define _LINUX_BYTEORDER_BIG_ENDIAN_H
+
+#ifndef __BIG_ENDIAN
+#define __BIG_ENDIAN 4321
+#endif
+#ifndef __BIG_ENDIAN_BITFIELD
+#define __BIG_ENDIAN_BITFIELD
+#endif
+#define __BYTE_ORDER	__BIG_ENDIAN
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/byteorder/swab.h>
+
+#define __constant_htonl(x) ((__force __be32)(__u32)(x))
+#define __constant_ntohl(x) ((__force __u32)(__be32)(x))
+#define __constant_htons(x) ((__force __be16)(__u16)(x))
+#define __constant_ntohs(x) ((__force __u16)(__be16)(x))
+#define __constant_cpu_to_le64(x) ((__force __le64)___constant_swab64((x)))
+#define __constant_le64_to_cpu(x) ___constant_swab64((__force __u64)(__le64)(x))
+#define __constant_cpu_to_le32(x) ((__force __le32)___constant_swab32((x)))
+#define __constant_le32_to_cpu(x) ___constant_swab32((__force __u32)(__le32)(x))
+#define __constant_cpu_to_le16(x) ((__force __le16)___constant_swab16((x)))
+#define __constant_le16_to_cpu(x) ___constant_swab16((__force __u16)(__le16)(x))
+#define __constant_cpu_to_be64(x) ((__force __be64)(__u64)(x))
+#define __constant_be64_to_cpu(x) ((__force __u64)(__be64)(x))
+#define __constant_cpu_to_be32(x) ((__force __be32)(__u32)(x))
+#define __constant_be32_to_cpu(x) ((__force __u32)(__be32)(x))
+#define __constant_cpu_to_be16(x) ((__force __be16)(__u16)(x))
+#define __constant_be16_to_cpu(x) ((__force __u16)(__be16)(x))
+#define __cpu_to_le64(x) ((__force __le64)__swab64((x)))
+#define __le64_to_cpu(x) __swab64((__force __u64)(__le64)(x))
+#define __cpu_to_le32(x) ((__force __le32)__swab32((x)))
+#define __le32_to_cpu(x) __swab32((__force __u32)(__le32)(x))
+#define __cpu_to_le16(x) ((__force __le16)__swab16((x)))
+#define __le16_to_cpu(x) __swab16((__force __u16)(__le16)(x))
+#define __cpu_to_be64(x) ((__force __be64)(__u64)(x))
+#define __be64_to_cpu(x) ((__force __u64)(__be64)(x))
+#define __cpu_to_be32(x) ((__force __be32)(__u32)(x))
+#define __be32_to_cpu(x) ((__force __u32)(__be32)(x))
+#define __cpu_to_be16(x) ((__force __be16)(__u16)(x))
+#define __be16_to_cpu(x) ((__force __u16)(__be16)(x))
+
+static inline __le64 __cpu_to_le64p(const __u64 *p)
+{
+	return (__force __le64)__swab64p(p);
+}
+static inline __u64 __le64_to_cpup(const __le64 *p)
+{
+	return __swab64p((__u64 *)p);
+}
+static inline __le32 __cpu_to_le32p(const __u32 *p)
+{
+	return (__force __le32)__swab32p(p);
+}
+static inline __u32 __le32_to_cpup(const __le32 *p)
+{
+	return __swab32p((__u32 *)p);
+}
+static inline __le16 __cpu_to_le16p(const __u16 *p)
+{
+	return (__force __le16)__swab16p(p);
+}
+static inline __u16 __le16_to_cpup(const __le16 *p)
+{
+	return __swab16p((__u16 *)p);
+}
+static inline __be64 __cpu_to_be64p(const __u64 *p)
+{
+	return (__force __be64)*p;
+}
+static inline __u64 __be64_to_cpup(const __be64 *p)
+{
+	return (__force __u64)*p;
+}
+static inline __be32 __cpu_to_be32p(const __u32 *p)
+{
+	return (__force __be32)*p;
+}
+static inline __u32 __be32_to_cpup(const __be32 *p)
+{
+	return (__force __u32)*p;
+}
+static inline __be16 __cpu_to_be16p(const __u16 *p)
+{
+	return (__force __be16)*p;
+}
+static inline __u16 __be16_to_cpup(const __be16 *p)
+{
+	return (__force __u16)*p;
+}
+#define __cpu_to_le64s(x) __swab64s((x))
+#define __le64_to_cpus(x) __swab64s((x))
+#define __cpu_to_le32s(x) __swab32s((x))
+#define __le32_to_cpus(x) __swab32s((x))
+#define __cpu_to_le16s(x) __swab16s((x))
+#define __le16_to_cpus(x) __swab16s((x))
+#define __cpu_to_be64s(x) do { (void)(x); } while (0)
+#define __be64_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_be32s(x) do { (void)(x); } while (0)
+#define __be32_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_be16s(x) do { (void)(x); } while (0)
+#define __be16_to_cpus(x) do { (void)(x); } while (0)
+
+#ifdef __KERNEL__
+#include <linux/byteorder/generic.h>
+#endif
+
+#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
diff --git a/include/linux/byteorder/generic.h b/include/linux/byteorder/generic.h
new file mode 100644
index 0000000..8fae186
--- /dev/null
+++ b/include/linux/byteorder/generic.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+#define _LINUX_BYTEORDER_GENERIC_H
+
+/*
+ * linux/byteorder/generic.h
+ * Generic Byte-reordering support
+ *
+ * The "... p" macros, like le64_to_cpup, can be used with pointers
+ * to unaligned data, but there will be a performance penalty on
+ * some architectures.  Use get_unaligned for unaligned data.
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19970707
+ *    gathered all the good ideas from all asm-foo/byteorder.h into one file,
+ *    cleaned them up.
+ *    I hope it is compliant with non-GCC compilers.
+ *    I decided to put __BYTEORDER_HAS_U64__ in byteorder.h,
+ *    because I wasn't sure it would be ok to put it in types.h
+ *    Upgraded it to 2.1.43
+ * Francois-Rene Rideau <fare@tunes.org> 19971012
+ *    Upgraded it to 2.1.57
+ *    to please Linus T., replaced huge #ifdef's between little/big endian
+ *    by nestedly #include'd files.
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    Made it to 2.1.71; now a facelift:
+ *    Put files under include/linux/byteorder/
+ *    Split swab from generic support.
+ *
+ * TODO:
+ *   = Regular kernel maintainers could also replace all these manual
+ *    byteswap macros that remain, disseminated among drivers,
+ *    after some grep or the sources...
+ *   = Linus might want to rename all these macros and files to fit his taste,
+ *    to fit his personal naming scheme.
+ *   = it seems that a few drivers would also appreciate
+ *    nybble swapping support...
+ *   = every architecture could add their byteswap macro in asm/byteorder.h
+ *    see how some architectures already do (i386, alpha, ppc, etc)
+ *   = cpu_to_beXX and beXX_to_cpu might some day need to be well
+ *    distinguished throughout the kernel. This is not the case currently,
+ *    since little endian, big endian, and pdp endian machines needn't it.
+ *    But this might be the case for, say, a port of Linux to 20/21 bit
+ *    architectures (and F21 Linux addict around?).
+ */
+
+/*
+ * The following macros are to be defined by <asm/byteorder.h>:
+ *
+ * Conversion of long and short int between network and host format
+ *	ntohl(__u32 x)
+ *	ntohs(__u16 x)
+ *	htonl(__u32 x)
+ *	htons(__u16 x)
+ * It seems that some programs (which? where? or perhaps a standard? POSIX?)
+ * might like the above to be functions, not macros (why?).
+ * if that's true, then detect them, and take measures.
+ * Anyway, the measure is: define only ___ntohl as a macro instead,
+ * and in a separate file, have
+ * unsigned long inline ntohl(x){return ___ntohl(x);}
+ *
+ * The same for constant arguments
+ *	__constant_ntohl(__u32 x)
+ *	__constant_ntohs(__u16 x)
+ *	__constant_htonl(__u32 x)
+ *	__constant_htons(__u16 x)
+ *
+ * Conversion of XX-bit integers (16- 32- or 64-)
+ * between native CPU format and little/big endian format
+ * 64-bit stuff only defined for proper architectures
+ *	cpu_to_[bl]eXX(__uXX x)
+ *	[bl]eXX_to_cpu(__uXX x)
+ *
+ * The same, but takes a pointer to the value to convert
+ *	cpu_to_[bl]eXXp(__uXX x)
+ *	[bl]eXX_to_cpup(__uXX x)
+ *
+ * The same, but change in situ
+ *	cpu_to_[bl]eXXs(__uXX x)
+ *	[bl]eXX_to_cpus(__uXX x)
+ *
+ * See asm-foo/byteorder.h for examples of how to provide
+ * architecture-optimized versions
+ *
+ */
+
+#define cpu_to_le64 __cpu_to_le64
+#define le64_to_cpu __le64_to_cpu
+#define cpu_to_le32 __cpu_to_le32
+#define le32_to_cpu __le32_to_cpu
+#define cpu_to_le16 __cpu_to_le16
+#define le16_to_cpu __le16_to_cpu
+#define cpu_to_be64 __cpu_to_be64
+#define be64_to_cpu __be64_to_cpu
+#define cpu_to_be32 __cpu_to_be32
+#define be32_to_cpu __be32_to_cpu
+#define cpu_to_be16 __cpu_to_be16
+#define be16_to_cpu __be16_to_cpu
+#define cpu_to_le64p __cpu_to_le64p
+#define le64_to_cpup __le64_to_cpup
+#define cpu_to_le32p __cpu_to_le32p
+#define le32_to_cpup __le32_to_cpup
+#define cpu_to_le16p __cpu_to_le16p
+#define le16_to_cpup __le16_to_cpup
+#define cpu_to_be64p __cpu_to_be64p
+#define be64_to_cpup __be64_to_cpup
+#define cpu_to_be32p __cpu_to_be32p
+#define be32_to_cpup __be32_to_cpup
+#define cpu_to_be16p __cpu_to_be16p
+#define be16_to_cpup __be16_to_cpup
+#define cpu_to_le64s __cpu_to_le64s
+#define le64_to_cpus __le64_to_cpus
+#define cpu_to_le32s __cpu_to_le32s
+#define le32_to_cpus __le32_to_cpus
+#define cpu_to_le16s __cpu_to_le16s
+#define le16_to_cpus __le16_to_cpus
+#define cpu_to_be64s __cpu_to_be64s
+#define be64_to_cpus __be64_to_cpus
+#define cpu_to_be32s __cpu_to_be32s
+#define be32_to_cpus __be32_to_cpus
+#define cpu_to_be16s __cpu_to_be16s
+#define be16_to_cpus __be16_to_cpus
+
+/*
+ * They have to be macros in order to do the constant folding
+ * correctly - if the argument passed into a inline function
+ * it is no longer constant according to gcc..
+ */
+
+#undef ntohl
+#undef ntohs
+#undef htonl
+#undef htons
+
+#define ___htonl(x) __cpu_to_be32(x)
+#define ___htons(x) __cpu_to_be16(x)
+#define ___ntohl(x) __be32_to_cpu(x)
+#define ___ntohs(x) __be16_to_cpu(x)
+
+#define htonl(x) ___htonl(x)
+#define ntohl(x) ___ntohl(x)
+#define htons(x) ___htons(x)
+#define ntohs(x) ___ntohs(x)
+
+static inline void le16_add_cpu(__le16 *var, u16 val)
+{
+	*var = cpu_to_le16(le16_to_cpu(*var) + val);
+}
+
+static inline void le32_add_cpu(__le32 *var, u32 val)
+{
+	*var = cpu_to_le32(le32_to_cpu(*var) + val);
+}
+
+static inline void le64_add_cpu(__le64 *var, u64 val)
+{
+	*var = cpu_to_le64(le64_to_cpu(*var) + val);
+}
+
+/* XXX: this stuff can be optimized */
+static inline void le32_to_cpu_array(u32 *buf, unsigned int words)
+{
+	while (words--) {
+		__le32_to_cpus(buf);
+		buf++;
+	}
+}
+
+static inline void cpu_to_le32_array(u32 *buf, unsigned int words)
+{
+	while (words--) {
+		__cpu_to_le32s(buf);
+		buf++;
+	}
+}
+
+static inline void be16_add_cpu(__be16 *var, u16 val)
+{
+	*var = cpu_to_be16(be16_to_cpu(*var) + val);
+}
+
+static inline void be32_add_cpu(__be32 *var, u32 val)
+{
+	*var = cpu_to_be32(be32_to_cpu(*var) + val);
+}
+
+static inline void be64_add_cpu(__be64 *var, u64 val)
+{
+	*var = cpu_to_be64(be64_to_cpu(*var) + val);
+}
+
+static inline void cpu_to_be32_array(__be32 *dst, const u32 *src, size_t len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		dst[i] = cpu_to_be32(src[i]);
+}
+
+static inline void be32_to_cpu_array(u32 *dst, const __be32 *src, size_t len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		dst[i] = be32_to_cpu(src[i]);
+}
+
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
diff --git a/include/linux/byteorder/little_endian.h b/include/linux/byteorder/little_endian.h
new file mode 100644
index 0000000..a4cb3bf
--- /dev/null
+++ b/include/linux/byteorder/little_endian.h
@@ -0,0 +1,110 @@
+#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+
+#ifndef __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN 1234
+#endif
+#ifndef __LITTLE_ENDIAN_BITFIELD
+#define __LITTLE_ENDIAN_BITFIELD
+#endif
+#define	__BYTE_ORDER	__LITTLE_ENDIAN
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/byteorder/swab.h>
+
+#define __constant_htonl(x) ((__force __be32)___constant_swab32((x)))
+#define __constant_ntohl(x) ___constant_swab32((__force __be32)(x))
+#define __constant_htons(x) ((__force __be16)___constant_swab16((x)))
+#define __constant_ntohs(x) ___constant_swab16((__force __be16)(x))
+#define __constant_cpu_to_le64(x) ((__force __le64)(__u64)(x))
+#define __constant_le64_to_cpu(x) ((__force __u64)(__le64)(x))
+#define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x))
+#define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x))
+#define __constant_cpu_to_le16(x) ((__force __le16)(__u16)(x))
+#define __constant_le16_to_cpu(x) ((__force __u16)(__le16)(x))
+#define __constant_cpu_to_be64(x) ((__force __be64)___constant_swab64((x)))
+#define __constant_be64_to_cpu(x) ___constant_swab64((__force __u64)(__be64)(x))
+#define __constant_cpu_to_be32(x) ((__force __be32)___constant_swab32((x)))
+#define __constant_be32_to_cpu(x) ___constant_swab32((__force __u32)(__be32)(x))
+#define __constant_cpu_to_be16(x) ((__force __be16)___constant_swab16((x)))
+#define __constant_be16_to_cpu(x) ___constant_swab16((__force __u16)(__be16)(x))
+#define __cpu_to_le64(x) ((__force __le64)(__u64)(x))
+#define __le64_to_cpu(x) ((__force __u64)(__le64)(x))
+#define __cpu_to_le32(x) ((__force __le32)(__u32)(x))
+#define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
+#define __cpu_to_le16(x) ((__force __le16)(__u16)(x))
+#define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
+#define __cpu_to_be64(x) ((__force __be64)__swab64((x)))
+#define __be64_to_cpu(x) __swab64((__force __u64)(__be64)(x))
+#define __cpu_to_be32(x) ((__force __be32)__swab32((x)))
+#define __be32_to_cpu(x) __swab32((__force __u32)(__be32)(x))
+#define __cpu_to_be16(x) ((__force __be16)__swab16((x)))
+#define __be16_to_cpu(x) __swab16((__force __u16)(__be16)(x))
+
+static inline __le64 __cpu_to_le64p(const __u64 *p)
+{
+	return (__force __le64)*p;
+}
+static inline __u64 __le64_to_cpup(const __le64 *p)
+{
+	return (__force __u64)*p;
+}
+static inline __le32 __cpu_to_le32p(const __u32 *p)
+{
+	return (__force __le32)*p;
+}
+static inline __u32 __le32_to_cpup(const __le32 *p)
+{
+	return (__force __u32)*p;
+}
+static inline __le16 __cpu_to_le16p(const __u16 *p)
+{
+	return (__force __le16)*p;
+}
+static inline __u16 __le16_to_cpup(const __le16 *p)
+{
+	return (__force __u16)*p;
+}
+static inline __be64 __cpu_to_be64p(const __u64 *p)
+{
+	return (__force __be64)__swab64p(p);
+}
+static inline __u64 __be64_to_cpup(const __be64 *p)
+{
+	return __swab64p((__u64 *)p);
+}
+static inline __be32 __cpu_to_be32p(const __u32 *p)
+{
+	return (__force __be32)__swab32p(p);
+}
+static inline __u32 __be32_to_cpup(const __be32 *p)
+{
+	return __swab32p((__u32 *)p);
+}
+static inline __be16 __cpu_to_be16p(const __u16 *p)
+{
+	return (__force __be16)__swab16p(p);
+}
+static inline __u16 __be16_to_cpup(const __be16 *p)
+{
+	return __swab16p((__u16 *)p);
+}
+#define __cpu_to_le64s(x) do { (void)(x); } while (0)
+#define __le64_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_le32s(x) do { (void)(x); } while (0)
+#define __le32_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_le16s(x) do { (void)(x); } while (0)
+#define __le16_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_be64s(x) __swab64s((x))
+#define __be64_to_cpus(x) __swab64s((x))
+#define __cpu_to_be32s(x) __swab32s((x))
+#define __be32_to_cpus(x) __swab32s((x))
+#define __cpu_to_be16s(x) __swab16s((x))
+#define __be16_to_cpus(x) __swab16s((x))
+
+#ifdef __KERNEL__
+#include <linux/byteorder/generic.h>
+#endif
+
+#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
diff --git a/include/linux/byteorder/swab.h b/include/linux/byteorder/swab.h
new file mode 100644
index 0000000..4334fa7
--- /dev/null
+++ b/include/linux/byteorder/swab.h
@@ -0,0 +1,156 @@
+#ifndef _LINUX_BYTEORDER_SWAB_H
+#define _LINUX_BYTEORDER_SWAB_H
+
+/*
+ * linux/byteorder/swab.h
+ * Byte-swapping, independently from CPU endianness
+ *	swabXX[ps]?(foo)
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    separated swab functions from cpu_to_XX,
+ *    to clean up support for bizarre-endian architectures.
+ *
+ * See asm-i386/byteorder.h and suches for examples of how to provide
+ * architecture-dependent optimized versions
+ *
+ */
+
+/* casts are necessary for constants, because we never know how for sure
+ * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.
+ */
+#define ___swab16(x) \
+	((__u16)( \
+		(((__u16)(x) & (__u16)0x00ffU) << 8) | \
+		(((__u16)(x) & (__u16)0xff00U) >> 8) ))
+#define ___swab32(x) \
+	((__u32)( \
+		(((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
+		(((__u32)(x) & (__u32)0x0000ff00UL) <<  8) | \
+		(((__u32)(x) & (__u32)0x00ff0000UL) >>  8) | \
+		(((__u32)(x) & (__u32)0xff000000UL) >> 24) ))
+#define ___swab64(x) \
+	((__u64)( \
+		(__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \
+		(__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \
+		(__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \
+		(__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) <<  8) | \
+		(__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >>  8) | \
+		(__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \
+		(__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \
+		(__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) ))
+
+/*
+ * provide defaults when no architecture-specific optimization is detected
+ */
+#ifndef __arch__swab16
+#  define __arch__swab16(x) ___swab16(x)
+#endif
+#ifndef __arch__swab32
+#  define __arch__swab32(x) ___swab32(x)
+#endif
+#ifndef __arch__swab64
+#  define __arch__swab64(x) ___swab64(x)
+#endif
+
+#ifndef __arch__swab16p
+#  define __arch__swab16p(x) __swab16(*(x))
+#endif
+#ifndef __arch__swab32p
+#  define __arch__swab32p(x) __swab32(*(x))
+#endif
+#ifndef __arch__swab64p
+#  define __arch__swab64p(x) __swab64(*(x))
+#endif
+
+#ifndef __arch__swab16s
+#  define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0)
+#endif
+#ifndef __arch__swab32s
+#  define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0)
+#endif
+#ifndef __arch__swab64s
+#  define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0)
+#endif
+
+
+/*
+ * Allow constant folding
+ */
+#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__)
+#  define __swab16(x) \
+(__builtin_constant_p((__u16)(x)) ? \
+ ___swab16((x)) : \
+ __fswab16((x)))
+#  define __swab32(x) \
+(__builtin_constant_p((__u32)(x)) ? \
+ ___swab32((x)) : \
+ __fswab32((x)))
+#  define __swab64(x) \
+(__builtin_constant_p((__u64)(x)) ? \
+ ___swab64((x)) : \
+ __fswab64((x)))
+#else
+#  define __swab16(x) __fswab16(x)
+#  define __swab32(x) __fswab32(x)
+#  define __swab64(x) __fswab64(x)
+#endif /* OPTIMIZE */
+
+
+static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x)
+{
+	return __arch__swab16(x);
+}
+static __inline__ __u16 __swab16p(const __u16 *x)
+{
+	return __arch__swab16p(x);
+}
+static __inline__ void __swab16s(__u16 *addr)
+{
+	__arch__swab16s(addr);
+}
+
+static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x)
+{
+	return __arch__swab32(x);
+}
+static __inline__ __u32 __swab32p(const __u32 *x)
+{
+	return __arch__swab32p(x);
+}
+static __inline__ void __swab32s(__u32 *addr)
+{
+	__arch__swab32s(addr);
+}
+
+static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x)
+{
+#  ifdef __SWAB_64_THRU_32__
+	__u32 h = x >> 32;
+	__u32 l = x & ((1ULL<<32)-1);
+	return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h)));
+#  else
+	return __arch__swab64(x);
+#  endif
+}
+static __inline__ __u64 __swab64p(const __u64 *x)
+{
+	return __arch__swab64p(x);
+}
+static __inline__ void __swab64s(__u64 *addr)
+{
+	__arch__swab64s(addr);
+}
+
+#if defined(__KERNEL__)
+#define swab16 __swab16
+#define swab32 __swab32
+#define swab64 __swab64
+#define swab16p __swab16p
+#define swab32p __swab32p
+#define swab64p __swab64p
+#define swab16s __swab16s
+#define swab32s __swab32s
+#define swab64s __swab64s
+#endif
+
+#endif /* _LINUX_BYTEORDER_SWAB_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
new file mode 100644
index 0000000..02ff1a3
--- /dev/null
+++ b/include/linux/clk-provider.h
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
+ */
+#ifndef __LINUX_CLK_PROVIDER_H
+#define __LINUX_CLK_PROVIDER_H
+#include <clk-uclass.h>
+
+static inline void clk_dm(ulong id, struct clk *clk)
+{
+	if (!IS_ERR(clk))
+		clk->id = id;
+}
+
+/*
+ * flags used across common struct clk.  these flags should only affect the
+ * top-level framework.  custom flags for dealing with hardware specifics
+ * belong in struct clk_foo
+ *
+ * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
+ */
+#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
+#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
+#define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
+#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
+				/* unused */
+#define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a to_clk_foo() */
+#define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
+#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
+#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
+#define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */
+#define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */
+#define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
+/* parents need enable during gate/ungate, set rate and re-parent */
+#define CLK_OPS_PARENT_ENABLE	BIT(12)
+/* duty cycle call may be forwarded to the parent clock */
+#define CLK_DUTY_CYCLE_PARENT	BIT(13)
+
+#define CLK_MUX_INDEX_ONE		BIT(0)
+#define CLK_MUX_INDEX_BIT		BIT(1)
+#define CLK_MUX_HIWORD_MASK		BIT(2)
+#define CLK_MUX_READ_ONLY		BIT(3) /* mux can't be changed */
+#define CLK_MUX_ROUND_CLOSEST		BIT(4)
+
+struct clk_mux {
+	struct clk	clk;
+	void __iomem	*reg;
+	u32		*table;
+	u32		mask;
+	u8		shift;
+	u8		flags;
+
+	/*
+	 * Fields from struct clk_init_data - this struct has been
+	 * omitted to avoid too deep level of CCF for bootloader
+	 */
+	const char	* const *parent_names;
+	u8		num_parents;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+	u32             io_mux_val;
+#endif
+
+};
+
+#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
+extern const struct clk_ops clk_mux_ops;
+u8 clk_mux_get_parent(struct clk *clk);
+
+struct clk_gate {
+	struct clk	clk;
+	void __iomem	*reg;
+	u8		bit_idx;
+	u8		flags;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+	u32		io_gate_val;
+#endif
+};
+
+#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
+
+#define CLK_GATE_SET_TO_DISABLE		BIT(0)
+#define CLK_GATE_HIWORD_MASK		BIT(1)
+
+extern const struct clk_ops clk_gate_ops;
+struct clk *clk_register_gate(struct device *dev, const char *name,
+			      const char *parent_name, unsigned long flags,
+			      void __iomem *reg, u8 bit_idx,
+			      u8 clk_gate_flags, spinlock_t *lock);
+
+struct clk_div_table {
+	unsigned int	val;
+	unsigned int	div;
+};
+
+struct clk_divider {
+	struct clk	clk;
+	void __iomem	*reg;
+	u8		shift;
+	u8		width;
+	u8		flags;
+	const struct clk_div_table	*table;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+	u32             io_divider_val;
+#endif
+};
+
+#define clk_div_mask(width)	((1 << (width)) - 1)
+#define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
+
+#define CLK_DIVIDER_ONE_BASED		BIT(0)
+#define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
+#define CLK_DIVIDER_ALLOW_ZERO		BIT(2)
+#define CLK_DIVIDER_HIWORD_MASK		BIT(3)
+#define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
+#define CLK_DIVIDER_READ_ONLY		BIT(5)
+#define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
+extern const struct clk_ops clk_divider_ops;
+unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
+				  unsigned int val,
+				  const struct clk_div_table *table,
+				  unsigned long flags, unsigned long width);
+
+struct clk_fixed_factor {
+	struct clk	clk;
+	unsigned int	mult;
+	unsigned int	div;
+};
+
+#define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
+					       clk)
+
+struct clk_fixed_rate {
+	struct clk clk;
+	unsigned long fixed_rate;
+};
+
+#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate *)dev_get_platdata(dev))
+
+struct clk_composite {
+	struct clk	clk;
+	struct clk_ops	ops;
+
+	struct clk	*mux;
+	struct clk	*rate;
+	struct clk	*gate;
+
+	const struct clk_ops	*mux_ops;
+	const struct clk_ops	*rate_ops;
+	const struct clk_ops	*gate_ops;
+};
+
+#define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+		const char * const *parent_names, int num_parents,
+		struct clk *mux_clk, const struct clk_ops *mux_ops,
+		struct clk *rate_clk, const struct clk_ops *rate_ops,
+		struct clk *gate_clk, const struct clk_ops *gate_ops,
+		unsigned long flags);
+
+int clk_register(struct clk *clk, const char *drv_name, const char *name,
+		 const char *parent_name);
+
+struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		unsigned int mult, unsigned int div);
+
+struct clk *clk_register_divider(struct device *dev, const char *name,
+		const char *parent_name, unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_divider_flags);
+
+struct clk *clk_register_mux(struct device *dev, const char *name,
+		const char * const *parent_names, u8 num_parents,
+		unsigned long flags,
+		void __iomem *reg, u8 shift, u8 width,
+		u8 clk_mux_flags);
+
+const char *clk_hw_get_name(const struct clk *hw);
+ulong clk_generic_get_rate(struct clk *clk);
+
+static inline struct clk *dev_get_clk_ptr(struct udevice *dev)
+{
+	return (struct clk *)dev_get_uclass_priv(dev);
+}
+#endif /* __LINUX_CLK_PROVIDER_H */
diff --git a/include/linux/clk/analogbits-wrpll-cln28hpc.h b/include/linux/clk/analogbits-wrpll-cln28hpc.h
new file mode 100644
index 0000000..0327909
--- /dev/null
+++ b/include/linux/clk/analogbits-wrpll-cln28hpc.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ */
+
+#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
+#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
+
+#include <linux/types.h>
+
+/* DIVQ_VALUES: number of valid DIVQ values */
+#define DIVQ_VALUES				6
+
+/*
+ * Bit definitions for struct wrpll_cfg.flags
+ *
+ * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
+ *	programmed to enter bypass
+ * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
+ * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
+ *	feedback mode
+ * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
+ *	feedback mode (not yet supported by this driver)
+ */
+#define WRPLL_FLAGS_BYPASS_SHIFT		0
+#define WRPLL_FLAGS_BYPASS_MASK		BIT(WRPLL_FLAGS_BYPASS_SHIFT)
+#define WRPLL_FLAGS_RESET_SHIFT		1
+#define WRPLL_FLAGS_RESET_MASK		BIT(WRPLL_FLAGS_RESET_SHIFT)
+#define WRPLL_FLAGS_INT_FEEDBACK_SHIFT	2
+#define WRPLL_FLAGS_INT_FEEDBACK_MASK	BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT)
+#define WRPLL_FLAGS_EXT_FEEDBACK_SHIFT	3
+#define WRPLL_FLAGS_EXT_FEEDBACK_MASK	BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT)
+
+/**
+ * struct wrpll_cfg - WRPLL configuration values
+ * @divr: reference divider value (6 bits), as presented to the PLL signals
+ * @divf: feedback divider value (9 bits), as presented to the PLL signals
+ * @divq: output divider value (3 bits), as presented to the PLL signals
+ * @flags: PLL configuration flags.  See above for more information
+ * @range: PLL loop filter range.  See below for more information
+ * @output_rate_cache: cached output rates, swept across DIVQ
+ * @parent_rate: PLL refclk rate for which values are valid
+ * @max_r: maximum possible R divider value, given @parent_rate
+ * @init_r: initial R divider value to start the search from
+ *
+ * @divr, @divq, @divq, @range represent what the PLL expects to see
+ * on its input signals.  Thus @divr and @divf are the actual divisors
+ * minus one.  @divq is a power-of-two divider; for example, 1 =
+ * divide-by-2 and 6 = divide-by-64.  0 is an invalid @divq value.
+ *
+ * When initially passing a struct wrpll_cfg record, the
+ * record should be zero-initialized with the exception of the @flags
+ * field.  The only flag bits that need to be set are either
+ * WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK.
+ */
+struct wrpll_cfg {
+	u8 divr;
+	u8 divq;
+	u8 range;
+	u8 flags;
+	u16 divf;
+/* private: */
+	u32 output_rate_cache[DIVQ_VALUES];
+	unsigned long parent_rate;
+	u8 max_r;
+	u8 init_r;
+};
+
+int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
+			     unsigned long parent_rate);
+
+unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c);
+
+unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c,
+				     unsigned long parent_rate);
+
+#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */
diff --git a/include/linux/compat.h b/include/linux/compat.h
new file mode 100644
index 0000000..d0f51ba
--- /dev/null
+++ b/include/linux/compat.h
@@ -0,0 +1,378 @@
+#ifndef _LINUX_COMPAT_H_
+#define _LINUX_COMPAT_H_
+
+#include <malloc.h>
+#include <linux/types.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+
+struct unused {};
+typedef struct unused unused_t;
+
+struct p_current{
+       int pid;
+};
+
+extern struct p_current *current;
+
+/* avoid conflict with <dm/device.h> */
+#ifdef dev_dbg
+#undef dev_dbg
+#endif
+#ifdef dev_vdbg
+#undef dev_vdbg
+#endif
+#ifdef dev_info
+#undef dev_info
+#endif
+#ifdef dev_err
+#undef dev_err
+#endif
+#ifdef dev_warn
+#undef dev_warn
+#endif
+
+#define dev_dbg(dev, fmt, args...)		\
+	debug(fmt, ##args)
+#define dev_vdbg(dev, fmt, args...)		\
+	debug(fmt, ##args)
+#define dev_info(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define dev_err(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define dev_warn(dev, fmt, args...)		\
+	printf(fmt, ##args)
+
+#define netdev_emerg(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define netdev_alert(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define netdev_crit(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define netdev_err(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define netdev_warn(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define netdev_notice(dev, fmt, args...)	\
+	printf(fmt, ##args)
+#define netdev_info(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define netdev_dbg(dev, fmt, args...)		\
+	debug(fmt, ##args)
+#define netdev_vdbg(dev, fmt, args...)		\
+	debug(fmt, ##args)
+
+#define GFP_ATOMIC ((gfp_t) 0)
+#define GFP_KERNEL ((gfp_t) 0)
+#define GFP_NOFS ((gfp_t) 0)
+#define GFP_USER ((gfp_t) 0)
+#define __GFP_NOWARN ((gfp_t) 0)
+#define __GFP_ZERO	((__force gfp_t)0x8000u)	/* Return zeroed page on success */
+
+void *kmalloc(size_t size, int flags);
+
+static inline void *kzalloc(size_t size, gfp_t flags)
+{
+	return kmalloc(size, flags | __GFP_ZERO);
+}
+
+static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags)
+{
+	if (size != 0 && n > SIZE_MAX / size)
+		return NULL;
+	return kmalloc(n * size, flags | __GFP_ZERO);
+}
+
+static inline void *kcalloc(size_t n, size_t size, gfp_t flags)
+{
+	return kmalloc_array(n, size, flags | __GFP_ZERO);
+}
+
+#define vmalloc(size)	kmalloc(size, 0)
+#define __vmalloc(size, flags, pgsz)	kmalloc(size, flags)
+static inline void *vzalloc(unsigned long size)
+{
+	return kzalloc(size, 0);
+}
+static inline void kfree(const void *block)
+{
+	free((void *)block);
+}
+static inline void vfree(const void *addr)
+{
+	free((void *)addr);
+}
+
+struct kmem_cache { int sz; };
+
+struct kmem_cache *get_mem(int element_sz);
+#define kmem_cache_create(a, sz, c, d, e)	get_mem(sz)
+void *kmem_cache_alloc(struct kmem_cache *obj, int flag);
+static inline void kmem_cache_free(struct kmem_cache *cachep, void *obj)
+{
+	free(obj);
+}
+static inline void kmem_cache_destroy(struct kmem_cache *cachep)
+{
+	free(cachep);
+}
+
+#define DECLARE_WAITQUEUE(...)	do { } while (0)
+#define add_wait_queue(...)	do { } while (0)
+#define remove_wait_queue(...)	do { } while (0)
+
+#define KERNEL_VERSION(a,b,c)	(((a) << 16) + ((b) << 8) + (c))
+
+#define PAGE_SIZE	4096
+
+/* drivers/char/random.c */
+#define get_random_bytes(...)
+
+/* include/linux/leds.h */
+struct led_trigger {};
+
+#define DEFINE_LED_TRIGGER(x)		static struct led_trigger *x;
+enum led_brightness {
+	LED_OFF		= 0,
+	LED_HALF	= 127,
+	LED_FULL	= 255,
+};
+
+static inline void led_trigger_register_simple(const char *name,
+					struct led_trigger **trigger) {}
+static inline void led_trigger_unregister_simple(struct led_trigger *trigger) {}
+static inline void led_trigger_event(struct led_trigger *trigger,
+					enum led_brightness event) {}
+
+/* uapi/linux/limits.h */
+#define XATTR_LIST_MAX 65536	/* size of extended attribute namelist (64k) */
+
+/**
+ * The type used for indexing onto a disc or disc partition.
+ *
+ * Linux always considers sectors to be 512 bytes long independently
+ * of the devices real block size.
+ *
+ * blkcnt_t is the type of the inode's block count.
+ */
+#ifdef CONFIG_LBDAF
+typedef u64 sector_t;
+typedef u64 blkcnt_t;
+#else
+typedef unsigned long sector_t;
+typedef unsigned long blkcnt_t;
+#endif
+
+/* module */
+#define THIS_MODULE		0
+#define try_module_get(...)	1
+#define module_put(...)		do { } while (0)
+#define module_init(...)
+#define module_exit(...)
+#define EXPORT_SYMBOL(...)
+#define EXPORT_SYMBOL_GPL(...)
+#define module_param(...)
+#define module_param_call(...)
+#define MODULE_PARM_DESC(...)
+#define MODULE_VERSION(...)
+#define MODULE_DESCRIPTION(...)
+#define MODULE_AUTHOR(...)
+#define MODULE_LICENSE(...)
+#define MODULE_ALIAS(...)
+#define __module_get(...)
+
+/* character device */
+#define MKDEV(...)			0
+#define MAJOR(dev)			0
+#define MINOR(dev)			0
+
+#define alloc_chrdev_region(...)	0
+#define unregister_chrdev_region(...)
+
+#define class_create(...)		__builtin_return_address(0)
+#define class_create_file(...)		0
+#define class_register(...)		0
+#define class_unregister(...)
+#define class_remove_file(...)
+#define class_destroy(...)
+#define misc_register(...)		0
+#define misc_deregister(...)
+
+#define blocking_notifier_call_chain(...) 0
+
+#define __initdata
+#define late_initcall(...)
+
+#define dev_set_name(...)		do { } while (0)
+#define device_register(...)		0
+#define device_unregister(...)
+#define volume_sysfs_init(...)		0
+#define volume_sysfs_close(...)		do { } while (0)
+
+#define init_waitqueue_head(...)	do { } while (0)
+#define wait_event_interruptible(...)	0
+#define wake_up_interruptible(...)	do { } while (0)
+#define dump_stack(...)			do { } while (0)
+
+#define task_pid_nr(x)			0
+#define set_freezable(...)		do { } while (0)
+#define try_to_freeze(...)		0
+#define set_current_state(...)		do { } while (0)
+#define kthread_should_stop(...)	0
+#define schedule()			do { } while (0)
+
+#define setup_timer(timer, func, data) do {} while (0)
+#define del_timer_sync(timer) do {} while (0)
+#define schedule_work(work) do {} while (0)
+#define INIT_WORK(work, fun) do {} while (0)
+
+struct work_struct {};
+
+unsigned long copy_from_user(void *dest, const void *src,
+			     unsigned long count);
+
+typedef unused_t spinlock_t;
+typedef int	wait_queue_head_t;
+
+#define spin_lock_init(lock) do {} while (0)
+#define spin_lock(lock) do {} while (0)
+#define spin_unlock(lock) do {} while (0)
+#define spin_lock_irqsave(lock, flags) do { debug("%lu\n", flags); } while (0)
+#define spin_unlock_irqrestore(lock, flags) do { flags = 0; } while (0)
+
+#define DEFINE_MUTEX(...)
+#define mutex_init(...)
+#define mutex_lock(...)
+#define mutex_unlock(...)
+
+#define init_rwsem(...)			do { } while (0)
+#define down_read(...)			do { } while (0)
+#define down_write(...)			do { } while (0)
+#define down_write_trylock(...)		1
+#define up_read(...)			do { } while (0)
+#define up_write(...)			do { } while (0)
+
+#define cond_resched()			do { } while (0)
+#define yield()				do { } while (0)
+
+#define __init
+#define __exit
+#define __devinit
+#define __devinitdata
+#define __devinitconst
+
+#define kthread_create(...)	__builtin_return_address(0)
+#define kthread_stop(...)	do { } while (0)
+#define wake_up_process(...)	do { } while (0)
+
+struct rw_semaphore { int i; };
+#define down_write(...)			do { } while (0)
+#define up_write(...)			do { } while (0)
+#define down_read(...)			do { } while (0)
+#define up_read(...)			do { } while (0)
+struct device {
+	struct device		*parent;
+	struct class		*class;
+	dev_t			devt;	/* dev_t, creates the sysfs "dev" */
+	void	(*release)(struct device *dev);
+	/* This is used from drivers/usb/musb-new subsystem only */
+	void		*driver_data;	/* data private to the driver */
+	void            *device_data;   /* data private to the device */
+};
+struct mutex { int i; };
+struct kernel_param { int i; };
+
+struct cdev {
+	int owner;
+	dev_t dev;
+};
+#define cdev_init(...)		do { } while (0)
+#define cdev_add(...)		0
+#define cdev_del(...)		do { } while (0)
+
+#define prandom_u32(...)	0
+
+typedef struct {
+	uid_t val;
+} kuid_t;
+
+typedef struct {
+	gid_t val;
+} kgid_t;
+
+/* from include/linux/types.h */
+
+/**
+ * struct callback_head - callback structure for use with RCU and task_work
+ * @next: next update requests in a list
+ * @func: actual update function to call after the grace period.
+ */
+struct callback_head {
+	struct callback_head *next;
+	void (*func)(struct callback_head *head);
+};
+#define rcu_head callback_head
+enum writeback_sync_modes {
+	WB_SYNC_NONE,	/* Don't wait on anything */
+	WB_SYNC_ALL,	/* Wait on every mapping */
+};
+
+/* from include/linux/writeback.h */
+/*
+ * A control structure which tells the writeback code what to do.  These are
+ * always on the stack, and hence need no locking.  They are always initialised
+ * in a manner such that unspecified fields are set to zero.
+ */
+struct writeback_control {
+	long nr_to_write;		/* Write this many pages, and decrement
+					   this for each page written */
+	long pages_skipped;		/* Pages which were not written */
+
+	/*
+	 * For a_ops->writepages(): if start or end are non-zero then this is
+	 * a hint that the filesystem need only write out the pages inside that
+	 * byterange.  The byte at `end' is included in the writeout request.
+	 */
+	loff_t range_start;
+	loff_t range_end;
+
+	enum writeback_sync_modes sync_mode;
+
+	unsigned for_kupdate:1;		/* A kupdate writeback */
+	unsigned for_background:1;	/* A background writeback */
+	unsigned tagged_writepages:1;	/* tag-and-write to avoid livelock */
+	unsigned for_reclaim:1;		/* Invoked from the page allocator */
+	unsigned range_cyclic:1;	/* range_start is cyclic */
+	unsigned for_sync:1;		/* sync(2) WB_SYNC_ALL writeback */
+};
+
+void *kmemdup(const void *src, size_t len, gfp_t gfp);
+
+typedef int irqreturn_t;
+
+struct timer_list {};
+struct notifier_block {};
+
+typedef unsigned long dmaaddr_t;
+
+#define pm_runtime_get_sync(dev) do {} while (0)
+#define pm_runtime_put(dev) do {} while (0)
+#define pm_runtime_put_sync(dev) do {} while (0)
+#define pm_runtime_use_autosuspend(dev) do {} while (0)
+#define pm_runtime_set_autosuspend_delay(dev, delay) do {} while (0)
+#define pm_runtime_enable(dev) do {} while (0)
+
+#define IRQ_NONE 0
+#define IRQ_HANDLED 1
+#define IRQ_WAKE_THREAD 2
+
+#define dev_set_drvdata(dev, data) do {} while (0)
+
+#define enable_irq(...)
+#define disable_irq(...)
+#define disable_irq_wake(irq) do {} while (0)
+#define enable_irq_wake(irq) -EINVAL
+#define free_irq(irq, data) do {} while (0)
+#define request_irq(nr, f, flags, nm, data) 0
+
+#endif
diff --git a/include/linux/compiler-clang.h b/include/linux/compiler-clang.h
new file mode 100644
index 0000000..d1e49d5
--- /dev/null
+++ b/include/linux/compiler-clang.h
@@ -0,0 +1,12 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-clang.h> directly, include <linux/compiler.h> instead."
+#endif
+
+/* Some compiler specific definitions are overwritten here
+ * for Clang compiler
+ */
+
+#ifdef uninitialized_var
+#undef uninitialized_var
+#define uninitialized_var(x) x = *(&(x))
+#endif
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
new file mode 100644
index 0000000..8d9e079
--- /dev/null
+++ b/include/linux/compiler-gcc.h
@@ -0,0 +1,285 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
+#endif
+
+/*
+ * Common definitions for all gcc versions go here.
+ */
+#define GCC_VERSION (__GNUC__ * 10000		\
+		     + __GNUC_MINOR__ * 100	\
+		     + __GNUC_PATCHLEVEL__)
+
+/* Optimization barrier */
+
+/* The "volatile" is due to gcc bugs */
+#define barrier() \
+	__asm__ __volatile__("": : :"memory")
+/*
+ * This version is i.e. to prevent dead stores elimination on @ptr
+ * where gcc and llvm may behave differently when otherwise using
+ * normal barrier(): while gcc behavior gets along with a normal
+ * barrier(), llvm needs an explicit input variable to be assumed
+ * clobbered. The issue is as follows: while the inline asm might
+ * access any memory it wants, the compiler could have fit all of
+ * @ptr into memory registers instead, and since @ptr never escaped
+ * from that, it proofed that the inline asm wasn't touching any of
+ * it. This version works well with both compilers, i.e. we're telling
+ * the compiler that the inline asm absolutely may see the contents
+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
+ */
+#define barrier_data(ptr) \
+	__asm__ __volatile__("": :"r"(ptr) :"memory")
+
+/*
+ * This macro obfuscates arithmetic on a variable address so that gcc
+ * shouldn't recognize the original var, and make assumptions about it.
+ *
+ * This is needed because the C standard makes it undefined to do
+ * pointer arithmetic on "objects" outside their boundaries and the
+ * gcc optimizers assume this is the case. In particular they
+ * assume such arithmetic does not wrap.
+ *
+ * A miscompilation has been observed because of this on PPC.
+ * To work around it we hide the relationship of the pointer and the object
+ * using this macro.
+ *
+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
+ * the inline assembly constraint from =g to =r, in this particular
+ * case either is valid.
+ */
+#define RELOC_HIDE(ptr, off)						\
+({									\
+	unsigned long __ptr;						\
+	__asm__ ("" : "=r"(__ptr) : "0"(ptr));				\
+	(typeof(ptr)) (__ptr + (off));					\
+})
+
+/* Make the optimizer believe the variable can be manipulated arbitrarily. */
+#define OPTIMIZER_HIDE_VAR(var)						\
+	__asm__ ("" : "=r" (var) : "0" (var))
+
+#ifdef __CHECKER__
+#define __must_be_array(a)	0
+#else
+/* &a[0] degrades to a pointer: a different type from an array */
+#define __must_be_array(a)	BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
+#endif
+
+/*
+ * Force always-inline if the user requests it so via the .config,
+ * or if gcc is too old:
+ */
+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) ||		\
+    !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
+#define inline		inline		__attribute__((always_inline)) notrace
+#define __inline__	__inline__	__attribute__((always_inline)) notrace
+#define __inline	__inline	__attribute__((always_inline)) notrace
+#else
+/* A lot of inline functions can cause havoc with function tracing */
+#define inline		inline		notrace
+#define __inline__	__inline__	notrace
+#define __inline	__inline	notrace
+#endif
+
+#define __always_inline	inline __attribute__((always_inline))
+#define  noinline	__attribute__((noinline))
+
+#define __deprecated	__attribute__((deprecated))
+#define __packed	__attribute__((packed))
+#define __weak		__attribute__((weak))
+#define __alias(symbol)	__attribute__((alias(#symbol)))
+
+/*
+ * it doesn't make sense on ARM (currently the only user of __naked)
+ * to trace naked functions because then mcount is called without
+ * stack and frame pointer being set up and there is no chance to
+ * restore the lr register to the value before mcount was called.
+ *
+ * The asm() bodies of naked functions often depend on standard calling
+ * conventions, therefore they must be noinline and noclone.
+ *
+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.
+ * See GCC PR44290.
+ */
+#define __naked		__attribute__((naked)) noinline __noclone notrace
+
+#define __noreturn	__attribute__((noreturn))
+
+/*
+ * From the GCC manual:
+ *
+ * Many functions have no effects except the return value and their
+ * return value depends only on the parameters and/or global
+ * variables.  Such a function can be subject to common subexpression
+ * elimination and loop optimization just as an arithmetic operator
+ * would be.
+ * [...]
+ */
+#define __pure			__attribute__((pure))
+#define __aligned(x)		__attribute__((aligned(x)))
+#define __printf(a, b)		__attribute__((format(printf, a, b)))
+#define __scanf(a, b)		__attribute__((format(scanf, a, b)))
+#define __attribute_const__	__attribute__((__const__))
+#define __maybe_unused		__attribute__((unused))
+#define __always_unused		__attribute__((unused))
+
+/* gcc version specific checks */
+
+#if GCC_VERSION < 30200
+# error Sorry, your compiler is too old - please upgrade it.
+#endif
+
+#if GCC_VERSION < 30300
+# define __used			__attribute__((__unused__))
+#else
+# define __used			__attribute__((__used__))
+#endif
+
+#ifdef CONFIG_GCOV_KERNEL
+# if GCC_VERSION < 30400
+#   error "GCOV profiling support for gcc versions below 3.4 not included"
+# endif /* __GNUC_MINOR__ */
+#endif /* CONFIG_GCOV_KERNEL */
+
+#if GCC_VERSION >= 30400
+#define __must_check		__attribute__((warn_unused_result))
+#endif
+
+#if GCC_VERSION >= 40000
+
+/* GCC 4.1.[01] miscompiles __weak */
+#ifdef __KERNEL__
+# if GCC_VERSION >= 40100 &&  GCC_VERSION <= 40101
+#  error Your version of gcc miscompiles the __weak directive
+# endif
+#endif
+
+#define __used			__attribute__((__used__))
+#define __compiler_offsetof(a, b)					\
+	__builtin_offsetof(a, b)
+
+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
+#endif
+
+#if GCC_VERSION >= 40300
+/* Mark functions as cold. gcc will assume any path leading to a call
+ * to them will be unlikely.  This means a lot of manual unlikely()s
+ * are unnecessary now for any paths leading to the usual suspects
+ * like BUG(), printk(), panic() etc. [but let's keep them for now for
+ * older compilers]
+ *
+ * Early snapshots of gcc 4.3 don't support this and we can't detect this
+ * in the preprocessor, but we can live with this because they're unreleased.
+ * Maketime probing would be overkill here.
+ *
+ * gcc also has a __attribute__((__hot__)) to move hot functions into
+ * a special section, but I don't see any sense in this right now in
+ * the kernel context
+ */
+#define __cold			__attribute__((__cold__))
+
+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
+
+#ifndef __CHECKER__
+# define __compiletime_warning(message) __attribute__((warning(message)))
+# define __compiletime_error(message) __attribute__((error(message)))
+#endif /* __CHECKER__ */
+#endif /* GCC_VERSION >= 40300 */
+
+#if GCC_VERSION >= 40500
+/*
+ * Mark a position in code as unreachable.  This can be used to
+ * suppress control flow warnings after asm blocks that transfer
+ * control elsewhere.
+ *
+ * Early snapshots of gcc 4.5 don't support this and we can't detect
+ * this in the preprocessor, but we can live with this because they're
+ * unreleased.  Really, we need to have autoconf for the kernel.
+ */
+#define unreachable() __builtin_unreachable()
+
+/* Mark a function definition as prohibited from being cloned. */
+#define __noclone	__attribute__((__noclone__))
+
+#endif /* GCC_VERSION >= 40500 */
+
+#if GCC_VERSION >= 40600
+/*
+ * When used with Link Time Optimization, gcc can optimize away C functions or
+ * variables which are referenced only from assembly code.  __visible tells the
+ * optimizer that something else uses this function or variable, thus preventing
+ * this.
+ */
+#define __visible	__attribute__((externally_visible))
+#endif
+
+
+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)
+/*
+ * __assume_aligned(n, k): Tell the optimizer that the returned
+ * pointer can be assumed to be k modulo n. The second argument is
+ * optional (default 0), so we use a variadic macro to make the
+ * shorthand.
+ *
+ * Beware: Do not apply this to functions which may return
+ * ERR_PTRs. Also, it is probably unwise to apply it to functions
+ * returning extra information in the low bits (but in that case the
+ * compiler should see some alignment anyway, when the return value is
+ * massaged by 'flags = ptr & 3; ptr &= ~3;').
+ */
+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
+#endif
+
+/*
+ * GCC 'asm goto' miscompiles certain code sequences:
+ *
+ *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
+ *
+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
+ *
+ * (asm goto is automatically volatile - the naming reflects this.)
+ */
+#define asm_volatile_goto(x...)	do { asm goto(x); asm (""); } while (0)
+
+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
+#if GCC_VERSION >= 40400
+#define __HAVE_BUILTIN_BSWAP32__
+#define __HAVE_BUILTIN_BSWAP64__
+#endif
+#if GCC_VERSION >= 40800 || (defined(__powerpc__) && GCC_VERSION >= 40600)
+#define __HAVE_BUILTIN_BSWAP16__
+#endif
+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
+
+#if GCC_VERSION >= 50000
+#define KASAN_ABI_VERSION 4
+#elif GCC_VERSION >= 40902
+#define KASAN_ABI_VERSION 3
+#endif
+
+#if GCC_VERSION >= 40902
+/*
+ * Tell the compiler that address safety instrumentation (KASAN)
+ * should not be applied to that function.
+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
+ */
+#define __no_sanitize_address __attribute__((no_sanitize_address))
+#endif
+
+#endif	/* gcc version >= 40000 specific checks */
+
+#if !defined(__noclone)
+#define __noclone	/* not needed */
+#endif
+
+#if !defined(__no_sanitize_address)
+#define __no_sanitize_address
+#endif
+
+/*
+ * A trick to suppress uninitialized variable warning without generating any
+ * code
+ */
+#define uninitialized_var(x) x = x
diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h
new file mode 100644
index 0000000..d4c7113
--- /dev/null
+++ b/include/linux/compiler-intel.h
@@ -0,0 +1,45 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-intel.h> directly, include <linux/compiler.h> instead."
+#endif
+
+#ifdef __ECC
+
+/* Some compiler specific definitions are overwritten here
+ * for Intel ECC compiler
+ */
+
+#include <asm/intrinsics.h>
+
+/* Intel ECC compiler doesn't support gcc specific asm stmts.
+ * It uses intrinsics to do the equivalent things.
+ */
+#undef barrier
+#undef barrier_data
+#undef RELOC_HIDE
+#undef OPTIMIZER_HIDE_VAR
+
+#define barrier() __memory_barrier()
+#define barrier_data(ptr) barrier()
+
+#define RELOC_HIDE(ptr, off)					\
+  ({ unsigned long __ptr;					\
+     __ptr = (unsigned long) (ptr);				\
+    (typeof(ptr)) (__ptr + (off)); })
+
+/* This should act as an optimization barrier on var.
+ * Given that this compiler does not have inline assembly, a compiler barrier
+ * is the best we can do.
+ */
+#define OPTIMIZER_HIDE_VAR(var) barrier()
+
+/* Intel ECC compiler doesn't support __builtin_types_compatible_p() */
+#define __must_be_array(a) 0
+
+#endif
+
+#ifndef __HAVE_BUILTIN_BSWAP16__
+/* icc has this, but it's called _bswap16 */
+#define __HAVE_BUILTIN_BSWAP16__
+#define __builtin_bswap16 _bswap16
+#endif
+
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
new file mode 100644
index 0000000..0ea6c8f
--- /dev/null
+++ b/include/linux/compiler.h
@@ -0,0 +1,559 @@
+#ifndef __LINUX_COMPILER_H
+#define __LINUX_COMPILER_H
+
+#ifndef __ASSEMBLY__
+
+#ifdef __CHECKER__
+# define __user		__attribute__((noderef, address_space(1)))
+# define __kernel	__attribute__((address_space(0)))
+# define __safe		__attribute__((safe))
+# define __force	__attribute__((force))
+# define __nocast	__attribute__((nocast))
+# define __iomem	__attribute__((noderef, address_space(2)))
+# define __must_hold(x)	__attribute__((context(x,1,1)))
+# define __acquires(x)	__attribute__((context(x,0,1)))
+# define __releases(x)	__attribute__((context(x,1,0)))
+# define __acquire(x)	__context__(x,1)
+# define __release(x)	__context__(x,-1)
+# define __cond_lock(x,c)	((c) ? ({ __acquire(x); 1; }) : 0)
+# define __percpu	__attribute__((noderef, address_space(3)))
+# define __pmem		__attribute__((noderef, address_space(5)))
+#ifdef CONFIG_SPARSE_RCU_POINTER
+# define __rcu		__attribute__((noderef, address_space(4)))
+#else
+# define __rcu
+#endif
+extern void __chk_user_ptr(const volatile void __user *);
+extern void __chk_io_ptr(const volatile void __iomem *);
+#else
+# define __user
+# define __kernel
+# define __safe
+# define __force
+# define __nocast
+# define __iomem
+# define __chk_user_ptr(x) (void)0
+# define __chk_io_ptr(x) (void)0
+# define __builtin_warning(x, y...) (1)
+# define __must_hold(x)
+# define __acquires(x)
+# define __releases(x)
+# define __acquire(x) (void)0
+# define __release(x) (void)0
+# define __cond_lock(x,c) (c)
+# define __percpu
+# define __rcu
+# define __pmem
+#endif
+
+/* Indirect macros required for expanded argument pasting, eg. __LINE__. */
+#define ___PASTE(a,b) a##b
+#define __PASTE(a,b) ___PASTE(a,b)
+
+#ifdef __KERNEL__
+
+#ifdef __GNUC__
+#include <linux/compiler-gcc.h>
+#endif
+
+#if defined(CC_USING_HOTPATCH) && !defined(__CHECKER__)
+#define notrace __attribute__((hotpatch(0,0)))
+#else
+#define notrace __attribute__((no_instrument_function))
+#endif
+
+/* Intel compiler defines __GNUC__. So we will overwrite implementations
+ * coming from above header files here
+ */
+#ifdef __INTEL_COMPILER
+# include <linux/compiler-intel.h>
+#endif
+
+/* Clang compiler defines __GNUC__. So we will overwrite implementations
+ * coming from above header files here
+ */
+#ifdef __clang__
+#include <linux/compiler-clang.h>
+#endif
+
+/*
+ * Generic compiler-dependent macros required for kernel
+ * build go below this comment. Actual compiler/compiler version
+ * specific implementations come from the above header files
+ */
+
+struct ftrace_branch_data {
+	const char *func;
+	const char *file;
+	unsigned line;
+	union {
+		struct {
+			unsigned long correct;
+			unsigned long incorrect;
+		};
+		struct {
+			unsigned long miss;
+			unsigned long hit;
+		};
+		unsigned long miss_hit[2];
+	};
+};
+
+/*
+ * Note: DISABLE_BRANCH_PROFILING can be used by special lowlevel code
+ * to disable branch tracing on a per file basis.
+ */
+#if defined(CONFIG_TRACE_BRANCH_PROFILING) \
+    && !defined(DISABLE_BRANCH_PROFILING) && !defined(__CHECKER__)
+void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+
+#define likely_notrace(x)	__builtin_expect(!!(x), 1)
+#define unlikely_notrace(x)	__builtin_expect(!!(x), 0)
+
+#define __branch_check__(x, expect) ({					\
+			int ______r;					\
+			static struct ftrace_branch_data		\
+				__attribute__((__aligned__(4)))		\
+				__attribute__((section("_ftrace_annotated_branch"))) \
+				______f = {				\
+				.func = __func__,			\
+				.file = __FILE__,			\
+				.line = __LINE__,			\
+			};						\
+			______r = likely_notrace(x);			\
+			ftrace_likely_update(&______f, ______r, expect); \
+			______r;					\
+		})
+
+/*
+ * Using __builtin_constant_p(x) to ignore cases where the return
+ * value is always the same.  This idea is taken from a similar patch
+ * written by Daniel Walker.
+ */
+# ifndef likely
+#  define likely(x)	(__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 1))
+# endif
+# ifndef unlikely
+#  define unlikely(x)	(__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 0))
+# endif
+
+#ifdef CONFIG_PROFILE_ALL_BRANCHES
+/*
+ * "Define 'is'", Bill Clinton
+ * "Define 'if'", Steven Rostedt
+ */
+#define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) )
+#define __trace_if(cond) \
+	if (__builtin_constant_p(!!(cond)) ? !!(cond) :			\
+	({								\
+		int ______r;						\
+		static struct ftrace_branch_data			\
+			__attribute__((__aligned__(4)))			\
+			__attribute__((section("_ftrace_branch")))	\
+			______f = {					\
+				.func = __func__,			\
+				.file = __FILE__,			\
+				.line = __LINE__,			\
+			};						\
+		______r = !!(cond);					\
+		______f.miss_hit[______r]++;					\
+		______r;						\
+	}))
+#endif /* CONFIG_PROFILE_ALL_BRANCHES */
+
+#else
+# define likely(x)	__builtin_expect(!!(x), 1)
+# define unlikely(x)	__builtin_expect(!!(x), 0)
+#endif
+
+/* Optimization barrier */
+#ifndef barrier
+# define barrier() __memory_barrier()
+#endif
+
+#ifndef barrier_data
+# define barrier_data(ptr) barrier()
+#endif
+
+/* Unreachable code */
+#ifndef unreachable
+# define unreachable() do { } while (1)
+#endif
+
+#ifndef RELOC_HIDE
+# define RELOC_HIDE(ptr, off)					\
+  ({ unsigned long __ptr;					\
+     __ptr = (unsigned long) (ptr);				\
+    (typeof(ptr)) (__ptr + (off)); })
+#endif
+
+#ifndef OPTIMIZER_HIDE_VAR
+#define OPTIMIZER_HIDE_VAR(var) barrier()
+#endif
+
+/* Not-quite-unique ID. */
+#ifndef __UNIQUE_ID
+# define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __LINE__)
+#endif
+
+#include <linux/types.h>
+
+#define __READ_ONCE_SIZE						\
+({									\
+	switch (size) {							\
+	case 1: *(__u8 *)res = *(volatile __u8 *)p; break;		\
+	case 2: *(__u16 *)res = *(volatile __u16 *)p; break;		\
+	case 4: *(__u32 *)res = *(volatile __u32 *)p; break;		\
+	case 8: *(__u64 *)res = *(volatile __u64 *)p; break;		\
+	default:							\
+		barrier();						\
+		__builtin_memcpy((void *)res, (const void *)p, size);	\
+		barrier();						\
+	}								\
+})
+
+static __always_inline
+void __read_once_size(const volatile void *p, void *res, int size)
+{
+	__READ_ONCE_SIZE;
+}
+
+#ifdef CONFIG_KASAN
+/*
+ * This function is not 'inline' because __no_sanitize_address confilcts
+ * with inlining. Attempt to inline it may cause a build failure.
+ * 	https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
+ * '__maybe_unused' allows us to avoid defined-but-not-used warnings.
+ */
+static __no_sanitize_address __maybe_unused
+void __read_once_size_nocheck(const volatile void *p, void *res, int size)
+{
+	__READ_ONCE_SIZE;
+}
+#else
+static __always_inline
+void __read_once_size_nocheck(const volatile void *p, void *res, int size)
+{
+	__READ_ONCE_SIZE;
+}
+#endif
+
+static __always_inline void __write_once_size(volatile void *p, void *res, int size)
+{
+	switch (size) {
+	case 1: *(volatile __u8 *)p = *(__u8 *)res; break;
+	case 2: *(volatile __u16 *)p = *(__u16 *)res; break;
+	case 4: *(volatile __u32 *)p = *(__u32 *)res; break;
+	case 8: *(volatile __u64 *)p = *(__u64 *)res; break;
+	default:
+		barrier();
+		__builtin_memcpy((void *)p, (const void *)res, size);
+		barrier();
+	}
+}
+
+/*
+ * Prevent the compiler from merging or refetching reads or writes. The
+ * compiler is also forbidden from reordering successive instances of
+ * READ_ONCE, WRITE_ONCE and ACCESS_ONCE (see below), but only when the
+ * compiler is aware of some particular ordering.  One way to make the
+ * compiler aware of ordering is to put the two invocations of READ_ONCE,
+ * WRITE_ONCE or ACCESS_ONCE() in different C statements.
+ *
+ * In contrast to ACCESS_ONCE these two macros will also work on aggregate
+ * data types like structs or unions. If the size of the accessed data
+ * type exceeds the word size of the machine (e.g., 32 bits or 64 bits)
+ * READ_ONCE() and WRITE_ONCE()  will fall back to memcpy and print a
+ * compile-time warning.
+ *
+ * Their two major use cases are: (1) Mediating communication between
+ * process-level code and irq/NMI handlers, all running on the same CPU,
+ * and (2) Ensuring that the compiler does not  fold, spindle, or otherwise
+ * mutilate accesses that either do not require ordering or that interact
+ * with an explicit memory barrier or atomic instruction that provides the
+ * required ordering.
+ */
+
+#define __READ_ONCE(x, check)						\
+({									\
+	union { typeof(x) __val; char __c[1]; } __u;			\
+	if (check)							\
+		__read_once_size(&(x), __u.__c, sizeof(x));		\
+	else								\
+		__read_once_size_nocheck(&(x), __u.__c, sizeof(x));	\
+	__u.__val;							\
+})
+#define READ_ONCE(x) __READ_ONCE(x, 1)
+
+/*
+ * Use READ_ONCE_NOCHECK() instead of READ_ONCE() if you need
+ * to hide memory access from KASAN.
+ */
+#define READ_ONCE_NOCHECK(x) __READ_ONCE(x, 0)
+
+#define WRITE_ONCE(x, val) \
+({							\
+	union { typeof(x) __val; char __c[1]; } __u =	\
+		{ .__val = (__force typeof(x)) (val) }; \
+	__write_once_size(&(x), __u.__c, sizeof(x));	\
+	__u.__val;					\
+})
+
+/**
+ * smp_cond_acquire() - Spin wait for cond with ACQUIRE ordering
+ * @cond: boolean expression to wait for
+ *
+ * Equivalent to using smp_load_acquire() on the condition variable but employs
+ * the control dependency of the wait to reduce the barrier on many platforms.
+ *
+ * The control dependency provides a LOAD->STORE order, the additional RMB
+ * provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order,
+ * aka. ACQUIRE.
+ */
+#define smp_cond_acquire(cond)	do {		\
+	while (!(cond))				\
+		cpu_relax();			\
+	smp_rmb(); /* ctrl + rmb := acquire */	\
+} while (0)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+/*
+ * Allow us to mark functions as 'deprecated' and have gcc emit a nice
+ * warning for each use, in hopes of speeding the functions removal.
+ * Usage is:
+ * 		int __deprecated foo(void)
+ */
+#ifndef __deprecated
+# define __deprecated		/* unimplemented */
+#endif
+
+#ifdef MODULE
+#define __deprecated_for_modules __deprecated
+#else
+#define __deprecated_for_modules
+#endif
+
+#ifndef __must_check
+#define __must_check
+#endif
+
+#ifndef CONFIG_ENABLE_MUST_CHECK
+#undef __must_check
+#define __must_check
+#endif
+#ifndef CONFIG_ENABLE_WARN_DEPRECATED
+#undef __deprecated
+#undef __deprecated_for_modules
+#define __deprecated
+#define __deprecated_for_modules
+#endif
+
+/*
+ * Allow us to avoid 'defined but not used' warnings on functions and data,
+ * as well as force them to be emitted to the assembly file.
+ *
+ * As of gcc 3.4, static functions that are not marked with attribute((used))
+ * may be elided from the assembly file.  As of gcc 3.4, static data not so
+ * marked will not be elided, but this may change in a future gcc version.
+ *
+ * NOTE: Because distributions shipped with a backported unit-at-a-time
+ * compiler in gcc 3.3, we must define __used to be __attribute__((used))
+ * for gcc >=3.3 instead of 3.4.
+ *
+ * In prior versions of gcc, such functions and data would be emitted, but
+ * would be warned about except with attribute((unused)).
+ *
+ * Mark functions that are referenced only in inline assembly as __used so
+ * the code is emitted even though it appears to be unreferenced.
+ */
+#ifndef __used
+# define __used			/* unimplemented */
+#endif
+
+#ifndef __maybe_unused
+# define __maybe_unused		/* unimplemented */
+#endif
+
+#ifndef __always_unused
+# define __always_unused	/* unimplemented */
+#endif
+
+#ifndef noinline
+#define noinline
+#endif
+
+/*
+ * Rather then using noinline to prevent stack consumption, use
+ * noinline_for_stack instead.  For documentation reasons.
+ */
+#define noinline_for_stack noinline
+
+#ifndef __always_inline
+#define __always_inline inline
+#endif
+
+#endif /* __KERNEL__ */
+
+/*
+ * From the GCC manual:
+ *
+ * Many functions do not examine any values except their arguments,
+ * and have no effects except the return value.  Basically this is
+ * just slightly more strict class than the `pure' attribute above,
+ * since function is not allowed to read global memory.
+ *
+ * Note that a function that has pointer arguments and examines the
+ * data pointed to must _not_ be declared `const'.  Likewise, a
+ * function that calls a non-`const' function usually must not be
+ * `const'.  It does not make sense for a `const' function to return
+ * `void'.
+ */
+#ifndef __attribute_const__
+# define __attribute_const__	/* unimplemented */
+#endif
+
+/*
+ * Tell gcc if a function is cold. The compiler will assume any path
+ * directly leading to the call is unlikely.
+ */
+
+#ifndef __cold
+#define __cold
+#endif
+
+/* Simple shorthand for a section definition */
+#ifndef __section
+# define __section(S) __attribute__ ((__section__(#S)))
+#endif
+
+#ifndef __visible
+#define __visible
+#endif
+
+/*
+ * Assume alignment of return value.
+ */
+#ifndef __assume_aligned
+#define __assume_aligned(a, ...)
+#endif
+
+
+/* Are two types/vars the same type (ignoring qualifiers)? */
+#ifndef __same_type
+# define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
+#endif
+
+/* Is this type a native word size -- useful for atomic operations */
+#ifndef __native_word
+# define __native_word(t) (sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long))
+#endif
+
+/* Compile time object size, -1 for unknown */
+#ifndef __compiletime_object_size
+# define __compiletime_object_size(obj) -1
+#endif
+#ifndef __compiletime_warning
+# define __compiletime_warning(message)
+#endif
+#ifndef __compiletime_error
+# define __compiletime_error(message)
+/*
+ * Sparse complains of variable sized arrays due to the temporary variable in
+ * __compiletime_assert. Unfortunately we can't just expand it out to make
+ * sparse see a constant array size without breaking compiletime_assert on old
+ * versions of GCC (e.g. 4.2.4), so hide the array from sparse altogether.
+ */
+# ifndef __CHECKER__
+#  define __compiletime_error_fallback(condition) \
+	do { ((void)sizeof(char[1 - 2 * condition])); } while (0)
+# endif
+#endif
+#ifndef __compiletime_error_fallback
+# define __compiletime_error_fallback(condition) do { } while (0)
+#endif
+
+#ifdef __OPTIMIZE__
+# define __compiletime_assert(condition, msg, prefix, suffix)		\
+	do {								\
+		bool __cond = !(condition);				\
+		extern void prefix ## suffix(void) __compiletime_error(msg); \
+		if (__cond)						\
+			prefix ## suffix();				\
+		__compiletime_error_fallback(__cond);			\
+	} while (0)
+#else
+# define __compiletime_assert(condition, msg, prefix, suffix) do { } while (0)
+#endif
+
+#define _compiletime_assert(condition, msg, prefix, suffix) \
+	__compiletime_assert(condition, msg, prefix, suffix)
+
+/**
+ * compiletime_assert - break build and emit msg if condition is false
+ * @condition: a compile-time constant condition to check
+ * @msg:       a message to emit if condition is false
+ *
+ * In tradition of POSIX assert, this macro will break the build if the
+ * supplied condition is *false*, emitting the supplied error message if the
+ * compiler has support to do so.
+ */
+#define compiletime_assert(condition, msg) \
+	_compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)
+
+#define compiletime_assert_atomic_type(t)				\
+	compiletime_assert(__native_word(t),				\
+		"Need native word sized stores/loads for atomicity.")
+
+/*
+ * Prevent the compiler from merging or refetching accesses.  The compiler
+ * is also forbidden from reordering successive instances of ACCESS_ONCE(),
+ * but only when the compiler is aware of some particular ordering.  One way
+ * to make the compiler aware of ordering is to put the two invocations of
+ * ACCESS_ONCE() in different C statements.
+ *
+ * ACCESS_ONCE will only work on scalar types. For union types, ACCESS_ONCE
+ * on a union member will work as long as the size of the member matches the
+ * size of the union and the size is smaller than word size.
+ *
+ * The major use cases of ACCESS_ONCE used to be (1) Mediating communication
+ * between process-level code and irq/NMI handlers, all running on the same CPU,
+ * and (2) Ensuring that the compiler does not  fold, spindle, or otherwise
+ * mutilate accesses that either do not require ordering or that interact
+ * with an explicit memory barrier or atomic instruction that provides the
+ * required ordering.
+ *
+ * If possible use READ_ONCE()/WRITE_ONCE() instead.
+ */
+#define __ACCESS_ONCE(x) ({ \
+	 __maybe_unused typeof(x) __var = (__force typeof(x)) 0; \
+	(volatile typeof(x) *)&(x); })
+#define ACCESS_ONCE(x) (*__ACCESS_ONCE(x))
+
+/**
+ * lockless_dereference() - safely load a pointer for later dereference
+ * @p: The pointer to load
+ *
+ * Similar to rcu_dereference(), but for situations where the pointed-to
+ * object's lifetime is managed by something other than RCU.  That
+ * "something other" might be reference counting or simple immortality.
+ */
+#define lockless_dereference(p) \
+({ \
+	typeof(p) _________p1 = READ_ONCE(p); \
+	smp_read_barrier_depends(); /* Dependency order vs. p above. */ \
+	(_________p1); \
+})
+
+/* Ignore/forbid kprobes attach on very low level functions marked by this attribute: */
+#ifdef CONFIG_KPROBES
+# define __kprobes	__attribute__((__section__(".kprobes.text")))
+# define nokprobe_inline	__always_inline
+#else
+# define __kprobes
+# define nokprobe_inline	inline
+#endif
+#endif /* __LINUX_COMPILER_H */
diff --git a/include/linux/completion.h b/include/linux/completion.h
new file mode 100644
index 0000000..9835826
--- /dev/null
+++ b/include/linux/completion.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_COMPLETION_H
+#define __LINUX_COMPLETION_H
+
+/*
+ * (C) Copyright 2001 Linus Torvalds
+ *
+ * Atomic wait-for-completion handler data structures.
+ * See kernel/sched/completion.c for details.
+ */
+#ifndef __UBOOT__
+#include <linux/wait.h>
+#endif /* __UBOOT__ */
+
+/*
+ * struct completion - structure used to maintain state for a "completion"
+ *
+ * This is the opaque structure used to maintain the state for a "completion".
+ * Completions currently use a FIFO to queue threads that have to wait for
+ * the "completion" event.
+ *
+ * See also:  complete(), wait_for_completion() (and friends _timeout,
+ * _interruptible, _interruptible_timeout, and _killable), init_completion(),
+ * reinit_completion(), and macros DECLARE_COMPLETION(),
+ * DECLARE_COMPLETION_ONSTACK().
+ */
+struct completion {
+	unsigned int done;
+#ifndef __UBOOT__
+	wait_queue_head_t wait;
+#endif /* __UBOOT__ */
+};
+
+#define init_completion_map(x, m) __init_completion(x)
+#define init_completion(x) __init_completion(x)
+static inline void complete_acquire(struct completion *x) {}
+static inline void complete_release(struct completion *x) {}
+
+#define COMPLETION_INITIALIZER(work) \
+	{ 0, __WAIT_QUEUE_HEAD_INITIALIZER((work).wait) }
+
+#define COMPLETION_INITIALIZER_ONSTACK_MAP(work, map) \
+	(*({ init_completion_map(&(work), &(map)); &(work); }))
+
+#define COMPLETION_INITIALIZER_ONSTACK(work) \
+	(*({ init_completion(&work); &work; }))
+
+/**
+ * DECLARE_COMPLETION - declare and initialize a completion structure
+ * @work:  identifier for the completion structure
+ *
+ * This macro declares and initializes a completion structure. Generally used
+ * for static declarations. You should use the _ONSTACK variant for automatic
+ * variables.
+ */
+#define DECLARE_COMPLETION(work) \
+	struct completion work = COMPLETION_INITIALIZER(work)
+
+/*
+ * Lockdep needs to run a non-constant initializer for on-stack
+ * completions - so we use the _ONSTACK() variant for those that
+ * are on the kernel stack:
+ */
+/**
+ * DECLARE_COMPLETION_ONSTACK - declare and initialize a completion structure
+ * @work:  identifier for the completion structure
+ *
+ * This macro declares and initializes a completion structure on the kernel
+ * stack.
+ */
+#ifdef CONFIG_LOCKDEP
+# define DECLARE_COMPLETION_ONSTACK(work) \
+	struct completion work = COMPLETION_INITIALIZER_ONSTACK(work)
+# define DECLARE_COMPLETION_ONSTACK_MAP(work, map) \
+	struct completion work = COMPLETION_INITIALIZER_ONSTACK_MAP(work, map)
+#else
+# define DECLARE_COMPLETION_ONSTACK(work) DECLARE_COMPLETION(work)
+# define DECLARE_COMPLETION_ONSTACK_MAP(work, map) DECLARE_COMPLETION(work)
+#endif
+
+/**
+ * init_completion - Initialize a dynamically allocated completion
+ * @x:  pointer to completion structure that is to be initialized
+ *
+ * This inline function will initialize a dynamically created completion
+ * structure.
+ */
+static inline void __init_completion(struct completion *x)
+{
+	x->done = 0;
+#ifndef __UBOOT__
+	init_waitqueue_head(&x->wait);
+#endif /* __UBOOT__ */
+}
+
+/**
+ * reinit_completion - reinitialize a completion structure
+ * @x:  pointer to completion structure that is to be reinitialized
+ *
+ * This inline function should be used to reinitialize a completion structure so it can
+ * be reused. This is especially important after complete_all() is used.
+ */
+static inline void reinit_completion(struct completion *x)
+{
+	x->done = 0;
+}
+
+#ifndef __UBOOT__
+extern void wait_for_completion(struct completion *);
+extern void wait_for_completion_io(struct completion *);
+extern int wait_for_completion_interruptible(struct completion *x);
+extern int wait_for_completion_killable(struct completion *x);
+extern unsigned long wait_for_completion_timeout(struct completion *x,
+						   unsigned long timeout);
+extern unsigned long wait_for_completion_io_timeout(struct completion *x,
+						    unsigned long timeout);
+extern long wait_for_completion_interruptible_timeout(
+	struct completion *x, unsigned long timeout);
+extern long wait_for_completion_killable_timeout(
+	struct completion *x, unsigned long timeout);
+extern bool try_wait_for_completion(struct completion *x);
+extern bool completion_done(struct completion *x);
+
+extern void complete(struct completion *);
+extern void complete_all(struct completion *);
+
+#else /* __UBOOT __ */
+
+#define wait_for_completion(x)		do {} while (0)
+#define wait_for_completion_io(x)	do {} while (0)
+
+inline int wait_for_completion_interruptible(struct completion *x)
+{
+	return 1;
+}
+inline int wait_for_completion_killable(struct completion *x)
+{
+	return 1;
+}
+inline unsigned long wait_for_completion_timeout(struct completion *x,
+						 unsigned long timeout)
+{
+	return 1;
+}
+inline unsigned long wait_for_completion_io_timeout(struct completion *x,
+						    unsigned long timeout)
+{
+	return 1;
+}
+inline long wait_for_completion_interruptible_timeout(struct completion *x,
+						      unsigned long timeout)
+{
+	return 1;
+}
+inline long wait_for_completion_killable_timeout(struct completion *x,
+						 unsigned long timeout)
+{
+	return 1;
+}
+inline bool try_wait_for_completion(struct completion *x)
+{
+	return 1;
+}
+inline bool completion_done(struct completion *x)
+{
+	return 1;
+}
+
+#define complete(x)		do {} while (0)
+#define complete_all(x)		do {} while (0)
+#endif /* __UBOOT__ */
+
+#endif
diff --git a/include/linux/const.h b/include/linux/const.h
new file mode 100644
index 0000000..379c889
--- /dev/null
+++ b/include/linux/const.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+#ifndef _LINUX_CONST_H
+#define _LINUX_CONST_H
+
+/* const.h: Macros for dealing with constants.  */
+
+/* Some constant macros are used in both assembler and
+ * C code.  Therefore we cannot annotate them always with
+ * 'UL' and other type specifiers unilaterally.  We
+ * use the following macros to deal with this.
+ *
+ * Similarly, _AT() will cast an expression with a type in C, but
+ * leave it unchanged in asm.
+ */
+
+#ifdef __ASSEMBLY__
+#define _AC(X,Y)	X
+#define _AT(T,X)	X
+#else
+#define __AC(X,Y)	(X##Y)
+#define _AC(X,Y)	__AC(X,Y)
+#define _AT(T,X)	((T)(X))
+#endif
+
+#define _UL(x)		(_AC(x, UL))
+#define _ULL(x)		(_AC(x, ULL))
+
+#define _BITUL(x)	(_UL(1) << (x))
+#define _BITULL(x)	(_ULL(1) << (x))
+
+#define UL(x)		(_UL(x))
+#define ULL(x)		(_ULL(x))
+
+#endif /* _LINUX_CONST_H */
diff --git a/include/linux/crc32.h b/include/linux/crc32.h
new file mode 100644
index 0000000..ac4aed1
--- /dev/null
+++ b/include/linux/crc32.h
@@ -0,0 +1,27 @@
+/*
+ * crc32.h
+ * See linux/lib/crc32.c for license and changes
+ */
+#ifndef _LINUX_CRC32_H
+#define _LINUX_CRC32_H
+
+#include <linux/types.h>
+/* #include <linux/bitrev.h> */
+
+extern u32  crc32_le(u32 crc, unsigned char const *p, size_t len);
+/* extern u32  crc32_be(u32 crc, unsigned char const *p, size_t len); */
+
+#define crc32(seed, data, length)  crc32_le(seed, (unsigned char const *)data, length)
+
+/*
+ * Helpers for hash table generation of ethernet nics:
+ *
+ * Ethernet sends the least significant bit of a byte first, thus crc32_le
+ * is used. The output of crc32_le is bit reversed [most significant bit
+ * is in bit nr 0], thus it must be reversed before use. Except for
+ * nics that bit swap the result internally...
+ */
+/* #define ether_crc(length, data)    bitrev32(crc32_le(~0, data, length)) */
+/* #define ether_crc_le(length, data) crc32_le(~0, data, length) */
+
+#endif /* _LINUX_CRC32_H */
diff --git a/include/linux/crc7.h b/include/linux/crc7.h
new file mode 100644
index 0000000..1786e77
--- /dev/null
+++ b/include/linux/crc7.h
@@ -0,0 +1,14 @@
+#ifndef _LINUX_CRC7_H
+#define _LINUX_CRC7_H
+#include <linux/types.h>
+
+extern const u8 crc7_syndrome_table[256];
+
+static inline u8 crc7_byte(u8 crc, u8 data)
+{
+	return crc7_syndrome_table[(crc << 1) ^ data];
+}
+
+extern u8 crc7(u8 crc, const u8 *buffer, size_t len);
+
+#endif
diff --git a/include/linux/crc8.h b/include/linux/crc8.h
new file mode 100644
index 0000000..0ab5b9a
--- /dev/null
+++ b/include/linux/crc8.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ */
+
+
+#ifndef __linux_crc8_h
+#define __linux_crc8_h
+
+/**
+ * crc8() - Calculate and return CRC-8 of the data
+ *
+ * This uses an x^8 + x^2 + x + 1 polynomial.  A table-based algorithm would
+ * be faster, but for only a few bytes it isn't worth the code size
+ *
+ * @crc_start: CRC8 start value
+ * @vptr: Buffer to checksum
+ * @len: Length of buffer in bytes
+ * @return CRC8 checksum
+ */
+unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len);
+
+#endif
diff --git a/include/linux/ctype.h b/include/linux/ctype.h
new file mode 100644
index 0000000..42f9305
--- /dev/null
+++ b/include/linux/ctype.h
@@ -0,0 +1,60 @@
+#ifndef _LINUX_CTYPE_H
+#define _LINUX_CTYPE_H
+
+/*
+ * NOTE! This ctype does not handle EOF like the standard C
+ * library is required to.
+ */
+
+#define _U	0x01	/* upper */
+#define _L	0x02	/* lower */
+#define _D	0x04	/* digit */
+#define _C	0x08	/* cntrl */
+#define _P	0x10	/* punct */
+#define _S	0x20	/* white space (space/lf/tab) */
+#define _X	0x40	/* hex digit */
+#define _SP	0x80	/* hard space (0x20) */
+
+extern const unsigned char _ctype[];
+
+#define __ismask(x) (_ctype[(int)(unsigned char)(x)])
+
+#define isalnum(c)	((__ismask(c)&(_U|_L|_D)) != 0)
+#define isalpha(c)	((__ismask(c)&(_U|_L)) != 0)
+#define iscntrl(c)	((__ismask(c)&(_C)) != 0)
+#define isdigit(c)	((__ismask(c)&(_D)) != 0)
+#define isgraph(c)	((__ismask(c)&(_P|_U|_L|_D)) != 0)
+#define islower(c)	((__ismask(c)&(_L)) != 0)
+#define isprint(c)	((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0)
+#define ispunct(c)	((__ismask(c)&(_P)) != 0)
+#define isspace(c)	((__ismask(c)&(_S)) != 0)
+#define isupper(c)	((__ismask(c)&(_U)) != 0)
+#define isxdigit(c)	((__ismask(c)&(_D|_X)) != 0)
+
+/*
+ * Rather than doubling the size of the _ctype lookup table to hold a 'blank'
+ * flag, just check for space or tab.
+ */
+#define isblank(c)	(c == ' ' || c == '\t')
+
+#define isascii(c) (((unsigned char)(c))<=0x7f)
+#define toascii(c) (((unsigned char)(c))&0x7f)
+
+static inline unsigned char __tolower(unsigned char c)
+{
+	if (isupper(c))
+		c -= 'A'-'a';
+	return c;
+}
+
+static inline unsigned char __toupper(unsigned char c)
+{
+	if (islower(c))
+		c -= 'a'-'A';
+	return c;
+}
+
+#define tolower(c) __tolower(c)
+#define toupper(c) __toupper(c)
+
+#endif
diff --git a/include/linux/delay.h b/include/linux/delay.h
new file mode 100644
index 0000000..71a38e1
--- /dev/null
+++ b/include/linux/delay.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _LINUX_DELAY_H
+#define _LINUX_DELAY_H
+
+#include <linux/kernel.h>
+
+void __udelay(unsigned long usec);
+void udelay(unsigned long usec);
+
+static inline void mdelay(unsigned long msec)
+{
+	udelay(1000 * msec);
+}
+
+static inline void ndelay(unsigned long nsec)
+{
+	udelay(DIV_ROUND_UP(nsec, 1000));
+}
+
+#endif /* defined(_LINUX_DELAY_H) */
diff --git a/include/linux/dma-direction.h b/include/linux/dma-direction.h
new file mode 100644
index 0000000..95b6a82
--- /dev/null
+++ b/include/linux/dma-direction.h
@@ -0,0 +1,13 @@
+#ifndef _LINUX_DMA_DIRECTION_H
+#define _LINUX_DMA_DIRECTION_H
+/*
+ * These definitions mirror those in pci.h, so they can be used
+ * interchangeably with their PCI_ counterparts.
+ */
+enum dma_data_direction {
+	DMA_BIDIRECTIONAL = 0,
+	DMA_TO_DEVICE = 1,
+	DMA_FROM_DEVICE = 2,
+	DMA_NONE = 3,
+};
+#endif
diff --git a/include/linux/drm_dp_helper.h b/include/linux/drm_dp_helper.h
new file mode 100644
index 0000000..758e4a4
--- /dev/null
+++ b/include/linux/drm_dp_helper.h
@@ -0,0 +1,406 @@
+/*
+ * Copyright © 2008 Keith Packard
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#ifndef _DRM_DP_HELPER_H_
+#define _DRM_DP_HELPER_H_
+
+/*
+ * Unless otherwise noted, all values are from the DP 1.1a spec.  Note that
+ * DP and DPCD versions are independent.  Differences from 1.0 are not noted,
+ * 1.0 devices basically don't exist in the wild.
+ *
+ * Abbreviations, in chronological order:
+ *
+ * eDP: Embedded DisplayPort version 1
+ * DPI: DisplayPort Interoperability Guideline v1.1a
+ * 1.2: DisplayPort 1.2
+ * MST: Multistream Transport - part of DP 1.2a
+ *
+ * 1.2 formally includes both eDP and DPI definitions.
+ */
+
+#define DP_AUX_I2C_WRITE		0x0
+#define DP_AUX_I2C_READ			0x1
+#define DP_AUX_I2C_STATUS		0x2
+#define DP_AUX_I2C_MOT			0x4
+#define DP_AUX_NATIVE_WRITE		0x8
+#define DP_AUX_NATIVE_READ		0x9
+
+#define DP_AUX_NATIVE_REPLY_ACK		(0x0 << 0)
+#define DP_AUX_NATIVE_REPLY_NACK	(0x1 << 0)
+#define DP_AUX_NATIVE_REPLY_DEFER	(0x2 << 0)
+#define DP_AUX_NATIVE_REPLY_MASK	(0x3 << 0)
+
+#define DP_AUX_I2C_REPLY_ACK		(0x0 << 2)
+#define DP_AUX_I2C_REPLY_NACK		(0x1 << 2)
+#define DP_AUX_I2C_REPLY_DEFER		(0x2 << 2)
+#define DP_AUX_I2C_REPLY_MASK		(0x3 << 2)
+
+/* AUX CH addresses */
+/* DPCD */
+#define DP_DPCD_REV                         0x000
+
+#define DP_MAX_LINK_RATE                    0x001
+
+#define DP_MAX_LANE_COUNT                   0x002
+# define DP_MAX_LANE_COUNT_MASK		    0x1f
+# define DP_TPS3_SUPPORTED		    (1 << 6) /* 1.2 */
+# define DP_ENHANCED_FRAME_CAP		    (1 << 7)
+
+#define DP_MAX_DOWNSPREAD                   0x003
+# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING  (1 << 6)
+
+#define DP_NORP                             0x004
+
+#define DP_DOWNSTREAMPORT_PRESENT           0x005
+# define DP_DWN_STRM_PORT_PRESENT           (1 << 0)
+# define DP_DWN_STRM_PORT_TYPE_MASK         0x06
+# define DP_DWN_STRM_PORT_TYPE_DP           (0 << 1)
+# define DP_DWN_STRM_PORT_TYPE_ANALOG       (1 << 1)
+# define DP_DWN_STRM_PORT_TYPE_TMDS         (2 << 1)
+# define DP_DWN_STRM_PORT_TYPE_OTHER        (3 << 1)
+# define DP_FORMAT_CONVERSION               (1 << 3)
+# define DP_DETAILED_CAP_INFO_AVAILABLE	    (1 << 4) /* DPI */
+
+#define DP_MAIN_LINK_CHANNEL_CODING         0x006
+
+#define DP_DOWN_STREAM_PORT_COUNT	    0x007
+# define DP_PORT_COUNT_MASK		    0x0f
+# define DP_MSA_TIMING_PAR_IGNORED	    (1 << 6) /* eDP */
+# define DP_OUI_SUPPORT			    (1 << 7)
+
+#define DP_I2C_SPEED_CAP		    0x00c    /* DPI */
+# define DP_I2C_SPEED_1K		    0x01
+# define DP_I2C_SPEED_5K		    0x02
+# define DP_I2C_SPEED_10K		    0x04
+# define DP_I2C_SPEED_100K		    0x08
+# define DP_I2C_SPEED_400K		    0x10
+# define DP_I2C_SPEED_1M		    0x20
+
+#define DP_EDP_CONFIGURATION_CAP            0x00d   /* XXX 1.2? */
+#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
+
+/* Multiple stream transport */
+#define DP_FAUX_CAP			    0x020   /* 1.2 */
+# define DP_FAUX_CAP_1			    (1 << 0)
+
+#define DP_MSTM_CAP			    0x021   /* 1.2 */
+# define DP_MST_CAP			    (1 << 0)
+
+#define DP_GUID				    0x030   /* 1.2 */
+
+#define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
+# define DP_PSR_IS_SUPPORTED                1
+#define DP_PSR_CAPS                         0x071   /* XXX 1.2? */
+# define DP_PSR_NO_TRAIN_ON_EXIT            1
+# define DP_PSR_SETUP_TIME_330              (0 << 1)
+# define DP_PSR_SETUP_TIME_275              (1 << 1)
+# define DP_PSR_SETUP_TIME_220              (2 << 1)
+# define DP_PSR_SETUP_TIME_165              (3 << 1)
+# define DP_PSR_SETUP_TIME_110              (4 << 1)
+# define DP_PSR_SETUP_TIME_55               (5 << 1)
+# define DP_PSR_SETUP_TIME_0                (6 << 1)
+# define DP_PSR_SETUP_TIME_MASK             (7 << 1)
+# define DP_PSR_SETUP_TIME_SHIFT            1
+
+/*
+ * 0x80-0x8f describe downstream port capabilities, but there are two layouts
+ * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it was not,
+ * each port's descriptor is one byte wide.  If it was set, each port's is
+ * four bytes wide, starting with the one byte from the base info.  As of
+ * DP interop v1.1a only VGA defines additional detail.
+ */
+
+/* offset 0 */
+#define DP_DOWNSTREAM_PORT_0		    0x80
+# define DP_DS_PORT_TYPE_MASK		    (7 << 0)
+# define DP_DS_PORT_TYPE_DP		    0
+# define DP_DS_PORT_TYPE_VGA		    1
+# define DP_DS_PORT_TYPE_DVI		    2
+# define DP_DS_PORT_TYPE_HDMI		    3
+# define DP_DS_PORT_TYPE_NON_EDID	    4
+# define DP_DS_PORT_HPD			    (1 << 3)
+/* offset 1 for VGA is maximum megapixels per second / 8 */
+/* offset 2 */
+# define DP_DS_VGA_MAX_BPC_MASK		    (3 << 0)
+# define DP_DS_VGA_8BPC			    0
+# define DP_DS_VGA_10BPC		    1
+# define DP_DS_VGA_12BPC		    2
+# define DP_DS_VGA_16BPC		    3
+
+/* link configuration */
+#define	DP_LINK_BW_SET		            0x100
+# define DP_LINK_BW_1_62		    0x06
+# define DP_LINK_BW_2_7			    0x0a
+# define DP_LINK_BW_5_4			    0x14    /* 1.2 */
+
+#define DP_LANE_COUNT_SET	            0x101
+# define DP_LANE_COUNT_MASK		    0x0f
+# define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
+
+#define DP_TRAINING_PATTERN_SET	            0x102
+# define DP_TRAINING_PATTERN_DISABLE	    0
+# define DP_TRAINING_PATTERN_1		    1
+# define DP_TRAINING_PATTERN_2		    2
+# define DP_TRAINING_PATTERN_3		    3	    /* 1.2 */
+# define DP_TRAINING_PATTERN_MASK	    0x3
+
+# define DP_LINK_QUAL_PATTERN_DISABLE	    (0 << 2)
+# define DP_LINK_QUAL_PATTERN_D10_2	    (1 << 2)
+# define DP_LINK_QUAL_PATTERN_ERROR_RATE    (2 << 2)
+# define DP_LINK_QUAL_PATTERN_PRBS7	    (3 << 2)
+# define DP_LINK_QUAL_PATTERN_MASK	    (3 << 2)
+
+# define DP_RECOVERED_CLOCK_OUT_EN	    (1 << 4)
+# define DP_LINK_SCRAMBLING_DISABLE	    (1 << 5)
+
+# define DP_SYMBOL_ERROR_COUNT_BOTH	    (0 << 6)
+# define DP_SYMBOL_ERROR_COUNT_DISPARITY    (1 << 6)
+# define DP_SYMBOL_ERROR_COUNT_SYMBOL	    (2 << 6)
+# define DP_SYMBOL_ERROR_COUNT_MASK	    (3 << 6)
+
+#define DP_TRAINING_LANE0_SET		    0x103
+#define DP_TRAINING_LANE1_SET		    0x104
+#define DP_TRAINING_LANE2_SET		    0x105
+#define DP_TRAINING_LANE3_SET		    0x106
+
+# define DP_TRAIN_VOLTAGE_SWING_MASK	    0x3
+# define DP_TRAIN_VOLTAGE_SWING_SHIFT	    0
+# define DP_TRAIN_MAX_SWING_REACHED	    (1 << 2)
+# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
+# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
+# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
+# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
+
+# define DP_TRAIN_PRE_EMPHASIS_MASK	    (3 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_0		(0 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_1		(1 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_2		(2 << 3)
+# define DP_TRAIN_PRE_EMPH_LEVEL_3		(3 << 3)
+
+# define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
+# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
+
+#define DP_DOWNSPREAD_CTRL		    0x107
+# define DP_SPREAD_AMP_0_5		    (1 << 4)
+# define DP_MSA_TIMING_PAR_IGNORE_EN	    (1 << 7) /* eDP */
+
+#define DP_MAIN_LINK_CHANNEL_CODING_SET	    0x108
+# define DP_SET_ANSI_8B10B		    (1 << 0)
+
+#define DP_I2C_SPEED_CONTROL_STATUS	    0x109   /* DPI */
+/* bitmask as for DP_I2C_SPEED_CAP */
+
+#define DP_EDP_CONFIGURATION_SET            0x10a   /* XXX 1.2? */
+
+#define DP_MSTM_CTRL			    0x111   /* 1.2 */
+# define DP_MST_EN			    (1 << 0)
+# define DP_UP_REQ_EN			    (1 << 1)
+# define DP_UPSTREAM_IS_SRC		    (1 << 2)
+
+#define DP_PSR_EN_CFG			    0x170   /* XXX 1.2? */
+# define DP_PSR_ENABLE			    (1 << 0)
+# define DP_PSR_MAIN_LINK_ACTIVE	    (1 << 1)
+# define DP_PSR_CRC_VERIFICATION	    (1 << 2)
+# define DP_PSR_FRAME_CAPTURE		    (1 << 3)
+
+#define DP_ADAPTER_CTRL			    0x1a0
+# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE   (1 << 0)
+
+#define DP_BRANCH_DEVICE_CTRL		    0x1a1
+# define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
+
+#define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
+#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
+#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
+
+#define DP_SINK_COUNT			    0x200
+/* prior to 1.2 bit 7 was reserved mbz */
+# define DP_GET_SINK_COUNT(x)		    ((((x) & 0x80) >> 1) | ((x) & 0x3f))
+# define DP_SINK_CP_READY		    (1 << 6)
+
+#define DP_DEVICE_SERVICE_IRQ_VECTOR	    0x201
+# define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
+# define DP_AUTOMATED_TEST_REQUEST	    (1 << 1)
+# define DP_CP_IRQ			    (1 << 2)
+# define DP_MCCS_IRQ			    (1 << 3)
+# define DP_DOWN_REP_MSG_RDY		    (1 << 4) /* 1.2 MST */
+# define DP_UP_REQ_MSG_RDY		    (1 << 5) /* 1.2 MST */
+# define DP_SINK_SPECIFIC_IRQ		    (1 << 6)
+
+#define DP_LANE0_1_STATUS		    0x202
+#define DP_LANE2_3_STATUS		    0x203
+# define DP_LANE_CR_DONE		    (1 << 0)
+# define DP_LANE_CHANNEL_EQ_DONE	    (1 << 1)
+# define DP_LANE_SYMBOL_LOCKED		    (1 << 2)
+
+#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |		\
+			    DP_LANE_CHANNEL_EQ_DONE |	\
+			    DP_LANE_SYMBOL_LOCKED)
+
+#define DP_LANE_ALIGN_STATUS_UPDATED	    0x204
+
+#define DP_INTERLANE_ALIGN_DONE		    (1 << 0)
+#define DP_DOWNSTREAM_PORT_STATUS_CHANGED   (1 << 6)
+#define DP_LINK_STATUS_UPDATED		    (1 << 7)
+
+#define DP_SINK_STATUS			    0x205
+#define DP_SINK_STATUS_PORT0_IN_SYNC	    (1 << 0)
+
+#define DP_RECEIVE_PORT_0_STATUS	    (1 << 0)
+#define DP_RECEIVE_PORT_1_STATUS	    (1 << 1)
+
+#define DP_ADJUST_REQUEST_LANE0_1	    0x206
+#define DP_ADJUST_REQUEST_LANE2_3	    0x207
+# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK  0x03
+# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
+# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK   0x0c
+# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT  2
+# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK  0x30
+# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
+# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
+# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
+
+#define DP_TEST_REQUEST			    0x218
+# define DP_TEST_LINK_TRAINING		    (1 << 0)
+# define DP_TEST_LINK_VIDEO_PATTERN	    (1 << 1)
+# define DP_TEST_LINK_EDID_READ		    (1 << 2)
+# define DP_TEST_LINK_PHY_TEST_PATTERN	    (1 << 3) /* DPCD >= 1.1 */
+# define DP_TEST_LINK_FAUX_PATTERN	    (1 << 4) /* DPCD >= 1.2 */
+
+#define DP_TEST_LINK_RATE		    0x219
+# define DP_LINK_RATE_162		    (0x6)
+# define DP_LINK_RATE_27		    (0xa)
+
+#define DP_TEST_LANE_COUNT		    0x220
+
+#define DP_TEST_PATTERN			    0x221
+
+#define DP_TEST_CRC_R_CR		    0x240
+#define DP_TEST_CRC_G_Y			    0x242
+#define DP_TEST_CRC_B_CB		    0x244
+
+#define DP_TEST_SINK_MISC		    0x246
+#define DP_TEST_CRC_SUPPORTED		    (1 << 5)
+
+#define DP_TEST_RESPONSE		    0x260
+# define DP_TEST_ACK			    (1 << 0)
+# define DP_TEST_NAK			    (1 << 1)
+# define DP_TEST_EDID_CHECKSUM_WRITE	    (1 << 2)
+
+#define DP_TEST_EDID_CHECKSUM		    0x261
+
+#define DP_TEST_SINK			    0x270
+#define DP_TEST_SINK_START	    (1 << 0)
+
+#define DP_PAYLOAD_TABLE_UPDATE_STATUS      0x2c0   /* 1.2 MST */
+# define DP_PAYLOAD_TABLE_UPDATED           (1 << 0)
+# define DP_PAYLOAD_ACT_HANDLED             (1 << 1)
+
+#define DP_VC_PAYLOAD_ID_SLOT_1             0x2c1   /* 1.2 MST */
+/* up to ID_SLOT_63 at 0x2ff */
+
+#define DP_SOURCE_OUI			    0x300
+#define DP_SINK_OUI			    0x400
+#define DP_BRANCH_OUI			    0x500
+
+#define DP_SET_POWER                        0x600
+# define DP_SET_POWER_D0                    0x1
+# define DP_SET_POWER_D3                    0x2
+# define DP_SET_POWER_MASK                  0x3
+
+#define DP_SIDEBAND_MSG_DOWN_REQ_BASE	    0x1000   /* 1.2 MST */
+#define DP_SIDEBAND_MSG_UP_REP_BASE	    0x1200   /* 1.2 MST */
+#define DP_SIDEBAND_MSG_DOWN_REP_BASE	    0x1400   /* 1.2 MST */
+#define DP_SIDEBAND_MSG_UP_REQ_BASE	    0x1600   /* 1.2 MST */
+
+#define DP_SINK_COUNT_ESI		    0x2002   /* 1.2 */
+/* 0-5 sink count */
+# define DP_SINK_COUNT_CP_READY             (1 << 6)
+
+#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x2003   /* 1.2 */
+
+#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x2004   /* 1.2 */
+
+#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0     0x2005   /* 1.2 */
+
+#define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
+# define DP_PSR_LINK_CRC_ERROR              (1 << 0)
+# define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
+
+#define DP_PSR_ESI                          0x2007  /* XXX 1.2? */
+# define DP_PSR_CAPS_CHANGE                 (1 << 0)
+
+#define DP_PSR_STATUS                       0x2008  /* XXX 1.2? */
+# define DP_PSR_SINK_INACTIVE               0
+# define DP_PSR_SINK_ACTIVE_SRC_SYNCED      1
+# define DP_PSR_SINK_ACTIVE_RFB             2
+# define DP_PSR_SINK_ACTIVE_SINK_SYNCED     3
+# define DP_PSR_SINK_ACTIVE_RESYNC          4
+# define DP_PSR_SINK_INTERNAL_ERROR         7
+# define DP_PSR_SINK_STATE_MASK             0x07
+
+/* DP 1.2 Sideband message defines */
+/* peer device type - DP 1.2a Table 2-92 */
+#define DP_PEER_DEVICE_NONE		0x0
+#define DP_PEER_DEVICE_SOURCE_OR_SST	0x1
+#define DP_PEER_DEVICE_MST_BRANCHING	0x2
+#define DP_PEER_DEVICE_SST_SINK		0x3
+#define DP_PEER_DEVICE_DP_LEGACY_CONV	0x4
+
+/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
+#define DP_LINK_ADDRESS			0x01
+#define DP_CONNECTION_STATUS_NOTIFY	0x02
+#define DP_ENUM_PATH_RESOURCES		0x10
+#define DP_ALLOCATE_PAYLOAD		0x11
+#define DP_QUERY_PAYLOAD		0x12
+#define DP_RESOURCE_STATUS_NOTIFY	0x13
+#define DP_CLEAR_PAYLOAD_ID_TABLE	0x14
+#define DP_REMOTE_DPCD_READ		0x20
+#define DP_REMOTE_DPCD_WRITE		0x21
+#define DP_REMOTE_I2C_READ		0x22
+#define DP_REMOTE_I2C_WRITE		0x23
+#define DP_POWER_UP_PHY			0x24
+#define DP_POWER_DOWN_PHY		0x25
+#define DP_SINK_EVENT_NOTIFY		0x30
+#define DP_QUERY_STREAM_ENC_STATUS	0x38
+
+/* DP 1.2 MST sideband nak reasons - table 2.84 */
+#define DP_NAK_WRITE_FAILURE		0x01
+#define DP_NAK_INVALID_READ		0x02
+#define DP_NAK_CRC_FAILURE		0x03
+#define DP_NAK_BAD_PARAM		0x04
+#define DP_NAK_DEFER			0x05
+#define DP_NAK_LINK_FAILURE		0x06
+#define DP_NAK_NO_RESOURCES		0x07
+#define DP_NAK_DPCD_FAIL		0x08
+#define DP_NAK_I2C_NAK			0x09
+#define DP_NAK_ALLOCATE_FAIL		0x0a
+
+#define MODE_I2C_START	1
+#define MODE_I2C_WRITE	2
+#define MODE_I2C_READ	4
+#define MODE_I2C_STOP	8
+
+/* Rest of file omitted as it is not used in U-Boot */
+
+#endif /* _DRM_DP_HELPER_H_ */
diff --git a/include/linux/edd.h b/include/linux/edd.h
new file mode 100644
index 0000000..992ce7c
--- /dev/null
+++ b/include/linux/edd.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * linux/include/linux/edd.h
+ *  Copyright (C) 2002, 2003, 2004 Dell Inc.
+ *  by Matt Domsch <Matt_Domsch@dell.com>
+ *
+ * structures and definitions for the int 13h, ax={41,48}h
+ * BIOS Enhanced Disk Drive Services
+ * This is based on the T13 group document D1572 Revision 0 (August 14 2002)
+ * available at http://www.t13.org/docs2002/d1572r0.pdf.  It is
+ * very similar to D1484 Revision 3 http://www.t13.org/docs2002/d1484r3.pdf
+ *
+ * In a nutshell, arch/{i386,x86_64}/boot/setup.S populates a scratch
+ * table in the boot_params that contains a list of BIOS-enumerated
+ * boot devices.
+ * In arch/{i386,x86_64}/kernel/setup.c, this information is
+ * transferred into the edd structure, and in drivers/firmware/edd.c, that
+ * information is used to identify BIOS boot disk.  The code in setup.S
+ * is very sensitive to the size of these structures.
+ */
+#ifndef _LINUX_EDD_H
+#define _LINUX_EDD_H
+
+#include <linux/types.h>
+
+#define EDDNR 0x1e9		/* addr of number of edd_info structs at EDDBUF
+				   in boot_params - treat this as 1 byte  */
+#define EDDBUF	0xd00		/* addr of edd_info structs in boot_params */
+#define EDDMAXNR 6		/* number of edd_info structs starting at EDDBUF  */
+#define EDDEXTSIZE 8		/* change these if you muck with the structures */
+#define EDDPARMSIZE 74
+#define CHECKEXTENSIONSPRESENT 0x41
+#define GETDEVICEPARAMETERS 0x48
+#define LEGACYGETDEVICEPARAMETERS 0x08
+#define EDDMAGIC1 0x55AA
+#define EDDMAGIC2 0xAA55
+
+
+#define READ_SECTORS 0x02         /* int13 AH=0x02 is READ_SECTORS command */
+#define EDD_MBR_SIG_OFFSET 0x1B8  /* offset of signature in the MBR */
+#define EDD_MBR_SIG_BUF    0x290  /* addr in boot params */
+#define EDD_MBR_SIG_MAX 16        /* max number of signatures to store */
+#define EDD_MBR_SIG_NR_BUF 0x1ea  /* addr of number of MBR signtaures at EDD_MBR_SIG_BUF
+				     in boot_params - treat this as 1 byte  */
+
+#ifndef __ASSEMBLY__
+
+#define EDD_EXT_FIXED_DISK_ACCESS           (1 << 0)
+#define EDD_EXT_DEVICE_LOCKING_AND_EJECTING (1 << 1)
+#define EDD_EXT_ENHANCED_DISK_DRIVE_SUPPORT (1 << 2)
+#define EDD_EXT_64BIT_EXTENSIONS            (1 << 3)
+
+#define EDD_INFO_DMA_BOUNDARY_ERROR_TRANSPARENT (1 << 0)
+#define EDD_INFO_GEOMETRY_VALID                (1 << 1)
+#define EDD_INFO_REMOVABLE                     (1 << 2)
+#define EDD_INFO_WRITE_VERIFY                  (1 << 3)
+#define EDD_INFO_MEDIA_CHANGE_NOTIFICATION     (1 << 4)
+#define EDD_INFO_LOCKABLE                      (1 << 5)
+#define EDD_INFO_NO_MEDIA_PRESENT              (1 << 6)
+#define EDD_INFO_USE_INT13_FN50                (1 << 7)
+
+struct edd_device_params {
+	__u16 length;
+	__u16 info_flags;
+	__u32 num_default_cylinders;
+	__u32 num_default_heads;
+	__u32 sectors_per_track;
+	__u64 number_of_sectors;
+	__u16 bytes_per_sector;
+	__u32 dpte_ptr;		/* 0xFFFFFFFF for our purposes */
+	__u16 key;		/* = 0xBEDD */
+	__u8 device_path_info_length;	/* = 44 */
+	__u8 reserved2;
+	__u16 reserved3;
+	__u8 host_bus_type[4];
+	__u8 interface_type[8];
+	union {
+		struct {
+			__u16 base_address;
+			__u16 reserved1;
+			__u32 reserved2;
+		} __attribute__ ((packed)) isa;
+		struct {
+			__u8 bus;
+			__u8 slot;
+			__u8 function;
+			__u8 channel;
+			__u32 reserved;
+		} __attribute__ ((packed)) pci;
+		/* pcix is same as pci */
+		struct {
+			__u64 reserved;
+		} __attribute__ ((packed)) ibnd;
+		struct {
+			__u64 reserved;
+		} __attribute__ ((packed)) xprs;
+		struct {
+			__u64 reserved;
+		} __attribute__ ((packed)) htpt;
+		struct {
+			__u64 reserved;
+		} __attribute__ ((packed)) unknown;
+	} interface_path;
+	union {
+		struct {
+			__u8 device;
+			__u8 reserved1;
+			__u16 reserved2;
+			__u32 reserved3;
+			__u64 reserved4;
+		} __attribute__ ((packed)) ata;
+		struct {
+			__u8 device;
+			__u8 lun;
+			__u8 reserved1;
+			__u8 reserved2;
+			__u32 reserved3;
+			__u64 reserved4;
+		} __attribute__ ((packed)) atapi;
+		struct {
+			__u16 id;
+			__u64 lun;
+			__u16 reserved1;
+			__u32 reserved2;
+		} __attribute__ ((packed)) scsi;
+		struct {
+			__u64 serial_number;
+			__u64 reserved;
+		} __attribute__ ((packed)) usb;
+		struct {
+			__u64 eui;
+			__u64 reserved;
+		} __attribute__ ((packed)) i1394;
+		struct {
+			__u64 wwid;
+			__u64 lun;
+		} __attribute__ ((packed)) fibre;
+		struct {
+			__u64 identity_tag;
+			__u64 reserved;
+		} __attribute__ ((packed)) i2o;
+		struct {
+			__u32 array_number;
+			__u32 reserved1;
+			__u64 reserved2;
+		} __attribute__ ((packed)) raid;
+		struct {
+			__u8 device;
+			__u8 reserved1;
+			__u16 reserved2;
+			__u32 reserved3;
+			__u64 reserved4;
+		} __attribute__ ((packed)) sata;
+		struct {
+			__u64 reserved1;
+			__u64 reserved2;
+		} __attribute__ ((packed)) unknown;
+	} device_path;
+	__u8 reserved4;
+	__u8 checksum;
+} __attribute__ ((packed));
+
+struct edd_info {
+	__u8 device;
+	__u8 version;
+	__u16 interface_support;
+	__u16 legacy_max_cylinder;
+	__u8 legacy_max_head;
+	__u8 legacy_sectors_per_track;
+	struct edd_device_params params;
+} __attribute__ ((packed));
+
+struct edd {
+	unsigned int mbr_signature[EDD_MBR_SIG_MAX];
+	struct edd_info edd_info[EDDMAXNR];
+	unsigned char mbr_signature_nr;
+	unsigned char edd_info_nr;
+};
+
+#ifdef __KERNEL__
+extern struct edd edd;
+#endif /* __KERNEL__ */
+#endif				/*!__ASSEMBLY__ */
+
+#endif				/* _LINUX_EDD_H */
diff --git a/include/linux/err.h b/include/linux/err.h
new file mode 100644
index 0000000..22e5756
--- /dev/null
+++ b/include/linux/err.h
@@ -0,0 +1,59 @@
+#ifndef _LINUX_ERR_H
+#define _LINUX_ERR_H
+
+#include <linux/compiler.h>
+#include <linux/compat.h>
+
+#include <linux/errno.h>
+
+
+/*
+ * Kernel pointers have redundant information, so we can use a
+ * scheme where we can return either an error code or a dentry
+ * pointer with the same return value.
+ *
+ * This should be a per-architecture thing, to allow different
+ * error and pointer decisions.
+ */
+#define MAX_ERRNO	4095
+
+#ifndef __ASSEMBLY__
+
+#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
+
+static inline void *ERR_PTR(long error)
+{
+	return (void *) error;
+}
+
+static inline long PTR_ERR(const void *ptr)
+{
+	return (long) ptr;
+}
+
+static inline long IS_ERR(const void *ptr)
+{
+	return IS_ERR_VALUE((unsigned long)ptr);
+}
+
+static inline bool IS_ERR_OR_NULL(const void *ptr)
+{
+	return !ptr || IS_ERR_VALUE((unsigned long)ptr);
+}
+
+/**
+ * ERR_CAST - Explicitly cast an error-valued pointer to another pointer type
+ * @ptr: The pointer to cast.
+ *
+ * Explicitly cast an error-valued pointer to another pointer type in such a
+ * way as to make it clear that's what's going on.
+ */
+static inline void * __must_check ERR_CAST(__force const void *ptr)
+{
+	/* cast away the const */
+	return (void *) ptr;
+}
+
+#endif
+
+#endif /* _LINUX_ERR_H */
diff --git a/include/linux/errno.h b/include/linux/errno.h
new file mode 100644
index 0000000..3d94207
--- /dev/null
+++ b/include/linux/errno.h
@@ -0,0 +1,168 @@
+#ifndef _LINUX_ERRNO_H
+#define _LINUX_ERRNO_H
+
+#define	EPERM		 1	/* Operation not permitted */
+#define	ENOENT		 2	/* No such file or directory */
+#define	ESRCH		 3	/* No such process */
+#define	EINTR		 4	/* Interrupted system call */
+#define	EIO		 5	/* I/O error */
+#define	ENXIO		 6	/* No such device or address */
+#define	E2BIG		 7	/* Argument list too long */
+#define	ENOEXEC		 8	/* Exec format error */
+#define	EBADF		 9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+
+#define	ENOSYS		38	/* Invalid system call number */
+
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+
+#define	EDEADLOCK	EDEADLK
+
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+#define	ECANCELED	125	/* Operation Canceled */
+#define	ENOKEY		126	/* Required key not available */
+#define	EKEYEXPIRED	127	/* Key has expired */
+#define	EKEYREVOKED	128	/* Key has been revoked */
+#define	EKEYREJECTED	129	/* Key was rejected by service */
+
+/* for robust mutexes */
+#define	EOWNERDEAD	130	/* Owner died */
+#define	ENOTRECOVERABLE	131	/* State not recoverable */
+
+#define ERFKILL		132	/* Operation not possible due to RF-kill */
+
+#define EHWPOISON	133	/* Memory page has hardware error */
+
+#define ERESTARTSYS	512
+#define ERESTARTNOINTR	513
+#define ERESTARTNOHAND	514	/* restart if no handler.. */
+#define ENOIOCTLCMD	515	/* No ioctl command */
+#define ERESTART_RESTARTBLOCK 516 /* restart by calling sys_restart_syscall */
+#define EPROBE_DEFER	517	/* Driver requests probe retry */
+#define EOPENSTALE	518	/* open found a stale dentry */
+
+/* Defined for the NFSv3 protocol */
+#define EBADHANDLE	521	/* Illegal NFS file handle */
+#define ENOTSYNC	522	/* Update synchronization mismatch */
+#define EBADCOOKIE	523	/* Cookie is stale */
+#define ENOTSUPP	524	/* Operation is not supported */
+#define ETOOSMALL	525	/* Buffer or request is too small */
+#define ESERVERFAULT	526	/* An untranslatable error occurred */
+#define EBADTYPE	527	/* Type not supported by server */
+#define EJUKEBOX	528	/* Request initiated, but will not complete before timeout */
+#define EIOCBQUEUED	529	/* iocb queued, will get completion event */
+#define ERECALLCONFLICT	530	/* conflict with recalled state */
+
+#endif
diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
new file mode 100644
index 0000000..f6dbdb0
--- /dev/null
+++ b/include/linux/ethtool.h
@@ -0,0 +1,725 @@
+/*
+ * ethtool.h: Defines for Linux ethtool.
+ *
+ * Copyright (C) 1998 David S. Miller (davem@redhat.com)
+ * Copyright 2001 Jeff Garzik <jgarzik@pobox.com>
+ * Portions Copyright 2001 Sun Microsystems (thockin@sun.com)
+ * Portions Copyright 2002 Intel (eli.kupermann@intel.com,
+ *                                christopher.leech@intel.com,
+ *                                scott.feldman@intel.com)
+ * Portions Copyright (C) Sun Microsystems 2008
+ */
+
+#ifndef _LINUX_ETHTOOL_H
+#define _LINUX_ETHTOOL_H
+
+#include <linux/types.h>
+
+/* This should work for both 32 and 64 bit userland. */
+struct ethtool_cmd {
+	__u32	cmd;
+	__u32	supported;	/* Features this interface supports */
+	__u32	advertising;	/* Features this interface advertises */
+	__u16	speed;		/* The forced speed, 10Mb, 100Mb, gigabit */
+	__u8	duplex;		/* Duplex, half or full */
+	__u8	port;		/* Which connector port */
+	__u8	phy_address;
+	__u8	transceiver;	/* Which transceiver to use */
+	__u8	autoneg;	/* Enable or disable autonegotiation */
+	__u8	mdio_support;
+	__u32	maxtxpkt;	/* Tx pkts before generating tx int */
+	__u32	maxrxpkt;	/* Rx pkts before generating rx int */
+	__u16	speed_hi;
+	__u8	eth_tp_mdix;
+	__u8	reserved2;
+	__u32	lp_advertising;	/* Features the link partner advertises */
+	__u32	reserved[2];
+};
+
+static inline void ethtool_cmd_speed_set(struct ethtool_cmd *ep,
+						__u32 speed)
+{
+
+	ep->speed = (__u16)speed;
+	ep->speed_hi = (__u16)(speed >> 16);
+}
+
+static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep)
+{
+	return (ep->speed_hi << 16) | ep->speed;
+}
+
+#define ETHTOOL_FWVERS_LEN	32
+#define ETHTOOL_BUSINFO_LEN	32
+/* these strings are set to whatever the driver author decides... */
+struct ethtool_drvinfo {
+	__u32	cmd;
+	char	driver[32];	/* driver short name, "tulip", "eepro100" */
+	char	version[32];	/* driver version string */
+	char	fw_version[ETHTOOL_FWVERS_LEN];	/* firmware version string */
+	char	bus_info[ETHTOOL_BUSINFO_LEN];	/* Bus info for this IF. */
+				/* For PCI devices, use pci_name(pci_dev). */
+	char	reserved1[32];
+	char	reserved2[12];
+				/*
+				 * Some struct members below are filled in
+				 * using ops->get_sset_count().  Obtaining
+				 * this info from ethtool_drvinfo is now
+				 * deprecated; Use ETHTOOL_GSSET_INFO
+				 * instead.
+				 */
+	__u32	n_priv_flags;	/* number of flags valid in ETHTOOL_GPFLAGS */
+	__u32	n_stats;	/* number of u64's from ETHTOOL_GSTATS */
+	__u32	testinfo_len;
+	__u32	eedump_len;	/* Size of data from ETHTOOL_GEEPROM (bytes) */
+	__u32	regdump_len;	/* Size of data from ETHTOOL_GREGS (bytes) */
+};
+
+#define SOPASS_MAX	6
+/* wake-on-lan settings */
+struct ethtool_wolinfo {
+	__u32	cmd;
+	__u32	supported;
+	__u32	wolopts;
+	__u8	sopass[SOPASS_MAX]; /* SecureOn(tm) password */
+};
+
+/* for passing single values */
+struct ethtool_value {
+	__u32	cmd;
+	__u32	data;
+};
+
+/* for passing big chunks of data */
+struct ethtool_regs {
+	__u32	cmd;
+	__u32	version; /* driver-specific, indicates different chips/revs */
+	__u32	len; /* bytes */
+	__u8	data[0];
+};
+
+/* for passing EEPROM chunks */
+struct ethtool_eeprom {
+	__u32	cmd;
+	__u32	magic;
+	__u32	offset; /* in bytes */
+	__u32	len; /* in bytes */
+	__u8	data[0];
+};
+
+/* for configuring coalescing parameters of chip */
+struct ethtool_coalesce {
+	__u32	cmd;	/* ETHTOOL_{G,S}COALESCE */
+
+	/* How many usecs to delay an RX interrupt after
+	 * a packet arrives.  If 0, only rx_max_coalesced_frames
+	 * is used.
+	 */
+	__u32	rx_coalesce_usecs;
+
+	/* How many packets to delay an RX interrupt after
+	 * a packet arrives.  If 0, only rx_coalesce_usecs is
+	 * used.  It is illegal to set both usecs and max frames
+	 * to zero as this would cause RX interrupts to never be
+	 * generated.
+	 */
+	__u32	rx_max_coalesced_frames;
+
+	/* Same as above two parameters, except that these values
+	 * apply while an IRQ is being serviced by the host.  Not
+	 * all cards support this feature and the values are ignored
+	 * in that case.
+	 */
+	__u32	rx_coalesce_usecs_irq;
+	__u32	rx_max_coalesced_frames_irq;
+
+	/* How many usecs to delay a TX interrupt after
+	 * a packet is sent.  If 0, only tx_max_coalesced_frames
+	 * is used.
+	 */
+	__u32	tx_coalesce_usecs;
+
+	/* How many packets to delay a TX interrupt after
+	 * a packet is sent.  If 0, only tx_coalesce_usecs is
+	 * used.  It is illegal to set both usecs and max frames
+	 * to zero as this would cause TX interrupts to never be
+	 * generated.
+	 */
+	__u32	tx_max_coalesced_frames;
+
+	/* Same as above two parameters, except that these values
+	 * apply while an IRQ is being serviced by the host.  Not
+	 * all cards support this feature and the values are ignored
+	 * in that case.
+	 */
+	__u32	tx_coalesce_usecs_irq;
+	__u32	tx_max_coalesced_frames_irq;
+
+	/* How many usecs to delay in-memory statistics
+	 * block updates.  Some drivers do not have an in-memory
+	 * statistic block, and in such cases this value is ignored.
+	 * This value must not be zero.
+	 */
+	__u32	stats_block_coalesce_usecs;
+
+	/* Adaptive RX/TX coalescing is an algorithm implemented by
+	 * some drivers to improve latency under low packet rates and
+	 * improve throughput under high packet rates.  Some drivers
+	 * only implement one of RX or TX adaptive coalescing.  Anything
+	 * not implemented by the driver causes these values to be
+	 * silently ignored.
+	 */
+	__u32	use_adaptive_rx_coalesce;
+	__u32	use_adaptive_tx_coalesce;
+
+	/* When the packet rate (measured in packets per second)
+	 * is below pkt_rate_low, the {rx,tx}_*_low parameters are
+	 * used.
+	 */
+	__u32	pkt_rate_low;
+	__u32	rx_coalesce_usecs_low;
+	__u32	rx_max_coalesced_frames_low;
+	__u32	tx_coalesce_usecs_low;
+	__u32	tx_max_coalesced_frames_low;
+
+	/* When the packet rate is below pkt_rate_high but above
+	 * pkt_rate_low (both measured in packets per second) the
+	 * normal {rx,tx}_* coalescing parameters are used.
+	 */
+
+	/* When the packet rate is (measured in packets per second)
+	 * is above pkt_rate_high, the {rx,tx}_*_high parameters are
+	 * used.
+	 */
+	__u32	pkt_rate_high;
+	__u32	rx_coalesce_usecs_high;
+	__u32	rx_max_coalesced_frames_high;
+	__u32	tx_coalesce_usecs_high;
+	__u32	tx_max_coalesced_frames_high;
+
+	/* How often to do adaptive coalescing packet rate sampling,
+	 * measured in seconds.  Must not be zero.
+	 */
+	__u32	rate_sample_interval;
+};
+
+/* for configuring RX/TX ring parameters */
+struct ethtool_ringparam {
+	__u32	cmd;	/* ETHTOOL_{G,S}RINGPARAM */
+
+	/* Read only attributes.  These indicate the maximum number
+	 * of pending RX/TX ring entries the driver will allow the
+	 * user to set.
+	 */
+	__u32	rx_max_pending;
+	__u32	rx_mini_max_pending;
+	__u32	rx_jumbo_max_pending;
+	__u32	tx_max_pending;
+
+	/* Values changeable by the user.  The valid values are
+	 * in the range 1 to the "*_max_pending" counterpart above.
+	 */
+	__u32	rx_pending;
+	__u32	rx_mini_pending;
+	__u32	rx_jumbo_pending;
+	__u32	tx_pending;
+};
+
+/* for configuring link flow control parameters */
+struct ethtool_pauseparam {
+	__u32	cmd;	/* ETHTOOL_{G,S}PAUSEPARAM */
+
+	/* If the link is being auto-negotiated (via ethtool_cmd.autoneg
+	 * being true) the user may set 'autonet' here non-zero to have the
+	 * pause parameters be auto-negotiated too.  In such a case, the
+	 * {rx,tx}_pause values below determine what capabilities are
+	 * advertised.
+	 *
+	 * If 'autoneg' is zero or the link is not being auto-negotiated,
+	 * then {rx,tx}_pause force the driver to use/not-use pause
+	 * flow control.
+	 */
+	__u32	autoneg;
+	__u32	rx_pause;
+	__u32	tx_pause;
+};
+
+#define ETH_GSTRING_LEN		32
+enum ethtool_stringset {
+	ETH_SS_TEST		= 0,
+	ETH_SS_STATS,
+	ETH_SS_PRIV_FLAGS,
+	ETH_SS_NTUPLE_FILTERS,
+	ETH_SS_FEATURES,
+};
+
+/* for passing string sets for data tagging */
+struct ethtool_gstrings {
+	__u32	cmd;		/* ETHTOOL_GSTRINGS */
+	__u32	string_set;	/* string set id e.c. ETH_SS_TEST, etc*/
+	__u32	len;		/* number of strings in the string set */
+	__u8	data[0];
+};
+
+struct ethtool_sset_info {
+	__u32	cmd;		/* ETHTOOL_GSSET_INFO */
+	__u32	reserved;
+	__u64	sset_mask;	/* input: each bit selects an sset to query */
+				/* output: each bit a returned sset */
+	__u32	data[0];	/* ETH_SS_xxx count, in order, based on bits
+				   in sset_mask.  One bit implies one
+				   __u32, two bits implies two
+				   __u32's, etc. */
+};
+
+enum ethtool_test_flags {
+	ETH_TEST_FL_OFFLINE	= (1 << 0),	/* online / offline */
+	ETH_TEST_FL_FAILED	= (1 << 1),	/* test passed / failed */
+};
+
+/* for requesting NIC test and getting results*/
+struct ethtool_test {
+	__u32	cmd;		/* ETHTOOL_TEST */
+	__u32	flags;		/* ETH_TEST_FL_xxx */
+	__u32	reserved;
+	__u32	len;		/* result length, in number of u64 elements */
+	__u64	data[0];
+};
+
+/* for dumping NIC-specific statistics */
+struct ethtool_stats {
+	__u32	cmd;		/* ETHTOOL_GSTATS */
+	__u32	n_stats;	/* number of u64's being returned */
+	__u64	data[0];
+};
+
+struct ethtool_perm_addr {
+	__u32	cmd;		/* ETHTOOL_GPERMADDR */
+	__u32	size;
+	__u8	data[0];
+};
+
+/* boolean flags controlling per-interface behavior characteristics.
+ * When reading, the flag indicates whether or not a certain behavior
+ * is enabled/present.  When writing, the flag indicates whether
+ * or not the driver should turn on (set) or off (clear) a behavior.
+ *
+ * Some behaviors may read-only (unconditionally absent or present).
+ * If such is the case, return EINVAL in the set-flags operation if the
+ * flag differs from the read-only value.
+ */
+enum ethtool_flags {
+	ETH_FLAG_TXVLAN		= (1 << 7),	/* TX VLAN offload enabled */
+	ETH_FLAG_RXVLAN		= (1 << 8),	/* RX VLAN offload enabled */
+	ETH_FLAG_LRO		= (1 << 15),	/* LRO is enabled */
+	ETH_FLAG_NTUPLE		= (1 << 27),	/* N-tuple filters enabled */
+	ETH_FLAG_RXHASH		= (1 << 28),
+};
+
+/* The following structures are for supporting RX network flow
+ * classification and RX n-tuple configuration. Note, all multibyte
+ * fields, e.g., ip4src, ip4dst, psrc, pdst, spi, etc. are expected to
+ * be in network byte order.
+ */
+
+/**
+ * struct ethtool_tcpip4_spec - flow specification for TCP/IPv4 etc.
+ * @ip4src: Source host
+ * @ip4dst: Destination host
+ * @psrc: Source port
+ * @pdst: Destination port
+ * @tos: Type-of-service
+ *
+ * This can be used to specify a TCP/IPv4, UDP/IPv4 or SCTP/IPv4 flow.
+ */
+struct ethtool_tcpip4_spec {
+	__be32	ip4src;
+	__be32	ip4dst;
+	__be16	psrc;
+	__be16	pdst;
+	__u8    tos;
+};
+
+/**
+ * struct ethtool_ah_espip4_spec - flow specification for IPsec/IPv4
+ * @ip4src: Source host
+ * @ip4dst: Destination host
+ * @spi: Security parameters index
+ * @tos: Type-of-service
+ *
+ * This can be used to specify an IPsec transport or tunnel over IPv4.
+ */
+struct ethtool_ah_espip4_spec {
+	__be32	ip4src;
+	__be32	ip4dst;
+	__be32	spi;
+	__u8    tos;
+};
+
+#define	ETH_RX_NFC_IP4	1
+
+/**
+ * struct ethtool_usrip4_spec - general flow specification for IPv4
+ * @ip4src: Source host
+ * @ip4dst: Destination host
+ * @l4_4_bytes: First 4 bytes of transport (layer 4) header
+ * @tos: Type-of-service
+ * @ip_ver: Value must be %ETH_RX_NFC_IP4; mask must be 0
+ * @proto: Transport protocol number; mask must be 0
+ */
+struct ethtool_usrip4_spec {
+	__be32	ip4src;
+	__be32	ip4dst;
+	__be32	l4_4_bytes;
+	__u8    tos;
+	__u8    ip_ver;
+	__u8    proto;
+};
+
+
+/**
+ * struct ethtool_rxfh_indir - command to get or set RX flow hash indirection
+ * @cmd: Specific command number - %ETHTOOL_GRXFHINDIR or %ETHTOOL_SRXFHINDIR
+ * @size: On entry, the array size of the user buffer.  On return from
+ *	%ETHTOOL_GRXFHINDIR, the array size of the hardware indirection table.
+ * @ring_index: RX ring/queue index for each hash value
+ */
+struct ethtool_rxfh_indir {
+	__u32	cmd;
+	__u32	size;
+	__u32	ring_index[0];
+};
+
+#define ETHTOOL_FLASH_MAX_FILENAME	128
+enum ethtool_flash_op_type {
+	ETHTOOL_FLASH_ALL_REGIONS	= 0,
+};
+
+/* for passing firmware flashing related parameters */
+struct ethtool_flash {
+	__u32	cmd;
+	__u32	region;
+	char	data[ETHTOOL_FLASH_MAX_FILENAME];
+};
+
+/* for returning and changing feature sets */
+
+/**
+ * struct ethtool_get_features_block - block with state of 32 features
+ * @available: mask of changeable features
+ * @requested: mask of features requested to be enabled if possible
+ * @active: mask of currently enabled features
+ * @never_changed: mask of features not changeable for any device
+ */
+struct ethtool_get_features_block {
+	__u32	available;
+	__u32	requested;
+	__u32	active;
+	__u32	never_changed;
+};
+
+/**
+ * struct ethtool_gfeatures - command to get state of device's features
+ * @cmd: command number = %ETHTOOL_GFEATURES
+ * @size: in: number of elements in the features[] array;
+ *       out: number of elements in features[] needed to hold all features
+ * @features: state of features
+ */
+struct ethtool_gfeatures {
+	__u32	cmd;
+	__u32	size;
+	struct ethtool_get_features_block features[0];
+};
+
+/**
+ * struct ethtool_set_features_block - block with request for 32 features
+ * @valid: mask of features to be changed
+ * @requested: values of features to be changed
+ */
+struct ethtool_set_features_block {
+	__u32	valid;
+	__u32	requested;
+};
+
+/**
+ * struct ethtool_sfeatures - command to request change in device's features
+ * @cmd: command number = %ETHTOOL_SFEATURES
+ * @size: array size of the features[] array
+ * @features: feature change masks
+ */
+struct ethtool_sfeatures {
+	__u32	cmd;
+	__u32	size;
+	struct ethtool_set_features_block features[0];
+};
+
+/*
+ * %ETHTOOL_SFEATURES changes features present in features[].valid to the
+ * values of corresponding bits in features[].requested. Bits in .requested
+ * not set in .valid or not changeable are ignored.
+ *
+ * Returns %EINVAL when .valid contains undefined or never-changable bits
+ * or size is not equal to required number of features words (32-bit blocks).
+ * Returns >= 0 if request was completed; bits set in the value mean:
+ *   %ETHTOOL_F_UNSUPPORTED - there were bits set in .valid that are not
+ *	changeable (not present in %ETHTOOL_GFEATURES' features[].available)
+ *	those bits were ignored.
+ *   %ETHTOOL_F_WISH - some or all changes requested were recorded but the
+ *      resulting state of bits masked by .valid is not equal to .requested.
+ *      Probably there are other device-specific constraints on some features
+ *      in the set. When %ETHTOOL_F_UNSUPPORTED is set, .valid is considered
+ *      here as though ignored bits were cleared.
+ *   %ETHTOOL_F_COMPAT - some or all changes requested were made by calling
+ *      compatibility functions. Requested offload state cannot be properly
+ *      managed by kernel.
+ *
+ * Meaning of bits in the masks are obtained by %ETHTOOL_GSSET_INFO (number of
+ * bits in the arrays - always multiple of 32) and %ETHTOOL_GSTRINGS commands
+ * for ETH_SS_FEATURES string set. First entry in the table corresponds to least
+ * significant bit in features[0] fields. Empty strings mark undefined features.
+ */
+enum ethtool_sfeatures_retval_bits {
+	ETHTOOL_F_UNSUPPORTED__BIT,
+	ETHTOOL_F_WISH__BIT,
+	ETHTOOL_F_COMPAT__BIT,
+};
+
+#define ETHTOOL_F_UNSUPPORTED   (1 << ETHTOOL_F_UNSUPPORTED__BIT)
+#define ETHTOOL_F_WISH          (1 << ETHTOOL_F_WISH__BIT)
+#define ETHTOOL_F_COMPAT        (1 << ETHTOOL_F_COMPAT__BIT)
+
+/* CMDs currently supported */
+#define ETHTOOL_GSET		0x00000001 /* Get settings. */
+#define ETHTOOL_SSET		0x00000002 /* Set settings. */
+#define ETHTOOL_GDRVINFO	0x00000003 /* Get driver info. */
+#define ETHTOOL_GREGS		0x00000004 /* Get NIC registers. */
+#define ETHTOOL_GWOL		0x00000005 /* Get wake-on-lan options. */
+#define ETHTOOL_SWOL		0x00000006 /* Set wake-on-lan options. */
+#define ETHTOOL_GMSGLVL		0x00000007 /* Get driver message level */
+#define ETHTOOL_SMSGLVL		0x00000008 /* Set driver msg level. */
+#define ETHTOOL_NWAY_RST	0x00000009 /* Restart autonegotiation. */
+/* Get link status for host, i.e. whether the interface *and* the
+ * physical port (if there is one) are up (ethtool_value). */
+#define ETHTOOL_GLINK		0x0000000a
+#define ETHTOOL_GEEPROM		0x0000000b /* Get EEPROM data */
+#define ETHTOOL_SEEPROM		0x0000000c /* Set EEPROM data. */
+#define ETHTOOL_GCOALESCE	0x0000000e /* Get coalesce config */
+#define ETHTOOL_SCOALESCE	0x0000000f /* Set coalesce config. */
+#define ETHTOOL_GRINGPARAM	0x00000010 /* Get ring parameters */
+#define ETHTOOL_SRINGPARAM	0x00000011 /* Set ring parameters. */
+#define ETHTOOL_GPAUSEPARAM	0x00000012 /* Get pause parameters */
+#define ETHTOOL_SPAUSEPARAM	0x00000013 /* Set pause parameters. */
+#define ETHTOOL_GRXCSUM		0x00000014 /* Get RX hw csum enable (ethtool_value) */
+#define ETHTOOL_SRXCSUM		0x00000015 /* Set RX hw csum enable (ethtool_value) */
+#define ETHTOOL_GTXCSUM		0x00000016 /* Get TX hw csum enable (ethtool_value) */
+#define ETHTOOL_STXCSUM		0x00000017 /* Set TX hw csum enable (ethtool_value) */
+#define ETHTOOL_GSG		0x00000018 /* Get scatter-gather enable
+					    * (ethtool_value) */
+#define ETHTOOL_SSG		0x00000019 /* Set scatter-gather enable
+					    * (ethtool_value). */
+#define ETHTOOL_TEST		0x0000001a /* execute NIC self-test. */
+#define ETHTOOL_GSTRINGS	0x0000001b /* get specified string set */
+#define ETHTOOL_PHYS_ID		0x0000001c /* identify the NIC */
+#define ETHTOOL_GSTATS		0x0000001d /* get NIC-specific statistics */
+#define ETHTOOL_GTSO		0x0000001e /* Get TSO enable (ethtool_value) */
+#define ETHTOOL_STSO		0x0000001f /* Set TSO enable (ethtool_value) */
+#define ETHTOOL_GPERMADDR	0x00000020 /* Get permanent hardware address */
+#define ETHTOOL_GUFO		0x00000021 /* Get UFO enable (ethtool_value) */
+#define ETHTOOL_SUFO		0x00000022 /* Set UFO enable (ethtool_value) */
+#define ETHTOOL_GGSO		0x00000023 /* Get GSO enable (ethtool_value) */
+#define ETHTOOL_SGSO		0x00000024 /* Set GSO enable (ethtool_value) */
+#define ETHTOOL_GFLAGS		0x00000025 /* Get flags bitmap(ethtool_value) */
+#define ETHTOOL_SFLAGS		0x00000026 /* Set flags bitmap(ethtool_value) */
+#define ETHTOOL_GPFLAGS		0x00000027 /* Get driver-private flags bitmap */
+#define ETHTOOL_SPFLAGS		0x00000028 /* Set driver-private flags bitmap */
+
+#define ETHTOOL_GRXFH		0x00000029 /* Get RX flow hash configuration */
+#define ETHTOOL_SRXFH		0x0000002a /* Set RX flow hash configuration */
+#define ETHTOOL_GGRO		0x0000002b /* Get GRO enable (ethtool_value) */
+#define ETHTOOL_SGRO		0x0000002c /* Set GRO enable (ethtool_value) */
+#define ETHTOOL_GRXRINGS	0x0000002d /* Get RX rings available for LB */
+#define ETHTOOL_GRXCLSRLCNT	0x0000002e /* Get RX class rule count */
+#define ETHTOOL_GRXCLSRULE	0x0000002f /* Get RX classification rule */
+#define ETHTOOL_GRXCLSRLALL	0x00000030 /* Get all RX classification rule */
+#define ETHTOOL_SRXCLSRLDEL	0x00000031 /* Delete RX classification rule */
+#define ETHTOOL_SRXCLSRLINS	0x00000032 /* Insert RX classification rule */
+#define ETHTOOL_FLASHDEV	0x00000033 /* Flash firmware to device */
+#define ETHTOOL_RESET		0x00000034 /* Reset hardware */
+#define ETHTOOL_SRXNTUPLE	0x00000035 /* Add an n-tuple filter to device */
+#define ETHTOOL_GRXNTUPLE	0x00000036 /* Get n-tuple filters from device */
+#define ETHTOOL_GSSET_INFO	0x00000037 /* Get string set info */
+#define ETHTOOL_GRXFHINDIR	0x00000038 /* Get RX flow hash indir'n table */
+#define ETHTOOL_SRXFHINDIR	0x00000039 /* Set RX flow hash indir'n table */
+
+#define ETHTOOL_GFEATURES	0x0000003a /* Get device offload settings */
+#define ETHTOOL_SFEATURES	0x0000003b /* Change device offload settings */
+
+/* compatibility with older code */
+#define SPARC_ETH_GSET		ETHTOOL_GSET
+#define SPARC_ETH_SSET		ETHTOOL_SSET
+
+/* Indicates what features are supported by the interface. */
+#define SUPPORTED_10baseT_Half		(1 << 0)
+#define SUPPORTED_10baseT_Full		(1 << 1)
+#define SUPPORTED_100baseT_Half		(1 << 2)
+#define SUPPORTED_100baseT_Full		(1 << 3)
+#define SUPPORTED_1000baseT_Half	(1 << 4)
+#define SUPPORTED_1000baseT_Full	(1 << 5)
+#define SUPPORTED_Autoneg		(1 << 6)
+#define SUPPORTED_TP			(1 << 7)
+#define SUPPORTED_AUI			(1 << 8)
+#define SUPPORTED_MII			(1 << 9)
+#define SUPPORTED_FIBRE			(1 << 10)
+#define SUPPORTED_BNC			(1 << 11)
+#define SUPPORTED_10000baseT_Full	(1 << 12)
+#define SUPPORTED_Pause			(1 << 13)
+#define SUPPORTED_Asym_Pause		(1 << 14)
+#define SUPPORTED_2500baseX_Full	(1 << 15)
+#define SUPPORTED_Backplane		(1 << 16)
+#define SUPPORTED_1000baseKX_Full	(1 << 17)
+#define SUPPORTED_10000baseKX4_Full	(1 << 18)
+#define SUPPORTED_10000baseKR_Full	(1 << 19)
+#define SUPPORTED_10000baseR_FEC	(1 << 20)
+#define SUPPORTED_1000baseX_Half	(1 << 21)
+#define SUPPORTED_1000baseX_Full	(1 << 22)
+
+/* Indicates what features are advertised by the interface. */
+#define ADVERTISED_10baseT_Half		(1 << 0)
+#define ADVERTISED_10baseT_Full		(1 << 1)
+#define ADVERTISED_100baseT_Half	(1 << 2)
+#define ADVERTISED_100baseT_Full	(1 << 3)
+#define ADVERTISED_1000baseT_Half	(1 << 4)
+#define ADVERTISED_1000baseT_Full	(1 << 5)
+#define ADVERTISED_Autoneg		(1 << 6)
+#define ADVERTISED_TP			(1 << 7)
+#define ADVERTISED_AUI			(1 << 8)
+#define ADVERTISED_MII			(1 << 9)
+#define ADVERTISED_FIBRE		(1 << 10)
+#define ADVERTISED_BNC			(1 << 11)
+#define ADVERTISED_10000baseT_Full	(1 << 12)
+#define ADVERTISED_Pause		(1 << 13)
+#define ADVERTISED_Asym_Pause		(1 << 14)
+#define ADVERTISED_2500baseX_Full	(1 << 15)
+#define ADVERTISED_Backplane		(1 << 16)
+#define ADVERTISED_1000baseKX_Full	(1 << 17)
+#define ADVERTISED_10000baseKX4_Full	(1 << 18)
+#define ADVERTISED_10000baseKR_Full	(1 << 19)
+#define ADVERTISED_10000baseR_FEC	(1 << 20)
+#define ADVERTISED_1000baseX_Half	(1 << 21)
+#define ADVERTISED_1000baseX_Full	(1 << 22)
+
+/* The following are all involved in forcing a particular link
+ * mode for the device for setting things.  When getting the
+ * devices settings, these indicate the current mode and whether
+ * it was foced up into this mode or autonegotiated.
+ */
+
+/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
+#define SPEED_10		10
+#define SPEED_100		100
+#define SPEED_1000		1000
+#define SPEED_2500		2500
+#define SPEED_10000		10000
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF		0x00
+#define DUPLEX_FULL		0x01
+
+/* Which connector port. */
+#define PORT_TP			0x00
+#define PORT_AUI		0x01
+#define PORT_MII		0x02
+#define PORT_FIBRE		0x03
+#define PORT_BNC		0x04
+#define PORT_DA			0x05
+#define PORT_NONE		0xef
+#define PORT_OTHER		0xff
+
+/* Which transceiver to use. */
+#define XCVR_INTERNAL		0x00
+#define XCVR_EXTERNAL		0x01
+#define XCVR_DUMMY1		0x02
+#define XCVR_DUMMY2		0x03
+#define XCVR_DUMMY3		0x04
+
+/* Enable or disable autonegotiation.  If this is set to enable,
+ * the forced link modes above are completely ignored.
+ */
+#define AUTONEG_DISABLE		0x00
+#define AUTONEG_ENABLE		0x01
+
+/* Mode MDI or MDI-X */
+#define ETH_TP_MDI_INVALID	0x00
+#define ETH_TP_MDI		0x01
+#define ETH_TP_MDI_X		0x02
+
+/* Wake-On-Lan options. */
+#define WAKE_PHY		(1 << 0)
+#define WAKE_UCAST		(1 << 1)
+#define WAKE_MCAST		(1 << 2)
+#define WAKE_BCAST		(1 << 3)
+#define WAKE_ARP		(1 << 4)
+#define WAKE_MAGIC		(1 << 5)
+#define WAKE_MAGICSECURE	(1 << 6) /* only meaningful if WAKE_MAGIC */
+
+/* L2-L4 network traffic flow types */
+#define	TCP_V4_FLOW	0x01	/* hash or spec (tcp_ip4_spec) */
+#define	UDP_V4_FLOW	0x02	/* hash or spec (udp_ip4_spec) */
+#define	SCTP_V4_FLOW	0x03	/* hash or spec (sctp_ip4_spec) */
+#define	AH_ESP_V4_FLOW	0x04	/* hash only */
+#define	TCP_V6_FLOW	0x05	/* hash only */
+#define	UDP_V6_FLOW	0x06	/* hash only */
+#define	SCTP_V6_FLOW	0x07	/* hash only */
+#define	AH_ESP_V6_FLOW	0x08	/* hash only */
+#define	AH_V4_FLOW	0x09	/* hash or spec (ah_ip4_spec) */
+#define	ESP_V4_FLOW	0x0a	/* hash or spec (esp_ip4_spec) */
+#define	AH_V6_FLOW	0x0b	/* hash only */
+#define	ESP_V6_FLOW	0x0c	/* hash only */
+#define	IP_USER_FLOW	0x0d	/* spec only (usr_ip4_spec) */
+#define	IPV4_FLOW	0x10	/* hash only */
+#define	IPV6_FLOW	0x11	/* hash only */
+#define	ETHER_FLOW	0x12	/* spec only (ether_spec) */
+
+/* L3-L4 network traffic flow hash options */
+#define	RXH_L2DA	(1 << 1)
+#define	RXH_VLAN	(1 << 2)
+#define	RXH_L3_PROTO	(1 << 3)
+#define	RXH_IP_SRC	(1 << 4)
+#define	RXH_IP_DST	(1 << 5)
+#define	RXH_L4_B_0_1	(1 << 6) /* src port in case of TCP/UDP/SCTP */
+#define	RXH_L4_B_2_3	(1 << 7) /* dst port in case of TCP/UDP/SCTP */
+#define	RXH_DISCARD	(1 << 31)
+
+#define	RX_CLS_FLOW_DISC	0xffffffffffffffffULL
+
+/* Reset flags */
+/* The reset() operation must clear the flags for the components which
+ * were actually reset.  On successful return, the flags indicate the
+ * components which were not reset, either because they do not exist
+ * in the hardware or because they cannot be reset independently.  The
+ * driver must never reset any components that were not requested.
+ */
+enum ethtool_reset_flags {
+	/* These flags represent components dedicated to the interface
+	 * the command is addressed to.  Shift any flag left by
+	 * ETH_RESET_SHARED_SHIFT to reset a shared component of the
+	 * same type.
+	 */
+	ETH_RESET_MGMT		= 1 << 0,	/* Management processor */
+	ETH_RESET_IRQ		= 1 << 1,	/* Interrupt requester */
+	ETH_RESET_DMA		= 1 << 2,	/* DMA engine */
+	ETH_RESET_FILTER	= 1 << 3,	/* Filtering/flow direction */
+	ETH_RESET_OFFLOAD	= 1 << 4,	/* Protocol offload */
+	ETH_RESET_MAC		= 1 << 5,	/* Media access controller */
+	ETH_RESET_PHY		= 1 << 6,	/* Transceiver/PHY */
+	ETH_RESET_RAM		= 1 << 7,	/* RAM shared between
+						 * multiple components */
+
+	ETH_RESET_DEDICATED	= 0x0000ffff,	/* All components dedicated to
+						 * this interface */
+	ETH_RESET_ALL		= 0xffffffff,	/* All components used by this
+						 * interface, even if shared */
+};
+#define ETH_RESET_SHARED_SHIFT	16
+
+#endif /* _LINUX_ETHTOOL_H */
diff --git a/include/linux/fb.h b/include/linux/fb.h
new file mode 100644
index 0000000..c820a4f
--- /dev/null
+++ b/include/linux/fb.h
@@ -0,0 +1,619 @@
+#ifndef _LINUX_FB_H
+#define _LINUX_FB_H
+
+#include <linux/types.h>
+#include <linux/list.h>
+
+/* Definitions of frame buffers						*/
+
+#define FB_MAX			32	/* sufficient for now */
+
+#define FB_TYPE_PACKED_PIXELS		0	/* Packed Pixels	*/
+
+#define FB_VISUAL_MONO01		0	/* Monochr. 1=Black 0=White */
+#define FB_VISUAL_MONO10		1	/* Monochr. 1=White 0=Black */
+#define FB_VISUAL_TRUECOLOR		2	/* True color	*/
+#define FB_VISUAL_PSEUDOCOLOR		3	/* Pseudo color (like atari) */
+#define FB_VISUAL_DIRECTCOLOR		4	/* Direct color */
+#define FB_VISUAL_STATIC_PSEUDOCOLOR	5	/* Pseudo color readonly */
+
+#define FB_ACCEL_NONE		0	/* no hardware accelerator	*/
+
+struct fb_fix_screeninfo {
+	char id[16];			/* identification string eg "TT Builtin" */
+	unsigned long smem_start;	/* Start of frame buffer mem */
+					/* (physical address) */
+	__u32 smem_len;			/* Length of frame buffer mem */
+	__u32 type;			/* see FB_TYPE_*		*/
+	__u32 type_aux;			/* Interleave for interleaved Planes */
+	__u32 visual;			/* see FB_VISUAL_*		*/
+	__u16 xpanstep;			/* zero if no hardware panning	*/
+	__u16 ypanstep;			/* zero if no hardware panning	*/
+	__u16 ywrapstep;		/* zero if no hardware ywrap	*/
+	__u32 line_length;		/* length of a line in bytes	*/
+	unsigned long mmio_start;	/* Start of Memory Mapped I/O	*/
+					/* (physical address) */
+	__u32 mmio_len;			/* Length of Memory Mapped I/O	*/
+	__u32 accel;			/* Indicate to driver which	*/
+					/*  specific chip/card we have	*/
+	__u16 reserved[3];		/* Reserved for future compatibility */
+};
+
+/*
+ * Interpretation of offset for color fields: All offsets are from the right,
+ * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
+ * can use the offset as right argument to <<). A pixel afterwards is a bit
+ * stream and is written to video memory as that unmodified.
+ *
+ * For pseudocolor: offset and length should be the same for all color
+ * components. Offset specifies the position of the least significant bit
+ * of the pallette index in a pixel value. Length indicates the number
+ * of available palette entries (i.e. # of entries = 1 << length).
+ */
+struct fb_bitfield {
+	__u32 offset;			/* beginning of bitfield	*/
+	__u32 length;			/* length of bitfield		*/
+	__u32 msb_right;
+
+};
+
+#define FB_NONSTD_HAM		1	/* Hold-And-Modify (HAM)	*/
+#define FB_NONSTD_REV_PIX_IN_B	2	/* order of pixels in each byte is reversed */
+
+#define FB_ACTIVATE_NOW		0	/* set values immediately (or vbl)*/
+#define FB_ACTIVATE_NXTOPEN	1	/* activate on next open	*/
+#define FB_ACTIVATE_TEST	2	/* don't set, round up impossible */
+#define FB_ACTIVATE_MASK       15
+					/* values			*/
+#define FB_ACTIVATE_VBL	       16	/* activate values on next vbl	*/
+#define FB_CHANGE_CMAP_VBL     32	/* change colormap on vbl	*/
+#define FB_ACTIVATE_ALL	       64	/* change all VCs on this fb	*/
+#define FB_ACTIVATE_FORCE     128	/* force apply even when no change*/
+#define FB_ACTIVATE_INV_MODE  256	/* invalidate videomode */
+
+#define FB_SYNC_HOR_HIGH_ACT	1	/* horizontal sync high active	*/
+#define FB_SYNC_VERT_HIGH_ACT	2	/* vertical sync high active	*/
+#define FB_SYNC_EXT		4	/* external sync		*/
+#define FB_SYNC_COMP_HIGH_ACT	8	/* composite sync high active	*/
+#define FB_SYNC_BROADCAST	16	/* broadcast video timings	*/
+					/* vtotal = 144d/288n/576i => PAL  */
+					/* vtotal = 121d/242n/484i => NTSC */
+#define FB_SYNC_ON_GREEN	32	/* sync on green */
+
+#define FB_VMODE_NONINTERLACED	0	/* non interlaced */
+#define FB_VMODE_INTERLACED	1	/* interlaced	*/
+#define FB_VMODE_DOUBLE		2	/* double scan */
+#define FB_VMODE_ODD_FLD_FIRST	4	/* interlaced: top line first */
+#define FB_VMODE_MASK		255
+
+#define FB_VMODE_YWRAP		256	/* ywrap instead of panning	*/
+#define FB_VMODE_SMOOTH_XPAN	512	/* smooth xpan possible (internally used) */
+#define FB_VMODE_CONUPDATE	512	/* don't update x/yoffset	*/
+
+/*
+ * Display rotation support
+ */
+#define FB_ROTATE_UR	  0
+#define FB_ROTATE_CW	  1
+#define FB_ROTATE_UD	  2
+#define FB_ROTATE_CCW	  3
+
+#define PICOS2KHZ(a) (1000000000UL/(a))
+#define KHZ2PICOS(a) (1000000000UL/(a))
+
+struct fb_var_screeninfo {
+	__u32 xres;			/* visible resolution		*/
+	__u32 yres;
+	__u32 xres_virtual;		/* virtual resolution		*/
+	__u32 yres_virtual;
+	__u32 xoffset;			/* offset from virtual to visible */
+	__u32 yoffset;			/* resolution			*/
+
+	__u32 bits_per_pixel;		/* guess what			*/
+	__u32 grayscale;		/* != 0 Graylevels instead of colors */
+
+	struct fb_bitfield red;		/* bitfield in fb mem if true color, */
+	struct fb_bitfield green;	/* else only length is significant */
+	struct fb_bitfield blue;
+	struct fb_bitfield transp;	/* transparency			*/
+
+	__u32 nonstd;			/* != 0 Non standard pixel format */
+
+	__u32 activate;			/* see FB_ACTIVATE_*		*/
+
+	__u32 height;			/* height of picture in mm    */
+	__u32 width;			/* width of picture in mm     */
+
+	__u32 accel_flags;		/* (OBSOLETE) see fb_info.flags */
+
+	/* Timing: All values in pixclocks, except pixclock (of course) */
+	__u32 pixclock;			/* pixel clock in ps (pico seconds) */
+	__u32 left_margin;		/* time from sync to picture	*/
+	__u32 right_margin;		/* time from picture to sync	*/
+	__u32 upper_margin;		/* time from sync to picture	*/
+	__u32 lower_margin;
+	__u32 hsync_len;		/* length of horizontal sync	*/
+	__u32 vsync_len;		/* length of vertical sync	*/
+	__u32 sync;			/* see FB_SYNC_*		*/
+	__u32 vmode;			/* see FB_VMODE_*		*/
+	__u32 rotate;			/* angle we rotate counter clockwise */
+	__u32 reserved[5];		/* Reserved for future compatibility */
+};
+
+struct fb_cmap {
+	__u32 start;			/* First entry	*/
+	__u32 len;			/* Number of entries */
+	__u16 *red;			/* Red values	*/
+	__u16 *green;
+	__u16 *blue;
+	__u16 *transp;			/* transparency, can be NULL */
+};
+
+struct fb_con2fbmap {
+	__u32 console;
+	__u32 framebuffer;
+};
+
+/* VESA Blanking Levels */
+#define VESA_NO_BLANKING	0
+#define VESA_VSYNC_SUSPEND	1
+#define VESA_HSYNC_SUSPEND	2
+#define VESA_POWERDOWN		3
+
+
+enum {
+	/* screen: unblanked, hsync: on,  vsync: on */
+	FB_BLANK_UNBLANK       = VESA_NO_BLANKING,
+
+	/* screen: blanked,   hsync: on,  vsync: on */
+	FB_BLANK_NORMAL        = VESA_NO_BLANKING + 1,
+
+	/* screen: blanked,   hsync: on,  vsync: off */
+	FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
+
+	/* screen: blanked,   hsync: off, vsync: on */
+	FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
+
+	/* screen: blanked,   hsync: off, vsync: off */
+	FB_BLANK_POWERDOWN     = VESA_POWERDOWN + 1
+};
+
+#define FB_VBLANK_VBLANKING	0x001	/* currently in a vertical blank */
+#define FB_VBLANK_HBLANKING	0x002	/* currently in a horizontal blank */
+#define FB_VBLANK_HAVE_VBLANK	0x004	/* vertical blanks can be detected */
+#define FB_VBLANK_HAVE_HBLANK	0x008	/* horizontal blanks can be detected */
+#define FB_VBLANK_HAVE_COUNT	0x010	/* global retrace counter is available */
+#define FB_VBLANK_HAVE_VCOUNT	0x020	/* the vcount field is valid */
+#define FB_VBLANK_HAVE_HCOUNT	0x040	/* the hcount field is valid */
+#define FB_VBLANK_VSYNCING	0x080	/* currently in a vsync */
+#define FB_VBLANK_HAVE_VSYNC	0x100	/* verical syncs can be detected */
+
+struct fb_vblank {
+	__u32 flags;			/* FB_VBLANK flags */
+	__u32 count;			/* counter of retraces since boot */
+	__u32 vcount;			/* current scanline position */
+	__u32 hcount;			/* current scandot position */
+	__u32 reserved[4];		/* reserved for future compatibility */
+};
+
+/* Internal HW accel */
+#define ROP_COPY 0
+#define ROP_XOR  1
+
+struct fb_copyarea {
+	__u32 dx;
+	__u32 dy;
+	__u32 width;
+	__u32 height;
+	__u32 sx;
+	__u32 sy;
+};
+
+struct fb_fillrect {
+	__u32 dx;	/* screen-relative */
+	__u32 dy;
+	__u32 width;
+	__u32 height;
+	__u32 color;
+	__u32 rop;
+};
+
+struct fb_image {
+	__u32 dx;		/* Where to place image */
+	__u32 dy;
+	__u32 width;		/* Size of image */
+	__u32 height;
+	__u32 fg_color;		/* Only used when a mono bitmap */
+	__u32 bg_color;
+	__u8  depth;		/* Depth of the image */
+	const char *data;	/* Pointer to image data */
+	struct fb_cmap cmap;	/* color map info */
+};
+
+/*
+ * hardware cursor control
+ */
+
+#define FB_CUR_SETIMAGE 0x01
+#define FB_CUR_SETPOS	0x02
+#define FB_CUR_SETHOT	0x04
+#define FB_CUR_SETCMAP	0x08
+#define FB_CUR_SETSHAPE 0x10
+#define FB_CUR_SETSIZE	0x20
+#define FB_CUR_SETALL	0xFF
+
+struct fbcurpos {
+	__u16 x, y;
+};
+
+struct fb_cursor {
+	__u16 set;		/* what to set */
+	__u16 enable;		/* cursor on/off */
+	__u16 rop;		/* bitop operation */
+	const char *mask;	/* cursor mask bits */
+	struct fbcurpos hot;	/* cursor hot spot */
+	struct fb_image	image;	/* Cursor image */
+};
+
+#ifdef CONFIG_FB_BACKLIGHT
+/* Settings for the generic backlight code */
+#define FB_BACKLIGHT_LEVELS	128
+#define FB_BACKLIGHT_MAX	0xFF
+#endif
+
+#ifdef __KERNEL__
+
+struct vm_area_struct;
+struct fb_info;
+struct device;
+struct file;
+
+/* Definitions below are used in the parsed monitor specs */
+#define FB_DPMS_ACTIVE_OFF	1
+#define FB_DPMS_SUSPEND		2
+#define FB_DPMS_STANDBY		4
+
+#define FB_DISP_DDI		1
+#define FB_DISP_ANA_700_300	2
+#define FB_DISP_ANA_714_286	4
+#define FB_DISP_ANA_1000_400	8
+#define FB_DISP_ANA_700_000	16
+
+#define FB_DISP_MONO		32
+#define FB_DISP_RGB		64
+#define FB_DISP_MULTI		128
+#define FB_DISP_UNKNOWN		256
+
+#define FB_SIGNAL_NONE		0
+#define FB_SIGNAL_BLANK_BLANK	1
+#define FB_SIGNAL_SEPARATE	2
+#define FB_SIGNAL_COMPOSITE	4
+#define FB_SIGNAL_SYNC_ON_GREEN	8
+#define FB_SIGNAL_SERRATION_ON	16
+
+#define FB_MISC_PRIM_COLOR	1
+#define FB_MISC_1ST_DETAIL	2	/* First Detailed Timing is preferred */
+struct fb_chroma {
+	__u32 redx;	/* in fraction of 1024 */
+	__u32 greenx;
+	__u32 bluex;
+	__u32 whitex;
+	__u32 redy;
+	__u32 greeny;
+	__u32 bluey;
+	__u32 whitey;
+};
+
+struct fb_monspecs {
+	struct fb_chroma chroma;
+	struct fb_videomode *modedb;	/* mode database */
+	__u8  manufacturer[4];		/* Manufacturer */
+	__u8  monitor[14];		/* Monitor String */
+	__u8  serial_no[14];		/* Serial Number */
+	__u8  ascii[14];		/* ? */
+	__u32 modedb_len;		/* mode database length */
+	__u32 model;			/* Monitor Model */
+	__u32 serial;			/* Serial Number - Integer */
+	__u32 year;			/* Year manufactured */
+	__u32 week;			/* Week Manufactured */
+	__u32 hfmin;			/* hfreq lower limit (Hz) */
+	__u32 hfmax;			/* hfreq upper limit (Hz) */
+	__u32 dclkmin;			/* pixelclock lower limit (Hz) */
+	__u32 dclkmax;			/* pixelclock upper limit (Hz) */
+	__u16 input;			/* display type - see FB_DISP_* */
+	__u16 dpms;			/* DPMS support - see FB_DPMS_ */
+	__u16 signal;			/* Signal Type - see FB_SIGNAL_* */
+	__u16 vfmin;			/* vfreq lower limit (Hz) */
+	__u16 vfmax;			/* vfreq upper limit (Hz) */
+	__u16 gamma;			/* Gamma - in fractions of 100 */
+	__u16 gtf	: 1;		/* supports GTF */
+	__u16 misc;			/* Misc flags - see FB_MISC_* */
+	__u8  version;			/* EDID version... */
+	__u8  revision;			/* ...and revision */
+	__u8  max_x;			/* Maximum horizontal size (cm) */
+	__u8  max_y;			/* Maximum vertical size (cm) */
+};
+
+struct fb_cmap_user {
+	__u32 start;			/* First entry	*/
+	__u32 len;			/* Number of entries */
+	__u16 *red;		/* Red values	*/
+	__u16 *green;
+	__u16 *blue;
+	__u16 *transp;		/* transparency, can be NULL */
+};
+
+struct fb_image_user {
+	__u32 dx;			/* Where to place image */
+	__u32 dy;
+	__u32 width;			/* Size of image */
+	__u32 height;
+	__u32 fg_color;			/* Only used when a mono bitmap */
+	__u32 bg_color;
+	__u8  depth;			/* Depth of the image */
+	const char *data;	/* Pointer to image data */
+	struct fb_cmap_user cmap;	/* color map info */
+};
+
+struct fb_cursor_user {
+	__u16 set;			/* what to set */
+	__u16 enable;			/* cursor on/off */
+	__u16 rop;			/* bitop operation */
+	const char *mask;	/* cursor mask bits */
+	struct fbcurpos hot;		/* cursor hot spot */
+	struct fb_image_user image;	/* Cursor image */
+};
+
+/*
+ * Register/unregister for framebuffer events
+ */
+
+/*	The resolution of the passed in fb_info about to change */
+#define FB_EVENT_MODE_CHANGE		0x01
+/*	The display on this fb_info is beeing suspended, no access to the
+ *	framebuffer is allowed any more after that call returns
+ */
+#define FB_EVENT_SUSPEND		0x02
+/*	The display on this fb_info was resumed, you can restore the display
+ *	if you own it
+ */
+#define FB_EVENT_RESUME			0x03
+/*	An entry from the modelist was removed */
+#define FB_EVENT_MODE_DELETE		0x04
+/*	A driver registered itself */
+#define FB_EVENT_FB_REGISTERED		0x05
+/*	A driver unregistered itself */
+#define FB_EVENT_FB_UNREGISTERED	0x06
+/*	CONSOLE-SPECIFIC: get console to framebuffer mapping */
+#define FB_EVENT_GET_CONSOLE_MAP	0x07
+/*	CONSOLE-SPECIFIC: set console to framebuffer mapping */
+#define FB_EVENT_SET_CONSOLE_MAP	0x08
+/*	A hardware display blank change occurred */
+#define FB_EVENT_BLANK			0x09
+/*	Private modelist is to be replaced */
+#define FB_EVENT_NEW_MODELIST		0x0A
+/*	The resolution of the passed in fb_info about to change and
+	all vc's should be changed	   */
+#define FB_EVENT_MODE_CHANGE_ALL	0x0B
+/*	A software display blank change occurred */
+#define FB_EVENT_CONBLANK		0x0C
+/*	Get drawing requirements	*/
+#define FB_EVENT_GET_REQ		0x0D
+/*	Unbind from the console if possible */
+#define FB_EVENT_FB_UNBIND		0x0E
+
+struct fb_event {
+	struct fb_info *info;
+	void *data;
+};
+
+struct fb_blit_caps {
+	u32 x;
+	u32 y;
+	u32 len;
+	u32 flags;
+};
+
+/*
+ * Pixmap structure definition
+ *
+ * The purpose of this structure is to translate data
+ * from the hardware independent format of fbdev to what
+ * format the hardware needs.
+ */
+
+#define FB_PIXMAP_DEFAULT 1	/* used internally by fbcon */
+#define FB_PIXMAP_SYSTEM  2	/* memory is in system RAM  */
+#define FB_PIXMAP_IO	  4	/* memory is iomapped	    */
+#define FB_PIXMAP_SYNC	  256	/* set if GPU can DMA	    */
+
+struct fb_pixmap {
+	u8  *addr;		/* pointer to memory			*/
+	u32 size;		/* size of buffer in bytes		*/
+	u32 offset;		/* current offset to buffer		*/
+	u32 buf_align;		/* byte alignment of each bitmap	*/
+	u32 scan_align;		/* alignment per scanline		*/
+	u32 access_align;	/* alignment per read/write (bits)	*/
+	u32 flags;		/* see FB_PIXMAP_*			*/
+	u32 blit_x;		/* supported bit block dimensions (1-32)*/
+	u32 blit_y;		/* Format: blit_x = 1 << (width - 1)	*/
+				/*	   blit_y = 1 << (height - 1)	*/
+				/* if 0, will be set to 0xffffffff (all)*/
+	/* access methods */
+	void (*writeio)(struct fb_info *info, void *dst, void *src, unsigned int size);
+	void (*readio) (struct fb_info *info, void *dst, void *src, unsigned int size);
+};
+
+#ifdef CONFIG_FB_DEFERRED_IO
+struct fb_deferred_io {
+	/* delay between mkwrite and deferred handler */
+	unsigned long delay;
+	struct mutex lock; /* mutex that protects the page list */
+	struct list_head pagelist; /* list of touched pages */
+	/* callback */
+	void (*deferred_io)(struct fb_info *info, struct list_head *pagelist);
+};
+#endif
+
+/* FBINFO_* = fb_info.flags bit flags */
+#define FBINFO_MODULE		0x0001	/* Low-level driver is a module */
+#define FBINFO_HWACCEL_DISABLED	0x0002
+	/* When FBINFO_HWACCEL_DISABLED is set:
+	 *  Hardware acceleration is turned off.  Software implementations
+	 *  of required functions (copyarea(), fillrect(), and imageblit())
+	 *  takes over; acceleration engine should be in a quiescent state */
+
+/* hints */
+#define FBINFO_PARTIAL_PAN_OK	0x0040 /* otw use pan only for double-buffering */
+#define FBINFO_READS_FAST	0x0080 /* soft-copy faster than rendering */
+
+/*
+ * A driver may set this flag to indicate that it does want a set_par to be
+ * called every time when fbcon_switch is executed. The advantage is that with
+ * this flag set you can really be sure that set_par is always called before
+ * any of the functions dependant on the correct hardware state or altering
+ * that state, even if you are using some broken X releases. The disadvantage
+ * is that it introduces unwanted delays to every console switch if set_par
+ * is slow. It is a good idea to try this flag in the drivers initialization
+ * code whenever there is a bug report related to switching between X and the
+ * framebuffer console.
+ */
+#define FBINFO_MISC_ALWAYS_SETPAR   0x40000
+
+/*
+ * Host and GPU endianness differ.
+ */
+#define FBINFO_FOREIGN_ENDIAN	0x100000
+/*
+ * Big endian math. This is the same flags as above, but with different
+ * meaning, it is set by the fb subsystem depending FOREIGN_ENDIAN flag
+ * and host endianness. Drivers should not use this flag.
+ */
+#define FBINFO_BE_MATH	0x100000
+
+struct fb_info {
+	int node;
+	int flags;
+	struct fb_var_screeninfo var;	/* Current var */
+	struct fb_fix_screeninfo fix;	/* Current fix */
+	struct fb_monspecs monspecs;	/* Current Monitor specs */
+	struct fb_pixmap pixmap;	/* Image hardware mapper */
+	struct fb_pixmap sprite;	/* Cursor hardware mapper */
+	struct fb_cmap cmap;		/* Current cmap */
+	struct list_head modelist;	/* mode list */
+	struct fb_videomode *mode;	/* current mode */
+
+	char *screen_base;	/* Virtual address */
+	unsigned long screen_size;	/* Amount of ioremapped VRAM or 0 */
+	void *pseudo_palette;		/* Fake palette of 16 colors */
+#define FBINFO_STATE_RUNNING	0
+#define FBINFO_STATE_SUSPENDED	1
+	u32 state;			/* Hardware state i.e suspend */
+	void *fbcon_par;		/* fbcon use-only private area */
+	/* From here on everything is device dependent */
+	void *par;
+};
+
+#define FBINFO_DEFAULT	0
+
+#define FBINFO_FLAG_MODULE	FBINFO_MODULE
+#define FBINFO_FLAG_DEFAULT	FBINFO_DEFAULT
+
+/* This will go away */
+#if defined(__sparc__)
+
+/* We map all of our framebuffers such that big-endian accesses
+ * are what we want, so the following is sufficient.
+ */
+
+/* This will go away */
+#define fb_readb sbus_readb
+#define fb_readw sbus_readw
+#define fb_readl sbus_readl
+#define fb_readq sbus_readq
+#define fb_writeb sbus_writeb
+#define fb_writew sbus_writew
+#define fb_writel sbus_writel
+#define fb_writeq sbus_writeq
+#define fb_memset sbus_memset_io
+
+#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || defined(__sh__) || defined(__powerpc__) || defined(__bfin__)
+
+#define fb_readb __raw_readb
+#define fb_readw __raw_readw
+#define fb_readl __raw_readl
+#define fb_readq __raw_readq
+#define fb_writeb __raw_writeb
+#define fb_writew __raw_writew
+#define fb_writel __raw_writel
+#define fb_writeq __raw_writeq
+#define fb_memset memset_io
+
+#else
+
+#define fb_readb(addr) (*(volatile u8 *) (addr))
+#define fb_readw(addr) (*(volatile u16 *) (addr))
+#define fb_readl(addr) (*(volatile u32 *) (addr))
+#define fb_readq(addr) (*(volatile u64 *) (addr))
+#define fb_writeb(b,addr) (*(volatile u8 *) (addr) = (b))
+#define fb_writew(b,addr) (*(volatile u16 *) (addr) = (b))
+#define fb_writel(b,addr) (*(volatile u32 *) (addr) = (b))
+#define fb_writeq(b,addr) (*(volatile u64 *) (addr) = (b))
+#define fb_memset memset
+
+#endif
+
+#define FB_LEFT_POS(p, bpp)	     (fb_be_math(p) ? (32 - (bpp)) : 0)
+#define FB_SHIFT_HIGH(p, val, bits)  (fb_be_math(p) ? (val) >> (bits) : \
+						      (val) << (bits))
+#define FB_SHIFT_LOW(p, val, bits)   (fb_be_math(p) ? (val) << (bits) : \
+						      (val) >> (bits))
+/* drivers/video/fbmon.c */
+#define FB_MAXTIMINGS		0
+#define FB_VSYNCTIMINGS		1
+#define FB_HSYNCTIMINGS		2
+#define FB_DCLKTIMINGS		3
+#define FB_IGNOREMON		0x100
+
+#define FB_MODE_IS_UNKNOWN	0
+#define FB_MODE_IS_DETAILED	1
+#define FB_MODE_IS_STANDARD	2
+#define FB_MODE_IS_VESA		4
+#define FB_MODE_IS_CALCULATED	8
+#define FB_MODE_IS_FIRST	16
+#define FB_MODE_IS_FROM_VAR	32
+
+
+/* drivers/video/fbcmap.c */
+
+extern int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp);
+extern void fb_dealloc_cmap(struct fb_cmap *cmap);
+extern int fb_copy_cmap(const struct fb_cmap *from, struct fb_cmap *to);
+extern int fb_cmap_to_user(const struct fb_cmap *from, struct fb_cmap_user *to);
+extern int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *fb_info);
+extern int fb_set_user_cmap(struct fb_cmap_user *cmap, struct fb_info *fb_info);
+extern const struct fb_cmap *fb_default_cmap(int len);
+extern void fb_invert_cmaps(void);
+
+struct fb_videomode {
+	const char *name;	/* optional */
+	u32 refresh;		/* optional */
+	u32 xres;
+	u32 yres;
+	u32 pixclock;
+	u32 left_margin;
+	u32 right_margin;
+	u32 upper_margin;
+	u32 lower_margin;
+	u32 hsync_len;
+	u32 vsync_len;
+	u32 sync;
+	u32 vmode;
+	u32 flag;
+};
+
+int board_video_skip(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _LINUX_FB_H */
diff --git a/include/linux/if_ether.h b/include/linux/if_ether.h
new file mode 100644
index 0000000..0d62aef
--- /dev/null
+++ b/include/linux/if_ether.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
+/*
+ * INET		An implementation of the TCP/IP protocol suite for the LINUX
+ *		operating system.  INET is implemented using the  BSD Socket
+ *		interface as the means of communication with the user level.
+ *
+ *		Global definitions for the Ethernet IEEE 802.3 interface.
+ *
+ * Version:	@(#)if_ether.h	1.0.1a	02/08/94
+ *
+ * Author:	Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
+ *		Donald Becker, <becker@super.org>
+ *		Alan Cox, <alan@lxorguk.ukuu.org.uk>
+ *		Steve Whitehouse, <gw7rrm@eeshack3.swan.ac.uk>
+ *
+ *		This program is free software; you can redistribute it and/or
+ *		modify it under the terms of the GNU General Public License
+ *		as published by the Free Software Foundation; either version
+ *		2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _UAPI_LINUX_IF_ETHER_H
+#define _UAPI_LINUX_IF_ETHER_H
+
+#include <linux/types.h>
+
+/*
+ *	IEEE 802.3 Ethernet magic constants.  The frame sizes omit the preamble
+ *	and FCS/CRC (frame check sequence).
+ */
+
+#define ETH_ALEN	6	/* Octets in one ethernet addr   */
+#define ETH_TLEN	2	/* Octets in ethernet type field */
+#define ETH_HLEN	14	/* Total octets in header.       */
+#define ETH_ZLEN	60	/* Min. octets in frame sans FCS */
+#define ETH_DATA_LEN	1500	/* Max. octets in payload        */
+#define ETH_FRAME_LEN	1514	/* Max. octets in frame sans FCS */
+#define ETH_FCS_LEN	4	/* Octets in the FCS             */
+
+#define ETH_MIN_MTU	68	/* Min IPv4 MTU per RFC791       */
+#define ETH_MAX_MTU	0xFFFFU	/* 65535, same as IP_MAX_MTU     */
+
+/*
+ *	These are the defined Ethernet Protocol ID's.
+ */
+
+#define ETH_P_LOOP	0x0060	/* Ethernet Loopback packet     */
+#define ETH_P_PUP	0x0200	/* Xerox PUP packet             */
+#define ETH_P_PUPAT	0x0201	/* Xerox PUP Addr Trans packet  */
+#define ETH_P_TSN	0x22F0	/* TSN (IEEE 1722) packet       */
+#define ETH_P_ERSPAN2	0x22EB	/* ERSPAN version 2 (type III)  */
+#define ETH_P_IP	0x0800	/* Internet Protocol packet     */
+#define ETH_P_X25	0x0805	/* CCITT X.25                   */
+#define ETH_P_ARP	0x0806	/* Address Resolution packet    */
+#define ETH_P_BPQ	0x08FF	/* G8BPQ AX.25 Ethernet Packet  */
+				/* [ NOT AN OFFICIALLY REGISTERED ID ] */
+#define ETH_P_IEEEPUP	0x0a00	/* Xerox IEEE802.3 PUP packet   */
+#define ETH_P_IEEEPUPAT	0x0a01	/* Xerox IEEE802.3 PUP Addr Trans packet */
+#define ETH_P_BATMAN	0x4305	/* B.A.T.M.A.N.-Advanced packet */
+				/* [ NOT AN OFFICIALLY REGISTERED ID ] */
+#define ETH_P_DEC	0x6000	/* DEC Assigned proto           */
+#define ETH_P_DNA_DL	0x6001	/* DEC DNA Dump/Load            */
+#define ETH_P_DNA_RC	0x6002	/* DEC DNA Remote Console       */
+#define ETH_P_DNA_RT	0x6003	/* DEC DNA Routing              */
+#define ETH_P_LAT	0x6004	/* DEC LAT                      */
+#define ETH_P_DIAG	0x6005	/* DEC Diagnostics              */
+#define ETH_P_CUST	0x6006	/* DEC Customer use             */
+#define ETH_P_SCA	0x6007	/* DEC Systems Comms Arch       */
+#define ETH_P_TEB	0x6558	/* Trans Ether Bridging         */
+#define ETH_P_RARP	0x8035	/* Reverse Addr Res packet      */
+#define ETH_P_ATALK	0x809B	/* Appletalk DDP                */
+#define ETH_P_AARP	0x80F3	/* Appletalk AARP               */
+#define ETH_P_8021Q	0x8100	/* 802.1Q VLAN Extended Header  */
+#define ETH_P_ERSPAN	0x88BE	/* ERSPAN type II               */
+#define ETH_P_IPX	0x8137	/* IPX over DIX                 */
+#define ETH_P_IPV6	0x86DD	/* IPv6 over bluebook           */
+#define ETH_P_PAUSE	0x8808	/* IEEE Pause frames. See 802.3 31B */
+#define ETH_P_SLOW	0x8809	/* Slow Protocol. See 802.3ad 43B */
+#define ETH_P_WCCP	0x883E	/* Web-cache coordination */
+				/* protocol defined in */
+				/* draft-wilson-wrec-wccp-v2-00.txt */
+#define ETH_P_MPLS_UC	0x8847	/* MPLS Unicast traffic         */
+#define ETH_P_MPLS_MC	0x8848	/* MPLS Multicast traffic       */
+#define ETH_P_ATMMPOA	0x884c	/* MultiProtocol Over ATM       */
+#define ETH_P_PPP_DISC	0x8863	/* PPPoE discovery messages     */
+#define ETH_P_PPP_SES	0x8864	/* PPPoE session messages       */
+#define ETH_P_LINK_CTL	0x886c	/* HPNA, wlan link local tunnel */
+#define ETH_P_ATMFATE	0x8884	/* Frame-based ATM Transport over Ethernet */
+#define ETH_P_PAE	0x888E	/* Port Access Entity (IEEE 802.1X) */
+#define ETH_P_AOE	0x88A2	/* ATA over Ethernet            */
+#define ETH_P_8021AD	0x88A8	/* 802.1ad Service VLAN         */
+#define ETH_P_802_EX1	0x88B5	/* 802.1 Local Experimental 1.  */
+#define ETH_P_PREAUTH	0x88C7	/* 802.11 Preauthentication     */
+#define ETH_P_TIPC	0x88CA	/* TIPC                         */
+#define ETH_P_MACSEC	0x88E5	/* 802.1ae MACsec               */
+#define ETH_P_8021AH	0x88E7	/* 802.1ah Backbone Service Tag */
+#define ETH_P_MVRP	0x88F5	/* 802.1Q MVRP                  */
+#define ETH_P_1588	0x88F7	/* IEEE 1588 Timesync           */
+#define ETH_P_NCSI	0x88F8	/* NCSI protocol                */
+#define ETH_P_PRP	0x88FB	/* IEC 62439-3 PRP/HSRv0        */
+#define ETH_P_FCOE	0x8906	/* Fibre Channel over Ethernet  */
+#define ETH_P_IBOE	0x8915	/* Infiniband over Ethernet     */
+#define ETH_P_TDLS	0x890D	/* TDLS                         */
+#define ETH_P_FIP	0x8914	/* FCoE Initialization Protocol */
+#define ETH_P_80221	0x8917	/* IEEE 802.21 Media Independent */
+				/* Handover Protocol            */
+#define ETH_P_HSR	0x892F	/* IEC 62439-3 HSRv1            */
+#define ETH_P_NSH	0x894F	/* Network Service Header       */
+#define ETH_P_LOOPBACK	0x9000	/* Ethernet loopback packet, per IEEE 802.3 */
+#define ETH_P_QINQ1	0x9100	/* deprecated QinQ VLAN         */
+				/* [ NOT AN OFFICIALLY REGISTERED ID ] */
+#define ETH_P_QINQ2	0x9200	/* deprecated QinQ VLAN         */
+				/* [ NOT AN OFFICIALLY REGISTERED ID ] */
+#define ETH_P_QINQ3	0x9300	/* deprecated QinQ VLAN]        */
+				/* [ NOT AN OFFICIALLY REGISTERED ID ] */
+#define ETH_P_EDSA	0xDADA	/* Ethertype DSA                */
+				/* [ NOT AN OFFICIALLY REGISTERED ID ] */
+#define ETH_P_IFE	0xED3E	/* ForCES inter-FE LFB type     */
+#define ETH_P_AF_IUCV   0xFBFB	/* IBM af_iucv                  */
+				/* [ NOT AN OFFICIALLY REGISTERED ID ] */
+
+#define ETH_P_802_3_MIN	0x0600	/* If the value in the ethernet type is less */
+				/* than this value then the frame is Ethernet */
+				/* II. Else it is 802.3 */
+
+/*
+ *	Non DIX types. Won't clash for 1500 types.
+ */
+
+#define ETH_P_802_3	0x0001	/* Dummy type for 802.3 frames  */
+#define ETH_P_AX25	0x0002	/* Dummy protocol id for AX.25  */
+#define ETH_P_ALL	0x0003	/* Every packet (be careful!!!) */
+#define ETH_P_802_2	0x0004	/* 802.2 frames                 */
+#define ETH_P_SNAP	0x0005	/* Internal only                */
+#define ETH_P_DDCMP	0x0006	/* DEC DDCMP: Internal only     */
+#define ETH_P_WAN_PPP	0x0007	/* Dummy type for WAN PPP frames*/
+#define ETH_P_PPP_MP	0x0008	/* Dummy type for PPP MP frames */
+#define ETH_P_LOCALTALK	0x0009	/* Localtalk pseudo type        */
+#define ETH_P_CAN	0x000C	/* CAN: Controller Area Network */
+#define ETH_P_CANFD	0x000D	/* CANFD: CAN flexible data rate*/
+#define ETH_P_PPPTALK	0x0010	/* Dummy type for Atalk over PPP*/
+#define ETH_P_TR_802_2	0x0011	/* 802.2 frames                 */
+#define ETH_P_MOBITEX	0x0015	/* Mobitex (kaz@cafe.net)       */
+#define ETH_P_CONTROL	0x0016	/* Card specific control frames */
+#define ETH_P_IRDA	0x0017	/* Linux-IrDA                   */
+#define ETH_P_ECONET	0x0018	/* Acorn Econet                 */
+#define ETH_P_HDLC	0x0019	/* HDLC frames                  */
+#define ETH_P_ARCNET	0x001A	/* 1A for ArcNet :-)            */
+#define ETH_P_DSA	0x001B	/* Distributed Switch Arch      */
+#define ETH_P_TRAILER	0x001C	/* Trailer switch tagging       */
+#define ETH_P_PHONET	0x00F5	/* Nokia Phonet frames          */
+#define ETH_P_IEEE802154 0x00F6	/* IEEE802.15.4 frame           */
+#define ETH_P_CAIF	0x00F7	/* ST-Ericsson CAIF protocol    */
+#define ETH_P_XDSA	0x00F8	/* Multiplexed DSA protocol     */
+#define ETH_P_MAP	0x00F9	/* Qualcomm multiplexing and    */
+				/* aggregation protocol         */
+
+/* The following macros come from Linux kernel include/linux/if_vlan.h */
+
+#define VLAN_HLEN	4	/* The additional bytes required by VLAN */
+				/* (in addition to the Ethernet header)  */
+#define VLAN_ETH_HLEN	18	/* Total octets in header.               */
+#define VLAN_ETH_ZLEN	64	/* Min. octets in frame sans FCS         */
+
+/*
+ * According to 802.3ac, the packet can be 4 bytes longer. --Klika Jan
+ */
+#define VLAN_ETH_DATA_LEN	1500	/* Max. octets in payload        */
+#define VLAN_ETH_FRAME_LEN	1518	/* Max. octets in frame sans FCS */
+
+#define VLAN_PRIO_MASK		0xe000	/* Priority Code Point           */
+#define VLAN_PRIO_SHIFT		13
+#define VLAN_CFI_MASK		0x1000	/* Canonical Format Indicator    */
+#define VLAN_TAG_PRESENT	VLAN_CFI_MASK
+#define VLAN_VID_MASK		0x0fff	/* VLAN Identifier               */
+#define VLAN_N_VID		4096
+
+#endif /* _UAPI_LINUX_IF_ETHER_H */
diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h
new file mode 100644
index 0000000..022771f
--- /dev/null
+++ b/include/linux/immap_qe.h
@@ -0,0 +1,593 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * QUICC Engine (QE) Internal Memory Map.
+ * The Internal Memory Map for devices with QE on them. This
+ * is the superset of all QE devices (8360, etc.).
+ *
+ * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc.
+ * Author: Shlomi Gridih <gridish@freescale.com>
+ */
+
+#ifndef __IMMAP_QE_H__
+#define __IMMAP_QE_H__
+
+#ifdef CONFIG_MPC83xx
+#if defined(CONFIG_ARCH_MPC8360)
+#define QE_MURAM_SIZE		0xc000UL
+#define MAX_QE_RISC		2
+#define QE_NUM_OF_SNUM		28
+#elif defined(CONFIG_ARCH_MPC832X) || defined(CONFIG_ARCH_MPC8309)
+#define QE_MURAM_SIZE		0x4000UL
+#define MAX_QE_RISC		1
+#define QE_NUM_OF_SNUM		28
+#endif
+#endif
+
+#ifdef CONFIG_ARCH_LS1021A
+#define QE_MURAM_SIZE          0x6000UL
+#define MAX_QE_RISC            1
+#define QE_NUM_OF_SNUM         28
+#endif
+
+#ifdef CONFIG_PPC
+#define QE_IMMR_OFFSET		0x00140000
+#else
+#define QE_IMMR_OFFSET		0x01400000
+#endif
+
+/* QE I-RAM */
+typedef struct qe_iram {
+	u32 iadd;		/* I-RAM Address Register */
+	u32 idata;		/* I-RAM Data Register    */
+	u8 res0[0x4];
+	u32 iready;
+	u8 res1[0x70];
+} __attribute__ ((packed)) qe_iram_t;
+
+/* QE Interrupt Controller */
+typedef struct qe_ic {
+	u32 qicr;
+	u32 qivec;
+	u32 qripnr;
+	u32 qipnr;
+	u32 qipxcc;
+	u32 qipycc;
+	u32 qipwcc;
+	u32 qipzcc;
+	u32 qimr;
+	u32 qrimr;
+	u32 qicnr;
+	u8 res0[0x4];
+	u32 qiprta;
+	u32 qiprtb;
+	u8 res1[0x4];
+	u32 qricr;
+	u8 res2[0x20];
+	u32 qhivec;
+	u8 res3[0x1C];
+} __attribute__ ((packed)) qe_ic_t;
+
+/* Communications Processor */
+typedef struct cp_qe {
+	u32 cecr;		/* QE command register */
+	u32 ceccr;		/* QE controller configuration register */
+	u32 cecdr;		/* QE command data register */
+	u8 res0[0xA];
+	u16 ceter;		/* QE timer event register */
+	u8 res1[0x2];
+	u16 cetmr;		/* QE timers mask register */
+	u32 cetscr;		/* QE time-stamp timer control register */
+	u32 cetsr1;		/* QE time-stamp register 1 */
+	u32 cetsr2;		/* QE time-stamp register 2 */
+	u8 res2[0x8];
+	u32 cevter;		/* QE virtual tasks event register */
+	u32 cevtmr;		/* QE virtual tasks mask register */
+	u16 cercr;		/* QE RAM control register */
+	u8 res3[0x2];
+	u8 res4[0x24];
+	u16 ceexe1;		/* QE external request 1 event register */
+	u8 res5[0x2];
+	u16 ceexm1;		/* QE external request 1 mask register */
+	u8 res6[0x2];
+	u16 ceexe2;		/* QE external request 2 event register */
+	u8 res7[0x2];
+	u16 ceexm2;		/* QE external request 2 mask register */
+	u8 res8[0x2];
+	u16 ceexe3;		/* QE external request 3 event register */
+	u8 res9[0x2];
+	u16 ceexm3;		/* QE external request 3 mask register */
+	u8 res10[0x2];
+	u16 ceexe4;		/* QE external request 4 event register */
+	u8 res11[0x2];
+	u16 ceexm4;		/* QE external request 4 mask register */
+	u8 res12[0x2];
+	u8 res13[0x280];
+} __attribute__ ((packed)) cp_qe_t;
+
+/* QE Multiplexer */
+typedef struct qe_mux {
+	u32 cmxgcr;		/* CMX general clock route register    */
+	u32 cmxsi1cr_l;		/* CMX SI1 clock route low register    */
+	u32 cmxsi1cr_h;		/* CMX SI1 clock route high register   */
+	u32 cmxsi1syr;		/* CMX SI1 SYNC route register         */
+	u32 cmxucr1;		/* CMX UCC1, UCC3 clock route register */
+	u32 cmxucr2;		/* CMX UCC5, UCC7 clock route register */
+	u32 cmxucr3;		/* CMX UCC2, UCC4 clock route register */
+	u32 cmxucr4;		/* CMX UCC6, UCC8 clock route register */
+	u32 cmxupcr;		/* CMX UPC clock route register        */
+	u8 res0[0x1C];
+} __attribute__ ((packed)) qe_mux_t;
+
+/* QE Timers */
+typedef struct qe_timers {
+	u8 gtcfr1;		/* Timer 1 2 global configuration register */
+	u8 res0[0x3];
+	u8 gtcfr2;		/* Timer 3 4 global configuration register */
+	u8 res1[0xB];
+	u16 gtmdr1;		/* Timer 1 mode register */
+	u16 gtmdr2;		/* Timer 2 mode register */
+	u16 gtrfr1;		/* Timer 1 reference register */
+	u16 gtrfr2;		/* Timer 2 reference register */
+	u16 gtcpr1;		/* Timer 1 capture register */
+	u16 gtcpr2;		/* Timer 2 capture register */
+	u16 gtcnr1;		/* Timer 1 counter */
+	u16 gtcnr2;		/* Timer 2 counter */
+	u16 gtmdr3;		/* Timer 3 mode register */
+	u16 gtmdr4;		/* Timer 4 mode register */
+	u16 gtrfr3;		/* Timer 3 reference register */
+	u16 gtrfr4;		/* Timer 4 reference register */
+	u16 gtcpr3;		/* Timer 3 capture register */
+	u16 gtcpr4;		/* Timer 4 capture register */
+	u16 gtcnr3;		/* Timer 3 counter */
+	u16 gtcnr4;		/* Timer 4 counter */
+	u16 gtevr1;		/* Timer 1 event register */
+	u16 gtevr2;		/* Timer 2 event register */
+	u16 gtevr3;		/* Timer 3 event register */
+	u16 gtevr4;		/* Timer 4 event register */
+	u16 gtps;		/* Timer 1 prescale register */
+	u8 res2[0x46];
+} __attribute__ ((packed)) qe_timers_t;
+
+/* BRG */
+typedef struct qe_brg {
+	u32 brgc1;		/* BRG1 configuration register  */
+	u32 brgc2;		/* BRG2 configuration register  */
+	u32 brgc3;		/* BRG3 configuration register  */
+	u32 brgc4;		/* BRG4 configuration register  */
+	u32 brgc5;		/* BRG5 configuration register  */
+	u32 brgc6;		/* BRG6 configuration register  */
+	u32 brgc7;		/* BRG7 configuration register  */
+	u32 brgc8;		/* BRG8 configuration register  */
+	u32 brgc9;		/* BRG9 configuration register  */
+	u32 brgc10;		/* BRG10 configuration register */
+	u32 brgc11;		/* BRG11 configuration register */
+	u32 brgc12;		/* BRG12 configuration register */
+	u32 brgc13;		/* BRG13 configuration register */
+	u32 brgc14;		/* BRG14 configuration register */
+	u32 brgc15;		/* BRG15 configuration register */
+	u32 brgc16;		/* BRG16 configuration register */
+	u8 res0[0x40];
+} __attribute__ ((packed)) qe_brg_t;
+
+/* SPI */
+typedef struct spi {
+	u8 res0[0x20];
+	u32 spmode;		/* SPI mode register */
+	u8 res1[0x2];
+	u8 spie;		/* SPI event register */
+	u8 res2[0x1];
+	u8 res3[0x2];
+	u8 spim;		/* SPI mask register */
+	u8 res4[0x1];
+	u8 res5[0x1];
+	u8 spcom;		/* SPI command register  */
+	u8 res6[0x2];
+	u32 spitd;		/* SPI transmit data register (cpu mode) */
+	u32 spird;		/* SPI receive data register (cpu mode) */
+	u8 res7[0x8];
+} __attribute__ ((packed)) spi_t;
+
+/* SI */
+typedef struct si1 {
+	u16 siamr1;		/* SI1 TDMA mode register */
+	u16 sibmr1;		/* SI1 TDMB mode register */
+	u16 sicmr1;		/* SI1 TDMC mode register */
+	u16 sidmr1;		/* SI1 TDMD mode register */
+	u8 siglmr1_h;		/* SI1 global mode register high */
+	u8 res0[0x1];
+	u8 sicmdr1_h;		/* SI1 command register high */
+	u8 res2[0x1];
+	u8 sistr1_h;		/* SI1 status register high */
+	u8 res3[0x1];
+	u16 sirsr1_h;		/* SI1 RAM shadow address register high */
+	u8 sitarc1;		/* SI1 RAM counter Tx TDMA */
+	u8 sitbrc1;		/* SI1 RAM counter Tx TDMB */
+	u8 sitcrc1;		/* SI1 RAM counter Tx TDMC */
+	u8 sitdrc1;		/* SI1 RAM counter Tx TDMD */
+	u8 sirarc1;		/* SI1 RAM counter Rx TDMA */
+	u8 sirbrc1;		/* SI1 RAM counter Rx TDMB */
+	u8 sircrc1;		/* SI1 RAM counter Rx TDMC */
+	u8 sirdrc1;		/* SI1 RAM counter Rx TDMD */
+	u8 res4[0x8];
+	u16 siemr1;		/* SI1 TDME mode register 16 bits */
+	u16 sifmr1;		/* SI1 TDMF mode register 16 bits */
+	u16 sigmr1;		/* SI1 TDMG mode register 16 bits */
+	u16 sihmr1;		/* SI1 TDMH mode register 16 bits */
+	u8 siglmg1_l;		/* SI1 global mode register low 8 bits */
+	u8 res5[0x1];
+	u8 sicmdr1_l;		/* SI1 command register low 8 bits */
+	u8 res6[0x1];
+	u8 sistr1_l;		/* SI1 status register low 8 bits */
+	u8 res7[0x1];
+	u16 sirsr1_l;		/* SI1 RAM shadow address register low 16 bits */
+	u8 siterc1;		/* SI1 RAM counter Tx TDME 8 bits */
+	u8 sitfrc1;		/* SI1 RAM counter Tx TDMF 8 bits */
+	u8 sitgrc1;		/* SI1 RAM counter Tx TDMG 8 bits */
+	u8 sithrc1;		/* SI1 RAM counter Tx TDMH 8 bits */
+	u8 sirerc1;		/* SI1 RAM counter Rx TDME 8 bits */
+	u8 sirfrc1;		/* SI1 RAM counter Rx TDMF 8 bits */
+	u8 sirgrc1;		/* SI1 RAM counter Rx TDMG 8 bits */
+	u8 sirhrc1;		/* SI1 RAM counter Rx TDMH 8 bits */
+	u8 res8[0x8];
+	u32 siml1;		/* SI1 multiframe limit register */
+	u8 siedm1;		/* SI1 extended diagnostic mode register */
+	u8 res9[0xBB];
+} __attribute__ ((packed)) si1_t;
+
+/* SI Routing Tables */
+typedef struct sir {
+	u8 tx[0x400];
+	u8 rx[0x400];
+	u8 res0[0x800];
+} __attribute__ ((packed)) sir_t;
+
+/* USB Controller.  */
+typedef struct usb_ctlr {
+	u8 usb_usmod;
+	u8 usb_usadr;
+	u8 usb_uscom;
+	u8 res1[1];
+	u16 usb_usep1;
+	u16 usb_usep2;
+	u16 usb_usep3;
+	u16 usb_usep4;
+	u8 res2[4];
+	u16 usb_usber;
+	u8 res3[2];
+	u16 usb_usbmr;
+	u8 res4[1];
+	u8 usb_usbs;
+	u16 usb_ussft;
+	u8 res5[2];
+	u16 usb_usfrn;
+	u8 res6[0x22];
+} __attribute__ ((packed)) usb_t;
+
+/* MCC */
+typedef struct mcc {
+	u32 mcce;		/* MCC event register */
+	u32 mccm;		/* MCC mask register */
+	u32 mccf;		/* MCC configuration register */
+	u32 merl;		/* MCC emergency request level register */
+	u8 res0[0xF0];
+} __attribute__ ((packed)) mcc_t;
+
+/* QE UCC Slow */
+typedef struct ucc_slow {
+	u32 gumr_l;		/* UCCx general mode register (low) */
+	u32 gumr_h;		/* UCCx general mode register (high) */
+	u16 upsmr;		/* UCCx protocol-specific mode register */
+	u8 res0[0x2];
+	u16 utodr;		/* UCCx transmit on demand register */
+	u16 udsr;		/* UCCx data synchronization register */
+	u16 ucce;		/* UCCx event register */
+	u8 res1[0x2];
+	u16 uccm;		/* UCCx mask register */
+	u8 res2[0x1];
+	u8 uccs;		/* UCCx status register */
+	u8 res3[0x24];
+	u16 utpt;
+	u8 guemr;		/* UCC general extended mode register */
+	u8 res4[0x200 - 0x091];
+} __attribute__ ((packed)) ucc_slow_t;
+
+typedef struct ucc_mii_mng {
+	u32 miimcfg;		/* MII management configuration reg    */
+	u32 miimcom;		/* MII management command reg          */
+	u32 miimadd;		/* MII management address reg          */
+	u32 miimcon;		/* MII management control reg          */
+	u32 miimstat;		/* MII management status reg           */
+	u32 miimind;		/* MII management indication reg       */
+	u32 ifctl;		/* interface control reg               */
+	u32 ifstat;		/* interface statux reg                */
+} __attribute__ ((packed))uec_mii_t;
+
+typedef struct ucc_ethernet {
+	u32 maccfg1;		/* mac configuration reg. 1            */
+	u32 maccfg2;		/* mac configuration reg. 2            */
+	u32 ipgifg;		/* interframe gap reg.                 */
+	u32 hafdup;		/* half-duplex reg.                    */
+	u8 res1[0x10];
+	u32 miimcfg;		/* MII management configuration reg    */
+	u32 miimcom;		/* MII management command reg          */
+	u32 miimadd;		/* MII management address reg          */
+	u32 miimcon;		/* MII management control reg          */
+	u32 miimstat;		/* MII management status reg           */
+	u32 miimind;		/* MII management indication reg       */
+	u32 ifctl;		/* interface control reg               */
+	u32 ifstat;		/* interface statux reg                */
+	u32 macstnaddr1;	/* mac station address part 1 reg      */
+	u32 macstnaddr2;	/* mac station address part 2 reg      */
+	u8 res2[0x8];
+	u32 uempr;		/* UCC Ethernet Mac parameter reg      */
+	u32 utbipar;		/* UCC tbi address reg                 */
+	u16 uescr;		/* UCC Ethernet statistics control reg */
+	u8 res3[0x180 - 0x15A];
+	u32 tx64;		/* Total number of frames (including bad
+				 * frames) transmitted that were exactly
+				 * of the minimal length (64 for un tagged,
+				 * 68 for tagged, or with length exactly
+				 * equal to the parameter MINLength */
+	u32 tx127;		/* Total number of frames (including bad
+				 * frames) transmitted that were between
+				 * MINLength (Including FCS length==4)
+				 * and 127 octets */
+	u32 tx255;		/* Total number of frames (including bad
+				 * frames) transmitted that were between
+				 * 128 (Including FCS length==4) and 255
+				 * octets */
+	u32 rx64;		/* Total number of frames received including
+				 * bad frames that were exactly of the
+				 * mninimal length (64 bytes) */
+	u32 rx127;		/* Total number of frames (including bad
+				 * frames) received that were between
+				 * MINLength (Including FCS length==4)
+				 * and 127 octets */
+	u32 rx255;		/* Total number of frames (including
+				 * bad frames) received that were between
+				 * 128 (Including FCS length==4) and 255
+				 * octets */
+	u32 txok;		/* Total number of octets residing in frames
+				 * that where involved in succesfull
+				 * transmission */
+	u16 txcf;		/* Total number of PAUSE control frames
+				 *  transmitted by this MAC */
+	u8 res4[0x2];
+	u32 tmca;		/* Total number of frames that were transmitted
+				 * succesfully with the group address bit set
+				 * that are not broadcast frames */
+	u32 tbca;		/* Total number of frames transmitted
+				 * succesfully that had destination address
+				 * field equal to the broadcast address */
+	u32 rxfok;		/* Total number of frames received OK */
+	u32 rxbok;		/* Total number of octets received OK */
+	u32 rbyt;		/* Total number of octets received including
+				 * octets in bad frames. Must be implemented
+				 * in HW because it includes octets in frames
+				 * that never even reach the UCC */
+	u32 rmca;		/* Total number of frames that were received
+				 * succesfully with the group address bit set
+				 * that are not broadcast frames */
+	u32 rbca;		/* Total number of frames received succesfully
+				 * that had destination address equal to the
+				 * broadcast address */
+	u32 scar;		/* Statistics carry register */
+	u32 scam;		/* Statistics caryy mask register */
+	u8 res5[0x200 - 0x1c4];
+} __attribute__ ((packed)) uec_t;
+
+/* QE UCC Fast */
+typedef struct ucc_fast {
+	u32 gumr;		/* UCCx general mode register */
+	u32 upsmr;		/* UCCx protocol-specific mode register  */
+	u16 utodr;		/* UCCx transmit on demand register  */
+	u8 res0[0x2];
+	u16 udsr;		/* UCCx data synchronization register  */
+	u8 res1[0x2];
+	u32 ucce;		/* UCCx event register */
+	u32 uccm;		/* UCCx mask register.  */
+	u8 uccs;		/* UCCx status register */
+	u8 res2[0x7];
+	u32 urfb;		/* UCC receive FIFO base */
+	u16 urfs;		/* UCC receive FIFO size */
+	u8 res3[0x2];
+	u16 urfet;		/* UCC receive FIFO emergency threshold */
+	u16 urfset;		/* UCC receive FIFO special emergency
+				 * threshold */
+	u32 utfb;		/* UCC transmit FIFO base */
+	u16 utfs;		/* UCC transmit FIFO size */
+	u8 res4[0x2];
+	u16 utfet;		/* UCC transmit FIFO emergency threshold */
+	u8 res5[0x2];
+	u16 utftt;		/* UCC transmit FIFO transmit threshold */
+	u8 res6[0x2];
+	u16 utpt;		/* UCC transmit polling timer */
+	u8 res7[0x2];
+	u32 urtry;		/* UCC retry counter register */
+	u8 res8[0x4C];
+	u8 guemr;		/* UCC general extended mode register */
+	u8 res9[0x100 - 0x091];
+	uec_t ucc_eth;
+} __attribute__ ((packed)) ucc_fast_t;
+
+/* QE UCC */
+typedef struct ucc_common {
+	u8 res1[0x90];
+	u8 guemr;
+	u8 res2[0x200 - 0x091];
+} __attribute__ ((packed)) ucc_common_t;
+
+typedef struct ucc {
+	union {
+		ucc_slow_t slow;
+		ucc_fast_t fast;
+		ucc_common_t common;
+	};
+} __attribute__ ((packed)) ucc_t;
+
+/* MultiPHY UTOPIA POS Controllers (UPC) */
+typedef struct upc {
+	u32 upgcr;		/* UTOPIA/POS general configuration register */
+	u32 uplpa;		/* UTOPIA/POS last PHY address */
+	u32 uphec;		/* ATM HEC register */
+	u32 upuc;		/* UTOPIA/POS UCC configuration */
+	u32 updc1;		/* UTOPIA/POS device 1 configuration */
+	u32 updc2;		/* UTOPIA/POS device 2 configuration  */
+	u32 updc3;		/* UTOPIA/POS device 3 configuration */
+	u32 updc4;		/* UTOPIA/POS device 4 configuration  */
+	u32 upstpa;		/* UTOPIA/POS STPA threshold  */
+	u8 res0[0xC];
+	u32 updrs1_h;		/* UTOPIA/POS device 1 rate select  */
+	u32 updrs1_l;		/* UTOPIA/POS device 1 rate select  */
+	u32 updrs2_h;		/* UTOPIA/POS device 2 rate select  */
+	u32 updrs2_l;		/* UTOPIA/POS device 2 rate select */
+	u32 updrs3_h;		/* UTOPIA/POS device 3 rate select */
+	u32 updrs3_l;		/* UTOPIA/POS device 3 rate select */
+	u32 updrs4_h;		/* UTOPIA/POS device 4 rate select */
+	u32 updrs4_l;		/* UTOPIA/POS device 4 rate select */
+	u32 updrp1;		/* UTOPIA/POS device 1 receive priority low  */
+	u32 updrp2;		/* UTOPIA/POS device 2 receive priority low  */
+	u32 updrp3;		/* UTOPIA/POS device 3 receive priority low  */
+	u32 updrp4;		/* UTOPIA/POS device 4 receive priority low  */
+	u32 upde1;		/* UTOPIA/POS device 1 event */
+	u32 upde2;		/* UTOPIA/POS device 2 event */
+	u32 upde3;		/* UTOPIA/POS device 3 event */
+	u32 upde4;		/* UTOPIA/POS device 4 event */
+	u16 uprp1;
+	u16 uprp2;
+	u16 uprp3;
+	u16 uprp4;
+	u8 res1[0x8];
+	u16 uptirr1_0;		/* Device 1 transmit internal rate 0 */
+	u16 uptirr1_1;		/* Device 1 transmit internal rate 1 */
+	u16 uptirr1_2;		/* Device 1 transmit internal rate 2 */
+	u16 uptirr1_3;		/* Device 1 transmit internal rate 3 */
+	u16 uptirr2_0;		/* Device 2 transmit internal rate 0 */
+	u16 uptirr2_1;		/* Device 2 transmit internal rate 1 */
+	u16 uptirr2_2;		/* Device 2 transmit internal rate 2 */
+	u16 uptirr2_3;		/* Device 2 transmit internal rate 3 */
+	u16 uptirr3_0;		/* Device 3 transmit internal rate 0 */
+	u16 uptirr3_1;		/* Device 3 transmit internal rate 1 */
+	u16 uptirr3_2;		/* Device 3 transmit internal rate 2 */
+	u16 uptirr3_3;		/* Device 3 transmit internal rate 3 */
+	u16 uptirr4_0;		/* Device 4 transmit internal rate 0 */
+	u16 uptirr4_1;		/* Device 4 transmit internal rate 1 */
+	u16 uptirr4_2;		/* Device 4 transmit internal rate 2 */
+	u16 uptirr4_3;		/* Device 4 transmit internal rate 3 */
+	u32 uper1;		/* Device 1 port enable register */
+	u32 uper2;		/* Device 2 port enable register */
+	u32 uper3;		/* Device 3 port enable register */
+	u32 uper4;		/* Device 4 port enable register */
+	u8 res2[0x150];
+} __attribute__ ((packed)) upc_t;
+
+/* SDMA */
+typedef struct sdma {
+	u32 sdsr;		/* Serial DMA status register */
+	u32 sdmr;		/* Serial DMA mode register */
+	u32 sdtr1;		/* SDMA system bus threshold register */
+	u32 sdtr2;		/* SDMA secondary bus threshold register */
+	u32 sdhy1;		/* SDMA system bus hysteresis register */
+	u32 sdhy2;		/* SDMA secondary bus hysteresis register */
+	u32 sdta1;		/* SDMA system bus address register */
+	u32 sdta2;		/* SDMA secondary bus address register */
+	u32 sdtm1;		/* SDMA system bus MSNUM register */
+	u32 sdtm2;		/* SDMA secondary bus MSNUM register */
+	u8 res0[0x10];
+	u32 sdaqr;		/* SDMA address bus qualify register */
+	u32 sdaqmr;		/* SDMA address bus qualify mask register */
+	u8 res1[0x4];
+	u32 sdwbcr;		/* SDMA CAM entries base register */
+	u8 res2[0x38];
+} __attribute__ ((packed)) sdma_t;
+
+/* Debug Space */
+typedef struct dbg {
+	u32 bpdcr;		/* Breakpoint debug command register */
+	u32 bpdsr;		/* Breakpoint debug status register */
+	u32 bpdmr;		/* Breakpoint debug mask register */
+	u32 bprmrr0;		/* Breakpoint request mode risc register 0 */
+	u32 bprmrr1;		/* Breakpoint request mode risc register 1 */
+	u8 res0[0x8];
+	u32 bprmtr0;		/* Breakpoint request mode trb register 0 */
+	u32 bprmtr1;		/* Breakpoint request mode trb register 1 */
+	u8 res1[0x8];
+	u32 bprmir;		/* Breakpoint request mode immediate register */
+	u32 bprmsr;		/* Breakpoint request mode serial register */
+	u32 bpemr;		/* Breakpoint exit mode register */
+	u8 res2[0x48];
+} __attribute__ ((packed)) dbg_t;
+
+/*
+ * RISC Special Registers (Trap and Breakpoint).  These are described in
+ * the QE Developer's Handbook.
+*/
+typedef struct rsp {
+	u32 tibcr[16];	/* Trap/instruction breakpoint control regs */
+	u8 res0[64];
+	u32 ibcr0;
+	u32 ibs0;
+	u32 ibcnr0;
+	u8 res1[4];
+	u32 ibcr1;
+	u32 ibs1;
+	u32 ibcnr1;
+	u32 npcr;
+	u32 dbcr;
+	u32 dbar;
+	u32 dbamr;
+	u32 dbsr;
+	u32 dbcnr;
+	u8 res2[12];
+	u32 dbdr_h;
+	u32 dbdr_l;
+	u32 dbdmr_h;
+	u32 dbdmr_l;
+	u32 bsr;
+	u32 bor;
+	u32 bior;
+	u8 res3[4];
+	u32 iatr[4];
+	u32 eccr;		/* Exception control configuration register */
+	u32 eicr;
+	u8 res4[0x100-0xf8];
+} __attribute__ ((packed)) rsp_t;
+
+typedef struct qe_immap {
+	qe_iram_t iram;		/* I-RAM */
+	qe_ic_t ic;		/* Interrupt Controller */
+	cp_qe_t cp;		/* Communications Processor */
+	qe_mux_t qmx;		/* QE Multiplexer */
+	qe_timers_t qet;	/* QE Timers */
+	spi_t spi[0x2];		/* spi  */
+	mcc_t mcc;		/* mcc */
+	qe_brg_t brg;		/* brg */
+	usb_t usb;		/* USB */
+	si1_t si1;		/* SI */
+	u8 res11[0x800];
+	sir_t sir;		/* SI Routing Tables  */
+	ucc_t ucc1;		/* ucc1 */
+	ucc_t ucc3;		/* ucc3 */
+	ucc_t ucc5;		/* ucc5 */
+	ucc_t ucc7;		/* ucc7 */
+	u8 res12[0x600];
+	upc_t upc1;		/* MultiPHY UTOPIA POS Controller 1 */
+	ucc_t ucc2;		/* ucc2 */
+	ucc_t ucc4;		/* ucc4 */
+	ucc_t ucc6;		/* ucc6 */
+	ucc_t ucc8;		/* ucc8 */
+	u8 res13[0x600];
+	upc_t upc2;		/* MultiPHY UTOPIA POS Controller 2 */
+	sdma_t sdma;		/* SDMA */
+	dbg_t dbg;		/* Debug Space */
+	rsp_t rsp[0x2];		/* RISC Special Registers
+				 * (Trap and Breakpoint) */
+	u8 res14[0x300];
+	u8 res15[0x3A00];
+	u8 res16[0x8000];	/* 0x108000 -  0x110000 */
+	u8 muram[QE_MURAM_SIZE];
+} __attribute__ ((packed)) qe_map_t;
+
+extern qe_map_t *qe_immr;
+
+#endif				/* __IMMAP_QE_H__ */
diff --git a/include/linux/input.h b/include/linux/input.h
new file mode 100644
index 0000000..c7ee22a
--- /dev/null
+++ b/include/linux/input.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 1999-2002 Vojtech Pavlik
+ */
+
+#ifndef _LINUX_INPUT_H
+#define _LINUX_INPUT_H
+
+/*
+ * Keys and buttons
+ *
+ * Most of the keys/buttons are modeled after USB HUT 1.12
+ * (see http://www.usb.org/developers/hidpage).
+ * Abbreviations in the comments:
+ * AC - Application Control
+ * AL - Application Launch Button
+ * SC - System Control
+ */
+
+#define KEY_RESERVED		0
+#define KEY_ESC			1
+#define KEY_1			2
+#define KEY_2			3
+#define KEY_3			4
+#define KEY_4			5
+#define KEY_5			6
+#define KEY_6			7
+#define KEY_7			8
+#define KEY_8			9
+#define KEY_9			10
+#define KEY_0			11
+#define KEY_MINUS		12
+#define KEY_EQUAL		13
+#define KEY_BACKSPACE		14
+#define KEY_TAB			15
+#define KEY_Q			16
+#define KEY_W			17
+#define KEY_E			18
+#define KEY_R			19
+#define KEY_T			20
+#define KEY_Y			21
+#define KEY_U			22
+#define KEY_I			23
+#define KEY_O			24
+#define KEY_P			25
+#define KEY_LEFTBRACE		26
+#define KEY_RIGHTBRACE		27
+#define KEY_ENTER		28
+#define KEY_LEFTCTRL		29
+#define KEY_A			30
+#define KEY_S			31
+#define KEY_D			32
+#define KEY_F			33
+#define KEY_G			34
+#define KEY_H			35
+#define KEY_J			36
+#define KEY_K			37
+#define KEY_L			38
+#define KEY_SEMICOLON		39
+#define KEY_APOSTROPHE		40
+#define KEY_GRAVE		41
+#define KEY_LEFTSHIFT		42
+#define KEY_BACKSLASH		43
+#define KEY_Z			44
+#define KEY_X			45
+#define KEY_C			46
+#define KEY_V			47
+#define KEY_B			48
+#define KEY_N			49
+#define KEY_M			50
+#define KEY_COMMA		51
+#define KEY_DOT			52
+#define KEY_SLASH		53
+#define KEY_RIGHTSHIFT		54
+#define KEY_KPASTERISK		55
+#define KEY_LEFTALT		56
+#define KEY_SPACE		57
+#define KEY_CAPSLOCK		58
+#define KEY_F1			59
+#define KEY_F2			60
+#define KEY_F3			61
+#define KEY_F4			62
+#define KEY_F5			63
+#define KEY_F6			64
+#define KEY_F7			65
+#define KEY_F8			66
+#define KEY_F9			67
+#define KEY_F10			68
+#define KEY_NUMLOCK		69
+#define KEY_SCROLLLOCK		70
+#define KEY_KP7			71
+#define KEY_KP8			72
+#define KEY_KP9			73
+#define KEY_KPMINUS		74
+#define KEY_KP4			75
+#define KEY_KP5			76
+#define KEY_KP6			77
+#define KEY_KPPLUS		78
+#define KEY_KP1			79
+#define KEY_KP2			80
+#define KEY_KP3			81
+#define KEY_KP0			82
+#define KEY_KPDOT		83
+
+#define KEY_ZENKAKUHANKAKU	85
+#define KEY_102ND		86
+#define KEY_F11			87
+#define KEY_F12			88
+#define KEY_RO			89
+#define KEY_KATAKANA		90
+#define KEY_HIRAGANA		91
+#define KEY_HENKAN		92
+#define KEY_KATAKANAHIRAGANA	93
+#define KEY_MUHENKAN		94
+#define KEY_KPJPCOMMA		95
+#define KEY_KPENTER		96
+#define KEY_RIGHTCTRL		97
+#define KEY_KPSLASH		98
+#define KEY_SYSRQ		99
+#define KEY_RIGHTALT		100
+#define KEY_LINEFEED		101
+#define KEY_HOME		102
+#define KEY_UP			103
+#define KEY_PAGEUP		104
+#define KEY_LEFT		105
+#define KEY_RIGHT		106
+#define KEY_END			107
+#define KEY_DOWN		108
+#define KEY_PAGEDOWN		109
+#define KEY_INSERT		110
+#define KEY_DELETE		111
+#define KEY_MACRO		112
+#define KEY_MUTE		113
+#define KEY_VOLUMEDOWN		114
+#define KEY_VOLUMEUP		115
+#define KEY_POWER		116	/* SC System Power Down */
+#define KEY_KPEQUAL		117
+#define KEY_KPPLUSMINUS		118
+#define KEY_PAUSE		119
+#define KEY_SCALE		120	/* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA		121
+#define KEY_HANGEUL		122
+#define KEY_HANGUEL		KEY_HANGEUL
+#define KEY_HANJA		123
+#define KEY_YEN			124
+#define KEY_LEFTMETA		125
+#define KEY_RIGHTMETA		126
+#define KEY_COMPOSE		127
+#define KEY_FN			0x1d0
+
+#endif
diff --git a/include/linux/io.h b/include/linux/io.h
new file mode 100644
index 0000000..7984788
--- /dev/null
+++ b/include/linux/io.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _LINUX_IO_H
+#define _LINUX_IO_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/io.h>
+
+#ifndef CONFIG_HAVE_ARCH_IOMAP
+static inline u8 ioread8(const volatile void __iomem *addr)
+{
+	return readb(addr);
+}
+
+static inline u16 ioread16(const volatile void __iomem *addr)
+{
+	return readw(addr);
+}
+
+static inline u32 ioread32(const volatile void __iomem *addr)
+{
+	return readl(addr);
+}
+#endif /* !CONFIG_HAVE_ARCH_IOMAP */
+
+#ifdef CONFIG_64BIT
+static inline u64 ioread64(const volatile void __iomem *addr)
+{
+	return readq(addr);
+}
+#endif /* CONFIG_64BIT */
+
+#ifndef CONFIG_HAVE_ARCH_IOMAP
+static inline void iowrite8(u8 value, volatile void __iomem *addr)
+{
+	writeb(value, addr);
+}
+
+static inline void iowrite16(u16 value, volatile void __iomem *addr)
+{
+	writew(value, addr);
+}
+
+static inline void iowrite32(u32 value, volatile void __iomem *addr)
+{
+	writel(value, addr);
+}
+#endif /* !CONFIG_HAVE_ARCH_IOMAP */
+
+#ifdef CONFIG_64BIT
+static inline void iowrite64(u64 value, volatile void __iomem *addr)
+{
+	writeq(value, addr);
+}
+#endif /* CONFIG_64BIT */
+
+#ifndef CONFIG_HAVE_ARCH_IOREMAP
+static inline void __iomem *ioremap(resource_size_t offset,
+				    resource_size_t size)
+{
+	return (void __iomem *)(unsigned long)offset;
+}
+
+static inline void iounmap(void __iomem *addr)
+{
+}
+#endif
+
+#define devm_ioremap(dev, offset, size)		ioremap(offset, size)
+
+#endif /* _LINUX_IO_H */
diff --git a/include/linux/ioctl.h b/include/linux/ioctl.h
new file mode 100644
index 0000000..7e55c36
--- /dev/null
+++ b/include/linux/ioctl.h
@@ -0,0 +1,6 @@
+#ifndef _LINUX_IOCTL_H
+#define _LINUX_IOCTL_H
+
+#include <asm/ioctl.h>
+
+#endif /* _LINUX_IOCTL_H */
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
new file mode 100644
index 0000000..ab0ae19
--- /dev/null
+++ b/include/linux/iopoll.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2012-2014 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _LINUX_IOPOLL_H
+#define _LINUX_IOPOLL_H
+
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <time.h>
+
+/**
+ * readx_poll_timeout - Periodically poll an address until a condition is met or a timeout occurs
+ * @op: accessor function (takes @addr as its only argument)
+ * @addr: Address to poll
+ * @val: Variable to read the value into
+ * @cond: Break condition (usually involving @val)
+ * @timeout_us: Timeout in us, 0 means never timeout
+ *
+ * Returns 0 on success and -ETIMEDOUT upon a timeout. In either
+ * case, the last read value at @addr is stored in @val.
+ *
+ * When available, you'll probably want to use one of the specialized
+ * macros defined below rather than this macro directly.
+ */
+#define readx_poll_timeout(op, addr, val, cond, timeout_us)	\
+({ \
+	unsigned long timeout = timer_get_us() + timeout_us; \
+	for (;;) { \
+		(val) = op(addr); \
+		if (cond) \
+			break; \
+		if (timeout_us && time_after(timer_get_us(), timeout)) { \
+			(val) = op(addr); \
+			break; \
+		} \
+	} \
+	(cond) ? 0 : -ETIMEDOUT; \
+})
+
+
+#define readb_poll_timeout(addr, val, cond, timeout_us) \
+	readx_poll_timeout(readb, addr, val, cond, timeout_us)
+
+#define readw_poll_timeout(addr, val, cond, timeout_us) \
+	readx_poll_timeout(readw, addr, val, cond, timeout_us)
+
+#define readl_poll_timeout(addr, val, cond, timeout_us) \
+	readx_poll_timeout(readl, addr, val, cond, timeout_us)
+
+#define readq_poll_timeout(addr, val, cond, timeout_us) \
+	readx_poll_timeout(readq, addr, val, cond, timeout_us)
+
+#define readb_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+	readx_poll_timeout(readb_relaxed, addr, val, cond, timeout_us)
+
+#define readw_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+	readx_poll_timeout(readw_relaxed, addr, val, cond, timeout_us)
+
+#define readl_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+	readx_poll_timeout(readl_relaxed, addr, val, cond, timeout_us)
+
+#define readq_relaxed_poll_timeout(addr, val, cond, timeout_us) \
+	readx_poll_timeout(readq_relaxed, addr, val, cond, timeout_us)
+
+#endif /* _LINUX_IOPOLL_H */
diff --git a/include/linux/ioport.h b/include/linux/ioport.h
new file mode 100644
index 0000000..7129504
--- /dev/null
+++ b/include/linux/ioport.h
@@ -0,0 +1,192 @@
+/*
+ * ioport.h	Definitions of routines for detecting, reserving and
+ *		allocating system resources.
+ *
+ * Authors:	Linus Torvalds
+ */
+
+#ifndef _LINUX_IOPORT_H
+#define _LINUX_IOPORT_H
+
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#include <linux/types.h>
+/*
+ * Resources are tree-like, allowing
+ * nesting etc..
+ */
+struct resource {
+	resource_size_t start;
+	resource_size_t end;
+	const char *name;
+	unsigned long flags;
+	struct resource *parent, *sibling, *child;
+};
+
+struct resource_list {
+	struct resource_list *next;
+	struct resource *res;
+	struct pci_dev *dev;
+};
+
+/*
+ * IO resources have these defined flags.
+ */
+#define IORESOURCE_BITS		0x000000ff	/* Bus-specific bits */
+
+#define IORESOURCE_TYPE_BITS	0x00000f00	/* Resource type */
+#define IORESOURCE_IO		0x00000100
+#define IORESOURCE_MEM		0x00000200
+#define IORESOURCE_IRQ		0x00000400
+#define IORESOURCE_DMA		0x00000800
+
+#define IORESOURCE_PREFETCH	0x00001000	/* No side effects */
+#define IORESOURCE_READONLY	0x00002000
+#define IORESOURCE_CACHEABLE	0x00004000
+#define IORESOURCE_RANGELENGTH	0x00008000
+#define IORESOURCE_SHADOWABLE	0x00010000
+
+#define IORESOURCE_SIZEALIGN	0x00020000	/* size indicates alignment */
+#define IORESOURCE_STARTALIGN	0x00040000	/* start field is alignment */
+
+#define IORESOURCE_MEM_64	0x00100000
+
+#define IORESOURCE_EXCLUSIVE	0x08000000	/* Userland may not map this resource */
+#define IORESOURCE_DISABLED	0x10000000
+#define IORESOURCE_UNSET	0x20000000
+#define IORESOURCE_AUTO		0x40000000
+#define IORESOURCE_BUSY		0x80000000	/* Driver has marked this resource busy */
+
+/* PnP IRQ specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_IRQ_HIGHEDGE		(1<<0)
+#define IORESOURCE_IRQ_LOWEDGE		(1<<1)
+#define IORESOURCE_IRQ_HIGHLEVEL	(1<<2)
+#define IORESOURCE_IRQ_LOWLEVEL		(1<<3)
+#define IORESOURCE_IRQ_SHAREABLE	(1<<4)
+#define IORESOURCE_IRQ_OPTIONAL 	(1<<5)
+
+/* PnP DMA specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_DMA_TYPE_MASK	(3<<0)
+#define IORESOURCE_DMA_8BIT		(0<<0)
+#define IORESOURCE_DMA_8AND16BIT	(1<<0)
+#define IORESOURCE_DMA_16BIT		(2<<0)
+
+#define IORESOURCE_DMA_MASTER		(1<<2)
+#define IORESOURCE_DMA_BYTE		(1<<3)
+#define IORESOURCE_DMA_WORD		(1<<4)
+
+#define IORESOURCE_DMA_SPEED_MASK	(3<<6)
+#define IORESOURCE_DMA_COMPATIBLE	(0<<6)
+#define IORESOURCE_DMA_TYPEA		(1<<6)
+#define IORESOURCE_DMA_TYPEB		(2<<6)
+#define IORESOURCE_DMA_TYPEF		(3<<6)
+
+/* PnP memory I/O specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_MEM_WRITEABLE	(1<<0)	/* dup: IORESOURCE_READONLY */
+#define IORESOURCE_MEM_CACHEABLE	(1<<1)	/* dup: IORESOURCE_CACHEABLE */
+#define IORESOURCE_MEM_RANGELENGTH	(1<<2)	/* dup: IORESOURCE_RANGELENGTH */
+#define IORESOURCE_MEM_TYPE_MASK	(3<<3)
+#define IORESOURCE_MEM_8BIT		(0<<3)
+#define IORESOURCE_MEM_16BIT		(1<<3)
+#define IORESOURCE_MEM_8AND16BIT	(2<<3)
+#define IORESOURCE_MEM_32BIT		(3<<3)
+#define IORESOURCE_MEM_SHADOWABLE	(1<<5)	/* dup: IORESOURCE_SHADOWABLE */
+#define IORESOURCE_MEM_EXPANSIONROM	(1<<6)
+
+/* PnP I/O specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_IO_16BIT_ADDR	(1<<0)
+#define IORESOURCE_IO_FIXED		(1<<1)
+
+/* PCI ROM control bits (IORESOURCE_BITS) */
+#define IORESOURCE_ROM_ENABLE		(1<<0)	/* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */
+#define IORESOURCE_ROM_SHADOW		(1<<1)	/* ROM is copy at C000:0 */
+#define IORESOURCE_ROM_COPY		(1<<2)	/* ROM is alloc'd copy, resource field overlaid */
+#define IORESOURCE_ROM_BIOS_COPY	(1<<3)	/* ROM is BIOS copy, resource field overlaid */
+
+/* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
+#define IORESOURCE_PCI_FIXED		(1<<4)	/* Do not move resource */
+
+/* PC/ISA/whatever - the normal PC address spaces: IO and memory */
+extern struct resource ioport_resource;
+extern struct resource iomem_resource;
+
+extern int request_resource(struct resource *root, struct resource *new);
+extern int release_resource(struct resource *new);
+extern void reserve_region_with_split(struct resource *root,
+			     resource_size_t start, resource_size_t end,
+			     const char *name);
+extern int insert_resource(struct resource *parent, struct resource *new);
+extern void insert_resource_expand_to_fit(struct resource *root, struct resource *new);
+extern int allocate_resource(struct resource *root, struct resource *new,
+			     resource_size_t size, resource_size_t min,
+			     resource_size_t max, resource_size_t align,
+			     void (*alignf)(void *, struct resource *,
+					    resource_size_t, resource_size_t),
+			     void *alignf_data);
+int adjust_resource(struct resource *res, resource_size_t start,
+		    resource_size_t size);
+resource_size_t resource_alignment(struct resource *res);
+static inline resource_size_t resource_size(const struct resource *res)
+{
+	return res->end - res->start + 1;
+}
+static inline unsigned long resource_type(const struct resource *res)
+{
+	return res->flags & IORESOURCE_TYPE_BITS;
+}
+
+/* Convenience shorthand with allocation */
+#define request_region(start,n,name)	__request_region(&ioport_resource, (start), (n), (name), 0)
+#define __request_mem_region(start,n,name, excl) __request_region(&iomem_resource, (start), (n), (name), excl)
+#define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name), 0)
+#define request_mem_region_exclusive(start,n,name) \
+	__request_region(&iomem_resource, (start), (n), (name), IORESOURCE_EXCLUSIVE)
+#define rename_region(region, newname) do { (region)->name = (newname); } while (0)
+
+extern struct resource * __request_region(struct resource *,
+					resource_size_t start,
+					resource_size_t n,
+					const char *name, int flags);
+
+/* Compatibility cruft */
+#define release_region(start,n)	__release_region(&ioport_resource, (start), (n))
+#define check_mem_region(start,n)	__check_region(&iomem_resource, (start), (n))
+#define release_mem_region(start,n)	__release_region(&iomem_resource, (start), (n))
+
+extern int __check_region(struct resource *, resource_size_t, resource_size_t);
+extern void __release_region(struct resource *, resource_size_t,
+				resource_size_t);
+
+static inline int __deprecated check_region(resource_size_t s,
+						resource_size_t n)
+{
+	return __check_region(&ioport_resource, s, n);
+}
+
+/* Wrappers for managed devices */
+struct device;
+#define devm_request_region(dev,start,n,name) \
+	__devm_request_region(dev, &ioport_resource, (start), (n), (name))
+#define devm_request_mem_region(dev,start,n,name) \
+	__devm_request_region(dev, &iomem_resource, (start), (n), (name))
+
+extern struct resource * __devm_request_region(struct device *dev,
+				struct resource *parent, resource_size_t start,
+				resource_size_t n, const char *name);
+
+#define devm_release_region(dev, start, n) \
+	__devm_release_region(dev, &ioport_resource, (start), (n))
+#define devm_release_mem_region(dev, start, n) \
+	__devm_release_region(dev, &iomem_resource, (start), (n))
+
+extern void __devm_release_region(struct device *dev, struct resource *parent,
+				  resource_size_t start, resource_size_t n);
+extern int iomem_map_sanity_check(resource_size_t addr, unsigned long size);
+extern int iomem_is_exclusive(u64 addr);
+
+extern int
+walk_system_ram_range(unsigned long start_pfn, unsigned long nr_pages,
+		void *arg, int (*func)(unsigned long, unsigned long, void *));
+
+#endif /* __ASSEMBLY__ */
+#endif	/* _LINUX_IOPORT_H */
diff --git a/include/linux/kbuild.h b/include/linux/kbuild.h
new file mode 100644
index 0000000..8a9f645
--- /dev/null
+++ b/include/linux/kbuild.h
@@ -0,0 +1,20 @@
+/*
+ * Copied from Linux:
+ * commit 37487a56523d402e25650da16c337acf4cecd13d
+ * Author: Christoph Lameter <clameter@sgi.com>
+ */
+#ifndef __LINUX_KBUILD_H
+#define __LINUX_KBUILD_H
+
+#define DEFINE(sym, val) \
+	asm volatile("\n.ascii \"->" #sym " %0 " #val "\"" : : "i" (val))
+
+#define BLANK() asm volatile("\n.ascii \"->\"" : : )
+
+#define OFFSET(sym, str, mem) \
+	DEFINE(sym, offsetof(struct str, mem))
+
+#define COMMENT(x) \
+	asm volatile("\n.ascii \"->#" x "\"")
+
+#endif
diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h
new file mode 100644
index 0000000..921f77d
--- /dev/null
+++ b/include/linux/kconfig.h
@@ -0,0 +1,109 @@
+#ifndef __LINUX_KCONFIG_H
+#define __LINUX_KCONFIG_H
+
+//#include <generated/autoconf.h>
+
+/*
+ * Helper macros to use CONFIG_ options in C/CPP expressions. Note that
+ * these only work with boolean and tristate options.
+ */
+
+/*
+ * Getting something that works in C and CPP for an arg that may or may
+ * not be defined is tricky.  Here, if we have "#define CONFIG_BOOGER 1"
+ * we match on the placeholder define, insert the "0," for arg1 and generate
+ * the triplet (0, 1, 0).  Then the last step cherry picks the 2nd arg (a one).
+ * When CONFIG_BOOGER is not defined, we generate a (... 1, 0) pair, and when
+ * the last step cherry picks the 2nd arg, we get a zero.
+ */
+#define __ARG_PLACEHOLDER_1 0,
+#define config_enabled(cfg) _config_enabled(cfg)
+#define _config_enabled(value) __config_enabled(__ARG_PLACEHOLDER_##value)
+#define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0)
+#define ___config_enabled(__ignored, val, ...) val
+
+/*
+ * IS_ENABLED(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y' or 'm',
+ * 0 otherwise.
+ *
+ */
+#define IS_ENABLED(option) \
+	(config_enabled(option) || config_enabled(option##_MODULE))
+
+/*
+ * IS_BUILTIN(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'y', 0
+ * otherwise. For boolean options, this is equivalent to
+ * IS_ENABLED(CONFIG_FOO).
+ */
+#define IS_BUILTIN(option) config_enabled(option)
+
+/*
+ * IS_MODULE(CONFIG_FOO) evaluates to 1 if CONFIG_FOO is set to 'm', 0
+ * otherwise.
+ */
+#define IS_MODULE(option) config_enabled(option##_MODULE)
+
+/*
+ * U-Boot add-on: Helper macros to reference to different macros
+ * (CONFIG_ or CONFIG_SPL_ prefixed), depending on the build context.
+ */
+#ifdef CONFIG_SPL_BUILD
+#define _IS_SPL 1
+#endif
+
+#ifdef CONFIG_TPL_BUILD
+#define _IS_TPL 1
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+#define config_val(cfg) _config_val(_IS_TPL, cfg)
+#define _config_val(x, cfg) __config_val(x, cfg)
+#define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg)
+#define ___config_val(arg1_or_junk, cfg)  \
+	____config_val(arg1_or_junk CONFIG_TPL_##cfg, CONFIG_##cfg)
+#define ____config_val(__ignored, val, ...) val
+#else
+#define config_val(cfg) _config_val(_IS_SPL, cfg)
+#define _config_val(x, cfg) __config_val(x, cfg)
+#define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg)
+#define ___config_val(arg1_or_junk, cfg)  \
+	____config_val(arg1_or_junk CONFIG_SPL_##cfg, CONFIG_##cfg)
+#define ____config_val(__ignored, val, ...) val
+#endif
+
+/*
+ * CONFIG_VAL(FOO) evaluates to the value of
+ *  CONFIG_FOO if CONFIG_SPL_BUILD is undefined,
+ *  CONFIG_SPL_FOO if CONFIG_SPL_BUILD is defined.
+ *  CONFIG_TPL_FOO if CONFIG_TPL_BUILD is defined.
+ */
+#define CONFIG_VAL(option)  config_val(option)
+
+/*
+ * CONFIG_IS_ENABLED(FOO) evaluates to
+ *  1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y' or 'm',
+ *  1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y' or 'm',
+ *  1 if CONFIG_TPL_BUILD is defined and CONFIG_TPL_FOO is set to 'y' or 'm',
+ *  0 otherwise.
+ */
+#define CONFIG_IS_ENABLED(option) \
+	(config_enabled(CONFIG_VAL(option)) ||		\
+	 config_enabled(CONFIG_VAL(option##_MODULE)))
+
+/*
+ * CONFIG_IS_BUILTIN(FOO) evaluates to
+ *  1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'y',
+ *  1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y',
+ *  0 otherwise.
+ */
+#define CONFIG_IS_BUILTIN(option) config_enabled(CONFIG_VAL(option))
+
+/*
+ * CONFIG_IS_MODULE(FOO) evaluates to
+ *  1 if CONFIG_SPL_BUILD is undefined and CONFIG_FOO is set to 'm',
+ *  1 if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'm',
+ *  0 otherwise.
+ */
+#define CONFIG_IS_MODULE(option) config_enabled(CONFIG_VAL(option##_MODULE))
+
+#endif /* __LINUX_KCONFIG_H */
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
new file mode 100644
index 0000000..a85c15d
--- /dev/null
+++ b/include/linux/kernel.h
@@ -0,0 +1,269 @@
+#ifndef _LINUX_KERNEL_H
+#define _LINUX_KERNEL_H
+
+
+#include <linux/types.h>
+
+#define USHRT_MAX	((u16)(~0U))
+#define SHRT_MAX	((s16)(USHRT_MAX>>1))
+#define SHRT_MIN	((s16)(-SHRT_MAX - 1))
+#define INT_MAX		((int)(~0U>>1))
+#define INT_MIN		(-INT_MAX - 1)
+#define UINT_MAX	(~0U)
+#define LONG_MAX	((long)(~0UL>>1))
+#define LONG_MIN	(-LONG_MAX - 1)
+#define ULONG_MAX	(~0UL)
+#define LLONG_MAX	((long long)(~0ULL>>1))
+#define LLONG_MIN	(-LLONG_MAX - 1)
+#define ULLONG_MAX	(~0ULL)
+#ifndef SIZE_MAX
+#define SIZE_MAX	(~(size_t)0)
+#endif
+
+#define U8_MAX		((u8)~0U)
+#define S8_MAX		((s8)(U8_MAX>>1))
+#define S8_MIN		((s8)(-S8_MAX - 1))
+#define U16_MAX		((u16)~0U)
+#define S16_MAX		((s16)(U16_MAX>>1))
+#define S16_MIN		((s16)(-S16_MAX - 1))
+#define U32_MAX		((u32)~0U)
+#define S32_MAX		((s32)(U32_MAX>>1))
+#define S32_MIN		((s32)(-S32_MAX - 1))
+#define U64_MAX		((u64)~0ULL)
+#define S64_MAX		((s64)(U64_MAX>>1))
+#define S64_MIN		((s64)(-S64_MAX - 1))
+
+/* Aliases defined by stdint.h */
+#define UINT32_MAX	U32_MAX
+#define UINT64_MAX	U64_MAX
+
+#define STACK_MAGIC	0xdeadbeef
+
+#define REPEAT_BYTE(x)	((~0ul / 0xff) * (x))
+
+#define ALIGN(x,a)		__ALIGN_MASK((x),(typeof(x))(a)-1)
+#define ALIGN_DOWN(x, a)	ALIGN((x) - ((a) - 1), (a))
+#define __ALIGN_MASK(x,mask)	(((x)+(mask))&~(mask))
+#define PTR_ALIGN(p, a)		((typeof(p))ALIGN((unsigned long)(p), (a)))
+#define IS_ALIGNED(x, a)		(((x) & ((typeof(x))(a) - 1)) == 0)
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/*
+ * This looks more complex than it should be. But we need to
+ * get the type for the ~ right in round_down (it needs to be
+ * as wide as the result!), and we want to evaluate the macro
+ * arguments just once each.
+ */
+#define __round_mask(x, y) ((__typeof__(x))((y)-1))
+#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)
+#define round_down(x, y) ((x) & ~__round_mask(x, y))
+
+#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+
+#define DIV_ROUND_DOWN_ULL(ll, d) \
+	({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
+
+#define DIV_ROUND_UP_ULL(ll, d)		DIV_ROUND_DOWN_ULL((ll) + (d) - 1, (d))
+
+#if BITS_PER_LONG == 32
+# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP_ULL(ll, d)
+#else
+# define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP(ll,d)
+#endif
+
+/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */
+#define roundup(x, y) (					\
+{							\
+	const typeof(y) __y = y;			\
+	(((x) + (__y - 1)) / __y) * __y;		\
+}							\
+)
+#define rounddown(x, y) (				\
+{							\
+	typeof(x) __x = (x);				\
+	__x - (__x % (y));				\
+}							\
+)
+
+/*
+ * Divide positive or negative dividend by positive divisor and round
+ * to closest integer. Result is undefined for negative divisors and
+ * for negative dividends if the divisor variable type is unsigned.
+ */
+#define DIV_ROUND_CLOSEST(x, divisor)(			\
+{							\
+	typeof(x) __x = x;				\
+	typeof(divisor) __d = divisor;			\
+	(((typeof(x))-1) > 0 ||				\
+	 ((typeof(divisor))-1) > 0 || (__x) > 0) ?	\
+		(((__x) + ((__d) / 2)) / (__d)) :	\
+		(((__x) - ((__d) / 2)) / (__d));	\
+}							\
+)
+/*
+ * Same as above but for u64 dividends. divisor must be a 32-bit
+ * number.
+ */
+#define DIV_ROUND_CLOSEST_ULL(x, divisor)(		\
+{							\
+	typeof(divisor) __d = divisor;			\
+	unsigned long long _tmp = (x) + (__d) / 2;	\
+	do_div(_tmp, __d);				\
+	_tmp;						\
+}							\
+)
+
+/*
+ * Multiplies an integer by a fraction, while avoiding unnecessary
+ * overflow or loss of precision.
+ */
+#define mult_frac(x, numer, denom)(			\
+{							\
+	typeof(x) quot = (x) / (denom);			\
+	typeof(x) rem  = (x) % (denom);			\
+	(quot * (numer)) + ((rem * (numer)) / (denom));	\
+}							\
+)
+
+/**
+ * upper_32_bits - return bits 32-63 of a number
+ * @n: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * lower_32_bits - return bits 0-31 of a number
+ * @n: the number we're accessing
+ */
+#define lower_32_bits(n) ((u32)(n))
+
+/*
+ * abs() handles unsigned and signed longs, ints, shorts and chars.  For all
+ * input types abs() returns a signed long.
+ * abs() should not be used for 64-bit types (s64, u64, long long) - use abs64()
+ * for those.
+ */
+#define abs(x) ({						\
+		long ret;					\
+		if (sizeof(x) == sizeof(long)) {		\
+			long __x = (x);				\
+			ret = (__x < 0) ? -__x : __x;		\
+		} else {					\
+			int __x = (x);				\
+			ret = (__x < 0) ? -__x : __x;		\
+		}						\
+		ret;						\
+	})
+
+#define abs64(x) ({				\
+		s64 __x = (x);			\
+		(__x < 0) ? -__x : __x;		\
+	})
+
+/*
+ * min()/max()/clamp() macros that also do
+ * strict type-checking.. See the
+ * "unnecessary" pointer comparison.
+ */
+#define min(x, y) ({				\
+	typeof(x) _min1 = (x);			\
+	typeof(y) _min2 = (y);			\
+	(void) (&_min1 == &_min2);		\
+	_min1 < _min2 ? _min1 : _min2; })
+
+#define max(x, y) ({				\
+	typeof(x) _max1 = (x);			\
+	typeof(y) _max2 = (y);			\
+	(void) (&_max1 == &_max2);		\
+	_max1 > _max2 ? _max1 : _max2; })
+
+#define min3(x, y, z) min((typeof(x))min(x, y), z)
+#define max3(x, y, z) max((typeof(x))max(x, y), z)
+
+/**
+ * min_not_zero - return the minimum that is _not_ zero, unless both are zero
+ * @x: value1
+ * @y: value2
+ */
+#define min_not_zero(x, y) ({			\
+	typeof(x) __x = (x);			\
+	typeof(y) __y = (y);			\
+	__x == 0 ? __y : ((__y == 0) ? __x : min(__x, __y)); })
+
+/**
+ * clamp - return a value clamped to a given range with strict typechecking
+ * @val: current value
+ * @lo: lowest allowable value
+ * @hi: highest allowable value
+ *
+ * This macro does strict typechecking of lo/hi to make sure they are of the
+ * same type as val.  See the unnecessary pointer comparisons.
+ */
+#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
+
+/*
+ * ..and if you can't take the strict
+ * types, you can specify one yourself.
+ *
+ * Or not use min/max/clamp at all, of course.
+ */
+#define min_t(type, x, y) ({			\
+	type __min1 = (x);			\
+	type __min2 = (y);			\
+	__min1 < __min2 ? __min1: __min2; })
+
+#define max_t(type, x, y) ({			\
+	type __max1 = (x);			\
+	type __max2 = (y);			\
+	__max1 > __max2 ? __max1: __max2; })
+
+/**
+ * clamp_t - return a value clamped to a given range using a given type
+ * @type: the type of variable to use
+ * @val: current value
+ * @lo: minimum allowable value
+ * @hi: maximum allowable value
+ *
+ * This macro does no typechecking and uses temporary variables of type
+ * 'type' to make all the comparisons.
+ */
+#define clamp_t(type, val, lo, hi) min_t(type, max_t(type, val, lo), hi)
+
+/**
+ * clamp_val - return a value clamped to a given range using val's type
+ * @val: current value
+ * @lo: minimum allowable value
+ * @hi: maximum allowable value
+ *
+ * This macro does no typechecking and uses temporary variables of whatever
+ * type the input argument 'val' is.  This is useful when val is an unsigned
+ * type and min and max are literals that will otherwise be assigned a signed
+ * integer type.
+ */
+#define clamp_val(val, lo, hi) clamp_t(typeof(val), val, lo, hi)
+
+
+/*
+ * swap - swap value of @a and @b
+ */
+#define swap(a, b) \
+	do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr:	the pointer to the member.
+ * @type:	the type of the container struct this is embedded in.
+ * @member:	the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+#endif
diff --git a/include/linux/libfdt.h b/include/linux/libfdt.h
new file mode 100644
index 0000000..eeb2344
--- /dev/null
+++ b/include/linux/libfdt.h
@@ -0,0 +1,312 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _INCLUDE_LIBFDT_H_
+#define _INCLUDE_LIBFDT_H_
+
+#ifndef USE_HOSTCC
+#include <linux/libfdt_env.h>
+#endif
+#include "../../scripts/dtc/libfdt/libfdt.h"
+
+/* U-Boot local hacks */
+
+#ifndef SWIG /* Not available in Python */
+struct fdt_region {
+	int offset;
+	int size;
+};
+
+/*
+ * Flags for fdt_find_regions()
+ *
+ * Add a region for the string table (always the last region)
+ */
+#define FDT_REG_ADD_STRING_TAB		(1 << 0)
+
+/*
+ * Add all supernodes of a matching node/property, useful for creating a
+ * valid subset tree
+ */
+#define FDT_REG_SUPERNODES		(1 << 1)
+
+/* Add the FDT_BEGIN_NODE tags of subnodes, including their names */
+#define FDT_REG_DIRECT_SUBNODES	(1 << 2)
+
+/* Add all subnodes of a matching node */
+#define FDT_REG_ALL_SUBNODES		(1 << 3)
+
+/* Add a region for the mem_rsvmap table (always the first region) */
+#define FDT_REG_ADD_MEM_RSVMAP		(1 << 4)
+
+/* Indicates what an fdt part is (node, property, value) */
+#define FDT_IS_NODE			(1 << 0)
+#define FDT_IS_PROP			(1 << 1)
+#define FDT_IS_VALUE			(1 << 2)	/* not supported */
+#define FDT_IS_COMPAT			(1 << 3)	/* used internally */
+#define FDT_NODE_HAS_PROP		(1 << 4)	/* node contains prop */
+
+#define FDT_ANY_GLOBAL		(FDT_IS_NODE | FDT_IS_PROP | FDT_IS_VALUE | \
+					FDT_IS_COMPAT)
+#define FDT_IS_ANY			0x1f		/* all the above */
+
+/* We set a reasonable limit on the number of nested nodes */
+#define FDT_MAX_DEPTH			32
+
+/* Decribes what we want to include from the current tag */
+enum want_t {
+	WANT_NOTHING,
+	WANT_NODES_ONLY,		/* No properties */
+	WANT_NODES_AND_PROPS,		/* Everything for one level */
+	WANT_ALL_NODES_AND_PROPS	/* Everything for all levels */
+};
+
+/* Keeps track of the state at parent nodes */
+struct fdt_subnode_stack {
+	int offset;		/* Offset of node */
+	enum want_t want;	/* The 'want' value here */
+	int included;		/* 1 if we included this node, 0 if not */
+};
+
+struct fdt_region_ptrs {
+	int depth;			/* Current tree depth */
+	int done;			/* What we have completed scanning */
+	enum want_t want;		/* What we are currently including */
+	char *end;			/* Pointer to end of full node path */
+	int nextoffset;			/* Next node offset to check */
+};
+
+/* The state of our finding algortihm */
+struct fdt_region_state {
+	struct fdt_subnode_stack stack[FDT_MAX_DEPTH];	/* node stack */
+	struct fdt_region *region;	/* Contains list of regions found */
+	int count;			/* Numnber of regions found */
+	const void *fdt;		/* FDT blob */
+	int max_regions;		/* Maximum regions to find */
+	int can_merge;		/* 1 if we can merge with previous region */
+	int start;			/* Start position of current region */
+	struct fdt_region_ptrs ptrs;	/* Pointers for what we are up to */
+};
+
+/**
+ * fdt_find_regions() - find regions in device tree
+ *
+ * Given a list of nodes to include and properties to exclude, find
+ * the regions of the device tree which describe those included parts.
+ *
+ * The intent is to get a list of regions which will be invariant provided
+ * those parts are invariant. For example, if you request a list of regions
+ * for all nodes but exclude the property "data", then you will get the
+ * same region contents regardless of any change to "data" properties.
+ *
+ * This function can be used to produce a byte-stream to send to a hashing
+ * function to verify that critical parts of the FDT have not changed.
+ *
+ * Nodes which are given in 'inc' are included in the region list, as
+ * are the names of the immediate subnodes nodes (but not the properties
+ * or subnodes of those subnodes).
+ *
+ * For eaxample "/" means to include the root node, all root properties
+ * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter
+ * ensures that we capture the names of the subnodes. In a hashing situation
+ * it prevents the root node from changing at all Any change to non-excluded
+ * properties, names of subnodes or number of subnodes would be detected.
+ *
+ * When used with FITs this provides the ability to hash and sign parts of
+ * the FIT based on different configurations in the FIT. Then it is
+ * impossible to change anything about that configuration (include images
+ * attached to the configuration), but it may be possible to add new
+ * configurations, new images or new signatures within the existing
+ * framework.
+ *
+ * Adding new properties to a device tree may result in the string table
+ * being extended (if the new property names are different from those
+ * already added). This function can optionally include a region for
+ * the string table so that this can be part of the hash too.
+ *
+ * The device tree header is not included in the list.
+ *
+ * @fdt:	Device tree to check
+ * @inc:	List of node paths to included
+ * @inc_count:	Number of node paths in list
+ * @exc_prop:	List of properties names to exclude
+ * @exc_prop_count:	Number of properties in exclude list
+ * @region:	Returns list of regions
+ * @max_region:	Maximum length of region list
+ * @path:	Pointer to a temporary string for the function to use for
+ *		building path names
+ * @path_len:	Length of path, must be large enough to hold the longest
+ *		path in the tree
+ * @add_string_tab:	1 to add a region for the string table
+ * @return number of regions in list. If this is >max_regions then the
+ * region array was exhausted. You should increase max_regions and try
+ * the call again.
+ */
+int fdt_find_regions(const void *fdt, char * const inc[], int inc_count,
+		     char * const exc_prop[], int exc_prop_count,
+		     struct fdt_region region[], int max_regions,
+		     char *path, int path_len, int add_string_tab);
+
+/**
+ * fdt_first_region() - find regions in device tree
+ *
+ * Given a nodes and properties to include and properties to exclude, find
+ * the regions of the device tree which describe those included parts.
+ *
+ * The use for this function is twofold. Firstly it provides a convenient
+ * way of performing a structure-aware grep of the tree. For example it is
+ * possible to grep for a node and get all the properties associated with
+ * that node. Trees can be subsetted easily, by specifying the nodes that
+ * are required, and then writing out the regions returned by this function.
+ * This is useful for small resource-constrained systems, such as boot
+ * loaders, which want to use an FDT but do not need to know about all of
+ * it.
+ *
+ * Secondly it makes it easy to hash parts of the tree and detect changes.
+ * The intent is to get a list of regions which will be invariant provided
+ * those parts are invariant. For example, if you request a list of regions
+ * for all nodes but exclude the property "data", then you will get the
+ * same region contents regardless of any change to "data" properties.
+ *
+ * This function can be used to produce a byte-stream to send to a hashing
+ * function to verify that critical parts of the FDT have not changed.
+ * Note that semantically null changes in order could still cause false
+ * hash misses. Such reordering might happen if the tree is regenerated
+ * from source, and nodes are reordered (the bytes-stream will be emitted
+ * in a different order and many hash functions will detect this). However
+ * if an existing tree is modified using libfdt functions, such as
+ * fdt_add_subnode() and fdt_setprop(), then this problem is avoided.
+ *
+ * The nodes/properties to include/exclude are defined by a function
+ * provided by the caller. This function is called for each node and
+ * property, and must return:
+ *
+ *    0 - to exclude this part
+ *    1 - to include this part
+ *   -1 - for FDT_IS_PROP only: no information is available, so include
+ *		if its containing node is included
+ *
+ * The last case is only used to deal with properties. Often a property is
+ * included if its containing node is included - this is the case where
+ * -1 is returned.. However if the property is specifically required to be
+ * included/excluded, then 0 or 1 can be returned. Note that including a
+ * property when the FDT_REG_SUPERNODES flag is given will force its
+ * containing node to be included since it is not valid to have a property
+ * that is not in a node.
+ *
+ * Using the information provided, the inclusion of a node can be controlled
+ * either by a node name or its compatible string, or any other property
+ * that the function can determine.
+ *
+ * As an example, including node "/" means to include the root node and all
+ * root properties. A flag provides a way of also including supernodes (of
+ * which there is none for the root node), and another flag includes
+ * immediate subnodes, so in this case we would get the FDT_BEGIN_NODE and
+ * FDT_END_NODE of all subnodes of /.
+ *
+ * The subnode feature helps in a hashing situation since it prevents the
+ * root node from changing at all. Any change to non-excluded properties,
+ * names of subnodes or number of subnodes would be detected.
+ *
+ * When used with FITs this provides the ability to hash and sign parts of
+ * the FIT based on different configurations in the FIT. Then it is
+ * impossible to change anything about that configuration (include images
+ * attached to the configuration), but it may be possible to add new
+ * configurations, new images or new signatures within the existing
+ * framework.
+ *
+ * Adding new properties to a device tree may result in the string table
+ * being extended (if the new property names are different from those
+ * already added). This function can optionally include a region for
+ * the string table so that this can be part of the hash too. This is always
+ * the last region.
+ *
+ * The FDT also has a mem_rsvmap table which can also be included, and is
+ * always the first region if so.
+ *
+ * The device tree header is not included in the region list. Since the
+ * contents of the FDT are changing (shrinking, often), the caller will need
+ * to regenerate the header anyway.
+ *
+ * @fdt:	Device tree to check
+ * @h_include:	Function to call to determine whether to include a part or
+ *		not:
+ *
+ *		@priv: Private pointer as passed to fdt_find_regions()
+ *		@fdt: Pointer to FDT blob
+ *		@offset: Offset of this node / property
+ *		@type: Type of this part, FDT_IS_...
+ *		@data: Pointer to data (node name, property name, compatible
+ *			string, value (not yet supported)
+ *		@size: Size of data, or 0 if none
+ *		@return 0 to exclude, 1 to include, -1 if no information is
+ *		available
+ * @priv:	Private pointer passed to h_include
+ * @region:	Returns list of regions, sorted by offset
+ * @max_regions: Maximum length of region list
+ * @path:	Pointer to a temporary string for the function to use for
+ *		building path names
+ * @path_len:	Length of path, must be large enough to hold the longest
+ *		path in the tree
+ * @flags:	Various flags that control the region algortihm, see
+ *		FDT_REG_...
+ * @return number of regions in list. If this is >max_regions then the
+ * region array was exhausted. You should increase max_regions and try
+ * the call again. Only the first max_regions elements are available in the
+ * array.
+ *
+ * On error a -ve value is return, which can be:
+ *
+ *	-FDT_ERR_BADSTRUCTURE (too deep or more END tags than BEGIN tags
+ *	-FDT_ERR_BADLAYOUT
+ *	-FDT_ERR_NOSPACE (path area is too small)
+ */
+int fdt_first_region(const void *fdt,
+		     int (*h_include)(void *priv, const void *fdt, int offset,
+				      int type, const char *data, int size),
+		     void *priv, struct fdt_region *region,
+		     char *path, int path_len, int flags,
+		     struct fdt_region_state *info);
+
+/** fdt_next_region() - find next region
+ *
+ * See fdt_first_region() for full description. This function finds the
+ * next region according to the provided parameters, which must be the same
+ * as passed to fdt_first_region().
+ *
+ * This function can additionally return -FDT_ERR_NOTFOUND when there are no
+ * more regions
+ */
+int fdt_next_region(const void *fdt,
+		    int (*h_include)(void *priv, const void *fdt, int offset,
+				     int type, const char *data, int size),
+		    void *priv, struct fdt_region *region,
+		    char *path, int path_len, int flags,
+		    struct fdt_region_state *info);
+
+/**
+ * fdt_add_alias_regions() - find aliases that point to existing regions
+ *
+ * Once a device tree grep is complete some of the nodes will be present
+ * and some will have been dropped. This function checks all the alias nodes
+ * to figure out which points point to nodes which are still present. These
+ * aliases need to be kept, along with the nodes they reference.
+ *
+ * Given a list of regions function finds the aliases that still apply and
+ * adds more regions to the list for these. This function is called after
+ * fdt_next_region() has finished returning regions and requires the same
+ * state.
+ *
+ * @fdt:	Device tree file to reference
+ * @region:	List of regions that will be kept
+ * @count:	Number of regions
+ * @max_regions: Number of entries that can fit in @region
+ * @info:	Region state as returned from fdt_next_region()
+ * @return new number of regions in @region (i.e. count + the number added)
+ * or -FDT_ERR_NOSPACE if there was not enough space.
+ */
+int fdt_add_alias_regions(const void *fdt, struct fdt_region *region, int count,
+			  int max_regions, struct fdt_region_state *info);
+#endif /* SWIG */
+
+extern struct fdt_header *working_fdt;  /* Pointer to the working fdt */
+
+#endif /* _INCLUDE_LIBFDT_H_ */
diff --git a/include/linux/libfdt_env.h b/include/linux/libfdt_env.h
new file mode 100644
index 0000000..e2bf79c
--- /dev/null
+++ b/include/linux/libfdt_env.h
@@ -0,0 +1,31 @@
+#ifdef USE_HOSTCC
+#include "../scripts/dtc/libfdt/libfdt_env.h"
+#else
+/*
+ * This position of the include guard is intentional.
+ * Using the same guard name as that of scripts/dtc/libfdt/libfdt_env.h
+ * prevents it from being included.
+ */
+#ifndef LIBFDT_ENV_H
+#define LIBFDT_ENV_H
+
+#include <linux/string.h>
+
+#include <asm/byteorder.h>
+
+typedef __be16 fdt16_t;
+typedef __be32 fdt32_t;
+typedef __be64 fdt64_t;
+
+#define fdt32_to_cpu(x) be32_to_cpu(x)
+#define cpu_to_fdt32(x) cpu_to_be32(x)
+#define fdt64_to_cpu(x) be64_to_cpu(x)
+#define cpu_to_fdt64(x) cpu_to_be64(x)
+
+/* U-Boot: for strtoul in fdt_overlay.c */
+#include <vsprintf.h>
+
+#define strtoul(cp, endp, base)	simple_strtoul(cp, endp, base)
+
+#endif /* LIBFDT_ENV_H */
+#endif
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
new file mode 100644
index 0000000..0b24111
--- /dev/null
+++ b/include/linux/linkage.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * U-Boot - linkage.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ */
+
+#ifndef _LINUX_LINKAGE_H
+#define _LINUX_LINKAGE_H
+
+#include <asm/linkage.h>
+
+/* Some toolchains use other characters (e.g. '`') to mark new line in macro */
+#ifndef ASM_NL
+#define ASM_NL		 ;
+#endif
+
+#ifdef __cplusplus
+#define CPP_ASMLINKAGE		extern "C"
+#else
+#define CPP_ASMLINKAGE
+#endif
+
+#ifndef asmlinkage
+#define asmlinkage CPP_ASMLINKAGE
+#endif
+
+#define SYMBOL_NAME_STR(X)	#X
+#define SYMBOL_NAME(X)		X
+#ifdef __STDC__
+#define SYMBOL_NAME_LABEL(X)	X##:
+#else
+#define SYMBOL_NAME_LABEL(X)	X:
+#endif
+
+#ifndef __ALIGN
+#define __ALIGN .align		4
+#endif
+
+#ifndef __ALIGN_STR
+#define __ALIGN_STR		".align 4"
+#endif
+
+#ifdef __ASSEMBLY__
+
+#define ALIGN			__ALIGN
+#define ALIGN_STR		__ALIGN_STR
+
+#define LENTRY(name) \
+	ALIGN ASM_NL \
+	SYMBOL_NAME_LABEL(name)
+
+#define ENTRY(name) \
+	.globl SYMBOL_NAME(name) ASM_NL \
+	LENTRY(name)
+
+#define WEAK(name) \
+	.weak SYMBOL_NAME(name) ASM_NL \
+	LENTRY(name)
+
+#ifndef END
+#define END(name) \
+	.size name, .-name
+#endif
+
+#ifndef ENDPROC
+#define ENDPROC(name) \
+	.type name STT_FUNC ASM_NL \
+	END(name)
+#endif
+
+#endif
+
+#endif
diff --git a/include/linux/linux_string.h b/include/linux/linux_string.h
new file mode 100644
index 0000000..192b4c9
--- /dev/null
+++ b/include/linux/linux_string.h
@@ -0,0 +1,8 @@
+#ifndef _LINUX_LINUX_STRING_H_
+#define _LINUX_LINUX_STRING_H_
+
+extern char * skip_spaces(const char *);
+
+extern char *strim(char *);
+
+#endif
diff --git a/include/linux/list.h b/include/linux/list.h
new file mode 100644
index 0000000..5b8d1df
--- /dev/null
+++ b/include/linux/list.h
@@ -0,0 +1,685 @@
+#ifndef _LINUX_LIST_H
+#define _LINUX_LIST_H
+
+#include <linux/stddef.h>
+#include <linux/poison.h>
+
+#ifndef ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCH
+static inline void prefetch(const void *x) {;}
+#endif
+
+/*
+ * Simple doubly linked list implementation.
+ *
+ * Some of the internal functions ("__xxx") are useful when
+ * manipulating whole lists rather than single entries, as
+ * sometimes we already know the next/prev entries and we can
+ * generate better code by using them directly rather than
+ * using the generic single-entry routines.
+ */
+
+struct list_head {
+	struct list_head *next, *prev;
+};
+
+#define LIST_HEAD_INIT(name) { &(name), &(name) }
+
+#define LIST_HEAD(name) \
+	struct list_head name = LIST_HEAD_INIT(name)
+
+static inline void INIT_LIST_HEAD(struct list_head *list)
+{
+	list->next = list;
+	list->prev = list;
+}
+
+/*
+ * Insert a new entry between two known consecutive entries.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static inline void __list_add(struct list_head *new,
+			      struct list_head *prev,
+			      struct list_head *next)
+{
+	next->prev = new;
+	new->next = next;
+	new->prev = prev;
+	prev->next = new;
+}
+
+/**
+ * list_add - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it after
+ *
+ * Insert a new entry after the specified head.
+ * This is good for implementing stacks.
+ */
+static inline void list_add(struct list_head *new, struct list_head *head)
+{
+	__list_add(new, head, head->next);
+}
+
+/**
+ * list_add_tail - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it before
+ *
+ * Insert a new entry before the specified head.
+ * This is useful for implementing queues.
+ */
+static inline void list_add_tail(struct list_head *new, struct list_head *head)
+{
+	__list_add(new, head->prev, head);
+}
+
+/*
+ * Delete a list entry by making the prev/next entries
+ * point to each other.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static inline void __list_del(struct list_head *prev, struct list_head *next)
+{
+	next->prev = prev;
+	prev->next = next;
+}
+
+/**
+ * list_del - deletes entry from list.
+ * @entry: the element to delete from the list.
+ * Note: list_empty() on entry does not return true after this, the entry is
+ * in an undefined state.
+ */
+static inline void list_del(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+	entry->next = LIST_POISON1;
+	entry->prev = LIST_POISON2;
+}
+
+/**
+ * list_replace - replace old entry by new one
+ * @old : the element to be replaced
+ * @new : the new element to insert
+ *
+ * If @old was empty, it will be overwritten.
+ */
+static inline void list_replace(struct list_head *old,
+				struct list_head *new)
+{
+	new->next = old->next;
+	new->next->prev = new;
+	new->prev = old->prev;
+	new->prev->next = new;
+}
+
+static inline void list_replace_init(struct list_head *old,
+					struct list_head *new)
+{
+	list_replace(old, new);
+	INIT_LIST_HEAD(old);
+}
+
+/**
+ * list_del_init - deletes entry from list and reinitialize it.
+ * @entry: the element to delete from the list.
+ */
+static inline void list_del_init(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+	INIT_LIST_HEAD(entry);
+}
+
+/**
+ * list_move - delete from one list and add as another's head
+ * @list: the entry to move
+ * @head: the head that will precede our entry
+ */
+static inline void list_move(struct list_head *list, struct list_head *head)
+{
+	__list_del(list->prev, list->next);
+	list_add(list, head);
+}
+
+/**
+ * list_move_tail - delete from one list and add as another's tail
+ * @list: the entry to move
+ * @head: the head that will follow our entry
+ */
+static inline void list_move_tail(struct list_head *list,
+				  struct list_head *head)
+{
+	__list_del(list->prev, list->next);
+	list_add_tail(list, head);
+}
+
+/**
+ * list_is_last - tests whether @list is the last entry in list @head
+ * @list: the entry to test
+ * @head: the head of the list
+ */
+static inline int list_is_last(const struct list_head *list,
+				const struct list_head *head)
+{
+	return list->next == head;
+}
+
+/**
+ * list_empty - tests whether a list is empty
+ * @head: the list to test.
+ */
+static inline int list_empty(const struct list_head *head)
+{
+	return head->next == head;
+}
+
+/**
+ * list_empty_careful - tests whether a list is empty and not being modified
+ * @head: the list to test
+ *
+ * Description:
+ * tests whether a list is empty _and_ checks that no other CPU might be
+ * in the process of modifying either member (next or prev)
+ *
+ * NOTE: using list_empty_careful() without synchronization
+ * can only be safe if the only activity that can happen
+ * to the list entry is list_del_init(). Eg. it cannot be used
+ * if another CPU could re-list_add() it.
+ */
+static inline int list_empty_careful(const struct list_head *head)
+{
+	struct list_head *next = head->next;
+	return (next == head) && (next == head->prev);
+}
+
+/**
+ * list_is_singular - tests whether a list has just one entry.
+ * @head: the list to test.
+ */
+static inline int list_is_singular(const struct list_head *head)
+{
+	return !list_empty(head) && (head->next == head->prev);
+}
+
+static inline void __list_cut_position(struct list_head *list,
+		struct list_head *head, struct list_head *entry)
+{
+	struct list_head *new_first = entry->next;
+	list->next = head->next;
+	list->next->prev = list;
+	list->prev = entry;
+	entry->next = list;
+	head->next = new_first;
+	new_first->prev = head;
+}
+
+/**
+ * list_cut_position - cut a list into two
+ * @list: a new list to add all removed entries
+ * @head: a list with entries
+ * @entry: an entry within head, could be the head itself
+ *	and if so we won't cut the list
+ *
+ * This helper moves the initial part of @head, up to and
+ * including @entry, from @head to @list. You should
+ * pass on @entry an element you know is on @head. @list
+ * should be an empty list or a list you do not care about
+ * losing its data.
+ *
+ */
+static inline void list_cut_position(struct list_head *list,
+		struct list_head *head, struct list_head *entry)
+{
+	if (list_empty(head))
+		return;
+	if (list_is_singular(head) &&
+		(head->next != entry && head != entry))
+		return;
+	if (entry == head)
+		INIT_LIST_HEAD(list);
+	else
+		__list_cut_position(list, head, entry);
+}
+
+static inline void __list_splice(const struct list_head *list,
+				 struct list_head *prev,
+				 struct list_head *next)
+{
+	struct list_head *first = list->next;
+	struct list_head *last = list->prev;
+
+	first->prev = prev;
+	prev->next = first;
+
+	last->next = next;
+	next->prev = last;
+}
+
+/**
+ * list_splice - join two lists, this is designed for stacks
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static inline void list_splice(const struct list_head *list,
+				struct list_head *head)
+{
+	if (!list_empty(list))
+		__list_splice(list, head, head->next);
+}
+
+/**
+ * list_splice_tail - join two lists, each list being a queue
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static inline void list_splice_tail(struct list_head *list,
+				struct list_head *head)
+{
+	if (!list_empty(list))
+		__list_splice(list, head->prev, head);
+}
+
+/**
+ * list_splice_init - join two lists and reinitialise the emptied list.
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ *
+ * The list at @list is reinitialised
+ */
+static inline void list_splice_init(struct list_head *list,
+				    struct list_head *head)
+{
+	if (!list_empty(list)) {
+		__list_splice(list, head, head->next);
+		INIT_LIST_HEAD(list);
+	}
+}
+
+/**
+ * list_splice_tail_init - join two lists and reinitialise the emptied list
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ *
+ * Each of the lists is a queue.
+ * The list at @list is reinitialised
+ */
+static inline void list_splice_tail_init(struct list_head *list,
+					 struct list_head *head)
+{
+	if (!list_empty(list)) {
+		__list_splice(list, head->prev, head);
+		INIT_LIST_HEAD(list);
+	}
+}
+
+/**
+ * list_entry - get the struct for this entry
+ * @ptr:	the &struct list_head pointer.
+ * @type:	the type of the struct this is embedded in.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_entry(ptr, type, member) \
+	container_of(ptr, type, member)
+
+/**
+ * list_first_entry - get the first element from a list
+ * @ptr:	the list head to take the element from.
+ * @type:	the type of the struct this is embedded in.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define list_first_entry(ptr, type, member) \
+	list_entry((ptr)->next, type, member)
+
+/**
+ * list_last_entry - get the last element from a list
+ * @ptr:	the list head to take the element from.
+ * @type:	the type of the struct this is embedded in.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define list_last_entry(ptr, type, member) \
+	list_entry((ptr)->prev, type, member)
+
+/**
+ * list_for_each	-	iterate over a list
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @head:	the head for your list.
+ */
+#define list_for_each(pos, head) \
+	for (pos = (head)->next; prefetch(pos->next), pos != (head); \
+		pos = pos->next)
+
+/**
+ * __list_for_each	-	iterate over a list
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @head:	the head for your list.
+ *
+ * This variant differs from list_for_each() in that it's the
+ * simplest possible list iteration code, no prefetching is done.
+ * Use this for code that knows the list to be very short (empty
+ * or 1 entry) most of the time.
+ */
+#define __list_for_each(pos, head) \
+	for (pos = (head)->next; pos != (head); pos = pos->next)
+
+/**
+ * list_for_each_prev	-	iterate over a list backwards
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @head:	the head for your list.
+ */
+#define list_for_each_prev(pos, head) \
+	for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \
+		pos = pos->prev)
+
+/**
+ * list_for_each_safe - iterate over a list safe against removal of list entry
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @n:		another &struct list_head to use as temporary storage
+ * @head:	the head for your list.
+ */
+#define list_for_each_safe(pos, n, head) \
+	for (pos = (head)->next, n = pos->next; pos != (head); \
+		pos = n, n = pos->next)
+
+/**
+ * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @n:		another &struct list_head to use as temporary storage
+ * @head:	the head for your list.
+ */
+#define list_for_each_prev_safe(pos, n, head) \
+	for (pos = (head)->prev, n = pos->prev; \
+	     prefetch(pos->prev), pos != (head); \
+	     pos = n, n = pos->prev)
+
+/**
+ * list_for_each_entry	-	iterate over list of given type
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry(pos, head, member)				\
+	for (pos = list_entry((head)->next, typeof(*pos), member);	\
+	     prefetch(pos->member.next), &pos->member != (head);	\
+	     pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_reverse - iterate backwards over list of given type.
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_reverse(pos, head, member)			\
+	for (pos = list_entry((head)->prev, typeof(*pos), member);	\
+	     prefetch(pos->member.prev), &pos->member != (head);	\
+	     pos = list_entry(pos->member.prev, typeof(*pos), member))
+
+/**
+ * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue()
+ * @pos:	the type * to use as a start point
+ * @head:	the head of the list
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Prepares a pos entry for use as a start point in list_for_each_entry_continue().
+ */
+#define list_prepare_entry(pos, head, member) \
+	((pos) ? : list_entry(head, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_continue - continue iteration over list of given type
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Continue to iterate over list of given type, continuing after
+ * the current position.
+ */
+#define list_for_each_entry_continue(pos, head, member) 		\
+	for (pos = list_entry(pos->member.next, typeof(*pos), member);	\
+	     prefetch(pos->member.next), &pos->member != (head);	\
+	     pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_continue_reverse - iterate backwards from the given point
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Start to iterate over list of given type backwards, continuing after
+ * the current position.
+ */
+#define list_for_each_entry_continue_reverse(pos, head, member)		\
+	for (pos = list_entry(pos->member.prev, typeof(*pos), member);	\
+	     prefetch(pos->member.prev), &pos->member != (head);	\
+	     pos = list_entry(pos->member.prev, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_from - iterate over list of given type from the current point
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type, continuing from current position.
+ */
+#define list_for_each_entry_from(pos, head, member)			\
+	for (; prefetch(pos->member.next), &pos->member != (head);	\
+	     pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_safe(pos, n, head, member)			\
+	for (pos = list_entry((head)->next, typeof(*pos), member),	\
+		n = list_entry(pos->member.next, typeof(*pos), member);	\
+	     &pos->member != (head);					\
+	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_continue
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type, continuing after current point,
+ * safe against removal of list entry.
+ */
+#define list_for_each_entry_safe_continue(pos, n, head, member) 		\
+	for (pos = list_entry(pos->member.next, typeof(*pos), member),		\
+		n = list_entry(pos->member.next, typeof(*pos), member);		\
+	     &pos->member != (head);						\
+	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_from
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type from current point, safe against
+ * removal of list entry.
+ */
+#define list_for_each_entry_safe_from(pos, n, head, member)			\
+	for (n = list_entry(pos->member.next, typeof(*pos), member);		\
+	     &pos->member != (head);						\
+	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_reverse
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate backwards over list of given type, safe against removal
+ * of list entry.
+ */
+#define list_for_each_entry_safe_reverse(pos, n, head, member)		\
+	for (pos = list_entry((head)->prev, typeof(*pos), member),	\
+		n = list_entry(pos->member.prev, typeof(*pos), member);	\
+	     &pos->member != (head);					\
+	     pos = n, n = list_entry(n->member.prev, typeof(*n), member))
+
+/*
+ * Double linked lists with a single pointer list head.
+ * Mostly useful for hash tables where the two pointer list head is
+ * too wasteful.
+ * You lose the ability to access the tail in O(1).
+ */
+
+struct hlist_head {
+	struct hlist_node *first;
+};
+
+struct hlist_node {
+	struct hlist_node *next, **pprev;
+};
+
+#define HLIST_HEAD_INIT { .first = NULL }
+#define HLIST_HEAD(name) struct hlist_head name = {  .first = NULL }
+#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL)
+static inline void INIT_HLIST_NODE(struct hlist_node *h)
+{
+	h->next = NULL;
+	h->pprev = NULL;
+}
+
+static inline int hlist_unhashed(const struct hlist_node *h)
+{
+	return !h->pprev;
+}
+
+static inline int hlist_empty(const struct hlist_head *h)
+{
+	return !h->first;
+}
+
+static inline void __hlist_del(struct hlist_node *n)
+{
+	struct hlist_node *next = n->next;
+	struct hlist_node **pprev = n->pprev;
+	*pprev = next;
+	if (next)
+		next->pprev = pprev;
+}
+
+static inline void hlist_del(struct hlist_node *n)
+{
+	__hlist_del(n);
+	n->next = LIST_POISON1;
+	n->pprev = LIST_POISON2;
+}
+
+static inline void hlist_del_init(struct hlist_node *n)
+{
+	if (!hlist_unhashed(n)) {
+		__hlist_del(n);
+		INIT_HLIST_NODE(n);
+	}
+}
+
+static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)
+{
+	struct hlist_node *first = h->first;
+	n->next = first;
+	if (first)
+		first->pprev = &n->next;
+	h->first = n;
+	n->pprev = &h->first;
+}
+
+/* next must be != NULL */
+static inline void hlist_add_before(struct hlist_node *n,
+					struct hlist_node *next)
+{
+	n->pprev = next->pprev;
+	n->next = next;
+	next->pprev = &n->next;
+	*(n->pprev) = n;
+}
+
+static inline void hlist_add_after(struct hlist_node *n,
+					struct hlist_node *next)
+{
+	next->next = n->next;
+	n->next = next;
+	next->pprev = &n->next;
+
+	if(next->next)
+		next->next->pprev  = &next->next;
+}
+
+#define hlist_entry(ptr, type, member) container_of(ptr,type,member)
+
+#define hlist_for_each(pos, head) \
+	for (pos = (head)->first; pos && ({ prefetch(pos->next); 1; }); \
+	     pos = pos->next)
+
+#define hlist_for_each_safe(pos, n, head) \
+	for (pos = (head)->first; pos && ({ n = pos->next; 1; }); \
+	     pos = n)
+
+/**
+ * hlist_for_each_entry	- iterate over list of given type
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry(tpos, pos, head, member)			 \
+	for (pos = (head)->first;					 \
+	     pos && ({ prefetch(pos->next); 1;}) &&			 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = pos->next)
+
+/**
+ * hlist_for_each_entry_continue - iterate over a hlist continuing after current point
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry_continue(tpos, pos, member)		 \
+	for (pos = (pos)->next;						 \
+	     pos && ({ prefetch(pos->next); 1;}) &&			 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = pos->next)
+
+/**
+ * hlist_for_each_entry_from - iterate over a hlist continuing from current point
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry_from(tpos, pos, member)			 \
+	for (; pos && ({ prefetch(pos->next); 1;}) &&			 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = pos->next)
+
+/**
+ * hlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @n:		another &struct hlist_node to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry_safe(tpos, pos, n, head, member)		 \
+	for (pos = (head)->first;					 \
+	     pos && ({ n = pos->next; 1; }) &&				 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = n)
+
+#endif
diff --git a/include/linux/list_sort.h b/include/linux/list_sort.h
new file mode 100644
index 0000000..1a2df2e
--- /dev/null
+++ b/include/linux/list_sort.h
@@ -0,0 +1,11 @@
+#ifndef _LINUX_LIST_SORT_H
+#define _LINUX_LIST_SORT_H
+
+#include <linux/types.h>
+
+struct list_head;
+
+void list_sort(void *priv, struct list_head *head,
+	       int (*cmp)(void *priv, struct list_head *a,
+			  struct list_head *b));
+#endif
diff --git a/include/linux/log2.h b/include/linux/log2.h
new file mode 100644
index 0000000..d4e32ec
--- /dev/null
+++ b/include/linux/log2.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Integer base 2 logarithm calculation
+ *
+ * Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _LINUX_LOG2_H
+#define _LINUX_LOG2_H
+
+#include <linux/types.h>
+#include <linux/bitops.h>
+
+/*
+ * non-constant log of base 2 calculators
+ * - the arch may override these in asm/bitops.h if they can be implemented
+ *   more efficiently than using fls() and fls64()
+ * - the arch is not required to handle n==0 if implementing the fallback
+ */
+#ifndef CONFIG_ARCH_HAS_ILOG2_U32
+static inline __attribute__((const))
+int __ilog2_u32(u32 n)
+{
+	return fls(n) - 1;
+}
+#endif
+
+#ifndef CONFIG_ARCH_HAS_ILOG2_U64
+static inline __attribute__((const))
+int __ilog2_u64(u64 n)
+{
+	return fls64(n) - 1;
+}
+#endif
+
+/**
+ * is_power_of_2() - check if a value is a power of two
+ * @n: the value to check
+ *
+ * Determine whether some value is a power of two, where zero is
+ * *not* considered a power of two.
+ * Return: true if @n is a power of 2, otherwise false.
+ */
+static inline __attribute__((const))
+bool is_power_of_2(unsigned long n)
+{
+	return (n != 0 && ((n & (n - 1)) == 0));
+}
+
+/**
+ * __roundup_pow_of_two() - round up to nearest power of two
+ * @n: value to round up
+ */
+static inline __attribute__((const))
+unsigned long __roundup_pow_of_two(unsigned long n)
+{
+	return 1UL << fls_long(n - 1);
+}
+
+/**
+ * __rounddown_pow_of_two() - round down to nearest power of two
+ * @n: value to round down
+ */
+static inline __attribute__((const))
+unsigned long __rounddown_pow_of_two(unsigned long n)
+{
+	return 1UL << (fls_long(n) - 1);
+}
+
+/**
+ * ilog2 - log base 2 of 32-bit or a 64-bit unsigned value
+ * @n: parameter
+ *
+ * constant-capable log of base 2 calculation
+ * - this can be used to initialise global variables from constant data, hence
+ * the massive ternary operator construction
+ *
+ * selects the appropriately-sized optimised version depending on sizeof(n)
+ */
+#define ilog2(n)				\
+(						\
+	__builtin_constant_p(n) ? (		\
+		(n) < 2 ? 0 :			\
+		(n) & (1ULL << 63) ? 63 :	\
+		(n) & (1ULL << 62) ? 62 :	\
+		(n) & (1ULL << 61) ? 61 :	\
+		(n) & (1ULL << 60) ? 60 :	\
+		(n) & (1ULL << 59) ? 59 :	\
+		(n) & (1ULL << 58) ? 58 :	\
+		(n) & (1ULL << 57) ? 57 :	\
+		(n) & (1ULL << 56) ? 56 :	\
+		(n) & (1ULL << 55) ? 55 :	\
+		(n) & (1ULL << 54) ? 54 :	\
+		(n) & (1ULL << 53) ? 53 :	\
+		(n) & (1ULL << 52) ? 52 :	\
+		(n) & (1ULL << 51) ? 51 :	\
+		(n) & (1ULL << 50) ? 50 :	\
+		(n) & (1ULL << 49) ? 49 :	\
+		(n) & (1ULL << 48) ? 48 :	\
+		(n) & (1ULL << 47) ? 47 :	\
+		(n) & (1ULL << 46) ? 46 :	\
+		(n) & (1ULL << 45) ? 45 :	\
+		(n) & (1ULL << 44) ? 44 :	\
+		(n) & (1ULL << 43) ? 43 :	\
+		(n) & (1ULL << 42) ? 42 :	\
+		(n) & (1ULL << 41) ? 41 :	\
+		(n) & (1ULL << 40) ? 40 :	\
+		(n) & (1ULL << 39) ? 39 :	\
+		(n) & (1ULL << 38) ? 38 :	\
+		(n) & (1ULL << 37) ? 37 :	\
+		(n) & (1ULL << 36) ? 36 :	\
+		(n) & (1ULL << 35) ? 35 :	\
+		(n) & (1ULL << 34) ? 34 :	\
+		(n) & (1ULL << 33) ? 33 :	\
+		(n) & (1ULL << 32) ? 32 :	\
+		(n) & (1ULL << 31) ? 31 :	\
+		(n) & (1ULL << 30) ? 30 :	\
+		(n) & (1ULL << 29) ? 29 :	\
+		(n) & (1ULL << 28) ? 28 :	\
+		(n) & (1ULL << 27) ? 27 :	\
+		(n) & (1ULL << 26) ? 26 :	\
+		(n) & (1ULL << 25) ? 25 :	\
+		(n) & (1ULL << 24) ? 24 :	\
+		(n) & (1ULL << 23) ? 23 :	\
+		(n) & (1ULL << 22) ? 22 :	\
+		(n) & (1ULL << 21) ? 21 :	\
+		(n) & (1ULL << 20) ? 20 :	\
+		(n) & (1ULL << 19) ? 19 :	\
+		(n) & (1ULL << 18) ? 18 :	\
+		(n) & (1ULL << 17) ? 17 :	\
+		(n) & (1ULL << 16) ? 16 :	\
+		(n) & (1ULL << 15) ? 15 :	\
+		(n) & (1ULL << 14) ? 14 :	\
+		(n) & (1ULL << 13) ? 13 :	\
+		(n) & (1ULL << 12) ? 12 :	\
+		(n) & (1ULL << 11) ? 11 :	\
+		(n) & (1ULL << 10) ? 10 :	\
+		(n) & (1ULL <<  9) ?  9 :	\
+		(n) & (1ULL <<  8) ?  8 :	\
+		(n) & (1ULL <<  7) ?  7 :	\
+		(n) & (1ULL <<  6) ?  6 :	\
+		(n) & (1ULL <<  5) ?  5 :	\
+		(n) & (1ULL <<  4) ?  4 :	\
+		(n) & (1ULL <<  3) ?  3 :	\
+		(n) & (1ULL <<  2) ?  2 :	\
+		1) :				\
+	(sizeof(n) <= 4) ?			\
+	__ilog2_u32(n) :			\
+	__ilog2_u64(n)				\
+ )
+
+/**
+ * roundup_pow_of_two - round the given value up to nearest power of two
+ * @n: parameter
+ *
+ * round the given value up to the nearest power of two
+ * - the result is undefined when n == 0
+ * - this can be used to initialise global variables from constant data
+ */
+#define roundup_pow_of_two(n)			\
+(						\
+	__builtin_constant_p(n) ? (		\
+		(n == 1) ? 1 :			\
+		(1UL << (ilog2((n) - 1) + 1))	\
+				   ) :		\
+	__roundup_pow_of_two(n)			\
+ )
+
+/**
+ * rounddown_pow_of_two - round the given value down to nearest power of two
+ * @n: parameter
+ *
+ * round the given value down to the nearest power of two
+ * - the result is undefined when n == 0
+ * - this can be used to initialise global variables from constant data
+ */
+#define rounddown_pow_of_two(n)			\
+(						\
+	__builtin_constant_p(n) ? (		\
+		(1UL << ilog2(n))) :		\
+	__rounddown_pow_of_two(n)		\
+ )
+
+static inline __attribute_const__
+int __order_base_2(unsigned long n)
+{
+	return n > 1 ? ilog2(n - 1) + 1 : 0;
+}
+
+/**
+ * order_base_2 - calculate the (rounded up) base 2 order of the argument
+ * @n: parameter
+ *
+ * The first few values calculated by this routine:
+ *  ob2(0) = 0
+ *  ob2(1) = 0
+ *  ob2(2) = 1
+ *  ob2(3) = 2
+ *  ob2(4) = 2
+ *  ob2(5) = 3
+ *  ... and so on.
+ */
+#define order_base_2(n)				\
+(						\
+	__builtin_constant_p(n) ? (		\
+		((n) == 0 || (n) == 1) ? 0 :	\
+		ilog2((n) - 1) + 1) :		\
+	__order_base_2(n)			\
+)
+#endif /* _LINUX_LOG2_H */
diff --git a/include/linux/lzo.h b/include/linux/lzo.h
new file mode 100644
index 0000000..8981d04
--- /dev/null
+++ b/include/linux/lzo.h
@@ -0,0 +1,51 @@
+#ifndef __LZO_H__
+#define __LZO_H__
+/*
+ *  LZO Public Kernel Interface
+ *  A mini subset of the LZO real-time data compression library
+ *
+ *  Copyright (C) 1996-2005 Markus F.X.J. Oberhumer <markus@oberhumer.com>
+ *
+ *  The full LZO package can be found at:
+ *  http://www.oberhumer.com/opensource/lzo/
+ *
+ *  Changed for kernel use by:
+ *  Nitin Gupta <nitingupta910@gmail.com>
+ *  Richard Purdie <rpurdie@openedhand.com>
+ */
+
+#define LZO1X_MEM_COMPRESS	(16384 * sizeof(unsigned char *))
+#define LZO1X_1_MEM_COMPRESS	LZO1X_MEM_COMPRESS
+
+#define lzo1x_worst_compress(x) ((x) + ((x) / 16) + 64 + 3)
+
+/* This requires 'workmem' of size LZO1X_1_MEM_COMPRESS */
+int lzo1x_1_compress(const unsigned char *src, size_t src_len,
+			unsigned char *dst, size_t *dst_len, void *wrkmem);
+
+/* safe decompression with overrun testing */
+int lzo1x_decompress_safe(const unsigned char *src, size_t src_len,
+			unsigned char *dst, size_t *dst_len);
+
+/* decompress lzop format */
+int lzop_decompress(const unsigned char *src, size_t src_len,
+		    unsigned char *dst, size_t *dst_len);
+
+/* check if the header is valid (based on magic numbers) */
+bool lzop_is_valid_header(const unsigned char *src);
+
+/*
+ * Return values (< 0 = Error)
+ */
+#define LZO_E_OK			0
+#define LZO_E_ERROR			(-1)
+#define LZO_E_OUT_OF_MEMORY		(-2)
+#define LZO_E_NOT_COMPRESSIBLE		(-3)
+#define LZO_E_INPUT_OVERRUN		(-4)
+#define LZO_E_OUTPUT_OVERRUN		(-5)
+#define LZO_E_LOOKBEHIND_OVERRUN	(-6)
+#define LZO_E_EOF_NOT_FOUND		(-7)
+#define LZO_E_INPUT_NOT_CONSUMED	(-8)
+#define LZO_E_NOT_YET_IMPLEMENTED	(-9)
+
+#endif
diff --git a/include/linux/math64.h b/include/linux/math64.h
new file mode 100644
index 0000000..08584c8
--- /dev/null
+++ b/include/linux/math64.h
@@ -0,0 +1,257 @@
+#ifndef _LINUX_MATH64_H
+#define _LINUX_MATH64_H
+
+#include <div64.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+
+#if BITS_PER_LONG == 64
+
+#define div64_long(x, y) div64_s64((x), (y))
+#define div64_ul(x, y)   div64_u64((x), (y))
+
+/**
+ * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
+ *
+ * This is commonly provided by 32bit archs to provide an optimized 64bit
+ * divide.
+ */
+static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
+{
+	*remainder = dividend % divisor;
+	return dividend / divisor;
+}
+
+/**
+ * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
+ */
+static inline s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder)
+{
+	*remainder = dividend % divisor;
+	return dividend / divisor;
+}
+
+/**
+ * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
+ */
+static inline u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder)
+{
+	*remainder = dividend % divisor;
+	return dividend / divisor;
+}
+
+/**
+ * div64_u64 - unsigned 64bit divide with 64bit divisor
+ */
+static inline u64 div64_u64(u64 dividend, u64 divisor)
+{
+	return dividend / divisor;
+}
+
+/**
+ * div64_s64 - signed 64bit divide with 64bit divisor
+ */
+static inline s64 div64_s64(s64 dividend, s64 divisor)
+{
+	return dividend / divisor;
+}
+
+#elif BITS_PER_LONG == 32
+
+#define div64_long(x, y) div_s64((x), (y))
+#define div64_ul(x, y)   div_u64((x), (y))
+
+#ifndef div_u64_rem
+static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
+{
+	*remainder = do_div(dividend, divisor);
+	return dividend;
+}
+#endif
+
+#ifndef div_s64_rem
+extern s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder);
+#endif
+
+#ifndef div64_u64_rem
+extern u64 div64_u64_rem(u64 dividend, u64 divisor, u64 *remainder);
+#endif
+
+#ifndef div64_u64
+extern u64 div64_u64(u64 dividend, u64 divisor);
+#endif
+
+#ifndef div64_s64
+extern s64 div64_s64(s64 dividend, s64 divisor);
+#endif
+
+#endif /* BITS_PER_LONG */
+
+/**
+ * div_u64 - unsigned 64bit divide with 32bit divisor
+ *
+ * This is the most common 64bit divide and should be used if possible,
+ * as many 32bit archs can optimize this variant better than a full 64bit
+ * divide.
+ */
+#ifndef div_u64
+static inline u64 div_u64(u64 dividend, u32 divisor)
+{
+	u32 remainder;
+	return div_u64_rem(dividend, divisor, &remainder);
+}
+#endif
+
+/**
+ * div_s64 - signed 64bit divide with 32bit divisor
+ */
+#ifndef div_s64
+static inline s64 div_s64(s64 dividend, s32 divisor)
+{
+	s32 remainder;
+	return div_s64_rem(dividend, divisor, &remainder);
+}
+#endif
+
+u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder);
+
+static __always_inline u32
+__iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder)
+{
+	u32 ret = 0;
+
+	while (dividend >= divisor) {
+		/* The following asm() prevents the compiler from
+		   optimising this loop into a modulo operation.  */
+		asm("" : "+rm"(dividend));
+
+		dividend -= divisor;
+		ret++;
+	}
+
+	*remainder = dividend;
+
+	return ret;
+}
+
+#ifndef mul_u32_u32
+/*
+ * Many a GCC version messes this up and generates a 64x64 mult :-(
+ */
+static inline u64 mul_u32_u32(u32 a, u32 b)
+{
+	return (u64)a * b;
+}
+#endif
+
+#if defined(CONFIG_ARCH_SUPPORTS_INT128) && defined(__SIZEOF_INT128__)
+
+#ifndef mul_u64_u32_shr
+static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift)
+{
+	return (u64)(((unsigned __int128)a * mul) >> shift);
+}
+#endif /* mul_u64_u32_shr */
+
+#ifndef mul_u64_u64_shr
+static inline u64 mul_u64_u64_shr(u64 a, u64 mul, unsigned int shift)
+{
+	return (u64)(((unsigned __int128)a * mul) >> shift);
+}
+#endif /* mul_u64_u64_shr */
+
+#else
+
+#ifndef mul_u64_u32_shr
+static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift)
+{
+	u32 ah, al;
+	u64 ret;
+
+	al = a;
+	ah = a >> 32;
+
+	ret = mul_u32_u32(al, mul) >> shift;
+	if (ah)
+		ret += mul_u32_u32(ah, mul) << (32 - shift);
+
+	return ret;
+}
+#endif /* mul_u64_u32_shr */
+
+#ifndef mul_u64_u64_shr
+static inline u64 mul_u64_u64_shr(u64 a, u64 b, unsigned int shift)
+{
+	union {
+		u64 ll;
+		struct {
+#ifdef __BIG_ENDIAN
+			u32 high, low;
+#else
+			u32 low, high;
+#endif
+		} l;
+	} rl, rm, rn, rh, a0, b0;
+	u64 c;
+
+	a0.ll = a;
+	b0.ll = b;
+
+	rl.ll = mul_u32_u32(a0.l.low, b0.l.low);
+	rm.ll = mul_u32_u32(a0.l.low, b0.l.high);
+	rn.ll = mul_u32_u32(a0.l.high, b0.l.low);
+	rh.ll = mul_u32_u32(a0.l.high, b0.l.high);
+
+	/*
+	 * Each of these lines computes a 64-bit intermediate result into "c",
+	 * starting at bits 32-95.  The low 32-bits go into the result of the
+	 * multiplication, the high 32-bits are carried into the next step.
+	 */
+	rl.l.high = c = (u64)rl.l.high + rm.l.low + rn.l.low;
+	rh.l.low = c = (c >> 32) + rm.l.high + rn.l.high + rh.l.low;
+	rh.l.high = (c >> 32) + rh.l.high;
+
+	/*
+	 * The 128-bit result of the multiplication is in rl.ll and rh.ll,
+	 * shift it right and throw away the high part of the result.
+	 */
+	if (shift == 0)
+		return rl.ll;
+	if (shift < 64)
+		return (rl.ll >> shift) | (rh.ll << (64 - shift));
+	return rh.ll >> (shift & 63);
+}
+#endif /* mul_u64_u64_shr */
+
+#endif
+
+#ifndef mul_u64_u32_div
+static inline u64 mul_u64_u32_div(u64 a, u32 mul, u32 divisor)
+{
+	union {
+		u64 ll;
+		struct {
+#ifdef __BIG_ENDIAN
+			u32 high, low;
+#else
+			u32 low, high;
+#endif
+		} l;
+	} u, rl, rh;
+
+	u.ll = a;
+	rl.ll = mul_u32_u32(u.l.low, mul);
+	rh.ll = mul_u32_u32(u.l.high, mul) + rl.l.high;
+
+	/* Bits 32-63 of the result will be in rh.l.low. */
+	rl.l.high = do_div(rh.ll, divisor);
+
+	/* Bits 0-31 of the result will be in rl.l.low.	*/
+	do_div(rl.ll, divisor);
+
+	rl.l.high = rh.l.low;
+	return rl.ll;
+}
+#endif /* mul_u64_u32_div */
+
+#endif /* _LINUX_MATH64_H */
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
new file mode 100644
index 0000000..717cbea
--- /dev/null
+++ b/include/linux/mbus.h
@@ -0,0 +1,73 @@
+/*
+ * Marvell MBUS common definitions.
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __LINUX_MBUS_H
+#define __LINUX_MBUS_H
+
+struct resource;
+
+struct mbus_dram_target_info {
+	/*
+	 * The 4-bit MBUS target ID of the DRAM controller.
+	 */
+	u8		mbus_dram_target_id;
+
+	/*
+	 * The base address, size, and MBUS attribute ID for each
+	 * of the possible DRAM chip selects.  Peripherals are
+	 * required to support at least 4 decode windows.
+	 */
+	int		num_cs;
+	struct mbus_dram_window {
+		u8	cs_index;
+		u8	mbus_attr;
+		u32	base;
+		u32	size;
+	} cs[4];
+};
+
+struct mvebu_mbus_state {
+	void __iomem *mbuswins_base;
+	void __iomem *sdramwins_base;
+	struct dentry *debugfs_root;
+	struct dentry *debugfs_sdram;
+	struct dentry *debugfs_devs;
+	const struct mvebu_mbus_soc_data *soc;
+	int hw_io_coherency;
+};
+
+/* Flags for PCI/PCIe address decoding regions */
+#define MVEBU_MBUS_PCI_IO  0x1
+#define MVEBU_MBUS_PCI_MEM 0x2
+#define MVEBU_MBUS_PCI_WA  0x3
+
+/*
+ * Magic value that explicits that we don't need a remapping-capable
+ * address decoding window.
+ */
+#define MVEBU_MBUS_NO_REMAP (0xffffffff)
+
+/* Maximum size of a mbus window name */
+#define MVEBU_MBUS_MAX_WINNAME_SZ 32
+
+const struct mbus_dram_target_info *mvebu_mbus_dram_info(void);
+void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
+void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+				      unsigned int attribute,
+				      phys_addr_t base, size_t size,
+				      phys_addr_t remap);
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+				phys_addr_t base, size_t size);
+int mvebu_mbus_del_window(phys_addr_t base, size_t size);
+int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
+		      u32 base, u32 size, u8 target, u8 attr);
+
+#endif /* __LINUX_MBUS_H */
diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h
new file mode 100644
index 0000000..0644d92
--- /dev/null
+++ b/include/linux/mc146818rtc.h
@@ -0,0 +1,86 @@
+/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
+ * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
+ * derived from Data Sheet, Copyright Motorola 1984 (!).
+ * It was written to be part of the Linux operating system.
+ */
+/* permission is hereby granted to copy, modify and redistribute this code
+ * in terms of the GNU Library General Public License, Version 2 or later,
+ * at your option.
+ */
+
+#ifndef _MC146818RTC_H
+#define _MC146818RTC_H
+
+#include <asm/io.h>
+#include <linux/rtc.h>          /* get the user-level API */
+#include <asm/mc146818rtc.h>        /* register access macros */
+
+/**********************************************************************
+ * register summary
+ **********************************************************************/
+#define RTC_SECONDS     0
+#define RTC_SECONDS_ALARM   1
+#define RTC_MINUTES     2
+#define RTC_MINUTES_ALARM   3
+#define RTC_HOURS       4
+#define RTC_HOURS_ALARM     5
+/* RTC_*_alarm is always true if 2 MSBs are set */
+# define RTC_ALARM_DONT_CARE    0xC0
+
+#define RTC_DAY_OF_WEEK     6
+#define RTC_DAY_OF_MONTH    7
+#define RTC_MONTH       8
+#define RTC_YEAR        9
+
+/* control registers - Moto names
+ */
+#define RTC_REG_A       10
+#define RTC_REG_B       11
+#define RTC_REG_C       12
+#define RTC_REG_D       13
+
+/**********************************************************************
+ * register details
+ **********************************************************************/
+#define RTC_FREQ_SELECT RTC_REG_A
+
+/* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
+ * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
+ * totalling to a max high interval of 2.228 ms.
+ */
+# define RTC_UIP        0x80
+# define RTC_DIV_CTL        0x70
+   /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
+#  define RTC_REF_CLCK_4MHZ 0x00
+#  define RTC_REF_CLCK_1MHZ 0x10
+#  define RTC_REF_CLCK_32KHZ    0x20
+   /* 2 values for divider stage reset, others for "testing purposes only" */
+#  define RTC_DIV_RESET1    0x60
+#  define RTC_DIV_RESET2    0x70
+  /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
+# define RTC_RATE_SELECT    0x0F
+
+/**********************************************************************/
+#define RTC_CONTROL RTC_REG_B
+# define RTC_SET 0x80       /* disable updates for clock setting */
+# define RTC_PIE 0x40       /* periodic interrupt enable */
+# define RTC_AIE 0x20       /* alarm interrupt enable */
+# define RTC_UIE 0x10       /* update-finished interrupt enable */
+# define RTC_SQWE 0x08      /* enable square-wave output */
+# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
+# define RTC_24H 0x02       /* 24 hour mode - else hours bit 7 means pm */
+# define RTC_DST_EN 0x01    /* auto switch DST - works f. USA only */
+
+/**********************************************************************/
+#define RTC_INTR_FLAGS  RTC_REG_C
+/* caution - cleared by read */
+# define RTC_IRQF 0x80      /* any of the following 3 is active */
+# define RTC_PF 0x40
+# define RTC_AF 0x20
+# define RTC_UF 0x10
+
+/**********************************************************************/
+#define RTC_VALID   RTC_REG_D
+# define RTC_VRT 0x80       /* valid RAM and time */
+/**********************************************************************/
+#endif /* _MC146818RTC_H */
diff --git a/include/linux/mdio.h b/include/linux/mdio.h
new file mode 100644
index 0000000..6e821d9
--- /dev/null
+++ b/include/linux/mdio.h
@@ -0,0 +1,310 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * linux/mdio.h: definitions for MDIO (clause 45) transceivers
+ * Copyright 2006-2009 Solarflare Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ */
+
+#ifndef __LINUX_MDIO_H__
+#define __LINUX_MDIO_H__
+
+#include <linux/mii.h>
+
+/* MDIO Manageable Devices (MMDs). */
+#define MDIO_MMD_PMAPMD		1	/* Physical Medium Attachment/
+					 * Physical Medium Dependent */
+#define MDIO_MMD_WIS		2	/* WAN Interface Sublayer */
+#define MDIO_MMD_PCS		3	/* Physical Coding Sublayer */
+#define MDIO_MMD_PHYXS		4	/* PHY Extender Sublayer */
+#define MDIO_MMD_DTEXS		5	/* DTE Extender Sublayer */
+#define MDIO_MMD_TC		6	/* Transmission Convergence */
+#define MDIO_MMD_AN		7	/* Auto-Negotiation */
+#define MDIO_MMD_C22EXT		29	/* Clause 22 extension */
+#define MDIO_MMD_VEND1		30	/* Vendor specific 1 */
+#define MDIO_MMD_VEND2		31	/* Vendor specific 2 */
+
+/* Generic MDIO registers. */
+#define MDIO_CTRL1		MII_BMCR
+#define MDIO_STAT1		MII_BMSR
+#define MDIO_DEVID1		MII_PHYSID1
+#define MDIO_DEVID2		MII_PHYSID2
+#define MDIO_SPEED		4	/* Speed ability */
+#define MDIO_DEVS1		5	/* Devices in package */
+#define MDIO_DEVS2		6
+#define MDIO_CTRL2		7	/* 10G control 2 */
+#define MDIO_STAT2		8	/* 10G status 2 */
+#define MDIO_PMA_TXDIS		9	/* 10G PMA/PMD transmit disable */
+#define MDIO_PMA_RXDET		10	/* 10G PMA/PMD receive signal detect */
+#define MDIO_PMA_EXTABLE	11	/* 10G PMA/PMD extended ability */
+#define MDIO_PKGID1		14	/* Package identifier */
+#define MDIO_PKGID2		15
+#define MDIO_AN_ADVERTISE	16	/* AN advertising (base page) */
+#define MDIO_AN_LPA		19	/* AN LP abilities (base page) */
+#define MDIO_PCS_EEE_ABLE	20	/* EEE Capability register */
+#define MDIO_PCS_EEE_WK_ERR	22	/* EEE wake error counter */
+#define MDIO_PHYXS_LNSTAT	24	/* PHY XGXS lane state */
+#define MDIO_AN_EEE_ADV		60	/* EEE advertisement */
+#define MDIO_AN_EEE_LPABLE	61	/* EEE link partner ability */
+
+/* Media-dependent registers. */
+#define MDIO_PMA_10GBT_SWAPPOL	130	/* 10GBASE-T pair swap & polarity */
+#define MDIO_PMA_10GBT_TXPWR	131	/* 10GBASE-T TX power control */
+#define MDIO_PMA_10GBT_SNR	133	/* 10GBASE-T SNR margin, lane A.
+					 * Lanes B-D are numbered 134-136. */
+#define MDIO_PMA_10GBR_FECABLE	170	/* 10GBASE-R FEC ability */
+#define MDIO_PCS_10GBX_STAT1	24	/* 10GBASE-X PCS status 1 */
+#define MDIO_PCS_10GBRT_STAT1	32	/* 10GBASE-R/-T PCS status 1 */
+#define MDIO_PCS_10GBRT_STAT2	33	/* 10GBASE-R/-T PCS status 2 */
+#define MDIO_AN_10GBT_CTRL	32	/* 10GBASE-T auto-negotiation control */
+#define MDIO_AN_10GBT_STAT	33	/* 10GBASE-T auto-negotiation status */
+
+/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
+#define MDIO_PMA_LASI_RXCTRL	0x9000	/* RX_ALARM control */
+#define MDIO_PMA_LASI_TXCTRL	0x9001	/* TX_ALARM control */
+#define MDIO_PMA_LASI_CTRL	0x9002	/* LASI control */
+#define MDIO_PMA_LASI_RXSTAT	0x9003	/* RX_ALARM status */
+#define MDIO_PMA_LASI_TXSTAT	0x9004	/* TX_ALARM status */
+#define MDIO_PMA_LASI_STAT	0x9005	/* LASI status */
+
+/* Control register 1. */
+/* Enable extended speed selection */
+#define MDIO_CTRL1_SPEEDSELEXT		(BMCR_SPEED1000 | BMCR_SPEED100)
+/* All speed selection bits */
+#define MDIO_CTRL1_SPEEDSEL		(MDIO_CTRL1_SPEEDSELEXT | 0x003c)
+#define MDIO_CTRL1_FULLDPLX		BMCR_FULLDPLX
+#define MDIO_CTRL1_LPOWER		BMCR_PDOWN
+#define MDIO_CTRL1_RESET		BMCR_RESET
+#define MDIO_PMA_CTRL1_LOOPBACK		0x0001
+#define MDIO_PMA_CTRL1_SPEED1000	BMCR_SPEED1000
+#define MDIO_PMA_CTRL1_SPEED100		BMCR_SPEED100
+#define MDIO_PCS_CTRL1_LOOPBACK		BMCR_LOOPBACK
+#define MDIO_PHYXS_CTRL1_LOOPBACK	BMCR_LOOPBACK
+#define MDIO_AN_CTRL1_RESTART		BMCR_ANRESTART
+#define MDIO_AN_CTRL1_ENABLE		BMCR_ANENABLE
+#define MDIO_AN_CTRL1_XNP		0x2000	/* Enable extended next page */
+#define MDIO_PCS_CTRL1_CLKSTOP_EN	0x400	/* Stop the clock during LPI */
+
+/* 10 Gb/s */
+#define MDIO_CTRL1_SPEED10G		(MDIO_CTRL1_SPEEDSELEXT | 0x00)
+/* 10PASS-TS/2BASE-TL */
+#define MDIO_CTRL1_SPEED10P2B		(MDIO_CTRL1_SPEEDSELEXT | 0x04)
+
+/* Status register 1. */
+#define MDIO_STAT1_LPOWERABLE		0x0002	/* Low-power ability */
+#define MDIO_STAT1_LSTATUS		BMSR_LSTATUS
+#define MDIO_STAT1_FAULT		0x0080	/* Fault */
+#define MDIO_AN_STAT1_LPABLE		0x0001	/* Link partner AN ability */
+#define MDIO_AN_STAT1_ABLE		BMSR_ANEGCAPABLE
+#define MDIO_AN_STAT1_RFAULT		BMSR_RFAULT
+#define MDIO_AN_STAT1_COMPLETE		BMSR_ANEGCOMPLETE
+#define MDIO_AN_STAT1_PAGE		0x0040	/* Page received */
+#define MDIO_AN_STAT1_XNP		0x0080	/* Extended next page status */
+
+/* Speed register. */
+#define MDIO_SPEED_10G			0x0001	/* 10G capable */
+#define MDIO_PMA_SPEED_2B		0x0002	/* 2BASE-TL capable */
+#define MDIO_PMA_SPEED_10P		0x0004	/* 10PASS-TS capable */
+#define MDIO_PMA_SPEED_1000		0x0010	/* 1000M capable */
+#define MDIO_PMA_SPEED_100		0x0020	/* 100M capable */
+#define MDIO_PMA_SPEED_10		0x0040	/* 10M capable */
+#define MDIO_PCS_SPEED_10P2B		0x0002	/* 10PASS-TS/2BASE-TL capable */
+
+/* Device present registers. */
+#define MDIO_DEVS_PRESENT(devad)	(1 << (devad))
+#define MDIO_DEVS_PMAPMD		MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
+#define MDIO_DEVS_WIS			MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
+#define MDIO_DEVS_PCS			MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
+#define MDIO_DEVS_PHYXS			MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
+#define MDIO_DEVS_DTEXS			MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
+#define MDIO_DEVS_TC			MDIO_DEVS_PRESENT(MDIO_MMD_TC)
+#define MDIO_DEVS_AN			MDIO_DEVS_PRESENT(MDIO_MMD_AN)
+#define MDIO_DEVS_C22EXT		MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
+#define MDIO_DEVS_VEND1			MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
+#define MDIO_DEVS_VEND2			MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
+
+#define MDIO_DEVS_LINK			(MDIO_DEVS_PMAPMD | \
+					MDIO_DEVS_WIS | \
+					MDIO_DEVS_PCS | \
+					MDIO_DEVS_PHYXS | \
+					MDIO_DEVS_DTEXS | \
+					MDIO_DEVS_AN)
+
+/* Control register 2. */
+#define MDIO_PMA_CTRL2_TYPE		0x000f	/* PMA/PMD type selection */
+#define MDIO_PMA_CTRL2_10GBCX4		0x0000	/* 10GBASE-CX4 type */
+#define MDIO_PMA_CTRL2_10GBEW		0x0001	/* 10GBASE-EW type */
+#define MDIO_PMA_CTRL2_10GBLW		0x0002	/* 10GBASE-LW type */
+#define MDIO_PMA_CTRL2_10GBSW		0x0003	/* 10GBASE-SW type */
+#define MDIO_PMA_CTRL2_10GBLX4		0x0004	/* 10GBASE-LX4 type */
+#define MDIO_PMA_CTRL2_10GBER		0x0005	/* 10GBASE-ER type */
+#define MDIO_PMA_CTRL2_10GBLR		0x0006	/* 10GBASE-LR type */
+#define MDIO_PMA_CTRL2_10GBSR		0x0007	/* 10GBASE-SR type */
+#define MDIO_PMA_CTRL2_10GBLRM		0x0008	/* 10GBASE-LRM type */
+#define MDIO_PMA_CTRL2_10GBT		0x0009	/* 10GBASE-T type */
+#define MDIO_PMA_CTRL2_10GBKX4		0x000a	/* 10GBASE-KX4 type */
+#define MDIO_PMA_CTRL2_10GBKR		0x000b	/* 10GBASE-KR type */
+#define MDIO_PMA_CTRL2_1000BT		0x000c	/* 1000BASE-T type */
+#define MDIO_PMA_CTRL2_1000BKX		0x000d	/* 1000BASE-KX type */
+#define MDIO_PMA_CTRL2_100BTX		0x000e	/* 100BASE-TX type */
+#define MDIO_PMA_CTRL2_10BT		0x000f	/* 10BASE-T type */
+#define MDIO_PCS_CTRL2_TYPE		0x0003	/* PCS type selection */
+#define MDIO_PCS_CTRL2_10GBR		0x0000	/* 10GBASE-R type */
+#define MDIO_PCS_CTRL2_10GBX		0x0001	/* 10GBASE-X type */
+#define MDIO_PCS_CTRL2_10GBW		0x0002	/* 10GBASE-W type */
+#define MDIO_PCS_CTRL2_10GBT		0x0003	/* 10GBASE-T type */
+
+/* Status register 2. */
+#define MDIO_STAT2_RXFAULT		0x0400	/* Receive fault */
+#define MDIO_STAT2_TXFAULT		0x0800	/* Transmit fault */
+#define MDIO_STAT2_DEVPRST		0xc000	/* Device present */
+#define MDIO_STAT2_DEVPRST_VAL		0x8000	/* Device present value */
+#define MDIO_PMA_STAT2_LBABLE		0x0001	/* PMA loopback ability */
+#define MDIO_PMA_STAT2_10GBEW		0x0002	/* 10GBASE-EW ability */
+#define MDIO_PMA_STAT2_10GBLW		0x0004	/* 10GBASE-LW ability */
+#define MDIO_PMA_STAT2_10GBSW		0x0008	/* 10GBASE-SW ability */
+#define MDIO_PMA_STAT2_10GBLX4		0x0010	/* 10GBASE-LX4 ability */
+#define MDIO_PMA_STAT2_10GBER		0x0020	/* 10GBASE-ER ability */
+#define MDIO_PMA_STAT2_10GBLR		0x0040	/* 10GBASE-LR ability */
+#define MDIO_PMA_STAT2_10GBSR		0x0080	/* 10GBASE-SR ability */
+#define MDIO_PMD_STAT2_TXDISAB		0x0100	/* PMD TX disable ability */
+#define MDIO_PMA_STAT2_EXTABLE		0x0200	/* Extended abilities */
+#define MDIO_PMA_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
+#define MDIO_PMA_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */
+#define MDIO_PCS_STAT2_10GBR		0x0001	/* 10GBASE-R capable */
+#define MDIO_PCS_STAT2_10GBX		0x0002	/* 10GBASE-X capable */
+#define MDIO_PCS_STAT2_10GBW		0x0004	/* 10GBASE-W capable */
+#define MDIO_PCS_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
+#define MDIO_PCS_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */
+
+/* Transmit disable register. */
+#define MDIO_PMD_TXDIS_GLOBAL		0x0001	/* Global PMD TX disable */
+#define MDIO_PMD_TXDIS_0		0x0002	/* PMD TX disable 0 */
+#define MDIO_PMD_TXDIS_1		0x0004	/* PMD TX disable 1 */
+#define MDIO_PMD_TXDIS_2		0x0008	/* PMD TX disable 2 */
+#define MDIO_PMD_TXDIS_3		0x0010	/* PMD TX disable 3 */
+
+/* Receive signal detect register. */
+#define MDIO_PMD_RXDET_GLOBAL		0x0001	/* Global PMD RX signal detect */
+#define MDIO_PMD_RXDET_0		0x0002	/* PMD RX signal detect 0 */
+#define MDIO_PMD_RXDET_1		0x0004	/* PMD RX signal detect 1 */
+#define MDIO_PMD_RXDET_2		0x0008	/* PMD RX signal detect 2 */
+#define MDIO_PMD_RXDET_3		0x0010	/* PMD RX signal detect 3 */
+
+/* Extended abilities register. */
+#define MDIO_PMA_EXTABLE_10GCX4		0x0001	/* 10GBASE-CX4 ability */
+#define MDIO_PMA_EXTABLE_10GBLRM	0x0002	/* 10GBASE-LRM ability */
+#define MDIO_PMA_EXTABLE_10GBT		0x0004	/* 10GBASE-T ability */
+#define MDIO_PMA_EXTABLE_10GBKX4	0x0008	/* 10GBASE-KX4 ability */
+#define MDIO_PMA_EXTABLE_10GBKR		0x0010	/* 10GBASE-KR ability */
+#define MDIO_PMA_EXTABLE_1000BT		0x0020	/* 1000BASE-T ability */
+#define MDIO_PMA_EXTABLE_1000BKX	0x0040	/* 1000BASE-KX ability */
+#define MDIO_PMA_EXTABLE_100BTX		0x0080	/* 100BASE-TX ability */
+#define MDIO_PMA_EXTABLE_10BT		0x0100	/* 10BASE-T ability */
+
+/* PHY XGXS lane state register. */
+#define MDIO_PHYXS_LNSTAT_SYNC0		0x0001
+#define MDIO_PHYXS_LNSTAT_SYNC1		0x0002
+#define MDIO_PHYXS_LNSTAT_SYNC2		0x0004
+#define MDIO_PHYXS_LNSTAT_SYNC3		0x0008
+#define MDIO_PHYXS_LNSTAT_ALIGN		0x1000
+
+/* PMA 10GBASE-T pair swap & polarity */
+#define MDIO_PMA_10GBT_SWAPPOL_ABNX	0x0001	/* Pair A/B uncrossed */
+#define MDIO_PMA_10GBT_SWAPPOL_CDNX	0x0002	/* Pair C/D uncrossed */
+#define MDIO_PMA_10GBT_SWAPPOL_AREV	0x0100	/* Pair A polarity reversed */
+#define MDIO_PMA_10GBT_SWAPPOL_BREV	0x0200	/* Pair B polarity reversed */
+#define MDIO_PMA_10GBT_SWAPPOL_CREV	0x0400	/* Pair C polarity reversed */
+#define MDIO_PMA_10GBT_SWAPPOL_DREV	0x0800	/* Pair D polarity reversed */
+
+/* PMA 10GBASE-T TX power register. */
+#define MDIO_PMA_10GBT_TXPWR_SHORT	0x0001	/* Short-reach mode */
+
+/* PMA 10GBASE-T SNR registers. */
+/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
+#define MDIO_PMA_10GBT_SNR_BIAS		0x8000
+#define MDIO_PMA_10GBT_SNR_MAX		127
+
+/* PMA 10GBASE-R FEC ability register. */
+#define MDIO_PMA_10GBR_FECABLE_ABLE	0x0001	/* FEC ability */
+#define MDIO_PMA_10GBR_FECABLE_ERRABLE	0x0002	/* FEC error indic. ability */
+
+/* PCS 10GBASE-R/-T status register 1. */
+#define MDIO_PCS_10GBRT_STAT1_BLKLK	0x0001	/* Block lock attained */
+
+/* PCS 10GBASE-R/-T status register 2. */
+#define MDIO_PCS_10GBRT_STAT2_ERR	0x00ff
+#define MDIO_PCS_10GBRT_STAT2_BER	0x3f00
+
+/* AN 10GBASE-T control register. */
+#define MDIO_AN_10GBT_CTRL_ADV10G	0x1000	/* Advertise 10GBASE-T */
+
+/* AN 10GBASE-T status register. */
+#define MDIO_AN_10GBT_STAT_LPTRR	0x0200	/* LP training reset req. */
+#define MDIO_AN_10GBT_STAT_LPLTABLE	0x0400	/* LP loop timing ability */
+#define MDIO_AN_10GBT_STAT_LP10G	0x0800	/* LP is 10GBT capable */
+#define MDIO_AN_10GBT_STAT_REMOK	0x1000	/* Remote OK */
+#define MDIO_AN_10GBT_STAT_LOCOK	0x2000	/* Local OK */
+#define MDIO_AN_10GBT_STAT_MS		0x4000	/* Master/slave config */
+#define MDIO_AN_10GBT_STAT_MSFLT	0x8000	/* Master/slave config fault */
+
+/* EEE Supported/Advertisement/LP Advertisement registers.
+ *
+ * EEE capability Register (3.20), Advertisement (7.60) and
+ * Link partner ability (7.61) registers have and can use the same identical
+ * bit masks.
+ */
+#define MDIO_AN_EEE_ADV_100TX	0x0002	/* Advertise 100TX EEE cap */
+#define MDIO_AN_EEE_ADV_1000T	0x0004	/* Advertise 1000T EEE cap */
+/* Note: the two defines above can be potentially used by the user-land
+ * and cannot remove them now.
+ * So, we define the new generic MDIO_EEE_100TX and MDIO_EEE_1000T macros
+ * using the previous ones (that can be considered obsolete).
+ */
+#define MDIO_EEE_100TX		MDIO_AN_EEE_ADV_100TX	/* 100TX EEE cap */
+#define MDIO_EEE_1000T		MDIO_AN_EEE_ADV_1000T	/* 1000T EEE cap */
+#define MDIO_EEE_10GT		0x0008	/* 10GT EEE cap */
+#define MDIO_EEE_1000KX		0x0010	/* 1000KX EEE cap */
+#define MDIO_EEE_10GKX4		0x0020	/* 10G KX4 EEE cap */
+#define MDIO_EEE_10GKR		0x0040	/* 10G KR EEE cap */
+
+/* LASI RX_ALARM control/status registers. */
+#define MDIO_PMA_LASI_RX_PHYXSLFLT	0x0001	/* PHY XS RX local fault */
+#define MDIO_PMA_LASI_RX_PCSLFLT	0x0008	/* PCS RX local fault */
+#define MDIO_PMA_LASI_RX_PMALFLT	0x0010	/* PMA/PMD RX local fault */
+#define MDIO_PMA_LASI_RX_OPTICPOWERFLT	0x0020	/* RX optical power fault */
+#define MDIO_PMA_LASI_RX_WISLFLT	0x0200	/* WIS local fault */
+
+/* LASI TX_ALARM control/status registers. */
+#define MDIO_PMA_LASI_TX_PHYXSLFLT	0x0001	/* PHY XS TX local fault */
+#define MDIO_PMA_LASI_TX_PCSLFLT	0x0008	/* PCS TX local fault */
+#define MDIO_PMA_LASI_TX_PMALFLT	0x0010	/* PMA/PMD TX local fault */
+#define MDIO_PMA_LASI_TX_LASERPOWERFLT	0x0080	/* Laser output power fault */
+#define MDIO_PMA_LASI_TX_LASERTEMPFLT	0x0100	/* Laser temperature fault */
+#define MDIO_PMA_LASI_TX_LASERBICURRFLT	0x0200	/* Laser bias current fault */
+
+/* LASI control/status registers. */
+#define MDIO_PMA_LASI_LSALARM		0x0001	/* LS_ALARM enable/status */
+#define MDIO_PMA_LASI_TXALARM		0x0002	/* TX_ALARM enable/status */
+#define MDIO_PMA_LASI_RXALARM		0x0004	/* RX_ALARM enable/status */
+
+/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
+
+#define MDIO_PHY_ID_C45			0x8000
+#define MDIO_PHY_ID_PRTAD		0x03e0
+#define MDIO_PHY_ID_DEVAD		0x001f
+#define MDIO_PHY_ID_C45_MASK						\
+	(MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
+
+#define MDIO_PRTAD_NONE			(-1)
+#define MDIO_DEVAD_NONE			(-1)
+#define MDIO_EMULATE_C22		4
+
+static inline __u16 mdio_phy_id_c45(int prtad, int devad)
+{
+	return MDIO_PHY_ID_C45 | (prtad << 5) | devad;
+}
+
+#endif /* __LINUX_MDIO_H__ */
diff --git a/include/linux/mii.h b/include/linux/mii.h
new file mode 100644
index 0000000..21db032
--- /dev/null
+++ b/include/linux/mii.h
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * linux/mii.h: definitions for MII-compatible transceivers
+ * Originally drivers/net/sunhme.h.
+ *
+ * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef __LINUX_MII_H__
+#define __LINUX_MII_H__
+
+/* Generic MII registers. */
+#define MII_BMCR		0x00	/* Basic mode control register */
+#define MII_BMSR		0x01	/* Basic mode status register  */
+#define MII_PHYSID1		0x02	/* PHYS ID 1                   */
+#define MII_PHYSID2		0x03	/* PHYS ID 2                   */
+#define MII_ADVERTISE		0x04	/* Advertisement control reg   */
+#define MII_LPA			0x05	/* Link partner ability reg    */
+#define MII_EXPANSION		0x06	/* Expansion register          */
+#define MII_CTRL1000		0x09	/* 1000BASE-T control          */
+#define MII_STAT1000		0x0a	/* 1000BASE-T status           */
+#define MII_MMD_CTRL		0x0d	/* MMD Access Control Register */
+#define MII_MMD_DATA		0x0e	/* MMD Access Data Register */
+#define MII_ESTATUS		0x0f	/* Extended Status             */
+#define MII_DCOUNTER		0x12	/* Disconnect counter          */
+#define MII_FCSCOUNTER		0x13	/* False carrier counter       */
+#define MII_NWAYTEST		0x14	/* N-way auto-neg test reg     */
+#define MII_RERRCOUNTER		0x15	/* Receive error counter       */
+#define MII_SREVISION		0x16	/* Silicon revision            */
+#define MII_RESV1		0x17	/* Reserved...                 */
+#define MII_LBRERROR		0x18	/* Lpback, rx, bypass error    */
+#define MII_PHYADDR		0x19	/* PHY address                 */
+#define MII_RESV2		0x1a	/* Reserved...                 */
+#define MII_TPISTATUS		0x1b	/* TPI status for 10mbps       */
+#define MII_NCONFIG		0x1c	/* Network interface config    */
+
+/* Basic mode control register. */
+#define BMCR_RESV		0x003f	/* Unused...                   */
+#define BMCR_SPEED1000		0x0040	/* MSB of Speed (1000)         */
+#define BMCR_CTST		0x0080	/* Collision test              */
+#define BMCR_FULLDPLX		0x0100	/* Full duplex                 */
+#define BMCR_ANRESTART		0x0200	/* Auto negotiation restart    */
+#define BMCR_ISOLATE		0x0400	/* Isolate data paths from MII */
+#define BMCR_PDOWN		0x0800	/* Enable low power state      */
+#define BMCR_ANENABLE		0x1000	/* Enable auto negotiation     */
+#define BMCR_SPEED100		0x2000	/* Select 100Mbps              */
+#define BMCR_LOOPBACK		0x4000	/* TXD loopback bits           */
+#define BMCR_RESET		0x8000	/* Reset to default state      */
+#define BMCR_SPEED10		0x0000	/* Select 10Mbps               */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP		0x0001	/* Ext-reg capability          */
+#define BMSR_JCD		0x0002	/* Jabber detected             */
+#define BMSR_LSTATUS		0x0004	/* Link status                 */
+#define BMSR_ANEGCAPABLE	0x0008	/* Able to do auto-negotiation */
+#define BMSR_RFAULT		0x0010	/* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE	0x0020	/* Auto-negotiation complete   */
+#define BMSR_RESV		0x00c0	/* Unused...                   */
+#define BMSR_ESTATEN		0x0100	/* Extended Status in R15      */
+#define BMSR_100HALF2		0x0200	/* Can do 100BASE-T2 HDX       */
+#define BMSR_100FULL2		0x0400	/* Can do 100BASE-T2 FDX       */
+#define BMSR_10HALF		0x0800	/* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL		0x1000	/* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF		0x2000	/* Can do 100mbps, half-duplex */
+#define BMSR_100FULL		0x4000	/* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4		0x8000	/* Can do 100mbps, 4k packets  */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT		0x001f	/* Selector bits               */
+#define ADVERTISE_CSMA		0x0001	/* Only selector supported     */
+#define ADVERTISE_10HALF	0x0020	/* Try for 10mbps half-duplex  */
+#define ADVERTISE_1000XFULL	0x0020	/* Try for 1000BASE-X full-duplex */
+#define ADVERTISE_10FULL	0x0040	/* Try for 10mbps full-duplex  */
+#define ADVERTISE_1000XHALF	0x0040	/* Try for 1000BASE-X half-duplex */
+#define ADVERTISE_100HALF	0x0080	/* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE	0x0080	/* Try for 1000BASE-X pause    */
+#define ADVERTISE_100FULL	0x0100	/* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM	0x0100	/* Try for 1000BASE-X asym pause */
+#define ADVERTISE_100BASE4	0x0200	/* Try for 100mbps 4k packets  */
+#define ADVERTISE_PAUSE_CAP	0x0400	/* Try for pause               */
+#define ADVERTISE_PAUSE_ASYM	0x0800	/* Try for asymetric pause     */
+#define ADVERTISE_RESV		0x1000	/* Unused...                   */
+#define ADVERTISE_RFAULT	0x2000	/* Say we can detect faults    */
+#define ADVERTISE_LPACK		0x4000	/* Ack link partners response  */
+#define ADVERTISE_NPAGE		0x8000	/* Next page bit               */
+
+#define ADVERTISE_FULL		(ADVERTISE_100FULL | ADVERTISE_10FULL | \
+				 ADVERTISE_CSMA)
+#define ADVERTISE_ALL		(ADVERTISE_10HALF | ADVERTISE_10FULL | \
+				 ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register. */
+#define LPA_SLCT		0x001f	/* Same as advertise selector  */
+#define LPA_10HALF		0x0020	/* Can do 10mbps half-duplex   */
+#define LPA_1000XFULL		0x0020	/* Can do 1000BASE-X full-duplex */
+#define LPA_10FULL		0x0040	/* Can do 10mbps full-duplex   */
+#define LPA_1000XHALF		0x0040	/* Can do 1000BASE-X half-duplex */
+#define LPA_100HALF		0x0080	/* Can do 100mbps half-duplex  */
+#define LPA_1000XPAUSE		0x0080	/* Can do 1000BASE-X pause     */
+#define LPA_100FULL		0x0100	/* Can do 100mbps full-duplex  */
+#define LPA_1000XPAUSE_ASYM	0x0100	/* Can do 1000BASE-X pause asym*/
+#define LPA_100BASE4		0x0200	/* Can do 100mbps 4k packets   */
+#define LPA_PAUSE_CAP		0x0400	/* Can pause                   */
+#define LPA_PAUSE_ASYM		0x0800	/* Can pause asymetrically     */
+#define LPA_RESV		0x1000	/* Unused...                   */
+#define LPA_RFAULT		0x2000	/* Link partner faulted        */
+#define LPA_LPACK		0x4000	/* Link partner acked us       */
+#define LPA_NPAGE		0x8000	/* Next page bit               */
+
+#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
+#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY		0x0001	/* Can do N-way auto-nego      */
+#define EXPANSION_LCWP		0x0002	/* Got new RX page code word   */
+#define EXPANSION_ENABLENPAGE	0x0004	/* This enables npage words    */
+#define EXPANSION_NPCAPABLE	0x0008	/* Link partner supports npage */
+#define EXPANSION_MFAULTS	0x0010	/* Multiple faults detected    */
+#define EXPANSION_RESV		0xffe0	/* Unused...                   */
+
+#define ESTATUS_1000_XFULL	0x8000	/* Can do 1000BX Full */
+#define ESTATUS_1000_XHALF	0x4000	/* Can do 1000BX Half */
+#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full          */
+#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half          */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1		0x00ff	/* Unused...                   */
+#define NWAYTEST_LOOPBACK	0x0100	/* Enable loopback for N-way   */
+#define NWAYTEST_RESV2		0xfe00	/* Unused...                   */
+
+/* 1000BASE-T Control register */
+#define ADVERTISE_1000FULL	0x0200  /* Advertise 1000BASE-T full duplex */
+#define ADVERTISE_1000HALF	0x0100  /* Advertise 1000BASE-T half duplex */
+#define CTL1000_AS_MASTER	0x0800
+#define CTL1000_ENABLE_MASTER	0x1000
+
+/* 1000BASE-T Status register */
+#define LPA_1000LOCALRXOK	0x2000	/* Link partner local receiver status */
+#define LPA_1000REMRXOK		0x1000	/* Link partner remote receiver status */
+#define LPA_1000FULL		0x0800	/* Link partner 1000BASE-T full duplex */
+#define LPA_1000HALF		0x0400	/* Link partner 1000BASE-T half duplex */
+
+/* Flow control flags */
+#define FLOW_CTRL_TX		0x01
+#define FLOW_CTRL_RX		0x02
+
+/* MMD Access Control register fields */
+#define MII_MMD_CTRL_DEVAD_MASK	0x1f	/* Mask MMD DEVAD*/
+#define MII_MMD_CTRL_ADDR	0x0000	/* Address */
+#define MII_MMD_CTRL_NOINCR	0x4000	/* no post increment */
+#define MII_MMD_CTRL_INCR_RDWT	0x8000	/* post increment on reads & writes */
+#define MII_MMD_CTRL_INCR_ON_WT	0xC000	/* post increment on writes only */
+
+/**
+ * mii_nway_result
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * Given a set of MII abilities, check each bit and returns the
+ * currently supported media, in the priority order defined by
+ * IEEE 802.3u.  We use LPA_xxx constants but note this is not the
+ * value of LPA solely, as described above.
+ *
+ * The one exception to IEEE 802.3u is that 100baseT4 is placed
+ * between 100T-full and 100T-half.  If your phy does not support
+ * 100T4 this is fine. If your phy places 100T4 elsewhere in the
+ * priority order, you will need to roll your own function.
+ */
+static inline unsigned int mii_nway_result (unsigned int negotiated)
+{
+	unsigned int ret;
+
+	if (negotiated & LPA_100FULL)
+		ret = LPA_100FULL;
+	else if (negotiated & LPA_100BASE4)
+		ret = LPA_100BASE4;
+	else if (negotiated & LPA_100HALF)
+		ret = LPA_100HALF;
+	else if (negotiated & LPA_10FULL)
+		ret = LPA_10FULL;
+	else
+		ret = LPA_10HALF;
+
+	return ret;
+}
+
+/**
+ * mii_duplex
+ * @duplex_lock: Non-zero if duplex is locked at full
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * A small helper function for a common case.  Returns one
+ * if the media is operating or locked at full duplex, and
+ * returns zero otherwise.
+ */
+static inline unsigned int mii_duplex (unsigned int duplex_lock,
+				       unsigned int negotiated)
+{
+	if (duplex_lock)
+		return 1;
+	if (mii_nway_result(negotiated) & LPA_DUPLEX)
+		return 1;
+	return 0;
+}
+
+/**
+ * mii_resolve_flowctrl_fdx
+ * @lcladv: value of MII ADVERTISE register
+ * @rmtadv: value of MII LPA register
+ *
+ * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3
+ */
+static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv)
+{
+	u8 cap = 0;
+
+	if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) {
+		cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
+	} else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) {
+		if (lcladv & ADVERTISE_PAUSE_CAP)
+			cap = FLOW_CTRL_RX;
+		else if (rmtadv & ADVERTISE_PAUSE_CAP)
+			cap = FLOW_CTRL_TX;
+	}
+
+	return cap;
+}
+
+#endif /* __LINUX_MII_H__ */
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
new file mode 100644
index 0000000..7239eb1
--- /dev/null
+++ b/include/linux/mtd/bbm.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  linux/include/linux/mtd/bbm.h
+ *
+ *  NAND family Bad Block Management (BBM) header file
+ *    - Bad Block Table (BBT) implementation
+ *
+ *  Copyright © 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  Copyright © 2000-2005
+ *  Thomas Gleixner <tglx@linuxtronix.de>
+ *
+ */
+#ifndef __LINUX_MTD_BBM_H
+#define __LINUX_MTD_BBM_H
+
+/* The maximum number of NAND chips in an array */
+#ifndef CONFIG_SYS_NAND_MAX_CHIPS
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#endif
+
+/**
+ * struct nand_bbt_descr - bad block table descriptor
+ * @options:	options for this descriptor
+ * @pages:	the page(s) where we find the bbt, used with option BBT_ABSPAGE
+ *		when bbt is searched, then we store the found bbts pages here.
+ *		Its an array and supports up to 8 chips now
+ * @offs:	offset of the pattern in the oob area of the page
+ * @veroffs:	offset of the bbt version counter in the oob are of the page
+ * @version:	version read from the bbt page during scan
+ * @len:	length of the pattern, if 0 no pattern check is performed
+ * @maxblocks:	maximum number of blocks to search for a bbt. This number of
+ *		blocks is reserved at the end of the device where the tables are
+ *		written.
+ * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
+ *              bad) block in the stored bbt
+ * @pattern:	pattern to identify bad block table or factory marked good /
+ *		bad blocks, can be NULL, if len = 0
+ *
+ * Descriptor for the bad block table marker and the descriptor for the
+ * pattern which identifies good and bad blocks. The assumption is made
+ * that the pattern and the version count are always located in the oob area
+ * of the first block.
+ */
+struct nand_bbt_descr {
+	int options;
+	int pages[CONFIG_SYS_NAND_MAX_CHIPS];
+	int offs;
+	int veroffs;
+	uint8_t version[CONFIG_SYS_NAND_MAX_CHIPS];
+	int len;
+	int maxblocks;
+	int reserved_block_code;
+	uint8_t *pattern;
+};
+
+/* Options for the bad block table descriptors */
+
+/* The number of bits used per block in the bbt on the device */
+#define NAND_BBT_NRBITS_MSK	0x0000000F
+#define NAND_BBT_1BIT		0x00000001
+#define NAND_BBT_2BIT		0x00000002
+#define NAND_BBT_4BIT		0x00000004
+#define NAND_BBT_8BIT		0x00000008
+/* The bad block table is in the last good block of the device */
+#define NAND_BBT_LASTBLOCK	0x00000010
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_ABSPAGE	0x00000020
+/* bbt is stored per chip on multichip devices */
+#define NAND_BBT_PERCHIP	0x00000080
+/* bbt has a version counter at offset veroffs */
+#define NAND_BBT_VERSION	0x00000100
+/* Create a bbt if none exists */
+#define NAND_BBT_CREATE		0x00000200
+/*
+ * Create an empty BBT with no vendor information. Vendor's information may be
+ * unavailable, for example, if the NAND controller has a different data and OOB
+ * layout or if this information is already purged. Must be used in conjunction
+ * with NAND_BBT_CREATE.
+ */
+#define NAND_BBT_CREATE_EMPTY	0x00000400
+/* Write bbt if neccecary */
+#define NAND_BBT_WRITE		0x00002000
+/* Read and write back block contents when writing bbt */
+#define NAND_BBT_SAVECONTENT	0x00004000
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE	0x00008000
+/* Search good / bad pattern on the last page of the eraseblock */
+#define NAND_BBT_SCANLASTPAGE	0x00010000
+/*
+ * Use a flash based bad block table. By default, OOB identifier is saved in
+ * OOB area. This option is passed to the default bad block table function.
+ */
+#define NAND_BBT_USE_FLASH	0x00020000
+/*
+ * Do not store flash based bad block table marker in the OOB area; store it
+ * in-band.
+ */
+#define NAND_BBT_NO_OOB		0x00040000
+/*
+ * Do not write new bad block markers to OOB; useful, e.g., when ECC covers
+ * entire spare area. Must be used with NAND_BBT_USE_FLASH.
+ */
+#define NAND_BBT_NO_OOB_BBM	0x00080000
+
+/*
+ * Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
+ * was allocated dynamicaly and must be freed in nand_release(). Has no meaning
+ * in nand_chip.bbt_options.
+ */
+#define NAND_BBT_DYNAMICSTRUCT	0x80000000
+
+/* The maximum number of blocks to scan for a bbt */
+#define NAND_BBT_SCAN_MAXBLOCKS	4
+
+/*
+ * Constants for oob configuration
+ */
+#define NAND_SMALL_BADBLOCK_POS		5
+#define NAND_LARGE_BADBLOCK_POS		0
+#define ONENAND_BADBLOCK_POS		0
+
+/*
+ * Bad block scanning errors
+ */
+#define ONENAND_BBT_READ_ERROR		1
+#define ONENAND_BBT_READ_ECC_ERROR	2
+#define ONENAND_BBT_READ_FATAL_ERROR	4
+
+/**
+ * struct bbm_info - [GENERIC] Bad Block Table data structure
+ * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
+ * @badblockpos:	[INTERN] position of the bad block marker in the oob area
+ * @options:		options for this descriptor
+ * @bbt:		[INTERN] bad block table pointer
+ * @isbad_bbt:		function to determine if a block is bad
+ * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for
+ *			initial bad block scan
+ * @priv:		[OPTIONAL] pointer to private bbm date
+ */
+struct bbm_info {
+	int bbt_erase_shift;
+	int badblockpos;
+	int options;
+
+	uint8_t *bbt;
+
+	int (*isbad_bbt)(struct mtd_info *mtd, loff_t ofs, int allowbbt);
+
+	/* TODO Add more NAND specific fileds */
+	struct nand_bbt_descr *badblock_pattern;
+
+	void *priv;
+};
+
+/* OneNAND BBT interface */
+extern int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int onenand_default_bbt(struct mtd_info *mtd);
+
+#endif	/* __LINUX_MTD_BBM_H */
diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h
new file mode 100644
index 0000000..3555518
--- /dev/null
+++ b/include/linux/mtd/cfi.h
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> et al.
+ *
+ */
+
+#ifndef __MTD_CFI_H__
+#define __MTD_CFI_H__
+
+#define CFI_MFR_ANY		0xFFFF
+#define CFI_ID_ANY		0xFFFF
+#define CFI_MFR_CONTINUATION	0x007F
+
+#define CFI_MFR_AMD		0x0001
+#define CFI_MFR_AMIC		0x0037
+#define CFI_MFR_ATMEL		0x001F
+#define CFI_MFR_EON		0x001C
+#define CFI_MFR_FUJITSU		0x0004
+#define CFI_MFR_HYUNDAI		0x00AD
+#define CFI_MFR_INTEL		0x0089
+#define CFI_MFR_MACRONIX	0x00C2
+#define CFI_MFR_NEC		0x0010
+#define CFI_MFR_PMC		0x009D
+#define CFI_MFR_SAMSUNG		0x00EC
+#define CFI_MFR_SHARP		0x00B0
+#define CFI_MFR_SST		0x00BF
+#define CFI_MFR_ST		0x0020 /* STMicroelectronics */
+#define CFI_MFR_MICRON		0x002C	/* Micron */
+#define CFI_MFR_TOSHIBA		0x0098
+#define CFI_MFR_WINBOND		0x00DA
+
+#endif /* __MTD_CFI_H__ */
diff --git a/include/linux/mtd/concat.h b/include/linux/mtd/concat.h
new file mode 100644
index 0000000..c57e973
--- /dev/null
+++ b/include/linux/mtd/concat.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * MTD device concatenation layer definitions
+ *
+ * Copyright © 2002      Robert Kaiser <rkaiser@sysgo.de>
+ *
+ */
+
+#ifndef MTD_CONCAT_H
+#define MTD_CONCAT_H
+
+struct mtd_info *mtd_concat_create(
+    struct mtd_info *subdev[],  /* subdevices to concatenate */
+    int num_devs,               /* number of subdevices      */
+#ifndef __UBOOT__
+    const char *name);          /* name for the new device   */
+#else
+    char *name);          /* name for the new device   */
+#endif
+
+void mtd_concat_destroy(struct mtd_info *mtd);
+
+#endif
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
new file mode 100644
index 0000000..d57f8da
--- /dev/null
+++ b/include/linux/mtd/doc2000.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Linux driver for Disk-On-Chip devices
+ *
+ * Copyright © 1999 Machine Vision Holdings, Inc.
+ * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
+ * Copyright © 2002-2003 Greg Ungerer <gerg@snapgear.com>
+ * Copyright © 2002-2003 SnapGear Inc
+ *
+ */
+
+#ifndef __MTD_DOC2000_H__
+#define __MTD_DOC2000_H__
+
+#include <linux/mtd/mtd.h>
+#if 0
+#include <linux/mutex.h>
+#endif
+
+#define DoC_Sig1 0
+#define DoC_Sig2 1
+
+#define DoC_ChipID		0x1000
+#define DoC_DOCStatus		0x1001
+#define DoC_DOCControl		0x1002
+#define DoC_FloorSelect		0x1003
+#define DoC_CDSNControl		0x1004
+#define DoC_CDSNDeviceSelect	0x1005
+#define DoC_ECCConf		0x1006
+#define DoC_2k_ECCStatus	0x1007
+
+#define DoC_CDSNSlowIO		0x100d
+#define DoC_ECCSyndrome0	0x1010
+#define DoC_ECCSyndrome1	0x1011
+#define DoC_ECCSyndrome2	0x1012
+#define DoC_ECCSyndrome3	0x1013
+#define DoC_ECCSyndrome4	0x1014
+#define DoC_ECCSyndrome5	0x1015
+#define DoC_AliasResolution	0x101b
+#define DoC_ConfigInput		0x101c
+#define DoC_ReadPipeInit	0x101d
+#define DoC_WritePipeTerm	0x101e
+#define DoC_LastDataRead	0x101f
+#define DoC_NOP			0x1020
+
+#define DoC_Mil_CDSN_IO		0x0800
+#define DoC_2k_CDSN_IO		0x1800
+
+#define DoC_Mplus_NOP			0x1002
+#define DoC_Mplus_AliasResolution	0x1004
+#define DoC_Mplus_DOCControl		0x1006
+#define DoC_Mplus_AccessStatus		0x1008
+#define DoC_Mplus_DeviceSelect		0x1008
+#define DoC_Mplus_Configuration		0x100a
+#define DoC_Mplus_OutputControl		0x100c
+#define DoC_Mplus_FlashControl		0x1020
+#define DoC_Mplus_FlashSelect 		0x1022
+#define DoC_Mplus_FlashCmd		0x1024
+#define DoC_Mplus_FlashAddress		0x1026
+#define DoC_Mplus_FlashData0		0x1028
+#define DoC_Mplus_FlashData1		0x1029
+#define DoC_Mplus_ReadPipeInit		0x102a
+#define DoC_Mplus_LastDataRead		0x102c
+#define DoC_Mplus_LastDataRead1		0x102d
+#define DoC_Mplus_WritePipeTerm 	0x102e
+#define DoC_Mplus_ECCSyndrome0		0x1040
+#define DoC_Mplus_ECCSyndrome1		0x1041
+#define DoC_Mplus_ECCSyndrome2		0x1042
+#define DoC_Mplus_ECCSyndrome3		0x1043
+#define DoC_Mplus_ECCSyndrome4		0x1044
+#define DoC_Mplus_ECCSyndrome5		0x1045
+#define DoC_Mplus_ECCConf 		0x1046
+#define DoC_Mplus_Toggle		0x1046
+#define DoC_Mplus_DownloadStatus	0x1074
+#define DoC_Mplus_CtrlConfirm		0x1076
+#define DoC_Mplus_Power			0x1fff
+
+/* How to access the device?
+ * On ARM, it'll be mmap'd directly with 32-bit wide accesses.
+ * On PPC, it's mmap'd and 16-bit wide.
+ * Others use readb/writeb
+ */
+#if defined(__arm__)
+#define ReadDOC_(adr, reg)      ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2))))
+#define WriteDOC_(d, adr, reg)  do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0)
+#define DOC_IOREMAP_LEN 0x8000
+#elif defined(__ppc__)
+#define ReadDOC_(adr, reg)      ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1))))
+#define WriteDOC_(d, adr, reg)  do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0)
+#define DOC_IOREMAP_LEN 0x4000
+#else
+#define ReadDOC_(adr, reg)      readb((void __iomem *)(adr) + (reg))
+#define WriteDOC_(d, adr, reg)  writeb(d, (void __iomem *)(adr) + (reg))
+#define DOC_IOREMAP_LEN 0x2000
+
+#endif
+
+#if defined(__i386__) || defined(__x86_64__)
+#define USE_MEMCPY
+#endif
+
+/* These are provided to directly use the DoC_xxx defines */
+#define ReadDOC(adr, reg)      ReadDOC_(adr,DoC_##reg)
+#define WriteDOC(d, adr, reg)  WriteDOC_(d,adr,DoC_##reg)
+
+#define DOC_MODE_RESET		0
+#define DOC_MODE_NORMAL		1
+#define DOC_MODE_RESERVED1	2
+#define DOC_MODE_RESERVED2	3
+
+#define DOC_MODE_CLR_ERR	0x80
+#define	DOC_MODE_RST_LAT	0x10
+#define	DOC_MODE_BDECT		0x08
+#define DOC_MODE_MDWREN	0x04
+
+#define DOC_ChipID_Doc2k	0x20
+#define DOC_ChipID_Doc2kTSOP	0x21	/* internal number for MTD */
+#define DOC_ChipID_DocMil	0x30
+#define DOC_ChipID_DocMilPlus32	0x40
+#define DOC_ChipID_DocMilPlus16	0x41
+
+#define CDSN_CTRL_FR_B		0x80
+#define CDSN_CTRL_FR_B0		0x40
+#define CDSN_CTRL_FR_B1		0x80
+
+#define CDSN_CTRL_ECC_IO	0x20
+#define CDSN_CTRL_FLASH_IO	0x10
+#define CDSN_CTRL_WP		0x08
+#define CDSN_CTRL_ALE		0x04
+#define CDSN_CTRL_CLE		0x02
+#define CDSN_CTRL_CE		0x01
+
+#define DOC_ECC_RESET		0
+#define DOC_ECC_ERROR		0x80
+#define DOC_ECC_RW		0x20
+#define DOC_ECC__EN		0x08
+#define DOC_TOGGLE_BIT		0x04
+#define DOC_ECC_RESV		0x02
+#define DOC_ECC_IGNORE		0x01
+
+#define DOC_FLASH_CE		0x80
+#define DOC_FLASH_WP		0x40
+#define DOC_FLASH_BANK		0x02
+
+/* We have to also set the reserved bit 1 for enable */
+#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV)
+#define DOC_ECC_DIS (DOC_ECC_RESV)
+
+struct Nand {
+	char floor, chip;
+	unsigned long curadr;
+	unsigned char curmode;
+	/* Also some erase/write/pipeline info when we get that far */
+};
+
+#define MAX_FLOORS 4
+#define MAX_CHIPS 4
+
+#define MAX_FLOORS_MIL 1
+#define MAX_CHIPS_MIL 1
+
+#define MAX_FLOORS_MPLUS 2
+#define MAX_CHIPS_MPLUS 1
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+struct DiskOnChip {
+	unsigned long physadr;
+	void __iomem *virtadr;
+	unsigned long totlen;
+	unsigned char ChipID; /* Type of DiskOnChip */
+	int ioreg;
+
+	unsigned long mfr; /* Flash IDs - only one type of flash per device */
+	unsigned long id;
+	int chipshift;
+	char page256;
+	char pageadrlen;
+	char interleave; /* Internal interleaving - Millennium Plus style */
+	unsigned long erasesize;
+
+	int curfloor;
+	int curchip;
+
+	int numchips;
+	struct Nand *chips;
+	struct mtd_info *nextdoc;
+/* XXX U-BOOT XXX */
+#if 0
+	struct mutex lock;
+#endif
+};
+
+int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]);
+
+/* XXX U-BOOT XXX */
+#if 1
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA   0x98
+#define NAND_MFR_SAMSUNG   0xec
+#endif
+
+#endif /* __MTD_DOC2000_H__ */
diff --git a/include/linux/mtd/flashchip.h b/include/linux/mtd/flashchip.h
new file mode 100644
index 0000000..666480d
--- /dev/null
+++ b/include/linux/mtd/flashchip.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright © 2000      Red Hat UK Limited
+ * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
+ *
+ */
+
+#ifndef __MTD_FLASHCHIP_H__
+#define __MTD_FLASHCHIP_H__
+
+#ifndef __UBOOT__
+/* For spinlocks. sched.h includes spinlock.h from whichever directory it
+ * happens to be in - so we don't have to care whether we're on 2.2, which
+ * has asm/spinlock.h, or 2.4, which has linux/spinlock.h
+ */
+#include <linux/sched.h>
+#include <linux/mutex.h>
+#endif
+
+typedef enum {
+	FL_READY,
+	FL_STATUS,
+	FL_CFI_QUERY,
+	FL_JEDEC_QUERY,
+	FL_ERASING,
+	FL_ERASE_SUSPENDING,
+	FL_ERASE_SUSPENDED,
+	FL_WRITING,
+	FL_WRITING_TO_BUFFER,
+	FL_OTP_WRITE,
+	FL_WRITE_SUSPENDING,
+	FL_WRITE_SUSPENDED,
+	FL_PM_SUSPENDED,
+	FL_SYNCING,
+	FL_UNLOADING,
+	FL_LOCKING,
+	FL_UNLOCKING,
+	FL_POINT,
+	FL_XIP_WHILE_ERASING,
+	FL_XIP_WHILE_WRITING,
+	FL_SHUTDOWN,
+	/* These 2 come from nand_state_t, which has been unified here */
+	FL_READING,
+	FL_CACHEDPRG,
+	/* These 4 come from onenand_state_t, which has been unified here */
+	FL_RESETING,
+	FL_OTPING,
+	FL_PREPARING_ERASE,
+	FL_VERIFYING_ERASE,
+
+	FL_UNKNOWN
+} flstate_t;
+
+
+
+/* NOTE: confusingly, this can be used to refer to more than one chip at a time,
+   if they're interleaved.  This can even refer to individual partitions on
+   the same physical chip when present. */
+
+struct flchip {
+	unsigned long start; /* Offset within the map */
+	//	unsigned long len;
+	/* We omit len for now, because when we group them together
+	   we insist that they're all of the same size, and the chip size
+	   is held in the next level up. If we get more versatile later,
+	   it'll make it a damn sight harder to find which chip we want from
+	   a given offset, and we'll want to add the per-chip length field
+	   back in.
+	*/
+	int ref_point_counter;
+	flstate_t state;
+	flstate_t oldstate;
+
+	unsigned int write_suspended:1;
+	unsigned int erase_suspended:1;
+	unsigned long in_progress_block_addr;
+
+	struct mutex mutex;
+#ifndef __UBOOT__
+	wait_queue_head_t wq; /* Wait on here when we're waiting for the chip
+			     to be ready */
+#endif
+	int word_write_time;
+	int buffer_write_time;
+	int erase_time;
+
+	int word_write_time_max;
+	int buffer_write_time_max;
+	int erase_time_max;
+
+	void *priv;
+};
+
+/* This is used to handle contention on write/erase operations
+   between partitions of the same physical chip. */
+struct flchip_shared {
+	struct mutex lock;
+	struct flchip *writing;
+	struct flchip *erasing;
+};
+
+
+#endif /* __MTD_FLASHCHIP_H__ */
diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h
new file mode 100644
index 0000000..9999993
--- /dev/null
+++ b/include/linux/mtd/fsl_upm.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * FSL UPM NAND driver
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ */
+
+#ifndef __LINUX_MTD_NAND_FSL_UPM
+#define __LINUX_MTD_NAND_FSL_UPM
+
+#include <linux/mtd/rawnand.h>
+
+#define FSL_UPM_WAIT_RUN_PATTERN  0x1
+#define FSL_UPM_WAIT_WRITE_BYTE   0x2
+#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
+
+struct fsl_upm {
+	void __iomem *mdr;
+	void __iomem *mxmr;
+	void __iomem *mar;
+	void __iomem *io_addr;
+};
+
+struct fsl_upm_nand {
+	struct fsl_upm upm;
+
+	int width;
+	int upm_cmd_offset;
+	int upm_addr_offset;
+	int upm_mar_chip_offset;
+	int wait_flags;
+	int (*dev_ready)(int chip_nr);
+	int chip_delay;
+	int chip_offset;
+	int chip_nr;
+
+	/* no need to fill */
+	int last_ctrl;
+};
+
+extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
+
+#endif
diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h
new file mode 100644
index 0000000..6079f9e
--- /dev/null
+++ b/include/linux/mtd/fsmc_nand.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#ifndef __FSMC_NAND_H__
+#define __FSMC_NAND_H__
+
+#include <linux/mtd/rawnand.h>
+
+struct fsmc_regs {
+	u32 ctrl;			/* 0x00 */
+	u8 reserved_1[0x40 - 0x04];
+	u32 pc;				/* 0x40 */
+	u32 sts;			/* 0x44 */
+	u32 comm;			/* 0x48 */
+	u32 attrib;			/* 0x4c */
+	u32 ioata;			/* 0x50 */
+	u32 ecc1;			/* 0x54 */
+	u32 ecc2;			/* 0x58 */
+	u32 ecc3;			/* 0x5c */
+	u8 reserved_2[0xfe0 - 0x60];
+	u32 peripid0;			/* 0xfe0 */
+	u32 peripid1;			/* 0xfe4 */
+	u32 peripid2;			/* 0xfe8 */
+	u32 peripid3;			/* 0xfec */
+	u32 pcellid0;			/* 0xff0 */
+	u32 pcellid1;			/* 0xff4 */
+	u32 pcellid2;			/* 0xff8 */
+	u32 pcellid3;			/* 0xffc */
+};
+
+/* ctrl register definitions */
+#define FSMC_WP			(1 << 7)
+
+/* pc register definitions */
+#define FSMC_RESET		(1 << 0)
+#define FSMC_WAITON		(1 << 1)
+#define FSMC_ENABLE		(1 << 2)
+#define FSMC_DEVTYPE_NAND	(1 << 3)
+#define FSMC_DEVWID_8		(0 << 4)
+#define FSMC_DEVWID_16		(1 << 4)
+#define FSMC_ECCEN		(1 << 6)
+#define FSMC_ECCPLEN_512	(0 << 7)
+#define FSMC_ECCPLEN_256	(1 << 7)
+#define FSMC_TCLR_1		(1 << 9)
+#define FSMC_TAR_1		(1 << 13)
+
+/* sts register definitions */
+#define FSMC_CODE_RDY		(1 << 15)
+
+/* comm register definitions */
+#define FSMC_TSET_0		(0 << 0)
+#define FSMC_TWAIT_6		(6 << 8)
+#define FSMC_THOLD_4		(4 << 16)
+#define FSMC_THIZ_1		(1 << 24)
+
+/* peripid2 register definitions */
+#define FSMC_REVISION_MSK	(0xf)
+#define FSMC_REVISION_SHFT	(0x4)
+
+#define FSMC_VER8		0x8
+
+/*
+ * There are 13 bytes of ecc for every 512 byte block and it has to be read
+ * consecutively and immediately after the 512 byte data block for hardware to
+ * generate the error bit offsets
+ * Managing the ecc bytes in the following way is easier. This way is similar to
+ * oobfree structure maintained already in u-boot nand driver
+ */
+#define FSMC_MAX_ECCPLACE_ENTRIES	32
+
+struct fsmc_nand_eccplace {
+	u32 offset;
+	u32 length;
+};
+
+struct fsmc_eccplace {
+	struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES];
+};
+
+extern int fsmc_nand_init(struct nand_chip *nand);
+#endif
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
new file mode 100644
index 0000000..e3549f0
--- /dev/null
+++ b/include/linux/mtd/mtd.h
@@ -0,0 +1,608 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> et al.
+ *
+ */
+
+#ifndef __MTD_MTD_H__
+#define __MTD_MTD_H__
+
+#ifndef __UBOOT__
+#include <linux/types.h>
+#include <linux/uio.h>
+#include <linux/notifier.h>
+#include <linux/device.h>
+
+#include <mtd/mtd-abi.h>
+
+#include <asm/div64.h>
+#else
+#include <linux/compat.h>
+#include <mtd/mtd-abi.h>
+#include <linux/errno.h>
+#include <linux/list.h>
+#include <div64.h>
+#if IS_ENABLED(CONFIG_DM)
+#include <dm/device.h>
+#endif
+
+#define MAX_MTD_DEVICES 32
+#endif
+
+#define MTD_ERASE_PENDING	0x01
+#define MTD_ERASING		0x02
+#define MTD_ERASE_SUSPEND	0x04
+#define MTD_ERASE_DONE		0x08
+#define MTD_ERASE_FAILED	0x10
+
+#define MTD_FAIL_ADDR_UNKNOWN -1LL
+
+/*
+ * If the erase fails, fail_addr might indicate exactly which block failed. If
+ * fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level
+ * or was not specific to any particular block.
+ */
+struct erase_info {
+	struct mtd_info *mtd;
+	uint64_t addr;
+	uint64_t len;
+	uint64_t fail_addr;
+	u_long time;
+	u_long retries;
+	unsigned dev;
+	unsigned cell;
+	void (*callback) (struct erase_info *self);
+	u_long priv;
+	u_char state;
+	struct erase_info *next;
+	int scrub;
+};
+
+struct mtd_erase_region_info {
+	uint64_t offset;		/* At which this region starts, from the beginning of the MTD */
+	uint32_t erasesize;		/* For this region */
+	uint32_t numblocks;		/* Number of blocks of erasesize in this region */
+	unsigned long *lockmap;		/* If keeping bitmap of locks */
+};
+
+/**
+ * struct mtd_oob_ops - oob operation operands
+ * @mode:	operation mode
+ *
+ * @len:	number of data bytes to write/read
+ *
+ * @retlen:	number of data bytes written/read
+ *
+ * @ooblen:	number of oob bytes to write/read
+ * @oobretlen:	number of oob bytes written/read
+ * @ooboffs:	offset of oob data in the oob area (only relevant when
+ *		mode = MTD_OPS_PLACE_OOB or MTD_OPS_RAW)
+ * @datbuf:	data buffer - if NULL only oob data are read/written
+ * @oobbuf:	oob data buffer
+ */
+struct mtd_oob_ops {
+	unsigned int	mode;
+	size_t		len;
+	size_t		retlen;
+	size_t		ooblen;
+	size_t		oobretlen;
+	uint32_t	ooboffs;
+	uint8_t		*datbuf;
+	uint8_t		*oobbuf;
+};
+
+#ifdef CONFIG_SYS_NAND_MAX_OOBFREE
+#define MTD_MAX_OOBFREE_ENTRIES_LARGE	CONFIG_SYS_NAND_MAX_OOBFREE
+#else
+#define MTD_MAX_OOBFREE_ENTRIES_LARGE	32
+#endif
+
+#ifdef CONFIG_SYS_NAND_MAX_ECCPOS
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE	CONFIG_SYS_NAND_MAX_ECCPOS
+#else
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE	680
+#endif
+/**
+ * struct mtd_oob_region - oob region definition
+ * @offset: region offset
+ * @length: region length
+ *
+ * This structure describes a region of the OOB area, and is used
+ * to retrieve ECC or free bytes sections.
+ * Each section is defined by an offset within the OOB area and a
+ * length.
+ */
+struct mtd_oob_region {
+	u32 offset;
+	u32 length;
+};
+
+/*
+ * struct mtd_ooblayout_ops - NAND OOB layout operations
+ * @ecc: function returning an ECC region in the OOB area.
+ *	 Should return -ERANGE if %section exceeds the total number of
+ *	 ECC sections.
+ * @free: function returning a free region in the OOB area.
+ *	  Should return -ERANGE if %section exceeds the total number of
+ *	  free sections.
+ */
+struct mtd_ooblayout_ops {
+	int (*ecc)(struct mtd_info *mtd, int section,
+		   struct mtd_oob_region *oobecc);
+	int (*free)(struct mtd_info *mtd, int section,
+		    struct mtd_oob_region *oobfree);
+};
+
+/*
+ * Internal ECC layout control structure. For historical reasons, there is a
+ * similar, smaller struct nand_ecclayout_user (in mtd-abi.h) that is retained
+ * for export to user-space via the ECCGETLAYOUT ioctl.
+ * nand_ecclayout should be expandable in the future simply by the above macros.
+ */
+struct nand_ecclayout {
+	__u32 eccbytes;
+	__u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
+	__u32 oobavail;
+	struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
+};
+
+struct module;	/* only needed for owner field in mtd_info */
+
+struct mtd_info {
+	u_char type;
+	uint32_t flags;
+	uint64_t size;	 // Total size of the MTD
+
+	/* "Major" erase size for the device. Naïve users may take this
+	 * to be the only erase size available, or may use the more detailed
+	 * information below if they desire
+	 */
+	uint32_t erasesize;
+	/* Minimal writable flash unit size. In case of NOR flash it is 1 (even
+	 * though individual bits can be cleared), in case of NAND flash it is
+	 * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR
+	 * it is of ECC block size, etc. It is illegal to have writesize = 0.
+	 * Any driver registering a struct mtd_info must ensure a writesize of
+	 * 1 or larger.
+	 */
+	uint32_t writesize;
+
+	/*
+	 * Size of the write buffer used by the MTD. MTD devices having a write
+	 * buffer can write multiple writesize chunks at a time. E.g. while
+	 * writing 4 * writesize bytes to a device with 2 * writesize bytes
+	 * buffer the MTD driver can (but doesn't have to) do 2 writesize
+	 * operations, but not 4. Currently, all NANDs have writebufsize
+	 * equivalent to writesize (NAND page size). Some NOR flashes do have
+	 * writebufsize greater than writesize.
+	 */
+	uint32_t writebufsize;
+
+	uint32_t oobsize;   // Amount of OOB data per block (e.g. 16)
+	uint32_t oobavail;  // Available OOB bytes per block
+
+	/*
+	 * If erasesize is a power of 2 then the shift is stored in
+	 * erasesize_shift otherwise erasesize_shift is zero. Ditto writesize.
+	 */
+	unsigned int erasesize_shift;
+	unsigned int writesize_shift;
+	/* Masks based on erasesize_shift and writesize_shift */
+	unsigned int erasesize_mask;
+	unsigned int writesize_mask;
+
+	/*
+	 * read ops return -EUCLEAN if max number of bitflips corrected on any
+	 * one region comprising an ecc step equals or exceeds this value.
+	 * Settable by driver, else defaults to ecc_strength.  User can override
+	 * in sysfs.  N.B. The meaning of the -EUCLEAN return code has changed;
+	 * see Documentation/ABI/testing/sysfs-class-mtd for more detail.
+	 */
+	unsigned int bitflip_threshold;
+
+	// Kernel-only stuff starts here.
+#ifndef __UBOOT__
+	const char *name;
+#else
+	char *name;
+#endif
+	int index;
+
+	/* OOB layout description */
+	const struct mtd_ooblayout_ops *ooblayout;
+
+	/* ECC layout structure pointer - read only! */
+	struct nand_ecclayout *ecclayout;
+
+	/* the ecc step size. */
+	unsigned int ecc_step_size;
+
+	/* max number of correctible bit errors per ecc step */
+	unsigned int ecc_strength;
+
+	/* Data for variable erase regions. If numeraseregions is zero,
+	 * it means that the whole device has erasesize as given above.
+	 */
+	int numeraseregions;
+	struct mtd_erase_region_info *eraseregions;
+
+	/*
+	 * Do not call via these pointers, use corresponding mtd_*()
+	 * wrappers instead.
+	 */
+	int (*_erase) (struct mtd_info *mtd, struct erase_info *instr);
+#ifndef __UBOOT__
+	int (*_point) (struct mtd_info *mtd, loff_t from, size_t len,
+		       size_t *retlen, void **virt, resource_size_t *phys);
+	int (*_unpoint) (struct mtd_info *mtd, loff_t from, size_t len);
+#endif
+	unsigned long (*_get_unmapped_area) (struct mtd_info *mtd,
+					     unsigned long len,
+					     unsigned long offset,
+					     unsigned long flags);
+	int (*_read) (struct mtd_info *mtd, loff_t from, size_t len,
+		      size_t *retlen, u_char *buf);
+	int (*_write) (struct mtd_info *mtd, loff_t to, size_t len,
+		       size_t *retlen, const u_char *buf);
+	int (*_panic_write) (struct mtd_info *mtd, loff_t to, size_t len,
+			     size_t *retlen, const u_char *buf);
+	int (*_read_oob) (struct mtd_info *mtd, loff_t from,
+			  struct mtd_oob_ops *ops);
+	int (*_write_oob) (struct mtd_info *mtd, loff_t to,
+			   struct mtd_oob_ops *ops);
+	int (*_get_fact_prot_info) (struct mtd_info *mtd, size_t len,
+				    size_t *retlen, struct otp_info *buf);
+	int (*_read_fact_prot_reg) (struct mtd_info *mtd, loff_t from,
+				    size_t len, size_t *retlen, u_char *buf);
+	int (*_get_user_prot_info) (struct mtd_info *mtd, size_t len,
+				    size_t *retlen, struct otp_info *buf);
+	int (*_read_user_prot_reg) (struct mtd_info *mtd, loff_t from,
+				    size_t len, size_t *retlen, u_char *buf);
+	int (*_write_user_prot_reg) (struct mtd_info *mtd, loff_t to,
+				     size_t len, size_t *retlen, u_char *buf);
+	int (*_lock_user_prot_reg) (struct mtd_info *mtd, loff_t from,
+				    size_t len);
+#ifndef __UBOOT__
+	int (*_writev) (struct mtd_info *mtd, const struct kvec *vecs,
+			unsigned long count, loff_t to, size_t *retlen);
+#endif
+	void (*_sync) (struct mtd_info *mtd);
+	int (*_lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
+	int (*_unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
+	int (*_is_locked) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
+	int (*_block_isreserved) (struct mtd_info *mtd, loff_t ofs);
+	int (*_block_isbad) (struct mtd_info *mtd, loff_t ofs);
+	int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
+#ifndef __UBOOT__
+	int (*_suspend) (struct mtd_info *mtd);
+	void (*_resume) (struct mtd_info *mtd);
+	void (*_reboot) (struct mtd_info *mtd);
+#endif
+	/*
+	 * If the driver is something smart, like UBI, it may need to maintain
+	 * its own reference counting. The below functions are only for driver.
+	 */
+	int (*_get_device) (struct mtd_info *mtd);
+	void (*_put_device) (struct mtd_info *mtd);
+
+#ifndef __UBOOT__
+	/* Backing device capabilities for this device
+	 * - provides mmap capabilities
+	 */
+	struct backing_dev_info *backing_dev_info;
+
+	struct notifier_block reboot_notifier;  /* default mode before reboot */
+#endif
+
+	/* ECC status information */
+	struct mtd_ecc_stats ecc_stats;
+	/* Subpage shift (NAND) */
+	int subpage_sft;
+
+	void *priv;
+
+	struct module *owner;
+#ifndef __UBOOT__
+	struct device dev;
+#else
+	struct udevice *dev;
+#endif
+	int usecount;
+
+	/* MTD devices do not have any parent. MTD partitions do. */
+	struct mtd_info *parent;
+
+	/*
+	 * Offset of the partition relatively to the parent offset.
+	 * Is 0 for real MTD devices (ie. not partitions).
+	 */
+	u64 offset;
+
+	/*
+	 * List node used to add an MTD partition to the parent
+	 * partition list.
+	 */
+	struct list_head node;
+
+	/*
+	 * List of partitions attached to this MTD device (the parent
+	 * MTD device can itself be a partition).
+	 */
+	struct list_head partitions;
+};
+
+#if IS_ENABLED(CONFIG_DM)
+static inline void mtd_set_of_node(struct mtd_info *mtd,
+				   const struct device_node *np)
+{
+	mtd->dev->node.np = np;
+}
+
+static inline const struct device_node *mtd_get_of_node(struct mtd_info *mtd)
+{
+	return mtd->dev->node.np;
+}
+#else
+struct device_node;
+
+static inline void mtd_set_of_node(struct mtd_info *mtd,
+				   const struct device_node *np)
+{
+}
+
+static inline const struct device_node *mtd_get_of_node(struct mtd_info *mtd)
+{
+	return NULL;
+}
+#endif
+
+static inline bool mtd_is_partition(const struct mtd_info *mtd)
+{
+	return mtd->parent;
+}
+
+static inline bool mtd_has_partitions(const struct mtd_info *mtd)
+{
+	return !list_empty(&mtd->partitions);
+}
+
+bool mtd_partitions_used(struct mtd_info *master);
+
+int mtd_ooblayout_ecc(struct mtd_info *mtd, int section,
+		      struct mtd_oob_region *oobecc);
+int mtd_ooblayout_find_eccregion(struct mtd_info *mtd, int eccbyte,
+				 int *section,
+				 struct mtd_oob_region *oobregion);
+int mtd_ooblayout_get_eccbytes(struct mtd_info *mtd, u8 *eccbuf,
+			       const u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_set_eccbytes(struct mtd_info *mtd, const u8 *eccbuf,
+			       u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_free(struct mtd_info *mtd, int section,
+		       struct mtd_oob_region *oobfree);
+int mtd_ooblayout_get_databytes(struct mtd_info *mtd, u8 *databuf,
+				const u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_set_databytes(struct mtd_info *mtd, const u8 *databuf,
+				u8 *oobbuf, int start, int nbytes);
+int mtd_ooblayout_count_freebytes(struct mtd_info *mtd);
+int mtd_ooblayout_count_eccbytes(struct mtd_info *mtd);
+
+static inline void mtd_set_ooblayout(struct mtd_info *mtd,
+				     const struct mtd_ooblayout_ops *ooblayout)
+{
+	mtd->ooblayout = ooblayout;
+}
+
+static inline u32 mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops)
+{
+	return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
+}
+
+int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
+#ifndef __UBOOT__
+int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+	      void **virt, resource_size_t *phys);
+int mtd_unpoint(struct mtd_info *mtd, loff_t from, size_t len);
+#endif
+unsigned long mtd_get_unmapped_area(struct mtd_info *mtd, unsigned long len,
+				    unsigned long offset, unsigned long flags);
+int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+	     u_char *buf);
+int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+	      const u_char *buf);
+int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+		    const u_char *buf);
+
+int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
+int mtd_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops);
+
+int mtd_get_fact_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
+			   struct otp_info *buf);
+int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+			   size_t *retlen, u_char *buf);
+int mtd_get_user_prot_info(struct mtd_info *mtd, size_t len, size_t *retlen,
+			   struct otp_info *buf);
+int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+			   size_t *retlen, u_char *buf);
+int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len,
+			    size_t *retlen, u_char *buf);
+int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len);
+
+#ifndef __UBOOT__
+int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+	       unsigned long count, loff_t to, size_t *retlen);
+#endif
+
+static inline void mtd_sync(struct mtd_info *mtd)
+{
+	if (mtd->_sync)
+		mtd->_sync(mtd);
+}
+
+int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs);
+int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs);
+int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs);
+
+#ifndef __UBOOT__
+static inline int mtd_suspend(struct mtd_info *mtd)
+{
+	return mtd->_suspend ? mtd->_suspend(mtd) : 0;
+}
+
+static inline void mtd_resume(struct mtd_info *mtd)
+{
+	if (mtd->_resume)
+		mtd->_resume(mtd);
+}
+#endif
+
+static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd)
+{
+	if (mtd->erasesize_shift)
+		return sz >> mtd->erasesize_shift;
+	do_div(sz, mtd->erasesize);
+	return sz;
+}
+
+static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd)
+{
+	if (mtd->erasesize_shift)
+		return sz & mtd->erasesize_mask;
+	return do_div(sz, mtd->erasesize);
+}
+
+static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd)
+{
+	if (mtd->writesize_shift)
+		return sz >> mtd->writesize_shift;
+	do_div(sz, mtd->writesize);
+	return sz;
+}
+
+static inline uint32_t mtd_mod_by_ws(uint64_t sz, struct mtd_info *mtd)
+{
+	if (mtd->writesize_shift)
+		return sz & mtd->writesize_mask;
+	return do_div(sz, mtd->writesize);
+}
+
+static inline int mtd_has_oob(const struct mtd_info *mtd)
+{
+	return mtd->_read_oob && mtd->_write_oob;
+}
+
+static inline int mtd_type_is_nand(const struct mtd_info *mtd)
+{
+	return mtd->type == MTD_NANDFLASH || mtd->type == MTD_MLCNANDFLASH;
+}
+
+static inline int mtd_can_have_bb(const struct mtd_info *mtd)
+{
+	return !!mtd->_block_isbad;
+}
+
+	/* Kernel-side ioctl definitions */
+
+struct mtd_partition;
+struct mtd_part_parser_data;
+
+extern int mtd_device_parse_register(struct mtd_info *mtd,
+				     const char * const *part_probe_types,
+				     struct mtd_part_parser_data *parser_data,
+				     const struct mtd_partition *defparts,
+				     int defnr_parts);
+#define mtd_device_register(master, parts, nr_parts)	\
+	mtd_device_parse_register(master, NULL, NULL, parts, nr_parts)
+extern int mtd_device_unregister(struct mtd_info *master);
+extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num);
+extern int __get_mtd_device(struct mtd_info *mtd);
+extern void __put_mtd_device(struct mtd_info *mtd);
+extern struct mtd_info *get_mtd_device_nm(const char *name);
+extern void put_mtd_device(struct mtd_info *mtd);
+
+
+#ifndef __UBOOT__
+struct mtd_notifier {
+	void (*add)(struct mtd_info *mtd);
+	void (*remove)(struct mtd_info *mtd);
+	struct list_head list;
+};
+
+
+extern void register_mtd_user (struct mtd_notifier *new);
+extern int unregister_mtd_user (struct mtd_notifier *old);
+#endif
+void *mtd_kmalloc_up_to(const struct mtd_info *mtd, size_t *size);
+
+#ifdef CONFIG_MTD_PARTITIONS
+void mtd_erase_callback(struct erase_info *instr);
+#else
+static inline void mtd_erase_callback(struct erase_info *instr)
+{
+	if (instr->callback)
+		instr->callback(instr);
+}
+#endif
+
+static inline int mtd_is_bitflip(int err) {
+	return err == -EUCLEAN;
+}
+
+static inline int mtd_is_eccerr(int err) {
+	return err == -EBADMSG;
+}
+
+static inline int mtd_is_bitflip_or_eccerr(int err) {
+	return mtd_is_bitflip(err) || mtd_is_eccerr(err);
+}
+
+unsigned mtd_mmap_capabilities(struct mtd_info *mtd);
+
+#ifdef __UBOOT__
+/* drivers/mtd/mtdcore.h */
+int add_mtd_device(struct mtd_info *mtd);
+int del_mtd_device(struct mtd_info *mtd);
+
+#ifdef CONFIG_MTD_PARTITIONS
+int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int);
+int del_mtd_partitions(struct mtd_info *);
+#else
+static inline int add_mtd_partitions(struct mtd_info *mtd,
+				     const struct mtd_partition *parts,
+				     int nparts)
+{
+	return 0;
+}
+
+static inline int del_mtd_partitions(struct mtd_info *mtd)
+{
+	return 0;
+}
+#endif
+
+struct mtd_info *__mtd_next_device(int i);
+#define mtd_for_each_device(mtd)			\
+	for ((mtd) = __mtd_next_device(0);		\
+	     (mtd) != NULL;				\
+	     (mtd) = __mtd_next_device(mtd->index + 1))
+
+int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size,
+		loff_t *maxsize, int devtype, uint64_t chipsize);
+int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off,
+		     loff_t *size, loff_t *maxsize, int devtype,
+		     uint64_t chipsize);
+
+/* drivers/mtd/mtdcore.c */
+void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
+			  const uint64_t length, uint64_t *len_incl_bad,
+			  int *truncated);
+bool mtd_dev_list_updated(void);
+
+/* drivers/mtd/mtd_uboot.c */
+int mtd_search_alternate_name(const char *mtdname, char *altname,
+			      unsigned int max_len);
+
+#endif
+#endif /* __MTD_MTD_H__ */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
new file mode 100644
index 0000000..13e8dd1
--- /dev/null
+++ b/include/linux/mtd/nand.h
@@ -0,0 +1,734 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright 2017 - Free Electrons
+ *
+ *  Authors:
+ *	Boris Brezillon <boris.brezillon@free-electrons.com>
+ *	Peter Pan <peterpandong@micron.com>
+ */
+
+#ifndef __LINUX_MTD_NAND_H
+#define __LINUX_MTD_NAND_H
+
+#include <linux/mtd/mtd.h>
+
+/**
+ * struct nand_memory_organization - Memory organization structure
+ * @bits_per_cell: number of bits per NAND cell
+ * @pagesize: page size
+ * @oobsize: OOB area size
+ * @pages_per_eraseblock: number of pages per eraseblock
+ * @eraseblocks_per_lun: number of eraseblocks per LUN (Logical Unit Number)
+ * @planes_per_lun: number of planes per LUN
+ * @luns_per_target: number of LUN per target (target is a synonym for die)
+ * @ntargets: total number of targets exposed by the NAND device
+ */
+struct nand_memory_organization {
+	unsigned int bits_per_cell;
+	unsigned int pagesize;
+	unsigned int oobsize;
+	unsigned int pages_per_eraseblock;
+	unsigned int eraseblocks_per_lun;
+	unsigned int planes_per_lun;
+	unsigned int luns_per_target;
+	unsigned int ntargets;
+};
+
+#define NAND_MEMORG(bpc, ps, os, ppe, epl, ppl, lpt, nt)	\
+	{							\
+		.bits_per_cell = (bpc),				\
+		.pagesize = (ps),				\
+		.oobsize = (os),				\
+		.pages_per_eraseblock = (ppe),			\
+		.eraseblocks_per_lun = (epl),			\
+		.planes_per_lun = (ppl),			\
+		.luns_per_target = (lpt),			\
+		.ntargets = (nt),				\
+	}
+
+/**
+ * struct nand_row_converter - Information needed to convert an absolute offset
+ *			       into a row address
+ * @lun_addr_shift: position of the LUN identifier in the row address
+ * @eraseblock_addr_shift: position of the eraseblock identifier in the row
+ *			   address
+ */
+struct nand_row_converter {
+	unsigned int lun_addr_shift;
+	unsigned int eraseblock_addr_shift;
+};
+
+/**
+ * struct nand_pos - NAND position object
+ * @target: the NAND target/die
+ * @lun: the LUN identifier
+ * @plane: the plane within the LUN
+ * @eraseblock: the eraseblock within the LUN
+ * @page: the page within the LUN
+ *
+ * These information are usually used by specific sub-layers to select the
+ * appropriate target/die and generate a row address to pass to the device.
+ */
+struct nand_pos {
+	unsigned int target;
+	unsigned int lun;
+	unsigned int plane;
+	unsigned int eraseblock;
+	unsigned int page;
+};
+
+/**
+ * struct nand_page_io_req - NAND I/O request object
+ * @pos: the position this I/O request is targeting
+ * @dataoffs: the offset within the page
+ * @datalen: number of data bytes to read from/write to this page
+ * @databuf: buffer to store data in or get data from
+ * @ooboffs: the OOB offset within the page
+ * @ooblen: the number of OOB bytes to read from/write to this page
+ * @oobbuf: buffer to store OOB data in or get OOB data from
+ * @mode: one of the %MTD_OPS_XXX mode
+ *
+ * This object is used to pass per-page I/O requests to NAND sub-layers. This
+ * way all useful information are already formatted in a useful way and
+ * specific NAND layers can focus on translating these information into
+ * specific commands/operations.
+ */
+struct nand_page_io_req {
+	struct nand_pos pos;
+	unsigned int dataoffs;
+	unsigned int datalen;
+	union {
+		const void *out;
+		void *in;
+	} databuf;
+	unsigned int ooboffs;
+	unsigned int ooblen;
+	union {
+		const void *out;
+		void *in;
+	} oobbuf;
+	int mode;
+};
+
+/**
+ * struct nand_ecc_req - NAND ECC requirements
+ * @strength: ECC strength
+ * @step_size: ECC step/block size
+ */
+struct nand_ecc_req {
+	unsigned int strength;
+	unsigned int step_size;
+};
+
+#define NAND_ECCREQ(str, stp) { .strength = (str), .step_size = (stp) }
+
+/**
+ * struct nand_bbt - bad block table object
+ * @cache: in memory BBT cache
+ */
+struct nand_bbt {
+	unsigned long *cache;
+};
+
+struct nand_device;
+
+/**
+ * struct nand_ops - NAND operations
+ * @erase: erase a specific block. No need to check if the block is bad before
+ *	   erasing, this has been taken care of by the generic NAND layer
+ * @markbad: mark a specific block bad. No need to check if the block is
+ *	     already marked bad, this has been taken care of by the generic
+ *	     NAND layer. This method should just write the BBM (Bad Block
+ *	     Marker) so that future call to struct_nand_ops->isbad() return
+ *	     true
+ * @isbad: check whether a block is bad or not. This method should just read
+ *	   the BBM and return whether the block is bad or not based on what it
+ *	   reads
+ *
+ * These are all low level operations that should be implemented by specialized
+ * NAND layers (SPI NAND, raw NAND, ...).
+ */
+struct nand_ops {
+	int (*erase)(struct nand_device *nand, const struct nand_pos *pos);
+	int (*markbad)(struct nand_device *nand, const struct nand_pos *pos);
+	bool (*isbad)(struct nand_device *nand, const struct nand_pos *pos);
+};
+
+/**
+ * struct nand_device - NAND device
+ * @mtd: MTD instance attached to the NAND device
+ * @memorg: memory layout
+ * @eccreq: ECC requirements
+ * @rowconv: position to row address converter
+ * @bbt: bad block table info
+ * @ops: NAND operations attached to the NAND device
+ *
+ * Generic NAND object. Specialized NAND layers (raw NAND, SPI NAND, OneNAND)
+ * should declare their own NAND object embedding a nand_device struct (that's
+ * how inheritance is done).
+ * struct_nand_device->memorg and struct_nand_device->eccreq should be filled
+ * at device detection time to reflect the NAND device
+ * capabilities/requirements. Once this is done nanddev_init() can be called.
+ * It will take care of converting NAND information into MTD ones, which means
+ * the specialized NAND layers should never manually tweak
+ * struct_nand_device->mtd except for the ->_read/write() hooks.
+ */
+struct nand_device {
+	struct mtd_info *mtd;
+	struct nand_memory_organization memorg;
+	struct nand_ecc_req eccreq;
+	struct nand_row_converter rowconv;
+	struct nand_bbt bbt;
+	const struct nand_ops *ops;
+};
+
+/**
+ * struct nand_io_iter - NAND I/O iterator
+ * @req: current I/O request
+ * @oobbytes_per_page: maximum number of OOB bytes per page
+ * @dataleft: remaining number of data bytes to read/write
+ * @oobleft: remaining number of OOB bytes to read/write
+ *
+ * Can be used by specialized NAND layers to iterate over all pages covered
+ * by an MTD I/O request, which should greatly simplifies the boiler-plate
+ * code needed to read/write data from/to a NAND device.
+ */
+struct nand_io_iter {
+	struct nand_page_io_req req;
+	unsigned int oobbytes_per_page;
+	unsigned int dataleft;
+	unsigned int oobleft;
+};
+
+/**
+ * mtd_to_nanddev() - Get the NAND device attached to the MTD instance
+ * @mtd: MTD instance
+ *
+ * Return: the NAND device embedding @mtd.
+ */
+static inline struct nand_device *mtd_to_nanddev(struct mtd_info *mtd)
+{
+	return mtd->priv;
+}
+
+/**
+ * nanddev_to_mtd() - Get the MTD device attached to a NAND device
+ * @nand: NAND device
+ *
+ * Return: the MTD device embedded in @nand.
+ */
+static inline struct mtd_info *nanddev_to_mtd(struct nand_device *nand)
+{
+	return nand->mtd;
+}
+
+/*
+ * nanddev_bits_per_cell() - Get the number of bits per cell
+ * @nand: NAND device
+ *
+ * Return: the number of bits per cell.
+ */
+static inline unsigned int nanddev_bits_per_cell(const struct nand_device *nand)
+{
+	return nand->memorg.bits_per_cell;
+}
+
+/**
+ * nanddev_page_size() - Get NAND page size
+ * @nand: NAND device
+ *
+ * Return: the page size.
+ */
+static inline size_t nanddev_page_size(const struct nand_device *nand)
+{
+	return nand->memorg.pagesize;
+}
+
+/**
+ * nanddev_per_page_oobsize() - Get NAND OOB size
+ * @nand: NAND device
+ *
+ * Return: the OOB size.
+ */
+static inline unsigned int
+nanddev_per_page_oobsize(const struct nand_device *nand)
+{
+	return nand->memorg.oobsize;
+}
+
+/**
+ * nanddev_pages_per_eraseblock() - Get the number of pages per eraseblock
+ * @nand: NAND device
+ *
+ * Return: the number of pages per eraseblock.
+ */
+static inline unsigned int
+nanddev_pages_per_eraseblock(const struct nand_device *nand)
+{
+	return nand->memorg.pages_per_eraseblock;
+}
+
+/**
+ * nanddev_per_page_oobsize() - Get NAND erase block size
+ * @nand: NAND device
+ *
+ * Return: the eraseblock size.
+ */
+static inline size_t nanddev_eraseblock_size(const struct nand_device *nand)
+{
+	return nand->memorg.pagesize * nand->memorg.pages_per_eraseblock;
+}
+
+/**
+ * nanddev_eraseblocks_per_lun() - Get the number of eraseblocks per LUN
+ * @nand: NAND device
+ *
+ * Return: the number of eraseblocks per LUN.
+ */
+static inline unsigned int
+nanddev_eraseblocks_per_lun(const struct nand_device *nand)
+{
+	return nand->memorg.eraseblocks_per_lun;
+}
+
+/**
+ * nanddev_target_size() - Get the total size provided by a single target/die
+ * @nand: NAND device
+ *
+ * Return: the total size exposed by a single target/die in bytes.
+ */
+static inline u64 nanddev_target_size(const struct nand_device *nand)
+{
+	return (u64)nand->memorg.luns_per_target *
+	       nand->memorg.eraseblocks_per_lun *
+	       nand->memorg.pages_per_eraseblock *
+	       nand->memorg.pagesize;
+}
+
+/**
+ * nanddev_ntarget() - Get the total of targets
+ * @nand: NAND device
+ *
+ * Return: the number of targets/dies exposed by @nand.
+ */
+static inline unsigned int nanddev_ntargets(const struct nand_device *nand)
+{
+	return nand->memorg.ntargets;
+}
+
+/**
+ * nanddev_neraseblocks() - Get the total number of erasablocks
+ * @nand: NAND device
+ *
+ * Return: the total number of eraseblocks exposed by @nand.
+ */
+static inline unsigned int nanddev_neraseblocks(const struct nand_device *nand)
+{
+	return (u64)nand->memorg.luns_per_target *
+	       nand->memorg.eraseblocks_per_lun *
+	       nand->memorg.pages_per_eraseblock;
+}
+
+/**
+ * nanddev_size() - Get NAND size
+ * @nand: NAND device
+ *
+ * Return: the total size (in bytes) exposed by @nand.
+ */
+static inline u64 nanddev_size(const struct nand_device *nand)
+{
+	return nanddev_target_size(nand) * nanddev_ntargets(nand);
+}
+
+/**
+ * nanddev_get_memorg() - Extract memory organization info from a NAND device
+ * @nand: NAND device
+ *
+ * This can be used by the upper layer to fill the memorg info before calling
+ * nanddev_init().
+ *
+ * Return: the memorg object embedded in the NAND device.
+ */
+static inline struct nand_memory_organization *
+nanddev_get_memorg(struct nand_device *nand)
+{
+	return &nand->memorg;
+}
+
+int nanddev_init(struct nand_device *nand, const struct nand_ops *ops,
+		 struct module *owner);
+void nanddev_cleanup(struct nand_device *nand);
+
+/**
+ * nanddev_register() - Register a NAND device
+ * @nand: NAND device
+ *
+ * Register a NAND device.
+ * This function is just a wrapper around mtd_device_register()
+ * registering the MTD device embedded in @nand.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+static inline int nanddev_register(struct nand_device *nand)
+{
+	return mtd_device_register(nand->mtd, NULL, 0);
+}
+
+/**
+ * nanddev_unregister() - Unregister a NAND device
+ * @nand: NAND device
+ *
+ * Unregister a NAND device.
+ * This function is just a wrapper around mtd_device_unregister()
+ * unregistering the MTD device embedded in @nand.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+static inline int nanddev_unregister(struct nand_device *nand)
+{
+	return mtd_device_unregister(nand->mtd);
+}
+
+/**
+ * nanddev_set_of_node() - Attach a DT node to a NAND device
+ * @nand: NAND device
+ * @np: DT node
+ *
+ * Attach a DT node to a NAND device.
+ */
+static inline void nanddev_set_of_node(struct nand_device *nand,
+				       const struct device_node *np)
+{
+	mtd_set_of_node(nand->mtd, np);
+}
+
+/**
+ * nanddev_get_of_node() - Retrieve the DT node attached to a NAND device
+ * @nand: NAND device
+ *
+ * Return: the DT node attached to @nand.
+ */
+static inline const struct device_node *nanddev_get_of_node(struct nand_device *nand)
+{
+	return mtd_get_of_node(nand->mtd);
+}
+
+/**
+ * nanddev_offs_to_pos() - Convert an absolute NAND offset into a NAND position
+ * @nand: NAND device
+ * @offs: absolute NAND offset (usually passed by the MTD layer)
+ * @pos: a NAND position object to fill in
+ *
+ * Converts @offs into a nand_pos representation.
+ *
+ * Return: the offset within the NAND page pointed by @pos.
+ */
+static inline unsigned int nanddev_offs_to_pos(struct nand_device *nand,
+					       loff_t offs,
+					       struct nand_pos *pos)
+{
+	unsigned int pageoffs;
+	u64 tmp = offs;
+
+	pageoffs = do_div(tmp, nand->memorg.pagesize);
+	pos->page = do_div(tmp, nand->memorg.pages_per_eraseblock);
+	pos->eraseblock = do_div(tmp, nand->memorg.eraseblocks_per_lun);
+	pos->plane = pos->eraseblock % nand->memorg.planes_per_lun;
+	pos->lun = do_div(tmp, nand->memorg.luns_per_target);
+	pos->target = tmp;
+
+	return pageoffs;
+}
+
+/**
+ * nanddev_pos_cmp() - Compare two NAND positions
+ * @a: First NAND position
+ * @b: Second NAND position
+ *
+ * Compares two NAND positions.
+ *
+ * Return: -1 if @a < @b, 0 if @a == @b and 1 if @a > @b.
+ */
+static inline int nanddev_pos_cmp(const struct nand_pos *a,
+				  const struct nand_pos *b)
+{
+	if (a->target != b->target)
+		return a->target < b->target ? -1 : 1;
+
+	if (a->lun != b->lun)
+		return a->lun < b->lun ? -1 : 1;
+
+	if (a->eraseblock != b->eraseblock)
+		return a->eraseblock < b->eraseblock ? -1 : 1;
+
+	if (a->page != b->page)
+		return a->page < b->page ? -1 : 1;
+
+	return 0;
+}
+
+/**
+ * nanddev_pos_to_offs() - Convert a NAND position into an absolute offset
+ * @nand: NAND device
+ * @pos: the NAND position to convert
+ *
+ * Converts @pos NAND position into an absolute offset.
+ *
+ * Return: the absolute offset. Note that @pos points to the beginning of a
+ *	   page, if one wants to point to a specific offset within this page
+ *	   the returned offset has to be adjusted manually.
+ */
+static inline loff_t nanddev_pos_to_offs(struct nand_device *nand,
+					 const struct nand_pos *pos)
+{
+	unsigned int npages;
+
+	npages = pos->page +
+		 ((pos->eraseblock +
+		   (pos->lun +
+		    (pos->target * nand->memorg.luns_per_target)) *
+		   nand->memorg.eraseblocks_per_lun) *
+		  nand->memorg.pages_per_eraseblock);
+
+	return (loff_t)npages * nand->memorg.pagesize;
+}
+
+/**
+ * nanddev_pos_to_row() - Extract a row address from a NAND position
+ * @nand: NAND device
+ * @pos: the position to convert
+ *
+ * Converts a NAND position into a row address that can then be passed to the
+ * device.
+ *
+ * Return: the row address extracted from @pos.
+ */
+static inline unsigned int nanddev_pos_to_row(struct nand_device *nand,
+					      const struct nand_pos *pos)
+{
+	return (pos->lun << nand->rowconv.lun_addr_shift) |
+	       (pos->eraseblock << nand->rowconv.eraseblock_addr_shift) |
+	       pos->page;
+}
+
+/**
+ * nanddev_pos_next_target() - Move a position to the next target/die
+ * @nand: NAND device
+ * @pos: the position to update
+ *
+ * Updates @pos to point to the start of the next target/die. Useful when you
+ * want to iterate over all targets/dies of a NAND device.
+ */
+static inline void nanddev_pos_next_target(struct nand_device *nand,
+					   struct nand_pos *pos)
+{
+	pos->page = 0;
+	pos->plane = 0;
+	pos->eraseblock = 0;
+	pos->lun = 0;
+	pos->target++;
+}
+
+/**
+ * nanddev_pos_next_lun() - Move a position to the next LUN
+ * @nand: NAND device
+ * @pos: the position to update
+ *
+ * Updates @pos to point to the start of the next LUN. Useful when you want to
+ * iterate over all LUNs of a NAND device.
+ */
+static inline void nanddev_pos_next_lun(struct nand_device *nand,
+					struct nand_pos *pos)
+{
+	if (pos->lun >= nand->memorg.luns_per_target - 1)
+		return nanddev_pos_next_target(nand, pos);
+
+	pos->lun++;
+	pos->page = 0;
+	pos->plane = 0;
+	pos->eraseblock = 0;
+}
+
+/**
+ * nanddev_pos_next_eraseblock() - Move a position to the next eraseblock
+ * @nand: NAND device
+ * @pos: the position to update
+ *
+ * Updates @pos to point to the start of the next eraseblock. Useful when you
+ * want to iterate over all eraseblocks of a NAND device.
+ */
+static inline void nanddev_pos_next_eraseblock(struct nand_device *nand,
+					       struct nand_pos *pos)
+{
+	if (pos->eraseblock >= nand->memorg.eraseblocks_per_lun - 1)
+		return nanddev_pos_next_lun(nand, pos);
+
+	pos->eraseblock++;
+	pos->page = 0;
+	pos->plane = pos->eraseblock % nand->memorg.planes_per_lun;
+}
+
+/**
+ * nanddev_pos_next_eraseblock() - Move a position to the next page
+ * @nand: NAND device
+ * @pos: the position to update
+ *
+ * Updates @pos to point to the start of the next page. Useful when you want to
+ * iterate over all pages of a NAND device.
+ */
+static inline void nanddev_pos_next_page(struct nand_device *nand,
+					 struct nand_pos *pos)
+{
+	if (pos->page >= nand->memorg.pages_per_eraseblock - 1)
+		return nanddev_pos_next_eraseblock(nand, pos);
+
+	pos->page++;
+}
+
+/**
+ * nand_io_iter_init - Initialize a NAND I/O iterator
+ * @nand: NAND device
+ * @offs: absolute offset
+ * @req: MTD request
+ * @iter: NAND I/O iterator
+ *
+ * Initializes a NAND iterator based on the information passed by the MTD
+ * layer.
+ */
+static inline void nanddev_io_iter_init(struct nand_device *nand,
+					loff_t offs, struct mtd_oob_ops *req,
+					struct nand_io_iter *iter)
+{
+	struct mtd_info *mtd = nanddev_to_mtd(nand);
+
+	iter->req.mode = req->mode;
+	iter->req.dataoffs = nanddev_offs_to_pos(nand, offs, &iter->req.pos);
+	iter->req.ooboffs = req->ooboffs;
+	iter->oobbytes_per_page = mtd_oobavail(mtd, req);
+	iter->dataleft = req->len;
+	iter->oobleft = req->ooblen;
+	iter->req.databuf.in = req->datbuf;
+	iter->req.datalen = min_t(unsigned int,
+				  nand->memorg.pagesize - iter->req.dataoffs,
+				  iter->dataleft);
+	iter->req.oobbuf.in = req->oobbuf;
+	iter->req.ooblen = min_t(unsigned int,
+				 iter->oobbytes_per_page - iter->req.ooboffs,
+				 iter->oobleft);
+}
+
+/**
+ * nand_io_iter_next_page - Move to the next page
+ * @nand: NAND device
+ * @iter: NAND I/O iterator
+ *
+ * Updates the @iter to point to the next page.
+ */
+static inline void nanddev_io_iter_next_page(struct nand_device *nand,
+					     struct nand_io_iter *iter)
+{
+	nanddev_pos_next_page(nand, &iter->req.pos);
+	iter->dataleft -= iter->req.datalen;
+	iter->req.databuf.in += iter->req.datalen;
+	iter->oobleft -= iter->req.ooblen;
+	iter->req.oobbuf.in += iter->req.ooblen;
+	iter->req.dataoffs = 0;
+	iter->req.ooboffs = 0;
+	iter->req.datalen = min_t(unsigned int, nand->memorg.pagesize,
+				  iter->dataleft);
+	iter->req.ooblen = min_t(unsigned int, iter->oobbytes_per_page,
+				 iter->oobleft);
+}
+
+/**
+ * nand_io_iter_end - Should end iteration or not
+ * @nand: NAND device
+ * @iter: NAND I/O iterator
+ *
+ * Check whether @iter has reached the end of the NAND portion it was asked to
+ * iterate on or not.
+ *
+ * Return: true if @iter has reached the end of the iteration request, false
+ *	   otherwise.
+ */
+static inline bool nanddev_io_iter_end(struct nand_device *nand,
+				       const struct nand_io_iter *iter)
+{
+	if (iter->dataleft || iter->oobleft)
+		return false;
+
+	return true;
+}
+
+/**
+ * nand_io_for_each_page - Iterate over all NAND pages contained in an MTD I/O
+ *			   request
+ * @nand: NAND device
+ * @start: start address to read/write from
+ * @req: MTD I/O request
+ * @iter: NAND I/O iterator
+ *
+ * Should be used for iterate over pages that are contained in an MTD request.
+ */
+#define nanddev_io_for_each_page(nand, start, req, iter)		\
+	for (nanddev_io_iter_init(nand, start, req, iter);		\
+	     !nanddev_io_iter_end(nand, iter);				\
+	     nanddev_io_iter_next_page(nand, iter))
+
+bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos);
+bool nanddev_isreserved(struct nand_device *nand, const struct nand_pos *pos);
+int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos);
+int nanddev_markbad(struct nand_device *nand, const struct nand_pos *pos);
+
+/* BBT related functions */
+enum nand_bbt_block_status {
+	NAND_BBT_BLOCK_STATUS_UNKNOWN,
+	NAND_BBT_BLOCK_GOOD,
+	NAND_BBT_BLOCK_WORN,
+	NAND_BBT_BLOCK_RESERVED,
+	NAND_BBT_BLOCK_FACTORY_BAD,
+	NAND_BBT_BLOCK_NUM_STATUS,
+};
+
+int nanddev_bbt_init(struct nand_device *nand);
+void nanddev_bbt_cleanup(struct nand_device *nand);
+int nanddev_bbt_update(struct nand_device *nand);
+int nanddev_bbt_get_block_status(const struct nand_device *nand,
+				 unsigned int entry);
+int nanddev_bbt_set_block_status(struct nand_device *nand, unsigned int entry,
+				 enum nand_bbt_block_status status);
+int nanddev_bbt_markbad(struct nand_device *nand, unsigned int block);
+
+/**
+ * nanddev_bbt_pos_to_entry() - Convert a NAND position into a BBT entry
+ * @nand: NAND device
+ * @pos: the NAND position we want to get BBT entry for
+ *
+ * Return the BBT entry used to store information about the eraseblock pointed
+ * by @pos.
+ *
+ * Return: the BBT entry storing information about eraseblock pointed by @pos.
+ */
+static inline unsigned int nanddev_bbt_pos_to_entry(struct nand_device *nand,
+						    const struct nand_pos *pos)
+{
+	return pos->eraseblock +
+	       ((pos->lun + (pos->target * nand->memorg.luns_per_target)) *
+		nand->memorg.eraseblocks_per_lun);
+}
+
+/**
+ * nanddev_bbt_is_initialized() - Check if the BBT has been initialized
+ * @nand: NAND device
+ *
+ * Return: true if the BBT has been initialized, false otherwise.
+ */
+static inline bool nanddev_bbt_is_initialized(struct nand_device *nand)
+{
+	return !!nand->bbt.cache;
+}
+
+/* MTD -> NAND helper functions. */
+int nanddev_mtd_erase(struct mtd_info *mtd, struct erase_info *einfo);
+
+#endif /* __LINUX_MTD_NAND_H */
diff --git a/include/linux/mtd/nand_bch.h b/include/linux/mtd/nand_bch.h
new file mode 100644
index 0000000..8ea6b04
--- /dev/null
+++ b/include/linux/mtd/nand_bch.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright © 2011 Ivan Djelic <ivan.djelic@parrot.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file is the header for the NAND BCH ECC implementation.
+ */
+
+#ifndef __MTD_NAND_BCH_H__
+#define __MTD_NAND_BCH_H__
+
+struct mtd_info;
+struct nand_bch_control;
+
+#if defined(CONFIG_NAND_ECC_BCH)
+
+static inline int mtd_nand_has_bch(void) { return 1; }
+
+/*
+ * Calculate BCH ecc code
+ */
+int nand_bch_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+			   u_char *ecc_code);
+
+/*
+ * Detect and correct bit errors
+ */
+int nand_bch_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc,
+			  u_char *calc_ecc);
+/*
+ * Initialize BCH encoder/decoder
+ */
+struct nand_bch_control *nand_bch_init(struct mtd_info *mtd);
+/*
+ * Release BCH encoder/decoder resources
+ */
+void nand_bch_free(struct nand_bch_control *nbc);
+
+#else /* !CONFIG_NAND_ECC_BCH */
+
+static inline int mtd_nand_has_bch(void) { return 0; }
+
+static inline int
+nand_bch_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+		       u_char *ecc_code)
+{
+	return -1;
+}
+
+static inline int
+nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
+		      unsigned char *read_ecc, unsigned char *calc_ecc)
+{
+	return -ENOTSUPP;
+}
+
+static inline struct nand_bch_control *nand_bch_init(struct mtd_info *mtd)
+{
+	return NULL;
+}
+
+static inline void nand_bch_free(struct nand_bch_control *nbc) {}
+
+#endif /* CONFIG_NAND_ECC_BCH */
+
+#endif /* __MTD_NAND_BCH_H__ */
diff --git a/include/linux/mtd/nand_ecc.h b/include/linux/mtd/nand_ecc.h
new file mode 100644
index 0000000..3978363
--- /dev/null
+++ b/include/linux/mtd/nand_ecc.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  drivers/mtd/nand_ecc.h
+ *
+ *  Copyright (C) 2000-2010 Steven J. Hill <sjhill@realitydiluted.com>
+ *			    David Woodhouse <dwmw2@infradead.org>
+ *			    Thomas Gleixner <tglx@linutronix.de>
+ *
+ * This file is the header for the ECC algorithm.
+ */
+
+#ifndef __MTD_NAND_ECC_H__
+#define __MTD_NAND_ECC_H__
+
+struct mtd_info;
+
+/*
+ * Calculate 3 byte ECC code for 256 byte block
+ */
+int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
+
+/*
+ * Detect and correct a 1 bit error for 256 byte block
+ */
+int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
+
+#endif /* __MTD_NAND_ECC_H__ */
diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h
new file mode 100644
index 0000000..d0558a9
--- /dev/null
+++ b/include/linux/mtd/ndfc.h
@@ -0,0 +1,67 @@
+/*
+ *  linux/include/linux/mtd/ndfc.h
+ *
+ *  Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Info:
+ *   Contains defines, datastructures for ndfc nand controller
+ *
+ */
+#ifndef __LINUX_MTD_NDFC_H
+#define __LINUX_MTD_NDFC_H
+
+/* NDFC Register definitions */
+#define NDFC_CMD		0x00
+#define NDFC_ALE		0x04
+#define NDFC_DATA		0x08
+#define NDFC_ECC		0x10
+#define NDFC_BCFG0		0x30
+#define NDFC_BCFG1		0x34
+#define NDFC_BCFG2		0x38
+#define NDFC_BCFG3		0x3c
+#define NDFC_CCR		0x40
+#define NDFC_STAT		0x44
+#define NDFC_HWCTL		0x48
+#define NDFC_REVID		0x50
+
+#define NDFC_STAT_IS_READY	0x01000000
+
+#define NDFC_CCR_RESET_CE	0x80000000 /* CE Reset */
+#define NDFC_CCR_RESET_ECC	0x40000000 /* ECC Reset */
+#define NDFC_CCR_RIE		0x20000000 /* Interrupt Enable on Device Rdy */
+#define NDFC_CCR_REN		0x10000000 /* Enable wait for Rdy in LinearR */
+#define NDFC_CCR_ROMEN		0x08000000 /* Enable ROM In LinearR */
+#define NDFC_CCR_ARE		0x04000000 /* Auto-Read Enable */
+#define NDFC_CCR_BS(x)		(((x) & 0x3) << 24) /* Select Bank on CE[x] */
+#define NDFC_CCR_BS_MASK	0x03000000 /* Select Bank */
+#define NDFC_CCR_ARAC0		0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
+#define NDFC_CCR_ARAC1		0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
+#define NDFC_CCR_ARAC2		0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
+#define NDFC_CCR_ARAC3		0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
+#define NDFC_CCR_ARAC_MASK	0x00003000 /* Auto-Read mode Addr Cycles */
+#define NDFC_CCR_RPG		0x0000C000 /* Auto-Read Page */
+#define NDFC_CCR_EBCC		0x00000004 /* EBC Configuration Completed */
+#define NDFC_CCR_DHC		0x00000002 /* Direct Hardware Control Enable */
+
+#define NDFC_BxCFG_EN		0x80000000 /* Bank Enable */
+#define NDFC_BxCFG_CED		0x40000000 /* nCE Style */
+#define NDFC_BxCFG_SZ_MASK	0x08000000 /* Bank Size */
+#define NDFC_BxCFG_SZ_8BIT	0x00000000 /* 8bit */
+#define NDFC_BxCFG_SZ_16BIT	0x08000000 /* 16bit */
+
+#define NDFC_MAX_BANKS		4
+
+struct ndfc_controller_settings {
+	uint32_t	ccr_settings;
+	uint64_t	ndfc_erpn;
+};
+
+struct ndfc_chip_settings {
+	uint32_t	bank_settings;
+};
+
+#endif
diff --git a/include/linux/mtd/omap_elm.h b/include/linux/mtd/omap_elm.h
new file mode 100644
index 0000000..f3db00d
--- /dev/null
+++ b/include/linux/mtd/omap_elm.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3
+ */
+#ifndef __ASM_ARCH_ELM_H
+#define __ASM_ARCH_ELM_H
+/*
+ * ELM Module Registers
+ */
+
+/* ELM registers bit fields */
+#define ELM_SYSCONFIG_SOFTRESET_MASK			(0x2)
+#define ELM_SYSCONFIG_SOFTRESET			(0x2)
+#define ELM_SYSSTATUS_RESETDONE_MASK			(0x1)
+#define ELM_SYSSTATUS_RESETDONE			(0x1)
+#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK		(0x3)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK		(0x7FF0000)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_POS		(16)
+#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID		(0x00010000)
+#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK	(0x100)
+#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK		(0x1F)
+
+#define ELM_MAX_CHANNELS				8
+#define ELM_MAX_ERROR_COUNT				16
+
+#ifndef __ASSEMBLY__
+
+enum bch_level {
+	BCH_4_BIT = 0,
+	BCH_8_BIT,
+	BCH_16_BIT
+};
+
+
+/* BCH syndrome registers */
+struct syndrome {
+	u32 syndrome_fragment_x[7];	/* 0x400, 0x404.... 0x418 */
+	u8 res1[36];			/* 0x41c */
+};
+
+/* BCH error status & location register */
+struct location {
+	u32 location_status;		/* 0x800 */
+	u8 res1[124];			/* 0x804 */
+	u32 error_location_x[ELM_MAX_ERROR_COUNT]; /* 0x880, 0x980, .. */
+	u8 res2[64];			/* 0x8c0 */
+};
+
+/* BCH ELM register map - do not try to allocate memmory for this structure.
+ * We have used plenty of reserved variables to fill the slots in the ELM
+ * register memory map.
+ * Directly initialize the struct pointer to ELM base address.
+ */
+struct elm {
+	u32 rev;				/* 0x000 */
+	u8 res1[12];				/* 0x004 */
+	u32 sysconfig;				/* 0x010 */
+	u32 sysstatus;				/* 0x014 */
+	u32 irqstatus;				/* 0x018 */
+	u32 irqenable;				/* 0x01c */
+	u32 location_config;			/* 0x020 */
+	u8 res2[92];				/* 0x024 */
+	u32 page_ctrl;				/* 0x080 */
+	u8 res3[892];				/* 0x084 */
+	struct  syndrome syndrome_fragments[ELM_MAX_CHANNELS]; /* 0x400,0x420 */
+	u8 res4[512];				/* 0x600 */
+	struct location  error_location[ELM_MAX_CHANNELS]; /* 0x800,0x900 ... */
+};
+
+int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count,
+		u32 *error_locations);
+int elm_config(enum bch_level level);
+void elm_reset(void);
+void elm_init(void);
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_ELM_H */
diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h
new file mode 100644
index 0000000..864b05e
--- /dev/null
+++ b/include/linux/mtd/omap_gpmc.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * (C) Copyright 2013 Andreas Bießmann <andreas@biessmann.org>
+ */
+#ifndef __ASM_OMAP_GPMC_H
+#define __ASM_OMAP_GPMC_H
+
+#define GPMC_BUF_EMPTY	0
+#define GPMC_BUF_FULL	1
+#define GPMC_MAX_SECTORS	8
+
+enum omap_ecc {
+	/* 1-bit  ECC calculation by Software, Error detection by Software */
+	OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
+	/* 1-bit  ECC calculation by GPMC, Error detection by Software */
+	/* ECC layout compatible to legacy ROMCODE. */
+	OMAP_ECC_HAM1_CODE_HW,
+	/* 4-bit  ECC calculation by GPMC, Error detection by Software */
+	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
+	/* 4-bit  ECC calculation by GPMC, Error detection by ELM */
+	OMAP_ECC_BCH4_CODE_HW,
+	/* 8-bit  ECC calculation by GPMC, Error detection by Software */
+	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
+	/* 8-bit  ECC calculation by GPMC, Error detection by ELM */
+	OMAP_ECC_BCH8_CODE_HW,
+	/* 16-bit  ECC calculation by GPMC, Error detection by ELM */
+	OMAP_ECC_BCH16_CODE_HW,
+};
+
+struct gpmc_cs {
+	u32 config1;		/* 0x00 */
+	u32 config2;		/* 0x04 */
+	u32 config3;		/* 0x08 */
+	u32 config4;		/* 0x0C */
+	u32 config5;		/* 0x10 */
+	u32 config6;		/* 0x14 */
+	u32 config7;		/* 0x18 */
+	u32 nand_cmd;		/* 0x1C */
+	u32 nand_adr;		/* 0x20 */
+	u32 nand_dat;		/* 0x24 */
+	u8 res[8];		/* blow up to 0x30 byte */
+};
+
+struct bch_res_0_3 {
+	u32 bch_result_x[4];
+};
+
+struct bch_res_4_6 {
+	u32 bch_result_x[3];
+};
+
+struct gpmc {
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u8 res2[0x4];
+	u32 irqstatus;		/* 0x18 */
+	u32 irqenable;		/* 0x1C */
+	u8 res3[0x20];
+	u32 timeout_control;	/* 0x40 */
+	u8 res4[0xC];
+	u32 config;		/* 0x50 */
+	u32 status;		/* 0x54 */
+	u8 res5[0x8];		/* 0x58 */
+	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
+	u32 prefetch_config1;	/* 0x1E0 */
+	u32 prefetch_config2;	/* 0x1E4 */
+	u32 res6;		/* 0x1E8 */
+	u32 prefetch_control;	/* 0x1EC */
+	u32 prefetch_status;	/* 0x1F0 */
+	u32 ecc_config;		/* 0x1F4 */
+	u32 ecc_control;	/* 0x1F8 */
+	u32 ecc_size_config;	/* 0x1FC */
+	u32 ecc1_result;	/* 0x200 */
+	u32 ecc2_result;	/* 0x204 */
+	u32 ecc3_result;	/* 0x208 */
+	u32 ecc4_result;	/* 0x20C */
+	u32 ecc5_result;	/* 0x210 */
+	u32 ecc6_result;	/* 0x214 */
+	u32 ecc7_result;	/* 0x218 */
+	u32 ecc8_result;	/* 0x21C */
+	u32 ecc9_result;	/* 0x220 */
+	u8 res7[12];		/* 0x224 */
+	u32 testmomde_ctrl;	/* 0x230 */
+	u8 res8[12];		/* 0x234 */
+	struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */
+	u8 res9[16 * 4];	/* 0x2C0 - 0x2FF */
+	struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */
+};
+
+/* Used for board specific gpmc initialization */
+extern const struct gpmc *gpmc_cfg;
+extern char gpmc_cs0_flash;
+
+#endif /* __ASM_OMAP_GPMC_H */
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
new file mode 100644
index 0000000..e7b63dd
--- /dev/null
+++ b/include/linux/mtd/onenand.h
@@ -0,0 +1,180 @@
+/*
+ *  linux/include/linux/mtd/onenand.h
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_ONENAND_H
+#define __LINUX_MTD_ONENAND_H
+
+#include <linux/mtd/onenand_regs.h>
+
+/* Note: The header order is impoertant */
+#include <onenand_uboot.h>
+
+#include <linux/compat.h>
+#include <linux/mtd/bbm.h>
+
+#define MAX_DIES		2
+#define MAX_BUFFERRAM		2
+#define MAX_ONENAND_PAGESIZE	(4096 + 128)
+
+/* Scan and identify a OneNAND device */
+extern int onenand_scan (struct mtd_info *mtd, int max_chips);
+/* Free resources held by the OneNAND device */
+extern void onenand_release (struct mtd_info *mtd);
+
+/**
+ * struct onenand_bufferram - OneNAND BufferRAM Data
+ * @param blockpage	block & page address in BufferRAM
+ */
+struct onenand_bufferram {
+	int blockpage;
+};
+
+/**
+ * struct onenand_chip - OneNAND Private Flash Chip Data
+ * @param base		[BOARDSPECIFIC] address to access OneNAND
+ * @dies:               [INTERN][FLEXONENAND] number of dies on chip
+ * @boundary:           [INTERN][FLEXONENAND] Boundary of the dies
+ * @diesize:            [INTERN][FLEXONENAND] Size of the dies
+ * @param chipsize	[INTERN] the size of one chip for multichip arrays
+ * @param device_id	[INTERN] device ID
+ * @param verstion_id	[INTERN] version ID
+ * @technology		[INTERN] describes the internal NAND array technology such as SLC or MLC.
+ * @density_mask:	[INTERN] chip density, used for DDP devices
+ * @param options	[BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
+ * @param erase_shift	[INTERN] number of address bits in a block
+ * @param page_shift	[INTERN] number of address bits in a page
+ * @param ppb_shift	[INTERN] number of address bits in a pages per block
+ * @param page_mask	[INTERN] a page per block mask
+ * @param writesize	[INTERN] a real page size
+ * @param bufferam_index	[INTERN] BufferRAM index
+ * @param bufferam	[INTERN] BufferRAM info
+ * @param readw		[REPLACEABLE] hardware specific function for read short
+ * @param writew	[REPLACEABLE] hardware specific function for write short
+ * @param command	[REPLACEABLE] hardware specific function for writing commands to the chip
+ * @param wait		[REPLACEABLE] hardware specific function for wait on ready
+ * @param read_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param write_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param chip_lock	[INTERN] spinlock used to protect access to this structure and the chip
+ * @param wq		[INTERN] wait queue to sleep on if a OneNAND operation is in progress
+ * @param state		[INTERN] the current state of the OneNAND device
+ * @param autooob	[REPLACEABLE] the default (auto)placement scheme
+ * @param priv		[OPTIONAL] pointer to private chip date
+ */
+struct onenand_chip {
+	void __iomem *base;
+	unsigned int dies;
+	unsigned int boundary[MAX_DIES];
+	unsigned int diesize[MAX_DIES];
+	unsigned int chipsize;
+	unsigned int device_id;
+	unsigned int version_id;
+	unsigned int technology;
+	unsigned int density_mask;
+	unsigned int options;
+
+	unsigned int erase_shift;
+	unsigned int page_shift;
+	unsigned int ppb_shift;	/* Pages per block shift */
+	unsigned int page_mask;
+	unsigned int writesize;
+
+	unsigned int bufferram_index;
+	struct onenand_bufferram bufferram[MAX_BUFFERRAM];
+
+	int (*command) (struct mtd_info *mtd, int cmd, loff_t address,
+			size_t len);
+	int (*wait) (struct mtd_info *mtd, int state);
+	int (*bbt_wait) (struct mtd_info *mtd, int state);
+	void (*unlock_all)(struct mtd_info *mtd);
+	int (*read_bufferram) (struct mtd_info *mtd, loff_t addr, int area,
+			       unsigned char *buffer, int offset, size_t count);
+	int (*write_bufferram) (struct mtd_info *mtd, loff_t addr, int area,
+				const unsigned char *buffer, int offset,
+				size_t count);
+	unsigned short (*read_word) (void __iomem *addr);
+	void (*write_word) (unsigned short value, void __iomem *addr);
+	int (*chip_probe)(struct mtd_info *mtd);
+	void (*mmcontrol) (struct mtd_info *mtd, int sync_read);
+	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
+	int (*scan_bbt)(struct mtd_info *mtd);
+
+	unsigned char		*main_buf;
+	unsigned char		*spare_buf;
+#ifdef DONT_USE_UBOOT
+	spinlock_t chip_lock;
+	wait_queue_head_t wq;
+#endif
+	int state;
+	unsigned char		*page_buf;
+	unsigned char		*oob_buf;
+
+	struct nand_oobinfo *autooob;
+	int			subpagesize;
+	struct nand_ecclayout	*ecclayout;
+
+	void *bbm;
+
+	void *priv;
+};
+
+/*
+ * Helper macros
+ */
+#define ONENAND_CURRENT_BUFFERRAM(this)		(this->bufferram_index)
+#define ONENAND_NEXT_BUFFERRAM(this)		(this->bufferram_index ^ 1)
+#define ONENAND_SET_NEXT_BUFFERRAM(this)	(this->bufferram_index ^= 1)
+#define ONENAND_SET_PREV_BUFFERRAM(this)	(this->bufferram_index ^= 1)
+#define ONENAND_SET_BUFFERRAM0(this)		(this->bufferram_index = 0)
+#define ONENAND_SET_BUFFERRAM1(this)		(this->bufferram_index = 1)
+
+#define FLEXONENAND(this)	(this->device_id & DEVICE_IS_FLEXONENAND)
+#define ONENAND_IS_MLC(this)	(this->technology & ONENAND_TECHNOLOGY_IS_MLC)
+#define ONENAND_IS_DDP(this)						\
+	(this->device_id & ONENAND_DEVICE_IS_DDP)
+
+#define ONENAND_IS_4KB_PAGE(this)					\
+	(this->options & ONENAND_HAS_4KB_PAGE)
+
+#define ONENAND_IS_2PLANE(this)			(0)
+
+/*
+ * Options bits
+ */
+#define ONENAND_HAS_CONT_LOCK		(0x0001)
+#define ONENAND_HAS_UNLOCK_ALL		(0x0002)
+#define ONENAND_HAS_2PLANE		(0x0004)
+#define ONENAND_HAS_4KB_PAGE            (0x0008)
+#define ONENAND_RUNTIME_BADBLOCK_CHECK	(0x0200)
+#define ONENAND_PAGEBUF_ALLOC		(0x1000)
+#define ONENAND_OOBBUF_ALLOC		(0x2000)
+
+/*
+ * OneNAND Flash Manufacturer ID Codes
+ */
+#define ONENAND_MFR_NUMONYX	0x20
+#define ONENAND_MFR_SAMSUNG	0xec
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @param name:		Manufacturer name
+ * @param id:		manufacturer ID code of device.
+*/
+struct onenand_manufacturers {
+	int id;
+	char *name;
+};
+
+int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
+			struct mtd_oob_ops *ops);
+
+unsigned int onenand_block(struct onenand_chip *this, loff_t addr);
+int flexonenand_region(struct mtd_info *mtd, loff_t addr);
+#endif				/* __LINUX_MTD_ONENAND_H */
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
new file mode 100644
index 0000000..8449a3c
--- /dev/null
+++ b/include/linux/mtd/onenand_regs.h
@@ -0,0 +1,208 @@
+/*
+ *  linux/include/linux/mtd/onenand_regs.h
+ *
+ *  OneNAND Register header file
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ONENAND_REG_H
+#define __ONENAND_REG_H
+
+/* Memory Address Map Translation (Word order) */
+#define ONENAND_MEMORY_MAP(x)		((x) << 1)
+
+/*
+ * External BufferRAM area
+ */
+#define	ONENAND_BOOTRAM			ONENAND_MEMORY_MAP(0x0000)
+#define	ONENAND_DATARAM			ONENAND_MEMORY_MAP(0x0200)
+#define	ONENAND_SPARERAM		ONENAND_MEMORY_MAP(0x8010)
+
+/*
+ * OneNAND Registers
+ */
+#define ONENAND_REG_MANUFACTURER_ID	ONENAND_MEMORY_MAP(0xF000)
+#define ONENAND_REG_DEVICE_ID		ONENAND_MEMORY_MAP(0xF001)
+#define ONENAND_REG_VERSION_ID		ONENAND_MEMORY_MAP(0xF002)
+#define ONENAND_REG_DATA_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF003)
+#define ONENAND_REG_BOOT_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF004)
+#define ONENAND_REG_NUM_BUFFERS		ONENAND_MEMORY_MAP(0xF005)
+#define ONENAND_REG_TECHNOLOGY		ONENAND_MEMORY_MAP(0xF006)
+
+#define ONENAND_REG_START_ADDRESS1	ONENAND_MEMORY_MAP(0xF100)
+#define ONENAND_REG_START_ADDRESS2	ONENAND_MEMORY_MAP(0xF101)
+#define ONENAND_REG_START_ADDRESS3	ONENAND_MEMORY_MAP(0xF102)
+#define ONENAND_REG_START_ADDRESS4	ONENAND_MEMORY_MAP(0xF103)
+#define ONENAND_REG_START_ADDRESS5	ONENAND_MEMORY_MAP(0xF104)
+#define ONENAND_REG_START_ADDRESS6	ONENAND_MEMORY_MAP(0xF105)
+#define ONENAND_REG_START_ADDRESS7	ONENAND_MEMORY_MAP(0xF106)
+#define ONENAND_REG_START_ADDRESS8	ONENAND_MEMORY_MAP(0xF107)
+
+#define ONENAND_REG_START_BUFFER	ONENAND_MEMORY_MAP(0xF200)
+#define ONENAND_REG_COMMAND		ONENAND_MEMORY_MAP(0xF220)
+#define ONENAND_REG_SYS_CFG1		ONENAND_MEMORY_MAP(0xF221)
+#define ONENAND_REG_SYS_CFG2		ONENAND_MEMORY_MAP(0xF222)
+#define ONENAND_REG_CTRL_STATUS		ONENAND_MEMORY_MAP(0xF240)
+#define ONENAND_REG_INTERRUPT		ONENAND_MEMORY_MAP(0xF241)
+#define ONENAND_REG_START_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24C)
+#define ONENAND_REG_END_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24D)
+#define ONENAND_REG_WP_STATUS		ONENAND_MEMORY_MAP(0xF24E)
+
+#define ONENAND_REG_ECC_STATUS		ONENAND_MEMORY_MAP(0xFF00)
+#define ONENAND_REG_ECC_M0		ONENAND_MEMORY_MAP(0xFF01)
+#define ONENAND_REG_ECC_S0		ONENAND_MEMORY_MAP(0xFF02)
+#define ONENAND_REG_ECC_M1		ONENAND_MEMORY_MAP(0xFF03)
+#define ONENAND_REG_ECC_S1		ONENAND_MEMORY_MAP(0xFF04)
+#define ONENAND_REG_ECC_M2		ONENAND_MEMORY_MAP(0xFF05)
+#define ONENAND_REG_ECC_S2		ONENAND_MEMORY_MAP(0xFF06)
+#define ONENAND_REG_ECC_M3		ONENAND_MEMORY_MAP(0xFF07)
+#define ONENAND_REG_ECC_S3		ONENAND_MEMORY_MAP(0xFF08)
+
+/*
+ * Device ID Register F001h (R)
+ */
+#define DEVICE_IS_FLEXONENAND		(1 << 9)
+#define FLEXONENAND_PI_MASK		(0x3ff)
+#define FLEXONENAND_PI_UNLOCK_SHIFT	(14)
+#define ONENAND_DEVICE_DENSITY_MASK	(0xf)
+#define ONENAND_DEVICE_DENSITY_SHIFT	(4)
+#define ONENAND_DEVICE_IS_DDP		(1 << 3)
+#define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
+#define ONENAND_DEVICE_VCC_MASK		(0x3)
+
+#define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
+#define ONENAND_DEVICE_DENSITY_1Gb	(0x003)
+#define ONENAND_DEVICE_DENSITY_2Gb	(0x004)
+#define ONENAND_DEVICE_DENSITY_4Gb	(0x005)
+
+/*
+ * Version ID Register F002h (R)
+ */
+#define ONENAND_VERSION_PROCESS_SHIFT	(8)
+
+/*
+ * Technology Register F006h (R)
+ */
+#define ONENAND_TECHNOLOGY_IS_MLC	(1 << 0)
+
+/*
+ * Start Address 1 F100h (R/W)
+ */
+#define ONENAND_DDP_SHIFT		(15)
+#define ONENAND_DDP_CHIP0		(0)
+#define ONENAND_DDP_CHIP1		(1 << ONENAND_DDP_SHIFT)
+
+/*
+ * Start Address 8 F107h (R/W)
+ */
+#define ONENAND_FPA_MASK		(0x7f)
+#define ONENAND_FPA_SHIFT		(2)
+#define ONENAND_FSA_MASK		(0x03)
+
+/*
+ * Start Buffer Register F200h (R/W)
+ */
+#define ONENAND_BSA_MASK		(0x03)
+#define ONENAND_BSA_SHIFT		(8)
+#define ONENAND_BSA_BOOTRAM		(0 << 2)
+#define ONENAND_BSA_DATARAM0		(2 << 2)
+#define ONENAND_BSA_DATARAM1		(3 << 2)
+#define ONENAND_BSC_MASK		(0x07)
+
+/*
+ * Command Register F220h (R/W)
+ */
+#define ONENAND_CMD_READ		(0x00)
+#define ONENAND_CMD_READOOB		(0x13)
+#define ONENAND_CMD_PROG		(0x80)
+#define ONENAND_CMD_PROGOOB		(0x1A)
+#define ONENAND_CMD_2X_PROG		(0x7D)
+#define ONENAND_CMD_2X_CACHE_PROG	(0x7F)
+#define ONENAND_CMD_UNLOCK		(0x23)
+#define ONENAND_CMD_LOCK		(0x2A)
+#define ONENAND_CMD_LOCK_TIGHT		(0x2C)
+#define ONENAND_CMD_UNLOCK_ALL		(0x27)
+#define ONENAND_CMD_ERASE		(0x94)
+#define ONENAND_CMD_MULTIBLOCK_ERASE	(0x95)
+#define ONENAND_CMD_ERASE_VERIFY	(0x71)
+#define ONENAND_CMD_RESET		(0xF0)
+#define ONENAND_CMD_READID		(0x90)
+#define FLEXONENAND_CMD_RESET		(0xF3)
+#define FLEXONENAND_CMD_PI_UPDATE	(0x05)
+#define FLEXONENAND_CMD_PI_ACCESS	(0x66)
+#define FLEXONENAND_CMD_RECOVER_LSB	(0x05)
+
+/* NOTE: Those are not *REAL* commands */
+#define ONENAND_CMD_BUFFERRAM		(0x1978)
+#define FLEXONENAND_CMD_READ_PI		(0x1985)
+
+/*
+ * System Configuration 1 Register F221h (R, R/W)
+ */
+#define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
+#define ONENAND_SYS_CFG1_BRL_7		(7 << 12)
+#define ONENAND_SYS_CFG1_BRL_6		(6 << 12)
+#define ONENAND_SYS_CFG1_BRL_5		(5 << 12)
+#define ONENAND_SYS_CFG1_BRL_4		(4 << 12)
+#define ONENAND_SYS_CFG1_BRL_3		(3 << 12)
+#define ONENAND_SYS_CFG1_BRL_10		(2 << 12)
+#define ONENAND_SYS_CFG1_BRL_9		(1 << 12)
+#define ONENAND_SYS_CFG1_BRL_8		(0 << 12)
+#define ONENAND_SYS_CFG1_BRL_SHIFT	(12)
+#define ONENAND_SYS_CFG1_BL_32		(4 << 9)
+#define ONENAND_SYS_CFG1_BL_16		(3 << 9)
+#define ONENAND_SYS_CFG1_BL_8		(2 << 9)
+#define ONENAND_SYS_CFG1_BL_4		(1 << 9)
+#define ONENAND_SYS_CFG1_BL_CONT	(0 << 9)
+#define ONENAND_SYS_CFG1_BL_SHIFT	(9)
+#define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
+#define ONENAND_SYS_CFG1_RDY		(1 << 7)
+#define ONENAND_SYS_CFG1_INT		(1 << 6)
+#define ONENAND_SYS_CFG1_IOBE		(1 << 5)
+#define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)
+
+/*
+ * Controller Status Register F240h (R)
+ */
+#define ONENAND_CTRL_ONGO		(1 << 15)
+#define ONENAND_CTRL_LOCK		(1 << 14)
+#define ONENAND_CTRL_LOAD		(1 << 13)
+#define ONENAND_CTRL_PROGRAM		(1 << 12)
+#define ONENAND_CTRL_ERASE		(1 << 11)
+#define ONENAND_CTRL_ERROR		(1 << 10)
+#define ONENAND_CTRL_RSTB		(1 << 7)
+
+/*
+ * Interrupt Status Register F241h (R)
+ */
+#define ONENAND_INT_MASTER		(1 << 15)
+#define ONENAND_INT_READ		(1 << 7)
+#define ONENAND_INT_WRITE		(1 << 6)
+#define ONENAND_INT_ERASE		(1 << 5)
+#define ONENAND_INT_RESET		(1 << 4)
+#define ONENAND_INT_CLEAR		(0 << 0)
+
+/*
+ * NAND Flash Write Protection Status Register F24Eh (R)
+ */
+#define ONENAND_WP_US			(1 << 2)
+#define ONENAND_WP_LS			(1 << 1)
+#define ONENAND_WP_LTS			(1 << 0)
+
+/*
+ * ECC Status Reigser FF00h (R)
+ */
+#define ONENAND_ECC_1BIT		(1 << 0)
+#define ONENAND_ECC_1BIT_ALL		(0x5555)
+#define ONENAND_ECC_2BIT		(1 << 1)
+#define ONENAND_ECC_2BIT_ALL		(0xAAAA)
+#define ONENAND_ECC_4BIT_UNCORRECTABLE	(0x1010)
+#define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010)
+
+#endif				/* __ONENAND_REG_H */
diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h
new file mode 100644
index 0000000..3822237
--- /dev/null
+++ b/include/linux/mtd/partitions.h
@@ -0,0 +1,110 @@
+/*
+ * MTD partitioning layer definitions
+ *
+ * (C) 2000 Nicolas Pitre <nico@fluxnic.net>
+ *
+ * This code is GPL
+ */
+
+#ifndef MTD_PARTITIONS_H
+#define MTD_PARTITIONS_H
+
+#include <linux/types.h>
+
+
+/*
+ * Partition definition structure:
+ *
+ * An array of struct partition is passed along with a MTD object to
+ * mtd_device_register() to create them.
+ *
+ * For each partition, these fields are available:
+ * name: string that will be used to label the partition's MTD device.
+ * size: the partition size; if defined as MTDPART_SIZ_FULL, the partition
+ * 	will extend to the end of the master MTD device.
+ * offset: absolute starting position within the master MTD device; if
+ * 	defined as MTDPART_OFS_APPEND, the partition will start where the
+ *	previous one ended; if MTDPART_OFS_NXTBLK, at the next erase block;
+ *	if MTDPART_OFS_RETAIN, consume as much as possible, leaving size
+ *	after the end of partition.
+ * mask_flags: contains flags that have to be masked (removed) from the
+ * 	master MTD flag set for the corresponding MTD partition.
+ * 	For example, to force a read-only partition, simply adding
+ * 	MTD_WRITEABLE to the mask_flags will do the trick.
+ *
+ * Note: writeable partitions require their size and offset be
+ * erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK).
+ */
+
+struct mtd_partition {
+	const char *name;		/* identifier string */
+	uint64_t size;			/* partition size */
+	uint64_t offset;		/* offset within the master MTD space */
+	uint32_t mask_flags;		/* master MTD flags to mask out for this partition */
+	struct nand_ecclayout *ecclayout;	/* out of band layout for this partition (NAND only) */
+};
+
+#define MTDPART_OFS_RETAIN	(-3)
+#define MTDPART_OFS_NXTBLK	(-2)
+#define MTDPART_OFS_APPEND	(-1)
+#define MTDPART_SIZ_FULL	(0)
+
+
+struct mtd_info;
+struct device_node;
+
+#ifndef __UBOOT__
+/**
+ * struct mtd_part_parser_data - used to pass data to MTD partition parsers.
+ * @origin: for RedBoot, start address of MTD device
+ * @of_node: for OF parsers, device node containing partitioning information
+ */
+struct mtd_part_parser_data {
+	unsigned long origin;
+	struct device_node *of_node;
+};
+
+
+/*
+ * Functions dealing with the various ways of partitioning the space
+ */
+
+struct mtd_part_parser {
+	struct list_head list;
+	struct module *owner;
+	const char *name;
+	int (*parse_fn)(struct mtd_info *, struct mtd_partition **,
+			struct mtd_part_parser_data *);
+};
+
+extern void register_mtd_parser(struct mtd_part_parser *parser);
+extern void deregister_mtd_parser(struct mtd_part_parser *parser);
+#endif
+
+int mtd_add_partition(struct mtd_info *master, const char *name,
+		      long long offset, long long length);
+int mtd_del_partition(struct mtd_info *master, int partno);
+uint64_t mtd_get_device_size(const struct mtd_info *mtd);
+
+#if defined(CONFIG_MTD_PARTITIONS)
+int mtd_parse_partitions(struct mtd_info *parent, const char **_mtdparts,
+			 struct mtd_partition **_parts, int *_nparts);
+void mtd_free_parsed_partitions(struct mtd_partition *parts,
+				unsigned int nparts);
+#else
+static inline int
+mtd_parse_partitions(struct mtd_info *parent, const char **_mtdparts,
+		     struct mtd_partition **_parts, int *_nparts)
+{
+	*_nparts = 0;
+
+	return 0;
+}
+static inline void
+mtd_free_parsed_partitions(struct mtd_partition *parts, unsigned int nparts)
+{
+	return;
+}
+#endif /* defined(MTD_PARTITIONS) */
+
+#endif
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
new file mode 100644
index 0000000..bd373b9
--- /dev/null
+++ b/include/linux/mtd/rawnand.h
@@ -0,0 +1,1332 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
+ *                        Steven J. Hill <sjhill@realitydiluted.com>
+ *		          Thomas Gleixner <tglx@linutronix.de>
+ *
+ * Info:
+ *	Contains standard defines and IDs for NAND flash devices
+ *
+ * Changelog:
+ *	See git changelog.
+ */
+#ifndef __LINUX_MTD_RAWNAND_H
+#define __LINUX_MTD_RAWNAND_H
+
+#include <config.h>
+
+#include <dm/device.h>
+#include <linux/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/flashchip.h>
+#include <linux/mtd/bbm.h>
+#include <asm/cache.h>
+
+struct mtd_info;
+struct nand_chip;
+struct nand_flash_dev;
+struct device_node;
+
+/* Get the flash and manufacturer id and lookup if the type is supported. */
+struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
+					   struct nand_chip *chip,
+					   int *maf_id, int *dev_id,
+					   struct nand_flash_dev *type);
+
+/* Scan and identify a NAND device */
+int nand_scan(struct mtd_info *mtd, int max_chips);
+/*
+ * Separate phases of nand_scan(), allowing board driver to intervene
+ * and override command or ECC setup according to flash type.
+ */
+int nand_scan_ident(struct mtd_info *mtd, int max_chips,
+			   struct nand_flash_dev *table);
+int nand_scan_tail(struct mtd_info *mtd);
+
+/* Free resources held by the NAND device */
+void nand_release(struct mtd_info *mtd);
+
+/* Internal helper for board drivers which need to override command function */
+void nand_wait_ready(struct mtd_info *mtd);
+
+/*
+ * This constant declares the max. oobsize / page, which
+ * is supported now. If you add a chip with bigger oobsize/page
+ * adjust this accordingly.
+ */
+#define NAND_MAX_OOBSIZE       1664
+#define NAND_MAX_PAGESIZE      16384
+
+/*
+ * Constants for hardware specific CLE/ALE/NCE function
+ *
+ * These are bits which can be or'ed to set/clear multiple
+ * bits in one go.
+ */
+/* Select the chip by setting nCE to low */
+#define NAND_NCE		0x01
+/* Select the command latch by setting CLE to high */
+#define NAND_CLE		0x02
+/* Select the address latch by setting ALE to high */
+#define NAND_ALE		0x04
+
+#define NAND_CTRL_CLE		(NAND_NCE | NAND_CLE)
+#define NAND_CTRL_ALE		(NAND_NCE | NAND_ALE)
+#define NAND_CTRL_CHANGE	0x80
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0		0
+#define NAND_CMD_READ1		1
+#define NAND_CMD_RNDOUT		5
+#define NAND_CMD_PAGEPROG	0x10
+#define NAND_CMD_READOOB	0x50
+#define NAND_CMD_ERASE1		0x60
+#define NAND_CMD_STATUS		0x70
+#define NAND_CMD_SEQIN		0x80
+#define NAND_CMD_RNDIN		0x85
+#define NAND_CMD_READID		0x90
+#define NAND_CMD_ERASE2		0xd0
+#define NAND_CMD_PARAM		0xec
+#define NAND_CMD_GET_FEATURES	0xee
+#define NAND_CMD_SET_FEATURES	0xef
+#define NAND_CMD_RESET		0xff
+
+#define NAND_CMD_LOCK		0x2a
+#define NAND_CMD_UNLOCK1	0x23
+#define NAND_CMD_UNLOCK2	0x24
+
+/* Extended commands for large page devices */
+#define NAND_CMD_READSTART	0x30
+#define NAND_CMD_RNDOUTSTART	0xE0
+#define NAND_CMD_CACHEDPROG	0x15
+
+/* Extended commands for AG-AND device */
+/*
+ * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
+ *       there is no way to distinguish that from NAND_CMD_READ0
+ *       until the remaining sequence of commands has been completed
+ *       so add a high order bit and mask it off in the command.
+ */
+#define NAND_CMD_DEPLETE1	0x100
+#define NAND_CMD_DEPLETE2	0x38
+#define NAND_CMD_STATUS_MULTI	0x71
+#define NAND_CMD_STATUS_ERROR	0x72
+/* multi-bank error status (banks 0-3) */
+#define NAND_CMD_STATUS_ERROR0	0x73
+#define NAND_CMD_STATUS_ERROR1	0x74
+#define NAND_CMD_STATUS_ERROR2	0x75
+#define NAND_CMD_STATUS_ERROR3	0x76
+#define NAND_CMD_STATUS_RESET	0x7f
+#define NAND_CMD_STATUS_CLEAR	0xff
+
+#define NAND_CMD_NONE		-1
+
+/* Status bits */
+#define NAND_STATUS_FAIL	0x01
+#define NAND_STATUS_FAIL_N1	0x02
+#define NAND_STATUS_TRUE_READY	0x20
+#define NAND_STATUS_READY	0x40
+#define NAND_STATUS_WP		0x80
+
+#define NAND_DATA_IFACE_CHECK_ONLY	-1
+
+/*
+ * Constants for ECC_MODES
+ */
+typedef enum {
+	NAND_ECC_NONE,
+	NAND_ECC_SOFT,
+	NAND_ECC_HW,
+	NAND_ECC_HW_SYNDROME,
+	NAND_ECC_HW_OOB_FIRST,
+	NAND_ECC_SOFT_BCH,
+} nand_ecc_modes_t;
+
+enum nand_ecc_algo {
+	NAND_ECC_UNKNOWN,
+	NAND_ECC_HAMMING,
+	NAND_ECC_BCH,
+};
+
+/*
+ * Constants for Hardware ECC
+ */
+/* Reset Hardware ECC for read */
+#define NAND_ECC_READ		0
+/* Reset Hardware ECC for write */
+#define NAND_ECC_WRITE		1
+/* Enable Hardware ECC before syndrome is read back from flash */
+#define NAND_ECC_READSYN	2
+
+/*
+ * Enable generic NAND 'page erased' check. This check is only done when
+ * ecc.correct() returns -EBADMSG.
+ * Set this flag if your implementation does not fix bitflips in erased
+ * pages and you want to rely on the default implementation.
+ */
+#define NAND_ECC_GENERIC_ERASED_CHECK	BIT(0)
+#define NAND_ECC_MAXIMIZE		BIT(1)
+/*
+ * If your controller already sends the required NAND commands when
+ * reading or writing a page, then the framework is not supposed to
+ * send READ0 and SEQIN/PAGEPROG respectively.
+ */
+#define NAND_ECC_CUSTOM_PAGE_ACCESS	BIT(2)
+
+/* Bit mask for flags passed to do_nand_read_ecc */
+#define NAND_GET_DEVICE		0x80
+
+
+/*
+ * Option constants for bizarre disfunctionality and real
+ * features.
+ */
+/* Buswidth is 16 bit */
+#define NAND_BUSWIDTH_16	0x00000002
+/* Device supports partial programming without padding */
+#define NAND_NO_PADDING		0x00000004
+/* Chip has cache program function */
+#define NAND_CACHEPRG		0x00000008
+/* Chip has copy back function */
+#define NAND_COPYBACK		0x00000010
+/*
+ * Chip requires ready check on read (for auto-incremented sequential read).
+ * True only for small page devices; large page devices do not support
+ * autoincrement.
+ */
+#define NAND_NEED_READRDY	0x00000100
+
+/* Chip does not allow subpage writes */
+#define NAND_NO_SUBPAGE_WRITE	0x00000200
+
+/* Device is one of 'new' xD cards that expose fake nand command set */
+#define NAND_BROKEN_XD		0x00000400
+
+/* Device behaves just like nand, but is readonly */
+#define NAND_ROM		0x00000800
+
+/* Device supports subpage reads */
+#define NAND_SUBPAGE_READ	0x00001000
+
+/*
+ * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
+ * patterns.
+ */
+#define NAND_NEED_SCRAMBLING	0x00002000
+
+/* Device needs 3rd row address cycle */
+#define NAND_ROW_ADDR_3		0x00004000
+
+/* Options valid for Samsung large page devices */
+#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
+
+/* Macros to identify the above */
+#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
+#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
+#define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
+
+/* Non chip related options */
+/* This option skips the bbt scan during initialization. */
+#define NAND_SKIP_BBTSCAN	0x00010000
+/*
+ * This option is defined if the board driver allocates its own buffers
+ * (e.g. because it needs them DMA-coherent).
+ */
+#define NAND_OWN_BUFFERS	0x00020000
+/* Chip may not exist, so silence any errors in scan */
+#define NAND_SCAN_SILENT_NODEV	0x00040000
+/*
+ * Autodetect nand buswidth with readid/onfi.
+ * This suppose the driver will configure the hardware in 8 bits mode
+ * when calling nand_scan_ident, and update its configuration
+ * before calling nand_scan_tail.
+ */
+#define NAND_BUSWIDTH_AUTO      0x00080000
+/*
+ * This option could be defined by controller drivers to protect against
+ * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
+ */
+#define NAND_USE_BOUNCE_BUFFER	0x00100000
+
+/* Options set by nand scan */
+/* bbt has already been read */
+#define NAND_BBT_SCANNED	0x40000000
+/* Nand scan has allocated controller struct */
+#define NAND_CONTROLLER_ALLOC	0x80000000
+
+/* Cell info constants */
+#define NAND_CI_CHIPNR_MSK	0x03
+#define NAND_CI_CELLTYPE_MSK	0x0C
+#define NAND_CI_CELLTYPE_SHIFT	2
+
+/* ONFI features */
+#define ONFI_FEATURE_16_BIT_BUS		(1 << 0)
+#define ONFI_FEATURE_EXT_PARAM_PAGE	(1 << 7)
+
+/* ONFI timing mode, used in both asynchronous and synchronous mode */
+#define ONFI_TIMING_MODE_0		(1 << 0)
+#define ONFI_TIMING_MODE_1		(1 << 1)
+#define ONFI_TIMING_MODE_2		(1 << 2)
+#define ONFI_TIMING_MODE_3		(1 << 3)
+#define ONFI_TIMING_MODE_4		(1 << 4)
+#define ONFI_TIMING_MODE_5		(1 << 5)
+#define ONFI_TIMING_MODE_UNKNOWN	(1 << 6)
+
+/* ONFI feature address */
+#define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
+
+/* Vendor-specific feature address (Micron) */
+#define ONFI_FEATURE_ADDR_READ_RETRY	0x89
+
+/* ONFI subfeature parameters length */
+#define ONFI_SUBFEATURE_PARAM_LEN	4
+
+/* ONFI optional commands SET/GET FEATURES supported? */
+#define ONFI_OPT_CMD_SET_GET_FEATURES	(1 << 2)
+
+struct nand_onfi_params {
+	/* rev info and features block */
+	/* 'O' 'N' 'F' 'I'  */
+	u8 sig[4];
+	__le16 revision;
+	__le16 features;
+	__le16 opt_cmd;
+	u8 reserved0[2];
+	__le16 ext_param_page_length; /* since ONFI 2.1 */
+	u8 num_of_param_pages;        /* since ONFI 2.1 */
+	u8 reserved1[17];
+
+	/* manufacturer information block */
+	char manufacturer[12];
+	char model[20];
+	u8 jedec_id;
+	__le16 date_code;
+	u8 reserved2[13];
+
+	/* memory organization block */
+	__le32 byte_per_page;
+	__le16 spare_bytes_per_page;
+	__le32 data_bytes_per_ppage;
+	__le16 spare_bytes_per_ppage;
+	__le32 pages_per_block;
+	__le32 blocks_per_lun;
+	u8 lun_count;
+	u8 addr_cycles;
+	u8 bits_per_cell;
+	__le16 bb_per_lun;
+	__le16 block_endurance;
+	u8 guaranteed_good_blocks;
+	__le16 guaranteed_block_endurance;
+	u8 programs_per_page;
+	u8 ppage_attr;
+	u8 ecc_bits;
+	u8 interleaved_bits;
+	u8 interleaved_ops;
+	u8 reserved3[13];
+
+	/* electrical parameter block */
+	u8 io_pin_capacitance_max;
+	__le16 async_timing_mode;
+	__le16 program_cache_timing_mode;
+	__le16 t_prog;
+	__le16 t_bers;
+	__le16 t_r;
+	__le16 t_ccs;
+	__le16 src_sync_timing_mode;
+	u8 src_ssync_features;
+	__le16 clk_pin_capacitance_typ;
+	__le16 io_pin_capacitance_typ;
+	__le16 input_pin_capacitance_typ;
+	u8 input_pin_capacitance_max;
+	u8 driver_strength_support;
+	__le16 t_int_r;
+	__le16 t_adl;
+	u8 reserved4[8];
+
+	/* vendor */
+	__le16 vendor_revision;
+	u8 vendor[88];
+
+	__le16 crc;
+} __packed;
+
+#define ONFI_CRC_BASE	0x4F4E
+
+/* Extended ECC information Block Definition (since ONFI 2.1) */
+struct onfi_ext_ecc_info {
+	u8 ecc_bits;
+	u8 codeword_size;
+	__le16 bb_per_lun;
+	__le16 block_endurance;
+	u8 reserved[2];
+} __packed;
+
+#define ONFI_SECTION_TYPE_0	0	/* Unused section. */
+#define ONFI_SECTION_TYPE_1	1	/* for additional sections. */
+#define ONFI_SECTION_TYPE_2	2	/* for ECC information. */
+struct onfi_ext_section {
+	u8 type;
+	u8 length;
+} __packed;
+
+#define ONFI_EXT_SECTION_MAX 8
+
+/* Extended Parameter Page Definition (since ONFI 2.1) */
+struct onfi_ext_param_page {
+	__le16 crc;
+	u8 sig[4];             /* 'E' 'P' 'P' 'S' */
+	u8 reserved0[10];
+	struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
+
+	/*
+	 * The actual size of the Extended Parameter Page is in
+	 * @ext_param_page_length of nand_onfi_params{}.
+	 * The following are the variable length sections.
+	 * So we do not add any fields below. Please see the ONFI spec.
+	 */
+} __packed;
+
+struct nand_onfi_vendor_micron {
+	u8 two_plane_read;
+	u8 read_cache;
+	u8 read_unique_id;
+	u8 dq_imped;
+	u8 dq_imped_num_settings;
+	u8 dq_imped_feat_addr;
+	u8 rb_pulldown_strength;
+	u8 rb_pulldown_strength_feat_addr;
+	u8 rb_pulldown_strength_num_settings;
+	u8 otp_mode;
+	u8 otp_page_start;
+	u8 otp_data_prot_addr;
+	u8 otp_num_pages;
+	u8 otp_feat_addr;
+	u8 read_retry_options;
+	u8 reserved[72];
+	u8 param_revision;
+} __packed;
+
+struct jedec_ecc_info {
+	u8 ecc_bits;
+	u8 codeword_size;
+	__le16 bb_per_lun;
+	__le16 block_endurance;
+	u8 reserved[2];
+} __packed;
+
+/* JEDEC features */
+#define JEDEC_FEATURE_16_BIT_BUS	(1 << 0)
+
+struct nand_jedec_params {
+	/* rev info and features block */
+	/* 'J' 'E' 'S' 'D'  */
+	u8 sig[4];
+	__le16 revision;
+	__le16 features;
+	u8 opt_cmd[3];
+	__le16 sec_cmd;
+	u8 num_of_param_pages;
+	u8 reserved0[18];
+
+	/* manufacturer information block */
+	char manufacturer[12];
+	char model[20];
+	u8 jedec_id[6];
+	u8 reserved1[10];
+
+	/* memory organization block */
+	__le32 byte_per_page;
+	__le16 spare_bytes_per_page;
+	u8 reserved2[6];
+	__le32 pages_per_block;
+	__le32 blocks_per_lun;
+	u8 lun_count;
+	u8 addr_cycles;
+	u8 bits_per_cell;
+	u8 programs_per_page;
+	u8 multi_plane_addr;
+	u8 multi_plane_op_attr;
+	u8 reserved3[38];
+
+	/* electrical parameter block */
+	__le16 async_sdr_speed_grade;
+	__le16 toggle_ddr_speed_grade;
+	__le16 sync_ddr_speed_grade;
+	u8 async_sdr_features;
+	u8 toggle_ddr_features;
+	u8 sync_ddr_features;
+	__le16 t_prog;
+	__le16 t_bers;
+	__le16 t_r;
+	__le16 t_r_multi_plane;
+	__le16 t_ccs;
+	__le16 io_pin_capacitance_typ;
+	__le16 input_pin_capacitance_typ;
+	__le16 clk_pin_capacitance_typ;
+	u8 driver_strength_support;
+	__le16 t_adl;
+	u8 reserved4[36];
+
+	/* ECC and endurance block */
+	u8 guaranteed_good_blocks;
+	__le16 guaranteed_block_endurance;
+	struct jedec_ecc_info ecc_info[4];
+	u8 reserved5[29];
+
+	/* reserved */
+	u8 reserved6[148];
+
+	/* vendor */
+	__le16 vendor_rev_num;
+	u8 reserved7[88];
+
+	/* CRC for Parameter Page */
+	__le16 crc;
+} __packed;
+
+/**
+ * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
+ * @lock:               protection lock
+ * @active:		the mtd device which holds the controller currently
+ * @wq:			wait queue to sleep on if a NAND operation is in
+ *			progress used instead of the per chip wait queue
+ *			when a hw controller is available.
+ */
+struct nand_hw_control {
+	spinlock_t lock;
+	struct nand_chip *active;
+};
+
+static inline void nand_hw_control_init(struct nand_hw_control *nfc)
+{
+	nfc->active = NULL;
+	spin_lock_init(&nfc->lock);
+	init_waitqueue_head(&nfc->wq);
+}
+
+/**
+ * struct nand_ecc_step_info - ECC step information of ECC engine
+ * @stepsize: data bytes per ECC step
+ * @strengths: array of supported strengths
+ * @nstrengths: number of supported strengths
+ */
+struct nand_ecc_step_info {
+	int stepsize;
+	const int *strengths;
+	int nstrengths;
+};
+
+/**
+ * struct nand_ecc_caps - capability of ECC engine
+ * @stepinfos: array of ECC step information
+ * @nstepinfos: number of ECC step information
+ * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
+ */
+struct nand_ecc_caps {
+	const struct nand_ecc_step_info *stepinfos;
+	int nstepinfos;
+	int (*calc_ecc_bytes)(int step_size, int strength);
+};
+
+/* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
+#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...)	\
+static const int __name##_strengths[] = { __VA_ARGS__ };	\
+static const struct nand_ecc_step_info __name##_stepinfo = {	\
+	.stepsize = __step,					\
+	.strengths = __name##_strengths,			\
+	.nstrengths = ARRAY_SIZE(__name##_strengths),		\
+};								\
+static const struct nand_ecc_caps __name = {			\
+	.stepinfos = &__name##_stepinfo,			\
+	.nstepinfos = 1,					\
+	.calc_ecc_bytes = __calc,				\
+}
+
+/**
+ * struct nand_ecc_ctrl - Control structure for ECC
+ * @mode:	ECC mode
+ * @algo:	ECC algorithm
+ * @steps:	number of ECC steps per page
+ * @size:	data bytes per ECC step
+ * @bytes:	ECC bytes per step
+ * @strength:	max number of correctible bits per ECC step
+ * @total:	total number of ECC bytes per page
+ * @prepad:	padding information for syndrome based ECC generators
+ * @postpad:	padding information for syndrome based ECC generators
+ * @options:	ECC specific options (see NAND_ECC_XXX flags defined above)
+ * @layout:	ECC layout control struct pointer
+ * @priv:	pointer to private ECC control data
+ * @hwctl:	function to control hardware ECC generator. Must only
+ *		be provided if an hardware ECC is available
+ * @calculate:	function for ECC calculation or readback from ECC hardware
+ * @correct:	function for ECC correction, matching to ECC generator (sw/hw).
+ *		Should return a positive number representing the number of
+ *		corrected bitflips, -EBADMSG if the number of bitflips exceed
+ *		ECC strength, or any other error code if the error is not
+ *		directly related to correction.
+ *		If -EBADMSG is returned the input buffers should be left
+ *		untouched.
+ * @read_page_raw:	function to read a raw page without ECC. This function
+ *			should hide the specific layout used by the ECC
+ *			controller and always return contiguous in-band and
+ *			out-of-band data even if they're not stored
+ *			contiguously on the NAND chip (e.g.
+ *			NAND_ECC_HW_SYNDROME interleaves in-band and
+ *			out-of-band data).
+ * @write_page_raw:	function to write a raw page without ECC. This function
+ *			should hide the specific layout used by the ECC
+ *			controller and consider the passed data as contiguous
+ *			in-band and out-of-band data. ECC controller is
+ *			responsible for doing the appropriate transformations
+ *			to adapt to its specific layout (e.g.
+ *			NAND_ECC_HW_SYNDROME interleaves in-band and
+ *			out-of-band data).
+ * @read_page:	function to read a page according to the ECC generator
+ *		requirements; returns maximum number of bitflips corrected in
+ *		any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
+ * @read_subpage:	function to read parts of the page covered by ECC;
+ *			returns same as read_page()
+ * @write_subpage:	function to write parts of the page covered by ECC.
+ * @write_page:	function to write a page according to the ECC generator
+ *		requirements.
+ * @write_oob_raw:	function to write chip OOB data without ECC
+ * @read_oob_raw:	function to read chip OOB data without ECC
+ * @read_oob:	function to read chip OOB data
+ * @write_oob:	function to write chip OOB data
+ */
+struct nand_ecc_ctrl {
+	nand_ecc_modes_t mode;
+	enum nand_ecc_algo algo;
+	int steps;
+	int size;
+	int bytes;
+	int total;
+	int strength;
+	int prepad;
+	int postpad;
+	unsigned int options;
+	struct nand_ecclayout	*layout;
+	void *priv;
+	void (*hwctl)(struct mtd_info *mtd, int mode);
+	int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
+			uint8_t *ecc_code);
+	int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
+			uint8_t *calc_ecc);
+	int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			uint8_t *buf, int oob_required, int page);
+	int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			const uint8_t *buf, int oob_required, int page);
+	int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
+			uint8_t *buf, int oob_required, int page);
+	int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
+			uint32_t offs, uint32_t len, uint8_t *buf, int page);
+	int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
+			uint32_t offset, uint32_t data_len,
+			const uint8_t *data_buf, int oob_required, int page);
+	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+			const uint8_t *buf, int oob_required, int page);
+	int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			int page);
+	int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			int page);
+	int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
+	int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
+			int page);
+};
+
+static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
+{
+	return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
+}
+
+/**
+ * struct nand_buffers - buffer structure for read/write
+ * @ecccalc:	buffer pointer for calculated ECC, size is oobsize.
+ * @ecccode:	buffer pointer for ECC read from flash, size is oobsize.
+ * @databuf:	buffer pointer for data, size is (page size + oobsize).
+ *
+ * Do not change the order of buffers. databuf and oobrbuf must be in
+ * consecutive order.
+ */
+struct nand_buffers {
+	uint8_t	ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t	ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
+			      ARCH_DMA_MINALIGN)];
+};
+
+/**
+ * struct nand_sdr_timings - SDR NAND chip timings
+ *
+ * This struct defines the timing requirements of a SDR NAND chip.
+ * These information can be found in every NAND datasheets and the timings
+ * meaning are described in the ONFI specifications:
+ * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
+ * Parameters)
+ *
+ * All these timings are expressed in picoseconds.
+ *
+ * @tBERS_max: Block erase time
+ * @tCCS_min: Change column setup time
+ * @tPROG_max: Page program time
+ * @tR_max: Page read time
+ * @tALH_min: ALE hold time
+ * @tADL_min: ALE to data loading time
+ * @tALS_min: ALE setup time
+ * @tAR_min: ALE to RE# delay
+ * @tCEA_max: CE# access time
+ * @tCEH_min: CE# high hold time
+ * @tCH_min:  CE# hold time
+ * @tCHZ_max: CE# high to output hi-Z
+ * @tCLH_min: CLE hold time
+ * @tCLR_min: CLE to RE# delay
+ * @tCLS_min: CLE setup time
+ * @tCOH_min: CE# high to output hold
+ * @tCS_min: CE# setup time
+ * @tDH_min: Data hold time
+ * @tDS_min: Data setup time
+ * @tFEAT_max: Busy time for Set Features and Get Features
+ * @tIR_min: Output hi-Z to RE# low
+ * @tITC_max: Interface and Timing Mode Change time
+ * @tRC_min: RE# cycle time
+ * @tREA_max: RE# access time
+ * @tREH_min: RE# high hold time
+ * @tRHOH_min: RE# high to output hold
+ * @tRHW_min: RE# high to WE# low
+ * @tRHZ_max: RE# high to output hi-Z
+ * @tRLOH_min: RE# low to output hold
+ * @tRP_min: RE# pulse width
+ * @tRR_min: Ready to RE# low (data only)
+ * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
+ *	      rising edge of R/B#.
+ * @tWB_max: WE# high to SR[6] low
+ * @tWC_min: WE# cycle time
+ * @tWH_min: WE# high hold time
+ * @tWHR_min: WE# high to RE# low
+ * @tWP_min: WE# pulse width
+ * @tWW_min: WP# transition to WE# low
+ */
+struct nand_sdr_timings {
+	u64 tBERS_max;
+	u32 tCCS_min;
+	u64 tPROG_max;
+	u64 tR_max;
+	u32 tALH_min;
+	u32 tADL_min;
+	u32 tALS_min;
+	u32 tAR_min;
+	u32 tCEA_max;
+	u32 tCEH_min;
+	u32 tCH_min;
+	u32 tCHZ_max;
+	u32 tCLH_min;
+	u32 tCLR_min;
+	u32 tCLS_min;
+	u32 tCOH_min;
+	u32 tCS_min;
+	u32 tDH_min;
+	u32 tDS_min;
+	u32 tFEAT_max;
+	u32 tIR_min;
+	u32 tITC_max;
+	u32 tRC_min;
+	u32 tREA_max;
+	u32 tREH_min;
+	u32 tRHOH_min;
+	u32 tRHW_min;
+	u32 tRHZ_max;
+	u32 tRLOH_min;
+	u32 tRP_min;
+	u32 tRR_min;
+	u64 tRST_max;
+	u32 tWB_max;
+	u32 tWC_min;
+	u32 tWH_min;
+	u32 tWHR_min;
+	u32 tWP_min;
+	u32 tWW_min;
+};
+
+/**
+ * enum nand_data_interface_type - NAND interface timing type
+ * @NAND_SDR_IFACE:	Single Data Rate interface
+ */
+enum nand_data_interface_type {
+	NAND_SDR_IFACE,
+};
+
+/**
+ * struct nand_data_interface - NAND interface timing
+ * @type:	type of the timing
+ * @timings:	The timing, type according to @type
+ */
+struct nand_data_interface {
+	enum nand_data_interface_type type;
+	union {
+		struct nand_sdr_timings sdr;
+	} timings;
+};
+
+/**
+ * nand_get_sdr_timings - get SDR timing from data interface
+ * @conf:	The data interface
+ */
+static inline const struct nand_sdr_timings *
+nand_get_sdr_timings(const struct nand_data_interface *conf)
+{
+	if (conf->type != NAND_SDR_IFACE)
+		return ERR_PTR(-EINVAL);
+
+	return &conf->timings.sdr;
+}
+
+/**
+ * struct nand_chip - NAND Private Flash Chip Data
+ * @mtd:		MTD device registered to the MTD framework
+ * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the
+ *			flash device
+ * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the
+ *			flash device.
+ * @flash_node:		[BOARDSPECIFIC] device node describing this instance
+ * @read_byte:		[REPLACEABLE] read one byte from the chip
+ * @read_word:		[REPLACEABLE] read one word from the chip
+ * @write_byte:		[REPLACEABLE] write a single byte to the chip on the
+ *			low 8 I/O lines
+ * @write_buf:		[REPLACEABLE] write data from the buffer to the chip
+ * @read_buf:		[REPLACEABLE] read data from the chip into the buffer
+ * @select_chip:	[REPLACEABLE] select chip nr
+ * @block_bad:		[REPLACEABLE] check if a block is bad, using OOB markers
+ * @block_markbad:	[REPLACEABLE] mark a block bad
+ * @cmd_ctrl:		[BOARDSPECIFIC] hardwarespecific function for controlling
+ *			ALE/CLE/nCE. Also used to write command and address
+ * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accessing
+ *			device ready/busy line. If set to NULL no access to
+ *			ready/busy is available and the ready/busy information
+ *			is read from the chip status register.
+ * @cmdfunc:		[REPLACEABLE] hardwarespecific function for writing
+ *			commands to the chip.
+ * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on
+ *			ready.
+ * @setup_read_retry:	[FLASHSPECIFIC] flash (vendor) specific function for
+ *			setting the read-retry mode. Mostly needed for MLC NAND.
+ * @ecc:		[BOARDSPECIFIC] ECC control structure
+ * @buffers:		buffer structure for read/write
+ * @buf_align:		minimum buffer alignment required by a platform
+ * @hwcontrol:		platform-specific hardware control structure
+ * @erase:		[REPLACEABLE] erase function
+ * @scan_bbt:		[REPLACEABLE] function to scan bad block table
+ * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transferring
+ *			data from array to read regs (tR).
+ * @state:		[INTERN] the current state of the NAND device
+ * @oob_poi:		"poison value buffer," used for laying out OOB data
+ *			before writing
+ * @page_shift:		[INTERN] number of address bits in a page (column
+ *			address bits).
+ * @phys_erase_shift:	[INTERN] number of address bits in a physical eraseblock
+ * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
+ * @chip_shift:		[INTERN] number of address bits in one chip
+ * @options:		[BOARDSPECIFIC] various chip options. They can partly
+ *			be set to inform nand_scan about special functionality.
+ *			See the defines for further explanation.
+ * @bbt_options:	[INTERN] bad block specific options. All options used
+ *			here must come from bbm.h. By default, these options
+ *			will be copied to the appropriate nand_bbt_descr's.
+ * @badblockpos:	[INTERN] position of the bad block marker in the oob
+ *			area.
+ * @badblockbits:	[INTERN] minimum number of set bits in a good block's
+ *			bad block marker position; i.e., BBM == 11110111b is
+ *			not bad when badblockbits == 7
+ * @bits_per_cell:	[INTERN] number of bits per cell. i.e., 1 means SLC.
+ * @ecc_strength_ds:	[INTERN] ECC correctability from the datasheet.
+ *			Minimum amount of bit errors per @ecc_step_ds guaranteed
+ *			to be correctable. If unknown, set to zero.
+ * @ecc_step_ds:	[INTERN] ECC step required by the @ecc_strength_ds,
+ *                      also from the datasheet. It is the recommended ECC step
+ *			size, if known; if unknown, set to zero.
+ * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
+ *			      set to the actually used ONFI mode if the chip is
+ *			      ONFI compliant or deduced from the datasheet if
+ *			      the NAND chip is not ONFI compliant.
+ * @numchips:		[INTERN] number of physical chips
+ * @chipsize:		[INTERN] the size of one chip for multichip arrays
+ * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
+ * @pagebuf:		[INTERN] holds the pagenumber which is currently in
+ *			data_buf.
+ * @pagebuf_bitflips:	[INTERN] holds the bitflip count for the page which is
+ *			currently in data_buf.
+ * @subpagesize:	[INTERN] holds the subpagesize
+ * @onfi_version:	[INTERN] holds the chip ONFI version (BCD encoded),
+ *			non 0 if ONFI supported.
+ * @jedec_version:	[INTERN] holds the chip JEDEC version (BCD encoded),
+ *			non 0 if JEDEC supported.
+ * @onfi_params:	[INTERN] holds the ONFI page parameter when ONFI is
+ *			supported, 0 otherwise.
+ * @jedec_params:	[INTERN] holds the JEDEC parameter page when JEDEC is
+ *			supported, 0 otherwise.
+ * @read_retries:	[INTERN] the number of read retry modes supported
+ * @onfi_set_features:	[REPLACEABLE] set the features for ONFI nand
+ * @onfi_get_features:	[REPLACEABLE] get the features for ONFI nand
+ * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
+ *			  chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
+ *			  means the configuration should not be applied but
+ *			  only checked.
+ * @bbt:		[INTERN] bad block table pointer
+ * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
+ *			lookup.
+ * @bbt_md:		[REPLACEABLE] bad block table mirror descriptor
+ * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial
+ *			bad block scan.
+ * @controller:		[REPLACEABLE] a pointer to a hardware controller
+ *			structure which is shared among multiple independent
+ *			devices.
+ * @priv:		[OPTIONAL] pointer to private chip data
+ * @write_page:		[REPLACEABLE] High-level page write function
+ */
+
+struct nand_chip {
+	struct mtd_info mtd;
+	void __iomem *IO_ADDR_R;
+	void __iomem *IO_ADDR_W;
+
+	int flash_node;
+
+	uint8_t (*read_byte)(struct mtd_info *mtd);
+	u16 (*read_word)(struct mtd_info *mtd);
+	void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
+	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
+	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
+	void (*select_chip)(struct mtd_info *mtd, int chip);
+	int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
+	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
+	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
+	int (*dev_ready)(struct mtd_info *mtd);
+	void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
+			int page_addr);
+	int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
+	int (*erase)(struct mtd_info *mtd, int page);
+	int (*scan_bbt)(struct mtd_info *mtd);
+	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+			uint32_t offset, int data_len, const uint8_t *buf,
+			int oob_required, int page, int raw);
+	int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
+	int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
+	int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
+	int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
+				    const struct nand_data_interface *conf);
+
+
+	int chip_delay;
+	unsigned int options;
+	unsigned int bbt_options;
+
+	int page_shift;
+	int phys_erase_shift;
+	int bbt_erase_shift;
+	int chip_shift;
+	int numchips;
+	uint64_t chipsize;
+	int pagemask;
+	int pagebuf;
+	unsigned int pagebuf_bitflips;
+	int subpagesize;
+	uint8_t bits_per_cell;
+	uint16_t ecc_strength_ds;
+	uint16_t ecc_step_ds;
+	int onfi_timing_mode_default;
+	int badblockpos;
+	int badblockbits;
+
+	int onfi_version;
+	int jedec_version;
+	struct nand_onfi_params	onfi_params;
+	struct nand_jedec_params jedec_params;
+ 
+	struct nand_data_interface *data_interface;
+
+	int read_retries;
+
+	flstate_t state;
+
+	uint8_t *oob_poi;
+	struct nand_hw_control *controller;
+	struct nand_ecclayout *ecclayout;
+
+	struct nand_ecc_ctrl ecc;
+	struct nand_buffers *buffers;
+	unsigned long buf_align;
+	struct nand_hw_control hwcontrol;
+
+	uint8_t *bbt;
+	struct nand_bbt_descr *bbt_td;
+	struct nand_bbt_descr *bbt_md;
+
+	struct nand_bbt_descr *badblock_pattern;
+
+	void *priv;
+};
+
+static inline void nand_set_flash_node(struct nand_chip *chip,
+				       ofnode node)
+{
+	chip->flash_node = ofnode_to_offset(node);
+}
+
+static inline ofnode nand_get_flash_node(struct nand_chip *chip)
+{
+	return offset_to_ofnode(chip->flash_node);
+}
+
+static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
+{
+	return container_of(mtd, struct nand_chip, mtd);
+}
+
+static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
+{
+	return &chip->mtd;
+}
+
+static inline void *nand_get_controller_data(struct nand_chip *chip)
+{
+	return chip->priv;
+}
+
+static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
+{
+	chip->priv = priv;
+}
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA	0x98
+#define NAND_MFR_SAMSUNG	0xec
+#define NAND_MFR_FUJITSU	0x04
+#define NAND_MFR_NATIONAL	0x8f
+#define NAND_MFR_RENESAS	0x07
+#define NAND_MFR_STMICRO	0x20
+#define NAND_MFR_HYNIX		0xad
+#define NAND_MFR_MICRON		0x2c
+#define NAND_MFR_AMD		0x01
+#define NAND_MFR_MACRONIX	0xc2
+#define NAND_MFR_EON		0x92
+#define NAND_MFR_SANDISK	0x45
+#define NAND_MFR_INTEL		0x89
+#define NAND_MFR_ATO		0x9b
+
+/* The maximum expected count of bytes in the NAND ID sequence */
+#define NAND_MAX_ID_LEN 8
+
+/*
+ * A helper for defining older NAND chips where the second ID byte fully
+ * defined the chip, including the geometry (chip size, eraseblock size, page
+ * size). All these chips have 512 bytes NAND page size.
+ */
+#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts)          \
+	{ .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
+	  .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
+
+/*
+ * A helper for defining newer chips which report their page size and
+ * eraseblock size via the extended ID bytes.
+ *
+ * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
+ * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
+ * device ID now only represented a particular total chip size (and voltage,
+ * buswidth), and the page size, eraseblock size, and OOB size could vary while
+ * using the same device ID.
+ */
+#define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
+	{ .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
+	  .options = (opts) }
+
+#define NAND_ECC_INFO(_strength, _step)	\
+			{ .strength_ds = (_strength), .step_ds = (_step) }
+#define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
+#define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
+
+/**
+ * struct nand_flash_dev - NAND Flash Device ID Structure
+ * @name: a human-readable name of the NAND chip
+ * @dev_id: the device ID (the second byte of the full chip ID array)
+ * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
+ *          memory address as @id[0])
+ * @dev_id: device ID part of the full chip ID array (refers the same memory
+ *          address as @id[1])
+ * @id: full device ID array
+ * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
+ *            well as the eraseblock size) is determined from the extended NAND
+ *            chip ID array)
+ * @chipsize: total chip size in MiB
+ * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
+ * @options: stores various chip bit options
+ * @id_len: The valid length of the @id.
+ * @oobsize: OOB size
+ * @ecc: ECC correctability and step information from the datasheet.
+ * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
+ *                   @ecc_strength_ds in nand_chip{}.
+ * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
+ *               @ecc_step_ds in nand_chip{}, also from the datasheet.
+ *               For example, the "4bit ECC for each 512Byte" can be set with
+ *               NAND_ECC_INFO(4, 512).
+ * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
+ *			      reset. Should be deduced from timings described
+ *			      in the datasheet.
+ *
+ */
+struct nand_flash_dev {
+	char *name;
+	union {
+		struct {
+			uint8_t mfr_id;
+			uint8_t dev_id;
+		};
+		uint8_t id[NAND_MAX_ID_LEN];
+	};
+	unsigned int pagesize;
+	unsigned int chipsize;
+	unsigned int erasesize;
+	unsigned int options;
+	uint16_t id_len;
+	uint16_t oobsize;
+	struct {
+		uint16_t strength_ds;
+		uint16_t step_ds;
+	} ecc;
+	int onfi_timing_mode_default;
+};
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @name:	Manufacturer name
+ * @id:		manufacturer ID code of device.
+*/
+struct nand_manufacturers {
+	int id;
+	char *name;
+};
+
+extern struct nand_flash_dev nand_flash_ids[];
+extern struct nand_manufacturers nand_manuf_ids[];
+
+int nand_default_bbt(struct mtd_info *mtd);
+int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
+int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
+int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
+int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
+			   int allowbbt);
+int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
+			size_t *retlen, uint8_t *buf);
+
+/*
+* Constants for oob configuration
+*/
+#define NAND_SMALL_BADBLOCK_POS		5
+#define NAND_LARGE_BADBLOCK_POS		0
+
+/**
+ * struct platform_nand_chip - chip level device structure
+ * @nr_chips:		max. number of chips to scan for
+ * @chip_offset:	chip number offset
+ * @nr_partitions:	number of partitions pointed to by partitions (or zero)
+ * @partitions:		mtd partition list
+ * @chip_delay:		R/B delay value in us
+ * @options:		Option flags, e.g. 16bit buswidth
+ * @bbt_options:	BBT option flags, e.g. NAND_BBT_USE_FLASH
+ * @part_probe_types:	NULL-terminated array of probe types
+ */
+struct platform_nand_chip {
+	int nr_chips;
+	int chip_offset;
+	int nr_partitions;
+	struct mtd_partition *partitions;
+	int chip_delay;
+	unsigned int options;
+	unsigned int bbt_options;
+	const char **part_probe_types;
+};
+
+/* Keep gcc happy */
+struct platform_device;
+
+/**
+ * struct platform_nand_ctrl - controller level device structure
+ * @probe:		platform specific function to probe/setup hardware
+ * @remove:		platform specific function to remove/teardown hardware
+ * @hwcontrol:		platform specific hardware control structure
+ * @dev_ready:		platform specific function to read ready/busy pin
+ * @select_chip:	platform specific chip select function
+ * @cmd_ctrl:		platform specific function for controlling
+ *			ALE/CLE/nCE. Also used to write command and address
+ * @write_buf:		platform specific function for write buffer
+ * @read_buf:		platform specific function for read buffer
+ * @read_byte:		platform specific function to read one byte from chip
+ * @priv:		private data to transport driver specific settings
+ *
+ * All fields are optional and depend on the hardware driver requirements
+ */
+struct platform_nand_ctrl {
+	int (*probe)(struct platform_device *pdev);
+	void (*remove)(struct platform_device *pdev);
+	void (*hwcontrol)(struct mtd_info *mtd, int cmd);
+	int (*dev_ready)(struct mtd_info *mtd);
+	void (*select_chip)(struct mtd_info *mtd, int chip);
+	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
+	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
+	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
+	unsigned char (*read_byte)(struct mtd_info *mtd);
+	void *priv;
+};
+
+/**
+ * struct platform_nand_data - container structure for platform-specific data
+ * @chip:		chip level chip structure
+ * @ctrl:		controller level device structure
+ */
+struct platform_nand_data {
+	struct platform_nand_chip chip;
+	struct platform_nand_ctrl ctrl;
+};
+
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+/* return the supported features. */
+static inline int onfi_feature(struct nand_chip *chip)
+{
+	return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
+}
+
+/* return the supported asynchronous timing mode. */
+static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
+{
+	if (!chip->onfi_version)
+		return ONFI_TIMING_MODE_UNKNOWN;
+	return le16_to_cpu(chip->onfi_params.async_timing_mode);
+}
+
+/* return the supported synchronous timing mode. */
+static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
+{
+	if (!chip->onfi_version)
+		return ONFI_TIMING_MODE_UNKNOWN;
+	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
+}
+#else
+static inline int onfi_feature(struct nand_chip *chip)
+{
+	return 0;
+}
+
+static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
+{
+	return ONFI_TIMING_MODE_UNKNOWN;
+}
+
+static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
+{
+	return ONFI_TIMING_MODE_UNKNOWN;
+}
+#endif
+
+int onfi_init_data_interface(struct nand_chip *chip,
+			     struct nand_data_interface *iface,
+			     enum nand_data_interface_type type,
+			     int timing_mode);
+
+/*
+ * Check if it is a SLC nand.
+ * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
+ * We do not distinguish the MLC and TLC now.
+ */
+static inline bool nand_is_slc(struct nand_chip *chip)
+{
+	return chip->bits_per_cell == 1;
+}
+
+/**
+ * Check if the opcode's address should be sent only on the lower 8 bits
+ * @command: opcode to check
+ */
+static inline int nand_opcode_8bits(unsigned int command)
+{
+	switch (command) {
+	case NAND_CMD_READID:
+	case NAND_CMD_PARAM:
+	case NAND_CMD_GET_FEATURES:
+	case NAND_CMD_SET_FEATURES:
+		return 1;
+	default:
+		break;
+	}
+	return 0;
+}
+
+/* return the supported JEDEC features. */
+static inline int jedec_feature(struct nand_chip *chip)
+{
+	return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
+		: 0;
+}
+
+/* Standard NAND functions from nand_base.c */
+void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
+void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
+void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
+void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
+uint8_t nand_read_byte(struct mtd_info *mtd);
+
+/* get timing characteristics from ONFI timing mode. */
+const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
+/* get data interface from ONFI timing mode 0, used after reset. */
+const struct nand_data_interface *nand_get_default_data_interface(void);
+
+int nand_check_erased_ecc_chunk(void *data, int datalen,
+				void *ecc, int ecclen,
+				void *extraoob, int extraooblen,
+				int threshold);
+
+int nand_check_ecc_caps(struct nand_chip *chip,
+			const struct nand_ecc_caps *caps, int oobavail);
+
+int nand_match_ecc_req(struct nand_chip *chip,
+		       const struct nand_ecc_caps *caps,  int oobavail);
+
+int nand_maximize_ecc(struct nand_chip *chip,
+		      const struct nand_ecc_caps *caps, int oobavail);
+
+/* Reset and initialize a NAND device */
+int nand_reset(struct nand_chip *chip, int chipnr);
+
+/* NAND operation helpers */
+int nand_reset_op(struct nand_chip *chip);
+int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
+		   unsigned int len);
+int nand_status_op(struct nand_chip *chip, u8 *status);
+int nand_exit_status_op(struct nand_chip *chip);
+int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
+int nand_read_page_op(struct nand_chip *chip, unsigned int page,
+		      unsigned int offset_in_page, void *buf, unsigned int len);
+int nand_change_read_column_op(struct nand_chip *chip,
+			       unsigned int offset_in_page, void *buf,
+			       unsigned int len, bool force_8bit);
+int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
+		     unsigned int offset_in_page, void *buf, unsigned int len);
+int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
+			    unsigned int offset_in_page, const void *buf,
+			    unsigned int len);
+int nand_prog_page_end_op(struct nand_chip *chip);
+int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
+		      unsigned int offset_in_page, const void *buf,
+		      unsigned int len);
+int nand_change_write_column_op(struct nand_chip *chip,
+				unsigned int offset_in_page, const void *buf,
+				unsigned int len, bool force_8bit);
+int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
+		      bool force_8bit);
+int nand_write_data_op(struct nand_chip *chip, const void *buf,
+		       unsigned int len, bool force_8bit);
+
+#endif /* __LINUX_MTD_RAWNAND_H */
diff --git a/include/linux/mtd/samsung_onenand.h b/include/linux/mtd/samsung_onenand.h
new file mode 100644
index 0000000..7774fec
--- /dev/null
+++ b/include/linux/mtd/samsung_onenand.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2005-2009 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ */
+
+#ifndef __SAMSUNG_ONENAND_H__
+#define __SAMSUNG_ONENAND_H__
+
+/*
+ * OneNAND Controller
+ */
+
+#ifndef __ASSEMBLY__
+struct samsung_onenand {
+	unsigned int	mem_cfg;	/* 0x0000 */
+	unsigned char	res1[0xc];
+	unsigned int	burst_len;	/* 0x0010 */
+	unsigned char	res2[0xc];
+	unsigned int	mem_reset;	/* 0x0020 */
+	unsigned char	res3[0xc];
+	unsigned int	int_err_stat;	/* 0x0030 */
+	unsigned char	res4[0xc];
+	unsigned int	int_err_mask;	/* 0x0040 */
+	unsigned char	res5[0xc];
+	unsigned int	int_err_ack;	/* 0x0050 */
+	unsigned char	res6[0xc];
+	unsigned int	ecc_err_stat;	/* 0x0060 */
+	unsigned char	res7[0xc];
+	unsigned int	manufact_id;	/* 0x0070 */
+	unsigned char	res8[0xc];
+	unsigned int	device_id;	/* 0x0080 */
+	unsigned char	res9[0xc];
+	unsigned int	data_buf_size;	/* 0x0090 */
+	unsigned char	res10[0xc];
+	unsigned int	boot_buf_size;	/* 0x00A0 */
+	unsigned char	res11[0xc];
+	unsigned int	buf_amount;	/* 0x00B0 */
+	unsigned char	res12[0xc];
+	unsigned int	tech;		/* 0x00C0 */
+	unsigned char	res13[0xc];
+	unsigned int	fba;		/* 0x00D0 */
+	unsigned char	res14[0xc];
+	unsigned int	fpa;		/* 0x00E0 */
+	unsigned char	res15[0xc];
+	unsigned int	fsa;		/* 0x00F0 */
+	unsigned char	res16[0x3c];
+	unsigned int	sync_mode;	/* 0x0130 */
+	unsigned char	res17[0xc];
+	unsigned int	trans_spare;	/* 0x0140 */
+	unsigned char	res18[0x3c];
+	unsigned int	err_page_addr;	/* 0x0180 */
+	unsigned char	res19[0x1c];
+	unsigned int	int_pin_en;	/* 0x01A0 */
+	unsigned char	res20[0x1c];
+	unsigned int	acc_clock;	/* 0x01C0 */
+	unsigned char	res21[0x1c];
+	unsigned int	err_blk_addr;	/* 0x01E0 */
+	unsigned char	res22[0xc];
+	unsigned int	flash_ver_id;	/* 0x01F0 */
+	unsigned char	res23[0x6c];
+	unsigned int	watchdog_cnt_low;	/* 0x0260 */
+	unsigned char	res24[0xc];
+	unsigned int	watchdog_cnt_hi;	/* 0x0270 */
+	unsigned char	res25[0xc];
+	unsigned int	sync_write;	/* 0x0280 */
+	unsigned char	res26[0x1c];
+	unsigned int	cold_reset;	/* 0x02A0 */
+	unsigned char	res27[0xc];
+	unsigned int	ddp_device;	/* 0x02B0 */
+	unsigned char	res28[0xc];
+	unsigned int	multi_plane;	/* 0x02C0 */
+	unsigned char	res29[0x1c];
+	unsigned int	trans_mode;	/* 0x02E0 */
+	unsigned char	res30[0x1c];
+	unsigned int	ecc_err_stat2;	/* 0x0300 */
+	unsigned char	res31[0xc];
+	unsigned int	ecc_err_stat3;	/* 0x0310 */
+	unsigned char	res32[0xc];
+	unsigned int	ecc_err_stat4;	/* 0x0320 */
+	unsigned char	res33[0x1c];
+	unsigned int	dev_page_size;	/* 0x0340 */
+	unsigned char	res34[0x4c];
+	unsigned int	int_mon_status;	/* 0x0390 */
+};
+#endif
+
+#define ONENAND_MEM_RESET_HOT	0x3
+#define ONENAND_MEM_RESET_COLD	0x2
+#define ONENAND_MEM_RESET_WARM	0x1
+
+#define INT_ERR_ALL	0x3fff
+#define CACHE_OP_ERR    (1 << 13)
+#define RST_CMP         (1 << 12)
+#define RDY_ACT         (1 << 11)
+#define INT_ACT         (1 << 10)
+#define UNSUP_CMD       (1 << 9)
+#define LOCKED_BLK      (1 << 8)
+#define BLK_RW_CMP      (1 << 7)
+#define ERS_CMP         (1 << 6)
+#define PGM_CMP         (1 << 5)
+#define LOAD_CMP        (1 << 4)
+#define ERS_FAIL        (1 << 3)
+#define PGM_FAIL        (1 << 2)
+#define INT_TO          (1 << 1)
+#define LD_FAIL_ECC_ERR (1 << 0)
+
+#define TSRF		(1 << 0)
+
+/* common initialize function */
+extern void s3c_onenand_init(struct mtd_info *);
+extern int s5pc110_chip_probe(struct mtd_info *);
+extern int s5pc210_chip_probe(struct mtd_info *);
+
+#endif
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
new file mode 100644
index 0000000..f9964a7
--- /dev/null
+++ b/include/linux/mtd/spi-nor.h
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Synced from Linux v4.19
+ */
+
+#ifndef __LINUX_MTD_SPI_NOR_H
+#define __LINUX_MTD_SPI_NOR_H
+
+#include <linux/bitops.h>
+#include <linux/mtd/cfi.h>
+#include <linux/mtd/mtd.h>
+
+/*
+ * Manufacturer IDs
+ *
+ * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
+ * Sometimes these are the same as CFI IDs, but sometimes they aren't.
+ */
+#define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
+#define SNOR_MFR_GIGADEVICE	0xc8
+#define SNOR_MFR_INTEL		CFI_MFR_INTEL
+#define SNOR_MFR_ST		CFI_MFR_ST /* ST Micro <--> Micron */
+#define SNOR_MFR_MICRON		CFI_MFR_MICRON /* ST Micro <--> Micron */
+#define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
+#define SNOR_MFR_SPANSION	CFI_MFR_AMD
+#define SNOR_MFR_SST		CFI_MFR_SST
+#define SNOR_MFR_WINBOND	0xef /* Also used by some Spansion */
+
+/*
+ * Note on opcode nomenclature: some opcodes have a format like
+ * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
+ * of I/O lines used for the opcode, address, and data (respectively). The
+ * FUNCTION has an optional suffix of '4', to represent an opcode which
+ * requires a 4-byte (32-bit) address.
+ */
+
+/* Flash opcodes. */
+#define SPINOR_OP_WREN		0x06	/* Write enable */
+#define SPINOR_OP_RDSR		0x05	/* Read status register */
+#define SPINOR_OP_WRSR		0x01	/* Write status register 1 byte */
+#define SPINOR_OP_RDSR2		0x3f	/* Read status register 2 */
+#define SPINOR_OP_WRSR2		0x3e	/* Write status register 2 */
+#define SPINOR_OP_READ		0x03	/* Read data bytes (low frequency) */
+#define SPINOR_OP_READ_FAST	0x0b	/* Read data bytes (high frequency) */
+#define SPINOR_OP_READ_1_1_2	0x3b	/* Read data bytes (Dual Output SPI) */
+#define SPINOR_OP_READ_1_2_2	0xbb	/* Read data bytes (Dual I/O SPI) */
+#define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad Output SPI) */
+#define SPINOR_OP_READ_1_4_4	0xeb	/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_PP		0x02	/* Page program (up to 256 bytes) */
+#define SPINOR_OP_PP_1_1_4	0x32	/* Quad page program */
+#define SPINOR_OP_PP_1_4_4	0x38	/* Quad page program */
+#define SPINOR_OP_BE_4K		0x20	/* Erase 4KiB block */
+#define SPINOR_OP_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */
+#define SPINOR_OP_BE_32K	0x52	/* Erase 32KiB block */
+#define SPINOR_OP_CHIP_ERASE	0xc7	/* Erase whole flash chip */
+#define SPINOR_OP_SE		0xd8	/* Sector erase (usually 64KiB) */
+#define SPINOR_OP_RDID		0x9f	/* Read JEDEC ID */
+#define SPINOR_OP_RDSFDP	0x5a	/* Read SFDP */
+#define SPINOR_OP_RDCR		0x35	/* Read configuration register */
+#define SPINOR_OP_RDFSR		0x70	/* Read flag status register */
+#define SPINOR_OP_CLFSR		0x50	/* Clear flag status register */
+#define SPINOR_OP_RDEAR		0xc8	/* Read Extended Address Register */
+#define SPINOR_OP_WREAR		0xc5	/* Write Extended Address Register */
+
+/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
+#define SPINOR_OP_READ_4B	0x13	/* Read data bytes (low frequency) */
+#define SPINOR_OP_READ_FAST_4B	0x0c	/* Read data bytes (high frequency) */
+#define SPINOR_OP_READ_1_1_2_4B	0x3c	/* Read data bytes (Dual Output SPI) */
+#define SPINOR_OP_READ_1_2_2_4B	0xbc	/* Read data bytes (Dual I/O SPI) */
+#define SPINOR_OP_READ_1_1_4_4B	0x6c	/* Read data bytes (Quad Output SPI) */
+#define SPINOR_OP_READ_1_4_4_4B	0xec	/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_PP_4B		0x12	/* Page program (up to 256 bytes) */
+#define SPINOR_OP_PP_1_1_4_4B	0x34	/* Quad page program */
+#define SPINOR_OP_PP_1_4_4_4B	0x3e	/* Quad page program */
+#define SPINOR_OP_BE_4K_4B	0x21	/* Erase 4KiB block */
+#define SPINOR_OP_BE_32K_4B	0x5c	/* Erase 32KiB block */
+#define SPINOR_OP_SE_4B		0xdc	/* Sector erase (usually 64KiB) */
+
+/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
+#define SPINOR_OP_READ_1_1_1_DTR	0x0d
+#define SPINOR_OP_READ_1_2_2_DTR	0xbd
+#define SPINOR_OP_READ_1_4_4_DTR	0xed
+
+#define SPINOR_OP_READ_1_1_1_DTR_4B	0x0e
+#define SPINOR_OP_READ_1_2_2_DTR_4B	0xbe
+#define SPINOR_OP_READ_1_4_4_DTR_4B	0xee
+
+/* Used for SST flashes only. */
+#define SPINOR_OP_BP		0x02	/* Byte program */
+#define SPINOR_OP_WRDI		0x04	/* Write disable */
+#define SPINOR_OP_AAI_WP	0xad	/* Auto address increment word program */
+
+/* Used for SST26* flashes only. */
+#define SPINOR_OP_READ_BPR	0x72	/* Read block protection register */
+#define SPINOR_OP_WRITE_BPR	0x42	/* Write block protection register */
+
+/* Used for S3AN flashes only */
+#define SPINOR_OP_XSE		0x50	/* Sector erase */
+#define SPINOR_OP_XPP		0x82	/* Page program */
+#define SPINOR_OP_XRDSR		0xd7	/* Read status register */
+
+#define XSR_PAGESIZE		BIT(0)	/* Page size in Po2 or Linear */
+#define XSR_RDY			BIT(7)	/* Ready */
+
+/* Used for Macronix and Winbond flashes. */
+#define SPINOR_OP_EN4B		0xb7	/* Enter 4-byte mode */
+#define SPINOR_OP_EX4B		0xe9	/* Exit 4-byte mode */
+
+/* Used for Spansion flashes only. */
+#define SPINOR_OP_BRWR		0x17	/* Bank register write */
+#define SPINOR_OP_BRRD		0x16	/* Bank register read */
+#define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */
+
+/* Used for Micron flashes only. */
+#define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
+#define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
+
+/* Status Register bits. */
+#define SR_WIP			BIT(0)	/* Write in progress */
+#define SR_WEL			BIT(1)	/* Write enable latch */
+/* meaning of other SR_* bits may differ between vendors */
+#define SR_BP0			BIT(2)	/* Block protect 0 */
+#define SR_BP1			BIT(3)	/* Block protect 1 */
+#define SR_BP2			BIT(4)	/* Block protect 2 */
+#define SR_TB			BIT(5)	/* Top/Bottom protect */
+#define SR_SRWD			BIT(7)	/* SR write protect */
+/* Spansion/Cypress specific status bits */
+#define SR_E_ERR		BIT(5)
+#define SR_P_ERR		BIT(6)
+
+#define SR_QUAD_EN_MX		BIT(6)	/* Macronix Quad I/O */
+
+/* Enhanced Volatile Configuration Register bits */
+#define EVCR_QUAD_EN_MICRON	BIT(7)	/* Micron Quad I/O */
+
+/* Flag Status Register bits */
+#define FSR_READY		BIT(7)	/* Device status, 0 = Busy, 1 = Ready */
+#define FSR_E_ERR		BIT(5)	/* Erase operation status */
+#define FSR_P_ERR		BIT(4)	/* Program operation status */
+#define FSR_PT_ERR		BIT(1)	/* Protection error bit */
+
+/* Configuration Register bits. */
+#define CR_QUAD_EN_SPAN		BIT(1)	/* Spansion Quad I/O */
+
+/* Status Register 2 bits. */
+#define SR2_QUAD_EN_BIT7	BIT(7)
+
+/* Supported SPI protocols */
+#define SNOR_PROTO_INST_MASK	GENMASK(23, 16)
+#define SNOR_PROTO_INST_SHIFT	16
+#define SNOR_PROTO_INST(_nbits)	\
+	((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
+	 SNOR_PROTO_INST_MASK)
+
+#define SNOR_PROTO_ADDR_MASK	GENMASK(15, 8)
+#define SNOR_PROTO_ADDR_SHIFT	8
+#define SNOR_PROTO_ADDR(_nbits)	\
+	((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
+	 SNOR_PROTO_ADDR_MASK)
+
+#define SNOR_PROTO_DATA_MASK	GENMASK(7, 0)
+#define SNOR_PROTO_DATA_SHIFT	0
+#define SNOR_PROTO_DATA(_nbits)	\
+	((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
+	 SNOR_PROTO_DATA_MASK)
+
+#define SNOR_PROTO_IS_DTR	BIT(24)	/* Double Transfer Rate */
+
+#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)	\
+	(SNOR_PROTO_INST(_inst_nbits) |				\
+	 SNOR_PROTO_ADDR(_addr_nbits) |				\
+	 SNOR_PROTO_DATA(_data_nbits))
+#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits)	\
+	(SNOR_PROTO_IS_DTR |					\
+	 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
+
+enum spi_nor_protocol {
+	SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
+	SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
+	SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
+	SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
+	SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
+	SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
+	SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
+	SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
+	SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
+	SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
+
+	SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
+	SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
+	SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
+	SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
+};
+
+static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
+{
+	return !!(proto & SNOR_PROTO_IS_DTR);
+}
+
+static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
+{
+	return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
+		SNOR_PROTO_INST_SHIFT;
+}
+
+static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
+{
+	return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
+		SNOR_PROTO_ADDR_SHIFT;
+}
+
+static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
+{
+	return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
+		SNOR_PROTO_DATA_SHIFT;
+}
+
+static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
+{
+	return spi_nor_get_protocol_data_nbits(proto);
+}
+
+#define SPI_NOR_MAX_CMD_SIZE	8
+enum spi_nor_ops {
+	SPI_NOR_OPS_READ = 0,
+	SPI_NOR_OPS_WRITE,
+	SPI_NOR_OPS_ERASE,
+	SPI_NOR_OPS_LOCK,
+	SPI_NOR_OPS_UNLOCK,
+};
+
+enum spi_nor_option_flags {
+	SNOR_F_USE_FSR		= BIT(0),
+	SNOR_F_HAS_SR_TB	= BIT(1),
+	SNOR_F_NO_OP_CHIP_ERASE	= BIT(2),
+	SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
+	SNOR_F_READY_XSR_RDY	= BIT(4),
+	SNOR_F_USE_CLSR		= BIT(5),
+	SNOR_F_BROKEN_RESET	= BIT(6),
+};
+
+/**
+ * struct flash_info - Forward declaration of a structure used internally by
+ *		       spi_nor_scan()
+ */
+struct flash_info;
+
+/*
+ * TODO: Remove, once all users of spi_flash interface are moved to MTD
+ *
+ * struct spi_flash {
+ *	Defined below (keep this text to enable searching for spi_flash decl)
+ * }
+ */
+#define spi_flash spi_nor
+
+/**
+ * struct spi_nor - Structure for defining a the SPI NOR layer
+ * @mtd:		point to a mtd_info structure
+ * @lock:		the lock for the read/write/erase/lock/unlock operations
+ * @dev:		point to a spi device, or a spi nor controller device.
+ * @info:		spi-nor part JDEC MFR id and other info
+ * @page_size:		the page size of the SPI NOR
+ * @addr_width:		number of address bytes
+ * @erase_opcode:	the opcode for erasing a sector
+ * @read_opcode:	the read opcode
+ * @read_dummy:		the dummy needed by the read operation
+ * @program_opcode:	the program opcode
+ * @bank_read_cmd:	Bank read cmd
+ * @bank_write_cmd:	Bank write cmd
+ * @bank_curr:		Current flash bank
+ * @sst_write_second:	used by the SST write operation
+ * @flags:		flag options for the current SPI-NOR (SNOR_F_*)
+ * @read_proto:		the SPI protocol for read operations
+ * @write_proto:	the SPI protocol for write operations
+ * @reg_proto		the SPI protocol for read_reg/write_reg/erase operations
+ * @cmd_buf:		used by the write_reg
+ * @prepare:		[OPTIONAL] do some preparations for the
+ *			read/write/erase/lock/unlock operations
+ * @unprepare:		[OPTIONAL] do some post work after the
+ *			read/write/erase/lock/unlock operations
+ * @read_reg:		[DRIVER-SPECIFIC] read out the register
+ * @write_reg:		[DRIVER-SPECIFIC] write data to the register
+ * @read:		[DRIVER-SPECIFIC] read data from the SPI NOR
+ * @write:		[DRIVER-SPECIFIC] write data to the SPI NOR
+ * @erase:		[DRIVER-SPECIFIC] erase a sector of the SPI NOR
+ *			at the offset @offs; if not provided by the driver,
+ *			spi-nor will send the erase opcode via write_reg()
+ * @flash_lock:		[FLASH-SPECIFIC] lock a region of the SPI NOR
+ * @flash_unlock:	[FLASH-SPECIFIC] unlock a region of the SPI NOR
+ * @flash_is_locked:	[FLASH-SPECIFIC] check if a region of the SPI NOR is
+ * @quad_enable:	[FLASH-SPECIFIC] enables SPI NOR quad mode
+ *			completely locked
+ * @priv:		the private data
+ */
+struct spi_nor {
+	struct mtd_info		mtd;
+	struct udevice		*dev;
+	struct spi_slave	*spi;
+	const struct flash_info	*info;
+	u32			page_size;
+	u8			addr_width;
+	u8			erase_opcode;
+	u8			read_opcode;
+	u8			read_dummy;
+	u8			program_opcode;
+#ifdef CONFIG_SPI_FLASH_BAR
+	u8			bank_read_cmd;
+	u8			bank_write_cmd;
+	u8			bank_curr;
+#endif
+	enum spi_nor_protocol	read_proto;
+	enum spi_nor_protocol	write_proto;
+	enum spi_nor_protocol	reg_proto;
+	bool			sst_write_second;
+	u32			flags;
+	u8			cmd_buf[SPI_NOR_MAX_CMD_SIZE];
+
+	int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+	void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
+	int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
+	int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
+
+	ssize_t (*read)(struct spi_nor *nor, loff_t from,
+			size_t len, u_char *read_buf);
+	ssize_t (*write)(struct spi_nor *nor, loff_t to,
+			 size_t len, const u_char *write_buf);
+	int (*erase)(struct spi_nor *nor, loff_t offs);
+
+	int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
+	int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
+	int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
+	int (*quad_enable)(struct spi_nor *nor);
+
+	void *priv;
+/* Compatibility for spi_flash, remove once sf layer is merged with mtd */
+	const char *name;
+	u32 size;
+	u32 sector_size;
+	u32 erase_size;
+};
+
+static inline void spi_nor_set_flash_node(struct spi_nor *nor,
+					  const struct device_node *np)
+{
+	mtd_set_of_node(&nor->mtd, np);
+}
+
+static inline const struct
+device_node *spi_nor_get_flash_node(struct spi_nor *nor)
+{
+	return mtd_get_of_node(&nor->mtd);
+}
+
+/**
+ * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
+ * supported by the SPI controller (bus master).
+ * @mask:		the bitmask listing all the supported hw capabilies
+ */
+struct spi_nor_hwcaps {
+	u32	mask;
+};
+
+/*
+ *(Fast) Read capabilities.
+ * MUST be ordered by priority: the higher bit position, the higher priority.
+ * As a matter of performances, it is relevant to use Octo SPI protocols first,
+ * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
+ * (Slow) Read.
+ */
+#define SNOR_HWCAPS_READ_MASK		GENMASK(14, 0)
+#define SNOR_HWCAPS_READ		BIT(0)
+#define SNOR_HWCAPS_READ_FAST		BIT(1)
+#define SNOR_HWCAPS_READ_1_1_1_DTR	BIT(2)
+
+#define SNOR_HWCAPS_READ_DUAL		GENMASK(6, 3)
+#define SNOR_HWCAPS_READ_1_1_2		BIT(3)
+#define SNOR_HWCAPS_READ_1_2_2		BIT(4)
+#define SNOR_HWCAPS_READ_2_2_2		BIT(5)
+#define SNOR_HWCAPS_READ_1_2_2_DTR	BIT(6)
+
+#define SNOR_HWCAPS_READ_QUAD		GENMASK(10, 7)
+#define SNOR_HWCAPS_READ_1_1_4		BIT(7)
+#define SNOR_HWCAPS_READ_1_4_4		BIT(8)
+#define SNOR_HWCAPS_READ_4_4_4		BIT(9)
+#define SNOR_HWCAPS_READ_1_4_4_DTR	BIT(10)
+
+#define SNOR_HWCPAS_READ_OCTO		GENMASK(14, 11)
+#define SNOR_HWCAPS_READ_1_1_8		BIT(11)
+#define SNOR_HWCAPS_READ_1_8_8		BIT(12)
+#define SNOR_HWCAPS_READ_8_8_8		BIT(13)
+#define SNOR_HWCAPS_READ_1_8_8_DTR	BIT(14)
+
+/*
+ * Page Program capabilities.
+ * MUST be ordered by priority: the higher bit position, the higher priority.
+ * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
+ * legacy SPI 1-1-1 protocol.
+ * Note that Dual Page Programs are not supported because there is no existing
+ * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
+ * implements such commands.
+ */
+#define SNOR_HWCAPS_PP_MASK	GENMASK(22, 16)
+#define SNOR_HWCAPS_PP		BIT(16)
+
+#define SNOR_HWCAPS_PP_QUAD	GENMASK(19, 17)
+#define SNOR_HWCAPS_PP_1_1_4	BIT(17)
+#define SNOR_HWCAPS_PP_1_4_4	BIT(18)
+#define SNOR_HWCAPS_PP_4_4_4	BIT(19)
+
+#define SNOR_HWCAPS_PP_OCTO	GENMASK(22, 20)
+#define SNOR_HWCAPS_PP_1_1_8	BIT(20)
+#define SNOR_HWCAPS_PP_1_8_8	BIT(21)
+#define SNOR_HWCAPS_PP_8_8_8	BIT(22)
+
+/**
+ * spi_nor_scan() - scan the SPI NOR
+ * @nor:	the spi_nor structure
+ *
+ * The drivers can use this function to scan the SPI NOR.
+ * In the scanning, it will try to get all the necessary information to
+ * fill the mtd_info{} and the spi_nor{}.
+ *
+ * Return: 0 for success, others for failure.
+ */
+int spi_nor_scan(struct spi_nor *nor);
+
+#endif
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
new file mode 100644
index 0000000..be01e1e
--- /dev/null
+++ b/include/linux/mtd/spinand.h
@@ -0,0 +1,433 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016-2017 Micron Technology, Inc.
+ *
+ *  Authors:
+ *	Peter Pan <peterpandong@micron.com>
+ */
+#ifndef __LINUX_MTD_SPINAND_H
+#define __LINUX_MTD_SPINAND_H
+
+#ifndef __UBOOT__
+#include <linux/mutex.h>
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+#else
+#include <common.h>
+#include <spi.h>
+#include <spi-mem.h>
+#include <linux/mtd/nand.h>
+#endif
+
+/**
+ * Standard SPI NAND flash operations
+ */
+
+#define SPINAND_RESET_OP						\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0xff, 1),				\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+#define SPINAND_WR_EN_DIS_OP(enable)					\
+	SPI_MEM_OP(SPI_MEM_OP_CMD((enable) ? 0x06 : 0x04, 1),		\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+#define SPINAND_READID_OP(ndummy, buf, len)				\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1),				\
+		   SPI_MEM_OP_NO_ADDR,					\
+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 1))
+
+#define SPINAND_SET_FEATURE_OP(reg, valptr)				\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1),				\
+		   SPI_MEM_OP_ADDR(1, reg, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_OUT(1, valptr, 1))
+
+#define SPINAND_GET_FEATURE_OP(reg, valptr)				\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x0f, 1),				\
+		   SPI_MEM_OP_ADDR(1, reg, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_IN(1, valptr, 1))
+
+#define SPINAND_BLK_ERASE_OP(addr)					\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0xd8, 1),				\
+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+#define SPINAND_PAGE_READ_OP(addr)					\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x13, 1),				\
+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+#define SPINAND_PAGE_READ_FROM_CACHE_OP(fast, addr, ndummy, buf, len)	\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1),		\
+		   SPI_MEM_OP_ADDR(2, addr, 1),				\
+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 1))
+
+#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len)	\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),				\
+		   SPI_MEM_OP_ADDR(2, addr, 1),				\
+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 2))
+
+#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len)	\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),				\
+		   SPI_MEM_OP_ADDR(2, addr, 1),				\
+		   SPI_MEM_OP_DUMMY(ndummy, 1),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 4))
+
+#define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len)	\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1),				\
+		   SPI_MEM_OP_ADDR(2, addr, 2),				\
+		   SPI_MEM_OP_DUMMY(ndummy, 2),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 2))
+
+#define SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(addr, ndummy, buf, len)	\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1),				\
+		   SPI_MEM_OP_ADDR(2, addr, 4),				\
+		   SPI_MEM_OP_DUMMY(ndummy, 4),				\
+		   SPI_MEM_OP_DATA_IN(len, buf, 4))
+
+#define SPINAND_PROG_EXEC_OP(addr)					\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1),				\
+		   SPI_MEM_OP_ADDR(3, addr, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_NO_DATA)
+
+#define SPINAND_PROG_LOAD(reset, addr, buf, len)			\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x02 : 0x84, 1),		\
+		   SPI_MEM_OP_ADDR(2, addr, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_OUT(len, buf, 1))
+
+#define SPINAND_PROG_LOAD_X4(reset, addr, buf, len)			\
+	SPI_MEM_OP(SPI_MEM_OP_CMD(reset ? 0x32 : 0x34, 1),		\
+		   SPI_MEM_OP_ADDR(2, addr, 1),				\
+		   SPI_MEM_OP_NO_DUMMY,					\
+		   SPI_MEM_OP_DATA_OUT(len, buf, 4))
+
+/**
+ * Standard SPI NAND flash commands
+ */
+#define SPINAND_CMD_PROG_LOAD_X4		0x32
+#define SPINAND_CMD_PROG_LOAD_RDM_DATA_X4	0x34
+
+/* feature register */
+#define REG_BLOCK_LOCK		0xa0
+#define BL_ALL_UNLOCKED		0x00
+
+/* configuration register */
+#define REG_CFG			0xb0
+#define CFG_OTP_ENABLE		BIT(6)
+#define CFG_ECC_ENABLE		BIT(4)
+#define CFG_QUAD_ENABLE		BIT(0)
+
+/* status register */
+#define REG_STATUS		0xc0
+#define STATUS_BUSY		BIT(0)
+#define STATUS_ERASE_FAILED	BIT(2)
+#define STATUS_PROG_FAILED	BIT(3)
+#define STATUS_ECC_MASK		GENMASK(5, 4)
+#define STATUS_ECC_NO_BITFLIPS	(0 << 4)
+#define STATUS_ECC_HAS_BITFLIPS	(1 << 4)
+#define STATUS_ECC_UNCOR_ERROR	(2 << 4)
+
+struct spinand_op;
+struct spinand_device;
+
+#define SPINAND_MAX_ID_LEN	4
+
+/**
+ * struct spinand_id - SPI NAND id structure
+ * @data: buffer containing the id bytes. Currently 4 bytes large, but can
+ *	  be extended if required
+ * @len: ID length
+ *
+ * struct_spinand_id->data contains all bytes returned after a READ_ID command,
+ * including dummy bytes if the chip does not emit ID bytes right after the
+ * READ_ID command. The responsibility to extract real ID bytes is left to
+ * struct_manufacurer_ops->detect().
+ */
+struct spinand_id {
+	u8 data[SPINAND_MAX_ID_LEN];
+	int len;
+};
+
+/**
+ * struct manufacurer_ops - SPI NAND manufacturer specific operations
+ * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
+ *	    the core calls the struct_manufacurer_ops->detect() hook of each
+ *	    registered manufacturer until one of them return 1. Note that
+ *	    the first thing to check in this hook is that the manufacturer ID
+ *	    in struct_spinand_device->id matches the manufacturer whose
+ *	    ->detect() hook has been called. Should return 1 if there's a
+ *	    match, 0 if the manufacturer ID does not match and a negative
+ *	    error code otherwise. When true is returned, the core assumes
+ *	    that properties of the NAND chip (spinand->base.memorg and
+ *	    spinand->base.eccreq) have been filled
+ * @init: initialize a SPI NAND device
+ * @cleanup: cleanup a SPI NAND device
+ *
+ * Each SPI NAND manufacturer driver should implement this interface so that
+ * NAND chips coming from this vendor can be detected and initialized properly.
+ */
+struct spinand_manufacturer_ops {
+	int (*detect)(struct spinand_device *spinand);
+	int (*init)(struct spinand_device *spinand);
+	void (*cleanup)(struct spinand_device *spinand);
+};
+
+/**
+ * struct spinand_manufacturer - SPI NAND manufacturer instance
+ * @id: manufacturer ID
+ * @name: manufacturer name
+ * @ops: manufacturer operations
+ */
+struct spinand_manufacturer {
+	u8 id;
+	char *name;
+	const struct spinand_manufacturer_ops *ops;
+};
+
+/* SPI NAND manufacturers */
+extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
+extern const struct spinand_manufacturer macronix_spinand_manufacturer;
+extern const struct spinand_manufacturer micron_spinand_manufacturer;
+extern const struct spinand_manufacturer winbond_spinand_manufacturer;
+
+/**
+ * struct spinand_op_variants - SPI NAND operation variants
+ * @ops: the list of variants for a given operation
+ * @nops: the number of variants
+ *
+ * Some operations like read-from-cache/write-to-cache have several variants
+ * depending on the number of IO lines you use to transfer data or address
+ * cycles. This structure is a way to describe the different variants supported
+ * by a chip and let the core pick the best one based on the SPI mem controller
+ * capabilities.
+ */
+struct spinand_op_variants {
+	const struct spi_mem_op *ops;
+	unsigned int nops;
+};
+
+#define SPINAND_OP_VARIANTS(name, ...)					\
+	const struct spinand_op_variants name = {			\
+		.ops = (struct spi_mem_op[]) { __VA_ARGS__ },		\
+		.nops = sizeof((struct spi_mem_op[]){ __VA_ARGS__ }) /	\
+			sizeof(struct spi_mem_op),			\
+	}
+
+/**
+ * spinand_ecc_info - description of the on-die ECC implemented by a SPI NAND
+ *		      chip
+ * @get_status: get the ECC status. Should return a positive number encoding
+ *		the number of corrected bitflips if correction was possible or
+ *		-EBADMSG if there are uncorrectable errors. I can also return
+ *		other negative error codes if the error is not caused by
+ *		uncorrectable bitflips
+ * @ooblayout: the OOB layout used by the on-die ECC implementation
+ */
+struct spinand_ecc_info {
+	int (*get_status)(struct spinand_device *spinand, u8 status);
+	const struct mtd_ooblayout_ops *ooblayout;
+};
+
+#define SPINAND_HAS_QE_BIT		BIT(0)
+
+/**
+ * struct spinand_info - Structure used to describe SPI NAND chips
+ * @model: model name
+ * @devid: device ID
+ * @flags: OR-ing of the SPINAND_XXX flags
+ * @memorg: memory organization
+ * @eccreq: ECC requirements
+ * @eccinfo: on-die ECC info
+ * @op_variants: operations variants
+ * @op_variants.read_cache: variants of the read-cache operation
+ * @op_variants.write_cache: variants of the write-cache operation
+ * @op_variants.update_cache: variants of the update-cache operation
+ * @select_target: function used to select a target/die. Required only for
+ *		   multi-die chips
+ *
+ * Each SPI NAND manufacturer driver should have a spinand_info table
+ * describing all the chips supported by the driver.
+ */
+struct spinand_info {
+	const char *model;
+	u8 devid;
+	u32 flags;
+	struct nand_memory_organization memorg;
+	struct nand_ecc_req eccreq;
+	struct spinand_ecc_info eccinfo;
+	struct {
+		const struct spinand_op_variants *read_cache;
+		const struct spinand_op_variants *write_cache;
+		const struct spinand_op_variants *update_cache;
+	} op_variants;
+	int (*select_target)(struct spinand_device *spinand,
+			     unsigned int target);
+};
+
+#define SPINAND_INFO_OP_VARIANTS(__read, __write, __update)		\
+	{								\
+		.read_cache = __read,					\
+		.write_cache = __write,					\
+		.update_cache = __update,				\
+	}
+
+#define SPINAND_ECCINFO(__ooblayout, __get_status)			\
+	.eccinfo = {							\
+		.ooblayout = __ooblayout,				\
+		.get_status = __get_status,				\
+	}
+
+#define SPINAND_SELECT_TARGET(__func)					\
+	.select_target = __func,
+
+#define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants,	\
+		     __flags, ...)					\
+	{								\
+		.model = __model,					\
+		.devid = __id,						\
+		.memorg = __memorg,					\
+		.eccreq = __eccreq,					\
+		.op_variants = __op_variants,				\
+		.flags = __flags,					\
+		__VA_ARGS__						\
+	}
+
+/**
+ * struct spinand_device - SPI NAND device instance
+ * @base: NAND device instance
+ * @slave: pointer to the SPI slave object
+ * @lock: lock used to serialize accesses to the NAND
+ * @id: NAND ID as returned by READ_ID
+ * @flags: NAND flags
+ * @op_templates: various SPI mem op templates
+ * @op_templates.read_cache: read cache op template
+ * @op_templates.write_cache: write cache op template
+ * @op_templates.update_cache: update cache op template
+ * @select_target: select a specific target/die. Usually called before sending
+ *		   a command addressing a page or an eraseblock embedded in
+ *		   this die. Only required if your chip exposes several dies
+ * @cur_target: currently selected target/die
+ * @eccinfo: on-die ECC information
+ * @cfg_cache: config register cache. One entry per die
+ * @databuf: bounce buffer for data
+ * @oobbuf: bounce buffer for OOB data
+ * @scratchbuf: buffer used for everything but page accesses. This is needed
+ *		because the spi-mem interface explicitly requests that buffers
+ *		passed in spi_mem_op be DMA-able, so we can't based the bufs on
+ *		the stack
+ * @manufacturer: SPI NAND manufacturer information
+ * @priv: manufacturer private data
+ */
+struct spinand_device {
+	struct nand_device base;
+#ifndef __UBOOT__
+	struct spi_mem *spimem;
+	struct mutex lock;
+#else
+	struct spi_slave *slave;
+#endif
+	struct spinand_id id;
+	u32 flags;
+
+	struct {
+		const struct spi_mem_op *read_cache;
+		const struct spi_mem_op *write_cache;
+		const struct spi_mem_op *update_cache;
+	} op_templates;
+
+	int (*select_target)(struct spinand_device *spinand,
+			     unsigned int target);
+	unsigned int cur_target;
+
+	struct spinand_ecc_info eccinfo;
+
+	u8 *cfg_cache;
+	u8 *databuf;
+	u8 *oobbuf;
+	u8 *scratchbuf;
+	const struct spinand_manufacturer *manufacturer;
+	void *priv;
+};
+
+/**
+ * mtd_to_spinand() - Get the SPI NAND device attached to an MTD instance
+ * @mtd: MTD instance
+ *
+ * Return: the SPI NAND device attached to @mtd.
+ */
+static inline struct spinand_device *mtd_to_spinand(struct mtd_info *mtd)
+{
+	return container_of(mtd_to_nanddev(mtd), struct spinand_device, base);
+}
+
+/**
+ * spinand_to_mtd() - Get the MTD device embedded in a SPI NAND device
+ * @spinand: SPI NAND device
+ *
+ * Return: the MTD device embedded in @spinand.
+ */
+static inline struct mtd_info *spinand_to_mtd(struct spinand_device *spinand)
+{
+	return nanddev_to_mtd(&spinand->base);
+}
+
+/**
+ * nand_to_spinand() - Get the SPI NAND device embedding an NAND object
+ * @nand: NAND object
+ *
+ * Return: the SPI NAND device embedding @nand.
+ */
+static inline struct spinand_device *nand_to_spinand(struct nand_device *nand)
+{
+	return container_of(nand, struct spinand_device, base);
+}
+
+/**
+ * spinand_to_nand() - Get the NAND device embedded in a SPI NAND object
+ * @spinand: SPI NAND device
+ *
+ * Return: the NAND device embedded in @spinand.
+ */
+static inline struct nand_device *
+spinand_to_nand(struct spinand_device *spinand)
+{
+	return &spinand->base;
+}
+
+/**
+ * spinand_set_of_node - Attach a DT node to a SPI NAND device
+ * @spinand: SPI NAND device
+ * @np: DT node
+ *
+ * Attach a DT node to a SPI NAND device.
+ */
+static inline void spinand_set_of_node(struct spinand_device *spinand,
+				       const struct device_node *np)
+{
+	nanddev_set_of_node(&spinand->base, np);
+}
+
+int spinand_match_and_init(struct spinand_device *dev,
+			   const struct spinand_info *table,
+			   unsigned int table_size, u8 devid);
+
+int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
+int spinand_select_target(struct spinand_device *spinand, unsigned int target);
+
+#endif /* __LINUX_MTD_SPINAND_H */
diff --git a/include/linux/mtd/st_smi.h b/include/linux/mtd/st_smi.h
new file mode 100644
index 0000000..6058969
--- /dev/null
+++ b/include/linux/mtd/st_smi.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ */
+
+#ifndef ST_SMI_H
+#define ST_SMI_H
+
+/* 0xF800.0000 . 0xFBFF.FFFF	64MB	SMI (Serial Flash Mem) */
+/* 0xFC00.0000 . 0xFC1F.FFFF	2MB	SMI (Serial Flash Reg.) */
+
+#define FLASH_START_ADDRESS	CONFIG_SYS_FLASH_BASE
+#define FLASH_BANK_SIZE		CONFIG_SYS_FLASH_BANK_SIZE
+
+#define SMIBANK0_BASE		(FLASH_START_ADDRESS)
+#define SMIBANK1_BASE		(SMIBANK0_BASE + FLASH_BANK_SIZE)
+#define SMIBANK2_BASE		(SMIBANK1_BASE + FLASH_BANK_SIZE)
+#define SMIBANK3_BASE		(SMIBANK2_BASE + FLASH_BANK_SIZE)
+
+#define BANK0			0
+#define BANK1			1
+#define BANK2			2
+#define BANK3			3
+
+struct smi_regs {
+	u32 smi_cr1;
+	u32 smi_cr2;
+	u32 smi_sr;
+	u32 smi_tr;
+	u32 smi_rr;
+};
+
+/* CONTROL REG 1 */
+#define BANK_EN			0x0000000F	/* enables all banks */
+#define DSEL_TIME		0x00000060	/* Deselect time */
+#define PRESCAL5		0x00000500	/* AHB_CK prescaling value */
+#define PRESCALA		0x00000A00	/* AHB_CK prescaling value */
+#define PRESCAL3		0x00000300	/* AHB_CK prescaling value */
+#define PRESCAL4		0x00000400	/* AHB_CK prescaling value */
+#define SW_MODE			0x10000000	/* enables SW Mode */
+#define WB_MODE			0x20000000	/* Write Burst Mode */
+#define FAST_MODE		0x00008000	/* Fast Mode */
+#define HOLD1			0x00010000
+
+/* CONTROL REG 2 */
+#define RD_STATUS_REG		0x00000400	/* reads status reg */
+#define WE			0x00000800	/* Write Enable */
+#define BANK0_SEL		0x00000000	/* Select Banck0 */
+#define BANK1_SEL		0x00001000	/* Select Banck1 */
+#define BANK2_SEL		0x00002000	/* Select Banck2 */
+#define BANK3_SEL		0x00003000	/* Select Banck3 */
+#define BANKSEL_SHIFT		12
+#define SEND			0x00000080	/* Send data */
+#define TX_LEN_1		0x00000001	/* data length = 1 byte */
+#define TX_LEN_2		0x00000002	/* data length = 2 byte */
+#define TX_LEN_3		0x00000003	/* data length = 3 byte */
+#define TX_LEN_4		0x00000004	/* data length = 4 byte */
+#define RX_LEN_1		0x00000010	/* data length = 1 byte */
+#define RX_LEN_2		0x00000020	/* data length = 2 byte */
+#define RX_LEN_3		0x00000030	/* data length = 3 byte */
+#define RX_LEN_4		0x00000040	/* data length = 4 byte */
+#define TFIE			0x00000100	/* Tx Flag Interrupt Enable */
+#define WCIE			0x00000200	/* WCF Interrupt Enable */
+
+/* STATUS_REG */
+#define INT_WCF_CLR		0xFFFFFDFF	/* clear: WCF clear */
+#define INT_TFF_CLR		0xFFFFFEFF	/* clear: TFF clear */
+#define WIP_BIT			0x00000001	/* WIP Bit of SPI SR */
+#define WEL_BIT			0x00000002	/* WEL Bit of SPI SR */
+#define RSR			0x00000005	/* Read Status regiser */
+#define TFF			0x00000100	/* Transfer Finished FLag */
+#define WCF			0x00000200	/* Transfer Finished FLag */
+#define ERF1			0x00000400	/* Error Flag 1 */
+#define ERF2			0x00000800	/* Error Flag 2 */
+#define WM0			0x00001000	/* WM Bank 0 */
+#define WM1			0x00002000	/* WM Bank 1 */
+#define WM2			0x00004000	/* WM Bank 2 */
+#define WM3			0x00008000	/* WM Bank 3 */
+#define WM_SHIFT		12
+
+/* TR REG */
+#define READ_ID			0x0000009F	/* Read Identification */
+#define BULK_ERASE		0x000000C7	/* BULK erase */
+#define SECTOR_ERASE		0x000000D8	/* SECTOR erase */
+#define WRITE_ENABLE		0x00000006	/* Wenable command to FLASH */
+
+struct flash_dev {
+	u32 density;
+	ulong size;
+	ushort sector_count;
+};
+
+#define SFLASH_PAGE_SIZE	0x100	/* flash page size */
+#define XFER_FINISH_TOUT	15	/* xfer finish timeout(in ms) */
+#define WMODE_TOUT		15	/* write enable timeout(in ms) */
+
+extern void smi_init(void);
+
+#endif
diff --git a/include/linux/mtd/ubi.h b/include/linux/mtd/ubi.h
new file mode 100644
index 0000000..badf6a0
--- /dev/null
+++ b/include/linux/mtd/ubi.h
@@ -0,0 +1,289 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) International Business Machines Corp., 2006
+ *
+ * Author: Artem Bityutskiy (Битюцкий �ртём)
+ */
+
+#ifndef __LINUX_UBI_H__
+#define __LINUX_UBI_H__
+
+#include <linux/types.h>
+#ifndef __UBOOT__
+#include <linux/ioctl.h>
+#include <linux/scatterlist.h>
+#include <mtd/ubi-user.h>
+#endif
+
+/* All voumes/LEBs */
+#define UBI_ALL -1
+
+/*
+ * Maximum number of scatter gather list entries,
+ * we use only 64 to have a lower memory foot print.
+ */
+#define UBI_MAX_SG_COUNT 64
+
+/*
+ * enum ubi_open_mode - UBI volume open mode constants.
+ *
+ * UBI_READONLY: read-only mode
+ * UBI_READWRITE: read-write mode
+ * UBI_EXCLUSIVE: exclusive mode
+ * UBI_METAONLY: modify only the volume meta-data,
+ *  i.e. the data stored in the volume table, but not in any of volume LEBs.
+ */
+enum {
+	UBI_READONLY = 1,
+	UBI_READWRITE,
+	UBI_EXCLUSIVE,
+	UBI_METAONLY
+};
+
+/**
+ * struct ubi_volume_info - UBI volume description data structure.
+ * @vol_id: volume ID
+ * @ubi_num: UBI device number this volume belongs to
+ * @size: how many physical eraseblocks are reserved for this volume
+ * @used_bytes: how many bytes of data this volume contains
+ * @used_ebs: how many physical eraseblocks of this volume actually contain any
+ *            data
+ * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
+ * @corrupted: non-zero if the volume is corrupted (static volumes only)
+ * @upd_marker: non-zero if the volume has update marker set
+ * @alignment: volume alignment
+ * @usable_leb_size: how many bytes are available in logical eraseblocks of
+ *                   this volume
+ * @name_len: volume name length
+ * @name: volume name
+ * @cdev: UBI volume character device major and minor numbers
+ *
+ * The @corrupted flag is only relevant to static volumes and is always zero
+ * for dynamic ones. This is because UBI does not care about dynamic volume
+ * data protection and only cares about protecting static volume data.
+ *
+ * The @upd_marker flag is set if the volume update operation was interrupted.
+ * Before touching the volume data during the update operation, UBI first sets
+ * the update marker flag for this volume. If the volume update operation was
+ * further interrupted, the update marker indicates this. If the update marker
+ * is set, the contents of the volume is certainly damaged and a new volume
+ * update operation has to be started.
+ *
+ * To put it differently, @corrupted and @upd_marker fields have different
+ * semantics:
+ *     o the @corrupted flag means that this static volume is corrupted for some
+ *       reasons, but not because an interrupted volume update
+ *     o the @upd_marker field means that the volume is damaged because of an
+ *       interrupted update operation.
+ *
+ * I.e., the @corrupted flag is never set if the @upd_marker flag is set.
+ *
+ * The @used_bytes and @used_ebs fields are only really needed for static
+ * volumes and contain the number of bytes stored in this static volume and how
+ * many eraseblock this data occupies. In case of dynamic volumes, the
+ * @used_bytes field is equivalent to @size*@usable_leb_size, and the @used_ebs
+ * field is equivalent to @size.
+ *
+ * In general, logical eraseblock size is a property of the UBI device, not
+ * of the UBI volume. Indeed, the logical eraseblock size depends on the
+ * physical eraseblock size and on how much bytes UBI headers consume. But
+ * because of the volume alignment (@alignment), the usable size of logical
+ * eraseblocks if a volume may be less. The following equation is true:
+ *	@usable_leb_size = LEB size - (LEB size mod @alignment),
+ * where LEB size is the logical eraseblock size defined by the UBI device.
+ *
+ * The alignment is multiple to the minimal flash input/output unit size or %1
+ * if all the available space is used.
+ *
+ * To put this differently, alignment may be considered is a way to change
+ * volume logical eraseblock sizes.
+ */
+struct ubi_volume_info {
+	int ubi_num;
+	int vol_id;
+	int size;
+	long long used_bytes;
+	int used_ebs;
+	int vol_type;
+	int corrupted;
+	int upd_marker;
+	int alignment;
+	int usable_leb_size;
+	int name_len;
+	const char *name;
+	dev_t cdev;
+};
+
+/**
+ * struct ubi_sgl - UBI scatter gather list data structure.
+ * @list_pos: current position in @sg[]
+ * @page_pos: current position in @sg[@list_pos]
+ * @sg: the scatter gather list itself
+ *
+ * ubi_sgl is a wrapper around a scatter list which keeps track of the
+ * current position in the list and the current list item such that
+ * it can be used across multiple ubi_leb_read_sg() calls.
+ */
+struct ubi_sgl {
+	int list_pos;
+	int page_pos;
+#ifndef __UBOOT__
+	struct scatterlist sg[UBI_MAX_SG_COUNT];
+#endif
+};
+
+/**
+ * ubi_sgl_init - initialize an UBI scatter gather list data structure.
+ * @usgl: the UBI scatter gather struct itself
+ *
+ * Please note that you still have to use sg_init_table() or any adequate
+ * function to initialize the unterlaying struct scatterlist.
+ */
+static inline void ubi_sgl_init(struct ubi_sgl *usgl)
+{
+	usgl->list_pos = 0;
+	usgl->page_pos = 0;
+}
+
+/**
+ * struct ubi_device_info - UBI device description data structure.
+ * @ubi_num: ubi device number
+ * @leb_size: logical eraseblock size on this UBI device
+ * @leb_start: starting offset of logical eraseblocks within physical
+ *             eraseblocks
+ * @min_io_size: minimal I/O unit size
+ * @max_write_size: maximum amount of bytes the underlying flash can write at a
+ *                  time (MTD write buffer size)
+ * @ro_mode: if this device is in read-only mode
+ * @cdev: UBI character device major and minor numbers
+ *
+ * Note, @leb_size is the logical eraseblock size offered by the UBI device.
+ * Volumes of this UBI device may have smaller logical eraseblock size if their
+ * alignment is not equivalent to %1.
+ *
+ * The @max_write_size field describes flash write maximum write unit. For
+ * example, NOR flash allows for changing individual bytes, so @min_io_size is
+ * %1. However, it does not mean than NOR flash has to write data byte-by-byte.
+ * Instead, CFI NOR flashes have a write-buffer of, e.g., 64 bytes, and when
+ * writing large chunks of data, they write 64-bytes at a time. Obviously, this
+ * improves write throughput.
+ *
+ * Also, the MTD device may have N interleaved (striped) flash chips
+ * underneath, in which case @min_io_size can be physical min. I/O size of
+ * single flash chip, while @max_write_size can be N * @min_io_size.
+ *
+ * The @max_write_size field is always greater or equivalent to @min_io_size.
+ * E.g., some NOR flashes may have (@min_io_size = 1, @max_write_size = 64). In
+ * contrast, NAND flashes usually have @min_io_size = @max_write_size = NAND
+ * page size.
+ */
+struct ubi_device_info {
+	int ubi_num;
+	int leb_size;
+	int leb_start;
+	int min_io_size;
+	int max_write_size;
+	int ro_mode;
+#ifndef __UBOOT__
+	dev_t cdev;
+#endif
+};
+
+/*
+ * Volume notification types.
+ * @UBI_VOLUME_ADDED: a volume has been added (an UBI device was attached or a
+ *                    volume was created)
+ * @UBI_VOLUME_REMOVED: a volume has been removed (an UBI device was detached
+ *			or a volume was removed)
+ * @UBI_VOLUME_RESIZED: a volume has been re-sized
+ * @UBI_VOLUME_RENAMED: a volume has been re-named
+ * @UBI_VOLUME_UPDATED: data has been written to a volume
+ *
+ * These constants define which type of event has happened when a volume
+ * notification function is invoked.
+ */
+enum {
+	UBI_VOLUME_ADDED,
+	UBI_VOLUME_REMOVED,
+	UBI_VOLUME_RESIZED,
+	UBI_VOLUME_RENAMED,
+	UBI_VOLUME_UPDATED,
+};
+
+/*
+ * struct ubi_notification - UBI notification description structure.
+ * @di: UBI device description object
+ * @vi: UBI volume description object
+ *
+ * UBI notifiers are called with a pointer to an object of this type. The
+ * object describes the notification. Namely, it provides a description of the
+ * UBI device and UBI volume the notification informs about.
+ */
+struct ubi_notification {
+	struct ubi_device_info di;
+	struct ubi_volume_info vi;
+};
+
+/* UBI descriptor given to users when they open UBI volumes */
+struct ubi_volume_desc;
+
+int ubi_get_device_info(int ubi_num, struct ubi_device_info *di);
+void ubi_get_volume_info(struct ubi_volume_desc *desc,
+			 struct ubi_volume_info *vi);
+struct ubi_volume_desc *ubi_open_volume(int ubi_num, int vol_id, int mode);
+struct ubi_volume_desc *ubi_open_volume_nm(int ubi_num, const char *name,
+					   int mode);
+struct ubi_volume_desc *ubi_open_volume_path(const char *pathname, int mode);
+
+#ifndef __UBOOT__
+typedef	int (*notifier_fn_t)(void *nb,
+			unsigned long action, void *data);
+
+struct notifier_block {
+	notifier_fn_t notifier_call;
+	struct notifier_block *next;
+	void *next;
+	int priority;
+};
+
+int ubi_register_volume_notifier(struct notifier_block *nb,
+				 int ignore_existing);
+int ubi_unregister_volume_notifier(struct notifier_block *nb);
+#endif
+
+void ubi_close_volume(struct ubi_volume_desc *desc);
+int ubi_leb_read(struct ubi_volume_desc *desc, int lnum, char *buf, int offset,
+		 int len, int check);
+int ubi_leb_read_sg(struct ubi_volume_desc *desc, int lnum, struct ubi_sgl *sgl,
+		   int offset, int len, int check);
+int ubi_leb_write(struct ubi_volume_desc *desc, int lnum, const void *buf,
+		  int offset, int len);
+int ubi_leb_change(struct ubi_volume_desc *desc, int lnum, const void *buf,
+		   int len);
+int ubi_leb_erase(struct ubi_volume_desc *desc, int lnum);
+int ubi_leb_unmap(struct ubi_volume_desc *desc, int lnum);
+int ubi_leb_map(struct ubi_volume_desc *desc, int lnum);
+int ubi_is_mapped(struct ubi_volume_desc *desc, int lnum);
+int ubi_sync(int ubi_num);
+int ubi_flush(int ubi_num, int vol_id, int lnum);
+
+/*
+ * This function is the same as the 'ubi_leb_read()' function, but it does not
+ * provide the checking capability.
+ */
+static inline int ubi_read(struct ubi_volume_desc *desc, int lnum, char *buf,
+			   int offset, int len)
+{
+	return ubi_leb_read(desc, lnum, buf, offset, len, 0);
+}
+
+/*
+ * This function is the same as the 'ubi_leb_read_sg()' function, but it does
+ * not provide the checking capability.
+ */
+static inline int ubi_read_sg(struct ubi_volume_desc *desc, int lnum,
+			      struct ubi_sgl *sgl, int offset, int len)
+{
+	return ubi_leb_read_sg(desc, lnum, sgl, offset, len, 0);
+}
+#endif /* !__LINUX_UBI_H__ */
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
new file mode 100644
index 0000000..40dad25
--- /dev/null
+++ b/include/linux/netdevice.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * INET		An implementation of the TCP/IP protocol suite for the LINUX
+ *		operating system.  INET is implemented using the  BSD Socket
+ *		interface as the means of communication with the user level.
+ *
+ *		Definitions for the Interfaces handler.
+ *
+ * Version:	@(#)dev.h	1.0.10	08/12/93
+ *
+ * Authors:	Ross Biro
+ *		Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
+ *		Corey Minyard <wf-rch!minyard@relay.EU.net>
+ *		Donald J. Becker, <becker@cesdis.gsfc.nasa.gov>
+ *		Alan Cox, <Alan.Cox@linux.org>
+ *		Bjorn Ekwall. <bj0rn@blox.se>
+ *              Pekka Riikonen <priikone@poseidon.pspt.fi>
+ *
+ *		Moved to /usr/include/linux for NET3
+ */
+#ifndef _LINUX_NETDEVICE_H
+#define _LINUX_NETDEVICE_H
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats {
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error	*/
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+#endif	/* _LINUX_NETDEVICE_H */
diff --git a/include/linux/poison.h b/include/linux/poison.h
new file mode 100644
index 0000000..b3d873b
--- /dev/null
+++ b/include/linux/poison.h
@@ -0,0 +1,11 @@
+#ifndef _LINUX_POISON_H
+#define _LINUX_POISON_H
+
+/********** include/linux/list.h **********/
+/*
+ * used to verify that nobody uses non-initialized list entries.
+ */
+#define LIST_POISON1  ((void *) 0x0)
+#define LIST_POISON2  ((void *) 0x0)
+
+#endif
diff --git a/include/linux/posix_types.h b/include/linux/posix_types.h
new file mode 100644
index 0000000..bd37e1f
--- /dev/null
+++ b/include/linux/posix_types.h
@@ -0,0 +1,48 @@
+#ifndef _LINUX_POSIX_TYPES_H
+#define _LINUX_POSIX_TYPES_H
+
+#include <linux/stddef.h>
+
+/*
+ * This allows for 1024 file descriptors: if NR_OPEN is ever grown
+ * beyond that you'll have to change this too. But 1024 fd's seem to be
+ * enough even for such "real" unices like OSF/1, so hopefully this is
+ * one limit that doesn't have to be changed [again].
+ *
+ * Note that POSIX wants the FD_CLEAR(fd,fdsetp) defines to be in
+ * <sys/time.h> (and thus <linux/time.h>) - but this is a more logical
+ * place for them. Solved by having dummy defines in <sys/time.h>.
+ */
+
+/*
+ * Those macros may have been defined in <gnu/types.h>. But we always
+ * use the ones here.
+ */
+#undef __NFDBITS
+#define __NFDBITS	(8 * sizeof(unsigned long))
+
+#undef __FD_SETSIZE
+#define __FD_SETSIZE	1024
+
+#undef __FDSET_LONGS
+#define __FDSET_LONGS	(__FD_SETSIZE/__NFDBITS)
+
+#undef __FDELT
+#define	__FDELT(d)	((d) / __NFDBITS)
+
+#undef __FDMASK
+#define	__FDMASK(d)	(1UL << ((d) % __NFDBITS))
+
+typedef struct {
+	unsigned long fds_bits [__FDSET_LONGS];
+} __kernel_fd_set;
+
+/* Type of a signal handler.  */
+typedef void (*__kernel_sighandler_t)(int);
+
+/* Type of a SYSV IPC key.  */
+typedef int __kernel_key_t;
+
+#include <asm/posix_types.h>
+
+#endif /* _LINUX_POSIX_TYPES_H */
diff --git a/include/linux/printk.h b/include/linux/printk.h
new file mode 100644
index 0000000..088513a
--- /dev/null
+++ b/include/linux/printk.h
@@ -0,0 +1,79 @@
+#ifndef __KERNEL_PRINTK__
+#define __KERNEL_PRINTK__
+
+#include <stdio.h>
+#include <linux/compiler.h>
+
+#define KERN_EMERG
+#define KERN_ALERT
+#define KERN_CRIT
+#define KERN_ERR
+#define KERN_WARNING
+#define KERN_NOTICE
+#define KERN_INFO
+#define KERN_DEBUG
+#define KERN_CONT
+
+#define printk(fmt, ...) \
+	printf(fmt, ##__VA_ARGS__)
+
+/*
+ * Dummy printk for disabled debugging statements to use whilst maintaining
+ * gcc's format checking.
+ */
+#define no_printk(fmt, ...)				\
+({							\
+	if (0)						\
+		printk(fmt, ##__VA_ARGS__);		\
+	0;						\
+})
+
+#define __printk(level, fmt, ...)					\
+({									\
+	level < CONFIG_LOGLEVEL ? printk(fmt, ##__VA_ARGS__) : 0;	\
+})
+
+#ifndef pr_fmt
+#define pr_fmt(fmt) fmt
+#endif
+
+#define pr_emerg(fmt, ...) \
+	__printk(0, pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_alert(fmt, ...) \
+	__printk(1, pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_crit(fmt, ...) \
+	__printk(2, pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_err(fmt, ...) \
+	__printk(3, pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_warning(fmt, ...) \
+	__printk(4, pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_warn pr_warning
+#define pr_notice(fmt, ...) \
+	__printk(5, pr_fmt(fmt), ##__VA_ARGS__)
+#define pr_info(fmt, ...) \
+	__printk(6, pr_fmt(fmt), ##__VA_ARGS__)
+
+#define pr_cont(fmt, ...) \
+	printk(fmt, ##__VA_ARGS__)
+
+/* pr_devel() should produce zero code unless DEBUG is defined */
+#ifdef DEBUG
+#define pr_devel(fmt, ...) \
+	__printk(7, pr_fmt(fmt), ##__VA_ARGS__)
+#else
+#define pr_devel(fmt, ...) \
+	no_printk(pr_fmt(fmt), ##__VA_ARGS__)
+#endif
+
+#ifdef DEBUG
+#define pr_debug(fmt, ...) \
+	__printk(7, pr_fmt(fmt), ##__VA_ARGS__)
+#else
+#define pr_debug(fmt, ...) \
+	no_printk(pr_fmt(fmt), ##__VA_ARGS__)
+#endif
+
+#define printk_once(fmt, ...) \
+	printk(fmt, ##__VA_ARGS__)
+
+#endif
diff --git a/include/linux/psci.h b/include/linux/psci.h
new file mode 100644
index 0000000..9433df8
--- /dev/null
+++ b/include/linux/psci.h
@@ -0,0 +1,101 @@
+/*
+ * ARM Power State and Coordination Interface (PSCI) header
+ *
+ * This header holds common PSCI defines and macros shared
+ * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space.
+ *
+ * Copyright (C) 2014 Linaro Ltd.
+ * Author: Anup Patel <anup.patel@linaro.org>
+ */
+
+#ifndef _UAPI_LINUX_PSCI_H
+#define _UAPI_LINUX_PSCI_H
+
+/*
+ * PSCI v0.1 interface
+ *
+ * The PSCI v0.1 function numbers are implementation defined.
+ *
+ * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED,
+ * INVALID_PARAMS, and DENIED defined below are applicable
+ * to PSCI v0.1.
+ */
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE			0x84000000
+#define PSCI_0_2_FN(n)				(PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT				0x40000000
+#define PSCI_0_2_FN64_BASE			\
+					(PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n)			(PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION		PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND			PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF			PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON			PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO		PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE			PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE		PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU		PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF			PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET		PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND		PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON			PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO		PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE			PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU	PSCI_0_2_FN64(7)
+
+/* PSCI v0.2 power state encoding for CPU_SUSPEND function */
+#define PSCI_0_2_POWER_STATE_ID_MASK		0xffff
+#define PSCI_0_2_POWER_STATE_ID_SHIFT		0
+#define PSCI_0_2_POWER_STATE_TYPE_SHIFT		16
+#define PSCI_0_2_POWER_STATE_TYPE_MASK		\
+				(0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT)
+#define PSCI_0_2_POWER_STATE_AFFL_SHIFT		24
+#define PSCI_0_2_POWER_STATE_AFFL_MASK		\
+				(0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT)
+
+/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
+#define PSCI_0_2_AFFINITY_LEVEL_ON		0
+#define PSCI_0_2_AFFINITY_LEVEL_OFF		1
+#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING	2
+
+/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */
+#define PSCI_0_2_TOS_UP_MIGRATE			0
+#define PSCI_0_2_TOS_UP_NO_MIGRATE		1
+#define PSCI_0_2_TOS_MP				2
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT		16
+#define PSCI_VERSION_MINOR_MASK			\
+		((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK			~PSCI_VERSION_MINOR_MASK
+#define PSCI_VERSION_MAJOR(ver)			\
+		(((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver)			\
+		((ver) & PSCI_VERSION_MINOR_MASK)
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_RET_SUCCESS			0
+#define PSCI_RET_NOT_SUPPORTED			-1
+#define PSCI_RET_INVALID_PARAMS			-2
+#define PSCI_RET_DENIED				-3
+#define PSCI_RET_ALREADY_ON			-4
+#define PSCI_RET_ON_PENDING			-5
+#define PSCI_RET_INTERNAL_FAILURE		-6
+#define PSCI_RET_NOT_PRESENT			-7
+#define PSCI_RET_DISABLED			-8
+
+#ifdef CONFIG_ARM_PSCI_FW
+unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1,
+			     unsigned long a2, unsigned long a3);
+#else
+unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1,
+			     unsigned long a2, unsigned long a3)
+{
+	return PSCI_RET_DISABLED;
+}
+#endif
+
+#endif /* _UAPI_LINUX_PSCI_H */
diff --git a/include/linux/rbtree.h b/include/linux/rbtree.h
new file mode 100644
index 0000000..1d2b176
--- /dev/null
+++ b/include/linux/rbtree.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+  Red Black Trees
+  (C) 1999  Andrea Arcangeli <andrea@suse.de>
+  
+  linux/include/linux/rbtree.h
+
+  To use rbtrees you'll have to implement your own insert and search cores.
+  This will avoid us to use callbacks and to drop drammatically performances.
+  I know it's not the cleaner way,  but in C (not in C++) to get
+  performances and genericity...
+
+  See Documentation/rbtree.txt for documentation and samples.
+*/
+
+#ifndef	_LINUX_RBTREE_H
+#define	_LINUX_RBTREE_H
+
+#ifndef __UBOOT__
+#include <linux/kernel.h>
+#endif
+#include <linux/stddef.h>
+
+struct rb_node {
+	unsigned long  __rb_parent_color;
+	struct rb_node *rb_right;
+	struct rb_node *rb_left;
+} __attribute__((aligned(sizeof(long))));
+    /* The alignment might seem pointless, but allegedly CRIS needs it */
+
+struct rb_root {
+	struct rb_node *rb_node;
+};
+
+
+#define rb_parent(r)   ((struct rb_node *)((r)->__rb_parent_color & ~3))
+
+#define RB_ROOT	(struct rb_root) { NULL, }
+#define	rb_entry(ptr, type, member) container_of(ptr, type, member)
+
+#define RB_EMPTY_ROOT(root)  ((root)->rb_node == NULL)
+
+/* 'empty' nodes are nodes that are known not to be inserted in an rbree */
+#define RB_EMPTY_NODE(node)  \
+	((node)->__rb_parent_color == (unsigned long)(node))
+#define RB_CLEAR_NODE(node)  \
+	((node)->__rb_parent_color = (unsigned long)(node))
+
+
+extern void rb_insert_color(struct rb_node *, struct rb_root *);
+extern void rb_erase(struct rb_node *, struct rb_root *);
+
+
+/* Find logical next and previous nodes in a tree */
+extern struct rb_node *rb_next(const struct rb_node *);
+extern struct rb_node *rb_prev(const struct rb_node *);
+extern struct rb_node *rb_first(const struct rb_root *);
+extern struct rb_node *rb_last(const struct rb_root *);
+
+/* Postorder iteration - always visit the parent after its children */
+extern struct rb_node *rb_first_postorder(const struct rb_root *);
+extern struct rb_node *rb_next_postorder(const struct rb_node *);
+
+/* Fast replacement of a single node without remove/rebalance/add/rebalance */
+extern void rb_replace_node(struct rb_node *victim, struct rb_node *new, 
+			    struct rb_root *root);
+
+static inline void rb_link_node(struct rb_node * node, struct rb_node * parent,
+				struct rb_node ** rb_link)
+{
+	node->__rb_parent_color = (unsigned long)parent;
+	node->rb_left = node->rb_right = NULL;
+
+	*rb_link = node;
+}
+
+#define rb_entry_safe(ptr, type, member) \
+	({ typeof(ptr) ____ptr = (ptr); \
+	   ____ptr ? rb_entry(____ptr, type, member) : NULL; \
+	})
+
+/**
+ * rbtree_postorder_for_each_entry_safe - iterate over rb_root in post order of
+ * given type safe against removal of rb_node entry
+ *
+ * @pos:	the 'type *' to use as a loop cursor.
+ * @n:		another 'type *' to use as temporary storage
+ * @root:	'rb_root *' of the rbtree.
+ * @field:	the name of the rb_node field within 'type'.
+ */
+#define rbtree_postorder_for_each_entry_safe(pos, n, root, field) \
+	for (pos = rb_entry_safe(rb_first_postorder(root), typeof(*pos), field); \
+	     pos && ({ n = rb_entry_safe(rb_next_postorder(&pos->field), \
+			typeof(*pos), field); 1; }); \
+	     pos = n)
+
+#endif	/* _LINUX_RBTREE_H */
diff --git a/include/linux/rbtree_augmented.h b/include/linux/rbtree_augmented.h
new file mode 100644
index 0000000..da04156
--- /dev/null
+++ b/include/linux/rbtree_augmented.h
@@ -0,0 +1,219 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+  Red Black Trees
+  (C) 1999  Andrea Arcangeli <andrea@suse.de>
+  (C) 2002  David Woodhouse <dwmw2@infradead.org>
+  (C) 2012  Michel Lespinasse <walken@google.com>
+
+  linux/include/linux/rbtree_augmented.h
+*/
+
+#ifndef _LINUX_RBTREE_AUGMENTED_H
+#define _LINUX_RBTREE_AUGMENTED_H
+
+#include <linux/compiler.h>
+#include <linux/rbtree.h>
+
+/*
+ * Please note - only struct rb_augment_callbacks and the prototypes for
+ * rb_insert_augmented() and rb_erase_augmented() are intended to be public.
+ * The rest are implementation details you are not expected to depend on.
+ *
+ * See Documentation/rbtree.txt for documentation and samples.
+ */
+
+struct rb_augment_callbacks {
+	void (*propagate)(struct rb_node *node, struct rb_node *stop);
+	void (*copy)(struct rb_node *old, struct rb_node *new);
+	void (*rotate)(struct rb_node *old, struct rb_node *new);
+};
+
+extern void __rb_insert_augmented(struct rb_node *node, struct rb_root *root,
+	void (*augment_rotate)(struct rb_node *old, struct rb_node *new));
+static inline void
+rb_insert_augmented(struct rb_node *node, struct rb_root *root,
+		    const struct rb_augment_callbacks *augment)
+{
+	__rb_insert_augmented(node, root, augment->rotate);
+}
+
+#define RB_DECLARE_CALLBACKS(rbstatic, rbname, rbstruct, rbfield,	\
+			     rbtype, rbaugmented, rbcompute)		\
+static inline void							\
+rbname ## _propagate(struct rb_node *rb, struct rb_node *stop)		\
+{									\
+	while (rb != stop) {						\
+		rbstruct *node = rb_entry(rb, rbstruct, rbfield);	\
+		rbtype augmented = rbcompute(node);			\
+		if (node->rbaugmented == augmented)			\
+			break;						\
+		node->rbaugmented = augmented;				\
+		rb = rb_parent(&node->rbfield);				\
+	}								\
+}									\
+static inline void							\
+rbname ## _copy(struct rb_node *rb_old, struct rb_node *rb_new)		\
+{									\
+	rbstruct *old = rb_entry(rb_old, rbstruct, rbfield);		\
+	rbstruct *new = rb_entry(rb_new, rbstruct, rbfield);		\
+	new->rbaugmented = old->rbaugmented;				\
+}									\
+static void								\
+rbname ## _rotate(struct rb_node *rb_old, struct rb_node *rb_new)	\
+{									\
+	rbstruct *old = rb_entry(rb_old, rbstruct, rbfield);		\
+	rbstruct *new = rb_entry(rb_new, rbstruct, rbfield);		\
+	new->rbaugmented = old->rbaugmented;				\
+	old->rbaugmented = rbcompute(old);				\
+}									\
+rbstatic const struct rb_augment_callbacks rbname = {			\
+	rbname ## _propagate, rbname ## _copy, rbname ## _rotate	\
+};
+
+
+#define	RB_RED		0
+#define	RB_BLACK	1
+
+#define __rb_parent(pc)    ((struct rb_node *)(pc & ~3))
+
+#define __rb_color(pc)     ((pc) & 1)
+#define __rb_is_black(pc)  __rb_color(pc)
+#define __rb_is_red(pc)    (!__rb_color(pc))
+#define rb_color(rb)       __rb_color((rb)->__rb_parent_color)
+#define rb_is_red(rb)      __rb_is_red((rb)->__rb_parent_color)
+#define rb_is_black(rb)    __rb_is_black((rb)->__rb_parent_color)
+
+static inline void rb_set_parent(struct rb_node *rb, struct rb_node *p)
+{
+	rb->__rb_parent_color = rb_color(rb) | (unsigned long)p;
+}
+
+static inline void rb_set_parent_color(struct rb_node *rb,
+				       struct rb_node *p, int color)
+{
+	rb->__rb_parent_color = (unsigned long)p | color;
+}
+
+static inline void
+__rb_change_child(struct rb_node *old, struct rb_node *new,
+		  struct rb_node *parent, struct rb_root *root)
+{
+	if (parent) {
+		if (parent->rb_left == old)
+			parent->rb_left = new;
+		else
+			parent->rb_right = new;
+	} else
+		root->rb_node = new;
+}
+
+extern void __rb_erase_color(struct rb_node *parent, struct rb_root *root,
+	void (*augment_rotate)(struct rb_node *old, struct rb_node *new));
+
+static __always_inline struct rb_node *
+__rb_erase_augmented(struct rb_node *node, struct rb_root *root,
+		     const struct rb_augment_callbacks *augment)
+{
+	struct rb_node *child = node->rb_right, *tmp = node->rb_left;
+	struct rb_node *parent, *rebalance;
+	unsigned long pc;
+
+	if (!tmp) {
+		/*
+		 * Case 1: node to erase has no more than 1 child (easy!)
+		 *
+		 * Note that if there is one child it must be red due to 5)
+		 * and node must be black due to 4). We adjust colors locally
+		 * so as to bypass __rb_erase_color() later on.
+		 */
+		pc = node->__rb_parent_color;
+		parent = __rb_parent(pc);
+		__rb_change_child(node, child, parent, root);
+		if (child) {
+			child->__rb_parent_color = pc;
+			rebalance = NULL;
+		} else
+			rebalance = __rb_is_black(pc) ? parent : NULL;
+		tmp = parent;
+	} else if (!child) {
+		/* Still case 1, but this time the child is node->rb_left */
+		tmp->__rb_parent_color = pc = node->__rb_parent_color;
+		parent = __rb_parent(pc);
+		__rb_change_child(node, tmp, parent, root);
+		rebalance = NULL;
+		tmp = parent;
+	} else {
+		struct rb_node *successor = child, *child2;
+		tmp = child->rb_left;
+		if (!tmp) {
+			/*
+			 * Case 2: node's successor is its right child
+			 *
+			 *    (n)          (s)
+			 *    / \          / \
+			 *  (x) (s)  ->  (x) (c)
+			 *        \
+			 *        (c)
+			 */
+			parent = successor;
+			child2 = successor->rb_right;
+			augment->copy(node, successor);
+		} else {
+			/*
+			 * Case 3: node's successor is leftmost under
+			 * node's right child subtree
+			 *
+			 *    (n)          (s)
+			 *    / \          / \
+			 *  (x) (y)  ->  (x) (y)
+			 *      /            /
+			 *    (p)          (p)
+			 *    /            /
+			 *  (s)          (c)
+			 *    \
+			 *    (c)
+			 */
+			do {
+				parent = successor;
+				successor = tmp;
+				tmp = tmp->rb_left;
+			} while (tmp);
+			parent->rb_left = child2 = successor->rb_right;
+			successor->rb_right = child;
+			rb_set_parent(child, successor);
+			augment->copy(node, successor);
+			augment->propagate(parent, successor);
+		}
+
+		successor->rb_left = tmp = node->rb_left;
+		rb_set_parent(tmp, successor);
+
+		pc = node->__rb_parent_color;
+		tmp = __rb_parent(pc);
+		__rb_change_child(node, successor, tmp, root);
+		if (child2) {
+			successor->__rb_parent_color = pc;
+			rb_set_parent_color(child2, parent, RB_BLACK);
+			rebalance = NULL;
+		} else {
+			unsigned long pc2 = successor->__rb_parent_color;
+			successor->__rb_parent_color = pc;
+			rebalance = __rb_is_black(pc2) ? parent : NULL;
+		}
+		tmp = successor;
+	}
+
+	augment->propagate(tmp, NULL);
+	return rebalance;
+}
+
+static __always_inline void
+rb_erase_augmented(struct rb_node *node, struct rb_root *root,
+		   const struct rb_augment_callbacks *augment)
+{
+	struct rb_node *rebalance = __rb_erase_augmented(node, root, augment);
+	if (rebalance)
+		__rb_erase_color(rebalance, root, augment->rotate);
+}
+
+#endif	/* _LINUX_RBTREE_AUGMENTED_H */
diff --git a/include/linux/screen_info.h b/include/linux/screen_info.h
new file mode 100644
index 0000000..899fbb4
--- /dev/null
+++ b/include/linux/screen_info.h
@@ -0,0 +1,84 @@
+#ifndef _SCREEN_INFO_H
+#define _SCREEN_INFO_H
+
+#include <linux/types.h>
+
+/*
+ * These are set up by the setup-routine at boot-time:
+ */
+
+struct screen_info {
+	__u8  orig_x;		/* 0x00 */
+	__u8  orig_y;		/* 0x01 */
+	__u16 ext_mem_k;	/* 0x02 */
+	__u16 orig_video_page;	/* 0x04 */
+	__u8  orig_video_mode;	/* 0x06 */
+	__u8  orig_video_cols;	/* 0x07 */
+	__u8  flags;		/* 0x08 */
+	__u8  unused2;		/* 0x09 */
+	__u16 orig_video_ega_bx;/* 0x0a */
+	__u16 unused3;		/* 0x0c */
+	__u8  orig_video_lines;	/* 0x0e */
+	__u8  orig_video_isVGA;	/* 0x0f */
+	__u16 orig_video_points;/* 0x10 */
+
+	/* VESA graphic mode -- linear frame buffer */
+	__u16 lfb_width;	/* 0x12 */
+	__u16 lfb_height;	/* 0x14 */
+	__u16 lfb_depth;	/* 0x16 */
+	__u32 lfb_base;		/* 0x18 */
+	__u32 lfb_size;		/* 0x1c */
+	__u16 cl_magic, cl_offset; /* 0x20 */
+	__u16 lfb_linelength;	/* 0x24 */
+	__u8  red_size;		/* 0x26 */
+	__u8  red_pos;		/* 0x27 */
+	__u8  green_size;	/* 0x28 */
+	__u8  green_pos;	/* 0x29 */
+	__u8  blue_size;	/* 0x2a */
+	__u8  blue_pos;		/* 0x2b */
+	__u8  rsvd_size;	/* 0x2c */
+	__u8  rsvd_pos;		/* 0x2d */
+	__u16 vesapm_seg;	/* 0x2e */
+	__u16 vesapm_off;	/* 0x30 */
+	__u16 pages;		/* 0x32 */
+	__u16 vesa_attributes;	/* 0x34 */
+	__u32 capabilities;     /* 0x36 */
+	__u8  _reserved[6];	/* 0x3a */
+} __attribute__((packed));
+
+#define VIDEO_TYPE_MDA		0x10	/* Monochrome Text Display	*/
+#define VIDEO_TYPE_CGA		0x11	/* CGA Display 			*/
+#define VIDEO_TYPE_EGAM		0x20	/* EGA/VGA in Monochrome Mode	*/
+#define VIDEO_TYPE_EGAC		0x21	/* EGA in Color Mode		*/
+#define VIDEO_TYPE_VGAC		0x22	/* VGA+ in Color Mode		*/
+#define VIDEO_TYPE_VLFB		0x23	/* VESA VGA in graphic mode	*/
+
+#define VIDEO_TYPE_PICA_S3	0x30	/* ACER PICA-61 local S3 video	*/
+#define VIDEO_TYPE_MIPS_G364	0x31    /* MIPS Magnum 4000 G364 video  */
+#define VIDEO_TYPE_SGI          0x33    /* Various SGI graphics hardware */
+
+#define VIDEO_TYPE_TGAC		0x40	/* DEC TGA */
+
+#define VIDEO_TYPE_SUN          0x50    /* Sun frame buffer. */
+#define VIDEO_TYPE_SUNPCI       0x51    /* Sun PCI based frame buffer. */
+
+#define VIDEO_TYPE_PMAC		0x60	/* PowerMacintosh frame buffer. */
+
+#define VIDEO_TYPE_EFI		0x70	/* EFI graphic mode		*/
+
+#define VIDEO_FLAGS_NOCURSOR	(1 << 0) /* The video mode has no cursor set */
+
+#ifdef __KERNEL__
+extern struct screen_info screen_info;
+
+#define ORIG_X			(screen_info.orig_x)
+#define ORIG_Y			(screen_info.orig_y)
+#define ORIG_VIDEO_MODE		(screen_info.orig_video_mode)
+#define ORIG_VIDEO_COLS 	(screen_info.orig_video_cols)
+#define ORIG_VIDEO_EGA_BX	(screen_info.orig_video_ega_bx)
+#define ORIG_VIDEO_LINES	(screen_info.orig_video_lines)
+#define ORIG_VIDEO_ISVGA	(screen_info.orig_video_isVGA)
+#define ORIG_VIDEO_POINTS       (screen_info.orig_video_points)
+#endif /* __KERNEL__ */
+
+#endif /* _SCREEN_INFO_H */
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
new file mode 100644
index 0000000..29c3b5b
--- /dev/null
+++ b/include/linux/serial_reg.h
@@ -0,0 +1,387 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/linux/serial_reg.h
+ *
+ * Copyright (C) 1992, 1994 by Theodore Ts'o.
+ * 
+ * These are the UART port assignments, expressed as offsets from the base
+ * register.  These assignments should hold for any serial port based on
+ * a 8250, 16450, or 16550(A).
+ */
+
+#ifndef _LINUX_SERIAL_REG_H
+#define _LINUX_SERIAL_REG_H
+
+/*
+ * DLAB=0
+ */
+#define UART_RX		0	/* In:  Receive buffer */
+#define UART_TX		0	/* Out: Transmit buffer */
+
+#define UART_IER	1	/* Out: Interrupt Enable Register */
+#define UART_IER_MSI		0x08 /* Enable Modem status interrupt */
+#define UART_IER_RLSI		0x04 /* Enable receiver line status interrupt */
+#define UART_IER_THRI		0x02 /* Enable Transmitter holding register int. */
+#define UART_IER_RDI		0x01 /* Enable receiver data interrupt */
+/*
+ * Sleep mode for ST16650 and TI16750.  For the ST16650, EFR[4]=1
+ */
+#define UART_IERX_SLEEP		0x10 /* Enable sleep mode */
+
+#define UART_IIR	2	/* In:  Interrupt ID Register */
+#define UART_IIR_NO_INT		0x01 /* No interrupts pending */
+#define UART_IIR_ID		0x0e /* Mask for the interrupt ID */
+#define UART_IIR_MSI		0x00 /* Modem status interrupt */
+#define UART_IIR_THRI		0x02 /* Transmitter holding register empty */
+#define UART_IIR_RDI		0x04 /* Receiver data interrupt */
+#define UART_IIR_RLSI		0x06 /* Receiver line status interrupt */
+
+#define UART_IIR_BUSY		0x07 /* DesignWare APB Busy Detect */
+
+#define UART_IIR_RX_TIMEOUT	0x0c /* OMAP RX Timeout interrupt */
+#define UART_IIR_XOFF		0x10 /* OMAP XOFF/Special Character */
+#define UART_IIR_CTS_RTS_DSR	0x20 /* OMAP CTS/RTS/DSR Change */
+
+#define UART_FCR	2	/* Out: FIFO Control Register */
+#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
+#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
+/*
+ * Note: The FIFO trigger levels are chip specific:
+ *	RX:76 = 00  01  10  11	TX:54 = 00  01  10  11
+ * PC16550D:	 1   4   8  14		xx  xx  xx  xx
+ * TI16C550A:	 1   4   8  14          xx  xx  xx  xx
+ * TI16C550C:	 1   4   8  14          xx  xx  xx  xx
+ * ST16C550:	 1   4   8  14		xx  xx  xx  xx
+ * ST16C650:	 8  16  24  28		16   8  24  30	PORT_16650V2
+ * NS16C552:	 1   4   8  14		xx  xx  xx  xx
+ * ST16C654:	 8  16  56  60		 8  16  32  56	PORT_16654
+ * TI16C750:	 1  16  32  56		xx  xx  xx  xx	PORT_16750
+ * TI16C752:	 8  16  56  60		 8  16  32  56
+ * Tegra:	 1   4   8  14		16   8   4   1	PORT_TEGRA
+ */
+#define UART_FCR_R_TRIG_00	0x00
+#define UART_FCR_R_TRIG_01	0x40
+#define UART_FCR_R_TRIG_10	0x80
+#define UART_FCR_R_TRIG_11	0xc0
+#define UART_FCR_T_TRIG_00	0x00
+#define UART_FCR_T_TRIG_01	0x10
+#define UART_FCR_T_TRIG_10	0x20
+#define UART_FCR_T_TRIG_11	0x30
+
+#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
+/* 16650 definitions */
+#define UART_FCR6_R_TRIGGER_8	0x00 /* Mask for receive trigger set at 1 */
+#define UART_FCR6_R_TRIGGER_16	0x40 /* Mask for receive trigger set at 4 */
+#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
+#define UART_FCR6_R_TRIGGER_28	0xC0 /* Mask for receive trigger set at 14 */
+#define UART_FCR6_T_TRIGGER_16	0x00 /* Mask for transmit trigger set at 16 */
+#define UART_FCR6_T_TRIGGER_8	0x10 /* Mask for transmit trigger set at 8 */
+#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
+#define UART_FCR6_T_TRIGGER_30	0x30 /* Mask for transmit trigger set at 30 */
+#define UART_FCR7_64BYTE	0x20 /* Go into 64 byte mode (TI16C750) */
+
+#define UART_LCR	3	/* Out: Line Control Register */
+/*
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_DLAB		0x80 /* Divisor latch access bit */
+#define UART_LCR_SBC		0x40 /* Set break control */
+#define UART_LCR_SPAR		0x20 /* Stick parity (?) */
+#define UART_LCR_EPAR		0x10 /* Even parity select */
+#define UART_LCR_PARITY		0x08 /* Parity Enable */
+#define UART_LCR_STOP		0x04 /* Stop bits: 0=1 bit, 1=2 bits */
+#define UART_LCR_WLEN5		0x00 /* Wordlength: 5 bits */
+#define UART_LCR_WLEN6		0x01 /* Wordlength: 6 bits */
+#define UART_LCR_WLEN7		0x02 /* Wordlength: 7 bits */
+#define UART_LCR_WLEN8		0x03 /* Wordlength: 8 bits */
+
+/*
+ * Access to some registers depends on register access / configuration
+ * mode.
+ */
+#define UART_LCR_CONF_MODE_A	UART_LCR_DLAB	/* Configutation mode A */
+#define UART_LCR_CONF_MODE_B	0xBF		/* Configutation mode B */
+
+#define UART_MCR	4	/* Out: Modem Control Register */
+#define UART_MCR_CLKSEL		0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
+#define UART_MCR_TCRTLR		0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
+#define UART_MCR_XONANY		0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
+#define UART_MCR_AFE		0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
+#define UART_MCR_LOOP		0x10 /* Enable loopback test mode */
+#define UART_MCR_OUT2		0x08 /* Out2 complement */
+#define UART_MCR_OUT1		0x04 /* Out1 complement */
+#define UART_MCR_RTS		0x02 /* RTS complement */
+#define UART_MCR_DTR		0x01 /* DTR complement */
+
+#define UART_LSR	5	/* In:  Line Status Register */
+#define UART_LSR_FIFOE		0x80 /* Fifo error */
+#define UART_LSR_TEMT		0x40 /* Transmitter empty */
+#define UART_LSR_THRE		0x20 /* Transmit-hold-register empty */
+#define UART_LSR_BI		0x10 /* Break interrupt indicator */
+#define UART_LSR_FE		0x08 /* Frame error indicator */
+#define UART_LSR_PE		0x04 /* Parity error indicator */
+#define UART_LSR_OE		0x02 /* Overrun error indicator */
+#define UART_LSR_DR		0x01 /* Receiver data ready */
+#define UART_LSR_BRK_ERROR_BITS	0x1E /* BI, FE, PE, OE bits */
+
+#define UART_MSR	6	/* In:  Modem Status Register */
+#define UART_MSR_DCD		0x80 /* Data Carrier Detect */
+#define UART_MSR_RI		0x40 /* Ring Indicator */
+#define UART_MSR_DSR		0x20 /* Data Set Ready */
+#define UART_MSR_CTS		0x10 /* Clear to Send */
+#define UART_MSR_DDCD		0x08 /* Delta DCD */
+#define UART_MSR_TERI		0x04 /* Trailing edge ring indicator */
+#define UART_MSR_DDSR		0x02 /* Delta DSR */
+#define UART_MSR_DCTS		0x01 /* Delta CTS */
+#define UART_MSR_ANY_DELTA	0x0F /* Any of the delta bits! */
+
+#define UART_SCR	7	/* I/O: Scratch Register */
+
+/*
+ * DLAB=1
+ */
+#define UART_DLL	0	/* Out: Divisor Latch Low */
+#define UART_DLM	1	/* Out: Divisor Latch High */
+
+/*
+ * LCR=0xBF (or DLAB=1 for 16C660)
+ */
+#define UART_EFR	2	/* I/O: Extended Features Register */
+#define UART_XR_EFR	9	/* I/O: Extended Features Register (XR17D15x) */
+#define UART_EFR_CTS		0x80 /* CTS flow control */
+#define UART_EFR_RTS		0x40 /* RTS flow control */
+#define UART_EFR_SCD		0x20 /* Special character detect */
+#define UART_EFR_ECB		0x10 /* Enhanced control bit */
+/*
+ * the low four bits control software flow control
+ */
+
+/*
+ * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
+ */
+#define UART_XON1	4	/* I/O: Xon character 1 */
+#define UART_XON2	5	/* I/O: Xon character 2 */
+#define UART_XOFF1	6	/* I/O: Xoff character 1 */
+#define UART_XOFF2	7	/* I/O: Xoff character 2 */
+
+/*
+ * EFR[4]=1 MCR[6]=1, TI16C752
+ */
+#define UART_TI752_TCR	6	/* I/O: transmission control register */
+#define UART_TI752_TLR	7	/* I/O: trigger level register */
+
+/*
+ * LCR=0xBF, XR16C85x
+ */
+#define UART_TRG	0	/* FCTR bit 7 selects Rx or Tx
+				 * In: Fifo count
+				 * Out: Fifo custom trigger levels */
+/*
+ * These are the definitions for the Programmable Trigger Register
+ */
+#define UART_TRG_1		0x01
+#define UART_TRG_4		0x04
+#define UART_TRG_8		0x08
+#define UART_TRG_16		0x10
+#define UART_TRG_32		0x20
+#define UART_TRG_64		0x40
+#define UART_TRG_96		0x60
+#define UART_TRG_120		0x78
+#define UART_TRG_128		0x80
+
+#define UART_FCTR	1	/* Feature Control Register */
+#define UART_FCTR_RTS_NODELAY	0x00  /* RTS flow control delay */
+#define UART_FCTR_RTS_4DELAY	0x01
+#define UART_FCTR_RTS_6DELAY	0x02
+#define UART_FCTR_RTS_8DELAY	0x03
+#define UART_FCTR_IRDA		0x04  /* IrDa data encode select */
+#define UART_FCTR_TX_INT	0x08  /* Tx interrupt type select */
+#define UART_FCTR_TRGA		0x00  /* Tx/Rx 550 trigger table select */
+#define UART_FCTR_TRGB		0x10  /* Tx/Rx 650 trigger table select */
+#define UART_FCTR_TRGC		0x20  /* Tx/Rx 654 trigger table select */
+#define UART_FCTR_TRGD		0x30  /* Tx/Rx 850 programmable trigger select */
+#define UART_FCTR_SCR_SWAP	0x40  /* Scratch pad register swap */
+#define UART_FCTR_RX		0x00  /* Programmable trigger mode select */
+#define UART_FCTR_TX		0x80  /* Programmable trigger mode select */
+
+/*
+ * LCR=0xBF, FCTR[6]=1
+ */
+#define UART_EMSR	7	/* Extended Mode Select Register */
+#define UART_EMSR_FIFO_COUNT	0x01  /* Rx/Tx select */
+#define UART_EMSR_ALT_COUNT	0x02  /* Alternating count select */
+
+/*
+ * The Intel XScale on-chip UARTs define these bits
+ */
+#define UART_IER_DMAE	0x80	/* DMA Requests Enable */
+#define UART_IER_UUE	0x40	/* UART Unit Enable */
+#define UART_IER_NRZE	0x20	/* NRZ coding Enable */
+#define UART_IER_RTOIE	0x10	/* Receiver Time Out Interrupt Enable */
+
+#define UART_IIR_TOD	0x08	/* Character Timeout Indication Detected */
+
+#define UART_FCR_PXAR1	0x00	/* receive FIFO threshold = 1 */
+#define UART_FCR_PXAR8	0x40	/* receive FIFO threshold = 8 */
+#define UART_FCR_PXAR16	0x80	/* receive FIFO threshold = 16 */
+#define UART_FCR_PXAR32	0xc0	/* receive FIFO threshold = 32 */
+
+/*
+ * Intel MID on-chip HSU (High Speed UART) defined bits
+ */
+#define UART_FCR_HSU_64_1B	0x00	/* receive FIFO treshold = 1 */
+#define UART_FCR_HSU_64_16B	0x40	/* receive FIFO treshold = 16 */
+#define UART_FCR_HSU_64_32B	0x80	/* receive FIFO treshold = 32 */
+#define UART_FCR_HSU_64_56B	0xc0	/* receive FIFO treshold = 56 */
+
+#define UART_FCR_HSU_16_1B	0x00	/* receive FIFO treshold = 1 */
+#define UART_FCR_HSU_16_4B	0x40	/* receive FIFO treshold = 4 */
+#define UART_FCR_HSU_16_8B	0x80	/* receive FIFO treshold = 8 */
+#define UART_FCR_HSU_16_14B	0xc0	/* receive FIFO treshold = 14 */
+
+#define UART_FCR_HSU_64B_FIFO	0x20	/* chose 64 bytes FIFO */
+#define UART_FCR_HSU_16B_FIFO	0x00	/* chose 16 bytes FIFO */
+
+#define UART_FCR_HALF_EMPT_TXI	0x00	/* trigger TX_EMPT IRQ for half empty */
+#define UART_FCR_FULL_EMPT_TXI	0x08	/* trigger TX_EMPT IRQ for full empty */
+
+/*
+ * These register definitions are for the 16C950
+ */
+#define UART_ASR	0x01	/* Additional Status Register */
+#define UART_RFL	0x03	/* Receiver FIFO level */
+#define UART_TFL 	0x04	/* Transmitter FIFO level */
+#define UART_ICR	0x05	/* Index Control Register */
+
+/* The 16950 ICR registers */
+#define UART_ACR	0x00	/* Additional Control Register */
+#define UART_CPR	0x01	/* Clock Prescalar Register */
+#define UART_TCR	0x02	/* Times Clock Register */
+#define UART_CKS	0x03	/* Clock Select Register */
+#define UART_TTL	0x04	/* Transmitter Interrupt Trigger Level */
+#define UART_RTL	0x05	/* Receiver Interrupt Trigger Level */
+#define UART_FCL	0x06	/* Flow Control Level Lower */
+#define UART_FCH	0x07	/* Flow Control Level Higher */
+#define UART_ID1	0x08	/* ID #1 */
+#define UART_ID2	0x09	/* ID #2 */
+#define UART_ID3	0x0A	/* ID #3 */
+#define UART_REV	0x0B	/* Revision */
+#define UART_CSR	0x0C	/* Channel Software Reset */
+#define UART_NMR	0x0D	/* Nine-bit Mode Register */
+#define UART_CTR	0xFF
+
+/*
+ * The 16C950 Additional Control Register
+ */
+#define UART_ACR_RXDIS	0x01	/* Receiver disable */
+#define UART_ACR_TXDIS	0x02	/* Transmitter disable */
+#define UART_ACR_DSRFC	0x04	/* DSR Flow Control */
+#define UART_ACR_TLENB	0x20	/* 950 trigger levels enable */
+#define UART_ACR_ICRRD	0x40	/* ICR Read enable */
+#define UART_ACR_ASREN	0x80	/* Additional status enable */
+
+
+
+/*
+ * These definitions are for the RSA-DV II/S card, from
+ *
+ * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
+ */
+
+#define UART_RSA_BASE (-8)
+
+#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
+
+#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
+#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
+#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
+#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
+
+#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
+
+#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
+#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
+#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
+#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
+#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
+
+#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
+
+#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
+#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
+#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
+#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
+#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
+#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
+#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
+#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
+
+#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
+
+#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
+
+#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
+
+#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
+
+/*
+ * The RSA DSV/II board has two fixed clock frequencies.  One is the
+ * standard rate, and the other is 8 times faster.
+ */
+#define SERIAL_RSA_BAUD_BASE (921600)
+#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
+
+/*
+ * Extra serial register definitions for the internal UARTs
+ * in TI OMAP processors.
+ */
+#define UART_OMAP_MDR1		0x08	/* Mode definition register */
+#define UART_OMAP_MDR2		0x09	/* Mode definition register 2 */
+#define UART_OMAP_SCR		0x10	/* Supplementary control register */
+#define UART_OMAP_SSR		0x11	/* Supplementary status register */
+#define UART_OMAP_EBLR		0x12	/* BOF length register */
+#define UART_OMAP_OSC_12M_SEL	0x13	/* OMAP1510 12MHz osc select */
+#define UART_OMAP_MVER		0x14	/* Module version register */
+#define UART_OMAP_SYSC		0x15	/* System configuration register */
+#define UART_OMAP_SYSS		0x16	/* System status register */
+#define UART_OMAP_WER		0x17	/* Wake-up enable register */
+
+/*
+ * These are the definitions for the MDR1 register
+ */
+#define UART_OMAP_MDR1_16X_MODE		0x00	/* UART 16x mode */
+#define UART_OMAP_MDR1_SIR_MODE		0x01	/* SIR mode */
+#define UART_OMAP_MDR1_16X_ABAUD_MODE	0x02	/* UART 16x auto-baud */
+#define UART_OMAP_MDR1_13X_MODE		0x03	/* UART 13x mode */
+#define UART_OMAP_MDR1_MIR_MODE		0x04	/* MIR mode */
+#define UART_OMAP_MDR1_FIR_MODE		0x05	/* FIR mode */
+#define UART_OMAP_MDR1_CIR_MODE		0x06	/* CIR mode */
+#define UART_OMAP_MDR1_DISABLE		0x07	/* Disable (default state) */
+
+/*
+ * These are definitions for the Exar XR17V35X and XR17(C|D)15X
+ */
+#define UART_EXAR_8XMODE	0x88	/* 8X sampling rate select */
+#define UART_EXAR_SLEEP		0x8b	/* Sleep mode */
+#define UART_EXAR_DVID		0x8d	/* Device identification */
+
+#define UART_EXAR_FCTR		0x08	/* Feature Control Register */
+#define UART_FCTR_EXAR_IRDA	0x08	/* IrDa data encode select */
+#define UART_FCTR_EXAR_485	0x10	/* Auto 485 half duplex dir ctl */
+#define UART_FCTR_EXAR_TRGA	0x00	/* FIFO trigger table A */
+#define UART_FCTR_EXAR_TRGB	0x60	/* FIFO trigger table B */
+#define UART_FCTR_EXAR_TRGC	0x80	/* FIFO trigger table C */
+#define UART_FCTR_EXAR_TRGD	0xc0	/* FIFO trigger table D programmable */
+
+#define UART_EXAR_TXTRG		0x0a	/* Tx FIFO trigger level write-only */
+#define UART_EXAR_RXTRG		0x0b	/* Rx FIFO trigger level write-only */
+
+#endif /* _LINUX_SERIAL_REG_H */
+
diff --git a/include/linux/sizes.h b/include/linux/sizes.h
new file mode 100644
index 0000000..fbde0bc
--- /dev/null
+++ b/include/linux/sizes.h
@@ -0,0 +1,51 @@
+/*
+ * include/linux/sizes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_SIZES_H__
+#define __LINUX_SIZES_H__
+
+#include <linux/const.h>
+
+#define SZ_1				0x00000001
+#define SZ_2				0x00000002
+#define SZ_4				0x00000004
+#define SZ_8				0x00000008
+#define SZ_16				0x00000010
+#define SZ_32				0x00000020
+#define SZ_64				0x00000040
+#define SZ_128				0x00000080
+#define SZ_256				0x00000100
+#define SZ_512				0x00000200
+
+#define SZ_1K				0x00000400
+#define SZ_2K				0x00000800
+#define SZ_4K				0x00001000
+#define SZ_8K				0x00002000
+#define SZ_16K				0x00004000
+#define SZ_32K				0x00008000
+#define SZ_64K				0x00010000
+#define SZ_128K				0x00020000
+#define SZ_256K				0x00040000
+#define SZ_512K				0x00080000
+
+#define SZ_1M				0x00100000
+#define SZ_2M				0x00200000
+#define SZ_4M				0x00400000
+#define SZ_8M				0x00800000
+#define SZ_16M				0x01000000
+#define SZ_32M				0x02000000
+#define SZ_64M				0x04000000
+#define SZ_128M				0x08000000
+#define SZ_256M				0x10000000
+#define SZ_512M				0x20000000
+
+#define SZ_1G				0x40000000
+#define SZ_2G				0x80000000
+
+#define SZ_4G				_AC(0x100000000, ULL)
+
+#endif /* __LINUX_SIZES_H__ */
diff --git a/include/linux/soc/ti/cppi5.h b/include/linux/soc/ti/cppi5.h
new file mode 100644
index 0000000..34038b3
--- /dev/null
+++ b/include/linux/soc/ti/cppi5.h
@@ -0,0 +1,995 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * CPPI5 descriptors interface
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ */
+
+#ifndef __TI_CPPI5_H__
+#define __TI_CPPI5_H__
+
+#include <hexdump.h>
+#include <linux/bitops.h>
+
+/**
+ * Descriptor header, present in all types of descriptors
+ */
+struct cppi5_desc_hdr_t {
+	u32 pkt_info0;	/* Packet info word 0 (n/a in Buffer desc) */
+	u32 pkt_info1;	/* Packet info word 1 (n/a in Buffer desc) */
+	u32 pkt_info2;	/* Packet info word 2 Buffer reclamation info */
+	u32 src_dst_tag; /* Packet info word 3 (n/a in Buffer desc) */
+} __packed;
+
+/**
+ * Host-mode packet and buffer descriptor definition
+ */
+struct cppi5_host_desc_t {
+	struct cppi5_desc_hdr_t hdr;
+	u64 next_desc;	/* w4/5: Linking word */
+	u64 buf_ptr;	/* w6/7: Buffer pointer */
+	u32 buf_info1;	/* w8: Buffer valid data length */
+	u32 org_buf_len; /* w9: Original buffer length */
+	u64 org_buf_ptr; /* w10/11: Original buffer pointer */
+	u32 epib[0];	/* Extended Packet Info Data (optional, 4 words) */
+	/*
+	 * Protocol Specific Data (optional, 0-128 bytes in multiples of 4),
+	 * and/or Other Software Data (0-N bytes, optional)
+	 */
+} __packed;
+
+#define CPPI5_DESC_MIN_ALIGN			(16U)
+
+#define CPPI5_INFO0_HDESC_EPIB_SIZE		(16U)
+#define CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE	(128U)
+
+#define CPPI5_INFO0_HDESC_TYPE_SHIFT		(30U)
+#define CPPI5_INFO0_HDESC_TYPE_MASK		GENMASK(31, 30)
+#define   CPPI5_INFO0_DESC_TYPE_VAL_HOST	(1U)
+#define   CPPI5_INFO0_DESC_TYPE_VAL_MONO	(2U)
+#define   CPPI5_INFO0_DESC_TYPE_VAL_TR		(3U)
+#define CPPI5_INFO0_HDESC_EPIB_PRESENT		BIT(29)
+/*
+ * Protocol Specific Words location:
+ * 0 - located in the descriptor,
+ * 1 = located in the SOP Buffer immediately prior to the data.
+ */
+#define CPPI5_INFO0_HDESC_PSINFO_LOCATION	BIT(28)
+#define CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT	(22U)
+#define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK	GENMASK(27, 22)
+#define CPPI5_INFO0_HDESC_PKTLEN_SHIFT		(0)
+#define CPPI5_INFO0_HDESC_PKTLEN_MASK		GENMASK(21, 0)
+
+#define CPPI5_INFO1_DESC_PKTERROR_SHIFT		(28U)
+#define CPPI5_INFO1_DESC_PKTERROR_MASK		GENMASK(31, 28)
+#define CPPI5_INFO1_HDESC_PSFLGS_SHIFT		(24U)
+#define CPPI5_INFO1_HDESC_PSFLGS_MASK		GENMASK(27, 24)
+#define CPPI5_INFO1_DESC_PKTID_SHIFT		(14U)
+#define CPPI5_INFO1_DESC_PKTID_MASK		GENMASK(23, 14)
+#define CPPI5_INFO1_DESC_FLOWID_SHIFT		(0)
+#define CPPI5_INFO1_DESC_FLOWID_MASK		GENMASK(13, 0)
+
+#define CPPI5_INFO2_HDESC_PKTTYPE_SHIFT		(27U)
+#define CPPI5_INFO2_HDESC_PKTTYPE_MASK		GENMASK(31, 27)
+/* Return Policy: 0 - Entire packet 1 - Each buffer */
+#define CPPI5_INFO2_HDESC_RETPOLICY		BIT(18)
+/*
+ * Early Return:
+ * 0 = desc pointers should be returned after all reads have been completed
+ * 1 = desc pointers should be returned immediately upon fetching
+ * the descriptor and beginning to transfer data.
+ */
+#define CPPI5_INFO2_HDESC_EARLYRET		BIT(17)
+/*
+ * Return Push Policy:
+ * 0 = Descriptor must be returned to tail of queue
+ * 1 = Descriptor must be returned to head of queue
+ */
+#define CPPI5_INFO2_DESC_RETPUSHPOLICY		BIT(16)
+#define CPPI5_INFO2_DESC_RETQ_SHIFT		(0)
+#define CPPI5_INFO2_DESC_RETQ_MASK		GENMASK(15, 0)
+
+#define CPPI5_INFO3_DESC_SRCTAG_SHIFT		(16U)
+#define CPPI5_INFO3_DESC_SRCTAG_MASK		GENMASK(31, 16)
+#define CPPI5_INFO3_DESC_DSTTAG_SHIFT		(0)
+#define CPPI5_INFO3_DESC_DSTTAG_MASK		GENMASK(15, 0)
+
+#define CPPI5_BUFINFO1_HDESC_DATA_LEN_SHIFT	(0)
+#define CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK	GENMASK(27, 0)
+
+#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_SHIFT	(0)
+#define CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK	GENMASK(27, 0)
+
+/*
+ * Host Packet Descriptor Extended Packet Info Block
+ */
+struct cppi5_desc_epib_t {
+	u32 timestamp;	/* w0: application specific timestamp */
+	u32 sw_info0;	/* w1: Software Info 0 */
+	u32 sw_info1;	/* w2: Software Info 1 */
+	u32 sw_info2;	/* w3: Software Info 2 */
+};
+
+/**
+ * Monolithic-mode packet descriptor
+ */
+struct cppi5_monolithic_desc_t {
+	struct cppi5_desc_hdr_t hdr;
+	u32 epib[0];	/* Extended Packet Info Data (optional, 4 words) */
+	/*
+	 * Protocol Specific Data (optional, 0-128 bytes in multiples of 4),
+	 *  and/or Other Software Data (0-N bytes, optional)
+	 */
+};
+
+#define CPPI5_INFO2_MDESC_DATA_OFFSET_SHIFT	(18U)
+#define CPPI5_INFO2_MDESC_DATA_OFFSET_MASK	GENMASK(26, 18)
+
+/*
+ * Reload Enable:
+ * 0 = Finish the packet and place the descriptor back on the return queue
+ * 1 = Vector to the Reload Index and resume processing
+ */
+#define CPPI5_INFO0_TRDESC_RLDCNT_SHIFT		(20U)
+#define CPPI5_INFO0_TRDESC_RLDCNT_MASK		GENMASK(28, 20)
+#define CPPI5_INFO0_TRDESC_RLDCNT_MAX		(0x1ff)
+#define CPPI5_INFO0_TRDESC_RLDCNT_INFINITE	CPPI5_INFO0_TRDESC_RLDCNT_MAX
+#define CPPI5_INFO0_TRDESC_RLDIDX_SHIFT		(14U)
+#define CPPI5_INFO0_TRDESC_RLDIDX_MASK		GENMASK(19, 14)
+#define CPPI5_INFO0_TRDESC_RLDIDX_MAX		(0x3f)
+#define CPPI5_INFO0_TRDESC_LASTIDX_SHIFT	(0)
+#define CPPI5_INFO0_TRDESC_LASTIDX_MASK		GENMASK(13, 0)
+
+#define CPPI5_INFO1_TRDESC_RECSIZE_SHIFT	(24U)
+#define CPPI5_INFO1_TRDESC_RECSIZE_MASK		GENMASK(26, 24)
+#define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_16B	(0)
+#define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_32B	(1U)
+#define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_64B	(2U)
+#define   CPPI5_INFO1_TRDESC_RECSIZE_VAL_128B	(3U)
+
+static inline void cppi5_desc_dump(void *desc, u32 size)
+{
+	print_hex_dump(KERN_ERR "dump udmap_desc: ", DUMP_PREFIX_NONE,
+		       32, 4, desc, size, false);
+}
+
+/**
+ * cppi5_desc_get_type - get descriptor type
+ * @desc_hdr: packet descriptor/TR header
+ *
+ * Returns descriptor type:
+ * CPPI5_INFO0_DESC_TYPE_VAL_HOST
+ * CPPI5_INFO0_DESC_TYPE_VAL_MONO
+ * CPPI5_INFO0_DESC_TYPE_VAL_TR
+ */
+static inline u32 cppi5_desc_get_type(struct cppi5_desc_hdr_t *desc_hdr)
+{
+	WARN_ON(!desc_hdr);
+
+	return (desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_TYPE_MASK) >>
+		CPPI5_INFO0_HDESC_TYPE_SHIFT;
+}
+
+/**
+ * cppi5_desc_get_errflags - get Error Flags from Desc
+ * @desc_hdr: packet/TR descriptor header
+ *
+ * Returns Error Flags from Packet/TR Descriptor
+ */
+static inline u32 cppi5_desc_get_errflags(struct cppi5_desc_hdr_t *desc_hdr)
+{
+	WARN_ON(!desc_hdr);
+
+	return (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTERROR_MASK) >>
+		CPPI5_INFO1_DESC_PKTERROR_SHIFT;
+}
+
+/**
+ * cppi5_desc_get_pktids - get Packet and Flow ids from Desc
+ * @desc_hdr: packet/TR descriptor header
+ * @pkt_id: Packet ID
+ * @flow_id: Flow ID
+ *
+ * Returns Packet and Flow ids from packet/TR descriptor
+ */
+static inline void cppi5_desc_get_pktids(struct cppi5_desc_hdr_t *desc_hdr,
+					 u32 *pkt_id, u32 *flow_id)
+{
+	WARN_ON(!desc_hdr);
+
+	*pkt_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTID_MASK) >>
+		   CPPI5_INFO1_DESC_PKTID_SHIFT;
+	*flow_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_FLOWID_MASK) >>
+		    CPPI5_INFO1_DESC_FLOWID_SHIFT;
+}
+
+/**
+ * cppi5_desc_set_pktids - set Packet and Flow ids in Desc
+ * @desc_hdr: packet/TR descriptor header
+ * @pkt_id: Packet ID
+ * @flow_id: Flow ID
+ */
+static inline void cppi5_desc_set_pktids(struct cppi5_desc_hdr_t *desc_hdr,
+					 u32 pkt_id, u32 flow_id)
+{
+	WARN_ON(!desc_hdr);
+
+	desc_hdr->pkt_info1 |= (pkt_id << CPPI5_INFO1_DESC_PKTID_SHIFT) &
+				CPPI5_INFO1_DESC_PKTID_MASK;
+	desc_hdr->pkt_info1 |= (flow_id << CPPI5_INFO1_DESC_FLOWID_SHIFT) &
+				CPPI5_INFO1_DESC_FLOWID_MASK;
+}
+
+/**
+ * cppi5_desc_set_retpolicy - set Packet Return Policy in Desc
+ * @desc_hdr: packet/TR descriptor header
+ * @flags: fags, supported values
+ *  CPPI5_INFO2_HDESC_RETPOLICY
+ *  CPPI5_INFO2_HDESC_EARLYRET
+ *  CPPI5_INFO2_DESC_RETPUSHPOLICY
+ * @return_ring_id: Packet Return Queue/Ring id, value 0xFFFF reserved
+ */
+static inline void cppi5_desc_set_retpolicy(struct cppi5_desc_hdr_t *desc_hdr,
+					    u32 flags, u32 return_ring_id)
+{
+	WARN_ON(!desc_hdr);
+
+	desc_hdr->pkt_info2 |= flags;
+	desc_hdr->pkt_info2 |= return_ring_id & CPPI5_INFO2_DESC_RETQ_MASK;
+}
+
+/**
+ * cppi5_desc_get_tags_ids - get Packet Src/Dst Tags from Desc
+ * @desc_hdr: packet/TR descriptor header
+ * @src_tag_id: Source Tag
+ * @dst_tag_id: Dest Tag
+ *
+ * Returns Packet Src/Dst Tags from packet/TR descriptor
+ */
+static inline void cppi5_desc_get_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
+					   u32 *src_tag_id, u32 *dst_tag_id)
+{
+	WARN_ON(!desc_hdr);
+
+	if (src_tag_id)
+		*src_tag_id = (desc_hdr->src_dst_tag &
+			      CPPI5_INFO3_DESC_SRCTAG_MASK) >>
+			      CPPI5_INFO3_DESC_SRCTAG_SHIFT;
+	if (dst_tag_id)
+		*dst_tag_id = desc_hdr->src_dst_tag &
+			      CPPI5_INFO3_DESC_DSTTAG_MASK;
+}
+
+/**
+ * cppi5_desc_set_tags_ids - set Packet Src/Dst Tags in HDesc
+ * @desc_hdr: packet/TR descriptor header
+ * @src_tag_id: Source Tag
+ * @dst_tag_id: Dest Tag
+ *
+ * Returns Packet Src/Dst Tags from packet/TR descriptor
+ */
+static inline void cppi5_desc_set_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
+					   u32 src_tag_id, u32 dst_tag_id)
+{
+	WARN_ON(!desc_hdr);
+
+	desc_hdr->src_dst_tag = (src_tag_id << CPPI5_INFO3_DESC_SRCTAG_SHIFT) &
+				CPPI5_INFO3_DESC_SRCTAG_MASK;
+	desc_hdr->src_dst_tag |= dst_tag_id & CPPI5_INFO3_DESC_DSTTAG_MASK;
+}
+
+/**
+ * cppi5_hdesc_calc_size - Calculate Host Packet Descriptor size
+ * @epib: is EPIB present
+ * @psdata_size: PSDATA size
+ * @sw_data_size: SWDATA size
+ *
+ * Returns required Host Packet Descriptor size
+ * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
+ */
+static inline u32 cppi5_hdesc_calc_size(bool epib, u32 psdata_size,
+					u32 sw_data_size)
+{
+	u32 desc_size;
+
+	if (psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE)
+		return 0;
+	//TODO_GS: align
+	desc_size = sizeof(struct cppi5_host_desc_t) + psdata_size +
+		    sw_data_size;
+
+	if (epib)
+		desc_size += CPPI5_INFO0_HDESC_EPIB_SIZE;
+
+	return ALIGN(desc_size, CPPI5_DESC_MIN_ALIGN);
+}
+
+/**
+ * cppi5_hdesc_init - Init Host Packet Descriptor size
+ * @desc: Host packet descriptor
+ * @flags: supported values
+ *	CPPI5_INFO0_HDESC_EPIB_PRESENT
+ *	CPPI5_INFO0_HDESC_PSINFO_LOCATION
+ * @psdata_size: PSDATA size
+ *
+ * Returns required Host Packet Descriptor size
+ * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
+ */
+static inline void cppi5_hdesc_init(struct cppi5_host_desc_t *desc, u32 flags,
+				    u32 psdata_size)
+{
+	WARN_ON(!desc);
+	WARN_ON(psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE);
+	WARN_ON(flags & ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
+			  CPPI5_INFO0_HDESC_PSINFO_LOCATION));
+
+	desc->hdr.pkt_info0 = (CPPI5_INFO0_DESC_TYPE_VAL_HOST <<
+			       CPPI5_INFO0_HDESC_TYPE_SHIFT) | (flags);
+	desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
+				CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
+				CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
+	desc->next_desc = 0;
+}
+
+/**
+ * cppi5_hdesc_update_flags - Replace descriptor flags
+ * @desc: Host packet descriptor
+ * @flags: supported values
+ *	CPPI5_INFO0_HDESC_EPIB_PRESENT
+ *	CPPI5_INFO0_HDESC_PSINFO_LOCATION
+ */
+static inline void cppi5_hdesc_update_flags(struct cppi5_host_desc_t *desc,
+					    u32 flags)
+{
+	WARN_ON(!desc);
+	WARN_ON(flags & ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
+			  CPPI5_INFO0_HDESC_PSINFO_LOCATION));
+
+	desc->hdr.pkt_info0 &= ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
+				 CPPI5_INFO0_HDESC_PSINFO_LOCATION);
+	desc->hdr.pkt_info0 |= flags;
+}
+
+/**
+ * cppi5_hdesc_update_psdata_size - Replace PSdata size
+ * @desc: Host packet descriptor
+ * @psdata_size: PSDATA size
+ */
+static inline void cppi5_hdesc_update_psdata_size(
+				struct cppi5_host_desc_t *desc, u32 psdata_size)
+{
+	WARN_ON(!desc);
+	WARN_ON(psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE);
+
+	desc->hdr.pkt_info0 &= ~CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
+	desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
+				CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
+				CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
+}
+
+/**
+ * cppi5_hdesc_get_psdata_size - get PSdata size in bytes
+ * @desc: Host packet descriptor
+ */
+static inline u32 cppi5_hdesc_get_psdata_size(struct cppi5_host_desc_t *desc)
+{
+	u32 psdata_size = 0;
+
+	WARN_ON(!desc);
+
+	if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
+		psdata_size = (desc->hdr.pkt_info0 &
+			       CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
+			       CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
+
+	return (psdata_size << 2);
+}
+
+/**
+ * cppi5_hdesc_get_pktlen - get Packet Length from HDesc
+ * @desc: Host packet descriptor
+ *
+ * Returns Packet Length from Host Packet Descriptor
+ */
+static inline u32 cppi5_hdesc_get_pktlen(struct cppi5_host_desc_t *desc)
+{
+	WARN_ON(!desc);
+
+	return (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PKTLEN_MASK);
+}
+
+/**
+ * cppi5_hdesc_set_pktlen - set Packet Length in HDesc
+ * @desc: Host packet descriptor
+ */
+static inline void cppi5_hdesc_set_pktlen(struct cppi5_host_desc_t *desc,
+					  u32 pkt_len)
+{
+	WARN_ON(!desc);
+
+	desc->hdr.pkt_info0 |= (pkt_len & CPPI5_INFO0_HDESC_PKTLEN_MASK);
+}
+
+/**
+ * cppi5_hdesc_get_psflags - get Protocol Specific Flags from HDesc
+ * @desc: Host packet descriptor
+ *
+ * Returns Protocol Specific Flags from Host Packet Descriptor
+ */
+static inline u32 cppi5_hdesc_get_psflags(struct cppi5_host_desc_t *desc)
+{
+	WARN_ON(!desc);
+
+	return (desc->hdr.pkt_info1 & CPPI5_INFO1_HDESC_PSFLGS_MASK) >>
+		CPPI5_INFO1_HDESC_PSFLGS_SHIFT;
+}
+
+/**
+ * cppi5_hdesc_set_psflags - set Protocol Specific Flags in HDesc
+ * @desc: Host packet descriptor
+ */
+static inline void cppi5_hdesc_set_psflags(struct cppi5_host_desc_t *desc,
+					   u32 ps_flags)
+{
+	WARN_ON(!desc);
+
+	desc->hdr.pkt_info1 |= (ps_flags <<
+				CPPI5_INFO1_HDESC_PSFLGS_SHIFT) &
+				CPPI5_INFO1_HDESC_PSFLGS_MASK;
+}
+
+/**
+ * cppi5_hdesc_get_errflags - get Packet Type from HDesc
+ * @desc: Host packet descriptor
+ */
+static inline u32 cppi5_hdesc_get_pkttype(struct cppi5_host_desc_t *desc)
+{
+	WARN_ON(!desc);
+
+	return (desc->hdr.pkt_info2 & CPPI5_INFO2_HDESC_PKTTYPE_MASK) >>
+		CPPI5_INFO2_HDESC_PKTTYPE_SHIFT;
+}
+
+/**
+ * cppi5_hdesc_get_errflags - set Packet Type in HDesc
+ * @desc: Host packet descriptor
+ * @pkt_type: Packet Type
+ */
+static inline void cppi5_hdesc_set_pkttype(struct cppi5_host_desc_t *desc,
+					   u32 pkt_type)
+{
+	WARN_ON(!desc);
+	desc->hdr.pkt_info2 |=
+			(pkt_type << CPPI5_INFO2_HDESC_PKTTYPE_SHIFT) &
+			 CPPI5_INFO2_HDESC_PKTTYPE_MASK;
+}
+
+/**
+ * cppi5_hdesc_attach_buf - attach buffer to HDesc
+ * @desc: Host packet descriptor
+ * @buf: Buffer physical address
+ * @buf_data_len: Buffer length
+ * @obuf: Original Buffer physical address
+ * @obuf_len: Original Buffer length
+ *
+ * Attaches buffer to Host Packet Descriptor
+ */
+static inline void cppi5_hdesc_attach_buf(struct cppi5_host_desc_t *desc,
+					  dma_addr_t buf, u32 buf_data_len,
+					  dma_addr_t obuf, u32 obuf_len)
+{
+	WARN_ON(!desc);
+	WARN_ON(!buf && !obuf);
+
+	desc->buf_ptr = buf;
+	desc->buf_info1 = buf_data_len & CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK;
+	desc->org_buf_ptr = obuf;
+	desc->org_buf_len = obuf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
+}
+
+static inline void cppi5_hdesc_get_obuf(struct cppi5_host_desc_t *desc,
+					dma_addr_t *obuf, u32 *obuf_len)
+{
+	WARN_ON(!desc);
+	WARN_ON(!obuf);
+	WARN_ON(!obuf_len);
+
+	*obuf = desc->org_buf_ptr;
+	*obuf_len = desc->org_buf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
+}
+
+static inline void cppi5_hdesc_reset_to_original(struct cppi5_host_desc_t *desc)
+{
+	WARN_ON(!desc);
+
+	desc->buf_ptr = desc->org_buf_ptr;
+	desc->buf_info1 = desc->org_buf_len;
+}
+
+/**
+ * cppi5_hdesc_link_hbdesc - link Host Buffer Descriptor to HDesc
+ * @desc: Host Packet Descriptor
+ * @buf_desc: Host Buffer Descriptor physical address
+ *
+ * add and link Host Buffer Descriptor to HDesc
+ */
+static inline void cppi5_hdesc_link_hbdesc(struct cppi5_host_desc_t *desc,
+					   dma_addr_t hbuf_desc)
+{
+	WARN_ON(!desc);
+	WARN_ON(!hbuf_desc);
+
+	desc->next_desc = hbuf_desc;
+}
+
+static inline dma_addr_t cppi5_hdesc_get_next_hbdesc(
+				struct cppi5_host_desc_t *desc)
+{
+	WARN_ON(!desc);
+
+	return (dma_addr_t)desc->next_desc;
+}
+
+static inline void cppi5_hdesc_reset_hbdesc(struct cppi5_host_desc_t *desc)
+{
+	WARN_ON(!desc);
+
+	desc->hdr = (struct cppi5_desc_hdr_t) { 0 };
+	desc->next_desc = 0;
+}
+
+/**
+ * cppi5_hdesc_epib_present -  check if EPIB present
+ * @desc_hdr: packet descriptor/TR header
+ *
+ * Returns true if EPIB present in the packet
+ */
+static inline bool cppi5_hdesc_epib_present(struct cppi5_desc_hdr_t *desc_hdr)
+{
+	WARN_ON(!desc_hdr);
+	return !!(desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_EPIB_PRESENT);
+}
+
+/**
+ * cppi5_hdesc_get_psdata -  Get pointer on PSDATA
+ * @desc: Host packet descriptor
+ *
+ * Returns pointer on PSDATA in HDesc.
+ * NULL - if ps_data placed at the start of data buffer.
+ */
+static inline void *cppi5_hdesc_get_psdata(struct cppi5_host_desc_t *desc)
+{
+	u32 psdata_size;
+	void *psdata;
+
+	WARN_ON(!desc);
+
+	if (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION)
+		return NULL;
+
+	psdata_size = (desc->hdr.pkt_info0 &
+		       CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
+		       CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
+
+	if (!psdata_size)
+		return NULL;
+
+	psdata = &desc->epib;
+
+	if (cppi5_hdesc_epib_present(&desc->hdr))
+		psdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
+
+	return psdata;
+}
+
+static inline u32 *cppi5_hdesc_get_psdata32(struct cppi5_host_desc_t *desc)
+{
+	return (u32 *)cppi5_hdesc_get_psdata(desc);
+}
+
+/**
+ * cppi5_hdesc_get_swdata -  Get pointer on swdata
+ * @desc: Host packet descriptor
+ *
+ * Returns pointer on SWDATA in HDesc.
+ * NOTE. It's caller responsibility to be sure hdesc actually has swdata.
+ */
+static inline void *cppi5_hdesc_get_swdata(struct cppi5_host_desc_t *desc)
+{
+	u32 psdata_size = 0;
+	void *swdata;
+
+	WARN_ON(!desc);
+
+	if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
+		psdata_size = (desc->hdr.pkt_info0 &
+			       CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
+			       CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
+
+	swdata = &desc->epib;
+
+	if (cppi5_hdesc_epib_present(&desc->hdr))
+		swdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
+
+	swdata += (psdata_size << 2);
+
+	return swdata;
+}
+
+/* ================================== TR ================================== */
+
+#define CPPI5_TR_TYPE_SHIFT			(0U)
+#define CPPI5_TR_TYPE_MASK			GENMASK(3, 0)
+#define CPPI5_TR_STATIC				BIT(4)
+#define CPPI5_TR_WAIT				BIT(5)
+#define CPPI5_TR_EVENT_SIZE_SHIFT		(6U)
+#define CPPI5_TR_EVENT_SIZE_MASK		GENMASK(7, 6)
+#define CPPI5_TR_TRIGGER0_SHIFT			(8U)
+#define CPPI5_TR_TRIGGER0_MASK			GENMASK(9, 8)
+#define CPPI5_TR_TRIGGER0_TYPE_SHIFT		(10U)
+#define CPPI5_TR_TRIGGER0_TYPE_MASK		GENMASK(11, 10)
+#define CPPI5_TR_TRIGGER1_SHIFT			(12U)
+#define CPPI5_TR_TRIGGER1_MASK			GENMASK(13, 12)
+#define CPPI5_TR_TRIGGER1_TYPE_SHIFT		(14U)
+#define CPPI5_TR_TRIGGER1_TYPE_MASK		GENMASK(15, 14)
+#define CPPI5_TR_CMD_ID_SHIFT			(16U)
+#define CPPI5_TR_CMD_ID_MASK			GENMASK(23, 16)
+#define CPPI5_TR_CSF_FLAGS_SHIFT		(24U)
+#define CPPI5_TR_CSF_FLAGS_MASK			GENMASK(31, 24)
+#define   CPPI5_TR_CSF_SA_INDIRECT		BIT(0)
+#define   CPPI5_TR_CSF_DA_INDIRECT		BIT(1)
+#define   CPPI5_TR_CSF_SUPR_EVT			BIT(2)
+#define   CPPI5_TR_CSF_EOL_ADV_SHIFT		(4U)
+#define   CPPI5_TR_CSF_EOL_ADV_MASK		GENMASK(6, 4)
+#define   CPPI5_TR_CSF_EOP			BIT(7)
+
+/* Udmap TR flags Type field specifies the type of TR. */
+enum cppi5_tr_types {
+	/* type0: One dimensional data move */
+	CPPI5_TR_TYPE0 = 0,
+	/* type1: Two dimensional data move */
+	CPPI5_TR_TYPE1,
+	/* type2: Three dimensional data move */
+	CPPI5_TR_TYPE2,
+	/* type3: Four dimensional data move */
+	CPPI5_TR_TYPE3,
+	/* type4: Four dimensional data move with data formatting */
+	CPPI5_TR_TYPE4,
+	/* type5: Four dimensional Cache Warm */
+	CPPI5_TR_TYPE5,
+	/* type6-7: Reserved */
+	/* type8: Four Dimensional Block Move */
+	CPPI5_TR_TYPE8 = 8,
+	/* type9: Four Dimensional Block Move with Repacking */
+	CPPI5_TR_TYPE9,
+	/* type10: Two Dimensional Block Move */
+	CPPI5_TR_TYPE10,
+	/* type11: Two Dimensional Block Move with Repacking */
+	CPPI5_TR_TYPE11,
+	/* type12-14: Reserved */
+	/* type15 Four Dimensional Block Move with Repacking and Indirection */
+	CPPI5_TR_TYPE15 = 15,
+	CPPI5_TR_TYPE_MAX
+};
+
+/*
+ * Udmap TR Flags EVENT_SIZE field specifies when an event is generated
+ * for each TR.
+ */
+enum cppi5_tr_event_size {
+	/* When TR is complete and all status for the TR has been received */
+	CPPI5_TR_EVENT_SIZE_COMPLETION,
+	/*
+	 * Type 0: when the last data transaction is sent for the TR;
+	 * Type 1-11: when ICNT1 is decremented
+	 */
+	CPPI5_TR_EVENT_SIZE_ICNT1_DEC,
+	/*
+	 * Type 0-1,10-11: when the last data transaction is sent for the TR;
+	 * All other types: when ICNT2 is decremented
+	 */
+	CPPI5_TR_EVENT_SIZE_ICNT2_DEC,
+	/*
+	 * Type 0-2,10-11: when the last data transaction is sent for the TR;
+	 * All other types: when ICNT3 is decremented
+	 */
+	CPPI5_TR_EVENT_SIZE_ICNT3_DEC,
+	CPPI5_TR_EVENT_SIZE_MAX
+};
+
+/*
+ * Udmap TR Flags TRIGGERx field specifies the type of trigger used to
+ * enable the TR to transfer data as specified by TRIGGERx_TYPE field.
+ */
+enum cppi5_tr_trigger {
+	CPPI5_TR_TRIGGER_NONE,		/* No Trigger */
+	CPPI5_TR_TRIGGER_GLOBAL0,		/* Global Trigger 0 */
+	CPPI5_TR_TRIGGER_GLOBAL1,		/* Global Trigger 1 */
+	CPPI5_TR_TRIGGER_LOCAL_EVENT,	/* Local Event */
+	CPPI5_TR_TRIGGER_MAX
+};
+
+/*
+ * Udmap TR Flags TRIGGERx_TYPE field specifies the type of data transfer
+ * that will be enabled by receiving a trigger as specified by TRIGGERx.
+ */
+enum cppi5_tr_trigger_type {
+	/* The second inner most loop (ICNT1) will be decremented by 1 */
+	CPPI5_TR_TRIGGER_TYPE_ICNT1_DEC,
+	/* The third inner most loop (ICNT2) will be decremented by 1 */
+	CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC,
+	/* The outer most loop (ICNT3) will be decremented by 1 */
+	CPPI5_TR_TRIGGER_TYPE_ICNT3_DEC,
+	/* The entire TR will be allowed to complete */
+	CPPI5_TR_TRIGGER_TYPE_ALL,
+	CPPI5_TR_TRIGGER_TYPE_MAX
+};
+
+typedef u32 cppi5_tr_flags_t;
+
+/* Type 0 (One dimensional data move) TR (16 byte) */
+struct cppi5_tr_type0_t {
+	cppi5_tr_flags_t flags;
+	u16 icnt0;
+	u16 unused;
+	u64 addr;
+} __aligned(16) __packed;
+
+/* Type 1 (Two dimensional data move) TR (32 byte) */
+struct cppi5_tr_type1_t {
+	cppi5_tr_flags_t flags;
+	u16 icnt0;
+	u16 icnt1;
+	u64 addr;
+	s32 dim1;
+} __aligned(32) __packed;
+
+/* Type 2 (Three dimensional data move) TR (32 byte) */
+struct cppi5_tr_type2_t {
+	cppi5_tr_flags_t flags;
+	u16 icnt0;
+	u16 icnt1;
+	u64 addr;
+	s32 dim1;
+	u16 icnt2;
+	u16 unused;
+	s32 dim2;
+} __aligned(32) __packed;
+
+/* Type 3 (Four dimensional data move) TR (32 byte) */
+struct cppi5_tr_type3_t {
+	cppi5_tr_flags_t flags;
+	u16 icnt0;
+	u16 icnt1;
+	u64 addr;
+	s32 dim1;
+	u16 icnt2;
+	u16 icnt3;
+	s32 dim2;
+	s32 dim3;
+} __aligned(32) __packed;
+
+/*
+ * Type 15 (Four Dimensional Block Copy with Repacking and
+ * Indirection Support) TR (64 byte).
+ */
+struct cppi5_tr_type15_t {
+	cppi5_tr_flags_t flags;
+	u16 icnt0;
+	u16 icnt1;
+	u64 addr;
+	s32 dim1;
+	u16 icnt2;
+	u16 icnt3;
+	s32 dim2;
+	s32 dim3;
+	u32 _reserved;
+	s32 ddim1;
+	u64 daddr;
+	s32 ddim2;
+	s32 ddim3;
+	u16 dicnt0;
+	u16 dicnt1;
+	u16 dicnt2;
+	u16 dicnt3;
+} __aligned(64) __packed;
+
+struct cppi5_tr_resp_t {
+	u8 status;
+	u8 reserved;
+	u8 cmd_id;
+	u8 flags;
+} __packed;
+
+#define CPPI5_TR_RESPONSE_STATUS_TYPE_SHIFT	(0U)
+#define CPPI5_TR_RESPONSE_STATUS_TYPE_MASK	GENMASK(3, 0)
+#define CPPI5_TR_RESPONSE_STATUS_INFO_SHIFT	(4U)
+#define CPPI5_TR_RESPONSE_STATUS_INFO_MASK	GENMASK(7, 4)
+#define CPPI5_TR_RESPONSE_CMDID_SHIFT		(16U)
+#define CPPI5_TR_RESPONSE_CMDID_MASK		GENMASK(23, 16)
+#define CPPI5_TR_RESPONSE_CFG_SPECIFIC_SHIFT	(24U)
+#define CPPI5_TR_RESPONSE_CFG_SPECIFIC_MASK	GENMASK(31, 24)
+
+/*
+ * Udmap TR Response Status Type field is used to determine
+ * what type of status is being returned.
+ */
+enum cppi5_tr_resp_status_type {
+	CPPI5_TR_RESPONSE_STATUS_COMPLETE,		/* None */
+	CPPI5_TR_RESPONSE_STATUS_TRANSFER_ERR,		/* Transfer Error */
+	CPPI5_TR_RESPONSE_STATUS_ABORTED_ERR,		/* Aborted Error */
+	CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR,	/* Submission Error */
+	CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR,	/* Unsup. Feature */
+	CPPI5_TR_RESPONSE_STATUS_MAX
+};
+
+/*
+ * Udmap TR Response Status field values which corresponds
+ * CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR
+ */
+enum cppi5_tr_resp_status_submission {
+	/* ICNT0 was 0 */
+	CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ICNT0,
+	/* Channel FIFO was full when TR received */
+	CPPI5_TR_RESPONSE_STATUS_SUBMISSION_FIFO_FULL,
+	/* Channel is not owned by the submitter */
+	CPPI5_TR_RESPONSE_STATUS_SUBMISSION_OWN,
+	CPPI5_TR_RESPONSE_STATUS_SUBMISSION_MAX
+};
+
+/*
+ * Udmap TR Response Status field values which corresponds
+ * CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR
+ */
+enum cppi5_tr_resp_status_unsupported {
+	/* TR Type not supported */
+	CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_TR_TYPE,
+	/* STATIC not supported */
+	CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_STATIC,
+	/* EOL not supported */
+	CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_EOL,
+	/* CONFIGURATION SPECIFIC not supported */
+	CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_CFG_SPECIFIC,
+	/* AMODE not supported */
+	CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE,
+	/* ELTYPE not supported */
+	CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ELTYPE,
+	/* DFMT not supported */
+	CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_DFMT,
+	/* SECTR not supported */
+	CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_SECTR,
+	/* AMODE SPECIFIC field not supported */
+	CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE_SPECIFIC,
+	CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_MAX
+};
+
+/**
+ * cppi5_trdesc_calc_size - Calculate TR Descriptor size
+ * @tr_count: number of TR records
+ * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
+ *
+ * Returns required TR Descriptor size
+ */
+static inline size_t cppi5_trdesc_calc_size(u32 tr_count, u32 tr_size)
+{
+	/*
+	 * The Size of a TR descriptor is:
+	 * 1 x tr_size : the first 16 bytes is used by the packet info block +
+	 * tr_count x tr_size : Transfer Request Records +
+	 * tr_count x sizeof(struct cppi5_tr_resp_t) : Transfer Response Records
+	 */
+	return tr_size * (tr_count + 1) +
+		sizeof(struct cppi5_tr_resp_t) * tr_count;
+}
+
+/**
+ * cppi5_trdesc_init - Init TR Descriptor
+ * @desc: TR Descriptor
+ * @tr_count: number of TR records
+ * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
+ * @reload_idx: Absolute index to jump to on the 2nd and following passes
+ *		through the TR packet.
+ * @reload_count: Number of times to jump from last entry to reload_idx. 0x1ff
+ *		  indicates infinite looping.
+ *
+ * Init TR Descriptor
+ */
+static inline void cppi5_trdesc_init(struct cppi5_desc_hdr_t *desc_hdr,
+				     u32 tr_count, u32 tr_size, u32 reload_idx,
+				     u32 reload_count)
+{
+	WARN_ON(!desc_hdr);
+	WARN_ON(tr_count & ~CPPI5_INFO0_TRDESC_LASTIDX_MASK);
+	WARN_ON(reload_idx > CPPI5_INFO0_TRDESC_RLDIDX_MAX);
+	WARN_ON(reload_count > CPPI5_INFO0_TRDESC_RLDCNT_MAX);
+
+	desc_hdr->pkt_info0 = CPPI5_INFO0_DESC_TYPE_VAL_TR <<
+			      CPPI5_INFO0_HDESC_TYPE_SHIFT;
+	desc_hdr->pkt_info0 |= (reload_count << CPPI5_INFO0_TRDESC_RLDCNT_SHIFT) &
+			       CPPI5_INFO0_TRDESC_RLDCNT_MASK;
+	desc_hdr->pkt_info0 |= (reload_idx << CPPI5_INFO0_TRDESC_RLDIDX_SHIFT) &
+			       CPPI5_INFO0_TRDESC_RLDIDX_MASK;
+	desc_hdr->pkt_info0 |= (tr_count - 1) & CPPI5_INFO0_TRDESC_LASTIDX_MASK;
+
+	desc_hdr->pkt_info1 |= ((ffs(tr_size >> 4) - 1) <<
+				CPPI5_INFO1_TRDESC_RECSIZE_SHIFT) &
+				CPPI5_INFO1_TRDESC_RECSIZE_MASK;
+}
+
+/**
+ * cppi5_tr_init - Init TR record
+ * @flags: Pointer to the TR's flags
+ * @type: TR type
+ * @static_tr: TR is static
+ * @wait: Wait for TR completion before allow the next TR to start
+ * @event_size: output event generation cfg
+ * @cmd_id: TR identifier (application specifics)
+ *
+ * Init TR record
+ */
+static inline void cppi5_tr_init(cppi5_tr_flags_t *flags,
+				 enum cppi5_tr_types type, bool static_tr,
+				 bool wait, enum cppi5_tr_event_size event_size,
+				 u32 cmd_id)
+{
+	WARN_ON(!flags);
+
+	*flags = type;
+	*flags |= (event_size << CPPI5_TR_EVENT_SIZE_SHIFT) &
+		  CPPI5_TR_EVENT_SIZE_MASK;
+
+	*flags |= (cmd_id << CPPI5_TR_CMD_ID_SHIFT) &
+		  CPPI5_TR_CMD_ID_MASK;
+
+	if (static_tr && (type == CPPI5_TR_TYPE8 || type == CPPI5_TR_TYPE9))
+		*flags |= CPPI5_TR_STATIC;
+
+	if (wait)
+		*flags |= CPPI5_TR_WAIT;
+}
+
+/**
+ * cppi5_tr_set_trigger - Configure trigger0/1 and trigger0/1_type
+ * @flags: Pointer to the TR's flags
+ * @trigger0: trigger0 selection
+ * @trigger0_type: type of data transfer that will be enabled by trigger0
+ * @trigger1: trigger1 selection
+ * @trigger1_type: type of data transfer that will be enabled by trigger1
+ *
+ * Configure the triggers for the TR
+ */
+static inline void cppi5_tr_set_trigger(cppi5_tr_flags_t *flags,
+				enum cppi5_tr_trigger trigger0,
+				enum cppi5_tr_trigger_type trigger0_type,
+				enum cppi5_tr_trigger trigger1,
+				enum cppi5_tr_trigger_type trigger1_type)
+{
+	WARN_ON(!flags);
+
+	*flags |= (trigger0 << CPPI5_TR_TRIGGER0_SHIFT) &
+		  CPPI5_TR_TRIGGER0_MASK;
+	*flags |= (trigger0_type << CPPI5_TR_TRIGGER0_TYPE_SHIFT) &
+		  CPPI5_TR_TRIGGER0_TYPE_MASK;
+
+	*flags |= (trigger1 << CPPI5_TR_TRIGGER1_SHIFT) &
+		  CPPI5_TR_TRIGGER1_MASK;
+	*flags |= (trigger1_type << CPPI5_TR_TRIGGER1_TYPE_SHIFT) &
+		  CPPI5_TR_TRIGGER1_TYPE_MASK;
+}
+
+/**
+ * cppi5_tr_cflag_set - Update the Configuration specific flags
+ * @flags: Pointer to the TR's flags
+ * @csf: Configuration specific flags
+ *
+ * Set a bit in Configuration Specific Flags section of the TR flags.
+ */
+static inline void cppi5_tr_csf_set(cppi5_tr_flags_t *flags, u32 csf)
+{
+	WARN_ON(!flags);
+
+	*flags |= (csf << CPPI5_TR_CSF_FLAGS_SHIFT) &
+		  CPPI5_TR_CSF_FLAGS_MASK;
+}
+
+#endif /* __TI_CPPI5_H__ */
diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h
new file mode 100644
index 0000000..487dfe9
--- /dev/null
+++ b/include/linux/soc/ti/k3-navss-ringacc.h
@@ -0,0 +1,236 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * TI K3 AM65x NAVSS Ring accelerator Manager (RA) subsystem driver
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ */
+
+#ifndef __SOC_TI_K3_NAVSS_RINGACC_API_H_
+#define __SOC_TI_K3_NAVSS_RINGACC_API_H_
+
+#include <dm/ofnode.h>
+
+/**
+ * enum k3_nav_ring_mode - &struct k3_nav_ring_cfg mode
+ *
+ * RA ring operational modes
+ *
+ * @K3_NAV_RINGACC_RING_MODE_RING: Exposed Ring mode for SW direct access
+ * @K3_NAV_RINGACC_RING_MODE_MESSAGE: Messaging mode. Messaging mode requires
+ *	that all accesses to the queue must go through this IP so that all
+ *	accesses to the memory are controlled and ordered. This IP then
+ *	controls the entire state of the queue, and SW has no directly control,
+ *	such as through doorbells and cannot access the storage memory directly.
+ *	This is particularly useful when more than one SW or HW entity can be
+ *	the producer and/or consumer at the same time
+ * @K3_NAV_RINGACC_RING_MODE_CREDENTIALS: Credentials mode is message mode plus
+ *	stores credentials with each message, requiring the element size to be
+ *	doubled to fit the credentials. Any exposed memory should be protected
+ *	by a firewall from unwanted access
+ * @K3_NAV_RINGACC_RING_MODE_QM:  Queue manager mode. This takes the credentials
+ *	mode and adds packet length per element, along with additional read only
+ *	fields for element count and accumulated queue length. The QM mode only
+ *	operates with an 8 byte element size (any other element size is
+ *	illegal), and like in credentials mode each operation uses 2 element
+ *	slots to store the credentials and length fields
+ */
+enum k3_nav_ring_mode {
+	K3_NAV_RINGACC_RING_MODE_RING = 0,
+	K3_NAV_RINGACC_RING_MODE_MESSAGE,
+	K3_NAV_RINGACC_RING_MODE_CREDENTIALS,
+	K3_NAV_RINGACC_RING_MODE_QM,
+	k3_NAV_RINGACC_RING_MODE_INVALID
+};
+
+/**
+ * enum k3_nav_ring_size - &struct k3_nav_ring_cfg elm_size
+ *
+ * RA ring element's sizes in bytes.
+ */
+enum k3_nav_ring_size {
+	K3_NAV_RINGACC_RING_ELSIZE_4 = 0,
+	K3_NAV_RINGACC_RING_ELSIZE_8,
+	K3_NAV_RINGACC_RING_ELSIZE_16,
+	K3_NAV_RINGACC_RING_ELSIZE_32,
+	K3_NAV_RINGACC_RING_ELSIZE_64,
+	K3_NAV_RINGACC_RING_ELSIZE_128,
+	K3_NAV_RINGACC_RING_ELSIZE_256,
+	K3_NAV_RINGACC_RING_ELSIZE_INVALID
+};
+
+struct k3_nav_ringacc;
+struct k3_nav_ring;
+
+/**
+ * enum k3_nav_ring_cfg - RA ring configuration structure
+ *
+ * @size: Ring size, number of elements
+ * @elm_size: Ring element size
+ * @mode: Ring operational mode
+ * @flags: Ring configuration flags. Possible values:
+ *	 @K3_NAV_RINGACC_RING_SHARED: when set allows to request the same ring
+ *	 few times. It's usable when the same ring is used as Free Host PD ring
+ *	 for different flows, for example.
+ *	 Note: Locking should be done by consumer if required
+ */
+struct k3_nav_ring_cfg {
+	u32 size;
+	enum k3_nav_ring_size elm_size;
+	enum k3_nav_ring_mode mode;
+#define K3_NAV_RINGACC_RING_SHARED BIT(1)
+	u32 flags;
+};
+
+#define K3_NAV_RINGACC_RING_ID_ANY (-1)
+#define K3_NAV_RINGACC_RING_USE_PROXY BIT(1)
+
+/**
+ * k3_nav_ringacc_request_ring - request ring from ringacc
+ * @ringacc: pointer on ringacc
+ * @id: ring id or K3_NAV_RINGACC_RING_ID_ANY for any general purpose ring
+ * @flags:
+ *	@K3_NAV_RINGACC_RING_USE_PROXY: if set - proxy will be allocated and
+ *		used to access ring memory. Sopported only for rings in
+ *		Message/Credentials/Queue mode.
+ *
+ * Returns pointer on the Ring - struct k3_nav_ring
+ * or NULL in case of failure.
+ */
+struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
+						int id, u32 flags);
+
+/**
+ * k3_nav_ringacc_get_dev - get pointer on RA device
+ * @ringacc: pointer on RA
+ *
+ * Returns device pointer
+ */
+struct udevice *k3_nav_ringacc_get_dev(struct k3_nav_ringacc *ringacc);
+
+/**
+ * k3_nav_ringacc_ring_reset - ring reset
+ * @ring: pointer on Ring
+ *
+ * Resets ring internal state ((hw)occ, (hw)idx).
+ * TODO_GS: ? Ring can be reused without reconfiguration
+ */
+void k3_nav_ringacc_ring_reset(struct k3_nav_ring *ring);
+/**
+ * k3_nav_ringacc_ring_reset - ring reset for DMA rings
+ * @ring: pointer on Ring
+ *
+ * Resets ring internal state ((hw)occ, (hw)idx). Should be used for rings
+ * which are read by K3 UDMA, like TX or Free Host PD rings.
+ */
+void k3_nav_ringacc_ring_reset_dma(struct k3_nav_ring *ring, u32 occ);
+
+/**
+ * k3_nav_ringacc_ring_free - ring free
+ * @ring: pointer on Ring
+ *
+ * Resets ring and free all alocated resources.
+ */
+int k3_nav_ringacc_ring_free(struct k3_nav_ring *ring);
+
+/**
+ * k3_nav_ringacc_get_ring_id - Get the Ring ID
+ * @ring: pointer on ring
+ *
+ * Returns the Ring ID
+ */
+u32 k3_nav_ringacc_get_ring_id(struct k3_nav_ring *ring);
+
+/**
+ * k3_nav_ringacc_ring_cfg - ring configure
+ * @ring: pointer on ring
+ * @cfg: Ring configuration parameters (see &struct k3_nav_ring_cfg)
+ *
+ * Configures ring, including ring memory allocation.
+ * Returns 0 on success, errno otherwise.
+ */
+int k3_nav_ringacc_ring_cfg(struct k3_nav_ring *ring,
+			    struct k3_nav_ring_cfg *cfg);
+
+/**
+ * k3_nav_ringacc_ring_get_size - get ring size
+ * @ring: pointer on ring
+ *
+ * Returns ring size in number of elements.
+ */
+u32 k3_nav_ringacc_ring_get_size(struct k3_nav_ring *ring);
+
+/**
+ * k3_nav_ringacc_ring_get_free - get free elements
+ * @ring: pointer on ring
+ *
+ * Returns number of free elements in the ring.
+ */
+u32 k3_nav_ringacc_ring_get_free(struct k3_nav_ring *ring);
+
+/**
+ * k3_nav_ringacc_ring_get_occ - get ring occupancy
+ * @ring: pointer on ring
+ *
+ * Returns total number of valid entries on the ring
+ */
+u32 k3_nav_ringacc_ring_get_occ(struct k3_nav_ring *ring);
+
+/**
+ * k3_nav_ringacc_ring_is_full - checks if ring is full
+ * @ring: pointer on ring
+ *
+ * Returns true if the ring is full
+ */
+u32 k3_nav_ringacc_ring_is_full(struct k3_nav_ring *ring);
+
+/**
+ * k3_nav_ringacc_ring_push - push element to the ring tail
+ * @ring: pointer on ring
+ * @elem: pointer on ring element buffer
+ *
+ * Push one ring element to the ring tail. Size of the ring element is
+ * determined by ring configuration &struct k3_nav_ring_cfg elm_size.
+ *
+ * Returns 0 on success, errno otherwise.
+ */
+int k3_nav_ringacc_ring_push(struct k3_nav_ring *ring, void *elem);
+
+/**
+ * k3_nav_ringacc_ring_pop - pop element from the ring head
+ * @ring: pointer on ring
+ * @elem: pointer on ring element buffer
+ *
+ * Push one ring element from the ring head. Size of the ring element is
+ * determined by ring configuration &struct k3_nav_ring_cfg elm_size..
+ *
+ * Returns 0 on success, errno otherwise.
+ */
+int k3_nav_ringacc_ring_pop(struct k3_nav_ring *ring, void *elem);
+
+/**
+ * k3_nav_ringacc_ring_push_head - push element to the ring head
+ * @ring: pointer on ring
+ * @elem: pointer on ring element buffer
+ *
+ * Push one ring element to the ring head. Size of the ring element is
+ * determined by ring configuration &struct k3_nav_ring_cfg elm_size.
+ *
+ * Returns 0 on success, errno otherwise.
+ * Not Supported by ring modes: K3_NAV_RINGACC_RING_MODE_RING
+ */
+int k3_nav_ringacc_ring_push_head(struct k3_nav_ring *ring, void *elem);
+
+/**
+ * k3_nav_ringacc_ring_pop_tail - pop element from the ring tail
+ * @ring: pointer on ring
+ * @elem: pointer on ring element buffer
+ *
+ * Push one ring element from the ring tail. Size of the ring element is
+ * determined by ring configuration &struct k3_nav_ring_cfg elm_size.
+ *
+ * Returns 0 on success, errno otherwise.
+ * Not Supported by ring modes: K3_NAV_RINGACC_RING_MODE_RING
+ */
+int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem);
+
+#endif /* __SOC_TI_K3_NAVSS_RINGACC_API_H_ */
diff --git a/include/linux/soc/ti/k3-sec-proxy.h b/include/linux/soc/ti/k3-sec-proxy.h
new file mode 100644
index 0000000..f34854c
--- /dev/null
+++ b/include/linux/soc/ti/k3-sec-proxy.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Texas Instruments' K3 Secure proxy
+ *
+ * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ */
+
+#ifndef K3_SEC_PROXY_H
+#define K3_SEC_PROXY_H
+
+/**
+ * struct k3_sec_proxy_msg - Secure proxy message structure
+ * @len: Length of data in the Buffer
+ * @buf: Buffer pointer
+ *
+ * This is the structure for data used in mbox_send() and mbox_recv().
+ */
+struct k3_sec_proxy_msg {
+	size_t len;
+	u32 *buf;
+};
+
+#endif /* K3_SEC_PROXY_H */
diff --git a/include/linux/soc/ti/ti-udma.h b/include/linux/soc/ti/ti-udma.h
new file mode 100644
index 0000000..e9d4226
--- /dev/null
+++ b/include/linux/soc/ti/ti-udma.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *  Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
+ *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
+ */
+
+#ifndef __TI_UDMA_H
+#define __TI_UDMA_H
+
+/**
+ * struct ti_udma_drv_packet_data - TI UDMA transfer specific data
+ *
+ * @pkt_type: Packet Type - specific for each DMA client HW
+ * @dest_tag: Destination tag The source pointer.
+ *
+ * TI UDMA transfer specific data passed as part of DMA transfer to
+ * the DMA client HW in UDMA descriptors.
+ */
+struct ti_udma_drv_packet_data {
+	u32	pkt_type;
+	u32	dest_tag;
+};
+
+#endif /* __TI_UDMA_H */
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
new file mode 100644
index 0000000..1cba8d9
--- /dev/null
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -0,0 +1,693 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Texas Instruments System Control Interface Protocol
+ * Based on include/linux/soc/ti/ti_sci_protocol.h from Linux.
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Nishanth Menon
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#ifndef __TISCI_PROTOCOL_H
+#define __TISCI_PROTOCOL_H
+
+/**
+ * struct ti_sci_version_info - version information structure
+ * @abi_major:	Major ABI version. Change here implies risk of backward
+ *		compatibility break.
+ * @abi_minor:	Minor ABI version. Change here implies new feature addition,
+ *		or compatible change in ABI.
+ * @firmware_revision:	Firmware revision (not usually used).
+ * @firmware_description: Firmware description (not usually used).
+ */
+struct ti_sci_version_info {
+	u8 abi_major;
+	u8 abi_minor;
+	u16 firmware_revision;
+	char firmware_description[32];
+};
+
+struct ti_sci_handle;
+
+/**
+ * struct ti_sci_board_ops - Board config operations
+ * @board_config: Command to set the board configuration
+ *		  Returns 0 for successful exclusive request, else returns
+ *		  corresponding error message.
+ * @board_config_rm: Command to set the board resource management
+ *		  configuration
+ *		  Returns 0 for successful exclusive request, else returns
+ *		  corresponding error message.
+ * @board_config_security: Command to set the board security configuration
+ *		  Returns 0 for successful exclusive request, else returns
+ *		  corresponding error message.
+ * @board_config_pm: Command to trigger and set the board power and clock
+ *		  management related configuration
+ *		  Returns 0 for successful exclusive request, else returns
+ *		  corresponding error message.
+ */
+struct ti_sci_board_ops {
+	int (*board_config)(const struct ti_sci_handle *handle,
+			    u64 addr, u32 size);
+	int (*board_config_rm)(const struct ti_sci_handle *handle,
+			       u64 addr, u32 size);
+	int (*board_config_security)(const struct ti_sci_handle *handle,
+				     u64 addr, u32 size);
+	int (*board_config_pm)(const struct ti_sci_handle *handle,
+			       u64 addr, u32 size);
+};
+
+/**
+ * struct ti_sci_dev_ops - Device control operations
+ * @get_device: Command to request for device managed by TISCI
+ *		Returns 0 for successful exclusive request, else returns
+ *		corresponding error message.
+ * @idle_device: Command to idle a device managed by TISCI
+ *		Returns 0 for successful exclusive request, else returns
+ *		corresponding error message.
+ * @put_device:	Command to release a device managed by TISCI
+ *		Returns 0 for successful release, else returns corresponding
+ *		error message.
+ * @is_valid:	Check if the device ID is a valid ID.
+ *		Returns 0 if the ID is valid, else returns corresponding error.
+ * @get_context_loss_count: Command to retrieve context loss counter - this
+ *		increments every time the device looses context. Overflow
+ *		is possible.
+ *		- count: pointer to u32 which will retrieve counter
+ *		Returns 0 for successful information request and count has
+ *		proper data, else returns corresponding error message.
+ * @is_idle:	Reports back about device idle state
+ *		- req_state: Returns requested idle state
+ *		Returns 0 for successful information request and req_state and
+ *		current_state has proper data, else returns corresponding error
+ *		message.
+ * @is_stop:	Reports back about device stop state
+ *		- req_state: Returns requested stop state
+ *		- current_state: Returns current stop state
+ *		Returns 0 for successful information request and req_state and
+ *		current_state has proper data, else returns corresponding error
+ *		message.
+ * @is_on:	Reports back about device ON(or active) state
+ *		- req_state: Returns requested ON state
+ *		- current_state: Returns current ON state
+ *		Returns 0 for successful information request and req_state and
+ *		current_state has proper data, else returns corresponding error
+ *		message.
+ * @is_transitioning: Reports back if the device is in the middle of transition
+ *		of state.
+ *		-current_state: Returns 'true' if currently transitioning.
+ * @set_device_resets: Command to configure resets for device managed by TISCI.
+ *		-reset_state: Device specific reset bit field
+ *		Returns 0 for successful request, else returns
+ *		corresponding error message.
+ * @get_device_resets: Command to read state of resets for device managed
+ *		by TISCI.
+ *		-reset_state: pointer to u32 which will retrieve resets
+ *		Returns 0 for successful request, else returns
+ *		corresponding error message.
+ * @release_exclusive_devices: Command to release all the exclusive devices
+ *		attached to this host. This should be used very carefully
+ *		and only at the end of execution of your software.
+ *
+ * NOTE: for all these functions, the following parameters are generic in
+ * nature:
+ * -handle:	Pointer to TISCI handle as retrieved by *ti_sci_get_handle
+ * -id:		Device Identifier
+ *
+ * Request for the device - NOTE: the client MUST maintain integrity of
+ * usage count by balancing get_device with put_device. No refcounting is
+ * managed by driver for that purpose.
+ */
+struct ti_sci_dev_ops {
+	int (*get_device)(const struct ti_sci_handle *handle, u32 id);
+	int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
+	int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
+	int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
+				     u32 id);
+	int (*put_device)(const struct ti_sci_handle *handle, u32 id);
+	int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
+	int (*get_context_loss_count)(const struct ti_sci_handle *handle,
+				      u32 id, u32 *count);
+	int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
+		       bool *requested_state);
+	int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
+		       bool *req_state, bool *current_state);
+	int (*is_on)(const struct ti_sci_handle *handle, u32 id,
+		     bool *req_state, bool *current_state);
+	int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
+				bool *current_state);
+	int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
+				 u32 reset_state);
+	int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
+				 u32 *reset_state);
+	int (*release_exclusive_devices)(const struct ti_sci_handle *handle);
+};
+
+/**
+ * struct ti_sci_clk_ops - Clock control operations
+ * @get_clock:	Request for activation of clock and manage by processor
+ *		- needs_ssc: 'true' if Spread Spectrum clock is desired.
+ *		- can_change_freq: 'true' if frequency change is desired.
+ *		- enable_input_term: 'true' if input termination is desired.
+ * @idle_clock:	Request for Idling a clock managed by processor
+ * @put_clock:	Release the clock to be auto managed by TISCI
+ * @is_auto:	Is the clock being auto managed
+ *		- req_state: state indicating if the clock is auto managed
+ * @is_on:	Is the clock ON
+ *		- req_state: if the clock is requested to be forced ON
+ *		- current_state: if the clock is currently ON
+ * @is_off:	Is the clock OFF
+ *		- req_state: if the clock is requested to be forced OFF
+ *		- current_state: if the clock is currently Gated
+ * @set_parent:	Set the clock source of a specific device clock
+ *		- parent_id: Parent clock identifier to set.
+ * @get_parent:	Get the current clock source of a specific device clock
+ *		- parent_id: Parent clock identifier which is the parent.
+ * @get_num_parents: Get the number of parents of the current clock source
+ *		- num_parents: returns the number of parent clocks.
+ * @get_best_match_freq: Find a best matching frequency for a frequency
+ *		range.
+ *		- match_freq: Best matching frequency in Hz.
+ * @set_freq:	Set the Clock frequency
+ * @get_freq:	Get the Clock frequency
+ *		- current_freq: Frequency in Hz that the clock is at.
+ *
+ * NOTE: for all these functions, the following parameters are generic in
+ * nature:
+ * -handle:	Pointer to TISCI handle as retrieved by *ti_sci_get_handle
+ * -did:	Device identifier this request is for
+ * -cid:	Clock identifier for the device for this request.
+ *		Each device has it's own set of clock inputs. This indexes
+ *		which clock input to modify.
+ * -min_freq:	The minimum allowable frequency in Hz. This is the minimum
+ *		allowable programmed frequency and does not account for clock
+ *		tolerances and jitter.
+ * -target_freq: The target clock frequency in Hz. A frequency will be
+ *		processed as close to this target frequency as possible.
+ * -max_freq:	The maximum allowable frequency in Hz. This is the maximum
+ *		allowable programmed frequency and does not account for clock
+ *		tolerances and jitter.
+ *
+ * Request for the clock - NOTE: the client MUST maintain integrity of
+ * usage count by balancing get_clock with put_clock. No refcounting is
+ * managed by driver for that purpose.
+ */
+struct ti_sci_clk_ops {
+	int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid,
+			 bool needs_ssc, bool can_change_freq,
+			 bool enable_input_term);
+	int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid);
+	int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u8 cid);
+	int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u8 cid,
+		       bool *req_state);
+	int (*is_on)(const struct ti_sci_handle *handle, u32 did, u8 cid,
+		     bool *req_state, bool *current_state);
+	int (*is_off)(const struct ti_sci_handle *handle, u32 did, u8 cid,
+		      bool *req_state, bool *current_state);
+	int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid,
+			  u8 parent_id);
+	int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u8 cid,
+			  u8 *parent_id);
+	int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
+			       u8 cid, u8 *num_parents);
+	int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
+				   u8 cid, u64 min_freq, u64 target_freq,
+				   u64 max_freq, u64 *match_freq);
+	int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid,
+			u64 min_freq, u64 target_freq, u64 max_freq);
+	int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u8 cid,
+			u64 *current_freq);
+};
+
+/**
+ * struct ti_sci_rm_core_ops - Resource management core operations
+ * @get_range:		Get a range of resources belonging to ti sci host.
+ * @get_rage_from_shost:	Get a range of resources belonging to
+ *				specified host id.
+ *			- s_host: Host processing entity to which the
+ *				  resources are allocated
+ *
+ * NOTE: for these functions, all the parameters are consolidated and defined
+ * as below:
+ * - handle:	Pointer to TISCI handle as retrieved by *ti_sci_get_handle
+ * - dev_id:	TISCI device ID.
+ * - subtype:	Resource assignment subtype that is being requested
+ *		from the given device.
+ * - range_start:	Start index of the resource range
+ * - range_end:		Number of resources in the range
+ */
+struct ti_sci_rm_core_ops {
+	int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
+			 u8 subtype, u16 *range_start, u16 *range_num);
+	int (*get_range_from_shost)(const struct ti_sci_handle *handle,
+				    u32 dev_id, u8 subtype, u8 s_host,
+				    u16 *range_start, u16 *range_num);
+};
+
+/**
+ * struct ti_sci_core_ops - SoC Core Operations
+ * @reboot_device: Reboot the SoC
+ *		Returns 0 for successful request(ideally should never return),
+ *		else returns corresponding error value.
+ * @query_msmc: Query the size of available msmc
+ *		Return 0 for successful query else appropriate error value.
+ */
+struct ti_sci_core_ops {
+	int (*reboot_device)(const struct ti_sci_handle *handle);
+	int (*query_msmc)(const struct ti_sci_handle *handle,
+			  u64 *msmc_start, u64 *msmc_end);
+};
+
+/**
+ * struct ti_sci_proc_ops - Processor specific operations.
+ *
+ * @proc_request: Request for controlling a physical processor.
+ *		The requesting host should be in the processor access list.
+ * @proc_release: Relinquish a physical processor control
+ * @proc_handover: Handover a physical processor control to another host
+ *		   in the permitted list.
+ * @set_proc_boot_cfg: Base configuration of the processor
+ * @set_proc_boot_ctrl: Setup limited control flags in specific cases.
+ * @proc_auth_boot_image:
+ * @get_proc_boot_status: Get the state of physical processor
+ * @proc_shutdown_no_wait: Shutdown a core without requesting or waiting for a
+ *			   response.
+ *
+ * NOTE: for all these functions, the following parameters are generic in
+ * nature:
+ * -handle:	Pointer to TISCI handle as retrieved by *ti_sci_get_handle
+ * -pid:	Processor ID
+ *
+ */
+struct ti_sci_proc_ops {
+	int (*proc_request)(const struct ti_sci_handle *handle, u8 pid);
+	int (*proc_release)(const struct ti_sci_handle *handle, u8 pid);
+	int (*proc_handover)(const struct ti_sci_handle *handle, u8 pid,
+			     u8 hid);
+	int (*set_proc_boot_cfg)(const struct ti_sci_handle *handle, u8 pid,
+				 u64 bv, u32 cfg_set, u32 cfg_clr);
+	int (*set_proc_boot_ctrl)(const struct ti_sci_handle *handle, u8 pid,
+				  u32 ctrl_set, u32 ctrl_clr);
+	int (*proc_auth_boot_image)(const struct ti_sci_handle *handle,
+				    u64 *image_addr, u32 *image_size);
+	int (*get_proc_boot_status)(const struct ti_sci_handle *handle, u8 pid,
+				    u64 *bv, u32 *cfg_flags, u32 *ctrl_flags,
+				    u32 *sts_flags);
+	int (*proc_shutdown_no_wait)(const struct ti_sci_handle *handle,
+				     u8 pid);
+};
+
+#define TI_SCI_RING_MODE_RING			(0)
+#define TI_SCI_RING_MODE_MESSAGE		(1)
+#define TI_SCI_RING_MODE_CREDENTIALS		(2)
+#define TI_SCI_RING_MODE_QM			(3)
+
+#define TI_SCI_MSG_UNUSED_SECONDARY_HOST TI_SCI_RM_NULL_U8
+
+/* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID	BIT(0)
+/* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID	BIT(1)
+ /* RA config.count parameter is valid for RM ring configure TI_SCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID	BIT(2)
+/* RA config.mode parameter is valid for RM ring configure TI_SCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID	BIT(3)
+/* RA config.size parameter is valid for RM ring configure TI_SCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID	BIT(4)
+/* RA config.order_id parameter is valid for RM ring configure TISCI message */
+#define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID	BIT(5)
+
+#define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
+	(TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
+	TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
+	TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
+	TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
+	TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
+
+/**
+ * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
+ * @config: configure the SoC Navigator Subsystem Ring Accelerator ring
+ * @get_config: get the SoC Navigator Subsystem Ring Accelerator ring
+ *		configuration
+ */
+struct ti_sci_rm_ringacc_ops {
+	int (*config)(const struct ti_sci_handle *handle,
+		      u32 valid_params, u16 nav_id, u16 index,
+		      u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
+		      u8 size, u8 order_id
+	);
+	int (*get_config)(const struct ti_sci_handle *handle,
+			  u32 nav_id, u32 index, u8 *mode,
+			  u32 *addr_lo, u32 *addr_hi, u32 *count,
+			  u8 *size, u8 *order_id);
+};
+
+/**
+ * struct ti_sci_rm_psil_ops - PSI-L thread operations
+ * @pair: pair PSI-L source thread to a destination thread.
+ *	If the src_thread is mapped to UDMA tchan, the corresponding channel's
+ *	TCHAN_THRD_ID register is updated.
+ *	If the dst_thread is mapped to UDMA rchan, the corresponding channel's
+ *	RCHAN_THRD_ID register is updated.
+ * @unpair: unpair PSI-L source thread from a destination thread.
+ *	If the src_thread is mapped to UDMA tchan, the corresponding channel's
+ *	TCHAN_THRD_ID register is cleared.
+ *	If the dst_thread is mapped to UDMA rchan, the corresponding channel's
+ *	RCHAN_THRD_ID register is cleared.
+ */
+struct ti_sci_rm_psil_ops {
+	int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
+		    u32 src_thread, u32 dst_thread);
+	int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
+		      u32 src_thread, u32 dst_thread);
+};
+
+/* UDMAP channel types */
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR		2
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB		3	/* RX only */
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR		10
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR		11
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR	12
+#define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR	13
+
+/* UDMAP channel atypes */
+#define TI_SCI_RM_UDMAP_ATYPE_PHYS			0
+#define TI_SCI_RM_UDMAP_ATYPE_INTERMEDIATE		1
+#define TI_SCI_RM_UDMAP_ATYPE_VIRTUAL			2
+
+/* UDMAP channel scheduling priorities */
+#define TI_SCI_RM_UDMAP_SCHED_PRIOR_HIGH		0
+#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDHIGH		1
+#define TI_SCI_RM_UDMAP_SCHED_PRIOR_MEDLOW		2
+#define TI_SCI_RM_UDMAP_SCHED_PRIOR_LOW			3
+
+#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST		0
+#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO		2
+
+/* UDMAP TX/RX channel valid_params common declarations */
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID		BIT(0)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID                BIT(1)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID            BIT(2)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID           BIT(3)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID              BIT(4)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID             BIT(5)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID                  BIT(6)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID             BIT(7)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID       BIT(8)
+
+/**
+ * Configures a Navigator Subsystem UDMAP transmit channel
+ *
+ * Configures a Navigator Subsystem UDMAP transmit channel registers.
+ * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
+ */
+struct ti_sci_msg_rm_udmap_tx_ch_cfg {
+	u32 valid_params;
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID        BIT(9)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID      BIT(10)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID        BIT(11)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID      BIT(12)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID            BIT(13)
+	u16 nav_id;
+	u16 index;
+	u8 tx_pause_on_err;
+	u8 tx_filt_einfo;
+	u8 tx_filt_pswords;
+	u8 tx_atype;
+	u8 tx_chan_type;
+	u8 tx_supr_tdpkt;
+	u16 tx_fetch_size;
+	u8 tx_credit_count;
+	u16 txcq_qnum;
+	u8 tx_priority;
+	u8 tx_qos;
+	u8 tx_orderid;
+	u16 fdepth;
+	u8 tx_sched_priority;
+};
+
+/**
+ * Configures a Navigator Subsystem UDMAP receive channel
+ *
+ * Configures a Navigator Subsystem UDMAP receive channel registers.
+ * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
+ */
+struct ti_sci_msg_rm_udmap_rx_ch_cfg {
+	u32 valid_params;
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID      BIT(9)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID        BIT(10)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID      BIT(11)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID       BIT(12)
+	u16 nav_id;
+	u16 index;
+	u16 rx_fetch_size;
+	u16 rxcq_qnum;
+	u8 rx_priority;
+	u8 rx_qos;
+	u8 rx_orderid;
+	u8 rx_sched_priority;
+	u16 flowid_start;
+	u16 flowid_cnt;
+	u8 rx_pause_on_err;
+	u8 rx_atype;
+	u8 rx_chan_type;
+	u8 rx_ignore_short;
+	u8 rx_ignore_long;
+};
+
+/**
+ * Configures a Navigator Subsystem UDMAP receive flow
+ *
+ * Configures a Navigator Subsystem UDMAP receive flow's registers.
+ * See @tis_ci_msg_rm_udmap_flow_cfg_req
+ */
+struct ti_sci_msg_rm_udmap_flow_cfg {
+	u32 valid_params;
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID	BIT(0)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID     BIT(1)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID     BIT(2)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID          BIT(3)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID         BIT(4)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID          BIT(5)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID         BIT(6)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID         BIT(7)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID        BIT(8)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID        BIT(9)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID     BIT(10)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID     BIT(11)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID    BIT(12)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID    BIT(13)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID      BIT(14)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID          BIT(15)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID          BIT(16)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID          BIT(17)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID        BIT(18)
+	u16 nav_id;
+	u16 flow_index;
+	u8 rx_einfo_present;
+	u8 rx_psinfo_present;
+	u8 rx_error_handling;
+	u8 rx_desc_type;
+	u16 rx_sop_offset;
+	u16 rx_dest_qnum;
+	u8 rx_src_tag_hi;
+	u8 rx_src_tag_lo;
+	u8 rx_dest_tag_hi;
+	u8 rx_dest_tag_lo;
+	u8 rx_src_tag_hi_sel;
+	u8 rx_src_tag_lo_sel;
+	u8 rx_dest_tag_hi_sel;
+	u8 rx_dest_tag_lo_sel;
+	u16 rx_fdq0_sz0_qnum;
+	u16 rx_fdq1_qnum;
+	u16 rx_fdq2_qnum;
+	u16 rx_fdq3_qnum;
+	u8 rx_ps_location;
+};
+
+/**
+ * struct ti_sci_rm_udmap_ops - UDMA Management operations
+ * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
+ * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
+ * @rx_flow_cfg: configure SoC Navigator Subsystem UDMA receive flow.
+ */
+struct ti_sci_rm_udmap_ops {
+	int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
+			 const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
+	int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
+			 const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
+	int (*rx_flow_cfg)(
+		const struct ti_sci_handle *handle,
+		const struct ti_sci_msg_rm_udmap_flow_cfg *params);
+};
+
+/**
+ * struct ti_sci_msg_fwl_region_cfg - Request and Response for firewalls settings
+ *
+ * @fwl_id:		Firewall ID in question
+ * @region:		Region or channel number to set config info
+ *			This field is unused in case of a simple firewall  and must be initialized
+ *			to zero.  In case of a region based firewall, this field indicates the
+ *			region in question. (index starting from 0) In case of a channel based
+ *			firewall, this field indicates the channel in question (index starting
+ *			from 0)
+ * @n_permission_regs:	Number of permission registers to set
+ * @control:		Contents of the firewall CONTROL register to set
+ * @permissions:	Contents of the firewall PERMISSION register to set
+ * @start_address:	Contents of the firewall START_ADDRESS register to set
+ * @end_address:	Contents of the firewall END_ADDRESS register to set
+ */
+struct ti_sci_msg_fwl_region {
+	u16 fwl_id;
+	u16 region;
+	u32 n_permission_regs;
+	u32 control;
+	u32 permissions[3];
+	u64 start_address;
+	u64 end_address;
+} __packed;
+
+/**
+ * \brief Request and Response for firewall owner change
+ *
+ * @fwl_id:		Firewall ID in question
+ * @region:		Region or channel number to set config info
+ *			This field is unused in case of a simple firewall  and must be initialized
+ *			to zero.  In case of a region based firewall, this field indicates the
+ *			region in question. (index starting from 0) In case of a channel based
+ *			firewall, this field indicates the channel in question (index starting
+ *			from 0)
+ * @n_permission_regs:	Number of permission registers <= 3
+ * @control:		Control register value for this region
+ * @owner_index:	New owner index to change to. Owner indexes are setup in DMSC firmware boot configuration data
+ * @owner_privid:	New owner priv-id, used to lookup owner_index is not known, must be set to zero otherwise
+ * @owner_permission_bits: New owner permission bits
+ */
+struct ti_sci_msg_fwl_owner {
+	u16 fwl_id;
+	u16 region;
+	u8 owner_index;
+	u8 owner_privid;
+	u16 owner_permission_bits;
+} __packed;
+
+/**
+ * struct ti_sci_fwl_ops - Firewall specific operations
+ * @set_fwl_region: Request for configuring the firewall permissions.
+ * @get_fwl_region: Request for retrieving the firewall permissions.
+ * @change_fwl_owner: Request for a change of firewall owner.
+ */
+struct ti_sci_fwl_ops {
+	int (*set_fwl_region)(const struct ti_sci_handle *handle, const struct ti_sci_msg_fwl_region *region);
+	int (*get_fwl_region)(const struct ti_sci_handle *handle, struct ti_sci_msg_fwl_region *region);
+	int (*change_fwl_owner)(const struct ti_sci_handle *handle, struct ti_sci_msg_fwl_owner *owner);
+};
+
+/**
+ * struct ti_sci_ops - Function support for TI SCI
+ * @board_ops:	Miscellaneous operations
+ * @dev_ops:	Device specific operations
+ * @clk_ops:	Clock specific operations
+ * @core_ops:	Core specific operations
+ * @proc_ops:	Processor specific operations
+ * @ring_ops: Ring Accelerator Management operations
+ * @fw_ops:	Firewall specific operations
+ */
+struct ti_sci_ops {
+	struct ti_sci_board_ops board_ops;
+	struct ti_sci_dev_ops dev_ops;
+	struct ti_sci_clk_ops clk_ops;
+	struct ti_sci_core_ops core_ops;
+	struct ti_sci_proc_ops proc_ops;
+	struct ti_sci_rm_core_ops rm_core_ops;
+	struct ti_sci_rm_ringacc_ops rm_ring_ops;
+	struct ti_sci_rm_psil_ops rm_psil_ops;
+	struct ti_sci_rm_udmap_ops rm_udmap_ops;
+	struct ti_sci_fwl_ops fwl_ops;
+};
+
+/**
+ * struct ti_sci_handle - Handle returned to TI SCI clients for usage.
+ * @ops:	operations that are made available to TI SCI clients
+ * @version:	structure containing version information
+ */
+struct ti_sci_handle {
+	struct ti_sci_ops ops;
+	struct ti_sci_version_info version;
+};
+
+#define TI_SCI_RESOURCE_NULL	0xffff
+
+/**
+ * struct ti_sci_resource_desc - Description of TI SCI resource instance range.
+ * @start:	Start index of the resource.
+ * @num:	Number of resources.
+ * @res_map:	Bitmap to manage the allocation of these resources.
+ */
+struct ti_sci_resource_desc {
+	u16 start;
+	u16 num;
+	unsigned long *res_map;
+};
+
+/**
+ * struct ti_sci_resource - Structure representing a resource assigned
+ *			    to a device.
+ * @sets:	Number of sets available from this resource type
+ * @desc:	Array of resource descriptors.
+ */
+struct ti_sci_resource {
+	u16 sets;
+	struct ti_sci_resource_desc *desc;
+};
+
+#if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
+
+const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *dev);
+const struct ti_sci_handle *ti_sci_get_handle(struct udevice *dev);
+const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
+						  const char *property);
+u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
+void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
+struct ti_sci_resource *
+devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
+			    struct udevice *dev, u32 dev_id, char *of_prop);
+
+#else	/* CONFIG_TI_SCI_PROTOCOL */
+
+static inline
+const struct ti_sci_handle *ti_sci_get_handle_from_sysfw(struct udevice *dev)
+{
+	return ERR_PTR(-EINVAL);
+}
+
+static inline const struct ti_sci_handle *ti_sci_get_handle(struct udevice *dev)
+{
+	return ERR_PTR(-EINVAL);
+}
+
+static inline
+const struct ti_sci_handle *ti_sci_get_by_phandle(struct udevice *dev,
+						  const char *property)
+{
+	return ERR_PTR(-EINVAL);
+}
+
+static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
+{
+	return TI_SCI_RESOURCE_NULL;
+}
+
+static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
+{
+}
+
+static inline struct ti_sci_resource *
+devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
+			    struct udevice *dev, u32 dev_id, char *of_prop)
+{
+	return ERR_PTR(-EINVAL);
+}
+#endif	/* CONFIG_TI_SCI_PROTOCOL */
+
+#endif	/* __TISCI_PROTOCOL_H */
diff --git a/include/linux/stat.h b/include/linux/stat.h
new file mode 100644
index 0000000..5eba633
--- /dev/null
+++ b/include/linux/stat.h
@@ -0,0 +1,158 @@
+#ifndef _LINUX_STAT_H
+#define _LINUX_STAT_H
+
+#include <linux/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define S_IFMT	00170000	/* type of file */
+#define S_IFSOCK 0140000	/* named socket */
+#define S_IFLNK	 0120000	/* symbolic link */
+#define S_IFREG  0100000	/* regular */
+#define S_IFBLK  0060000	/* block special */
+#define S_IFDIR  0040000	/* directory */
+#define S_IFCHR  0020000	/* character special */
+#define S_IFIFO  0010000	/* fifo */
+#define S_ISUID  0004000	/* set user id on execution */
+#define S_ISGID  0002000	/* set group id on execution */
+#define S_ISVTX  0001000	/* save swapped text even after use */
+
+#define S_ISLNK(m)	(((m) & S_IFMT) == S_IFLNK)
+#define S_ISREG(m)	(((m) & S_IFMT) == S_IFREG)
+#define S_ISDIR(m)	(((m) & S_IFMT) == S_IFDIR)
+#define S_ISCHR(m)	(((m) & S_IFMT) == S_IFCHR)
+#define S_ISBLK(m)	(((m) & S_IFMT) == S_IFBLK)
+#define S_ISFIFO(m)	(((m) & S_IFMT) == S_IFIFO)
+#define S_ISSOCK(m)	(((m) & S_IFMT) == S_IFSOCK)
+
+#define S_IRWXU 00700		/* rwx for owner */
+#define S_IRUSR 00400		/* read permission for owner */
+#define S_IWUSR 00200		/* write permission for owner */
+#define S_IXUSR 00100		/* execute/search permission for owner */
+
+#define S_IRWXG 00070		/* rwx for group */
+#define S_IRGRP 00040		/* read permission for group */
+#define S_IWGRP 00020		/* write permission for group */
+#define S_IXGRP 00010		/* execute/search permission for group */
+
+#define S_IRWXO 00007		/* rwx for other */
+#define S_IROTH 00004		/* read permission for other */
+#define S_IWOTH 00002		/* read permission for other */
+#define S_IXOTH 00001		/* execute/search permission for other */
+
+#ifdef	__PPC__
+
+struct stat {
+	dev_t		st_dev;		/* file system id */
+	ino_t		st_ino;		/* file id */
+	mode_t		st_mode;	/* ownership/protection */
+	nlink_t		st_nlink;	/* number of links */
+	uid_t		st_uid;		/* user id */
+	gid_t		st_gid;		/* group id */
+	dev_t		st_rdev;
+	off_t		st_size;	/* file size in # of bytes */
+	unsigned long	st_blksize;	/* block size */
+	unsigned long	st_blocks;	/* file size in # of blocks */
+	unsigned long	st_atime;	/* time file was last accessed */
+	unsigned long	__unused1;
+	unsigned long	st_mtime;	/* time file was last modified */
+	unsigned long	__unused2;
+	unsigned long	st_ctime;	/* time file status was last changed */
+	unsigned long	__unused3;
+	unsigned long	__unused4;
+	unsigned long	__unused5;
+};
+
+#endif	/* __PPC__ */
+
+#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\
+	defined (__microblaze__) || defined (__nios2__)
+
+struct stat {
+	unsigned short st_dev;
+	unsigned short __pad1;
+	unsigned long st_ino;
+	unsigned short st_mode;
+	unsigned short st_nlink;
+	unsigned short st_uid;
+	unsigned short st_gid;
+	unsigned short st_rdev;
+	unsigned short __pad2;
+	unsigned long  st_size;
+	unsigned long  st_blksize;
+	unsigned long  st_blocks;
+	unsigned long  st_atime;
+	unsigned long  __unused1;
+	unsigned long  st_mtime;
+	unsigned long  __unused2;
+	unsigned long  st_ctime;
+	unsigned long  __unused3;
+	unsigned long  __unused4;
+	unsigned long  __unused5;
+};
+
+#endif	/* __ARM__ */
+
+#if defined (__MIPS__)
+
+struct stat {
+	dev_t		st_dev;
+	long		st_pad1[3];
+	ino_t		st_ino;
+	mode_t		st_mode;
+	nlink_t		st_nlink;
+	uid_t		st_uid;
+	gid_t		st_gid;
+	dev_t		st_rdev;
+	long		st_pad2[2];
+	off_t		st_size;
+	long		st_pad3;
+	/*
+	 * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+	 * but we don't have it under Linux.
+	 */
+	time_t		st_atime;
+	long		reserved0;
+	time_t		st_mtime;
+	long		reserved1;
+	time_t		st_ctime;
+	long		reserved2;
+	long		st_blksize;
+	long		st_blocks;
+	long		st_pad4[14];
+};
+
+#endif	/* __MIPS__ */
+
+#if defined(__SH__) || defined(__XTENSA__)
+
+struct stat {
+	unsigned long st_dev;
+	unsigned long st_ino;
+	unsigned short st_mode;
+	unsigned short st_nlink;
+	unsigned short st_uid;
+	unsigned short st_gid;
+	unsigned long  st_rdev;
+	unsigned long  st_size;
+	unsigned long  st_blksize;
+	unsigned long  st_blocks;
+	unsigned long  st_atime;
+	unsigned long  st_atime_nsec;
+	unsigned long  st_mtime;
+	unsigned long  st_mtime_nsec;
+	unsigned long  st_ctime;
+	unsigned long  st_ctime_nsec;
+	unsigned long  __unused4;
+	unsigned long  __unused5;
+};
+
+#endif /* __SH__  || __XTENSA__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/linux/stddef.h b/include/linux/stddef.h
new file mode 100644
index 0000000..c540f61
--- /dev/null
+++ b/include/linux/stddef.h
@@ -0,0 +1,20 @@
+#ifndef _LINUX_STDDEF_H
+#define _LINUX_STDDEF_H
+
+#undef NULL
+#if defined(__cplusplus)
+#define NULL 0
+#else
+#define NULL ((void *)0)
+#endif
+
+#ifndef _SIZE_T
+#include <linux/types.h>
+#endif
+
+#ifndef __CHECKER__
+#undef offsetof
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/include/linux/string.h b/include/linux/string.h
new file mode 100644
index 0000000..5d63be4
--- /dev/null
+++ b/include/linux/string.h
@@ -0,0 +1,131 @@
+#ifndef _LINUX_STRING_H_
+#define _LINUX_STRING_H_
+
+#include <linux/types.h>	/* for size_t */
+#include <linux/stddef.h>	/* for NULL */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern char * ___strtok;
+extern char * strpbrk(const char *,const char *);
+extern char * strtok(char *,const char *);
+extern char * strsep(char **,const char *);
+extern __kernel_size_t strspn(const char *,const char *);
+
+
+/*
+ * Include machine specific inline routines
+ */
+#include <asm/string.h>
+
+#ifndef __HAVE_ARCH_STRCPY
+extern char * strcpy(char *,const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNCPY
+extern char * strncpy(char *,const char *, __kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRLCPY
+size_t strlcpy(char *, const char *, size_t);
+#endif
+#ifndef __HAVE_ARCH_STRCAT
+extern char * strcat(char *, const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNCAT
+extern char * strncat(char *, const char *, __kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRCMP
+extern int strcmp(const char *,const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNCMP
+extern int strncmp(const char *,const char *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRCASECMP
+int strcasecmp(const char *s1, const char *s2);
+#endif
+#ifndef __HAVE_ARCH_STRNCASECMP
+extern int strncasecmp(const char *s1, const char *s2, __kernel_size_t len);
+#endif
+#ifndef __HAVE_ARCH_STRCHR
+extern char * strchr(const char *,int);
+#endif
+
+/**
+ * strchrnul() - return position of a character in the string, or end of string
+ *
+ * The strchrnul() function is like strchr() except that if c is not found
+ * in s, then it returns a pointer to the nul byte at the end of s, rather than
+ * NULL
+ * @s: string to search
+ * @c: character to search for
+ * @return position of @c in @s, or end of @s if not found
+ */
+const char *strchrnul(const char *s, int c);
+
+#ifndef __HAVE_ARCH_STRRCHR
+extern char * strrchr(const char *,int);
+#endif
+#include <linux/linux_string.h>
+#ifndef __HAVE_ARCH_STRSTR
+extern char * strstr(const char *,const char *);
+#endif
+#ifndef __HAVE_ARCH_STRLEN
+extern __kernel_size_t strlen(const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNLEN
+extern __kernel_size_t strnlen(const char *,__kernel_size_t);
+#endif
+
+#ifndef __HAVE_ARCH_STRCSPN
+/**
+ * strcspn() - find span of string without given characters
+ *
+ * Calculates the length of the initial segment of @s which consists entirely
+ * of bsytes not in reject.
+ *
+ * @s: string to search
+ * @reject: strings which cause the search to halt
+ * @return number of characters at the start of @s which are not in @reject
+ */
+size_t strcspn(const char *s, const char *reject);
+#endif
+
+#ifndef __HAVE_ARCH_STRDUP
+extern char * strdup(const char *);
+#endif
+extern char * strndup(const char *, size_t);
+#ifndef __HAVE_ARCH_STRSWAB
+extern char * strswab(const char *);
+#endif
+
+#ifndef __HAVE_ARCH_MEMSET
+extern void * memset(void *,int,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *,const void *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *,const void *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMSCAN
+extern void * memscan(void *,int,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMCMP
+extern int memcmp(const void *,const void *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMCHR
+extern void * memchr(const void *,int,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMCHR_INV
+void *memchr_inv(const void *, int, size_t);
+#endif
+
+unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
+unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LINUX_STRING_H_ */
diff --git a/include/linux/stringify.h b/include/linux/stringify.h
new file mode 100644
index 0000000..841cec8
--- /dev/null
+++ b/include/linux/stringify.h
@@ -0,0 +1,12 @@
+#ifndef __LINUX_STRINGIFY_H
+#define __LINUX_STRINGIFY_H
+
+/* Indirect stringification.  Doing two levels allows the parameter to be a
+ * macro itself.  For example, compile with -DFOO=bar, __stringify(FOO)
+ * converts to "bar".
+ */
+
+#define __stringify_1(x...)	#x
+#define __stringify(x...)	__stringify_1(x)
+
+#endif	/* !__LINUX_STRINGIFY_H */
diff --git a/include/linux/time.h b/include/linux/time.h
new file mode 100644
index 0000000..b8d298e
--- /dev/null
+++ b/include/linux/time.h
@@ -0,0 +1,153 @@
+#ifndef _LINUX_TIME_H
+#define _LINUX_TIME_H
+
+#include <linux/types.h>
+
+#define _DEFUN(a,b,c) a(c)
+#define _CONST const
+#define _AND ,
+
+#define _REENT_ONLY
+
+#define SECSPERMIN	60L
+#define MINSPERHOUR	60L
+#define HOURSPERDAY	24L
+#define SECSPERHOUR	(SECSPERMIN * MINSPERHOUR)
+#define SECSPERDAY	(SECSPERHOUR * HOURSPERDAY)
+#define DAYSPERWEEK	7
+#define MONSPERYEAR	12
+
+#define YEAR_BASE	1900
+#define EPOCH_YEAR      1970
+#define EPOCH_WDAY      4
+
+#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0)
+
+
+/* Used by other time functions.  */
+struct tm {
+    int tm_sec;                   /* Seconds.     [0-60] (1 leap second) */
+    int tm_min;                   /* Minutes.     [0-59] */
+    int tm_hour;                  /* Hours.       [0-23] */
+    int tm_mday;                  /* Day.         [1-31] */
+    int tm_mon;                   /* Month.       [0-11] */
+    int tm_year;                  /* Year - 1900.  */
+    int tm_wday;                  /* Day of week. [0-6] */
+    int tm_yday;                  /* Days in year.[0-365] */
+    int tm_isdst;                 /* DST.         [-1/0/1]*/
+
+# ifdef __USE_BSD
+    long int tm_gmtoff;           /* Seconds east of UTC.  */
+    __const char *tm_zone;        /* Timezone abbreviation.  */
+# else
+    long int __tm_gmtoff;         /* Seconds east of UTC.  */
+    __const char *__tm_zone;      /* Timezone abbreviation.  */
+# endif
+};
+
+static inline char *
+_DEFUN (asctime_r, (tim_p, result),
+	_CONST struct tm *tim_p _AND
+	char *result)
+{
+    static _CONST char day_name[7][3] = {
+	"Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat"
+    };
+    static _CONST char mon_name[12][3] = {
+	"Jan", "Feb", "Mar", "Apr", "May", "Jun",
+	"Jul", "Aug", "Sep", "Oct", "Nov", "Dec"
+    };
+
+    sprintf (result, "%.3s %.3s %.2d %.2d:%.2d:%.2d %d\n",
+	    day_name[tim_p->tm_wday],
+	    mon_name[tim_p->tm_mon],
+	    tim_p->tm_mday, tim_p->tm_hour, tim_p->tm_min,
+	    tim_p->tm_sec, 1900 + tim_p->tm_year);
+    return result;
+}
+
+static inline struct tm *
+_DEFUN (localtime_r, (tim_p, res),
+	_CONST time_t * tim_p _AND
+	struct tm *res)
+{
+    static _CONST int mon_lengths[2][MONSPERYEAR] = {
+      {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31},
+      {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}
+    } ;
+
+    static _CONST int year_lengths[2] = {
+      365,
+      366
+    } ;
+
+    long days, rem;
+    int y;
+    int yleap;
+    _CONST int *ip;
+
+    days = ((long) *tim_p) / SECSPERDAY;
+    rem = ((long) *tim_p) % SECSPERDAY;
+    while (rem < 0)
+    {
+	rem += SECSPERDAY;
+	--days;
+    }
+
+    /* compute hour, min, and sec */
+    res->tm_hour = (int) (rem / SECSPERHOUR);
+    rem %= SECSPERHOUR;
+    res->tm_min = (int) (rem / SECSPERMIN);
+    res->tm_sec = (int) (rem % SECSPERMIN);
+
+    /* compute day of week */
+    if ((res->tm_wday = ((EPOCH_WDAY + days) % DAYSPERWEEK)) < 0)
+	res->tm_wday += DAYSPERWEEK;
+
+    /* compute year & day of year */
+    y = EPOCH_YEAR;
+    if (days >= 0)
+    {
+	for (;;)
+	{
+	    yleap = isleap(y);
+	    if (days < year_lengths[yleap])
+		break;
+	    y++;
+	    days -= year_lengths[yleap];
+	}
+    }
+    else
+    {
+	do
+	{
+	    --y;
+	    yleap = isleap(y);
+	    days += year_lengths[yleap];
+	} while (days < 0);
+    }
+
+    res->tm_year = y - YEAR_BASE;
+    res->tm_yday = days;
+    ip = mon_lengths[yleap];
+    for (res->tm_mon = 0; days >= ip[res->tm_mon]; ++res->tm_mon)
+	days -= ip[res->tm_mon];
+    res->tm_mday = days + 1;
+
+    /* set daylight saving time flag */
+    res->tm_isdst = -1;
+
+    return (res);
+}
+
+static inline char *
+_DEFUN (ctime_r, (tim_p, result),
+	_CONST time_t * tim_p _AND
+	char * result)
+
+{
+    struct tm tm;
+    return asctime_r (localtime_r (tim_p, &tm), result);
+}
+
+#endif
diff --git a/include/linux/typecheck.h b/include/linux/typecheck.h
new file mode 100644
index 0000000..eb5b74a
--- /dev/null
+++ b/include/linux/typecheck.h
@@ -0,0 +1,24 @@
+#ifndef TYPECHECK_H_INCLUDED
+#define TYPECHECK_H_INCLUDED
+
+/*
+ * Check at compile time that something is of a particular type.
+ * Always evaluates to 1 so you may use it easily in comparisons.
+ */
+#define typecheck(type,x) \
+({	type __dummy; \
+	typeof(x) __dummy2; \
+	(void)(&__dummy == &__dummy2); \
+	1; \
+})
+
+/*
+ * Check at compile time that 'function' is a certain type, or is a pointer
+ * to that type (needs to use typedef for the function type.)
+ */
+#define typecheck_fn(type,function) \
+({	typeof(type) __tmp = function; \
+	(void)__tmp; \
+})
+
+#endif		/* TYPECHECK_H_INCLUDED */
diff --git a/include/linux/types.h b/include/linux/types.h
new file mode 100644
index 0000000..cc6f7cb
--- /dev/null
+++ b/include/linux/types.h
@@ -0,0 +1,164 @@
+#ifndef _LINUX_TYPES_H
+#define _LINUX_TYPES_H
+
+#include <linux/posix_types.h>
+#include <asm/types.h>
+#include <stdbool.h>
+
+#ifndef __KERNEL_STRICT_NAMES
+
+typedef __kernel_fd_set		fd_set;
+typedef __kernel_dev_t		dev_t;
+typedef __kernel_ino_t		ino_t;
+typedef __kernel_mode_t		mode_t;
+typedef __kernel_nlink_t	nlink_t;
+typedef __kernel_off_t		off_t;
+typedef __kernel_pid_t		pid_t;
+typedef __kernel_daddr_t	daddr_t;
+typedef __kernel_key_t		key_t;
+typedef __kernel_suseconds_t	suseconds_t;
+
+#ifdef __KERNEL__
+typedef __kernel_uid32_t	uid_t;
+typedef __kernel_gid32_t	gid_t;
+typedef __kernel_uid16_t        uid16_t;
+typedef __kernel_gid16_t        gid16_t;
+
+typedef unsigned long		uintptr_t;
+
+#ifdef CONFIG_UID16
+/* This is defined by include/asm-{arch}/posix_types.h */
+typedef __kernel_old_uid_t	old_uid_t;
+typedef __kernel_old_gid_t	old_gid_t;
+#endif /* CONFIG_UID16 */
+
+/* libc5 includes this file to define uid_t, thus uid_t can never change
+ * when it is included by non-kernel code
+ */
+#else
+typedef __kernel_uid_t		uid_t;
+typedef __kernel_gid_t		gid_t;
+#endif /* __KERNEL__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __kernel_loff_t		loff_t;
+#endif
+
+/*
+ * The following typedefs are also protected by individual ifdefs for
+ * historical reasons:
+ */
+#ifndef _SIZE_T
+#define _SIZE_T
+typedef __kernel_size_t		size_t;
+#endif
+
+#ifndef _SSIZE_T
+#define _SSIZE_T
+typedef __kernel_ssize_t	ssize_t;
+#endif
+
+#ifndef _PTRDIFF_T
+#define _PTRDIFF_T
+typedef __kernel_ptrdiff_t	ptrdiff_t;
+#endif
+
+#ifndef _TIME_T
+#define _TIME_T
+typedef __kernel_time_t		time_t;
+#endif
+
+#ifndef _CLOCK_T
+#define _CLOCK_T
+typedef __kernel_clock_t	clock_t;
+#endif
+
+#ifndef _CADDR_T
+#define _CADDR_T
+typedef __kernel_caddr_t	caddr_t;
+#endif
+
+/* bsd */
+typedef unsigned char		u_char;
+typedef unsigned short		u_short;
+typedef unsigned int		u_int;
+typedef unsigned long		u_long;
+
+/* sysv */
+typedef unsigned char		unchar;
+typedef unsigned short		ushort;
+typedef unsigned int		uint;
+typedef unsigned long		ulong;
+
+#ifndef __BIT_TYPES_DEFINED__
+#define __BIT_TYPES_DEFINED__
+
+typedef		__u8		u_int8_t;
+typedef		__s8		int8_t;
+typedef		__u16		u_int16_t;
+typedef		__s16		int16_t;
+typedef		__u32		u_int32_t;
+typedef		__s32		int32_t;
+
+#endif /* !(__BIT_TYPES_DEFINED__) */
+
+typedef		__u8		uint8_t;
+typedef		__u16		uint16_t;
+typedef		__u32		uint32_t;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef		__u64		uint64_t;
+typedef		__u64		u_int64_t;
+typedef		__s64		int64_t;
+#endif
+
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* this is a special 64bit data type that is 8-byte aligned */
+#define aligned_u64 __u64 __aligned(8)
+#define aligned_be64 __be64 __aligned(8)
+#define aligned_le64 __le64 __aligned(8)
+
+#ifdef __KERNEL__
+typedef phys_addr_t resource_size_t;
+#endif
+
+/*
+ * Below are truly Linux-specific types that should never collide with
+ * any application/library that wants linux/types.h.
+ */
+#ifdef __CHECKER__
+#define __bitwise__ __attribute__((bitwise))
+#else
+#define __bitwise__
+#endif
+#ifdef __CHECK_ENDIAN__
+#define __bitwise __bitwise__
+#else
+#define __bitwise
+#endif
+
+typedef __u16 __bitwise __le16;
+typedef __u16 __bitwise __be16;
+typedef __u32 __bitwise __le32;
+typedef __u32 __bitwise __be32;
+#if defined(__GNUC__)
+typedef __u64 __bitwise __le64;
+typedef __u64 __bitwise __be64;
+#endif
+typedef __u16 __bitwise __sum16;
+typedef __u32 __bitwise __wsum;
+
+typedef unsigned __bitwise__	gfp_t;
+
+struct ustat {
+	__kernel_daddr_t	f_tfree;
+	__kernel_ino_t		f_tinode;
+	char			f_fname[6];
+	char			f_fpack[6];
+};
+
+#define DECLARE_BITMAP(name, bits) \
+	unsigned long name[BITS_TO_LONGS(bits)]
+
+#endif /* _LINUX_TYPES_H */
diff --git a/include/linux/unaligned/access_ok.h b/include/linux/unaligned/access_ok.h
new file mode 100644
index 0000000..5f46eee
--- /dev/null
+++ b/include/linux/unaligned/access_ok.h
@@ -0,0 +1,66 @@
+#ifndef _LINUX_UNALIGNED_ACCESS_OK_H
+#define _LINUX_UNALIGNED_ACCESS_OK_H
+
+#include <asm/byteorder.h>
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+	return le16_to_cpup((__le16 *)p);
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+	return le32_to_cpup((__le32 *)p);
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+	return le64_to_cpup((__le64 *)p);
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+	return be16_to_cpup((__be16 *)p);
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+	return be32_to_cpup((__be32 *)p);
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+	return be64_to_cpup((__be64 *)p);
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+	*((__le16 *)p) = cpu_to_le16(val);
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+	*((__le32 *)p) = cpu_to_le32(val);
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+	*((__le64 *)p) = cpu_to_le64(val);
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+	*((__be16 *)p) = cpu_to_be16(val);
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+	*((__be32 *)p) = cpu_to_be32(val);
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+	*((__be64 *)p) = cpu_to_be64(val);
+}
+
+#endif /* _LINUX_UNALIGNED_ACCESS_OK_H */
diff --git a/include/linux/unaligned/be_byteshift.h b/include/linux/unaligned/be_byteshift.h
new file mode 100644
index 0000000..9356b24
--- /dev/null
+++ b/include/linux/unaligned/be_byteshift.h
@@ -0,0 +1,70 @@
+#ifndef _LINUX_UNALIGNED_BE_BYTESHIFT_H
+#define _LINUX_UNALIGNED_BE_BYTESHIFT_H
+
+#include <linux/types.h>
+
+static inline u16 __get_unaligned_be16(const u8 *p)
+{
+	return p[0] << 8 | p[1];
+}
+
+static inline u32 __get_unaligned_be32(const u8 *p)
+{
+	return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3];
+}
+
+static inline u64 __get_unaligned_be64(const u8 *p)
+{
+	return (u64)__get_unaligned_be32(p) << 32 |
+	       __get_unaligned_be32(p + 4);
+}
+
+static inline void __put_unaligned_be16(u16 val, u8 *p)
+{
+	*p++ = val >> 8;
+	*p++ = val;
+}
+
+static inline void __put_unaligned_be32(u32 val, u8 *p)
+{
+	__put_unaligned_be16(val >> 16, p);
+	__put_unaligned_be16(val, p + 2);
+}
+
+static inline void __put_unaligned_be64(u64 val, u8 *p)
+{
+	__put_unaligned_be32(val >> 32, p);
+	__put_unaligned_be32(val, p + 4);
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+	return __get_unaligned_be16((const u8 *)p);
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+	return __get_unaligned_be32((const u8 *)p);
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+	return __get_unaligned_be64((const u8 *)p);
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+	__put_unaligned_be16(val, p);
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+	__put_unaligned_be32(val, p);
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+	__put_unaligned_be64(val, p);
+}
+
+#endif /* _LINUX_UNALIGNED_BE_BYTESHIFT_H */
diff --git a/include/linux/unaligned/generic.h b/include/linux/unaligned/generic.h
new file mode 100644
index 0000000..02d97ff
--- /dev/null
+++ b/include/linux/unaligned/generic.h
@@ -0,0 +1,68 @@
+#ifndef _LINUX_UNALIGNED_GENERIC_H
+#define _LINUX_UNALIGNED_GENERIC_H
+
+/*
+ * Cause a link-time error if we try an unaligned access other than
+ * 1,2,4 or 8 bytes long
+ */
+extern void __bad_unaligned_access_size(void);
+
+#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)),	\
+	__bad_unaligned_access_size()))));					\
+	}))
+
+#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)),	\
+	__bad_unaligned_access_size()))));					\
+	}))
+
+#define __put_unaligned_le(val, ptr) ({					\
+	void *__gu_p = (ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		*(u8 *)__gu_p = (__force u8)(val);			\
+		break;							\
+	case 2:								\
+		put_unaligned_le16((__force u16)(val), __gu_p);		\
+		break;							\
+	case 4:								\
+		put_unaligned_le32((__force u32)(val), __gu_p);		\
+		break;							\
+	case 8:								\
+		put_unaligned_le64((__force u64)(val), __gu_p);		\
+		break;							\
+	default:							\
+		__bad_unaligned_access_size();				\
+		break;							\
+	}								\
+	(void)0; })
+
+#define __put_unaligned_be(val, ptr) ({					\
+	void *__gu_p = (ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		*(u8 *)__gu_p = (__force u8)(val);			\
+		break;							\
+	case 2:								\
+		put_unaligned_be16((__force u16)(val), __gu_p);		\
+		break;							\
+	case 4:								\
+		put_unaligned_be32((__force u32)(val), __gu_p);		\
+		break;							\
+	case 8:								\
+		put_unaligned_be64((__force u64)(val), __gu_p);		\
+		break;							\
+	default:							\
+		__bad_unaligned_access_size();				\
+		break;							\
+	}								\
+	(void)0; })
+
+#endif /* _LINUX_UNALIGNED_GENERIC_H */
diff --git a/include/linux/unaligned/le_byteshift.h b/include/linux/unaligned/le_byteshift.h
new file mode 100644
index 0000000..be376fb
--- /dev/null
+++ b/include/linux/unaligned/le_byteshift.h
@@ -0,0 +1,70 @@
+#ifndef _LINUX_UNALIGNED_LE_BYTESHIFT_H
+#define _LINUX_UNALIGNED_LE_BYTESHIFT_H
+
+#include <linux/types.h>
+
+static inline u16 __get_unaligned_le16(const u8 *p)
+{
+	return p[0] | p[1] << 8;
+}
+
+static inline u32 __get_unaligned_le32(const u8 *p)
+{
+	return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
+}
+
+static inline u64 __get_unaligned_le64(const u8 *p)
+{
+	return (u64)__get_unaligned_le32(p + 4) << 32 |
+	       __get_unaligned_le32(p);
+}
+
+static inline void __put_unaligned_le16(u16 val, u8 *p)
+{
+	*p++ = val;
+	*p++ = val >> 8;
+}
+
+static inline void __put_unaligned_le32(u32 val, u8 *p)
+{
+	__put_unaligned_le16(val >> 16, p + 2);
+	__put_unaligned_le16(val, p);
+}
+
+static inline void __put_unaligned_le64(u64 val, u8 *p)
+{
+	__put_unaligned_le32(val >> 32, p + 4);
+	__put_unaligned_le32(val, p);
+}
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+	return __get_unaligned_le16((const u8 *)p);
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+	return __get_unaligned_le32((const u8 *)p);
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+	return __get_unaligned_le64((const u8 *)p);
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+	__put_unaligned_le16(val, p);
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+	__put_unaligned_le32(val, p);
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+	__put_unaligned_le64(val, p);
+}
+
+#endif /* _LINUX_UNALIGNED_LE_BYTESHIFT_H */
diff --git a/include/linux/usb/at91_udc.h b/include/linux/usb/at91_udc.h
new file mode 100644
index 0000000..541e2ba
--- /dev/null
+++ b/include/linux/usb/at91_udc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Platform data definitions for Atmel USBA gadget driver
+ * pieces copied from linux:include/linux/platform_data/atmel.h
+ */
+#ifndef __LINUX_USB_AT91_UDC_H__
+#define __LINUX_USB_AT91_UDC_H__
+
+struct at91_udc_data {
+	int	vbus_pin;		/* high == host powering us */
+	u8	vbus_active_low;	/* vbus polarity */
+	u8	vbus_polled;		/* Use polling, not interrupt */
+	int	pullup_pin;		/* active == D+ pulled up */
+	u8	pullup_active_low;	/* true == pullup_pin is active low */
+	unsigned long	baseaddr;
+};
+
+int at91_udc_probe(struct at91_udc_data *pdata);
+#endif /* __LINUX_USB_AT91_UDC_H__ */
diff --git a/include/linux/usb/atmel_usba_udc.h b/include/linux/usb/atmel_usba_udc.h
new file mode 100644
index 0000000..c1c8107
--- /dev/null
+++ b/include/linux/usb/atmel_usba_udc.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Platform data definitions for Atmel USBA gadget driver
+ * [Original from Linux kernel: include/linux/usb/atmel_usba_udc.h]
+ */
+#ifndef __LINUX_USB_USBA_H__
+#define __LINUX_USB_USBA_H__
+
+struct usba_ep_data {
+	char *name;
+	int index;
+	int fifo_size;
+	int nr_banks;
+	int can_dma;
+	int can_isoc;
+};
+
+struct usba_platform_data {
+	int			num_ep;
+	struct usba_ep_data	*ep;
+};
+
+extern int usba_udc_probe(struct usba_platform_data *pdata);
+
+#endif /* __LINUX_USB_USBA_H */
diff --git a/include/linux/usb/cdc.h b/include/linux/usb/cdc.h
new file mode 100644
index 0000000..442316b
--- /dev/null
+++ b/include/linux/usb/cdc.h
@@ -0,0 +1,224 @@
+/*
+ * USB Communications Device Class (CDC) definitions
+ *
+ * CDC says how to talk to lots of different types of network adapters,
+ * notably ethernet adapters and various modems.  It's used mostly with
+ * firmware based USB peripherals.
+ *
+ * Ported to U-Boot by: Thomas Smits <ts.smits@gmail.com> and
+ *                      Remy Bohmer <linux@bohmer.net>
+ */
+
+#define USB_CDC_SUBCLASS_ACM			0x02
+#define USB_CDC_SUBCLASS_ETHERNET		0x06
+#define USB_CDC_SUBCLASS_WHCM			0x08
+#define USB_CDC_SUBCLASS_DMM			0x09
+#define USB_CDC_SUBCLASS_MDLM			0x0a
+#define USB_CDC_SUBCLASS_OBEX			0x0b
+
+#define USB_CDC_PROTO_NONE			0
+
+#define USB_CDC_ACM_PROTO_AT_V25TER		1
+#define USB_CDC_ACM_PROTO_AT_PCCA101		2
+#define USB_CDC_ACM_PROTO_AT_PCCA101_WAKE	3
+#define USB_CDC_ACM_PROTO_AT_GSM		4
+#define USB_CDC_ACM_PROTO_AT_3G			5
+#define USB_CDC_ACM_PROTO_AT_CDMA		6
+#define USB_CDC_ACM_PROTO_VENDOR		0xff
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Class-Specific descriptors ... there are a couple dozen of them
+ */
+
+#define USB_CDC_HEADER_TYPE		0x00	/* header_desc */
+#define USB_CDC_CALL_MANAGEMENT_TYPE	0x01	/* call_mgmt_descriptor */
+#define USB_CDC_ACM_TYPE		0x02	/* acm_descriptor */
+#define USB_CDC_UNION_TYPE		0x06	/* union_desc */
+#define USB_CDC_COUNTRY_TYPE		0x07
+#define USB_CDC_NETWORK_TERMINAL_TYPE	0x0a	/* network_terminal_desc */
+#define USB_CDC_ETHERNET_TYPE		0x0f	/* ether_desc */
+#define USB_CDC_WHCM_TYPE		0x11
+#define USB_CDC_MDLM_TYPE		0x12	/* mdlm_desc */
+#define USB_CDC_MDLM_DETAIL_TYPE	0x13	/* mdlm_detail_desc */
+#define USB_CDC_DMM_TYPE		0x14
+#define USB_CDC_OBEX_TYPE		0x15
+
+/* "Header Functional Descriptor" from CDC spec  5.2.3.1 */
+struct usb_cdc_header_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__le16	bcdCDC;
+} __attribute__ ((packed));
+
+/* "Call Management Descriptor" from CDC spec  5.2.3.2 */
+struct usb_cdc_call_mgmt_descriptor {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	bmCapabilities;
+#define USB_CDC_CALL_MGMT_CAP_CALL_MGMT		0x01
+#define USB_CDC_CALL_MGMT_CAP_DATA_INTF		0x02
+
+	__u8	bDataInterface;
+} __attribute__ ((packed));
+
+/* "Abstract Control Management Descriptor" from CDC spec  5.2.3.3 */
+struct usb_cdc_acm_descriptor {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	bmCapabilities;
+} __attribute__ ((packed));
+
+/* capabilities from 5.2.3.3 */
+
+#define USB_CDC_COMM_FEATURE	0x01
+#define USB_CDC_CAP_LINE	0x02
+#define USB_CDC_CAP_BRK	0x04
+#define USB_CDC_CAP_NOTIFY	0x08
+
+/* "Union Functional Descriptor" from CDC spec 5.2.3.8 */
+struct usb_cdc_union_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	bMasterInterface0;
+	__u8	bSlaveInterface0;
+	/* ... and there could be other slave interfaces */
+} __attribute__ ((packed));
+
+/* "Country Selection Functional Descriptor" from CDC spec 5.2.3.9 */
+struct usb_cdc_country_functional_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	iCountryCodeRelDate;
+	__le16	wCountyCode0;
+	/* ... and there can be a lot of country codes */
+} __attribute__ ((packed));
+
+/* "Network Channel Terminal Functional Descriptor" from CDC spec 5.2.3.11 */
+struct usb_cdc_network_terminal_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	bEntityId;
+	__u8	iName;
+	__u8	bChannelIndex;
+	__u8	bPhysicalInterface;
+} __attribute__ ((packed));
+
+/* "Ethernet Networking Functional Descriptor" from CDC spec 5.2.3.16 */
+struct usb_cdc_ether_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	iMACAddress;
+	__le32	bmEthernetStatistics;
+	__le16	wMaxSegmentSize;
+	__le16	wNumberMCFilters;
+	__u8	bNumberPowerFilters;
+} __attribute__ ((packed));
+
+/* "MDLM Functional Descriptor" from CDC WMC spec 6.7.2.3 */
+struct usb_cdc_mdlm_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__le16	bcdVersion;
+	__u8	bGUID[16];
+} __attribute__ ((packed));
+
+/* "MDLM Detail Functional Descriptor" from CDC WMC spec 6.7.2.4 */
+struct usb_cdc_mdlm_detail_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	/* type is associated with mdlm_desc.bGUID */
+	__u8	bGuidDescriptorType;
+	__u8	bDetailData[0];
+} __attribute__ ((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Class-Specific Control Requests (6.2)
+ *
+ * section 3.6.2.1 table 4 has the ACM profile, for modems.
+ * section 3.8.2 table 10 has the ethernet profile.
+ *
+ * Microsoft's RNDIS stack for Ethernet is a vendor-specific CDC ACM variant,
+ * heavily dependent on the encapsulated (proprietary) command mechanism.
+ */
+
+#define USB_CDC_SEND_ENCAPSULATED_COMMAND	0x00
+#define USB_CDC_GET_ENCAPSULATED_RESPONSE	0x01
+#define USB_CDC_REQ_SET_LINE_CODING		0x20
+#define USB_CDC_REQ_GET_LINE_CODING		0x21
+#define USB_CDC_REQ_SET_CONTROL_LINE_STATE	0x22
+#define USB_CDC_REQ_SEND_BREAK			0x23
+#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS	0x40
+#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER	0x41
+#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER	0x42
+#define USB_CDC_SET_ETHERNET_PACKET_FILTER	0x43
+#define USB_CDC_GET_ETHERNET_STATISTIC		0x44
+
+/* Line Coding Structure from CDC spec 6.2.13 */
+struct usb_cdc_line_coding {
+	__le32	dwDTERate;
+	__u8	bCharFormat;
+#define USB_CDC_1_STOP_BITS			0
+#define USB_CDC_1_5_STOP_BITS			1
+#define USB_CDC_2_STOP_BITS			2
+
+	__u8	bParityType;
+#define USB_CDC_NO_PARITY			0
+#define USB_CDC_ODD_PARITY			1
+#define USB_CDC_EVEN_PARITY			2
+#define USB_CDC_MARK_PARITY			3
+#define USB_CDC_SPACE_PARITY			4
+
+	__u8	bDataBits;
+} __attribute__ ((packed));
+
+/* table 62; bits in multicast filter */
+#define	USB_CDC_PACKET_TYPE_PROMISCUOUS		(1 << 0)
+#define	USB_CDC_PACKET_TYPE_ALL_MULTICAST	(1 << 1) /* no filter */
+#define	USB_CDC_PACKET_TYPE_DIRECTED		(1 << 2)
+#define	USB_CDC_PACKET_TYPE_BROADCAST		(1 << 3)
+#define	USB_CDC_PACKET_TYPE_MULTICAST		(1 << 4) /* filtered */
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Class-Specific Notifications (6.3) sent by interrupt transfers
+ *
+ * section 3.8.2 table 11 of the CDC spec lists Ethernet notifications
+ * section 3.6.2.1 table 5 specifies ACM notifications, accepted by RNDIS
+ * RNDIS also defines its own bit-incompatible notifications
+ */
+
+#define USB_CDC_NOTIFY_NETWORK_CONNECTION	0x00
+#define USB_CDC_NOTIFY_RESPONSE_AVAILABLE	0x01
+#define USB_CDC_NOTIFY_SERIAL_STATE		0x20
+#define USB_CDC_NOTIFY_SPEED_CHANGE		0x2a
+
+struct usb_cdc_notification {
+	__u8	bmRequestType;
+	__u8	bNotificationType;
+	__le16	wValue;
+	__le16	wIndex;
+	__le16	wLength;
+} __attribute__ ((packed));
diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h
new file mode 100644
index 0000000..264c971
--- /dev/null
+++ b/include/linux/usb/ch9.h
@@ -0,0 +1,1063 @@
+/*
+ * This file holds USB constants and structures that are needed for
+ * USB device APIs.  These are used by the USB device model, which is
+ * defined in chapter 9 of the USB 2.0 specification and in the
+ * Wireless USB 1.0 (spread around).  Linux has several APIs in C that
+ * need these:
+ *
+ * - the master/host side Linux-USB kernel driver API;
+ * - the "usbfs" user space API; and
+ * - the Linux "gadget" slave/device/peripheral side driver API.
+ *
+ * USB 2.0 adds an additional "On The Go" (OTG) mode, which lets systems
+ * act either as a USB master/host or as a USB slave/device.  That means
+ * the master and slave side APIs benefit from working well together.
+ *
+ * There's also "Wireless USB", using low power short range radios for
+ * peripheral interconnection but otherwise building on the USB framework.
+ *
+ * Note all descriptors are declared '__attribute__((packed))' so that:
+ *
+ * [a] they never get padded, either internally (USB spec writers
+ *     probably handled that) or externally;
+ *
+ * [b] so that accessing bigger-than-a-bytes fields will never
+ *     generate bus errors on any platform, even when the location of
+ *     its descriptor inside a bundle isn't "naturally aligned", and
+ *
+ * [c] for consistency, removing all doubt even when it appears to
+ *     someone that the two other points are non-issues for that
+ *     particular descriptor type.
+ */
+
+#ifndef __LINUX_USB_CH9_H
+#define __LINUX_USB_CH9_H
+
+#include <linux/types.h>	/* __u8 etc */
+#include <asm/byteorder.h>	/* le16_to_cpu */
+#include <asm/unaligned.h>	/* get_unaligned() */
+
+/*-------------------------------------------------------------------------*/
+
+/* CONTROL REQUEST SUPPORT */
+
+/*
+ * USB directions
+ *
+ * This bit flag is used in endpoint descriptors' bEndpointAddress field.
+ * It's also one of three fields in control requests bRequestType.
+ */
+#define USB_DIR_OUT			0		/* to device */
+#define USB_DIR_IN			0x80		/* to host */
+
+/*
+ * USB types, the second of three bRequestType fields
+ */
+#define USB_TYPE_MASK			(0x03 << 5)
+#define USB_TYPE_STANDARD		(0x00 << 5)
+#define USB_TYPE_CLASS			(0x01 << 5)
+#define USB_TYPE_VENDOR			(0x02 << 5)
+#define USB_TYPE_RESERVED		(0x03 << 5)
+
+/*
+ * USB recipients, the third of three bRequestType fields
+ */
+#define USB_RECIP_MASK			0x1f
+#define USB_RECIP_DEVICE		0x00
+#define USB_RECIP_INTERFACE		0x01
+#define USB_RECIP_ENDPOINT		0x02
+#define USB_RECIP_OTHER			0x03
+/* From Wireless USB 1.0 */
+#define USB_RECIP_PORT			0x04
+#define USB_RECIP_RPIPE		0x05
+
+/*
+ * Standard requests, for the bRequest field of a SETUP packet.
+ *
+ * These are qualified by the bRequestType field, so that for example
+ * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
+ * by a GET_STATUS request.
+ */
+#define USB_REQ_GET_STATUS		0x00
+#define USB_REQ_CLEAR_FEATURE		0x01
+#define USB_REQ_SET_FEATURE		0x03
+#define USB_REQ_SET_ADDRESS		0x05
+#define USB_REQ_GET_DESCRIPTOR		0x06
+#define USB_REQ_SET_DESCRIPTOR		0x07
+#define USB_REQ_GET_CONFIGURATION	0x08
+#define USB_REQ_SET_CONFIGURATION	0x09
+#define USB_REQ_GET_INTERFACE		0x0A
+#define USB_REQ_SET_INTERFACE		0x0B
+#define USB_REQ_SYNCH_FRAME		0x0C
+#define USB_REQ_SET_SEL			0x30
+#define USB_REQ_SET_ISOCH_DELAY		0x31
+
+#define USB_REQ_SET_ENCRYPTION		0x0D	/* Wireless USB */
+#define USB_REQ_GET_ENCRYPTION		0x0E
+#define USB_REQ_RPIPE_ABORT		0x0E
+#define USB_REQ_SET_HANDSHAKE		0x0F
+#define USB_REQ_RPIPE_RESET		0x0F
+#define USB_REQ_GET_HANDSHAKE		0x10
+#define USB_REQ_SET_CONNECTION		0x11
+#define USB_REQ_SET_SECURITY_DATA	0x12
+#define USB_REQ_GET_SECURITY_DATA	0x13
+#define USB_REQ_SET_WUSB_DATA		0x14
+#define USB_REQ_LOOPBACK_DATA_WRITE	0x15
+#define USB_REQ_LOOPBACK_DATA_READ	0x16
+#define USB_REQ_SET_INTERFACE_DS	0x17
+
+/* The Link Power Management (LPM) ECN defines USB_REQ_TEST_AND_SET command,
+ * used by hubs to put ports into a new L1 suspend state, except that it
+ * forgot to define its number ...
+ */
+
+/*
+ * USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and
+ * are read as a bit array returned by USB_REQ_GET_STATUS.  (So there
+ * are at most sixteen features of each type.)  Hubs may also support a
+ * new USB_REQ_TEST_AND_SET_FEATURE to put ports into L1 suspend.
+ */
+#define USB_DEVICE_SELF_POWERED		0	/* (read only) */
+#define USB_DEVICE_REMOTE_WAKEUP	1	/* dev may initiate wakeup */
+#define USB_DEVICE_TEST_MODE		2	/* (wired high speed only) */
+#define USB_DEVICE_BATTERY		2	/* (wireless) */
+#define USB_DEVICE_B_HNP_ENABLE		3	/* (otg) dev may initiate HNP */
+#define USB_DEVICE_WUSB_DEVICE		3	/* (wireless)*/
+#define USB_DEVICE_A_HNP_SUPPORT	4	/* (otg) RH port supports HNP */
+#define USB_DEVICE_A_ALT_HNP_SUPPORT	5	/* (otg) other RH port does */
+#define USB_DEVICE_DEBUG_MODE		6	/* (special devices only) */
+
+/*
+ * Test Mode Selectors
+ * See USB 2.0 spec Table 9-7
+ */
+#define	TEST_J		1
+#define	TEST_K		2
+#define	TEST_SE0_NAK	3
+#define	TEST_PACKET	4
+#define	TEST_FORCE_EN	5
+
+/*
+ * New Feature Selectors as added by USB 3.0
+ * See USB 3.0 spec Table 9-6
+ */
+#define USB_DEVICE_U1_ENABLE	48	/* dev may initiate U1 transition */
+#define USB_DEVICE_U2_ENABLE	49	/* dev may initiate U2 transition */
+#define USB_DEVICE_LTM_ENABLE	50	/* dev may send LTM */
+#define USB_INTRF_FUNC_SUSPEND	0	/* function suspend */
+
+#define USB_INTR_FUNC_SUSPEND_OPT_MASK	0xFF00
+/*
+ * Suspend Options, Table 9-7 USB 3.0 spec
+ */
+#define USB_INTRF_FUNC_SUSPEND_LP	(1 << (8 + 0))
+#define USB_INTRF_FUNC_SUSPEND_RW	(1 << (8 + 1))
+
+#define USB_ENDPOINT_HALT		0	/* IN/OUT will STALL */
+
+/* Bit array elements as returned by the USB_REQ_GET_STATUS request. */
+#define USB_DEV_STAT_U1_ENABLED		2	/* transition into U1 state */
+#define USB_DEV_STAT_U2_ENABLED		3	/* transition into U2 state */
+#define USB_DEV_STAT_LTM_ENABLED	4	/* Latency tolerance messages */
+
+/**
+ * struct usb_ctrlrequest - SETUP data for a USB device control request
+ * @bRequestType: matches the USB bmRequestType field
+ * @bRequest: matches the USB bRequest field
+ * @wValue: matches the USB wValue field (le16 byte order)
+ * @wIndex: matches the USB wIndex field (le16 byte order)
+ * @wLength: matches the USB wLength field (le16 byte order)
+ *
+ * This structure is used to send control requests to a USB device.  It matches
+ * the different fields of the USB 2.0 Spec section 9.3, table 9-2.  See the
+ * USB spec for a fuller description of the different fields, and what they are
+ * used for.
+ *
+ * Note that the driver for any interface can issue control requests.
+ * For most devices, interfaces don't coordinate with each other, so
+ * such requests may be made at any time.
+ */
+struct usb_ctrlrequest {
+	__u8 bRequestType;
+	__u8 bRequest;
+	__le16 wValue;
+	__le16 wIndex;
+	__le16 wLength;
+} __attribute__ ((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * STANDARD DESCRIPTORS ... as returned by GET_DESCRIPTOR, or
+ * (rarely) accepted by SET_DESCRIPTOR.
+ *
+ * Note that all multi-byte values here are encoded in little endian
+ * byte order "on the wire".  Within the kernel and when exposed
+ * through the Linux-USB APIs, they are not converted to cpu byte
+ * order; it is the responsibility of the client code to do this.
+ * The single exception is when device and configuration descriptors (but
+ * not other descriptors) are read from usbfs (i.e. /proc/bus/usb/BBB/DDD);
+ * in this case the fields are converted to host endianness by the kernel.
+ */
+
+/*
+ * Descriptor types ... USB 2.0 spec table 9.5
+ */
+#define USB_DT_DEVICE			0x01
+#define USB_DT_CONFIG			0x02
+#define USB_DT_STRING			0x03
+#define USB_DT_INTERFACE		0x04
+#define USB_DT_ENDPOINT			0x05
+#define USB_DT_DEVICE_QUALIFIER		0x06
+#define USB_DT_OTHER_SPEED_CONFIG	0x07
+#define USB_DT_INTERFACE_POWER		0x08
+/* these are from a minor usb 2.0 revision (ECN) */
+#define USB_DT_OTG			0x09
+#define USB_DT_DEBUG			0x0a
+#define USB_DT_INTERFACE_ASSOCIATION	0x0b
+/* these are from the Wireless USB spec */
+#define USB_DT_SECURITY			0x0c
+#define USB_DT_KEY			0x0d
+#define USB_DT_ENCRYPTION_TYPE		0x0e
+#define USB_DT_BOS			0x0f
+#define USB_DT_DEVICE_CAPABILITY	0x10
+#define USB_DT_WIRELESS_ENDPOINT_COMP	0x11
+#define USB_DT_WIRE_ADAPTER		0x21
+#define USB_DT_RPIPE			0x22
+#define USB_DT_CS_RADIO_CONTROL		0x23
+/* From the T10 UAS specification */
+#define USB_DT_PIPE_USAGE		0x24
+/* From the USB 3.0 spec */
+#define	USB_DT_SS_ENDPOINT_COMP		0x30
+/* From HID 1.11 spec */
+#define USB_DT_HID_REPORT		0x22
+
+/* Conventional codes for class-specific descriptors.  The convention is
+ * defined in the USB "Common Class" Spec (3.11).  Individual class specs
+ * are authoritative for their usage, not the "common class" writeup.
+ */
+#define USB_DT_CS_DEVICE		(USB_TYPE_CLASS | USB_DT_DEVICE)
+#define USB_DT_CS_CONFIG		(USB_TYPE_CLASS | USB_DT_CONFIG)
+#define USB_DT_CS_STRING		(USB_TYPE_CLASS | USB_DT_STRING)
+#define USB_DT_CS_INTERFACE		(USB_TYPE_CLASS | USB_DT_INTERFACE)
+#define USB_DT_CS_ENDPOINT		(USB_TYPE_CLASS | USB_DT_ENDPOINT)
+
+/* All standard descriptors have these 2 fields at the beginning */
+struct usb_descriptor_header {
+	__u8  bLength;
+	__u8  bDescriptorType;
+} __attribute__ ((packed));
+
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_DEVICE: Device descriptor */
+struct usb_device_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 bcdUSB;
+	__u8  bDeviceClass;
+	__u8  bDeviceSubClass;
+	__u8  bDeviceProtocol;
+	__u8  bMaxPacketSize0;
+	__le16 idVendor;
+	__le16 idProduct;
+	__le16 bcdDevice;
+	__u8  iManufacturer;
+	__u8  iProduct;
+	__u8  iSerialNumber;
+	__u8  bNumConfigurations;
+} __attribute__ ((packed));
+
+#define USB_DT_DEVICE_SIZE		18
+
+
+/*
+ * Device and/or Interface Class codes
+ * as found in bDeviceClass or bInterfaceClass
+ * and defined by www.usb.org documents
+ */
+#define USB_CLASS_PER_INTERFACE		0	/* for DeviceClass */
+#define USB_CLASS_AUDIO			1
+#define USB_CLASS_COMM			2
+#define USB_CLASS_HID			3
+#define USB_CLASS_PHYSICAL		5
+#define USB_CLASS_STILL_IMAGE		6
+#define USB_CLASS_PRINTER		7
+#define USB_CLASS_MASS_STORAGE		8
+#define USB_CLASS_HUB			9
+#define USB_CLASS_CDC_DATA		0x0a
+#define USB_CLASS_CSCID			0x0b	/* chip+ smart card */
+#define USB_CLASS_CONTENT_SEC		0x0d	/* content security */
+#define USB_CLASS_VIDEO			0x0e
+#define USB_CLASS_WIRELESS_CONTROLLER	0xe0
+#define USB_CLASS_MISC			0xef
+#define USB_CLASS_APP_SPEC		0xfe
+#define USB_CLASS_VENDOR_SPEC		0xff
+
+#define USB_SUBCLASS_VENDOR_SPEC	0xff
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_CONFIG: Configuration descriptor information.
+ *
+ * USB_DT_OTHER_SPEED_CONFIG is the same descriptor, except that the
+ * descriptor type is different.  Highspeed-capable devices can look
+ * different depending on what speed they're currently running.  Only
+ * devices with a USB_DT_DEVICE_QUALIFIER have any OTHER_SPEED_CONFIG
+ * descriptors.
+ */
+struct usb_config_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 wTotalLength;
+	__u8  bNumInterfaces;
+	__u8  bConfigurationValue;
+	__u8  iConfiguration;
+	__u8  bmAttributes;
+	__u8  bMaxPower;
+} __attribute__ ((packed));
+
+#define USB_DT_CONFIG_SIZE		9
+
+/* from config descriptor bmAttributes */
+#define USB_CONFIG_ATT_ONE		(1 << 7)	/* must be set */
+#define USB_CONFIG_ATT_SELFPOWER	(1 << 6)	/* self powered */
+#define USB_CONFIG_ATT_WAKEUP		(1 << 5)	/* can wakeup */
+#define USB_CONFIG_ATT_BATTERY		(1 << 4)	/* battery powered */
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_STRING: String descriptor */
+struct usb_string_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 wData[1];		/* UTF-16LE encoded */
+} __attribute__ ((packed));
+
+/* note that "string" zero is special, it holds language codes that
+ * the device supports, not Unicode characters.
+ */
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_INTERFACE: Interface descriptor */
+struct usb_interface_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bInterfaceNumber;
+	__u8  bAlternateSetting;
+	__u8  bNumEndpoints;
+	__u8  bInterfaceClass;
+	__u8  bInterfaceSubClass;
+	__u8  bInterfaceProtocol;
+	__u8  iInterface;
+} __attribute__ ((packed));
+
+#define USB_DT_INTERFACE_SIZE		9
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_ENDPOINT: Endpoint descriptor */
+struct usb_endpoint_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bEndpointAddress;
+	__u8  bmAttributes;
+	__le16 wMaxPacketSize;
+	__u8  bInterval;
+
+	/* NOTE:  these two are _only_ in audio endpoints. */
+	/* use USB_DT_ENDPOINT*_SIZE in bLength, not sizeof. */
+	__u8  bRefresh;
+	__u8  bSynchAddress;
+} __attribute__ ((packed));
+
+#define USB_DT_ENDPOINT_SIZE		7
+#define USB_DT_ENDPOINT_AUDIO_SIZE	9	/* Audio extension */
+
+/* Used to access common fields */
+struct usb_generic_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+};
+
+struct __packed usb_class_hid_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;
+	u16 bcdCDC;
+	u8 bCountryCode;
+	u8 bNumDescriptors;	/* 0x01 */
+	u8 bDescriptorType0;
+	u16 wDescriptorLength0;
+	/* optional descriptors are not supported. */
+};
+
+struct __packed usb_class_report_descriptor {
+	u8 bLength;	/* dummy */
+	u8 bDescriptorType;
+	u16 wLength;
+	u8 bData[0];
+};
+
+/*
+ * Endpoints
+ */
+#define USB_ENDPOINT_NUMBER_MASK	0x0f	/* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK		0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK	0x03	/* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL	0
+#define USB_ENDPOINT_XFER_ISOC		1
+#define USB_ENDPOINT_XFER_BULK		2
+#define USB_ENDPOINT_XFER_INT		3
+#define USB_ENDPOINT_MAX_ADJUSTABLE	0x80
+
+#define USB_ENDPOINT_MAXP_MASK		0x07ff
+#define USB_EP_MAXP_MULT_SHIFT		11
+#define USB_EP_MAXP_MULT_MASK		(3 << USB_EP_MAXP_MULT_SHIFT)
+#define USB_EP_MAXP_MULT(m)		\
+	(((m) & USB_EP_MAXP_MULT_MASK) >> USB_EP_MAXP_MULT_SHIFT)
+
+/* The USB 3.0 spec redefines bits 5:4 of bmAttributes as interrupt ep type. */
+#define USB_ENDPOINT_INTRTYPE		0x30
+#define USB_ENDPOINT_INTR_PERIODIC	(0 << 4)
+#define USB_ENDPOINT_INTR_NOTIFICATION	(1 << 4)
+
+#define USB_ENDPOINT_SYNCTYPE		0x0c
+#define USB_ENDPOINT_SYNC_NONE		(0 << 2)
+#define USB_ENDPOINT_SYNC_ASYNC		(1 << 2)
+#define USB_ENDPOINT_SYNC_ADAPTIVE	(2 << 2)
+#define USB_ENDPOINT_SYNC_SYNC		(3 << 2)
+
+#define USB_ENDPOINT_USAGE_MASK		0x30
+#define USB_ENDPOINT_USAGE_DATA		0x00
+#define USB_ENDPOINT_USAGE_FEEDBACK	0x10
+#define USB_ENDPOINT_USAGE_IMPLICIT_FB	0x20	/* Implicit feedback Data endpoint */
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * usb_endpoint_num - get the endpoint's number
+ * @epd: endpoint to be checked
+ *
+ * Returns @epd's number: 0 to 15.
+ */
+static inline int usb_endpoint_num(const struct usb_endpoint_descriptor *epd)
+{
+	return epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+}
+
+/**
+ * usb_endpoint_type - get the endpoint's transfer type
+ * @epd: endpoint to be checked
+ *
+ * Returns one of USB_ENDPOINT_XFER_{CONTROL, ISOC, BULK, INT} according
+ * to @epd's transfer type.
+ */
+static inline int usb_endpoint_type(const struct usb_endpoint_descriptor *epd)
+{
+	return epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+}
+
+/**
+ * usb_endpoint_dir_in - check if the endpoint has IN direction
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type IN, otherwise it returns false.
+ */
+static inline int usb_endpoint_dir_in(const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN);
+}
+
+/**
+ * usb_endpoint_dir_out - check if the endpoint has OUT direction
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type OUT, otherwise it returns false.
+ */
+static inline int usb_endpoint_dir_out(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT);
+}
+
+/**
+ * usb_endpoint_xfer_bulk - check if the endpoint has bulk transfer type
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type bulk, otherwise it returns false.
+ */
+static inline int usb_endpoint_xfer_bulk(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
+		USB_ENDPOINT_XFER_BULK);
+}
+
+/**
+ * usb_endpoint_xfer_control - check if the endpoint has control transfer type
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type control, otherwise it returns false.
+ */
+static inline int usb_endpoint_xfer_control(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
+		USB_ENDPOINT_XFER_CONTROL);
+}
+
+/**
+ * usb_endpoint_xfer_int - check if the endpoint has interrupt transfer type
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type interrupt, otherwise it returns
+ * false.
+ */
+static inline int usb_endpoint_xfer_int(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
+		USB_ENDPOINT_XFER_INT);
+}
+
+/**
+ * usb_endpoint_xfer_isoc - check if the endpoint has isochronous transfer type
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type isochronous, otherwise it returns
+ * false.
+ */
+static inline int usb_endpoint_xfer_isoc(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
+		USB_ENDPOINT_XFER_ISOC);
+}
+
+/**
+ * usb_endpoint_is_bulk_in - check if the endpoint is bulk IN
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has bulk transfer type and IN direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_bulk_in(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_bulk(epd) && usb_endpoint_dir_in(epd);
+}
+
+/**
+ * usb_endpoint_is_bulk_out - check if the endpoint is bulk OUT
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has bulk transfer type and OUT direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_bulk_out(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_bulk(epd) && usb_endpoint_dir_out(epd);
+}
+
+/**
+ * usb_endpoint_is_int_in - check if the endpoint is interrupt IN
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has interrupt transfer type and IN direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_int_in(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_int(epd) && usb_endpoint_dir_in(epd);
+}
+
+/**
+ * usb_endpoint_is_int_out - check if the endpoint is interrupt OUT
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has interrupt transfer type and OUT direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_int_out(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_int(epd) && usb_endpoint_dir_out(epd);
+}
+
+/**
+ * usb_endpoint_is_isoc_in - check if the endpoint is isochronous IN
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has isochronous transfer type and IN direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_isoc_in(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_isoc(epd) && usb_endpoint_dir_in(epd);
+}
+
+/**
+ * usb_endpoint_is_isoc_out - check if the endpoint is isochronous OUT
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has isochronous transfer type and OUT direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_isoc_out(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_isoc(epd) && usb_endpoint_dir_out(epd);
+}
+
+/**
+ * usb_endpoint_maxp - get endpoint's max packet size
+ * @epd: endpoint to be checked
+ *
+ * Returns @epd's max packet
+ */
+static inline int usb_endpoint_maxp(const struct usb_endpoint_descriptor *epd)
+{
+	return __le16_to_cpu(get_unaligned(&epd->wMaxPacketSize));
+}
+
+/**
+ * usb_endpoint_maxp_mult - get endpoint's transactional opportunities
+ * @epd: endpoint to be checked
+ *
+ * Return @epd's wMaxPacketSize[12:11] + 1
+ */
+static inline int
+usb_endpoint_maxp_mult(const struct usb_endpoint_descriptor *epd)
+{
+	int maxp = __le16_to_cpu(epd->wMaxPacketSize);
+
+	return USB_EP_MAXP_MULT(maxp) + 1;
+}
+
+static inline int usb_endpoint_interrupt_type(
+		const struct usb_endpoint_descriptor *epd)
+{
+	return epd->bmAttributes & USB_ENDPOINT_INTRTYPE;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_SS_ENDPOINT_COMP: SuperSpeed Endpoint Companion descriptor */
+struct usb_ss_ep_comp_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bMaxBurst;
+	__u8  bmAttributes;
+	__le16 wBytesPerInterval;
+} __attribute__ ((packed));
+
+#define USB_DT_SS_EP_COMP_SIZE		6
+
+/* Bits 4:0 of bmAttributes if this is a bulk endpoint */
+static inline int
+usb_ss_max_streams(const struct usb_ss_ep_comp_descriptor *comp)
+{
+	int		max_streams;
+
+	if (!comp)
+		return 0;
+
+	max_streams = comp->bmAttributes & 0x1f;
+
+	if (!max_streams)
+		return 0;
+
+	max_streams = 1 << max_streams;
+
+	return max_streams;
+}
+
+/* Bits 1:0 of bmAttributes if this is an isoc endpoint */
+#define USB_SS_MULT(p)			(1 + ((p) & 0x3))
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_DEVICE_QUALIFIER: Device Qualifier descriptor */
+struct usb_qualifier_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 bcdUSB;
+	__u8  bDeviceClass;
+	__u8  bDeviceSubClass;
+	__u8  bDeviceProtocol;
+	__u8  bMaxPacketSize0;
+	__u8  bNumConfigurations;
+	__u8  bRESERVED;
+} __attribute__ ((packed));
+
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_OTG (from OTG 1.0a supplement) */
+struct usb_otg_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bmAttributes;	/* support for HNP, SRP, etc */
+} __attribute__ ((packed));
+
+/* from usb_otg_descriptor.bmAttributes */
+#define USB_OTG_SRP		(1 << 0)
+#define USB_OTG_HNP		(1 << 1)	/* swap host/device roles */
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_DEBUG:  for special highspeed devices, replacing serial console */
+struct usb_debug_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	/* bulk endpoints with 8 byte maxpacket */
+	__u8  bDebugInEndpoint;
+	__u8  bDebugOutEndpoint;
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_INTERFACE_ASSOCIATION: groups interfaces */
+struct usb_interface_assoc_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bFirstInterface;
+	__u8  bInterfaceCount;
+	__u8  bFunctionClass;
+	__u8  bFunctionSubClass;
+	__u8  bFunctionProtocol;
+	__u8  iFunction;
+} __attribute__ ((packed));
+
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_SECURITY:  group of wireless security descriptors, including
+ * encryption types available for setting up a CC/association.
+ */
+struct usb_security_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 wTotalLength;
+	__u8  bNumEncryptionTypes;
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_KEY:  used with {GET,SET}_SECURITY_DATA; only public keys
+ * may be retrieved.
+ */
+struct usb_key_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  tTKID[3];
+	__u8  bReserved;
+	__u8  bKeyData[0];
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_ENCRYPTION_TYPE:  bundled in DT_SECURITY groups */
+struct usb_encryption_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bEncryptionType;
+#define	USB_ENC_TYPE_UNSECURE		0
+#define	USB_ENC_TYPE_WIRED		1	/* non-wireless mode */
+#define	USB_ENC_TYPE_CCM_1		2	/* aes128/cbc session */
+#define	USB_ENC_TYPE_RSA_1		3	/* rsa3072/sha1 auth */
+	__u8  bEncryptionValue;		/* use in SET_ENCRYPTION */
+	__u8  bAuthKeyIndex;
+} __attribute__((packed));
+
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_BOS:  group of device-level capabilities */
+struct usb_bos_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 wTotalLength;
+	__u8  bNumDeviceCaps;
+} __attribute__((packed));
+
+#define USB_DT_BOS_SIZE		5
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_DEVICE_CAPABILITY:  grouped with BOS */
+struct usb_dev_cap_header {
+	__u8  bLength;
+	__u8  bDescriptorType;
+	__u8  bDevCapabilityType;
+} __attribute__((packed));
+
+#define	USB_CAP_TYPE_WIRELESS_USB	1
+
+struct usb_wireless_cap_descriptor {	/* Ultra Wide Band */
+	__u8  bLength;
+	__u8  bDescriptorType;
+	__u8  bDevCapabilityType;
+
+	__u8  bmAttributes;
+#define	USB_WIRELESS_P2P_DRD		(1 << 1)
+#define	USB_WIRELESS_BEACON_MASK	(3 << 2)
+#define	USB_WIRELESS_BEACON_SELF	(1 << 2)
+#define	USB_WIRELESS_BEACON_DIRECTED	(2 << 2)
+#define	USB_WIRELESS_BEACON_NONE	(3 << 2)
+	__le16 wPHYRates;	/* bit rates, Mbps */
+#define	USB_WIRELESS_PHY_53		(1 << 0)	/* always set */
+#define	USB_WIRELESS_PHY_80		(1 << 1)
+#define	USB_WIRELESS_PHY_107		(1 << 2)	/* always set */
+#define	USB_WIRELESS_PHY_160		(1 << 3)
+#define	USB_WIRELESS_PHY_200		(1 << 4)	/* always set */
+#define	USB_WIRELESS_PHY_320		(1 << 5)
+#define	USB_WIRELESS_PHY_400		(1 << 6)
+#define	USB_WIRELESS_PHY_480		(1 << 7)
+	__u8  bmTFITXPowerInfo;	/* TFI power levels */
+	__u8  bmFFITXPowerInfo;	/* FFI power levels */
+	__le16 bmBandGroup;
+	__u8  bReserved;
+} __attribute__((packed));
+
+/* USB 2.0 Extension descriptor */
+#define	USB_CAP_TYPE_EXT		2
+
+struct usb_ext_cap_descriptor {		/* Link Power Management */
+	__u8  bLength;
+	__u8  bDescriptorType;
+	__u8  bDevCapabilityType;
+	__le32 bmAttributes;
+#define USB_LPM_SUPPORT			(1 << 1)	/* supports LPM */
+#define USB_BESL_SUPPORT		(1 << 2)	/* supports BESL */
+#define USB_BESL_BASELINE_VALID		(1 << 3)	/* Baseline BESL valid*/
+#define USB_BESL_DEEP_VALID		(1 << 4)	/* Deep BESL valid */
+#define USB_GET_BESL_BASELINE(p)	(((p) & (0xf << 8)) >> 8)
+#define USB_GET_BESL_DEEP(p)		(((p) & (0xf << 12)) >> 12)
+} __attribute__((packed));
+
+#define USB_DT_USB_EXT_CAP_SIZE	7
+
+/*
+ * SuperSpeed USB Capability descriptor: Defines the set of SuperSpeed USB
+ * specific device level capabilities
+ */
+#define		USB_SS_CAP_TYPE		3
+struct usb_ss_cap_descriptor {		/* Link Power Management */
+	__u8  bLength;
+	__u8  bDescriptorType;
+	__u8  bDevCapabilityType;
+	__u8  bmAttributes;
+#define USB_LTM_SUPPORT			(1 << 1) /* supports LTM */
+	__le16 wSpeedSupported;
+#define USB_LOW_SPEED_OPERATION		(1)	 /* Low speed operation */
+#define USB_FULL_SPEED_OPERATION	(1 << 1) /* Full speed operation */
+#define USB_HIGH_SPEED_OPERATION	(1 << 2) /* High speed operation */
+#define USB_5GBPS_OPERATION		(1 << 3) /* Operation at 5Gbps */
+	__u8  bFunctionalitySupport;
+	__u8  bU1devExitLat;
+	__le16 bU2DevExitLat;
+} __attribute__((packed));
+
+#define USB_DT_USB_SS_CAP_SIZE	10
+
+/*
+ * Container ID Capability descriptor: Defines the instance unique ID used to
+ * identify the instance across all operating modes
+ */
+#define	CONTAINER_ID_TYPE	4
+struct usb_ss_container_id_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+	__u8  bDevCapabilityType;
+	__u8  bReserved;
+	__u8  ContainerID[16]; /* 128-bit number */
+} __attribute__((packed));
+
+#define USB_DT_USB_SS_CONTN_ID_SIZE	20
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_WIRELESS_ENDPOINT_COMP:  companion descriptor associated with
+ * each endpoint descriptor for a wireless device
+ */
+struct usb_wireless_ep_comp_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bMaxBurst;
+	__u8  bMaxSequence;
+	__le16 wMaxStreamDelay;
+	__le16 wOverTheAirPacketSize;
+	__u8  bOverTheAirInterval;
+	__u8  bmCompAttributes;
+#define USB_ENDPOINT_SWITCH_MASK	0x03	/* in bmCompAttributes */
+#define USB_ENDPOINT_SWITCH_NO		0
+#define USB_ENDPOINT_SWITCH_SWITCH	1
+#define USB_ENDPOINT_SWITCH_SCALE	2
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_REQ_SET_HANDSHAKE is a four-way handshake used between a wireless
+ * host and a device for connection set up, mutual authentication, and
+ * exchanging short lived session keys.  The handshake depends on a CC.
+ */
+struct usb_handshake {
+	__u8 bMessageNumber;
+	__u8 bStatus;
+	__u8 tTKID[3];
+	__u8 bReserved;
+	__u8 CDID[16];
+	__u8 nonce[16];
+	__u8 MIC[8];
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_REQ_SET_CONNECTION modifies or revokes a connection context (CC).
+ * A CC may also be set up using non-wireless secure channels (including
+ * wired USB!), and some devices may support CCs with multiple hosts.
+ */
+struct usb_connection_context {
+	__u8 CHID[16];		/* persistent host id */
+	__u8 CDID[16];		/* device id (unique w/in host context) */
+	__u8 CK[16];		/* connection key */
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB 2.0 defines three speeds, here's how Linux identifies them */
+
+enum usb_device_speed {
+	USB_SPEED_UNKNOWN = 0,			/* enumerating */
+	USB_SPEED_LOW, USB_SPEED_FULL,		/* usb 1.1 */
+	USB_SPEED_HIGH,				/* usb 2.0 */
+	USB_SPEED_WIRELESS,			/* wireless (usb 2.5) */
+	USB_SPEED_SUPER,			/* usb 3.0 */
+};
+
+#ifdef __KERNEL__
+
+/**
+ * usb_speed_string() - Returns human readable-name of the speed.
+ * @speed: The speed to return human-readable name for.  If it's not
+ *   any of the speeds defined in usb_device_speed enum, string for
+ *   USB_SPEED_UNKNOWN will be returned.
+ */
+extern const char *usb_speed_string(enum usb_device_speed speed);
+
+#endif
+
+enum usb_device_state {
+	/* NOTATTACHED isn't in the USB spec, and this state acts
+	 * the same as ATTACHED ... but it's clearer this way.
+	 */
+	USB_STATE_NOTATTACHED = 0,
+
+	/* chapter 9 and authentication (wireless) device states */
+	USB_STATE_ATTACHED,
+	USB_STATE_POWERED,			/* wired */
+	USB_STATE_RECONNECTING,			/* auth */
+	USB_STATE_UNAUTHENTICATED,		/* auth */
+	USB_STATE_DEFAULT,			/* limited function */
+	USB_STATE_ADDRESS,
+	USB_STATE_CONFIGURED,			/* most functions */
+
+	USB_STATE_SUSPENDED
+
+	/* NOTE:  there are actually four different SUSPENDED
+	 * states, returning to POWERED, DEFAULT, ADDRESS, or
+	 * CONFIGURED respectively when SOF tokens flow again.
+	 * At this level there's no difference between L1 and L2
+	 * suspend states.  (L2 being original USB 1.1 suspend.)
+	 */
+};
+
+enum usb3_link_state {
+	USB3_LPM_U0 = 0,
+	USB3_LPM_U1,
+	USB3_LPM_U2,
+	USB3_LPM_U3
+};
+
+/*
+ * A U1 timeout of 0x0 means the parent hub will reject any transitions to U1.
+ * 0xff means the parent hub will accept transitions to U1, but will not
+ * initiate a transition.
+ *
+ * A U1 timeout of 0x1 to 0x7F also causes the hub to initiate a transition to
+ * U1 after that many microseconds.  Timeouts of 0x80 to 0xFE are reserved
+ * values.
+ *
+ * A U2 timeout of 0x0 means the parent hub will reject any transitions to U2.
+ * 0xff means the parent hub will accept transitions to U2, but will not
+ * initiate a transition.
+ *
+ * A U2 timeout of 0x1 to 0xFE also causes the hub to initiate a transition to
+ * U2 after N*256 microseconds.  Therefore a U2 timeout value of 0x1 means a U2
+ * idle timer of 256 microseconds, 0x2 means 512 microseconds, 0xFE means
+ * 65.024ms.
+ */
+#define USB3_LPM_DISABLED		0x0
+#define USB3_LPM_U1_MAX_TIMEOUT		0x7F
+#define USB3_LPM_U2_MAX_TIMEOUT		0xFE
+#define USB3_LPM_DEVICE_INITIATED	0xFF
+
+struct usb_set_sel_req {
+	__u8	u1_sel;
+	__u8	u1_pel;
+	__le16	u2_sel;
+	__le16	u2_pel;
+} __attribute__ ((packed));
+
+/*
+ * The Set System Exit Latency control transfer provides one byte each for
+ * U1 SEL and U1 PEL, so the max exit latency is 0xFF.  U2 SEL and U2 PEL each
+ * are two bytes long.
+ */
+#define USB3_LPM_MAX_U1_SEL_PEL		0xFF
+#define USB3_LPM_MAX_U2_SEL_PEL		0xFFFF
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * As per USB compliance update, a device that is actively drawing
+ * more than 100mA from USB must report itself as bus-powered in
+ * the GetStatus(DEVICE) call.
+ * http://compliance.usb.org/index.asp?UpdateFile=Electrical&Format=Standard#34
+ */
+#define USB_SELF_POWER_VBUS_MAX_DRAW		100
+
+/**
+ * struct usb_string - wraps a C string and its USB id
+ * @id:the (nonzero) ID for this string
+ * @s:the string, in UTF-8 encoding
+ *
+ * If you're using usb_gadget_get_string(), use this to wrap a string
+ * together with its ID.
+ */
+struct usb_string {
+	u8 id;
+	const char *s;
+};
+
+#endif /* __LINUX_USB_CH9_H */
diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h
new file mode 100644
index 0000000..a49a66f
--- /dev/null
+++ b/include/linux/usb/composite.h
@@ -0,0 +1,346 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * composite.h -- framework for usb gadgets which are composite devices
+ *
+ * Copyright (C) 2006-2008 David Brownell
+ */
+
+#ifndef	__LINUX_USB_COMPOSITE_H
+#define	__LINUX_USB_COMPOSITE_H
+
+/*
+ * This framework is an optional layer on top of the USB Gadget interface,
+ * making it easier to build (a) Composite devices, supporting multiple
+ * functions within any single configuration, and (b) Multi-configuration
+ * devices, also supporting multiple functions but without necessarily
+ * having more than one function per configuration.
+ *
+ * Example:  a device with a single configuration supporting both network
+ * link and mass storage functions is a composite device.  Those functions
+ * might alternatively be packaged in individual configurations, but in
+ * the composite model the host can use both functions at the same time.
+ */
+
+#include <common.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/bitmap.h>
+
+/*
+ * USB function drivers should return USB_GADGET_DELAYED_STATUS if they
+ * wish to delay the data/status stages of the control transfer till they
+ * are ready. The control transfer will then be kept from completing till
+ * all the function drivers that requested for USB_GADGET_DELAYED_STAUS
+ * invoke usb_composite_setup_continue().
+ */
+#define	USB_GADGET_DELAYED_STATUS	0x7fff /* Impossibly large value */
+
+struct usb_configuration;
+
+/**
+ * struct usb_function - describes one function of a configuration
+ * @name: For diagnostics, identifies the function.
+ * @strings: tables of strings, keyed by identifiers assigned during bind()
+ *	and by language IDs provided in control requests
+ * @descriptors: Table of full (or low) speed descriptors, using interface and
+ *	string identifiers assigned during @bind().  If this pointer is null,
+ *	the function will not be available at full speed (or at low speed).
+ * @hs_descriptors: Table of high speed descriptors, using interface and
+ *	string identifiers assigned during @bind().  If this pointer is null,
+ *	the function will not be available at high speed.
+ * @config: assigned when @usb_add_function() is called; this is the
+ *	configuration with which this function is associated.
+ * @bind: Before the gadget can register, all of its functions bind() to the
+ *	available resources including string and interface identifiers used
+ *	in interface or class descriptors; endpoints; I/O buffers; and so on.
+ * @unbind: Reverses @bind; called as a side effect of unregistering the
+ *	driver which added this function.
+ * @set_alt: (REQUIRED) Reconfigures altsettings; function drivers may
+ *	initialize usb_ep.driver data at this time (when it is used).
+ *	Note that setting an interface to its current altsetting resets
+ *	interface state, and that all interfaces have a disabled state.
+ * @get_alt: Returns the active altsetting.  If this is not provided,
+ *	then only altsetting zero is supported.
+ * @disable: (REQUIRED) Indicates the function should be disabled.  Reasons
+ *	include host resetting or reconfiguring the gadget, and disconnection.
+ * @setup: Used for interface-specific control requests.
+ * @suspend: Notifies functions when the host stops sending USB traffic.
+ * @resume: Notifies functions when the host restarts USB traffic.
+ *
+ * A single USB function uses one or more interfaces, and should in most
+ * cases support operation at both full and high speeds.  Each function is
+ * associated by @usb_add_function() with a one configuration; that function
+ * causes @bind() to be called so resources can be allocated as part of
+ * setting up a gadget driver.  Those resources include endpoints, which
+ * should be allocated using @usb_ep_autoconfig().
+ *
+ * To support dual speed operation, a function driver provides descriptors
+ * for both high and full speed operation.  Except in rare cases that don't
+ * involve bulk endpoints, each speed needs different endpoint descriptors.
+ *
+ * Function drivers choose their own strategies for managing instance data.
+ * The simplest strategy just declares it "static', which means the function
+ * can only be activated once.  If the function needs to be exposed in more
+ * than one configuration at a given speed, it needs to support multiple
+ * usb_function structures (one for each configuration).
+ *
+ * A more complex strategy might encapsulate a @usb_function structure inside
+ * a driver-specific instance structure to allows multiple activations.  An
+ * example of multiple activations might be a CDC ACM function that supports
+ * two or more distinct instances within the same configuration, providing
+ * several independent logical data links to a USB host.
+ */
+struct usb_function {
+	const char			*name;
+	struct usb_gadget_strings	**strings;
+	struct usb_descriptor_header	**descriptors;
+	struct usb_descriptor_header	**hs_descriptors;
+
+	struct usb_configuration	*config;
+
+	/* REVISIT:  bind() functions can be marked __init, which
+	 * makes trouble for section mismatch analysis.  See if
+	 * we can't restructure things to avoid mismatching.
+	 * Related:  unbind() may kfree() but bind() won't...
+	 */
+
+	/* configuration management:  bind/unbind */
+	int			(*bind)(struct usb_configuration *,
+					struct usb_function *);
+	void			(*unbind)(struct usb_configuration *,
+					struct usb_function *);
+
+	/* runtime state management */
+	int			(*set_alt)(struct usb_function *,
+					unsigned interface, unsigned alt);
+	int			(*get_alt)(struct usb_function *,
+					unsigned interface);
+	void			(*disable)(struct usb_function *);
+	int			(*setup)(struct usb_function *,
+					const struct usb_ctrlrequest *);
+	void			(*suspend)(struct usb_function *);
+	void			(*resume)(struct usb_function *);
+
+	/* private: */
+	/* internals */
+	struct list_head		list;
+	DECLARE_BITMAP(endpoints, 32);
+};
+
+int usb_add_function(struct usb_configuration *, struct usb_function *);
+
+int usb_function_deactivate(struct usb_function *);
+int usb_function_activate(struct usb_function *);
+
+int usb_interface_id(struct usb_configuration *, struct usb_function *);
+
+/**
+ * ep_choose - select descriptor endpoint at current device speed
+ * @g: gadget, connected and running at some speed
+ * @hs: descriptor to use for high speed operation
+ * @fs: descriptor to use for full or low speed operation
+ */
+static inline struct usb_endpoint_descriptor *
+ep_choose(struct usb_gadget *g, struct usb_endpoint_descriptor *hs,
+		struct usb_endpoint_descriptor *fs)
+{
+	if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
+		return hs;
+	return fs;
+}
+
+#define	MAX_CONFIG_INTERFACES		16	/* arbitrary; max 255 */
+
+/**
+ * struct usb_configuration - represents one gadget configuration
+ * @label: For diagnostics, describes the configuration.
+ * @strings: Tables of strings, keyed by identifiers assigned during @bind()
+ *	and by language IDs provided in control requests.
+ * @descriptors: Table of descriptors preceding all function descriptors.
+ *	Examples include OTG and vendor-specific descriptors.
+ * @bind: Called from @usb_add_config() to allocate resources unique to this
+ *	configuration and to call @usb_add_function() for each function used.
+ * @unbind: Reverses @bind; called as a side effect of unregistering the
+ *	driver which added this configuration.
+ * @setup: Used to delegate control requests that aren't handled by standard
+ *	device infrastructure or directed at a specific interface.
+ * @bConfigurationValue: Copied into configuration descriptor.
+ * @iConfiguration: Copied into configuration descriptor.
+ * @bmAttributes: Copied into configuration descriptor.
+ * @bMaxPower: Copied into configuration descriptor.
+ * @cdev: assigned by @usb_add_config() before calling @bind(); this is
+ *	the device associated with this configuration.
+ *
+ * Configurations are building blocks for gadget drivers structured around
+ * function drivers.  Simple USB gadgets require only one function and one
+ * configuration, and handle dual-speed hardware by always providing the same
+ * functionality.  Slightly more complex gadgets may have more than one
+ * single-function configuration at a given speed; or have configurations
+ * that only work at one speed.
+ *
+ * Composite devices are, by definition, ones with configurations which
+ * include more than one function.
+ *
+ * The lifecycle of a usb_configuration includes allocation, initialization
+ * of the fields described above, and calling @usb_add_config() to set up
+ * internal data and bind it to a specific device.  The configuration's
+ * @bind() method is then used to initialize all the functions and then
+ * call @usb_add_function() for them.
+ *
+ * Those functions would normally be independant of each other, but that's
+ * not mandatory.  CDC WMC devices are an example where functions often
+ * depend on other functions, with some functions subsidiary to others.
+ * Such interdependency may be managed in any way, so long as all of the
+ * descriptors complete by the time the composite driver returns from
+ * its bind() routine.
+ */
+struct usb_configuration {
+	const char			*label;
+	struct usb_gadget_strings	**strings;
+	const struct usb_descriptor_header **descriptors;
+
+	/* REVISIT:  bind() functions can be marked __init, which
+	 * makes trouble for section mismatch analysis.  See if
+	 * we can't restructure things to avoid mismatching...
+	 */
+
+	/* configuration management:  bind/unbind */
+	int			(*bind)(struct usb_configuration *);
+	void			(*unbind)(struct usb_configuration *);
+	int			(*setup)(struct usb_configuration *,
+					const struct usb_ctrlrequest *);
+
+	/* fields in the config descriptor */
+	u8			bConfigurationValue;
+	u8			iConfiguration;
+	u8			bmAttributes;
+	u8			bMaxPower;
+
+	struct usb_composite_dev	*cdev;
+
+	/* private: */
+	/* internals */
+	struct list_head	list;
+	struct list_head	functions;
+	u8			next_interface_id;
+	unsigned		highspeed:1;
+	unsigned		fullspeed:1;
+	struct usb_function	*interface[MAX_CONFIG_INTERFACES];
+};
+
+int usb_add_config(struct usb_composite_dev *,
+		struct usb_configuration *);
+
+/**
+ * struct usb_composite_driver - groups configurations into a gadget
+ * @name: For diagnostics, identifies the driver.
+ * @dev: Template descriptor for the device, including default device
+ *	identifiers.
+ * @strings: tables of strings, keyed by identifiers assigned during bind()
+ *	and language IDs provided in control requests
+ * @bind: (REQUIRED) Used to allocate resources that are shared across the
+ *	whole device, such as string IDs, and add its configurations using
+ *	@usb_add_config().  This may fail by returning a negative errno
+ *	value; it should return zero on successful initialization.
+ * @unbind: Reverses @bind(); called as a side effect of unregistering
+ *	this driver.
+ * @disconnect: optional driver disconnect method
+ * @suspend: Notifies when the host stops sending USB traffic,
+ *	after function notifications
+ * @resume: Notifies configuration when the host restarts USB traffic,
+ *	before function notifications
+ *
+ * Devices default to reporting self powered operation.  Devices which rely
+ * on bus powered operation should report this in their @bind() method.
+ *
+ * Before returning from @bind, various fields in the template descriptor
+ * may be overridden.  These include the idVendor/idProduct/bcdDevice values
+ * normally to bind the appropriate host side driver, and the three strings
+ * (iManufacturer, iProduct, iSerialNumber) normally used to provide user
+ * meaningful device identifiers.  (The strings will not be defined unless
+ * they are defined in @dev and @strings.)  The correct ep0 maxpacket size
+ * is also reported, as defined by the underlying controller driver.
+ */
+struct usb_composite_driver {
+	const char				*name;
+	const struct usb_device_descriptor	*dev;
+	struct usb_gadget_strings		**strings;
+
+	/* REVISIT:  bind() functions can be marked __init, which
+	 * makes trouble for section mismatch analysis.  See if
+	 * we can't restructure things to avoid mismatching...
+	 */
+
+	int			(*bind)(struct usb_composite_dev *);
+	int			(*unbind)(struct usb_composite_dev *);
+
+	void			(*disconnect)(struct usb_composite_dev *);
+
+	/* global suspend hooks */
+	void			(*suspend)(struct usb_composite_dev *);
+	void			(*resume)(struct usb_composite_dev *);
+};
+
+extern int usb_composite_register(struct usb_composite_driver *);
+extern void usb_composite_unregister(struct usb_composite_driver *);
+
+
+/**
+ * struct usb_composite_device - represents one composite usb gadget
+ * @gadget: read-only, abstracts the gadget's usb peripheral controller
+ * @req: used for control responses; buffer is pre-allocated
+ * @bufsiz: size of buffer pre-allocated in @req
+ * @config: the currently active configuration
+ *
+ * One of these devices is allocated and initialized before the
+ * associated device driver's bind() is called.
+ *
+ * OPEN ISSUE:  it appears that some WUSB devices will need to be
+ * built by combining a normal (wired) gadget with a wireless one.
+ * This revision of the gadget framework should probably try to make
+ * sure doing that won't hurt too much.
+ *
+ * One notion for how to handle Wireless USB devices involves:
+ * (a) a second gadget here, discovery mechanism TBD, but likely
+ *     needing separate "register/unregister WUSB gadget" calls;
+ * (b) updates to usb_gadget to include flags "is it wireless",
+ *     "is it wired", plus (presumably in a wrapper structure)
+ *     bandgroup and PHY info;
+ * (c) presumably a wireless_ep wrapping a usb_ep, and reporting
+ *     wireless-specific parameters like maxburst and maxsequence;
+ * (d) configurations that are specific to wireless links;
+ * (e) function drivers that understand wireless configs and will
+ *     support wireless for (additional) function instances;
+ * (f) a function to support association setup (like CBAF), not
+ *     necessarily requiring a wireless adapter;
+ * (g) composite device setup that can create one or more wireless
+ *     configs, including appropriate association setup support;
+ * (h) more, TBD.
+ */
+struct usb_composite_dev {
+	struct usb_gadget		*gadget;
+	struct usb_request		*req;
+	unsigned			bufsiz;
+
+	struct usb_configuration	*config;
+
+	/* private: */
+	/* internals */
+	unsigned int			suspended:1;
+	struct usb_device_descriptor __aligned(CONFIG_SYS_CACHELINE_SIZE) desc;
+	struct list_head		configs;
+	struct usb_composite_driver	*driver;
+	u8				next_string_id;
+
+	/* the gadget driver won't enable the data pullup
+	 * while the deactivation count is nonzero.
+	 */
+	unsigned			deactivations;
+};
+
+extern int usb_string_id(struct usb_composite_dev *c);
+extern int usb_string_ids_tab(struct usb_composite_dev *c,
+			      struct usb_string *str);
+extern int usb_string_ids_n(struct usb_composite_dev *c, unsigned n);
+
+#endif	/* __LINUX_USB_COMPOSITE_H */
diff --git a/include/linux/usb/dwc3-omap.h b/include/linux/usb/dwc3-omap.h
new file mode 100644
index 0000000..62180e3
--- /dev/null
+++ b/include/linux/usb/dwc3-omap.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* include/linux/usb/dwc3-omap.h
+ *
+ * Copyright (c) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Designware SuperSpeed Glue
+ */
+
+#ifndef __DWC3_OMAP_H_
+#define __DWC3_OMAP_H_
+
+enum dwc3_omap_utmi_mode {
+	DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
+	DWC3_OMAP_UTMI_MODE_HW,
+	DWC3_OMAP_UTMI_MODE_SW,
+};
+
+#endif /* __DWC3_OMAP_H_ */
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
new file mode 100644
index 0000000..9ceee0a
--- /dev/null
+++ b/include/linux/usb/dwc3.h
@@ -0,0 +1,223 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* include/linux/usb/dwc3.h
+ *
+ * Copyright (c) 2012 Samsung Electronics Co. Ltd
+ *
+ * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
+ */
+
+#ifndef __DWC3_H_
+#define __DWC3_H_
+
+/* Global constants */
+#define DWC3_ENDPOINTS_NUM			32
+
+#define DWC3_EVENT_BUFFERS_SIZE			PAGE_SIZE
+#define DWC3_EVENT_TYPE_MASK			0xfe
+
+#define DWC3_EVENT_TYPE_DEV			0
+#define DWC3_EVENT_TYPE_CARKIT			3
+#define DWC3_EVENT_TYPE_I2C			4
+
+#define DWC3_DEVICE_EVENT_DISCONNECT		0
+#define DWC3_DEVICE_EVENT_RESET			1
+#define DWC3_DEVICE_EVENT_CONNECT_DONE		2
+#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
+#define DWC3_DEVICE_EVENT_WAKEUP		4
+#define DWC3_DEVICE_EVENT_EOPF			6
+#define DWC3_DEVICE_EVENT_SOF			7
+#define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
+#define DWC3_DEVICE_EVENT_CMD_CMPL		10
+#define DWC3_DEVICE_EVENT_OVERFLOW		11
+
+#define DWC3_GEVNTCOUNT_MASK			0xfffc
+#define DWC3_GSNPSID_MASK			0xffff0000
+#define DWC3_GSNPSID_SHIFT			16
+#define DWC3_GSNPSREV_MASK			0xffff
+
+#define DWC3_REVISION_MASK			0xffff
+
+#define DWC3_REG_OFFSET				0xC100
+
+struct g_event_buffer {
+	u32 g_evntadrlo;
+	u32 g_evntadrhi;
+	u32 g_evntsiz;
+	u32 g_evntcount;
+};
+
+struct d_physical_endpoint {
+	u32 d_depcmdpar2;
+	u32 d_depcmdpar1;
+	u32 d_depcmdpar0;
+	u32 d_depcmd;
+};
+
+struct dwc3 {					/* offset: 0xC100 */
+	u32 g_sbuscfg0;
+	u32 g_sbuscfg1;
+	u32 g_txthrcfg;
+	u32 g_rxthrcfg;
+	u32 g_ctl;
+
+	u32 reserved1;
+
+	u32 g_sts;
+
+	u32 reserved2;
+
+	u32 g_snpsid;
+	u32 g_gpio;
+	u32 g_uid;
+	u32 g_uctl;
+	u64 g_buserraddr;
+	u64 g_prtbimap;
+
+	u32 g_hwparams0;
+	u32 g_hwparams1;
+	u32 g_hwparams2;
+	u32 g_hwparams3;
+	u32 g_hwparams4;
+	u32 g_hwparams5;
+	u32 g_hwparams6;
+	u32 g_hwparams7;
+
+	u32 g_dbgfifospace;
+	u32 g_dbgltssm;
+	u32 g_dbglnmcc;
+	u32 g_dbgbmu;
+	u32 g_dbglspmux;
+	u32 g_dbglsp;
+	u32 g_dbgepinfo0;
+	u32 g_dbgepinfo1;
+
+	u64 g_prtbimap_hs;
+	u64 g_prtbimap_fs;
+
+	u32 reserved3[28];
+
+	u32 g_usb2phycfg[16];
+	u32 g_usb2i2cctl[16];
+	u32 g_usb2phyacc[16];
+	u32 g_usb3pipectl[16];
+
+	u32 g_txfifosiz[32];
+	u32 g_rxfifosiz[32];
+
+	struct g_event_buffer g_evnt_buf[32];
+
+	u32 g_hwparams8;
+
+	u32 reserved4[11];
+
+	u32 g_fladj;
+
+	u32 reserved5[51];
+
+	u32 d_cfg;
+	u32 d_ctl;
+	u32 d_evten;
+	u32 d_sts;
+	u32 d_gcmdpar;
+	u32 d_gcmd;
+
+	u32 reserved6[2];
+
+	u32 d_alepena;
+
+	u32 reserved7[55];
+
+	struct d_physical_endpoint d_phy_ep_cmd[32];
+
+	u32 reserved8[128];
+
+	u32 o_cfg;
+	u32 o_ctl;
+	u32 o_evt;
+	u32 o_evten;
+	u32 o_sts;
+
+	u32 reserved9[3];
+
+	u32 adp_cfg;
+	u32 adp_ctl;
+	u32 adp_evt;
+	u32 adp_evten;
+
+	u32 bc_cfg;
+
+	u32 reserved10;
+
+	u32 bc_evt;
+	u32 bc_evten;
+};
+
+/* Global Configuration Register */
+#define DWC3_GCTL_PWRDNSCALE(n)			((n) << 19)
+#define DWC3_GCTL_U2RSTECN			(1 << 16)
+#define DWC3_GCTL_RAMCLKSEL(x)			\
+		(((x) & DWC3_GCTL_CLK_MASK) << 6)
+#define DWC3_GCTL_CLK_BUS			(0)
+#define DWC3_GCTL_CLK_PIPE			(1)
+#define DWC3_GCTL_CLK_PIPEHALF			(2)
+#define DWC3_GCTL_CLK_MASK			(3)
+#define DWC3_GCTL_PRTCAP(n)			(((n) & (3 << 12)) >> 12)
+#define DWC3_GCTL_PRTCAPDIR(n)			((n) << 12)
+#define DWC3_GCTL_PRTCAP_HOST			1
+#define DWC3_GCTL_PRTCAP_DEVICE			2
+#define DWC3_GCTL_PRTCAP_OTG			3
+#define DWC3_GCTL_CORESOFTRESET			(1 << 11)
+#define DWC3_GCTL_SCALEDOWN(n)			((n) << 4)
+#define DWC3_GCTL_SCALEDOWN_MASK		DWC3_GCTL_SCALEDOWN(3)
+#define DWC3_GCTL_DISSCRAMBLE			(1 << 3)
+#define DWC3_GCTL_DSBLCLKGTNG			(1 << 0)
+
+/* Global HWPARAMS1 Register */
+#define DWC3_GHWPARAMS1_EN_PWROPT(n)		(((n) & (3 << 24)) >> 24)
+#define DWC3_GHWPARAMS1_EN_PWROPT_NO		0
+#define DWC3_GHWPARAMS1_EN_PWROPT_CLK		1
+
+/* Global USB2 PHY Configuration Register */
+#define DWC3_GUSB2PHYCFG_PHYSOFTRST		(1 << 31)
+#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
+#define DWC3_GUSB2PHYCFG_ENBLSLPM		(1 << 8)
+#define DWC3_GUSB2PHYCFG_SUSPHY			(1 << 6)
+#define DWC3_GUSB2PHYCFG_PHYIF			(1 << 3)
+
+/* Global USB2 PHY Configuration Mask */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK		(0xf << 10)
+
+/* Global USB2 PHY Configuration Offset */
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET	10
+
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
+		DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
+		DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
+
+/* Global USB3 PIPE Control Register */
+#define DWC3_GUSB3PIPECTL_PHYSOFTRST		(1 << 31)
+#define DWC3_GUSB3PIPECTL_DISRXDETP3		(1 << 28)
+#define DWC3_GUSB3PIPECTL_SUSPHY		(1 << 17)
+
+/* Global TX Fifo Size Register */
+#define DWC3_GTXFIFOSIZ_TXFDEF(n)		((n) & 0xffff)
+#define DWC3_GTXFIFOSIZ_TXFSTADDR(n)		((n) & 0xffff0000)
+
+/* Device Control Register */
+#define DWC3_DCTL_RUN_STOP			(1 << 31)
+#define DWC3_DCTL_CSFTRST			(1 << 30)
+#define DWC3_DCTL_LSFTRST			(1 << 29)
+
+/* Global Frame Length Adjustment Register */
+#define GFLADJ_30MHZ_REG_SEL			(1 << 7)
+#define GFLADJ_30MHZ(n)				((n) & 0x3f)
+#define GFLADJ_30MHZ_DEFAULT			0x20
+
+#ifdef CONFIG_USB_XHCI_DWC3
+void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
+void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
+int dwc3_core_init(struct dwc3 *dwc3_reg);
+void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
+#endif
+#endif /* __DWC3_H_ */
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
new file mode 100644
index 0000000..497798a
--- /dev/null
+++ b/include/linux/usb/gadget.h
@@ -0,0 +1,947 @@
+/*
+ * <linux/usb/gadget.h>
+ *
+ * We call the USB code inside a Linux-based peripheral device a "gadget"
+ * driver, except for the hardware-specific bus glue.  One USB host can
+ * master many USB gadgets, but the gadgets are only slaved to one host.
+ *
+ *
+ * (C) Copyright 2002-2004 by David Brownell
+ * All Rights Reserved.
+ *
+ * This software is licensed under the GNU GPL version 2.
+ *
+ * Ported to U-Boot by: Thomas Smits <ts.smits@gmail.com> and
+ *                      Remy Bohmer <linux@bohmer.net>
+ */
+
+#ifndef __LINUX_USB_GADGET_H
+#define __LINUX_USB_GADGET_H
+
+#include <errno.h>
+#include <usb.h>
+#include <linux/compat.h>
+#include <linux/list.h>
+
+struct usb_ep;
+
+/**
+ * struct usb_request - describes one i/o request
+ * @buf: Buffer used for data.  Always provide this; some controllers
+ *	only use PIO, or don't use DMA for some endpoints.
+ * @dma: DMA address corresponding to 'buf'.  If you don't set this
+ *	field, and the usb controller needs one, it is responsible
+ *	for mapping and unmapping the buffer.
+ * @stream_id: The stream id, when USB3.0 bulk streams are being used
+ * @length: Length of that data
+ * @no_interrupt: If true, hints that no completion irq is needed.
+ *	Helpful sometimes with deep request queues that are handled
+ *	directly by DMA controllers.
+ * @zero: If true, when writing data, makes the last packet be "short"
+ *     by adding a zero length packet as needed;
+ * @short_not_ok: When reading data, makes short packets be
+ *     treated as errors (queue stops advancing till cleanup).
+ * @complete: Function called when request completes, so this request and
+ *	its buffer may be re-used.
+ *	Reads terminate with a short packet, or when the buffer fills,
+ *	whichever comes first.  When writes terminate, some data bytes
+ *	will usually still be in flight (often in a hardware fifo).
+ *	Errors (for reads or writes) stop the queue from advancing
+ *	until the completion function returns, so that any transfers
+ *	invalidated by the error may first be dequeued.
+ * @context: For use by the completion callback
+ * @list: For use by the gadget driver.
+ * @status: Reports completion code, zero or a negative errno.
+ *	Normally, faults block the transfer queue from advancing until
+ *	the completion callback returns.
+ *	Code "-ESHUTDOWN" indicates completion caused by device disconnect,
+ *	or when the driver disabled the endpoint.
+ * @actual: Reports bytes transferred to/from the buffer.  For reads (OUT
+ *	transfers) this may be less than the requested length.  If the
+ *	short_not_ok flag is set, short reads are treated as errors
+ *	even when status otherwise indicates successful completion.
+ *	Note that for writes (IN transfers) some data bytes may still
+ *	reside in a device-side FIFO when the request is reported as
+ *	complete.
+ *
+ * These are allocated/freed through the endpoint they're used with.  The
+ * hardware's driver can add extra per-request data to the memory it returns,
+ * which often avoids separate memory allocations (potential failures),
+ * later when the request is queued.
+ *
+ * Request flags affect request handling, such as whether a zero length
+ * packet is written (the "zero" flag), whether a short read should be
+ * treated as an error (blocking request queue advance, the "short_not_ok"
+ * flag), or hinting that an interrupt is not required (the "no_interrupt"
+ * flag, for use with deep request queues).
+ *
+ * Bulk endpoints can use any size buffers, and can also be used for interrupt
+ * transfers. interrupt-only endpoints can be much less functional.
+ *
+ * NOTE:  this is analagous to 'struct urb' on the host side, except that
+ * it's thinner and promotes more pre-allocation.
+ */
+
+struct usb_request {
+	void			*buf;
+	unsigned		length;
+	dma_addr_t		dma;
+
+	unsigned		stream_id:16;
+	unsigned		no_interrupt:1;
+	unsigned		zero:1;
+	unsigned		short_not_ok:1;
+
+	void			(*complete)(struct usb_ep *ep,
+					struct usb_request *req);
+	void			*context;
+	struct list_head	list;
+
+	int			status;
+	unsigned		actual;
+};
+
+/*-------------------------------------------------------------------------*/
+
+/* endpoint-specific parts of the api to the usb controller hardware.
+ * unlike the urb model, (de)multiplexing layers are not required.
+ * (so this api could slash overhead if used on the host side...)
+ *
+ * note that device side usb controllers commonly differ in how many
+ * endpoints they support, as well as their capabilities.
+ */
+struct usb_ep_ops {
+	int (*enable) (struct usb_ep *ep,
+		const struct usb_endpoint_descriptor *desc);
+	int (*disable) (struct usb_ep *ep);
+
+	struct usb_request *(*alloc_request) (struct usb_ep *ep,
+		gfp_t gfp_flags);
+	void (*free_request) (struct usb_ep *ep, struct usb_request *req);
+
+	int (*queue) (struct usb_ep *ep, struct usb_request *req,
+		gfp_t gfp_flags);
+	int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
+
+	int (*set_halt) (struct usb_ep *ep, int value);
+	int (*set_wedge)(struct usb_ep *ep);
+	int (*fifo_status) (struct usb_ep *ep);
+	void (*fifo_flush) (struct usb_ep *ep);
+};
+
+/**
+ * struct usb_ep - device side representation of USB endpoint
+ * @name:identifier for the endpoint, such as "ep-a" or "ep9in-bulk"
+ * @ops: Function pointers used to access hardware-specific operations.
+ * @ep_list:the gadget's ep_list holds all of its endpoints
+ * @maxpacket:The maximum packet size used on this endpoint.  The initial
+ *	value can sometimes be reduced (hardware allowing), according to
+ *      the endpoint descriptor used to configure the endpoint.
+ * @maxpacket_limit:The maximum packet size value which can be handled by this
+ *	endpoint. It's set once by UDC driver when endpoint is initialized, and
+ *	should not be changed. Should not be confused with maxpacket.
+ * @max_streams: The maximum number of streams supported
+ * 	by this EP (0 - 16, actual number is 2^n)
+ * @maxburst: the maximum number of bursts supported by this EP (for usb3)
+ * @driver_data:for use by the gadget driver.  all other fields are
+ *	read-only to gadget drivers.
+ * @desc: endpoint descriptor.  This pointer is set before the endpoint is
+ * 	enabled and remains valid until the endpoint is disabled.
+ * @comp_desc: In case of SuperSpeed support, this is the endpoint companion
+ * 	descriptor that is used to configure the endpoint
+ *
+ * the bus controller driver lists all the general purpose endpoints in
+ * gadget->ep_list.  the control endpoint (gadget->ep0) is not in that list,
+ * and is accessed only in response to a driver setup() callback.
+ */
+struct usb_ep {
+	void			*driver_data;
+	const char		*name;
+	const struct usb_ep_ops	*ops;
+	struct list_head	ep_list;
+	unsigned		maxpacket:16;
+	unsigned		maxpacket_limit:16;
+	unsigned		max_streams:16;
+	unsigned		maxburst:5;
+	const struct usb_endpoint_descriptor	*desc;
+	const struct usb_ss_ep_comp_descriptor	*comp_desc;
+};
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * usb_ep_set_maxpacket_limit - set maximum packet size limit for endpoint
+ * @ep:the endpoint being configured
+ * @maxpacket_limit:value of maximum packet size limit
+ *
+ * This function shoud be used only in UDC drivers to initialize endpoint
+ * (usually in probe function).
+ */
+static inline void usb_ep_set_maxpacket_limit(struct usb_ep *ep,
+					      unsigned maxpacket_limit)
+{
+	ep->maxpacket_limit = maxpacket_limit;
+	ep->maxpacket = maxpacket_limit;
+}
+
+/**
+ * usb_ep_enable - configure endpoint, making it usable
+ * @ep:the endpoint being configured.  may not be the endpoint named "ep0".
+ *	drivers discover endpoints through the ep_list of a usb_gadget.
+ * @desc:descriptor for desired behavior.  caller guarantees this pointer
+ *	remains valid until the endpoint is disabled; the data byte order
+ *	is little-endian (usb-standard).
+ *
+ * when configurations are set, or when interface settings change, the driver
+ * will enable or disable the relevant endpoints.  while it is enabled, an
+ * endpoint may be used for i/o until the driver receives a disconnect() from
+ * the host or until the endpoint is disabled.
+ *
+ * the ep0 implementation (which calls this routine) must ensure that the
+ * hardware capabilities of each endpoint match the descriptor provided
+ * for it.  for example, an endpoint named "ep2in-bulk" would be usable
+ * for interrupt transfers as well as bulk, but it likely couldn't be used
+ * for iso transfers or for endpoint 14.  some endpoints are fully
+ * configurable, with more generic names like "ep-a".  (remember that for
+ * USB, "in" means "towards the USB master".)
+ *
+ * returns zero, or a negative error code.
+ */
+static inline int usb_ep_enable(struct usb_ep *ep,
+				const struct usb_endpoint_descriptor *desc)
+{
+	return ep->ops->enable(ep, desc);
+}
+
+/**
+ * usb_ep_disable - endpoint is no longer usable
+ * @ep:the endpoint being unconfigured.  may not be the endpoint named "ep0".
+ *
+ * no other task may be using this endpoint when this is called.
+ * any pending and uncompleted requests will complete with status
+ * indicating disconnect (-ESHUTDOWN) before this call returns.
+ * gadget drivers must call usb_ep_enable() again before queueing
+ * requests to the endpoint.
+ *
+ * returns zero, or a negative error code.
+ */
+static inline int usb_ep_disable(struct usb_ep *ep)
+{
+	return ep->ops->disable(ep);
+}
+
+/**
+ * usb_ep_alloc_request - allocate a request object to use with this endpoint
+ * @ep:the endpoint to be used with with the request
+ * @gfp_flags:GFP_* flags to use
+ *
+ * Request objects must be allocated with this call, since they normally
+ * need controller-specific setup and may even need endpoint-specific
+ * resources such as allocation of DMA descriptors.
+ * Requests may be submitted with usb_ep_queue(), and receive a single
+ * completion callback.  Free requests with usb_ep_free_request(), when
+ * they are no longer needed.
+ *
+ * Returns the request, or null if one could not be allocated.
+ */
+static inline struct usb_request *usb_ep_alloc_request(struct usb_ep *ep,
+						       gfp_t gfp_flags)
+{
+	return ep->ops->alloc_request(ep, gfp_flags);
+}
+
+/**
+ * usb_ep_free_request - frees a request object
+ * @ep:the endpoint associated with the request
+ * @req:the request being freed
+ *
+ * Reverses the effect of usb_ep_alloc_request().
+ * Caller guarantees the request is not queued, and that it will
+ * no longer be requeued (or otherwise used).
+ */
+static inline void usb_ep_free_request(struct usb_ep *ep,
+				       struct usb_request *req)
+{
+	ep->ops->free_request(ep, req);
+}
+
+/**
+ * usb_ep_queue - queues (submits) an I/O request to an endpoint.
+ * @ep:the endpoint associated with the request
+ * @req:the request being submitted
+ * @gfp_flags: GFP_* flags to use in case the lower level driver couldn't
+ *	pre-allocate all necessary memory with the request.
+ *
+ * This tells the device controller to perform the specified request through
+ * that endpoint (reading or writing a buffer).  When the request completes,
+ * including being canceled by usb_ep_dequeue(), the request's completion
+ * routine is called to return the request to the driver.  Any endpoint
+ * (except control endpoints like ep0) may have more than one transfer
+ * request queued; they complete in FIFO order.  Once a gadget driver
+ * submits a request, that request may not be examined or modified until it
+ * is given back to that driver through the completion callback.
+ *
+ * Each request is turned into one or more packets.  The controller driver
+ * never merges adjacent requests into the same packet.  OUT transfers
+ * will sometimes use data that's already buffered in the hardware.
+ * Drivers can rely on the fact that the first byte of the request's buffer
+ * always corresponds to the first byte of some USB packet, for both
+ * IN and OUT transfers.
+ *
+ * Bulk endpoints can queue any amount of data; the transfer is packetized
+ * automatically.  The last packet will be short if the request doesn't fill it
+ * out completely.  Zero length packets (ZLPs) should be avoided in portable
+ * protocols since not all usb hardware can successfully handle zero length
+ * packets.  (ZLPs may be explicitly written, and may be implicitly written if
+ * the request 'zero' flag is set.)  Bulk endpoints may also be used
+ * for interrupt transfers; but the reverse is not true, and some endpoints
+ * won't support every interrupt transfer.  (Such as 768 byte packets.)
+ *
+ * Interrupt-only endpoints are less functional than bulk endpoints, for
+ * example by not supporting queueing or not handling buffers that are
+ * larger than the endpoint's maxpacket size.  They may also treat data
+ * toggle differently.
+ *
+ * Control endpoints ... after getting a setup() callback, the driver queues
+ * one response (even if it would be zero length).  That enables the
+ * status ack, after transfering data as specified in the response.  Setup
+ * functions may return negative error codes to generate protocol stalls.
+ * (Note that some USB device controllers disallow protocol stall responses
+ * in some cases.)  When control responses are deferred (the response is
+ * written after the setup callback returns), then usb_ep_set_halt() may be
+ * used on ep0 to trigger protocol stalls.
+ *
+ * For periodic endpoints, like interrupt or isochronous ones, the usb host
+ * arranges to poll once per interval, and the gadget driver usually will
+ * have queued some data to transfer at that time.
+ *
+ * Returns zero, or a negative error code.  Endpoints that are not enabled
+ * report errors; errors will also be
+ * reported when the usb peripheral is disconnected.
+ */
+static inline int usb_ep_queue(struct usb_ep *ep,
+			       struct usb_request *req, gfp_t gfp_flags)
+{
+	return ep->ops->queue(ep, req, gfp_flags);
+}
+
+/**
+ * usb_ep_dequeue - dequeues (cancels, unlinks) an I/O request from an endpoint
+ * @ep:the endpoint associated with the request
+ * @req:the request being canceled
+ *
+ * if the request is still active on the endpoint, it is dequeued and its
+ * completion routine is called (with status -ECONNRESET); else a negative
+ * error code is returned.
+ *
+ * note that some hardware can't clear out write fifos (to unlink the request
+ * at the head of the queue) except as part of disconnecting from usb.  such
+ * restrictions prevent drivers from supporting configuration changes,
+ * even to configuration zero (a "chapter 9" requirement).
+ */
+static inline int usb_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
+{
+	return ep->ops->dequeue(ep, req);
+}
+
+/**
+ * usb_ep_set_halt - sets the endpoint halt feature.
+ * @ep: the non-isochronous endpoint being stalled
+ *
+ * Use this to stall an endpoint, perhaps as an error report.
+ * Except for control endpoints,
+ * the endpoint stays halted (will not stream any data) until the host
+ * clears this feature; drivers may need to empty the endpoint's request
+ * queue first, to make sure no inappropriate transfers happen.
+ *
+ * Note that while an endpoint CLEAR_FEATURE will be invisible to the
+ * gadget driver, a SET_INTERFACE will not be.  To reset endpoints for the
+ * current altsetting, see usb_ep_clear_halt().  When switching altsettings,
+ * it's simplest to use usb_ep_enable() or usb_ep_disable() for the endpoints.
+ *
+ * Returns zero, or a negative error code.  On success, this call sets
+ * underlying hardware state that blocks data transfers.
+ * Attempts to halt IN endpoints will fail (returning -EAGAIN) if any
+ * transfer requests are still queued, or if the controller hardware
+ * (usually a FIFO) still holds bytes that the host hasn't collected.
+ */
+static inline int usb_ep_set_halt(struct usb_ep *ep)
+{
+	return ep->ops->set_halt(ep, 1);
+}
+
+/**
+ * usb_ep_clear_halt - clears endpoint halt, and resets toggle
+ * @ep:the bulk or interrupt endpoint being reset
+ *
+ * Use this when responding to the standard usb "set interface" request,
+ * for endpoints that aren't reconfigured, after clearing any other state
+ * in the endpoint's i/o queue.
+ *
+ * Returns zero, or a negative error code.  On success, this call clears
+ * the underlying hardware state reflecting endpoint halt and data toggle.
+ * Note that some hardware can't support this request (like pxa2xx_udc),
+ * and accordingly can't correctly implement interface altsettings.
+ */
+static inline int usb_ep_clear_halt(struct usb_ep *ep)
+{
+	return ep->ops->set_halt(ep, 0);
+}
+
+/**
+ * usb_ep_fifo_status - returns number of bytes in fifo, or error
+ * @ep: the endpoint whose fifo status is being checked.
+ *
+ * FIFO endpoints may have "unclaimed data" in them in certain cases,
+ * such as after aborted transfers.  Hosts may not have collected all
+ * the IN data written by the gadget driver (and reported by a request
+ * completion).  The gadget driver may not have collected all the data
+ * written OUT to it by the host.  Drivers that need precise handling for
+ * fault reporting or recovery may need to use this call.
+ *
+ * This returns the number of such bytes in the fifo, or a negative
+ * errno if the endpoint doesn't use a FIFO or doesn't support such
+ * precise handling.
+ */
+static inline int usb_ep_fifo_status(struct usb_ep *ep)
+{
+	if (ep->ops->fifo_status)
+		return ep->ops->fifo_status(ep);
+	else
+		return -EOPNOTSUPP;
+}
+
+/**
+ * usb_ep_fifo_flush - flushes contents of a fifo
+ * @ep: the endpoint whose fifo is being flushed.
+ *
+ * This call may be used to flush the "unclaimed data" that may exist in
+ * an endpoint fifo after abnormal transaction terminations.  The call
+ * must never be used except when endpoint is not being used for any
+ * protocol translation.
+ */
+static inline void usb_ep_fifo_flush(struct usb_ep *ep)
+{
+	if (ep->ops->fifo_flush)
+		ep->ops->fifo_flush(ep);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+struct usb_gadget;
+struct usb_gadget_driver;
+
+/* the rest of the api to the controller hardware: device operations,
+ * which don't involve endpoints (or i/o).
+ */
+struct usb_gadget_ops {
+	int	(*get_frame)(struct usb_gadget *);
+	int	(*wakeup)(struct usb_gadget *);
+	int	(*set_selfpowered) (struct usb_gadget *, int is_selfpowered);
+	int	(*vbus_session) (struct usb_gadget *, int is_active);
+	int	(*vbus_draw) (struct usb_gadget *, unsigned mA);
+	int	(*pullup) (struct usb_gadget *, int is_on);
+	int	(*ioctl)(struct usb_gadget *,
+				unsigned code, unsigned long param);
+	int	(*udc_start)(struct usb_gadget *,
+			     struct usb_gadget_driver *);
+	int	(*udc_stop)(struct usb_gadget *);
+};
+
+/**
+ * struct usb_gadget - represents a usb slave device
+ * @ops: Function pointers used to access hardware-specific operations.
+ * @ep0: Endpoint zero, used when reading or writing responses to
+ *	driver setup() requests
+ * @ep_list: List of other endpoints supported by the device.
+ * @speed: Speed of current connection to USB host.
+ * @max_speed: Maximal speed the UDC can handle.  UDC must support this
+ *      and all slower speeds.
+ * @is_dualspeed: true if the controller supports both high and full speed
+ *	operation.  If it does, the gadget driver must also support both.
+ * @is_otg: true if the USB device port uses a Mini-AB jack, so that the
+ *	gadget driver must provide a USB OTG descriptor.
+ * @is_a_peripheral: false unless is_otg, the "A" end of a USB cable
+ *	is in the Mini-AB jack, and HNP has been used to switch roles
+ *	so that the "A" device currently acts as A-Peripheral, not A-Host.
+ * @a_hnp_support: OTG device feature flag, indicating that the A-Host
+ *	supports HNP at this port.
+ * @a_alt_hnp_support: OTG device feature flag, indicating that the A-Host
+ *	only supports HNP on a different root port.
+ * @b_hnp_enable: OTG device feature flag, indicating that the A-Host
+ *	enabled HNP support.
+ * @name: Identifies the controller hardware type.  Used in diagnostics
+ *	and sometimes configuration.
+ * @dev: Driver model state for this abstract device.
+ * @quirk_ep_out_aligned_size: epout requires buffer size to be aligned to
+ *	MaxPacketSize.
+ *
+ * Gadgets have a mostly-portable "gadget driver" implementing device
+ * functions, handling all usb configurations and interfaces.  Gadget
+ * drivers talk to hardware-specific code indirectly, through ops vectors.
+ * That insulates the gadget driver from hardware details, and packages
+ * the hardware endpoints through generic i/o queues.  The "usb_gadget"
+ * and "usb_ep" interfaces provide that insulation from the hardware.
+ *
+ * Except for the driver data, all fields in this structure are
+ * read-only to the gadget driver.  That driver data is part of the
+ * "driver model" infrastructure in 2.6 (and later) kernels, and for
+ * earlier systems is grouped in a similar structure that's not known
+ * to the rest of the kernel.
+ *
+ * Values of the three OTG device feature flags are updated before the
+ * setup() call corresponding to USB_REQ_SET_CONFIGURATION, and before
+ * driver suspend() calls.  They are valid only when is_otg, and when the
+ * device is acting as a B-Peripheral (so is_a_peripheral is false).
+ */
+struct usb_gadget {
+	/* readonly to gadget driver */
+	const struct usb_gadget_ops	*ops;
+	struct usb_ep			*ep0;
+	struct list_head		ep_list;	/* of usb_ep */
+	enum usb_device_speed		speed;
+	enum usb_device_speed		max_speed;
+	enum usb_device_state		state;
+	unsigned			is_dualspeed:1;
+	unsigned			is_otg:1;
+	unsigned			is_a_peripheral:1;
+	unsigned			b_hnp_enable:1;
+	unsigned			a_hnp_support:1;
+	unsigned			a_alt_hnp_support:1;
+	const char			*name;
+	struct device			dev;
+	unsigned			quirk_ep_out_aligned_size:1;
+};
+
+static inline void set_gadget_data(struct usb_gadget *gadget, void *data)
+{
+	gadget->dev.driver_data = data;
+}
+
+static inline void *get_gadget_data(struct usb_gadget *gadget)
+{
+	return gadget->dev.driver_data;
+}
+
+static inline struct usb_gadget *dev_to_usb_gadget(struct device *dev)
+{
+	return container_of(dev, struct usb_gadget, dev);
+}
+
+/* iterates the non-control endpoints; 'tmp' is a struct usb_ep pointer */
+#define gadget_for_each_ep(tmp, gadget) \
+	list_for_each_entry(tmp, &(gadget)->ep_list, ep_list)
+
+
+/**
+ * gadget_is_dualspeed - return true iff the hardware handles high speed
+ * @g: controller that might support both high and full speeds
+ */
+static inline int gadget_is_dualspeed(struct usb_gadget *g)
+{
+#ifdef CONFIG_USB_GADGET_DUALSPEED
+	/* runtime test would check "g->is_dualspeed" ... that might be
+	 * useful to work around hardware bugs, but is mostly pointless
+	 */
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+/**
+ * gadget_is_otg - return true iff the hardware is OTG-ready
+ * @g: controller that might have a Mini-AB connector
+ *
+ * This is a runtime test, since kernels with a USB-OTG stack sometimes
+ * run on boards which only have a Mini-B (or Mini-A) connector.
+ */
+static inline int gadget_is_otg(struct usb_gadget *g)
+{
+#ifdef CONFIG_USB_OTG
+	return g->is_otg;
+#else
+	return 0;
+#endif
+}
+
+/**
+ * usb_gadget_frame_number - returns the current frame number
+ * @gadget: controller that reports the frame number
+ *
+ * Returns the usb frame number, normally eleven bits from a SOF packet,
+ * or negative errno if this device doesn't support this capability.
+ */
+static inline int usb_gadget_frame_number(struct usb_gadget *gadget)
+{
+	return gadget->ops->get_frame(gadget);
+}
+
+/**
+ * usb_gadget_wakeup - tries to wake up the host connected to this gadget
+ * @gadget: controller used to wake up the host
+ *
+ * Returns zero on success, else negative error code if the hardware
+ * doesn't support such attempts, or its support has not been enabled
+ * by the usb host.  Drivers must return device descriptors that report
+ * their ability to support this, or hosts won't enable it.
+ *
+ * This may also try to use SRP to wake the host and start enumeration,
+ * even if OTG isn't otherwise in use.  OTG devices may also start
+ * remote wakeup even when hosts don't explicitly enable it.
+ */
+static inline int usb_gadget_wakeup(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->wakeup)
+		return -EOPNOTSUPP;
+	return gadget->ops->wakeup(gadget);
+}
+
+/**
+ * usb_gadget_set_selfpowered - sets the device selfpowered feature.
+ * @gadget:the device being declared as self-powered
+ *
+ * this affects the device status reported by the hardware driver
+ * to reflect that it now has a local power supply.
+ *
+ * returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_set_selfpowered(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->set_selfpowered)
+		return -EOPNOTSUPP;
+	return gadget->ops->set_selfpowered(gadget, 1);
+}
+
+/**
+ * usb_gadget_clear_selfpowered - clear the device selfpowered feature.
+ * @gadget:the device being declared as bus-powered
+ *
+ * this affects the device status reported by the hardware driver.
+ * some hardware may not support bus-powered operation, in which
+ * case this feature's value can never change.
+ *
+ * returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_clear_selfpowered(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->set_selfpowered)
+		return -EOPNOTSUPP;
+	return gadget->ops->set_selfpowered(gadget, 0);
+}
+
+/**
+ * usb_gadget_vbus_connect - Notify controller that VBUS is powered
+ * @gadget:The device which now has VBUS power.
+ *
+ * This call is used by a driver for an external transceiver (or GPIO)
+ * that detects a VBUS power session starting.  Common responses include
+ * resuming the controller, activating the D+ (or D-) pullup to let the
+ * host detect that a USB device is attached, and starting to draw power
+ * (8mA or possibly more, especially after SET_CONFIGURATION).
+ *
+ * Returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_vbus_connect(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->vbus_session)
+		return -EOPNOTSUPP;
+	return gadget->ops->vbus_session(gadget, 1);
+}
+
+/**
+ * usb_gadget_vbus_draw - constrain controller's VBUS power usage
+ * @gadget:The device whose VBUS usage is being described
+ * @mA:How much current to draw, in milliAmperes.  This should be twice
+ *	the value listed in the configuration descriptor bMaxPower field.
+ *
+ * This call is used by gadget drivers during SET_CONFIGURATION calls,
+ * reporting how much power the device may consume.  For example, this
+ * could affect how quickly batteries are recharged.
+ *
+ * Returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
+{
+	if (!gadget->ops->vbus_draw)
+		return -EOPNOTSUPP;
+	return gadget->ops->vbus_draw(gadget, mA);
+}
+
+/**
+ * usb_gadget_vbus_disconnect - notify controller about VBUS session end
+ * @gadget:the device whose VBUS supply is being described
+ *
+ * This call is used by a driver for an external transceiver (or GPIO)
+ * that detects a VBUS power session ending.  Common responses include
+ * reversing everything done in usb_gadget_vbus_connect().
+ *
+ * Returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_vbus_disconnect(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->vbus_session)
+		return -EOPNOTSUPP;
+	return gadget->ops->vbus_session(gadget, 0);
+}
+
+/**
+ * usb_gadget_connect - software-controlled connect to USB host
+ * @gadget:the peripheral being connected
+ *
+ * Enables the D+ (or potentially D-) pullup.  The host will start
+ * enumerating this gadget when the pullup is active and a VBUS session
+ * is active (the link is powered).  This pullup is always enabled unless
+ * usb_gadget_disconnect() has been used to disable it.
+ *
+ * Returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_connect(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->pullup)
+		return -EOPNOTSUPP;
+	return gadget->ops->pullup(gadget, 1);
+}
+
+/**
+ * usb_gadget_disconnect - software-controlled disconnect from USB host
+ * @gadget:the peripheral being disconnected
+ *
+ * Disables the D+ (or potentially D-) pullup, which the host may see
+ * as a disconnect (when a VBUS session is active).  Not all systems
+ * support software pullup controls.
+ *
+ * This routine may be used during the gadget driver bind() call to prevent
+ * the peripheral from ever being visible to the USB host, unless later
+ * usb_gadget_connect() is called.  For example, user mode components may
+ * need to be activated before the system can talk to hosts.
+ *
+ * Returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_disconnect(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->pullup)
+		return -EOPNOTSUPP;
+	return gadget->ops->pullup(gadget, 0);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * struct usb_gadget_driver - driver for usb 'slave' devices
+ * @function: String describing the gadget's function
+ * @speed: Highest speed the driver handles.
+ * @bind: Invoked when the driver is bound to a gadget, usually
+ *	after registering the driver.
+ *	At that point, ep0 is fully initialized, and ep_list holds
+ *	the currently-available endpoints.
+ *	Called in a context that permits sleeping.
+ * @setup: Invoked for ep0 control requests that aren't handled by
+ *	the hardware level driver. Most calls must be handled by
+ *	the gadget driver, including descriptor and configuration
+ *	management.  The 16 bit members of the setup data are in
+ *	USB byte order. Called in_interrupt; this may not sleep.  Driver
+ *	queues a response to ep0, or returns negative to stall.
+ * @disconnect: Invoked after all transfers have been stopped,
+ *	when the host is disconnected.  May be called in_interrupt; this
+ *	may not sleep.  Some devices can't detect disconnect, so this might
+ *	not be called except as part of controller shutdown.
+ * @unbind: Invoked when the driver is unbound from a gadget,
+ *	usually from rmmod (after a disconnect is reported).
+ *	Called in a context that permits sleeping.
+ * @suspend: Invoked on USB suspend.  May be called in_interrupt.
+ * @resume: Invoked on USB resume.  May be called in_interrupt.
+ * @reset: Invoked on USB bus reset. It is mandatory for all gadget drivers
+ *	and should be called in_interrupt.
+ *
+ * Devices are disabled till a gadget driver successfully bind()s, which
+ * means the driver will handle setup() requests needed to enumerate (and
+ * meet "chapter 9" requirements) then do some useful work.
+ *
+ * If gadget->is_otg is true, the gadget driver must provide an OTG
+ * descriptor during enumeration, or else fail the bind() call.  In such
+ * cases, no USB traffic may flow until both bind() returns without
+ * having called usb_gadget_disconnect(), and the USB host stack has
+ * initialized.
+ *
+ * Drivers use hardware-specific knowledge to configure the usb hardware.
+ * endpoint addressing is only one of several hardware characteristics that
+ * are in descriptors the ep0 implementation returns from setup() calls.
+ *
+ * Except for ep0 implementation, most driver code shouldn't need change to
+ * run on top of different usb controllers.  It'll use endpoints set up by
+ * that ep0 implementation.
+ *
+ * The usb controller driver handles a few standard usb requests.  Those
+ * include set_address, and feature flags for devices, interfaces, and
+ * endpoints (the get_status, set_feature, and clear_feature requests).
+ *
+ * Accordingly, the driver's setup() callback must always implement all
+ * get_descriptor requests, returning at least a device descriptor and
+ * a configuration descriptor.  Drivers must make sure the endpoint
+ * descriptors match any hardware constraints. Some hardware also constrains
+ * other descriptors. (The pxa250 allows only configurations 1, 2, or 3).
+ *
+ * The driver's setup() callback must also implement set_configuration,
+ * and should also implement set_interface, get_configuration, and
+ * get_interface.  Setting a configuration (or interface) is where
+ * endpoints should be activated or (config 0) shut down.
+ *
+ * (Note that only the default control endpoint is supported.  Neither
+ * hosts nor devices generally support control traffic except to ep0.)
+ *
+ * Most devices will ignore USB suspend/resume operations, and so will
+ * not provide those callbacks.  However, some may need to change modes
+ * when the host is not longer directing those activities.  For example,
+ * local controls (buttons, dials, etc) may need to be re-enabled since
+ * the (remote) host can't do that any longer; or an error state might
+ * be cleared, to make the device behave identically whether or not
+ * power is maintained.
+ */
+struct usb_gadget_driver {
+	char			*function;
+	enum usb_device_speed	speed;
+	int			(*bind)(struct usb_gadget *);
+	void			(*unbind)(struct usb_gadget *);
+	int			(*setup)(struct usb_gadget *,
+					const struct usb_ctrlrequest *);
+	void			(*disconnect)(struct usb_gadget *);
+	void			(*suspend)(struct usb_gadget *);
+	void			(*resume)(struct usb_gadget *);
+	void			(*reset)(struct usb_gadget *);
+};
+
+
+/*-------------------------------------------------------------------------*/
+
+/* driver modules register and unregister, as usual.
+ * these calls must be made in a context that can sleep.
+ *
+ * these will usually be implemented directly by the hardware-dependent
+ * usb bus interface driver, which will only support a single driver.
+ */
+
+/**
+ * usb_gadget_register_driver - register a gadget driver
+ * @driver:the driver being registered
+ *
+ * Call this in your gadget driver's module initialization function,
+ * to tell the underlying usb controller driver about your driver.
+ * The driver's bind() function will be called to bind it to a
+ * gadget before this registration call returns.  It's expected that
+ * the bind() functions will be in init sections.
+ * This function must be called in a context that can sleep.
+ */
+int usb_gadget_register_driver(struct usb_gadget_driver *driver);
+
+/**
+ * usb_gadget_unregister_driver - unregister a gadget driver
+ * @driver:the driver being unregistered
+ *
+ * Call this in your gadget driver's module cleanup function,
+ * to tell the underlying usb controller that your driver is
+ * going away.  If the controller is connected to a USB host,
+ * it will first disconnect().  The driver is also requested
+ * to unbind() and clean up any device state, before this procedure
+ * finally returns.  It's expected that the unbind() functions
+ * will in in exit sections, so may not be linked in some kernels.
+ * This function must be called in a context that can sleep.
+ */
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver);
+
+int usb_add_gadget_udc_release(struct device *parent,
+		struct usb_gadget *gadget, void (*release)(struct device *dev));
+int usb_add_gadget_udc(struct device *parent, struct usb_gadget *gadget);
+void usb_del_gadget_udc(struct usb_gadget *gadget);
+/*-------------------------------------------------------------------------*/
+
+/* utility to simplify dealing with string descriptors */
+
+/**
+ * struct usb_gadget_strings - a set of USB strings in a given language
+ * @language:identifies the strings' language (0x0409 for en-us)
+ * @strings:array of strings with their ids
+ *
+ * If you're using usb_gadget_get_string(), use this to wrap all the
+ * strings for a given language.
+ */
+struct usb_gadget_strings {
+	u16			language;	/* 0x0409 for en-us */
+	struct usb_string	*strings;
+};
+
+/* put descriptor for string with that id into buf (buflen >= 256) */
+int usb_gadget_get_string(struct usb_gadget_strings *table, int id, u8 *buf);
+
+/*-------------------------------------------------------------------------*/
+
+/* utility to simplify managing config descriptors */
+
+/* write vector of descriptors into buffer */
+int usb_descriptor_fillbuf(void *, unsigned,
+		const struct usb_descriptor_header **);
+
+/* build config descriptor from single descriptor vector */
+int usb_gadget_config_buf(const struct usb_config_descriptor *config,
+	void *buf, unsigned buflen, const struct usb_descriptor_header **desc);
+
+/*-------------------------------------------------------------------------*/
+/* utility to simplify map/unmap of usb_requests to/from DMA */
+
+extern int usb_gadget_map_request(struct usb_gadget *gadget,
+				  struct usb_request *req, int is_in);
+
+extern void usb_gadget_unmap_request(struct usb_gadget *gadget,
+				     struct usb_request *req, int is_in);
+
+/*-------------------------------------------------------------------------*/
+
+/* utility to set gadget state properly */
+
+extern void usb_gadget_set_state(struct usb_gadget *gadget,
+				 enum usb_device_state state);
+
+/*-------------------------------------------------------------------------*/
+
+/* utility to tell udc core that the bus reset occurs */
+extern void usb_gadget_udc_reset(struct usb_gadget *gadget,
+				 struct usb_gadget_driver *driver);
+
+/*-------------------------------------------------------------------------*/
+
+/* utility to give requests back to the gadget layer */
+
+extern void usb_gadget_giveback_request(struct usb_ep *ep,
+					struct usb_request *req);
+
+/*-------------------------------------------------------------------------*/
+
+/* utility wrapping a simple endpoint selection policy */
+
+extern struct usb_ep *usb_ep_autoconfig(struct usb_gadget *,
+			struct usb_endpoint_descriptor *);
+
+extern void usb_ep_autoconfig_reset(struct usb_gadget *);
+
+extern int usb_gadget_handle_interrupts(int index);
+
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+int usb_gadget_initialize(int index);
+int usb_gadget_release(int index);
+int dm_usb_gadget_handle_interrupts(struct udevice *dev);
+#else
+#include <usb.h>
+static inline int usb_gadget_initialize(int index)
+{
+	return board_usb_init(index, USB_INIT_DEVICE);
+}
+
+static inline int usb_gadget_release(int index)
+{
+	return board_usb_cleanup(index, USB_INIT_DEVICE);
+}
+#endif
+
+#endif	/* __LINUX_USB_GADGET_H */
diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h
new file mode 100644
index 0000000..a31ce67
--- /dev/null
+++ b/include/linux/usb/musb.h
@@ -0,0 +1,156 @@
+/*
+ * This is used to for host and peripheral modes of the driver for
+ * Inventra (Multidrop) Highspeed Dual-Role Controllers:  (M)HDRC.
+ *
+ * Board initialization should put one of these into dev->platform_data,
+ * probably on some platform_device named "musb-hdrc".  It encapsulates
+ * key configuration differences between boards.
+ */
+
+#ifndef __LINUX_USB_MUSB_H
+#define __LINUX_USB_MUSB_H
+
+#ifndef __deprecated
+#define __deprecated
+#endif
+
+#include <linux/compat.h>
+
+/* The USB role is defined by the connector used on the board, so long as
+ * standards are being followed.  (Developer boards sometimes won't.)
+ */
+enum musb_mode {
+	MUSB_UNDEFINED = 0,
+	MUSB_HOST,		/* A or Mini-A connector */
+	MUSB_PERIPHERAL,	/* B or Mini-B connector */
+	MUSB_OTG		/* Mini-AB connector */
+};
+
+struct clk;
+
+enum musb_fifo_style {
+	FIFO_RXTX,
+	FIFO_TX,
+	FIFO_RX
+} __attribute__ ((packed));
+
+enum musb_buf_mode {
+	BUF_SINGLE,
+	BUF_DOUBLE
+} __attribute__ ((packed));
+
+struct musb_fifo_cfg {
+	u8			hw_ep_num;
+	enum musb_fifo_style	style;
+	enum musb_buf_mode	mode;
+	u16			maxpacket;
+};
+
+#define MUSB_EP_FIFO(ep, st, m, pkt)		\
+{						\
+	.hw_ep_num	= ep,			\
+	.style		= st,			\
+	.mode		= m,			\
+	.maxpacket	= pkt,			\
+}
+
+#define MUSB_EP_FIFO_SINGLE(ep, st, pkt)	\
+	MUSB_EP_FIFO(ep, st, BUF_SINGLE, pkt)
+
+#define MUSB_EP_FIFO_DOUBLE(ep, st, pkt)	\
+	MUSB_EP_FIFO(ep, st, BUF_DOUBLE, pkt)
+
+struct musb_hdrc_eps_bits {
+	const char	name[16];
+	u8		bits;
+};
+
+struct musb_hdrc_config {
+	struct musb_fifo_cfg	*fifo_cfg;	/* board fifo configuration */
+	unsigned		fifo_cfg_size;	/* size of the fifo configuration */
+
+	/* MUSB configuration-specific details */
+	unsigned	multipoint:1;	/* multipoint device */
+	unsigned	dyn_fifo:1 __deprecated; /* supports dynamic fifo sizing */
+	unsigned	soft_con:1 __deprecated; /* soft connect required */
+	unsigned	utm_16:1 __deprecated; /* utm data witdh is 16 bits */
+	unsigned	big_endian:1;	/* true if CPU uses big-endian */
+	unsigned	mult_bulk_tx:1;	/* Tx ep required for multbulk pkts */
+	unsigned	mult_bulk_rx:1;	/* Rx ep required for multbulk pkts */
+	unsigned	high_iso_tx:1;	/* Tx ep required for HB iso */
+	unsigned	high_iso_rx:1;	/* Rx ep required for HD iso */
+	unsigned	dma:1 __deprecated; /* supports DMA */
+	unsigned	vendor_req:1 __deprecated; /* vendor registers required */
+
+	u8		num_eps;	/* number of endpoints _with_ ep0 */
+	u8		dma_channels __deprecated; /* number of dma channels */
+	u8		dyn_fifo_size;	/* dynamic size in bytes */
+	u8		vendor_ctrl __deprecated; /* vendor control reg width */
+	u8		vendor_stat __deprecated; /* vendor status reg witdh */
+	u8		dma_req_chan __deprecated; /* bitmask for required dma channels */
+	u8		ram_bits;	/* ram address size */
+
+	struct musb_hdrc_eps_bits *eps_bits __deprecated;
+};
+
+struct musb_hdrc_platform_data {
+	/* MUSB_HOST, MUSB_PERIPHERAL, or MUSB_OTG */
+	u8		mode;
+
+	/* for clk_get() */
+	const char	*clock;
+
+	/* (HOST or OTG) switch VBUS on/off */
+	int		(*set_vbus)(struct device *dev, int is_on);
+
+	/* (HOST or OTG) mA/2 power supplied on (default = 8mA) */
+	u8		power;
+
+	/* (PERIPHERAL) mA/2 max power consumed (default = 100mA) */
+	u8		min_power;
+
+	/* (HOST or OTG) msec/2 after VBUS on till power good */
+	u8		potpgt;
+
+	/* (HOST or OTG) program PHY for external Vbus */
+	unsigned	extvbus:1;
+
+	/* Power the device on or off */
+	int		(*set_power)(int state);
+
+	/* MUSB configuration-specific details */
+	struct musb_hdrc_config	*config;
+
+	/* Architecture specific board data	*/
+	void		*board_data;
+
+	/* Platform specific struct musb_ops pointer */
+	const void	*platform_ops;
+};
+
+
+/* TUSB 6010 support */
+
+#define	TUSB6010_OSCCLK_60	16667	/* psec/clk @ 60.0 MHz */
+#define	TUSB6010_REFCLK_24	41667	/* psec/clk @ 24.0 MHz XI */
+#define	TUSB6010_REFCLK_19	52083	/* psec/clk @ 19.2 MHz CLKIN */
+
+#ifdef	CONFIG_ARCH_OMAP2PLUS
+
+extern int __init tusb6010_setup_interface(
+		struct musb_hdrc_platform_data *data,
+		unsigned ps_refclk, unsigned waitpin,
+		unsigned async_cs, unsigned sync_cs,
+		unsigned irq, unsigned dmachan);
+
+extern int tusb6010_platform_retime(unsigned is_refclk);
+
+#endif	/* OMAP2 */
+
+/*
+ * U-Boot specfic stuff
+ */
+struct musb *musb_register(struct musb_hdrc_platform_data *plat, void *bdata,
+			   void *ctl_regs);
+
+#endif /* __LINUX_USB_MUSB_H */
diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
new file mode 100644
index 0000000..d2604c5
--- /dev/null
+++ b/include/linux/usb/otg.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* include/linux/usb/otg.h
+ *
+ * Copyright (c) 2015 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * USB OTG (On The Go) defines
+ */
+
+#ifndef __LINUX_USB_OTG_H
+#define __LINUX_USB_OTG_H
+
+enum usb_dr_mode {
+	USB_DR_MODE_UNKNOWN,
+	USB_DR_MODE_HOST,
+	USB_DR_MODE_PERIPHERAL,
+	USB_DR_MODE_OTG,
+};
+
+/**
+ * usb_get_dr_mode() - Get dual role mode for given device
+ * @node: Node offset to the given device
+ *
+ * The function gets phy interface string from property 'dr_mode',
+ * and returns the correspondig enum usb_dr_mode
+ */
+enum usb_dr_mode usb_get_dr_mode(int node);
+
+/**
+ * usb_get_maximum_speed() - Get maximum speed for given device
+ * @node: Node offset to the given device
+ *
+ * The function gets phy interface string from property 'maximum-speed',
+ * and returns the correspondig enum usb_device_speed
+ */
+enum usb_device_speed usb_get_maximum_speed(int node);
+
+#endif /* __LINUX_USB_OTG_H */
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
new file mode 100644
index 0000000..1367149
--- /dev/null
+++ b/include/linux/usb/xhci-fsl.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * FSL USB HOST xHCI Controller
+ *
+ * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
+ */
+
+#ifndef _ASM_ARCH_XHCI_FSL_H_
+#define _ASM_ARCH_XHCI_FSL_H_
+
+/* Default to the FSL XHCI defines */
+#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON     BIT(6)
+#define USB3_PHY_RX_POWERON		BIT(14)
+#define USB3_PHY_TX_POWERON		BIT(15)
+#define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT   14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT	22
+#define USB3_ENABLE_BEAT_BURST		0xF
+#define USB3_ENABLE_BEAT_BURST_MASK	0xFF
+#define USB3_SET_BEAT_BURST_LIMIT	0xF00
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET	BIT(17)
+#define USBOTGSS_DMADISABLE BIT(16)
+#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
+#define USBOTGSS_STANDBYMODE_SMRT		BIT(5)
+#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
+#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
+#define USBOTGSS_IDLEMODE_SMRT BIT(3)
+#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
+
+/* USBOTGSS_IRQENABLE_SET_0 bit */
+#define USBOTGSS_COREIRQ_EN	BIT(1)
+
+/* USBOTGSS_IRQENABLE_SET_1 bits */
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN	BIT(1)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN	BIT(3)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	BIT(4)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	BIT(5)
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	BIT(8)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	BIT(11)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN	BIT(12)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN	BIT(13)
+#define USBOTGSS_IRQ_SET_1_OEVT_EN		BIT(16)
+#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN	BIT(17)
+
+struct fsl_xhci {
+	struct xhci_hccr *hcd;
+	struct dwc3 *dwc3_reg;
+};
+
+#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
+#elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR
+#endif
+
+#define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+					CONFIG_SYS_FSL_XHCI_USB2_ADDR, \
+					CONFIG_SYS_FSL_XHCI_USB3_ADDR}
+#endif /* _ASM_ARCH_XHCI_FSL_H_ */
diff --git a/include/linux/usb/xhci-omap.h b/include/linux/usb/xhci-omap.h
new file mode 100644
index 0000000..ce9c074
--- /dev/null
+++ b/include/linux/usb/xhci-omap.h
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Inc, <www.ti.com>
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ */
+
+#ifndef _ASM_ARCH_XHCI_OMAP_H_
+#define _ASM_ARCH_XHCI_OMAP_H_
+
+#ifdef CONFIG_DRA7XX
+#if CONFIG_USB_XHCI_DRA7XX_INDEX == 1
+#define OMAP_XHCI_BASE 0x488d0000
+#define OMAP_OCP1_SCP_BASE 0x4A081000
+#define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#elif CONFIG_USB_XHCI_DRA7XX_INDEX == 0
+#define OMAP_XHCI_BASE 0x48890000
+#define OMAP_OCP1_SCP_BASE 0x4A084c00
+#define OMAP_OTG_WRAPPER_BASE 0x48880000
+#endif /* CONFIG_USB_XHCI_DRA7XX_INDEX == 1 */
+#elif defined CONFIG_AM43XX
+#define OMAP_XHCI_BASE 0x483d0000
+#define OMAP_OCP1_SCP_BASE 0x483E8000
+#define OMAP_OTG_WRAPPER_BASE 0x483dc100
+#else
+/* Default to the OMAP5 XHCI defines */
+#define OMAP_XHCI_BASE 0x4a030000
+#define OMAP_OCP1_SCP_BASE 0x4a084c00
+#define OMAP_OTG_WRAPPER_BASE 0x4A020000
+#endif
+
+/* Phy register MACRO definitions */
+#define	PLL_REGM_MASK		0x001FFE00
+#define	PLL_REGM_SHIFT		0x9
+#define	PLL_REGM_F_MASK		0x0003FFFF
+#define	PLL_REGM_F_SHIFT	0x0
+#define	PLL_REGN_MASK		0x000001FE
+#define	PLL_REGN_SHIFT		0x1
+#define	PLL_SELFREQDCO_MASK	0x0000000E
+#define	PLL_SELFREQDCO_SHIFT	0x1
+#define	PLL_SD_MASK		0x0003FC00
+#define	PLL_SD_SHIFT		0x9
+#define	SET_PLL_GO		0x1
+#define	PLL_TICOPWDN		0x10000
+#define	PLL_LOCK		0x2
+#define	PLL_IDLE		0x1
+
+#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON     (1 << 6)
+#define USB3_PHY_RX_POWERON		(1 << 14)
+#define USB3_PHY_TX_POWERON		(1 << 15)
+#define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT   14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT	22
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET	(1 << 17)
+#define USBOTGSS_DMADISABLE (1 << 16)
+#define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4)
+#define USBOTGSS_STANDBYMODE_SMRT		(1 << 5)
+#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
+#define USBOTGSS_IDLEMODE_NOIDLE (1 << 2)
+#define USBOTGSS_IDLEMODE_SMRT (1 << 3)
+#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
+
+/* USBOTGSS_IRQENABLE_SET_0 bit */
+#define USBOTGSS_COREIRQ_EN	(1 << 0)
+
+/* USBOTGSS_IRQENABLE_SET_1 bits */
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN	(1 << 0)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN	(1 << 3)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	(1 << 4)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	(1 << 5)
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	(1 << 8)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	(1 << 11)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN	(1 << 12)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN	(1 << 13)
+#define USBOTGSS_IRQ_SET_1_OEVT_EN	(1 << 16)
+#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN	(1 << 17)
+
+/*
+ * USBOTGSS_WRAPPER registers
+ */
+struct omap_dwc_wrapper {
+	u32 revision;
+
+	u32 reserve_1[3];
+
+	u32 sysconfig; /* offset of 0x10 */
+
+	u32 reserve_2[3];
+	u16 reserve_3;
+
+	u32 irqstatus_raw_0; /* offset of 0x24 */
+	u32 irqstatus_0;
+	u32 irqenable_set_0;
+	u32 irqenable_clr_0;
+
+	u32 irqstatus_raw_1; /* offset of 0x34 */
+	u32 irqstatus_1;
+	u32 irqenable_set_1;
+	u32 irqenable_clr_1;
+
+	u32 reserve_4[15];
+
+	u32 utmi_otg_ctrl; /* offset of 0x80 */
+	u32 utmi_otg_status;
+
+	u32 reserve_5[30];
+
+	u32 mram_offset; /* offset of 0x100 */
+	u32 fladj;
+	u32 dbg_config;
+	u32 dbg_data;
+	u32 dev_ebc_en;
+};
+
+/* XHCI PHY register structure */
+struct omap_usb3_phy {
+	u32 reserve1;
+	u32 pll_status;
+	u32 pll_go;
+	u32 pll_config_1;
+	u32 pll_config_2;
+	u32 pll_config_3;
+	u32 pll_ssc_config_1;
+	u32 pll_ssc_config_2;
+	u32 pll_config_4;
+};
+
+struct omap_xhci {
+	struct omap_dwc_wrapper *otg_wrapper;
+	struct omap_usb3_phy *usb3_phy;
+	struct xhci_hccr *hcd;
+	struct dwc3 *dwc3_reg;
+};
+
+/* USB PHY functions */
+void omap_enable_phy(struct omap_xhci *omap);
+void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
+void usb_phy_power(int on);
+
+#endif /* _ASM_ARCH_XHCI_OMAP_H_ */
diff --git a/include/linux/xxhash.h b/include/linux/xxhash.h
new file mode 100644
index 0000000..85feb67
--- /dev/null
+++ b/include/linux/xxhash.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-2-Clause) */
+/*
+ * xxHash - Extremely Fast Hash algorithm
+ * Copyright (C) 2012-2016, Yann Collet.
+ *
+ * You can contact the author at:
+ * - xxHash homepage: http://cyan4973.github.io/xxHash/
+ * - xxHash source repository: https://github.com/Cyan4973/xxHash
+ */
+
+/*
+ * Notice extracted from xxHash homepage:
+ *
+ * xxHash is an extremely fast Hash algorithm, running at RAM speed limits.
+ * It also successfully passes all tests from the SMHasher suite.
+ *
+ * Comparison (single thread, Windows Seven 32 bits, using SMHasher on a Core 2
+ * Duo @3GHz)
+ *
+ * Name            Speed       Q.Score   Author
+ * xxHash          5.4 GB/s     10
+ * CrapWow         3.2 GB/s      2       Andrew
+ * MumurHash 3a    2.7 GB/s     10       Austin Appleby
+ * SpookyHash      2.0 GB/s     10       Bob Jenkins
+ * SBox            1.4 GB/s      9       Bret Mulvey
+ * Lookup3         1.2 GB/s      9       Bob Jenkins
+ * SuperFastHash   1.2 GB/s      1       Paul Hsieh
+ * CityHash64      1.05 GB/s    10       Pike & Alakuijala
+ * FNV             0.55 GB/s     5       Fowler, Noll, Vo
+ * CRC32           0.43 GB/s     9
+ * MD5-32          0.33 GB/s    10       Ronald L. Rivest
+ * SHA1-32         0.28 GB/s    10
+ *
+ * Q.Score is a measure of quality of the hash function.
+ * It depends on successfully passing SMHasher test set.
+ * 10 is a perfect score.
+ *
+ * A 64-bits version, named xxh64 offers much better speed,
+ * but for 64-bits applications only.
+ * Name     Speed on 64 bits    Speed on 32 bits
+ * xxh64       13.8 GB/s            1.9 GB/s
+ * xxh32        6.8 GB/s            6.0 GB/s
+ */
+
+#ifndef XXHASH_H
+#define XXHASH_H
+
+#include <linux/types.h>
+
+/*-****************************
+ * Simple Hash Functions
+ *****************************/
+
+/**
+ * xxh32() - calculate the 32-bit hash of the input with a given seed.
+ *
+ * @input:  The data to hash.
+ * @length: The length of the data to hash.
+ * @seed:   The seed can be used to alter the result predictably.
+ *
+ * Speed on Core 2 Duo @ 3 GHz (single thread, SMHasher benchmark) : 5.4 GB/s
+ *
+ * Return:  The 32-bit hash of the data.
+ */
+uint32_t xxh32(const void *input, size_t length, uint32_t seed);
+
+/**
+ * xxh64() - calculate the 64-bit hash of the input with a given seed.
+ *
+ * @input:  The data to hash.
+ * @length: The length of the data to hash.
+ * @seed:   The seed can be used to alter the result predictably.
+ *
+ * This function runs 2x faster on 64-bit systems, but slower on 32-bit systems.
+ *
+ * Return:  The 64-bit hash of the data.
+ */
+uint64_t xxh64(const void *input, size_t length, uint64_t seed);
+
+/**
+ * xxhash() - calculate wordsize hash of the input with a given seed
+ * @input:  The data to hash.
+ * @length: The length of the data to hash.
+ * @seed:   The seed can be used to alter the result predictably.
+ *
+ * If the hash does not need to be comparable between machines with
+ * different word sizes, this function will call whichever of xxh32()
+ * or xxh64() is faster.
+ *
+ * Return:  wordsize hash of the data.
+ */
+
+static inline unsigned long xxhash(const void *input, size_t length,
+				   uint64_t seed)
+{
+#if BITS_PER_LONG == 64
+       return xxh64(input, length, seed);
+#else
+       return xxh32(input, length, seed);
+#endif
+}
+
+/*-****************************
+ * Streaming Hash Functions
+ *****************************/
+
+/*
+ * These definitions are only meant to allow allocation of XXH state
+ * statically, on stack, or in a struct for example.
+ * Do not use members directly.
+ */
+
+/**
+ * struct xxh32_state - private xxh32 state, do not use members directly
+ */
+struct xxh32_state {
+	uint32_t total_len_32;
+	uint32_t large_len;
+	uint32_t v1;
+	uint32_t v2;
+	uint32_t v3;
+	uint32_t v4;
+	uint32_t mem32[4];
+	uint32_t memsize;
+};
+
+/**
+ * struct xxh32_state - private xxh64 state, do not use members directly
+ */
+struct xxh64_state {
+	uint64_t total_len;
+	uint64_t v1;
+	uint64_t v2;
+	uint64_t v3;
+	uint64_t v4;
+	uint64_t mem64[4];
+	uint32_t memsize;
+};
+
+/**
+ * xxh32_reset() - reset the xxh32 state to start a new hashing operation
+ *
+ * @state: The xxh32 state to reset.
+ * @seed:  Initialize the hash state with this seed.
+ *
+ * Call this function on any xxh32_state to prepare for a new hashing operation.
+ */
+void xxh32_reset(struct xxh32_state *state, uint32_t seed);
+
+/**
+ * xxh32_update() - hash the data given and update the xxh32 state
+ *
+ * @state:  The xxh32 state to update.
+ * @input:  The data to hash.
+ * @length: The length of the data to hash.
+ *
+ * After calling xxh32_reset() call xxh32_update() as many times as necessary.
+ *
+ * Return:  Zero on success, otherwise an error code.
+ */
+int xxh32_update(struct xxh32_state *state, const void *input, size_t length);
+
+/**
+ * xxh32_digest() - produce the current xxh32 hash
+ *
+ * @state: Produce the current xxh32 hash of this state.
+ *
+ * A hash value can be produced at any time. It is still possible to continue
+ * inserting input into the hash state after a call to xxh32_digest(), and
+ * generate new hashes later on, by calling xxh32_digest() again.
+ *
+ * Return: The xxh32 hash stored in the state.
+ */
+uint32_t xxh32_digest(const struct xxh32_state *state);
+
+/**
+ * xxh64_reset() - reset the xxh64 state to start a new hashing operation
+ *
+ * @state: The xxh64 state to reset.
+ * @seed:  Initialize the hash state with this seed.
+ */
+void xxh64_reset(struct xxh64_state *state, uint64_t seed);
+
+/**
+ * xxh64_update() - hash the data given and update the xxh64 state
+ * @state:  The xxh64 state to update.
+ * @input:  The data to hash.
+ * @length: The length of the data to hash.
+ *
+ * After calling xxh64_reset() call xxh64_update() as many times as necessary.
+ *
+ * Return:  Zero on success, otherwise an error code.
+ */
+int xxh64_update(struct xxh64_state *state, const void *input, size_t length);
+
+/**
+ * xxh64_digest() - produce the current xxh64 hash
+ *
+ * @state: Produce the current xxh64 hash of this state.
+ *
+ * A hash value can be produced at any time. It is still possible to continue
+ * inserting input into the hash state after a call to xxh64_digest(), and
+ * generate new hashes later on, by calling xxh64_digest() again.
+ *
+ * Return: The xxh64 hash stored in the state.
+ */
+uint64_t xxh64_digest(const struct xxh64_state *state);
+
+/*-**************************
+ * Utils
+ ***************************/
+
+/**
+ * xxh32_copy_state() - copy the source state into the destination state
+ *
+ * @src: The source xxh32 state.
+ * @dst: The destination xxh32 state.
+ */
+void xxh32_copy_state(struct xxh32_state *dst, const struct xxh32_state *src);
+
+/**
+ * xxh64_copy_state() - copy the source state into the destination state
+ *
+ * @src: The source xxh64 state.
+ * @dst: The destination xxh64 state.
+ */
+void xxh64_copy_state(struct xxh64_state *dst, const struct xxh64_state *src);
+
+#endif /* XXHASH_H */
diff --git a/include/linux/zstd.h b/include/linux/zstd.h
new file mode 100644
index 0000000..724f693
--- /dev/null
+++ b/include/linux/zstd.h
@@ -0,0 +1,1147 @@
+/* SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause-Clear) */
+/*
+ * Copyright (c) 2016-present, Yann Collet, Facebook, Inc.
+ * All rights reserved.
+ */
+
+#ifndef ZSTD_H
+#define ZSTD_H
+
+/* ======   Dependency   ======*/
+#include <linux/types.h>   /* size_t */
+
+
+/*-*****************************************************************************
+ * Introduction
+ *
+ * zstd, short for Zstandard, is a fast lossless compression algorithm,
+ * targeting real-time compression scenarios at zlib-level and better
+ * compression ratios. The zstd compression library provides in-memory
+ * compression and decompression functions. The library supports compression
+ * levels from 1 up to ZSTD_maxCLevel() which is 22. Levels >= 20, labeled
+ * ultra, should be used with caution, as they require more memory.
+ * Compression can be done in:
+ *  - a single step, reusing a context (described as Explicit memory management)
+ *  - unbounded multiple steps (described as Streaming compression)
+ * The compression ratio achievable on small data can be highly improved using
+ * compression with a dictionary in:
+ *  - a single step (described as Simple dictionary API)
+ *  - a single step, reusing a dictionary (described as Fast dictionary API)
+ ******************************************************************************/
+
+/*======  Helper functions  ======*/
+
+/**
+ * enum ZSTD_ErrorCode - zstd error codes
+ *
+ * Functions that return size_t can be checked for errors using ZSTD_isError()
+ * and the ZSTD_ErrorCode can be extracted using ZSTD_getErrorCode().
+ */
+typedef enum {
+	ZSTD_error_no_error,
+	ZSTD_error_GENERIC,
+	ZSTD_error_prefix_unknown,
+	ZSTD_error_version_unsupported,
+	ZSTD_error_parameter_unknown,
+	ZSTD_error_frameParameter_unsupported,
+	ZSTD_error_frameParameter_unsupportedBy32bits,
+	ZSTD_error_frameParameter_windowTooLarge,
+	ZSTD_error_compressionParameter_unsupported,
+	ZSTD_error_init_missing,
+	ZSTD_error_memory_allocation,
+	ZSTD_error_stage_wrong,
+	ZSTD_error_dstSize_tooSmall,
+	ZSTD_error_srcSize_wrong,
+	ZSTD_error_corruption_detected,
+	ZSTD_error_checksum_wrong,
+	ZSTD_error_tableLog_tooLarge,
+	ZSTD_error_maxSymbolValue_tooLarge,
+	ZSTD_error_maxSymbolValue_tooSmall,
+	ZSTD_error_dictionary_corrupted,
+	ZSTD_error_dictionary_wrong,
+	ZSTD_error_dictionaryCreation_failed,
+	ZSTD_error_maxCode
+} ZSTD_ErrorCode;
+
+/**
+ * ZSTD_maxCLevel() - maximum compression level available
+ *
+ * Return: Maximum compression level available.
+ */
+int ZSTD_maxCLevel(void);
+/**
+ * ZSTD_compressBound() - maximum compressed size in worst case scenario
+ * @srcSize: The size of the data to compress.
+ *
+ * Return:   The maximum compressed size in the worst case scenario.
+ */
+size_t ZSTD_compressBound(size_t srcSize);
+/**
+ * ZSTD_isError() - tells if a size_t function result is an error code
+ * @code:  The function result to check for error.
+ *
+ * Return: Non-zero iff the code is an error.
+ */
+static __attribute__((unused)) unsigned int ZSTD_isError(size_t code)
+{
+	return code > (size_t)-ZSTD_error_maxCode;
+}
+/**
+ * ZSTD_getErrorCode() - translates an error function result to a ZSTD_ErrorCode
+ * @functionResult: The result of a function for which ZSTD_isError() is true.
+ *
+ * Return:          The ZSTD_ErrorCode corresponding to the functionResult or 0
+ *                  if the functionResult isn't an error.
+ */
+static __attribute__((unused)) ZSTD_ErrorCode ZSTD_getErrorCode(
+	size_t functionResult)
+{
+	if (!ZSTD_isError(functionResult))
+		return (ZSTD_ErrorCode)0;
+	return (ZSTD_ErrorCode)(0 - functionResult);
+}
+
+/**
+ * enum ZSTD_strategy - zstd compression search strategy
+ *
+ * From faster to stronger.
+ */
+typedef enum {
+	ZSTD_fast,
+	ZSTD_dfast,
+	ZSTD_greedy,
+	ZSTD_lazy,
+	ZSTD_lazy2,
+	ZSTD_btlazy2,
+	ZSTD_btopt,
+	ZSTD_btopt2
+} ZSTD_strategy;
+
+/**
+ * struct ZSTD_compressionParameters - zstd compression parameters
+ * @windowLog:    Log of the largest match distance. Larger means more
+ *                compression, and more memory needed during decompression.
+ * @chainLog:     Fully searched segment. Larger means more compression, slower,
+ *                and more memory (useless for fast).
+ * @hashLog:      Dispatch table. Larger means more compression,
+ *                slower, and more memory.
+ * @searchLog:    Number of searches. Larger means more compression and slower.
+ * @searchLength: Match length searched. Larger means faster decompression,
+ *                sometimes less compression.
+ * @targetLength: Acceptable match size for optimal parser (only). Larger means
+ *                more compression, and slower.
+ * @strategy:     The zstd compression strategy.
+ */
+typedef struct {
+	unsigned int windowLog;
+	unsigned int chainLog;
+	unsigned int hashLog;
+	unsigned int searchLog;
+	unsigned int searchLength;
+	unsigned int targetLength;
+	ZSTD_strategy strategy;
+} ZSTD_compressionParameters;
+
+/**
+ * struct ZSTD_frameParameters - zstd frame parameters
+ * @contentSizeFlag: Controls whether content size will be present in the frame
+ *                   header (when known).
+ * @checksumFlag:    Controls whether a 32-bit checksum is generated at the end
+ *                   of the frame for error detection.
+ * @noDictIDFlag:    Controls whether dictID will be saved into the frame header
+ *                   when using dictionary compression.
+ *
+ * The default value is all fields set to 0.
+ */
+typedef struct {
+	unsigned int contentSizeFlag;
+	unsigned int checksumFlag;
+	unsigned int noDictIDFlag;
+} ZSTD_frameParameters;
+
+/**
+ * struct ZSTD_parameters - zstd parameters
+ * @cParams: The compression parameters.
+ * @fParams: The frame parameters.
+ */
+typedef struct {
+	ZSTD_compressionParameters cParams;
+	ZSTD_frameParameters fParams;
+} ZSTD_parameters;
+
+/**
+ * ZSTD_getCParams() - returns ZSTD_compressionParameters for selected level
+ * @compressionLevel: The compression level from 1 to ZSTD_maxCLevel().
+ * @estimatedSrcSize: The estimated source size to compress or 0 if unknown.
+ * @dictSize:         The dictionary size or 0 if a dictionary isn't being used.
+ *
+ * Return:            The selected ZSTD_compressionParameters.
+ */
+ZSTD_compressionParameters ZSTD_getCParams(int compressionLevel,
+	unsigned long long estimatedSrcSize, size_t dictSize);
+
+/**
+ * ZSTD_getParams() - returns ZSTD_parameters for selected level
+ * @compressionLevel: The compression level from 1 to ZSTD_maxCLevel().
+ * @estimatedSrcSize: The estimated source size to compress or 0 if unknown.
+ * @dictSize:         The dictionary size or 0 if a dictionary isn't being used.
+ *
+ * The same as ZSTD_getCParams() except also selects the default frame
+ * parameters (all zero).
+ *
+ * Return:            The selected ZSTD_parameters.
+ */
+ZSTD_parameters ZSTD_getParams(int compressionLevel,
+	unsigned long long estimatedSrcSize, size_t dictSize);
+
+/*-*************************************
+ * Explicit memory management
+ **************************************/
+
+/**
+ * ZSTD_CCtxWorkspaceBound() - amount of memory needed to initialize a ZSTD_CCtx
+ * @cParams: The compression parameters to be used for compression.
+ *
+ * If multiple compression parameters might be used, the caller must call
+ * ZSTD_CCtxWorkspaceBound() for each set of parameters and use the maximum
+ * size.
+ *
+ * Return:   A lower bound on the size of the workspace that is passed to
+ *           ZSTD_initCCtx().
+ */
+size_t ZSTD_CCtxWorkspaceBound(ZSTD_compressionParameters cParams);
+
+/**
+ * struct ZSTD_CCtx - the zstd compression context
+ *
+ * When compressing many times it is recommended to allocate a context just once
+ * and reuse it for each successive compression operation.
+ */
+typedef struct ZSTD_CCtx_s ZSTD_CCtx;
+/**
+ * ZSTD_initCCtx() - initialize a zstd compression context
+ * @workspace:     The workspace to emplace the context into. It must outlive
+ *                 the returned context.
+ * @workspaceSize: The size of workspace. Use ZSTD_CCtxWorkspaceBound() to
+ *                 determine how large the workspace must be.
+ *
+ * Return:         A compression context emplaced into workspace.
+ */
+ZSTD_CCtx *ZSTD_initCCtx(void *workspace, size_t workspaceSize);
+
+/**
+ * ZSTD_compressCCtx() - compress src into dst
+ * @ctx:         The context. Must have been initialized with a workspace at
+ *               least as large as ZSTD_CCtxWorkspaceBound(params.cParams).
+ * @dst:         The buffer to compress src into.
+ * @dstCapacity: The size of the destination buffer. May be any size, but
+ *               ZSTD_compressBound(srcSize) is guaranteed to be large enough.
+ * @src:         The data to compress.
+ * @srcSize:     The size of the data to compress.
+ * @params:      The parameters to use for compression. See ZSTD_getParams().
+ *
+ * Return:       The compressed size or an error, which can be checked using
+ *               ZSTD_isError().
+ */
+size_t ZSTD_compressCCtx(ZSTD_CCtx *ctx, void *dst, size_t dstCapacity,
+	const void *src, size_t srcSize, ZSTD_parameters params);
+
+/**
+ * ZSTD_DCtxWorkspaceBound() - amount of memory needed to initialize a ZSTD_DCtx
+ *
+ * Return: A lower bound on the size of the workspace that is passed to
+ *         ZSTD_initDCtx().
+ */
+size_t ZSTD_DCtxWorkspaceBound(void);
+
+/**
+ * struct ZSTD_DCtx - the zstd decompression context
+ *
+ * When decompressing many times it is recommended to allocate a context just
+ * once and reuse it for each successive decompression operation.
+ */
+typedef struct ZSTD_DCtx_s ZSTD_DCtx;
+/**
+ * ZSTD_initDCtx() - initialize a zstd decompression context
+ * @workspace:     The workspace to emplace the context into. It must outlive
+ *                 the returned context.
+ * @workspaceSize: The size of workspace. Use ZSTD_DCtxWorkspaceBound() to
+ *                 determine how large the workspace must be.
+ *
+ * Return:         A decompression context emplaced into workspace.
+ */
+ZSTD_DCtx *ZSTD_initDCtx(void *workspace, size_t workspaceSize);
+
+/**
+ * ZSTD_decompressDCtx() - decompress zstd compressed src into dst
+ * @ctx:         The decompression context.
+ * @dst:         The buffer to decompress src into.
+ * @dstCapacity: The size of the destination buffer. Must be at least as large
+ *               as the decompressed size. If the caller cannot upper bound the
+ *               decompressed size, then it's better to use the streaming API.
+ * @src:         The zstd compressed data to decompress. Multiple concatenated
+ *               frames and skippable frames are allowed.
+ * @srcSize:     The exact size of the data to decompress.
+ *
+ * Return:       The decompressed size or an error, which can be checked using
+ *               ZSTD_isError().
+ */
+size_t ZSTD_decompressDCtx(ZSTD_DCtx *ctx, void *dst, size_t dstCapacity,
+	const void *src, size_t srcSize);
+
+/*-************************
+ * Simple dictionary API
+ **************************/
+
+/**
+ * ZSTD_compress_usingDict() - compress src into dst using a dictionary
+ * @ctx:         The context. Must have been initialized with a workspace at
+ *               least as large as ZSTD_CCtxWorkspaceBound(params.cParams).
+ * @dst:         The buffer to compress src into.
+ * @dstCapacity: The size of the destination buffer. May be any size, but
+ *               ZSTD_compressBound(srcSize) is guaranteed to be large enough.
+ * @src:         The data to compress.
+ * @srcSize:     The size of the data to compress.
+ * @dict:        The dictionary to use for compression.
+ * @dictSize:    The size of the dictionary.
+ * @params:      The parameters to use for compression. See ZSTD_getParams().
+ *
+ * Compression using a predefined dictionary. The same dictionary must be used
+ * during decompression.
+ *
+ * Return:       The compressed size or an error, which can be checked using
+ *               ZSTD_isError().
+ */
+size_t ZSTD_compress_usingDict(ZSTD_CCtx *ctx, void *dst, size_t dstCapacity,
+	const void *src, size_t srcSize, const void *dict, size_t dictSize,
+	ZSTD_parameters params);
+
+/**
+ * ZSTD_decompress_usingDict() - decompress src into dst using a dictionary
+ * @ctx:         The decompression context.
+ * @dst:         The buffer to decompress src into.
+ * @dstCapacity: The size of the destination buffer. Must be at least as large
+ *               as the decompressed size. If the caller cannot upper bound the
+ *               decompressed size, then it's better to use the streaming API.
+ * @src:         The zstd compressed data to decompress. Multiple concatenated
+ *               frames and skippable frames are allowed.
+ * @srcSize:     The exact size of the data to decompress.
+ * @dict:        The dictionary to use for decompression. The same dictionary
+ *               must've been used to compress the data.
+ * @dictSize:    The size of the dictionary.
+ *
+ * Return:       The decompressed size or an error, which can be checked using
+ *               ZSTD_isError().
+ */
+size_t ZSTD_decompress_usingDict(ZSTD_DCtx *ctx, void *dst, size_t dstCapacity,
+	const void *src, size_t srcSize, const void *dict, size_t dictSize);
+
+/*-**************************
+ * Fast dictionary API
+ ***************************/
+
+/**
+ * ZSTD_CDictWorkspaceBound() - memory needed to initialize a ZSTD_CDict
+ * @cParams: The compression parameters to be used for compression.
+ *
+ * Return:   A lower bound on the size of the workspace that is passed to
+ *           ZSTD_initCDict().
+ */
+size_t ZSTD_CDictWorkspaceBound(ZSTD_compressionParameters cParams);
+
+/**
+ * struct ZSTD_CDict - a digested dictionary to be used for compression
+ */
+typedef struct ZSTD_CDict_s ZSTD_CDict;
+
+/**
+ * ZSTD_initCDict() - initialize a digested dictionary for compression
+ * @dictBuffer:    The dictionary to digest. The buffer is referenced by the
+ *                 ZSTD_CDict so it must outlive the returned ZSTD_CDict.
+ * @dictSize:      The size of the dictionary.
+ * @params:        The parameters to use for compression. See ZSTD_getParams().
+ * @workspace:     The workspace. It must outlive the returned ZSTD_CDict.
+ * @workspaceSize: The workspace size. Must be at least
+ *                 ZSTD_CDictWorkspaceBound(params.cParams).
+ *
+ * When compressing multiple messages / blocks with the same dictionary it is
+ * recommended to load it just once. The ZSTD_CDict merely references the
+ * dictBuffer, so it must outlive the returned ZSTD_CDict.
+ *
+ * Return:         The digested dictionary emplaced into workspace.
+ */
+ZSTD_CDict *ZSTD_initCDict(const void *dictBuffer, size_t dictSize,
+	ZSTD_parameters params, void *workspace, size_t workspaceSize);
+
+/**
+ * ZSTD_compress_usingCDict() - compress src into dst using a ZSTD_CDict
+ * @ctx:         The context. Must have been initialized with a workspace at
+ *               least as large as ZSTD_CCtxWorkspaceBound(cParams) where
+ *               cParams are the compression parameters used to initialize the
+ *               cdict.
+ * @dst:         The buffer to compress src into.
+ * @dstCapacity: The size of the destination buffer. May be any size, but
+ *               ZSTD_compressBound(srcSize) is guaranteed to be large enough.
+ * @src:         The data to compress.
+ * @srcSize:     The size of the data to compress.
+ * @cdict:       The digested dictionary to use for compression.
+ * @params:      The parameters to use for compression. See ZSTD_getParams().
+ *
+ * Compression using a digested dictionary. The same dictionary must be used
+ * during decompression.
+ *
+ * Return:       The compressed size or an error, which can be checked using
+ *               ZSTD_isError().
+ */
+size_t ZSTD_compress_usingCDict(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity,
+	const void *src, size_t srcSize, const ZSTD_CDict *cdict);
+
+
+/**
+ * ZSTD_DDictWorkspaceBound() - memory needed to initialize a ZSTD_DDict
+ *
+ * Return:  A lower bound on the size of the workspace that is passed to
+ *          ZSTD_initDDict().
+ */
+size_t ZSTD_DDictWorkspaceBound(void);
+
+/**
+ * struct ZSTD_DDict - a digested dictionary to be used for decompression
+ */
+typedef struct ZSTD_DDict_s ZSTD_DDict;
+
+/**
+ * ZSTD_initDDict() - initialize a digested dictionary for decompression
+ * @dictBuffer:    The dictionary to digest. The buffer is referenced by the
+ *                 ZSTD_DDict so it must outlive the returned ZSTD_DDict.
+ * @dictSize:      The size of the dictionary.
+ * @workspace:     The workspace. It must outlive the returned ZSTD_DDict.
+ * @workspaceSize: The workspace size. Must be at least
+ *                 ZSTD_DDictWorkspaceBound().
+ *
+ * When decompressing multiple messages / blocks with the same dictionary it is
+ * recommended to load it just once. The ZSTD_DDict merely references the
+ * dictBuffer, so it must outlive the returned ZSTD_DDict.
+ *
+ * Return:         The digested dictionary emplaced into workspace.
+ */
+ZSTD_DDict *ZSTD_initDDict(const void *dictBuffer, size_t dictSize,
+	void *workspace, size_t workspaceSize);
+
+/**
+ * ZSTD_decompress_usingDDict() - decompress src into dst using a ZSTD_DDict
+ * @ctx:         The decompression context.
+ * @dst:         The buffer to decompress src into.
+ * @dstCapacity: The size of the destination buffer. Must be at least as large
+ *               as the decompressed size. If the caller cannot upper bound the
+ *               decompressed size, then it's better to use the streaming API.
+ * @src:         The zstd compressed data to decompress. Multiple concatenated
+ *               frames and skippable frames are allowed.
+ * @srcSize:     The exact size of the data to decompress.
+ * @ddict:       The digested dictionary to use for decompression. The same
+ *               dictionary must've been used to compress the data.
+ *
+ * Return:       The decompressed size or an error, which can be checked using
+ *               ZSTD_isError().
+ */
+size_t ZSTD_decompress_usingDDict(ZSTD_DCtx *dctx, void *dst,
+	size_t dstCapacity, const void *src, size_t srcSize,
+	const ZSTD_DDict *ddict);
+
+
+/*-**************************
+ * Streaming
+ ***************************/
+
+/**
+ * struct ZSTD_inBuffer - input buffer for streaming
+ * @src:  Start of the input buffer.
+ * @size: Size of the input buffer.
+ * @pos:  Position where reading stopped. Will be updated.
+ *        Necessarily 0 <= pos <= size.
+ */
+typedef struct ZSTD_inBuffer_s {
+	const void *src;
+	size_t size;
+	size_t pos;
+} ZSTD_inBuffer;
+
+/**
+ * struct ZSTD_outBuffer - output buffer for streaming
+ * @dst:  Start of the output buffer.
+ * @size: Size of the output buffer.
+ * @pos:  Position where writing stopped. Will be updated.
+ *        Necessarily 0 <= pos <= size.
+ */
+typedef struct ZSTD_outBuffer_s {
+	void *dst;
+	size_t size;
+	size_t pos;
+} ZSTD_outBuffer;
+
+
+
+/*-*****************************************************************************
+ * Streaming compression - HowTo
+ *
+ * A ZSTD_CStream object is required to track streaming operation.
+ * Use ZSTD_initCStream() to initialize a ZSTD_CStream object.
+ * ZSTD_CStream objects can be reused multiple times on consecutive compression
+ * operations. It is recommended to re-use ZSTD_CStream in situations where many
+ * streaming operations will be achieved consecutively. Use one separate
+ * ZSTD_CStream per thread for parallel execution.
+ *
+ * Use ZSTD_compressStream() repetitively to consume input stream.
+ * The function will automatically update both `pos` fields.
+ * Note that it may not consume the entire input, in which case `pos < size`,
+ * and it's up to the caller to present again remaining data.
+ * It returns a hint for the preferred number of bytes to use as an input for
+ * the next function call.
+ *
+ * At any moment, it's possible to flush whatever data remains within internal
+ * buffer, using ZSTD_flushStream(). `output->pos` will be updated. There might
+ * still be some content left within the internal buffer if `output->size` is
+ * too small. It returns the number of bytes left in the internal buffer and
+ * must be called until it returns 0.
+ *
+ * ZSTD_endStream() instructs to finish a frame. It will perform a flush and
+ * write frame epilogue. The epilogue is required for decoders to consider a
+ * frame completed. Similar to ZSTD_flushStream(), it may not be able to flush
+ * the full content if `output->size` is too small. In which case, call again
+ * ZSTD_endStream() to complete the flush. It returns the number of bytes left
+ * in the internal buffer and must be called until it returns 0.
+ ******************************************************************************/
+
+/**
+ * ZSTD_CStreamWorkspaceBound() - memory needed to initialize a ZSTD_CStream
+ * @cParams: The compression parameters to be used for compression.
+ *
+ * Return:   A lower bound on the size of the workspace that is passed to
+ *           ZSTD_initCStream() and ZSTD_initCStream_usingCDict().
+ */
+size_t ZSTD_CStreamWorkspaceBound(ZSTD_compressionParameters cParams);
+
+/**
+ * struct ZSTD_CStream - the zstd streaming compression context
+ */
+typedef struct ZSTD_CStream_s ZSTD_CStream;
+
+/*===== ZSTD_CStream management functions =====*/
+/**
+ * ZSTD_initCStream() - initialize a zstd streaming compression context
+ * @params:         The zstd compression parameters.
+ * @pledgedSrcSize: If params.fParams.contentSizeFlag == 1 then the caller must
+ *                  pass the source size (zero means empty source). Otherwise,
+ *                  the caller may optionally pass the source size, or zero if
+ *                  unknown.
+ * @workspace:      The workspace to emplace the context into. It must outlive
+ *                  the returned context.
+ * @workspaceSize:  The size of workspace.
+ *                  Use ZSTD_CStreamWorkspaceBound(params.cParams) to determine
+ *                  how large the workspace must be.
+ *
+ * Return:          The zstd streaming compression context.
+ */
+ZSTD_CStream *ZSTD_initCStream(ZSTD_parameters params,
+	unsigned long long pledgedSrcSize, void *workspace,
+	size_t workspaceSize);
+
+/**
+ * ZSTD_initCStream_usingCDict() - initialize a streaming compression context
+ * @cdict:          The digested dictionary to use for compression.
+ * @pledgedSrcSize: Optionally the source size, or zero if unknown.
+ * @workspace:      The workspace to emplace the context into. It must outlive
+ *                  the returned context.
+ * @workspaceSize:  The size of workspace. Call ZSTD_CStreamWorkspaceBound()
+ *                  with the cParams used to initialize the cdict to determine
+ *                  how large the workspace must be.
+ *
+ * Return:          The zstd streaming compression context.
+ */
+ZSTD_CStream *ZSTD_initCStream_usingCDict(const ZSTD_CDict *cdict,
+	unsigned long long pledgedSrcSize, void *workspace,
+	size_t workspaceSize);
+
+/*===== Streaming compression functions =====*/
+/**
+ * ZSTD_resetCStream() - reset the context using parameters from creation
+ * @zcs:            The zstd streaming compression context to reset.
+ * @pledgedSrcSize: Optionally the source size, or zero if unknown.
+ *
+ * Resets the context using the parameters from creation. Skips dictionary
+ * loading, since it can be reused. If `pledgedSrcSize` is non-zero the frame
+ * content size is always written into the frame header.
+ *
+ * Return:          Zero or an error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_resetCStream(ZSTD_CStream *zcs, unsigned long long pledgedSrcSize);
+/**
+ * ZSTD_compressStream() - streaming compress some of input into output
+ * @zcs:    The zstd streaming compression context.
+ * @output: Destination buffer. `output->pos` is updated to indicate how much
+ *          compressed data was written.
+ * @input:  Source buffer. `input->pos` is updated to indicate how much data was
+ *          read. Note that it may not consume the entire input, in which case
+ *          `input->pos < input->size`, and it's up to the caller to present
+ *          remaining data again.
+ *
+ * The `input` and `output` buffers may be any size. Guaranteed to make some
+ * forward progress if `input` and `output` are not empty.
+ *
+ * Return:  A hint for the number of bytes to use as the input for the next
+ *          function call or an error, which can be checked using
+ *          ZSTD_isError().
+ */
+size_t ZSTD_compressStream(ZSTD_CStream *zcs, ZSTD_outBuffer *output,
+	ZSTD_inBuffer *input);
+/**
+ * ZSTD_flushStream() - flush internal buffers into output
+ * @zcs:    The zstd streaming compression context.
+ * @output: Destination buffer. `output->pos` is updated to indicate how much
+ *          compressed data was written.
+ *
+ * ZSTD_flushStream() must be called until it returns 0, meaning all the data
+ * has been flushed. Since ZSTD_flushStream() causes a block to be ended,
+ * calling it too often will degrade the compression ratio.
+ *
+ * Return:  The number of bytes still present within internal buffers or an
+ *          error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_flushStream(ZSTD_CStream *zcs, ZSTD_outBuffer *output);
+/**
+ * ZSTD_endStream() - flush internal buffers into output and end the frame
+ * @zcs:    The zstd streaming compression context.
+ * @output: Destination buffer. `output->pos` is updated to indicate how much
+ *          compressed data was written.
+ *
+ * ZSTD_endStream() must be called until it returns 0, meaning all the data has
+ * been flushed and the frame epilogue has been written.
+ *
+ * Return:  The number of bytes still present within internal buffers or an
+ *          error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_endStream(ZSTD_CStream *zcs, ZSTD_outBuffer *output);
+
+/**
+ * ZSTD_CStreamInSize() - recommended size for the input buffer
+ *
+ * Return: The recommended size for the input buffer.
+ */
+size_t ZSTD_CStreamInSize(void);
+/**
+ * ZSTD_CStreamOutSize() - recommended size for the output buffer
+ *
+ * When the output buffer is at least this large, it is guaranteed to be large
+ * enough to flush at least one complete compressed block.
+ *
+ * Return: The recommended size for the output buffer.
+ */
+size_t ZSTD_CStreamOutSize(void);
+
+
+
+/*-*****************************************************************************
+ * Streaming decompression - HowTo
+ *
+ * A ZSTD_DStream object is required to track streaming operations.
+ * Use ZSTD_initDStream() to initialize a ZSTD_DStream object.
+ * ZSTD_DStream objects can be re-used multiple times.
+ *
+ * Use ZSTD_decompressStream() repetitively to consume your input.
+ * The function will update both `pos` fields.
+ * If `input->pos < input->size`, some input has not been consumed.
+ * It's up to the caller to present again remaining data.
+ * If `output->pos < output->size`, decoder has flushed everything it could.
+ * Returns 0 iff a frame is completely decoded and fully flushed.
+ * Otherwise it returns a suggested next input size that will never load more
+ * than the current frame.
+ ******************************************************************************/
+
+/**
+ * ZSTD_DStreamWorkspaceBound() - memory needed to initialize a ZSTD_DStream
+ * @maxWindowSize: The maximum window size allowed for compressed frames.
+ *
+ * Return:         A lower bound on the size of the workspace that is passed to
+ *                 ZSTD_initDStream() and ZSTD_initDStream_usingDDict().
+ */
+size_t ZSTD_DStreamWorkspaceBound(size_t maxWindowSize);
+
+/**
+ * struct ZSTD_DStream - the zstd streaming decompression context
+ */
+typedef struct ZSTD_DStream_s ZSTD_DStream;
+/*===== ZSTD_DStream management functions =====*/
+/**
+ * ZSTD_initDStream() - initialize a zstd streaming decompression context
+ * @maxWindowSize: The maximum window size allowed for compressed frames.
+ * @workspace:     The workspace to emplace the context into. It must outlive
+ *                 the returned context.
+ * @workspaceSize: The size of workspace.
+ *                 Use ZSTD_DStreamWorkspaceBound(maxWindowSize) to determine
+ *                 how large the workspace must be.
+ *
+ * Return:         The zstd streaming decompression context.
+ */
+ZSTD_DStream *ZSTD_initDStream(size_t maxWindowSize, void *workspace,
+	size_t workspaceSize);
+/**
+ * ZSTD_initDStream_usingDDict() - initialize streaming decompression context
+ * @maxWindowSize: The maximum window size allowed for compressed frames.
+ * @ddict:         The digested dictionary to use for decompression.
+ * @workspace:     The workspace to emplace the context into. It must outlive
+ *                 the returned context.
+ * @workspaceSize: The size of workspace.
+ *                 Use ZSTD_DStreamWorkspaceBound(maxWindowSize) to determine
+ *                 how large the workspace must be.
+ *
+ * Return:         The zstd streaming decompression context.
+ */
+ZSTD_DStream *ZSTD_initDStream_usingDDict(size_t maxWindowSize,
+	const ZSTD_DDict *ddict, void *workspace, size_t workspaceSize);
+
+/*===== Streaming decompression functions =====*/
+/**
+ * ZSTD_resetDStream() - reset the context using parameters from creation
+ * @zds:   The zstd streaming decompression context to reset.
+ *
+ * Resets the context using the parameters from creation. Skips dictionary
+ * loading, since it can be reused.
+ *
+ * Return: Zero or an error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_resetDStream(ZSTD_DStream *zds);
+/**
+ * ZSTD_decompressStream() - streaming decompress some of input into output
+ * @zds:    The zstd streaming decompression context.
+ * @output: Destination buffer. `output.pos` is updated to indicate how much
+ *          decompressed data was written.
+ * @input:  Source buffer. `input.pos` is updated to indicate how much data was
+ *          read. Note that it may not consume the entire input, in which case
+ *          `input.pos < input.size`, and it's up to the caller to present
+ *          remaining data again.
+ *
+ * The `input` and `output` buffers may be any size. Guaranteed to make some
+ * forward progress if `input` and `output` are not empty.
+ * ZSTD_decompressStream() will not consume the last byte of the frame until
+ * the entire frame is flushed.
+ *
+ * Return:  Returns 0 iff a frame is completely decoded and fully flushed.
+ *          Otherwise returns a hint for the number of bytes to use as the input
+ *          for the next function call or an error, which can be checked using
+ *          ZSTD_isError(). The size hint will never load more than the frame.
+ */
+size_t ZSTD_decompressStream(ZSTD_DStream *zds, ZSTD_outBuffer *output,
+	ZSTD_inBuffer *input);
+
+/**
+ * ZSTD_DStreamInSize() - recommended size for the input buffer
+ *
+ * Return: The recommended size for the input buffer.
+ */
+size_t ZSTD_DStreamInSize(void);
+/**
+ * ZSTD_DStreamOutSize() - recommended size for the output buffer
+ *
+ * When the output buffer is at least this large, it is guaranteed to be large
+ * enough to flush at least one complete decompressed block.
+ *
+ * Return: The recommended size for the output buffer.
+ */
+size_t ZSTD_DStreamOutSize(void);
+
+
+/* --- Constants ---*/
+#define ZSTD_MAGICNUMBER            0xFD2FB528   /* >= v0.8.0 */
+#define ZSTD_MAGIC_SKIPPABLE_START  0x184D2A50U
+
+#define ZSTD_CONTENTSIZE_UNKNOWN (0ULL - 1)
+#define ZSTD_CONTENTSIZE_ERROR   (0ULL - 2)
+
+#define ZSTD_WINDOWLOG_MAX_32  27
+#define ZSTD_WINDOWLOG_MAX_64  27
+#define ZSTD_WINDOWLOG_MAX \
+	((unsigned int)(sizeof(size_t) == 4 \
+		? ZSTD_WINDOWLOG_MAX_32 \
+		: ZSTD_WINDOWLOG_MAX_64))
+#define ZSTD_WINDOWLOG_MIN 10
+#define ZSTD_HASHLOG_MAX ZSTD_WINDOWLOG_MAX
+#define ZSTD_HASHLOG_MIN        6
+#define ZSTD_CHAINLOG_MAX     (ZSTD_WINDOWLOG_MAX+1)
+#define ZSTD_CHAINLOG_MIN      ZSTD_HASHLOG_MIN
+#define ZSTD_HASHLOG3_MAX      17
+#define ZSTD_SEARCHLOG_MAX    (ZSTD_WINDOWLOG_MAX-1)
+#define ZSTD_SEARCHLOG_MIN      1
+/* only for ZSTD_fast, other strategies are limited to 6 */
+#define ZSTD_SEARCHLENGTH_MAX   7
+/* only for ZSTD_btopt, other strategies are limited to 4 */
+#define ZSTD_SEARCHLENGTH_MIN   3
+#define ZSTD_TARGETLENGTH_MIN   4
+#define ZSTD_TARGETLENGTH_MAX 999
+
+/* for static allocation */
+#define ZSTD_FRAMEHEADERSIZE_MAX 18
+#define ZSTD_FRAMEHEADERSIZE_MIN  6
+static const size_t ZSTD_frameHeaderSize_prefix = 5;
+static const size_t ZSTD_frameHeaderSize_min = ZSTD_FRAMEHEADERSIZE_MIN;
+static const size_t ZSTD_frameHeaderSize_max = ZSTD_FRAMEHEADERSIZE_MAX;
+/* magic number + skippable frame length */
+static const size_t ZSTD_skippableHeaderSize = 8;
+
+
+/*-*************************************
+ * Compressed size functions
+ **************************************/
+
+/**
+ * ZSTD_findFrameCompressedSize() - returns the size of a compressed frame
+ * @src:     Source buffer. It should point to the start of a zstd encoded frame
+ *           or a skippable frame.
+ * @srcSize: The size of the source buffer. It must be at least as large as the
+ *           size of the frame.
+ *
+ * Return:   The compressed size of the frame pointed to by `src` or an error,
+ *           which can be check with ZSTD_isError().
+ *           Suitable to pass to ZSTD_decompress() or similar functions.
+ */
+size_t ZSTD_findFrameCompressedSize(const void *src, size_t srcSize);
+
+/*-*************************************
+ * Decompressed size functions
+ **************************************/
+/**
+ * ZSTD_getFrameContentSize() - returns the content size in a zstd frame header
+ * @src:     It should point to the start of a zstd encoded frame.
+ * @srcSize: The size of the source buffer. It must be at least as large as the
+ *           frame header. `ZSTD_frameHeaderSize_max` is always large enough.
+ *
+ * Return:   The frame content size stored in the frame header if known.
+ *           `ZSTD_CONTENTSIZE_UNKNOWN` if the content size isn't stored in the
+ *           frame header. `ZSTD_CONTENTSIZE_ERROR` on invalid input.
+ */
+unsigned long long ZSTD_getFrameContentSize(const void *src, size_t srcSize);
+
+/**
+ * ZSTD_findDecompressedSize() - returns decompressed size of a series of frames
+ * @src:     It should point to the start of a series of zstd encoded and/or
+ *           skippable frames.
+ * @srcSize: The exact size of the series of frames.
+ *
+ * If any zstd encoded frame in the series doesn't have the frame content size
+ * set, `ZSTD_CONTENTSIZE_UNKNOWN` is returned. But frame content size is always
+ * set when using ZSTD_compress(). The decompressed size can be very large.
+ * If the source is untrusted, the decompressed size could be wrong or
+ * intentionally modified. Always ensure the result fits within the
+ * application's authorized limits. ZSTD_findDecompressedSize() handles multiple
+ * frames, and so it must traverse the input to read each frame header. This is
+ * efficient as most of the data is skipped, however it does mean that all frame
+ * data must be present and valid.
+ *
+ * Return:   Decompressed size of all the data contained in the frames if known.
+ *           `ZSTD_CONTENTSIZE_UNKNOWN` if the decompressed size is unknown.
+ *           `ZSTD_CONTENTSIZE_ERROR` if an error occurred.
+ */
+unsigned long long ZSTD_findDecompressedSize(const void *src, size_t srcSize);
+
+/*-*************************************
+ * Advanced compression functions
+ **************************************/
+/**
+ * ZSTD_checkCParams() - ensure parameter values remain within authorized range
+ * @cParams: The zstd compression parameters.
+ *
+ * Return:   Zero or an error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_checkCParams(ZSTD_compressionParameters cParams);
+
+/**
+ * ZSTD_adjustCParams() - optimize parameters for a given srcSize and dictSize
+ * @srcSize:  Optionally the estimated source size, or zero if unknown.
+ * @dictSize: Optionally the estimated dictionary size, or zero if unknown.
+ *
+ * Return:    The optimized parameters.
+ */
+ZSTD_compressionParameters ZSTD_adjustCParams(
+	ZSTD_compressionParameters cParams, unsigned long long srcSize,
+	size_t dictSize);
+
+/*--- Advanced decompression functions ---*/
+
+/**
+ * ZSTD_isFrame() - returns true iff the buffer starts with a valid frame
+ * @buffer: The source buffer to check.
+ * @size:   The size of the source buffer, must be at least 4 bytes.
+ *
+ * Return: True iff the buffer starts with a zstd or skippable frame identifier.
+ */
+unsigned int ZSTD_isFrame(const void *buffer, size_t size);
+
+/**
+ * ZSTD_getDictID_fromDict() - returns the dictionary id stored in a dictionary
+ * @dict:     The dictionary buffer.
+ * @dictSize: The size of the dictionary buffer.
+ *
+ * Return:    The dictionary id stored within the dictionary or 0 if the
+ *            dictionary is not a zstd dictionary. If it returns 0 the
+ *            dictionary can still be loaded as a content-only dictionary.
+ */
+unsigned int ZSTD_getDictID_fromDict(const void *dict, size_t dictSize);
+
+/**
+ * ZSTD_getDictID_fromDDict() - returns the dictionary id stored in a ZSTD_DDict
+ * @ddict: The ddict to find the id of.
+ *
+ * Return: The dictionary id stored within `ddict` or 0 if the dictionary is not
+ *         a zstd dictionary. If it returns 0 `ddict` will be loaded as a
+ *         content-only dictionary.
+ */
+unsigned int ZSTD_getDictID_fromDDict(const ZSTD_DDict *ddict);
+
+/**
+ * ZSTD_getDictID_fromFrame() - returns the dictionary id stored in a zstd frame
+ * @src:     Source buffer. It must be a zstd encoded frame.
+ * @srcSize: The size of the source buffer. It must be at least as large as the
+ *           frame header. `ZSTD_frameHeaderSize_max` is always large enough.
+ *
+ * Return:   The dictionary id required to decompress the frame stored within
+ *           `src` or 0 if the dictionary id could not be decoded. It can return
+ *           0 if the frame does not require a dictionary, the dictionary id
+ *           wasn't stored in the frame, `src` is not a zstd frame, or `srcSize`
+ *           is too small.
+ */
+unsigned int ZSTD_getDictID_fromFrame(const void *src, size_t srcSize);
+
+/**
+ * struct ZSTD_frameParams - zstd frame parameters stored in the frame header
+ * @frameContentSize: The frame content size, or 0 if not present.
+ * @windowSize:       The window size, or 0 if the frame is a skippable frame.
+ * @dictID:           The dictionary id, or 0 if not present.
+ * @checksumFlag:     Whether a checksum was used.
+ */
+typedef struct {
+	unsigned long long frameContentSize;
+	unsigned int windowSize;
+	unsigned int dictID;
+	unsigned int checksumFlag;
+} ZSTD_frameParams;
+
+/**
+ * ZSTD_getFrameParams() - extracts parameters from a zstd or skippable frame
+ * @fparamsPtr: On success the frame parameters are written here.
+ * @src:        The source buffer. It must point to a zstd or skippable frame.
+ * @srcSize:    The size of the source buffer. `ZSTD_frameHeaderSize_max` is
+ *              always large enough to succeed.
+ *
+ * Return:      0 on success. If more data is required it returns how many bytes
+ *              must be provided to make forward progress. Otherwise it returns
+ *              an error, which can be checked using ZSTD_isError().
+ */
+size_t ZSTD_getFrameParams(ZSTD_frameParams *fparamsPtr, const void *src,
+	size_t srcSize);
+
+/*-*****************************************************************************
+ * Buffer-less and synchronous inner streaming functions
+ *
+ * This is an advanced API, giving full control over buffer management, for
+ * users which need direct control over memory.
+ * But it's also a complex one, with many restrictions (documented below).
+ * Prefer using normal streaming API for an easier experience
+ ******************************************************************************/
+
+/*-*****************************************************************************
+ * Buffer-less streaming compression (synchronous mode)
+ *
+ * A ZSTD_CCtx object is required to track streaming operations.
+ * Use ZSTD_initCCtx() to initialize a context.
+ * ZSTD_CCtx object can be re-used multiple times within successive compression
+ * operations.
+ *
+ * Start by initializing a context.
+ * Use ZSTD_compressBegin(), or ZSTD_compressBegin_usingDict() for dictionary
+ * compression,
+ * or ZSTD_compressBegin_advanced(), for finer parameter control.
+ * It's also possible to duplicate a reference context which has already been
+ * initialized, using ZSTD_copyCCtx()
+ *
+ * Then, consume your input using ZSTD_compressContinue().
+ * There are some important considerations to keep in mind when using this
+ * advanced function :
+ * - ZSTD_compressContinue() has no internal buffer. It uses externally provided
+ *   buffer only.
+ * - Interface is synchronous : input is consumed entirely and produce 1+
+ *   (or more) compressed blocks.
+ * - Caller must ensure there is enough space in `dst` to store compressed data
+ *   under worst case scenario. Worst case evaluation is provided by
+ *   ZSTD_compressBound().
+ *   ZSTD_compressContinue() doesn't guarantee recover after a failed
+ *   compression.
+ * - ZSTD_compressContinue() presumes prior input ***is still accessible and
+ *   unmodified*** (up to maximum distance size, see WindowLog).
+ *   It remembers all previous contiguous blocks, plus one separated memory
+ *   segment (which can itself consists of multiple contiguous blocks)
+ * - ZSTD_compressContinue() detects that prior input has been overwritten when
+ *   `src` buffer overlaps. In which case, it will "discard" the relevant memory
+ *   section from its history.
+ *
+ * Finish a frame with ZSTD_compressEnd(), which will write the last block(s)
+ * and optional checksum. It's possible to use srcSize==0, in which case, it
+ * will write a final empty block to end the frame. Without last block mark,
+ * frames will be considered unfinished (corrupted) by decoders.
+ *
+ * `ZSTD_CCtx` object can be re-used (ZSTD_compressBegin()) to compress some new
+ * frame.
+ ******************************************************************************/
+
+/*=====   Buffer-less streaming compression functions  =====*/
+size_t ZSTD_compressBegin(ZSTD_CCtx *cctx, int compressionLevel);
+size_t ZSTD_compressBegin_usingDict(ZSTD_CCtx *cctx, const void *dict,
+	size_t dictSize, int compressionLevel);
+size_t ZSTD_compressBegin_advanced(ZSTD_CCtx *cctx, const void *dict,
+	size_t dictSize, ZSTD_parameters params,
+	unsigned long long pledgedSrcSize);
+size_t ZSTD_copyCCtx(ZSTD_CCtx *cctx, const ZSTD_CCtx *preparedCCtx,
+	unsigned long long pledgedSrcSize);
+size_t ZSTD_compressBegin_usingCDict(ZSTD_CCtx *cctx, const ZSTD_CDict *cdict,
+	unsigned long long pledgedSrcSize);
+size_t ZSTD_compressContinue(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity,
+	const void *src, size_t srcSize);
+size_t ZSTD_compressEnd(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity,
+	const void *src, size_t srcSize);
+
+
+
+/*-*****************************************************************************
+ * Buffer-less streaming decompression (synchronous mode)
+ *
+ * A ZSTD_DCtx object is required to track streaming operations.
+ * Use ZSTD_initDCtx() to initialize a context.
+ * A ZSTD_DCtx object can be re-used multiple times.
+ *
+ * First typical operation is to retrieve frame parameters, using
+ * ZSTD_getFrameParams(). It fills a ZSTD_frameParams structure which provide
+ * important information to correctly decode the frame, such as the minimum
+ * rolling buffer size to allocate to decompress data (`windowSize`), and the
+ * dictionary ID used.
+ * Note: content size is optional, it may not be present. 0 means unknown.
+ * Note that these values could be wrong, either because of data malformation,
+ * or because an attacker is spoofing deliberate false information. As a
+ * consequence, check that values remain within valid application range,
+ * especially `windowSize`, before allocation. Each application can set its own
+ * limit, depending on local restrictions. For extended interoperability, it is
+ * recommended to support at least 8 MB.
+ * Frame parameters are extracted from the beginning of the compressed frame.
+ * Data fragment must be large enough to ensure successful decoding, typically
+ * `ZSTD_frameHeaderSize_max` bytes.
+ * Result: 0: successful decoding, the `ZSTD_frameParams` structure is filled.
+ *        >0: `srcSize` is too small, provide at least this many bytes.
+ *        errorCode, which can be tested using ZSTD_isError().
+ *
+ * Start decompression, with ZSTD_decompressBegin() or
+ * ZSTD_decompressBegin_usingDict(). Alternatively, you can copy a prepared
+ * context, using ZSTD_copyDCtx().
+ *
+ * Then use ZSTD_nextSrcSizeToDecompress() and ZSTD_decompressContinue()
+ * alternatively.
+ * ZSTD_nextSrcSizeToDecompress() tells how many bytes to provide as 'srcSize'
+ * to ZSTD_decompressContinue().
+ * ZSTD_decompressContinue() requires this _exact_ amount of bytes, or it will
+ * fail.
+ *
+ * The result of ZSTD_decompressContinue() is the number of bytes regenerated
+ * within 'dst' (necessarily <= dstCapacity). It can be zero, which is not an
+ * error; it just means ZSTD_decompressContinue() has decoded some metadata
+ * item. It can also be an error code, which can be tested with ZSTD_isError().
+ *
+ * ZSTD_decompressContinue() needs previous data blocks during decompression, up
+ * to `windowSize`. They should preferably be located contiguously, prior to
+ * current block. Alternatively, a round buffer of sufficient size is also
+ * possible. Sufficient size is determined by frame parameters.
+ * ZSTD_decompressContinue() is very sensitive to contiguity, if 2 blocks don't
+ * follow each other, make sure that either the compressor breaks contiguity at
+ * the same place, or that previous contiguous segment is large enough to
+ * properly handle maximum back-reference.
+ *
+ * A frame is fully decoded when ZSTD_nextSrcSizeToDecompress() returns zero.
+ * Context can then be reset to start a new decompression.
+ *
+ * Note: it's possible to know if next input to present is a header or a block,
+ * using ZSTD_nextInputType(). This information is not required to properly
+ * decode a frame.
+ *
+ * == Special case: skippable frames ==
+ *
+ * Skippable frames allow integration of user-defined data into a flow of
+ * concatenated frames. Skippable frames will be ignored (skipped) by a
+ * decompressor. The format of skippable frames is as follows:
+ * a) Skippable frame ID - 4 Bytes, Little endian format, any value from
+ *    0x184D2A50 to 0x184D2A5F
+ * b) Frame Size - 4 Bytes, Little endian format, unsigned 32-bits
+ * c) Frame Content - any content (User Data) of length equal to Frame Size
+ * For skippable frames ZSTD_decompressContinue() always returns 0.
+ * For skippable frames ZSTD_getFrameParams() returns fparamsPtr->windowLog==0
+ * what means that a frame is skippable.
+ * Note: If fparamsPtr->frameContentSize==0, it is ambiguous: the frame might
+ *       actually be a zstd encoded frame with no content. For purposes of
+ *       decompression, it is valid in both cases to skip the frame using
+ *       ZSTD_findFrameCompressedSize() to find its size in bytes.
+ * It also returns frame size as fparamsPtr->frameContentSize.
+ ******************************************************************************/
+
+/*=====   Buffer-less streaming decompression functions  =====*/
+size_t ZSTD_decompressBegin(ZSTD_DCtx *dctx);
+size_t ZSTD_decompressBegin_usingDict(ZSTD_DCtx *dctx, const void *dict,
+	size_t dictSize);
+void   ZSTD_copyDCtx(ZSTD_DCtx *dctx, const ZSTD_DCtx *preparedDCtx);
+size_t ZSTD_nextSrcSizeToDecompress(ZSTD_DCtx *dctx);
+size_t ZSTD_decompressContinue(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity,
+	const void *src, size_t srcSize);
+typedef enum {
+	ZSTDnit_frameHeader,
+	ZSTDnit_blockHeader,
+	ZSTDnit_block,
+	ZSTDnit_lastBlock,
+	ZSTDnit_checksum,
+	ZSTDnit_skippableFrame
+} ZSTD_nextInputType_e;
+ZSTD_nextInputType_e ZSTD_nextInputType(ZSTD_DCtx *dctx);
+
+/*-*****************************************************************************
+ * Block functions
+ *
+ * Block functions produce and decode raw zstd blocks, without frame metadata.
+ * Frame metadata cost is typically ~18 bytes, which can be non-negligible for
+ * very small blocks (< 100 bytes). User will have to take in charge required
+ * information to regenerate data, such as compressed and content sizes.
+ *
+ * A few rules to respect:
+ * - Compressing and decompressing require a context structure
+ *   + Use ZSTD_initCCtx() and ZSTD_initDCtx()
+ * - It is necessary to init context before starting
+ *   + compression : ZSTD_compressBegin()
+ *   + decompression : ZSTD_decompressBegin()
+ *   + variants _usingDict() are also allowed
+ *   + copyCCtx() and copyDCtx() work too
+ * - Block size is limited, it must be <= ZSTD_getBlockSizeMax()
+ *   + If you need to compress more, cut data into multiple blocks
+ *   + Consider using the regular ZSTD_compress() instead, as frame metadata
+ *     costs become negligible when source size is large.
+ * - When a block is considered not compressible enough, ZSTD_compressBlock()
+ *   result will be zero. In which case, nothing is produced into `dst`.
+ *   + User must test for such outcome and deal directly with uncompressed data
+ *   + ZSTD_decompressBlock() doesn't accept uncompressed data as input!!!
+ *   + In case of multiple successive blocks, decoder must be informed of
+ *     uncompressed block existence to follow proper history. Use
+ *     ZSTD_insertBlock() in such a case.
+ ******************************************************************************/
+
+/* Define for static allocation */
+#define ZSTD_BLOCKSIZE_ABSOLUTEMAX (128 * 1024)
+/*=====   Raw zstd block functions  =====*/
+size_t ZSTD_getBlockSizeMax(ZSTD_CCtx *cctx);
+size_t ZSTD_compressBlock(ZSTD_CCtx *cctx, void *dst, size_t dstCapacity,
+	const void *src, size_t srcSize);
+size_t ZSTD_decompressBlock(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity,
+	const void *src, size_t srcSize);
+size_t ZSTD_insertBlock(ZSTD_DCtx *dctx, const void *blockStart,
+	size_t blockSize);
+
+#endif  /* ZSTD_H */
diff --git a/include/lmb.h b/include/lmb.h
new file mode 100644
index 0000000..3b338df
--- /dev/null
+++ b/include/lmb.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _LINUX_LMB_H
+#define _LINUX_LMB_H
+#ifdef __KERNEL__
+
+#include <asm/types.h>
+#include <asm/u-boot.h>
+
+/*
+ * Logical memory blocks.
+ *
+ * Copyright (C) 2001 Peter Bergner, IBM Corp.
+ */
+
+#define MAX_LMB_REGIONS 8
+
+struct lmb_property {
+	phys_addr_t base;
+	phys_size_t size;
+};
+
+struct lmb_region {
+	unsigned long cnt;
+	phys_size_t size;
+	struct lmb_property region[MAX_LMB_REGIONS+1];
+};
+
+struct lmb {
+	struct lmb_region memory;
+	struct lmb_region reserved;
+};
+
+extern void lmb_init(struct lmb *lmb);
+extern void lmb_init_and_reserve(struct lmb *lmb, bd_t *bd, void *fdt_blob);
+extern void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base,
+				       phys_size_t size, void *fdt_blob);
+extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
+extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
+			    phys_addr_t max_addr);
+extern phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
+			      phys_addr_t max_addr);
+extern phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base,
+				  phys_size_t size);
+extern phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr);
+extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
+extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+
+extern void lmb_dump_all(struct lmb *lmb);
+
+static inline phys_size_t
+lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
+{
+	return type->region[region_nr].size;
+}
+
+void board_lmb_reserve(struct lmb *lmb);
+void arch_lmb_reserve(struct lmb *lmb);
+
+#endif /* __KERNEL__ */
+
+#endif /* _LINUX_LMB_H */
diff --git a/include/log.h b/include/log.h
new file mode 100644
index 0000000..d8f18a6
--- /dev/null
+++ b/include/log.h
@@ -0,0 +1,442 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Logging support
+ *
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __LOG_H
+#define __LOG_H
+
+#include <dm/uclass-id.h>
+#include <linux/list.h>
+
+/** Log levels supported, ranging from most to least important */
+enum log_level_t {
+	LOGL_EMERG = 0,		/* U-Boot is unstable */
+	LOGL_ALERT,		/* Action must be taken immediately */
+	LOGL_CRIT,		/* Critical conditions */
+	LOGL_ERR,		/* Error that prevents something from working */
+	LOGL_WARNING,		/* Warning may prevent optimial operation */
+	LOGL_NOTICE,		/* Normal but significant condition, printf() */
+	LOGL_INFO,		/* General information message */
+	LOGL_DEBUG,		/* Basic debug-level message */
+	LOGL_DEBUG_CONTENT,	/* Debug message showing full message content */
+	LOGL_DEBUG_IO,		/* Debug message showing hardware I/O access */
+
+	LOGL_COUNT,
+	LOGL_NONE,
+
+	LOGL_FIRST = LOGL_EMERG,
+	LOGL_MAX = LOGL_DEBUG_IO,
+};
+
+/**
+ * Log categories supported. Most of these correspond to uclasses (i.e.
+ * enum uclass_id) but there are also some more generic categories
+ */
+enum log_category_t {
+	LOGC_FIRST = 0,	/* First part mirrors UCLASS_... */
+
+	LOGC_NONE = UCLASS_COUNT,	/* First number is after all uclasses */
+	LOGC_ARCH,	/* Related to arch-specific code */
+	LOGC_BOARD,	/* Related to board-specific code */
+	LOGC_CORE,	/* Related to core features (non-driver-model) */
+	LOGC_DM,	/* Core driver-model */
+	LOGC_DT,	/* Device-tree */
+	LOGC_EFI,	/* EFI implementation */
+	LOGC_ALLOC,	/* Memory allocation */
+	LOGC_SANDBOX,	/* Related to the sandbox board */
+	LOGC_BLOBLIST,	/* Bloblist */
+
+	LOGC_COUNT,	/* Number of log categories */
+	LOGC_END,	/* Sentinel value for a list of log categories */
+};
+
+/* Helper to cast a uclass ID to a log category */
+static inline int log_uc_cat(enum uclass_id id)
+{
+	return (enum log_category_t)id;
+}
+
+/**
+ * _log() - Internal function to emit a new log record
+ *
+ * @cat: Category of log record (indicating which subsystem generated it)
+ * @level: Level of log record (indicating its severity)
+ * @file: File name of file where log record was generated
+ * @line: Line number in file where log record was generated
+ * @func: Function where log record was generated
+ * @fmt: printf() format string for log record
+ * @...: Optional parameters, according to the format string @fmt
+ * @return 0 if log record was emitted, -ve on error
+ */
+int _log(enum log_category_t cat, enum log_level_t level, const char *file,
+	 int line, const char *func, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 6, 7)));
+
+static inline int _log_nop(enum log_category_t cat, enum log_level_t level,
+			   const char *file, int line, const char *func,
+			   const char *fmt, ...)
+		__attribute__ ((format (__printf__, 6, 7)));
+
+static inline int _log_nop(enum log_category_t cat, enum log_level_t level,
+			   const char *file, int line, const char *func,
+			   const char *fmt, ...)
+{
+	return 0;
+}
+
+/* Define this at the top of a file to add a prefix to debug messages */
+#ifndef pr_fmt
+#define pr_fmt(fmt) fmt
+#endif
+
+/* Use a default category if this file does not supply one */
+#ifndef LOG_CATEGORY
+#define LOG_CATEGORY LOGC_NONE
+#endif
+
+/*
+ * This header may be including when CONFIG_LOG is disabled, in which case
+ * CONFIG_LOG_MAX_LEVEL is not defined. Add a check for this.
+ */
+#if CONFIG_IS_ENABLED(LOG)
+#define _LOG_MAX_LEVEL CONFIG_VAL(LOG_MAX_LEVEL)
+#define log_err(_fmt...)	log(LOG_CATEGORY, LOGL_ERR, ##_fmt)
+#define log_warning(_fmt...)	log(LOG_CATEGORY, LOGL_WARNING, ##_fmt)
+#define log_notice(_fmt...)	log(LOG_CATEGORY, LOGL_NOTICE, ##_fmt)
+#define log_info(_fmt...)	log(LOG_CATEGORY, LOGL_INFO, ##_fmt)
+#define log_debug(_fmt...)	log(LOG_CATEGORY, LOGL_DEBUG, ##_fmt)
+#define log_content(_fmt...)	log(LOG_CATEGORY, LOGL_DEBUG_CONTENT, ##_fmt)
+#define log_io(_fmt...)		log(LOG_CATEGORY, LOGL_DEBUG_IO, ##_fmt)
+#else
+#define _LOG_MAX_LEVEL LOGL_INFO
+#define log_err(_fmt...)	log_nop(LOG_CATEGORY, LOGL_ERR, ##_fmt)
+#define log_warning(_fmt...)	log_nop(LOG_CATEGORY, LOGL_WARNING, ##_fmt)
+#define log_notice(_fmt...)	log_nop(LOG_CATEGORY, LOGL_NOTICE, ##_fmt)
+#define log_info(_fmt...)	log_nop(LOG_CATEGORY, LOGL_INFO, ##_fmt)
+#define log_debug(_fmt...)	log_nop(LOG_CATEGORY, LOGL_DEBUG, ##_fmt)
+#define log_content(_fmt...)	log_nop(LOG_CATEGORY, \
+					LOGL_DEBUG_CONTENT, ##_fmt)
+#define log_io(_fmt...)		log_nop(LOG_CATEGORY, LOGL_DEBUG_IO, ##_fmt)
+#endif
+
+#if CONFIG_IS_ENABLED(LOG)
+#ifdef LOG_DEBUG
+#define _LOG_DEBUG	1
+#else
+#define _LOG_DEBUG	0
+#endif
+
+/* Emit a log record if the level is less that the maximum */
+#define log(_cat, _level, _fmt, _args...) ({ \
+	int _l = _level; \
+	if (CONFIG_IS_ENABLED(LOG) && (_l <= _LOG_MAX_LEVEL || _LOG_DEBUG)) \
+		_log((enum log_category_t)(_cat), _l, __FILE__, __LINE__, \
+		      __func__, \
+		      pr_fmt(_fmt), ##_args); \
+	})
+#else
+#define log(_cat, _level, _fmt, _args...)
+#endif
+
+#define log_nop(_cat, _level, _fmt, _args...) ({ \
+	int _l = _level; \
+	_log_nop((enum log_category_t)(_cat), _l, __FILE__, __LINE__, \
+		      __func__, pr_fmt(_fmt), ##_args); \
+})
+
+#ifdef DEBUG
+#define _DEBUG	1
+#else
+#define _DEBUG	0
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define _SPL_BUILD	1
+#else
+#define _SPL_BUILD	0
+#endif
+
+#if !_DEBUG && CONFIG_IS_ENABLED(LOG)
+
+#define debug_cond(cond, fmt, args...)			\
+	do {						\
+		if (1)					\
+			log(LOG_CATEGORY, LOGL_DEBUG, fmt, ##args); \
+	} while (0)
+
+#else /* _DEBUG */
+
+/*
+ * Output a debug text when condition "cond" is met. The "cond" should be
+ * computed by a preprocessor in the best case, allowing for the best
+ * optimization.
+ */
+#define debug_cond(cond, fmt, args...)			\
+	do {						\
+		if (cond)				\
+			printf(pr_fmt(fmt), ##args);	\
+	} while (0)
+
+#endif /* _DEBUG */
+
+/* Show a message if DEBUG is defined in a file */
+#define debug(fmt, args...)			\
+	debug_cond(_DEBUG, fmt, ##args)
+
+/* Show a message if not in SPL */
+#define warn_non_spl(fmt, args...)			\
+	debug_cond(!_SPL_BUILD, fmt, ##args)
+
+/*
+ * An assertion is run-time check done in debug mode only. If DEBUG is not
+ * defined then it is skipped. If DEBUG is defined and the assertion fails,
+ * then it calls panic*( which may or may not reset/halt U-Boot (see
+ * CONFIG_PANIC_HANG), It is hoped that all failing assertions are found
+ * before release, and after release it is hoped that they don't matter. But
+ * in any case these failing assertions cannot be fixed with a reset (which
+ * may just do the same assertion again).
+ */
+void __assert_fail(const char *assertion, const char *file, unsigned int line,
+		   const char *function);
+
+/**
+ * assert() - assert expression is true
+ *
+ * If the expression x evaluates to false and _DEBUG evaluates to true, a panic
+ * message is written and the system stalls. The value of _DEBUG is set to true
+ * if DEBUG is defined before including common.h.
+ *
+ * The expression x is always executed irrespective of the value of _DEBUG.
+ *
+ * @x:		expression to test
+ */
+#define assert(x) \
+	({ if (!(x) && _DEBUG) \
+		__assert_fail(#x, __FILE__, __LINE__, __func__); })
+
+#if CONFIG_IS_ENABLED(LOG) && defined(CONFIG_LOG_ERROR_RETURN)
+/*
+ * Log an error return value, possibly with a message. Usage:
+ *
+ *	return log_ret(fred_call());
+ *
+ * or:
+ *
+ *	return log_msg_ret("fred failed", fred_call());
+ */
+#define log_ret(_ret) ({ \
+	int __ret = (_ret); \
+	if (__ret < 0) \
+		log(LOG_CATEGORY, LOGL_ERR, "returning err=%d\n", __ret); \
+	__ret; \
+	})
+#define log_msg_ret(_msg, _ret) ({ \
+	int __ret = (_ret); \
+	if (__ret < 0) \
+		log(LOG_CATEGORY, LOGL_ERR, "%s: returning err=%d\n", _msg, \
+		    __ret); \
+	__ret; \
+	})
+#else
+/* Non-logging versions of the above which just return the error code */
+#define log_ret(_ret) (_ret)
+#define log_msg_ret(_msg, _ret) ((void)(_msg), _ret)
+#endif
+
+/**
+ * struct log_rec - a single log record
+ *
+ * Holds information about a single record in the log
+ *
+ * Members marked as 'not allocated' are stored as pointers and the caller is
+ * responsible for making sure that the data pointed to is not overwritten.
+ * Memebers marked as 'allocated' are allocated (e.g. via strdup()) by the log
+ * system.
+ *
+ * @cat: Category, representing a uclass or part of U-Boot
+ * @level: Severity level, less severe is higher
+ * @file: Name of file where the log record was generated (not allocated)
+ * @line: Line number where the log record was generated
+ * @func: Function where the log record was generated (not allocated)
+ * @msg: Log message (allocated)
+ */
+struct log_rec {
+	enum log_category_t cat;
+	enum log_level_t level;
+	const char *file;
+	int line;
+	const char *func;
+	const char *msg;
+};
+
+struct log_device;
+
+/**
+ * struct log_driver - a driver which accepts and processes log records
+ *
+ * @name: Name of driver
+ */
+struct log_driver {
+	const char *name;
+	/**
+	 * emit() - emit a log record
+	 *
+	 * Called by the log system to pass a log record to a particular driver
+	 * for processing. The filter is checked before calling this function.
+	 */
+	int (*emit)(struct log_device *ldev, struct log_rec *rec);
+};
+
+/**
+ * struct log_device - an instance of a log driver
+ *
+ * Since drivers are set up at build-time we need to have a separate device for
+ * the run-time aspects of drivers (currently just a list of filters to apply
+ * to records send to this device).
+ *
+ * @next_filter_num: Seqence number of next filter filter added (0=no filters
+ *	yet). This increments with each new filter on the device, but never
+ *	decrements
+ * @drv: Pointer to driver for this device
+ * @filter_head: List of filters for this device
+ * @sibling_node: Next device in the list of all devices
+ */
+struct log_device {
+	int next_filter_num;
+	struct log_driver *drv;
+	struct list_head filter_head;
+	struct list_head sibling_node;
+};
+
+enum {
+	LOGF_MAX_CATEGORIES = 5,	/* maximum categories per filter */
+};
+
+enum log_filter_flags {
+	LOGFF_HAS_CAT		= 1 << 0,	/* Filter has a category list */
+};
+
+/**
+ * struct log_filter - criterial to filter out log messages
+ *
+ * @filter_num: Sequence number of this filter.  This is returned when adding a
+ *	new filter, and must be provided when removing a previously added
+ *	filter.
+ * @flags: Flags for this filter (LOGFF_...)
+ * @cat_list: List of categories to allow (terminated by LOGC_none). If empty
+ *	then all categories are permitted. Up to LOGF_MAX_CATEGORIES entries
+ *	can be provided
+ * @max_level: Maximum log level to allow
+ * @file_list: List of files to allow, separated by comma. If NULL then all
+ *	files are permitted
+ * @sibling_node: Next filter in the list of filters for this log device
+ */
+struct log_filter {
+	int filter_num;
+	int flags;
+	enum log_category_t cat_list[LOGF_MAX_CATEGORIES];
+	enum log_level_t max_level;
+	const char *file_list;
+	struct list_head sibling_node;
+};
+
+#define LOG_DRIVER(_name) \
+	ll_entry_declare(struct log_driver, _name, log_driver)
+
+/**
+ * log_get_cat_name() - Get the name of a category
+ *
+ * @cat: Category to look up
+ * @return category name (which may be a uclass driver name) if found, or
+ *	 "<invalid>" if invalid, or "<missing>" if not found
+ */
+const char *log_get_cat_name(enum log_category_t cat);
+
+/**
+ * log_get_cat_by_name() - Look up a category by name
+ *
+ * @name: Name to look up
+ * @return category ID, or LOGC_NONE if not found
+ */
+enum log_category_t log_get_cat_by_name(const char *name);
+
+/**
+ * log_get_level_name() - Get the name of a log level
+ *
+ * @level: Log level to look up
+ * @return log level name (in ALL CAPS)
+ */
+const char *log_get_level_name(enum log_level_t level);
+
+/**
+ * log_get_level_by_name() - Look up a log level by name
+ *
+ * @name: Name to look up
+ * @return log level ID, or LOGL_NONE if not found
+ */
+enum log_level_t log_get_level_by_name(const char *name);
+
+/* Log format flags (bit numbers) for gd->log_fmt. See log_fmt_chars */
+enum log_fmt {
+	LOGF_CAT	= 0,
+	LOGF_LEVEL,
+	LOGF_FILE,
+	LOGF_LINE,
+	LOGF_FUNC,
+	LOGF_MSG,
+
+	LOGF_COUNT,
+	LOGF_DEFAULT = (1 << LOGF_FUNC) | (1 << LOGF_MSG),
+	LOGF_ALL = 0x3f,
+};
+
+/* Handle the 'log test' command */
+int do_log_test(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+
+/**
+ * log_add_filter() - Add a new filter to a log device
+ *
+ * @drv_name: Driver name to add the filter to (since each driver only has a
+ *	single device)
+ * @cat_list: List of categories to allow (terminated by LOGC_none). If empty
+ *	then all categories are permitted. Up to LOGF_MAX_CATEGORIES entries
+ *	can be provided
+ * @max_level: Maximum log level to allow
+ * @file_list: List of files to allow, separated by comma. If NULL then all
+ *	files are permitted
+ * @return the sequence number of the new filter (>=0) if the filter was added,
+ *	or a -ve value on error
+ */
+int log_add_filter(const char *drv_name, enum log_category_t cat_list[],
+		   enum log_level_t max_level, const char *file_list);
+
+/**
+ * log_remove_filter() - Remove a filter from a log device
+ *
+ * @drv_name: Driver name to remove the filter from (since each driver only has
+ *	a single device)
+ * @filter_num: Filter number to remove (as returned by log_add_filter())
+ * @return 0 if the filter was removed, -ENOENT if either the driver or the
+ *	filter number was not found
+ */
+int log_remove_filter(const char *drv_name, int filter_num);
+
+#if CONFIG_IS_ENABLED(LOG)
+/**
+ * log_init() - Set up the log system ready for use
+ *
+ * @return 0 if OK, -ENOMEM if out of memory
+ */
+int log_init(void);
+#else
+static inline int log_init(void)
+{
+	return 0;
+}
+#endif
+
+#endif
diff --git a/include/lzma/LzmaDec.h b/include/lzma/LzmaDec.h
new file mode 100644
index 0000000..b96cf1d
--- /dev/null
+++ b/include/lzma/LzmaDec.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Fake include for LzmaDec.h
+ *
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
+ * Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
+ *
+ */
+
+#ifndef __LZMADEC_H__FAKE__
+#define __LZMADEC_H__FAKE__
+
+#include "../../lib/lzma/LzmaDec.h"
+
+#endif
diff --git a/include/lzma/LzmaTools.h b/include/lzma/LzmaTools.h
new file mode 100644
index 0000000..4629e6b
--- /dev/null
+++ b/include/lzma/LzmaTools.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Fake include for LzmaTools.h
+ *
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
+ * Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
+ */
+
+#ifndef __LZMATOOLS_H__FAKE__
+#define __LZMATOOLS_H__FAKE__
+
+#include "../../lib/lzma/LzmaTools.h"
+
+#endif
diff --git a/include/lzma/LzmaTypes.h b/include/lzma/LzmaTypes.h
new file mode 100644
index 0000000..3670c3f
--- /dev/null
+++ b/include/lzma/LzmaTypes.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Fake include for Types.h
+ *
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
+ * Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
+ */
+
+#ifndef __TYPES_H__FAKE__
+#define __TYPES_H__FAKE__
+
+/*
+ *This avoids the collition with zlib.h Byte definition
+ */
+#define Byte LZByte
+
+#include "../../lib/lzma/Types.h"
+
+#endif
diff --git a/include/mailbox-uclass.h b/include/mailbox-uclass.h
new file mode 100644
index 0000000..e0618aa
--- /dev/null
+++ b/include/mailbox-uclass.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _MAILBOX_UCLASS_H
+#define _MAILBOX_UCLASS_H
+
+/* See mailbox.h for background documentation. */
+
+#include <mailbox.h>
+
+struct udevice;
+
+/**
+ * struct mbox_ops - The functions that a mailbox driver must implement.
+ */
+struct mbox_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) mailbox specifier.
+	 *
+	 * The mailbox core calls this function as the first step in
+	 * implementing a client's mbox_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the mailbox core will use
+	 * a default implementation, which assumes #mbox-cells = <1>, and that
+	 * the DT cell contains a simple integer channel ID.
+	 *
+	 * At present, the mailbox API solely supports device-tree. If this
+	 * changes, other xxx_xlate() functions may be added to support those
+	 * other mechanisms.
+	 *
+	 * @chan:	The channel to hold the translation result.
+	 * @args:	The mailbox specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct mbox_chan *chan,
+			struct ofnode_phandle_args *args);
+	/**
+	 * request - Request a translated channel.
+	 *
+	 * The mailbox core calls this function as the second step in
+	 * implementing a client's mbox_get_by_*() call, following a successful
+	 * xxx_xlate() call.
+	 *
+	 * @chan:	The channel to request; this has been filled in by a
+	 *		previoux xxx_xlate() function call.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct mbox_chan *chan);
+	/**
+	 * free - Free a previously requested channel.
+	 *
+	 * This is the implementation of the client mbox_free() API.
+	 *
+	 * @chan:	The channel to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct mbox_chan *chan);
+	/**
+	* send - Send a message over a mailbox channel
+	*
+	* @chan:	The channel to send to the message to.
+	* @data:	A pointer to the message to send.
+	* @return 0 if OK, or a negative error code.
+	*/
+	int (*send)(struct mbox_chan *chan, const void *data);
+	/**
+	* recv - Receive any available message from the channel.
+	*
+	* This function does not block. If not message is immediately
+	* available, the function should return an error.
+	*
+	* @chan:	The channel to receive to the message from.
+	* @data:	A pointer to the buffer to hold the received message.
+	* @return 0 if OK, -ENODATA if no message was available, or a negative
+	* error code.
+	*/
+	int (*recv)(struct mbox_chan *chan, void *data);
+};
+
+#endif
diff --git a/include/mailbox.h b/include/mailbox.h
new file mode 100644
index 0000000..93f4715
--- /dev/null
+++ b/include/mailbox.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _MAILBOX_H
+#define _MAILBOX_H
+
+/**
+ * A mailbox is a hardware mechanism for transferring small fixed-size messages
+ * and/or notifications between the CPU on which U-Boot runs and some other
+ * device such as an auxiliary CPU running firmware or a hardware module.
+ *
+ * Data transfer is optional; a mailbox may consist solely of a notification
+ * mechanism. When data transfer is implemented, it is via HW registers or
+ * FIFOs, rather than via RAM-based buffers. The mailbox API generally
+ * implements any communication protocol enforced solely by hardware, and
+ * leaves any higher-level protocols to other layers.
+ *
+ * A mailbox channel is a bi-directional mechanism that can send a message or
+ * notification to a single specific remote entity, and receive messages or
+ * notifications from that entity. The size, content, and format of such
+ * messages is defined by the mailbox implementation, or the remote entity with
+ * which it communicates; there is no general standard at this API level.
+ *
+ * A driver that implements UCLASS_MAILBOX is a mailbox provider. A provider
+ * will often implement multiple separate mailbox channels, since the hardware
+ * it manages often has this capability. mailbox-uclass.h describes the
+ * interface which mailbox providers must implement.
+ *
+ * Mailbox consumers/clients generate and send, or receive and process,
+ * messages. This header file describes the API used by clients.
+ */
+
+struct udevice;
+
+/**
+ * struct mbox_chan - A handle to a single mailbox channel.
+ *
+ * Clients provide storage for channels. The content of the channel structure
+ * is managed solely by the mailbox API and mailbox drivers. A mailbox channel
+ * is initialized by "get"ing the mailbox. The channel struct is passed to all
+ * other mailbox APIs to identify which mailbox to operate upon.
+ *
+ * @dev: The device which implements the mailbox.
+ * @id: The mailbox channel ID within the provider.
+ * @con_priv: Hook for controller driver to attach private data
+ *
+ * Currently, the mailbox API assumes that a single integer ID is enough to
+ * identify and configure any mailbox channel for any mailbox provider. If this
+ * assumption becomes invalid in the future, the struct could be expanded to
+ * either (a) add more fields to allow mailbox providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct mbox_chan {
+	struct udevice *dev;
+	/* Written by of_xlate.*/
+	unsigned long id;
+	void *con_priv;
+};
+
+/**
+ * mbox_get_by_index - Get/request a mailbox by integer index
+ *
+ * This looks up and requests a mailbox channel. The index is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel indices to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the mailbox channel to request, within the
+ *		client's list of channels.
+ * @chan	A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan);
+
+/**
+ * mbox_get_by_name - Get/request a mailbox by name
+ *
+ * This looks up and requests a mailbox channel. The name is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel names to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the mailbox channel to request, within the client's
+ *		list of channels.
+ * @chan	A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_name(struct udevice *dev, const char *name,
+		     struct mbox_chan *chan);
+
+/**
+ * mbox_free - Free a previously requested mailbox channel.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_free(struct mbox_chan *chan);
+
+/**
+ * mbox_send - Send a message over a mailbox channel
+ *
+ * This function will send a message to the remote entity. It may return before
+ * the remote entity has received and/or processed the message.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @data:	A pointer to the message to transfer. The format and size of
+ *		the memory region pointed at by @data is determined by the
+ *		mailbox provider. Providers that solely transfer notifications
+ *		will ignore this parameter.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_send(struct mbox_chan *chan, const void *data);
+
+/**
+ * mbox_recv - Receive any available message from a mailbox channel
+ *
+ * This function will wait (up to the specified @timeout_us) for a message to
+ * be sent by the remote entity, and write the content of any such message
+ * into a caller-provided buffer.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @data:	A pointer to the buffer to receive the message. The format and
+ *		size of the memory region pointed at by @data is determined by
+ *		the mailbox provider. Providers that solely transfer
+ *		notifications will ignore this parameter.
+ * @timeout_us:	The maximum time to wait for a message to be available, in
+ *		micro-seconds. A value of 0 does not wait at all.
+ * @return 0 if OK, -ENODATA if no message was available, or a negative error
+ * code.
+ */
+int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us);
+
+#endif
diff --git a/include/malloc.h b/include/malloc.h
new file mode 100644
index 0000000..5efa692
--- /dev/null
+++ b/include/malloc.h
@@ -0,0 +1,965 @@
+/*
+  A version of malloc/free/realloc written by Doug Lea and released to the
+  public domain.  Send questions/comments/complaints/performance data
+  to dl@cs.oswego.edu
+
+* VERSION 2.6.6  Sun Mar  5 19:10:03 2000  Doug Lea  (dl at gee)
+
+   Note: There may be an updated version of this malloc obtainable at
+	   ftp://g.oswego.edu/pub/misc/malloc.c
+	 Check before installing!
+
+* Why use this malloc?
+
+  This is not the fastest, most space-conserving, most portable, or
+  most tunable malloc ever written. However it is among the fastest
+  while also being among the most space-conserving, portable and tunable.
+  Consistent balance across these factors results in a good general-purpose
+  allocator. For a high-level description, see
+     http://g.oswego.edu/dl/html/malloc.html
+
+* Synopsis of public routines
+
+  (Much fuller descriptions are contained in the program documentation below.)
+
+  malloc(size_t n);
+     Return a pointer to a newly allocated chunk of at least n bytes, or null
+     if no space is available.
+  free(Void_t* p);
+     Release the chunk of memory pointed to by p, or no effect if p is null.
+  realloc(Void_t* p, size_t n);
+     Return a pointer to a chunk of size n that contains the same data
+     as does chunk p up to the minimum of (n, p's size) bytes, or null
+     if no space is available. The returned pointer may or may not be
+     the same as p. If p is null, equivalent to malloc.  Unless the
+     #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a
+     size argument of zero (re)allocates a minimum-sized chunk.
+  memalign(size_t alignment, size_t n);
+     Return a pointer to a newly allocated chunk of n bytes, aligned
+     in accord with the alignment argument, which must be a power of
+     two.
+  valloc(size_t n);
+     Equivalent to memalign(pagesize, n), where pagesize is the page
+     size of the system (or as near to this as can be figured out from
+     all the includes/defines below.)
+  pvalloc(size_t n);
+     Equivalent to valloc(minimum-page-that-holds(n)), that is,
+     round up n to nearest pagesize.
+  calloc(size_t unit, size_t quantity);
+     Returns a pointer to quantity * unit bytes, with all locations
+     set to zero.
+  cfree(Void_t* p);
+     Equivalent to free(p).
+  malloc_trim(size_t pad);
+     Release all but pad bytes of freed top-most memory back
+     to the system. Return 1 if successful, else 0.
+  malloc_usable_size(Void_t* p);
+     Report the number usable allocated bytes associated with allocated
+     chunk p. This may or may not report more bytes than were requested,
+     due to alignment and minimum size constraints.
+  malloc_stats();
+     Prints brief summary statistics on stderr.
+  mallinfo()
+     Returns (by copy) a struct containing various summary statistics.
+  mallopt(int parameter_number, int parameter_value)
+     Changes one of the tunable parameters described below. Returns
+     1 if successful in changing the parameter, else 0.
+
+* Vital statistics:
+
+  Alignment:                            8-byte
+       8 byte alignment is currently hardwired into the design.  This
+       seems to suffice for all current machines and C compilers.
+
+  Assumed pointer representation:       4 or 8 bytes
+       Code for 8-byte pointers is untested by me but has worked
+       reliably by Wolfram Gloger, who contributed most of the
+       changes supporting this.
+
+  Assumed size_t  representation:       4 or 8 bytes
+       Note that size_t is allowed to be 4 bytes even if pointers are 8.
+
+  Minimum overhead per allocated chunk: 4 or 8 bytes
+       Each malloced chunk has a hidden overhead of 4 bytes holding size
+       and status information.
+
+  Minimum allocated size: 4-byte ptrs:  16 bytes    (including 4 overhead)
+			  8-byte ptrs:  24/32 bytes (including, 4/8 overhead)
+
+       When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte
+       ptrs but 4 byte size) or 24 (for 8/8) additional bytes are
+       needed; 4 (8) for a trailing size field
+       and 8 (16) bytes for free list pointers. Thus, the minimum
+       allocatable size is 16/24/32 bytes.
+
+       Even a request for zero bytes (i.e., malloc(0)) returns a
+       pointer to something of the minimum allocatable size.
+
+  Maximum allocated size: 4-byte size_t: 2^31 -  8 bytes
+			  8-byte size_t: 2^63 - 16 bytes
+
+       It is assumed that (possibly signed) size_t bit values suffice to
+       represent chunk sizes. `Possibly signed' is due to the fact
+       that `size_t' may be defined on a system as either a signed or
+       an unsigned type. To be conservative, values that would appear
+       as negative numbers are avoided.
+       Requests for sizes with a negative sign bit when the request
+       size is treaded as a long will return null.
+
+  Maximum overhead wastage per allocated chunk: normally 15 bytes
+
+       Alignnment demands, plus the minimum allocatable size restriction
+       make the normal worst-case wastage 15 bytes (i.e., up to 15
+       more bytes will be allocated than were requested in malloc), with
+       two exceptions:
+	 1. Because requests for zero bytes allocate non-zero space,
+	    the worst case wastage for a request of zero bytes is 24 bytes.
+	 2. For requests >= mmap_threshold that are serviced via
+	    mmap(), the worst case wastage is 8 bytes plus the remainder
+	    from a system page (the minimal mmap unit); typically 4096 bytes.
+
+* Limitations
+
+    Here are some features that are NOT currently supported
+
+    * No user-definable hooks for callbacks and the like.
+    * No automated mechanism for fully checking that all accesses
+      to malloced memory stay within their bounds.
+    * No support for compaction.
+
+* Synopsis of compile-time options:
+
+    People have reported using previous versions of this malloc on all
+    versions of Unix, sometimes by tweaking some of the defines
+    below. It has been tested most extensively on Solaris and
+    Linux. It is also reported to work on WIN32 platforms.
+    People have also reported adapting this malloc for use in
+    stand-alone embedded systems.
+
+    The implementation is in straight, hand-tuned ANSI C.  Among other
+    consequences, it uses a lot of macros.  Because of this, to be at
+    all usable, this code should be compiled using an optimizing compiler
+    (for example gcc -O2) that can simplify expressions and control
+    paths.
+
+  __STD_C                  (default: derived from C compiler defines)
+     Nonzero if using ANSI-standard C compiler, a C++ compiler, or
+     a C compiler sufficiently close to ANSI to get away with it.
+  DEBUG                    (default: NOT defined)
+     Define to enable debugging. Adds fairly extensive assertion-based
+     checking to help track down memory errors, but noticeably slows down
+     execution.
+  REALLOC_ZERO_BYTES_FREES (default: NOT defined)
+     Define this if you think that realloc(p, 0) should be equivalent
+     to free(p). Otherwise, since malloc returns a unique pointer for
+     malloc(0), so does realloc(p, 0).
+  HAVE_MEMCPY               (default: defined)
+     Define if you are not otherwise using ANSI STD C, but still
+     have memcpy and memset in your C library and want to use them.
+     Otherwise, simple internal versions are supplied.
+  USE_MEMCPY               (default: 1 if HAVE_MEMCPY is defined, 0 otherwise)
+     Define as 1 if you want the C library versions of memset and
+     memcpy called in realloc and calloc (otherwise macro versions are used).
+     At least on some platforms, the simple macro versions usually
+     outperform libc versions.
+  HAVE_MMAP                 (default: defined as 1)
+     Define to non-zero to optionally make malloc() use mmap() to
+     allocate very large blocks.
+  HAVE_MREMAP                 (default: defined as 0 unless Linux libc set)
+     Define to non-zero to optionally make realloc() use mremap() to
+     reallocate very large blocks.
+  malloc_getpagesize        (default: derived from system #includes)
+     Either a constant or routine call returning the system page size.
+  HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined)
+     Optionally define if you are on a system with a /usr/include/malloc.h
+     that declares struct mallinfo. It is not at all necessary to
+     define this even if you do, but will ensure consistency.
+  INTERNAL_SIZE_T           (default: size_t)
+     Define to a 32-bit type (probably `unsigned int') if you are on a
+     64-bit machine, yet do not want or need to allow malloc requests of
+     greater than 2^31 to be handled. This saves space, especially for
+     very small chunks.
+  INTERNAL_LINUX_C_LIB      (default: NOT defined)
+     Defined only when compiled as part of Linux libc.
+     Also note that there is some odd internal name-mangling via defines
+     (for example, internally, `malloc' is named `mALLOc') needed
+     when compiling in this case. These look funny but don't otherwise
+     affect anything.
+  WIN32                     (default: undefined)
+     Define this on MS win (95, nt) platforms to compile in sbrk emulation.
+  LACKS_UNISTD_H            (default: undefined if not WIN32)
+     Define this if your system does not have a <unistd.h>.
+  LACKS_SYS_PARAM_H         (default: undefined if not WIN32)
+     Define this if your system does not have a <sys/param.h>.
+  MORECORE                  (default: sbrk)
+     The name of the routine to call to obtain more memory from the system.
+  MORECORE_FAILURE          (default: -1)
+     The value returned upon failure of MORECORE.
+  MORECORE_CLEARS           (default 1)
+     true (1) if the routine mapped to MORECORE zeroes out memory (which
+     holds for sbrk).
+  DEFAULT_TRIM_THRESHOLD
+  DEFAULT_TOP_PAD
+  DEFAULT_MMAP_THRESHOLD
+  DEFAULT_MMAP_MAX
+     Default values of tunable parameters (described in detail below)
+     controlling interaction with host system routines (sbrk, mmap, etc).
+     These values may also be changed dynamically via mallopt(). The
+     preset defaults are those that give best performance for typical
+     programs/systems.
+  USE_DL_PREFIX             (default: undefined)
+     Prefix all public routines with the string 'dl'.  Useful to
+     quickly avoid procedure declaration conflicts and linker symbol
+     conflicts with existing memory allocation routines.
+
+
+*/
+
+
+#ifndef __MALLOC_H__
+#define __MALLOC_H__
+
+/* Preliminaries */
+
+#ifndef __STD_C
+#ifdef __STDC__
+#define __STD_C     1
+#else
+#if __cplusplus
+#define __STD_C     1
+#else
+#define __STD_C     0
+#endif /*__cplusplus*/
+#endif /*__STDC__*/
+#endif /*__STD_C*/
+
+#ifndef Void_t
+#if (__STD_C || defined(WIN32))
+#define Void_t      void
+#else
+#define Void_t      char
+#endif
+#endif /*Void_t*/
+
+#if __STD_C
+#include <linux/stddef.h>	/* for size_t */
+#else
+#include <sys/types.h>
+#endif	/* __STD_C */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if 0	/* not for U-Boot */
+#include <stdio.h>	/* needed for malloc_stats */
+#endif
+
+
+/*
+  Compile-time options
+*/
+
+
+/*
+    Debugging:
+
+    Because freed chunks may be overwritten with link fields, this
+    malloc will often die when freed memory is overwritten by user
+    programs.  This can be very effective (albeit in an annoying way)
+    in helping track down dangling pointers.
+
+    If you compile with -DDEBUG, a number of assertion checks are
+    enabled that will catch more memory errors. You probably won't be
+    able to make much sense of the actual assertion errors, but they
+    should help you locate incorrectly overwritten memory.  The
+    checking is fairly extensive, and will slow down execution
+    noticeably. Calling malloc_stats or mallinfo with DEBUG set will
+    attempt to check every non-mmapped allocated and free chunk in the
+    course of computing the summmaries. (By nature, mmapped regions
+    cannot be checked very much automatically.)
+
+    Setting DEBUG may also be helpful if you are trying to modify
+    this code. The assertions in the check routines spell out in more
+    detail the assumptions and invariants underlying the algorithms.
+
+*/
+
+/*
+  INTERNAL_SIZE_T is the word-size used for internal bookkeeping
+  of chunk sizes. On a 64-bit machine, you can reduce malloc
+  overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int'
+  at the expense of not being able to handle requests greater than
+  2^31. This limitation is hardly ever a concern; you are encouraged
+  to set this. However, the default version is the same as size_t.
+*/
+
+#ifndef INTERNAL_SIZE_T
+#define INTERNAL_SIZE_T size_t
+#endif
+
+/*
+  REALLOC_ZERO_BYTES_FREES should be set if a call to
+  realloc with zero bytes should be the same as a call to free.
+  Some people think it should. Otherwise, since this malloc
+  returns a unique pointer for malloc(0), so does realloc(p, 0).
+*/
+
+
+/*   #define REALLOC_ZERO_BYTES_FREES */
+
+
+/*
+  WIN32 causes an emulation of sbrk to be compiled in
+  mmap-based options are not currently supported in WIN32.
+*/
+
+/* #define WIN32 */
+#ifdef WIN32
+#define MORECORE wsbrk
+#define HAVE_MMAP 0
+
+#define LACKS_UNISTD_H
+#define LACKS_SYS_PARAM_H
+
+/*
+  Include 'windows.h' to get the necessary declarations for the
+  Microsoft Visual C++ data structures and routines used in the 'sbrk'
+  emulation.
+
+  Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft
+  Visual C++ header files are included.
+*/
+#define WIN32_LEAN_AND_MEAN
+#include <windows.h>
+#endif
+
+
+/*
+  HAVE_MEMCPY should be defined if you are not otherwise using
+  ANSI STD C, but still have memcpy and memset in your C library
+  and want to use them in calloc and realloc. Otherwise simple
+  macro versions are defined here.
+
+  USE_MEMCPY should be defined as 1 if you actually want to
+  have memset and memcpy called. People report that the macro
+  versions are often enough faster than libc versions on many
+  systems that it is better to use them.
+
+*/
+
+#define HAVE_MEMCPY
+
+#ifndef USE_MEMCPY
+#ifdef HAVE_MEMCPY
+#define USE_MEMCPY 1
+#else
+#define USE_MEMCPY 0
+#endif
+#endif
+
+#if (__STD_C || defined(HAVE_MEMCPY))
+
+#if __STD_C
+void* memset(void*, int, size_t);
+void* memcpy(void*, const void*, size_t);
+#else
+#ifdef WIN32
+/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */
+/* 'windows.h' */
+#else
+Void_t* memset();
+Void_t* memcpy();
+#endif
+#endif
+#endif
+
+#if USE_MEMCPY
+
+/* The following macros are only invoked with (2n+1)-multiples of
+   INTERNAL_SIZE_T units, with a positive integer n. This is exploited
+   for fast inline execution when n is small. */
+
+#define MALLOC_ZERO(charp, nbytes)                                            \
+do {                                                                          \
+  INTERNAL_SIZE_T mzsz = (nbytes);                                            \
+  if(mzsz <= 9*sizeof(mzsz)) {                                                \
+    INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp);                         \
+    if(mzsz >= 5*sizeof(mzsz)) {     *mz++ = 0;                               \
+				     *mz++ = 0;                               \
+      if(mzsz >= 7*sizeof(mzsz)) {   *mz++ = 0;                               \
+				     *mz++ = 0;                               \
+	if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0;                               \
+				     *mz++ = 0; }}}                           \
+				     *mz++ = 0;                               \
+				     *mz++ = 0;                               \
+				     *mz   = 0;                               \
+  } else memset((charp), 0, mzsz);                                            \
+} while(0)
+
+#define MALLOC_COPY(dest,src,nbytes)                                          \
+do {                                                                          \
+  INTERNAL_SIZE_T mcsz = (nbytes);                                            \
+  if(mcsz <= 9*sizeof(mcsz)) {                                                \
+    INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src);                        \
+    INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest);                       \
+    if(mcsz >= 5*sizeof(mcsz)) {     *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++;                     \
+      if(mcsz >= 7*sizeof(mcsz)) {   *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++;                     \
+	if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++; }}}                 \
+				     *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++;                     \
+				     *mcdst   = *mcsrc  ;                     \
+  } else memcpy(dest, src, mcsz);                                             \
+} while(0)
+
+#else /* !USE_MEMCPY */
+
+/* Use Duff's device for good zeroing/copying performance. */
+
+#define MALLOC_ZERO(charp, nbytes)                                            \
+do {                                                                          \
+  INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp);                           \
+  long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn;                         \
+  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
+  switch (mctmp) {                                                            \
+    case 0: for(;;) { *mzp++ = 0;                                             \
+    case 7:           *mzp++ = 0;                                             \
+    case 6:           *mzp++ = 0;                                             \
+    case 5:           *mzp++ = 0;                                             \
+    case 4:           *mzp++ = 0;                                             \
+    case 3:           *mzp++ = 0;                                             \
+    case 2:           *mzp++ = 0;                                             \
+    case 1:           *mzp++ = 0; if(mcn <= 0) break; mcn--; }                \
+  }                                                                           \
+} while(0)
+
+#define MALLOC_COPY(dest,src,nbytes)                                          \
+do {                                                                          \
+  INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src;                            \
+  INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest;                           \
+  long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn;                         \
+  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
+  switch (mctmp) {                                                            \
+    case 0: for(;;) { *mcdst++ = *mcsrc++;                                    \
+    case 7:           *mcdst++ = *mcsrc++;                                    \
+    case 6:           *mcdst++ = *mcsrc++;                                    \
+    case 5:           *mcdst++ = *mcsrc++;                                    \
+    case 4:           *mcdst++ = *mcsrc++;                                    \
+    case 3:           *mcdst++ = *mcsrc++;                                    \
+    case 2:           *mcdst++ = *mcsrc++;                                    \
+    case 1:           *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; }       \
+  }                                                                           \
+} while(0)
+
+#endif
+
+
+/*
+  Define HAVE_MMAP to optionally make malloc() use mmap() to
+  allocate very large blocks.  These will be returned to the
+  operating system immediately after a free().
+*/
+
+/***
+#ifndef HAVE_MMAP
+#define HAVE_MMAP 1
+#endif
+***/
+#undef	HAVE_MMAP	/* Not available for U-Boot */
+
+/*
+  Define HAVE_MREMAP to make realloc() use mremap() to re-allocate
+  large blocks.  This is currently only possible on Linux with
+  kernel versions newer than 1.3.77.
+*/
+
+/***
+#ifndef HAVE_MREMAP
+#ifdef INTERNAL_LINUX_C_LIB
+#define HAVE_MREMAP 1
+#else
+#define HAVE_MREMAP 0
+#endif
+#endif
+***/
+#undef	HAVE_MREMAP	/* Not available for U-Boot */
+
+#ifdef HAVE_MMAP
+
+#include <unistd.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+
+#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON)
+#define MAP_ANONYMOUS MAP_ANON
+#endif
+
+#endif /* HAVE_MMAP */
+
+/*
+  Access to system page size. To the extent possible, this malloc
+  manages memory from the system in page-size units.
+
+  The following mechanics for getpagesize were adapted from
+  bsd/gnu getpagesize.h
+*/
+
+#define	LACKS_UNISTD_H	/* Shortcut for U-Boot */
+#define	malloc_getpagesize	4096
+
+#ifndef LACKS_UNISTD_H
+#  include <unistd.h>
+#endif
+
+#ifndef malloc_getpagesize
+#  ifdef _SC_PAGESIZE         /* some SVR4 systems omit an underscore */
+#    ifndef _SC_PAGE_SIZE
+#      define _SC_PAGE_SIZE _SC_PAGESIZE
+#    endif
+#  endif
+#  ifdef _SC_PAGE_SIZE
+#    define malloc_getpagesize sysconf(_SC_PAGE_SIZE)
+#  else
+#    if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE)
+       extern size_t getpagesize();
+#      define malloc_getpagesize getpagesize()
+#    else
+#      ifdef WIN32
+#        define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */
+#      else
+#        ifndef LACKS_SYS_PARAM_H
+#          include <sys/param.h>
+#        endif
+#        ifdef EXEC_PAGESIZE
+#          define malloc_getpagesize EXEC_PAGESIZE
+#        else
+#          ifdef NBPG
+#            ifndef CLSIZE
+#              define malloc_getpagesize NBPG
+#            else
+#              define malloc_getpagesize (NBPG * CLSIZE)
+#            endif
+#          else
+#            ifdef NBPC
+#              define malloc_getpagesize NBPC
+#            else
+#              ifdef PAGESIZE
+#                define malloc_getpagesize PAGESIZE
+#              else
+#                define malloc_getpagesize (4096) /* just guess */
+#              endif
+#            endif
+#          endif
+#        endif
+#      endif
+#    endif
+#  endif
+#endif
+
+
+/*
+
+  This version of malloc supports the standard SVID/XPG mallinfo
+  routine that returns a struct containing the same kind of
+  information you can get from malloc_stats. It should work on
+  any SVID/XPG compliant system that has a /usr/include/malloc.h
+  defining struct mallinfo. (If you'd like to install such a thing
+  yourself, cut out the preliminary declarations as described above
+  and below and save them in a malloc.h file. But there's no
+  compelling reason to bother to do this.)
+
+  The main declaration needed is the mallinfo struct that is returned
+  (by-copy) by mallinfo().  The SVID/XPG malloinfo struct contains a
+  bunch of fields, most of which are not even meaningful in this
+  version of malloc. Some of these fields are are instead filled by
+  mallinfo() with other numbers that might possibly be of interest.
+
+  HAVE_USR_INCLUDE_MALLOC_H should be set if you have a
+  /usr/include/malloc.h file that includes a declaration of struct
+  mallinfo.  If so, it is included; else an SVID2/XPG2 compliant
+  version is declared below.  These must be precisely the same for
+  mallinfo() to work.
+
+*/
+
+/* #define HAVE_USR_INCLUDE_MALLOC_H */
+
+#ifdef HAVE_USR_INCLUDE_MALLOC_H
+#include "/usr/include/malloc.h"
+#else
+
+/* SVID2/XPG mallinfo structure */
+
+struct mallinfo {
+  int arena;    /* total space allocated from system */
+  int ordblks;  /* number of non-inuse chunks */
+  int smblks;   /* unused -- always zero */
+  int hblks;    /* number of mmapped regions */
+  int hblkhd;   /* total space in mmapped regions */
+  int usmblks;  /* unused -- always zero */
+  int fsmblks;  /* unused -- always zero */
+  int uordblks; /* total allocated space */
+  int fordblks; /* total non-inuse space */
+  int keepcost; /* top-most, releasable (via malloc_trim) space */
+};
+
+/* SVID2/XPG mallopt options */
+
+#define M_MXFAST  1    /* UNUSED in this malloc */
+#define M_NLBLKS  2    /* UNUSED in this malloc */
+#define M_GRAIN   3    /* UNUSED in this malloc */
+#define M_KEEP    4    /* UNUSED in this malloc */
+
+#endif
+
+/* mallopt options that actually do something */
+
+#define M_TRIM_THRESHOLD    -1
+#define M_TOP_PAD           -2
+#define M_MMAP_THRESHOLD    -3
+#define M_MMAP_MAX          -4
+
+
+#ifndef DEFAULT_TRIM_THRESHOLD
+#define DEFAULT_TRIM_THRESHOLD (128 * 1024)
+#endif
+
+/*
+    M_TRIM_THRESHOLD is the maximum amount of unused top-most memory
+      to keep before releasing via malloc_trim in free().
+
+      Automatic trimming is mainly useful in long-lived programs.
+      Because trimming via sbrk can be slow on some systems, and can
+      sometimes be wasteful (in cases where programs immediately
+      afterward allocate more large chunks) the value should be high
+      enough so that your overall system performance would improve by
+      releasing.
+
+      The trim threshold and the mmap control parameters (see below)
+      can be traded off with one another. Trimming and mmapping are
+      two different ways of releasing unused memory back to the
+      system. Between these two, it is often possible to keep
+      system-level demands of a long-lived program down to a bare
+      minimum. For example, in one test suite of sessions measuring
+      the XF86 X server on Linux, using a trim threshold of 128K and a
+      mmap threshold of 192K led to near-minimal long term resource
+      consumption.
+
+      If you are using this malloc in a long-lived program, it should
+      pay to experiment with these values.  As a rough guide, you
+      might set to a value close to the average size of a process
+      (program) running on your system.  Releasing this much memory
+      would allow such a process to run in memory.  Generally, it's
+      worth it to tune for trimming rather tham memory mapping when a
+      program undergoes phases where several large chunks are
+      allocated and released in ways that can reuse each other's
+      storage, perhaps mixed with phases where there are no such
+      chunks at all.  And in well-behaved long-lived programs,
+      controlling release of large blocks via trimming versus mapping
+      is usually faster.
+
+      However, in most programs, these parameters serve mainly as
+      protection against the system-level effects of carrying around
+      massive amounts of unneeded memory. Since frequent calls to
+      sbrk, mmap, and munmap otherwise degrade performance, the default
+      parameters are set to relatively high values that serve only as
+      safeguards.
+
+      The default trim value is high enough to cause trimming only in
+      fairly extreme (by current memory consumption standards) cases.
+      It must be greater than page size to have any useful effect.  To
+      disable trimming completely, you can set to (unsigned long)(-1);
+
+
+*/
+
+
+#ifndef DEFAULT_TOP_PAD
+#define DEFAULT_TOP_PAD        (0)
+#endif
+
+/*
+    M_TOP_PAD is the amount of extra `padding' space to allocate or
+      retain whenever sbrk is called. It is used in two ways internally:
+
+      * When sbrk is called to extend the top of the arena to satisfy
+	a new malloc request, this much padding is added to the sbrk
+	request.
+
+      * When malloc_trim is called automatically from free(),
+	it is used as the `pad' argument.
+
+      In both cases, the actual amount of padding is rounded
+      so that the end of the arena is always a system page boundary.
+
+      The main reason for using padding is to avoid calling sbrk so
+      often. Having even a small pad greatly reduces the likelihood
+      that nearly every malloc request during program start-up (or
+      after trimming) will invoke sbrk, which needlessly wastes
+      time.
+
+      Automatic rounding-up to page-size units is normally sufficient
+      to avoid measurable overhead, so the default is 0.  However, in
+      systems where sbrk is relatively slow, it can pay to increase
+      this value, at the expense of carrying around more memory than
+      the program needs.
+
+*/
+
+
+#ifndef DEFAULT_MMAP_THRESHOLD
+#define DEFAULT_MMAP_THRESHOLD (128 * 1024)
+#endif
+
+/*
+
+    M_MMAP_THRESHOLD is the request size threshold for using mmap()
+      to service a request. Requests of at least this size that cannot
+      be allocated using already-existing space will be serviced via mmap.
+      (If enough normal freed space already exists it is used instead.)
+
+      Using mmap segregates relatively large chunks of memory so that
+      they can be individually obtained and released from the host
+      system. A request serviced through mmap is never reused by any
+      other request (at least not directly; the system may just so
+      happen to remap successive requests to the same locations).
+
+      Segregating space in this way has the benefit that mmapped space
+      can ALWAYS be individually released back to the system, which
+      helps keep the system level memory demands of a long-lived
+      program low. Mapped memory can never become `locked' between
+      other chunks, as can happen with normally allocated chunks, which
+      menas that even trimming via malloc_trim would not release them.
+
+      However, it has the disadvantages that:
+
+	 1. The space cannot be reclaimed, consolidated, and then
+	    used to service later requests, as happens with normal chunks.
+	 2. It can lead to more wastage because of mmap page alignment
+	    requirements
+	 3. It causes malloc performance to be more dependent on host
+	    system memory management support routines which may vary in
+	    implementation quality and may impose arbitrary
+	    limitations. Generally, servicing a request via normal
+	    malloc steps is faster than going through a system's mmap.
+
+      All together, these considerations should lead you to use mmap
+      only for relatively large requests.
+
+
+*/
+
+
+#ifndef DEFAULT_MMAP_MAX
+#ifdef HAVE_MMAP
+#define DEFAULT_MMAP_MAX       (64)
+#else
+#define DEFAULT_MMAP_MAX       (0)
+#endif
+#endif
+
+/*
+    M_MMAP_MAX is the maximum number of requests to simultaneously
+      service using mmap. This parameter exists because:
+
+	 1. Some systems have a limited number of internal tables for
+	    use by mmap.
+	 2. In most systems, overreliance on mmap can degrade overall
+	    performance.
+	 3. If a program allocates many large regions, it is probably
+	    better off using normal sbrk-based allocation routines that
+	    can reclaim and reallocate normal heap memory. Using a
+	    small value allows transition into this mode after the
+	    first few allocations.
+
+      Setting to 0 disables all use of mmap.  If HAVE_MMAP is not set,
+      the default value is 0, and attempts to set it to non-zero values
+      in mallopt will fail.
+*/
+
+
+/*
+    USE_DL_PREFIX will prefix all public routines with the string 'dl'.
+      Useful to quickly avoid procedure declaration conflicts and linker
+      symbol conflicts with existing memory allocation routines.
+
+*/
+
+/* #define USE_DL_PREFIX */
+
+
+/*
+
+  Special defines for linux libc
+
+  Except when compiled using these special defines for Linux libc
+  using weak aliases, this malloc is NOT designed to work in
+  multithreaded applications.  No semaphores or other concurrency
+  control are provided to ensure that multiple malloc or free calls
+  don't run at the same time, which could be disasterous. A single
+  semaphore could be used across malloc, realloc, and free (which is
+  essentially the effect of the linux weak alias approach). It would
+  be hard to obtain finer granularity.
+
+*/
+
+
+#ifdef INTERNAL_LINUX_C_LIB
+
+#if __STD_C
+
+Void_t * __default_morecore_init (ptrdiff_t);
+Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init;
+
+#else
+
+Void_t * __default_morecore_init ();
+Void_t *(*__morecore)() = __default_morecore_init;
+
+#endif
+
+#define MORECORE (*__morecore)
+#define MORECORE_FAILURE 0
+#define MORECORE_CLEARS 1
+
+#else /* INTERNAL_LINUX_C_LIB */
+
+#if __STD_C
+extern Void_t*     sbrk(ptrdiff_t);
+#else
+extern Void_t*     sbrk();
+#endif
+
+#ifndef MORECORE
+#define MORECORE sbrk
+#endif
+
+#ifndef MORECORE_FAILURE
+#define MORECORE_FAILURE -1
+#endif
+
+#ifndef MORECORE_CLEARS
+#define MORECORE_CLEARS 1
+#endif
+
+#endif /* INTERNAL_LINUX_C_LIB */
+
+#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__)
+
+#define cALLOc		__libc_calloc
+#define fREe		__libc_free
+#define mALLOc		__libc_malloc
+#define mEMALIGn	__libc_memalign
+#define rEALLOc		__libc_realloc
+#define vALLOc		__libc_valloc
+#define pvALLOc		__libc_pvalloc
+#define mALLINFo	__libc_mallinfo
+#define mALLOPt		__libc_mallopt
+
+#pragma weak calloc = __libc_calloc
+#pragma weak free = __libc_free
+#pragma weak cfree = __libc_free
+#pragma weak malloc = __libc_malloc
+#pragma weak memalign = __libc_memalign
+#pragma weak realloc = __libc_realloc
+#pragma weak valloc = __libc_valloc
+#pragma weak pvalloc = __libc_pvalloc
+#pragma weak mallinfo = __libc_mallinfo
+#pragma weak mallopt = __libc_mallopt
+
+#else
+
+#if CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE)
+#define malloc malloc_simple
+#define realloc realloc_simple
+#define memalign memalign_simple
+static inline void free(void *ptr) {}
+void *calloc(size_t nmemb, size_t size);
+void *realloc_simple(void *ptr, size_t size);
+void malloc_simple_info(void);
+#else
+
+# ifdef USE_DL_PREFIX
+# define cALLOc		dlcalloc
+# define fREe		dlfree
+# define mALLOc		dlmalloc
+# define mEMALIGn	dlmemalign
+# define rEALLOc		dlrealloc
+# define vALLOc		dlvalloc
+# define pvALLOc		dlpvalloc
+# define mALLINFo	dlmallinfo
+# define mALLOPt		dlmallopt
+# else /* USE_DL_PREFIX */
+# define cALLOc		calloc
+# define fREe		free
+# define mALLOc		malloc
+# define mEMALIGn	memalign
+# define rEALLOc		realloc
+# define vALLOc		valloc
+# define pvALLOc		pvalloc
+# define mALLINFo	mallinfo
+# define mALLOPt		mallopt
+# endif /* USE_DL_PREFIX */
+
+#endif
+
+/* Set up pre-relocation malloc() ready for use */
+int initf_malloc(void);
+
+/* Public routines */
+
+/* Simple versions which can be used when space is tight */
+void *malloc_simple(size_t size);
+void *memalign_simple(size_t alignment, size_t bytes);
+
+#pragma GCC visibility push(hidden)
+# if __STD_C
+
+Void_t* mALLOc(size_t);
+void    fREe(Void_t*);
+Void_t* rEALLOc(Void_t*, size_t);
+Void_t* mEMALIGn(size_t, size_t);
+Void_t* vALLOc(size_t);
+Void_t* pvALLOc(size_t);
+Void_t* cALLOc(size_t, size_t);
+void    cfree(Void_t*);
+int     malloc_trim(size_t);
+size_t  malloc_usable_size(Void_t*);
+void    malloc_stats(void);
+int     mALLOPt(int, int);
+struct mallinfo mALLINFo(void);
+# else
+Void_t* mALLOc();
+void    fREe();
+Void_t* rEALLOc();
+Void_t* mEMALIGn();
+Void_t* vALLOc();
+Void_t* pvALLOc();
+Void_t* cALLOc();
+void    cfree();
+int     malloc_trim();
+size_t  malloc_usable_size();
+void    malloc_stats();
+int     mALLOPt();
+struct mallinfo mALLINFo();
+# endif
+#endif
+#pragma GCC visibility pop
+
+/*
+ * Begin and End of memory area for malloc(), and current "brk"
+ */
+extern ulong mem_malloc_start;
+extern ulong mem_malloc_end;
+extern ulong mem_malloc_brk;
+
+void mem_malloc_init(ulong start, ulong size);
+
+#ifdef __cplusplus
+};  /* end of extern "C" */
+#endif
+
+#endif /* __MALLOC_H__ */
diff --git a/include/mapmem.h b/include/mapmem.h
new file mode 100644
index 0000000..2134c80
--- /dev/null
+++ b/include/mapmem.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015 National Instruments
+ *
+ * (C) Copyright 2015
+ * Joe Hershberger <joe.hershberger@ni.com>
+ */
+
+#ifndef __MAPMEM_H
+#define __MAPMEM_H
+
+/* Define a null map_sysmem() if the architecture doesn't use it */
+# ifdef CONFIG_ARCH_MAP_SYSMEM
+#include <asm/io.h>
+# else
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+	return (void *)(uintptr_t)paddr;
+}
+
+static inline void unmap_sysmem(const void *vaddr)
+{
+}
+
+static inline phys_addr_t map_to_sysmem(const void *ptr)
+{
+	return (phys_addr_t)(uintptr_t)ptr;
+}
+# endif
+
+#endif /* __MAPMEM_H */
diff --git a/include/mb862xx.h b/include/mb862xx.h
new file mode 100644
index 0000000..54c8c75
--- /dev/null
+++ b/include/mb862xx.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007
+ * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
+ */
+
+/*
+ * mb862xx.h - Graphic interface for Fujitsu CoralP/Lime
+ */
+
+#ifndef _MB862XX_H_
+#define _MB862XX_H_
+
+#define PCI_VENDOR_ID_FUJITSU	0x10CF
+#define PCI_DEVICE_ID_CORAL_P	0x2019
+#define PCI_DEVICE_ID_CORAL_PA	0x201E
+
+#define MB862XX_TYPE_LIME	0x1
+
+#define GC_HOST_BASE		0x01fc0000
+#define GC_DISP_BASE		0x01fd0000
+#define GC_DRAW_BASE		0x01ff0000
+
+/* Host interface registers */
+#define GC_SRST			0x0000002c
+#define GC_CCF			0x00000038
+#define GC_CID			0x000000f0
+#define GC_MMR			0x0000fffc
+
+/*
+ * Display Controller registers
+ * _A means the offset is aligned, we use these for boards
+ * with 8-/16-bit GDC access not working or buggy.
+ */
+#define GC_DCM0			0x00000000
+#define GC_HTP_A		0x00000004
+#define GC_HTP			0x00000006
+#define GC_HDB_HDP_A		0x00000008
+#define GC_HDP			0x00000008
+#define GC_HDB			0x0000000a
+#define GC_VSW_HSW_HSP_A	0x0000000c
+#define GC_HSP			0x0000000c
+#define GC_HSW			0x0000000e
+#define GC_VSW			0x0000000f
+#define GC_VTR_A		0x00000010
+#define GC_VTR			0x00000012
+#define GC_VDP_VSP_A		0x00000014
+#define GC_VSP			0x00000014
+#define GC_VDP			0x00000016
+#define GC_WY_WX		0x00000018
+#define GC_WH_WW		0x0000001c
+#define GC_L0M			0x00000020
+#define GC_L0OA0		0x00000024
+#define GC_L0DA0		0x00000028
+#define GC_L0DY_L0DX		0x0000002c
+#define GC_L2M			0x00000040
+#define GC_L2OA0		0x00000044
+#define GC_L2DA0		0x00000048
+#define GC_L2OA1		0x0000004c
+#define GC_L2DA1		0x00000050
+#define GC_L2DX			0x00000054
+#define GC_L2DY			0x00000056
+#define GC_DCM1			0x00000100
+#define GC_DCM2			0x00000104
+#define GC_DCM3			0x00000108
+#define GC_L0EM			0x00000110
+#define GC_L0WY_L0WX		0x00000114
+#define GC_L0WH_L0WW		0x00000118
+#define GC_L2EM			0x00000130
+#define GC_L2WX			0x00000134
+#define GC_L2WY			0x00000136
+#define GC_L2WW			0x00000138
+#define GC_L2WH			0x0000013a
+#define GC_L0PAL0		0x00000400
+
+/* Drawing registers */
+#define GC_CTR			0x00000400
+#define GC_IFCNT		0x00000408
+#define GC_FBR			0x00000440
+#define GC_XRES			0x00000444
+#define GC_CXMIN		0x00000454
+#define GC_CXMAX		0x00000458
+#define GC_CYMIN		0x0000045c
+#define GC_CYMAX		0x00000460
+#define GC_FC			0x00000480
+#define GC_BC			0x00000484
+#define GC_FIFO			0x000004a0
+#define GC_REV			0x00008084
+#define GC_GEO_FIFO		0x00008400
+
+typedef struct {
+	unsigned int index;
+	unsigned int value;
+} gdc_regs;
+
+int mb862xx_probe(unsigned int addr);
+const gdc_regs *board_get_regs (void);
+unsigned int board_video_init (void);
+void board_backlight_switch(int);
+
+#endif /* _MB862XX_H_ */
diff --git a/include/mc13783.h b/include/mc13783.h
new file mode 100644
index 0000000..47345f0
--- /dev/null
+++ b/include/mc13783.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at
+ */
+
+
+#ifndef __MC13783_H__
+#define __MC13783_H__
+
+/* REG_MODE_0 */
+#define VAUDIOEN	(1 << 0)
+#define VAUDIOSTBY	(1 << 1)
+#define VAUDIOMODE	(1 << 2)
+#define VIOHIEN		(1 << 3)
+#define VIOHISTBY	(1 << 4)
+#define VIOHIMODE	(1 << 5)
+#define VIOLOEN		(1 << 6)
+#define VIOLOSTBY	(1 << 7)
+#define VIOLOMODE	(1 << 8)
+#define VDIGEN 		(1 << 9)
+#define VDIGSTBY	(1 << 10)
+#define VDIGMODE	(1 << 11)
+#define VGENEN		(1 << 12)
+#define VGENSTBY	(1 << 13)
+#define VGENMODE	(1 << 14)
+#define VRFDIGEN	(1 << 15)
+#define VRFDIGSTBY	(1 << 16)
+#define VRFDIGMODE	(1 << 17)
+#define VRFREFEN	(1 << 18)
+#define VRFREFSTBY	(1 << 19)
+#define VRFREFMODE	(1 << 20)
+#define VRFCPEN		(1 << 21)
+#define VRFCPSTBY	(1 << 22)
+#define VRFCPMODE	(1 << 23)
+
+/* REG_MODE_1 */
+#define VSIMEN		(1 << 0)
+#define VSIMSTBY	(1 << 1)
+#define VSIMMODE	(1 << 2)
+#define VESIMEN		(1 << 3)
+#define VESIMSTBY	(1 << 4)
+#define VESIMMODE	(1 << 5)
+#define VCAMEN		(1 << 6)
+#define VCAMSTBY	(1 << 7)
+#define VCAMMODE	(1 << 8)
+#define VRFBGEN		(1 << 9)
+#define VRFBGSTBY	(1 << 10)
+#define VVIBEN		(1 << 11)
+#define VRF1EN		(1 << 12)
+#define VRF1STBY	(1 << 13)
+#define VRF1MODE	(1 << 14)
+#define VRF2EN		(1 << 15)
+#define VRF2STBY	(1 << 16)
+#define VRF2MODE	(1 << 17)
+#define VMMC1EN		(1 << 18)
+#define VMMC1STBY	(1 << 19)
+#define VMMC1MODE	(1 << 20)
+#define VMMC2EN		(1 << 21)
+#define VMMC2STBY	(1 << 22)
+#define VMMC2MODE	(1 << 23)
+
+#endif
diff --git a/include/mc13892.h b/include/mc13892.h
new file mode 100644
index 0000000..8e8b63e
--- /dev/null
+++ b/include/mc13892.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ */
+
+
+#ifndef __MC13892_H__
+#define __MC13892_H__
+
+/* REG_CHARGE */
+
+#define VCHRG0		(1 << 0)
+#define VCHRG1		(1 << 1)
+#define VCHRG2		(1 << 2)
+#define ICHRG0		(1 << 3)
+#define ICHRG1		(1 << 4)
+#define ICHRG2		(1 << 5)
+#define ICHRG3		(1 << 6)
+#define TREN		(1 << 7)
+#define ACKLPB		(1 << 8)
+#define THCHKB		(1 << 9)
+#define FETOVRD		(1 << 10)
+#define FETCTRL		(1 << 11)
+#define RVRSMODE	(1 << 13)
+#define PLIM0		(1 << 15)
+#define PLIM1		(1 << 16)
+#define PLIMDIS		(1 << 17)
+#define CHRGLEDEN	(1 << 18)
+#define CHGTMRRST	(1 << 19)
+#define CHGRESTART	(1 << 20)
+#define CHGAUTOB	(1 << 21)
+#define CYCLB		(1 << 22)
+#define CHGAUTOVIB	(1 << 23)
+
+/* REG_SETTING_0/1 */
+#define VO_1_20V	0
+#define VO_1_30V	1
+#define VO_1_50V	2
+#define VO_1_80V	3
+#define VO_1_10V	4
+#define VO_2_00V	5
+#define VO_2_77V	6
+#define VO_2_40V	7
+
+#define VIOL		2
+#define VDIG		4
+#define VGEN		6
+
+/* SWxMode for Normal/Standby Mode */
+#define SWMODE_OFF_OFF		0
+#define SWMODE_PWM_OFF		1
+#define SWMODE_PWMPS_OFF	2
+#define SWMODE_PFM_OFF		3
+#define SWMODE_AUTO_OFF		4
+#define SWMODE_PWM_PWM		5
+#define SWMODE_PWM_AUTO		6
+#define SWMODE_AUTO_AUTO	8
+#define SWMODE_PWM_PWMPS	9
+#define SWMODE_PWMS_PWMPS	10
+#define SWMODE_PWMS_AUTO	11
+#define SWMODE_AUTO_PFM		12
+#define SWMODE_PWM_PFM		13
+#define SWMODE_PWMS_PFM		14
+#define SWMODE_PFM_PFM		15
+#define SWMODE_MASK		0x0F
+
+#define SWMODE1_SHIFT		0
+#define SWMODE2_SHIFT		10
+#define SWMODE3_SHIFT		0
+#define SWMODE4_SHIFT		8
+
+/* Fields in REG_SETTING_1 */
+#define VVIDEO_2_7	(0 << 2)
+#define VVIDEO_2_775	(1 << 2)
+#define VVIDEO_2_5	(2 << 2)
+#define VVIDEO_2_6	(3 << 2)
+#define VVIDEO_MASK	(3 << 2)
+#define VAUDIO_2_3	(0 << 4)
+#define VAUDIO_2_5	(1 << 4)
+#define VAUDIO_2_775	(2 << 4)
+#define VAUDIO_3_0	(3 << 4)
+#define VAUDIO_MASK	(3 << 4)
+#define VSD_1_8		(0 << 6)
+#define VSD_2_0		(1 << 6)
+#define VSD_2_6		(2 << 6)
+#define VSD_2_7		(3 << 6)
+#define VSD_2_8		(4 << 6)
+#define VSD_2_9		(5 << 6)
+#define VSD_3_0		(6 << 6)
+#define VSD_3_15	(7 << 6)
+#define VSD_MASK	(7 << 6)
+#define VGEN1_1_2	0
+#define VGEN1_1_5	1
+#define VGEN1_2_775	2
+#define VGEN1_3_15	3
+#define VGEN1_MASK	3
+#define VGEN2_1_2	(0 << 6)
+#define VGEN2_1_5	(1 << 6)
+#define VGEN2_1_6	(2 << 6)
+#define VGEN2_1_8	(3 << 6)
+#define VGEN2_2_7	(4 << 6)
+#define VGEN2_2_8	(5 << 6)
+#define VGEN2_3_0	(6 << 6)
+#define VGEN2_3_15	(7 << 6)
+#define VGEN2_MASK	(7 << 6)
+
+/* Fields in REG_SETTING_1 */
+#define VGEN3_1_8	(0 << 14)
+#define VGEN3_2_9	(1 << 14)
+#define VGEN3_MASK	(1 << 14)
+#define VDIG_1_05	(0 << 4)
+#define VDIG_1_25	(1 << 4)
+#define VDIG_1_65	(2 << 4)
+#define VDIG_1_8	(3 << 4)
+#define VDIG_MASK	(3 << 4)
+#define VCAM_2_5	(0 << 16)
+#define VCAM_2_6	(1 << 16)
+#define VCAM_2_75	(2 << 16)
+#define VCAM_3_0	(3 << 16)
+#define VCAM_MASK	(3 << 16)
+
+/* Reg Mode 0 */
+#define VGEN1EN		(1 << 0)
+#define VGEN1STBY	(1 << 1)
+#define VGEN1MODE	(1 << 2)
+#define VIOHIEN		(1 << 3)
+#define VIOHISTBY	(1 << 4)
+#define VDIGEN		(1 << 9)
+#define VDIGSTBY	(1 << 10)
+#define VGEN2EN		(1 << 12)
+#define VGEN2STBY	(1 << 13)
+#define VGEN2MODE	(1 << 14)
+#define VPLLEN		(1 << 15)
+#define VPLLSTBY	(1 << 16)
+#define VUSBEN		(1 << 18)
+#define VUSBSTBY	(1 << 19)
+
+/* Reg Mode 1 */
+#define VGEN3EN		(1 << 0)
+#define VGEN3STBY	(1 << 1)
+#define VGEN3MODE	(1 << 2)
+#define VGEN3CONFIG	(1 << 3)
+#define VCAMEN		(1 << 6)
+#define VCAMSTBY	(1 << 7)
+#define VCAMMODE	(1 << 8)
+#define VCAMCONFIG	(1 << 9)
+#define VVIDEOEN	(1 << 12)
+#define VIDEOSTBY	(1 << 13)
+#define VVIDEOMODE	(1 << 14)
+#define VAUDIOEN	(1 << 15)
+#define VAUDIOSTBY	(1 << 16)
+#define VSDEN		(1 << 18)
+#define VSDSTBY		(1 << 19)
+#define VSDMODE		(1 << 20)
+
+/* Reg Power Control 2*/
+#define WDIRESET	(1 << 12)
+
+/* SWx Output Volts */
+#define SWX_OUT_MASK	0x1F
+#define SWX_OUT_1_25	0x1A
+#define SWX_OUT_1_30    0X1C
+
+/* Buck Switchers (SW1,2,3,4) Output Voltage */
+/*
+ * NOTE: These values are for SWxHI = 0,
+ * SWxHI = 1 adds 0.5V to the desired voltage
+ */
+#define SWx_0_600V	0
+#define SWx_0_625V	1
+#define SWx_0_650V	2
+#define SWx_0_675V	3
+#define SWx_0_700V	4
+#define SWx_0_725V	5
+#define SWx_0_750V	6
+#define SWx_0_775V	7
+#define SWx_0_800V	8
+#define SWx_0_825V	9
+#define SWx_0_850V	10
+#define SWx_0_875V	11
+#define SWx_0_900V	12
+#define SWx_0_925V	13
+#define SWx_0_950V	14
+#define SWx_0_975V	15
+#define SWx_1_000V	16
+#define SWx_1_025V	17
+#define SWx_1_050V	18
+#define SWx_1_075V	19
+#define SWx_1_100V	20
+#define SWx_1_125V	21
+#define SWx_1_150V	22
+#define SWx_1_175V	23
+#define SWx_1_200V	24
+#define SWx_1_225V	25
+#define SWx_1_250V	26
+#define SWx_1_275V	27
+#define SWx_1_300V	28
+#define SWx_1_325V	29
+#define SWx_1_350V	30
+#define SWx_1_375V	31
+#define SWx_VOLT_MASK	0x1F
+
+#endif
diff --git a/include/mc34704.h b/include/mc34704.h
new file mode 100644
index 0000000..b837dda
--- /dev/null
+++ b/include/mc34704.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __MC34704_H__
+#define __MC34704_H__
+
+enum {
+	MC34704_RESERVED0_REG = 0,	/* 0x00 */
+	MC34704_GENERAL1_REG,		/* 0x01 */
+	MC34704_GENERAL2_REG,		/* 0x02 */
+	MC34704_GENERAL3_REG,		/* 0x03 */
+	MC34704_RESERVED4_REG,		/* 0x04 */
+	MC34704_VGSET2_REG,		/* 0x05 */
+	MC34704_REG2SET1_REG,		/* 0x06 */
+	MC34704_REG2SET2_REG,		/* 0x07 */
+	MC34704_REG3SET1_REG,		/* 0x08 */
+	MC34704_REG3SET2_REG,		/* 0x09 */
+	MC34704_REG4SET1_REG,		/* 0x0a */
+	MC34704_REG4SET2_REG,		/* 0x0b */
+	MC34704_REG5SET1_REG,		/* 0x0c */
+	MC34704_REG5SET2_REG,		/* 0x0d */
+	MC34704_REG5SET3_REG,		/* 0x0e */
+	MC34704_RESERVEDF_REG,		/* 0x0f */
+	MC34704_RESERVED10_REG,		/* 0x10 */
+	MC34704_RESERVED11_REG,		/* 0x11 */
+	MC34704_RESERVED12_REG,		/* 0x12 */
+	MC34704_FSW2SET_REG,		/* 0x13 */
+	MC34704_RESERVED14_REG,		/* 0x14 */
+	MC34704_REG8SET1_REG,		/* 0x15 */
+	MC34704_REG8SET2_REG,		/* 0x16 */
+	MC34704_REG8SET3_REG,		/* 0x17 */
+	MC34704_FAULTS_REG,		/* 0x18 */
+	MC34704_I2CSET1,		/* 0x19 */
+	MC34704_NUM_OF_REGS,
+};
+
+/* GENERAL2 register fields */
+#define ONOFFE		(1 << 0)
+#define ONOFFD		(1 << 1)
+#define ONOFFA		(1 << 3)
+#define ALLOFF		(1 << 4)
+
+#endif /* __MC34704_H__ */
diff --git a/include/mc9sdz60.h b/include/mc9sdz60.h
new file mode 100644
index 0000000..ffe376b
--- /dev/null
+++ b/include/mc9sdz60.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de>
+ *
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+#ifndef __ASM_ARCH_MC9SDZ60_H
+#define __ASM_ARCH_MC9SDZ60_H
+
+/**
+ * Register addresses for the MC9SDZ60
+ *
+ * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h
+ * but not include/linux/mfd/mc9s08dz60/pmic.h
+ *
+ */
+enum mc9sdz60_reg {
+	MC9SDZ60_REG_VERSION		= 0x00,
+	/* reserved                       0x01 */
+	MC9SDZ60_REG_SECS		= 0x02,
+	MC9SDZ60_REG_MINS		= 0x03,
+	MC9SDZ60_REG_HRS		= 0x04,
+	MC9SDZ60_REG_DAY		= 0x05,
+	MC9SDZ60_REG_DATE		= 0x06,
+	MC9SDZ60_REG_MONTH		= 0x07,
+	MC9SDZ60_REG_YEAR		= 0x08,
+	MC9SDZ60_REG_ALARM_SECS		= 0x09,
+	MC9SDZ60_REG_ALARM_MINS		= 0x0a,
+	MC9SDZ60_REG_ALARM_HRS		= 0x0b,
+	/* reserved                       0x0c */
+	/* reserved                       0x0d */
+	MC9SDZ60_REG_TS_CONTROL		= 0x0e,
+	MC9SDZ60_REG_X_LOW		= 0x0f,
+	MC9SDZ60_REG_Y_LOW		= 0x10,
+	MC9SDZ60_REG_XY_HIGH		= 0x11,
+	MC9SDZ60_REG_X_LEFT_LOW		= 0x12,
+	MC9SDZ60_REG_X_LEFT_HIGH	= 0x13,
+	MC9SDZ60_REG_X_RIGHT		= 0x14,
+	MC9SDZ60_REG_Y_TOP_LOW		= 0x15,
+	MC9SDZ60_REG_Y_TOP_HIGH		= 0x16,
+	MC9SDZ60_REG_Y_BOTTOM		= 0x17,
+	/* reserved                       0x18 */
+	/* reserved                       0x19 */
+	MC9SDZ60_REG_RESET_1		= 0x1a,
+	MC9SDZ60_REG_RESET_2		= 0x1b,
+	MC9SDZ60_REG_POWER_CTL		= 0x1c,
+	MC9SDZ60_REG_DELAY_CONFIG	= 0x1d,
+	/* reserved                       0x1e */
+	/* reserved                       0x1f */
+	MC9SDZ60_REG_GPIO_1		= 0x20,
+	MC9SDZ60_REG_GPIO_2		= 0x21,
+	MC9SDZ60_REG_KPD_1		= 0x22,
+	MC9SDZ60_REG_KPD_2		= 0x23,
+	MC9SDZ60_REG_KPD_CONTROL	= 0x24,
+	MC9SDZ60_REG_INT_ENABLE_1	= 0x25,
+	MC9SDZ60_REG_INT_ENABLE_2	= 0x26,
+	MC9SDZ60_REG_INT_FLAG_1		= 0x27,
+	MC9SDZ60_REG_INT_FLAG_2		= 0x28,
+	MC9SDZ60_REG_DES_FLAG		= 0x29,
+};
+
+extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg);
+extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val);
+
+#endif /* __ASM_ARCH_MC9SDZ60_H */
diff --git a/include/media_bus_format.h b/include/media_bus_format.h
new file mode 100644
index 0000000..d6a5a3b
--- /dev/null
+++ b/include/media_bus_format.h
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Media Bus API header
+ *
+ * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MEDIA_BUS_FORMAT_H
+#define __LINUX_MEDIA_BUS_FORMAT_H
+
+/*
+ * These bus formats uniquely identify data formats on the data bus. Format 0
+ * is reserved, MEDIA_BUS_FMT_FIXED shall be used by host-client pairs, where
+ * the data format is fixed. Additionally, "2X8" means that one pixel is
+ * transferred in two 8-bit samples, "BE" or "LE" specify in which order those
+ * samples are transferred over the bus: "LE" means that the least significant
+ * bits are transferred first, "BE" means that the most significant bits are
+ * transferred first, and "PADHI" and "PADLO" define which bits - low or high,
+ * in the incomplete high byte, are filled with padding bits.
+ *
+ * The bus formats are grouped by type, bus_width, bits per component, samples
+ * per pixel and order of subsamples. Numerical values are sorted using generic
+ * numerical sort order (8 thus comes before 10).
+ *
+ * As their value can't change when a new bus format is inserted in the
+ * enumeration, the bus formats are explicitly given a numerical value. The next
+ * free values for each category are listed below, update them when inserting
+ * new pixel codes.
+ */
+
+#define MEDIA_BUS_FMT_FIXED			0x0001
+
+/* RGB - next is	0x101b */
+#define MEDIA_BUS_FMT_RGB444_1X12		0x1016
+#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE	0x1001
+#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE	0x1002
+#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE	0x1003
+#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE	0x1004
+#define MEDIA_BUS_FMT_RGB565_1X16		0x1017
+#define MEDIA_BUS_FMT_BGR565_2X8_BE		0x1005
+#define MEDIA_BUS_FMT_BGR565_2X8_LE		0x1006
+#define MEDIA_BUS_FMT_RGB565_2X8_BE		0x1007
+#define MEDIA_BUS_FMT_RGB565_2X8_LE		0x1008
+#define MEDIA_BUS_FMT_RGB666_1X18		0x1009
+#define MEDIA_BUS_FMT_RBG888_1X24		0x100e
+#define MEDIA_BUS_FMT_RGB666_1X24_CPADHI	0x1015
+#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG		0x1010
+#define MEDIA_BUS_FMT_BGR888_1X24		0x1013
+#define MEDIA_BUS_FMT_GBR888_1X24		0x1014
+#define MEDIA_BUS_FMT_RGB888_1X24		0x100a
+#define MEDIA_BUS_FMT_RGB888_2X12_BE		0x100b
+#define MEDIA_BUS_FMT_RGB888_2X12_LE		0x100c
+#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG		0x1011
+#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA	0x1012
+#define MEDIA_BUS_FMT_ARGB8888_1X32		0x100d
+#define MEDIA_BUS_FMT_RGB888_1X32_PADHI		0x100f
+#define MEDIA_BUS_FMT_RGB101010_1X30		0x1018
+#define MEDIA_BUS_FMT_RGB121212_1X36		0x1019
+#define MEDIA_BUS_FMT_RGB161616_1X48		0x101a
+
+/* YUV (including grey) - next is	0x202d */
+#define MEDIA_BUS_FMT_Y8_1X8			0x2001
+#define MEDIA_BUS_FMT_UV8_1X8			0x2015
+#define MEDIA_BUS_FMT_UYVY8_1_5X8		0x2002
+#define MEDIA_BUS_FMT_VYUY8_1_5X8		0x2003
+#define MEDIA_BUS_FMT_YUYV8_1_5X8		0x2004
+#define MEDIA_BUS_FMT_YVYU8_1_5X8		0x2005
+#define MEDIA_BUS_FMT_UYVY8_2X8			0x2006
+#define MEDIA_BUS_FMT_VYUY8_2X8			0x2007
+#define MEDIA_BUS_FMT_YUYV8_2X8			0x2008
+#define MEDIA_BUS_FMT_YVYU8_2X8			0x2009
+#define MEDIA_BUS_FMT_Y10_1X10			0x200a
+#define MEDIA_BUS_FMT_Y10_2X8_PADHI_LE		0x202c
+#define MEDIA_BUS_FMT_UYVY10_2X10		0x2018
+#define MEDIA_BUS_FMT_VYUY10_2X10		0x2019
+#define MEDIA_BUS_FMT_YUYV10_2X10		0x200b
+#define MEDIA_BUS_FMT_YVYU10_2X10		0x200c
+#define MEDIA_BUS_FMT_Y12_1X12			0x2013
+#define MEDIA_BUS_FMT_UYVY12_2X12		0x201c
+#define MEDIA_BUS_FMT_VYUY12_2X12		0x201d
+#define MEDIA_BUS_FMT_YUYV12_2X12		0x201e
+#define MEDIA_BUS_FMT_YVYU12_2X12		0x201f
+#define MEDIA_BUS_FMT_UYVY8_1X16		0x200f
+#define MEDIA_BUS_FMT_VYUY8_1X16		0x2010
+#define MEDIA_BUS_FMT_YUYV8_1X16		0x2011
+#define MEDIA_BUS_FMT_YVYU8_1X16		0x2012
+#define MEDIA_BUS_FMT_YDYUYDYV8_1X16		0x2014
+#define MEDIA_BUS_FMT_UYVY10_1X20		0x201a
+#define MEDIA_BUS_FMT_VYUY10_1X20		0x201b
+#define MEDIA_BUS_FMT_YUYV10_1X20		0x200d
+#define MEDIA_BUS_FMT_YVYU10_1X20		0x200e
+#define MEDIA_BUS_FMT_VUY8_1X24			0x2024
+#define MEDIA_BUS_FMT_YUV8_1X24			0x2025
+#define MEDIA_BUS_FMT_UYYVYY8_0_5X24		0x2026
+#define MEDIA_BUS_FMT_UYVY12_1X24		0x2020
+#define MEDIA_BUS_FMT_VYUY12_1X24		0x2021
+#define MEDIA_BUS_FMT_YUYV12_1X24		0x2022
+#define MEDIA_BUS_FMT_YVYU12_1X24		0x2023
+#define MEDIA_BUS_FMT_YUV10_1X30		0x2016
+#define MEDIA_BUS_FMT_UYYVYY10_0_5X30		0x2027
+#define MEDIA_BUS_FMT_AYUV8_1X32		0x2017
+#define MEDIA_BUS_FMT_UYYVYY12_0_5X36		0x2028
+#define MEDIA_BUS_FMT_YUV12_1X36		0x2029
+#define MEDIA_BUS_FMT_YUV16_1X48		0x202a
+#define MEDIA_BUS_FMT_UYYVYY16_0_5X48		0x202b
+
+/* Bayer - next is	0x3021 */
+#define MEDIA_BUS_FMT_SBGGR8_1X8		0x3001
+#define MEDIA_BUS_FMT_SGBRG8_1X8		0x3013
+#define MEDIA_BUS_FMT_SGRBG8_1X8		0x3002
+#define MEDIA_BUS_FMT_SRGGB8_1X8		0x3014
+#define MEDIA_BUS_FMT_SBGGR10_ALAW8_1X8		0x3015
+#define MEDIA_BUS_FMT_SGBRG10_ALAW8_1X8		0x3016
+#define MEDIA_BUS_FMT_SGRBG10_ALAW8_1X8		0x3017
+#define MEDIA_BUS_FMT_SRGGB10_ALAW8_1X8		0x3018
+#define MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8		0x300b
+#define MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8		0x300c
+#define MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8		0x3009
+#define MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8		0x300d
+#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE	0x3003
+#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE	0x3004
+#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE	0x3005
+#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE	0x3006
+#define MEDIA_BUS_FMT_SBGGR10_1X10		0x3007
+#define MEDIA_BUS_FMT_SGBRG10_1X10		0x300e
+#define MEDIA_BUS_FMT_SGRBG10_1X10		0x300a
+#define MEDIA_BUS_FMT_SRGGB10_1X10		0x300f
+#define MEDIA_BUS_FMT_SBGGR12_1X12		0x3008
+#define MEDIA_BUS_FMT_SGBRG12_1X12		0x3010
+#define MEDIA_BUS_FMT_SGRBG12_1X12		0x3011
+#define MEDIA_BUS_FMT_SRGGB12_1X12		0x3012
+#define MEDIA_BUS_FMT_SBGGR14_1X14		0x3019
+#define MEDIA_BUS_FMT_SGBRG14_1X14		0x301a
+#define MEDIA_BUS_FMT_SGRBG14_1X14		0x301b
+#define MEDIA_BUS_FMT_SRGGB14_1X14		0x301c
+#define MEDIA_BUS_FMT_SBGGR16_1X16		0x301d
+#define MEDIA_BUS_FMT_SGBRG16_1X16		0x301e
+#define MEDIA_BUS_FMT_SGRBG16_1X16		0x301f
+#define MEDIA_BUS_FMT_SRGGB16_1X16		0x3020
+
+/* JPEG compressed formats - next is	0x4002 */
+#define MEDIA_BUS_FMT_JPEG_1X8			0x4001
+
+/* Vendor specific formats - next is	0x5002 */
+
+/* S5C73M3 sensor specific interleaved UYVY and JPEG */
+#define MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8		0x5001
+
+/* HSV - next is	0x6002 */
+#define MEDIA_BUS_FMT_AHSV8888_1X32		0x6001
+
+#endif /* __LINUX_MEDIA_BUS_FORMAT_H */
diff --git a/include/memalign.h b/include/memalign.h
new file mode 100644
index 0000000..24d9da7
--- /dev/null
+++ b/include/memalign.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#ifndef __ALIGNMEM_H
+#define __ALIGNMEM_H
+
+/*
+ * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture.  It
+ * is used to align DMA buffers.
+ */
+#ifndef __ASSEMBLY__
+#include <asm/cache.h>
+#include <malloc.h>
+
+/*
+ * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the
+ * stack that meets the minimum architecture alignment requirements for DMA.
+ * Such a buffer is useful for DMA operations where flushing and invalidating
+ * the cache before and after a read and/or write operation is required for
+ * correct operations.
+ *
+ * When called the macro creates an array on the stack that is sized such
+ * that:
+ *
+ * 1) The beginning of the array can be advanced enough to be aligned.
+ *
+ * 2) The size of the aligned portion of the array is a multiple of the minimum
+ *    architecture alignment required for DMA.
+ *
+ * 3) The aligned portion contains enough space for the original number of
+ *    elements requested.
+ *
+ * The macro then creates a pointer to the aligned portion of this array and
+ * assigns to the pointer the address of the first element in the aligned
+ * portion of the array.
+ *
+ * Calling the macro as:
+ *
+ *     ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024);
+ *
+ * Will result in something similar to saying:
+ *
+ *     uint32_t    buffer[1024];
+ *
+ * The following differences exist:
+ *
+ * 1) The resulting buffer is guaranteed to be aligned to the value of
+ *    ARCH_DMA_MINALIGN.
+ *
+ * 2) The buffer variable created by the macro is a pointer to the specified
+ *    type, and NOT an array of the specified type.  This can be very important
+ *    if you want the address of the buffer, which you probably do, to pass it
+ *    to the DMA hardware.  The value of &buffer is different in the two cases.
+ *    In the macro case it will be the address of the pointer, not the address
+ *    of the space reserved for the buffer.  However, in the second case it
+ *    would be the address of the buffer.  So if you are replacing hard coded
+ *    stack buffers with this macro you need to make sure you remove the & from
+ *    the locations where you are taking the address of the buffer.
+ *
+ * Note that the size parameter is the number of array elements to allocate,
+ * not the number of bytes.
+ *
+ * This macro can not be used outside of function scope, or for the creation
+ * of a function scoped static buffer.  It can not be used to create a cache
+ * line aligned global buffer.
+ */
+#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1)
+#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad)
+#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad)		\
+	char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align)  \
+		      + (align - 1)];					\
+									\
+	type *name = (type *)ALIGN((uintptr_t)__##name, align)
+#define ALLOC_ALIGN_BUFFER(type, name, size, align)		\
+	ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1)
+#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad)		\
+	ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad)
+#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size)			\
+	ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
+
+/*
+ * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's
+ * purpose is to allow allocating aligned buffers outside of function scope.
+ * Usage of this macro shall be avoided or used with extreme care!
+ */
+#define DEFINE_ALIGN_BUFFER(type, name, size, align)			\
+	static char __##name[ALIGN(size * sizeof(type), align)]	\
+			__aligned(align);				\
+									\
+	static type *name = (type *)__##name
+#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size)			\
+	DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
+
+/**
+ * malloc_cache_aligned() - allocate a memory region aligned to cache line size
+ *
+ * This allocates memory at a cache-line boundary. The amount allocated may
+ * be larger than requested as it is rounded up to the nearest multiple of the
+ * cache-line size. This ensured that subsequent cache operations on this
+ * memory (flush, invalidate) will not affect subsequently allocated regions.
+ *
+ * @size:	Minimum number of bytes to allocate
+ *
+ * @return pointer to new memory region, or NULL if there is no more memory
+ * available.
+ */
+
+/* set ARCH_DMA_MINALIGN to 64, good for all architectures */
+#ifdef ARCH_DMA_MINALIGN
+#undef ARCH_DMA_MINALIGN
+#endif
+#define ARCH_DMA_MINALIGN 64
+
+static inline void *malloc_cache_aligned(size_t size)
+{
+	return memalign(ARCH_DMA_MINALIGN, ALIGN(size, ARCH_DMA_MINALIGN));
+}
+#endif
+
+#endif /* __ALIGNMEM_H */
diff --git a/include/membuff.h b/include/membuff.h
new file mode 100644
index 0000000..c992067
--- /dev/null
+++ b/include/membuff.h
@@ -0,0 +1,245 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * Copyright (c) 1992 Simon Glass
+ */
+
+#ifndef _MEMBUFF_H
+#define _MEMBUFF_H
+
+/**
+ * @struct membuff: holds the state of a membuff - it is used for input and
+ * output buffers. The buffer extends from @start to (@start + @size - 1).
+ * Data in the buffer extends from @tail to @head: it is written in at
+ * @head and read out from @tail. The membuff is empty when @head == @tail
+ * and full when adding another character would make @head == @tail. We
+ * therefore waste one character in the membuff to avoid having an extra flag
+ * to determine whether (when @head == @tail) the membuff is empty or full.
+ *
+ * xxxxxx  data
+ * ......  empty
+ *
+ * .............xxxxxxxxxxxxxxxx.........................
+ *		^		^
+ *		tail		head
+ *
+ * xxxxxxxxxxxxx................xxxxxxxxxxxxxxxxxxxxxxxxx
+ *		^		^
+ *		head		tail
+ */
+struct membuff {
+	char *start;		/** the start of the buffer */
+	char *end;		/** the end of the buffer (start + length) */
+	char *head;		/** current buffer head */
+	char *tail;		/** current buffer tail */
+};
+
+/**
+ * membuff_purge() - reset a membuff to the empty state
+ *
+ * Initialise head and tail pointers so that the membuff becomes empty.
+ *
+ * @mb: membuff to purge
+ */
+void membuff_purge(struct membuff *mb);
+
+/**
+ * membuff_putraw() - find out where bytes can be written
+ *
+ * Work out where in the membuff some data could be written. Return a pointer
+ * to the address and the number of bytes which can be written there. If
+ * @update is true, the caller must then write the data immediately, since
+ * the membuff is updated as if the write has been done,
+ *
+ * Note that because the spare space in a membuff may not be contiguous, this
+ * function may not return @maxlen even if there is enough space in the
+ * membuff. However, by calling this function twice (with @update == true),
+ * you will get access to all the spare space.
+ *
+ * @mb: membuff to adjust
+ * @maxlen: the number of bytes we want to write
+ * @update: true to update the membuff as if the write happened, false to not
+ * @data: the address data can be written to
+ * @return number of bytes which can be written
+ */
+int membuff_putraw(struct membuff *mb, int maxlen, bool update, char **data);
+
+/**
+ * membuff_getraw() - find and return a pointer to available bytes
+ *
+ * Returns a pointer to any valid input data in the given membuff and
+ * optionally marks it as read. Note that not all input data may not be
+ * returned, since data is not necessarily contiguous in the membuff. However,
+ * if you call this function twice (with @update == true) you are guaranteed
+ * to get all available data, in at most two installments.
+ *
+ * @mb: membuff to adjust
+ * @maxlen: maximum number of bytes to get
+ * @update: true to update the membuff as if the bytes have been read (use
+ * false to check bytes without reading them)
+ * @data: returns address of data in input membuff
+ * @return the number of bytes available at *@data
+ */
+int membuff_getraw(struct membuff *mb, int maxlen, bool update, char **data);
+
+/**
+ * membuff_putbyte() - Writes a byte to a membuff
+ *
+ * @mb: membuff to adjust
+ * @ch: byte to write
+ * @return true on success, false if membuff is full
+ */
+bool membuff_putbyte(struct membuff *mb, int ch);
+
+/**
+ * @mb: membuff to adjust
+ * membuff_getbyte() - Read a byte from the membuff
+ * @return the byte read, or -1 if the membuff is empty
+ */
+int membuff_getbyte(struct membuff *mb);
+
+/**
+ * membuff_peekbyte() - check the next available byte
+ *
+ * Return the next byte which membuff_getbyte() would return, without
+ * removing it from the membuff.
+ *
+ * @mb: membuff to adjust
+ * @return the byte peeked, or -1 if the membuff is empty
+ */
+int membuff_peekbyte(struct membuff *mb);
+
+/**
+ * membuff_get() - get data from a membuff
+ *
+ * Copies any available data (up to @maxlen bytes) to @buff and removes it
+ * from the membuff.
+ *
+ * @mb: membuff to adjust
+ * @Buff: address of membuff to transfer bytes to
+ * @maxlen: maximum number of bytes to read
+ * @return the number of bytes read
+ */
+int membuff_get(struct membuff *mb, char *buff, int maxlen);
+
+/**
+ * membuff_put() - write data to a membuff
+ *
+ * Writes some data to a membuff. Returns the number of bytes added. If this
+ * is less than @lnehgt, then the membuff got full
+ *
+ * @mb: membuff to adjust
+ * @data: the data to write
+ * @length: number of bytes to write from 'data'
+ * @return the number of bytes added
+ */
+int membuff_put(struct membuff *mb, const char *buff, int length);
+
+/**
+ * membuff_isempty() - check if a membuff is empty
+ *
+ * @mb: membuff to check
+ * @return true if empty, else false
+ */
+bool membuff_isempty(struct membuff *mb);
+
+/**
+ * membuff_avail() - check available data in a membuff
+ *
+ * @mb: membuff to check
+ * @return number of bytes of data available
+ */
+int membuff_avail(struct membuff *mb);
+
+/**
+ * membuff_size() - get the size of a membuff
+ *
+ * Note that a membuff can only old data up to one byte less than its size.
+ *
+ * @mb: membuff to check
+ * @return total size
+ */
+int membuff_size(struct membuff *mb);
+
+/**
+ * membuff_makecontig() - adjust all membuff data to be contiguous
+ *
+ * This places all data in a membuff into a single contiguous lump, if
+ * possible
+ *
+ * @mb: membuff to adjust
+ * @return true on success
+ */
+bool membuff_makecontig(struct membuff *mb);
+
+/**
+ * membuff_free() - find the number of bytes that can be written to a membuff
+ *
+ * @mb: membuff to check
+ * @return returns the number of bytes free in a membuff
+ */
+int membuff_free(struct membuff *mb);
+
+/**
+ * membuff_readline() - read a line of text from a membuff
+ *
+ * Reads a line of text of up to 'maxlen' characters from a membuff and puts
+ * it in @str. Any character less than @minch is assumed to be the end of
+ * line character
+ *
+ * @mb: membuff to adjust
+ * @str: Place to put the line
+ * @maxlen: Maximum line length (excluding terminator)
+ * @return number of bytes read (including terminator) if a line has been
+ *	   read, 0 if nothing was there
+ */
+int membuff_readline(struct membuff *mb, char *str, int maxlen, int minch);
+
+/**
+ * membuff_extend_by() - expand a membuff
+ *
+ * Extends a membuff by the given number of bytes
+ *
+ * @mb: membuff to adjust
+ * @by: Number of bytes to increase the size by
+ * @max: Maximum size to allow
+ * @return 0 if the expand succeeded, -ENOMEM if not enough memory, -E2BIG
+ * if the the size would exceed @max
+ */
+int membuff_extend_by(struct membuff *mb, int by, int max);
+
+/**
+ * membuff_init() - set up a new membuff using an existing membuff
+ *
+ * @mb: membuff to set up
+ * @buff: Address of buffer
+ * @size: Size of buffer
+ */
+void membuff_init(struct membuff *mb, char *buff, int size);
+
+/**
+ * membuff_uninit() - clear a membuff so it can no longer be used
+ *
+ * @mb: membuff to uninit
+ */
+void membuff_uninit(struct membuff *mb);
+
+/**
+ * membuff_new() - create a new membuff
+ *
+ * @mb: membuff to init
+ * @size: size of membuff to create
+ * @return 0 if OK, -ENOMEM if out of memory
+ */
+int membuff_new(struct membuff *mb, int size);
+
+/**
+ * membuff_dispose() - free memory allocated to a membuff and uninit it
+ *
+ * @mb: membuff to dispose
+ */
+void membuff_dispose(struct membuff *mb);
+
+#endif
diff --git a/include/menu.h b/include/menu.h
new file mode 100644
index 0000000..2d227c2
--- /dev/null
+++ b/include/menu.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ */
+
+#ifndef __MENU_H__
+#define __MENU_H__
+
+struct menu;
+
+struct menu *menu_create(char *title, int timeout, int prompt,
+				void (*item_data_print)(void *),
+				char *(*item_choice)(void *),
+				void *item_choice_data);
+int menu_default_set(struct menu *m, char *item_key);
+int menu_get_choice(struct menu *m, void **choice);
+int menu_item_add(struct menu *m, char *item_key, void *item_data);
+int menu_destroy(struct menu *m);
+void menu_display_statusline(struct menu *m);
+int menu_default_choice(struct menu *m, void **choice);
+
+/**
+ * menu_show() Show a boot menu
+ *
+ * This shows a menu and lets the user select an option. The menu is defined by
+ * environment variables (see README.bootmenu).
+ *
+ * This function doesn't normally return, but if the users requests the command
+ * problem, it will.
+ *
+ * @bootdelay: Delay to wait before running the default menu option (0 to run
+ *		the entry immediately)
+ * @return If it returns, it always returns -1 to indicate that the boot should
+ *	be aborted and the command prompt should be provided
+ */
+int menu_show(int bootdelay);
+
+#endif /* __MENU_H__ */
diff --git a/include/micrel.h b/include/micrel.h
new file mode 100644
index 0000000..3e6b531
--- /dev/null
+++ b/include/micrel.h
@@ -0,0 +1,39 @@
+#ifndef _MICREL_H
+
+#define MII_KSZ9021_EXT_COMMON_CTRL		0x100
+#define MII_KSZ9021_EXT_STRAP_STATUS		0x101
+#define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE	0x102
+#define MII_KSZ9021_EXT_OP_STRAP_STATUS		0x103
+#define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW	0x104
+#define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW	0x105
+#define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW	0x106
+#define MII_KSZ9021_EXT_ANALOG_TEST		0x107
+/* Register operations */
+#define MII_KSZ9031_MOD_REG			0x0000
+/* Data operations */
+#define MII_KSZ9031_MOD_DATA_NO_POST_INC	0x4000
+#define MII_KSZ9031_MOD_DATA_POST_INC_RW	0x8000
+#define MII_KSZ9031_MOD_DATA_POST_INC_W		0xC000
+
+#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW	0x4
+#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW	0x5
+#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW	0x6
+#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW	0x8
+
+#define MII_KSZ9031_FLP_BURST_TX_LO		0x3
+#define MII_KSZ9031_FLP_BURST_TX_HI		0x4
+
+/* Registers */
+#define MMD_ACCESS_CONTROL	0xd
+#define MMD_ACCESS_REG_DATA	0xe
+
+struct phy_device;
+int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
+int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
+
+int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
+			       int regnum, u16 mode, u16 val);
+int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
+			      int regnum, u16 mode);
+
+#endif
diff --git a/include/mii_phy.h b/include/mii_phy.h
new file mode 100644
index 0000000..f0d3e62
--- /dev/null
+++ b/include/mii_phy.h
@@ -0,0 +1,8 @@
+#ifndef _MII_PHY_H_
+#define _MII_PHY_H_
+
+void mii_discover_phy(void);
+unsigned short mii_phy_read(unsigned short reg);
+void mii_phy_write(unsigned short reg, unsigned short val);
+
+#endif
diff --git a/include/miiphy.h b/include/miiphy.h
new file mode 100644
index 0000000..9b97d09
--- /dev/null
+++ b/include/miiphy.h
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0 OR IBM-pibs */
+/*
+ * Additions (C) Copyright 2009 Industrie Dial Face S.p.A.
+ */
+/*----------------------------------------------------------------------------+
+|
+|  File Name:	miiphy.h
+|
+|  Function:	Include file defining PHY registers.
+|
+|  Author:	Mark Wisner
+|
++----------------------------------------------------------------------------*/
+#ifndef _miiphy_h_
+#define _miiphy_h_
+
+#include <common.h>
+#include <linux/mii.h>
+#include <linux/list.h>
+#include <net.h>
+#include <phy.h>
+
+int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
+		 unsigned short *value);
+int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
+		  unsigned short value);
+int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
+		 unsigned char *model, unsigned char *rev);
+int miiphy_reset(const char *devname, unsigned char addr);
+int miiphy_speed(const char *devname, unsigned char addr);
+int miiphy_duplex(const char *devname, unsigned char addr);
+int miiphy_is_1000base_x(const char *devname, unsigned char addr);
+#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+int miiphy_link(const char *devname, unsigned char addr);
+#endif
+
+void miiphy_init(void);
+
+int miiphy_set_current_dev(const char *devname);
+const char *miiphy_get_current_dev(void);
+struct mii_dev *mdio_get_current_dev(void);
+struct list_head *mdio_get_list_head(void);
+struct mii_dev *miiphy_get_dev_by_name(const char *devname);
+struct phy_device *mdio_phydev_for_ethname(const char *devname);
+
+void miiphy_listdev(void);
+
+struct mii_dev *mdio_alloc(void);
+void mdio_free(struct mii_dev *bus);
+int mdio_register(struct mii_dev *bus);
+
+/**
+ * mdio_register_seq - Register mdio bus with sequence number
+ * @bus: mii device structure
+ * @seq: sequence number
+ *
+ * Return: 0 if success, negative value if error
+ */
+int mdio_register_seq(struct mii_dev *bus, int seq);
+int mdio_unregister(struct mii_dev *bus);
+void mdio_list_devices(void);
+
+#ifdef CONFIG_BITBANGMII
+
+#define BB_MII_DEVNAME	"bb_miiphy"
+
+struct bb_miiphy_bus {
+	char name[16];
+	int (*init)(struct bb_miiphy_bus *bus);
+	int (*mdio_active)(struct bb_miiphy_bus *bus);
+	int (*mdio_tristate)(struct bb_miiphy_bus *bus);
+	int (*set_mdio)(struct bb_miiphy_bus *bus, int v);
+	int (*get_mdio)(struct bb_miiphy_bus *bus, int *v);
+	int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
+	int (*delay)(struct bb_miiphy_bus *bus);
+#ifdef CONFIG_BITBANGMII_MULTI
+	void *priv;
+#endif
+};
+
+extern struct bb_miiphy_bus bb_miiphy_buses[];
+extern int bb_miiphy_buses_num;
+
+void bb_miiphy_init(void);
+int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg);
+int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg,
+		    u16 value);
+#endif
+
+/* phy seed setup */
+#define AUTO			99
+#define _1000BASET		1000
+#define _100BASET		100
+#define _10BASET		10
+#define HALF			22
+#define FULL			44
+
+/* phy register offsets */
+#define MII_MIPSCR		0x11
+
+/* MII_LPA */
+#define PHY_ANLPAR_PSB_802_3	0x0001
+#define PHY_ANLPAR_PSB_802_9	0x0002
+
+/* MII_CTRL1000 masks */
+#define PHY_1000BTCR_1000FD	0x0200
+#define PHY_1000BTCR_1000HD	0x0100
+
+/* MII_STAT1000 masks */
+#define PHY_1000BTSR_MSCF	0x8000
+#define PHY_1000BTSR_MSCR	0x4000
+#define PHY_1000BTSR_LRS	0x2000
+#define PHY_1000BTSR_RRS	0x1000
+#define PHY_1000BTSR_1000FD	0x0800
+#define PHY_1000BTSR_1000HD	0x0400
+
+/* phy EXSR */
+#define ESTATUS_1000XF		0x8000
+#define ESTATUS_1000XH		0x4000
+
+#ifdef CONFIG_DM_MDIO
+
+/**
+ * struct mdio_perdev_priv - Per-device class data for MDIO DM
+ *
+ * @mii_bus: Supporting MII legacy bus
+ */
+struct mdio_perdev_priv {
+	struct mii_dev *mii_bus;
+};
+
+/**
+ * struct mdio_ops - MDIO bus operations
+ *
+ * @read: Read from a PHY register
+ * @write: Write to a PHY register
+ * @reset: Reset the MDIO bus, NULL if not supported
+ */
+struct mdio_ops {
+	int (*read)(struct udevice *mdio_dev, int addr, int devad, int reg);
+	int (*write)(struct udevice *mdio_dev, int addr, int devad, int reg,
+		     u16 val);
+	int (*reset)(struct udevice *mdio_dev);
+};
+
+#define mdio_get_ops(dev) ((struct mdio_ops *)(dev)->driver->ops)
+
+/**
+ * dm_mdio_probe_devices - Call probe on all MII devices, currently used for
+ * MDIO console commands.
+ */
+void dm_mdio_probe_devices(void);
+
+/**
+ * dm_mdio_phy_connect - Wrapper over phy_connect for DM MDIO
+ *
+ * @dev: mdio dev
+ * @addr: PHY address on MDIO bus
+ * @ethdev: ethernet device to connect to the PHY
+ * @interface: MAC-PHY protocol
+ *
+ * @return pointer to phy_device, or 0 on error
+ */
+struct phy_device *dm_mdio_phy_connect(struct udevice *dev, int addr,
+				       struct udevice *ethdev,
+				       phy_interface_t interface);
+
+#endif
+
+#ifdef CONFIG_DM_MDIO_MUX
+
+/* indicates none of the child buses is selected */
+#define MDIO_MUX_SELECT_NONE	-1
+
+/**
+ * struct mdio_mux_ops - MDIO MUX operations
+ *
+ * @select: Selects a child bus
+ * @deselect: Clean up selection.  Optional, can be NULL
+ */
+struct mdio_mux_ops {
+	int (*select)(struct udevice *mux, int cur, int sel);
+	int (*deselect)(struct udevice *mux, int sel);
+};
+
+#define mdio_mux_get_ops(dev) ((struct mdio_mux_ops *)(dev)->driver->ops)
+
+#endif
+
+#endif
diff --git a/include/mipi_display.h b/include/mipi_display.h
new file mode 100644
index 0000000..19aa65a
--- /dev/null
+++ b/include/mipi_display.h
@@ -0,0 +1,138 @@
+/*
+ * Defines for Mobile Industry Processor Interface (MIPI(R))
+ * Display Working Group standards: DSI, DCS, DBI, DPI
+ *
+ * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ * Copyright (C) 2006 Nokia Corporation
+ * Author: Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef MIPI_DISPLAY_H
+#define MIPI_DISPLAY_H
+
+/* MIPI DSI Processor-to-Peripheral transaction types */
+enum {
+	MIPI_DSI_V_SYNC_START				= 0x01,
+	MIPI_DSI_V_SYNC_END				= 0x11,
+	MIPI_DSI_H_SYNC_START				= 0x21,
+	MIPI_DSI_H_SYNC_END				= 0x31,
+
+	MIPI_DSI_COLOR_MODE_OFF				= 0x02,
+	MIPI_DSI_COLOR_MODE_ON				= 0x12,
+	MIPI_DSI_SHUTDOWN_PERIPHERAL			= 0x22,
+	MIPI_DSI_TURN_ON_PERIPHERAL			= 0x32,
+
+	MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM		= 0x03,
+	MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM		= 0x13,
+	MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM		= 0x23,
+
+	MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM		= 0x04,
+	MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM		= 0x14,
+	MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM		= 0x24,
+
+	MIPI_DSI_DCS_SHORT_WRITE			= 0x05,
+	MIPI_DSI_DCS_SHORT_WRITE_PARAM			= 0x15,
+
+	MIPI_DSI_DCS_READ				= 0x06,
+
+	MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE		= 0x37,
+
+	MIPI_DSI_END_OF_TRANSMISSION			= 0x08,
+
+	MIPI_DSI_NULL_PACKET				= 0x09,
+	MIPI_DSI_BLANKING_PACKET			= 0x19,
+	MIPI_DSI_GENERIC_LONG_WRITE			= 0x29,
+	MIPI_DSI_DCS_LONG_WRITE				= 0x39,
+
+	MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20	= 0x0c,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24		= 0x1c,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16		= 0x2c,
+
+	MIPI_DSI_PACKED_PIXEL_STREAM_30			= 0x0d,
+	MIPI_DSI_PACKED_PIXEL_STREAM_36			= 0x1d,
+	MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12		= 0x3d,
+
+	MIPI_DSI_PACKED_PIXEL_STREAM_16			= 0x0e,
+	MIPI_DSI_PACKED_PIXEL_STREAM_18			= 0x1e,
+	MIPI_DSI_PIXEL_STREAM_3BYTE_18			= 0x2e,
+	MIPI_DSI_PACKED_PIXEL_STREAM_24			= 0x3e,
+};
+
+/* MIPI DSI Peripheral-to-Processor transaction types */
+enum {
+	MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT	= 0x02,
+	MIPI_DSI_RX_END_OF_TRANSMISSION			= 0x08,
+	MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE	= 0x11,
+	MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE	= 0x12,
+	MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE		= 0x1a,
+	MIPI_DSI_RX_DCS_LONG_READ_RESPONSE		= 0x1c,
+	MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE	= 0x21,
+	MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE	= 0x22,
+};
+
+/* MIPI DCS commands */
+enum {
+	MIPI_DCS_NOP			= 0x00,
+	MIPI_DCS_SOFT_RESET		= 0x01,
+	MIPI_DCS_GET_DISPLAY_ID		= 0x04,
+	MIPI_DCS_GET_RED_CHANNEL	= 0x06,
+	MIPI_DCS_GET_GREEN_CHANNEL	= 0x07,
+	MIPI_DCS_GET_BLUE_CHANNEL	= 0x08,
+	MIPI_DCS_GET_DISPLAY_STATUS	= 0x09,
+	MIPI_DCS_GET_POWER_MODE		= 0x0A,
+	MIPI_DCS_GET_ADDRESS_MODE	= 0x0B,
+	MIPI_DCS_GET_PIXEL_FORMAT	= 0x0C,
+	MIPI_DCS_GET_DISPLAY_MODE	= 0x0D,
+	MIPI_DCS_GET_SIGNAL_MODE	= 0x0E,
+	MIPI_DCS_GET_DIAGNOSTIC_RESULT	= 0x0F,
+	MIPI_DCS_ENTER_SLEEP_MODE	= 0x10,
+	MIPI_DCS_EXIT_SLEEP_MODE	= 0x11,
+	MIPI_DCS_ENTER_PARTIAL_MODE	= 0x12,
+	MIPI_DCS_ENTER_NORMAL_MODE	= 0x13,
+	MIPI_DCS_EXIT_INVERT_MODE	= 0x20,
+	MIPI_DCS_ENTER_INVERT_MODE	= 0x21,
+	MIPI_DCS_SET_GAMMA_CURVE	= 0x26,
+	MIPI_DCS_SET_DISPLAY_OFF	= 0x28,
+	MIPI_DCS_SET_DISPLAY_ON		= 0x29,
+	MIPI_DCS_SET_COLUMN_ADDRESS	= 0x2A,
+	MIPI_DCS_SET_PAGE_ADDRESS	= 0x2B,
+	MIPI_DCS_WRITE_MEMORY_START	= 0x2C,
+	MIPI_DCS_WRITE_LUT		= 0x2D,
+	MIPI_DCS_READ_MEMORY_START	= 0x2E,
+	MIPI_DCS_SET_PARTIAL_AREA	= 0x30,
+	MIPI_DCS_SET_SCROLL_AREA	= 0x33,
+	MIPI_DCS_SET_TEAR_OFF		= 0x34,
+	MIPI_DCS_SET_TEAR_ON		= 0x35,
+	MIPI_DCS_SET_ADDRESS_MODE	= 0x36,
+	MIPI_DCS_SET_SCROLL_START	= 0x37,
+	MIPI_DCS_EXIT_IDLE_MODE		= 0x38,
+	MIPI_DCS_ENTER_IDLE_MODE	= 0x39,
+	MIPI_DCS_SET_PIXEL_FORMAT	= 0x3A,
+	MIPI_DCS_WRITE_MEMORY_CONTINUE	= 0x3C,
+	MIPI_DCS_READ_MEMORY_CONTINUE	= 0x3E,
+	MIPI_DCS_SET_TEAR_SCANLINE	= 0x44,
+	MIPI_DCS_GET_SCANLINE		= 0x45,
+	MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51,		/* MIPI DCS 1.3 */
+	MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52,		/* MIPI DCS 1.3 */
+	MIPI_DCS_WRITE_CONTROL_DISPLAY  = 0x53,		/* MIPI DCS 1.3 */
+	MIPI_DCS_GET_CONTROL_DISPLAY	= 0x54,		/* MIPI DCS 1.3 */
+	MIPI_DCS_WRITE_POWER_SAVE	= 0x55,		/* MIPI DCS 1.3 */
+	MIPI_DCS_GET_POWER_SAVE		= 0x56,		/* MIPI DCS 1.3 */
+	MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E,	/* MIPI DCS 1.3 */
+	MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F,	/* MIPI DCS 1.3 */
+	MIPI_DCS_READ_DDB_START		= 0xA1,
+	MIPI_DCS_READ_DDB_CONTINUE	= 0xA8,
+};
+
+/* MIPI DCS pixel formats */
+#define MIPI_DCS_PIXEL_FMT_24BIT	7
+#define MIPI_DCS_PIXEL_FMT_18BIT	6
+#define MIPI_DCS_PIXEL_FMT_16BIT	5
+#define MIPI_DCS_PIXEL_FMT_12BIT	3
+#define MIPI_DCS_PIXEL_FMT_8BIT		2
+#define MIPI_DCS_PIXEL_FMT_3BIT		1
+
+#endif
diff --git a/include/mipi_dsi.h b/include/mipi_dsi.h
new file mode 100644
index 0000000..f4a63b4
--- /dev/null
+++ b/include/mipi_dsi.h
@@ -0,0 +1,466 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Andrzej Hajda <a.hajda@samsung.com>
+ *            Yannick Fertre <yannick.fertre@st.com>
+ *            Philippe Cornu <philippe.cornu@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef MIPI_DSI_H
+#define MIPI_DSI_H
+
+#include <mipi_display.h>
+
+struct mipi_dsi_host;
+struct mipi_dsi_device;
+
+/* request ACK from peripheral */
+#define MIPI_DSI_MSG_REQ_ACK	BIT(0)
+/* use Low Power Mode to transmit message */
+#define MIPI_DSI_MSG_USE_LPM	BIT(1)
+
+/**
+ * struct mipi_dsi_msg - read/write DSI buffer
+ * @channel: virtual channel id
+ * @type: payload data type
+ * @flags: flags controlling this message transmission
+ * @tx_len: length of @tx_buf
+ * @tx_buf: data to be written
+ * @rx_len: length of @rx_buf
+ * @rx_buf: data to be read, or NULL
+ */
+struct mipi_dsi_msg {
+	u8 channel;
+	u8 type;
+	u16 flags;
+
+	size_t tx_len;
+	const void *tx_buf;
+
+	size_t rx_len;
+	void *rx_buf;
+};
+
+bool mipi_dsi_packet_format_is_short(u8 type);
+bool mipi_dsi_packet_format_is_long(u8 type);
+
+/**
+ * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
+ * @size: size (in bytes) of the packet
+ * @header: the four bytes that make up the header (Data ID, Word Count or
+ *     Packet Data, and ECC)
+ * @payload_length: number of bytes in the payload
+ * @payload: a pointer to a buffer containing the payload, if any
+ */
+struct mipi_dsi_packet {
+	size_t size;
+	u8 header[4];
+	size_t payload_length;
+	const u8 *payload;
+};
+
+int mipi_dsi_create_packet(struct mipi_dsi_packet *packet,
+			   const struct mipi_dsi_msg *msg);
+
+/**
+ * struct mipi_dsi_host_ops - DSI bus operations
+ * @attach: attach DSI device to DSI host
+ * @detach: detach DSI device from DSI host
+ * @transfer: transmit a DSI packet
+ *
+ * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg
+ * structures. This structure contains information about the type of packet
+ * being transmitted as well as the transmit and receive buffers. When an
+ * error is encountered during transmission, this function will return a
+ * negative error code. On success it shall return the number of bytes
+ * transmitted for write packets or the number of bytes received for read
+ * packets.
+ *
+ * Note that typically DSI packet transmission is atomic, so the .transfer()
+ * function will seldomly return anything other than the number of bytes
+ * contained in the transmit buffer on success.
+ */
+struct mipi_dsi_host_ops {
+	int (*attach)(struct mipi_dsi_host *host,
+		      struct mipi_dsi_device *dsi);
+	int (*detach)(struct mipi_dsi_host *host,
+		      struct mipi_dsi_device *dsi);
+	ssize_t (*transfer)(struct mipi_dsi_host *host,
+			    const struct mipi_dsi_msg *msg);
+};
+
+/**
+ * struct mipi_dsi_phy_ops - DSI host physical operations
+ * @init: initialized host physical part
+ * @get_lane_mbps: get lane bitrate per lane (mbps)
+ * @post_set_mode: operation that should after set mode
+ */
+struct mipi_dsi_phy_ops {
+	int (*init)(void *priv_data);
+	int (*get_lane_mbps)(void *priv_data, struct display_timing *timings,
+			     u32 lanes, u32 format, unsigned int *lane_mbps);
+	void (*post_set_mode)(void *priv_data,  unsigned long mode_flags);
+};
+
+/**
+ * struct mipi_dsi_host - DSI host device
+ * @dev: driver model device node for this DSI host
+ * @ops: DSI host operations
+ * @list: list management
+ */
+struct mipi_dsi_host {
+	struct device *dev;
+	const struct mipi_dsi_host_ops *ops;
+	struct list_head list;
+};
+
+/* DSI mode flags */
+
+/* video mode */
+#define MIPI_DSI_MODE_VIDEO		BIT(0)
+/* video burst mode */
+#define MIPI_DSI_MODE_VIDEO_BURST	BIT(1)
+/* video pulse mode */
+#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE	BIT(2)
+/* enable auto vertical count mode */
+#define MIPI_DSI_MODE_VIDEO_AUTO_VERT	BIT(3)
+/* enable hsync-end packets in vsync-pulse and v-porch area */
+#define MIPI_DSI_MODE_VIDEO_HSE		BIT(4)
+/* disable hfront-porch area */
+#define MIPI_DSI_MODE_VIDEO_HFP		BIT(5)
+/* disable hback-porch area */
+#define MIPI_DSI_MODE_VIDEO_HBP		BIT(6)
+/* disable hsync-active area */
+#define MIPI_DSI_MODE_VIDEO_HSA		BIT(7)
+/* flush display FIFO on vsync pulse */
+#define MIPI_DSI_MODE_VSYNC_FLUSH	BIT(8)
+/* disable EoT packets in HS mode */
+#define MIPI_DSI_MODE_EOT_PACKET	BIT(9)
+/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
+#define MIPI_DSI_CLOCK_NON_CONTINUOUS	BIT(10)
+/* transmit data in low power */
+#define MIPI_DSI_MODE_LPM		BIT(11)
+
+enum mipi_dsi_pixel_format {
+	MIPI_DSI_FMT_RGB888,
+	MIPI_DSI_FMT_RGB666,
+	MIPI_DSI_FMT_RGB666_PACKED,
+	MIPI_DSI_FMT_RGB565,
+};
+
+#define DSI_DEV_NAME_SIZE		20
+
+/**
+ * struct mipi_dsi_device_info - template for creating a mipi_dsi_device
+ * @type: DSI peripheral chip type
+ * @channel: DSI virtual channel assigned to peripheral
+ * @node: pointer to OF device node or NULL
+ *
+ * This is populated and passed to mipi_dsi_device_new to create a new
+ * DSI device
+ */
+struct mipi_dsi_device_info {
+	char type[DSI_DEV_NAME_SIZE];
+	u32 channel;
+	struct device_node *node;
+};
+
+/**
+ * struct mipi_dsi_device - DSI peripheral device
+ * @host: DSI host for this peripheral
+ * @dev: driver model device node for this peripheral
+ * @name: DSI peripheral chip type
+ * @channel: virtual channel assigned to the peripheral
+ * @format: pixel format for video mode
+ * @lanes: number of active data lanes
+ * @mode_flags: DSI operation mode related flags
+ */
+struct mipi_dsi_device {
+	struct mipi_dsi_host *host;
+	struct udevice *dev;
+
+	char name[DSI_DEV_NAME_SIZE];
+	unsigned int channel;
+	unsigned int lanes;
+	enum mipi_dsi_pixel_format format;
+	unsigned long mode_flags;
+};
+
+/**
+ * mipi_dsi_pixel_format_to_bpp - obtain the number of bits per pixel for any
+ *                                given pixel format defined by the MIPI DSI
+ *                                specification
+ * @fmt: MIPI DSI pixel format
+ *
+ * Returns: The number of bits per pixel of the given pixel format.
+ */
+static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
+{
+	switch (fmt) {
+	case MIPI_DSI_FMT_RGB888:
+	case MIPI_DSI_FMT_RGB666:
+		return 24;
+
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		return 18;
+
+	case MIPI_DSI_FMT_RGB565:
+		return 16;
+	}
+
+	return -EINVAL;
+}
+
+/**
+ * struct mipi_dsi_panel_plat - DSI panel platform data
+ * @device: DSI peripheral device
+ */
+struct mipi_dsi_panel_plat {
+	struct mipi_dsi_device *device;
+};
+
+/**
+ * mipi_dsi_attach - attach a DSI device to its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_attach(struct mipi_dsi_device *dsi);
+
+/**
+ * mipi_dsi_detach - detach a DSI device from its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_detach(struct mipi_dsi_device *dsi);
+int mipi_dsi_shutdown_peripheral(struct mipi_dsi_device *dsi);
+int mipi_dsi_turn_on_peripheral(struct mipi_dsi_device *dsi);
+int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
+					    u16 value);
+
+ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload,
+			       size_t size);
+ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params,
+			      size_t num_params, void *data, size_t size);
+
+/**
+ * enum mipi_dsi_dcs_tear_mode - Tearing Effect Output Line mode
+ * @MIPI_DSI_DCS_TEAR_MODE_VBLANK: the TE output line consists of V-Blanking
+ *    information only
+ * @MIPI_DSI_DCS_TEAR_MODE_VHBLANK : the TE output line consists of both
+ *    V-Blanking and H-Blanking information
+ */
+enum mipi_dsi_dcs_tear_mode {
+	MIPI_DSI_DCS_TEAR_MODE_VBLANK,
+	MIPI_DSI_DCS_TEAR_MODE_VHBLANK,
+};
+
+#define MIPI_DSI_DCS_POWER_MODE_DISPLAY BIT(2)
+#define MIPI_DSI_DCS_POWER_MODE_NORMAL  BIT(3)
+#define MIPI_DSI_DCS_POWER_MODE_SLEEP   BIT(4)
+#define MIPI_DSI_DCS_POWER_MODE_PARTIAL BIT(5)
+#define MIPI_DSI_DCS_POWER_MODE_IDLE    BIT(6)
+
+/**
+ * mipi_dsi_dcs_write_buffer() - transmit a DCS command with payload
+ * @dsi: DSI peripheral device
+ * @data: buffer containing data to be transmitted
+ * @len: size of transmission buffer
+ *
+ * This function will automatically choose the right data type depending on
+ * the command payload length.
+ *
+ * Return: The number of bytes successfully transmitted or a negative error
+ * code on failure.
+ */
+ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi,
+				  const void *data, size_t len);
+
+/**
+ * mipi_dsi_dcs_write() - send DCS write command
+ * @dsi: DSI peripheral device
+ * @cmd: DCS command
+ * @data: buffer containing the command payload
+ * @len: command payload length
+ *
+ * This function will automatically choose the right data type depending on
+ * the command payload length.
+
+ * code on failure.
+ */
+ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd,
+			   const void *data, size_t len);
+
+/**
+ * mipi_dsi_dcs_read() - send DCS read request command
+ * @dsi: DSI peripheral device
+ * @cmd: DCS command
+ * @data: buffer in which to receive data
+ * @len: size of receive buffer
+ *
+ * Return: The number of bytes read or a negative error code on failure.
+ */
+ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data,
+			  size_t len);
+
+/**
+ * mipi_dsi_dcs_nop() - send DCS nop packet
+ * @dsi: DSI peripheral device
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_nop(struct mipi_dsi_device *dsi);
+
+/**
+ * mipi_dsi_dcs_soft_reset() - perform a software reset of the display module
+ * @dsi: DSI peripheral device
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_soft_reset(struct mipi_dsi_device *dsi);
+
+/**
+ * mipi_dsi_dcs_get_power_mode() - query the display module's current power
+ *    mode
+ * @dsi: DSI peripheral device
+ * @mode: return location for the current power mode
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_get_power_mode(struct mipi_dsi_device *dsi, u8 *mode);
+
+/**
+ * mipi_dsi_dcs_get_pixel_format() - gets the pixel format for the RGB image
+ *    data used by the interface
+ * @dsi: DSI peripheral device
+ * @format: return location for the pixel format
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_get_pixel_format(struct mipi_dsi_device *dsi, u8 *format);
+
+/**
+ * mipi_dsi_dcs_enter_sleep_mode() - disable all unnecessary blocks inside the
+ *    display module except interface communication
+ * @dsi: DSI peripheral device
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_enter_sleep_mode(struct mipi_dsi_device *dsi);
+
+/**
+ * mipi_dsi_dcs_exit_sleep_mode() - enable all blocks inside the display
+ *    module
+ * @dsi: DSI peripheral device
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi);
+
+/**
+ * mipi_dsi_dcs_set_display_off() - stop displaying the image data on the
+ *    display device
+ * @dsi: DSI peripheral device
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_set_display_off(struct mipi_dsi_device *dsi);
+
+/**
+ * mipi_dsi_dcs_set_display_on() - start displaying the image data on the
+ *    display device
+ * @dsi: DSI peripheral device
+ *
+ * Return: 0 on success or a negative error code on failure
+ */
+int mipi_dsi_dcs_set_display_on(struct mipi_dsi_device *dsi);
+
+/**
+ * mipi_dsi_dcs_set_column_address() - define the column extent of the frame
+ *    memory accessed by the host processor
+ * @dsi: DSI peripheral device
+ * @start: first column of frame memory
+ * @end: last column of frame memory
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_set_column_address(struct mipi_dsi_device *dsi, u16 start,
+				    u16 end);
+/**
+ * mipi_dsi_dcs_set_page_address() - define the page extent of the frame
+ *    memory accessed by the host processor
+ * @dsi: DSI peripheral device
+ * @start: first page of frame memory
+ * @end: last page of frame memory
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_set_page_address(struct mipi_dsi_device *dsi, u16 start,
+				  u16 end);
+
+/**
+ * mipi_dsi_dcs_set_tear_off() - turn off the display module's Tearing Effect
+ *    output signal on the TE signal line
+ * @dsi: DSI peripheral device
+ *
+ * Return: 0 on success or a negative error code on failure
+ */
+int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi);
+
+/**
+ * mipi_dsi_dcs_set_tear_on() - turn on the display module's Tearing Effect
+ *    output signal on the TE signal line.
+ * @dsi: DSI peripheral device
+ * @mode: the Tearing Effect Output Line mode
+ *
+ * Return: 0 on success or a negative error code on failure
+ */
+int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi,
+			     enum mipi_dsi_dcs_tear_mode mode);
+
+/**
+ * mipi_dsi_dcs_set_pixel_format() - sets the pixel format for the RGB image
+ *    data used by the interface
+ * @dsi: DSI peripheral device
+ * @format: pixel format
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format);
+
+/**
+ * mipi_dsi_dcs_set_tear_scanline() - set the scanline to use as trigger for
+ *    the Tearing Effect output signal of the display module
+ * @dsi: DSI peripheral device
+ * @scanline: scanline to use as trigger
+ *
+ * Return: 0 on success or a negative error code on failure
+ */
+int mipi_dsi_dcs_set_tear_scanline(struct mipi_dsi_device *dsi, u16 scanline);
+
+/**
+ * mipi_dsi_dcs_set_display_brightness() - sets the brightness value of the
+ *    display
+ * @dsi: DSI peripheral device
+ * @brightness: brightness value
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi,
+					u16 brightness);
+
+/**
+ * mipi_dsi_dcs_get_display_brightness() - gets the current brightness value
+ *    of the display
+ * @dsi: DSI peripheral device
+ * @brightness: brightness value
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi,
+					u16 *brightness);
+
+#endif /* MIPI_DSI_H */
diff --git a/include/misc.h b/include/misc.h
new file mode 100644
index 0000000..12d1325
--- /dev/null
+++ b/include/misc.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
+ */
+
+#ifndef _MISC_H_
+#define _MISC_H_
+
+/**
+ * misc_read() - Read the device to buffer, optional.
+ * @dev: the device
+ * @offset: offset to read the device
+ * @buf: pointer to data buffer
+ * @size: data size in bytes to read the device
+ *
+ * Return: number of bytes read if OK (may be 0 if EOF), -ve on error
+ */
+int misc_read(struct udevice *dev, int offset, void *buf, int size);
+
+/**
+ * misc_write() - Write buffer to the device, optional.
+ * @dev: the device
+ * @offset: offset to write the device
+ * @buf: pointer to data buffer
+ * @size: data size in bytes to write the device
+ *
+ * Return: number of bytes written if OK (may be < @size), -ve on error
+ */
+int misc_write(struct udevice *dev, int offset, void *buf, int size);
+
+/**
+ * misc_ioctl() - Assert command to the device, optional.
+ * @dev: the device
+ * @request: command to be sent to the device
+ * @buf: pointer to buffer related to the request
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int misc_ioctl(struct udevice *dev, unsigned long request, void *buf);
+
+/**
+ * misc_call() - Send a message to the device and wait for a response.
+ * @dev: the device.
+ * @msgid: the message ID/number to send.
+ * @tx_msg: the request/transmit message payload.
+ * @tx_size: the size of the buffer pointed at by tx_msg.
+ * @rx_msg: the buffer to receive the response message payload. May be NULL if
+ *          the caller only cares about the error code.
+ * @rx_size: the size of the buffer pointed at by rx_msg.
+ *
+ * The caller provides the message type/ID and payload to be sent.
+ * The callee constructs any message header required, transmits it to the
+ * target, waits for a response, checks any error code in the response,
+ * strips any message header from the response, and returns the error code
+ * (or a parsed version of it) and the response message payload.
+ *
+ * Return: the response message size if OK, -ve on error
+ */
+int misc_call(struct udevice *dev, int msgid, void *tx_msg, int tx_size,
+	      void *rx_msg, int rx_size);
+
+/**
+ * misc_set_enabled() - Enable or disable a device.
+ * @dev: the device to enable or disable.
+ * @val: the flag that tells the driver to either enable or disable the device.
+ *
+ * The semantics of "disable" and "enable" should be understood here as
+ * activating or deactivating the device's primary function, hence a "disabled"
+ * device should be dormant, but still answer to commands and queries.
+ *
+ * A probed device may start in a disabled or enabled state, depending on the
+ * driver and hardware.
+ *
+ * Return: -ve on error, 0 if the previous state was "disabled", 1 if the
+ *	   previous state was "enabled"
+ */
+int misc_set_enabled(struct udevice *dev, bool val);
+
+/*
+ * struct misc_ops - Driver model Misc operations
+ *
+ * The uclass interface is implemented by all miscellaneous devices which
+ * use driver model.
+ */
+struct misc_ops {
+	/**
+	 * Read the device to buffer, optional.
+	 * @dev: the device
+	 * @offset: offset to read the device
+	 * @buf: pointer to data buffer
+	 * @size: data size in bytes to read the device
+	 *
+	 * Return: number of bytes read if OK (may be 0 if EOF), -ve on error
+	 */
+	int (*read)(struct udevice *dev, int offset, void *buf, int size);
+
+	/**
+	 * Write buffer to the device, optional.
+	 * @dev: the device
+	 * @offset: offset to write the device
+	 * @buf: pointer to data buffer
+	 * @size: data size in bytes to write the device
+	 *
+	 * Return: number of bytes written if OK (may be < @size), -ve on error
+	 */
+	int (*write)(struct udevice *dev, int offset, const void *buf,
+		     int size);
+	/**
+	 * Assert command to the device, optional.
+	 * @dev: the device
+	 * @request: command to be sent to the device
+	 * @buf: pointer to buffer related to the request
+	 *
+	 * Return: 0 if OK, -ve on error
+	 */
+	int (*ioctl)(struct udevice *dev, unsigned long request, void *buf);
+
+	/**
+	 * Send a message to the device and wait for a response.
+	 * @dev: the device
+	 * @msgid: the message ID/number to send
+	 * @tx_msg: the request/transmit message payload
+	 * @tx_size: the size of the buffer pointed at by tx_msg
+	 * @rx_msg: the buffer to receive the response message payload. May be
+	 *          NULL if the caller only cares about the error code.
+	 * @rx_size: the size of the buffer pointed at by rx_msg
+	 *
+	 * Return: the response message size if OK, -ve on error
+	 */
+	int (*call)(struct udevice *dev, int msgid, void *tx_msg, int tx_size,
+		    void *rx_msg, int rx_size);
+	/**
+	 * Enable or disable a device, optional.
+	 * @dev: the device to enable.
+	 * @val: the flag that tells the driver to either enable or disable the
+	 *	 device.
+	 *
+	 * Return: -ve on error, 0 if the previous state was "disabled", 1 if
+	 *	   the previous state was "enabled"
+	 */
+	int (*set_enabled)(struct udevice *dev, bool val);
+};
+
+#endif	/* _MISC_H_ */
diff --git a/include/mk48t59.h b/include/mk48t59.h
new file mode 100644
index 0000000..5d863ef
--- /dev/null
+++ b/include/mk48t59.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ */
+
+/*
+ * Date & Time support for the MK48T59 RTC
+ */
+
+
+#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE)
+
+#define RTC_PORT_ADDR0		CONFIG_SYS_ISA_IO +  0x70
+#define RTC_PORT_ADDR1		RTC_PORT_ADDR0 +  0x1
+#define RTC_PORT_DATA		CONFIG_SYS_ISA_IO +  0x76
+
+/* RTC Offsets */
+#define RTC_SECONDS             0x1FF9
+#define RTC_MINUTES             0x1FFA
+#define RTC_HOURS               0x1FFB
+#define RTC_DAY_OF_WEEK         0x1FFC
+#define RTC_DAY_OF_MONTH        0x1FFD
+#define RTC_MONTH               0x1FFE
+#define RTC_YEAR                0x1FFF
+
+#define RTC_CONTROLA            0x1FF8
+#define RTC_CA_WRITE            0x80
+#define RTC_CA_READ             0x40
+#define RTC_CA_CALIB_SIGN       0x20
+#define RTC_CA_CALIB_MASK       0x1f
+
+#define RTC_CONTROLB            0x1FF9
+#define RTC_CB_STOP             0x80
+
+#define RTC_WATCHDOG			0x1FF7
+#define RTC_WDS					0x80
+#define RTC_WD_RB_16TH			0x0
+#define RTC_WD_RB_4TH			0x1
+#define RTC_WD_RB_1				0x2
+#define RTC_WD_RB_4				0x3
+
+void rtc_set_watchdog(short multi, short res);
+void *nvram_read(void *dest, const short src, size_t count);
+void nvram_write(short dest, const void *src, size_t count);
+
+#endif
diff --git a/include/mmc.h b/include/mmc.h
new file mode 100644
index 0000000..1a9efe4
--- /dev/null
+++ b/include/mmc.h
@@ -0,0 +1,882 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2008,2010 Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based (loosely) on the Linux code
+ */
+
+#ifndef _MMC_H_
+#define _MMC_H_
+
+#include <linux/list.h>
+#include <linux/sizes.h>
+#include <linux/compiler.h>
+#include <part.h>
+
+#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
+#define MMC_SUPPORTS_TUNING
+#endif
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+#define MMC_SUPPORTS_TUNING
+#endif
+
+/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
+#define SD_VERSION_SD	(1U << 31)
+#define MMC_VERSION_MMC	(1U << 30)
+
+#define MAKE_SDMMC_VERSION(a, b, c)	\
+	((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
+#define MAKE_SD_VERSION(a, b, c)	\
+	(SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
+#define MAKE_MMC_VERSION(a, b, c)	\
+	(MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
+
+#define EXTRACT_SDMMC_MAJOR_VERSION(x)	\
+	(((u32)(x) >> 16) & 0xff)
+#define EXTRACT_SDMMC_MINOR_VERSION(x)	\
+	(((u32)(x) >> 8) & 0xff)
+#define EXTRACT_SDMMC_CHANGE_VERSION(x)	\
+	((u32)(x) & 0xff)
+
+#define SD_VERSION_3		MAKE_SD_VERSION(3, 0, 0)
+#define SD_VERSION_2		MAKE_SD_VERSION(2, 0, 0)
+#define SD_VERSION_1_0		MAKE_SD_VERSION(1, 0, 0)
+#define SD_VERSION_1_10		MAKE_SD_VERSION(1, 10, 0)
+
+#define MMC_VERSION_UNKNOWN	MAKE_MMC_VERSION(0, 0, 0)
+#define MMC_VERSION_1_2		MAKE_MMC_VERSION(1, 2, 0)
+#define MMC_VERSION_1_4		MAKE_MMC_VERSION(1, 4, 0)
+#define MMC_VERSION_2_2		MAKE_MMC_VERSION(2, 2, 0)
+#define MMC_VERSION_3		MAKE_MMC_VERSION(3, 0, 0)
+#define MMC_VERSION_4		MAKE_MMC_VERSION(4, 0, 0)
+#define MMC_VERSION_4_1		MAKE_MMC_VERSION(4, 1, 0)
+#define MMC_VERSION_4_2		MAKE_MMC_VERSION(4, 2, 0)
+#define MMC_VERSION_4_3		MAKE_MMC_VERSION(4, 3, 0)
+#define MMC_VERSION_4_4		MAKE_MMC_VERSION(4, 4, 0)
+#define MMC_VERSION_4_41	MAKE_MMC_VERSION(4, 4, 1)
+#define MMC_VERSION_4_5		MAKE_MMC_VERSION(4, 5, 0)
+#define MMC_VERSION_5_0		MAKE_MMC_VERSION(5, 0, 0)
+#define MMC_VERSION_5_1		MAKE_MMC_VERSION(5, 1, 0)
+
+#define MMC_CAP(mode)		(1 << mode)
+#define MMC_MODE_HS		(MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
+#define MMC_MODE_HS_52MHz	MMC_CAP(MMC_HS_52)
+#define MMC_MODE_DDR_52MHz	MMC_CAP(MMC_DDR_52)
+#define MMC_MODE_HS200		MMC_CAP(MMC_HS_200)
+#define MMC_MODE_HS400		MMC_CAP(MMC_HS_400)
+#define MMC_MODE_HS400_ES	MMC_CAP(MMC_HS_400_ES)
+
+#define MMC_CAP_NONREMOVABLE	BIT(14)
+#define MMC_CAP_NEEDS_POLL	BIT(15)
+#define MMC_CAP_CD_ACTIVE_HIGH  BIT(16)
+
+#define MMC_MODE_8BIT		BIT(30)
+#define MMC_MODE_4BIT		BIT(29)
+#define MMC_MODE_1BIT		BIT(28)
+#define MMC_MODE_SPI		BIT(27)
+
+
+#define SD_DATA_4BIT	0x00040000
+
+#define IS_SD(x)	((x)->version & SD_VERSION_SD)
+#define IS_MMC(x)	((x)->version & MMC_VERSION_MMC)
+
+#define MMC_DATA_READ		1
+#define MMC_DATA_WRITE		2
+
+#define MMC_CMD_GO_IDLE_STATE		0
+#define MMC_CMD_SEND_OP_COND		1
+#define MMC_CMD_ALL_SEND_CID		2
+#define MMC_CMD_SET_RELATIVE_ADDR	3
+#define MMC_CMD_SET_DSR			4
+#define MMC_CMD_SWITCH			6
+#define MMC_CMD_SELECT_CARD		7
+#define MMC_CMD_SEND_EXT_CSD		8
+#define MMC_CMD_SEND_CSD		9
+#define MMC_CMD_SEND_CID		10
+#define MMC_CMD_STOP_TRANSMISSION	12
+#define MMC_CMD_SEND_STATUS		13
+#define MMC_CMD_SET_BLOCKLEN		16
+#define MMC_CMD_READ_SINGLE_BLOCK	17
+#define MMC_CMD_READ_MULTIPLE_BLOCK	18
+#define MMC_CMD_SEND_TUNING_BLOCK		19
+#define MMC_CMD_SEND_TUNING_BLOCK_HS200	21
+#define MMC_CMD_SET_BLOCK_COUNT         23
+#define MMC_CMD_WRITE_SINGLE_BLOCK	24
+#define MMC_CMD_WRITE_MULTIPLE_BLOCK	25
+#define MMC_CMD_ERASE_GROUP_START	35
+#define MMC_CMD_ERASE_GROUP_END		36
+#define MMC_CMD_ERASE			38
+#define MMC_CMD_APP_CMD			55
+#define MMC_CMD_SPI_READ_OCR		58
+#define MMC_CMD_SPI_CRC_ON_OFF		59
+#define MMC_CMD_RES_MAN			62
+
+#define MMC_CMD62_ARG1			0xefac62ec
+#define MMC_CMD62_ARG2			0xcbaea7
+
+
+#define SD_CMD_SEND_RELATIVE_ADDR	3
+#define SD_CMD_SWITCH_FUNC		6
+#define SD_CMD_SEND_IF_COND		8
+#define SD_CMD_SWITCH_UHS18V		11
+
+#define SD_CMD_APP_SET_BUS_WIDTH	6
+#define SD_CMD_APP_SD_STATUS		13
+#define SD_CMD_ERASE_WR_BLK_START	32
+#define SD_CMD_ERASE_WR_BLK_END		33
+#define SD_CMD_APP_SEND_OP_COND		41
+#define SD_CMD_APP_SEND_SCR		51
+
+static inline bool mmc_is_tuning_cmd(uint cmdidx)
+{
+	if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
+	    (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
+		return true;
+	return false;
+}
+
+/* SCR definitions in different words */
+#define SD_HIGHSPEED_BUSY	0x00020000
+#define SD_HIGHSPEED_SUPPORTED	0x00020000
+
+#define UHS_SDR12_BUS_SPEED	0
+#define HIGH_SPEED_BUS_SPEED	1
+#define UHS_SDR25_BUS_SPEED	1
+#define UHS_SDR50_BUS_SPEED	2
+#define UHS_SDR104_BUS_SPEED	3
+#define UHS_DDR50_BUS_SPEED	4
+
+#define SD_MODE_UHS_SDR12	BIT(UHS_SDR12_BUS_SPEED)
+#define SD_MODE_UHS_SDR25	BIT(UHS_SDR25_BUS_SPEED)
+#define SD_MODE_UHS_SDR50	BIT(UHS_SDR50_BUS_SPEED)
+#define SD_MODE_UHS_SDR104	BIT(UHS_SDR104_BUS_SPEED)
+#define SD_MODE_UHS_DDR50	BIT(UHS_DDR50_BUS_SPEED)
+
+#define OCR_BUSY		0x80000000
+#define OCR_HCS			0x40000000
+#define OCR_S18R		0x1000000
+#define OCR_VOLTAGE_MASK	0x007FFF80
+#define OCR_ACCESS_MODE		0x60000000
+
+#define MMC_ERASE_ARG		0x00000000
+#define MMC_SECURE_ERASE_ARG	0x80000000
+#define MMC_TRIM_ARG		0x00000001
+#define MMC_DISCARD_ARG		0x00000003
+#define MMC_SECURE_TRIM1_ARG	0x80000001
+#define MMC_SECURE_TRIM2_ARG	0x80008000
+
+#define MMC_STATUS_MASK		(~0x0206BF7F)
+#define MMC_STATUS_SWITCH_ERROR	(1 << 7)
+#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
+#define MMC_STATUS_CURR_STATE	(0xf << 9)
+#define MMC_STATUS_ERROR	(1 << 19)
+
+#define MMC_STATE_PRG		(7 << 9)
+
+#define MMC_VDD_165_195		0x00000080	/* VDD voltage 1.65 - 1.95 */
+#define MMC_VDD_20_21		0x00000100	/* VDD voltage 2.0 ~ 2.1 */
+#define MMC_VDD_21_22		0x00000200	/* VDD voltage 2.1 ~ 2.2 */
+#define MMC_VDD_22_23		0x00000400	/* VDD voltage 2.2 ~ 2.3 */
+#define MMC_VDD_23_24		0x00000800	/* VDD voltage 2.3 ~ 2.4 */
+#define MMC_VDD_24_25		0x00001000	/* VDD voltage 2.4 ~ 2.5 */
+#define MMC_VDD_25_26		0x00002000	/* VDD voltage 2.5 ~ 2.6 */
+#define MMC_VDD_26_27		0x00004000	/* VDD voltage 2.6 ~ 2.7 */
+#define MMC_VDD_27_28		0x00008000	/* VDD voltage 2.7 ~ 2.8 */
+#define MMC_VDD_28_29		0x00010000	/* VDD voltage 2.8 ~ 2.9 */
+#define MMC_VDD_29_30		0x00020000	/* VDD voltage 2.9 ~ 3.0 */
+#define MMC_VDD_30_31		0x00040000	/* VDD voltage 3.0 ~ 3.1 */
+#define MMC_VDD_31_32		0x00080000	/* VDD voltage 3.1 ~ 3.2 */
+#define MMC_VDD_32_33		0x00100000	/* VDD voltage 3.2 ~ 3.3 */
+#define MMC_VDD_33_34		0x00200000	/* VDD voltage 3.3 ~ 3.4 */
+#define MMC_VDD_34_35		0x00400000	/* VDD voltage 3.4 ~ 3.5 */
+#define MMC_VDD_35_36		0x00800000	/* VDD voltage 3.5 ~ 3.6 */
+
+#define MMC_SWITCH_MODE_CMD_SET		0x00 /* Change the command set */
+#define MMC_SWITCH_MODE_SET_BITS	0x01 /* Set bits in EXT_CSD byte
+						addressed by index which are
+						1 in value field */
+#define MMC_SWITCH_MODE_CLEAR_BITS	0x02 /* Clear bits in EXT_CSD byte
+						addressed by index, which are
+						1 in value field */
+#define MMC_SWITCH_MODE_WRITE_BYTE	0x03 /* Set target byte to value */
+
+#define SD_SWITCH_CHECK		0
+#define SD_SWITCH_SWITCH	1
+
+/*
+ * EXT_CSD fields
+ */
+#define EXT_CSD_ENH_START_ADDR		136	/* R/W */
+#define EXT_CSD_ENH_SIZE_MULT		140	/* R/W */
+#define EXT_CSD_GP_SIZE_MULT		143	/* R/W */
+#define EXT_CSD_PARTITION_SETTING	155	/* R/W */
+#define EXT_CSD_PARTITIONS_ATTRIBUTE	156	/* R/W */
+#define EXT_CSD_MAX_ENH_SIZE_MULT	157	/* R */
+#define EXT_CSD_PARTITIONING_SUPPORT	160	/* RO */
+#define EXT_CSD_RST_N_FUNCTION		162	/* R/W */
+#define EXT_CSD_BKOPS_EN		163	/* R/W & R/W/E */
+#define EXT_CSD_WR_REL_PARAM		166	/* R */
+#define EXT_CSD_WR_REL_SET		167	/* R/W */
+#define EXT_CSD_RPMB_MULT		168	/* RO */
+#define EXT_CSD_ERASE_GROUP_DEF		175	/* R/W */
+#define EXT_CSD_BOOT_BUS_WIDTH		177
+#define EXT_CSD_PART_CONF		179	/* R/W */
+#define EXT_CSD_BUS_WIDTH		183	/* R/W */
+#define EXT_CSD_STROBE_SUPPORT		184	/* R/W */
+#define EXT_CSD_HS_TIMING		185	/* R/W */
+#define EXT_CSD_REV			192	/* RO */
+#define EXT_CSD_CARD_TYPE		196	/* RO */
+#define EXT_CSD_PART_SWITCH_TIME	199	/* RO */
+#define EXT_CSD_SEC_CNT			212	/* RO, 4 bytes */
+#define EXT_CSD_HC_WP_GRP_SIZE		221	/* RO */
+#define EXT_CSD_HC_ERASE_GRP_SIZE	224	/* RO */
+#define EXT_CSD_BOOT_MULT		226	/* RO */
+#define EXT_CSD_GENERIC_CMD6_TIME       248     /* RO */
+#define EXT_CSD_BKOPS_SUPPORT		502	/* RO */
+
+/*
+ * EXT_CSD field definitions
+ */
+
+#define EXT_CSD_CMD_SET_NORMAL		(1 << 0)
+#define EXT_CSD_CMD_SET_SECURE		(1 << 1)
+#define EXT_CSD_CMD_SET_CPSECURE	(1 << 2)
+
+#define EXT_CSD_CARD_TYPE_26	(1 << 0)	/* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52	(1 << 1)	/* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V	(1 << 2)
+#define EXT_CSD_CARD_TYPE_DDR_1_2V	(1 << 3)
+#define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V \
+					| EXT_CSD_CARD_TYPE_DDR_1_2V)
+
+#define EXT_CSD_CARD_TYPE_HS200_1_8V	BIT(4)	/* Card can run at 200MHz */
+						/* SDR mode @1.8V I/O */
+#define EXT_CSD_CARD_TYPE_HS200_1_2V	BIT(5)	/* Card can run at 200MHz */
+						/* SDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_HS200		(EXT_CSD_CARD_TYPE_HS200_1_8V | \
+					 EXT_CSD_CARD_TYPE_HS200_1_2V)
+#define EXT_CSD_CARD_TYPE_HS400_1_8V	BIT(6)
+#define EXT_CSD_CARD_TYPE_HS400_1_2V	BIT(7)
+#define EXT_CSD_CARD_TYPE_HS400		(EXT_CSD_CARD_TYPE_HS400_1_8V | \
+					 EXT_CSD_CARD_TYPE_HS400_1_2V)
+
+#define EXT_CSD_BUS_WIDTH_1	0	/* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4	1	/* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8	2	/* Card is in 8 bit mode */
+#define EXT_CSD_DDR_BUS_WIDTH_4	5	/* Card is in 4 bit DDR mode */
+#define EXT_CSD_DDR_BUS_WIDTH_8	6	/* Card is in 8 bit DDR mode */
+#define EXT_CSD_DDR_FLAG	BIT(2)	/* Flag for DDR mode */
+#define EXT_CSD_BUS_WIDTH_STROBE BIT(7)	/* Enhanced strobe mode */
+
+#define EXT_CSD_TIMING_LEGACY	0	/* no high speed */
+#define EXT_CSD_TIMING_HS	1	/* HS */
+#define EXT_CSD_TIMING_HS200	2	/* HS200 */
+#define EXT_CSD_TIMING_HS400	3	/* HS400 */
+#define EXT_CSD_DRV_STR_SHIFT	4	/* Driver Strength shift */
+
+#define EXT_CSD_BOOT_ACK_ENABLE			(1 << 6)
+#define EXT_CSD_BOOT_PARTITION_ENABLE		(1 << 3)
+#define EXT_CSD_PARTITION_ACCESS_ENABLE		(1 << 0)
+#define EXT_CSD_PARTITION_ACCESS_DISABLE	(0 << 0)
+
+#define EXT_CSD_BOOT_ACK(x)		(x << 6)
+#define EXT_CSD_BOOT_PART_NUM(x)	(x << 3)
+#define EXT_CSD_PARTITION_ACCESS(x)	(x << 0)
+
+#define EXT_CSD_EXTRACT_BOOT_ACK(x)		(((x) >> 6) & 0x1)
+#define EXT_CSD_EXTRACT_BOOT_PART(x)		(((x) >> 3) & 0x7)
+#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x)	((x) & 0x7)
+
+#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)	(x << 3)
+#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x)	(x << 2)
+#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x)	(x)
+
+#define EXT_CSD_PARTITION_SETTING_COMPLETED	(1 << 0)
+
+#define EXT_CSD_ENH_USR		(1 << 0)	/* user data area is enhanced */
+#define EXT_CSD_ENH_GP(x)	(1 << ((x)+1))	/* GP part (x+1) is enhanced */
+
+#define EXT_CSD_HS_CTRL_REL	(1 << 0)	/* host controlled WR_REL_SET */
+
+#define EXT_CSD_WR_DATA_REL_USR		(1 << 0)	/* user data area WR_REL */
+#define EXT_CSD_WR_DATA_REL_GP(x)	(1 << ((x)+1))	/* GP part (x+1) WR_REL */
+
+#define R1_ILLEGAL_COMMAND		(1 << 22)
+#define R1_APP_CMD			(1 << 5)
+
+#define MMC_RSP_PRESENT (1 << 0)
+#define MMC_RSP_136	(1 << 1)		/* 136 bit response */
+#define MMC_RSP_CRC	(1 << 2)		/* expect valid crc */
+#define MMC_RSP_BUSY	(1 << 3)		/* card may send busy */
+#define MMC_RSP_OPCODE	(1 << 4)		/* response contains opcode */
+
+#define MMC_RSP_NONE	(0)
+#define MMC_RSP_R1	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R1b	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
+			MMC_RSP_BUSY)
+#define MMC_RSP_R2	(MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
+#define MMC_RSP_R3	(MMC_RSP_PRESENT)
+#define MMC_RSP_R4	(MMC_RSP_PRESENT)
+#define MMC_RSP_R5	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R6	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R7	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+
+#define MMCPART_NOAVAILABLE	(0xff)
+#define PART_ACCESS_MASK	(0x7)
+#define PART_SUPPORT		(0x1)
+#define ENHNCD_SUPPORT		(0x2)
+#define PART_ENH_ATTRIB		(0x1f)
+
+#define MMC_QUIRK_RETRY_SEND_CID	BIT(0)
+#define MMC_QUIRK_RETRY_SET_BLOCKLEN	BIT(1)
+
+enum mmc_voltage {
+	MMC_SIGNAL_VOLTAGE_000 = 0,
+	MMC_SIGNAL_VOLTAGE_120 = 1,
+	MMC_SIGNAL_VOLTAGE_180 = 2,
+	MMC_SIGNAL_VOLTAGE_330 = 4,
+};
+
+#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
+				MMC_SIGNAL_VOLTAGE_180 |\
+				MMC_SIGNAL_VOLTAGE_330)
+
+/* Maximum block size for MMC */
+#define MMC_MAX_BLOCK_LEN	512
+
+/* The number of MMC physical partitions.  These consist of:
+ * boot partitions (2), general purpose partitions (4) in MMC v4.4.
+ */
+#define MMC_NUM_BOOT_PARTITION	2
+#define MMC_PART_RPMB           3       /* RPMB partition number */
+
+/* Driver model support */
+
+/**
+ * struct mmc_uclass_priv - Holds information about a device used by the uclass
+ */
+struct mmc_uclass_priv {
+	struct mmc *mmc;
+};
+
+/**
+ * mmc_get_mmc_dev() - get the MMC struct pointer for a device
+ *
+ * Provided that the device is already probed and ready for use, this value
+ * will be available.
+ *
+ * @dev:	Device
+ * @return associated mmc struct pointer if available, else NULL
+ */
+struct mmc *mmc_get_mmc_dev(struct udevice *dev);
+
+/* End of driver model support */
+
+struct mmc_cid {
+	unsigned long psn;
+	unsigned short oid;
+	unsigned char mid;
+	unsigned char prv;
+	unsigned char mdt;
+	char pnm[7];
+};
+
+struct mmc_cmd {
+	ushort cmdidx;
+	uint resp_type;
+	uint cmdarg;
+	uint response[4];
+};
+
+struct mmc_data {
+	union {
+		char *dest;
+		const char *src; /* src buffers don't get written to */
+	};
+	uint flags;
+	uint blocks;
+	uint blocksize;
+};
+
+/* forward decl. */
+struct mmc;
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+struct dm_mmc_ops {
+	/**
+	 * send_cmd() - Send a command to the MMC device
+	 *
+	 * @dev:	Device to receive the command
+	 * @cmd:	Command to send
+	 * @data:	Additional data to send/receive
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
+			struct mmc_data *data);
+
+	/**
+	 * set_ios() - Set the I/O speed/width for an MMC device
+	 *
+	 * @dev:	Device to update
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_ios)(struct udevice *dev);
+
+	/**
+	 * get_cd() - See whether a card is present
+	 *
+	 * @dev:	Device to check
+	 * @return 0 if not present, 1 if present, -ve on error
+	 */
+	int (*get_cd)(struct udevice *dev);
+
+	/**
+	 * get_wp() - See whether a card has write-protect enabled
+	 *
+	 * @dev:	Device to check
+	 * @return 0 if write-enabled, 1 if write-protected, -ve on error
+	 */
+	int (*get_wp)(struct udevice *dev);
+
+#ifdef MMC_SUPPORTS_TUNING
+	/**
+	 * execute_tuning() - Start the tuning process
+	 *
+	 * @dev:	Device to start the tuning
+	 * @opcode:	Command opcode to send
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*execute_tuning)(struct udevice *dev, uint opcode);
+#endif
+
+	/**
+	 * wait_dat0() - wait until dat0 is in the target state
+	 *		(CLK must be running during the wait)
+	 *
+	 * @dev:	Device to check
+	 * @state:	target state
+	 * @timeout_us:	timeout in us
+	 * @return 0 if dat0 is in the target state, -ve on error
+	 */
+	int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
+
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+	/* set_enhanced_strobe() - set HS400 enhanced strobe */
+	int (*set_enhanced_strobe)(struct udevice *dev);
+#endif
+
+	/**
+	 * host_power_cycle - host specific tasks in power cycle sequence
+	 *		      Called between mmc_power_off() and
+	 *		      mmc_power_on()
+	 *
+	 * @dev:	Device to check
+	 * @return 0 if not present, 1 if present, -ve on error
+	 */
+	int (*host_power_cycle)(struct udevice *dev);
+};
+
+#define mmc_get_ops(dev)        ((struct dm_mmc_ops *)(dev)->driver->ops)
+
+int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+		    struct mmc_data *data);
+int dm_mmc_set_ios(struct udevice *dev);
+int dm_mmc_get_cd(struct udevice *dev);
+int dm_mmc_get_wp(struct udevice *dev);
+int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
+int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
+int dm_mmc_host_power_cycle(struct udevice *dev);
+
+/* Transition functions for compatibility */
+int mmc_set_ios(struct mmc *mmc);
+int mmc_getcd(struct mmc *mmc);
+int mmc_getwp(struct mmc *mmc);
+int mmc_execute_tuning(struct mmc *mmc, uint opcode);
+int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
+int mmc_set_enhanced_strobe(struct mmc *mmc);
+int mmc_host_power_cycle(struct mmc *mmc);
+
+#else
+struct mmc_ops {
+	int (*send_cmd)(struct mmc *mmc,
+			struct mmc_cmd *cmd, struct mmc_data *data);
+	int (*set_ios)(struct mmc *mmc);
+	int (*init)(struct mmc *mmc);
+	int (*getcd)(struct mmc *mmc);
+	int (*getwp)(struct mmc *mmc);
+	int (*host_power_cycle)(struct mmc *mmc);
+};
+#endif
+
+struct mmc_config {
+	const char *name;
+#if !CONFIG_IS_ENABLED(DM_MMC)
+	const struct mmc_ops *ops;
+#endif
+	uint host_caps;
+	uint voltages;
+	uint f_min;
+	uint f_max;
+	uint b_max;
+	unsigned char part_type;
+};
+
+struct sd_ssr {
+	unsigned int au;		/* In sectors */
+	unsigned int erase_timeout;	/* In milliseconds */
+	unsigned int erase_offset;	/* In milliseconds */
+};
+
+enum bus_mode {
+	MMC_LEGACY,
+	SD_LEGACY,
+	MMC_HS,
+	SD_HS,
+	MMC_HS_52,
+	MMC_DDR_52,
+	UHS_SDR12,
+	UHS_SDR25,
+	UHS_SDR50,
+	UHS_DDR50,
+	UHS_SDR104,
+	MMC_HS_200,
+	MMC_HS_400,
+	MMC_HS_400_ES,
+	MMC_MODES_END
+};
+
+const char *mmc_mode_name(enum bus_mode mode);
+void mmc_dump_capabilities(const char *text, uint caps);
+
+static inline bool mmc_is_mode_ddr(enum bus_mode mode)
+{
+	if (mode == MMC_DDR_52)
+		return true;
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+	else if (mode == UHS_DDR50)
+		return true;
+#endif
+#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+	else if (mode == MMC_HS_400)
+		return true;
+#endif
+#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
+	else if (mode == MMC_HS_400_ES)
+		return true;
+#endif
+	else
+		return false;
+}
+
+#define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
+		  MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
+		  MMC_CAP(UHS_DDR50))
+
+static inline bool supports_uhs(uint caps)
+{
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
+	return (caps & UHS_CAPS) ? true : false;
+#else
+	return false;
+#endif
+}
+
+/*
+ * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
+ * with mmc_get_mmc_dev().
+ *
+ * TODO struct mmc should be in mmc_private but it's hard to fix right now
+ */
+struct mmc {
+#if !CONFIG_IS_ENABLED(BLK)
+	struct list_head link;
+#endif
+	const struct mmc_config *cfg;	/* provided configuration */
+	uint version;
+	void *priv;
+	uint has_init;
+	int high_capacity;
+	bool clk_disable; /* true if the clock can be turned off */
+	uint bus_width;
+	uint clock;
+	enum mmc_voltage signal_voltage;
+	uint card_caps;
+	uint host_caps;
+	uint ocr;
+	uint dsr;
+	uint dsr_imp;
+	uint scr[2];
+	uint csd[4];
+	uint cid[4];
+	ushort rca;
+	u8 part_support;
+	u8 part_attr;
+	u8 wr_rel_set;
+	u8 part_config;
+	u8 gen_cmd6_time;	/* units: 10 ms */
+	u8 part_switch_time;	/* units: 10 ms */
+	uint tran_speed;
+	uint legacy_speed; /* speed for the legacy mode provided by the card */
+	uint read_bl_len;
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+	uint write_bl_len;
+	uint erase_grp_size;	/* in 512-byte sectors */
+#endif
+#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
+	uint hc_wp_grp_size;	/* in 512-byte sectors */
+#endif
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+	struct sd_ssr	ssr;	/* SD status register */
+#endif
+	u64 capacity;
+	u64 capacity_user;
+	u64 capacity_boot;
+	u64 capacity_rpmb;
+	u64 capacity_gp[4];
+#ifndef CONFIG_SPL_BUILD
+	u64 enh_user_start;
+	u64 enh_user_size;
+#endif
+#if !CONFIG_IS_ENABLED(BLK)
+	struct blk_desc block_dev;
+#endif
+	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
+	char init_in_progress;	/* 1 if we have done mmc_start_init() */
+	char preinit;		/* start init as early as possible */
+	int ddr_mode;
+#if CONFIG_IS_ENABLED(DM_MMC)
+	struct udevice *dev;	/* Device for this MMC controller */
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	struct udevice *vmmc_supply;	/* Main voltage regulator (Vcc)*/
+	struct udevice *vqmmc_supply;	/* IO voltage regulator (Vccq)*/
+#endif
+#endif
+	u8 *ext_csd;
+	u32 cardtype;		/* cardtype read from the MMC */
+	enum mmc_voltage current_voltage;
+	enum bus_mode selected_mode; /* mode currently used */
+	enum bus_mode best_mode; /* best mode is the supported mode with the
+				  * highest bandwidth. It may not always be the
+				  * operating mode due to limitations when
+				  * accessing the boot partitions
+				  */
+	u32 quirks;
+};
+
+struct mmc_hwpart_conf {
+	struct {
+		uint enh_start;	/* in 512-byte sectors */
+		uint enh_size;	/* in 512-byte sectors, if 0 no enh area */
+		unsigned wr_rel_change : 1;
+		unsigned wr_rel_set : 1;
+	} user;
+	struct {
+		uint size;	/* in 512-byte sectors */
+		unsigned enhanced : 1;
+		unsigned wr_rel_change : 1;
+		unsigned wr_rel_set : 1;
+	} gp_part[4];
+};
+
+enum mmc_hwpart_conf_mode {
+	MMC_HWPART_CONF_CHECK,
+	MMC_HWPART_CONF_SET,
+	MMC_HWPART_CONF_COMPLETE,
+};
+
+struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
+
+/**
+ * mmc_bind() - Set up a new MMC device ready for probing
+ *
+ * A child block device is bound with the IF_TYPE_MMC interface type. This
+ * allows the device to be used with CONFIG_BLK
+ *
+ * @dev:	MMC device to set up
+ * @mmc:	MMC struct
+ * @cfg:	MMC configuration
+ * @return 0 if OK, -ve on error
+ */
+int mmc_bind(struct udevice *dev, struct mmc *mmc,
+	     const struct mmc_config *cfg);
+void mmc_destroy(struct mmc *mmc);
+
+/**
+ * mmc_unbind() - Unbind a MMC device's child block device
+ *
+ * @dev:	MMC device
+ * @return 0 if OK, -ve on error
+ */
+int mmc_unbind(struct udevice *dev);
+int mmc_initialize(bd_t *bis);
+int mmc_init_device(int num);
+int mmc_init(struct mmc *mmc);
+int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
+
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+    CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+    CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+int mmc_deinit(struct mmc *mmc);
+#endif
+
+/**
+ * mmc_of_parse() - Parse the device tree to get the capabilities of the host
+ *
+ * @dev:	MMC device
+ * @cfg:	MMC configuration
+ * @return 0 if OK, -ve on error
+ */
+int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
+
+int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
+
+/**
+ * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
+ *
+ * @voltage:	The mmc_voltage to convert
+ * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
+ */
+int mmc_voltage_to_mv(enum mmc_voltage voltage);
+
+/**
+ * mmc_set_clock() - change the bus clock
+ * @mmc:	MMC struct
+ * @clock:	bus frequency in Hz
+ * @disable:	flag indicating if the clock must on or off
+ * @return 0 if OK, -ve on error
+ */
+int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
+
+#define MMC_CLK_ENABLE		false
+#define MMC_CLK_DISABLE		true
+
+struct mmc *find_mmc_device(int dev_num);
+int mmc_set_dev(int dev_num);
+void print_mmc_devices(char separator);
+
+/**
+ * get_mmc_num() - get the total MMC device number
+ *
+ * @return 0 if there is no MMC device, else the number of devices
+ */
+int get_mmc_num(void);
+int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
+int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
+		      enum mmc_hwpart_conf_mode mode);
+
+#if !CONFIG_IS_ENABLED(DM_MMC)
+int mmc_getcd(struct mmc *mmc);
+int board_mmc_getcd(struct mmc *mmc);
+int mmc_getwp(struct mmc *mmc);
+int board_mmc_getwp(struct mmc *mmc);
+#endif
+
+int mmc_set_dsr(struct mmc *mmc, u16 val);
+/* Function to change the size of boot partition and rpmb partitions */
+int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
+					unsigned long rpmbsize);
+/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
+int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
+/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
+int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
+/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
+int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
+/* Functions to read / write the RPMB partition */
+int mmc_rpmb_set_key(struct mmc *mmc, void *key);
+int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
+int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
+		  unsigned short cnt, unsigned char *key);
+int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
+		   unsigned short cnt, unsigned char *key);
+
+/**
+ * mmc_rpmb_route_frames() - route RPMB data frames
+ * @mmc		Pointer to a MMC device struct
+ * @req		Request data frames
+ * @reqlen	Length of data frames in bytes
+ * @rsp		Supplied buffer for response data frames
+ * @rsplen	Length of supplied buffer for response data frames
+ *
+ * The RPMB data frames are routed to/from some external entity, for
+ * example a Trusted Exectuion Environment in an arm TrustZone protected
+ * secure world. It's expected that it's the external entity who is in
+ * control of the RPMB key.
+ *
+ * Returns 0 on success, < 0 on error.
+ */
+int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
+			  void *rsp, unsigned long rsplen);
+
+#ifdef CONFIG_CMD_BKOPS_ENABLE
+int mmc_set_bkops_enable(struct mmc *mmc);
+#endif
+
+/**
+ * Start device initialization and return immediately; it does not block on
+ * polling OCR (operation condition register) status. Useful for checking
+ * the presence of SD/eMMC when no card detect logic is available.
+ *
+ * @param mmc	Pointer to a MMC device struct
+ * @return 0 on success, <0 on error.
+ */
+int mmc_get_op_cond(struct mmc *mmc);
+
+/**
+ * Start device initialization and return immediately; it does not block on
+ * polling OCR (operation condition register) status.  Then you should call
+ * mmc_init, which would block on polling OCR status and complete the device
+ * initializatin.
+ *
+ * @param mmc	Pointer to a MMC device struct
+ * @return 0 on success, <0 on error.
+ */
+int mmc_start_init(struct mmc *mmc);
+
+/**
+ * Set preinit flag of mmc device.
+ *
+ * This will cause the device to be pre-inited during mmc_initialize(),
+ * which may save boot time if the device is not accessed until later.
+ * Some eMMC devices take 200-300ms to init, but unfortunately they
+ * must be sent a series of commands to even get them to start preparing
+ * for operation.
+ *
+ * @param mmc		Pointer to a MMC device struct
+ * @param preinit	preinit flag value
+ */
+void mmc_set_preinit(struct mmc *mmc, int preinit);
+
+#ifdef CONFIG_MMC_SPI
+#define mmc_host_is_spi(mmc)	((mmc)->cfg->host_caps & MMC_MODE_SPI)
+#else
+#define mmc_host_is_spi(mmc)	0
+#endif
+
+void board_mmc_power_init(void);
+int board_mmc_init(bd_t *bis);
+int cpu_mmc_init(bd_t *bis);
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
+# ifdef CONFIG_SYS_MMC_ENV_PART
+extern uint mmc_get_env_part(struct mmc *mmc);
+# endif
+int mmc_get_env_dev(void);
+
+/* Minimum partition switch timeout in units of 10-milliseconds */
+#define MMC_MIN_PART_SWITCH_TIME	30 /* 300 ms */
+
+/* Set block count limit because of 16 bit register limit on some hardware*/
+#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
+#endif
+
+/**
+ * mmc_get_blk_desc() - Get the block descriptor for an MMC device
+ *
+ * @mmc:	MMC device
+ * @return block device if found, else NULL
+ */
+struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
+
+#endif /* _MMC_H_ */
diff --git a/include/mpc106.h b/include/mpc106.h
new file mode 100644
index 0000000..2157b32
--- /dev/null
+++ b/include/mpc106.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ */
+
+#ifndef _MPC106_PCI_H
+#define _MPC106_PCI_H
+
+/*
+ * Defines for the MPC106 PCI Config address and data registers followed by
+ * defines for the standard PCI device configuration header.
+ */
+#define PCIDEVID_MPC106			0x0
+
+/*
+ * MPC106 Registers
+ */
+#define	MPC106_REG			0x80000000
+
+#ifdef CONFIG_SYS_ADDRESS_MAP_A
+#define MPC106_REG_ADDR			0x80000cf8
+#define	MPC106_REG_DATA			0x80000cfc
+#define MPC106_ISA_IO_PHYS		0x80000000
+#define MPC106_ISA_IO_BUS		0x00000000
+#define MPC106_ISA_IO_SIZE		0x00800000
+#define MPC106_PCI_IO_PHYS		0x81000000
+#define MPC106_PCI_IO_BUS		0x01000000
+#define MPC106_PCI_IO_SIZE		0x3e800000
+#define MPC106_PCI_MEM_PHYS		0xc0000000
+#define MPC106_PCI_MEM_BUS		0x00000000
+#define MPC106_PCI_MEM_SIZE		0x3f000000
+#define	MPC106_PCI_MEMORY_PHYS		0x00000000
+#define	MPC106_PCI_MEMORY_BUS		0x80000000
+#define	MPC106_PCI_MEMORY_SIZE		0x80000000
+#else
+#define MPC106_REG_ADDR			0xfec00cf8
+#define	MPC106_REG_DATA			0xfee00cfc
+#define MPC106_ISA_MEM_PHYS		0xfd000000
+#define MPC106_ISA_MEM_BUS		0x00000000
+#define MPC106_ISA_MEM_SIZE		0x01000000
+#define MPC106_ISA_IO_PHYS		0xfe000000
+#define MPC106_ISA_IO_BUS		0x00000000
+#define MPC106_ISA_IO_SIZE		0x00800000
+#define MPC106_PCI_IO_PHYS		0xfe800000
+#define MPC106_PCI_IO_BUS		0x00800000
+#define MPC106_PCI_IO_SIZE		0x00400000
+#define MPC106_PCI_MEM_PHYS		0x80000000
+#define MPC106_PCI_MEM_BUS		0x80000000
+#define MPC106_PCI_MEM_SIZE		0x7d000000
+#define	MPC106_PCI_MEMORY_PHYS		0x00000000
+#define	MPC106_PCI_MEMORY_BUS		0x00000000
+#define MPC106_PCI_MEMORY_SIZE		0x40000000
+#endif
+
+#define CMD_SERR			0x0100
+#define PCI_CMD_MASTER			0x0004
+#define PCI_CMD_MEMEN			0x0002
+#define PCI_CMD_IOEN			0x0001
+
+#define PCI_STAT_NO_RSV_BITS		0xffff
+
+#define PCI_BUSNUM			0x40
+#define PCI_SUBBUSNUM			0x41
+#define PCI_DISCOUNT			0x42
+
+#define PCI_PICR1			0xA8
+#define PICR1_CF_CBA(value)		((value & 0xff) << 24)
+#define PICR1_CF_BREAD_WS(value)	((value & 0x3) << 22)
+#define PICR1_PROC_TYPE_603		0x40000
+#define PICR1_PROC_TYPE_604		0x60000
+#define PICR1_MCP_EN			0x800
+#define PICR1_CF_DPARK			0x200
+#define PICR1_CF_LOOP_SNOOP		0x10
+#define PICR1_CF_L2_COPY_BACK		0x2
+#define PICR1_CF_L2_CACHE_MASK		0x3
+#define PICR1_CF_APARK			0x8
+#define PICR1_ADDRESS_MAP		0x10000
+#define PICR1_XIO_MODE			0x80000
+#define PICR1_CF_CACHE_1G		0x200000
+
+#define PCI_PICR2			0xAC
+#define PICR2_CF_SNOOP_WS(value)	((value & 0x3) << 18)
+#define PICR2_CF_FLUSH_L2		0x10000000
+#define PICR2_CF_L2_HIT_DELAY(value)	((value & 0x3) << 9)
+#define PICR2_CF_APHASE_WS(value)	((value & 0x3) << 2)
+#define PICR2_CF_INV_MODE		0x00001000
+#define PICR2_CF_MOD_HIGH		0x00020000
+#define PICR2_CF_HIT_HIGH		0x00010000
+#define PICR2_L2_SIZE_256K		0x00000000
+#define PICR2_L2_SIZE_512K		0x00000010
+#define PICR2_L2_SIZE_1MB		0x00000020
+#define PICR2_L2_EN			0x40000000
+#define PICR2_L2_UPDATE_EN		0x80000000
+#define PICR2_CF_ADDR_ONLY_DISABLE	0x00004000
+#define PICR2_CF_FAST_CASTOUT		0x00000080
+#define PICR2_CF_WDATA			0x00000001
+#define PICR2_CF_DATA_RAM_PBURST	0x00400000
+
+/*
+ * Memory controller
+ */
+#define MPC106_MCCR1			0xF0
+#define MCCR1_TYPE_EDO			0x00020000
+#define MCCR1_BK0_9BITS			0x0
+#define MCCR1_BK0_10BITS		0x1
+#define MCCR1_BK0_11BITS		0x2
+#define MCCR1_BK0_12BITS		0x3
+#define MCCR1_BK1_9BITS			0x0
+#define MCCR1_BK1_10BITS		0x4
+#define MCCR1_BK1_11BITS		0x8
+#define MCCR1_BK1_12BITS		0xC
+#define MCCR1_BK2_9BITS			0x00
+#define MCCR1_BK2_10BITS		0x10
+#define MCCR1_BK2_11BITS		0x20
+#define MCCR1_BK2_12BITS		0x30
+#define MCCR1_BK3_9BITS			0x00
+#define MCCR1_BK3_10BITS		0x40
+#define MCCR1_BK3_11BITS		0x80
+#define MCCR1_BK3_12BITS		0xC0
+#define MCCR1_MEMGO			0x00080000
+
+#define MPC106_MCCR2			0xF4
+#define MPC106_MCCR3			0xF8
+#define MPC106_MCCR4			0xFC
+
+#define MPC106_MSAR1			0x80
+#define MPC106_EMSAR1			0x88
+#define MPC106_EMSAR2			0x8C
+#define MPC106_MEAR1			0x90
+#define MPC106_EMEAR1			0x98
+#define MPC106_EMEAR2			0x9C
+
+#define MPC106_MBER			0xA0
+#define MBER_BANK0			0x1
+#define MBER_BANK1			0x2
+#define MBER_BANK2			0x4
+#define MBER_BANK3			0x8
+
+#endif
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
new file mode 100644
index 0000000..c2a1853
--- /dev/null
+++ b/include/mpc83xx.h
@@ -0,0 +1,1590 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
+ */
+
+#ifndef __MPC83XX_H__
+#define __MPC83XX_H__
+
+#include <config.h>
+#include <asm/fsl_lbc.h>
+#if defined(CONFIG_E300)
+#include <asm/e300.h>
+#endif
+
+/*
+ * MPC83xx cpu provide RCR register to do reset thing specially
+ */
+#define MPC83xx_RESET
+
+/*
+ * System reset offset (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET		0x0100
+#define	_START_OFFSET			EXC_OFF_SYS_RESET
+
+/*
+ * IMMRBAR - Internal Memory Register Base Address
+ */
+#ifndef CONFIG_DEFAULT_IMMR
+/* Default IMMR base address */
+#define CONFIG_DEFAULT_IMMR		0xFF400000
+#endif
+/* Register offset to immr */
+#define IMMRBAR				0x0000
+#define IMMRBAR_BASE_ADDR		0xFFF00000	/* Base addr. mask */
+#define IMMRBAR_RES			~(IMMRBAR_BASE_ADDR)
+
+/*
+ * LAWBAR - Local Access Window Base Address Register
+ */
+/* Register offset to immr */
+#define LBLAWBAR0			0x0020
+#define LBLAWAR0			0x0024
+#define LBLAWBAR1			0x0028
+#define LBLAWAR1			0x002C
+#define LBLAWBAR2			0x0030
+#define LBLAWAR2			0x0034
+#define LBLAWBAR3			0x0038
+#define LBLAWAR3			0x003C
+#define LAWBAR_BAR			0xFFFFF000	/* Base addr. mask */
+
+/*
+ * SPRIDR - System Part and Revision ID Register
+ */
+#define SPRIDR_PARTID			0xFFFF0000	/* Part Id */
+#define SPRIDR_REVID			0x0000FFFF	/* Revision Id */
+
+#if defined(CONFIG_ARCH_MPC834X)
+#define REVID_MAJOR(spridr)		((spridr & 0x0000FF00) >> 8)
+#define REVID_MINOR(spridr)		(spridr & 0x000000FF)
+#else
+#define REVID_MAJOR(spridr)		((spridr & 0x000000F0) >> 4)
+#define REVID_MINOR(spridr)		(spridr & 0x0000000F)
+#endif
+
+#define PARTID_NO_E(spridr)		((spridr & 0xFFFE0000) >> 16)
+#define SPR_FAMILY(spridr)		((spridr & 0xFFF00000) >> 20)
+
+#define SPR_8308			0x8100
+#define SPR_8309			0x8110
+#define SPR_831X_FAMILY			0x80B
+#define SPR_8311			0x80B2
+#define SPR_8313			0x80B0
+#define SPR_8314			0x80B6
+#define SPR_8315			0x80B4
+#define SPR_832X_FAMILY			0x806
+#define SPR_8321			0x8066
+#define SPR_8323			0x8062
+#define SPR_834X_FAMILY			0x803
+#define SPR_8343			0x8036
+#define SPR_8347_TBGA_			0x8032
+#define SPR_8347_PBGA_			0x8034
+#define SPR_8349			0x8030
+#define SPR_836X_FAMILY			0x804
+#define SPR_8358_TBGA_			0x804A
+#define SPR_8358_PBGA_			0x804E
+#define SPR_8360			0x8048
+#define SPR_837X_FAMILY			0x80C
+#define SPR_8377			0x80C6
+#define SPR_8378			0x80C4
+#define SPR_8379			0x80C2
+
+/*
+ * SPCR - System Priority Configuration Register
+ */
+/* PCI Highest Priority Enable */
+#define SPCR_PCIHPE			0x10000000
+#define SPCR_PCIHPE_SHIFT		(31-3)
+/* PCI bridge system bus request priority */
+#define SPCR_PCIPR			0x03000000
+#define SPCR_PCIPR_SHIFT		(31-7)
+#define SPCR_OPT			0x00800000	/* Optimize */
+#define SPCR_OPT_SHIFT			(31-8)
+/* E300 PowerPC core time base unit enable */
+#define SPCR_TBEN			0x00400000
+#define SPCR_TBEN_SHIFT			(31-9)
+/* E300 PowerPC Core system bus request priority */
+#define SPCR_COREPR			0x00300000
+#define SPCR_COREPR_SHIFT		(31-11)
+
+#if defined(CONFIG_ARCH_MPC834X)
+/* SPCR bits - MPC8349 specific */
+/* TSEC1 data priority */
+#define SPCR_TSEC1DP			0x00003000
+#define SPCR_TSEC1DP_SHIFT		(31-19)
+/* TSEC1 buffer descriptor priority */
+#define SPCR_TSEC1BDP			0x00000C00
+#define SPCR_TSEC1BDP_SHIFT		(31-21)
+/* TSEC1 emergency priority */
+#define SPCR_TSEC1EP			0x00000300
+#define SPCR_TSEC1EP_SHIFT		(31-23)
+/* TSEC2 data priority */
+#define SPCR_TSEC2DP			0x00000030
+#define SPCR_TSEC2DP_SHIFT		(31-27)
+/* TSEC2 buffer descriptor priority */
+#define SPCR_TSEC2BDP			0x0000000C
+#define SPCR_TSEC2BDP_SHIFT		(31-29)
+/* TSEC2 emergency priority */
+#define SPCR_TSEC2EP			0x00000003
+#define SPCR_TSEC2EP_SHIFT		(31-31)
+
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC837X)
+/* SPCR bits - MPC8308, MPC831x and MPC837X specific */
+/* TSEC data priority */
+#define SPCR_TSECDP			0x00003000
+#define SPCR_TSECDP_SHIFT		(31-19)
+/* TSEC buffer descriptor priority */
+#define SPCR_TSECBDP			0x00000C00
+#define SPCR_TSECBDP_SHIFT		(31-21)
+/* TSEC emergency priority */
+#define SPCR_TSECEP			0x00000300
+#define SPCR_TSECEP_SHIFT		(31-23)
+#endif
+
+/* SICRL/H - System I/O Configuration Register Low/High
+ */
+#if defined(CONFIG_ARCH_MPC834X)
+/* SICRL bits - MPC8349 specific */
+#define SICRL_LDP_A			0x80000000
+#define SICRL_USB1			0x40000000
+#define SICRL_USB0			0x20000000
+#define SICRL_UART			0x0C000000
+#define SICRL_GPIO1_A			0x02000000
+#define SICRL_GPIO1_B			0x01000000
+#define SICRL_GPIO1_C			0x00800000
+#define SICRL_GPIO1_D			0x00400000
+#define SICRL_GPIO1_E			0x00200000
+#define SICRL_GPIO1_F			0x00180000
+#define SICRL_GPIO1_G			0x00040000
+#define SICRL_GPIO1_H			0x00020000
+#define SICRL_GPIO1_I			0x00010000
+#define SICRL_GPIO1_J			0x00008000
+#define SICRL_GPIO1_K			0x00004000
+#define SICRL_GPIO1_L			0x00003000
+
+/* SICRH bits - MPC8349 specific */
+#define SICRH_DDR			0x80000000
+#define SICRH_TSEC1_A			0x10000000
+#define SICRH_TSEC1_B			0x08000000
+#define SICRH_TSEC1_C			0x04000000
+#define SICRH_TSEC1_D			0x02000000
+#define SICRH_TSEC1_E			0x01000000
+#define SICRH_TSEC1_F			0x00800000
+#define SICRH_TSEC2_A			0x00400000
+#define SICRH_TSEC2_B			0x00200000
+#define SICRH_TSEC2_C			0x00100000
+#define SICRH_TSEC2_D			0x00080000
+#define SICRH_TSEC2_E			0x00040000
+#define SICRH_TSEC2_F			0x00020000
+#define SICRH_TSEC2_G			0x00010000
+#define SICRH_TSEC2_H			0x00008000
+#define SICRH_GPIO2_A			0x00004000
+#define SICRH_GPIO2_B			0x00002000
+#define SICRH_GPIO2_C			0x00001000
+#define SICRH_GPIO2_D			0x00000800
+#define SICRH_GPIO2_E			0x00000400
+#define SICRH_GPIO2_F			0x00000200
+#define SICRH_GPIO2_G			0x00000180
+#define SICRH_GPIO2_H			0x00000060
+#define SICRH_TSOBI1			0x00000002
+#define SICRH_TSOBI2			0x00000001
+
+#elif defined(CONFIG_ARCH_MPC8360)
+/* SICRL bits - MPC8360 specific */
+#define SICRL_LDP_A			0xC0000000
+#define SICRL_LCLK_1			0x10000000
+#define SICRL_LCLK_2			0x08000000
+#define SICRL_SRCID_A			0x03000000
+#define SICRL_IRQ_CKSTP_A		0x00C00000
+
+/* SICRH bits - MPC8360 specific */
+#define SICRH_DDR			0x80000000
+#define SICRH_SECONDARY_DDR		0x40000000
+#define SICRH_SDDROE			0x20000000
+#define SICRH_IRQ3			0x10000000
+#define SICRH_UC1EOBI			0x00000004
+#define SICRH_UC2E1OBI			0x00000002
+#define SICRH_UC2E2OBI			0x00000001
+
+#elif defined(CONFIG_ARCH_MPC832X)
+/* SICRL bits - MPC832x specific */
+#define SICRL_LDP_LCS_A			0x80000000
+#define SICRL_IRQ_CKS			0x20000000
+#define SICRL_PCI_MSRC			0x10000000
+#define SICRL_URT_CTPR			0x06000000
+#define SICRL_IRQ_CTPR			0x00C00000
+
+#elif defined(CONFIG_ARCH_MPC8313)
+/* SICRL bits - MPC8313 specific */
+#define SICRL_LBC			0x30000000
+#define SICRL_UART			0x0C000000
+#define SICRL_SPI_A			0x03000000
+#define SICRL_SPI_B			0x00C00000
+#define SICRL_SPI_C			0x00300000
+#define SICRL_SPI_D			0x000C0000
+#define SICRL_USBDR_11			0x00000C00
+#define SICRL_USBDR_10			0x00000800
+#define SICRL_USBDR_01			0x00000400
+#define SICRL_USBDR_00			0x00000000
+#define SICRL_ETSEC1_A			0x0000000C
+#define SICRL_ETSEC2_A			0x00000003
+
+/* SICRH bits - MPC8313 specific */
+#define SICRH_INTR_A			0x02000000
+#define SICRH_INTR_B			0x00C00000
+#define SICRH_IIC			0x00300000
+#define SICRH_ETSEC2_B			0x000C0000
+#define SICRH_ETSEC2_C			0x00030000
+#define SICRH_ETSEC2_D			0x0000C000
+#define SICRH_ETSEC2_E			0x00003000
+#define SICRH_ETSEC2_F			0x00000C00
+#define SICRH_ETSEC2_G			0x00000300
+#define SICRH_ETSEC1_B			0x00000080
+#define SICRH_ETSEC1_C			0x00000060
+#define SICRH_GTX1_DLY			0x00000008
+#define SICRH_GTX2_DLY			0x00000004
+#define SICRH_TSOBI1			0x00000002
+#define SICRH_TSOBI2			0x00000001
+
+#elif defined(CONFIG_ARCH_MPC8315)
+/* SICRL bits - MPC8315 specific */
+#define SICRL_DMA_CH0			0xc0000000
+#define SICRL_DMA_SPI			0x30000000
+#define SICRL_UART			0x0c000000
+#define SICRL_IRQ4			0x02000000
+#define SICRL_IRQ5			0x01800000
+#define SICRL_IRQ6_7			0x00400000
+#define SICRL_IIC1			0x00300000
+#define SICRL_TDM			0x000c0000
+#define SICRL_TDM_SHARED		0x00030000
+#define SICRL_PCI_A			0x0000c000
+#define SICRL_ELBC_A			0x00003000
+#define SICRL_ETSEC1_A			0x000000c0
+#define SICRL_ETSEC1_B			0x00000030
+#define SICRL_ETSEC1_C			0x0000000c
+#define SICRL_TSEXPOBI			0x00000001
+
+/* SICRH bits - MPC8315 specific */
+#define SICRH_GPIO_0			0xc0000000
+#define SICRH_GPIO_1			0x30000000
+#define SICRH_GPIO_2			0x0c000000
+#define SICRH_GPIO_3			0x03000000
+#define SICRH_GPIO_4			0x00c00000
+#define SICRH_GPIO_5			0x00300000
+#define SICRH_GPIO_6			0x000c0000
+#define SICRH_GPIO_7			0x00030000
+#define SICRH_GPIO_8			0x0000c000
+#define SICRH_GPIO_9			0x00003000
+#define SICRH_GPIO_10			0x00000c00
+#define SICRH_GPIO_11			0x00000300
+#define SICRH_ETSEC2_A			0x000000c0
+#define SICRH_TSOBI1			0x00000002
+#define SICRH_TSOBI2			0x00000001
+
+#elif defined(CONFIG_ARCH_MPC837X)
+/* SICRL bits - MPC837X specific */
+#define SICRL_USB_A			0xC0000000
+#define SICRL_USB_B			0x30000000
+#define SICRL_USB_B_SD			0x20000000
+#define SICRL_UART			0x0C000000
+#define SICRL_GPIO_A			0x02000000
+#define SICRL_GPIO_B			0x01000000
+#define SICRL_GPIO_C			0x00800000
+#define SICRL_GPIO_D			0x00400000
+#define SICRL_GPIO_E			0x00200000
+#define SICRL_GPIO_F			0x00180000
+#define SICRL_GPIO_G			0x00040000
+#define SICRL_GPIO_H			0x00020000
+#define SICRL_GPIO_I			0x00010000
+#define SICRL_GPIO_J			0x00008000
+#define SICRL_GPIO_K			0x00004000
+#define SICRL_GPIO_L			0x00003000
+#define SICRL_DMA_A			0x00000800
+#define SICRL_DMA_B			0x00000400
+#define SICRL_DMA_C			0x00000200
+#define SICRL_DMA_D			0x00000100
+#define SICRL_DMA_E			0x00000080
+#define SICRL_DMA_F			0x00000040
+#define SICRL_DMA_G			0x00000020
+#define SICRL_DMA_H			0x00000010
+#define SICRL_DMA_I			0x00000008
+#define SICRL_DMA_J			0x00000004
+#define SICRL_LDP_A			0x00000002
+#define SICRL_LDP_B			0x00000001
+
+/* SICRH bits - MPC837X specific */
+#define SICRH_DDR			0x80000000
+#define SICRH_TSEC1_A			0x10000000
+#define SICRH_TSEC1_B			0x08000000
+#define SICRH_TSEC2_A			0x00400000
+#define SICRH_TSEC2_B			0x00200000
+#define SICRH_TSEC2_C			0x00100000
+#define SICRH_TSEC2_D			0x00080000
+#define SICRH_TSEC2_E			0x00040000
+#define SICRH_TMR			0x00010000
+#define SICRH_GPIO2_A			0x00008000
+#define SICRH_GPIO2_B			0x00004000
+#define SICRH_GPIO2_C			0x00002000
+#define SICRH_GPIO2_D			0x00001000
+#define SICRH_GPIO2_E			0x00000C00
+#define SICRH_GPIO2_E_SD		0x00000800
+#define SICRH_GPIO2_F			0x00000300
+#define SICRH_GPIO2_G			0x000000C0
+#define SICRH_GPIO2_H			0x00000030
+#define SICRH_SPI			0x00000003
+#define SICRH_SPI_SD			0x00000001
+
+#elif defined(CONFIG_ARCH_MPC8308)
+/* SICRL bits - MPC8308 specific */
+#define SICRL_SPI_PF0			(0 << 28)
+#define SICRL_SPI_PF1			(1 << 28)
+#define SICRL_SPI_PF3			(3 << 28)
+#define SICRL_UART_PF0			(0 << 26)
+#define SICRL_UART_PF1			(1 << 26)
+#define SICRL_UART_PF3			(3 << 26)
+#define SICRL_IRQ_PF0			(0 << 24)
+#define SICRL_IRQ_PF1			(1 << 24)
+#define SICRL_I2C2_PF0			(0 << 20)
+#define SICRL_I2C2_PF1			(1 << 20)
+#define SICRL_ETSEC1_TX_CLK		(0 << 6)
+#define SICRL_ETSEC1_GTX_CLK125		(1 << 6)
+
+/* SICRH bits - MPC8308 specific */
+#define SICRH_ESDHC_A_SD		(0 << 30)
+#define SICRH_ESDHC_A_GTM		(1 << 30)
+#define SICRH_ESDHC_A_GPIO		(3 << 30)
+#define SICRH_ESDHC_B_SD		(0 << 28)
+#define SICRH_ESDHC_B_GTM		(1 << 28)
+#define SICRH_ESDHC_B_GPIO		(3 << 28)
+#define SICRH_ESDHC_C_SD		(0 << 26)
+#define SICRH_ESDHC_C_GTM		(1 << 26)
+#define SICRH_ESDHC_C_GPIO		(3 << 26)
+#define SICRH_GPIO_A_GPIO		(0 << 24)
+#define SICRH_GPIO_A_TSEC2		(1 << 24)
+#define SICRH_GPIO_B_GPIO		(0 << 22)
+#define SICRH_GPIO_B_TSEC2_TX_CLK	(1 << 22)
+#define SICRH_GPIO_B_TSEC2_GTX_CLK125	(2 << 22)
+#define SICRH_IEEE1588_A_TMR		(1 << 20)
+#define SICRH_IEEE1588_A_GPIO		(3 << 20)
+#define SICRH_USB			(1 << 18)
+#define SICRH_GTM_GTM			(1 << 16)
+#define SICRH_GTM_GPIO			(3 << 16)
+#define SICRH_IEEE1588_B_TMR		(1 << 14)
+#define SICRH_IEEE1588_B_GPIO		(3 << 14)
+#define SICRH_ETSEC2_CRS		(1 << 12)
+#define SICRH_ETSEC2_GPIO		(3 << 12)
+#define SICRH_GPIOSEL_0			(0 << 8)
+#define SICRH_GPIOSEL_1			(1 << 8)
+#define SICRH_TMROBI_V3P3		(0 << 4)
+#define SICRH_TMROBI_V2P5		(1 << 4)
+#define SICRH_TSOBI1_V3P3		(0 << 1)
+#define SICRH_TSOBI1_V2P5		(1 << 1)
+#define SICRH_TSOBI2_V3P3		(0 << 0)
+#define SICRH_TSOBI2_V2P5		(1 << 0)
+
+#elif defined(CONFIG_ARCH_MPC8309)
+/* SICR_1 */
+#define SICR_1_UART1_UART1S		(0 << (30-2))
+#define SICR_1_UART1_UART1RTS		(1 << (30-2))
+#define SICR_1_I2C_I2C			(0 << (30-4))
+#define SICR_1_I2C_CKSTOP		(1 << (30-4))
+#define SICR_1_IRQ_A_IRQ		(0 << (30-6))
+#define SICR_1_IRQ_A_MCP		(1 << (30-6))
+#define SICR_1_IRQ_B_IRQ		(0 << (30-8))
+#define SICR_1_IRQ_B_CKSTOP		(1 << (30-8))
+#define SICR_1_GPIO_A_GPIO		(0 << (30-10))
+#define SICR_1_GPIO_A_SD		(2 << (30-10))
+#define SICR_1_GPIO_A_DDR		(3 << (30-10))
+#define SICR_1_GPIO_B_GPIO		(0 << (30-12))
+#define SICR_1_GPIO_B_SD		(2 << (30-12))
+#define SICR_1_GPIO_B_QE		(3 << (30-12))
+#define SICR_1_GPIO_C_GPIO		(0 << (30-14))
+#define SICR_1_GPIO_C_CAN		(1 << (30-14))
+#define SICR_1_GPIO_C_DDR		(2 << (30-14))
+#define SICR_1_GPIO_C_LCS		(3 << (30-14))
+#define SICR_1_GPIO_D_GPIO		(0 << (30-16))
+#define SICR_1_GPIO_D_CAN		(1 << (30-16))
+#define SICR_1_GPIO_D_DDR		(2 << (30-16))
+#define SICR_1_GPIO_D_LCS		(3 << (30-16))
+#define SICR_1_GPIO_E_GPIO		(0 << (30-18))
+#define SICR_1_GPIO_E_CAN		(1 << (30-18))
+#define SICR_1_GPIO_E_DDR		(2 << (30-18))
+#define SICR_1_GPIO_E_LCS		(3 << (30-18))
+#define SICR_1_GPIO_F_GPIO		(0 << (30-20))
+#define SICR_1_GPIO_F_CAN		(1 << (30-20))
+#define SICR_1_GPIO_F_CK		(2 << (30-20))
+#define SICR_1_USB_A_USBDR		(0 << (30-22))
+#define SICR_1_USB_A_UART2S		(1 << (30-22))
+#define SICR_1_USB_B_USBDR		(0 << (30-24))
+#define SICR_1_USB_B_UART2S		(1 << (30-24))
+#define SICR_1_USB_B_UART2RTS		(2 << (30-24))
+#define SICR_1_USB_C_USBDR		(0 << (30-26))
+#define SICR_1_USB_C_QE_EXT		(3 << (30-26))
+#define SICR_1_FEC1_FEC1		(0 << (30-28))
+#define SICR_1_FEC1_GTM			(1 << (30-28))
+#define SICR_1_FEC1_GPIO		(2 << (30-28))
+#define SICR_1_FEC2_FEC2		(0 << (30-30))
+#define SICR_1_FEC2_GTM			(1 << (30-30))
+#define SICR_1_FEC2_GPIO		(2 << (30-30))
+/* SICR_2 */
+#define SICR_2_FEC3_FEC3		(0 << (30-0))
+#define SICR_2_FEC3_TMR			(1 << (30-0))
+#define SICR_2_FEC3_GPIO		(2 << (30-0))
+#define SICR_2_HDLC1_A_HDLC1		(0 << (30-2))
+#define SICR_2_HDLC1_A_GPIO		(1 << (30-2))
+#define SICR_2_HDLC1_A_TDM1		(2 << (30-2))
+#define SICR_2_ELBC_A_LA		(0 << (30-4))
+#define SICR_2_ELBC_B_LCLK		(0 << (30-6))
+#define SICR_2_HDLC2_A_HDLC2		(0 << (30-8))
+#define SICR_2_HDLC2_A_GPIO		(0 << (30-8))
+#define SICR_2_HDLC2_A_TDM2		(0 << (30-8))
+/* bits 10-11 unused */
+#define SICR_2_USB_D_USBDR		(0 << (30-12))
+#define SICR_2_USB_D_GPIO		(2 << (30-12))
+#define SICR_2_USB_D_QE_BRG		(3 << (30-12))
+#define SICR_2_PCI_PCI			(0 << (30-14))
+#define SICR_2_PCI_CPCI_HS		(2 << (30-14))
+#define SICR_2_HDLC1_B_HDLC1		(0 << (30-16))
+#define SICR_2_HDLC1_B_GPIO		(1 << (30-16))
+#define SICR_2_HDLC1_B_QE_BRG		(2 << (30-16))
+#define SICR_2_HDLC1_B_TDM1		(3 << (30-16))
+#define SICR_2_HDLC1_C_HDLC1		(0 << (30-18))
+#define SICR_2_HDLC1_C_GPIO		(1 << (30-18))
+#define SICR_2_HDLC1_C_TDM1		(2 << (30-18))
+#define SICR_2_HDLC2_B_HDLC2		(0 << (30-20))
+#define SICR_2_HDLC2_B_GPIO		(1 << (30-20))
+#define SICR_2_HDLC2_B_QE_BRG		(2 << (30-20))
+#define SICR_2_HDLC2_B_TDM2		(3 << (30-20))
+#define SICR_2_HDLC2_C_HDLC2		(0 << (30-22))
+#define SICR_2_HDLC2_C_GPIO		(1 << (30-22))
+#define SICR_2_HDLC2_C_TDM2		(2 << (30-22))
+#define SICR_2_HDLC2_C_QE_BRG		(3 << (30-22))
+#define SICR_2_QUIESCE_B		(0 << (30-24))
+
+#endif
+
+/*
+ * SWCRR - System Watchdog Control Register
+ */
+/* Register offset to immr */
+#define SWCRR				0x0204
+/* Software Watchdog Time Count */
+#define SWCRR_SWTC			0xFFFF0000
+/* Watchdog Enable bit */
+#define SWCRR_SWEN			0x00000004
+/* Software Watchdog Reset/Interrupt Select bit */
+#define SWCRR_SWRI			0x00000002
+/* Software Watchdog Counter Prescale bit */
+#define SWCRR_SWPR			0x00000001
+#define SWCRR_RES			(~(SWCRR_SWTC | SWCRR_SWEN | \
+						SWCRR_SWRI | SWCRR_SWPR))
+
+/*
+ * SWCNR - System Watchdog Counter Register
+ */
+/* Register offset to immr */
+#define SWCNR				0x0208
+/* Software Watchdog Count mask */
+#define SWCNR_SWCN			0x0000FFFF
+#define SWCNR_RES			~(SWCNR_SWCN)
+
+/*
+ * SWSRR - System Watchdog Service Register
+ */
+/* Register offset to immr */
+#define SWSRR				0x020E
+
+/*
+ * ACR - Arbiter Configuration Register
+ */
+#define ACR_COREDIS			0x10000000	/* Core disable */
+#define ACR_COREDIS_SHIFT		(31-7)
+#define ACR_PIPE_DEP			0x00070000	/* Pipeline depth */
+#define ACR_PIPE_DEP_SHIFT		(31-15)
+#define ACR_PCI_RPTCNT			0x00007000	/* PCI repeat count */
+#define ACR_PCI_RPTCNT_SHIFT		(31-19)
+#define ACR_RPTCNT			0x00000700	/* Repeat count */
+#define ACR_RPTCNT_SHIFT		(31-23)
+#define ACR_APARK			0x00000030	/* Address parking */
+#define ACR_APARK_SHIFT			(31-27)
+#define ACR_PARKM			0x0000000F	/* Parking master */
+#define ACR_PARKM_SHIFT			(31-31)
+
+/*
+ * ATR - Arbiter Timers Register
+ */
+#define ATR_DTO				0x00FF0000	/* Data time out */
+#define ATR_DTO_SHIFT			16
+#define ATR_ATO				0x000000FF	/* Address time out */
+#define ATR_ATO_SHIFT			0
+
+/*
+ * AER - Arbiter Event Register
+ */
+#define AER_ETEA			0x00000020	/* Transfer error */
+/* Reserved transfer type */
+#define AER_RES				0x00000010
+/* External control word transfer type */
+#define AER_ECW				0x00000008
+/* Address Only transfer type */
+#define AER_AO				0x00000004
+#define AER_DTO				0x00000002	/* Data time out */
+#define AER_ATO				0x00000001	/* Address time out */
+
+/*
+ * AEATR - Arbiter Event Address Register
+ */
+#define AEATR_EVENT			0x07000000	/* Event type */
+#define AEATR_EVENT_SHIFT		24
+#define AEATR_MSTR_ID			0x001F0000	/* Master Id */
+#define AEATR_MSTR_ID_SHIFT		16
+#define AEATR_TBST			0x00000800	/* Transfer burst */
+#define AEATR_TBST_SHIFT		11
+#define AEATR_TSIZE			0x00000700	/* Transfer Size */
+#define AEATR_TSIZE_SHIFT		8
+#define AEATR_TTYPE			0x0000001F	/* Transfer Type */
+#define AEATR_TTYPE_SHIFT		0
+
+/*
+ * HRCWL - Hard Reset Configuration Word Low
+ */
+#define HRCWL_LBIUCM			0x80000000
+#define HRCWL_LBIUCM_SHIFT		31
+#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1	0x00000000
+#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1	0x80000000
+
+#define HRCWL_DDRCM			0x40000000
+#define HRCWL_DDRCM_SHIFT		30
+#define HRCWL_DDR_TO_SCB_CLK_1X1	0x00000000
+#define HRCWL_DDR_TO_SCB_CLK_2X1	0x40000000
+
+#define HRCWL_SPMF			0x0f000000
+#define HRCWL_SPMF_SHIFT		24
+#define HRCWL_CSB_TO_CLKIN_16X1		0x00000000
+#define HRCWL_CSB_TO_CLKIN_1X1		0x01000000
+#define HRCWL_CSB_TO_CLKIN_2X1		0x02000000
+#define HRCWL_CSB_TO_CLKIN_3X1		0x03000000
+#define HRCWL_CSB_TO_CLKIN_4X1		0x04000000
+#define HRCWL_CSB_TO_CLKIN_5X1		0x05000000
+#define HRCWL_CSB_TO_CLKIN_6X1		0x06000000
+#define HRCWL_CSB_TO_CLKIN_7X1		0x07000000
+#define HRCWL_CSB_TO_CLKIN_8X1		0x08000000
+#define HRCWL_CSB_TO_CLKIN_9X1		0x09000000
+#define HRCWL_CSB_TO_CLKIN_10X1		0x0A000000
+#define HRCWL_CSB_TO_CLKIN_11X1		0x0B000000
+#define HRCWL_CSB_TO_CLKIN_12X1		0x0C000000
+#define HRCWL_CSB_TO_CLKIN_13X1		0x0D000000
+#define HRCWL_CSB_TO_CLKIN_14X1		0x0E000000
+#define HRCWL_CSB_TO_CLKIN_15X1		0x0F000000
+
+#define HRCWL_VCO_BYPASS		0x00000000
+#define HRCWL_VCO_1X2			0x00000000
+#define HRCWL_VCO_1X4			0x00200000
+#define HRCWL_VCO_1X8			0x00400000
+
+#define HRCWL_COREPLL			0x007F0000
+#define HRCWL_COREPLL_SHIFT		16
+#define HRCWL_CORE_TO_CSB_BYPASS	0x00000000
+#define HRCWL_CORE_TO_CSB_1X1		0x00020000
+#define HRCWL_CORE_TO_CSB_1_5X1		0x00030000
+#define HRCWL_CORE_TO_CSB_2X1		0x00040000
+#define HRCWL_CORE_TO_CSB_2_5X1		0x00050000
+#define HRCWL_CORE_TO_CSB_3X1		0x00060000
+
+#if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X)
+#define HRCWL_CEVCOD			0x000000C0
+#define HRCWL_CEVCOD_SHIFT		6
+#define HRCWL_CE_PLL_VCO_DIV_4		0x00000000
+#define HRCWL_CE_PLL_VCO_DIV_8		0x00000040
+#define HRCWL_CE_PLL_VCO_DIV_2		0x00000080
+
+#define HRCWL_CEPDF			0x00000020
+#define HRCWL_CEPDF_SHIFT		5
+#define HRCWL_CE_PLL_DIV_1X1		0x00000000
+#define HRCWL_CE_PLL_DIV_2X1		0x00000020
+
+#define HRCWL_CEPMF			0x0000001F
+#define HRCWL_CEPMF_SHIFT		0
+#define HRCWL_CE_TO_PLL_1X16_		0x00000000
+#define HRCWL_CE_TO_PLL_1X2		0x00000002
+#define HRCWL_CE_TO_PLL_1X3		0x00000003
+#define HRCWL_CE_TO_PLL_1X4		0x00000004
+#define HRCWL_CE_TO_PLL_1X5		0x00000005
+#define HRCWL_CE_TO_PLL_1X6		0x00000006
+#define HRCWL_CE_TO_PLL_1X7		0x00000007
+#define HRCWL_CE_TO_PLL_1X8		0x00000008
+#define HRCWL_CE_TO_PLL_1X9		0x00000009
+#define HRCWL_CE_TO_PLL_1X10		0x0000000A
+#define HRCWL_CE_TO_PLL_1X11		0x0000000B
+#define HRCWL_CE_TO_PLL_1X12		0x0000000C
+#define HRCWL_CE_TO_PLL_1X13		0x0000000D
+#define HRCWL_CE_TO_PLL_1X14		0x0000000E
+#define HRCWL_CE_TO_PLL_1X15		0x0000000F
+#define HRCWL_CE_TO_PLL_1X16		0x00000010
+#define HRCWL_CE_TO_PLL_1X17		0x00000011
+#define HRCWL_CE_TO_PLL_1X18		0x00000012
+#define HRCWL_CE_TO_PLL_1X19		0x00000013
+#define HRCWL_CE_TO_PLL_1X20		0x00000014
+#define HRCWL_CE_TO_PLL_1X21		0x00000015
+#define HRCWL_CE_TO_PLL_1X22		0x00000016
+#define HRCWL_CE_TO_PLL_1X23		0x00000017
+#define HRCWL_CE_TO_PLL_1X24		0x00000018
+#define HRCWL_CE_TO_PLL_1X25		0x00000019
+#define HRCWL_CE_TO_PLL_1X26		0x0000001A
+#define HRCWL_CE_TO_PLL_1X27		0x0000001B
+#define HRCWL_CE_TO_PLL_1X28		0x0000001C
+#define HRCWL_CE_TO_PLL_1X29		0x0000001D
+#define HRCWL_CE_TO_PLL_1X30		0x0000001E
+#define HRCWL_CE_TO_PLL_1X31		0x0000001F
+
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
+#define HRCWL_SVCOD			0x30000000
+#define HRCWL_SVCOD_SHIFT		28
+#define HRCWL_SVCOD_DIV_2		0x00000000
+#define HRCWL_SVCOD_DIV_4		0x10000000
+#define HRCWL_SVCOD_DIV_8		0x20000000
+#define HRCWL_SVCOD_DIV_1		0x30000000
+
+#elif defined(CONFIG_ARCH_MPC837X)
+#define HRCWL_SVCOD			0x30000000
+#define HRCWL_SVCOD_SHIFT		28
+#define HRCWL_SVCOD_DIV_4		0x00000000
+#define HRCWL_SVCOD_DIV_8		0x10000000
+#define HRCWL_SVCOD_DIV_2		0x20000000
+#define HRCWL_SVCOD_DIV_1		0x30000000
+#elif defined(CONFIG_ARCH_MPC8309)
+
+#define HRCWL_CEVCOD			0x000000C0
+#define HRCWL_CEVCOD_SHIFT		6
+/*
+ * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
+ * these are different than with 8360, 832x
+ */
+#define HRCWL_CE_PLL_VCO_DIV_2		0x00000000
+#define HRCWL_CE_PLL_VCO_DIV_4		0x00000040
+#define HRCWL_CE_PLL_VCO_DIV_8		0x00000080
+
+#define HRCWL_CEPDF			0x00000020
+#define HRCWL_CEPDF_SHIFT		5
+#define HRCWL_CE_PLL_DIV_1X1		0x00000000
+#define HRCWL_CE_PLL_DIV_2X1		0x00000020
+
+#define HRCWL_CEPMF			0x0000001F
+#define HRCWL_CEPMF_SHIFT		0
+#define HRCWL_CE_TO_PLL_1X16_		0x00000000
+#define HRCWL_CE_TO_PLL_1X2		0x00000002
+#define HRCWL_CE_TO_PLL_1X3		0x00000003
+#define HRCWL_CE_TO_PLL_1X4		0x00000004
+#define HRCWL_CE_TO_PLL_1X5		0x00000005
+#define HRCWL_CE_TO_PLL_1X6		0x00000006
+#define HRCWL_CE_TO_PLL_1X7		0x00000007
+#define HRCWL_CE_TO_PLL_1X8		0x00000008
+#define HRCWL_CE_TO_PLL_1X9		0x00000009
+#define HRCWL_CE_TO_PLL_1X10		0x0000000A
+#define HRCWL_CE_TO_PLL_1X11		0x0000000B
+#define HRCWL_CE_TO_PLL_1X12		0x0000000C
+#define HRCWL_CE_TO_PLL_1X13		0x0000000D
+#define HRCWL_CE_TO_PLL_1X14		0x0000000E
+#define HRCWL_CE_TO_PLL_1X15		0x0000000F
+#define HRCWL_CE_TO_PLL_1X16		0x00000010
+#define HRCWL_CE_TO_PLL_1X17		0x00000011
+#define HRCWL_CE_TO_PLL_1X18		0x00000012
+#define HRCWL_CE_TO_PLL_1X19		0x00000013
+#define HRCWL_CE_TO_PLL_1X20		0x00000014
+#define HRCWL_CE_TO_PLL_1X21		0x00000015
+#define HRCWL_CE_TO_PLL_1X22		0x00000016
+#define HRCWL_CE_TO_PLL_1X23		0x00000017
+#define HRCWL_CE_TO_PLL_1X24		0x00000018
+#define HRCWL_CE_TO_PLL_1X25		0x00000019
+#define HRCWL_CE_TO_PLL_1X26		0x0000001A
+#define HRCWL_CE_TO_PLL_1X27		0x0000001B
+#define HRCWL_CE_TO_PLL_1X28		0x0000001C
+#define HRCWL_CE_TO_PLL_1X29		0x0000001D
+#define HRCWL_CE_TO_PLL_1X30		0x0000001E
+#define HRCWL_CE_TO_PLL_1X31		0x0000001F
+
+#define HRCWL_SVCOD			0x30000000
+#define HRCWL_SVCOD_SHIFT		28
+#define HRCWL_SVCOD_DIV_2		0x00000000
+#define HRCWL_SVCOD_DIV_4		0x10000000
+#define HRCWL_SVCOD_DIV_8		0x20000000
+#define HRCWL_SVCOD_DIV_1		0x30000000
+#endif
+
+/*
+ * HRCWH - Hardware Reset Configuration Word High
+ */
+#define HRCWH_PCI_HOST			0x80000000
+#define HRCWH_PCI_HOST_SHIFT		31
+#define HRCWH_PCI_AGENT			0x00000000
+
+#if defined(CONFIG_ARCH_MPC834X)
+#define HRCWH_32_BIT_PCI		0x00000000
+#define HRCWH_64_BIT_PCI		0x40000000
+#endif
+
+#define HRCWH_PCI1_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI1_ARBITER_ENABLE	0x20000000
+
+#define HRCWH_PCI_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI_ARBITER_ENABLE	0x20000000
+
+#if defined(CONFIG_ARCH_MPC834X)
+#define HRCWH_PCI2_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI2_ARBITER_ENABLE	0x10000000
+
+#elif defined(CONFIG_ARCH_MPC8360)
+#define HRCWH_PCICKDRV_DISABLE		0x00000000
+#define HRCWH_PCICKDRV_ENABLE		0x10000000
+#endif
+
+#define HRCWH_CORE_DISABLE		0x08000000
+#define HRCWH_CORE_ENABLE		0x00000000
+
+#define HRCWH_FROM_0X00000100		0x00000000
+#define HRCWH_FROM_0XFFF00100		0x04000000
+
+#define HRCWH_BOOTSEQ_DISABLE		0x00000000
+#define HRCWH_BOOTSEQ_NORMAL		0x01000000
+#define HRCWH_BOOTSEQ_EXTENDED		0x02000000
+
+#define HRCWH_SW_WATCHDOG_DISABLE	0x00000000
+#define HRCWH_SW_WATCHDOG_ENABLE	0x00800000
+
+#define HRCWH_ROM_LOC_DDR_SDRAM		0x00000000
+#define HRCWH_ROM_LOC_PCI1		0x00100000
+#if defined(CONFIG_ARCH_MPC834X)
+#define HRCWH_ROM_LOC_PCI2		0x00200000
+#endif
+#if defined(CONFIG_ARCH_MPC837X)
+#define HRCWH_ROM_LOC_ON_CHIP_ROM	0x00300000
+#endif
+#define HRCWH_ROM_LOC_LOCAL_8BIT	0x00500000
+#define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
+#define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
+
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC837X)
+#define HRCWH_ROM_LOC_NAND_SP_8BIT	0x00100000
+#define HRCWH_ROM_LOC_NAND_SP_16BIT	0x00200000
+#define HRCWH_ROM_LOC_NAND_LP_8BIT	0x00500000
+#define HRCWH_ROM_LOC_NAND_LP_16BIT	0x00600000
+
+#define HRCWH_RL_EXT_LEGACY		0x00000000
+#define HRCWH_RL_EXT_NAND		0x00040000
+
+#define HRCWH_TSEC1M_MASK		0x0000E000
+#define HRCWH_TSEC1M_IN_MII		0x00000000
+#define HRCWH_TSEC1M_IN_RMII		0x00002000
+#define HRCWH_TSEC1M_IN_RGMII		0x00006000
+#define HRCWH_TSEC1M_IN_RTBI		0x0000A000
+#define HRCWH_TSEC1M_IN_SGMII		0x0000C000
+
+#define HRCWH_TSEC2M_MASK		0x00001C00
+#define HRCWH_TSEC2M_IN_MII		0x00000000
+#define HRCWH_TSEC2M_IN_RMII		0x00000400
+#define HRCWH_TSEC2M_IN_RGMII		0x00000C00
+#define HRCWH_TSEC2M_IN_RTBI		0x00001400
+#define HRCWH_TSEC2M_IN_SGMII		0x00001800
+#endif
+
+#if defined(CONFIG_ARCH_MPC834X)
+#define HRCWH_TSEC1M_IN_RGMII		0x00000000
+#define HRCWH_TSEC1M_IN_RTBI		0x00004000
+#define HRCWH_TSEC1M_IN_GMII		0x00008000
+#define HRCWH_TSEC1M_IN_TBI		0x0000C000
+#define HRCWH_TSEC2M_IN_RGMII		0x00000000
+#define HRCWH_TSEC2M_IN_RTBI		0x00001000
+#define HRCWH_TSEC2M_IN_GMII		0x00002000
+#define HRCWH_TSEC2M_IN_TBI		0x00003000
+#endif
+
+#if defined(CONFIG_ARCH_MPC8360)
+#define HRCWH_SECONDARY_DDR_DISABLE	0x00000000
+#define HRCWH_SECONDARY_DDR_ENABLE	0x00000010
+#endif
+
+#define HRCWH_BIG_ENDIAN		0x00000000
+#define HRCWH_LITTLE_ENDIAN		0x00000008
+
+#define HRCWH_LALE_NORMAL		0x00000000
+#define HRCWH_LALE_EARLY		0x00000004
+
+#define HRCWH_LDP_SET			0x00000000
+#define HRCWH_LDP_CLEAR			0x00000002
+
+/*
+ * RSR - Reset Status Register
+ */
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
+	defined(CONFIG_ARCH_MPC837X)
+#define RSR_RSTSRC			0xF0000000	/* Reset source */
+#define RSR_RSTSRC_SHIFT		28
+#else
+#define RSR_RSTSRC			0xE0000000	/* Reset source */
+#define RSR_RSTSRC_SHIFT		29
+#endif
+#define RSR_BSF				0x00010000	/* Boot seq. fail */
+#define RSR_BSF_SHIFT			16
+/* software soft reset */
+#define RSR_SWSR			0x00002000
+#define RSR_SWSR_SHIFT			13
+/* software hard reset */
+#define RSR_SWHR			0x00001000
+#define RSR_SWHR_SHIFT			12
+#define RSR_JHRS			0x00000200	/* jtag hreset */
+#define RSR_JHRS_SHIFT			9
+/* jtag sreset status */
+#define RSR_JSRS			0x00000100
+#define RSR_JSRS_SHIFT			8
+/* checkstop reset status */
+#define RSR_CSHR			0x00000010
+#define RSR_CSHR_SHIFT			4
+/* software watchdog reset status */
+#define RSR_SWRS			0x00000008
+#define RSR_SWRS_SHIFT			3
+/* bus monitop reset status */
+#define RSR_BMRS			0x00000004
+#define RSR_BMRS_SHIFT			2
+#define RSR_SRS				0x00000002	/* soft reset status */
+#define RSR_SRS_SHIFT			1
+#define RSR_HRS				0x00000001	/* hard reset status */
+#define RSR_HRS_SHIFT			0
+#define RSR_RES				(~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
+						RSR_SWHR | RSR_JHRS | \
+						RSR_JSRS | RSR_CSHR | \
+						RSR_SWRS | RSR_BMRS | \
+						RSR_SRS | RSR_HRS))
+/*
+ * RMR - Reset Mode Register
+ */
+/* checkstop reset enable */
+#define RMR_CSRE			0x00000001
+#define RMR_CSRE_SHIFT			0
+#define RMR_RES				~(RMR_CSRE)
+
+/*
+ * RCR - Reset Control Register
+ */
+/* software hard reset */
+#define RCR_SWHR			0x00000002
+/* software soft reset */
+#define RCR_SWSR			0x00000001
+#define RCR_RES				~(RCR_SWHR | RCR_SWSR)
+
+/*
+ * RCER - Reset Control Enable Register
+ */
+/* software hard reset */
+#define RCER_CRE			0x00000001
+#define RCER_RES			~(RCER_CRE)
+
+/*
+ * SPMR - System PLL Mode Register
+ */
+#define SPMR_LBIUCM			0x80000000
+#define SPMR_LBIUCM_SHIFT		31
+#define SPMR_DDRCM			0x40000000
+#define SPMR_DDRCM_SHIFT		30
+#define SPMR_SPMF			0x0F000000
+#define SPMR_SPMF_SHIFT		24
+#define SPMR_CKID			0x00800000
+#define SPMR_CKID_SHIFT			23
+#define SPMR_COREPLL			0x007F0000
+#define SPMR_COREPLL_SHIFT		16
+#define SPMR_CEVCOD			0x000000C0
+#define SPMR_CEVCOD_SHIFT		6
+#define SPMR_CEPDF			0x00000020
+#define SPMR_CEPDF_SHIFT		5
+#define SPMR_CEPMF			0x0000001F
+#define SPMR_CEPMF_SHIFT		0
+
+/*
+ * OCCR - Output Clock Control Register
+ */
+#define OCCR_PCICOE0			0x80000000
+#define OCCR_PCICOE1			0x40000000
+#define OCCR_PCICOE2			0x20000000
+#define OCCR_PCICOE3			0x10000000
+#define OCCR_PCICOE4			0x08000000
+#define OCCR_PCICOE5			0x04000000
+#define OCCR_PCICOE6			0x02000000
+#define OCCR_PCICOE7			0x01000000
+#define OCCR_PCICD0			0x00800000
+#define OCCR_PCICD1			0x00400000
+#define OCCR_PCICD2			0x00200000
+#define OCCR_PCICD3			0x00100000
+#define OCCR_PCICD4			0x00080000
+#define OCCR_PCICD5			0x00040000
+#define OCCR_PCICD6			0x00020000
+#define OCCR_PCICD7			0x00010000
+#define OCCR_PCI1CR			0x00000002
+#define OCCR_PCI2CR			0x00000001
+#define OCCR_PCICR			OCCR_PCI1CR
+
+/*
+ * SCCR - System Clock Control Register
+ */
+#define SCCR_ENCCM			0x03000000
+#define SCCR_ENCCM_SHIFT		24
+#define SCCR_ENCCM_0			0x00000000
+#define SCCR_ENCCM_1			0x01000000
+#define SCCR_ENCCM_2			0x02000000
+#define SCCR_ENCCM_3			0x03000000
+
+#define SCCR_PCICM			0x00010000
+#define SCCR_PCICM_SHIFT		16
+
+#if defined(CONFIG_ARCH_MPC834X)
+/* SCCR bits - MPC834X specific */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC2CM			0x30000000
+#define SCCR_TSEC2CM_SHIFT		28
+#define SCCR_TSEC2CM_0			0x00000000
+#define SCCR_TSEC2CM_1			0x10000000
+#define SCCR_TSEC2CM_2			0x20000000
+#define SCCR_TSEC2CM_3			0x30000000
+
+/* The MPH must have the same clock ratio as DR, unless its clock disabled */
+#define SCCR_USBMPHCM			0x00c00000
+#define SCCR_USBMPHCM_SHIFT		22
+#define SCCR_USBDRCM			0x00300000
+#define SCCR_USBDRCM_SHIFT		20
+#define SCCR_USBCM			0x00f00000
+#define SCCR_USBCM_SHIFT		20
+#define SCCR_USBCM_0			0x00000000
+#define SCCR_USBCM_1			0x00500000
+#define SCCR_USBCM_2			0x00A00000
+#define SCCR_USBCM_3			0x00F00000
+
+#elif defined(CONFIG_ARCH_MPC8313)
+/* TSEC1 bits are for TSEC2 as well */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC1ON			0x20000000
+#define SCCR_TSEC1ON_SHIFT		29
+#define SCCR_TSEC2ON			0x10000000
+#define SCCR_TSEC2ON_SHIFT		28
+
+#define SCCR_USBDRCM			0x00300000
+#define SCCR_USBDRCM_SHIFT		20
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00100000
+#define SCCR_USBDRCM_2			0x00200000
+#define SCCR_USBDRCM_3			0x00300000
+
+#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
+/* SCCR bits - MPC8315/MPC8308 specific */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC2CM			0x30000000
+#define SCCR_TSEC2CM_SHIFT		28
+#define SCCR_TSEC2CM_0			0x00000000
+#define SCCR_TSEC2CM_1			0x10000000
+#define SCCR_TSEC2CM_2			0x20000000
+#define SCCR_TSEC2CM_3			0x30000000
+
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+
+#define SCCR_USBDRCM			0x00c00000
+#define SCCR_USBDRCM_SHIFT		22
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00400000
+#define SCCR_USBDRCM_2			0x00800000
+#define SCCR_USBDRCM_3			0x00c00000
+
+#define SCCR_SATA1CM			0x00003000
+#define SCCR_SATA1CM_SHIFT		12
+#define SCCR_SATACM			0x00003c00
+#define SCCR_SATACM_SHIFT		10
+#define SCCR_SATACM_0			0x00000000
+#define SCCR_SATACM_1			0x00001400
+#define SCCR_SATACM_2			0x00002800
+#define SCCR_SATACM_3			0x00003c00
+
+#define SCCR_TDMCM			0x00000030
+#define SCCR_TDMCM_SHIFT		4
+#define SCCR_TDMCM_0			0x00000000
+#define SCCR_TDMCM_1			0x00000010
+#define SCCR_TDMCM_2			0x00000020
+#define SCCR_TDMCM_3			0x00000030
+
+#elif defined(CONFIG_ARCH_MPC837X)
+/* SCCR bits - MPC837X specific */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC2CM			0x30000000
+#define SCCR_TSEC2CM_SHIFT		28
+#define SCCR_TSEC2CM_0			0x00000000
+#define SCCR_TSEC2CM_1			0x10000000
+#define SCCR_TSEC2CM_2			0x20000000
+#define SCCR_TSEC2CM_3			0x30000000
+
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+
+#define SCCR_USBDRCM			0x00c00000
+#define SCCR_USBDRCM_SHIFT		22
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00400000
+#define SCCR_USBDRCM_2			0x00800000
+#define SCCR_USBDRCM_3			0x00c00000
+
+/* All of the four SATA controllers must have the same clock ratio */
+#define SCCR_SATA1CM			0x000000c0
+#define SCCR_SATA1CM_SHIFT		6
+#define SCCR_SATACM			0x000000ff
+#define SCCR_SATACM_SHIFT		0
+#define SCCR_SATACM_0			0x00000000
+#define SCCR_SATACM_1			0x00000055
+#define SCCR_SATACM_2			0x000000aa
+#define SCCR_SATACM_3			0x000000ff
+#elif defined(CONFIG_ARCH_MPC8309)
+/* SCCR bits - MPC8309 specific */
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+
+#define SCCR_USBDRCM			0x00c00000
+#define SCCR_USBDRCM_SHIFT		22
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00400000
+#define SCCR_USBDRCM_2			0x00800000
+#define SCCR_USBDRCM_3			0x00c00000
+#endif
+
+#define SCCR_PCIEXP1CM			0x00300000
+#define SCCR_PCIEXP1CM_SHIFT		20
+#define SCCR_PCIEXP1CM_0		0x00000000
+#define SCCR_PCIEXP1CM_1		0x00100000
+#define SCCR_PCIEXP1CM_2		0x00200000
+#define SCCR_PCIEXP1CM_3		0x00300000
+
+#define SCCR_PCIEXP2CM			0x000c0000
+#define SCCR_PCIEXP2CM_SHIFT		18
+#define SCCR_PCIEXP2CM_0		0x00000000
+#define SCCR_PCIEXP2CM_1		0x00040000
+#define SCCR_PCIEXP2CM_2		0x00080000
+#define SCCR_PCIEXP2CM_3		0x000c0000
+
+/*
+ * CSn_BDNS - Chip Select memory Bounds Register
+ */
+#define CSBNDS_SA			0x00FF0000
+#define CSBNDS_SA_SHIFT			8
+#define CSBNDS_EA			0x000000FF
+#define CSBNDS_EA_SHIFT			24
+
+#ifndef CONFIG_MPC83XX_SDRAM
+
+/*
+ * CSn_CONFIG - Chip Select Configuration Register
+ */
+#define CSCONFIG_EN			0x80000000
+#define CSCONFIG_AP			0x00800000
+#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X)
+#define CSCONFIG_ODT_RD_NEVER		0x00000000
+#define CSCONFIG_ODT_RD_ONLY_CURRENT	0x00100000
+#define CSCONFIG_ODT_RD_ONLY_OTHER_CS	0x00200000
+#define CSCONFIG_ODT_RD_ALL		0x00400000
+#define CSCONFIG_ODT_WR_NEVER		0x00000000
+#define CSCONFIG_ODT_WR_ONLY_CURRENT	0x00010000
+#define CSCONFIG_ODT_WR_ONLY_OTHER_CS	0x00020000
+#define CSCONFIG_ODT_WR_ALL		0x00040000
+#elif defined(CONFIG_ARCH_MPC832X)
+#define CSCONFIG_ODT_RD_CFG		0x00400000
+#define CSCONFIG_ODT_WR_CFG		0x00040000
+#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X)
+#define CSCONFIG_ODT_RD_NEVER		0x00000000
+#define CSCONFIG_ODT_RD_ONLY_CURRENT	0x00100000
+#define CSCONFIG_ODT_RD_ONLY_OTHER_CS	0x00200000
+#define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM	0x00300000
+#define CSCONFIG_ODT_RD_ALL		0x00400000
+#define CSCONFIG_ODT_WR_NEVER		0x00000000
+#define CSCONFIG_ODT_WR_ONLY_CURRENT	0x00010000
+#define CSCONFIG_ODT_WR_ONLY_OTHER_CS	0x00020000
+#define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM	0x00030000
+#define CSCONFIG_ODT_WR_ALL		0x00040000
+#endif
+#define CSCONFIG_BANK_BIT_3		0x00004000
+#define CSCONFIG_ROW_BIT		0x00000700
+#define CSCONFIG_ROW_BIT_12		0x00000000
+#define CSCONFIG_ROW_BIT_13		0x00000100
+#define CSCONFIG_ROW_BIT_14		0x00000200
+#define CSCONFIG_COL_BIT		0x00000007
+#define CSCONFIG_COL_BIT_8		0x00000000
+#define CSCONFIG_COL_BIT_9		0x00000001
+#define CSCONFIG_COL_BIT_10		0x00000002
+#define CSCONFIG_COL_BIT_11		0x00000003
+
+/*
+ * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
+ */
+#define TIMING_CFG0_RWT			0xC0000000
+#define TIMING_CFG0_RWT_SHIFT		30
+#define TIMING_CFG0_WRT			0x30000000
+#define TIMING_CFG0_WRT_SHIFT		28
+#define TIMING_CFG0_RRT			0x0C000000
+#define TIMING_CFG0_RRT_SHIFT		26
+#define TIMING_CFG0_WWT			0x03000000
+#define TIMING_CFG0_WWT_SHIFT		24
+#define TIMING_CFG0_ACT_PD_EXIT		0x00700000
+#define TIMING_CFG0_ACT_PD_EXIT_SHIFT	20
+#define TIMING_CFG0_PRE_PD_EXIT		0x00070000
+#define TIMING_CFG0_PRE_PD_EXIT_SHIFT	16
+#define TIMING_CFG0_ODT_PD_EXIT		0x00000F00
+#define TIMING_CFG0_ODT_PD_EXIT_SHIFT	8
+#define TIMING_CFG0_MRS_CYC		0x0000000F
+#define TIMING_CFG0_MRS_CYC_SHIFT	0
+
+/*
+ * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
+ */
+#define TIMING_CFG1_PRETOACT		0x70000000
+#define TIMING_CFG1_PRETOACT_SHIFT	28
+#define TIMING_CFG1_ACTTOPRE		0x0F000000
+#define TIMING_CFG1_ACTTOPRE_SHIFT	24
+#define TIMING_CFG1_ACTTORW		0x00700000
+#define TIMING_CFG1_ACTTORW_SHIFT	20
+#define TIMING_CFG1_CASLAT		0x00070000
+#define TIMING_CFG1_CASLAT_SHIFT	16
+#define TIMING_CFG1_REFREC		0x0000F000
+#define TIMING_CFG1_REFREC_SHIFT	12
+#define TIMING_CFG1_WRREC		0x00000700
+#define TIMING_CFG1_WRREC_SHIFT		8
+#define TIMING_CFG1_ACTTOACT		0x00000070
+#define TIMING_CFG1_ACTTOACT_SHIFT	4
+#define TIMING_CFG1_WRTORD		0x00000007
+#define TIMING_CFG1_WRTORD_SHIFT	0
+#define TIMING_CFG1_CASLAT_20		0x00030000	/* CAS latency = 2.0 */
+#define TIMING_CFG1_CASLAT_25		0x00040000	/* CAS latency = 2.5 */
+#define TIMING_CFG1_CASLAT_30		0x00050000	/* CAS latency = 3.0 */
+#define TIMING_CFG1_CASLAT_35		0x00060000	/* CAS latency = 3.5 */
+#define TIMING_CFG1_CASLAT_40		0x00070000	/* CAS latency = 4.0 */
+#define TIMING_CFG1_CASLAT_45		0x00080000	/* CAS latency = 4.5 */
+#define TIMING_CFG1_CASLAT_50		0x00090000	/* CAS latency = 5.0 */
+
+/*
+ * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
+ */
+#define TIMING_CFG2_CPO			0x0F800000
+#define TIMING_CFG2_CPO_SHIFT		23
+#define TIMING_CFG2_ACSM		0x00080000
+#define TIMING_CFG2_WR_DATA_DELAY	0x00001C00
+#define TIMING_CFG2_WR_DATA_DELAY_SHIFT	10
+/* default (= CASLAT + 1) */
+#define TIMING_CFG2_CPO_DEF		0x00000000
+
+#define TIMING_CFG2_ADD_LAT		0x70000000
+#define TIMING_CFG2_ADD_LAT_SHIFT	28
+#define TIMING_CFG2_WR_LAT_DELAY	0x00380000
+#define TIMING_CFG2_WR_LAT_DELAY_SHIFT	19
+#define TIMING_CFG2_RD_TO_PRE		0x0000E000
+#define TIMING_CFG2_RD_TO_PRE_SHIFT	13
+#define TIMING_CFG2_CKE_PLS		0x000001C0
+#define TIMING_CFG2_CKE_PLS_SHIFT	6
+#define TIMING_CFG2_FOUR_ACT		0x0000003F
+#define TIMING_CFG2_FOUR_ACT_SHIFT	0
+
+/*
+ * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
+ */
+#define TIMING_CFG3_EXT_REFREC		0x00070000
+#define TIMING_CFG3_EXT_REFREC_SHIFT	16
+
+/*
+ * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN		0x80000000
+#define SDRAM_CFG_SREN			0x40000000
+#define SDRAM_CFG_ECC_EN		0x20000000
+#define SDRAM_CFG_RD_EN			0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
+#define SDRAM_CFG_DYN_PWR		0x00200000
+#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
+#define SDRAM_CFG_DBW_MASK		0x00180000
+#define SDRAM_CFG_DBW_16		0x00100000
+#define SDRAM_CFG_DBW_32		0x00080000
+#else
+#define SDRAM_CFG_32_BE			0x00080000
+#endif
+#if !defined(CONFIG_ARCH_MPC8308)
+#define SDRAM_CFG_8_BE			0x00040000
+#endif
+#define SDRAM_CFG_NCAP			0x00020000
+#define SDRAM_CFG_2T_EN			0x00008000
+#define SDRAM_CFG_HSE			0x00000008
+#define SDRAM_CFG_BI			0x00000001
+
+/*
+ * DDR_SDRAM_MODE - DDR SDRAM Mode Register
+ */
+#define SDRAM_MODE_ESD			0xFFFF0000
+#define SDRAM_MODE_ESD_SHIFT		16
+#define SDRAM_MODE_SD			0x0000FFFF
+#define SDRAM_MODE_SD_SHIFT		0
+/* select extended mode reg */
+#define DDR_MODE_EXT_MODEREG		0x4000
+/* operating mode, mask */
+#define DDR_MODE_EXT_OPMODE		0x3FF8
+#define DDR_MODE_EXT_OP_NORMAL		0x0000		/* normal operation */
+/* QFC / compatibility, mask */
+#define DDR_MODE_QFC			0x0004
+/* compatible to older SDRAMs */
+#define DDR_MODE_QFC_COMP		0x0000
+/* weak drivers */
+#define DDR_MODE_WEAK			0x0002
+/* disable DLL */
+#define DDR_MODE_DLL_DIS		0x0001
+/* CAS latency, mask */
+#define DDR_MODE_CASLAT			0x0070
+#define DDR_MODE_CASLAT_15		0x0010		/* CAS latency 1.5 */
+#define DDR_MODE_CASLAT_20		0x0020		/* CAS latency 2 */
+#define DDR_MODE_CASLAT_25		0x0060		/* CAS latency 2.5 */
+#define DDR_MODE_CASLAT_30		0x0030		/* CAS latency 3 */
+/* sequential burst */
+#define DDR_MODE_BTYPE_SEQ		0x0000
+/* interleaved burst */
+#define DDR_MODE_BTYPE_ILVD		0x0008
+#define DDR_MODE_BLEN_2			0x0001		/* burst length 2 */
+#define DDR_MODE_BLEN_4			0x0002		/* burst length 4 */
+/* exact value for 7.8125us */
+#define DDR_REFINT_166MHZ_7US		1302
+/* use 256 cycles as a starting point */
+#define DDR_BSTOPRE			256
+/* select mode register */
+#define DDR_MODE_MODEREG		0x0000
+
+/*
+ * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
+ */
+#define SDRAM_INTERVAL_REFINT		0x3FFF0000
+#define SDRAM_INTERVAL_REFINT_SHIFT	16
+#define SDRAM_INTERVAL_BSTOPRE_SHIFT	0
+
+/*
+ * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
+ */
+#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025	0x01000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075	0x03000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1		0x04000000
+
+/*
+ * ECC_ERR_INJECT - Memory data path error injection mask ECC
+ */
+/* ECC Mirror Byte */
+#define ECC_ERR_INJECT_EMB		(0x80000000 >> 22)
+/* Error Injection Enable */
+#define ECC_ERR_INJECT_EIEN		(0x80000000 >> 23)
+/* ECC Erroe Injection Enable */
+#define ECC_ERR_INJECT_EEIM		(0xff000000 >> 24)
+#define ECC_ERR_INJECT_EEIM_SHIFT	0
+
+/*
+ * CAPTURE_ECC - Memory data path read capture ECC
+ */
+#define CAPTURE_ECC_ECE			(0xff000000 >> 24)
+#define CAPTURE_ECC_ECE_SHIFT		0
+
+/*
+ * ERR_DETECT - Memory error detect
+ */
+/* Multiple Memory Errors */
+#define ECC_ERROR_DETECT_MME		(0x80000000 >> 0)
+/* Multiple-Bit Error */
+#define ECC_ERROR_DETECT_MBE		(0x80000000 >> 28)
+/* Single-Bit ECC Error Pickup */
+#define ECC_ERROR_DETECT_SBE		(0x80000000 >> 29)
+/* Memory Select Error */
+#define ECC_ERROR_DETECT_MSE		(0x80000000 >> 31)
+
+/*
+ * ERR_DISABLE - Memory error disable
+ */
+/* Multiple-Bit ECC Error Disable */
+#define ECC_ERROR_DISABLE_MBED		(0x80000000 >> 28)
+/* Sinle-Bit ECC Error disable */
+#define ECC_ERROR_DISABLE_SBED		(0x80000000 >> 29)
+/* Memory Select Error Disable */
+#define ECC_ERROR_DISABLE_MSED		(0x80000000 >> 31)
+#define ECC_ERROR_ENABLE		(~(ECC_ERROR_DISABLE_MSED | \
+						ECC_ERROR_DISABLE_SBED | \
+						ECC_ERROR_DISABLE_MBED))
+
+/*
+ * ERR_INT_EN - Memory error interrupt enable
+ */
+/* Multiple-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MBEE		(0x80000000 >> 28)
+/* Single-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_SBEE		(0x80000000 >> 29)
+/* Memory Select Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MSEE		(0x80000000 >> 31)
+#define ECC_ERR_INT_DISABLE		(~(ECC_ERR_INT_EN_MBEE | \
+						ECC_ERR_INT_EN_SBEE | \
+						ECC_ERR_INT_EN_MSEE))
+
+/*
+ * CAPTURE_ATTRIBUTES - Memory error attributes capture
+ */
+/* Data Beat Num */
+#define ECC_CAPT_ATTR_BNUM		(0xe0000000 >> 1)
+#define ECC_CAPT_ATTR_BNUM_SHIFT	28
+/* Transaction Size */
+#define ECC_CAPT_ATTR_TSIZ		(0xc0000000 >> 6)
+#define ECC_CAPT_ATTR_TSIZ_FOUR_DW	0
+#define ECC_CAPT_ATTR_TSIZ_ONE_DW	1
+#define ECC_CAPT_ATTR_TSIZ_TWO_DW	2
+#define ECC_CAPT_ATTR_TSIZ_THREE_DW	3
+#define ECC_CAPT_ATTR_TSIZ_SHIFT	24
+/* Transaction Source */
+#define ECC_CAPT_ATTR_TSRC		(0xf8000000 >> 11)
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT	0x0
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF	0x2
+#define ECC_CAPT_ATTR_TSRC_TSEC1	0x4
+#define ECC_CAPT_ATTR_TSRC_TSEC2	0x5
+#define ECC_CAPT_ATTR_TSRC_USB		(0x06|0x07)
+#define ECC_CAPT_ATTR_TSRC_ENCRYPT	0x8
+#define ECC_CAPT_ATTR_TSRC_I2C		0x9
+#define ECC_CAPT_ATTR_TSRC_JTAG		0xA
+#define ECC_CAPT_ATTR_TSRC_PCI1		0xD
+#define ECC_CAPT_ATTR_TSRC_PCI2		0xE
+#define ECC_CAPT_ATTR_TSRC_DMA		0xF
+#define ECC_CAPT_ATTR_TSRC_SHIFT	16
+/* Transaction Type */
+#define ECC_CAPT_ATTR_TTYP		(0xe0000000 >> 18)
+#define ECC_CAPT_ATTR_TTYP_WRITE	0x1
+#define ECC_CAPT_ATTR_TTYP_READ		0x2
+#define ECC_CAPT_ATTR_TTYP_R_M_W	0x3
+#define ECC_CAPT_ATTR_TTYP_SHIFT	12
+#define ECC_CAPT_ATTR_VLD		(0x80000000 >> 31)	/* Valid */
+
+/*
+ * ERR_SBE - Single bit ECC memory error management
+ */
+/* Single-Bit Error Threshold 0..255 */
+#define ECC_ERROR_MAN_SBET		(0xff000000 >> 8)
+#define ECC_ERROR_MAN_SBET_SHIFT	16
+/* Single Bit Error Counter 0..255 */
+#define ECC_ERROR_MAN_SBEC		(0xff000000 >> 24)
+#define ECC_ERROR_MAN_SBEC_SHIFT	0
+
+#endif /* !CONFIG_MPC83XX_SDRAM */
+
+/*
+ * CONFIG_ADDRESS - PCI Config Address Register
+ */
+#define PCI_CONFIG_ADDRESS_EN		0x80000000
+#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
+#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
+#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
+#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
+#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
+#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
+#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
+#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
+
+/*
+ * POTAR - PCI Outbound Translation Address Register
+ */
+#define POTAR_TA_MASK			0x000fffff
+
+/*
+ * POBAR - PCI Outbound Base Address Register
+ */
+#define POBAR_BA_MASK			0x000fffff
+
+/*
+ * POCMR - PCI Outbound Comparision Mask Register
+ */
+#define POCMR_EN			0x80000000
+/* 0-memory space 1-I/O space */
+#define POCMR_IO			0x40000000
+#define POCMR_SE			0x20000000	/* streaming enable */
+#define POCMR_DST			0x10000000	/* 0-PCI1 1-PCI2 */
+#define POCMR_CM_MASK			0x000fffff
+#define POCMR_CM_4G			0x00000000
+#define POCMR_CM_2G			0x00080000
+#define POCMR_CM_1G			0x000C0000
+#define POCMR_CM_512M			0x000E0000
+#define POCMR_CM_256M			0x000F0000
+#define POCMR_CM_128M			0x000F8000
+#define POCMR_CM_64M			0x000FC000
+#define POCMR_CM_32M			0x000FE000
+#define POCMR_CM_16M			0x000FF000
+#define POCMR_CM_8M			0x000FF800
+#define POCMR_CM_4M			0x000FFC00
+#define POCMR_CM_2M			0x000FFE00
+#define POCMR_CM_1M			0x000FFF00
+#define POCMR_CM_512K			0x000FFF80
+#define POCMR_CM_256K			0x000FFFC0
+#define POCMR_CM_128K			0x000FFFE0
+#define POCMR_CM_64K			0x000FFFF0
+#define POCMR_CM_32K			0x000FFFF8
+#define POCMR_CM_16K			0x000FFFFC
+#define POCMR_CM_8K			0x000FFFFE
+#define POCMR_CM_4K			0x000FFFFF
+
+/*
+ * PITAR - PCI Inbound Translation Address Register
+ */
+#define PITAR_TA_MASK			0x000fffff
+
+/*
+ * PIBAR - PCI Inbound Base/Extended Address Register
+ */
+#define PIBAR_MASK			0xffffffff
+#define PIEBAR_EBA_MASK			0x000fffff
+
+/*
+ * PIWAR - PCI Inbound Windows Attributes Register
+ */
+#define PIWAR_EN			0x80000000
+#define PIWAR_PF			0x20000000
+#define PIWAR_RTT_MASK			0x000f0000
+#define PIWAR_RTT_NO_SNOOP		0x00040000
+#define PIWAR_RTT_SNOOP			0x00050000
+#define PIWAR_WTT_MASK			0x0000f000
+#define PIWAR_WTT_NO_SNOOP		0x00004000
+#define PIWAR_WTT_SNOOP			0x00005000
+#define PIWAR_IWS_MASK			0x0000003F
+#define PIWAR_IWS_4K			0x0000000B
+#define PIWAR_IWS_8K			0x0000000C
+#define PIWAR_IWS_16K			0x0000000D
+#define PIWAR_IWS_32K			0x0000000E
+#define PIWAR_IWS_64K			0x0000000F
+#define PIWAR_IWS_128K			0x00000010
+#define PIWAR_IWS_256K			0x00000011
+#define PIWAR_IWS_512K			0x00000012
+#define PIWAR_IWS_1M			0x00000013
+#define PIWAR_IWS_2M			0x00000014
+#define PIWAR_IWS_4M			0x00000015
+#define PIWAR_IWS_8M			0x00000016
+#define PIWAR_IWS_16M			0x00000017
+#define PIWAR_IWS_32M			0x00000018
+#define PIWAR_IWS_64M			0x00000019
+#define PIWAR_IWS_128M			0x0000001A
+#define PIWAR_IWS_256M			0x0000001B
+#define PIWAR_IWS_512M			0x0000001C
+#define PIWAR_IWS_1G			0x0000001D
+#define PIWAR_IWS_2G			0x0000001E
+
+/*
+ * PMCCR1 - PCI Configuration Register 1
+ */
+#define PMCCR1_POWER_OFF		0x00000020
+
+#ifndef CONFIG_RAM
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define DDRCDR_DHC_EN		0x80000000
+#define DDRCDR_EN		0x40000000
+#define DDRCDR_PZ		0x3C000000
+#define DDRCDR_PZ_MAXZ		0x00000000
+#define DDRCDR_PZ_HIZ		0x20000000
+#define DDRCDR_PZ_NOMZ		0x30000000
+#define DDRCDR_PZ_LOZ		0x38000000
+#define DDRCDR_PZ_MINZ		0x3C000000
+#define DDRCDR_NZ		0x3C000000
+#define DDRCDR_NZ_MAXZ		0x00000000
+#define DDRCDR_NZ_HIZ		0x02000000
+#define DDRCDR_NZ_NOMZ		0x03000000
+#define DDRCDR_NZ_LOZ		0x03800000
+#define DDRCDR_NZ_MINZ		0x03C00000
+#define DDRCDR_ODT		0x00080000
+#define DDRCDR_DDR_CFG		0x00040000
+#define DDRCDR_M_ODR		0x00000002
+#define DDRCDR_Q_DRN		0x00000001
+#endif /* !CONFIG_RAM */
+
+/*
+ * PCIE Bridge Register
+ */
+#define PEX_CSB_CTRL_OBPIOE	0x00000001
+#define PEX_CSB_CTRL_IBPIOE	0x00000002
+#define PEX_CSB_CTRL_WDMAE	0x00000004
+#define PEX_CSB_CTRL_RDMAE	0x00000008
+
+#define PEX_CSB_OBCTRL_PIOE	0x00000001
+#define PEX_CSB_OBCTRL_MEMWE	0x00000002
+#define PEX_CSB_OBCTRL_IOWE	0x00000004
+#define PEX_CSB_OBCTRL_CFGWE	0x00000008
+
+#define PEX_CSB_IBCTRL_PIOE	0x00000001
+
+#define PEX_OWAR_EN		0x00000001
+#define PEX_OWAR_TYPE_CFG	0x00000000
+#define PEX_OWAR_TYPE_IO	0x00000002
+#define PEX_OWAR_TYPE_MEM	0x00000004
+#define PEX_OWAR_RLXO		0x00000008
+#define PEX_OWAR_NANP		0x00000010
+#define PEX_OWAR_SIZE		0xFFFFF000
+
+#define PEX_IWAR_EN		0x00000001
+#define PEX_IWAR_TYPE_INT	0x00000000
+#define PEX_IWAR_TYPE_PF	0x00000004
+#define PEX_IWAR_TYPE_NO_PF	0x00000006
+#define PEX_IWAR_NSOV		0x00000008
+#define PEX_IWAR_NSNP		0x00000010
+#define PEX_IWAR_SIZE		0xFFFFF000
+#define PEX_IWAR_SIZE_1M	0x000FF000
+#define PEX_IWAR_SIZE_2M	0x001FF000
+#define PEX_IWAR_SIZE_4M	0x003FF000
+#define PEX_IWAR_SIZE_8M	0x007FF000
+#define PEX_IWAR_SIZE_16M	0x00FFF000
+#define PEX_IWAR_SIZE_32M	0x01FFF000
+#define PEX_IWAR_SIZE_64M	0x03FFF000
+#define PEX_IWAR_SIZE_128M	0x07FFF000
+#define PEX_IWAR_SIZE_256M	0x0FFFF000
+
+#define PEX_GCLK_RATIO		0x440
+
+#ifndef __ASSEMBLY__
+struct pci_region;
+void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
+void mpc83xx_pcislave_unlock(int bus);
+void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
+#endif
+
+#endif	/* __MPC83XX_H__ */
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
new file mode 100644
index 0000000..3753e47
--- /dev/null
+++ b/include/mpc85xx.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright(c) 2003 Motorola Inc.
+ */
+
+#ifndef	__MPC85xx_H__
+#define __MPC85xx_H__
+
+#if defined(CONFIG_E500)
+#include <e500.h>
+#endif
+
+/*
+ * SCCR - System Clock Control Register, 9-8
+ */
+#define SCCR_CLPD       0x00000004      /* CPM Low Power Disable */
+#define SCCR_DFBRG_MSK  0x00000003      /* Division by BRGCLK Mask */
+#define SCCR_DFBRG_SHIFT 0
+
+#define SCCR_DFBRG00    0x00000000      /* BRGCLK division by 4 */
+#define SCCR_DFBRG01    0x00000001      /* BRGCLK div by 16 (normal) */
+#define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64 */
+#define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256 */
+
+/*
+ * Define default values for some CCSR macros to make header files cleaner*
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
+CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR 		CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW 	CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
+#ifndef CONFIG_SYS_IMMR
+#define CONFIG_SYS_IMMR 		CONFIG_SYS_CCSRBAR
+#endif
+
+#endif	/* __MPC85xx_H__ */
diff --git a/include/mpc86xx.h b/include/mpc86xx.h
new file mode 100644
index 0000000..9fe4748
--- /dev/null
+++ b/include/mpc86xx.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ * Jeffrey Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ */
+
+#ifndef	__MPC86xx_H__
+#define __MPC86xx_H__
+
+#include <asm/fsl_lbc.h>
+
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset	offset */
+#define _START_OFFSET		EXC_OFF_SYS_RESET
+
+/*
+ * platform register addresses
+ */
+
+#define GUTS_SVR	(CONFIG_SYS_CCSRBAR + 0xE00A4)
+#define MCM_ABCR	(CONFIG_SYS_CCSRBAR + 0x01000)
+#define MCM_DBCR	(CONFIG_SYS_CCSRBAR + 0x01008)
+
+/*
+ * l2cr values.  Look in config_<BOARD>.h for the actual setup
+ */
+#define l2cr		 1017
+
+#define L2CR_L2E         0x80000000 /* bit 0 - enable */
+#define L2CR_L2PE        0x40000000 /* bit 1 - data parity */
+#define L2CR_L2I         0x00200000 /* bit 10 - global invalidate bit */
+#define L2CR_L2CTL       0x00100000 /* bit 11 - l2 ram control */
+#define L2CR_L2DO        0x00010000 /* bit 15 - data-only mode */
+#define L2CR_REP         0x00001000 /* bit 19 - l2 replacement alg */
+#define L2CR_HWF         0x00000800 /* bit 20 - hardware flush */
+#define L2CR_L2IP        0x00000001 /* global invalidate in progress */
+
+#define HID0_XBSEN              0x00000100
+#define HID0_HIGH_BAT_EN        0x00800000
+#define HID0_XAEN               0x00020000
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+	unsigned long freq_processor;
+	unsigned long freq_systembus;
+	unsigned long freq_localbus;
+} MPC86xx_SYS_INFO;
+
+#define l1icache_enable	icache_enable
+
+void l2cache_enable(void);
+void l1dcache_enable(void);
+
+static __inline__ unsigned long get_hid0 (void)
+{
+	unsigned long hid0;
+	asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
+	return hid0;
+}
+
+static __inline__ unsigned long get_hid1 (void)
+{
+	unsigned long hid1;
+	asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
+	return hid1;
+}
+
+static __inline__ void set_hid0 (unsigned long hid0)
+{
+	asm volatile("mtspr 1008, %0" : : "r" (hid0));
+}
+
+static __inline__ void set_hid1 (unsigned long hid1)
+{
+	asm volatile("mtspr 1009, %0" : : "r" (hid1));
+}
+
+
+static __inline__ unsigned long get_l2cr (void)
+{
+   unsigned long l2cr_val;
+   asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
+   return l2cr_val;
+}
+
+void setup_ddr_bat(phys_addr_t dram_size);
+extern void setup_bats(void);
+
+#endif  /* _ASMLANGUAGE */
+#endif	/* __MPC86xx_H__ */
diff --git a/include/mpc8xx.h b/include/mpc8xx.h
new file mode 100644
index 0000000..0e0e0cb
--- /dev/null
+++ b/include/mpc8xx.h
@@ -0,0 +1,603 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * mpc8xx.h
+ *
+ * MPC8xx specific definitions
+ */
+
+#ifndef __MPCXX_H__
+#define __MPCXX_H__
+
+
+/*-----------------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
+#define _START_OFFSET		EXC_OFF_SYS_RESET
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control Register				11-9
+ */
+#define SYPCR_SWTC	0xFFFF0000	/* Software Watchdog Timer Count	*/
+#define SYPCR_BMT	0x0000FF00	/* Bus Monitor Timing			*/
+#define SYPCR_BME	0x00000080	/* Bus Monitor Enable			*/
+#define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze		*/
+#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable		*/
+#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select	*/
+#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale		*/
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register				11-6
+ */
+#define SIUMCR_EARB	0x80000000	/* External Arbitration			*/
+#define SIUMCR_EARP0	0x00000000	/* External Arbi. Request priority 0	*/
+#define SIUMCR_EARP1	0x10000000	/* External Arbi. Request priority 1	*/
+#define SIUMCR_EARP2	0x20000000	/* External Arbi. Request priority 2	*/
+#define SIUMCR_EARP3	0x30000000	/* External Arbi. Request priority 3	*/
+#define SIUMCR_EARP4	0x40000000	/* External Arbi. Request priority 4	*/
+#define SIUMCR_EARP5	0x50000000	/* External Arbi. Request priority 5	*/
+#define SIUMCR_EARP6	0x60000000	/* External Arbi. Request priority 6	*/
+#define SIUMCR_EARP7	0x70000000	/* External Arbi. Request priority 7	*/
+#define SIUMCR_DSHW	0x00800000	/* Data Showcycles			*/
+#define SIUMCR_DBGC00	0x00000000	/* Debug pins configuration		*/
+#define SIUMCR_DBGC01	0x00200000	/* - " -				*/
+#define SIUMCR_DBGC10	0x00400000	/* - " -				*/
+#define SIUMCR_DBGC11	0x00600000	/* - " -				*/
+#define SIUMCR_DBPC00	0x00000000	/* Debug Port pins Config.		*/
+#define SIUMCR_DBPC01	0x00080000	/* - " -				*/
+#define SIUMCR_DBPC10	0x00100000	/* - " -				*/
+#define SIUMCR_DBPC11	0x00180000	/* - " -				*/
+#define SIUMCR_FRC	0x00020000	/* FRZ pin Configuration		*/
+#define SIUMCR_DLK	0x00010000	/* Debug Register Lock			*/
+#define SIUMCR_PNCS	0x00008000	/* Parity Non-mem Crtl reg		*/
+#define SIUMCR_OPAR	0x00004000	/* Odd Parity				*/
+#define SIUMCR_DPC	0x00002000	/* Data Parity pins Config.		*/
+#define SIUMCR_MPRE	0x00001000	/* Multi CPU Reserva. Enable		*/
+#define SIUMCR_MLRC00	0x00000000	/* Multi Level Reserva. Ctrl		*/
+#define SIUMCR_MLRC01	0x00000400	/* - " -				*/
+#define SIUMCR_MLRC10	0x00000800	/* - " -				*/
+#define SIUMCR_MLRC11	0x00000C00	/* - " -				*/
+#define SIUMCR_AEME	0x00000200	/* Asynchro External Master		*/
+#define SIUMCR_SEME	0x00000100	/* Synchro External Master		*/
+#define SIUMCR_BSC	0x00000080	/* Byte Select Configuration		*/
+#define SIUMCR_GB5E	0x00000040	/* GPL_B(5) Enable			*/
+#define SIUMCR_B2DD	0x00000020	/* Bank 2 Double Drive			*/
+#define SIUMCR_B3DD	0x00000010	/* Bank 3 Double Drive			*/
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control Register			11-26
+ */
+#define TBSCR_TBIRQ7	0x8000		/* Time Base Interrupt Request 7	*/
+#define TBSCR_TBIRQ6	0x4000		/* Time Base Interrupt Request 6	*/
+#define TBSCR_TBIRQ5	0x2000		/* Time Base Interrupt Request 5	*/
+#define TBSCR_TBIRQ4	0x1000		/* Time Base Interrupt Request 4	*/
+#define TBSCR_TBIRQ3	0x0800		/* Time Base Interrupt Request 3	*/
+#define TBSCR_TBIRQ2	0x0400		/* Time Base Interrupt Request 2	*/
+#define TBSCR_TBIRQ1	0x0200		/* Time Base Interrupt Request 1	*/
+#define TBSCR_TBIRQ0	0x0100		/* Time Base Interrupt Request 0	*/
+#if 0	/* already in asm/immap_8xx.h */
+#define TBSCR_REFA	0x0080		/* Reference Interrupt Status A		*/
+#define TBSCR_REFB	0x0040		/* Reference Interrupt Status B		*/
+#define TBSCR_REFAE	0x0008		/* Second Interrupt Enable A		*/
+#define TBSCR_REFBE	0x0004		/* Second Interrupt Enable B		*/
+#define TBSCR_TBF	0x0002		/* Time Base Freeze			*/
+#define TBSCR_TBE	0x0001		/* Time Base Enable			*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control Register		11-31
+ */
+#undef	PISCR_PIRQ			/* TBD					*/
+#define PISCR_PITF	0x0002		/* Periodic Interrupt Timer Freeze	*/
+#if 0	/* already in asm/immap_8xx.h */
+#define PISCR_PS	0x0080		/* Periodic interrupt Status		*/
+#define PISCR_PIE	0x0004		/* Periodic Interrupt Enable		*/
+#define PISCR_PTE	0x0001		/* Periodic Timer Enable		*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * RSR - Reset Status Register						 5-4
+ */
+#define RSR_JTRS	0x01000000	/* JTAG Reset Status		*/
+#define RSR_DBSRS	0x02000000	/* Debug Port Soft Reset Status */
+#define RSR_DBHRS	0x04000000	/* Debug Port Hard Reset Status */
+#define RSR_CSRS	0x08000000	/* Check Stop Reset Status	*/
+#define RSR_SWRS	0x10000000	/* Software Watchdog Reset Status*/
+#define RSR_LLRS	0x20000000	/* Loss-of-Lock Reset Status	*/
+#define RSR_ESRS	0x40000000	/* External Soft Reset Status	*/
+#define RSR_EHRS	0x80000000	/* External Hard Reset Status	*/
+
+#define RSR_ALLBITS	(RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS)
+
+/*-----------------------------------------------------------------------
+ * Newer chips (MPC866 family and MPC87x/88x family) have different
+ * clock distribution system. Their IMMR lower half is >= 0x0800
+ */
+#define MPC8xx_NEW_CLK 0x0800
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register			15-30
+ */
+/* Newer chips (MPC866/87x/88x et al) defines */
+#define PLPRCR_MFN_MSK	0xF8000000	/* Multiplication factor numerator bits */
+#define PLPRCR_MFN_SHIFT	27	/* Multiplication factor numerator shift*/
+#define PLPRCR_MFD_MSK	0x07C00000	/* Multiplication factor denominator bits */
+#define PLPRCR_MFD_SHIFT	22	/* Multiplication factor denominator shift*/
+#define PLPRCR_S_MSK	0x00300000	/* Multiplication factor integer bits	*/
+#define PLPRCR_S_SHIFT		20	/* Multiplication factor integer shift	*/
+#define PLPRCR_MFI_MSK	0x000F0000	/* Multiplication factor integer bits	*/
+#define PLPRCR_MFI_SHIFT	16	/* Multiplication factor integer shift	*/
+
+#define PLPRCR_PDF_MSK	0x0000001E	/* Predivision Factor bits		*/
+#define PLPRCR_PDF_SHIFT	 1	/* Predivision Factor shift value	*/
+#define PLPRCR_DBRMO	0x00000001	/* DPLL BRM Order bit			*/
+
+/* Multiplication factor + PDF bits */
+#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \
+			  PLPRCR_MFD_MSK | \
+			  PLPRCR_S_MSK	 | \
+			  PLPRCR_MFI_MSK | \
+			  PLPRCR_PDF_MSK)
+
+/* Common defines */
+#define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
+#define PLPRCR_CSRC	0x00000400	/* Clock Source				*/
+
+#define PLPRCR_CSR	0x00000080	/* CheskStop Reset value		*/
+#define PLPRCR_LOLRE	0x00000040	/* Loss Of Lock Reset Enable		*/
+#define PLPRCR_FIOPD	0x00000020	/* Force I/O Pull Down			*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register			15-27
+ */
+#define SCCR_COM00	0x00000000	/* full strength CLKOUT output buffer	*/
+#define SCCR_COM01	0x20000000	/* half strength CLKOUT output buffer	*/
+#define SCCR_COM10	0x40000000	/* reserved				*/
+#define SCCR_COM11	0x60000000	/* CLKOUT output buffer disabled	*/
+#define SCCR_TBS	0x02000000	/* Time Base Source			*/
+#define SCCR_RTDIV	0x01000000	/* RTC Clock Divide			*/
+#define SCCR_RTSEL	0x00800000	/* RTC circuit input source select	*/
+#define SCCR_CRQEN	0x00400000	/* CPM Request Enable			*/
+#define SCCR_PRQEN	0x00200000	/* Power Management Request Enable	*/
+#define SCCR_EBDF00	0x00000000	/* CLKOUT is GCLK2 / 1 (normal op.)	*/
+#define SCCR_EBDF01	0x00020000	/* CLKOUT is GCLK2 / 2			*/
+#define SCCR_EBDF10	0x00040000	/* reserved				*/
+#define SCCR_EBDF11	0x00060000	/* reserved				*/
+#define SCCR_DFSYNC00	0x00000000	/* SyncCLK division by 1 (normal op.)	*/
+#define SCCR_DFSYNC01	0x00002000	/* SyncCLK division by 4		*/
+#define SCCR_DFSYNC10	0x00004000	/* SyncCLK division by 16		*/
+#define SCCR_DFSYNC11	0x00006000	/* SyncCLK division by 64		*/
+#define SCCR_DFBRG00	0x00000000	/* BRGCLK division by 1 (normal op.)	*/
+#define SCCR_DFBRG01	0x00000800	/* BRGCLK division by 4			*/
+#define SCCR_DFBRG10	0x00001000	/* BRGCLK division by 16		*/
+#define SCCR_DFBRG11	0x00001800	/* BRGCLK division by 64		*/
+#define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
+#define SCCR_DFNL001	0x00000100	/* Division by 4	                */
+#define SCCR_DFNL010	0x00000200	/* Division by 8	                */
+#define SCCR_DFNL011	0x00000300	/* Division by 16	                */
+#define SCCR_DFNL100	0x00000400	/* Division by 32	                */
+#define SCCR_DFNL101	0x00000500	/* Division by 64	                */
+#define SCCR_DFNL110	0x00000600	/* Division by 128	                */
+#define SCCR_DFNL111	0x00000700	/* Division by 256 (maximum)		*/
+#define SCCR_DFNH000	0x00000000	/* Division by 1 (default = minimum)	*/
+#define SCCR_DFNH110	0x000000D0	/* Division by 64 (maximum)		*/
+#define SCCR_DFNH111	0x000000E0	/* reserved				*/
+#define SCCR_DFLCD000	0x00000000	/* Division by 1 (default = minimum)	*/
+#define SCCR_DFLCD001	0x00000004	/* Division by 2			*/
+#define SCCR_DFLCD010	0x00000008	/* Division by 4			*/
+#define SCCR_DFLCD011	0x0000000C	/* Division by 8			*/
+#define SCCR_DFLCD100	0x00000010	/* Division by 16			*/
+#define SCCR_DFLCD101	0x00000014	/* Division by 32			*/
+#define SCCR_DFLCD110	0x00000018	/* Division by 64 (maximum)		*/
+#define SCCR_DFLCD111	0x0000001C	/* reserved				*/
+#define SCCR_DFALCD00	0x00000000	/* Division by 1 (default = minimum)	*/
+#define SCCR_DFALCD01	0x00000001	/* Division by 3			*/
+#define SCCR_DFALCD10	0x00000002	/* Division by 5			*/
+#define SCCR_DFALCD11	0x00000003	/* Division by 7 (maximum)		*/
+
+
+/*-----------------------------------------------------------------------
+ * BR - Memory Controler: Base Register					16-9
+ */
+#define BR_BA_MSK	0xFFFF8000	/* Base Address Mask			*/
+#define BR_AT_MSK	0x00007000	/* Address Type Mask			*/
+#define BR_PS_MSK	0x00000C00	/* Port Size Mask			*/
+#define BR_PS_32	0x00000000	/* 32 bit port size			*/
+#define BR_PS_16	0x00000800	/* 16 bit port size			*/
+#define BR_PS_8		0x00000400	/*  8 bit port size			*/
+#define BR_PARE		0x00000200	/* Parity Enable			*/
+#define BR_WP		0x00000100	/* Write Protect			*/
+#define BR_MS_MSK	0x000000C0	/* Machine Select Mask			*/
+#define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select		*/
+#define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select		*/
+#define BR_MS_UPMB	0x000000C0	/* U.P.M.B Machine Select		*/
+#define BR_V		0x00000001	/* Bank Valid				*/
+
+/*-----------------------------------------------------------------------
+ * OR - Memory Controler: Option Register				16-11
+ */
+#define OR_AM_MSK	0xFFFF8000	/* Address Mask Mask			*/
+#define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask		*/
+#define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start	*/
+					/* Address Multiplex			*/
+#define OR_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask	*/
+#define OR_ACS_DIV1	0x00000000	/* CS is output at the same time	*/
+#define OR_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later	*/
+#define OR_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later	*/
+#define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
+#define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
+#define OR_BI		0x00000100	/* Burst inhibit			*/
+#define OR_SCY_MSK	0x000000F0	/* Cycle Lenght in Clocks		*/
+#define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
+#define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
+#define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
+#define OR_SCY_3_CLK	0x00000030	/* 3 clock cycles wait states		*/
+#define OR_SCY_4_CLK	0x00000040	/* 4 clock cycles wait states		*/
+#define OR_SCY_5_CLK	0x00000050	/* 5 clock cycles wait states		*/
+#define OR_SCY_6_CLK	0x00000060	/* 6 clock cycles wait states		*/
+#define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
+#define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
+#define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
+#define OR_SCY_10_CLK	0x000000A0	/* 10 clock cycles wait states		*/
+#define OR_SCY_11_CLK	0x000000B0	/* 11 clock cycles wait states		*/
+#define OR_SCY_12_CLK	0x000000C0	/* 12 clock cycles wait states		*/
+#define OR_SCY_13_CLK	0x000000D0	/* 13 clock cycles wait states		*/
+#define OR_SCY_14_CLK	0x000000E0	/* 14 clock cycles wait states		*/
+#define OR_SCY_15_CLK	0x000000F0	/* 15 clock cycles wait states		*/
+#define OR_SETA		0x00000008	/* External Transfer Acknowledge	*/
+#define OR_TRLX		0x00000004	/* Timing Relaxed			*/
+#define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/
+
+
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Periodic Timer Prescaler Register			16-17
+ */
+#define MPTPR_PTP_MSK	0xFF00		/* Periodic Timers Prescaler Mask	*/
+#define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2			*/
+#define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4			*/
+#define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8			*/
+#define MPTPR_PTP_DIV16 0x0400		/* BRGCLK divided by 16			*/
+#define MPTPR_PTP_DIV32 0x0200		/* BRGCLK divided by 32			*/
+#define MPTPR_PTP_DIV64 0x0100		/* BRGCLK divided by 64			*/
+
+/*-----------------------------------------------------------------------
+ * MCR - Memory Command Register
+ */
+#define MCR_OP_WRITE	0x00000000	/* WRITE command			*/
+#define MCR_OP_READ	0x40000000	/* READ	 command			*/
+#define MCR_OP_RUN	0x80000000	/* RUN	 command			*/
+#define MCR_UPM_A	0x00000000	/* Select UPM A				*/
+#define MCR_UPM_B	0x00800000	/* Select UPM B				*/
+#define MCR_MB_CS0	0x00000000	/* Use Chip Select /CS0			*/
+#define MCR_MB_CS1	0x00002000	/* Use Chip Select /CS1			*/
+#define MCR_MB_CS2	0x00004000	/* Use Chip Select /CS2			*/
+#define MCR_MB_CS3	0x00006000	/* Use Chip Select /CS3			*/
+#define MCR_MB_CS4	0x00008000	/* Use Chip Select /CS4			*/
+#define MCR_MB_CS5	0x0000A000	/* Use Chip Select /CS5			*/
+#define MCR_MB_CS6	0x0000C000	/* Use Chip Select /CS6			*/
+#define MCR_MB_CS7	0x0000E000	/* Use Chip Select /CS7			*/
+#define MCR_MLCF(n)	(((n)&0xF)<<8)	/* Memory Command Loop Count Field	*/
+#define MCR_MAD(addr)	((addr)&0x3F)	/* Memory Array Index			*/
+
+/*-----------------------------------------------------------------------
+ * Machine A Mode Register						16-13
+ */
+#define MAMR_PTA_MSK	0xFF000000	/* Periodic Timer A period mask		*/
+#define MAMR_PTA_SHIFT	0x00000018	/* Periodic Timer A period shift	*/
+#define MAMR_PTAE	0x00800000	/* Periodic Timer A Enable		*/
+#define MAMR_AMA_MSK	0x00700000	/* Addess Multiplexing size A		*/
+#define MAMR_AMA_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
+#define MAMR_AMA_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
+#define MAMR_AMA_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
+#define MAMR_AMA_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
+#define MAMR_AMA_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
+#define MAMR_AMA_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
+#define MAMR_DSA_MSK	0x00060000	/* Disable Timer period mask		*/
+#define MAMR_DSA_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
+#define MAMR_DSA_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
+#define MAMR_DSA_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
+#define MAMR_DSA_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
+#define MAMR_G0CLA_MSK	0x0000E000	/* General Line 0 Control A		*/
+#define MAMR_G0CLA_A12	0x00000000	/* General Line 0 : A12			*/
+#define MAMR_G0CLA_A11	0x00002000	/* General Line 0 : A11			*/
+#define MAMR_G0CLA_A10	0x00004000	/* General Line 0 : A10			*/
+#define MAMR_G0CLA_A9	0x00006000	/* General Line 0 : A9			*/
+#define MAMR_G0CLA_A8	0x00008000	/* General Line 0 : A8			*/
+#define MAMR_G0CLA_A7	0x0000A000	/* General Line 0 : A7			*/
+#define MAMR_G0CLA_A6	0x0000C000	/* General Line 0 : A6			*/
+#define MAMR_G0CLA_A5	0x0000E000	/* General Line 0 : A5			*/
+#define MAMR_GPL_A4DIS	0x00001000	/* GPL_A4 ouput line Disable		*/
+#define MAMR_RLFA_MSK	0x00000F00	/* Read Loop Field A mask		*/
+#define MAMR_RLFA_1X	0x00000100	/* The Read Loop is executed 1 time	*/
+#define MAMR_RLFA_2X	0x00000200	/* The Read Loop is executed 2 times	*/
+#define MAMR_RLFA_3X	0x00000300	/* The Read Loop is executed 3 times	*/
+#define MAMR_RLFA_4X	0x00000400	/* The Read Loop is executed 4 times	*/
+#define MAMR_RLFA_5X	0x00000500	/* The Read Loop is executed 5 times	*/
+#define MAMR_RLFA_6X	0x00000600	/* The Read Loop is executed 6 times	*/
+#define MAMR_RLFA_7X	0x00000700	/* The Read Loop is executed 7 times	*/
+#define MAMR_RLFA_8X	0x00000800	/* The Read Loop is executed 8 times	*/
+#define MAMR_RLFA_9X	0x00000900	/* The Read Loop is executed 9 times	*/
+#define MAMR_RLFA_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
+#define MAMR_RLFA_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
+#define MAMR_RLFA_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
+#define MAMR_RLFA_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
+#define MAMR_RLFA_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
+#define MAMR_RLFA_15X	0x00000F00	/* The Read Loop is executed 15 times	*/
+#define MAMR_RLFA_16X	0x00000000	/* The Read Loop is executed 16 times	*/
+#define MAMR_WLFA_MSK	0x000000F0	/* Write Loop Field A mask		*/
+#define MAMR_WLFA_1X	0x00000010	/* The Write Loop is executed 1 time	*/
+#define MAMR_WLFA_2X	0x00000020	/* The Write Loop is executed 2 times	*/
+#define MAMR_WLFA_3X	0x00000030	/* The Write Loop is executed 3 times	*/
+#define MAMR_WLFA_4X	0x00000040	/* The Write Loop is executed 4 times	*/
+#define MAMR_WLFA_5X	0x00000050	/* The Write Loop is executed 5 times	*/
+#define MAMR_WLFA_6X	0x00000060	/* The Write Loop is executed 6 times	*/
+#define MAMR_WLFA_7X	0x00000070	/* The Write Loop is executed 7 times	*/
+#define MAMR_WLFA_8X	0x00000080	/* The Write Loop is executed 8 times	*/
+#define MAMR_WLFA_9X	0x00000090	/* The Write Loop is executed 9 times	*/
+#define MAMR_WLFA_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
+#define MAMR_WLFA_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
+#define MAMR_WLFA_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
+#define MAMR_WLFA_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
+#define MAMR_WLFA_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
+#define MAMR_WLFA_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
+#define MAMR_WLFA_16X	0x00000000	/* The Write Loop is executed 16 times	*/
+#define MAMR_TLFA_MSK	0x0000000F	/* Timer Loop Field A mask		*/
+#define MAMR_TLFA_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
+#define MAMR_TLFA_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
+#define MAMR_TLFA_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
+#define MAMR_TLFA_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
+#define MAMR_TLFA_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
+#define MAMR_TLFA_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
+#define MAMR_TLFA_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
+#define MAMR_TLFA_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
+#define MAMR_TLFA_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
+#define MAMR_TLFA_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
+#define MAMR_TLFA_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
+#define MAMR_TLFA_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
+#define MAMR_TLFA_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
+#define MAMR_TLFA_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
+#define MAMR_TLFA_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
+#define MAMR_TLFA_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
+
+/*-----------------------------------------------------------------------
+ * Machine B Mode Register						16-13
+ */
+#define MBMR_PTB_MSK	0xFF000000	/* Periodic Timer B period mask		*/
+#define MBMR_PTB_SHIFT	0x00000018	/* Periodic Timer B period shift	*/
+#define MBMR_PTBE	0x00800000	/* Periodic Timer B Enable		*/
+#define MBMR_AMB_MSK	0x00700000	/* Addess Multiplex size B		*/
+#define MBMR_AMB_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
+#define MBMR_AMB_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
+#define MBMR_AMB_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
+#define MBMR_AMB_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
+#define MBMR_AMB_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
+#define MBMR_AMB_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
+#define MBMR_DSB_MSK	0x00060000	/* Disable Timer period mask		*/
+#define MBMR_DSB_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
+#define MBMR_DSB_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
+#define MBMR_DSB_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
+#define MBMR_DSB_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
+#define MBMR_G0CLB_MSK	0x0000E000	/* General Line 0 Control B		*/
+#define MBMR_G0CLB_A12	0x00000000	/* General Line 0 : A12			*/
+#define MBMR_G0CLB_A11	0x00002000	/* General Line 0 : A11			*/
+#define MBMR_G0CLB_A10	0x00004000	/* General Line 0 : A10			*/
+#define MBMR_G0CLB_A9	0x00006000	/* General Line 0 : A9			*/
+#define MBMR_G0CLB_A8	0x00008000	/* General Line 0 : A8			*/
+#define MBMR_G0CLB_A7	0x0000A000	/* General Line 0 : A7			*/
+#define MBMR_G0CLB_A6	0x0000C000	/* General Line 0 : A6			*/
+#define MBMR_G0CLB_A5	0x0000E000	/* General Line 0 : A5			*/
+#define MBMR_GPL_B4DIS	0x00001000	/* GPL_B4 ouput line Disable		*/
+#define MBMR_RLFB_MSK	0x00000F00	/* Read Loop Field B mask		*/
+#define MBMR_RLFB_1X	0x00000100	/* The Read Loop is executed 1 time	*/
+#define MBMR_RLFB_2X	0x00000200	/* The Read Loop is executed 2 times	*/
+#define MBMR_RLFB_3X	0x00000300	/* The Read Loop is executed 3 times	*/
+#define MBMR_RLFB_4X	0x00000400	/* The Read Loop is executed 4 times	*/
+#define MBMR_RLFB_5X	0x00000500	/* The Read Loop is executed 5 times	*/
+#define MBMR_RLFB_6X	0x00000600	/* The Read Loop is executed 6 times	*/
+#define MBMR_RLFB_7X	0x00000700	/* The Read Loop is executed 7 times	*/
+#define MBMR_RLFB_8X	0x00000800	/* The Read Loop is executed 8 times	*/
+#define MBMR_RLFB_9X	0x00000900	/* The Read Loop is executed 9 times	*/
+#define MBMR_RLFB_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
+#define MBMR_RLFB_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
+#define MBMR_RLFB_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
+#define MBMR_RLFB_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
+#define MBMR_RLFB_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
+#define MBMR_RLFB_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
+#define MBMR_RLFB_16X	0x00000000	/* The Read Loop is executed 16 times	*/
+#define MBMR_WLFB_MSK	0x000000F0	/* Write Loop Field B mask		*/
+#define MBMR_WLFB_1X	0x00000010	/* The Write Loop is executed 1 time	*/
+#define MBMR_WLFB_2X	0x00000020	/* The Write Loop is executed 2 times	*/
+#define MBMR_WLFB_3X	0x00000030	/* The Write Loop is executed 3 times	*/
+#define MBMR_WLFB_4X	0x00000040	/* The Write Loop is executed 4 times	*/
+#define MBMR_WLFB_5X	0x00000050	/* The Write Loop is executed 5 times	*/
+#define MBMR_WLFB_6X	0x00000060	/* The Write Loop is executed 6 times	*/
+#define MBMR_WLFB_7X	0x00000070	/* The Write Loop is executed 7 times	*/
+#define MBMR_WLFB_8X	0x00000080	/* The Write Loop is executed 8 times	*/
+#define MBMR_WLFB_9X	0x00000090	/* The Write Loop is executed 9 times	*/
+#define MBMR_WLFB_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
+#define MBMR_WLFB_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
+#define MBMR_WLFB_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
+#define MBMR_WLFB_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
+#define MBMR_WLFB_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
+#define MBMR_WLFB_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
+#define MBMR_WLFB_16X	0x00000000	/* The Write Loop is executed 16 times	*/
+#define MBMR_TLFB_MSK	0x0000000F	/* Timer Loop Field B mask		*/
+#define MBMR_TLFB_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
+#define MBMR_TLFB_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
+#define MBMR_TLFB_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
+#define MBMR_TLFB_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
+#define MBMR_TLFB_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
+#define MBMR_TLFB_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
+#define MBMR_TLFB_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
+#define MBMR_TLFB_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
+#define MBMR_TLFB_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
+#define MBMR_TLFB_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
+#define MBMR_TLFB_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
+#define MBMR_TLFB_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
+#define MBMR_TLFB_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
+#define MBMR_TLFB_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
+#define MBMR_TLFB_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
+#define MBMR_TLFB_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
+
+/*-----------------------------------------------------------------------
+ * Timer Global Configuration Register					18-8
+ */
+#define TGCR_CAS4	0x8000		/* Cascade Timer 3 and 4	*/
+#define TGCR_FRZ4	0x4000		/* Freeze timer 4		*/
+#define TGCR_STP4	0x2000		/* Stop timer	4		*/
+#define TGCR_RST4	0x1000		/* Reset timer	4		*/
+#define TGCR_GM2	0x0800		/* Gate Mode for Pin 2		*/
+#define TGCR_FRZ3	0x0400		/* Freeze timer 3		*/
+#define TGCR_STP3	0x0200		/* Stop timer	3		*/
+#define TGCR_RST3	0x0100		/* Reset timer	3		*/
+#define TGCR_CAS2	0x0080		/* Cascade Timer 1 and 2	*/
+#define TGCR_FRZ2	0x0040		/* Freeze timer 2		*/
+#define TGCR_STP2	0x0020		/* Stop timer	2		*/
+#define TGCR_RST2	0x0010		/* Reset timer	2		*/
+#define TGCR_GM1	0x0008		/* Gate Mode for Pin 1		*/
+#define TGCR_FRZ1	0x0004		/* Freeze timer 1		*/
+#define TGCR_STP1	0x0002		/* Stop timer	1		*/
+#define TGCR_RST1	0x0001		/* Reset timer	1		*/
+
+
+/*-----------------------------------------------------------------------
+ * Timer Mode Register							18-9
+ */
+#define TMR_PS_MSK		0xFF00	/* Prescaler Value			*/
+#define TMR_PS_SHIFT		     8	/* Prescaler position			*/
+#define TMR_CE_MSK		0x00C0	/* Capture Edge and Enable Interrupt	*/
+#define TMR_CE_INTR_DIS		0x0000	/* Disable Interrupt on capture event	*/
+#define TMR_CE_RISING		0x0040	/* Capture on Rising TINx edge only	*/
+#define TMR_CE_FALLING		0x0080	/* Capture on Falling TINx edge only	*/
+#define TMR_CE_ANY		0x00C0	/* Capture on any TINx edge		*/
+#define TMR_OM			0x0020	/* Output Mode				*/
+#define TMR_ORI			0x0010	/* Output Reference Interrupt Enable	*/
+#define TMR_FRR			0x0008	/* Free Run/Restart			*/
+#define TMR_ICLK_MSK		0x0006	/* Timer Input Clock Source mask	*/
+#define TMR_ICLK_IN_CAS		0x0000	/* Internally cascaded input		*/
+#define TMR_ICLK_IN_GEN		0x0002	/* Internal General system clock	*/
+#define TMR_ICLK_IN_GEN_DIV16	0x0004	/* Internal General system clk div 16	*/
+#define TMR_ICLK_TIN_PIN	0x0006	/* TINx pin				*/
+#define TMR_GE			0x0001	/* Gate Enable				*/
+
+
+/*-----------------------------------------------------------------------
+ * I2C Controller Registers
+ */
+#define I2MOD_REVD		0x20	/* Reverese Data			*/
+#define I2MOD_GCD		0x10	/* General Call Disable			*/
+#define I2MOD_FLT		0x08	/* Clock Filter				*/
+#define I2MOD_PDIV32		0x00	/* Pre-Divider 32			*/
+#define I2MOD_PDIV16		0x02	/* Pre-Divider 16			*/
+#define I2MOD_PDIV8		0x04	/* Pre-Divider	8			*/
+#define I2MOD_PDIV4		0x06	/* Pre-Divider	4			*/
+#define I2MOD_EN		0x01	/* Enable				*/
+
+#define I2CER_TXE		0x10	/* Tx Error				*/
+#define I2CER_BSY		0x04	/* Busy Condition			*/
+#define I2CER_TXB		0x02	/* Tx Buffer Transmitted		*/
+#define I2CER_RXB		0x01	/* Rx Buffer Received			*/
+#define I2CER_ALL		(I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB)
+
+#define I2COM_STR		0x80	/* Start Transmit			*/
+#define I2COM_MASTER		0x01	/* Master mode				*/
+
+/*-----------------------------------------------------------------------
+ * SPI Controller Registers						31-10
+ */
+#define SPI_EMASK		0x37	/* Event Mask				*/
+#define SPI_MME			0x20	/* Multi-Master Error			*/
+#define SPI_TXE			0x10	/* Transmit Error			*/
+#define SPI_BSY			0x04	/* Busy					*/
+#define SPI_TXB			0x02	/* Tx Buffer Empty			*/
+#define SPI_RXB			0x01	/* RX Buffer full/closed		*/
+
+#define SPI_STR			0x80	/* SPCOM: Start transmit		*/
+
+/*-----------------------------------------------------------------------
+ * PCMCIA Interface General Control Register				17-12
+ */
+#define PCMCIA_GCRX_CXRESET	0x00000040
+#define PCMCIA_GCRX_CXOE	0x00000080
+
+#define PCMCIA_VS1(slot)	(0x80000000 >> (slot << 4))
+#define PCMCIA_VS2(slot)	(0x40000000 >> (slot << 4))
+#define PCMCIA_VS_MASK(slot)	(0xC0000000 >> (slot << 4))
+#define PCMCIA_VS_SHIFT(slot)	(30 - (slot << 4))
+
+#define PCMCIA_WP(slot)		(0x20000000 >> (slot << 4))
+#define PCMCIA_CD2(slot)	(0x10000000 >> (slot << 4))
+#define PCMCIA_CD1(slot)	(0x08000000 >> (slot << 4))
+#define PCMCIA_BVD2(slot)	(0x04000000 >> (slot << 4))
+#define PCMCIA_BVD1(slot)	(0x02000000 >> (slot << 4))
+#define PCMCIA_RDY(slot)	(0x01000000 >> (slot << 4))
+#define PCMCIA_RDY_L(slot)	(0x00800000 >> (slot << 4))
+#define PCMCIA_RDY_H(slot)	(0x00400000 >> (slot << 4))
+#define PCMCIA_RDY_R(slot)	(0x00200000 >> (slot << 4))
+#define PCMCIA_RDY_F(slot)	(0x00100000 >> (slot << 4))
+#define PCMCIA_MASK(slot)	(0xFFFF0000 >> (slot << 4))
+
+/*-----------------------------------------------------------------------
+ * PCMCIA Option Register Definitions
+ *
+ * Bank Sizes:
+ */
+#define PCMCIA_BSIZE_1		0x00000000	/* Bank size:	1 Bytes */
+#define PCMCIA_BSIZE_2		0x08000000	/* Bank size:	2 Bytes */
+#define PCMCIA_BSIZE_4		0x18000000	/* Bank size:	4 Bytes */
+#define PCMCIA_BSIZE_8		0x10000000	/* Bank size:	8 Bytes */
+#define PCMCIA_BSIZE_16		0x30000000	/* Bank size:  16 Bytes */
+#define PCMCIA_BSIZE_32		0x38000000	/* Bank size:  32 Bytes */
+#define PCMCIA_BSIZE_64		0x28000000	/* Bank size:  64 Bytes */
+#define PCMCIA_BSIZE_128	0x20000000	/* Bank size: 128 Bytes */
+#define PCMCIA_BSIZE_256	0x60000000	/* Bank size: 256 Bytes */
+#define PCMCIA_BSIZE_512	0x68000000	/* Bank size: 512 Bytes */
+#define PCMCIA_BSIZE_1K		0x78000000	/* Bank size:	1 kB	*/
+#define PCMCIA_BSIZE_2K		0x70000000	/* Bank size:	2 kB	*/
+#define PCMCIA_BSIZE_4K		0x50000000	/* Bank size:	4 kB	*/
+#define PCMCIA_BSIZE_8K		0x58000000	/* Bank size:	8 kB	*/
+#define PCMCIA_BSIZE_16K	0x48000000	/* Bank size:  16 kB	*/
+#define PCMCIA_BSIZE_32K	0x40000000	/* Bank size:  32 kB	*/
+#define PCMCIA_BSIZE_64K	0xC0000000	/* Bank size:  64 kB	*/
+#define PCMCIA_BSIZE_128K	0xC8000000	/* Bank size: 128 kB	*/
+#define PCMCIA_BSIZE_256K	0xD8000000	/* Bank size: 256 kB	*/
+#define PCMCIA_BSIZE_512K	0xD0000000	/* Bank size: 512 kB	*/
+#define PCMCIA_BSIZE_1M		0xF0000000	/* Bank size:	1 MB	*/
+#define PCMCIA_BSIZE_2M		0xF8000000	/* Bank size:	2 MB	*/
+#define PCMCIA_BSIZE_4M		0xE8000000	/* Bank size:	4 MB	*/
+#define PCMCIA_BSIZE_8M		0xE0000000	/* Bank size:	8 MB	*/
+#define PCMCIA_BSIZE_16M	0xA0000000	/* Bank size:  16 MB	*/
+#define PCMCIA_BSIZE_32M	0xA8000000	/* Bank size:  32 MB	*/
+#define PCMCIA_BSIZE_64M	0xB8000000	/* Bank size:  64 MB	*/
+
+/* PCMCIA Timing */
+#define PCMCIA_SHT(t)	((t & 0x0F)<<16)	/* Strobe Hold	Time	*/
+#define PCMCIA_SST(t)	((t & 0x0F)<<12)	/* Strobe Setup Time	*/
+#define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length	*/
+
+/* PCMCIA Port Sizes */
+#define PCMCIA_PPS_8		0x00000000	/*  8 bit port size	*/
+#define PCMCIA_PPS_16		0x00000040	/* 16 bit port size	*/
+
+/* PCMCIA Region Select */
+#define PCMCIA_PRS_MEM		0x00000000	/* Common Memory Space	*/
+#define PCMCIA_PRS_ATTR		0x00000010	/*     Attribute Space	*/
+#define PCMCIA_PRS_IO		0x00000018	/*	     I/O Space	*/
+#define PCMCIA_PRS_DMA		0x00000020	/* DMA, normal transfer */
+#define PCMCIA_PRS_DMA_LAST	0x00000028	/* DMA, last transactn	*/
+#define PCMCIA_PRS_CEx		0x00000030	/* A[22:23] ==> CE1,CE2 */
+
+#define PCMCIA_PSLOT_A		0x00000000	/* Slot A		*/
+#define PCMCIA_PSLOT_B		0x00000004	/* Slot B		*/
+#define PCMCIA_WPROT		0x00000002	/* Write Protect	*/
+#define PCMCIA_PV		0x00000001	/* Valid Bit		*/
+
+#define UPMA	0x00000000
+#define UPMB	0x00800000
+
+#endif	/* __MPCXX_H__ */
diff --git a/include/mpc8xx_irq.h b/include/mpc8xx_irq.h
new file mode 100644
index 0000000..15cf693
--- /dev/null
+++ b/include/mpc8xx_irq.h
@@ -0,0 +1,59 @@
+#ifndef _MPC8XX_IRQ_H
+#define _MPC8XX_IRQ_H
+
+/* The MPC8xx cores have 16 possible interrupts.  There are eight
+ * possible level sensitive interrupts assigned and generated internally
+ * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
+ * There are eight external interrupts (IRQs) that can be configured
+ * as either level or edge sensitive.
+ *
+ * On some implementations, there is also the possibility of an 8259
+ * through the PCI and PCI-ISA bridges.
+ *
+ * We don't support the 8259 (yet).
+ */
+#define NR_SIU_INTS	16
+#define	NR_8259_INTS	0
+
+#define NR_IRQS	(NR_SIU_INTS + NR_8259_INTS)
+
+/* These values must be zero-based and map 1:1 with the SIU configuration.
+ * They are used throughout the 8xx I/O subsystem to generate
+ * interrupt masks, flags, and other control patterns.  This is why the
+ * current kernel assumption of the 8259 as the base controller is such
+ * a pain in the butt.
+ */
+#define	SIU_IRQ0	(0)	/* Highest priority */
+#define	SIU_LEVEL0	(1)
+#define	SIU_IRQ1	(2)
+#define	SIU_LEVEL1	(3)
+#define	SIU_IRQ2	(4)
+#define	SIU_LEVEL2	(5)
+#define	SIU_IRQ3	(6)
+#define	SIU_LEVEL3	(7)
+#define	SIU_IRQ4	(8)
+#define	SIU_LEVEL4	(9)
+#define	SIU_IRQ5	(10)
+#define	SIU_LEVEL5	(11)
+#define	SIU_IRQ6	(12)
+#define	SIU_LEVEL6	(13)
+#define	SIU_IRQ7	(14)
+#define	SIU_LEVEL7	(15)
+
+/* The internal interrupts we can configure as we see fit.
+ * My personal preference is CPM at level 2, which puts it above the
+ * MBX PCI/ISA/IDE interrupts.
+ */
+
+#ifdef CONFIG_SYS_CPM_INTERRUPT
+# define CPM_INTERRUPT		CONFIG_SYS_CPM_INTERRUPT
+#else
+# define CPM_INTERRUPT		SIU_LEVEL2
+#endif
+
+/* Some internal interrupt registers use an 8-bit mask for the interrupt
+ * level instead of a number.
+ */
+#define	mk_int_int_mask(IL) (1 << (7 - (IL/2)))
+
+#endif /* _MPC8XX_IRQ_H */
diff --git a/include/msc01.h b/include/msc01.h
new file mode 100644
index 0000000..ec18a72
--- /dev/null
+++ b/include/msc01.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __MSC01_H__
+#define __MSC01_H__
+
+/*
+ * Bus Interface Unit
+ */
+
+#define MSC01_BIU_IP1BAS1L_OFS		0x0208
+#define MSC01_BIU_IP1MSK1L_OFS		0x0218
+#define MSC01_BIU_IP1BAS2L_OFS		0x0248
+#define MSC01_BIU_IP1MSK2L_OFS		0x0258
+#define MSC01_BIU_IP2BAS1L_OFS		0x0288
+#define MSC01_BIU_IP2MSK1L_OFS		0x0298
+#define MSC01_BIU_IP2BAS2L_OFS		0x02c8
+#define MSC01_BIU_IP2MSK2L_OFS		0x02d8
+#define MSC01_BIU_IP3BAS1L_OFS		0x0308
+#define MSC01_BIU_IP3MSK1L_OFS		0x0318
+#define MSC01_BIU_IP3BAS2L_OFS		0x0348
+#define MSC01_BIU_IP3MSK2L_OFS		0x0358
+#define MSC01_BIU_MCBAS1L_OFS		0x0388
+#define MSC01_BIU_MCMSK1L_OFS		0x0398
+#define MSC01_BIU_MCBAS2L_OFS		0x03c8
+#define MSC01_BIU_MCMSK2L_OFS		0x03d8
+
+/*
+ * PCI Bridge
+ */
+
+#define MSC01_PCI_SC2PMBASL_OFS		0x0208
+#define MSC01_PCI_SC2PMMSKL_OFS		0x0218
+#define MSC01_PCI_SC2PMMAPL_OFS		0x0228
+#define MSC01_PCI_SC2PIOBASL_OFS	0x0248
+#define MSC01_PCI_SC2PIOMSKL_OFS	0x0258
+#define MSC01_PCI_SC2PIOMAPL_OFS	0x0268
+#define MSC01_PCI_P2SCMSKL_OFS		0x0308
+#define MSC01_PCI_P2SCMAPL_OFS		0x0318
+#define MSC01_PCI_INTSTAT_OFS		0x0608
+#define MSC01_PCI_CFGADDR_OFS		0x0610
+#define MSC01_PCI_CFGDATA_OFS		0x0618
+#define MSC01_PCI_HEAD0_OFS		0x2000
+#define MSC01_PCI_HEAD1_OFS		0x2008
+#define MSC01_PCI_HEAD2_OFS		0x2010
+#define MSC01_PCI_HEAD3_OFS		0x2018
+#define MSC01_PCI_HEAD4_OFS		0x2020
+#define MSC01_PCI_HEAD5_OFS		0x2028
+#define MSC01_PCI_HEAD6_OFS		0x2030
+#define MSC01_PCI_HEAD7_OFS		0x2038
+#define MSC01_PCI_HEAD8_OFS		0x2040
+#define MSC01_PCI_HEAD9_OFS		0x2048
+#define MSC01_PCI_HEAD10_OFS		0x2050
+#define MSC01_PCI_HEAD11_OFS		0x2058
+#define MSC01_PCI_HEAD12_OFS		0x2060
+#define MSC01_PCI_HEAD13_OFS		0x2068
+#define MSC01_PCI_HEAD14_OFS		0x2070
+#define MSC01_PCI_HEAD15_OFS		0x2078
+#define MSC01_PCI_BAR0_OFS		0x2220
+#define MSC01_PCI_CFG_OFS		0x2380
+#define MSC01_PCI_SWAP_OFS		0x2388
+
+#define MSC01_PCI_SC2PMMSKL_MSK_MSK	0xff000000
+#define MSC01_PCI_SC2PIOMSKL_MSK_MSK	0xff000000
+
+#define MSC01_PCI_INTSTAT_TA_SHF	6
+#define MSC01_PCI_INTSTAT_TA_MSK	(0x1 << MSC01_PCI_INTSTAT_TA_SHF)
+#define MSC01_PCI_INTSTAT_MA_SHF	7
+#define MSC01_PCI_INTSTAT_MA_MSK	(0x1 << MSC01_PCI_INTSTAT_MA_SHF)
+
+#define MSC01_PCI_CFGADDR_BNUM_SHF	16
+#define MSC01_PCI_CFGADDR_BNUM_MSK	(0xff << MSC01_PCI_CFGADDR_BNUM_SHF)
+#define MSC01_PCI_CFGADDR_DNUM_SHF	11
+#define MSC01_PCI_CFGADDR_DNUM_MSK	(0x1f << MSC01_PCI_CFGADDR_DNUM_SHF)
+#define MSC01_PCI_CFGADDR_FNUM_SHF	8
+#define MSC01_PCI_CFGADDR_FNUM_MSK	(0x3 << MSC01_PCI_CFGADDR_FNUM_SHF)
+#define MSC01_PCI_CFGADDR_RNUM_SHF	2
+#define MSC01_PCI_CFGADDR_RNUM_MSK	(0x3f << MSC01_PCI_CFGADDR_RNUM_SHF)
+
+#define MSC01_PCI_HEAD0_VENDORID_SHF	0
+#define MSC01_PCI_HEAD0_DEVICEID_SHF	16
+
+#define MSC01_PCI_HEAD2_REV_SHF		0
+#define MSC01_PCI_HEAD2_CLASS_SHF	16
+
+#define MSC01_PCI_CFG_EN_SHF		15
+#define MSC01_PCI_CFG_EN_MSK		(0x1 << MSC01_PCI_CFG_EN_SHF)
+#define MSC01_PCI_CFG_G_SHF		16
+#define MSC01_PCI_CFG_G_MSK		(0x1 << MSC01_PCI_CFG_G_SHF)
+#define MSC01_PCI_CFG_RA_SHF		17
+#define MSC01_PCI_CFG_RA_MSK		(0x1 << MSC01_PCI_CFG_RA_SHF)
+
+#define MSC01_PCI_SWAP_BAR0_BSWAP_SHF	0
+#define MSC01_PCI_SWAP_IO_BSWAP_SHF	18
+
+/*
+ * Peripheral Bus Controller
+ */
+
+#define MSC01_PBC_CLKCFG_OFS		0x0100
+#define MSC01_PBC_CS0CFG_OFS		0x0400
+#define MSC01_PBC_CS0TIM_OFS		0x0500
+#define MSC01_PBC_CS0RW_OFS		0x0600
+
+#define MSC01_PBC_CLKCFG_SHF		0
+#define MSC01_PBC_CLKCFG_MSK		(0x1f << MSC01_PBC_CLKCFG_SHF)
+
+#define MSC01_PBC_CS0CFG_WS_SHF		0
+#define MSC01_PBC_CS0CFG_WS_MSK		(0x1f << MSC01_PBC_CS0CFG_WS_SHF)
+#define MSC01_PBC_CS0CFG_WSIDLE_SHF	8
+#define MSC01_PBC_CS0CFG_WSIDLE_MSK	(0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF)
+#define MSC01_PBC_CS0CFG_DTYP_SHF	16
+#define MSC01_PBC_CS0CFG_DTYP_MSK	(0x3 << MSC01_PBC_CS0CFG_DTYP_SHF)
+#define MSC01_PBC_CS0CFG_ADM_SHF	20
+#define MSC01_PBC_CS0CFG_ADM_MSK	(0x1 << MSC01_PBC_CS0CFG_ADM_SHF)
+
+#define MSC01_PBC_CS0TIM_CAT_SHF	0
+#define MSC01_PBC_CS0TIM_CAT_MSK	(0x1f << MSC01_PBC_CS0TIM_CAT_SHF)
+#define MSC01_PBC_CS0TIM_CDT_SHF	8
+#define MSC01_PBC_CS0TIM_CDT_MSK	(0x1f << MSC01_PBC_CS0TIM_CDT_SHF)
+
+#define MSC01_PBC_CS0RW_WAT_SHF		0
+#define MSC01_PBC_CS0RW_WAT_MSK		(0x1f << MSC01_PBC_CS0RW_WAT_SHF)
+#define MSC01_PBC_CS0RW_WDT_SHF		8
+#define MSC01_PBC_CS0RW_WDT_MSK		(0x1f << MSC01_PBC_CS0RW_WDT_SHF)
+#define MSC01_PBC_CS0RW_RAT_SHF		16
+#define MSC01_PBC_CS0RW_RAT_MSK		(0x1f << MSC01_PBC_CS0RW_RAT_SHF)
+#define MSC01_PBC_CS0RW_RDT_SHF		24
+#define MSC01_PBC_CS0RW_RDT_MSK		(0x1f << MSC01_PBC_CS0RW_RDT_SHF)
+
+#endif /* __MSC01_H__ */
diff --git a/include/mtd.h b/include/mtd.h
new file mode 100644
index 0000000..65fcd3c
--- /dev/null
+++ b/include/mtd.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
+ */
+
+#ifndef _MTD_H_
+#define _MTD_H_
+
+#include <linux/mtd/mtd.h>
+
+int mtd_probe(struct udevice *dev);
+int mtd_probe_devices(void);
+
+#endif	/* _MTD_H_ */
diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h
new file mode 100644
index 0000000..4963c89
--- /dev/null
+++ b/include/mtd/cfi_flash.h
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ */
+
+#ifndef __CFI_FLASH_H__
+#define __CFI_FLASH_H__
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_SETUP			0x60
+#define FLASH_CMD_SET_CR_CONFIRM	0x03
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_READ_STATUS		0x70
+#define FLASH_CMD_WRITE_TO_BUFFER	0xE8
+#define FLASH_CMD_WRITE_BUFFER_PROG	0xE9
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM	0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define AMD_CMD_RESET			0xF0
+#define AMD_CMD_WRITE			0xA0
+#define AMD_CMD_ERASE_START		0x80
+#define AMD_CMD_ERASE_SECTOR		0x30
+#define AMD_CMD_UNLOCK_START		0xAA
+#define AMD_CMD_UNLOCK_ACK		0x55
+#define AMD_CMD_WRITE_TO_BUFFER		0x25
+#define AMD_CMD_WRITE_BUFFER_CONFIRM	0x29
+#define AMD_CMD_SET_PPB_ENTRY		0xC0
+#define AMD_CMD_SET_PPB_EXIT_BC1	0x90
+#define AMD_CMD_SET_PPB_EXIT_BC2	0x00
+#define AMD_CMD_PPB_UNLOCK_BC1		0x80
+#define AMD_CMD_PPB_UNLOCK_BC2		0x30
+#define AMD_CMD_PPB_LOCK_BC1		0xA0
+#define AMD_CMD_PPB_LOCK_BC2		0x00
+
+#define AMD_STATUS_TOGGLE		0x40
+#define AMD_STATUS_ERROR		0x20
+
+#define ATM_CMD_UNLOCK_SECT		0x70
+#define ATM_CMD_SOFTLOCK_START		0x80
+#define ATM_CMD_LOCK_SECT		0x40
+
+#define FLASH_CONTINUATION_CODE		0x7F
+
+#define FLASH_OFFSET_MANUFACTURER_ID	0x00
+#define FLASH_OFFSET_DEVICE_ID		0x01
+#define FLASH_OFFSET_LOWER_SW_BITS	0x0C
+#define FLASH_OFFSET_DEVICE_ID2		0x0E
+#define FLASH_OFFSET_DEVICE_ID3		0x0F
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_ALT		0x555
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_PRIMARY_VENDOR	0x13
+/* extended query table primary address */
+#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR	0x15
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT		0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT		0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT		0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT		0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE		0x28
+#define FLASH_OFFSET_BUFFER_SIZE	0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION	0x85
+#define FLASH_OFFSET_INTEL_PROTECTION	0x81
+
+#define CFI_CMDSET_NONE			0
+#define CFI_CMDSET_INTEL_EXTENDED	1
+#define CFI_CMDSET_AMD_STANDARD		2
+#define CFI_CMDSET_INTEL_STANDARD	3
+#define CFI_CMDSET_AMD_EXTENDED		4
+#define CFI_CMDSET_MITSU_STANDARD	256
+#define CFI_CMDSET_MITSU_EXTENDED	257
+#define CFI_CMDSET_SST			258
+#define CFI_CMDSET_INTEL_PROG_REGIONS	512
+
+#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
+# undef  FLASH_CMD_RESET
+# define FLASH_CMD_RESET	AMD_CMD_RESET /* use AMD-Reset instead */
+#endif
+
+#define NUM_ERASE_REGIONS	4 /* max. number of erase regions */
+
+typedef union {
+	u8 w8;
+	u16 w16;
+	u32 w32;
+	u64 w64;
+} cfiword_t;
+
+/* CFI standard query structure */
+/* The offsets and sizes of this packed structure members correspond
+ * to the actual layout in CFI Flash chips. Some 16- and 32-bit members
+ * are unaligned and must be accessed with explicit unaligned access macros.
+ */
+struct cfi_qry {
+	u8	qry[3];
+	u16	p_id;			/* unaligned */
+	u16	p_adr;			/* unaligned */
+	u16	a_id;			/* unaligned */
+	u16	a_adr;			/* unaligned */
+	u8	vcc_min;
+	u8	vcc_max;
+	u8	vpp_min;
+	u8	vpp_max;
+	u8	word_write_timeout_typ;
+	u8	buf_write_timeout_typ;
+	u8	block_erase_timeout_typ;
+	u8	chip_erase_timeout_typ;
+	u8	word_write_timeout_max;
+	u8	buf_write_timeout_max;
+	u8	block_erase_timeout_max;
+	u8	chip_erase_timeout_max;
+	u8	dev_size;
+	u16	interface_desc;		/* aligned */
+	u16	max_buf_write_size;	/* aligned */
+	u8	num_erase_regions;
+	u32	erase_region_info[NUM_ERASE_REGIONS];	/* unaligned */
+} __attribute__((packed));
+
+struct cfi_pri_hdr {
+	u8	pri[3];
+	u8	major_version;
+	u8	minor_version;
+} __attribute__((packed));
+
+#ifndef CONFIG_SYS_FLASH_BANKS_LIST
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#endif
+
+/*
+ * CFI_MAX_FLASH_BANKS only used for flash_info struct declaration.
+ *
+ * Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined
+ */
+#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
+#define CONFIG_SYS_MAX_FLASH_BANKS	(cfi_flash_num_flash_banks)
+#define CFI_MAX_FLASH_BANKS	CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+/* board code can update this variable before CFI detection */
+extern int cfi_flash_num_flash_banks;
+#else
+#define CFI_MAX_FLASH_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
+#endif
+
+phys_addr_t cfi_flash_bank_addr(int i);
+unsigned long cfi_flash_bank_size(int i);
+void flash_cmd_reset(flash_info_t *info);
+
+#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+void flash_write8(u8 value, void *addr);
+void flash_write16(u16 value, void *addr);
+void flash_write32(u32 value, void *addr);
+void flash_write64(u64 value, void *addr);
+u8 flash_read8(void *addr);
+u16 flash_read16(void *addr);
+u32 flash_read32(void *addr);
+u64 flash_read64(void *addr);
+#endif
+
+#endif /* __CFI_FLASH_H__ */
diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h
new file mode 100644
index 0000000..8d97610
--- /dev/null
+++ b/include/mtd/mtd-abi.h
@@ -0,0 +1,274 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> et al.
+ *
+ */
+
+#ifndef __MTD_ABI_H__
+#define __MTD_ABI_H__
+
+#ifdef __UBOOT__
+#include <linux/compat.h>
+#endif
+
+#include <linux/compiler.h>
+
+struct erase_info_user {
+	__u32 start;
+	__u32 length;
+};
+
+struct erase_info_user64 {
+	__u64 start;
+	__u64 length;
+};
+
+struct mtd_oob_buf {
+	__u32 start;
+	__u32 length;
+	unsigned char __user *ptr;
+};
+
+struct mtd_oob_buf64 {
+	__u64 start;
+	__u32 pad;
+	__u32 length;
+	__u64 usr_ptr;
+};
+
+/**
+ * MTD operation modes
+ *
+ * @MTD_OPS_PLACE_OOB:	OOB data are placed at the given offset (default)
+ * @MTD_OPS_AUTO_OOB:	OOB data are automatically placed at the free areas
+ *			which are defined by the internal ecclayout
+ * @MTD_OPS_RAW:	data are transferred as-is, with no error correction;
+ *			this mode implies %MTD_OPS_PLACE_OOB
+ *
+ * These modes can be passed to ioctl(MEMWRITE) and are also used internally.
+ * See notes on "MTD file modes" for discussion on %MTD_OPS_RAW vs.
+ * %MTD_FILE_MODE_RAW.
+ */
+enum {
+	MTD_OPS_PLACE_OOB = 0,
+	MTD_OPS_AUTO_OOB = 1,
+	MTD_OPS_RAW = 2,
+};
+
+/**
+ * struct mtd_write_req - data structure for requesting a write operation
+ *
+ * @start:	start address
+ * @len:	length of data buffer
+ * @ooblen:	length of OOB buffer
+ * @usr_data:	user-provided data buffer
+ * @usr_oob:	user-provided OOB buffer
+ * @mode:	MTD mode (see "MTD operation modes")
+ * @padding:	reserved, must be set to 0
+ *
+ * This structure supports ioctl(MEMWRITE) operations, allowing data and/or OOB
+ * writes in various modes. To write to OOB-only, set @usr_data == NULL, and to
+ * write data-only, set @usr_oob == NULL. However, setting both @usr_data and
+ * @usr_oob to NULL is not allowed.
+ */
+struct mtd_write_req {
+	__u64 start;
+	__u64 len;
+	__u64 ooblen;
+	__u64 usr_data;
+	__u64 usr_oob;
+	__u8 mode;
+	__u8 padding[7];
+};
+
+#define MTD_ABSENT		0
+#define MTD_RAM			1
+#define MTD_ROM			2
+#define MTD_NORFLASH		3
+#define MTD_NANDFLASH		4	/* SLC NAND */
+#define MTD_DATAFLASH		6
+#define MTD_UBIVOLUME		7
+#define MTD_MLCNANDFLASH	8	/* MLC NAND (including TLC) */
+
+#define MTD_WRITEABLE		0x400	/* Device is writeable */
+#define MTD_BIT_WRITEABLE	0x800	/* Single bits can be flipped */
+#define MTD_NO_ERASE		0x1000	/* No erase necessary */
+#define MTD_POWERUP_LOCK	0x2000	/* Always locked after reset */
+
+/* Some common devices / combinations of capabilities */
+#define MTD_CAP_ROM		0
+#define MTD_CAP_RAM		(MTD_WRITEABLE | MTD_BIT_WRITEABLE | MTD_NO_ERASE)
+#define MTD_CAP_NORFLASH	(MTD_WRITEABLE | MTD_BIT_WRITEABLE)
+#define MTD_CAP_NANDFLASH	(MTD_WRITEABLE)
+
+/* Obsolete ECC byte placement modes (used with obsolete MEMGETOOBSEL) */
+#define MTD_NANDECC_OFF		0	// Switch off ECC (Not recommended)
+#define MTD_NANDECC_PLACE	1	// Use the given placement in the structure (YAFFS1 legacy mode)
+#define MTD_NANDECC_AUTOPLACE	2	// Use the default placement scheme
+#define MTD_NANDECC_PLACEONLY	3	// Use the given placement in the structure (Do not store ecc result on read)
+#define MTD_NANDECC_AUTOPL_USR 	4	// Use the given autoplacement scheme rather than using the default
+
+/* OTP mode selection */
+#define MTD_OTP_OFF		0
+#define MTD_OTP_FACTORY		1
+#define MTD_OTP_USER		2
+
+struct mtd_info_user {
+	__u8 type;
+	__u32 flags;
+	__u32 size;	/* Total size of the MTD */
+	__u32 erasesize;
+	__u32 writesize;
+	__u32 oobsize;	/* Amount of OOB data per block (e.g. 16) */
+	__u64 padding;	/* Old obsolete field; do not use */
+};
+
+struct region_info_user {
+	__u32 offset;		/* At which this region starts,
+				 * from the beginning of the MTD */
+	__u32 erasesize;	/* For this region */
+	__u32 numblocks;	/* Number of blocks in this region */
+	__u32 regionindex;
+};
+
+struct otp_info {
+	__u32 start;
+	__u32 length;
+	__u32 locked;
+};
+
+/*
+ * Note, the following ioctl existed in the past and was removed:
+ * #define MEMSETOOBSEL           _IOW('M', 9, struct nand_oobinfo)
+ * Try to avoid adding a new ioctl with the same ioctl number.
+ */
+
+/* Get basic MTD characteristics info (better to use sysfs) */
+#define MEMGETINFO		_IOR('M', 1, struct mtd_info_user)
+/* Erase segment of MTD */
+#define MEMERASE		_IOW('M', 2, struct erase_info_user)
+/* Write out-of-band data from MTD */
+#define MEMWRITEOOB		_IOWR('M', 3, struct mtd_oob_buf)
+/* Read out-of-band data from MTD */
+#define MEMREADOOB		_IOWR('M', 4, struct mtd_oob_buf)
+/* Lock a chip (for MTD that supports it) */
+#define MEMLOCK			_IOW('M', 5, struct erase_info_user)
+/* Unlock a chip (for MTD that supports it) */
+#define MEMUNLOCK		_IOW('M', 6, struct erase_info_user)
+/* Get the number of different erase regions */
+#define MEMGETREGIONCOUNT	_IOR('M', 7, int)
+/* Get information about the erase region for a specific index */
+#define MEMGETREGIONINFO	_IOWR('M', 8, struct region_info_user)
+/* Get info about OOB modes (e.g., RAW, PLACE, AUTO) - legacy interface */
+#define MEMGETOOBSEL		_IOR('M', 10, struct nand_oobinfo)
+/* Check if an eraseblock is bad */
+#define MEMGETBADBLOCK		_IOW('M', 11, __kernel_loff_t)
+/* Mark an eraseblock as bad */
+#define MEMSETBADBLOCK		_IOW('M', 12, __kernel_loff_t)
+/* Set OTP (One-Time Programmable) mode (factory vs. user) */
+#define OTPSELECT		_IOR('M', 13, int)
+/* Get number of OTP (One-Time Programmable) regions */
+#define OTPGETREGIONCOUNT	_IOW('M', 14, int)
+/* Get all OTP (One-Time Programmable) info about MTD */
+#define OTPGETREGIONINFO	_IOW('M', 15, struct otp_info)
+/* Lock a given range of user data (must be in mode %MTD_FILE_MODE_OTP_USER) */
+#define OTPLOCK			_IOR('M', 16, struct otp_info)
+/* Get ECC layout (deprecated) */
+#define ECCGETLAYOUT		_IOR('M', 17, struct nand_ecclayout_user)
+/* Get statistics about corrected/uncorrected errors */
+#define ECCGETSTATS		_IOR('M', 18, struct mtd_ecc_stats)
+/* Set MTD mode on a per-file-descriptor basis (see "MTD file modes") */
+#define MTDFILEMODE		_IO('M', 19)
+/* Erase segment of MTD (supports 64-bit address) */
+#define MEMERASE64		_IOW('M', 20, struct erase_info_user64)
+/* Write data to OOB (64-bit version) */
+#define MEMWRITEOOB64		_IOWR('M', 21, struct mtd_oob_buf64)
+/* Read data from OOB (64-bit version) */
+#define MEMREADOOB64		_IOWR('M', 22, struct mtd_oob_buf64)
+/* Check if chip is locked (for MTD that supports it) */
+#define MEMISLOCKED		_IOR('M', 23, struct erase_info_user)
+/*
+ * Most generic write interface; can write in-band and/or out-of-band in various
+ * modes (see "struct mtd_write_req"). This ioctl is not supported for flashes
+ * without OOB, e.g., NOR flash.
+ */
+#define MEMWRITE		_IOWR('M', 24, struct mtd_write_req)
+
+/*
+ * Obsolete legacy interface. Keep it in order not to break userspace
+ * interfaces
+ */
+struct nand_oobinfo {
+	__u32 useecc;
+	__u32 eccbytes;
+	__u32 oobfree[8][2];
+	__u32 eccpos[32];
+};
+
+struct nand_oobfree {
+	__u32 offset;
+	__u32 length;
+};
+
+#define MTD_MAX_OOBFREE_ENTRIES	8
+#define MTD_MAX_ECCPOS_ENTRIES	64
+/*
+ * OBSOLETE: ECC layout control structure. Exported to user-space via ioctl
+ * ECCGETLAYOUT for backwards compatbility and should not be mistaken as a
+ * complete set of ECC information. The ioctl truncates the larger internal
+ * structure to retain binary compatibility with the static declaration of the
+ * ioctl. Note that the "MTD_MAX_..._ENTRIES" macros represent the max size of
+ * the user struct, not the MAX size of the internal struct nand_ecclayout.
+ */
+struct nand_ecclayout_user {
+	__u32 eccbytes;
+	__u32 eccpos[MTD_MAX_ECCPOS_ENTRIES];
+	__u32 oobavail;
+	struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
+};
+
+/**
+ * struct mtd_ecc_stats - error correction stats
+ *
+ * @corrected:	number of corrected bits
+ * @failed:	number of uncorrectable errors
+ * @badblocks:	number of bad blocks in this partition
+ * @bbtblocks:	number of blocks reserved for bad block tables
+ */
+struct mtd_ecc_stats {
+	__u32 corrected;
+	__u32 failed;
+	__u32 badblocks;
+	__u32 bbtblocks;
+};
+
+/*
+ * MTD file modes - for read/write access to MTD
+ *
+ * @MTD_FILE_MODE_NORMAL:	OTP disabled, ECC enabled
+ * @MTD_FILE_MODE_OTP_FACTORY:	OTP enabled in factory mode
+ * @MTD_FILE_MODE_OTP_USER:	OTP enabled in user mode
+ * @MTD_FILE_MODE_RAW:		OTP disabled, ECC disabled
+ *
+ * These modes can be set via ioctl(MTDFILEMODE). The mode mode will be retained
+ * separately for each open file descriptor.
+ *
+ * Note: %MTD_FILE_MODE_RAW provides the same functionality as %MTD_OPS_RAW -
+ * raw access to the flash, without error correction or autoplacement schemes.
+ * Wherever possible, the MTD_OPS_* mode will override the MTD_FILE_MODE_* mode
+ * (e.g., when using ioctl(MEMWRITE)), but in some cases, the MTD_FILE_MODE is
+ * used out of necessity (e.g., `write()', ioctl(MEMWRITEOOB64)).
+ */
+enum mtd_file_modes {
+	MTD_FILE_MODE_NORMAL = MTD_OTP_OFF,
+	MTD_FILE_MODE_OTP_FACTORY = MTD_OTP_FACTORY,
+	MTD_FILE_MODE_OTP_USER = MTD_OTP_USER,
+	MTD_FILE_MODE_RAW,
+};
+
+static inline int mtd_type_is_nand_user(const struct mtd_info_user *mtd)
+{
+	return mtd->type == MTD_NANDFLASH || mtd->type == MTD_MLCNANDFLASH;
+}
+
+#endif /* __MTD_ABI_H__ */
diff --git a/include/mtd/ubi-user.h b/include/mtd/ubi-user.h
new file mode 100644
index 0000000..8d472cc
--- /dev/null
+++ b/include/mtd/ubi-user.h
@@ -0,0 +1,446 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright © International Business Machines Corp., 2006
+ *
+ * Author: Artem Bityutskiy (Битюцкий �ртём)
+ */
+
+#ifndef __UBI_USER_H__
+#define __UBI_USER_H__
+
+#include <linux/types.h>
+
+/*
+ * UBI device creation (the same as MTD device attachment)
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * MTD devices may be attached using %UBI_IOCATT ioctl command of the UBI
+ * control device. The caller has to properly fill and pass
+ * &struct ubi_attach_req object - UBI will attach the MTD device specified in
+ * the request and return the newly created UBI device number as the ioctl
+ * return value.
+ *
+ * UBI device deletion (the same as MTD device detachment)
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * An UBI device maybe deleted with %UBI_IOCDET ioctl command of the UBI
+ * control device.
+ *
+ * UBI volume creation
+ * ~~~~~~~~~~~~~~~~~~~
+ *
+ * UBI volumes are created via the %UBI_IOCMKVOL ioctl command of UBI character
+ * device. A &struct ubi_mkvol_req object has to be properly filled and a
+ * pointer to it has to be passed to the ioctl.
+ *
+ * UBI volume deletion
+ * ~~~~~~~~~~~~~~~~~~~
+ *
+ * To delete a volume, the %UBI_IOCRMVOL ioctl command of the UBI character
+ * device should be used. A pointer to the 32-bit volume ID hast to be passed
+ * to the ioctl.
+ *
+ * UBI volume re-size
+ * ~~~~~~~~~~~~~~~~~~
+ *
+ * To re-size a volume, the %UBI_IOCRSVOL ioctl command of the UBI character
+ * device should be used. A &struct ubi_rsvol_req object has to be properly
+ * filled and a pointer to it has to be passed to the ioctl.
+ *
+ * UBI volumes re-name
+ * ~~~~~~~~~~~~~~~~~~~
+ *
+ * To re-name several volumes atomically at one go, the %UBI_IOCRNVOL command
+ * of the UBI character device should be used. A &struct ubi_rnvol_req object
+ * has to be properly filled and a pointer to it has to be passed to the ioctl.
+ *
+ * UBI volume update
+ * ~~~~~~~~~~~~~~~~~
+ *
+ * Volume update should be done via the %UBI_IOCVOLUP ioctl command of the
+ * corresponding UBI volume character device. A pointer to a 64-bit update
+ * size should be passed to the ioctl. After this, UBI expects user to write
+ * this number of bytes to the volume character device. The update is finished
+ * when the claimed number of bytes is passed. So, the volume update sequence
+ * is something like:
+ *
+ * fd = open("/dev/my_volume");
+ * ioctl(fd, UBI_IOCVOLUP, &image_size);
+ * write(fd, buf, image_size);
+ * close(fd);
+ *
+ * Logical eraseblock erase
+ * ~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * To erase a logical eraseblock, the %UBI_IOCEBER ioctl command of the
+ * corresponding UBI volume character device should be used. This command
+ * unmaps the requested logical eraseblock, makes sure the corresponding
+ * physical eraseblock is successfully erased, and returns.
+ *
+ * Atomic logical eraseblock change
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * Atomic logical eraseblock change operation is called using the %UBI_IOCEBCH
+ * ioctl command of the corresponding UBI volume character device. A pointer to
+ * a &struct ubi_leb_change_req object has to be passed to the ioctl. Then the
+ * user is expected to write the requested amount of bytes (similarly to what
+ * should be done in case of the "volume update" ioctl).
+ *
+ * Logical eraseblock map
+ * ~~~~~~~~~~~~~~~~~~~~~
+ *
+ * To map a logical eraseblock to a physical eraseblock, the %UBI_IOCEBMAP
+ * ioctl command should be used. A pointer to a &struct ubi_map_req object is
+ * expected to be passed. The ioctl maps the requested logical eraseblock to
+ * a physical eraseblock and returns.  Only non-mapped logical eraseblocks can
+ * be mapped. If the logical eraseblock specified in the request is already
+ * mapped to a physical eraseblock, the ioctl fails and returns error.
+ *
+ * Logical eraseblock unmap
+ * ~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * To unmap a logical eraseblock to a physical eraseblock, the %UBI_IOCEBUNMAP
+ * ioctl command should be used. The ioctl unmaps the logical eraseblocks,
+ * schedules corresponding physical eraseblock for erasure, and returns. Unlike
+ * the "LEB erase" command, it does not wait for the physical eraseblock being
+ * erased. Note, the side effect of this is that if an unclean reboot happens
+ * after the unmap ioctl returns, you may find the LEB mapped again to the same
+ * physical eraseblock after the UBI is run again.
+ *
+ * Check if logical eraseblock is mapped
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * To check if a logical eraseblock is mapped to a physical eraseblock, the
+ * %UBI_IOCEBISMAP ioctl command should be used. It returns %0 if the LEB is
+ * not mapped, and %1 if it is mapped.
+ *
+ * Set an UBI volume property
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * To set an UBI volume property the %UBI_IOCSETPROP ioctl command should be
+ * used. A pointer to a &struct ubi_set_vol_prop_req object is expected to be
+ * passed. The object describes which property should be set, and to which value
+ * it should be set.
+ *
+ * Block devices on UBI volumes
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * To create a R/O block device on top of an UBI volume the %UBI_IOCVOLCRBLK
+ * should be used. A pointer to a &struct ubi_blkcreate_req object is expected
+ * to be passed, which is not used and reserved for future usage.
+ *
+ * Conversely, to remove a block device the %UBI_IOCVOLRMBLK should be used,
+ * which takes no arguments.
+ */
+
+/*
+ * When a new UBI volume or UBI device is created, users may either specify the
+ * volume/device number they want to create or to let UBI automatically assign
+ * the number using these constants.
+ */
+#define UBI_VOL_NUM_AUTO (-1)
+#define UBI_DEV_NUM_AUTO (-1)
+
+/* Maximum volume name length */
+#define UBI_MAX_VOLUME_NAME 127
+
+/* ioctl commands of UBI character devices */
+
+#define UBI_IOC_MAGIC 'o'
+
+/* Create an UBI volume */
+#define UBI_IOCMKVOL _IOW(UBI_IOC_MAGIC, 0, struct ubi_mkvol_req)
+/* Remove an UBI volume */
+#define UBI_IOCRMVOL _IOW(UBI_IOC_MAGIC, 1, __s32)
+/* Re-size an UBI volume */
+#define UBI_IOCRSVOL _IOW(UBI_IOC_MAGIC, 2, struct ubi_rsvol_req)
+/* Re-name volumes */
+#define UBI_IOCRNVOL _IOW(UBI_IOC_MAGIC, 3, struct ubi_rnvol_req)
+
+/* ioctl commands of the UBI control character device */
+
+#define UBI_CTRL_IOC_MAGIC 'o'
+
+/* Attach an MTD device */
+#define UBI_IOCATT _IOW(UBI_CTRL_IOC_MAGIC, 64, struct ubi_attach_req)
+/* Detach an MTD device */
+#define UBI_IOCDET _IOW(UBI_CTRL_IOC_MAGIC, 65, __s32)
+
+/* ioctl commands of UBI volume character devices */
+
+#define UBI_VOL_IOC_MAGIC 'O'
+
+/* Start UBI volume update
+ * Note: This actually takes a pointer (__s64*), but we can't change
+ *       that without breaking the ABI on 32bit systems
+ */
+#define UBI_IOCVOLUP _IOW(UBI_VOL_IOC_MAGIC, 0, __s64)
+/* LEB erasure command, used for debugging, disabled by default */
+#define UBI_IOCEBER _IOW(UBI_VOL_IOC_MAGIC, 1, __s32)
+/* Atomic LEB change command */
+#define UBI_IOCEBCH _IOW(UBI_VOL_IOC_MAGIC, 2, __s32)
+/* Map LEB command */
+#define UBI_IOCEBMAP _IOW(UBI_VOL_IOC_MAGIC, 3, struct ubi_map_req)
+/* Unmap LEB command */
+#define UBI_IOCEBUNMAP _IOW(UBI_VOL_IOC_MAGIC, 4, __s32)
+/* Check if LEB is mapped command */
+#define UBI_IOCEBISMAP _IOR(UBI_VOL_IOC_MAGIC, 5, __s32)
+/* Set an UBI volume property */
+#define UBI_IOCSETVOLPROP _IOW(UBI_VOL_IOC_MAGIC, 6, \
+			       struct ubi_set_vol_prop_req)
+/* Create a R/O block device on top of an UBI volume */
+#define UBI_IOCVOLCRBLK _IOW(UBI_VOL_IOC_MAGIC, 7, struct ubi_blkcreate_req)
+/* Remove the R/O block device */
+#define UBI_IOCVOLRMBLK _IO(UBI_VOL_IOC_MAGIC, 8)
+
+/* Maximum MTD device name length supported by UBI */
+#define MAX_UBI_MTD_NAME_LEN 127
+
+/* Maximum amount of UBI volumes that can be re-named at one go */
+#define UBI_MAX_RNVOL 32
+
+/*
+ * UBI volume type constants.
+ *
+ * @UBI_DYNAMIC_VOLUME: dynamic volume
+ * @UBI_STATIC_VOLUME:  static volume
+ */
+enum {
+	UBI_DYNAMIC_VOLUME = 3,
+	UBI_STATIC_VOLUME  = 4,
+};
+
+/*
+ * UBI set volume property ioctl constants.
+ *
+ * @UBI_VOL_PROP_DIRECT_WRITE: allow (any non-zero value) or disallow (value 0)
+ *                             user to directly write and erase individual
+ *                             eraseblocks on dynamic volumes
+ */
+enum {
+	UBI_VOL_PROP_DIRECT_WRITE = 1,
+};
+
+/**
+ * struct ubi_attach_req - attach MTD device request.
+ * @ubi_num: UBI device number to create
+ * @mtd_num: MTD device number to attach
+ * @vid_hdr_offset: VID header offset (use defaults if %0)
+ * @max_beb_per1024: maximum expected number of bad PEB per 1024 PEBs
+ * @padding: reserved for future, not used, has to be zeroed
+ *
+ * This data structure is used to specify MTD device UBI has to attach and the
+ * parameters it has to use. The number which should be assigned to the new UBI
+ * device is passed in @ubi_num. UBI may automatically assign the number if
+ * @UBI_DEV_NUM_AUTO is passed. In this case, the device number is returned in
+ * @ubi_num.
+ *
+ * Most applications should pass %0 in @vid_hdr_offset to make UBI use default
+ * offset of the VID header within physical eraseblocks. The default offset is
+ * the next min. I/O unit after the EC header. For example, it will be offset
+ * 512 in case of a 512 bytes page NAND flash with no sub-page support. Or
+ * it will be 512 in case of a 2KiB page NAND flash with 4 512-byte sub-pages.
+ *
+ * But in rare cases, if this optimizes things, the VID header may be placed to
+ * a different offset. For example, the boot-loader might do things faster if
+ * the VID header sits at the end of the first 2KiB NAND page with 4 sub-pages.
+ * As the boot-loader would not normally need to read EC headers (unless it
+ * needs UBI in RW mode), it might be faster to calculate ECC. This is weird
+ * example, but it real-life example. So, in this example, @vid_hdr_offer would
+ * be 2KiB-64 bytes = 1984. Note, that this position is not even 512-bytes
+ * aligned, which is OK, as UBI is clever enough to realize this is 4th
+ * sub-page of the first page and add needed padding.
+ *
+ * The @max_beb_per1024 is the maximum amount of bad PEBs UBI expects on the
+ * UBI device per 1024 eraseblocks.  This value is often given in an other form
+ * in the NAND datasheet (min NVB i.e. minimal number of valid blocks). The
+ * maximum expected bad eraseblocks per 1024 is then:
+ *    1024 * (1 - MinNVB / MaxNVB)
+ * Which gives 20 for most NAND devices.  This limit is used in order to derive
+ * amount of eraseblock UBI reserves for handling new bad blocks. If the device
+ * has more bad eraseblocks than this limit, UBI does not reserve any physical
+ * eraseblocks for new bad eraseblocks, but attempts to use available
+ * eraseblocks (if any). The accepted range is 0-768. If 0 is given, the
+ * default kernel value of %CONFIG_MTD_UBI_BEB_LIMIT will be used.
+ */
+struct ubi_attach_req {
+	__s32 ubi_num;
+	__s32 mtd_num;
+	__s32 vid_hdr_offset;
+	__s16 max_beb_per1024;
+	__s8 padding[10];
+};
+
+/*
+ * UBI volume flags.
+ *
+ * @UBI_VOL_SKIP_CRC_CHECK_FLG: skip the CRC check done on a static volume at
+ *				open time. Only valid for static volumes and
+ *				should only be used if the volume user has a
+ *				way to verify data integrity
+ */
+enum {
+	UBI_VOL_SKIP_CRC_CHECK_FLG = 0x1,
+};
+
+#define UBI_VOL_VALID_FLGS	(UBI_VOL_SKIP_CRC_CHECK_FLG)
+
+/**
+ * struct ubi_mkvol_req - volume description data structure used in
+ *                        volume creation requests.
+ * @vol_id: volume number
+ * @alignment: volume alignment
+ * @bytes: volume size in bytes
+ * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
+ * @flags: volume flags (%UBI_VOL_SKIP_CRC_CHECK_FLG)
+ * @name_len: volume name length
+ * @padding2: reserved for future, not used, has to be zeroed
+ * @name: volume name
+ *
+ * This structure is used by user-space programs when creating new volumes. The
+ * @used_bytes field is only necessary when creating static volumes.
+ *
+ * The @alignment field specifies the required alignment of the volume logical
+ * eraseblock. This means, that the size of logical eraseblocks will be aligned
+ * to this number, i.e.,
+ *	(UBI device logical eraseblock size) mod (@alignment) = 0.
+ *
+ * To put it differently, the logical eraseblock of this volume may be slightly
+ * shortened in order to make it properly aligned. The alignment has to be
+ * multiple of the flash minimal input/output unit, or %1 to utilize the entire
+ * available space of logical eraseblocks.
+ *
+ * The @alignment field may be useful, for example, when one wants to maintain
+ * a block device on top of an UBI volume. In this case, it is desirable to fit
+ * an integer number of blocks in logical eraseblocks of this UBI volume. With
+ * alignment it is possible to update this volume using plane UBI volume image
+ * BLOBs, without caring about how to properly align them.
+ */
+struct ubi_mkvol_req {
+	__s32 vol_id;
+	__s32 alignment;
+	__s64 bytes;
+	__s8 vol_type;
+	__u8 flags;
+	__s16 name_len;
+	__s8 padding2[4];
+	char name[UBI_MAX_VOLUME_NAME + 1];
+} __packed;
+
+/**
+ * struct ubi_rsvol_req - a data structure used in volume re-size requests.
+ * @vol_id: ID of the volume to re-size
+ * @bytes: new size of the volume in bytes
+ *
+ * Re-sizing is possible for both dynamic and static volumes. But while dynamic
+ * volumes may be re-sized arbitrarily, static volumes cannot be made to be
+ * smaller than the number of bytes they bear. To arbitrarily shrink a static
+ * volume, it must be wiped out first (by means of volume update operation with
+ * zero number of bytes).
+ */
+struct ubi_rsvol_req {
+	__s64 bytes;
+	__s32 vol_id;
+} __packed;
+
+/**
+ * struct ubi_rnvol_req - volumes re-name request.
+ * @count: count of volumes to re-name
+ * @padding1:  reserved for future, not used, has to be zeroed
+ * @vol_id: ID of the volume to re-name
+ * @name_len: name length
+ * @padding2:  reserved for future, not used, has to be zeroed
+ * @name: new volume name
+ *
+ * UBI allows to re-name up to %32 volumes at one go. The count of volumes to
+ * re-name is specified in the @count field. The ID of the volumes to re-name
+ * and the new names are specified in the @vol_id and @name fields.
+ *
+ * The UBI volume re-name operation is atomic, which means that should power cut
+ * happen, the volumes will have either old name or new name. So the possible
+ * use-cases of this command is atomic upgrade. Indeed, to upgrade, say, volumes
+ * A and B one may create temporary volumes %A1 and %B1 with the new contents,
+ * then atomically re-name A1->A and B1->B, in which case old %A and %B will
+ * be removed.
+ *
+ * If it is not desirable to remove old A and B, the re-name request has to
+ * contain 4 entries: A1->A, A->A1, B1->B, B->B1, in which case old A1 and B1
+ * become A and B, and old A and B will become A1 and B1.
+ *
+ * It is also OK to request: A1->A, A1->X, B1->B, B->Y, in which case old A1
+ * and B1 become A and B, and old A and B become X and Y.
+ *
+ * In other words, in case of re-naming into an existing volume name, the
+ * existing volume is removed, unless it is re-named as well at the same
+ * re-name request.
+ */
+struct ubi_rnvol_req {
+	__s32 count;
+	__s8 padding1[12];
+	struct {
+		__s32 vol_id;
+		__s16 name_len;
+		__s8  padding2[2];
+		char    name[UBI_MAX_VOLUME_NAME + 1];
+	} ents[UBI_MAX_RNVOL];
+} __packed;
+
+/**
+ * struct ubi_leb_change_req - a data structure used in atomic LEB change
+ *                             requests.
+ * @lnum: logical eraseblock number to change
+ * @bytes: how many bytes will be written to the logical eraseblock
+ * @dtype: pass "3" for better compatibility with old kernels
+ * @padding: reserved for future, not used, has to be zeroed
+ *
+ * The @dtype field used to inform UBI about what kind of data will be written
+ * to the LEB: long term (value 1), short term (value 2), unknown (value 3).
+ * UBI tried to pick a PEB with lower erase counter for short term data and a
+ * PEB with higher erase counter for long term data. But this was not really
+ * used because users usually do not know this and could easily mislead UBI. We
+ * removed this feature in May 2012. UBI currently just ignores the @dtype
+ * field. But for better compatibility with older kernels it is recommended to
+ * set @dtype to 3 (unknown).
+ */
+struct ubi_leb_change_req {
+	__s32 lnum;
+	__s32 bytes;
+	__s8  dtype; /* obsolete, do not use! */
+	__s8  padding[7];
+} __packed;
+
+/**
+ * struct ubi_map_req - a data structure used in map LEB requests.
+ * @dtype: pass "3" for better compatibility with old kernels
+ * @lnum: logical eraseblock number to unmap
+ * @padding: reserved for future, not used, has to be zeroed
+ */
+struct ubi_map_req {
+	__s32 lnum;
+	__s8  dtype; /* obsolete, do not use! */
+	__s8  padding[3];
+} __packed;
+
+
+/**
+ * struct ubi_set_vol_prop_req - a data structure used to set an UBI volume
+ *                               property.
+ * @property: property to set (%UBI_VOL_PROP_DIRECT_WRITE)
+ * @padding: reserved for future, not used, has to be zeroed
+ * @value: value to set
+ */
+struct ubi_set_vol_prop_req {
+	__u8  property;
+	__u8  padding[7];
+	__u64 value;
+}  __packed;
+
+/**
+ * struct ubi_blkcreate_req - a data structure used in block creation requests.
+ * @padding: reserved for future, not used, has to be zeroed
+ */
+struct ubi_blkcreate_req {
+	__s8  padding[128];
+}  __packed;
+
+#endif /* __UBI_USER_H__ */
diff --git a/include/mtd_node.h b/include/mtd_node.h
new file mode 100644
index 0000000..5aae085
--- /dev/null
+++ b/include/mtd_node.h
@@ -0,0 +1,11 @@
+#ifndef _NODE_INFO
+#define _NODE_INFO
+
+/*
+ * Info we use to search for a flash node in DTB.
+ */
+struct node_info {
+	const char *compat;	/* compatible string */
+	int type;		/* mtd flash type */
+};
+#endif
diff --git a/include/mv88e6352.h b/include/mv88e6352.h
new file mode 100644
index 0000000..2e810c8
--- /dev/null
+++ b/include/mv88e6352.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
+ */
+
+#ifndef __MV886352_H
+#define __MV886352_H
+
+#include <common.h>
+
+/* PHY registers */
+#define PHY(itf)	(itf)
+
+#define PHY_CTRL	0x00
+#define PHY_100_MBPS	0x2000
+#define PHY_1_GBPS	0x0040
+#define AUTONEG_EN	0x1000
+#define AUTONEG_RST	0x0200
+#define FULL_DUPLEX	0x0100
+#define PHY_PWR_DOWN	0x0800
+
+#define PHY_STATUS	0x01
+#define AN1000FIX	0x0001
+
+#define PHY_SPEC_CTRL	0x10
+#define SPEC_PWR_DOWN	0x0004
+#define AUTO_MDIX_EN	0x0060
+
+#define PHY_1000_CTRL	0x9
+
+#define NO_ADV		0x0000
+#define ADV_1000_FDPX	0x0200
+#define ADV_1000_HDPX	0x0100
+
+#define PHY_PAGE	0x16
+
+#define AN1000FIX_PAGE	0x00fc
+
+/* PORT or MAC registers */
+#define PORT(itf)	(itf+0x10)
+
+#define PORT_STATUS	0x00
+#define NO_PHY_DETECT	0x0000
+
+#define PORT_PHY	0x01
+#define RX_RGMII_TIM	0x8000
+#define TX_RGMII_TIM	0x4000
+#define FLOW_CTRL_EN	0x0080
+#define FLOW_CTRL_FOR	0x0040
+#define LINK_VAL	0x0020
+#define LINK_FOR	0x0010
+#define FULL_DPX	0x0008
+#define FULL_DPX_FOR	0x0004
+#define NO_SPEED_FOR	0x0003
+#define SPEED_1000_FOR	0x0002
+#define SPEED_100_FOR	0x0001
+#define SPEED_10_FOR	0x0000
+
+#define PORT_CTRL	0x04
+#define FORWARDING	0x0003
+#define EGRS_FLD_ALL	0x000c
+#define PORT_DIS	0x0000
+
+struct mv88e_sw_reg {
+	u8 port;
+	u8 reg;
+	u16 value;
+};
+
+int mv88e_sw_reset(const char *devname, u8 phy_addr);
+int mv88e_sw_program(const char *devname, u8 phy_addr,
+	struct mv88e_sw_reg *regs, int regs_nb);
+
+#endif
diff --git a/include/mvebu/comphy.h b/include/mvebu/comphy.h
new file mode 100644
index 0000000..cde7a02
--- /dev/null
+++ b/include/mvebu/comphy.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ */
+
+#ifndef _MVEBU_COMPHY_H_
+#define _MVEBU_COMPHY_H_
+
+#include <dt-bindings/comphy/comphy_data.h>
+
+struct comphy_map {
+	u32 type;
+	u32 speed;
+	u32 invert;
+	bool clk_src;
+	bool end_point;
+};
+
+int comphy_update_map(struct comphy_map *serdes_map, int count);
+
+#endif /* _MVEBU_COMPHY_H_ */
+
diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h
new file mode 100644
index 0000000..7397165
--- /dev/null
+++ b/include/mvebu_mmc.h
@@ -0,0 +1,274 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Marvell MMC/SD/SDIO driver
+ *
+ * (C) Copyright 2012
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Maen Suleiman, Gerald Kerma
+ */
+
+#ifndef __MVEBU_MMC_H__
+#define __MVEBU_MMC_H__
+
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
+#define MMC_BLOCK_SIZE				512
+
+/*
+ * Clock rates
+ */
+
+#define MVEBU_MMC_CLOCKRATE_MAX			50000000
+#define MVEBU_MMC_BASE_DIV_MAX			0x7ff
+#define MVEBU_MMC_BASE_FAST_CLOCK		CONFIG_SYS_TCLK
+#define MVEBU_MMC_BASE_FAST_CLK_100		100000000
+#define MVEBU_MMC_BASE_FAST_CLK_200		200000000
+
+/* SDIO register */
+#define SDIO_SYS_ADDR_LOW			0x000
+#define SDIO_SYS_ADDR_HI			0x004
+#define SDIO_BLK_SIZE				0x008
+#define SDIO_BLK_COUNT				0x00c
+#define SDIO_ARG_LOW				0x010
+#define SDIO_ARG_HI				0x014
+#define SDIO_XFER_MODE				0x018
+#define SDIO_CMD				0x01c
+#define SDIO_RSP(i)				(0x020 + ((i)<<2))
+#define SDIO_RSP0				0x020
+#define SDIO_RSP1				0x024
+#define SDIO_RSP2				0x028
+#define SDIO_RSP3				0x02c
+#define SDIO_RSP4				0x030
+#define SDIO_RSP5				0x034
+#define SDIO_RSP6				0x038
+#define SDIO_RSP7				0x03c
+#define SDIO_BUF_DATA_PORT			0x040
+#define SDIO_RSVED				0x044
+#define SDIO_HW_STATE				0x048
+#define SDIO_PRESENT_STATE0			0x048
+#define SDIO_PRESENT_STATE1			0x04c
+#define SDIO_HOST_CTRL				0x050
+#define SDIO_BLK_GAP_CTRL			0x054
+#define SDIO_CLK_CTRL				0x058
+#define SDIO_SW_RESET				0x05c
+#define SDIO_NOR_INTR_STATUS			0x060
+#define SDIO_ERR_INTR_STATUS			0x064
+#define SDIO_NOR_STATUS_EN			0x068
+#define SDIO_ERR_STATUS_EN			0x06c
+#define SDIO_NOR_INTR_EN			0x070
+#define SDIO_ERR_INTR_EN			0x074
+#define SDIO_AUTOCMD12_ERR_STATUS		0x078
+#define SDIO_CURR_BYTE_LEFT			0x07c
+#define SDIO_CURR_BLK_LEFT			0x080
+#define SDIO_AUTOCMD12_ARG_LOW			0x084
+#define SDIO_AUTOCMD12_ARG_HI			0x088
+#define SDIO_AUTOCMD12_INDEX			0x08c
+#define SDIO_AUTO_RSP(i)			(0x090 + ((i)<<2))
+#define SDIO_AUTO_RSP0				0x090
+#define SDIO_AUTO_RSP1				0x094
+#define SDIO_AUTO_RSP2				0x098
+#define SDIO_CLK_DIV				0x128
+
+#define WINDOW_CTRL(i)				(0x108 + ((i) << 3))
+#define WINDOW_BASE(i)				(0x10c + ((i) << 3))
+
+/* SDIO_PRESENT_STATE */
+#define CARD_BUSY				(1 << 1)
+#define CMD_INHIBIT				(1 << 0)
+#define CMD_TXACTIVE				(1 << 8)
+#define CMD_RXACTIVE				(1 << 9)
+#define CMD_FIFO_EMPTY				(1 << 13)
+#define CMD_AUTOCMD12ACTIVE			(1 << 14)
+#define CMD_BUS_BUSY				(CMD_AUTOCMD12ACTIVE |	\
+						CMD_RXACTIVE |	\
+						CMD_TXACTIVE |	\
+						CMD_INHIBIT |	\
+						CARD_BUSY)
+
+/*
+ * SDIO_CMD
+ */
+
+#define SDIO_CMD_RSP_NONE			(0 << 0)
+#define SDIO_CMD_RSP_136			(1 << 0)
+#define SDIO_CMD_RSP_48				(2 << 0)
+#define SDIO_CMD_RSP_48BUSY			(3 << 0)
+
+#define SDIO_CMD_CHECK_DATACRC16		(1 << 2)
+#define SDIO_CMD_CHECK_CMDCRC			(1 << 3)
+#define SDIO_CMD_INDX_CHECK			(1 << 4)
+#define SDIO_CMD_DATA_PRESENT			(1 << 5)
+#define SDIO_UNEXPECTED_RESP			(1 << 7)
+
+#define SDIO_CMD_INDEX(x)			((x) << 8)
+
+/*
+ * SDIO_XFER_MODE
+ */
+
+#define SDIO_XFER_MODE_STOP_CLK			(1 << 5)
+#define SDIO_XFER_MODE_HW_WR_DATA_EN		(1 << 1)
+#define SDIO_XFER_MODE_AUTO_CMD12		(1 << 2)
+#define SDIO_XFER_MODE_INT_CHK_EN		(1 << 3)
+#define SDIO_XFER_MODE_TO_HOST			(1 << 4)
+#define SDIO_XFER_MODE_DMA			(0 << 6)
+
+/*
+ * SDIO_HOST_CTRL
+ */
+
+#define SDIO_HOST_CTRL_PUSH_PULL_EN		(1 << 0)
+
+#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY	(0 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY	(1 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO	(2 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC		(3 << 1)
+#define SDIO_HOST_CTRL_CARD_TYPE_MASK		(3 << 1)
+
+#define SDIO_HOST_CTRL_BIG_ENDIAN		(1 << 3)
+#define SDIO_HOST_CTRL_LSB_FIRST		(1 << 4)
+#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT		(0 << 9)
+#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS	(1 << 9)
+#define SDIO_HOST_CTRL_HI_SPEED_EN		(1 << 10)
+
+#define SDIO_HOST_CTRL_TMOUT_MAX		0xf
+#define SDIO_HOST_CTRL_TMOUT_MASK		(0xf << 11)
+#define SDIO_HOST_CTRL_TMOUT(x)			((x) << 11)
+#define SDIO_HOST_CTRL_TMOUT_EN			(1 << 15)
+
+/*
+ * SDIO_SW_RESET
+ */
+
+#define SDIO_SW_RESET_NOW			(1 << 8)
+
+/*
+ * Normal interrupt status bits
+ */
+
+#define SDIO_NOR_ERROR				(1 << 15)
+#define SDIO_NOR_UNEXP_RSP			(1 << 14)
+#define SDIO_NOR_AUTOCMD12_DONE			(1 << 13)
+#define SDIO_NOR_SUSPEND_ON			(1 << 12)
+#define SDIO_NOR_LMB_FF_8W_AVAIL		(1 << 11)
+#define SDIO_NOR_LMB_FF_8W_FILLED		(1 << 10)
+#define SDIO_NOR_READ_WAIT_ON			(1 << 9)
+#define SDIO_NOR_CARD_INT			(1 << 8)
+#define SDIO_NOR_READ_READY			(1 << 5)
+#define SDIO_NOR_WRITE_READY			(1 << 4)
+#define SDIO_NOR_DMA_INI			(1 << 3)
+#define SDIO_NOR_BLK_GAP_EVT			(1 << 2)
+#define SDIO_NOR_XFER_DONE			(1 << 1)
+#define SDIO_NOR_CMD_DONE			(1 << 0)
+
+/*
+ * Error status bits
+ */
+
+#define SDIO_ERR_CRC_STATUS			(1 << 14)
+#define SDIO_ERR_CRC_STARTBIT			(1 << 13)
+#define SDIO_ERR_CRC_ENDBIT			(1 << 12)
+#define SDIO_ERR_RESP_TBIT			(1 << 11)
+#define SDIO_ERR_XFER_SIZE			(1 << 10)
+#define SDIO_ERR_CMD_STARTBIT			(1 << 9)
+#define SDIO_ERR_AUTOCMD12			(1 << 8)
+#define SDIO_ERR_DATA_ENDBIT			(1 << 6)
+#define SDIO_ERR_DATA_CRC			(1 << 5)
+#define SDIO_ERR_DATA_TIMEOUT			(1 << 4)
+#define SDIO_ERR_CMD_INDEX			(1 << 3)
+#define SDIO_ERR_CMD_ENDBIT			(1 << 2)
+#define SDIO_ERR_CMD_CRC			(1 << 1)
+#define SDIO_ERR_CMD_TIMEOUT			(1 << 0)
+/* enable all for polling */
+#define SDIO_POLL_MASK				0xffff
+
+/*
+ * CMD12 error status bits
+ */
+
+#define SDIO_AUTOCMD12_ERR_NOTEXE		(1 << 0)
+#define SDIO_AUTOCMD12_ERR_TIMEOUT		(1 << 1)
+#define SDIO_AUTOCMD12_ERR_CRC			(1 << 2)
+#define SDIO_AUTOCMD12_ERR_ENDBIT		(1 << 3)
+#define SDIO_AUTOCMD12_ERR_INDEX		(1 << 4)
+#define SDIO_AUTOCMD12_ERR_RESP_T_BIT		(1 << 5)
+#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT	(1 << 6)
+
+#define MMC_RSP_PRESENT				(1 << 0)
+/* 136 bit response */
+#define MMC_RSP_136				(1 << 1)
+/* expect valid crc */
+#define MMC_RSP_CRC				(1 << 2)
+/* card may send busy */
+#define MMC_RSP_BUSY				(1 << 3)
+/* response contains opcode */
+#define MMC_RSP_OPCODE				(1 << 4)
+
+#define MMC_BUSMODE_OPENDRAIN			1
+#define MMC_BUSMODE_PUSHPULL			2
+
+#define MMC_BUS_WIDTH_1				0
+#define MMC_BUS_WIDTH_4				2
+#define MMC_BUS_WIDTH_8				3
+
+/* Can the host do 4 bit transfers */
+#define MMC_CAP_4_BIT_DATA			(1 << 0)
+/* Can do MMC high-speed timing */
+#define MMC_CAP_MMC_HIGHSPEED			(1 << 1)
+/* Can do SD high-speed timing */
+#define MMC_CAP_SD_HIGHSPEED			(1 << 2)
+/* Can signal pending SDIO IRQs */
+#define MMC_CAP_SDIO_IRQ			(1 << 3)
+/* Talks only SPI protocols */
+#define MMC_CAP_SPI				(1 << 4)
+/* Can the host do 8 bit transfers */
+#define MMC_CAP_8_BIT_DATA			(1 << 6)
+
+/* Waits while card is busy */
+#define MMC_CAP_WAIT_WHILE_BUSY			(1 << 9)
+/* Allow erase/trim commands */
+#define MMC_CAP_ERASE				(1 << 10)
+/* can support DDR mode at 1.8V */
+#define MMC_CAP_1_8V_DDR			(1 << 11)
+/* can support DDR mode at 1.2V */
+#define MMC_CAP_1_2V_DDR			(1 << 12)
+/* Can power off after boot */
+#define MMC_CAP_POWER_OFF_CARD			(1 << 13)
+/* CMD14/CMD19 bus width ok */
+#define MMC_CAP_BUS_WIDTH_TEST			(1 << 14)
+/* Host supports UHS SDR12 mode */
+#define MMC_CAP_UHS_SDR12			(1 << 15)
+/* Host supports UHS SDR25 mode */
+#define MMC_CAP_UHS_SDR25			(1 << 16)
+/* Host supports UHS SDR50 mode */
+#define MMC_CAP_UHS_SDR50			(1 << 17)
+/* Host supports UHS SDR104 mode */
+#define MMC_CAP_UHS_SDR104			(1 << 18)
+/* Host supports UHS DDR50 mode */
+#define MMC_CAP_UHS_DDR50			(1 << 19)
+/* Host supports Driver Type A */
+#define MMC_CAP_DRIVER_TYPE_A			(1 << 23)
+/* Host supports Driver Type C */
+#define MMC_CAP_DRIVER_TYPE_C			(1 << 24)
+/* Host supports Driver Type D */
+#define MMC_CAP_DRIVER_TYPE_D			(1 << 25)
+/* CMD23 supported. */
+#define MMC_CAP_CMD23				(1 << 30)
+/* Hardware reset */
+#define MMC_CAP_HW_RESET			(1 << 31)
+
+struct mvebu_mmc_cfg {
+	u32	mvebu_mmc_base;
+	u32	mvebu_mmc_clk;
+	u8	max_bus_width;
+	struct mmc_config cfg;
+};
+
+/*
+ * Functions prototypes
+ */
+
+int mvebu_mmc_init(bd_t *bis);
+
+#endif /* __MVEBU_MMC_H__ */
diff --git a/include/mvmfp.h b/include/mvmfp.h
new file mode 100644
index 0000000..16f2684
--- /dev/null
+++ b/include/mvmfp.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef __MVMFP_H
+#define __MVMFP_H
+
+/*
+ * Header file for MultiFunctionPin (MFP) Configururation framework
+ *
+ * Processors Supported:
+ * 1. Marvell ARMADA100 Processors
+ *
+ * processor to be supported should be added here
+ */
+
+/*
+ * MFP configuration is represented by a 32-bit unsigned integer
+ */
+#ifdef CONFIG_MVMFP_V2
+#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \
+	/* bits 31..16 - MFP Register Offset */	(((_off) & 0xffff) << 16) | \
+	/* bits 15..13 - Run Mode Pull State */	(((_pull) & 0x7) << 13) | \
+	/* bit  12..11 - Driver Strength */	(((_drv) & 0x3) << 11) | \
+	/* bits 10     - pad driver */		(((_slp) & 0x1) << 10) | \
+	/* bit  09..07 - sleep mode */		(((_sleep) & 0xe) << 6) | \
+	/* bits 06..04 - Edge Detection */	(((_edge) & 0x7) << 4) | \
+	/* bits 03     - sleep mode */		(((_sleep) & 0x1) << 3) | \
+	/* bits 02..00 - Alt-fun select */	((_afn) & 0x7))
+#else
+#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \
+	/* bits 31..16 - MFP Register Offset */	(((_off) & 0xffff) << 16) | \
+	/* bits 15..13 - Run Mode Pull State */	(((_pull) & 0x7) << 13) | \
+	/* bit  12     - Unused */ \
+	/* bits 11..10 - Driver Strength */	(((_drv) & 0x3) << 10) | \
+	/* bit  09..07 - sleep mode */		(((_sleep) & 0xe) << 6) | \
+	/* bits 06..04 - Edge Detection */	(((_edge) & 0x7) << 4) | \
+	/* bits 03     - sleep mode */		(((_sleep) & 0x1) << 3) | \
+	/* bits 02..00 - Alt-fun select */	((_afn) & 0x7))
+#endif
+
+/*
+ * to facilitate the definition, the following macros are provided
+ *
+ * 				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+#define MFP_OFFSET_MASK		MFP(0xffff,    0,    0,   0,   0,   0,   0)
+#define MFP_REG(x)		MFP(x,         0,    0,   0,   0,   0,   0)
+#define MFP_REG_GET_OFFSET(x)	((x & MFP_OFFSET_MASK) >> 16)
+
+#define MFP_AF0			MFP(0x0000,    0,    0,   0,   0,   0,   0)
+#define MFP_AF1			MFP(0x0000,    0,    0,   0,   0,   0,   1)
+#define MFP_AF2			MFP(0x0000,    0,    0,   0,   0,   0,   2)
+#define MFP_AF3			MFP(0x0000,    0,    0,   0,   0,   0,   3)
+#define MFP_AF4			MFP(0x0000,    0,    0,   0,   0,   0,   4)
+#define MFP_AF5			MFP(0x0000,    0,    0,   0,   0,   0,   5)
+#define MFP_AF6			MFP(0x0000,    0,    0,   0,   0,   0,   6)
+#define MFP_AF7			MFP(0x0000,    0,    0,   0,   0,   0,   7)
+#define MFP_AF_MASK		MFP(0x0000,    0,    0,   0,   0,   0,   7)
+
+#define MFP_SLEEP_CTRL2		MFP(0x0000,    0,    0,   0,   0,   1,   0)
+#define MFP_SLEEP_DIR		MFP(0x0000,    0,    0,   0,   0,   2,   0)
+#define MFP_SLEEP_DATA		MFP(0x0000,    0,    0,   0,   0,   4,   0)
+#define MFP_SLEEP_CTRL		MFP(0x0000,    0,    0,   0,   0,   8,   0)
+#define MFP_SLEEP_MASK		MFP(0x0000,    0,    0,   0,   0, 0xf,   0)
+
+#define MFP_LPM_EDGE_NONE	MFP(0x0000,    0,    0,   0,   4,   0,   0)
+#define MFP_LPM_EDGE_RISE	MFP(0x0000,    0,    0,   0,   1,   0,   0)
+#define MFP_LPM_EDGE_FALL	MFP(0x0000,    0,    0,   0,   2,   0,   0)
+#define MFP_LPM_EDGE_BOTH	MFP(0x0000,    0,    0,   0,   3,   0,   0)
+#define MFP_LPM_EDGE_MASK	MFP(0x0000,    0,    0,   0,   7,   0,   0)
+
+#define MFP_SLP_DI		MFP(0x0000,    0,    0,   1,   0,   0,   0)
+
+#define MFP_DRIVE_VERY_SLOW	MFP(0x0000,    0,    0,   0,   0,   0,   0)
+#define MFP_DRIVE_SLOW		MFP(0x0000,    0,    1,   0,   0,   0,   0)
+#define MFP_DRIVE_MEDIUM	MFP(0x0000,    0,    2,   0,   0,   0,   0)
+#define MFP_DRIVE_FAST		MFP(0x0000,    0,    3,   0,   0,   0,   0)
+#define MFP_DRIVE_MASK		MFP(0x0000,    0,    3,   0,   0,   0,   0)
+
+#define MFP_PULL_NONE		MFP(0x0000,    0,    0,   0,   0,   0,   0)
+#define MFP_PULL_LOW		MFP(0x0000,    5,    0,   0,   0,   0,   0)
+#define MFP_PULL_HIGH		MFP(0x0000,    6,    0,   0,   0,   0,   0)
+#define MFP_PULL_BOTH		MFP(0x0000,    7,    0,   0,   0,   0,   0)
+#define MFP_PULL_FLOAT		MFP(0x0000,    4,    0,   0,   0,   0,   0)
+#define MFP_PULL_MASK		MFP(0x0000,    7,    0,   0,   0,   0,   0)
+
+#define MFP_VALUE_MASK		(MFP_PULL_MASK | MFP_DRIVE_MASK | MFP_SLP_DI \
+				| MFP_LPM_EDGE_MASK | MFP_SLEEP_MASK \
+				| MFP_AF_MASK)
+#define MFP_EOC			0xffffffff	/* indicates end-of-conf */
+
+/* Functions */
+void mfp_config(u32 *mfp_cfgs);
+
+#endif /* __MVMFP_H */
diff --git a/include/mxs_nand.h b/include/mxs_nand.h
new file mode 100644
index 0000000..4bd65cd
--- /dev/null
+++ b/include/mxs_nand.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * NXP GPMI NAND flash driver
+ *
+ * Copyright (C) 2018 Toradex
+ * Authors:
+ * Stefan Agner <stefan.agner@toradex.com>
+ */
+
+#include <linux/mtd/mtd.h>
+#include <asm/cache.h>
+#include <nand.h>
+#include <asm/mach-imx/dma.h>
+
+/**
+ * @gf_len:                   The length of Galois Field. (e.g., 13 or 14)
+ * @ecc_strength:             A number that describes the strength of the ECC
+ *                            algorithm.
+ * @ecc_chunk_size:           The size, in bytes, of a single ECC chunk. Note
+ *                            the first chunk in the page includes both data and
+ *                            metadata, so it's a bit larger than this value.
+ * @ecc_chunk_count:          The number of ECC chunks in the page,
+ * @block_mark_byte_offset:   The byte offset in the ECC-based page view at
+ *                            which the underlying physical block mark appears.
+ * @block_mark_bit_offset:    The bit offset into the ECC-based page view at
+ *                            which the underlying physical block mark appears.
+ */
+struct bch_geometry {
+	unsigned int  gf_len;
+	unsigned int  ecc_strength;
+	unsigned int  ecc_chunk_size;
+	unsigned int  ecc_chunk_count;
+	unsigned int  block_mark_byte_offset;
+	unsigned int  block_mark_bit_offset;
+};
+
+struct mxs_nand_info {
+	struct nand_chip chip;
+	struct udevice *dev;
+	unsigned int	max_ecc_strength_supported;
+	bool		use_minimum_ecc;
+	int		cur_chip;
+
+	uint32_t	cmd_queue_len;
+	uint32_t	data_buf_size;
+	struct bch_geometry bch_geometry;
+
+	uint8_t		*cmd_buf;
+	uint8_t		*data_buf;
+	uint8_t		*oob_buf;
+
+	uint8_t		marking_block_bad;
+	uint8_t		raw_oob_mode;
+
+	struct mxs_gpmi_regs *gpmi_regs;
+	struct mxs_bch_regs *bch_regs;
+
+	/* Functions with altered behaviour */
+	int		(*hooked_read_oob)(struct mtd_info *mtd,
+				loff_t from, struct mtd_oob_ops *ops);
+	int		(*hooked_write_oob)(struct mtd_info *mtd,
+				loff_t to, struct mtd_oob_ops *ops);
+	int		(*hooked_block_markbad)(struct mtd_info *mtd,
+				loff_t ofs);
+
+	/* DMA descriptors */
+	struct mxs_dma_desc	**desc;
+	uint32_t		desc_index;
+};
+
+int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info);
+int mxs_nand_init_spl(struct nand_chip *nand);
+int mxs_nand_setup_ecc(struct mtd_info *mtd);
diff --git a/include/nand.h b/include/nand.h
new file mode 100644
index 0000000..93cbe1e
--- /dev/null
+++ b/include/nand.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2005
+ * 2N Telekomunikace, a.s. <www.2n.cz>
+ * Ladislav Michl <michl@2n.cz>
+ */
+
+#ifndef _NAND_H_
+#define _NAND_H_
+
+#include <config.h>
+
+/*
+ * All boards using a given driver must convert to self-init
+ * at the same time, so do it here.  When all drivers are
+ * converted, this will go away.
+ */
+#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_FSL_IFC)
+#define CONFIG_SYS_NAND_SELF_INIT
+#endif
+#else
+#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
+	|| defined(CONFIG_NAND_FSL_IFC)
+#define CONFIG_SYS_NAND_SELF_INIT
+#endif
+#endif
+
+extern void nand_init(void);
+unsigned long nand_size(void);
+
+#include <linux/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+
+int nand_mtd_to_devnum(struct mtd_info *mtd);
+
+#ifdef CONFIG_SYS_NAND_SELF_INIT
+void board_nand_init(void);
+int nand_register(int devnum, struct mtd_info *mtd);
+#else
+extern int board_nand_init(struct nand_chip *nand);
+#endif
+
+extern int nand_curr_device;
+
+static inline int nand_read(struct mtd_info *info, loff_t ofs, size_t *len,
+			    u_char *buf)
+{
+	return mtd_read(info, ofs, *len, (size_t *)len, buf);
+}
+
+static inline int nand_write(struct mtd_info *info, loff_t ofs, size_t *len,
+			     u_char *buf)
+{
+	return mtd_write(info, ofs, *len, (size_t *)len, buf);
+}
+
+static inline int nand_block_isbad(struct mtd_info *info, loff_t ofs)
+{
+	return mtd_block_isbad(info, ofs);
+}
+
+static inline int nand_erase(struct mtd_info *info, loff_t off, size_t size)
+{
+	struct erase_info instr;
+
+	instr.mtd = info;
+	instr.addr = off;
+	instr.len = size;
+	instr.callback = 0;
+
+	return mtd_erase(info, &instr);
+}
+
+
+/*****************************************************************************
+ * declarations from nand_util.c
+ ****************************************************************************/
+
+typedef struct mtd_oob_ops mtd_oob_ops_t;
+
+struct nand_erase_options {
+	loff_t length;		/* number of bytes to erase */
+	loff_t offset;		/* first address in NAND to erase */
+	int quiet;		/* don't display progress messages */
+	int jffs2;		/* if true: format for jffs2 usage
+				 * (write appropriate cleanmarker blocks) */
+	int scrub;		/* if true, really clean NAND by erasing
+				 * bad blocks (UNSAFE) */
+
+	/* Don't include skipped bad blocks in size to be erased */
+	int spread;
+	/* maximum size that actual may be in order to not exceed the buf */
+	loff_t lim;
+};
+
+typedef struct nand_erase_options nand_erase_options_t;
+
+int nand_read_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
+		       size_t *actual, loff_t lim, u_char *buffer);
+
+#define WITH_DROP_FFS	(1 << 0) /* drop trailing all-0xff pages */
+#define WITH_WR_VERIFY	(1 << 1) /* verify data was written correctly */
+
+int nand_write_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
+			size_t *actual, loff_t lim, u_char *buffer, int flags);
+int nand_erase_opts(struct mtd_info *mtd,
+		    const nand_erase_options_t *opts);
+int nand_torture(struct mtd_info *mtd, loff_t offset);
+int nand_verify_page_oob(struct mtd_info *mtd, struct mtd_oob_ops *ops,
+			 loff_t ofs);
+int nand_verify(struct mtd_info *mtd, loff_t ofs, size_t len, u_char *buf);
+
+#define NAND_LOCK_STATUS_TIGHT	0x01
+#define NAND_LOCK_STATUS_UNLOCK 0x04
+
+int nand_lock(struct mtd_info *mtd, int tight);
+int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
+		int allexcept);
+int nand_get_lock_status(struct mtd_info *mtd, loff_t offset);
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
+int nand_spl_read_block(int block, int offset, int len, void *dst);
+void nand_deselect(void);
+
+#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
+void board_nand_select_device(struct nand_chip *nand, int chip);
+#endif
+
+__attribute__((noreturn)) void nand_boot(void);
+
+#ifdef CONFIG_ENV_OFFSET_OOB
+#define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored
+				    as block number*/
+#define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is
+					stored as byte number */
+#define ENV_OFFSET_SIZE 8
+int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result);
+#endif
+int spl_nand_erase_one(int block, int page);
+
+/* platform specific init functions */
+void sunxi_nand_init(void);
+
+/*
+ * get_nand_dev_by_index - Get the nand info based in index.
+ *
+ * @dev - index to the nand device.
+ *
+ * returns pointer to the nand device info structure or NULL on failure.
+ */
+struct mtd_info *get_nand_dev_by_index(int dev);
+
+#endif /* _NAND_H_ */
diff --git a/include/net.h b/include/net.h
new file mode 100644
index 0000000..75a16e4
--- /dev/null
+++ b/include/net.h
@@ -0,0 +1,889 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ *	LiMon Monitor (LiMon) - Network.
+ *
+ *	Copyright 1994 - 2000 Neil Russell.
+ *	(See License)
+ *
+ * History
+ *	9/16/00	  bor  adapted to TQM823L/STK8xxL board, RARP/TFTP boot added
+ */
+
+#ifndef __NET_H__
+#define __NET_H__
+
+#include <asm/cache.h>
+#include <asm/byteorder.h>	/* for nton* / ntoh* stuff */
+#include <env.h>
+#include <linux/if_ether.h>
+
+#define DEBUG_LL_STATE 0	/* Link local state machine changes */
+#define DEBUG_DEV_PKT 0		/* Packets or info directed to the device */
+#define DEBUG_NET_PKT 0		/* Packets on info on the network at large */
+#define DEBUG_INT_STATE 0	/* Internal network state changes */
+
+/*
+ *	The number of receive packet buffers, and the required packet buffer
+ *	alignment in memory.
+ *
+ */
+
+#ifdef CONFIG_SYS_RX_ETH_BUFFER
+# define PKTBUFSRX	CONFIG_SYS_RX_ETH_BUFFER
+#else
+# define PKTBUFSRX	4
+#endif
+
+#define PKTALIGN	ARCH_DMA_MINALIGN
+
+/* ARP hardware address length */
+#define ARP_HLEN 6
+/*
+ * The size of a MAC address in string form, each digit requires two chars
+ * and five separator characters to form '00:00:00:00:00:00'.
+ */
+#define ARP_HLEN_ASCII (ARP_HLEN * 2) + (ARP_HLEN - 1)
+
+/* IPv4 addresses are always 32 bits in size */
+struct in_addr {
+	__be32 s_addr;
+};
+
+/**
+ * An incoming packet handler.
+ * @param pkt    pointer to the application packet
+ * @param dport  destination UDP port
+ * @param sip    source IP address
+ * @param sport  source UDP port
+ * @param len    packet length
+ */
+typedef void rxhand_f(uchar *pkt, unsigned dport,
+		      struct in_addr sip, unsigned sport,
+		      unsigned len);
+
+/**
+ * An incoming ICMP packet handler.
+ * @param type	ICMP type
+ * @param code	ICMP code
+ * @param dport	destination UDP port
+ * @param sip	source IP address
+ * @param sport	source UDP port
+ * @param pkt	pointer to the ICMP packet data
+ * @param len	packet length
+ */
+typedef void rxhand_icmp_f(unsigned type, unsigned code, unsigned dport,
+		struct in_addr sip, unsigned sport, uchar *pkt, unsigned len);
+
+/*
+ *	A timeout handler.  Called after time interval has expired.
+ */
+typedef void	thand_f(void);
+
+enum eth_state_t {
+	ETH_STATE_INIT,
+	ETH_STATE_PASSIVE,
+	ETH_STATE_ACTIVE
+};
+
+#ifdef CONFIG_DM_ETH
+/**
+ * struct eth_pdata - Platform data for Ethernet MAC controllers
+ *
+ * @iobase: The base address of the hardware registers
+ * @enetaddr: The Ethernet MAC address that is loaded from EEPROM or env
+ * @phy_interface: PHY interface to use - see PHY_INTERFACE_MODE_...
+ * @max_speed: Maximum speed of Ethernet connection supported by MAC
+ * @priv_pdata: device specific platdata
+ */
+struct eth_pdata {
+	phys_addr_t iobase;
+	unsigned char enetaddr[ARP_HLEN];
+	int phy_interface;
+	int max_speed;
+	void *priv_pdata;
+};
+
+enum eth_recv_flags {
+	/*
+	 * Check hardware device for new packets (otherwise only return those
+	 * which are already in the memory buffer ready to process)
+	 */
+	ETH_RECV_CHECK_DEVICE		= 1 << 0,
+};
+
+/**
+ * struct eth_ops - functions of Ethernet MAC controllers
+ *
+ * start: Prepare the hardware to send and receive packets
+ * send: Send the bytes passed in "packet" as a packet on the wire
+ * recv: Check if the hardware received a packet. If so, set the pointer to the
+ *	 packet buffer in the packetp parameter. If not, return an error or 0 to
+ *	 indicate that the hardware receive FIFO is empty. If 0 is returned, the
+ *	 network stack will not process the empty packet, but free_pkt() will be
+ *	 called if supplied
+ * free_pkt: Give the driver an opportunity to manage its packet buffer memory
+ *	     when the network stack is finished processing it. This will only be
+ *	     called when no error was returned from recv - optional
+ * stop: Stop the hardware from looking for packets - may be called even if
+ *	 state == PASSIVE
+ * mcast: Join or leave a multicast group (for TFTP) - optional
+ * write_hwaddr: Write a MAC address to the hardware (used to pass it to Linux
+ *		 on some platforms like ARM). This function expects the
+ *		 eth_pdata::enetaddr field to be populated. The method can
+ *		 return -ENOSYS to indicate that this is not implemented for
+		 this hardware - optional.
+ * read_rom_hwaddr: Some devices have a backup of the MAC address stored in a
+ *		    ROM on the board. This is how the driver should expose it
+ *		    to the network stack. This function should fill in the
+ *		    eth_pdata::enetaddr field - optional
+ */
+struct eth_ops {
+	int (*start)(struct udevice *dev);
+	int (*send)(struct udevice *dev, void *packet, int length);
+	int (*recv)(struct udevice *dev, int flags, uchar **packetp);
+	int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
+	void (*stop)(struct udevice *dev);
+	int (*mcast)(struct udevice *dev, const u8 *enetaddr, int join);
+	int (*write_hwaddr)(struct udevice *dev);
+	int (*read_rom_hwaddr)(struct udevice *dev);
+};
+
+#define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops)
+
+struct udevice *eth_get_dev(void); /* get the current device */
+/*
+ * The devname can be either an exact name given by the driver or device tree
+ * or it can be an alias of the form "eth%d"
+ */
+struct udevice *eth_get_dev_by_name(const char *devname);
+unsigned char *eth_get_ethaddr(void); /* get the current device MAC */
+
+/* Used only when NetConsole is enabled */
+int eth_is_active(struct udevice *dev); /* Test device for active state */
+int eth_init_state_only(void); /* Set active state */
+void eth_halt_state_only(void); /* Set passive state */
+#endif
+
+#ifndef CONFIG_DM_ETH
+struct eth_device {
+#define ETH_NAME_LEN 20
+	char name[ETH_NAME_LEN];
+	unsigned char enetaddr[ARP_HLEN];
+	phys_addr_t iobase;
+	int state;
+
+	int (*init)(struct eth_device *, bd_t *);
+	int (*send)(struct eth_device *, void *packet, int length);
+	int (*recv)(struct eth_device *);
+	void (*halt)(struct eth_device *);
+	int (*mcast)(struct eth_device *, const u8 *enetaddr, int join);
+	int (*write_hwaddr)(struct eth_device *);
+	struct eth_device *next;
+	int index;
+	void *priv;
+};
+
+int eth_register(struct eth_device *dev);/* Register network device */
+int eth_unregister(struct eth_device *dev);/* Remove network device */
+
+extern struct eth_device *eth_current;
+
+static __always_inline struct eth_device *eth_get_dev(void)
+{
+	return eth_current;
+}
+struct eth_device *eth_get_dev_by_name(const char *devname);
+struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */
+
+/* get the current device MAC */
+static inline unsigned char *eth_get_ethaddr(void)
+{
+	if (eth_current)
+		return eth_current->enetaddr;
+	return NULL;
+}
+
+/* Used only when NetConsole is enabled */
+int eth_is_active(struct eth_device *dev); /* Test device for active state */
+/* Set active state */
+static __always_inline int eth_init_state_only(void)
+{
+	eth_get_dev()->state = ETH_STATE_ACTIVE;
+
+	return 0;
+}
+/* Set passive state */
+static __always_inline void eth_halt_state_only(void)
+{
+	eth_get_dev()->state = ETH_STATE_PASSIVE;
+}
+
+/*
+ * Set the hardware address for an ethernet interface based on 'eth%daddr'
+ * environment variable (or just 'ethaddr' if eth_number is 0).
+ * Args:
+ *	base_name - base name for device (normally "eth")
+ *	eth_number - value of %d (0 for first device of this type)
+ * Returns:
+ *	0 is success, non-zero is error status from driver.
+ */
+int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
+		     int eth_number);
+
+int usb_eth_initialize(bd_t *bi);
+#endif
+
+int eth_initialize(void);		/* Initialize network subsystem */
+void eth_try_another(int first_restart);	/* Change the device */
+void eth_set_current(void);		/* set nterface to ethcur var */
+
+int eth_get_dev_index(void);		/* get the device index */
+
+/**
+ * eth_env_set_enetaddr_by_index() - set the MAC address environment variable
+ *
+ * This sets up an environment variable with the given MAC address (@enetaddr).
+ * The environment variable to be set is defined by <@base_name><@index>addr.
+ * If @index is 0 it is omitted. For common Ethernet this means ethaddr,
+ * eth1addr, etc.
+ *
+ * @base_name:  Base name for variable, typically "eth"
+ * @index:      Index of interface being updated (>=0)
+ * @enetaddr:   Pointer to MAC address to put into the variable
+ * @return 0 if OK, other value on error
+ */
+int eth_env_set_enetaddr_by_index(const char *base_name, int index,
+				 uchar *enetaddr);
+
+
+/*
+ * Initialize USB ethernet device with CONFIG_DM_ETH
+ * Returns:
+ *	0 is success, non-zero is error status.
+ */
+int usb_ether_init(void);
+
+/*
+ * Get the hardware address for an ethernet interface .
+ * Args:
+ *	base_name - base name for device (normally "eth")
+ *	index - device index number (0 for first)
+ *	enetaddr - returns 6 byte hardware address
+ * Returns:
+ *	Return true if the address is valid.
+ */
+int eth_env_get_enetaddr_by_index(const char *base_name, int index,
+				 uchar *enetaddr);
+
+int eth_init(void);			/* Initialize the device */
+int eth_send(void *packet, int length);	   /* Send a packet */
+
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
+int eth_receive(void *packet, int length); /* Receive a packet*/
+extern void (*push_packet)(void *packet, int length);
+#endif
+int eth_rx(void);			/* Check for received packets */
+void eth_halt(void);			/* stop SCC */
+const char *eth_get_name(void);		/* get name of current device */
+int eth_mcast_join(struct in_addr mcast_addr, int join);
+
+/**********************************************************************/
+/*
+ *	Protocol headers.
+ */
+
+/*
+ *	Ethernet header
+ */
+
+struct ethernet_hdr {
+	u8		et_dest[ARP_HLEN];	/* Destination node	*/
+	u8		et_src[ARP_HLEN];	/* Source node		*/
+	u16		et_protlen;		/* Protocol or length	*/
+} __attribute__((packed));
+
+/* Ethernet header size */
+#define ETHER_HDR_SIZE	(sizeof(struct ethernet_hdr))
+
+#define ETH_FCS_LEN	4		/* Octets in the FCS		*/
+
+struct e802_hdr {
+	u8		et_dest[ARP_HLEN];	/* Destination node	*/
+	u8		et_src[ARP_HLEN];	/* Source node		*/
+	u16		et_protlen;		/* Protocol or length	*/
+	u8		et_dsap;		/* 802 DSAP		*/
+	u8		et_ssap;		/* 802 SSAP		*/
+	u8		et_ctl;			/* 802 control		*/
+	u8		et_snap1;		/* SNAP			*/
+	u8		et_snap2;
+	u8		et_snap3;
+	u16		et_prot;		/* 802 protocol		*/
+} __attribute__((packed));
+
+/* 802 + SNAP + ethernet header size */
+#define E802_HDR_SIZE	(sizeof(struct e802_hdr))
+
+/*
+ *	Virtual LAN Ethernet header
+ */
+struct vlan_ethernet_hdr {
+	u8		vet_dest[ARP_HLEN];	/* Destination node	*/
+	u8		vet_src[ARP_HLEN];	/* Source node		*/
+	u16		vet_vlan_type;		/* PROT_VLAN		*/
+	u16		vet_tag;		/* TAG of VLAN		*/
+	u16		vet_type;		/* protocol type	*/
+} __attribute__((packed));
+
+/* VLAN Ethernet header size */
+#define VLAN_ETHER_HDR_SIZE	(sizeof(struct vlan_ethernet_hdr))
+
+#define PROT_IP		0x0800		/* IP protocol			*/
+#define PROT_ARP	0x0806		/* IP ARP protocol		*/
+#define PROT_WOL	0x0842		/* ether-wake WoL protocol	*/
+#define PROT_RARP	0x8035		/* IP ARP protocol		*/
+#define PROT_VLAN	0x8100		/* IEEE 802.1q protocol		*/
+#define PROT_IPV6	0x86dd		/* IPv6 over bluebook		*/
+#define PROT_PPP_SES	0x8864		/* PPPoE session messages	*/
+
+#define IPPROTO_ICMP	 1	/* Internet Control Message Protocol	*/
+#define IPPROTO_UDP	17	/* User Datagram Protocol		*/
+
+/*
+ *	Internet Protocol (IP) header.
+ */
+struct ip_hdr {
+	u8		ip_hl_v;	/* header length and version	*/
+	u8		ip_tos;		/* type of service		*/
+	u16		ip_len;		/* total length			*/
+	u16		ip_id;		/* identification		*/
+	u16		ip_off;		/* fragment offset field	*/
+	u8		ip_ttl;		/* time to live			*/
+	u8		ip_p;		/* protocol			*/
+	u16		ip_sum;		/* checksum			*/
+	struct in_addr	ip_src;		/* Source IP address		*/
+	struct in_addr	ip_dst;		/* Destination IP address	*/
+} __attribute__((packed));
+
+#define IP_OFFS		0x1fff /* ip offset *= 8 */
+#define IP_FLAGS	0xe000 /* first 3 bits */
+#define IP_FLAGS_RES	0x8000 /* reserved */
+#define IP_FLAGS_DFRAG	0x4000 /* don't fragments */
+#define IP_FLAGS_MFRAG	0x2000 /* more fragments */
+
+#define IP_HDR_SIZE		(sizeof(struct ip_hdr))
+
+/*
+ *	Internet Protocol (IP) + UDP header.
+ */
+struct ip_udp_hdr {
+	u8		ip_hl_v;	/* header length and version	*/
+	u8		ip_tos;		/* type of service		*/
+	u16		ip_len;		/* total length			*/
+	u16		ip_id;		/* identification		*/
+	u16		ip_off;		/* fragment offset field	*/
+	u8		ip_ttl;		/* time to live			*/
+	u8		ip_p;		/* protocol			*/
+	u16		ip_sum;		/* checksum			*/
+	struct in_addr	ip_src;		/* Source IP address		*/
+	struct in_addr	ip_dst;		/* Destination IP address	*/
+	u16		udp_src;	/* UDP source port		*/
+	u16		udp_dst;	/* UDP destination port		*/
+	u16		udp_len;	/* Length of UDP packet		*/
+	u16		udp_xsum;	/* Checksum			*/
+} __attribute__((packed));
+
+#define IP_UDP_HDR_SIZE		(sizeof(struct ip_udp_hdr))
+#define UDP_HDR_SIZE		(IP_UDP_HDR_SIZE - IP_HDR_SIZE)
+
+/*
+ *	Address Resolution Protocol (ARP) header.
+ */
+struct arp_hdr {
+	u16		ar_hrd;		/* Format of hardware address	*/
+#   define ARP_ETHER	    1		/* Ethernet  hardware address	*/
+	u16		ar_pro;		/* Format of protocol address	*/
+	u8		ar_hln;		/* Length of hardware address	*/
+	u8		ar_pln;		/* Length of protocol address	*/
+#   define ARP_PLEN	4
+	u16		ar_op;		/* Operation			*/
+#   define ARPOP_REQUEST    1		/* Request  to resolve  address	*/
+#   define ARPOP_REPLY	    2		/* Response to previous request	*/
+
+#   define RARPOP_REQUEST   3		/* Request  to resolve  address	*/
+#   define RARPOP_REPLY	    4		/* Response to previous request */
+
+	/*
+	 * The remaining fields are variable in size, according to
+	 * the sizes above, and are defined as appropriate for
+	 * specific hardware/protocol combinations.
+	 */
+	u8		ar_data[0];
+#define ar_sha		ar_data[0]
+#define ar_spa		ar_data[ARP_HLEN]
+#define ar_tha		ar_data[ARP_HLEN + ARP_PLEN]
+#define ar_tpa		ar_data[ARP_HLEN + ARP_PLEN + ARP_HLEN]
+#if 0
+	u8		ar_sha[];	/* Sender hardware address	*/
+	u8		ar_spa[];	/* Sender protocol address	*/
+	u8		ar_tha[];	/* Target hardware address	*/
+	u8		ar_tpa[];	/* Target protocol address	*/
+#endif /* 0 */
+} __attribute__((packed));
+
+#define ARP_HDR_SIZE	(8+20)		/* Size assuming ethernet	*/
+
+/*
+ * ICMP stuff (just enough to handle (host) redirect messages)
+ */
+#define ICMP_ECHO_REPLY		0	/* Echo reply			*/
+#define ICMP_NOT_REACH		3	/* Detination unreachable	*/
+#define ICMP_REDIRECT		5	/* Redirect (change route)	*/
+#define ICMP_ECHO_REQUEST	8	/* Echo request			*/
+
+/* Codes for REDIRECT. */
+#define ICMP_REDIR_NET		0	/* Redirect Net			*/
+#define ICMP_REDIR_HOST		1	/* Redirect Host		*/
+
+/* Codes for NOT_REACH */
+#define ICMP_NOT_REACH_PORT	3	/* Port unreachable		*/
+
+struct icmp_hdr {
+	u8		type;
+	u8		code;
+	u16		checksum;
+	union {
+		struct {
+			u16	id;
+			u16	sequence;
+		} echo;
+		u32	gateway;
+		struct {
+			u16	unused;
+			u16	mtu;
+		} frag;
+		u8 data[0];
+	} un;
+} __attribute__((packed));
+
+#define ICMP_HDR_SIZE		(sizeof(struct icmp_hdr))
+#define IP_ICMP_HDR_SIZE	(IP_HDR_SIZE + ICMP_HDR_SIZE)
+
+/*
+ * Maximum packet size; used to allocate packet storage. Use
+ * the maxium Ethernet frame size as specified by the Ethernet
+ * standard including the 802.1Q tag (VLAN tagging).
+ * maximum packet size =  1522
+ * maximum packet size and multiple of 32 bytes =  1536
+ */
+#define PKTSIZE			1522
+#define PKTSIZE_ALIGN		1536
+
+/*
+ * Maximum receive ring size; that is, the number of packets
+ * we can buffer before overflow happens. Basically, this just
+ * needs to be enough to prevent a packet being discarded while
+ * we are processing the previous one.
+ */
+#define RINGSZ		4
+#define RINGSZ_LOG2	2
+
+/**********************************************************************/
+/*
+ *	Globals.
+ *
+ * Note:
+ *
+ * All variables of type struct in_addr are stored in NETWORK byte order
+ * (big endian).
+ */
+
+/* net.c */
+/** BOOTP EXTENTIONS **/
+extern struct in_addr net_gateway;	/* Our gateway IP address */
+extern struct in_addr net_netmask;	/* Our subnet mask (0 = unknown) */
+/* Our Domain Name Server (0 = unknown) */
+extern struct in_addr net_dns_server;
+#if defined(CONFIG_BOOTP_DNS2)
+/* Our 2nd Domain Name Server (0 = unknown) */
+extern struct in_addr net_dns_server2;
+#endif
+extern char	net_nis_domain[32];	/* Our IS domain */
+extern char	net_hostname[32];	/* Our hostname */
+extern char	net_root_path[64];	/* Our root path */
+/** END OF BOOTP EXTENTIONS **/
+extern u8		net_ethaddr[ARP_HLEN];		/* Our ethernet address */
+extern u8		net_server_ethaddr[ARP_HLEN];	/* Boot server enet address */
+extern struct in_addr	net_ip;		/* Our    IP addr (0 = unknown) */
+extern struct in_addr	net_server_ip;	/* Server IP addr (0 = unknown) */
+extern uchar		*net_tx_packet;		/* THE transmit packet */
+extern uchar		*net_rx_packets[PKTBUFSRX]; /* Receive packets */
+extern uchar		*net_rx_packet;		/* Current receive packet */
+extern int		net_rx_packet_len;	/* Current rx packet length */
+extern const u8		net_bcast_ethaddr[ARP_HLEN];	/* Ethernet broadcast address */
+extern const u8		net_null_ethaddr[ARP_HLEN];
+
+#define VLAN_NONE	4095			/* untagged */
+#define VLAN_IDMASK	0x0fff			/* mask of valid vlan id */
+extern ushort		net_our_vlan;		/* Our VLAN */
+extern ushort		net_native_vlan;	/* Our Native VLAN */
+
+extern int		net_restart_wrap;	/* Tried all network devices */
+
+enum proto_t {
+	BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
+	TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL
+};
+
+extern char	net_boot_file_name[1024];/* Boot File name */
+/* Indicates whether the file name was specified on the command line */
+extern bool	net_boot_file_name_explicit;
+/* The actual transferred size of the bootfile (in bytes) */
+extern u32	net_boot_file_size;
+/* Boot file size in blocks as reported by the DHCP server */
+extern u32	net_boot_file_expected_size_in_blocks;
+
+#if defined(CONFIG_CMD_DNS)
+extern char *net_dns_resolve;		/* The host to resolve  */
+extern char *net_dns_env_var;		/* the env var to put the ip into */
+#endif
+
+#if defined(CONFIG_CMD_PING)
+extern struct in_addr net_ping_ip;	/* the ip address to ping */
+#endif
+
+#if defined(CONFIG_CMD_CDP)
+/* when CDP completes these hold the return values */
+extern ushort cdp_native_vlan;		/* CDP returned native VLAN */
+extern ushort cdp_appliance_vlan;	/* CDP returned appliance VLAN */
+
+/*
+ * Check for a CDP packet by examining the received MAC address field
+ */
+static inline int is_cdp_packet(const uchar *ethaddr)
+{
+	extern const u8 net_cdp_ethaddr[ARP_HLEN];
+
+	return memcmp(ethaddr, net_cdp_ethaddr, ARP_HLEN) == 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_SNTP)
+extern struct in_addr	net_ntp_server;		/* the ip address to NTP */
+extern int net_ntp_time_offset;			/* offset time from UTC */
+#endif
+
+/* Initialize the network adapter */
+void net_init(void);
+int net_loop(enum proto_t);
+
+/* Load failed.	 Start again. */
+int net_start_again(void);
+
+/* Get size of the ethernet header when we send */
+int net_eth_hdr_size(void);
+
+/* Set ethernet header; returns the size of the header */
+int net_set_ether(uchar *xet, const uchar *dest_ethaddr, uint prot);
+int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot);
+
+/* Set IP header */
+void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source,
+		       u16 pkt_len, u8 proto);
+void net_set_udp_header(uchar *pkt, struct in_addr dest, int dport,
+				int sport, int len);
+
+/**
+ * compute_ip_checksum() - Compute IP checksum
+ *
+ * @addr:	Address to check (must be 16-bit aligned)
+ * @nbytes:	Number of bytes to check (normally a multiple of 2)
+ * @return 16-bit IP checksum
+ */
+unsigned compute_ip_checksum(const void *addr, unsigned nbytes);
+
+/**
+ * add_ip_checksums() - add two IP checksums
+ *
+ * @offset:	Offset of first sum (if odd we do a byte-swap)
+ * @sum:	First checksum
+ * @new_sum:	New checksum to add
+ * @return updated 16-bit IP checksum
+ */
+unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned new_sum);
+
+/**
+ * ip_checksum_ok() - check if a checksum is correct
+ *
+ * This works by making sure the checksum sums to 0
+ *
+ * @addr:	Address to check (must be 16-bit aligned)
+ * @nbytes:	Number of bytes to check (normally a multiple of 2)
+ * @return true if the checksum matches, false if not
+ */
+int ip_checksum_ok(const void *addr, unsigned nbytes);
+
+/* Callbacks */
+rxhand_f *net_get_udp_handler(void);	/* Get UDP RX packet handler */
+void net_set_udp_handler(rxhand_f *);	/* Set UDP RX packet handler */
+rxhand_f *net_get_arp_handler(void);	/* Get ARP RX packet handler */
+void net_set_arp_handler(rxhand_f *);	/* Set ARP RX packet handler */
+bool arp_is_waiting(void);		/* Waiting for ARP reply? */
+void net_set_icmp_handler(rxhand_icmp_f *f); /* Set ICMP RX handler */
+void net_set_timeout_handler(ulong, thand_f *);/* Set timeout handler */
+
+/* Network loop state */
+enum net_loop_state {
+	NETLOOP_CONTINUE,
+	NETLOOP_RESTART,
+	NETLOOP_SUCCESS,
+	NETLOOP_FAIL
+};
+extern enum net_loop_state net_state;
+
+static inline void net_set_state(enum net_loop_state state)
+{
+	debug_cond(DEBUG_INT_STATE, "--- NetState set to %d\n", state);
+	net_state = state;
+}
+
+/*
+ * net_get_async_tx_pkt_buf - Get a packet buffer that is not in use for
+ *			      sending an asynchronous reply
+ *
+ * returns - ptr to packet buffer
+ */
+uchar * net_get_async_tx_pkt_buf(void);
+
+/* Transmit a packet */
+static inline void net_send_packet(uchar *pkt, int len)
+{
+	/* Currently no way to return errors from eth_send() */
+	(void) eth_send(pkt, len);
+}
+
+/*
+ * Transmit "net_tx_packet" as UDP packet, performing ARP request if needed
+ *  (ether will be populated)
+ *
+ * @param ether Raw packet buffer
+ * @param dest IP address to send the datagram to
+ * @param dport Destination UDP port
+ * @param sport Source UDP port
+ * @param payload_len Length of data after the UDP header
+ */
+int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport,
+		       int payload_len, int proto, u8 action, u32 tcp_seq_num,
+		       u32 tcp_ack_num);
+int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport,
+			int sport, int payload_len);
+
+/* Processes a received packet */
+void net_process_received_packet(uchar *in_packet, int len);
+
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD)
+void nc_start(void);
+int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port,
+	unsigned src_port, unsigned len);
+#endif
+
+static __always_inline int eth_is_on_demand_init(void)
+{
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD)
+	extern enum proto_t net_loop_last_protocol;
+
+	return net_loop_last_protocol != NETCONS;
+#else
+	return 1;
+#endif
+}
+
+static inline void eth_set_last_protocol(int protocol)
+{
+#if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_SPL_BUILD)
+	extern enum proto_t net_loop_last_protocol;
+
+	net_loop_last_protocol = protocol;
+#endif
+}
+
+/*
+ * Check if autoload is enabled. If so, use either NFS or TFTP to download
+ * the boot file.
+ */
+void net_auto_load(void);
+
+/*
+ * The following functions are a bit ugly, but necessary to deal with
+ * alignment restrictions on ARM.
+ *
+ * We're using inline functions, which had the smallest memory
+ * footprint in our tests.
+ */
+/* return IP *in network byteorder* */
+static inline struct in_addr net_read_ip(void *from)
+{
+	struct in_addr ip;
+
+	memcpy((void *)&ip, (void *)from, sizeof(ip));
+	return ip;
+}
+
+/* return ulong *in network byteorder* */
+static inline u32 net_read_u32(void *from)
+{
+	u32 l;
+
+	memcpy((void *)&l, (void *)from, sizeof(l));
+	return l;
+}
+
+/* write IP *in network byteorder* */
+static inline void net_write_ip(void *to, struct in_addr ip)
+{
+	memcpy(to, (void *)&ip, sizeof(ip));
+}
+
+/* copy IP */
+static inline void net_copy_ip(void *to, void *from)
+{
+	memcpy((void *)to, from, sizeof(struct in_addr));
+}
+
+/* copy ulong */
+static inline void net_copy_u32(void *to, void *from)
+{
+	memcpy((void *)to, (void *)from, sizeof(u32));
+}
+
+/**
+ * is_zero_ethaddr - Determine if give Ethernet address is all zeros.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is all zeroes.
+ */
+static inline int is_zero_ethaddr(const u8 *addr)
+{
+	return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
+}
+
+/**
+ * is_multicast_ethaddr - Determine if the Ethernet address is a multicast.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is a multicast address.
+ * By definition the broadcast address is also a multicast address.
+ */
+static inline int is_multicast_ethaddr(const u8 *addr)
+{
+	return 0x01 & addr[0];
+}
+
+/*
+ * is_broadcast_ethaddr - Determine if the Ethernet address is broadcast
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is the broadcast address.
+ */
+static inline int is_broadcast_ethaddr(const u8 *addr)
+{
+	return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) ==
+		0xff;
+}
+
+/*
+ * is_valid_ethaddr - Determine if the given Ethernet address is valid
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
+ * a multicast address, and is not FF:FF:FF:FF:FF:FF.
+ *
+ * Return true if the address is valid.
+ */
+static inline int is_valid_ethaddr(const u8 *addr)
+{
+	/* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
+	 * explicitly check for it here. */
+	return !is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr);
+}
+
+/**
+ * net_random_ethaddr - Generate software assigned random Ethernet address
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Generate a random Ethernet address (MAC) that is not multicast
+ * and has the local assigned bit set.
+ */
+static inline void net_random_ethaddr(uchar *addr)
+{
+	int i;
+	unsigned int seed = get_ticks();
+
+	for (i = 0; i < 6; i++)
+		addr[i] = rand_r(&seed);
+
+	addr[0] &= 0xfe;	/* clear multicast bit */
+	addr[0] |= 0x02;	/* set local assignment bit (IEEE802) */
+}
+
+/* Convert an IP address to a string */
+void ip_to_string(struct in_addr x, char *s);
+
+/* Convert a string to ip address */
+struct in_addr string_to_ip(const char *s);
+
+/* Convert a VLAN id to a string */
+void vlan_to_string(ushort x, char *s);
+
+/* Convert a string to a vlan id */
+ushort string_to_vlan(const char *s);
+
+/* read a VLAN id from an environment variable */
+ushort env_get_vlan(char *);
+
+/* copy a filename (allow for "..." notation, limit length) */
+void copy_filename(char *dst, const char *src, int size);
+
+/* check if serverip is specified in filename from the command line */
+int is_serverip_in_cmd(void);
+
+/**
+ * net_parse_bootfile - Parse the bootfile env var / cmd line param
+ *
+ * @param ipaddr - a pointer to the ipaddr to populate if included in bootfile
+ * @param filename - a pointer to the string to save the filename part
+ * @param max_len - The longest - 1 that the filename part can be
+ *
+ * return 1 if parsed, 0 if bootfile is empty
+ */
+int net_parse_bootfile(struct in_addr *ipaddr, char *filename, int max_len);
+
+/* get a random source port */
+unsigned int random_port(void);
+
+/**
+ * update_tftp - Update firmware over TFTP (via DFU)
+ *
+ * This function updates board's firmware via TFTP
+ *
+ * @param addr - memory address where data is stored
+ * @param interface - the DFU medium name - e.g. "mmc"
+ * @param devstring - the DFU medium number - e.g. "1"
+ *
+ * @return - 0 on success, other value on failure
+ */
+int update_tftp(ulong addr, char *interface, char *devstring);
+
+/**********************************************************************/
+
+/**
+ * eth_parse_enetaddr() - Parse a MAC address
+ *
+ * Convert a string MAC address
+ *
+ * @addr: MAC address in aa:bb:cc:dd:ee:ff format, where each part is a 2-digit
+ *	hex value
+ * @enetaddr: Place to put MAC address (6 bytes)
+ */
+void eth_parse_enetaddr(const char *addr, uint8_t *enetaddr);
+
+#endif /* __NET_H__ */
diff --git a/include/net/fastboot.h b/include/net/fastboot.h
new file mode 100644
index 0000000..6860209
--- /dev/null
+++ b/include/net/fastboot.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2016 The Android Open Source Project
+ */
+
+#ifndef __NET_FASTBOOT_H__
+#define __NET_FASTBOOT_H__
+
+/**********************************************************************/
+/*
+ *	Global functions and variables.
+ */
+
+/**
+ * Wait for incoming fastboot comands.
+ */
+void fastboot_start_server(void);
+
+/**********************************************************************/
+
+#endif /* __NET_FASTBOOT_H__ */
diff --git a/include/net/pcap.h b/include/net/pcap.h
new file mode 100644
index 0000000..512ba98
--- /dev/null
+++ b/include/net/pcap.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019
+ * Ramon Fried <rfried.dev@gmail.com>
+ */
+
+/**
+ * pcap_init() - Initialize PCAP memory buffer
+ *
+ * @paddr	physicaly memory address to store buffer
+ * @size	maximum size of capture file in memory
+ *
+ * @return	0 on success, -ERROR on error
+ */
+int pcap_init(phys_addr_t paddr, unsigned long size);
+
+/**
+ * pcap_start_stop() - start / stop pcap capture
+ *
+ * @start	if true, start capture if false stop capture
+ *
+ * @return	0 on success, -ERROR on error
+ */
+int pcap_start_stop(bool start);
+
+/**
+ * pcap_clear() - clear pcap capture buffer and statistics
+ *
+ * @return	0 on success, -ERROR on error
+ */
+int pcap_clear(void);
+
+/**
+ * pcap_print_status() - print status of pcap capture
+ *
+ * @return	0 on success, -ERROR on error
+ */
+int pcap_print_status(void);
+
+/**
+ * pcap_active() - check if pcap is enabled
+ *
+ * @return	TRUE if active, FALSE if not.
+ */
+bool pcap_active(void);
+
+/**
+ * pcap_post() - Post a packet to PCAP file
+ *
+ * @packet:	packet to post
+ * @len:	packet length in bytes
+ * @outgoing	packet direction (outgoing/incoming)
+ * @return	0 on success, -ERROR on error
+ */
+int pcap_post(const void *packet, size_t len, bool outgoing);
diff --git a/include/net/pfe_eth/pfe/cbus.h b/include/net/pfe_eth/pfe/cbus.h
new file mode 100644
index 0000000..e8e9f34
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _CBUS_H_
+#define _CBUS_H_
+
+#include "cbus/emac.h"
+#include "cbus/gpi.h"
+#include "cbus/bmu.h"
+#include "cbus/hif.h"
+#include "cbus/tmu_csr.h"
+#include "cbus/class_csr.h"
+#include "cbus/hif_nocpy.h"
+#include "cbus/util_csr.h"
+
+#define CBUS_BASE_ADDR		((void *)CONFIG_SYS_FSL_PFE_ADDR)
+
+/* PFE Control and Status Register Desciption */
+#define EMAC1_BASE_ADDR		(CBUS_BASE_ADDR + 0x200000)
+#define EGPI1_BASE_ADDR		(CBUS_BASE_ADDR + 0x210000)
+#define EMAC2_BASE_ADDR		(CBUS_BASE_ADDR + 0x220000)
+#define EGPI2_BASE_ADDR		(CBUS_BASE_ADDR + 0x230000)
+#define BMU1_BASE_ADDR		(CBUS_BASE_ADDR + 0x240000)
+#define BMU2_BASE_ADDR		(CBUS_BASE_ADDR + 0x250000)
+#define ARB_BASE_ADDR		(CBUS_BASE_ADDR + 0x260000)
+#define DDR_CONFIG_BASE_ADDR	(CBUS_BASE_ADDR + 0x270000)
+#define HIF_BASE_ADDR		(CBUS_BASE_ADDR + 0x280000)
+#define HGPI_BASE_ADDR		(CBUS_BASE_ADDR + 0x290000)
+#define LMEM_BASE_ADDR		(CBUS_BASE_ADDR + 0x300000)
+#define LMEM_SIZE		0x10000
+#define LMEM_END		(LMEM_BASE_ADDR + LMEM_SIZE)
+#define TMU_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x310000)
+#define CLASS_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x320000)
+#define HIF_NOCPY_BASE_ADDR	(CBUS_BASE_ADDR + 0x350000)
+#define UTIL_CSR_BASE_ADDR	(CBUS_BASE_ADDR + 0x360000)
+#define CBUS_GPT_BASE_ADDR	(CBUS_BASE_ADDR + 0x370000)
+
+/*
+ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
+ * XXX_MEM_ACCESS_ADDR register bit definitions.
+ */
+/* Internal Memory Write. */
+#define PE_MEM_ACCESS_WRITE		BIT(31)
+/* Internal Memory Read. */
+#define PE_MEM_ACCESS_READ		(0 << 31)
+
+#define PE_MEM_ACCESS_IMEM		BIT(15)
+#define PE_MEM_ACCESS_DMEM		BIT(16)
+
+/* Byte Enables of the Internal memory access. These are interpred in BE */
+#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size)	(((((1 << (size)) - 1) << (4 \
+							- (offset) - (size)))\
+							& 0xf) << 24)
+
+/* PFE cores states */
+#define CORE_DISABLE	0x00000000
+#define CORE_ENABLE	0x00000001
+#define CORE_SW_RESET	0x00000002
+
+/* LMEM defines */
+#define LMEM_HDR_SIZE		0x0010
+#define LMEM_BUF_SIZE_LN2	0x7
+#define LMEM_BUF_SIZE		BIT(LMEM_BUF_SIZE_LN2)
+
+/* DDR defines */
+#define DDR_HDR_SIZE		0x0100
+#define DDR_BUF_SIZE_LN2	0xb
+#define DDR_BUF_SIZE		BIT(DDR_BUF_SIZE_LN2)
+
+/* Clock generation through PLL */
+#define PLL_CLK_EN	1
+
+#endif /* _CBUS_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/bmu.h b/include/net/pfe_eth/pfe/cbus/bmu.h
new file mode 100644
index 0000000..3a83e4d
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/bmu.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _BMU_H_
+#define _BMU_H_
+
+#define BMU_VERSION		0x000
+#define BMU_CTRL		0x004
+#define BMU_UCAST_CONFIG	0x008
+#define BMU_UCAST_BASE_ADDR	0x00c
+#define BMU_BUF_SIZE		0x010
+#define BMU_BUF_CNT		0x014
+#define BMU_THRES		0x018
+#define BMU_INT_SRC		0x020
+#define BMU_INT_ENABLE		0x024
+#define BMU_ALLOC_CTRL		0x030
+#define BMU_FREE_CTRL		0x034
+#define BMU_FREE_ERR_ADDR	0x038
+#define BMU_CURR_BUF_CNT	0x03c
+#define BMU_MCAST_CNT		0x040
+#define BMU_MCAST_ALLOC_CTRL	0x044
+#define BMU_REM_BUF_CNT		0x048
+#define BMU_LOW_WATERMARK	0x050
+#define BMU_HIGH_WATERMARK	0x054
+#define BMU_INT_MEM_ACCESS	0x100
+
+struct bmu_cfg {
+	u32 baseaddr;
+	u32 count;
+	u32 size;
+};
+
+#define BMU1_BUF_SIZE	LMEM_BUF_SIZE_LN2
+#define BMU2_BUF_SIZE	DDR_BUF_SIZE_LN2
+
+#endif /* _BMU_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/class_csr.h b/include/net/pfe_eth/pfe/cbus/class_csr.h
new file mode 100644
index 0000000..e2fece7
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/class_csr.h
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _CLASS_CSR_H_
+#define _CLASS_CSR_H_
+
+/*
+ * @file class_csr.h.
+ * class_csr - block containing all the classifier control and status register.
+ * Mapped on CBUS and accessible from all PE's and ARM.
+ */
+#define CLASS_VERSION			(CLASS_CSR_BASE_ADDR + 0x000)
+#define CLASS_TX_CTRL			(CLASS_CSR_BASE_ADDR + 0x004)
+#define CLASS_INQ_PKTPTR		(CLASS_CSR_BASE_ADDR + 0x010)
+/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
+#define CLASS_HDR_SIZE			(CLASS_CSR_BASE_ADDR + 0x014)
+/* LMEM header size for the Classifier block.
+ * Data in the LMEM is written from this offset.
+ */
+#define CLASS_HDR_SIZE_LMEM(off)	((off) & 0x3f)
+/* DDR header size for the Classifier block.
+ * Data in the DDR is written from this offset.
+ */
+#define CLASS_HDR_SIZE_DDR(off)		(((off) & 0x1ff) << 16)
+
+/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
+#define CLASS_PE0_QB_DM_ADDR0		(CLASS_CSR_BASE_ADDR + 0x020)
+/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
+#define CLASS_PE0_QB_DM_ADDR1		(CLASS_CSR_BASE_ADDR + 0x024)
+
+/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
+#define CLASS_PE0_RO_DM_ADDR0		(CLASS_CSR_BASE_ADDR + 0x060)
+/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
+#define CLASS_PE0_RO_DM_ADDR1		(CLASS_CSR_BASE_ADDR + 0x064)
+
+/*
+ * @name Class PE memory access. Allows external PE's and HOST to
+ * read/write PMEM/DMEM memory ranges for each classifier PE.
+ */
+#define CLASS_MEM_ACCESS_ADDR		(CLASS_CSR_BASE_ADDR + 0x100)
+/* Internal Memory Access Write Data [31:0] */
+#define CLASS_MEM_ACCESS_WDATA		(CLASS_CSR_BASE_ADDR + 0x104)
+/* Internal Memory Access Read Data [31:0] */
+#define CLASS_MEM_ACCESS_RDATA		(CLASS_CSR_BASE_ADDR + 0x108)
+#define CLASS_TM_INQ_ADDR		(CLASS_CSR_BASE_ADDR + 0x114)
+#define CLASS_PE_STATUS			(CLASS_CSR_BASE_ADDR + 0x118)
+
+#define CLASS_PE_SYS_CLK_RATIO		(CLASS_CSR_BASE_ADDR + 0x200)
+#define CLASS_AFULL_THRES		(CLASS_CSR_BASE_ADDR + 0x204)
+#define CLASS_GAP_BETWEEN_READS		(CLASS_CSR_BASE_ADDR + 0x208)
+#define CLASS_MAX_BUF_CNT		(CLASS_CSR_BASE_ADDR + 0x20c)
+#define CLASS_TSQ_FIFO_THRES		(CLASS_CSR_BASE_ADDR + 0x210)
+#define CLASS_TSQ_MAX_CNT		(CLASS_CSR_BASE_ADDR + 0x214)
+#define CLASS_IRAM_DATA_0		(CLASS_CSR_BASE_ADDR + 0x218)
+#define CLASS_IRAM_DATA_1		(CLASS_CSR_BASE_ADDR + 0x21c)
+#define CLASS_IRAM_DATA_2		(CLASS_CSR_BASE_ADDR + 0x220)
+#define CLASS_IRAM_DATA_3		(CLASS_CSR_BASE_ADDR + 0x224)
+
+#define CLASS_BUS_ACCESS_ADDR		(CLASS_CSR_BASE_ADDR + 0x228)
+/* bit 23:0 of PE peripheral address are stored in CLASS_BUS_ACCESS_ADDR */
+#define CLASS_BUS_ACCESS_ADDR_MASK	(0x0001FFFF)
+
+#define CLASS_BUS_ACCESS_WDATA		(CLASS_CSR_BASE_ADDR + 0x22c)
+#define CLASS_BUS_ACCESS_RDATA		(CLASS_CSR_BASE_ADDR + 0x230)
+
+/*
+ * (route_entry_size[9:0], route_hash_size[23:16]
+ * (this is actually ln2(size)))
+ */
+#define CLASS_ROUTE_HASH_ENTRY_SIZE	(CLASS_CSR_BASE_ADDR + 0x234)
+#define CLASS_ROUTE_ENTRY_SIZE(size)	 ((size) & 0x1ff)
+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
+
+#define CLASS_ROUTE_TABLE_BASE		(CLASS_CSR_BASE_ADDR + 0x238)
+#define CLASS_ROUTE_MULTI		(CLASS_CSR_BASE_ADDR + 0x23c)
+#define CLASS_SMEM_OFFSET		(CLASS_CSR_BASE_ADDR + 0x240)
+#define CLASS_LMEM_BUF_SIZE		(CLASS_CSR_BASE_ADDR + 0x244)
+#define CLASS_VLAN_ID			(CLASS_CSR_BASE_ADDR + 0x248)
+#define CLASS_BMU1_BUF_FREE		(CLASS_CSR_BASE_ADDR + 0x24c)
+#define CLASS_USE_TMU_INQ		(CLASS_CSR_BASE_ADDR + 0x250)
+#define CLASS_VLAN_ID1			(CLASS_CSR_BASE_ADDR + 0x254)
+
+#define CLASS_BUS_ACCESS_BASE		(CLASS_CSR_BASE_ADDR + 0x258)
+/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
+#define CLASS_BUS_ACCESS_BASE_MASK	(0xFF000000)
+
+#define CLASS_HIF_PARSE			(CLASS_CSR_BASE_ADDR + 0x25c)
+
+#define CLASS_HOST_PE0_GP		(CLASS_CSR_BASE_ADDR + 0x260)
+#define CLASS_PE0_GP			(CLASS_CSR_BASE_ADDR + 0x264)
+#define CLASS_HOST_PE1_GP		(CLASS_CSR_BASE_ADDR + 0x268)
+#define CLASS_PE1_GP			(CLASS_CSR_BASE_ADDR + 0x26c)
+#define CLASS_HOST_PE2_GP		(CLASS_CSR_BASE_ADDR + 0x270)
+#define CLASS_PE2_GP			(CLASS_CSR_BASE_ADDR + 0x274)
+#define CLASS_HOST_PE3_GP		(CLASS_CSR_BASE_ADDR + 0x278)
+#define CLASS_PE3_GP			(CLASS_CSR_BASE_ADDR + 0x27c)
+#define CLASS_HOST_PE4_GP		(CLASS_CSR_BASE_ADDR + 0x280)
+#define CLASS_PE4_GP			(CLASS_CSR_BASE_ADDR + 0x284)
+#define CLASS_HOST_PE5_GP		(CLASS_CSR_BASE_ADDR + 0x288)
+#define CLASS_PE5_GP			(CLASS_CSR_BASE_ADDR + 0x28c)
+
+#define CLASS_PE_INT_SRC		(CLASS_CSR_BASE_ADDR + 0x290)
+#define CLASS_PE_INT_ENABLE		(CLASS_CSR_BASE_ADDR + 0x294)
+
+#define CLASS_TPID0_TPID1		(CLASS_CSR_BASE_ADDR + 0x298)
+#define CLASS_TPID2			(CLASS_CSR_BASE_ADDR + 0x29c)
+
+#define CLASS_L4_CHKSUM_ADDR		(CLASS_CSR_BASE_ADDR + 0x2a0)
+
+#define CLASS_PE0_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2a4)
+#define CLASS_PE1_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2a8)
+#define CLASS_PE2_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2ac)
+#define CLASS_PE3_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2b0)
+#define CLASS_PE4_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2b4)
+#define CLASS_PE5_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2b8)
+
+#define CLASS_STATE			(CLASS_CSR_BASE_ADDR + 0x2bc)
+#define CLASS_AXI_CTRL			(CLASS_CSR_BASE_ADDR + 0x2d0)
+
+/* CLASS defines */
+#define CLASS_PBUF_SIZE			0x100	/* Fixed by hardware */
+#define CLASS_PBUF_HEADER_OFFSET	0x80	/* Can be configured */
+
+#define CLASS_PBUF0_BASE_ADDR		0x000	/* Can be configured */
+/* Can be configured */
+#define CLASS_PBUF1_BASE_ADDR	(CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
+/* Can be configured */
+#define CLASS_PBUF2_BASE_ADDR	(CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
+/* Can be configured */
+#define CLASS_PBUF3_BASE_ADDR	(CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
+
+#define CLASS_PBUF0_HEADER_BASE_ADDR	(CLASS_PBUF0_BASE_ADDR +\
+						CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF1_HEADER_BASE_ADDR	(CLASS_PBUF1_BASE_ADDR +\
+						CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF2_HEADER_BASE_ADDR	(CLASS_PBUF2_BASE_ADDR +\
+						CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF3_HEADER_BASE_ADDR	(CLASS_PBUF3_BASE_ADDR +\
+						CLASS_PBUF_HEADER_OFFSET)
+
+#define CLASS_PE0_RO_DM_ADDR0_VAL	((CLASS_PBUF1_BASE_ADDR << 16) |\
+						CLASS_PBUF0_BASE_ADDR)
+#define CLASS_PE0_RO_DM_ADDR1_VAL	((CLASS_PBUF3_BASE_ADDR << 16) |\
+						CLASS_PBUF2_BASE_ADDR)
+
+#define CLASS_PE0_QB_DM_ADDR0_VAL	((CLASS_PBUF1_HEADER_BASE_ADDR << 16)\
+						| CLASS_PBUF0_HEADER_BASE_ADDR)
+#define CLASS_PE0_QB_DM_ADDR1_VAL	((CLASS_PBUF3_HEADER_BASE_ADDR << 16)\
+						| CLASS_PBUF2_HEADER_BASE_ADDR)
+
+#define CLASS_ROUTE_SIZE		128
+#define CLASS_ROUTE_HASH_BITS		20
+#define CLASS_ROUTE_HASH_MASK		(BIT(CLASS_ROUTE_HASH_BITS) - 1)
+
+#define TWO_LEVEL_ROUTE		BIT(0)
+#define PHYNO_IN_HASH		BIT(1)
+#define HW_ROUTE_FETCH		BIT(3)
+#define HW_BRIDGE_FETCH		BIT(5)
+#define IP_ALIGNED		BIT(6)
+#define ARC_HIT_CHECK_EN	BIT(7)
+#define CLASS_TOE		BIT(11)
+#define HASH_CRC_PORT		BIT(12)
+#define HASH_CRC_IP		BIT(13)
+#define HASH_CRC_PORT_IP	GENMASK(13, 12)
+#define QB2BUS_LE		BIT(15)
+
+#define	TCP_CHKSUM_DROP		BIT(0)
+#define	UDP_CHKSUM_DROP		BIT(1)
+#define	IPV4_CHKSUM_DROP	BIT(9)
+
+struct class_cfg {
+	u32 route_table_baseaddr;
+	u32 route_table_hash_bits;
+};
+
+#endif /* _CLASS_CSR_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/emac.h b/include/net/pfe_eth/pfe/cbus/emac.h
new file mode 100644
index 0000000..53db8cc
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/emac.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _EMAC_H_
+#define _EMAC_H_
+
+#define EMAC_IEVENT_REG		0x004
+#define EMAC_IMASK_REG		0x008
+#define EMAC_R_DES_ACTIVE_REG	0x010
+#define EMAC_X_DES_ACTIVE_REG	0x014
+#define EMAC_ECNTRL_REG		0x024
+#define EMAC_MII_DATA_REG	0x040
+#define EMAC_MII_CTRL_REG	0x044
+#define EMAC_MIB_CTRL_STS_REG	0x064
+#define EMAC_RCNTRL_REG		0x084
+#define EMAC_TCNTRL_REG		0x0C4
+#define EMAC_PHY_ADDR_LOW	0x0E4
+#define EMAC_PHY_ADDR_HIGH	0x0E8
+#define EMAC_TFWR_STR_FWD	0x144
+#define EMAC_RX_SECTIOM_FULL	0x190
+#define EMAC_TX_SECTION_EMPTY	0x1A0
+#define EMAC_TRUNC_FL		0x1B0
+
+/* GEMAC definitions and settings */
+#define EMAC_PORT_0			0
+#define EMAC_PORT_1			1
+
+/* GEMAC Bit definitions */
+#define EMAC_IEVENT_HBERR                BIT(31)
+#define EMAC_IEVENT_BABR                 BIT(30)
+#define EMAC_IEVENT_BABT                 BIT(29)
+#define EMAC_IEVENT_GRA                  BIT(28)
+#define EMAC_IEVENT_TXF                  BIT(27)
+#define EMAC_IEVENT_TXB                  BIT(26)
+#define EMAC_IEVENT_RXF                  BIT(25)
+#define EMAC_IEVENT_RXB                  BIT(24)
+#define EMAC_IEVENT_MII                  BIT(23)
+#define EMAC_IEVENT_EBERR                BIT(22)
+#define EMAC_IEVENT_LC                   BIT(21)
+#define EMAC_IEVENT_RL                   BIT(20)
+#define EMAC_IEVENT_UN                   BIT(19)
+
+#define EMAC_IMASK_HBERR                 BIT(31)
+#define EMAC_IMASK_BABR                  BIT(30)
+#define EMAC_IMASKT_BABT                 BIT(29)
+#define EMAC_IMASK_GRA                   BIT(28)
+#define EMAC_IMASKT_TXF                  BIT(27)
+#define EMAC_IMASK_TXB                   BIT(26)
+#define EMAC_IMASKT_RXF                  BIT(25)
+#define EMAC_IMASK_RXB                   BIT(24)
+#define EMAC_IMASK_MII                   BIT(23)
+#define EMAC_IMASK_EBERR                 BIT(22)
+#define EMAC_IMASK_LC                    BIT(21)
+#define EMAC_IMASKT_RL                   BIT(20)
+#define EMAC_IMASK_UN                    BIT(19)
+
+#define EMAC_RCNTRL_MAX_FL_SHIFT         16
+#define EMAC_RCNTRL_LOOP                 BIT(0)
+#define EMAC_RCNTRL_DRT                  BIT(1)
+#define EMAC_RCNTRL_MII_MODE             BIT(2)
+#define EMAC_RCNTRL_PROM                 BIT(3)
+#define EMAC_RCNTRL_BC_REJ               BIT(4)
+#define EMAC_RCNTRL_FCE                  BIT(5)
+#define EMAC_RCNTRL_RGMII                BIT(6)
+#define EMAC_RCNTRL_SGMII                BIT(7)
+#define EMAC_RCNTRL_RMII                 BIT(8)
+#define EMAC_RCNTRL_RMII_10T             BIT(9)
+#define EMAC_RCNTRL_CRC_FWD		 BIT(10)
+
+#define EMAC_TCNTRL_GTS                  BIT(0)
+#define EMAC_TCNTRL_HBC                  BIT(1)
+#define EMAC_TCNTRL_FDEN                 BIT(2)
+#define EMAC_TCNTRL_TFC_PAUSE            BIT(3)
+#define EMAC_TCNTRL_RFC_PAUSE            BIT(4)
+
+#define EMAC_ECNTRL_RESET                BIT(0)      /* reset the EMAC */
+#define EMAC_ECNTRL_ETHER_EN             BIT(1)      /* enable the EMAC */
+#define EMAC_ECNTRL_SPEED                BIT(5)
+#define EMAC_ECNTRL_DBSWAP               BIT(8)
+
+#define EMAC_X_WMRK_STRFWD               BIT(8)
+
+#define EMAC_X_DES_ACTIVE_TDAR           BIT(24)
+#define EMAC_R_DES_ACTIVE_RDAR           BIT(24)
+
+#define EMAC_TFWR			(0x4)
+#define EMAC_RX_SECTION_FULL_32		(0x5)
+#define EMAC_TRUNC_FL_16K		(0x3FFF)
+#define EMAC_TX_SECTION_EMPTY_30	(0x30)
+#define EMAC_MIBC_NO_CLR_NO_DIS		(0x0)
+
+/*
+ * The possible operating speeds of the MAC, currently supporting 10, 100 and
+ * 1000Mb modes.
+ */
+enum mac_speed {PFE_MAC_SPEED_10M, PFE_MAC_SPEED_100M, PFE_MAC_SPEED_1000M,
+		PFE_MAC_SPEED_1000M_PCS};
+
+/* MII-related definitios */
+#define EMAC_MII_DATA_ST         0x40000000      /* Start of frame delimiter */
+#define EMAC_MII_DATA_OP_RD      0x20000000      /* Perform a read operation */
+#define EMAC_MII_DATA_OP_CL45_RD 0x30000000      /* Perform a read operation */
+#define EMAC_MII_DATA_OP_WR      0x10000000      /* Perform a write operation */
+#define EMAC_MII_DATA_OP_CL45_WR 0x10000000      /* Perform a write operation */
+#define EMAC_MII_DATA_PA_MSK     0x0f800000      /* PHY Address field mask */
+#define EMAC_MII_DATA_RA_MSK     0x007c0000      /* PHY Register field mask */
+#define EMAC_MII_DATA_TA         0x00020000      /* Turnaround */
+#define EMAC_MII_DATA_DATAMSK    0x0000ffff      /* PHY data field */
+
+#define EMAC_MII_DATA_RA_SHIFT   18      /* MII Register address bits */
+#define EMAC_MII_DATA_RA_MASK	 0x1F      /* MII Register address mask */
+#define EMAC_MII_DATA_PA_SHIFT   23      /* MII PHY address bits */
+#define EMAC_MII_DATA_PA_MASK    0x1F      /* MII PHY address mask */
+
+#define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
+				EMAC_MII_DATA_RA_SHIFT)
+#define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
+				EMAC_MII_DATA_PA_SHIFT)
+#define EMAC_MII_DATA(v)    (v & 0xffff)
+
+#define EMAC_MII_SPEED_SHIFT	1
+#define EMAC_HOLDTIME_SHIFT	8
+#define EMAC_HOLDTIME_MASK	0x7
+#define EMAC_HOLDTIME(v)    ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT)
+
+/* Internal PHY Registers - SGMII */
+#define PHY_SGMII_CR_PHY_RESET      0x8000
+#define PHY_SGMII_CR_RESET_AN       0x0200
+#define PHY_SGMII_CR_DEF_VAL        0x1140
+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
+#define PHY_SGMII_IF_MODE_AN        0x0002
+#define PHY_SGMII_IF_MODE_SGMII     0x0001
+#define PHY_SGMII_IF_MODE_SGMII_GBT 0x0008
+#define PHY_SGMII_ENABLE_AN         0x1000
+
+#endif /* _EMAC_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/gpi.h b/include/net/pfe_eth/pfe/cbus/gpi.h
new file mode 100644
index 0000000..6b5ba5d
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/gpi.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _GPI_H_
+#define _GPI_H_
+
+#define GPI_VERSION			0x00
+#define GPI_CTRL			0x04
+#define GPI_RX_CONFIG			0x08
+#define GPI_HDR_SIZE			0x0c
+#define GPI_BUF_SIZE			0x10
+#define GPI_LMEM_ALLOC_ADDR		0x14
+#define GPI_LMEM_FREE_ADDR		0x18
+#define GPI_DDR_ALLOC_ADDR		0x1c
+#define GPI_DDR_FREE_ADDR		0x20
+#define GPI_CLASS_ADDR			0x24
+#define GPI_DRX_FIFO			0x28
+#define GPI_TRX_FIFO			0x2c
+#define GPI_INQ_PKTPTR			0x30
+#define GPI_DDR_DATA_OFFSET		0x34
+#define GPI_LMEM_DATA_OFFSET		0x38
+#define GPI_TMLF_TX			0x4c
+#define GPI_DTX_ASEQ			0x50
+#define GPI_FIFO_STATUS			0x54
+#define GPI_FIFO_DEBUG			0x58
+#define GPI_TX_PAUSE_TIME		0x5c
+#define GPI_LMEM_SEC_BUF_DATA_OFFSET	0x60
+#define GPI_DDR_SEC_BUF_DATA_OFFSET	0x64
+#define GPI_TOE_CHKSUM_EN		0x68
+#define GPI_OVERRUN_DROPCNT		0x6c
+#define GPI_AXI_CTRL			0x70
+
+struct gpi_cfg {
+	u32 lmem_rtry_cnt;
+	u32 tmlf_txthres;
+	u32 aseq_len;
+};
+
+/* GPI commons defines */
+#define GPI_LMEM_BUF_EN		0x1
+#define GPI_DDR_BUF_EN		0x1
+
+/* EGPI 1 defines */
+#define EGPI1_LMEM_RTRY_CNT	0x40
+#define EGPI1_TMLF_TXTHRES	0xBC
+#define EGPI1_ASEQ_LEN		0x50
+
+/* EGPI 2 defines */
+#define EGPI2_LMEM_RTRY_CNT	0x40
+#define EGPI2_TMLF_TXTHRES	0xBC
+#define EGPI2_ASEQ_LEN		0x40
+
+/* HGPI defines */
+#define HGPI_LMEM_RTRY_CNT	0x40
+#define HGPI_TMLF_TXTHRES	0xBC
+#define HGPI_ASEQ_LEN		0x40
+
+#endif /* _GPI_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/hif.h b/include/net/pfe_eth/pfe/cbus/hif.h
new file mode 100644
index 0000000..36722c5
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/hif.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _HIF_H_
+#define _HIF_H_
+
+/*
+ * @file hif.h.
+ * hif - PFE hif block control and status register.
+ * Mapped on CBUS and accessible from all PE's and ARM.
+ */
+#define HIF_VERSION		(HIF_BASE_ADDR + 0x00)
+#define HIF_TX_CTRL		(HIF_BASE_ADDR + 0x04)
+#define HIF_TX_CURR_BD_ADDR	(HIF_BASE_ADDR + 0x08)
+#define HIF_TX_ALLOC		(HIF_BASE_ADDR + 0x0c)
+#define HIF_TX_BDP_ADDR		(HIF_BASE_ADDR + 0x10)
+#define HIF_TX_STATUS		(HIF_BASE_ADDR + 0x14)
+#define HIF_RX_CTRL		(HIF_BASE_ADDR + 0x20)
+#define HIF_RX_BDP_ADDR		(HIF_BASE_ADDR + 0x24)
+#define HIF_RX_STATUS		(HIF_BASE_ADDR + 0x30)
+#define HIF_INT_SRC		(HIF_BASE_ADDR + 0x34)
+#define HIF_INT_ENABLE		(HIF_BASE_ADDR + 0x38)
+#define HIF_POLL_CTRL		(HIF_BASE_ADDR + 0x3c)
+#define HIF_RX_CURR_BD_ADDR	(HIF_BASE_ADDR + 0x40)
+#define HIF_RX_ALLOC		(HIF_BASE_ADDR + 0x44)
+#define HIF_TX_DMA_STATUS	(HIF_BASE_ADDR + 0x48)
+#define HIF_RX_DMA_STATUS	(HIF_BASE_ADDR + 0x4c)
+#define HIF_INT_COAL		(HIF_BASE_ADDR + 0x50)
+#define HIF_AXI_CTRL		(HIF_BASE_ADDR + 0x54)
+
+/* HIF_TX_CTRL bits */
+#define HIF_CTRL_DMA_EN			BIT(0)
+#define HIF_CTRL_BDP_POLL_CTRL_EN	BIT(1)
+#define HIF_CTRL_BDP_CH_START_WSTB	BIT(2)
+
+/* HIF_RX_STATUS bits */
+#define BDP_CSR_RX_DMA_ACTV	BIT(16)
+
+/* HIF_INT_ENABLE bits */
+#define HIF_INT_EN		BIT(0)
+#define HIF_RXBD_INT_EN		BIT(1)
+#define HIF_RXPKT_INT_EN	BIT(2)
+#define HIF_TXBD_INT_EN		BIT(3)
+#define HIF_TXPKT_INT_EN	BIT(4)
+
+/* HIF_POLL_CTRL bits*/
+#define HIF_RX_POLL_CTRL_CYCLE	0x0400
+#define HIF_TX_POLL_CTRL_CYCLE	0x0400
+
+/* Buffer descriptor control bits */
+#define BD_CTRL_BUFLEN_MASK	(0xffff)
+#define BD_BUF_LEN(x)	(x & BD_CTRL_BUFLEN_MASK)
+#define BD_CTRL_CBD_INT_EN	BIT(16)
+#define BD_CTRL_PKT_INT_EN	BIT(17)
+#define BD_CTRL_LIFM		BIT(18)
+#define BD_CTRL_LAST_BD		BIT(19)
+#define BD_CTRL_DIR		BIT(20)
+#define BD_CTRL_PKT_XFER	BIT(24)
+#define BD_CTRL_DESC_EN		BIT(31)
+#define BD_CTRL_PARSE_DISABLE	BIT(25)
+#define BD_CTRL_BRFETCH_DISABLE	BIT(26)
+#define BD_CTRL_RTFETCH_DISABLE	BIT(27)
+
+#endif /* _HIF_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/hif_nocpy.h b/include/net/pfe_eth/pfe/cbus/hif_nocpy.h
new file mode 100644
index 0000000..21aa133
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/hif_nocpy.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _HIF_NOCPY_H_
+#define _HIF_NOCPY_H_
+
+#define HIF_NOCPY_VERSION		(HIF_NOCPY_BASE_ADDR + 0x00)
+#define HIF_NOCPY_TX_CTRL		(HIF_NOCPY_BASE_ADDR + 0x04)
+#define HIF_NOCPY_TX_CURR_BD_ADDR	(HIF_NOCPY_BASE_ADDR + 0x08)
+#define HIF_NOCPY_TX_ALLOC		(HIF_NOCPY_BASE_ADDR + 0x0c)
+#define HIF_NOCPY_TX_BDP_ADDR		(HIF_NOCPY_BASE_ADDR + 0x10)
+#define HIF_NOCPY_TX_STATUS		(HIF_NOCPY_BASE_ADDR + 0x14)
+#define HIF_NOCPY_RX_CTRL		(HIF_NOCPY_BASE_ADDR + 0x20)
+#define HIF_NOCPY_RX_BDP_ADDR		(HIF_NOCPY_BASE_ADDR + 0x24)
+#define HIF_NOCPY_RX_STATUS		(HIF_NOCPY_BASE_ADDR + 0x30)
+#define HIF_NOCPY_INT_SRC		(HIF_NOCPY_BASE_ADDR + 0x34)
+#define HIF_NOCPY_INT_ENABLE		(HIF_NOCPY_BASE_ADDR + 0x38)
+#define HIF_NOCPY_POLL_CTRL		(HIF_NOCPY_BASE_ADDR + 0x3c)
+#define HIF_NOCPY_RX_CURR_BD_ADDR	(HIF_NOCPY_BASE_ADDR + 0x40)
+#define HIF_NOCPY_RX_ALLOC		(HIF_NOCPY_BASE_ADDR + 0x44)
+#define HIF_NOCPY_TX_DMA_STATUS		(HIF_NOCPY_BASE_ADDR + 0x48)
+#define HIF_NOCPY_RX_DMA_STATUS		(HIF_NOCPY_BASE_ADDR + 0x4c)
+#define HIF_NOCPY_RX_INQ0_PKTPTR	(HIF_NOCPY_BASE_ADDR + 0x50)
+#define HIF_NOCPY_RX_INQ1_PKTPTR	(HIF_NOCPY_BASE_ADDR + 0x54)
+#define HIF_NOCPY_TX_PORT_NO		(HIF_NOCPY_BASE_ADDR + 0x60)
+#define HIF_NOCPY_LMEM_ALLOC_ADDR	(HIF_NOCPY_BASE_ADDR + 0x64)
+#define HIF_NOCPY_CLASS_ADDR		(HIF_NOCPY_BASE_ADDR + 0x68)
+#define HIF_NOCPY_TMU_PORT0_ADDR	(HIF_NOCPY_BASE_ADDR + 0x70)
+#define HIF_NOCPY_TMU_PORT1_ADDR	(HIF_NOCPY_BASE_ADDR + 0x74)
+#define HIF_NOCPY_TMU_PORT2_ADDR	(HIF_NOCPY_BASE_ADDR + 0x7c)
+#define HIF_NOCPY_TMU_PORT3_ADDR	(HIF_NOCPY_BASE_ADDR + 0x80)
+#define HIF_NOCPY_TMU_PORT4_ADDR	(HIF_NOCPY_BASE_ADDR + 0x84)
+#define HIF_NOCPY_INT_COAL		(HIF_NOCPY_BASE_ADDR + 0x90)
+#define HIF_NOCPY_AXI_CTRL		(HIF_NOCPY_BASE_ADDR + 0x94)
+
+#endif /* _HIF_NOCPY_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/tmu_csr.h b/include/net/pfe_eth/pfe/cbus/tmu_csr.h
new file mode 100644
index 0000000..1e1abe2
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/tmu_csr.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _TMU_CSR_H_
+#define _TMU_CSR_H_
+
+#define TMU_VERSION			(TMU_CSR_BASE_ADDR + 0x000)
+#define TMU_INQ_WATERMARK		(TMU_CSR_BASE_ADDR + 0x004)
+#define TMU_PHY_INQ_PKTPTR		(TMU_CSR_BASE_ADDR + 0x008)
+#define TMU_PHY_INQ_PKTINFO		(TMU_CSR_BASE_ADDR + 0x00c)
+#define TMU_PHY_INQ_FIFO_CNT		(TMU_CSR_BASE_ADDR + 0x010)
+#define TMU_SYS_GENERIC_CONTROL		(TMU_CSR_BASE_ADDR + 0x014)
+#define TMU_SYS_GENERIC_STATUS		(TMU_CSR_BASE_ADDR + 0x018)
+#define TMU_SYS_GEN_CON0		(TMU_CSR_BASE_ADDR + 0x01c)
+#define TMU_SYS_GEN_CON1		(TMU_CSR_BASE_ADDR + 0x020)
+#define TMU_SYS_GEN_CON2		(TMU_CSR_BASE_ADDR + 0x024)
+#define TMU_SYS_GEN_CON3		(TMU_CSR_BASE_ADDR + 0x028)
+#define TMU_SYS_GEN_CON4		(TMU_CSR_BASE_ADDR + 0x02c)
+#define TMU_TEQ_DISABLE_DROPCHK		(TMU_CSR_BASE_ADDR + 0x030)
+#define TMU_TEQ_CTRL			(TMU_CSR_BASE_ADDR + 0x034)
+#define TMU_TEQ_QCFG			(TMU_CSR_BASE_ADDR + 0x038)
+#define TMU_TEQ_DROP_STAT		(TMU_CSR_BASE_ADDR + 0x03c)
+#define TMU_TEQ_QAVG			(TMU_CSR_BASE_ADDR + 0x040)
+#define TMU_TEQ_WREG_PROB		(TMU_CSR_BASE_ADDR + 0x044)
+#define TMU_TEQ_TRANS_STAT		(TMU_CSR_BASE_ADDR + 0x048)
+#define TMU_TEQ_HW_PROB_CFG0		(TMU_CSR_BASE_ADDR + 0x04c)
+#define TMU_TEQ_HW_PROB_CFG1		(TMU_CSR_BASE_ADDR + 0x050)
+#define TMU_TEQ_HW_PROB_CFG2		(TMU_CSR_BASE_ADDR + 0x054)
+#define TMU_TEQ_HW_PROB_CFG3		(TMU_CSR_BASE_ADDR + 0x058)
+#define TMU_TEQ_HW_PROB_CFG4		(TMU_CSR_BASE_ADDR + 0x05c)
+#define TMU_TEQ_HW_PROB_CFG5		(TMU_CSR_BASE_ADDR + 0x060)
+#define TMU_TEQ_HW_PROB_CFG6		(TMU_CSR_BASE_ADDR + 0x064)
+#define TMU_TEQ_HW_PROB_CFG7		(TMU_CSR_BASE_ADDR + 0x068)
+#define TMU_TEQ_HW_PROB_CFG8		(TMU_CSR_BASE_ADDR + 0x06c)
+#define TMU_TEQ_HW_PROB_CFG9		(TMU_CSR_BASE_ADDR + 0x070)
+#define TMU_TEQ_HW_PROB_CFG10		(TMU_CSR_BASE_ADDR + 0x074)
+#define TMU_TEQ_HW_PROB_CFG11		(TMU_CSR_BASE_ADDR + 0x078)
+#define TMU_TEQ_HW_PROB_CFG12		(TMU_CSR_BASE_ADDR + 0x07c)
+#define TMU_TEQ_HW_PROB_CFG13		(TMU_CSR_BASE_ADDR + 0x080)
+#define TMU_TEQ_HW_PROB_CFG14		(TMU_CSR_BASE_ADDR + 0x084)
+#define TMU_TEQ_HW_PROB_CFG15		(TMU_CSR_BASE_ADDR + 0x088)
+#define TMU_TEQ_HW_PROB_CFG16		(TMU_CSR_BASE_ADDR + 0x08c)
+#define TMU_TEQ_HW_PROB_CFG17		(TMU_CSR_BASE_ADDR + 0x090)
+#define TMU_TEQ_HW_PROB_CFG18		(TMU_CSR_BASE_ADDR + 0x094)
+#define TMU_TEQ_HW_PROB_CFG19		(TMU_CSR_BASE_ADDR + 0x098)
+#define TMU_TEQ_HW_PROB_CFG20		(TMU_CSR_BASE_ADDR + 0x09c)
+#define TMU_TEQ_HW_PROB_CFG21		(TMU_CSR_BASE_ADDR + 0x0a0)
+#define TMU_TEQ_HW_PROB_CFG22		(TMU_CSR_BASE_ADDR + 0x0a4)
+#define TMU_TEQ_HW_PROB_CFG23		(TMU_CSR_BASE_ADDR + 0x0a8)
+#define TMU_TEQ_HW_PROB_CFG24		(TMU_CSR_BASE_ADDR + 0x0ac)
+#define TMU_TEQ_HW_PROB_CFG25		(TMU_CSR_BASE_ADDR + 0x0b0)
+#define TMU_TDQ_IIFG_CFG		(TMU_CSR_BASE_ADDR + 0x0b4)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
+ * This is a global Enable for all schedulers in PHY0
+ */
+#define TMU_TDQ0_SCH_CTRL		(TMU_CSR_BASE_ADDR + 0x0b8)
+#define TMU_LLM_CTRL			(TMU_CSR_BASE_ADDR + 0x0bc)
+#define TMU_LLM_BASE_ADDR		(TMU_CSR_BASE_ADDR + 0x0c0)
+#define TMU_LLM_QUE_LEN			(TMU_CSR_BASE_ADDR + 0x0c4)
+#define TMU_LLM_QUE_HEADPTR		(TMU_CSR_BASE_ADDR + 0x0c8)
+#define TMU_LLM_QUE_TAILPTR		(TMU_CSR_BASE_ADDR + 0x0cc)
+#define TMU_LLM_QUE_DROPCNT		(TMU_CSR_BASE_ADDR + 0x0d0)
+#define TMU_INT_EN			(TMU_CSR_BASE_ADDR + 0x0d4)
+#define TMU_INT_SRC			(TMU_CSR_BASE_ADDR + 0x0d8)
+#define TMU_INQ_STAT			(TMU_CSR_BASE_ADDR + 0x0dc)
+#define TMU_CTRL			(TMU_CSR_BASE_ADDR + 0x0e0)
+
+/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal
+ * memory Write [27:24] Byte Enables of the Internal memory access [23:0]
+ * Address of the internal memory. This address is used to access both the
+ * PM and DM of all the PE's
+ */
+#define TMU_MEM_ACCESS_ADDR		(TMU_CSR_BASE_ADDR + 0x0e4)
+
+/* Internal Memory Access Write Data */
+#define TMU_MEM_ACCESS_WDATA		(TMU_CSR_BASE_ADDR + 0x0e8)
+/* Internal Memory Access Read Data. The commands are blocked at the
+ * mem_access only
+ */
+#define TMU_MEM_ACCESS_RDATA		(TMU_CSR_BASE_ADDR + 0x0ec)
+
+/* [31:0] PHY0 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY0_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x0f0)
+/* [31:0] PHY1 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY1_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x0f4)
+/* [31:0] PHY3 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY3_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x0fc)
+#define TMU_BMU_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x100)
+#define TMU_TX_CTRL			(TMU_CSR_BASE_ADDR + 0x104)
+
+#define TMU_PE_SYS_CLK_RATIO		(TMU_CSR_BASE_ADDR + 0x114)
+#define TMU_PE_STATUS			(TMU_CSR_BASE_ADDR + 0x118)
+#define TMU_TEQ_MAX_THRESHOLD		(TMU_CSR_BASE_ADDR + 0x11c)
+
+/* [31:0] PHY4 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY4_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x134)
+
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
+ * is a global Enable for all schedulers in PHY1
+ */
+#define TMU_TDQ1_SCH_CTRL		(TMU_CSR_BASE_ADDR + 0x138)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
+ * is a global Enable for all schedulers in PHY3
+ */
+#define TMU_TDQ3_SCH_CTRL		(TMU_CSR_BASE_ADDR + 0x140)
+
+#define TMU_BMU_BUF_SIZE		(TMU_CSR_BASE_ADDR + 0x144)
+/* [31:0] PHY5 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY5_INQ_ADDR		(TMU_CSR_BASE_ADDR + 0x148)
+
+#define TMU_AXI_CTRL			(TMU_CSR_BASE_ADDR + 0x17c)
+
+#define SW_RESET		BIT(0) /* Global software reset */
+#define INQ_RESET		BIT(2)
+#define TEQ_RESET		BIT(3)
+#define TDQ_RESET		BIT(4)
+#define PE_RESET		BIT(5)
+#define MEM_INIT		BIT(6)
+#define MEM_INIT_DONE		BIT(7)
+#define LLM_INIT		BIT(8)
+#define LLM_INIT_DONE		BIT(9)
+#define ECC_MEM_INIT_DONE	BIT(10)
+
+struct tmu_cfg {
+	u32 llm_base_addr;
+	u32 llm_queue_len;
+};
+
+/* Not HW related for pfe_ctrl/pfe common defines */
+#define DEFAULT_MAX_QDEPTH	80
+#define DEFAULT_Q0_QDEPTH	511 /* We keep 1 large queue for host tx qos */
+#define DEFAULT_TMU3_QDEPTH	127
+
+#endif /* _TMU_CSR_H_ */
diff --git a/include/net/pfe_eth/pfe/cbus/util_csr.h b/include/net/pfe_eth/pfe/cbus/util_csr.h
new file mode 100644
index 0000000..40476cd
--- /dev/null
+++ b/include/net/pfe_eth/pfe/cbus/util_csr.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _UTIL_CSR_H_
+#define _UTIL_CSR_H_
+
+#define UTIL_VERSION			(UTIL_CSR_BASE_ADDR + 0x000)
+#define UTIL_TX_CTRL			(UTIL_CSR_BASE_ADDR + 0x004)
+#define UTIL_INQ_PKTPTR			(UTIL_CSR_BASE_ADDR + 0x010)
+
+#define UTIL_HDR_SIZE			(UTIL_CSR_BASE_ADDR + 0x014)
+
+#define UTIL_PE0_QB_DM_ADDR0		(UTIL_CSR_BASE_ADDR + 0x020)
+#define UTIL_PE0_QB_DM_ADDR1		(UTIL_CSR_BASE_ADDR + 0x024)
+#define UTIL_PE0_RO_DM_ADDR0		(UTIL_CSR_BASE_ADDR + 0x060)
+#define UTIL_PE0_RO_DM_ADDR1		(UTIL_CSR_BASE_ADDR + 0x064)
+
+#define UTIL_MEM_ACCESS_ADDR		(UTIL_CSR_BASE_ADDR + 0x100)
+#define UTIL_MEM_ACCESS_WDATA		(UTIL_CSR_BASE_ADDR + 0x104)
+#define UTIL_MEM_ACCESS_RDATA		(UTIL_CSR_BASE_ADDR + 0x108)
+
+#define UTIL_TM_INQ_ADDR		(UTIL_CSR_BASE_ADDR + 0x114)
+#define UTIL_PE_STATUS			(UTIL_CSR_BASE_ADDR + 0x118)
+
+#define UTIL_PE_SYS_CLK_RATIO		(UTIL_CSR_BASE_ADDR + 0x200)
+#define UTIL_AFULL_THRES		(UTIL_CSR_BASE_ADDR + 0x204)
+#define UTIL_GAP_BETWEEN_READS		(UTIL_CSR_BASE_ADDR + 0x208)
+#define UTIL_MAX_BUF_CNT		(UTIL_CSR_BASE_ADDR + 0x20c)
+#define UTIL_TSQ_FIFO_THRES		(UTIL_CSR_BASE_ADDR + 0x210)
+#define UTIL_TSQ_MAX_CNT		(UTIL_CSR_BASE_ADDR + 0x214)
+#define UTIL_IRAM_DATA_0		(UTIL_CSR_BASE_ADDR + 0x218)
+#define UTIL_IRAM_DATA_1		(UTIL_CSR_BASE_ADDR + 0x21c)
+#define UTIL_IRAM_DATA_2		(UTIL_CSR_BASE_ADDR + 0x220)
+#define UTIL_IRAM_DATA_3		(UTIL_CSR_BASE_ADDR + 0x224)
+
+#define UTIL_BUS_ACCESS_ADDR		(UTIL_CSR_BASE_ADDR + 0x228)
+#define UTIL_BUS_ACCESS_WDATA		(UTIL_CSR_BASE_ADDR + 0x22c)
+#define UTIL_BUS_ACCESS_RDATA		(UTIL_CSR_BASE_ADDR + 0x230)
+
+#define UTIL_INQ_AFULL_THRES		(UTIL_CSR_BASE_ADDR + 0x234)
+#define UTIL_AXI_CTRL			(UTIL_CSR_BASE_ADDR + 0x240)
+
+#endif /* _UTIL_CSR_H_ */
diff --git a/include/net/pfe_eth/pfe/pfe_hw.h b/include/net/pfe_eth/pfe/pfe_hw.h
new file mode 100644
index 0000000..5da676b
--- /dev/null
+++ b/include/net/pfe_eth/pfe/pfe_hw.h
@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _PFE_H_
+#define _PFE_H_
+
+#include <elf.h>
+#include "cbus.h"
+
+#define PFE_RESET_WA
+
+#define CLASS_DMEM_BASE_ADDR(i)	(0x00000000 | ((i) << 20))
+/* Only valid for mem access register interface */
+#define CLASS_IMEM_BASE_ADDR(i)	(0x00000000 | ((i) << 20))
+#define CLASS_DMEM_SIZE		0x00002000
+#define CLASS_IMEM_SIZE		0x00008000
+
+#define TMU_DMEM_BASE_ADDR(i)	(0x00000000 + ((i) << 20))
+/* Only valid for mem access register interface */
+#define TMU_IMEM_BASE_ADDR(i)	(0x00000000 + ((i) << 20))
+#define TMU_DMEM_SIZE		0x00000800
+#define TMU_IMEM_SIZE		0x00002000
+
+#define UTIL_DMEM_BASE_ADDR	0x00000000
+#define UTIL_DMEM_SIZE		0x00002000
+
+#define PE_LMEM_BASE_ADDR	0xc3010000
+#define PE_LMEM_SIZE		0x8000
+#define PE_LMEM_END		(PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
+
+#define DMEM_BASE_ADDR		0x00000000
+#define DMEM_SIZE		0x2000		/* TMU has less... */
+#define DMEM_END		(DMEM_BASE_ADDR + DMEM_SIZE)
+
+#define PMEM_BASE_ADDR		0x00010000
+#define PMEM_SIZE		0x8000		/* TMU has less... */
+#define PMEM_END		(PMEM_BASE_ADDR + PMEM_SIZE)
+
+/* Memory ranges check from PE point of view/memory map */
+#define IS_DMEM(addr, len)	(((unsigned long)(addr) >= DMEM_BASE_ADDR) &&\
+					(((unsigned long)(addr) +\
+					(len)) <= DMEM_END))
+#define IS_PMEM(addr, len)	(((unsigned long)(addr) >= PMEM_BASE_ADDR) &&\
+					(((unsigned long)(addr) +\
+					(len)) <= PMEM_END))
+#define IS_PE_LMEM(addr, len)	(((unsigned long)(addr) >= PE_LMEM_BASE_ADDR\
+					) && (((unsigned long)(addr)\
+					+ (len)) <= PE_LMEM_END))
+
+#define IS_PFE_LMEM(addr, len)	(((unsigned long)(addr) >=\
+					CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&\
+					(((unsigned long)(addr) + (len)) <=\
+					CBUS_VIRT_TO_PFE(LMEM_END)))
+#define IS_PHYS_DDR(addr, len)	(((unsigned long)(addr) >=\
+					PFE_DDR_PHYS_BASE_ADDR) &&\
+					(((unsigned long)(addr) + (len)) <=\
+					PFE_DDR_PHYS_END))
+
+/* Host View Address */
+extern void *ddr_pfe_base_addr;
+
+/* PFE View Address */
+/* DDR physical base address as seen by PE's. */
+#define PFE_DDR_PHYS_BASE_ADDR	0x03800000
+#define PFE_DDR_PHYS_SIZE	0xC000000
+#define PFE_DDR_PHYS_END	(PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE)
+/* CBUS physical base address as seen by PE's. */
+#define PFE_CBUS_PHYS_BASE_ADDR	0xc0000000
+
+/* Host<->PFE Mapping */
+#define DDR_PFE_TO_VIRT(p)	((unsigned long int)((p) + 0x80000000))
+#define CBUS_VIRT_TO_PFE(v)	(((v) - CBUS_BASE_ADDR) +\
+					PFE_CBUS_PHYS_BASE_ADDR)
+#define CBUS_PFE_TO_VIRT(p)	(((p) - PFE_CBUS_PHYS_BASE_ADDR) +\
+					CBUS_BASE_ADDR)
+
+enum {
+	CLASS0_ID = 0,
+	CLASS1_ID,
+	CLASS2_ID,
+	CLASS3_ID,
+	CLASS4_ID,
+	CLASS5_ID,
+
+	TMU0_ID,
+	TMU1_ID,
+	TMU2_ID,
+	TMU3_ID,
+	MAX_PE
+};
+
+#define CLASS_MASK	(BIT(CLASS0_ID) | BIT(CLASS1_ID) | BIT(CLASS2_ID)\
+				| BIT(CLASS3_ID) | BIT(CLASS4_ID) |\
+				BIT(CLASS5_ID))
+#define CLASS_MAX_ID	CLASS5_ID
+
+#define TMU_MASK	(BIT(TMU0_ID) | BIT(TMU1_ID) | BIT(TMU3_ID))
+#define TMU_MAX_ID	TMU3_ID
+
+/*
+ * PE information.
+ * Structure containing PE's specific information. It is used to create
+ * generic C functions common to all PEs.
+ * Before using the library functions this structure needs to be
+ * initialized with the different registers virtual addresses
+ * (according to the ARM MMU mmaping). The default initialization supports a
+ * virtual == physical mapping.
+ *
+ */
+struct pe_info {
+	u32 dmem_base_addr;		/* PE's dmem base address */
+	u32 pmem_base_addr;		/* PE's pmem base address */
+	u32 pmem_size;			/* PE's pmem size */
+
+	void *mem_access_wdata;	       /* PE's _MEM_ACCESS_WDATA
+					* register address
+					*/
+	void *mem_access_addr;	       /* PE's _MEM_ACCESS_ADDR
+					* register address
+					*/
+	void *mem_access_rdata;	       /* PE's _MEM_ACCESS_RDATA
+					* register address
+					*/
+};
+
+void pe_lmem_read(u32 *dst, u32 len, u32 offset);
+void pe_lmem_write(u32 *src, u32 len, u32 offset);
+
+u32 pe_pmem_read(int id, u32 addr, u8 size);
+void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
+u32 pe_dmem_read(int id, u32 addr, u8 size);
+
+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
+
+void pfe_lib_init(void);
+
+void bmu_init(void *base, struct bmu_cfg *cfg);
+void bmu_enable(void *base);
+
+void gpi_init(void *base, struct gpi_cfg *cfg);
+void gpi_enable(void *base);
+void gpi_disable(void *base);
+
+void class_init(struct class_cfg *cfg);
+void class_enable(void);
+void class_disable(void);
+
+void tmu_init(struct tmu_cfg *cfg);
+void tmu_enable(u32 pe_mask);
+void tmu_disable(u32 pe_mask);
+
+void hif_init(void);
+void hif_tx_enable(void);
+void hif_tx_disable(void);
+void hif_rx_enable(void);
+void hif_rx_disable(void);
+void hif_rx_desc_disable(void);
+
+#endif /* _PFE_H_ */
diff --git a/include/net/pfe_eth/pfe_driver.h b/include/net/pfe_eth/pfe_driver.h
new file mode 100644
index 0000000..fa9f2fa
--- /dev/null
+++ b/include/net/pfe_eth/pfe_driver.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef __PFE_DRIVER_H__
+#define __PFE_DRIVER_H__
+
+#include <net/pfe_eth/pfe/pfe_hw.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+
+#define HIF_RX_DESC_NT		64
+#define	HIF_TX_DESC_NT		64
+
+#define RX_BD_BASEADDR		(HIF_DESC_BASEADDR)
+#define TX_BD_BASEADDR		(HIF_DESC_BASEADDR + HIF_TX_DESC_SIZE)
+
+#define MIN_PKT_SIZE		56
+#define MAX_FRAME_SIZE		2048
+
+struct __packed hif_header_s {
+	u8	port_no; /* Carries input port no for host rx packets and
+			  * output port no for tx pkts
+			  */
+	u8 reserved0;
+	u32 reserved2;
+};
+
+struct __packed buf_desc {
+	u32 ctrl;
+	u32 status;
+	u32 data;
+	u32 next;
+};
+
+struct rx_desc_s {
+	struct buf_desc *rx_base;
+	unsigned int rx_base_pa;
+	int rx_to_read;
+	int rx_ring_size;
+};
+
+struct tx_desc_s {
+	struct buf_desc *tx_base;
+	unsigned int tx_base_pa;
+	int tx_to_send;
+	int tx_ring_size;
+};
+
+int pfe_send(int phy_port, void *data, int length);
+int pfe_recv(uchar **pkt_ptr, int *phy_port);
+int pfe_tx_done(void);
+int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length);
+int pfe_drv_init(struct pfe_ddr_address  *pfe_addr);
+int pfe_eth_remove(struct udevice *dev);
+
+#endif
diff --git a/include/net/pfe_eth/pfe_eth.h b/include/net/pfe_eth/pfe_eth.h
new file mode 100644
index 0000000..68b2e38
--- /dev/null
+++ b/include/net/pfe_eth/pfe_eth.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef __PFE_ETH_H__
+#define __PFE_ETH_H__
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include "pfe_driver.h"
+
+#define BMU2_DDR_BASEADDR	0
+#define BMU2_BUF_COUNT		(3 * SZ_1K)
+#define BMU2_DDR_SIZE		(DDR_BUF_SIZE * BMU2_BUF_COUNT)
+
+#define HIF_RX_PKT_DDR_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
+#define HIF_RX_PKT_DDR_SIZE     (HIF_RX_DESC_NT * DDR_BUF_SIZE)
+#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
+#define HIF_TX_PKT_DDR_SIZE     (HIF_TX_DESC_NT * DDR_BUF_SIZE)
+
+#define HIF_DESC_BASEADDR       (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
+#define HIF_RX_DESC_SIZE        (16 * HIF_RX_DESC_NT)
+#define HIF_TX_DESC_SIZE        (16 * HIF_TX_DESC_NT)
+
+#define UTIL_CODE_BASEADDR	0x780000
+#define UTIL_CODE_SIZE		(128 * SZ_1K)
+
+#define UTIL_DDR_DATA_BASEADDR	(UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
+#define UTIL_DDR_DATA_SIZE	(64 * SZ_1K)
+
+#define CLASS_DDR_DATA_BASEADDR	(UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
+#define CLASS_DDR_DATA_SIZE	(32 * SZ_1K)
+
+#define TMU_DDR_DATA_BASEADDR	(CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
+#define TMU_DDR_DATA_SIZE	(32 * SZ_1K)
+
+#define TMU_LLM_BASEADDR	(TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
+#define TMU_LLM_QUEUE_LEN	(16 * 256)
+	/* Must be power of two and at least 16 * 8 = 128 bytes */
+#define TMU_LLM_SIZE		(4 * 16 * TMU_LLM_QUEUE_LEN)
+	/* (4 TMU's x 16 queues x queue_len) */
+
+#define ROUTE_TABLE_BASEADDR	0x800000
+#define ROUTE_TABLE_HASH_BITS_MAX	15 /* 32K entries */
+#define ROUTE_TABLE_HASH_BITS		8  /* 256 entries */
+#define ROUTE_TABLE_SIZE	(BIT(ROUTE_TABLE_HASH_BITS_MAX) \
+				* CLASS_ROUTE_SIZE)
+
+#define	PFE_TOTAL_DATA_SIZE	(ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
+
+#if PFE_TOTAL_DATA_SIZE > (12 * SZ_1M)
+#error DDR mapping above 12MiB
+#endif
+
+/* LMEM Mapping */
+#define BMU1_LMEM_BASEADDR	0
+#define BMU1_BUF_COUNT		256
+#define BMU1_LMEM_SIZE		(LMEM_BUF_SIZE * BMU1_BUF_COUNT)
+
+struct gemac_s {
+	void *gemac_base;
+	void *egpi_base;
+
+	/* GEMAC config */
+	int gemac_mode;
+	int gemac_speed;
+	int gemac_duplex;
+	int flags;
+	/* phy iface */
+	int phy_address;
+	int phy_mode;
+	struct mii_dev *bus;
+
+};
+
+struct pfe_mdio_info {
+	void *reg_base;
+	char *name;
+};
+
+struct pfe_eth_dev {
+	int gemac_port;
+	struct gemac_s *gem;
+	struct pfe_ddr_address pfe_addr;
+	struct udevice *dev;
+#ifdef CONFIG_PHYLIB
+	struct phy_device *phydev;
+#endif
+};
+
+int pfe_remove(struct pfe_ddr_address *pfe_addr);
+struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info);
+void pfe_set_mdio(int dev_id, struct mii_dev *bus);
+void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode);
+int gemac_initialize(bd_t *bis, int dev_id, char *devname);
+int pfe_init(struct pfe_ddr_address *pfe_addr);
+int pfe_eth_board_init(struct udevice *dev);
+
+#endif /* __PFE_ETH_H__ */
diff --git a/include/net/pfe_eth/pfe_firmware.h b/include/net/pfe_eth/pfe_firmware.h
new file mode 100644
index 0000000..b4fe313
--- /dev/null
+++ b/include/net/pfe_eth/pfe_firmware.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+/** @file
+ *  Contains all the defines to handle parsing and loading of PE firmware files.
+ */
+#ifndef __PFE_FIRMWARE_H__
+#define __PFE_FIRMWARE_H__
+
+int pfe_firmware_init(void);
+void pfe_firmware_exit(void);
+
+#endif
diff --git a/include/net/pfe_eth/pfe_mdio.h b/include/net/pfe_eth/pfe_mdio.h
new file mode 100644
index 0000000..972b879
--- /dev/null
+++ b/include/net/pfe_eth/pfe_mdio.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#ifndef _PFE_MDIO_H_
+#define _PFE_MDIO_H_
+
+int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id);
+
+#endif /* _PFE_MDIO_H_ */
diff --git a/include/net/tftp.h b/include/net/tftp.h
new file mode 100644
index 0000000..c411c9b
--- /dev/null
+++ b/include/net/tftp.h
@@ -0,0 +1,30 @@
+/*
+ *	LiMon - BOOTP/TFTP.
+ *
+ *	Copyright 1994, 1995, 2000 Neil Russell.
+ *	Copyright 2011 Comelit Group SpA
+ *	               Luca Ceresoli <luca.ceresoli@comelit.it>
+ *	(See License)
+ */
+
+#ifndef __TFTP_H__
+#define __TFTP_H__
+
+/**********************************************************************/
+/*
+ *	Global functions and variables.
+ */
+
+/* tftp.c */
+void tftp_start(enum proto_t protocol);	/* Begin TFTP get/put */
+
+#ifdef CONFIG_CMD_TFTPSRV
+void tftp_start_server(void);	/* Wait for incoming TFTP put */
+#endif
+
+extern ulong tftp_timeout_ms;
+extern int tftp_timeout_count_max;
+
+/**********************************************************************/
+
+#endif /* __TFTP_H__ */
diff --git a/include/netdev.h b/include/netdev.h
new file mode 100644
index 0000000..68a3fce
--- /dev/null
+++ b/include/netdev.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008
+ * Benjamin Warren, biggerbadderben@gmail.com
+ */
+
+/*
+ * netdev.h - definitions an prototypes for network devices
+ */
+
+#ifndef _NETDEV_H_
+#define _NETDEV_H_
+#include <phy_interface.h>
+
+/*
+ * Board and CPU-specific initialization functions
+ * board_eth_init() has highest priority.  cpu_eth_init() only
+ * gets called if board_eth_init() isn't instantiated or fails.
+ * Return values:
+ *      0: success
+ *     -1: failure
+ */
+
+int board_eth_init(bd_t *bis);
+int board_interface_eth_init(struct udevice *dev,
+			     phy_interface_t interface_type);
+int cpu_eth_init(bd_t *bis);
+
+/* Driver initialization prototypes */
+int at91emac_register(bd_t *bis, unsigned long iobase);
+int ax88180_initialize(bd_t *bis);
+int bcm_sf2_eth_register(bd_t *bis, u8 dev_num);
+int bfin_EMAC_initialize(bd_t *bis);
+int calxedaxgmac_initialize(u32 id, ulong base_addr);
+int cs8900_initialize(u8 dev_num, int base_addr);
+int dc21x4x_initialize(bd_t *bis);
+int designware_initialize(ulong base_addr, u32 interface);
+int dm9000_initialize(bd_t *bis);
+int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
+int e1000_initialize(bd_t *bis);
+int eepro100_initialize(bd_t *bis);
+int ep93xx_eth_initialize(u8 dev_num, int base_addr);
+int eth_3com_initialize (bd_t * bis);
+int ethoc_initialize(u8 dev_num, int base_addr);
+int fec_initialize (bd_t *bis);
+int fecmxc_initialize(bd_t *bis);
+int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
+int ftmac100_initialize(bd_t *bits);
+int ftmac110_initialize(bd_t *bits);
+void gt6426x_eth_initialize(bd_t *bis);
+int ks8851_mll_initialize(u8 dev_num, int base_addr);
+int lan91c96_initialize(u8 dev_num, int base_addr);
+int lpc32xx_eth_initialize(bd_t *bis);
+int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
+int mcdmafec_initialize(bd_t *bis);
+int mcffec_initialize(bd_t *bis);
+int mvgbe_initialize(bd_t *bis);
+int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr);
+int natsemi_initialize(bd_t *bis);
+int ne2k_register(void);
+int npe_initialize(bd_t *bis);
+int ns8382x_initialize(bd_t *bis);
+int pcnet_initialize(bd_t *bis);
+int ppc_4xx_eth_initialize (bd_t *bis);
+int rtl8139_initialize(bd_t *bis);
+int rtl8169_initialize(bd_t *bis);
+int scc_initialize(bd_t *bis);
+int sh_eth_initialize(bd_t *bis);
+int skge_initialize(bd_t *bis);
+int smc91111_initialize(u8 dev_num, int base_addr);
+int smc911x_initialize(u8 dev_num, int base_addr);
+int uec_standard_init(bd_t *bis);
+int uli526x_initialize(bd_t *bis);
+int armada100_fec_register(unsigned long base_addr);
+
+/* Boards with PCI network controllers can call this from their board_eth_init()
+ * function to initialize whatever's on board.
+ * Return value is total # of devices found */
+
+static inline int pci_eth_init(bd_t *bis)
+{
+	int num = 0;
+
+#ifdef CONFIG_PCI
+
+#ifdef CONFIG_EEPRO100
+	num += eepro100_initialize(bis);
+#endif
+#ifdef CONFIG_TULIP
+	num += dc21x4x_initialize(bis);
+#endif
+#ifdef CONFIG_E1000
+	num += e1000_initialize(bis);
+#endif
+#ifdef CONFIG_PCNET
+	num += pcnet_initialize(bis);
+#endif
+#ifdef CONFIG_NATSEMI
+	num += natsemi_initialize(bis);
+#endif
+#ifdef CONFIG_NS8382X
+	num += ns8382x_initialize(bis);
+#endif
+#if defined(CONFIG_RTL8139)
+	num += rtl8139_initialize(bis);
+#endif
+#if defined(CONFIG_RTL8169)
+	num += rtl8169_initialize(bis);
+#endif
+#if defined(CONFIG_ULI526X)
+	num += uli526x_initialize(bis);
+#endif
+
+#endif  /* CONFIG_PCI */
+	return num;
+}
+
+struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id);
+
+#ifdef CONFIG_PHYLIB
+struct phy_device;
+int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
+		struct mii_dev *bus, struct phy_device *phydev);
+#else
+/*
+ * Allow FEC to fine-tune MII configuration on boards which require this.
+ */
+int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
+#endif
+
+#endif /* _NETDEV_H_ */
diff --git a/include/ns16550.h b/include/ns16550.h
new file mode 100644
index 0000000..701efee
--- /dev/null
+++ b/include/ns16550.h
@@ -0,0 +1,254 @@
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/powerpc/boot/ns16550.h)
+ *
+ * Cleanup and unification
+ * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
+ *
+ * modified slightly to
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ *
+ * added support for port on 64-bit bus
+ * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
+ */
+
+/*
+ * Note that the following macro magic uses the fact that the compiler
+ * will not allocate storage for arrays of size 0
+ */
+
+#include <linux/types.h>
+
+#ifdef CONFIG_DM_SERIAL
+/*
+ * For driver model we always use one byte per register, and sort out the
+ * differences in the driver
+ */
+#define CONFIG_SYS_NS16550_REG_SIZE (-1)
+#endif
+
+#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
+#error "Please define NS16550 registers size."
+#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
+#define UART_REG(x) u32 x
+#elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
+#define UART_REG(x)						   \
+	unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
+	unsigned char x;
+#elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
+#define UART_REG(x)							\
+	unsigned char x;						\
+	unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
+#endif
+
+/**
+ * struct ns16550_platdata - information about a NS16550 port
+ *
+ * @base:		Base register address
+ * @reg_width:		IO accesses size of registers (in bytes)
+ * @reg_shift:		Shift size of registers (0=byte, 1=16bit, 2=32bit...)
+ * @clock:		UART base clock speed in Hz
+ * @bdf:		PCI slot/function (pci_dev_t)
+ */
+struct ns16550_platdata {
+	unsigned long base;
+	int reg_width;
+	int reg_shift;
+	int reg_offset;
+	int clock;
+	u32 fcr;
+#if defined(CONFIG_PCI) && defined(CONFIG_SPL)
+	int bdf;
+#endif
+};
+
+struct udevice;
+
+struct NS16550 {
+	UART_REG(rbr);		/* 0 */
+	UART_REG(ier);		/* 1 */
+	UART_REG(fcr);		/* 2 */
+	UART_REG(lcr);		/* 3 */
+	UART_REG(mcr);		/* 4 */
+	UART_REG(lsr);		/* 5 */
+	UART_REG(msr);		/* 6 */
+	UART_REG(spr);		/* 7 */
+#ifdef CONFIG_SOC_DA8XX
+	UART_REG(reg8);		/* 8 */
+	UART_REG(reg9);		/* 9 */
+	UART_REG(revid1);	/* A */
+	UART_REG(revid2);	/* B */
+	UART_REG(pwr_mgmt);	/* C */
+	UART_REG(mdr1);		/* D */
+#else
+	UART_REG(mdr1);		/* 8 */
+	UART_REG(reg9);		/* 9 */
+	UART_REG(regA);		/* A */
+	UART_REG(regB);		/* B */
+	UART_REG(regC);		/* C */
+	UART_REG(regD);		/* D */
+	UART_REG(regE);		/* E */
+	UART_REG(uasr);		/* F */
+	UART_REG(scr);		/* 10*/
+	UART_REG(ssr);		/* 11*/
+#endif
+#ifdef CONFIG_DM_SERIAL
+	struct ns16550_platdata *plat;
+#endif
+};
+
+#define thr rbr
+#define iir fcr
+#define dll rbr
+#define dlm ier
+
+typedef struct NS16550 *NS16550_t;
+
+/*
+ * These are the definitions for the FIFO Control Register
+ */
+#define UART_FCR_FIFO_EN	0x01 /* Fifo enable */
+#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
+
+#define UART_FCR_RXSR		0x02 /* Receiver soft reset */
+#define UART_FCR_TXSR		0x04 /* Transmitter soft reset */
+
+/* Ingenic JZ47xx specific UART-enable bit. */
+#define UART_FCR_UME		0x10
+
+/* Clear & enable FIFOs */
+#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
+			UART_FCR_RXSR |	\
+			UART_FCR_TXSR)
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_DTR	0x01		/* DTR   */
+#define UART_MCR_RTS	0x02		/* RTS   */
+#define UART_MCR_OUT1	0x04		/* Out 1 */
+#define UART_MCR_OUT2	0x08		/* Out 2 */
+#define UART_MCR_LOOP	0x10		/* Enable loopback test mode */
+#define UART_MCR_AFE	0x20		/* Enable auto-RTS/CTS */
+
+#define UART_MCR_DMA_EN	0x04
+#define UART_MCR_TX_DFR	0x08
+
+/*
+ * These are the definitions for the Line Control Register
+ *
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_WLS_MSK 0x03		/* character length select mask */
+#define UART_LCR_WLS_5	0x00		/* 5 bit character length */
+#define UART_LCR_WLS_6	0x01		/* 6 bit character length */
+#define UART_LCR_WLS_7	0x02		/* 7 bit character length */
+#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
+#define UART_LCR_STB	0x04		/* # stop Bits, off=1, on=1.5 or 2) */
+#define UART_LCR_PEN	0x08		/* Parity eneble */
+#define UART_LCR_EPS	0x10		/* Even Parity Select */
+#define UART_LCR_STKP	0x20		/* Stick Parity */
+#define UART_LCR_SBRK	0x40		/* Set Break */
+#define UART_LCR_BKSE	0x80		/* Bank select enable */
+#define UART_LCR_DLAB	0x80		/* Divisor latch access bit */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR	0x01		/* Data ready */
+#define UART_LSR_OE	0x02		/* Overrun */
+#define UART_LSR_PE	0x04		/* Parity error */
+#define UART_LSR_FE	0x08		/* Framing error */
+#define UART_LSR_BI	0x10		/* Break */
+#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
+#define UART_LSR_TEMT	0x40		/* Xmitter empty */
+#define UART_LSR_ERR	0x80		/* Error */
+
+#define UART_MSR_DCD	0x80		/* Data Carrier Detect */
+#define UART_MSR_RI	0x40		/* Ring Indicator */
+#define UART_MSR_DSR	0x20		/* Data Set Ready */
+#define UART_MSR_CTS	0x10		/* Clear to Send */
+#define UART_MSR_DDCD	0x08		/* Delta DCD */
+#define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
+#define UART_MSR_DDSR	0x02		/* Delta DSR */
+#define UART_MSR_DCTS	0x01		/* Delta CTS */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
+#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
+
+#define UART_IIR_MSI	0x00	/* Modem status interrupt */
+#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
+#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
+#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
+#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
+#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
+#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
+
+/* useful defaults for LCR */
+#define UART_LCR_8N1	0x03
+
+void NS16550_init(NS16550_t com_port, int baud_divisor);
+void NS16550_putc(NS16550_t com_port, char c);
+char NS16550_getc(NS16550_t com_port);
+int NS16550_tstc(NS16550_t com_port);
+void NS16550_reinit(NS16550_t com_port, int baud_divisor);
+
+/**
+ * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
+ *
+ * Given the UART input clock and required baudrate, calculate the divisor
+ * that should be used.
+ *
+ * @port:	UART port
+ * @clock:	UART input clock speed in Hz
+ * @baudrate:	Required baud rate
+ * @return baud rate divisor that should be used
+ */
+int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate);
+
+/**
+ * ns16550_serial_ofdata_to_platdata() - convert DT to platform data
+ *
+ * Decode a device tree node for an ns16550 device. This includes the
+ * register base address and register shift properties. The caller must set
+ * up the clock frequency.
+ *
+ * @dev:	dev to decode platform data for
+ * @return:	0 if OK, -EINVAL on error
+ */
+int ns16550_serial_ofdata_to_platdata(struct udevice *dev);
+
+/**
+ * ns16550_serial_probe() - probe a serial port
+ *
+ * This sets up the serial port ready for use, except for the baud rate
+ * @return 0, or -ve on error
+ */
+int ns16550_serial_probe(struct udevice *dev);
+
+/**
+ * struct ns16550_serial_ops - ns16550 serial operations
+ *
+ * These should be used by the client driver for the driver's 'ops' member
+ */
+extern const struct dm_serial_ops ns16550_serial_ops;
diff --git a/include/ns87308.h b/include/ns87308.h
new file mode 100644
index 0000000..d5ccd3b
--- /dev/null
+++ b/include/ns87308.h
@@ -0,0 +1,233 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ */
+
+#ifndef _NS87308_H_
+#define _NS87308_H_
+
+#include <asm/pci_io.h>
+
+/* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
+   functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
+
+void initialise_ns87308(void);
+
+/*
+ * The following struct represents the GPIO registers on the NS87308/NS97307
+ */
+struct GPIO
+{
+  unsigned char dta1;  /* 0 data port 1 */
+  unsigned char dir1;  /* 1 direction port 1 */
+  unsigned char out1;  /* 2 output type port 1 */
+  unsigned char puc1;  /* 3 pull-up control port 1 */
+  unsigned char dta2;  /* 4 data port 2 */
+  unsigned char dir2;  /* 5 direction port 2 */
+  unsigned char out2;  /* 6 output type port 2 */
+  unsigned char puc2;  /* 7 pull-up control port 2  */
+};
+
+/*
+ * The following represents the power management registers on the NS87308/NS97307
+ */
+#define PWM_FER1 0  /* 0 function enable reg. 1 */
+#define PWM_FER2 1  /* 1 function enable reg. 2 */
+#define PWM_PMC1 2  /* 2 power mgmt. control 1 */
+#define PWM_PMC2 3  /* 3 power mgmt. control 2 */
+#define PWM_PMC3 4  /* 4 power mgmt. control 3 */
+#define PWM_WDTO 5  /* 5 watchdog time-out */
+#define PWM_WDCF 6  /* 6 watchdog config. */
+#define PWM_WDST 7  /* 7 watchdog status  */
+
+/*PNP config registers:
+ * these depend on the stated of BADDR1 and BADDR0 on startup
+ * so there's three versions here with the last two digits indicating
+ * for which configuration their valid
+ * the 1st of the two digits indicates the state of BADDR1
+ * the 2st of the two digits indicates the state of BADDR0
+ */
+
+
+#define IO_INDEX_OFFSET_0x 0x0279  /* full PnP isa Mode */
+#define IO_INDEX_OFFSET_10 0x015C  /* PnP motherboard mode */
+#define IO_INDEX_OFFSET_11 0x002E  /* PnP motherboard mode */
+#define IO_DATA_OFFSET_0x  0x0A79  /* full PnP isa Mode */
+#define IO_DATA_OFFSET_10  0x015D  /* PnP motherboard mode */
+#define IO_DATA_OFFSET_11  0x002F  /* PnP motherboard mode */
+
+#if defined(CONFIG_SYS_NS87308_BADDR_0x)
+#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
+#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
+#elif defined(CONFIG_SYS_NS87308_BADDR_10)
+#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
+#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
+#elif defined(CONFIG_SYS_NS87308_BADDR_11)
+#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
+#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
+#endif
+
+/* PnP register definitions */
+
+#define SET_RD_DATA_PORT    0x00
+#define SERIAL_ISOLATION    0x01
+#define CONFIG_CONTROL      0x02
+#define WAKE_CSN            0x03
+#define RES_DATA            0x04
+#define STATUS              0x05
+#define SET_CSN             0x06
+#define LOGICAL_DEVICE      0x07
+
+/*vendor defined values */
+#define SID_REG             0x20
+#define SUPOERIO_CONF1      0x21
+#define SUPOERIO_CONF2      0x22
+#define PGCS_INDEX          0x23
+#define PGCS_DATA           0x24
+
+/* values above 30 are different for each logical device
+   but I can't be arsed to enter them all. the ones here
+   are pretty consistent between all logical devices
+   feel free to correct the situation if you want.. ;)
+   */
+#define ACTIVATE            0x30
+#define ACTIVATE_OFF        0x00
+#define ACTIVATE_ON         0x01
+
+#define BASE_ADDR_HIGH      0x60
+#define BASE_ADDR_LOW       0x61
+#define LUN_CONFIG_REG		0xF0
+#define DBASE_HIGH			0x60	/* SIO KBC data base address, 15:8 */
+#define DBASE_LOW			0x61	/* SIO KBC data base address,  7:0 */
+#define CBASE_HIGH			0x62	/* SIO KBC command base addr, 15:8 */
+#define CBASE_LOW			0x63	/* SIO KBC command base addr,  7:0 */
+
+/* the logical devices*/
+#define LDEV_KBC1           0x00	/* 2 devices for keyboard and mouse controller*/
+#define LDEV_KBC2           0x01
+#define LDEV_MOUSE          0x01
+#define LDEV_RTC_APC        0x02	/*Real Time Clock and Advanced Power Control*/
+#define LDEV_FDC            0x03	/*floppy disk controller*/
+#define LDEV_PARP           0x04	/*Parallel port*/
+#define LDEV_UART2          0x05
+#define LDEV_UART1          0x06
+#define LDEV_GPIO           0x07    /*General Purpose IO and chip select output signals*/
+#define LDEV_POWRMAN        0x08    /*Power Managment*/
+
+#define CONFIG_SYS_NS87308_KBC1	(1 << LDEV_KBC1)
+#define CONFIG_SYS_NS87308_KBC2	(1 << LDEV_KBC2)
+#define CONFIG_SYS_NS87308_MOUSE	(1 << LDEV_MOUSE)
+#define CONFIG_SYS_NS87308_RTC_APC	(1 << LDEV_RTC_APC)
+#define CONFIG_SYS_NS87308_FDC		(1 << LDEV_FDC)
+#define CONFIG_SYS_NS87308_PARP	(1 << LDEV_PARP)
+#define CONFIG_SYS_NS87308_UART2	(1 << LDEV_UART2)
+#define CONFIG_SYS_NS87308_UART1	(1 << LDEV_UART1)
+#define CONFIG_SYS_NS87308_GPIO	(1 << LDEV_GPIO)
+#define CONFIG_SYS_NS87308_POWRMAN	(1 << LDEV_POWRMAN)
+
+/*some functions and macro's for doing configuration */
+
+static inline void read_pnp_config(unsigned char index, unsigned char *data)
+{
+    pci_writeb(index,IO_INDEX);
+    pci_readb(IO_DATA, *data);
+}
+
+static inline void write_pnp_config(unsigned char index, unsigned char data)
+{
+    pci_writeb(index,IO_INDEX);
+    pci_writeb(data, IO_DATA);
+}
+
+static inline void pnp_set_device(unsigned char dev)
+{
+    write_pnp_config(LOGICAL_DEVICE, dev);
+}
+
+static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
+{
+    pci_writeb(index, CONFIG_SYS_ISA_IO + base);
+    eieio();
+    pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
+}
+
+/*void write_pnp_config(unsigned char index, unsigned char data);
+void pnp_set_device(unsigned char dev);
+*/
+
+#define PNP_SET_DEVICE_BASE(dev,base) \
+   pnp_set_device(dev); \
+   write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
+   write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
+   write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
+   write_pnp_config(ACTIVATE, ACTIVATE_ON);
+
+#define PNP_ACTIVATE_DEVICE(dev) \
+   pnp_set_device(dev); \
+   write_pnp_config(ACTIVATE, ACTIVATE_ON);
+
+#define PNP_DEACTIVATE_DEVICE(dev) \
+   pnp_set_device(dev); \
+   write_pnp_config(ACTIVATE, ACTIVATE_OFF);
+
+
+static inline void write_pgcs_config(unsigned char index, unsigned char data)
+{
+    write_pnp_config(PGCS_INDEX, index);
+    write_pnp_config(PGCS_DATA, data);
+}
+
+/* these macrose configure the 3 CS lines
+   on the sandpoint board these controll NVRAM
+   CS0 is connected to NVRAMCS
+   CS1 is connected to NVRAMAS0
+   CS2 is connected to NVRAMAS1
+   */
+#define PGCS_CS_ASSERT_ON_WRITE 0x10
+#define PGCS_CS_ASSERT_ON_READ  0x20
+
+#define PNP_PGCS_CSLINE_BASE(cs, base) \
+  write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
+  write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
+
+#define PNP_PGCS_CSLINE_CONF(cs, conf) \
+  write_pgcs_config(((cs) << 2) + 2, (conf) );
+
+
+/* The following sections are for 87308 extensions to the standard compoents it emulates */
+
+/* extensions to 16550*/
+
+#define MCR_MDSL_MSK    0xe0 /*mode select mask*/
+#define MCR_MDSL_UART   0x00 /*uart, default*/
+#define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
+#define MCR_MDSL_SIR    0x03 /*SIR*/
+#define MCR_MDSL_CIR    0x06 /*Consumer IR*/
+
+#define FCR_TXFTH0      0x10    /* these bits control threshod of data level in fifo */
+#define FCR_TXFTH1      0x20    /* for interrupt trigger */
+
+/*
+ * Default NS87308 configuration
+ */
+#ifndef CONFIG_SYS_NS87308_KBC1_BASE
+#define CONFIG_SYS_NS87308_KBC1_BASE	0x0060
+#endif
+#ifndef CONFIG_SYS_NS87308_RTC_BASE
+#define CONFIG_SYS_NS87308_RTC_BASE	0x0070
+#endif
+#ifndef CONFIG_SYS_NS87308_FDC_BASE
+#define CONFIG_SYS_NS87308_FDC_BASE	0x03F0
+#endif
+#ifndef CONFIG_SYS_NS87308_LPT_BASE
+#define CONFIG_SYS_NS87308_LPT_BASE	0x0278
+#endif
+#ifndef CONFIG_SYS_NS87308_UART1_BASE
+#define CONFIG_SYS_NS87308_UART1_BASE	0x03F8
+#endif
+#ifndef CONFIG_SYS_NS87308_UART2_BASE
+#define CONFIG_SYS_NS87308_UART2_BASE	0x02F8
+#endif
+
+#endif /*_NS87308_H_*/
diff --git a/include/nuvoton_nct6102d.h b/include/nuvoton_nct6102d.h
new file mode 100644
index 0000000..a02f392
--- /dev/null
+++ b/include/nuvoton_nct6102d.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _NUVOTON_NCT6102D_H_
+#define _NUVOTON_NCT6102D_H_
+
+/* I/O address of Nuvoton Super IO chip */
+#define NCT6102D_IO_PORT	0x4e
+
+/* Extended Function Enable Registers */
+#define NCT_EFER (NCT6102D_IO_PORT + 0)
+/* Extended Function Index Register (same as EFER) */
+#define NCT_EFIR (NCT6102D_IO_PORT + 0)
+/* Extended Function Data Register */
+#define NCT_EFDR (NCT_EFIR + 1)
+
+#define NCT_LD_SELECT_REG	0x07
+
+/* Logical device number */
+#define NCT6102D_LD_UARTA	0x02
+#define NCT6102D_LD_WDT		0x08
+
+#define NCT6102D_UARTA_ENABLE	0x30
+#define NCT6102D_WDT_TIMEOUT	0xf1
+
+#define NCT_ENTRY_KEY		0x87
+#define NCT_EXIT_KEY		0xaa
+
+int nct6102d_wdt_disable(void);
+
+#endif /* _NUVOTON_NCT6102D_H_ */
diff --git a/include/nvme.h b/include/nvme.h
new file mode 100644
index 0000000..2cdf8ce
--- /dev/null
+++ b/include/nvme.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 NXP Semiconductors
+ * Copyright (C) 2017 Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef __NVME_H__
+#define __NVME_H__
+
+struct nvme_dev;
+
+/**
+ * nvme_identify - identify controller or namespace capabilities and status
+ *
+ * This issues an identify command to the NVMe controller to return a data
+ * buffer that describes the controller or namespace capabilities and status.
+ *
+ * @dev:	NVMe controller device
+ * @nsid:	0 for controller, namespace id for namespace to identify
+ * @cns:	1 for controller, 0 for namespace
+ * @dma_addr:	dma buffer address to store the identify result
+ * @return:	0 on success, -ETIMEDOUT on command execution timeout,
+ *		-EIO on command execution fails
+ */
+int nvme_identify(struct nvme_dev *dev, unsigned nsid,
+		  unsigned cns, dma_addr_t dma_addr);
+
+/**
+ * nvme_get_features - retrieve the attributes of the feature specified
+ *
+ * This retrieves the attributes of the feature specified.
+ *
+ * @dev:	NVMe controller device
+ * @fid:	feature id to provide data
+ * @nsid:	namespace id the command applies to
+ * @dma_addr:	data structure used as part of the specified feature
+ * @result:	command-specific result in the completion queue entry
+ * @return:	0 on success, -ETIMEDOUT on command execution timeout,
+ *		-EIO on command execution fails
+ */
+int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
+		      dma_addr_t dma_addr, u32 *result);
+
+/**
+ * nvme_set_features - specify the attributes of the feature indicated
+ *
+ * This specifies the attributes of the feature indicated.
+ *
+ * @dev:	NVMe controller device
+ * @fid:	feature id to provide data
+ * @dword11:	command-specific input parameter
+ * @dma_addr:	data structure used as part of the specified feature
+ * @result:	command-specific result in the completion queue entry
+ * @return:	0 on success, -ETIMEDOUT on command execution timeout,
+ *		-EIO on command execution fails
+ */
+int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
+		      dma_addr_t dma_addr, u32 *result);
+
+/**
+ * nvme_scan_namespace - scan all namespaces attached to NVMe controllers
+ *
+ * This probes all registered NVMe uclass device drivers in the system,
+ * and tries to find all namespaces attached to the NVMe controllers.
+ *
+ * @return:	0 on success, -ve on error
+ */
+int nvme_scan_namespace(void);
+
+/**
+ * nvme_print_info - print detailed NVMe controller and namespace information
+ *
+ * This prints out detailed human readable NVMe controller and namespace
+ * information which is very useful for debugging.
+ *
+ * @udev:	NVMe controller device
+ * @return:	0 on success, -EIO if NVMe identify command fails
+ */
+int nvme_print_info(struct udevice *udev);
+
+/**
+ * nvme_get_namespace_id - return namespace identifier
+ *
+ * This returns the namespace identifier.
+ *
+ * @udev:	NVMe controller device
+ * @ns_id:	Place where to put the name space identifier
+ * @eui64:	Place where to put the IEEE Extended Unique Identifier
+ * @return:	0 on success, -ve on error
+ */
+int nvme_get_namespace_id(struct udevice *udev, u32 *ns_id, u8 *eui64);
+
+#endif /* __NVME_H__ */
diff --git a/include/of_live.h b/include/of_live.h
new file mode 100644
index 0000000..b8561f5
--- /dev/null
+++ b/include/of_live.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * Support for a 'live' (as opposed to flat) device tree
+ */
+
+#ifndef _OF_LIVE_H
+#define _OF_LIVE_H
+
+struct device_node;
+
+/**
+ * of_live_build() - build a live (hierarchical) tree from a flat DT
+ *
+ * @fdt_blob: Input tree to convert
+ * @rootp: Returns live tree that was created
+ * @return 0 if OK, -ve on error
+ */
+int of_live_build(const void *fdt_blob, struct device_node **rootp);
+
+#endif
diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h
new file mode 100644
index 0000000..995f0aa
--- /dev/null
+++ b/include/onenand_uboot.h
@@ -0,0 +1,55 @@
+/*
+ *  Header file for OneNAND support for U-Boot
+ *
+ *  Adaptation from kernel to U-Boot
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __UBOOT_ONENAND_H
+#define __UBOOT_ONENAND_H
+
+#include <linux/types.h>
+
+/* Forward declarations */
+struct mtd_info;
+struct mtd_oob_ops;
+struct erase_info;
+struct onenand_chip;
+
+extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
+
+/* board */
+extern int onenand_board_init(struct mtd_info *);
+
+/* Functions */
+extern void onenand_init(void);
+extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
+			size_t * retlen, u_char * buf);
+extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
+extern int onenand_write(struct mtd_info *mtd, loff_t from, size_t len,
+			 size_t * retlen, const u_char * buf);
+extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr);
+
+extern char *onenand_print_device_info(int device, int version);
+
+extern unsigned onenand_block(struct onenand_chip *this, loff_t addr);
+
+extern loff_t onenand_addr(struct onenand_chip *this, int block);
+
+extern int flexonenand_region(struct mtd_info *mtd, loff_t addr);
+
+extern int flexonenand_set_boundary(struct mtd_info *mtd, int die,
+					int boundary, int lock);
+
+/* SPL */
+int onenand_spl_read_block(int block, int offset, int len, void *dst);
+void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst);
+
+#endif /* __UBOOT_ONENAND_H */
diff --git a/include/opensbi.h b/include/opensbi.h
new file mode 100644
index 0000000..9f1d62e
--- /dev/null
+++ b/include/opensbi.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Based on include/sbi/{fw_dynamic.h,sbi_scratch.h} from the OpenSBI project.
+ */
+#ifndef OPENSBI_H
+#define OPENSBI_H
+
+/** Expected value of info magic ('OSBI' ascii string in hex) */
+#define FW_DYNAMIC_INFO_MAGIC_VALUE		0x4942534f
+
+/** Maximum supported info version */
+#define FW_DYNAMIC_INFO_VERSION			0x1
+
+/** Possible next mode values */
+#define FW_DYNAMIC_INFO_NEXT_MODE_U		0x0
+#define FW_DYNAMIC_INFO_NEXT_MODE_S		0x1
+#define FW_DYNAMIC_INFO_NEXT_MODE_M		0x3
+
+enum sbi_scratch_options {
+	/** Disable prints during boot */
+	SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
+};
+
+/** Representation dynamic info passed by previous booting stage */
+struct fw_dynamic_info {
+	/** Info magic */
+	unsigned long magic;
+	/** Info version */
+	unsigned long version;
+	/** Next booting stage address */
+	unsigned long next_addr;
+	/** Next booting stage mode */
+	unsigned long next_mode;
+	/** Options for OpenSBI library */
+	unsigned long options;
+} __packed;
+
+#endif
diff --git a/include/os.h b/include/os.h
new file mode 100644
index 0000000..7a4f78b
--- /dev/null
+++ b/include/os.h
@@ -0,0 +1,378 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Operating System Interface
+ *
+ * This provides access to useful OS routines for the sandbox architecture.
+ * They are kept in a separate file so we can include system headers.
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ */
+
+#ifndef __OS_H__
+#define __OS_H__
+
+#include <linux/types.h>
+
+struct rtc_time;
+struct sandbox_state;
+
+/**
+ * Access to the OS read() system call
+ *
+ * \param fd	File descriptor as returned by os_open()
+ * \param buf	Buffer to place data
+ * \param count	Number of bytes to read
+ * \return number of bytes read, or -1 on error
+ */
+ssize_t os_read(int fd, void *buf, size_t count);
+
+/**
+ * Access to the OS write() system call
+ *
+ * \param fd	File descriptor as returned by os_open()
+ * \param buf	Buffer containing data to write
+ * \param count	Number of bytes to write
+ * \return number of bytes written, or -1 on error
+ */
+ssize_t os_write(int fd, const void *buf, size_t count);
+
+/**
+ * Access to the OS lseek() system call
+ *
+ * \param fd	File descriptor as returned by os_open()
+ * \param offset	File offset (based on whence)
+ * \param whence	Position offset is relative to (see below)
+ * \return new file offset
+ */
+off_t os_lseek(int fd, off_t offset, int whence);
+
+/* Defines for "whence" in os_lseek() */
+#define OS_SEEK_SET	0
+#define OS_SEEK_CUR	1
+#define OS_SEEK_END	2
+
+/**
+ * Access to the OS open() system call
+ *
+ * \param pathname	Pathname of file to open
+ * \param flags		Flags, like OS_O_RDONLY, OS_O_RDWR
+ * \return file descriptor, or -1 on error
+ */
+int os_open(const char *pathname, int flags);
+
+#define OS_O_RDONLY	0
+#define OS_O_WRONLY	1
+#define OS_O_RDWR	2
+#define OS_O_MASK	3	/* Mask for read/write flags */
+#define OS_O_CREAT	0100
+#define OS_O_TRUNC	01000
+
+/**
+ * Access to the OS close() system call
+ *
+ * \param fd	File descriptor to close
+ * \return 0 on success, -1 on error
+ */
+int os_close(int fd);
+
+/**
+ * Access to the OS unlink() system call
+ *
+ * \param pathname Path of file to delete
+ * \return 0 for success, other for error
+ */
+int os_unlink(const char *pathname);
+
+/**
+ * Access to the OS exit() system call
+ *
+ * This exits with the supplied return code, which should be 0 to indicate
+ * success.
+ *
+ * @param exit_code	exit code for U-Boot
+ */
+void os_exit(int exit_code) __attribute__((noreturn));
+
+/**
+ * Put tty into raw mode to mimic serial console better
+ *
+ * @param fd		File descriptor of stdin (normally 0)
+ * @param allow_sigs	Allow Ctrl-C, Ctrl-Z to generate signals rather than
+ *			be handled by U-Boot
+ */
+void os_tty_raw(int fd, bool allow_sigs);
+
+/**
+ * Restore the tty to its original mode
+ *
+ * Call this to restore the original terminal mode, after it has been changed
+ * by os_tty_raw(). This is an internal function.
+ */
+void os_fd_restore(void);
+
+/**
+ * Acquires some memory from the underlying os.
+ *
+ * \param length	Number of bytes to be allocated
+ * \return Pointer to length bytes or NULL on error
+ */
+void *os_malloc(size_t length);
+
+/**
+ * Free memory previous allocated with os_malloc()/os_realloc()
+ *
+ * This returns the memory to the OS.
+ *
+ * \param ptr		Pointer to memory block to free
+ */
+void os_free(void *ptr);
+
+/**
+ * Reallocate previously-allocated memory to increase/decrease space
+ *
+ * This works in a similar way to the C library realloc() function. If
+ * length is 0, then ptr is freed. Otherwise the space used by ptr is
+ * expanded or reduced depending on whether length is larger or smaller
+ * than before.
+ *
+ * If ptr is NULL, then this is similar to calling os_malloc().
+ *
+ * This function may need to move the memory block to make room for any
+ * extra space, in which case the new pointer is returned.
+ *
+ * \param ptr		Pointer to memory block to reallocate
+ * \param length	New length for memory block
+ * \return pointer to new memory block, or NULL on failure or if length
+ *	is 0.
+ */
+void *os_realloc(void *ptr, size_t length);
+
+/**
+ * Access to the usleep function of the os
+ *
+ * \param usec Time to sleep in micro seconds
+ */
+void os_usleep(unsigned long usec);
+
+/**
+ * Gets a monotonic increasing number of nano seconds from the OS
+ *
+ * \return A monotonic increasing time scaled in nano seconds
+ */
+uint64_t os_get_nsec(void);
+
+/**
+ * Parse arguments and update sandbox state.
+ *
+ * @param state		Sandbox state to update
+ * @param argc		Argument count
+ * @param argv		Argument vector
+ * @return 0 if ok, and program should continue;
+ *	1 if ok, but program should stop;
+ *	-1 on error: program should terminate.
+ */
+int os_parse_args(struct sandbox_state *state, int argc, char *argv[]);
+
+/*
+ * Types of directory entry that we support. See also os_dirent_typename in
+ * the C file.
+ */
+enum os_dirent_t {
+	OS_FILET_REG,		/* Regular file */
+	OS_FILET_LNK,		/* Symbolic link */
+	OS_FILET_DIR,		/* Directory */
+	OS_FILET_UNKNOWN,	/* Something else */
+
+	OS_FILET_COUNT,
+};
+
+/** A directory entry node, containing information about a single dirent */
+struct os_dirent_node {
+	struct os_dirent_node *next;	/* Pointer to next node, or NULL */
+	ulong size;			/* Size of file in bytes */
+	enum os_dirent_t type;		/* Type of entry */
+	char name[0];			/* Name of entry */
+};
+
+/**
+ * Get a directionry listing
+ *
+ * This allocates and returns a linked list containing the directory listing.
+ *
+ * @param dirname	Directory to examine
+ * @param headp		Returns pointer to head of linked list, or NULL if none
+ * @return 0 if ok, -ve on error
+ */
+int os_dirent_ls(const char *dirname, struct os_dirent_node **headp);
+
+/**
+ * Free directory list
+ *
+ * This frees a linked list containing a directory listing.
+ *
+ * @param node		Pointer to head of linked list
+ */
+void os_dirent_free(struct os_dirent_node *node);
+
+/**
+ * Get the name of a directory entry type
+ *
+ * @param type		Type to check
+ * @return string containing the name of that type, or "???" if none/invalid
+ */
+const char *os_dirent_get_typename(enum os_dirent_t type);
+
+/**
+ * Get the size of a file
+ *
+ * @param fname		Filename to check
+ * @param size		size of file is returned if no error
+ * @return 0 on success or -1 if an error ocurred
+ */
+int os_get_filesize(const char *fname, loff_t *size);
+
+/**
+ * Write a character to the controlling OS terminal
+ *
+ * This bypasses the U-Boot console support and writes directly to the OS
+ * stdout file descriptor.
+ *
+ * @param ch	Character to write
+ */
+void os_putc(int ch);
+
+/**
+ * Write a string to the controlling OS terminal
+ *
+ * This bypasses the U-Boot console support and writes directly to the OS
+ * stdout file descriptor.
+ *
+ * @param str	String to write (note that \n is not appended)
+ */
+void os_puts(const char *str);
+
+/**
+ * Write the sandbox RAM buffer to a existing file
+ *
+ * @param fname		Filename to write memory to (simple binary format)
+ * @return 0 if OK, -ve on error
+ */
+int os_write_ram_buf(const char *fname);
+
+/**
+ * Read the sandbox RAM buffer from an existing file
+ *
+ * @param fname		Filename containing memory (simple binary format)
+ * @return 0 if OK, -ve on error
+ */
+int os_read_ram_buf(const char *fname);
+
+/**
+ * Jump to a new executable image
+ *
+ * This uses exec() to run a new executable image, after putting it in a
+ * temporary file. The same arguments and environment are passed to this
+ * new image, with the addition of:
+ *
+ *	-j <filename>	Specifies the filename the image was written to. The
+ *			calling image may want to delete this at some point.
+ *	-m <filename>	Specifies the file containing the sandbox memory
+ *			(ram_buf) from this image, so that the new image can
+ *			have access to this. It also means that the original
+ *			memory filename passed to U-Boot will be left intact.
+ *
+ * @param dest		Buffer containing executable image
+ * @param size		Size of buffer
+ */
+int os_jump_to_image(const void *dest, int size);
+
+/**
+ * os_find_u_boot() - Determine the path to U-Boot proper
+ *
+ * This function is intended to be called from within sandbox SPL. It uses
+ * a few heuristics to find U-Boot proper. Normally it is either in the same
+ * directory, or the directory above (since u-boot-spl is normally in an
+ * spl/ subdirectory when built).
+ *
+ * @fname:	Place to put full path to U-Boot
+ * @maxlen:	Maximum size of @fname
+ * @return 0 if OK, -NOSPC if the filename is too large, -ENOENT if not found
+ */
+int os_find_u_boot(char *fname, int maxlen);
+
+/**
+ * os_spl_to_uboot() - Run U-Boot proper
+ *
+ * When called from SPL, this runs U-Boot proper. The filename is obtained by
+ * calling os_find_u_boot().
+ *
+ * @fname:	Full pathname to U-Boot executable
+ * @return 0 if OK, -ve on error
+ */
+int os_spl_to_uboot(const char *fname);
+
+/**
+ * Read the current system time
+ *
+ * This reads the current Local Time and places it into the provided
+ * structure.
+ *
+ * @param rt		Place to put system time
+ */
+void os_localtime(struct rtc_time *rt);
+
+/**
+ * os_abort() - Raise SIGABRT to exit sandbox (e.g. to debugger)
+ */
+void os_abort(void);
+
+/**
+ * os_mprotect_allow() - Remove write-protection on a region of memory
+ *
+ * The start and length will be page-aligned before use.
+ *
+ * @start:	Region start
+ * @len:	Region length in bytes
+ * @return 0 if OK, -1 on error from mprotect()
+ */
+int os_mprotect_allow(void *start, size_t len);
+
+/**
+ * os_write_file() - Write a file to the host filesystem
+ *
+ * This can be useful when debugging for writing data out of sandbox for
+ * inspection by external tools.
+ *
+ * @name:	File path to write to
+ * @buf:	Data to write
+ * @size:	Size of data to write
+ * @return 0 if OK, -ve on error
+ */
+int os_write_file(const char *name, const void *buf, int size);
+
+/**
+ * os_read_file() - Read a file from the host filesystem
+ *
+ * This can be useful when reading test data into sandbox for use by test
+ * routines. The data is allocated using os_malloc() and should be freed by
+ * the caller.
+ *
+ * @name:	File path to read from
+ * @bufp:	Returns buffer containing data read
+ * @sizep:	Returns size of data
+ * @return 0 if OK, -ve on error
+ */
+int os_read_file(const char *name, void **bufp, int *sizep);
+
+/*
+ * os_find_text_base() - Find the text section in this running process
+ *
+ * This tries to find the address of the text section in this running process.
+ * It can be useful to map the address of functions to the address listed in
+ * the u-boot.map file.
+ *
+ * @return address if found, else NULL
+ */
+void *os_find_text_base(void);
+
+#endif
diff --git a/include/palmas.h b/include/palmas.h
new file mode 100644
index 0000000..20c7e48
--- /dev/null
+++ b/include/palmas.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012-2013
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef PALMAS_H
+#define PALMAS_H
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses, TW6035/37 */
+#define TWL603X_CHIP_P1		0x48	/* Page 1 */
+#define TWL603X_CHIP_P2		0x49	/* Page 2 */
+#define TWL603X_CHIP_P3		0x4a	/* Page 3 */
+
+/* TPS659038/39 */
+#define TPS65903X_CHIP_P1	0x58	/* Page 1 */
+
+/* Page 1 registers (0x1XY translates to page 1, reg addr 0xXY): */
+
+/* LDO1 control/voltage */
+#define LDO1_CTRL		0x50
+#define LDO1_VOLTAGE		0x51
+
+/* LDO1 control/voltage for LP873x */
+#define LP873X_LDO1_ADDR	0x60
+#define LP873X_LDO1_CTRL	0x9
+#define LP873X_LDO1_VOLTAGE	0xa
+#define LP873X_LDO_VOLT_3V0	0x19
+#define LP873X_LDO_VOLT_1V8	0xa
+#define LP873X_LDO_CTRL_EN	(0x1 << 0)
+#define LP873X_LDO_CTRL_EN_PINCTRL	(0x1 << 1)
+#define LP873X_LDO_CTRL_RDIS_EN	(0x1 << 2)
+
+/* LDO2 control/voltage */
+#define LDO2_CTRL		0x52
+#define LDO2_VOLTAGE		0x53
+
+/* LDO2 control/voltage */
+#define LDO4_CTRL		0x5e
+#define LDO4_VOLTAGE		0x5f
+
+/* LDO9 control/voltage */
+#define LDO9_CTRL		0x60
+#define LDO9_VOLTAGE		0x61
+
+/* LDOUSB control/voltage */
+#define LDOUSB_CTRL		0x64
+#define LDOUSB_VOLTAGE		0x65
+#define LDO_CTRL		0x6a
+
+/* Control of 32 kHz audio clock */
+#define CLK32KGAUDIO_CTRL	0xd5
+
+/* SYSEN2_CTRL for VCC_3v3_AUX supply on the sEVM */
+#define SYSEN2_CTRL		0xd9
+
+/*
+ * Bit field definitions for LDOx_CTRL, SYSENx_CTRL
+ * and some other xxx_CTRL resources:
+ */
+#define LDO9_BYP_EN		(1 << 6)	/* LDO9 only! */
+#define RSC_STAT_ON		(1 << 4)	/* RO status bit! */
+#define RSC_MODE_SLEEP		(1 << 2)
+#define RSC_MODE_ACTIVE		(1 << 0)
+
+/* Some LDO voltage values */
+#define LDO_VOLT_OFF		0
+#define LDO_VOLT_1V8		0x13
+#define LDO_VOLT_3V0		0x2b
+#define LDO_VOLT_3V3		0x31
+/* Request bypass, LDO9 only */
+#define LDO9_BYPASS		0x3f
+
+/* SMPS7_CTRL */
+#define SMPS7_CTRL		0x30
+
+/* SMPS9_CTRL */
+#define SMPS9_CTRL		0x38
+#define SMPS9_VOLTAGE		0x3b
+
+/* SMPS10_CTRL */
+#define SMPS10_CTRL		0x3c
+#define SMPS10_MODE_ACTIVE_D	0x0d
+
+/* Bit field definitions for SMPSx_CTRL */
+#define SMPS_MODE_ACT_AUTO	1
+#define SMPS_MODE_ACT_ECO	2
+#define SMPS_MODE_ACT_FPWM	3
+#define SMPS_MODE_SLP_AUTO	(1 << 2)
+#define SMPS_MODE_SLP_ECO	(2 << 2)
+#define SMPS_MODE_SLP_FPWM	(3 << 2)
+
+/*
+ * Some popular SMPS voltages, all with RANGE=1; note
+ * that RANGE cannot be changed on the fly
+ */
+#define SMPS_VOLT_OFF		0
+#define SMPS_VOLT_1V2		0x90
+#define SMPS_VOLT_1V8		0xae
+#define SMPS_VOLT_2V1		0xbd
+#define SMPS_VOLT_3V0		0xea
+#define SMPS_VOLT_3V3		0xf9
+
+/* Backup Battery & VRTC Control */
+#define BB_VRTC_CTRL		0xa8
+/* Bit definitions for BB_VRTC_CTRL */
+#define VRTC_EN_SLP		(1 << 6)
+#define VRTC_EN_OFF		(1 << 5)
+#define VRTC_PWEN		(1 << 4)
+#define BB_LOW_ICHRG		(1 << 3)
+#define BB_HIGH_ICHRG		(0 << 3)
+#define BB_VSEL_3V0		(0 << 1)
+#define BB_VSEL_2V5		(1 << 1)
+#define BB_VSEL_3V15		(2 << 1)
+#define BB_VSEL_VBAT		(3 << 1)
+#define BB_CHRG_EN		(1 << 0)
+
+#ifndef CONFIG_DM_I2C
+/*
+ * Functions to read and write from TPS659038/TWL6035/TWL6037
+ * or other Palmas family of TI PMICs
+ */
+static inline int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+#else
+int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val);
+int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val);
+#endif
+
+void palmas_init_settings(void);
+int palmas_mmc1_poweron_ldo(uint ldo_volt, uint ldo_ctrl, uint voltage);
+int lp873x_mmc1_poweron_ldo(uint voltage);
+int twl603x_mmc1_set_ldo9(u8 vsel);
+int twl603x_audio_power(u8 on);
+int twl603x_enable_bb_charge(u8 bb_fields);
+int palmas_enable_ss_ldo(void);
+
+#endif /* PALMAS_H */
diff --git a/include/panel.h b/include/panel.h
new file mode 100644
index 0000000..cd596d4
--- /dev/null
+++ b/include/panel.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _PANEL_H
+#define _PANEL_H
+
+struct panel_ops {
+	/**
+	 * enable_backlight() - Enable the panel backlight
+	 *
+	 * @dev:	Panel device containing the backlight to enable
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*enable_backlight)(struct udevice *dev);
+
+	/**
+	 * set_backlight - Set panel backlight brightness
+	 *
+	 * @dev:	Panel device containing the backlight to update
+	 * @percent:	Brightness value (0 to 100, or BACKLIGHT_... value)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_backlight)(struct udevice *dev, int percent);
+
+	/**
+	 * get_timings() - Get display timings from panel.
+	 *
+	 * @dev:	Panel device containing the display timings
+	 * @tim:	Place to put timings
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_display_timing)(struct udevice *dev,
+				  struct display_timing *timing);
+};
+
+#define panel_get_ops(dev)	((struct panel_ops *)(dev)->driver->ops)
+
+/**
+ * panel_enable_backlight() - Enable/disable the panel backlight
+ *
+ * @dev:	Panel device containing the backlight to enable
+ * @enable:	true to enable the backlight, false to dis
+ * @return 0 if OK, -ve on error
+ */
+int panel_enable_backlight(struct udevice *dev);
+
+/**
+ * panel_set_backlight - Set brightness for the panel backlight
+ *
+ * @dev:	Panel device containing the backlight to update
+ * @percent:	Brightness value (0 to 100, or BACKLIGHT_... value)
+ * @return 0 if OK, -ve on error
+ */
+int panel_set_backlight(struct udevice *dev, int percent);
+
+/**
+ * panel_get_display_timing() - Get display timings from panel.
+ *
+ * @dev:	Panel device containing the display timings
+ * @return 0 if OK, -ve on error
+ */
+int panel_get_display_timing(struct udevice *dev,
+			     struct display_timing *timing);
+
+#endif
diff --git a/include/part.h b/include/part.h
new file mode 100644
index 0000000..0b5cf3d
--- /dev/null
+++ b/include/part.h
@@ -0,0 +1,469 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+#ifndef _PART_H
+#define _PART_H
+
+#include <blk.h>
+#include <ide.h>
+#include <uuid.h>
+#include <linux/list.h>
+
+struct block_drvr {
+	char *name;
+	int (*select_hwpart)(int dev_num, int hwpart);
+};
+
+#define LOG2(x) (((x & 0xaaaaaaaa) ? 1 : 0) + ((x & 0xcccccccc) ? 2 : 0) + \
+		 ((x & 0xf0f0f0f0) ? 4 : 0) + ((x & 0xff00ff00) ? 8 : 0) + \
+		 ((x & 0xffff0000) ? 16 : 0))
+#define LOG2_INVALID(type) ((type)((sizeof(type)<<3)-1))
+
+/* Part types */
+#define PART_TYPE_UNKNOWN	0x00
+#define PART_TYPE_MAC		0x01
+#define PART_TYPE_DOS		0x02
+#define PART_TYPE_ISO		0x03
+#define PART_TYPE_AMIGA		0x04
+#define PART_TYPE_EFI		0x05
+
+/* maximum number of partition entries supported by search */
+#define DOS_ENTRY_NUMBERS	8
+#define ISO_ENTRY_NUMBERS	64
+#define MAC_ENTRY_NUMBERS	64
+#define AMIGA_ENTRY_NUMBERS	8
+/*
+ * Type string for U-Boot bootable partitions
+ */
+#define BOOT_PART_TYPE	"U-Boot"	/* primary boot partition type	*/
+#define BOOT_PART_COMP	"PPCBoot"	/* PPCBoot compatibility type	*/
+
+/* device types */
+#define DEV_TYPE_UNKNOWN	0xff	/* not connected */
+#define DEV_TYPE_HARDDISK	0x00	/* harddisk */
+#define DEV_TYPE_TAPE		0x01	/* Tape */
+#define DEV_TYPE_CDROM		0x05	/* CD-ROM */
+#define DEV_TYPE_OPDISK		0x07	/* optical disk */
+
+#define PART_NAME_LEN 32
+#define PART_TYPE_LEN 32
+#define MAX_SEARCH_PARTITIONS 64
+
+typedef struct disk_partition {
+	lbaint_t	start;	/* # of first block in partition	*/
+	lbaint_t	size;	/* number of blocks in partition	*/
+	ulong	blksz;		/* block size in bytes			*/
+	uchar	name[PART_NAME_LEN];	/* partition name			*/
+	uchar	type[PART_TYPE_LEN];	/* string type description		*/
+	int	bootable;	/* Active/Bootable flag is set		*/
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+	char	uuid[UUID_STR_LEN + 1];	/* filesystem UUID as string, if exists	*/
+#endif
+#ifdef CONFIG_PARTITION_TYPE_GUID
+	char	type_guid[UUID_STR_LEN + 1];	/* type GUID as string, if exists	*/
+#endif
+#ifdef CONFIG_DOS_PARTITION
+	uchar	sys_ind;	/* partition type 			*/
+#endif
+} disk_partition_t;
+
+struct disk_part {
+	int partnum;
+	disk_partition_t gpt_part_info;
+	struct list_head list;
+};
+
+/* Misc _get_dev functions */
+#ifdef CONFIG_PARTITIONS
+/**
+ * blk_get_dev() - get a pointer to a block device given its type and number
+ *
+ * Each interface allocates its own devices and typically struct blk_desc is
+ * contained with the interface's data structure. There is no global
+ * numbering for block devices, so the interface name must be provided.
+ *
+ * @ifname:	Interface name (e.g. "ide", "scsi")
+ * @dev:	Device number (0 for first device on that interface, 1 for
+ *		second, etc.
+ * @return pointer to the block device, or NULL if not available, or an
+ *	   error occurred.
+ */
+struct blk_desc *blk_get_dev(const char *ifname, int dev);
+
+struct blk_desc *mg_disk_get_dev(int dev);
+int host_get_dev_err(int dev, struct blk_desc **blk_devp);
+
+/* disk/part.c */
+int part_get_info(struct blk_desc *dev_desc, int part, disk_partition_t *info);
+/**
+ * part_get_info_whole_disk() - get partition info for the special case of
+ * a partition occupying the entire disk.
+ */
+int part_get_info_whole_disk(struct blk_desc *dev_desc, disk_partition_t *info);
+
+void part_print(struct blk_desc *dev_desc);
+void part_init(struct blk_desc *dev_desc);
+void dev_print(struct blk_desc *dev_desc);
+
+/**
+ * blk_get_device_by_str() - Get a block device given its interface/hw partition
+ *
+ * Each interface allocates its own devices and typically struct blk_desc is
+ * contained with the interface's data structure. There is no global
+ * numbering for block devices, so the interface name must be provided.
+ *
+ * The hardware parition is not related to the normal software partitioning
+ * of a device - each hardware partition is effectively a separately
+ * accessible block device. When a hardware parition is selected on MMC the
+ * other hardware partitions become inaccessible. The same block device is
+ * used to access all hardware partitions, but its capacity may change when a
+ * different hardware partition is selected.
+ *
+ * When a hardware partition number is given, the block device switches to
+ * that hardware partition.
+ *
+ * @ifname:	Interface name (e.g. "ide", "scsi")
+ * @dev_str:	Device and optional hw partition. This can either be a string
+ *		containing the device number (e.g. "2") or the device number
+ *		and hardware partition number (e.g. "2.4") for devices that
+ *		support it (currently only MMC).
+ * @dev_desc:	Returns a pointer to the block device on success
+ * @return block device number (local to the interface), or -1 on error
+ */
+int blk_get_device_by_str(const char *ifname, const char *dev_str,
+			  struct blk_desc **dev_desc);
+
+/**
+ * blk_get_device_part_str() - Get a block device and partition
+ *
+ * This calls blk_get_device_by_str() to look up a device. It also looks up
+ * a partition and returns information about it.
+ *
+ * @dev_part_str is in the format:
+ *	<dev>.<hw_part>:<part> where <dev> is the device number,
+ *	<hw_part> is the optional hardware partition number and
+ *	<part> is the partition number
+ *
+ * If ifname is "hostfs" then this function returns the sandbox host block
+ * device.
+ *
+ * If ifname is ubi, then this function returns 0, with @info set to a
+ * special UBI device.
+ *
+ * If @dev_part_str is NULL or empty or "-", then this function looks up
+ * the "bootdevice" environment variable and uses that string instead.
+ *
+ * If the partition string is empty then the first partition is used. If the
+ * partition string is "auto" then the first bootable partition is used.
+ *
+ * @ifname:	Interface name (e.g. "ide", "scsi")
+ * @dev_part_str:	Device and partition string
+ * @dev_desc:	Returns a pointer to the block device on success
+ * @info:	Returns partition information
+ * @allow_whole_dev:	true to allow the user to select partition 0
+ *		(which means the whole device), false to require a valid
+ *		partition number >= 1
+ * @return partition number, or -1 on error
+ *
+ */
+int blk_get_device_part_str(const char *ifname, const char *dev_part_str,
+			    struct blk_desc **dev_desc,
+			    disk_partition_t *info, int allow_whole_dev);
+
+/**
+ * part_get_info_by_name_type() - Search for a partition by name
+ *                                for only specified partition type
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_name - the specified table entry name
+ * @param info - returns the disk partition info
+ * @param part_type - only search in partitions of this type
+ *
+ * @return - the partition number on match (starting on 1), -1 on no match,
+ * otherwise error
+ */
+int part_get_info_by_name_type(struct blk_desc *dev_desc, const char *name,
+			       disk_partition_t *info, int part_type);
+
+/**
+ * part_get_info_by_name() - Search for a partition by name
+ *                           among all available registered partitions
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_name - the specified table entry name
+ * @param info - returns the disk partition info
+ *
+ * @return - the partition number on match (starting on 1), -1 on no match,
+ * otherwise error
+ */
+int part_get_info_by_name(struct blk_desc *dev_desc,
+			      const char *name, disk_partition_t *info);
+
+/**
+ * Get partition info from dev number + part name, or dev number + part number.
+ *
+ * Parse a device number and partition description (either name or number)
+ * in the form of device number plus partition name separated by a "#"
+ * (like "device_num#partition_name") or a device number plus a partition number
+ * separated by a ":". For example both "0#misc" and "0:1" can be valid
+ * partition descriptions for a given interface. If the partition is found, sets
+ * dev_desc and part_info accordingly with the information of the partition.
+ *
+ * @param[in] dev_iface	Device interface
+ * @param[in] dev_part_str Input partition description, like "0#misc" or "0:1"
+ * @param[out] dev_desc	Place to store the device description pointer
+ * @param[out] part_info Place to store the partition information
+ * @return 0 on success, or a negative on error
+ */
+int part_get_info_by_dev_and_name_or_num(const char *dev_iface,
+					 const char *dev_part_str,
+					 struct blk_desc **dev_desc,
+					 disk_partition_t *part_info);
+
+/**
+ * part_set_generic_name() - create generic partition like hda1 or sdb2
+ *
+ * Helper function for partition tables, which don't hold partition names
+ * (DOS, ISO). Generates partition name out of the device type and partition
+ * number.
+ *
+ * @dev_desc:	pointer to the block device
+ * @part_num:	partition number for which the name is generated
+ * @name:	buffer where the name is written
+ */
+void part_set_generic_name(const struct blk_desc *dev_desc,
+	int part_num, char *name);
+
+extern const struct block_drvr block_drvr[];
+#else
+static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
+{ return NULL; }
+static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
+
+static inline int part_get_info(struct blk_desc *dev_desc, int part,
+				disk_partition_t *info) { return -1; }
+static inline int part_get_info_whole_disk(struct blk_desc *dev_desc,
+					   disk_partition_t *info)
+{ return -1; }
+static inline void part_print(struct blk_desc *dev_desc) {}
+static inline void part_init(struct blk_desc *dev_desc) {}
+static inline void dev_print(struct blk_desc *dev_desc) {}
+static inline int blk_get_device_by_str(const char *ifname, const char *dev_str,
+					struct blk_desc **dev_desc)
+{ return -1; }
+static inline int blk_get_device_part_str(const char *ifname,
+					   const char *dev_part_str,
+					   struct blk_desc **dev_desc,
+					   disk_partition_t *info,
+					   int allow_whole_dev)
+{ *dev_desc = NULL; return -1; }
+#endif
+
+/*
+ * We don't support printing partition information in SPL and only support
+ * getting partition information in a few cases.
+ */
+#ifdef CONFIG_SPL_BUILD
+# define part_print_ptr(x)	NULL
+# if defined(CONFIG_SPL_FS_EXT4) || defined(CONFIG_SPL_FS_FAT) || \
+	defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
+#  define part_get_info_ptr(x)	x
+# else
+#  define part_get_info_ptr(x)	NULL
+# endif
+#else
+#define part_print_ptr(x)	x
+#define part_get_info_ptr(x)	x
+#endif
+
+
+struct part_driver {
+	const char *name;
+	int part_type;
+	const int max_entries;	/* maximum number of entries to search */
+
+	/**
+	 * get_info() - Get information about a partition
+	 *
+	 * @dev_desc:	Block device descriptor
+	 * @part:	Partition number (1 = first)
+	 * @info:	Returns partition information
+	 */
+	int (*get_info)(struct blk_desc *dev_desc, int part,
+			disk_partition_t *info);
+
+	/**
+	 * print() - Print partition information
+	 *
+	 * @dev_desc:	Block device descriptor
+	 */
+	void (*print)(struct blk_desc *dev_desc);
+
+	/**
+	 * test() - Test if a device contains this partition type
+	 *
+	 * @dev_desc:	Block device descriptor
+	 * @return 0 if the block device appears to contain this partition
+	 *	   type, -ve if not
+	 */
+	int (*test)(struct blk_desc *dev_desc);
+};
+
+/* Declare a new U-Boot partition 'driver' */
+#define U_BOOT_PART_TYPE(__name)					\
+	ll_entry_declare(struct part_driver, __name, part_driver)
+
+#include <part_efi.h>
+
+#if CONFIG_IS_ENABLED(EFI_PARTITION)
+/* disk/part_efi.c */
+/**
+ * write_gpt_table() - Write the GUID Partition Table to disk
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_h - pointer to GPT header representation
+ * @param gpt_e - pointer to GPT partition table entries
+ *
+ * @return - zero on success, otherwise error
+ */
+int write_gpt_table(struct blk_desc *dev_desc,
+		  gpt_header *gpt_h, gpt_entry *gpt_e);
+
+/**
+ * gpt_fill_pte(): Fill the GPT partition table entry
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_h - GPT header representation
+ * @param gpt_e - GPT partition table entries
+ * @param partitions - list of partitions
+ * @param parts - number of partitions
+ *
+ * @return zero on success
+ */
+int gpt_fill_pte(struct blk_desc *dev_desc,
+		 gpt_header *gpt_h, gpt_entry *gpt_e,
+		 disk_partition_t *partitions, int parts);
+
+/**
+ * gpt_fill_header(): Fill the GPT header
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_h - GPT header representation
+ * @param str_guid - disk guid string representation
+ * @param parts_count - number of partitions
+ *
+ * @return - error on str_guid conversion error
+ */
+int gpt_fill_header(struct blk_desc *dev_desc, gpt_header *gpt_h,
+		char *str_guid, int parts_count);
+
+/**
+ * gpt_restore(): Restore GPT partition table
+ *
+ * @param dev_desc - block device descriptor
+ * @param str_disk_guid - disk GUID
+ * @param partitions - list of partitions
+ * @param parts - number of partitions
+ *
+ * @return zero on success
+ */
+int gpt_restore(struct blk_desc *dev_desc, char *str_disk_guid,
+		disk_partition_t *partitions, const int parts_count);
+
+/**
+ * is_valid_gpt_buf() - Ensure that the Primary GPT information is valid
+ *
+ * @param dev_desc - block device descriptor
+ * @param buf - buffer which contains the MBR and Primary GPT info
+ *
+ * @return - '0' on success, otherwise error
+ */
+int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf);
+
+/**
+ * write_mbr_and_gpt_partitions() - write MBR, Primary GPT and Backup GPT
+ *
+ * @param dev_desc - block device descriptor
+ * @param buf - buffer which contains the MBR and Primary GPT info
+ *
+ * @return - '0' on success, otherwise error
+ */
+int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf);
+
+/**
+ * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header
+ *                        and partition table entries (PTE)
+ *
+ * As a side effect if sets gpt_head and gpt_pte so they point to GPT data.
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_head - pointer to GPT header data read from medium
+ * @param gpt_pte - pointer to GPT partition table enties read from medium
+ *
+ * @return - '0' on success, otherwise error
+ */
+int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head,
+		       gpt_entry **gpt_pte);
+
+/**
+ * gpt_verify_partitions() - Function to check if partitions' name, start and
+ *                           size correspond to '$partitions' env variable
+ *
+ * This function checks if on medium stored GPT data is in sync with information
+ * provided in '$partitions' environment variable. Specificially, name, start
+ * and size of the partition is checked.
+ *
+ * @param dev_desc - block device descriptor
+ * @param partitions - partition data read from '$partitions' env variable
+ * @param parts - number of partitions read from '$partitions' env variable
+ * @param gpt_head - pointer to GPT header data read from medium
+ * @param gpt_pte - pointer to GPT partition table enties read from medium
+ *
+ * @return - '0' on success, otherwise error
+ */
+int gpt_verify_partitions(struct blk_desc *dev_desc,
+			  disk_partition_t *partitions, int parts,
+			  gpt_header *gpt_head, gpt_entry **gpt_pte);
+
+
+/**
+ * get_disk_guid() - Function to read the GUID string from a device's GPT
+ *
+ * This function reads the GUID string from a block device whose descriptor
+ * is provided.
+ *
+ * @param dev_desc - block device descriptor
+ * @param guid - pre-allocated string in which to return the GUID
+ *
+ * @return - '0' on success, otherwise error
+ */
+int get_disk_guid(struct blk_desc *dev_desc, char *guid);
+
+#endif
+
+#if CONFIG_IS_ENABLED(DOS_PARTITION)
+/**
+ * is_valid_dos_buf() - Ensure that a DOS MBR image is valid
+ *
+ * @param buf - buffer which contains the MBR
+ *
+ * @return - '0' on success, otherwise error
+ */
+int is_valid_dos_buf(void *buf);
+
+/**
+ * write_mbr_partition() - write DOS MBR
+ *
+ * @param dev_desc - block device descriptor
+ * @param buf - buffer which contains the MBR
+ *
+ * @return - '0' on success, otherwise error
+ */
+int write_mbr_partition(struct blk_desc *dev_desc, void *buf);
+
+#endif
+
+
+#endif /* _PART_H */
diff --git a/include/part_efi.h b/include/part_efi.h
new file mode 100644
index 0000000..eb5797a
--- /dev/null
+++ b/include/part_efi.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2008 RuggedCom, Inc.
+ * Richard Retanubun <RichardRetanubun@RuggedCom.com>
+ */
+
+/*
+ * See also linux/fs/partitions/efi.h
+ *
+ * EFI GUID Partition Table
+ * Per Intel EFI Specification v1.02
+ * http://developer.intel.com/technology/efi/efi.htm
+*/
+
+#include <linux/compiler.h>
+
+#ifndef _DISK_PART_EFI_H
+#define _DISK_PART_EFI_H
+
+#include <efi.h>
+
+#define MSDOS_MBR_SIGNATURE 0xAA55
+#define MSDOS_MBR_BOOT_CODE_SIZE 440
+#define EFI_PMBR_OSTYPE_EFI 0xEF
+#define EFI_PMBR_OSTYPE_EFI_GPT 0xEE
+
+#define GPT_HEADER_SIGNATURE_UBOOT 0x5452415020494645ULL
+#define GPT_HEADER_CHROMEOS_IGNORE 0x454d45524f4e4749ULL // 'IGNOREME'
+
+#define GPT_HEADER_REVISION_V1 0x00010000
+#define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL
+#define GPT_ENTRY_NUMBERS		CONFIG_EFI_PARTITION_ENTRIES_NUMBERS
+#define GPT_ENTRY_SIZE			128
+
+#define PARTITION_SYSTEM_GUID \
+	EFI_GUID( 0xC12A7328, 0xF81F, 0x11d2, \
+		0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B)
+#define LEGACY_MBR_PARTITION_GUID \
+	EFI_GUID( 0x024DEE41, 0x33E7, 0x11d3, \
+		0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F)
+#define PARTITION_MSFT_RESERVED_GUID \
+	EFI_GUID( 0xE3C9E316, 0x0B5C, 0x4DB8, \
+		0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE)
+#define PARTITION_BASIC_DATA_GUID \
+	EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \
+		0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7)
+#define PARTITION_LINUX_FILE_SYSTEM_DATA_GUID \
+	EFI_GUID(0x0FC63DAF, 0x8483, 0x4772, \
+		0x8E, 0x79, 0x3D, 0x69, 0xD8, 0x47, 0x7D, 0xE4)
+#define PARTITION_LINUX_RAID_GUID \
+	EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \
+		0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e)
+#define PARTITION_LINUX_SWAP_GUID \
+	EFI_GUID( 0x0657fd6d, 0xa4ab, 0x43c4, \
+		0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f)
+#define PARTITION_LINUX_LVM_GUID \
+	EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
+		0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
+
+/* linux/include/efi.h */
+typedef u16 efi_char16_t;
+
+/* based on linux/include/genhd.h */
+struct partition {
+	u8 boot_ind;		/* 0x80 - active */
+	u8 head;		/* starting head */
+	u8 sector;		/* starting sector */
+	u8 cyl;			/* starting cylinder */
+	u8 sys_ind;		/* What partition type */
+	u8 end_head;		/* end head */
+	u8 end_sector;		/* end sector */
+	u8 end_cyl;		/* end cylinder */
+	__le32 start_sect;	/* starting sector counting from 0 */
+	__le32 nr_sects;	/* nr of sectors in partition */
+} __packed;
+
+/* based on linux/fs/partitions/efi.h */
+typedef struct _gpt_header {
+	__le64 signature;
+	__le32 revision;
+	__le32 header_size;
+	__le32 header_crc32;
+	__le32 reserved1;
+	__le64 my_lba;
+	__le64 alternate_lba;
+	__le64 first_usable_lba;
+	__le64 last_usable_lba;
+	efi_guid_t disk_guid;
+	__le64 partition_entry_lba;
+	__le32 num_partition_entries;
+	__le32 sizeof_partition_entry;
+	__le32 partition_entry_array_crc32;
+} __packed gpt_header;
+
+typedef union _gpt_entry_attributes {
+	struct {
+		u64 required_to_function:1;
+		u64 no_block_io_protocol:1;
+		u64 legacy_bios_bootable:1;
+		u64 reserved:45;
+		u64 type_guid_specific:16;
+	} fields;
+	unsigned long long raw;
+} __packed gpt_entry_attributes;
+
+#define PARTNAME_SZ	(72 / sizeof(efi_char16_t))
+typedef struct _gpt_entry {
+	efi_guid_t partition_type_guid;
+	efi_guid_t unique_partition_guid;
+	__le64 starting_lba;
+	__le64 ending_lba;
+	gpt_entry_attributes attributes;
+	efi_char16_t partition_name[PARTNAME_SZ];
+} __packed gpt_entry;
+
+typedef struct _legacy_mbr {
+	u8 boot_code[MSDOS_MBR_BOOT_CODE_SIZE];
+	__le32 unique_mbr_signature;
+	__le16 unknown;
+	struct partition partition_record[4];
+	__le16 signature;
+} __packed legacy_mbr;
+
+#endif	/* _DISK_PART_EFI_H */
diff --git a/include/pca953x.h b/include/pca953x.h
new file mode 100644
index 0000000..aa4401a
--- /dev/null
+++ b/include/pca953x.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ */
+
+#ifndef __PCA953X_H_
+#define __PCA953X_H_
+
+#define PCA953X_IN		0x00
+#define PCA953X_OUT		0x01
+#define PCA953X_POL		0x02
+#define PCA953X_CONF		0x03
+
+#define PCA953X_OUT_LOW		0
+#define PCA953X_OUT_HIGH	1
+#define PCA953X_POL_NORMAL	0
+#define PCA953X_POL_INVERT	1
+#define PCA953X_DIR_OUT		0
+#define PCA953X_DIR_IN		1
+
+int pca953x_set_val(u8 chip, uint mask, uint data);
+int pca953x_set_pol(u8 chip, uint mask, uint data);
+int pca953x_set_dir(u8 chip, uint mask, uint data);
+int pca953x_get_val(u8 chip);
+
+#endif /* __PCA953X_H_ */
diff --git a/include/pca9564.h b/include/pca9564.h
new file mode 100644
index 0000000..99e8bcd
--- /dev/null
+++ b/include/pca9564.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * File:         include/pca9564.h
+ * Author:
+ *
+ * Created:      2009-06-23
+ * Description:  PCA9564 i2c bridge driver
+ *
+ * Modified:
+ *               Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
+ *
+ * Bugs:
+ */
+
+#ifndef _PCA9564_H
+#define _PCA9564_H
+
+/* Clock speeds for the bus */
+#define PCA_CON_330kHz      0x00
+#define PCA_CON_288kHz      0x01
+#define PCA_CON_217kHz      0x02
+#define PCA_CON_146kHz      0x03
+#define PCA_CON_88kHz       0x04
+#define PCA_CON_59kHz       0x05
+#define PCA_CON_44kHz       0x06
+#define PCA_CON_36kHz       0x07
+
+#define PCA_CON_AA          0x80 /* Assert Acknowledge */
+#define PCA_CON_ENSIO       0x40 /* Enable */
+#define PCA_CON_STA         0x20 /* Start */
+#define PCA_CON_STO         0x10 /* Stop */
+#define PCA_CON_SI          0x08 /* Serial Interrupt */
+#define PCA_CON_CR          0x07 /* Clock Rate (MASK) */
+
+#endif
diff --git a/include/pca9698.h b/include/pca9698.h
new file mode 100644
index 0000000..48a5f75
--- /dev/null
+++ b/include/pca9698.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ */
+
+#ifndef __PCA9698_H_
+#define __PCA9698_H_
+
+int pca9698_request(unsigned gpio, const char *label);
+void pca9698_free(unsigned gpio);
+int pca9698_direction_input(u8 addr, unsigned gpio);
+int pca9698_direction_output(u8 addr, unsigned gpio, int value);
+int pca9698_get_value(u8 addr, unsigned gpio);
+int pca9698_set_value(u8 addr, unsigned gpio, int value);
+
+#endif /* __PCA9698_H_ */
diff --git a/include/pch.h b/include/pch.h
new file mode 100644
index 0000000..0b44b66
--- /dev/null
+++ b/include/pch.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __pch_h
+#define __pch_h
+
+#define PCH_RCBA		0xf0
+
+#define BIOS_CTRL_BIOSWE	BIT(0)
+
+/* All the supported PCH ioctls */
+enum pch_req_t {
+	/* Returns HDA config info if Azalia V1CTL enabled, -ENOENT if not */
+	PCH_REQ_HDA_CONFIG,
+
+	/* Fills out a struct pch_pmbase_info if available */
+	PCH_REQ_PMBASE_INFO,
+
+	PCH_REQ_TEST1,		/* Test requests for sandbox driver */
+	PCH_REQ_TEST2,
+	PCH_REQ_TEST3,
+
+	PCH_REQ_COUNT,		/* Number of ioctrls supported */
+};
+
+/**
+ * struct pch_pmbase_info - Information filled in by PCH_REQ_PMBASE_INFO
+ *
+ * @pmbase: IO address of power-management controller
+ * @gpio0_en_ofs: Offset of GPIO0 enable register
+ * @pm1_sts_ofs: Offset of status register
+ * @pm1_cnt_ofs: Offset of control register
+ */
+struct pch_pmbase_info {
+	u16 base;
+	u8 gpio0_en_ofs;
+	u8 pm1_sts_ofs;
+	u8 pm1_cnt_ofs;
+};
+
+/**
+ * struct pch_ops - Operations for the Platform Controller Hub
+ *
+ * Consider using ioctl() to add rarely used or driver-specific operations.
+ */
+struct pch_ops {
+	/**
+	 * get_spi_base() - get the address of SPI base
+	 *
+	 * @dev:	PCH device to check
+	 * @sbasep:	Returns address of SPI base if available, else 0
+	 * @return 0 if OK, -ve on error (e.g. there is no SPI base)
+	 */
+	int (*get_spi_base)(struct udevice *dev, ulong *sbasep);
+
+	/**
+	 * set_spi_protect() - set whether SPI flash is protected or not
+	 *
+	 * @dev:	PCH device to adjust
+	 * @protect:	true to protect, false to unprotect
+	 *
+	 * @return 0 on success, -ENOSYS if not implemented
+	 */
+	int (*set_spi_protect)(struct udevice *dev, bool protect);
+
+	/**
+	 * get_gpio_base() - get the address of GPIO base
+	 *
+	 * @dev:	PCH device to check
+	 * @gbasep:	Returns address of GPIO base if available, else 0
+	 * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
+	 */
+	int (*get_gpio_base)(struct udevice *dev, u32 *gbasep);
+
+	/**
+	 * get_io_base() - get the address of IO base
+	 *
+	 * @dev:	PCH device to check
+	 * @iobasep:	Returns address of IO base if available, else 0
+	 * @return 0 if OK, -ve on error (e.g. there is no IO base)
+	 */
+	int (*get_io_base)(struct udevice *dev, u32 *iobasep);
+
+	/**
+	 * ioctl() - perform misc read/write operations
+	 *
+	 * This is a catch-all operation intended to avoid adding lots of
+	 * methods to this uclass, of which few are commonly used. Uncommon
+	 * operations that pertain only to a few devices in this uclass should
+	 * use this method instead of adding new methods.
+	 *
+	 * @dev:	PCH device to check
+	 * @req:	PCH request ID
+	 * @data:	Input/output data
+	 * @size:	Size of input data (and maximum size of output data)
+	 * @return size of output data on sucesss, -ve on error
+	 */
+	int (*ioctl)(struct udevice *dev, enum pch_req_t req, void *data,
+		     int size);
+};
+
+#define pch_get_ops(dev)        ((struct pch_ops *)(dev)->driver->ops)
+
+/**
+ * pch_get_spi_base() - get the address of SPI base
+ *
+ * @dev:	PCH device to check
+ * @sbasep:	Returns address of SPI base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no SPI base)
+ */
+int pch_get_spi_base(struct udevice *dev, ulong *sbasep);
+
+/**
+ * set_spi_protect() - set whether SPI flash is protected or not
+ *
+ * @dev:	PCH device to adjust
+ * @protect:	true to protect, false to unprotect
+ *
+ * @return 0 on success, -ENOSYS if not implemented
+ */
+int pch_set_spi_protect(struct udevice *dev, bool protect);
+
+/**
+ * pch_get_gpio_base() - get the address of GPIO base
+ *
+ * @dev:	PCH device to check
+ * @gbasep:	Returns address of GPIO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no GPIO base)
+ */
+int pch_get_gpio_base(struct udevice *dev, u32 *gbasep);
+
+/**
+ * pch_get_io_base() - get the address of IO base
+ *
+ * @dev:	PCH device to check
+ * @iobasep:	Returns address of IO base if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no IO base)
+ */
+int pch_get_io_base(struct udevice *dev, u32 *iobasep);
+
+/**
+ * pch_ioctl() - perform misc read/write operations
+ *
+ * This is a catch-all operation intended to avoid adding lots of
+ * methods to this uclass, of which few are commonly used. Uncommon
+ * operations that pertain only to a few devices in this uclass should
+ * use this method instead of adding new methods.
+ *
+ * @dev:	PCH device to check
+ * @req:	PCH request ID
+ * @data:	Input/output data
+ * @size:	Size of input data (and maximum size of output data)
+ * @return size of output data on sucesss, -ve on error
+ */
+int pch_ioctl(struct udevice *dev, ulong req, void *data, int size);
+
+#endif
diff --git a/include/pci.h b/include/pci.h
new file mode 100644
index 0000000..ff59ac0
--- /dev/null
+++ b/include/pci.h
@@ -0,0 +1,1700 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef _PCI_H
+#define _PCI_H
+
+#define PCI_CFG_SPACE_SIZE	256
+#define PCI_CFG_SPACE_EXP_SIZE	4096
+
+/*
+ * Under PCI, each device has 256 bytes of configuration address space,
+ * of which the first 64 bytes are standardized as follows:
+ */
+#define PCI_STD_HEADER_SIZEOF	64
+#define PCI_VENDOR_ID		0x00	/* 16 bits */
+#define PCI_DEVICE_ID		0x02	/* 16 bits */
+#define PCI_COMMAND		0x04	/* 16 bits */
+#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
+#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
+#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
+#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
+#define  PCI_COMMAND_INVALIDATE 0x10	/* Use memory write and invalidate */
+#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
+#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
+#define  PCI_COMMAND_WAIT	0x80	/* Enable address/data stepping */
+#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
+#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
+
+#define PCI_STATUS		0x06	/* 16 bits */
+#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
+#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
+#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
+#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
+#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
+#define  PCI_STATUS_DEVSEL_MASK 0x600	/* DEVSEL timing */
+#define  PCI_STATUS_DEVSEL_FAST 0x000
+#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
+#define  PCI_STATUS_DEVSEL_SLOW 0x400
+#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
+#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
+#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
+#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
+#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
+
+#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
+					   revision */
+#define PCI_REVISION_ID		0x08	/* Revision ID */
+#define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
+#define PCI_CLASS_DEVICE	0x0a	/* Device class */
+#define PCI_CLASS_CODE		0x0b	/* Device class code */
+#define  PCI_CLASS_CODE_TOO_OLD	0x00
+#define  PCI_CLASS_CODE_STORAGE 0x01
+#define  PCI_CLASS_CODE_NETWORK 0x02
+#define  PCI_CLASS_CODE_DISPLAY	0x03
+#define  PCI_CLASS_CODE_MULTIMEDIA 0x04
+#define  PCI_CLASS_CODE_MEMORY	0x05
+#define  PCI_CLASS_CODE_BRIDGE	0x06
+#define  PCI_CLASS_CODE_COMM	0x07
+#define  PCI_CLASS_CODE_PERIPHERAL 0x08
+#define  PCI_CLASS_CODE_INPUT	0x09
+#define  PCI_CLASS_CODE_DOCKING	0x0A
+#define  PCI_CLASS_CODE_PROCESSOR 0x0B
+#define  PCI_CLASS_CODE_SERIAL	0x0C
+#define  PCI_CLASS_CODE_WIRELESS 0x0D
+#define  PCI_CLASS_CODE_I2O	0x0E
+#define  PCI_CLASS_CODE_SATELLITE 0x0F
+#define  PCI_CLASS_CODE_CRYPTO	0x10
+#define  PCI_CLASS_CODE_DATA	0x11
+/* Base Class 0x12 - 0xFE is reserved */
+#define  PCI_CLASS_CODE_OTHER	0xFF
+
+#define PCI_CLASS_SUB_CODE	0x0a	/* Device sub-class code */
+#define  PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA	0x00
+#define  PCI_CLASS_SUB_CODE_TOO_OLD_VGA		0x01
+#define  PCI_CLASS_SUB_CODE_STORAGE_SCSI	0x00
+#define  PCI_CLASS_SUB_CODE_STORAGE_IDE		0x01
+#define  PCI_CLASS_SUB_CODE_STORAGE_FLOPPY	0x02
+#define  PCI_CLASS_SUB_CODE_STORAGE_IPIBUS	0x03
+#define  PCI_CLASS_SUB_CODE_STORAGE_RAID	0x04
+#define  PCI_CLASS_SUB_CODE_STORAGE_ATA		0x05
+#define  PCI_CLASS_SUB_CODE_STORAGE_SATA	0x06
+#define  PCI_CLASS_SUB_CODE_STORAGE_SAS		0x07
+#define  PCI_CLASS_SUB_CODE_STORAGE_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_NETWORK_ETHERNET	0x00
+#define  PCI_CLASS_SUB_CODE_NETWORK_TOKENRING	0x01
+#define  PCI_CLASS_SUB_CODE_NETWORK_FDDI	0x02
+#define  PCI_CLASS_SUB_CODE_NETWORK_ATM		0x03
+#define  PCI_CLASS_SUB_CODE_NETWORK_ISDN	0x04
+#define  PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP	0x05
+#define  PCI_CLASS_SUB_CODE_NETWORK_PICMG	0x06
+#define  PCI_CLASS_SUB_CODE_NETWORK_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_DISPLAY_VGA		0x00
+#define  PCI_CLASS_SUB_CODE_DISPLAY_XGA		0x01
+#define  PCI_CLASS_SUB_CODE_DISPLAY_3D		0x02
+#define  PCI_CLASS_SUB_CODE_DISPLAY_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO	0x00
+#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO	0x01
+#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE	0x02
+#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_MEMORY_RAM		0x00
+#define  PCI_CLASS_SUB_CODE_MEMORY_FLASH	0x01
+#define  PCI_CLASS_SUB_CODE_MEMORY_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_BRIDGE_HOST		0x00
+#define  PCI_CLASS_SUB_CODE_BRIDGE_ISA		0x01
+#define  PCI_CLASS_SUB_CODE_BRIDGE_EISA		0x02
+#define  PCI_CLASS_SUB_CODE_BRIDGE_MCA		0x03
+#define  PCI_CLASS_SUB_CODE_BRIDGE_PCI		0x04
+#define  PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA	0x05
+#define  PCI_CLASS_SUB_CODE_BRIDGE_NUBUS	0x06
+#define  PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS	0x07
+#define  PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY	0x08
+#define  PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI	0x09
+#define  PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND	0x0A
+#define  PCI_CLASS_SUB_CODE_BRIDGE_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_COMM_SERIAL		0x00
+#define  PCI_CLASS_SUB_CODE_COMM_PARALLEL	0x01
+#define  PCI_CLASS_SUB_CODE_COMM_MULTIPORT	0x02
+#define  PCI_CLASS_SUB_CODE_COMM_MODEM		0x03
+#define  PCI_CLASS_SUB_CODE_COMM_GPIB		0x04
+#define  PCI_CLASS_SUB_CODE_COMM_SMARTCARD	0x05
+#define  PCI_CLASS_SUB_CODE_COMM_OTHER		0x80
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_PIC	0x00
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_DMA	0x01
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER	0x02
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_RTC	0x03
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG	0x04
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_SD	0x05
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_INPUT_KEYBOARD	0x00
+#define  PCI_CLASS_SUB_CODE_INPUT_DIGITIZER	0x01
+#define  PCI_CLASS_SUB_CODE_INPUT_MOUSE		0x02
+#define  PCI_CLASS_SUB_CODE_INPUT_SCANNER	0x03
+#define  PCI_CLASS_SUB_CODE_INPUT_GAMEPORT	0x04
+#define  PCI_CLASS_SUB_CODE_INPUT_OTHER		0x80
+#define  PCI_CLASS_SUB_CODE_DOCKING_GENERIC	0x00
+#define  PCI_CLASS_SUB_CODE_DOCKING_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_386	0x00
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_486	0x01
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM	0x02
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA	0x10
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC	0x20
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_MIPS	0x30
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_COPROC	0x40
+#define  PCI_CLASS_SUB_CODE_SERIAL_1394		0x00
+#define  PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS	0x01
+#define  PCI_CLASS_SUB_CODE_SERIAL_SSA		0x02
+#define  PCI_CLASS_SUB_CODE_SERIAL_USB		0x03
+#define  PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN	0x04
+#define  PCI_CLASS_SUB_CODE_SERIAL_SMBUS	0x05
+#define  PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND	0x06
+#define  PCI_CLASS_SUB_CODE_SERIAL_IPMI		0x07
+#define  PCI_CLASS_SUB_CODE_SERIAL_SERCOS	0x08
+#define  PCI_CLASS_SUB_CODE_SERIAL_CANBUS	0x09
+#define  PCI_CLASS_SUB_CODE_WIRELESS_IRDA	0x00
+#define  PCI_CLASS_SUB_CODE_WIRELESS_IR		0x01
+#define  PCI_CLASS_SUB_CODE_WIRELESS_RF		0x10
+#define  PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH	0x11
+#define  PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND	0x12
+#define  PCI_CLASS_SUB_CODE_WIRELESS_80211A	0x20
+#define  PCI_CLASS_SUB_CODE_WIRELESS_80211B	0x21
+#define  PCI_CLASS_SUB_CODE_WIRELESS_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_I2O_V1_0		0x00
+#define  PCI_CLASS_SUB_CODE_SATELLITE_TV	0x01
+#define  PCI_CLASS_SUB_CODE_SATELLITE_AUDIO	0x02
+#define  PCI_CLASS_SUB_CODE_SATELLITE_VOICE	0x03
+#define  PCI_CLASS_SUB_CODE_SATELLITE_DATA	0x04
+#define  PCI_CLASS_SUB_CODE_CRYPTO_NETWORK	0x00
+#define  PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
+#define  PCI_CLASS_SUB_CODE_CRYPTO_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_DATA_DPIO		0x00
+#define  PCI_CLASS_SUB_CODE_DATA_PERFCNTR	0x01
+#define  PCI_CLASS_SUB_CODE_DATA_COMMSYNC	0x10
+#define  PCI_CLASS_SUB_CODE_DATA_MGMT		0x20
+#define  PCI_CLASS_SUB_CODE_DATA_OTHER		0x80
+
+#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
+#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
+#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
+#define  PCI_HEADER_TYPE_NORMAL 0
+#define  PCI_HEADER_TYPE_BRIDGE 1
+#define  PCI_HEADER_TYPE_CARDBUS 2
+
+#define PCI_BIST		0x0f	/* 8 bits */
+#define PCI_BIST_CODE_MASK	0x0f	/* Return result */
+#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
+#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
+
+/*
+ * Base addresses specify locations in memory or I/O space.
+ * Decoded size can be determined by writing a value of
+ * 0xffffffff to the register, and reading it back.  Only
+ * 1 bits are decoded.
+ */
+#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
+#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
+#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
+#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
+#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
+#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
+#define  PCI_BASE_ADDRESS_SPACE 0x01	/* 0 = memory, 1 = I/O */
+#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
+#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
+#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
+#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
+#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
+#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
+#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
+#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fULL)
+#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03ULL)
+/* bit 1 is reserved if address_space = 1 */
+
+/* Convert a regsister address (e.g. PCI_BASE_ADDRESS_1) to a bar # (e.g. 1) */
+#define pci_offset_to_barnum(offset)	\
+		(((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
+
+/* Header type 0 (normal devices) */
+#define PCI_CARDBUS_CIS		0x28
+#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
+#define PCI_SUBSYSTEM_ID	0x2e
+#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
+#define  PCI_ROM_ADDRESS_ENABLE 0x01
+#define PCI_ROM_ADDRESS_MASK	(~0x7ffULL)
+
+#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
+
+/* 0x35-0x3b are reserved */
+#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
+#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
+#define PCI_MIN_GNT		0x3e	/* 8 bits */
+#define PCI_MAX_LAT		0x3f	/* 8 bits */
+
+#define PCI_INTERRUPT_LINE_DISABLE	0xff
+
+/* Header type 1 (PCI-to-PCI bridges) */
+#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
+#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
+#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
+#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
+#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
+#define PCI_IO_LIMIT		0x1d
+#define  PCI_IO_RANGE_TYPE_MASK 0x0f	/* I/O bridging type */
+#define  PCI_IO_RANGE_TYPE_16	0x00
+#define  PCI_IO_RANGE_TYPE_32	0x01
+#define  PCI_IO_RANGE_MASK	~0x0f
+#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
+#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
+#define PCI_MEMORY_LIMIT	0x22
+#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
+#define  PCI_MEMORY_RANGE_MASK	~0x0f
+#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
+#define PCI_PREF_MEMORY_LIMIT	0x26
+#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
+#define  PCI_PREF_RANGE_TYPE_32 0x00
+#define  PCI_PREF_RANGE_TYPE_64 0x01
+#define  PCI_PREF_RANGE_MASK	~0x0f
+#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
+#define PCI_PREF_LIMIT_UPPER32	0x2c
+#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
+#define PCI_IO_LIMIT_UPPER16	0x32
+/* 0x34 same as for htype 0 */
+/* 0x35-0x3b is reserved */
+#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_BRIDGE_CONTROL	0x3e
+#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
+#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
+#define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
+#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
+#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
+#define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
+#define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
+
+/* Header type 2 (CardBus bridges) */
+#define PCI_CB_CAPABILITY_LIST	0x14
+/* 0x15 reserved */
+#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
+#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
+#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
+#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
+#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
+#define PCI_CB_MEMORY_BASE_0	0x1c
+#define PCI_CB_MEMORY_LIMIT_0	0x20
+#define PCI_CB_MEMORY_BASE_1	0x24
+#define PCI_CB_MEMORY_LIMIT_1	0x28
+#define PCI_CB_IO_BASE_0	0x2c
+#define PCI_CB_IO_BASE_0_HI	0x2e
+#define PCI_CB_IO_LIMIT_0	0x30
+#define PCI_CB_IO_LIMIT_0_HI	0x32
+#define PCI_CB_IO_BASE_1	0x34
+#define PCI_CB_IO_BASE_1_HI	0x36
+#define PCI_CB_IO_LIMIT_1	0x38
+#define PCI_CB_IO_LIMIT_1_HI	0x3a
+#define  PCI_CB_IO_RANGE_MASK	~0x03
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_CB_BRIDGE_CONTROL	0x3e
+#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
+#define  PCI_CB_BRIDGE_CTL_SERR		0x02
+#define  PCI_CB_BRIDGE_CTL_ISA		0x04
+#define  PCI_CB_BRIDGE_CTL_VGA		0x08
+#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
+#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
+#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
+#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
+#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
+#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
+#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
+#define PCI_CB_SUBSYSTEM_ID	0x42
+#define PCI_CB_LEGACY_MODE_BASE 0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
+/* 0x48-0x7f reserved */
+
+/* Capability lists */
+
+#define PCI_CAP_LIST_ID		0	/* Capability ID */
+#define  PCI_CAP_ID_PM		0x01	/* Power Management */
+#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
+#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
+#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
+#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
+#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
+#define  PCI_CAP_ID_PCIX	0x07	/* PCI-X */
+#define  PCI_CAP_ID_HT		0x08	/* HyperTransport */
+#define  PCI_CAP_ID_VNDR	0x09	/* Vendor-Specific */
+#define  PCI_CAP_ID_DBG		0x0A	/* Debug port */
+#define  PCI_CAP_ID_CCRC	0x0B	/* CompactPCI Central Resource Control */
+#define  PCI_CAP_ID_SHPC	0x0C	/* PCI Standard Hot-Plug Controller */
+#define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */
+#define  PCI_CAP_ID_AGP3	0x0E	/* AGP Target PCI-PCI bridge */
+#define  PCI_CAP_ID_SECDEV	0x0F	/* Secure Device */
+#define  PCI_CAP_ID_EXP		0x10	/* PCI Express */
+#define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
+#define  PCI_CAP_ID_SATA	0x12	/* SATA Data/Index Conf. */
+#define  PCI_CAP_ID_AF		0x13	/* PCI Advanced Features */
+#define  PCI_CAP_ID_EA		0x14	/* PCI Enhanced Allocation */
+#define  PCI_CAP_ID_MAX		PCI_CAP_ID_EA
+#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
+#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
+#define PCI_CAP_SIZEOF		4
+
+/* Power Management Registers */
+
+#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
+#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
+#define  PCI_PM_CAP_AUX_POWER	0x0010	/* Auxilliary power support */
+#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
+#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
+#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
+#define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
+#define PCI_PM_CTRL		4	/* PM control and status register */
+#define  PCI_PM_CTRL_STATE_MASK 0x0003	/* Current power state (D0 to D3) */
+#define  PCI_PM_CTRL_PME_ENABLE 0x0100	/* PME pin enable */
+#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
+#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
+#define  PCI_PM_CTRL_PME_STATUS 0x8000	/* PME pin status */
+#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
+#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
+#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
+#define PCI_PM_DATA_REGISTER	7	/* (??) */
+#define PCI_PM_SIZEOF		8
+
+/* AGP registers */
+
+#define PCI_AGP_VERSION		2	/* BCD version number */
+#define PCI_AGP_RFU		3	/* Rest of capability flags */
+#define PCI_AGP_STATUS		4	/* Status register */
+#define  PCI_AGP_STATUS_RQ_MASK 0xff000000	/* Maximum number of requests - 1 */
+#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
+#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
+#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
+#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
+#define PCI_AGP_COMMAND		8	/* Control register */
+#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
+#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
+#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
+#define  PCI_AGP_COMMAND_64BIT	0x0020	/* Allow processing of 64-bit addresses */
+#define  PCI_AGP_COMMAND_FW	0x0010	/* Force FW transfers */
+#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 4x rate */
+#define PCI_AGP_SIZEOF		12
+
+/* PCI-X registers */
+
+#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
+#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
+#define  PCI_X_CMD_MAX_READ     0x0000  /* Max Memory Read Byte Count */
+#define  PCI_X_CMD_MAX_SPLIT    0x0030  /* Max Outstanding Split Transactions */
+#define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
+
+
+/* Slot Identification */
+
+#define PCI_SID_ESR		2	/* Expansion Slot Register */
+#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
+#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
+#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
+
+/* Message Signalled Interrupts registers */
+
+#define PCI_MSI_FLAGS		2	/* Various flags */
+#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
+#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
+#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
+#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
+#define  PCI_MSI_FLAGS_MASKBIT	0x0100	/* Per-vector masking capable */
+#define PCI_MSI_RFU		3	/* Rest of capability flags */
+#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
+#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
+#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
+#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
+
+#define PCI_MAX_PCI_DEVICES	32
+#define PCI_MAX_PCI_FUNCTIONS	8
+
+#define PCI_FIND_CAP_TTL 0x48
+#define CAP_START_POS 0x40
+
+/* Extended Capabilities (PCI-X 2.0 and Express) */
+#define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
+#define PCI_EXT_CAP_VER(header)		((header >> 16) & 0xf)
+#define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
+
+#define PCI_EXT_CAP_ID_ERR	0x01	/* Advanced Error Reporting */
+#define PCI_EXT_CAP_ID_VC	0x02	/* Virtual Channel Capability */
+#define PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
+#define PCI_EXT_CAP_ID_PWR	0x04	/* Power Budgeting */
+#define PCI_EXT_CAP_ID_RCLD	0x05	/* Root Complex Link Declaration */
+#define PCI_EXT_CAP_ID_RCILC	0x06	/* Root Complex Internal Link Control */
+#define PCI_EXT_CAP_ID_RCEC	0x07	/* Root Complex Event Collector */
+#define PCI_EXT_CAP_ID_MFVC	0x08	/* Multi-Function VC Capability */
+#define PCI_EXT_CAP_ID_VC9	0x09	/* same as _VC */
+#define PCI_EXT_CAP_ID_RCRB	0x0A	/* Root Complex RB? */
+#define PCI_EXT_CAP_ID_VNDR	0x0B	/* Vendor-Specific */
+#define PCI_EXT_CAP_ID_CAC	0x0C	/* Config Access - obsolete */
+#define PCI_EXT_CAP_ID_ACS	0x0D	/* Access Control Services */
+#define PCI_EXT_CAP_ID_ARI	0x0E	/* Alternate Routing ID */
+#define PCI_EXT_CAP_ID_ATS	0x0F	/* Address Translation Services */
+#define PCI_EXT_CAP_ID_SRIOV	0x10	/* Single Root I/O Virtualization */
+#define PCI_EXT_CAP_ID_MRIOV	0x11	/* Multi Root I/O Virtualization */
+#define PCI_EXT_CAP_ID_MCAST	0x12	/* Multicast */
+#define PCI_EXT_CAP_ID_PRI	0x13	/* Page Request Interface */
+#define PCI_EXT_CAP_ID_AMD_XXX	0x14	/* Reserved for AMD */
+#define PCI_EXT_CAP_ID_REBAR	0x15	/* Resizable BAR */
+#define PCI_EXT_CAP_ID_DPA	0x16	/* Dynamic Power Allocation */
+#define PCI_EXT_CAP_ID_TPH	0x17	/* TPH Requester */
+#define PCI_EXT_CAP_ID_LTR	0x18	/* Latency Tolerance Reporting */
+#define PCI_EXT_CAP_ID_SECPCI	0x19	/* Secondary PCIe Capability */
+#define PCI_EXT_CAP_ID_PMUX	0x1A	/* Protocol Multiplexing */
+#define PCI_EXT_CAP_ID_PASID	0x1B	/* Process Address Space ID */
+#define PCI_EXT_CAP_ID_DPC	0x1D	/* Downstream Port Containment */
+#define PCI_EXT_CAP_ID_L1SS	0x1E	/* L1 PM Substates */
+#define PCI_EXT_CAP_ID_PTM	0x1F	/* Precision Time Measurement */
+#define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_PTM
+
+/* Enhanced Allocation Registers */
+#define PCI_EA_NUM_ENT		2	/* Number of Capability Entries */
+#define  PCI_EA_NUM_ENT_MASK	0x3f	/* Num Entries Mask */
+#define PCI_EA_FIRST_ENT	4	/* First EA Entry in List */
+#define  PCI_EA_ES		0x00000007 /* Entry Size */
+#define  PCI_EA_BEI		0x000000f0 /* BAR Equivalent Indicator */
+/* Base, MaxOffset registers */
+/* bit 0 is reserved */
+#define  PCI_EA_IS_64		0x00000002	/* 64-bit field flag */
+#define  PCI_EA_FIELD_MASK	0xfffffffc	/* For Base & Max Offset */
+
+/* PCI Express capabilities */
+#define PCI_EXP_DEVCAP		4	/* Device capabilities */
+#define  PCI_EXP_DEVCAP_FLR     0x10000000 /* Function Level Reset */
+#define PCI_EXP_DEVCTL		8	/* Device Control */
+#define  PCI_EXP_DEVCTL_BCR_FLR 0x8000  /* Bridge Configuration Retry / FLR */
+
+/* Include the ID list */
+
+#include <pci_ids.h>
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_SYS_PCI_64BIT
+typedef u64 pci_addr_t;
+typedef u64 pci_size_t;
+#else
+typedef u32 pci_addr_t;
+typedef u32 pci_size_t;
+#endif
+
+struct pci_region {
+	pci_addr_t bus_start;	/* Start on the bus */
+	phys_addr_t phys_start;	/* Start in physical address space */
+	pci_size_t size;	/* Size */
+	unsigned long flags;	/* Resource flags */
+
+	pci_addr_t bus_lower;
+};
+
+#define PCI_REGION_MEM		0x00000000	/* PCI memory space */
+#define PCI_REGION_IO		0x00000001	/* PCI IO space */
+#define PCI_REGION_TYPE		0x00000001
+#define PCI_REGION_PREFETCH	0x00000008	/* prefetchable PCI memory */
+
+#define PCI_REGION_SYS_MEMORY	0x00000100	/* System memory */
+#define PCI_REGION_RO		0x00000200	/* Read-only memory */
+
+static inline void pci_set_region(struct pci_region *reg,
+				      pci_addr_t bus_start,
+				      phys_addr_t phys_start,
+				      pci_size_t size,
+				      unsigned long flags) {
+	reg->bus_start	= bus_start;
+	reg->phys_start = phys_start;
+	reg->size	= size;
+	reg->flags	= flags;
+}
+
+typedef int pci_dev_t;
+
+#define PCI_BUS(d)		(((d) >> 16) & 0xff)
+
+/*
+ * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot
+ * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0.
+ * Please see the Linux header include/uapi/linux/pci.h for more details.
+ * This is relevant for the following macros:
+ * PCI_DEV, PCI_FUNC, PCI_DEVFN
+ * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with
+ * the remark from above (input d in bits 15-8 instead of 7-0.
+ */
+#define PCI_DEV(d)		(((d) >> 11) & 0x1f)
+#define PCI_FUNC(d)		(((d) >> 8) & 0x7)
+#define PCI_DEVFN(d, f)		((d) << 11 | (f) << 8)
+
+#define PCI_MASK_BUS(bdf)	((bdf) & 0xffff)
+#define PCI_ADD_BUS(bus, devfn)	(((bus) << 16) | (devfn))
+#define PCI_BDF(b, d, f)	((b) << 16 | PCI_DEVFN(d, f))
+#define PCI_VENDEV(v, d)	(((v) << 16) | (d))
+#define PCI_ANY_ID		(~0)
+
+struct pci_device_id {
+	unsigned int vendor, device;	/* Vendor and device ID or PCI_ANY_ID */
+	unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
+	unsigned int class, class_mask;	/* (class,subclass,prog-if) triplet */
+	unsigned long driver_data;	/* Data private to the driver */
+};
+
+struct pci_controller;
+
+struct pci_config_table {
+	unsigned int vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
+	unsigned int class;			/* Class ID, or  PCI_ANY_ID */
+	unsigned int bus;			/* Bus number, or PCI_ANY_ID */
+	unsigned int dev;			/* Device number, or PCI_ANY_ID */
+	unsigned int func;			/* Function number, or PCI_ANY_ID */
+
+	void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
+			      struct pci_config_table *);
+	unsigned long priv[3];
+};
+
+extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
+				   struct pci_config_table *);
+extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
+				      struct pci_config_table *);
+
+#define MAX_PCI_REGIONS		7
+
+#define INDIRECT_TYPE_NO_PCIE_LINK	1
+
+/*
+ * Structure of a PCI controller (host bridge)
+ *
+ * With driver model this is dev_get_uclass_priv(bus)
+ */
+struct pci_controller {
+#ifdef CONFIG_DM_PCI
+	struct udevice *bus;
+	struct udevice *ctlr;
+#else
+	struct pci_controller *next;
+#endif
+
+	int first_busno;
+	int last_busno;
+
+	volatile unsigned int *cfg_addr;
+	volatile unsigned char *cfg_data;
+
+	int indirect_type;
+
+	/*
+	 * TODO(sjg@chromium.org): With driver model we use struct
+	 * pci_controller for both the controller and any bridge devices
+	 * attached to it. But there is only one region list and it is in the
+	 * top-level controller.
+	 *
+	 * This could be changed so that struct pci_controller is only used
+	 * for PCI controllers and a separate UCLASS (or perhaps
+	 * UCLASS_PCI_GENERIC) is used for bridges.
+	 */
+	struct pci_region regions[MAX_PCI_REGIONS];
+	int region_count;
+
+	struct pci_config_table *config_table;
+
+	void (*fixup_irq)(struct pci_controller *, pci_dev_t);
+#ifndef CONFIG_DM_PCI
+	/* Low-level architecture-dependent routines */
+	int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
+	int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
+	int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
+	int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
+	int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
+	int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
+#endif
+
+	/* Used by auto config */
+	struct pci_region *pci_mem, *pci_io, *pci_prefetch;
+
+#ifndef CONFIG_DM_PCI
+	int current_busno;
+
+	void *priv_data;
+#endif
+};
+
+#ifndef CONFIG_DM_PCI
+static inline void pci_set_ops(struct pci_controller *hose,
+				   int (*read_byte)(struct pci_controller*,
+						    pci_dev_t, int where, u8 *),
+				   int (*read_word)(struct pci_controller*,
+						    pci_dev_t, int where, u16 *),
+				   int (*read_dword)(struct pci_controller*,
+						     pci_dev_t, int where, u32 *),
+				   int (*write_byte)(struct pci_controller*,
+						     pci_dev_t, int where, u8),
+				   int (*write_word)(struct pci_controller*,
+						     pci_dev_t, int where, u16),
+				   int (*write_dword)(struct pci_controller*,
+						      pci_dev_t, int where, u32)) {
+	hose->read_byte   = read_byte;
+	hose->read_word   = read_word;
+	hose->read_dword  = read_dword;
+	hose->write_byte  = write_byte;
+	hose->write_word  = write_word;
+	hose->write_dword = write_dword;
+}
+#endif
+
+#ifdef CONFIG_PCI_INDIRECT_BRIDGE
+extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
+#endif
+
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
+extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
+					pci_addr_t addr, unsigned long flags);
+extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
+					phys_addr_t addr, unsigned long flags);
+
+#define pci_phys_to_bus(dev, addr, flags) \
+	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
+#define pci_bus_to_phys(dev, addr, flags) \
+	pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
+
+#define pci_virt_to_bus(dev, addr, flags) \
+	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
+			     (virt_to_phys(addr)), (flags))
+#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
+	map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
+					 (addr), (flags)), \
+		    (len), (map_flags))
+
+#define pci_phys_to_mem(dev, addr) \
+	pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
+#define pci_mem_to_phys(dev, addr) \
+	pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
+#define pci_phys_to_io(dev, addr)  pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
+#define pci_io_to_phys(dev, addr)  pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+
+#define pci_virt_to_mem(dev, addr) \
+	pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
+#define pci_mem_to_virt(dev, addr, len, map_flags) \
+	pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
+#define pci_virt_to_io(dev, addr) \
+	pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
+#define pci_io_to_virt(dev, addr, len, map_flags) \
+	pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
+
+/* For driver model these are defined in macros in pci_compat.c */
+extern int pci_hose_read_config_byte(struct pci_controller *hose,
+				     pci_dev_t dev, int where, u8 *val);
+extern int pci_hose_read_config_word(struct pci_controller *hose,
+				     pci_dev_t dev, int where, u16 *val);
+extern int pci_hose_read_config_dword(struct pci_controller *hose,
+				      pci_dev_t dev, int where, u32 *val);
+extern int pci_hose_write_config_byte(struct pci_controller *hose,
+				      pci_dev_t dev, int where, u8 val);
+extern int pci_hose_write_config_word(struct pci_controller *hose,
+				      pci_dev_t dev, int where, u16 val);
+extern int pci_hose_write_config_dword(struct pci_controller *hose,
+				       pci_dev_t dev, int where, u32 val);
+#endif
+
+#ifndef CONFIG_DM_PCI
+extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
+extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
+extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
+extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
+extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
+extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
+#endif
+
+void pciauto_region_init(struct pci_region *res);
+void pciauto_region_align(struct pci_region *res, pci_size_t size);
+void pciauto_config_init(struct pci_controller *hose);
+
+/**
+ * pciauto_region_allocate() - Allocate resources from a PCI resource region
+ *
+ * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
+ * false, the result will be guaranteed to fit in 32 bits.
+ *
+ * @res:		PCI region to allocate from
+ * @size:		Amount of bytes to allocate
+ * @bar:		Returns the PCI bus address of the allocated resource
+ * @supports_64bit:	Whether to allow allocations above the 32-bit boundary
+ * @return 0 if successful, -1 on failure
+ */
+int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
+			    pci_addr_t *bar, bool supports_64bit);
+
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
+extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
+					       pci_dev_t dev, int where, u8 *val);
+extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
+					       pci_dev_t dev, int where, u16 *val);
+extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
+						pci_dev_t dev, int where, u8 val);
+extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
+						pci_dev_t dev, int where, u16 val);
+
+extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
+extern void pci_register_hose(struct pci_controller* hose);
+extern struct pci_controller* pci_bus_to_hose(int bus);
+extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
+extern struct pci_controller *pci_get_hose_head(void);
+
+extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
+extern int pci_hose_scan(struct pci_controller *hose);
+extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
+
+extern void pciauto_setup_device(struct pci_controller *hose,
+				 pci_dev_t dev, int bars_num,
+				 struct pci_region *mem,
+				 struct pci_region *prefetch,
+				 struct pci_region *io);
+extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
+				 pci_dev_t dev, int sub_bus);
+extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
+				 pci_dev_t dev, int sub_bus);
+extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
+
+extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
+extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
+pci_dev_t pci_find_class(unsigned int find_class, int index);
+
+extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
+				    int cap);
+extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
+				   u8 hdr_type);
+extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
+			int cap);
+
+int pci_find_next_ext_capability(struct pci_controller *hose,
+				 pci_dev_t dev, int start, int cap);
+int pci_hose_find_ext_capability(struct pci_controller *hose,
+				 pci_dev_t dev, int cap);
+
+#ifdef CONFIG_PCI_FIXUP_DEV
+extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
+				unsigned short vendor,
+				unsigned short device,
+				unsigned short class);
+#endif
+#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
+
+const char * pci_class_str(u8 class);
+int pci_last_busno(void);
+
+#ifdef CONFIG_MPC85xx
+extern void pci_mpc85xx_init (struct pci_controller *hose);
+#endif
+
+#ifdef CONFIG_PCIE_IMX
+extern void imx_pcie_remove(void);
+#endif
+
+#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
+/**
+ * pci_write_bar32() - Write the address of a BAR including control bits
+ *
+ * This writes a raw address (with control bits) to a bar. This can be used
+ * with devices which require hard-coded addresses, not part of the normal
+ * PCI enumeration process.
+ *
+ * @hose:	PCI hose to use
+ * @dev:	PCI device to update
+ * @barnum:	BAR number (0-5)
+ * @addr:	BAR address with control bits
+ */
+void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
+		     u32 addr);
+
+/**
+ * pci_read_bar32() - read the address of a bar
+ *
+ * @hose:	PCI hose to use
+ * @dev:	PCI device to inspect
+ * @barnum:	BAR number (0-5)
+ * @return address of the bar, masking out any control bits
+ * */
+u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
+
+/**
+ * pci_hose_find_devices() - Find devices by vendor/device ID
+ *
+ * @hose:	PCI hose to search
+ * @busnum:	Bus number to search
+ * @ids:	PCI vendor/device IDs to look for, terminated by 0, 0 record
+ * @indexp:	Pointer to device index to find. To find the first matching
+ *		device, pass 0; to find the second, pass 1, etc. This
+ *		parameter is decremented for each non-matching device so
+ *		can be called repeatedly.
+ */
+pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
+				struct pci_device_id *ids, int *indexp);
+#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
+
+/* Access sizes for PCI reads and writes */
+enum pci_size_t {
+	PCI_SIZE_8,
+	PCI_SIZE_16,
+	PCI_SIZE_32,
+};
+
+struct udevice;
+
+#ifdef CONFIG_DM_PCI
+/**
+ * struct pci_child_platdata - information stored about each PCI device
+ *
+ * Every device on a PCI bus has this per-child data.
+ *
+ * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a
+ * PCI bus (i.e. UCLASS_PCI)
+ *
+ * @devfn:	Encoded device and function index - see PCI_DEVFN()
+ * @vendor:	PCI vendor ID (see pci_ids.h)
+ * @device:	PCI device ID (see pci_ids.h)
+ * @class:	PCI class, 3 bytes: (base, sub, prog-if)
+ */
+struct pci_child_platdata {
+	int devfn;
+	unsigned short vendor;
+	unsigned short device;
+	unsigned int class;
+};
+
+/* PCI bus operations */
+struct dm_pci_ops {
+	/**
+	 * read_config() - Read a PCI configuration value
+	 *
+	 * PCI buses must support reading and writing configuration values
+	 * so that the bus can be scanned and its devices configured.
+	 *
+	 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
+	 * If bridges exist it is possible to use the top-level bus to
+	 * access a sub-bus. In that case @bus will be the top-level bus
+	 * and PCI_BUS(bdf) will be a different (higher) value
+	 *
+	 * @bus:	Bus to read from
+	 * @bdf:	Bus, device and function to read
+	 * @offset:	Byte offset within the device's configuration space
+	 * @valuep:	Place to put the returned value
+	 * @size:	Access size
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
+			   ulong *valuep, enum pci_size_t size);
+	/**
+	 * write_config() - Write a PCI configuration value
+	 *
+	 * @bus:	Bus to write to
+	 * @bdf:	Bus, device and function to write
+	 * @offset:	Byte offset within the device's configuration space
+	 * @value:	Value to write
+	 * @size:	Access size
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
+			    ulong value, enum pci_size_t size);
+};
+
+/* Get access to a PCI bus' operations */
+#define pci_get_ops(dev)	((struct dm_pci_ops *)(dev)->driver->ops)
+
+/**
+ * dm_pci_get_bdf() - Get the BDF value for a device
+ *
+ * @dev:	Device to check
+ * @return bus/device/function value (see PCI_BDF())
+ */
+pci_dev_t dm_pci_get_bdf(struct udevice *dev);
+
+/**
+ * pci_bind_bus_devices() - scan a PCI bus and bind devices
+ *
+ * Scan a PCI bus looking for devices. Bind each one that is found. If
+ * devices are already bound that match the scanned devices, just update the
+ * child data so that the device can be used correctly (this happens when
+ * the device tree describes devices we expect to see on the bus).
+ *
+ * Devices that are bound in this way will use a generic PCI driver which
+ * does nothing. The device can still be accessed but will not provide any
+ * driver interface.
+ *
+ * @bus:	Bus containing devices to bind
+ * @return 0 if OK, -ve on error
+ */
+int pci_bind_bus_devices(struct udevice *bus);
+
+/**
+ * pci_auto_config_devices() - configure bus devices ready for use
+ *
+ * This works through all devices on a bus by scanning the driver model
+ * data structures (normally these have been set up by pci_bind_bus_devices()
+ * earlier).
+ *
+ * Space is allocated for each PCI base address register (BAR) so that the
+ * devices are mapped into memory and I/O space ready for use.
+ *
+ * @bus:	Bus containing devices to bind
+ * @return 0 if OK, -ve on error
+ */
+int pci_auto_config_devices(struct udevice *bus);
+
+/**
+ * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
+ *
+ * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
+ * @devp:	Returns the device for this address, if found
+ * @return 0 if OK, -ENODEV if not found
+ */
+int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
+
+/**
+ * pci_bus_find_devfn() - Find a device on a bus
+ *
+ * @find_devfn:		PCI device address (device and function only)
+ * @devp:	Returns the device for this address, if found
+ * @return 0 if OK, -ENODEV if not found
+ */
+int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
+		       struct udevice **devp);
+
+/**
+ * pci_find_first_device() - return the first available PCI device
+ *
+ * This function and pci_find_first_device() allow iteration through all
+ * available PCI devices on all buses. Assuming there are any, this will
+ * return the first one.
+ *
+ * @devp:	Set to the first available device, or NULL if no more are left
+ *		or we got an error
+ * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
+ */
+int pci_find_first_device(struct udevice **devp);
+
+/**
+ * pci_find_next_device() - return the next available PCI device
+ *
+ * Finds the next available PCI device after the one supplied, or sets @devp
+ * to NULL if there are no more.
+ *
+ * @devp:	On entry, the last device returned. Set to the next available
+ *		device, or NULL if no more are left or we got an error
+ * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
+ */
+int pci_find_next_device(struct udevice **devp);
+
+/**
+ * pci_get_ff() - Returns a mask for the given access size
+ *
+ * @size:	Access size
+ * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
+ * PCI_SIZE_32
+ */
+int pci_get_ff(enum pci_size_t size);
+
+/**
+ * pci_bus_find_devices () - Find devices on a bus
+ *
+ * @bus:	Bus to search
+ * @ids:	PCI vendor/device IDs to look for, terminated by 0, 0 record
+ * @indexp:	Pointer to device index to find. To find the first matching
+ *		device, pass 0; to find the second, pass 1, etc. This
+ *		parameter is decremented for each non-matching device so
+ *		can be called repeatedly.
+ * @devp:	Returns matching device if found
+ * @return 0 if found, -ENODEV if not
+ */
+int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
+			 int *indexp, struct udevice **devp);
+
+/**
+ * pci_find_device_id() - Find a device on any bus
+ *
+ * @ids:	PCI vendor/device IDs to look for, terminated by 0, 0 record
+ * @index:	Index number of device to find, 0 for the first match, 1 for
+ *		the second, etc.
+ * @devp:	Returns matching device if found
+ * @return 0 if found, -ENODEV if not
+ */
+int pci_find_device_id(struct pci_device_id *ids, int index,
+		       struct udevice **devp);
+
+/**
+ * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
+ *
+ * This probes the given bus which causes it to be scanned for devices. The
+ * devices will be bound but not probed.
+ *
+ * @hose specifies the PCI hose that will be used for the scan. This is
+ * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
+ * in @bdf, and is a subordinate bus reachable from @hose.
+ *
+ * @hose:	PCI hose to scan
+ * @bdf:	PCI bus address to scan (PCI_BUS(bdf) is the bus number)
+ * @return 0 if OK, -ve on error
+ */
+int dm_pci_hose_probe_bus(struct udevice *bus);
+
+/**
+ * pci_bus_read_config() - Read a configuration value from a device
+ *
+ * TODO(sjg@chromium.org): We should be able to pass just a device and have
+ * it do the right thing. It would be good to have that function also.
+ *
+ * @bus:	Bus to read from
+ * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:	Register offset to read
+ * @valuep:	Place to put the returned value
+ * @size:	Access size
+ * @return 0 if OK, -ve on error
+ */
+int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
+			unsigned long *valuep, enum pci_size_t size);
+
+/**
+ * pci_bus_write_config() - Write a configuration value to a device
+ *
+ * @bus:	Bus to write from
+ * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:	Register offset to write
+ * @value:	Value to write
+ * @size:	Access size
+ * @return 0 if OK, -ve on error
+ */
+int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
+			 unsigned long value, enum pci_size_t size);
+
+/**
+ * pci_bus_clrset_config32() - Update a configuration value for a device
+ *
+ * The register at @offset is updated to (oldvalue & ~clr) | set.
+ *
+ * @bus:	Bus to access
+ * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
+ * @offset:	Register offset to update
+ * @clr:	Bits to clear
+ * @set:	Bits to set
+ * @return 0 if OK, -ve on error
+ */
+int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
+			    u32 clr, u32 set);
+
+/**
+ * Driver model PCI config access functions. Use these in preference to others
+ * when you have a valid device
+ */
+int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
+		       enum pci_size_t size);
+
+int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
+int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
+int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
+
+int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
+			enum pci_size_t size);
+
+int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
+int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
+int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
+
+/**
+ * These permit convenient read/modify/write on PCI configuration. The
+ * register is updated to (oldvalue & ~clr) | set.
+ */
+int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
+int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
+int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
+
+/*
+ * The following functions provide access to the above without needing the
+ * size parameter. We are trying to encourage the use of the 8/16/32-style
+ * functions, rather than byte/word/dword. But both are supported.
+ */
+int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
+int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
+int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
+int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
+int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
+int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
+
+/**
+ * pci_generic_mmap_write_config() - Generic helper for writing to
+ * memory-mapped PCI configuration space.
+ * @bus: Pointer to the PCI bus
+ * @addr_f: Callback for calculating the config space address
+ * @bdf: Identifies the PCI device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Write the value @value of size @size from offset @offset within the
+ * configuration space of the device identified by the bus, device & function
+ * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
+ * responsible for calculating the CPU address of the respective configuration
+ * space offset.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+int pci_generic_mmap_write_config(
+	struct udevice *bus,
+	int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+	pci_dev_t bdf,
+	uint offset,
+	ulong value,
+	enum pci_size_t size);
+
+/**
+ * pci_generic_mmap_read_config() - Generic helper for reading from
+ * memory-mapped PCI configuration space.
+ * @bus: Pointer to the PCI bus
+ * @addr_f: Callback for calculating the config space address
+ * @bdf: Identifies the PCI device to access
+ * @offset: The offset into the device's configuration space
+ * @valuep: A pointer at which to store the read value
+ * @size: Indicates the size of access to perform
+ *
+ * Read a value of size @size from offset @offset within the configuration
+ * space of the device identified by the bus, device & function numbers in @bdf
+ * on the PCI bus @bus. The callback function @addr_f is responsible for
+ * calculating the CPU address of the respective configuration space offset.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+int pci_generic_mmap_read_config(
+	struct udevice *bus,
+	int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+	pci_dev_t bdf,
+	uint offset,
+	ulong *valuep,
+	enum pci_size_t size);
+
+#ifdef CONFIG_DM_PCI_COMPAT
+/* Compatibility with old naming */
+static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
+					 u32 value)
+{
+	return pci_write_config32(pcidev, offset, value);
+}
+
+/* Compatibility with old naming */
+static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
+					u16 value)
+{
+	return pci_write_config16(pcidev, offset, value);
+}
+
+/* Compatibility with old naming */
+static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
+					u8 value)
+{
+	return pci_write_config8(pcidev, offset, value);
+}
+
+/* Compatibility with old naming */
+static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
+					u32 *valuep)
+{
+	return pci_read_config32(pcidev, offset, valuep);
+}
+
+/* Compatibility with old naming */
+static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
+				       u16 *valuep)
+{
+	return pci_read_config16(pcidev, offset, valuep);
+}
+
+/* Compatibility with old naming */
+static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
+				       u8 *valuep)
+{
+	return pci_read_config8(pcidev, offset, valuep);
+}
+#endif /* CONFIG_DM_PCI_COMPAT */
+
+/**
+ * dm_pciauto_config_device() - configure a device ready for use
+ *
+ * Space is allocated for each PCI base address register (BAR) so that the
+ * devices are mapped into memory and I/O space ready for use.
+ *
+ * @dev:	Device to configure
+ * @return 0 if OK, -ve on error
+ */
+int dm_pciauto_config_device(struct udevice *dev);
+
+/**
+ * pci_conv_32_to_size() - convert a 32-bit read value to the given size
+ *
+ * Some PCI buses must always perform 32-bit reads. The data must then be
+ * shifted and masked to reflect the required access size and offset. This
+ * function performs this transformation.
+ *
+ * @value:	Value to transform (32-bit value read from @offset & ~3)
+ * @offset:	Register offset that was read
+ * @size:	Required size of the result
+ * @return the value that would have been obtained if the read had been
+ * performed at the given offset with the correct size
+ */
+ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
+
+/**
+ * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
+ *
+ * Some PCI buses must always perform 32-bit writes. To emulate a smaller
+ * write the old 32-bit data must be read, updated with the required new data
+ * and written back as a 32-bit value. This function performs the
+ * transformation from the old value to the new value.
+ *
+ * @value:	Value to transform (32-bit value read from @offset & ~3)
+ * @offset:	Register offset that should be written
+ * @size:	Required size of the write
+ * @return the value that should be written as a 32-bit access to @offset & ~3.
+ */
+ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
+			  enum pci_size_t size);
+
+/**
+ * pci_get_controller() - obtain the controller to use for a bus
+ *
+ * @dev:	Device to check
+ * @return pointer to the controller device for this bus
+ */
+struct udevice *pci_get_controller(struct udevice *dev);
+
+/**
+ * pci_get_regions() - obtain pointers to all the region types
+ *
+ * @dev:	Device to check
+ * @iop:	Returns a pointer to the I/O region, or NULL if none
+ * @memp:	Returns a pointer to the memory region, or NULL if none
+ * @prefp:	Returns a pointer to the pre-fetch region, or NULL if none
+ * @return the number of non-NULL regions returned, normally 3
+ */
+int pci_get_regions(struct udevice *dev, struct pci_region **iop,
+		    struct pci_region **memp, struct pci_region **prefp);
+
+/**
+ * dm_pci_write_bar32() - Write the address of a BAR
+ *
+ * This writes a raw address to a bar
+ *
+ * @dev:	PCI device to update
+ * @barnum:	BAR number (0-5)
+ * @addr:	BAR address
+ */
+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
+
+/**
+ * dm_pci_read_bar32() - read a base address register from a device
+ *
+ * @dev:	Device to check
+ * @barnum:	Bar number to read (numbered from 0)
+ * @return: value of BAR
+ */
+u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
+
+/**
+ * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
+ *
+ * @dev:	Device containing the PCI address
+ * @addr:	PCI address to convert
+ * @flags:	Flags for the region type (PCI_REGION_...)
+ * @return physical address corresponding to that PCI bus address
+ */
+phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
+			       unsigned long flags);
+
+/**
+ * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
+ *
+ * @dev:	Device containing the bus address
+ * @addr:	Physical address to convert
+ * @flags:	Flags for the region type (PCI_REGION_...)
+ * @return PCI bus address corresponding to that physical address
+ */
+pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
+			      unsigned long flags);
+
+/**
+ * dm_pci_map_bar() - get a virtual address associated with a BAR region
+ *
+ * Looks up a base address register and finds the physical memory address
+ * that corresponds to it.
+ * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
+ * type 1 functions.
+ * Can also be used on type 0 functions that support Enhanced Allocation for
+ * 32b/64b BARs.  Note that duplicate BEI entries are not supported.
+ *
+ * @dev:	Device to check
+ * @bar:	Bar register offset (PCI_BASE_ADDRESS_...)
+ * @flags:	Flags for the region type (PCI_REGION_...)
+ * @return: pointer to the virtual address to use or 0 on error
+ */
+void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
+
+/**
+ * dm_pci_find_next_capability() - find a capability starting from an offset
+ *
+ * Tell if a device supports a given PCI capability. Returns the
+ * address of the requested capability structure within the device's
+ * PCI configuration space or 0 in case the device does not support it.
+ *
+ * Possible values for @cap:
+ *
+ *  %PCI_CAP_ID_MSI	Message Signalled Interrupts
+ *  %PCI_CAP_ID_PCIX	PCI-X
+ *  %PCI_CAP_ID_EXP	PCI Express
+ *  %PCI_CAP_ID_MSIX	MSI-X
+ *
+ * See PCI_CAP_ID_xxx for the complete capability ID codes.
+ *
+ * @dev:	PCI device to query
+ * @start:	offset to start from
+ * @cap:	capability code
+ * @return:	capability address or 0 if not supported
+ */
+int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
+
+/**
+ * dm_pci_find_capability() - find a capability
+ *
+ * Tell if a device supports a given PCI capability. Returns the
+ * address of the requested capability structure within the device's
+ * PCI configuration space or 0 in case the device does not support it.
+ *
+ * Possible values for @cap:
+ *
+ *  %PCI_CAP_ID_MSI	Message Signalled Interrupts
+ *  %PCI_CAP_ID_PCIX	PCI-X
+ *  %PCI_CAP_ID_EXP	PCI Express
+ *  %PCI_CAP_ID_MSIX	MSI-X
+ *
+ * See PCI_CAP_ID_xxx for the complete capability ID codes.
+ *
+ * @dev:	PCI device to query
+ * @cap:	capability code
+ * @return:	capability address or 0 if not supported
+ */
+int dm_pci_find_capability(struct udevice *dev, int cap);
+
+/**
+ * dm_pci_find_next_ext_capability() - find an extended capability
+ *				       starting from an offset
+ *
+ * Tell if a device supports a given PCI express extended capability.
+ * Returns the address of the requested extended capability structure
+ * within the device's PCI configuration space or 0 in case the device
+ * does not support it.
+ *
+ * Possible values for @cap:
+ *
+ *  %PCI_EXT_CAP_ID_ERR	Advanced Error Reporting
+ *  %PCI_EXT_CAP_ID_VC	Virtual Channel
+ *  %PCI_EXT_CAP_ID_DSN	Device Serial Number
+ *  %PCI_EXT_CAP_ID_PWR	Power Budgeting
+ *
+ * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
+ *
+ * @dev:	PCI device to query
+ * @start:	offset to start from
+ * @cap:	extended capability code
+ * @return:	extended capability address or 0 if not supported
+ */
+int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
+
+/**
+ * dm_pci_find_ext_capability() - find an extended capability
+ *
+ * Tell if a device supports a given PCI express extended capability.
+ * Returns the address of the requested extended capability structure
+ * within the device's PCI configuration space or 0 in case the device
+ * does not support it.
+ *
+ * Possible values for @cap:
+ *
+ *  %PCI_EXT_CAP_ID_ERR	Advanced Error Reporting
+ *  %PCI_EXT_CAP_ID_VC	Virtual Channel
+ *  %PCI_EXT_CAP_ID_DSN	Device Serial Number
+ *  %PCI_EXT_CAP_ID_PWR	Power Budgeting
+ *
+ * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
+ *
+ * @dev:	PCI device to query
+ * @cap:	extended capability code
+ * @return:	extended capability address or 0 if not supported
+ */
+int dm_pci_find_ext_capability(struct udevice *dev, int cap);
+
+/**
+ * dm_pci_flr() - Perform FLR if the device suppoorts it
+ *
+ * @dev:	PCI device to reset
+ * @return:	0 if OK, -ENOENT if FLR is not supported by dev
+ */
+int dm_pci_flr(struct udevice *dev);
+
+#define dm_pci_virt_to_bus(dev, addr, flags) \
+	dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
+#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
+	map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
+		    (len), (map_flags))
+
+#define dm_pci_phys_to_mem(dev, addr) \
+	dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_mem_to_phys(dev, addr) \
+	dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_phys_to_io(dev, addr) \
+	dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
+#define dm_pci_io_to_phys(dev, addr) \
+	dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+
+#define dm_pci_virt_to_mem(dev, addr) \
+	dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
+#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
+	dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
+#define dm_pci_virt_to_io(dev, addr) \
+	dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
+#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
+	dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
+
+/**
+ * dm_pci_find_device() - find a device by vendor/device ID
+ *
+ * @vendor:	Vendor ID
+ * @device:	Device ID
+ * @index:	0 to find the first match, 1 for second, etc.
+ * @devp:	Returns pointer to the device, if found
+ * @return 0 if found, -ve on error
+ */
+int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
+		       struct udevice **devp);
+
+/**
+ * dm_pci_find_class() - find a device by class
+ *
+ * @find_class: 3-byte (24-bit) class value to find
+ * @index:	0 to find the first match, 1 for second, etc.
+ * @devp:	Returns pointer to the device, if found
+ * @return 0 if found, -ve on error
+ */
+int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
+
+/**
+ * struct pci_emul_uc_priv - holds info about an emulator device
+ *
+ * There is always at most one emulator per client
+ *
+ * @client: Client device if any, else NULL
+ */
+struct pci_emul_uc_priv {
+	struct udevice *client;
+};
+
+/**
+ * struct dm_pci_emul_ops - PCI device emulator operations
+ */
+struct dm_pci_emul_ops {
+	/**
+	 * read_config() - Read a PCI configuration value
+	 *
+	 * @dev:	Emulated device to read from
+	 * @offset:	Byte offset within the device's configuration space
+	 * @valuep:	Place to put the returned value
+	 * @size:	Access size
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
+			   enum pci_size_t size);
+	/**
+	 * write_config() - Write a PCI configuration value
+	 *
+	 * @dev:	Emulated device to write to
+	 * @offset:	Byte offset within the device's configuration space
+	 * @value:	Value to write
+	 * @size:	Access size
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*write_config)(struct udevice *dev, uint offset, ulong value,
+			    enum pci_size_t size);
+	/**
+	 * read_io() - Read a PCI I/O value
+	 *
+	 * @dev:	Emulated device to read from
+	 * @addr:	I/O address to read
+	 * @valuep:	Place to put the returned value
+	 * @size:	Access size
+	 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
+	 *		other -ve value on error
+	 */
+	int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
+		       enum pci_size_t size);
+	/**
+	 * write_io() - Write a PCI I/O value
+	 *
+	 * @dev:	Emulated device to write from
+	 * @addr:	I/O address to write
+	 * @value:	Value to write
+	 * @size:	Access size
+	 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
+	 *		other -ve value on error
+	 */
+	int (*write_io)(struct udevice *dev, unsigned int addr,
+			ulong value, enum pci_size_t size);
+	/**
+	 * map_physmem() - Map a device into sandbox memory
+	 *
+	 * @dev:	Emulated device to map
+	 * @addr:	Memory address, normally corresponding to a PCI BAR.
+	 *		The device should have been configured to have a BAR
+	 *		at this address.
+	 * @lenp:	On entry, the size of the area to map, On exit it is
+	 *		updated to the size actually mapped, which may be less
+	 *		if the device has less space
+	 * @ptrp:	Returns a pointer to the mapped address. The device's
+	 *		space can be accessed as @lenp bytes starting here
+	 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
+	 *		other -ve value on error
+	 */
+	int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
+			   unsigned long *lenp, void **ptrp);
+	/**
+	 * unmap_physmem() - undo a memory mapping
+	 *
+	 * This must be called after map_physmem() to undo the mapping.
+	 * Some devices can use this to check what has been written into
+	 * their mapped memory and perform an operations they require on it.
+	 * In this way, map/unmap can be used as a sort of handshake between
+	 * the emulated device and its users.
+	 *
+	 * @dev:	Emuated device to unmap
+	 * @vaddr:	Mapped memory address, as passed to map_physmem()
+	 * @len:	Size of area mapped, as returned by map_physmem()
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
+			     unsigned long len);
+};
+
+/* Get access to a PCI device emulator's operations */
+#define pci_get_emul_ops(dev)	((struct dm_pci_emul_ops *)(dev)->driver->ops)
+
+/**
+ * sandbox_pci_get_emul() - Get the emulation device for a PCI device
+ *
+ * Searches for a suitable emulator for the given PCI bus device
+ *
+ * @bus:	PCI bus to search
+ * @find_devfn:	PCI device and function address (PCI_DEVFN())
+ * @containerp:	Returns container device if found
+ * @emulp:	Returns emulated device if found
+ * @return 0 if found, -ENODEV if not found
+ */
+int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
+			 struct udevice **containerp, struct udevice **emulp);
+
+/**
+ * sandbox_pci_get_client() - Find the client for an emulation device
+ *
+ * @emul:	Emulation device to check
+ * @devp:	Returns the client device emulated by this device
+ * @return 0 if OK, -ENOENT if the device has no client yet
+ */
+int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
+
+/**
+ * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device
+ *
+ * Get devfn from fdt_pci_addr of the specified device
+ *
+ * @dev:	PCI device
+ * @return devfn in bits 15...8 if found, -ENODEV if not found
+ */
+int pci_get_devfn(struct udevice *dev);
+
+#endif /* CONFIG_DM_PCI */
+
+/**
+ * PCI_DEVICE - macro used to describe a specific pci device
+ * @vend: the 16 bit PCI Vendor ID
+ * @dev: the 16 bit PCI Device ID
+ *
+ * This macro is used to create a struct pci_device_id that matches a
+ * specific device.  The subvendor and subdevice fields will be set to
+ * PCI_ANY_ID.
+ */
+#define PCI_DEVICE(vend, dev) \
+	.vendor = (vend), .device = (dev), \
+	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
+
+/**
+ * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
+ * @vend: the 16 bit PCI Vendor ID
+ * @dev: the 16 bit PCI Device ID
+ * @subvend: the 16 bit PCI Subvendor ID
+ * @subdev: the 16 bit PCI Subdevice ID
+ *
+ * This macro is used to create a struct pci_device_id that matches a
+ * specific device with subsystem information.
+ */
+#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
+	.vendor = (vend), .device = (dev), \
+	.subvendor = (subvend), .subdevice = (subdev)
+
+/**
+ * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
+ * @dev_class: the class, subclass, prog-if triple for this device
+ * @dev_class_mask: the class mask for this device
+ *
+ * This macro is used to create a struct pci_device_id that matches a
+ * specific PCI class.  The vendor, device, subvendor, and subdevice
+ * fields will be set to PCI_ANY_ID.
+ */
+#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
+	.class = (dev_class), .class_mask = (dev_class_mask), \
+	.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
+	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
+
+/**
+ * PCI_VDEVICE - macro used to describe a specific pci device in short form
+ * @vend: the vendor name
+ * @dev: the 16 bit PCI Device ID
+ *
+ * This macro is used to create a struct pci_device_id that matches a
+ * specific PCI device.  The subvendor, and subdevice fields will be set
+ * to PCI_ANY_ID. The macro allows the next field to follow as the device
+ * private data.
+ */
+
+#define PCI_VDEVICE(vend, dev) \
+	.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
+	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
+
+/**
+ * struct pci_driver_entry - Matches a driver to its pci_device_id list
+ * @driver: Driver to use
+ * @match: List of match records for this driver, terminated by {}
+ */
+struct pci_driver_entry {
+	struct driver *driver;
+	const struct pci_device_id *match;
+};
+
+#define U_BOOT_PCI_DEVICE(__name, __match)				\
+	ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
+		.driver = llsym(struct driver, __name, driver), \
+		.match = __match, \
+		}
+
+#endif /* __ASSEMBLY__ */
+#endif /* _PCI_H */
diff --git a/include/pci_ep.h b/include/pci_ep.h
new file mode 100644
index 0000000..00e8c6d
--- /dev/null
+++ b/include/pci_ep.h
@@ -0,0 +1,414 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Adapted from Linux kernel driver
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * (C) Copyright 2019
+ * Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#ifndef _PCI_EP_H
+#define _PCI_EP_H
+
+#include <pci.h>
+
+/**
+ * enum pci_interrupt_pin - PCI INTx interrupt values
+ * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
+ * @PCI_INTERRUPT_INTA: PCI INTA pin
+ * @PCI_INTERRUPT_INTB: PCI INTB pin
+ * @PCI_INTERRUPT_INTC: PCI INTC pin
+ * @PCI_INTERRUPT_INTD: PCI INTD pin
+ *
+ * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
+ * PCI_INTERRUPT_PIN register.
+ */
+enum pci_interrupt_pin {
+	PCI_INTERRUPT_UNKNOWN,
+	PCI_INTERRUPT_INTA,
+	PCI_INTERRUPT_INTB,
+	PCI_INTERRUPT_INTC,
+	PCI_INTERRUPT_INTD,
+};
+
+enum pci_barno {
+	BAR_0,
+	BAR_1,
+	BAR_2,
+	BAR_3,
+	BAR_4,
+	BAR_5,
+};
+
+enum pci_ep_irq_type {
+	PCI_EP_IRQ_UNKNOWN,
+	PCI_EP_IRQ_LEGACY,
+	PCI_EP_IRQ_MSI,
+	PCI_EP_IRQ_MSIX,
+};
+
+/**
+ * struct pci_bar - represents the BAR (Base Address Register) of EP device
+ * @phys_addr: physical address that should be mapped to the BAR
+ * @size: the size of the address space present in BAR
+ * pci_barno: number of pci BAR to set (0..5)
+ * @flags: BAR access flags
+ */
+struct pci_bar {
+	dma_addr_t	phys_addr;
+	size_t		size;
+	enum pci_barno	barno;
+	int		flags;
+};
+
+/**
+ * struct pci_ep_header - represents standard configuration header
+ * @vendorid: identifies device manufacturer
+ * @deviceid: identifies a particular device
+ * @revid: specifies a device-specific revision identifier
+ * @progif_code: identifies a specific register-level programming interface
+ * @subclass_code: identifies more specifically the function of the device
+ * @baseclass_code: broadly classifies the type of function the device performs
+ * @cache_line_size: specifies the system cacheline size in units of DWORDs
+ * @subsys_vendor_id: vendor of the add-in card or subsystem
+ * @subsys_id: id specific to vendor
+ * @interrupt_pin: interrupt pin the device (or device function) uses
+ */
+struct pci_ep_header {
+	u16	vendorid;
+	u16	deviceid;
+	u8	revid;
+	u8	progif_code;
+	u8	subclass_code;
+	u8	baseclass_code;
+	u8	cache_line_size;
+	u16	subsys_vendor_id;
+	u16	subsys_id;
+	enum pci_interrupt_pin interrupt_pin;
+};
+
+/* PCI endpoint operations */
+struct pci_ep_ops {
+	/**
+	 * write_header() - Write a PCI configuration space header
+	 *
+	 * @dev:	device to write to
+	 * @func_num:	EP function to fill
+	 * @hdr:	header to write
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*write_header)(struct udevice *dev, uint func_num,
+				struct pci_ep_header *hdr);
+	/**
+	 * read_header() - Read a PCI configuration space header
+	 *
+	 * @dev:	device to write to
+	 * @func_num:	EP function to fill
+	 * @hdr:	header to read to
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*read_header)(struct udevice *dev, uint func_num,
+			       struct pci_ep_header *hdr);
+	/**
+	 * set_bar() - Set BAR (Base Address Register) properties
+	 *
+	 * @dev:	device to set
+	 * @func_num:	EP function to set
+	 * @bar:	bar data
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*set_bar)(struct udevice *dev, uint func_num,
+			   struct pci_bar *bar);
+	/**
+	 * read_bar() - Read BAR (Base Address Register) properties
+	 *
+	 * @dev:	device to read
+	 * @func_num:	EP function to read
+	 * @bar:	struct to copy data to
+	 * @barno:	bar number to read
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*read_bar)(struct udevice *dev, uint func_num,
+			    struct pci_bar *bar, enum pci_barno barno);
+	/**
+	 * clear_bar() - clear BAR (Base Address Register)
+	 *
+	 * @dev:	device to clear
+	 * @func_num:	EP function to clear
+	 * @bar:	bar number
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*clear_bar)(struct udevice *dev, uint func_num,
+			     enum pci_barno bar);
+	/**
+	 * map_addr() - map CPU address to PCI address
+	 *
+	 * outband region is used in order to generate PCI read/write
+	 * transaction from local memory/write.
+	 *
+	 * @dev:	device to set
+	 * @func_num:	EP function to set
+	 * @addr:	local physical address base
+	 * @pci_addr:	pci address to translate to
+	 * @size:	region size
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*map_addr)(struct udevice *dev, uint func_num,
+			    phys_addr_t addr, u64 pci_addr, size_t size);
+	/**
+	 * unmap_addr() - unmap CPU address to PCI address
+	 *
+	 * unmap previously mapped region.
+	 *
+	 * @dev:	device to set
+	 * @func_num:	EP function to set
+	 * @addr:	local physical address base
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*unmap_addr)(struct udevice *dev, uint func_num,
+			      phys_addr_t addr);
+	/**
+	 * set_msi() - set msi capability property
+	 *
+	 * set the number of required MSI vectors the device
+	 * needs for operation.
+	 *
+	 * @dev:	device to set
+	 * @func_num:	EP function to set
+	 * @interrupts:	required interrupts count
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*set_msi)(struct udevice *dev, uint func_num, uint interrupts);
+
+	/**
+	 * get_msi() - get the number of MSI interrupts allocated by the host.
+	 *
+	 * Read the Multiple Message Enable bitfield from
+	 * Message control register.
+	 *
+	 * @dev:	device to use
+	 * @func_num:	EP function to use
+	 * @return msi count if OK, -EINVAL if msi were not enabled at host.
+	 */
+	int	(*get_msi)(struct udevice *dev, uint func_num);
+
+	/**
+	 * set_msix() - set msix capability property
+	 *
+	 * set the number of required MSIx vectors the device
+	 * needs for operation.
+	 *
+	 * @dev:	device to set
+	 * @func_num:	EP function to set
+	 * @interrupts:	required interrupts count
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*set_msix)(struct udevice *dev, uint func_num,
+			    uint interrupts);
+
+	/**
+	 * get_msix() - get the number of MSIx interrupts allocated by the host.
+	 *
+	 * Read the Multiple Message Enable bitfield from
+	 * Message control register.
+	 *
+	 * @dev:	device to use
+	 * @func_num:	EP function to use
+	 * @return msi count if OK, -EINVAL if msi were not enabled at host.
+	 */
+	int	(*get_msix)(struct udevice *dev, uint func_num);
+
+	/**
+	 * raise_irq() - raise a legacy, MSI or MSI-X interrupt
+	 *
+	 * @dev:	device to set
+	 * @func_num:	EP function to set
+	 * @type:	type of irq to send
+	 * @interrupt_num: interrupt vector to use
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*raise_irq)(struct udevice *dev, uint func_num,
+			     enum pci_ep_irq_type type, uint interrupt_num);
+	/**
+	 * start() - start the PCI link
+	 *
+	 * @dev:	device to set
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*start)(struct udevice *dev);
+
+	/**
+	 * stop() - stop the PCI link
+	 *
+	 * @dev:	device to set
+	 * @return 0 if OK, -ve on error
+	 */
+	int	(*stop)(struct udevice *dev);
+};
+
+#define pci_ep_get_ops(dev)	((struct pci_ep_ops *)(dev)->driver->ops)
+
+/**
+ * pci_ep_write_header() - Write a PCI configuration space header
+ *
+ * @dev:	device to write to
+ * @func_num:	EP function to fill
+ * @hdr:	header to write
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_write_header(struct udevice *dev, uint func_num,
+			struct pci_ep_header *hdr);
+
+/**
+ * dm_pci_ep_read_header() - Read a PCI configuration space header
+ *
+ * @dev:	device to write to
+ * @func_num:	EP function to fill
+ * @hdr:	header to read to
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_read_header(struct udevice *dev, uint func_num,
+		       struct pci_ep_header *hdr);
+/**
+ * pci_ep_set_bar() - Set BAR (Base Address Register) properties
+ *
+ * @dev:	device to set
+ * @func_num:	EP function to set
+ * @bar:	bar data
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_set_bar(struct udevice *dev, uint func_num, struct pci_bar *bar);
+
+/**
+ * pci_ep_read_bar() - Read BAR (Base Address Register) properties
+ *
+ * @dev:	device to read
+ * @func_num:	EP function to read
+ * @bar:	struct to copy data to
+ * @barno:	bar number to read
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
+		    enum pci_barno barno);
+
+/**
+ * pci_ep_clear_bar() - Clear BAR (Base Address Register)
+ *			mark the BAR as empty so host won't map it.
+ * @dev:	device to clear
+ * @func_num:	EP function to clear
+ * @bar:	bar number
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar);
+/**
+ * pci_ep_map_addr() - map CPU address to PCI address
+ *
+ * outband region is used in order to generate PCI read/write
+ * transaction from local memory/write.
+ *
+ * @dev:	device to set
+ * @func_num:	EP function to set
+ * @addr:	local physical address base
+ * @pci_addr:	pci address to translate to
+ * @size:	region size
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_map_addr(struct udevice *dev, uint func_num, phys_addr_t addr,
+		    u64 pci_addr, size_t size);
+/**
+ * pci_ep_unmap_addr() - unmap CPU address to PCI address
+ *
+ * unmap previously mapped region.
+ *
+ * @dev:	device to set
+ * @func_num:	EP function to set
+ * @addr:	local physical address base
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_unmap_addr(struct udevice *dev, uint func_num, phys_addr_t addr);
+
+/**
+ * pci_ep_set_msi() - set msi capability property
+ *
+ * set the number of required MSI vectors the device
+ * needs for operation.
+ *
+ * @dev:	device to set
+ * @func_num:	EP function to set
+ * @interrupts:	required interrupts count
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_set_msi(struct udevice *dev, uint func_num, uint interrupts);
+
+/**
+ * pci_ep_get_msi() - get the number of MSI interrupts allocated by the host.
+ *
+ * Read the Multiple Message Enable bitfield from
+ * Message control register.
+ *
+ * @dev:	device to use
+ * @func_num:	EP function to use
+ * @return msi count if OK, -EINVAL if msi were not enabled at host.
+ */
+int pci_ep_get_msi(struct udevice *dev, uint func_num);
+
+/**
+ * pci_ep_set_msix() - set msi capability property
+ *
+ * set the number of required MSIx vectors the device
+ * needs for operation.
+ *
+ * @dev:	device to set
+ * @func_num:	EP function to set
+ * @interrupts:	required interrupts count
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_set_msix(struct udevice *dev, uint func_num, uint interrupts);
+
+/**
+ * pci_ep_get_msix() - get the number of MSIx interrupts allocated by the host.
+ *
+ * Read the Multiple Message Enable bitfield from
+ * Message control register.
+ *
+ * @dev:	device to use
+ * @func_num:	EP function to use
+ * @return msi count if OK, -EINVAL if msi were not enabled at host.
+ */
+int pci_ep_get_msix(struct udevice *dev, uint func_num);
+
+/**
+ * pci_ep_raise_irq() - raise a legacy, MSI or MSI-X interrupt
+ *
+ * @dev:	device to set
+ * @func_num:	EP function to set
+ * @type:	type of irq to send
+ * @interrupt_num: interrupt vector to use
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_raise_irq(struct udevice *dev, uint func_num,
+		     enum pci_ep_irq_type type, uint interrupt_num);
+/**
+ * pci_ep_start() - start the PCI link
+ *
+ * Enable PCI endpoint device and start link
+ * process.
+ *
+ * @dev:	device to set
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_start(struct udevice *dev);
+
+/**
+ * pci_ep_stop() - stop the PCI link
+ *
+ * Disable PCI endpoint device and stop
+ * link.
+ *
+ * @dev:	device to set
+ * @return 0 if OK, -ve on error
+ */
+int pci_ep_stop(struct udevice *dev);
+
+#endif
diff --git a/include/pci_gt64120.h b/include/pci_gt64120.h
new file mode 100644
index 0000000..c9fb9fa
--- /dev/null
+++ b/include/pci_gt64120.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ */
+
+#ifndef _PCI_GT64120_H
+#define _PCI_GT64120_H
+
+void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
+		     unsigned long sys_size, unsigned long mem_bus,
+		     unsigned long mem_phys, unsigned long mem_size,
+		     unsigned long io_bus, unsigned long io_phys,
+		     unsigned long io_size);
+
+
+#endif /* _PCI_GT64120_H */
diff --git a/include/pci_ids.h b/include/pci_ids.h
new file mode 100644
index 0000000..bd59578
--- /dev/null
+++ b/include/pci_ids.h
@@ -0,0 +1,3136 @@
+/*
+ *	PCI Class, Vendor and Device IDs
+ *
+ *	Please keep sorted.
+ *
+ *	Do not add new entries to this file unless the definitions
+ *	are shared between multiple drivers.
+ */
+
+/* Device classes and subclasses */
+
+#define PCI_CLASS_NOT_DEFINED		0x0000
+#define PCI_CLASS_NOT_DEFINED_VGA	0x0001
+
+#define PCI_BASE_CLASS_STORAGE		0x01
+#define PCI_CLASS_STORAGE_SCSI		0x0100
+#define PCI_CLASS_STORAGE_IDE		0x0101
+#define PCI_CLASS_STORAGE_FLOPPY	0x0102
+#define PCI_CLASS_STORAGE_IPI		0x0103
+#define PCI_CLASS_STORAGE_RAID		0x0104
+#define PCI_CLASS_STORAGE_SATA		0x0106
+#define PCI_CLASS_STORAGE_SATA_AHCI	0x010601
+#define PCI_CLASS_STORAGE_SAS		0x0107
+#define PCI_CLASS_STORAGE_EXPRESS	0x010802
+#define PCI_CLASS_STORAGE_OTHER		0x0180
+
+#define PCI_BASE_CLASS_NETWORK		0x02
+#define PCI_CLASS_NETWORK_ETHERNET	0x0200
+#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
+#define PCI_CLASS_NETWORK_FDDI		0x0202
+#define PCI_CLASS_NETWORK_ATM		0x0203
+#define PCI_CLASS_NETWORK_OTHER		0x0280
+
+#define PCI_BASE_CLASS_DISPLAY		0x03
+#define PCI_CLASS_DISPLAY_VGA		0x0300
+#define PCI_CLASS_DISPLAY_XGA		0x0301
+#define PCI_CLASS_DISPLAY_3D		0x0302
+#define PCI_CLASS_DISPLAY_OTHER		0x0380
+
+#define PCI_BASE_CLASS_MULTIMEDIA	0x04
+#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
+#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
+#define PCI_CLASS_MULTIMEDIA_PHONE	0x0402
+#define PCI_CLASS_MULTIMEDIA_HD_AUDIO	0x0403
+#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480
+
+#define PCI_BASE_CLASS_MEMORY		0x05
+#define PCI_CLASS_MEMORY_RAM		0x0500
+#define PCI_CLASS_MEMORY_FLASH		0x0501
+#define PCI_CLASS_MEMORY_OTHER		0x0580
+
+#define PCI_BASE_CLASS_BRIDGE		0x06
+#define PCI_CLASS_BRIDGE_HOST		0x0600
+#define PCI_CLASS_BRIDGE_ISA		0x0601
+#define PCI_CLASS_BRIDGE_EISA		0x0602
+#define PCI_CLASS_BRIDGE_MC		0x0603
+#define PCI_CLASS_BRIDGE_PCI		0x0604
+#define PCI_CLASS_BRIDGE_PCMCIA		0x0605
+#define PCI_CLASS_BRIDGE_NUBUS		0x0606
+#define PCI_CLASS_BRIDGE_CARDBUS	0x0607
+#define PCI_CLASS_BRIDGE_RACEWAY	0x0608
+#define PCI_CLASS_BRIDGE_OTHER		0x0680
+
+#define PCI_BASE_CLASS_COMMUNICATION	0x07
+#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
+#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
+#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
+#define PCI_CLASS_COMMUNICATION_MODEM	0x0703
+#define PCI_CLASS_COMMUNICATION_OTHER	0x0780
+
+#define PCI_BASE_CLASS_SYSTEM		0x08
+#define PCI_CLASS_SYSTEM_PIC		0x0800
+#define PCI_CLASS_SYSTEM_PIC_IOAPIC	0x080010
+#define PCI_CLASS_SYSTEM_PIC_IOXAPIC	0x080020
+#define PCI_CLASS_SYSTEM_DMA		0x0801
+#define PCI_CLASS_SYSTEM_TIMER		0x0802
+#define PCI_CLASS_SYSTEM_RTC		0x0803
+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804
+#define PCI_CLASS_SYSTEM_SDHCI		0x0805
+#define PCI_CLASS_SYSTEM_OTHER		0x0880
+
+#define PCI_BASE_CLASS_INPUT		0x09
+#define PCI_CLASS_INPUT_KEYBOARD	0x0900
+#define PCI_CLASS_INPUT_PEN		0x0901
+#define PCI_CLASS_INPUT_MOUSE		0x0902
+#define PCI_CLASS_INPUT_SCANNER		0x0903
+#define PCI_CLASS_INPUT_GAMEPORT	0x0904
+#define PCI_CLASS_INPUT_OTHER		0x0980
+
+#define PCI_BASE_CLASS_DOCKING		0x0a
+#define PCI_CLASS_DOCKING_GENERIC	0x0a00
+#define PCI_CLASS_DOCKING_OTHER		0x0a80
+
+#define PCI_BASE_CLASS_PROCESSOR	0x0b
+#define PCI_CLASS_PROCESSOR_386		0x0b00
+#define PCI_CLASS_PROCESSOR_486		0x0b01
+#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
+#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
+#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
+#define PCI_CLASS_PROCESSOR_MIPS	0x0b30
+#define PCI_CLASS_PROCESSOR_CO		0x0b40
+
+#define PCI_BASE_CLASS_SERIAL		0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
+#define PCI_CLASS_SERIAL_FIREWIRE_OHCI	0x0c0010
+#define PCI_CLASS_SERIAL_ACCESS		0x0c01
+#define PCI_CLASS_SERIAL_SSA		0x0c02
+#define PCI_CLASS_SERIAL_USB		0x0c03
+#define PCI_CLASS_SERIAL_USB_UHCI	0x0c0300
+#define PCI_CLASS_SERIAL_USB_OHCI	0x0c0310
+#define PCI_CLASS_SERIAL_USB_EHCI	0x0c0320
+#define PCI_CLASS_SERIAL_USB_XHCI	0x0c0330
+#define PCI_CLASS_SERIAL_FIBER		0x0c04
+#define PCI_CLASS_SERIAL_SMBUS		0x0c05
+
+#define PCI_BASE_CLASS_WIRELESS			0x0d
+#define PCI_CLASS_WIRELESS_RF_CONTROLLER	0x0d10
+#define PCI_CLASS_WIRELESS_WHCI			0x0d1010
+
+#define PCI_BASE_CLASS_INTELLIGENT	0x0e
+#define PCI_CLASS_INTELLIGENT_I2O	0x0e00
+
+#define PCI_BASE_CLASS_SATELLITE	0x0f
+#define PCI_CLASS_SATELLITE_TV		0x0f00
+#define PCI_CLASS_SATELLITE_AUDIO	0x0f01
+#define PCI_CLASS_SATELLITE_VOICE	0x0f03
+#define PCI_CLASS_SATELLITE_DATA	0x0f04
+
+#define PCI_BASE_CLASS_CRYPT		0x10
+#define PCI_CLASS_CRYPT_NETWORK		0x1000
+#define PCI_CLASS_CRYPT_ENTERTAINMENT	0x1001
+#define PCI_CLASS_CRYPT_OTHER		0x1080
+
+#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
+#define PCI_CLASS_SP_DPIO		0x1100
+#define PCI_CLASS_SP_OTHER		0x1180
+
+#define PCI_CLASS_OTHERS		0xff
+
+/* Vendors and devices.  Sort key: vendor first, device next. */
+
+#define PCI_VENDOR_ID_TTTECH		0x0357
+#define PCI_DEVICE_ID_TTTECH_MC322	0x000a
+
+#define PCI_VENDOR_ID_DYNALINK		0x0675
+#define PCI_DEVICE_ID_DYNALINK_IS64PH	0x1702
+
+#define PCI_VENDOR_ID_BERKOM			0x0871
+#define PCI_DEVICE_ID_BERKOM_A1T		0xffa1
+#define PCI_DEVICE_ID_BERKOM_T_CONCEPT		0xffa2
+#define PCI_DEVICE_ID_BERKOM_A4T		0xffa4
+#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO	0xffa8
+
+#define PCI_VENDOR_ID_COMPAQ		0x0e11
+#define PCI_DEVICE_ID_COMPAQ_TOKENRING	0x0508
+#define PCI_DEVICE_ID_COMPAQ_TACHYON	0xa0fc
+#define PCI_DEVICE_ID_COMPAQ_SMART2P	0xae10
+#define PCI_DEVICE_ID_COMPAQ_NETEL100	0xae32
+#define PCI_DEVICE_ID_COMPAQ_NETEL10	0xae34
+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I	0xae35
+#define PCI_DEVICE_ID_COMPAQ_NETEL100D	0xae40
+#define PCI_DEVICE_ID_COMPAQ_NETEL100PI	0xae43
+#define PCI_DEVICE_ID_COMPAQ_NETEL100I	0xb011
+#define PCI_DEVICE_ID_COMPAQ_CISS	0xb060
+#define PCI_DEVICE_ID_COMPAQ_CISSB	0xb178
+#define PCI_DEVICE_ID_COMPAQ_CISSC	0x46
+#define PCI_DEVICE_ID_COMPAQ_THUNDER	0xf130
+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B	0xf150
+
+#define PCI_VENDOR_ID_NCR		0x1000
+#define PCI_VENDOR_ID_LSI_LOGIC		0x1000
+#define PCI_DEVICE_ID_NCR_53C810	0x0001
+#define PCI_DEVICE_ID_NCR_53C820	0x0002
+#define PCI_DEVICE_ID_NCR_53C825	0x0003
+#define PCI_DEVICE_ID_NCR_53C815	0x0004
+#define PCI_DEVICE_ID_LSI_53C810AP	0x0005
+#define PCI_DEVICE_ID_NCR_53C860	0x0006
+#define PCI_DEVICE_ID_LSI_53C1510	0x000a
+#define PCI_DEVICE_ID_NCR_53C896	0x000b
+#define PCI_DEVICE_ID_NCR_53C895	0x000c
+#define PCI_DEVICE_ID_NCR_53C885	0x000d
+#define PCI_DEVICE_ID_NCR_53C875	0x000f
+#define PCI_DEVICE_ID_NCR_53C1510	0x0010
+#define PCI_DEVICE_ID_LSI_53C895A	0x0012
+#define PCI_DEVICE_ID_LSI_53C875A	0x0013
+#define PCI_DEVICE_ID_LSI_53C1010_33	0x0020
+#define PCI_DEVICE_ID_LSI_53C1010_66	0x0021
+#define PCI_DEVICE_ID_LSI_53C1030	0x0030
+#define PCI_DEVICE_ID_LSI_1030_53C1035	0x0032
+#define PCI_DEVICE_ID_LSI_53C1035	0x0040
+#define PCI_DEVICE_ID_NCR_53C875J	0x008f
+#define PCI_DEVICE_ID_LSI_FC909		0x0621
+#define PCI_DEVICE_ID_LSI_FC929		0x0622
+#define PCI_DEVICE_ID_LSI_FC929_LAN	0x0623
+#define PCI_DEVICE_ID_LSI_FC919		0x0624
+#define PCI_DEVICE_ID_LSI_FC919_LAN	0x0625
+#define PCI_DEVICE_ID_LSI_FC929X	0x0626
+#define PCI_DEVICE_ID_LSI_FC939X	0x0642
+#define PCI_DEVICE_ID_LSI_FC949X	0x0640
+#define PCI_DEVICE_ID_LSI_FC949ES	0x0646
+#define PCI_DEVICE_ID_LSI_FC919X	0x0628
+#define PCI_DEVICE_ID_NCR_YELLOWFIN	0x0701
+#define PCI_DEVICE_ID_LSI_61C102	0x0901
+#define PCI_DEVICE_ID_LSI_63C815	0x1000
+#define PCI_DEVICE_ID_LSI_SAS1064	0x0050
+#define PCI_DEVICE_ID_LSI_SAS1064R	0x0411
+#define PCI_DEVICE_ID_LSI_SAS1066	0x005E
+#define PCI_DEVICE_ID_LSI_SAS1068	0x0054
+#define PCI_DEVICE_ID_LSI_SAS1064A	0x005C
+#define PCI_DEVICE_ID_LSI_SAS1064E	0x0056
+#define PCI_DEVICE_ID_LSI_SAS1066E	0x005A
+#define PCI_DEVICE_ID_LSI_SAS1068E	0x0058
+#define PCI_DEVICE_ID_LSI_SAS1078	0x0060
+
+#define PCI_VENDOR_ID_ATI		0x1002
+/* Mach64 */
+#define PCI_DEVICE_ID_ATI_68800		0x4158
+#define PCI_DEVICE_ID_ATI_215CT222	0x4354
+#define PCI_DEVICE_ID_ATI_210888CX	0x4358
+#define PCI_DEVICE_ID_ATI_215ET222	0x4554
+/* Mach64 / Rage */
+#define PCI_DEVICE_ID_ATI_215GB		0x4742
+#define PCI_DEVICE_ID_ATI_215GD		0x4744
+#define PCI_DEVICE_ID_ATI_215GI		0x4749
+#define PCI_DEVICE_ID_ATI_215GP		0x4750
+#define PCI_DEVICE_ID_ATI_215GQ		0x4751
+#define PCI_DEVICE_ID_ATI_215XL		0x4752
+#define PCI_DEVICE_ID_ATI_215GT		0x4754
+#define PCI_DEVICE_ID_ATI_215GTB	0x4755
+#define PCI_DEVICE_ID_ATI_215_IV	0x4756
+#define PCI_DEVICE_ID_ATI_215_IW	0x4757
+#define PCI_DEVICE_ID_ATI_215_IZ	0x475A
+#define PCI_DEVICE_ID_ATI_210888GX	0x4758
+#define PCI_DEVICE_ID_ATI_215_LB	0x4c42
+#define PCI_DEVICE_ID_ATI_215_LD	0x4c44
+#define PCI_DEVICE_ID_ATI_215_LG	0x4c47
+#define PCI_DEVICE_ID_ATI_215_LI	0x4c49
+#define PCI_DEVICE_ID_ATI_215_LM	0x4c4D
+#define PCI_DEVICE_ID_ATI_215_LN	0x4c4E
+#define PCI_DEVICE_ID_ATI_215_LR	0x4c52
+#define PCI_DEVICE_ID_ATI_215_LS	0x4c53
+#define PCI_DEVICE_ID_ATI_264_LT	0x4c54
+/* Mach64 VT */
+#define PCI_DEVICE_ID_ATI_264VT		0x5654
+#define PCI_DEVICE_ID_ATI_264VU		0x5655
+#define PCI_DEVICE_ID_ATI_264VV		0x5656
+/* Rage128 GL */
+#define PCI_DEVICE_ID_ATI_RAGE128_RE	0x5245
+#define PCI_DEVICE_ID_ATI_RAGE128_RF	0x5246
+#define PCI_DEVICE_ID_ATI_RAGE128_RG	0x5247
+/* Rage128 VR */
+#define PCI_DEVICE_ID_ATI_RAGE128_RK	0x524b
+#define PCI_DEVICE_ID_ATI_RAGE128_RL	0x524c
+#define PCI_DEVICE_ID_ATI_RAGE128_SE	0x5345
+#define PCI_DEVICE_ID_ATI_RAGE128_SF	0x5346
+#define PCI_DEVICE_ID_ATI_RAGE128_SG	0x5347
+#define PCI_DEVICE_ID_ATI_RAGE128_SH	0x5348
+#define PCI_DEVICE_ID_ATI_RAGE128_SK	0x534b
+#define PCI_DEVICE_ID_ATI_RAGE128_SL	0x534c
+#define PCI_DEVICE_ID_ATI_RAGE128_SM	0x534d
+#define PCI_DEVICE_ID_ATI_RAGE128_SN	0x534e
+/* Rage128 Ultra */
+#define PCI_DEVICE_ID_ATI_RAGE128_TF	0x5446
+#define PCI_DEVICE_ID_ATI_RAGE128_TL	0x544c
+#define PCI_DEVICE_ID_ATI_RAGE128_TR	0x5452
+#define PCI_DEVICE_ID_ATI_RAGE128_TS	0x5453
+#define PCI_DEVICE_ID_ATI_RAGE128_TT	0x5454
+#define PCI_DEVICE_ID_ATI_RAGE128_TU	0x5455
+/* Rage128 M3 */
+#define PCI_DEVICE_ID_ATI_RAGE128_LE	0x4c45
+#define PCI_DEVICE_ID_ATI_RAGE128_LF	0x4c46
+/* Rage128 M4 */
+#define PCI_DEVICE_ID_ATI_RAGE128_MF    0x4d46
+#define PCI_DEVICE_ID_ATI_RAGE128_ML    0x4d4c
+/* Rage128 Pro GL */
+#define PCI_DEVICE_ID_ATI_RAGE128_PA	0x5041
+#define PCI_DEVICE_ID_ATI_RAGE128_PB	0x5042
+#define PCI_DEVICE_ID_ATI_RAGE128_PC	0x5043
+#define PCI_DEVICE_ID_ATI_RAGE128_PD	0x5044
+#define PCI_DEVICE_ID_ATI_RAGE128_PE	0x5045
+#define PCI_DEVICE_ID_ATI_RAGE128_PF	0x5046
+/* Rage128 Pro VR */
+#define PCI_DEVICE_ID_ATI_RAGE128_PG	0x5047
+#define PCI_DEVICE_ID_ATI_RAGE128_PH	0x5048
+#define PCI_DEVICE_ID_ATI_RAGE128_PI	0x5049
+#define PCI_DEVICE_ID_ATI_RAGE128_PJ	0x504A
+#define PCI_DEVICE_ID_ATI_RAGE128_PK	0x504B
+#define PCI_DEVICE_ID_ATI_RAGE128_PL	0x504C
+#define PCI_DEVICE_ID_ATI_RAGE128_PM	0x504D
+#define PCI_DEVICE_ID_ATI_RAGE128_PN	0x504E
+#define PCI_DEVICE_ID_ATI_RAGE128_PO	0x504F
+#define PCI_DEVICE_ID_ATI_RAGE128_PP	0x5050
+#define PCI_DEVICE_ID_ATI_RAGE128_PQ	0x5051
+#define PCI_DEVICE_ID_ATI_RAGE128_PR	0x5052
+#define PCI_DEVICE_ID_ATI_RAGE128_PS	0x5053
+#define PCI_DEVICE_ID_ATI_RAGE128_PT	0x5054
+#define PCI_DEVICE_ID_ATI_RAGE128_PU	0x5055
+#define PCI_DEVICE_ID_ATI_RAGE128_PV	0x5056
+#define PCI_DEVICE_ID_ATI_RAGE128_PW	0x5057
+#define PCI_DEVICE_ID_ATI_RAGE128_PX	0x5058
+/* Rage128 M4 */
+/* Radeon R100 */
+#define PCI_DEVICE_ID_ATI_RADEON_QD	0x5144
+#define PCI_DEVICE_ID_ATI_RADEON_QE	0x5145
+#define PCI_DEVICE_ID_ATI_RADEON_QF	0x5146
+#define PCI_DEVICE_ID_ATI_RADEON_QG	0x5147
+/* Radeon RV100 (VE) */
+#define PCI_DEVICE_ID_ATI_RADEON_QY	0x5159
+#define PCI_DEVICE_ID_ATI_RADEON_QZ	0x515a
+/* Radeon R200 (8500) */
+#define PCI_DEVICE_ID_ATI_RADEON_QL	0x514c
+#define PCI_DEVICE_ID_ATI_RADEON_QN	0x514e
+#define PCI_DEVICE_ID_ATI_RADEON_QO	0x514f
+#define PCI_DEVICE_ID_ATI_RADEON_Ql	0x516c
+#define PCI_DEVICE_ID_ATI_RADEON_BB	0x4242
+/* Radeon R200 (9100) */
+#define PCI_DEVICE_ID_ATI_RADEON_QM	0x514d
+/* Radeon RV200 (7500) */
+#define PCI_DEVICE_ID_ATI_RADEON_QW	0x5157
+#define PCI_DEVICE_ID_ATI_RADEON_QX	0x5158
+/* Radeon NV-100 */
+/* Radeon RV250 (9000) */
+#define PCI_DEVICE_ID_ATI_RADEON_Id	0x4964
+#define PCI_DEVICE_ID_ATI_RADEON_Ie	0x4965
+#define PCI_DEVICE_ID_ATI_RADEON_If	0x4966
+#define PCI_DEVICE_ID_ATI_RADEON_Ig	0x4967
+/* Radeon RV280 (9200) */
+#define PCI_DEVICE_ID_ATI_RADEON_Ya	0x5961
+#define PCI_DEVICE_ID_ATI_RADEON_Yd	0x5964
+/* Radeon R300 (9500) */
+/* Radeon R300 (9700) */
+#define PCI_DEVICE_ID_ATI_RADEON_ND	0x4e44
+#define PCI_DEVICE_ID_ATI_RADEON_NE	0x4e45
+#define PCI_DEVICE_ID_ATI_RADEON_NF	0x4e46
+#define PCI_DEVICE_ID_ATI_RADEON_NG	0x4e47
+/* Radeon R350 (9800) */
+/* Radeon RV350 (9600) */
+/* Radeon M6 */
+#define PCI_DEVICE_ID_ATI_RADEON_LY	0x4c59
+#define PCI_DEVICE_ID_ATI_RADEON_LZ	0x4c5a
+/* Radeon M7 */
+#define PCI_DEVICE_ID_ATI_RADEON_LW	0x4c57
+#define PCI_DEVICE_ID_ATI_RADEON_LX	0x4c58
+/* Radeon M9 */
+#define PCI_DEVICE_ID_ATI_RADEON_Ld	0x4c64
+#define PCI_DEVICE_ID_ATI_RADEON_Le	0x4c65
+#define PCI_DEVICE_ID_ATI_RADEON_Lf	0x4c66
+#define PCI_DEVICE_ID_ATI_RADEON_Lg	0x4c67
+/* Radeon */
+/* RadeonIGP */
+#define PCI_DEVICE_ID_ATI_RS100		0xcab0
+#define PCI_DEVICE_ID_ATI_RS200		0xcab2
+#define PCI_DEVICE_ID_ATI_RS200_B	0xcbb2
+#define PCI_DEVICE_ID_ATI_RS250		0xcab3
+#define PCI_DEVICE_ID_ATI_RS300_100	0x5830
+#define PCI_DEVICE_ID_ATI_RS300_133	0x5831
+#define PCI_DEVICE_ID_ATI_RS300_166	0x5832
+#define PCI_DEVICE_ID_ATI_RS300_200	0x5833
+#define PCI_DEVICE_ID_ATI_RS350_100     0x7830
+#define PCI_DEVICE_ID_ATI_RS350_133     0x7831
+#define PCI_DEVICE_ID_ATI_RS350_166     0x7832
+#define PCI_DEVICE_ID_ATI_RS350_200     0x7833
+#define PCI_DEVICE_ID_ATI_RS400_100     0x5a30
+#define PCI_DEVICE_ID_ATI_RS400_133     0x5a31
+#define PCI_DEVICE_ID_ATI_RS400_166     0x5a32
+#define PCI_DEVICE_ID_ATI_RS400_200     0x5a33
+#define PCI_DEVICE_ID_ATI_RS480         0x5950
+/* additional Radeon families */
+#define PCI_DEVICE_ID_ATI_EVERGREEN     0x9802
+#define PCI_DEVICE_ID_ATI_EVERGREEN2    0x9804
+#define PCI_DEVICE_ID_ATI_WRESTLER      0x9806
+/* ATI IXP Chipset */
+#define PCI_DEVICE_ID_ATI_IXP200_IDE	0x4349
+#define PCI_DEVICE_ID_ATI_IXP200_SMBUS	0x4353
+#define PCI_DEVICE_ID_ATI_IXP300_SMBUS	0x4363
+#define PCI_DEVICE_ID_ATI_IXP300_IDE	0x4369
+#define PCI_DEVICE_ID_ATI_IXP300_SATA   0x436e
+#define PCI_DEVICE_ID_ATI_IXP400_SMBUS	0x4372
+#define PCI_DEVICE_ID_ATI_IXP400_IDE	0x4376
+#define PCI_DEVICE_ID_ATI_IXP400_SATA   0x4379
+#define PCI_DEVICE_ID_ATI_IXP400_SATA2	0x437a
+#define PCI_DEVICE_ID_ATI_IXP600_SATA	0x4380
+#define PCI_DEVICE_ID_ATI_SBX00_PCI_BRIDGE	0x4384
+#define PCI_DEVICE_ID_ATI_SBX00_SMBUS	0x4385
+#define PCI_DEVICE_ID_ATI_IXP600_IDE	0x438c
+#define PCI_DEVICE_ID_ATI_IXP700_SATA	0x4390
+#define PCI_DEVICE_ID_ATI_SBX00_SATA_AHCI	0x4391
+#define PCI_DEVICE_ID_ATI_SBX00_EHCI	0x4396
+#define PCI_DEVICE_ID_ATI_SBX00_OHCI	0x4397
+#define PCI_DEVICE_ID_ATI_IXP700_IDE	0x439c
+
+#define PCI_VENDOR_ID_VLSI		0x1004
+#define PCI_DEVICE_ID_VLSI_82C592	0x0005
+#define PCI_DEVICE_ID_VLSI_82C593	0x0006
+#define PCI_DEVICE_ID_VLSI_82C594	0x0007
+#define PCI_DEVICE_ID_VLSI_82C597	0x0009
+#define PCI_DEVICE_ID_VLSI_82C541	0x000c
+#define PCI_DEVICE_ID_VLSI_82C543	0x000d
+#define PCI_DEVICE_ID_VLSI_82C532	0x0101
+#define PCI_DEVICE_ID_VLSI_82C534	0x0102
+#define PCI_DEVICE_ID_VLSI_82C535	0x0104
+#define PCI_DEVICE_ID_VLSI_82C147	0x0105
+#define PCI_DEVICE_ID_VLSI_VAS96011	0x0702
+
+/* AMD RD890 Chipset */
+#define PCI_DEVICE_ID_RD890_IOMMU	0x5a23
+
+#define PCI_VENDOR_ID_ADL		0x1005
+#define PCI_DEVICE_ID_ADL_2301		0x2301
+
+#define PCI_VENDOR_ID_NS		0x100b
+#define PCI_DEVICE_ID_NS_87415		0x0002
+#define PCI_DEVICE_ID_NS_87560_LIO	0x000e
+#define PCI_DEVICE_ID_NS_87560_USB	0x0012
+#define PCI_DEVICE_ID_NS_83815		0x0020
+#define PCI_DEVICE_ID_NS_83820		0x0022
+#define PCI_DEVICE_ID_NS_CS5535_ISA	0x002b
+#define PCI_DEVICE_ID_NS_CS5535_IDE	0x002d
+#define PCI_DEVICE_ID_NS_CS5535_AUDIO	0x002e
+#define PCI_DEVICE_ID_NS_CS5535_USB	0x002f
+#define PCI_DEVICE_ID_NS_GX_VIDEO	0x0030
+#define PCI_DEVICE_ID_NS_SATURN		0x0035
+#define PCI_DEVICE_ID_NS_SCx200_BRIDGE	0x0500
+#define PCI_DEVICE_ID_NS_SCx200_SMI	0x0501
+#define PCI_DEVICE_ID_NS_SCx200_IDE	0x0502
+#define PCI_DEVICE_ID_NS_SCx200_AUDIO	0x0503
+#define PCI_DEVICE_ID_NS_SCx200_VIDEO	0x0504
+#define PCI_DEVICE_ID_NS_SCx200_XBUS	0x0505
+#define PCI_DEVICE_ID_NS_SC1100_BRIDGE	0x0510
+#define PCI_DEVICE_ID_NS_SC1100_SMI	0x0511
+#define PCI_DEVICE_ID_NS_SC1100_XBUS	0x0515
+#define PCI_DEVICE_ID_NS_87410		0xd001
+
+#define PCI_DEVICE_ID_NS_GX_HOST_BRIDGE  0x0028
+
+#define PCI_VENDOR_ID_TSENG		0x100c
+#define PCI_DEVICE_ID_TSENG_W32P_2	0x3202
+#define PCI_DEVICE_ID_TSENG_W32P_b	0x3205
+#define PCI_DEVICE_ID_TSENG_W32P_c	0x3206
+#define PCI_DEVICE_ID_TSENG_W32P_d	0x3207
+#define PCI_DEVICE_ID_TSENG_ET6000	0x3208
+
+#define PCI_VENDOR_ID_WEITEK		0x100e
+#define PCI_DEVICE_ID_WEITEK_P9000	0x9001
+#define PCI_DEVICE_ID_WEITEK_P9100	0x9100
+
+#define PCI_VENDOR_ID_DEC		0x1011
+#define PCI_DEVICE_ID_DEC_BRD		0x0001
+#define PCI_DEVICE_ID_DEC_TULIP		0x0002
+#define PCI_DEVICE_ID_DEC_TGA		0x0004
+#define PCI_DEVICE_ID_DEC_TULIP_FAST	0x0009
+#define PCI_DEVICE_ID_DEC_TGA2		0x000D
+#define PCI_DEVICE_ID_DEC_FDDI		0x000F
+#define PCI_DEVICE_ID_DEC_TULIP_PLUS	0x0014
+#define PCI_DEVICE_ID_DEC_21142		0x0019
+#define PCI_DEVICE_ID_DEC_21052		0x0021
+#define PCI_DEVICE_ID_DEC_21150		0x0022
+#define PCI_DEVICE_ID_DEC_21152		0x0024
+#define PCI_DEVICE_ID_DEC_21153		0x0025
+#define PCI_DEVICE_ID_DEC_21154		0x0026
+#define PCI_DEVICE_ID_DEC_21285		0x1065
+#define PCI_DEVICE_ID_COMPAQ_42XX	0x0046
+
+#define PCI_VENDOR_ID_CIRRUS		0x1013
+#define PCI_DEVICE_ID_CIRRUS_7548	0x0038
+#define PCI_DEVICE_ID_CIRRUS_5430	0x00a0
+#define PCI_DEVICE_ID_CIRRUS_5434_4	0x00a4
+#define PCI_DEVICE_ID_CIRRUS_5434_8	0x00a8
+#define PCI_DEVICE_ID_CIRRUS_5436	0x00ac
+#define PCI_DEVICE_ID_CIRRUS_5446	0x00b8
+#define PCI_DEVICE_ID_CIRRUS_5480	0x00bc
+#define PCI_DEVICE_ID_CIRRUS_5462	0x00d0
+#define PCI_DEVICE_ID_CIRRUS_5464	0x00d4
+#define PCI_DEVICE_ID_CIRRUS_5465	0x00d6
+#define PCI_DEVICE_ID_CIRRUS_6729	0x1100
+#define PCI_DEVICE_ID_CIRRUS_6832	0x1110
+#define PCI_DEVICE_ID_CIRRUS_7543	0x1202
+#define PCI_DEVICE_ID_CIRRUS_4610	0x6001
+#define PCI_DEVICE_ID_CIRRUS_4612	0x6003
+#define PCI_DEVICE_ID_CIRRUS_4615	0x6004
+
+#define PCI_VENDOR_ID_IBM		0x1014
+#define PCI_DEVICE_ID_IBM_TR		0x0018
+#define PCI_DEVICE_ID_IBM_TR_WAKE	0x003e
+#define PCI_DEVICE_ID_IBM_CPC710_PCI64	0x00fc
+#define PCI_DEVICE_ID_IBM_405GP		0x0156
+#define PCI_DEVICE_ID_IBM_SNIPE		0x0180
+#define PCI_DEVICE_ID_IBM_CITRINE		0x028C
+#define PCI_DEVICE_ID_IBM_GEMSTONE		0xB166
+#define PCI_DEVICE_ID_IBM_OBSIDIAN		0x02BD
+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1	0x0031
+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2	0x0219
+#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX		0x021A
+#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM	0x0251
+#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361
+#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL	0x252
+
+#define PCI_SUBVENDOR_ID_IBM		0x1014
+#define PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT	0x03d4
+
+#define PCI_VENDOR_ID_UNISYS		0x1018
+#define PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR 0x001C
+
+#define PCI_VENDOR_ID_COMPEX2		0x101a /* pci.ids says "AT&T GIS (NCR)" */
+#define PCI_DEVICE_ID_COMPEX2_100VG	0x0005
+
+#define PCI_VENDOR_ID_WD		0x101c
+#define PCI_DEVICE_ID_WD_90C		0xc24a
+
+#define PCI_VENDOR_ID_AMI		0x101e
+#define PCI_DEVICE_ID_AMI_MEGARAID3	0x1960
+#define PCI_DEVICE_ID_AMI_MEGARAID	0x9010
+#define PCI_DEVICE_ID_AMI_MEGARAID2	0x9060
+
+#define PCI_VENDOR_ID_AMD		0x1022
+#define PCI_DEVICE_ID_AMD_K8_NB		0x1100
+#define PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP	0x1101
+#define PCI_DEVICE_ID_AMD_K8_NB_MEMCTL	0x1102
+#define PCI_DEVICE_ID_AMD_K8_NB_MISC	0x1103
+#define PCI_DEVICE_ID_AMD_10H_NB_HT	0x1200
+#define PCI_DEVICE_ID_AMD_10H_NB_MAP	0x1201
+#define PCI_DEVICE_ID_AMD_10H_NB_DRAM	0x1202
+#define PCI_DEVICE_ID_AMD_10H_NB_MISC	0x1203
+#define PCI_DEVICE_ID_AMD_10H_NB_LINK	0x1204
+#define PCI_DEVICE_ID_AMD_11H_NB_HT	0x1300
+#define PCI_DEVICE_ID_AMD_11H_NB_MAP	0x1301
+#define PCI_DEVICE_ID_AMD_11H_NB_DRAM	0x1302
+#define PCI_DEVICE_ID_AMD_11H_NB_MISC	0x1303
+#define PCI_DEVICE_ID_AMD_11H_NB_LINK	0x1304
+#define PCI_DEVICE_ID_AMD_15H_M10H_F3	0x1403
+#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F3 0x141d
+#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F4 0x141e
+#define PCI_DEVICE_ID_AMD_15H_NB_F0	0x1600
+#define PCI_DEVICE_ID_AMD_15H_NB_F1	0x1601
+#define PCI_DEVICE_ID_AMD_15H_NB_F2	0x1602
+#define PCI_DEVICE_ID_AMD_15H_NB_F3	0x1603
+#define PCI_DEVICE_ID_AMD_15H_NB_F4	0x1604
+#define PCI_DEVICE_ID_AMD_15H_NB_F5	0x1605
+#define PCI_DEVICE_ID_AMD_16H_NB_F3	0x1533
+#define PCI_DEVICE_ID_AMD_16H_NB_F4	0x1534
+#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 0x1583
+#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F4 0x1584
+#define PCI_DEVICE_ID_AMD_CNB17H_F3	0x1703
+#define PCI_DEVICE_ID_AMD_LANCE		0x2000
+#define PCI_DEVICE_ID_AMD_LANCE_HOME	0x2001
+#define PCI_DEVICE_ID_AMD_SCSI		0x2020
+#define PCI_DEVICE_ID_AMD_SERENADE	0x36c0
+#define PCI_DEVICE_ID_AMD_FE_GATE_7006	0x7006
+#define PCI_DEVICE_ID_AMD_FE_GATE_7007	0x7007
+#define PCI_DEVICE_ID_AMD_FE_GATE_700C	0x700C
+#define PCI_DEVICE_ID_AMD_FE_GATE_700E	0x700E
+#define PCI_DEVICE_ID_AMD_COBRA_7401	0x7401
+#define PCI_DEVICE_ID_AMD_VIPER_7409	0x7409
+#define PCI_DEVICE_ID_AMD_VIPER_740B	0x740B
+#define PCI_DEVICE_ID_AMD_VIPER_7410	0x7410
+#define PCI_DEVICE_ID_AMD_VIPER_7411	0x7411
+#define PCI_DEVICE_ID_AMD_VIPER_7413	0x7413
+#define PCI_DEVICE_ID_AMD_VIPER_7440	0x7440
+#define PCI_DEVICE_ID_AMD_OPUS_7441	0x7441
+#define PCI_DEVICE_ID_AMD_OPUS_7443	0x7443
+#define PCI_DEVICE_ID_AMD_VIPER_7443	0x7443
+#define PCI_DEVICE_ID_AMD_OPUS_7445	0x7445
+#define PCI_DEVICE_ID_AMD_8111_PCI	0x7460
+#define PCI_DEVICE_ID_AMD_8111_LPC	0x7468
+#define PCI_DEVICE_ID_AMD_8111_IDE	0x7469
+#define PCI_DEVICE_ID_AMD_8111_SMBUS2	0x746a
+#define PCI_DEVICE_ID_AMD_8111_SMBUS	0x746b
+#define PCI_DEVICE_ID_AMD_8111_AUDIO	0x746d
+#define PCI_DEVICE_ID_AMD_8151_0	0x7454
+#define PCI_DEVICE_ID_AMD_8131_BRIDGE	0x7450
+#define PCI_DEVICE_ID_AMD_8131_APIC	0x7451
+#define PCI_DEVICE_ID_AMD_8132_BRIDGE	0x7458
+#define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS	0x780b
+#define PCI_DEVICE_ID_AMD_CS5535_IDE    0x208F
+#define PCI_DEVICE_ID_AMD_CS5536_ISA    0x2090
+#define PCI_DEVICE_ID_AMD_CS5536_FLASH  0x2091
+#define PCI_DEVICE_ID_AMD_CS5536_AUDIO  0x2093
+#define PCI_DEVICE_ID_AMD_CS5536_OHC    0x2094
+#define PCI_DEVICE_ID_AMD_CS5536_EHC    0x2095
+#define PCI_DEVICE_ID_AMD_CS5536_UDC    0x2096
+#define PCI_DEVICE_ID_AMD_CS5536_UOC    0x2097
+#define PCI_DEVICE_ID_AMD_CS5536_IDE    0x209A
+#define PCI_DEVICE_ID_AMD_LX_VIDEO  0x2081
+#define PCI_DEVICE_ID_AMD_LX_AES    0x2082
+#define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE	0x7800
+#define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS		0x780b
+#define PCI_DEVICE_ID_AMD_HUDSON2_IDE		0x780c
+
+#define PCI_VENDOR_ID_TRIDENT		0x1023
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX	0x2001
+#define PCI_DEVICE_ID_TRIDENT_9320	0x9320
+#define PCI_DEVICE_ID_TRIDENT_9388	0x9388
+#define PCI_DEVICE_ID_TRIDENT_9397	0x9397
+#define PCI_DEVICE_ID_TRIDENT_939A	0x939A
+#define PCI_DEVICE_ID_TRIDENT_9520	0x9520
+#define PCI_DEVICE_ID_TRIDENT_9525	0x9525
+#define PCI_DEVICE_ID_TRIDENT_9420	0x9420
+#define PCI_DEVICE_ID_TRIDENT_9440	0x9440
+#define PCI_DEVICE_ID_TRIDENT_9660	0x9660
+#define PCI_DEVICE_ID_TRIDENT_9750	0x9750
+#define PCI_DEVICE_ID_TRIDENT_9850	0x9850
+#define PCI_DEVICE_ID_TRIDENT_9880	0x9880
+#define PCI_DEVICE_ID_TRIDENT_8400	0x8400
+#define PCI_DEVICE_ID_TRIDENT_8420	0x8420
+#define PCI_DEVICE_ID_TRIDENT_8500	0x8500
+
+#define PCI_VENDOR_ID_AI		0x1025
+#define PCI_DEVICE_ID_AI_M1435		0x1435
+
+#define PCI_VENDOR_ID_DELL		0x1028
+#define PCI_DEVICE_ID_DELL_RACIII	0x0008
+#define PCI_DEVICE_ID_DELL_RAC4		0x0012
+#define PCI_DEVICE_ID_DELL_PERC5	0x0015
+
+#define PCI_VENDOR_ID_MATROX		0x102B
+#define PCI_DEVICE_ID_MATROX_MGA_2	0x0518
+#define PCI_DEVICE_ID_MATROX_MIL	0x0519
+#define PCI_DEVICE_ID_MATROX_MYS	0x051A
+#define PCI_DEVICE_ID_MATROX_MIL_2	0x051b
+#define PCI_DEVICE_ID_MATROX_MYS_AGP	0x051e
+#define PCI_DEVICE_ID_MATROX_MIL_2_AGP	0x051f
+#define PCI_DEVICE_ID_MATROX_MGA_IMP	0x0d10
+#define PCI_DEVICE_ID_MATROX_G100_MM	0x1000
+#define PCI_DEVICE_ID_MATROX_G100_AGP	0x1001
+#define PCI_DEVICE_ID_MATROX_G200_PCI	0x0520
+#define PCI_DEVICE_ID_MATROX_G200_AGP	0x0521
+#define	PCI_DEVICE_ID_MATROX_G400	0x0525
+#define	PCI_DEVICE_ID_MATROX_G200EV_PCI	0x0530
+#define PCI_DEVICE_ID_MATROX_G550	0x2527
+#define PCI_DEVICE_ID_MATROX_VIA	0x4536
+
+#define PCI_VENDOR_ID_MOBILITY_ELECTRONICS	0x14f2
+
+#define PCI_VENDOR_ID_CT		0x102c
+#define PCI_DEVICE_ID_CT_69000		0x00c0
+#define PCI_DEVICE_ID_CT_65545		0x00d8
+#define PCI_DEVICE_ID_CT_65548		0x00dc
+#define PCI_DEVICE_ID_CT_65550		0x00e0
+#define PCI_DEVICE_ID_CT_65554		0x00e4
+#define PCI_DEVICE_ID_CT_65555		0x00e5
+#define PCI_DEVICE_ID_CT_69030		0x0c30
+
+#define PCI_VENDOR_ID_MIRO		0x1031
+#define PCI_DEVICE_ID_MIRO_36050	0x5601
+#define PCI_DEVICE_ID_MIRO_DC10PLUS	0x7efe
+#define PCI_DEVICE_ID_MIRO_DC30PLUS	0xd801
+
+#define PCI_VENDOR_ID_NEC		0x1033
+#define PCI_DEVICE_ID_NEC_CBUS_1	0x0001 /* PCI-Cbus Bridge */
+#define PCI_DEVICE_ID_NEC_LOCAL		0x0002 /* Local Bridge */
+#define PCI_DEVICE_ID_NEC_ATM		0x0003 /* ATM LAN Controller */
+#define PCI_DEVICE_ID_NEC_R4000		0x0004 /* R4000 Bridge */
+#define PCI_DEVICE_ID_NEC_486		0x0005 /* 486 Like Peripheral Bus Bridge */
+#define PCI_DEVICE_ID_NEC_ACCEL_1	0x0006 /* Graphic Accelerator */
+#define PCI_DEVICE_ID_NEC_UXBUS		0x0007 /* UX-Bus Bridge */
+#define PCI_DEVICE_ID_NEC_ACCEL_2	0x0008 /* Graphic Accelerator */
+#define PCI_DEVICE_ID_NEC_GRAPH		0x0009 /* PCI-CoreGraph Bridge */
+#define PCI_DEVICE_ID_NEC_VL		0x0016 /* PCI-VL Bridge */
+#define PCI_DEVICE_ID_NEC_STARALPHA2	0x002c /* STAR ALPHA2 */
+#define PCI_DEVICE_ID_NEC_CBUS_2	0x002d /* PCI-Cbus Bridge */
+#define PCI_DEVICE_ID_NEC_USB		0x0035 /* PCI-USB Host */
+#define PCI_DEVICE_ID_NEC_CBUS_3	0x003b
+#define PCI_DEVICE_ID_NEC_NAPCCARD	0x003e
+#define PCI_DEVICE_ID_NEC_PCX2		0x0046 /* PowerVR */
+#define PCI_DEVICE_ID_NEC_VRC5476       0x009b
+#define PCI_DEVICE_ID_NEC_VRC4173	0x00a5
+#define PCI_DEVICE_ID_NEC_VRC5477_AC97  0x00a6
+#define PCI_DEVICE_ID_NEC_PC9821CS01    0x800c /* PC-9821-CS01 */
+#define PCI_DEVICE_ID_NEC_PC9821NRB06   0x800d /* PC-9821NR-B06 */
+
+#define PCI_VENDOR_ID_FD		0x1036
+#define PCI_DEVICE_ID_FD_36C70		0x0000
+
+#define PCI_VENDOR_ID_SI		0x1039
+#define PCI_DEVICE_ID_SI_5591_AGP	0x0001
+#define PCI_DEVICE_ID_SI_6202		0x0002
+#define PCI_DEVICE_ID_SI_503		0x0008
+#define PCI_DEVICE_ID_SI_ACPI		0x0009
+#define PCI_DEVICE_ID_SI_SMBUS		0x0016
+#define PCI_DEVICE_ID_SI_LPC		0x0018
+#define PCI_DEVICE_ID_SI_5597_VGA	0x0200
+#define PCI_DEVICE_ID_SI_6205		0x0205
+#define PCI_DEVICE_ID_SI_501		0x0406
+#define PCI_DEVICE_ID_SI_496		0x0496
+#define PCI_DEVICE_ID_SI_300		0x0300
+#define PCI_DEVICE_ID_SI_315H		0x0310
+#define PCI_DEVICE_ID_SI_315		0x0315
+#define PCI_DEVICE_ID_SI_315PRO		0x0325
+#define PCI_DEVICE_ID_SI_530		0x0530
+#define PCI_DEVICE_ID_SI_540		0x0540
+#define PCI_DEVICE_ID_SI_550		0x0550
+#define PCI_DEVICE_ID_SI_540_VGA	0x5300
+#define PCI_DEVICE_ID_SI_550_VGA	0x5315
+#define PCI_DEVICE_ID_SI_620		0x0620
+#define PCI_DEVICE_ID_SI_630		0x0630
+#define PCI_DEVICE_ID_SI_633		0x0633
+#define PCI_DEVICE_ID_SI_635		0x0635
+#define PCI_DEVICE_ID_SI_640		0x0640
+#define PCI_DEVICE_ID_SI_645		0x0645
+#define PCI_DEVICE_ID_SI_646		0x0646
+#define PCI_DEVICE_ID_SI_648		0x0648
+#define PCI_DEVICE_ID_SI_650		0x0650
+#define PCI_DEVICE_ID_SI_651		0x0651
+#define PCI_DEVICE_ID_SI_655		0x0655
+#define PCI_DEVICE_ID_SI_661		0x0661
+#define PCI_DEVICE_ID_SI_730		0x0730
+#define PCI_DEVICE_ID_SI_733		0x0733
+#define PCI_DEVICE_ID_SI_630_VGA	0x6300
+#define PCI_DEVICE_ID_SI_735		0x0735
+#define PCI_DEVICE_ID_SI_740		0x0740
+#define PCI_DEVICE_ID_SI_741		0x0741
+#define PCI_DEVICE_ID_SI_745		0x0745
+#define PCI_DEVICE_ID_SI_746		0x0746
+#define PCI_DEVICE_ID_SI_755		0x0755
+#define PCI_DEVICE_ID_SI_760		0x0760
+#define PCI_DEVICE_ID_SI_900		0x0900
+#define PCI_DEVICE_ID_SI_961		0x0961
+#define PCI_DEVICE_ID_SI_962		0x0962
+#define PCI_DEVICE_ID_SI_963		0x0963
+#define PCI_DEVICE_ID_SI_965		0x0965
+#define PCI_DEVICE_ID_SI_966		0x0966
+#define PCI_DEVICE_ID_SI_968		0x0968
+#define PCI_DEVICE_ID_SI_1180		0x1180
+#define PCI_DEVICE_ID_SI_5511		0x5511
+#define PCI_DEVICE_ID_SI_5513		0x5513
+#define PCI_DEVICE_ID_SI_5517		0x5517
+#define PCI_DEVICE_ID_SI_5518		0x5518
+#define PCI_DEVICE_ID_SI_5571		0x5571
+#define PCI_DEVICE_ID_SI_5581		0x5581
+#define PCI_DEVICE_ID_SI_5582		0x5582
+#define PCI_DEVICE_ID_SI_5591		0x5591
+#define PCI_DEVICE_ID_SI_5596		0x5596
+#define PCI_DEVICE_ID_SI_5597		0x5597
+#define PCI_DEVICE_ID_SI_5598		0x5598
+#define PCI_DEVICE_ID_SI_5600		0x5600
+#define PCI_DEVICE_ID_SI_7012		0x7012
+#define PCI_DEVICE_ID_SI_7013		0x7013
+#define PCI_DEVICE_ID_SI_7016		0x7016
+#define PCI_DEVICE_ID_SI_7018		0x7018
+
+#define PCI_VENDOR_ID_HP		0x103c
+#define PCI_VENDOR_ID_HP_3PAR		0x1590
+#define PCI_DEVICE_ID_HP_VISUALIZE_EG	0x1005
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX6	0x1006
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX4	0x1008
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX2	0x100a
+#define PCI_DEVICE_ID_HP_TACHYON	0x1028
+#define PCI_DEVICE_ID_HP_TACHLITE	0x1029
+#define PCI_DEVICE_ID_HP_J2585A		0x1030
+#define PCI_DEVICE_ID_HP_J2585B		0x1031
+#define PCI_DEVICE_ID_HP_J2973A		0x1040
+#define PCI_DEVICE_ID_HP_J2970A		0x1042
+#define PCI_DEVICE_ID_HP_DIVA		0x1048
+#define PCI_DEVICE_ID_HP_DIVA_TOSCA1	0x1049
+#define PCI_DEVICE_ID_HP_DIVA_TOSCA2	0x104A
+#define PCI_DEVICE_ID_HP_DIVA_MAESTRO	0x104B
+#define PCI_DEVICE_ID_HP_REO_IOC	0x10f1
+#define PCI_DEVICE_ID_HP_VISUALIZE_FXE	0x108b
+#define PCI_DEVICE_ID_HP_DIVA_HALFDOME	0x1223
+#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE	0x1226
+#define PCI_DEVICE_ID_HP_DIVA_POWERBAR	0x1227
+#define PCI_DEVICE_ID_HP_ZX1_IOC	0x122a
+#define PCI_DEVICE_ID_HP_PCIX_LBA	0x122e
+#define PCI_DEVICE_ID_HP_SX1000_IOC	0x127c
+#define PCI_DEVICE_ID_HP_DIVA_EVEREST	0x1282
+#define PCI_DEVICE_ID_HP_DIVA_AUX	0x1290
+#define PCI_DEVICE_ID_HP_DIVA_RMP3	0x1301
+#define PCI_DEVICE_ID_HP_DIVA_HURRICANE	0x132a
+#define PCI_DEVICE_ID_HP_CISSA		0x3220
+#define PCI_DEVICE_ID_HP_CISSC		0x3230
+#define PCI_DEVICE_ID_HP_CISSD		0x3238
+#define PCI_DEVICE_ID_HP_CISSE		0x323a
+#define PCI_DEVICE_ID_HP_CISSF		0x323b
+#define PCI_DEVICE_ID_HP_CISSH		0x323c
+#define PCI_DEVICE_ID_HP_CISSI		0x3239
+#define PCI_DEVICE_ID_HP_ZX2_IOC	0x4031
+
+#define PCI_VENDOR_ID_PCTECH		0x1042
+#define PCI_DEVICE_ID_PCTECH_RZ1000	0x1000
+#define PCI_DEVICE_ID_PCTECH_RZ1001	0x1001
+#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
+
+#define PCI_VENDOR_ID_ASUSTEK		0x1043
+#define PCI_DEVICE_ID_ASUSTEK_0675	0x0675
+
+#define PCI_VENDOR_ID_DPT		0x1044
+#define PCI_DEVICE_ID_DPT		0xa400
+
+#define PCI_VENDOR_ID_OPTI		0x1045
+#define PCI_DEVICE_ID_OPTI_82C558	0xc558
+#define PCI_DEVICE_ID_OPTI_82C621	0xc621
+#define PCI_DEVICE_ID_OPTI_82C700	0xc700
+#define PCI_DEVICE_ID_OPTI_82C825	0xd568
+
+#define PCI_VENDOR_ID_ELSA		0x1048
+#define PCI_DEVICE_ID_ELSA_MICROLINK	0x1000
+#define PCI_DEVICE_ID_ELSA_QS3000	0x3000
+
+#define PCI_VENDOR_ID_STMICRO		0x104A
+#define PCI_DEVICE_ID_STMICRO_USB_HOST	0xCC00
+#define PCI_DEVICE_ID_STMICRO_USB_OHCI	0xCC01
+#define PCI_DEVICE_ID_STMICRO_USB_OTG	0xCC02
+#define PCI_DEVICE_ID_STMICRO_UART_HWFC 0xCC03
+#define PCI_DEVICE_ID_STMICRO_UART_NO_HWFC	0xCC04
+#define PCI_DEVICE_ID_STMICRO_SOC_DMA	0xCC05
+#define PCI_DEVICE_ID_STMICRO_SATA	0xCC06
+#define PCI_DEVICE_ID_STMICRO_I2C	0xCC07
+#define PCI_DEVICE_ID_STMICRO_SPI_HS	0xCC08
+#define PCI_DEVICE_ID_STMICRO_MAC	0xCC09
+#define PCI_DEVICE_ID_STMICRO_SDIO_EMMC 0xCC0A
+#define PCI_DEVICE_ID_STMICRO_SDIO	0xCC0B
+#define PCI_DEVICE_ID_STMICRO_GPIO	0xCC0C
+#define PCI_DEVICE_ID_STMICRO_VIP	0xCC0D
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_DMA	0xCC0E
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_SRCS 0xCC0F
+#define PCI_DEVICE_ID_STMICRO_AUDIO_ROUTER_MSPS 0xCC10
+#define PCI_DEVICE_ID_STMICRO_CAN	0xCC11
+#define PCI_DEVICE_ID_STMICRO_MLB	0xCC12
+#define PCI_DEVICE_ID_STMICRO_DBP	0xCC13
+#define PCI_DEVICE_ID_STMICRO_SATA_PHY	0xCC14
+#define PCI_DEVICE_ID_STMICRO_ESRAM	0xCC15
+#define PCI_DEVICE_ID_STMICRO_VIC	0xCC16
+
+#define PCI_VENDOR_ID_BUSLOGIC		      0x104B
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER    0x1040
+#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT     0x8130
+
+#define PCI_VENDOR_ID_TI		0x104c
+#define PCI_DEVICE_ID_TI_TVP4020	0x3d07
+#define PCI_DEVICE_ID_TI_4450		0x8011
+#define PCI_DEVICE_ID_TI_XX21_XX11	0x8031
+#define PCI_DEVICE_ID_TI_XX21_XX11_FM	0x8033
+#define PCI_DEVICE_ID_TI_XX21_XX11_SD	0x8034
+#define PCI_DEVICE_ID_TI_X515		0x8036
+#define PCI_DEVICE_ID_TI_XX12		0x8039
+#define PCI_DEVICE_ID_TI_XX12_FM	0x803b
+#define PCI_DEVICE_ID_TI_XIO2000A	0x8231
+#define PCI_DEVICE_ID_TI_1130		0xac12
+#define PCI_DEVICE_ID_TI_1031		0xac13
+#define PCI_DEVICE_ID_TI_1131		0xac15
+#define PCI_DEVICE_ID_TI_1250		0xac16
+#define PCI_DEVICE_ID_TI_1220		0xac17
+#define PCI_DEVICE_ID_TI_1221		0xac19
+#define PCI_DEVICE_ID_TI_1210		0xac1a
+#define PCI_DEVICE_ID_TI_1450		0xac1b
+#define PCI_DEVICE_ID_TI_1225		0xac1c
+#define PCI_DEVICE_ID_TI_1251A		0xac1d
+#define PCI_DEVICE_ID_TI_1211		0xac1e
+#define PCI_DEVICE_ID_TI_1251B		0xac1f
+#define PCI_DEVICE_ID_TI_4410		0xac41
+#define PCI_DEVICE_ID_TI_4451		0xac42
+#define PCI_DEVICE_ID_TI_4510		0xac44
+#define PCI_DEVICE_ID_TI_4520		0xac46
+#define PCI_DEVICE_ID_TI_7510		0xac47
+#define PCI_DEVICE_ID_TI_7610		0xac48
+#define PCI_DEVICE_ID_TI_7410		0xac49
+#define PCI_DEVICE_ID_TI_1410		0xac50
+#define PCI_DEVICE_ID_TI_1420		0xac51
+#define PCI_DEVICE_ID_TI_1451A		0xac52
+#define PCI_DEVICE_ID_TI_1620		0xac54
+#define PCI_DEVICE_ID_TI_1520		0xac55
+#define PCI_DEVICE_ID_TI_1510		0xac56
+#define PCI_DEVICE_ID_TI_X620		0xac8d
+#define PCI_DEVICE_ID_TI_X420		0xac8e
+#define PCI_DEVICE_ID_TI_XX20_FM	0xac8f
+
+#define PCI_VENDOR_ID_SONY		0x104d
+
+/* Winbond have two vendor IDs! See 0x10ad as well */
+#define PCI_VENDOR_ID_WINBOND2		0x1050
+#define PCI_DEVICE_ID_WINBOND2_89C940F	0x5a5a
+#define PCI_DEVICE_ID_WINBOND2_6692	0x6692
+
+#define PCI_VENDOR_ID_ANIGMA		0x1051
+#define PCI_DEVICE_ID_ANIGMA_MC145575	0x0100
+
+#define PCI_VENDOR_ID_EFAR		0x1055
+#define PCI_DEVICE_ID_EFAR_SLC90E66_1	0x9130
+#define PCI_DEVICE_ID_EFAR_SLC90E66_3	0x9463
+
+#define PCI_VENDOR_ID_MOTOROLA		0x1057
+#define PCI_DEVICE_ID_MOTOROLA_MPC105	0x0001
+#define PCI_DEVICE_ID_MOTOROLA_MPC106	0x0002
+#define PCI_DEVICE_ID_MOTOROLA_MPC107	0x0004
+#define PCI_DEVICE_ID_MOTOROLA_RAVEN	0x4801
+#define PCI_DEVICE_ID_MOTOROLA_FALCON	0x4802
+#define PCI_DEVICE_ID_MOTOROLA_HAWK	0x4803
+#define PCI_DEVICE_ID_MOTOROLA_HARRIER	0x480b
+#define PCI_DEVICE_ID_MOTOROLA_MPC5200	0x5803
+#define PCI_DEVICE_ID_MOTOROLA_MPC5200B	0x5809
+
+#define PCI_VENDOR_ID_PROMISE		0x105a
+#define PCI_DEVICE_ID_PROMISE_20265	0x0d30
+#define PCI_DEVICE_ID_PROMISE_20267	0x4d30
+#define PCI_DEVICE_ID_PROMISE_20246	0x4d33
+#define PCI_DEVICE_ID_PROMISE_20262	0x4d38
+#define PCI_DEVICE_ID_PROMISE_20263	0x0D38
+#define PCI_DEVICE_ID_PROMISE_20268	0x4d68
+#define PCI_DEVICE_ID_PROMISE_20269	0x4d69
+#define PCI_DEVICE_ID_PROMISE_20270	0x6268
+#define PCI_DEVICE_ID_PROMISE_20271	0x6269
+#define PCI_DEVICE_ID_PROMISE_20275	0x1275
+#define PCI_DEVICE_ID_PROMISE_20276	0x5275
+#define PCI_DEVICE_ID_PROMISE_20277	0x7275
+
+#define PCI_VENDOR_ID_FOXCONN		0x105b
+
+#define PCI_VENDOR_ID_UMC		0x1060
+#define PCI_DEVICE_ID_UMC_UM8673F	0x0101
+#define PCI_DEVICE_ID_UMC_UM8886BF	0x673a
+#define PCI_DEVICE_ID_UMC_UM8886A	0x886a
+
+#define PCI_VENDOR_ID_PICOPOWER		0x1066
+#define PCI_DEVICE_ID_PICOPOWER_PT86C523	0x0002
+#define PCI_DEVICE_ID_PICOPOWER_PT86C523BBP	0x8002
+
+#define PCI_VENDOR_ID_MYLEX		0x1069
+#define PCI_DEVICE_ID_MYLEX_DAC960_P	0x0001
+#define PCI_DEVICE_ID_MYLEX_DAC960_PD	0x0002
+#define PCI_DEVICE_ID_MYLEX_DAC960_PG	0x0010
+#define PCI_DEVICE_ID_MYLEX_DAC960_LA	0x0020
+#define PCI_DEVICE_ID_MYLEX_DAC960_LP	0x0050
+#define PCI_DEVICE_ID_MYLEX_DAC960_BA	0xBA56
+#define PCI_DEVICE_ID_MYLEX_DAC960_GEM	0xB166
+
+#define PCI_VENDOR_ID_APPLE		0x106b
+#define PCI_DEVICE_ID_APPLE_BANDIT	0x0001
+#define PCI_DEVICE_ID_APPLE_HYDRA	0x000e
+#define PCI_DEVICE_ID_APPLE_UNI_N_FW	0x0018
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP	0x0020
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC	0x0021
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP	0x0024
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P	0x0027
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15	0x002d
+#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15	0x002e
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2	0x0032
+#define PCI_DEVICE_ID_APPLE_UNI_N_ATA	0x0033
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2	0x0034
+#define PCI_DEVICE_ID_APPLE_IPID_ATA100	0x003b
+#define PCI_DEVICE_ID_APPLE_K2_ATA100	0x0043
+#define PCI_DEVICE_ID_APPLE_U3_AGP	0x004b
+#define PCI_DEVICE_ID_APPLE_K2_GMAC	0x004c
+#define PCI_DEVICE_ID_APPLE_SH_ATA      0x0050
+#define PCI_DEVICE_ID_APPLE_SH_SUNGEM   0x0051
+#define PCI_DEVICE_ID_APPLE_U3L_AGP	0x0058
+#define PCI_DEVICE_ID_APPLE_U3H_AGP	0x0059
+#define PCI_DEVICE_ID_APPLE_U4_PCIE	0x005b
+#define PCI_DEVICE_ID_APPLE_IPID2_AGP	0x0066
+#define PCI_DEVICE_ID_APPLE_IPID2_ATA	0x0069
+#define PCI_DEVICE_ID_APPLE_IPID2_FW	0x006a
+#define PCI_DEVICE_ID_APPLE_IPID2_GMAC	0x006b
+#define PCI_DEVICE_ID_APPLE_TIGON3	0x1645
+
+#define PCI_VENDOR_ID_YAMAHA		0x1073
+#define PCI_DEVICE_ID_YAMAHA_724	0x0004
+#define PCI_DEVICE_ID_YAMAHA_724F	0x000d
+#define PCI_DEVICE_ID_YAMAHA_740	0x000a
+#define PCI_DEVICE_ID_YAMAHA_740C	0x000c
+#define PCI_DEVICE_ID_YAMAHA_744	0x0010
+#define PCI_DEVICE_ID_YAMAHA_754	0x0012
+
+#define PCI_VENDOR_ID_QLOGIC		0x1077
+#define PCI_DEVICE_ID_QLOGIC_ISP10160	0x1016
+#define PCI_DEVICE_ID_QLOGIC_ISP1020	0x1020
+#define PCI_DEVICE_ID_QLOGIC_ISP1080	0x1080
+#define PCI_DEVICE_ID_QLOGIC_ISP12160	0x1216
+#define PCI_DEVICE_ID_QLOGIC_ISP1240	0x1240
+#define PCI_DEVICE_ID_QLOGIC_ISP1280	0x1280
+#define PCI_DEVICE_ID_QLOGIC_ISP2100	0x2100
+#define PCI_DEVICE_ID_QLOGIC_ISP2200	0x2200
+#define PCI_DEVICE_ID_QLOGIC_ISP2300	0x2300
+#define PCI_DEVICE_ID_QLOGIC_ISP2312	0x2312
+#define PCI_DEVICE_ID_QLOGIC_ISP2322	0x2322
+#define PCI_DEVICE_ID_QLOGIC_ISP6312	0x6312
+#define PCI_DEVICE_ID_QLOGIC_ISP6322	0x6322
+#define PCI_DEVICE_ID_QLOGIC_ISP2422	0x2422
+#define PCI_DEVICE_ID_QLOGIC_ISP2432	0x2432
+#define PCI_DEVICE_ID_QLOGIC_ISP2512	0x2512
+#define PCI_DEVICE_ID_QLOGIC_ISP2522	0x2522
+#define PCI_DEVICE_ID_QLOGIC_ISP5422	0x5422
+#define PCI_DEVICE_ID_QLOGIC_ISP5432	0x5432
+
+#define PCI_VENDOR_ID_CYRIX		0x1078
+#define PCI_DEVICE_ID_CYRIX_5510	0x0000
+#define PCI_DEVICE_ID_CYRIX_PCI_MASTER	0x0001
+#define PCI_DEVICE_ID_CYRIX_5520	0x0002
+#define PCI_DEVICE_ID_CYRIX_5530_LEGACY	0x0100
+#define PCI_DEVICE_ID_CYRIX_5530_IDE	0x0102
+#define PCI_DEVICE_ID_CYRIX_5530_AUDIO	0x0103
+#define PCI_DEVICE_ID_CYRIX_5530_VIDEO	0x0104
+
+#define PCI_VENDOR_ID_CONTAQ		0x1080
+#define PCI_DEVICE_ID_CONTAQ_82C693	0xc693
+
+#define PCI_VENDOR_ID_OLICOM		0x108d
+#define PCI_DEVICE_ID_OLICOM_OC2325	0x0012
+#define PCI_DEVICE_ID_OLICOM_OC2183	0x0013
+#define PCI_DEVICE_ID_OLICOM_OC2326	0x0014
+
+#define PCI_VENDOR_ID_SUN		0x108e
+#define PCI_DEVICE_ID_SUN_EBUS		0x1000
+#define PCI_DEVICE_ID_SUN_HAPPYMEAL	0x1001
+#define PCI_DEVICE_ID_SUN_RIO_EBUS	0x1100
+#define PCI_DEVICE_ID_SUN_RIO_GEM	0x1101
+#define PCI_DEVICE_ID_SUN_RIO_1394	0x1102
+#define PCI_DEVICE_ID_SUN_RIO_USB	0x1103
+#define PCI_DEVICE_ID_SUN_GEM		0x2bad
+#define PCI_DEVICE_ID_SUN_SIMBA		0x5000
+#define PCI_DEVICE_ID_SUN_PBM		0x8000
+#define PCI_DEVICE_ID_SUN_SCHIZO	0x8001
+#define PCI_DEVICE_ID_SUN_SABRE		0xa000
+#define PCI_DEVICE_ID_SUN_HUMMINGBIRD	0xa001
+#define PCI_DEVICE_ID_SUN_TOMATILLO	0xa801
+#define PCI_DEVICE_ID_SUN_CASSINI	0xabba
+
+#define PCI_VENDOR_ID_NI		0x1093
+#define PCI_DEVICE_ID_NI_PCI2322	0xd130
+#define PCI_DEVICE_ID_NI_PCI2324	0xd140
+#define PCI_DEVICE_ID_NI_PCI2328	0xd150
+#define PCI_DEVICE_ID_NI_PXI8422_2322	0xd190
+#define PCI_DEVICE_ID_NI_PXI8422_2324	0xd1a0
+#define PCI_DEVICE_ID_NI_PXI8420_2322	0xd1d0
+#define PCI_DEVICE_ID_NI_PXI8420_2324	0xd1e0
+#define PCI_DEVICE_ID_NI_PXI8420_2328	0xd1f0
+#define PCI_DEVICE_ID_NI_PXI8420_23216	0xd1f1
+#define PCI_DEVICE_ID_NI_PCI2322I	0xd250
+#define PCI_DEVICE_ID_NI_PCI2324I	0xd270
+#define PCI_DEVICE_ID_NI_PCI23216	0xd2b0
+#define PCI_DEVICE_ID_NI_PXI8430_2322	0x7080
+#define PCI_DEVICE_ID_NI_PCI8430_2322	0x70db
+#define PCI_DEVICE_ID_NI_PXI8430_2324	0x70dd
+#define PCI_DEVICE_ID_NI_PCI8430_2324	0x70df
+#define PCI_DEVICE_ID_NI_PXI8430_2328	0x70e2
+#define PCI_DEVICE_ID_NI_PCI8430_2328	0x70e4
+#define PCI_DEVICE_ID_NI_PXI8430_23216	0x70e6
+#define PCI_DEVICE_ID_NI_PCI8430_23216	0x70e7
+#define PCI_DEVICE_ID_NI_PXI8432_2322	0x70e8
+#define PCI_DEVICE_ID_NI_PCI8432_2322	0x70ea
+#define PCI_DEVICE_ID_NI_PXI8432_2324	0x70ec
+#define PCI_DEVICE_ID_NI_PCI8432_2324	0x70ee
+
+#define PCI_VENDOR_ID_CMD		0x1095
+#define PCI_DEVICE_ID_CMD_643		0x0643
+#define PCI_DEVICE_ID_CMD_646		0x0646
+#define PCI_DEVICE_ID_CMD_648		0x0648
+#define PCI_DEVICE_ID_CMD_649		0x0649
+
+#define PCI_VENDOR_ID_SILICONIMAGE	0x1095
+#define PCI_DEVICE_ID_SII_1210SA	0x0240
+#define PCI_DEVICE_ID_SII_680		0x0680
+#define PCI_DEVICE_ID_SII_3112		0x3112
+#define PCI_DEVICE_ID_SIL3124		0x3124
+#define PCI_DEVICE_ID_SIL3131		0x3131
+#define PCI_DEVICE_ID_SIL3132		0x3132
+
+#define PCI_VENDOR_ID_BROOKTREE		0x109e
+#define PCI_DEVICE_ID_BROOKTREE_878	0x0878
+#define PCI_DEVICE_ID_BROOKTREE_879	0x0879
+
+#define PCI_VENDOR_ID_SGI		0x10a9
+#define PCI_DEVICE_ID_SGI_IOC3		0x0003
+#define PCI_DEVICE_ID_SGI_LITHIUM	0x1002
+#define PCI_DEVICE_ID_SGI_IOC4		0x100a
+
+#define PCI_VENDOR_ID_WINBOND		0x10ad
+#define PCI_DEVICE_ID_WINBOND_82C105	0x0105
+#define PCI_DEVICE_ID_WINBOND_83C553	0x0565
+
+#define PCI_VENDOR_ID_PLX		0x10b5
+#define PCI_DEVICE_ID_PLX_R685		0x1030
+#define PCI_DEVICE_ID_PLX_ROMULUS	0x106a
+#define PCI_DEVICE_ID_PLX_SPCOM800	0x1076
+#define PCI_DEVICE_ID_PLX_1077		0x1077
+#define PCI_DEVICE_ID_PLX_SPCOM200	0x1103
+#define PCI_DEVICE_ID_PLX_DJINN_ITOO	0x1151
+#define PCI_DEVICE_ID_PLX_R753		0x1152
+#define PCI_DEVICE_ID_PLX_OLITEC	0x1187
+#define PCI_DEVICE_ID_PLX_PCI200SYN	0x3196
+#define PCI_DEVICE_ID_PLX_9030          0x9030
+#define PCI_DEVICE_ID_PLX_9050		0x9050
+#define PCI_DEVICE_ID_PLX_9056		0x9056
+#define PCI_DEVICE_ID_PLX_9080		0x9080
+#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2	0xa001
+
+#define PCI_VENDOR_ID_MADGE		0x10b6
+#define PCI_DEVICE_ID_MADGE_MK2		0x0002
+
+#define PCI_VENDOR_ID_3COM		0x10b7
+#define PCI_DEVICE_ID_3COM_3C985	0x0001
+#define PCI_DEVICE_ID_3COM_3C940	0x1700
+#define PCI_DEVICE_ID_3COM_3C339	0x3390
+#define PCI_DEVICE_ID_3COM_3C359	0x3590
+#define PCI_DEVICE_ID_3COM_3C940B	0x80eb
+#define PCI_DEVICE_ID_3COM_3CR990	0x9900
+#define PCI_DEVICE_ID_3COM_3CR990_TX_95	0x9902
+#define PCI_DEVICE_ID_3COM_3CR990_TX_97	0x9903
+#define PCI_DEVICE_ID_3COM_3CR990B	0x9904
+#define PCI_DEVICE_ID_3COM_3CR990_FX	0x9905
+#define PCI_DEVICE_ID_3COM_3CR990SVR95	0x9908
+#define PCI_DEVICE_ID_3COM_3CR990SVR97	0x9909
+#define PCI_DEVICE_ID_3COM_3CR990SVR	0x990a
+
+#define PCI_VENDOR_ID_AL		0x10b9
+#define PCI_DEVICE_ID_AL_M1533		0x1533
+#define PCI_DEVICE_ID_AL_M1535		0x1535
+#define PCI_DEVICE_ID_AL_M1541		0x1541
+#define PCI_DEVICE_ID_AL_M1563		0x1563
+#define PCI_DEVICE_ID_AL_M1621		0x1621
+#define PCI_DEVICE_ID_AL_M1631		0x1631
+#define PCI_DEVICE_ID_AL_M1632		0x1632
+#define PCI_DEVICE_ID_AL_M1641		0x1641
+#define PCI_DEVICE_ID_AL_M1644		0x1644
+#define PCI_DEVICE_ID_AL_M1647		0x1647
+#define PCI_DEVICE_ID_AL_M1651		0x1651
+#define PCI_DEVICE_ID_AL_M1671		0x1671
+#define PCI_DEVICE_ID_AL_M1681		0x1681
+#define PCI_DEVICE_ID_AL_M1683		0x1683
+#define PCI_DEVICE_ID_AL_M1689		0x1689
+#define PCI_DEVICE_ID_AL_M5219		0x5219
+#define PCI_DEVICE_ID_AL_M5228		0x5228
+#define PCI_DEVICE_ID_AL_M5229		0x5229
+#define PCI_DEVICE_ID_AL_M5451		0x5451
+#define PCI_DEVICE_ID_AL_M7101		0x7101
+
+#define PCI_VENDOR_ID_NEOMAGIC		0x10c8
+#define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005
+#define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006
+#define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016
+
+#define PCI_VENDOR_ID_TCONRAD		0x10da
+#define PCI_DEVICE_ID_TCONRAD_TOKENRING	0x0508
+
+#define PCI_VENDOR_ID_NVIDIA			0x10de
+#define PCI_DEVICE_ID_NVIDIA_TNT		0x0020
+#define PCI_DEVICE_ID_NVIDIA_TNT2		0x0028
+#define PCI_DEVICE_ID_NVIDIA_UTNT2		0x0029
+#define PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN        0x002a
+#define PCI_DEVICE_ID_NVIDIA_VTNT2		0x002C
+#define PCI_DEVICE_ID_NVIDIA_UVTNT2		0x002D
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS	0x0034
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE	0x0035
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA	0x0036
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2	0x003e
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800       0x0041
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE    0x0042
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT    0x0045
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000     0x004E
+#define PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS	0x0052
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE	0x0053
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA	0x0054
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2	0x0055
+#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO	0x0059
+#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE		0x005d
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS	0x0064
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE	0x0065
+#define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM		0x0069
+#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO		0x006a
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS	0x0084
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE	0x0085
+#define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM	0x0089
+#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO		0x008a
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA	0x008e
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT   0x0090
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX	0x0091
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800   0x0098
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX 0x0099
+#define PCI_DEVICE_ID_NVIDIA_ITNT2		0x00A0
+#define PCI_DEVICE_ID_GEFORCE_6800A             0x00c1
+#define PCI_DEVICE_ID_GEFORCE_6800A_LE          0x00c2
+#define PCI_DEVICE_ID_GEFORCE_GO_6800           0x00c8
+#define PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA     0x00c9
+#define PCI_DEVICE_ID_QUADRO_FX_GO1400          0x00cc
+#define PCI_DEVICE_ID_QUADRO_FX_1400            0x00ce
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3		0x00d1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS	0x00d4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE	0x00d5
+#define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM		0x00d9
+#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO		0x00da
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S		0x00e1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA	0x00e3
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS	0x00e4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE	0x00e5
+#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO		0x00ea
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2	0x00ee
+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1 0x00f0
+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1 0x00f1
+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2 0x00f2
+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1 0x00f3
+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT   0x00f9
+#define PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280	0x00fd
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR	0x0100
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR	0x0101
+#define PCI_DEVICE_ID_NVIDIA_QUADRO		0x0103
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX	0x0110
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2	0x0111
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO	0x0112
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR	0x0113
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT	0x0140
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600	0x0141
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL	0x0145
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540	0x014E
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200	0x014F
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS	0x0150
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2	0x0151
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA	0x0152
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO	0x0153
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE 0x0161
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200    0x0164
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250    0x0166
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1  0x0167
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1  0x0168
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460	0x0170
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440	0x0171
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420	0x0172
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE	0x0173
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO	0x0174
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO	0x0175
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO    0x0177
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL	0x0178
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200	0x017A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL	0x017B
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL	0x017C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16 0x017D
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X 0x0181
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X 0x0182
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X 0x0183
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000   0x0185
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO    0x0186
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO    0x0187
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL    0x0188
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC    0x0189
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS    0x018A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL    0x018B
+#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2		0x01a0
+#define PCI_DEVICE_ID_NVIDIA_NFORCE		0x01a4
+#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO		0x01b1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS	0x01b4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE		0x01bc
+#define PCI_DEVICE_ID_NVIDIA_MCP1_MODEM		0x01c1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2		0x01e0
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3		0x0200
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1		0x0201
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2		0x0202
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC		0x0203
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B      0x0211
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE   0x0212
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT   0x0215
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600	0x0250
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400	0x0251
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200	0x0253
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL	0x0258
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL	0x0259
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL	0x025B
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS	0x0264
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE	0x0265
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA	0x0266
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2	0x0267
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS	0x0368
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE	0x036E
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA	0x037E
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2	0x037F
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800	0x0280
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X    0x0281
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE     0x0282
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO       0x0286
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL        0x0288
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL        0x0289
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL       0x028C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA  0x0301
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800        0x0302
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000         0x0308
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000         0x0309
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA  0x0311
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600        0x0312
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE      0x0314
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600      0x031A
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650      0x031B
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700        0x031C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200        0x0320
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA  0x0321
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1      0x0322
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE      0x0323
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200      0x0324
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250      0x0325
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500        0x0326
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100        0x0327
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32   0x0328
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200	    0x0329
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI     0x032A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500          0x032B
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300      0x032C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100      0x032D
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA  0x0330
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900        0x0331
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT      0x0332
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA  0x0333
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT      0x0334
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000         0x0338
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700          0x033F
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA  0x0341
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700        0x0342
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE      0x0343
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE      0x0344
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1    0x0347
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2    0x0348
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000       0x034C
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100         0x034E
+#define PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0	    0x0360
+#define PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4	    0x0364
+#define PCI_DEVICE_ID_NVIDIA_NVENET_15              0x0373
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA      0x03E7
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS	    0x03EB
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE       0x03EC
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2     0x03F6
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3     0x03F7
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS	    0x0446
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE	    0x0448
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS     0x0542
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE       0x0560
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE       0x056C
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS    0x0752
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE       0x0759
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS     0x07D8
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS     0x0AA2
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA	    0x0D85
+
+#define PCI_VENDOR_ID_IMS		0x10e0
+#define PCI_DEVICE_ID_IMS_TT128		0x9128
+#define PCI_DEVICE_ID_IMS_TT3D		0x9135
+
+#define PCI_VENDOR_ID_TUNDRA		0x10e3
+#define PCI_DEVICE_ID_TUNDRA_CA91C042	0x0000
+
+#define PCI_VENDOR_ID_AMCC		0x10e8
+
+#define PCI_VENDOR_ID_INTERG		0x10ea
+#define PCI_DEVICE_ID_INTERG_1682	0x1682
+#define PCI_DEVICE_ID_INTERG_2000	0x2000
+#define PCI_DEVICE_ID_INTERG_2010	0x2010
+#define PCI_DEVICE_ID_INTERG_5000	0x5000
+#define PCI_DEVICE_ID_INTERG_5050	0x5050
+
+#define PCI_VENDOR_ID_REALTEK		0x10ec
+#define PCI_DEVICE_ID_REALTEK_8139	0x8139
+#define PCI_DEVICE_ID_REALTEK_8168	0x8168
+
+#define PCI_VENDOR_ID_XILINX		0x10ee
+#define PCI_DEVICE_ID_RME_DIGI96	0x3fc0
+#define PCI_DEVICE_ID_RME_DIGI96_8	0x3fc1
+#define PCI_DEVICE_ID_RME_DIGI96_8_PRO	0x3fc2
+#define PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST 0x3fc3
+#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
+#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6
+
+#define PCI_VENDOR_ID_INIT		0x1101
+
+#define PCI_VENDOR_ID_CREATIVE		0x1102 /* duplicate: ECTIVA */
+#define PCI_DEVICE_ID_CREATIVE_EMU10K1	0x0002
+#define PCI_DEVICE_ID_CREATIVE_20K1	0x0005
+#define PCI_DEVICE_ID_CREATIVE_20K2	0x000b
+#define PCI_DEVICE_ID_CREATIVE_CA01322	0x0011
+#define PCI_SUBDEVICE_ID_CREATIVE_SB0760	0x0024
+#define PCI_SUBDEVICE_ID_CREATIVE_SB08801	0x0041
+#define PCI_SUBDEVICE_ID_CREATIVE_SB08802	0x0042
+#define PCI_SUBDEVICE_ID_CREATIVE_SB08803	0x0043
+#define PCI_SUBDEVICE_ID_CREATIVE_SB1270	0x0062
+#define PCI_SUBDEVICE_ID_CREATIVE_HENDRIX	0x6000
+
+#define PCI_VENDOR_ID_ECTIVA		0x1102 /* duplicate: CREATIVE */
+#define PCI_DEVICE_ID_ECTIVA_EV1938	0x8938
+
+#define PCI_VENDOR_ID_TTI		0x1103
+#define PCI_DEVICE_ID_TTI_HPT343	0x0003
+#define PCI_DEVICE_ID_TTI_HPT366	0x0004
+#define PCI_DEVICE_ID_TTI_HPT372	0x0005
+#define PCI_DEVICE_ID_TTI_HPT302	0x0006
+#define PCI_DEVICE_ID_TTI_HPT371	0x0007
+#define PCI_DEVICE_ID_TTI_HPT374	0x0008
+#define PCI_DEVICE_ID_TTI_HPT372N	0x0009	/* apparently a 372N variant? */
+
+#define PCI_VENDOR_ID_VIA		0x1106
+#define PCI_DEVICE_ID_VIA_8763_0	0x0198
+#define PCI_DEVICE_ID_VIA_8380_0	0x0204
+#define PCI_DEVICE_ID_VIA_3238_0	0x0238
+#define PCI_DEVICE_ID_VIA_PT880		0x0258
+#define PCI_DEVICE_ID_VIA_PT880ULTRA	0x0308
+#define PCI_DEVICE_ID_VIA_PX8X0_0	0x0259
+#define PCI_DEVICE_ID_VIA_3269_0	0x0269
+#define PCI_DEVICE_ID_VIA_K8T800PRO_0	0x0282
+#define PCI_DEVICE_ID_VIA_3296_0	0x0296
+#define PCI_DEVICE_ID_VIA_8363_0	0x0305
+#define PCI_DEVICE_ID_VIA_P4M800CE	0x0314
+#define PCI_DEVICE_ID_VIA_P4M890	0x0327
+#define PCI_DEVICE_ID_VIA_VT3324	0x0324
+#define PCI_DEVICE_ID_VIA_VT3336	0x0336
+#define PCI_DEVICE_ID_VIA_VT3351	0x0351
+#define PCI_DEVICE_ID_VIA_VT3364	0x0364
+#define PCI_DEVICE_ID_VIA_8371_0	0x0391
+#define PCI_DEVICE_ID_VIA_6415		0x0415
+#define PCI_DEVICE_ID_VIA_8501_0	0x0501
+#define PCI_DEVICE_ID_VIA_82C561	0x0561
+#define PCI_DEVICE_ID_VIA_82C586_1	0x0571
+#define PCI_DEVICE_ID_VIA_82C576	0x0576
+#define PCI_DEVICE_ID_VIA_82C586_0	0x0586
+#define PCI_DEVICE_ID_VIA_82C596	0x0596
+#define PCI_DEVICE_ID_VIA_82C597_0	0x0597
+#define PCI_DEVICE_ID_VIA_82C598_0	0x0598
+#define PCI_DEVICE_ID_VIA_8601_0	0x0601
+#define PCI_DEVICE_ID_VIA_8605_0	0x0605
+#define PCI_DEVICE_ID_VIA_82C686	0x0686
+#define PCI_DEVICE_ID_VIA_82C691_0	0x0691
+#define PCI_DEVICE_ID_VIA_82C576_1	0x1571
+#define PCI_DEVICE_ID_VIA_82C586_2	0x3038
+#define PCI_DEVICE_ID_VIA_82C586_3	0x3040
+#define PCI_DEVICE_ID_VIA_82C596_3	0x3050
+#define PCI_DEVICE_ID_VIA_82C596B_3	0x3051
+#define PCI_DEVICE_ID_VIA_82C686_4	0x3057
+#define PCI_DEVICE_ID_VIA_82C686_5	0x3058
+#define PCI_DEVICE_ID_VIA_8233_5	0x3059
+#define PCI_DEVICE_ID_VIA_8233_0	0x3074
+#define PCI_DEVICE_ID_VIA_8633_0	0x3091
+#define PCI_DEVICE_ID_VIA_8367_0	0x3099
+#define PCI_DEVICE_ID_VIA_8653_0	0x3101
+#define PCI_DEVICE_ID_VIA_8622		0x3102
+#define PCI_DEVICE_ID_VIA_8235_USB_2	0x3104
+#define PCI_DEVICE_ID_VIA_8233C_0	0x3109
+#define PCI_DEVICE_ID_VIA_8361		0x3112
+#define PCI_DEVICE_ID_VIA_XM266		0x3116
+#define PCI_DEVICE_ID_VIA_612X		0x3119
+#define PCI_DEVICE_ID_VIA_862X_0	0x3123
+#define PCI_DEVICE_ID_VIA_8753_0	0x3128
+#define PCI_DEVICE_ID_VIA_8233A		0x3147
+#define PCI_DEVICE_ID_VIA_8703_51_0	0x3148
+#define PCI_DEVICE_ID_VIA_8237_SATA	0x3149
+#define PCI_DEVICE_ID_VIA_XN266		0x3156
+#define PCI_DEVICE_ID_VIA_6410		0x3164
+#define PCI_DEVICE_ID_VIA_8754C_0	0x3168
+#define PCI_DEVICE_ID_VIA_8235		0x3177
+#define PCI_DEVICE_ID_VIA_8385_0	0x3188
+#define PCI_DEVICE_ID_VIA_8377_0	0x3189
+#define PCI_DEVICE_ID_VIA_8378_0	0x3205
+#define PCI_DEVICE_ID_VIA_8783_0	0x3208
+#define PCI_DEVICE_ID_VIA_8237		0x3227
+#define PCI_DEVICE_ID_VIA_8251		0x3287
+#define PCI_DEVICE_ID_VIA_8261		0x3402
+#define PCI_DEVICE_ID_VIA_8237A		0x3337
+#define PCI_DEVICE_ID_VIA_8237S		0x3372
+#define PCI_DEVICE_ID_VIA_SATA_EIDE	0x5324
+#define PCI_DEVICE_ID_VIA_8231		0x8231
+#define PCI_DEVICE_ID_VIA_8231_4	0x8235
+#define PCI_DEVICE_ID_VIA_8365_1	0x8305
+#define PCI_DEVICE_ID_VIA_CX700		0x8324
+#define PCI_DEVICE_ID_VIA_CX700_IDE	0x0581
+#define PCI_DEVICE_ID_VIA_VX800		0x8353
+#define PCI_DEVICE_ID_VIA_VX855		0x8409
+#define PCI_DEVICE_ID_VIA_VX900		0x8410
+#define PCI_DEVICE_ID_VIA_8371_1	0x8391
+#define PCI_DEVICE_ID_VIA_82C598_1	0x8598
+#define PCI_DEVICE_ID_VIA_838X_1	0xB188
+#define PCI_DEVICE_ID_VIA_83_87XX_1	0xB198
+#define PCI_DEVICE_ID_VIA_VX855_IDE	0xC409
+#define PCI_DEVICE_ID_VIA_ANON		0xFFFF
+
+#define PCI_VENDOR_ID_SIEMENS           0x110A
+#define PCI_DEVICE_ID_SIEMENS_DSCC4     0x2102
+
+#define PCI_VENDOR_ID_VORTEX		0x1119
+#define PCI_DEVICE_ID_VORTEX_GDT60x0	0x0000
+#define PCI_DEVICE_ID_VORTEX_GDT6000B	0x0001
+#define PCI_DEVICE_ID_VORTEX_GDT6x10	0x0002
+#define PCI_DEVICE_ID_VORTEX_GDT6x20	0x0003
+#define PCI_DEVICE_ID_VORTEX_GDT6530	0x0004
+#define PCI_DEVICE_ID_VORTEX_GDT6550	0x0005
+#define PCI_DEVICE_ID_VORTEX_GDT6x17	0x0006
+#define PCI_DEVICE_ID_VORTEX_GDT6x27	0x0007
+#define PCI_DEVICE_ID_VORTEX_GDT6537	0x0008
+#define PCI_DEVICE_ID_VORTEX_GDT6557	0x0009
+#define PCI_DEVICE_ID_VORTEX_GDT6x15	0x000a
+#define PCI_DEVICE_ID_VORTEX_GDT6x25	0x000b
+#define PCI_DEVICE_ID_VORTEX_GDT6535	0x000c
+#define PCI_DEVICE_ID_VORTEX_GDT6555	0x000d
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP	0x0100
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP	0x0101
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP	0x0102
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP	0x0103
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP	0x0104
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP	0x0105
+
+#define PCI_VENDOR_ID_EF		0x111a
+#define PCI_DEVICE_ID_EF_ATM_FPGA	0x0000
+#define PCI_DEVICE_ID_EF_ATM_ASIC	0x0002
+#define PCI_DEVICE_ID_EF_ATM_LANAI2	0x0003
+#define PCI_DEVICE_ID_EF_ATM_LANAIHB	0x0005
+
+#define PCI_VENDOR_ID_IDT		0x111d
+#define PCI_DEVICE_ID_IDT_IDT77201	0x0001
+
+#define PCI_VENDOR_ID_FORE		0x1127
+#define PCI_DEVICE_ID_FORE_PCA200E	0x0300
+
+#define PCI_VENDOR_ID_PHILIPS		0x1131
+#define PCI_DEVICE_ID_PHILIPS_SAA7146	0x7146
+#define PCI_DEVICE_ID_PHILIPS_SAA9730	0x9730
+
+#define PCI_VENDOR_ID_EICON		0x1133
+#define PCI_DEVICE_ID_EICON_DIVA20	0xe002
+#define PCI_DEVICE_ID_EICON_DIVA20_U	0xe004
+#define PCI_DEVICE_ID_EICON_DIVA201	0xe005
+#define PCI_DEVICE_ID_EICON_DIVA202	0xe00b
+#define PCI_DEVICE_ID_EICON_MAESTRA	0xe010
+#define PCI_DEVICE_ID_EICON_MAESTRAQ	0xe012
+#define PCI_DEVICE_ID_EICON_MAESTRAQ_U	0xe013
+#define PCI_DEVICE_ID_EICON_MAESTRAP	0xe014
+
+#define PCI_VENDOR_ID_CISCO		0x1137
+
+#define PCI_VENDOR_ID_ZIATECH		0x1138
+#define PCI_DEVICE_ID_ZIATECH_5550_HC	0x5550
+
+
+#define PCI_VENDOR_ID_SYSKONNECT	0x1148
+#define PCI_DEVICE_ID_SYSKONNECT_TR	0x4200
+#define PCI_DEVICE_ID_SYSKONNECT_GE	0x4300
+#define PCI_DEVICE_ID_SYSKONNECT_YU	0x4320
+#define PCI_DEVICE_ID_SYSKONNECT_9DXX	0x4400
+#define PCI_DEVICE_ID_SYSKONNECT_9MXX	0x4500
+
+#define PCI_VENDOR_ID_DIGI		0x114f
+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E	0x0070
+#define PCI_DEVICE_ID_DIGI_DF_M_E	0x0071
+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A	0x0072
+#define PCI_DEVICE_ID_DIGI_DF_M_A	0x0073
+#define PCI_DEVICE_ID_DIGI_NEO_8	0x00B1
+#define PCI_DEVICE_ID_NEO_2DB9          0x00C8
+#define PCI_DEVICE_ID_NEO_2DB9PRI       0x00C9
+#define PCI_DEVICE_ID_NEO_2RJ45         0x00CA
+#define PCI_DEVICE_ID_NEO_2RJ45PRI      0x00CB
+#define PCIE_DEVICE_ID_NEO_4_IBM        0x00F4
+
+#define PCI_VENDOR_ID_XIRCOM		0x115d
+#define PCI_DEVICE_ID_XIRCOM_RBM56G	0x0101
+#define PCI_DEVICE_ID_XIRCOM_X3201_MDM	0x0103
+
+#define PCI_VENDOR_ID_SERVERWORKS	  0x1166
+#define PCI_DEVICE_ID_SERVERWORKS_HE	  0x0008
+#define PCI_DEVICE_ID_SERVERWORKS_LE	  0x0009
+#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
+#define PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB	0x0036
+#define PCI_DEVICE_ID_SERVERWORKS_EPB	  0x0103
+#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE	0x0132
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4	  0x0200
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5	  0x0201
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6    0x0203
+#define PCI_DEVICE_ID_SERVERWORKS_HT1000SB 0x0205
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
+#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
+#define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
+
+#define PCI_VENDOR_ID_SBE		0x1176
+#define PCI_DEVICE_ID_SBE_WANXL100	0x0301
+#define PCI_DEVICE_ID_SBE_WANXL200	0x0302
+#define PCI_DEVICE_ID_SBE_WANXL400	0x0104
+#define PCI_SUBDEVICE_ID_SBE_T3E3	0x0009
+#define PCI_SUBDEVICE_ID_SBE_2T3E3_P0	0x0901
+#define PCI_SUBDEVICE_ID_SBE_2T3E3_P1	0x0902
+
+#define PCI_VENDOR_ID_TOSHIBA		0x1179
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1	0x0101
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2	0x0102
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_3	0x0103
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_5	0x0105
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95	0x060a
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC97	0x060f
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC100	0x0617
+
+#define PCI_VENDOR_ID_TOSHIBA_2		0x102f
+#define PCI_DEVICE_ID_TOSHIBA_TC35815CF	0x0030
+#define PCI_DEVICE_ID_TOSHIBA_TC35815_NWU	0x0031
+#define PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939	0x0032
+#define PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE	0x0105
+#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC	0x0108
+#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3
+
+#define PCI_VENDOR_ID_ATTO		0x117c
+
+#define PCI_VENDOR_ID_RICOH		0x1180
+#define PCI_DEVICE_ID_RICOH_RL5C465	0x0465
+#define PCI_DEVICE_ID_RICOH_RL5C466	0x0466
+#define PCI_DEVICE_ID_RICOH_RL5C475	0x0475
+#define PCI_DEVICE_ID_RICOH_RL5C476	0x0476
+#define PCI_DEVICE_ID_RICOH_RL5C478	0x0478
+#define PCI_DEVICE_ID_RICOH_R5C822	0x0822
+#define PCI_DEVICE_ID_RICOH_R5CE822	0xe822
+#define PCI_DEVICE_ID_RICOH_R5CE823	0xe823
+#define PCI_DEVICE_ID_RICOH_R5C832	0x0832
+#define PCI_DEVICE_ID_RICOH_R5C843	0x0843
+
+#define PCI_VENDOR_ID_DLINK		0x1186
+#define PCI_DEVICE_ID_DLINK_8139	0x1300
+#define PCI_DEVICE_ID_DLINK_DGE510T	0x4c00
+
+#define PCI_VENDOR_ID_ARTOP		0x1191
+#define PCI_DEVICE_ID_ARTOP_ATP850UF	0x0005
+#define PCI_DEVICE_ID_ARTOP_ATP860	0x0006
+#define PCI_DEVICE_ID_ARTOP_ATP860R	0x0007
+#define PCI_DEVICE_ID_ARTOP_ATP865	0x0008
+#define PCI_DEVICE_ID_ARTOP_ATP865R	0x0009
+#define PCI_DEVICE_ID_ARTOP_ATP867A	0x000A
+#define PCI_DEVICE_ID_ARTOP_ATP867B	0x000B
+#define PCI_DEVICE_ID_ARTOP_AEC7610	0x8002
+#define PCI_DEVICE_ID_ARTOP_AEC7612UW	0x8010
+#define PCI_DEVICE_ID_ARTOP_AEC7612U	0x8020
+#define PCI_DEVICE_ID_ARTOP_AEC7612S	0x8030
+#define PCI_DEVICE_ID_ARTOP_AEC7612D	0x8040
+#define PCI_DEVICE_ID_ARTOP_AEC7612SUW	0x8050
+#define PCI_DEVICE_ID_ARTOP_8060	0x8060
+
+#define PCI_VENDOR_ID_ZEITNET		0x1193
+#define PCI_DEVICE_ID_ZEITNET_1221	0x0001
+#define PCI_DEVICE_ID_ZEITNET_1225	0x0002
+
+#define PCI_VENDOR_ID_FUJITSU_ME	0x119e
+#define PCI_DEVICE_ID_FUJITSU_FS155	0x0001
+#define PCI_DEVICE_ID_FUJITSU_FS50	0x0003
+
+#define PCI_SUBVENDOR_ID_KEYSPAN	0x11a9
+#define PCI_SUBDEVICE_ID_KEYSPAN_SX2	0x5334
+
+#define PCI_VENDOR_ID_MARVELL		0x11ab
+#define PCI_VENDOR_ID_MARVELL_EXT	0x1b4b
+#define PCI_DEVICE_ID_MARVELL_GT64111	0x4146
+#define PCI_DEVICE_ID_MARVELL_GT64260	0x6430
+#define PCI_DEVICE_ID_MARVELL_MV64360	0x6460
+#define PCI_DEVICE_ID_MARVELL_MV64460	0x6480
+#define PCI_DEVICE_ID_MARVELL_88ALP01_NAND	0x4100
+#define PCI_DEVICE_ID_MARVELL_88ALP01_SD	0x4101
+#define PCI_DEVICE_ID_MARVELL_88ALP01_CCIC	0x4102
+
+#define PCI_VENDOR_ID_V3		0x11b0
+#define PCI_DEVICE_ID_V3_V960		0x0001
+#define PCI_DEVICE_ID_V3_V351		0x0002
+
+#define PCI_VENDOR_ID_ATT		0x11c1
+#define PCI_DEVICE_ID_ATT_VENUS_MODEM	0x480
+
+#define PCI_VENDOR_ID_SPECIALIX		0x11cb
+#define PCI_DEVICE_ID_SPECIALIX_IO8	0x2000
+#define PCI_DEVICE_ID_SPECIALIX_RIO	0x8000
+#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
+
+#define PCI_VENDOR_ID_ANALOG_DEVICES	0x11d4
+#define PCI_DEVICE_ID_AD1889JS		0x1889
+
+#define PCI_DEVICE_ID_SEGA_BBA		0x1234
+
+#define PCI_VENDOR_ID_ZORAN		0x11de
+#define PCI_DEVICE_ID_ZORAN_36057	0x6057
+#define PCI_DEVICE_ID_ZORAN_36120	0x6120
+
+#define PCI_VENDOR_ID_COMPEX		0x11f6
+#define PCI_DEVICE_ID_COMPEX_ENET100VG4	0x0112
+
+#define PCI_VENDOR_ID_PMC_Sierra	0x11f8
+
+#define PCI_VENDOR_ID_RP		0x11fe
+#define PCI_DEVICE_ID_RP32INTF		0x0001
+#define PCI_DEVICE_ID_RP8INTF		0x0002
+#define PCI_DEVICE_ID_RP16INTF		0x0003
+#define PCI_DEVICE_ID_RP4QUAD		0x0004
+#define PCI_DEVICE_ID_RP8OCTA		0x0005
+#define PCI_DEVICE_ID_RP8J		0x0006
+#define PCI_DEVICE_ID_RP4J		0x0007
+#define PCI_DEVICE_ID_RP8SNI		0x0008
+#define PCI_DEVICE_ID_RP16SNI		0x0009
+#define PCI_DEVICE_ID_RPP4		0x000A
+#define PCI_DEVICE_ID_RPP8		0x000B
+#define PCI_DEVICE_ID_RP4M		0x000D
+#define PCI_DEVICE_ID_RP2_232		0x000E
+#define PCI_DEVICE_ID_RP2_422		0x000F
+#define PCI_DEVICE_ID_URP32INTF		0x0801
+#define PCI_DEVICE_ID_URP8INTF		0x0802
+#define PCI_DEVICE_ID_URP16INTF		0x0803
+#define PCI_DEVICE_ID_URP8OCTA		0x0805
+#define PCI_DEVICE_ID_UPCI_RM3_8PORT	0x080C
+#define PCI_DEVICE_ID_UPCI_RM3_4PORT	0x080D
+#define PCI_DEVICE_ID_CRP16INTF		0x0903
+
+#define PCI_VENDOR_ID_CYCLADES		0x120e
+#define PCI_DEVICE_ID_CYCLOM_Y_Lo	0x0100
+#define PCI_DEVICE_ID_CYCLOM_Y_Hi	0x0101
+#define PCI_DEVICE_ID_CYCLOM_4Y_Lo	0x0102
+#define PCI_DEVICE_ID_CYCLOM_4Y_Hi	0x0103
+#define PCI_DEVICE_ID_CYCLOM_8Y_Lo	0x0104
+#define PCI_DEVICE_ID_CYCLOM_8Y_Hi	0x0105
+#define PCI_DEVICE_ID_CYCLOM_Z_Lo	0x0200
+#define PCI_DEVICE_ID_CYCLOM_Z_Hi	0x0201
+#define PCI_DEVICE_ID_PC300_RX_2	0x0300
+#define PCI_DEVICE_ID_PC300_RX_1	0x0301
+#define PCI_DEVICE_ID_PC300_TE_2	0x0310
+#define PCI_DEVICE_ID_PC300_TE_1	0x0311
+#define PCI_DEVICE_ID_PC300_TE_M_2	0x0320
+#define PCI_DEVICE_ID_PC300_TE_M_1	0x0321
+
+#define PCI_VENDOR_ID_ESSENTIAL		0x120f
+#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER	0x0001
+
+#define PCI_VENDOR_ID_O2		0x1217
+#define PCI_DEVICE_ID_O2_6729		0x6729
+#define PCI_DEVICE_ID_O2_6730		0x673a
+#define PCI_DEVICE_ID_O2_6832		0x6832
+#define PCI_DEVICE_ID_O2_6836		0x6836
+#define PCI_DEVICE_ID_O2_6812		0x6872
+#define PCI_DEVICE_ID_O2_6933		0x6933
+#define PCI_DEVICE_ID_O2_8120		0x8120
+#define PCI_DEVICE_ID_O2_8220		0x8220
+#define PCI_DEVICE_ID_O2_8221		0x8221
+#define PCI_DEVICE_ID_O2_8320		0x8320
+#define PCI_DEVICE_ID_O2_8321		0x8321
+
+#define PCI_VENDOR_ID_3DFX		0x121a
+#define PCI_DEVICE_ID_3DFX_VOODOO	0x0001
+#define PCI_DEVICE_ID_3DFX_VOODOO2	0x0002
+#define PCI_DEVICE_ID_3DFX_BANSHEE	0x0003
+#define PCI_DEVICE_ID_3DFX_VOODOO3	0x0005
+#define PCI_DEVICE_ID_3DFX_VOODOO5	0x0009
+
+#define PCI_VENDOR_ID_AVM		0x1244
+#define PCI_DEVICE_ID_AVM_B1		0x0700
+#define PCI_DEVICE_ID_AVM_C4		0x0800
+#define PCI_DEVICE_ID_AVM_A1		0x0a00
+#define PCI_DEVICE_ID_AVM_A1_V2		0x0e00
+#define PCI_DEVICE_ID_AVM_C2		0x1100
+#define PCI_DEVICE_ID_AVM_T1		0x1200
+
+#define PCI_VENDOR_ID_STALLION		0x124d
+
+/* Allied Telesyn */
+#define PCI_VENDOR_ID_AT		0x1259
+#define PCI_SUBDEVICE_ID_AT_2700FX	0x2701
+#define PCI_SUBDEVICE_ID_AT_2701FX	0x2703
+
+#define PCI_VENDOR_ID_ESS		0x125d
+#define PCI_DEVICE_ID_ESS_ESS1968	0x1968
+#define PCI_DEVICE_ID_ESS_ESS1978	0x1978
+#define PCI_DEVICE_ID_ESS_ALLEGRO_1	0x1988
+#define PCI_DEVICE_ID_ESS_ALLEGRO	0x1989
+#define PCI_DEVICE_ID_ESS_CANYON3D_2LE	0x1990
+#define PCI_DEVICE_ID_ESS_CANYON3D_2	0x1992
+#define PCI_DEVICE_ID_ESS_MAESTRO3	0x1998
+#define PCI_DEVICE_ID_ESS_MAESTRO3_1	0x1999
+#define PCI_DEVICE_ID_ESS_MAESTRO3_HW	0x199a
+#define PCI_DEVICE_ID_ESS_MAESTRO3_2	0x199b
+
+#define PCI_VENDOR_ID_SATSAGEM		0x1267
+#define PCI_DEVICE_ID_SATSAGEM_NICCY	0x1016
+
+#define PCI_VENDOR_ID_SMI		0x126f
+#define PCI_DEVICE_ID_SMI_710		0x0710
+#define PCI_DEVICE_ID_SMI_712		0x0712
+#define PCI_DEVICE_ID_SMI_810		0x0810
+#define PCI_DEVICE_ID_SMI_501		0x0501
+
+#define PCI_VENDOR_ID_ENSONIQ		0x1274
+#define PCI_DEVICE_ID_ENSONIQ_CT5880	0x5880
+#define PCI_DEVICE_ID_ENSONIQ_ES1370	0x5000
+#define PCI_DEVICE_ID_ENSONIQ_ES1371	0x1371
+
+#define PCI_VENDOR_ID_TRANSMETA		0x1279
+#define PCI_DEVICE_ID_EFFICEON		0x0060
+
+#define PCI_VENDOR_ID_ROCKWELL		0x127A
+
+#define PCI_VENDOR_ID_DAVICOM		0x1282
+#define PCI_DEVICE_ID_DAVICOM_DM9102A	0x9102
+
+#define PCI_VENDOR_ID_ITE		0x1283
+#define PCI_DEVICE_ID_ITE_8172		0x8172
+#define PCI_DEVICE_ID_ITE_8211		0x8211
+#define PCI_DEVICE_ID_ITE_8212		0x8212
+#define PCI_DEVICE_ID_ITE_8213		0x8213
+#define PCI_DEVICE_ID_ITE_8152		0x8152
+#define PCI_DEVICE_ID_ITE_8872		0x8872
+#define PCI_DEVICE_ID_ITE_IT8330G_0	0xe886
+
+/* formerly Platform Tech */
+#define PCI_DEVICE_ID_ESS_ESS0100	0x0100
+
+#define PCI_VENDOR_ID_ALTEON		0x12ae
+
+#define PCI_SUBVENDOR_ID_CONNECT_TECH			0x12c4
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232		0x0001
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232		0x0002
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232		0x0003
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485		0x0004
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4	0x0005
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485		0x0006
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2	0x0007
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485		0x0008
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6	0x0009
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1	0x000A
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1	0x000B
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ		0x000C
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM		0x000D
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI		0x0100
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2		0x0201
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4		0x0202
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232	0x0300
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232	0x0301
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232	0x0302
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1	0x0310
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2	0x0311
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4	0x0312
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2	0x0320
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4	0x0321
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8	0x0322
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485	0x0330
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485	0x0331
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485	0x0332
+
+#define PCI_VENDOR_ID_NVIDIA_SGS	0x12d2
+#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
+
+#define PCI_SUBVENDOR_ID_CHASE_PCIFAST		0x12E0
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4		0x0031
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8		0x0021
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16	0x0011
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC	0x0041
+#define PCI_SUBVENDOR_ID_CHASE_PCIRAS		0x124D
+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4		0xF001
+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8		0xF010
+
+#define PCI_VENDOR_ID_AUREAL		0x12eb
+#define PCI_DEVICE_ID_AUREAL_VORTEX_1	0x0001
+#define PCI_DEVICE_ID_AUREAL_VORTEX_2	0x0002
+#define PCI_DEVICE_ID_AUREAL_ADVANTAGE	0x0003
+
+#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8
+#define PCI_DEVICE_ID_LML_33R10		0x8a02
+
+#define PCI_VENDOR_ID_ESDGMBH		0x12fe
+#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
+
+#define PCI_VENDOR_ID_CB		0x1307	/* Measurement Computing */
+
+#define PCI_VENDOR_ID_SIIG		0x131f
+#define PCI_SUBVENDOR_ID_SIIG		0x131f
+#define PCI_DEVICE_ID_SIIG_1S_10x_550	0x1000
+#define PCI_DEVICE_ID_SIIG_1S_10x_650	0x1001
+#define PCI_DEVICE_ID_SIIG_1S_10x_850	0x1002
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_550	0x1010
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_650	0x1011
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_850	0x1012
+#define PCI_DEVICE_ID_SIIG_1P_10x	0x1020
+#define PCI_DEVICE_ID_SIIG_2P_10x	0x1021
+#define PCI_DEVICE_ID_SIIG_2S_10x_550	0x1030
+#define PCI_DEVICE_ID_SIIG_2S_10x_650	0x1031
+#define PCI_DEVICE_ID_SIIG_2S_10x_850	0x1032
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_550	0x1034
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_650	0x1035
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_850	0x1036
+#define PCI_DEVICE_ID_SIIG_4S_10x_550	0x1050
+#define PCI_DEVICE_ID_SIIG_4S_10x_650	0x1051
+#define PCI_DEVICE_ID_SIIG_4S_10x_850	0x1052
+#define PCI_DEVICE_ID_SIIG_1S_20x_550	0x2000
+#define PCI_DEVICE_ID_SIIG_1S_20x_650	0x2001
+#define PCI_DEVICE_ID_SIIG_1S_20x_850	0x2002
+#define PCI_DEVICE_ID_SIIG_1P_20x	0x2020
+#define PCI_DEVICE_ID_SIIG_2P_20x	0x2021
+#define PCI_DEVICE_ID_SIIG_2S_20x_550	0x2030
+#define PCI_DEVICE_ID_SIIG_2S_20x_650	0x2031
+#define PCI_DEVICE_ID_SIIG_2S_20x_850	0x2032
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_550	0x2040
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_650	0x2041
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_850	0x2042
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_550	0x2010
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_650	0x2011
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_850	0x2012
+#define PCI_DEVICE_ID_SIIG_4S_20x_550	0x2050
+#define PCI_DEVICE_ID_SIIG_4S_20x_650	0x2051
+#define PCI_DEVICE_ID_SIIG_4S_20x_850	0x2052
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_550	0x2060
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_650	0x2061
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_850	0x2062
+#define PCI_DEVICE_ID_SIIG_8S_20x_550	0x2080
+#define PCI_DEVICE_ID_SIIG_8S_20x_650	0x2081
+#define PCI_DEVICE_ID_SIIG_8S_20x_850	0x2082
+#define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL	0x2050
+#define PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL	0x2530
+
+#define PCI_VENDOR_ID_RADISYS		0x1331
+
+#define PCI_VENDOR_ID_MICRO_MEMORY		0x1332
+#define PCI_DEVICE_ID_MICRO_MEMORY_5415CN	0x5415
+#define PCI_DEVICE_ID_MICRO_MEMORY_5425CN	0x5425
+#define PCI_DEVICE_ID_MICRO_MEMORY_6155		0x6155
+
+#define PCI_VENDOR_ID_DOMEX		0x134a
+#define PCI_DEVICE_ID_DOMEX_DMX3191D	0x0001
+
+#define PCI_VENDOR_ID_INTASHIELD	0x135a
+#define PCI_DEVICE_ID_INTASHIELD_IS200	0x0d80
+#define PCI_DEVICE_ID_INTASHIELD_IS400	0x0dc0
+
+#define PCI_VENDOR_ID_QUATECH		0x135C
+#define PCI_DEVICE_ID_QUATECH_QSC100	0x0010
+#define PCI_DEVICE_ID_QUATECH_DSC100	0x0020
+#define PCI_DEVICE_ID_QUATECH_DSC200	0x0030
+#define PCI_DEVICE_ID_QUATECH_QSC200	0x0040
+#define PCI_DEVICE_ID_QUATECH_ESC100D	0x0050
+#define PCI_DEVICE_ID_QUATECH_ESC100M	0x0060
+#define PCI_DEVICE_ID_QUATECH_QSCP100	0x0120
+#define PCI_DEVICE_ID_QUATECH_DSCP100	0x0130
+#define PCI_DEVICE_ID_QUATECH_QSCP200	0x0140
+#define PCI_DEVICE_ID_QUATECH_DSCP200	0x0150
+#define PCI_DEVICE_ID_QUATECH_QSCLP100	0x0170
+#define PCI_DEVICE_ID_QUATECH_DSCLP100	0x0180
+#define PCI_DEVICE_ID_QUATECH_DSC100E	0x0181
+#define PCI_DEVICE_ID_QUATECH_SSCLP100	0x0190
+#define PCI_DEVICE_ID_QUATECH_QSCLP200	0x01A0
+#define PCI_DEVICE_ID_QUATECH_DSCLP200	0x01B0
+#define PCI_DEVICE_ID_QUATECH_DSC200E	0x01B1
+#define PCI_DEVICE_ID_QUATECH_SSCLP200	0x01C0
+#define PCI_DEVICE_ID_QUATECH_ESCLP100	0x01E0
+#define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278
+
+#define PCI_VENDOR_ID_SEALEVEL		0x135e
+#define PCI_DEVICE_ID_SEALEVEL_U530	0x7101
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM2	0x7201
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM422	0x7402
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM232	0x7202
+#define PCI_DEVICE_ID_SEALEVEL_COMM4	0x7401
+#define PCI_DEVICE_ID_SEALEVEL_COMM8	0x7801
+#define PCI_DEVICE_ID_SEALEVEL_7803	0x7803
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM8	0x7804
+
+#define PCI_VENDOR_ID_HYPERCOPE		0x1365
+#define PCI_DEVICE_ID_HYPERCOPE_PLX	0x9050
+#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO	0x0104
+#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO		0x0106
+#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO	0x0107
+#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2	0x0108
+
+#define PCI_VENDOR_ID_DIGIGRAM		0x1369
+#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_SERIAL_SUBSYSTEM	0xc001
+#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM	0xc002
+
+#define PCI_VENDOR_ID_KAWASAKI		0x136b
+#define PCI_DEVICE_ID_MCHIP_KL5A72002	0xff01
+
+#define PCI_VENDOR_ID_CNET		0x1371
+#define PCI_DEVICE_ID_CNET_GIGACARD	0x434e
+
+#define PCI_VENDOR_ID_LMC		0x1376
+#define PCI_DEVICE_ID_LMC_HSSI		0x0003
+#define PCI_DEVICE_ID_LMC_DS3		0x0004
+#define PCI_DEVICE_ID_LMC_SSI		0x0005
+#define PCI_DEVICE_ID_LMC_T1		0x0006
+
+#define PCI_VENDOR_ID_NETGEAR		0x1385
+#define PCI_DEVICE_ID_NETGEAR_GA620	0x620a
+
+#define PCI_VENDOR_ID_APPLICOM		0x1389
+#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
+#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002
+#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003
+
+#define PCI_VENDOR_ID_MOXA		0x1393
+#define PCI_DEVICE_ID_MOXA_RC7000	0x0001
+#define PCI_DEVICE_ID_MOXA_CP102	0x1020
+#define PCI_DEVICE_ID_MOXA_CP102UL	0x1021
+#define PCI_DEVICE_ID_MOXA_CP102U	0x1022
+#define PCI_DEVICE_ID_MOXA_C104		0x1040
+#define PCI_DEVICE_ID_MOXA_CP104U	0x1041
+#define PCI_DEVICE_ID_MOXA_CP104JU	0x1042
+#define PCI_DEVICE_ID_MOXA_CP104EL	0x1043
+#define PCI_DEVICE_ID_MOXA_CT114	0x1140
+#define PCI_DEVICE_ID_MOXA_CP114	0x1141
+#define PCI_DEVICE_ID_MOXA_CP118U	0x1180
+#define PCI_DEVICE_ID_MOXA_CP118EL	0x1181
+#define PCI_DEVICE_ID_MOXA_CP132	0x1320
+#define PCI_DEVICE_ID_MOXA_CP132U	0x1321
+#define PCI_DEVICE_ID_MOXA_CP134U	0x1340
+#define PCI_DEVICE_ID_MOXA_C168		0x1680
+#define PCI_DEVICE_ID_MOXA_CP168U	0x1681
+#define PCI_DEVICE_ID_MOXA_CP168EL	0x1682
+#define PCI_DEVICE_ID_MOXA_CP204J	0x2040
+#define PCI_DEVICE_ID_MOXA_C218		0x2180
+#define PCI_DEVICE_ID_MOXA_C320		0x3200
+
+#define PCI_VENDOR_ID_CCD		0x1397
+#define PCI_DEVICE_ID_CCD_HFC4S		0x08B4
+#define PCI_SUBDEVICE_ID_CCD_PMX2S	0x1234
+#define PCI_DEVICE_ID_CCD_HFC8S		0x16B8
+#define PCI_DEVICE_ID_CCD_2BD0		0x2bd0
+#define PCI_DEVICE_ID_CCD_HFCE1		0x30B1
+#define PCI_SUBDEVICE_ID_CCD_SPD4S	0x3136
+#define PCI_SUBDEVICE_ID_CCD_SPDE1	0x3137
+#define PCI_DEVICE_ID_CCD_B000		0xb000
+#define PCI_DEVICE_ID_CCD_B006		0xb006
+#define PCI_DEVICE_ID_CCD_B007		0xb007
+#define PCI_DEVICE_ID_CCD_B008		0xb008
+#define PCI_DEVICE_ID_CCD_B009		0xb009
+#define PCI_DEVICE_ID_CCD_B00A		0xb00a
+#define PCI_DEVICE_ID_CCD_B00B		0xb00b
+#define PCI_DEVICE_ID_CCD_B00C		0xb00c
+#define PCI_DEVICE_ID_CCD_B100		0xb100
+#define PCI_SUBDEVICE_ID_CCD_IOB4ST	0xB520
+#define PCI_SUBDEVICE_ID_CCD_IOB8STR	0xB521
+#define PCI_SUBDEVICE_ID_CCD_IOB8ST	0xB522
+#define PCI_SUBDEVICE_ID_CCD_IOB1E1	0xB523
+#define PCI_SUBDEVICE_ID_CCD_SWYX4S	0xB540
+#define PCI_SUBDEVICE_ID_CCD_JH4S20	0xB550
+#define PCI_SUBDEVICE_ID_CCD_IOB8ST_1	0xB552
+#define PCI_SUBDEVICE_ID_CCD_JHSE1	0xB553
+#define PCI_SUBDEVICE_ID_CCD_JH8S	0xB55B
+#define PCI_SUBDEVICE_ID_CCD_BN4S	0xB560
+#define PCI_SUBDEVICE_ID_CCD_BN8S	0xB562
+#define PCI_SUBDEVICE_ID_CCD_BNE1	0xB563
+#define PCI_SUBDEVICE_ID_CCD_BNE1D	0xB564
+#define PCI_SUBDEVICE_ID_CCD_BNE1DP	0xB565
+#define PCI_SUBDEVICE_ID_CCD_BN2S	0xB566
+#define PCI_SUBDEVICE_ID_CCD_BN1SM	0xB567
+#define PCI_SUBDEVICE_ID_CCD_BN4SM	0xB568
+#define PCI_SUBDEVICE_ID_CCD_BN2SM	0xB569
+#define PCI_SUBDEVICE_ID_CCD_BNE1M	0xB56A
+#define PCI_SUBDEVICE_ID_CCD_BN8SP	0xB56B
+#define PCI_SUBDEVICE_ID_CCD_HFC4S	0xB620
+#define PCI_SUBDEVICE_ID_CCD_HFC8S	0xB622
+#define PCI_DEVICE_ID_CCD_B700		0xb700
+#define PCI_DEVICE_ID_CCD_B701		0xb701
+#define PCI_SUBDEVICE_ID_CCD_HFCE1	0xC523
+#define PCI_SUBDEVICE_ID_CCD_OV2S	0xE884
+#define PCI_SUBDEVICE_ID_CCD_OV4S	0xE888
+#define PCI_SUBDEVICE_ID_CCD_OV8S	0xE998
+
+#define PCI_VENDOR_ID_EXAR		0x13a8
+#define PCI_DEVICE_ID_EXAR_XR17C152	0x0152
+#define PCI_DEVICE_ID_EXAR_XR17C154	0x0154
+#define PCI_DEVICE_ID_EXAR_XR17C158	0x0158
+#define PCI_DEVICE_ID_EXAR_XR17V352	0x0352
+#define PCI_DEVICE_ID_EXAR_XR17V354	0x0354
+#define PCI_DEVICE_ID_EXAR_XR17V358	0x0358
+
+#define PCI_VENDOR_ID_MICROGATE		0x13c0
+#define PCI_DEVICE_ID_MICROGATE_USC	0x0010
+#define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
+
+#define PCI_VENDOR_ID_3WARE		0x13C1
+#define PCI_DEVICE_ID_3WARE_1000	0x1000
+#define PCI_DEVICE_ID_3WARE_7000	0x1001
+#define PCI_DEVICE_ID_3WARE_9000	0x1002
+
+#define PCI_VENDOR_ID_IOMEGA		0x13ca
+#define PCI_DEVICE_ID_IOMEGA_BUZ	0x4231
+
+#define PCI_VENDOR_ID_ABOCOM		0x13D1
+#define PCI_DEVICE_ID_ABOCOM_2BD1       0x2BD1
+
+#define PCI_VENDOR_ID_SUNDANCE		0x13f0
+
+#define PCI_VENDOR_ID_CMEDIA		0x13f6
+#define PCI_DEVICE_ID_CMEDIA_CM8338A	0x0100
+#define PCI_DEVICE_ID_CMEDIA_CM8338B	0x0101
+#define PCI_DEVICE_ID_CMEDIA_CM8738	0x0111
+#define PCI_DEVICE_ID_CMEDIA_CM8738B	0x0112
+
+#define PCI_VENDOR_ID_ADVANTECH		0x13fe
+
+#define PCI_VENDOR_ID_MEILHAUS		0x1402
+
+#define PCI_VENDOR_ID_LAVA		0x1407
+#define PCI_DEVICE_ID_LAVA_DSERIAL	0x0100 /* 2x 16550 */
+#define PCI_DEVICE_ID_LAVA_QUATRO_A	0x0101 /* 2x 16550, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUATRO_B	0x0102 /* 2x 16550, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUATTRO_A	0x0120 /* 2x 16550A, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUATTRO_B	0x0121 /* 2x 16550A, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_OCTO_A	0x0180 /* 4x 16550A, half of 8 port */
+#define PCI_DEVICE_ID_LAVA_OCTO_B	0x0181 /* 4x 16550A, half of 8 port */
+#define PCI_DEVICE_ID_LAVA_PORT_PLUS	0x0200 /* 2x 16650 */
+#define PCI_DEVICE_ID_LAVA_QUAD_A	0x0201 /* 2x 16650, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUAD_B	0x0202 /* 2x 16650, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_SSERIAL	0x0500 /* 1x 16550 */
+#define PCI_DEVICE_ID_LAVA_PORT_650	0x0600 /* 1x 16650 */
+#define PCI_DEVICE_ID_LAVA_PARALLEL	0x8000
+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A	0x8002 /* The Lava Dual Parallel is */
+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B	0x8003 /* two PCI devices on a card */
+#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR	0x8800
+
+#define PCI_VENDOR_ID_TIMEDIA		0x1409
+#define PCI_DEVICE_ID_TIMEDIA_1889	0x7168
+
+#define PCI_VENDOR_ID_ICE		0x1412
+#define PCI_DEVICE_ID_ICE_1712		0x1712
+#define PCI_DEVICE_ID_VT1724		0x1724
+
+#define PCI_VENDOR_ID_OXSEMI		0x1415
+#define PCI_DEVICE_ID_OXSEMI_12PCI840	0x8403
+#define PCI_DEVICE_ID_OXSEMI_PCIe840		0xC000
+#define PCI_DEVICE_ID_OXSEMI_PCIe840_G		0xC004
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_0		0xC100
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_0_G	0xC104
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1		0xC110
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_G	0xC114
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_U	0xC118
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU	0xC11C
+#define PCI_DEVICE_ID_OXSEMI_16PCI954	0x9501
+#define PCI_DEVICE_ID_OXSEMI_C950	0x950B
+#define PCI_DEVICE_ID_OXSEMI_16PCI95N	0x9511
+#define PCI_DEVICE_ID_OXSEMI_16PCI954PP	0x9513
+#define PCI_DEVICE_ID_OXSEMI_16PCI952	0x9521
+#define PCI_DEVICE_ID_OXSEMI_16PCI952PP	0x9523
+#define PCI_SUBDEVICE_ID_OXSEMI_C950	0x0001
+
+#define PCI_VENDOR_ID_CHELSIO		0x1425
+
+#define PCI_VENDOR_ID_ADLINK		0x144a
+
+#define PCI_VENDOR_ID_SAMSUNG		0x144d
+
+#define PCI_VENDOR_ID_GIGABYTE		0x1458
+
+#define PCI_VENDOR_ID_AMBIT		0x1468
+
+#define PCI_VENDOR_ID_MYRICOM		0x14c1
+
+#define PCI_VENDOR_ID_TITAN		0x14D2
+#define PCI_DEVICE_ID_TITAN_010L	0x8001
+#define PCI_DEVICE_ID_TITAN_100L	0x8010
+#define PCI_DEVICE_ID_TITAN_110L	0x8011
+#define PCI_DEVICE_ID_TITAN_200L	0x8020
+#define PCI_DEVICE_ID_TITAN_210L	0x8021
+#define PCI_DEVICE_ID_TITAN_400L	0x8040
+#define PCI_DEVICE_ID_TITAN_800L	0x8080
+#define PCI_DEVICE_ID_TITAN_100		0xA001
+#define PCI_DEVICE_ID_TITAN_200		0xA005
+#define PCI_DEVICE_ID_TITAN_400		0xA003
+#define PCI_DEVICE_ID_TITAN_800B	0xA004
+
+#define PCI_VENDOR_ID_PANACOM		0x14d4
+#define PCI_DEVICE_ID_PANACOM_QUADMODEM	0x0400
+#define PCI_DEVICE_ID_PANACOM_DUALMODEM	0x0402
+
+#define PCI_VENDOR_ID_SIPACKETS		0x14d9
+#define PCI_DEVICE_ID_SP1011		0x0010
+
+#define PCI_VENDOR_ID_AFAVLAB		0x14db
+#define PCI_DEVICE_ID_AFAVLAB_P028	0x2180
+#define PCI_DEVICE_ID_AFAVLAB_P030	0x2182
+#define PCI_SUBDEVICE_ID_AFAVLAB_P061		0x2150
+
+#define PCI_VENDOR_ID_AMPLICON		0x14dc
+
+#define PCI_VENDOR_ID_BCM_GVC          0x14a4
+#define PCI_VENDOR_ID_BROADCOM		0x14e4
+#define PCI_DEVICE_ID_TIGON3_5752	0x1600
+#define PCI_DEVICE_ID_TIGON3_5752M	0x1601
+#define PCI_DEVICE_ID_NX2_5709		0x1639
+#define PCI_DEVICE_ID_NX2_5709S		0x163a
+#define PCI_DEVICE_ID_TIGON3_5700	0x1644
+#define PCI_DEVICE_ID_TIGON3_5701	0x1645
+#define PCI_DEVICE_ID_TIGON3_5702	0x1646
+#define PCI_DEVICE_ID_TIGON3_5703	0x1647
+#define PCI_DEVICE_ID_TIGON3_5704	0x1648
+#define PCI_DEVICE_ID_TIGON3_5704S_2	0x1649
+#define PCI_DEVICE_ID_NX2_5706		0x164a
+#define PCI_DEVICE_ID_NX2_5708		0x164c
+#define PCI_DEVICE_ID_TIGON3_5702FE	0x164d
+#define PCI_DEVICE_ID_NX2_57710		0x164e
+#define PCI_DEVICE_ID_NX2_57711		0x164f
+#define PCI_DEVICE_ID_NX2_57711E	0x1650
+#define PCI_DEVICE_ID_TIGON3_5705	0x1653
+#define PCI_DEVICE_ID_TIGON3_5705_2	0x1654
+#define PCI_DEVICE_ID_TIGON3_5719	0x1657
+#define PCI_DEVICE_ID_TIGON3_5721	0x1659
+#define PCI_DEVICE_ID_TIGON3_5722	0x165a
+#define PCI_DEVICE_ID_TIGON3_5723	0x165b
+#define PCI_DEVICE_ID_TIGON3_5705M	0x165d
+#define PCI_DEVICE_ID_TIGON3_5705M_2	0x165e
+#define PCI_DEVICE_ID_NX2_57712		0x1662
+#define PCI_DEVICE_ID_NX2_57712E	0x1663
+#define PCI_DEVICE_ID_NX2_57712_MF	0x1663
+#define PCI_DEVICE_ID_TIGON3_5714	0x1668
+#define PCI_DEVICE_ID_TIGON3_5714S	0x1669
+#define PCI_DEVICE_ID_TIGON3_5780	0x166a
+#define PCI_DEVICE_ID_TIGON3_5780S	0x166b
+#define PCI_DEVICE_ID_TIGON3_5705F	0x166e
+#define PCI_DEVICE_ID_NX2_57712_VF	0x166f
+#define PCI_DEVICE_ID_TIGON3_5754M	0x1672
+#define PCI_DEVICE_ID_TIGON3_5755M	0x1673
+#define PCI_DEVICE_ID_TIGON3_5756	0x1674
+#define PCI_DEVICE_ID_TIGON3_5750	0x1676
+#define PCI_DEVICE_ID_TIGON3_5751	0x1677
+#define PCI_DEVICE_ID_TIGON3_5715	0x1678
+#define PCI_DEVICE_ID_TIGON3_5715S	0x1679
+#define PCI_DEVICE_ID_TIGON3_5754	0x167a
+#define PCI_DEVICE_ID_TIGON3_5755	0x167b
+#define PCI_DEVICE_ID_TIGON3_5751M	0x167d
+#define PCI_DEVICE_ID_TIGON3_5751F	0x167e
+#define PCI_DEVICE_ID_TIGON3_5787F	0x167f
+#define PCI_DEVICE_ID_TIGON3_5761E	0x1680
+#define PCI_DEVICE_ID_TIGON3_5761	0x1681
+#define PCI_DEVICE_ID_TIGON3_5764	0x1684
+#define PCI_DEVICE_ID_NX2_57800		0x168a
+#define PCI_DEVICE_ID_NX2_57840		0x168d
+#define PCI_DEVICE_ID_NX2_57810		0x168e
+#define PCI_DEVICE_ID_TIGON3_5787M	0x1693
+#define PCI_DEVICE_ID_TIGON3_5782	0x1696
+#define PCI_DEVICE_ID_TIGON3_5784	0x1698
+#define PCI_DEVICE_ID_TIGON3_5786	0x169a
+#define PCI_DEVICE_ID_TIGON3_5787	0x169b
+#define PCI_DEVICE_ID_TIGON3_5788	0x169c
+#define PCI_DEVICE_ID_TIGON3_5789	0x169d
+#define PCI_DEVICE_ID_NX2_57840_4_10	0x16a1
+#define PCI_DEVICE_ID_NX2_57840_2_20	0x16a2
+#define PCI_DEVICE_ID_NX2_57840_MF	0x16a4
+#define PCI_DEVICE_ID_NX2_57800_MF	0x16a5
+#define PCI_DEVICE_ID_TIGON3_5702X	0x16a6
+#define PCI_DEVICE_ID_TIGON3_5703X	0x16a7
+#define PCI_DEVICE_ID_TIGON3_5704S	0x16a8
+#define PCI_DEVICE_ID_NX2_57800_VF	0x16a9
+#define PCI_DEVICE_ID_NX2_5706S		0x16aa
+#define PCI_DEVICE_ID_NX2_5708S		0x16ac
+#define PCI_DEVICE_ID_NX2_57840_VF	0x16ad
+#define PCI_DEVICE_ID_NX2_57810_MF	0x16ae
+#define PCI_DEVICE_ID_NX2_57810_VF	0x16af
+#define PCI_DEVICE_ID_TIGON3_5702A3	0x16c6
+#define PCI_DEVICE_ID_TIGON3_5703A3	0x16c7
+#define PCI_DEVICE_ID_TIGON3_5781	0x16dd
+#define PCI_DEVICE_ID_TIGON3_5753	0x16f7
+#define PCI_DEVICE_ID_TIGON3_5753M	0x16fd
+#define PCI_DEVICE_ID_TIGON3_5753F	0x16fe
+#define PCI_DEVICE_ID_TIGON3_5901	0x170d
+#define PCI_DEVICE_ID_BCM4401B1		0x170c
+#define PCI_DEVICE_ID_TIGON3_5901_2	0x170e
+#define PCI_DEVICE_ID_TIGON3_5906	0x1712
+#define PCI_DEVICE_ID_TIGON3_5906M	0x1713
+#define PCI_DEVICE_ID_BCM4401		0x4401
+#define PCI_DEVICE_ID_BCM4401B0		0x4402
+
+#define PCI_VENDOR_ID_TOPIC		0x151f
+#define PCI_DEVICE_ID_TOPIC_TP560	0x0000
+
+#define PCI_VENDOR_ID_MAINPINE		0x1522
+#define PCI_DEVICE_ID_MAINPINE_PBRIDGE	0x0100
+#define PCI_VENDOR_ID_ENE		0x1524
+#define PCI_DEVICE_ID_ENE_CB710_FLASH	0x0510
+#define PCI_DEVICE_ID_ENE_CB712_SD	0x0550
+#define PCI_DEVICE_ID_ENE_CB712_SD_2	0x0551
+#define PCI_DEVICE_ID_ENE_CB714_SD	0x0750
+#define PCI_DEVICE_ID_ENE_CB714_SD_2	0x0751
+#define PCI_DEVICE_ID_ENE_1211		0x1211
+#define PCI_DEVICE_ID_ENE_1225		0x1225
+#define PCI_DEVICE_ID_ENE_1410		0x1410
+#define PCI_DEVICE_ID_ENE_710		0x1411
+#define PCI_DEVICE_ID_ENE_712		0x1412
+#define PCI_DEVICE_ID_ENE_1420		0x1420
+#define PCI_DEVICE_ID_ENE_720		0x1421
+#define PCI_DEVICE_ID_ENE_722		0x1422
+
+#define PCI_VENDOR_ID_MIPS		0x153f
+#define PCI_DEVICE_ID_MIPS_MSC01	0x0001
+
+#define PCI_SUBVENDOR_ID_PERLE          0x155f
+#define PCI_SUBDEVICE_ID_PCI_RAS4       0xf001
+#define PCI_SUBDEVICE_ID_PCI_RAS8       0xf010
+
+#define PCI_VENDOR_ID_SYBA		0x1592
+#define PCI_DEVICE_ID_SYBA_2P_EPP	0x0782
+#define PCI_DEVICE_ID_SYBA_1P_ECP	0x0783
+
+#define PCI_VENDOR_ID_MORETON		0x15aa
+#define PCI_DEVICE_ID_RASTEL_2PORT	0x2000
+
+#define PCI_VENDOR_ID_ZOLTRIX		0x15b0
+#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0
+
+#define PCI_VENDOR_ID_MELLANOX		0x15b3
+#define PCI_DEVICE_ID_MELLANOX_TAVOR	0x5a44
+#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE	0x5a46
+#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
+#define PCI_DEVICE_ID_MELLANOX_ARBEL	0x6282
+#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c
+#define PCI_DEVICE_ID_MELLANOX_SINAI	0x6274
+
+#define PCI_VENDOR_ID_DFI		0x15bd
+
+#define PCI_VENDOR_ID_QUICKNET		0x15e2
+#define PCI_DEVICE_ID_QUICKNET_XJ	0x0500
+
+/*
+ * ADDI-DATA GmbH communication cards <info@addi-data.com>
+ */
+#define PCI_VENDOR_ID_ADDIDATA_OLD             0x10E8
+#define PCI_VENDOR_ID_ADDIDATA                 0x15B8
+#define PCI_DEVICE_ID_ADDIDATA_APCI7500        0x7000
+#define PCI_DEVICE_ID_ADDIDATA_APCI7420        0x7001
+#define PCI_DEVICE_ID_ADDIDATA_APCI7300        0x7002
+#define PCI_DEVICE_ID_ADDIDATA_APCI7800        0x818E
+#define PCI_DEVICE_ID_ADDIDATA_APCI7500_2      0x7009
+#define PCI_DEVICE_ID_ADDIDATA_APCI7420_2      0x700A
+#define PCI_DEVICE_ID_ADDIDATA_APCI7300_2      0x700B
+#define PCI_DEVICE_ID_ADDIDATA_APCI7500_3      0x700C
+#define PCI_DEVICE_ID_ADDIDATA_APCI7420_3      0x700D
+#define PCI_DEVICE_ID_ADDIDATA_APCI7300_3      0x700E
+#define PCI_DEVICE_ID_ADDIDATA_APCI7800_3      0x700F
+#define PCI_DEVICE_ID_ADDIDATA_APCIe7300       0x7010
+#define PCI_DEVICE_ID_ADDIDATA_APCIe7420       0x7011
+#define PCI_DEVICE_ID_ADDIDATA_APCIe7500       0x7012
+#define PCI_DEVICE_ID_ADDIDATA_APCIe7800       0x7013
+
+#define PCI_VENDOR_ID_PDC		0x15e9
+
+#define PCI_VENDOR_ID_FARSITE           0x1619
+#define PCI_DEVICE_ID_FARSITE_T2P       0x0400
+#define PCI_DEVICE_ID_FARSITE_T4P       0x0440
+#define PCI_DEVICE_ID_FARSITE_T1U       0x0610
+#define PCI_DEVICE_ID_FARSITE_T2U       0x0620
+#define PCI_DEVICE_ID_FARSITE_T4U       0x0640
+#define PCI_DEVICE_ID_FARSITE_TE1       0x1610
+#define PCI_DEVICE_ID_FARSITE_TE1C      0x1612
+
+#define PCI_VENDOR_ID_ARIMA		0x161f
+
+#define PCI_VENDOR_ID_BROCADE		0x1657
+#define PCI_DEVICE_ID_BROCADE_CT	0x0014
+#define PCI_DEVICE_ID_BROCADE_FC_8G1P	0x0017
+#define PCI_DEVICE_ID_BROCADE_CT_FC	0x0021
+
+#define PCI_VENDOR_ID_SIBYTE		0x166d
+#define PCI_DEVICE_ID_BCM1250_PCI	0x0001
+#define PCI_DEVICE_ID_BCM1250_HT	0x0002
+
+#define PCI_VENDOR_ID_ATHEROS		0x168c
+
+#define PCI_VENDOR_ID_NETCELL		0x169c
+#define PCI_DEVICE_ID_REVOLUTION	0x0044
+
+#define PCI_VENDOR_ID_CENATEK		0x16CA
+#define PCI_DEVICE_ID_CENATEK_IDE	0x0001
+
+#define PCI_VENDOR_ID_VITESSE		0x1725
+#define PCI_DEVICE_ID_VITESSE_VSC7174	0x7174
+
+#define PCI_VENDOR_ID_LINKSYS		0x1737
+#define PCI_DEVICE_ID_LINKSYS_EG1064	0x1064
+
+#define PCI_VENDOR_ID_ALTIMA		0x173b
+#define PCI_DEVICE_ID_ALTIMA_AC1000	0x03e8
+#define PCI_DEVICE_ID_ALTIMA_AC1001	0x03e9
+#define PCI_DEVICE_ID_ALTIMA_AC9100	0x03ea
+#define PCI_DEVICE_ID_ALTIMA_AC1003	0x03eb
+
+#define PCI_VENDOR_ID_BELKIN		0x1799
+#define PCI_DEVICE_ID_BELKIN_F5D7010V7	0x701f
+
+#define PCI_VENDOR_ID_RDC		0x17f3
+#define PCI_DEVICE_ID_RDC_R6020		0x6020
+#define PCI_DEVICE_ID_RDC_R6030		0x6030
+#define PCI_DEVICE_ID_RDC_R6040		0x6040
+#define PCI_DEVICE_ID_RDC_R6060		0x6060
+#define PCI_DEVICE_ID_RDC_R6061		0x6061
+#define PCI_DEVICE_ID_RDC_D1010		0x1010
+
+#define PCI_VENDOR_ID_LENOVO		0x17aa
+
+#define PCI_VENDOR_ID_ARECA		0x17d3
+#define PCI_DEVICE_ID_ARECA_1110	0x1110
+#define PCI_DEVICE_ID_ARECA_1120	0x1120
+#define PCI_DEVICE_ID_ARECA_1130	0x1130
+#define PCI_DEVICE_ID_ARECA_1160	0x1160
+#define PCI_DEVICE_ID_ARECA_1170	0x1170
+#define PCI_DEVICE_ID_ARECA_1200	0x1200
+#define PCI_DEVICE_ID_ARECA_1201	0x1201
+#define PCI_DEVICE_ID_ARECA_1202	0x1202
+#define PCI_DEVICE_ID_ARECA_1210	0x1210
+#define PCI_DEVICE_ID_ARECA_1220	0x1220
+#define PCI_DEVICE_ID_ARECA_1230	0x1230
+#define PCI_DEVICE_ID_ARECA_1260	0x1260
+#define PCI_DEVICE_ID_ARECA_1270	0x1270
+#define PCI_DEVICE_ID_ARECA_1280	0x1280
+#define PCI_DEVICE_ID_ARECA_1380	0x1380
+#define PCI_DEVICE_ID_ARECA_1381	0x1381
+#define PCI_DEVICE_ID_ARECA_1680	0x1680
+#define PCI_DEVICE_ID_ARECA_1681	0x1681
+
+#define PCI_VENDOR_ID_S2IO		0x17d5
+#define	PCI_DEVICE_ID_S2IO_WIN		0x5731
+#define	PCI_DEVICE_ID_S2IO_UNI		0x5831
+#define PCI_DEVICE_ID_HERC_WIN		0x5732
+#define PCI_DEVICE_ID_HERC_UNI		0x5832
+
+#define PCI_VENDOR_ID_SITECOM		0x182d
+#define PCI_DEVICE_ID_SITECOM_DC105V2	0x3069
+
+#define PCI_VENDOR_ID_TOPSPIN		0x1867
+
+#define PCI_VENDOR_ID_COMMTECH		0x18f7
+
+#define PCI_VENDOR_ID_SILAN		0x1904
+
+#define PCI_VENDOR_ID_RENESAS		0x1912
+#define PCI_DEVICE_ID_RENESAS_SH7781	0x0001
+#define PCI_DEVICE_ID_RENESAS_SH7780	0x0002
+#define PCI_DEVICE_ID_RENESAS_SH7763	0x0004
+#define PCI_DEVICE_ID_RENESAS_SH7785	0x0007
+#define PCI_DEVICE_ID_RENESAS_SH7786	0x0010
+
+#define PCI_VENDOR_ID_SOLARFLARE	0x1924
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0	0x0703
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1	0x6703
+#define PCI_DEVICE_ID_SOLARFLARE_SFC4000B	0x0710
+
+#define PCI_VENDOR_ID_TDI               0x192E
+#define PCI_DEVICE_ID_TDI_EHCI          0x0101
+
+#define PCI_VENDOR_ID_FREESCALE		0x1957
+#define PCI_DEVICE_ID_MPC8308		0xc006
+#define PCI_DEVICE_ID_MPC8315E		0x00b4
+#define PCI_DEVICE_ID_MPC8315		0x00b5
+#define PCI_DEVICE_ID_MPC8314E		0x00b6
+#define PCI_DEVICE_ID_MPC8314		0x00b7
+#define PCI_DEVICE_ID_MPC8378E		0x00c4
+#define PCI_DEVICE_ID_MPC8378		0x00c5
+#define PCI_DEVICE_ID_MPC8377E		0x00c6
+#define PCI_DEVICE_ID_MPC8377		0x00c7
+#define PCI_DEVICE_ID_MPC8548E		0x0012
+#define PCI_DEVICE_ID_MPC8548		0x0013
+#define PCI_DEVICE_ID_MPC8543E		0x0014
+#define PCI_DEVICE_ID_MPC8543		0x0015
+#define PCI_DEVICE_ID_MPC8547E		0x0018
+#define PCI_DEVICE_ID_MPC8545E		0x0019
+#define PCI_DEVICE_ID_MPC8545		0x001a
+#define PCI_DEVICE_ID_MPC8569E		0x0061
+#define PCI_DEVICE_ID_MPC8569		0x0060
+#define PCI_DEVICE_ID_MPC8568E		0x0020
+#define PCI_DEVICE_ID_MPC8568		0x0021
+#define PCI_DEVICE_ID_MPC8567E		0x0022
+#define PCI_DEVICE_ID_MPC8567		0x0023
+#define PCI_DEVICE_ID_MPC8533E		0x0030
+#define PCI_DEVICE_ID_MPC8533		0x0031
+#define PCI_DEVICE_ID_MPC8544E		0x0032
+#define PCI_DEVICE_ID_MPC8544		0x0033
+#define PCI_DEVICE_ID_MPC8572E		0x0040
+#define PCI_DEVICE_ID_MPC8572		0x0041
+#define PCI_DEVICE_ID_MPC8536E		0x0050
+#define PCI_DEVICE_ID_MPC8536		0x0051
+#define PCI_DEVICE_ID_P2020E		0x0070
+#define PCI_DEVICE_ID_P2020		0x0071
+#define PCI_DEVICE_ID_P2010E		0x0078
+#define PCI_DEVICE_ID_P2010		0x0079
+#define PCI_DEVICE_ID_P1020E		0x0100
+#define PCI_DEVICE_ID_P1020		0x0101
+#define PCI_DEVICE_ID_P1021E		0x0102
+#define PCI_DEVICE_ID_P1021		0x0103
+#define PCI_DEVICE_ID_P1011E		0x0108
+#define PCI_DEVICE_ID_P1011		0x0109
+#define PCI_DEVICE_ID_P1022E		0x0110
+#define PCI_DEVICE_ID_P1022		0x0111
+#define PCI_DEVICE_ID_P1013E		0x0118
+#define PCI_DEVICE_ID_P1013		0x0119
+#define PCI_DEVICE_ID_P4080E		0x0400
+#define PCI_DEVICE_ID_P4080		0x0401
+#define PCI_DEVICE_ID_P4040E		0x0408
+#define PCI_DEVICE_ID_P4040		0x0409
+#define PCI_DEVICE_ID_P2040E		0x0410
+#define PCI_DEVICE_ID_P2040		0x0411
+#define PCI_DEVICE_ID_P3041E		0x041E
+#define PCI_DEVICE_ID_P3041		0x041F
+#define PCI_DEVICE_ID_P5020E		0x0420
+#define PCI_DEVICE_ID_P5020		0x0421
+#define PCI_DEVICE_ID_P5010E		0x0428
+#define PCI_DEVICE_ID_P5010		0x0429
+#define PCI_DEVICE_ID_MPC8641		0x7010
+#define PCI_DEVICE_ID_MPC8641D		0x7011
+#define PCI_DEVICE_ID_MPC8610		0x7018
+
+#define PCI_VENDOR_ID_PASEMI		0x1959
+
+#define PCI_VENDOR_ID_ATTANSIC		0x1969
+#define PCI_DEVICE_ID_ATTANSIC_L1	0x1048
+#define PCI_DEVICE_ID_ATTANSIC_L2	0x2048
+
+#define PCI_VENDOR_ID_JMICRON		0x197B
+#define PCI_DEVICE_ID_JMICRON_JMB360	0x2360
+#define PCI_DEVICE_ID_JMICRON_JMB361	0x2361
+#define PCI_DEVICE_ID_JMICRON_JMB362	0x2362
+#define PCI_DEVICE_ID_JMICRON_JMB363	0x2363
+#define PCI_DEVICE_ID_JMICRON_JMB364	0x2364
+#define PCI_DEVICE_ID_JMICRON_JMB365	0x2365
+#define PCI_DEVICE_ID_JMICRON_JMB366	0x2366
+#define PCI_DEVICE_ID_JMICRON_JMB368	0x2368
+#define PCI_DEVICE_ID_JMICRON_JMB369	0x2369
+#define PCI_DEVICE_ID_JMICRON_JMB38X_SD	0x2381
+#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382
+#define PCI_DEVICE_ID_JMICRON_JMB38X_MS	0x2383
+#define PCI_DEVICE_ID_JMICRON_JMB385_MS	0x2388
+#define PCI_DEVICE_ID_JMICRON_JMB388_SD	0x2391
+#define PCI_DEVICE_ID_JMICRON_JMB388_ESD 0x2392
+#define PCI_DEVICE_ID_JMICRON_JMB390_MS	0x2393
+
+#define PCI_VENDOR_ID_KORENIX		0x1982
+#define PCI_DEVICE_ID_KORENIX_JETCARDF0	0x1600
+#define PCI_DEVICE_ID_KORENIX_JETCARDF1	0x16ff
+#define PCI_DEVICE_ID_KORENIX_JETCARDF2	0x1700
+#define PCI_DEVICE_ID_KORENIX_JETCARDF3	0x17ff
+
+#define PCI_VENDOR_ID_QMI		0x1a32
+
+#define PCI_VENDOR_ID_AZWAVE		0x1a3b
+
+#define PCI_VENDOR_ID_ASMEDIA		0x1b21
+
+#define PCI_VENDOR_ID_CIRCUITCO		0x1cc8
+#define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD	0x0001
+
+#define PCI_VENDOR_ID_TEKRAM		0x1de1
+#define PCI_DEVICE_ID_TEKRAM_DC290	0xdc29
+
+#define PCI_VENDOR_ID_TEHUTI		0x1fc9
+#define PCI_DEVICE_ID_TEHUTI_3009	0x3009
+#define PCI_DEVICE_ID_TEHUTI_3010	0x3010
+#define PCI_DEVICE_ID_TEHUTI_3014	0x3014
+
+#define PCI_VENDOR_ID_HINT             0x3388
+#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013
+
+#define PCI_VENDOR_ID_3DLABS		0x3d3d
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2	0x0007
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V	0x0009
+
+#define PCI_VENDOR_ID_NETXEN		0x4040
+#define PCI_DEVICE_ID_NX2031_10GXSR	0x0001
+#define PCI_DEVICE_ID_NX2031_10GCX4	0x0002
+#define PCI_DEVICE_ID_NX2031_4GCU	0x0003
+#define PCI_DEVICE_ID_NX2031_IMEZ	0x0004
+#define PCI_DEVICE_ID_NX2031_HMEZ	0x0005
+#define PCI_DEVICE_ID_NX2031_XG_MGMT	0x0024
+#define PCI_DEVICE_ID_NX2031_XG_MGMT2	0x0025
+#define PCI_DEVICE_ID_NX3031		0x0100
+
+#define PCI_VENDOR_ID_AKS		0x416c
+#define PCI_DEVICE_ID_AKS_ALADDINCARD	0x0100
+
+#define PCI_VENDOR_ID_ACCESSIO		0x494f
+#define PCI_DEVICE_ID_ACCESSIO_WDG_CSM	0x22c0
+
+#define PCI_VENDOR_ID_S3		0x5333
+#define PCI_DEVICE_ID_S3_TRIO		0x8811
+#define PCI_DEVICE_ID_S3_868		0x8880
+#define PCI_DEVICE_ID_S3_968		0x88f0
+#define PCI_DEVICE_ID_S3_SAVAGE4	0x8a25
+#define PCI_DEVICE_ID_S3_PROSAVAGE8	0x8d04
+#define PCI_DEVICE_ID_S3_SONICVIBES	0xca00
+
+#define PCI_VENDOR_ID_DUNORD		0x5544
+#define PCI_DEVICE_ID_DUNORD_I3000	0x0001
+
+#define PCI_VENDOR_ID_DCI		0x6666
+#define PCI_DEVICE_ID_DCI_PCCOM4	0x0001
+#define PCI_DEVICE_ID_DCI_PCCOM8	0x0002
+#define PCI_DEVICE_ID_DCI_PCCOM2	0x0004
+
+#define PCI_VENDOR_ID_INTEL		0x8086
+#define PCI_DEVICE_ID_INTEL_EESSC	0x0008
+#define PCI_DEVICE_ID_INTEL_SNB_IMC	0x0100
+#define PCI_DEVICE_ID_INTEL_IVB_IMC	0x0154
+#define PCI_DEVICE_ID_INTEL_HSW_IMC	0x0c00
+#define PCI_DEVICE_ID_INTEL_PXHD_0	0x0320
+#define PCI_DEVICE_ID_INTEL_PXHD_1	0x0321
+#define PCI_DEVICE_ID_INTEL_PXH_0	0x0329
+#define PCI_DEVICE_ID_INTEL_PXH_1	0x032A
+#define PCI_DEVICE_ID_INTEL_PXHV	0x032C
+#define PCI_DEVICE_ID_INTEL_80332_0	0x0330
+#define PCI_DEVICE_ID_INTEL_80332_1	0x0332
+#define PCI_DEVICE_ID_INTEL_80333_0	0x0370
+#define PCI_DEVICE_ID_INTEL_80333_1	0x0372
+#define PCI_DEVICE_ID_INTEL_82375	0x0482
+#define PCI_DEVICE_ID_INTEL_82424	0x0483
+#define PCI_DEVICE_ID_INTEL_82378	0x0484
+#define PCI_DEVICE_ID_INTEL_MRST_SD0	0x0807
+#define PCI_DEVICE_ID_INTEL_MRST_SD1	0x0808
+#define PCI_DEVICE_ID_INTEL_MFD_SD	0x0820
+#define PCI_DEVICE_ID_INTEL_MFD_SDIO1	0x0821
+#define PCI_DEVICE_ID_INTEL_MFD_SDIO2	0x0822
+#define PCI_DEVICE_ID_INTEL_MFD_EMMC0	0x0823
+#define PCI_DEVICE_ID_INTEL_MFD_EMMC1	0x0824
+#define PCI_DEVICE_ID_INTEL_MRST_SD2	0x084F
+#define PCI_DEVICE_ID_INTEL_QRK_SDIO	0x08A7
+#define PCI_DEVICE_ID_INTEL_QRK_UART	0x0936
+#define PCI_DEVICE_ID_INTEL_QRK_EMAC	0x0937
+#define PCI_DEVICE_ID_INTEL_QRK_ILB	0x095E
+#define PCI_DEVICE_ID_INTEL_I960	0x0960
+#define PCI_DEVICE_ID_INTEL_I960RM	0x0962
+#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB	0x0c60
+#define PCI_DEVICE_ID_INTEL_BYT_SDIO		0x0f15
+#define PCI_DEVICE_ID_INTEL_BYT_SD		0x0f16
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC	0x0f1c
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IDE	0x0f20
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IDE_ALT	0x0f21
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA	0x0f22
+#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT	0x0f23
+#define PCI_DEVICE_ID_INTEL_BYT_EMMC2	0x0f50
+#define PCI_DEVICE_ID_INTEL_82541ER	0x1078
+#define PCI_DEVICE_ID_INTEL_82541GI_LF	0x107c
+#define PCI_DEVICE_ID_INTEL_82542	0x1000
+#define PCI_DEVICE_ID_INTEL_82543GC_FIBER	0x1001
+#define PCI_DEVICE_ID_INTEL_82543GC_COPPER	0x1004
+#define PCI_DEVICE_ID_INTEL_82544EI_COPPER	0x1008
+#define PCI_DEVICE_ID_INTEL_82544EI_FIBER	0x1009
+#define PCI_DEVICE_ID_INTEL_82544GC_COPPER	0x100C
+#define PCI_DEVICE_ID_INTEL_82544GC_LOM		0x100D
+#define PCI_DEVICE_ID_INTEL_82540EM		0x100E
+#define PCI_DEVICE_ID_INTEL_82545EM_COPPER	0x100F
+#define PCI_DEVICE_ID_INTEL_82546EB_COPPER	0x1010
+#define PCI_DEVICE_ID_INTEL_82545EM_FIBER	0x1011
+#define PCI_DEVICE_ID_INTEL_82546EB_FIBER	0x1012
+#define PCI_DEVICE_ID_INTEL_82546GB_COPPER	0x1079
+#define PCI_DEVICE_ID_INTEL_82540EM_LOM		0x1015
+#define PCI_DEVICE_ID_INTEL_82545GM_COPPER	0x1026
+#define PCI_DEVICE_ID_INTEL_82559		0x1030
+#define PCI_DEVICE_ID_INTEL_82559ER		0x1209
+#define PCI_DEVICE_ID_INTEL_82557		0x1229
+
+#define PCI_DEVICE_ID_INTEL_82562ET	0x1031
+
+#define PCI_DEVICE_ID_INTEL_82571EB_COPPER      0x105E
+#define PCI_DEVICE_ID_INTEL_82571EB_FIBER       0x105F
+#define PCI_DEVICE_ID_INTEL_82571EB_SERDES      0x1060
+#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER 0x10A4
+#define PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER 0x10D5
+#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER  0x10A5
+#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE  0x10BC
+#define PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL 0x10D9
+#define PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD 0x10DA
+#define PCI_DEVICE_ID_INTEL_82572EI_COPPER      0x107D
+#define PCI_DEVICE_ID_INTEL_82572EI_FIBER       0x107E
+#define PCI_DEVICE_ID_INTEL_82572EI_SERDES      0x107F
+#define PCI_DEVICE_ID_INTEL_82572EI             0x10B9
+#define PCI_DEVICE_ID_INTEL_82573E              0x108B
+#define PCI_DEVICE_ID_INTEL_82573E_IAMT         0x108C
+#define PCI_DEVICE_ID_INTEL_82573L              0x109A
+#define PCI_DEVICE_ID_INTEL_82574L              0x10D3
+#define PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3 0x10B5
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT     0x1096
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT     0x1098
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT     0x10BA
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT     0x10BB
+
+#define PCI_DEVICE_ID_INTEL_8257X_SOL	0x1062
+#define PCI_DEVICE_ID_INTEL_82573E_SOL	0x1085
+#define PCI_DEVICE_ID_INTEL_82573L_SOL	0x108F
+#define PCI_DEVICE_ID_INTEL_82815_MC	0x1130
+#define PCI_DEVICE_ID_INTEL_82815_CGC	0x1132
+#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
+#define PCI_DEVICE_ID_INTEL_7505_0	0x2550
+#define PCI_DEVICE_ID_INTEL_7205_0	0x255d
+#define PCI_DEVICE_ID_INTEL_82437	0x122d
+#define PCI_DEVICE_ID_INTEL_82371FB_0	0x122e
+#define PCI_DEVICE_ID_INTEL_82371FB_1	0x1230
+#define PCI_DEVICE_ID_INTEL_82371MX	0x1234
+#define PCI_DEVICE_ID_INTEL_82441	0x1237
+#define PCI_DEVICE_ID_INTEL_82380FB	0x124b
+#define PCI_DEVICE_ID_INTEL_82439	0x1250
+#define PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED		0x1531
+#define PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED		0x1532
+#define PCI_DEVICE_ID_INTEL_I210_COPPER			0x1533
+#define PCI_DEVICE_ID_INTEL_I210_SERDES			0x1536
+#define PCI_DEVICE_ID_INTEL_I210_1000BASEKX		0x1537
+#define PCI_DEVICE_ID_INTEL_I210_EXTPHY			0x1538
+#define PCI_DEVICE_ID_INTEL_I211_COPPER			0x1539
+#define PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS	0x157b
+#define PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS	0x157c
+#define PCI_DEVICE_ID_INTEL_80960_RP	0x1960
+#define PCI_DEVICE_ID_INTEL_82840_HB	0x1a21
+#define PCI_DEVICE_ID_INTEL_82845_HB	0x1a30
+#define PCI_DEVICE_ID_INTEL_IOAT	0x1a38
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE	0x1c03
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6	0x1c02
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDA	0x1c20
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS	0x1c22
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN	0x1c41
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Z68		0x1c44
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_P67		0x1c46
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_UM67	0x1c47
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM65	0x1c49
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H67		0x1c4a
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_HM67	0x1c4b
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q65		0x1c4c
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QS67	0x1c4d
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_Q67		0x1c4e
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_QM67	0x1c4f
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_B65		0x1c50
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C202	0x1c52
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C204	0x1c54
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_C206	0x1c56
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_H61		0x1c5c
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX	0x1c5f
+#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS	0x1d22
+#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC	0x1d40
+#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0	0x1d40
+#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1	0x1d41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE	0x1e03
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA	0x1e20
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI	0x1e31
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN	0x1e41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_B75	0x1e49
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_C216	0x1e53
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_H77	0x1e4A
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM70	0x1e5e
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM75	0x1e5d
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM76	0x1e59
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_HM77	0x1e57
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MBL_SAMPLE 0x1e42
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_NM70	0x1e5f
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q75	0x1e48
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Q77	0x1e47
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QM77	0x1e55
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_QS77	0x1e56
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_SFF_SAMPLE 0x1e43
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_UM77	0x1e58
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z75	0x1e46
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_Z77	0x1e44
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX	0x1e5f
+#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN	0x2310
+#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX	0x231f
+#define PCI_DEVICE_ID_INTEL_82801AA_0	0x2410
+#define PCI_DEVICE_ID_INTEL_82801AA_1	0x2411
+#define PCI_DEVICE_ID_INTEL_82801AA_3	0x2413
+#define PCI_DEVICE_ID_INTEL_82801AA_5	0x2415
+#define PCI_DEVICE_ID_INTEL_82801AA_6	0x2416
+#define PCI_DEVICE_ID_INTEL_82801AA_8	0x2418
+#define PCI_DEVICE_ID_INTEL_82801AB_0	0x2420
+#define PCI_DEVICE_ID_INTEL_82801AB_1	0x2421
+#define PCI_DEVICE_ID_INTEL_82801AB_3	0x2423
+#define PCI_DEVICE_ID_INTEL_82801AB_5	0x2425
+#define PCI_DEVICE_ID_INTEL_82801AB_6	0x2426
+#define PCI_DEVICE_ID_INTEL_82801AB_8	0x2428
+#define PCI_DEVICE_ID_INTEL_82801BA_0	0x2440
+#define PCI_DEVICE_ID_INTEL_82801BA_2	0x2443
+#define PCI_DEVICE_ID_INTEL_82801BA_4	0x2445
+#define PCI_DEVICE_ID_INTEL_82801BA_6	0x2448
+#define PCI_DEVICE_ID_INTEL_82801BA_8	0x244a
+#define PCI_DEVICE_ID_INTEL_82801BA_9	0x244b
+#define PCI_DEVICE_ID_INTEL_82801BA_10	0x244c
+#define PCI_DEVICE_ID_INTEL_82801BA_11	0x244e
+#define PCI_DEVICE_ID_INTEL_82801E_0	0x2450
+#define PCI_DEVICE_ID_INTEL_82801E_11	0x245b
+#define PCI_DEVICE_ID_INTEL_82801CA_0	0x2480
+#define PCI_DEVICE_ID_INTEL_82801CA_3	0x2483
+#define PCI_DEVICE_ID_INTEL_82801CA_5	0x2485
+#define PCI_DEVICE_ID_INTEL_82801CA_6	0x2486
+#define PCI_DEVICE_ID_INTEL_82801CA_10	0x248a
+#define PCI_DEVICE_ID_INTEL_82801CA_11	0x248b
+#define PCI_DEVICE_ID_INTEL_82801CA_12	0x248c
+#define PCI_DEVICE_ID_INTEL_82801DB_0	0x24c0
+#define PCI_DEVICE_ID_INTEL_82801DB_1	0x24c1
+#define PCI_DEVICE_ID_INTEL_82801DB_2	0x24c2
+#define PCI_DEVICE_ID_INTEL_82801DB_3	0x24c3
+#define PCI_DEVICE_ID_INTEL_82801DB_5	0x24c5
+#define PCI_DEVICE_ID_INTEL_82801DB_6	0x24c6
+#define PCI_DEVICE_ID_INTEL_82801DB_9	0x24c9
+#define PCI_DEVICE_ID_INTEL_82801DB_10	0x24ca
+#define PCI_DEVICE_ID_INTEL_82801DB_11	0x24cb
+#define PCI_DEVICE_ID_INTEL_82801DB_12  0x24cc
+#define PCI_DEVICE_ID_INTEL_82801EB_0	0x24d0
+#define PCI_DEVICE_ID_INTEL_82801EB_1	0x24d1
+#define PCI_DEVICE_ID_INTEL_82801EB_3	0x24d3
+#define PCI_DEVICE_ID_INTEL_82801EB_5	0x24d5
+#define PCI_DEVICE_ID_INTEL_82801EB_6	0x24d6
+#define PCI_DEVICE_ID_INTEL_82801EB_11	0x24db
+#define PCI_DEVICE_ID_INTEL_82801EB_12	0x24dc
+#define PCI_DEVICE_ID_INTEL_82801EB_13	0x24dd
+#define PCI_DEVICE_ID_INTEL_ESB_1	0x25a1
+#define PCI_DEVICE_ID_INTEL_ESB_2	0x25a2
+#define PCI_DEVICE_ID_INTEL_ESB_4	0x25a4
+#define PCI_DEVICE_ID_INTEL_ESB_5	0x25a6
+#define PCI_DEVICE_ID_INTEL_ESB_9	0x25ab
+#define PCI_DEVICE_ID_INTEL_ESB_10	0x25ac
+#define PCI_DEVICE_ID_INTEL_82820_HB	0x2500
+#define PCI_DEVICE_ID_INTEL_82820_UP_HB	0x2501
+#define PCI_DEVICE_ID_INTEL_82850_HB	0x2530
+#define PCI_DEVICE_ID_INTEL_82860_HB	0x2531
+#define PCI_DEVICE_ID_INTEL_E7501_MCH	0x254c
+#define PCI_DEVICE_ID_INTEL_82845G_HB	0x2560
+#define PCI_DEVICE_ID_INTEL_82845G_IG	0x2562
+#define PCI_DEVICE_ID_INTEL_82865_HB	0x2570
+#define PCI_DEVICE_ID_INTEL_82865_IG	0x2572
+#define PCI_DEVICE_ID_INTEL_82875_HB	0x2578
+#define PCI_DEVICE_ID_INTEL_82915G_HB	0x2580
+#define PCI_DEVICE_ID_INTEL_82915G_IG	0x2582
+#define PCI_DEVICE_ID_INTEL_82915GM_HB	0x2590
+#define PCI_DEVICE_ID_INTEL_82915GM_IG	0x2592
+#define PCI_DEVICE_ID_INTEL_5000_ERR	0x25F0
+#define PCI_DEVICE_ID_INTEL_5000_FBD0	0x25F5
+#define PCI_DEVICE_ID_INTEL_5000_FBD1	0x25F6
+#define PCI_DEVICE_ID_INTEL_82945G_HB	0x2770
+#define PCI_DEVICE_ID_INTEL_82945G_IG	0x2772
+#define PCI_DEVICE_ID_INTEL_3000_HB	0x2778
+#define PCI_DEVICE_ID_INTEL_82945GM_HB	0x27A0
+#define PCI_DEVICE_ID_INTEL_82945GM_IG	0x27A2
+#define PCI_DEVICE_ID_INTEL_ICH6_0	0x2640
+#define PCI_DEVICE_ID_INTEL_ICH6_1	0x2641
+#define PCI_DEVICE_ID_INTEL_ICH6_2	0x2642
+#define PCI_DEVICE_ID_INTEL_ICH6_16	0x266a
+#define PCI_DEVICE_ID_INTEL_ICH6_17	0x266d
+#define PCI_DEVICE_ID_INTEL_ICH6_18	0x266e
+#define PCI_DEVICE_ID_INTEL_ICH6_19	0x266f
+#define PCI_DEVICE_ID_INTEL_ESB2_0	0x2670
+#define PCI_DEVICE_ID_INTEL_ESB2_14	0x2698
+#define PCI_DEVICE_ID_INTEL_ESB2_17	0x269b
+#define PCI_DEVICE_ID_INTEL_ESB2_18	0x269e
+#define PCI_DEVICE_ID_INTEL_ICH7_0	0x27b8
+#define PCI_DEVICE_ID_INTEL_ICH7_1	0x27b9
+#define PCI_DEVICE_ID_INTEL_ICH7_30	0x27b0
+#define PCI_DEVICE_ID_INTEL_TGP_LPC	0x27bc
+#define PCI_DEVICE_ID_INTEL_ICH7_31	0x27bd
+#define PCI_DEVICE_ID_INTEL_NM10_AHCI	0x27c1
+#define PCI_DEVICE_ID_INTEL_ICH7_17	0x27da
+#define PCI_DEVICE_ID_INTEL_ICH7_19	0x27dd
+#define PCI_DEVICE_ID_INTEL_ICH7_20	0x27de
+#define PCI_DEVICE_ID_INTEL_ICH7_21	0x27df
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDMI	0x2806
+#define PCI_DEVICE_ID_INTEL_ICH8_0	0x2810
+#define PCI_DEVICE_ID_INTEL_ICH8_1	0x2811
+#define PCI_DEVICE_ID_INTEL_ICH8_2	0x2812
+#define PCI_DEVICE_ID_INTEL_ICH8_3	0x2814
+#define PCI_DEVICE_ID_INTEL_ICH8_4	0x2815
+#define PCI_DEVICE_ID_INTEL_ICH8_5	0x283e
+#define PCI_DEVICE_ID_INTEL_ICH8_6	0x2850
+#define PCI_DEVICE_ID_INTEL_ICH9_0	0x2910
+#define PCI_DEVICE_ID_INTEL_ICH9_1	0x2917
+#define PCI_DEVICE_ID_INTEL_ICH9_2	0x2912
+#define PCI_DEVICE_ID_INTEL_ICH9_3	0x2913
+#define PCI_DEVICE_ID_INTEL_ICH9_4	0x2914
+#define PCI_DEVICE_ID_INTEL_ICH9_5	0x2919
+#define PCI_DEVICE_ID_INTEL_ICH9_6	0x2930
+#define PCI_DEVICE_ID_INTEL_ICH9_7	0x2916
+#define PCI_DEVICE_ID_INTEL_ICH9_8	0x2918
+#define PCI_DEVICE_ID_INTEL_ICH9_AHCI	0x2922
+#define PCI_DEVICE_ID_INTEL_I7_MCR	0x2c18
+#define PCI_DEVICE_ID_INTEL_I7_MC_TAD	0x2c19
+#define PCI_DEVICE_ID_INTEL_I7_MC_RAS	0x2c1a
+#define PCI_DEVICE_ID_INTEL_I7_MC_TEST	0x2c1c
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL  0x2c20
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR  0x2c21
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK  0x2c22
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC    0x2c23
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL  0x2c28
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR  0x2c29
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK  0x2c2a
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC    0x2c2b
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL  0x2c30
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR  0x2c31
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK  0x2c32
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC    0x2c33
+#define PCI_DEVICE_ID_INTEL_I7_NONCORE	0x2c41
+#define PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT 0x2c40
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE     0x2c50
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT 0x2c51
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2 0x2c70
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_SAD         0x2c81
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0   0x2c90
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_PHY0    0x2c91
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR         0x2c98
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD      0x2c99
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST     0x2c9C
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL 0x2ca0
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR 0x2ca1
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK 0x2ca2
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC   0x2ca3
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL 0x2ca8
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR 0x2ca9
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK 0x2caa
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC   0x2cab
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2          0x2d98
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2       0x2d99
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2       0x2d9a
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2      0x2d9c
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2  0x2da0
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2  0x2da1
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2  0x2da2
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2    0x2da3
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2  0x2da8
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2  0x2da9
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2  0x2daa
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2    0x2dab
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2  0x2db0
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2  0x2db1
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2  0x2db2
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2    0x2db3
+#define PCI_DEVICE_ID_INTEL_82855PM_HB	0x3340
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG4	0x3429
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG5	0x342a
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG6	0x342b
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG7	0x342c
+#define PCI_DEVICE_ID_INTEL_X58_HUB_MGMT 0x342e
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG0	0x3430
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG1	0x3431
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG2	0x3432
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG3	0x3433
+#define PCI_DEVICE_ID_INTEL_82830_HB	0x3575
+#define PCI_DEVICE_ID_INTEL_82830_CGC	0x3577
+#define PCI_DEVICE_ID_INTEL_82854_HB	0x358c
+#define PCI_DEVICE_ID_INTEL_82854_IG	0x358e
+#define PCI_DEVICE_ID_INTEL_82855GM_HB	0x3580
+#define PCI_DEVICE_ID_INTEL_82855GM_IG	0x3582
+#define PCI_DEVICE_ID_INTEL_E7520_MCH	0x3590
+#define PCI_DEVICE_ID_INTEL_E7320_MCH	0x3592
+#define PCI_DEVICE_ID_INTEL_MCH_PA	0x3595
+#define PCI_DEVICE_ID_INTEL_MCH_PA1	0x3596
+#define PCI_DEVICE_ID_INTEL_MCH_PB	0x3597
+#define PCI_DEVICE_ID_INTEL_MCH_PB1	0x3598
+#define PCI_DEVICE_ID_INTEL_MCH_PC	0x3599
+#define PCI_DEVICE_ID_INTEL_MCH_PC1	0x359a
+#define PCI_DEVICE_ID_INTEL_E7525_MCH	0x359e
+#define PCI_DEVICE_ID_INTEL_I7300_MCH_ERR 0x360c
+#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 0x360f
+#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 0x3610
+#define PCI_DEVICE_ID_INTEL_IOAT_CNB	0x360b
+#define PCI_DEVICE_ID_INTEL_FBD_CNB	0x360c
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF0	0x3710
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF1	0x3711
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF2	0x3712
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF3	0x3713
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF4	0x3714
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF5	0x3715
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF6	0x3716
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF7	0x3717
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF8	0x3718
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF9	0x3719
+#define PCI_DEVICE_ID_INTEL_ICH10_0	0x3a14
+#define PCI_DEVICE_ID_INTEL_ICH10_1	0x3a16
+#define PCI_DEVICE_ID_INTEL_ICH10_2	0x3a18
+#define PCI_DEVICE_ID_INTEL_ICH10_3	0x3a1a
+#define PCI_DEVICE_ID_INTEL_ICH10_4	0x3a30
+#define PCI_DEVICE_ID_INTEL_ICH10_5	0x3a60
+#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN	0x3b00
+#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX	0x3b1f
+#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS	0x3b30
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB0	0x3c20
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB1	0x3c21
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB2	0x3c22
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB3	0x3c23
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB4	0x3c24
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB5	0x3c25
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB6	0x3c26
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB7	0x3c27
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB8	0x3c2e
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB9	0x3c2f
+#define PCI_DEVICE_ID_INTEL_UNC_HA	0x3c46
+#define PCI_DEVICE_ID_INTEL_UNC_IMC0	0x3cb0
+#define PCI_DEVICE_ID_INTEL_UNC_IMC1	0x3cb1
+#define PCI_DEVICE_ID_INTEL_UNC_IMC2	0x3cb4
+#define PCI_DEVICE_ID_INTEL_UNC_IMC3	0x3cb5
+#define PCI_DEVICE_ID_INTEL_UNC_QPI0	0x3c41
+#define PCI_DEVICE_ID_INTEL_UNC_QPI1	0x3c42
+#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE	0x3c43
+#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0	0x3c44
+#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1	0x3c45
+#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX	0x3ce0
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB	0x402f
+#define PCI_DEVICE_ID_INTEL_5100_16	0x65f0
+#define PCI_DEVICE_ID_INTEL_5100_19	0x65f3
+#define PCI_DEVICE_ID_INTEL_5100_21	0x65f5
+#define PCI_DEVICE_ID_INTEL_5100_22	0x65f6
+#define PCI_DEVICE_ID_INTEL_5400_ERR	0x4030
+#define PCI_DEVICE_ID_INTEL_5400_FBD0	0x4035
+#define PCI_DEVICE_ID_INTEL_5400_FBD1	0x4036
+#define PCI_DEVICE_ID_INTEL_IOAT_SCNB	0x65ff
+#define PCI_DEVICE_ID_INTEL_EP80579_0	0x5031
+#define PCI_DEVICE_ID_INTEL_EP80579_1	0x5032
+#define PCI_DEVICE_ID_INTEL_82371SB_0	0x7000
+#define PCI_DEVICE_ID_INTEL_82371SB_1	0x7010
+#define PCI_DEVICE_ID_INTEL_82371SB_2	0x7020
+#define PCI_DEVICE_ID_INTEL_82437VX	0x7030
+#define PCI_DEVICE_ID_INTEL_82439TX	0x7100
+#define PCI_DEVICE_ID_INTEL_82371AB_0	0x7110
+#define PCI_DEVICE_ID_INTEL_82371AB	0x7111
+#define PCI_DEVICE_ID_INTEL_82371AB_2	0x7112
+#define PCI_DEVICE_ID_INTEL_82371AB_3	0x7113
+#define PCI_DEVICE_ID_INTEL_82810_MC1	0x7120
+#define PCI_DEVICE_ID_INTEL_82810_IG1	0x7121
+#define PCI_DEVICE_ID_INTEL_82810_MC3	0x7122
+#define PCI_DEVICE_ID_INTEL_82810_IG3	0x7123
+#define PCI_DEVICE_ID_INTEL_82810E_MC	0x7124
+#define PCI_DEVICE_ID_INTEL_82810E_IG	0x7125
+#define PCI_DEVICE_ID_INTEL_82443LX_0	0x7180
+#define PCI_DEVICE_ID_INTEL_82443LX_1	0x7181
+#define PCI_DEVICE_ID_INTEL_82443BX_0	0x7190
+#define PCI_DEVICE_ID_INTEL_82443BX_1	0x7191
+#define PCI_DEVICE_ID_INTEL_82443BX_2	0x7192
+#define PCI_DEVICE_ID_INTEL_440MX	0x7195
+#define PCI_DEVICE_ID_INTEL_440MX_6	0x7196
+#define PCI_DEVICE_ID_INTEL_82443MX_0	0x7198
+#define PCI_DEVICE_ID_INTEL_82443MX_1	0x7199
+#define PCI_DEVICE_ID_INTEL_82443MX_3	0x719b
+#define PCI_DEVICE_ID_INTEL_82443GX_0	0x71a0
+#define PCI_DEVICE_ID_INTEL_82443GX_2	0x71a2
+#define PCI_DEVICE_ID_INTEL_82372FB_1	0x7601
+#define PCI_DEVICE_ID_INTEL_SCH_LPC	0x8119
+#define PCI_DEVICE_ID_INTEL_SCH_IDE	0x811a
+#define PCI_DEVICE_ID_INTEL_ITC_LPC	0x8186
+#define PCI_DEVICE_ID_INTEL_82454GX	0x84c4
+#define PCI_DEVICE_ID_INTEL_82450GX	0x84c5
+#define PCI_DEVICE_ID_INTEL_82451NX	0x84ca
+#define PCI_DEVICE_ID_INTEL_82454NX     0x84cb
+#define PCI_DEVICE_ID_INTEL_84460GX	0x84ea
+#define PCI_DEVICE_ID_INTEL_IXP4XX	0x8500
+#define PCI_DEVICE_ID_INTEL_TCF_GBE	0x8802
+#define PCI_DEVICE_ID_INTEL_TCF_SDIO_0	0x8809
+#define PCI_DEVICE_ID_INTEL_TCF_SDIO_1	0x880a
+#define PCI_DEVICE_ID_INTEL_TCF_SATA	0x880b
+#define PCI_DEVICE_ID_INTEL_TCF_UART_0	0x8811
+#define PCI_DEVICE_ID_INTEL_TCF_UART_1	0x8812
+#define PCI_DEVICE_ID_INTEL_TCF_UART_2	0x8813
+#define PCI_DEVICE_ID_INTEL_TCF_UART_3	0x8814
+#define PCI_DEVICE_ID_INTEL_IXP2800	0x9004
+#define PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI	0x9c03
+#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC	0x9c45
+#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI	0x9c83
+#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_HDA	0x9ca0
+#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_ADSP	0x9cb6
+#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC	0x9cc3
+#define PCI_DEVICE_ID_INTEL_S21152BB	0xb152
+
+#define PCI_VENDOR_ID_SCALEMP		0x8686
+#define PCI_DEVICE_ID_SCALEMP_VSMP_CTL	0x1010
+
+#define PCI_VENDOR_ID_COMPUTONE		0x8e0e
+#define PCI_DEVICE_ID_COMPUTONE_IP2EX	0x0291
+#define PCI_DEVICE_ID_COMPUTONE_PG	0x0302
+#define PCI_SUBVENDOR_ID_COMPUTONE	0x8e0e
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG4	0x0001
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG8	0x0002
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG6	0x0003
+
+#define PCI_VENDOR_ID_KTI		0x8e2e
+
+#define PCI_VENDOR_ID_ADAPTEC		0x9004
+#define PCI_DEVICE_ID_ADAPTEC_7810	0x1078
+#define PCI_DEVICE_ID_ADAPTEC_7821	0x2178
+#define PCI_DEVICE_ID_ADAPTEC_38602	0x3860
+#define PCI_DEVICE_ID_ADAPTEC_7850	0x5078
+#define PCI_DEVICE_ID_ADAPTEC_7855	0x5578
+#define PCI_DEVICE_ID_ADAPTEC_3860	0x6038
+#define PCI_DEVICE_ID_ADAPTEC_1480A	0x6075
+#define PCI_DEVICE_ID_ADAPTEC_7860	0x6078
+#define PCI_DEVICE_ID_ADAPTEC_7861	0x6178
+#define PCI_DEVICE_ID_ADAPTEC_7870	0x7078
+#define PCI_DEVICE_ID_ADAPTEC_7871	0x7178
+#define PCI_DEVICE_ID_ADAPTEC_7872	0x7278
+#define PCI_DEVICE_ID_ADAPTEC_7873	0x7378
+#define PCI_DEVICE_ID_ADAPTEC_7874	0x7478
+#define PCI_DEVICE_ID_ADAPTEC_7895	0x7895
+#define PCI_DEVICE_ID_ADAPTEC_7880	0x8078
+#define PCI_DEVICE_ID_ADAPTEC_7881	0x8178
+#define PCI_DEVICE_ID_ADAPTEC_7882	0x8278
+#define PCI_DEVICE_ID_ADAPTEC_7883	0x8378
+#define PCI_DEVICE_ID_ADAPTEC_7884	0x8478
+#define PCI_DEVICE_ID_ADAPTEC_7885	0x8578
+#define PCI_DEVICE_ID_ADAPTEC_7886	0x8678
+#define PCI_DEVICE_ID_ADAPTEC_7887	0x8778
+#define PCI_DEVICE_ID_ADAPTEC_7888	0x8878
+
+#define PCI_VENDOR_ID_ADAPTEC2		0x9005
+#define PCI_DEVICE_ID_ADAPTEC2_2940U2	0x0010
+#define PCI_DEVICE_ID_ADAPTEC2_2930U2	0x0011
+#define PCI_DEVICE_ID_ADAPTEC2_7890B	0x0013
+#define PCI_DEVICE_ID_ADAPTEC2_7890	0x001f
+#define PCI_DEVICE_ID_ADAPTEC2_3940U2	0x0050
+#define PCI_DEVICE_ID_ADAPTEC2_3950U2D	0x0051
+#define PCI_DEVICE_ID_ADAPTEC2_7896	0x005f
+#define PCI_DEVICE_ID_ADAPTEC2_7892A	0x0080
+#define PCI_DEVICE_ID_ADAPTEC2_7892B	0x0081
+#define PCI_DEVICE_ID_ADAPTEC2_7892D	0x0083
+#define PCI_DEVICE_ID_ADAPTEC2_7892P	0x008f
+#define PCI_DEVICE_ID_ADAPTEC2_7899A	0x00c0
+#define PCI_DEVICE_ID_ADAPTEC2_7899B	0x00c1
+#define PCI_DEVICE_ID_ADAPTEC2_7899D	0x00c3
+#define PCI_DEVICE_ID_ADAPTEC2_7899P	0x00cf
+#define PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN   0x0500
+#define PCI_DEVICE_ID_ADAPTEC2_SCAMP	0x0503
+
+#define PCI_VENDOR_ID_HOLTEK		0x9412
+#define PCI_DEVICE_ID_HOLTEK_6565	0x6565
+
+#define PCI_VENDOR_ID_NETMOS		0x9710
+#define PCI_DEVICE_ID_NETMOS_9705	0x9705
+#define PCI_DEVICE_ID_NETMOS_9715	0x9715
+#define PCI_DEVICE_ID_NETMOS_9735	0x9735
+#define PCI_DEVICE_ID_NETMOS_9745	0x9745
+#define PCI_DEVICE_ID_NETMOS_9755	0x9755
+#define PCI_DEVICE_ID_NETMOS_9805	0x9805
+#define PCI_DEVICE_ID_NETMOS_9815	0x9815
+#define PCI_DEVICE_ID_NETMOS_9835	0x9835
+#define PCI_DEVICE_ID_NETMOS_9845	0x9845
+#define PCI_DEVICE_ID_NETMOS_9855	0x9855
+#define PCI_DEVICE_ID_NETMOS_9865	0x9865
+#define PCI_DEVICE_ID_NETMOS_9900	0x9900
+#define PCI_DEVICE_ID_NETMOS_9901	0x9901
+#define PCI_DEVICE_ID_NETMOS_9904	0x9904
+#define PCI_DEVICE_ID_NETMOS_9912	0x9912
+#define PCI_DEVICE_ID_NETMOS_9922	0x9922
+
+#define PCI_VENDOR_ID_3COM_2		0xa727
+
+#define PCI_VENDOR_ID_DIGIUM		0xd161
+#define PCI_DEVICE_ID_DIGIUM_HFC4S	0xb410
+
+#define PCI_SUBVENDOR_ID_EXSYS		0xd84d
+#define PCI_SUBDEVICE_ID_EXSYS_4014	0x4014
+#define PCI_SUBDEVICE_ID_EXSYS_4055	0x4055
+
+#define PCI_VENDOR_ID_TIGERJET		0xe159
+#define PCI_DEVICE_ID_TIGERJET_300	0x0001
+#define PCI_DEVICE_ID_TIGERJET_100	0x0002
+
+#define PCI_VENDOR_ID_XILINX_RME	0xea60
+#define PCI_DEVICE_ID_RME_DIGI32	0x9896
+#define PCI_DEVICE_ID_RME_DIGI32_PRO	0x9897
+#define PCI_DEVICE_ID_RME_DIGI32_8	0x9898
+
+#define PCI_VENDOR_ID_XEN		0x5853
+#define PCI_DEVICE_ID_XEN_PLATFORM	0x0001
+
+#define PCI_VENDOR_ID_OCZ		0x1b85
diff --git a/include/pci_msc01.h b/include/pci_msc01.h
new file mode 100644
index 0000000..cdfd066
--- /dev/null
+++ b/include/pci_msc01.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@mips.com>
+ */
+
+#ifndef __PCI_MSC01_H__
+#define __PCI_MSC01_H__
+
+extern void msc01_pci_init(void *base, unsigned long sys_bus,
+			   unsigned long sys_phys, unsigned long sys_size,
+			   unsigned long mem_bus, unsigned long mem_phys,
+			   unsigned long mem_size, unsigned long io_bus,
+			   unsigned long io_phys, unsigned long io_size);
+
+#endif /* __PCI_MSC01_H__ */
diff --git a/include/pci_rom.h b/include/pci_rom.h
new file mode 100644
index 0000000..895c962
--- /dev/null
+++ b/include/pci_rom.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * From coreboot file of same name
+ */
+
+#ifndef _PCI_ROM_H
+#define _PCI_ROM_H
+
+#define PCI_ROM_HDR			0xaa55
+
+struct pci_rom_header {
+	uint16_t signature;
+	uint8_t size;
+	uint8_t init[3];
+	uint8_t reserved[0x12];
+	uint16_t data;
+};
+
+struct pci_rom_data {
+	uint32_t signature;
+	uint16_t vendor;
+	uint16_t device;
+	uint16_t reserved_1;
+	uint16_t dlen;
+	uint8_t drevision;
+	uint8_t class_lo;
+	uint16_t class_hi;
+	uint16_t ilen;
+	uint16_t irevision;
+	uint8_t type;
+	uint8_t indicator;
+	uint16_t reserved_2;
+};
+
+/*
+ * Determines which execution method is used and whether we allow falling back
+ * to the other if the requested method is not available.
+ */
+enum pci_rom_emul {
+	PCI_ROM_EMULATE		= 0 << 0,
+	PCI_ROM_USE_NATIVE	= 1 << 0,
+	PCI_ROM_ALLOW_FALLBACK	= 1 << 1,
+};
+
+ /**
+ * dm_pci_run_vga_bios() - Run the VGA BIOS in an x86 PC
+ *
+ * @dev:	Video device containing the BIOS
+ * @int15_handler:	Function to call to handle int 0x15
+ * @exec_method:	flags from enum pci_rom_emul
+ */
+int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
+			int exec_method);
+
+/**
+ * board_map_oprom_vendev() - map several PCI IDs to the one the ROM expects
+ *
+ * Some VGA option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselves.
+ *
+ * @vendev:	Vendor and device for the video device
+ * @return standard vendor and device expected by the ROM
+ */
+uint32_t board_map_oprom_vendev(uint32_t vendev);
+
+#endif
diff --git a/include/pci_tegra.h b/include/pci_tegra.h
new file mode 100644
index 0000000..11e92fc
--- /dev/null
+++ b/include/pci_tegra.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Toradex, Inc.
+ */
+
+struct tegra_pcie_port;
+
+int tegra_pcie_port_index_of_port(struct tegra_pcie_port *port);
+
+void tegra_pcie_port_reset(struct tegra_pcie_port *port);
diff --git a/include/pe.h b/include/pe.h
new file mode 100644
index 0000000..bff3b0a
--- /dev/null
+++ b/include/pe.h
@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Portable Executable binary format structures
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  Based on wine code
+ */
+
+#ifndef _PE_H
+#define _PE_H
+
+#include <asm-generic/pe.h>
+
+typedef struct _IMAGE_DOS_HEADER {
+	uint16_t e_magic;	/* 00: MZ Header signature */
+	uint16_t e_cblp;	/* 02: Bytes on last page of file */
+	uint16_t e_cp;		/* 04: Pages in file */
+	uint16_t e_crlc;	/* 06: Relocations */
+	uint16_t e_cparhdr;	/* 08: Size of header in paragraphs */
+	uint16_t e_minalloc;	/* 0a: Minimum extra paragraphs needed */
+	uint16_t e_maxalloc;	/* 0c: Maximum extra paragraphs needed */
+	uint16_t e_ss;		/* 0e: Initial (relative) SS value */
+	uint16_t e_sp;		/* 10: Initial SP value */
+	uint16_t e_csum;	/* 12: Checksum */
+	uint16_t e_ip;		/* 14: Initial IP value */
+	uint16_t e_cs;		/* 16: Initial (relative) CS value */
+	uint16_t e_lfarlc;	/* 18: File address of relocation table */
+	uint16_t e_ovno;	/* 1a: Overlay number */
+	uint16_t e_res[4];	/* 1c: Reserved words */
+	uint16_t e_oemid;	/* 24: OEM identifier (for e_oeminfo) */
+	uint16_t e_oeminfo;	/* 26: OEM information; e_oemid specific */
+	uint16_t e_res2[10];	/* 28: Reserved words */
+	uint32_t e_lfanew;	/* 3c: Offset to extended header */
+} IMAGE_DOS_HEADER, *PIMAGE_DOS_HEADER;
+
+typedef struct _IMAGE_FILE_HEADER {
+	uint16_t Machine;
+	uint16_t NumberOfSections;
+	uint32_t TimeDateStamp;
+	uint32_t PointerToSymbolTable;
+	uint32_t NumberOfSymbols;
+	uint16_t SizeOfOptionalHeader;
+	uint16_t Characteristics;
+} IMAGE_FILE_HEADER, *PIMAGE_FILE_HEADER;
+
+typedef struct _IMAGE_DATA_DIRECTORY {
+	uint32_t VirtualAddress;
+	uint32_t Size;
+} IMAGE_DATA_DIRECTORY, *PIMAGE_DATA_DIRECTORY;
+
+#define IMAGE_NUMBEROF_DIRECTORY_ENTRIES 16
+
+typedef struct _IMAGE_OPTIONAL_HEADER64 {
+	uint16_t Magic; /* 0x20b */
+	uint8_t  MajorLinkerVersion;
+	uint8_t  MinorLinkerVersion;
+	uint32_t SizeOfCode;
+	uint32_t SizeOfInitializedData;
+	uint32_t SizeOfUninitializedData;
+	uint32_t AddressOfEntryPoint;
+	uint32_t BaseOfCode;
+	uint64_t ImageBase;
+	uint32_t SectionAlignment;
+	uint32_t FileAlignment;
+	uint16_t MajorOperatingSystemVersion;
+	uint16_t MinorOperatingSystemVersion;
+	uint16_t MajorImageVersion;
+	uint16_t MinorImageVersion;
+	uint16_t MajorSubsystemVersion;
+	uint16_t MinorSubsystemVersion;
+	uint32_t Win32VersionValue;
+	uint32_t SizeOfImage;
+	uint32_t SizeOfHeaders;
+	uint32_t CheckSum;
+	uint16_t Subsystem;
+	uint16_t DllCharacteristics;
+	uint64_t SizeOfStackReserve;
+	uint64_t SizeOfStackCommit;
+	uint64_t SizeOfHeapReserve;
+	uint64_t SizeOfHeapCommit;
+	uint32_t LoaderFlags;
+	uint32_t NumberOfRvaAndSizes;
+	IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES];
+} IMAGE_OPTIONAL_HEADER64, *PIMAGE_OPTIONAL_HEADER64;
+
+typedef struct _IMAGE_NT_HEADERS64 {
+	uint32_t Signature;
+	IMAGE_FILE_HEADER FileHeader;
+	IMAGE_OPTIONAL_HEADER64 OptionalHeader;
+} IMAGE_NT_HEADERS64, *PIMAGE_NT_HEADERS64;
+
+typedef struct _IMAGE_OPTIONAL_HEADER {
+
+	/* Standard fields */
+
+	uint16_t Magic; /* 0x10b or 0x107 */     /* 0x00 */
+	uint8_t  MajorLinkerVersion;
+	uint8_t  MinorLinkerVersion;
+	uint32_t SizeOfCode;
+	uint32_t SizeOfInitializedData;
+	uint32_t SizeOfUninitializedData;
+	uint32_t AddressOfEntryPoint;            /* 0x10 */
+	uint32_t BaseOfCode;
+	uint32_t BaseOfData;
+
+	/* NT additional fields */
+
+	uint32_t ImageBase;
+	uint32_t SectionAlignment;               /* 0x20 */
+	uint32_t FileAlignment;
+	uint16_t MajorOperatingSystemVersion;
+	uint16_t MinorOperatingSystemVersion;
+	uint16_t MajorImageVersion;
+	uint16_t MinorImageVersion;
+	uint16_t MajorSubsystemVersion;          /* 0x30 */
+	uint16_t MinorSubsystemVersion;
+	uint32_t Win32VersionValue;
+	uint32_t SizeOfImage;
+	uint32_t SizeOfHeaders;
+	uint32_t CheckSum;                       /* 0x40 */
+	uint16_t Subsystem;
+	uint16_t DllCharacteristics;
+	uint32_t SizeOfStackReserve;
+	uint32_t SizeOfStackCommit;
+	uint32_t SizeOfHeapReserve;              /* 0x50 */
+	uint32_t SizeOfHeapCommit;
+	uint32_t LoaderFlags;
+	uint32_t NumberOfRvaAndSizes;
+	IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; /* 0x60 */
+	/* 0xE0 */
+} IMAGE_OPTIONAL_HEADER32, *PIMAGE_OPTIONAL_HEADER32;
+
+typedef struct _IMAGE_NT_HEADERS {
+	uint32_t Signature; /* "PE"\0\0 */       /* 0x00 */
+	IMAGE_FILE_HEADER FileHeader;         /* 0x04 */
+	IMAGE_OPTIONAL_HEADER32 OptionalHeader;       /* 0x18 */
+} IMAGE_NT_HEADERS32, *PIMAGE_NT_HEADERS32;
+
+#define IMAGE_SIZEOF_SHORT_NAME 8
+
+typedef struct _IMAGE_SECTION_HEADER {
+	uint8_t	Name[IMAGE_SIZEOF_SHORT_NAME];
+	union {
+		uint32_t PhysicalAddress;
+		uint32_t VirtualSize;
+	} Misc;
+	uint32_t VirtualAddress;
+	uint32_t SizeOfRawData;
+	uint32_t PointerToRawData;
+	uint32_t PointerToRelocations;
+	uint32_t PointerToLinenumbers;
+	uint16_t NumberOfRelocations;
+	uint16_t NumberOfLinenumbers;
+	uint32_t Characteristics;
+} IMAGE_SECTION_HEADER, *PIMAGE_SECTION_HEADER;
+
+#define IMAGE_DIRECTORY_ENTRY_BASERELOC         5
+
+typedef struct _IMAGE_BASE_RELOCATION
+{
+        uint32_t VirtualAddress;
+        uint32_t SizeOfBlock;
+        /* WORD TypeOffset[1]; */
+} IMAGE_BASE_RELOCATION,*PIMAGE_BASE_RELOCATION;
+
+typedef struct _IMAGE_RELOCATION
+{
+	union {
+		uint32_t VirtualAddress;
+		uint32_t RelocCount;
+	} DUMMYUNIONNAME;
+	uint32_t SymbolTableIndex;
+	uint16_t Type;
+} IMAGE_RELOCATION, *PIMAGE_RELOCATION;
+
+#define IMAGE_SIZEOF_RELOCATION 10
+
+/* generic relocation types */
+#define IMAGE_REL_BASED_ABSOLUTE                0
+#define IMAGE_REL_BASED_HIGH                    1
+#define IMAGE_REL_BASED_LOW                     2
+#define IMAGE_REL_BASED_HIGHLOW                 3
+#define IMAGE_REL_BASED_HIGHADJ                 4
+#define IMAGE_REL_BASED_MIPS_JMPADDR            5
+#define IMAGE_REL_BASED_ARM_MOV32A              5 /* yes, 5 too */
+#define IMAGE_REL_BASED_ARM_MOV32               5 /* yes, 5 too */
+#define IMAGE_REL_BASED_RISCV_HI20		5 /* yes, 5 too */
+#define IMAGE_REL_BASED_SECTION                 6
+#define IMAGE_REL_BASED_REL                     7
+#define IMAGE_REL_BASED_ARM_MOV32T              7 /* yes, 7 too */
+#define IMAGE_REL_BASED_THUMB_MOV32             7 /* yes, 7 too */
+#define IMAGE_REL_BASED_RISCV_LOW12I		7 /* yes, 7 too */
+#define IMAGE_REL_BASED_RISCV_LOW12S		8
+#define IMAGE_REL_BASED_MIPS_JMPADDR16          9
+#define IMAGE_REL_BASED_IA64_IMM64              9 /* yes, 9 too */
+#define IMAGE_REL_BASED_DIR64                   10
+#define IMAGE_REL_BASED_HIGH3ADJ                11
+
+/* ARM relocation types */
+#define IMAGE_REL_ARM_ABSOLUTE          0x0000
+#define IMAGE_REL_ARM_ADDR              0x0001
+#define IMAGE_REL_ARM_ADDR32NB          0x0002
+#define IMAGE_REL_ARM_BRANCH24          0x0003
+#define IMAGE_REL_ARM_BRANCH11          0x0004
+#define IMAGE_REL_ARM_TOKEN             0x0005
+#define IMAGE_REL_ARM_GPREL12           0x0006
+#define IMAGE_REL_ARM_GPREL7            0x0007
+#define IMAGE_REL_ARM_BLX24             0x0008
+#define IMAGE_REL_ARM_BLX11             0x0009
+#define IMAGE_REL_ARM_SECTION           0x000E
+#define IMAGE_REL_ARM_SECREL            0x000F
+#define IMAGE_REL_ARM_MOV32A            0x0010
+#define IMAGE_REL_ARM_MOV32T            0x0011
+#define IMAGE_REL_ARM_BRANCH20T         0x0012
+#define IMAGE_REL_ARM_BRANCH24T         0x0014
+#define IMAGE_REL_ARM_BLX23T            0x0015
+
+/* ARM64 relocation types */
+#define IMAGE_REL_ARM64_ABSOLUTE        0x0000
+#define IMAGE_REL_ARM64_ADDR32          0x0001
+#define IMAGE_REL_ARM64_ADDR32NB        0x0002
+#define IMAGE_REL_ARM64_BRANCH26        0x0003
+#define IMAGE_REL_ARM64_PAGEBASE_REL21  0x0004
+#define IMAGE_REL_ARM64_REL21           0x0005
+#define IMAGE_REL_ARM64_PAGEOFFSET_12A  0x0006
+#define IMAGE_REL_ARM64_PAGEOFFSET_12L  0x0007
+#define IMAGE_REL_ARM64_SECREL          0x0008
+#define IMAGE_REL_ARM64_SECREL_LOW12A   0x0009
+#define IMAGE_REL_ARM64_SECREL_HIGH12A  0x000A
+#define IMAGE_REL_ARM64_SECREL_LOW12L   0x000B
+#define IMAGE_REL_ARM64_TOKEN           0x000C
+#define IMAGE_REL_ARM64_SECTION         0x000D
+#define IMAGE_REL_ARM64_ADDR64          0x000E
+
+/* AMD64 relocation types */
+#define IMAGE_REL_AMD64_ABSOLUTE        0x0000
+#define IMAGE_REL_AMD64_ADDR64          0x0001
+#define IMAGE_REL_AMD64_ADDR32          0x0002
+#define IMAGE_REL_AMD64_ADDR32NB        0x0003
+#define IMAGE_REL_AMD64_REL32           0x0004
+#define IMAGE_REL_AMD64_REL32_1         0x0005
+#define IMAGE_REL_AMD64_REL32_2         0x0006
+#define IMAGE_REL_AMD64_REL32_3         0x0007
+#define IMAGE_REL_AMD64_REL32_4         0x0008
+#define IMAGE_REL_AMD64_REL32_5         0x0009
+#define IMAGE_REL_AMD64_SECTION         0x000A
+#define IMAGE_REL_AMD64_SECREL          0x000B
+#define IMAGE_REL_AMD64_SECREL7         0x000C
+#define IMAGE_REL_AMD64_TOKEN           0x000D
+#define IMAGE_REL_AMD64_SREL32          0x000E
+#define IMAGE_REL_AMD64_PAIR            0x000F
+#define IMAGE_REL_AMD64_SSPAN32         0x0010
+
+#endif /* _PE_H */
diff --git a/include/phy-sun4i-usb.h b/include/phy-sun4i-usb.h
new file mode 100644
index 0000000..b0a45b2
--- /dev/null
+++ b/include/phy-sun4i-usb.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __GENERIC_PHY_SUN4I_USB_H
+#define __GENERIC_PHY_SUN4I_USB_H
+
+/**
+ * sun4i_usb_phy_id_detect - detect ID pin of USB PHY
+ *
+ * @phy:	USB PHY port to detect ID pin
+ * @return 0 if OK, or a negative error code
+ */
+int sun4i_usb_phy_id_detect(struct phy *phy);
+
+/**
+ * sun4i_usb_phy_vbus_detect - detect VBUS pin of USB PHY
+ *
+ * @phy:	USB PHY port to detect VBUS pin
+ * @return 0 if OK, or a negative error code
+ */
+int sun4i_usb_phy_vbus_detect(struct phy *phy);
+
+/**
+ * sun4i_usb_phy_set_squelch_detect() - Enable/disable squelch detect
+ *
+ * @phy: reference to a sun4i usb phy
+ * @enabled: wether to enable or disable squelch detect
+ */
+void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled);
+
+#endif /*__GENERIC_PHY_SUN4I_USB_H */
diff --git a/include/phy.h b/include/phy.h
new file mode 100644
index 0000000..e50f56b
--- /dev/null
+++ b/include/phy.h
@@ -0,0 +1,440 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *	Andy Fleming <afleming@gmail.com>
+ *
+ * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
+ */
+
+#ifndef _PHY_H
+#define _PHY_H
+
+#include <dm.h>
+#include <linux/list.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/mdio.h>
+#include <phy_interface.h>
+
+#define PHY_FIXED_ID		0xa5a55a5a
+/*
+ * There is no actual id for this.
+ * This is just a dummy id for gmii2rgmmi converter.
+ */
+#define PHY_GMII2RGMII_ID	0x5a5a5a5a
+
+#define PHY_MAX_ADDR 32
+
+#define PHY_FLAG_BROKEN_RESET	(1 << 0) /* soft reset not supported */
+
+#define PHY_DEFAULT_FEATURES	(SUPPORTED_Autoneg | \
+				 SUPPORTED_TP | \
+				 SUPPORTED_MII)
+
+#define PHY_10BT_FEATURES	(SUPPORTED_10baseT_Half | \
+				 SUPPORTED_10baseT_Full)
+
+#define PHY_100BT_FEATURES	(SUPPORTED_100baseT_Half | \
+				 SUPPORTED_100baseT_Full)
+
+#define PHY_1000BT_FEATURES	(SUPPORTED_1000baseT_Half | \
+				 SUPPORTED_1000baseT_Full)
+
+#define PHY_BASIC_FEATURES	(PHY_10BT_FEATURES | \
+				 PHY_100BT_FEATURES | \
+				 PHY_DEFAULT_FEATURES)
+
+#define PHY_GBIT_FEATURES	(PHY_BASIC_FEATURES | \
+				 PHY_1000BT_FEATURES)
+
+#define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
+				SUPPORTED_10000baseT_Full)
+
+#ifndef PHY_ANEG_TIMEOUT
+#define PHY_ANEG_TIMEOUT	4000
+#endif
+
+
+struct phy_device;
+
+#define MDIO_NAME_LEN 32
+
+struct mii_dev {
+	struct list_head link;
+	char name[MDIO_NAME_LEN];
+	void *priv;
+	int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
+	int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
+			u16 val);
+	int (*reset)(struct mii_dev *bus);
+	struct phy_device *phymap[PHY_MAX_ADDR];
+	u32 phy_mask;
+};
+
+/* struct phy_driver: a structure which defines PHY behavior
+ *
+ * uid will contain a number which represents the PHY.  During
+ * startup, the driver will poll the PHY to find out what its
+ * UID--as defined by registers 2 and 3--is.  The 32-bit result
+ * gotten from the PHY will be masked to
+ * discard any bits which may change based on revision numbers
+ * unimportant to functionality
+ *
+ */
+struct phy_driver {
+	char *name;
+	unsigned int uid;
+	unsigned int mask;
+	unsigned int mmds;
+
+	u32 features;
+
+	/* Called to do any driver startup necessities */
+	/* Will be called during phy_connect */
+	int (*probe)(struct phy_device *phydev);
+
+	/* Called to configure the PHY, and modify the controller
+	 * based on the results.  Should be called after phy_connect */
+	int (*config)(struct phy_device *phydev);
+
+	/* Called when starting up the controller */
+	int (*startup)(struct phy_device *phydev);
+
+	/* Called when bringing down the controller */
+	int (*shutdown)(struct phy_device *phydev);
+
+	int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
+	int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
+			u16 val);
+
+	/* Phy specific driver override for reading a MMD register */
+	int (*read_mmd)(struct phy_device *phydev, int devad, int reg);
+
+	/* Phy specific driver override for writing a MMD register */
+	int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
+			 u16 val);
+
+	struct list_head list;
+};
+
+struct phy_device {
+	/* Information about the PHY type */
+	/* And management functions */
+	struct mii_dev *bus;
+	struct phy_driver *drv;
+	void *priv;
+
+#ifdef CONFIG_DM_ETH
+	struct udevice *dev;
+	ofnode node;
+#else
+	struct eth_device *dev;
+#endif
+
+	/* forced speed & duplex (no autoneg)
+	 * partner speed & duplex & pause (autoneg)
+	 */
+	int speed;
+	int duplex;
+
+	/* The most recently read link state */
+	int link;
+	int port;
+	phy_interface_t interface;
+
+	u32 advertising;
+	u32 supported;
+	u32 mmds;
+
+	int autoneg;
+	int addr;
+	int pause;
+	int asym_pause;
+	u32 phy_id;
+	bool is_c45;
+	u32 flags;
+};
+
+struct fixed_link {
+	int phy_id;
+	int duplex;
+	int link_speed;
+	int pause;
+	int asym_pause;
+};
+
+static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
+{
+	struct mii_dev *bus = phydev->bus;
+
+	return bus->read(bus, phydev->addr, devad, regnum);
+}
+
+static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
+			u16 val)
+{
+	struct mii_dev *bus = phydev->bus;
+
+	return bus->write(bus, phydev->addr, devad, regnum, val);
+}
+
+static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
+					  int regnum)
+{
+	/* Write the desired MMD Devad */
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
+
+	/* Write the desired MMD register address */
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
+
+	/* Select the Function : DATA with no post increment */
+	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
+		  (devad | MII_MMD_CTRL_NOINCR));
+}
+
+static inline int phy_read_mmd(struct phy_device *phydev, int devad,
+			       int regnum)
+{
+	struct phy_driver *drv = phydev->drv;
+
+	if (regnum > (u16)~0 || devad > 32)
+		return -EINVAL;
+
+	/* driver-specific access */
+	if (drv->read_mmd)
+		return drv->read_mmd(phydev, devad, regnum);
+
+	/* direct C45 / C22 access */
+	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
+	    devad == MDIO_DEVAD_NONE || !devad)
+		return phy_read(phydev, devad, regnum);
+
+	/* indirect C22 access */
+	phy_mmd_start_indirect(phydev, devad, regnum);
+
+	/* Read the content of the MMD's selected register */
+	return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
+}
+
+static inline int phy_write_mmd(struct phy_device *phydev, int devad,
+				int regnum, u16 val)
+{
+	struct phy_driver *drv = phydev->drv;
+
+	if (regnum > (u16)~0 || devad > 32)
+		return -EINVAL;
+
+	/* driver-specific access */
+	if (drv->write_mmd)
+		return drv->write_mmd(phydev, devad, regnum, val);
+
+	/* direct C45 / C22 access */
+	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
+	    devad == MDIO_DEVAD_NONE || !devad)
+		return phy_write(phydev, devad, regnum, val);
+
+	/* indirect C22 access */
+	phy_mmd_start_indirect(phydev, devad, regnum);
+
+	/* Write the data into MMD's selected register */
+	return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
+}
+
+#ifdef CONFIG_PHYLIB_10G
+extern struct phy_driver gen10g_driver;
+
+/* For now, XGMII is the only 10G interface */
+static inline int is_10g_interface(phy_interface_t interface)
+{
+	return interface == PHY_INTERFACE_MODE_XGMII;
+}
+
+#endif
+
+/**
+ * phy_init() - Initializes the PHY drivers
+ *
+ * This function registers all available PHY drivers
+ *
+ * @return 0 if OK, -ve on error
+ */
+int phy_init(void);
+
+/**
+ * phy_reset() - Resets the specified PHY
+ *
+ * Issues a reset of the PHY and waits for it to complete
+ *
+ * @phydev:	PHY to reset
+ * @return 0 if OK, -ve on error
+ */
+int phy_reset(struct phy_device *phydev);
+
+/**
+ * phy_find_by_mask() - Searches for a PHY on the specified MDIO bus
+ *
+ * The function checks the PHY addresses flagged in phy_mask and returns a
+ * phy_device pointer if it detects a PHY.
+ * This function should only be called if just one PHY is expected to be present
+ * in the set of addresses flagged in phy_mask.  If multiple PHYs are present,
+ * it is undefined which of these PHYs is returned.
+ *
+ * @bus:	MII/MDIO bus to scan
+ * @phy_mask:	bitmap of PYH addresses to scan
+ * @interface:	type of MAC-PHY interface
+ * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ */
+struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
+		phy_interface_t interface);
+
+#ifdef CONFIG_DM_ETH
+
+/**
+ * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
+ * @phydev:	PHY device
+ * @dev:	Ethernet device
+ */
+void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
+
+/**
+ * phy_connect() - Creates a PHY device for the Ethernet interface
+ *
+ * Creates a PHY device for the PHY at the given address, if one doesn't exist
+ * already, and associates it with the Ethernet device.
+ * The function may be called with addr <= 0, in this case addr value is ignored
+ * and the bus is scanned to detect a PHY.  Scanning should only be used if only
+ * one PHY is expected to be present on the MDIO bus, otherwise it is undefined
+ * which PHY is returned.
+ *
+ * @bus:	MII/MDIO bus that hosts the PHY
+ * @addr:	PHY address on MDIO bus
+ * @dev:	Ethernet device to associate to the PHY
+ * @interface:	type of MAC-PHY interface
+ * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ */
+struct phy_device *phy_connect(struct mii_dev *bus, int addr,
+				struct udevice *dev,
+				phy_interface_t interface);
+
+static inline ofnode phy_get_ofnode(struct phy_device *phydev)
+{
+	if (ofnode_valid(phydev->node))
+		return phydev->node;
+	else
+		return dev_ofnode(phydev->dev);
+}
+#else
+
+/**
+ * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
+ * @phydev:	PHY device
+ * @dev:	Ethernet device
+ */
+void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
+
+/**
+ * phy_connect() - Creates a PHY device for the Ethernet interface
+ *
+ * Creates a PHY device for the PHY at the given address, if one doesn't exist
+ * already, and associates it with the Ethernet device.
+ * The function may be called with addr <= 0, in this case addr value is ignored
+ * and the bus is scanned to detect a PHY.  Scanning should only be used if only
+ * one PHY is expected to be present on the MDIO bus, otherwise it is undefined
+ * which PHY is returned.
+ *
+ * @bus:	MII/MDIO bus that hosts the PHY
+ * @addr:	PHY address on MDIO bus
+ * @dev:	Ethernet device to associate to the PHY
+ * @interface:	type of MAC-PHY interface
+ * @return pointer to phy_device if a PHY is found, or NULL otherwise
+ */
+struct phy_device *phy_connect(struct mii_dev *bus, int addr,
+				struct eth_device *dev,
+				phy_interface_t interface);
+
+static inline ofnode phy_get_ofnode(struct phy_device *phydev)
+{
+	return ofnode_null();
+}
+#endif
+int phy_startup(struct phy_device *phydev);
+int phy_config(struct phy_device *phydev);
+int phy_shutdown(struct phy_device *phydev);
+int phy_register(struct phy_driver *drv);
+int phy_set_supported(struct phy_device *phydev, u32 max_speed);
+int genphy_config_aneg(struct phy_device *phydev);
+int genphy_restart_aneg(struct phy_device *phydev);
+int genphy_update_link(struct phy_device *phydev);
+int genphy_parse_link(struct phy_device *phydev);
+int genphy_config(struct phy_device *phydev);
+int genphy_startup(struct phy_device *phydev);
+int genphy_shutdown(struct phy_device *phydev);
+int gen10g_config(struct phy_device *phydev);
+int gen10g_startup(struct phy_device *phydev);
+int gen10g_shutdown(struct phy_device *phydev);
+int gen10g_discover_mmds(struct phy_device *phydev);
+
+int phy_b53_init(void);
+int phy_mv88e61xx_init(void);
+int phy_aquantia_init(void);
+int phy_atheros_init(void);
+int phy_broadcom_init(void);
+int phy_cortina_init(void);
+int phy_davicom_init(void);
+int phy_et1011c_init(void);
+int phy_lxt_init(void);
+int phy_marvell_init(void);
+int phy_micrel_ksz8xxx_init(void);
+int phy_micrel_ksz90x1_init(void);
+int phy_meson_gxl_init(void);
+int phy_natsemi_init(void);
+int phy_realtek_init(void);
+int phy_smsc_init(void);
+int phy_teranetics_init(void);
+int phy_ti_init(void);
+int phy_vitesse_init(void);
+int phy_xilinx_init(void);
+int phy_mscc_init(void);
+int phy_fixed_init(void);
+int phy_xilinx_gmii2rgmii_init(void);
+
+int board_phy_config(struct phy_device *phydev);
+int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
+
+/**
+ * phy_get_interface_by_name() - Look up a PHY interface name
+ *
+ * @str:	PHY interface name, e.g. "mii"
+ * @return PHY_INTERFACE_MODE_... value, or -1 if not found
+ */
+int phy_get_interface_by_name(const char *str);
+
+/**
+ * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
+ * is RGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+{
+	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
+		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
+}
+
+/**
+ * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
+ * is SGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
+{
+	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
+		phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
+}
+
+/* PHY UIDs for various PHYs that are referenced in external code */
+#define PHY_UID_CS4340  	0x13e51002
+#define PHY_UID_CS4223  	0x03e57003
+#define PHY_UID_TN2020		0x00a19410
+#define PHY_UID_IN112525_S03	0x02107440
+
+#endif
diff --git a/include/phy_interface.h b/include/phy_interface.h
new file mode 100644
index 0000000..c682318
--- /dev/null
+++ b/include/phy_interface.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *	Andy Fleming <afleming@gmail.com>
+ *
+ * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
+ */
+
+#ifndef _PHY_INTERFACE_H
+#define _PHY_INTERFACE_H
+
+typedef enum {
+	PHY_INTERFACE_MODE_MII,
+	PHY_INTERFACE_MODE_GMII,
+	PHY_INTERFACE_MODE_SGMII,
+	PHY_INTERFACE_MODE_SGMII_2500,
+	PHY_INTERFACE_MODE_QSGMII,
+	PHY_INTERFACE_MODE_TBI,
+	PHY_INTERFACE_MODE_RMII,
+	PHY_INTERFACE_MODE_RGMII,
+	PHY_INTERFACE_MODE_RGMII_ID,
+	PHY_INTERFACE_MODE_RGMII_RXID,
+	PHY_INTERFACE_MODE_RGMII_TXID,
+	PHY_INTERFACE_MODE_RTBI,
+	PHY_INTERFACE_MODE_XGMII,
+	PHY_INTERFACE_MODE_XAUI,
+	PHY_INTERFACE_MODE_RXAUI,
+	PHY_INTERFACE_MODE_SFI,
+	PHY_INTERFACE_MODE_INTERNAL,
+	PHY_INTERFACE_MODE_25G_AUI,
+	PHY_INTERFACE_MODE_XLAUI,
+	PHY_INTERFACE_MODE_CAUI2,
+	PHY_INTERFACE_MODE_CAUI4,
+	PHY_INTERFACE_MODE_NONE,	/* Must be last */
+
+	PHY_INTERFACE_MODE_COUNT,
+} phy_interface_t;
+
+static const char * const phy_interface_strings[] = {
+	[PHY_INTERFACE_MODE_MII]		= "mii",
+	[PHY_INTERFACE_MODE_GMII]		= "gmii",
+	[PHY_INTERFACE_MODE_SGMII]		= "sgmii",
+	[PHY_INTERFACE_MODE_SGMII_2500]		= "sgmii-2500",
+	[PHY_INTERFACE_MODE_QSGMII]		= "qsgmii",
+	[PHY_INTERFACE_MODE_TBI]		= "tbi",
+	[PHY_INTERFACE_MODE_RMII]		= "rmii",
+	[PHY_INTERFACE_MODE_RGMII]		= "rgmii",
+	[PHY_INTERFACE_MODE_RGMII_ID]		= "rgmii-id",
+	[PHY_INTERFACE_MODE_RGMII_RXID]		= "rgmii-rxid",
+	[PHY_INTERFACE_MODE_RGMII_TXID]		= "rgmii-txid",
+	[PHY_INTERFACE_MODE_RTBI]		= "rtbi",
+	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
+	[PHY_INTERFACE_MODE_XAUI]		= "xaui",
+	[PHY_INTERFACE_MODE_RXAUI]		= "rxaui",
+	[PHY_INTERFACE_MODE_SFI]		= "sfi",
+	[PHY_INTERFACE_MODE_INTERNAL]		= "internal",
+	[PHY_INTERFACE_MODE_25G_AUI]		= "25g-aui",
+	[PHY_INTERFACE_MODE_XLAUI]		= "xlaui4",
+	[PHY_INTERFACE_MODE_CAUI2]		= "caui2",
+	[PHY_INTERFACE_MODE_CAUI4]		= "caui4",
+	[PHY_INTERFACE_MODE_NONE]		= "",
+};
+
+static inline const char *phy_string_for_interface(phy_interface_t i)
+{
+	/* Default to unknown */
+	if (i > PHY_INTERFACE_MODE_NONE)
+		i = PHY_INTERFACE_MODE_NONE;
+
+	return phy_interface_strings[i];
+}
+
+#endif /* _PHY_INTERFACE_H */
diff --git a/include/phys2bus.h b/include/phys2bus.h
new file mode 100644
index 0000000..dc9b8e5
--- /dev/null
+++ b/include/phys2bus.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015 Stephen Warren
+ */
+
+#ifndef _BUS_ADDR_H
+#define _BUS_ADDR_H
+
+#ifdef CONFIG_PHYS_TO_BUS
+unsigned long phys_to_bus(unsigned long phys);
+unsigned long bus_to_phys(unsigned long bus);
+#else
+static inline unsigned long phys_to_bus(unsigned long phys)
+{
+	return phys;
+}
+
+static inline unsigned long bus_to_phys(unsigned long bus)
+{
+	return bus;
+}
+#endif
+
+#endif
diff --git a/include/physmem.h b/include/physmem.h
new file mode 100644
index 0000000..03d3a78
--- /dev/null
+++ b/include/physmem.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+/*
+ * These functions work like memset but operate on physical memory which may
+ * not be accessible directly.
+ *
+ * @param s	The physical address to start setting memory at.
+ * @param c	The character to set each byte of the region to.
+ * @param n	The number of bytes to set.
+ *
+ * @return	The physical address of the memory which was set.
+ */
+phys_addr_t arch_phys_memset(phys_addr_t s, int c, phys_size_t n);
diff --git a/include/post.h b/include/post.h
new file mode 100644
index 0000000..eb218ac
--- /dev/null
+++ b/include/post.h
@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2010
+ * Michael Zaidman, Kodak, michael.zaidman@kodak.com
+ * post_word_{load|store} cleanup.
+ */
+#ifndef _POST_H
+#define _POST_H
+
+#ifndef	__ASSEMBLY__
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_POST)
+
+#ifndef CONFIG_POST_EXTERNAL_WORD_FUNCS
+#ifdef CONFIG_SYS_POST_WORD_ADDR
+#define _POST_WORD_ADDR	CONFIG_SYS_POST_WORD_ADDR
+#else
+
+#if defined(CONFIG_ARCH_MPC8360)
+#include <linux/immap_qe.h>
+#define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
+
+#elif defined (CONFIG_MPC85xx)
+#include <asm/immap_85xx.h>
+#define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
+				offsetof(ccsr_pic_t, tfrr))
+
+#elif defined (CONFIG_MPC86xx)
+#include <asm/immap_86xx.h>
+#define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \
+				offsetof(ccsr_pic_t, tfrr))
+#endif
+
+#ifndef _POST_WORD_ADDR
+#error "_POST_WORD_ADDR currently not implemented for this platform!"
+#endif
+#endif /* CONFIG_SYS_POST_WORD_ADDR */
+
+static inline ulong post_word_load (void)
+{
+	return in_le32((volatile void *)(_POST_WORD_ADDR));
+}
+
+static inline void post_word_store (ulong value)
+{
+	out_le32((volatile void *)(_POST_WORD_ADDR), value);
+}
+
+#else
+
+extern ulong post_word_load(void);
+extern void post_word_store(ulong value);
+
+#endif /* CONFIG_POST_EXTERNAL_WORD_FUNCS */
+#endif /* defined (CONFIG_POST) */
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_POST
+
+#define POST_POWERON		0x01	/* test runs on power-on booting */
+#define POST_NORMAL		0x02	/* test runs on normal booting */
+#define POST_SLOWTEST		0x04	/* test is slow, enabled by key press */
+#define POST_POWERTEST		0x08	/* test runs after watchdog reset */
+
+#define POST_COLDBOOT		0x80	/* first boot after power-on */
+
+#define POST_ROM		0x0100	/* test runs in ROM */
+#define POST_RAM		0x0200	/* test runs in RAM */
+#define POST_MANUAL		0x0400	/* test runs on diag command */
+#define POST_REBOOT		0x0800	/* test may cause rebooting */
+#define POST_PREREL		0x1000  /* test runs before relocation */
+
+#define POST_CRITICAL		0x2000	/* Use failbootcmd if test failed */
+#define POST_STOP		0x4000	/* Interrupt POST sequence on fail */
+
+#define POST_MEM		(POST_RAM | POST_ROM)
+#define POST_ALWAYS		(POST_NORMAL	| \
+				 POST_SLOWTEST	| \
+				 POST_MANUAL	| \
+				 POST_POWERON	)
+
+#define POST_FAIL_SAVE		0x80
+
+#define POST_BEFORE		1
+#define POST_AFTER		0
+#define POST_PASSED		1
+#define POST_FAILED		0
+
+#ifndef	__ASSEMBLY__
+
+struct post_test {
+	char *name;
+	char *cmd;
+	char *desc;
+	int flags;
+	int (*test) (int flags);
+	int (*init_f) (void);
+	void (*reloc) (void);
+	unsigned long testid;
+};
+int post_init_f (void);
+void post_bootmode_init (void);
+int post_bootmode_get (unsigned int * last_test);
+void post_bootmode_clear (void);
+void post_output_backlog ( void );
+int post_run (char *name, int flags);
+int post_info (char *name);
+int post_log (char *format, ...);
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+void post_reloc (void);
+#endif
+unsigned long post_time_ms (unsigned long base);
+
+extern struct post_test post_list[];
+extern unsigned int post_list_size;
+extern int post_hotkeys_pressed(void);
+extern int memory_post_test(int flags);
+
+/*
+ *  If GCC is configured to use a version of GAS that supports
+ * the .gnu_attribute directive, it will use that directive to
+ * record certain properties of the output code.
+ *  This feature is new to GCC 4.3.0.
+ *  .gnu_attribute is new to GAS 2.18.
+ */
+#if (__GNUC__ >= 4 && __GNUC_MINOR__ >= 3)
+/* Tag_GNU_Power_ABI_FP/soft-float */
+#define GNU_FPOST_ATTR	asm(".gnu_attribute	4, 2");
+#else
+#define GNU_FPOST_ATTR
+#endif /* __GNUC__ */
+#endif /* __ASSEMBLY__ */
+
+#define CONFIG_SYS_POST_RTC		0x00000001
+#define CONFIG_SYS_POST_WATCHDOG	0x00000002
+#define CONFIG_SYS_POST_MEMORY		0x00000004
+#define CONFIG_SYS_POST_CPU		0x00000008
+#define CONFIG_SYS_POST_I2C		0x00000010
+#define CONFIG_SYS_POST_CACHE		0x00000020
+#define CONFIG_SYS_POST_UART		0x00000040
+#define CONFIG_SYS_POST_ETHER		0x00000080
+#define CONFIG_SYS_POST_USB		0x00000200
+#define CONFIG_SYS_POST_SPR		0x00000400
+#define CONFIG_SYS_POST_SYSMON		0x00000800
+#define CONFIG_SYS_POST_DSP		0x00001000
+#define CONFIG_SYS_POST_OCM		0x00002000
+#define CONFIG_SYS_POST_FPU		0x00004000
+#define CONFIG_SYS_POST_ECC		0x00008000
+#define CONFIG_SYS_POST_BSPEC1		0x00010000
+#define CONFIG_SYS_POST_BSPEC2		0x00020000
+#define CONFIG_SYS_POST_BSPEC3		0x00040000
+#define CONFIG_SYS_POST_BSPEC4		0x00080000
+#define CONFIG_SYS_POST_BSPEC5		0x00100000
+#define CONFIG_SYS_POST_CODEC		0x00200000
+#define CONFIG_SYS_POST_COPROC		0x00400000
+#define CONFIG_SYS_POST_FLASH		0x00800000
+#define CONFIG_SYS_POST_MEM_REGIONS	0x01000000
+
+#endif /* CONFIG_POST */
+
+#endif /* _POST_H */
diff --git a/include/power-domain-uclass.h b/include/power-domain-uclass.h
new file mode 100644
index 0000000..bd9906b
--- /dev/null
+++ b/include/power-domain-uclass.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _POWER_DOMAIN_UCLASS_H
+#define _POWER_DOMAIN_UCLASS_H
+
+/* See power-domain.h for background documentation. */
+
+#include <power-domain.h>
+
+struct udevice;
+
+/**
+ * struct power_domain_ops - The functions that a power domain controller driver
+ * must implement.
+ */
+struct power_domain_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) power domain
+	 * specifier.
+	 *
+	 * The power domain core calls this function as the first step in
+	 * implementing a client's power_domain_get() call.
+	 *
+	 * If this function pointer is set to NULL, the power domain core will
+	 * use a default implementation, which assumes #power-domain-cells =
+	 * <1>, and that the DT cell contains a simple integer power domain ID.
+	 *
+	 * At present, the power domain API solely supports device-tree. If
+	 * this changes, other xxx_xlate() functions may be added to support
+	 * those other mechanisms.
+	 *
+	 * @power_domain:	The power domain struct to hold the
+	 *			translation result.
+	 * @args:		The power domain specifier values from device
+	 *			tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct power_domain *power_domain,
+			struct ofnode_phandle_args *args);
+	/**
+	 * request - Request a translated power domain.
+	 *
+	 * The power domain core calls this function as the second step in
+	 * implementing a client's power_domain_get() call, following a
+	 * successful xxx_xlate() call.
+	 *
+	 * @power_domain:	The power domain to request; this has been
+	 *			filled in by a previous xxx_xlate() function
+	 *			call.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct power_domain *power_domain);
+	/**
+	 * free - Free a previously requested power domain.
+	 *
+	 * This is the implementation of the client power_domain_free() API.
+	 *
+	 * @power_domain:	The power domain to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct power_domain *power_domain);
+	/**
+	 * on - Power on a power domain.
+	 *
+	 * @power_domain:	The power domain to turn on.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*on)(struct power_domain *power_domain);
+	/**
+	 * off - Power off a power domain.
+	 *
+	 * @power_domain:	The power domain to turn off.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*off)(struct power_domain *power_domain);
+};
+
+#endif
diff --git a/include/power-domain.h b/include/power-domain.h
new file mode 100644
index 0000000..72ff2ff
--- /dev/null
+++ b/include/power-domain.h
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _POWER_DOMAIN_H
+#define _POWER_DOMAIN_H
+
+/**
+ * A power domain is a portion of an SoC or chip that is powered by a
+ * switchable source of power. In many cases, software has control over the
+ * power domain, and can turn the power source on or off. This is typically
+ * done to save power by powering off unused devices, or to enable software
+ * sequencing of initial powerup at boot. This API provides a means for
+ * drivers to turn power domains on and off.
+ *
+ * A driver that implements UCLASS_POWER_DOMAIN is a power domain controller or
+ * provider. A controller will often implement multiple separate power domains,
+ * since the hardware it manages often has this capability.
+ * power-domain-uclass.h describes the interface which power domain controllers
+ * must implement.
+ *
+ * Depending on the power domain controller hardware, changing the state of a
+ * power domain may require performing related operations on other resources.
+ * For example, some power domains may require certain clocks to be enabled
+ * whenever the power domain is powered on, or during the time when the power
+ * domain is transitioning state. These details are implementation-specific
+ * and should ideally be encapsulated entirely within the provider driver, or
+ * configured through mechanisms (e.g. device tree) that do not require client
+ * drivers to provide extra configuration information.
+ *
+ * Power domain consumers/clients are the drivers for HW modules within the
+ * power domain. This header file describes the API used by those drivers.
+ *
+ * In many cases, a single complex IO controller (e.g. a PCIe controller) will
+ * be the sole logic contained within a power domain. In such cases, it is
+ * logical for the relevant device driver to directly control that power
+ * domain. In other cases, multiple controllers, each with their own driver,
+ * may be contained in a single power domain. Any logic require to co-ordinate
+ * between drivers for these multiple controllers is beyond the scope of this
+ * API at present. Equally, this API does not define or implement any policy
+ * by which power domains are managed.
+ */
+
+struct udevice;
+
+/**
+ * struct power_domain - A handle to (allowing control of) a single power domain.
+ *
+ * Clients provide storage for power domain handles. The content of the
+ * structure is managed solely by the power domain API and power domain
+ * drivers. A power domain struct is initialized by "get"ing the power domain
+ * struct. The power domain struct is passed to all other power domain APIs to
+ * identify which power domain to operate upon.
+ *
+ * @dev: The device which implements the power domain.
+ * @id: The power domain ID within the provider.
+ * @priv: Private data corresponding to each power domain.
+ */
+struct power_domain {
+	struct udevice *dev;
+	unsigned long id;
+	void *priv;
+};
+
+/**
+ * power_domain_get - Get/request the power domain for a device.
+ *
+ * This looks up and requests a power domain. Each device is assumed to have
+ * a single (or, at least one) power domain associated with it somehow, and
+ * that domain, or the first/default domain. The mapping of client device to
+ * provider power domain may be via device-tree properties, board-provided
+ * mapping tables, or some other mechanism.
+ *
+ * @dev:	The client device.
+ * @power_domain	A pointer to a power domain struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+int power_domain_get(struct udevice *dev, struct power_domain *power_domain);
+#else
+static inline
+int power_domain_get(struct udevice *dev, struct power_domain *power_domain)
+{
+	return -ENOSYS;
+}
+#endif
+
+/**
+ * power_domain_get_by_index - Get the indexed power domain for a device.
+ *
+ * @dev:		The client device.
+ * @power_domain:	A pointer to a power domain struct to initialize.
+ * @index:		Power domain index to be powered on.
+ *
+ * @return 0 if OK, or a negative error code.
+ */
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+int power_domain_get_by_index(struct udevice *dev,
+			      struct power_domain *power_domain, int index);
+#else
+static inline
+int power_domain_get_by_index(struct udevice *dev,
+			      struct power_domain *power_domain, int index)
+{
+	return -ENOSYS;
+}
+#endif
+
+/**
+ * power_domain_free - Free a previously requested power domain.
+ *
+ * @power_domain:	A power domain struct that was previously successfully
+ *		requested by power_domain_get().
+ * @return 0 if OK, or a negative error code.
+ */
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+int power_domain_free(struct power_domain *power_domain);
+#else
+static inline int power_domain_free(struct power_domain *power_domain)
+{
+	return -ENOSYS;
+}
+#endif
+
+/**
+ * power_domain_on - Enable power to a power domain.
+ *
+ * @power_domain:	A power domain struct that was previously successfully
+ *		requested by power_domain_get().
+ * @return 0 if OK, or a negative error code.
+ */
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+int power_domain_on(struct power_domain *power_domain);
+#else
+static inline int power_domain_on(struct power_domain *power_domain)
+{
+	return -ENOSYS;
+}
+#endif
+
+/**
+ * power_domain_off - Disable power to a power domain.
+ *
+ * @power_domain:	A power domain struct that was previously successfully
+ *		requested by power_domain_get().
+ * @return 0 if OK, or a negative error code.
+ */
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+int power_domain_off(struct power_domain *power_domain);
+#else
+static inline int power_domain_off(struct power_domain *power_domain)
+{
+	return -ENOSYS;
+}
+#endif
+
+/**
+ * dev_power_domain_on - Enable power domains for a device .
+ *
+ * @dev:		The client device.
+ *
+ * @return 0 if OK, or a negative error code.
+ */
+#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
+	CONFIG_IS_ENABLED(POWER_DOMAIN)
+int dev_power_domain_on(struct udevice *dev);
+#else
+static inline int dev_power_domain_on(struct udevice *dev)
+{
+	return 0;
+}
+#endif
+
+/**
+ * dev_power_domain_off - Disable power domains for a device .
+ *
+ * @dev:		The client device.
+ *
+ * @return 0 if OK, or a negative error code.
+ */
+#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
+	CONFIG_IS_ENABLED(POWER_DOMAIN)
+int dev_power_domain_off(struct udevice *dev);
+#else
+static inline int dev_power_domain_off(struct udevice *dev)
+{
+	return 0;
+}
+#endif
+
+#endif
diff --git a/include/power/act8846_pmic.h b/include/power/act8846_pmic.h
new file mode 100644
index 0000000..acd0fd6
--- /dev/null
+++ b/include/power/act8846_pmic.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _PMIC_ACT8846_H_
+#define _PMIC_ACT8846_H_
+
+#include <asm/gpio.h>
+
+#define ACT8846_NUM_OF_REGS	12
+
+#define BUCK_VOL_MASK 0x3f
+#define LDO_VOL_MASK 0x3f
+
+#define BUCK_EN_MASK 0x80
+#define LDO_EN_MASK 0x80
+
+#define VOL_MIN_IDX 0x00
+#define VOL_MAX_IDX 0x3f
+
+struct  act8846_reg_table {
+	char	*name;
+	char	reg_ctl;
+	char	reg_vol;
+};
+
+struct pmic_act8846 {
+	struct pmic *pmic;
+	int node;	/*device tree node*/
+	struct gpio_desc pwr_hold;
+	struct udevice *dev;
+};
+
+#endif
diff --git a/include/power/as3722.h b/include/power/as3722.h
new file mode 100644
index 0000000..2782857
--- /dev/null
+++ b/include/power/as3722.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 NVIDIA Corporation
+ */
+
+#ifndef __POWER_AS3722_H__
+#define __POWER_AS3722_H__
+
+#define AS3722_GPIO_OUTPUT_VDDH (1 << 0)
+#define AS3722_GPIO_INVERT (1 << 1)
+
+#define AS3722_DEVICE_ID 0x0c
+#define AS3722_SD_VOLTAGE(n) (0x00 + (n))
+#define AS3722_LDO_VOLTAGE(n) (0x10 + (n))
+#define AS3722_SD_CONTROL 0x4d
+#define AS3722_LDO_CONTROL0 0x4e
+#define AS3722_LDO_CONTROL1 0x4f
+#define AS3722_ASIC_ID1 0x90
+#define AS3722_ASIC_ID2 0x91
+
+#define AS3722_GPIO_CONTROL(n) (0x08 + (n))
+#define AS3722_GPIO_SIGNAL_OUT 0x20
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDH (1 << 0)
+#define AS3722_GPIO_CONTROL_MODE_OUTPUT_VDDL (7 << 0)
+#define AS3722_GPIO_CONTROL_INVERT (1 << 7)
+
+int as3722_sd_set_voltage(struct udevice *dev, unsigned int sd, u8 value);
+int as3722_ldo_set_voltage(struct udevice *dev, unsigned int ldo, u8 value);
+
+#endif /* __POWER_AS3722_H__ */
diff --git a/include/power/battery.h b/include/power/battery.h
new file mode 100644
index 0000000..1e3d59d
--- /dev/null
+++ b/include/power/battery.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __POWER_BATTERY_H_
+#define __POWER_BATTERY_H_
+
+struct battery {
+	unsigned int version;
+	unsigned int state_of_chrg;
+	unsigned int time_to_empty;
+	unsigned int capacity;
+	unsigned int voltage_uV;
+
+	unsigned int state;
+};
+
+int power_bat_init(unsigned char bus);
+#endif /* __POWER_BATTERY_H_ */
diff --git a/include/power/bd71837.h b/include/power/bd71837.h
new file mode 100644
index 0000000..75e07e1
--- /dev/null
+++ b/include/power/bd71837.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2018 ROHM Semiconductors */
+
+#ifndef BD718XX_H_
+#define BD718XX_H_
+
+#define BD718XX_REGULATOR_DRIVER "bd718x7_regulator"
+
+enum {
+	ROHM_CHIP_TYPE_BD71837 = 0,
+	ROHM_CHIP_TYPE_BD71847,
+	ROHM_CHIP_TYPE_BD70528,
+	ROHM_CHIP_TYPE_AMOUNT
+};
+
+enum {
+	BD718XX_REV			= 0x00,
+	BD718XX_SWRESET			= 0x01,
+	BD718XX_I2C_DEV			= 0x02,
+	BD718XX_PWRCTRL0		= 0x03,
+	BD718XX_PWRCTRL1		= 0x04,
+	BD718XX_BUCK1_CTRL		= 0x05,
+	BD718XX_BUCK2_CTRL		= 0x06,
+	BD71837_BUCK3_CTRL		= 0x07,
+	BD71837_BUCK4_CTRL		= 0x08,
+	BD718XX_1ST_NODVS_BUCK_CTRL	= 0x09,
+	BD718XX_2ND_NODVS_BUCK_CTRL	= 0x0a,
+	BD718XX_3RD_NODVS_BUCK_CTRL	= 0x0b,
+	BD718XX_4TH_NODVS_BUCK_CTRL	= 0x0c,
+	BD718XX_BUCK1_VOLT_RUN		= 0x0d,
+	BD718XX_BUCK1_VOLT_IDLE		= 0x0e,
+	BD718XX_BUCK1_VOLT_SUSP		= 0x0f,
+	BD718XX_BUCK2_VOLT_RUN		= 0x10,
+	BD718XX_BUCK2_VOLT_IDLE		= 0x11,
+	BD71837_BUCK3_VOLT_RUN		= 0x12,
+	BD71837_BUCK4_VOLT_RUN		= 0x13,
+	BD718XX_1ST_NODVS_BUCK_VOLT	= 0x14,
+	BD718XX_2ND_NODVS_BUCK_VOLT	= 0x15,
+	BD718XX_3RD_NODVS_BUCK_VOLT	= 0x16,
+	BD718XX_4TH_NODVS_BUCK_VOLT	= 0x17,
+	BD718XX_LDO1_VOLT		= 0x18,
+	BD718XX_LDO2_VOLT		= 0x19,
+	BD718XX_LDO3_VOLT		= 0x1a,
+	BD718XX_LDO4_VOLT		= 0x1b,
+	BD718XX_LDO5_VOLT		= 0x1c,
+	BD718XX_LDO6_VOLT		= 0x1d,
+	BD71837_LDO7_VOLT		= 0x1e,
+	BD718XX_TRANS_COND0		= 0x1f,
+	BD718XX_TRANS_COND1		= 0x20,
+	BD718XX_VRFAULTEN		= 0x21,
+	BD718XX_MVRFLTMASK0		= 0x22,
+	BD718XX_MVRFLTMASK1		= 0x23,
+	BD718XX_MVRFLTMASK2		= 0x24,
+	BD718XX_RCVCFG			= 0x25,
+	BD718XX_RCVNUM			= 0x26,
+	BD718XX_PWRONCONFIG0		= 0x27,
+	BD718XX_PWRONCONFIG1		= 0x28,
+	BD718XX_RESETSRC		= 0x29,
+	BD718XX_MIRQ			= 0x2a,
+	BD718XX_IRQ			= 0x2b,
+	BD718XX_IN_MON			= 0x2c,
+	BD718XX_POW_STATE		= 0x2d,
+	BD718XX_OUT32K			= 0x2e,
+	BD718XX_REGLOCK			= 0x2f,
+	BD718XX_MUXSW_EN		= 0x30,
+	BD718XX_REG_OTPVER		= 0xff,
+	BD718XX_MAX_REGISTER		= 0x100,
+};
+
+#define BD718XX_REGLOCK_PWRSEQ		0x1
+#define BD718XX_REGLOCK_VREG		0x10
+
+#define BD718XX_BUCK_EN			0x01
+#define BD718XX_LDO_EN			0x40
+#define BD718XX_BUCK_SEL		0x02
+#define BD718XX_LDO_SEL			0x80
+
+#define DVS_BUCK_RUN_MASK		0x3f
+#define BD718XX_1ST_NODVS_BUCK_MASK	0x07
+#define BD718XX_3RD_NODVS_BUCK_MASK	0x07
+#define BD718XX_4TH_NODVS_BUCK_MASK	0x3f
+
+#define BD71847_BUCK3_MASK		0x07
+#define BD71847_BUCK3_RANGE_MASK	0xc0
+#define BD71847_BUCK4_MASK		0x03
+#define BD71847_BUCK4_RANGE_MASK	0x40
+
+#define BD71837_BUCK5_RANGE_MASK	0x80
+#define BD71837_BUCK6_MASK		0x03
+
+#define BD718XX_LDO1_MASK		0x03
+#define BD718XX_LDO1_RANGE_MASK		0x20
+#define BD718XX_LDO2_MASK		0x20
+#define BD718XX_LDO3_MASK		0x0f
+#define BD718XX_LDO4_MASK		0x0f
+#define BD718XX_LDO6_MASK		0x0f
+
+#define BD71837_LDO5_MASK		0x0f
+#define BD71847_LDO5_MASK		0x0f
+#define BD71847_LDO5_RANGE_MASK		0x20
+#define BD71837_LDO7_MASK		0x0f
+
+#endif
diff --git a/include/power/fg_battery_cell_params.h b/include/power/fg_battery_cell_params.h
new file mode 100644
index 0000000..b8c895b
--- /dev/null
+++ b/include/power/fg_battery_cell_params.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __FG_BATTERY_CELL_PARAMS_H_
+#define __FG_BATTERY_CELL_PARAMS_H_
+
+#if  defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TRATS)
+
+/* Cell characteristics - Exynos4 TRATS development board */
+/* Shall be written to addr 0x80h */
+u16 cell_character0[16] = {
+	0xA2A0,
+	0xB6E0,
+	0xB850,
+	0xBAD0,
+	0xBB20,
+	0xBB70,
+	0xBBC0,
+	0xBC20,
+	0xBC80,
+	0xBCE0,
+	0xBD80,
+	0xBE20,
+	0xC090,
+	0xC420,
+	0xC910,
+	0xD070
+};
+
+/* Shall be written to addr 0x90h */
+u16 cell_character1[16] = {
+	0x0090,
+	0x1A50,
+	0x02F0,
+	0x2060,
+	0x2060,
+	0x2E60,
+	0x26A0,
+	0x2DB0,
+	0x2DB0,
+	0x1870,
+	0x2A20,
+	0x16F0,
+	0x08F0,
+	0x0D40,
+	0x08C0,
+	0x08C0
+};
+
+/* Shall be written to addr 0xA0h */
+u16 cell_character2[16] = {
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100
+};
+#endif
+#endif /* __FG_BATTERY_CELL_PARAMS_H_ */
diff --git a/include/power/hi6553_pmic.h b/include/power/hi6553_pmic.h
new file mode 100644
index 0000000..d0abe20
--- /dev/null
+++ b/include/power/hi6553_pmic.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Linaro
+ * Peter Griffin <peter.griffin@linaro.org>
+ */
+
+#ifndef __HI6553_PMIC_H__
+#define __HI6553_PMIC_H__
+
+/* Registers */
+enum {
+	HI6553_VERSION_REG = 0x000,
+	HI6553_ENABLE2_LDO1_8 = 0x029,
+	HI6553_DISABLE2_LDO1_8,
+	HI6553_ONOFF_STATUS2_LDO1_8,
+	HI6553_ENABLE3_LDO9_16,
+	HI6553_DISABLE3_LDO9_16,
+	HI6553_ONOFF_STATUS3_LDO9_16,
+
+	HI6553_DISABLE6_XO_CLK = 0x036,
+	HI6553_PERI_EN_MARK = 0x040,
+	HI6553_BUCK2_REG1 = 0x04a,
+	HI6553_BUCK2_REG5 = 0x04e,
+	HI6553_BUCK2_REG6,
+
+	HI6553_BUCK3_REG3 = 0x054,
+	HI6553_BUCK3_REG5 = 0x056,
+	HI6553_BUCK3_REG6,
+	HI6553_BUCK4_REG2 = 0x05b,
+	HI6553_BUCK4_REG5 = 0x05e,
+	HI6553_BUCK4_REG6,
+
+	HI6553_CLK_TOP0 = 0x063,
+	HI6553_CLK_TOP3 = 0x066,
+	HI6553_CLK_TOP4,
+	HI6553_VSET_BUCK2_ADJ = 0x06d,
+	HI6553_VSET_BUCK3_ADJ,
+	HI6553_LDO7_REG_ADJ = 0x078,
+	HI6553_LDO10_REG_ADJ = 0x07b,
+	HI6553_LDO19_REG_ADJ = 0x084,
+	HI6553_LDO20_REG_ADJ,
+	HI6553_DR_LED_CTRL = 0x098,
+	HI6553_DR_OUT_CTRL,
+	HI6553_DR3_ISET,
+	HI6553_DR3_START_DEL,
+	HI6553_DR4_ISET,
+	HI6553_DR4_START_DEL,
+	HI6553_DR345_TIM_CONF0 = 0x0a0,
+	HI6553_NP_REG_ADJ1 = 0x0be,
+	HI6553_NP_REG_CHG = 0x0c0,
+	HI6553_BUCK01_CTRL2 = 0x0d9,
+	HI6553_BUCK0_CTRL1 = 0x0dd,
+	HI6553_BUCK0_CTRL5 = 0x0e1,
+	HI6553_BUCK0_CTRL7 = 0x0e3,
+	HI6553_BUCK1_CTRL1 = 0x0e8,
+	HI6553_BUCK1_CTRL5 = 0x0ec,
+	HI6553_BUCK1_CTRL7 = 0x0ef,
+	HI6553_CLK19M2_600_586_EN = 0x0fe,
+};
+
+#define HI6553_DISABLE6_XO_CLK_BB		(1 << 0)
+#define HI6553_DISABLE6_XO_CLK_CONN		(1 << 1)
+#define HI6553_DISABLE6_XO_CLK_NFC		(1 << 2)
+#define HI6553_DISABLE6_XO_CLK_RF1		(1 << 3)
+#define HI6553_DISABLE6_XO_CLK_RF2		(1 << 4)
+
+#define HI6553_LED_START_DELAY_TIME		0x00
+#define HI6553_LED_ELEC_VALUE			0x07
+#define HI6553_LED_LIGHT_TIME			0xf0
+#define HI6553_LED_GREEN_ENABLE			(1 << 1)
+#define HI6553_LED_OUT_CTRL			0x00
+
+#define HI6553_PMU_V300				0x30
+#define HI6553_PMU_V310				0x31
+
+int power_hi6553_init(u8 *base);
+
+#endif	/* __HI6553_PMIC_H__ */
diff --git a/include/power/lp873x.h b/include/power/lp873x.h
new file mode 100644
index 0000000..e0c0711
--- /dev/null
+++ b/include/power/lp873x.h
@@ -0,0 +1,19 @@
+#define	LP8732		0x0
+#define LP8733		0x1
+
+#define LP873X_LDO_NUM		2
+#define LP873X_BUCK_NUM		2
+
+/* Drivers name */
+#define LP873X_LDO_DRIVER	"lp873x_ldo"
+#define LP873X_BUCK_DRIVER	"lp873x_buck"
+
+#define LP873X_BUCK_VOLT_MASK		0xFF
+#define LP873X_BUCK_VOLT_MAX_HEX	0xFF
+#define LP873X_BUCK_VOLT_MAX		3360000
+#define LP873X_BUCK_MODE_MASK		0x1
+
+#define LP873X_LDO_VOLT_MASK    0x1F
+#define LP873X_LDO_VOLT_MAX_HEX 0x19
+#define LP873X_LDO_VOLT_MAX     3300000
+#define LP873X_LDO_MODE_MASK	0x1
diff --git a/include/power/lp87565.h b/include/power/lp87565.h
new file mode 100644
index 0000000..5160f5d
--- /dev/null
+++ b/include/power/lp87565.h
@@ -0,0 +1,12 @@
+#define LP87565	0x0
+#define LP87565_Q1	0x1
+
+#define LP87565_BUCK_NUM		6
+
+/* Drivers name */
+#define LP87565_BUCK_DRIVER	"lp87565_buck"
+
+#define LP87565_BUCK_VOLT_MASK		0xFF
+#define LP87565_BUCK_VOLT_MAX_HEX	0xFF
+#define LP87565_BUCK_VOLT_MAX		3360000
+#define LP87565_BUCK_MODE_MASK		0x80
diff --git a/include/power/ltc3676_pmic.h b/include/power/ltc3676_pmic.h
new file mode 100644
index 0000000..36c7971
--- /dev/null
+++ b/include/power/ltc3676_pmic.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2014 Gateworks Corporation
+ *  Tim Harvey <tharvey@gateworks.com>
+ */
+
+#ifndef __LTC3676_PMIC_H_
+#define __LTC3676_PMIC_H_
+
+/* LTC3676 registers */
+enum {
+	LTC3676_BUCK1	= 0x01,
+	LTC3676_BUCK2	= 0x02,
+	LTC3676_BUCK3	= 0x03,
+	LTC3676_BUCK4	= 0x04,
+	LTC3676_LDOA	= 0x05,
+	LTC3676_LDOB	= 0x06,
+	LTC3676_SQD1	= 0x07,
+	LTC3676_SQD2	= 0x08,
+	LTC3676_CNTRL	= 0x09,
+	LTC3676_DVB1A	= 0x0A,
+	LTC3676_DVB1B	= 0x0B,
+	LTC3676_DVB2A	= 0x0C,
+	LTC3676_DVB2B	= 0x0D,
+	LTC3676_DVB3A	= 0x0E,
+	LTC3676_DVB3B	= 0x0F,
+	LTC3676_DVB4A	= 0x10,
+	LTC3676_DVB4B	= 0x11,
+	LTC3676_MSKIRQ	= 0x12,
+	LTC3676_MSKPG	= 0x13,
+	LTC3676_USER	= 0x14,
+	LTC3676_HRST	= 0x1E,
+	LTC3676_CLIRQ	= 0x1F,
+	LTC3676_IRQSTAT	= 0x15,
+	LTC3676_PGSTATL	= 0x16,
+	LTC3676_PGSTATR	= 0x17,
+	LTC3676_NUM_OF_REGS = 0x20,
+};
+
+/*
+ * SW Configuration
+ */
+
+#define LTC3676_DVB_MASK	0x1f
+#define LTC3676_PGOOD_MASK	(1<<5)
+#define LTC3676_REF_SELA	(0<<5)
+#define LTC3676_REF_SELB	(1<<5)
+
+int power_ltc3676_init(unsigned char bus);
+#endif
diff --git a/include/power/max17042_fg.h b/include/power/max17042_fg.h
new file mode 100644
index 0000000..ec8377d
--- /dev/null
+++ b/include/power/max17042_fg.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __MAX17042_FG_H_
+#define __MAX17042_FG_H_
+
+/* MAX 17042 registers */
+enum {
+	MAX17042_STATUS         = 0x00,
+	MAX17042_SOCREP         = 0x06,
+	MAX17042_VCELL          = 0x09,
+	MAX17042_CURRENT        = 0x0A,
+	MAX17042_AVG_CURRENT	= 0x0B,
+	MAX17042_SOCMIX	= 0x0D,
+	MAX17042_SOCAV		= 0x0E,
+	MAX17042_DESIGN_CAP	= 0x18,
+	MAX17042_AVG_VCELL	= 0x19,
+	MAX17042_CONFIG	= 0x1D,
+	MAX17042_VERSION	= 0x21,
+	MAX17042_LEARNCFG       = 0x28,
+	MAX17042_FILTERCFG	= 0x29,
+	MAX17042_RELAXCFG	= 0x2A,
+	MAX17042_MISCCFG	= 0x2B,
+	MAX17042_CGAIN		= 0x2E,
+	MAX17042_COFF		= 0x2F,
+	MAX17042_RCOMP0	= 0x38,
+	MAX17042_TEMPCO	= 0x39,
+	MAX17042_FSTAT		= 0x3D,
+	MAX17042_MLOCKReg1	= 0x62,
+	MAX17042_MLOCKReg2	= 0x63,
+	MAX17042_MODEL1         = 0x80,
+	MAX17042_MODEL2         = 0x90,
+	MAX17042_MODEL3         = 0xA0,
+	MAX17042_VFOCV		= 0xFB,
+	MAX17042_VFSOC		= 0xFF,
+
+	FG_NUM_OF_REGS = 0x100,
+};
+
+#define RCOMP0			0x0060
+#define TempCo			0x1015
+
+
+#define MAX17042_POR (1 << 1)
+
+#define MODEL_UNLOCK1		0x0059
+#define MODEL_UNLOCK2		0x00c4
+#define MODEL_LOCK1		0x0000
+#define MODEL_LOCK2		0x0000
+
+#define MAX17042_I2C_ADDR	(0x6C >> 1)
+
+int power_fg_init(unsigned char bus);
+#endif /* __MAX17042_FG_H_ */
diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h
new file mode 100644
index 0000000..82fe350
--- /dev/null
+++ b/include/power/max77686_pmic.h
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ */
+
+#ifndef __MAX77686_H_
+#define __MAX77686_H_
+
+#include <power/pmic.h>
+
+enum {
+	MAX77686_REG_PMIC_ID		= 0x0,
+	MAX77686_REG_PMIC_INTSRC,
+	MAX77686_REG_PMIC_INT1,
+	MAX77686_REG_PMIC_INT2,
+	MAX77686_REG_PMIC_INT1MSK,
+	MAX77686_REG_PMIC_INT2MSK,
+
+	MAX77686_REG_PMIC_STATUS1,
+	MAX77686_REG_PMIC_STATUS2,
+
+	MAX77686_REG_PMIC_PWRON,
+	MAX77686_REG_PMIC_ONOFFDELAY,
+	MAX77686_REG_PMIC_MRSTB,
+
+	MAX77686_REG_PMIC_BUCK1CRTL	= 0x10,
+	MAX77686_REG_PMIC_BUCK1OUT,
+	MAX77686_REG_PMIC_BUCK2CTRL1,
+	MAX77686_REG_PMIC_BUCK234FREQ,
+	MAX77686_REG_PMIC_BUCK2DVS1,
+	MAX77686_REG_PMIC_BUCK2DVS2,
+	MAX77686_REG_PMIC_BUCK2DVS3,
+	MAX77686_REG_PMIC_BUCK2DVS4,
+	MAX77686_REG_PMIC_BUCK2DVS5,
+	MAX77686_REG_PMIC_BUCK2DVS6,
+	MAX77686_REG_PMIC_BUCK2DVS7,
+	MAX77686_REG_PMIC_BUCK2DVS8,
+	MAX77686_REG_PMIC_BUCK3CTRL,
+	MAX77686_REG_PMIC_BUCK3DVS1	= 0x1e,
+	MAX77686_REG_PMIC_BUCK3DVS2,
+	MAX77686_REG_PMIC_BUCK3DVS3,
+	MAX77686_REG_PMIC_BUCK3DVS4,
+	MAX77686_REG_PMIC_BUCK3DVS5,
+	MAX77686_REG_PMIC_BUCK3DVS6,
+	MAX77686_REG_PMIC_BUCK3DVS7,
+	MAX77686_REG_PMIC_BUCK3DVS8,
+	MAX77686_REG_PMIC_BUCK4CTRL1,
+	MAX77686_REG_PMIC_BUCK4DVS1	= 0x28,
+	MAX77686_REG_PMIC_BUCK4DVS2,
+	MAX77686_REG_PMIC_BUCK4DVS3,
+	MAX77686_REG_PMIC_BUCK4DVS4,
+	MAX77686_REG_PMIC_BUCK4DVS5,
+	MAX77686_REG_PMIC_BUCK4DVS6,
+	MAX77686_REG_PMIC_BUCK4DVS7,
+	MAX77686_REG_PMIC_BUCK4DVS8,
+	MAX77686_REG_PMIC_BUCK5CTRL,
+	MAX77686_REG_PMIC_BUCK5OUT,
+	MAX77686_REG_PMIC_BUCK6CRTL,
+	MAX77686_REG_PMIC_BUCK6OUT,
+	MAX77686_REG_PMIC_BUCK7CRTL,
+	MAX77686_REG_PMIC_BUCK7OUT,
+	MAX77686_REG_PMIC_BUCK8CRTL,
+	MAX77686_REG_PMIC_BUCK8OUT,
+	MAX77686_REG_PMIC_BUCK9CRTL,
+	MAX77686_REG_PMIC_BUCK9OUT,
+
+	MAX77686_REG_PMIC_LDO1CTRL1	= 0x40,
+	MAX77686_REG_PMIC_LDO2CTRL1,
+	MAX77686_REG_PMIC_LDO3CTRL1,
+	MAX77686_REG_PMIC_LDO4CTRL1,
+	MAX77686_REG_PMIC_LDO5CTRL1,
+	MAX77686_REG_PMIC_LDO6CTRL1,
+	MAX77686_REG_PMIC_LDO7CTRL1,
+	MAX77686_REG_PMIC_LDO8CTRL1,
+	MAX77686_REG_PMIC_LDO9CTRL1,
+	MAX77686_REG_PMIC_LDO10CTRL1,
+	MAX77686_REG_PMIC_LDO11CTRL1,
+	MAX77686_REG_PMIC_LDO12CTRL1,
+	MAX77686_REG_PMIC_LDO13CTRL1,
+	MAX77686_REG_PMIC_LDO14CTRL1,
+	MAX77686_REG_PMIC_LDO15CTRL1,
+	MAX77686_REG_PMIC_LDO16CTRL1,
+	MAX77686_REG_PMIC_LDO17CTRL1,
+	MAX77686_REG_PMIC_LDO18CTRL1,
+	MAX77686_REG_PMIC_LDO19CTRL1,
+	MAX77686_REG_PMIC_LDO20CTRL1,
+	MAX77686_REG_PMIC_LDO21CTRL1,
+	MAX77686_REG_PMIC_LDO22CTRL1,
+	MAX77686_REG_PMIC_LDO23CTRL1,
+	MAX77686_REG_PMIC_LDO24CTRL1,
+	MAX77686_REG_PMIC_LDO25CTRL1,
+	MAX77686_REG_PMIC_LDO26CTRL1,
+	MAX77686_REG_PMIC_LDO1CTRL2,
+	MAX77686_REG_PMIC_LDO2CTRL2,
+	MAX77686_REG_PMIC_LDO3CTRL2,
+	MAX77686_REG_PMIC_LDO4CTRL2,
+	MAX77686_REG_PMIC_LDO5CTRL2,
+	MAX77686_REG_PMIC_LDO6CTRL2,
+	MAX77686_REG_PMIC_LDO7CTRL2,
+	MAX77686_REG_PMIC_LDO8CTRL2,
+	MAX77686_REG_PMIC_LDO9CTRL2,
+	MAX77686_REG_PMIC_LDO10CTRL2,
+	MAX77686_REG_PMIC_LDO11CTRL2,
+	MAX77686_REG_PMIC_LDO12CTRL2,
+	MAX77686_REG_PMIC_LDO13CTRL2,
+	MAX77686_REG_PMIC_LDO14CTRL2,
+	MAX77686_REG_PMIC_LDO15CTRL2,
+	MAX77686_REG_PMIC_LDO16CTRL2,
+	MAX77686_REG_PMIC_LDO17CTRL2,
+	MAX77686_REG_PMIC_LDO18CTRL2,
+	MAX77686_REG_PMIC_LDO19CTRL2,
+	MAX77686_REG_PMIC_LDO20CTRL2,
+	MAX77686_REG_PMIC_LDO21CTRL2,
+	MAX77686_REG_PMIC_LDO22CTRL2,
+	MAX77686_REG_PMIC_LDO23CTRL2,
+	MAX77686_REG_PMIC_LDO24CTRL2,
+	MAX77686_REG_PMIC_LDO25CTRL2,
+	MAX77686_REG_PMIC_LDO26CTRL2,
+
+	MAX77686_REG_PMIC_BBAT		= 0x7e,
+	MAX77686_REG_PMIC_32KHZ,
+
+	MAX77686_NUM_OF_REGS,
+};
+
+/* I2C device address for pmic max77686 */
+#define MAX77686_I2C_ADDR	(0x12 >> 1)
+#define MAX77686_LDO_NUM	26
+#define MAX77686_BUCK_NUM	9
+
+/* Drivers name */
+#define MAX77686_LDO_DRIVER	"max77686_ldo"
+#define MAX77686_BUCK_DRIVER	"max77686_buck"
+
+enum {
+	REG_DISABLE = 0,
+	REG_ENABLE
+};
+
+enum {
+	LDO_OFF = 0,
+	LDO_ON,
+
+	DIS_LDO = (0x00 << 6),
+	EN_LDO = (0x3 << 6),
+};
+
+enum {
+	OPMODE_OFF = 0,
+	OPMODE_LPM,
+	OPMODE_STANDBY,
+	OPMODE_STANDBY_LPM,
+	OPMODE_ON,
+};
+
+#ifdef CONFIG_POWER
+int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
+int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
+int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV);
+int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
+#endif
+
+#define MAX77686_LDO_VOLT_MAX_HEX	0x3f
+#define MAX77686_LDO_VOLT_MASK		0x3f
+#define MAX77686_LDO_MODE_MASK		0xc0
+#define MAX77686_LDO_MODE_OFF		(0x00 << 0x06)
+#define MAX77686_LDO_MODE_LPM		(0x01 << 0x06)
+#define MAX77686_LDO_MODE_STANDBY	(0x01 << 0x06)
+#define MAX77686_LDO_MODE_STANDBY_LPM	(0x02 << 0x06)
+#define MAX77686_LDO_MODE_ON		(0x03 << 0x06)
+#define MAX77686_BUCK234_VOLT_MAX_HEX	0xff
+#define MAX77686_BUCK234_VOLT_MASK	0xff
+#define MAX77686_BUCK_VOLT_MAX_HEX	0x3f
+#define MAX77686_BUCK_VOLT_MASK		0x3f
+#define MAX77686_BUCK_MODE_MASK		0x03
+#define MAX77686_BUCK_MODE_SHIFT_1	0x00
+#define MAX77686_BUCK_MODE_SHIFT_2	0x04
+#define MAX77686_BUCK_MODE_OFF		0x00
+#define MAX77686_BUCK_MODE_STANDBY	0x01
+#define MAX77686_BUCK_MODE_LPM		0x02
+#define MAX77686_BUCK_MODE_ON		0x03
+
+/* For regulator hex<->volt conversion */
+#define MAX77686_LDO_UV_MIN		800000 /* Minimum LDO uV value */
+#define MAX77686_LDO_UV_LSTEP		25000 /* uV lower value step */
+#define MAX77686_LDO_UV_HSTEP		50000 /* uV higher value step */
+#define MAX77686_BUCK_UV_LMIN		600000 /* Lower minimun BUCK value */
+#define MAX77686_BUCK_UV_HMIN		750000 /* Higher minimun BUCK value */
+#define MAX77686_BUCK_UV_LSTEP		12500  /* uV lower value step */
+#define MAX77686_BUCK_UV_HSTEP		50000  /* uV higher value step */
+
+/* Buck1 1 volt value */
+#define MAX77686_BUCK1OUT_1V	0x5
+/* Buck1 1.05 volt value */
+#define MAX77686_BUCK1OUT_1_05V    0x6
+#define MAX77686_BUCK1CTRL_EN	(3 << 0)
+/* Buck2 1.3 volt value */
+#define MAX77686_BUCK2DVS1_1_3V	0x38
+#define MAX77686_BUCK2CTRL_ON	(1 << 4)
+/* Buck3 1.0125 volt value */
+#define MAX77686_BUCK3DVS1_1_0125V	0x21
+#define MAX77686_BUCK3CTRL_ON	(1 << 4)
+/* Buck4 1.2 volt value */
+#define MAX77686_BUCK4DVS1_1_2V	0x30
+#define MAX77686_BUCK4CTRL_ON	(1 << 4)
+/* LDO2 1.5 volt value */
+#define MAX77686_LD02CTRL1_1_5V	0x1c
+/* LDO3 1.8 volt value */
+#define MAX77686_LD03CTRL1_1_8V	0x14
+/* LDO5 1.8 volt value */
+#define MAX77686_LD05CTRL1_1_8V	0x14
+/* LDO10 1.8 volt value */
+#define MAX77686_LD10CTRL1_1_8V	0x14
+/*
+ * MAX77686_REG_PMIC_32KHZ set to 32KH CP
+ * output is activated
+ */
+#define MAX77686_32KHCP_EN	(1 << 1)
+/*
+ * MAX77686_REG_PMIC_BBAT set to
+ * Back up batery charger on and
+ * limit voltage setting to 3.5v
+ */
+#define MAX77686_BBCHOSTEN	(1 << 0)
+#define MAX77686_BBCVS_3_5V	(3 << 3)
+#endif /* __MAX77686_PMIC_H_ */
diff --git a/include/power/max77693_fg.h b/include/power/max77693_fg.h
new file mode 100644
index 0000000..c2ae622
--- /dev/null
+++ b/include/power/max77693_fg.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ */
+
+#ifndef __MAX77693_FG_H_
+#define __MAX77693_FG_H_
+
+/* MAX 77693 registers */
+enum {
+	MAX77693_STATUS		= 0x00,
+	MAX77693_SOCREP		= 0x06,
+	MAX77693_VCELL		= 0x09,
+	MAX77693_CURRENT	= 0x0A,
+	MAX77693_AVG_CURRENT	= 0x0B,
+	MAX77693_SOCMIX		= 0x0D,
+	MAX77693_SOCAV		= 0x0E,
+	MAX77693_DESIGN_CAP	= 0x18,
+	MAX77693_AVG_VCELL	= 0x19,
+	MAX77693_CONFIG		= 0x1D,
+	MAX77693_VERSION	= 0x21,
+	MAX77693_LEARNCFG	= 0x28,
+	MAX77693_FILTERCFG	= 0x29,
+	MAX77693_RELAXCFG	= 0x2A,
+	MAX77693_MISCCFG	= 0x2B,
+	MAX77693_CGAIN		= 0x2E,
+	MAX77693_COFF		= 0x2F,
+	MAX77693_RCOMP0		= 0x38,
+	MAX77693_TEMPCO		= 0x39,
+	MAX77693_FSTAT		= 0x3D,
+	MAX77693_VFOCV		= 0xEE,
+	MAX77693_VFSOC		= 0xFF,
+
+	FG_NUM_OF_REGS		= 0x100,
+};
+
+#define MAX77693_POR (1 << 1)
+
+#define MODEL_UNLOCK1		0x0059
+#define MODEL_UNLOCK2		0x00c4
+#define MODEL_LOCK1		0x0000
+#define MODEL_LOCK2		0x0000
+
+#define MAX77693_FUEL_I2C_ADDR	(0x6C >> 1)
+
+int power_fg_init(unsigned char bus);
+#endif /* __MAX77693_FG_H_ */
diff --git a/include/power/max77693_muic.h b/include/power/max77693_muic.h
new file mode 100644
index 0000000..c9afab2
--- /dev/null
+++ b/include/power/max77693_muic.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ */
+
+#ifndef __MAX77693_MUIC_H_
+#define __MAX77693_MUIC_H_
+
+#include <power/power_chrg.h>
+
+/*
+ * MUIC REGISTER
+ */
+
+#define MAX77693_MUIC_PREFIX	"max77693-muic:"
+
+/* MAX77693_MUIC_STATUS1 */
+#define MAX77693_MUIC_ADC_MASK	0x1F
+
+/* MAX77693_MUIC_STATUS2 */
+#define MAX77693_MUIC_CHG_NO		0x00
+#define MAX77693_MUIC_CHG_USB		0x01
+#define MAX77693_MUIC_CHG_USB_D		0x02
+#define MAX77693_MUIC_CHG_TA		0x03
+#define MAX77693_MUIC_CHG_TA_500	0x04
+#define MAX77693_MUIC_CHG_TA_1A		0x05
+#define MAX77693_MUIC_CHG_MASK		0x07
+
+/* MAX77693_MUIC_CONTROL1 */
+#define MAX77693_MUIC_CTRL1_DN1DP2	((0x1 << 3) | 0x1)
+#define MAX77693_MUIC_CTRL1_UT1UR2	((0x3 << 3) | 0x3)
+#define MAX77693_MUIC_CTRL1_ADN1ADP2	((0x4 << 3) | 0x4)
+#define MAX77693_MUIC_CTRL1_AUT1AUR2	((0x5 << 3) | 0x5)
+#define MAX77693_MUIC_CTRL1_MASK	0xC0
+
+#define MUIC_PATH_USB	0
+#define MUIC_PATH_UART	1
+
+#define MUIC_PATH_CP	0
+#define MUIC_PATH_AP	1
+
+enum muic_path {
+	MUIC_PATH_USB_CP,
+	MUIC_PATH_USB_AP,
+	MUIC_PATH_UART_CP,
+	MUIC_PATH_UART_AP,
+};
+
+/* MAX 777693 MUIC registers */
+enum {
+	MAX77693_MUIC_ID	= 0x00,
+	MAX77693_MUIC_INT1	= 0x01,
+	MAX77693_MUIC_INT2	= 0x02,
+	MAX77693_MUIC_INT3	= 0x03,
+	MAX77693_MUIC_STATUS1	= 0x04,
+	MAX77693_MUIC_STATUS2	= 0x05,
+	MAX77693_MUIC_STATUS3	= 0x06,
+	MAX77693_MUIC_INTMASK1	= 0x07,
+	MAX77693_MUIC_INTMASK2	= 0x08,
+	MAX77693_MUIC_INTMASK3	= 0x09,
+	MAX77693_MUIC_CDETCTRL	= 0x0A,
+	MAX77693_MUIC_CONTROL1	= 0x0C,
+	MAX77693_MUIC_CONTROL2	= 0x0D,
+	MAX77693_MUIC_CONTROL3	= 0x0E,
+
+	MUIC_NUM_OF_REGS	= 0x0F,
+};
+
+#define MAX77693_MUIC_I2C_ADDR	(0x4A >> 1)
+
+int power_muic_init(unsigned int bus);
+#endif /* __MAX77693_MUIC_H_ */
diff --git a/include/power/max77693_pmic.h b/include/power/max77693_pmic.h
new file mode 100644
index 0000000..9e0e05c
--- /dev/null
+++ b/include/power/max77693_pmic.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ */
+
+#ifndef __MAX77693_PMIC_H_
+#define __MAX77693_PMIC_H_
+
+#include <power/power_chrg.h>
+
+#define CHARGER_MIN_CURRENT 200
+#define CHARGER_MAX_CURRENT 2000
+
+#define MAX77693_CHG_PREFIX	"max77693-chg:"
+
+/* Registers */
+
+#define MAX77693_CHG_BASE	0xB0
+#define MAX77693_CHG_INT_OK	0xB2
+#define MAX77693_CHG_CNFG_00	0xB7
+#define MAX77693_CHG_CNFG_02	0xB9
+#define MAX77693_CHG_CNFG_06	0xBD
+#define MAX77693_SAFEOUT	0xC6
+
+#define PMIC_NUM_OF_REGS	0xC7
+
+#define MAX77693_CHG_DETBAT	(0x1 << 7)	/* MAX77693_CHG_INT_OK */
+#define MAX77693_CHG_MODE_ON	0x05		/* MAX77693_CHG_CNFG_00 */
+#define MAX77693_CHG_CC		0x3F		/* MAX77693_CHG_CNFG_02	*/
+#define MAX77693_CHG_LOCK	(0x0 << 2)	/* MAX77693_CHG_CNFG_06	*/
+#define MAX77693_CHG_UNLOCK	(0x3 << 2)	/* MAX77693_CHG_CNFG_06	*/
+
+#define MAX77693_ENSAFEOUT1	(1 << 6)
+#define MAX77693_ENSAFEOUT2	(1 << 7)
+
+#define MAX77693_PMIC_I2C_ADDR	(0xCC >> 1)
+
+int pmic_init_max77693(unsigned char bus);
+#endif /* __MAX77693_PMIC_H_ */
diff --git a/include/power/max77696_pmic.h b/include/power/max77696_pmic.h
new file mode 100644
index 0000000..69bb7da
--- /dev/null
+++ b/include/power/max77696_pmic.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *  Fabio Estevam <fabio.estevam@freescale.com>
+ */
+
+#ifndef __MAX77696_PMIC_H__
+#define __MAX77696_PMIC_H__
+
+#define CONFIG_POWER_MAX77696_I2C_ADDR	0x3C
+
+enum {
+	L01_CNFG1 =	0x43,
+	L01_CNFG2,
+	L02_CNFG1,
+	L02_CNFG2,
+	L03_CNFG1,
+	L03_CNFG2,
+	L04_CNFG1,
+	L04_CNFG2,
+	L05_CNFG1,
+	L05_CNFG2,
+	L06_CNFG1,
+	L06_CNFG2,
+	L07_CNFG1,
+	L07_CNFG2,
+	L08_CNFG1,
+	L08_CNFG2,
+	L09_CNFG1,
+	L09_CNFG2,
+	L10_CNFG1,
+	L10_CNFG2,
+	LDO_INT1,
+	LDO_INT2,
+	LDO_INT1M,
+	LDO_INT2M,
+	LDO_CNFG3,
+	SW1_CNTRL,
+	SW2_CNTRL,
+	SW3_CNTRL,
+	SW4_CNTRL,
+	EPDCNFG,
+	EPDINTS,
+	EPDINT,
+	EPDINTM,
+	EPDVCOM,
+	EPDVEE,
+	EPDVNEG,
+	EPDVPOS,
+	EPDVDDH,
+	EPDSEQ,
+	EPDOKINTS,
+	CID =	0x9c,
+	PMIC_NUM_OF_REGS,
+};
+
+int power_max77696_init(unsigned char bus);
+
+#endif
diff --git a/include/power/max8997_muic.h b/include/power/max8997_muic.h
new file mode 100644
index 0000000..e4ceab6
--- /dev/null
+++ b/include/power/max8997_muic.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __MAX8997_MUIC_H_
+#define __MAX8997_MUIC_H_
+
+#include <power/power_chrg.h>
+
+/* MAX8997_MUIC_STATUS2 */
+#define MAX8997_MUIC_CHG_NO	0x00
+#define MAX8997_MUIC_CHG_USB	0x01
+#define MAX8997_MUIC_CHG_USB_D	0x02
+#define MAX8997_MUIC_CHG_TA	0x03
+#define MAX8997_MUIC_CHG_TA_500 0x04
+#define MAX8997_MUIC_CHG_TA_1A	0x05
+#define MAX8997_MUIC_CHG_MASK	0x07
+
+/* MAX 8997 MUIC registers */
+enum {
+	MAX8997_MUIC_ID         = 0x00,
+	MAX8997_MUIC_INT1	= 0x01,
+	MAX8997_MUIC_INT2	= 0x02,
+	MAX8997_MUIC_INT3	= 0x03,
+	MAX8997_MUIC_STATUS1	= 0x04,
+	MAX8997_MUIC_STATUS2	= 0x05,
+	MAX8997_MUIC_STATUS3	= 0x06,
+	MAX8997_MUIC_INTMASK1	= 0x07,
+	MAX8997_MUIC_INTMASK2	= 0x08,
+	MAX8997_MUIC_INTMASK3	= 0x09,
+	MAX8997_MUIC_CDETCTRL	= 0x0A,
+	MAX8997_MUIC_CONTROL1	= 0x0C,
+	MAX8997_MUIC_CONTROL2	= 0x0D,
+	MAX8997_MUIC_CONTROL3	= 0x0E,
+
+	MUIC_NUM_OF_REGS = 0x0F,
+};
+
+#define MAX8997_MUIC_I2C_ADDR	(0x4A >> 1)
+
+int power_muic_init(unsigned int bus);
+#endif /* __MAX8997_MUIC_H_ */
diff --git a/include/power/max8997_pmic.h b/include/power/max8997_pmic.h
new file mode 100644
index 0000000..956eebb
--- /dev/null
+++ b/include/power/max8997_pmic.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2011 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __MAX8997_PMIC_H_
+#define __MAX8997_PMIC_H_
+
+/* MAX 8997 registers */
+enum {
+	MAX8997_REG_PMIC_ID0	= 0x00,
+	MAX8997_REG_PMIC_ID1	= 0x01,
+	MAX8997_REG_INTSRC	= 0x02,
+	MAX8997_REG_INT1	= 0x03,
+	MAX8997_REG_INT2	= 0x04,
+	MAX8997_REG_INT3	= 0x05,
+	MAX8997_REG_INT4	= 0x06,
+
+	MAX8997_REG_INT1MSK	= 0x08,
+	MAX8997_REG_INT2MSK	= 0x09,
+	MAX8997_REG_INT3MSK	= 0x0a,
+	MAX8997_REG_INT4MSK	= 0x0b,
+
+	MAX8997_REG_STATUS1	= 0x0d,
+	MAX8997_REG_STATUS2	= 0x0e,
+	MAX8997_REG_STATUS3	= 0x0f,
+	MAX8997_REG_STATUS4	= 0x10,
+
+	MAX8997_REG_MAINCON1	= 0x13,
+	MAX8997_REG_MAINCON2	= 0x14,
+	MAX8997_REG_BUCKRAMP	= 0x15,
+
+	MAX8997_REG_BUCK1CTRL	= 0x18,
+	MAX8997_REG_BUCK1DVS1	= 0x19,
+	MAX8997_REG_BUCK1DVS2	= 0x1a,
+	MAX8997_REG_BUCK1DVS3	= 0x1b,
+	MAX8997_REG_BUCK1DVS4	= 0x1c,
+	MAX8997_REG_BUCK1DVS5	= 0x1d,
+	MAX8997_REG_BUCK1DVS6	= 0x1e,
+	MAX8997_REG_BUCK1DVS7	= 0x1f,
+	MAX8997_REG_BUCK1DVS8	= 0x20,
+	MAX8997_REG_BUCK2CTRL	= 0x21,
+	MAX8997_REG_BUCK2DVS1	= 0x22,
+	MAX8997_REG_BUCK2DVS2	= 0x23,
+	MAX8997_REG_BUCK2DVS3	= 0x24,
+	MAX8997_REG_BUCK2DVS4	= 0x25,
+	MAX8997_REG_BUCK2DVS5	= 0x26,
+	MAX8997_REG_BUCK2DVS6	= 0x27,
+	MAX8997_REG_BUCK2DVS7	= 0x28,
+	MAX8997_REG_BUCK2DVS8	= 0x29,
+	MAX8997_REG_BUCK3CTRL	= 0x2a,
+	MAX8997_REG_BUCK3DVS	= 0x2b,
+	MAX8997_REG_BUCK4CTRL	= 0x2c,
+	MAX8997_REG_BUCK4DVS	= 0x2d,
+	MAX8997_REG_BUCK5CTRL	= 0x2e,
+	MAX8997_REG_BUCK5DVS1	= 0x2f,
+	MAX8997_REG_BUCK5DVS2	= 0x30,
+	MAX8997_REG_BUCK5DVS3	= 0x31,
+	MAX8997_REG_BUCK5DVS4	= 0x32,
+	MAX8997_REG_BUCK5DVS5	= 0x33,
+	MAX8997_REG_BUCK5DVS6	= 0x34,
+	MAX8997_REG_BUCK5DVS7	= 0x35,
+	MAX8997_REG_BUCK5DVS8	= 0x36,
+	MAX8997_REG_BUCK6CTRL	= 0x37,
+	MAX8997_REG_BUCK6BPSKIPCTRL	= 0x38,
+	MAX8997_REG_BUCK7CTRL	= 0x39,
+	MAX8997_REG_BUCK7DVS	= 0x3a,
+	MAX8997_REG_LDO1CTRL	= 0x3b,
+	MAX8997_REG_LDO2CTRL	= 0x3c,
+	MAX8997_REG_LDO3CTRL	= 0x3d,
+	MAX8997_REG_LDO4CTRL	= 0x3e,
+	MAX8997_REG_LDO5CTRL	= 0x3f,
+	MAX8997_REG_LDO6CTRL	= 0x40,
+	MAX8997_REG_LDO7CTRL	= 0x41,
+	MAX8997_REG_LDO8CTRL	= 0x42,
+	MAX8997_REG_LDO9CTRL	= 0x43,
+	MAX8997_REG_LDO10CTRL	= 0x44,
+	MAX8997_REG_LDO11CTRL	= 0x45,
+	MAX8997_REG_LDO12CTRL	= 0x46,
+	MAX8997_REG_LDO13CTRL	= 0x47,
+	MAX8997_REG_LDO14CTRL	= 0x48,
+	MAX8997_REG_LDO15CTRL	= 0x49,
+	MAX8997_REG_LDO16CTRL	= 0x4a,
+	MAX8997_REG_LDO17CTRL	= 0x4b,
+	MAX8997_REG_LDO18CTRL	= 0x4c,
+	MAX8997_REG_LDO21CTRL	= 0x4d,
+
+	MAX8997_REG_MBCCTRL1	= 0x50,
+	MAX8997_REG_MBCCTRL2	= 0x51,
+	MAX8997_REG_MBCCTRL3	= 0x52,
+	MAX8997_REG_MBCCTRL4	= 0x53,
+	MAX8997_REG_MBCCTRL5	= 0x54,
+	MAX8997_REG_MBCCTRL6	= 0x55,
+	MAX8997_REG_OTPCGHCVS	= 0x56,
+
+	MAX8997_REG_SAFEOUTCTRL = 0x5a,
+
+	MAX8997_REG_LBCNFG1	= 0x5e,
+	MAX8997_REG_LBCNFG2	= 0x5f,
+	MAX8997_REG_BBCCTRL	= 0x60,
+
+	MAX8997_REG_FLASH1_CUR	= 0x63, /* 0x63 ~ 0x6e for FLASH */
+	MAX8997_REG_FLASH2_CUR	= 0x64,
+	MAX8997_REG_MOVIE_CUR	= 0x65,
+	MAX8997_REG_GSMB_CUR	= 0x66,
+	MAX8997_REG_BOOST_CNTL	= 0x67,
+	MAX8997_REG_LEN_CNTL	= 0x68,
+	MAX8997_REG_FLASH_CNTL	= 0x69,
+	MAX8997_REG_WDT_CNTL	= 0x6a,
+	MAX8997_REG_MAXFLASH1	= 0x6b,
+	MAX8997_REG_MAXFLASH2	= 0x6c,
+	MAX8997_REG_FLASHSTATUS	= 0x6d,
+	MAX8997_REG_FLASHSTATUSMASK	= 0x6e,
+
+	MAX8997_REG_GPIOCNTL1	= 0x70,
+	MAX8997_REG_GPIOCNTL2	= 0x71,
+	MAX8997_REG_GPIOCNTL3	= 0x72,
+	MAX8997_REG_GPIOCNTL4	= 0x73,
+	MAX8997_REG_GPIOCNTL5	= 0x74,
+	MAX8997_REG_GPIOCNTL6	= 0x75,
+	MAX8997_REG_GPIOCNTL7	= 0x76,
+	MAX8997_REG_GPIOCNTL8	= 0x77,
+	MAX8997_REG_GPIOCNTL9	= 0x78,
+	MAX8997_REG_GPIOCNTL10	= 0x79,
+	MAX8997_REG_GPIOCNTL11	= 0x7a,
+	MAX8997_REG_GPIOCNTL12	= 0x7b,
+
+	MAX8997_REG_LDO1CONFIG	= 0x80,
+	MAX8997_REG_LDO2CONFIG	= 0x81,
+	MAX8997_REG_LDO3CONFIG	= 0x82,
+	MAX8997_REG_LDO4CONFIG	= 0x83,
+	MAX8997_REG_LDO5CONFIG	= 0x84,
+	MAX8997_REG_LDO6CONFIG	= 0x85,
+	MAX8997_REG_LDO7CONFIG	= 0x86,
+	MAX8997_REG_LDO8CONFIG	= 0x87,
+	MAX8997_REG_LDO9CONFIG	= 0x88,
+	MAX8997_REG_LDO10CONFIG	= 0x89,
+	MAX8997_REG_LDO11CONFIG	= 0x8a,
+	MAX8997_REG_LDO12CONFIG	= 0x8b,
+	MAX8997_REG_LDO13CONFIG	= 0x8c,
+	MAX8997_REG_LDO14CONFIG	= 0x8d,
+	MAX8997_REG_LDO15CONFIG	= 0x8e,
+	MAX8997_REG_LDO16CONFIG	= 0x8f,
+	MAX8997_REG_LDO17CONFIG	= 0x90,
+	MAX8997_REG_LDO18CONFIG	= 0x91,
+	MAX8997_REG_LDO21CONFIG	= 0x92,
+
+	MAX8997_REG_DVSOKTIMER1	= 0x97,
+	MAX8997_REG_DVSOKTIMER2	= 0x98,
+	MAX8997_REG_DVSOKTIMER4	= 0x99,
+	MAX8997_REG_DVSOKTIMER5	= 0x9a,
+
+	PMIC_NUM_OF_REGS = 0x9b,
+};
+
+#define ACTDISSAFEO1 (1 << 4)
+#define ACTDISSAFEO2 (1 << 5)
+#define ENSAFEOUT1 (1 << 6)
+#define ENSAFEOUT2 (1 << 7)
+
+#define ENBUCK (1 << 0)
+#define ACTIVE_DISCHARGE (1 << 3)
+#define GNSLCT (1 << 2)
+#define LDO_ADE (1 << 1)
+#define SAFEOUT_4_85V 0x00
+#define SAFEOUT_4_90V 0x01
+#define SAFEOUT_4_95V 0x02
+#define SAFEOUT_3_30V 0x03
+
+/* Charger */
+#define DETBAT                  (1 << 2)
+#define MBCICHFCSET             (1 << 4)
+#define MBCHOSTEN               (1 << 6)
+#define VCHGR_FC                (1 << 7)
+
+#define CHARGER_MIN_CURRENT 200
+#define CHARGER_MAX_CURRENT 950
+#define CHARGER_CURRENT_RESOLUTION 50
+
+#define MAX8997_I2C_ADDR        (0xCC >> 1)
+#define MAX8997_RTC_ADDR	(0x0C >> 1)
+#define MAX8997_MUIC_ADDR	(0x4A >> 1)
+#define MAX8997_FG_ADDR	(0x6C >> 1)
+
+enum {
+	LDO_OFF = 0,
+	LDO_ON = 1,
+
+	DIS_LDO = (0x00 << 6),
+	EN_LDO = (0x3 << 6),
+};
+
+#define MAX8997_LDO_MAX_VAL 0x3F
+unsigned char max8997_reg_ldo(int uV);
+#endif /* __MAX8997_PMIC_H_ */
diff --git a/include/power/max8998_pmic.h b/include/power/max8998_pmic.h
new file mode 100644
index 0000000..b1a87d6
--- /dev/null
+++ b/include/power/max8998_pmic.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2011 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __MAX8998_PMIC_H_
+#define __MAX8998_PMIC_H_
+
+/* MAX 8998 registers */
+enum {
+	MAX8998_REG_IRQ1,
+	MAX8998_REG_IRQ2,
+	MAX8998_REG_IRQ3,
+	MAX8998_REG_IRQ4,
+	MAX8998_REG_IRQM1,
+	MAX8998_REG_IRQM2,
+	MAX8998_REG_IRQM3,
+	MAX8998_REG_IRQM4,
+	MAX8998_REG_STATUS1,
+	MAX8998_REG_STATUS2,
+	MAX8998_REG_STATUSM1,
+	MAX8998_REG_STATUSM2,
+	MAX8998_REG_CHGR1,
+	MAX8998_REG_CHGR2,
+	MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
+	MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
+	MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
+	MAX8998_REG_ONOFF1,
+	MAX8998_REG_ONOFF2,
+	MAX8998_REG_ONOFF3,
+	MAX8998_REG_ONOFF4,
+	MAX8998_REG_BUCK1_VOLTAGE1,
+	MAX8998_REG_BUCK1_VOLTAGE2,
+	MAX8998_REG_BUCK1_VOLTAGE3,
+	MAX8998_REG_BUCK1_VOLTAGE4,
+	MAX8998_REG_BUCK2_VOLTAGE1,
+	MAX8998_REG_BUCK2_VOLTAGE2,
+	MAX8998_REG_BUCK3,
+	MAX8998_REG_BUCK4,
+	MAX8998_REG_LDO2_LDO3,
+	MAX8998_REG_LDO4,
+	MAX8998_REG_LDO5,
+	MAX8998_REG_LDO6,
+	MAX8998_REG_LDO7,
+	MAX8998_REG_LDO8_LDO9,
+	MAX8998_REG_LDO10_LDO11,
+	MAX8998_REG_LDO12,
+	MAX8998_REG_LDO13,
+	MAX8998_REG_LDO14,
+	MAX8998_REG_LDO15,
+	MAX8998_REG_LDO16,
+	MAX8998_REG_LDO17,
+	MAX8998_REG_BKCHR,
+	MAX8998_REG_LBCNFG1,
+	MAX8998_REG_LBCNFG2,
+	PMIC_NUM_OF_REGS,
+};
+
+#define MAX8998_LDO3		(1 << 2)
+#define MAX8998_LDO4		(1 << 1)
+#define MAX8998_LDO7		(1 << 6)
+#define MAX8998_LDO8		(1 << 5)
+#define MAX8998_LDO17		(1 << 4)
+#define MAX8998_SAFEOUT1	(1 << 4)
+
+#define MAX8998_I2C_ADDR        (0xCC >> 1)
+
+enum { LDO_OFF, LDO_ON };
+
+#endif /* __MAX8998_PMIC_H_ */
diff --git a/include/power/mc34vr500_pmic.h b/include/power/mc34vr500_pmic.h
new file mode 100644
index 0000000..d2edda6
--- /dev/null
+++ b/include/power/mc34vr500_pmic.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
+ */
+
+#ifndef __MC34VR500_H_
+#define __MC34VR500_H_
+
+#include <power/pmic.h>
+
+#define MC34VR500_I2C_ADDR	0x08
+
+/* Drivers name */
+#define MC34VR500_REGULATOR_DRIVER	"mc34vr500_regulator"
+
+/* Register map */
+enum {
+	MC34VR500_DEVICEID		= 0x00,
+
+	MC34VR500_SILICONREVID		= 0x03,
+	MC34VR500_FABID,
+	MC34VR500_INTSTAT0,
+	MC34VR500_INTMASK0,
+	MC34VR500_INTSENSE0,
+	MC34VR500_INTSTAT1,
+	MC34VR500_INTMASK1,
+	MC34VR500_INTSENSE1,
+
+	MC34VR500_INTSTAT4		= 0x11,
+	MC34VR500_INTMASK4,
+	MC34VR500_INTSENSE4,
+
+	MC34VR500_PWRCTL		= 0x1B,
+
+	MC34VR500_SW1VOLT		= 0x2E,
+	MC34VR500_SW1STBY,
+	MC34VR500_SW1OFF,
+	MC34VR500_SW1MODE,
+	MC34VR500_SW1CONF,
+	MC34VR500_SW2VOLT,
+	MC34VR500_SW2STBY,
+	MC34VR500_SW2OFF,
+	MC34VR500_SW2MODE,
+	MC34VR500_SW2CONF,
+
+	MC34VR500_SW3VOLT		= 0x3C,
+	MC34VR500_SW3STBY,
+	MC34VR500_SW3OFF,
+	MC34VR500_SW3MODE,
+	MC34VR500_SW3CONF,
+
+	MC34VR500_SW4VOLT		= 0x4A,
+	MC34VR500_SW4STBY,
+	MC34VR500_SW4OFF,
+	MC34VR500_SW4MODE,
+	MC34VR500_SW4CONF,
+
+	MC34VR500_REFOUTCRTRL		= 0x6A,
+
+	MC34VR500_LDO1CTL		= 0x6D,
+	MC34VR500_LDO2CTL,
+	MC34VR500_LDO3CTL,
+	MC34VR500_LDO4CTL,
+	MC34VR500_LDO5CTL,
+
+	MC34VR500_PAGE_REGISTER		= 0x7F,
+
+	/* Internal RAM */
+	MC34VR500_SW1_VOLT		= 0xA8,
+	MC34VR500_SW1_SEQ,
+	MC34VR500_SW1_CONFIG,
+
+	MC34VR500_SW2_VOLT		= 0xAC,
+	MC34VR500_SW2_SEQ,
+	MC34VR500_SW2_CONFIG,
+
+	MC34VR500_SW3_VOLT		= 0xB0,
+	MC34VR500_SW3_SEQ,
+	MC34VR500_SW3_CONFIG,
+
+	MC34VR500_SW4_VOLT		= 0xB8,
+	MC34VR500_SW4_SEQ,
+	MC34VR500_SW4_CONFIG,
+
+	MC34VR500_REFOUT_SEQ		= 0xC4,
+
+	MC34VR500_LDO1_VOLT		= 0xCC,
+	MC34VR500_LDO1_SEQ,
+
+	MC34VR500_LDO2_VOLT		= 0xD0,
+	MC34VR500_LDO2_SEQ,
+
+	MC34VR500_LDO3_VOLT		= 0xD4,
+	MC34VR500_LDO3_SEQ,
+
+	MC34VR500_LDO4_VOLT		= 0xD8,
+	MC34VR500_LDO4_SEQ,
+
+	MC34VR500_LDO5_VOLT		= 0xDC,
+	MC34VR500_LDO5_SEQ,
+
+	MC34VR500_PU_CONFIG1		= 0xE0,
+
+	MC34VR500_TBB_POR		= 0xE4,
+
+	MC34VR500_PWRGD_EN		= 0xE8,
+
+	MC34VR500_NUM_OF_REGS,
+};
+
+/* Registor offset based on SWxVOLT register */
+#define MC34VR500_VOLT_OFFSET	0
+#define MC34VR500_STBY_OFFSET	1
+#define MC34VR500_OFF_OFFSET	2
+#define MC34VR500_MODE_OFFSET	3
+#define MC34VR500_CONF_OFFSET	4
+
+#define SW_MODE_MASK	0xf
+#define SW_MODE_SHIFT	0
+
+#define LDO_VOL_MASK	0xf
+#define LDO_EN		(1 << 4)
+#define LDO_MODE_SHIFT	4
+#define LDO_MODE_MASK	(1 << 4)
+#define LDO_MODE_OFF	0
+#define LDO_MODE_ON	1
+
+#define REFOUTEN	(1 << 4)
+
+/*
+ * Regulator Mode Control
+ *
+ * OFF: The regulator is switched off and the output voltage is discharged.
+ * PFM: In this mode, the regulator is always in PFM mode, which is useful
+ *      at light loads for optimized efficiency.
+ * PWM: In this mode, the regulator is always in PWM mode operation
+ *	regardless of load conditions.
+ * APS: In this mode, the regulator moves automatically between pulse
+ *	skipping mode and PWM mode depending on load conditions.
+ *
+ * SWxMODE[3:0]
+ * Normal Mode  |  Standby Mode	|      value
+ *   OFF		OFF		0x0
+ *   PWM		OFF		0x1
+ *   PFM		OFF		0x3
+ *   APS		OFF		0x4
+ *   PWM		PWM		0x5
+ *   PWM		APS		0x6
+ *   APS		APS		0x8
+ *   APS		PFM		0xc
+ *   PWM		PFM		0xd
+ */
+#define OFF_OFF		0x0
+#define PWM_OFF		0x1
+#define PFM_OFF		0x3
+#define APS_OFF		0x4
+#define PWM_PWM		0x5
+#define PWM_APS		0x6
+#define APS_APS		0x8
+#define APS_PFM		0xc
+#define PWM_PFM		0xd
+
+enum swx {
+	SW1 = 0,
+	SW2,
+	SW3,
+	SW4,
+};
+
+int mc34vr500_get_sw_volt(uint8_t sw);
+int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt);
+int power_mc34vr500_init(unsigned char bus);
+#endif /* __MC34VR500_PMIC_H_ */
diff --git a/include/power/palmas.h b/include/power/palmas.h
new file mode 100644
index 0000000..df5f15c
--- /dev/null
+++ b/include/power/palmas.h
@@ -0,0 +1,26 @@
+#define	PALMAS		0x0
+#define TPS659038	0x1
+#define TPS65917	0x2
+
+/* I2C device address for pmic palmas */
+#define PALMAS_I2C_ADDR	(0x12 >> 1)
+#define PALMAS_LDO_NUM		11
+#define PALMAS_SMPS_NUM	8
+
+/* Drivers name */
+#define PALMAS_LDO_DRIVER     "palmas_ldo"
+#define PALMAS_SMPS_DRIVER    "palmas_smps"
+
+#define PALMAS_SMPS_VOLT_MASK		0x7F
+#define PALMAS_SMPS_RANGE_MASK		0x80
+#define PALMAS_SMPS_VOLT_MAX_HEX	0x7F
+#define PALMAS_SMPS_VOLT_MAX		3300000
+#define PALMAS_SMPS_MODE_MASK		0x3
+#define	PALMAS_SMPS_STATUS_MASK		0x30
+
+#define PALMAS_LDO_VOLT_MASK    0x3F
+#define PALMAS_LDO_VOLT_MAX_HEX 0x3F
+#define PALMAS_LDO_VOLT_MAX     3300000
+#define PALMAS_LDO_MODE_MASK	0x1
+#define PALMAS_LDO_STATUS_MASK	0x10
+#define PALMAS_LDO_BYPASS_EN	0x40
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
new file mode 100644
index 0000000..f4383ed
--- /dev/null
+++ b/include/power/pfuze100_pmic.h
@@ -0,0 +1,258 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2014 Gateworks Corporation
+ *  Tim Harvey <tharvey@gateworks.com>
+ */
+
+#ifndef __PFUZE100_PMIC_H_
+#define __PFUZE100_PMIC_H_
+
+/* Device ID */
+enum {PFUZE100 = 0x10, PFUZE200 = 0x11, PFUZE3000 = 0x30};
+
+#define PFUZE100_REGULATOR_DRIVER	"pfuze100_regulator"
+
+/* PFUZE100 registers */
+enum {
+	PFUZE100_DEVICEID	= 0x00,
+	PFUZE100_REVID		= 0x03,
+	PFUZE100_FABID		= 0x04,
+
+	PFUZE100_SW1ABVOL	= 0x20,
+	PFUZE100_SW1ABSTBY	= 0x21,
+	PFUZE100_SW1ABOFF	= 0x22,
+	PFUZE100_SW1ABMODE	= 0x23,
+	PFUZE100_SW1ABCONF	= 0x24,
+	PFUZE100_SW1CVOL	= 0x2e,
+	PFUZE100_SW1CSTBY	= 0x2f,
+	PFUZE100_SW1COFF	= 0x30,
+	PFUZE100_SW1CMODE	= 0x31,
+	PFUZE100_SW1CCONF	= 0x32,
+	PFUZE100_SW2VOL		= 0x35,
+	PFUZE100_SW2STBY	= 0x36,
+	PFUZE100_SW2OFF		= 0x37,
+	PFUZE100_SW2MODE	= 0x38,
+	PFUZE100_SW2CONF	= 0x39,
+	PFUZE100_SW3AVOL	= 0x3c,
+	PFUZE100_SW3ASTBY	= 0x3D,
+	PFUZE100_SW3AOFF	= 0x3E,
+	PFUZE100_SW3AMODE	= 0x3F,
+	PFUZE100_SW3ACONF	= 0x40,
+	PFUZE100_SW3BVOL	= 0x43,
+	PFUZE100_SW3BSTBY	= 0x44,
+	PFUZE100_SW3BOFF	= 0x45,
+	PFUZE100_SW3BMODE	= 0x46,
+	PFUZE100_SW3BCONF	= 0x47,
+	PFUZE100_SW4VOL		= 0x4a,
+	PFUZE100_SW4STBY	= 0x4b,
+	PFUZE100_SW4OFF		= 0x4c,
+	PFUZE100_SW4MODE	= 0x4d,
+	PFUZE100_SW4CONF	= 0x4e,
+	PFUZE100_SWBSTCON1	= 0x66,
+	PFUZE100_VREFDDRCON	= 0x6a,
+	PFUZE100_VSNVSVOL	= 0x6b,
+	PFUZE100_VGEN1VOL	= 0x6c,
+	PFUZE100_VGEN2VOL	= 0x6d,
+	PFUZE100_VGEN3VOL	= 0x6e,
+	PFUZE100_VGEN4VOL	= 0x6f,
+	PFUZE100_VGEN5VOL	= 0x70,
+	PFUZE100_VGEN6VOL	= 0x71,
+
+	PFUZE100_NUM_OF_REGS	= 0x7f,
+};
+
+/* Registor offset based on VOLT register */
+#define PFUZE100_VOL_OFFSET	0
+#define PFUZE100_STBY_OFFSET	1
+#define PFUZE100_OFF_OFFSET	2
+#define PFUZE100_MODE_OFFSET	3
+#define PFUZE100_CONF_OFFSET	4
+
+/*
+ * Buck Regulators
+ */
+
+#define PFUZE100_SW1ABC_SETP(x)	((x - 3000) / 250)
+
+/* SW1A/B/C Output Voltage Configuration */
+#define SW1x_0_300V 0
+#define SW1x_0_325V 1
+#define SW1x_0_350V 2
+#define SW1x_0_375V 3
+#define SW1x_0_400V 4
+#define SW1x_0_425V 5
+#define SW1x_0_450V 6
+#define SW1x_0_475V 7
+#define SW1x_0_500V 8
+#define SW1x_0_525V 9
+#define SW1x_0_550V 10
+#define SW1x_0_575V 11
+#define SW1x_0_600V 12
+#define SW1x_0_625V 13
+#define SW1x_0_650V 14
+#define SW1x_0_675V 15
+#define SW1x_0_700V 16
+#define SW1x_0_725V 17
+#define SW1x_0_750V 18
+#define SW1x_0_775V 19
+#define SW1x_0_800V 20
+#define SW1x_0_825V 21
+#define SW1x_0_850V 22
+#define SW1x_0_875V 23
+#define SW1x_0_900V 24
+#define SW1x_0_925V 25
+#define SW1x_0_950V 26
+#define SW1x_0_975V 27
+#define SW1x_1_000V 28
+#define SW1x_1_025V 29
+#define SW1x_1_050V 30
+#define SW1x_1_075V 31
+#define SW1x_1_100V 32
+#define SW1x_1_125V 33
+#define SW1x_1_150V 34
+#define SW1x_1_175V 35
+#define SW1x_1_200V 36
+#define SW1x_1_225V 37
+#define SW1x_1_250V 38
+#define SW1x_1_275V 39
+#define SW1x_1_300V 40
+#define SW1x_1_325V 41
+#define SW1x_1_350V 42
+#define SW1x_1_375V 43
+#define SW1x_1_400V 44
+#define SW1x_1_425V 45
+#define SW1x_1_450V 46
+#define SW1x_1_475V 47
+#define SW1x_1_500V 48
+#define SW1x_1_525V 49
+#define SW1x_1_550V 50
+#define SW1x_1_575V 51
+#define SW1x_1_600V 52
+#define SW1x_1_625V 53
+#define SW1x_1_650V 54
+#define SW1x_1_675V 55
+#define SW1x_1_700V 56
+#define SW1x_1_725V 57
+#define SW1x_1_750V 58
+#define SW1x_1_775V 59
+#define SW1x_1_800V 60
+#define SW1x_1_825V 61
+#define SW1x_1_850V 62
+#define SW1x_1_875V 63
+
+#define SW1x_NORMAL_MASK  0x3f
+#define SW1x_STBY_MASK    0x3f
+#define SW1x_OFF_MASK     0x3f
+
+#define SW_MODE_MASK	0xf
+#define SW_MODE_SHIFT	0
+
+#define SW1xCONF_DVSSPEED_MASK 0xc0
+#define SW1xCONF_DVSSPEED_2US  0x00
+#define SW1xCONF_DVSSPEED_4US  0x40
+#define SW1xCONF_DVSSPEED_8US  0x80
+#define SW1xCONF_DVSSPEED_16US 0xc0
+
+/*
+ * LDO Configuration
+ */
+
+/* VGEN1/2 Voltage Configuration */
+#define LDOA_0_80V	0
+#define LDOA_0_85V	1
+#define LDOA_0_90V	2
+#define LDOA_0_95V	3
+#define LDOA_1_00V	4
+#define LDOA_1_05V	5
+#define LDOA_1_10V	6
+#define LDOA_1_15V	7
+#define LDOA_1_20V	8
+#define LDOA_1_25V	9
+#define LDOA_1_30V	10
+#define LDOA_1_35V	11
+#define LDOA_1_40V	12
+#define LDOA_1_45V	13
+#define LDOA_1_50V	14
+#define LDOA_1_55V	15
+
+/* VGEN3/4/5/6 Voltage Configuration */
+#define LDOB_1_80V	0
+#define LDOB_1_90V	1
+#define LDOB_2_00V	2
+#define LDOB_2_10V	3
+#define LDOB_2_20V	4
+#define LDOB_2_30V	5
+#define LDOB_2_40V	6
+#define LDOB_2_50V	7
+#define LDOB_2_60V	8
+#define LDOB_2_70V	9
+#define LDOB_2_80V	10
+#define LDOB_2_90V	11
+#define LDOB_3_00V	12
+#define LDOB_3_10V	13
+#define LDOB_3_20V	14
+#define LDOB_3_30V	15
+
+#define LDO_VOL_MASK	0xf
+#define LDO_EN		(1 << 4)
+#define LDO_MODE_SHIFT	4
+#define LDO_MODE_MASK	(1 << 4)
+#define LDO_MODE_OFF	0
+#define LDO_MODE_ON	1
+
+#define VREFDDRCON_EN	(1 << 4)
+/*
+ * Boost Regulator
+ */
+
+/* SWBST Output Voltage */
+#define SWBST_5_00V	0
+#define SWBST_5_05V	1
+#define SWBST_5_10V	2
+#define SWBST_5_15V	3
+
+#define SWBST_VOL_MASK	0x3
+#define SWBST_MODE_MASK	0xC
+#define SWBST_MODE_SHIFT 0x2
+#define SWBST_MODE_OFF	0
+#define SWBST_MODE_PFM	1
+#define SWBST_MODE_AUTO	2
+#define SWBST_MODE_APS	3
+
+/*
+ * Regulator Mode Control
+ *
+ * OFF: The regulator is switched off and the output voltage is discharged.
+ * PFM: In this mode, the regulator is always in PFM mode, which is useful
+ *      at light loads for optimized efficiency.
+ * PWM: In this mode, the regulator is always in PWM mode operation
+ *	regardless of load conditions.
+ * APS: In this mode, the regulator moves automatically between pulse
+ *	skipping mode and PWM mode depending on load conditions.
+ *
+ * SWxMODE[3:0]
+ * Normal Mode  |  Standby Mode	|      value
+ *   OFF		OFF		0x0
+ *   PWM		OFF		0x1
+ *   PFM		OFF		0x3
+ *   APS		OFF		0x4
+ *   PWM		PWM		0x5
+ *   PWM		APS		0x6
+ *   APS		APS		0x8
+ *   APS		PFM		0xc
+ *   PWM		PFM		0xd
+ */
+#define OFF_OFF		0x0
+#define PWM_OFF		0x1
+#define PFM_OFF		0x3
+#define APS_OFF		0x4
+#define PWM_PWM		0x5
+#define PWM_APS		0x6
+#define APS_APS		0x8
+#define APS_PFM		0xc
+#define PWM_PFM		0xd
+
+#define SWITCH_SIZE	0x7
+
+int power_pfuze100_init(unsigned char bus);
+#endif
diff --git a/include/power/pfuze3000_pmic.h b/include/power/pfuze3000_pmic.h
new file mode 100644
index 0000000..b836d67
--- /dev/null
+++ b/include/power/pfuze3000_pmic.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2015 Freescale Semiconductor, Inc
+ *  Peng Fan <Peng.Fan@freescale.com>
+ */
+#ifndef __PFUZE3000_PMIC_H_
+#define __PFUZE3000_PMIC_H_
+
+/* PFUZE3000 registers */
+enum {
+	PFUZE3000_DEVICEID	= 0x00,
+
+	PFUZE3000_REVID		= 0x03,
+	PFUZE3000_FABID		= 0x04,
+	PFUZE3000_INTSTAT0	= 0x05,
+	PFUZE3000_INTMASK0	= 0x06,
+	PFUZE3000_INTSENSE0	= 0x07,
+	PFUZE3000_INTSTAT1	= 0x08,
+	PFUZE3000_INTMASK1	= 0x09,
+	PFUZE3000_INTSENSE1	= 0x0A,
+
+	PFUZE3000_INTSTAT3	= 0x0E,
+	PFUZE3000_INTMASK3	= 0x0F,
+	PFUZE3000_INTSENSE3	= 0x10,
+	PFUZE3000_INTSTAT4	= 0x11,
+	PFUZE3000_INTMASK4	= 0x12,
+	PFUZE3000_INTSENSE4	= 0x13,
+
+	PFUZE3000_COINCTL	= 0x1A,
+	PFUZE3000_PWRCTL	= 0x1B,
+	PFUZE3000_MEMA		= 0x1C,
+	PFUZE3000_MEMB		= 0x1D,
+	PFUZE3000_MEMC		= 0x1E,
+	PFUZE3000_MEMD		= 0x1F,
+
+	PFUZE3000_SW1AVOLT	= 0x20,
+	PFUZE3000_SW1ASTBY	= 0x21,
+	PFUZE3000_SW1AOFF	= 0x22,
+	PFUZE3000_SW1AMODE	= 0x23,
+	PFUZE3000_SW1ACONF	= 0x24,
+
+	PFUZE3000_SW1BVOLT	= 0x2E,
+	PFUZE3000_SW1BSTBY	= 0x2F,
+	PFUZE3000_SW1BOFF	= 0x30,
+	PFUZE3000_SW1BMODE	= 0x31,
+	PFUZE3000_SW1BCONF	= 0x32,
+
+	PFUZE3000_SW2VOLT	= 0x35,
+	PFUZE3000_SW2STBY	= 0x36,
+	PFUZE3000_SW2OFF	= 0x37,
+	PFUZE3000_SW2MODE	= 0x38,
+	PFUZE3000_SW2CONF	= 0x39,
+
+	PFUZE3000_SW3VOLT	= 0x3C,
+	PFUZE3000_SW3STBY	= 0x3D,
+	PFUZE3000_SW3OFF	= 0x3E,
+	PFUZE3000_SW3MODE	= 0x3F,
+	PFUZE3000_SW3CONF	= 0x40,
+
+	PFUZE3000_SWBSTCTL	= 0x66,
+
+	PFUZE3000_LDOGCTL	= 0x69,
+	PFUZE3000_VREFDDRCTL	= 0x6A,
+	PFUZE3000_VSNVSCTL	= 0x6B,
+	PFUZE3000_VLDO1CTL	= 0x6C,
+	PFUZE3000_VLDO2CTL	= 0x6D,
+	PFUZE3000_VCC_SDCTL	= 0x6E,
+	PFUZE3000_V33CTL	= 0x6F,
+	PFUZE3000_VLDO3CTL	= 0x70,
+	PFUZE3000_VLD4CTL	= 0x71,
+
+	PFUZE3000_NUM_OF_REGS	= 0x100,
+};
+
+int power_pfuze3000_init(unsigned char bus);
+
+/* Voltage Configuration */
+#define PFUZE3000_SW1AB_SETP(x)    ((x - 7000) / 250)
+#define PFUZE3000_SW3_SETP(x)      ((x - 9000) / 500)
+#define PFUZE3000_VLDO_SETP(x)     ((x - 8000) / 500)
+
+#endif
diff --git a/include/power/pmic.h b/include/power/pmic.h
new file mode 100644
index 0000000..be9de6b
--- /dev/null
+++ b/include/power/pmic.h
@@ -0,0 +1,330 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2014-2015 Samsung Electronics
+ *  Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ *  Copyright (C) 2011-2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __CORE_PMIC_H_
+#define __CORE_PMIC_H_
+
+#include <dm/ofnode.h>
+#include <i2c.h>
+#include <linux/list.h>
+#include <power/power_chrg.h>
+
+enum { PMIC_I2C, PMIC_SPI, PMIC_NONE};
+
+#ifdef CONFIG_POWER
+enum { I2C_PMIC, I2C_NUM, };
+enum { PMIC_READ, PMIC_WRITE, };
+enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, };
+
+enum {
+	PMIC_CHARGER_DISABLE,
+	PMIC_CHARGER_ENABLE,
+};
+
+struct p_i2c {
+	unsigned char addr;
+	unsigned char *buf;
+	unsigned char tx_num;
+};
+
+struct p_spi {
+	unsigned int cs;
+	unsigned int mode;
+	unsigned int bitlen;
+	unsigned int clk;
+	unsigned int flags;
+	u32 (*prepare_tx)(u32 reg, u32 *val, u32 write);
+};
+
+struct pmic;
+struct power_fg {
+	int (*fg_battery_check) (struct pmic *p, struct pmic *bat);
+	int (*fg_battery_update) (struct pmic *p, struct pmic *bat);
+};
+
+struct power_chrg {
+	int (*chrg_type) (struct pmic *p);
+	int (*chrg_bat_present) (struct pmic *p);
+	int (*chrg_state) (struct pmic *p, int state, int current);
+};
+
+struct power_battery {
+	struct battery *bat;
+	int (*battery_init) (struct pmic *bat, struct pmic *p1,
+			     struct pmic *p2, struct pmic *p3);
+	int (*battery_charge) (struct pmic *bat);
+	/* Keep info about power devices involved with battery operation */
+	struct pmic *chrg, *fg, *muic;
+};
+
+struct pmic {
+	const char *name;
+	unsigned char bus;
+	unsigned char interface;
+	unsigned char sensor_byte_order;
+	unsigned int number_of_regs;
+	union hw {
+		struct p_i2c i2c;
+		struct p_spi spi;
+	} hw;
+
+	void (*low_power_mode) (void);
+	struct power_battery *pbat;
+	struct power_chrg *chrg;
+	struct power_fg *fg;
+
+	struct pmic *parent;
+	struct list_head list;
+};
+#endif /* CONFIG_POWER */
+
+#ifdef CONFIG_DM_PMIC
+/**
+ * U-Boot PMIC Framework
+ * =====================
+ *
+ * UCLASS_PMIC - This is designed to provide an I/O interface for PMIC devices.
+ *
+ * For the multi-function PMIC devices, this can be used as parent I/O device
+ * for each IC's interface. Then, each child uses its parent for read/write.
+ *
+ * The driver model tree could look like this:
+ *
+ *_ root device
+ * |_ BUS 0 device (e.g. I2C0)                 - UCLASS_I2C/SPI/...
+ * | |_ PMIC device (READ/WRITE ops)           - UCLASS_PMIC
+ * |   |_ REGULATOR device (ldo/buck/... ops)  - UCLASS_REGULATOR
+ * |   |_ CHARGER device (charger ops)         - UCLASS_CHARGER (in the future)
+ * |   |_ MUIC device (microUSB connector ops) - UCLASS_MUIC    (in the future)
+ * |   |_ ...
+ * |
+ * |_ BUS 1 device (e.g. I2C1)                 - UCLASS_I2C/SPI/...
+ *   |_ PMIC device (READ/WRITE ops)           - UCLASS_PMIC
+ *     |_ RTC device (rtc ops)                 - UCLASS_RTC     (in the future)
+ *
+ * We can find two PMIC cases in boards design:
+ * - single I/O interface
+ * - multiple I/O interfaces
+ * We bind a single PMIC device for each interface, to provide an I/O for
+ * its child devices. And each child usually implements a different function,
+ * controlled by the same interface.
+ *
+ * The binding should be done automatically. If device tree nodes/subnodes are
+ * proper defined, then:
+ *
+ * |_ the ROOT driver will bind the device for I2C/SPI node:
+ *   |_ the I2C/SPI driver should bind a device for pmic node:
+ *     |_ the PMIC driver should bind devices for its childs:
+ *       |_ regulator (child)
+ *       |_ charger   (child)
+ *       |_ other     (child)
+ *
+ * The same for other device nodes, for multi-interface PMIC.
+ *
+ * Note:
+ * Each PMIC interface driver should use a different compatible string.
+ *
+ * If a PMIC child device driver needs access the PMIC-specific registers,
+ * it need know only the register address and the access can be done through
+ * the parent pmic driver. Like in the example:
+ *
+ *_ root driver
+ * |_ dev: bus I2C0                                         - UCLASS_I2C
+ * | |_ dev: my_pmic (read/write)              (is parent)  - UCLASS_PMIC
+ * |   |_ dev: my_regulator (set value/etc..)  (is child)   - UCLASS_REGULATOR
+ *
+ * To ensure such device relationship, the pmic device driver should also bind
+ * all its child devices, like in the example below. It can be done by calling
+ * the 'pmic_bind_children()' - please refer to the function description, which
+ * can be found in this header file. This function, should be called inside the
+ * driver's bind() method.
+ *
+ * For the example driver, please refer the MAX77686 driver:
+ * - 'drivers/power/pmic/max77686.c'
+ */
+
+/**
+ * struct dm_pmic_ops - PMIC device I/O interface
+ *
+ * Should be implemented by UCLASS_PMIC device drivers. The standard
+ * device operations provides the I/O interface for it's childs.
+ *
+ * @reg_count: device's register count
+ * @read:      read 'len' bytes at "reg" and store it into the 'buffer'
+ * @write:     write 'len' bytes from the 'buffer' to the register at 'reg' address
+ */
+struct dm_pmic_ops {
+	int (*reg_count)(struct udevice *dev);
+	int (*read)(struct udevice *dev, uint reg, uint8_t *buffer, int len);
+	int (*write)(struct udevice *dev, uint reg, const uint8_t *buffer,
+		     int len);
+};
+
+/**
+ * enum pmic_op_type - used for various pmic devices operation calls,
+ * for reduce a number of lines with the same code for read/write or get/set.
+ *
+ * @PMIC_OP_GET - get operation
+ * @PMIC_OP_SET - set operation
+*/
+enum pmic_op_type {
+	PMIC_OP_GET,
+	PMIC_OP_SET,
+};
+
+/**
+ * struct pmic_child_info - basic device's child info for bind child nodes with
+ * the driver by the node name prefix and driver name. This is a helper struct
+ * for function: pmic_bind_children().
+ *
+ * @prefix - child node name prefix (or its name if is unique or single)
+ * @driver - driver name for the sub-node with prefix
+ */
+struct pmic_child_info {
+	const char *prefix;
+	const char *driver;
+};
+
+/* drivers/power/pmic-uclass.c */
+
+/**
+ * pmic_bind_children() - bind drivers for given parent pmic, using child info
+ * found in 'child_info' array.
+ *
+ * @pmic       - pmic device - the parent of found child's
+ * @child_info - N-childs info array
+ * @return a positive number of childs, or 0 if no child found (error)
+ *
+ * Note: For N-childs the child_info array should have N+1 entries and the last
+ * entry prefix should be NULL - the same as for drivers compatible.
+ *
+ * For example, a single prefix info (N=1):
+ * static const struct pmic_child_info bind_info[] = {
+ *     { .prefix = "ldo", .driver = "ldo_driver" },
+ *     { },
+ * };
+ *
+ * This function is useful for regulator sub-nodes:
+ * my_regulator@0xa {
+ *     reg = <0xa>;
+ *     (pmic - bind automatically by compatible)
+ *     compatible = "my_pmic";
+ *     ...
+ *     (pmic's childs - bind by pmic_bind_children())
+ *     (nodes prefix: "ldo", driver: "my_regulator_ldo")
+ *     ldo1 { ... };
+ *     ldo2 { ... };
+ *
+ *     (nodes prefix: "buck", driver: "my_regulator_buck")
+ *     buck1 { ... };
+ *     buck2 { ... };
+ * };
+ */
+int pmic_bind_children(struct udevice *pmic, ofnode parent,
+		       const struct pmic_child_info *child_info);
+
+/**
+ * pmic_get: get the pmic device using its name
+ *
+ * @name - device name
+ * @devp - returned pointer to the pmic device
+ * @return 0 on success or negative value of errno.
+ *
+ * The returned devp device can be used with pmic_read/write calls
+ */
+int pmic_get(const char *name, struct udevice **devp);
+
+/**
+ * pmic_reg_count: get the pmic register count
+ *
+ * The required pmic device can be obtained by 'pmic_get()'
+ *
+ * @dev - pointer to the UCLASS_PMIC device
+ * @return register count value on success or negative value of errno.
+ */
+int pmic_reg_count(struct udevice *dev);
+
+/**
+ * pmic_read/write: read/write to the UCLASS_PMIC device
+ *
+ * The required pmic device can be obtained by 'pmic_get()'
+ *
+ * @pmic   - pointer to the UCLASS_PMIC device
+ * @reg    - device register offset
+ * @buffer - pointer to read/write buffer
+ * @len    - byte count for read/write
+ * @return 0 on success or negative value of errno.
+ */
+int pmic_read(struct udevice *dev, uint reg, uint8_t *buffer, int len);
+int pmic_write(struct udevice *dev, uint reg, const uint8_t *buffer, int len);
+
+/**
+ * pmic_reg_read() - read a PMIC register value
+ *
+ * @dev:	PMIC device to read
+ * @reg:	Register to read
+ * @return value read on success or negative value of errno.
+ */
+int pmic_reg_read(struct udevice *dev, uint reg);
+
+/**
+ * pmic_reg_write() - write a PMIC register value
+ *
+ * @dev:	PMIC device to write
+ * @reg:	Register to write
+ * @value:	Value to write
+ * @return 0 on success or negative value of errno.
+ */
+int pmic_reg_write(struct udevice *dev, uint reg, uint value);
+
+/**
+ * pmic_clrsetbits() - clear and set bits in a PMIC register
+ *
+ * This reads a register, optionally clears some bits, optionally sets some
+ * bits, then writes the register.
+ *
+ * @dev:	PMIC device to update
+ * @reg:	Register to update
+ * @clr:	Bit mask to clear (set those bits that you want cleared)
+ * @set:	Bit mask to set (set those bits that you want set)
+ * @return 0 on success or negative value of errno.
+ */
+int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set);
+
+/*
+ * This structure holds the private data for PMIC uclass
+ * For now we store information about the number of bytes
+ * being sent at once to the device.
+ */
+struct uc_pmic_priv {
+	uint trans_len;
+};
+
+#endif /* CONFIG_DM_PMIC */
+
+#ifdef CONFIG_POWER
+int pmic_init(unsigned char bus);
+int power_init_board(void);
+int pmic_dialog_init(unsigned char bus);
+int check_reg(struct pmic *p, u32 reg);
+struct pmic *pmic_alloc(void);
+struct pmic *pmic_get(const char *s);
+int pmic_probe(struct pmic *p);
+int pmic_reg_read(struct pmic *p, u32 reg, u32 *val);
+int pmic_reg_write(struct pmic *p, u32 reg, u32 val);
+int pmic_set_output(struct pmic *p, u32 reg, int ldo, int on);
+#endif
+
+#define pmic_i2c_addr (p->hw.i2c.addr)
+#define pmic_i2c_tx_num (p->hw.i2c.tx_num)
+
+#define pmic_spi_bitlen (p->hw.spi.bitlen)
+#define pmic_spi_flags (p->hw.spi.flags)
+
+#endif /* __CORE_PMIC_H_ */
diff --git a/include/power/power_chrg.h b/include/power/power_chrg.h
new file mode 100644
index 0000000..db19953
--- /dev/null
+++ b/include/power/power_chrg.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ */
+
+#ifndef __POWER_CHARGER_H_
+#define __POWER_CHARGER_H_
+
+/* Type of available chargers */
+enum {
+	CHARGER_NO = 0,
+	CHARGER_TA,
+	CHARGER_USB,
+	CHARGER_TA_500,
+	CHARGER_UNKNOWN,
+};
+
+enum {
+	UNKNOWN,
+	EXT_SOURCE,
+	CHARGE,
+	NORMAL,
+};
+
+#endif /* __POWER_CHARGER_H_ */
diff --git a/include/power/regulator.h b/include/power/regulator.h
new file mode 100644
index 0000000..6c6e2cd
--- /dev/null
+++ b/include/power/regulator.h
@@ -0,0 +1,465 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2014-2015 Samsung Electronics
+ *  Przemyslaw Marczak <p.marczak@samsung.com>
+ */
+
+#ifndef _INCLUDE_REGULATOR_H_
+#define _INCLUDE_REGULATOR_H_
+
+/**
+ * U-Boot Voltage/Current Regulator
+ * ================================
+ *
+ * The regulator API is based on a driver model, with the device tree support.
+ * And this header describes the functions and data types for the uclass id:
+ * 'UCLASS_REGULATOR' and the regulator driver API.
+ *
+ * The regulator uclass - is based on uclass platform data which is allocated,
+ * automatically for each regulator device on bind and 'dev->uclass_platdata'
+ * points to it. The data type is: 'struct dm_regulator_uclass_platdata'.
+ * The uclass file: 'drivers/power/regulator/regulator-uclass.c'
+ *
+ * The regulator device - is based on driver's model 'struct udevice'.
+ * The API can use regulator name in two meanings:
+ * - devname  - the regulator device's name: 'dev->name'
+ * - platname - the device's platdata's name. So in the code it looks like:
+ *              'uc_pdata = dev->uclass_platdata'; 'name = uc_pdata->name'.
+ *
+ * The regulator device driver - provide an implementation of uclass operations
+ * pointed by 'dev->driver->ops' as a struct of type 'struct dm_regulator_ops'.
+ *
+ * To proper bind the regulator device, the device tree node should provide
+ * regulator constraints, like in the example below:
+ *
+ * ldo1 {
+ *      regulator-name = "VDD_MMC_1.8V";     (must be unique for proper bind)
+ *      regulator-min-microvolt = <1000000>; (optional)
+ *      regulator-max-microvolt = <1000000>; (optional)
+ *      regulator-min-microamp = <1000>;     (optional)
+ *      regulator-max-microamp = <1000>;     (optional)
+ *      regulator-always-on;                 (optional)
+ *      regulator-boot-on;                   (optional)
+ * };
+ *
+ * Note: For the proper operation, at least name constraint is needed, since
+ * it can be used when calling regulator_get_by_platname(). And the mandatory
+ * rule for this name is, that it must be globally unique for the single dts.
+ * If regulator-name property is not provided, node name will be chosen.
+ *
+ * Regulator bind:
+ * For each regulator device, the device_bind() should be called with passed
+ * device tree offset. This is required for this uclass's '.post_bind' method,
+ * which does the scan on the device node, for the 'regulator-name' constraint.
+ * If the parent is not a PMIC device, and the child is not bind by function:
+ * 'pmic_bind_childs()', then it's recommended to bind the device by call to
+ * dm_scan_fdt_dev() - this is usually done automatically for bus devices,
+ * as a post bind method.
+ *
+ * Regulator get:
+ * Having the device's name constraint, we can call regulator_by_platname(),
+ * to find the required regulator. Before return, the regulator is probed,
+ * and the rest of its constraints are put into the device's uclass platform
+ * data, by the uclass regulator '.pre_probe' method.
+ *
+ * For more info about PMIC bind, please refer to file: 'include/power/pmic.h'
+ *
+ * Note:
+ * Please do not use the device_bind_by_name() function, since it pass '-1' as
+ * device node offset - and the bind will fail on uclass .post_bind method,
+ * because of missing 'regulator-name' constraint.
+ *
+ *
+ * Fixed Voltage/Current Regulator
+ * ===============================
+ *
+ * When fixed voltage regulator is needed, then enable the config:
+ * - CONFIG_DM_REGULATOR_FIXED
+ *
+ * The driver file: 'drivers/power/regulator/fixed.c', provides basic support
+ * for control the GPIO, and return the device tree constraint values.
+ *
+ * To bind the fixed voltage regulator device, we usually use a 'simple-bus'
+ * node as a parent. And 'regulator-fixed' for the driver compatible. This is
+ * the same as in the kernel. The example node of fixed regulator:
+ *
+ * simple-bus {
+ *     compatible = "simple-bus";
+ *     #address-cells = <1>;
+ *     #size-cells = <0>;
+ *
+ *     blue_led {
+ *         compatible = "regulator-fixed";
+ *         regulator-name = "VDD_LED_3.3V";
+ *         regulator-min-microvolt = <3300000>;
+ *         regulator-max-microvolt = <3300000>;
+ *         gpio = <&gpc1 0 GPIO_ACTIVE_LOW>;
+ *     };
+ * };
+ *
+ * The fixed regulator devices also provide regulator uclass platform data. And
+ * devices bound from such node, can use the regulator drivers API.
+*/
+
+/* enum regulator_type - used for regulator_*() variant calls */
+enum regulator_type {
+	REGULATOR_TYPE_LDO = 0,
+	REGULATOR_TYPE_BUCK,
+	REGULATOR_TYPE_DVS,
+	REGULATOR_TYPE_FIXED,
+	REGULATOR_TYPE_GPIO,
+	REGULATOR_TYPE_OTHER,
+};
+
+/**
+ * struct dm_regulator_mode - this structure holds an information about
+ * each regulator operation mode. Probably in most cases - an array.
+ * This will be probably a driver-static data, since it is device-specific.
+ *
+ * @id             - a driver-specific mode id
+ * @register_value - a driver-specific value for its mode id
+ * @name           - the name of mode - used for regulator command
+ * Note:
+ * The field 'id', should be always a positive number, since the negative values
+ * are reserved for the errno numbers when returns the mode id.
+ */
+struct dm_regulator_mode {
+	int id; /* Set only as >= 0 (negative value is reserved for errno) */
+	int register_value;
+	const char *name;
+};
+
+enum regulator_flag {
+	REGULATOR_FLAG_AUTOSET_UV	= 1 << 0,
+	REGULATOR_FLAG_AUTOSET_UA	= 1 << 1,
+};
+
+/**
+ * struct dm_regulator_uclass_platdata - pointed by dev->uclass_platdata, and
+ * allocated on each regulator bind. This structure holds an information
+ * about each regulator's constraints and supported operation modes.
+ * There is no "step" voltage value - so driver should take care of this.
+ *
+ * @type       - one of 'enum regulator_type'
+ * @mode       - pointer to the regulator mode (array if more than one)
+ * @mode_count - number of '.mode' entries
+ * @min_uV*    - minimum voltage (micro Volts)
+ * @max_uV*    - maximum voltage (micro Volts)
+ * @min_uA*    - minimum amperage (micro Amps)
+ * @max_uA*    - maximum amperage (micro Amps)
+ * @always_on* - bool type, true or false
+ * @boot_on*   - bool type, true or false
+ * TODO(sjg@chromium.org): Consider putting the above two into @flags
+ * @ramp_delay - Time to settle down after voltage change (unit: uV/us)
+ * @flags:     - flags value (see REGULATOR_FLAG_...)
+ * @name**     - fdt regulator name - should be taken from the device tree
+ * ctrl_reg:   - Control register offset used to enable/disable regulator
+ * volt_reg:   - register offset for writing voltage vsel values
+ *
+ * Note:
+ * *  - set automatically on device probe by the uclass's '.pre_probe' method.
+ * ** - set automatically on device bind by the uclass's '.post_bind' method.
+ * The constraints: type, mode, mode_count, can be set by device driver, e.g.
+ * by the driver '.probe' method.
+ */
+struct dm_regulator_uclass_platdata {
+	enum regulator_type type;
+	struct dm_regulator_mode *mode;
+	int mode_count;
+	int min_uV;
+	int max_uV;
+	int min_uA;
+	int max_uA;
+	unsigned int ramp_delay;
+	bool always_on;
+	bool boot_on;
+	const char *name;
+	int flags;
+	u8 ctrl_reg;
+	u8 volt_reg;
+};
+
+/* Regulator device operations */
+struct dm_regulator_ops {
+	/**
+	 * The regulator output value function calls operates on a micro Volts.
+	 *
+	 * get/set_value - get/set output value of the given output number
+	 * @dev          - regulator device
+	 * Sets:
+	 * @uV           - set the output value [micro Volts]
+	 * @return output value [uV] on success or negative errno if fail.
+	 */
+	int (*get_value)(struct udevice *dev);
+	int (*set_value)(struct udevice *dev, int uV);
+
+	/**
+	 * The regulator output current function calls operates on a micro Amps.
+	 *
+	 * get/set_current - get/set output current of the given output number
+	 * @dev            - regulator device
+	 * Sets:
+	 * @uA           - set the output current [micro Amps]
+	 * @return output value [uA] on success or negative errno if fail.
+	 */
+	int (*get_current)(struct udevice *dev);
+	int (*set_current)(struct udevice *dev, int uA);
+
+	/**
+	 * The most basic feature of the regulator output is its enable state.
+	 *
+	 * get/set_enable - get/set enable state of the given output number
+	 * @dev           - regulator device
+	 * Sets:
+	 * @enable         - set true - enable or false - disable
+	 * @return true/false for get or -errno if fail; 0 / -errno for set.
+	 */
+	int (*get_enable)(struct udevice *dev);
+	int (*set_enable)(struct udevice *dev, bool enable);
+
+	/**
+	 * The 'get/set_mode()' function calls should operate on a driver-
+	 * specific mode id definitions, which should be found in:
+	 * field 'id' of struct dm_regulator_mode.
+	 *
+	 * get/set_mode - get/set operation mode of the given output number
+	 * @dev         - regulator device
+	 * Sets
+	 * @mode_id     - set output mode id (struct dm_regulator_mode->id)
+	 * @return id/0 for get/set on success or negative errno if fail.
+	 * Note:
+	 * The field 'id' of struct type 'dm_regulator_mode', should be always
+	 * a positive number, since the negative is reserved for the error.
+	 */
+	int (*get_mode)(struct udevice *dev);
+	int (*set_mode)(struct udevice *dev, int mode_id);
+};
+
+/**
+ * regulator_mode: returns a pointer to the array of regulator mode info
+ *
+ * @dev        - pointer to the regulator device
+ * @modep      - pointer to the returned mode info array
+ * @return     - count of modep entries on success or negative errno if fail.
+ */
+int regulator_mode(struct udevice *dev, struct dm_regulator_mode **modep);
+
+/**
+ * regulator_get_value: get microvoltage voltage value of a given regulator
+ *
+ * @dev    - pointer to the regulator device
+ * @return - positive output value [uV] on success or negative errno if fail.
+ */
+int regulator_get_value(struct udevice *dev);
+
+/**
+ * regulator_set_value: set the microvoltage value of a given regulator.
+ *
+ * @dev    - pointer to the regulator device
+ * @uV     - the output value to set [micro Volts]
+ * @return - 0 on success or -errno val if fails
+ */
+int regulator_set_value(struct udevice *dev, int uV);
+
+/**
+ * regulator_set_value_force: set the microvoltage value of a given regulator
+ *			      without any min-,max condition check
+ *
+ * @dev    - pointer to the regulator device
+ * @uV     - the output value to set [micro Volts]
+ * @return - 0 on success or -errno val if fails
+ */
+int regulator_set_value_force(struct udevice *dev, int uV);
+
+/**
+ * regulator_get_current: get microampere value of a given regulator
+ *
+ * @dev    - pointer to the regulator device
+ * @return - positive output current [uA] on success or negative errno if fail.
+ */
+int regulator_get_current(struct udevice *dev);
+
+/**
+ * regulator_set_current: set the microampere value of a given regulator.
+ *
+ * @dev    - pointer to the regulator device
+ * @uA     - set the output current [micro Amps]
+ * @return - 0 on success or -errno val if fails
+ */
+int regulator_set_current(struct udevice *dev, int uA);
+
+/**
+ * regulator_get_enable: get regulator device enable state.
+ *
+ * @dev    - pointer to the regulator device
+ * @return - true/false of enable state or -errno val if fails
+ */
+int regulator_get_enable(struct udevice *dev);
+
+/**
+ * regulator_set_enable: set regulator enable state
+ *
+ * @dev    - pointer to the regulator device
+ * @enable - set true or false
+ * @return - 0 on success or -errno val if fails
+ */
+int regulator_set_enable(struct udevice *dev, bool enable);
+
+/**
+ * regulator_set_enable_if_allowed: set regulator enable state if allowed by
+ *					regulator
+ *
+ * @dev    - pointer to the regulator device
+ * @enable - set true or false
+ * @return - 0 on success or if enabling is not supported
+ *	     -errno val if fails.
+ */
+int regulator_set_enable_if_allowed(struct udevice *dev, bool enable);
+
+/**
+ * regulator_get_mode: get active operation mode id of a given regulator
+ *
+ * @dev    - pointer to the regulator device
+ * @return - positive mode 'id' number on success or -errno val if fails
+ * Note:
+ * The device can provide an array of operating modes, which is type of struct
+ * dm_regulator_mode. Each mode has it's own 'id', which should be unique inside
+ * that array. By calling this function, the driver should return an active mode
+ * id of the given regulator device.
+ */
+int regulator_get_mode(struct udevice *dev);
+
+/**
+ * regulator_set_mode: set the given regulator's, active mode id
+ *
+ * @dev     - pointer to the regulator device
+ * @mode_id - mode id to set ('id' field of struct type dm_regulator_mode)
+ * @return  - 0 on success or -errno value if fails
+ * Note:
+ * The device can provide an array of operating modes, which is type of struct
+ * dm_regulator_mode. Each mode has it's own 'id', which should be unique inside
+ * that array. By calling this function, the driver should set the active mode
+ * of a given regulator to given by "mode_id" argument.
+ */
+int regulator_set_mode(struct udevice *dev, int mode_id);
+
+/**
+ * regulators_enable_boot_on() - enable regulators needed for boot
+ *
+ * This enables all regulators which are marked to be on at boot time. This
+ * only works for regulators which don't have a range for voltage/current,
+ * since in that case it is not possible to know which value to use.
+ *
+ * This effectively calls regulator_autoset() for every regulator.
+ */
+int regulators_enable_boot_on(bool verbose);
+
+/**
+ * regulator_autoset: setup the voltage/current on a regulator
+ *
+ * The setup depends on constraints found in device's uclass's platform data
+ * (struct dm_regulator_uclass_platdata):
+ *
+ * - Enable - will set - if any of: 'always_on' or 'boot_on' is set to true,
+ *   or if both are unset, then the function returns
+ * - Voltage value - will set - if '.min_uV' and '.max_uV' values are equal
+ * - Current limit - will set - if '.min_uA' and '.max_uA' values are equal
+ *
+ * The function returns on the first-encountered error.
+ *
+ * @platname - expected string for dm_regulator_uclass_platdata .name field
+ * @devp     - returned pointer to the regulator device - if non-NULL passed
+ * @return: 0 on success or negative value of errno.
+ */
+int regulator_autoset(struct udevice *dev);
+
+/**
+ * regulator_autoset_by_name: setup the regulator given by its uclass's
+ * platform data name field. The setup depends on constraints found in device's
+ * uclass's platform data (struct dm_regulator_uclass_platdata):
+ * - Enable - will set - if any of: 'always_on' or 'boot_on' is set to true,
+ *   or if both are unset, then the function returns
+ * - Voltage value - will set - if '.min_uV' and '.max_uV' values are equal
+ * - Current limit - will set - if '.min_uA' and '.max_uA' values are equal
+ *
+ * The function returns on first encountered error.
+ *
+ * @platname - expected string for dm_regulator_uclass_platdata .name field
+ * @devp     - returned pointer to the regulator device - if non-NULL passed
+ * @return: 0 on success or negative value of errno.
+ *
+ * The returned 'regulator' device can be used with:
+ * - regulator_get/set_*
+ */
+int regulator_autoset_by_name(const char *platname, struct udevice **devp);
+
+/**
+ * regulator_list_autoset: setup the regulators given by list of their uclass's
+ * platform data name field. The setup depends on constraints found in device's
+ * uclass's platform data. The function loops with calls to:
+ * regulator_autoset_by_name() for each name from the list.
+ *
+ * @list_platname - an array of expected strings for .name field of each
+ *                  regulator's uclass platdata
+ * @list_devp     - an array of returned pointers to the successfully setup
+ *                  regulator devices if non-NULL passed
+ * @verbose       - (true/false) print each regulator setup info, or be quiet
+ * @return 0 on successfully setup of all list entries, otherwise first error.
+ *
+ * The returned 'regulator' devices can be used with:
+ * - regulator_get/set_*
+ *
+ * Note: The list must ends with NULL entry, like in the "platname" list below:
+ * char *my_regulators[] = {
+ *     "VCC_3.3V",
+ *     "VCC_1.8V",
+ *     NULL,
+ * };
+ */
+int regulator_list_autoset(const char *list_platname[],
+			   struct udevice *list_devp[],
+			   bool verbose);
+
+/**
+ * regulator_get_by_devname: returns the pointer to the pmic regulator device.
+ * Search by name, found in regulator device's name.
+ *
+ * @devname - expected string for 'dev->name' of regulator device
+ * @devp    - returned pointer to the regulator device
+ * @return 0 on success or negative value of errno.
+ *
+ * The returned 'regulator' device is probed and can be used with:
+ * - regulator_get/set_*
+ */
+int regulator_get_by_devname(const char *devname, struct udevice **devp);
+
+/**
+ * regulator_get_by_platname: returns the pointer to the pmic regulator device.
+ * Search by name, found in regulator uclass platdata.
+ *
+ * @platname - expected string for uc_pdata->name of regulator uclass platdata
+ * @devp     - returns pointer to the regulator device or NULL on error
+ * @return 0 on success or negative value of errno.
+ *
+ * The returned 'regulator' device is probed and can be used with:
+ * - regulator_get/set_*
+ */
+int regulator_get_by_platname(const char *platname, struct udevice **devp);
+
+/**
+ * device_get_supply_regulator: returns the pointer to the supply regulator.
+ * Search by phandle, found in device's node.
+ *
+ * Note: Please pay attention to proper order of device bind sequence.
+ * The regulator device searched by the phandle, must be binded before
+ * this function call.
+ *
+ * @dev         - device with supply phandle
+ * @supply_name - phandle name of regulator
+ * @devp        - returned pointer to the supply device
+ * @return 0 on success or negative value of errno.
+ */
+int device_get_supply_regulator(struct udevice *dev, const char *supply_name,
+				struct udevice **devp);
+
+#endif /* _INCLUDE_REGULATOR_H_ */
diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h
new file mode 100644
index 0000000..c06248f
--- /dev/null
+++ b/include/power/rk8xx_pmic.h
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef _PMIC_RK8XX_H_
+#define _PMIC_RK8XX_H_
+
+enum {
+	REG_SECONDS			= 0x00,
+	REG_MINUTES,
+	REG_HOURS,
+	REG_DAYS,
+	REG_MONTHS,
+	REG_YEARS,
+	REG_WEEKS,
+	REG_ALARM_SECONDS,
+	REG_ALARM_MINUTES,
+	REG_ALARM_HOURS,
+	REG_ALARM_DAYS,
+	REG_ALARM_MONTHS,
+	REG_ALARM_YEARS,
+
+	REG_RTC_CTRL			= 0x10,
+	REG_RTC_STATUS,
+	REG_RTC_INT,
+	REG_RTC_COMP_LSB,
+	REG_RTC_COMP_MSB,
+
+	ID_MSB				= 0x17,
+	ID_LSB,
+
+	REG_CLK32OUT			= 0x20,
+	REG_VB_MON,
+	REG_THERMAL,
+	REG_DCDC_EN,
+	REG_LDO_EN,
+	REG_SLEEP_SET_OFF1,
+	REG_SLEEP_SET_OFF2,
+	REG_DCDC_UV_STS,
+	REG_DCDC_UV_ACT,
+	REG_LDO_UV_STS,
+	REG_LDO_UV_ACT,
+	REG_DCDC_PG,
+	REG_LDO_PG,
+	REG_VOUT_MON_TDB,
+	REG_BUCK1_CONFIG,
+	REG_BUCK1_ON_VSEL,
+	REG_BUCK1_SLP_VSEL,
+	REG_BUCK1_DVS_VSEL,
+	REG_BUCK2_CONFIG,
+	REG_BUCK2_ON_VSEL,
+	REG_BUCK2_SLP_VSEL,
+	REG_BUCK2_DVS_VSEL,
+	REG_BUCK3_CONFIG,
+	REG_BUCK4_CONFIG,
+	REG_BUCK4_ON_VSEL,
+	REG_BUCK4_SLP_VSEL,
+	REG_BOOST_CONFIG_REG,
+	REG_LDO1_ON_VSEL,
+	REG_LDO1_SLP_VSEL,
+	REG_LDO2_ON_VSEL,
+	REG_LDO2_SLP_VSEL,
+	REG_LDO3_ON_VSEL,
+	REG_LDO3_SLP_VSEL,
+	REG_LDO4_ON_VSEL,
+	REG_LDO4_SLP_VSEL,
+	REG_LDO5_ON_VSEL,
+	REG_LDO5_SLP_VSEL,
+	REG_LDO6_ON_VSEL,
+	REG_LDO6_SLP_VSEL,
+	REG_LDO7_ON_VSEL,
+	REG_LDO7_SLP_VSEL,
+	REG_LDO8_ON_VSEL,
+	REG_LDO8_SLP_VSEL,
+	REG_DEVCTRL,
+	REG_INT_STS1,
+	REG_INT_STS_MSK1,
+	REG_INT_STS2,
+	REG_INT_STS_MSK2,
+	REG_IO_POL,
+	REG_OTP_VDD_EN,
+	REG_H5V_EN,
+	REG_SLEEP_SET_OFF,
+	REG_BOOST_LDO9_ON_VSEL,
+	REG_BOOST_LDO9_SLP_VSEL,
+	REG_BOOST_CTRL,
+
+	/* Not sure what this does */
+	REG_DCDC_ILMAX			= 0x90,
+	REG_CHRG_COMP			= 0x9a,
+	REG_SUP_STS			= 0xa0,
+	REG_USB_CTRL,
+	REG1_CHRG_CTRL,
+	REG2_CHRG_CTRL,
+	REG3_CHRG_CTRL,
+	REG_BAT_CTRL,
+	REG_BAT_HTS_TS1,
+	REG_BAT_LTS_TS1,
+	REG_BAT_HTS_TS2,
+	REG_BAT_LTS_TS2,
+	REG_TS_CTRL,
+	REG_ADC_CTRL,
+	REG_ON_SOURCE,
+	REG_OFF_SOURCE,
+	REG_GGCON,
+	REG_GGSTS,
+	REG_FRAME_SMP_INTERV,
+	REG_AUTO_SLP_CUR_THR,
+	REG3_GASCNT_CAL,
+	REG2_GASCNT_CAL,
+	REG1_GASCNT_CAL,
+	REG0_GASCNT_CAL,
+	REG3_GASCNT,
+	REG2_GASCNT,
+	REG1_GASCNT,
+	REG0_GASCNT,
+	REGH_BAT_CUR_AVG,
+	REGL_BAT_CUR_AVG,
+	REGH_TS1_ADC,
+	REGL_TS1_ADC,
+	REGH_TS2_ADC,
+	REGL_TS2_ADC,
+	REGH_BAT_OCV,
+	REGL_BAT_OCV,
+	REGH_BAT_VOL,
+	REGL_BAT_VOL,
+	REGH_RELAX_ENTRY_THRES,
+	REGL_RELAX_ENTRY_THRES,
+	REGH_RELAX_EXIT_THRES,
+	REGL_RELAX_EXIT_THRES,
+	REGH_RELAX_VOL1,
+	REGL_RELAX_VOL1,
+	REGH_RELAX_VOL2,
+	REGL_RELAX_VOL2,
+	REGH_BAT_CUR_R_CALC,
+	REGL_BAT_CUR_R_CALC,
+	REGH_BAT_VOL_R_CALC,
+	REGL_BAT_VOL_R_CALC,
+	REGH_CAL_OFFSET,
+	REGL_CAL_OFFSET,
+	REG_NON_ACT_TIMER_CNT,
+	REGH_VCALIB0,
+	REGL_VCALIB0,
+	REGH_VCALIB1,
+	REGL_VCALIB1,
+	REGH_IOFFSET,
+	REGL_IOFFSET,
+	REG_SOC,
+	REG3_REMAIN_CAP,
+	REG2_REMAIN_CAP,
+	REG1_REMAIN_CAP,
+	REG0_REMAIN_CAP,
+	REG_UPDAT_LEVE,
+	REG3_NEW_FCC,
+	REG2_NEW_FCC,
+	REG1_NEW_FCC,
+	REG0_NEW_FCC,
+	REG_NON_ACT_TIMER_CNT_SAVE,
+	REG_OCV_VOL_VALID,
+	REG_REBOOT_CNT,
+	REG_POFFSET,
+	REG_MISC_MARK,
+	REG_HALT_CNT,
+	REGH_CALC_REST,
+	REGL_CALC_REST,
+	SAVE_DATA19,
+	RK808_NUM_OF_REGS,
+};
+
+enum {
+	RK805_ID = 0x8050,
+	RK808_ID = 0x0000,
+	RK818_ID = 0x8180,
+};
+
+#define RK8XX_ID_MSK	0xfff0
+
+struct rk8xx_reg_table {
+	char *name;
+	u8 reg_ctl;
+	u8 reg_vol;
+};
+
+struct rk8xx_priv {
+	int variant;
+};
+
+int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
+int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma);
+int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt);
+
+#endif
diff --git a/include/power/rn5t567_pmic.h b/include/power/rn5t567_pmic.h
new file mode 100644
index 0000000..93bc7cb
--- /dev/null
+++ b/include/power/rn5t567_pmic.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Toradex AG
+ * Stefan Agner <stefan.agner@toradex.com>
+ */
+#ifndef __RN5T567_PMIC_H_
+#define __RN5T567_PMIC_H_
+
+/* RN5T567 registers */
+enum {
+	RN5T567_LSIVER		= 0x00,
+	RN5T567_OTPVER		= 0x01,
+	RN5T567_IODAC		= 0x02,
+	RN5T567_VINDAC		= 0x03,
+	RN5T567_OUT32KEN	= 0x05,
+
+	RN5T567_CPUCNT		= 0x06,
+
+	RN5T567_PSWR		= 0x07,
+	RN5T567_PONHIS		= 0x09,
+	RN5T567_POFFHIS		= 0x0A,
+	RN5T567_WATCHDOG	= 0x0B,
+	RN5T567_WATCHDOGCNT	= 0x0C,
+	RN5T567_PWRFUNC		= 0x0D,
+	RN5T567_SLPCNT		= 0x0E,
+	RN5T567_REPCNT		= 0x0F,
+	RN5T567_PWRONTIMSET	= 0x10,
+	RN5T567_NOETIMSETCNT	= 0x11,
+	RN5T567_PWRIREN		= 0x12,
+	RN5T567_PWRIRQ		= 0x13,
+	RN5T567_PWRMON		= 0x14,
+	RN5T567_PWRIRSEL	= 0x15,
+
+	RN5T567_DC1_SLOT	= 0x16,
+	RN5T567_DC2_SLOT	= 0x17,
+	RN5T567_DC3_SLOT	= 0x18,
+	RN5T567_DC4_SLOT	= 0x19,
+
+	RN5T567_LDO1_SLOT	= 0x1B,
+	RN5T567_LDO2_SLOT	= 0x1C,
+	RN5T567_LDO3_SLOT	= 0x1D,
+	RN5T567_LDO4_SLOT	= 0x1E,
+	RN5T567_LDO5_SLOT	= 0x1F,
+
+	RN5T567_PSO0_SLOT	= 0x25,
+	RN5T567_PSO1_SLOT	= 0x26,
+	RN5T567_PSO2_SLOT	= 0x27,
+	RN5T567_PSO3_SLOT	= 0x28,
+
+	RN5T567_LDORTC1_SLOT	= 0x2A,
+
+	RN5T567_DC1CTL		= 0x2C,
+	RN5T567_DC1CTL2		= 0x2D,
+	RN5T567_DC2CTL		= 0x2E,
+	RN5T567_DC2CTL2		= 0x2F,
+	RN5T567_DC3CTL		= 0x30,
+	RN5T567_DC3CTL2		= 0x31,
+	RN5T567_DC4CTL		= 0x32,
+	RN5T567_DC4CTL2		= 0x33,
+
+	RN5T567_DC1DAC		= 0x36,
+	RN5T567_DC2DAC		= 0x37,
+	RN5T567_DC3DAC		= 0x38,
+	RN5T567_DC4DAC		= 0x39,
+
+	RN5T567_DC1DAC_SLP	= 0x3B,
+	RN5T567_DC2DAC_SLP	= 0x3C,
+	RN5T567_DC3DAC_SLP	= 0x3D,
+	RN5T567_DC4DAC_SLP	= 0x3E,
+
+	RN5T567_DCIREN		= 0x40,
+	RN5T567_DCIRQ		= 0x41,
+	RN5T567_DCIRMON		= 0x42,
+
+	RN5T567_LDOEN1		= 0x44,
+	RN5T567_LDOEN2		= 0x45,
+	RN5T567_LDODIS1		= 0x46,
+
+	RN5T567_LDO1DAC		= 0x4C,
+	RN5T567_LDO2DAC		= 0x4D,
+	RN5T567_LDO3DAC		= 0x4E,
+	RN5T567_LDO4DAC		= 0x4F,
+	RN5T567_LDO5DAC		= 0x50,
+
+	RN5T567_LDORTC1DAC	= 0x56,
+	RN5T567_LDORTC2DAC	= 0x57,
+
+	RN5T567_LDO1DAC_SLP	= 0x58,
+	RN5T567_LDO2DAC_SLP	= 0x59,
+	RN5T567_LDO3DAC_SLP	= 0x5A,
+	RN5T567_LDO4DAC_SLP	= 0x5B,
+	RN5T567_LDO5DAC_SLP	= 0x5C,
+
+	RN5T567_IOSEL		= 0x90,
+	RN5T567_IOOUT		= 0x91,
+	RN5T567_GPEDGE1		= 0x92,
+	RN5T567_EN_GPIR		= 0x94,
+	RN5T567_IR_GPR		= 0x95,
+	RN5T567_IR_GPF		= 0x96,
+	RN5T567_MON_IOIN	= 0x97,
+	RN5T567_GPLED_FUNC	= 0x98,
+	RN5T567_INTPOL		= 0x9C,
+	RN5T567_INTEN		= 0x9D,
+	RN5T567_INTMON		= 0x9E,
+
+	RN5T567_PREVINDAC	= 0xB0,
+	RN5T567_OVTEMP		= 0xBC,
+
+	RN5T567_NUM_OF_REGS	= 0xBF,
+};
+
+#endif
diff --git a/include/power/s2mps11.h b/include/power/s2mps11.h
new file mode 100644
index 0000000..22b38ff
--- /dev/null
+++ b/include/power/s2mps11.h
@@ -0,0 +1,164 @@
+#ifndef __S2MPS11__H__
+#define __S2MPS11__H__
+
+enum s2mps11_reg {
+	S2MPS11_REG_ID = 0,
+	S2MPS11_REG_INT1,
+	S2MPS11_REG_INT2,
+	S2MPS11_REG_INT3,
+	S2MPS11_REG_INT1M,
+	S2MPS11_REG_INT2M,
+	S2MPS11_REG_INT3M,
+	S2MPS11_REG_STATUS1,
+	S2MPS11_REG_STATUS2,
+	S2MPS11_REG_OFFSRC,
+	S2MPS11_REG_PWRONSRC,
+	S2MPS11_REG_RTC_CTRL,
+	S2MPS11_REG_CTRL1,
+	S2MPS11_REG_ETC_TEST,
+	S2MPS11_REG_RSVD3,
+	S2MPS11_REG_BU_CHG,
+	S2MPS11_REG_RAMP,
+	S2MPS11_REG_RAMP_BUCK,
+	S2MPS11_REG_LDO1_8,
+	S2MPS11_REG_LDO9_16,
+	S2MPS11_REG_LDO17_24,
+	S2MPS11_REG_LDO25_32,
+	S2MPS11_REG_LDO33_38,
+	S2MPS11_REG_LDO1_8_OVC,
+	S2MPS11_REG_LDO9_16_OVC,
+	S2MPS11_REG_LDO17_24_OVC,
+	S2MPS11_REG_LDO25_32_OVC,
+	S2MPS11_REG_LDO33_38_OVC,
+	S2MPS11_REG_RESERVED1,
+	S2MPS11_REG_RESERVED2,
+	S2MPS11_REG_RESERVED3,
+	S2MPS11_REG_RESERVED4,
+	S2MPS11_REG_RESERVED5,
+	S2MPS11_REG_RESERVED6,
+	S2MPS11_REG_RESERVED7,
+	S2MPS11_REG_RESERVED8,
+	S2MPS11_REG_WDRSTEN_CTRL,
+	S2MPS11_REG_B1CTRL1,
+	S2MPS11_REG_B1CTRL2,
+	S2MPS11_REG_B2CTRL1,
+	S2MPS11_REG_B2CTRL2,
+	S2MPS11_REG_B3CTRL1,
+	S2MPS11_REG_B3CTRL2,
+	S2MPS11_REG_B4CTRL1,
+	S2MPS11_REG_B4CTRL2,
+	S2MPS11_REG_B5CTRL1,
+	S2MPS11_REG_BUCK5_SW,
+	S2MPS11_REG_B5CTRL2,
+	S2MPS11_REG_B5CTRL3,
+	S2MPS11_REG_B5CTRL4,
+	S2MPS11_REG_B5CTRL5,
+	S2MPS11_REG_B6CTRL1,
+	S2MPS11_REG_B6CTRL2,
+	S2MPS11_REG_B7CTRL1,
+	S2MPS11_REG_B7CTRL2,
+	S2MPS11_REG_B8CTRL1,
+	S2MPS11_REG_B8CTRL2,
+	S2MPS11_REG_B9CTRL1,
+	S2MPS11_REG_B9CTRL2,
+	S2MPS11_REG_B10CTRL1,
+	S2MPS11_REG_B10CTRL2,
+	S2MPS11_REG_L1CTRL,
+	S2MPS11_REG_L2CTRL,
+	S2MPS11_REG_L3CTRL,
+	S2MPS11_REG_L4CTRL,
+	S2MPS11_REG_L5CTRL,
+	S2MPS11_REG_L6CTRL,
+	S2MPS11_REG_L7CTRL,
+	S2MPS11_REG_L8CTRL,
+	S2MPS11_REG_L9CTRL,
+	S2MPS11_REG_L10CTRL,
+	S2MPS11_REG_L11CTRL,
+	S2MPS11_REG_L12CTRL,
+	S2MPS11_REG_L13CTRL,
+	S2MPS11_REG_L14CTRL,
+	S2MPS11_REG_L15CTRL,
+	S2MPS11_REG_L16CTRL,
+	S2MPS11_REG_L17CTRL,
+	S2MPS11_REG_L18CTRL,
+	S2MPS11_REG_L19CTRL,
+	S2MPS11_REG_L20CTRL,
+	S2MPS11_REG_L21CTRL,
+	S2MPS11_REG_L22CTRL,
+	S2MPS11_REG_L23CTRL,
+	S2MPS11_REG_L24CTRL,
+	S2MPS11_REG_L25CTRL,
+	S2MPS11_REG_L26CTRL,
+	S2MPS11_REG_L27CTRL,
+	S2MPS11_REG_L28CTRL,
+	S2MPS11_REG_L29CTRL,
+	S2MPS11_REG_L30CTRL,
+	S2MPS11_REG_L31CTRL,
+	S2MPS11_REG_L32CTRL,
+	S2MPS11_REG_L33CTRL,
+	S2MPS11_REG_L34CTRL,
+	S2MPS11_REG_L35CTRL,
+	S2MPS11_REG_L36CTRL,
+	S2MPS11_REG_L37CTRL,
+	S2MPS11_REG_L38CTRL,
+	S2MPS11_REG_COUNT,
+};
+
+#define S2MPS11_LDO26_ENABLE	0xec
+
+#define S2MPS11_LDO_NUM		26
+#define S2MPS11_BUCK_NUM	10
+
+/* Driver name */
+#define S2MPS11_BUCK_DRIVER	"s2mps11_buck"
+#define S2MPS11_OF_BUCK_PREFIX	"BUCK"
+#define S2MPS11_LDO_DRIVER	"s2mps11_ldo"
+#define S2MPS11_OF_LDO_PREFIX	"LDO"
+
+/* BUCK */
+#define S2MPS11_BUCK_VOLT_MASK	0xff
+#define S2MPS11_BUCK9_VOLT_MASK	0x1f
+
+#define S2MPS11_BUCK_LSTEP	6250
+#define S2MPS11_BUCK_HSTEP	12500
+#define S2MPS11_BUCK9_STEP	25000
+
+#define S2MPS11_BUCK_UV_MIN	600000
+#define S2MPS11_BUCK_UV_HMIN	750000
+#define S2MPS11_BUCK9_UV_MIN	1400000
+
+#define S2MPS11_BUCK_VOLT_MAX_HEX	0xA0
+#define S2MPS11_BUCK5_VOLT_MAX_HEX	0xDF
+#define S2MPS11_BUCK7_8_10_VOLT_MAX_HEX	0xDC
+#define S2MPS11_BUCK9_VOLT_MAX_HEX	0x5F
+
+#define S2MPS11_BUCK_MODE_SHIFT		6
+#define S2MPS11_BUCK_MODE_MASK		(0x3)
+#define S2MPS11_BUCK_MODE_OFF		(0x0 << 6)
+#define S2MPS11_BUCK_MODE_STANDBY	(0x1 << 6)
+#define S2MPS11_BUCK_MODE_ON		(0x3 << 6)
+
+/* LDO */
+#define S2MPS11_LDO_VOLT_MASK		0x3F
+#define S2MPS11_LDO_VOLT_MAX_HEX	0x3F
+
+#define S2MPS11_LDO_STEP	25000
+#define S2MPS11_LDO_UV_MIN	800000
+
+#define S2MPS11_LDO_MODE_MASK		0x3
+#define S2MPS11_LDO_MODE_SHIFT		6
+
+#define S2MPS11_LDO_MODE_OFF		(0x0 << 6)
+#define S2MPS11_LDO_MODE_STANDBY	(0x1 << 6)
+#define S2MPS11_LDO_MODE_STANDBY_LPM	(0x2 << 6)
+#define S2MPS11_LDO_MODE_ON		(0x3 << 6)
+
+enum {
+	OP_OFF = 0,
+	OP_LPM,
+	OP_STANDBY,
+	OP_STANDBY_LPM,
+	OP_ON,
+};
+
+#endif
diff --git a/include/power/s5m8767.h b/include/power/s5m8767.h
new file mode 100644
index 0000000..f75ed5d
--- /dev/null
+++ b/include/power/s5m8767.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#ifndef __S5M8767_H_
+#define __S5M8767_H_
+
+enum s5m8767_regnum {
+	S5M8767_BUCK1 = 0,
+	S5M8767_BUCK2,
+	S5M8767_BUCK3,
+	S5M8767_BUCK4,
+	S5M8767_BUCK5,
+	S5M8767_BUCK6,
+	S5M8767_BUCK7,
+	S5M8767_BUCK8,
+	S5M8767_BUCK9,
+	S5M8767_LDO1,
+	S5M8767_LDO2,
+	S5M8767_LDO3,
+	S5M8767_LDO4,
+	S5M8767_LDO5,
+	S5M8767_LDO6,
+	S5M8767_LDO7,
+	S5M8767_LDO8,
+	S5M8767_LDO9,
+	S5M8767_LDO10,
+	S5M8767_LDO11,
+	S5M8767_LDO12,
+	S5M8767_LDO13,
+	S5M8767_LDO14,
+	S5M8767_LDO15,
+	S5M8767_LDO16,
+	S5M8767_LDO17,
+	S5M8767_LDO18,
+	S5M8767_LDO19,
+	S5M8767_LDO20,
+	S5M8767_LDO21,
+	S5M8767_LDO22,
+	S5M8767_LDO23,
+	S5M8767_LDO24,
+	S5M8767_LDO25,
+	S5M8767_LDO26,
+	S5M8767_LDO27,
+	S5M8767_LDO28,
+	S5M8767_EN32KHZ_CP,
+
+	S5M8767_NUM_OF_REGS,
+};
+
+struct sec_voltage_desc {
+	int max;
+	int min;
+	int step;
+};
+
+/**
+ * struct s5m8767_para - s5m8767 register parameters
+ * @param vol_addr	i2c address of the given buck/ldo register
+ * @param vol_bitpos	bit position to be set or clear within register
+ * @param vol_bitmask	bit mask value
+ * @param reg_enaddr	control register address, which enable the given
+ *			given buck/ldo.
+ * @param reg_enbiton	value to be written to buck/ldo to make it ON
+ * @param vol		Voltage information
+ */
+struct s5m8767_para {
+	enum s5m8767_regnum regnum;
+	u8	vol_addr;
+	u8	vol_bitpos;
+	u8	vol_bitmask;
+	u8	reg_enaddr;
+	u8	reg_enbiton;
+	const struct sec_voltage_desc *vol;
+};
+
+/* Drivers name */
+#define S5M8767_LDO_DRIVER	"s5m8767_ldo"
+#define S5M8767_BUCK_DRIVER	"s5m8767_buck"
+
+int s5m8767_enable_32khz_cp(struct udevice *dev);
+
+#endif /* __S5M8767_PMIC_H_ */
diff --git a/include/power/sandbox_pmic.h b/include/power/sandbox_pmic.h
new file mode 100644
index 0000000..1dbd15b
--- /dev/null
+++ b/include/power/sandbox_pmic.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2015 Samsung Electronics
+ *  Przemyslaw Marczak  <p.marczak@samsung.com>
+ */
+
+#ifndef _SANDBOX_PMIC_H_
+#define  _SANDBOX_PMIC_H_
+
+#define SANDBOX_LDO_DRIVER		"sandbox_ldo"
+#define SANDBOX_OF_LDO_PREFIX		"ldo"
+#define SANDBOX_BUCK_DRIVER		"sandbox_buck"
+#define SANDBOX_OF_BUCK_PREFIX		"buck"
+
+#define SANDBOX_BUCK_COUNT	3
+#define SANDBOX_LDO_COUNT	2
+/*
+ * Sandbox PMIC registers:
+ * We have only 12 significant registers, but we alloc 16 for padding.
+ */
+enum {
+	SANDBOX_PMIC_REG_BUCK1_UV = 0,
+	SANDBOX_PMIC_REG_BUCK1_UA,
+	SANDBOX_PMIC_REG_BUCK1_OM,
+
+	SANDBOX_PMIC_REG_BUCK2_UV,
+	SANDBOX_PMIC_REG_BUCK2_UA,
+	SANDBOX_PMIC_REG_BUCK2_OM,
+
+	SANDBOX_PMIC_REG_LDO_OFFSET,
+	SANDBOX_PMIC_REG_LDO1_UV = SANDBOX_PMIC_REG_LDO_OFFSET,
+	SANDBOX_PMIC_REG_LDO1_UA,
+	SANDBOX_PMIC_REG_LDO1_OM,
+
+	SANDBOX_PMIC_REG_LDO2_UV,
+	SANDBOX_PMIC_REG_LDO2_UA,
+	SANDBOX_PMIC_REG_LDO2_OM,
+
+	SANDBOX_PMIC_REG_COUNT = 16,
+};
+
+/* Register offset for output: micro Volts, micro Amps, Operation Mode */
+enum {
+	OUT_REG_UV = 0,
+	OUT_REG_UA,
+	OUT_REG_OM,
+	OUT_REG_COUNT,
+};
+
+/* Buck operation modes */
+enum {
+	BUCK_OM_OFF = 0,
+	BUCK_OM_ON,
+	BUCK_OM_PWM,
+	BUCK_OM_COUNT,
+};
+
+/* Ldo operation modes */
+enum {
+	LDO_OM_OFF = 0,
+	LDO_OM_ON,
+	LDO_OM_SLEEP,
+	LDO_OM_STANDBY,
+	LDO_OM_COUNT,
+};
+
+/* BUCK1 Voltage: min: 0.8V, step: 25mV, max 2.4V */
+#define OUT_BUCK1_UV_MIN	800000
+#define OUT_BUCK1_UV_MAX	2400000
+#define OUT_BUCK1_UV_STEP	25000
+
+/* BUCK1 Amperage: min: 150mA, step: 25mA, max: 250mA */
+#define OUT_BUCK1_UA_MIN	150000
+#define OUT_BUCK1_UA_MAX	250000
+#define OUT_BUCK1_UA_STEP	25000
+
+/* BUCK2 Voltage: min: 0.75V, step: 50mV, max 3.95V */
+#define OUT_BUCK2_UV_MIN	750000
+#define OUT_BUCK2_UV_MAX	3950000
+#define OUT_BUCK2_UV_STEP	50000
+
+/* LDO1 Voltage: min: 0.8V, step: 25mV, max 2.4V */
+#define OUT_LDO1_UV_MIN		800000
+#define OUT_LDO1_UV_MAX		2400000
+#define OUT_LDO1_UV_STEP	25000
+
+/* LDO1 Amperage: min: 100mA, step: 50mA, max: 200mA */
+#define OUT_LDO1_UA_MIN		100000
+#define OUT_LDO1_UA_MAX		200000
+#define OUT_LDO1_UA_STEP	50000
+
+/* LDO2 Voltage: min: 0.75V, step: 50mV, max 3.95V */
+#define OUT_LDO2_UV_MIN		750000
+#define OUT_LDO2_UV_MAX		3950000
+#define OUT_LDO2_UV_STEP	50000
+
+/* register <-> value conversion */
+#define REG2VAL(min, step, reg)		((min) + ((step) * (reg)))
+#define VAL2REG(min, step, val)		(((val) - (min)) / (step))
+
+/* Operation mode id -> register value conversion */
+#define OM2REG(x)			(x)
+
+/* Test data for: test/dm/power.c */
+
+/* BUCK names */
+#define SANDBOX_BUCK1_DEVNAME	"buck1"
+#define SANDBOX_BUCK1_PLATNAME	"SUPPLY_1.2V"
+#define SANDBOX_BUCK2_DEVNAME	"buck2"
+#define SANDBOX_BUCK2_PLATNAME	"SUPPLY_3.3V"
+/* BUCK3: for testing fallback regulator prefix matching during bind */
+#define SANDBOX_BUCK3_DEVNAME	"no_match_by_nodename"
+#define SANDBOX_BUCK3_PLATNAME	"buck_SUPPLY_1.5V"
+/* LDO names */
+#define SANDBOX_LDO1_DEVNAME	"ldo1"
+#define SANDBOX_LDO1_PLATNAME	"VDD_EMMC_1.8V"
+#define SANDBOX_LDO2_DEVNAME	"ldo2"
+#define SANDBOX_LDO2_PLATNAME	"VDD_LCD_3.3V"
+
+/*
+ * Expected regulators setup after call of:
+ * - regulator_autoset_by_name()
+ * - regulator_list_autoset()
+ */
+
+/* BUCK1: for testing regulator_autoset_by_name() */
+#define SANDBOX_BUCK1_AUTOSET_EXPECTED_UV	1200000
+#define SANDBOX_BUCK1_AUTOSET_EXPECTED_UA	200000
+#define SANDBOX_BUCK1_AUTOSET_EXPECTED_ENABLE	true
+
+/* BUCK2: for testing sandbox ADC's supply */
+#define SANDBOX_BUCK2_INITIAL_EXPECTED_UV	3000000
+#define SANDBOX_BUCK2_SET_UV			3300000
+
+/* LDO1/2 for testing regulator_list_autoset() */
+#define SANDBOX_LDO1_AUTOSET_EXPECTED_UV	1800000
+#define SANDBOX_LDO1_AUTOSET_EXPECTED_UA	100000
+#define SANDBOX_LDO1_AUTOSET_EXPECTED_ENABLE	true
+
+#define SANDBOX_LDO2_AUTOSET_EXPECTED_UV	3000000
+#define SANDBOX_LDO2_AUTOSET_EXPECTED_UA	-ENOSYS
+#define SANDBOX_LDO2_AUTOSET_EXPECTED_ENABLE	false
+
+#endif
diff --git a/include/power/stpmic1.h b/include/power/stpmic1.h
new file mode 100644
index 0000000..dc8b5a7
--- /dev/null
+++ b/include/power/stpmic1.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef __PMIC_STPMIC1_H_
+#define __PMIC_STPMIC1_H_
+
+#define STPMIC1_MAIN_CR			0x10
+#define STPMIC1_BUCKS_MRST_CR		0x18
+#define STPMIC1_LDOS_MRST_CR		0x1a
+#define STPMIC1_BUCKX_MAIN_CR(buck)	(0x20 + (buck))
+#define STPMIC1_REFDDR_MAIN_CR		0x24
+#define STPMIC1_LDOX_MAIN_CR(ldo)	(0x25 + (ldo))
+#define STPMIC1_BST_SW_CR		0x40
+#define STPMIC1_NVM_SR			0xb8
+#define STPMIC1_NVM_CR			0xb9
+
+/* Main PMIC Control Register (MAIN_CR) */
+#define STPMIC1_SWOFF			BIT(0)
+#define STPMIC1_RREQ_EN			BIT(1)
+
+/* BUCKS_MRST_CR */
+#define STPMIC1_MRST_BUCK(buck)		BIT(buck)
+#define STPMIC1_MRST_BUCK_DEBUG		(STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \
+					 STPMIC1_MRST_BUCK(STPMIC1_BUCK3))
+
+/* LDOS_MRST_CR */
+#define STPMIC1_MRST_LDO(ldo)		BIT(ldo)
+#define STPMIC1_MRST_LDO_DEBUG		0
+
+/* BUCKx_MAIN_CR (x=1...4) */
+#define STPMIC1_BUCK_ENA		BIT(0)
+#define STPMIC1_BUCK_PREG_MODE		BIT(1)
+#define STPMIC1_BUCK_VOUT_MASK		GENMASK(7, 2)
+#define STPMIC1_BUCK_VOUT_SHIFT		2
+#define STPMIC1_BUCK_VOUT(sel)		(sel << STPMIC1_BUCK_VOUT_SHIFT)
+
+#define STPMIC1_BUCK2_1200000V		STPMIC1_BUCK_VOUT(24)
+#define STPMIC1_BUCK2_1350000V		STPMIC1_BUCK_VOUT(30)
+
+#define STPMIC1_BUCK3_1800000V		STPMIC1_BUCK_VOUT(39)
+
+/* REFDDR_MAIN_CR */
+#define STPMIC1_VREF_ENA		BIT(0)
+
+/* LDOX_MAIN_CR */
+#define STPMIC1_LDO_ENA			BIT(0)
+#define STPMIC1_LDO12356_VOUT_MASK	GENMASK(6, 2)
+#define STPMIC1_LDO12356_VOUT_SHIFT	2
+#define STPMIC1_LDO_VOUT(sel)		(sel << STPMIC1_LDO12356_VOUT_SHIFT)
+
+#define STPMIC1_LDO3_MODE		BIT(7)
+#define STPMIC1_LDO3_DDR_SEL		31
+#define STPMIC1_LDO3_1800000		STPMIC1_LDO_VOUT(9)
+
+#define STPMIC1_LDO4_UV			3300000
+
+/* BST_SW_CR */
+#define STPMIC1_BST_ON			BIT(0)
+#define STPMIC1_VBUSOTG_ON		BIT(1)
+#define STPMIC1_SWOUT_ON		BIT(2)
+#define STPMIC1_PWR_SW_ON		(STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)
+
+/* NVM_SR */
+#define STPMIC1_NVM_BUSY		BIT(0)
+
+/* NVM_CR */
+#define STPMIC1_NVM_CMD_PROGRAM		1
+#define STPMIC1_NVM_CMD_READ		2
+
+/* Timeout */
+#define STPMIC1_DEFAULT_START_UP_DELAY_MS	1
+#define STPMIC1_DEFAULT_STOP_DELAY_MS		5
+#define STPMIC1_USB_BOOST_START_UP_DELAY_MS	10
+
+enum {
+	STPMIC1_BUCK1,
+	STPMIC1_BUCK2,
+	STPMIC1_BUCK3,
+	STPMIC1_BUCK4,
+	STPMIC1_MAX_BUCK,
+};
+
+enum {
+	STPMIC1_PREG_MODE_HP,
+	STPMIC1_PREG_MODE_LP,
+};
+
+enum {
+	STPMIC1_LDO1,
+	STPMIC1_LDO2,
+	STPMIC1_LDO3,
+	STPMIC1_LDO4,
+	STPMIC1_LDO5,
+	STPMIC1_LDO6,
+	STPMIC1_MAX_LDO,
+};
+
+enum {
+	STPMIC1_LDO_MODE_NORMAL,
+	STPMIC1_LDO_MODE_BYPASS,
+	STPMIC1_LDO_MODE_SINK_SOURCE,
+};
+
+enum {
+	STPMIC1_PWR_SW1,
+	STPMIC1_PWR_SW2,
+	STPMIC1_MAX_PWR_SW,
+};
+#endif
diff --git a/include/power/tps62362.h b/include/power/tps62362.h
new file mode 100644
index 0000000..f0fc538
--- /dev/null
+++ b/include/power/tps62362.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Felipe Balbi <balbi@ti.com>
+ */
+
+#ifndef __POWER_TPS62362_H__
+#define __POWER_TPS62362_H__
+
+/* I2C chip address */
+#define TPS62362_I2C_ADDR			0x60
+
+/* Registers */
+#define TPS62362_SET0				0x00
+#define TPS62362_SET1				0x01
+#define TPS62362_SET2				0x02
+#define TPS62362_SET3				0x03
+#define TPS62362_NUM_REGS			4
+
+#define TPS62362_DCDC_VOLT_SEL_0950MV		0x12
+#define TPS62362_DCDC_VOLT_SEL_1100MV		0x21
+#define TPS62362_DCDC_VOLT_SEL_1200MV		0x2b
+#define TPS62362_DCDC_VOLT_SEL_1260MV		0x31
+#define TPS62362_DCDC_VOLT_SEL_1330MV		0x38
+
+int tps62362_voltage_update(unsigned char reg, unsigned char volt_sel);
+int power_tps62362_init(unsigned char bus);
+#endif	/* __POWER_TPS62362_H__ */
diff --git a/include/power/tps65090.h b/include/power/tps65090.h
new file mode 100644
index 0000000..2716968
--- /dev/null
+++ b/include/power/tps65090.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __TPS65090_PMIC_H_
+#define __TPS65090_PMIC_H_
+
+/* I2C device address for TPS65090 PMU */
+#define TPS65090_I2C_ADDR	0x48
+
+/* TPS65090 register addresses */
+enum {
+	REG_IRQ1 = 0,
+	REG_CG_CTRL0 = 4,
+	REG_CG_STATUS1 = 0xa,
+	REG_FET_BASE = 0xe,	/* Not a real register, FETs count from here */
+	REG_FET1_CTRL,
+	REG_FET2_CTRL,
+	REG_FET3_CTRL,
+	REG_FET4_CTRL,
+	REG_FET5_CTRL,
+	REG_FET6_CTRL,
+	REG_FET7_CTRL,
+	TPS65090_NUM_REGS,
+};
+
+enum {
+	IRQ1_VBATG = 1 << 3,
+	CG_CTRL0_ENC_MASK	= 0x01,
+
+	MAX_FET_NUM	= 7,
+	MAX_CTRL_READ_TRIES = 5,
+
+	/* TPS65090 FET_CTRL register values */
+	FET_CTRL_TOFET		= 1 << 7,  /* Timeout, startup, overload */
+	FET_CTRL_PGFET		= 1 << 4,  /* Power good for FET status */
+	FET_CTRL_WAIT		= 3 << 2,  /* Overcurrent timeout max */
+	FET_CTRL_ADENFET	= 1 << 1,  /* Enable output auto discharge */
+	FET_CTRL_ENFET		= 1 << 0,  /* Enable FET */
+};
+
+enum {
+	/* Status register fields */
+	TPS65090_ST1_OTC	= 1 << 0,
+	TPS65090_ST1_OCC	= 1 << 1,
+	TPS65090_ST1_STATE_SHIFT = 4,
+	TPS65090_ST1_STATE_MASK	= 0xf << TPS65090_ST1_STATE_SHIFT,
+};
+
+/* Drivers name */
+#define TPS65090_FET_DRIVER	"tps65090_fet"
+
+#endif /* __TPS65090_PMIC_H_ */
diff --git a/include/power/tps65217.h b/include/power/tps65217.h
new file mode 100644
index 0000000..669a94a
--- /dev/null
+++ b/include/power/tps65217.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * For more details, please see the TRM at http://www.ti.com/product/tps65217a
+ */
+
+#ifndef __POWER_TPS65217_H__
+#define __POWER_TPS65217_H__
+
+/* I2C chip address */
+#define TPS65217_CHIP_PM			0x24
+
+/* Registers */
+enum {
+	TPS65217_CHIPID				= 0x00,
+	TPS65217_POWER_PATH,
+	TPS65217_INTERRUPT,
+	TPS65217_CHGCONFIG0,
+	TPS65217_CHGCONFIG1,
+	TPS65217_CHGCONFIG2,
+	TPS65217_CHGCONFIG3,
+	TPS65217_WLEDCTRL1,
+	TPS65217_WLEDCTRL2,
+	TPS65217_MUXCTRL,
+	TPS65217_STATUS,
+	TPS65217_PASSWORD,
+	TPS65217_PGOOD,
+	TPS65217_DEFPG,
+	TPS65217_DEFDCDC1,
+	TPS65217_DEFDCDC2,
+	TPS65217_DEFDCDC3,
+	TPS65217_DEFSLEW,
+	TPS65217_DEFLDO1,
+	TPS65217_DEFLDO2,
+	TPS65217_DEFLS1,
+	TPS65217_DEFLS2,
+	TPS65217_ENABLE,
+	TPS65217_RESERVED0, /* no 0x17 register available */
+	TPS65217_DEFUVLO,
+	TPS65217_SEQ1,
+	TPS65217_SEQ2,
+	TPS65217_SEQ3,
+	TPS65217_SEQ4,
+	TPS65217_SEQ5,
+	TPS65217_SEQ6,
+	TPS65217_PMIC_NUM_OF_REGS,
+};
+
+#define TPS65217_PROT_LEVEL_NONE		0x00
+#define TPS65217_PROT_LEVEL_1			0x01
+#define TPS65217_PROT_LEVEL_2			0x02
+
+#define TPS65217_PASSWORD_LOCK_FOR_WRITE	0x00
+#define TPS65217_PASSWORD_UNLOCK		0x7D
+
+#define TPS65217_DCDC_GO			0x80
+
+#define TPS65217_MASK_ALL_BITS			0xFF
+
+#define TPS65217_USB_INPUT_CUR_LIMIT_MASK	0x03
+#define TPS65217_USB_INPUT_CUR_LIMIT_100MA	0x00
+#define TPS65217_USB_INPUT_CUR_LIMIT_500MA	0x01
+#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA	0x02
+#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA	0x03
+
+#define TPS65217_DCDC_VOLT_SEL_950MV		0x02
+#define TPS65217_DCDC_VOLT_SEL_1100MV		0x08
+#define TPS65217_DCDC_VOLT_SEL_1125MV		0x09
+#define TPS65217_DCDC_VOLT_SEL_1200MV		0x0c
+#define TPS65217_DCDC_VOLT_SEL_1275MV		0x0F
+#define TPS65217_DCDC_VOLT_SEL_1325MV		0x11
+
+#define TPS65217_LDO_MASK			0x1F
+#define TPS65217_LDO_VOLTAGE_OUT_1_8		0x06
+#define TPS65217_LDO_VOLTAGE_OUT_3_3		0x1F
+
+#define TPS65217_PWR_OFF			0x80
+#define TPS65217_PWR_SRC_USB_BITMASK		0x4
+#define TPS65217_PWR_SRC_AC_BITMASK		0x8
+
+int power_tps65217_init(unsigned char bus);
+
+int tps65217_reg_read(uchar src_reg, uchar *src_val);
+int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+		       uchar mask);
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
+#endif	/* __POWER_TPS65217_H__ */
diff --git a/include/power/tps65218.h b/include/power/tps65218.h
new file mode 100644
index 0000000..bb66c3f
--- /dev/null
+++ b/include/power/tps65218.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2014
+ * Texas Instruments, <www.ti.com>
+ */
+
+#ifndef __POWER_TPS65218_H__
+#define __POWER_TPS65218_H__
+
+#include <linux/bitops.h>
+
+/* I2C chip address */
+#define TPS65218_CHIP_PM			0x24
+
+/* Registers */
+enum {
+	TPS65218_CHIPID				= 0x00,
+	TPS65218_INT1,
+	TPS65218_INT2,
+	TPS65218_INT_MASK1,
+	TPS65218_INT_MASK2,
+	TPS65218_STATUS,
+	TPS65218_CONTROL,
+	TPS65218_FLAG,
+	TPS65218_PASSWORD			= 0x10,
+	TPS65218_ENABLE1,
+	TPS65218_ENABLE2,
+	TPS65218_CONFIG1,
+	TPS65218_CONFIG2,
+	TPS65218_CONFIG3,
+	TPS65218_DCDC1,
+	TPS65218_DCDC2,
+	TPS65218_DCDC3,
+	TPS65218_DCDC4,
+	TPS65218_SLEW,
+	TPS65218_LDO1,
+	TPS65218_SEQ1				= 0x20,
+	TPS65218_SEQ2,
+	TPS65218_SEQ3,
+	TPS65218_SEQ4,
+	TPS65218_SEQ5,
+	TPS65218_SEQ6,
+	TPS65218_SEQ7,
+	TPS65218_PMIC_NUM_OF_REGS,
+};
+
+#define TPS65218_PROT_LEVEL_NONE		0x00
+#define TPS65218_PROT_LEVEL_1			0x01
+#define TPS65218_PROT_LEVEL_2			0x02
+
+#define TPS65218_PASSWORD_LOCK_FOR_WRITE	0x00
+#define TPS65218_PASSWORD_UNLOCK		0x7D
+
+#define TPS65218_DCDC_GO			0x80
+
+#define TPS65218_MASK_ALL_BITS			0xFF
+
+#define TPS65218_DCDC_VSEL_MASK			0x3F
+
+#define TPS65218_DCDC_VOLT_SEL_0950MV		0x0a
+#define TPS65218_DCDC_VOLT_SEL_1100MV		0x19
+#define TPS65218_DCDC_VOLT_SEL_1200MV		0x23
+#define TPS65218_DCDC_VOLT_SEL_1260MV		0x29
+#define TPS65218_DCDC_VOLT_SEL_1330MV		0x30
+#define TPS65218_DCDC3_VOLT_SEL_1350MV		0x12
+#define TPS65218_DCDC3_VOLT_SEL_1200MV		0xC
+
+#define TPS65218_CC_STAT	(BIT(0) | BIT(1))
+#define TPS65218_STATE		(BIT(2) | BIT(3))
+#define TPS65218_PB_STATE	BIT(4)
+#define TPS65218_AC_STATE	BIT(5)
+#define TPS65218_EE		BIT(6)
+#define TPS65218_FSEAL		BIT(7)
+
+int tps65218_reg_read(uchar dest_reg, uchar *dest_val);
+int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+		       uchar mask);
+int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
+int tps65218_toggle_fseal(void);
+int tps65218_lock_fseal(void);
+int power_tps65218_init(unsigned char bus);
+#endif	/* __POWER_TPS65218_H__ */
diff --git a/include/power/tps65910.h b/include/power/tps65910.h
new file mode 100644
index 0000000..21b2a21
--- /dev/null
+++ b/include/power/tps65910.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * For more details, please see the TRM at http://www.ti.com/product/tps65910
+ */
+#ifndef __POWER_TPS65910_H__
+#define __POWER_TPS65910_H__
+
+#define MPU     0
+#define CORE    1
+
+#define TPS65910_SR_I2C_ADDR				0x12
+#define TPS65910_CTRL_I2C_ADDR				0x2D
+
+/* PMIC Register offsets */
+enum {
+	TPS65910_VDD1_REG				= 0x21,
+	TPS65910_VDD1_OP_REG				= 0x22,
+	TPS65910_VDD2_REG				= 0x24,
+	TPS65910_VDD2_OP_REG				= 0x25,
+	TPS65910_DEVCTRL_REG				= 0x3F,
+};
+
+/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
+#define TPS65910_VGAIN_SEL_MASK				(0x3 << 6)
+#define TPS65910_ILMAX_MASK				(0x1 << 5)
+#define TPS65910_TSTEP_MASK				(0x7 << 2)
+#define TPS65910_ST_MASK				(0x3)
+
+#define TPS65910_REG_VGAIN_SEL_X1			(0x0 << 6)
+#define TPS65910_REG_VGAIN_SEL_X1_0			(0x1 << 6)
+#define TPS65910_REG_VGAIN_SEL_X3			(0x2 << 6)
+#define TPS65910_REG_VGAIN_SEL_X4			(0x3 << 6)
+
+#define TPS65910_REG_ILMAX_1_0_A			(0x0 << 5)
+#define TPS65910_REG_ILMAX_1_5_A			(0x1 << 5)
+
+#define TPS65910_REG_TSTEP_				(0x0 << 2)
+#define TPS65910_REG_TSTEP_12_5				(0x1 << 2)
+#define TPS65910_REG_TSTEP_9_4				(0x2 << 2)
+#define TPS65910_REG_TSTEP_7_5				(0x3 << 2)
+#define TPS65910_REG_TSTEP_6_25				(0x4 << 2)
+#define TPS65910_REG_TSTEP_4_7				(0x5 << 2)
+#define TPS65910_REG_TSTEP_3_12				(0x6 << 2)
+#define TPS65910_REG_TSTEP_2_5				(0x7 << 2)
+
+#define TPS65910_REG_ST_OFF				(0x0)
+#define TPS65910_REG_ST_ON_HI_POW			(0x1)
+#define TPS65910_REG_ST_OFF_1				(0x2)
+#define TPS65910_REG_ST_ON_LOW_POW			(0x3)
+
+
+/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
+#define TPS65910_OP_REG_SEL				(0x7F)
+
+#define TPS65910_OP_REG_CMD_MASK			(0x1 << 7)
+#define TPS65910_OP_REG_CMD_OP				(0x0 << 7)
+#define TPS65910_OP_REG_CMD_SR				(0x1 << 7)
+
+#define TPS65910_OP_REG_SEL_MASK			(0x7F)
+#define TPS65910_OP_REG_SEL_0_9_5			(0x1F)	/* 0.9500 V */
+#define TPS65910_OP_REG_SEL_1_1_0			(0x2B)	/* 1.1000 V */
+#define TPS65910_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
+#define TPS65910_OP_REG_SEL_1_2_0			(0x33)	/* 1.2000 V */
+#define TPS65910_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */
+#define TPS65910_OP_REG_SEL_1_3_2_5			(0x3D)	/* 1.3250 V */
+
+/* Device control register . (DEVCTRL_REG) */
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK		(0x1 << 4)
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C	(0x0 << 4)
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C	(0x1 << 4)
+
+int power_tps65910_init(unsigned char bus);
+int tps65910_set_i2c_control(void);
+int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel);
+#endif	/* __POWER_TPS65910_H__ */
diff --git a/include/power/tps65910_pmic.h b/include/power/tps65910_pmic.h
new file mode 100644
index 0000000..6621478
--- /dev/null
+++ b/include/power/tps65910_pmic.h
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
+ */
+
+#ifndef __TPS65910_PMIC_H_
+#define __TPS65910_PMIC_H_
+
+#define TPS65910_I2C_SEL_MASK		(0x1 << 4)
+#define TPS65910_VDD_SR_MASK		(0x1 << 7)
+#define TPS65910_GAIN_SEL_MASK		(0x3 << 6)
+#define TPS65910_VDD_SEL_MASK		0x7f
+#define TPS65910_VDD_SEL_MIN		3
+#define TPS65910_VDD_SEL_MAX		75
+#define TPS65910_SEL_MASK		(0x3 << 2)
+#define TPS65910_SUPPLY_STATE_MASK	0x3
+#define TPS65910_SUPPLY_STATE_OFF	0x0
+#define TPS65910_SUPPLY_STATE_ON	0x1
+
+/* i2c registers */
+enum {
+	TPS65910_REG_RTC_SEC			= 0x00,
+	TPS65910_REG_RTC_MIN,
+	TPS65910_REG_RTC_HOUR,
+	TPS65910_REG_RTC_DAY,
+	TPS65910_REG_RTC_MONTH,
+	TPS65910_REG_RTC_YEAR,
+	TPS65910_REG_RTC_WEEK,
+	TPS65910_REG_RTC_ALARM_SEC		= 0x08,
+	TPS65910_REG_RTC_ALARM_MIN,
+	TPS65910_REG_RTC_ALARM_HOUR,
+	TPS65910_REG_RTC_ALARM_DAY,
+	TPS65910_REG_RTC_ALARM_MONTH,
+	TPS65910_REG_RTC_ALARM_YEAR,
+	TPS65910_REG_RTC_CTRL			= 0x10,
+	TPS65910_REG_RTC_STAT,
+	TPS65910_REG_RTC_INT,
+	TPS65910_REG_RTC_COMP_LSB,
+	TPS65910_REG_RTC_COMP_MSB,
+	TPS65910_REG_RTC_RESISTOR_PRG,
+	TPS65910_REG_RTC_RESET_STAT,
+	TPS65910_REG_BACKUP1,
+	TPS65910_REG_BACKUP2,
+	TPS65910_REG_BACKUP3,
+	TPS65910_REG_BACKUP4,
+	TPS65910_REG_BACKUP5,
+	TPS65910_REG_PUADEN,
+	TPS65910_REG_REF,
+	TPS65910_REG_VRTC,
+	TPS65910_REG_VIO			= 0x20,
+	TPS65910_REG_VDD1,
+	TPS65910_REG_VDD1_VAL,
+	TPS65910_REG_VDD1_VAL_SR,
+	TPS65910_REG_VDD2,
+	TPS65910_REG_VDD2_VAL,
+	TPS65910_REG_VDD2_VAL_SR,
+	TPS65910_REG_VDD3,
+	TPS65910_REG_VDIG1			= 0x30,
+	TPS65910_REG_VDIG2,
+	TPS65910_REG_VAUX1,
+	TPS65910_REG_VAUX2,
+	TPS65910_REG_VAUX33,
+	TPS65910_REG_VMMC,
+	TPS65910_REG_VPLL,
+	TPS65910_REG_VDAC,
+	TPS65910_REG_THERM,
+	TPS65910_REG_BATTERY_BACKUP_CHARGE,
+	TPS65910_REG_DCDC_CTRL			= 0x3e,
+	TPS65910_REG_DEVICE_CTRL,
+	TPS65910_REG_DEVICE_CTRL2,
+	TPS65910_REG_SLEEP_KEEP_LDO_ON,
+	TPS65910_REG_SLEEP_KEEP_RES_ON,
+	TPS65910_REG_SLEEP_SET_LDO_OFF,
+	TPS65910_REG_SLEEP_SET_RES_OFF,
+	TPS65910_REG_EN1_LDO_ASS,
+	TPS65910_REG_EM1_SMPS_ASS,
+	TPS65910_REG_EN2_LDO_ASS,
+	TPS65910_REG_EM2_SMPS_ASS,
+	TPS65910_REG_INT_STAT			= 0x50,
+	TPS65910_REG_INT_MASK,
+	TPS65910_REG_INT_STAT2,
+	TPS65910_REG_INT_MASK2,
+	TPS65910_REG_GPIO			= 0x60,
+	TPS65910_REG_JTAGREVNUM			= 0x80,
+	TPS65910_NUM_REGS
+};
+
+/* chip supplies */
+enum {
+	TPS65910_SUPPLY_VCCIO	= 0x00,
+	TPS65910_SUPPLY_VCC1,
+	TPS65910_SUPPLY_VCC2,
+	TPS65910_SUPPLY_VCC3,
+	TPS65910_SUPPLY_VCC4,
+	TPS65910_SUPPLY_VCC5,
+	TPS65910_SUPPLY_VCC6,
+	TPS65910_SUPPLY_VCC7,
+	TPS65910_NUM_SUPPLIES
+};
+
+/* regulator unit numbers */
+enum {
+	TPS65910_UNIT_VRTC = 0x00,
+	TPS65910_UNIT_VIO,
+	TPS65910_UNIT_VDD1,
+	TPS65910_UNIT_VDD2,
+	TPS65910_UNIT_VDD3,
+	TPS65910_UNIT_VDIG1,
+	TPS65910_UNIT_VDIG2,
+	TPS65910_UNIT_VPLL,
+	TPS65910_UNIT_VDAC,
+	TPS65910_UNIT_VAUX1,
+	TPS65910_UNIT_VAUX2,
+	TPS65910_UNIT_VAUX33,
+	TPS65910_UNIT_VMMC,
+};
+
+/* platform data */
+struct tps65910_regulator_pdata {
+	u32 supply;	/* regulator supply voltage in uV */
+	uint unit;	/* unit-address according to DT */
+};
+
+/* driver names */
+#define TPS65910_BUCK_DRIVER	"tps65910_buck"
+#define TPS65910_BOOST_DRIVER	"tps65910_boost"
+#define TPS65910_LDO_DRIVER	"tps65910_ldo"
+
+#endif /* __TPS65910_PMIC_H_ */
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
new file mode 100644
index 0000000..db7b166
--- /dev/null
+++ b/include/ppc_asm.tmpl
@@ -0,0 +1,286 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * This file contains all the macros and symbols which define
+ * a PowerPC assembly language environment.
+ */
+#ifndef	__PPC_ASM_TMPL__
+#define __PPC_ASM_TMPL__
+
+#include <config.h>
+
+/***************************************************************************
+ *
+ * These definitions simplify the ugly declarations necessary for GOT
+ * definitions.
+ *
+ * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
+ *
+ * Uses r12 to access the GOT
+ */
+
+#define START_GOT			\
+	.section	".got2","aw";	\
+.LCTOC1 = .+32768
+
+#define END_GOT				\
+	.text
+
+#define GET_GOT				\
+	bl	1f		;	\
+	.text	2		;	\
+0:	.long	.LCTOC1-1f	;	\
+	.text			;	\
+1:	mflr	r12		;	\
+	lwz	r0,0b-1b(r12)	;	\
+	add	r12,r0,r12	;
+
+#define GOT_ENTRY(NAME)		.L_ ## NAME = . - .LCTOC1 ; .long NAME
+
+#define GOT(NAME)		.L_ ## NAME (r12)
+
+
+/***************************************************************************
+ * Register names
+ */
+#define	r0	0
+#define	r1	1
+#define	r2	2
+#define	r3	3
+#define	r4	4
+#define	r5	5
+#define	r6	6
+#define	r7	7
+#define	r8	8
+#define	r9	9
+#define	r10	10
+#define	r11	11
+#define	r12	12
+#define	r13	13
+#define	r14	14
+#define	r15	15
+#define	r16	16
+#define	r17	17
+#define	r18	18
+#define	r19	19
+#define	r20	20
+#define	r21	21
+#define	r22	22
+#define	r23	23
+#define	r24	24
+#define	r25	25
+#define	r26	26
+#define	r27	27
+#define	r28	28
+#define	r29	29
+#define	r30	30
+#define	r31	31
+
+#if defined(CONFIG_MPC8xx)
+
+/* Some special registers */
+
+#define ICR	148	/* Interrupt Cause Register (37-44) */
+#define DER	149
+#define COUNTA	150	/* Breakpoint Counter	    (37-44) */
+#define COUNTB	151	/* Breakpoint Counter	    (37-44) */
+#define LCTRL1	156	/* Load/Store Support	    (37-40) */
+#define LCTRL2	157	/* Load/Store Support	    (37-41) */
+#define ICTRL	158
+
+#endif	/* CONFIG_MPC8xx */
+
+
+#if defined(CONFIG_MPC8xx)
+
+/* Registers in the processor's internal memory map that we use.
+*/
+#define SYPCR	0x00000004
+#define BR0	0x00000100
+#define OR0	0x00000104
+#define BR1	0x00000108
+#define OR1	0x0000010c
+#define BR2	0x00000110
+#define OR2	0x00000114
+#define BR3	0x00000118
+#define OR3	0x0000011c
+#define BR4	0x00000120
+#define OR4	0x00000124
+
+#define MAR	0x00000164
+#define MCR	0x00000168
+#define MAMR	0x00000170
+#define MBMR	0x00000174
+#define MSTAT	0x00000178
+#define MPTPR	0x0000017a
+#define MDR	0x0000017c
+
+#define TBSCR	0x00000200
+#define TBREFF0	0x00000204
+
+#define PLPRCR	0x00000284
+
+#endif
+
+#define curptr r2
+
+#define SYNC \
+	sync; \
+	isync
+
+/*
+ * Macros for storing registers into and loading registers from
+ * exception frames.
+ */
+#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)
+#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)
+#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
+#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
+#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
+#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)
+#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)
+#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)
+#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)
+#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)
+
+/*
+ * GCC sometimes accesses words at negative offsets from the stack
+ * pointer, although the SysV ABI says it shouldn't.  To cope with
+ * this, we leave this much untouched space on the stack on exception
+ * entry.
+ */
+#define STACK_UNDERHEAD	64
+
+/*
+ * Exception entry code.  This code runs with address translation
+ * turned off, i.e. using physical addresses.
+ * We assume sprg3 has the physical address of the current
+ * task's thread_struct.
+ */
+#define EXCEPTION_PROLOG(reg1, reg2)	\
+	mtspr	SPRG0,r20;	\
+	mtspr	SPRG1,r21;	\
+	mfcr	r20;		\
+	subi	r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD;	/* alloc exc. frame */\
+	stw	r20,_CCR(r21);		/* save registers */ \
+	stw	r22,GPR22(r21);	\
+	stw	r23,GPR23(r21);	\
+	mfspr	r20,SPRG0;	\
+	stw	r20,GPR20(r21);	\
+	mfspr	r22,SPRG1;	\
+	stw	r22,GPR21(r21);	\
+	mflr	r20;		\
+	stw	r20,_LINK(r21);	\
+	mfctr	r22;		\
+	stw	r22,_CTR(r21);	\
+	mfspr	r20,XER;	\
+	stw	r20,_XER(r21);	\
+	mfspr	r20, DAR_DEAR;	\
+	stw	r20,_DAR(r21);	\
+	mfspr	r22,reg1;	\
+	mfspr	r23,reg2;	\
+	stw	r0,GPR0(r21);	\
+	stw	r1,GPR1(r21);	\
+	stw	r2,GPR2(r21);	\
+	stw	r1,0(r21);	\
+	mr	r1,r21;			/* set new kernel sp */	\
+	SAVE_4GPRS(3, r21);
+/*
+ * Note: code which follows this uses cr0.eq (set if from kernel),
+ * r21, r22 (SRR0), and r23 (SRR1).
+ */
+
+/*
+ * Exception vectors.
+ *
+ * The data words for `hdlr' and `int_return' are initialized with
+ * OFFSET values only; they must be relocated first before they can
+ * be used!
+ */
+#define COPY_EE(d, s)		rlwimi d,s,0,16,16
+#define NOCOPY(d, s)
+
+#ifdef CONFIG_E500
+#define EXC_XFER_TEMPLATE(n, label, hdlr, msr, copyee)	\
+	stw	r22,_NIP(r21);				\
+	stw	r23,_MSR(r21);				\
+	li	r23,n;					\
+	stw	r23,TRAP(r21);				\
+	li	r20,msr;				\
+	copyee(r20,r23);				\
+	rlwimi	r20,r23,0,25,25;			\
+	mtmsr	r20;					\
+	bl	1f;					\
+1:	mflr	r23;					\
+	addis	r23,r23,(hdlr - 1b)@ha;			\
+	addi	r23,r23,(hdlr - 1b)@l;			\
+	b	transfer_to_handler
+
+#define STD_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
+label:								\
+	EXCEPTION_PROLOG(SRR0, SRR1);				\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	EXC_XFER_TEMPLATE(n, label, hdlr, MSR_KERNEL, NOCOPY)	\
+
+#define CRIT_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
+label:								\
+	EXCEPTION_PROLOG(CSRR0, CSRR1);				\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	EXC_XFER_TEMPLATE(n, label, hdlr,			\
+	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
+
+#define MCK_EXCEPTION(n, label, hdlr)				\
+.align 4;							\
+label:								\
+	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	EXC_XFER_TEMPLATE(n, label, hdlr,			\
+	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
+
+#else	/* !E500 */
+
+#define EXC_XFER_TEMPLATE(label, hdlr, msr, copyee)	\
+	bl	1f;					\
+1:	mflr    r20;					\
+	lwz	r20,(.L_ ## label)-1b+8(r20);		\
+	mtlr	r20;					\
+	li	r20,msr;				\
+	copyee(r20,r23);				\
+	rlwimi	r20,r23,0,25,25;			\
+	blrl;						\
+.L_ ## label :						\
+	.long	hdlr - _start + _START_OFFSET;		\
+	.long	int_return - _start + _START_OFFSET;	\
+	.long	transfer_to_handler - _start + _START_OFFSET
+
+#define STD_EXCEPTION(n, label, hdlr)				\
+	. = n;							\
+label:								\
+	EXCEPTION_PROLOG(SRR0, SRR1);				\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	EXC_XFER_TEMPLATE(label, hdlr, MSR_KERNEL, NOCOPY)	\
+
+#define CRIT_EXCEPTION(n, label, hdlr)				\
+	. = n;							\
+label:								\
+	EXCEPTION_PROLOG(CSRR0, CSRR1);				\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	EXC_XFER_TEMPLATE(label, hdlr,				\
+	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
+
+#define MCK_EXCEPTION(n, label, hdlr)				\
+	. = n;							\
+label:								\
+	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	EXC_XFER_TEMPLATE(label, hdlr,				\
+	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
+
+#endif	/* !E500 */
+#endif	/* __PPC_ASM_TMPL__ */
diff --git a/include/ppc_defs.h b/include/ppc_defs.h
new file mode 100644
index 0000000..42ddc3b
--- /dev/null
+++ b/include/ppc_defs.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * WARNING! This file is automatically generated - DO NOT EDIT!
+ */
+#define	KERNELBASE	-1073741824
+#define	STATE	0
+#define	NEXT_TASK	64
+#define	COUNTER	52
+#define	PROCESSOR	916
+#define	SIGPENDING	8
+#define	TSS	576
+#define	MM	880
+#define	TASK_STRUCT_SIZE	928
+#define	KSP	0
+#define	PG_TABLES	4
+#define	PGD	8
+#define	LAST_SYSCALL	20
+#define	PT_REGS	12
+#define	PF_TRACESYS	32
+#define	TASK_FLAGS	4
+#define	TSS_FPR0	24
+#define	TSS_FPSCR	284
+#define	TSS_SMP_FORK_RET	288
+#define	TASK_UNION_SIZE	8192
+#define	STACK_FRAME_OVERHEAD	16
+#define	INT_FRAME_SIZE	192
+#define	GPR0	16
+#define	GPR1	20
+#define	GPR2	24
+#define	GPR3	28
+#define	GPR4	32
+#define	GPR5	36
+#define	GPR6	40
+#define	GPR7	44
+#define	GPR8	48
+#define	GPR9	52
+#define	GPR10	56
+#define	GPR11	60
+#define	GPR12	64
+#define	GPR13	68
+#define	GPR14	72
+#define	GPR15	76
+#define	GPR16	80
+#define	GPR17	84
+#define	GPR18	88
+#define	GPR19	92
+#define	GPR20	96
+#define	GPR21	100
+#define	GPR22	104
+#define	GPR23	108
+#define	GPR24	112
+#define	GPR25	116
+#define	GPR26	120
+#define	GPR27	124
+#define	GPR28	128
+#define	GPR29	132
+#define	GPR30	136
+#define	GPR31	140
+#define	_NIP	144
+#define	_MSR	148
+#define	_CTR	156
+#define	_LINK	160
+#define	_CCR	168
+#define	_XER	164
+#define	_DAR	180
+#define	_DSISR	184
+#define	ORIG_GPR3	152
+#define	RESULT	188
+#define	TRAP	176
diff --git a/include/pwm.h b/include/pwm.h
new file mode 100644
index 0000000..54ae3e6
--- /dev/null
+++ b/include/pwm.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * header file for pwm driver.
+ *
+ * Copyright 2016 Google Inc.
+ * Copyright (c) 2011 samsung electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ */
+
+#ifndef _pwm_h_
+#define _pwm_h_
+
+/* struct pwm_ops: Operations for the PWM uclass */
+struct pwm_ops {
+	/**
+	 * set_config() - Set the PWM configuration
+	 *
+	 * @dev:	PWM device to update
+	 * @channel:	PWM channel to update
+	 * @period_ns:	PWM period in nanoseconds
+	 * @duty_ns:	PWM duty period in nanoseconds
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_config)(struct udevice *dev, uint channel, uint period_ns,
+			  uint duty_ns);
+
+	/**
+	 * set_enable() - Enable or disable the PWM
+	 *
+	 * @dev:	PWM device to update
+	 * @channel:	PWM channel to update
+	 * @enable:	true to enable, false to disable
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_enable)(struct udevice *dev, uint channel, bool enable);
+	/**
+	 * set_invert() - Set the PWM invert
+	 *
+	 * @dev:        PWM device to update
+	 * @channel:    PWM channel to update
+	 * @polarity:   true to invert, false to keep normal polarity
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_invert)(struct udevice *dev, uint channel, bool polarity);
+};
+
+#define pwm_get_ops(dev)	((struct pwm_ops *)(dev)->driver->ops)
+
+/**
+ * pwm_set_config() - Set the PWM configuration
+ *
+ * @dev:	PWM device to update
+ * @channel:	PWM channel to update
+ * @period_ns:	PWM period in nanoseconds
+ * @duty_ns:	PWM duty period in nanoseconds
+ * @return 0 if OK, -ve on error
+ */
+int pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
+		   uint duty_ns);
+
+/**
+ * pwm_set_enable() - Enable or disable the PWM
+ *
+ * @dev:	PWM device to update
+ * @channel:	PWM channel to update
+ * @enable:	true to enable, false to disable
+ * @return 0 if OK, -ve on error
+ */
+int pwm_set_enable(struct udevice *dev, uint channel, bool enable);
+
+/**
+ * pwm_set_invert() - Set pwm default polarity
+ *
+ * @dev:	PWM device to update
+ * @channel:	PWM channel to update
+ * @polarity:	true to invert, false to keep normal polarity
+ * @return 0 if OK, -ve on error
+ */
+int pwm_set_invert(struct udevice *dev, uint channel, bool polarity);
+
+/* Legacy interface */
+#ifndef CONFIG_DM_PWM
+int	pwm_init		(int pwm_id, int div, int invert);
+int	pwm_config		(int pwm_id, int duty_ns, int period_ns);
+int	pwm_enable		(int pwm_id);
+void	pwm_disable		(int pwm_id);
+#endif
+
+#endif /* _pwm_h_ */
diff --git a/include/pwrseq.h b/include/pwrseq.h
new file mode 100644
index 0000000..fbf6376
--- /dev/null
+++ b/include/pwrseq.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc
+ */
+
+#ifndef __pwrseq_h
+#define __pwrseq_h
+
+struct pwrseq_ops {
+	int (*set_power)(struct udevice *dev, bool enable);
+};
+
+#define pwrseq_get_ops(dev)	((struct pwrseq_ops *)(dev)->driver->ops)
+
+int pwrseq_set_power(struct udevice *dev, bool enable);
+
+#endif
diff --git a/include/pxa_lcd.h b/include/pxa_lcd.h
new file mode 100644
index 0000000..11a22ab
--- /dev/null
+++ b/include/pxa_lcd.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * pxa_lcd.h - PXA LCD Controller structures
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef _PXA_LCD_H_
+#define _PXA_LCD_H_
+
+/*
+ * PXA LCD DMA descriptor
+ */
+struct pxafb_dma_descriptor {
+	u_long	fdadr;		/* Frame descriptor address register */
+	u_long	fsadr;		/* Frame source address register */
+	u_long	fidr;		/* Frame ID register */
+	u_long	ldcmd;		/* Command register */
+};
+
+/*
+ * PXA LCD info
+ */
+struct pxafb_info {
+	/* Misc registers */
+	u_long	reg_lccr3;
+	u_long	reg_lccr2;
+	u_long	reg_lccr1;
+	u_long	reg_lccr0;
+	u_long	fdadr0;
+	u_long	fdadr1;
+
+	/* DMA descriptors */
+	struct	pxafb_dma_descriptor *dmadesc_fblow;
+	struct	pxafb_dma_descriptor *dmadesc_fbhigh;
+	struct	pxafb_dma_descriptor *dmadesc_palette;
+
+	u_long	screen;		/* physical address of frame buffer */
+	u_long	palette;	/* physical address of palette memory */
+	u_int	palette_size;
+};
+
+/*
+ * LCD controller stucture for PXA CPU
+ */
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 640) */
+	ushort	vl_row;		/* Number of rows (i.e. 480) */
+	ushort  vl_rot;		/* Rotation of Display (0, 1, 2, 3) */
+	ushort	vl_width;	/* Width of display area in millimeters */
+	ushort	vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char	vl_clkp;	/* Clock polarity */
+	u_char	vl_oep;		/* Output Enable polarity */
+	u_char	vl_hsp;		/* Horizontal Sync polarity */
+	u_char	vl_vsp;		/* Vertical Sync polarity */
+	u_char	vl_dp;		/* Data polarity */
+	u_char	vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
+	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
+	u_char	vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */
+	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
+	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
+
+	/* Horizontal control register. Timing from data sheet */
+	ushort	vl_hpw;		/* Horz sync pulse width */
+	u_char	vl_blw;		/* Wait before of line */
+	u_char	vl_elw;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u_char	vl_vpw;		/* Vertical sync pulse width */
+	u_char	vl_bfw;		/* Wait before of frame */
+	u_char	vl_efw;		/* Wait end of frame */
+
+	/* PXA LCD controller params */
+	struct	pxafb_info pxa;
+} vidinfo_t;
+
+#endif
diff --git a/include/qfw.h b/include/qfw.h
new file mode 100644
index 0000000..2f1a204
--- /dev/null
+++ b/include/qfw.h
@@ -0,0 +1,175 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ */
+
+#ifndef __FW_CFG__
+#define __FW_CFG__
+
+#include <linux/list.h>
+
+enum qemu_fwcfg_items {
+	FW_CFG_SIGNATURE	= 0x00,
+	FW_CFG_ID		= 0x01,
+	FW_CFG_UUID		= 0x02,
+	FW_CFG_RAM_SIZE		= 0x03,
+	FW_CFG_NOGRAPHIC	= 0x04,
+	FW_CFG_NB_CPUS		= 0x05,
+	FW_CFG_MACHINE_ID	= 0x06,
+	FW_CFG_KERNEL_ADDR	= 0x07,
+	FW_CFG_KERNEL_SIZE	= 0x08,
+	FW_CFG_KERNEL_CMDLINE   = 0x09,
+	FW_CFG_INITRD_ADDR	= 0x0a,
+	FW_CFG_INITRD_SIZE	= 0x0b,
+	FW_CFG_BOOT_DEVICE	= 0x0c,
+	FW_CFG_NUMA		= 0x0d,
+	FW_CFG_BOOT_MENU	= 0x0e,
+	FW_CFG_MAX_CPUS		= 0x0f,
+	FW_CFG_KERNEL_ENTRY	= 0x10,
+	FW_CFG_KERNEL_DATA	= 0x11,
+	FW_CFG_INITRD_DATA	= 0x12,
+	FW_CFG_CMDLINE_ADDR	= 0x13,
+	FW_CFG_CMDLINE_SIZE	= 0x14,
+	FW_CFG_CMDLINE_DATA	= 0x15,
+	FW_CFG_SETUP_ADDR	= 0x16,
+	FW_CFG_SETUP_SIZE	= 0x17,
+	FW_CFG_SETUP_DATA	= 0x18,
+	FW_CFG_FILE_DIR		= 0x19,
+	FW_CFG_FILE_FIRST	= 0x20,
+	FW_CFG_WRITE_CHANNEL	= 0x4000,
+	FW_CFG_ARCH_LOCAL	= 0x8000,
+	FW_CFG_INVALID		= 0xffff,
+};
+
+enum {
+	BIOS_LINKER_LOADER_COMMAND_ALLOCATE	= 0x1,
+	BIOS_LINKER_LOADER_COMMAND_ADD_POINTER  = 0x2,
+	BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
+};
+
+enum {
+	BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
+	BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
+};
+
+#define FW_CFG_FILE_SLOTS	0x10
+#define FW_CFG_MAX_ENTRY	(FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS)
+#define FW_CFG_ENTRY_MASK	 ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
+
+#define FW_CFG_MAX_FILE_PATH	56
+#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
+
+#define QEMU_FW_CFG_SIGNATURE	(('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U')
+
+#define FW_CFG_DMA_ERROR	(1 << 0)
+#define FW_CFG_DMA_READ	(1 << 1)
+#define FW_CFG_DMA_SKIP	(1 << 2)
+#define FW_CFG_DMA_SELECT	(1 << 3)
+
+#define FW_CFG_DMA_ENABLED	(1 << 1)
+
+struct fw_cfg_file {
+	__be32 size;
+	__be16 select;
+	__be16 reserved;
+	char name[FW_CFG_MAX_FILE_PATH];
+};
+
+struct fw_file {
+	struct fw_cfg_file cfg; /* firmware file information */
+	unsigned long addr;     /* firmware file in-memory address */
+	struct list_head list;  /* list node to link to fw_list */
+};
+
+struct fw_cfg_file_iter {
+	struct list_head *entry; /* structure to iterate file list */
+};
+
+struct fw_cfg_dma_access {
+	__be32 control;
+	__be32 length;
+	__be64 address;
+};
+
+struct fw_cfg_arch_ops {
+	void (*arch_read_pio)(uint16_t selector, uint32_t size,
+			void *address);
+	void (*arch_read_dma)(struct fw_cfg_dma_access *dma);
+};
+
+struct bios_linker_entry {
+	__le32 command;
+	union {
+		/*
+		 * COMMAND_ALLOCATE - allocate a table from @alloc.file
+		 * subject to @alloc.align alignment (must be power of 2)
+		 * and @alloc.zone (can be HIGH or FSEG) requirements.
+		 *
+		 * Must appear exactly once for each file, and before
+		 * this file is referenced by any other command.
+		 */
+		struct {
+			char file[BIOS_LINKER_LOADER_FILESZ];
+			__le32 align;
+			uint8_t zone;
+		} alloc;
+
+		/*
+		 * COMMAND_ADD_POINTER - patch the table (originating from
+		 * @dest_file) at @pointer.offset, by adding a pointer to the
+		 * table originating from @src_file. 1,2,4 or 8 byte unsigned
+		 * addition is used depending on @pointer.size.
+		 */
+		struct {
+			char dest_file[BIOS_LINKER_LOADER_FILESZ];
+			char src_file[BIOS_LINKER_LOADER_FILESZ];
+			__le32 offset;
+			uint8_t size;
+		} pointer;
+
+		/*
+		 * COMMAND_ADD_CHECKSUM - calculate checksum of the range
+		 * specified by @cksum_start and @cksum_length fields,
+		 * and then add the value at @cksum.offset.
+		 * Checksum simply sums -X for each byte X in the range
+		 * using 8-bit math.
+		 */
+		struct {
+			char file[BIOS_LINKER_LOADER_FILESZ];
+			__le32 offset;
+			__le32 start;
+			__le32 length;
+		} cksum;
+
+		/* padding */
+		char pad[124];
+	};
+} __packed;
+
+/**
+ * Initialize QEMU fw_cfg interface
+ *
+ * @ops: arch specific read operations
+ */
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops);
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address);
+int qemu_fwcfg_read_firmware_list(void);
+struct fw_file *qemu_fwcfg_find_file(const char *name);
+
+/**
+ * Get system cpu number
+ *
+ * @return:   cpu number in system
+ */
+int qemu_fwcfg_online_cpus(void);
+
+/* helper functions to iterate firmware file list */
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter);
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter);
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter);
+
+bool qemu_fwcfg_present(void);
+bool qemu_fwcfg_dma_present(void);
+
+#endif
diff --git a/include/radeon.h b/include/radeon.h
new file mode 100644
index 0000000..da6c26b
--- /dev/null
+++ b/include/radeon.h
@@ -0,0 +1,1988 @@
+#ifndef _RADEON_H
+#define _RADEON_H
+
+
+#define RADEON_REGSIZE			0x4000
+
+
+#define MM_INDEX			0x0000
+#define MM_DATA				0x0004
+#define BUS_CNTL			0x0030
+#define HI_STAT				0x004C
+#define BUS_CNTL1			0x0034
+#define I2C_CNTL_1			0x0094
+#define CONFIG_CNTL			0x00E0
+#define CONFIG_MEMSIZE			0x00F8
+#define CONFIG_APER_0_BASE		0x0100
+#define CONFIG_APER_1_BASE		0x0104
+#define CONFIG_APER_SIZE		0x0108
+#define CONFIG_REG_1_BASE		0x010C
+#define CONFIG_REG_APER_SIZE		0x0110
+#define PAD_AGPINPUT_DELAY		0x0164
+#define PAD_CTLR_STRENGTH		0x0168
+#define PAD_CTLR_UPDATE			0x016C
+#define PAD_CTLR_MISC			0x0aa0
+#define AGP_CNTL			0x0174
+#define BM_STATUS			0x0160
+#define CAP0_TRIG_CNTL			0x0950
+#define CAP1_TRIG_CNTL			0x09c0
+#define VIPH_CONTROL			0x0C40
+#define VENDOR_ID			0x0F00
+#define DEVICE_ID			0x0F02
+#define COMMAND				0x0F04
+#define STATUS				0x0F06
+#define REVISION_ID			0x0F08
+#define REGPROG_INF			0x0F09
+#define SUB_CLASS			0x0F0A
+#define BASE_CODE			0x0F0B
+#define CACHE_LINE			0x0F0C
+#define LATENCY				0x0F0D
+#define HEADER				0x0F0E
+#define BIST				0x0F0F
+#define REG_MEM_BASE			0x0F10
+#define REG_IO_BASE			0x0F14
+#define REG_REG_BASE			0x0F18
+#define ADAPTER_ID			0x0F2C
+#define BIOS_ROM			0x0F30
+#define CAPABILITIES_PTR		0x0F34
+#define INTERRUPT_LINE			0x0F3C
+#define INTERRUPT_PIN			0x0F3D
+#define MIN_GRANT			0x0F3E
+#define MAX_LATENCY			0x0F3F
+#define ADAPTER_ID_W			0x0F4C
+#define PMI_CAP_ID			0x0F50
+#define PMI_NXT_CAP_PTR			0x0F51
+#define PMI_PMC_REG			0x0F52
+#define PM_STATUS			0x0F54
+#define PMI_DATA			0x0F57
+#define AGP_CAP_ID			0x0F58
+#define AGP_STATUS			0x0F5C
+#define AGP_COMMAND			0x0F60
+#define AIC_CTRL			0x01D0
+#define AIC_STAT			0x01D4
+#define AIC_PT_BASE			0x01D8
+#define AIC_LO_ADDR			0x01DC
+#define AIC_HI_ADDR			0x01E0
+#define AIC_TLB_ADDR			0x01E4
+#define AIC_TLB_DATA			0x01E8
+#define DAC_CNTL			0x0058
+#define DAC_CNTL2			0x007c
+#define CRTC_GEN_CNTL			0x0050
+#define MEM_CNTL			0x0140
+#define MC_CNTL				0x0140
+#define EXT_MEM_CNTL			0x0144
+#define MC_TIMING_CNTL			0x0144
+#define MC_AGP_LOCATION			0x014C
+#define MEM_IO_CNTL_A0			0x0178
+#define MEM_REFRESH_CNTL		0x0178
+#define MEM_INIT_LATENCY_TIMER		0x0154
+#define MC_INIT_GFX_LAT_TIMER		0x0154
+#define MEM_SDRAM_MODE_REG		0x0158
+#define AGP_BASE			0x0170
+#define MEM_IO_CNTL_A1			0x017C
+#define MC_READ_CNTL_AB			0x017C
+#define MEM_IO_CNTL_B0			0x0180
+#define MC_INIT_MISC_LAT_TIMER		0x0180
+#define MEM_IO_CNTL_B1			0x0184
+#define MC_IOPAD_CNTL			0x0184
+#define MC_DEBUG			0x0188
+#define MC_STATUS			0x0150
+#define MEM_IO_OE_CNTL			0x018C
+#define MC_CHIP_IO_OE_CNTL_AB		0x018C
+#define MC_FB_LOCATION			0x0148
+/* #define MC_FB_LOCATION		0x0188 */
+#define HOST_PATH_CNTL			0x0130
+#define MEM_VGA_WP_SEL			0x0038
+#define MEM_VGA_RP_SEL			0x003C
+#define HDP_DEBUG			0x0138
+#define SW_SEMAPHORE			0x013C
+#define CRTC2_GEN_CNTL			0x03f8
+#define CRTC2_DISPLAY_BASE_ADDR		0x033c
+#define SURFACE_CNTL			0x0B00
+#define SURFACE0_LOWER_BOUND		0x0B04
+#define SURFACE1_LOWER_BOUND		0x0B14
+#define SURFACE2_LOWER_BOUND		0x0B24
+#define SURFACE3_LOWER_BOUND		0x0B34
+#define SURFACE4_LOWER_BOUND		0x0B44
+#define SURFACE5_LOWER_BOUND		0x0B54
+#define SURFACE6_LOWER_BOUND		0x0B64
+#define SURFACE7_LOWER_BOUND		0x0B74
+#define SURFACE0_UPPER_BOUND		0x0B08
+#define SURFACE1_UPPER_BOUND		0x0B18
+#define SURFACE2_UPPER_BOUND		0x0B28
+#define SURFACE3_UPPER_BOUND		0x0B38
+#define SURFACE4_UPPER_BOUND		0x0B48
+#define SURFACE5_UPPER_BOUND		0x0B58
+#define SURFACE6_UPPER_BOUND		0x0B68
+#define SURFACE7_UPPER_BOUND		0x0B78
+#define SURFACE0_INFO			0x0B0C
+#define SURFACE1_INFO			0x0B1C
+#define SURFACE2_INFO			0x0B2C
+#define SURFACE3_INFO			0x0B3C
+#define SURFACE4_INFO			0x0B4C
+#define SURFACE5_INFO			0x0B5C
+#define SURFACE6_INFO			0x0B6C
+#define SURFACE7_INFO			0x0B7C
+#define SURFACE_ACCESS_FLAGS		0x0BF8
+#define SURFACE_ACCESS_CLR		0x0BFC
+#define GEN_INT_CNTL			0x0040
+#define GEN_INT_STATUS			0x0044
+#define CRTC_EXT_CNTL			0x0054
+#define RB3D_CNTL			0x1C3C
+#define WAIT_UNTIL			0x1720
+#define ISYNC_CNTL			0x1724
+#define RBBM_GUICNTL			0x172C
+#define RBBM_STATUS			0x0E40
+#define RBBM_STATUS_alt_1		0x1740
+#define RBBM_CNTL			0x00EC
+#define RBBM_CNTL_alt_1			0x0E44
+#define RBBM_SOFT_RESET			0x00F0
+#define RBBM_SOFT_RESET_alt_1		0x0E48
+#define NQWAIT_UNTIL			0x0E50
+#define RBBM_DEBUG			0x0E6C
+#define RBBM_CMDFIFO_ADDR		0x0E70
+#define RBBM_CMDFIFO_DATAL		0x0E74
+#define RBBM_CMDFIFO_DATAH		0x0E78
+#define RBBM_CMDFIFO_STAT		0x0E7C
+#define CRTC_STATUS			0x005C
+#define GPIO_VGA_DDC			0x0060
+#define GPIO_DVI_DDC			0x0064
+#define GPIO_MONID			0x0068
+#define GPIO_CRT2_DDC			0x006c
+#define PALETTE_INDEX			0x00B0
+#define PALETTE_DATA			0x00B4
+#define PALETTE_30_DATA			0x00B8
+#define CRTC_H_TOTAL_DISP		0x0200
+#define CRTC_H_SYNC_STRT_WID		0x0204
+#define CRTC_H_SYNC_POL			(1 << 23)
+#define CRTC_V_TOTAL_DISP		0x0208
+#define CRTC_V_SYNC_STRT_WID		0x020C
+#define CRTC_V_SYNC_POL			(1 << 23)
+#define CRTC_VLINE_CRNT_VLINE		0x0210
+#define CRTC_CRNT_FRAME			0x0214
+#define CRTC_GUI_TRIG_VLINE		0x0218
+#define CRTC_DEBUG			0x021C
+#define CRTC_OFFSET_RIGHT		0x0220
+#define CRTC_OFFSET			0x0224
+#define CRTC_OFFSET_CNTL		0x0228
+#define CRTC_PITCH			0x022C
+#define OVR_CLR				0x0230
+#define OVR_WID_LEFT_RIGHT		0x0234
+#define OVR_WID_TOP_BOTTOM		0x0238
+#define DISPLAY_BASE_ADDR		0x023C
+#define SNAPSHOT_VH_COUNTS		0x0240
+#define SNAPSHOT_F_COUNT		0x0244
+#define N_VIF_COUNT			0x0248
+#define SNAPSHOT_VIF_COUNT		0x024C
+#define FP_CRTC_H_TOTAL_DISP		0x0250
+#define FP_CRTC_V_TOTAL_DISP		0x0254
+#define CRT_CRTC_H_SYNC_STRT_WID	0x0258
+#define CRT_CRTC_V_SYNC_STRT_WID	0x025C
+#define CUR_OFFSET			0x0260
+#define CUR_HORZ_VERT_POSN		0x0264
+#define CUR_HORZ_VERT_OFF		0x0268
+#define CUR_CLR0			0x026C
+#define CUR_CLR1			0x0270
+#define FP_HORZ_VERT_ACTIVE		0x0278
+#define CRTC_MORE_CNTL			0x027C
+#define CRTC_H_CUTOFF_ACTIVE_EN		(1<<4)
+#define CRTC_V_CUTOFF_ACTIVE_EN		(1<<5)
+#define DAC_EXT_CNTL			0x0280
+#define FP_GEN_CNTL			0x0284
+#define FP_HORZ_STRETCH			0x028C
+#define FP_VERT_STRETCH			0x0290
+#define FP_H_SYNC_STRT_WID		0x02C4
+#define FP_V_SYNC_STRT_WID		0x02C8
+#define AUX_WINDOW_HORZ_CNTL		0x02D8
+#define AUX_WINDOW_VERT_CNTL		0x02DC
+/* #define DDA_CONFIG			0x02e0 */
+/* #define DDA_ON_OFF			0x02e4 */
+#define DVI_I2C_CNTL_1			0x02e4
+#define GRPH_BUFFER_CNTL		0x02F0
+#define GRPH2_BUFFER_CNTL		0x03F0
+#define VGA_BUFFER_CNTL			0x02F4
+#define OV0_Y_X_START			0x0400
+#define OV0_Y_X_END			0x0404
+#define OV0_PIPELINE_CNTL		0x0408
+#define OV0_REG_LOAD_CNTL		0x0410
+#define OV0_SCALE_CNTL			0x0420
+#define OV0_V_INC			0x0424
+#define OV0_P1_V_ACCUM_INIT		0x0428
+#define OV0_P23_V_ACCUM_INIT		0x042C
+#define OV0_P1_BLANK_LINES_AT_TOP	0x0430
+#define OV0_P23_BLANK_LINES_AT_TOP	0x0434
+#define OV0_BASE_ADDR			0x043C
+#define OV0_VID_BUF0_BASE_ADRS		0x0440
+#define OV0_VID_BUF1_BASE_ADRS		0x0444
+#define OV0_VID_BUF2_BASE_ADRS		0x0448
+#define OV0_VID_BUF3_BASE_ADRS		0x044C
+#define OV0_VID_BUF4_BASE_ADRS		0x0450
+#define OV0_VID_BUF5_BASE_ADRS		0x0454
+#define OV0_VID_BUF_PITCH0_VALUE	0x0460
+#define OV0_VID_BUF_PITCH1_VALUE	0x0464
+#define OV0_AUTO_FLIP_CNTRL		0x0470
+#define OV0_DEINTERLACE_PATTERN		0x0474
+#define OV0_SUBMIT_HISTORY		0x0478
+#define OV0_H_INC			0x0480
+#define OV0_STEP_BY			0x0484
+#define OV0_P1_H_ACCUM_INIT		0x0488
+#define OV0_P23_H_ACCUM_INIT		0x048C
+#define OV0_P1_X_START_END		0x0494
+#define OV0_P2_X_START_END		0x0498
+#define OV0_P3_X_START_END		0x049C
+#define OV0_FILTER_CNTL			0x04A0
+#define OV0_FOUR_TAP_COEF_0		0x04B0
+#define OV0_FOUR_TAP_COEF_1		0x04B4
+#define OV0_FOUR_TAP_COEF_2		0x04B8
+#define OV0_FOUR_TAP_COEF_3		0x04BC
+#define OV0_FOUR_TAP_COEF_4		0x04C0
+#define OV0_FLAG_CNTRL			0x04DC
+#define OV0_SLICE_CNTL			0x04E0
+#define OV0_VID_KEY_CLR_LOW		0x04E4
+#define OV0_VID_KEY_CLR_HIGH		0x04E8
+#define OV0_GRPH_KEY_CLR_LOW		0x04EC
+#define OV0_GRPH_KEY_CLR_HIGH		0x04F0
+#define OV0_KEY_CNTL			0x04F4
+#define OV0_TEST			0x04F8
+#define SUBPIC_CNTL			0x0540
+#define SUBPIC_DEFCOLCON		0x0544
+#define SUBPIC_Y_X_START		0x054C
+#define SUBPIC_Y_X_END			0x0550
+#define SUBPIC_V_INC			0x0554
+#define SUBPIC_H_INC			0x0558
+#define SUBPIC_BUF0_OFFSET		0x055C
+#define SUBPIC_BUF1_OFFSET		0x0560
+#define SUBPIC_LC0_OFFSET		0x0564
+#define SUBPIC_LC1_OFFSET		0x0568
+#define SUBPIC_PITCH			0x056C
+#define SUBPIC_BTN_HLI_COLCON		0x0570
+#define SUBPIC_BTN_HLI_Y_X_START	0x0574
+#define SUBPIC_BTN_HLI_Y_X_END		0x0578
+#define SUBPIC_PALETTE_INDEX		0x057C
+#define SUBPIC_PALETTE_DATA		0x0580
+#define SUBPIC_H_ACCUM_INIT		0x0584
+#define SUBPIC_V_ACCUM_INIT		0x0588
+#define DISP_MISC_CNTL			0x0D00
+#define DAC_MACRO_CNTL			0x0D04
+#define DISP_PWR_MAN			0x0D08
+#define DISP_TEST_DEBUG_CNTL		0x0D10
+#define DISP_HW_DEBUG			0x0D14
+#define DAC_CRC_SIG1			0x0D18
+#define DAC_CRC_SIG2			0x0D1C
+#define OV0_LIN_TRANS_A			0x0D20
+#define OV0_LIN_TRANS_B			0x0D24
+#define OV0_LIN_TRANS_C			0x0D28
+#define OV0_LIN_TRANS_D			0x0D2C
+#define OV0_LIN_TRANS_E			0x0D30
+#define OV0_LIN_TRANS_F			0x0D34
+#define OV0_GAMMA_0_F			0x0D40
+#define OV0_GAMMA_10_1F			0x0D44
+#define OV0_GAMMA_20_3F			0x0D48
+#define OV0_GAMMA_40_7F			0x0D4C
+#define OV0_GAMMA_380_3BF		0x0D50
+#define OV0_GAMMA_3C0_3FF		0x0D54
+#define DISP_MERGE_CNTL			0x0D60
+#define DISP_OUTPUT_CNTL		0x0D64
+#define DISP_LIN_TRANS_GRPH_A		0x0D80
+#define DISP_LIN_TRANS_GRPH_B		0x0D84
+#define DISP_LIN_TRANS_GRPH_C		0x0D88
+#define DISP_LIN_TRANS_GRPH_D		0x0D8C
+#define DISP_LIN_TRANS_GRPH_E		0x0D90
+#define DISP_LIN_TRANS_GRPH_F		0x0D94
+#define DISP_LIN_TRANS_VID_A		0x0D98
+#define DISP_LIN_TRANS_VID_B		0x0D9C
+#define DISP_LIN_TRANS_VID_C		0x0DA0
+#define DISP_LIN_TRANS_VID_D		0x0DA4
+#define DISP_LIN_TRANS_VID_E		0x0DA8
+#define DISP_LIN_TRANS_VID_F		0x0DAC
+#define RMX_HORZ_FILTER_0TAP_COEF	0x0DB0
+#define RMX_HORZ_FILTER_1TAP_COEF	0x0DB4
+#define RMX_HORZ_FILTER_2TAP_COEF	0x0DB8
+#define RMX_HORZ_PHASE			0x0DBC
+#define DAC_EMBEDDED_SYNC_CNTL		0x0DC0
+#define DAC_BROAD_PULSE			0x0DC4
+#define DAC_SKEW_CLKS			0x0DC8
+#define DAC_INCR			0x0DCC
+#define DAC_NEG_SYNC_LEVEL		0x0DD0
+#define DAC_POS_SYNC_LEVEL		0x0DD4
+#define DAC_BLANK_LEVEL			0x0DD8
+#define CLOCK_CNTL_INDEX		0x0008
+#define CLOCK_CNTL_DATA			0x000C
+#define CP_RB_CNTL			0x0704
+#define CP_RB_BASE			0x0700
+#define CP_RB_RPTR_ADDR			0x070C
+#define CP_RB_RPTR			0x0710
+#define CP_RB_WPTR			0x0714
+#define CP_RB_WPTR_DELAY		0x0718
+#define CP_IB_BASE			0x0738
+#define CP_IB_BUFSZ			0x073C
+#define SCRATCH_REG0			0x15E0
+#define GUI_SCRATCH_REG0		0x15E0
+#define SCRATCH_REG1			0x15E4
+#define GUI_SCRATCH_REG1		0x15E4
+#define SCRATCH_REG2			0x15E8
+#define GUI_SCRATCH_REG2		0x15E8
+#define SCRATCH_REG3			0x15EC
+#define GUI_SCRATCH_REG3		0x15EC
+#define SCRATCH_REG4			0x15F0
+#define GUI_SCRATCH_REG4		0x15F0
+#define SCRATCH_REG5			0x15F4
+#define GUI_SCRATCH_REG5		0x15F4
+#define SCRATCH_UMSK			0x0770
+#define SCRATCH_ADDR			0x0774
+#define DP_BRUSH_FRGD_CLR		0x147C
+#define DP_BRUSH_BKGD_CLR		0x1478
+#define DST_LINE_START			0x1600
+#define DST_LINE_END			0x1604
+#define SRC_OFFSET			0x15AC
+#define SRC_PITCH			0x15B0
+#define SRC_TILE			0x1704
+#define SRC_PITCH_OFFSET		0x1428
+#define SRC_X				0x1414
+#define SRC_Y				0x1418
+#define SRC_X_Y				0x1590
+#define SRC_Y_X				0x1434
+#define DST_Y_X				0x1438
+#define DST_WIDTH_HEIGHT		0x1598
+#define DST_HEIGHT_WIDTH		0x143c
+#define DST_OFFSET			0x1404
+#define SRC_CLUT_ADDRESS		0x1780
+#define SRC_CLUT_DATA			0x1784
+#define SRC_CLUT_DATA_RD		0x1788
+#define HOST_DATA0			0x17C0
+#define HOST_DATA1			0x17C4
+#define HOST_DATA2			0x17C8
+#define HOST_DATA3			0x17CC
+#define HOST_DATA4			0x17D0
+#define HOST_DATA5			0x17D4
+#define HOST_DATA6			0x17D8
+#define HOST_DATA7			0x17DC
+#define HOST_DATA_LAST			0x17E0
+#define DP_SRC_ENDIAN			0x15D4
+#define DP_SRC_FRGD_CLR			0x15D8
+#define DP_SRC_BKGD_CLR			0x15DC
+#define SC_LEFT				0x1640
+#define SC_RIGHT			0x1644
+#define SC_TOP				0x1648
+#define SC_BOTTOM			0x164C
+#define SRC_SC_RIGHT			0x1654
+#define SRC_SC_BOTTOM			0x165C
+#define DP_CNTL				0x16C0
+#define DP_CNTL_XDIR_YDIR_YMAJOR	0x16D0
+#define DP_DATATYPE			0x16C4
+#define DP_MIX				0x16C8
+#define DP_WRITE_MSK			0x16CC
+#define DP_XOP				0x17F8
+#define CLR_CMP_CLR_SRC			0x15C4
+#define CLR_CMP_CLR_DST			0x15C8
+#define CLR_CMP_CNTL			0x15C0
+#define CLR_CMP_MSK			0x15CC
+#define DSTCACHE_MODE			0x1710
+#define DSTCACHE_CTLSTAT		0x1714
+#define DEFAULT_PITCH_OFFSET		0x16E0
+#define DEFAULT_SC_BOTTOM_RIGHT		0x16E8
+#define DEFAULT_SC_TOP_LEFT		0x16EC
+#define SRC_PITCH_OFFSET		0x1428
+#define DST_PITCH_OFFSET		0x142C
+#define DP_GUI_MASTER_CNTL		0x146C
+#define SC_TOP_LEFT			0x16EC
+#define SC_BOTTOM_RIGHT			0x16F0
+#define SRC_SC_BOTTOM_RIGHT		0x16F4
+#define RB2D_DSTCACHE_MODE		0x3428
+#define RB2D_DSTCACHE_CTLSTAT		0x342C
+#define LVDS_GEN_CNTL			0x02d0
+#define LVDS_PLL_CNTL			0x02d4
+#define FP2_GEN_CNTL			0x0288
+#define TMDS_CNTL			0x0294
+#define TMDS_CRC			0x02a0
+#define TMDS_TRANSMITTER_CNTL		0x02a4
+#define MPP_TB_CONFIG			0x01c0
+#define PAMAC0_DLY_CNTL			0x0a94
+#define PAMAC1_DLY_CNTL			0x0a98
+#define PAMAC2_DLY_CNTL			0x0a9c
+#define FW_CNTL				0x0118
+#define FCP_CNTL			0x0910
+#define VGA_DDA_ON_OFF			0x02ec
+#define TV_MASTER_CNTL			0x0800
+
+/* #define BASE_CODE			0x0f0b */
+#define BIOS_0_SCRATCH			0x0010
+#define BIOS_1_SCRATCH			0x0014
+#define BIOS_2_SCRATCH			0x0018
+#define BIOS_3_SCRATCH			0x001c
+#define BIOS_4_SCRATCH			0x0020
+#define BIOS_5_SCRATCH			0x0024
+#define BIOS_6_SCRATCH			0x0028
+#define BIOS_7_SCRATCH			0x002c
+
+#define HDP_SOFT_RESET			(1 << 26)
+
+#define TV_DAC_CNTL			0x088c
+#define GPIOPAD_MASK			0x0198
+#define GPIOPAD_A			0x019c
+#define GPIOPAD_EN			0x01a0
+#define GPIOPAD_Y			0x01a4
+#define ZV_LCDPAD_MASK			0x01a8
+#define ZV_LCDPAD_A			0x01ac
+#define ZV_LCDPAD_EN			0x01b0
+#define ZV_LCDPAD_Y			0x01b4
+
+/* PLL Registers */
+#define CLK_PIN_CNTL			0x0001
+#define PPLL_CNTL			0x0002
+#define PPLL_REF_DIV			0x0003
+#define PPLL_DIV_0			0x0004
+#define PPLL_DIV_1			0x0005
+#define PPLL_DIV_2			0x0006
+#define PPLL_DIV_3			0x0007
+#define VCLK_ECP_CNTL			0x0008
+#define HTOTAL_CNTL			0x0009
+#define M_SPLL_REF_FB_DIV		0x000a
+#define AGP_PLL_CNTL			0x000b
+#define SPLL_CNTL			0x000c
+#define SCLK_CNTL			0x000d
+#define MPLL_CNTL			0x000e
+#define MDLL_CKO			0x000f
+#define MDLL_RDCKA			0x0010
+#define MCLK_CNTL			0x0012
+#define AGP_PLL_CNTL			0x000b
+#define PLL_TEST_CNTL			0x0013
+#define CLK_PWRMGT_CNTL			0x0014
+#define PLL_PWRMGT_CNTL			0x0015
+#define MCLK_MISC			0x001f
+#define P2PLL_CNTL			0x002a
+#define P2PLL_REF_DIV			0x002b
+#define PIXCLKS_CNTL			0x002d
+#define SCLK_MORE_CNTL			0x0035
+
+/* MCLK_CNTL bit constants */
+#define FORCEON_MCLKA			(1 << 16)
+#define FORCEON_MCLKB			(1 << 17)
+#define FORCEON_YCLKA			(1 << 18)
+#define FORCEON_YCLKB			(1 << 19)
+#define FORCEON_MC			(1 << 20)
+#define FORCEON_AIC			(1 << 21)
+
+/* SCLK_CNTL bit constants */
+#define DYN_STOP_LAT_MASK		0x00007ff8
+#define CP_MAX_DYN_STOP_LAT		0x0008
+#define SCLK_FORCEON_MASK		0xffff8000
+
+/* SCLK_MORE_CNTL bit constants */
+#define SCLK_MORE_FORCEON		0x0700
+
+/* BUS_CNTL bit constants */
+#define BUS_DBL_RESYNC			0x00000001
+#define BUS_MSTR_RESET			0x00000002
+#define BUS_FLUSH_BUF			0x00000004
+#define BUS_STOP_REQ_DIS		0x00000008
+#define BUS_ROTATION_DIS		0x00000010
+#define BUS_MASTER_DIS			0x00000040
+#define BUS_ROM_WRT_EN			0x00000080
+#define BUS_DIS_ROM			0x00001000
+#define BUS_PCI_READ_RETRY_EN		0x00002000
+#define BUS_AGP_AD_STEPPING_EN		0x00004000
+#define BUS_PCI_WRT_RETRY_EN		0x00008000
+#define BUS_MSTR_RD_MULT		0x00100000
+#define BUS_MSTR_RD_LINE		0x00200000
+#define BUS_SUSPEND			0x00400000
+#define LAT_16X				0x00800000
+#define BUS_RD_DISCARD_EN		0x01000000
+#define BUS_RD_ABORT_EN			0x02000000
+#define BUS_MSTR_WS			0x04000000
+#define BUS_PARKING_DIS			0x08000000
+#define BUS_MSTR_DISCONNECT_EN		0x10000000
+#define BUS_WRT_BURST			0x20000000
+#define BUS_READ_BURST			0x40000000
+#define BUS_RDY_READ_DLY		0x80000000
+
+/* PIXCLKS_CNTL */
+#define PIX2CLK_SRC_SEL_MASK		0x03
+#define PIX2CLK_SRC_SEL_CPUCLK		0x00
+#define PIX2CLK_SRC_SEL_PSCANCLK	0x01
+#define PIX2CLK_SRC_SEL_BYTECLK		0x02
+#define PIX2CLK_SRC_SEL_P2PLLCLK	0x03
+#define PIX2CLK_ALWAYS_ONb		(1<<6)
+#define PIX2CLK_DAC_ALWAYS_ONb		(1<<7)
+#define PIXCLK_TV_SRC_SEL		(1 << 8)
+#define PIXCLK_LVDS_ALWAYS_ONb		(1 << 14)
+#define PIXCLK_TMDS_ALWAYS_ONb		(1 << 15)
+
+
+/* CLOCK_CNTL_INDEX bit constants */
+#define PLL_WR_EN			0x00000080
+
+/* CONFIG_CNTL bit constants */
+#define CONFIG_SYS_VGA_RAM_EN			0x00000100
+#define CONFIG_SYS_ATI_REV_ID_MASK		(0xf << 16)
+#define CONFIG_SYS_ATI_REV_A11			(0 << 16)
+#define CONFIG_SYS_ATI_REV_A12			(1 << 16)
+#define CONFIG_SYS_ATI_REV_A13			(2 << 16)
+
+/* CRTC_EXT_CNTL bit constants */
+#define VGA_ATI_LINEAR			0x00000008
+#define VGA_128KAP_PAGING		0x00000010
+#define XCRT_CNT_EN			(1 << 6)
+#define CRTC_HSYNC_DIS			(1 << 8)
+#define CRTC_VSYNC_DIS			(1 << 9)
+#define CRTC_DISPLAY_DIS		(1 << 10)
+#define CRTC_CRT_ON			(1 << 15)
+
+
+/* DSTCACHE_CTLSTAT bit constants */
+#define RB2D_DC_FLUSH			(3 << 0)
+#define RB2D_DC_FLUSH_ALL		0xf
+#define RB2D_DC_BUSY			(1 << 31)
+
+
+/* CRTC_GEN_CNTL bit constants */
+#define CRTC_DBL_SCAN_EN		0x00000001
+#define CRTC_CUR_EN			0x00010000
+#define CRTC_INTERLACE_EN		(1 << 1)
+#define CRTC_BYPASS_LUT_EN		(1 << 14)
+#define CRTC_EXT_DISP_EN		(1 << 24)
+#define CRTC_EN				(1 << 25)
+#define CRTC_DISP_REQ_EN_B		(1 << 26)
+
+/* CRTC_STATUS bit constants */
+#define CRTC_VBLANK			0x00000001
+
+/* CRTC2_GEN_CNTL bit constants */
+#define CRT2_ON				(1 << 7)
+#define CRTC2_DISPLAY_DIS		(1 << 23)
+#define CRTC2_EN			(1 << 25)
+#define CRTC2_DISP_REQ_EN_B		(1 << 26)
+
+/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
+#define CUR_LOCK			0x80000000
+
+/* GPIO bit constants */
+#define GPIO_A_0			(1 <<  0)
+#define GPIO_A_1			(1 <<  1)
+#define GPIO_Y_0			(1 <<  8)
+#define GPIO_Y_1			(1 <<  9)
+#define GPIO_EN_0			(1 << 16)
+#define GPIO_EN_1			(1 << 17)
+#define GPIO_MASK_0			(1 << 24)
+#define GPIO_MASK_1			(1 << 25)
+#define VGA_DDC_DATA_OUTPUT		GPIO_A_0
+#define VGA_DDC_CLK_OUTPUT		GPIO_A_1
+#define VGA_DDC_DATA_INPUT		GPIO_Y_0
+#define VGA_DDC_CLK_INPUT		GPIO_Y_1
+#define VGA_DDC_DATA_OUT_EN		GPIO_EN_0
+#define VGA_DDC_CLK_OUT_EN		GPIO_EN_1
+
+
+/* FP bit constants */
+#define FP_CRTC_H_TOTAL_MASK		000003ff
+#define FP_CRTC_H_DISP_MASK		0x01ff0000
+#define FP_CRTC_V_TOTAL_MASK		0x00000fff
+#define FP_CRTC_V_DISP_MASK		0x0fff0000
+#define FP_H_SYNC_STRT_CHAR_MASK	0x00001ff8
+#define FP_H_SYNC_WID_MASK		0x003f0000
+#define FP_V_SYNC_STRT_MASK		0x00000fff
+#define FP_V_SYNC_WID_MASK		0x001f0000
+#define FP_CRTC_H_TOTAL_SHIFT		0x00000000
+#define FP_CRTC_H_DISP_SHIFT		0x00000010
+#define FP_CRTC_V_TOTAL_SHIFT		0x00000000
+#define FP_CRTC_V_DISP_SHIFT		0x00000010
+#define FP_H_SYNC_STRT_CHAR_SHIFT	0x00000003
+#define FP_H_SYNC_WID_SHIFT		0x00000010
+#define FP_V_SYNC_STRT_SHIFT		0x00000000
+#define FP_V_SYNC_WID_SHIFT		0x00000010
+
+/* FP_GEN_CNTL bit constants */
+#define FP_FPON				(1 << 0)
+#define FP_TMDS_EN			(1 << 2)
+#define FP_PANEL_FORMAT			(1 << 3)
+#define FP_EN_TMDS			(1 << 7)
+#define FP_DETECT_SENSE			(1 << 8)
+#define R200_FP_SOURCE_SEL_MASK		(3 << 10)
+#define R200_FP_SOURCE_SEL_CRTC1	(0 << 10)
+#define R200_FP_SOURCE_SEL_CRTC2	(1 << 10)
+#define R200_FP_SOURCE_SEL_RMX		(2 << 10)
+#define R200_FP_SOURCE_SEL_TRANS	(3 << 10)
+#define FP_SEL_CRTC1			(0 << 13)
+#define FP_SEL_CRTC2			(1 << 13)
+#define FP_USE_VGA_HSYNC		(1 << 14)
+#define FP_CRTC_DONT_SHADOW_HPAR	(1 << 15)
+#define FP_CRTC_DONT_SHADOW_VPAR	(1 << 16)
+#define FP_CRTC_DONT_SHADOW_HEND	(1 << 17)
+#define FP_CRTC_USE_SHADOW_VEND		(1 << 18)
+#define FP_RMX_HVSYNC_CONTROL_EN	(1 << 20)
+#define FP_DFP_SYNC_SEL			(1 << 21)
+#define FP_CRTC_LOCK_8DOT		(1 << 22)
+#define FP_CRT_SYNC_SEL			(1 << 23)
+#define FP_USE_SHADOW_EN		(1 << 24)
+#define FP_CRT_SYNC_ALT			(1 << 26)
+
+/* FP2_GEN_CNTL bit constants */
+#define FP2_BLANK_EN			(1 <<	1)
+#define FP2_ON				(1 <<	2)
+#define FP2_PANEL_FORMAT		(1 <<	3)
+#define FP2_SOURCE_SEL_MASK		(3 << 10)
+#define FP2_SOURCE_SEL_CRTC2		(1 << 10)
+#define FP2_SRC_SEL_MASK		(3 << 13)
+#define FP2_SRC_SEL_CRTC2		(1 << 13)
+#define FP2_FP_POL			(1 << 16)
+#define FP2_LP_POL			(1 << 17)
+#define FP2_SCK_POL			(1 << 18)
+#define FP2_LCD_CNTL_MASK		(7 << 19)
+#define FP2_PAD_FLOP_EN			(1 << 22)
+#define FP2_CRC_EN			(1 << 23)
+#define FP2_CRC_READ_EN			(1 << 24)
+#define FP2_DV0_EN			(1 << 25)
+#define FP2_DV0_RATE_SEL_SDR		(1 << 26)
+
+
+/* LVDS_GEN_CNTL bit constants */
+#define LVDS_ON				(1 << 0)
+#define LVDS_DISPLAY_DIS		(1 << 1)
+#define LVDS_PANEL_TYPE			(1 << 2)
+#define LVDS_PANEL_FORMAT		(1 << 3)
+#define LVDS_EN				(1 << 7)
+#define LVDS_BL_MOD_LEVEL_MASK		0x0000ff00
+#define LVDS_BL_MOD_LEVEL_SHIFT		8
+#define LVDS_BL_MOD_EN			(1 << 16)
+#define LVDS_DIGON			(1 << 18)
+#define LVDS_BLON			(1 << 19)
+#define LVDS_SEL_CRTC2			(1 << 23)
+#define LVDS_STATE_MASK \
+	(LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
+
+/* LVDS_PLL_CNTL bit constatns */
+#define HSYNC_DELAY_SHIFT		0x1c
+#define HSYNC_DELAY_MASK		(0xf << 0x1c)
+
+/* TMDS_TRANSMITTER_CNTL bit constants */
+#define TMDS_PLL_EN			(1 << 0)
+#define TMDS_PLLRST			(1 << 1)
+#define TMDS_RAN_PAT_RST		(1 << 7)
+#define TMDS_ICHCSEL			(1 << 28)
+
+/* FP_HORZ_STRETCH bit constants */
+#define HORZ_STRETCH_RATIO_MASK		0xffff
+#define HORZ_STRETCH_RATIO_MAX		4096
+#define HORZ_PANEL_SIZE			(0x1ff << 16)
+#define HORZ_PANEL_SHIFT		16
+#define HORZ_STRETCH_PIXREP		(0 << 25)
+#define HORZ_STRETCH_BLEND		(1 << 26)
+#define HORZ_STRETCH_ENABLE		(1 << 25)
+#define HORZ_AUTO_RATIO			(1 << 27)
+#define HORZ_FP_LOOP_STRETCH		(0x7 << 28)
+#define HORZ_AUTO_RATIO_INC		(1 << 31)
+
+
+/* FP_VERT_STRETCH bit constants */
+#define VERT_STRETCH_RATIO_MASK		0xfff
+#define VERT_STRETCH_RATIO_MAX		4096
+#define VERT_PANEL_SIZE			(0xfff << 12)
+#define VERT_PANEL_SHIFT		12
+#define VERT_STRETCH_LINREP		(0 << 26)
+#define VERT_STRETCH_BLEND		(1 << 26)
+#define VERT_STRETCH_ENABLE		(1 << 25)
+#define VERT_AUTO_RATIO_EN		(1 << 27)
+#define VERT_FP_LOOP_STRETCH		(0x7 << 28)
+#define VERT_STRETCH_RESERVED		0xf1000000
+
+/* DAC_CNTL bit constants */
+#define DAC_8BIT_EN			0x00000100
+#define DAC_4BPP_PIX_ORDER		0x00000200
+#define DAC_CRC_EN			0x00080000
+#define DAC_MASK_ALL			(0xff << 24)
+#define DAC_PDWN			(1 << 15)
+#define DAC_EXPAND_MODE			(1 << 14)
+#define DAC_VGA_ADR_EN			(1 << 13)
+#define DAC_RANGE_CNTL			(3 <<  0)
+#define DAC_RANGE_CNTL_MASK		0x03
+#define DAC_BLANKING			(1 <<  2)
+#define DAC_CMP_EN			(1 <<  3)
+#define DAC_CMP_OUTPUT			(1 <<  7)
+
+/* DAC_CNTL2 bit constants */
+#define DAC2_EXPAND_MODE		(1 << 14)
+#define DAC2_CMP_EN			(1 << 7)
+#define DAC2_PALETTE_ACCESS_CNTL	(1 << 5)
+
+/* DAC_EXT_CNTL bit constants */
+#define DAC_FORCE_BLANK_OFF_EN		(1 << 4)
+#define DAC_FORCE_DATA_EN		(1 << 5)
+#define DAC_FORCE_DATA_SEL_MASK		(3 << 6)
+#define DAC_FORCE_DATA_MASK		0x0003ff00
+#define DAC_FORCE_DATA_SHIFT		8
+
+/* GEN_RESET_CNTL bit constants */
+#define SOFT_RESET_GUI			0x00000001
+#define SOFT_RESET_VCLK			0x00000100
+#define SOFT_RESET_PCLK			0x00000200
+#define SOFT_RESET_ECP			0x00000400
+#define SOFT_RESET_DISPENG_XCLK		0x00000800
+
+/* MEM_CNTL bit constants */
+#define MEM_CTLR_STATUS_IDLE		0x00000000
+#define MEM_CTLR_STATUS_BUSY		0x00100000
+#define MEM_SEQNCR_STATUS_IDLE		0x00000000
+#define MEM_SEQNCR_STATUS_BUSY		0x00200000
+#define MEM_ARBITER_STATUS_IDLE		0x00000000
+#define MEM_ARBITER_STATUS_BUSY		0x00400000
+#define MEM_REQ_UNLOCK			0x00000000
+#define MEM_REQ_LOCK			0x00800000
+#define MEM_NUM_CHANNELS_MASK		0x00000001
+#define MEM_USE_B_CH_ONLY		0x00000002
+#define RV100_MEM_HALF_MODE		0x00000008
+#define R300_MEM_NUM_CHANNELS_MASK	0x00000003
+#define R300_MEM_USE_CD_CH_ONLY		0x00000004
+
+
+/* RBBM_SOFT_RESET bit constants */
+#define SOFT_RESET_CP			(1 <<  0)
+#define SOFT_RESET_HI			(1 <<  1)
+#define SOFT_RESET_SE			(1 <<  2)
+#define SOFT_RESET_RE			(1 <<  3)
+#define SOFT_RESET_PP			(1 <<  4)
+#define SOFT_RESET_E2			(1 <<  5)
+#define SOFT_RESET_RB			(1 <<  6)
+#define SOFT_RESET_HDP			(1 <<  7)
+
+/* SURFACE_CNTL bit consants */
+#define SURF_TRANSLATION_DIS		(1 << 8)
+#define NONSURF_AP0_SWP_16BPP		(1 << 20)
+#define NONSURF_AP0_SWP_32BPP		(1 << 21)
+#define NONSURF_AP1_SWP_16BPP		(1 << 22)
+#define NONSURF_AP1_SWP_32BPP		(1 << 23)
+
+#define R200_SURF_TILE_COLOR_MACRO	(1 << 16)
+
+/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
+#define DEFAULT_SC_RIGHT_MAX		(0x1fff << 0)
+#define DEFAULT_SC_BOTTOM_MAX		(0x1fff << 16)
+
+/* MM_INDEX bit constants */
+#define MM_APER				0x80000000
+
+/* CLR_CMP_CNTL bit constants */
+#define COMPARE_SRC_FALSE		0x00000000
+#define COMPARE_SRC_TRUE		0x00000001
+#define COMPARE_SRC_NOT_EQUAL		0x00000004
+#define COMPARE_SRC_EQUAL		0x00000005
+#define COMPARE_SRC_EQUAL_FLIP		0x00000007
+#define COMPARE_DST_FALSE		0x00000000
+#define COMPARE_DST_TRUE		0x00000100
+#define COMPARE_DST_NOT_EQUAL		0x00000400
+#define COMPARE_DST_EQUAL		0x00000500
+#define COMPARE_DESTINATION		0x00000000
+#define COMPARE_SOURCE			0x01000000
+#define COMPARE_SRC_AND_DST		0x02000000
+
+
+/* DP_CNTL bit constants */
+#define DST_X_RIGHT_TO_LEFT		0x00000000
+#define DST_X_LEFT_TO_RIGHT		0x00000001
+#define DST_Y_BOTTOM_TO_TOP		0x00000000
+#define DST_Y_TOP_TO_BOTTOM		0x00000002
+#define DST_X_MAJOR			0x00000000
+#define DST_Y_MAJOR			0x00000004
+#define DST_X_TILE			0x00000008
+#define DST_Y_TILE			0x00000010
+#define DST_LAST_PEL			0x00000020
+#define DST_TRAIL_X_RIGHT_TO_LEFT	0x00000000
+#define DST_TRAIL_X_LEFT_TO_RIGHT	0x00000040
+#define DST_TRAP_FILL_RIGHT_TO_LEFT	0x00000000
+#define DST_TRAP_FILL_LEFT_TO_RIGHT	0x00000080
+#define DST_BRES_SIGN			0x00000100
+#define DST_HOST_BIG_ENDIAN_EN		0x00000200
+#define DST_POLYLINE_NONLAST		0x00008000
+#define DST_RASTER_STALL		0x00010000
+#define DST_POLY_EDGE			0x00040000
+
+
+/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
+#define DST_X_MAJOR_S			0x00000000
+#define DST_Y_MAJOR_S			0x00000001
+#define DST_Y_BOTTOM_TO_TOP_S		0x00000000
+#define DST_Y_TOP_TO_BOTTOM_S		0x00008000
+#define DST_X_RIGHT_TO_LEFT_S		0x00000000
+#define DST_X_LEFT_TO_RIGHT_S		0x80000000
+
+
+/* DP_DATATYPE bit constants */
+#define DST_8BPP			0x00000002
+#define DST_15BPP			0x00000003
+#define DST_16BPP			0x00000004
+#define DST_24BPP			0x00000005
+#define DST_32BPP			0x00000006
+#define DST_8BPP_RGB332			0x00000007
+#define DST_8BPP_Y8			0x00000008
+#define DST_8BPP_RGB8			0x00000009
+#define DST_16BPP_VYUY422		0x0000000b
+#define DST_16BPP_YVYU422		0x0000000c
+#define DST_32BPP_AYUV444		0x0000000e
+#define DST_16BPP_ARGB4444		0x0000000f
+#define BRUSH_SOLIDCOLOR		0x00000d00
+#define SRC_MONO			0x00000000
+#define SRC_MONO_LBKGD			0x00010000
+#define SRC_DSTCOLOR			0x00030000
+#define BYTE_ORDER_MSB_TO_LSB		0x00000000
+#define BYTE_ORDER_LSB_TO_MSB		0x40000000
+#define DP_CONVERSION_TEMP		0x80000000
+#define HOST_BIG_ENDIAN_EN		(1 << 29)
+
+
+/* DP_GUI_MASTER_CNTL bit constants */
+#define GMC_SRC_PITCH_OFFSET_DEFAULT	0x00000000
+#define GMC_SRC_PITCH_OFFSET_LEAVE	0x00000001
+#define GMC_DST_PITCH_OFFSET_DEFAULT	0x00000000
+#define GMC_DST_PITCH_OFFSET_LEAVE	0x00000002
+#define GMC_SRC_CLIP_DEFAULT		0x00000000
+#define GMC_SRC_CLIP_LEAVE		0x00000004
+#define GMC_DST_CLIP_DEFAULT		0x00000000
+#define GMC_DST_CLIP_LEAVE		0x00000008
+#define GMC_BRUSH_8x8MONO		0x00000000
+#define GMC_BRUSH_8x8MONO_LBKGD		0x00000010
+#define GMC_BRUSH_8x1MONO		0x00000020
+#define GMC_BRUSH_8x1MONO_LBKGD		0x00000030
+#define GMC_BRUSH_1x8MONO		0x00000040
+#define GMC_BRUSH_1x8MONO_LBKGD		0x00000050
+#define GMC_BRUSH_32x1MONO		0x00000060
+#define GMC_BRUSH_32x1MONO_LBKGD	0x00000070
+#define GMC_BRUSH_32x32MONO		0x00000080
+#define GMC_BRUSH_32x32MONO_LBKGD	0x00000090
+#define GMC_BRUSH_8x8COLOR		0x000000a0
+#define GMC_BRUSH_8x1COLOR		0x000000b0
+#define GMC_BRUSH_1x8COLOR		0x000000c0
+#define GMC_BRUSH_SOLID_COLOR		0x000000d0
+#define GMC_DST_8BPP			0x00000200
+#define GMC_DST_15BPP			0x00000300
+#define GMC_DST_16BPP			0x00000400
+#define GMC_DST_24BPP			0x00000500
+#define GMC_DST_32BPP			0x00000600
+#define GMC_DST_8BPP_RGB332		0x00000700
+#define GMC_DST_8BPP_Y8			0x00000800
+#define GMC_DST_8BPP_RGB8		0x00000900
+#define GMC_DST_16BPP_VYUY422		0x00000b00
+#define GMC_DST_16BPP_YVYU422		0x00000c00
+#define GMC_DST_32BPP_AYUV444		0x00000e00
+#define GMC_DST_16BPP_ARGB4444		0x00000f00
+#define GMC_SRC_MONO			0x00000000
+#define GMC_SRC_MONO_LBKGD		0x00001000
+#define GMC_SRC_DSTCOLOR		0x00003000
+#define GMC_BYTE_ORDER_MSB_TO_LSB	0x00000000
+#define GMC_BYTE_ORDER_LSB_TO_MSB	0x00004000
+#define GMC_DP_CONVERSION_TEMP_9300	0x00008000
+#define GMC_DP_CONVERSION_TEMP_6500	0x00000000
+#define GMC_DP_SRC_RECT			0x02000000
+#define GMC_DP_SRC_HOST			0x03000000
+#define GMC_DP_SRC_HOST_BYTEALIGN	0x04000000
+#define GMC_3D_FCN_EN_CLR		0x00000000
+#define GMC_3D_FCN_EN_SET		0x08000000
+#define GMC_DST_CLR_CMP_FCN_LEAVE	0x00000000
+#define GMC_DST_CLR_CMP_FCN_CLEAR	0x10000000
+#define GMC_AUX_CLIP_LEAVE		0x00000000
+#define GMC_AUX_CLIP_CLEAR		0x20000000
+#define GMC_WRITE_MASK_LEAVE		0x00000000
+#define GMC_WRITE_MASK_SET		0x40000000
+#define GMC_CLR_CMP_CNTL_DIS		(1 << 28)
+#define GMC_SRC_DATATYPE_COLOR		(3 << 12)
+#define ROP3_S				0x00cc0000
+#define ROP3_SRCCOPY			0x00cc0000
+#define ROP3_P				0x00f00000
+#define ROP3_PATCOPY			0x00f00000
+#define DP_SRC_SOURCE_MASK		(7  << 24)
+#define GMC_BRUSH_NONE			(15 <<  4)
+#define DP_SRC_SOURCE_MEMORY		(2  << 24)
+#define GMC_BRUSH_SOLIDCOLOR		0x000000d0
+
+/* DP_MIX bit constants */
+#define DP_SRC_RECT			0x00000200
+#define DP_SRC_HOST			0x00000300
+#define DP_SRC_HOST_BYTEALIGN		0x00000400
+
+/* MPLL_CNTL bit constants */
+#define MPLL_RESET			0x00000001
+
+/* MDLL_CKO bit constants */
+#define MCKOA_SLEEP			0x00000001
+#define MCKOA_RESET			0x00000002
+#define MCKOA_REF_SKEW_MASK		0x00000700
+#define MCKOA_FB_SKEW_MASK		0x00007000
+
+/* MDLL_RDCKA bit constants */
+#define MRDCKA0_SLEEP			0x00000001
+#define MRDCKA0_RESET			0x00000002
+#define MRDCKA1_SLEEP			0x00010000
+#define MRDCKA1_RESET			0x00020000
+
+/* VCLK_ECP_CNTL constants */
+#define VCLK_SRC_SEL_MASK		0x03
+#define VCLK_SRC_SEL_CPUCLK		0x00
+#define VCLK_SRC_SEL_PSCANCLK		0x01
+#define VCLK_SRC_SEL_BYTECLK		0x02
+#define VCLK_SRC_SEL_PPLLCLK		0x03
+#define PIXCLK_ALWAYS_ONb		0x00000040
+#define PIXCLK_DAC_ALWAYS_ONb		0x00000080
+
+/* BUS_CNTL1 constants */
+#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK	0x0c000000
+#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT	26
+#define BUS_CNTL1_AGPCLK_VALID			0x80000000
+
+/* PLL_PWRMGT_CNTL constants */
+#define PLL_PWRMGT_CNTL_SPLL_TURNOFF		0x00000002
+#define PLL_PWRMGT_CNTL_PPLL_TURNOFF		0x00000004
+#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF		0x00000008
+#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF		0x00000010
+#define PLL_PWRMGT_CNTL_MOBILE_SU		0x00010000
+#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK	0x00020000
+#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK	0x00040000
+
+/* TV_DAC_CNTL constants */
+#define TV_DAC_CNTL_BGSLEEP			0x00000040
+#define TV_DAC_CNTL_DETECT			0x00000010
+#define TV_DAC_CNTL_BGADJ_MASK			0x000f0000
+#define TV_DAC_CNTL_DACADJ_MASK			0x00f00000
+#define TV_DAC_CNTL_BGADJ__SHIFT		16
+#define TV_DAC_CNTL_DACADJ__SHIFT		20
+#define TV_DAC_CNTL_RDACPD			0x01000000
+#define TV_DAC_CNTL_GDACPD			0x02000000
+#define TV_DAC_CNTL_BDACPD			0x04000000
+
+/* DISP_MISC_CNTL constants */
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP	(1 << 0)
+#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP	(1 << 1)
+#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP	(1 << 2)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK	(1 << 4)
+#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK	(1 << 5)
+#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK	(1 << 6)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP	(1 << 12)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK	(1 << 15)
+#define DISP_MISC_CNTL_SOFT_RESET_LVDS		(1 << 16)
+#define DISP_MISC_CNTL_SOFT_RESET_TMDS		(1 << 17)
+#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS	(1 << 18)
+#define DISP_MISC_CNTL_SOFT_RESET_TV		(1 << 19)
+
+/* DISP_PWR_MAN constants */
+#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN	(1 << 0)
+#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN	(1 << 4)
+#define DISP_PWR_MAN_DISP_D3_RST		(1 << 16)
+#define DISP_PWR_MAN_DISP_D3_REG_RST		(1 << 17)
+#define DISP_PWR_MAN_DISP_D3_GRPH_RST		(1 << 18)
+#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST		(1 << 19)
+#define DISP_PWR_MAN_DISP_D3_OV0_RST		(1 << 20)
+#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST		(1 << 21)
+#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST	(1 << 22)
+#define DISP_PWR_MAN_DISP_D1D2_OV0_RST		(1 << 23)
+#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST	(1 << 24)
+#define DISP_PWR_MAN_TV_ENABLE_RST		(1 << 25)
+#define DISP_PWR_MAN_AUTO_PWRUP_EN		(1 << 26)
+
+/* masks */
+
+#define CONFIG_MEMSIZE_MASK		0x1f000000
+#define MEM_CFG_TYPE			0x40000000
+#define DST_OFFSET_MASK			0x003fffff
+#define DST_PITCH_MASK			0x3fc00000
+#define DEFAULT_TILE_MASK		0xc0000000
+#define PPLL_DIV_SEL_MASK		0x00000300
+#define PPLL_RESET			0x00000001
+#define PPLL_SLEEP			0x00000002
+#define PPLL_ATOMIC_UPDATE_EN		0x00010000
+#define PPLL_REF_DIV_MASK		0x000003ff
+#define PPLL_FB3_DIV_MASK		0x000007ff
+#define PPLL_POST3_DIV_MASK		0x00070000
+#define PPLL_ATOMIC_UPDATE_R		0x00008000
+#define PPLL_ATOMIC_UPDATE_W		0x00008000
+#define PPLL_VGA_ATOMIC_UPDATE_EN	0x00020000
+#define R300_PPLL_REF_DIV_ACC_MASK	(0x3ff << 18)
+#define R300_PPLL_REF_DIV_ACC_SHIFT	18
+
+#define GUI_ACTIVE			0x80000000
+
+
+#define MC_IND_INDEX			0x01F8
+#define MC_IND_DATA			0x01FC
+
+/* PAD_CTLR_STRENGTH */
+#define PAD_MANUAL_OVERRIDE		0x80000000
+
+/* pllCLK_PIN_CNTL */
+#define CLK_PIN_CNTL__OSC_EN_MASK			0x00000001L
+#define CLK_PIN_CNTL__OSC_EN				0x00000001L
+#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK			0x00000004L
+#define CLK_PIN_CNTL__XTL_LOW_GAIN			0x00000004L
+#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK		0x00000010L
+#define CLK_PIN_CNTL__DONT_USE_XTALIN			0x00000010L
+#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK		0x00000020L
+#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE			0x00000020L
+#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK		0x00000800L
+#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN			0x00000800L
+#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK	0x00001000L
+#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN		0x00001000L
+#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK	0x00002000L
+#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND		0x00002000L
+#define CLK_PIN_CNTL__CG_SPARE_MASK			0x00004000L
+#define CLK_PIN_CNTL__CG_SPARE				0x00004000L
+#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK		0x00008000L
+#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL		0x00008000L
+#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK		0x00010000L
+#define CLK_PIN_CNTL__CP_CLK_RUNNING			0x00010000L
+#define CLK_PIN_CNTL__CG_SPARE_RD_MASK			0x00060000L
+#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK		0x00080000L
+#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb			0x00080000L
+#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK			0xff000000L
+
+/* pllCLK_PWRMGT_CNTL */
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT		0x00000000
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT		0x00000001
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT		0x00000002
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT	0x00000003
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT		0x00000004
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT		0x00000005
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT		0x00000006
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT		0x00000007
+#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT		0x00000008
+#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT		0x00000009
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT		0x0000000a
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT	0x0000000c
+#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT		0x0000000d
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT	0x0000000f
+#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT			0x00000010
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT		0x00000011
+#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT		0x00000012
+#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT		0x00000013
+#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT			0x00000014
+#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT		0x00000015
+#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT		0x00000018
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT	0x0000001e
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT		0x0000001f
+
+/* pllP2PLL_CNTL */
+#define P2PLL_CNTL__P2PLL_RESET_MASK			0x00000001L
+#define P2PLL_CNTL__P2PLL_RESET				0x00000001L
+#define P2PLL_CNTL__P2PLL_SLEEP_MASK			0x00000002L
+#define P2PLL_CNTL__P2PLL_SLEEP				0x00000002L
+#define P2PLL_CNTL__P2PLL_TST_EN_MASK			0x00000004L
+#define P2PLL_CNTL__P2PLL_TST_EN			0x00000004L
+#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK		0x00000010L
+#define P2PLL_CNTL__P2PLL_REFCLK_SEL			0x00000010L
+#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK		0x00000020L
+#define P2PLL_CNTL__P2PLL_FBCLK_SEL			0x00000020L
+#define P2PLL_CNTL__P2PLL_TCPOFF_MASK			0x00000040L
+#define P2PLL_CNTL__P2PLL_TCPOFF			0x00000040L
+#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK			0x00000080L
+#define P2PLL_CNTL__P2PLL_TVCOMAX			0x00000080L
+#define P2PLL_CNTL__P2PLL_PCP_MASK			0x00000700L
+#define P2PLL_CNTL__P2PLL_PVG_MASK			0x00003800L
+#define P2PLL_CNTL__P2PLL_PDC_MASK			0x0000c000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK		0x00010000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN		0x00010000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK	0x00040000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC		0x00040000L
+#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK	0x00080000L
+#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET		0x00080000L
+
+/* pllPIXCLKS_CNTL */
+#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT		0x00000000
+#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT		0x00000004
+#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT		0x00000005
+#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT		0x00000006
+#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT	0x00000007
+#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT		0x00000008
+#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT	0x0000000b
+#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT	0x0000000c
+#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT	0x0000000d
+#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT	0x0000000e
+#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT	0x0000000f
+
+
+/* pllPIXCLKS_CNTL */
+#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK		0x00000003L
+#define PIXCLKS_CNTL__PIX2CLK_INVERT			0x00000010L
+#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT		0x00000020L
+#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb		0x00000040L
+#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb		0x00000080L
+#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL			0x00000100L
+#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb		0x00000800L
+#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb		0x00001000L
+#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb	0x00002000L
+#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb		0x00004000L
+#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb		0x00008000L
+#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb	(1 << 9)
+#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb		(1 << 10)
+#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb	(1 << 13)
+#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb	(1 << 16)
+#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb	(1 << 17)
+#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb		(1 << 18)
+#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb	(1 << 19)
+#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
+
+
+/* pllP2PLL_DIV_0 */
+#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK			0x000007ffL
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK		0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W		0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK		0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R		0x00008000L
+#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK		0x00070000L
+
+/* pllSCLK_CNTL */
+#define SCLK_CNTL__SCLK_SRC_SEL_MASK			0x00000007L
+#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT			0x00000008L
+#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT			0x00000010L
+#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT			0x00000020L
+#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT			0x00000040L
+#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT			0x00000080L
+#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT		0x00000100L
+#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT			0x00000200L
+#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT			0x00000400L
+#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT			0x00000800L
+#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT			0x00001000L
+#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT			0x00002000L
+#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT			0x00004000L
+#define SCLK_CNTL__DYN_STOP_LAT_MASK			0x00007ff8
+#define SCLK_CNTL__FORCE_DISP2				0x00008000L
+#define SCLK_CNTL__FORCE_CP				0x00010000L
+#define SCLK_CNTL__FORCE_HDP				0x00020000L
+#define SCLK_CNTL__FORCE_DISP1				0x00040000L
+#define SCLK_CNTL__FORCE_TOP				0x00080000L
+#define SCLK_CNTL__FORCE_E2				0x00100000L
+#define SCLK_CNTL__FORCE_SE				0x00200000L
+#define SCLK_CNTL__FORCE_IDCT				0x00400000L
+#define SCLK_CNTL__FORCE_VIP				0x00800000L
+#define SCLK_CNTL__FORCE_RE				0x01000000L
+#define SCLK_CNTL__FORCE_PB				0x02000000L
+#define SCLK_CNTL__FORCE_TAM				0x04000000L
+#define SCLK_CNTL__FORCE_TDM				0x08000000L
+#define SCLK_CNTL__FORCE_RB				0x10000000L
+#define SCLK_CNTL__FORCE_TV_SCLK			0x20000000L
+#define SCLK_CNTL__FORCE_SUBPIC				0x40000000L
+#define SCLK_CNTL__FORCE_OV0				0x80000000L
+#define SCLK_CNTL__R300_FORCE_VAP			(1<<21)
+#define SCLK_CNTL__R300_FORCE_SR			(1<<25)
+#define SCLK_CNTL__R300_FORCE_PX			(1<<26)
+#define SCLK_CNTL__R300_FORCE_TX			(1<<27)
+#define SCLK_CNTL__R300_FORCE_US			(1<<28)
+#define SCLK_CNTL__R300_FORCE_SU			(1<<30)
+#define SCLK_CNTL__FORCEON_MASK				0xffff8000L
+
+/* pllSCLK_CNTL2 */
+#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT		(1<<10)
+#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT		(1<<11)
+#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT		(1<<12)
+#define SCLK_CNTL2__R300_FORCE_TCL			(1<<13)
+#define SCLK_CNTL2__R300_FORCE_CBA			(1<<14)
+#define SCLK_CNTL2__R300_FORCE_GA			(1<<15)
+
+/* SCLK_MORE_CNTL */
+#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT	0x00000001L
+#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT		0x00000002L
+#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT	0x00000004L
+#define SCLK_MORE_CNTL__FORCE_DISPREGS			0x00000100L
+#define SCLK_MORE_CNTL__FORCE_MC_GUI			0x00000200L
+#define SCLK_MORE_CNTL__FORCE_MC_HOST			0x00000400L
+#define SCLK_MORE_CNTL__STOP_SCLK_EN			0x00001000L
+#define SCLK_MORE_CNTL__STOP_SCLK_A			0x00002000L
+#define SCLK_MORE_CNTL__STOP_SCLK_B			0x00004000L
+#define SCLK_MORE_CNTL__STOP_SCLK_C			0x00008000L
+#define SCLK_MORE_CNTL__HALF_SPEED_SCLK			0x00010000L
+#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP		0x00020000L
+#define SCLK_MORE_CNTL__TVFB_SOFT_RESET			0x00040000L
+#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC		0x00080000L
+#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK		0x00400000L
+#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK		0x00800000L
+#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK		0xff000000L
+#define SCLK_MORE_CNTL__FORCEON				0x00000700L
+
+/* MCLK_CNTL */
+#define MCLK_CNTL__MCLKA_SRC_SEL_MASK			0x00000007L
+#define MCLK_CNTL__YCLKA_SRC_SEL_MASK			0x00000070L
+#define MCLK_CNTL__MCLKB_SRC_SEL_MASK			0x00000700L
+#define MCLK_CNTL__YCLKB_SRC_SEL_MASK			0x00007000L
+#define MCLK_CNTL__FORCE_MCLKA_MASK			0x00010000L
+#define MCLK_CNTL__FORCE_MCLKA				0x00010000L
+#define MCLK_CNTL__FORCE_MCLKB_MASK			0x00020000L
+#define MCLK_CNTL__FORCE_MCLKB				0x00020000L
+#define MCLK_CNTL__FORCE_YCLKA_MASK			0x00040000L
+#define MCLK_CNTL__FORCE_YCLKA				0x00040000L
+#define MCLK_CNTL__FORCE_YCLKB_MASK			0x00080000L
+#define MCLK_CNTL__FORCE_YCLKB				0x00080000L
+#define MCLK_CNTL__FORCE_MC_MASK			0x00100000L
+#define MCLK_CNTL__FORCE_MC				0x00100000L
+#define MCLK_CNTL__FORCE_AIC_MASK			0x00200000L
+#define MCLK_CNTL__FORCE_AIC				0x00200000L
+#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK			0x03000000L
+#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK			0x0c000000L
+#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK			0x30000000L
+#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK			0xc0000000L
+#define MCLK_CNTL__R300_DISABLE_MC_MCLKA		(1 << 21)
+#define MCLK_CNTL__R300_DISABLE_MC_MCLKB		(1 << 21)
+
+/* MCLK_MISC */
+#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK	0x00000003L
+#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK		0x00000004L
+#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL		0x00000004L
+#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK		0x00000008L
+#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL		0x00000008L
+#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK	0x00000010L
+#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN		0x00000010L
+#define MCLK_MISC__DLL_READY_LAT_MASK			0x00000100L
+#define MCLK_MISC__DLL_READY_LAT			0x00000100L
+#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK	0x00001000L
+#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT		0x00001000L
+#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK	0x00002000L
+#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT		0x00002000L
+#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK		0x00004000L
+#define MCLK_MISC__MC_MCLK_DYN_ENABLE			0x00004000L
+#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK		0x00008000L
+#define MCLK_MISC__IO_MCLK_DYN_ENABLE			0x00008000L
+#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK		0x00010000L
+#define MCLK_MISC__CGM_CLK_TO_OUTPIN			0x00010000L
+#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK		0x00020000L
+#define MCLK_MISC__CLK_OR_COUNT_SEL			0x00020000L
+#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK	0x00040000L
+#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND		0x00040000L
+#define MCLK_MISC__CGM_SPARE_RD_MASK			0x00300000L
+#define MCLK_MISC__CGM_SPARE_A_RD_MASK			0x00c00000L
+#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK		0x01000000L
+#define MCLK_MISC__TCLK_TO_YCLKB_EN			0x01000000L
+#define MCLK_MISC__CGM_SPARE_A_MASK			0x0e000000L
+
+/* VCLK_ECP_CNTL */
+#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK		0x00000003L
+#define VCLK_ECP_CNTL__VCLK_INVERT			0x00000010L
+#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT		0x00000020L
+#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb		0x00000040L
+#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb		0x00000080L
+#define VCLK_ECP_CNTL__ECP_DIV_MASK			0x00000300L
+#define VCLK_ECP_CNTL__ECP_FORCE_ON			0x00040000L
+#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON			0x00080000L
+#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF  (1<<23)
+
+/* PLL_PWRMGT_CNTL */
+#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK		0x00000001L
+#define PLL_PWRMGT_CNTL__MPLL_TURNOFF			0x00000001L
+#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK		0x00000002L
+#define PLL_PWRMGT_CNTL__SPLL_TURNOFF			0x00000002L
+#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK		0x00000004L
+#define PLL_PWRMGT_CNTL__PPLL_TURNOFF			0x00000004L
+#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK		0x00000008L
+#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF			0x00000008L
+#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK		0x00000010L
+#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF			0x00000010L
+#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK	0x000001e0L
+#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK		0x00000600L
+#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK		0x00001800L
+#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK		0x00002000L
+#define PLL_PWRMGT_CNTL__PM_MODE_SEL			0x00002000L
+#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK	0x00004000L
+#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND		0x00004000L
+#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK	0x00008000L
+#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND		0x00008000L
+#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK			0x00010000L
+#define PLL_PWRMGT_CNTL__MOBILE_SU			0x00010000L
+#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK		0x00020000L
+#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK		0x00020000L
+#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK		0x00040000L
+#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK		0x00040000L
+#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK	0x00080000L
+#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE		0x00080000L
+#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK	0x00100000L
+#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE		0x00100000L
+#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK	0x00200000L
+#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD		0x00200000L
+#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK		0xff000000L
+
+/* CLK_PWRMGT_CNTL */
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK		0x00000001L
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF		0x00000001L
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK		0x00000002L
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF		0x00000002L
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK		0x00000004L
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF		0x00000004L
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK		0x00000008L
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF		0x00000008L
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK		0x00000010L
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF			0x00000010L
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK		0x00000020L
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF			0x00000020L
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK		0x00000040L
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF			0x00000040L
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK		0x00000080L
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF			0x00000080L
+#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK		0x00000100L
+#define CLK_PWRMGT_CNTL__MC_CH_MODE			0x00000100L
+#define CLK_PWRMGT_CNTL__TEST_MODE_MASK			0x00000200L
+#define CLK_PWRMGT_CNTL__TEST_MODE			0x00000200L
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK		0x00000400L
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN			0x00000400L
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK	0x00001000L
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE		0x00001000L
+#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK		0x00006000L
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK		0x00008000L
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT		0x00008000L
+#define CLK_PWRMGT_CNTL__MC_BUSY_MASK			0x00010000L
+#define CLK_PWRMGT_CNTL__MC_BUSY			0x00010000L
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK		0x00020000L
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL			0x00020000L
+#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK			0x00040000L
+#define CLK_PWRMGT_CNTL__MC_SWITCH			0x00040000L
+#define CLK_PWRMGT_CNTL__DLL_READY_MASK			0x00080000L
+#define CLK_PWRMGT_CNTL__DLL_READY			0x00080000L
+#define CLK_PWRMGT_CNTL__DISP_PM_MASK			0x00100000L
+#define CLK_PWRMGT_CNTL__DISP_PM			0x00100000L
+#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK		0x00e00000L
+#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK		0x3f000000L
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK		0x40000000L
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF		0x40000000L
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK		0x80000000L
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF			0x80000000L
+
+/* BUS_CNTL1 */
+#define BUS_CNTL1__PMI_IO_DISABLE_MASK			0x00000001L
+#define BUS_CNTL1__PMI_IO_DISABLE			0x00000001L
+#define BUS_CNTL1__PMI_MEM_DISABLE_MASK			0x00000002L
+#define BUS_CNTL1__PMI_MEM_DISABLE			0x00000002L
+#define BUS_CNTL1__PMI_BM_DISABLE_MASK			0x00000004L
+#define BUS_CNTL1__PMI_BM_DISABLE			0x00000004L
+#define BUS_CNTL1__PMI_INT_DISABLE_MASK			0x00000008L
+#define BUS_CNTL1__PMI_INT_DISABLE			0x00000008L
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK	0x00000020L
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE		0x00000020L
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK	0x00000100L
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS		0x00000100L
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK	0x00000200L
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS		0x00000200L
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK	0x00000400L
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS		0x00000400L
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS	0x00000800L
+#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK		0x0c000000L
+#define BUS_CNTL1__SEND_SBA_LATENCY_MASK		0x70000000L
+#define BUS_CNTL1__AGPCLK_VALID_MASK			0x80000000L
+#define BUS_CNTL1__AGPCLK_VALID				0x80000000L
+
+/* BUS_CNTL1 */
+#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT		0x00000000
+#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT		0x00000001
+#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT		0x00000002
+#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT		0x00000003
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT	0x00000005
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT	0x00000008
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT	0x00000009
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT	0x0000000a
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
+#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT		0x0000001a
+#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT		0x0000001c
+#define BUS_CNTL1__AGPCLK_VALID__SHIFT			0x0000001f
+
+/* CRTC_OFFSET_CNTL */
+#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK		0x0000000fL
+#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK	0x000000f0L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK	0x00004000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT		0x00004000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK		0x00008000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN			0x00008000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK	0x00010000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL		0x00010000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK	0x00020000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN		0x00020000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK	0x000c0000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK	0x00100000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN	0x00100000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK		0x00200000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC		0x00200000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN	0x10000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN	0x20000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK	0x40000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET		0x40000000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK		0x80000000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK		0x80000000L
+
+/* CRTC_GEN_CNTL */
+#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK		0x00000001L
+#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN			0x00000001L
+#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK		0x00000002L
+#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN		0x00000002L
+#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK		0x00000010L
+#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN			0x00000010L
+#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK		0x00000f00L
+#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK		0x00008000L
+#define CRTC_GEN_CNTL__CRTC_ICON_EN			0x00008000L
+#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK			0x00010000L
+#define CRTC_GEN_CNTL__CRTC_CUR_EN			0x00010000L
+#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK		0x00060000L
+#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK		0x00700000L
+#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK		0x01000000L
+#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN			0x01000000L
+#define CRTC_GEN_CNTL__CRTC_EN_MASK			0x02000000L
+#define CRTC_GEN_CNTL__CRTC_EN				0x02000000L
+#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK		0x04000000L
+#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B		0x04000000L
+
+/* CRTC2_GEN_CNTL */
+#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK		0x00000001L
+#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN		0x00000001L
+#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK		0x00000002L
+#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN		0x00000002L
+#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK	0x00000010L
+#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE		0x00000010L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK	0x00000020L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE		0x00000020L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK	0x00000040L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE		0x00000040L
+#define CRTC2_GEN_CNTL__CRT2_ON_MASK			0x00000080L
+#define CRTC2_GEN_CNTL__CRT2_ON				0x00000080L
+#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK		0x00000f00L
+#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK		0x00008000L
+#define CRTC2_GEN_CNTL__CRTC2_ICON_EN			0x00008000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK		0x00010000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_EN			0x00010000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK		0x00700000L
+#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK		0x00800000L
+#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS		0x00800000L
+#define CRTC2_GEN_CNTL__CRTC2_EN_MASK			0x02000000L
+#define CRTC2_GEN_CNTL__CRTC2_EN			0x02000000L
+#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK	0x04000000L
+#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B		0x04000000L
+#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK		0x08000000L
+#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN			0x08000000L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK		0x10000000L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS			0x10000000L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK		0x20000000L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS			0x20000000L
+
+/* AGP_CNTL */
+#define AGP_CNTL__MAX_IDLE_CLK_MASK			0x000000ffL
+#define AGP_CNTL__HOLD_RD_FIFO_MASK			0x00000100L
+#define AGP_CNTL__HOLD_RD_FIFO				0x00000100L
+#define AGP_CNTL__HOLD_RQ_FIFO_MASK			0x00000200L
+#define AGP_CNTL__HOLD_RQ_FIFO				0x00000200L
+#define AGP_CNTL__EN_2X_STBB_MASK			0x00000400L
+#define AGP_CNTL__EN_2X_STBB				0x00000400L
+#define AGP_CNTL__FORCE_FULL_SBA_MASK			0x00000800L
+#define AGP_CNTL__FORCE_FULL_SBA			0x00000800L
+#define AGP_CNTL__SBA_DIS_MASK				0x00001000L
+#define AGP_CNTL__SBA_DIS				0x00001000L
+#define AGP_CNTL__AGP_REV_ID_MASK			0x00002000L
+#define AGP_CNTL__AGP_REV_ID				0x00002000L
+#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK		0x00004000L
+#define AGP_CNTL__REG_CRIPPLE_AGP4X			0x00004000L
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK		0x00008000L
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X			0x00008000L
+#define AGP_CNTL__FORCE_INT_VREF_MASK			0x00010000L
+#define AGP_CNTL__FORCE_INT_VREF			0x00010000L
+#define AGP_CNTL__PENDING_SLOTS_VAL_MASK		0x00060000L
+#define AGP_CNTL__PENDING_SLOTS_SEL_MASK		0x00080000L
+#define AGP_CNTL__PENDING_SLOTS_SEL			0x00080000L
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK		0x00100000L
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X			0x00100000L
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK		0x00200000L
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX			0x00200000L
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK		0x00400000L
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET		0x00400000L
+#define AGP_CNTL__EN_RBFCALM_MASK			0x00800000L
+#define AGP_CNTL__EN_RBFCALM				0x00800000L
+#define AGP_CNTL__FORCE_EXT_VREF_MASK			0x01000000L
+#define AGP_CNTL__FORCE_EXT_VREF			0x01000000L
+#define AGP_CNTL__DIS_RBF_MASK				0x02000000L
+#define AGP_CNTL__DIS_RBF				0x02000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK		0x04000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_EN			0x04000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK		0x38000000L
+#define AGP_CNTL__AGP_MISC_MASK				0xc0000000L
+
+/* AGP_CNTL */
+#define AGP_CNTL__MAX_IDLE_CLK__SHIFT			0x00000000
+#define AGP_CNTL__HOLD_RD_FIFO__SHIFT			0x00000008
+#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT			0x00000009
+#define AGP_CNTL__EN_2X_STBB__SHIFT			0x0000000a
+#define AGP_CNTL__FORCE_FULL_SBA__SHIFT			0x0000000b
+#define AGP_CNTL__SBA_DIS__SHIFT			0x0000000c
+#define AGP_CNTL__AGP_REV_ID__SHIFT			0x0000000d
+#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT		0x0000000e
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT		0x0000000f
+#define AGP_CNTL__FORCE_INT_VREF__SHIFT			0x00000010
+#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT		0x00000011
+#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT		0x00000013
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT		0x00000014
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT		0x00000015
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT	0x00000016
+#define AGP_CNTL__EN_RBFCALM__SHIFT			0x00000017
+#define AGP_CNTL__FORCE_EXT_VREF__SHIFT			0x00000018
+#define AGP_CNTL__DIS_RBF__SHIFT			0x00000019
+#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT		0x0000001a
+#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT		0x0000001b
+#define AGP_CNTL__AGP_MISC__SHIFT			0x0000001e
+
+/* DISP_MISC_CNTL */
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK		0x00000001L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP		0x00000001L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK	0x00000002L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP		0x00000002L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK		0x00000004L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP		0x00000004L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK	0x00000010L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK		0x00000010L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK	0x00000020L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK		0x00000020L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK	0x00000040L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK		0x00000040L
+#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK		0x00000300L
+#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK		0x00000400L
+#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN		0x00000400L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK	0x00001000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP		0x00001000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK	0x00008000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK		0x00008000L
+#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK		0x00010000L
+#define DISP_MISC_CNTL__SOFT_RESET_LVDS			0x00010000L
+#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK		0x00020000L
+#define DISP_MISC_CNTL__SOFT_RESET_TMDS			0x00020000L
+#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK	0x00040000L
+#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS		0x00040000L
+#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK		0x00080000L
+#define DISP_MISC_CNTL__SOFT_RESET_TV			0x00080000L
+#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK	0x00f00000L
+#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK	0x0f000000L
+#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK	0xf0000000L
+
+/* DISP_PWR_MAN */
+#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK	0x00000001L
+#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN		0x00000001L
+#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK	0x00000010L
+#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN		0x00000010L
+#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK		0x00000300L
+#define DISP_PWR_MAN__DISP_D3_RST_MASK			0x00010000L
+#define DISP_PWR_MAN__DISP_D3_RST			0x00010000L
+#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK		0x00020000L
+#define DISP_PWR_MAN__DISP_D3_REG_RST			0x00020000L
+#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK		0x00040000L
+#define DISP_PWR_MAN__DISP_D3_GRPH_RST			0x00040000L
+#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK		0x00080000L
+#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST		0x00080000L
+#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK		0x00100000L
+#define DISP_PWR_MAN__DISP_D3_OV0_RST			0x00100000L
+#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK		0x00200000L
+#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST		0x00200000L
+#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK		0x00400000L
+#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST		0x00400000L
+#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK		0x00800000L
+#define DISP_PWR_MAN__DISP_D1D2_OV0_RST			0x00800000L
+#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK		0x01000000L
+#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST		0x01000000L
+#define DISP_PWR_MAN__TV_ENABLE_RST_MASK		0x02000000L
+#define DISP_PWR_MAN__TV_ENABLE_RST			0x02000000L
+#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK		0x04000000L
+#define DISP_PWR_MAN__AUTO_PWRUP_EN			0x04000000L
+
+/* MC_IND_INDEX */
+#define MC_IND_INDEX__MC_IND_ADDR_MASK			0x0000001fL
+#define MC_IND_INDEX__MC_IND_WR_EN_MASK			0x00000100L
+#define MC_IND_INDEX__MC_IND_WR_EN			0x00000100L
+
+/* MC_IND_DATA */
+#define MC_IND_DATA__MC_IND_DATA_MASK			0xffffffffL
+
+/* MC_CHP_IO_CNTL_A1 */
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT		0x00000000
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT		0x00000001
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT	0x00000002
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT	0x00000003
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT		0x00000004
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT		0x00000005
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT	0x00000006
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT	0x00000007
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT		0x00000008
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT	0x00000009
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT	0x0000000a
+#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT		0x0000000c
+#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT		0x0000000e
+#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT		0x00000010
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT		0x00000012
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT		0x00000014
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT	0x00000016
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT	0x00000017
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT		0x00000018
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT		0x0000001a
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT		0x0000001c
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT	0x0000001e
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT	0x0000001f
+
+/* MC_CHP_IO_CNTL_B1 */
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT		0x00000000
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT		0x00000001
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT	0x00000002
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT	0x00000003
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT		0x00000004
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT		0x00000005
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT	0x00000006
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT	0x00000007
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT		0x00000008
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT	0x00000009
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT	0x0000000a
+#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT		0x0000000c
+#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT		0x0000000e
+#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT		0x00000010
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT		0x00000012
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT		0x00000014
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT	0x00000016
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT	0x00000017
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT		0x00000018
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT		0x0000001a
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT		0x0000001c
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT	0x0000001e
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT	0x0000001f
+
+/* MC_CHP_IO_CNTL_A1 */
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK		0x00000001L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA		0x00000001L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK		0x00000002L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA			0x00000002L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK		0x00000004L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA		0x00000004L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK		0x00000008L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA		0x00000008L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK		0x00000010L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA		0x00000010L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK		0x00000020L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA			0x00000020L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK		0x00000040L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA		0x00000040L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK		0x00000080L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA		0x00000080L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK		0x00000100L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA		0x00000100L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK		0x00000200L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA		0x00000200L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK		0x00000400L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA		0x00000400L
+#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK		0x00003000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK		0x0000c000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK		0x00030000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK		0x000c0000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK		0x00300000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK		0x00400000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA		0x00400000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK	0x00800000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA		0x00800000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK		0x03000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK		0x0c000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK		0x10000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA			0x10000000L
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK	0x40000000L
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A		0x40000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK	0x80000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A		0x80000000L
+
+/* MC_CHP_IO_CNTL_B1 */
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK		0x00000001L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB		0x00000001L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK		0x00000002L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB			0x00000002L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK		0x00000004L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB		0x00000004L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK		0x00000008L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB		0x00000008L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK		0x00000010L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB		0x00000010L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK		0x00000020L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB			0x00000020L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK		0x00000040L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB		0x00000040L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK		0x00000080L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB		0x00000080L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK		0x00000100L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB		0x00000100L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK		0x00000200L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB		0x00000200L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK		0x00000400L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB		0x00000400L
+#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK		0x00003000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK		0x0000c000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK		0x00030000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK		0x000c0000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK		0x00300000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK		0x00400000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB		0x00400000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK	0x00800000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB		0x00800000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK		0x03000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK		0x0c000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK		0x10000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB			0x10000000L
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK	0x40000000L
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B		0x40000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK	0x80000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B		0x80000000L
+
+/* MEM_SDRAM_MODE_REG */
+#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK		0x00007fffL
+#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK		0x000f0000L
+#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK	0x00700000L
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK	0x00800000L
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY		0x00800000L
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK	0x01000000L
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY		0x01000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK	0x02000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD		0x02000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK	0x04000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA		0x04000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK	0x08000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR		0x08000000L
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK	0x10000000L
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE		0x10000000L
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK		0x20000000L
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL			0x20000000L
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK		0x40000000L
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE		0x40000000L
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK	0x80000000L
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET		0x80000000L
+
+/* MEM_SDRAM_MODE_REG */
+#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT		0x00000000
+#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT	0x00000010
+#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT	0x00000014
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT	0x00000017
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT	0x00000018
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT	0x00000019
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT	0x0000001a
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT	0x0000001b
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT	0x0000001c
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT		0x0000001d
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT		0x0000001e
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT	0x0000001f
+
+/* MEM_REFRESH_CNTL */
+#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK		0x000000ffL
+#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK		0x00000100L
+#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS		0x00000100L
+#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK		0x00000200L
+#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE		0x00000200L
+#define MEM_REFRESH_CNTL__MEM_TRFC_MASK			0x0000f000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK		0x00010000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE		0x00010000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK	0x00020000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE		0x00020000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK		0x00040000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE		0x00040000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK	0x00080000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE		0x00080000L
+#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK	0x00100000L
+#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE		0x00100000L
+#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK		0x00c00000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK		0x01000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE		0x01000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK	0x02000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE		0x02000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK		0x04000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE		0x04000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK	0x08000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE		0x08000000L
+#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK	0x10000000L
+#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE		0x10000000L
+#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK		0xc0000000L
+
+/* MC_STATUS */
+#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK		0x00000001L
+#define MC_STATUS__MEM_PWRUP_COMPL_A			0x00000001L
+#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK		0x00000002L
+#define MC_STATUS__MEM_PWRUP_COMPL_B			0x00000002L
+#define MC_STATUS__MC_IDLE_MASK				0x00000004L
+#define MC_STATUS__MC_IDLE				0x00000004L
+#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK		0x00000078L
+#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK		0x00000780L
+#define MC_STATUS__TEST_OUT_R_BACK_MASK			0x00000800L
+#define MC_STATUS__TEST_OUT_R_BACK			0x00000800L
+#define MC_STATUS__DUMMY_OUT_R_BACK_MASK		0x00001000L
+#define MC_STATUS__DUMMY_OUT_R_BACK			0x00001000L
+#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK		0x0001e000L
+#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK		0x001e0000L
+#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK		0x01e00000L
+#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK		0x1e000000L
+
+/* MDLL_CKO */
+#define MDLL_CKO__MCKOA_SLEEP_MASK			0x00000001L
+#define MDLL_CKO__MCKOA_SLEEP				0x00000001L
+#define MDLL_CKO__MCKOA_RESET_MASK			0x00000002L
+#define MDLL_CKO__MCKOA_RESET				0x00000002L
+#define MDLL_CKO__MCKOA_RANGE_MASK			0x0000000cL
+#define MDLL_CKO__ERSTA_SOUTSEL_MASK			0x00000030L
+#define MDLL_CKO__MCKOA_FB_SEL_MASK			0x000000c0L
+#define MDLL_CKO__MCKOA_REF_SKEW_MASK			0x00000700L
+#define MDLL_CKO__MCKOA_FB_SKEW_MASK			0x00007000L
+#define MDLL_CKO__MCKOA_BP_SEL_MASK			0x00008000L
+#define MDLL_CKO__MCKOA_BP_SEL				0x00008000L
+#define MDLL_CKO__MCKOB_SLEEP_MASK			0x00010000L
+#define MDLL_CKO__MCKOB_SLEEP				0x00010000L
+#define MDLL_CKO__MCKOB_RESET_MASK			0x00020000L
+#define MDLL_CKO__MCKOB_RESET				0x00020000L
+#define MDLL_CKO__MCKOB_RANGE_MASK			0x000c0000L
+#define MDLL_CKO__ERSTB_SOUTSEL_MASK			0x00300000L
+#define MDLL_CKO__MCKOB_FB_SEL_MASK			0x00c00000L
+#define MDLL_CKO__MCKOB_REF_SKEW_MASK			0x07000000L
+#define MDLL_CKO__MCKOB_FB_SKEW_MASK			0x70000000L
+#define MDLL_CKO__MCKOB_BP_SEL_MASK			0x80000000L
+#define MDLL_CKO__MCKOB_BP_SEL				0x80000000L
+
+/* MDLL_RDCKA */
+#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK			0x00000001L
+#define MDLL_RDCKA__MRDCKA0_SLEEP			0x00000001L
+#define MDLL_RDCKA__MRDCKA0_RESET_MASK			0x00000002L
+#define MDLL_RDCKA__MRDCKA0_RESET			0x00000002L
+#define MDLL_RDCKA__MRDCKA0_RANGE_MASK			0x0000000cL
+#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK		0x00000030L
+#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK			0x000000c0L
+#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK		0x00000700L
+#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK			0x00000800L
+#define MDLL_RDCKA__MRDCKA0_SINSEL			0x00000800L
+#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK		0x00007000L
+#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK			0x00008000L
+#define MDLL_RDCKA__MRDCKA0_BP_SEL			0x00008000L
+#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK			0x00010000L
+#define MDLL_RDCKA__MRDCKA1_SLEEP			0x00010000L
+#define MDLL_RDCKA__MRDCKA1_RESET_MASK			0x00020000L
+#define MDLL_RDCKA__MRDCKA1_RESET			0x00020000L
+#define MDLL_RDCKA__MRDCKA1_RANGE_MASK			0x000c0000L
+#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK		0x00300000L
+#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK			0x00c00000L
+#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK		0x07000000L
+#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK			0x08000000L
+#define MDLL_RDCKA__MRDCKA1_SINSEL			0x08000000L
+#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK		0x70000000L
+#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK			0x80000000L
+#define MDLL_RDCKA__MRDCKA1_BP_SEL			0x80000000L
+
+/* MDLL_RDCKB */
+#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK			0x00000001L
+#define MDLL_RDCKB__MRDCKB0_SLEEP			0x00000001L
+#define MDLL_RDCKB__MRDCKB0_RESET_MASK			0x00000002L
+#define MDLL_RDCKB__MRDCKB0_RESET			0x00000002L
+#define MDLL_RDCKB__MRDCKB0_RANGE_MASK			0x0000000cL
+#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK		0x00000030L
+#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK			0x000000c0L
+#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK		0x00000700L
+#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK			0x00000800L
+#define MDLL_RDCKB__MRDCKB0_SINSEL			0x00000800L
+#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK		0x00007000L
+#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK			0x00008000L
+#define MDLL_RDCKB__MRDCKB0_BP_SEL			0x00008000L
+#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK			0x00010000L
+#define MDLL_RDCKB__MRDCKB1_SLEEP			0x00010000L
+#define MDLL_RDCKB__MRDCKB1_RESET_MASK			0x00020000L
+#define MDLL_RDCKB__MRDCKB1_RESET			0x00020000L
+#define MDLL_RDCKB__MRDCKB1_RANGE_MASK			0x000c0000L
+#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK		0x00300000L
+#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK			0x00c00000L
+#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK		0x07000000L
+#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK			0x08000000L
+#define MDLL_RDCKB__MRDCKB1_SINSEL			0x08000000L
+#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK		0x70000000L
+#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK			0x80000000L
+#define MDLL_RDCKB__MRDCKB1_BP_SEL			0x80000000L
+
+#define MDLL_R300_RDCK__MRDCKA_SLEEP			0x00000001L
+#define MDLL_R300_RDCK__MRDCKA_RESET			0x00000002L
+#define MDLL_R300_RDCK__MRDCKB_SLEEP			0x00000004L
+#define MDLL_R300_RDCK__MRDCKB_RESET			0x00000008L
+#define MDLL_R300_RDCK__MRDCKC_SLEEP			0x00000010L
+#define MDLL_R300_RDCK__MRDCKC_RESET			0x00000020L
+#define MDLL_R300_RDCK__MRDCKD_SLEEP			0x00000040L
+#define MDLL_R300_RDCK__MRDCKD_RESET			0x00000080L
+
+#define pllCLK_PIN_CNTL				0x0001
+#define pllPPLL_CNTL				0x0002
+#define pllPPLL_REF_DIV				0x0003
+#define pllPPLL_DIV_0				0x0004
+#define pllPPLL_DIV_1				0x0005
+#define pllPPLL_DIV_2				0x0006
+#define pllPPLL_DIV_3				0x0007
+#define pllVCLK_ECP_CNTL			0x0008
+#define pllHTOTAL_CNTL				0x0009
+#define pllM_SPLL_REF_FB_DIV			0x000A
+#define pllAGP_PLL_CNTL				0x000B
+#define pllSPLL_CNTL				0x000C
+#define pllSCLK_CNTL				0x000D
+#define pllMPLL_CNTL				0x000E
+#define pllMDLL_CKO				0x000F
+#define pllMDLL_RDCKA				0x0010
+#define pllMDLL_RDCKB				0x0011
+#define pllMCLK_CNTL				0x0012
+#define pllPLL_TEST_CNTL			0x0013
+#define pllCLK_PWRMGT_CNTL			0x0014
+#define pllPLL_PWRMGT_CNTL			0x0015
+#define pllCG_TEST_MACRO_RW_WRITE		0x0016
+#define pllCG_TEST_MACRO_RW_READ		0x0017
+#define pllCG_TEST_MACRO_RW_DATA		0x0018
+#define pllCG_TEST_MACRO_RW_CNTL		0x0019
+#define pllDISP_TEST_MACRO_RW_WRITE		0x001A
+#define pllDISP_TEST_MACRO_RW_READ		0x001B
+#define pllDISP_TEST_MACRO_RW_DATA		0x001C
+#define pllDISP_TEST_MACRO_RW_CNTL		0x001D
+#define pllSCLK_CNTL2				0x001E
+#define pllMCLK_MISC				0x001F
+#define pllTV_PLL_FINE_CNTL			0x0020
+#define pllTV_PLL_CNTL				0x0021
+#define pllTV_PLL_CNTL1				0x0022
+#define pllTV_DTO_INCREMENTS			0x0023
+#define pllSPLL_AUX_CNTL			0x0024
+#define pllMPLL_AUX_CNTL			0x0025
+#define pllP2PLL_CNTL				0x002A
+#define pllP2PLL_REF_DIV			0x002B
+#define pllP2PLL_DIV_0				0x002C
+#define pllPIXCLKS_CNTL				0x002D
+#define pllHTOTAL2_CNTL				0x002E
+#define pllSSPLL_CNTL				0x0030
+#define pllSSPLL_REF_DIV			0x0031
+#define pllSSPLL_DIV_0				0x0032
+#define pllSS_INT_CNTL				0x0033
+#define pllSS_TST_CNTL				0x0034
+#define pllSCLK_MORE_CNTL			0x0035
+
+#define ixMC_PERF_CNTL				0x0000
+#define ixMC_PERF_SEL				0x0001
+#define ixMC_PERF_REGION_0			0x0002
+#define ixMC_PERF_REGION_1			0x0003
+#define ixMC_PERF_COUNT_0			0x0004
+#define ixMC_PERF_COUNT_1			0x0005
+#define ixMC_PERF_COUNT_2			0x0006
+#define ixMC_PERF_COUNT_3			0x0007
+#define ixMC_PERF_COUNT_MEMCH_A			0x0008
+#define ixMC_PERF_COUNT_MEMCH_B			0x0009
+#define ixMC_IMP_CNTL				0x000A
+#define ixMC_CHP_IO_CNTL_A0			0x000B
+#define ixMC_CHP_IO_CNTL_A1			0x000C
+#define ixMC_CHP_IO_CNTL_B0			0x000D
+#define ixMC_CHP_IO_CNTL_B1			0x000E
+#define ixMC_IMP_CNTL_0				0x000F
+#define ixTC_MISMATCH_1				0x0010
+#define ixTC_MISMATCH_2				0x0011
+#define ixMC_BIST_CTRL				0x0012
+#define ixREG_COLLAR_WRITE			0x0013
+#define ixREG_COLLAR_READ			0x0014
+#define ixR300_MC_IMP_CNTL			0x0018
+#define ixR300_MC_CHP_IO_CNTL_A0		0x0019
+#define ixR300_MC_CHP_IO_CNTL_A1		0x001a
+#define ixR300_MC_CHP_IO_CNTL_B0		0x001b
+#define ixR300_MC_CHP_IO_CNTL_B1		0x001c
+#define ixR300_MC_CHP_IO_CNTL_C0		0x001d
+#define ixR300_MC_CHP_IO_CNTL_C1		0x001e
+#define ixR300_MC_CHP_IO_CNTL_D0		0x001f
+#define ixR300_MC_CHP_IO_CNTL_D1		0x0020
+#define ixR300_MC_IMP_CNTL_0			0x0021
+#define ixR300_MC_ELPIDA_CNTL			0x0022
+#define ixR300_MC_CHP_IO_OE_CNTL_CD		0x0023
+#define ixR300_MC_READ_CNTL_CD			0x0024
+#define ixR300_MC_MC_INIT_WR_LAT_TIMER		0x0025
+#define ixR300_MC_DEBUG_CNTL			0x0026
+#define ixR300_MC_BIST_CNTL_0			0x0028
+#define ixR300_MC_BIST_CNTL_1			0x0029
+#define ixR300_MC_BIST_CNTL_2			0x002a
+#define ixR300_MC_BIST_CNTL_3			0x002b
+#define ixR300_MC_BIST_CNTL_4			0x002c
+#define ixR300_MC_BIST_CNTL_5			0x002d
+#define ixR300_MC_IMP_STATUS			0x002e
+#define ixR300_MC_DLL_CNTL			0x002f
+#define NB_TOM					0x15C
+
+#endif	/* _RADEON_H */
diff --git a/include/ram.h b/include/ram.h
new file mode 100644
index 0000000..67e22d7
--- /dev/null
+++ b/include/ram.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __RAM_H
+#define __RAM_H
+
+struct ram_info {
+	phys_addr_t base;
+	size_t size;
+};
+
+struct ram_ops {
+	/**
+	 * get_info() - Get basic memory info
+	 *
+	 * @dev:	Device to check (UCLASS_RAM)
+	 * @info:	Place to put info
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_info)(struct udevice *dev, struct ram_info *info);
+};
+
+#define ram_get_ops(dev)        ((struct ram_ops *)(dev)->driver->ops)
+
+/**
+ * ram_get_info() - Get information about a RAM device
+ *
+ * @dev:	Device to check (UCLASS_RAM)
+ * @info:	Returns RAM info
+ * @return 0 if OK, -ve on error
+ */
+int ram_get_info(struct udevice *dev, struct ram_info *info);
+
+#endif
diff --git a/include/rc4.h b/include/rc4.h
new file mode 100644
index 0000000..c1ff134
--- /dev/null
+++ b/include/rc4.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ */
+
+#ifndef __RC4_H
+#define __RC4_H
+
+/**
+ * rc4_encode() - encode a buf with the RC4 cipher
+ *
+ * @buf:	Buffer to encode (it is overwrite in the process
+ * @len:	Length of buffer in bytes
+ * @key:	16-byte key to use
+ */
+void rc4_encode(unsigned char *buf, unsigned int len, unsigned char key[16]);
+
+#endif
diff --git a/include/regmap.h b/include/regmap.h
new file mode 100644
index 0000000..0854200
--- /dev/null
+++ b/include/regmap.h
@@ -0,0 +1,352 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __REGMAP_H
+#define __REGMAP_H
+
+/**
+ * DOC: Overview
+ *
+ * Regmaps are an abstraction mechanism that allows device drivers to access
+ * register maps irrespective of the underlying bus architecture. This entails
+ * that for devices that support multiple busses (e.g. I2C and SPI for a GPIO
+ * expander chip) only one driver has to be written. This driver will
+ * instantiate a regmap with a backend depending on the bus the device is
+ * attached to, and use the regmap API to access the register map through that
+ * bus transparently.
+ *
+ * Read and write functions are supplied, which can read/write data of
+ * arbitrary length from/to the regmap.
+ *
+ * The endianness of regmap accesses is selectable for each map through device
+ * tree settings via the boolean "little-endian", "big-endian", and
+ * "native-endian" properties.
+ *
+ * Furthermore, the register map described by a regmap can be split into
+ * multiple disjoint areas called ranges. In this way, register maps with
+ * "holes", i.e. areas of addressable memory that are not part of the register
+ * map, can be accessed in a concise manner.
+ *
+ * Currently, only a bare "mem" backend for regmaps is supported, which
+ * accesses the register map as regular IO-mapped memory.
+ */
+
+/**
+ * enum regmap_size_t - Access sizes for regmap reads and writes
+ *
+ * @REGMAP_SIZE_8: 8-bit read/write access size
+ * @REGMAP_SIZE_16: 16-bit read/write access size
+ * @REGMAP_SIZE_32: 32-bit read/write access size
+ * @REGMAP_SIZE_64: 64-bit read/write access size
+ */
+enum regmap_size_t {
+	REGMAP_SIZE_8 = 1,
+	REGMAP_SIZE_16 = 2,
+	REGMAP_SIZE_32 = 4,
+	REGMAP_SIZE_64 = 8,
+};
+
+/**
+ * enum regmap_endianness_t - Endianness for regmap reads and writes
+ *
+ * @REGMAP_NATIVE_ENDIAN: Native endian read/write accesses
+ * @REGMAP_LITTLE_ENDIAN: Little endian read/write accesses
+ * @REGMAP_BIG_ENDIAN: Big endian read/write accesses
+ */
+enum regmap_endianness_t {
+	REGMAP_NATIVE_ENDIAN,
+	REGMAP_LITTLE_ENDIAN,
+	REGMAP_BIG_ENDIAN,
+};
+
+/**
+ * struct regmap_range - a register map range
+ *
+ * @start:	Start address
+ * @size:	Size in bytes
+ */
+struct regmap_range {
+	ulong start;
+	ulong size;
+};
+
+/**
+ * struct regmap - a way of accessing hardware/bus registers
+ *
+ * @range_count:	Number of ranges available within the map
+ * @ranges:		Array of ranges
+ */
+struct regmap {
+	enum regmap_endianness_t endianness;
+	int range_count;
+	struct regmap_range ranges[0];
+};
+
+/*
+ * Interface to provide access to registers either through a direct memory
+ * bus or through a peripheral bus like I2C, SPI.
+ */
+
+/**
+ * regmap_write() - Write a 32-bit value to a regmap
+ *
+ * @map:	Regmap to write to
+ * @offset:	Offset in the regmap to write to
+ * @val:	Data to write to the regmap at the specified offset
+ *
+ * Note that this function will only write values of 32 bit width to the
+ * regmap; if the size of data to be read is different, the regmap_raw_write
+ * function can be used.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int regmap_write(struct regmap *map, uint offset, uint val);
+
+/**
+ * regmap_read() - Read a 32-bit value from a regmap
+ *
+ * @map:	Regmap to read from
+ * @offset:	Offset in the regmap to read from
+ * @valp:	Pointer to the buffer to receive the data read from the regmap
+ *		at the specified offset
+ *
+ * Note that this function will only read values of 32 bit width from the
+ * regmap; if the size of data to be read is different, the regmap_raw_read
+ * function can be used.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int regmap_read(struct regmap *map, uint offset, uint *valp);
+
+/**
+ * regmap_raw_write() - Write a value of specified length to a regmap
+ *
+ * @map:	Regmap to write to
+ * @offset:	Offset in the regmap to write to
+ * @val:	Value to write to the regmap at the specified offset
+ * @val_len:	Length of the data to be written to the regmap
+ *
+ * Note that this function will, as opposed to regmap_write, write data of
+ * arbitrary length to the regmap, and not just 32-bit values, and is thus a
+ * generalized version of regmap_write.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int regmap_raw_write(struct regmap *map, uint offset, const void *val,
+		     size_t val_len);
+
+/**
+ * regmap_raw_read() - Read a value of specified length from a regmap
+ *
+ * @map:	Regmap to read from
+ * @offset:	Offset in the regmap to read from
+ * @valp:	Pointer to the buffer to receive the data read from the regmap
+ *		at the specified offset
+ * @val_len:	Length of the data to be read from the regmap
+ *
+ * Note that this function will, as opposed to regmap_read, read data of
+ * arbitrary length from the regmap, and not just 32-bit values, and is thus a
+ * generalized version of regmap_read.
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int regmap_raw_read(struct regmap *map, uint offset, void *valp,
+		    size_t val_len);
+
+/**
+ * regmap_raw_write_range() - Write a value of specified length to a range of a
+ *			      regmap
+ *
+ * @map:	Regmap to write to
+ * @range_num:	Number of the range in the regmap to write to
+ * @offset:	Offset in the regmap to write to
+ * @val:	Value to write to the regmap at the specified offset
+ * @val_len:	Length of the data to be written to the regmap
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset,
+			   const void *val, size_t val_len);
+
+/**
+ * regmap_raw_read_range() - Read a value of specified length from a range of a
+ *			     regmap
+ *
+ * @map:	Regmap to read from
+ * @range_num:	Number of the range in the regmap to write to
+ * @offset:	Offset in the regmap to read from
+ * @valp:	Pointer to the buffer to receive the data read from the regmap
+ *		at the specified offset
+ * @val_len:	Length of the data to be read from the regmap
+ *
+ * Return: 0 if OK, -ve on error
+ */
+int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset,
+			  void *valp, size_t val_len);
+
+/**
+ * regmap_range_set() - Set a value in a regmap range described by a struct
+ * @map:    Regmap in which a value should be set
+ * @range:  Range of the regmap in which a value should be set
+ * @type:   Structure type that describes the memory layout of the regmap range
+ * @member: Member of the describing structure that should be set in the regmap
+ *          range
+ * @val:    Value which should be written to the regmap range
+ */
+#define regmap_range_set(map, range, type, member, val) \
+	do { \
+		typeof(((type *)0)->member) __tmp = val; \
+		regmap_raw_write_range(map, range, offsetof(type, member), \
+				       &__tmp, sizeof(((type *)0)->member)); \
+	} while (0)
+
+/**
+ * regmap_set() - Set a value in a regmap described by a struct
+ * @map:    Regmap in which a value should be set
+ * @type:   Structure type that describes the memory layout of the regmap
+ * @member: Member of the describing structure that should be set in the regmap
+ * @val:    Value which should be written to the regmap
+ */
+#define regmap_set(map, type, member, val) \
+	regmap_range_set(map, 0, type, member, val)
+
+/**
+ * regmap_range_get() - Get a value from a regmap range described by a struct
+ * @map:    Regmap from which a value should be read
+ * @range:  Range of the regmap from which a value should be read
+ * @type:   Structure type that describes the memory layout of the regmap
+ *          range
+ * @member: Member of the describing structure that should be read in the
+ *          regmap range
+ * @valp:   Variable that receives the value read from the regmap range
+ */
+#define regmap_range_get(map, range, type, member, valp) \
+	regmap_raw_read_range(map, range, offsetof(type, member), \
+			      (void *)valp, sizeof(((type *)0)->member))
+
+/**
+ * regmap_get() - Get a value from a regmap described by a struct
+ * @map:    Regmap from which a value should be read
+ * @type:   Structure type that describes the memory layout of the regmap
+ *          range
+ * @member: Member of the describing structure that should be read in the
+ *          regmap
+ * @valp:   Variable that receives the value read from the regmap
+ */
+#define regmap_get(map, type, member, valp) \
+	regmap_range_get(map, 0, type, member, valp)
+
+/**
+ * regmap_read_poll_timeout - Poll until a condition is met or a timeout occurs
+ *
+ * @map:	Regmap to read from
+ * @addr:	Offset to poll
+ * @val:	Unsigned integer variable to read the value into
+ * @cond:	Break condition (usually involving @val)
+ * @sleep_us:	Maximum time to sleep between reads in us (0 tight-loops).
+ * @timeout_ms:	Timeout in ms, 0 means never timeout
+ * @test_add_time: Used for sandbox testing - amount of time to add after
+ *		starting the loop (0 if not testing)
+ *
+ * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read
+ * error return value in case of a error read. In the two former cases,
+ * the last read value at @addr is stored in @val. Must not be called
+ * from atomic context if sleep_us or timeout_us are used.
+ *
+ * This is modelled after the regmap_read_poll_timeout macros in linux but
+ * with millisecond timeout.
+ *
+ * The _test version is for sandbox testing only. Do not use this in normal
+ * code as it advances the timer.
+ */
+#define regmap_read_poll_timeout_test(map, addr, val, cond, sleep_us, \
+				      timeout_ms, test_add_time) \
+({ \
+	unsigned long __start = get_timer(0); \
+	int __ret; \
+	for (;;) { \
+		__ret = regmap_read((map), (addr), &(val)); \
+		if (__ret) \
+			break; \
+		if (cond) \
+			break; \
+		if (IS_ENABLED(CONFIG_SANDBOX) && test_add_time) \
+			timer_test_add_offset(test_add_time); \
+		if ((timeout_ms) && get_timer(__start) > (timeout_ms)) { \
+			__ret = regmap_read((map), (addr), &(val)); \
+			break; \
+		} \
+		if ((sleep_us)) \
+			udelay((sleep_us)); \
+	} \
+	__ret ?: ((cond) ? 0 : -ETIMEDOUT); \
+})
+
+#define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, timeout_ms) \
+	regmap_read_poll_timeout_test(map, addr, val, cond, sleep_us, \
+				      timeout_ms, 0) \
+
+/**
+ * regmap_update_bits() - Perform a read/modify/write using a mask
+ *
+ * @map:	The map returned by regmap_init_mem*()
+ * @offset:	Offset of the memory
+ * @mask:	Mask to apply to the read value
+ * @val:	Value to apply to the value to write
+ * Return: 0 if OK, -ve on error
+ */
+int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val);
+
+/**
+ * regmap_init_mem() - Set up a new register map that uses memory access
+ *
+ * @node:	Device node that uses this map
+ * @mapp:	Returns allocated map
+ * Return: 0 if OK, -ve on error
+ *
+ * Use regmap_uninit() to free it.
+ */
+int regmap_init_mem(ofnode node, struct regmap **mapp);
+
+/**
+ * regmap_init_mem_platdata() - Set up a new memory register map for
+ *				of-platdata
+ *
+ * @dev:	Device that uses this map
+ * @reg:	List of address, size pairs
+ * @count:	Number of pairs (e.g. 1 if the regmap has a single entry)
+ * @mapp:	Returns allocated map
+ * Return: 0 if OK, -ve on error
+ *
+ * This creates a new regmap with a list of regions passed in, rather than
+ * using the device tree. It only supports 32-bit machines.
+ *
+ * Use regmap_uninit() to free it.
+ *
+ */
+int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count,
+			     struct regmap **mapp);
+
+int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index);
+
+/**
+ * regmap_get_range() - Obtain the base memory address of a regmap range
+ *
+ * @map:	Regmap to query
+ * @range_num:	Range to look up
+ * Return: Pointer to the range in question if OK, NULL on error
+ */
+void *regmap_get_range(struct regmap *map, unsigned int range_num);
+
+/**
+ * regmap_uninit() - free a previously inited regmap
+ *
+ * @map:	Regmap to free
+ * Return: 0 if OK, -ve on error
+ */
+int regmap_uninit(struct regmap *map);
+
+#endif
diff --git a/include/reiserfs.h b/include/reiserfs.h
new file mode 100644
index 0000000..de41500
--- /dev/null
+++ b/include/reiserfs.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright 2000-2002 by Hans Reiser, licensing governed by reiserfs/README
+ *
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 2000, 2001  Free Software Foundation, Inc.
+ *
+ *  (C) Copyright 2003 Sysgo Real-Time Solutions, AG <www.elinos.com>
+ *  Pavel Bartusek <pba@sysgo.de>
+ */
+
+/* An implementation for the ReiserFS filesystem ported from GRUB.
+ * Some parts of this code (mainly the structures and defines) are
+ * from the original reiser fs code, as found in the linux kernel.
+ */
+
+
+#define SECTOR_SIZE		0x200
+#define SECTOR_BITS		9
+
+/* Error codes */
+typedef enum
+{
+  ERR_NONE = 0,
+  ERR_BAD_FILENAME,
+  ERR_BAD_FILETYPE,
+  ERR_BAD_GZIP_DATA,
+  ERR_BAD_GZIP_HEADER,
+  ERR_BAD_PART_TABLE,
+  ERR_BAD_VERSION,
+  ERR_BELOW_1MB,
+  ERR_BOOT_COMMAND,
+  ERR_BOOT_FAILURE,
+  ERR_BOOT_FEATURES,
+  ERR_DEV_FORMAT,
+  ERR_DEV_VALUES,
+  ERR_EXEC_FORMAT,
+  ERR_FILELENGTH,
+  ERR_FILE_NOT_FOUND,
+  ERR_FSYS_CORRUPT,
+  ERR_FSYS_MOUNT,
+  ERR_GEOM,
+  ERR_NEED_LX_KERNEL,
+  ERR_NEED_MB_KERNEL,
+  ERR_NO_DISK,
+  ERR_NO_PART,
+  ERR_NUMBER_PARSING,
+  ERR_OUTSIDE_PART,
+  ERR_READ,
+  ERR_SYMLINK_LOOP,
+  ERR_UNRECOGNIZED,
+  ERR_WONT_FIT,
+  ERR_WRITE,
+  ERR_BAD_ARGUMENT,
+  ERR_UNALIGNED,
+  ERR_PRIVILEGED,
+  ERR_DEV_NEED_INIT,
+  ERR_NO_DISK_SPACE,
+  ERR_NUMBER_OVERFLOW,
+
+  MAX_ERR_NUM
+} reiserfs_error_t;
+
+
+void reiserfs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
+extern int reiserfs_ls (char *dirname);
+extern int reiserfs_open (char *filename);
+extern int reiserfs_read (char *buf, unsigned len);
+extern int reiserfs_mount (unsigned part_length);
diff --git a/include/relocate.h b/include/relocate.h
new file mode 100644
index 0000000..9ceeecd
--- /dev/null
+++ b/include/relocate.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ */
+
+#ifndef _RELOCATE_H_
+#define _RELOCATE_H_
+
+#include <common.h>
+
+/**
+ * copy_uboot_to_ram() - Copy U-Boot to its new relocated position
+ *
+ * @return 0 if OK, -ve on error
+ */
+int copy_uboot_to_ram(void);
+
+/**
+ * clear_bss() - Clear the BSS (Blocked Start by Symbol) segment
+ *
+ * This clears the memory used by global variables
+ *
+ * @return 0 if OK, -ve on error
+ */
+int clear_bss(void);
+
+/**
+ * do_elf_reloc_fixups() - Fix up ELF relocations in the relocated code
+ *
+ * This processes the relocation tables to ensure that the code can run in its
+ * new location.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int do_elf_reloc_fixups(void);
+
+#endif	/* _RELOCATE_H_ */
diff --git a/include/remoteproc.h b/include/remoteproc.h
new file mode 100644
index 0000000..046cd9e
--- /dev/null
+++ b/include/remoteproc.h
@@ -0,0 +1,309 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#ifndef _RPROC_H_
+#define _RPROC_H_
+
+/*
+ * Note: The platform data support is not meant for use with newer
+ * platforms. This is meant only for legacy devices. This mode of
+ * initialization *will* be eventually removed once all necessary
+ * platforms have moved to dm/fdt.
+ */
+#include <dm/platdata.h>	/* For platform data support - non dt world */
+
+/**
+ * enum rproc_mem_type - What type of memory model does the rproc use
+ * @RPROC_INTERNAL_MEMORY_MAPPED: Remote processor uses own memory and is memory
+ *	mapped to the host processor over an address range.
+ *
+ * Please note that this is an enumeration of memory model of different types
+ * of remote processors. Few of the remote processors do have own internal
+ * memories, while others use external memory for instruction and data.
+ */
+enum rproc_mem_type {
+	RPROC_INTERNAL_MEMORY_MAPPED	= 0,
+};
+
+/**
+ * struct dm_rproc_uclass_pdata - platform data for a CPU
+ * @name: Platform-specific way of naming the Remote proc
+ * @mem_type: one of 'enum rproc_mem_type'
+ * @driver_plat_data: driver specific platform data that may be needed.
+ *
+ * This can be accessed with dev_get_uclass_platdata() for any UCLASS_REMOTEPROC
+ * device.
+ *
+ */
+struct dm_rproc_uclass_pdata {
+	const char *name;
+	enum rproc_mem_type mem_type;
+	void *driver_plat_data;
+};
+
+/**
+ * struct dm_rproc_ops - Driver model remote proc operations.
+ *
+ * This defines the operations provided by remote proc driver.
+ */
+struct dm_rproc_ops {
+	/**
+	 * init() - Initialize the remoteproc device (optional)
+	 *
+	 * This is called after the probe is completed allowing the remote
+	 * processor drivers to split up the initializations between probe and
+	 * init if needed.
+	 *
+	 * @dev:	Remote proc device
+	 * @return 0 if all ok, else appropriate error value.
+	 */
+	int (*init)(struct udevice *dev);
+
+	/**
+	 * load() - Load the remoteproc device using data provided (mandatory)
+	 *
+	 * Load the remoteproc device with an image, do not start the device.
+	 *
+	 * @dev:	Remote proc device
+	 * @addr:	Address of the image to be loaded
+	 * @size:	Size of the image to be loaded
+	 * @return 0 if all ok, else appropriate error value.
+	 */
+	int (*load)(struct udevice *dev, ulong addr, ulong size);
+
+	/**
+	 * start() - Start the remoteproc device (mandatory)
+	 *
+	 * @dev:	Remote proc device
+	 * @return 0 if all ok, else appropriate error value.
+	 */
+	int (*start)(struct udevice *dev);
+
+	/**
+	 * stop() - Stop the remoteproc device (optional)
+	 *
+	 * @dev:	Remote proc device
+	 * @return 0 if all ok, else appropriate error value.
+	 */
+	int (*stop)(struct udevice *dev);
+
+	/**
+	 * reset() - Reset the remoteproc device (optional)
+	 *
+	 * @dev:	Remote proc device
+	 * @return 0 if all ok, else appropriate error value.
+	 */
+	int (*reset)(struct udevice *dev);
+
+	/**
+	 * is_running() - Check if the remote processor is running (optional)
+	 *
+	 * @dev:	Remote proc device
+	 * @return 0 if running, 1 if not running, -ve on error.
+	 */
+	int (*is_running)(struct udevice *dev);
+
+	/**
+	 * ping() - Ping the remote device for basic communication (optional)
+	 *
+	 * @dev:	Remote proc device
+	 * @return 0 on success, 1 if not responding, -ve on other errors.
+	 */
+	int (*ping)(struct udevice *dev);
+
+	/**
+	 * device_to_virt() - Return translated virtual address (optional)
+	 *
+	 * Translate a device address (remote processor view) to virtual
+	 * address (main processor view).
+	 *
+	 * @dev:	Remote proc device
+	 * @da:		Device address
+	 * @size:	Size of the memory region @da is pointing to
+	 * @return virtual address.
+	 */
+	void * (*device_to_virt)(struct udevice *dev, ulong da, ulong size);
+};
+
+/* Accessor */
+#define rproc_get_ops(dev) ((struct dm_rproc_ops *)(dev)->driver->ops)
+
+#if CONFIG_IS_ENABLED(REMOTEPROC)
+/**
+ * rproc_init() - Initialize all bound remote proc devices
+ * @return 0 if all ok, else appropriate error value.
+ */
+int rproc_init(void);
+
+/**
+ * rproc_dev_init() - Initialize a remote proc device based on id
+ * @id:		id of the remote processor
+ * @return 0 if all ok, else appropriate error value.
+ */
+int rproc_dev_init(int id);
+
+/**
+ * rproc_is_initialized() - check to see if remoteproc devices are initialized
+ * @return true if all devices are initialized, false otherwise.
+ */
+bool rproc_is_initialized(void);
+
+/**
+ * rproc_load() - load binary or elf to a remote processor
+ * @id:		id of the remote processor
+ * @addr:	address in memory where the image is located
+ * @size:	size of the image
+ * @return 0 if all ok, else appropriate error value.
+ */
+int rproc_load(int id, ulong addr, ulong size);
+
+/**
+ * rproc_start() - Start a remote processor
+ * @id:		id of the remote processor
+ * @return 0 if all ok, else appropriate error value.
+ */
+int rproc_start(int id);
+
+/**
+ * rproc_stop() - Stop a remote processor
+ * @id:		id of the remote processor
+ * @return 0 if all ok, else appropriate error value.
+ */
+int rproc_stop(int id);
+
+/**
+ * rproc_reset() - reset a remote processor
+ * @id:		id of the remote processor
+ * @return 0 if all ok, else appropriate error value.
+ */
+int rproc_reset(int id);
+
+/**
+ * rproc_ping() - ping a remote processor to check if it can communicate
+ * @id:		id of the remote processor
+ * @return 0 if all ok, else appropriate error value.
+ *
+ * NOTE: this might need communication path available, which is not implemented
+ * as part of remoteproc framework - hook on to appropriate bus architecture to
+ * do the same
+ */
+int rproc_ping(int id);
+
+/**
+ * rproc_is_running() - check to see if remote processor is running
+ * @id:		id of the remote processor
+ * @return 0 if running, 1 if not running, -ve on error.
+ *
+ * NOTE: this may not involve actual communication capability of the remote
+ * processor, but just ensures that it is out of reset and executing code.
+ */
+int rproc_is_running(int id);
+
+/**
+ * rproc_elf32_sanity_check() - Verify if an image is a valid ELF32 one
+ *
+ * Check if a valid ELF32 image exists at the given memory location. Verify
+ * basic ELF32 format requirements like magic number and sections size.
+ *
+ * @addr:	address of the image to verify
+ * @size:	size of the image
+ * @return 0 if the image looks good, else appropriate error value.
+ */
+int rproc_elf32_sanity_check(ulong addr, ulong size);
+
+/**
+ * rproc_elf64_sanity_check() - Verify if an image is a valid ELF32 one
+ *
+ * Check if a valid ELF64 image exists at the given memory location. Verify
+ * basic ELF64 format requirements like magic number and sections size.
+ *
+ * @addr:	address of the image to verify
+ * @size:	size of the image
+ * @return 0 if the image looks good, else appropriate error value.
+ */
+int rproc_elf64_sanity_check(ulong addr, ulong size);
+
+/**
+ * rproc_elf_sanity_check() - Verify if an image is a valid ELF one
+ *
+ * Check if a valid ELF image exists at the given memory location. Auto
+ * detects ELF32/ELF64 and verifies basic ELF64/ELF32 format requirements
+ * like magic number and sections size.
+ *
+ * @addr:	address of the image to verify
+ * @size:	size of the image
+ * @return 0 if the image looks good, else appropriate error value.
+ */
+int rproc_elf_sanity_check(ulong addr, ulong size);
+
+/**
+ * rproc_elf32_load_image() - load an ELF32 image
+ * @dev:	device loading the ELF32 image
+ * @addr:	valid ELF32 image address
+ * @size:	size of the image
+ * @return 0 if the image is successfully loaded, else appropriate error value.
+ */
+int rproc_elf32_load_image(struct udevice *dev, unsigned long addr, ulong size);
+
+/**
+ * rproc_elf64_load_image() - load an ELF64 image
+ * @dev:	device loading the ELF64 image
+ * @addr:	valid ELF64 image address
+ * @size:	size of the image
+ * @return 0 if the image is successfully loaded, else appropriate error value.
+ */
+int rproc_elf64_load_image(struct udevice *dev, ulong addr, ulong size);
+
+/**
+ * rproc_elf_load_image() - load an ELF image
+ * @dev:	device loading the ELF image
+ * @addr:	valid ELF image address
+ * @size:	size of the image
+ *
+ * Auto detects if the image is ELF32 or ELF64 image and load accordingly.
+ * @return 0 if the image is successfully loaded, else appropriate error value.
+ */
+int rproc_elf_load_image(struct udevice *dev, unsigned long addr, ulong size);
+
+/**
+ * rproc_elf_get_boot_addr() - Get rproc's boot address.
+ * @dev:	device loading the ELF image
+ * @addr:	valid ELF image address
+ *
+ * This function returns the entry point address of the ELF
+ * image.
+ */
+ulong rproc_elf_get_boot_addr(struct udevice *dev, ulong addr);
+#else
+static inline int rproc_init(void) { return -ENOSYS; }
+static inline int rproc_dev_init(int id) { return -ENOSYS; }
+static inline bool rproc_is_initialized(void) { return false; }
+static inline int rproc_load(int id, ulong addr, ulong size) { return -ENOSYS; }
+static inline int rproc_start(int id) { return -ENOSYS; }
+static inline int rproc_stop(int id) { return -ENOSYS; }
+static inline int rproc_reset(int id) { return -ENOSYS; }
+static inline int rproc_ping(int id) { return -ENOSYS; }
+static inline int rproc_is_running(int id) { return -ENOSYS; }
+static inline int rproc_elf32_sanity_check(ulong addr,
+					   ulong size) { return -ENOSYS; }
+static inline int rproc_elf64_sanity_check(ulong addr,
+					   ulong size) { return -ENOSYS; }
+static inline int rproc_elf_sanity_check(ulong addr,
+					 ulong size) { return -ENOSYS; }
+static inline int rproc_elf32_load_image(struct udevice *dev,
+					 unsigned long addr, ulong size)
+{ return -ENOSYS; }
+static inline int rproc_elf64_load_image(struct udevice *dev, ulong addr,
+					 ulong size)
+{ return -ENOSYS; }
+static inline int rproc_elf_load_image(struct udevice *dev, ulong addr,
+				       ulong size)
+{ return -ENOSYS; }
+static inline ulong rproc_elf_get_boot_addr(struct udevice *dev, ulong addr)
+{ return 0; }
+#endif
+
+#endif	/* _RPROC_H_ */
diff --git a/include/reset-uclass.h b/include/reset-uclass.h
new file mode 100644
index 0000000..7b5cc3c
--- /dev/null
+++ b/include/reset-uclass.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _RESET_UCLASS_H
+#define _RESET_UCLASS_H
+
+/* See reset.h for background documentation. */
+
+#include <reset.h>
+
+struct ofnode_phandle_args;
+struct udevice;
+
+/**
+ * struct reset_ops - The functions that a reset controller driver must
+ * implement.
+ */
+struct reset_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) reset specifier.
+	 *
+	 * The reset core calls this function as the first step in implementing
+	 * a client's reset_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the reset core will use a
+	 * default implementation, which assumes #reset-cells = <1>, and that
+	 * the DT cell contains a simple integer reset signal ID.
+	 *
+	 * At present, the reset API solely supports device-tree. If this
+	 * changes, other xxx_xlate() functions may be added to support those
+	 * other mechanisms.
+	 *
+	 * @reset_ctl:	The reset control struct to hold the translation result.
+	 * @args:	The reset specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct reset_ctl *reset_ctl,
+			struct ofnode_phandle_args *args);
+	/**
+	 * request - Request a translated reset control.
+	 *
+	 * The reset core calls this function as the second step in
+	 * implementing a client's reset_get_by_*() call, following a
+	 * successful xxx_xlate() call.
+	 *
+	 * @reset_ctl:	The reset control struct to request; this has been
+	 *		filled in by a previoux xxx_xlate() function call.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct reset_ctl *reset_ctl);
+	/**
+	 * free - Free a previously requested reset control.
+	 *
+	 * This is the implementation of the client reset_free() API.
+	 *
+	 * @reset_ctl:	The reset control to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct reset_ctl *reset_ctl);
+	/**
+	 * rst_assert - Assert a reset signal.
+	 *
+	 * Note: This function is named rst_assert not assert to avoid
+	 * conflicting with global macro assert().
+	 *
+	 * @reset_ctl:	The reset signal to assert.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*rst_assert)(struct reset_ctl *reset_ctl);
+	/**
+	 * rst_deassert - Deassert a reset signal.
+	 *
+	 * @reset_ctl:	The reset signal to deassert.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*rst_deassert)(struct reset_ctl *reset_ctl);
+	/**
+	 * rst_status - Check reset signal status.
+	 *
+	 * @reset_ctl:	The reset signal to check.
+	 * @return 0 if deasserted, positive if asserted, or a negative
+	 *           error code.
+	 */
+	int (*rst_status)(struct reset_ctl *reset_ctl);
+};
+
+#endif
diff --git a/include/reset.h b/include/reset.h
new file mode 100644
index 0000000..4fac4e6
--- /dev/null
+++ b/include/reset.h
@@ -0,0 +1,339 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ */
+
+#ifndef _RESET_H
+#define _RESET_H
+
+#include <dm/ofnode.h>
+#include <linux/errno.h>
+
+/**
+ * A reset is a hardware signal indicating that a HW module (or IP block, or
+ * sometimes an entire off-CPU chip) reset all of its internal state to some
+ * known-good initial state. Drivers will often reset HW modules when they
+ * begin execution to ensure that hardware correctly responds to all requests,
+ * or in response to some error condition. Reset signals are often controlled
+ * externally to the HW module being reset, by an entity this API calls a reset
+ * controller. This API provides a standard means for drivers to request that
+ * reset controllers set or clear reset signals.
+ *
+ * A driver that implements UCLASS_RESET is a reset controller or provider. A
+ * controller will often implement multiple separate reset signals, since the
+ * hardware it manages often has this capability. reset-uclass.h describes the
+ * interface which reset controllers must implement.
+ *
+ * Reset consumers/clients are the HW modules affected by reset signals. This
+ * header file describes the API used by drivers for those HW modules.
+ */
+
+struct udevice;
+
+/**
+ * struct reset_ctl - A handle to (allowing control of) a single reset signal.
+ *
+ * Clients provide storage for reset control handles. The content of the
+ * structure is managed solely by the reset API and reset drivers. A reset
+ * control struct is initialized by "get"ing the reset control struct. The
+ * reset control struct is passed to all other reset APIs to identify which
+ * reset signal to operate upon.
+ *
+ * @dev: The device which implements the reset signal.
+ * @id: The reset signal ID within the provider.
+ * @data: An optional data field for scenarios where a single integer ID is not
+ *	  sufficient. If used, it can be populated through an .of_xlate op and
+ *	  processed during the various reset ops.
+ * @polarity: An optional polarity field for drivers that support
+ *	  different reset polarities.
+ *
+ * Should additional information to identify and configure any reset signal
+ * for any provider be required in the future, the struct could be expanded to
+ * either (a) add more fields to allow reset providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct reset_ctl {
+	struct udevice *dev;
+	/*
+	 * Written by of_xlate. In the future, we might add more fields here.
+	 */
+	unsigned long id;
+	unsigned long data;
+	unsigned long polarity;
+};
+
+/**
+ * struct reset_ctl_bulk - A handle to (allowing control of) a bulk of reset
+ * signals.
+ *
+ * Clients provide storage for the reset control bulk. The content of the
+ * structure is managed solely by the reset API. A reset control bulk struct is
+ * initialized by "get"ing the reset control bulk struct.
+ * The reset control bulk struct is passed to all other bulk reset APIs to apply
+ * the API to all the reset signals in the bulk struct.
+ *
+ * @resets: An array of reset signal handles handles.
+ * @count: The number of reset signal handles in the reset array.
+ */
+struct reset_ctl_bulk {
+	struct reset_ctl *resets;
+	unsigned int count;
+};
+
+#if CONFIG_IS_ENABLED(DM_RESET)
+/**
+ * reset_get_by_index - Get/request a reset signal by integer index.
+ *
+ * This looks up and requests a reset signal. The index is relative to the
+ * client device; each device is assumed to have n reset signals associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device reset signal indices to provider reset signals may
+ * be via device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the reset signal to request, within the client's
+ *		list of reset signals.
+ * @reset_ctl	A pointer to a reset control struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_by_index(struct udevice *dev, int index,
+		       struct reset_ctl *reset_ctl);
+
+/**
+ * reset_get_by_index_nodev - Get/request a reset signal by integer index
+ * without a device.
+ *
+ * This is a version of reset_get_by_index() that does not use a device.
+ *
+ * @node:	The client ofnode.
+ * @index:	The index of the reset signal to request, within the client's
+ *		list of reset signals.
+ * @reset_ctl	A pointer to a reset control struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_by_index_nodev(ofnode node, int index,
+			     struct reset_ctl *reset_ctl);
+
+/**
+ * reset_get_bulk - Get/request all reset signals of a device.
+ *
+ * This looks up and requests all reset signals of the client device; each
+ * device is assumed to have n reset signals associated with it somehow,
+ * and this function finds and requests all of them in a separate structure.
+ * The mapping of client device reset signals indices to provider reset signals
+ * may be via device-tree properties, board-provided mapping tables, or some
+ * other mechanism.
+ *
+ * @dev:	The client device.
+ * @bulk	A pointer to a reset control bulk struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk);
+
+/**
+ * reset_get_by_name - Get/request a reset signal by name.
+ *
+ * This looks up and requests a reset signal. The name is relative to the
+ * client device; each device is assumed to have n reset signals associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device reset signal names to provider reset signal may be
+ * via device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the reset signal to request, within the client's
+ *		list of reset signals.
+ * @reset_ctl:	A pointer to a reset control struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_by_name(struct udevice *dev, const char *name,
+		      struct reset_ctl *reset_ctl);
+
+/**
+ * reset_request - Request a reset signal.
+ *
+ * @reset_ctl:	A reset control struct.
+ *
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_request(struct reset_ctl *reset_ctl);
+
+/**
+ * reset_free - Free a previously requested reset signal.
+ *
+ * @reset_ctl:	A reset control struct that was previously successfully
+ *		requested by reset_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_free(struct reset_ctl *reset_ctl);
+
+/**
+ * reset_assert - Assert a reset signal.
+ *
+ * This function will assert the specified reset signal, thus resetting the
+ * affected HW module(s). Depending on the reset controller hardware, the reset
+ * signal will either stay asserted until reset_deassert() is called, or the
+ * hardware may autonomously clear the reset signal itself.
+ *
+ * @reset_ctl:	A reset control struct that was previously successfully
+ *		requested by reset_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_assert(struct reset_ctl *reset_ctl);
+
+/**
+ * reset_assert_bulk - Assert all reset signals in a reset control bulk struct.
+ *
+ * This function will assert the specified reset signals in a reset control
+ * bulk struct, thus resetting the affected HW module(s). Depending on the
+ * reset controller hardware, the reset signals will either stay asserted
+ * until reset_deassert_bulk() is called, or the hardware may autonomously
+ * clear the reset signals itself.
+ *
+ * @bulk:	A reset control bulk struct that was previously successfully
+ *		requested by reset_get_bulk().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_assert_bulk(struct reset_ctl_bulk *bulk);
+
+/**
+ * reset_deassert - Deassert a reset signal.
+ *
+ * This function will deassert the specified reset signal, thus releasing the
+ * affected HW modules() from reset, and allowing them to continue normal
+ * operation.
+ *
+ * @reset_ctl:	A reset control struct that was previously successfully
+ *		requested by reset_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_deassert(struct reset_ctl *reset_ctl);
+
+/**
+ * reset_deassert_bulk - Deassert all reset signals in a reset control bulk
+ * struct.
+ *
+ * This function will deassert the specified reset signals in a reset control
+ * bulk struct, thus releasing the affected HW modules() from reset, and
+ * allowing them to continue normal operation.
+ *
+ * @bulk:	A reset control bulk struct that was previously successfully
+ *		requested by reset_get_bulk().
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_deassert_bulk(struct reset_ctl_bulk *bulk);
+
+/**
+ * rst_status - Check reset signal status.
+ *
+ * @reset_ctl:	The reset signal to check.
+ * @return 0 if deasserted, positive if asserted, or a negative
+ *           error code.
+ */
+int reset_status(struct reset_ctl *reset_ctl);
+
+/**
+ * reset_release_all - Assert/Free an array of previously requested resets.
+ *
+ * For each reset contained in the reset array, this function will check if
+ * reset has been previously requested and then will assert and free it.
+ *
+ * @reset_ctl:	A reset struct array that was previously successfully
+ *		requested by reset_get_by_*().
+ * @count	Number of reset contained in the array
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_release_all(struct reset_ctl *reset_ctl, int count);
+
+/**
+ * reset_release_bulk - Assert/Free an array of previously requested reset
+ * signals in a reset control bulk struct.
+ *
+ * For each reset contained in the reset control bulk struct, this function
+ * will check if reset has been previously requested and then will assert
+ * and free it.
+ *
+ * @bulk:	A reset control bulk struct that was previously successfully
+ *		requested by reset_get_bulk().
+ * @return 0 if OK, or a negative error code.
+ */
+static inline int reset_release_bulk(struct reset_ctl_bulk *bulk)
+{
+	return reset_release_all(bulk->resets, bulk->count);
+}
+#else
+static inline int reset_get_by_index(struct udevice *dev, int index,
+				     struct reset_ctl *reset_ctl)
+{
+	return -ENOTSUPP;
+}
+
+static inline int reset_get_bulk(struct udevice *dev,
+				 struct reset_ctl_bulk *bulk)
+{
+	return -ENOTSUPP;
+}
+
+static inline int reset_get_by_name(struct udevice *dev, const char *name,
+				    struct reset_ctl *reset_ctl)
+{
+	return -ENOTSUPP;
+}
+
+static inline int reset_free(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static inline int reset_assert(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static inline int reset_assert_bulk(struct reset_ctl_bulk *bulk)
+{
+	return 0;
+}
+
+static inline int reset_deassert(struct reset_ctl *reset_ctl)
+{
+	return 0;
+}
+
+static inline int reset_deassert_bulk(struct reset_ctl_bulk *bulk)
+{
+	return 0;
+}
+
+static inline int reset_status(struct reset_ctl *reset_ctl)
+{
+	return -ENOTSUPP;
+}
+
+static inline int reset_release_all(struct reset_ctl *reset_ctl, int count)
+{
+	return 0;
+}
+
+static inline int reset_release_bulk(struct reset_ctl_bulk *bulk)
+{
+	return 0;
+}
+#endif
+
+/**
+ * reset_valid() - check if reset is valid
+ *
+ * @reset_ctl:		the reset to check
+ * @return TRUE if valid, or FALSE
+ */
+static inline bool reset_valid(struct reset_ctl *reset_ctl)
+{
+	return !!reset_ctl->dev;
+}
+
+#endif
diff --git a/include/rtc.h b/include/rtc.h
new file mode 100644
index 0000000..7386d52
--- /dev/null
+++ b/include/rtc.h
@@ -0,0 +1,275 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * Generic RTC interface.
+ */
+#ifndef _RTC_H_
+#define _RTC_H_
+
+/* bcd<->bin functions are needed by almost all the RTC drivers, let's include
+ * it there instead of in evey single driver */
+
+#include <bcd.h>
+#include <rtc_def.h>
+
+#ifdef CONFIG_DM_RTC
+
+struct rtc_ops {
+	/**
+	 * get() - get the current time
+	 *
+	 * Returns the current time read from the RTC device. The driver
+	 * is responsible for setting up every field in the structure.
+	 *
+	 * @dev:	Device to read from
+	 * @time:	Place to put the time that is read
+	 */
+	int (*get)(struct udevice *dev, struct rtc_time *time);
+
+	/**
+	 * set() - set the current time
+	 *
+	 * Sets the time in the RTC device. The driver can expect every
+	 * field to be set correctly.
+	 *
+	 * @dev:	Device to read from
+	 * @time:	Time to write
+	 */
+	int (*set)(struct udevice *dev, const struct rtc_time *time);
+
+	/**
+	 * reset() - reset the RTC to a known-good state
+	 *
+	 * This function resets the RTC to a known-good state. The time may
+	 * be unset by this method, so should be set after this method is
+	 * called.
+	 *
+	 * @dev:	Device to read from
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*reset)(struct udevice *dev);
+
+	/**
+	 * read8() - Read an 8-bit register
+	 *
+	 * @dev:	Device to read from
+	 * @reg:	Register to read
+	 * @return value read, or -ve on error
+	 */
+	int (*read8)(struct udevice *dev, unsigned int reg);
+
+	/**
+	* write8() - Write an 8-bit register
+	*
+	* @dev:		Device to write to
+	* @reg:		Register to write
+	* @value:	Value to write
+	* @return 0 if OK, -ve on error
+	*/
+	int (*write8)(struct udevice *dev, unsigned int reg, int val);
+};
+
+/* Access the operations for an RTC device */
+#define rtc_get_ops(dev)	((struct rtc_ops *)(dev)->driver->ops)
+
+/**
+ * dm_rtc_get() - Read the time from an RTC
+ *
+ * @dev:	Device to read from
+ * @time:	Place to put the current time
+ * @return 0 if OK, -ve on error
+ */
+int dm_rtc_get(struct udevice *dev, struct rtc_time *time);
+
+/**
+ * dm_rtc_set() - Write a time to an RTC
+ *
+ * @dev:	Device to read from
+ * @time:	Time to write into the RTC
+ * @return 0 if OK, -ve on error
+ */
+int dm_rtc_set(struct udevice *dev, struct rtc_time *time);
+
+/**
+ * dm_rtc_reset() - reset the RTC to a known-good state
+ *
+ * If the RTC appears to be broken (e.g. it is not counting up in seconds)
+ * it may need to be reset to a known good state. This function achieves this.
+ * After resetting the RTC the time should then be set to a known value by
+ * the caller.
+ *
+ * @dev:	Device to read from
+ * @return 0 if OK, -ve on error
+ */
+int dm_rtc_reset(struct udevice *dev);
+
+/**
+ * rtc_read8() - Read an 8-bit register
+ *
+ * @dev:	Device to read from
+ * @reg:	Register to read
+ * @return value read, or -ve on error
+ */
+int rtc_read8(struct udevice *dev, unsigned int reg);
+
+/**
+ * rtc_write8() - Write an 8-bit register
+ *
+ * @dev:	Device to write to
+ * @reg:	Register to write
+ * @value:	Value to write
+ * @return 0 if OK, -ve on error
+ */
+int rtc_write8(struct udevice *dev, unsigned int reg, int val);
+
+/**
+ * rtc_read16() - Read a 16-bit value from the RTC
+ *
+ * @dev:	Device to read from
+ * @reg:	Offset to start reading from
+ * @valuep:	Place to put the value that is read
+ * @return 0 if OK, -ve on error
+ */
+int rtc_read16(struct udevice *dev, unsigned int reg, u16 *valuep);
+
+/**
+ * rtc_write16() - Write a 16-bit value to the RTC
+ *
+ * @dev:	Device to write to
+ * @reg:	Register to start writing to
+ * @value:	Value to write
+ * @return 0 if OK, -ve on error
+ */
+int rtc_write16(struct udevice *dev, unsigned int reg, u16 value);
+
+/**
+ * rtc_read32() - Read a 32-bit value from the RTC
+ *
+ * @dev:	Device to read from
+ * @reg:	Offset to start reading from
+ * @valuep:	Place to put the value that is read
+ * @return 0 if OK, -ve on error
+ */
+int rtc_read32(struct udevice *dev, unsigned int reg, u32 *valuep);
+
+/**
+ * rtc_write32() - Write a 32-bit value to the RTC
+ *
+ * @dev:	Device to write to
+ * @reg:	Register to start writing to
+ * @value:	Value to write
+ * @return 0 if OK, -ve on error
+ */
+int rtc_write32(struct udevice *dev, unsigned int reg, u32 value);
+
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
+int rtc_enable_32khz_output(int busnum, int chip_addr);
+#endif
+
+#else
+int rtc_get (struct rtc_time *);
+int rtc_set (struct rtc_time *);
+void rtc_reset (void);
+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
+void rtc_enable_32khz_output(void);
+#endif
+
+/**
+ * rtc_read8() - Read an 8-bit register
+ *
+ * @reg:	Register to read
+ * @return value read
+ */
+int rtc_read8(int reg);
+
+/**
+ * rtc_write8() - Write an 8-bit register
+ *
+ * @reg:	Register to write
+ * @value:	Value to write
+ */
+void rtc_write8(int reg, uchar val);
+
+/**
+ * rtc_read32() - Read a 32-bit value from the RTC
+ *
+ * @reg:	Offset to start reading from
+ * @return value read
+ */
+u32 rtc_read32(int reg);
+
+/**
+ * rtc_write32() - Write a 32-bit value to the RTC
+ *
+ * @reg:	Register to start writing to
+ * @value:	Value to write
+ */
+void rtc_write32(int reg, u32 value);
+
+/**
+ * rtc_init() - Set up the real time clock ready for use
+ */
+void rtc_init(void);
+#endif /* CONFIG_DM_RTC */
+
+/**
+ * is_leap_year - Check if year is a leap year
+ *
+ * @year	Year
+ * @return	1 if leap year
+ */
+static inline bool is_leap_year(unsigned int year)
+{
+	return (!(year % 4) && (year % 100)) || !(year % 400);
+}
+
+/**
+ * rtc_calc_weekday() - Work out the weekday from a time
+ *
+ * This only works for the Gregorian calendar - i.e. after 1752 (in the UK).
+ * It sets time->tm_wdaay to the correct day of the week.
+ *
+ * @time:	Time to inspect. tm_wday is updated
+ * @return 0 if OK, -EINVAL if the weekday could not be determined
+ */
+int rtc_calc_weekday(struct rtc_time *time);
+
+/**
+ * rtc_to_tm() - Convert a time_t value into a broken-out time
+ *
+ * The following fields are set up by this function:
+ *	tm_sec, tm_min, tm_hour, tm_mday, tm_mon, tm_year, tm_wday
+ *
+ * Note that tm_yday and tm_isdst are set to 0.
+ *
+ * @time_t:	Number of seconds since 1970-01-01 00:00:00
+ * @time:	Place to put the broken-out time
+ */
+void rtc_to_tm(u64 time_t, struct rtc_time *time);
+
+/**
+ * rtc_mktime() - Convert a broken-out time into a time_t value
+ *
+ * The following fields need to be valid for this function to work:
+ *	tm_sec, tm_min, tm_hour, tm_mday, tm_mon, tm_year
+ *
+ * Note that tm_wday and tm_yday are ignored.
+ *
+ * @time:	Broken-out time to convert
+ * @return corresponding time_t value, seconds since 1970-01-01 00:00:00
+ */
+unsigned long rtc_mktime(const struct rtc_time *time);
+
+/**
+ * rtc_month_days() - The number of days in the month
+ *
+ * @month:	month (January = 0)
+ * @year:	year (4 digits)
+ */
+int rtc_month_days(unsigned int month, unsigned int year);
+
+#endif	/* _RTC_H_ */
diff --git a/include/rtc_def.h b/include/rtc_def.h
new file mode 100644
index 0000000..6cb490c
--- /dev/null
+++ b/include/rtc_def.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __rtc_def_h
+#define __rtc_def_h
+
+/*
+ * The struct used to pass data from the generic interface code to
+ * the hardware dependend low-level code ande vice versa. Identical
+ * to struct rtc_time used by the Linux kernel.
+ *
+ * Note that there are small but significant differences to the
+ * common "struct time":
+ *
+ *		struct time:		struct rtc_time:
+ * tm_mon	0 ... 11		1 ... 12
+ * tm_year	years since 1900	years since 0
+ */
+
+struct rtc_time {
+	int tm_sec;
+	int tm_min;
+	int tm_hour;
+	int tm_mday;
+	int tm_mon;
+	int tm_year;
+	int tm_wday;
+	int tm_yday;
+	int tm_isdst;
+};
+
+#endif
diff --git a/include/s_record.h b/include/s_record.h
new file mode 100644
index 0000000..3ece695
--- /dev/null
+++ b/include/s_record.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*--------------------------------------------------------------------------
+ *
+ * Motorola S-Record Format:
+ *
+ * Motorola S-Records are an industry-standard format for
+ * transmitting binary files to target systems and PROM
+ * programmers. LSI Logic have extended this standard to include
+ * an S4-record containing an address and a symbol.
+ *
+ * The extended S-record standard is as follows:
+ *
+ * S<type><length><address><data....><checksum>
+ * S4<length><address><name>,<checksum>
+ *
+ * Where:
+ *
+ * type
+ *     is the record type. Where:
+ *
+ *     0  starting record (optional)
+ *     1  data record with 16-bit address
+ *     2  data record with 24-bit address
+ *     3  data record with 32-bit address
+ *     4  symbol record (LSI extension)
+ *     5  number of data records in preceding block
+ *     6  unused
+ *     7  ending record for S3 records
+ *     8  ending record for S2 records
+ *     9  ending record for S1 records
+ *
+ * length
+ *     is two hex characters. This defines the length of the
+ *     record in bytes (not characters). It includes the address
+ *     field, the data field, and the checksum field.
+ *
+ * address
+ *     is 4, 6, or 8 characters. Corresponding to a 16-, 24-, or
+ *     32-bit address. The address field for S4 records is
+ *     always 32 bits.
+ *
+ * data
+ *
+ *     Are the data bytes. Each pair of hex characters represent
+ *     one byte in memory.
+ *
+ * name
+ *     Is the symbol name. The symbol is terminated by a ','.
+ *
+ * checksum
+ *     Is the one's complement of the 8-bit checksum.
+ *
+ * Example
+ *
+ * S0030000FC
+ * .
+ * .
+ * S325000004403C0880018D08DD900000000011000026000000003C0880012508DC50C50000B401
+ * S32500000460C50100B8C50200BCC50300C0C50400C4C50500C8C50600CCC50700D0C50800D4FA
+ * S32500000480C50900D8C50A00DCC50B00E0C50C00E4C50D00E8C50E00ECC50F00F0C51000F49A
+ * S325000004A0C51100F8C51200FCC5130100C5140104C5150108C516010CC5170110C518011434
+ * .
+ * .
+ * S70500000000FA
+ *
+ * The S0 record starts the file. The S3 records contain the
+ * data. The S7 record contains the entry address and terminates
+ * the download.
+ *
+ *--------------------------------------------------------------------------
+ */
+
+#define SREC_START	0	/* Start Record (module name)		    */
+#define SREC_DATA2	1	/* Data  Record with 2 byte address	    */
+#define SREC_DATA3	2	/* Data  Record with 3 byte address	    */
+#define SREC_DATA4	3	/* Data  Record with 4 byte address	    */
+#define SREC_COUNT	5	/* Count Record (previously transmitted)    */
+#define SREC_END4	7	/* End   Record with 4 byte start address   */
+#define SREC_END3	8	/* End   Record with 3 byte start address   */
+#define SREC_END2	9	/* End   Record with 2 byte start address   */
+#define SREC_EMPTY	10	/* Empty Record without any data	    */
+
+#define SREC_REC_OK  SREC_EMPTY /* last code without error condition	    */
+
+#define SREC_E_BADTYPE	-1	/* no valid S-Record		            */
+#define SREC_E_NOSREC	-2	/* line format differs from s-record	    */
+#define SREC_E_BADCHKS	-3	/* checksum error in an s-record line	    */
+
+#define SREC_MAXRECLEN	(512 + 4)   /* max ASCII record length		    */
+#define SREC_MAXBINLEN	255	    /* resulting binary length		    */
+
+int srec_decode (char *input, int *count, ulong *addr, char *data);
diff --git a/include/samsung-usb-phy-uboot.h b/include/samsung-usb-phy-uboot.h
new file mode 100644
index 0000000..f2bce57
--- /dev/null
+++ b/include/samsung-usb-phy-uboot.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* include/samsung-usb-phy-uboot.h
+ *
+ * Copyright (c) 2015 Samsung Electronics
+ *
+ * USB3 (DWC3) PHY uboot init
+ */
+
+#ifndef __SAMSUNG_USB_PHY_UBOOT_H_
+#define __SAMSUNG_USB_PHY_UBOOT_H_
+
+#include <asm/arch/xhci-exynos.h>
+
+void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy);
+#endif /* __SAMSUNG_USB_PHY_UBOOT_H_ */
diff --git a/include/samsung/exynos5-dt-types.h b/include/samsung/exynos5-dt-types.h
new file mode 100644
index 0000000..8fe08fe
--- /dev/null
+++ b/include/samsung/exynos5-dt-types.h
@@ -0,0 +1,31 @@
+#ifndef _EXYNOS5_DT_H_
+#define _EXYNOS5_DT_H_
+
+enum {
+	EXYNOS5_BOARD_GENERIC,
+
+	EXYNOS5_BOARD_ODROID_XU3,
+	EXYNOS5_BOARD_ODROID_XU3_REV01,
+	EXYNOS5_BOARD_ODROID_XU3_REV02,
+	EXYNOS5_BOARD_ODROID_XU4_REV01,
+	EXYNOS5_BOARD_ODROID_HC1_REV01,
+	EXYNOS5_BOARD_ODROID_HC2_REV01,
+	EXYNOS5_BOARD_ODROID_UNKNOWN,
+
+	EXYNOS5_BOARD_COUNT,
+};
+
+struct odroid_rev_info {
+	int board_type;
+	int board_rev;
+	int adc_val;
+	const char *name;
+};
+
+bool board_is_generic(void);
+bool board_is_odroidxu3(void);
+bool board_is_odroidxu4(void);
+bool board_is_odroidhc1(void);
+bool board_is_odroidhc2(void);
+
+#endif
diff --git a/include/samsung/misc.h b/include/samsung/misc.h
new file mode 100644
index 0000000..4ff28a1
--- /dev/null
+++ b/include/samsung/misc.h
@@ -0,0 +1,39 @@
+#ifndef __SAMSUNG_MISC_COMMON_H__
+#define __SAMSUNG_MISC_COMMON_H__
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void);
+#endif
+
+#ifdef CONFIG_LCD_MENU
+enum {
+	BOOT_MODE_INFO,
+	BOOT_MODE_THOR,
+	BOOT_MODE_UMS,
+	BOOT_MODE_DFU,
+	BOOT_MODE_GPT,
+	BOOT_MODE_ENV,
+	BOOT_MODE_EXIT,
+};
+
+void keys_init(void);
+void check_boot_mode(void);
+#endif /* CONFIG_LCD_MENU */
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void);
+#endif
+
+#ifdef CONFIG_SET_DFU_ALT_INFO
+char *get_dfu_alt_system(char *interface, char *devstr);
+char *get_dfu_alt_boot(char *interface, char *devstr);
+#endif
+void set_board_type(void);
+void set_board_revision(void);
+const char *get_board_type(void);
+
+#endif /* __SAMSUNG_MISC_COMMON_H__ */
diff --git a/include/sandbox-adc.h b/include/sandbox-adc.h
new file mode 100644
index 0000000..2017b9c
--- /dev/null
+++ b/include/sandbox-adc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ */
+
+#ifndef _SANDBOX_ADC_H_
+#define _SANDBOX_ADC_H_
+
+#define SANDBOX_ADC_DEVNAME		"adc@0"
+#define SANDBOX_ADC_DATA_MASK		0xffff /* 16-bits resolution */
+#define SANDBOX_ADC_CHANNELS		4
+#define SANDBOX_ADC_CHANNEL0_DATA	0x0
+#define SANDBOX_ADC_CHANNEL1_DATA	0x1000
+#define SANDBOX_ADC_CHANNEL2_DATA	0x2000
+#define SANDBOX_ADC_CHANNEL3_DATA	0x3000
+
+enum sandbox_adc_mode {
+	SANDBOX_ADC_MODE_SINGLE_CHANNEL = 0,
+	SANDBOX_ADC_MODE_MULTI_CHANNEL,
+};
+
+enum sandbox_adc_status {
+	SANDBOX_ADC_INACTIVE = 0,
+	SANDBOX_ADC_ACTIVE,
+};
+
+#define SANDBOX_ADC_VSS_VALUE		0
+
+#endif
diff --git a/include/sandbox-clk.h b/include/sandbox-clk.h
new file mode 100644
index 0000000..296cddf
--- /dev/null
+++ b/include/sandbox-clk.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+#ifndef __SANDBOX_CLK_H__
+#define __SANDBOX_CLK_H__
+
+#include <linux/clk-provider.h>
+
+enum {
+	SANDBOX_CLK_PLL2 = 1,
+	SANDBOX_CLK_PLL3,
+	SANDBOX_CLK_PLL3_60M,
+	SANDBOX_CLK_PLL3_80M,
+	SANDBOX_CLK_ECSPI_ROOT,
+	SANDBOX_CLK_ECSPI0,
+	SANDBOX_CLK_ECSPI1,
+	SANDBOX_CLK_USDHC1_SEL,
+	SANDBOX_CLK_USDHC2_SEL,
+	SANDBOX_CLK_I2C,
+	SANDBOX_CLK_I2C_ROOT,
+};
+
+enum sandbox_pllv3_type {
+	SANDBOX_PLLV3_GENERIC,
+	SANDBOX_PLLV3_USB,
+};
+
+struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
+			      const char *parent_name, void __iomem *base,
+			      u32 div_mask);
+
+static inline struct clk *sandbox_clk_fixed_factor(const char *name,
+						   const char *parent,
+						   unsigned int mult,
+						   unsigned int div)
+{
+	return clk_register_fixed_factor(NULL, name, parent,
+			CLK_SET_RATE_PARENT, mult, div);
+}
+
+static inline struct clk *sandbox_clk_divider(const char *name,
+					      const char *parent,
+					      void __iomem *reg, u8 shift,
+					      u8 width)
+{
+	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
+			reg, shift, width, 0);
+}
+
+struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
+				       const char *parent_name,
+				       unsigned long flags,
+				       void __iomem *reg, u8 bit_idx,
+				       u8 cgr_val, u8 clk_gate_flags);
+
+static inline struct clk *sandbox_clk_gate2(const char *name,
+					    const char *parent,
+					    void __iomem *reg, u8 shift)
+{
+	return sandbox_clk_register_gate2(NULL, name, parent,
+					  CLK_SET_RATE_PARENT, reg, shift,
+					  0x3, 0);
+}
+
+static inline struct clk *sandbox_clk_mux(const char *name, void __iomem *reg,
+					  u8 shift, u8 width,
+					  const char * const *parents,
+					  int num_parents)
+{
+	return clk_register_mux(NULL, name, parents, num_parents,
+				CLK_SET_RATE_NO_REPARENT, reg, shift,
+				width, 0);
+}
+
+int sandbox_clk_enable_count(struct clk *clk);
+
+#endif /* __SANDBOX_CLK_H__ */
diff --git a/include/sandboxblockdev.h b/include/sandboxblockdev.h
new file mode 100644
index 0000000..c1f0afb
--- /dev/null
+++ b/include/sandboxblockdev.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013, Henrik Nordstrom <henrik@henriknordstrom.net>
+ */
+
+#ifndef __SANDBOX_BLOCK_DEV__
+#define __SANDBOX_BLOCK_DEV__
+
+struct host_block_dev {
+#ifndef CONFIG_BLK
+	struct blk_desc blk_dev;
+#endif
+	char *filename;
+	int fd;
+};
+
+int host_dev_bind(int dev, char *filename);
+
+#endif
diff --git a/include/sandboxfs.h b/include/sandboxfs.h
new file mode 100644
index 0000000..6e6e3c6
--- /dev/null
+++ b/include/sandboxfs.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2012, Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __SANDBOX_FS__
+#define __SANDBOX_FS__
+
+int sandbox_fs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
+
+int sandbox_fs_read_at(const char *filename, loff_t pos, void *buffer,
+		       loff_t maxsize, loff_t *actread);
+int sandbox_fs_write_at(const char *filename, loff_t pos, void *buffer,
+			loff_t maxsize, loff_t *actwrite);
+
+void sandbox_fs_close(void);
+int sandbox_fs_ls(const char *dirname);
+int sandbox_fs_exists(const char *filename);
+int sandbox_fs_size(const char *filename, loff_t *size);
+int fs_read_sandbox(const char *filename, void *buf, loff_t offset, loff_t len,
+		    loff_t *actread);
+int fs_write_sandbox(const char *filename, void *buf, loff_t offset,
+		     loff_t len, loff_t *actwrite);
+
+#endif
diff --git a/include/sandboxtee.h b/include/sandboxtee.h
new file mode 100644
index 0000000..419643a
--- /dev/null
+++ b/include/sandboxtee.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Linaro Limited
+ */
+
+#ifndef __SANDBOXTEE_H
+#define __SANDBOXTEE_H
+
+#include <search.h>
+#include <tee/optee_ta_avb.h>
+
+/**
+ * struct sandbox_tee_state - internal state of the sandbox TEE
+ * @session:			current open session
+ * @num_shms:			number of registered shared memory objects
+ * @ta:				Trusted Application of current session
+ * @ta_avb_rollback_indexes	TA avb rollback indexes storage
+ * @ta_avb_lock_state		TA avb lock state storage
+ * @pstorage_htab		named persistent values storage
+ */
+struct sandbox_tee_state {
+	u32 session;
+	int num_shms;
+	void *ta;
+	u64 ta_avb_rollback_indexes[TA_AVB_MAX_ROLLBACK_LOCATIONS];
+	u32 ta_avb_lock_state;
+	struct hsearch_data pstorage_htab;
+};
+
+#endif /*__SANDBOXTEE_H*/
diff --git a/include/sata.h b/include/sata.h
new file mode 100644
index 0000000..d89f7a8
--- /dev/null
+++ b/include/sata.h
@@ -0,0 +1,24 @@
+#ifndef __SATA_H__
+#define __SATA_H__
+#include <part.h>
+
+#if !defined(CONFIG_DM_SCSI) && !defined(CONFIG_AHCI)
+int init_sata(int dev);
+int reset_sata(int dev);
+int scan_sata(int dev);
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer);
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
+
+int sata_initialize(void);
+int __sata_initialize(void);
+int sata_stop(void);
+int __sata_stop(void);
+int sata_port_status(int dev, int port);
+
+extern struct blk_desc sata_dev_desc[];
+#endif
+
+int sata_probe(int devnum);
+int sata_remove(int devnum);
+
+#endif
diff --git a/include/scf0403_lcd.h b/include/scf0403_lcd.h
new file mode 100644
index 0000000..07f8c64
--- /dev/null
+++ b/include/scf0403_lcd.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013, Compulab Inc.
+ */
+#ifndef SCF0403_LCD_H_
+#define SCF0403_LCD_H_
+
+int scf0403_init(int reset_gpio);
+
+#endif
diff --git a/include/scsi.h b/include/scsi.h
new file mode 100644
index 0000000..61da958
--- /dev/null
+++ b/include/scsi.h
@@ -0,0 +1,249 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ */
+ #ifndef _SCSI_H
+ #define _SCSI_H
+
+#include <linux/dma-direction.h>
+
+struct scsi_cmd {
+	unsigned char		cmd[16];					/* command				   */
+	/* for request sense */
+	unsigned char		sense_buf[64]
+		__attribute__((aligned(ARCH_DMA_MINALIGN)));
+	unsigned char		status;						/* SCSI Status			 */
+	unsigned char		target;						/* Target ID				 */
+	unsigned char		lun;							/* Target LUN        */
+	unsigned char		cmdlen;						/* command len				*/
+	unsigned long		datalen;					/* Total data length	*/
+	unsigned char	*	pdata;						/* pointer to data		*/
+	unsigned char		msgout[12];				/* Messge out buffer (NOT USED) */
+	unsigned char		msgin[12];				/* Message in buffer	*/
+	unsigned char		sensecmdlen;			/* Sense command len	*/
+	unsigned long		sensedatalen;			/* Sense data len			*/
+	unsigned char		sensecmd[6];			/* Sense command			*/
+	unsigned long		contr_stat;				/* Controller Status	*/
+	unsigned long		trans_bytes;			/* tranfered bytes		*/
+
+	unsigned int		priv;
+	enum dma_data_direction	dma_dir;
+};
+
+/*-----------------------------------------------------------
+**
+**	SCSI  constants.
+**
+**-----------------------------------------------------------
+*/
+
+/*
+**	Messages
+*/
+
+#define	M_COMPLETE	(0x00)
+#define	M_EXTENDED	(0x01)
+#define	M_SAVE_DP	(0x02)
+#define	M_RESTORE_DP	(0x03)
+#define	M_DISCONNECT	(0x04)
+#define	M_ID_ERROR	(0x05)
+#define	M_ABORT		(0x06)
+#define	M_REJECT	(0x07)
+#define	M_NOOP		(0x08)
+#define	M_PARITY	(0x09)
+#define	M_LCOMPLETE	(0x0a)
+#define	M_FCOMPLETE	(0x0b)
+#define	M_RESET		(0x0c)
+#define	M_ABORT_TAG	(0x0d)
+#define	M_CLEAR_QUEUE	(0x0e)
+#define	M_INIT_REC	(0x0f)
+#define	M_REL_REC	(0x10)
+#define	M_TERMINATE	(0x11)
+#define	M_SIMPLE_TAG	(0x20)
+#define	M_HEAD_TAG	(0x21)
+#define	M_ORDERED_TAG	(0x22)
+#define	M_IGN_RESIDUE	(0x23)
+#define	M_IDENTIFY	(0x80)
+
+#define	M_X_MODIFY_DP	(0x00)
+#define	M_X_SYNC_REQ	(0x01)
+#define	M_X_WIDE_REQ	(0x03)
+#define	M_X_PPR_REQ	(0x04)
+
+
+/*
+**	Status
+*/
+
+#define	S_GOOD		(0x00)
+#define	S_CHECK_COND	(0x02)
+#define	S_COND_MET	(0x04)
+#define	S_BUSY		(0x08)
+#define	S_INT		(0x10)
+#define	S_INT_COND_MET	(0x14)
+#define	S_CONFLICT	(0x18)
+#define	S_TERMINATED	(0x20)
+#define	S_QUEUE_FULL	(0x28)
+#define	S_ILLEGAL	(0xff)
+#define	S_SENSE		(0x80)
+
+/*
+ * Sense_keys
+ */
+
+#define SENSE_NO_SENSE				0x0
+#define SENSE_RECOVERED_ERROR	0x1
+#define SENSE_NOT_READY				0x2
+#define SENSE_MEDIUM_ERROR		0x3
+#define SENSE_HARDWARE_ERROR	0x4
+#define SENSE_ILLEGAL_REQUEST	0x5
+#define SENSE_UNIT_ATTENTION	0x6
+#define SENSE_DATA_PROTECT		0x7
+#define SENSE_BLANK_CHECK			0x8
+#define SENSE_VENDOR_SPECIFIC	0x9
+#define SENSE_COPY_ABORTED		0xA
+#define SENSE_ABORTED_COMMAND	0xB
+#define SENSE_VOLUME_OVERFLOW	0xD
+#define SENSE_MISCOMPARE			0xE
+
+
+#define SCSI_CHANGE_DEF	0x40		/* Change Definition (Optional) */
+#define SCSI_COMPARE		0x39		/* Compare (O) */
+#define SCSI_COPY			0x18		/* Copy (O) */
+#define SCSI_COP_VERIFY	0x3A		/* Copy and Verify (O) */
+#define SCSI_INQUIRY		0x12		/* Inquiry (MANDATORY) */
+#define SCSI_LOG_SELECT	0x4C		/* Log Select (O) */
+#define SCSI_LOG_SENSE	0x4D		/* Log Sense (O) */
+#define SCSI_MODE_SEL6	0x15		/* Mode Select 6-byte (Device Specific) */
+#define SCSI_MODE_SEL10	0x55		/* Mode Select 10-byte (Device Specific) */
+#define SCSI_MODE_SEN6	0x1A		/* Mode Sense 6-byte (Device Specific) */
+#define SCSI_MODE_SEN10	0x5A		/* Mode Sense 10-byte (Device Specific) */
+#define SCSI_READ_BUFF	0x3C		/* Read Buffer (O) */
+#define SCSI_REQ_SENSE	0x03		/* Request Sense (MANDATORY) */
+#define SCSI_SEND_DIAG	0x1D		/* Send Diagnostic (O) */
+#define SCSI_TST_U_RDY	0x00		/* Test Unit Ready (MANDATORY) */
+#define SCSI_WRITE_BUFF	0x3B		/* Write Buffer (O) */
+/***************************************************************************
+ *			  %%% Commands Unique to Direct Access Devices %%%
+ ***************************************************************************/
+#define SCSI_COMPARE		0x39		/* Compare (O) */
+#define SCSI_FORMAT		0x04		/* Format Unit (MANDATORY) */
+#define SCSI_LCK_UN_CAC	0x36		/* Lock Unlock Cache (O) */
+#define SCSI_PREFETCH	0x34		/* Prefetch (O) */
+#define SCSI_MED_REMOVL	0x1E		/* Prevent/Allow medium Removal (O) */
+#define SCSI_READ6		0x08		/* Read 6-byte (MANDATORY) */
+#define SCSI_READ10		0x28		/* Read 10-byte (MANDATORY) */
+#define SCSI_READ16	0x48
+#define SCSI_RD_CAPAC	0x25		/* Read Capacity (MANDATORY) */
+#define SCSI_RD_CAPAC10	SCSI_RD_CAPAC	/* Read Capacity (10) */
+#define SCSI_RD_CAPAC16	0x9e		/* Read Capacity (16) */
+#define SCSI_RD_DEFECT	0x37		/* Read Defect Data (O) */
+#define SCSI_READ_LONG	0x3E		/* Read Long (O) */
+#define SCSI_REASS_BLK	0x07		/* Reassign Blocks (O) */
+#define SCSI_RCV_DIAG	0x1C		/* Receive Diagnostic Results (O) */
+#define SCSI_RELEASE	0x17		/* Release Unit (MANDATORY) */
+#define SCSI_REZERO		0x01		/* Rezero Unit (O) */
+#define SCSI_SRCH_DAT_E	0x31		/* Search Data Equal (O) */
+#define SCSI_SRCH_DAT_H	0x30		/* Search Data High (O) */
+#define SCSI_SRCH_DAT_L	0x32		/* Search Data Low (O) */
+#define SCSI_SEEK6		0x0B		/* Seek 6-Byte (O) */
+#define SCSI_SEEK10		0x2B		/* Seek 10-Byte (O) */
+#define SCSI_SEND_DIAG	0x1D		/* Send Diagnostics (MANDATORY) */
+#define SCSI_SET_LIMIT	0x33		/* Set Limits (O) */
+#define SCSI_START_STP	0x1B		/* Start/Stop Unit (O) */
+#define SCSI_SYNC_CACHE	0x35		/* Synchronize Cache (O) */
+#define SCSI_VERIFY		0x2F		/* Verify (O) */
+#define SCSI_WRITE6		0x0A		/* Write 6-Byte (MANDATORY) */
+#define SCSI_WRITE10	0x2A		/* Write 10-Byte (MANDATORY) */
+#define SCSI_WRT_VERIFY	0x2E		/* Write and Verify (O) */
+#define SCSI_WRITE_LONG	0x3F		/* Write Long (O) */
+#define SCSI_WRITE_SAME	0x41		/* Write Same (O) */
+
+/**
+ * struct scsi_platdata - stores information about SCSI controller
+ *
+ * @base: Controller base address
+ * @max_lun: Maximum number of logical units
+ * @max_id: Maximum number of target ids
+ * @max_bytes_per_req: Maximum number of bytes per read/write request
+ */
+struct scsi_platdata {
+	unsigned long base;
+	unsigned long max_lun;
+	unsigned long max_id;
+	unsigned long max_bytes_per_req;
+};
+
+/* Operations for SCSI */
+struct scsi_ops {
+	/**
+	 * exec() - execute a command
+	 *
+	 * @dev:	SCSI bus
+	 * @cmd:	Command to execute
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*exec)(struct udevice *dev, struct scsi_cmd *cmd);
+
+	/**
+	 * bus_reset() - reset the bus
+	 *
+	 * @dev:	SCSI bus to reset
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*bus_reset)(struct udevice *dev);
+};
+
+#define scsi_get_ops(dev)        ((struct scsi_ops *)(dev)->driver->ops)
+
+extern struct scsi_ops scsi_ops;
+
+/**
+ * scsi_exec() - execute a command
+ *
+ * @dev:	SCSI bus
+ * @cmd:	Command to execute
+ * @return 0 if OK, -ve on error
+ */
+int scsi_exec(struct udevice *dev, struct scsi_cmd *cmd);
+
+/**
+ * scsi_bus_reset() - reset the bus
+ *
+ * @dev:	SCSI bus to reset
+ * @return 0 if OK, -ve on error
+ */
+int scsi_bus_reset(struct udevice *dev);
+
+/**
+ * scsi_scan() - Scan all SCSI controllers for available devices
+ *
+ * @vebose: true to show information about each device found
+ */
+int scsi_scan(bool verbose);
+
+/**
+ * scsi_scan_dev() - scan a SCSI bus and create devices
+ *
+ * @dev:	SCSI bus
+ * @verbose:	true to show information about each device found
+ */
+int scsi_scan_dev(struct udevice *dev, bool verbose);
+
+#ifndef CONFIG_DM_SCSI
+void scsi_low_level_init(int busdevfunc);
+void scsi_init(void);
+#endif
+
+#define SCSI_IDENTIFY					0xC0  /* not used */
+
+/* Hardware errors  */
+#define SCSI_SEL_TIME_OUT			 0x00000101	 /* Selection time out */
+#define SCSI_HNS_TIME_OUT			 0x00000102  /* Handshake */
+#define SCSI_MA_TIME_OUT			 0x00000103  /* Phase error */
+#define SCSI_UNEXP_DIS				 0x00000104  /* unexpected disconnect */
+
+#define SCSI_INT_STATE				 0x00010000  /* unknown Interrupt number is stored in 16 LSB */
+
+#endif /* _SCSI_H */
diff --git a/include/sdhci.h b/include/sdhci.h
new file mode 100644
index 0000000..01addb7
--- /dev/null
+++ b/include/sdhci.h
@@ -0,0 +1,495 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * Back ported to the 8xx platform (from the 8260 platform) by
+ * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
+ */
+#ifndef __SDHCI_HW_H
+#define __SDHCI_HW_H
+
+#include <asm/io.h>
+#include <mmc.h>
+#include <asm/gpio.h>
+
+/*
+ * Controller registers
+ */
+
+#define SDHCI_DMA_ADDRESS	0x00
+
+#define SDHCI_BLOCK_SIZE	0x04
+#define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
+
+#define SDHCI_BLOCK_COUNT	0x06
+
+#define SDHCI_ARGUMENT		0x08
+
+#define SDHCI_TRANSFER_MODE	0x0C
+#define  SDHCI_TRNS_DMA		BIT(0)
+#define  SDHCI_TRNS_BLK_CNT_EN	BIT(1)
+#define  SDHCI_TRNS_ACMD12	BIT(2)
+#define  SDHCI_TRNS_READ	BIT(4)
+#define  SDHCI_TRNS_MULTI	BIT(5)
+
+#define SDHCI_COMMAND		0x0E
+#define  SDHCI_CMD_RESP_MASK	0x03
+#define  SDHCI_CMD_CRC		0x08
+#define  SDHCI_CMD_INDEX	0x10
+#define  SDHCI_CMD_DATA		0x20
+#define  SDHCI_CMD_ABORTCMD	0xC0
+
+#define  SDHCI_CMD_RESP_NONE	0x00
+#define  SDHCI_CMD_RESP_LONG	0x01
+#define  SDHCI_CMD_RESP_SHORT	0x02
+#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
+
+#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
+#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
+
+#define SDHCI_RESPONSE		0x10
+
+#define SDHCI_BUFFER		0x20
+
+#define SDHCI_PRESENT_STATE	0x24
+#define  SDHCI_CMD_INHIBIT	BIT(0)
+#define  SDHCI_DATA_INHIBIT	BIT(1)
+#define  SDHCI_DOING_WRITE	BIT(8)
+#define  SDHCI_DOING_READ	BIT(9)
+#define  SDHCI_SPACE_AVAILABLE	BIT(10)
+#define  SDHCI_DATA_AVAILABLE	BIT(11)
+#define  SDHCI_CARD_PRESENT	BIT(16)
+#define  SDHCI_CARD_STATE_STABLE	BIT(17)
+#define  SDHCI_CARD_DETECT_PIN_LEVEL	BIT(18)
+#define  SDHCI_WRITE_PROTECT	BIT(19)
+
+#define SDHCI_HOST_CONTROL	0x28
+#define  SDHCI_CTRL_LED		BIT(0)
+#define  SDHCI_CTRL_4BITBUS	BIT(1)
+#define  SDHCI_CTRL_HISPD	BIT(2)
+#define  SDHCI_CTRL_DMA_MASK	0x18
+#define   SDHCI_CTRL_SDMA	0x00
+#define   SDHCI_CTRL_ADMA1	0x08
+#define   SDHCI_CTRL_ADMA32	0x10
+#define   SDHCI_CTRL_ADMA64	0x18
+#define  SDHCI_CTRL_8BITBUS	BIT(5)
+#define  SDHCI_CTRL_CD_TEST_INS	BIT(6)
+#define  SDHCI_CTRL_CD_TEST	BIT(7)
+
+#define SDHCI_POWER_CONTROL	0x29
+#define  SDHCI_POWER_ON		0x01
+#define  SDHCI_POWER_180	0x0A
+#define  SDHCI_POWER_300	0x0C
+#define  SDHCI_POWER_330	0x0E
+
+#define SDHCI_BLOCK_GAP_CONTROL	0x2A
+
+#define SDHCI_WAKE_UP_CONTROL	0x2B
+#define  SDHCI_WAKE_ON_INT	BIT(0)
+#define  SDHCI_WAKE_ON_INSERT	BIT(1)
+#define  SDHCI_WAKE_ON_REMOVE	BIT(2)
+
+#define SDHCI_CLOCK_CONTROL	0x2C
+#define  SDHCI_DIVIDER_SHIFT	8
+#define  SDHCI_DIVIDER_HI_SHIFT	6
+#define  SDHCI_DIV_MASK	0xFF
+#define  SDHCI_DIV_MASK_LEN	8
+#define  SDHCI_DIV_HI_MASK	0x300
+#define  SDHCI_PROG_CLOCK_MODE  BIT(5)
+#define  SDHCI_CLOCK_CARD_EN	BIT(2)
+#define  SDHCI_CLOCK_INT_STABLE	BIT(1)
+#define  SDHCI_CLOCK_INT_EN	BIT(0)
+
+#define SDHCI_TIMEOUT_CONTROL	0x2E
+
+#define SDHCI_SOFTWARE_RESET	0x2F
+#define  SDHCI_RESET_ALL	0x01
+#define  SDHCI_RESET_CMD	0x02
+#define  SDHCI_RESET_DATA	0x04
+
+#define SDHCI_INT_STATUS	0x30
+#define SDHCI_INT_ENABLE	0x34
+#define SDHCI_SIGNAL_ENABLE	0x38
+#define  SDHCI_INT_RESPONSE	BIT(0)
+#define  SDHCI_INT_DATA_END	BIT(1)
+#define  SDHCI_INT_DMA_END	BIT(3)
+#define  SDHCI_INT_SPACE_AVAIL	BIT(4)
+#define  SDHCI_INT_DATA_AVAIL	BIT(5)
+#define  SDHCI_INT_CARD_INSERT	BIT(6)
+#define  SDHCI_INT_CARD_REMOVE	BIT(7)
+#define  SDHCI_INT_CARD_INT	BIT(8)
+#define  SDHCI_INT_ERROR	BIT(15)
+#define  SDHCI_INT_TIMEOUT	BIT(16)
+#define  SDHCI_INT_CRC		BIT(17)
+#define  SDHCI_INT_END_BIT	BIT(18)
+#define  SDHCI_INT_INDEX	BIT(19)
+#define  SDHCI_INT_DATA_TIMEOUT	BIT(20)
+#define  SDHCI_INT_DATA_CRC	BIT(21)
+#define  SDHCI_INT_DATA_END_BIT	BIT(22)
+#define  SDHCI_INT_BUS_POWER	BIT(23)
+#define  SDHCI_INT_ACMD12ERR	BIT(24)
+#define  SDHCI_INT_ADMA_ERROR	BIT(25)
+
+#define  SDHCI_INT_NORMAL_MASK	0x00007FFF
+#define  SDHCI_INT_ERROR_MASK	0xFFFF8000
+
+#define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
+		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
+#define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
+		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
+		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
+		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
+#define SDHCI_INT_ALL_MASK	((unsigned int)-1)
+
+#define SDHCI_ACMD12_ERR	0x3C
+
+#define SDHCI_HOST_CONTROL2	0x3E
+#define  SDHCI_CTRL_UHS_MASK	0x0007
+#define  SDHCI_CTRL_UHS_SDR12	0x0000
+#define  SDHCI_CTRL_UHS_SDR25	0x0001
+#define  SDHCI_CTRL_UHS_SDR50	0x0002
+#define  SDHCI_CTRL_UHS_SDR104	0x0003
+#define  SDHCI_CTRL_UHS_DDR50	0x0004
+#define  SDHCI_CTRL_HS400	0x0005 /* Non-standard */
+#define  SDHCI_CTRL_VDD_180	0x0008
+#define  SDHCI_CTRL_DRV_TYPE_MASK	0x0030
+#define  SDHCI_CTRL_DRV_TYPE_B	0x0000
+#define  SDHCI_CTRL_DRV_TYPE_A	0x0010
+#define  SDHCI_CTRL_DRV_TYPE_C	0x0020
+#define  SDHCI_CTRL_DRV_TYPE_D	0x0030
+#define  SDHCI_CTRL_EXEC_TUNING	0x0040
+#define  SDHCI_CTRL_TUNED_CLK	0x0080
+#define  SDHCI_CTRL_PRESET_VAL_ENABLE	0x8000
+
+#define SDHCI_CAPABILITIES	0x40
+#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
+#define  SDHCI_TIMEOUT_CLK_SHIFT 0
+#define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
+#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
+#define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
+#define  SDHCI_CLOCK_BASE_SHIFT	8
+#define  SDHCI_MAX_BLOCK_MASK	0x00030000
+#define  SDHCI_MAX_BLOCK_SHIFT  16
+#define  SDHCI_CAN_DO_8BIT	BIT(18)
+#define  SDHCI_CAN_DO_ADMA2	BIT(19)
+#define  SDHCI_CAN_DO_ADMA1	BIT(20)
+#define  SDHCI_CAN_DO_HISPD	BIT(21)
+#define  SDHCI_CAN_DO_SDMA	BIT(22)
+#define  SDHCI_CAN_VDD_330	BIT(24)
+#define  SDHCI_CAN_VDD_300	BIT(25)
+#define  SDHCI_CAN_VDD_180	BIT(26)
+#define  SDHCI_CAN_64BIT	BIT(28)
+
+#define SDHCI_CAPABILITIES_1	0x44
+#define  SDHCI_SUPPORT_SDR50	0x00000001
+#define  SDHCI_SUPPORT_SDR104	0x00000002
+#define  SDHCI_SUPPORT_DDR50	0x00000004
+#define  SDHCI_USE_SDR50_TUNING	0x00002000
+
+#define  SDHCI_CLOCK_MUL_MASK	0x00FF0000
+#define  SDHCI_CLOCK_MUL_SHIFT	16
+
+#define SDHCI_MAX_CURRENT	0x48
+
+/* 4C-4F reserved for more max current */
+
+#define SDHCI_SET_ACMD12_ERROR	0x50
+#define SDHCI_SET_INT_ERROR	0x52
+
+#define SDHCI_ADMA_ERROR	0x54
+
+/* 55-57 reserved */
+
+#define SDHCI_ADMA_ADDRESS	0x58
+#define SDHCI_ADMA_ADDRESS_HI	0x5c
+
+/* 60-FB reserved */
+
+#define SDHCI_SLOT_INT_STATUS	0xFC
+
+#define SDHCI_HOST_VERSION	0xFE
+#define  SDHCI_VENDOR_VER_MASK	0xFF00
+#define  SDHCI_VENDOR_VER_SHIFT	8
+#define  SDHCI_SPEC_VER_MASK	0x00FF
+#define  SDHCI_SPEC_VER_SHIFT	0
+#define   SDHCI_SPEC_100	0
+#define   SDHCI_SPEC_200	1
+#define   SDHCI_SPEC_300	2
+
+#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
+
+/*
+ * End of controller registers.
+ */
+
+#define SDHCI_MAX_DIV_SPEC_200	256
+#define SDHCI_MAX_DIV_SPEC_300	2046
+
+/*
+ * quirks
+ */
+#define SDHCI_QUIRK_32BIT_DMA_ADDR	(1 << 0)
+#define SDHCI_QUIRK_REG32_RW		(1 << 1)
+#define SDHCI_QUIRK_BROKEN_R1B		(1 << 2)
+#define SDHCI_QUIRK_NO_HISPD_BIT	(1 << 3)
+#define SDHCI_QUIRK_BROKEN_VOLTAGE	(1 << 4)
+/*
+ * SDHCI_QUIRK_BROKEN_HISPD_MODE
+ * the hardware cannot operate correctly in high-speed mode,
+ * this quirk forces the sdhci host-controller to non high-speed mode
+ */
+#define SDHCI_QUIRK_BROKEN_HISPD_MODE	BIT(5)
+#define SDHCI_QUIRK_WAIT_SEND_CMD	(1 << 6)
+#define SDHCI_QUIRK_USE_WIDE8		(1 << 8)
+#define SDHCI_QUIRK_NO_1_8_V		(1 << 9)
+
+/* to make gcc happy */
+struct sdhci_host;
+
+/*
+ * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
+ */
+#define SDHCI_DEFAULT_BOUNDARY_SIZE	(512 * 1024)
+#define SDHCI_DEFAULT_BOUNDARY_ARG	(7)
+struct sdhci_ops {
+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
+	u32	(*read_l)(struct sdhci_host *host, int reg);
+	u16	(*read_w)(struct sdhci_host *host, int reg);
+	u8	(*read_b)(struct sdhci_host *host, int reg);
+	void	(*write_l)(struct sdhci_host *host, u32 val, int reg);
+	void	(*write_w)(struct sdhci_host *host, u16 val, int reg);
+	void	(*write_b)(struct sdhci_host *host, u8 val, int reg);
+#endif
+	int	(*get_cd)(struct sdhci_host *host);
+	void	(*set_control_reg)(struct sdhci_host *host);
+	int	(*set_ios_post)(struct sdhci_host *host);
+	void	(*set_clock)(struct sdhci_host *host, u32 div);
+	int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
+	void (*set_delay)(struct sdhci_host *host);
+};
+
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+#define ADMA_MAX_LEN	65532
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+#define ADMA_DESC_LEN	16
+#else
+#define ADMA_DESC_LEN	8
+#endif
+#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
+			       MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
+
+#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
+
+/* Decriptor table defines */
+#define ADMA_DESC_ATTR_VALID		BIT(0)
+#define ADMA_DESC_ATTR_END		BIT(1)
+#define ADMA_DESC_ATTR_INT		BIT(2)
+#define ADMA_DESC_ATTR_ACT1		BIT(4)
+#define ADMA_DESC_ATTR_ACT2		BIT(5)
+
+#define ADMA_DESC_TRANSFER_DATA		ADMA_DESC_ATTR_ACT2
+#define ADMA_DESC_LINK_DESC	(ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
+
+struct sdhci_adma_desc {
+	u8 attr;
+	u8 reserved;
+	u16 len;
+	u32 addr_lo;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+	u32 addr_hi;
+#endif
+} __packed;
+#endif
+struct sdhci_host {
+	const char *name;
+	void *ioaddr;
+	unsigned int quirks;
+	unsigned int host_caps;
+	unsigned int version;
+	unsigned int max_clk;   /* Maximum Base Clock frequency */
+	unsigned int clk_mul;   /* Clock Multiplier value */
+	unsigned int clock;
+	struct mmc *mmc;
+	const struct sdhci_ops *ops;
+	int index;
+
+	int bus_width;
+	struct gpio_desc pwr_gpio;	/* Power GPIO */
+	struct gpio_desc cd_gpio;		/* Card Detect GPIO */
+
+	uint	voltages;
+
+	struct mmc_config cfg;
+	dma_addr_t start_addr;
+	int flags;
+#define USE_SDMA	(0x1 << 0)
+#define USE_ADMA	(0x1 << 1)
+#define USE_ADMA64	(0x1 << 2)
+#define USE_DMA		(USE_SDMA | USE_ADMA | USE_ADMA64)
+	dma_addr_t adma_addr;
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+	struct sdhci_adma_desc *adma_desc_table;
+	uint desc_slot;
+#endif
+};
+
+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
+
+static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	if (unlikely(host->ops->write_l))
+		host->ops->write_l(host, val, reg);
+	else
+		writel(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
+{
+	if (unlikely(host->ops->write_w))
+		host->ops->write_w(host, val, reg);
+	else
+		writew(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+	if (unlikely(host->ops->write_b))
+		host->ops->write_b(host, val, reg);
+	else
+		writeb(val, host->ioaddr + reg);
+}
+
+static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
+{
+	if (unlikely(host->ops->read_l))
+		return host->ops->read_l(host, reg);
+	else
+		return readl(host->ioaddr + reg);
+}
+
+static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
+{
+	if (unlikely(host->ops->read_w))
+		return host->ops->read_w(host, reg);
+	else
+		return readw(host->ioaddr + reg);
+}
+
+static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
+{
+	if (unlikely(host->ops->read_b))
+		return host->ops->read_b(host, reg);
+	else
+		return readb(host->ioaddr + reg);
+}
+
+#else
+
+static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	writel(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
+{
+	writew(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+	writeb(val, host->ioaddr + reg);
+}
+static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
+{
+	return readl(host->ioaddr + reg);
+}
+
+static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
+{
+	return readw(host->ioaddr + reg);
+}
+
+static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
+{
+	return readb(host->ioaddr + reg);
+}
+#endif
+
+#ifdef CONFIG_BLK
+/**
+ * sdhci_setup_cfg() - Set up the configuration for DWMMC
+ *
+ * This is used to set up an SDHCI device when you are using CONFIG_BLK.
+ *
+ * This should be called from your MMC driver's probe() method once you have
+ * the information required.
+ *
+ * Generally your driver will have a platform data structure which holds both
+ * the configuration (struct mmc_config) and the MMC device info (struct mmc).
+ * For example:
+ *
+ * struct msm_sdhc_plat {
+ *	struct mmc_config cfg;
+ *	struct mmc mmc;
+ * };
+ *
+ * ...
+ *
+ * Inside U_BOOT_DRIVER():
+ *	.platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
+ *
+ * To access platform data:
+ *	struct msm_sdhc_plat *plat = dev_get_platdata(dev);
+ *
+ * See msm_sdhci.c for an example.
+ *
+ * @cfg:	Configuration structure to fill in (generally &plat->mmc)
+ * @host:	SDHCI host structure
+ * @f_max:	Maximum supported clock frequency in HZ (0 for default)
+ * @f_min:	Minimum supported clock frequency in HZ (0 for default)
+ */
+int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
+		    u32 f_max, u32 f_min);
+
+/**
+ * sdhci_bind() - Set up a new MMC block device
+ *
+ * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
+ * It should be called from your driver's bind() method.
+ *
+ * See msm_sdhci.c for an example.
+ *
+ * @dev:	Device to set up
+ * @mmc:	Pointer to mmc structure (normally &plat->mmc)
+ * @cfg:	Empty configuration structure (generally &plat->cfg). This is
+ *		normally all zeroes at this point. The only purpose of passing
+ *		this in is to set mmc->cfg to it.
+ * @return 0 if OK, -ve if the block device could not be created
+ */
+int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
+#else
+
+/**
+ * add_sdhci() - Add a new SDHCI interface
+ *
+ * This is used when you are not using CONFIG_BLK. Convert your driver over!
+ *
+ * @host:	SDHCI host structure
+ * @f_max:	Maximum supported clock frequency in HZ (0 for default)
+ * @f_min:	Minimum supported clock frequency in HZ (0 for default)
+ * @return 0 if OK, -ve on error
+ */
+int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
+#endif /* !CONFIG_BLK */
+
+void sdhci_set_uhs_timing(struct sdhci_host *host);
+#ifdef CONFIG_DM_MMC
+/* Export the operations to drivers */
+int sdhci_probe(struct udevice *dev);
+int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
+extern const struct dm_mmc_ops sdhci_ops;
+#else
+#endif
+
+#endif /* __SDHCI_HW_H */
diff --git a/include/sdp.h b/include/sdp.h
new file mode 100644
index 0000000..6ac64fb
--- /dev/null
+++ b/include/sdp.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * sdp.h - Serial Download Protocol
+ *
+ * Copyright (C) 2017 Toradex
+ * Author: Stefan Agner <stefan.agner@toradex.com>
+ */
+
+#ifndef __SDP_H_
+#define __SDP_H_
+
+int sdp_init(int controller_index);
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+
+int spl_sdp_handle(int controller_index, struct spl_image_info *spl_image);
+#else
+int sdp_handle(int controller_index);
+#endif
+
+#endif /* __SDP_H_ */
diff --git a/include/search.h b/include/search.h
new file mode 100644
index 0000000..0469a85
--- /dev/null
+++ b/include/search.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: LGPL-2.1+ */
+/*
+ * Declarations for System V style searching functions.
+ * Copyright (C) 1995-1999, 2000 Free Software Foundation, Inc.
+ * This file is part of the GNU C Library.
+ */
+
+/*
+ * Based on code from uClibc-0.9.30.3
+ * Extensions for use within U-Boot
+ * Copyright (C) 2010-2013 Wolfgang Denk <wd@denx.de>
+ */
+
+#ifndef _SEARCH_H_
+#define _SEARCH_H_
+
+#include <env.h>
+#include <stddef.h>
+
+#define set_errno(val) do { errno = val; } while (0)
+
+/* enum env_action: action which shall be performed in the call to hsearch */
+enum env_action {
+	ENV_FIND,
+	ENV_ENTER,
+};
+
+/** struct env_entry - An entry in the environment hashtable */
+struct env_entry {
+	const char *key;
+	char *data;
+	int (*callback)(const char *name, const char *value, enum env_op op,
+		int flags);
+	int flags;
+};
+
+/*
+ * Family of hash table handling functions.  The functions also
+ * have reentrant counterparts ending with _r.  The non-reentrant
+ * functions all work on a single internal hash table.
+ */
+
+/* Data type for reentrant functions.  */
+struct hsearch_data {
+	struct env_entry_node *table;
+	unsigned int size;
+	unsigned int filled;
+/*
+ * Callback function which will check whether the given change for variable
+ * "item" to "newval" may be applied or not, and possibly apply such change.
+ * When (flag & H_FORCE) is set, it shall not print out any error message and
+ * shall force overwriting of write-once variables.
+ * Must return 0 for approval, 1 for denial.
+ */
+	int (*change_ok)(const struct env_entry *item, const char *newval,
+			 enum env_op, int flag);
+};
+
+/* Create a new hash table which will contain at most "nel" elements.  */
+int hcreate_r(size_t nel, struct hsearch_data *htab);
+
+/* Destroy current internal hash table.  */
+void hdestroy_r(struct hsearch_data *htab);
+
+/*
+ * Search for entry matching item.key in internal hash table.  If
+ * action is `ENV_FIND' return found entry or signal error by returning
+ * NULL.  If action is `ENV_ENTER' replace existing data (if any) with
+ * item.data.
+ * */
+int hsearch_r(struct env_entry item, enum env_action action,
+	      struct env_entry **retval, struct hsearch_data *htab, int flag);
+
+/*
+ * Search for an entry matching "match".  Otherwise, Same semantics
+ * as hsearch_r().
+ */
+int hmatch_r(const char *match, int last_idx, struct env_entry **retval,
+	     struct hsearch_data *htab);
+
+/* Search and delete entry matching "key" in internal hash table. */
+int hdelete_r(const char *key, struct hsearch_data *htab, int flag);
+
+ssize_t hexport_r(struct hsearch_data *htab, const char sep, int flag,
+		  char **resp, size_t size, int argc, char * const argv[]);
+
+/*
+ * nvars: length of vars array
+ * vars: array of strings (variable names) to import (nvars == 0 means all)
+ */
+int himport_r(struct hsearch_data *htab, const char *env, size_t size,
+	      const char sep, int flag, int crlf_is_lf, int nvars,
+	      char * const vars[]);
+
+/* Walk the whole table calling the callback on each element */
+int hwalk_r(struct hsearch_data *htab,
+	    int (*callback)(struct env_entry *entry));
+
+/* Flags for himport_r(), hexport_r(), hdelete_r(), and hsearch_r() */
+#define H_NOCLEAR	(1 << 0) /* do not clear hash table before importing */
+#define H_FORCE		(1 << 1) /* overwrite read-only/write-once variables */
+#define H_INTERACTIVE	(1 << 2) /* indicate that an import is user directed */
+#define H_HIDE_DOT	(1 << 3) /* don't print env vars that begin with '.' */
+#define H_MATCH_KEY	(1 << 4) /* search/grep key  = variable names	     */
+#define H_MATCH_DATA	(1 << 5) /* search/grep data = variable values	     */
+#define H_MATCH_BOTH	(H_MATCH_KEY | H_MATCH_DATA) /* search/grep both     */
+#define H_MATCH_IDENT	(1 << 6) /* search for indentical strings	     */
+#define H_MATCH_SUBSTR	(1 << 7) /* search for substring matches	     */
+#define H_MATCH_REGEX	(1 << 8) /* search for regular expression matches    */
+#define H_MATCH_METHOD	(H_MATCH_IDENT | H_MATCH_SUBSTR | H_MATCH_REGEX)
+#define H_PROGRAMMATIC	(1 << 9) /* indicate that an import is from env_set() */
+#define H_ORIGIN_FLAGS	(H_INTERACTIVE | H_PROGRAMMATIC)
+
+#endif /* _SEARCH_H_ */
diff --git a/include/serial.h b/include/serial.h
new file mode 100644
index 0000000..c1368c6
--- /dev/null
+++ b/include/serial.h
@@ -0,0 +1,325 @@
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#include <post.h>
+
+struct serial_device {
+	/* enough bytes to match alignment of following func pointer */
+	char	name[16];
+
+	int	(*start)(void);
+	int	(*stop)(void);
+	void	(*setbrg)(void);
+	int	(*getc)(void);
+	int	(*tstc)(void);
+	void	(*putc)(const char c);
+	void	(*puts)(const char *s);
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+	void	(*loop)(int);
+#endif
+	struct serial_device	*next;
+};
+
+void default_serial_puts(const char *s);
+
+extern struct serial_device serial_smc_device;
+extern struct serial_device serial_scc_device;
+extern struct serial_device *default_serial_console(void);
+
+#if	defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+	defined(CONFIG_MPC86xx) || \
+	defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
+	defined(CONFIG_MICROBLAZE)
+extern struct serial_device serial0_device;
+extern struct serial_device serial1_device;
+#endif
+
+extern struct serial_device eserial1_device;
+extern struct serial_device eserial2_device;
+extern struct serial_device eserial3_device;
+extern struct serial_device eserial4_device;
+extern struct serial_device eserial5_device;
+extern struct serial_device eserial6_device;
+
+extern void serial_register(struct serial_device *);
+extern void serial_initialize(void);
+extern void serial_stdio_init(void);
+extern int serial_assign(const char *name);
+extern void serial_reinit_all(void);
+
+/* For usbtty */
+#ifdef CONFIG_USB_TTY
+
+extern int usbtty_getc(void);
+extern void usbtty_putc(const char c);
+extern void usbtty_puts(const char *str);
+extern int usbtty_tstc(void);
+
+#else
+
+/* stubs */
+#define usbtty_getc() 0
+#define usbtty_putc(a)
+#define usbtty_puts(a)
+#define usbtty_tstc() 0
+
+#endif /* CONFIG_USB_TTY */
+
+struct udevice;
+
+enum serial_par {
+	SERIAL_PAR_NONE,
+	SERIAL_PAR_ODD,
+	SERIAL_PAR_EVEN
+};
+
+#define SERIAL_PAR_SHIFT	0
+#define SERIAL_PAR_MASK		(0x03 << SERIAL_PAR_SHIFT)
+#define SERIAL_SET_PARITY(parity) \
+	((parity << SERIAL_PAR_SHIFT) & SERIAL_PAR_MASK)
+#define SERIAL_GET_PARITY(config) \
+	((config & SERIAL_PAR_MASK) >> SERIAL_PAR_SHIFT)
+
+enum serial_bits {
+	SERIAL_5_BITS,
+	SERIAL_6_BITS,
+	SERIAL_7_BITS,
+	SERIAL_8_BITS
+};
+
+#define SERIAL_BITS_SHIFT	2
+#define SERIAL_BITS_MASK	(0x3 << SERIAL_BITS_SHIFT)
+#define SERIAL_SET_BITS(bits) \
+	((bits << SERIAL_BITS_SHIFT) & SERIAL_BITS_MASK)
+#define SERIAL_GET_BITS(config) \
+	((config & SERIAL_BITS_MASK) >> SERIAL_BITS_SHIFT)
+
+enum serial_stop {
+	SERIAL_HALF_STOP,	/* 0.5 stop bit */
+	SERIAL_ONE_STOP,	/*   1 stop bit */
+	SERIAL_ONE_HALF_STOP,	/* 1.5 stop bit */
+	SERIAL_TWO_STOP		/*   2 stop bit */
+};
+
+#define SERIAL_STOP_SHIFT	4
+#define SERIAL_STOP_MASK	(0x3 << SERIAL_STOP_SHIFT)
+#define SERIAL_SET_STOP(stop) \
+	((stop << SERIAL_STOP_SHIFT) & SERIAL_STOP_MASK)
+#define SERIAL_GET_STOP(config) \
+	((config & SERIAL_STOP_MASK) >> SERIAL_STOP_SHIFT)
+
+#define SERIAL_CONFIG(par, bits, stop) \
+		     (par << SERIAL_PAR_SHIFT | \
+		      bits << SERIAL_BITS_SHIFT | \
+		      stop << SERIAL_STOP_SHIFT)
+
+#define SERIAL_DEFAULT_CONFIG \
+			(SERIAL_PAR_NONE << SERIAL_PAR_SHIFT | \
+			 SERIAL_8_BITS << SERIAL_BITS_SHIFT | \
+			 SERIAL_ONE_STOP << SERIAL_STOP_SHIFT)
+
+enum serial_chip_type {
+	SERIAL_CHIP_UNKNOWN = -1,
+	SERIAL_CHIP_16550_COMPATIBLE,
+};
+
+enum adr_space_type {
+	SERIAL_ADDRESS_SPACE_MEMORY = 0,
+	SERIAL_ADDRESS_SPACE_IO,
+};
+
+/**
+ * struct serial_device_info - structure to hold serial device info
+ *
+ * @type:	type of the UART chip
+ * @addr_space:	address space to access the registers
+ * @addr:	physical address of the registers
+ * @reg_width:	size (in bytes) of the IO accesses to the registers
+ * @reg_offset:	offset to apply to the @addr from the start of the registers
+ * @reg_shift:	quantity to shift the register offsets by
+ * @baudrate:	baud rate
+ */
+struct serial_device_info {
+	enum serial_chip_type type;
+	enum adr_space_type addr_space;
+	ulong addr;
+	u8 reg_width;
+	u8 reg_offset;
+	u8 reg_shift;
+	unsigned int baudrate;
+};
+
+#define SERIAL_DEFAULT_ADDRESS	0xBADACCE5
+
+/**
+ * struct struct dm_serial_ops - Driver model serial operations
+ *
+ * The uclass interface is implemented by all serial devices which use
+ * driver model.
+ */
+struct dm_serial_ops {
+	/**
+	 * setbrg() - Set up the baud rate generator
+	 *
+	 * Adjust baud rate divisors to set up a new baud rate for this
+	 * device. Not all devices will support all rates. If the rate
+	 * cannot be supported, the driver is free to select the nearest
+	 * available rate. or return -EINVAL if this is not possible.
+	 *
+	 * @dev: Device pointer
+	 * @baudrate: New baud rate to use
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*setbrg)(struct udevice *dev, int baudrate);
+	/**
+	 * getc() - Read a character and return it
+	 *
+	 * If no character is available, this should return -EAGAIN without
+	 * waiting.
+	 *
+	 * @dev: Device pointer
+	 * @return character (0..255), -ve on error
+	 */
+	int (*getc)(struct udevice *dev);
+	/**
+	 * putc() - Write a character
+	 *
+	 * @dev: Device pointer
+	 * @ch: character to write
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*putc)(struct udevice *dev, const char ch);
+	/**
+	 * pending() - Check if input/output characters are waiting
+	 *
+	 * This can be used to return an indication of the number of waiting
+	 * characters if the driver knows this (e.g. by looking at the FIFO
+	 * level). It is acceptable to return 1 if an indeterminant number
+	 * of characters is waiting.
+	 *
+	 * This method is optional.
+	 *
+	 * @dev: Device pointer
+	 * @input: true to check input characters, false for output
+	 * @return number of waiting characters, 0 for none, -ve on error
+	 */
+	int (*pending)(struct udevice *dev, bool input);
+	/**
+	 * clear() - Clear the serial FIFOs/holding registers
+	 *
+	 * This method is optional.
+	 *
+	 * This quickly clears any input/output characters from the UART.
+	 * If this is not possible, but characters still exist, then it
+	 * is acceptable to return -EAGAIN (try again) or -EINVAL (not
+	 * supported).
+	 *
+	 * @dev: Device pointer
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*clear)(struct udevice *dev);
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+	/**
+	 * loop() - Control serial device loopback mode
+	 *
+	 * @dev: Device pointer
+	 * @on: 1 to turn loopback on, 0 to turn if off
+	 */
+	int (*loop)(struct udevice *dev, int on);
+#endif
+
+	/**
+	 * getconfig() - Get the uart configuration
+	 * (parity, 5/6/7/8 bits word length, stop bits)
+	 *
+	 * Get a current config for this device.
+	 *
+	 * @dev: Device pointer
+	 * @serial_config: Returns config information (see SERIAL_... above)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*getconfig)(struct udevice *dev, uint *serial_config);
+	/**
+	 * setconfig() - Set up the uart configuration
+	 * (parity, 5/6/7/8 bits word length, stop bits)
+	 *
+	 * Set up a new config for this device.
+	 *
+	 * @dev: Device pointer
+	 * @serial_config: number of bits, parity and number of stopbits to use
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*setconfig)(struct udevice *dev, uint serial_config);
+	/**
+	 * getinfo() - Get serial device information
+	 *
+	 * @dev: Device pointer
+	 * @info: struct serial_device_info to fill
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*getinfo)(struct udevice *dev, struct serial_device_info *info);
+};
+
+/**
+ * struct serial_dev_priv - information about a device used by the uclass
+ *
+ * @sdev:	stdio device attached to this uart
+ *
+ * @buf:	Pointer to the RX buffer
+ * @rd_ptr:	Read pointer in the RX buffer
+ * @wr_ptr:	Write pointer in the RX buffer
+ */
+struct serial_dev_priv {
+	struct stdio_dev *sdev;
+
+	char *buf;
+	int rd_ptr;
+	int wr_ptr;
+};
+
+/* Access the serial operations for a device */
+#define serial_get_ops(dev)	((struct dm_serial_ops *)(dev)->driver->ops)
+
+/**
+ * serial_getconfig() - Get the uart configuration
+ * (parity, 5/6/7/8 bits word length, stop bits)
+ *
+ * Get a current config for this device.
+ *
+ * @dev: Device pointer
+ * @serial_config: Returns config information (see SERIAL_... above)
+ * @return 0 if OK, -ve on error
+ */
+int serial_getconfig(struct udevice *dev, uint *config);
+
+/**
+ * serial_setconfig() - Set up the uart configuration
+ * (parity, 5/6/7/8 bits word length, stop bits)
+ *
+ * Set up a new config for this device.
+ *
+ * @dev: Device pointer
+ * @serial_config: number of bits, parity and number of stopbits to use
+ * @return 0 if OK, -ve on error
+ */
+int serial_setconfig(struct udevice *dev, uint config);
+
+/**
+ * serial_getinfo() - Get serial device information
+ *
+ * @dev: Device pointer
+ * @info: struct serial_device_info to fill
+ * @return 0 if OK, -ve on error
+ */
+int serial_getinfo(struct udevice *dev, struct serial_device_info *info);
+
+void atmel_serial_initialize(void);
+void mcf_serial_initialize(void);
+void mpc85xx_serial_initialize(void);
+void mxc_serial_initialize(void);
+void ns16550_serial_initialize(void);
+void pl01x_serial_initialize(void);
+void pxa_serial_initialize(void);
+void sh_serial_initialize(void);
+
+#endif
diff --git a/include/sh_pfc.h b/include/sh_pfc.h
new file mode 100644
index 0000000..0692593
--- /dev/null
+++ b/include/sh_pfc.h
@@ -0,0 +1,195 @@
+/*
+ * SuperH Pin Function Controller Support
+ * Copy from Linux kernel. (include/linux/sh_pfc.h)
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (c) 2008 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __SH_PFC_H
+#define __SH_PFC_H
+
+typedef unsigned short pinmux_enum_t;
+typedef unsigned short pinmux_flag_t;
+
+#define PINMUX_TYPE_NONE            0
+#define PINMUX_TYPE_FUNCTION        1
+#define PINMUX_TYPE_GPIO            2
+#define PINMUX_TYPE_OUTPUT          3
+#define PINMUX_TYPE_INPUT           4
+#define PINMUX_TYPE_INPUT_PULLUP    5
+#define PINMUX_TYPE_INPUT_PULLDOWN  6
+
+#define PINMUX_FLAG_TYPE            (0x7)
+#define PINMUX_FLAG_WANT_PULLUP     (1 << 3)
+#define PINMUX_FLAG_WANT_PULLDOWN   (1 << 4)
+
+#define PINMUX_FLAG_DBIT_SHIFT      5
+#define PINMUX_FLAG_DBIT            (0x1f << PINMUX_FLAG_DBIT_SHIFT)
+#define PINMUX_FLAG_DREG_SHIFT      10
+#define PINMUX_FLAG_DREG            (0x3f << PINMUX_FLAG_DREG_SHIFT)
+
+struct pinmux_gpio {
+	pinmux_enum_t enum_id;
+	pinmux_flag_t flags;
+};
+
+#define PINMUX_GPIO(gpio, data_or_mark)[gpio] = { data_or_mark }
+#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
+
+struct pinmux_cfg_reg {
+	unsigned long reg, reg_width, field_width;
+	unsigned long *cnt;
+	pinmux_enum_t *enum_ids;
+	unsigned long *var_field_width;
+};
+
+#define PINMUX_CFG_REG(name, r, r_width, f_width) \
+	.reg = r, .reg_width = r_width, .field_width = f_width,		\
+	.cnt = (unsigned long [r_width / f_width]) {}, \
+	.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
+
+#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
+	.reg = r, .reg_width = r_width,	\
+	.cnt = (unsigned long [r_width]) {}, \
+	.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
+	.enum_ids = (pinmux_enum_t [])
+
+struct pinmux_data_reg {
+	unsigned long reg, reg_width, reg_shadow;
+	pinmux_enum_t *enum_ids;
+	void *mapped_reg;
+};
+
+#define PINMUX_DATA_REG(name, r, r_width) \
+	.reg = r, .reg_width = r_width,	\
+	.enum_ids = (pinmux_enum_t [r_width]) \
+
+struct pinmux_irq {
+	int irq;
+	pinmux_enum_t *enum_ids;
+};
+
+#define PINMUX_IRQ(irq_nr, ids...)			   \
+	{ .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } }	\
+
+struct pinmux_range {
+	pinmux_enum_t begin;
+	pinmux_enum_t end;
+	pinmux_enum_t force;
+};
+
+struct pinmux_info {
+	char *name;
+	pinmux_enum_t reserved_id;
+	struct pinmux_range data;
+	struct pinmux_range input;
+	struct pinmux_range input_pd;
+	struct pinmux_range input_pu;
+	struct pinmux_range output;
+	struct pinmux_range mark;
+	struct pinmux_range function;
+
+	unsigned first_gpio, last_gpio;
+
+	struct pinmux_gpio *gpios;
+	struct pinmux_cfg_reg *cfg_regs;
+	struct pinmux_data_reg *data_regs;
+
+	pinmux_enum_t *gpio_data;
+	unsigned int gpio_data_size;
+
+	struct pinmux_irq *gpio_irq;
+	unsigned int gpio_irq_size;
+
+	struct resource *resource;
+	unsigned int num_resources;
+	unsigned long unlock_reg;
+};
+
+int register_pinmux(struct pinmux_info *pip);
+int unregister_pinmux(struct pinmux_info *pip);
+
+/* helper macro for port */
+#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
+
+#define PORT_10(fn, pfx, sfx) \
+	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),	\
+	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),	\
+	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),	\
+	PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
+
+#define PORT_90(fn, pfx, sfx) \
+	PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx),	\
+	PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx),	\
+	PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx),	\
+	PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx),	\
+	PORT_10(fn, pfx##9, sfx)
+
+#define _PORT_ALL(pfx, sfx) pfx##_##sfx
+#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
+#define PORT_ALL(str)	CPU_ALL_PORT(_PORT_ALL, PORT, str)
+#define GPIO_PORT_ALL()	CPU_ALL_PORT(_GPIO_PORT, , unused)
+#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
+#define GPIO_GFN(str) PINMUX_GPIO(GPIO_GFN_##str, str##_GMARK)
+#define GPIO_IFN(str) PINMUX_GPIO(GPIO_IFN_##str, str##_IMARK)
+
+/* helper macro for pinmux_enum_t */
+#define PORT_DATA_I(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
+
+#define PORT_DATA_I_PD(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
+		    PORT##nr##_IN, PORT##nr##_IN_PD)
+
+#define PORT_DATA_I_PU(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
+		    PORT##nr##_IN, PORT##nr##_IN_PU)
+
+#define PORT_DATA_I_PU_PD(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,			\
+		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+#define PORT_DATA_O(nr)		\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
+
+#define PORT_DATA_IO(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
+		    PORT##nr##_IN)
+
+#define PORT_DATA_IO_PD(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
+		    PORT##nr##_IN, PORT##nr##_IN_PD)
+
+#define PORT_DATA_IO_PU(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
+		    PORT##nr##_IN, PORT##nr##_IN_PU)
+
+#define PORT_DATA_IO_PU_PD(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
+		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+/* helper macro for top 4 bits in PORTnCR */
+#define _PCRH(in, in_pd, in_pu, out)	\
+	0, (out), (in), 0,		\
+	0, 0, 0, 0,			\
+	0, 0, (in_pd), 0,		\
+	0, 0, (in_pu), 0
+
+#define PORTCR(nr, reg)							\
+	{								\
+		PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {		\
+			_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD,		\
+			      PORT##nr##_IN_PU, PORT##nr##_OUT),	\
+				PORT##nr##_FN0, PORT##nr##_FN1,		\
+				PORT##nr##_FN2, PORT##nr##_FN3,		\
+				PORT##nr##_FN4, PORT##nr##_FN5,		\
+				PORT##nr##_FN6, PORT##nr##_FN7 }	\
+	}
+
+#endif /* __SH_PFC_H */
diff --git a/include/sja1000.h b/include/sja1000.h
new file mode 100644
index 0000000..6ceb6f4
--- /dev/null
+++ b/include/sja1000.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu>
+ *
+ * SJA1000 register layout for basic CAN mode
+ */
+
+#ifndef _SJA1000_H_
+#define _SJA1000_H_
+
+/*
+ * SJA1000 register layout in basic can mode
+ */
+struct sja1000_basic_s {
+	u8 cr;
+	u8 cmr;
+	u8 sr;
+	u8 ir;
+	u8 ac;
+	u8 am;
+	u8 btr0;
+	u8 btr1;
+	u8 oc;
+	u8 txb[10];
+	u8 rxb[10];
+	u8 unused;
+	u8 cdr;
+};
+
+/* control register */
+#define CR_RR		0x01
+
+/* output control register */
+#define OC_MODE0	0x01
+#define OC_MODE1	0x02
+#define OC_POL0		0x04
+#define OC_TN0		0x08
+#define OC_TP0		0x10
+#define OC_POL1		0x20
+#define OC_TN1		0x40
+#define OC_TP1		0x80
+
+#endif
diff --git a/include/slre.h b/include/slre.h
new file mode 100644
index 0000000..4b41a4b
--- /dev/null
+++ b/include/slre.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2004-2005 Sergey Lyubka <valenok@gmail.com>
+ * All rights reserved
+ *
+ * "THE BEER-WARE LICENSE" (Revision 42):
+ * Sergey Lyubka wrote this file.  As long as you retain this notice you
+ * can do whatever you want with this stuff. If we meet some day, and you think
+ * this stuff is worth it, you can buy me a beer in return.
+ */
+
+/*
+ * Downloaded Sat Nov  5 17:42:08 CET 2011 at
+ * http://slre.sourceforge.net/1.0/slre.h
+ */
+
+/*
+ * This is a regular expression library that implements a subset of Perl RE.
+ * Please refer to http://slre.sourceforge.net for detailed description.
+ *
+ * Usage example (parsing HTTP request):
+ *
+ * struct slre	slre;
+ * struct cap	captures[4 + 1];  // Number of braket pairs + 1
+ * ...
+ *
+ * slre_compile(&slre,"^(GET|POST) (\S+) HTTP/(\S+?)\r\n");
+ *
+ * if (slre_match(&slre, buf, len, captures)) {
+ *	printf("Request line length: %d\n", captures[0].len);
+ *	printf("Method: %.*s\n", captures[1].len, captures[1].ptr);
+ *	printf("URI: %.*s\n", captures[2].len, captures[2].ptr);
+ * }
+ *
+ * Supported syntax:
+ *	^		Match beginning of a buffer
+ *	$		Match end of a buffer
+ *	()		Grouping and substring capturing
+ *	[...]		Match any character from set
+ *	[^...]		Match any character but ones from set
+ *	\s		Match whitespace
+ *	\S		Match non-whitespace
+ *	\d		Match decimal digit
+ *	\r		Match carriage return
+ *	\n		Match newline
+ *	+		Match one or more times (greedy)
+ *	+?		Match one or more times (non-greedy)
+ *	*		Match zero or more times (greedy)
+ *	*?		Match zero or more times (non-greedy)
+ *	?		Match zero or once
+ *	\xDD		Match byte with hex value 0xDD
+ *	\meta		Match one of the meta character: ^$().[*+?\
+ */
+
+#ifndef SLRE_HEADER_DEFINED
+#define	SLRE_HEADER_DEFINED
+
+/*
+ * Compiled regular expression
+ */
+struct slre {
+	unsigned char	code[256];
+	unsigned char	data[256];
+	int		code_size;
+	int		data_size;
+	int		num_caps;	/* Number of bracket pairs	*/
+	int		anchored;	/* Must match from string start	*/
+	const char	*err_str;	/* Error string			*/
+};
+
+/*
+ * Captured substring
+ */
+struct cap {
+	const char	*ptr;		/* Pointer to the substring	*/
+	int		len;		/* Substring length		*/
+};
+
+/*
+ * Compile regular expression. If success, 1 is returned.
+ * If error, 0 is returned and slre.err_str points to the error message.
+ */
+int slre_compile(struct slre *, const char *re);
+
+/*
+ * Return 1 if match, 0 if no match.
+ * If `captured_substrings' array is not NULL, then it is filled with the
+ * values of captured substrings. captured_substrings[0] element is always
+ * a full matched substring. The round bracket captures start from
+ * captured_substrings[1].
+ * It is assumed that the size of captured_substrings array is enough to
+ * hold all captures. The caller function must make sure it is! So, the
+ * array_size = number_of_round_bracket_pairs + 1
+ */
+int slre_match(const struct slre *, const char *buf, int buf_len,
+	struct cap *captured_substrings);
+
+#ifdef SLRE_TEST
+void slre_dump(const struct slre *r, FILE *fp);
+#endif /* SLRE_TEST */
+#endif /* SLRE_HEADER_DEFINED */
diff --git a/include/smbios.h b/include/smbios.h
new file mode 100644
index 0000000..97b9ddc
--- /dev/null
+++ b/include/smbios.h
@@ -0,0 +1,240 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Adapted from coreboot src/include/smbios.h
+ */
+
+#ifndef _SMBIOS_H_
+#define _SMBIOS_H_
+
+/* SMBIOS spec version implemented */
+#define SMBIOS_MAJOR_VER	3
+#define SMBIOS_MINOR_VER	0
+
+/* SMBIOS structure types */
+enum {
+	SMBIOS_BIOS_INFORMATION = 0,
+	SMBIOS_SYSTEM_INFORMATION = 1,
+	SMBIOS_BOARD_INFORMATION = 2,
+	SMBIOS_SYSTEM_ENCLOSURE = 3,
+	SMBIOS_PROCESSOR_INFORMATION = 4,
+	SMBIOS_CACHE_INFORMATION = 7,
+	SMBIOS_SYSTEM_SLOTS = 9,
+	SMBIOS_PHYS_MEMORY_ARRAY = 16,
+	SMBIOS_MEMORY_DEVICE = 17,
+	SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19,
+	SMBIOS_SYSTEM_BOOT_INFORMATION = 32,
+	SMBIOS_END_OF_TABLE = 127
+};
+
+#define SMBIOS_INTERMEDIATE_OFFSET	16
+#define SMBIOS_STRUCT_EOS_BYTES		2
+
+struct __packed smbios_entry {
+	u8 anchor[4];
+	u8 checksum;
+	u8 length;
+	u8 major_ver;
+	u8 minor_ver;
+	u16 max_struct_size;
+	u8 entry_point_rev;
+	u8 formatted_area[5];
+	u8 intermediate_anchor[5];
+	u8 intermediate_checksum;
+	u16 struct_table_length;
+	u32 struct_table_address;
+	u16 struct_count;
+	u8 bcd_rev;
+};
+
+/* BIOS characteristics */
+#define BIOS_CHARACTERISTICS_PCI_SUPPORTED	(1 << 7)
+#define BIOS_CHARACTERISTICS_UPGRADEABLE	(1 << 11)
+#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT	(1 << 16)
+
+#define BIOS_CHARACTERISTICS_EXT1_ACPI		(1 << 0)
+#define BIOS_CHARACTERISTICS_EXT1_UEFI		(1 << 3)
+#define BIOS_CHARACTERISTICS_EXT2_TARGET	(1 << 2)
+
+struct __packed smbios_type0 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 vendor;
+	u8 bios_ver;
+	u16 bios_start_segment;
+	u8 bios_release_date;
+	u8 bios_rom_size;
+	u64 bios_characteristics;
+	u8 bios_characteristics_ext1;
+	u8 bios_characteristics_ext2;
+	u8 bios_major_release;
+	u8 bios_minor_release;
+	u8 ec_major_release;
+	u8 ec_minor_release;
+	char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_type1 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 manufacturer;
+	u8 product_name;
+	u8 version;
+	u8 serial_number;
+	u8 uuid[16];
+	u8 wakeup_type;
+	u8 sku_number;
+	u8 family;
+	char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+#define SMBIOS_BOARD_FEATURE_HOSTING	(1 << 0)
+#define SMBIOS_BOARD_MOTHERBOARD	10
+
+struct __packed smbios_type2 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 manufacturer;
+	u8 product_name;
+	u8 version;
+	u8 serial_number;
+	u8 asset_tag_number;
+	u8 feature_flags;
+	u8 chassis_location;
+	u16 chassis_handle;
+	u8 board_type;
+	char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+#define SMBIOS_ENCLOSURE_DESKTOP	3
+#define SMBIOS_STATE_SAFE		3
+#define SMBIOS_SECURITY_NONE		3
+
+struct __packed smbios_type3 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 manufacturer;
+	u8 chassis_type;
+	u8 version;
+	u8 serial_number;
+	u8 asset_tag_number;
+	u8 bootup_state;
+	u8 power_supply_state;
+	u8 thermal_state;
+	u8 security_status;
+	u32 oem_defined;
+	u8 height;
+	u8 number_of_power_cords;
+	u8 element_count;
+	u8 element_record_length;
+	char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+#define SMBIOS_PROCESSOR_TYPE_CENTRAL	3
+#define SMBIOS_PROCESSOR_STATUS_ENABLED	1
+#define SMBIOS_PROCESSOR_UPGRADE_NONE	6
+
+#define SMBIOS_PROCESSOR_FAMILY_OTHER	1
+#define SMBIOS_PROCESSOR_FAMILY_UNKNOWN	2
+
+struct __packed smbios_type4 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 socket_designation;
+	u8 processor_type;
+	u8 processor_family;
+	u8 processor_manufacturer;
+	u32 processor_id[2];
+	u8 processor_version;
+	u8 voltage;
+	u16 external_clock;
+	u16 max_speed;
+	u16 current_speed;
+	u8 status;
+	u8 processor_upgrade;
+	u16 l1_cache_handle;
+	u16 l2_cache_handle;
+	u16 l3_cache_handle;
+	u8 serial_number;
+	u8 asset_tag;
+	u8 part_number;
+	u8 core_count;
+	u8 core_enabled;
+	u8 thread_count;
+	u16 processor_characteristics;
+	u16 processor_family2;
+	u16 core_count2;
+	u16 core_enabled2;
+	u16 thread_count2;
+	char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_type32 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 reserved[6];
+	u8 boot_status;
+	u8 eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_type127 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_header {
+	u8 type;
+	u8 length;
+	u16 handle;
+};
+
+/**
+ * fill_smbios_header() - Fill the header of an SMBIOS table
+ *
+ * This fills the header of an SMBIOS table structure.
+ *
+ * @table:	start address of the structure
+ * @type:	the type of structure
+ * @length:	the length of the formatted area of the structure
+ * @handle:	the structure's handle, a unique 16-bit number
+ */
+static inline void fill_smbios_header(void *table, int type,
+				      int length, int handle)
+{
+	struct smbios_header *header = table;
+
+	header->type = type;
+	header->length = length - SMBIOS_STRUCT_EOS_BYTES;
+	header->handle = handle;
+}
+
+/**
+ * Function prototype to write a specific type of SMBIOS structure
+ *
+ * @addr:	start address to write the structure
+ * @handle:	the structure's handle, a unique 16-bit number
+ * @return:	size of the structure
+ */
+typedef int (*smbios_write_type)(ulong *addr, int handle);
+
+/**
+ * write_smbios_table() - Write SMBIOS table
+ *
+ * This writes SMBIOS table at a given address.
+ *
+ * @addr:	start address to write SMBIOS table. If this is not
+ *	16-byte-aligned then it will be aligned before the table is written
+ * @return:	end address of SMBIOS table (and start address for next entry)
+ */
+ulong write_smbios_table(ulong addr);
+
+#endif /* _SMBIOS_H_ */
diff --git a/include/smem.h b/include/smem.h
new file mode 100644
index 0000000..598799d
--- /dev/null
+++ b/include/smem.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * The shared memory system is an allocate-only heap structure that
+ * consists of one of more memory areas that can be accessed by the processors
+ * in the SoC.
+ *
+ * Allocation can be done globally for all processors or to an individual processor.
+ * This is controlled by the @host parameter.
+ *
+ * Allocation and management of heap can be implemented in various ways,
+ * The @item parameter should be used as an index/hash to the memory region.
+ *
+ * Copyright (c) 2018 Ramon Fried <ramon.fried@gmail.com>
+ */
+
+#ifndef _smemh_
+#define _smemh_
+
+/* struct smem_ops: Operations for the SMEM uclass */
+struct smem_ops {
+	/**
+	 * alloc() - allocate space for a smem item
+	 *
+	 * @host:	remote processor id, or -1 for all processors.
+	 * @item:	smem item handle
+	 * @size:	number of bytes to be allocated
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*alloc)(unsigned int host,
+		unsigned int item, size_t size);
+
+	/**
+	 * get() - Resolve ptr of size of a smem item
+	 *
+	 * @host:	the remote processor, of -1 for all processors.
+	 * @item:	smem item handle
+	 * @size:	pointer to be filled out with the size of the item
+	 * @return	pointer on success, NULL on error
+	 */
+	void *(*get)(unsigned int host,
+		unsigned int item, size_t *size);
+
+	/**
+	 * get_free_space() - Get free space in smem in bytes
+	 *
+	 * @host:   the remote processor identifying a partition, or -1
+	 *			for all processors.
+	 * @return	free space, -ve on error
+	 */
+	int (*get_free_space)(unsigned int host);
+};
+
+#define smem_get_ops(dev)	((struct smem_ops *)(dev)->driver->ops)
+
+/**
+ * smem_alloc() - allocate space for a smem item
+ * @host:	remote processor id, or -1
+ * @item:	smem item handle
+ * @size:	number of bytes to be allocated
+ * @return 0 if OK, -ve on error
+ *
+ * Allocate space for a given smem item of size @size, given that the item is
+ * not yet allocated.
+ */
+int smem_alloc(struct udevice *dev, unsigned int host, unsigned int item, size_t size);
+
+/**
+ * smem_get() - resolve ptr of size of a smem item
+ * @host:	the remote processor, or -1 for all processors.
+ * @item:	smem item handle
+ * @size:	pointer to be filled out with size of the item
+ * @return	pointer on success, NULL on error
+ *
+ * Looks up smem item and returns pointer to it. Size of smem
+ * item is returned in @size.
+ */
+void *smem_get(struct udevice *dev, unsigned int host, unsigned int item, size_t *size);
+
+/**
+ * smem_get_free_space() - retrieve amount of free space in a partition
+ * @host:	the remote processor identifying a partition, or -1
+ *			for all processors.
+ * @return	size in bytes, -ve on error
+ *
+ * To be used by smem clients as a quick way to determine if any new
+ * allocations has been made.
+ */
+int smem_get_free_space(struct udevice *dev, unsigned int host);
+
+#endif /* _smem_h_ */
+
diff --git a/include/smsc_lpc47m.h b/include/smsc_lpc47m.h
new file mode 100644
index 0000000..8a972ac
--- /dev/null
+++ b/include/smsc_lpc47m.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _SMSC_LPC47M_H_
+#define _SMSC_LPC47M_H_
+
+/* I/O address of LPC47M */
+#define LPC47M_IO_PORT	0x2e
+
+/* Logical device number */
+#define LPC47M_FDC	0	/* Floppy */
+#define LPC47M_SP2	2	/* Serial Port 2 */
+#define LPC47M_PP	3	/* Parallel Port */
+#define LPC47M_SP1	4	/* Serial Port 1 */
+#define LPC47M_KBC	7	/* Keyboard & Mouse */
+#define LPC47M_PME	10	/* Power Control */
+
+/**
+ * Configure the base I/O port of the specified serial device and enable the
+ * serial device.
+ *
+ * @dev: high 8 bits = super I/O port, low 8 bits = logical device number
+ * @iobase: processor I/O port address to assign to this serial device
+ * @irq: processor IRQ number to assign to this serial device
+ */
+void lpc47m_enable_serial(uint dev, uint iobase, uint irq);
+
+/**
+ * Configure the specified keyboard controller device and enable the keyboard
+ * controller device.
+ *
+ * @dev: high 8 bits = Super I/O port, low 8 bits = logical device number
+ * @irq0: processor IRQ number to assign to keyboard
+ * @irq1: processor IRQ number to assign to mouse
+ */
+void lpc47m_enable_kbc(uint dev, uint irq0, uint irq1);
+
+#endif /* _SMSC_LPC47M_H_ */
diff --git a/include/smsc_sio1007.h b/include/smsc_sio1007.h
new file mode 100644
index 0000000..ca3f3f7
--- /dev/null
+++ b/include/smsc_sio1007.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _SMSC_SIO1007_H_
+#define _SMSC_SIO1007_H_
+
+/*
+ * The I/O base address of SIO1007 at power-up is determined by the SYSOPT0
+ * and SYSOPT1 pins at the deasserting edge of PCIRST#. The combination of
+ * SYSOPT0 and SYSOPT1 determines one of the following addresses.
+ */
+#define SIO1007_IOPORT0		0x002e
+#define SIO1007_IOPORT1		0x004e
+#define SIO1007_IOPORT2		0x162e
+#define SIO1007_IOPORT3		0x164e
+
+/* SIO1007 registers */
+
+#define DEV_POWER_CTRL		0x02
+#define UART1_POWER_ON		(1 << 3)
+#define UART2_POWER_ON		(1 << 7)
+
+#define UART1_IOBASE		0x24
+#define UART2_IOBASE		0x25
+#define UART_IRQ		0x28
+
+#define RTR_IOBASE_HIGH		0x21
+#define RTR_IOBASE_LOW		0x30
+
+#define GPIO0_DIR		0x31
+#define GPIO1_DIR		0x35
+#define GPIO_DIR_INPUT		0
+#define GPIO_DIR_OUTPUT		1
+
+#define GPIO0_POL		0x32
+#define GPIO1_POL		0x36
+#define GPIO_POL_NO_INVERT	0
+#define GPIO_POL_INVERT		1
+
+#define GPIO0_TYPE		0x33
+#define GPIO1_TYPE		0x37
+#define GPIO_TYPE_PUSH_PULL	0
+#define GPIO_TYPE_OPEN_DRAIN	1
+
+#define DEV_ACTIVATE		0x3a
+#define RTR_EN			(1 << 1)
+
+/* Runtime register offset */
+
+#define GPIO0_DATA		0xc
+#define GPIO1_DATA		0xe
+
+/* Number of serial ports supported */
+#define SIO1007_UART_NUM	2
+
+/* Number of gpio pins supported */
+#define GPIO_NUM_PER_GROUP	8
+#define GPIO_GROUP_NUM		2
+#define SIO1007_GPIO_NUM	(GPIO_NUM_PER_GROUP * GPIO_GROUP_NUM)
+
+/**
+ * Configure the I/O port address of the specified serial device and
+ * enable the serial device.
+ *
+ * @port:	SIO1007 I/O port address
+ * @num:	serial device number (0 or 1)
+ * @iobase:	processor I/O port address to assign to this serial device
+ * @irq:	processor IRQ number to assign to this serial device
+ */
+void sio1007_enable_serial(int port, int num, int iobase, int irq);
+
+/**
+ * Configure the I/O port address of the runtime register block and
+ * enable the address decoding.
+ *
+ * @port:	SIO1007 I/O port address
+ * @iobase:	processor I/O port address to assign to the runtime registers
+ */
+void sio1007_enable_runtime(int port, int iobase);
+
+/**
+ * Configure the direction/polority/type of a specified GPIO pin
+ *
+ * @port:	SIO1007 I/O port address
+ * @gpio:	GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
+ * @dir:	GPIO_DIR_INPUT or GPIO_DIR_OUTPUT
+ * @pol:	GPIO_POL_NO_INVERT or GPIO_POL_INVERT
+ * @type:	GPIO_TYPE_PUSH_PULL or GPIO_TYPE_OPEN_DRAIN
+ */
+void sio1007_gpio_config(int port, int gpio, int dir, int pol, int type);
+
+/**
+ * Get a GPIO pin value.
+ * This will work whether the GPIO is an input or an output.
+ *
+ * @port:	runtime register block I/O port address
+ * @gpio:	GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
+ * @return:	0 if low, 1 if high, -EINVAL if gpio number is invalid
+ */
+int sio1007_gpio_get_value(int port, int gpio);
+
+/**
+ * Set a GPIO pin value.
+ * This will only work when the GPIO is configured as an output.
+ *
+ * @port:	runtime register block I/O port address
+ * @gpio:	GPIO number (0-7 for GP10-GP17, 8-15 for GP30-GP37)
+ * @val:	0 if low, 1 if high
+ */
+void sio1007_gpio_set_value(int port, int gpio, int val);
+
+#endif /* _SMSC_SIO1007_H_ */
diff --git a/include/sound.h b/include/sound.h
new file mode 100644
index 0000000..47de9fa
--- /dev/null
+++ b/include/sound.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar < rcsekar@samsung.com>
+ */
+
+#ifndef __SOUND_H__
+#define __SOUND_H__
+
+/* sound codec enum */
+enum sound_compat {
+	AUDIO_COMPAT_SPI,
+	AUDIO_COMPAT_I2C,
+};
+
+/* Codec information structure to store the info from device tree */
+struct sound_codec_info {
+	int i2c_bus;
+	int i2c_dev_addr;
+};
+
+/**
+ * struct sound_uc_priv - private uclass information about each sound device
+ *
+ * This is used to line the codec and i2s together
+ *
+ * @codec: Codec that is used for this sound device
+ * @i2s: I2S bus that is used for this sound device
+ * @setup_done: true if setup() has been called
+ */
+struct sound_uc_priv {
+	struct udevice *codec;
+	struct udevice *i2s;
+	int setup_done;
+};
+
+/**
+ * Generates square wave sound data for 1 second
+ *
+ * @sample_rate: Sample rate in Hz
+ * @data: data buffer pointer
+ * @size: size of the buffer in bytes
+ * @freq: frequency of the wave
+ * @channels: Number of channels to use
+ */
+void sound_create_square_wave(uint sample_rate, unsigned short *data, int size,
+			      uint freq, uint channels);
+
+/*
+ * The sound uclass brings together a data transport (currently only I2C) and a
+ * codec (currently connected over I2C).
+ */
+
+/* Operations for sound */
+struct sound_ops {
+	/**
+	 * setup() - Set up to play a sound (optional)
+	 */
+	int (*setup)(struct udevice *dev);
+
+	/**
+	 * play() - Play a beep
+	 *
+	 * @dev: Sound device
+	 * @data: Data buffer to play
+	 * @data_size: Size of data buffer in bytes
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*play)(struct udevice *dev, void *data, uint data_size);
+
+	/**
+	 * start_beep() - Start beeping (optional)
+	 *
+	 * This tells the sound hardware to start a beep. It will continue until
+	 * stopped by sound_stop_beep().
+	 *
+	 * @dev: Sound device
+	 * @frequency_hz: Beep frequency in hertz
+	 * @return if OK, -ENOSYS if not supported, -ve on error
+	 */
+	int (*start_beep)(struct udevice *dev, int frequency_hz);
+
+	/**
+	 * stop_beep() - Stop beeping (optional)
+	 *
+	 * This tells the sound hardware to stop a previously started beep.
+	 *
+	 * @dev: Sound device
+	 * @return if OK, -ve on error
+	 */
+	int (*stop_beep)(struct udevice *dev);
+};
+
+#define sound_get_ops(dev)	((struct sound_ops *)(dev)->driver->ops)
+
+/**
+ * setup() - Set up to play a sound
+ */
+int sound_setup(struct udevice *dev);
+
+/**
+ * play() - Play a beep
+ *
+ * @dev: Sound device
+ * @msecs: Duration of beep in milliseconds
+ * @frequency_hz: Frequency of the beep in Hertz
+ * @return 0 if OK, -ve on error
+ */
+int sound_beep(struct udevice *dev, int msecs, int frequency_hz);
+
+/**
+ * sound_start_beep() - Start beeping
+ *
+ * This tells the sound hardware to start a beep. It will continue until stopped
+ * by sound_stop_beep().
+ *
+ * @dev: Sound device
+ * @frequency_hz: Beep frequency in hertz
+ * @return if OK, -ve on error
+ */
+int sound_start_beep(struct udevice *dev, int frequency_hz);
+
+/**
+ * sound_stop_beep() - Stop beeping
+ *
+ * This tells the sound hardware to stop a previously started beep.
+ *
+ * @dev: Sound device
+ * @return if OK, -ve on error
+ */
+int sound_stop_beep(struct udevice *dev);
+
+/**
+ * sound_find_codec_i2s() - Called by sound drivers to locate codec and i2s
+ *
+ * This finds the audio codec and i2s devices and puts them in the uclass's
+ * private data for this device.
+ */
+int sound_find_codec_i2s(struct udevice *dev);
+
+#endif  /* __SOUND__H__ */
diff --git a/include/sparse_defs.h b/include/sparse_defs.h
new file mode 100644
index 0000000..4bbdffe
--- /dev/null
+++ b/include/sparse_defs.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Broadcom Corporation.
+ */
+
+#include <linux/types.h>
diff --git a/include/sparse_format.h b/include/sparse_format.h
new file mode 100644
index 0000000..bcd3059
--- /dev/null
+++ b/include/sparse_format.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * This is from the Android Project,
+ * Repository: https://android.googlesource.com/platform/system/core
+ * File: libsparse/sparse_format.h
+ * Commit: 28fa5bc347390480fe190294c6c385b6a9f0d68b
+ * Copyright (C) 2010 The Android Open Source Project
+ */
+
+#ifndef _LIBSPARSE_SPARSE_FORMAT_H_
+#define _LIBSPARSE_SPARSE_FORMAT_H_
+#include "sparse_defs.h"
+
+typedef struct sparse_header {
+  __le32	magic;		/* 0xed26ff3a */
+  __le16	major_version;	/* (0x1) - reject images with higher major versions */
+  __le16	minor_version;	/* (0x0) - allow images with higer minor versions */
+  __le16	file_hdr_sz;	/* 28 bytes for first revision of the file format */
+  __le16	chunk_hdr_sz;	/* 12 bytes for first revision of the file format */
+  __le32	blk_sz;		/* block size in bytes, must be a multiple of 4 (4096) */
+  __le32	total_blks;	/* total blocks in the non-sparse output image */
+  __le32	total_chunks;	/* total chunks in the sparse input image */
+  __le32	image_checksum; /* CRC32 checksum of the original data, counting "don't care" */
+				/* as 0. Standard 802.3 polynomial, use a Public Domain */
+				/* table implementation */
+} sparse_header_t;
+
+#define SPARSE_HEADER_MAGIC	0xed26ff3a
+
+#define CHUNK_TYPE_RAW		0xCAC1
+#define CHUNK_TYPE_FILL		0xCAC2
+#define CHUNK_TYPE_DONT_CARE	0xCAC3
+#define CHUNK_TYPE_CRC32    0xCAC4
+
+typedef struct chunk_header {
+  __le16	chunk_type;	/* 0xCAC1 -> raw; 0xCAC2 -> fill; 0xCAC3 -> don't care */
+  __le16	reserved1;
+  __le32	chunk_sz;	/* in blocks in output image */
+  __le32	total_sz;	/* in bytes of chunk input file including chunk header and data */
+} chunk_header_t;
+
+/* Following a Raw or Fill or CRC32 chunk is data.
+ *  For a Raw chunk, it's the data in chunk_sz * blk_sz.
+ *  For a Fill chunk, it's 4 bytes of the fill data.
+ *  For a CRC32 chunk, it's 4 bytes of CRC32
+ */
+
+#endif
diff --git a/include/spartan2.h b/include/spartan2.h
new file mode 100644
index 0000000..618eddd
--- /dev/null
+++ b/include/spartan2.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ */
+
+#ifndef _SPARTAN2_H_
+#define _SPARTAN2_H_
+
+#include <xilinx.h>
+
+/* Slave Parallel Implementation function table */
+typedef struct {
+	xilinx_pre_fn	pre;
+	xilinx_pgm_fn	pgm;
+	xilinx_init_fn	init;
+	xilinx_err_fn	err;
+	xilinx_done_fn	done;
+	xilinx_clk_fn	clk;
+	xilinx_cs_fn	cs;
+	xilinx_wr_fn	wr;
+	xilinx_rdata_fn	rdata;
+	xilinx_wdata_fn	wdata;
+	xilinx_busy_fn	busy;
+	xilinx_abort_fn	abort;
+	xilinx_post_fn	post;
+} xilinx_spartan2_slave_parallel_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	xilinx_pre_fn	pre;
+	xilinx_pgm_fn	pgm;
+	xilinx_clk_fn	clk;
+	xilinx_init_fn	init;
+	xilinx_done_fn	done;
+	xilinx_wr_fn	wr;
+	xilinx_post_fn	post;
+} xilinx_spartan2_slave_serial_fns;
+
+#if defined(CONFIG_FPGA_SPARTAN2)
+extern struct xilinx_fpga_op spartan2_op;
+# define FPGA_SPARTAN2_OPS	&spartan2_op
+#else
+# define FPGA_SPARTAN2_OPS	NULL
+#endif
+
+/* Device Image Sizes
+ *********************************************************************/
+/* Spartan-II (2.5V) */
+#define XILINX_XC2S15_SIZE	197728/8
+#define XILINX_XC2S30_SIZE	336800/8
+#define XILINX_XC2S50_SIZE	559232/8
+#define XILINX_XC2S100_SIZE	781248/8
+#define XILINX_XC2S150_SIZE	1040128/8
+#define XILINX_XC2S200_SIZE	1335872/8
+
+/* Spartan-IIE (1.8V) */
+#define XILINX_XC2S50E_SIZE     630048/8
+#define XILINX_XC2S100E_SIZE    863840/8
+#define XILINX_XC2S150E_SIZE    1134496/8
+#define XILINX_XC2S200E_SIZE    1442016/8
+#define XILINX_XC2S300E_SIZE    1875648/8
+
+/* Descriptor Macros
+ *********************************************************************/
+/* Spartan-II devices */
+#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
+
+#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN2_OPS }
+
+#endif /* _SPARTAN2_H_ */
diff --git a/include/spartan3.h b/include/spartan3.h
new file mode 100644
index 0000000..cf98adc
--- /dev/null
+++ b/include/spartan3.h
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ */
+
+#ifndef _SPARTAN3_H_
+#define _SPARTAN3_H_
+
+#include <xilinx.h>
+
+/* Slave Parallel Implementation function table */
+typedef struct {
+	xilinx_pre_fn	pre;
+	xilinx_pgm_fn	pgm;
+	xilinx_init_fn	init;
+	xilinx_err_fn	err;
+	xilinx_done_fn	done;
+	xilinx_clk_fn	clk;
+	xilinx_cs_fn	cs;
+	xilinx_wr_fn	wr;
+	xilinx_rdata_fn	rdata;
+	xilinx_wdata_fn	wdata;
+	xilinx_busy_fn	busy;
+	xilinx_abort_fn	abort;
+	xilinx_post_fn	post;
+} xilinx_spartan3_slave_parallel_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	xilinx_pre_fn	pre;
+	xilinx_pgm_fn	pgm;
+	xilinx_clk_fn	clk;
+	xilinx_init_fn	init;
+	xilinx_done_fn	done;
+	xilinx_wr_fn	wr;
+	xilinx_post_fn	post;
+	xilinx_bwr_fn	bwr; /* block write function */
+	xilinx_abort_fn abort;
+} xilinx_spartan3_slave_serial_fns;
+
+#if defined(CONFIG_FPGA_SPARTAN3)
+extern struct xilinx_fpga_op spartan3_op;
+# define FPGA_SPARTAN3_OPS	&spartan3_op
+#else
+# define FPGA_SPARTAN3_OPS	NULL
+#endif
+
+/* Device Image Sizes
+ *********************************************************************/
+/* Spartan-III (1.2V) */
+#define XILINX_XC3S50_SIZE	439264/8
+#define XILINX_XC3S200_SIZE	1047616/8
+#define XILINX_XC3S400_SIZE	1699136/8
+#define XILINX_XC3S1000_SIZE	3223488/8
+#define XILINX_XC3S1500_SIZE	5214784/8
+#define XILINX_XC3S2000_SIZE	7673024/8
+#define XILINX_XC3S4000_SIZE	11316864/8
+#define XILINX_XC3S5000_SIZE	13271936/8
+
+/* Spartan-3E (v3.4) */
+#define	XILINX_XC3S100E_SIZE	581344/8
+#define	XILINX_XC3S250E_SIZE	1353728/8
+#define	XILINX_XC3S500E_SIZE	2270208/8
+#define	XILINX_XC3S1200E_SIZE	3841184/8
+#define	XILINX_XC3S1600E_SIZE	5969696/8
+
+/*
+ * Spartan-6 : the Spartan-6 family can be programmed
+ * exactly as the Spartan-3
+ */
+#define XILINK_XC6SLX4_SIZE	(3713568/8)
+
+/* Descriptor Macros
+ *********************************************************************/
+/* Spartan-III devices */
+#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+/* Spartan-3E devices */
+#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, \
+	FPGA_SPARTAN3_OPS }
+
+#endif /* _SPARTAN3_H_ */
diff --git a/include/spd.h b/include/spd.h
new file mode 100644
index 0000000..2bcf46d
--- /dev/null
+++ b/include/spd.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Serial Presence Detect (SPD) EEPROM format according to the
+ * Intel's PC SDRAM Serial Presence Detect (SPD) Specification,
+ * revision 1.2B, November 1999
+ */
+
+#ifndef _SPD_H_
+#define _SPD_H_
+
+typedef struct spd_eeprom_s {
+	unsigned char info_size;   /*  0 # bytes written into serial memory */
+	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
+	unsigned char mem_type;    /*  2 Fundamental memory type */
+	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
+	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
+	unsigned char nrows;       /*  5 # of Module Rows on this assembly */
+	unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
+	unsigned char dataw_msb;   /*  7 ... Data Width continuation */
+	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
+	unsigned char clk_cycle;   /*  9 SDRAM Cycle time at CL=X */
+	unsigned char clk_access;  /* 10 SDRAM Access from Clock at CL=X */
+	unsigned char config;      /* 11 DIMM Configuration type */
+	unsigned char refresh;     /* 12 Refresh Rate/Type */
+	unsigned char primw;       /* 13 Primary SDRAM Width */
+	unsigned char ecw;         /* 14 Error Checking SDRAM width */
+	unsigned char min_delay;   /* 15 for Back to Back Random Address */
+	unsigned char burstl;      /* 16 Burst Lengths Supported */
+	unsigned char nbanks;      /* 17 # of Banks on Each SDRAM Device */
+	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
+	unsigned char cs_lat;      /* 19 CS# Latency */
+	unsigned char write_lat;   /* 20 Write Latency (aka Write Recovery) */
+	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
+	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
+	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time at CL=X-1 */
+	unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
+	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time at CL=X-2 */
+	unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */
+	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
+	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
+	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
+	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
+	unsigned char row_dens;    /* 31 Density of each row on module */
+	unsigned char ca_setup;    /* 32 Cmd + Addr signal input setup time */
+	unsigned char ca_hold;     /* 33 Cmd and Addr signal input hold time */
+	unsigned char data_setup;  /* 34 Data signal input setup time */
+	unsigned char data_hold;   /* 35 Data signal input hold time */
+	unsigned char twr;         /* 36 Write Recovery time tWR */
+	unsigned char twtr;        /* 37 Int write to read delay tWTR */
+	unsigned char trtp;        /* 38 Int read to precharge delay tRTP */
+	unsigned char mem_probe;   /* 39 Mem analysis probe characteristics */
+	unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
+	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
+	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
+	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
+	unsigned char tdqsq;       /* 44 Max DQS to DQ skew */
+	unsigned char tqhs;        /* 45 Max Read DataHold skew tQHS */
+	unsigned char pll_relock;  /* 46 PLL Relock time */
+	unsigned char res[15];     /* 47-xx IDD in SPD and Reserved space */
+	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
+	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
+	unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-108E */
+	unsigned char mloc;        /* 72 Manufacturing Location */
+	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
+	unsigned char rev[2];      /* 91 Revision Code */
+	unsigned char mdate[2];    /* 93 Manufacturing Date */
+	unsigned char sernum[4];   /* 95 Assembly Serial Number */
+	unsigned char mspec[27];   /* 99 Manufacturer Specific Data */
+
+	/*
+	 * Open for Customer Use starting with byte 128.
+	 */
+	unsigned char freq;        /* 128 Intel spec: frequency */
+	unsigned char intel_cas;   /* 129 Intel spec: CAS# Latency support */
+} spd_eeprom_t;
+
+
+/*
+ * Byte 2 Fundamental Memory Types.
+ */
+#define SPD_MEMTYPE_FPM		(0x01)
+#define SPD_MEMTYPE_EDO		(0x02)
+#define SPD_MEMTYPE_PIPE_NIBBLE	(0x03)
+#define SPD_MEMTYPE_SDRAM	(0x04)
+#define SPD_MEMTYPE_ROM		(0x05)
+#define SPD_MEMTYPE_SGRAM	(0x06)
+#define SPD_MEMTYPE_DDR		(0x07)
+#define SPD_MEMTYPE_DDR2	(0x08)
+
+#endif /* _SPD_H_ */
diff --git a/include/spd_sdram.h b/include/spd_sdram.h
new file mode 100644
index 0000000..a2be96c
--- /dev/null
+++ b/include/spd_sdram.h
@@ -0,0 +1,6 @@
+#ifndef _SPD_SDRAM_H_
+#define _SPD_SDRAM_H_
+
+long int spd_sdram(void);
+
+#endif
diff --git a/include/spi-mem.h b/include/spi-mem.h
new file mode 100644
index 0000000..36814ef
--- /dev/null
+++ b/include/spi-mem.h
@@ -0,0 +1,258 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Exceet Electronics GmbH
+ * Copyright (C) 2018 Bootlin
+ *
+ * Author:
+ *	Peter Pan <peterpandong@micron.com>
+ *	Boris Brezillon <boris.brezillon@bootlin.com>
+ */
+
+#ifndef __UBOOT_SPI_MEM_H
+#define __UBOOT_SPI_MEM_H
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <spi.h>
+
+#define SPI_MEM_OP_CMD(__opcode, __buswidth)			\
+	{							\
+		.buswidth = __buswidth,				\
+		.opcode = __opcode,				\
+	}
+
+#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth)		\
+	{							\
+		.nbytes = __nbytes,				\
+		.val = __val,					\
+		.buswidth = __buswidth,				\
+	}
+
+#define SPI_MEM_OP_NO_ADDR	{ }
+
+#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth)			\
+	{							\
+		.nbytes = __nbytes,				\
+		.buswidth = __buswidth,				\
+	}
+
+#define SPI_MEM_OP_NO_DUMMY	{ }
+
+#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth)		\
+	{							\
+		.dir = SPI_MEM_DATA_IN,				\
+		.nbytes = __nbytes,				\
+		.buf.in = __buf,				\
+		.buswidth = __buswidth,				\
+	}
+
+#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth)	\
+	{							\
+		.dir = SPI_MEM_DATA_OUT,			\
+		.nbytes = __nbytes,				\
+		.buf.out = __buf,				\
+		.buswidth = __buswidth,				\
+	}
+
+#define SPI_MEM_OP_NO_DATA	{ }
+
+/**
+ * enum spi_mem_data_dir - describes the direction of a SPI memory data
+ *			   transfer from the controller perspective
+ * @SPI_MEM_DATA_IN: data coming from the SPI memory
+ * @SPI_MEM_DATA_OUT: data sent the SPI memory
+ */
+enum spi_mem_data_dir {
+	SPI_MEM_DATA_IN,
+	SPI_MEM_DATA_OUT,
+};
+
+/**
+ * struct spi_mem_op - describes a SPI memory operation
+ * @cmd.buswidth: number of IO lines used to transmit the command
+ * @cmd.opcode: operation opcode
+ * @addr.nbytes: number of address bytes to send. Can be zero if the operation
+ *		 does not need to send an address
+ * @addr.buswidth: number of IO lines used to transmit the address cycles
+ * @addr.val: address value. This value is always sent MSB first on the bus.
+ *	      Note that only @addr.nbytes are taken into account in this
+ *	      address value, so users should make sure the value fits in the
+ *	      assigned number of bytes.
+ * @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can
+ *		  be zero if the operation does not require dummy bytes
+ * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes
+ * @data.buswidth: number of IO lanes used to send/receive the data
+ * @data.dir: direction of the transfer
+ * @data.buf.in: input buffer
+ * @data.buf.out: output buffer
+ */
+struct spi_mem_op {
+	struct {
+		u8 buswidth;
+		u8 opcode;
+	} cmd;
+
+	struct {
+		u8 nbytes;
+		u8 buswidth;
+		u64 val;
+	} addr;
+
+	struct {
+		u8 nbytes;
+		u8 buswidth;
+	} dummy;
+
+	struct {
+		u8 buswidth;
+		enum spi_mem_data_dir dir;
+		unsigned int nbytes;
+		/* buf.{in,out} must be DMA-able. */
+		union {
+			void *in;
+			const void *out;
+		} buf;
+	} data;
+};
+
+#define SPI_MEM_OP(__cmd, __addr, __dummy, __data)		\
+	{							\
+		.cmd = __cmd,					\
+		.addr = __addr,					\
+		.dummy = __dummy,				\
+		.data = __data,					\
+	}
+
+#ifndef __UBOOT__
+/**
+ * struct spi_mem - describes a SPI memory device
+ * @spi: the underlying SPI device
+ * @drvpriv: spi_mem_driver private data
+ *
+ * Extra information that describe the SPI memory device and may be needed by
+ * the controller to properly handle this device should be placed here.
+ *
+ * One example would be the device size since some controller expose their SPI
+ * mem devices through a io-mapped region.
+ */
+struct spi_mem {
+	struct udevice *dev;
+	void *drvpriv;
+};
+
+/**
+ * struct spi_mem_set_drvdata() - attach driver private data to a SPI mem
+ *				  device
+ * @mem: memory device
+ * @data: data to attach to the memory device
+ */
+static inline void spi_mem_set_drvdata(struct spi_mem *mem, void *data)
+{
+	mem->drvpriv = data;
+}
+
+/**
+ * struct spi_mem_get_drvdata() - get driver private data attached to a SPI mem
+ *				  device
+ * @mem: memory device
+ *
+ * Return: the data attached to the mem device.
+ */
+static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
+{
+	return mem->drvpriv;
+}
+#endif /* __UBOOT__ */
+
+/**
+ * struct spi_controller_mem_ops - SPI memory operations
+ * @adjust_op_size: shrink the data xfer of an operation to match controller's
+ *		    limitations (can be alignment of max RX/TX size
+ *		    limitations)
+ * @supports_op: check if an operation is supported by the controller
+ * @exec_op: execute a SPI memory operation
+ *
+ * This interface should be implemented by SPI controllers providing an
+ * high-level interface to execute SPI memory operation, which is usually the
+ * case for QSPI controllers.
+ */
+struct spi_controller_mem_ops {
+	int (*adjust_op_size)(struct spi_slave *slave, struct spi_mem_op *op);
+	bool (*supports_op)(struct spi_slave *slave,
+			    const struct spi_mem_op *op);
+	int (*exec_op)(struct spi_slave *slave,
+		       const struct spi_mem_op *op);
+};
+
+#ifndef __UBOOT__
+/**
+ * struct spi_mem_driver - SPI memory driver
+ * @spidrv: inherit from a SPI driver
+ * @probe: probe a SPI memory. Usually where detection/initialization takes
+ *	   place
+ * @remove: remove a SPI memory
+ * @shutdown: take appropriate action when the system is shutdown
+ *
+ * This is just a thin wrapper around a spi_driver. The core takes care of
+ * allocating the spi_mem object and forwarding the probe/remove/shutdown
+ * request to the spi_mem_driver. The reason we use this wrapper is because
+ * we might have to stuff more information into the spi_mem struct to let
+ * SPI controllers know more about the SPI memory they interact with, and
+ * having this intermediate layer allows us to do that without adding more
+ * useless fields to the spi_device object.
+ */
+struct spi_mem_driver {
+	struct spi_driver spidrv;
+	int (*probe)(struct spi_mem *mem);
+	int (*remove)(struct spi_mem *mem);
+	void (*shutdown)(struct spi_mem *mem);
+};
+
+#if IS_ENABLED(CONFIG_SPI_MEM)
+int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
+				       const struct spi_mem_op *op,
+				       struct sg_table *sg);
+
+void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
+					  const struct spi_mem_op *op,
+					  struct sg_table *sg);
+#else
+static inline int
+spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
+				   const struct spi_mem_op *op,
+				   struct sg_table *sg)
+{
+	return -ENOTSUPP;
+}
+
+static inline void
+spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
+				     const struct spi_mem_op *op,
+				     struct sg_table *sg)
+{
+}
+#endif /* CONFIG_SPI_MEM */
+#endif /* __UBOOT__ */
+
+int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op);
+
+bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op);
+
+int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op);
+
+#ifndef __UBOOT__
+int spi_mem_driver_register_with_owner(struct spi_mem_driver *drv,
+				       struct module *owner);
+
+void spi_mem_driver_unregister(struct spi_mem_driver *drv);
+
+#define spi_mem_driver_register(__drv)                                  \
+	spi_mem_driver_register_with_owner(__drv, THIS_MODULE)
+
+#define module_spi_mem_driver(__drv)                                    \
+	module_driver(__drv, spi_mem_driver_register,                   \
+		      spi_mem_driver_unregister)
+#endif
+
+#endif /* __LINUX_SPI_MEM_H */
diff --git a/include/spi.h b/include/spi.h
new file mode 100644
index 0000000..5eec0c4
--- /dev/null
+++ b/include/spi.h
@@ -0,0 +1,658 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Common SPI Interface: Controller-specific definitions
+ *
+ * (C) Copyright 2001
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ */
+
+#ifndef _SPI_H_
+#define _SPI_H_
+
+#include <common.h>
+
+/* SPI mode flags */
+#define SPI_CPHA	BIT(0)			/* clock phase */
+#define SPI_CPOL	BIT(1)			/* clock polarity */
+#define SPI_MODE_0	(0|0)			/* (original MicroWire) */
+#define SPI_MODE_1	(0|SPI_CPHA)
+#define SPI_MODE_2	(SPI_CPOL|0)
+#define SPI_MODE_3	(SPI_CPOL|SPI_CPHA)
+#define SPI_CS_HIGH	BIT(2)			/* CS active high */
+#define SPI_LSB_FIRST	BIT(3)			/* per-word bits-on-wire */
+#define SPI_3WIRE	BIT(4)			/* SI/SO signals shared */
+#define SPI_LOOP	BIT(5)			/* loopback mode */
+#define SPI_SLAVE	BIT(6)			/* slave mode */
+#define SPI_PREAMBLE	BIT(7)			/* Skip preamble bytes */
+#define SPI_TX_BYTE	BIT(8)			/* transmit with 1 wire byte */
+#define SPI_TX_DUAL	BIT(9)			/* transmit with 2 wires */
+#define SPI_TX_QUAD	BIT(10)			/* transmit with 4 wires */
+#define SPI_RX_SLOW	BIT(11)			/* receive with 1 wire slow */
+#define SPI_RX_DUAL	BIT(12)			/* receive with 2 wires */
+#define SPI_RX_QUAD	BIT(13)			/* receive with 4 wires */
+
+/* Header byte that marks the start of the message */
+#define SPI_PREAMBLE_END_BYTE	0xec
+
+#define SPI_DEFAULT_WORDLEN	8
+
+#ifdef CONFIG_DM_SPI
+/* TODO(sjg@chromium.org): Remove this and use max_hz from struct spi_slave */
+struct dm_spi_bus {
+	uint max_hz;
+};
+
+/**
+ * struct dm_spi_platdata - platform data for all SPI slaves
+ *
+ * This describes a SPI slave, a child device of the SPI bus. To obtain this
+ * struct from a spi_slave, use dev_get_parent_platdata(dev) or
+ * dev_get_parent_platdata(slave->dev).
+ *
+ * This data is immuatable. Each time the device is probed, @max_hz and @mode
+ * will be copied to struct spi_slave.
+ *
+ * @cs:		Chip select number (0..n-1)
+ * @max_hz:	Maximum bus speed that this slave can tolerate
+ * @mode:	SPI mode to use for this device (see SPI mode flags)
+ */
+struct dm_spi_slave_platdata {
+	unsigned int cs;
+	uint max_hz;
+	uint mode;
+};
+
+#endif /* CONFIG_DM_SPI */
+
+/**
+ * struct spi_slave - Representation of a SPI slave
+ *
+ * For driver model this is the per-child data used by the SPI bus. It can
+ * be accessed using dev_get_parent_priv() on the slave device. The SPI uclass
+ * sets uip per_child_auto_alloc_size to sizeof(struct spi_slave), and the
+ * driver should not override it. Two platform data fields (max_hz and mode)
+ * are copied into this structure to provide an initial value. This allows
+ * them to be changed, since we should never change platform data in drivers.
+ *
+ * If not using driver model, drivers are expected to extend this with
+ * controller-specific data.
+ *
+ * @dev:		SPI slave device
+ * @max_hz:		Maximum speed for this slave
+ * @speed:		Current bus speed. This is 0 until the bus is first
+ *			claimed.
+ * @bus:		ID of the bus that the slave is attached to. For
+ *			driver model this is the sequence number of the SPI
+ *			bus (bus->seq) so does not need to be stored
+ * @cs:			ID of the chip select connected to the slave.
+ * @mode:		SPI mode to use for this slave (see SPI mode flags)
+ * @wordlen:		Size of SPI word in number of bits
+ * @max_read_size:	If non-zero, the maximum number of bytes which can
+ *			be read at once.
+ * @max_write_size:	If non-zero, the maximum number of bytes which can
+ *			be written at once.
+ * @memory_map:		Address of read-only SPI flash access.
+ * @flags:		Indication of SPI flags.
+ */
+struct spi_slave {
+#ifdef CONFIG_DM_SPI
+	struct udevice *dev;	/* struct spi_slave is dev->parentdata */
+	uint max_hz;
+	uint speed;
+#else
+	unsigned int bus;
+	unsigned int cs;
+#endif
+	uint mode;
+	unsigned int wordlen;
+	unsigned int max_read_size;
+	unsigned int max_write_size;
+	void *memory_map;
+
+	u8 flags;
+#define SPI_XFER_BEGIN		BIT(0)	/* Assert CS before transfer */
+#define SPI_XFER_END		BIT(1)	/* Deassert CS after transfer */
+#define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
+#define SPI_XFER_MMAP		BIT(2)	/* Memory Mapped start */
+#define SPI_XFER_MMAP_END	BIT(3)	/* Memory Mapped End */
+};
+
+/**
+ * spi_do_alloc_slave - Allocate a new SPI slave (internal)
+ *
+ * Allocate and zero all fields in the spi slave, and set the bus/chip
+ * select. Use the helper macro spi_alloc_slave() to call this.
+ *
+ * @offset:	Offset of struct spi_slave within slave structure.
+ * @size:	Size of slave structure.
+ * @bus:	Bus ID of the slave chip.
+ * @cs:		Chip select ID of the slave chip on the specified bus.
+ */
+void *spi_do_alloc_slave(int offset, int size, unsigned int bus,
+			 unsigned int cs);
+
+/**
+ * spi_alloc_slave - Allocate a new SPI slave
+ *
+ * Allocate and zero all fields in the spi slave, and set the bus/chip
+ * select.
+ *
+ * @_struct:	Name of structure to allocate (e.g. struct tegra_spi).
+ *		This structure must contain a member 'struct spi_slave *slave'.
+ * @bus:	Bus ID of the slave chip.
+ * @cs:		Chip select ID of the slave chip on the specified bus.
+ */
+#define spi_alloc_slave(_struct, bus, cs) \
+	spi_do_alloc_slave(offsetof(_struct, slave), \
+			    sizeof(_struct), bus, cs)
+
+/**
+ * spi_alloc_slave_base - Allocate a new SPI slave with no private data
+ *
+ * Allocate and zero all fields in the spi slave, and set the bus/chip
+ * select.
+ *
+ * @bus:	Bus ID of the slave chip.
+ * @cs:		Chip select ID of the slave chip on the specified bus.
+ */
+#define spi_alloc_slave_base(bus, cs) \
+	spi_do_alloc_slave(0, sizeof(struct spi_slave), bus, cs)
+
+/**
+ * Set up communications parameters for a SPI slave.
+ *
+ * This must be called once for each slave. Note that this function
+ * usually doesn't touch any actual hardware, it only initializes the
+ * contents of spi_slave so that the hardware can be easily
+ * initialized later.
+ *
+ * @bus:	Bus ID of the slave chip.
+ * @cs:		Chip select ID of the slave chip on the specified bus.
+ * @max_hz:	Maximum SCK rate in Hz.
+ * @mode:	Clock polarity, clock phase and other parameters.
+ *
+ * Returns: A spi_slave reference that can be used in subsequent SPI
+ * calls, or NULL if one or more of the parameters are not supported.
+ */
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode);
+
+/**
+ * Free any memory associated with a SPI slave.
+ *
+ * @slave:	The SPI slave
+ */
+void spi_free_slave(struct spi_slave *slave);
+
+/**
+ * Claim the bus and prepare it for communication with a given slave.
+ *
+ * This must be called before doing any transfers with a SPI slave. It
+ * will enable and initialize any SPI hardware as necessary, and make
+ * sure that the SCK line is in the correct idle state. It is not
+ * allowed to claim the same bus for several slaves without releasing
+ * the bus in between.
+ *
+ * @slave:	The SPI slave
+ *
+ * Returns: 0 if the bus was claimed successfully, or a negative value
+ * if it wasn't.
+ */
+int spi_claim_bus(struct spi_slave *slave);
+
+/**
+ * Release the SPI bus
+ *
+ * This must be called once for every call to spi_claim_bus() after
+ * all transfers have finished. It may disable any SPI hardware as
+ * appropriate.
+ *
+ * @slave:	The SPI slave
+ */
+void spi_release_bus(struct spi_slave *slave);
+
+/**
+ * Set the word length for SPI transactions
+ *
+ * Set the word length (number of bits per word) for SPI transactions.
+ *
+ * @slave:	The SPI slave
+ * @wordlen:	The number of bits in a word
+ *
+ * Returns: 0 on success, -1 on failure.
+ */
+int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen);
+
+/**
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port.  That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter.  Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ *
+ * spi_xfer() interface:
+ * @slave:	The SPI slave which will be sending/receiving the data.
+ * @bitlen:	How many bits to write and read.
+ * @dout:	Pointer to a string of bits to send out.  The bits are
+ *		held in a byte array and are sent MSB first.
+ * @din:	Pointer to a string of bits that will be filled in.
+ * @flags:	A bitwise combination of SPI_XFER_* flags.
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+		void *din, unsigned long flags);
+
+/**
+ * spi_write_then_read - SPI synchronous write followed by read
+ *
+ * This performs a half duplex transaction in which the first transaction
+ * is to send the opcode and if the length of buf is non-zero then it start
+ * the second transaction as tx or rx based on the need from respective slave.
+ *
+ * @slave:	The SPI slave device with which opcode/data will be exchanged
+ * @opcode:	opcode used for specific transfer
+ * @n_opcode:	size of opcode, in bytes
+ * @txbuf:	buffer into which data to be written
+ * @rxbuf:	buffer into which data will be read
+ * @n_buf:	size of buf (whether it's [tx|rx]buf), in bytes
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int spi_write_then_read(struct spi_slave *slave, const u8 *opcode,
+			size_t n_opcode, const u8 *txbuf, u8 *rxbuf,
+			size_t n_buf);
+
+/* Copy memory mapped data */
+void spi_flash_copy_mmap(void *data, void *offset, size_t len);
+
+/**
+ * Determine if a SPI chipselect is valid.
+ * This function is provided by the board if the low-level SPI driver
+ * needs it to determine if a given chipselect is actually valid.
+ *
+ * Returns: 1 if bus:cs identifies a valid chip on this board, 0
+ * otherwise.
+ */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs);
+
+#ifndef CONFIG_DM_SPI
+/**
+ * Activate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should activate the chip select
+ * to the device identified by "slave".
+ */
+void spi_cs_activate(struct spi_slave *slave);
+
+/**
+ * Deactivate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should deactivate the chip
+ * select to the device identified by "slave".
+ */
+void spi_cs_deactivate(struct spi_slave *slave);
+
+/**
+ * Set transfer speed.
+ * This sets a new speed to be applied for next spi_xfer().
+ * @slave:	The SPI slave
+ * @hz:		The transfer speed
+ */
+void spi_set_speed(struct spi_slave *slave, uint hz);
+#endif
+
+/**
+ * Write 8 bits, then read 8 bits.
+ * @slave:	The SPI slave we're communicating with
+ * @byte:	Byte to be written
+ *
+ * Returns: The value that was read, or a negative value on error.
+ *
+ * TODO: This function probably shouldn't be inlined.
+ */
+static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
+{
+	unsigned char dout[2];
+	unsigned char din[2];
+	int ret;
+
+	dout[0] = byte;
+	dout[1] = 0;
+
+	ret = spi_xfer(slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
+	return ret < 0 ? ret : din[1];
+}
+
+#ifdef CONFIG_DM_SPI
+
+/**
+ * struct spi_cs_info - Information about a bus chip select
+ *
+ * @dev:	Connected device, or NULL if none
+ */
+struct spi_cs_info {
+	struct udevice *dev;
+};
+
+/**
+ * struct struct dm_spi_ops - Driver model SPI operations
+ *
+ * The uclass interface is implemented by all SPI devices which use
+ * driver model.
+ */
+struct dm_spi_ops {
+	/**
+	 * Claim the bus and prepare it for communication.
+	 *
+	 * The device provided is the slave device. It's parent controller
+	 * will be used to provide the communication.
+	 *
+	 * This must be called before doing any transfers with a SPI slave. It
+	 * will enable and initialize any SPI hardware as necessary, and make
+	 * sure that the SCK line is in the correct idle state. It is not
+	 * allowed to claim the same bus for several slaves without releasing
+	 * the bus in between.
+	 *
+	 * @dev:	The SPI slave
+	 *
+	 * Returns: 0 if the bus was claimed successfully, or a negative value
+	 * if it wasn't.
+	 */
+	int (*claim_bus)(struct udevice *dev);
+
+	/**
+	 * Release the SPI bus
+	 *
+	 * This must be called once for every call to spi_claim_bus() after
+	 * all transfers have finished. It may disable any SPI hardware as
+	 * appropriate.
+	 *
+	 * @dev:	The SPI slave
+	 */
+	int (*release_bus)(struct udevice *dev);
+
+	/**
+	 * Set the word length for SPI transactions
+	 *
+	 * Set the word length (number of bits per word) for SPI transactions.
+	 *
+	 * @bus:	The SPI slave
+	 * @wordlen:	The number of bits in a word
+	 *
+	 * Returns: 0 on success, -ve on failure.
+	 */
+	int (*set_wordlen)(struct udevice *dev, unsigned int wordlen);
+
+	/**
+	 * SPI transfer
+	 *
+	 * This writes "bitlen" bits out the SPI MOSI port and simultaneously
+	 * clocks "bitlen" bits in the SPI MISO port.  That's just the way SPI
+	 * works.
+	 *
+	 * The source of the outgoing bits is the "dout" parameter and the
+	 * destination of the input bits is the "din" parameter.  Note that
+	 * "dout" and "din" can point to the same memory location, in which
+	 * case the input data overwrites the output data (since both are
+	 * buffered by temporary variables, this is OK).
+	 *
+	 * spi_xfer() interface:
+	 * @dev:	The slave device to communicate with
+	 * @bitlen:	How many bits to write and read.
+	 * @dout:	Pointer to a string of bits to send out.  The bits are
+	 *		held in a byte array and are sent MSB first.
+	 * @din:	Pointer to a string of bits that will be filled in.
+	 * @flags:	A bitwise combination of SPI_XFER_* flags.
+	 *
+	 * Returns: 0 on success, not -1 on failure
+	 */
+	int (*xfer)(struct udevice *dev, unsigned int bitlen, const void *dout,
+		    void *din, unsigned long flags);
+
+	/**
+	 * Optimized handlers for SPI memory-like operations.
+	 *
+	 * Optimized/dedicated operations for interactions with SPI memory. This
+	 * field is optional and should only be implemented if the controller
+	 * has native support for memory like operations.
+	 */
+	const struct spi_controller_mem_ops *mem_ops;
+
+	/**
+	 * Set transfer speed.
+	 * This sets a new speed to be applied for next spi_xfer().
+	 * @bus:	The SPI bus
+	 * @hz:		The transfer speed
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_speed)(struct udevice *bus, uint hz);
+
+	/**
+	 * Set the SPI mode/flags
+	 *
+	 * It is unclear if we want to set speed and mode together instead
+	 * of separately.
+	 *
+	 * @bus:	The SPI bus
+	 * @mode:	Requested SPI mode (SPI_... flags)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_mode)(struct udevice *bus, uint mode);
+
+	/**
+	 * Get information on a chip select
+	 *
+	 * This is only called when the SPI uclass does not know about a
+	 * chip select, i.e. it has no attached device. It gives the driver
+	 * a chance to allow activity on that chip select even so.
+	 *
+	 * @bus:	The SPI bus
+	 * @cs:		The chip select (0..n-1)
+	 * @info:	Returns information about the chip select, if valid.
+	 *		On entry info->dev is NULL
+	 * @return 0 if OK (and @info is set up), -ENODEV if the chip select
+	 *	   is invalid, other -ve value on error
+	 */
+	int (*cs_info)(struct udevice *bus, uint cs, struct spi_cs_info *info);
+};
+
+struct dm_spi_emul_ops {
+	/**
+	 * SPI transfer
+	 *
+	 * This writes "bitlen" bits out the SPI MOSI port and simultaneously
+	 * clocks "bitlen" bits in the SPI MISO port.  That's just the way SPI
+	 * works. Here the device is a slave.
+	 *
+	 * The source of the outgoing bits is the "dout" parameter and the
+	 * destination of the input bits is the "din" parameter.  Note that
+	 * "dout" and "din" can point to the same memory location, in which
+	 * case the input data overwrites the output data (since both are
+	 * buffered by temporary variables, this is OK).
+	 *
+	 * spi_xfer() interface:
+	 * @slave:	The SPI slave which will be sending/receiving the data.
+	 * @bitlen:	How many bits to write and read.
+	 * @dout:	Pointer to a string of bits sent to the device. The
+	 *		bits are held in a byte array and are sent MSB first.
+	 * @din:	Pointer to a string of bits that will be sent back to
+	 *		the master.
+	 * @flags:	A bitwise combination of SPI_XFER_* flags.
+	 *
+	 * Returns: 0 on success, not -1 on failure
+	 */
+	int (*xfer)(struct udevice *slave, unsigned int bitlen,
+		    const void *dout, void *din, unsigned long flags);
+};
+
+/**
+ * spi_find_bus_and_cs() - Find bus and slave devices by number
+ *
+ * Given a bus number and chip select, this finds the corresponding bus
+ * device and slave device. Neither device is activated by this function,
+ * although they may have been activated previously.
+ *
+ * @busnum:	SPI bus number
+ * @cs:		Chip select to look for
+ * @busp:	Returns bus device
+ * @devp:	Return slave device
+ * @return 0 if found, -ENODEV on error
+ */
+int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
+			struct udevice **devp);
+
+/**
+ * spi_get_bus_and_cs() - Find and activate bus and slave devices by number
+ *
+ * Given a bus number and chip select, this finds the corresponding bus
+ * device and slave device.
+ *
+ * If no such slave exists, and drv_name is not NULL, then a new slave device
+ * is automatically bound on this chip select with requested speed and mode.
+ *
+ * Ths new slave device is probed ready for use with the speed and mode
+ * from platdata when available or the requested values.
+ *
+ * @busnum:	SPI bus number
+ * @cs:		Chip select to look for
+ * @speed:	SPI speed to use for this slave when not available in platdata
+ * @mode:	SPI mode to use for this slave when not available in platdata
+ * @drv_name:	Name of driver to attach to this chip select
+ * @dev_name:	Name of the new device thus created
+ * @busp:	Returns bus device
+ * @devp:	Return slave device
+ * @return 0 if found, -ve on error
+ */
+int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode,
+			const char *drv_name, const char *dev_name,
+			struct udevice **busp, struct spi_slave **devp);
+
+/**
+ * spi_chip_select() - Get the chip select for a slave
+ *
+ * @return the chip select this slave is attached to
+ */
+int spi_chip_select(struct udevice *slave);
+
+/**
+ * spi_find_chip_select() - Find the slave attached to chip select
+ *
+ * @bus:	SPI bus to search
+ * @cs:		Chip select to look for
+ * @devp:	Returns the slave device if found
+ * @return 0 if found, -ENODEV on error
+ */
+int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp);
+
+/**
+ * spi_slave_ofdata_to_platdata() - decode standard SPI platform data
+ *
+ * This decodes the speed and mode for a slave from a device tree node
+ *
+ * @blob:	Device tree blob
+ * @node:	Node offset to read from
+ * @plat:	Place to put the decoded information
+ */
+int spi_slave_ofdata_to_platdata(struct udevice *dev,
+				 struct dm_spi_slave_platdata *plat);
+
+/**
+ * spi_cs_info() - Check information on a chip select
+ *
+ * This checks a particular chip select on a bus to see if it has a device
+ * attached, or is even valid.
+ *
+ * @bus:	The SPI bus
+ * @cs:		The chip select (0..n-1)
+ * @info:	Returns information about the chip select, if valid
+ * @return 0 if OK (and @info is set up), -ENODEV if the chip select
+ *	   is invalid, other -ve value on error
+ */
+int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info);
+
+struct sandbox_state;
+
+/**
+ * sandbox_spi_get_emul() - get an emulator for a SPI slave
+ *
+ * This provides a way to attach an emulated SPI device to a particular SPI
+ * slave, so that xfer() operations on the slave will be handled by the
+ * emulator. If a emulator already exists on that chip select it is returned.
+ * Otherwise one is created.
+ *
+ * @state:	Sandbox state
+ * @bus:	SPI bus requesting the emulator
+ * @slave:	SPI slave device requesting the emulator
+ * @emuip:	Returns pointer to emulator
+ * @return 0 if OK, -ve on error
+ */
+int sandbox_spi_get_emul(struct sandbox_state *state,
+			 struct udevice *bus, struct udevice *slave,
+			 struct udevice **emulp);
+
+/**
+ * Claim the bus and prepare it for communication with a given slave.
+ *
+ * This must be called before doing any transfers with a SPI slave. It
+ * will enable and initialize any SPI hardware as necessary, and make
+ * sure that the SCK line is in the correct idle state. It is not
+ * allowed to claim the same bus for several slaves without releasing
+ * the bus in between.
+ *
+ * @dev:	The SPI slave device
+ *
+ * Returns: 0 if the bus was claimed successfully, or a negative value
+ * if it wasn't.
+ */
+int dm_spi_claim_bus(struct udevice *dev);
+
+/**
+ * Release the SPI bus
+ *
+ * This must be called once for every call to dm_spi_claim_bus() after
+ * all transfers have finished. It may disable any SPI hardware as
+ * appropriate.
+ *
+ * @slave:	The SPI slave device
+ */
+void dm_spi_release_bus(struct udevice *dev);
+
+/**
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port.  That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter.  Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ *
+ * dm_spi_xfer() interface:
+ * @dev:	The SPI slave device which will be sending/receiving the data.
+ * @bitlen:	How many bits to write and read.
+ * @dout:	Pointer to a string of bits to send out.  The bits are
+ *		held in a byte array and are sent MSB first.
+ * @din:	Pointer to a string of bits that will be filled in.
+ * @flags:	A bitwise combination of SPI_XFER_* flags.
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int dm_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags);
+
+/* Access the operations for a SPI device */
+#define spi_get_ops(dev)	((struct dm_spi_ops *)(dev)->driver->ops)
+#define spi_emul_get_ops(dev)	((struct dm_spi_emul_ops *)(dev)->driver->ops)
+#endif /* CONFIG_DM_SPI */
+
+#endif	/* _SPI_H_ */
diff --git a/include/spi_flash.h b/include/spi_flash.h
new file mode 100644
index 0000000..55b4721
--- /dev/null
+++ b/include/spi_flash.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Common SPI flash Interface
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ */
+
+#ifndef _SPI_FLASH_H_
+#define _SPI_FLASH_H_
+
+#include <dm.h>	/* Because we dereference struct udevice here */
+#include <linux/types.h>
+#include <linux/mtd/spi-nor.h>
+
+/* by default ENV use the same parameters than SF command */
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS	CONFIG_SF_DEFAULT_BUS
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS	CONFIG_SF_DEFAULT_CS
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+#endif
+#ifndef CONFIG_ENV_SPI_MODE
+# define CONFIG_ENV_SPI_MODE	CONFIG_SF_DEFAULT_MODE
+#endif
+
+struct spi_slave;
+
+struct dm_spi_flash_ops {
+	int (*read)(struct udevice *dev, u32 offset, size_t len, void *buf);
+	int (*write)(struct udevice *dev, u32 offset, size_t len,
+		     const void *buf);
+	int (*erase)(struct udevice *dev, u32 offset, size_t len);
+	/**
+	 * get_sw_write_prot() - Check state of software write-protect feature
+	 *
+	 * SPI flash chips can lock a region of the flash defined by a
+	 * 'protected area'. This function checks if this protected area is
+	 * defined.
+	 *
+	 * @dev:	SPI flash device
+	 * @return 0 if no region is write-protected, 1 if a region is
+	 *	write-protected, -ENOSYS if the driver does not implement this,
+	 *	other -ve value on error
+	 */
+	int (*get_sw_write_prot)(struct udevice *dev);
+};
+
+/* Access the serial operations for a device */
+#define sf_get_ops(dev) ((struct dm_spi_flash_ops *)(dev)->driver->ops)
+
+#ifdef CONFIG_DM_SPI_FLASH
+/**
+ * spi_flash_read_dm() - Read data from SPI flash
+ *
+ * @dev:	SPI flash device
+ * @offset:	Offset into device in bytes to read from
+ * @len:	Number of bytes to read
+ * @buf:	Buffer to put the data that is read
+ * @return 0 if OK, -ve on error
+ */
+int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf);
+
+/**
+ * spi_flash_write_dm() - Write data to SPI flash
+ *
+ * @dev:	SPI flash device
+ * @offset:	Offset into device in bytes to write to
+ * @len:	Number of bytes to write
+ * @buf:	Buffer containing bytes to write
+ * @return 0 if OK, -ve on error
+ */
+int spi_flash_write_dm(struct udevice *dev, u32 offset, size_t len,
+		       const void *buf);
+
+/**
+ * spi_flash_erase_dm() - Erase blocks of the SPI flash
+ *
+ * Note that @len must be a muiltiple of the flash sector size.
+ *
+ * @dev:	SPI flash device
+ * @offset:	Offset into device in bytes to start erasing
+ * @len:	Number of bytes to erase
+ * @return 0 if OK, -ve on error
+ */
+int spi_flash_erase_dm(struct udevice *dev, u32 offset, size_t len);
+
+/**
+ * spl_flash_get_sw_write_prot() - Check state of software write-protect feature
+ *
+ * SPI flash chips can lock a region of the flash defined by a
+ * 'protected area'. This function checks if this protected area is
+ * defined.
+ *
+ * @dev:	SPI flash device
+ * @return 0 if no region is write-protected, 1 if a region is
+ *	write-protected, -ENOSYS if the driver does not implement this,
+ *	other -ve value on error
+ */
+int spl_flash_get_sw_write_prot(struct udevice *dev);
+
+int spi_flash_probe_bus_cs(unsigned int busnum, unsigned int cs,
+			   unsigned int max_hz, unsigned int spi_mode,
+			   struct udevice **devp);
+
+/* Compatibility function - this is the old U-Boot API */
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int spi_mode);
+
+/* Compatibility function - this is the old U-Boot API */
+void spi_flash_free(struct spi_flash *flash);
+
+static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
+				 size_t len, void *buf)
+{
+	return spi_flash_read_dm(flash->dev, offset, len, buf);
+}
+
+static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
+				  size_t len, const void *buf)
+{
+	return spi_flash_write_dm(flash->dev, offset, len, buf);
+}
+
+static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
+				  size_t len)
+{
+	return spi_flash_erase_dm(flash->dev, offset, len);
+}
+
+struct sandbox_state;
+
+int sandbox_sf_bind_emul(struct sandbox_state *state, int busnum, int cs,
+			 struct udevice *bus, ofnode node, const char *spec);
+
+void sandbox_sf_unbind_emul(struct sandbox_state *state, int busnum, int cs);
+
+#else
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int spi_mode);
+
+void spi_flash_free(struct spi_flash *flash);
+
+static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
+		size_t len, void *buf)
+{
+	struct mtd_info *mtd = &flash->mtd;
+	size_t retlen;
+
+	return mtd->_read(mtd, offset, len, &retlen, buf);
+}
+
+static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
+		size_t len, const void *buf)
+{
+	struct mtd_info *mtd = &flash->mtd;
+	size_t retlen;
+
+	return mtd->_write(mtd, offset, len, &retlen, buf);
+}
+
+static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
+		size_t len)
+{
+	struct mtd_info *mtd = &flash->mtd;
+	struct erase_info instr;
+
+	if (offset % mtd->erasesize || len % mtd->erasesize) {
+		printf("SF: Erase offset/length not multiple of erase size\n");
+		return -EINVAL;
+	}
+
+	memset(&instr, 0, sizeof(instr));
+	instr.addr = offset;
+	instr.len = len;
+
+	return mtd->_erase(mtd, &instr);
+}
+#endif
+
+static inline int spi_flash_protect(struct spi_flash *flash, u32 ofs, u32 len,
+					bool prot)
+{
+	if (!flash->flash_lock || !flash->flash_unlock)
+		return -EOPNOTSUPP;
+
+	if (prot)
+		return flash->flash_lock(flash, ofs, len);
+	else
+		return flash->flash_unlock(flash, ofs, len);
+}
+
+#endif /* _SPI_FLASH_H_ */
diff --git a/include/spl.h b/include/spl.h
new file mode 100644
index 0000000..b5387ef
--- /dev/null
+++ b/include/spl.h
@@ -0,0 +1,500 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ */
+#ifndef	_SPL_H_
+#define	_SPL_H_
+
+#include <binman_sym.h>
+
+/* Platform-specific defines */
+#include <linux/compiler.h>
+#include <asm/spl.h>
+#include <handoff.h>
+
+/* Value in r0 indicates we booted from U-Boot */
+#define UBOOT_NOT_LOADED_FROM_SPL	0x13578642
+
+/* Boot type */
+#define MMCSD_MODE_UNDEFINED	0
+#define MMCSD_MODE_RAW		1
+#define MMCSD_MODE_FS		2
+#define MMCSD_MODE_EMMCBOOT	3
+
+/*
+ * u_boot_first_phase() - check if this is the first U-Boot phase
+ *
+ * U-Boot has up to three phases: TPL, SPL and U-Boot proper. Depending on the
+ * build flags we can determine whether the current build is for the first
+ * phase of U-Boot or not. If there is no SPL, then this is U-Boot proper. If
+ * there is SPL but no TPL, the the first phase is SPL. If there is TPL, then
+ * it is the first phase.
+ *
+ * @returns true if this is the first phase of U-Boot
+ *
+ */
+static inline bool u_boot_first_phase(void)
+{
+	if (IS_ENABLED(CONFIG_TPL)) {
+		if (IS_ENABLED(CONFIG_TPL_BUILD))
+			return true;
+	} else if (IS_ENABLED(CONFIG_SPL)) {
+		if (IS_ENABLED(CONFIG_SPL_BUILD))
+			return true;
+	} else {
+		return true;
+	}
+
+	return false;
+}
+
+enum u_boot_phase {
+	PHASE_TPL,	/* Running in TPL */
+	PHASE_SPL,	/* Running in SPL */
+	PHASE_BOARD_F,	/* Running in U-Boot before relocation */
+	PHASE_BOARD_R,	/* Running in U-Boot after relocation */
+};
+
+/**
+ * spl_phase() - Find out the phase of U-Boot
+ *
+ * This can be used to avoid #ifdef logic and use if() instead.
+ *
+ * For example, to include code only in TPL, you might do:
+ *
+ *    #ifdef CONFIG_TPL_BUILD
+ *    ...
+ *    #endif
+ *
+ * but with this you can use:
+ *
+ *    if (spl_phase() == PHASE_TPL) {
+ *       ...
+ *    }
+ *
+ * To include code only in SPL, you might do:
+ *
+ *    #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+ *    ...
+ *    #endif
+ *
+ * but with this you can use:
+ *
+ *    if (spl_phase() == PHASE_SPL) {
+ *       ...
+ *    }
+ *
+ * To include code only in U-Boot proper, you might do:
+ *
+ *    #ifndef CONFIG_SPL_BUILD
+ *    ...
+ *    #endif
+ *
+ * but with this you can use:
+ *
+ *    if (spl_phase() == PHASE_BOARD_F) {
+ *       ...
+ *    }
+ *
+ * @return U-Boot phase
+ */
+static inline enum u_boot_phase spl_phase(void)
+{
+#ifdef CONFIG_TPL_BUILD
+	return PHASE_TPL;
+#elif CONFIG_SPL_BUILD
+	return PHASE_SPL;
+#else
+	DECLARE_GLOBAL_DATA_PTR;
+
+	if (!(gd->flags & GD_FLG_RELOC))
+		return PHASE_BOARD_F;
+	else
+		return PHASE_BOARD_R;
+#endif
+}
+
+/* A string name for SPL or TPL */
+#ifdef CONFIG_SPL_BUILD
+# ifdef CONFIG_TPL_BUILD
+#  define SPL_TPL_NAME	"TPL"
+# else
+#  define SPL_TPL_NAME	"SPL"
+# endif
+# define SPL_TPL_PROMPT	SPL_TPL_NAME ": "
+#else
+# define SPL_TPL_NAME	""
+# define SPL_TPL_PROMPT	""
+#endif
+
+struct spl_image_info {
+	const char *name;
+	u8 os;
+	uintptr_t load_addr;
+	uintptr_t entry_point;
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
+	void *fdt_addr;
+#endif
+	u32 boot_device;
+	u32 size;
+	u32 flags;
+	void *arg;
+#ifdef CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK
+	ulong dcrc_data;
+	ulong dcrc_length;
+	ulong dcrc;
+#endif
+};
+
+/*
+ * Information required to load data from a device
+ *
+ * @dev: Pointer to the device, e.g. struct mmc *
+ * @priv: Private data for the device
+ * @bl_len: Block length for reading in bytes
+ * @filename: Name of the fit image file.
+ * @read: Function to call to read from the device
+ */
+struct spl_load_info {
+	void *dev;
+	void *priv;
+	int bl_len;
+	const char *filename;
+	ulong (*read)(struct spl_load_info *load, ulong sector, ulong count,
+		      void *buf);
+};
+
+/*
+ * We need to know the position of U-Boot in memory so we can jump to it. We
+ * allow any U-Boot binary to be used (u-boot.bin, u-boot-nodtb.bin,
+ * u-boot.img), hence the '_any'. These is no checking here that the correct
+ * image is found. For * example if u-boot.img is used we don't check that
+ * spl_parse_image_header() can parse a valid header.
+ */
+binman_sym_extern(ulong, u_boot_any, image_pos);
+
+/**
+ * spl_load_simple_fit_skip_processing() - Hook to allow skipping the FIT
+ *	image processing during spl_load_simple_fit().
+ *
+ * Return true to skip FIT processing, false to preserve the full code flow
+ * of spl_load_simple_fit().
+ */
+bool spl_load_simple_fit_skip_processing(void);
+
+/**
+ * spl_load_simple_fit() - Loads a fit image from a device.
+ * @spl_image:	Image description to set up
+ * @info:	Structure containing the information required to load data.
+ * @sector:	Sector number where FIT image is located in the device
+ * @fdt:	Pointer to the copied FIT header.
+ *
+ * Reads the FIT image @sector in the device. Loads u-boot image to
+ * specified load address and copies the dtb to end of u-boot image.
+ * Returns 0 on success.
+ */
+int spl_load_simple_fit(struct spl_image_info *spl_image,
+			struct spl_load_info *info, ulong sector, void *fdt);
+
+#define SPL_COPY_PAYLOAD_ONLY	1
+#define SPL_FIT_FOUND		2
+
+/**
+ * spl_load_imx_container() - Loads a imx container image from a device.
+ * @spl_image:	Image description to set up
+ * @info:	Structure containing the information required to load data.
+ * @sector:	Sector number where container image is located in the device
+ *
+ * Reads the container image @sector in the device. Loads u-boot image to
+ * specified load address.
+ */
+int spl_load_imx_container(struct spl_image_info *spl_image,
+			   struct spl_load_info *info, ulong sector);
+
+/* SPL common functions */
+void preloader_console_init(void);
+u32 spl_boot_device(void);
+u32 spl_boot_mode(const u32 boot_device);
+int spl_boot_partition(const u32 boot_device);
+void spl_set_bd(void);
+
+/**
+ * spl_set_header_raw_uboot() - Set up a standard SPL image structure
+ *
+ * This sets up the given spl_image which the standard values obtained from
+ * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START,
+ * CONFIG_SYS_TEXT_BASE.
+ *
+ * @spl_image: Image description to set up
+ */
+void spl_set_header_raw_uboot(struct spl_image_info *spl_image);
+
+/**
+ * spl_parse_image_header() - parse the image header and set up info
+ *
+ * This parses the legacy image header information at @header and sets up
+ * @spl_image according to what is found. If no image header is found, then
+ * a raw image or bootz is assumed. If CONFIG_SPL_PANIC_ON_RAW_IMAGE is
+ * enabled, then this causes a panic. If CONFIG_SPL_RAW_IMAGE_SUPPORT is not
+ * enabled then U-Boot gives up. Otherwise U-Boot sets up the image using
+ * spl_set_header_raw_uboot(), or possibly the bootz header.
+ *
+ * @spl_image: Image description to set up
+ * @header image header to parse
+ * @return 0 if a header was correctly parsed, -ve on error
+ */
+int spl_parse_image_header(struct spl_image_info *spl_image,
+			   const struct image_header *header);
+
+void spl_board_prepare_for_linux(void);
+void spl_board_prepare_for_boot(void);
+int spl_board_ubi_load_image(u32 boot_device);
+
+/**
+ * jump_to_image_linux() - Jump to a Linux kernel from SPL
+ *
+ * This jumps into a Linux kernel using the information in @spl_image.
+ *
+ * @spl_image: Image description to set up
+ */
+void __noreturn jump_to_image_linux(struct spl_image_info *spl_image);
+
+/**
+ * spl_start_uboot() - Check if SPL should start the kernel or U-Boot
+ *
+ * This is called by the various SPL loaders to determine whether the board
+ * wants to load the kernel or U-Boot. This function should be provided by
+ * the board.
+ *
+ * @return 0 if SPL should start the kernel, 1 if U-Boot must be started
+ */
+int spl_start_uboot(void);
+
+/**
+ * spl_display_print() - Display a board-specific message in SPL
+ *
+ * If CONFIG_SPL_DISPLAY_PRINT is enabled, U-Boot will call this function
+ * immediately after displaying the SPL console banner ("U-Boot SPL ...").
+ * This function should be provided by the board.
+ */
+void spl_display_print(void);
+
+/**
+ * struct spl_boot_device - Describes a boot device used by SPL
+ *
+ * @boot_device: A number indicating the BOOT_DEVICE type. There are various
+ * BOOT_DEVICE... #defines and enums in U-Boot and they are not consistently
+ * numbered.
+ * @boot_device_name: Named boot device, or NULL if none.
+ *
+ * Note: Additional fields can be added here, bearing in mind that SPL is
+ * size-sensitive and common fields will be present on all boards. This
+ * struct can also be used to return additional information about the load
+ * process if that becomes useful.
+ */
+struct spl_boot_device {
+	uint boot_device;
+	const char *boot_device_name;
+};
+
+/**
+ * Holds information about a way of loading an SPL image
+ *
+ * @name: User-friendly name for this method (e.g. "MMC")
+ * @boot_device: Boot device that this loader supports
+ * @load_image: Function to call to load image
+ */
+struct spl_image_loader {
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+	const char *name;
+#endif
+	uint boot_device;
+	/**
+	 * load_image() - Load an SPL image
+	 *
+	 * @spl_image: place to put image information
+	 * @bootdev: describes the boot device to load from
+	 */
+	int (*load_image)(struct spl_image_info *spl_image,
+			  struct spl_boot_device *bootdev);
+};
+
+/* Declare an SPL image loader */
+#define SPL_LOAD_IMAGE(__name)					\
+	ll_entry_declare(struct spl_image_loader, __name, spl_image_loader)
+
+/*
+ * _priority is the priority of this method, 0 meaning it will be the top
+ * choice for this device, 9 meaning it is the bottom choice.
+ * _boot_device is the BOOT_DEVICE_... value
+ * _method is the load_image function to call
+ */
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+#define SPL_LOAD_IMAGE_METHOD(_name, _priority, _boot_device, _method) \
+	SPL_LOAD_IMAGE(_method ## _priority ## _boot_device) = { \
+		.name = _name, \
+		.boot_device = _boot_device, \
+		.load_image = _method, \
+	}
+#else
+#define SPL_LOAD_IMAGE_METHOD(_name, _priority, _boot_device, _method) \
+	SPL_LOAD_IMAGE(_method ## _priority ## _boot_device) = { \
+		.boot_device = _boot_device, \
+		.load_image = _method, \
+	}
+#endif
+
+/* SPL FAT image functions */
+int spl_load_image_fat(struct spl_image_info *spl_image,
+		       struct blk_desc *block_dev, int partition,
+		       const char *filename);
+int spl_load_image_fat_os(struct spl_image_info *spl_image,
+			  struct blk_desc *block_dev, int partition);
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image);
+
+/* SPL EXT image functions */
+int spl_load_image_ext(struct spl_image_info *spl_image,
+		       struct blk_desc *block_dev, int partition,
+		       const char *filename);
+int spl_load_image_ext_os(struct spl_image_info *spl_image,
+			  struct blk_desc *block_dev, int partition);
+
+/**
+ * spl_early_init() - Set up device tree and driver model in SPL if enabled
+ *
+ * Call this function in board_init_f() if you want to use device tree and
+ * driver model early, before board_init_r() is called.
+ *
+ * If this is not called, then driver model will be inactive in SPL's
+ * board_init_f(), and no device tree will be available.
+ */
+int spl_early_init(void);
+
+/**
+ * spl_init() - Set up device tree and driver model in SPL if enabled
+ *
+ * You can optionally call spl_early_init(), then optionally call spl_init().
+ * This function will be called from board_init_r() if not called earlier.
+ *
+ * Both spl_early_init() and spl_init() perform a similar function except that
+ * the latter will not set up the malloc() area if
+ * CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is enabled, since it is assumed to
+ * already be done by a calll to spl_relocate_stack_gd() before board_init_r()
+ * is reached.
+ *
+ * This function will be called from board_init_r() if not called earlier.
+ *
+ * If this is not called, then driver model will be inactive in SPL's
+ * board_init_f(), and no device tree will be available.
+ */
+int spl_init(void);
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void);
+#endif
+
+/**
+ * spl_was_boot_source() - check if U-Boot booted from SPL
+ *
+ * This will normally be true, but if U-Boot jumps to second U-Boot, it will
+ * be false. This should be implemented by board-specific code.
+ *
+ * @return true if U-Boot booted from SPL, else false
+ */
+bool spl_was_boot_source(void);
+
+/**
+ * spl_dfu_cmd- run dfu command with chosen mmc device interface
+ * @param usb_index - usb controller number
+ * @param mmc_dev -  mmc device nubmer
+ *
+ * @return 0 on success, otherwise error code
+ */
+int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr);
+
+int spl_mmc_load_image(struct spl_image_info *spl_image,
+		       struct spl_boot_device *bootdev);
+
+/**
+ * spl_mmc_load() - Load an image file from MMC/SD media
+ *
+ * @param spl_image	Image data filled in by loading process
+ * @param bootdev	Describes which device to load from
+ * @param filename	Name of file to load (in FS mode)
+ * @param raw_part	Partition to load from (in RAW mode)
+ * @param raw_sect	Sector to load from (in RAW mode)
+ *
+ * @return 0 on success, otherwise error code
+ */
+int spl_mmc_load(struct spl_image_info *spl_image,
+		 struct spl_boot_device *bootdev,
+		 const char *filename,
+		 int raw_part,
+		 unsigned long raw_sect);
+
+int spl_ymodem_load_image(struct spl_image_info *spl_image,
+			  struct spl_boot_device *bootdev);
+
+/**
+ * spl_invoke_atf - boot using an ARM trusted firmware image
+ */
+void spl_invoke_atf(struct spl_image_info *spl_image);
+
+/**
+ * spl_optee_entry - entry function for optee
+ *
+ * args defind in op-tee project
+ * https://github.com/OP-TEE/optee_os/
+ * core/arch/arm/kernel/generic_entry_a32.S
+ * @arg0: pagestore
+ * @arg1: (ARMv7 standard bootarg #1)
+ * @arg2: device tree address, (ARMv7 standard bootarg #2)
+ * @arg3: non-secure entry address (ARMv7 bootarg #0)
+ */
+void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3);
+
+/**
+ * spl_invoke_opensbi - boot using a RISC-V OpenSBI image
+ */
+void spl_invoke_opensbi(struct spl_image_info *spl_image);
+
+/**
+ * board_return_to_bootrom - allow for boards to continue with the boot ROM
+ *
+ * If a board (e.g. the Rockchip RK3368 boards) provide some
+ * supporting functionality for SPL in their boot ROM and the SPL
+ * stage wants to return to the ROM code to continue booting, boards
+ * can implement 'board_return_to_bootrom'.
+ */
+int board_return_to_bootrom(struct spl_image_info *spl_image,
+			    struct spl_boot_device *bootdev);
+
+/**
+ * board_spl_fit_post_load - allow process images after loading finished
+ *
+ */
+void board_spl_fit_post_load(ulong load_addr, size_t length);
+
+/**
+ * board_spl_fit_size_align - specific size align before processing payload
+ *
+ */
+ulong board_spl_fit_size_align(ulong size);
+
+/**
+ * spl_perform_fixups() - arch/board-specific callback before processing
+ *                        the boot-payload
+ */
+void spl_perform_fixups(struct spl_image_info *spl_image);
+
+/*
+ * spl_get_load_buffer() - get buffer for loading partial image data
+ *
+ * Returns memory area which can be populated by partial image data,
+ * ie. uImage or fitImage header.
+ */
+struct image_header *spl_get_load_buffer(ssize_t offset, size_t size);
+
+#endif
diff --git a/include/spl_gpio.h b/include/spl_gpio.h
new file mode 100644
index 0000000..e410e62
--- /dev/null
+++ b/include/spl_gpio.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Simple GPIO access from SPL. This only supports a single GPIO space,
+ * typically the SoC GPIO banks.
+ *
+ * Copyright 2018 Google LLC
+ */
+
+#ifndef __SPL_GPIO_H
+#define __SPL_GPIO_H
+
+#include <asm/gpio.h>
+
+/*
+ * The functions listed here should be implemented in the SoC GPIO driver.
+ * They correspond to the normal GPIO API (asm-generic/gpio.h). The GPIO
+ * number is encoded in an unsigned int by an SoC-specific means. Pull
+ * values are also SoC-specific.
+ *
+ * This API should only be used in TPL/SPL where GPIO access is needed but
+ * driver model is not available (yet) or adds too much overhead.
+ *
+ * The caller must supply the GPIO register base since this information is
+ * often specific to a particular SoC generation. This allows the GPIO
+ * code to be fairly generic.
+ *
+ * Only a single implementation of each of these functions can be provided.
+ *
+ * The 'gpio' value can include both a bank and a GPIO number, if desired. The
+ * encoding is SoC-specific.
+ */
+
+/**
+ * spl_gpio_set_pull() - Set the pull up/down state of a GPIO
+ *
+ * @regs: Pointer to GPIO registers
+ * @gpio: GPIO to adjust (SoC-specific)
+ * @pull: Pull value (SoC-specific)
+ * @return return 0 if OK, -ve on error
+ */
+int spl_gpio_set_pull(void *regs, uint gpio, int pull);
+
+/**
+ * spl_gpio_output() - Set a GPIO as an output
+ *
+ * @regs: Pointer to GPIO registers
+ * @gpio: GPIO to adjust (SoC-specific)
+ * @value: 0 to set the output low, 1 to set it high
+ * @return return 0 if OK, -ve on error
+ */
+int spl_gpio_output(void *regs, uint gpio, int value);
+
+/**
+ * spl_gpio_input() - Set a GPIO as an input
+ *
+ * @regs: Pointer to GPIO registers
+ * @gpio: GPIO to adjust (SoC-specific)
+ * @return return 0 if OK, -ve on error
+ */
+int spl_gpio_input(void *regs, uint gpio);
+
+#endif /* __SPL_GPIO_H */
diff --git a/include/splash.h b/include/splash.h
new file mode 100644
index 0000000..7fd2de8
--- /dev/null
+++ b/include/splash.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., http://www.fsf.org/about/contact/
+ */
+
+#ifndef _SPLASH_H_
+#define _SPLASH_H_
+
+#include <errno.h>
+
+enum splash_storage {
+	SPLASH_STORAGE_NAND,
+	SPLASH_STORAGE_SF,
+	SPLASH_STORAGE_MMC,
+	SPLASH_STORAGE_USB,
+	SPLASH_STORAGE_SATA,
+};
+
+enum splash_flags {
+	SPLASH_STORAGE_RAW, /* Stored in raw memory */
+	SPLASH_STORAGE_FS,  /* Stored within a file system */
+	SPLASH_STORAGE_FIT, /* Stored inside a FIT image */
+};
+
+struct splash_location {
+	char *name;
+	enum splash_storage storage;
+	enum splash_flags flags;
+	u32 offset;	/* offset from start of storage */
+	char *devpart;  /* Use the load command dev:part conventions */
+	char *mtdpart;	/* MTD partition for ubi part */
+	char *ubivol;	/* UBI volume-name for ubifsmount */
+};
+
+#ifdef CONFIG_SPLASH_SOURCE
+int splash_source_load(struct splash_location *locations, uint size);
+#else
+static inline int splash_source_load(struct splash_location *locations,
+				     uint size)
+{
+	return 0;
+}
+#endif
+
+int splash_screen_prepare(void);
+
+#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+void splash_get_pos(int *x, int *y);
+#else
+static inline void splash_get_pos(int *x, int *y) { }
+#endif
+
+#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP)
+int splash_display(void);
+#else
+static inline int splash_display(void)
+{
+	return -ENOSYS;
+}
+#endif
+
+#define BMP_ALIGN_CENTER	0x7FFF
+
+#endif
diff --git a/include/spmi/spmi.h b/include/spmi/spmi.h
new file mode 100644
index 0000000..3242e6b
--- /dev/null
+++ b/include/spmi/spmi.h
@@ -0,0 +1,46 @@
+#ifndef _SPMI_SPMI_H
+#define _SPMI_SPMI_H
+
+/**
+ * struct dm_spmi_ops - SPMI device I/O interface
+ *
+ * Should be implemented by UCLASS_SPMI device drivers. The standard
+ * device operations provides the I/O interface for it's childs.
+ *
+ * @read:      read register 'reg' of slave 'usid' and peripheral 'pid'
+ * @write:     write register 'reg' of slave 'usid' and peripheral 'pid'
+ *
+ * Each register is 8-bit, both read and write can return negative values
+ * on error.
+ */
+struct dm_spmi_ops {
+	int (*read)(struct udevice *dev, int usid, int pid, int reg);
+	int (*write)(struct udevice *dev, int usid, int pid, int reg,
+		     uint8_t value);
+};
+
+/**
+ * spmi_reg_read() - read a register from specific slave/peripheral
+ *
+ * @dev:	SPMI bus to read
+ * @usid	SlaveID
+ * @pid		Peripheral ID
+ * @reg:	Register to read
+ * @return value read on success or negative value of errno.
+ */
+int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg);
+
+/**
+ * spmi_reg_write() - write a register of specific slave/peripheral
+ *
+ * @dev:	SPMI bus to write
+ * @usid	SlaveID
+ * @pid		Peripheral ID
+ * @reg:	Register to write
+ * @value:	Value to write
+ * @return 0 on success or negative value of errno.
+ */
+int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg,
+		   uint8_t value);
+
+#endif
diff --git a/include/st_logo_data.h b/include/st_logo_data.h
new file mode 100644
index 0000000..d8d1fd3
--- /dev/null
+++ b/include/st_logo_data.h
@@ -0,0 +1,3266 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
+ *	      Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
+ */
+
+/*
+ * file generated from picture
+ * tools/logos/stmicroelectronics_uboot_logo_8bit_rle.bmp
+ */
+
+unsigned char stmicroelectronics_uboot_logo_8bit_rle[] = {
+0x42, 0x4d, 0x5c, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x04,
+0x00, 0x00, 0x6c, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x60, 0x01,
+0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0xe2, 0x93,
+0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x01,
+0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x42, 0x47, 0x52, 0x73, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0xae, 0x82, 0x3a, 0x00, 0xa5, 0x7b,
+0x37, 0x00, 0xfe, 0xfe, 0xfe, 0x00, 0xac, 0x80, 0x39, 0x00, 0x4e, 0x1b,
+0x02, 0x00, 0xb7, 0x88, 0x3b, 0x00, 0x4f, 0x1c, 0x02, 0x00, 0xb3, 0x85,
+0x3a, 0x00, 0xe1, 0xaa, 0x35, 0x00, 0x86, 0x62, 0x1f, 0x00, 0x65, 0x4a,
+0x13, 0x00, 0xa9, 0x7e, 0x38, 0x00, 0xff, 0xfe, 0xff, 0x00, 0x77, 0x55,
+0x13, 0x00, 0xbe, 0x91, 0x47, 0x00, 0xbc, 0x8d, 0x3d, 0x00, 0xfe, 0xfd,
+0xfd, 0x00, 0xa3, 0x7a, 0x38, 0x00, 0xbd, 0x8e, 0x42, 0x00, 0xa7, 0x7d,
+0x39, 0x00, 0x72, 0x52, 0x14, 0x00, 0xbc, 0x8d, 0x40, 0x00, 0x84, 0x60,
+0x1e, 0x00, 0xba, 0x8a, 0x3c, 0x00, 0x75, 0x53, 0x13, 0x00, 0x87, 0x62,
+0x11, 0x00, 0x85, 0x60, 0x10, 0x00, 0x7e, 0x5b, 0x12, 0x00, 0xb4, 0x86,
+0x3a, 0x00, 0x8c, 0x6a, 0x35, 0x00, 0xb1, 0x84, 0x3b, 0x00, 0xaa, 0x7f,
+0x3a, 0x00, 0xbc, 0x8c, 0x3c, 0x00, 0x85, 0x64, 0x34, 0x00, 0xb9, 0x89,
+0x3b, 0x00, 0x93, 0x69, 0x0e, 0x00, 0x8d, 0x65, 0x0e, 0x00, 0xfd, 0xfd,
+0xfc, 0x00, 0xa0, 0x78, 0x37, 0x00, 0x81, 0x5d, 0x12, 0x00, 0x9e, 0x76,
+0x36, 0x00, 0xbe, 0x90, 0x45, 0x00, 0x94, 0x6a, 0x0b, 0x00, 0x8b, 0x64,
+0x10, 0x00, 0x68, 0x4c, 0x14, 0x00, 0x8b, 0x69, 0x35, 0x00, 0x82, 0x5e,
+0x11, 0x00, 0x90, 0x6c, 0x35, 0x00, 0x89, 0x63, 0x0f, 0x00, 0xaf, 0x83,
+0x39, 0x00, 0xa2, 0x75, 0x06, 0x00, 0x96, 0x6b, 0x0d, 0x00, 0x7b, 0x59,
+0x12, 0x00, 0x9c, 0x70, 0x08, 0x00, 0x99, 0x73, 0x37, 0x00, 0xb0, 0x83,
+0x39, 0x00, 0x84, 0x60, 0x11, 0x00, 0x80, 0x5c, 0x14, 0x00, 0x91, 0x68,
+0x0c, 0x00, 0x6a, 0x4d, 0x14, 0x00, 0xc3, 0x99, 0x54, 0x00, 0x92, 0x6e,
+0x36, 0x00, 0x9a, 0x6e, 0x0b, 0x00, 0x8a, 0x68, 0x34, 0x00, 0xc0, 0x94,
+0x4b, 0x00, 0x98, 0x6c, 0x09, 0x00, 0x8f, 0x67, 0x0f, 0x00, 0x82, 0x62,
+0x34, 0x00, 0x7d, 0x5a, 0x15, 0x00, 0xc5, 0x9f, 0x5f, 0x00, 0xbb, 0x8b,
+0x3b, 0x00, 0xc8, 0xa7, 0x6a, 0x00, 0xc0, 0x95, 0x4e, 0x00, 0x87, 0x66,
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+0xff, 0x00, 0x1a, 0x00, 0x01, 0x0d, 0x2a, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x00, 0xff, 0x00, 0xe1, 0x00, 0x00, 0x00, 0xff, 0x00,
+0xe1, 0x00, 0x00, 0x01
+};
+
diff --git a/include/status_led.h b/include/status_led.h
new file mode 100644
index 0000000..5b35701
--- /dev/null
+++ b/include/status_led.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+/*
+ * The purpose of this code is to signal the operational status of a
+ * target which usually boots over the network; while running in
+ * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
+ * message has been received, the LED is turned off. The Linux
+ * kernel, once it is running, will start blinking the LED again,
+ * with another frequency.
+ */
+
+#ifndef _STATUS_LED_H_
+#define	_STATUS_LED_H_
+
+#ifdef CONFIG_LED_STATUS
+
+#define LED_STATUS_PERIOD	(CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ)
+#ifdef CONFIG_LED_STATUS1
+#define LED_STATUS_PERIOD1	(CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ1)
+#endif /* CONFIG_LED_STATUS1 */
+#ifdef CONFIG_LED_STATUS2
+#define LED_STATUS_PERIOD2	(CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ2)
+#endif /* CONFIG_LED_STATUS2 */
+#ifdef CONFIG_LED_STATUS3
+#define LED_STATUS_PERIOD3	(CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ3)
+#endif /* CONFIG_LED_STATUS3 */
+#ifdef CONFIG_LED_STATUS4
+#define LED_STATUS_PERIOD4	(CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ4)
+#endif /* CONFIG_LED_STATUS4 */
+#ifdef CONFIG_LED_STATUS5
+#define LED_STATUS_PERIOD5	(CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ5)
+#endif /* CONFIG_LED_STATUS5 */
+
+void status_led_init(void);
+void status_led_tick (unsigned long timestamp);
+void status_led_set  (int led, int state);
+
+/*****  MVS v1  **********************************************************/
+#if (defined(CONFIG_MVS) && CONFIG_MVS < 2)
+# define STATUS_LED_PAR		im_ioport.iop_pdpar
+# define STATUS_LED_DIR		im_ioport.iop_pddir
+# undef  STATUS_LED_ODR
+# define STATUS_LED_DAT		im_ioport.iop_pddat
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+/*****  Someone else defines these  *************************************/
+#elif defined(STATUS_LED_PAR)
+  /*
+   * ADVICE: Define in your board configuration file rather than
+   * filling this file up with lots of custom board stuff.
+   */
+
+#elif defined(CONFIG_LED_STATUS_BOARD_SPECIFIC)
+/* led_id_t is unsigned long mask */
+typedef unsigned long led_id_t;
+
+extern void __led_toggle (led_id_t mask);
+extern void __led_init (led_id_t mask, int state);
+extern void __led_set (led_id_t mask, int state);
+void __led_blink(led_id_t mask, int freq);
+#else
+# error Status LED configuration missing
+#endif
+/************************************************************************/
+
+#ifndef CONFIG_LED_STATUS_BOARD_SPECIFIC
+# include <asm/status_led.h>
+#endif
+
+#endif	/* CONFIG_LED_STATUS	*/
+
+/*
+ * Coloured LEDs API
+ */
+#ifndef	__ASSEMBLY__
+void coloured_LED_init(void);
+void red_led_on(void);
+void red_led_off(void);
+void green_led_on(void);
+void green_led_off(void);
+void yellow_led_on(void);
+void yellow_led_off(void);
+void blue_led_on(void);
+void blue_led_off(void);
+#else
+	.extern LED_init
+	.extern red_led_on
+	.extern red_led_off
+	.extern yellow_led_on
+	.extern yellow_led_off
+	.extern green_led_on
+	.extern green_led_off
+	.extern blue_led_on
+	.extern blue_led_off
+#endif
+
+#endif	/* _STATUS_LED_H_	*/
diff --git a/include/stdint.h b/include/stdint.h
new file mode 100644
index 0000000..2e126d1
--- /dev/null
+++ b/include/stdint.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Dummy file to allow libraries linked with U-Boot to include stdint.h without
+ * getting the system version.
+ *
+ * U-Boot uses linux types (linux/types.h) so does not make use of stdint.h
+ */
diff --git a/include/stdio.h b/include/stdio.h
new file mode 100644
index 0000000..a18aab0
--- /dev/null
+++ b/include/stdio.h
@@ -0,0 +1,54 @@
+#ifndef __STDIO_H
+#define __STDIO_H
+
+#include <stdarg.h>
+#include <linux/compiler.h>
+
+/* stdin */
+int getc(void);
+int tstc(void);
+
+/* stdout */
+#if !defined(CONFIG_SPL_BUILD) || \
+	(defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_SERIAL_SUPPORT)) || \
+	(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) && \
+		defined(CONFIG_SPL_SERIAL_SUPPORT))
+void putc(const char c);
+void puts(const char *s);
+int __printf(1, 2) printf(const char *fmt, ...);
+int vprintf(const char *fmt, va_list args);
+#else
+static inline void putc(const char c)
+{
+}
+
+static inline void puts(const char *s)
+{
+}
+
+static inline int __printf(1, 2) printf(const char *fmt, ...)
+{
+	return 0;
+}
+
+static inline int vprintf(const char *fmt, va_list args)
+{
+	return 0;
+}
+#endif
+
+/*
+ * FILE based functions (can only be used AFTER relocation!)
+ */
+#define stdin		0
+#define stdout		1
+#define stderr		2
+#define MAX_FILES	3
+
+int __printf(2, 3) fprintf(int file, const char *fmt, ...);
+void fputs(int file, const char *s);
+void fputc(int file, const char c);
+int ftstc(int file);
+int fgetc(int file);
+
+#endif /* __STDIO_H */
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
new file mode 100644
index 0000000..cd0cd60
--- /dev/null
+++ b/include/stdio_dev.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ */
+
+#ifndef _STDIO_DEV_H_
+#define _STDIO_DEV_H_
+
+#include <stdio.h>
+#include <linux/list.h>
+
+/*
+ * STDIO DEVICES
+ */
+
+#define DEV_FLAGS_INPUT	 0x00000001	/* Device can be used as input	console */
+#define DEV_FLAGS_OUTPUT 0x00000002	/* Device can be used as output console */
+#define DEV_FLAGS_DM     0x00000004	/* Device priv is a struct udevice * */
+
+/* Device information */
+struct stdio_dev {
+	int	flags;			/* Device flags: input/output/system	*/
+	int	ext;			/* Supported extensions			*/
+	char	name[32];		/* Device name				*/
+
+/* GENERAL functions */
+
+	int (*start)(struct stdio_dev *dev);	/* To start the device */
+	int (*stop)(struct stdio_dev *dev);	/* To stop the device */
+
+/* OUTPUT functions */
+
+	/* To put a char */
+	void (*putc)(struct stdio_dev *dev, const char c);
+	/* To put a string (accelerator) */
+	void (*puts)(struct stdio_dev *dev, const char *s);
+
+/* INPUT functions */
+
+	/* To test if a char is ready... */
+	int (*tstc)(struct stdio_dev *dev);
+	int (*getc)(struct stdio_dev *dev);	/* To get that char */
+
+/* Other functions */
+
+	void *priv;			/* Private extensions			*/
+	struct list_head list;
+};
+
+/*
+ * VARIABLES
+ */
+extern struct stdio_dev *stdio_devices[];
+extern char *stdio_names[MAX_FILES];
+
+/*
+ * PROTOTYPES
+ */
+int	stdio_register (struct stdio_dev * dev);
+int stdio_register_dev(struct stdio_dev *dev, struct stdio_dev **devp);
+
+/**
+ * stdio_init_tables() - set up stdio tables ready for devices
+ *
+ * This does not add any devices, but just prepares stdio for use.
+ */
+int stdio_init_tables(void);
+
+/**
+ * stdio_add_devices() - Add stdio devices to the table
+ *
+ * This makes calls to all the various subsystems that use stdio, to make
+ * them register with stdio.
+ */
+int stdio_add_devices(void);
+
+/**
+ * stdio_init() - Sets up stdio ready for use
+ *
+ * This calls stdio_init_tables() and stdio_add_devices()
+ */
+int stdio_init(void);
+
+void	stdio_print_current_devices(void);
+#if CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER)
+int stdio_deregister(const char *devname, int force);
+int stdio_deregister_dev(struct stdio_dev *dev, int force);
+#endif
+struct list_head* stdio_get_list(void);
+struct stdio_dev* stdio_get_by_name(const char* name);
+struct stdio_dev* stdio_clone(struct stdio_dev *dev);
+
+#ifdef CONFIG_LCD
+int	drv_lcd_init (void);
+#endif
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+int	drv_video_init (void);
+#endif
+#ifdef CONFIG_KEYBOARD
+int	drv_keyboard_init (void);
+#endif
+#ifdef CONFIG_USB_TTY
+int	drv_usbtty_init (void);
+#endif
+#ifdef CONFIG_NETCONSOLE
+int	drv_nc_init (void);
+#endif
+#ifdef CONFIG_JTAG_CONSOLE
+int drv_jtag_console_init (void);
+#endif
+#ifdef CONFIG_CBMEM_CONSOLE
+int cbmemc_init(void);
+#endif
+
+#endif
diff --git a/include/stdlib.h b/include/stdlib.h
new file mode 100644
index 0000000..9c175d4
--- /dev/null
+++ b/include/stdlib.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2013 Google Inc.
+ */
+
+#ifndef __STDLIB_H_
+#define __STDLIB_H_
+
+#include <malloc.h>
+
+#endif /* __STDLIB_H_ */
diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h
new file mode 100644
index 0000000..a09a09f
--- /dev/null
+++ b/include/stm32_rcc.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ */
+
+#ifndef __STM32_RCC_H_
+#define __STM32_RCC_H_
+
+#define AHB_PSC_1			0
+#define AHB_PSC_2			0x8
+#define AHB_PSC_4			0x9
+#define AHB_PSC_8			0xA
+#define AHB_PSC_16			0xB
+#define AHB_PSC_64			0xC
+#define AHB_PSC_128			0xD
+#define AHB_PSC_256			0xE
+#define AHB_PSC_512			0xF
+
+#define APB_PSC_1			0
+#define APB_PSC_2			0x4
+#define APB_PSC_4			0x5
+#define APB_PSC_8			0x6
+#define APB_PSC_16			0x7
+
+struct pll_psc {
+	u8	pll_m;
+	u16	pll_n;
+	u8	pll_p;
+	u8	pll_q;
+	u8	ahb_psc;
+	u8	apb1_psc;
+	u8	apb2_psc;
+};
+
+struct stm32_clk_info {
+	struct pll_psc sys_pll_psc;
+	bool has_overdrive;
+	bool v2;
+};
+
+enum soc_family {
+	STM32F42X,
+	STM32F469,
+	STM32F7,
+	STM32MP1,
+};
+
+enum apb {
+	APB1,
+	APB2,
+};
+
+struct stm32_rcc_clk {
+	char *drv_name;
+	enum soc_family soc;
+};
+
+struct stm32_rcc_regs {
+	u32 cr;		/* RCC clock control */
+	u32 pllcfgr;	/* RCC PLL configuration */
+	u32 cfgr;	/* RCC clock configuration */
+	u32 cir;	/* RCC clock interrupt */
+	u32 ahb1rstr;	/* RCC AHB1 peripheral reset */
+	u32 ahb2rstr;	/* RCC AHB2 peripheral reset */
+	u32 ahb3rstr;	/* RCC AHB3 peripheral reset */
+	u32 rsv0;
+	u32 apb1rstr;	/* RCC APB1 peripheral reset */
+	u32 apb2rstr;	/* RCC APB2 peripheral reset */
+	u32 rsv1[2];
+	u32 ahb1enr;	/* RCC AHB1 peripheral clock enable */
+	u32 ahb2enr;	/* RCC AHB2 peripheral clock enable */
+	u32 ahb3enr;	/* RCC AHB3 peripheral clock enable */
+	u32 rsv2;
+	u32 apb1enr;	/* RCC APB1 peripheral clock enable */
+	u32 apb2enr;	/* RCC APB2 peripheral clock enable */
+	u32 rsv3[2];
+	u32 ahb1lpenr;	/* RCC AHB1 periph clk enable in low pwr mode */
+	u32 ahb2lpenr;	/* RCC AHB2 periph clk enable in low pwr mode */
+	u32 ahb3lpenr;	/* RCC AHB3 periph clk enable in low pwr mode */
+	u32 rsv4;
+	u32 apb1lpenr;	/* RCC APB1 periph clk enable in low pwr mode */
+	u32 apb2lpenr;	/* RCC APB2 periph clk enable in low pwr mode */
+	u32 rsv5[2];
+	u32 bdcr;	/* RCC Backup domain control */
+	u32 csr;	/* RCC clock control & status */
+	u32 rsv6[2];
+	u32 sscgr;	/* RCC spread spectrum clock generation */
+	u32 plli2scfgr;	/* RCC PLLI2S configuration */
+	/* below registers are only available on STM32F46x and STM32F7 SoCs*/
+	u32 pllsaicfgr;	/* PLLSAI configuration */
+	u32 dckcfgr;	/* dedicated clocks configuration register */
+	/* Below registers are only available on STM32F7 SoCs */
+	u32 dckcfgr2;	/* dedicated clocks configuration register */
+};
+
+#endif /* __STM32_RCC_H_ */
diff --git a/include/stratixII.h b/include/stratixII.h
new file mode 100644
index 0000000..3c06bb2
--- /dev/null
+++ b/include/stratixII.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007
+ * Eran Liberty, Extricom, eran.liberty@gmail.com
+ */
+#ifndef _STRATIXII_H_
+#define _STRATIXII_H_
+
+extern int StratixII_load (Altera_desc * desc, void *image, size_t size);
+extern int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize);
+extern int StratixII_info (Altera_desc * desc);
+
+#endif				/* _STRATIXII_H_ */
diff --git a/include/string.h b/include/string.h
new file mode 100644
index 0000000..38134dc
--- /dev/null
+++ b/include/string.h
@@ -0,0 +1 @@
+#include <linux/string.h>
diff --git a/include/sy8106a.h b/include/sy8106a.h
new file mode 100644
index 0000000..36bfdbd
--- /dev/null
+++ b/include/sy8106a.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016
+ * Jelle van der Waa <jelle@vdwaa.nl>
+ */
+#ifndef _SY8106A_PMIC_H_
+
+int sy8106a_set_vout1(unsigned int mvolt);
+
+#endif
diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h
new file mode 100644
index 0000000..7628c33
--- /dev/null
+++ b/include/sym53c8xx.h
@@ -0,0 +1,552 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * Most of these definitions are derived from
+ * linux/drivers/scsi/sym53c8xx_defs.h
+ */
+
+#ifndef _SYM53C8XX_DEFS_H
+#define _SYM53C8XX_DEFS_H
+
+
+#define SCNTL0		0x00    /* full arb., ena parity, par->ATN  */
+
+#define SCNTL1		0x01    /* no reset                         */
+  #define   ISCON   0x10  /* connected to scsi						*/
+  #define   CRST    0x08  /* force reset                      */
+  #define   IARB    0x02  /* immediate arbitration            */
+
+#define SCNTL2		0x02    /* no disconnect expected           */
+	#define   SDU     0x80  /* cmd: disconnect will raise error */
+	#define   CHM     0x40  /* sta: chained mode                */
+	#define   WSS     0x08  /* sta: wide scsi send           [W]*/
+	#define   WSR     0x01  /* sta: wide scsi received       [W]*/
+
+#define SCNTL3		0x03    /* cnf system clock dependent       */
+	#define   EWS     0x08  /* cmd: enable wide scsi         [W]*/
+	#define   ULTRA   0x80  /* cmd: ULTRA enable                */
+				/* bits 0-2, 7 rsvd for C1010       */
+
+#define SCID			0x04		/* cnf host adapter scsi address    */
+	#define   RRE     0x40  /* r/w:e enable response to resel.  */
+	#define   SRE     0x20  /* r/w:e enable response to select  */
+
+#define SXFER			0x05		/* ### Sync speed and count         */
+				/* bits 6-7 rsvd for C1010          */
+
+#define SDID			0x06	/* ### Destination-ID               */
+
+#define GPREG			0x07	/* ??? IO-Pins                      */
+
+#define SFBR			0x08	/* ### First byte in phase          */
+
+#define SOCL			0x09
+	#define   CREQ	  0x80	/* r/w: SCSI-REQ                    */
+	#define   CACK	  0x40	/* r/w: SCSI-ACK                    */
+	#define   CBSY	  0x20	/* r/w: SCSI-BSY                    */
+	#define   CSEL	  0x10	/* r/w: SCSI-SEL                    */
+	#define   CATN	  0x08	/* r/w: SCSI-ATN                    */
+	#define   CMSG	  0x04	/* r/w: SCSI-MSG                    */
+	#define   CC_D	  0x02	/* r/w: SCSI-C_D                    */
+	#define   CI_O	  0x01	/* r/w: SCSI-I_O                    */
+
+#define SSID			0x0a
+
+#define SBCL			0x0b
+
+#define DSTAT			0x0c
+  #define   DFE     0x80  /* sta: dma fifo empty              */
+  #define   MDPE    0x40  /* int: master data parity error    */
+  #define   BF      0x20  /* int: script: bus fault           */
+  #define   ABRT    0x10  /* int: script: command aborted     */
+  #define   SSI     0x08  /* int: script: single step         */
+  #define   SIR     0x04  /* int: script: interrupt instruct. */
+  #define   IID     0x01  /* int: script: illegal instruct.   */
+
+#define SSTAT0		0x0d
+  #define   ILF     0x80  /* sta: data in SIDL register lsb   */
+  #define   ORF     0x40  /* sta: data in SODR register lsb   */
+  #define   OLF     0x20  /* sta: data in SODL register lsb   */
+  #define   AIP     0x10  /* sta: arbitration in progress     */
+  #define   LOA     0x08  /* sta: arbitration lost            */
+  #define   WOA     0x04  /* sta: arbitration won             */
+  #define   IRST    0x02  /* sta: scsi reset signal           */
+  #define   SDP     0x01  /* sta: scsi parity signal          */
+
+#define SSTAT1		0x0e
+	#define   FF3210  0xf0	/* sta: bytes in the scsi fifo      */
+
+#define SSTAT2		0x0f
+  #define   ILF1    0x80  /* sta: data in SIDL register msb[W]*/
+  #define   ORF1    0x40  /* sta: data in SODR register msb[W]*/
+  #define   OLF1    0x20  /* sta: data in SODL register msb[W]*/
+  #define   DM      0x04  /* sta: DIFFSENS mismatch (895/6 only) */
+  #define   LDSC    0x02  /* sta: disconnect & reconnect      */
+
+#define DSA				0x10		/* --> Base page                    */
+#define DSA1			0x11
+#define DSA2			0x12
+#define DSA3			0x13
+
+#define ISTAT			0x14	/* --> Main Command and status      */
+  #define   CABRT   0x80  /* cmd: abort current operation     */
+  #define   SRST    0x40  /* mod: reset chip                  */
+  #define   SIGP    0x20  /* r/w: message from host to ncr    */
+  #define   SEM     0x10  /* r/w: message between host + ncr  */
+  #define   CON     0x08  /* sta: connected to scsi           */
+  #define   INTF    0x04  /* sta: int on the fly (reset by wr)*/
+  #define   SIP     0x02  /* sta: scsi-interrupt              */
+  #define   DIP     0x01  /* sta: host/script interrupt       */
+
+
+#define CTEST0		0x18
+#define CTEST1		0x19
+#define CTEST2		0x1a
+	#define   CSIGP   0x40
+				/* bits 0-2,7 rsvd for C1010        */
+
+#define CTEST3		0x1b
+	#define   FLF     0x08  /* cmd: flush dma fifo              */
+	#define   CLF		0x04	/* cmd: clear dma fifo		    */
+	#define   FM      0x02  /* mod: fetch pin mode              */
+	#define   WRIE    0x01  /* mod: write and invalidate enable */
+				/* bits 4-7 rsvd for C1010          */
+
+#define DFIFO			0x20
+#define CTEST4		0x21
+	#define   BDIS    0x80  /* mod: burst disable               */
+	#define   MPEE    0x08  /* mod: master parity error enable  */
+
+#define CTEST5		0x22
+	#define   DFS     0x20  /* mod: dma fifo size               */
+				/* bits 0-1, 3-7 rsvd for C1010          */
+#define CTEST6		0x23
+
+#define DBC				0x24	/* ### Byte count and command       */
+#define DNAD			0x28	/* ### Next command register        */
+#define DSP				0x2c	/* --> Script Pointer               */
+#define DSPS			0x30	/* --> Script pointer save/opcode#2 */
+
+#define SCRATCHA	0x34  /* Temporary register a            */
+#define SCRATCHA1	0x35
+#define SCRATCHA2	0x36
+#define SCRATCHA3	0x37
+
+#define DMODE			0x38
+	#define   BL_2    0x80  /* mod: burst length shift value +2 */
+	#define   BL_1    0x40  /* mod: burst length shift value +1 */
+	#define   ERL     0x08  /* mod: enable read line            */
+	#define   ERMP    0x04  /* mod: enable read multiple        */
+	#define   BOF     0x02  /* mod: burst op code fetch         */
+	#define   MAN     0x01  /* mod: manual start				         */
+
+#define DIEN		0x39
+#define SBR			0x3a
+
+#define DCNTL		0x3b			/* --> Script execution control     */
+	#define   CLSE    0x80  /* mod: cache line size enable      */
+	#define   PFF     0x40  /* cmd: pre-fetch flush             */
+	#define   PFEN    0x20  /* mod: pre-fetch enable            */
+	#define   SSM     0x10  /* mod: single step mode            */
+	#define   IRQM    0x08  /* mod: irq mode (1 = totem pole !) */
+	#define   STD     0x04  /* cmd: start dma mode              */
+	#define   IRQD    0x02  /* mod: irq disable                 */
+	#define	  NOCOM   0x01	/* cmd: protect sfbr while reselect */
+				/* bits 0-1 rsvd for C1010          */
+
+#define ADDER			0x3c
+
+#define SIEN			0x40	/* -->: interrupt enable            */
+#define SIST			0x42	/* <--: interrupt status            */
+  #define   SBMC    0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
+  #define   STO     0x0400/* sta: timeout (select)            */
+  #define   GEN     0x0200/* sta: timeout (general)           */
+  #define   HTH     0x0100/* sta: timeout (handshake)         */
+  #define   MA      0x80  /* sta: phase mismatch              */
+  #define   CMP     0x40  /* sta: arbitration complete        */
+  #define   SEL     0x20  /* sta: selected by another device  */
+  #define   RSL     0x10  /* sta: reselected by another device*/
+  #define   SGE     0x08  /* sta: gross error (over/underflow)*/
+  #define   UDC     0x04  /* sta: unexpected disconnect       */
+  #define   RST     0x02  /* sta: scsi bus reset detected     */
+  #define   PAR     0x01  /* sta: scsi parity error           */
+
+#define SLPAR				0x44
+#define SWIDE				0x45
+#define MACNTL			0x46
+#define GPCNTL			0x47
+#define STIME0			0x48    /* cmd: timeout for select&handshake*/
+#define STIME1			0x49    /* cmd: timeout user defined        */
+#define RESPID			0x4a    /* sta: Reselect-IDs                */
+
+#define STEST0			0x4c
+
+#define STEST1			0x4d
+	#define   SCLK    0x80	/* Use the PCI clock as SCSI clock	*/
+	#define   DBLEN   0x08	/* clock doubler running		*/
+	#define   DBLSEL  0x04	/* clock doubler selected		*/
+
+
+#define STEST2			0x4e
+	#define   ROF     0x40	/* reset scsi offset (after gross error!) */
+	#define   EXT     0x02  /* extended filtering                     */
+
+#define STEST3			0x4f
+	#define   TE     0x80	/* c: tolerAnt enable */
+	#define   HSC    0x20	/* c: Halt SCSI Clock */
+	#define   CSF    0x02	/* c: clear scsi fifo */
+
+#define SIDL			0x50	/* Lowlevel: latched from scsi data */
+#define STEST4		0x52
+	#define SMODE	0xc0	/* SCSI bus mode      (895/6 only) */
+	#define SMODE_HVD 0x40	/* High Voltage Differential       */
+	#define SMODE_SE  0x80	/* Single Ended                    */
+	#define SMODE_LVD 0xc0	/* Low Voltage Differential        */
+	#define LCKFRQ 0x20	/* Frequency Lock (895/6 only)     */
+				/* bits 0-5 rsvd for C1010          */
+
+#define SODL			0x54	/* Lowlevel: data out to scsi data  */
+
+#define SBDL			0x58	/* Lowlevel: data from scsi data    */
+
+
+/*-----------------------------------------------------------
+**
+**	Utility macros for the script.
+**
+**-----------------------------------------------------------
+*/
+
+#define REG(r) (r)
+
+/*-----------------------------------------------------------
+**
+**	SCSI phases
+**
+**	DT phases illegal for ncr driver.
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_DATA_OUT	0x00000000
+#define	SCR_DATA_IN	0x01000000
+#define	SCR_COMMAND	0x02000000
+#define	SCR_STATUS	0x03000000
+#define SCR_DT_DATA_OUT	0x04000000
+#define SCR_DT_DATA_IN	0x05000000
+#define SCR_MSG_OUT	0x06000000
+#define SCR_MSG_IN      0x07000000
+
+#define SCR_ILG_OUT	0x04000000
+#define SCR_ILG_IN	0x05000000
+
+/*-----------------------------------------------------------
+**
+**	Data transfer via SCSI.
+**
+**-----------------------------------------------------------
+**
+**	MOVE_ABS (LEN)
+**	<<start address>>
+**
+**	MOVE_IND (LEN)
+**	<<dnad_offset>>
+**
+**	MOVE_TBL
+**	<<dnad_offset>>
+**
+**-----------------------------------------------------------
+*/
+
+#define OPC_MOVE          0x08000000
+
+#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
+#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
+#define SCR_MOVE_TBL     (0x10000000 | OPC_MOVE)
+
+#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
+#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
+#define SCR_CHMOV_TBL     (0x10000000)
+
+
+/*-----------------------------------------------------------
+**
+**	Selection
+**
+**-----------------------------------------------------------
+**
+**	SEL_ABS | SCR_ID (0..15)    [ | REL_JMP]
+**	<<alternate_address>>
+**
+**	SEL_TBL | << dnad_offset>>  [ | REL_JMP]
+**	<<alternate_address>>
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_SEL_ABS	0x40000000
+#define	SCR_SEL_ABS_ATN	0x41000000
+#define	SCR_SEL_TBL	0x42000000
+#define	SCR_SEL_TBL_ATN	0x43000000
+
+
+#define SCR_JMP_REL     0x04000000
+#define SCR_ID(id)	(((unsigned long)(id)) << 16)
+
+/*-----------------------------------------------------------
+**
+**	Waiting for Disconnect or Reselect
+**
+**-----------------------------------------------------------
+**
+**	WAIT_DISC
+**	dummy: <<alternate_address>>
+**
+**	WAIT_RESEL
+**	<<alternate_address>>
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_WAIT_DISC	0x48000000
+#define SCR_WAIT_RESEL  0x50000000
+
+/*-----------------------------------------------------------
+**
+**	Bit Set / Reset
+**
+**-----------------------------------------------------------
+**
+**	SET (flags {|.. })
+**
+**	CLR (flags {|.. })
+**
+**-----------------------------------------------------------
+*/
+
+#define SCR_SET(f)     (0x58000000 | (f))
+#define SCR_CLR(f)     (0x60000000 | (f))
+
+#define	SCR_CARRY	0x00000400
+#define	SCR_TRG		0x00000200
+#define	SCR_ACK		0x00000040
+#define	SCR_ATN		0x00000008
+
+
+/*-----------------------------------------------------------
+**
+**	Memory to memory move
+**
+**-----------------------------------------------------------
+**
+**	COPY (bytecount)
+**	<< source_address >>
+**	<< destination_address >>
+**
+**	SCR_COPY   sets the NO FLUSH option by default.
+**	SCR_COPY_F does not set this option.
+**
+**	For chips which do not support this option,
+**	ncr_copy_and_bind() will remove this bit.
+**-----------------------------------------------------------
+*/
+
+#define SCR_NO_FLUSH 0x01000000
+
+#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
+#define SCR_COPY_F(n) (0xc0000000 | (n))
+
+/*-----------------------------------------------------------
+**
+**	Register move and binary operations
+**
+**-----------------------------------------------------------
+**
+**	SFBR_REG (reg, op, data)        reg  = SFBR op data
+**	<< 0 >>
+**
+**	REG_SFBR (reg, op, data)        SFBR = reg op data
+**	<< 0 >>
+**
+**	REG_REG  (reg, op, data)        reg  = reg op data
+**	<< 0 >>
+**
+**-----------------------------------------------------------
+**	On 810A, 860, 825A, 875, 895 and 896 chips the content
+**	of SFBR register can be used as data (SCR_SFBR_DATA).
+**	The 896 has additionnal IO registers starting at
+**	offset 0x80. Bit 7 of register offset is stored in
+**	bit 7 of the SCRIPTS instruction first DWORD.
+**-----------------------------------------------------------
+*/
+
+#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
+
+#define SCR_SFBR_REG(reg,op,data) \
+	(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
+
+#define SCR_REG_SFBR(reg,op,data) \
+	(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
+
+#define SCR_REG_REG(reg,op,data) \
+	(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
+
+
+#define      SCR_LOAD   0x00000000
+#define      SCR_SHL    0x01000000
+#define      SCR_OR     0x02000000
+#define      SCR_XOR    0x03000000
+#define      SCR_AND    0x04000000
+#define      SCR_SHR    0x05000000
+#define      SCR_ADD    0x06000000
+#define      SCR_ADDC   0x07000000
+
+#define      SCR_SFBR_DATA   (0x00800000>>8ul)	/* Use SFBR as data */
+
+/*-----------------------------------------------------------
+**
+**	FROM_REG (reg)		  SFBR = reg
+**	<< 0 >>
+**
+**	TO_REG	 (reg)		  reg  = SFBR
+**	<< 0 >>
+**
+**	LOAD_REG (reg, data)	  reg  = <data>
+**	<< 0 >>
+**
+**	LOAD_SFBR(data)		  SFBR = <data>
+**	<< 0 >>
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_FROM_REG(reg) \
+	SCR_REG_SFBR(reg,SCR_OR,0)
+
+#define	SCR_TO_REG(reg) \
+	SCR_SFBR_REG(reg,SCR_OR,0)
+
+#define	SCR_LOAD_REG(reg,data) \
+	SCR_REG_REG(reg,SCR_LOAD,data)
+
+#define SCR_LOAD_SFBR(data) \
+	(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
+
+/*-----------------------------------------------------------
+**
+**	LOAD  from memory   to register.
+**	STORE from register to memory.
+**
+**	Only supported by 810A, 860, 825A, 875, 895 and 896.
+**
+**-----------------------------------------------------------
+**
+**	LOAD_ABS (LEN)
+**	<<start address>>
+**
+**	LOAD_REL (LEN)        (DSA relative)
+**	<<dsa_offset>>
+**
+**-----------------------------------------------------------
+*/
+
+#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
+#define SCR_NO_FLUSH2	0x02000000
+#define SCR_DSA_REL2	0x10000000
+
+#define SCR_LOAD_R(reg, how, n) \
+	(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
+
+#define SCR_STORE_R(reg, how, n) \
+	(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
+
+#define SCR_LOAD_ABS(reg, n)	SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
+#define SCR_LOAD_REL(reg, n)	SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
+#define SCR_LOAD_ABS_F(reg, n)	SCR_LOAD_R(reg, 0, n)
+#define SCR_LOAD_REL_F(reg, n)	SCR_LOAD_R(reg, SCR_DSA_REL2, n)
+
+#define SCR_STORE_ABS(reg, n)	SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
+#define SCR_STORE_REL(reg, n)	SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
+#define SCR_STORE_ABS_F(reg, n)	SCR_STORE_R(reg, 0, n)
+#define SCR_STORE_REL_F(reg, n)	SCR_STORE_R(reg, SCR_DSA_REL2, n)
+
+
+/*-----------------------------------------------------------
+**
+**	Waiting for Disconnect or Reselect
+**
+**-----------------------------------------------------------
+**
+**	JUMP            [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<address>>
+**
+**	JUMPR           [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<distance>>
+**
+**	CALL            [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<address>>
+**
+**	CALLR           [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<distance>>
+**
+**	RETURN          [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<dummy>>
+**
+**	INT             [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<ident>>
+**
+**	INT_FLY         [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<ident>>
+**
+**	Conditions:
+**	     WHEN (phase)
+**	     IF   (phase)
+**	     CARRYSET
+**	     DATA (data, mask)
+**
+**-----------------------------------------------------------
+*/
+
+#define SCR_NO_OP       0x80000000
+#define SCR_JUMP        0x80080000
+#define SCR_JUMP64      0x80480000
+#define SCR_JUMPR       0x80880000
+#define SCR_CALL        0x88080000
+#define SCR_CALLR       0x88880000
+#define SCR_RETURN      0x90080000
+#define SCR_INT         0x98080000
+#define SCR_INT_FLY     0x98180000
+
+#define IFFALSE(arg)   (0x00080000 | (arg))
+#define IFTRUE(arg)    (0x00000000 | (arg))
+
+#define WHEN(phase)    (0x00030000 | (phase))
+#define IF(phase)      (0x00020000 | (phase))
+
+#define DATA(D)        (0x00040000 | ((D) & 0xff))
+#define MASK(D,M)      (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
+
+#define CARRYSET       (0x00200000)
+
+
+#define SIR_COMPLETE					 0x10000000
+/* script errors */
+#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
+#define SIR_CMD_OUT_ILL_PH     0x00000002
+#define SIR_STATUS_ILL_PH			 0x00000003
+#define SIR_MSG_RECEIVED			 0x00000004
+#define SIR_DATA_IN_ERR        0x00000005
+#define SIR_DATA_OUT_ERR			 0x00000006
+#define SIR_SCRIPT_ERROR			 0x00000007
+#define SIR_MSG_OUT_NO_CMD		 0x00000008
+#define SIR_MSG_OVER7					 0x00000009
+/* Fly interrupt */
+#define INT_ON_FY							 0x00000080
+
+/* Hardware errors  are defined in scsi.h */
+
+#define SCSI_IDENTIFY					0xC0
+
+#endif
diff --git a/include/synopsys/dwcddr21mctl.h b/include/synopsys/dwcddr21mctl.h
new file mode 100644
index 0000000..6bb5cff
--- /dev/null
+++ b/include/synopsys/dwcddr21mctl.h
@@ -0,0 +1,324 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <macpaul@andestech.com>
+ */
+
+/*
+ * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
+ */
+#ifndef __DWCDDR21MCTL_H
+#define __DWCDDR21MCTL_H
+
+#ifndef __ASSEMBLY__
+struct dwcddr21mctl {
+	unsigned int	ccr;		/* Controller Configuration */
+	unsigned int	dcr;		/* DRAM Configuration */
+	unsigned int	iocr;		/* I/O Configuration */
+	unsigned int	csr;		/* Controller Status */
+	unsigned int	drr;		/* DRAM refresh */
+	unsigned int	tpr0;		/* SDRAM Timing Parameters 0 */
+	unsigned int	tpr1;		/* SDRAM Timing Parameters 1 */
+	unsigned int	tpr2;		/* SDRAM Timing Parameters 2 */
+	unsigned int	gdllcr;		/* Global DLL Control */
+	unsigned int	dllcr[10];	/* DLL Control */
+	unsigned int	rslr[4];	/* Rank System Lantency */
+	unsigned int	rdgr[4];	/* Rank DQS Gating */
+	unsigned int	dqtr[9];	/* DQ Timing */
+	unsigned int	dqstr;		/* DQS Timing */
+	unsigned int	dqsbtr;		/* DQS_b Timing */
+	unsigned int	odtcr;		/* ODT Configuration */
+	unsigned int	dtr[2];		/* Data Training */
+	unsigned int	dtar;		/* Data Training Address */
+	unsigned int	rsved[82];	/* Reserved */
+	unsigned int	mr;		/* Mode Register */
+	unsigned int	emr;		/* Extended Mode Register */
+	unsigned int	emr2;		/* Extended Mode Register 2 */
+	unsigned int	emr3;		/* Extended Mode Register 3 */
+	unsigned int	hpcr[32];	/* Host Port Configurarion */
+	unsigned int	pqcr[8];	/* Priority Queue Configuration */
+	unsigned int	mmgcr;		/* Memory Manager General Config */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Control Configuration Register
+ */
+#define DWCDDR21MCTL_CCR_ECCEN(x)	((x) << 0)
+#define DWCDDR21MCTL_CCR_NOMRWR(x)	((x) << 1)
+#define DWCDDR21MCTL_CCR_HOSTEN(x)	((x) << 2)
+#define DWCDDR21MCTL_CCR_XBISC(x)	((x) << 3)
+#define DWCDDR21MCTL_CCR_NOAPD(x)	((x) << 4)
+#define DWCDDR21MCTL_CCR_RRB(x)		((x) << 13)
+#define DWCDDR21MCTL_CCR_DQSCFG(x)	((x) << 14)
+#define DWCDDR21MCTL_CCR_DFTLM(x)	(((x) & 0x3) << 15)
+#define DWCDDR21MCTL_CCR_DFTCMP(x)	((x) << 17)
+#define DWCDDR21MCTL_CCR_FLUSH(x)	((x) << 27)
+#define DWCDDR21MCTL_CCR_ITMRST(x)	((x) << 28)
+#define DWCDDR21MCTL_CCR_IB(x)		((x) << 29)
+#define DWCDDR21MCTL_CCR_DTT(x)		((x) << 30)
+#define DWCDDR21MCTL_CCR_IT(x)		((x) << 31)
+
+/*
+ * DRAM Configuration Register
+ */
+#define DWCDDR21MCTL_DCR_DDRMD(x)	((x) << 0)
+#define DWCDDR21MCTL_DCR_DIO(x)		(((x) & 0x3) << 1)
+#define DWCDDR21MCTL_DCR_DSIZE(x)	(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DCR_SIO(x)		(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DCR_PIO(x)		((x) << 9)
+#define DWCDDR21MCTL_DCR_RANKS(x)	(((x) & 0x3) << 10)
+#define DWCDDR21MCTL_DCR_RNKALL(x)	((x) << 12)
+#define DWCDDR21MCTL_DCR_AMAP(x)	(((x) & 0x3) << 13)
+#define DWCDDR21MCTL_DCR_RANK(x)	(((x) & 0x3) << 25)
+#define DWCDDR21MCTL_DCR_CMD(x)		(((x) & 0xf) << 27)
+#define DWCDDR21MCTL_DCR_EXE(x)		((x) << 31)
+
+/*
+ * I/O Configuration Register
+ */
+#define DWCDDR21MCTL_IOCR_RTT(x)	(((x) & 0xf) << 0)
+#define DWCDDR21MCTL_IOCR_DS(x)		(((x) & 0xf) << 4)
+#define DWCDDR21MCTL_IOCR_TESTEN(x)	((x) << 0x8)
+#define DWCDDR21MCTL_IOCR_RTTOH(x)	(((x) & 0x7) << 26)
+#define DWCDDR21MCTL_IOCR_RTTOE(x)	((x) << 29)
+#define DWCDDR21MCTL_IOCR_DQRTT(x)	((x) << 30)
+#define DWCDDR21MCTL_IOCR_DQSRTT(x)	((x) << 31)
+
+/*
+ * Controller Status Register
+ */
+#define DWCDDR21MCTL_CSR_DRIFT(x)	(((x) & 0x3ff) << 0)
+#define DWCDDR21MCTL_CSR_DFTERR(x)	((x) << 18)
+#define DWCDDR21MCTL_CSR_ECCERR(x)	((x) << 19)
+#define DWCDDR21MCTL_CSR_DTERR(x)	((x) << 20)
+#define DWCDDR21MCTL_CSR_DTIERR(x)	((x) << 21)
+#define DWCDDR21MCTL_CSR_ECCSEC(x)	((x) << 22)
+
+/*
+ * DRAM Refresh Register
+ */
+#define DWCDDR21MCTL_DRR_TRFC(x)	(((x) & 0xff) << 0)
+#define DWCDDR21MCTL_DRR_TRFPRD(x)	(((x) & 0xffff) << 8)
+#define DWCDDR21MCTL_DRR_RFBURST(x)	(((x) & 0xf) << 24)
+#define DWCDDR21MCTL_DRR_RD(x)		((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 0
+ */
+#define DWCDDR21MCTL_TPR0_TMRD(x)	(((x) & 0x3) << 0)
+#define DWCDDR21MCTL_TPR0_TRTP(x)	(((x) & 0x7) << 2)
+#define DWCDDR21MCTL_TPR0_TWTR(x)	(((x) & 0x7) << 5)
+#define DWCDDR21MCTL_TPR0_TRP(x)	(((x) & 0xf) << 8)
+#define DWCDDR21MCTL_TPR0_TRCD(x)	(((x) & 0xf) << 12)
+#define DWCDDR21MCTL_TPR0_TRAS(x)	(((x) & 0x1f) << 16)
+#define DWCDDR21MCTL_TPR0_TRRD(x)	(((x) & 0xf) << 21)
+#define DWCDDR21MCTL_TPR0_TRC(x)	(((x) & 0x3f) << 25)
+#define DWCDDR21MCTL_TPR0_TCCD(x)	((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 1
+ */
+#define DWCDDR21MCTL_TPR1_TAOND(x)	(((x) & 0x3) << 0)
+#define DWCDDR21MCTL_TPR1_TRTW(x)	((x) << 2)
+#define DWCDDR21MCTL_TPR1_TFAW(x)	(((x) & 0x3f) << 3)
+#define DWCDDR21MCTL_TPR1_TRNKRTR(x)	(((x) & 0x3) << 12)
+#define DWCDDR21MCTL_TPR1_TRNKWTW(x)	(((x) & 0x3) << 14)
+#define DWCDDR21MCTL_TPR1_XCL(x)	(((x) & 0xf) << 23)
+#define DWCDDR21MCTL_TPR1_XWR(x)	(((x) & 0xf) << 27)
+#define DWCDDR21MCTL_TPR1_XTP(x)	((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 2
+ */
+#define DWCDDR21MCTL_TPR2_TXS(x)	(((x) & 0x3ff) << 0)
+#define DWCDDR21MCTL_TPR2_TXP(x)	(((x) & 0x1f) << 10)
+#define DWCDDR21MCTL_TPR2_TCKE(x)	(((x) & 0xf) << 15)
+
+/*
+ * Global DLL Control Register
+ */
+#define DWCDDR21MCTL_GDLLCR_DRES(x)	(((x) & 0x3) << 0)
+#define DWCDDR21MCTL_GDLLCR_IPUMP(x)	(((x) & 0x7) << 2)
+#define DWCDDR21MCTL_GDLLCR_TESTEN(x)	((x) << 5)
+#define DWCDDR21MCTL_GDLLCR_DTC(x)	(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_GDLLCR_ATC(x)	(((x) & 0x3) << 9)
+#define DWCDDR21MCTL_GDLLCR_TESTSW(x)	((x) << 11)
+#define DWCDDR21MCTL_GDLLCR_MBIAS(x)	(((x) & 0xff) << 12)
+#define DWCDDR21MCTL_GDLLCR_SBIAS(x)	(((x) & 0xff) << 20)
+#define DWCDDR21MCTL_GDLLCR_LOCKDET(x)	((x) << 29)
+
+/*
+ * DLL Control Register 0-9
+ */
+#define DWCDDR21MCTL_DLLCR_SFBDLY(x)	(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DLLCR_SFWDLY(x)	(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DLLCR_MFBDLY(x)	(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DLLCR_MFWDLY(x)	(((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DLLCR_SSTART(x)	(((x) & 0x3) << 12)
+#define DWCDDR21MCTL_DLLCR_PHASE(x)	(((x) & 0xf) << 14)
+#define DWCDDR21MCTL_DLLCR_ATESTEN(x)	((x) << 18)
+#define DWCDDR21MCTL_DLLCR_DRSVD(x)	((x) << 19)
+#define DWCDDR21MCTL_DLLCR_DD(x)	((x) << 31)
+
+/*
+ * Rank System Lantency Register
+ */
+#define DWCDDR21MCTL_RSLR_SL0(x)	(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_RSLR_SL1(x)	(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_RSLR_SL2(x)	(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_RSLR_SL3(x)	(((x) & 0x7) << 9)
+#define DWCDDR21MCTL_RSLR_SL4(x)	(((x) & 0x7) << 12)
+#define DWCDDR21MCTL_RSLR_SL5(x)	(((x) & 0x7) << 15)
+#define DWCDDR21MCTL_RSLR_SL6(x)	(((x) & 0x7) << 18)
+#define DWCDDR21MCTL_RSLR_SL7(x)	(((x) & 0x7) << 21)
+#define DWCDDR21MCTL_RSLR_SL8(x)	(((x) & 0x7) << 24)
+
+/*
+ * Rank DQS Gating Register
+ */
+#define DWCDDR21MCTL_RDGR_DQSSEL0(x)	(((x) & 0x3) << 0)
+#define DWCDDR21MCTL_RDGR_DQSSEL1(x)	(((x) & 0x3) << 2)
+#define DWCDDR21MCTL_RDGR_DQSSEL2(x)	(((x) & 0x3) << 4)
+#define DWCDDR21MCTL_RDGR_DQSSEL3(x)	(((x) & 0x3) << 6)
+#define DWCDDR21MCTL_RDGR_DQSSEL4(x)	(((x) & 0x3) << 8)
+#define DWCDDR21MCTL_RDGR_DQSSEL5(x)	(((x) & 0x3) << 10)
+#define DWCDDR21MCTL_RDGR_DQSSEL6(x)	(((x) & 0x3) << 12)
+#define DWCDDR21MCTL_RDGR_DQSSEL7(x)	(((x) & 0x3) << 14)
+#define DWCDDR21MCTL_RDGR_DQSSEL8(x)	(((x) & 0x3) << 16)
+
+/*
+ * DQ Timing Register
+ */
+#define DWCDDR21MCTL_DQTR_DQDLY0(x)	(((x) & 0xf) << 0)
+#define DWCDDR21MCTL_DQTR_DQDLY1(x)	(((x) & 0xf) << 4)
+#define DWCDDR21MCTL_DQTR_DQDLY2(x)	(((x) & 0xf) << 8)
+#define DWCDDR21MCTL_DQTR_DQDLY3(x)	(((x) & 0xf) << 12)
+#define DWCDDR21MCTL_DQTR_DQDLY4(x)	(((x) & 0xf) << 16)
+#define DWCDDR21MCTL_DQTR_DQDLY5(x)	(((x) & 0xf) << 20)
+#define DWCDDR21MCTL_DQTR_DQDLY6(x)	(((x) & 0xf) << 24)
+#define DWCDDR21MCTL_DQTR_DQDLY7(x)	(((x) & 0xf) << 28)
+
+/*
+ * DQS Timing Register
+ */
+#define DWCDDR21MCTL_DQSTR_DQSDLY0(x)	(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DQSTR_DQSDLY1(x)	(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DQSTR_DQSDLY2(x)	(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DQSTR_DQSDLY3(x)	(((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DQSTR_DQSDLY4(x)	(((x) & 0x7) << 12)
+#define DWCDDR21MCTL_DQSTR_DQSDLY5(x)	(((x) & 0x7) << 15)
+#define DWCDDR21MCTL_DQSTR_DQSDLY6(x)	(((x) & 0x7) << 18)
+#define DWCDDR21MCTL_DQSTR_DQSDLY7(x)	(((x) & 0x7) << 21)
+#define DWCDDR21MCTL_DQSTR_DQSDLY8(x)	(((x) & 0x7) << 24)
+
+/*
+ * DQS_b (DQSBTR) Timing Register
+ */
+#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x)	(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x)	(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x)	(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x)	(((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x)	(((x) & 0x7) << 12)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x)	(((x) & 0x7) << 15)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x)	(((x) & 0x7) << 18)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x)	(((x) & 0x7) << 21)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x)	(((x) & 0x7) << 24)
+
+/*
+ * ODT Configuration Register
+ */
+#define DWCDDR21MCTL_ODTCR_RDODT0(x)	(((x) & 0xf) << 0)
+#define DWCDDR21MCTL_ODTCR_RDODT1(x)	(((x) & 0xf) << 4)
+#define DWCDDR21MCTL_ODTCR_RDODT2(x)	(((x) & 0xf) << 8)
+#define DWCDDR21MCTL_ODTCR_RDODT3(x)	(((x) & 0xf) << 12)
+#define DWCDDR21MCTL_ODTCR_WDODT0(x)	(((x) & 0xf) << 16)
+#define DWCDDR21MCTL_ODTCR_WDODT1(x)	(((x) & 0xf) << 20)
+#define DWCDDR21MCTL_ODTCR_WDODT2(x)	(((x) & 0xf) << 24)
+#define DWCDDR21MCTL_ODTCR_WDODT3(x)	(((x) & 0xf) << 28)
+
+/*
+ * Data Training Register
+ */
+#define DWCDDR21MCTL_DTR0_DTBYTE0(x)	(((x) & 0xff) << 0)	/* def: 0x11 */
+#define DWCDDR21MCTL_DTR0_DTBYTE1(x)	(((x) & 0xff) << 8)	/* def: 0xee */
+#define DWCDDR21MCTL_DTR0_DTBYTE2(x)	(((x) & 0xff) << 16)	/* def: 0x22 */
+#define DWCDDR21MCTL_DTR0_DTBYTE3(x)	(((x) & 0xff) << 24)	/* def: 0xdd */
+
+#define DWCDDR21MCTL_DTR1_DTBYTE4(x)	(((x) & 0xff) << 0)	/* def: 0x44 */
+#define DWCDDR21MCTL_DTR1_DTBYTE5(x)	(((x) & 0xff) << 8)	/* def: 0xbb */
+#define DWCDDR21MCTL_DTR1_DTBYTE6(x)	(((x) & 0xff) << 16)	/* def: 0x88 */
+#define DWCDDR21MCTL_DTR1_DTBYTE7(x)	(((x) & 0xff) << 24)	/* def: 0x77 */
+
+/*
+ * Data Training Address Register
+ */
+#define DWCDDR21MCTL_DTAR_DTCOL(x)	(((x) & 0xfff) << 0)
+#define DWCDDR21MCTL_DTAR_DTROW(x)	(((x) & 0xffff) << 12)
+#define DWCDDR21MCTL_DTAR_DTBANK(x)	(((x) & 0x7) << 28)
+
+/*
+ * Mode Register
+ */
+#define DWCDDR21MCTL_MR_BL(x)		(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_MR_BT(x)		((x) << 3)
+#define DWCDDR21MCTL_MR_CL(x)		(((x) & 0x7) << 4)
+#define DWCDDR21MCTL_MR_TM(x)		((x) << 7)
+#define DWCDDR21MCTL_MR_DR(x)		((x) << 8)
+#define DWCDDR21MCTL_MR_WR(x)		(((x) & 0x7) << 9)
+#define DWCDDR21MCTL_MR_PD(x)		((x) << 12)
+
+/*
+ * Extended Mode register
+ */
+#define DWCDDR21MCTL_EMR_DE(x)		((x) << 0)
+#define DWCDDR21MCTL_EMR_ODS(x)		((x) << 1)
+#define DWCDDR21MCTL_EMR_RTT2(x)	((x) << 2)
+#define DWCDDR21MCTL_EMR_AL(x)		(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_EMR_RTT6(x)	((x) << 6)
+#define DWCDDR21MCTL_EMR_OCD(x)		(((x) & 0x7) << 7)
+#define DWCDDR21MCTL_EMR_DQS(x)		((x) << 10)
+#define DWCDDR21MCTL_EMR_RDQS(x)	((x) << 11)
+#define DWCDDR21MCTL_EMR_OE(x)		((x) << 12)
+
+#define EMR_RTT2(x)			DWCDDR21MCTL_EMR_RTT2(x)
+#define EMR_RTT6(x)			DWCDDR21MCTL_EMR_RTT6(x)
+
+#define DWCDDR21MCTL_EMR_RTT_DISABLED	(EMR_RTT6(0) | EMR_RTT2(0))
+#define DWCDDR21MCTL_EMR_RTT_75		(EMR_RTT6(0) | EMR_RTT2(1))
+#define DWCDDR21MCTL_EMR_RTT_150	(EMR_RTT6(1) | EMR_RTT2(0))
+#define DWCDDR21MCTL_EMR_RTT_50		(EMR_RTT6(1) | EMR_RTT2(1))
+
+/*
+ * Extended Mode register 2
+ */
+#define DWCDDR21MCTL_EMR2_PASR(x)	(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_EMR2_DCC(x)	((x) << 3)
+#define DWCDDR21MCTL_EMR2_SRF(x)	((x) << 7)
+
+/*
+ * Extended Mode register 3: [15:0] reserved for JEDEC.
+ */
+
+/*
+ * Host port Configuration register 0-31
+ */
+#define DWCDDR21MCTL_HPCR_HPBL(x)	(((x) & 0xf) << 0)
+
+/*
+ * Priority Queue Configuration register 0-7
+ */
+#define DWCDDR21MCTL_HPCR_TOUT(x)	(((x) & 0xf) << 0)
+#define DWCDDR21MCTL_HPCR_TOUTX(x)	(((x) & 0x3) << 8)
+#define DWCDDR21MCTL_HPCR_LPQS(x)	(((x) & 0x3) << 10)
+#define DWCDDR21MCTL_HPCR_PQBL(x)	(((x) & 0xff) << 12)
+#define DWCDDR21MCTL_HPCR_SWAIT(x)	(((x) & 0x1f) << 20)
+#define DWCDDR21MCTL_HPCR_INTRPT(x)	(((x) & 0x7) << 25)
+#define DWCDDR21MCTL_HPCR_APQS(x)	((x) << 28)
+
+/*
+ * Memory Manager General Configuration register
+ */
+#define DWCDDR21MCTL_MMGCR_UHPP(x)	(((x) & 0x3) << 0)
+
+#endif	/* __DWCDDR21MCTL_H */
diff --git a/include/syscon.h b/include/syscon.h
new file mode 100644
index 0000000..3df96e3
--- /dev/null
+++ b/include/syscon.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __SYSCON_H
+#define __SYSCON_H
+
+#include <dm/ofnode.h>
+#include <fdtdec.h>
+
+/**
+ * struct syscon_uc_info - Information stored by the syscon UCLASS_UCLASS
+ *
+ * @regmap:	Register map for this controller
+ */
+struct syscon_uc_info {
+	struct regmap *regmap;
+};
+
+/* So far there are no ops so this is a placeholder */
+struct syscon_ops {
+};
+
+#define syscon_get_ops(dev)        ((struct syscon_ops *)(dev)->driver->ops)
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+/*
+ * We don't support 64-bit machines. If they are so resource-contrained that
+ * they need to use OF_PLATDATA, something is horribly wrong with the
+ * education of our hardware engineers.
+ *
+ * Update: 64-bit is now supported and we have an education crisis.
+ */
+struct syscon_base_platdata {
+	fdt_val_t reg[2];
+};
+#endif
+
+/**
+ * syscon_get_regmap() - Get access to a register map
+ *
+ * @dev:	Device to check (UCLASS_SCON)
+ * @info:	Returns regmap for the device
+ * @return 0 if OK, -ve on error
+ */
+struct regmap *syscon_get_regmap(struct udevice *dev);
+
+/**
+ * syscon_get_regmap_by_driver_data() - Look up a controller by its ID
+ *
+ * Each system controller can be accessed by its driver data, which is
+ * assumed to be unique through the scope of all system controllers that
+ * are in use. This function looks up the controller given this driver data.
+ *
+ * @driver_data:	Driver data value to look up
+ * @devp:		Returns the controller correponding to @driver_data
+ * @return 0 on success, -ENODEV if the ID was not found, or other -ve error
+ *	   code
+ */
+int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp);
+
+/**
+ * syscon_get_regmap_by_driver_data() - Look up a controller by its ID
+ *
+ * Each system controller can be accessed by its driver data, which is
+ * assumed to be unique through the scope of all system controllers that
+ * are in use. This function looks up the regmap given this driver data.
+ *
+ * @driver_data:	Driver data value to look up
+ * @return register map correponding to @driver_data, or -ve error code
+ */
+struct regmap *syscon_get_regmap_by_driver_data(ulong driver_data);
+
+/**
+ * syscon_regmap_lookup_by_phandle() - Look up a controller by a phandle
+ *
+ * This operates by looking up the given name in the device (device
+ * tree property) of the device using the system controller.
+ *
+ * @dev:	Device using the system controller
+ * @name:	Name of property referring to the system controller
+ * @return	A pointer to the regmap if found, ERR_PTR(-ve) on error
+ */
+struct regmap *syscon_regmap_lookup_by_phandle(struct udevice *dev,
+					       const char *name);
+
+/**
+ * syscon_get_first_range() - get the first memory range from a syscon regmap
+ *
+ * @driver_data:	Driver data value to look up
+ * @return first region of register map correponding to @driver_data, or
+ *			-ve error code
+ */
+void *syscon_get_first_range(ulong driver_data);
+
+/**
+ * syscon_node_to_regmap - get regmap from syscon
+ *
+ * @node:		Device node of syscon
+ */
+struct regmap *syscon_node_to_regmap(ofnode node);
+
+#endif
diff --git a/include/sysreset.h b/include/sysreset.h
new file mode 100644
index 0000000..61295e3
--- /dev/null
+++ b/include/sysreset.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __SYSRESET_H
+#define __SYSRESET_H
+
+enum sysreset_t {
+	SYSRESET_WARM,	/* Reset CPU, keep GPIOs active */
+	SYSRESET_COLD,	/* Reset CPU and GPIOs */
+	SYSRESET_POWER,	/* Reset PMIC (remove and restore power) */
+	SYSRESET_POWER_OFF,	/* Turn off power */
+
+	SYSRESET_COUNT,
+};
+
+struct sysreset_ops {
+	/**
+	 * request() - request a sysreset of the given type
+	 *
+	 * Note that this function may return before the reset takes effect.
+	 *
+	 * @type:	Reset type to request
+	 * @return -EINPROGRESS if the reset has been started and
+	 *		will complete soon, -EPROTONOSUPPORT if not supported
+	 *		by this device, 0 if the reset has already happened
+	 *		(in which case this method will not actually return)
+	 */
+	int (*request)(struct udevice *dev, enum sysreset_t type);
+	/**
+	 * get_status() - get printable reset status information
+	 *
+	 * @dev:	Device to check
+	 * @buf:	Buffer to receive the textual reset information
+	 * @size:	Size of the passed buffer
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_status)(struct udevice *dev, char *buf, int size);
+
+	/**
+	 * get_last() - get information on the last reset
+	 *
+	 * @dev:	Device to check
+	 * @return last reset state (enum sysreset_t) or -ve error
+	 */
+	int (*get_last)(struct udevice *dev);
+};
+
+#define sysreset_get_ops(dev)        ((struct sysreset_ops *)(dev)->driver->ops)
+
+/**
+ * sysreset_request() - request a sysreset
+ *
+ * @type:	Reset type to request
+ * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device
+ */
+int sysreset_request(struct udevice *dev, enum sysreset_t type);
+
+/**
+ * sysreset_get_status() - get printable reset status information
+ *
+ * @dev:	Device to check
+ * @buf:	Buffer to receive the textual reset information
+ * @size:	Size of the passed buffer
+ * @return 0 if OK, -ve on error
+ */
+int sysreset_get_status(struct udevice *dev, char *buf, int size);
+
+/**
+ * sysreset_get_last() - get information on the last reset
+ *
+ * @dev:	Device to check
+ * @return last reset state (enum sysreset_t) or -ve error
+ */
+int sysreset_get_last(struct udevice *dev);
+
+/**
+ * sysreset_walk() - cause a system reset
+ *
+ * This works through the available sysreset devices until it finds one that can
+ * perform a reset. If the provided sysreset type is not available, the next one
+ * will be tried.
+ *
+ * If this function fails to reset, it will display a message and halt
+ *
+ * @type:	Reset type to request
+ * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available
+ */
+int sysreset_walk(enum sysreset_t type);
+
+/**
+ * sysreset_get_last_walk() - get information on the last reset
+ *
+ * This works through the available sysreset devices until it finds one that can
+ * perform a reset. If the provided sysreset type is not available, the next one
+ * will be tried.
+ *
+ * If no device prives the information, this function returns -ENOENT
+ *
+ * @return last reset state (enum sysreset_t) or -ve error
+ */
+int sysreset_get_last_walk(void);
+
+/**
+ * sysreset_walk_halt() - try to reset, otherwise halt
+ *
+ * This calls sysreset_walk(). If it returns, indicating that reset is not
+ * supported, it prints a message and halts.
+ */
+void sysreset_walk_halt(enum sysreset_t type);
+
+/**
+ * reset_cpu() - calls sysreset_walk(SYSRESET_WARM)
+ */
+void reset_cpu(ulong addr);
+
+#endif
diff --git a/include/tables_csum.h b/include/tables_csum.h
new file mode 100644
index 0000000..5f7edc4
--- /dev/null
+++ b/include/tables_csum.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _TABLES_CSUM_H_
+#define _TABLES_CSUM_H_
+
+static inline u8 table_compute_checksum(void *v, int len)
+{
+	u8 *bytes = v;
+	u8 checksum = 0;
+	int i;
+
+	for (i = 0; i < len; i++)
+		checksum -= bytes[i];
+
+	return checksum;
+}
+
+#endif
diff --git a/include/tca642x.h b/include/tca642x.h
new file mode 100644
index 0000000..bda86c1
--- /dev/null
+++ b/include/tca642x.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Derived work from the pca953x.c driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TCA642X_H_
+#define __TCA642X_H_
+
+#ifdef CONFIG_CMD_TCA642X
+enum {
+	TCA642X_CMD_INFO,
+	TCA642X_CMD_DEVICE,
+	TCA642X_CMD_OUTPUT,
+	TCA642X_CMD_INPUT,
+	TCA642X_CMD_INVERT,
+};
+#endif
+
+#define TCA642X_OUT_LOW		0
+#define TCA642X_OUT_HIGH	1
+#define TCA642X_POL_NORMAL	0
+#define TCA642X_POL_INVERT	1
+#define TCA642X_DIR_OUT		0
+#define TCA642X_DIR_IN		1
+
+/* Default to an address that hopefully won't corrupt other i2c devices */
+#ifndef CONFIG_SYS_I2C_TCA642X_ADDR
+#define CONFIG_SYS_I2C_TCA642X_ADDR	(~0)
+#endif
+
+/* Default to an address that hopefully won't corrupt other i2c devices */
+#ifndef CONFIG_SYS_I2C_TCA642X_BUS_NUM
+#define CONFIG_SYS_I2C_TCA642X_BUS_NUM	(0)
+#endif
+
+struct tca642x_bank_info {
+	uint8_t input_reg;
+	uint8_t output_reg;
+	uint8_t polarity_reg;
+	uint8_t configuration_reg;
+};
+
+int tca642x_set_val(uchar chip, uint8_t gpio_bank,
+			uint8_t reg_bit, uint8_t data);
+int tca642x_set_pol(uchar chip, uint8_t gpio_bank,
+			uint8_t reg_bit, uint8_t data);
+int tca642x_set_dir(uchar chip, uint8_t gpio_bank,
+			uint8_t reg_bit, uint8_t data);
+int tca642x_get_val(uchar chip, uint8_t gpio_bank);
+int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[]);
+
+#endif /* __TCA642X_H_ */
diff --git a/include/tee.h b/include/tee.h
new file mode 100644
index 0000000..02bcd9e
--- /dev/null
+++ b/include/tee.h
@@ -0,0 +1,377 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Linaro Limited
+ */
+
+#ifndef __TEE_H
+#define __TEE_H
+
+#define TEE_UUID_LEN		16
+
+#define TEE_GEN_CAP_GP          BIT(0)	/* GlobalPlatform compliant TEE */
+#define TEE_GEN_CAP_REG_MEM     BIT(1)	/* Supports registering shared memory */
+
+#define TEE_SHM_REGISTER	BIT(0)	/* In list of shared memory */
+#define TEE_SHM_SEC_REGISTER	BIT(1)	/* TEE notified of this memory */
+#define TEE_SHM_ALLOC		BIT(2)	/* The memory is malloced() and must */
+					/* be freed() */
+
+#define TEE_PARAM_ATTR_TYPE_NONE		0	/* parameter not used */
+#define TEE_PARAM_ATTR_TYPE_VALUE_INPUT		1
+#define TEE_PARAM_ATTR_TYPE_VALUE_OUTPUT	2
+#define TEE_PARAM_ATTR_TYPE_VALUE_INOUT		3	/* input and output */
+#define TEE_PARAM_ATTR_TYPE_MEMREF_INPUT	5
+#define TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT	6
+#define TEE_PARAM_ATTR_TYPE_MEMREF_INOUT	7	/* input and output */
+#define TEE_PARAM_ATTR_TYPE_MASK		0xff
+#define TEE_PARAM_ATTR_META			0x100
+#define TEE_PARAM_ATTR_MASK			(TEE_PARAM_ATTR_TYPE_MASK | \
+						 TEE_PARAM_ATTR_META)
+
+/*
+ * Some Global Platform error codes which has a meaning if the
+ * TEE_GEN_CAP_GP bit is returned by the driver in
+ * struct tee_version_data::gen_caps
+ */
+#define TEE_SUCCESS			0x00000000
+#define TEE_ERROR_STORAGE_NOT_AVAILABLE	0xf0100003
+#define TEE_ERROR_GENERIC		0xffff0000
+#define TEE_ERROR_BAD_PARAMETERS	0xffff0006
+#define TEE_ERROR_ITEM_NOT_FOUND	0xffff0008
+#define TEE_ERROR_NOT_IMPLEMENTED	0xffff0009
+#define TEE_ERROR_NOT_SUPPORTED		0xffff000a
+#define TEE_ERROR_COMMUNICATION		0xffff000e
+#define TEE_ERROR_SECURITY		0xffff000f
+#define TEE_ERROR_OUT_OF_MEMORY		0xffff000c
+#define TEE_ERROR_OVERFLOW              0xffff300f
+#define TEE_ERROR_TARGET_DEAD		0xffff3024
+#define TEE_ERROR_STORAGE_NO_SPACE      0xffff3041
+
+#define TEE_ORIGIN_COMMS		0x00000002
+#define TEE_ORIGIN_TEE			0x00000003
+#define TEE_ORIGIN_TRUSTED_APP		0x00000004
+
+struct udevice;
+
+/**
+ * struct tee_optee_ta_uuid - OP-TEE Trusted Application (TA) UUID format
+ *
+ * Used to identify an OP-TEE TA and define suitable to initialize structs
+ * of this format is distributed with the interface of the TA. The
+ * individual fields of this struct doesn't have any special meaning in
+ * OP-TEE. See RFC4122 for details on the format.
+ */
+struct tee_optee_ta_uuid {
+	u32 time_low;
+	u16 time_mid;
+	u16 time_hi_and_version;
+	u8 clock_seq_and_node[8];
+};
+
+/**
+ * struct tee_shm - memory shared with the TEE
+ * @dev:	The TEE device
+ * @link:	List node in the list in struct struct tee_uclass_priv
+ * @addr:	Pointer to the shared memory
+ * @size:	Size of the the shared memory
+ * @flags:	TEE_SHM_* above
+ */
+struct tee_shm {
+	struct udevice *dev;
+	struct list_head link;
+	void *addr;
+	ulong size;
+	u32 flags;
+};
+
+/**
+ * struct tee_param_memref - memory reference for a Trusted Application
+ * @shm_offs:	Offset in bytes into the shared memory object @shm
+ * @size:	Size in bytes of the memory reference
+ * @shm:	Pointer to a shared memory object for the buffer
+ *
+ * Used as a part of struct tee_param, see that for more information.
+ */
+struct tee_param_memref {
+	ulong shm_offs;
+	ulong size;
+	struct tee_shm *shm;
+};
+
+/**
+ * struct tee_param_value - value parameter for a Trusted Application
+ * @a, @b, @c:	Parameters passed by value
+ *
+ * Used as a part of struct tee_param, see that for more information.
+ */
+struct tee_param_value {
+	u64 a;
+	u64 b;
+	u64 c;
+};
+
+/**
+ * struct tee_param - invoke parameter for a Trusted Application
+ * @attr:	Attributes
+ * @u.memref:	Memref parameter if (@attr & TEE_PARAM_ATTR_MASK) is one of
+ *		TEE_PARAM_ATTR_TYPE_MEMREF_* above
+ * @u.value:	Value parameter if (@attr & TEE_PARAM_ATTR_MASK) is one of
+ *		TEE_PARAM_ATTR_TYPE_VALUE_* above
+ *
+ * Parameters to TA are passed using an array of this struct, for
+ * flexibility both value parameters and memory refereces can be used.
+ */
+struct tee_param {
+	u64 attr;
+	union {
+		struct tee_param_memref memref;
+		struct tee_param_value value;
+	} u;
+};
+
+/**
+ * struct tee_open_session_arg - extra arguments for tee_open_session()
+ * @uuid:	[in] UUID of the Trusted Application
+ * @clnt_uuid:	[in] Normally zeroes
+ * @clnt_login:	[in] Normally 0
+ * @session:	[out] Session id
+ * @ret:	[out] return value
+ * @ret_origin:	[out] origin of the return value
+ */
+struct tee_open_session_arg {
+	u8 uuid[TEE_UUID_LEN];
+	u8 clnt_uuid[TEE_UUID_LEN];
+	u32 clnt_login;
+	u32 session;
+	u32 ret;
+	u32 ret_origin;
+};
+
+/**
+ * struct tee_invoke_arg - extra arguments for tee_invoke_func()
+ * @func:	[in] Trusted Application function, specific to the TA
+ * @session:	[in] Session id, from open session
+ * @ret:	[out] return value
+ * @ret_origin:	[out] origin of the return value
+ */
+struct tee_invoke_arg {
+	u32 func;
+	u32 session;
+	u32 ret;
+	u32 ret_origin;
+};
+
+/**
+ * struct tee_version_data - description of TEE
+ * @gen_caps:	Generic capabilities, TEE_GEN_CAP_* above
+ */
+struct tee_version_data {
+	u32 gen_caps;
+};
+
+/**
+ * struct tee_driver_ops - TEE driver operations
+ * @get_version:	Query capabilities of TEE device,
+ * @open_session:	Opens a session to a Trusted Application in the TEE,
+ * @close_session:	Closes a session to Trusted Application,
+ * @invoke_func:	Invokes a function in a Trusted Application,
+ * @shm_register:	Registers memory shared with the TEE
+ * @shm_unregister:	Unregisters memory shared with the TEE
+ */
+struct tee_driver_ops {
+	/**
+	 * get_version() - Query capabilities of TEE device
+	 * @dev:	The TEE device
+	 * @vers:	Pointer to version data
+	 */
+	void (*get_version)(struct udevice *dev, struct tee_version_data *vers);
+	/**
+	 * open_session() - Open a session to a Trusted Application
+	 * @dev:	The TEE device
+	 * @arg:	Open session arguments
+	 * @num_param:	Number of elements in @param
+	 * @param:	Parameters for Trusted Application
+	 *
+	 * Returns < 0 on error else see @arg->ret for result. If @arg->ret is
+	 * TEE_SUCCESS the session identifier is available in @arg->session.
+	 */
+	int (*open_session)(struct udevice *dev,
+			    struct tee_open_session_arg *arg, uint num_param,
+			    struct tee_param *param);
+	/**
+	 * close_session() - Close a session to a Trusted Application
+	 * @dev:	The TEE device
+	 * @session:	Session id
+	 *
+	 * Return < 0 on error else 0, regardless the session will not be valid
+	 * after this function has returned.
+	 */
+	int (*close_session)(struct udevice *dev, u32 session);
+	/**
+	 * tee_invoke_func() - Invoke a function in a Trusted Application
+	 * @dev:	The TEE device
+	 * @arg:	Invoke arguments
+	 * @num_param:	Number of elements in @param
+	 * @param:	Parameters for Trusted Application
+	 *
+	 * Returns < 0 on error else see @arg->ret for result.
+	 */
+	int (*invoke_func)(struct udevice *dev, struct tee_invoke_arg *arg,
+			   uint num_param, struct tee_param *param);
+	/**
+	 * shm_register() - Registers memory shared with the TEE
+	 * @dev:	The TEE device
+	 * @shm:	Pointer to a shared memory object
+	 * Returns 0 on success or < 0 on failure.
+	 */
+	int (*shm_register)(struct udevice *dev, struct tee_shm *shm);
+	/**
+	 * shm_unregister() - Unregisters memory shared with the TEE
+	 * @dev:	The TEE device
+	 * @shm:	Pointer to a shared memory object
+	 * Returns 0 on success or < 0 on failure.
+	 */
+	int (*shm_unregister)(struct udevice *dev, struct tee_shm *shm);
+};
+
+/**
+ * __tee_shm_add() - Internal helper function to register shared memory
+ * @dev:	The TEE device
+ * @align:	Required alignment of allocated memory block if
+ *		(@flags & TEE_SHM_ALLOC)
+ * @addr:	Address of memory block, ignored if (@flags & TEE_SHM_ALLOC)
+ * @size:	Size of memory block
+ * @flags:	TEE_SHM_* above
+ * @shmp:	If the function return 0, this holds the allocated
+ *		struct tee_shm
+ *
+ * returns 0 on success or < 0 on failure.
+ */
+int __tee_shm_add(struct udevice *dev, ulong align, void *addr, ulong size,
+		  u32 flags, struct tee_shm **shmp);
+
+/**
+ * tee_shm_alloc() - Allocate shared memory
+ * @dev:	The TEE device
+ * @size:	Size of memory block
+ * @flags:	TEE_SHM_* above
+ * @shmp:	If the function return 0, this holds the allocated
+ *		struct tee_shm
+ *
+ * returns 0 on success or < 0 on failure.
+ */
+int tee_shm_alloc(struct udevice *dev, ulong size, u32 flags,
+		  struct tee_shm **shmp);
+
+/**
+ * tee_shm_register() - Registers shared memory
+ * @dev:	The TEE device
+ * @addr:	Address of memory block
+ * @size:	Size of memory block
+ * @flags:	TEE_SHM_* above
+ * @shmp:	If the function return 0, this holds the allocated
+ *		struct tee_shm
+ *
+ * returns 0 on success or < 0 on failure.
+ */
+int tee_shm_register(struct udevice *dev, void *addr, ulong size, u32 flags,
+		     struct tee_shm **shmp);
+
+/**
+ * tee_shm_free() - Frees shared memory
+ * @shm:	Shared memory object
+ */
+void tee_shm_free(struct tee_shm *shm);
+
+/**
+ * tee_shm_is_registered() - Check register status of shared memory object
+ * @shm:	Pointer to shared memory object
+ * @dev:	The TEE device
+ *
+ * Returns true if the shared memory object is registered for the supplied
+ * TEE device
+ */
+bool tee_shm_is_registered(struct tee_shm *shm, struct udevice *dev);
+
+/**
+ * tee_find_device() - Look up a TEE device
+ * @start:	if not NULL, continue search after this device
+ * @match:	function to check TEE device, returns != 0 if the device
+ *		matches
+ * @data:	data for match function
+ * @vers:	if not NULL, version data of TEE device of the device returned
+ *
+ * Returns a probed TEE device of the first TEE device matched by the
+ * match() callback or NULL.
+ */
+struct udevice *tee_find_device(struct udevice *start,
+				int (*match)(struct tee_version_data *vers,
+					     const void *data),
+				const void *data,
+				struct tee_version_data *vers);
+
+/**
+ * tee_get_version() - Query capabilities of TEE device
+ * @dev:	The TEE device
+ * @vers:	Pointer to version data
+ */
+void tee_get_version(struct udevice *dev, struct tee_version_data *vers);
+
+/**
+ * tee_open_session() - Open a session to a Trusted Application
+ * @dev:	The TEE device
+ * @arg:	Open session arguments
+ * @num_param:	Number of elements in @param
+ * @param:	Parameters for Trusted Application
+ *
+ * Returns < 0 on error else see @arg->ret for result. If @arg->ret is
+ * TEE_SUCCESS the session identifier is available in @arg->session.
+ */
+int tee_open_session(struct udevice *dev, struct tee_open_session_arg *arg,
+		     uint num_param, struct tee_param *param);
+
+/**
+ * tee_close_session() - Close a session to a Trusted Application
+ * @dev:	The TEE device
+ * @session:	Session id
+ *
+ * Return < 0 on error else 0, regardless the session will not be valid
+ * after this function has returned.
+ */
+int tee_close_session(struct udevice *dev, u32 session);
+
+/**
+ * tee_invoke_func() - Invoke a function in a Trusted Application
+ * @dev:	The TEE device
+ * @arg:	Invoke arguments
+ * @num_param:	Number of elements in @param
+ * @param:	Parameters for Trusted Application
+ *
+ * Returns < 0 on error else see @arg->ret for result.
+ */
+int tee_invoke_func(struct udevice *dev, struct tee_invoke_arg *arg,
+		    uint num_param, struct tee_param *param);
+
+/**
+ * tee_optee_ta_uuid_from_octets() - Converts to struct tee_optee_ta_uuid
+ * @d:	Destination struct
+ * @s:	Source UUID octets
+ *
+ * Conversion to a struct tee_optee_ta_uuid represantion from binary octet
+ * representation.
+ */
+void tee_optee_ta_uuid_from_octets(struct tee_optee_ta_uuid *d,
+				   const u8 s[TEE_UUID_LEN]);
+
+/**
+ * tee_optee_ta_uuid_to_octets() - Converts from struct tee_optee_ta_uuid
+ * @d:	Destination UUID octets
+ * @s:	Source struct
+ *
+ * Conversion from a struct tee_optee_ta_uuid represantion to binary octet
+ * representation.
+ */
+void tee_optee_ta_uuid_to_octets(u8 d[TEE_UUID_LEN],
+				 const struct tee_optee_ta_uuid *s);
+
+#endif /* __TEE_H */
diff --git a/include/tee/optee.h b/include/tee/optee.h
new file mode 100644
index 0000000..9446928
--- /dev/null
+++ b/include/tee/optee.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * OP-TEE related definitions
+ *
+ * (C) Copyright 2016 Linaro Limited
+ * Andrew F. Davis <andrew.davis@linaro.org>
+ */
+
+#ifndef	_OPTEE_H
+#define _OPTEE_H
+
+#include <linux/errno.h>
+
+#define OPTEE_MAGIC             0x4554504f
+#define OPTEE_VERSION           1
+#define OPTEE_ARCH_ARM32        0
+#define OPTEE_ARCH_ARM64        1
+
+struct optee_header {
+	uint32_t magic;
+	uint8_t version;
+	uint8_t arch;
+	uint16_t flags;
+	uint32_t init_size;
+	uint32_t init_load_addr_hi;
+	uint32_t init_load_addr_lo;
+	uint32_t init_mem_usage;
+	uint32_t paged_size;
+};
+
+static inline uint32_t optee_image_get_entry_point(const image_header_t *hdr)
+{
+	struct optee_header *optee_hdr = (struct optee_header *)(hdr + 1);
+
+	return optee_hdr->init_load_addr_lo;
+}
+
+static inline uint32_t optee_image_get_load_addr(const image_header_t *hdr)
+{
+	return optee_image_get_entry_point(hdr) - sizeof(struct optee_header);
+}
+
+#if defined(CONFIG_OPTEE)
+int optee_verify_image(struct optee_header *hdr, unsigned long tzdram_start,
+		       unsigned long tzdram_len, unsigned long image_len);
+#else
+static inline int optee_verify_image(struct optee_header *hdr,
+				     unsigned long tzdram_start,
+				     unsigned long tzdram_len,
+				     unsigned long image_len)
+{
+	return -EPERM;
+}
+
+#endif
+
+#if defined(CONFIG_OPTEE)
+int optee_verify_bootm_image(unsigned long image_addr,
+			     unsigned long image_load_addr,
+			     unsigned long image_len);
+#else
+static inline int optee_verify_bootm_image(unsigned long image_addr,
+					   unsigned long image_load_addr,
+					   unsigned long image_len)
+{
+	return -EPERM;
+}
+#endif
+
+#endif /* _OPTEE_H */
diff --git a/include/tee/optee_ta_avb.h b/include/tee/optee_ta_avb.h
new file mode 100644
index 0000000..949875a
--- /dev/null
+++ b/include/tee/optee_ta_avb.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/* Copyright (c) 2018, Linaro Limited */
+
+#ifndef __TA_AVB_H
+#define __TA_AVB_H
+
+#define TA_AVB_UUID { 0x023f8f1a, 0x292a, 0x432b, \
+		      { 0x8f, 0xc4, 0xde, 0x84, 0x71, 0x35, 0x80, 0x67 } }
+
+#define TA_AVB_MAX_ROLLBACK_LOCATIONS	256
+
+/*
+ * Gets the rollback index corresponding to the given rollback index slot.
+ *
+ * in	params[0].value.a:	rollback index slot
+ * out	params[1].value.a:	upper 32 bits of rollback index
+ * out	params[1].value.b:	lower 32 bits of rollback index
+ */
+#define TA_AVB_CMD_READ_ROLLBACK_INDEX	0
+
+/*
+ * Updates the rollback index corresponding to the given rollback index slot.
+ *
+ * Will refuse to update a slot with a lower value.
+ *
+ * in	params[0].value.a:	rollback index slot
+ * in	params[1].value.a:	upper 32 bits of rollback index
+ * in	params[1].value.b:	lower 32 bits of rollback index
+ */
+#define TA_AVB_CMD_WRITE_ROLLBACK_INDEX	1
+
+/*
+ * Gets the lock state of the device.
+ *
+ * out	params[0].value.a:	lock state
+ */
+#define TA_AVB_CMD_READ_LOCK_STATE	2
+
+/*
+ * Sets the lock state of the device.
+ *
+ * If the lock state is changed all rollback slots will be reset to 0
+ *
+ * in	params[0].value.a:	lock state
+ */
+#define TA_AVB_CMD_WRITE_LOCK_STATE	3
+
+/*
+ * Reads a persistent value corresponding to the given name.
+ *
+ * in	params[0].u.memref:	persistent value name
+ * out	params[1].u.memref:	read persistent value buffer
+ */
+#define TA_AVB_CMD_READ_PERSIST_VALUE	4
+
+/*
+ * Writes a persistent value corresponding to the given name.
+ *
+ * in	params[0].u.memref:	persistent value name
+ * in	params[1].u.memref:	persistent value buffer to write
+ */
+#define TA_AVB_CMD_WRITE_PERSIST_VALUE	5
+
+#endif /* __TA_AVB_H */
diff --git a/include/tegra-kbc.h b/include/tegra-kbc.h
new file mode 100644
index 0000000..f331c79
--- /dev/null
+++ b/include/tegra-kbc.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __include_tegra_kbc_h__
+#define __include_tegra_kbc_h__
+
+#include <common.h>
+
+#define KEY_IS_MODIFIER(key) ((key) >= KEY_FIRST_MODIFIER)
+
+struct kbc_tegra {
+	u32 control;
+	u32 interrupt;
+	u32 row_cfg[4];
+	u32 col_cfg[3];
+	u32 timeout_dly;
+	u32 init_dly;
+	u32 rpt_dly;
+	u32 kp_ent[2];
+	u32 row_mask[16];
+};
+
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+extern int overwrite_console(void);
+#define OVERWRITE_CONSOLE overwrite_console()
+#else
+#define OVERWRITE_CONSOLE 0
+#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
+
+#endif /* __include_tegra_kbc_h__ */
diff --git a/include/test/compression.h b/include/test/compression.h
new file mode 100644
index 0000000..02fcfa4
--- /dev/null
+++ b/include/test/compression.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __TEST_COMPRESSION_H__
+#define __TEST_COMPRESSION_H__
+
+#include <test/test.h>
+
+/* Declare a new compression test */
+#define COMPRESSION_TEST(_name, _flags) \
+		UNIT_TEST(_name, _flags, compression_test)
+
+#endif /* __TEST_ENV_H__ */
diff --git a/include/test/env.h b/include/test/env.h
new file mode 100644
index 0000000..f45e33d
--- /dev/null
+++ b/include/test/env.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015
+ * Joe Hershberger, National Instruments, joe.hershberger@ni.com
+ */
+
+#ifndef __TEST_ENV_H__
+#define __TEST_ENV_H__
+
+#include <test/test.h>
+
+/* Declare a new environment test */
+#define ENV_TEST(_name, _flags)	UNIT_TEST(_name, _flags, env_test)
+
+#endif /* __TEST_ENV_H__ */
diff --git a/include/test/lib.h b/include/test/lib.h
new file mode 100644
index 0000000..04b6241
--- /dev/null
+++ b/include/test/lib.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+#ifndef __TEST_LIB_H__
+#define __TEST_LIB_H__
+
+#include <test/test.h>
+
+/* Declare a new library function test */
+#define LIB_TEST(_name, _flags)	UNIT_TEST(_name, _flags, lib_test)
+
+#endif /* __TEST_LIB_H__ */
diff --git a/include/test/overlay.h b/include/test/overlay.h
new file mode 100644
index 0000000..c13f4d6
--- /dev/null
+++ b/include/test/overlay.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2016 NextThing Co
+ * Copyright (c) 2016 Free Electrons
+ */
+
+#ifndef __TEST_OVERLAY_H__
+#define __TEST_OVERLAY_H__
+
+#include <test/test.h>
+
+/* Declare a new environment test */
+#define OVERLAY_TEST(_name, _flags)	UNIT_TEST(_name, _flags, overlay_test)
+
+#endif /* __TEST_OVERLAY_H__ */
diff --git a/include/test/suites.h b/include/test/suites.h
new file mode 100644
index 0000000..01bee09
--- /dev/null
+++ b/include/test/suites.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2015
+ * Joe Hershberger, National Instruments, joe.hershberger@ni.com
+ */
+
+#ifndef __TEST_SUITES_H__
+#define __TEST_SUITES_H__
+
+struct unit_test;
+
+/**
+ * cmd_ut_category() - Run a category of unit tests
+ *
+ * @name:	Category name
+ * @tests:	List of tests to run
+ * @n_ents:	Number of tests in @tests
+ * @argc:	Argument count provided. Must be >= 1. If this is 1 then all
+ *		tests are run, otherwise only the one named @argv[1] is run.
+ * @argv:	Arguments: argv[1] is the test to run (if @argc >= 2)
+ * @return 0 if OK, CMD_RET_FAILURE on failure
+ */
+int cmd_ut_category(const char *name, struct unit_test *tests, int n_ents,
+		    int argc, char * const argv[]);
+
+int do_ut_bloblist(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+int do_ut_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ut_lib(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ut_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ut_unicode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+#endif /* __TEST_SUITES_H__ */
diff --git a/include/test/test.h b/include/test/test.h
new file mode 100644
index 0000000..98fbcd1
--- /dev/null
+++ b/include/test/test.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 Google, Inc.
+ */
+
+#ifndef __TEST_TEST_H
+#define __TEST_TEST_H
+
+#include <malloc.h>
+
+/*
+ * struct unit_test_state - Entire state of test system
+ *
+ * @fail_count: Number of tests that failed
+ * @start: Store the starting mallinfo when doing leak test
+ * @priv: A pointer to some other info some suites want to track
+ * @of_root: Record of the livetree root node (used for setting up tests)
+ */
+struct unit_test_state {
+	int fail_count;
+	struct mallinfo start;
+	void *priv;
+	struct device_node *of_root;
+};
+
+/**
+ * struct unit_test - Information about a unit test
+ *
+ * @name: Name of test
+ * @func: Function to call to perform test
+ * @flags: Flags indicated pre-conditions for test
+ */
+struct unit_test {
+	const char *file;
+	const char *name;
+	int (*func)(struct unit_test_state *state);
+	int flags;
+};
+
+/* Declare a new unit test */
+#define UNIT_TEST(_name, _flags, _suite)				\
+	ll_entry_declare(struct unit_test, _name, _suite) = {		\
+		.file = __FILE__,					\
+		.name = #_name,						\
+		.flags = _flags,					\
+		.func = _name,						\
+	}
+
+
+#endif /* __TEST_TEST_H */
diff --git a/include/test/ut.h b/include/test/ut.h
new file mode 100644
index 0000000..19bcb8c
--- /dev/null
+++ b/include/test/ut.h
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Simple unit test library
+ *
+ * Copyright (c) 2013 Google, Inc
+ */
+
+#ifndef __TEST_UT_H
+#define __TEST_UT_H
+
+#include <linux/err.h>
+
+struct unit_test_state;
+
+/**
+ * ut_fail() - Record failure of a unit test
+ *
+ * @uts: Test state
+ * @fname: Filename where the error occurred
+ * @line: Line number where the error occurred
+ * @func: Function name where the error occurred
+ * @cond: The condition that failed
+ */
+void ut_fail(struct unit_test_state *uts, const char *fname, int line,
+	     const char *func, const char *cond);
+
+/**
+ * ut_failf() - Record failure of a unit test
+ *
+ * @uts: Test state
+ * @fname: Filename where the error occurred
+ * @line: Line number where the error occurred
+ * @func: Function name where the error occurred
+ * @cond: The condition that failed
+ * @fmt: printf() format string for the error, followed by args
+ */
+void ut_failf(struct unit_test_state *uts, const char *fname, int line,
+	      const char *func, const char *cond, const char *fmt, ...)
+			__attribute__ ((format (__printf__, 6, 7)));
+
+
+/* Assert that a condition is non-zero */
+#define ut_assert(cond)							\
+	if (!(cond)) {							\
+		ut_fail(uts, __FILE__, __LINE__, __func__, #cond);	\
+		return CMD_RET_FAILURE;					\
+	}
+
+/* Assert that a condition is non-zero, with printf() string */
+#define ut_assertf(cond, fmt, args...)					\
+	if (!(cond)) {							\
+		ut_failf(uts, __FILE__, __LINE__, __func__, #cond,	\
+			 fmt, ##args);					\
+		return CMD_RET_FAILURE;					\
+	}
+
+/* Assert that two int expressions are equal */
+#define ut_asserteq(expr1, expr2) {					\
+	unsigned int val1 = (expr1), val2 = (expr2);			\
+									\
+	if (val1 != val2) {						\
+		ut_failf(uts, __FILE__, __LINE__, __func__,		\
+			 #expr1 " == " #expr2,				\
+			 "Expected %d, got %d", val1, val2);		\
+		return CMD_RET_FAILURE;					\
+	}								\
+}
+
+/* Assert that two string expressions are equal */
+#define ut_asserteq_str(expr1, expr2) {					\
+	const char *val1 = (expr1), *val2 = (expr2);			\
+									\
+	if (strcmp(val1, val2)) {					\
+		ut_failf(uts, __FILE__, __LINE__, __func__,		\
+			 #expr1 " = " #expr2,				\
+			 "Expected \"%s\", got \"%s\"", val1, val2);	\
+		return CMD_RET_FAILURE;					\
+	}								\
+}
+
+/* Assert that two memory areas are equal */
+#define ut_asserteq_mem(expr1, expr2, len) {				\
+	const u8 *val1 = (u8 *)(expr1), *val2 = (u8 *)(expr2);		\
+	const uint __len = len;						\
+									\
+	if (memcmp(val1, val2, __len)) {				\
+		char __buf1[64 + 1] = "\0";				\
+		char __buf2[64 + 1] = "\0";				\
+		bin2hex(__buf1, val1, min(__len, (uint)32));		\
+		bin2hex(__buf2, val2, min(__len, (uint)32));		\
+		ut_failf(uts, __FILE__, __LINE__, __func__,		\
+			 #expr1 " = " #expr2,				\
+			 "Expected \"%s\", got \"%s\"",			\
+			 __buf1, __buf2);				\
+		return CMD_RET_FAILURE;					\
+	}								\
+}
+
+/* Assert that two pointers are equal */
+#define ut_asserteq_ptr(expr1, expr2) {					\
+	const void *val1 = (expr1), *val2 = (expr2);			\
+									\
+	if (val1 != val2) {						\
+		ut_failf(uts, __FILE__, __LINE__, __func__,		\
+			 #expr1 " = " #expr2,				\
+			 "Expected %p, got %p", val1, val2);		\
+		return CMD_RET_FAILURE;					\
+	}								\
+}
+
+/* Assert that a pointer is NULL */
+#define ut_assertnull(expr) {					\
+	const void *val = (expr);					\
+									\
+	if (val != NULL) {						\
+		ut_failf(uts, __FILE__, __LINE__, __func__,		\
+			 #expr " != NULL",				\
+			 "Expected NULL, got %p", val);		\
+		return CMD_RET_FAILURE;					\
+	}								\
+}
+
+/* Assert that a pointer is not NULL */
+#define ut_assertnonnull(expr) {					\
+	const void *val = (expr);					\
+									\
+	if (val == NULL) {						\
+		ut_failf(uts, __FILE__, __LINE__, __func__,		\
+			 #expr " = NULL",				\
+			 "Expected non-null, got NULL");		\
+		return CMD_RET_FAILURE;					\
+	}								\
+}
+
+/* Assert that a pointer is not an error pointer */
+#define ut_assertok_ptr(expr) {						\
+	const void *val = (expr);					\
+									\
+	if (IS_ERR(val)) {						\
+		ut_failf(uts, __FILE__, __LINE__, __func__,		\
+			 #expr " = NULL",				\
+			 "Expected pointer, got error %ld",		\
+			 PTR_ERR(val));					\
+		return CMD_RET_FAILURE;					\
+	}								\
+}
+
+/* Assert that an operation succeeds (returns 0) */
+#define ut_assertok(cond)	ut_asserteq(0, cond)
+
+#endif
diff --git a/include/thermal.h b/include/thermal.h
new file mode 100644
index 0000000..11d7525
--- /dev/null
+++ b/include/thermal.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *
+ * (C) Copyright 2014 Freescale Semiconductor, Inc
+ */
+
+#ifndef _THERMAL_H_
+#define _THERMAL_H_
+
+#include <dm.h>
+
+int thermal_get_temp(struct udevice *dev, int *temp);
+
+/**
+ * struct dm_thermal_ops - Driver model Thermal operations
+ *
+ * The uclass interface is implemented by all Thermal devices which use
+ * driver model.
+ */
+struct dm_thermal_ops {
+	/**
+	 * Get the current temperature
+	 *
+	 * This must be called before doing any transfers with a Thermal device.
+	 * It will enable and initialize any Thermal hardware as necessary.
+	 *
+	 * @dev:	The Thermal device
+	 * @temp:	pointer that returns the measured temperature
+	 */
+	int (*get_temp)(struct udevice *dev, int *temp);
+};
+
+#endif	/* _THERMAL_H_ */
diff --git a/include/thor.h b/include/thor.h
new file mode 100644
index 0000000..62501bd
--- /dev/null
+++ b/include/thor.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * thor.h -- USB THOR Downloader protocol
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Lukasz Majewski  <l.majewski@samsung.com>
+ *
+ */
+
+#ifndef __THOR_H_
+#define __THOR_H_
+
+#include <linux/usb/composite.h>
+
+int thor_handle(void);
+int thor_init(void);
+int thor_add(struct usb_configuration *c);
+#endif /* __THOR_H_ */
diff --git a/include/ti-usb-phy-uboot.h b/include/ti-usb-phy-uboot.h
new file mode 100644
index 0000000..cd2ba40
--- /dev/null
+++ b/include/ti-usb-phy-uboot.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* include/ti_usb_phy_uboot.h
+ *
+ * Copyright (c) 2014 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * USB2 and USB3 PHY uboot init
+ */
+
+#ifndef __TI_USB_PHY_UBOOT_H_
+#define __TI_USB_PHY_UBOOT_H_
+
+struct ti_usb_phy_device {
+	void *pll_ctrl_base;
+	void *usb2_phy_power;
+	void *usb3_phy_power;
+	int index;
+};
+
+int ti_usb_phy_uboot_init(struct ti_usb_phy_device *dev);
+void ti_usb_phy_uboot_exit(int index);
+#endif /* __TI_USB_PHY_UBOOT_H_ */
diff --git a/include/time.h b/include/time.h
new file mode 100644
index 0000000..1e9b369
--- /dev/null
+++ b/include/time.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _TIME_H
+#define _TIME_H
+
+#include <linux/typecheck.h>
+#include <linux/types.h>
+
+unsigned long get_timer(unsigned long base);
+
+/*
+ * Return the current value of a monotonically increasing microsecond timer.
+ * Granularity may be larger than 1us if hardware does not support this.
+ */
+unsigned long timer_get_us(void);
+
+/*
+ * timer_test_add_offset()
+ *
+ * Allow tests to add to the time reported through lib/time.c functions
+ * offset: number of milliseconds to advance the system time
+ */
+void timer_test_add_offset(unsigned long offset);
+
+/**
+ * usec_to_tick() - convert microseconds to clock ticks
+ *
+ * @usec:	duration in microseconds
+ * Return:	duration in clock ticks
+ */
+uint64_t usec_to_tick(unsigned long usec);
+
+/*
+ *	These inlines deal with timer wrapping correctly. You are
+ *	strongly encouraged to use them
+ *	1. Because people otherwise forget
+ *	2. Because if the timer wrap changes in future you won't have to
+ *	   alter your driver code.
+ *
+ * time_after(a,b) returns true if the time a is after time b.
+ *
+ * Do this with "<0" and ">=0" to only test the sign of the result. A
+ * good compiler would generate better code (and a really good compiler
+ * wouldn't care). Gcc is currently neither.
+ */
+#define time_after(a,b)		\
+	(typecheck(unsigned long, a) && \
+	 typecheck(unsigned long, b) && \
+	 ((long)((b) - (a)) < 0))
+#define time_before(a,b)	time_after(b,a)
+
+#define time_after_eq(a,b)	\
+	(typecheck(unsigned long, a) && \
+	 typecheck(unsigned long, b) && \
+	 ((long)((a) - (b)) >= 0))
+#define time_before_eq(a,b)	time_after_eq(b,a)
+
+/*
+ * Calculate whether a is in the range of [b, c].
+ */
+#define time_in_range(a,b,c) \
+	(time_after_eq(a,b) && \
+	 time_before_eq(a,c))
+
+/*
+ * Calculate whether a is in the range of [b, c).
+ */
+#define time_in_range_open(a,b,c) \
+	(time_after_eq(a,b) && \
+	 time_before(a,c))
+
+#endif /* _TIME_H */
diff --git a/include/timer.h b/include/timer.h
new file mode 100644
index 0000000..a49b500
--- /dev/null
+++ b/include/timer.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
+ */
+
+#ifndef _TIMER_H_
+#define _TIMER_H_
+
+/*
+ * dm_timer_init - initialize a timer for time keeping. On success
+ * initializes gd->timer so that lib/timer can use it for future
+ * referrence.
+ *
+ * @return - 0 on success or error number
+ */
+int dm_timer_init(void);
+
+/*
+ * timer_conv_64 - convert 32-bit counter value to 64-bit
+ *
+ * @count: 32-bit counter value
+ * @return: 64-bit counter value
+ */
+u64 timer_conv_64(u32 count);
+
+/*
+ * Get the current timer count
+ *
+ * @dev: The timer device
+ * @count: pointer that returns the current timer count
+ * @return: 0 if OK, -ve on error
+ */
+int timer_get_count(struct udevice *dev, u64 *count);
+
+/*
+ * Get the timer input clock frequency
+ *
+ * @dev: The timer device
+ * @return: the timer input clock frequency
+ */
+unsigned long timer_get_rate(struct udevice *dev);
+
+/*
+ * struct timer_ops - Driver model timer operations
+ *
+ * The uclass interface is implemented by all timer devices which use
+ * driver model.
+ */
+struct timer_ops {
+	/*
+	 * Get the current timer count
+	 *
+	 * @dev: The timer device
+	 * @count: pointer that returns the current 64-bit timer count
+	 * @return: 0 if OK, -ve on error
+	 */
+	int (*get_count)(struct udevice *dev, u64 *count);
+};
+
+/*
+ * struct timer_dev_priv - information about a device used by the uclass
+ *
+ * @clock_rate: the timer input clock frequency
+ */
+struct timer_dev_priv {
+	unsigned long clock_rate;
+};
+
+/**
+ * timer_early_get_count() - Implement timer_get_count() before driver model
+ *
+ * If CONFIG_TIMER_EARLY is enabled, this function wil be called to return
+ * the current timer value before the proper driver model timer is ready.
+ * It should be implemented by one of the timer values. This is mostly useful
+ * for tracing.
+ */
+u64 timer_early_get_count(void);
+
+/**
+ * timer_early_get_rate() - Get the timer rate before driver model
+ *
+ * If CONFIG_TIMER_EARLY is enabled, this function wil be called to return
+ * the current timer rate in Hz before the proper driver model timer is ready.
+ * It should be implemented by one of the timer values. This is mostly useful
+ * for tracing. This corresponds to the clock_rate value in struct
+ * timer_dev_priv.
+ */
+unsigned long timer_early_get_rate(void);
+
+#endif	/* _TIMER_H_ */
diff --git a/include/timestamp.h b/include/timestamp.h
new file mode 100644
index 0000000..643a5a4
--- /dev/null
+++ b/include/timestamp.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ */
+
+#ifndef	__TIMESTAMP_H__
+#define	__TIMESTAMP_H__
+
+#ifndef DO_DEPS_ONLY
+#include "generated/timestamp_autogenerated.h"
+#endif
+
+#endif	/* __TIMESTAMP_H__ */
diff --git a/include/tmu.h b/include/tmu.h
new file mode 100644
index 0000000..da07a22
--- /dev/null
+++ b/include/tmu.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *      http://www.samsung.com
+ * Akshay Saraswat <akshay.s@samsung.com>
+ *
+ * Thermal Management Unit
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TMU_H
+#define _TMU_H
+
+enum tmu_status_t {
+	TMU_STATUS_INIT = -1,
+	TMU_STATUS_NORMAL = 0,
+	TMU_STATUS_WARNING,
+	TMU_STATUS_TRIPPED,
+};
+
+/*
+ * Monitors status of the TMU device and exynos temperature
+ *
+ * @param temp	pointer to the current temperature value
+ * @return	enum tmu_status_t value, code indicating event to execute
+ *		and -1 on error
+ */
+enum tmu_status_t tmu_monitor(int *temp);
+
+/*
+ * Initialize TMU device
+ *
+ * @param blob  FDT blob
+ * @return	int value, 0 for success
+ */
+int tmu_init(const void *blob);
+#endif	/* _THERMAL_H_ */
diff --git a/include/tpm-common.h b/include/tpm-common.h
new file mode 100644
index 0000000..f9c2ca2
--- /dev/null
+++ b/include/tpm-common.h
@@ -0,0 +1,296 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ * Coypright (c) 2013 Guntermann & Drunck GmbH
+ */
+
+#ifndef __TPM_COMMON_H
+#define __TPM_COMMON_H
+
+enum tpm_duration {
+	TPM_SHORT = 0,
+	TPM_MEDIUM = 1,
+	TPM_LONG = 2,
+	TPM_UNDEFINED,
+
+	TPM_DURATION_COUNT,
+};
+
+/*
+ * Here is a partial implementation of TPM commands.  Please consult TCG Main
+ * Specification for definitions of TPM commands.
+ */
+
+#define TPM_HEADER_SIZE		10
+
+/* Max buffer size supported by our tpm */
+#define TPM_DEV_BUFSIZE		1260
+
+#define TPM_PCR_MINIMUM_DIGEST_SIZE 20
+
+/**
+ * enum tpm_version - The version of the TPM stack to be used
+ * @TPM_V1:		Use TPM v1.x stack
+ * @TPM_V2:		Use TPM v2.x stack
+ */
+enum tpm_version {
+	TPM_V1 = 0,
+	TPM_V2,
+};
+
+/**
+ * struct tpm_chip_priv - Information about a TPM, stored by the uclass
+ *
+ * These values must be set up by the device's probe() method before
+ * communcation is attempted. If the device has an xfer() method, this is
+ * not needed. There is no need to set up @buf.
+ *
+ * @version:		TPM stack to be used
+ * @duration_ms:	Length of each duration type in milliseconds
+ * @retry_time_ms:	Time to wait before retrying receive
+ * @buf:		Buffer used during the exchanges with the chip
+ * @pcr_count:		Number of PCR per bank
+ * @pcr_select_min:	Minimum size in bytes of the pcrSelect array
+ */
+struct tpm_chip_priv {
+	enum tpm_version version;
+
+	uint duration_ms[TPM_DURATION_COUNT];
+	uint retry_time_ms;
+	u8 buf[TPM_DEV_BUFSIZE + sizeof(u8)];  /* Max buffer size + addr */
+
+	/* TPM v2 specific data */
+	uint pcr_count;
+	uint pcr_select_min;
+};
+
+/**
+ * struct tpm_ops - low-level TPM operations
+ *
+ * These are designed to avoid loops and delays in the driver itself. These
+ * should be handled in the uclass.
+ *
+ * In gneral you should implement everything except xfer(). Where you need
+ * complete control of the transfer, then xfer() can be provided and will
+ * override the other methods.
+ *
+ * This interface is for low-level TPM access. It does not understand the
+ * concept of localities or the various TPM messages. That interface is
+ * defined in the functions later on in this file, but they all translate
+ * to bytes which are sent and received.
+ */
+struct tpm_ops {
+	/**
+	 * open() - Request access to locality 0 for the caller
+	 *
+	 * After all commands have been completed the caller should call
+	 * close().
+	 *
+	 * @dev:	Device to open
+	 * @return 0 ok OK, -ve on error
+	 */
+	int (*open)(struct udevice *dev);
+
+	/**
+	 * close() - Close the current session
+	 *
+	 * Releasing the locked locality. Returns 0 on success, -ve 1 on
+	 * failure (in case lock removal did not succeed).
+	 *
+	 * @dev:	Device to close
+	 * @return 0 ok OK, -ve on error
+	 */
+	int (*close)(struct udevice *dev);
+
+	/**
+	 * get_desc() - Get a text description of the TPM
+	 *
+	 * @dev:	Device to check
+	 * @buf:	Buffer to put the string
+	 * @size:	Maximum size of buffer
+	 * @return length of string, or -ENOSPC it no space
+	 */
+	int (*get_desc)(struct udevice *dev, char *buf, int size);
+
+	/**
+	 * send() - send data to the TPM
+	 *
+	 * @dev:	Device to talk to
+	 * @sendbuf:	Buffer of the data to send
+	 * @send_size:	Size of the data to send
+	 *
+	 * Returns 0 on success or -ve on failure.
+	 */
+	int (*send)(struct udevice *dev, const u8 *sendbuf, size_t send_size);
+
+	/**
+	 * recv() - receive a response from the TPM
+	 *
+	 * @dev:	Device to talk to
+	 * @recvbuf:	Buffer to save the response to
+	 * @max_size:	Maximum number of bytes to receive
+	 *
+	 * Returns number of bytes received on success, -EAGAIN if the TPM
+	 * response is not ready, -EINTR if cancelled, or other -ve value on
+	 * failure.
+	 */
+	int (*recv)(struct udevice *dev, u8 *recvbuf, size_t max_size);
+
+	/**
+	 * cleanup() - clean up after an operation in progress
+	 *
+	 * This is called if receiving times out. The TPM may need to abort
+	 * the current transaction if it did not complete, and make itself
+	 * ready for another.
+	 *
+	 * @dev:	Device to talk to
+	 */
+	int (*cleanup)(struct udevice *dev);
+
+	/**
+	 * xfer() - send data to the TPM and get response
+	 *
+	 * This method is optional. If it exists it is used in preference
+	 * to send(), recv() and cleanup(). It should handle all aspects of
+	 * TPM communication for a single transfer.
+	 *
+	 * @dev:	Device to talk to
+	 * @sendbuf:	Buffer of the data to send
+	 * @send_size:	Size of the data to send
+	 * @recvbuf:	Buffer to save the response to
+	 * @recv_size:	Pointer to the size of the response buffer
+	 *
+	 * Returns 0 on success (and places the number of response bytes at
+	 * recv_size) or -ve on failure.
+	 */
+	int (*xfer)(struct udevice *dev, const u8 *sendbuf, size_t send_size,
+		    u8 *recvbuf, size_t *recv_size);
+};
+
+#define tpm_get_ops(dev)        ((struct tpm_ops *)device_get_ops(dev))
+
+#define MAKE_TPM_CMD_ENTRY(cmd) \
+	U_BOOT_CMD_MKENT(cmd, 0, 1, do_tpm_ ## cmd, "", "")
+
+#define TPM_COMMAND_NO_ARG(cmd)				\
+int do_##cmd(cmd_tbl_t *cmdtp, int flag,		\
+	     int argc, char * const argv[])		\
+{							\
+	struct udevice *dev;				\
+	int rc;						\
+							\
+	rc = get_tpm(&dev);				\
+	if (rc)						\
+		return rc;				\
+	if (argc != 1)					\
+		return CMD_RET_USAGE;			\
+	return report_return_code(cmd(dev));		\
+}
+
+/**
+ * tpm_open() - Request access to locality 0 for the caller
+ *
+ * After all commands have been completed the caller is supposed to
+ * call tpm_close().
+ *
+ * @dev - TPM device
+ * Returns 0 on success, -ve on failure.
+ */
+int tpm_open(struct udevice *dev);
+
+/**
+ * tpm_close() - Close the current session
+ *
+ * Releasing the locked locality. Returns 0 on success, -ve 1 on
+ * failure (in case lock removal did not succeed).
+ *
+ * @dev - TPM device
+ * Returns 0 on success, -ve on failure.
+ */
+int tpm_close(struct udevice *dev);
+
+/**
+ * tpm_clear_and_reenable() - Force clear the TPM and reenable it
+ *
+ * @dev: TPM device
+ * @return 0 on success, -ve on failure
+ */
+u32 tpm_clear_and_reenable(struct udevice *dev);
+
+/**
+ * tpm_get_desc() - Get a text description of the TPM
+ *
+ * @dev:	Device to check
+ * @buf:	Buffer to put the string
+ * @size:	Maximum size of buffer
+ * @return length of string, or -ENOSPC it no space
+ */
+int tpm_get_desc(struct udevice *dev, char *buf, int size);
+
+/**
+ * tpm_xfer() - send data to the TPM and get response
+ *
+ * This first uses the device's send() method to send the bytes. Then it calls
+ * recv() to get the reply. If recv() returns -EAGAIN then it will delay a
+ * short time and then call recv() again.
+ *
+ * Regardless of whether recv() completes successfully, it will then call
+ * cleanup() to finish the transaction.
+ *
+ * Note that the outgoing data is inspected to determine command type
+ * (ordinal) and a timeout is used for that command type.
+ *
+ * @dev - TPM device
+ * @sendbuf - buffer of the data to send
+ * @send_size size of the data to send
+ * @recvbuf - memory to save the response to
+ * @recv_len - pointer to the size of the response buffer
+ *
+ * Returns 0 on success (and places the number of response bytes at
+ * recv_len) or -ve on failure.
+ */
+int tpm_xfer(struct udevice *dev, const u8 *sendbuf, size_t send_size,
+	     u8 *recvbuf, size_t *recv_size);
+
+/**
+ * Initialize TPM device.  It must be called before any TPM commands.
+ *
+ * @dev - TPM device
+ * @return 0 on success, non-0 on error.
+ */
+int tpm_init(struct udevice *dev);
+
+/**
+ * Retrieve the array containing all the v1 (resp. v2) commands.
+ *
+ * @return a cmd_tbl_t array.
+ */
+#if defined(CONFIG_TPM_V1)
+cmd_tbl_t *get_tpm1_commands(unsigned int *size);
+#else
+static inline cmd_tbl_t *get_tpm1_commands(unsigned int *size)
+{
+	return NULL;
+}
+#endif
+#if defined(CONFIG_TPM_V2)
+cmd_tbl_t *get_tpm2_commands(unsigned int *size);
+#else
+static inline cmd_tbl_t *get_tpm2_commands(unsigned int *size)
+{
+	return NULL;
+}
+#endif
+
+/**
+ * tpm_get_version() - Find the version of a TPM
+ *
+ * This checks the uclass data for a TPM device and returns the version number
+ * it supports.
+ *
+ * @dev: TPM device
+ * @return version number (TPM_V1 or TPMV2)
+ */
+enum tpm_version tpm_get_version(struct udevice *dev);
+
+#endif /* __TPM_COMMON_H */
diff --git a/include/tpm-v1.h b/include/tpm-v1.h
new file mode 100644
index 0000000..45b7a48
--- /dev/null
+++ b/include/tpm-v1.h
@@ -0,0 +1,591 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ * Coypright (c) 2013 Guntermann & Drunck GmbH
+ */
+
+#ifndef __TPM_V1_H
+#define __TPM_V1_H
+
+#include <tpm-common.h>
+
+/* Useful constants */
+enum {
+	TPM_REQUEST_HEADER_LENGTH	= 10,
+	TPM_RESPONSE_HEADER_LENGTH	= 10,
+	PCR_DIGEST_LENGTH		= 20,
+	DIGEST_LENGTH			= 20,
+	TPM_REQUEST_AUTH_LENGTH		= 45,
+	TPM_RESPONSE_AUTH_LENGTH	= 41,
+	/* some max lengths, valid for RSA keys <= 2048 bits */
+	TPM_KEY12_MAX_LENGTH		= 618,
+	TPM_PUBKEY_MAX_LENGTH		= 288,
+};
+
+enum tpm_startup_type {
+	TPM_ST_CLEAR		= 0x0001,
+	TPM_ST_STATE		= 0x0002,
+	TPM_ST_DEACTIVATED	= 0x0003,
+};
+
+enum tpm_physical_presence {
+	TPM_PHYSICAL_PRESENCE_HW_DISABLE	= 0x0200,
+	TPM_PHYSICAL_PRESENCE_CMD_DISABLE	= 0x0100,
+	TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK	= 0x0080,
+	TPM_PHYSICAL_PRESENCE_HW_ENABLE		= 0x0040,
+	TPM_PHYSICAL_PRESENCE_CMD_ENABLE	= 0x0020,
+	TPM_PHYSICAL_PRESENCE_NOTPRESENT	= 0x0010,
+	TPM_PHYSICAL_PRESENCE_PRESENT		= 0x0008,
+	TPM_PHYSICAL_PRESENCE_LOCK		= 0x0004,
+};
+
+enum tpm_nv_index {
+	TPM_NV_INDEX_LOCK	= 0xffffffff,
+	TPM_NV_INDEX_0		= 0x00000000,
+	TPM_NV_INDEX_DIR	= 0x10000001,
+};
+
+enum tpm_resource_type {
+	TPM_RT_KEY	= 0x00000001,
+	TPM_RT_AUTH	= 0x00000002,
+	TPM_RT_HASH	= 0x00000003,
+	TPM_RT_TRANS	= 0x00000004,
+	TPM_RT_CONTEXT	= 0x00000005,
+	TPM_RT_COUNTER	= 0x00000006,
+	TPM_RT_DELEGATE	= 0x00000007,
+	TPM_RT_DAA_TPM	= 0x00000008,
+	TPM_RT_DAA_V0	= 0x00000009,
+	TPM_RT_DAA_V1	= 0x0000000A,
+};
+
+enum tpm_capability_areas {
+	TPM_CAP_ORD		= 0x00000001,
+	TPM_CAP_ALG		= 0x00000002,
+	TPM_CAP_PID		= 0x00000003,
+	TPM_CAP_FLAG		= 0x00000004,
+	TPM_CAP_PROPERTY	= 0x00000005,
+	TPM_CAP_VERSION		= 0x00000006,
+	TPM_CAP_KEY_HANDLE	= 0x00000007,
+	TPM_CAP_CHECK_LOADED	= 0x00000008,
+	TPM_CAP_SYM_MODE	= 0x00000009,
+	TPM_CAP_KEY_STATUS	= 0x0000000C,
+	TPM_CAP_NV_LIST		= 0x0000000D,
+	TPM_CAP_MFR		= 0x00000010,
+	TPM_CAP_NV_INDEX	= 0x00000011,
+	TPM_CAP_TRANS_ALG	= 0x00000012,
+	TPM_CAP_HANDLE		= 0x00000014,
+	TPM_CAP_TRANS_ES	= 0x00000015,
+	TPM_CAP_AUTH_ENCRYPT	= 0x00000017,
+	TPM_CAP_SELECT_SIZE	= 0x00000018,
+	TPM_CAP_DA_LOGIC	= 0x00000019,
+	TPM_CAP_VERSION_VAL	= 0x0000001A,
+};
+
+enum tmp_cap_flag {
+	TPM_CAP_FLAG_PERMANENT	= 0x108,
+};
+
+#define TPM_TAG_PERMANENT_FLAGS		0x001f
+
+#define TPM_NV_PER_GLOBALLOCK		BIT(15)
+#define TPM_NV_PER_PPREAD		BIT(16)
+#define TPM_NV_PER_PPWRITE		BIT(0)
+#define TPM_NV_PER_READ_STCLEAR		BIT(31)
+#define TPM_NV_PER_WRITE_STCLEAR	BIT(14)
+#define TPM_NV_PER_WRITEDEFINE		BIT(13)
+#define TPM_NV_PER_WRITEALL		BIT(12)
+
+enum {
+	TPM_PUBEK_SIZE			= 256,
+};
+
+enum {
+	TPM_CMD_EXTEND			= 0x14,
+	TPM_CMD_GET_CAPABILITY		= 0x65,
+	TPM_CMD_NV_DEFINE_SPACE		= 0xcc,
+	TPM_CMD_NV_WRITE_VALUE		= 0xcd,
+	TPM_CMD_NV_READ_VALUE		= 0xcf,
+};
+
+/**
+ * TPM return codes as defined in the TCG Main specification
+ * (TPM Main Part 2 Structures; Specification version 1.2)
+ */
+enum tpm_return_code {
+	TPM_BASE	= 0x00000000,
+	TPM_NON_FATAL	= 0x00000800,
+	TPM_SUCCESS	= TPM_BASE,
+	/* TPM-defined fatal error codes */
+	TPM_AUTHFAIL			= TPM_BASE +  1,
+	TPM_BADINDEX			= TPM_BASE +  2,
+	TPM_BAD_PARAMETER		= TPM_BASE +  3,
+	TPM_AUDITFAILURE		= TPM_BASE +  4,
+	TPM_CLEAR_DISABLED		= TPM_BASE +  5,
+	TPM_DEACTIVATED			= TPM_BASE +  6,
+	TPM_DISABLED			= TPM_BASE +  7,
+	TPM_DISABLED_CMD		= TPM_BASE +  8,
+	TPM_FAIL			= TPM_BASE +  9,
+	TPM_BAD_ORDINAL			= TPM_BASE + 10,
+	TPM_INSTALL_DISABLED		= TPM_BASE + 11,
+	TPM_INVALID_KEYHANDLE		= TPM_BASE + 12,
+	TPM_KEYNOTFOUND			= TPM_BASE + 13,
+	TPM_INAPPROPRIATE_ENC		= TPM_BASE + 14,
+	TPM_MIGRATE_FAIL		= TPM_BASE + 15,
+	TPM_INVALID_PCR_INFO		= TPM_BASE + 16,
+	TPM_NOSPACE			= TPM_BASE + 17,
+	TPM_NOSRK			= TPM_BASE + 18,
+	TPM_NOTSEALED_BLOB		= TPM_BASE + 19,
+	TPM_OWNER_SET			= TPM_BASE + 20,
+	TPM_RESOURCES			= TPM_BASE + 21,
+	TPM_SHORTRANDOM			= TPM_BASE + 22,
+	TPM_SIZE			= TPM_BASE + 23,
+	TPM_WRONGPCRVAL			= TPM_BASE + 24,
+	TPM_BAD_PARAM_SIZE		= TPM_BASE + 25,
+	TPM_SHA_THREAD			= TPM_BASE + 26,
+	TPM_SHA_ERROR			= TPM_BASE + 27,
+	TPM_FAILEDSELFTEST		= TPM_BASE + 28,
+	TPM_AUTH2FAIL			= TPM_BASE + 29,
+	TPM_BADTAG			= TPM_BASE + 30,
+	TPM_IOERROR			= TPM_BASE + 31,
+	TPM_ENCRYPT_ERROR		= TPM_BASE + 32,
+	TPM_DECRYPT_ERROR		= TPM_BASE + 33,
+	TPM_INVALID_AUTHHANDLE		= TPM_BASE + 34,
+	TPM_NO_ENDORSEMENT		= TPM_BASE + 35,
+	TPM_INVALID_KEYUSAGE		= TPM_BASE + 36,
+	TPM_WRONG_ENTITYTYPE		= TPM_BASE + 37,
+	TPM_INVALID_POSTINIT		= TPM_BASE + 38,
+	TPM_INAPPROPRIATE_SIG		= TPM_BASE + 39,
+	TPM_BAD_KEY_PROPERTY		= TPM_BASE + 40,
+	TPM_BAD_MIGRATION		= TPM_BASE + 41,
+	TPM_BAD_SCHEME			= TPM_BASE + 42,
+	TPM_BAD_DATASIZE		= TPM_BASE + 43,
+	TPM_BAD_MODE			= TPM_BASE + 44,
+	TPM_BAD_PRESENCE		= TPM_BASE + 45,
+	TPM_BAD_VERSION			= TPM_BASE + 46,
+	TPM_NO_WRAP_TRANSPORT		= TPM_BASE + 47,
+	TPM_AUDITFAIL_UNSUCCESSFUL	= TPM_BASE + 48,
+	TPM_AUDITFAIL_SUCCESSFUL	= TPM_BASE + 49,
+	TPM_NOTRESETABLE		= TPM_BASE + 50,
+	TPM_NOTLOCAL			= TPM_BASE + 51,
+	TPM_BAD_TYPE			= TPM_BASE + 52,
+	TPM_INVALID_RESOURCE		= TPM_BASE + 53,
+	TPM_NOTFIPS			= TPM_BASE + 54,
+	TPM_INVALID_FAMILY		= TPM_BASE + 55,
+	TPM_NO_NV_PERMISSION		= TPM_BASE + 56,
+	TPM_REQUIRES_SIGN		= TPM_BASE + 57,
+	TPM_KEY_NOTSUPPORTED		= TPM_BASE + 58,
+	TPM_AUTH_CONFLICT		= TPM_BASE + 59,
+	TPM_AREA_LOCKED			= TPM_BASE + 60,
+	TPM_BAD_LOCALITY		= TPM_BASE + 61,
+	TPM_READ_ONLY			= TPM_BASE + 62,
+	TPM_PER_NOWRITE			= TPM_BASE + 63,
+	TPM_FAMILY_COUNT		= TPM_BASE + 64,
+	TPM_WRITE_LOCKED		= TPM_BASE + 65,
+	TPM_BAD_ATTRIBUTES		= TPM_BASE + 66,
+	TPM_INVALID_STRUCTURE		= TPM_BASE + 67,
+	TPM_KEY_OWNER_CONTROL		= TPM_BASE + 68,
+	TPM_BAD_COUNTER			= TPM_BASE + 69,
+	TPM_NOT_FULLWRITE		= TPM_BASE + 70,
+	TPM_CONTEXT_GAP			= TPM_BASE + 71,
+	TPM_MAXNVWRITES			= TPM_BASE + 72,
+	TPM_NOOPERATOR			= TPM_BASE + 73,
+	TPM_RESOURCEMISSING		= TPM_BASE + 74,
+	TPM_DELEGATE_LOCK		= TPM_BASE + 75,
+	TPM_DELEGATE_FAMILY		= TPM_BASE + 76,
+	TPM_DELEGATE_ADMIN		= TPM_BASE + 77,
+	TPM_TRANSPORT_NOTEXCLUSIVE	= TPM_BASE + 78,
+	TPM_OWNER_CONTROL		= TPM_BASE + 79,
+	TPM_DAA_RESOURCES		= TPM_BASE + 80,
+	TPM_DAA_INPUT_DATA0		= TPM_BASE + 81,
+	TPM_DAA_INPUT_DATA1		= TPM_BASE + 82,
+	TPM_DAA_ISSUER_SETTINGS		= TPM_BASE + 83,
+	TPM_DAA_TPM_SETTINGS		= TPM_BASE + 84,
+	TPM_DAA_STAGE			= TPM_BASE + 85,
+	TPM_DAA_ISSUER_VALIDITY		= TPM_BASE + 86,
+	TPM_DAA_WRONG_W			= TPM_BASE + 87,
+	TPM_BAD_HANDLE			= TPM_BASE + 88,
+	TPM_BAD_DELEGATE		= TPM_BASE + 89,
+	TPM_BADCONTEXT			= TPM_BASE + 90,
+	TPM_TOOMANYCONTEXTS		= TPM_BASE + 91,
+	TPM_MA_TICKET_SIGNATURE		= TPM_BASE + 92,
+	TPM_MA_DESTINATION		= TPM_BASE + 93,
+	TPM_MA_SOURCE			= TPM_BASE + 94,
+	TPM_MA_AUTHORITY		= TPM_BASE + 95,
+	TPM_PERMANENTEK			= TPM_BASE + 97,
+	TPM_BAD_SIGNATURE		= TPM_BASE + 98,
+	TPM_NOCONTEXTSPACE		= TPM_BASE + 99,
+	/* TPM-defined non-fatal errors */
+	TPM_RETRY		= TPM_BASE + TPM_NON_FATAL,
+	TPM_NEEDS_SELFTEST	= TPM_BASE + TPM_NON_FATAL + 1,
+	TPM_DOING_SELFTEST	= TPM_BASE + TPM_NON_FATAL + 2,
+	TPM_DEFEND_LOCK_RUNNING	= TPM_BASE + TPM_NON_FATAL + 3,
+};
+
+struct tpm_permanent_flags {
+	__be16	tag;
+	u8	disable;
+	u8	ownership;
+	u8	deactivated;
+	u8	read_pubek;
+	u8	disable_owner_clear;
+	u8	allow_maintenance;
+	u8	physical_presence_lifetime_lock;
+	u8	physical_presence_hw_enable;
+	u8	physical_presence_cmd_enable;
+	u8	cekp_used;
+	u8	tpm_post;
+	u8	tpm_post_lock;
+	u8	fips;
+	u8	operator;
+	u8	enable_revoke_ek;
+	u8	nv_locked;
+	u8	read_srk_pub;
+	u8	tpm_established;
+	u8	maintenance_done;
+	u8	disable_full_da_logic_info;
+} __packed;
+
+#define TPM_SHA1_160_HASH_LEN	0x14
+
+struct __packed tpm_composite_hash {
+	u8	digest[TPM_SHA1_160_HASH_LEN];
+};
+
+struct __packed tpm_pcr_selection {
+	__be16	size_of_select;
+	u8	pcr_select[3];	/* matches vboot's struct */
+};
+
+struct __packed tpm_pcr_info_short {
+	struct tpm_pcr_selection pcr_selection;
+	u8	locality_at_release;
+	struct tpm_composite_hash digest_at_release;
+};
+
+struct __packed tpm_nv_attributes {
+	__be16	tag;
+	__be32	attributes;
+};
+
+struct __packed tpm_nv_data_public {
+	__be16	tag;
+	__be32	nv_index;
+	struct tpm_pcr_info_short pcr_info_read;
+	struct tpm_pcr_info_short pcr_info_write;
+	struct tpm_nv_attributes permission;
+	u8	read_st_clear;
+	u8	write_st_clear;
+	u8	write_define;
+	__be32	data_size;
+};
+
+/**
+ * Issue a TPM_Startup command.
+ *
+ * @param dev		TPM device
+ * @param mode		TPM startup mode
+ * @return return code of the operation
+ */
+u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode);
+
+/**
+ * Issue a TPM_SelfTestFull command.
+ *
+ * @param dev		TPM device
+ * @return return code of the operation
+ */
+u32 tpm_self_test_full(struct udevice *dev);
+
+/**
+ * Issue a TPM_ContinueSelfTest command.
+ *
+ * @param dev		TPM device
+ * @return return code of the operation
+ */
+u32 tpm_continue_self_test(struct udevice *dev);
+
+/**
+ * Issue a TPM_NV_DefineSpace command.  The implementation is limited
+ * to specify TPM_NV_ATTRIBUTES and size of the area.  The area index
+ * could be one of the special value listed in enum tpm_nv_index.
+ *
+ * @param dev		TPM device
+ * @param index		index of the area
+ * @param perm		TPM_NV_ATTRIBUTES of the area
+ * @param size		size of the area
+ * @return return code of the operation
+ */
+u32 tpm_nv_define_space(struct udevice *dev, u32 index, u32 perm, u32 size);
+
+/**
+ * Issue a TPM_NV_ReadValue command.  This implementation is limited
+ * to read the area from offset 0.  The area index could be one of
+ * the special value listed in enum tpm_nv_index.
+ *
+ * @param dev		TPM device
+ * @param index		index of the area
+ * @param data		output buffer of the area contents
+ * @param count		size of output buffer
+ * @return return code of the operation
+ */
+u32 tpm_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
+
+/**
+ * Issue a TPM_NV_WriteValue command.  This implementation is limited
+ * to write the area from offset 0.  The area index could be one of
+ * the special value listed in enum tpm_nv_index.
+ *
+ * @param dev		TPM device
+ * @param index		index of the area
+ * @param data		input buffer to be wrote to the area
+ * @param length	length of data bytes of input buffer
+ * @return return code of the operation
+ */
+u32 tpm_nv_write_value(struct udevice *dev, u32 index, const void *data,
+		       u32 length);
+
+/**
+ * Issue a TPM_Extend command.
+ *
+ * @param dev		TPM device
+ * @param index		index of the PCR
+ * @param in_digest	160-bit value representing the event to be
+ *			recorded
+ * @param out_digest	160-bit PCR value after execution of the
+ *			command
+ * @return return code of the operation
+ */
+u32 tpm_extend(struct udevice *dev, u32 index, const void *in_digest,
+	       void *out_digest);
+
+/**
+ * Issue a TPM_PCRRead command.
+ *
+ * @param dev		TPM device
+ * @param index		index of the PCR
+ * @param data		output buffer for contents of the named PCR
+ * @param count		size of output buffer
+ * @return return code of the operation
+ */
+u32 tpm_pcr_read(struct udevice *dev, u32 index, void *data, size_t count);
+
+/**
+ * Issue a TSC_PhysicalPresence command.  TPM physical presence flag
+ * is bit-wise OR'ed of flags listed in enum tpm_physical_presence.
+ *
+ * @param dev		TPM device
+ * @param presence	TPM physical presence flag
+ * @return return code of the operation
+ */
+u32 tpm_tsc_physical_presence(struct udevice *dev, u16 presence);
+
+/**
+ * Issue a TPM_ReadPubek command.
+ *
+ * @param dev		TPM device
+ * @param data		output buffer for the public endorsement key
+ * @param count		size of output buffer
+ * @return return code of the operation
+ */
+u32 tpm_read_pubek(struct udevice *dev, void *data, size_t count);
+
+/**
+ * Issue a TPM_ForceClear command.
+ *
+ * @param dev		TPM device
+ * @return return code of the operation
+ */
+u32 tpm_force_clear(struct udevice *dev);
+
+/**
+ * Issue a TPM_PhysicalEnable command.
+ *
+ * @param dev		TPM device
+ * @return return code of the operation
+ */
+u32 tpm_physical_enable(struct udevice *dev);
+
+/**
+ * Issue a TPM_PhysicalDisable command.
+ *
+ * @param dev		TPM device
+ * @return return code of the operation
+ */
+u32 tpm_physical_disable(struct udevice *dev);
+
+/**
+ * Issue a TPM_PhysicalSetDeactivated command.
+ *
+ * @param dev		TPM device
+ * @param state		boolean state of the deactivated flag
+ * @return return code of the operation
+ */
+u32 tpm_physical_set_deactivated(struct udevice *dev, u8 state);
+
+/**
+ * Issue a TPM_GetCapability command.  This implementation is limited
+ * to query sub_cap index that is 4-byte wide.
+ *
+ * @param dev		TPM device
+ * @param cap_area	partition of capabilities
+ * @param sub_cap	further definition of capability, which is
+ *			limited to be 4-byte wide
+ * @param cap		output buffer for capability information
+ * @param count		size of output buffer
+ * @return return code of the operation
+ */
+u32 tpm_get_capability(struct udevice *dev, u32 cap_area, u32 sub_cap,
+		       void *cap, size_t count);
+
+/**
+ * Issue a TPM_FlushSpecific command for a AUTH resource.
+ *
+ * @param dev		TPM device
+ * @param auth_handle	handle of the auth session
+ * @return return code of the operation
+ */
+u32 tpm_terminate_auth_session(struct udevice *dev, u32 auth_handle);
+
+/**
+ * Issue a TPM_OIAP command to setup an object independent authorization
+ * session.
+ * Information about the session is stored internally.
+ * If there was already an OIAP session active it is terminated and a new
+ * session is set up.
+ *
+ * @param dev		TPM device
+ * @param auth_handle	pointer to the (new) auth handle or NULL.
+ * @return return code of the operation
+ */
+u32 tpm_oiap(struct udevice *dev, u32 *auth_handle);
+
+/**
+ * Ends an active OIAP session.
+ *
+ * @param dev		TPM device
+ * @return return code of the operation
+ */
+u32 tpm_end_oiap(struct udevice *dev);
+
+/**
+ * Issue a TPM_LoadKey2 (Auth1) command using an OIAP session for authenticating
+ * the usage of the parent key.
+ *
+ * @param dev		TPM device
+ * @param parent_handle	handle of the parent key.
+ * @param key		pointer to the key structure (TPM_KEY or TPM_KEY12).
+ * @param key_length	size of the key structure
+ * @param parent_key_usage_auth	usage auth for the parent key
+ * @param key_handle	pointer to the key handle
+ * @return return code of the operation
+ */
+u32 tpm_load_key2_oiap(struct udevice *dev, u32 parent_handle, const void *key,
+		       size_t key_length, const void *parent_key_usage_auth,
+		       u32 *key_handle);
+
+/**
+ * Issue a TPM_GetPubKey (Auth1) command using an OIAP session for
+ * authenticating the usage of the key.
+ *
+ * @param dev		TPM device
+ * @param key_handle	handle of the key
+ * @param usage_auth	usage auth for the key
+ * @param pubkey	pointer to the pub key buffer; may be NULL if the pubkey
+ *			should not be stored.
+ * @param pubkey_len	pointer to the pub key buffer len. On entry: the size of
+ *			the provided pubkey buffer. On successful exit: the size
+ *			of the stored TPM_PUBKEY structure (iff pubkey != NULL).
+ * @return return code of the operation
+ */
+u32 tpm_get_pub_key_oiap(struct udevice *dev, u32 key_handle,
+			 const void *usage_auth, void *pubkey,
+			 size_t *pubkey_len);
+
+/**
+ * Get the TPM permanent flags value
+ *
+ * @param dev		TPM device
+ * @param pflags	Place to put permanent flags
+ * @return return code of the operation
+ */
+u32 tpm_get_permanent_flags(struct udevice *dev,
+			    struct tpm_permanent_flags *pflags);
+
+/**
+ * Get the TPM permissions
+ *
+ * @param dev		TPM device
+ * @param perm		Returns permissions value
+ * @return return code of the operation
+ */
+u32 tpm_get_permissions(struct udevice *dev, u32 index, u32 *perm);
+
+/**
+ * Flush a resource with a given handle and type from the TPM
+ *
+ * @param dev		TPM device
+ * @param key_handle           handle of the resource
+ * @param resource_type                type of the resource
+ * @return return code of the operation
+ */
+u32 tpm_flush_specific(struct udevice *dev, u32 key_handle, u32 resource_type);
+
+#ifdef CONFIG_TPM_LOAD_KEY_BY_SHA1
+/**
+ * Search for a key by usage AuthData and the hash of the parent's pub key.
+ *
+ * @param dev		TPM device
+ * @param auth	        Usage auth of the key to search for
+ * @param pubkey_digest	SHA1 hash of the pub key structure of the key
+ * @param[out] handle	The handle of the key (Non-null iff found)
+ * @return 0 if key was found in TPM; != 0 if not.
+ */
+u32 tpm_find_key_sha1(struct udevice *dev, const u8 auth[20],
+		      const u8 pubkey_digest[20], u32 *handle);
+#endif /* CONFIG_TPM_LOAD_KEY_BY_SHA1 */
+
+/**
+ * Read random bytes from the TPM RNG. The implementation deals with the fact
+ * that the TPM may legally return fewer bytes than requested by retrying
+ * until @p count bytes have been received.
+ *
+ * @param dev		TPM device
+ * @param data		output buffer for the random bytes
+ * @param count		size of output buffer
+ * @return return code of the operation
+ */
+u32 tpm_get_random(struct udevice *dev, void *data, u32 count);
+
+/**
+ * tpm_finalise_physical_presence() - Finalise physical presence
+ *
+ * @param dev		TPM device
+ * @return return code of the operation (0 = success)
+ */
+u32 tpm_finalise_physical_presence(struct udevice *dev);
+
+/**
+ * tpm_nv_set_locked() - lock the non-volatile space
+ *
+ * @param dev		TPM device
+ * @return return code of the operation (0 = success)
+ */
+u32 tpm_nv_set_locked(struct udevice *dev);
+
+/**
+ * tpm_set_global_lock() - set the global lock
+ *
+ * @param dev		TPM device
+ * @return return code of the operation (0 = success)
+ */
+u32 tpm_set_global_lock(struct udevice *dev);
+
+/**
+ * tpm_resume() - start up the TPM from resume (after suspend)
+ *
+ * @param dev		TPM device
+ * @return return code of the operation (0 = success)
+ */
+u32 tpm_resume(struct udevice *dev);
+
+#endif /* __TPM_V1_H */
diff --git a/include/tpm-v2.h b/include/tpm-v2.h
new file mode 100644
index 0000000..ae00803
--- /dev/null
+++ b/include/tpm-v2.h
@@ -0,0 +1,311 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Bootlin
+ * Author: Miquel Raynal <miquel.raynal@bootlin.com>
+ */
+
+#ifndef __TPM_V2_H
+#define __TPM_V2_H
+
+#include <tpm-common.h>
+
+#define TPM2_DIGEST_LEN		32
+
+/**
+ * TPM2 Structure Tags for command/response buffers.
+ *
+ * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
+ * @TPM2_ST_SESSIONS: the command needs an authentication.
+ */
+enum tpm2_structures {
+	TPM2_ST_NO_SESSIONS	= 0x8001,
+	TPM2_ST_SESSIONS	= 0x8002,
+};
+
+/**
+ * TPM2 type of boolean.
+ */
+enum tpm2_yes_no {
+	TPMI_YES		= 1,
+	TPMI_NO			= 0,
+};
+
+/**
+ * TPM2 startup values.
+ *
+ * @TPM2_SU_CLEAR: reset the internal state.
+ * @TPM2_SU_STATE: restore saved state (if any).
+ */
+enum tpm2_startup_types {
+	TPM2_SU_CLEAR		= 0x0000,
+	TPM2_SU_STATE		= 0x0001,
+};
+
+/**
+ * TPM2 permanent handles.
+ *
+ * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
+ * @TPM2_RS_PW: indicates a password.
+ * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
+ * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
+ * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
+ */
+enum tpm2_handles {
+	TPM2_RH_OWNER		= 0x40000001,
+	TPM2_RS_PW		= 0x40000009,
+	TPM2_RH_LOCKOUT		= 0x4000000A,
+	TPM2_RH_ENDORSEMENT	= 0x4000000B,
+	TPM2_RH_PLATFORM	= 0x4000000C,
+};
+
+/**
+ * TPM2 command codes used at the beginning of a buffer, gives the command.
+ *
+ * @TPM2_CC_STARTUP: TPM2_Startup().
+ * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
+ * @TPM2_CC_CLEAR: TPM2_Clear().
+ * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
+ * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
+ * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
+ * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
+ * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
+ * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
+ * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
+ * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
+ * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
+ */
+enum tpm2_command_codes {
+	TPM2_CC_STARTUP		= 0x0144,
+	TPM2_CC_SELF_TEST	= 0x0143,
+	TPM2_CC_CLEAR		= 0x0126,
+	TPM2_CC_CLEARCONTROL	= 0x0127,
+	TPM2_CC_HIERCHANGEAUTH	= 0x0129,
+	TPM2_CC_PCR_SETAUTHPOL	= 0x012C,
+	TPM2_CC_DAM_RESET	= 0x0139,
+	TPM2_CC_DAM_PARAMETERS	= 0x013A,
+	TPM2_CC_NV_READ         = 0x014E,
+	TPM2_CC_GET_CAPABILITY	= 0x017A,
+	TPM2_CC_PCR_READ	= 0x017E,
+	TPM2_CC_PCR_EXTEND	= 0x0182,
+	TPM2_CC_PCR_SETAUTHVAL	= 0x0183,
+};
+
+/**
+ * TPM2 return codes.
+ */
+enum tpm2_return_codes {
+	TPM2_RC_SUCCESS		= 0x0000,
+	TPM2_RC_BAD_TAG		= 0x001E,
+	TPM2_RC_FMT1		= 0x0080,
+	TPM2_RC_HASH		= TPM2_RC_FMT1 + 0x0003,
+	TPM2_RC_VALUE		= TPM2_RC_FMT1 + 0x0004,
+	TPM2_RC_SIZE		= TPM2_RC_FMT1 + 0x0015,
+	TPM2_RC_BAD_AUTH	= TPM2_RC_FMT1 + 0x0022,
+	TPM2_RC_HANDLE		= TPM2_RC_FMT1 + 0x000B,
+	TPM2_RC_VER1		= 0x0100,
+	TPM2_RC_INITIALIZE	= TPM2_RC_VER1 + 0x0000,
+	TPM2_RC_FAILURE		= TPM2_RC_VER1 + 0x0001,
+	TPM2_RC_DISABLED	= TPM2_RC_VER1 + 0x0020,
+	TPM2_RC_AUTH_MISSING	= TPM2_RC_VER1 + 0x0025,
+	TPM2_RC_COMMAND_CODE	= TPM2_RC_VER1 + 0x0043,
+	TPM2_RC_AUTHSIZE	= TPM2_RC_VER1 + 0x0044,
+	TPM2_RC_AUTH_CONTEXT	= TPM2_RC_VER1 + 0x0045,
+	TPM2_RC_NEEDS_TEST	= TPM2_RC_VER1 + 0x0053,
+	TPM2_RC_WARN		= 0x0900,
+	TPM2_RC_TESTING		= TPM2_RC_WARN + 0x000A,
+	TPM2_RC_REFERENCE_H0	= TPM2_RC_WARN + 0x0010,
+	TPM2_RC_LOCKOUT		= TPM2_RC_WARN + 0x0021,
+};
+
+/**
+ * TPM2 algorithms.
+ */
+enum tpm2_algorithms {
+	TPM2_ALG_XOR		= 0x0A,
+	TPM2_ALG_SHA256		= 0x0B,
+	TPM2_ALG_SHA384		= 0x0C,
+	TPM2_ALG_SHA512		= 0x0D,
+	TPM2_ALG_NULL		= 0x10,
+};
+
+/* NV index attributes */
+enum tpm_index_attrs {
+	TPMA_NV_PPWRITE		= 1UL << 0,
+	TPMA_NV_OWNERWRITE	= 1UL << 1,
+	TPMA_NV_AUTHWRITE	= 1UL << 2,
+	TPMA_NV_POLICYWRITE	= 1UL << 3,
+	TPMA_NV_COUNTER		= 1UL << 4,
+	TPMA_NV_BITS		= 1UL << 5,
+	TPMA_NV_EXTEND		= 1UL << 6,
+	TPMA_NV_POLICY_DELETE	= 1UL << 10,
+	TPMA_NV_WRITELOCKED	= 1UL << 11,
+	TPMA_NV_WRITEALL	= 1UL << 12,
+	TPMA_NV_WRITEDEFINE	= 1UL << 13,
+	TPMA_NV_WRITE_STCLEAR	= 1UL << 14,
+	TPMA_NV_GLOBALLOCK	= 1UL << 15,
+	TPMA_NV_PPREAD		= 1UL << 16,
+	TPMA_NV_OWNERREAD	= 1UL << 17,
+	TPMA_NV_AUTHREAD	= 1UL << 18,
+	TPMA_NV_POLICYREAD	= 1UL << 19,
+	TPMA_NV_NO_DA		= 1UL << 25,
+	TPMA_NV_ORDERLY		= 1UL << 26,
+	TPMA_NV_CLEAR_STCLEAR	= 1UL << 27,
+	TPMA_NV_READLOCKED	= 1UL << 28,
+	TPMA_NV_WRITTEN		= 1UL << 29,
+	TPMA_NV_PLATFORMCREATE	= 1UL << 30,
+	TPMA_NV_READ_STCLEAR	= 1UL << 31,
+
+	TPMA_NV_MASK_READ	= TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
+				TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
+	TPMA_NV_MASK_WRITE	= TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
+					TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
+};
+
+/**
+ * Issue a TPM2_Startup command.
+ *
+ * @dev		TPM device
+ * @mode	TPM startup mode
+ *
+ * @return code of the operation
+ */
+u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
+
+/**
+ * Issue a TPM2_SelfTest command.
+ *
+ * @dev		TPM device
+ * @full_test	Asking to perform all tests or only the untested ones
+ *
+ * @return code of the operation
+ */
+u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
+
+/**
+ * Issue a TPM2_Clear command.
+ *
+ * @dev		TPM device
+ * @handle	Handle
+ * @pw		Password
+ * @pw_sz	Length of the password
+ *
+ * @return code of the operation
+ */
+u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
+	       const ssize_t pw_sz);
+
+/**
+ * Issue a TPM2_PCR_Extend command.
+ *
+ * @dev		TPM device
+ * @index	Index of the PCR
+ * @digest	Value representing the event to be recorded
+ *
+ * @return code of the operation
+ */
+u32 tpm2_pcr_extend(struct udevice *dev, u32 index, const uint8_t *digest);
+
+/**
+ * Issue a TPM2_PCR_Read command.
+ *
+ * @dev		TPM device
+ * @idx		Index of the PCR
+ * @idx_min_sz	Minimum size in bytes of the pcrSelect array
+ * @data	Output buffer for contents of the named PCR
+ * @updates	Optional out parameter: number of updates for this PCR
+ *
+ * @return code of the operation
+ */
+u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
+		  void *data, unsigned int *updates);
+
+/**
+ * Issue a TPM2_GetCapability command.  This implementation is limited
+ * to query property index that is 4-byte wide.
+ *
+ * @dev		TPM device
+ * @capability	Partition of capabilities
+ * @property	Further definition of capability, limited to be 4 bytes wide
+ * @buf		Output buffer for capability information
+ * @prop_count	Size of output buffer
+ *
+ * @return code of the operation
+ */
+u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
+			void *buf, size_t prop_count);
+
+/**
+ * Issue a TPM2_DictionaryAttackLockReset command.
+ *
+ * @dev		TPM device
+ * @pw		Password
+ * @pw_sz	Length of the password
+ *
+ * @return code of the operation
+ */
+u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
+
+/**
+ * Issue a TPM2_DictionaryAttackParameters command.
+ *
+ * @dev		TPM device
+ * @pw		Password
+ * @pw_sz	Length of the password
+ * @max_tries	Count of authorizations before lockout
+ * @recovery_time Time before decrementation of the failure count
+ * @lockout_recovery Time to wait after a lockout
+ *
+ * @return code of the operation
+ */
+u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
+			const ssize_t pw_sz, unsigned int max_tries,
+			unsigned int recovery_time,
+			unsigned int lockout_recovery);
+
+/**
+ * Issue a TPM2_HierarchyChangeAuth command.
+ *
+ * @dev		TPM device
+ * @handle	Handle
+ * @newpw	New password
+ * @newpw_sz	Length of the new password
+ * @oldpw	Old password
+ * @oldpw_sz	Length of the old password
+ *
+ * @return code of the operation
+ */
+int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
+		     const ssize_t newpw_sz, const char *oldpw,
+		     const ssize_t oldpw_sz);
+
+/**
+ * Issue a TPM_PCR_SetAuthPolicy command.
+ *
+ * @dev		TPM device
+ * @pw		Platform password
+ * @pw_sz	Length of the password
+ * @index	Index of the PCR
+ * @digest	New key to access the PCR
+ *
+ * @return code of the operation
+ */
+u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
+			   const ssize_t pw_sz, u32 index, const char *key);
+
+/**
+ * Issue a TPM_PCR_SetAuthValue command.
+ *
+ * @dev		TPM device
+ * @pw		Platform password
+ * @pw_sz	Length of the password
+ * @index	Index of the PCR
+ * @digest	New key to access the PCR
+ * @key_sz	Length of the new key
+ *
+ * @return code of the operation
+ */
+u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
+			  const ssize_t pw_sz, u32 index, const char *key,
+			  const ssize_t key_sz);
+
+#endif /* __TPM_V2_H */
diff --git a/include/tps6586x.h b/include/tps6586x.h
new file mode 100644
index 0000000..785eb39
--- /dev/null
+++ b/include/tps6586x.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _TPS6586X_H_
+#define _TPS6586X_H_
+
+enum {
+	/* SM0-2 PWM/PFM Mode Selection */
+	TPS6586X_PWM_SM0	= 1 << 0,
+	TPS6586X_PWM_SM1	= 1 << 1,
+	TPS6586X_PWM_SM2	= 1 << 2,
+};
+
+/**
+ * Enable PWM mode for selected SM0-2
+ *
+ * @param mask	Mask of synchronous converter to enable (TPS6586X_PWM_...)
+ * @return 0 if ok, -1 on error
+ */
+int tps6586x_set_pwm_mode(int mask);
+
+/**
+ * Adjust SM0 and SM1 voltages to the given targets in incremental steps.
+ *
+ * @param sm0_target	Target voltage for SM0 in 25mW units, 0=725mV, 31=1.5V
+ * @param sm1_target	Target voltage for SM1 in 25mW units, 0=725mV, 31=1.5V
+ * @param step		Amount to change voltage in each step, in 25mW units
+ * @param rate		Slew ratein mV/us: 0=instantly, 1=0.11, 2=0.22,
+ *			3=0.44, 4=0.88, 5=1.76, 6=3.52, 7=7.04
+ * @param min_sm0_over_sm1	Minimum amount by which sm0 must exceed sm1.
+ *			If this condition is not met, no adjustment will be
+ *			done and an error will be reported. Use -1 to skip
+ *			this check.
+ * @return 0 if ok, -1 on error
+ */
+int tps6586x_adjust_sm0_sm1(int sm0_target, int sm1_target, int step, int rate,
+			    int min_sm0_over_sm1);
+
+/**
+ * Set up the TPS6586X I2C bus number. This will be used for all operations
+ * on the device. This function must be called before using other functions.
+ *
+ * @param bus	I2C bus containing the TPS6586X chip
+ * @return 0 (always succeeds)
+ */
+int tps6586x_init(struct udevice *bus);
+
+#endif	/* _TPS6586X_H_ */
diff --git a/include/trace.h b/include/trace.h
new file mode 100644
index 0000000..606dba9
--- /dev/null
+++ b/include/trace.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ */
+
+#ifndef __TRACE_H
+#define __TRACE_H
+
+enum {
+	/*
+	 * This affects the granularity of our trace. We can bin function
+	 * entry points into groups on the basis that functions typically
+	 * have a minimum size, so entry points can't appear any closer
+	 * than this to each other.
+	 *
+	 * The value here assumes a minimum instruction size of 4 bytes,
+	 * or that instructions are 2 bytes but there are at least 2 of
+	 * them in every function.
+	 *
+	 * Increasing this value reduces the number of functions we can
+	 * resolve, but reduces the size of the uintptr_t array used for
+	 * our function list, which is the length of the code divided by
+	 * this value.
+	 */
+	FUNC_SITE_SIZE	= 4,	/* distance between function sites */
+};
+
+enum trace_chunk_type {
+	TRACE_CHUNK_FUNCS,
+	TRACE_CHUNK_CALLS,
+};
+
+/* A trace record for a function, as written to the profile output file */
+struct trace_output_func {
+	uint32_t offset;		/* Function offset into code */
+	uint32_t call_count;		/* Number of times called */
+};
+
+/* A header at the start of the trace output buffer */
+struct trace_output_hdr {
+	enum trace_chunk_type type;	/* Record type */
+	size_t rec_count;		/* Number of records */
+};
+
+/* Print statistics about traced function calls */
+void trace_print_stats(void);
+
+/**
+ * Dump a list of functions and call counts into a buffer
+ *
+ * Each record in the buffer is a struct trace_func_stats. The 'needed'
+ * parameter returns the number of bytes needed to complete the operation,
+ * which may be more than buff_size if your buffer is too small.
+ *
+ * @param buff		Buffer in which to place data, or NULL to count size
+ * @param buff_size	Size of buffer
+ * @param needed	Returns number of bytes used / needed
+ * @return 0 if ok, -1 on error (buffer exhausted)
+ */
+int trace_list_functions(void *buff, size_t buff_size, size_t *needed);
+
+/* Flags for ftrace_record */
+enum ftrace_flags {
+	FUNCF_EXIT		= 0UL << 30,
+	FUNCF_ENTRY		= 1UL << 30,
+	FUNCF_TEXTBASE		= 2UL << 30,
+
+	FUNCF_TIMESTAMP_MASK	= 0x3fffffff,
+};
+
+#define TRACE_CALL_TYPE(call)	((call)->flags & 0xc0000000UL)
+
+/* Information about a single function entry/exit */
+struct trace_call {
+	uint32_t func;		/* Function offset */
+	uint32_t caller;	/* Caller function offset */
+	uint32_t flags;		/* Flags and timestamp */
+};
+
+int trace_list_calls(void *buff, size_t buff_size, size_t *needed);
+
+/**
+ * Turn function tracing on and off
+ *
+ * Don't enable trace if it has not been initialised.
+ *
+ * @param enabled	1 to enable trace, 0 to disable
+ */
+void trace_set_enabled(int enabled);
+
+int trace_early_init(void);
+
+/**
+ * Init the trace system
+ *
+ * This should be called after relocation with a suitably large buffer
+ * (typically as large as the U-Boot text area)
+ *
+ * @param buff		Pointer to trace buffer
+ * @param buff_size	Size of trace buffer
+ */
+int trace_init(void *buff, size_t buff_size);
+
+#endif
diff --git a/include/tsec.h b/include/tsec.h
new file mode 100644
index 0000000..b17fa95
--- /dev/null
+++ b/include/tsec.h
@@ -0,0 +1,433 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  tsec.h
+ *
+ *  Driver for the Motorola Triple Speed Ethernet Controller
+ *
+ * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
+ * (C) Copyright 2003, Motorola, Inc.
+ * maintained by Xianghua Xiao (x.xiao@motorola.com)
+ * author Andy Fleming
+ */
+
+#ifndef __TSEC_H
+#define __TSEC_H
+
+#include <net.h>
+#include <config.h>
+#include <phy.h>
+
+#define TSEC_MDIO_REGS_OFFSET	0x520
+
+#ifndef CONFIG_DM_ETH
+
+#ifdef CONFIG_ARCH_LS1021A
+#define TSEC_SIZE		0x40000
+#define TSEC_MDIO_OFFSET	0x40000
+#else
+#define TSEC_SIZE 		0x01000
+#define TSEC_MDIO_OFFSET	0x01000
+#endif
+
+#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET)
+
+#define TSEC_GET_REGS(num, offset) \
+	(struct tsec __iomem *)\
+	(TSEC_BASE_ADDR + (((num) - 1) * (offset)))
+
+#define TSEC_GET_REGS_BASE(num) \
+	TSEC_GET_REGS((num), TSEC_SIZE)
+
+#define TSEC_GET_MDIO_REGS(num, offset) \
+	(struct tsec_mii_mng __iomem *)\
+	(CONFIG_SYS_MDIO_BASE_ADDR  + ((num) - 1) * (offset))
+
+#define TSEC_GET_MDIO_REGS_BASE(num) \
+	TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
+
+#define DEFAULT_MII_NAME "FSL_MDIO"
+
+#define STD_TSEC_INFO(num) \
+{			\
+	.regs = TSEC_GET_REGS_BASE(num), \
+	.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
+	.devname = CONFIG_TSEC##num##_NAME, \
+	.phyaddr = TSEC##num##_PHY_ADDR, \
+	.flags = TSEC##num##_FLAGS, \
+	.mii_devname = DEFAULT_MII_NAME \
+}
+
+#define SET_STD_TSEC_INFO(x, num) \
+{			\
+	x.regs = TSEC_GET_REGS_BASE(num); \
+	x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
+	x.devname = CONFIG_TSEC##num##_NAME; \
+	x.phyaddr = TSEC##num##_PHY_ADDR; \
+	x.flags = TSEC##num##_FLAGS;\
+	x.mii_devname = DEFAULT_MII_NAME;\
+}
+
+#endif /* CONFIG_DM_ETH */
+
+#define MAC_ADDR_LEN		6
+
+/* #define TSEC_TIMEOUT	1000000 */
+#define TSEC_TIMEOUT		1000
+#define TOUT_LOOP		1000000
+
+/* TBI register addresses */
+#define TBI_CR			0x00
+#define TBI_SR			0x01
+#define TBI_ANA			0x04
+#define TBI_ANLPBPA		0x05
+#define TBI_ANEX		0x06
+#define TBI_TBICON		0x11
+
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT	0x0020
+#define TBIANA_ASYMMETRIC_PAUSE	0x0100
+#define TBIANA_SYMMETRIC_PAUSE	0x0080
+#define TBIANA_HALF_DUPLEX	0x0040
+#define TBIANA_FULL_DUPLEX	0x0020
+#define TBICR_PHY_RESET		0x8000
+#define TBICR_ANEG_ENABLE	0x1000
+#define TBICR_RESTART_ANEG	0x0200
+#define TBICR_FULL_DUPLEX	0x0100
+#define TBICR_SPEED1_SET	0x0040
+
+/* MAC register bits */
+#define MACCFG1_SOFT_RESET	0x80000000
+#define MACCFG1_RESET_RX_MC	0x00080000
+#define MACCFG1_RESET_TX_MC	0x00040000
+#define MACCFG1_RESET_RX_FUN	0x00020000
+#define MACCFG1_RESET_TX_FUN	0x00010000
+#define MACCFG1_LOOPBACK	0x00000100
+#define MACCFG1_RX_FLOW		0x00000020
+#define MACCFG1_TX_FLOW		0x00000010
+#define MACCFG1_SYNCD_RX_EN	0x00000008
+#define MACCFG1_RX_EN		0x00000004
+#define MACCFG1_SYNCD_TX_EN	0x00000002
+#define MACCFG1_TX_EN		0x00000001
+
+#define MACCFG2_INIT_SETTINGS	0x00007205
+#define MACCFG2_FULL_DUPLEX	0x00000001
+#define MACCFG2_IF		0x00000300
+#define MACCFG2_GMII		0x00000200
+#define MACCFG2_MII		0x00000100
+
+#define ECNTRL_INIT_SETTINGS	0x00001000
+#define ECNTRL_TBI_MODE		0x00000020
+#define ECNTRL_REDUCED_MODE	0x00000010
+#define ECNTRL_R100		0x00000008
+#define ECNTRL_REDUCED_MII_MODE	0x00000004
+#define ECNTRL_SGMII_MODE	0x00000002
+
+#ifndef CONFIG_SYS_TBIPA_VALUE
+# define CONFIG_SYS_TBIPA_VALUE	0x1f
+#endif
+
+#define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN
+
+#define MINFLR_INIT_SETTINGS	0x00000040
+
+#define DMACTRL_INIT_SETTINGS	0x000000c3
+#define DMACTRL_GRS		0x00000010
+#define DMACTRL_GTS		0x00000008
+#define DMACTRL_LE		0x00008000
+
+#define TSTAT_CLEAR_THALT	0x80000000
+#define RSTAT_CLEAR_RHALT	0x00800000
+
+#define IEVENT_INIT_CLEAR	0xffffffff
+#define IEVENT_BABR		0x80000000
+#define IEVENT_RXC		0x40000000
+#define IEVENT_BSY		0x20000000
+#define IEVENT_EBERR		0x10000000
+#define IEVENT_MSRO		0x04000000
+#define IEVENT_GTSC		0x02000000
+#define IEVENT_BABT		0x01000000
+#define IEVENT_TXC		0x00800000
+#define IEVENT_TXE		0x00400000
+#define IEVENT_TXB		0x00200000
+#define IEVENT_TXF		0x00100000
+#define IEVENT_IE		0x00080000
+#define IEVENT_LC		0x00040000
+#define IEVENT_CRL		0x00020000
+#define IEVENT_XFUN		0x00010000
+#define IEVENT_RXB0		0x00008000
+#define IEVENT_GRSC		0x00000100
+#define IEVENT_RXF0		0x00000080
+
+#define IMASK_INIT_CLEAR	0x00000000
+#define IMASK_TXEEN		0x00400000
+#define IMASK_TXBEN		0x00200000
+#define IMASK_TXFEN		0x00100000
+#define IMASK_RXFEN0		0x00000080
+
+/* Default Attribute fields */
+#define ATTR_INIT_SETTINGS	0x000000c0
+#define ATTRELI_INIT_SETTINGS	0x00000000
+
+/* TxBD status field bits */
+#define TXBD_READY		0x8000
+#define TXBD_PADCRC		0x4000
+#define TXBD_WRAP		0x2000
+#define TXBD_INTERRUPT		0x1000
+#define TXBD_LAST		0x0800
+#define TXBD_CRC		0x0400
+#define TXBD_DEF		0x0200
+#define TXBD_HUGEFRAME		0x0080
+#define TXBD_LATECOLLISION	0x0080
+#define TXBD_RETRYLIMIT		0x0040
+#define TXBD_RETRYCOUNTMASK	0x003c
+#define TXBD_UNDERRUN		0x0002
+#define TXBD_STATS		0x03ff
+
+/* RxBD status field bits */
+#define RXBD_EMPTY		0x8000
+#define RXBD_RO1		0x4000
+#define RXBD_WRAP		0x2000
+#define RXBD_INTERRUPT		0x1000
+#define RXBD_LAST		0x0800
+#define RXBD_FIRST		0x0400
+#define RXBD_MISS		0x0100
+#define RXBD_BROADCAST		0x0080
+#define RXBD_MULTICAST		0x0040
+#define RXBD_LARGE		0x0020
+#define RXBD_NONOCTET		0x0010
+#define RXBD_SHORT		0x0008
+#define RXBD_CRCERR		0x0004
+#define RXBD_OVERRUN		0x0002
+#define RXBD_TRUNCATED		0x0001
+#define RXBD_STATS		0x003f
+
+struct txbd8 {
+	uint16_t status;	/* Status Fields */
+	uint16_t length;	/* Buffer length */
+	uint32_t bufptr;	/* Buffer Pointer */
+};
+
+struct rxbd8 {
+	uint16_t status;	/* Status Fields */
+	uint16_t length;	/* Buffer Length */
+	uint32_t bufptr;	/* Buffer Pointer */
+};
+
+struct tsec_rmon_mib {
+	/* Transmit and Receive Counters */
+	u32	tr64;		/* Tx/Rx 64-byte Frame Counter */
+	u32	tr127;		/* Tx/Rx 65-127 byte Frame Counter */
+	u32	tr255;		/* Tx/Rx 128-255 byte Frame Counter */
+	u32	tr511;		/* Tx/Rx 256-511 byte Frame Counter */
+	u32	tr1k;		/* Tx/Rx 512-1023 byte Frame Counter */
+	u32	trmax;		/* Tx/Rx 1024-1518 byte Frame Counter */
+	u32	trmgv;		/* Tx/Rx 1519-1522 byte Good VLAN Frame */
+	/* Receive Counters */
+	u32	rbyt;		/* Receive Byte Counter */
+	u32	rpkt;		/* Receive Packet Counter */
+	u32	rfcs;		/* Receive FCS Error Counter */
+	u32	rmca;		/* Receive Multicast Packet (Counter) */
+	u32	rbca;		/* Receive Broadcast Packet */
+	u32	rxcf;		/* Receive Control Frame Packet */
+	u32	rxpf;		/* Receive Pause Frame Packet */
+	u32	rxuo;		/* Receive Unknown OP Code */
+	u32	raln;		/* Receive Alignment Error */
+	u32	rflr;		/* Receive Frame Length Error */
+	u32	rcde;		/* Receive Code Error */
+	u32	rcse;		/* Receive Carrier Sense Error */
+	u32	rund;		/* Receive Undersize Packet */
+	u32	rovr;		/* Receive Oversize Packet */
+	u32	rfrg;		/* Receive Fragments */
+	u32	rjbr;		/* Receive Jabber */
+	u32	rdrp;		/* Receive Drop */
+	/* Transmit Counters */
+	u32	tbyt;		/* Transmit Byte Counter */
+	u32	tpkt;		/* Transmit Packet */
+	u32	tmca;		/* Transmit Multicast Packet */
+	u32	tbca;		/* Transmit Broadcast Packet */
+	u32	txpf;		/* Transmit Pause Control Frame */
+	u32	tdfr;		/* Transmit Deferral Packet */
+	u32	tedf;		/* Transmit Excessive Deferral Packet */
+	u32	tscl;		/* Transmit Single Collision Packet */
+	/* (0x2_n700) */
+	u32	tmcl;		/* Transmit Multiple Collision Packet */
+	u32	tlcl;		/* Transmit Late Collision Packet */
+	u32	txcl;		/* Transmit Excessive Collision Packet */
+	u32	tncl;		/* Transmit Total Collision */
+
+	u32	res2;
+
+	u32	tdrp;		/* Transmit Drop Frame */
+	u32	tjbr;		/* Transmit Jabber Frame */
+	u32	tfcs;		/* Transmit FCS Error */
+	u32	txcf;		/* Transmit Control Frame */
+	u32	tovr;		/* Transmit Oversize Frame */
+	u32	tund;		/* Transmit Undersize Frame */
+	u32	tfrg;		/* Transmit Fragments Frame */
+	/* General Registers */
+	u32	car1;		/* Carry Register One */
+	u32	car2;		/* Carry Register Two */
+	u32	cam1;		/* Carry Register One Mask */
+	u32	cam2;		/* Carry Register Two Mask */
+};
+
+struct tsec_hash_regs {
+	u32	iaddr0;		/* Individual Address Register 0 */
+	u32	iaddr1;		/* Individual Address Register 1 */
+	u32	iaddr2;		/* Individual Address Register 2 */
+	u32	iaddr3;		/* Individual Address Register 3 */
+	u32	iaddr4;		/* Individual Address Register 4 */
+	u32	iaddr5;		/* Individual Address Register 5 */
+	u32	iaddr6;		/* Individual Address Register 6 */
+	u32	iaddr7;		/* Individual Address Register 7 */
+	u32	res1[24];
+	u32	gaddr0;		/* Group Address Register 0 */
+	u32	gaddr1;		/* Group Address Register 1 */
+	u32	gaddr2;		/* Group Address Register 2 */
+	u32	gaddr3;		/* Group Address Register 3 */
+	u32	gaddr4;		/* Group Address Register 4 */
+	u32	gaddr5;		/* Group Address Register 5 */
+	u32	gaddr6;		/* Group Address Register 6 */
+	u32	gaddr7;		/* Group Address Register 7 */
+	u32	res2[24];
+};
+
+struct tsec {
+	/* General Control and Status Registers (0x2_n000) */
+	u32	res000[4];
+
+	u32	ievent;		/* Interrupt Event */
+	u32	imask;		/* Interrupt Mask */
+	u32	edis;		/* Error Disabled */
+	u32	res01c;
+	u32	ecntrl;		/* Ethernet Control */
+	u32	minflr;		/* Minimum Frame Length */
+	u32	ptv;		/* Pause Time Value */
+	u32	dmactrl;	/* DMA Control */
+	u32	tbipa;		/* TBI PHY Address */
+
+	u32	res034[3];
+	u32	res040[48];
+
+	/* Transmit Control and Status Registers (0x2_n100) */
+	u32	tctrl;		/* Transmit Control */
+	u32	tstat;		/* Transmit Status */
+	u32	res108;
+	u32	tbdlen;		/* Tx BD Data Length */
+	u32	res110[5];
+	u32	ctbptr;		/* Current TxBD Pointer */
+	u32	res128[23];
+	u32	tbptr;		/* TxBD Pointer */
+	u32	res188[30];
+	/* (0x2_n200) */
+	u32	res200;
+	u32	tbase;		/* TxBD Base Address */
+	u32	res208[42];
+	u32	ostbd;		/* Out of Sequence TxBD */
+	u32	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
+	u32	res2b8[18];
+
+	/* Receive Control and Status Registers (0x2_n300) */
+	u32	rctrl;		/* Receive Control */
+	u32	rstat;		/* Receive Status */
+	u32	res308;
+	u32	rbdlen;		/* RxBD Data Length */
+	u32	res310[4];
+	u32	res320;
+	u32	crbptr;		/* Current Receive Buffer Pointer */
+	u32	res328[6];
+	u32	mrblr;		/* Maximum Receive Buffer Length */
+	u32	res344[16];
+	u32	rbptr;		/* RxBD Pointer */
+	u32	res388[30];
+	/* (0x2_n400) */
+	u32	res400;
+	u32	rbase;		/* RxBD Base Address */
+	u32	res408[62];
+
+	/* MAC Registers (0x2_n500) */
+	u32	maccfg1;	/* MAC Configuration #1 */
+	u32	maccfg2;	/* MAC Configuration #2 */
+	u32	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
+	u32	hafdup;		/* Half-duplex */
+	u32	maxfrm;		/* Maximum Frame */
+	u32	res514;
+	u32	res518;
+
+	u32	res51c;
+
+	u32	resmdio[6];
+
+	u32	res538;
+
+	u32	ifstat;		/* Interface Status */
+	u32	macstnaddr1;	/* Station Address, part 1 */
+	u32	macstnaddr2;	/* Station Address, part 2 */
+	u32	res548[46];
+
+	/* (0x2_n600) */
+	u32	res600[32];
+
+	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
+	struct tsec_rmon_mib	rmon;
+	u32	res740[48];
+
+	/* Hash Function Registers (0x2_n800) */
+	struct tsec_hash_regs	hash;
+
+	u32	res900[128];
+
+	/* Pattern Registers (0x2_nb00) */
+	u32	resb00[62];
+	u32	attr; /* Default Attribute Register */
+	u32	attreli; /* Default Attribute Extract Length and Index */
+
+	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
+	u32	resc00[256];
+};
+
+#define TSEC_GIGABIT	(1 << 0)
+
+/* These flags currently only have meaning if we're using the eTSEC */
+#define TSEC_REDUCED	(1 << 1)	/* MAC-PHY interface uses RGMII */
+#define TSEC_SGMII	(1 << 2)	/* MAC-PHY interface uses SGMII */
+
+#define TX_BUF_CNT	2
+
+struct tsec_private {
+	struct txbd8 __iomem txbd[TX_BUF_CNT];
+	struct rxbd8 __iomem rxbd[PKTBUFSRX];
+	struct tsec __iomem *regs;
+	struct tsec_mii_mng __iomem *phyregs_sgmii;
+	struct phy_device *phydev;
+	phy_interface_t interface;
+	struct mii_dev *bus;
+	uint phyaddr;
+	uint tbiaddr;
+	char mii_devname[16];
+	u32 flags;
+	uint rx_idx;	/* index of the current RX buffer */
+	uint tx_idx;	/* index of the current TX buffer */
+#ifndef CONFIG_DM_ETH
+	struct eth_device *dev;
+#else
+	struct udevice *dev;
+#endif
+};
+
+struct tsec_info_struct {
+	struct tsec __iomem *regs;
+	struct tsec_mii_mng __iomem *miiregs_sgmii;
+	char *devname;
+	char *mii_devname;
+	phy_interface_t interface;
+	unsigned int phyaddr;
+	u32 flags;
+};
+
+#ifndef CONFIG_DM_ETH
+int tsec_standard_init(bd_t *bis);
+int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
+#endif
+
+#endif /* __TSEC_H */
diff --git a/include/tsi148.h b/include/tsi148.h
new file mode 100644
index 0000000..a9f353b
--- /dev/null
+++ b/include/tsi148.h
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com
+ *
+ * base on universe.h by
+ *
+ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
+ */
+
+#ifndef _tsi148_h
+#define _tsi148_h
+
+#ifndef PCI_DEVICE_ID_TUNDRA_TSI148
+#define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148
+#endif
+
+typedef struct _TSI148 TSI148;
+typedef struct _OUTBOUND OUTBOUND;
+typedef struct _INBOUND  INBOUND;
+typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
+
+struct _OUTBOUND {
+	unsigned int otsau;                   /* 0x000 Outbound start       upper */
+	unsigned int otsal;                   /* 0x004 Outbouud start       lower */
+	unsigned int oteau;                   /* 0x008 Outbound end         upper */
+	unsigned int oteal;                   /* 0x00c Outbound end         lower */
+	unsigned int otofu;                   /* 0x010 Outbound translation upper */
+	unsigned int otofl;                   /* 0x014 Outbound translation lower */
+	unsigned int otbs;                    /* 0x018 Outbound translation 2eSST */
+	unsigned int otat;                    /* 0x01c Outbound translation attr  */
+};
+
+struct _INBOUND {
+	unsigned int itsau;                   /* 0x000 inbound  start       upper */
+	unsigned int itsal;                   /* 0x004 inbouud  start       lower */
+	unsigned int iteau;                   /* 0x008 inbound  end         upper */
+	unsigned int iteal;                   /* 0x00c inbound  end         lower */
+	unsigned int itofu;                   /* 0x010 inbound  translation upper */
+	unsigned int itofl;                   /* 0x014 inbound  translation lower */
+	unsigned int itat;                    /* 0x018 inbound  translation attr  */
+	unsigned int spare;                   /* 0x01c not used                   */
+};
+
+struct _TSI148 {
+	unsigned int pci_id;                  /* 0x000         */
+	unsigned int pci_csr;                 /* 0x004         */
+	unsigned int pci_class;               /* 0x008         */
+	unsigned int pci_misc0;               /* 0x00c         */
+	unsigned int pci_mbarl;               /* 0x010         */
+	unsigned int pci_mbarh;               /* 0x014         */
+	unsigned int spare0[(0x03c-0x018)/4]; /* 0x018         */
+	unsigned int pci_misc1;               /* 0x03c         */
+	unsigned int pci_pcixcap;             /* 0x040         */
+	unsigned int pci_pcixstat;            /* 0x044         */
+	unsigned int spare1[(0x100-0x048)/4]; /* 0x048         */
+	OUTBOUND     outbound[8];             /* 0x100         */
+	unsigned int viack[8];                /* 0x204         */
+	unsigned int rmwau;                   /* 0x220         */
+	unsigned int rmwal;                   /* 0x224         */
+	unsigned int rmwen;                   /* 0x228         */
+	unsigned int rmwc;                    /* 0x22c         */
+	unsigned int rmws;                    /* 0x230         */
+	unsigned int vmctrl;                  /* 0x234         */
+	unsigned int vctrl;                   /* 0x238         */
+	unsigned int vstat;                   /* 0x23c         */
+	unsigned int pcsr;                    /* 0x240         */
+	unsigned int spare2[3];               /* 0x244 - 0x24c */
+	unsigned int vmefl;                   /* 0x250         */
+	unsigned int spare3[3];               /* 0x254 - 0x25c */
+	unsigned int veau;                    /* 0x260         */
+	unsigned int veal;                    /* 0x264         */
+	unsigned int veat;                    /* 0x268         */
+	unsigned int spare4[1];               /* 0x26c         */
+	unsigned int edpau;                   /* 0x270         */
+	unsigned int edpal;                   /* 0x274         */
+	unsigned int edpxa;                   /* 0x278         */
+	unsigned int edpxs;                   /* 0x27c         */
+	unsigned int edpat;                   /* 0x280         */
+	unsigned int spare5[31];              /* 0x284 - 0x2fc */
+	INBOUND      inbound[8];              /* 0x100         */
+	unsigned int gbau;                    /* 0x400         */
+	unsigned int gbal;                    /* 0x404         */
+	unsigned int gcsrat;                  /* 0x408         */
+	unsigned int cbau;                    /* 0x40c         */
+	unsigned int cbal;                    /* 0x410         */
+	unsigned int crgat;                   /* 0x414         */
+	unsigned int crou;                    /* 0x418         */
+	unsigned int crol;                    /* 0x41c         */
+	unsigned int crat;                    /* 0x420         */
+	unsigned int lmbau;                   /* 0x424         */
+	unsigned int lmbal;                   /* 0x428         */
+	unsigned int lmat;                    /* 0x42c         */
+	unsigned int r64bcu;                  /* 0x430         */
+	unsigned int r64bcl;                  /* 0x434         */
+	unsigned int bpgtr;                   /* 0x438         */
+	unsigned int bpctr;                   /* 0x43c         */
+	unsigned int vicr;                    /* 0x440         */
+	unsigned int spare6[1];               /* 0x444         */
+	unsigned int inten;                   /* 0x448         */
+	unsigned int inteo;                   /* 0x44c         */
+	unsigned int ints;                    /* 0x450         */
+	unsigned int intc;                    /* 0x454         */
+	unsigned int intm1;                   /* 0x458         */
+	unsigned int intm2;                   /* 0x45c         */
+	unsigned int spare7[40];              /* 0x460 - 0x4fc */
+	unsigned int dctl0;                   /* 0x500         */
+	unsigned int dsta0;                   /* 0x504         */
+	unsigned int dcsau0;                  /* 0x508         */
+	unsigned int dcsal0;                  /* 0x50c         */
+	unsigned int dcdau0;                  /* 0x510         */
+	unsigned int dcdal0;                  /* 0x514         */
+	unsigned int dclau0;                  /* 0x518         */
+	unsigned int dclal0;                  /* 0x51c         */
+	unsigned int dsau0;                   /* 0x520         */
+	unsigned int dsal0;                   /* 0x524         */
+	unsigned int ddau0;                   /* 0x528         */
+	unsigned int ddal0;                   /* 0x52c         */
+	unsigned int dsat0;                   /* 0x530         */
+	unsigned int ddat0;                   /* 0x534         */
+	unsigned int dnlau0;                  /* 0x538         */
+	unsigned int dnlal0;                  /* 0x53c         */
+	unsigned int dcnt0;                   /* 0x540         */
+	unsigned int ddbs0;                   /* 0x544         */
+	unsigned int r20[14];                 /* 0x548 - 0x57c */
+	unsigned int dctl1;                   /* 0x580         */
+	unsigned int dsta1;                   /* 0x584         */
+	unsigned int dcsau1;                  /* 0x588         */
+	unsigned int dcsal1;                  /* 0x58c         */
+	unsigned int dcdau1;                  /* 0x590         */
+	unsigned int dcdal1;                  /* 0x594         */
+	unsigned int dclau1;                  /* 0x598         */
+	unsigned int dclal1;                  /* 0x59c         */
+	unsigned int dsau1;                   /* 0x5a0         */
+	unsigned int dsal1;                   /* 0x5a4         */
+	unsigned int ddau1;                   /* 0x5a8         */
+	unsigned int ddal1;                   /* 0x5ac         */
+	unsigned int dsat1;                   /* 0x5b0         */
+	unsigned int ddat1;                   /* 0x5b4         */
+	unsigned int dnlau1;                  /* 0x5b8         */
+	unsigned int dnlal1;                  /* 0x5bc         */
+	unsigned int dcnt1;                   /* 0x5c0         */
+	unsigned int ddbs1;                   /* 0x5c4         */
+	unsigned int r21[14];                 /* 0x5c8 - 0x5fc */
+	unsigned int devi_veni_2;             /* 0x600         */
+	unsigned int gctrl_ga_revid;          /* 0x604         */
+	unsigned int semaphore0_1_2_3;        /* 0x608         */
+	unsigned int semaphore4_5_6_7;        /* 0x60c         */
+	unsigned int mbox0;                   /* 0x610         */
+	unsigned int mbox1;                   /* 0x614         */
+	unsigned int mbox2;                   /* 0x618         */
+	unsigned int mbox3;                   /* 0x61c         */
+	unsigned int r22[629];                /* 0x620 - 0xff0 */
+	unsigned int csrbcr;                  /* 0xff4         */
+	unsigned int csrbsr;                  /* 0xff8         */
+	unsigned int cbar;                    /* 0xffc         */
+};
+
+#define IRQ_VOWN	0x0001
+#define IRQ_VIRQ1	0x0002
+#define IRQ_VIRQ2	0x0004
+#define IRQ_VIRQ3	0x0008
+#define IRQ_VIRQ4	0x0010
+#define IRQ_VIRQ5	0x0020
+#define IRQ_VIRQ6	0x0040
+#define IRQ_VIRQ7	0x0080
+#define IRQ_DMA		0x0100
+#define IRQ_LERR	0x0200
+#define IRQ_VERR	0x0400
+#define IRQ_res		0x0800
+#define IRQ_IACK	0x1000
+#define IRQ_SWINT	0x2000
+#define IRQ_SYSFAIL	0x4000
+#define IRQ_ACFAIL	0x8000
+
+struct _TDMA_CMD_PACKET {
+	unsigned int dctl;   /* DMA Control         */
+	unsigned int dtbc;   /* Transfer Byte Count */
+	unsigned int dlv;    /* PCI Address         */
+	unsigned int res1;   /* Reserved            */
+	unsigned int dva;    /* Vme Address         */
+	unsigned int res2;   /* Reserved            */
+	unsigned int dcpp;   /* Pointer to Numed Cmd Packet with rPN */
+	unsigned int res3;   /* Reserved                             */
+};
+
+#define VME_AM_A16		0x01
+#define VME_AM_A24		0x02
+#define VME_AM_A32		0x03
+#define VME_AM_Axx		0x03
+#define VME_AM_USR		0x04
+#define VME_AM_SUP		0x08
+#define VME_AM_DATA		0x10
+#define VME_AM_PROG		0x20
+#define VME_AM_Mxx		(VME_AM_DATA | VME_AM_PROG)
+
+#define VME_FLAG_D8		0x01
+#define VME_FLAG_D16		0x02
+#define VME_FLAG_D32		0x03
+#define VME_FLAG_Dxx		0x03
+
+#endif
diff --git a/include/twl4030.h b/include/twl4030.h
new file mode 100644
index 0000000..c27ad61
--- /dev/null
+++ b/include/twl4030.h
@@ -0,0 +1,702 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix at windriver.com>
+ *
+ * Derived from code on omapzoom, git://git.omapzoom.com/repo/u-boot.git
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ */
+
+#ifndef TWL4030_H
+#define TWL4030_H
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses */
+
+/* USB */
+#define TWL4030_CHIP_USB				0x48
+/* AUD */
+#define TWL4030_CHIP_AUDIO_VOICE			0x49
+#define TWL4030_CHIP_GPIO				0x49
+#define TWL4030_CHIP_INTBR				0x49
+#define TWL4030_CHIP_PIH				0x49
+#define TWL4030_CHIP_TEST				0x49
+/* AUX */
+#define TWL4030_CHIP_KEYPAD				0x4a
+#define TWL4030_CHIP_MADC				0x4a
+#define TWL4030_CHIP_INTERRUPTS				0x4a
+#define TWL4030_CHIP_LED				0x4a
+#define TWL4030_CHIP_MAIN_CHARGE			0x4a
+#define TWL4030_CHIP_PRECHARGE				0x4a
+#define TWL4030_CHIP_PWM0				0x4a
+#define TWL4030_CHIP_PWM1				0x4a
+#define TWL4030_CHIP_PWMA				0x4a
+#define TWL4030_CHIP_PWMB				0x4a
+/* POWER */
+#define TWL4030_CHIP_BACKUP				0x4b
+#define TWL4030_CHIP_INT				0x4b
+#define TWL4030_CHIP_PM_MASTER				0x4b
+#define TWL4030_CHIP_PM_RECEIVER			0x4b
+#define TWL4030_CHIP_RTC				0x4b
+#define TWL4030_CHIP_SECURED_REG			0x4b
+
+/* Register base addresses */
+
+/* USB */
+#define TWL4030_BASEADD_USB				0x0000
+/* AUD */
+#define TWL4030_BASEADD_AUDIO_VOICE			0x0000
+#define TWL4030_BASEADD_GPIO				0x0098
+#define TWL4030_BASEADD_INTBR				0x0085
+#define TWL4030_BASEADD_PIH				0x0080
+#define TWL4030_BASEADD_TEST				0x004C
+/* AUX */
+#define TWL4030_BASEADD_INTERRUPTS			0x00B9
+#define TWL4030_BASEADD_LED				0x00EE
+#define TWL4030_BASEADD_MADC				0x0000
+#define TWL4030_BASEADD_MAIN_CHARGE			0x0074
+#define TWL4030_BASEADD_PRECHARGE			0x00AA
+#define TWL4030_BASEADD_PWM0				0x00F8
+#define TWL4030_BASEADD_PWM1				0x00FB
+#define TWL4030_BASEADD_PWMA				0x00EF
+#define TWL4030_BASEADD_PWMB				0x00F1
+#define TWL4030_BASEADD_KEYPAD				0x00D2
+/* POWER */
+#define TWL4030_BASEADD_BACKUP				0x0014
+#define TWL4030_BASEADD_INT				0x002E
+#define TWL4030_BASEADD_PM_MASTER			0x0036
+#define TWL4030_BASEADD_PM_RECIEVER			0x005B
+#define TWL4030_BASEADD_RTC				0x001C
+#define TWL4030_BASEADD_SECURED_REG			0x0000
+
+/*
+ * Power Management Master
+ */
+#define TWL4030_PM_MASTER_CFG_P1_TRANSITION		0x36
+#define TWL4030_PM_MASTER_CFG_P2_TRANSITION		0x37
+#define TWL4030_PM_MASTER_CFG_P3_TRANSITION		0x38
+#define TWL4030_PM_MASTER_CFG_P123_TRANSITION		0x39
+#define TWL4030_PM_MASTER_STS_BOOT			0x3A
+#define TWL4030_PM_MASTER_CFG_BOOT			0x3B
+#define TWL4030_PM_MASTER_SHUNDAN			0x3C
+#define TWL4030_PM_MASTER_BOOT_BCI			0x3D
+#define TWL4030_PM_MASTER_CFG_PWRANA1			0x3E
+#define TWL4030_PM_MASTER_CFG_PWRANA2			0x3F
+#define TWL4030_PM_MASTER_BGAP_TRIM			0x40
+#define TWL4030_PM_MASTER_BACKUP_MISC_STS		0x41
+#define TWL4030_PM_MASTER_BACKUP_MISC_CFG		0x42
+#define TWL4030_PM_MASTER_BACKUP_MISC_TST		0x43
+#define TWL4030_PM_MASTER_PROTECT_KEY			0x44
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS		0x45
+#define TWL4030_PM_MASTER_P1_SW_EVENTS			0x46
+#define TWL4030_PM_MASTER_P2_SW_EVENTS			0x47
+#define TWL4030_PM_MASTER_P3_SW_EVENTS			0x48
+#define TWL4030_PM_MASTER_STS_P123_STATE		0x49
+#define TWL4030_PM_MASTER_PB_CFG			0x4A
+#define TWL4030_PM_MASTER_PB_WORD_MSB			0x4B
+#define TWL4030_PM_MASTER_PB_WORD_LSB			0x4C
+#define TWL4030_PM_MASTER_SEQ_ADD_W2P			0x52
+#define TWL4030_PM_MASTER_SEQ_ADD_P2A			0x53
+#define TWL4030_PM_MASTER_SEQ_ADD_A2W			0x54
+#define TWL4030_PM_MASTER_SEQ_ADD_A2S			0x55
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A12			0x56
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A3			0x57
+#define TWL4030_PM_MASTER_SEQ_ADD_WARM			0x58
+#define TWL4030_PM_MASTER_MEMORY_ADDRESS		0x59
+#define TWL4030_PM_MASTER_MEMORY_DATA			0x5A
+#define TWL4030_PM_MASTER_SC_CONFIG			0x5B
+#define TWL4030_PM_MASTER_SC_DETECT1			0x5C
+#define TWL4030_PM_MASTER_SC_DETECT2			0x5D
+#define TWL4030_PM_MASTER_WATCHDOG_CFG			0x5E
+#define TWL4030_PM_MASTER_IT_CHECK_CFG			0x5F
+#define TWL4030_PM_MASTER_VIBRATOR_CFG			0x60
+#define TWL4030_PM_MASTER_DCDC_GLOBAL_CFG		0x61
+#define TWL4030_PM_MASTER_VDD1_TRIM1			0x62
+#define TWL4030_PM_MASTER_VDD1_TRIM2			0x63
+#define TWL4030_PM_MASTER_VDD2_TRIM1			0x64
+#define TWL4030_PM_MASTER_VDD2_TRIM2			0x65
+#define TWL4030_PM_MASTER_VIO_TRIM1			0x66
+#define TWL4030_PM_MASTER_VIO_TRIM2			0x67
+#define TWL4030_PM_MASTER_MISC_CFG			0x68
+#define TWL4030_PM_MASTER_LS_TST_A			0x69
+#define TWL4030_PM_MASTER_LS_TST_B			0x6A
+#define TWL4030_PM_MASTER_LS_TST_C			0x6B
+#define TWL4030_PM_MASTER_LS_TST_D			0x6C
+#define TWL4030_PM_MASTER_BB_CFG			0x6D
+#define TWL4030_PM_MASTER_MISC_TST			0x6E
+#define TWL4030_PM_MASTER_TRIM1				0x6F
+
+/* Power bus message definitions */
+
+/* The TWL4030/5030 splits its power-management resources (the various
+ * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
+ * P3. These groups can then be configured to transition between sleep, wait-on
+ * and active states by sending messages to the power bus.  See Section 5.4.2
+ * Power Resources of TWL4030 TRM
+ */
+
+/* Processor groups */
+#define DEV_GRP_NULL		0x0
+#define DEV_GRP_P1		0x1	/* P1: all OMAP devices */
+#define DEV_GRP_P2		0x2	/* P2: all Modem devices */
+#define DEV_GRP_P3		0x4	/* P3: all peripheral devices */
+
+/* Resource groups */
+#define RES_GRP_RES		0x0	/* Reserved */
+#define RES_GRP_PP		0x1	/* Power providers */
+#define RES_GRP_RC		0x2	/* Reset and control */
+#define RES_GRP_PP_RC		0x3
+#define RES_GRP_PR		0x4	/* Power references */
+#define RES_GRP_PP_PR		0x5
+#define RES_GRP_RC_PR		0x6
+#define RES_GRP_ALL		0x7	/* All resource groups */
+
+#define RES_TYPE2_R0		0x0
+
+#define RES_TYPE_ALL		0x7
+
+/* Resource states */
+#define RES_STATE_WRST		0xF
+#define RES_STATE_ACTIVE	0xE
+#define RES_STATE_SLEEP		0x8
+#define RES_STATE_OFF		0x0
+
+/* Power resources */
+
+/* Power providers */
+#define RES_VAUX1               1
+#define RES_VAUX2               2
+#define RES_VAUX3               3
+#define RES_VAUX4               4
+#define RES_VMMC1               5
+#define RES_VMMC2               6
+#define RES_VPLL1               7
+#define RES_VPLL2               8
+#define RES_VSIM                9
+#define RES_VDAC                10
+#define RES_VINTANA1            11
+#define RES_VINTANA2            12
+#define RES_VINTDIG             13
+#define RES_VIO                 14
+#define RES_VDD1                15
+#define RES_VDD2                16
+#define RES_VUSB_1V5            17
+#define RES_VUSB_1V8            18
+#define RES_VUSB_3V1            19
+#define RES_VUSBCP              20
+#define RES_REGEN               21
+/* Reset and control */
+#define RES_NRES_PWRON          22
+#define RES_CLKEN               23
+#define RES_SYSEN               24
+#define RES_HFCLKOUT            25
+#define RES_32KCLKOUT           26
+#define RES_RESET               27
+/* Power Reference */
+#define RES_Main_Ref            28
+
+/* P[1-3]_SW_EVENTS */
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON	(1 << 6)
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN	(1 << 5)
+#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET	(1 << 4)
+#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP		(1 << 3)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT		(1 << 2)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP		(1 << 1)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF		(1 << 0)
+
+/* HW conditions */
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_PWON	(1 << 0)
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_CHG		(1 << 1)
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_USB		(1 << 2)
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_VBUS	(1 << 7)
+
+/* Power transition */
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_PWON	(1 << 0)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_CHG	(1 << 1)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_USB	(1 << 2)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_RTC	(1 << 3)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT	(1 << 4)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBUS	(1 << 5)
+#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_SWBUG	(1 << 7)
+
+/* PWRANA2 */
+#define TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT0_LOWV	(1 << 1)
+#define TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT1_LOWV	(1 << 2)
+
+#define TOTAL_RESOURCES		28
+/*
+ * Power Bus Message Format ... these can be sent individually by Linux,
+ * but are usually part of downloaded scripts that are run when various
+ * power events are triggered.
+ *
+ *  Broadcast Message (16 Bits):
+ *    DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
+ *    RES_STATE[3:0]
+ *
+ *  Singular Message (16 Bits):
+ *    DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
+ */
+
+#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
+	((devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
+	| (type) << 4 | (state))
+
+#define MSG_SINGULAR(devgrp, id, state) \
+	((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
+
+#define MSG_BROADCAST_ALL(devgrp, state) \
+	((devgrp) << 5 | (state))
+
+#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
+#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
+#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
+
+/* Power Managment Receiver */
+#define TWL4030_PM_RECEIVER_SC_CONFIG			0x5B
+#define TWL4030_PM_RECEIVER_SC_DETECT1			0x5C
+#define TWL4030_PM_RECEIVER_SC_DETECT2			0x5D
+#define TWL4030_PM_RECEIVER_WATCHDOG_CFG		0x5E
+#define TWL4030_PM_RECEIVER_IT_CHECK_CFG		0x5F
+#define TWL4030_PM_RECEIVER_VIBRATOR_CFG		0x5F
+#define TWL4030_PM_RECEIVER_DC_TO_DC_CFG		0x61
+#define TWL4030_PM_RECEIVER_VDD1_TRIM1			0x62
+#define TWL4030_PM_RECEIVER_VDD1_TRIM2			0x63
+#define TWL4030_PM_RECEIVER_VDD2_TRIM1			0x64
+#define TWL4030_PM_RECEIVER_VDD2_TRIM2			0x65
+#define TWL4030_PM_RECEIVER_VIO_TRIM1			0x66
+#define TWL4030_PM_RECEIVER_VIO_TRIM2			0x67
+#define TWL4030_PM_RECEIVER_MISC_CFG			0x68
+#define TWL4030_PM_RECEIVER_LS_TST_A			0x69
+#define TWL4030_PM_RECEIVER_LS_TST_B			0x6A
+#define TWL4030_PM_RECEIVER_LS_TST_C			0x6B
+#define TWL4030_PM_RECEIVER_LS_TST_D			0x6C
+#define TWL4030_PM_RECEIVER_BB_CFG			0x6D
+#define TWL4030_PM_RECEIVER_MISC_TST			0x6E
+#define TWL4030_PM_RECEIVER_TRIM1			0x6F
+#define TWL4030_PM_RECEIVER_TRIM2			0x70
+#define TWL4030_PM_RECEIVER_DC_DC_TIMEOUT		0x71
+#define TWL4030_PM_RECEIVER_VAUX1_DEV_GRP		0x72
+#define TWL4030_PM_RECEIVER_VAUX1_TYPE			0x73
+#define TWL4030_PM_RECEIVER_VAUX1_REMAP			0x74
+#define TWL4030_PM_RECEIVER_VAUX1_DEDICATED		0x75
+#define TWL4030_PM_RECEIVER_VAUX2_DEV_GRP		0x76
+#define TWL4030_PM_RECEIVER_VAUX2_TYPE			0x77
+#define TWL4030_PM_RECEIVER_VAUX2_REMAP			0x78
+#define TWL4030_PM_RECEIVER_VAUX2_DEDICATED		0x79
+#define TWL4030_PM_RECEIVER_VAUX3_DEV_GRP		0x7A
+#define TWL4030_PM_RECEIVER_VAUX3_TYPE			0x7B
+#define TWL4030_PM_RECEIVER_VAUX3_REMAP			0x7C
+#define TWL4030_PM_RECEIVER_VAUX3_DEDICATED		0x7D
+#define TWL4030_PM_RECEIVER_VAUX4_DEV_GRP		0x7E
+#define TWL4030_PM_RECEIVER_VAUX4_TYPE			0x7F
+#define TWL4030_PM_RECEIVER_VAUX4_REMAP			0x80
+#define TWL4030_PM_RECEIVER_VAUX4_DEDICATED		0x81
+#define TWL4030_PM_RECEIVER_VMMC1_DEV_GRP		0x82
+#define TWL4030_PM_RECEIVER_VMMC1_TYPE			0x83
+#define TWL4030_PM_RECEIVER_VMMC1_REMAP			0x84
+#define TWL4030_PM_RECEIVER_VMMC1_DEDICATED		0x85
+#define TWL4030_PM_RECEIVER_VMMC2_DEV_GRP		0x86
+#define TWL4030_PM_RECEIVER_VMMC2_TYPE			0x87
+#define TWL4030_PM_RECEIVER_VMMC2_REMAP			0x88
+#define TWL4030_PM_RECEIVER_VMMC2_DEDICATED		0x89
+#define TWL4030_PM_RECEIVER_VPLL1_DEV_GRP		0x8A
+#define TWL4030_PM_RECEIVER_VPLL1_TYPE			0x8B
+#define TWL4030_PM_RECEIVER_VPLL1_REMAP			0x8C
+#define TWL4030_PM_RECEIVER_VPLL1_DEDICATED		0x8D
+#define TWL4030_PM_RECEIVER_VPLL2_DEV_GRP		0x8E
+#define TWL4030_PM_RECEIVER_VPLL2_TYPE			0x8F
+#define TWL4030_PM_RECEIVER_VPLL2_REMAP			0x90
+#define TWL4030_PM_RECEIVER_VPLL2_DEDICATED		0x91
+#define TWL4030_PM_RECEIVER_VSIM_DEV_GRP		0x92
+#define TWL4030_PM_RECEIVER_VSIM_TYPE			0x93
+#define TWL4030_PM_RECEIVER_VSIM_REMAP			0x94
+#define TWL4030_PM_RECEIVER_VSIM_DEDICATED		0x95
+#define TWL4030_PM_RECEIVER_VDAC_DEV_GRP		0x96
+#define TWL4030_PM_RECEIVER_VDAC_TYPE			0x97
+#define TWL4030_PM_RECEIVER_VDAC_REMAP			0x98
+#define TWL4030_PM_RECEIVER_VDAC_DEDICATED		0x99
+#define TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP		0x9A
+#define TWL4030_PM_RECEIVER_VINTANA1_TYP		0x9B
+#define TWL4030_PM_RECEIVER_VINTANA1_REMAP		0x9C
+#define TWL4030_PM_RECEIVER_VINTANA1_DEDICATED		0x9D
+#define TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP		0x9E
+#define TWL4030_PM_RECEIVER_VINTANA2_TYPE		0x9F
+#define TWL4030_PM_RECEIVER_VINTANA2_REMAP		0xA0
+#define TWL4030_PM_RECEIVER_VINTANA2_DEDICATED		0xA1
+#define TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP		0xA2
+#define TWL4030_PM_RECEIVER_VINTDIG_TYPE		0xA3
+#define TWL4030_PM_RECEIVER_VINTDIG_REMAP		0xA4
+#define TWL4030_PM_RECEIVER_VINTDIG_DEDICATED		0xA5
+#define TWL4030_PM_RECEIVER_VIO_DEV_GRP			0xA6
+#define TWL4030_PM_RECEIVER_VIO_TYPE			0xA7
+#define TWL4030_PM_RECEIVER_VIO_REMAP			0xA8
+#define TWL4030_PM_RECEIVER_VIO_CFG			0xA9
+#define TWL4030_PM_RECEIVER_VIO_MISC_CFG		0xAA
+#define TWL4030_PM_RECEIVER_VIO_TEST1			0xAB
+#define TWL4030_PM_RECEIVER_VIO_TEST2			0xAC
+#define TWL4030_PM_RECEIVER_VIO_OSC			0xAD
+#define TWL4030_PM_RECEIVER_VIO_RESERVED		0xAE
+#define TWL4030_PM_RECEIVER_VIO_VSEL			0xAF
+#define TWL4030_PM_RECEIVER_VDD1_DEV_GRP		0xB0
+#define TWL4030_PM_RECEIVER_VDD1_TYPE			0xB1
+#define TWL4030_PM_RECEIVER_VDD1_REMAP			0xB2
+#define TWL4030_PM_RECEIVER_VDD1_CFG			0xB3
+#define TWL4030_PM_RECEIVER_VDD1_MISC_CFG		0xB4
+#define TWL4030_PM_RECEIVER_VDD1_TEST1			0xB5
+#define TWL4030_PM_RECEIVER_VDD1_TEST2			0xB6
+#define TWL4030_PM_RECEIVER_VDD1_OSC			0xB7
+#define TWL4030_PM_RECEIVER_VDD1_RESERVED		0xB8
+#define TWL4030_PM_RECEIVER_VDD1_VSEL			0xB9
+#define TWL4030_PM_RECEIVER_VDD1_VMODE_CFG		0xBA
+#define TWL4030_PM_RECEIVER_VDD1_VFLOOR			0xBB
+#define TWL4030_PM_RECEIVER_VDD1_VROOF			0xBC
+#define TWL4030_PM_RECEIVER_VDD1_STEP			0xBD
+#define TWL4030_PM_RECEIVER_VDD2_DEV_GRP		0xBE
+#define TWL4030_PM_RECEIVER_VDD2_TYPE			0xBF
+#define TWL4030_PM_RECEIVER_VDD2_REMAP			0xC0
+#define TWL4030_PM_RECEIVER_VDD2_CFG			0xC1
+#define TWL4030_PM_RECEIVER_VDD2_MISC_CFG		0xC2
+#define TWL4030_PM_RECEIVER_VDD2_TEST1			0xC3
+#define TWL4030_PM_RECEIVER_VDD2_TEST2			0xC4
+#define TWL4030_PM_RECEIVER_VDD2_OSC			0xC5
+#define TWL4030_PM_RECEIVER_VDD2_RESERVED		0xC6
+#define TWL4030_PM_RECEIVER_VDD2_VSEL			0xC7
+#define TWL4030_PM_RECEIVER_VDD2_VMODE_CFG		0xC8
+#define TWL4030_PM_RECEIVER_VDD2_VFLOOR			0xC9
+#define TWL4030_PM_RECEIVER_VDD2_VROOF			0xCA
+#define TWL4030_PM_RECEIVER_VDD2_STEP			0xCB
+#define TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP		0xCC
+#define TWL4030_PM_RECEIVER_VUSB1V5_TYPE		0xCD
+#define TWL4030_PM_RECEIVER_VUSB1V5_REMAP		0xCE
+#define TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP		0xCF
+#define TWL4030_PM_RECEIVER_VUSB1V8_TYPE		0xD0
+#define TWL4030_PM_RECEIVER_VUSB1V8_REMAP		0xD1
+#define TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP		0xD2
+#define TWL4030_PM_RECEIVER_VUSB3V1_TYPE		0xD3
+#define TWL4030_PM_RECEIVER_VUSB3V1_REMAP		0xD4
+#define TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP		0xD5
+#define TWL4030_PM_RECEIVER_VUSBCP_TYPE			0xD6
+#define TWL4030_PM_RECEIVER_VUSBCP_REMAP		0xD7
+#define TWL4030_PM_RECEIVER_VUSB_DEDICATED1		0xD8
+#define TWL4030_PM_RECEIVER_VUSB_DEDICATED2		0xD9
+#define TWL4030_PM_RECEIVER_REGEN_DEV_GRP		0xDA
+#define TWL4030_PM_RECEIVER_REGEN_TYPE			0xDB
+#define TWL4030_PM_RECEIVER_REGEN_REMAP			0xDC
+#define TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP		0xDD
+#define TWL4030_PM_RECEIVER_NRESPWRON_TYPE		0xDE
+#define TWL4030_PM_RECEIVER_NRESPWRON_REMAP		0xDF
+#define TWL4030_PM_RECEIVER_CLKEN_DEV_GRP		0xE0
+#define TWL4030_PM_RECEIVER_CLKEN_TYPE			0xE1
+#define TWL4030_PM_RECEIVER_CLKEN_REMAP			0xE2
+#define TWL4030_PM_RECEIVER_SYSEN_DEV_GRP		0xE3
+#define TWL4030_PM_RECEIVER_SYSEN_TYPE			0xE4
+#define TWL4030_PM_RECEIVER_SYSEN_REMAP			0xE5
+#define TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP		0xE6
+#define TWL4030_PM_RECEIVER_HFCLKOUT_TYPE		0xE7
+#define TWL4030_PM_RECEIVER_HFCLKOUT_REMAP		0xE8
+#define TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP		0xE9
+#define TWL4030_PM_RECEIVER_32KCLKOUT_TYPE		0xEA
+#define TWL4030_PM_RECEIVER_32KCLKOUT_REMAP		0xEB
+#define TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GRP	0xEC
+#define TWL4030_PM_RECEIVER_TRITON_RESET_TYPE		0xED
+#define TWL4030_PM_RECEIVER_TRITON_RESET_REMAP		0xEE
+#define TWL4030_PM_RECEIVER_MAINREF_DEV_GRP		0xEF
+#define TWL4030_PM_RECEIVER_MAINREF_TYPE		0xF0
+#define TWL4030_PM_RECEIVER_MAINREF_REMAP		0xF1
+
+/* Voltage Selection in PM Receiver Module */
+#define TWL4030_PM_RECEIVER_VAUX2_VSEL_18		0x05
+#define TWL4030_PM_RECEIVER_VAUX2_VSEL_28		0x09
+#define TWL4030_PM_RECEIVER_VAUX3_VSEL_18		0x01
+#define TWL4030_PM_RECEIVER_VAUX3_VSEL_28		0x03
+#define TWL4030_PM_RECEIVER_VPLL2_VSEL_18		0x05
+#define TWL4030_PM_RECEIVER_VDAC_VSEL_18		0x03
+#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30		0x02
+#define TWL4030_PM_RECEIVER_VMMC1_VSEL_32		0x03
+#define TWL4030_PM_RECEIVER_VMMC2_VSEL_30		0x0B
+#define TWL4030_PM_RECEIVER_VMMC2_VSEL_32		0x0C
+#define TWL4030_PM_RECEIVER_VSIM_VSEL_18		0x03
+
+/* Device Selection in PM Receiver Module */
+#define TWL4030_PM_RECEIVER_DEV_GRP_P1			0x20
+#define TWL4030_PM_RECEIVER_DEV_GRP_ALL			0xE0
+
+/* LED */
+#define TWL4030_LED_LEDEN				0xEE
+#define TWL4030_LED_LEDEN_LEDAON			(1 << 0)
+#define TWL4030_LED_LEDEN_LEDBON			(1 << 1)
+#define TWL4030_LED_LEDEN_LEDAPWM			(1 << 4)
+#define TWL4030_LED_LEDEN_LEDBPWM			(1 << 5)
+
+/* Keypad */
+#define TWL4030_KEYPAD_KEYP_CTRL_REG			0xD2
+#define TWL4030_KEYPAD_KEY_DEB_REG			0xD3
+#define TWL4030_KEYPAD_LONG_KEY_REG1			0xD4
+#define TWL4030_KEYPAD_LK_PTV_REG			0xD5
+#define TWL4030_KEYPAD_TIME_OUT_REG1			0xD6
+#define TWL4030_KEYPAD_TIME_OUT_REG2			0xD7
+#define TWL4030_KEYPAD_KBC_REG				0xD8
+#define TWL4030_KEYPAD_KBR_REG				0xD9
+#define TWL4030_KEYPAD_KEYP_SMS				0xDA
+#define TWL4030_KEYPAD_FULL_CODE_7_0			0xDB
+#define TWL4030_KEYPAD_FULL_CODE_15_8			0xDC
+#define TWL4030_KEYPAD_FULL_CODE_23_16			0xDD
+#define TWL4030_KEYPAD_FULL_CODE_31_24			0xDE
+#define TWL4030_KEYPAD_FULL_CODE_39_32			0xDF
+#define TWL4030_KEYPAD_FULL_CODE_47_40			0xE0
+#define TWL4030_KEYPAD_FULL_CODE_55_48			0xE1
+#define TWL4030_KEYPAD_FULL_CODE_63_56			0xE2
+#define TWL4030_KEYPAD_KEYP_ISR1			0xE3
+#define TWL4030_KEYPAD_KEYP_IMR1			0xE4
+#define TWL4030_KEYPAD_KEYP_ISR2			0xE5
+#define TWL4030_KEYPAD_KEYP_IMR2			0xE6
+#define TWL4030_KEYPAD_KEYP_SIR				0xE7
+#define TWL4030_KEYPAD_KEYP_EDR				0xE8
+#define TWL4030_KEYPAD_KEYP_SIH_CTRL			0xE9
+
+#define TWL4030_KEYPAD_CTRL_KBD_ON			(1 << 6)
+#define TWL4030_KEYPAD_CTRL_RP_EN			(1 << 5)
+#define TWL4030_KEYPAD_CTRL_TOLE_EN			(1 << 4)
+#define TWL4030_KEYPAD_CTRL_TOE_EN			(1 << 3)
+#define TWL4030_KEYPAD_CTRL_LK_EN			(1 << 2)
+#define TWL4030_KEYPAD_CTRL_SOFTMODEN			(1 << 1)
+#define TWL4030_KEYPAD_CTRL_SOFT_NRST			(1 << 0)
+
+/* USB */
+#define TWL4030_USB_VENDOR_ID_LO			0x00
+#define TWL4030_USB_VENDOR_ID_HI			0x01
+#define TWL4030_USB_PRODUCT_ID_LO			0x02
+#define TWL4030_USB_PRODUCT_ID_HI			0x03
+#define TWL4030_USB_FUNC_CTRL				0x04
+#define TWL4030_USB_FUNC_CTRL_SET			0x05
+#define TWL4030_USB_FUNC_CTRL_CLR			0x06
+#define TWL4030_USB_IFC_CTRL				0x07
+#define TWL4030_USB_IFC_CTRL_SET			0x08
+#define TWL4030_USB_IFC_CTRL_CLR			0x09
+#define TWL4030_USB_OTG_CTRL				0x0A
+#define TWL4030_USB_OTG_CTRL_SET			0x0B
+#define TWL4030_USB_OTG_CTRL_CLR			0x0C
+#define TWL4030_USB_USB_INT_EN_RISE			0x0D
+#define TWL4030_USB_USB_INT_EN_RISE_SET			0x0E
+#define TWL4030_USB_USB_INT_EN_RISE_CLR			0x0F
+#define TWL4030_USB_USB_INT_EN_FALL			0x10
+#define TWL4030_USB_USB_INT_EN_FALL_SET			0x11
+#define TWL4030_USB_USB_INT_EN_FALL_CLR			0x12
+#define TWL4030_USB_USB_INT_STS				0x13
+#define TWL4030_USB_USB_INT_LATCH			0x14
+#define TWL4030_USB_DEBUG				0x15
+#define TWL4030_USB_SCRATCH_REG				0x16
+#define TWL4030_USB_SCRATCH_REG_SET			0x17
+#define TWL4030_USB_SCRATCH_REG_CLR			0x18
+#define TWL4030_USB_CARKIT_CTRL				0x19
+#define TWL4030_USB_CARKIT_CTRL_SET			0x1A
+#define TWL4030_USB_CARKIT_CTRL_CLR			0x1B
+#define TWL4030_USB_CARKIT_INT_DELAY			0x1C
+#define TWL4030_USB_CARKIT_INT_EN			0x1D
+#define TWL4030_USB_CARKIT_INT_EN_SET			0x1E
+#define TWL4030_USB_CARKIT_INT_EN_CLR			0x1F
+#define TWL4030_USB_CARKIT_INT_STS			0x20
+#define TWL4030_USB_CARKIT_INT_LATCH			0x21
+#define TWL4030_USB_CARKIT_PLS_CTRL			0x22
+#define TWL4030_USB_CARKIT_PLS_CTRL_SET			0x23
+#define TWL4030_USB_CARKIT_PLS_CTRL_CLR			0x24
+#define TWL4030_USB_TRANS_POS_WIDTH			0x25
+#define TWL4030_USB_TRANS_NEG_WIDTH			0x26
+#define TWL4030_USB_RCV_PLTY_RECOVERY			0x27
+#define TWL4030_USB_MCPC_CTRL				0x30
+#define TWL4030_USB_MCPC_CTRL_SET			0x31
+#define TWL4030_USB_MCPC_CTRL_CLR			0x32
+#define TWL4030_USB_MCPC_IO_CTRL			0x33
+#define TWL4030_USB_MCPC_IO_CTRL_SET			0x34
+#define TWL4030_USB_MCPC_IO_CTRL_CLR			0x35
+#define TWL4030_USB_MCPC_CTRL2				0x36
+#define TWL4030_USB_MCPC_CTRL2_SET			0x37
+#define TWL4030_USB_MCPC_CTRL2_CLR			0x38
+#define TWL4030_USB_OTHER_FUNC_CTRL			0x80
+#define TWL4030_USB_OTHER_FUNC_CTRL_SET			0x81
+#define TWL4030_USB_OTHER_FUNC_CTRL_CLR			0x82
+#define TWL4030_USB_OTHER_IFC_CTRL			0x83
+#define TWL4030_USB_OTHER_IFC_CTRL_SET			0x84
+#define TWL4030_USB_OTHER_IFC_CTRL_CLR			0x85
+#define TWL4030_USB_OTHER_INT_EN_RISE_SET		0x87
+#define TWL4030_USB_OTHER_INT_EN_RISE_CLR		0x88
+#define TWL4030_USB_OTHER_INT_EN_FALL			0x89
+#define TWL4030_USB_OTHER_INT_EN_FALL_SET		0x8A
+#define TWL4030_USB_OTHER_INT_EN_FALL_CLR		0x8B
+#define TWL4030_USB_OTHER_INT_STS			0x8C
+#define TWL4030_USB_OTHER_INT_LATCH			0x8D
+#define TWL4030_USB_ID_STATUS				0x96
+#define TWL4030_USB_CARKIT_SM_1_INT_EN			0x97
+#define TWL4030_USB_CARKIT_SM_1_INT_EN_SET		0x98
+#define TWL4030_USB_CARKIT_SM_1_INT_EN_CLR		0x99
+#define TWL4030_USB_CARKIT_SM_1_INT_STS			0x9A
+#define TWL4030_USB_CARKIT_SM_1_INT_LATCH		0x9B
+#define TWL4030_USB_CARKIT_SM_2_INT_EN			0x9C
+#define TWL4030_USB_CARKIT_SM_2_INT_EN_SET		0x9D
+#define TWL4030_USB_CARKIT_SM_2_INT_EN_CLR		0x9E
+#define TWL4030_USB_CARKIT_SM_2_INT_STS			0x9F
+#define TWL4030_USB_CARKIT_SM_2_INT_LATCH		0xA0
+#define TWL4030_USB_CARKIT_SM_CTRL			0xA1
+#define TWL4030_USB_CARKIT_SM_CTRL_SET			0xA2
+#define TWL4030_USB_CARKIT_SM_CTRL_CLR			0xA3
+#define TWL4030_USB_CARKIT_SM_CMD			0xA4
+#define TWL4030_USB_CARKIT_SM_CMD_SET			0xA5
+#define TWL4030_USB_CARKIT_SM_CMD_CLR			0xA6
+#define TWL4030_USB_CARKIT_SM_CMD_STS			0xA7
+#define TWL4030_USB_CARKIT_SM_STATUS			0xA8
+#define TWL4030_USB_CARKIT_SM_ERR_STATUS		0xAA
+#define TWL4030_USB_CARKIT_SM_CTRL_STATE		0xAB
+#define TWL4030_USB_POWER_CTRL				0xAC
+#define TWL4030_USB_POWER_CTRL_SET			0xAD
+#define TWL4030_USB_POWER_CTRL_CLR			0xAE
+#define TWL4030_USB_OTHER_IFC_CTRL2			0xAF
+#define TWL4030_USB_OTHER_IFC_CTRL2_SET			0xB0
+#define TWL4030_USB_OTHER_IFC_CTRL2_CLR			0xB1
+#define TWL4030_USB_REG_CTRL_EN				0xB2
+#define TWL4030_USB_REG_CTRL_EN_SET			0xB3
+#define TWL4030_USB_REG_CTRL_EN_CLR			0xB4
+#define TWL4030_USB_REG_CTRL_ERROR			0xB5
+#define TWL4030_USB_OTHER_FUNC_CTRL2			0xB8
+#define TWL4030_USB_OTHER_FUNC_CTRL2_SET		0xB9
+#define TWL4030_USB_OTHER_FUNC_CTRL2_CLR		0xBA
+#define TWL4030_USB_CARKIT_ANA_CTRL			0xBB
+#define TWL4030_USB_CARKIT_ANA_CTRL_SET			0xBC
+#define TWL4030_USB_CARKIT_ANA_CTRL_CLR			0xBD
+#define TWL4030_USB_VBUS_DEBOUNCE			0xC0
+#define TWL4030_USB_ID_DEBOUNCE				0xC1
+#define TWL4030_USB_TPH_DP_CON_MIN			0xC2
+#define TWL4030_USB_TPH_DP_CON_MAX			0xC3
+#define TWL4030_USB_TCR_DP_CON_MIN			0xC4
+#define TWL4030_USB_TCR_DP_CON_MAX			0xC5
+#define TWL4030_USB_TPH_DP_PD_SHORT			0xC6
+#define TWL4030_USB_TPH_CMD_DLY				0xC7
+#define TWL4030_USB_TPH_DET_RST				0xC8
+#define TWL4030_USB_TPH_AUD_BIAS			0xC9
+#define TWL4030_USB_TCR_UART_DET_MIN			0xCA
+#define TWL4030_USB_TCR_UART_DET_MAX			0xCB
+#define TWL4030_USB_TPH_ID_INT_PW			0xCD
+#define TWL4030_USB_TACC_ID_INT_WAIT			0xCE
+#define TWL4030_USB_TACC_ID_INT_PW			0xCF
+#define TWL4030_USB_TPH_CMD_WAIT			0xD0
+#define TWL4030_USB_TPH_ACK_WAIT			0xD1
+#define TWL4030_USB_TPH_DP_DISC_DET			0xD2
+#define TWL4030_USB_VBAT_TIMER				0xD3
+#define TWL4030_USB_CARKIT_4W_DEBUG			0xE0
+#define TWL4030_USB_CARKIT_5W_DEBUG			0xE1
+#define TWL4030_USB_PHY_PWR_CTRL			0xFD
+#define TWL4030_USB_PHY_CLK_CTRL			0xFE
+#define TWL4030_USB_PHY_CLK_CTRL_STS			0xFF
+
+/* GPIO */
+#define TWL4030_GPIO_GPIODATAIN1			0x00
+#define TWL4030_GPIO_GPIODATAIN2			0x01
+#define TWL4030_GPIO_GPIODATAIN3			0x02
+#define TWL4030_GPIO_GPIODATADIR1			0x03
+#define TWL4030_GPIO_GPIODATADIR2			0x04
+#define TWL4030_GPIO_GPIODATADIR3			0x05
+#define TWL4030_GPIO_GPIODATAOUT1			0x06
+#define TWL4030_GPIO_GPIODATAOUT2			0x07
+#define TWL4030_GPIO_GPIODATAOUT3			0x08
+#define TWL4030_GPIO_CLEARGPIODATAOUT1			0x09
+#define TWL4030_GPIO_CLEARGPIODATAOUT2			0x0A
+#define TWL4030_GPIO_CLEARGPIODATAOUT3			0x0B
+#define TWL4030_GPIO_SETGPIODATAOUT1			0x0C
+#define TWL4030_GPIO_SETGPIODATAOUT2			0x0D
+#define TWL4030_GPIO_SETGPIODATAOUT3			0x0E
+#define TWL4030_GPIO_GPIO_DEBEN1			0x0F
+#define TWL4030_GPIO_GPIO_DEBEN2			0x10
+#define TWL4030_GPIO_GPIO_DEBEN3			0x11
+#define TWL4030_GPIO_GPIO_CTRL				0x12
+#define TWL4030_GPIO_GPIOPUPDCTR1			0x13
+#define TWL4030_GPIO_GPIOPUPDCTR2			0x14
+#define TWL4030_GPIO_GPIOPUPDCTR3			0x15
+#define TWL4030_GPIO_GPIOPUPDCTR4			0x16
+#define TWL4030_GPIO_GPIOPUPDCTR5			0x17
+#define TWL4030_GPIO_GPIO_ISR1A				0x19
+#define TWL4030_GPIO_GPIO_ISR2A				0x1A
+#define TWL4030_GPIO_GPIO_ISR3A				0x1B
+#define TWL4030_GPIO_GPIO_IMR1A				0x1C
+#define TWL4030_GPIO_GPIO_IMR2A				0x1D
+#define TWL4030_GPIO_GPIO_IMR3A				0x1E
+#define TWL4030_GPIO_GPIO_ISR1B				0x1F
+#define TWL4030_GPIO_GPIO_ISR2B				0x20
+#define TWL4030_GPIO_GPIO_ISR3B				0x21
+#define TWL4030_GPIO_GPIO_IMR1B				0x22
+#define TWL4030_GPIO_GPIO_IMR2B				0x23
+#define TWL4030_GPIO_GPIO_IMR3B				0x24
+#define TWL4030_GPIO_GPIO_EDR1				0x28
+#define TWL4030_GPIO_GPIO_EDR2				0x29
+#define TWL4030_GPIO_GPIO_EDR3				0x2A
+#define TWL4030_GPIO_GPIO_EDR4				0x2B
+#define TWL4030_GPIO_GPIO_EDR5				0x2C
+#define TWL4030_GPIO_GPIO_SIH_CTRL			0x2D
+
+/*
+ * Convience functions to read and write from TWL4030
+ *
+ * chip_no is the i2c address, it must be one of the chip addresses
+ *   defined at the top of this file with the prefix TWL4030_CHIP_
+ *   examples are TWL4030_CHIP_PM_RECEIVER and TWL4030_CHIP_KEYPAD
+ *
+ * val is the data either written to or read from the twl4030
+ *
+ * reg is the register to act on, it must be one of the defines
+ *   above and with the format TWL4030_<chip suffix>_<register name>
+ *   examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
+ *   TWL4030_LED_LEDEN.
+ */
+#ifndef CONFIG_DM_I2C
+static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+#else
+int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val);
+int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val);
+#endif
+/*
+ * Power
+ */
+
+/* For hardware resetting */
+void twl4030_power_reset_init(void);
+/* For power off */
+void twl4030_power_off(void);
+/* For setting device group and voltage */
+void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
+			     u8 dev_grp, u8 dev_grp_sel);
+/* For initializing power device */
+void twl4030_power_init(void);
+/* For initializing mmc power */
+void twl4030_power_mmc_init(int dev_index);
+
+/*
+ * Input
+ */
+
+int twl4030_input_power_button(void);
+int twl4030_input_charger(void);
+int twl4030_input_usb(void);
+
+int twl4030_keypad_scan(unsigned char *matrix);
+int twl4030_keypad_key(unsigned char *matrix, u8 c, u8 r);
+
+/*
+ * LED
+ */
+void twl4030_led_init(unsigned char ledon_mask);
+
+/*
+ * USB
+ */
+int twl4030_usb_ulpi_init(void);
+
+#endif /* TWL4030_H */
diff --git a/include/twl6030.h b/include/twl6030.h
new file mode 100644
index 0000000..41f17de
--- /dev/null
+++ b/include/twl6030.h
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ */
+
+#ifndef TWL6030_H
+#define TWL6030_H
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses */
+#define TWL6030_CHIP_PM		0x48
+
+#define TWL6030_CHIP_USB	0x49
+#define TWL6030_CHIP_ADC	0x49
+#define TWL6030_CHIP_CHARGER	0x49
+#define TWL6030_CHIP_PWM	0x49
+
+/* Slave Address 0x48 */
+#define TWL6030_STS_HW_CONDITIONS	0x21
+
+#define TWL6030_STS_HW_CONDITIONS_PWRON	(1 << 0)
+
+#define TWL6030_PHOENIX_DEV_ON		0x25
+
+#define TWL6030_PHOENIX_APP_DEVOFF	(1 << 0)
+#define TWL6030_PHOENIX_CON_DEVOFF	(1 << 1)
+#define TWL6030_PHOENIX_MOD_DEVOFF	(1 << 2)
+
+#define TWL6030_PH_STS_BOOT		0x29
+
+#define TWL6030_PH_STS_BOOT0		(1 << 0)
+#define TWL6030_PH_STS_BOOT1		(1 << 1)
+#define TWL6030_PH_STS_BOOT2		(1 << 2)
+#define TWL6030_PH_STS_BOOT3		(1 << 3)
+
+#define TWL6030_VAUX1_CFG_STATE		0x86
+#define TWL6030_VAUX1_CFG_VOLTAGE	0x87
+#define TWL6030_VMMC_CFG_STATE		0x9A
+#define TWL6030_VMMC_CFG_VOLTAGE	0x9B
+#define TWL6030_VUSB_CFG_STATE		0xA2
+#define TWL6030_VUSB_CFG_VOLTAGE	0xA3
+
+#define TWL6030_CFG_GRP_P1		(1 << 0)
+#define TWL6030_CFG_STATE_ON		(1 << 0)
+#define TWL6030_CFG_STATE_P1		(TWL6030_CFG_GRP_P1 << 5)
+#define TWL6030_CFG_VOLTAGE_18		0x09
+#define TWL6030_CFG_VOLTAGE_28		0x13
+#define TWL6030_CFG_VOLTAGE_30		0x15
+#define TWL6030_CFG_VOLTAGE_33		0x18
+
+#define MISC1			0xE4
+#define VAC_MEAS		(1 << 2)
+#define VBAT_MEAS		(1 << 1)
+#define BB_MEAS			(1 << 0)
+
+#define TWL6030_MISC2			0xE5
+#define TWL6030_MISC2_VUSB_IN_PMID	(1 << 3)
+#define TWL6030_MISC2_VUSB_IN_VSYS	(1 << 4)
+
+/* Slave Address 0x49 */
+
+#define TWL6030_CONTROLLER_STAT1		0xE3
+
+#define TWL6030_CONTROLLER_STAT1_VAC_DET	(1 << 3)
+#define TWL6030_CONTROLLER_STAT1_VBUS_DET	(1 << 2)
+
+/* Battery CHARGER REGISTERS */
+#define CONTROLLER_INT_MASK	0xE0
+#define CONTROLLER_CTRL1	0xE1
+#define CONTROLLER_WDG		0xE2
+#define CONTROLLER_STAT1	0xE3
+#define CHARGERUSB_INT_STATUS	0xE4
+#define CHARGERUSB_INT_MASK	0xE5
+#define CHARGERUSB_STATUS_INT1	0xE6
+#define CHARGERUSB_STATUS_INT2	0xE7
+#define CHARGERUSB_CTRL1	0xE8
+#define CHARGERUSB_CTRL2	0xE9
+#define CHARGERUSB_CTRL3	0xEA
+#define CHARGERUSB_STAT1	0xEB
+#define CHARGERUSB_VOREG	0xEC
+#define CHARGERUSB_VICHRG	0xED
+#define CHARGERUSB_CINLIMIT	0xEE
+#define CHARGERUSB_CTRLLIMIT1	0xEF
+
+/* CHARGERUSB_VICHRG */
+#define CHARGERUSB_VICHRG_500		0x4
+#define CHARGERUSB_VICHRG_1500		0xE
+/* CHARGERUSB_CINLIMIT */
+#define CHARGERUSB_CIN_LIMIT_100	0x1
+#define CHARGERUSB_CIN_LIMIT_300	0x5
+#define CHARGERUSB_CIN_LIMIT_500	0x9
+#define CHARGERUSB_CIN_LIMIT_NONE	0xF
+/* CONTROLLER_INT_MASK */
+#define MVAC_FAULT		(1 << 6)
+#define MAC_EOC			(1 << 5)
+#define MBAT_REMOVED		(1 << 4)
+#define MFAULT_WDG		(1 << 3)
+#define MBAT_TEMP		(1 << 2)
+#define MVBUS_DET		(1 << 1)
+#define MVAC_DET		(1 << 0)
+/* CHARGERUSB_INT_MASK */
+#define MASK_MCURRENT_TERM		(1 << 3)
+#define MASK_MCHARGERUSB_STAT		(1 << 2)
+#define MASK_MCHARGERUSB_THMREG		(1 << 1)
+#define MASK_MCHARGERUSB_FAULT		(1 << 0)
+/* CHARGERUSB_VOREG */
+#define CHARGERUSB_VOREG_3P52		0x01
+#define CHARGERUSB_VOREG_4P0		0x19
+#define CHARGERUSB_VOREG_4P2		0x23
+#define CHARGERUSB_VOREG_4P76		0x3F
+/* CHARGERUSB_CTRL1 */
+#define SUSPEND_BOOT		(1 << 7)
+#define OPA_MODE		(1 << 6)
+#define HZ_MODE			(1 << 5)
+#define TERM			(1 << 4)
+/* CHARGERUSB_CTRL2 */
+#define CHARGERUSB_CTRL2_VITERM_50	(0 << 5)
+#define CHARGERUSB_CTRL2_VITERM_100	(1 << 5)
+#define CHARGERUSB_CTRL2_VITERM_150	(2 << 5)
+#define CHARGERUSB_CTRL2_VITERM_400	(7 << 5)
+/* CONTROLLER_CTRL1 */
+#define CONTROLLER_CTRL1_EN_CHARGER	(1 << 4)
+#define CONTROLLER_CTRL1_SEL_CHARGER	(1 << 3)
+/* CONTROLLER_STAT1 */
+#define CHRG_EXTCHRG_STATZ	(1 << 7)
+#define CHRG_DET_N		(1 << 5)
+#define VAC_DET			(1 << 3)
+#define VBUS_DET		(1 << 2)
+
+#define FG_REG_10	0xCA
+#define FG_REG_11	0xCB
+
+#define TOGGLE1		0x90
+#define FGS		(1 << 5)
+#define FGR		(1 << 4)
+#define GPADCS		(1 << 1)
+#define GPADCR		(1 << 0)
+
+#define CTRL_P2		0x34
+#define CTRL_P2_SP2	(1 << 2)
+#define CTRL_P2_EOCP2	(1 << 1)
+#define CTRL_P2_BUSY	(1 << 0)
+
+#define TWL6032_CTRL_P1	0x36
+#define CTRL_P1_SP1	(1 << 3)
+
+#define GPCH0_LSB	0x57
+#define GPCH0_MSB	0x58
+
+#define TWL6032_GPCH0_LSB	0x3b
+
+#define TWL6032_GPSELECT_ISB	0x35
+
+#define USB_PRODUCT_ID_LSB	0x02
+
+#define TWL6030_GPADC_VBAT_CHNL	0x07
+#define TWL6032_GPADC_VBAT_CHNL	0x12
+
+#define TWL6030_GPADC_CTRL	0x2e
+#define TWL6032_GPADC_CTRL2	0x2f
+#define GPADC_CTRL2_CH18_SCALER_EN	(1 << 2)
+#define GPADC_CTRL_SCALER_DIV4		(1 << 3)
+
+#define TWL6030_VBAT_MULT	40 * 1000
+#define TWL6032_VBAT_MULT	25 * 1000
+
+#define TWL6030_VBAT_SHIFT	(10 + 3)
+#define TWL6032_VBAT_SHIFT	(12 + 2)
+
+enum twl603x_chip_type{
+	chip_TWL6030,
+	chip_TWL6032,
+	chip_TWL603X_cnt
+};
+
+struct twl6030_data{
+	u8 chip_type;
+	u8 adc_rbase;
+	u8 adc_ctrl;
+	u8 adc_enable;
+	int vbat_mult;
+	int vbat_shift;
+};
+
+/* Functions to read and write from TWL6030 */
+#ifndef CONFIG_DM_I2C
+static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+#else
+int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val);
+int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val);
+#endif
+
+/*
+ * Power
+ */
+
+void twl6030_power_off(void);
+void twl6030_init_battery_charging(void);
+void twl6030_usb_device_settings(void);
+void twl6030_start_usb_charging(void);
+void twl6030_stop_usb_charging(void);
+int twl6030_get_battery_voltage(void);
+int twl6030_get_battery_current(void);
+void twl6030_power_mmc_init(int dev_index);
+
+/*
+ * Input
+ */
+
+int twl6030_input_power_button(void);
+int twl6030_input_charger(void);
+int twl6030_input_usb(void);
+
+#endif /* TWL6030_H */
diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h
new file mode 100644
index 0000000..788ef29
--- /dev/null
+++ b/include/u-boot/crc.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ */
+
+#ifndef _UBOOT_CRC_H
+#define _UBOOT_CRC_H
+
+/* lib/crc8.c */
+unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len);
+
+/* lib/crc16.c - 16 bit CRC with polynomial x^16+x^12+x^5+1 (CRC-CCITT) */
+uint16_t crc16_ccitt(uint16_t crc_start, const unsigned char *s, int len);
+/**
+ * crc16_ccitt_wd_buf - Perform CRC16-CCIT on an input buffer and return the
+ *                      16-bit result (network byte-order) in an output buffer
+ *
+ * @in:	input buffer
+ * @len: input buffer length
+ * @out: output buffer (at least 2 bytes)
+ * @chunk_sz: ignored
+ */
+void crc16_ccitt_wd_buf(const uint8_t *in, uint len,
+			uint8_t *out, uint chunk_sz);
+
+/* lib/crc32.c */
+uint32_t crc32 (uint32_t, const unsigned char *, uint);
+uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint);
+uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint);
+
+/**
+ * crc32_wd_buf - Perform CRC32 on a buffer and return result in buffer
+ *
+ * @input:	Input buffer
+ * @ilen:	Input buffer length
+ * @output:	Place to put checksum result (4 bytes)
+ * @chunk_sz:	Trigger watchdog after processing this many bytes
+ */
+void crc32_wd_buf(const unsigned char *input, uint ilen,
+		    unsigned char *output, uint chunk_sz);
+
+/* lib/crc32c.c */
+void crc32c_init(uint32_t *, uint32_t);
+uint32_t crc32c_cal(uint32_t, const char *, int, uint32_t *);
+
+#endif /* _UBOOT_CRC_H */
diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h
new file mode 100644
index 0000000..e09c16a
--- /dev/null
+++ b/include/u-boot/md5.h
@@ -0,0 +1,34 @@
+/*
+ * This file was transplanted with slight modifications from Linux sources
+ * (fs/cifs/md5.h) into U-Boot by Bartlomiej Sieka <tur@semihalf.com>.
+ */
+
+#ifndef _MD5_H
+#define _MD5_H
+
+#include "compiler.h"
+
+struct MD5Context {
+	__u32 buf[4];
+	__u32 bits[2];
+	union {
+		unsigned char in[64];
+		__u32 in32[16];
+	};
+};
+
+/*
+ * Calculate and store in 'output' the MD5 digest of 'len' bytes at
+ * 'input'. 'output' must have enough space to hold 16 bytes.
+ */
+void md5 (unsigned char *input, int len, unsigned char output[16]);
+
+/*
+ * Calculate and store in 'output' the MD5 digest of 'len' bytes at 'input'.
+ * 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the
+ * watchdog every 'chunk_sz' bytes of input processed.
+ */
+void md5_wd (unsigned char *input, int len, unsigned char output[16],
+		unsigned int chunk_sz);
+
+#endif /* _MD5_H */
diff --git a/include/u-boot/rsa-checksum.h b/include/u-boot/rsa-checksum.h
new file mode 100644
index 0000000..02b814d
--- /dev/null
+++ b/include/u-boot/rsa-checksum.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013, Andreas Oetken.
+ */
+
+#ifndef _RSA_CHECKSUM_H
+#define _RSA_CHECKSUM_H
+
+#include <errno.h>
+#include <image.h>
+#include <u-boot/sha1.h>
+#include <u-boot/sha256.h>
+
+/**
+ * hash_calculate() - Calculate hash over the data
+ *
+ * @name:  Name of algorithm to be used for hash calculation
+ * @region: Array having info of regions over which hash needs to be calculated
+ * @region_count: Number of regions in the region array
+ * @checksum: Buffer contanining the output hash
+ *
+ * @return 0 if OK, < 0 if error
+ */
+int hash_calculate(const char *name,
+		   const struct image_region region[], int region_count,
+		   uint8_t *checksum);
+
+#endif
diff --git a/include/u-boot/rsa-mod-exp.h b/include/u-boot/rsa-mod-exp.h
new file mode 100644
index 0000000..8a428c4
--- /dev/null
+++ b/include/u-boot/rsa-mod-exp.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ */
+
+#ifndef _RSA_MOD_EXP_H
+#define _RSA_MOD_EXP_H
+
+#include <errno.h>
+#include <image.h>
+
+/**
+ * struct key_prop - holder for a public key properties
+ *
+ * The struct has pointers to modulus (Typically called N),
+ * The inverse, R^2, exponent. These can be typecasted and
+ * used as byte arrays or converted to the required format
+ * as per requirement of RSA implementation.
+ */
+struct key_prop {
+	const void *rr;		/* R^2 can be treated as byte array */
+	const void *modulus;	/* modulus as byte array */
+	const void *public_exponent; /* public exponent as byte array */
+	uint32_t n0inv;		/* -1 / modulus[0] mod 2^32 */
+	int num_bits;		/* Key length in bits */
+	uint32_t exp_len;	/* Exponent length in number of uint8_t */
+};
+
+/**
+ * rsa_mod_exp_sw() - Perform RSA Modular Exponentiation in sw
+ *
+ * Operation: out[] = sig ^ exponent % modulus
+ *
+ * @sig:	RSA PKCS1.5 signature
+ * @sig_len:	Length of signature in number of bytes
+ * @node:	Node with RSA key elements like modulus, exponent, R^2, n0inv
+ * @out:	Result in form of byte array of len equal to sig_len
+ */
+int rsa_mod_exp_sw(const uint8_t *sig, uint32_t sig_len,
+		struct key_prop *node, uint8_t *out);
+
+int rsa_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
+		struct key_prop *node, uint8_t *out);
+
+#if defined(CONFIG_CMD_ZYNQ_RSA)
+int zynq_pow_mod(u32 *keyptr, u32 *inout);
+#endif
+
+/**
+ * struct struct mod_exp_ops - Driver model for RSA Modular Exponentiation
+ *				operations
+ *
+ * The uclass interface is implemented by all crypto devices which use
+ * driver model.
+ */
+struct mod_exp_ops {
+	/**
+	 * Perform Modular Exponentiation
+	 *
+	 * Operation: out[] = sig ^ exponent % modulus
+	 *
+	 * @dev:	RSA Device
+	 * @sig:	RSA PKCS1.5 signature
+	 * @sig_len:	Length of signature in number of bytes
+	 * @node:	Node with RSA key elements like modulus, exponent,
+	 *		R^2, n0inv
+	 * @out:	Result in form of byte array of len equal to sig_len
+	 *
+	 * This function computes exponentiation over the signature.
+	 * Returns: 0 if exponentiation is successful, or a negative value
+	 * if it wasn't.
+	 */
+	int (*mod_exp)(struct udevice *dev, const uint8_t *sig,
+			   uint32_t sig_len, struct key_prop *node,
+			   uint8_t *outp);
+};
+
+#endif
diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h
new file mode 100644
index 0000000..2d3024d
--- /dev/null
+++ b/include/u-boot/rsa.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef _RSA_H
+#define _RSA_H
+
+#include <errno.h>
+#include <image.h>
+
+/**
+ * struct rsa_public_key - holder for a public key
+ *
+ * An RSA public key consists of a modulus (typically called N), the inverse
+ * and R^2, where R is 2^(# key bits).
+ */
+
+struct rsa_public_key {
+	uint len;		/* len of modulus[] in number of uint32_t */
+	uint32_t n0inv;		/* -1 / modulus[0] mod 2^32 */
+	uint32_t *modulus;	/* modulus as little endian array */
+	uint32_t *rr;		/* R^2 as little endian array */
+	uint64_t exponent;	/* public exponent */
+};
+
+struct image_sign_info;
+
+#if IMAGE_ENABLE_SIGN
+/**
+ * sign() - calculate and return signature for given input data
+ *
+ * @info:	Specifies key and FIT information
+ * @data:	Pointer to the input data
+ * @data_len:	Data length
+ * @sigp:	Set to an allocated buffer holding the signature
+ * @sig_len:	Set to length of the calculated hash
+ *
+ * This computes input data signature according to selected algorithm.
+ * Resulting signature value is placed in an allocated buffer, the
+ * pointer is returned as *sigp. The length of the calculated
+ * signature is returned via the sig_len pointer argument. The caller
+ * should free *sigp.
+ *
+ * @return: 0, on success, -ve on error
+ */
+int rsa_sign(struct image_sign_info *info,
+	     const struct image_region region[],
+	     int region_count, uint8_t **sigp, uint *sig_len);
+
+/**
+ * add_verify_data() - Add verification information to FDT
+ *
+ * Add public key information to the FDT node, suitable for
+ * verification at run-time. The information added depends on the
+ * algorithm being used.
+ *
+ * @info:	Specifies key and FIT information
+ * @keydest:	Destination FDT blob for public key data
+ * @return: 0, on success, -ENOSPC if the keydest FDT blob ran out of space,
+		other -ve value on error
+*/
+int rsa_add_verify_data(struct image_sign_info *info, void *keydest);
+#else
+static inline int rsa_sign(struct image_sign_info *info,
+		const struct image_region region[], int region_count,
+		uint8_t **sigp, uint *sig_len)
+{
+	return -ENXIO;
+}
+
+static inline int rsa_add_verify_data(struct image_sign_info *info,
+				      void *keydest)
+{
+	return -ENXIO;
+}
+#endif
+
+#if IMAGE_ENABLE_VERIFY
+/**
+ * rsa_verify() - Verify a signature against some data
+ *
+ * Verify a RSA PKCS1.5 signature against an expected hash.
+ *
+ * @info:	Specifies key and FIT information
+ * @data:	Pointer to the input data
+ * @data_len:	Data length
+ * @sig:	Signature
+ * @sig_len:	Number of bytes in signature
+ * @return 0 if verified, -ve on error
+ */
+int rsa_verify(struct image_sign_info *info,
+	       const struct image_region region[], int region_count,
+	       uint8_t *sig, uint sig_len);
+
+int padding_pkcs_15_verify(struct image_sign_info *info,
+			   uint8_t *msg, int msg_len,
+			   const uint8_t *hash, int hash_len);
+
+#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
+int padding_pss_verify(struct image_sign_info *info,
+		       uint8_t *msg, int msg_len,
+		       const uint8_t *hash, int hash_len);
+#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */
+#else
+static inline int rsa_verify(struct image_sign_info *info,
+		const struct image_region region[], int region_count,
+		uint8_t *sig, uint sig_len)
+{
+	return -ENXIO;
+}
+
+static inline int padding_pkcs_15_verify(struct image_sign_info *info,
+					 uint8_t *msg, int msg_len,
+					 const uint8_t *hash, int hash_len)
+{
+	return -ENXIO;
+}
+
+#ifdef CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
+static inline int padding_pss_verify(struct image_sign_info *info,
+				     uint8_t *msg, int msg_len,
+				     const uint8_t *hash, int hash_len)
+{
+	return -ENXIO;
+}
+#endif /* CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT */
+#endif
+
+#define RSA_DEFAULT_PADDING_NAME		"pkcs-1.5"
+
+#define RSA2048_BYTES	(2048 / 8)
+#define RSA4096_BYTES	(4096 / 8)
+
+/* This is the minimum/maximum key size we support, in bits */
+#define RSA_MIN_KEY_BITS	2048
+#define RSA_MAX_KEY_BITS	4096
+
+/* This is the maximum signature length that we support, in bits */
+#define RSA_MAX_SIG_BITS	4096
+
+#endif
diff --git a/include/u-boot/sha1.h b/include/u-boot/sha1.h
new file mode 100644
index 0000000..283f103
--- /dev/null
+++ b/include/u-boot/sha1.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: LGPL-2.1 */
+/**
+ * \file sha1.h
+ * based from http://xyssl.org/code/source/sha1/
+ *  FIPS-180-1 compliant SHA-1 implementation
+ *
+ *  Copyright (C) 2003-2006  Christophe Devine
+ */
+/*
+ *  The SHA-1 standard was published by NIST in 1993.
+ *
+ *  http://www.itl.nist.gov/fipspubs/fip180-1.htm
+ */
+#ifndef _SHA1_H
+#define _SHA1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SHA1_SUM_POS	-0x20
+#define SHA1_SUM_LEN	20
+#define SHA1_DER_LEN	15
+
+extern const uint8_t sha1_der_prefix[];
+
+/**
+ * \brief	   SHA-1 context structure
+ */
+typedef struct
+{
+    unsigned long total[2];	/*!< number of bytes processed	*/
+    unsigned long state[5];	/*!< intermediate digest state	*/
+    unsigned char buffer[64];	/*!< data block being processed */
+}
+sha1_context;
+
+/**
+ * \brief	   SHA-1 context setup
+ *
+ * \param ctx	   SHA-1 context to be initialized
+ */
+void sha1_starts( sha1_context *ctx );
+
+/**
+ * \brief	   SHA-1 process buffer
+ *
+ * \param ctx	   SHA-1 context
+ * \param input    buffer holding the  data
+ * \param ilen	   length of the input data
+ */
+void sha1_update(sha1_context *ctx, const unsigned char *input,
+		 unsigned int ilen);
+
+/**
+ * \brief	   SHA-1 final digest
+ *
+ * \param ctx	   SHA-1 context
+ * \param output   SHA-1 checksum result
+ */
+void sha1_finish( sha1_context *ctx, unsigned char output[20] );
+
+/**
+ * \brief	   Output = SHA-1( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen	   length of the input data
+ * \param output   SHA-1 checksum result
+ */
+void sha1_csum(const unsigned char *input, unsigned int ilen,
+		unsigned char *output);
+
+/**
+ * \brief	   Output = SHA-1( input buffer ), with watchdog triggering
+ *
+ * \param input    buffer holding the  data
+ * \param ilen	   length of the input data
+ * \param output   SHA-1 checksum result
+ * \param chunk_sz watchdog triggering period (in bytes of input processed)
+ */
+void sha1_csum_wd(const unsigned char *input, unsigned int ilen,
+		unsigned char *output, unsigned int chunk_sz);
+
+/**
+ * \brief	   Output = HMAC-SHA-1( input buffer, hmac key )
+ *
+ * \param key	   HMAC secret key
+ * \param keylen   length of the HMAC key
+ * \param input    buffer holding the  data
+ * \param ilen	   length of the input data
+ * \param output   HMAC-SHA-1 result
+ */
+void sha1_hmac(const unsigned char *key, int keylen,
+		const unsigned char *input, unsigned int ilen,
+		unsigned char *output);
+
+/**
+ * \brief	   Checkup routine
+ *
+ * \return	   0 if successful, or 1 if the test failed
+ */
+int sha1_self_test( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* sha1.h */
diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h
new file mode 100644
index 0000000..9aa1251
--- /dev/null
+++ b/include/u-boot/sha256.h
@@ -0,0 +1,25 @@
+#ifndef _SHA256_H
+#define _SHA256_H
+
+#define SHA256_SUM_LEN	32
+#define SHA256_DER_LEN	19
+
+extern const uint8_t sha256_der_prefix[];
+
+/* Reset watchdog each time we process this many bytes */
+#define CHUNKSZ_SHA256	(64 * 1024)
+
+typedef struct {
+	uint32_t total[2];
+	uint32_t state[8];
+	uint8_t buffer[64];
+} sha256_context;
+
+void sha256_starts(sha256_context * ctx);
+void sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length);
+void sha256_finish(sha256_context * ctx, uint8_t digest[SHA256_SUM_LEN]);
+
+void sha256_csum_wd(const unsigned char *input, unsigned int ilen,
+		unsigned char *output, unsigned int chunk_sz);
+
+#endif /* _SHA256_H */
diff --git a/include/u-boot/u-boot.lds.h b/include/u-boot/u-boot.lds.h
new file mode 100644
index 0000000..ead37d0
--- /dev/null
+++ b/include/u-boot/u-boot.lds.h
@@ -0,0 +1,25 @@
+/*
+ * Linker script helper macros
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __U_BOOT_LDS__
+#define __U_BOOT_LDS__
+
+/* See if the linker version is at least the specified version */
+#define LD_AT_LEAST(major, minor) \
+	((major > LD_MAJOR) || (major == LD_MAJOR && minor <= LD_MINOR))
+
+/*
+ * Linker versions prior to 2.16 don't understand the builtin
+ * functions SORT_BY_ALIGNMENT() and SORT_BY_NAME(), so disable these
+ */
+#if !LD_AT_LEAST(2, 16)
+# define SORT_BY_ALIGNMENT(x) x
+# define SORT_BY_NAME(x) x
+#endif
+
+#endif
diff --git a/include/u-boot/variadic-macro.h b/include/u-boot/variadic-macro.h
new file mode 100644
index 0000000..cb815d0
--- /dev/null
+++ b/include/u-boot/variadic-macro.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Helper for work with variadic macros
+ *
+ * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz
+ */
+
+#ifndef __VARIADIC_MACRO_H__
+#define __VARIADIC_MACRO_H__
+
+#define _VM_GET_NTH_ARG(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, \
+	_14, _15, _16, _17, _18, _19, _20, _21, _22, _23, _24, _25, _26, _27, \
+	_28, _29, _30, _31, _32, N, ...) N
+
+#define _VM_HELP_0(_call, ...)
+#define _VM_HELP_1(_call, x, ...) _call(x)
+#define _VM_HELP_2(_call, x, ...) _call(x) _VM_HELP_1(_call, __VA_ARGS__)
+#define _VM_HELP_3(_call, x, ...) _call(x) _VM_HELP_2(_call, __VA_ARGS__)
+#define _VM_HELP_4(_call, x, ...) _call(x) _VM_HELP_3(_call, __VA_ARGS__)
+#define _VM_HELP_5(_call, x, ...) _call(x) _VM_HELP_4(_call, __VA_ARGS__)
+#define _VM_HELP_6(_call, x, ...) _call(x) _VM_HELP_5(_call, __VA_ARGS__)
+#define _VM_HELP_7(_call, x, ...) _call(x) _VM_HELP_6(_call, __VA_ARGS__)
+#define _VM_HELP_8(_call, x, ...) _call(x) _VM_HELP_7(_call, __VA_ARGS__)
+#define _VM_HELP_9(_call, x, ...) _call(x) _VM_HELP_8(_call, __VA_ARGS__)
+#define _VM_HELP_10(_call, x, ...) _call(x) _VM_HELP_9(_call, __VA_ARGS__)
+#define _VM_HELP_11(_call, x, ...) _call(x) _VM_HELP_10(_call, __VA_ARGS__)
+#define _VM_HELP_12(_call, x, ...) _call(x) _VM_HELP_11(_call, __VA_ARGS__)
+#define _VM_HELP_13(_call, x, ...) _call(x) _VM_HELP_12(_call, __VA_ARGS__)
+#define _VM_HELP_14(_call, x, ...) _call(x) _VM_HELP_13(_call, __VA_ARGS__)
+#define _VM_HELP_15(_call, x, ...) _call(x) _VM_HELP_14(_call, __VA_ARGS__)
+#define _VM_HELP_16(_call, x, ...) _call(x) _VM_HELP_15(_call, __VA_ARGS__)
+#define _VM_HELP_17(_call, x, ...) _call(x) _VM_HELP_16(_call, __VA_ARGS__)
+#define _VM_HELP_18(_call, x, ...) _call(x) _VM_HELP_17(_call, __VA_ARGS__)
+#define _VM_HELP_19(_call, x, ...) _call(x) _VM_HELP_18(_call, __VA_ARGS__)
+#define _VM_HELP_20(_call, x, ...) _call(x) _VM_HELP_19(_call, __VA_ARGS__)
+#define _VM_HELP_21(_call, x, ...) _call(x) _VM_HELP_20(_call, __VA_ARGS__)
+#define _VM_HELP_22(_call, x, ...) _call(x) _VM_HELP_21(_call, __VA_ARGS__)
+#define _VM_HELP_23(_call, x, ...) _call(x) _VM_HELP_22(_call, __VA_ARGS__)
+#define _VM_HELP_24(_call, x, ...) _call(x) _VM_HELP_23(_call, __VA_ARGS__)
+#define _VM_HELP_25(_call, x, ...) _call(x) _VM_HELP_24(_call, __VA_ARGS__)
+#define _VM_HELP_26(_call, x, ...) _call(x) _VM_HELP_25(_call, __VA_ARGS__)
+#define _VM_HELP_27(_call, x, ...) _call(x) _VM_HELP_26(_call, __VA_ARGS__)
+#define _VM_HELP_28(_call, x, ...) _call(x) _VM_HELP_27(_call, __VA_ARGS__)
+#define _VM_HELP_29(_call, x, ...) _call(x) _VM_HELP_28(_call, __VA_ARGS__)
+#define _VM_HELP_30(_call, x, ...) _call(x) _VM_HELP_29(_call, __VA_ARGS__)
+#define _VM_HELP_31(_call, x, ...) _call(x) _VM_HELP_30(_call, __VA_ARGS__)
+
+#define CALL_MACRO_FOR_EACH(x, ...)					 \
+	_VM_GET_NTH_ARG("", ##__VA_ARGS__, _VM_HELP_31, _VM_HELP_30,	 \
+	_VM_HELP_29, _VM_HELP_28, _VM_HELP_27, _VM_HELP_26, _VM_HELP_25, \
+	_VM_HELP_24, _VM_HELP_23, _VM_HELP_22, _VM_HELP_21, _VM_HELP_20, \
+	_VM_HELP_19, _VM_HELP_18, _VM_HELP_17, _VM_HELP_16, _VM_HELP_15, \
+	_VM_HELP_14, _VM_HELP_13, _VM_HELP_12, _VM_HELP_11, _VM_HELP_10, \
+	_VM_HELP_9, _VM_HELP_8, _VM_HELP_7, _VM_HELP_6, _VM_HELP_5,	 \
+	_VM_HELP_4, _VM_HELP_3, _VM_HELP_2, _VM_HELP_1,			 \
+	_VM_HELP_0)(x, __VA_ARGS__)
+
+#endif /* __VARIADIC_MACRO_H__ */
diff --git a/include/u-boot/zlib.h b/include/u-boot/zlib.h
new file mode 100644
index 0000000..e23ceb5
--- /dev/null
+++ b/include/u-boot/zlib.h
@@ -0,0 +1,731 @@
+/*
+ * This file is derived from zlib.h and zconf.h from the zlib-1.2.3
+ * distribution by Jean-loup Gailly and Mark Adler, with some additions
+ * by Paul Mackerras to aid in implementing Deflate compression and
+ * decompression for PPP packets.
+ */
+
+ /*
+  * ==FILEVERSION 960122==
+  *
+  * This marker is used by the Linux installation script to determine
+  * whether an up-to-date version of this file is already installed.
+  */
+
+/* zlib.h -- interface of the 'zlib' general purpose compression library
+  version 1.2.3, July 18th, 2005
+
+  Copyright (C) 1995-2005 Jean-loup Gailly and Mark Adler
+
+  This software is provided 'as-is', without any express or implied
+  warranty.  In no event will the authors be held liable for any damages
+  arising from the use of this software.
+
+  Permission is granted to anyone to use this software for any purpose,
+  including commercial applications, and to alter it and redistribute it
+  freely, subject to the following restrictions:
+
+  1. The origin of this software must not be misrepresented; you must not
+     claim that you wrote the original software. If you use this software
+     in a product, an acknowledgment in the product documentation would be
+     appreciated but is not required.
+  2. Altered source versions must be plainly marked as such, and must not be
+     misrepresented as being the original software.
+  3. This notice may not be removed or altered from any source distribution.
+
+  Jean-loup Gailly        Mark Adler
+  jloup@gzip.org          madler@alumni.caltech.edu
+
+
+  The data format used by the zlib library is described by RFCs (Request for
+  Comments) 1950 to 1952 in the files http://www.ietf.org/rfc/rfc1950.txt
+  (zlib format), rfc1951.txt (deflate format) and rfc1952.txt (gzip format).
+*/
+
+#ifndef ZLIB_H
+#define ZLIB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ZLIB_VERSION "1.2.3"
+#define ZLIB_VERNUM 0x1230
+
+/* #include "zconf.h" */        /* included directly here */
+/* zconf.h -- configuration of the zlib compression library
+ * Copyright (C) 1995-2005 Jean-loup Gailly.
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+/* Begin of new zconf.h */
+/*
+ * If you *really* need a unique prefix for all types and library functions,
+ * compile with -DZ_PREFIX. The "standard" zlib should be compiled without it.
+ */
+#ifdef Z_PREFIX
+#  define deflateInit_          z_deflateInit_
+#  define deflate               z_deflate
+#  define deflateEnd            z_deflateEnd
+#  define inflateInit_          z_inflateInit_
+#  define inflate               z_inflate
+#  define inflateEnd            z_inflateEnd
+#  define deflateInit2_         z_deflateInit2_
+#  define deflateSetDictionary  z_deflateSetDictionary
+#  define deflateCopy           z_deflateCopy
+#  define deflateReset          z_deflateReset
+#  define deflateParams         z_deflateParams
+#  define deflateBound          z_deflateBound
+#  define deflatePrime          z_deflatePrime
+#  define inflateInit2_         z_inflateInit2_
+#  define inflateSetDictionary  z_inflateSetDictionary
+#  define inflateSync           z_inflateSync
+#  define inflateSyncPoint      z_inflateSyncPoint
+#  define inflateCopy           z_inflateCopy
+#  define inflateReset          z_inflateReset
+#  define inflateBack           z_inflateBack
+#  define inflateBackEnd        z_inflateBackEnd
+#  define compress              z_compress
+#  define compress2             z_compress2
+#  define compressBound         z_compressBound
+#  define uncompress            z_uncompress
+#  define adler32               z_adler32
+#  define crc32                 z_crc32
+#  define get_crc_table         z_get_crc_table
+#  define zError                z_zError
+
+#  define alloc_func            z_alloc_func
+#  define free_func             z_free_func
+#  define in_func               z_in_func
+#  define out_func              z_out_func
+#  define Byte                  z_Byte
+#  define uInt                  z_uInt
+#  define uLong                 z_uLong
+#  define Bytef                 z_Bytef
+#  define charf                 z_charf
+#  define intf                  z_intf
+#  define uIntf                 z_uIntf
+#  define uLongf                z_uLongf
+#  define voidpf                z_voidpf
+#  define voidp                 z_voidp
+#endif
+
+#if defined(__MSDOS__) && !defined(MSDOS)
+#  define MSDOS
+#endif
+#if (defined(OS_2) || defined(__OS2__)) && !defined(OS2)
+#  define OS2
+#endif
+#if defined(_WINDOWS) && !defined(WINDOWS)
+#  define WINDOWS
+#endif
+#if defined(_WIN32) || defined(_WIN32_WCE) || defined(__WIN32__)
+#  ifndef WIN32
+#    define WIN32
+#  endif
+#endif
+#if (defined(MSDOS) || defined(OS2) || defined(WINDOWS)) && !defined(WIN32)
+#  if !defined(__GNUC__) && !defined(__FLAT__) && !defined(__386__)
+#    ifndef SYS16BIT
+#      define SYS16BIT
+#    endif
+#  endif
+#endif
+
+/*
+ * Compile with -DMAXSEG_64K if the alloc function cannot allocate more
+ * than 64k bytes at a time (needed on systems with 16-bit int).
+ */
+#ifdef SYS16BIT
+#  define MAXSEG_64K
+#endif
+#ifdef MSDOS
+#  define UNALIGNED_OK
+#endif
+
+#ifdef __STDC_VERSION__
+#  ifndef STDC
+#    define STDC
+#  endif
+#  if __STDC_VERSION__ >= 199901L
+#    ifndef STDC99
+#      define STDC99
+#    endif
+#  endif
+#endif
+#if !defined(STDC) && (defined(__STDC__) || defined(__cplusplus))
+#  define STDC
+#endif
+#if !defined(STDC) && (defined(__GNUC__) || defined(__BORLANDC__))
+#  define STDC
+#endif
+#if !defined(STDC) && (defined(MSDOS) || defined(WINDOWS) || defined(WIN32))
+#  define STDC
+#endif
+#if !defined(STDC) && (defined(OS2) || defined(__HOS_AIX__))
+#  define STDC
+#endif
+
+#if defined(__OS400__) && !defined(STDC)    /* iSeries (formerly AS/400). */
+#  define STDC
+#endif
+
+#ifndef STDC
+#  ifndef const /* cannot use !defined(STDC) && !defined(const) on Mac */
+#    define const       /* note: need a more gentle solution here */
+#  endif
+#endif
+
+/* Some Mac compilers merge all .h files incorrectly: */
+#if defined(__MWERKS__)||defined(applec)||defined(THINK_C)||defined(__SC__)
+#  define NO_DUMMY_DECL
+#endif
+
+/* Maximum value for memLevel in deflateInit2 */
+#ifndef MAX_MEM_LEVEL
+#  ifdef MAXSEG_64K
+#    define MAX_MEM_LEVEL 8
+#  else
+#    define MAX_MEM_LEVEL 9
+#  endif
+#endif
+
+/* Maximum value for windowBits in deflateInit2 and inflateInit2.
+ * WARNING: reducing MAX_WBITS makes minigzip unable to extract .gz files
+ * created by gzip. (Files created by minigzip can still be extracted by
+ * gzip.)
+ */
+#ifndef MAX_WBITS
+#  define MAX_WBITS   15 /* 32K LZ77 window */
+#endif
+
+/* The memory requirements for deflate are (in bytes):
+            (1 << (windowBits+2)) +  (1 << (memLevel+9))
+ that is: 128K for windowBits=15  +  128K for memLevel = 8  (default values)
+ plus a few kilobytes for small objects. For example, if you want to reduce
+ the default memory requirements from 256K to 128K, compile with
+     make CFLAGS="-O -DMAX_WBITS=14 -DMAX_MEM_LEVEL=7"
+ Of course this will generally degrade compression (there's no free lunch).
+
+   The memory requirements for inflate are (in bytes) 1 << windowBits
+ that is, 32K for windowBits=15 (default value) plus a few kilobytes
+ for small objects.
+*/
+
+                        /* Type declarations */
+
+#ifndef OF /* function prototypes */
+#  ifdef STDC
+#    define OF(args)  args
+#  else
+#    define OF(args)  ()
+#  endif
+#endif
+
+/* The following definitions for FAR are needed only for MSDOS mixed
+ * model programming (small or medium model with some far allocations).
+ * This was tested only with MSC; for other MSDOS compilers you may have
+ * to define NO_MEMCPY in zutil.h.  If you don't need the mixed model,
+ * just define FAR to be empty.
+ */
+#ifdef SYS16BIT
+#  if defined(M_I86SM) || defined(M_I86MM)
+     /* MSC small or medium model */
+#    define SMALL_MEDIUM
+#    ifdef _MSC_VER
+#      define FAR _far
+#    else
+#      define FAR far
+#    endif
+#  endif
+#  if (defined(__SMALL__) || defined(__MEDIUM__))
+     /* Turbo C small or medium model */
+#    define SMALL_MEDIUM
+#    ifdef __BORLANDC__
+#      define FAR _far
+#    else
+#      define FAR far
+#    endif
+#  endif
+#endif
+
+#if defined(WINDOWS) || defined(WIN32)
+   /* If building or using zlib as a DLL, define ZLIB_DLL.
+    * This is not mandatory, but it offers a little performance increase.
+    */
+#  ifdef ZLIB_DLL
+#    if defined(WIN32) && (!defined(__BORLANDC__) || (__BORLANDC__ >= 0x500))
+#      ifdef ZLIB_INTERNAL
+#        define ZEXTERN extern __declspec(dllexport)
+#      else
+#        define ZEXTERN extern __declspec(dllimport)
+#      endif
+#    endif
+#  endif  /* ZLIB_DLL */
+   /* If building or using zlib with the WINAPI/WINAPIV calling convention,
+    * define ZLIB_WINAPI.
+    * Caution: the standard ZLIB1.DLL is NOT compiled using ZLIB_WINAPI.
+    */
+#  ifdef ZLIB_WINAPI
+#    ifdef FAR
+#      undef FAR
+#    endif
+#    include <windows.h>
+     /* No need for _export, use ZLIB.DEF instead. */
+     /* For complete Windows compatibility, use WINAPI, not __stdcall. */
+#    define ZEXPORT WINAPI
+#    ifdef WIN32
+#      define ZEXPORTVA WINAPIV
+#    else
+#      define ZEXPORTVA FAR CDECL
+#    endif
+#  endif
+#endif
+
+#if defined (__BEOS__)
+#  ifdef ZLIB_DLL
+#    ifdef ZLIB_INTERNAL
+#      define ZEXPORT   __declspec(dllexport)
+#      define ZEXPORTVA __declspec(dllexport)
+#    else
+#      define ZEXPORT   __declspec(dllimport)
+#      define ZEXPORTVA __declspec(dllimport)
+#    endif
+#  endif
+#endif
+
+#ifndef ZEXTERN
+#  define ZEXTERN extern
+#endif
+#ifndef ZEXPORT
+#  define ZEXPORT
+#endif
+#ifndef ZEXPORTVA
+#  define ZEXPORTVA
+#endif
+
+#ifndef FAR
+#  define FAR
+#endif
+
+#if !defined(__MACTYPES__)
+typedef unsigned char  Byte;  /* 8 bits */
+#endif
+typedef unsigned int   uInt;  /* 16 bits or more */
+typedef unsigned long  uLong; /* 32 bits or more */
+
+#ifdef SMALL_MEDIUM
+   /* Borland C/C++ and some old MSC versions ignore FAR inside typedef */
+#  define Bytef Byte FAR
+#else
+   typedef Byte  FAR Bytef;
+#endif
+typedef char  FAR charf;
+typedef int   FAR intf;
+typedef uInt  FAR uIntf;
+typedef uLong FAR uLongf;
+
+#ifdef STDC
+   typedef void const *voidpc;
+   typedef void FAR   *voidpf;
+   typedef void       *voidp;
+#else
+   typedef Byte const *voidpc;
+   typedef Byte FAR   *voidpf;
+   typedef Byte       *voidp;
+#endif
+
+#  ifdef VMS
+#    include <unixio.h>   /* for off_t */
+#  endif
+#  define z_off_t off_t
+#ifndef SEEK_SET
+#  define SEEK_SET        0       /* Seek from beginning of file.  */
+#  define SEEK_CUR        1       /* Seek from current position.  */
+#  define SEEK_END        2       /* Set file pointer to EOF plus "offset" */
+#endif
+#ifndef z_off_t
+#  define z_off_t long
+#endif
+
+#if defined(__OS400__)
+#  define NO_vsnprintf
+#endif
+
+#if defined(__MVS__)
+#  define NO_vsnprintf
+#  ifdef FAR
+#    undef FAR
+#  endif
+#endif
+
+/* MVS linker does not support external names larger than 8 bytes */
+#if defined(__MVS__)
+#   pragma map(deflateInit_,"DEIN")
+#   pragma map(deflateInit2_,"DEIN2")
+#   pragma map(deflateEnd,"DEEND")
+#   pragma map(deflateBound,"DEBND")
+#   pragma map(inflateInit_,"ININ")
+#   pragma map(inflateInit2_,"ININ2")
+#   pragma map(inflateEnd,"INEND")
+#   pragma map(inflateSync,"INSY")
+#   pragma map(inflateSetDictionary,"INSEDI")
+#   pragma map(compressBound,"CMBND")
+#   pragma map(inflate_table,"INTABL")
+#   pragma map(inflate_fast,"INFA")
+#   pragma map(inflate_copyright,"INCOPY")
+#endif
+/* End of new zconf.h */
+
+/*
+     The 'zlib' compression library provides in-memory compression and
+  decompression functions, including integrity checks of the uncompressed
+  data.  This version of the library supports only one compression method
+  (deflation) but other algorithms will be added later and will have the same
+  stream interface.
+
+     Compression can be done in a single step if the buffers are large
+  enough (for example if an input file is mmap'ed), or can be done by
+  repeated calls of the compression function.  In the latter case, the
+  application must provide more input and/or consume the output
+  (providing more output space) before each call.
+
+     The compressed data format used by default by the in-memory functions is
+  the zlib format, which is a zlib wrapper documented in RFC 1950, wrapped
+  around a deflate stream, which is itself documented in RFC 1951.
+
+     The library also supports reading and writing files in gzip (.gz) format
+  with an interface similar to that of stdio using the functions that start
+  with "gz".  The gzip format is different from the zlib format.  gzip is a
+  gzip wrapper, documented in RFC 1952, wrapped around a deflate stream.
+
+     This library can optionally read and write gzip streams in memory as well.
+
+     The zlib format was designed to be compact and fast for use in memory
+  and on communications channels.  The gzip format was designed for single-
+  file compression on file systems, has a larger header than zlib to maintain
+  directory information, and uses a different, slower check method than zlib.
+
+     The library does not install any signal handler. The decoder checks
+  the consistency of the compressed data, so the library should never
+  crash even in case of corrupted input.
+*/
+
+typedef voidpf (*alloc_func) OF((voidpf opaque, uInt items, uInt size));
+typedef void   (*free_func)  OF((voidpf opaque, voidpf address, uInt size));
+typedef void   (*cb_func)    OF((Bytef *buf, uInt len));
+
+struct internal_state;
+
+typedef struct z_stream_s {
+	Bytef	*next_in; /* next input byte */
+	uInt	avail_in; /* number of bytes available at next_in */
+	uLong	total_in; /* total nb of input bytes read so far */
+	Bytef	*next_out; /* next output byte should be put there */
+	uInt	avail_out; /* remaining free space at next_out */
+	uLong	total_out; /* total nb of bytes output so far */
+	char	*msg;	/* last error message, NULL if no error */
+	struct	internal_state FAR *state; /* not visible by applications */
+	alloc_func	zalloc;	/* used to allocate the internal state */
+	free_func	zfree;	/* used to free the internal state */
+	voidpf	opaque;	/* private data object passed to zalloc and zfree */
+	int	data_type;	/* best guess about the data type:
+					binary or text */
+	cb_func	outcb;	/* called regularly just before blocks of output */
+	uLong	adler;	/* adler32 value of the uncompressed data */
+	uLong	reserved;	/* reserved for future use */
+} z_stream;
+
+typedef z_stream FAR *z_streamp;
+
+/*
+     gzip header information passed to and from zlib routines.  See RFC 1952
+  for more details on the meanings of these fields.
+*/
+typedef struct gz_header_s {
+	int	text;	/* true if compressed data believed to be text */
+	uLong	time;	/* modification time */
+	int	xflags;	/* extra flags (not used when writing a gzip file) */
+	int	os;	/* operating system */
+	Bytef	*extra;	/* pointer to extra field or Z_NULL if none */
+	uInt	extra_len; /* extra field length (valid if extra != Z_NULL) */
+	uInt	extra_max; /* space at extra (only when reading header) */
+	Bytef	*name; /* pointer to zero-terminated file name or Z_NULL */
+	uInt	name_max; /* space at name (only when reading header) */
+	Bytef	*comment; /* pointer to zero-terminated comment or Z_NULL */
+	uInt	comm_max; /* space at comment (only when reading header) */
+	int	hcrc; /* true if there was or will be a header crc */
+	int	done; /* true when done reading gzip header (not used
+			when writing a gzip file) */
+} gz_header;
+
+typedef gz_header FAR *gz_headerp;
+
+                        /* constants */
+#define Z_NO_FLUSH      0
+#define Z_PARTIAL_FLUSH 1 /* will be removed, use Z_SYNC_FLUSH instead */
+#define Z_SYNC_FLUSH    2
+#define Z_FULL_FLUSH    3
+#define Z_FINISH        4
+#define Z_BLOCK         5
+/* Allowed flush values; see deflate() and inflate() below for details */
+
+#define Z_OK            0
+#define Z_STREAM_END    1
+#define Z_NEED_DICT     2
+#define Z_ERRNO        (-1)
+#define Z_STREAM_ERROR (-2)
+#define Z_DATA_ERROR   (-3)
+#define Z_MEM_ERROR    (-4)
+#define Z_BUF_ERROR    (-5)
+#define Z_VERSION_ERROR (-6)
+/* Return codes for the compression/decompression functions. Negative
+ * values are errors, positive values are used for special but normal events.
+ */
+
+#define Z_NO_COMPRESSION         0
+#define Z_BEST_SPEED             1
+#define Z_BEST_COMPRESSION       9
+#define Z_DEFAULT_COMPRESSION  (-1)
+/* compression levels */
+
+#define Z_FILTERED            1
+#define Z_HUFFMAN_ONLY        2
+#define Z_RLE                 3
+#define Z_FIXED               4
+#define Z_DEFAULT_STRATEGY    0
+/* compression strategy; see deflateInit2() below for details */
+
+#define Z_BINARY   0
+#define Z_TEXT     1
+#define Z_ASCII    Z_TEXT   /* for compatibility with 1.2.2 and earlier */
+#define Z_UNKNOWN  2
+/* Possible values of the data_type field (though see inflate()) */
+
+#define Z_DEFLATED   8
+/* The deflate compression method (the only one supported in this version) */
+
+#define Z_NULL  (void *)0  /* for initializing zalloc, zfree, opaque */
+
+                        /* basic functions */
+
+/* The application can compare zlibVersion and ZLIB_VERSION for consistency.
+   If the first character differs, the library code actually used is
+   not compatible with the zlib.h header file used by the application.
+   This check is automatically made by deflateInit and inflateInit.
+   */
+
+ZEXTERN int ZEXPORT deflate OF((z_streamp strm, int flush));
+ZEXTERN int ZEXPORT deflateInit_ OF((z_streamp strm, int level,
+			const char *version, int stream_size));
+ZEXTERN int ZEXPORT deflateEnd OF((z_streamp strm));
+ZEXTERN int ZEXPORT deflateInit2_ OF((z_streamp strm, int  level, int  method,
+			int windowBits, int memLevel,
+			int strategy, const char *version,
+			int stream_size));
+ZEXTERN int ZEXPORT deflateReset OF((z_streamp strm));
+ZEXTERN int ZEXPORT deflateSetDictionary OF((z_streamp strm,
+			const Bytef *dictionary,
+			uInt  dictLength));
+ZEXTERN int ZEXPORT deflateSetHeader OF((z_streamp strm,
+			gz_headerp head));
+ZEXTERN int ZEXPORT deflatePrime OF((z_streamp strm,
+			int bits,
+			int value));
+ZEXTERN int ZEXPORT deflateParams OF((z_streamp strm,
+			int level,
+			int strategy));
+ZEXTERN int ZEXPORT deflateTune OF((z_streamp strm,
+			int good_length,
+			int max_lazy,
+			int nice_length,
+			int max_chain));
+ZEXTERN uLong ZEXPORT deflateBound OF((z_streamp strm,
+			uLong sourceLen));
+ZEXTERN int ZEXPORT deflateCopy OF((z_streamp dest,
+			z_streamp source));
+
+
+ZEXTERN int ZEXPORT inflateInit_ OF((z_streamp strm,
+			const char *version, int stream_size));
+ZEXTERN int ZEXPORT inflate OF((z_streamp strm, int flush));
+/*
+    inflate decompresses as much data as possible, and stops when the input
+  buffer becomes empty or the output buffer becomes full. It may introduce
+  some output latency (reading input without producing any output) except when
+  forced to flush.
+
+  The detailed semantics are as follows. inflate performs one or both of the
+  following actions:
+
+  - Decompress more input starting at next_in and update next_in and avail_in
+    accordingly. If not all input can be processed (because there is not
+    enough room in the output buffer), next_in is updated and processing
+    will resume at this point for the next call of inflate().
+
+  - Provide more output starting at next_out and update next_out and avail_out
+    accordingly.  inflate() provides as much output as possible, until there
+    is no more input data or no more space in the output buffer (see below
+    about the flush parameter).
+
+  Before the call of inflate(), the application should ensure that at least
+  one of the actions is possible, by providing more input and/or consuming
+  more output, and updating the next_* and avail_* values accordingly.
+  The application can consume the uncompressed output when it wants, for
+  example when the output buffer is full (avail_out == 0), or after each
+  call of inflate(). If inflate returns Z_OK and with zero avail_out, it
+  must be called again after making room in the output buffer because there
+  might be more output pending.
+
+    The flush parameter of inflate() can be Z_NO_FLUSH, Z_SYNC_FLUSH,
+  Z_FINISH, or Z_BLOCK. Z_SYNC_FLUSH requests that inflate() flush as much
+  output as possible to the output buffer. Z_BLOCK requests that inflate() stop
+  if and when it gets to the next deflate block boundary. When decoding the
+  zlib or gzip format, this will cause inflate() to return immediately after
+  the header and before the first block. When doing a raw inflate, inflate()
+  will go ahead and process the first block, and will return when it gets to
+  the end of that block, or when it runs out of data.
+
+    The Z_BLOCK option assists in appending to or combining deflate streams.
+  Also to assist in this, on return inflate() will set strm->data_type to the
+  number of unused bits in the last byte taken from strm->next_in, plus 64
+  if inflate() is currently decoding the last block in the deflate stream,
+  plus 128 if inflate() returned immediately after decoding an end-of-block
+  code or decoding the complete header up to just before the first byte of the
+  deflate stream. The end-of-block will not be indicated until all of the
+  uncompressed data from that block has been written to strm->next_out.  The
+  number of unused bits may in general be greater than seven, except when
+  bit 7 of data_type is set, in which case the number of unused bits will be
+  less than eight.
+
+    inflate() should normally be called until it returns Z_STREAM_END or an
+  error. However if all decompression is to be performed in a single step
+  (a single call of inflate), the parameter flush should be set to
+  Z_FINISH. In this case all pending input is processed and all pending
+  output is flushed; avail_out must be large enough to hold all the
+  uncompressed data. (The size of the uncompressed data may have been saved
+  by the compressor for this purpose.) The next operation on this stream must
+  be inflateEnd to deallocate the decompression state. The use of Z_FINISH
+  is never required, but can be used to inform inflate that a faster approach
+  may be used for the single inflate() call.
+
+     In this implementation, inflate() always flushes as much output as
+  possible to the output buffer, and always uses the faster approach on the
+  first call. So the only effect of the flush parameter in this implementation
+  is on the return value of inflate(), as noted below, or when it returns early
+  because Z_BLOCK is used.
+
+     If a preset dictionary is needed after this call (see inflateSetDictionary
+  below), inflate sets strm->adler to the adler32 checksum of the dictionary
+  chosen by the compressor and returns Z_NEED_DICT; otherwise it sets
+  strm->adler to the adler32 checksum of all output produced so far (that is,
+  total_out bytes) and returns Z_OK, Z_STREAM_END or an error code as described
+  below. At the end of the stream, inflate() checks that its computed adler32
+  checksum is equal to that saved by the compressor and returns Z_STREAM_END
+  only if the checksum is correct.
+
+    inflate() will decompress and check either zlib-wrapped or gzip-wrapped
+  deflate data.  The header type is detected automatically.  Any information
+  contained in the gzip header is not retained, so applications that need that
+  information should instead use raw inflate, see inflateInit2() below, or
+  inflateBack() and perform their own processing of the gzip header and
+  trailer.
+
+    inflate() returns Z_OK if some progress has been made (more input processed
+  or more output produced), Z_STREAM_END if the end of the compressed data has
+  been reached and all uncompressed output has been produced, Z_NEED_DICT if a
+  preset dictionary is needed at this point, Z_DATA_ERROR if the input data was
+  corrupted (input stream not conforming to the zlib format or incorrect check
+  value), Z_STREAM_ERROR if the stream structure was inconsistent (for example
+  if next_in or next_out was NULL), Z_MEM_ERROR if there was not enough memory,
+  Z_BUF_ERROR if no progress is possible or if there was not enough room in the
+  output buffer when Z_FINISH is used. Note that Z_BUF_ERROR is not fatal, and
+  inflate() can be called again with more input and more output space to
+  continue decompressing. If Z_DATA_ERROR is returned, the application may then
+  call inflateSync() to look for a good compression block if a partial recovery
+  of the data is desired.
+*/
+
+ZEXTERN int ZEXPORT inflateEnd OF((z_streamp strm));
+/*
+     All dynamically allocated data structures for this stream are freed.
+   This function discards any unprocessed input and does not flush any
+   pending output.
+
+     inflateEnd returns Z_OK if success, Z_STREAM_ERROR if the stream state
+   was inconsistent. In the error case, msg may be set but then points to a
+   static string (which must not be deallocated).
+*/
+
+                        /* Advanced functions */
+
+ZEXTERN int ZEXPORT inflateReset OF((z_streamp strm));
+
+                        /* utility functions */
+
+/*
+     The following utility functions are implemented on top of the
+   basic stream-oriented functions. To simplify the interface, some
+   default options are assumed (compression level and memory usage,
+   standard memory allocation functions). The source code of these
+   utility functions can easily be modified if you need special options.
+*/
+
+ZEXTERN uLong ZEXPORT adler32 OF((uLong adler, const Bytef *buf, uInt len));
+/*
+     Update a running Adler-32 checksum with the bytes buf[0..len-1] and
+   return the updated checksum. If buf is NULL, this function returns
+   the required initial value for the checksum.
+   An Adler-32 checksum is almost as reliable as a CRC32 but can be computed
+   much faster. Usage example:
+
+     uLong adler = adler32(0L, Z_NULL, 0);
+
+     while (read_buffer(buffer, length) != EOF) {
+       adler = adler32(adler, buffer, length);
+     }
+     if (adler != original_adler) error();
+*/
+
+/*
+     Combine two Adler-32 checksums into one.  For two sequences of bytes, seq1
+   and seq2 with lengths len1 and len2, Adler-32 checksums were calculated for
+   each, adler1 and adler2.  adler32_combine() returns the Adler-32 checksum of
+   seq1 and seq2 concatenated, requiring only adler1, adler2, and len2.
+*/
+
+ZEXTERN  uInt ZEXPORT crc32  OF((uInt crc, const Bytef *buf, uInt len));
+/*
+     Update a running CRC-32 with the bytes buf[0..len-1] and return the
+   updated CRC-32. If buf is NULL, this function returns the required initial
+   value for the for the crc. Pre- and post-conditioning (one's complement) is
+   performed within this function so it shouldn't be done by the application.
+   Usage example:
+
+     uLong crc = crc32(0L, Z_NULL, 0);
+
+     while (read_buffer(buffer, length) != EOF) {
+       crc = crc32(crc, buffer, length);
+     }
+     if (crc != original_crc) error();
+*/
+
+ZEXTERN int ZEXPORT inflateInit2_ OF((z_streamp strm, int  windowBits,
+                                      const char *version, int stream_size));
+#define inflateInit(strm) \
+	inflateInit_((strm), ZLIB_VERSION, sizeof(z_stream))
+#define inflateInit2(strm, windowBits) \
+	inflateInit2_((strm), (windowBits), ZLIB_VERSION, sizeof(z_stream))
+
+#if !defined(ZUTIL_H) && !defined(NO_DUMMY_DECL)
+	struct internal_state {int dummy;}; /* hack for buggy compilers */
+#endif
+
+extern void *gzalloc(void *, unsigned, unsigned);
+extern void gzfree(void *, void *, unsigned);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZLIB_H */
diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h
new file mode 100644
index 0000000..0770228
--- /dev/null
+++ b/include/ubi_uboot.h
@@ -0,0 +1,81 @@
+/*
+ * Header file for UBI support for U-Boot
+ *
+ * Adaptation from kernel to U-Boot
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __UBOOT_UBI_H
+#define __UBOOT_UBI_H
+
+#include <common.h>
+#include <compiler.h>
+#include <linux/compat.h>
+#include <malloc.h>
+#include <div64.h>
+#include <linux/math64.h>
+#include <linux/crc32.h>
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/rbtree.h>
+#include <linux/string.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/ubi.h>
+
+#ifdef CONFIG_CMD_ONENAND
+#include <onenand_uboot.h>
+#endif
+
+#include <linux/errno.h>
+
+/* configurable */
+#define CONFIG_MTD_UBI_BEB_RESERVE	1
+
+/* debug options (Linux: drivers/mtd/ubi/Kconfig.debug) */
+#undef CONFIG_MTD_UBI_DEBUG
+#undef CONFIG_MTD_UBI_DEBUG_PARANOID
+#undef CONFIG_MTD_UBI_DEBUG_MSG
+#undef CONFIG_MTD_UBI_DEBUG_MSG_EBA
+#undef CONFIG_MTD_UBI_DEBUG_MSG_WL
+#undef CONFIG_MTD_UBI_DEBUG_MSG_IO
+#undef CONFIG_MTD_UBI_DEBUG_MSG_BLD
+
+#undef CONFIG_MTD_UBI_BLOCK
+
+/* ubi_init() disables returning error codes when built into the Linux
+ * kernel so that it doesn't hang the Linux kernel boot process.  Since
+ * the U-Boot driver code depends on getting valid error codes from this
+ * function we just tell the UBI layer that we are building as a module
+ * (which only enables the additional error reporting).
+ */
+#define CONFIG_MTD_UBI_MODULE
+
+/* build.c */
+#define get_device(...)
+#define put_device(...)
+#define ubi_sysfs_init(...)		0
+#define ubi_sysfs_close(...)		do { } while (0)
+
+#ifndef __UBIFS_H__
+#include "../drivers/mtd/ubi/ubi.h"
+#endif
+
+/* functions */
+extern int ubi_mtd_param_parse(const char *val, struct kernel_param *kp);
+extern int ubi_init(void);
+extern void ubi_exit(void);
+extern int ubi_part(char *part_name, const char *vid_header_offset);
+extern int ubi_volume_write(char *volume, void *buf, size_t size);
+extern int ubi_volume_read(char *volume, char *buf, size_t size);
+
+extern struct ubi_device *ubi_devices[];
+int cmd_ubifs_mount(char *vol_name);
+int cmd_ubifs_umount(void);
+
+#endif
diff --git a/include/ubifs_uboot.h b/include/ubifs_uboot.h
new file mode 100644
index 0000000..015ce12
--- /dev/null
+++ b/include/ubifs_uboot.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * UBIFS u-boot wrapper functions header
+ *
+ * Copyright (C) 2006-2008 Nokia Corporation
+ *
+ * (C) Copyright 2008-2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Authors: Artem Bityutskiy (Битюцкий �ртём)
+ *          Adrian Hunter
+ */
+
+#ifndef __UBIFS_UBOOT_H__
+#define __UBIFS_UBOOT_H__
+
+int ubifs_init(void);
+int uboot_ubifs_mount(char *vol_name);
+void uboot_ubifs_umount(void);
+int ubifs_is_mounted(void);
+int ubifs_load(char *filename, u32 addr, u32 size);
+
+int ubifs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
+int ubifs_ls(const char *dir_name);
+int ubifs_exists(const char *filename);
+int ubifs_size(const char *filename, loff_t *size);
+int ubifs_read(const char *filename, void *buf, loff_t offset,
+	       loff_t size, loff_t *actread);
+void ubifs_close(void);
+
+#endif /* __UBIFS_UBOOT_H__ */
diff --git a/include/ubispl.h b/include/ubispl.h
new file mode 100644
index 0000000..ecfe0c9
--- /dev/null
+++ b/include/ubispl.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL 2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (c) Thomas Gleixner <tglx@linutronix.de>
+ */
+#ifndef __UBOOT_UBISPL_H
+#define __UBOOT_UBISPL_H
+
+#define UBI_VOL_NAME_MAX	127
+
+/*
+ * The following CONFIG options are relevant for UBISPL
+ *
+ * #define CONFIG_SPL_UBI_MAX_VOL_LEBS		256
+ *
+ * Defines the maximum number of logical erase blocks per loadable
+ * (static) volume to size the ubispl internal arrays.
+ *
+ * #define CONFIG_SPL_UBI_MAX_PEB_SIZE		(256*1024)
+ *
+ * Defines the maximum physical erase block size to size the fastmap
+ * buffer for ubispl.
+ *
+ * #define CONFIG_SPL_UBI_MAX_PEBS		4096
+ *
+ * Define the maximum number of physical erase blocks to size the
+ * ubispl internal arrays.
+ *
+ * #define CONFIG_SPL_UBI_VOL_IDS		8
+ *
+ * Defines the maximum number of volumes in which UBISPL is
+ * interested. Limits the amount of memory for the scan data and
+ * speeds up the scan process as we simply ignore stuff which we dont
+ * want to load from the SPL anyway. So the volumes which can be
+ * loaded in the above example are ids 0 - 7
+ */
+
+/*
+ * The struct definition is in drivers/mtd/ubispl/ubispl.h. It does
+ * not fit into the BSS due to the large buffer requirement of the
+ * upstream fastmap code. So the caller of ubispl_load_volumes needs
+ * to hand in a pointer to a free memory area where ubispl will place
+ * its data. The area is not required to be initialized.
+ */
+struct ubi_scan_info;
+
+typedef int (*ubispl_read_flash)(int pnum, int offset, int len, void *dst);
+
+/**
+ * struct ubispl_info - description structure for fast ubi scan
+ * @ubi:		Pointer to memory space for ubi scan info structure
+ * @peb_size:		Physical erase block size
+ * @vid_offset:		Offset of the VID header
+ * @leb_start:		Start of the logical erase block, i.e. offset of data
+ * @peb_count:		Number of physical erase blocks in the UBI FLASH area
+ *			aka MTD partition.
+ * @peb_offset:		Offset of PEB0 in the UBI FLASH area (aka MTD partition)
+ *			to the real start of the FLASH in erase blocks.
+ * @fastmap:		Enable fastmap attachment
+ * @read:		Read function to access the flash
+ */
+struct ubispl_info {
+	struct ubi_scan_info	*ubi;
+	u32			peb_size;
+	u32			vid_offset;
+	u32			leb_start;
+	u32			peb_count;
+	u32			peb_offset;
+	int			fastmap;
+	ubispl_read_flash	read;
+};
+
+/**
+ * struct ubispl_load - structure to describe a volume to load
+ * @vol_id:	Volume id
+ * @load_addr:	Load address of the volume
+ */
+struct ubispl_load {
+	int		vol_id;
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+	u32		name_len;
+	char		name[UBI_VOL_NAME_MAX + 1];
+#endif
+	void		*load_addr;
+};
+
+/**
+ * ubispl_load_volumes - Scan flash and load volumes
+ * @info:	Pointer to the ubi scan info structure
+ * @lovls:	Pointer to array of volumes to load
+ * @nrvols:	Array size of @lovls
+ */
+int ubispl_load_volumes(struct ubispl_info *info,
+			struct ubispl_load *lvols, int nrvols);
+
+#endif
diff --git a/include/uboot_aes.h b/include/uboot_aes.h
new file mode 100644
index 0000000..2fda384
--- /dev/null
+++ b/include/uboot_aes.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
+ */
+
+#ifndef _AES_REF_H_
+#define _AES_REF_H_
+
+#ifdef USE_HOSTCC
+/* Define compat stuff for use in fw_* tools. */
+typedef unsigned char u8;
+typedef unsigned int u32;
+#define debug(...) do {} while (0)
+#endif
+
+/*
+ * AES encryption library, with small code size, supporting only 128-bit AES
+ *
+ * AES is a stream cipher which works a block at a time, with each block
+ * in this case being AES_KEY_LENGTH bytes.
+ */
+
+enum {
+	AES_STATECOLS	= 4,	/* columns in the state & expanded key */
+	AES_KEYCOLS	= 4,	/* columns in a key */
+	AES_ROUNDS	= 10,	/* rounds in encryption */
+
+	AES_KEY_LENGTH	= 128 / 8,
+	AES_EXPAND_KEY_LENGTH	= 4 * AES_STATECOLS * (AES_ROUNDS + 1),
+};
+
+/**
+ * aes_expand_key() - Expand the AES key
+ *
+ * Expand a key into a key schedule, which is then used for the other
+ * operations.
+ *
+ * @key		Key, of length AES_KEY_LENGTH bytes
+ * @expkey	Buffer to place expanded key, AES_EXPAND_KEY_LENGTH
+ */
+void aes_expand_key(u8 *key, u8 *expkey);
+
+/**
+ * aes_encrypt() - Encrypt single block of data with AES 128
+ *
+ * @in		Input data
+ * @expkey	Expanded key to use for encryption (from aes_expand_key())
+ * @out		Output data
+ */
+void aes_encrypt(u8 *in, u8 *expkey, u8 *out);
+
+/**
+ * aes_decrypt() - Decrypt single block of data with AES 128
+ *
+ * @in		Input data
+ * @expkey	Expanded key to use for decryption (from aes_expand_key())
+ * @out		Output data
+ */
+void aes_decrypt(u8 *in, u8 *expkey, u8 *out);
+
+/**
+ * Apply chain data to the destination using EOR
+ *
+ * Each array is of length AES_KEY_LENGTH.
+ *
+ * @cbc_chain_data	Chain data
+ * @src			Source data
+ * @dst			Destination data, which is modified here
+ */
+void aes_apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst);
+
+/**
+ * aes_cbc_encrypt_blocks() - Encrypt multiple blocks of data with AES CBC.
+ *
+ * @key_exp		Expanded key to use
+ * @iv			Initialization vector
+ * @src			Source data to encrypt
+ * @dst			Destination buffer
+ * @num_aes_blocks	Number of AES blocks to encrypt
+ */
+void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+			    u32 num_aes_blocks);
+
+/**
+ * Decrypt multiple blocks of data with AES CBC.
+ *
+ * @key_exp		Expanded key to use
+ * @iv			Initialization vector
+ * @src			Source data to decrypt
+ * @dst			Destination buffer
+ * @num_aes_blocks	Number of AES blocks to decrypt
+ */
+void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *iv, u8 *src, u8 *dst,
+			    u32 num_aes_blocks);
+
+#endif /* _AES_REF_H_ */
diff --git a/include/ufs.h b/include/ufs.h
new file mode 100644
index 0000000..0592a76
--- /dev/null
+++ b/include/ufs.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _UFS_H
+#define _UFS_H
+/**
+ * ufs_probe() - initialize all devices in the UFS uclass
+ *
+ * @return 0 if Ok, -ve on error
+ */
+int ufs_probe(void);
+
+/**
+ * ufs_probe_dev() - initialize a particular device in the UFS uclass
+ *
+ * @index: index in the uclass sequence
+ *
+ * @return 0 if successfully probed, -ve on error
+ */
+int ufs_probe_dev(int index);
+
+/*
+ * ufs_scsi_bind() - Create a new scsi device as a child of the UFS device and
+ *		     bind it to the ufs_scsi driver
+ * @ufs_dev: UFS device
+ * @scsi_devp: Pointer to scsi device
+ *
+ * @return 0 if Ok, -ve on error
+ */
+int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp);
+#endif
diff --git a/include/universe.h b/include/universe.h
new file mode 100644
index 0000000..c84bb58
--- /dev/null
+++ b/include/universe.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
+ */
+
+#ifndef _universe_h
+#define _universe_h
+
+typedef struct _UNIVERSE UNIVERSE;
+typedef struct _SLAVE_IMAGE SLAVE_IMAGE;
+typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
+
+struct _SLAVE_IMAGE {
+	unsigned int ctl;      /* Control     */
+	unsigned int bs;       /* Base        */
+	unsigned int bd;       /* Bound       */
+	unsigned int to;       /* Translation */
+	unsigned int reserved;
+};
+
+struct _UNIVERSE {
+	unsigned int pci_id;
+	unsigned int pci_csr;
+	unsigned int pci_class;
+	unsigned int pci_misc0;
+	unsigned int pci_bs;
+	unsigned int spare0[10];
+	unsigned int pci_misc1;
+	unsigned int spare1[48];
+	SLAVE_IMAGE  lsi[4];
+	unsigned int spare2[8];
+	unsigned int scyc_ctl;
+	unsigned int scyc_addr;
+	unsigned int scyc_en;
+	unsigned int scyc_cmp;
+	unsigned int scyc_swp;
+	unsigned int lmisc;
+	unsigned int slsi;
+	unsigned int l_cmderr;
+	unsigned int laerr;
+	unsigned int spare3[27];
+	unsigned int dctl;
+	unsigned int dtbc;
+	unsigned int dla;
+	unsigned int spare4[1];
+	unsigned int dva;
+	unsigned int spare5[1];
+	unsigned int dcpp;
+	unsigned int spare6[1];
+	unsigned int dgcs;
+	unsigned int d_llue;
+	unsigned int spare7[54];
+	unsigned int lint_en;
+	unsigned int lint_stat;
+	unsigned int lint_map0;
+	unsigned int lint_map1;
+	unsigned int vint_en;
+	unsigned int vint_stat;
+	unsigned int vint_map0;
+	unsigned int vint_map1;
+	unsigned int statid;
+	unsigned int vx_statid[7];
+	unsigned int spare8[48];
+	unsigned int mast_ctl;
+	unsigned int misc_ctl;
+	unsigned int misc_stat;
+	unsigned int user_am;
+	unsigned int spare9[700];
+	SLAVE_IMAGE  vsi[4];
+	unsigned int spare10[8];
+	unsigned int vrai_ctl;
+	unsigned int vrai_bs;
+	unsigned int spare11[2];
+	unsigned int vcsr_ctl;
+	unsigned int vcsr_to;
+	unsigned int v_amerr;
+	unsigned int vaerr;
+	unsigned int spare12[25];
+	unsigned int vcsr_clr;
+	unsigned int vcsr_set;
+	unsigned int vcsr_bs;
+};
+
+#define IRQ_VOWN    0x0001
+#define IRQ_VIRQ1   0x0002
+#define IRQ_VIRQ2   0x0004
+#define IRQ_VIRQ3   0x0008
+#define IRQ_VIRQ4   0x0010
+#define IRQ_VIRQ5   0x0020
+#define IRQ_VIRQ6   0x0040
+#define IRQ_VIRQ7   0x0080
+#define IRQ_DMA     0x0100
+#define IRQ_LERR    0x0200
+#define IRQ_VERR    0x0400
+#define IRQ_res     0x0800
+#define IRQ_IACK    0x1000
+#define IRQ_SWINT   0x2000
+#define IRQ_SYSFAIL 0x4000
+#define IRQ_ACFAIL  0x8000
+
+struct _TDMA_CMD_PACKET {
+	unsigned int dctl;   /* DMA Control         */
+	unsigned int dtbc;   /* Transfer Byte Count */
+	unsigned int dlv;    /* PCI Address         */
+	unsigned int res1;   /* Reserved            */
+	unsigned int dva;    /* Vme Address         */
+	unsigned int res2;   /* Reserved            */
+	unsigned int dcpp;   /* Pointer to Numed Cmd Packet with rPN */
+	unsigned int res3;   /* Reserved                             */
+};
+
+#define VME_AM_A16		0x01
+#define VME_AM_A24		0x02
+#define VME_AM_A32		0x03
+#define VME_AM_Axx		0x03
+#define VME_AM_SUP		0x04
+#define VME_AM_DATA		0x10
+#define VME_AM_PROG		0x20
+#define VME_AM_Mxx		0x30
+
+#define VME_FLAG_D8             0x01
+#define VME_FLAG_D16            0x02
+#define VME_FLAG_D32            0x03
+#define VME_FLAG_Dxx		0x03
+
+#define PCI_MS_MEM		0x01
+#define PCI_MS_IO		0x02
+#define PCI_MS_CONFIG		0x03
+#define PCI_MS_Mxx		0x03
+
+#endif
diff --git a/include/uuid.h b/include/uuid.h
new file mode 100644
index 0000000..abcc325
--- /dev/null
+++ b/include/uuid.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ */
+#ifndef __UUID_H__
+#define __UUID_H__
+
+#include <linux/bitops.h>
+
+/* This is structure is in big-endian */
+struct uuid {
+	unsigned int time_low;
+	unsigned short time_mid;
+	unsigned short time_hi_and_version;
+	unsigned char clock_seq_hi_and_reserved;
+	unsigned char clock_seq_low;
+	unsigned char node[6];
+} __packed;
+
+/* Bits of a bitmask specifying the output format for GUIDs */
+#define UUID_STR_FORMAT_STD	0
+#define UUID_STR_FORMAT_GUID	BIT(0)
+#define UUID_STR_UPPER_CASE	BIT(1)
+
+#define UUID_STR_LEN		36
+#define UUID_BIN_LEN		sizeof(struct uuid)
+
+#define UUID_VERSION_MASK	0xf000
+#define UUID_VERSION_SHIFT	12
+#define UUID_VERSION		0x4
+
+#define UUID_VARIANT_MASK	0xc0
+#define UUID_VARIANT_SHIFT	7
+#define UUID_VARIANT		0x1
+
+int uuid_str_valid(const char *uuid);
+int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format);
+void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format);
+#ifdef CONFIG_PARTITION_TYPE_GUID
+int uuid_guid_get_bin(const char *guid_str, unsigned char *guid_bin);
+int uuid_guid_get_str(unsigned char *guid_bin, char *guid_str);
+#endif
+void gen_rand_uuid(unsigned char *uuid_bin);
+void gen_rand_uuid_str(char *uuid_str, int str_format);
+#endif
diff --git a/include/vbe.h b/include/vbe.h
new file mode 100644
index 0000000..f420f49
--- /dev/null
+++ b/include/vbe.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * Copyright (c) 2009 Pattrick Hueper <phueper@hueper.net>
+ * All rights reserved.
+ *
+ * Contributors:
+ *     IBM Corporation - initial implementation
+ *****************************************************************************/
+#ifndef _VBE_H
+#define _VBE_H
+
+/* these structs are for input from and output to OF */
+struct __packed vbe_screen_info {
+	u8 display_type;	/* 0=NONE, 1= analog, 2=digital */
+	u16 screen_width;
+	u16 screen_height;
+	/* bytes per line in framebuffer, may be more than screen_width */
+	u16 screen_linebytes;
+	u8 color_depth;	/* color depth in bits per pixel */
+	u32 framebuffer_address;
+	u8 edid_block_zero[128];
+};
+
+struct __packed vbe_screen_info_input {
+	u8 signature[4];
+	u16 size_reserved;
+	u8 monitor_number;
+	u16 max_screen_width;
+	u8 color_depth;
+};
+
+/* these structs only store the required a subset of the VBE-defined fields */
+struct __packed vbe_info {
+	char signature[4];
+	u16 version;
+	u32 oem_string_ptr;
+	u32 capabilities;
+	u32 modes_ptr;
+	u16 total_memory;
+	u16 oem_version;
+	u32 vendor_name_ptr;
+	u32 product_name_ptr;
+	u32 product_rev_ptr;
+};
+
+struct __packed vesa_mode_info {
+	u16 mode_attributes;	/* 00 */
+	u8 win_a_attributes;	/* 02 */
+	u8 win_b_attributes;	/* 03 */
+	u16 win_granularity;	/* 04 */
+	u16 win_size;		/* 06 */
+	u16 win_a_segment;	/* 08 */
+	u16 win_b_segment;	/* 0a */
+	u32 win_func_ptr;	/* 0c */
+	u16 bytes_per_scanline;	/* 10 */
+	u16 x_resolution;	/* 12 */
+	u16 y_resolution;	/* 14 */
+	u8 x_charsize;		/* 16 */
+	u8 y_charsize;		/* 17 */
+	u8 number_of_planes;	/* 18 */
+	u8 bits_per_pixel;	/* 19 */
+	u8 number_of_banks;	/* 20 */
+	u8 memory_model;	/* 21 */
+	u8 bank_size;		/* 22 */
+	u8 number_of_image_pages; /* 23 */
+	u8 reserved_page;
+	u8 red_mask_size;
+	u8 red_mask_pos;
+	u8 green_mask_size;
+	u8 green_mask_pos;
+	u8 blue_mask_size;
+	u8 blue_mask_pos;
+	u8 reserved_mask_size;
+	u8 reserved_mask_pos;
+	u8 direct_color_mode_info;
+	u32 phys_base_ptr;
+	u32 offscreen_mem_offset;
+	u16 offscreen_mem_size;
+	u8 reserved[206];
+};
+
+struct vbe_mode_info {
+	u16 video_mode;
+	bool valid;
+	union {
+		struct vesa_mode_info vesa;
+		u8 mode_info_block[256];
+	};
+};
+
+struct vbe_ddc_info {
+	u8 port_number;	/* i.e. monitor number */
+	u8 edid_transfer_time;
+	u8 ddc_level;
+	u8 edid_block_zero[128];
+};
+
+#define VESA_GET_INFO		0x4f00
+#define VESA_GET_MODE_INFO	0x4f01
+#define VESA_SET_MODE		0x4f02
+#define VESA_GET_CUR_MODE	0x4f03
+
+extern struct vbe_mode_info mode_info;
+
+struct video_priv;
+struct video_uc_platdata;
+int vbe_setup_video_priv(struct vesa_mode_info *vesa,
+			 struct video_priv *uc_priv,
+			 struct video_uc_platdata *plat);
+int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void));
+
+#endif
diff --git a/include/versalpl.h b/include/versalpl.h
new file mode 100644
index 0000000..b94c82e
--- /dev/null
+++ b/include/versalpl.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * (C) Copyright 2019 Xilinx, Inc,
+ * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ */
+
+#ifndef _VERSALPL_H_
+#define _VERSALPL_H_
+
+#include <xilinx.h>
+
+#define VERSAL_PM_LOAD_PDI	0x701
+#define VERSAL_PM_PDI_TYPE	0xF
+
+extern struct xilinx_fpga_op versal_op;
+
+#define XILINX_VERSAL_DESC \
+{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op }
+
+#endif /* _VERSALPL_H_ */
diff --git a/include/version.h b/include/version.h
new file mode 100644
index 0000000..2d24451
--- /dev/null
+++ b/include/version.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef	__VERSION_H__
+#define	__VERSION_H__
+
+#include <timestamp.h>
+
+#ifndef DO_DEPS_ONLY
+#include "generated/version_autogenerated.h"
+#endif
+
+#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
+	U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING
+
+#ifndef __ASSEMBLY__
+extern const char version_string[];
+#endif	/* __ASSEMBLY__ */
+#endif	/* __VERSION_H__ */
diff --git a/include/video.h b/include/video.h
new file mode 100644
index 0000000..485071d
--- /dev/null
+++ b/include/video.h
@@ -0,0 +1,279 @@
+/*
+ * Video uclass and legacy implementation
+ *
+ * Copyright (c) 2015 Google, Inc
+ *
+ * MPC823 Video Controller
+ * =======================
+ * (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
+ * AIRVENT SAM s.p.a - RIMINI(ITALY)
+ *
+ */
+
+#ifndef _VIDEO_H_
+#define _VIDEO_H_
+
+#ifdef CONFIG_DM_VIDEO
+
+#include <stdio_dev.h>
+
+struct video_uc_platdata {
+	uint align;
+	uint size;
+	ulong base;
+};
+
+enum video_polarity {
+	VIDEO_ACTIVE_HIGH,	/* Pins are active high */
+	VIDEO_ACTIVE_LOW,	/* Pins are active low */
+};
+
+/*
+ * Bits per pixel selector. Each value n is such that the bits-per-pixel is
+ * 2 ^ n
+ */
+enum video_log2_bpp {
+	VIDEO_BPP1	= 0,
+	VIDEO_BPP2,
+	VIDEO_BPP4,
+	VIDEO_BPP8,
+	VIDEO_BPP16,
+	VIDEO_BPP32,
+};
+
+/*
+ * Convert enum video_log2_bpp to bytes and bits. Note we omit the outer
+ * brackets to allow multiplication by fractional pixels.
+ */
+#define VNBYTES(bpix)	(1 << (bpix)) / 8
+
+#define VNBITS(bpix)	(1 << (bpix))
+
+/**
+ * struct video_priv - Device information used by the video uclass
+ *
+ * @xsize:	Number of pixel columns (e.g. 1366)
+ * @ysize:	Number of pixels rows (e.g.. 768)
+ * @rot:	Display rotation (0=none, 1=90 degrees clockwise, etc.)
+ * @bpix:	Encoded bits per pixel (enum video_log2_bpp)
+ * @vidconsole_drv_name:	Driver to use for the text console, NULL to
+ *		select automatically
+ * @font_size:	Font size in pixels (0 to use a default value)
+ * @fb:		Frame buffer
+ * @fb_size:	Frame buffer size
+ * @line_length:	Length of each frame buffer line, in bytes. This can be
+ *		set by the driver, but if not, the uclass will set it after
+ *		probing
+ * @colour_fg:	Foreground colour (pixel value)
+ * @colour_bg:	Background colour (pixel value)
+ * @flush_dcache:	true to enable flushing of the data cache after
+ *		the LCD is updated
+ * @cmap:	Colour map for 8-bit-per-pixel displays
+ * @fg_col_idx:	Foreground color code (bit 3 = bold, bit 0-2 = color)
+ * @bg_col_idx:	Background color code (bit 3 = bold, bit 0-2 = color)
+ */
+struct video_priv {
+	/* Things set up by the driver: */
+	ushort xsize;
+	ushort ysize;
+	ushort rot;
+	enum video_log2_bpp bpix;
+	const char *vidconsole_drv_name;
+	int font_size;
+
+	/*
+	 * Things that are private to the uclass: don't use these in the
+	 * driver
+	 */
+	void *fb;
+	int fb_size;
+	int line_length;
+	u32 colour_fg;
+	u32 colour_bg;
+	bool flush_dcache;
+	ushort *cmap;
+	u8 fg_col_idx;
+	u8 bg_col_idx;
+};
+
+/* Placeholder - there are no video operations at present */
+struct video_ops {
+};
+
+#define video_get_ops(dev)        ((struct video_ops *)(dev)->driver->ops)
+
+/**
+ * video_reserve() - Reserve frame-buffer memory for video devices
+ *
+ * Note: This function is for internal use.
+ *
+ * This uses the uclass platdata's @size and @align members to figure out
+ * a size and position for each frame buffer as part of the pre-relocation
+ * process of determining the post-relocation memory layout.
+ *
+ * gd->video_top is set to the initial value of *@addrp and gd->video_bottom
+ * is set to the final value.
+ *
+ * @addrp:	On entry, the top of available memory. On exit, the new top,
+ *		after allocating the required memory.
+ * @return 0
+ */
+int video_reserve(ulong *addrp);
+
+/**
+ * video_clear() - Clear a device's frame buffer to background color.
+ *
+ * @dev:	Device to clear
+ * @return 0
+ */
+int video_clear(struct udevice *dev);
+
+/**
+ * video_sync() - Sync a device's frame buffer with its hardware
+ *
+ * Some frame buffers are cached or have a secondary frame buffer. This
+ * function syncs these up so that the current contents of the U-Boot frame
+ * buffer are displayed to the user.
+ *
+ * @dev:	Device to sync
+ * @force:	True to force a sync even if there was one recently (this is
+ *		very expensive on sandbox)
+ */
+void video_sync(struct udevice *vid, bool force);
+
+/**
+ * video_sync_all() - Sync all devices' frame buffers with there hardware
+ *
+ * This calls video_sync() on all active video devices.
+ */
+void video_sync_all(void);
+
+/**
+ * video_bmp_display() - Display a BMP file
+ *
+ * @dev:	Device to display the bitmap on
+ * @bmp_image:	Address of bitmap image to display
+ * @x:		X position in pixels from the left
+ * @y:		Y position in pixels from the top
+ * @align:	true to adjust the coordinates to centre the image. If false
+ *		the coordinates are used as is. If true:
+ *
+ *		- if a coordinate is 0x7fff then the image will be centred in
+ *		  that direction
+ *		- if a coordinate is -ve then it will be offset to the
+ *		  left/top of the centre by that many pixels
+ *		- if a coordinate is positive it will be used unchnaged.
+ * @return 0 if OK, -ve on error
+ */
+int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
+		      bool align);
+
+/**
+ * video_get_xsize() - Get the width of the display in pixels
+ *
+ * @dev:	Device to check
+ * @return device frame buffer width in pixels
+ */
+int video_get_xsize(struct udevice *dev);
+
+/**
+ * video_get_ysize() - Get the height of the display in pixels
+ *
+ * @dev:	Device to check
+ * @return device frame buffer height in pixels
+ */
+int video_get_ysize(struct udevice *dev);
+
+/**
+ * Set whether we need to flush the dcache when changing the image. This
+ * defaults to off.
+ *
+ * @param flush		non-zero to flush cache after update, 0 to skip
+ */
+void video_set_flush_dcache(struct udevice *dev, bool flush);
+
+/**
+ * Set default colors and attributes
+ *
+ * @dev:	video device
+ * @invert	true to invert colours
+ */
+void video_set_default_colors(struct udevice *dev, bool invert);
+
+#endif /* CONFIG_DM_VIDEO */
+
+#ifndef CONFIG_DM_VIDEO
+
+/* Video functions */
+
+/**
+ * Display a BMP format bitmap on the screen
+ *
+ * @param bmp_image	Address of BMP image
+ * @param x		X position to draw image
+ * @param y		Y position to draw image
+ */
+int video_display_bitmap(ulong bmp_image, int x, int y);
+
+/**
+ * Get the width of the screen in pixels
+ *
+ * @return width of screen in pixels
+ */
+int video_get_pixel_width(void);
+
+/**
+ * Get the height of the screen in pixels
+ *
+ * @return height of screen in pixels
+ */
+int video_get_pixel_height(void);
+
+/**
+ * Get the number of text lines/rows on the screen
+ *
+ * @return number of rows
+ */
+int video_get_screen_rows(void);
+
+/**
+ * Get the number of text columns on the screen
+ *
+ * @return number of columns
+ */
+int video_get_screen_columns(void);
+
+/**
+ * Set the position of the text cursor
+ *
+ * @param col	Column to place cursor (0 = left side)
+ * @param row	Row to place cursor (0 = top line)
+ */
+void video_position_cursor(unsigned col, unsigned row);
+
+/* Clear the display */
+void video_clear(void);
+
+#if defined(CONFIG_FORMIKE)
+int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs,
+	unsigned int max_hz, unsigned int spi_mode);
+#endif
+#if defined(CONFIG_LG4573)
+int lg4573_spi_startup(unsigned int bus, unsigned int cs,
+	unsigned int max_hz, unsigned int spi_mode);
+#endif
+
+/*
+ * video_get_info_str() - obtain a board string: type, speed, etc.
+ *
+ * This is called if CONFIG_CONSOLE_EXTRA_INFO is enabled.
+ *
+ * line_number:	location to place info string beside logo
+ * info:	buffer for info string (empty if nothing to display on this
+ * line)
+ */
+void video_get_info_str(int line_number, char *info);
+
+#endif /* !CONFIG_DM_VIDEO */
+
+#endif
diff --git a/include/video_bridge.h b/include/video_bridge.h
new file mode 100644
index 0000000..22e93db
--- /dev/null
+++ b/include/video_bridge.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __VIDEO_BRIDGE
+#define __VIDEO_BRIDGE
+
+#include <asm/gpio.h>
+
+/**
+ * struct video_bridge_priv - uclass information for video bridges
+ *
+ * @sleep:	GPIO to assert to power down the bridge
+ * @reset:	GPIO to assert to reset the bridge
+ * @hotplug:	Optional GPIO to check if bridge is connected
+ */
+struct video_bridge_priv {
+	struct gpio_desc sleep;
+	struct gpio_desc reset;
+	struct gpio_desc hotplug;
+};
+
+/**
+ * Operations for video bridges
+ */
+struct video_bridge_ops {
+	/**
+	 * attach() - attach a video bridge
+	 *
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*attach)(struct udevice *dev);
+
+	/**
+	 * check_attached() - check if a bridge is correctly attached
+	 *
+	 * This method is optional - if not provided then the hotplug GPIO
+	 * will be checked instead.
+	 *
+	 * @dev:	Device to check
+	 * @return 0 if attached, -EENOTCONN if not, or other -ve error
+	 */
+	int (*check_attached)(struct udevice *dev);
+
+	/**
+	 * set_backlight() - Set the backlight brightness
+	 *
+	 * @dev:	device to adjust
+	 * @percent:	brightness percentage (0=off, 100=full brightness)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_backlight)(struct udevice *dev, int percent);
+
+	/**
+	 * read_edid() - Read information from EDID
+	 *
+	 * @dev:	Device to read from
+	 * @buf:	Buffer to read into
+	 * @buf_size:	Buffer size
+	 * @return number of bytes read, <=0 for error
+	 */
+	int (*read_edid)(struct udevice *dev, u8 *buf, int buf_size);
+};
+
+#define video_bridge_get_ops(dev) \
+		((struct video_bridge_ops *)(dev)->driver->ops)
+
+/**
+ * video_bridge_attach() - attach a video bridge
+ *
+ * @return 0 if OK, -ve on error
+ */
+int video_bridge_attach(struct udevice *dev);
+
+/**
+ * video_bridge_set_backlight() - Set the backlight brightness
+ *
+ * @percent:	brightness percentage (0=off, 100=full brightness)
+ * @return 0 if OK, -ve on error
+ */
+int video_bridge_set_backlight(struct udevice *dev, int percent);
+
+/**
+ * video_bridge_set_active() - take the bridge in/out of reset/powerdown
+ *
+ * @dev:	Device to adjust
+ * @active:	true to power up and reset, false to power down
+ */
+int video_bridge_set_active(struct udevice *dev, bool active);
+
+/**
+ * check_attached() - check if a bridge is correctly attached
+ *
+ * @dev:	Device to check
+ * @return 0 if attached, -EENOTCONN if not, or other -ve error
+ */
+int video_bridge_check_attached(struct udevice *dev);
+
+/**
+ * video_bridge_read_edid() - Read information from EDID
+ *
+ * @dev:	Device to read from
+ * @buf:	Buffer to read into
+ * @buf_size:	Buffer size
+ * @return number of bytes read, <=0 for error
+ */
+int video_bridge_read_edid(struct udevice *dev, u8 *buf, int buf_size);
+
+#endif
diff --git a/include/video_console.h b/include/video_console.h
new file mode 100644
index 0000000..0936cea
--- /dev/null
+++ b/include/video_console.h
@@ -0,0 +1,261 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2015 Google, Inc
+ */
+
+#ifndef __video_console_h
+#define __video_console_h
+
+#include <video.h>
+
+#define VID_FRAC_DIV	256
+
+#define VID_TO_PIXEL(x)	((x) / VID_FRAC_DIV)
+#define VID_TO_POS(x)	((x) * VID_FRAC_DIV)
+
+/*
+ * The 16 colors supported by the console
+ */
+enum color_idx {
+	VID_BLACK = 0,
+	VID_RED,
+	VID_GREEN,
+	VID_BROWN,
+	VID_BLUE,
+	VID_MAGENTA,
+	VID_CYAN,
+	VID_LIGHT_GRAY,
+	VID_GRAY,
+	VID_LIGHT_RED,
+	VID_LIGTH_GREEN,
+	VID_YELLOW,
+	VID_LIGHT_BLUE,
+	VID_LIGHT_MAGENTA,
+	VID_LIGHT_CYAN,
+	VID_WHITE,
+
+	VID_COLOR_COUNT
+};
+
+/**
+ * struct vidconsole_priv - uclass-private data about a console device
+ *
+ * Drivers must set up @rows, @cols, @x_charsize, @y_charsize in their probe()
+ * method. Drivers may set up @xstart_frac if desired.
+ *
+ * @sdev:		stdio device, acting as an output sink
+ * @xcur_frac:		Current X position, in fractional units (VID_TO_POS(x))
+ * @ycur:		Current Y position in pixels (0=top)
+ * @rows:		Number of text rows
+ * @cols:		Number of text columns
+ * @x_charsize:		Character width in pixels
+ * @y_charsize:		Character height in pixels
+ * @tab_width_frac:	Tab width in fractional units
+ * @xsize_frac:		Width of the display in fractional units
+ * @xstart_frac:	Left margin for the text console in fractional units
+ * @last_ch:		Last character written to the text console on this line
+ * @escape:		TRUE if currently accumulating an ANSI escape sequence
+ * @escape_len:		Length of accumulated escape sequence so far
+ * @col_saved:		Saved X position, in fractional units (VID_TO_POS(x))
+ * @row_saved:		Saved Y position in pixels (0=top)
+ * @escape_buf:		Buffer to accumulate escape sequence
+ */
+struct vidconsole_priv {
+	struct stdio_dev sdev;
+	int xcur_frac;
+	int ycur;
+	int rows;
+	int cols;
+	int x_charsize;
+	int y_charsize;
+	int tab_width_frac;
+	int xsize_frac;
+	int xstart_frac;
+	int last_ch;
+	/*
+	 * ANSI escape sequences are accumulated character by character,
+	 * starting after the ESC char (0x1b) until the entire sequence
+	 * is consumed at which point it is acted upon.
+	 */
+	int escape;
+	int escape_len;
+	int row_saved;
+	int col_saved;
+	char escape_buf[32];
+};
+
+/**
+ * struct vidconsole_ops - Video console operations
+ *
+ * These operations work on either an absolute console position (measured
+ * in pixels) or a text row number (measured in rows, where each row consists
+ * of an entire line of text - typically 16 pixels).
+ */
+struct vidconsole_ops {
+	/**
+	 * putc_xy() - write a single character to a position
+	 *
+	 * @dev:	Device to write to
+	 * @x_frac:	Fractional pixel X position (0=left-most pixel) which
+	 *		is the X position multipled by VID_FRAC_DIV.
+	 * @y:		Pixel Y position (0=top-most pixel)
+	 * @ch:		Character to write
+	 * @return number of fractional pixels that the cursor should move,
+	 * if all is OK, -EAGAIN if we ran out of space on this line, other -ve
+	 * on error
+	 */
+	int (*putc_xy)(struct udevice *dev, uint x_frac, uint y, char ch);
+
+	/**
+	 * move_rows() - Move text rows from one place to another
+	 *
+	 * @dev:	Device to adjust
+	 * @rowdst:	Destination text row (0=top)
+	 * @rowsrc:	Source start text row
+	 * @count:	Number of text rows to move
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*move_rows)(struct udevice *dev, uint rowdst, uint rowsrc,
+			  uint count);
+
+	/**
+	 * set_row() - Set the colour of a text row
+	 *
+	 * Every pixel contained within the text row is adjusted
+	 *
+	 * @dev:	Device to adjust
+	 * @row:	Text row to adjust (0=top)
+	 * @clr:	Raw colour (pixel value) to write to each pixel
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_row)(struct udevice *dev, uint row, int clr);
+
+	/**
+	 * entry_start() - Indicate that text entry is starting afresh
+	 *
+	 * Consoles which use proportional fonts need to track the position of
+	 * each character output so that backspace will return to the correct
+	 * place. This method signals to the console driver that a new entry
+	 * line is being start (e.g. the user pressed return to start a new
+	 * command). The driver can use this signal to empty its list of
+	 * positions.
+	 */
+	int (*entry_start)(struct udevice *dev);
+
+	/**
+	 * backspace() - Handle erasing the last character
+	 *
+	 * With proportional fonts the vidconsole uclass cannot itself erase
+	 * the previous character. This optional method will be called when
+	 * a backspace is needed. The driver should erase the previous
+	 * character and update the cursor position (xcur_frac, ycur) to the
+	 * start of the previous character.
+	 *
+	 * If not implement, default behaviour will work for fixed-width
+	 * characters.
+	 */
+	int (*backspace)(struct udevice *dev);
+};
+
+/* Get a pointer to the driver operations for a video console device */
+#define vidconsole_get_ops(dev)  ((struct vidconsole_ops *)(dev)->driver->ops)
+
+/**
+ * vidconsole_putc_xy() - write a single character to a position
+ *
+ * @dev:	Device to write to
+ * @x_frac:	Fractional pixel X position (0=left-most pixel) which
+ *		is the X position multipled by VID_FRAC_DIV.
+ * @y:		Pixel Y position (0=top-most pixel)
+ * @ch:		Character to write
+ * @return number of fractional pixels that the cursor should move,
+ * if all is OK, -EAGAIN if we ran out of space on this line, other -ve
+ * on error
+ */
+int vidconsole_putc_xy(struct udevice *dev, uint x, uint y, char ch);
+
+/**
+ * vidconsole_move_rows() - Move text rows from one place to another
+ *
+ * @dev:	Device to adjust
+ * @rowdst:	Destination text row (0=top)
+ * @rowsrc:	Source start text row
+ * @count:	Number of text rows to move
+ * @return 0 if OK, -ve on error
+ */
+int vidconsole_move_rows(struct udevice *dev, uint rowdst, uint rowsrc,
+			 uint count);
+
+/**
+ * vidconsole_set_row() - Set the colour of a text row
+ *
+ * Every pixel contained within the text row is adjusted
+ *
+ * @dev:	Device to adjust
+ * @row:	Text row to adjust (0=top)
+ * @clr:	Raw colour (pixel value) to write to each pixel
+ * @return 0 if OK, -ve on error
+ */
+int vidconsole_set_row(struct udevice *dev, uint row, int clr);
+
+/**
+ * vidconsole_put_char() - Output a character to the current console position
+ *
+ * Outputs a character to the console and advances the cursor. This function
+ * handles wrapping to new lines and scrolling the console. Special
+ * characters are handled also: \n, \r, \b and \t.
+ *
+ * The device always starts with the cursor at position 0,0 (top left). It
+ * can be adjusted manually using vidconsole_position_cursor().
+ *
+ * @dev:	Device to adjust
+ * @ch:		Character to write
+ * @return 0 if OK, -ve on error
+ */
+int vidconsole_put_char(struct udevice *dev, char ch);
+
+/**
+ * vidconsole_put_string() - Output a string to the current console position
+ *
+ * Outputs a string to the console and advances the cursor. This function
+ * handles wrapping to new lines and scrolling the console. Special
+ * characters are handled also: \n, \r, \b and \t.
+ *
+ * The device always starts with the cursor at position 0,0 (top left). It
+ * can be adjusted manually using vidconsole_position_cursor().
+ *
+ * @dev:	Device to adjust
+ * @str:	String to write
+ * @return 0 if OK, -ve on error
+ */
+int vidconsole_put_string(struct udevice *dev, const char *str);
+
+/**
+ * vidconsole_position_cursor() - Move the text cursor
+ *
+ * @dev:	Device to adjust
+ * @col:	New cursor text column
+ * @row:	New cursor text row
+ * @return 0 if OK, -ve on error
+ */
+void vidconsole_position_cursor(struct udevice *dev, unsigned col,
+				unsigned row);
+
+#ifdef CONFIG_DM_VIDEO
+
+/**
+ * vid_console_color() - convert a color code to a pixel's internal
+ * representation
+ *
+ * The caller has to guarantee that the color index is less than
+ * VID_COLOR_COUNT.
+ *
+ * @priv	private data of the console device
+ * @idx		color index
+ * @return	color value
+ */
+u32 vid_console_color(struct video_priv *priv, unsigned int idx);
+
+#endif
+
+#endif
diff --git a/include/video_easylogo.h b/include/video_easylogo.h
new file mode 100644
index 0000000..ce93868
--- /dev/null
+++ b/include/video_easylogo.h
@@ -0,0 +1,26 @@
+/*
+** video easylogo
+** ==============
+** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
+** AIRVENT SAM s.p.a - RIMINI(ITALY)
+**
+** This utility is still under construction!
+*/
+
+#ifndef _EASYLOGO_H_
+#define _EASYLOGO_H_
+
+#if 0
+#define ENABLE_ASCII_BANNERS
+#endif
+
+typedef struct {
+	unsigned char	*data;
+	int		width;
+	int		height;
+	int		bpp;
+	int		pixel_size;
+	int		size;
+} fastimage_t ;
+
+#endif	/* _EASYLOGO_H_ */
diff --git a/include/video_fb.h b/include/video_fb.h
new file mode 100644
index 0000000..e410226
--- /dev/null
+++ b/include/video_fb.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 1997-2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ */
+
+/*
+ * smiLynxEM.h
+ * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
+ *
+ *
+ *  modification history
+ *  --------------------
+ *  04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
+ */
+
+#ifndef _VIDEO_FB_H_
+#define _VIDEO_FB_H_
+
+/*
+ * Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT
+ */
+#define GDF__8BIT_INDEX         0
+#define GDF_15BIT_555RGB        1
+#define GDF_16BIT_565RGB        2
+#define GDF_32BIT_X888RGB       3
+#define GDF_24BIT_888RGB        4
+#define GDF__8BIT_332RGB        5
+
+/******************************************************************************/
+/* Export Graphic Driver Control                                              */
+/******************************************************************************/
+
+typedef struct graphic_device {
+    unsigned int isaBase;
+    unsigned int pciBase;
+    unsigned int dprBase;
+    unsigned int vprBase;
+    unsigned int cprBase;
+    unsigned int frameAdrs;
+    unsigned int memSize;
+    unsigned int mode;
+    unsigned int gdfIndex;
+    unsigned int gdfBytesPP;
+    unsigned int fg;
+    unsigned int bg;
+    unsigned int plnSizeX;
+    unsigned int plnSizeY;
+    unsigned int winSizeX;
+    unsigned int winSizeY;
+    char modeIdent[80];
+} GraphicDevice;
+
+
+/******************************************************************************/
+/* Export Graphic Functions                                                   */
+/******************************************************************************/
+
+void *video_hw_init (void);       /* returns GraphicDevice struct or NULL */
+
+#ifdef VIDEO_HW_BITBLT
+void video_hw_bitblt (
+    unsigned int bpp,             /* bytes per pixel */
+    unsigned int src_x,           /* source pos x */
+    unsigned int src_y,           /* source pos y */
+    unsigned int dst_x,           /* dest pos x */
+    unsigned int dst_y,           /* dest pos y */
+    unsigned int dim_x,           /* frame width */
+    unsigned int dim_y            /* frame height */
+    );
+#endif
+
+#ifdef VIDEO_HW_RECTFILL
+void video_hw_rectfill (
+    unsigned int bpp,             /* bytes per pixel */
+    unsigned int dst_x,           /* dest pos x */
+    unsigned int dst_y,           /* dest pos y */
+    unsigned int dim_x,           /* frame width */
+    unsigned int dim_y,           /* frame height */
+    unsigned int color            /* fill color */
+     );
+#endif
+
+void video_set_lut (
+    unsigned int index,           /* color number */
+    unsigned char r,              /* red */
+    unsigned char g,              /* green */
+    unsigned char b               /* blue */
+    );
+
+#endif /*_VIDEO_FB_H_ */
diff --git a/include/video_font.h b/include/video_font.h
new file mode 100644
index 0000000..5e23f70
--- /dev/null
+++ b/include/video_font.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ */
+
+#ifndef _VIDEO_FONT_
+#define _VIDEO_FONT_
+
+#ifdef CONFIG_VIDEO_FONT_4X6
+#include <video_font_4x6.h>
+#else
+#include <video_font_data.h>
+#endif
+
+#endif /* _VIDEO_FONT_ */
diff --git a/include/video_font_4x6.h b/include/video_font_4x6.h
new file mode 100644
index 0000000..64c5ed2
--- /dev/null
+++ b/include/video_font_4x6.h
@@ -0,0 +1,2153 @@
+/* Hand composed "Minuscule" 4x6 font for code page 437, with binary data
+ * generated using Perl stub.
+ *
+ * Use 'perl -x mini_4x6.c < mini_4x6.c > new_version.c' to regenerate
+ * binary data.
+ *
+ * Created by Kenneth Albanowski.
+ * No rights reserved, released to the public domain.
+ *
+ * Version 1.0
+ */
+
+/*
+
+#!/usr/bin/perl -pn
+
+s{((0x)?[0-9a-fA-F]+)(.*\[([\*\ ]{4})\])}{
+
+	($num,$pat,$bits) = ($1,$3,$4);
+
+	$bits =~ s/([^\s0])|(.)/ defined($1) + 0 /ge;
+
+	$num = ord(pack("B8", $bits));
+	$num |= $num >> 4;
+	$num = sprintf("0x%.2x", $num);
+
+	#print "$num,$pat,$bits\n";
+
+	$num . $pat;
+}ge;
+
+__END__;
+*/
+
+/* Note: binary data consists of one byte for each row of each character top
+   to bottom, character 0 to character 255, six bytes per character. Each
+   byte contains the same four character bits in both nybbles.
+   MSBit to LSBit = left to right.
+ */
+
+#ifndef _VIDEO_FONT_DATA_
+#define _VIDEO_FONT_DATA_
+
+#define VIDEO_FONT_CHARS	256
+#define VIDEO_FONT_WIDTH	4
+#define VIDEO_FONT_HEIGHT	6
+#define VIDEO_FONT_SIZE		(VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
+
+static unsigned char video_fontdata[VIDEO_FONT_SIZE] = {
+
+	/*{*/
+	  	/*   Char 0: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 1: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 2: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 3: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 4: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 5: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 6: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 7: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 8: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 9: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 10: '' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 11: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 12: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 13: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 14: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 15: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 16: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 17: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 18: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 19: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 20: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 21: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 22: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 23: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 24: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 25: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 26: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 27: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 28: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 29: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 30: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 31: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 32: ' ' */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 33: '!' */
+	0x44,	/*=  [ *  ]       */
+	0x44,	/*=  [ *  ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 34: '"' */
+	0xaa,	/*=  [* * ]       */
+	0xaa,	/*=  [* * ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 35: '#' */
+	0xaa,	/*=  [* * ]       */
+	0xff,	/*=  [****]       */
+	0xff,	/*=  [****]       */
+	0xaa,	/*=  [* * ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 36: '$' */
+	0x44,	/*=  [ *  ]       */
+	0x66,	/*=  [ ** ]       */
+	0xee,	/*=  [*** ]       */
+	0xcc,	/*=  [**  ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 37: '%' */
+	0xaa,	/*=  [* * ]       */
+	0x22,	/*=  [  * ]       */
+	0x44,	/*=  [ *  ]       */
+	0x88,	/*=  [*   ]       */
+	0xaa,	/*=  [* * ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 38: '&' */
+	0x66,	/*=  [ ** ]       */
+	0x99,	/*=  [*  *]       */
+	0x66,	/*=  [ ** ]       */
+	0xaa,	/*=  [* * ]       */
+	0xdd,	/*=  [** *]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 39: ''' */
+	0x22,	/*=  [  * ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 40: '(' */
+	0x22,	/*=  [  * ]       */
+	0x44,	/*=  [ *  ]       */
+	0x44,	/*=  [ *  ]       */
+	0x44,	/*=  [ *  ]       */
+	0x22,	/*=  [  * ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 41: ')' */
+	0x44,	/*=  [ *  ]       */
+	0x22,	/*=  [  * ]       */
+	0x22,	/*=  [  * ]       */
+	0x22,	/*=  [  * ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 42: '*' */
+	0x00,	/*=  [    ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 43: '+' */
+	0x00,	/*=  [    ]       */
+	0x44,	/*=  [ *  ]       */
+	0xee,	/*=  [*** ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 44: ',' */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x44,	/*=  [ *  ]       */
+	0x88,	/*=  [*   ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 45: '-' */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 46: '.' */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 47: '/' */
+	0x00,	/*=  [    ]       */
+	0x22,	/*=  [  * ]       */
+	0x44,	/*=  [ *  ]       */
+	0x88,	/*=  [*   ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 48: '0'   */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/
+	  	/*   Char 49: '1'   */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/
+	  	/*   Char 50: '2'   */
+	0xcc,	/*=   [**  ]        */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/
+	  	/*   Char 51: '3'   */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x22,	/*=   [  * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 52: '4'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 53: '5'   */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 54: '6'   */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 55: '7'   */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 56: '8'   */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 57: '9'   */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 58: ':'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 59: ';'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	/*}*/
+	/*{*/ 	/*   Char 60: '<'   */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 61: '='   */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 62: '>'   */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 63: '?'   */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 64: '@'   */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 65: 'A'   */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 66: 'B'   */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 67: 'C'   */
+	0x66,	/*=   [ ** ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 68: 'D'   */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 69: 'E'   */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 70: 'F'   */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 71: 'G'   */
+	0x66,	/*=   [ ** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 72: 'H'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 73: 'I'   */
+	0xee,	/*=   [*** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 74: 'J'   */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 75: 'K'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 76: 'L'   */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 77: 'M'   */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 78: 'N'   */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 79: 'O'   */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 80: 'P'   */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 81: 'Q'   */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 82: 'R'   */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 83: 'S'   */
+	0x66,	/*=   [ ** ]        */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x22,	/*=   [  * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 84: 'T'   */
+	0xee,	/*=   [*** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 85: 'U'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 86: 'V'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 87: 'W'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 88: 'X'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 89: 'Y'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 90: 'Z'   */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 91: '['   */
+	0x66,	/*=   [ ** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 92: '\'   */
+	0x00,	/*=   [    ]        */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 93: ']'   */
+	0x66,	/*=   [ ** ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 94: '^'   */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 95: '_'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	/*}*/
+	/*{*/ 	/*   Char 96: '`'   */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 97: 'a'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 98: 'b'   */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 99: 'c'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0x88,	/*=   [*   ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 100: 'd'   */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x66,	/*=   [ ** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 101: 'e'   */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 102: 'f'   */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 103: 'g'   */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 104: 'h'   */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 105: 'i'   */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 106: 'j'   */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 107: 'k'   */
+	0x00,	/*=   [    ]        */
+	0x88,	/*=   [*   ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 108: 'l'   */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 109: 'm'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 110: 'n'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 111: 'o'   */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 112: 'p'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x88,	/*=   [*   ]        */
+	/*}*/
+	/*{*/ 	/*   Char 113: 'q'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x22,	/*=   [  * ]        */
+	/*}*/
+	/*{*/ 	/*   Char 114: 'r'   */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 115: 's'   */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0xcc,	/*=   [**  ]        */
+	0x22,	/*=   [  * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 116: 't'   */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 117: 'u'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 118: 'v'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 119: 'w'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 120: 'x'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 121: 'y'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0xcc,	/*=   [**  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 122: 'z' */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xcc,	/*=   [**  ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 123: '{' */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 124: '|' */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 125: '}' */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x66,	/*=   [ ** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 126: '~' */
+	0x55,	/*=   [ * *]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 127: '' */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 128:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 129:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 130:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 131:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 132:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 133:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 134:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 135:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 136:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 137:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 138:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 139:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 140:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 141:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 142:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 143:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 144:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 145:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 146:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 147:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 148:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 149:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 150:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 151:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 152:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 153:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 154:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 155:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 156:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 157:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 158:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 159:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 160:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 161:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 162:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 163:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 164:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 165:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 166:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 167:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 168:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 169:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 170:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 171:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 172:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 173:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 174:  */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0xcc,	/*=   [**  ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 175:  */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0x66,	/*=   [ ** ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 176:  */
+	0x88,	/*=   [*   ]        */
+	0x22,	/*=   [  * ]        */
+	0x88,	/*=   [*   ]        */
+	0x22,	/*=   [  * ]        */
+	0x88,	/*=   [*   ]        */
+	0x22,	/*=   [  * ]        */
+	/*}*/
+	/*{*/ 	/*   Char 177:  */
+	0xaa,	/*=   [* * ]        */
+	0x55,	/*=   [ * *]        */
+	0xaa,	/*=   [* * ]        */
+	0x55,	/*=   [ * *]        */
+	0xaa,	/*=   [* * ]        */
+	0x55,	/*=   [ * *]        */
+	/*}*/
+	/*{*/ 	/*   Char 178:  */
+	0xdd,	/*=   [** *]        */
+	0xbb,	/*=   [* **]        */
+	0xdd,	/*=   [** *]        */
+	0xbb,	/*=   [* **]        */
+	0xdd,	/*=   [** *]        */
+	0xbb,	/*=   [* **]        */
+	/*}*/
+	/*{*/ 	/*   Char 179:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 180:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 181:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 182:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 183:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 184:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 185:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 186:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 187:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 188:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 189:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 190:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 191:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 192:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x77,	/*=   [ ***]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 193:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 194:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 195:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x77,	/*=   [ ***]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 196:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 197:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xff,	/*=   [****]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 198:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 199:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x77,	/*=   [ ***]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 200:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 201:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 202:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 203:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 204:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 205:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 206:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 207:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 208:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 209:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 210:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 211:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x77,	/*=   [ ***]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 212:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 213:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 214:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x77,	/*=   [ ***]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 215:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xff,	/*=   [****]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 216:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 217:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 218:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x77,	/*=   [ ***]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 219:  */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	/*}*/
+	/*{*/ 	/*   Char 220:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	/*}*/
+	/*{*/ 	/*   Char 221:  */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 222:  */
+	0x33,	/*=   [  **]        */
+	0x33,	/*=   [  **]        */
+	0x33,	/*=   [  **]        */
+	0x33,	/*=   [  **]        */
+	0x33,	/*=   [  **]        */
+	0x33,	/*=   [  **]        */
+	/*}*/
+	/*{*/ 	/*   Char 223:  */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 224:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 225:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 226:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 227:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 228:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 229:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 230:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 231:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 232:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 233:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 234:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 235:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 236:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 237:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 238:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 239:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 240:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 241:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 242:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 243:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 244:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 245:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 246:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 247:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 248:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 249:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 250:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 251:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 252:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 253:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 254:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 255:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+};
+
+#endif
diff --git a/include/video_font_data.h b/include/video_font_data.h
new file mode 100644
index 0000000..ed5fd64
--- /dev/null
+++ b/include/video_font_data.h
@@ -0,0 +1,4629 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * This file contains an 8x16 bitmap font for code page 437.
+ */
+
+#ifndef _VIDEO_FONT_DATA_
+#define _VIDEO_FONT_DATA_
+
+#define VIDEO_FONT_CHARS	256
+#define VIDEO_FONT_WIDTH	8
+#define VIDEO_FONT_HEIGHT	16
+#define VIDEO_FONT_SIZE		(VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
+
+static unsigned char __maybe_unused video_fontdata[VIDEO_FONT_SIZE] = {
+
+	/* 0 0x00 '^@' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 1 0x01 '^A' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x81, /* 10000001 */
+	0xa5, /* 10100101 */
+	0x81, /* 10000001 */
+	0x81, /* 10000001 */
+	0xbd, /* 10111101 */
+	0x99, /* 10011001 */
+	0x81, /* 10000001 */
+	0x81, /* 10000001 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 2 0x02 '^B' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0xff, /* 11111111 */
+	0xdb, /* 11011011 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xc3, /* 11000011 */
+	0xe7, /* 11100111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 3 0x03 '^C' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 4 0x04 '^D' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x7c, /* 01111100 */
+	0xfe, /* 11111110 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 5 0x05 '^E' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0xe7, /* 11100111 */
+	0xe7, /* 11100111 */
+	0xe7, /* 11100111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 6 0x06 '^F' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 7 0x07 '^G' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 8 0x08 '^H' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xe7, /* 11100111 */
+	0xc3, /* 11000011 */
+	0xc3, /* 11000011 */
+	0xe7, /* 11100111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 9 0x09 '^I' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x42, /* 01000010 */
+	0x42, /* 01000010 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 10 0x0a '^J' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xc3, /* 11000011 */
+	0x99, /* 10011001 */
+	0xbd, /* 10111101 */
+	0xbd, /* 10111101 */
+	0x99, /* 10011001 */
+	0xc3, /* 11000011 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 11 0x0b '^K' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1e, /* 00011110 */
+	0x0e, /* 00001110 */
+	0x1a, /* 00011010 */
+	0x32, /* 00110010 */
+	0x78, /* 01111000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 12 0x0c '^L' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 13 0x0d '^M' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3f, /* 00111111 */
+	0x33, /* 00110011 */
+	0x3f, /* 00111111 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x70, /* 01110000 */
+	0xf0, /* 11110000 */
+	0xe0, /* 11100000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 14 0x0e '^N' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7f, /* 01111111 */
+	0x63, /* 01100011 */
+	0x7f, /* 01111111 */
+	0x63, /* 01100011 */
+	0x63, /* 01100011 */
+	0x63, /* 01100011 */
+	0x63, /* 01100011 */
+	0x67, /* 01100111 */
+	0xe7, /* 11100111 */
+	0xe6, /* 11100110 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 15 0x0f '^O' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xdb, /* 11011011 */
+	0x3c, /* 00111100 */
+	0xe7, /* 11100111 */
+	0x3c, /* 00111100 */
+	0xdb, /* 11011011 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 16 0x10 '^P' */
+	0x00, /* 00000000 */
+	0x80, /* 10000000 */
+	0xc0, /* 11000000 */
+	0xe0, /* 11100000 */
+	0xf0, /* 11110000 */
+	0xf8, /* 11111000 */
+	0xfe, /* 11111110 */
+	0xf8, /* 11111000 */
+	0xf0, /* 11110000 */
+	0xe0, /* 11100000 */
+	0xc0, /* 11000000 */
+	0x80, /* 10000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 17 0x11 '^Q' */
+	0x00, /* 00000000 */
+	0x02, /* 00000010 */
+	0x06, /* 00000110 */
+	0x0e, /* 00001110 */
+	0x1e, /* 00011110 */
+	0x3e, /* 00111110 */
+	0xfe, /* 11111110 */
+	0x3e, /* 00111110 */
+	0x1e, /* 00011110 */
+	0x0e, /* 00001110 */
+	0x06, /* 00000110 */
+	0x02, /* 00000010 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 18 0x12 '^R' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 19 0x13 '^S' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 20 0x14 '^T' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7f, /* 01111111 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0x7b, /* 01111011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 21 0x15 '^U' */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x0c, /* 00001100 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 22 0x16 '^V' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 23 0x17 '^W' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 24 0x18 '^X' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 25 0x19 '^Y' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 26 0x1a '^Z' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0xfe, /* 11111110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 27 0x1b '^[' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xfe, /* 11111110 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 28 0x1c '^\' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 29 0x1d '^]' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x28, /* 00101000 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x28, /* 00101000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 30 0x1e '^^' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x7c, /* 01111100 */
+	0x7c, /* 01111100 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 31 0x1f '^_' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x7c, /* 01111100 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 32 0x20 ' ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 33 0x21 '!' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 34 0x22 '"' */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x24, /* 00100100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 35 0x23 '#' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 36 0x24 '$' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0x7c, /* 01111100 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x86, /* 10000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 37 0x25 '%' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc2, /* 11000010 */
+	0xc6, /* 11000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc6, /* 11000110 */
+	0x86, /* 10000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 38 0x26 '&' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 39 0x27 ''' */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 40 0x28 '(' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 41 0x29 ')' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 42 0x2a '*' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0xff, /* 11111111 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 43 0x2b '+' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 44 0x2c ',' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 45 0x2d '-' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 46 0x2e '.' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 47 0x2f '/' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x02, /* 00000010 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0x80, /* 10000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 48 0x30 '0' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 49 0x31 '1' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x38, /* 00111000 */
+	0x78, /* 01111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 50 0x32 '2' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 51 0x33 '3' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x3c, /* 00111100 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 52 0x34 '4' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x1c, /* 00011100 */
+	0x3c, /* 00111100 */
+	0x6c, /* 01101100 */
+	0xcc, /* 11001100 */
+	0xfe, /* 11111110 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x1e, /* 00011110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 53 0x35 '5' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xfc, /* 11111100 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 54 0x36 '6' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xfc, /* 11111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 55 0x37 '7' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 56 0x38 '8' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 57 0x39 '9' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7e, /* 01111110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 58 0x3a ':' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 59 0x3b ';' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 60 0x3c '<' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 61 0x3d '=' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 62 0x3e '>' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 63 0x3f '?' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 64 0x40 '@' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xde, /* 11011110 */
+	0xde, /* 11011110 */
+	0xde, /* 11011110 */
+	0xdc, /* 11011100 */
+	0xc0, /* 11000000 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 65 0x41 'A' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 66 0x42 'B' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfc, /* 11111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xfc, /* 11111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 67 0x43 'C' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc2, /* 11000010 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 68 0x44 'D' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 69 0x45 'E' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x66, /* 01100110 */
+	0x62, /* 01100010 */
+	0x68, /* 01101000 */
+	0x78, /* 01111000 */
+	0x68, /* 01101000 */
+	0x60, /* 01100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 70 0x46 'F' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x66, /* 01100110 */
+	0x62, /* 01100010 */
+	0x68, /* 01101000 */
+	0x78, /* 01111000 */
+	0x68, /* 01101000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 71 0x47 'G' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xde, /* 11011110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x66, /* 01100110 */
+	0x3a, /* 00111010 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 72 0x48 'H' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 73 0x49 'I' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 74 0x4a 'J' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1e, /* 00011110 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 75 0x4b 'K' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe6, /* 11100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x78, /* 01111000 */
+	0x78, /* 01111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 76 0x4c 'L' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf0, /* 11110000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 77 0x4d 'M' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xee, /* 11101110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xd6, /* 11010110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 78 0x4e 'N' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xe6, /* 11100110 */
+	0xf6, /* 11110110 */
+	0xfe, /* 11111110 */
+	0xde, /* 11011110 */
+	0xce, /* 11001110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 79 0x4f 'O' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 80 0x50 'P' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfc, /* 11111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 81 0x51 'Q' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xde, /* 11011110 */
+	0x7c, /* 01111100 */
+	0x0c, /* 00001100 */
+	0x0e, /* 00001110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 82 0x52 'R' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfc, /* 11111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 83 0x53 'S' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x38, /* 00111000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 84 0x54 'T' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x5a, /* 01011010 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 85 0x55 'U' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 86 0x56 'V' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 87 0x57 'W' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xfe, /* 11111110 */
+	0xee, /* 11101110 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 88 0x58 'X' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x7c, /* 01111100 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 89 0x59 'Y' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 90 0x5a 'Z' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0x86, /* 10000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc2, /* 11000010 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 91 0x5b '[' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 92 0x5c '\' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x80, /* 10000000 */
+	0xc0, /* 11000000 */
+	0xe0, /* 11100000 */
+	0x70, /* 01110000 */
+	0x38, /* 00111000 */
+	0x1c, /* 00011100 */
+	0x0e, /* 00001110 */
+	0x06, /* 00000110 */
+	0x02, /* 00000010 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 93 0x5d ']' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 94 0x5e '^' */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 95 0x5f '_' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 96 0x60 '`' */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 97 0x61 'a' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 98 0x62 'b' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe0, /* 11100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x78, /* 01111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 99 0x63 'c' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 100 0x64 'd' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1c, /* 00011100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x3c, /* 00111100 */
+	0x6c, /* 01101100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 101 0x65 'e' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 102 0x66 'f' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1c, /* 00011100 */
+	0x36, /* 00110110 */
+	0x32, /* 00110010 */
+	0x30, /* 00110000 */
+	0x78, /* 01111000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 103 0x67 'g' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x7c, /* 01111100 */
+	0x0c, /* 00001100 */
+	0xcc, /* 11001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+
+	/* 104 0x68 'h' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe0, /* 11100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x6c, /* 01101100 */
+	0x76, /* 01110110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 105 0x69 'i' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 106 0x6a 'j' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+
+	/* 107 0x6b 'k' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe0, /* 11100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x78, /* 01111000 */
+	0x78, /* 01111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 108 0x6c 'l' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 109 0x6d 'm' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xec, /* 11101100 */
+	0xfe, /* 11111110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 110 0x6e 'n' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 111 0x6f 'o' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 112 0x70 'p' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+
+	/* 113 0x71 'q' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x7c, /* 01111100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x1e, /* 00011110 */
+	0x00, /* 00000000 */
+
+	/* 114 0x72 'r' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x76, /* 01110110 */
+	0x66, /* 01100110 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 115 0x73 's' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x38, /* 00111000 */
+	0x0c, /* 00001100 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 116 0x74 't' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0xfc, /* 11111100 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x36, /* 00110110 */
+	0x1c, /* 00011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 117 0x75 'u' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 118 0x76 'v' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 119 0x77 'w' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 120 0x78 'x' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 121 0x79 'y' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7e, /* 01111110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+
+	/* 122 0x7a 'z' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xcc, /* 11001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 123 0x7b '{' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x0e, /* 00001110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 124 0x7c '|' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 125 0x7d '}' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x70, /* 01110000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x0e, /* 00001110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 126 0x7e '~' */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 127 0x7f '' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 128 0x80 '€' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc2, /* 11000010 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 129 0x81 '�' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 130 0x82 '‚' */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 131 0x83 'ƒ' */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 132 0x84 '„' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 133 0x85 '…' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 134 0x86 '†' */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 135 0x87 '‡' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 136 0x88 'ˆ' */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 137 0x89 '‰' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 138 0x8a 'Š' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 139 0x8b '‹' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 140 0x8c 'Œ' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 141 0x8d '�' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 142 0x8e 'Ž' */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 143 0x8f '�' */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 144 0x90 '�' */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x66, /* 01100110 */
+	0x62, /* 01100010 */
+	0x68, /* 01101000 */
+	0x78, /* 01111000 */
+	0x68, /* 01101000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 145 0x91 '‘' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xec, /* 11101100 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x7e, /* 01111110 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0x6e, /* 01101110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 146 0x92 '’' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3e, /* 00111110 */
+	0x6c, /* 01101100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xfe, /* 11111110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xce, /* 11001110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 147 0x93 '“' */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 148 0x94 '”' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 149 0x95 '•' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 150 0x96 '–' */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x78, /* 01111000 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 151 0x97 '—' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 152 0x98 '˜' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7e, /* 01111110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+
+	/* 153 0x99 '™' */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 154 0x9a 'š' */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 155 0x9b '›' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 156 0x9c 'œ' */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x64, /* 01100100 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xe6, /* 11100110 */
+	0xfc, /* 11111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 157 0x9d '�' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 158 0x9e 'ž' */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xf8, /* 11111000 */
+	0xc4, /* 11000100 */
+	0xcc, /* 11001100 */
+	0xde, /* 11011110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 159 0x9f 'Ÿ' */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x1b, /* 00011011 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xd8, /* 11011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 160 0xa0 ' ' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 161 0xa1 '¡' */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 162 0xa2 '¢' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 163 0xa3 '£' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 164 0xa4 '¤' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 165 0xa5 '¥' */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xe6, /* 11100110 */
+	0xf6, /* 11110110 */
+	0xfe, /* 11111110 */
+	0xde, /* 11011110 */
+	0xce, /* 11001110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 166 0xa6 '¦' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x3e, /* 00111110 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 167 0xa7 '§' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 168 0xa8 '¨' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 169 0xa9 '©' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 170 0xaa 'ª' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 171 0xab '«' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0xe0, /* 11100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xdc, /* 11011100 */
+	0x86, /* 10000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x3e, /* 00111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 172 0xac '¬' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0xe0, /* 11100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x66, /* 01100110 */
+	0xce, /* 11001110 */
+	0x9a, /* 10011010 */
+	0x3f, /* 00111111 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 173 0xad '­' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 174 0xae '®' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x36, /* 00110110 */
+	0x6c, /* 01101100 */
+	0xd8, /* 11011000 */
+	0x6c, /* 01101100 */
+	0x36, /* 00110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 175 0xaf '¯' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xd8, /* 11011000 */
+	0x6c, /* 01101100 */
+	0x36, /* 00110110 */
+	0x6c, /* 01101100 */
+	0xd8, /* 11011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 176 0xb0 '°' */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+
+	/* 177 0xb1 '±' */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+
+	/* 178 0xb2 '²' */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+
+	/* 179 0xb3 '³' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 180 0xb4 '´' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 181 0xb5 'µ' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 182 0xb6 '¶' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf6, /* 11110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 183 0xb7 '·' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 184 0xb8 '¸' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 185 0xb9 '¹' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf6, /* 11110110 */
+	0x06, /* 00000110 */
+	0xf6, /* 11110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 186 0xba 'º' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 187 0xbb '»' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x06, /* 00000110 */
+	0xf6, /* 11110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 188 0xbc '¼' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf6, /* 11110110 */
+	0x06, /* 00000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 189 0xbd '½' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 190 0xbe '¾' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 191 0xbf '¿' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 192 0xc0 'À' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 193 0xc1 'Á' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 194 0xc2 'Â' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 195 0xc3 'Ã' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 196 0xc4 'Ä' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 197 0xc5 'Å' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 198 0xc6 'Æ' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 199 0xc7 'Ç' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x37, /* 00110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 200 0xc8 'È' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x37, /* 00110111 */
+	0x30, /* 00110000 */
+	0x3f, /* 00111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 201 0xc9 'É' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3f, /* 00111111 */
+	0x30, /* 00110000 */
+	0x37, /* 00110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 202 0xca 'Ê' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf7, /* 11110111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 203 0xcb 'Ë' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xf7, /* 11110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 204 0xcc 'Ì' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x37, /* 00110111 */
+	0x30, /* 00110000 */
+	0x37, /* 00110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 205 0xcd 'Í' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 206 0xce 'Î' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf7, /* 11110111 */
+	0x00, /* 00000000 */
+	0xf7, /* 11110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 207 0xcf 'Ï' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 208 0xd0 'Ð' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 209 0xd1 'Ñ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 210 0xd2 'Ò' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 211 0xd3 'Ó' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x3f, /* 00111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 212 0xd4 'Ô' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 213 0xd5 'Õ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 214 0xd6 'Ö' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3f, /* 00111111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 215 0xd7 '×' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xff, /* 11111111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 216 0xd8 'Ø' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 217 0xd9 'Ù' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 218 0xda 'Ú' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 219 0xdb 'Û' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 220 0xdc 'Ü' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 221 0xdd 'Ý' */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+
+	/* 222 0xde 'Þ' */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+
+	/* 223 0xdf 'ß' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 224 0xe0 'à' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xdc, /* 11011100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 225 0xe1 'á' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xd8, /* 11011000 */
+	0xcc, /* 11001100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 226 0xe2 'â' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 227 0xe3 'ã' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 228 0xe4 'ä' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 229 0xe5 'å' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 230 0xe6 'æ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+
+	/* 231 0xe7 'ç' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 232 0xe8 'è' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 233 0xe9 'é' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 234 0xea 'ê' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0xee, /* 11101110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 235 0xeb 'ë' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1e, /* 00011110 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x3e, /* 00111110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 236 0xec 'ì' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 237 0xed 'í' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x03, /* 00000011 */
+	0x06, /* 00000110 */
+	0x7e, /* 01111110 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0xf3, /* 11110011 */
+	0x7e, /* 01111110 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 238 0xee 'î' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1c, /* 00011100 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x1c, /* 00011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 239 0xef 'ï' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 240 0xf0 'ð' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 241 0xf1 'ñ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 242 0xf2 'ò' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 243 0xf3 'ó' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 244 0xf4 'ô' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 245 0xf5 'õ' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 246 0xf6 'ö' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 247 0xf7 '÷' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 248 0xf8 'ø' */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 249 0xf9 'ù' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 250 0xfa 'ú' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 251 0xfb 'û' */
+	0x00, /* 00000000 */
+	0x0f, /* 00001111 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0xec, /* 11101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x3c, /* 00111100 */
+	0x1c, /* 00011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 252 0xfc 'ü' */
+	0x00, /* 00000000 */
+	0x6c, /* 01101100 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 253 0xfd 'ý' */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x32, /* 00110010 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 254 0xfe 'þ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 255 0xff 'ÿ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+};
+
+#endif
diff --git a/include/video_osd.h b/include/video_osd.h
new file mode 100644
index 0000000..01ac94b
--- /dev/null
+++ b/include/video_osd.h
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2017
+ * Mario Six,  Guntermann & Drunck GmbH, mario.six@gdsys.cc
+ */
+
+#ifndef _VIDEO_OSD_H_
+#define _VIDEO_OSD_H_
+
+struct video_osd_info {
+	/* The width of the OSD display in columns */
+	uint width;
+	/* The height of the OSD display in rows */
+	uint height;
+	/* The major version of the OSD device */
+	uint major_version;
+	/* The minor version of the OSD device */
+	uint minor_version;
+};
+
+/**
+ * struct video_osd_ops - driver operations for OSD uclass
+ *
+ * The OSD uclass implements support for text-oriented on-screen displays,
+ * which are taken to be devices that independently display a graphical
+ * text-based overlay over the video output of an associated display.
+ *
+ * The functions defined by the uclass support writing text to the display in
+ * either a generic form (by specifying a string, a driver-specific color value
+ * for the text, and screen coordinates in rows and columns) or a
+ * driver-specific form (by specifying "raw" driver-specific data to display at
+ * a given coordinate).
+ *
+ * Functions to read device information and set the size of the virtual OSD
+ * screen (in rows and columns) are also supported.
+ *
+ * Drivers should support these operations unless otherwise noted. These
+ * operations are intended to be used by uclass code, not directly from
+ * other code.
+ */
+struct video_osd_ops {
+	/**
+	 * get_info() - Get information about a OSD instance
+	 *
+	 * A OSD instance may keep some internal data about itself. This
+	 * function can be used to access this data.
+	 *
+	 * @dev:	OSD instance to query.
+	 * @info:	Pointer to a structure that takes the information read
+	 *		from the OSD instance.
+	 * @return 0 if OK, -ve on error.
+	 */
+	int (*get_info)(struct udevice *dev, struct video_osd_info *info);
+
+	/**
+	 * set_mem() - Write driver-specific text data to OSD screen
+	 *
+	 * The passed data are device-specific, and it's up to the driver how
+	 * to interpret them. How the count parameter is interpreted is also
+	 * driver-specific; most likely the given data will be written to the
+	 * OSD count times back-to-back, which is e.g. convenient for filling
+	 * areas of the OSD with a single character.
+	 *
+	 * For example a invocation of
+	 *
+	 * video_osd_set_mem(dev, 0, 0, "A", 1, 10);
+	 *
+	 * will write the device-specific text data "A" to the positions (0, 0)
+	 * to (9, 0) on the OSD.
+	 *
+	 * Device-specific text data may, e.g. be a special encoding of glyphs
+	 * to display and color values in binary format.
+	 *
+	 * @dev:	OSD instance to write to.
+	 * @col:	Horizontal character coordinate to write to.
+	 * @row		Vertical character coordinate to write to.
+	 * @buf:	Array containing device-specific data to write to the
+	 *		specified coordinate on the OSD screen.
+	 * @buflen:	Length of the data in the passed buffer (in byte).
+	 * @count:	Write count many repetitions of the given text data
+	 * @return 0 if OK, -ve on error.
+	 */
+	int (*set_mem)(struct udevice *dev, uint col, uint row, u8 *buf,
+		       size_t buflen, uint count);
+
+	/**
+	 * set_size() - Set the position and dimension of the OSD's
+	 *              writeable window
+	 *
+	 * @dev:	OSD instance to write to.
+	 * @col		The number of characters in the window's columns
+	 * @row		The number of characters in the window's rows
+	 * @return 0 if OK, -ve on error.
+	 */
+	int (*set_size)(struct udevice *dev, uint col, uint row);
+
+	/**
+	 * print() - Print a string in a given color to specified coordinates
+	 *	     on the OSD
+	 *
+	 * @dev:	OSD instance to write to.
+	 * @col		The x-coordinate of the position the string should be
+	 *		written to
+	 * @row		The y-coordinate of the position the string should be
+	 *		written to
+	 * @color:	The color in which the specified string should be
+	 *		printed; the interpretation of the value is
+	 *		driver-specific, and possible values should be defined
+	 *		e.g. in a driver include file.
+	 * @text:	The string data that should be printed on the OSD
+	 * @return 0 if OK, -ve on error.
+	 */
+	int (*print)(struct udevice *dev, uint col, uint row, ulong color,
+		     char *text);
+};
+
+#define video_osd_get_ops(dev)	((struct video_osd_ops *)(dev)->driver->ops)
+
+/**
+ * video_osd_get_info() - Get information about a OSD instance
+ *
+ * A OSD instance may keep some internal data about itself. This function can
+ * be used to access this data.
+ *
+ * @dev:	OSD instance to query.
+ * @info:	Pointer to a structure that takes the information read from the
+ *		OSD instance.
+ * @return 0 if OK, -ve on error.
+ */
+int video_osd_get_info(struct udevice *dev, struct video_osd_info *info);
+
+/**
+ * video_osd_set_mem() - Write text data to OSD memory
+ *
+ * The passed data are device-specific, and it's up to the driver how to
+ * interpret them. How the count parameter is interpreted is also
+ * driver-specific; most likely the given data will be written to the OSD count
+ * times back-to-back, which is e.g. convenient for filling areas of the OSD
+ * with a single character.
+ *
+ * For example a invocation of
+ *
+ * video_osd_set_mem(dev, 0, 0, "A", 1, 10);
+ *
+ * will write the device-specific text data "A" to the positions (0, 0) to (9,
+ * 0) on the OSD.
+ *
+ * Device-specific text data may, e.g. be a special encoding of glyphs to
+ * display and color values in binary format.
+ *
+ * @dev:	OSD instance to write to.
+ * @col:	Horizontal character coordinate to write to.
+ * @row		Vertical character coordinate to write to.
+ * @buf:	Array containing device-specific data to write to the specified
+ *		coordinate on the OSD screen.
+ * @buflen:	Length of the data in the passed buffer (in byte).
+ * @count:	Write count many repetitions of the given text data
+ * @return 0 if OK, -ve on error.
+ */
+int video_osd_set_mem(struct udevice *dev, uint col, uint row, u8 *buf,
+		      size_t buflen, uint count);
+
+/**
+ * video_osd_set_size() - Set the position and dimension of the OSD's
+ *              writeable window
+ *
+ * @dev:	OSD instance to write to.
+ * @col		The number of characters in the window's columns
+ * @row		The number of characters in the window's rows
+ * @return 0 if OK, -ve on error.
+ */
+int video_osd_set_size(struct udevice *dev, uint col, uint row);
+
+/**
+ * video_osd_print() - Print a string in a given color to specified coordinates
+ *		       on the OSD
+ *
+ * @dev:	OSD instance to write to.
+ * @col		The x-coordinate of the position the string should be written
+ *		to
+ * @row		The y-coordinate of the position the string should be written
+ *		to
+ * @color:	The color in which the specified string should be printed; the
+ *		interpretation of the value is driver-specific, and possible
+ *		values should be defined e.g. in a driver include file.
+ * @text:	The string data that should be printed on the OSD
+ * @return 0 if OK, -ve on error.
+ */
+int video_osd_print(struct udevice *dev, uint col, uint row, ulong color,
+		    char *text);
+
+#endif /* !_VIDEO_OSD_H_ */
diff --git a/include/virtex2.h b/include/virtex2.h
new file mode 100644
index 0000000..7e8d93f
--- /dev/null
+++ b/include/virtex2.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com
+ */
+
+#ifndef _VIRTEX2_H_
+#define _VIRTEX2_H_
+
+#include <xilinx.h>
+
+/*
+ * Slave SelectMap or Serial Implementation function table.
+ */
+typedef struct {
+	xilinx_pre_fn	pre;
+	xilinx_pgm_fn	pgm;
+	xilinx_init_fn	init;
+	xilinx_err_fn	err;
+	xilinx_done_fn	done;
+	xilinx_clk_fn	clk;
+	xilinx_cs_fn	cs;
+	xilinx_wr_fn	wr;
+	xilinx_rdata_fn	rdata;
+	xilinx_wdata_fn	wdata;
+	xilinx_bwr_fn   wbulkdata;
+	xilinx_busy_fn	busy;
+	xilinx_abort_fn	abort;
+	xilinx_post_fn	post;
+} xilinx_virtex2_slave_fns;
+
+#if defined(CONFIG_FPGA_VIRTEX2)
+extern struct xilinx_fpga_op virtex2_op;
+# define FPGA_VIRTEX2_OPS	&virtex2_op
+#else
+# define FPGA_VIRTEX2_OPS	NULL
+#endif
+
+/* Device Image Sizes (in bytes)
+ *********************************************************************/
+#define XILINX_XC2V40_SIZE	(338208 / 8)
+#define XILINX_XC2V80_SIZE	(597408 / 8)
+#define XILINX_XC2V250_SIZE	(1591584 / 8)
+#define XILINX_XC2V500_SIZE	(2557857 / 8)
+#define XILINX_XC2V1000_SIZE	(3749408 / 8)
+#define XILINX_XC2V1500_SIZE	(5166240 / 8)
+#define XILINX_XC2V2000_SIZE	(6808352 / 8)
+#define XILINX_XC2V3000_SIZE	(9589408 / 8)
+#define XILINX_XC2V4000_SIZE	(14220192 / 8)
+#define XILINX_XC2V6000_SIZE	(19752096 / 8)
+#define XILINX_XC2V8000_SIZE	(26185120 / 8)
+#define XILINX_XC2V10000_SIZE	(33519264 / 8)
+
+/* Descriptor Macros
+ *********************************************************************/
+#define XILINX_XC2V40_DESC(iface, fn_table, cookie)	\
+{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
+	FPGA_VIRTEX2_OPS }
+
+#endif /* _VIRTEX2_H_ */
diff --git a/include/virtio.h b/include/virtio.h
new file mode 100644
index 0000000..654fdf1
--- /dev/null
+++ b/include/virtio.h
@@ -0,0 +1,707 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * VirtIO is a virtualization standard for network and disk device drivers
+ * where just the guest's device driver "knows" it is running in a virtual
+ * environment, and cooperates with the hypervisor. This enables guests to
+ * get high performance network and disk operations, and gives most of the
+ * performance benefits of paravirtualization. In the U-Boot case, the guest
+ * is U-Boot itself, while the virtual environment are normally QEMU targets
+ * like ARM, RISC-V and x86.
+ *
+ * See http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf for
+ * the VirtIO specification v1.0.
+ *
+ * This file is largely based on Linux kernel virtio_*.h files
+ */
+
+#ifndef __VIRTIO_H__
+#define __VIRTIO_H__
+
+#define VIRTIO_ID_NET		1 /* virtio net */
+#define VIRTIO_ID_BLOCK		2 /* virtio block */
+#define VIRTIO_ID_MAX_NUM	3
+
+#define VIRTIO_NET_DRV_NAME	"virtio-net"
+#define VIRTIO_BLK_DRV_NAME	"virtio-blk"
+
+/* Status byte for guest to report progress, and synchronize features */
+
+/* We have seen device and processed generic fields (VIRTIO_CONFIG_F_VIRTIO) */
+#define VIRTIO_CONFIG_S_ACKNOWLEDGE	1
+/* We have found a driver for the device */
+#define VIRTIO_CONFIG_S_DRIVER		2
+/* Driver has used its parts of the config, and is happy */
+#define VIRTIO_CONFIG_S_DRIVER_OK	4
+/* Driver has finished configuring features */
+#define VIRTIO_CONFIG_S_FEATURES_OK	8
+/* Device entered invalid state, driver must reset it */
+#define VIRTIO_CONFIG_S_NEEDS_RESET	0x40
+/* We've given up on this device */
+#define VIRTIO_CONFIG_S_FAILED		0x80
+
+/*
+ * Virtio feature bits VIRTIO_TRANSPORT_F_START through VIRTIO_TRANSPORT_F_END
+ * are reserved for the transport being used (eg: virtio_ring, virtio_pci etc.),
+ * the rest are per-device feature bits.
+ */
+#define VIRTIO_TRANSPORT_F_START	28
+#define VIRTIO_TRANSPORT_F_END		38
+
+#ifndef VIRTIO_CONFIG_NO_LEGACY
+/*
+ * Do we get callbacks when the ring is completely used,
+ * even if we've suppressed them?
+ */
+#define VIRTIO_F_NOTIFY_ON_EMPTY	24
+
+/* Can the device handle any descriptor layout? */
+#define VIRTIO_F_ANY_LAYOUT		27
+#endif /* VIRTIO_CONFIG_NO_LEGACY */
+
+/* v1.0 compliant */
+#define VIRTIO_F_VERSION_1		32
+
+/*
+ * If clear - device has the IOMMU bypass quirk feature.
+ * If set - use platform tools to detect the IOMMU.
+ *
+ * Note the reverse polarity (compared to most other features),
+ * this is for compatibility with legacy systems.
+ */
+#define VIRTIO_F_IOMMU_PLATFORM		33
+
+/* Does the device support Single Root I/O Virtualization? */
+#define VIRTIO_F_SR_IOV			37
+
+/**
+ * virtio scatter-gather struct
+ *
+ * @addr:		sg buffer address
+ * @lengh:		sg buffer length
+ */
+struct virtio_sg {
+	void *addr;
+	size_t length;
+};
+
+struct virtqueue;
+
+/* virtio bus operations */
+struct dm_virtio_ops {
+	/**
+	 * get_config() - read the value of a configuration field
+	 *
+	 * @vdev:	the real virtio device
+	 * @offset:	the offset of the configuration field
+	 * @buf:	the buffer to write the field value into
+	 * @len:	the length of the buffer
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_config)(struct udevice *vdev, unsigned int offset,
+			  void *buf, unsigned int len);
+	/**
+	 * set_config() - write the value of a configuration field
+	 *
+	 * @vdev:	the real virtio device
+	 * @offset:	the offset of the configuration field
+	 * @buf:	the buffer to read the field value from
+	 * @len:	the length of the buffer
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_config)(struct udevice *vdev, unsigned int offset,
+			  const void *buf, unsigned int len);
+	/**
+	 * generation() - config generation counter
+	 *
+	 * @vdev:	the real virtio device
+	 * @counter:	the returned config generation counter
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*generation)(struct udevice *vdev, u32 *counter);
+	/**
+	 * get_status() - read the status byte
+	 *
+	 * @vdev:	the real virtio device
+	 * @status:	the returned status byte
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_status)(struct udevice *vdev, u8 *status);
+	/**
+	 * set_status() - write the status byte
+	 *
+	 * @vdev:	the real virtio device
+	 * @status:	the new status byte
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_status)(struct udevice *vdev, u8 status);
+	/**
+	 * reset() - reset the device
+	 *
+	 * @vdev:	the real virtio device
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*reset)(struct udevice *vdev);
+	/**
+	 * get_features() - get the array of feature bits for this device
+	 *
+	 * @vdev:	the real virtio device
+	 * @features:	the first 32 feature bits (all we currently need)
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*get_features)(struct udevice *vdev, u64 *features);
+	/**
+	 * set_features() - confirm what device features we'll be using
+	 *
+	 * @vdev:	the real virtio device
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*set_features)(struct udevice *vdev);
+	/**
+	 * find_vqs() - find virtqueues and instantiate them
+	 *
+	 * @vdev:	the real virtio device
+	 * @nvqs:	the number of virtqueues to find
+	 * @vqs:	on success, includes new virtqueues
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*find_vqs)(struct udevice *vdev, unsigned int nvqs,
+			struct virtqueue *vqs[]);
+	/**
+	 * del_vqs() - free virtqueues found by find_vqs()
+	 *
+	 * @vdev:	the real virtio device
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*del_vqs)(struct udevice *vdev);
+	/**
+	 * notify() - notify the device to process the queue
+	 *
+	 * @vdev:	the real virtio device
+	 * @vq:		virtqueue to process
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*notify)(struct udevice *vdev, struct virtqueue *vq);
+};
+
+/* Get access to a virtio bus' operations */
+#define virtio_get_ops(dev)	((struct dm_virtio_ops *)(dev)->driver->ops)
+
+/**
+ * virtio uclass per device private data
+ *
+ * @vqs:			virtualqueue for the virtio device
+ * @vdev:			the real virtio device underneath
+ * @legacy:			is it a legacy device?
+ * @device:			virtio device ID
+ * @vendor:			virtio vendor ID
+ * @features:			negotiated supported features
+ * @feature_table:		an array of feature supported by the driver
+ * @feature_table_size:		number of entries in the feature table array
+ * @feature_table_legacy:	same as feature_table but working in legacy mode
+ * @feature_table_size_legacy:	number of entries in feature table legacy array
+ */
+struct virtio_dev_priv {
+	struct list_head vqs;
+	struct udevice *vdev;
+	bool legacy;
+	u32 device;
+	u32 vendor;
+	u64 features;
+	const u32 *feature_table;
+	u32 feature_table_size;
+	const u32 *feature_table_legacy;
+	u32 feature_table_size_legacy;
+};
+
+/**
+ * virtio_get_config() - read the value of a configuration field
+ *
+ * @vdev:	the real virtio device
+ * @offset:	the offset of the configuration field
+ * @buf:	the buffer to write the field value into
+ * @len:	the length of the buffer
+ * @return 0 if OK, -ve on error
+ */
+int virtio_get_config(struct udevice *vdev, unsigned int offset,
+		      void *buf, unsigned int len);
+
+/**
+ * virtio_set_config() - write the value of a configuration field
+ *
+ * @vdev:	the real virtio device
+ * @offset:	the offset of the configuration field
+ * @buf:	the buffer to read the field value from
+ * @len:	the length of the buffer
+ * @return 0 if OK, -ve on error
+ */
+int virtio_set_config(struct udevice *vdev, unsigned int offset,
+		      void *buf, unsigned int len);
+
+/**
+ * virtio_generation() - config generation counter
+ *
+ * @vdev:	the real virtio device
+ * @counter:	the returned config generation counter
+ * @return 0 if OK, -ve on error
+ */
+int virtio_generation(struct udevice *vdev, u32 *counter);
+
+/**
+ * virtio_get_status() - read the status byte
+ *
+ * @vdev:	the real virtio device
+ * @status:	the returned status byte
+ * @return 0 if OK, -ve on error
+ */
+int virtio_get_status(struct udevice *vdev, u8 *status);
+
+/**
+ * virtio_set_status() - write the status byte
+ *
+ * @vdev:	the real virtio device
+ * @status:	the new status byte
+ * @return 0 if OK, -ve on error
+ */
+int virtio_set_status(struct udevice *vdev, u8 status);
+
+/**
+ * virtio_reset() - reset the device
+ *
+ * @vdev:	the real virtio device
+ * @return 0 if OK, -ve on error
+ */
+int virtio_reset(struct udevice *vdev);
+
+/**
+ * virtio_get_features() - get the array of feature bits for this device
+ *
+ * @vdev:	the real virtio device
+ * @features:	the first 32 feature bits (all we currently need)
+ * @return 0 if OK, -ve on error
+ */
+int virtio_get_features(struct udevice *vdev, u64 *features);
+
+/**
+ * virtio_set_features() - confirm what device features we'll be using
+ *
+ * @vdev:	the real virtio device
+ * @return 0 if OK, -ve on error
+ */
+int virtio_set_features(struct udevice *vdev);
+
+/**
+ * virtio_find_vqs() - find virtqueues and instantiate them
+ *
+ * @vdev:	the real virtio device
+ * @nvqs:	the number of virtqueues to find
+ * @vqs:	on success, includes new virtqueues
+ * @return 0 if OK, -ve on error
+ */
+int virtio_find_vqs(struct udevice *vdev, unsigned int nvqs,
+		    struct virtqueue *vqs[]);
+
+/**
+ * virtio_del_vqs() - free virtqueues found by find_vqs()
+ *
+ * @vdev:	the real virtio device
+ * @return 0 if OK, -ve on error
+ */
+int virtio_del_vqs(struct udevice *vdev);
+
+/**
+ * virtio_notify() - notify the device to process the queue
+ *
+ * @vdev:	the real virtio device
+ * @vq:		virtqueue to process
+ * @return 0 if OK, -ve on error
+ */
+int virtio_notify(struct udevice *vdev, struct virtqueue *vq);
+
+/**
+ * virtio_add_status() - helper to set a new status code to the device
+ *
+ * @vdev:	the real virtio device
+ * @status:	new status code to be added
+ */
+void virtio_add_status(struct udevice *vdev, u8 status);
+
+/**
+ * virtio_finalize_features() - helper to finalize features
+ *
+ * @vdev:	the real virtio device
+ * @return 0 if OK, -ve on error
+ */
+int virtio_finalize_features(struct udevice *vdev);
+
+/**
+ * virtio_driver_features_init() - initialize driver supported features
+ *
+ * This fills in the virtio device parent per child private data with the given
+ * information, which contains driver supported features and legacy features.
+ *
+ * This API should be called in the virtio device driver's bind method, so that
+ * later virtio transport uclass driver can utilize the driver supplied features
+ * to negotiate with the device on the final supported features.
+ *
+ * @priv:		virtio uclass per device private data
+ * @feature:		an array of feature supported by the driver
+ * @feature_size:	number of entries in the feature table array
+ * @feature_legacy:	same as feature_table but working in legacy mode
+ * @feature_legacy_size:number of entries in feature table legacy array
+ */
+void virtio_driver_features_init(struct virtio_dev_priv *priv,
+				 const u32 *feature,
+				 u32 feature_size,
+				 const u32 *feature_legacy,
+				 u32 feature_legacy_size);
+
+/**
+ * virtio_init() - helper to enumerate all known virtio devices
+ *
+ * @return 0 if OK, -ve on error
+ */
+int virtio_init(void);
+
+static inline u16 __virtio16_to_cpu(bool little_endian, __virtio16 val)
+{
+	if (little_endian)
+		return le16_to_cpu((__force __le16)val);
+	else
+		return be16_to_cpu((__force __be16)val);
+}
+
+static inline __virtio16 __cpu_to_virtio16(bool little_endian, u16 val)
+{
+	if (little_endian)
+		return (__force __virtio16)cpu_to_le16(val);
+	else
+		return (__force __virtio16)cpu_to_be16(val);
+}
+
+static inline u32 __virtio32_to_cpu(bool little_endian, __virtio32 val)
+{
+	if (little_endian)
+		return le32_to_cpu((__force __le32)val);
+	else
+		return be32_to_cpu((__force __be32)val);
+}
+
+static inline __virtio32 __cpu_to_virtio32(bool little_endian, u32 val)
+{
+	if (little_endian)
+		return (__force __virtio32)cpu_to_le32(val);
+	else
+		return (__force __virtio32)cpu_to_be32(val);
+}
+
+static inline u64 __virtio64_to_cpu(bool little_endian, __virtio64 val)
+{
+	if (little_endian)
+		return le64_to_cpu((__force __le64)val);
+	else
+		return be64_to_cpu((__force __be64)val);
+}
+
+static inline __virtio64 __cpu_to_virtio64(bool little_endian, u64 val)
+{
+	if (little_endian)
+		return (__force __virtio64)cpu_to_le64(val);
+	else
+		return (__force __virtio64)cpu_to_be64(val);
+}
+
+/**
+ * __virtio_test_bit - helper to test feature bits
+ *
+ * For use by transports. Devices should normally use virtio_has_feature,
+ * which includes more checks.
+ *
+ * @udev: the transport device
+ * @fbit: the feature bit
+ */
+static inline bool __virtio_test_bit(struct udevice *udev, unsigned int fbit)
+{
+	struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
+
+	/* Did you forget to fix assumptions on max features? */
+	if (__builtin_constant_p(fbit))
+		BUILD_BUG_ON(fbit >= 64);
+	else
+		WARN_ON(fbit >= 64);
+
+	return uc_priv->features & BIT_ULL(fbit);
+}
+
+/**
+ * __virtio_set_bit - helper to set feature bits
+ *
+ * For use by transports.
+ *
+ * @udev: the transport device
+ * @fbit: the feature bit
+ */
+static inline void __virtio_set_bit(struct udevice *udev, unsigned int fbit)
+{
+	struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
+
+	/* Did you forget to fix assumptions on max features? */
+	if (__builtin_constant_p(fbit))
+		BUILD_BUG_ON(fbit >= 64);
+	else
+		WARN_ON(fbit >= 64);
+
+	uc_priv->features |= BIT_ULL(fbit);
+}
+
+/**
+ * __virtio_clear_bit - helper to clear feature bits
+ *
+ * For use by transports.
+ *
+ * @vdev: the transport device
+ * @fbit: the feature bit
+ */
+static inline void __virtio_clear_bit(struct udevice *udev, unsigned int fbit)
+{
+	struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
+
+	/* Did you forget to fix assumptions on max features? */
+	if (__builtin_constant_p(fbit))
+		BUILD_BUG_ON(fbit >= 64);
+	else
+		WARN_ON(fbit >= 64);
+
+	uc_priv->features &= ~BIT_ULL(fbit);
+}
+
+/**
+ * virtio_has_feature - helper to determine if this device has this feature
+ *
+ * Note this API is only usable after the virtio device driver's bind phase,
+ * as the feature has been negotiated between the device and the driver.
+ *
+ * @vdev: the virtio device
+ * @fbit: the feature bit
+ */
+static inline bool virtio_has_feature(struct udevice *vdev, unsigned int fbit)
+{
+	if (!(vdev->flags & DM_FLAG_BOUND))
+		WARN_ON(true);
+
+	return __virtio_test_bit(vdev->parent, fbit);
+}
+
+static inline bool virtio_legacy_is_little_endian(void)
+{
+#ifdef __LITTLE_ENDIAN
+	return true;
+#else
+	return false;
+#endif
+}
+
+static inline bool virtio_is_little_endian(struct udevice *vdev)
+{
+	struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(vdev->parent);
+
+	return !uc_priv->legacy || virtio_legacy_is_little_endian();
+}
+
+/* Memory accessors */
+static inline u16 virtio16_to_cpu(struct udevice *vdev, __virtio16 val)
+{
+	return __virtio16_to_cpu(virtio_is_little_endian(vdev), val);
+}
+
+static inline __virtio16 cpu_to_virtio16(struct udevice *vdev, u16 val)
+{
+	return __cpu_to_virtio16(virtio_is_little_endian(vdev), val);
+}
+
+static inline u32 virtio32_to_cpu(struct udevice *vdev, __virtio32 val)
+{
+	return __virtio32_to_cpu(virtio_is_little_endian(vdev), val);
+}
+
+static inline __virtio32 cpu_to_virtio32(struct udevice *vdev, u32 val)
+{
+	return __cpu_to_virtio32(virtio_is_little_endian(vdev), val);
+}
+
+static inline u64 virtio64_to_cpu(struct udevice *vdev, __virtio64 val)
+{
+	return __virtio64_to_cpu(virtio_is_little_endian(vdev), val);
+}
+
+static inline __virtio64 cpu_to_virtio64(struct udevice *vdev, u64 val)
+{
+	return __cpu_to_virtio64(virtio_is_little_endian(vdev), val);
+}
+
+/* Read @count fields, @bytes each */
+static inline void __virtio_cread_many(struct udevice *vdev,
+				       unsigned int offset,
+				       void *buf, size_t count, size_t bytes)
+{
+	u32 old, gen;
+	int i;
+
+	/* no need to check return value as generation can be optional */
+	virtio_generation(vdev, &gen);
+	do {
+		old = gen;
+
+		for (i = 0; i < count; i++)
+			virtio_get_config(vdev, offset + bytes * i,
+					  buf + i * bytes, bytes);
+
+		virtio_generation(vdev, &gen);
+	} while (gen != old);
+}
+
+static inline void virtio_cread_bytes(struct udevice *vdev,
+				      unsigned int offset,
+				      void *buf, size_t len)
+{
+	__virtio_cread_many(vdev, offset, buf, len, 1);
+}
+
+static inline u8 virtio_cread8(struct udevice *vdev, unsigned int offset)
+{
+	u8 ret;
+
+	virtio_get_config(vdev, offset, &ret, sizeof(ret));
+	return ret;
+}
+
+static inline void virtio_cwrite8(struct udevice *vdev,
+				  unsigned int offset, u8 val)
+{
+	virtio_set_config(vdev, offset, &val, sizeof(val));
+}
+
+static inline u16 virtio_cread16(struct udevice *vdev,
+				 unsigned int offset)
+{
+	u16 ret;
+
+	virtio_get_config(vdev, offset, &ret, sizeof(ret));
+	return virtio16_to_cpu(vdev, (__force __virtio16)ret);
+}
+
+static inline void virtio_cwrite16(struct udevice *vdev,
+				   unsigned int offset, u16 val)
+{
+	val = (__force u16)cpu_to_virtio16(vdev, val);
+	virtio_set_config(vdev, offset, &val, sizeof(val));
+}
+
+static inline u32 virtio_cread32(struct udevice *vdev,
+				 unsigned int offset)
+{
+	u32 ret;
+
+	virtio_get_config(vdev, offset, &ret, sizeof(ret));
+	return virtio32_to_cpu(vdev, (__force __virtio32)ret);
+}
+
+static inline void virtio_cwrite32(struct udevice *vdev,
+				   unsigned int offset, u32 val)
+{
+	val = (__force u32)cpu_to_virtio32(vdev, val);
+	virtio_set_config(vdev, offset, &val, sizeof(val));
+}
+
+static inline u64 virtio_cread64(struct udevice *vdev,
+				 unsigned int offset)
+{
+	u64 ret;
+
+	__virtio_cread_many(vdev, offset, &ret, 1, sizeof(ret));
+	return virtio64_to_cpu(vdev, (__force __virtio64)ret);
+}
+
+static inline void virtio_cwrite64(struct udevice *vdev,
+				   unsigned int offset, u64 val)
+{
+	val = (__force u64)cpu_to_virtio64(vdev, val);
+	virtio_set_config(vdev, offset, &val, sizeof(val));
+}
+
+/* Config space read accessor */
+#define virtio_cread(vdev, structname, member, ptr)			\
+	do {								\
+		/* Must match the member's type, and be integer */	\
+		if (!typecheck(typeof((((structname *)0)->member)), *(ptr))) \
+			(*ptr) = 1;					\
+									\
+		switch (sizeof(*ptr)) {					\
+		case 1:							\
+			*(ptr) = virtio_cread8(vdev,			\
+					       offsetof(structname, member)); \
+			break;						\
+		case 2:							\
+			*(ptr) = virtio_cread16(vdev,			\
+						offsetof(structname, member)); \
+			break;						\
+		case 4:							\
+			*(ptr) = virtio_cread32(vdev,			\
+						offsetof(structname, member)); \
+			break;						\
+		case 8:							\
+			*(ptr) = virtio_cread64(vdev,			\
+						offsetof(structname, member)); \
+			break;						\
+		default:						\
+			WARN_ON(true);					\
+		}							\
+	} while (0)
+
+/* Config space write accessor */
+#define virtio_cwrite(vdev, structname, member, ptr)			\
+	do {								\
+		/* Must match the member's type, and be integer */	\
+		if (!typecheck(typeof((((structname *)0)->member)), *(ptr))) \
+			WARN_ON((*ptr) == 1);				\
+									\
+		switch (sizeof(*ptr)) {					\
+		case 1:							\
+			virtio_cwrite8(vdev,				\
+				       offsetof(structname, member),	\
+				       *(ptr));				\
+			break;						\
+		case 2:							\
+			virtio_cwrite16(vdev,				\
+					offsetof(structname, member),	\
+					*(ptr));			\
+			break;						\
+		case 4:							\
+			virtio_cwrite32(vdev,				\
+					offsetof(structname, member),	\
+					*(ptr));			\
+			break;						\
+		case 8:							\
+			virtio_cwrite64(vdev,				\
+					offsetof(structname, member),	\
+					*(ptr));			\
+			break;						\
+		default:						\
+			WARN_ON(true);					\
+		}							\
+	} while (0)
+
+/* Conditional config space accessors */
+#define virtio_cread_feature(vdev, fbit, structname, member, ptr)	\
+	({								\
+		int _r = 0;						\
+		if (!virtio_has_feature(vdev, fbit))			\
+			_r = -ENOENT;					\
+		else							\
+			virtio_cread(vdev, structname, member, ptr);	\
+		_r;							\
+	})
+
+#endif /* __VIRTIO_H__ */
diff --git a/include/virtio_ring.h b/include/virtio_ring.h
new file mode 100644
index 0000000..6fc0593
--- /dev/null
+++ b/include/virtio_ring.h
@@ -0,0 +1,320 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (C) 2018, Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * From Linux kernel include/uapi/linux/virtio_ring.h
+ */
+
+#ifndef _LINUX_VIRTIO_RING_H
+#define _LINUX_VIRTIO_RING_H
+
+#include <virtio_types.h>
+
+/* This marks a buffer as continuing via the next field */
+#define VRING_DESC_F_NEXT		1
+/* This marks a buffer as write-only (otherwise read-only) */
+#define VRING_DESC_F_WRITE		2
+/* This means the buffer contains a list of buffer descriptors */
+#define VRING_DESC_F_INDIRECT		4
+
+/*
+ * The Host uses this in used->flags to advise the Guest: don't kick me when
+ * you add a buffer. It's unreliable, so it's simply an optimization. Guest
+ * will still kick if it's out of buffers.
+ */
+#define VRING_USED_F_NO_NOTIFY		1
+
+/*
+ * The Guest uses this in avail->flags to advise the Host: don't interrupt me
+ * when you consume a buffer. It's unreliable, so it's simply an optimization.
+ */
+#define VRING_AVAIL_F_NO_INTERRUPT	1
+
+/* We support indirect buffer descriptors */
+#define VIRTIO_RING_F_INDIRECT_DESC	28
+
+/*
+ * The Guest publishes the used index for which it expects an interrupt
+ * at the end of the avail ring. Host should ignore the avail->flags field.
+ *
+ * The Host publishes the avail index for which it expects a kick
+ * at the end of the used ring. Guest should ignore the used->flags field.
+ */
+#define VIRTIO_RING_F_EVENT_IDX		29
+
+/* Virtio ring descriptors: 16 bytes. These can chain together via "next". */
+struct vring_desc {
+	/* Address (guest-physical) */
+	__virtio64 addr;
+	/* Length */
+	__virtio32 len;
+	/* The flags as indicated above */
+	__virtio16 flags;
+	/* We chain unused descriptors via this, too */
+	__virtio16 next;
+};
+
+struct vring_avail {
+	__virtio16 flags;
+	__virtio16 idx;
+	__virtio16 ring[];
+};
+
+struct vring_used_elem {
+	/* Index of start of used descriptor chain */
+	__virtio32 id;
+	/* Total length of the descriptor chain which was used (written to) */
+	__virtio32 len;
+};
+
+struct vring_used {
+	__virtio16 flags;
+	__virtio16 idx;
+	struct vring_used_elem ring[];
+};
+
+struct vring {
+	unsigned int num;
+	struct vring_desc *desc;
+	struct vring_avail *avail;
+	struct vring_used *used;
+};
+
+/**
+ * virtqueue - a queue to register buffers for sending or receiving.
+ *
+ * @list: the chain of virtqueues for this device
+ * @vdev: the virtio device this queue was created for
+ * @index: the zero-based ordinal number for this queue
+ * @num_free: number of elements we expect to be able to fit
+ * @vring: actual memory layout for this queue
+ * @event: host publishes avail event idx
+ * @free_head: head of free buffer list
+ * @num_added: number we've added since last sync
+ * @last_used_idx: last used index we've seen
+ * @avail_flags_shadow: last written value to avail->flags
+ * @avail_idx_shadow: last written value to avail->idx in guest byte order
+ */
+struct virtqueue {
+	struct list_head list;
+	struct udevice *vdev;
+	unsigned int index;
+	unsigned int num_free;
+	struct vring vring;
+	bool event;
+	unsigned int free_head;
+	unsigned int num_added;
+	u16 last_used_idx;
+	u16 avail_flags_shadow;
+	u16 avail_idx_shadow;
+};
+
+/*
+ * Alignment requirements for vring elements.
+ * When using pre-virtio 1.0 layout, these fall out naturally.
+ */
+#define VRING_AVAIL_ALIGN_SIZE		2
+#define VRING_USED_ALIGN_SIZE		4
+#define VRING_DESC_ALIGN_SIZE		16
+
+/*
+ * We publish the used event index at the end of the available ring,
+ * and vice versa. They are at the end for backwards compatibility.
+ */
+#define vring_used_event(vr)	((vr)->avail->ring[(vr)->num])
+#define vring_avail_event(vr)	(*(__virtio16 *)&(vr)->used->ring[(vr)->num])
+
+static inline void vring_init(struct vring *vr, unsigned int num, void *p,
+			      unsigned long align)
+{
+	vr->num = num;
+	vr->desc = p;
+	vr->avail = p + num * sizeof(struct vring_desc);
+	vr->used = (void *)(((uintptr_t)&vr->avail->ring[num] +
+		   sizeof(__virtio16) + align - 1) & ~(align - 1));
+}
+
+static inline unsigned int vring_size(unsigned int num, unsigned long align)
+{
+	return ((sizeof(struct vring_desc) * num +
+		sizeof(__virtio16) * (3 + num)  + align - 1) & ~(align - 1)) +
+		sizeof(__virtio16) * 3 + sizeof(struct vring_used_elem) * num;
+}
+
+/*
+ * The following is used with USED_EVENT_IDX and AVAIL_EVENT_IDX.
+ * Assuming a given event_idx value from the other side, if we have just
+ * incremented index from old to new_idx, should we trigger an event?
+ */
+static inline int vring_need_event(__u16 event_idx, __u16 new_idx, __u16 old)
+{
+	/*
+	 * Note: Xen has similar logic for notification hold-off
+	 * in include/xen/interface/io/ring.h with req_event and req_prod
+	 * corresponding to event_idx + 1 and new_idx respectively.
+	 * Note also that req_event and req_prod in Xen start at 1,
+	 * event indexes in virtio start at 0.
+	 */
+	return (__u16)(new_idx - event_idx - 1) < (__u16)(new_idx - old);
+}
+
+struct virtio_sg;
+
+/**
+ * virtqueue_add - expose buffers to other end
+ *
+ * @vq:		the struct virtqueue we're talking about
+ * @sgs:	array of terminated scatterlists
+ * @out_sgs:	the number of scatterlists readable by other side
+ * @in_sgs:	the number of scatterlists which are writable
+ *		(after readable ones)
+ *
+ * Caller must ensure we don't call this with other virtqueue operations
+ * at the same time (except where noted).
+ *
+ * Returns zero or a negative error (ie. ENOSPC, ENOMEM, EIO).
+ */
+int virtqueue_add(struct virtqueue *vq, struct virtio_sg *sgs[],
+		  unsigned int out_sgs, unsigned int in_sgs);
+
+/**
+ * virtqueue_kick - update after add_buf
+ *
+ * @vq:		the struct virtqueue
+ *
+ * After one or more virtqueue_add() calls, invoke this to kick
+ * the other side.
+ *
+ * Caller must ensure we don't call this with other virtqueue
+ * operations at the same time (except where noted).
+ */
+void virtqueue_kick(struct virtqueue *vq);
+
+/**
+ * virtqueue_get_buf - get the next used buffer
+ *
+ * @vq:		the struct virtqueue we're talking about
+ * @len:	the length written into the buffer
+ *
+ * If the device wrote data into the buffer, @len will be set to the
+ * amount written. This means you don't need to clear the buffer
+ * beforehand to ensure there's no data leakage in the case of short
+ * writes.
+ *
+ * Caller must ensure we don't call this with other virtqueue
+ * operations at the same time (except where noted).
+ *
+ * Returns NULL if there are no used buffers, or the memory buffer
+ * handed to virtqueue_add_*().
+ */
+void *virtqueue_get_buf(struct virtqueue *vq, unsigned int *len);
+
+/**
+ * vring_create_virtqueue - create a virtqueue for a virtio device
+ *
+ * @index:	the index of the queue
+ * @num:	number of elements of the queue
+ * @vring_align:the alignment requirement of the descriptor ring
+ * @udev:	the virtio transport udevice
+ * @return: the virtqueue pointer or NULL if failed
+ *
+ * This creates a virtqueue and allocates the descriptor ring for a virtio
+ * device. The caller should query virtqueue_get_ring_size() to learn the
+ * actual size of the ring.
+ *
+ * This API is supposed to be called by the virtio transport driver in the
+ * virtio find_vqs() uclass method.
+ */
+struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num,
+					 unsigned int vring_align,
+					 struct udevice *udev);
+
+/**
+ * vring_del_virtqueue - destroy a virtqueue
+ *
+ * @vq:		the struct virtqueue we're talking about
+ *
+ * This destroys a virtqueue. If created with vring_create_virtqueue(),
+ * this also frees the descriptor ring.
+ *
+ * This API is supposed to be called by the virtio transport driver in the
+ * virtio del_vqs() uclass method.
+ */
+void vring_del_virtqueue(struct virtqueue *vq);
+
+/**
+ * virtqueue_get_vring_size - get the size of the virtqueue's vring
+ *
+ * @vq:		the struct virtqueue containing the vring of interest
+ * @return: the size of the vring in a virtqueue.
+ */
+unsigned int virtqueue_get_vring_size(struct virtqueue *vq);
+
+/**
+ * virtqueue_get_desc_addr - get the vring descriptor table address
+ *
+ * @vq:		the struct virtqueue containing the vring of interest
+ * @return: the descriptor table address of the vring in a virtqueue.
+ */
+ulong virtqueue_get_desc_addr(struct virtqueue *vq);
+
+/**
+ * virtqueue_get_avail_addr - get the vring available ring address
+ *
+ * @vq:		the struct virtqueue containing the vring of interest
+ * @return: the available ring address of the vring in a virtqueue.
+ */
+ulong virtqueue_get_avail_addr(struct virtqueue *vq);
+
+/**
+ * virtqueue_get_used_addr - get the vring used ring address
+ *
+ * @vq:		the struct virtqueue containing the vring of interest
+ * @return: the used ring address of the vring in a virtqueue.
+ */
+ulong virtqueue_get_used_addr(struct virtqueue *vq);
+
+/**
+ * virtqueue_poll - query pending used buffers
+ *
+ * @vq:			the struct virtqueue we're talking about
+ * @last_used_idx:	virtqueue last used index
+ *
+ * Returns "true" if there are pending used buffers in the queue.
+ */
+bool virtqueue_poll(struct virtqueue *vq, u16 last_used_idx);
+
+/**
+ * virtqueue_dump - dump the virtqueue for debugging
+ *
+ * @vq:		the struct virtqueue we're talking about
+ *
+ * Caller must ensure we don't call this with other virtqueue operations
+ * at the same time (except where noted).
+ */
+void virtqueue_dump(struct virtqueue *vq);
+
+/*
+ * Barriers in virtio are tricky. Since we are not in a hyperviosr/guest
+ * scenario, having these as nops is enough to work as expected.
+ */
+
+static inline void virtio_mb(void)
+{
+}
+
+static inline void virtio_rmb(void)
+{
+}
+
+static inline void virtio_wmb(void)
+{
+}
+
+static inline void virtio_store_mb(__virtio16 *p, __virtio16 v)
+{
+	WRITE_ONCE(*p, v);
+}
+
+#endif /* _LINUX_VIRTIO_RING_H */
diff --git a/include/virtio_types.h b/include/virtio_types.h
new file mode 100644
index 0000000..d700d19
--- /dev/null
+++ b/include/virtio_types.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (C) 2018, Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * From Linux kernel include/uapi/linux/virtio_types.h
+ */
+
+#ifndef _LINUX_VIRTIO_TYPES_H
+#define _LINUX_VIRTIO_TYPES_H
+
+#include <linux/types.h>
+
+/*
+ * __virtio{16,32,64} have the following meaning:
+ * - __u{16,32,64} for virtio devices in legacy mode, accessed in native endian
+ * - __le{16,32,64} for standard-compliant virtio devices
+ */
+
+typedef __u16 __bitwise __virtio16;
+typedef __u32 __bitwise __virtio32;
+typedef __u64 __bitwise __virtio64;
+
+#endif /* _LINUX_VIRTIO_TYPES_H */
diff --git a/include/vsc7385.h b/include/vsc7385.h
new file mode 100644
index 0000000..fceb078
--- /dev/null
+++ b/include/vsc7385.h
@@ -0,0 +1,12 @@
+/*
+ * Header file for vsc7385.c
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.  This file is licensed
+ * under the terms of the GNU General Public License version 2.  This
+ * program is licensed "as is" without any warranty of any kind, whether
+ * express or implied.
+ */
+
+int vsc7385_upload_firmware(void *firmware, unsigned int size);
diff --git a/include/vsc9953.h b/include/vsc9953.h
new file mode 100644
index 0000000..fe072da
--- /dev/null
+++ b/include/vsc9953.h
@@ -0,0 +1,722 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2013, 2015 Freescale Semiconductor, Inc.
+ *
+ * Driver for the Vitesse VSC9953 L2 Switch
+ */
+
+#ifndef _VSC9953_H_
+#define _VSC9953_H_
+
+#include <config.h>
+#include <miiphy.h>
+#include <asm/types.h>
+
+#define VSC9953_OFFSET			(CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
+
+#define VSC9953_SYS_OFFSET		0x010000
+#define VSC9953_REW_OFFSET		0x030000
+#define VSC9953_DEV_GMII_OFFSET		0x100000
+#define VSC9953_QSYS_OFFSET		0x200000
+#define VSC9953_ANA_OFFSET		0x280000
+#define VSC9953_DEVCPU_GCB		0x070000
+#define VSC9953_ES0			0x040000
+#define VSC9953_IS1			0x050000
+#define VSC9953_IS2			0x060000
+
+#define T1040_SWITCH_GMII_DEV_OFFSET	0x010000
+#define VSC9953_PHY_REGS_OFFST		0x0000AC
+
+/* Macros for vsc9953_chip_regs.soft_rst register */
+#define VSC9953_SOFT_SWC_RST_ENA	0x00000001
+
+/* Macros for vsc9953_sys_sys.reset_cfg register */
+#define VSC9953_CORE_ENABLE		0x80
+#define VSC9953_MEM_ENABLE		0x40
+#define VSC9953_MEM_INIT		0x20
+
+/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
+#define VSC9953_MAC_ENA_CFG		0x00000011
+
+/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
+#define VSC9953_MAC_MODE_CFG		0x00000011
+
+/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
+#define VSC9953_MAC_IFG_CFG		0x00000515
+
+/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
+#define VSC9953_MAC_HDX_CFG		0x00001043
+
+/* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
+#define VSC9953_MAC_MAX_LEN		0x000005ee
+
+/* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
+#define VSC9953_CLOCK_CFG		0x00000001
+#define VSC9953_CLOCK_CFG_1000M		0x00000001
+
+/* Macros for vsc9953_sys_sys.front_port_mode register */
+#define VSC9953_FRONT_PORT_MODE	0x00000000
+
+/* Macros for vsc9953_ana_pfc.pfc_cfg register */
+#define VSC9953_PFC_FC			0x00000001
+#define VSC9953_PFC_FC_QSGMII		0x00000000
+
+/* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
+#define VSC9953_MAC_FC_CFG		0x04700000
+#define VSC9953_MAC_FC_CFG_QSGMII	0x00700000
+
+/* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
+#define VSC9953_PAUSE_CFG		0x001ffffe
+
+/* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
+#define VSC9953_TOT_TAIL_DROP_LVL	0x000003ff
+
+/* Macros for vsc9953_sys_sys.stat_cfg register */
+#define VSC9953_STAT_CLEAR_RX		0x00000400
+#define VSC9953_STAT_CLEAR_TX		0x00000800
+#define VSC9953_STAT_CLEAR_DR		0x00001000
+
+/* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
+#define VSC9953_VCAP_MV_CFG		0x0000ffff
+#define VSC9953_VCAP_UPDATE_CTRL	0x01000004
+
+/* Macros for register vsc9953_ana_ana_tables.mac_access register */
+#define VSC9953_MAC_CMD_IDLE		0x00000000
+#define VSC9953_MAC_CMD_LEARN		0x00000001
+#define VSC9953_MAC_CMD_FORGET		0x00000002
+#define VSC9953_MAC_CMD_AGE		0x00000003
+#define VSC9953_MAC_CMD_NEXT		0x00000004
+#define VSC9953_MAC_CMD_READ		0x00000006
+#define VSC9953_MAC_CMD_WRITE		0x00000007
+#define VSC9953_MAC_CMD_MASK		0x00000007
+#define VSC9953_MAC_CMD_VALID		0x00000800
+#define VSC9953_MAC_ENTRYTYPE_NORMAL	0x00000000
+#define VSC9953_MAC_ENTRYTYPE_LOCKED	0x00000200
+#define VSC9953_MAC_ENTRYTYPE_IPV4MCAST	0x00000400
+#define VSC9953_MAC_ENTRYTYPE_IPV6MCAST	0x00000600
+#define VSC9953_MAC_ENTRYTYPE_MASK	0x00000600
+#define VSC9953_MAC_DESTIDX_MASK	0x000001f8
+#define VSC9953_MAC_VID_MASK		0x1fff0000
+#define VSC9953_MAC_MACH_MASK		0x0000ffff
+
+/* Macros for vsc9953_ana_port.vlan_cfg register */
+#define VSC9953_VLAN_CFG_AWARE_ENA	0x00100000
+#define VSC9953_VLAN_CFG_POP_CNT_MASK	0x000c0000
+#define VSC9953_VLAN_CFG_POP_CNT_NONE	0x00000000
+#define VSC9953_VLAN_CFG_POP_CNT_ONE	0x00040000
+#define VSC9953_VLAN_CFG_VID_MASK	0x00000fff
+
+/* Macros for vsc9953_rew_port.port_vlan_cfg register */
+#define VSC9953_PORT_VLAN_CFG_VID_MASK	0x00000fff
+
+/* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
+#define VSC9953_ANA_TBL_VID_MASK	0x00000fff
+
+/* Macros for vsc9953_ana_ana_tables.vlan_access register */
+#define VSC9953_VLAN_PORT_MASK		0x00001ffc
+#define VSC9953_VLAN_CMD_MASK		0x00000003
+#define VSC9953_VLAN_CMD_IDLE		0x00000000
+#define VSC9953_VLAN_CMD_READ		0x00000001
+#define VSC9953_VLAN_CMD_WRITE		0x00000002
+#define VSC9953_VLAN_CMD_INIT		0x00000003
+
+/* Macros for vsc9953_ana_port.port_cfg register */
+#define VSC9953_PORT_CFG_LEARN_ENA	0x00000080
+#define VSC9953_PORT_CFG_LEARN_AUTO	0x00000100
+#define VSC9953_PORT_CFG_LEARN_CPU	0x00000200
+#define VSC9953_PORT_CFG_LEARN_DROP	0x00000400
+#define VSC9953_PORT_CFG_PORTID_MASK	0x0000003c
+
+/* Macros for vsc9953_qsys_sys.switch_port_mode register */
+#define VSC9953_PORT_ENA		0x00002000
+
+/* Macros for vsc9953_ana_ana.agen_ctrl register */
+#define VSC9953_FID_MASK_ALL		0x00fff000
+
+/* Macros for vsc9953_ana_ana.adv_learn register */
+#define VSC9953_VLAN_CHK		0x00000400
+
+/* Macros for vsc9953_ana_ana.auto_age register */
+#define VSC9953_AUTOAGE_PERIOD_MASK	0x001ffffe
+
+/* Macros for vsc9953_rew_port.port_tag_cfg register */
+#define VSC9953_TAG_CFG_MASK		0x00000180
+#define VSC9953_TAG_CFG_NONE		0x00000000
+#define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO	0x00000080
+#define VSC9953_TAG_CFG_ALL_BUT_ZERO		0x00000100
+#define VSC9953_TAG_CFG_ALL		0x00000180
+#define VSC9953_TAG_VID_PVID		0x00000010
+
+/* Macros for vsc9953_ana_ana.anag_efil register */
+#define VSC9953_AGE_PORT_EN		0x00080000
+#define VSC9953_AGE_PORT_MASK		0x0007c000
+#define VSC9953_AGE_VID_EN		0x00002000
+#define VSC9953_AGE_VID_MASK		0x00001fff
+
+/* Macros for vsc9953_ana_ana_tables.mach_data register */
+#define VSC9953_MACHDATA_VID_MASK	0x1fff0000
+
+/* Macros for vsc9953_ana_common.aggr_cfg register */
+#define VSC9953_AC_RND_ENA		0x00000080
+#define VSC9953_AC_DMAC_ENA		0x00000040
+#define VSC9953_AC_SMAC_ENA		0x00000020
+#define VSC9953_AC_IP6_LBL_ENA		0x00000010
+#define VSC9953_AC_IP6_TCPUDP_ENA	0x00000008
+#define VSC9953_AC_IP4_SIPDIP_ENA	0x00000004
+#define VSC9953_AC_IP4_TCPUDP_ENA	0x00000002
+#define VSC9953_AC_MASK			0x000000fe
+
+/* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
+#define VSC9953_PGID_PORT_MASK		0x000003ff
+
+#define VSC9953_MAX_PORTS		10
+#define VSC9953_PORT_CHECK(port)	\
+	(((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
+#define VSC9953_INTERNAL_PORT_CHECK(port) ( \
+	( \
+		(port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
+	) ? 0 : 1 \
+)
+#define VSC9953_MAX_VLAN		4096
+#define VSC9953_VLAN_CHECK(vid)	\
+	(((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
+#define VSC9953_DEFAULT_AGE_TIME	300
+
+#define DEFAULT_VSC9953_MDIO_NAME	"VSC9953_MDIO0"
+
+#define MIIMIND_OPR_PEND		0x00000004
+
+#define VSC9953_BITMASK(offset)		((BIT(offset)) - 1)
+#define VSC9953_ENC_BITFIELD(target, offset, width) \
+	(((target) & VSC9953_BITMASK(width)) << (offset))
+
+#define VSC9953_IO_ADDR(target, offset)		((target) + (offset << 2))
+
+#define VSC9953_IO_REG(target, offset)	(VSC9953_IO_ADDR(target, offset))
+#define VSC9953_VCAP_CACHE_ENTRY_DAT(target, ri)  \
+	VSC9953_IO_REG(target, (0x2 + (ri)))
+
+#define VSC9953_VCAP_CACHE_MASK_DAT(target, ri) \
+	VSC9953_IO_REG(target, (0x42 + (ri)))
+
+#define VSC9953_VCAP_CACHE_TG_DAT(target)	VSC9953_IO_REG(target, 0xe2)
+#define VSC9953_VCAP_CFG_MV_CFG(target)	VSC9953_IO_REG(target, 0x1)
+#define VSC9953_VCAP_CFG_MV_CFG_SIZE(target) \
+	VSC9953_ENC_BITFIELD(target, 0, 16)
+
+#define VSC9953_VCAP_CFG_UPDATE_CTRL(target)	VSC9953_IO_REG(target, 0x0)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(target) \
+	VSC9953_ENC_BITFIELD(target, 22, 3)
+
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(target) \
+	VSC9953_ENC_BITFIELD(target, 3, 16)
+
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT	BIT(2)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS	BIT(21)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS	BIT(20)
+#define VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS		BIT(19)
+#define VSC9953_VCAP_CACHE_ACTION_DAT(target, ri) \
+	VSC9953_IO_REG(target, (0x82 + (ri)))
+
+#define VSC9953_VCAP_CACHE_CNT_DAT(target, ri)	\
+	VSC9953_IO_REG(target, (0xc2 + (ri)))
+
+#define VSC9953_PORT_OFFSET		1
+#define VSC9953_IS1_CNT			256
+#define VSC9953_IS2_CNT			1024
+#define VSC9953_ES0_CNT			1024
+
+#define BITS_TO_DWORD(in)		(1 + (((in) - 1) / 32))
+#define ENTRY_WORDS_ES0		BITS_TO_DWORD(29)
+#define ENTRY_WORDS_IS1		BITS_TO_DWORD(376)
+#define ENTRY_WORDS_IS2		BITS_TO_DWORD(376)
+#define ES0_ACT_WIDTH		BITS_TO_DWORD(91)
+#define ES0_CNT_WIDTH		BITS_TO_DWORD(1)
+#define IS1_ACT_WIDTH		BITS_TO_DWORD(320)
+#define IS1_CNT_WIDTH		BITS_TO_DWORD(4)
+#define IS2_ACT_WIDTH		BITS_TO_DWORD(103 - 2 * VSC9953_PORT_OFFSET)
+#define IS2_CNT_WIDTH		BITS_TO_DWORD(4 * 32)
+#define ES0_ACT_COUNT		(VSC9953_ES0_CNT + VSC9953_MAX_PORTS)
+#define IS1_ACT_COUNT		(VSC9953_IS1_CNT + 1)
+#define IS2_ACT_COUNT		(VSC9953_IS2_CNT + VSC9953_MAX_PORTS + 2)
+
+/* TCAM entries */
+enum tcam_sel {
+	TCAM_SEL_ENTRY   = BIT(0),
+	TCAM_SEL_ACTION  = BIT(1),
+	TCAM_SEL_COUNTER = BIT(2),
+	TCAM_SEL_ALL     = VSC9953_BITMASK(3),
+};
+
+enum tcam_cmd {
+	TCAM_CMD_WRITE      = 0,
+	TCAM_CMD_READ       = 1,
+	TCAM_CMD_MOVE_UP    = 2,
+	TCAM_CMD_MOVE_DOWN  = 3,
+	TCAM_CMD_INITIALIZE = 4,
+};
+
+struct vsc9953_mdio_info {
+	struct vsc9953_mii_mng	*regs;
+	char	*name;
+};
+
+/* VSC9953 ANA structure */
+
+struct vsc9953_ana_port {
+	u32	vlan_cfg;
+	u32	drop_cfg;
+	u32	qos_cfg;
+	u32	vcap_cfg;
+	u32	vcap_s1_key_cfg[3];
+	u32	vcap_s2_cfg;
+	u32	qos_pcp_dei_map_cfg[16];
+	u32	cpu_fwd_cfg;
+	u32	cpu_fwd_bpdu_cfg;
+	u32	cpu_fwd_garp_cfg;
+	u32	cpu_fwd_ccm_cfg;
+	u32	port_cfg;
+	u32	pol_cfg;
+	u32	reserved[34];
+};
+
+struct vsc9953_ana_pol {
+	u32	pol_pir_cfg;
+	u32	pol_cir_cfg;
+	u32	pol_mode_cfg;
+	u32	pol_pir_state;
+	u32	pol_cir_state;
+	u32	reserved1[3];
+};
+
+struct vsc9953_ana_ana_tables {
+	u32	entry_lim[11];
+	u32	an_moved;
+	u32	mach_data;
+	u32	macl_data;
+	u32	mac_access;
+	u32	mact_indx;
+	u32	vlan_access;
+	u32	vlan_tidx;
+};
+
+struct vsc9953_ana_ana {
+	u32	adv_learn;
+	u32	vlan_mask;
+	u32	reserved;
+	u32	anag_efil;
+	u32	an_events;
+	u32	storm_limit_burst;
+	u32	storm_limit_cfg[4];
+	u32	isolated_prts;
+	u32	community_ports;
+	u32	auto_age;
+	u32	mac_options;
+	u32	learn_disc;
+	u32	agen_ctrl;
+	u32	mirror_ports;
+	u32	emirror_ports;
+	u32	flooding;
+	u32	flooding_ipmc;
+	u32	sflow_cfg[11];
+	u32	port_mode[12];
+};
+
+#define PGID_DST_START		0
+#define PGID_AGGR_START		64
+#define PGID_SRC_START		80
+
+struct vsc9953_ana_pgid {
+	u32	port_grp_id[91];
+};
+
+struct vsc9953_ana_pfc {
+	u32	pfc_cfg;
+	u32	reserved1[15];
+};
+
+struct vsc9953_ana_pol_misc {
+	u32	pol_flowc[10];
+	u32	reserved1[17];
+	u32	pol_hyst;
+};
+
+struct vsc9953_ana_common {
+	u32	aggr_cfg;
+	u32	cpuq_cfg;
+	u32	cpuq_8021_cfg;
+	u32	dscp_cfg;
+	u32	dscp_rewr_cfg;
+	u32	vcap_rng_type_cfg;
+	u32	vcap_rng_val_cfg;
+	u32	discard_cfg;
+	u32	fid_cfg;
+};
+
+struct vsc9953_analyzer {
+	struct vsc9953_ana_port	port[11];
+	u32	reserved1[9536];
+	struct vsc9953_ana_pol	pol[164];
+	struct vsc9953_ana_ana_tables	ana_tables;
+	u32	reserved2[14];
+	struct vsc9953_ana_ana	ana;
+	u32	reserved3[21];
+	struct vsc9953_ana_pgid	port_id_tbl;
+	u32	reserved4[549];
+	struct vsc9953_ana_pfc	pfc[10];
+	struct vsc9953_ana_pol_misc	pol_misc;
+	u32	reserved5[196];
+	struct vsc9953_ana_common	common;
+};
+/* END VSC9953 ANA structure t*/
+
+/* VSC9953 DEV_GMII structure */
+
+struct vsc9953_dev_gmii_port_mode {
+	u32	clock_cfg;
+	u32	port_misc;
+	u32	reserved1;
+	u32	eee_cfg;
+};
+
+struct vsc9953_dev_gmii_mac_cfg_status {
+	u32	mac_ena_cfg;
+	u32	mac_mode_cfg;
+	u32	mac_maxlen_cfg;
+	u32	mac_tags_cfg;
+	u32	mac_adv_chk_cfg;
+	u32	mac_ifg_cfg;
+	u32	mac_hdx_cfg;
+	u32	mac_fc_mac_low_cfg;
+	u32	mac_fc_mac_high_cfg;
+	u32	mac_sticky;
+};
+
+struct vsc9953_dev_gmii {
+	struct vsc9953_dev_gmii_port_mode	port_mode;
+	struct vsc9953_dev_gmii_mac_cfg_status	mac_cfg_status;
+};
+
+/* END VSC9953 DEV_GMII structure */
+
+/* VSC9953 QSYS structure */
+
+struct vsc9953_qsys_hsch {
+	u32	cir_cfg;
+	u32	reserved1;
+	u32	se_cfg;
+	u32	se_dwrr_cfg[8];
+	u32	cir_state;
+	u32	reserved2[20];
+};
+
+struct vsc9953_qsys_sys {
+	u32	port_mode[12];
+	u32	switch_port_mode[11];
+	u32	stat_cnt_cfg;
+	u32	eee_cfg[10];
+	u32	eee_thrs;
+	u32	igr_no_sharing;
+	u32	egr_no_sharing;
+	u32	sw_status[11];
+	u32	ext_cpu_cfg;
+	u32	cpu_group_map;
+	u32	reserved1[23];
+};
+
+struct vsc9953_qsys_qos_cfg {
+	u32	red_profile[16];
+	u32	res_qos_mode;
+};
+
+struct vsc9953_qsys_drop_cfg {
+	u32	egr_drop_mode;
+};
+
+struct vsc9953_qsys_mmgt {
+	u32	eq_cntrl;
+	u32	reserved1;
+};
+
+struct vsc9953_qsys_hsch_misc {
+	u32	hsch_misc_cfg;
+	u32	reserved1[546];
+};
+
+struct vsc9953_qsys_res_ctrl {
+	u32	res_cfg;
+	u32	res_stat;
+
+};
+
+struct vsc9953_qsys_reg {
+	struct vsc9953_qsys_hsch	hsch[108];
+	struct vsc9953_qsys_sys	sys;
+	struct vsc9953_qsys_qos_cfg	qos_cfg;
+	struct vsc9953_qsys_drop_cfg	drop_cfg;
+	struct vsc9953_qsys_mmgt	mmgt;
+	struct vsc9953_qsys_hsch_misc	hsch_misc;
+	struct vsc9953_qsys_res_ctrl	res_ctrl[1024];
+};
+
+/* END VSC9953 QSYS structure */
+
+/* VSC9953 SYS structure */
+
+struct vsc9953_rx_cntrs {
+	u32	c_rx_oct;
+	u32	c_rx_uc;
+	u32	c_rx_mc;
+	u32	c_rx_bc;
+	u32	c_rx_short;
+	u32	c_rx_frag;
+	u32	c_rx_jabber;
+	u32	c_rx_crc;
+	u32	c_rx_symbol_err;
+	u32	c_rx_sz_64;
+	u32	c_rx_sz_65_127;
+	u32	c_rx_sz_128_255;
+	u32	c_rx_sz_256_511;
+	u32	c_rx_sz_512_1023;
+	u32	c_rx_sz_1024_1526;
+	u32	c_rx_sz_jumbo;
+	u32	c_rx_pause;
+	u32	c_rx_control;
+	u32	c_rx_long;
+	u32	c_rx_cat_drop;
+	u32	c_rx_red_prio_0;
+	u32	c_rx_red_prio_1;
+	u32	c_rx_red_prio_2;
+	u32	c_rx_red_prio_3;
+	u32	c_rx_red_prio_4;
+	u32	c_rx_red_prio_5;
+	u32	c_rx_red_prio_6;
+	u32	c_rx_red_prio_7;
+	u32	c_rx_yellow_prio_0;
+	u32	c_rx_yellow_prio_1;
+	u32	c_rx_yellow_prio_2;
+	u32	c_rx_yellow_prio_3;
+	u32	c_rx_yellow_prio_4;
+	u32	c_rx_yellow_prio_5;
+	u32	c_rx_yellow_prio_6;
+	u32	c_rx_yellow_prio_7;
+	u32	c_rx_green_prio_0;
+	u32	c_rx_green_prio_1;
+	u32	c_rx_green_prio_2;
+	u32	c_rx_green_prio_3;
+	u32	c_rx_green_prio_4;
+	u32	c_rx_green_prio_5;
+	u32	c_rx_green_prio_6;
+	u32	c_rx_green_prio_7;
+	u32	reserved[20];
+};
+
+struct vsc9953_tx_cntrs {
+	u32	c_tx_oct;
+	u32	c_tx_uc;
+	u32	c_tx_mc;
+	u32	c_tx_bc;
+	u32	c_tx_col;
+	u32	c_tx_drop;
+	u32	c_tx_pause;
+	u32	c_tx_sz_64;
+	u32	c_tx_sz_65_127;
+	u32	c_tx_sz_128_255;
+	u32	c_tx_sz_256_511;
+	u32	c_tx_sz_512_1023;
+	u32	c_tx_sz_1024_1526;
+	u32	c_tx_sz_jumbo;
+	u32	c_tx_yellow_prio_0;
+	u32	c_tx_yellow_prio_1;
+	u32	c_tx_yellow_prio_2;
+	u32	c_tx_yellow_prio_3;
+	u32	c_tx_yellow_prio_4;
+	u32	c_tx_yellow_prio_5;
+	u32	c_tx_yellow_prio_6;
+	u32	c_tx_yellow_prio_7;
+	u32	c_tx_green_prio_0;
+	u32	c_tx_green_prio_1;
+	u32	c_tx_green_prio_2;
+	u32	c_tx_green_prio_3;
+	u32	c_tx_green_prio_4;
+	u32	c_tx_green_prio_5;
+	u32	c_tx_green_prio_6;
+	u32	c_tx_green_prio_7;
+	u32	c_tx_aged;
+	u32	reserved[33];
+};
+
+struct vsc9953_drop_cntrs {
+	u32	c_dr_local;
+	u32	c_dr_tail;
+	u32	c_dr_yellow_prio_0;
+	u32	c_dr_yellow_prio_1;
+	u32	c_dr_yellow_prio_2;
+	u32	c_dr_yellow_prio_3;
+	u32	c_dr_yellow_prio_4;
+	u32	c_dr_yellow_prio_5;
+	u32	c_dr_yellow_prio_6;
+	u32	c_dr_yellow_prio_7;
+	u32	c_dr_green_prio_0;
+	u32	c_dr_green_prio_1;
+	u32	c_dr_green_prio_2;
+	u32	c_dr_green_prio_3;
+	u32	c_dr_green_prio_4;
+	u32	c_dr_green_prio_5;
+	u32	c_dr_green_prio_6;
+	u32	c_dr_green_prio_7;
+	u32	reserved[46];
+};
+
+struct vsc9953_sys_stat {
+	struct vsc9953_rx_cntrs	rx_cntrs;
+	struct vsc9953_tx_cntrs	tx_cntrs;
+	struct vsc9953_drop_cntrs	drop_cntrs;
+	u32	reserved1[6];
+};
+
+struct vsc9953_sys_sys {
+	u32	reset_cfg;
+	u32	reserved1;
+	u32	vlan_etype_cfg;
+	u32	port_mode[12];
+	u32	front_port_mode[10];
+	u32	frame_aging;
+	u32	stat_cfg;
+	u32	reserved2[50];
+};
+
+struct vsc9953_sys_pause_cfg {
+	u32	pause_cfg[11];
+	u32	pause_tot_cfg;
+	u32	tail_drop_level[11];
+	u32	tot_tail_drop_lvl;
+	u32	mac_fc_cfg[10];
+};
+
+struct vsc9953_sys_mmgt {
+	u16	free_cnt;
+};
+
+struct vsc9953_system_reg {
+	struct vsc9953_sys_stat	stat;
+	struct vsc9953_sys_sys	sys;
+	struct vsc9953_sys_pause_cfg	pause_cfg;
+	struct vsc9953_sys_mmgt	mmgt;
+};
+
+/* END VSC9953 SYS structure */
+
+/* VSC9953 REW structure */
+
+struct	vsc9953_rew_port {
+	u32	port_vlan_cfg;
+	u32	port_tag_cfg;
+	u32	port_port_cfg;
+	u32	port_dscp_cfg;
+	u32	port_pcp_dei_qos_map_cfg[16];
+	u32	reserved[12];
+};
+
+struct	vsc9953_rew_common {
+	u32	reserve[4];
+	u32	dscp_remap_dp1_cfg[64];
+	u32	dscp_remap_cfg[64];
+};
+
+struct	vsc9953_rew_reg {
+	struct vsc9953_rew_port	port[12];
+	struct vsc9953_rew_common	common;
+};
+
+/* END VSC9953 REW structure */
+
+/* VSC9953 DEVCPU_GCB structure */
+
+struct vsc9953_chip_regs {
+	u32	chipd_id;
+	u32	gpr;
+	u32	soft_rst;
+};
+
+struct vsc9953_gpio {
+	u32	gpio_out_set[10];
+	u32	gpio_out_clr[10];
+	u32	gpio_out[10];
+	u32	gpio_in[10];
+};
+
+struct vsc9953_mii_mng {
+	u32	miimstatus;
+	u32	reserved1;
+	u32	miimcmd;
+	u32	miimdata;
+	u32	miimcfg;
+	u32	miimscan_0;
+	u32	miimscan_1;
+	u32	miiscan_lst_rslts;
+	u32	miiscan_lst_rslts_valid;
+};
+
+struct vsc9953_mii_read_scan {
+	u32	mii_scan_results_sticky[2];
+};
+
+struct vsc9953_devcpu_gcb {
+	struct vsc9953_chip_regs	chip_regs;
+	struct vsc9953_gpio		gpio;
+	struct vsc9953_mii_mng	mii_mng[2];
+	struct vsc9953_mii_read_scan	mii_read_scan;
+};
+
+/* END VSC9953 DEVCPU_GCB structure */
+
+/* VSC9953 IS* structure */
+
+struct vsc9953_vcap_core_cfg {
+	u32	vcap_update_ctrl;
+	u32	vcap_mv_cfg;
+};
+
+struct vsc9953_vcap {
+	struct vsc9953_vcap_core_cfg	vcap_core_cfg;
+};
+
+/* END VSC9953 IS* structure */
+
+#define VSC9953_PORT_INFO_INITIALIZER(idx) \
+{									\
+	.enabled	= 0,						\
+	.phyaddr	= 0,						\
+	.index		= idx,						\
+	.phy_regs	= NULL,						\
+	.enet_if	= PHY_INTERFACE_MODE_NONE,			\
+	.bus		= NULL,						\
+	.phydev		= NULL,						\
+}
+
+/* Structure to describe a VSC9953 port */
+struct vsc9953_port_info {
+	u8	enabled;
+	u8	phyaddr;
+	int	index;
+	void	*phy_regs;
+	phy_interface_t	enet_if;
+	struct mii_dev	*bus;
+	struct phy_device	*phydev;
+};
+
+/* Structure to describe a VSC9953 switch */
+struct vsc9953_info {
+	struct vsc9953_port_info	port[VSC9953_MAX_PORTS];
+};
+
+void vsc9953_init(bd_t *bis);
+
+void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
+void vsc9953_port_info_set_phy_address(int port_no, int address);
+void vsc9953_port_enable(int port_no);
+void vsc9953_port_disable(int port_no);
+void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
+
+#endif /* _VSC9953_H_ */
diff --git a/include/vsprintf.h b/include/vsprintf.h
new file mode 100644
index 0000000..d1740a3
--- /dev/null
+++ b/include/vsprintf.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ */
+
+#ifndef __VSPRINTF_H
+#define __VSPRINTF_H
+
+#include <stdarg.h>
+#include <linux/types.h>
+
+ulong simple_strtoul(const char *cp, char **endp, unsigned int base);
+
+/**
+ * strict_strtoul - convert a string to an unsigned long strictly
+ * @param cp	The string to be converted
+ * @param base	The number base to use
+ * @param res	The converted result value
+ * @return 0 if conversion is successful and *res is set to the converted
+ * value, otherwise it returns -EINVAL and *res is set to 0.
+ *
+ * strict_strtoul converts a string to an unsigned long only if the
+ * string is really an unsigned long string, any string containing
+ * any invalid char at the tail will be rejected and -EINVAL is returned,
+ * only a newline char at the tail is acceptible because people generally
+ * change a module parameter in the following way:
+ *
+ *      echo 1024 > /sys/module/e1000/parameters/copybreak
+ *
+ * echo will append a newline to the tail.
+ *
+ * simple_strtoul just ignores the successive invalid characters and
+ * return the converted value of prefix part of the string.
+ *
+ * Copied this function from Linux 2.6.38 commit ID:
+ * 521cb40b0c44418a4fd36dc633f575813d59a43d
+ *
+ */
+int strict_strtoul(const char *cp, unsigned int base, unsigned long *res);
+unsigned long long simple_strtoull(const char *cp, char **endp,
+					unsigned int base);
+long simple_strtol(const char *cp, char **endp, unsigned int base);
+
+/**
+ * trailing_strtol() - extract a trailing integer from a string
+ *
+ * Given a string this finds a trailing number on the string and returns it.
+ * For example, "abc123" would return 123.
+ *
+ * @str:	String to exxamine
+ * @return training number if found, else -1
+ */
+long trailing_strtol(const char *str);
+
+/**
+ * trailing_strtoln() - extract a trailing integer from a fixed-length string
+ *
+ * Given a fixed-length string this finds a trailing number on the string
+ * and returns it. For example, "abc123" would return 123. Only the
+ * characters between @str and @end - 1 are examined. If @end is NULL, it is
+ * set to str + strlen(str).
+ *
+ * @str:	String to exxamine
+ * @end:	Pointer to end of string to examine, or NULL to use the
+ *		whole string
+ * @return training number if found, else -1
+ */
+long trailing_strtoln(const char *str, const char *end);
+
+/**
+ * panic() - Print a message and reset/hang
+ *
+ * Prints a message on the console(s) and then resets. If CONFIG_PANIC_HANG is
+ * defined, then it will hang instead of resetting.
+ *
+ * @param fmt:	printf() format string for message, which should not include
+ *		\n, followed by arguments
+ */
+void panic(const char *fmt, ...)
+		__attribute__ ((format (__printf__, 1, 2), noreturn));
+
+/**
+ * panic_str() - Print a message and reset/hang
+ *
+ * Prints a message on the console(s) and then resets. If CONFIG_PANIC_HANG is
+ * defined, then it will hang instead of resetting.
+ *
+ * This function can be used instead of panic() when your board does not
+ * already use printf(), * to keep code size small.
+ *
+ * @param fmt:	string to display, which should not include \n
+ */
+void panic_str(const char *str) __attribute__ ((noreturn));
+
+/**
+ * Format a string and place it in a buffer
+ *
+ * @param buf	The buffer to place the result into
+ * @param fmt	The format string to use
+ * @param ...	Arguments for the format string
+ *
+ * The function returns the number of characters written
+ * into @buf.
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int sprintf(char *buf, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 2, 3)));
+
+/**
+ * Format a string and place it in a buffer (va_list version)
+ *
+ * @param buf	The buffer to place the result into
+ * @param fmt	The format string to use
+ * @param args	Arguments for the format string
+ * @return the number of characters which have been written into
+ * the @buf not including the trailing '\0'.
+ *
+ * If you're not already dealing with a va_list consider using scnprintf().
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int vsprintf(char *buf, const char *fmt, va_list args);
+char *simple_itoa(ulong i);
+
+/**
+ * Format a string and place it in a buffer
+ *
+ * @param buf	The buffer to place the result into
+ * @param size	The size of the buffer, including the trailing null space
+ * @param fmt	The format string to use
+ * @param ...	Arguments for the format string
+ * @return the number of characters which would be
+ * generated for the given input, excluding the trailing null,
+ * as per ISO C99.  If the return is greater than or equal to
+ * @size, the resulting string is truncated.
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int snprintf(char *buf, size_t size, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 3, 4)));
+
+/**
+ * Format a string and place it in a buffer
+ *
+ * @param buf	The buffer to place the result into
+ * @param size	The size of the buffer, including the trailing null space
+ * @param fmt	The format string to use
+ * @param ...	Arguments for the format string
+ *
+ * The return value is the number of characters written into @buf not including
+ * the trailing '\0'. If @size is == 0 the function returns 0.
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int scnprintf(char *buf, size_t size, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 3, 4)));
+
+/**
+ * Format a string and place it in a buffer (base function)
+ *
+ * @param buf	The buffer to place the result into
+ * @param size	The size of the buffer, including the trailing null space
+ * @param fmt	The format string to use
+ * @param args	Arguments for the format string
+ * @return The number characters which would be generated for the given
+ * input, excluding the trailing '\0', as per ISO C99. Note that fewer
+ * characters may be written if this number of characters is >= size.
+ *
+ * This function follows C99 vsnprintf, but has some extensions:
+ * %pS output the name of a text symbol
+ * %pF output the name of a function pointer
+ * %pR output the address range in a struct resource
+ *
+ * The function returns the number of characters which would be
+ * generated for the given input, excluding the trailing '\0',
+ * as per ISO C99.
+ *
+ * Call this function if you are already dealing with a va_list.
+ * You probably want snprintf() instead.
+ */
+int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
+
+/**
+ * Format a string and place it in a buffer (va_list version)
+ *
+ * @param buf	The buffer to place the result into
+ * @param size	The size of the buffer, including the trailing null space
+ * @param fmt	The format string to use
+ * @param args	Arguments for the format string
+ * @return the number of characters which have been written into
+ * the @buf not including the trailing '\0'. If @size is == 0 the function
+ * returns 0.
+ *
+ * If you're not already dealing with a va_list consider using scnprintf().
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int vscnprintf(char *buf, size_t size, const char *fmt, va_list args);
+
+/**
+ * print_grouped_ull() - print a value with digits grouped by ','
+ *
+ * This prints a value with grouped digits, like 12,345,678 to make it easier
+ * to read.
+ *
+ * @val:	Value to print
+ * @digits:	Number of digiits to print
+ */
+void print_grouped_ull(unsigned long long int_val, int digits);
+
+bool str2off(const char *p, loff_t *num);
+bool str2long(const char *p, ulong *num);
+#endif
diff --git a/include/vxworks.h b/include/vxworks.h
new file mode 100644
index 0000000..1a29509
--- /dev/null
+++ b/include/vxworks.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2008
+ * Niklaus Giger, niklaus.giger@member.fsf.org
+ */
+
+#ifndef _VXWORKS_H_
+#define _VXWORKS_H_
+
+#include <efi_api.h>
+
+/*
+ * Physical address of memory base for VxWorks x86
+ * This is LOCAL_MEM_LOCAL_ADRS in the VxWorks kernel configuration.
+ */
+#define VXWORKS_PHYS_MEM_BASE	0x100000
+
+/* x86 bootline offset relative to LOCAL_MEM_LOCAL_ADRS in VxWorks */
+#define X86_BOOT_LINE_OFFSET	0x1200
+
+/*
+ * VxWorks x86 E820 related stuff
+ *
+ * VxWorks on x86 gets E820 information from pre-defined offset @
+ * 0x4a00 and 0x4000. At 0x4a00 it's an information table defined
+ * by VxWorks and the actual E820 table entries starts from 0x4000.
+ * As defined by the BIOS E820 spec, the maximum number of E820 table
+ * entries is 128 and each entry occupies 20 bytes, so it's 128 * 20
+ * = 2560 (0xa00) bytes in total. That's where VxWorks stores some
+ * information that is retrieved from the BIOS E820 call and saved
+ * later for sanity test during the kernel boot-up.
+ */
+#define E820_DATA_OFFSET	0x4000
+#define E820_INFO_OFFSET	0x4a00
+
+/* E820 info signatiure "SMAP" - System MAP */
+#define E820_SIGNATURE	0x534d4150
+
+struct e820_info {
+	u32 sign;	/* "SMAP" signature */
+	u32 x0;		/* don't care, used by VxWorks */
+	u32 x1;		/* don't care, used by VxWorks */
+	u32 x2;		/* don't care, used by VxWorks */
+	u32 addr;	/* last e820 table entry addr */
+	u32 x3;		/* don't care, used by VxWorks */
+	u32 entries;	/* e820 table entry count */
+	u32 error;	/* must be zero */
+};
+
+/*
+ * VxWorks bootloader stores its size at a pre-defined offset @ 0x5004.
+ * Later when VxWorks kernel boots up and system memory information is
+ * retrieved from the E820 table, the bootloader size will be subtracted
+ * from the total system memory size to calculate the size of available
+ * memory for the OS.
+ */
+#define BOOT_IMAGE_SIZE_OFFSET	0x5004
+
+/*
+ * When booting from EFI BIOS, VxWorks bootloader stores the EFI GOP
+ * framebuffer info at a pre-defined offset @ 0x6100. When VxWorks kernel
+ * boots up, its EFI console driver tries to find such a block and if
+ * the signature matches, the framebuffer information will be used to
+ * initialize the driver.
+ *
+ * However it is not necessary to prepare an EFI environment for VxWorks's
+ * EFI console driver to function (eg: EFI loader in U-Boot). If U-Boot has
+ * already initialized the graphics card and set it to a VESA mode that is
+ * compatible with EFI GOP, we can simply prepare such a block for VxWorks.
+ */
+#define EFI_GOP_INFO_OFFSET	0x6100
+
+/* EFI GOP info signatiure */
+#define EFI_GOP_INFO_MAGIC	0xfeedface
+
+struct efi_gop_info {
+	u32 magic;			/* signature */
+	struct efi_gop_mode_info info;	/* EFI GOP mode info structure */
+	phys_addr_t fb_base;		/* framebuffer base address */
+	u32 fb_size;			/* framebuffer size */
+};
+
+int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void boot_prep_vxworks(bootm_headers_t *images);
+void boot_jump_vxworks(bootm_headers_t *images);
+
+#endif
diff --git a/include/w1-eeprom.h b/include/w1-eeprom.h
new file mode 100644
index 0000000..2233736
--- /dev/null
+++ b/include/w1-eeprom.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Copyright (c) 2015 Free Electrons
+ * Copyright (c) 2015 NextThing Co
+ * Copyright (c) 2018 Microchip Technology, Inc.
+ *
+ */
+
+#ifndef __W1_EEPROM_H
+#define __W1_EEPROM_H
+
+struct udevice;
+
+struct w1_eeprom_ops {
+	/*
+	 * Reads a buff from the given EEPROM memory, starting at
+	 * given offset and place the results into the given buffer.
+	 * Should read given count of bytes.
+	 * Should return 0 on success, and normal error.h on error
+	 */
+	int	(*read_buf)(struct udevice *dev, unsigned int offset,
+			    u8 *buf, unsigned int count);
+};
+
+int w1_eeprom_read_buf(struct udevice *dev, unsigned int offset,
+		       u8 *buf, unsigned int count);
+
+int w1_eeprom_dm_init(void);
+
+int w1_eeprom_register_new_device(u64 id);
+
+int w1_eeprom_get_id(struct udevice *dev, u64 *id);
+#endif
diff --git a/include/w1.h b/include/w1.h
new file mode 100644
index 0000000..b958b1c
--- /dev/null
+++ b/include/w1.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Copyright (c) 2015 Free Electrons
+ * Copyright (c) 2015 NextThing Co
+ *
+ */
+
+#ifndef __W1_H
+#define __W1_H
+
+#include <dm.h>
+
+#define W1_FAMILY_DS24B33	0x23
+#define W1_FAMILY_DS2431	0x2d
+#define W1_FAMILY_DS2502	0x09
+#define W1_FAMILY_EEP_SANDBOX	0xfe
+
+struct w1_device {
+	u64	id;
+};
+
+struct w1_ops {
+	u8	(*read_byte)(struct udevice *dev);
+	bool	(*reset)(struct udevice *dev);
+	u8	(*triplet)(struct udevice *dev, bool bdir);
+	void	(*write_byte)(struct udevice *dev, u8 byte);
+};
+
+int w1_get_bus(int busnum, struct udevice **busp);
+u8 w1_get_device_family(struct udevice *dev);
+
+int w1_read_buf(struct udevice *dev, u8 *buf, unsigned int count);
+int w1_read_byte(struct udevice *dev);
+int w1_reset_select(struct udevice *dev);
+int w1_write_buf(struct udevice *dev, u8 *buf, unsigned int count);
+int w1_write_byte(struct udevice *dev, u8 byte);
+
+#endif
diff --git a/include/w83c553f.h b/include/w83c553f.h
new file mode 100644
index 0000000..2403e34
--- /dev/null
+++ b/include/w83c553f.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ */
+
+ /* winbond access routines and defines*/
+
+/* from the winbond data sheet -
+ The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
+ Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
+*/
+
+/*ISA bridge configuration space*/
+
+#define W83C553F_VID		0x10AD
+#define W83C553F_DID		0x0565
+
+#define WINBOND_PCICONTR	0x40  /*pci control reg*/
+#define WINBOND_SGBAR		0x41  /*scatter/gather base address reg*/
+#define WINBOND_LBCR		0x42  /*Line Buffer Control reg*/
+#define WINBOND_IDEIRCR		0x43  /*IDE Interrupt Routing Control  Reg*/
+#define WINBOND_PCIIRCR		0x44  /*PCI Interrupt Routing Control Reg*/
+#define WINBOND_BTBAR		0x46  /*BIOS Timer Base Address Register*/
+#define WINBOND_IPADCR		0x48  /*ISA to PCI Address Decoder Control Register*/
+#define WINBOND_IRADCR		0x49  /*ISA ROM Address Decoder Control Register*/
+#define WINBOND_IPMHSAR		0x4a  /*ISA to PCI Memory Hole STart Address Register*/
+#define WINBOND_IPMHSR		0x4b  /*ISA to PCI Memory Hols Size Register*/
+#define WINBOND_CDR			0x4c  /*Clock Divisor Register*/
+#define WINBOND_CSCR		0x4d  /*Chip Select Control Register*/
+#define WINBOND_ATSCR		0x4e  /*AT System Control register*/
+#define WINBOND_ATBCR		0x4f  /*AT Bus ControL Register*/
+#define WINBOND_IRQBEE0R	0x60  /*IRQ Break Event Enable 0 Register*/
+#define WINBOND_IRQBEE1R	0x61  /*IRQ Break Event Enable 1 Register*/
+#define WINBOND_ABEER		0x62  /*Additional Break Event Enable Register*/
+#define WINBOND_DMABEER		0x63  /*DMA Break Event Enable Register*/
+
+#define WINDOND_IDECSR		0x40  /*IDE Control/Status Register, Function 1*/
+
+#define IPADCR_MBE512		0x1
+#define IPADCR_MBE640		0x2
+#define IPADCR_IPATOM4		0x10
+#define IPADCR_IPATOM5		0x20
+#define IPADCR_IPATOM6		0x40
+#define IPADCR_IPATOM7		0x80
+
+#define CSCR_UBIOSCSE		0x10
+#define CSCR_BIOSWP			0x20
+
+#define IDECSR_P0EN			0x01
+#define IDECSR_P0F16		0x02
+#define IDECSR_P1EN			0x10
+#define IDECSR_P1F16		0x20
+#define IDECSR_LEGIRQ		0x800
+
+/*
+ * Interrupt controller
+ */
+#define W83C553F_PIC1_ICW1	CONFIG_SYS_ISA_IO + 0x20
+#define W83C553F_PIC1_ICW2	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_ICW3	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_ICW4	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_OCW1	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_OCW2	CONFIG_SYS_ISA_IO + 0x20
+#define W83C553F_PIC1_OCW3	CONFIG_SYS_ISA_IO + 0x20
+#define W83C553F_PIC1_ELC	CONFIG_SYS_ISA_IO + 0x4D0
+#define W83C553F_PIC2_ICW1	CONFIG_SYS_ISA_IO + 0xA0
+#define W83C553F_PIC2_ICW2	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_ICW3	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_ICW4	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_OCW1	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_OCW2	CONFIG_SYS_ISA_IO + 0xA0
+#define W83C553F_PIC2_OCW3	CONFIG_SYS_ISA_IO + 0xA0
+#define W83C553F_PIC2_ELC	CONFIG_SYS_ISA_IO + 0x4D1
+
+#define W83C553F_TMR1_CMOD	CONFIG_SYS_ISA_IO + 0x43
+
+/*
+ * DMA controller
+ */
+#define W83C553F_DMA1	CONFIG_SYS_ISA_IO + 0x000	/* channel 0 - 3 */
+#define W83C553F_DMA2	CONFIG_SYS_ISA_IO + 0x0C0	/* channel 4 - 7 */
+
+/* command/status register bit definitions */
+
+#define W83C553F_CS_COM_DACKAL	(1<<7)	/* DACK# assert level */
+#define W83C553F_CS_COM_DREQSAL	(1<<6)	/* DREQ sense assert level */
+#define W83C553F_CS_COM_GAP	(1<<4)	/* group arbitration priority */
+#define W83C553F_CS_COM_CGE	(1<<2)	/* channel group enable */
+
+#define W83C553F_CS_STAT_CH0REQ	(1<<4)	/* channel 0 (4) DREQ status */
+#define W83C553F_CS_STAT_CH1REQ	(1<<5)	/* channel 1 (5) DREQ status */
+#define W83C553F_CS_STAT_CH2REQ	(1<<6)	/* channel 2 (6) DREQ status */
+#define W83C553F_CS_STAT_CH3REQ	(1<<7)	/* channel 3 (7) DREQ status */
+
+#define W83C553F_CS_STAT_CH0TC	(1<<0)	/* channel 0 (4) TC status */
+#define W83C553F_CS_STAT_CH1TC	(1<<1)	/* channel 1 (5) TC status */
+#define W83C553F_CS_STAT_CH2TC	(1<<2)	/* channel 2 (6) TC status */
+#define W83C553F_CS_STAT_CH3TC	(1<<3)	/* channel 3 (7) TC status */
+
+/* mode register bit definitions */
+
+#define W83C553F_MODE_TM_DEMAND	(0<<6)	/* transfer mode - demand */
+#define W83C553F_MODE_TM_SINGLE	(1<<6)	/* transfer mode - single */
+#define W83C553F_MODE_TM_BLOCK	(2<<6)	/* transfer mode - block */
+#define W83C553F_MODE_TM_CASCADE	(3<<6)	/* transfer mode - cascade */
+#define W83C553F_MODE_ADDRDEC	(1<<5)	/* address increment/decrement select */
+#define W83C553F_MODE_AUTOINIT	(1<<4)	/* autoinitialize enable */
+#define W83C553F_MODE_TT_VERIFY	(0<<2)	/* transfer type - verify */
+#define W83C553F_MODE_TT_WRITE	(1<<2)	/* transfer type - write */
+#define W83C553F_MODE_TT_READ	(2<<2)	/* transfer type - read */
+#define W83C553F_MODE_TT_ILLEGAL	(3<<2)	/* transfer type - illegal */
+#define W83C553F_MODE_CH0SEL	(0<<0)	/* channel 0 (4) select */
+#define W83C553F_MODE_CH1SEL	(1<<0)	/* channel 1 (5) select */
+#define W83C553F_MODE_CH2SEL	(2<<0)	/* channel 2 (6) select */
+#define W83C553F_MODE_CH3SEL	(3<<0)	/* channel 3 (7) select */
+
+/* request register bit definitions */
+
+#define W83C553F_REQ_CHSERREQ	(1<<2)	/* channel service request */
+#define W83C553F_REQ_CH0SEL	(0<<0)	/* channel 0 (4) select */
+#define W83C553F_REQ_CH1SEL	(1<<0)	/* channel 1 (5) select */
+#define W83C553F_REQ_CH2SEL	(2<<0)	/* channel 2 (6) select */
+#define W83C553F_REQ_CH3SEL	(3<<0)	/* channel 3 (7) select */
+
+/* write single mask bit register bit definitions */
+
+#define W83C553F_WSMB_CHMASKSEL	(1<<2)	/* channel mask select */
+#define W83C553F_WSMB_CH0SEL	(0<<0)	/* channel 0 (4) select */
+#define W83C553F_WSMB_CH1SEL	(1<<0)	/* channel 1 (5) select */
+#define W83C553F_WSMB_CH2SEL	(2<<0)	/* channel 2 (6) select */
+#define W83C553F_WSMB_CH3SEL	(3<<0)	/* channel 3 (7) select */
+
+/* read/write all mask bits register bit definitions */
+
+#define W83C553F_RWAMB_CH0MASK	(1<<0)	/* channel 0 (4) mask */
+#define W83C553F_RWAMB_CH1MASK	(1<<1)	/* channel 1 (5) mask */
+#define W83C553F_RWAMB_CH2MASK	(1<<2)	/* channel 2 (6) mask */
+#define W83C553F_RWAMB_CH3MASK	(1<<3)	/* channel 3 (7) mask */
+
+/* typedefs */
+
+#define W83C553F_DMA1_CS		0x8
+#define W83C553F_DMA1_WR		0x9
+#define W83C553F_DMA1_WSMB		0xA
+#define W83C553F_DMA1_WM		0xB
+#define W83C553F_DMA1_CBP		0xC
+#define W83C553F_DMA1_MC		0xD
+#define W83C553F_DMA1_CM		0xE
+#define W83C553F_DMA1_RWAMB		0xF
+
+#define W83C553F_DMA2_CS		0x10
+#define W83C553F_DMA2_WR		0x12
+#define W83C553F_DMA2_WSMB		0x14
+#define W83C553F_DMA2_WM		0x16
+#define W83C553F_DMA2_CBP		0x18
+#define W83C553F_DMA2_MC		0x1A
+#define W83C553F_DMA2_CM		0x1C
+#define W83C553F_DMA2_RWAMB		0x1E
+
+void initialise_w83c553f(void);
diff --git a/include/wait_bit.h b/include/wait_bit.h
new file mode 100644
index 0000000..79da081
--- /dev/null
+++ b/include/wait_bit.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Wait for bit with timeout and ctrlc
+ *
+ * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ */
+
+#ifndef __WAIT_BIT_H
+#define __WAIT_BIT_H
+
+#include <common.h>
+#include <console.h>
+#include <watchdog.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+
+/**
+ * wait_for_bit_x()	waits for bit set/cleared in register
+ *
+ * Function polls register waiting for specific bit(s) change
+ * (either 0->1 or 1->0). It can fail under two conditions:
+ * - Timeout
+ * - User interaction (CTRL-C)
+ * Function succeeds only if all bits of masked register are set/cleared
+ * (depending on set option).
+ *
+ * @param reg		Register that will be read (using read_x())
+ * @param mask		Bit(s) of register that must be active
+ * @param set		Selects wait condition (bit set or clear)
+ * @param timeout_ms	Timeout (in milliseconds)
+ * @param breakable	Enables CTRL-C interruption
+ * @return		0 on success, -ETIMEDOUT or -EINTR on failure
+ */
+
+#define BUILD_WAIT_FOR_BIT(sfx, type, read)				\
+									\
+static inline int wait_for_bit_##sfx(const void *reg,			\
+				     const type mask,			\
+				     const bool set,			\
+				     const unsigned int timeout_ms,	\
+				     const bool breakable)		\
+{									\
+	type val;							\
+	unsigned long start = get_timer(0);				\
+									\
+	while (1) {							\
+		val = read(reg);					\
+									\
+		if (!set)						\
+			val = ~val;					\
+									\
+		if ((val & mask) == mask)				\
+			return 0;					\
+									\
+		if (get_timer(start) > timeout_ms)			\
+			break;						\
+									\
+		if (breakable && ctrlc()) {				\
+			puts("Abort\n");				\
+			return -EINTR;					\
+		}							\
+									\
+		udelay(1);						\
+		WATCHDOG_RESET();					\
+	}								\
+									\
+	debug("%s: Timeout (reg=%p mask=%x wait_set=%i)\n", __func__,	\
+	      reg, mask, set);						\
+									\
+	return -ETIMEDOUT;						\
+}
+
+BUILD_WAIT_FOR_BIT(8, u8, readb)
+BUILD_WAIT_FOR_BIT(le16, u16, readw)
+BUILD_WAIT_FOR_BIT(16, u16, readw)
+#ifdef readw_be
+BUILD_WAIT_FOR_BIT(be16, u16, readw_be)
+#endif
+BUILD_WAIT_FOR_BIT(le32, u32, readl)
+BUILD_WAIT_FOR_BIT(32, u32, readl)
+#ifdef readl_be
+BUILD_WAIT_FOR_BIT(be32, u32, readl_be)
+#endif
+
+#endif
diff --git a/include/watchdog.h b/include/watchdog.h
new file mode 100644
index 0000000..a4a4e8e
--- /dev/null
+++ b/include/watchdog.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2001
+ * Erik Theisen,  Wave 7 Optics, etheisen@mindspring.com.
+ */
+
+/*
+ * Watchdog functions and macros.
+ */
+#ifndef _WATCHDOG_H_
+#define _WATCHDOG_H_
+
+#if !defined(__ASSEMBLY__)
+/*
+ * Reset the watchdog timer, always returns 0
+ *
+ * This function is here since it is shared between board_f() and board_r(),
+ * and the legacy arch/<arch>/board.c code.
+ */
+int init_func_watchdog_reset(void);
+#endif
+
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
+#define INIT_FUNC_WATCHDOG_INIT	init_func_watchdog_init,
+#define INIT_FUNC_WATCHDOG_RESET	init_func_watchdog_reset,
+#else
+#define INIT_FUNC_WATCHDOG_INIT
+#define INIT_FUNC_WATCHDOG_RESET
+#endif
+
+#if defined(CONFIG_HW_WATCHDOG) && defined(CONFIG_WATCHDOG)
+#  error "Configuration error: CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG can't be used together."
+#endif
+
+/*
+ * Hardware watchdog
+ */
+#ifdef CONFIG_HW_WATCHDOG
+	#if defined(__ASSEMBLY__)
+		#define WATCHDOG_RESET bl hw_watchdog_reset
+	#else
+		extern void hw_watchdog_reset(void);
+
+		#define WATCHDOG_RESET hw_watchdog_reset
+	#endif /* __ASSEMBLY__ */
+#else
+	/*
+	 * Maybe a software watchdog?
+	 */
+	#if defined(CONFIG_WATCHDOG)
+		#if defined(__ASSEMBLY__)
+			#define WATCHDOG_RESET bl watchdog_reset
+		#else
+			/* Don't require the watchdog to be enabled in SPL */
+			#if defined(CONFIG_SPL_BUILD) &&		\
+				!defined(CONFIG_SPL_WATCHDOG_SUPPORT)
+				#define WATCHDOG_RESET() {}
+			#else
+				extern void watchdog_reset(void);
+
+				#define WATCHDOG_RESET watchdog_reset
+			#endif
+		#endif
+	#else
+		/*
+		 * No hardware or software watchdog.
+		 */
+		#if defined(__ASSEMBLY__)
+			#define WATCHDOG_RESET /*XXX DO_NOT_DEL_THIS_COMMENT*/
+		#else
+			#define WATCHDOG_RESET() {}
+		#endif /* __ASSEMBLY__ */
+	#endif /* CONFIG_WATCHDOG && !__ASSEMBLY__ */
+#endif /* CONFIG_HW_WATCHDOG */
+
+/*
+ * Prototypes from $(CPU)/cpu.c.
+ */
+
+#if (defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)) && !defined(__ASSEMBLY__)
+	void hw_watchdog_init(void);
+#endif
+
+#if defined(CONFIG_MPC85xx) && !defined(__ASSEMBLY__)
+	void init_85xx_watchdog(void);
+#endif
+#endif /* _WATCHDOG_H_ */
diff --git a/include/wdt.h b/include/wdt.h
new file mode 100644
index 0000000..5bcff24
--- /dev/null
+++ b/include/wdt.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 Google, Inc
+ */
+
+#ifndef _WDT_H_
+#define _WDT_H_
+
+#include <dm.h>
+#include <dm/read.h>
+
+/*
+ * Implement a simple watchdog uclass. Watchdog is basically a timer that
+ * is used to detect or recover from malfunction. During normal operation
+ * the watchdog would be regularly reset to prevent it from timing out.
+ * If, due to a hardware fault or program error, the computer fails to reset
+ * the watchdog, the timer will elapse and generate a timeout signal.
+ * The timeout signal is used to initiate corrective action or actions,
+ * which typically include placing the system in a safe, known state.
+ */
+
+/*
+ * Start the timer
+ *
+ * @dev: WDT Device
+ * @timeout_ms: Number of ticks (milliseconds) before timer expires
+ * @flags: Driver specific flags. This might be used to specify
+ * which action needs to be executed when the timer expires
+ * @return: 0 if OK, -ve on error
+ */
+int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags);
+
+/*
+ * Stop the timer, thus disabling the Watchdog. Use wdt_start to start it again.
+ *
+ * @dev: WDT Device
+ * @return: 0 if OK, -ve on error
+ */
+int wdt_stop(struct udevice *dev);
+
+/*
+ * Reset the timer, typically restoring the counter to
+ * the value configured by start()
+ *
+ * @dev: WDT Device
+ * @return: 0 if OK, -ve on error
+ */
+int wdt_reset(struct udevice *dev);
+
+/*
+ * Expire the timer, thus executing its action immediately.
+ * This is typically used to reset the board or peripherals.
+ *
+ * @dev: WDT Device
+ * @flags: Driver specific flags
+ * @return 0 if OK -ve on error. If wdt action is system reset,
+ * this function may never return.
+ */
+int wdt_expire_now(struct udevice *dev, ulong flags);
+
+/*
+ * struct wdt_ops - Driver model wdt operations
+ *
+ * The uclass interface is implemented by all wdt devices which use
+ * driver model.
+ */
+struct wdt_ops {
+	/*
+	 * Start the timer
+	 *
+	 * @dev: WDT Device
+	 * @timeout_ms: Number of ticks (milliseconds) before the timer expires
+	 * @flags: Driver specific flags. This might be used to specify
+	 * which action needs to be executed when the timer expires
+	 * @return: 0 if OK, -ve on error
+	 */
+	int (*start)(struct udevice *dev, u64 timeout_ms, ulong flags);
+	/*
+	 * Stop the timer
+	 *
+	 * @dev: WDT Device
+	 * @return: 0 if OK, -ve on error
+	 */
+	int (*stop)(struct udevice *dev);
+	/*
+	 * Reset the timer, typically restoring the counter to
+	 * the value configured by start()
+	 *
+	 * @dev: WDT Device
+	 * @return: 0 if OK, -ve on error
+	 */
+	int (*reset)(struct udevice *dev);
+	/*
+	 * Expire the timer, thus executing the action immediately (optional)
+	 *
+	 * If this function is not provided, a default implementation
+	 * will be used, which sets the counter to 1
+	 * and waits forever. This is good enough for system level
+	 * reset, where the function is not expected to return, but might not be
+	 * good enough for other use cases.
+	 *
+	 * @dev: WDT Device
+	 * @flags: Driver specific flags
+	 * @return 0 if OK -ve on error. May not return.
+	 */
+	int (*expire_now)(struct udevice *dev, ulong flags);
+};
+
+#if CONFIG_IS_ENABLED(WDT)
+#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS	(60 * 1000)
+#endif
+#define WATCHDOG_TIMEOUT_SECS	(CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000)
+
+static inline int initr_watchdog(void)
+{
+	u32 timeout = WATCHDOG_TIMEOUT_SECS;
+
+	/*
+	 * Init watchdog: This will call the probe function of the
+	 * watchdog driver, enabling the use of the device
+	 */
+	if (uclass_get_device_by_seq(UCLASS_WDT, 0,
+				     (struct udevice **)&gd->watchdog_dev)) {
+		debug("WDT:   Not found by seq!\n");
+		if (uclass_get_device(UCLASS_WDT, 0,
+				      (struct udevice **)&gd->watchdog_dev)) {
+			printf("WDT:   Not found!\n");
+			return 0;
+		}
+	}
+
+	if (CONFIG_IS_ENABLED(OF_CONTROL)) {
+		timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec",
+					       WATCHDOG_TIMEOUT_SECS);
+	}
+
+	wdt_start(gd->watchdog_dev, timeout * 1000, 0);
+	gd->flags |= GD_FLG_WDT_READY;
+	printf("WDT:   Started with%s servicing (%ds timeout)\n",
+	       IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", timeout);
+
+	return 0;
+}
+#endif
+
+#endif  /* _WDT_H_ */
diff --git a/include/winbond_w83627.h b/include/winbond_w83627.h
new file mode 100644
index 0000000..a58d816
--- /dev/null
+++ b/include/winbond_w83627.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ */
+
+#ifndef _WINBOND_W83627_H_
+#define _WINBOND_W83627_H_
+
+/* I/O address of Winbond Super IO chip */
+#define WINBOND_IO_PORT		0x2e
+
+/* Logical device number */
+#define W83627DHG_FDC		0	/* Floppy */
+#define W83627DHG_PP		1	/* Parallel port */
+#define W83627DHG_SP1		2	/* Com1 */
+#define W83627DHG_SP2		3	/* Com2 */
+#define W83627DHG_KBC		5	/* PS/2 keyboard & mouse */
+#define W83627DHG_SPI		6	/* Serial peripheral interface */
+#define W83627DHG_WDTO_PLED	8	/* WDTO#, PLED */
+#define W83627DHG_ACPI		10	/* ACPI */
+#define W83627DHG_HWM		11	/* Hardware monitor */
+#define W83627DHG_PECI_SST	12	/* PECI, SST */
+
+/**
+ * Configure the base I/O port of the specified serial device and enable the
+ * serial device.
+ *
+ * @dev: high 8 bits = super I/O port, low 8 bits = logical device number
+ * @iobase: processor I/O port address to assign to this serial device
+ * @irq: processor IRQ number to assign to this serial device
+ */
+void winbond_enable_serial(uint dev, uint iobase, uint irq);
+
+#endif /* _WINBOND_W83627_H_ */
diff --git a/include/xilinx.h b/include/xilinx.h
new file mode 100644
index 0000000..ab4537b
--- /dev/null
+++ b/include/xilinx.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ */
+
+#include <fpga.h>
+
+#ifndef _XILINX_H_
+#define _XILINX_H_
+
+/* Xilinx types
+ *********************************************************************/
+typedef enum {			/* typedef xilinx_iface */
+	min_xilinx_iface_type,	/* low range check value */
+	slave_serial,		/* serial data and external clock */
+	master_serial,		/* serial data w/ internal clock (not used) */
+	slave_parallel,		/* parallel data w/ external latch */
+	jtag_mode,		/* jtag/tap serial (not used ) */
+	master_selectmap,	/* master SelectMap (virtex2)           */
+	slave_selectmap,	/* slave SelectMap (virtex2)            */
+	devcfg,			/* devcfg interface (zynq) */
+	csu_dma,		/* csu_dma interface (zynqmp) */
+	cfi,			/* CFI interface(versal) */
+	max_xilinx_iface_type	/* insert all new types before this */
+} xilinx_iface;			/* end, typedef xilinx_iface */
+
+typedef enum {			/* typedef xilinx_family */
+	min_xilinx_type,	/* low range check value */
+	xilinx_spartan2,	/* Spartan-II Family */
+	xilinx_virtexE,		/* Virtex-E Family */
+	xilinx_virtex2,		/* Virtex2 Family */
+	xilinx_spartan3,	/* Spartan-III Family */
+	xilinx_zynq,		/* Zynq Family */
+	xilinx_zynqmp,		/* ZynqMP Family */
+	xilinx_versal,		/* Versal Family */
+	max_xilinx_type		/* insert all new types before this */
+} xilinx_family;		/* end, typedef xilinx_family */
+
+typedef struct {		/* typedef xilinx_desc */
+	xilinx_family family;	/* part type */
+	xilinx_iface iface;	/* interface type */
+	size_t size;		/* bytes of data part can accept */
+	void *iface_fns;	/* interface function table */
+	int cookie;		/* implementation specific cookie */
+	struct xilinx_fpga_op *operations; /* operations */
+	char *name;		/* device name in bitstream */
+} xilinx_desc;			/* end, typedef xilinx_desc */
+
+struct xilinx_fpga_op {
+	int (*load)(xilinx_desc *, const void *, size_t, bitstream_type);
+	int (*loadfs)(xilinx_desc *, const void *, size_t, fpga_fs_info *);
+	int (*loads)(xilinx_desc *desc, const void *buf, size_t bsize,
+		     struct fpga_secure_info *fpga_sec_info);
+	int (*dump)(xilinx_desc *, const void *, size_t);
+	int (*info)(xilinx_desc *);
+};
+
+/* Generic Xilinx Functions
+ *********************************************************************/
+int xilinx_load(xilinx_desc *desc, const void *image, size_t size,
+		bitstream_type bstype);
+int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+int xilinx_info(xilinx_desc *desc);
+int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
+		  fpga_fs_info *fpga_fsinfo);
+int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
+		 struct fpga_secure_info *fpga_sec_info);
+
+/* Board specific implementation specific function types
+ *********************************************************************/
+typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie);
+typedef int (*xilinx_init_fn)(int cookie);
+typedef int (*xilinx_err_fn)(int cookie);
+typedef int (*xilinx_done_fn)(int cookie);
+typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie);
+typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie);
+typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie);
+typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie);
+typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie);
+typedef int (*xilinx_busy_fn)(int cookie);
+typedef int (*xilinx_abort_fn)(int cookie);
+typedef int (*xilinx_pre_fn)(int cookie);
+typedef int (*xilinx_post_fn)(int cookie);
+typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie);
+
+#endif  /* _XILINX_H_ */
diff --git a/include/xyzModem.h b/include/xyzModem.h
new file mode 100644
index 0000000..6fae634
--- /dev/null
+++ b/include/xyzModem.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: eCos-2.0 */
+/*
+ *==========================================================================
+ *
+ *      xyzModem.h
+ *
+ *      RedBoot stream handler for xyzModem protocol
+ *
+ *==========================================================================
+ *#####DESCRIPTIONBEGIN####
+ *
+ * Author(s):    gthomas
+ * Contributors: gthomas
+ * Date:         2000-07-14
+ * Purpose:
+ * Description:
+ *
+ * This code is part of RedBoot (tm).
+ *
+ *####DESCRIPTIONEND####
+ *
+ *==========================================================================
+ */
+
+#ifndef _XYZMODEM_H_
+#define _XYZMODEM_H_
+
+#define xyzModem_xmodem 1
+#define xyzModem_ymodem 2
+/* Don't define this until the protocol support is in place */
+/*#define xyzModem_zmodem 3 */
+
+#define xyzModem_access   -1
+#define xyzModem_noZmodem -2
+#define xyzModem_timeout  -3
+#define xyzModem_eof      -4
+#define xyzModem_cancel   -5
+#define xyzModem_frame    -6
+#define xyzModem_cksum    -7
+#define xyzModem_sequence -8
+
+#define xyzModem_close 1
+#define xyzModem_abort 2
+
+
+#define CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT
+#define CYGACC_CALL_IF_SET_CONSOLE_COMM(x)
+
+#define diag_vprintf vprintf
+#define diag_printf printf
+#define diag_vsprintf vsprintf
+
+#define CYGACC_CALL_IF_DELAY_US(x) udelay(x)
+
+typedef struct {
+    char *filename;
+    int   mode;
+    int   chan;
+} connection_info_t;
+
+
+
+int   xyzModem_stream_open(connection_info_t *info, int *err);
+void  xyzModem_stream_close(int *err);
+void  xyzModem_stream_terminate(bool method, int (*getc)(void));
+int   xyzModem_stream_read(char *buf, int size, int *err);
+char *xyzModem_error(int err);
+
+#endif /* _XYZMODEM_H_ */